1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 #ifndef MLX5_IFC_H 33 #define MLX5_IFC_H 34 35 #include "mlx5_ifc_fpga.h" 36 37 enum { 38 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0, 39 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1, 40 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2, 41 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3, 42 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13, 43 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14, 44 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c, 45 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d, 46 MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4, 47 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5, 48 MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED = 0x7, 49 MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT = 0xc, 50 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10, 51 MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR = 0x11, 52 MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR = 0x12, 53 MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR = 0x8, 54 MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE = 0x9, 55 MLX5_EVENT_TYPE_CODING_GPIO_EVENT = 0x15, 56 MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19, 57 MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a, 58 MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT = 0x1b, 59 MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT = 0x1f, 60 MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa, 61 MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb, 62 MLX5_EVENT_TYPE_CODING_FPGA_ERROR = 0x20, 63 MLX5_EVENT_TYPE_CODING_FPGA_QP_ERROR = 0x21 64 }; 65 66 enum { 67 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0, 68 MLX5_SET_HCA_CAP_OP_MOD_ETHERNET_OFFLOADS = 0x1, 69 MLX5_SET_HCA_CAP_OP_MOD_ODP = 0x2, 70 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3, 71 MLX5_SET_HCA_CAP_OP_MOD_ROCE = 0x4, 72 MLX5_SET_HCA_CAP_OP_MOD_IPSEC = 0x15, 73 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE2 = 0x20, 74 MLX5_SET_HCA_CAP_OP_MOD_PORT_SELECTION = 0x25, 75 }; 76 77 enum { 78 MLX5_SHARED_RESOURCE_UID = 0xffff, 79 }; 80 81 enum { 82 MLX5_OBJ_TYPE_SW_ICM = 0x0008, 83 MLX5_OBJ_TYPE_HEADER_MODIFY_ARGUMENT = 0x23, 84 }; 85 86 enum { 87 MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM = (1ULL << MLX5_OBJ_TYPE_SW_ICM), 88 MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT = (1ULL << 11), 89 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q = (1ULL << 13), 90 MLX5_GENERAL_OBJ_TYPES_CAP_HEADER_MODIFY_ARGUMENT = 91 (1ULL << MLX5_OBJ_TYPE_HEADER_MODIFY_ARGUMENT), 92 MLX5_GENERAL_OBJ_TYPES_CAP_MACSEC_OFFLOAD = (1ULL << 39), 93 }; 94 95 enum { 96 MLX5_OBJ_TYPE_GENEVE_TLV_OPT = 0x000b, 97 MLX5_OBJ_TYPE_VIRTIO_NET_Q = 0x000d, 98 MLX5_OBJ_TYPE_VIRTIO_Q_COUNTERS = 0x001c, 99 MLX5_OBJ_TYPE_MATCH_DEFINER = 0x0018, 100 MLX5_OBJ_TYPE_PAGE_TRACK = 0x46, 101 MLX5_OBJ_TYPE_MKEY = 0xff01, 102 MLX5_OBJ_TYPE_QP = 0xff02, 103 MLX5_OBJ_TYPE_PSV = 0xff03, 104 MLX5_OBJ_TYPE_RMP = 0xff04, 105 MLX5_OBJ_TYPE_XRC_SRQ = 0xff05, 106 MLX5_OBJ_TYPE_RQ = 0xff06, 107 MLX5_OBJ_TYPE_SQ = 0xff07, 108 MLX5_OBJ_TYPE_TIR = 0xff08, 109 MLX5_OBJ_TYPE_TIS = 0xff09, 110 MLX5_OBJ_TYPE_DCT = 0xff0a, 111 MLX5_OBJ_TYPE_XRQ = 0xff0b, 112 MLX5_OBJ_TYPE_RQT = 0xff0e, 113 MLX5_OBJ_TYPE_FLOW_COUNTER = 0xff0f, 114 MLX5_OBJ_TYPE_CQ = 0xff10, 115 }; 116 117 enum { 118 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100, 119 MLX5_CMD_OP_QUERY_ADAPTER = 0x101, 120 MLX5_CMD_OP_INIT_HCA = 0x102, 121 MLX5_CMD_OP_TEARDOWN_HCA = 0x103, 122 MLX5_CMD_OP_ENABLE_HCA = 0x104, 123 MLX5_CMD_OP_DISABLE_HCA = 0x105, 124 MLX5_CMD_OP_QUERY_PAGES = 0x107, 125 MLX5_CMD_OP_MANAGE_PAGES = 0x108, 126 MLX5_CMD_OP_SET_HCA_CAP = 0x109, 127 MLX5_CMD_OP_QUERY_ISSI = 0x10a, 128 MLX5_CMD_OP_SET_ISSI = 0x10b, 129 MLX5_CMD_OP_SET_DRIVER_VERSION = 0x10d, 130 MLX5_CMD_OP_QUERY_SF_PARTITION = 0x111, 131 MLX5_CMD_OP_ALLOC_SF = 0x113, 132 MLX5_CMD_OP_DEALLOC_SF = 0x114, 133 MLX5_CMD_OP_SUSPEND_VHCA = 0x115, 134 MLX5_CMD_OP_RESUME_VHCA = 0x116, 135 MLX5_CMD_OP_QUERY_VHCA_MIGRATION_STATE = 0x117, 136 MLX5_CMD_OP_SAVE_VHCA_STATE = 0x118, 137 MLX5_CMD_OP_LOAD_VHCA_STATE = 0x119, 138 MLX5_CMD_OP_CREATE_MKEY = 0x200, 139 MLX5_CMD_OP_QUERY_MKEY = 0x201, 140 MLX5_CMD_OP_DESTROY_MKEY = 0x202, 141 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203, 142 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204, 143 MLX5_CMD_OP_ALLOC_MEMIC = 0x205, 144 MLX5_CMD_OP_DEALLOC_MEMIC = 0x206, 145 MLX5_CMD_OP_MODIFY_MEMIC = 0x207, 146 MLX5_CMD_OP_CREATE_EQ = 0x301, 147 MLX5_CMD_OP_DESTROY_EQ = 0x302, 148 MLX5_CMD_OP_QUERY_EQ = 0x303, 149 MLX5_CMD_OP_GEN_EQE = 0x304, 150 MLX5_CMD_OP_CREATE_CQ = 0x400, 151 MLX5_CMD_OP_DESTROY_CQ = 0x401, 152 MLX5_CMD_OP_QUERY_CQ = 0x402, 153 MLX5_CMD_OP_MODIFY_CQ = 0x403, 154 MLX5_CMD_OP_CREATE_QP = 0x500, 155 MLX5_CMD_OP_DESTROY_QP = 0x501, 156 MLX5_CMD_OP_RST2INIT_QP = 0x502, 157 MLX5_CMD_OP_INIT2RTR_QP = 0x503, 158 MLX5_CMD_OP_RTR2RTS_QP = 0x504, 159 MLX5_CMD_OP_RTS2RTS_QP = 0x505, 160 MLX5_CMD_OP_SQERR2RTS_QP = 0x506, 161 MLX5_CMD_OP_2ERR_QP = 0x507, 162 MLX5_CMD_OP_2RST_QP = 0x50a, 163 MLX5_CMD_OP_QUERY_QP = 0x50b, 164 MLX5_CMD_OP_SQD_RTS_QP = 0x50c, 165 MLX5_CMD_OP_INIT2INIT_QP = 0x50e, 166 MLX5_CMD_OP_CREATE_PSV = 0x600, 167 MLX5_CMD_OP_DESTROY_PSV = 0x601, 168 MLX5_CMD_OP_CREATE_SRQ = 0x700, 169 MLX5_CMD_OP_DESTROY_SRQ = 0x701, 170 MLX5_CMD_OP_QUERY_SRQ = 0x702, 171 MLX5_CMD_OP_ARM_RQ = 0x703, 172 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705, 173 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706, 174 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707, 175 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708, 176 MLX5_CMD_OP_CREATE_DCT = 0x710, 177 MLX5_CMD_OP_DESTROY_DCT = 0x711, 178 MLX5_CMD_OP_DRAIN_DCT = 0x712, 179 MLX5_CMD_OP_QUERY_DCT = 0x713, 180 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714, 181 MLX5_CMD_OP_CREATE_XRQ = 0x717, 182 MLX5_CMD_OP_DESTROY_XRQ = 0x718, 183 MLX5_CMD_OP_QUERY_XRQ = 0x719, 184 MLX5_CMD_OP_ARM_XRQ = 0x71a, 185 MLX5_CMD_OP_QUERY_XRQ_DC_PARAMS_ENTRY = 0x725, 186 MLX5_CMD_OP_SET_XRQ_DC_PARAMS_ENTRY = 0x726, 187 MLX5_CMD_OP_QUERY_XRQ_ERROR_PARAMS = 0x727, 188 MLX5_CMD_OP_RELEASE_XRQ_ERROR = 0x729, 189 MLX5_CMD_OP_MODIFY_XRQ = 0x72a, 190 MLX5_CMD_OP_QUERY_ESW_FUNCTIONS = 0x740, 191 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750, 192 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751, 193 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752, 194 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753, 195 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754, 196 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755, 197 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760, 198 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761, 199 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762, 200 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763, 201 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764, 202 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765, 203 MLX5_CMD_OP_QUERY_VNIC_ENV = 0x76f, 204 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770, 205 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771, 206 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772, 207 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773, 208 MLX5_CMD_OP_SET_MONITOR_COUNTER = 0x774, 209 MLX5_CMD_OP_ARM_MONITOR_COUNTER = 0x775, 210 MLX5_CMD_OP_SET_PP_RATE_LIMIT = 0x780, 211 MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781, 212 MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT = 0x782, 213 MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT = 0x783, 214 MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT = 0x784, 215 MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT = 0x785, 216 MLX5_CMD_OP_CREATE_QOS_PARA_VPORT = 0x786, 217 MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT = 0x787, 218 MLX5_CMD_OP_ALLOC_PD = 0x800, 219 MLX5_CMD_OP_DEALLOC_PD = 0x801, 220 MLX5_CMD_OP_ALLOC_UAR = 0x802, 221 MLX5_CMD_OP_DEALLOC_UAR = 0x803, 222 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804, 223 MLX5_CMD_OP_ACCESS_REG = 0x805, 224 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806, 225 MLX5_CMD_OP_DETACH_FROM_MCG = 0x807, 226 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a, 227 MLX5_CMD_OP_MAD_IFC = 0x50d, 228 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b, 229 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c, 230 MLX5_CMD_OP_NOP = 0x80d, 231 MLX5_CMD_OP_ALLOC_XRCD = 0x80e, 232 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f, 233 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816, 234 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817, 235 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822, 236 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823, 237 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824, 238 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825, 239 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826, 240 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827, 241 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828, 242 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829, 243 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a, 244 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b, 245 MLX5_CMD_OP_SET_WOL_ROL = 0x830, 246 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831, 247 MLX5_CMD_OP_CREATE_LAG = 0x840, 248 MLX5_CMD_OP_MODIFY_LAG = 0x841, 249 MLX5_CMD_OP_QUERY_LAG = 0x842, 250 MLX5_CMD_OP_DESTROY_LAG = 0x843, 251 MLX5_CMD_OP_CREATE_VPORT_LAG = 0x844, 252 MLX5_CMD_OP_DESTROY_VPORT_LAG = 0x845, 253 MLX5_CMD_OP_CREATE_TIR = 0x900, 254 MLX5_CMD_OP_MODIFY_TIR = 0x901, 255 MLX5_CMD_OP_DESTROY_TIR = 0x902, 256 MLX5_CMD_OP_QUERY_TIR = 0x903, 257 MLX5_CMD_OP_CREATE_SQ = 0x904, 258 MLX5_CMD_OP_MODIFY_SQ = 0x905, 259 MLX5_CMD_OP_DESTROY_SQ = 0x906, 260 MLX5_CMD_OP_QUERY_SQ = 0x907, 261 MLX5_CMD_OP_CREATE_RQ = 0x908, 262 MLX5_CMD_OP_MODIFY_RQ = 0x909, 263 MLX5_CMD_OP_SET_DELAY_DROP_PARAMS = 0x910, 264 MLX5_CMD_OP_DESTROY_RQ = 0x90a, 265 MLX5_CMD_OP_QUERY_RQ = 0x90b, 266 MLX5_CMD_OP_CREATE_RMP = 0x90c, 267 MLX5_CMD_OP_MODIFY_RMP = 0x90d, 268 MLX5_CMD_OP_DESTROY_RMP = 0x90e, 269 MLX5_CMD_OP_QUERY_RMP = 0x90f, 270 MLX5_CMD_OP_CREATE_TIS = 0x912, 271 MLX5_CMD_OP_MODIFY_TIS = 0x913, 272 MLX5_CMD_OP_DESTROY_TIS = 0x914, 273 MLX5_CMD_OP_QUERY_TIS = 0x915, 274 MLX5_CMD_OP_CREATE_RQT = 0x916, 275 MLX5_CMD_OP_MODIFY_RQT = 0x917, 276 MLX5_CMD_OP_DESTROY_RQT = 0x918, 277 MLX5_CMD_OP_QUERY_RQT = 0x919, 278 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f, 279 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930, 280 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931, 281 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932, 282 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933, 283 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934, 284 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935, 285 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936, 286 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937, 287 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938, 288 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939, 289 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a, 290 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b, 291 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c, 292 MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT = 0x93d, 293 MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT = 0x93e, 294 MLX5_CMD_OP_QUERY_PACKET_REFORMAT_CONTEXT = 0x93f, 295 MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT = 0x940, 296 MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941, 297 MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT = 0x942, 298 MLX5_CMD_OP_FPGA_CREATE_QP = 0x960, 299 MLX5_CMD_OP_FPGA_MODIFY_QP = 0x961, 300 MLX5_CMD_OP_FPGA_QUERY_QP = 0x962, 301 MLX5_CMD_OP_FPGA_DESTROY_QP = 0x963, 302 MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS = 0x964, 303 MLX5_CMD_OP_CREATE_GENERAL_OBJECT = 0xa00, 304 MLX5_CMD_OP_MODIFY_GENERAL_OBJECT = 0xa01, 305 MLX5_CMD_OP_QUERY_GENERAL_OBJECT = 0xa02, 306 MLX5_CMD_OP_DESTROY_GENERAL_OBJECT = 0xa03, 307 MLX5_CMD_OP_CREATE_UCTX = 0xa04, 308 MLX5_CMD_OP_DESTROY_UCTX = 0xa06, 309 MLX5_CMD_OP_CREATE_UMEM = 0xa08, 310 MLX5_CMD_OP_DESTROY_UMEM = 0xa0a, 311 MLX5_CMD_OP_SYNC_STEERING = 0xb00, 312 MLX5_CMD_OP_QUERY_VHCA_STATE = 0xb0d, 313 MLX5_CMD_OP_MODIFY_VHCA_STATE = 0xb0e, 314 MLX5_CMD_OP_SYNC_CRYPTO = 0xb12, 315 MLX5_CMD_OP_ALLOW_OTHER_VHCA_ACCESS = 0xb16, 316 MLX5_CMD_OP_MAX 317 }; 318 319 /* Valid range for general commands that don't work over an object */ 320 enum { 321 MLX5_CMD_OP_GENERAL_START = 0xb00, 322 MLX5_CMD_OP_GENERAL_END = 0xd00, 323 }; 324 325 enum { 326 MLX5_FT_NIC_RX_2_NIC_RX_RDMA = BIT(0), 327 MLX5_FT_NIC_TX_RDMA_2_NIC_TX = BIT(1), 328 }; 329 330 enum { 331 MLX5_CMD_OP_MOD_UPDATE_HEADER_MODIFY_ARGUMENT = 0x1, 332 }; 333 334 struct mlx5_ifc_flow_table_fields_supported_bits { 335 u8 outer_dmac[0x1]; 336 u8 outer_smac[0x1]; 337 u8 outer_ether_type[0x1]; 338 u8 outer_ip_version[0x1]; 339 u8 outer_first_prio[0x1]; 340 u8 outer_first_cfi[0x1]; 341 u8 outer_first_vid[0x1]; 342 u8 outer_ipv4_ttl[0x1]; 343 u8 outer_second_prio[0x1]; 344 u8 outer_second_cfi[0x1]; 345 u8 outer_second_vid[0x1]; 346 u8 reserved_at_b[0x1]; 347 u8 outer_sip[0x1]; 348 u8 outer_dip[0x1]; 349 u8 outer_frag[0x1]; 350 u8 outer_ip_protocol[0x1]; 351 u8 outer_ip_ecn[0x1]; 352 u8 outer_ip_dscp[0x1]; 353 u8 outer_udp_sport[0x1]; 354 u8 outer_udp_dport[0x1]; 355 u8 outer_tcp_sport[0x1]; 356 u8 outer_tcp_dport[0x1]; 357 u8 outer_tcp_flags[0x1]; 358 u8 outer_gre_protocol[0x1]; 359 u8 outer_gre_key[0x1]; 360 u8 outer_vxlan_vni[0x1]; 361 u8 outer_geneve_vni[0x1]; 362 u8 outer_geneve_oam[0x1]; 363 u8 outer_geneve_protocol_type[0x1]; 364 u8 outer_geneve_opt_len[0x1]; 365 u8 source_vhca_port[0x1]; 366 u8 source_eswitch_port[0x1]; 367 368 u8 inner_dmac[0x1]; 369 u8 inner_smac[0x1]; 370 u8 inner_ether_type[0x1]; 371 u8 inner_ip_version[0x1]; 372 u8 inner_first_prio[0x1]; 373 u8 inner_first_cfi[0x1]; 374 u8 inner_first_vid[0x1]; 375 u8 reserved_at_27[0x1]; 376 u8 inner_second_prio[0x1]; 377 u8 inner_second_cfi[0x1]; 378 u8 inner_second_vid[0x1]; 379 u8 reserved_at_2b[0x1]; 380 u8 inner_sip[0x1]; 381 u8 inner_dip[0x1]; 382 u8 inner_frag[0x1]; 383 u8 inner_ip_protocol[0x1]; 384 u8 inner_ip_ecn[0x1]; 385 u8 inner_ip_dscp[0x1]; 386 u8 inner_udp_sport[0x1]; 387 u8 inner_udp_dport[0x1]; 388 u8 inner_tcp_sport[0x1]; 389 u8 inner_tcp_dport[0x1]; 390 u8 inner_tcp_flags[0x1]; 391 u8 reserved_at_37[0x9]; 392 393 u8 geneve_tlv_option_0_data[0x1]; 394 u8 geneve_tlv_option_0_exist[0x1]; 395 u8 reserved_at_42[0x3]; 396 u8 outer_first_mpls_over_udp[0x4]; 397 u8 outer_first_mpls_over_gre[0x4]; 398 u8 inner_first_mpls[0x4]; 399 u8 outer_first_mpls[0x4]; 400 u8 reserved_at_55[0x2]; 401 u8 outer_esp_spi[0x1]; 402 u8 reserved_at_58[0x2]; 403 u8 bth_dst_qp[0x1]; 404 u8 reserved_at_5b[0x5]; 405 406 u8 reserved_at_60[0x18]; 407 u8 metadata_reg_c_7[0x1]; 408 u8 metadata_reg_c_6[0x1]; 409 u8 metadata_reg_c_5[0x1]; 410 u8 metadata_reg_c_4[0x1]; 411 u8 metadata_reg_c_3[0x1]; 412 u8 metadata_reg_c_2[0x1]; 413 u8 metadata_reg_c_1[0x1]; 414 u8 metadata_reg_c_0[0x1]; 415 }; 416 417 /* Table 2170 - Flow Table Fields Supported 2 Format */ 418 struct mlx5_ifc_flow_table_fields_supported_2_bits { 419 u8 reserved_at_0[0x2]; 420 u8 inner_l4_type[0x1]; 421 u8 outer_l4_type[0x1]; 422 u8 reserved_at_4[0xa]; 423 u8 bth_opcode[0x1]; 424 u8 reserved_at_f[0x1]; 425 u8 tunnel_header_0_1[0x1]; 426 u8 reserved_at_11[0xf]; 427 428 u8 reserved_at_20[0x60]; 429 }; 430 431 struct mlx5_ifc_flow_table_prop_layout_bits { 432 u8 ft_support[0x1]; 433 u8 reserved_at_1[0x1]; 434 u8 flow_counter[0x1]; 435 u8 flow_modify_en[0x1]; 436 u8 modify_root[0x1]; 437 u8 identified_miss_table_mode[0x1]; 438 u8 flow_table_modify[0x1]; 439 u8 reformat[0x1]; 440 u8 decap[0x1]; 441 u8 reset_root_to_default[0x1]; 442 u8 pop_vlan[0x1]; 443 u8 push_vlan[0x1]; 444 u8 reserved_at_c[0x1]; 445 u8 pop_vlan_2[0x1]; 446 u8 push_vlan_2[0x1]; 447 u8 reformat_and_vlan_action[0x1]; 448 u8 reserved_at_10[0x1]; 449 u8 sw_owner[0x1]; 450 u8 reformat_l3_tunnel_to_l2[0x1]; 451 u8 reformat_l2_to_l3_tunnel[0x1]; 452 u8 reformat_and_modify_action[0x1]; 453 u8 ignore_flow_level[0x1]; 454 u8 reserved_at_16[0x1]; 455 u8 table_miss_action_domain[0x1]; 456 u8 termination_table[0x1]; 457 u8 reformat_and_fwd_to_table[0x1]; 458 u8 reserved_at_1a[0x2]; 459 u8 ipsec_encrypt[0x1]; 460 u8 ipsec_decrypt[0x1]; 461 u8 sw_owner_v2[0x1]; 462 u8 reserved_at_1f[0x1]; 463 464 u8 termination_table_raw_traffic[0x1]; 465 u8 reserved_at_21[0x1]; 466 u8 log_max_ft_size[0x6]; 467 u8 log_max_modify_header_context[0x8]; 468 u8 max_modify_header_actions[0x8]; 469 u8 max_ft_level[0x8]; 470 471 u8 reformat_add_esp_trasport[0x1]; 472 u8 reformat_l2_to_l3_esp_tunnel[0x1]; 473 u8 reformat_add_esp_transport_over_udp[0x1]; 474 u8 reformat_del_esp_trasport[0x1]; 475 u8 reformat_l3_esp_tunnel_to_l2[0x1]; 476 u8 reformat_del_esp_transport_over_udp[0x1]; 477 u8 execute_aso[0x1]; 478 u8 reserved_at_47[0x19]; 479 480 u8 reserved_at_60[0x2]; 481 u8 reformat_insert[0x1]; 482 u8 reformat_remove[0x1]; 483 u8 macsec_encrypt[0x1]; 484 u8 macsec_decrypt[0x1]; 485 u8 reserved_at_66[0x2]; 486 u8 reformat_add_macsec[0x1]; 487 u8 reformat_remove_macsec[0x1]; 488 u8 reserved_at_6a[0xe]; 489 u8 log_max_ft_num[0x8]; 490 491 u8 reserved_at_80[0x10]; 492 u8 log_max_flow_counter[0x8]; 493 u8 log_max_destination[0x8]; 494 495 u8 reserved_at_a0[0x18]; 496 u8 log_max_flow[0x8]; 497 498 u8 reserved_at_c0[0x40]; 499 500 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support; 501 502 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support; 503 }; 504 505 struct mlx5_ifc_odp_per_transport_service_cap_bits { 506 u8 send[0x1]; 507 u8 receive[0x1]; 508 u8 write[0x1]; 509 u8 read[0x1]; 510 u8 atomic[0x1]; 511 u8 srq_receive[0x1]; 512 u8 reserved_at_6[0x1a]; 513 }; 514 515 struct mlx5_ifc_ipv4_layout_bits { 516 u8 reserved_at_0[0x60]; 517 518 u8 ipv4[0x20]; 519 }; 520 521 struct mlx5_ifc_ipv6_layout_bits { 522 u8 ipv6[16][0x8]; 523 }; 524 525 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits { 526 struct mlx5_ifc_ipv6_layout_bits ipv6_layout; 527 struct mlx5_ifc_ipv4_layout_bits ipv4_layout; 528 u8 reserved_at_0[0x80]; 529 }; 530 531 enum { 532 MLX5_PACKET_L4_TYPE_NONE, 533 MLX5_PACKET_L4_TYPE_TCP, 534 MLX5_PACKET_L4_TYPE_UDP, 535 }; 536 537 struct mlx5_ifc_fte_match_set_lyr_2_4_bits { 538 u8 smac_47_16[0x20]; 539 540 u8 smac_15_0[0x10]; 541 u8 ethertype[0x10]; 542 543 u8 dmac_47_16[0x20]; 544 545 u8 dmac_15_0[0x10]; 546 u8 first_prio[0x3]; 547 u8 first_cfi[0x1]; 548 u8 first_vid[0xc]; 549 550 u8 ip_protocol[0x8]; 551 u8 ip_dscp[0x6]; 552 u8 ip_ecn[0x2]; 553 u8 cvlan_tag[0x1]; 554 u8 svlan_tag[0x1]; 555 u8 frag[0x1]; 556 u8 ip_version[0x4]; 557 u8 tcp_flags[0x9]; 558 559 u8 tcp_sport[0x10]; 560 u8 tcp_dport[0x10]; 561 562 u8 l4_type[0x2]; 563 u8 reserved_at_c2[0xe]; 564 u8 ipv4_ihl[0x4]; 565 u8 reserved_at_c4[0x4]; 566 567 u8 ttl_hoplimit[0x8]; 568 569 u8 udp_sport[0x10]; 570 u8 udp_dport[0x10]; 571 572 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6; 573 574 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6; 575 }; 576 577 struct mlx5_ifc_nvgre_key_bits { 578 u8 hi[0x18]; 579 u8 lo[0x8]; 580 }; 581 582 union mlx5_ifc_gre_key_bits { 583 struct mlx5_ifc_nvgre_key_bits nvgre; 584 u8 key[0x20]; 585 }; 586 587 struct mlx5_ifc_fte_match_set_misc_bits { 588 u8 gre_c_present[0x1]; 589 u8 reserved_at_1[0x1]; 590 u8 gre_k_present[0x1]; 591 u8 gre_s_present[0x1]; 592 u8 source_vhca_port[0x4]; 593 u8 source_sqn[0x18]; 594 595 u8 source_eswitch_owner_vhca_id[0x10]; 596 u8 source_port[0x10]; 597 598 u8 outer_second_prio[0x3]; 599 u8 outer_second_cfi[0x1]; 600 u8 outer_second_vid[0xc]; 601 u8 inner_second_prio[0x3]; 602 u8 inner_second_cfi[0x1]; 603 u8 inner_second_vid[0xc]; 604 605 u8 outer_second_cvlan_tag[0x1]; 606 u8 inner_second_cvlan_tag[0x1]; 607 u8 outer_second_svlan_tag[0x1]; 608 u8 inner_second_svlan_tag[0x1]; 609 u8 reserved_at_64[0xc]; 610 u8 gre_protocol[0x10]; 611 612 union mlx5_ifc_gre_key_bits gre_key; 613 614 u8 vxlan_vni[0x18]; 615 u8 bth_opcode[0x8]; 616 617 u8 geneve_vni[0x18]; 618 u8 reserved_at_d8[0x6]; 619 u8 geneve_tlv_option_0_exist[0x1]; 620 u8 geneve_oam[0x1]; 621 622 u8 reserved_at_e0[0xc]; 623 u8 outer_ipv6_flow_label[0x14]; 624 625 u8 reserved_at_100[0xc]; 626 u8 inner_ipv6_flow_label[0x14]; 627 628 u8 reserved_at_120[0xa]; 629 u8 geneve_opt_len[0x6]; 630 u8 geneve_protocol_type[0x10]; 631 632 u8 reserved_at_140[0x8]; 633 u8 bth_dst_qp[0x18]; 634 u8 inner_esp_spi[0x20]; 635 u8 outer_esp_spi[0x20]; 636 u8 reserved_at_1a0[0x60]; 637 }; 638 639 struct mlx5_ifc_fte_match_mpls_bits { 640 u8 mpls_label[0x14]; 641 u8 mpls_exp[0x3]; 642 u8 mpls_s_bos[0x1]; 643 u8 mpls_ttl[0x8]; 644 }; 645 646 struct mlx5_ifc_fte_match_set_misc2_bits { 647 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls; 648 649 struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls; 650 651 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre; 652 653 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp; 654 655 u8 metadata_reg_c_7[0x20]; 656 657 u8 metadata_reg_c_6[0x20]; 658 659 u8 metadata_reg_c_5[0x20]; 660 661 u8 metadata_reg_c_4[0x20]; 662 663 u8 metadata_reg_c_3[0x20]; 664 665 u8 metadata_reg_c_2[0x20]; 666 667 u8 metadata_reg_c_1[0x20]; 668 669 u8 metadata_reg_c_0[0x20]; 670 671 u8 metadata_reg_a[0x20]; 672 673 u8 reserved_at_1a0[0x8]; 674 675 u8 macsec_syndrome[0x8]; 676 u8 ipsec_syndrome[0x8]; 677 u8 reserved_at_1b8[0x8]; 678 679 u8 reserved_at_1c0[0x40]; 680 }; 681 682 struct mlx5_ifc_fte_match_set_misc3_bits { 683 u8 inner_tcp_seq_num[0x20]; 684 685 u8 outer_tcp_seq_num[0x20]; 686 687 u8 inner_tcp_ack_num[0x20]; 688 689 u8 outer_tcp_ack_num[0x20]; 690 691 u8 reserved_at_80[0x8]; 692 u8 outer_vxlan_gpe_vni[0x18]; 693 694 u8 outer_vxlan_gpe_next_protocol[0x8]; 695 u8 outer_vxlan_gpe_flags[0x8]; 696 u8 reserved_at_b0[0x10]; 697 698 u8 icmp_header_data[0x20]; 699 700 u8 icmpv6_header_data[0x20]; 701 702 u8 icmp_type[0x8]; 703 u8 icmp_code[0x8]; 704 u8 icmpv6_type[0x8]; 705 u8 icmpv6_code[0x8]; 706 707 u8 geneve_tlv_option_0_data[0x20]; 708 709 u8 gtpu_teid[0x20]; 710 711 u8 gtpu_msg_type[0x8]; 712 u8 gtpu_msg_flags[0x8]; 713 u8 reserved_at_170[0x10]; 714 715 u8 gtpu_dw_2[0x20]; 716 717 u8 gtpu_first_ext_dw_0[0x20]; 718 719 u8 gtpu_dw_0[0x20]; 720 721 u8 reserved_at_1e0[0x20]; 722 }; 723 724 struct mlx5_ifc_fte_match_set_misc4_bits { 725 u8 prog_sample_field_value_0[0x20]; 726 727 u8 prog_sample_field_id_0[0x20]; 728 729 u8 prog_sample_field_value_1[0x20]; 730 731 u8 prog_sample_field_id_1[0x20]; 732 733 u8 prog_sample_field_value_2[0x20]; 734 735 u8 prog_sample_field_id_2[0x20]; 736 737 u8 prog_sample_field_value_3[0x20]; 738 739 u8 prog_sample_field_id_3[0x20]; 740 741 u8 reserved_at_100[0x100]; 742 }; 743 744 struct mlx5_ifc_fte_match_set_misc5_bits { 745 u8 macsec_tag_0[0x20]; 746 747 u8 macsec_tag_1[0x20]; 748 749 u8 macsec_tag_2[0x20]; 750 751 u8 macsec_tag_3[0x20]; 752 753 u8 tunnel_header_0[0x20]; 754 755 u8 tunnel_header_1[0x20]; 756 757 u8 tunnel_header_2[0x20]; 758 759 u8 tunnel_header_3[0x20]; 760 761 u8 reserved_at_100[0x100]; 762 }; 763 764 struct mlx5_ifc_cmd_pas_bits { 765 u8 pa_h[0x20]; 766 767 u8 pa_l[0x14]; 768 u8 reserved_at_34[0xc]; 769 }; 770 771 struct mlx5_ifc_uint64_bits { 772 u8 hi[0x20]; 773 774 u8 lo[0x20]; 775 }; 776 777 enum { 778 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0, 779 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7, 780 MLX5_ADS_STAT_RATE_10GBPS = 0x8, 781 MLX5_ADS_STAT_RATE_30GBPS = 0x9, 782 MLX5_ADS_STAT_RATE_5GBPS = 0xa, 783 MLX5_ADS_STAT_RATE_20GBPS = 0xb, 784 MLX5_ADS_STAT_RATE_40GBPS = 0xc, 785 MLX5_ADS_STAT_RATE_60GBPS = 0xd, 786 MLX5_ADS_STAT_RATE_80GBPS = 0xe, 787 MLX5_ADS_STAT_RATE_120GBPS = 0xf, 788 }; 789 790 struct mlx5_ifc_ads_bits { 791 u8 fl[0x1]; 792 u8 free_ar[0x1]; 793 u8 reserved_at_2[0xe]; 794 u8 pkey_index[0x10]; 795 796 u8 plane_index[0x8]; 797 u8 grh[0x1]; 798 u8 mlid[0x7]; 799 u8 rlid[0x10]; 800 801 u8 ack_timeout[0x5]; 802 u8 reserved_at_45[0x3]; 803 u8 src_addr_index[0x8]; 804 u8 reserved_at_50[0x4]; 805 u8 stat_rate[0x4]; 806 u8 hop_limit[0x8]; 807 808 u8 reserved_at_60[0x4]; 809 u8 tclass[0x8]; 810 u8 flow_label[0x14]; 811 812 u8 rgid_rip[16][0x8]; 813 814 u8 reserved_at_100[0x4]; 815 u8 f_dscp[0x1]; 816 u8 f_ecn[0x1]; 817 u8 reserved_at_106[0x1]; 818 u8 f_eth_prio[0x1]; 819 u8 ecn[0x2]; 820 u8 dscp[0x6]; 821 u8 udp_sport[0x10]; 822 823 u8 dei_cfi[0x1]; 824 u8 eth_prio[0x3]; 825 u8 sl[0x4]; 826 u8 vhca_port_num[0x8]; 827 u8 rmac_47_32[0x10]; 828 829 u8 rmac_31_0[0x20]; 830 }; 831 832 struct mlx5_ifc_flow_table_nic_cap_bits { 833 u8 nic_rx_multi_path_tirs[0x1]; 834 u8 nic_rx_multi_path_tirs_fts[0x1]; 835 u8 allow_sniffer_and_nic_rx_shared_tir[0x1]; 836 u8 reserved_at_3[0x4]; 837 u8 sw_owner_reformat_supported[0x1]; 838 u8 reserved_at_8[0x18]; 839 840 u8 encap_general_header[0x1]; 841 u8 reserved_at_21[0xa]; 842 u8 log_max_packet_reformat_context[0x5]; 843 u8 reserved_at_30[0x6]; 844 u8 max_encap_header_size[0xa]; 845 u8 reserved_at_40[0x1c0]; 846 847 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive; 848 849 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_rdma; 850 851 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer; 852 853 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit; 854 855 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_rdma; 856 857 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer; 858 859 u8 reserved_at_e00[0x600]; 860 861 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_receive; 862 863 u8 reserved_at_1480[0x80]; 864 865 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_receive_rdma; 866 867 u8 reserved_at_1580[0x280]; 868 869 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_transmit_rdma; 870 871 u8 reserved_at_1880[0x780]; 872 873 u8 sw_steering_nic_rx_action_drop_icm_address[0x40]; 874 875 u8 sw_steering_nic_tx_action_drop_icm_address[0x40]; 876 877 u8 sw_steering_nic_tx_action_allow_icm_address[0x40]; 878 879 u8 reserved_at_20c0[0x5f40]; 880 }; 881 882 struct mlx5_ifc_port_selection_cap_bits { 883 u8 reserved_at_0[0x10]; 884 u8 port_select_flow_table[0x1]; 885 u8 reserved_at_11[0x1]; 886 u8 port_select_flow_table_bypass[0x1]; 887 u8 reserved_at_13[0xd]; 888 889 u8 reserved_at_20[0x1e0]; 890 891 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_port_selection; 892 893 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_port_selection; 894 895 u8 reserved_at_480[0x7b80]; 896 }; 897 898 enum { 899 MLX5_FDB_TO_VPORT_REG_C_0 = 0x01, 900 MLX5_FDB_TO_VPORT_REG_C_1 = 0x02, 901 MLX5_FDB_TO_VPORT_REG_C_2 = 0x04, 902 MLX5_FDB_TO_VPORT_REG_C_3 = 0x08, 903 MLX5_FDB_TO_VPORT_REG_C_4 = 0x10, 904 MLX5_FDB_TO_VPORT_REG_C_5 = 0x20, 905 MLX5_FDB_TO_VPORT_REG_C_6 = 0x40, 906 MLX5_FDB_TO_VPORT_REG_C_7 = 0x80, 907 }; 908 909 struct mlx5_ifc_flow_table_eswitch_cap_bits { 910 u8 fdb_to_vport_reg_c_id[0x8]; 911 u8 reserved_at_8[0x5]; 912 u8 fdb_uplink_hairpin[0x1]; 913 u8 fdb_multi_path_any_table_limit_regc[0x1]; 914 u8 reserved_at_f[0x3]; 915 u8 fdb_multi_path_any_table[0x1]; 916 u8 reserved_at_13[0x2]; 917 u8 fdb_modify_header_fwd_to_table[0x1]; 918 u8 fdb_ipv4_ttl_modify[0x1]; 919 u8 flow_source[0x1]; 920 u8 reserved_at_18[0x2]; 921 u8 multi_fdb_encap[0x1]; 922 u8 egress_acl_forward_to_vport[0x1]; 923 u8 fdb_multi_path_to_table[0x1]; 924 u8 reserved_at_1d[0x3]; 925 926 u8 reserved_at_20[0x1e0]; 927 928 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb; 929 930 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress; 931 932 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress; 933 934 u8 reserved_at_800[0xC00]; 935 936 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_esw_fdb; 937 938 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_bitmask_support_2_esw_fdb; 939 940 u8 reserved_at_1500[0x300]; 941 942 u8 sw_steering_fdb_action_drop_icm_address_rx[0x40]; 943 944 u8 sw_steering_fdb_action_drop_icm_address_tx[0x40]; 945 946 u8 sw_steering_uplink_icm_address_rx[0x40]; 947 948 u8 sw_steering_uplink_icm_address_tx[0x40]; 949 950 u8 reserved_at_1900[0x6700]; 951 }; 952 953 enum { 954 MLX5_COUNTER_SOURCE_ESWITCH = 0x0, 955 MLX5_COUNTER_FLOW_ESWITCH = 0x1, 956 }; 957 958 struct mlx5_ifc_e_switch_cap_bits { 959 u8 vport_svlan_strip[0x1]; 960 u8 vport_cvlan_strip[0x1]; 961 u8 vport_svlan_insert[0x1]; 962 u8 vport_cvlan_insert_if_not_exist[0x1]; 963 u8 vport_cvlan_insert_overwrite[0x1]; 964 u8 reserved_at_5[0x1]; 965 u8 vport_cvlan_insert_always[0x1]; 966 u8 esw_shared_ingress_acl[0x1]; 967 u8 esw_uplink_ingress_acl[0x1]; 968 u8 root_ft_on_other_esw[0x1]; 969 u8 reserved_at_a[0xf]; 970 u8 esw_functions_changed[0x1]; 971 u8 reserved_at_1a[0x1]; 972 u8 ecpf_vport_exists[0x1]; 973 u8 counter_eswitch_affinity[0x1]; 974 u8 merged_eswitch[0x1]; 975 u8 nic_vport_node_guid_modify[0x1]; 976 u8 nic_vport_port_guid_modify[0x1]; 977 978 u8 vxlan_encap_decap[0x1]; 979 u8 nvgre_encap_decap[0x1]; 980 u8 reserved_at_22[0x1]; 981 u8 log_max_fdb_encap_uplink[0x5]; 982 u8 reserved_at_21[0x3]; 983 u8 log_max_packet_reformat_context[0x5]; 984 u8 reserved_2b[0x6]; 985 u8 max_encap_header_size[0xa]; 986 987 u8 reserved_at_40[0xb]; 988 u8 log_max_esw_sf[0x5]; 989 u8 esw_sf_base_id[0x10]; 990 991 u8 reserved_at_60[0x7a0]; 992 993 }; 994 995 struct mlx5_ifc_qos_cap_bits { 996 u8 packet_pacing[0x1]; 997 u8 esw_scheduling[0x1]; 998 u8 esw_bw_share[0x1]; 999 u8 esw_rate_limit[0x1]; 1000 u8 reserved_at_4[0x1]; 1001 u8 packet_pacing_burst_bound[0x1]; 1002 u8 packet_pacing_typical_size[0x1]; 1003 u8 reserved_at_7[0x1]; 1004 u8 nic_sq_scheduling[0x1]; 1005 u8 nic_bw_share[0x1]; 1006 u8 nic_rate_limit[0x1]; 1007 u8 packet_pacing_uid[0x1]; 1008 u8 log_esw_max_sched_depth[0x4]; 1009 u8 reserved_at_10[0x10]; 1010 1011 u8 reserved_at_20[0xb]; 1012 u8 log_max_qos_nic_queue_group[0x5]; 1013 u8 reserved_at_30[0x10]; 1014 1015 u8 packet_pacing_max_rate[0x20]; 1016 1017 u8 packet_pacing_min_rate[0x20]; 1018 1019 u8 reserved_at_80[0x10]; 1020 u8 packet_pacing_rate_table_size[0x10]; 1021 1022 u8 esw_element_type[0x10]; 1023 u8 esw_tsar_type[0x10]; 1024 1025 u8 reserved_at_c0[0x10]; 1026 u8 max_qos_para_vport[0x10]; 1027 1028 u8 max_tsar_bw_share[0x20]; 1029 1030 u8 nic_element_type[0x10]; 1031 u8 nic_tsar_type[0x10]; 1032 1033 u8 reserved_at_120[0x3]; 1034 u8 log_meter_aso_granularity[0x5]; 1035 u8 reserved_at_128[0x3]; 1036 u8 log_meter_aso_max_alloc[0x5]; 1037 u8 reserved_at_130[0x3]; 1038 u8 log_max_num_meter_aso[0x5]; 1039 u8 reserved_at_138[0x8]; 1040 1041 u8 reserved_at_140[0x6c0]; 1042 }; 1043 1044 struct mlx5_ifc_debug_cap_bits { 1045 u8 core_dump_general[0x1]; 1046 u8 core_dump_qp[0x1]; 1047 u8 reserved_at_2[0x7]; 1048 u8 resource_dump[0x1]; 1049 u8 reserved_at_a[0x16]; 1050 1051 u8 reserved_at_20[0x2]; 1052 u8 stall_detect[0x1]; 1053 u8 reserved_at_23[0x1d]; 1054 1055 u8 reserved_at_40[0x7c0]; 1056 }; 1057 1058 struct mlx5_ifc_per_protocol_networking_offload_caps_bits { 1059 u8 csum_cap[0x1]; 1060 u8 vlan_cap[0x1]; 1061 u8 lro_cap[0x1]; 1062 u8 lro_psh_flag[0x1]; 1063 u8 lro_time_stamp[0x1]; 1064 u8 reserved_at_5[0x2]; 1065 u8 wqe_vlan_insert[0x1]; 1066 u8 self_lb_en_modifiable[0x1]; 1067 u8 reserved_at_9[0x2]; 1068 u8 max_lso_cap[0x5]; 1069 u8 multi_pkt_send_wqe[0x2]; 1070 u8 wqe_inline_mode[0x2]; 1071 u8 rss_ind_tbl_cap[0x4]; 1072 u8 reg_umr_sq[0x1]; 1073 u8 scatter_fcs[0x1]; 1074 u8 enhanced_multi_pkt_send_wqe[0x1]; 1075 u8 tunnel_lso_const_out_ip_id[0x1]; 1076 u8 tunnel_lro_gre[0x1]; 1077 u8 tunnel_lro_vxlan[0x1]; 1078 u8 tunnel_stateless_gre[0x1]; 1079 u8 tunnel_stateless_vxlan[0x1]; 1080 1081 u8 swp[0x1]; 1082 u8 swp_csum[0x1]; 1083 u8 swp_lso[0x1]; 1084 u8 cqe_checksum_full[0x1]; 1085 u8 tunnel_stateless_geneve_tx[0x1]; 1086 u8 tunnel_stateless_mpls_over_udp[0x1]; 1087 u8 tunnel_stateless_mpls_over_gre[0x1]; 1088 u8 tunnel_stateless_vxlan_gpe[0x1]; 1089 u8 tunnel_stateless_ipv4_over_vxlan[0x1]; 1090 u8 tunnel_stateless_ip_over_ip[0x1]; 1091 u8 insert_trailer[0x1]; 1092 u8 reserved_at_2b[0x1]; 1093 u8 tunnel_stateless_ip_over_ip_rx[0x1]; 1094 u8 tunnel_stateless_ip_over_ip_tx[0x1]; 1095 u8 reserved_at_2e[0x2]; 1096 u8 max_vxlan_udp_ports[0x8]; 1097 u8 swp_csum_l4_partial[0x1]; 1098 u8 reserved_at_39[0x5]; 1099 u8 max_geneve_opt_len[0x1]; 1100 u8 tunnel_stateless_geneve_rx[0x1]; 1101 1102 u8 reserved_at_40[0x10]; 1103 u8 lro_min_mss_size[0x10]; 1104 1105 u8 reserved_at_60[0x120]; 1106 1107 u8 lro_timer_supported_periods[4][0x20]; 1108 1109 u8 reserved_at_200[0x600]; 1110 }; 1111 1112 enum { 1113 MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING = 0x0, 1114 MLX5_TIMESTAMP_FORMAT_CAP_REAL_TIME = 0x1, 1115 MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING_AND_REAL_TIME = 0x2, 1116 }; 1117 1118 struct mlx5_ifc_roce_cap_bits { 1119 u8 roce_apm[0x1]; 1120 u8 reserved_at_1[0x3]; 1121 u8 sw_r_roce_src_udp_port[0x1]; 1122 u8 fl_rc_qp_when_roce_disabled[0x1]; 1123 u8 fl_rc_qp_when_roce_enabled[0x1]; 1124 u8 roce_cc_general[0x1]; 1125 u8 qp_ooo_transmit_default[0x1]; 1126 u8 reserved_at_9[0x15]; 1127 u8 qp_ts_format[0x2]; 1128 1129 u8 reserved_at_20[0x60]; 1130 1131 u8 reserved_at_80[0xc]; 1132 u8 l3_type[0x4]; 1133 u8 reserved_at_90[0x8]; 1134 u8 roce_version[0x8]; 1135 1136 u8 reserved_at_a0[0x10]; 1137 u8 r_roce_dest_udp_port[0x10]; 1138 1139 u8 r_roce_max_src_udp_port[0x10]; 1140 u8 r_roce_min_src_udp_port[0x10]; 1141 1142 u8 reserved_at_e0[0x10]; 1143 u8 roce_address_table_size[0x10]; 1144 1145 u8 reserved_at_100[0x700]; 1146 }; 1147 1148 struct mlx5_ifc_sync_steering_in_bits { 1149 u8 opcode[0x10]; 1150 u8 uid[0x10]; 1151 1152 u8 reserved_at_20[0x10]; 1153 u8 op_mod[0x10]; 1154 1155 u8 reserved_at_40[0xc0]; 1156 }; 1157 1158 struct mlx5_ifc_sync_steering_out_bits { 1159 u8 status[0x8]; 1160 u8 reserved_at_8[0x18]; 1161 1162 u8 syndrome[0x20]; 1163 1164 u8 reserved_at_40[0x40]; 1165 }; 1166 1167 struct mlx5_ifc_sync_crypto_in_bits { 1168 u8 opcode[0x10]; 1169 u8 uid[0x10]; 1170 1171 u8 reserved_at_20[0x10]; 1172 u8 op_mod[0x10]; 1173 1174 u8 reserved_at_40[0x20]; 1175 1176 u8 reserved_at_60[0x10]; 1177 u8 crypto_type[0x10]; 1178 1179 u8 reserved_at_80[0x80]; 1180 }; 1181 1182 struct mlx5_ifc_sync_crypto_out_bits { 1183 u8 status[0x8]; 1184 u8 reserved_at_8[0x18]; 1185 1186 u8 syndrome[0x20]; 1187 1188 u8 reserved_at_40[0x40]; 1189 }; 1190 1191 struct mlx5_ifc_device_mem_cap_bits { 1192 u8 memic[0x1]; 1193 u8 reserved_at_1[0x1f]; 1194 1195 u8 reserved_at_20[0xb]; 1196 u8 log_min_memic_alloc_size[0x5]; 1197 u8 reserved_at_30[0x8]; 1198 u8 log_max_memic_addr_alignment[0x8]; 1199 1200 u8 memic_bar_start_addr[0x40]; 1201 1202 u8 memic_bar_size[0x20]; 1203 1204 u8 max_memic_size[0x20]; 1205 1206 u8 steering_sw_icm_start_address[0x40]; 1207 1208 u8 reserved_at_100[0x8]; 1209 u8 log_header_modify_sw_icm_size[0x8]; 1210 u8 reserved_at_110[0x2]; 1211 u8 log_sw_icm_alloc_granularity[0x6]; 1212 u8 log_steering_sw_icm_size[0x8]; 1213 1214 u8 log_indirect_encap_sw_icm_size[0x8]; 1215 u8 reserved_at_128[0x10]; 1216 u8 log_header_modify_pattern_sw_icm_size[0x8]; 1217 1218 u8 header_modify_sw_icm_start_address[0x40]; 1219 1220 u8 reserved_at_180[0x40]; 1221 1222 u8 header_modify_pattern_sw_icm_start_address[0x40]; 1223 1224 u8 memic_operations[0x20]; 1225 1226 u8 reserved_at_220[0x20]; 1227 1228 u8 indirect_encap_sw_icm_start_address[0x40]; 1229 1230 u8 reserved_at_280[0x580]; 1231 }; 1232 1233 struct mlx5_ifc_device_event_cap_bits { 1234 u8 user_affiliated_events[4][0x40]; 1235 1236 u8 user_unaffiliated_events[4][0x40]; 1237 }; 1238 1239 struct mlx5_ifc_virtio_emulation_cap_bits { 1240 u8 desc_tunnel_offload_type[0x1]; 1241 u8 eth_frame_offload_type[0x1]; 1242 u8 virtio_version_1_0[0x1]; 1243 u8 device_features_bits_mask[0xd]; 1244 u8 event_mode[0x8]; 1245 u8 virtio_queue_type[0x8]; 1246 1247 u8 max_tunnel_desc[0x10]; 1248 u8 reserved_at_30[0x3]; 1249 u8 log_doorbell_stride[0x5]; 1250 u8 reserved_at_38[0x3]; 1251 u8 log_doorbell_bar_size[0x5]; 1252 1253 u8 doorbell_bar_offset[0x40]; 1254 1255 u8 max_emulated_devices[0x8]; 1256 u8 max_num_virtio_queues[0x18]; 1257 1258 u8 reserved_at_a0[0x20]; 1259 1260 u8 reserved_at_c0[0x13]; 1261 u8 desc_group_mkey_supported[0x1]; 1262 u8 freeze_to_rdy_supported[0x1]; 1263 u8 reserved_at_d5[0xb]; 1264 1265 u8 reserved_at_e0[0x20]; 1266 1267 u8 umem_1_buffer_param_a[0x20]; 1268 1269 u8 umem_1_buffer_param_b[0x20]; 1270 1271 u8 umem_2_buffer_param_a[0x20]; 1272 1273 u8 umem_2_buffer_param_b[0x20]; 1274 1275 u8 umem_3_buffer_param_a[0x20]; 1276 1277 u8 umem_3_buffer_param_b[0x20]; 1278 1279 u8 reserved_at_1c0[0x640]; 1280 }; 1281 1282 enum { 1283 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0, 1284 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2, 1285 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4, 1286 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8, 1287 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10, 1288 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20, 1289 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40, 1290 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80, 1291 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100, 1292 }; 1293 1294 enum { 1295 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1, 1296 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2, 1297 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4, 1298 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8, 1299 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10, 1300 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20, 1301 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40, 1302 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80, 1303 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100, 1304 }; 1305 1306 struct mlx5_ifc_atomic_caps_bits { 1307 u8 reserved_at_0[0x40]; 1308 1309 u8 atomic_req_8B_endianness_mode[0x2]; 1310 u8 reserved_at_42[0x4]; 1311 u8 supported_atomic_req_8B_endianness_mode_1[0x1]; 1312 1313 u8 reserved_at_47[0x19]; 1314 1315 u8 reserved_at_60[0x20]; 1316 1317 u8 reserved_at_80[0x10]; 1318 u8 atomic_operations[0x10]; 1319 1320 u8 reserved_at_a0[0x10]; 1321 u8 atomic_size_qp[0x10]; 1322 1323 u8 reserved_at_c0[0x10]; 1324 u8 atomic_size_dc[0x10]; 1325 1326 u8 reserved_at_e0[0x720]; 1327 }; 1328 1329 struct mlx5_ifc_odp_cap_bits { 1330 u8 reserved_at_0[0x40]; 1331 1332 u8 sig[0x1]; 1333 u8 reserved_at_41[0x1f]; 1334 1335 u8 reserved_at_60[0x20]; 1336 1337 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps; 1338 1339 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps; 1340 1341 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps; 1342 1343 struct mlx5_ifc_odp_per_transport_service_cap_bits xrc_odp_caps; 1344 1345 struct mlx5_ifc_odp_per_transport_service_cap_bits dc_odp_caps; 1346 1347 u8 reserved_at_120[0x6E0]; 1348 }; 1349 1350 struct mlx5_ifc_tls_cap_bits { 1351 u8 tls_1_2_aes_gcm_128[0x1]; 1352 u8 tls_1_3_aes_gcm_128[0x1]; 1353 u8 tls_1_2_aes_gcm_256[0x1]; 1354 u8 tls_1_3_aes_gcm_256[0x1]; 1355 u8 reserved_at_4[0x1c]; 1356 1357 u8 reserved_at_20[0x7e0]; 1358 }; 1359 1360 struct mlx5_ifc_ipsec_cap_bits { 1361 u8 ipsec_full_offload[0x1]; 1362 u8 ipsec_crypto_offload[0x1]; 1363 u8 ipsec_esn[0x1]; 1364 u8 ipsec_crypto_esp_aes_gcm_256_encrypt[0x1]; 1365 u8 ipsec_crypto_esp_aes_gcm_128_encrypt[0x1]; 1366 u8 ipsec_crypto_esp_aes_gcm_256_decrypt[0x1]; 1367 u8 ipsec_crypto_esp_aes_gcm_128_decrypt[0x1]; 1368 u8 reserved_at_7[0x4]; 1369 u8 log_max_ipsec_offload[0x5]; 1370 u8 reserved_at_10[0x10]; 1371 1372 u8 min_log_ipsec_full_replay_window[0x8]; 1373 u8 max_log_ipsec_full_replay_window[0x8]; 1374 u8 reserved_at_30[0x7d0]; 1375 }; 1376 1377 struct mlx5_ifc_macsec_cap_bits { 1378 u8 macsec_epn[0x1]; 1379 u8 reserved_at_1[0x2]; 1380 u8 macsec_crypto_esp_aes_gcm_256_encrypt[0x1]; 1381 u8 macsec_crypto_esp_aes_gcm_128_encrypt[0x1]; 1382 u8 macsec_crypto_esp_aes_gcm_256_decrypt[0x1]; 1383 u8 macsec_crypto_esp_aes_gcm_128_decrypt[0x1]; 1384 u8 reserved_at_7[0x4]; 1385 u8 log_max_macsec_offload[0x5]; 1386 u8 reserved_at_10[0x10]; 1387 1388 u8 min_log_macsec_full_replay_window[0x8]; 1389 u8 max_log_macsec_full_replay_window[0x8]; 1390 u8 reserved_at_30[0x10]; 1391 1392 u8 reserved_at_40[0x7c0]; 1393 }; 1394 1395 enum { 1396 MLX5_WQ_TYPE_LINKED_LIST = 0x0, 1397 MLX5_WQ_TYPE_CYCLIC = 0x1, 1398 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2, 1399 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3, 1400 }; 1401 1402 enum { 1403 MLX5_WQ_END_PAD_MODE_NONE = 0x0, 1404 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1, 1405 }; 1406 1407 enum { 1408 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0, 1409 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1, 1410 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2, 1411 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3, 1412 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4, 1413 }; 1414 1415 enum { 1416 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0, 1417 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1, 1418 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2, 1419 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3, 1420 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4, 1421 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5, 1422 }; 1423 1424 enum { 1425 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0, 1426 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1, 1427 }; 1428 1429 enum { 1430 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0, 1431 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1, 1432 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3, 1433 }; 1434 1435 enum { 1436 MLX5_CAP_PORT_TYPE_IB = 0x0, 1437 MLX5_CAP_PORT_TYPE_ETH = 0x1, 1438 }; 1439 1440 enum { 1441 MLX5_CAP_UMR_FENCE_STRONG = 0x0, 1442 MLX5_CAP_UMR_FENCE_SMALL = 0x1, 1443 MLX5_CAP_UMR_FENCE_NONE = 0x2, 1444 }; 1445 1446 enum { 1447 MLX5_FLEX_PARSER_GENEVE_ENABLED = 1 << 3, 1448 MLX5_FLEX_PARSER_MPLS_OVER_GRE_ENABLED = 1 << 4, 1449 MLX5_FLEX_PARSER_MPLS_OVER_UDP_ENABLED = 1 << 5, 1450 MLX5_FLEX_PARSER_VXLAN_GPE_ENABLED = 1 << 7, 1451 MLX5_FLEX_PARSER_ICMP_V4_ENABLED = 1 << 8, 1452 MLX5_FLEX_PARSER_ICMP_V6_ENABLED = 1 << 9, 1453 MLX5_FLEX_PARSER_GENEVE_TLV_OPTION_0_ENABLED = 1 << 10, 1454 MLX5_FLEX_PARSER_GTPU_ENABLED = 1 << 11, 1455 MLX5_FLEX_PARSER_GTPU_DW_2_ENABLED = 1 << 16, 1456 MLX5_FLEX_PARSER_GTPU_FIRST_EXT_DW_0_ENABLED = 1 << 17, 1457 MLX5_FLEX_PARSER_GTPU_DW_0_ENABLED = 1 << 18, 1458 MLX5_FLEX_PARSER_GTPU_TEID_ENABLED = 1 << 19, 1459 }; 1460 1461 enum { 1462 MLX5_UCTX_CAP_RAW_TX = 1UL << 0, 1463 MLX5_UCTX_CAP_INTERNAL_DEV_RES = 1UL << 1, 1464 }; 1465 1466 #define MLX5_FC_BULK_SIZE_FACTOR 128 1467 1468 enum mlx5_fc_bulk_alloc_bitmask { 1469 MLX5_FC_BULK_128 = (1 << 0), 1470 MLX5_FC_BULK_256 = (1 << 1), 1471 MLX5_FC_BULK_512 = (1 << 2), 1472 MLX5_FC_BULK_1024 = (1 << 3), 1473 MLX5_FC_BULK_2048 = (1 << 4), 1474 MLX5_FC_BULK_4096 = (1 << 5), 1475 MLX5_FC_BULK_8192 = (1 << 6), 1476 MLX5_FC_BULK_16384 = (1 << 7), 1477 }; 1478 1479 #define MLX5_FC_BULK_NUM_FCS(fc_enum) (MLX5_FC_BULK_SIZE_FACTOR * (fc_enum)) 1480 1481 #define MLX5_FT_MAX_MULTIPATH_LEVEL 63 1482 1483 enum { 1484 MLX5_STEERING_FORMAT_CONNECTX_5 = 0, 1485 MLX5_STEERING_FORMAT_CONNECTX_6DX = 1, 1486 MLX5_STEERING_FORMAT_CONNECTX_7 = 2, 1487 }; 1488 1489 struct mlx5_ifc_cmd_hca_cap_bits { 1490 u8 reserved_at_0[0x6]; 1491 u8 page_request_disable[0x1]; 1492 u8 reserved_at_7[0x9]; 1493 u8 shared_object_to_user_object_allowed[0x1]; 1494 u8 reserved_at_13[0xe]; 1495 u8 vhca_resource_manager[0x1]; 1496 1497 u8 hca_cap_2[0x1]; 1498 u8 create_lag_when_not_master_up[0x1]; 1499 u8 dtor[0x1]; 1500 u8 event_on_vhca_state_teardown_request[0x1]; 1501 u8 event_on_vhca_state_in_use[0x1]; 1502 u8 event_on_vhca_state_active[0x1]; 1503 u8 event_on_vhca_state_allocated[0x1]; 1504 u8 event_on_vhca_state_invalid[0x1]; 1505 u8 reserved_at_28[0x8]; 1506 u8 vhca_id[0x10]; 1507 1508 u8 reserved_at_40[0x40]; 1509 1510 u8 log_max_srq_sz[0x8]; 1511 u8 log_max_qp_sz[0x8]; 1512 u8 event_cap[0x1]; 1513 u8 reserved_at_91[0x2]; 1514 u8 isolate_vl_tc_new[0x1]; 1515 u8 reserved_at_94[0x4]; 1516 u8 prio_tag_required[0x1]; 1517 u8 reserved_at_99[0x2]; 1518 u8 log_max_qp[0x5]; 1519 1520 u8 reserved_at_a0[0x3]; 1521 u8 ece_support[0x1]; 1522 u8 reserved_at_a4[0x5]; 1523 u8 reg_c_preserve[0x1]; 1524 u8 reserved_at_aa[0x1]; 1525 u8 log_max_srq[0x5]; 1526 u8 reserved_at_b0[0x1]; 1527 u8 uplink_follow[0x1]; 1528 u8 ts_cqe_to_dest_cqn[0x1]; 1529 u8 reserved_at_b3[0x6]; 1530 u8 go_back_n[0x1]; 1531 u8 reserved_at_ba[0x6]; 1532 1533 u8 max_sgl_for_optimized_performance[0x8]; 1534 u8 log_max_cq_sz[0x8]; 1535 u8 relaxed_ordering_write_umr[0x1]; 1536 u8 relaxed_ordering_read_umr[0x1]; 1537 u8 reserved_at_d2[0x7]; 1538 u8 virtio_net_device_emualtion_manager[0x1]; 1539 u8 virtio_blk_device_emualtion_manager[0x1]; 1540 u8 log_max_cq[0x5]; 1541 1542 u8 log_max_eq_sz[0x8]; 1543 u8 relaxed_ordering_write[0x1]; 1544 u8 relaxed_ordering_read_pci_enabled[0x1]; 1545 u8 log_max_mkey[0x6]; 1546 u8 reserved_at_f0[0x6]; 1547 u8 terminate_scatter_list_mkey[0x1]; 1548 u8 repeated_mkey[0x1]; 1549 u8 dump_fill_mkey[0x1]; 1550 u8 reserved_at_f9[0x2]; 1551 u8 fast_teardown[0x1]; 1552 u8 log_max_eq[0x4]; 1553 1554 u8 max_indirection[0x8]; 1555 u8 fixed_buffer_size[0x1]; 1556 u8 log_max_mrw_sz[0x7]; 1557 u8 force_teardown[0x1]; 1558 u8 reserved_at_111[0x1]; 1559 u8 log_max_bsf_list_size[0x6]; 1560 u8 umr_extended_translation_offset[0x1]; 1561 u8 null_mkey[0x1]; 1562 u8 log_max_klm_list_size[0x6]; 1563 1564 u8 reserved_at_120[0x2]; 1565 u8 qpc_extension[0x1]; 1566 u8 reserved_at_123[0x7]; 1567 u8 log_max_ra_req_dc[0x6]; 1568 u8 reserved_at_130[0x2]; 1569 u8 eth_wqe_too_small[0x1]; 1570 u8 reserved_at_133[0x6]; 1571 u8 vnic_env_cq_overrun[0x1]; 1572 u8 log_max_ra_res_dc[0x6]; 1573 1574 u8 reserved_at_140[0x5]; 1575 u8 release_all_pages[0x1]; 1576 u8 must_not_use[0x1]; 1577 u8 reserved_at_147[0x2]; 1578 u8 roce_accl[0x1]; 1579 u8 log_max_ra_req_qp[0x6]; 1580 u8 reserved_at_150[0xa]; 1581 u8 log_max_ra_res_qp[0x6]; 1582 1583 u8 end_pad[0x1]; 1584 u8 cc_query_allowed[0x1]; 1585 u8 cc_modify_allowed[0x1]; 1586 u8 start_pad[0x1]; 1587 u8 cache_line_128byte[0x1]; 1588 u8 reserved_at_165[0x4]; 1589 u8 rts2rts_qp_counters_set_id[0x1]; 1590 u8 reserved_at_16a[0x2]; 1591 u8 vnic_env_int_rq_oob[0x1]; 1592 u8 sbcam_reg[0x1]; 1593 u8 reserved_at_16e[0x1]; 1594 u8 qcam_reg[0x1]; 1595 u8 gid_table_size[0x10]; 1596 1597 u8 out_of_seq_cnt[0x1]; 1598 u8 vport_counters[0x1]; 1599 u8 retransmission_q_counters[0x1]; 1600 u8 debug[0x1]; 1601 u8 modify_rq_counter_set_id[0x1]; 1602 u8 rq_delay_drop[0x1]; 1603 u8 max_qp_cnt[0xa]; 1604 u8 pkey_table_size[0x10]; 1605 1606 u8 vport_group_manager[0x1]; 1607 u8 vhca_group_manager[0x1]; 1608 u8 ib_virt[0x1]; 1609 u8 eth_virt[0x1]; 1610 u8 vnic_env_queue_counters[0x1]; 1611 u8 ets[0x1]; 1612 u8 nic_flow_table[0x1]; 1613 u8 eswitch_manager[0x1]; 1614 u8 device_memory[0x1]; 1615 u8 mcam_reg[0x1]; 1616 u8 pcam_reg[0x1]; 1617 u8 local_ca_ack_delay[0x5]; 1618 u8 port_module_event[0x1]; 1619 u8 enhanced_error_q_counters[0x1]; 1620 u8 ports_check[0x1]; 1621 u8 reserved_at_1b3[0x1]; 1622 u8 disable_link_up[0x1]; 1623 u8 beacon_led[0x1]; 1624 u8 port_type[0x2]; 1625 u8 num_ports[0x8]; 1626 1627 u8 reserved_at_1c0[0x1]; 1628 u8 pps[0x1]; 1629 u8 pps_modify[0x1]; 1630 u8 log_max_msg[0x5]; 1631 u8 reserved_at_1c8[0x4]; 1632 u8 max_tc[0x4]; 1633 u8 temp_warn_event[0x1]; 1634 u8 dcbx[0x1]; 1635 u8 general_notification_event[0x1]; 1636 u8 reserved_at_1d3[0x2]; 1637 u8 fpga[0x1]; 1638 u8 rol_s[0x1]; 1639 u8 rol_g[0x1]; 1640 u8 reserved_at_1d8[0x1]; 1641 u8 wol_s[0x1]; 1642 u8 wol_g[0x1]; 1643 u8 wol_a[0x1]; 1644 u8 wol_b[0x1]; 1645 u8 wol_m[0x1]; 1646 u8 wol_u[0x1]; 1647 u8 wol_p[0x1]; 1648 1649 u8 stat_rate_support[0x10]; 1650 u8 reserved_at_1f0[0x1]; 1651 u8 pci_sync_for_fw_update_event[0x1]; 1652 u8 reserved_at_1f2[0x6]; 1653 u8 init2_lag_tx_port_affinity[0x1]; 1654 u8 reserved_at_1fa[0x3]; 1655 u8 cqe_version[0x4]; 1656 1657 u8 compact_address_vector[0x1]; 1658 u8 striding_rq[0x1]; 1659 u8 reserved_at_202[0x1]; 1660 u8 ipoib_enhanced_offloads[0x1]; 1661 u8 ipoib_basic_offloads[0x1]; 1662 u8 reserved_at_205[0x1]; 1663 u8 repeated_block_disabled[0x1]; 1664 u8 umr_modify_entity_size_disabled[0x1]; 1665 u8 umr_modify_atomic_disabled[0x1]; 1666 u8 umr_indirect_mkey_disabled[0x1]; 1667 u8 umr_fence[0x2]; 1668 u8 dc_req_scat_data_cqe[0x1]; 1669 u8 reserved_at_20d[0x2]; 1670 u8 drain_sigerr[0x1]; 1671 u8 cmdif_checksum[0x2]; 1672 u8 sigerr_cqe[0x1]; 1673 u8 reserved_at_213[0x1]; 1674 u8 wq_signature[0x1]; 1675 u8 sctr_data_cqe[0x1]; 1676 u8 reserved_at_216[0x1]; 1677 u8 sho[0x1]; 1678 u8 tph[0x1]; 1679 u8 rf[0x1]; 1680 u8 dct[0x1]; 1681 u8 qos[0x1]; 1682 u8 eth_net_offloads[0x1]; 1683 u8 roce[0x1]; 1684 u8 atomic[0x1]; 1685 u8 reserved_at_21f[0x1]; 1686 1687 u8 cq_oi[0x1]; 1688 u8 cq_resize[0x1]; 1689 u8 cq_moderation[0x1]; 1690 u8 cq_period_mode_modify[0x1]; 1691 u8 reserved_at_224[0x2]; 1692 u8 cq_eq_remap[0x1]; 1693 u8 pg[0x1]; 1694 u8 block_lb_mc[0x1]; 1695 u8 reserved_at_229[0x1]; 1696 u8 scqe_break_moderation[0x1]; 1697 u8 cq_period_start_from_cqe[0x1]; 1698 u8 cd[0x1]; 1699 u8 reserved_at_22d[0x1]; 1700 u8 apm[0x1]; 1701 u8 vector_calc[0x1]; 1702 u8 umr_ptr_rlky[0x1]; 1703 u8 imaicl[0x1]; 1704 u8 qp_packet_based[0x1]; 1705 u8 reserved_at_233[0x3]; 1706 u8 qkv[0x1]; 1707 u8 pkv[0x1]; 1708 u8 set_deth_sqpn[0x1]; 1709 u8 reserved_at_239[0x3]; 1710 u8 xrc[0x1]; 1711 u8 ud[0x1]; 1712 u8 uc[0x1]; 1713 u8 rc[0x1]; 1714 1715 u8 uar_4k[0x1]; 1716 u8 reserved_at_241[0x7]; 1717 u8 fl_rc_qp_when_roce_disabled[0x1]; 1718 u8 regexp_params[0x1]; 1719 u8 uar_sz[0x6]; 1720 u8 port_selection_cap[0x1]; 1721 u8 reserved_at_251[0x1]; 1722 u8 umem_uid_0[0x1]; 1723 u8 reserved_at_253[0x5]; 1724 u8 log_pg_sz[0x8]; 1725 1726 u8 bf[0x1]; 1727 u8 driver_version[0x1]; 1728 u8 pad_tx_eth_packet[0x1]; 1729 u8 reserved_at_263[0x3]; 1730 u8 mkey_by_name[0x1]; 1731 u8 reserved_at_267[0x4]; 1732 1733 u8 log_bf_reg_size[0x5]; 1734 1735 u8 reserved_at_270[0x3]; 1736 u8 qp_error_syndrome[0x1]; 1737 u8 reserved_at_274[0x2]; 1738 u8 lag_dct[0x2]; 1739 u8 lag_tx_port_affinity[0x1]; 1740 u8 lag_native_fdb_selection[0x1]; 1741 u8 reserved_at_27a[0x1]; 1742 u8 lag_master[0x1]; 1743 u8 num_lag_ports[0x4]; 1744 1745 u8 reserved_at_280[0x10]; 1746 u8 max_wqe_sz_sq[0x10]; 1747 1748 u8 reserved_at_2a0[0xb]; 1749 u8 shampo[0x1]; 1750 u8 reserved_at_2ac[0x4]; 1751 u8 max_wqe_sz_rq[0x10]; 1752 1753 u8 max_flow_counter_31_16[0x10]; 1754 u8 max_wqe_sz_sq_dc[0x10]; 1755 1756 u8 reserved_at_2e0[0x7]; 1757 u8 max_qp_mcg[0x19]; 1758 1759 u8 reserved_at_300[0x10]; 1760 u8 flow_counter_bulk_alloc[0x8]; 1761 u8 log_max_mcg[0x8]; 1762 1763 u8 reserved_at_320[0x3]; 1764 u8 log_max_transport_domain[0x5]; 1765 u8 reserved_at_328[0x2]; 1766 u8 relaxed_ordering_read[0x1]; 1767 u8 log_max_pd[0x5]; 1768 u8 reserved_at_330[0x6]; 1769 u8 pci_sync_for_fw_update_with_driver_unload[0x1]; 1770 u8 vnic_env_cnt_steering_fail[0x1]; 1771 u8 vport_counter_local_loopback[0x1]; 1772 u8 q_counter_aggregation[0x1]; 1773 u8 q_counter_other_vport[0x1]; 1774 u8 log_max_xrcd[0x5]; 1775 1776 u8 nic_receive_steering_discard[0x1]; 1777 u8 receive_discard_vport_down[0x1]; 1778 u8 transmit_discard_vport_down[0x1]; 1779 u8 eq_overrun_count[0x1]; 1780 u8 reserved_at_344[0x1]; 1781 u8 invalid_command_count[0x1]; 1782 u8 quota_exceeded_count[0x1]; 1783 u8 reserved_at_347[0x1]; 1784 u8 log_max_flow_counter_bulk[0x8]; 1785 u8 max_flow_counter_15_0[0x10]; 1786 1787 1788 u8 reserved_at_360[0x3]; 1789 u8 log_max_rq[0x5]; 1790 u8 reserved_at_368[0x3]; 1791 u8 log_max_sq[0x5]; 1792 u8 reserved_at_370[0x3]; 1793 u8 log_max_tir[0x5]; 1794 u8 reserved_at_378[0x3]; 1795 u8 log_max_tis[0x5]; 1796 1797 u8 basic_cyclic_rcv_wqe[0x1]; 1798 u8 reserved_at_381[0x2]; 1799 u8 log_max_rmp[0x5]; 1800 u8 reserved_at_388[0x3]; 1801 u8 log_max_rqt[0x5]; 1802 u8 reserved_at_390[0x3]; 1803 u8 log_max_rqt_size[0x5]; 1804 u8 reserved_at_398[0x3]; 1805 u8 log_max_tis_per_sq[0x5]; 1806 1807 u8 ext_stride_num_range[0x1]; 1808 u8 roce_rw_supported[0x1]; 1809 u8 log_max_current_uc_list_wr_supported[0x1]; 1810 u8 log_max_stride_sz_rq[0x5]; 1811 u8 reserved_at_3a8[0x3]; 1812 u8 log_min_stride_sz_rq[0x5]; 1813 u8 reserved_at_3b0[0x3]; 1814 u8 log_max_stride_sz_sq[0x5]; 1815 u8 reserved_at_3b8[0x3]; 1816 u8 log_min_stride_sz_sq[0x5]; 1817 1818 u8 hairpin[0x1]; 1819 u8 reserved_at_3c1[0x2]; 1820 u8 log_max_hairpin_queues[0x5]; 1821 u8 reserved_at_3c8[0x3]; 1822 u8 log_max_hairpin_wq_data_sz[0x5]; 1823 u8 reserved_at_3d0[0x3]; 1824 u8 log_max_hairpin_num_packets[0x5]; 1825 u8 reserved_at_3d8[0x3]; 1826 u8 log_max_wq_sz[0x5]; 1827 1828 u8 nic_vport_change_event[0x1]; 1829 u8 disable_local_lb_uc[0x1]; 1830 u8 disable_local_lb_mc[0x1]; 1831 u8 log_min_hairpin_wq_data_sz[0x5]; 1832 u8 reserved_at_3e8[0x1]; 1833 u8 silent_mode[0x1]; 1834 u8 vhca_state[0x1]; 1835 u8 log_max_vlan_list[0x5]; 1836 u8 reserved_at_3f0[0x3]; 1837 u8 log_max_current_mc_list[0x5]; 1838 u8 reserved_at_3f8[0x3]; 1839 u8 log_max_current_uc_list[0x5]; 1840 1841 u8 general_obj_types[0x40]; 1842 1843 u8 sq_ts_format[0x2]; 1844 u8 rq_ts_format[0x2]; 1845 u8 steering_format_version[0x4]; 1846 u8 create_qp_start_hint[0x18]; 1847 1848 u8 reserved_at_460[0x1]; 1849 u8 ats[0x1]; 1850 u8 cross_vhca_rqt[0x1]; 1851 u8 log_max_uctx[0x5]; 1852 u8 reserved_at_468[0x1]; 1853 u8 crypto[0x1]; 1854 u8 ipsec_offload[0x1]; 1855 u8 log_max_umem[0x5]; 1856 u8 max_num_eqs[0x10]; 1857 1858 u8 reserved_at_480[0x1]; 1859 u8 tls_tx[0x1]; 1860 u8 tls_rx[0x1]; 1861 u8 log_max_l2_table[0x5]; 1862 u8 reserved_at_488[0x8]; 1863 u8 log_uar_page_sz[0x10]; 1864 1865 u8 reserved_at_4a0[0x20]; 1866 u8 device_frequency_mhz[0x20]; 1867 u8 device_frequency_khz[0x20]; 1868 1869 u8 reserved_at_500[0x20]; 1870 u8 num_of_uars_per_page[0x20]; 1871 1872 u8 flex_parser_protocols[0x20]; 1873 1874 u8 max_geneve_tlv_options[0x8]; 1875 u8 reserved_at_568[0x3]; 1876 u8 max_geneve_tlv_option_data_len[0x5]; 1877 u8 reserved_at_570[0x9]; 1878 u8 adv_virtualization[0x1]; 1879 u8 reserved_at_57a[0x6]; 1880 1881 u8 reserved_at_580[0xb]; 1882 u8 log_max_dci_stream_channels[0x5]; 1883 u8 reserved_at_590[0x3]; 1884 u8 log_max_dci_errored_streams[0x5]; 1885 u8 reserved_at_598[0x8]; 1886 1887 u8 reserved_at_5a0[0x10]; 1888 u8 enhanced_cqe_compression[0x1]; 1889 u8 reserved_at_5b1[0x2]; 1890 u8 log_max_dek[0x5]; 1891 u8 reserved_at_5b8[0x4]; 1892 u8 mini_cqe_resp_stride_index[0x1]; 1893 u8 cqe_128_always[0x1]; 1894 u8 cqe_compression_128[0x1]; 1895 u8 cqe_compression[0x1]; 1896 1897 u8 cqe_compression_timeout[0x10]; 1898 u8 cqe_compression_max_num[0x10]; 1899 1900 u8 reserved_at_5e0[0x8]; 1901 u8 flex_parser_id_gtpu_dw_0[0x4]; 1902 u8 reserved_at_5ec[0x4]; 1903 u8 tag_matching[0x1]; 1904 u8 rndv_offload_rc[0x1]; 1905 u8 rndv_offload_dc[0x1]; 1906 u8 log_tag_matching_list_sz[0x5]; 1907 u8 reserved_at_5f8[0x3]; 1908 u8 log_max_xrq[0x5]; 1909 1910 u8 affiliate_nic_vport_criteria[0x8]; 1911 u8 native_port_num[0x8]; 1912 u8 num_vhca_ports[0x8]; 1913 u8 flex_parser_id_gtpu_teid[0x4]; 1914 u8 reserved_at_61c[0x2]; 1915 u8 sw_owner_id[0x1]; 1916 u8 reserved_at_61f[0x1]; 1917 1918 u8 max_num_of_monitor_counters[0x10]; 1919 u8 num_ppcnt_monitor_counters[0x10]; 1920 1921 u8 max_num_sf[0x10]; 1922 u8 num_q_monitor_counters[0x10]; 1923 1924 u8 reserved_at_660[0x20]; 1925 1926 u8 sf[0x1]; 1927 u8 sf_set_partition[0x1]; 1928 u8 reserved_at_682[0x1]; 1929 u8 log_max_sf[0x5]; 1930 u8 apu[0x1]; 1931 u8 reserved_at_689[0x4]; 1932 u8 migration[0x1]; 1933 u8 reserved_at_68e[0x2]; 1934 u8 log_min_sf_size[0x8]; 1935 u8 max_num_sf_partitions[0x8]; 1936 1937 u8 uctx_cap[0x20]; 1938 1939 u8 reserved_at_6c0[0x4]; 1940 u8 flex_parser_id_geneve_tlv_option_0[0x4]; 1941 u8 flex_parser_id_icmp_dw1[0x4]; 1942 u8 flex_parser_id_icmp_dw0[0x4]; 1943 u8 flex_parser_id_icmpv6_dw1[0x4]; 1944 u8 flex_parser_id_icmpv6_dw0[0x4]; 1945 u8 flex_parser_id_outer_first_mpls_over_gre[0x4]; 1946 u8 flex_parser_id_outer_first_mpls_over_udp_label[0x4]; 1947 1948 u8 max_num_match_definer[0x10]; 1949 u8 sf_base_id[0x10]; 1950 1951 u8 flex_parser_id_gtpu_dw_2[0x4]; 1952 u8 flex_parser_id_gtpu_first_ext_dw_0[0x4]; 1953 u8 num_total_dynamic_vf_msix[0x18]; 1954 u8 reserved_at_720[0x14]; 1955 u8 dynamic_msix_table_size[0xc]; 1956 u8 reserved_at_740[0xc]; 1957 u8 min_dynamic_vf_msix_table_size[0x4]; 1958 u8 reserved_at_750[0x4]; 1959 u8 max_dynamic_vf_msix_table_size[0xc]; 1960 1961 u8 reserved_at_760[0x3]; 1962 u8 log_max_num_header_modify_argument[0x5]; 1963 u8 reserved_at_768[0x4]; 1964 u8 log_header_modify_argument_granularity[0x4]; 1965 u8 reserved_at_770[0x3]; 1966 u8 log_header_modify_argument_max_alloc[0x5]; 1967 u8 reserved_at_778[0x8]; 1968 1969 u8 vhca_tunnel_commands[0x40]; 1970 u8 match_definer_format_supported[0x40]; 1971 }; 1972 1973 enum { 1974 MLX5_CROSS_VHCA_OBJ_TO_OBJ_SUPPORTED_LOCAL_FLOW_TABLE_TO_REMOTE_FLOW_TABLE_MISS = 0x80000, 1975 MLX5_CROSS_VHCA_OBJ_TO_OBJ_SUPPORTED_LOCAL_FLOW_TABLE_ROOT_TO_REMOTE_FLOW_TABLE = (1ULL << 20), 1976 }; 1977 1978 enum { 1979 MLX5_ALLOWED_OBJ_FOR_OTHER_VHCA_ACCESS_FLOW_TABLE = 0x200, 1980 }; 1981 1982 struct mlx5_ifc_cmd_hca_cap_2_bits { 1983 u8 reserved_at_0[0x80]; 1984 1985 u8 migratable[0x1]; 1986 u8 reserved_at_81[0x1f]; 1987 1988 u8 max_reformat_insert_size[0x8]; 1989 u8 max_reformat_insert_offset[0x8]; 1990 u8 max_reformat_remove_size[0x8]; 1991 u8 max_reformat_remove_offset[0x8]; 1992 1993 u8 reserved_at_c0[0x8]; 1994 u8 migration_multi_load[0x1]; 1995 u8 migration_tracking_state[0x1]; 1996 u8 multiplane_qp_ud[0x1]; 1997 u8 reserved_at_cb[0x5]; 1998 u8 migration_in_chunks[0x1]; 1999 u8 reserved_at_d1[0x1]; 2000 u8 sf_eq_usage[0x1]; 2001 u8 reserved_at_d3[0xd]; 2002 2003 u8 cross_vhca_object_to_object_supported[0x20]; 2004 2005 u8 allowed_object_for_other_vhca_access[0x40]; 2006 2007 u8 reserved_at_140[0x60]; 2008 2009 u8 flow_table_type_2_type[0x8]; 2010 u8 reserved_at_1a8[0x3]; 2011 u8 log_min_mkey_entity_size[0x5]; 2012 u8 reserved_at_1b0[0x10]; 2013 2014 u8 reserved_at_1c0[0x60]; 2015 2016 u8 reserved_at_220[0x1]; 2017 u8 sw_vhca_id_valid[0x1]; 2018 u8 sw_vhca_id[0xe]; 2019 u8 reserved_at_230[0x10]; 2020 2021 u8 reserved_at_240[0xb]; 2022 u8 ts_cqe_metadata_size2wqe_counter[0x5]; 2023 u8 reserved_at_250[0x10]; 2024 2025 u8 reserved_at_260[0x120]; 2026 u8 reserved_at_380[0xb]; 2027 u8 min_mkey_log_entity_size_fixed_buffer[0x5]; 2028 u8 ec_vf_vport_base[0x10]; 2029 2030 u8 reserved_at_3a0[0x10]; 2031 u8 max_rqt_vhca_id[0x10]; 2032 2033 u8 reserved_at_3c0[0x20]; 2034 2035 u8 reserved_at_3e0[0x10]; 2036 u8 pcc_ifa2[0x1]; 2037 u8 reserved_at_3f1[0xf]; 2038 2039 u8 reserved_at_400[0x1]; 2040 u8 min_mkey_log_entity_size_fixed_buffer_valid[0x1]; 2041 u8 reserved_at_402[0x1e]; 2042 2043 u8 reserved_at_420[0x20]; 2044 2045 u8 reserved_at_440[0x8]; 2046 u8 max_num_eqs_24b[0x18]; 2047 u8 reserved_at_460[0x3a0]; 2048 }; 2049 2050 enum mlx5_ifc_flow_destination_type { 2051 MLX5_IFC_FLOW_DESTINATION_TYPE_VPORT = 0x0, 2052 MLX5_IFC_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1, 2053 MLX5_IFC_FLOW_DESTINATION_TYPE_TIR = 0x2, 2054 MLX5_IFC_FLOW_DESTINATION_TYPE_FLOW_SAMPLER = 0x6, 2055 MLX5_IFC_FLOW_DESTINATION_TYPE_UPLINK = 0x8, 2056 MLX5_IFC_FLOW_DESTINATION_TYPE_TABLE_TYPE = 0xA, 2057 }; 2058 2059 enum mlx5_flow_table_miss_action { 2060 MLX5_FLOW_TABLE_MISS_ACTION_DEF, 2061 MLX5_FLOW_TABLE_MISS_ACTION_FWD, 2062 MLX5_FLOW_TABLE_MISS_ACTION_SWITCH_DOMAIN, 2063 }; 2064 2065 struct mlx5_ifc_dest_format_struct_bits { 2066 u8 destination_type[0x8]; 2067 u8 destination_id[0x18]; 2068 2069 u8 destination_eswitch_owner_vhca_id_valid[0x1]; 2070 u8 packet_reformat[0x1]; 2071 u8 reserved_at_22[0x6]; 2072 u8 destination_table_type[0x8]; 2073 u8 destination_eswitch_owner_vhca_id[0x10]; 2074 }; 2075 2076 struct mlx5_ifc_flow_counter_list_bits { 2077 u8 flow_counter_id[0x20]; 2078 2079 u8 reserved_at_20[0x20]; 2080 }; 2081 2082 struct mlx5_ifc_extended_dest_format_bits { 2083 struct mlx5_ifc_dest_format_struct_bits destination_entry; 2084 2085 u8 packet_reformat_id[0x20]; 2086 2087 u8 reserved_at_60[0x20]; 2088 }; 2089 2090 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits { 2091 struct mlx5_ifc_extended_dest_format_bits extended_dest_format; 2092 struct mlx5_ifc_flow_counter_list_bits flow_counter_list; 2093 }; 2094 2095 struct mlx5_ifc_fte_match_param_bits { 2096 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers; 2097 2098 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters; 2099 2100 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers; 2101 2102 struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2; 2103 2104 struct mlx5_ifc_fte_match_set_misc3_bits misc_parameters_3; 2105 2106 struct mlx5_ifc_fte_match_set_misc4_bits misc_parameters_4; 2107 2108 struct mlx5_ifc_fte_match_set_misc5_bits misc_parameters_5; 2109 2110 u8 reserved_at_e00[0x200]; 2111 }; 2112 2113 enum { 2114 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0, 2115 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1, 2116 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2, 2117 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3, 2118 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4, 2119 }; 2120 2121 struct mlx5_ifc_rx_hash_field_select_bits { 2122 u8 l3_prot_type[0x1]; 2123 u8 l4_prot_type[0x1]; 2124 u8 selected_fields[0x1e]; 2125 }; 2126 2127 enum { 2128 MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0, 2129 MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1, 2130 }; 2131 2132 enum { 2133 MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0, 2134 MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1, 2135 }; 2136 2137 struct mlx5_ifc_wq_bits { 2138 u8 wq_type[0x4]; 2139 u8 wq_signature[0x1]; 2140 u8 end_padding_mode[0x2]; 2141 u8 cd_slave[0x1]; 2142 u8 reserved_at_8[0x18]; 2143 2144 u8 hds_skip_first_sge[0x1]; 2145 u8 log2_hds_buf_size[0x3]; 2146 u8 reserved_at_24[0x7]; 2147 u8 page_offset[0x5]; 2148 u8 lwm[0x10]; 2149 2150 u8 reserved_at_40[0x8]; 2151 u8 pd[0x18]; 2152 2153 u8 reserved_at_60[0x8]; 2154 u8 uar_page[0x18]; 2155 2156 u8 dbr_addr[0x40]; 2157 2158 u8 hw_counter[0x20]; 2159 2160 u8 sw_counter[0x20]; 2161 2162 u8 reserved_at_100[0xc]; 2163 u8 log_wq_stride[0x4]; 2164 u8 reserved_at_110[0x3]; 2165 u8 log_wq_pg_sz[0x5]; 2166 u8 reserved_at_118[0x3]; 2167 u8 log_wq_sz[0x5]; 2168 2169 u8 dbr_umem_valid[0x1]; 2170 u8 wq_umem_valid[0x1]; 2171 u8 reserved_at_122[0x1]; 2172 u8 log_hairpin_num_packets[0x5]; 2173 u8 reserved_at_128[0x3]; 2174 u8 log_hairpin_data_sz[0x5]; 2175 2176 u8 reserved_at_130[0x4]; 2177 u8 log_wqe_num_of_strides[0x4]; 2178 u8 two_byte_shift_en[0x1]; 2179 u8 reserved_at_139[0x4]; 2180 u8 log_wqe_stride_size[0x3]; 2181 2182 u8 reserved_at_140[0x80]; 2183 2184 u8 headers_mkey[0x20]; 2185 2186 u8 shampo_enable[0x1]; 2187 u8 reserved_at_1e1[0x4]; 2188 u8 log_reservation_size[0x3]; 2189 u8 reserved_at_1e8[0x5]; 2190 u8 log_max_num_of_packets_per_reservation[0x3]; 2191 u8 reserved_at_1f0[0x6]; 2192 u8 log_headers_entry_size[0x2]; 2193 u8 reserved_at_1f8[0x4]; 2194 u8 log_headers_buffer_entry_num[0x4]; 2195 2196 u8 reserved_at_200[0x400]; 2197 2198 struct mlx5_ifc_cmd_pas_bits pas[]; 2199 }; 2200 2201 struct mlx5_ifc_rq_num_bits { 2202 u8 reserved_at_0[0x8]; 2203 u8 rq_num[0x18]; 2204 }; 2205 2206 struct mlx5_ifc_rq_vhca_bits { 2207 u8 reserved_at_0[0x8]; 2208 u8 rq_num[0x18]; 2209 u8 reserved_at_20[0x10]; 2210 u8 rq_vhca_id[0x10]; 2211 }; 2212 2213 struct mlx5_ifc_mac_address_layout_bits { 2214 u8 reserved_at_0[0x10]; 2215 u8 mac_addr_47_32[0x10]; 2216 2217 u8 mac_addr_31_0[0x20]; 2218 }; 2219 2220 struct mlx5_ifc_vlan_layout_bits { 2221 u8 reserved_at_0[0x14]; 2222 u8 vlan[0x0c]; 2223 2224 u8 reserved_at_20[0x20]; 2225 }; 2226 2227 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits { 2228 u8 reserved_at_0[0xa0]; 2229 2230 u8 min_time_between_cnps[0x20]; 2231 2232 u8 reserved_at_c0[0x12]; 2233 u8 cnp_dscp[0x6]; 2234 u8 reserved_at_d8[0x4]; 2235 u8 cnp_prio_mode[0x1]; 2236 u8 cnp_802p_prio[0x3]; 2237 2238 u8 reserved_at_e0[0x720]; 2239 }; 2240 2241 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits { 2242 u8 reserved_at_0[0x60]; 2243 2244 u8 reserved_at_60[0x4]; 2245 u8 clamp_tgt_rate[0x1]; 2246 u8 reserved_at_65[0x3]; 2247 u8 clamp_tgt_rate_after_time_inc[0x1]; 2248 u8 reserved_at_69[0x17]; 2249 2250 u8 reserved_at_80[0x20]; 2251 2252 u8 rpg_time_reset[0x20]; 2253 2254 u8 rpg_byte_reset[0x20]; 2255 2256 u8 rpg_threshold[0x20]; 2257 2258 u8 rpg_max_rate[0x20]; 2259 2260 u8 rpg_ai_rate[0x20]; 2261 2262 u8 rpg_hai_rate[0x20]; 2263 2264 u8 rpg_gd[0x20]; 2265 2266 u8 rpg_min_dec_fac[0x20]; 2267 2268 u8 rpg_min_rate[0x20]; 2269 2270 u8 reserved_at_1c0[0xe0]; 2271 2272 u8 rate_to_set_on_first_cnp[0x20]; 2273 2274 u8 dce_tcp_g[0x20]; 2275 2276 u8 dce_tcp_rtt[0x20]; 2277 2278 u8 rate_reduce_monitor_period[0x20]; 2279 2280 u8 reserved_at_320[0x20]; 2281 2282 u8 initial_alpha_value[0x20]; 2283 2284 u8 reserved_at_360[0x4a0]; 2285 }; 2286 2287 struct mlx5_ifc_cong_control_r_roce_general_bits { 2288 u8 reserved_at_0[0x80]; 2289 2290 u8 reserved_at_80[0x10]; 2291 u8 rtt_resp_dscp_valid[0x1]; 2292 u8 reserved_at_91[0x9]; 2293 u8 rtt_resp_dscp[0x6]; 2294 2295 u8 reserved_at_a0[0x760]; 2296 }; 2297 2298 struct mlx5_ifc_cong_control_802_1qau_rp_bits { 2299 u8 reserved_at_0[0x80]; 2300 2301 u8 rppp_max_rps[0x20]; 2302 2303 u8 rpg_time_reset[0x20]; 2304 2305 u8 rpg_byte_reset[0x20]; 2306 2307 u8 rpg_threshold[0x20]; 2308 2309 u8 rpg_max_rate[0x20]; 2310 2311 u8 rpg_ai_rate[0x20]; 2312 2313 u8 rpg_hai_rate[0x20]; 2314 2315 u8 rpg_gd[0x20]; 2316 2317 u8 rpg_min_dec_fac[0x20]; 2318 2319 u8 rpg_min_rate[0x20]; 2320 2321 u8 reserved_at_1c0[0x640]; 2322 }; 2323 2324 enum { 2325 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1, 2326 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2, 2327 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4, 2328 }; 2329 2330 struct mlx5_ifc_resize_field_select_bits { 2331 u8 resize_field_select[0x20]; 2332 }; 2333 2334 struct mlx5_ifc_resource_dump_bits { 2335 u8 more_dump[0x1]; 2336 u8 inline_dump[0x1]; 2337 u8 reserved_at_2[0xa]; 2338 u8 seq_num[0x4]; 2339 u8 segment_type[0x10]; 2340 2341 u8 reserved_at_20[0x10]; 2342 u8 vhca_id[0x10]; 2343 2344 u8 index1[0x20]; 2345 2346 u8 index2[0x20]; 2347 2348 u8 num_of_obj1[0x10]; 2349 u8 num_of_obj2[0x10]; 2350 2351 u8 reserved_at_a0[0x20]; 2352 2353 u8 device_opaque[0x40]; 2354 2355 u8 mkey[0x20]; 2356 2357 u8 size[0x20]; 2358 2359 u8 address[0x40]; 2360 2361 u8 inline_data[52][0x20]; 2362 }; 2363 2364 struct mlx5_ifc_resource_dump_menu_record_bits { 2365 u8 reserved_at_0[0x4]; 2366 u8 num_of_obj2_supports_active[0x1]; 2367 u8 num_of_obj2_supports_all[0x1]; 2368 u8 must_have_num_of_obj2[0x1]; 2369 u8 support_num_of_obj2[0x1]; 2370 u8 num_of_obj1_supports_active[0x1]; 2371 u8 num_of_obj1_supports_all[0x1]; 2372 u8 must_have_num_of_obj1[0x1]; 2373 u8 support_num_of_obj1[0x1]; 2374 u8 must_have_index2[0x1]; 2375 u8 support_index2[0x1]; 2376 u8 must_have_index1[0x1]; 2377 u8 support_index1[0x1]; 2378 u8 segment_type[0x10]; 2379 2380 u8 segment_name[4][0x20]; 2381 2382 u8 index1_name[4][0x20]; 2383 2384 u8 index2_name[4][0x20]; 2385 }; 2386 2387 struct mlx5_ifc_resource_dump_segment_header_bits { 2388 u8 length_dw[0x10]; 2389 u8 segment_type[0x10]; 2390 }; 2391 2392 struct mlx5_ifc_resource_dump_command_segment_bits { 2393 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2394 2395 u8 segment_called[0x10]; 2396 u8 vhca_id[0x10]; 2397 2398 u8 index1[0x20]; 2399 2400 u8 index2[0x20]; 2401 2402 u8 num_of_obj1[0x10]; 2403 u8 num_of_obj2[0x10]; 2404 }; 2405 2406 struct mlx5_ifc_resource_dump_error_segment_bits { 2407 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2408 2409 u8 reserved_at_20[0x10]; 2410 u8 syndrome_id[0x10]; 2411 2412 u8 reserved_at_40[0x40]; 2413 2414 u8 error[8][0x20]; 2415 }; 2416 2417 struct mlx5_ifc_resource_dump_info_segment_bits { 2418 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2419 2420 u8 reserved_at_20[0x18]; 2421 u8 dump_version[0x8]; 2422 2423 u8 hw_version[0x20]; 2424 2425 u8 fw_version[0x20]; 2426 }; 2427 2428 struct mlx5_ifc_resource_dump_menu_segment_bits { 2429 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2430 2431 u8 reserved_at_20[0x10]; 2432 u8 num_of_records[0x10]; 2433 2434 struct mlx5_ifc_resource_dump_menu_record_bits record[]; 2435 }; 2436 2437 struct mlx5_ifc_resource_dump_resource_segment_bits { 2438 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2439 2440 u8 reserved_at_20[0x20]; 2441 2442 u8 index1[0x20]; 2443 2444 u8 index2[0x20]; 2445 2446 u8 payload[][0x20]; 2447 }; 2448 2449 struct mlx5_ifc_resource_dump_terminate_segment_bits { 2450 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2451 }; 2452 2453 struct mlx5_ifc_menu_resource_dump_response_bits { 2454 struct mlx5_ifc_resource_dump_info_segment_bits info; 2455 struct mlx5_ifc_resource_dump_command_segment_bits cmd; 2456 struct mlx5_ifc_resource_dump_menu_segment_bits menu; 2457 struct mlx5_ifc_resource_dump_terminate_segment_bits terminate; 2458 }; 2459 2460 enum { 2461 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1, 2462 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2, 2463 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4, 2464 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8, 2465 }; 2466 2467 struct mlx5_ifc_modify_field_select_bits { 2468 u8 modify_field_select[0x20]; 2469 }; 2470 2471 struct mlx5_ifc_field_select_r_roce_np_bits { 2472 u8 field_select_r_roce_np[0x20]; 2473 }; 2474 2475 struct mlx5_ifc_field_select_r_roce_rp_bits { 2476 u8 field_select_r_roce_rp[0x20]; 2477 }; 2478 2479 enum { 2480 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4, 2481 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8, 2482 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10, 2483 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20, 2484 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40, 2485 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80, 2486 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100, 2487 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200, 2488 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400, 2489 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800, 2490 }; 2491 2492 struct mlx5_ifc_field_select_802_1qau_rp_bits { 2493 u8 field_select_8021qaurp[0x20]; 2494 }; 2495 2496 struct mlx5_ifc_phys_layer_cntrs_bits { 2497 u8 time_since_last_clear_high[0x20]; 2498 2499 u8 time_since_last_clear_low[0x20]; 2500 2501 u8 symbol_errors_high[0x20]; 2502 2503 u8 symbol_errors_low[0x20]; 2504 2505 u8 sync_headers_errors_high[0x20]; 2506 2507 u8 sync_headers_errors_low[0x20]; 2508 2509 u8 edpl_bip_errors_lane0_high[0x20]; 2510 2511 u8 edpl_bip_errors_lane0_low[0x20]; 2512 2513 u8 edpl_bip_errors_lane1_high[0x20]; 2514 2515 u8 edpl_bip_errors_lane1_low[0x20]; 2516 2517 u8 edpl_bip_errors_lane2_high[0x20]; 2518 2519 u8 edpl_bip_errors_lane2_low[0x20]; 2520 2521 u8 edpl_bip_errors_lane3_high[0x20]; 2522 2523 u8 edpl_bip_errors_lane3_low[0x20]; 2524 2525 u8 fc_fec_corrected_blocks_lane0_high[0x20]; 2526 2527 u8 fc_fec_corrected_blocks_lane0_low[0x20]; 2528 2529 u8 fc_fec_corrected_blocks_lane1_high[0x20]; 2530 2531 u8 fc_fec_corrected_blocks_lane1_low[0x20]; 2532 2533 u8 fc_fec_corrected_blocks_lane2_high[0x20]; 2534 2535 u8 fc_fec_corrected_blocks_lane2_low[0x20]; 2536 2537 u8 fc_fec_corrected_blocks_lane3_high[0x20]; 2538 2539 u8 fc_fec_corrected_blocks_lane3_low[0x20]; 2540 2541 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20]; 2542 2543 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20]; 2544 2545 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20]; 2546 2547 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20]; 2548 2549 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20]; 2550 2551 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20]; 2552 2553 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20]; 2554 2555 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20]; 2556 2557 u8 rs_fec_corrected_blocks_high[0x20]; 2558 2559 u8 rs_fec_corrected_blocks_low[0x20]; 2560 2561 u8 rs_fec_uncorrectable_blocks_high[0x20]; 2562 2563 u8 rs_fec_uncorrectable_blocks_low[0x20]; 2564 2565 u8 rs_fec_no_errors_blocks_high[0x20]; 2566 2567 u8 rs_fec_no_errors_blocks_low[0x20]; 2568 2569 u8 rs_fec_single_error_blocks_high[0x20]; 2570 2571 u8 rs_fec_single_error_blocks_low[0x20]; 2572 2573 u8 rs_fec_corrected_symbols_total_high[0x20]; 2574 2575 u8 rs_fec_corrected_symbols_total_low[0x20]; 2576 2577 u8 rs_fec_corrected_symbols_lane0_high[0x20]; 2578 2579 u8 rs_fec_corrected_symbols_lane0_low[0x20]; 2580 2581 u8 rs_fec_corrected_symbols_lane1_high[0x20]; 2582 2583 u8 rs_fec_corrected_symbols_lane1_low[0x20]; 2584 2585 u8 rs_fec_corrected_symbols_lane2_high[0x20]; 2586 2587 u8 rs_fec_corrected_symbols_lane2_low[0x20]; 2588 2589 u8 rs_fec_corrected_symbols_lane3_high[0x20]; 2590 2591 u8 rs_fec_corrected_symbols_lane3_low[0x20]; 2592 2593 u8 link_down_events[0x20]; 2594 2595 u8 successful_recovery_events[0x20]; 2596 2597 u8 reserved_at_640[0x180]; 2598 }; 2599 2600 struct mlx5_ifc_phys_layer_statistical_cntrs_bits { 2601 u8 time_since_last_clear_high[0x20]; 2602 2603 u8 time_since_last_clear_low[0x20]; 2604 2605 u8 phy_received_bits_high[0x20]; 2606 2607 u8 phy_received_bits_low[0x20]; 2608 2609 u8 phy_symbol_errors_high[0x20]; 2610 2611 u8 phy_symbol_errors_low[0x20]; 2612 2613 u8 phy_corrected_bits_high[0x20]; 2614 2615 u8 phy_corrected_bits_low[0x20]; 2616 2617 u8 phy_corrected_bits_lane0_high[0x20]; 2618 2619 u8 phy_corrected_bits_lane0_low[0x20]; 2620 2621 u8 phy_corrected_bits_lane1_high[0x20]; 2622 2623 u8 phy_corrected_bits_lane1_low[0x20]; 2624 2625 u8 phy_corrected_bits_lane2_high[0x20]; 2626 2627 u8 phy_corrected_bits_lane2_low[0x20]; 2628 2629 u8 phy_corrected_bits_lane3_high[0x20]; 2630 2631 u8 phy_corrected_bits_lane3_low[0x20]; 2632 2633 u8 reserved_at_200[0x5c0]; 2634 }; 2635 2636 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits { 2637 u8 symbol_error_counter[0x10]; 2638 2639 u8 link_error_recovery_counter[0x8]; 2640 2641 u8 link_downed_counter[0x8]; 2642 2643 u8 port_rcv_errors[0x10]; 2644 2645 u8 port_rcv_remote_physical_errors[0x10]; 2646 2647 u8 port_rcv_switch_relay_errors[0x10]; 2648 2649 u8 port_xmit_discards[0x10]; 2650 2651 u8 port_xmit_constraint_errors[0x8]; 2652 2653 u8 port_rcv_constraint_errors[0x8]; 2654 2655 u8 reserved_at_70[0x8]; 2656 2657 u8 link_overrun_errors[0x8]; 2658 2659 u8 reserved_at_80[0x10]; 2660 2661 u8 vl_15_dropped[0x10]; 2662 2663 u8 reserved_at_a0[0x80]; 2664 2665 u8 port_xmit_wait[0x20]; 2666 }; 2667 2668 struct mlx5_ifc_ib_ext_port_cntrs_grp_data_layout_bits { 2669 u8 reserved_at_0[0x300]; 2670 2671 u8 port_xmit_data_high[0x20]; 2672 2673 u8 port_xmit_data_low[0x20]; 2674 2675 u8 port_rcv_data_high[0x20]; 2676 2677 u8 port_rcv_data_low[0x20]; 2678 2679 u8 port_xmit_pkts_high[0x20]; 2680 2681 u8 port_xmit_pkts_low[0x20]; 2682 2683 u8 port_rcv_pkts_high[0x20]; 2684 2685 u8 port_rcv_pkts_low[0x20]; 2686 2687 u8 reserved_at_400[0x80]; 2688 2689 u8 port_unicast_xmit_pkts_high[0x20]; 2690 2691 u8 port_unicast_xmit_pkts_low[0x20]; 2692 2693 u8 port_multicast_xmit_pkts_high[0x20]; 2694 2695 u8 port_multicast_xmit_pkts_low[0x20]; 2696 2697 u8 port_unicast_rcv_pkts_high[0x20]; 2698 2699 u8 port_unicast_rcv_pkts_low[0x20]; 2700 2701 u8 port_multicast_rcv_pkts_high[0x20]; 2702 2703 u8 port_multicast_rcv_pkts_low[0x20]; 2704 2705 u8 reserved_at_580[0x240]; 2706 }; 2707 2708 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits { 2709 u8 transmit_queue_high[0x20]; 2710 2711 u8 transmit_queue_low[0x20]; 2712 2713 u8 no_buffer_discard_uc_high[0x20]; 2714 2715 u8 no_buffer_discard_uc_low[0x20]; 2716 2717 u8 reserved_at_80[0x740]; 2718 }; 2719 2720 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits { 2721 u8 wred_discard_high[0x20]; 2722 2723 u8 wred_discard_low[0x20]; 2724 2725 u8 ecn_marked_tc_high[0x20]; 2726 2727 u8 ecn_marked_tc_low[0x20]; 2728 2729 u8 reserved_at_80[0x740]; 2730 }; 2731 2732 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits { 2733 u8 rx_octets_high[0x20]; 2734 2735 u8 rx_octets_low[0x20]; 2736 2737 u8 reserved_at_40[0xc0]; 2738 2739 u8 rx_frames_high[0x20]; 2740 2741 u8 rx_frames_low[0x20]; 2742 2743 u8 tx_octets_high[0x20]; 2744 2745 u8 tx_octets_low[0x20]; 2746 2747 u8 reserved_at_180[0xc0]; 2748 2749 u8 tx_frames_high[0x20]; 2750 2751 u8 tx_frames_low[0x20]; 2752 2753 u8 rx_pause_high[0x20]; 2754 2755 u8 rx_pause_low[0x20]; 2756 2757 u8 rx_pause_duration_high[0x20]; 2758 2759 u8 rx_pause_duration_low[0x20]; 2760 2761 u8 tx_pause_high[0x20]; 2762 2763 u8 tx_pause_low[0x20]; 2764 2765 u8 tx_pause_duration_high[0x20]; 2766 2767 u8 tx_pause_duration_low[0x20]; 2768 2769 u8 rx_pause_transition_high[0x20]; 2770 2771 u8 rx_pause_transition_low[0x20]; 2772 2773 u8 rx_discards_high[0x20]; 2774 2775 u8 rx_discards_low[0x20]; 2776 2777 u8 device_stall_minor_watermark_cnt_high[0x20]; 2778 2779 u8 device_stall_minor_watermark_cnt_low[0x20]; 2780 2781 u8 device_stall_critical_watermark_cnt_high[0x20]; 2782 2783 u8 device_stall_critical_watermark_cnt_low[0x20]; 2784 2785 u8 reserved_at_480[0x340]; 2786 }; 2787 2788 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits { 2789 u8 port_transmit_wait_high[0x20]; 2790 2791 u8 port_transmit_wait_low[0x20]; 2792 2793 u8 reserved_at_40[0x100]; 2794 2795 u8 rx_buffer_almost_full_high[0x20]; 2796 2797 u8 rx_buffer_almost_full_low[0x20]; 2798 2799 u8 rx_buffer_full_high[0x20]; 2800 2801 u8 rx_buffer_full_low[0x20]; 2802 2803 u8 rx_icrc_encapsulated_high[0x20]; 2804 2805 u8 rx_icrc_encapsulated_low[0x20]; 2806 2807 u8 reserved_at_200[0x5c0]; 2808 }; 2809 2810 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits { 2811 u8 dot3stats_alignment_errors_high[0x20]; 2812 2813 u8 dot3stats_alignment_errors_low[0x20]; 2814 2815 u8 dot3stats_fcs_errors_high[0x20]; 2816 2817 u8 dot3stats_fcs_errors_low[0x20]; 2818 2819 u8 dot3stats_single_collision_frames_high[0x20]; 2820 2821 u8 dot3stats_single_collision_frames_low[0x20]; 2822 2823 u8 dot3stats_multiple_collision_frames_high[0x20]; 2824 2825 u8 dot3stats_multiple_collision_frames_low[0x20]; 2826 2827 u8 dot3stats_sqe_test_errors_high[0x20]; 2828 2829 u8 dot3stats_sqe_test_errors_low[0x20]; 2830 2831 u8 dot3stats_deferred_transmissions_high[0x20]; 2832 2833 u8 dot3stats_deferred_transmissions_low[0x20]; 2834 2835 u8 dot3stats_late_collisions_high[0x20]; 2836 2837 u8 dot3stats_late_collisions_low[0x20]; 2838 2839 u8 dot3stats_excessive_collisions_high[0x20]; 2840 2841 u8 dot3stats_excessive_collisions_low[0x20]; 2842 2843 u8 dot3stats_internal_mac_transmit_errors_high[0x20]; 2844 2845 u8 dot3stats_internal_mac_transmit_errors_low[0x20]; 2846 2847 u8 dot3stats_carrier_sense_errors_high[0x20]; 2848 2849 u8 dot3stats_carrier_sense_errors_low[0x20]; 2850 2851 u8 dot3stats_frame_too_longs_high[0x20]; 2852 2853 u8 dot3stats_frame_too_longs_low[0x20]; 2854 2855 u8 dot3stats_internal_mac_receive_errors_high[0x20]; 2856 2857 u8 dot3stats_internal_mac_receive_errors_low[0x20]; 2858 2859 u8 dot3stats_symbol_errors_high[0x20]; 2860 2861 u8 dot3stats_symbol_errors_low[0x20]; 2862 2863 u8 dot3control_in_unknown_opcodes_high[0x20]; 2864 2865 u8 dot3control_in_unknown_opcodes_low[0x20]; 2866 2867 u8 dot3in_pause_frames_high[0x20]; 2868 2869 u8 dot3in_pause_frames_low[0x20]; 2870 2871 u8 dot3out_pause_frames_high[0x20]; 2872 2873 u8 dot3out_pause_frames_low[0x20]; 2874 2875 u8 reserved_at_400[0x3c0]; 2876 }; 2877 2878 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits { 2879 u8 ether_stats_drop_events_high[0x20]; 2880 2881 u8 ether_stats_drop_events_low[0x20]; 2882 2883 u8 ether_stats_octets_high[0x20]; 2884 2885 u8 ether_stats_octets_low[0x20]; 2886 2887 u8 ether_stats_pkts_high[0x20]; 2888 2889 u8 ether_stats_pkts_low[0x20]; 2890 2891 u8 ether_stats_broadcast_pkts_high[0x20]; 2892 2893 u8 ether_stats_broadcast_pkts_low[0x20]; 2894 2895 u8 ether_stats_multicast_pkts_high[0x20]; 2896 2897 u8 ether_stats_multicast_pkts_low[0x20]; 2898 2899 u8 ether_stats_crc_align_errors_high[0x20]; 2900 2901 u8 ether_stats_crc_align_errors_low[0x20]; 2902 2903 u8 ether_stats_undersize_pkts_high[0x20]; 2904 2905 u8 ether_stats_undersize_pkts_low[0x20]; 2906 2907 u8 ether_stats_oversize_pkts_high[0x20]; 2908 2909 u8 ether_stats_oversize_pkts_low[0x20]; 2910 2911 u8 ether_stats_fragments_high[0x20]; 2912 2913 u8 ether_stats_fragments_low[0x20]; 2914 2915 u8 ether_stats_jabbers_high[0x20]; 2916 2917 u8 ether_stats_jabbers_low[0x20]; 2918 2919 u8 ether_stats_collisions_high[0x20]; 2920 2921 u8 ether_stats_collisions_low[0x20]; 2922 2923 u8 ether_stats_pkts64octets_high[0x20]; 2924 2925 u8 ether_stats_pkts64octets_low[0x20]; 2926 2927 u8 ether_stats_pkts65to127octets_high[0x20]; 2928 2929 u8 ether_stats_pkts65to127octets_low[0x20]; 2930 2931 u8 ether_stats_pkts128to255octets_high[0x20]; 2932 2933 u8 ether_stats_pkts128to255octets_low[0x20]; 2934 2935 u8 ether_stats_pkts256to511octets_high[0x20]; 2936 2937 u8 ether_stats_pkts256to511octets_low[0x20]; 2938 2939 u8 ether_stats_pkts512to1023octets_high[0x20]; 2940 2941 u8 ether_stats_pkts512to1023octets_low[0x20]; 2942 2943 u8 ether_stats_pkts1024to1518octets_high[0x20]; 2944 2945 u8 ether_stats_pkts1024to1518octets_low[0x20]; 2946 2947 u8 ether_stats_pkts1519to2047octets_high[0x20]; 2948 2949 u8 ether_stats_pkts1519to2047octets_low[0x20]; 2950 2951 u8 ether_stats_pkts2048to4095octets_high[0x20]; 2952 2953 u8 ether_stats_pkts2048to4095octets_low[0x20]; 2954 2955 u8 ether_stats_pkts4096to8191octets_high[0x20]; 2956 2957 u8 ether_stats_pkts4096to8191octets_low[0x20]; 2958 2959 u8 ether_stats_pkts8192to10239octets_high[0x20]; 2960 2961 u8 ether_stats_pkts8192to10239octets_low[0x20]; 2962 2963 u8 reserved_at_540[0x280]; 2964 }; 2965 2966 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits { 2967 u8 if_in_octets_high[0x20]; 2968 2969 u8 if_in_octets_low[0x20]; 2970 2971 u8 if_in_ucast_pkts_high[0x20]; 2972 2973 u8 if_in_ucast_pkts_low[0x20]; 2974 2975 u8 if_in_discards_high[0x20]; 2976 2977 u8 if_in_discards_low[0x20]; 2978 2979 u8 if_in_errors_high[0x20]; 2980 2981 u8 if_in_errors_low[0x20]; 2982 2983 u8 if_in_unknown_protos_high[0x20]; 2984 2985 u8 if_in_unknown_protos_low[0x20]; 2986 2987 u8 if_out_octets_high[0x20]; 2988 2989 u8 if_out_octets_low[0x20]; 2990 2991 u8 if_out_ucast_pkts_high[0x20]; 2992 2993 u8 if_out_ucast_pkts_low[0x20]; 2994 2995 u8 if_out_discards_high[0x20]; 2996 2997 u8 if_out_discards_low[0x20]; 2998 2999 u8 if_out_errors_high[0x20]; 3000 3001 u8 if_out_errors_low[0x20]; 3002 3003 u8 if_in_multicast_pkts_high[0x20]; 3004 3005 u8 if_in_multicast_pkts_low[0x20]; 3006 3007 u8 if_in_broadcast_pkts_high[0x20]; 3008 3009 u8 if_in_broadcast_pkts_low[0x20]; 3010 3011 u8 if_out_multicast_pkts_high[0x20]; 3012 3013 u8 if_out_multicast_pkts_low[0x20]; 3014 3015 u8 if_out_broadcast_pkts_high[0x20]; 3016 3017 u8 if_out_broadcast_pkts_low[0x20]; 3018 3019 u8 reserved_at_340[0x480]; 3020 }; 3021 3022 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits { 3023 u8 a_frames_transmitted_ok_high[0x20]; 3024 3025 u8 a_frames_transmitted_ok_low[0x20]; 3026 3027 u8 a_frames_received_ok_high[0x20]; 3028 3029 u8 a_frames_received_ok_low[0x20]; 3030 3031 u8 a_frame_check_sequence_errors_high[0x20]; 3032 3033 u8 a_frame_check_sequence_errors_low[0x20]; 3034 3035 u8 a_alignment_errors_high[0x20]; 3036 3037 u8 a_alignment_errors_low[0x20]; 3038 3039 u8 a_octets_transmitted_ok_high[0x20]; 3040 3041 u8 a_octets_transmitted_ok_low[0x20]; 3042 3043 u8 a_octets_received_ok_high[0x20]; 3044 3045 u8 a_octets_received_ok_low[0x20]; 3046 3047 u8 a_multicast_frames_xmitted_ok_high[0x20]; 3048 3049 u8 a_multicast_frames_xmitted_ok_low[0x20]; 3050 3051 u8 a_broadcast_frames_xmitted_ok_high[0x20]; 3052 3053 u8 a_broadcast_frames_xmitted_ok_low[0x20]; 3054 3055 u8 a_multicast_frames_received_ok_high[0x20]; 3056 3057 u8 a_multicast_frames_received_ok_low[0x20]; 3058 3059 u8 a_broadcast_frames_received_ok_high[0x20]; 3060 3061 u8 a_broadcast_frames_received_ok_low[0x20]; 3062 3063 u8 a_in_range_length_errors_high[0x20]; 3064 3065 u8 a_in_range_length_errors_low[0x20]; 3066 3067 u8 a_out_of_range_length_field_high[0x20]; 3068 3069 u8 a_out_of_range_length_field_low[0x20]; 3070 3071 u8 a_frame_too_long_errors_high[0x20]; 3072 3073 u8 a_frame_too_long_errors_low[0x20]; 3074 3075 u8 a_symbol_error_during_carrier_high[0x20]; 3076 3077 u8 a_symbol_error_during_carrier_low[0x20]; 3078 3079 u8 a_mac_control_frames_transmitted_high[0x20]; 3080 3081 u8 a_mac_control_frames_transmitted_low[0x20]; 3082 3083 u8 a_mac_control_frames_received_high[0x20]; 3084 3085 u8 a_mac_control_frames_received_low[0x20]; 3086 3087 u8 a_unsupported_opcodes_received_high[0x20]; 3088 3089 u8 a_unsupported_opcodes_received_low[0x20]; 3090 3091 u8 a_pause_mac_ctrl_frames_received_high[0x20]; 3092 3093 u8 a_pause_mac_ctrl_frames_received_low[0x20]; 3094 3095 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20]; 3096 3097 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20]; 3098 3099 u8 reserved_at_4c0[0x300]; 3100 }; 3101 3102 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits { 3103 u8 life_time_counter_high[0x20]; 3104 3105 u8 life_time_counter_low[0x20]; 3106 3107 u8 rx_errors[0x20]; 3108 3109 u8 tx_errors[0x20]; 3110 3111 u8 l0_to_recovery_eieos[0x20]; 3112 3113 u8 l0_to_recovery_ts[0x20]; 3114 3115 u8 l0_to_recovery_framing[0x20]; 3116 3117 u8 l0_to_recovery_retrain[0x20]; 3118 3119 u8 crc_error_dllp[0x20]; 3120 3121 u8 crc_error_tlp[0x20]; 3122 3123 u8 tx_overflow_buffer_pkt_high[0x20]; 3124 3125 u8 tx_overflow_buffer_pkt_low[0x20]; 3126 3127 u8 outbound_stalled_reads[0x20]; 3128 3129 u8 outbound_stalled_writes[0x20]; 3130 3131 u8 outbound_stalled_reads_events[0x20]; 3132 3133 u8 outbound_stalled_writes_events[0x20]; 3134 3135 u8 reserved_at_200[0x5c0]; 3136 }; 3137 3138 struct mlx5_ifc_cmd_inter_comp_event_bits { 3139 u8 command_completion_vector[0x20]; 3140 3141 u8 reserved_at_20[0xc0]; 3142 }; 3143 3144 struct mlx5_ifc_stall_vl_event_bits { 3145 u8 reserved_at_0[0x18]; 3146 u8 port_num[0x1]; 3147 u8 reserved_at_19[0x3]; 3148 u8 vl[0x4]; 3149 3150 u8 reserved_at_20[0xa0]; 3151 }; 3152 3153 struct mlx5_ifc_db_bf_congestion_event_bits { 3154 u8 event_subtype[0x8]; 3155 u8 reserved_at_8[0x8]; 3156 u8 congestion_level[0x8]; 3157 u8 reserved_at_18[0x8]; 3158 3159 u8 reserved_at_20[0xa0]; 3160 }; 3161 3162 struct mlx5_ifc_gpio_event_bits { 3163 u8 reserved_at_0[0x60]; 3164 3165 u8 gpio_event_hi[0x20]; 3166 3167 u8 gpio_event_lo[0x20]; 3168 3169 u8 reserved_at_a0[0x40]; 3170 }; 3171 3172 struct mlx5_ifc_port_state_change_event_bits { 3173 u8 reserved_at_0[0x40]; 3174 3175 u8 port_num[0x4]; 3176 u8 reserved_at_44[0x1c]; 3177 3178 u8 reserved_at_60[0x80]; 3179 }; 3180 3181 struct mlx5_ifc_dropped_packet_logged_bits { 3182 u8 reserved_at_0[0xe0]; 3183 }; 3184 3185 struct mlx5_ifc_default_timeout_bits { 3186 u8 to_multiplier[0x3]; 3187 u8 reserved_at_3[0x9]; 3188 u8 to_value[0x14]; 3189 }; 3190 3191 struct mlx5_ifc_dtor_reg_bits { 3192 u8 reserved_at_0[0x20]; 3193 3194 struct mlx5_ifc_default_timeout_bits pcie_toggle_to; 3195 3196 u8 reserved_at_40[0x60]; 3197 3198 struct mlx5_ifc_default_timeout_bits health_poll_to; 3199 3200 struct mlx5_ifc_default_timeout_bits full_crdump_to; 3201 3202 struct mlx5_ifc_default_timeout_bits fw_reset_to; 3203 3204 struct mlx5_ifc_default_timeout_bits flush_on_err_to; 3205 3206 struct mlx5_ifc_default_timeout_bits pci_sync_update_to; 3207 3208 struct mlx5_ifc_default_timeout_bits tear_down_to; 3209 3210 struct mlx5_ifc_default_timeout_bits fsm_reactivate_to; 3211 3212 struct mlx5_ifc_default_timeout_bits reclaim_pages_to; 3213 3214 struct mlx5_ifc_default_timeout_bits reclaim_vfs_pages_to; 3215 3216 struct mlx5_ifc_default_timeout_bits reset_unload_to; 3217 3218 u8 reserved_at_1c0[0x20]; 3219 }; 3220 3221 enum { 3222 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1, 3223 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2, 3224 }; 3225 3226 struct mlx5_ifc_cq_error_bits { 3227 u8 reserved_at_0[0x8]; 3228 u8 cqn[0x18]; 3229 3230 u8 reserved_at_20[0x20]; 3231 3232 u8 reserved_at_40[0x18]; 3233 u8 syndrome[0x8]; 3234 3235 u8 reserved_at_60[0x80]; 3236 }; 3237 3238 struct mlx5_ifc_rdma_page_fault_event_bits { 3239 u8 bytes_committed[0x20]; 3240 3241 u8 r_key[0x20]; 3242 3243 u8 reserved_at_40[0x10]; 3244 u8 packet_len[0x10]; 3245 3246 u8 rdma_op_len[0x20]; 3247 3248 u8 rdma_va[0x40]; 3249 3250 u8 reserved_at_c0[0x5]; 3251 u8 rdma[0x1]; 3252 u8 write[0x1]; 3253 u8 requestor[0x1]; 3254 u8 qp_number[0x18]; 3255 }; 3256 3257 struct mlx5_ifc_wqe_associated_page_fault_event_bits { 3258 u8 bytes_committed[0x20]; 3259 3260 u8 reserved_at_20[0x10]; 3261 u8 wqe_index[0x10]; 3262 3263 u8 reserved_at_40[0x10]; 3264 u8 len[0x10]; 3265 3266 u8 reserved_at_60[0x60]; 3267 3268 u8 reserved_at_c0[0x5]; 3269 u8 rdma[0x1]; 3270 u8 write_read[0x1]; 3271 u8 requestor[0x1]; 3272 u8 qpn[0x18]; 3273 }; 3274 3275 struct mlx5_ifc_qp_events_bits { 3276 u8 reserved_at_0[0xa0]; 3277 3278 u8 type[0x8]; 3279 u8 reserved_at_a8[0x18]; 3280 3281 u8 reserved_at_c0[0x8]; 3282 u8 qpn_rqn_sqn[0x18]; 3283 }; 3284 3285 struct mlx5_ifc_dct_events_bits { 3286 u8 reserved_at_0[0xc0]; 3287 3288 u8 reserved_at_c0[0x8]; 3289 u8 dct_number[0x18]; 3290 }; 3291 3292 struct mlx5_ifc_comp_event_bits { 3293 u8 reserved_at_0[0xc0]; 3294 3295 u8 reserved_at_c0[0x8]; 3296 u8 cq_number[0x18]; 3297 }; 3298 3299 enum { 3300 MLX5_QPC_STATE_RST = 0x0, 3301 MLX5_QPC_STATE_INIT = 0x1, 3302 MLX5_QPC_STATE_RTR = 0x2, 3303 MLX5_QPC_STATE_RTS = 0x3, 3304 MLX5_QPC_STATE_SQER = 0x4, 3305 MLX5_QPC_STATE_ERR = 0x6, 3306 MLX5_QPC_STATE_SQD = 0x7, 3307 MLX5_QPC_STATE_SUSPENDED = 0x9, 3308 }; 3309 3310 enum { 3311 MLX5_QPC_ST_RC = 0x0, 3312 MLX5_QPC_ST_UC = 0x1, 3313 MLX5_QPC_ST_UD = 0x2, 3314 MLX5_QPC_ST_XRC = 0x3, 3315 MLX5_QPC_ST_DCI = 0x5, 3316 MLX5_QPC_ST_QP0 = 0x7, 3317 MLX5_QPC_ST_QP1 = 0x8, 3318 MLX5_QPC_ST_RAW_DATAGRAM = 0x9, 3319 MLX5_QPC_ST_REG_UMR = 0xc, 3320 }; 3321 3322 enum { 3323 MLX5_QPC_PM_STATE_ARMED = 0x0, 3324 MLX5_QPC_PM_STATE_REARM = 0x1, 3325 MLX5_QPC_PM_STATE_RESERVED = 0x2, 3326 MLX5_QPC_PM_STATE_MIGRATED = 0x3, 3327 }; 3328 3329 enum { 3330 MLX5_QPC_OFFLOAD_TYPE_RNDV = 0x1, 3331 }; 3332 3333 enum { 3334 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0, 3335 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1, 3336 }; 3337 3338 enum { 3339 MLX5_QPC_MTU_256_BYTES = 0x1, 3340 MLX5_QPC_MTU_512_BYTES = 0x2, 3341 MLX5_QPC_MTU_1K_BYTES = 0x3, 3342 MLX5_QPC_MTU_2K_BYTES = 0x4, 3343 MLX5_QPC_MTU_4K_BYTES = 0x5, 3344 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7, 3345 }; 3346 3347 enum { 3348 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1, 3349 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2, 3350 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3, 3351 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4, 3352 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5, 3353 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6, 3354 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7, 3355 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8, 3356 }; 3357 3358 enum { 3359 MLX5_QPC_CS_REQ_DISABLE = 0x0, 3360 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11, 3361 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22, 3362 }; 3363 3364 enum { 3365 MLX5_QPC_CS_RES_DISABLE = 0x0, 3366 MLX5_QPC_CS_RES_UP_TO_32B = 0x1, 3367 MLX5_QPC_CS_RES_UP_TO_64B = 0x2, 3368 }; 3369 3370 enum { 3371 MLX5_TIMESTAMP_FORMAT_FREE_RUNNING = 0x0, 3372 MLX5_TIMESTAMP_FORMAT_DEFAULT = 0x1, 3373 MLX5_TIMESTAMP_FORMAT_REAL_TIME = 0x2, 3374 }; 3375 3376 struct mlx5_ifc_qpc_bits { 3377 u8 state[0x4]; 3378 u8 lag_tx_port_affinity[0x4]; 3379 u8 st[0x8]; 3380 u8 reserved_at_10[0x2]; 3381 u8 isolate_vl_tc[0x1]; 3382 u8 pm_state[0x2]; 3383 u8 reserved_at_15[0x1]; 3384 u8 req_e2e_credit_mode[0x2]; 3385 u8 offload_type[0x4]; 3386 u8 end_padding_mode[0x2]; 3387 u8 reserved_at_1e[0x2]; 3388 3389 u8 wq_signature[0x1]; 3390 u8 block_lb_mc[0x1]; 3391 u8 atomic_like_write_en[0x1]; 3392 u8 latency_sensitive[0x1]; 3393 u8 reserved_at_24[0x1]; 3394 u8 drain_sigerr[0x1]; 3395 u8 reserved_at_26[0x2]; 3396 u8 pd[0x18]; 3397 3398 u8 mtu[0x3]; 3399 u8 log_msg_max[0x5]; 3400 u8 reserved_at_48[0x1]; 3401 u8 log_rq_size[0x4]; 3402 u8 log_rq_stride[0x3]; 3403 u8 no_sq[0x1]; 3404 u8 log_sq_size[0x4]; 3405 u8 reserved_at_55[0x1]; 3406 u8 retry_mode[0x2]; 3407 u8 ts_format[0x2]; 3408 u8 reserved_at_5a[0x1]; 3409 u8 rlky[0x1]; 3410 u8 ulp_stateless_offload_mode[0x4]; 3411 3412 u8 counter_set_id[0x8]; 3413 u8 uar_page[0x18]; 3414 3415 u8 reserved_at_80[0x8]; 3416 u8 user_index[0x18]; 3417 3418 u8 reserved_at_a0[0x3]; 3419 u8 log_page_size[0x5]; 3420 u8 remote_qpn[0x18]; 3421 3422 struct mlx5_ifc_ads_bits primary_address_path; 3423 3424 struct mlx5_ifc_ads_bits secondary_address_path; 3425 3426 u8 log_ack_req_freq[0x4]; 3427 u8 reserved_at_384[0x4]; 3428 u8 log_sra_max[0x3]; 3429 u8 reserved_at_38b[0x2]; 3430 u8 retry_count[0x3]; 3431 u8 rnr_retry[0x3]; 3432 u8 reserved_at_393[0x1]; 3433 u8 fre[0x1]; 3434 u8 cur_rnr_retry[0x3]; 3435 u8 cur_retry_count[0x3]; 3436 u8 reserved_at_39b[0x5]; 3437 3438 u8 reserved_at_3a0[0x20]; 3439 3440 u8 reserved_at_3c0[0x8]; 3441 u8 next_send_psn[0x18]; 3442 3443 u8 reserved_at_3e0[0x3]; 3444 u8 log_num_dci_stream_channels[0x5]; 3445 u8 cqn_snd[0x18]; 3446 3447 u8 reserved_at_400[0x3]; 3448 u8 log_num_dci_errored_streams[0x5]; 3449 u8 deth_sqpn[0x18]; 3450 3451 u8 reserved_at_420[0x20]; 3452 3453 u8 reserved_at_440[0x8]; 3454 u8 last_acked_psn[0x18]; 3455 3456 u8 reserved_at_460[0x8]; 3457 u8 ssn[0x18]; 3458 3459 u8 reserved_at_480[0x8]; 3460 u8 log_rra_max[0x3]; 3461 u8 reserved_at_48b[0x1]; 3462 u8 atomic_mode[0x4]; 3463 u8 rre[0x1]; 3464 u8 rwe[0x1]; 3465 u8 rae[0x1]; 3466 u8 reserved_at_493[0x1]; 3467 u8 page_offset[0x6]; 3468 u8 reserved_at_49a[0x3]; 3469 u8 cd_slave_receive[0x1]; 3470 u8 cd_slave_send[0x1]; 3471 u8 cd_master[0x1]; 3472 3473 u8 reserved_at_4a0[0x3]; 3474 u8 min_rnr_nak[0x5]; 3475 u8 next_rcv_psn[0x18]; 3476 3477 u8 reserved_at_4c0[0x8]; 3478 u8 xrcd[0x18]; 3479 3480 u8 reserved_at_4e0[0x8]; 3481 u8 cqn_rcv[0x18]; 3482 3483 u8 dbr_addr[0x40]; 3484 3485 u8 q_key[0x20]; 3486 3487 u8 reserved_at_560[0x5]; 3488 u8 rq_type[0x3]; 3489 u8 srqn_rmpn_xrqn[0x18]; 3490 3491 u8 reserved_at_580[0x8]; 3492 u8 rmsn[0x18]; 3493 3494 u8 hw_sq_wqebb_counter[0x10]; 3495 u8 sw_sq_wqebb_counter[0x10]; 3496 3497 u8 hw_rq_counter[0x20]; 3498 3499 u8 sw_rq_counter[0x20]; 3500 3501 u8 reserved_at_600[0x20]; 3502 3503 u8 reserved_at_620[0xf]; 3504 u8 cgs[0x1]; 3505 u8 cs_req[0x8]; 3506 u8 cs_res[0x8]; 3507 3508 u8 dc_access_key[0x40]; 3509 3510 u8 reserved_at_680[0x3]; 3511 u8 dbr_umem_valid[0x1]; 3512 3513 u8 reserved_at_684[0xbc]; 3514 }; 3515 3516 struct mlx5_ifc_roce_addr_layout_bits { 3517 u8 source_l3_address[16][0x8]; 3518 3519 u8 reserved_at_80[0x3]; 3520 u8 vlan_valid[0x1]; 3521 u8 vlan_id[0xc]; 3522 u8 source_mac_47_32[0x10]; 3523 3524 u8 source_mac_31_0[0x20]; 3525 3526 u8 reserved_at_c0[0x14]; 3527 u8 roce_l3_type[0x4]; 3528 u8 roce_version[0x8]; 3529 3530 u8 reserved_at_e0[0x20]; 3531 }; 3532 3533 struct mlx5_ifc_crypto_cap_bits { 3534 u8 reserved_at_0[0x3]; 3535 u8 synchronize_dek[0x1]; 3536 u8 int_kek_manual[0x1]; 3537 u8 int_kek_auto[0x1]; 3538 u8 reserved_at_6[0x1a]; 3539 3540 u8 reserved_at_20[0x3]; 3541 u8 log_dek_max_alloc[0x5]; 3542 u8 reserved_at_28[0x3]; 3543 u8 log_max_num_deks[0x5]; 3544 u8 reserved_at_30[0x10]; 3545 3546 u8 reserved_at_40[0x20]; 3547 3548 u8 reserved_at_60[0x3]; 3549 u8 log_dek_granularity[0x5]; 3550 u8 reserved_at_68[0x3]; 3551 u8 log_max_num_int_kek[0x5]; 3552 u8 sw_wrapped_dek[0x10]; 3553 3554 u8 reserved_at_80[0x780]; 3555 }; 3556 3557 union mlx5_ifc_hca_cap_union_bits { 3558 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap; 3559 struct mlx5_ifc_cmd_hca_cap_2_bits cmd_hca_cap_2; 3560 struct mlx5_ifc_odp_cap_bits odp_cap; 3561 struct mlx5_ifc_atomic_caps_bits atomic_caps; 3562 struct mlx5_ifc_roce_cap_bits roce_cap; 3563 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps; 3564 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap; 3565 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap; 3566 struct mlx5_ifc_e_switch_cap_bits e_switch_cap; 3567 struct mlx5_ifc_port_selection_cap_bits port_selection_cap; 3568 struct mlx5_ifc_qos_cap_bits qos_cap; 3569 struct mlx5_ifc_debug_cap_bits debug_cap; 3570 struct mlx5_ifc_fpga_cap_bits fpga_cap; 3571 struct mlx5_ifc_tls_cap_bits tls_cap; 3572 struct mlx5_ifc_device_mem_cap_bits device_mem_cap; 3573 struct mlx5_ifc_virtio_emulation_cap_bits virtio_emulation_cap; 3574 struct mlx5_ifc_macsec_cap_bits macsec_cap; 3575 struct mlx5_ifc_crypto_cap_bits crypto_cap; 3576 struct mlx5_ifc_ipsec_cap_bits ipsec_cap; 3577 u8 reserved_at_0[0x8000]; 3578 }; 3579 3580 enum { 3581 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1, 3582 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2, 3583 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4, 3584 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8, 3585 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT = 0x10, 3586 MLX5_FLOW_CONTEXT_ACTION_DECAP = 0x20, 3587 MLX5_FLOW_CONTEXT_ACTION_MOD_HDR = 0x40, 3588 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP = 0x80, 3589 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100, 3590 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2 = 0x400, 3591 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2 = 0x800, 3592 MLX5_FLOW_CONTEXT_ACTION_CRYPTO_DECRYPT = 0x1000, 3593 MLX5_FLOW_CONTEXT_ACTION_CRYPTO_ENCRYPT = 0x2000, 3594 MLX5_FLOW_CONTEXT_ACTION_EXECUTE_ASO = 0x4000, 3595 }; 3596 3597 enum { 3598 MLX5_FLOW_CONTEXT_FLOW_SOURCE_ANY_VPORT = 0x0, 3599 MLX5_FLOW_CONTEXT_FLOW_SOURCE_UPLINK = 0x1, 3600 MLX5_FLOW_CONTEXT_FLOW_SOURCE_LOCAL_VPORT = 0x2, 3601 }; 3602 3603 enum { 3604 MLX5_FLOW_CONTEXT_ENCRYPT_DECRYPT_TYPE_IPSEC = 0x0, 3605 MLX5_FLOW_CONTEXT_ENCRYPT_DECRYPT_TYPE_MACSEC = 0x1, 3606 }; 3607 3608 struct mlx5_ifc_vlan_bits { 3609 u8 ethtype[0x10]; 3610 u8 prio[0x3]; 3611 u8 cfi[0x1]; 3612 u8 vid[0xc]; 3613 }; 3614 3615 enum { 3616 MLX5_FLOW_METER_COLOR_RED = 0x0, 3617 MLX5_FLOW_METER_COLOR_YELLOW = 0x1, 3618 MLX5_FLOW_METER_COLOR_GREEN = 0x2, 3619 MLX5_FLOW_METER_COLOR_UNDEFINED = 0x3, 3620 }; 3621 3622 enum { 3623 MLX5_EXE_ASO_FLOW_METER = 0x2, 3624 }; 3625 3626 struct mlx5_ifc_exe_aso_ctrl_flow_meter_bits { 3627 u8 return_reg_id[0x4]; 3628 u8 aso_type[0x4]; 3629 u8 reserved_at_8[0x14]; 3630 u8 action[0x1]; 3631 u8 init_color[0x2]; 3632 u8 meter_id[0x1]; 3633 }; 3634 3635 union mlx5_ifc_exe_aso_ctrl { 3636 struct mlx5_ifc_exe_aso_ctrl_flow_meter_bits exe_aso_ctrl_flow_meter; 3637 }; 3638 3639 struct mlx5_ifc_execute_aso_bits { 3640 u8 valid[0x1]; 3641 u8 reserved_at_1[0x7]; 3642 u8 aso_object_id[0x18]; 3643 3644 union mlx5_ifc_exe_aso_ctrl exe_aso_ctrl; 3645 }; 3646 3647 struct mlx5_ifc_flow_context_bits { 3648 struct mlx5_ifc_vlan_bits push_vlan; 3649 3650 u8 group_id[0x20]; 3651 3652 u8 reserved_at_40[0x8]; 3653 u8 flow_tag[0x18]; 3654 3655 u8 reserved_at_60[0x10]; 3656 u8 action[0x10]; 3657 3658 u8 extended_destination[0x1]; 3659 u8 uplink_hairpin_en[0x1]; 3660 u8 flow_source[0x2]; 3661 u8 encrypt_decrypt_type[0x4]; 3662 u8 destination_list_size[0x18]; 3663 3664 u8 reserved_at_a0[0x8]; 3665 u8 flow_counter_list_size[0x18]; 3666 3667 u8 packet_reformat_id[0x20]; 3668 3669 u8 modify_header_id[0x20]; 3670 3671 struct mlx5_ifc_vlan_bits push_vlan_2; 3672 3673 u8 encrypt_decrypt_obj_id[0x20]; 3674 u8 reserved_at_140[0xc0]; 3675 3676 struct mlx5_ifc_fte_match_param_bits match_value; 3677 3678 struct mlx5_ifc_execute_aso_bits execute_aso[4]; 3679 3680 u8 reserved_at_1300[0x500]; 3681 3682 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[]; 3683 }; 3684 3685 enum { 3686 MLX5_XRC_SRQC_STATE_GOOD = 0x0, 3687 MLX5_XRC_SRQC_STATE_ERROR = 0x1, 3688 }; 3689 3690 struct mlx5_ifc_xrc_srqc_bits { 3691 u8 state[0x4]; 3692 u8 log_xrc_srq_size[0x4]; 3693 u8 reserved_at_8[0x18]; 3694 3695 u8 wq_signature[0x1]; 3696 u8 cont_srq[0x1]; 3697 u8 reserved_at_22[0x1]; 3698 u8 rlky[0x1]; 3699 u8 basic_cyclic_rcv_wqe[0x1]; 3700 u8 log_rq_stride[0x3]; 3701 u8 xrcd[0x18]; 3702 3703 u8 page_offset[0x6]; 3704 u8 reserved_at_46[0x1]; 3705 u8 dbr_umem_valid[0x1]; 3706 u8 cqn[0x18]; 3707 3708 u8 reserved_at_60[0x20]; 3709 3710 u8 user_index_equal_xrc_srqn[0x1]; 3711 u8 reserved_at_81[0x1]; 3712 u8 log_page_size[0x6]; 3713 u8 user_index[0x18]; 3714 3715 u8 reserved_at_a0[0x20]; 3716 3717 u8 reserved_at_c0[0x8]; 3718 u8 pd[0x18]; 3719 3720 u8 lwm[0x10]; 3721 u8 wqe_cnt[0x10]; 3722 3723 u8 reserved_at_100[0x40]; 3724 3725 u8 db_record_addr_h[0x20]; 3726 3727 u8 db_record_addr_l[0x1e]; 3728 u8 reserved_at_17e[0x2]; 3729 3730 u8 reserved_at_180[0x80]; 3731 }; 3732 3733 struct mlx5_ifc_vnic_diagnostic_statistics_bits { 3734 u8 counter_error_queues[0x20]; 3735 3736 u8 total_error_queues[0x20]; 3737 3738 u8 send_queue_priority_update_flow[0x20]; 3739 3740 u8 reserved_at_60[0x20]; 3741 3742 u8 nic_receive_steering_discard[0x40]; 3743 3744 u8 receive_discard_vport_down[0x40]; 3745 3746 u8 transmit_discard_vport_down[0x40]; 3747 3748 u8 async_eq_overrun[0x20]; 3749 3750 u8 comp_eq_overrun[0x20]; 3751 3752 u8 reserved_at_180[0x20]; 3753 3754 u8 invalid_command[0x20]; 3755 3756 u8 quota_exceeded_command[0x20]; 3757 3758 u8 internal_rq_out_of_buffer[0x20]; 3759 3760 u8 cq_overrun[0x20]; 3761 3762 u8 eth_wqe_too_small[0x20]; 3763 3764 u8 reserved_at_220[0xc0]; 3765 3766 u8 generated_pkt_steering_fail[0x40]; 3767 3768 u8 handled_pkt_steering_fail[0x40]; 3769 3770 u8 reserved_at_360[0xc80]; 3771 }; 3772 3773 struct mlx5_ifc_traffic_counter_bits { 3774 u8 packets[0x40]; 3775 3776 u8 octets[0x40]; 3777 }; 3778 3779 struct mlx5_ifc_tisc_bits { 3780 u8 strict_lag_tx_port_affinity[0x1]; 3781 u8 tls_en[0x1]; 3782 u8 reserved_at_2[0x2]; 3783 u8 lag_tx_port_affinity[0x04]; 3784 3785 u8 reserved_at_8[0x4]; 3786 u8 prio[0x4]; 3787 u8 reserved_at_10[0x10]; 3788 3789 u8 reserved_at_20[0x100]; 3790 3791 u8 reserved_at_120[0x8]; 3792 u8 transport_domain[0x18]; 3793 3794 u8 reserved_at_140[0x8]; 3795 u8 underlay_qpn[0x18]; 3796 3797 u8 reserved_at_160[0x8]; 3798 u8 pd[0x18]; 3799 3800 u8 reserved_at_180[0x380]; 3801 }; 3802 3803 enum { 3804 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0, 3805 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1, 3806 }; 3807 3808 enum { 3809 MLX5_TIRC_PACKET_MERGE_MASK_IPV4_LRO = BIT(0), 3810 MLX5_TIRC_PACKET_MERGE_MASK_IPV6_LRO = BIT(1), 3811 }; 3812 3813 enum { 3814 MLX5_RX_HASH_FN_NONE = 0x0, 3815 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1, 3816 MLX5_RX_HASH_FN_TOEPLITZ = 0x2, 3817 }; 3818 3819 enum { 3820 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST = 0x1, 3821 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST = 0x2, 3822 }; 3823 3824 struct mlx5_ifc_tirc_bits { 3825 u8 reserved_at_0[0x20]; 3826 3827 u8 disp_type[0x4]; 3828 u8 tls_en[0x1]; 3829 u8 reserved_at_25[0x1b]; 3830 3831 u8 reserved_at_40[0x40]; 3832 3833 u8 reserved_at_80[0x4]; 3834 u8 lro_timeout_period_usecs[0x10]; 3835 u8 packet_merge_mask[0x4]; 3836 u8 lro_max_ip_payload_size[0x8]; 3837 3838 u8 reserved_at_a0[0x40]; 3839 3840 u8 reserved_at_e0[0x8]; 3841 u8 inline_rqn[0x18]; 3842 3843 u8 rx_hash_symmetric[0x1]; 3844 u8 reserved_at_101[0x1]; 3845 u8 tunneled_offload_en[0x1]; 3846 u8 reserved_at_103[0x5]; 3847 u8 indirect_table[0x18]; 3848 3849 u8 rx_hash_fn[0x4]; 3850 u8 reserved_at_124[0x2]; 3851 u8 self_lb_block[0x2]; 3852 u8 transport_domain[0x18]; 3853 3854 u8 rx_hash_toeplitz_key[10][0x20]; 3855 3856 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer; 3857 3858 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner; 3859 3860 u8 reserved_at_2c0[0x4c0]; 3861 }; 3862 3863 enum { 3864 MLX5_SRQC_STATE_GOOD = 0x0, 3865 MLX5_SRQC_STATE_ERROR = 0x1, 3866 }; 3867 3868 struct mlx5_ifc_srqc_bits { 3869 u8 state[0x4]; 3870 u8 log_srq_size[0x4]; 3871 u8 reserved_at_8[0x18]; 3872 3873 u8 wq_signature[0x1]; 3874 u8 cont_srq[0x1]; 3875 u8 reserved_at_22[0x1]; 3876 u8 rlky[0x1]; 3877 u8 reserved_at_24[0x1]; 3878 u8 log_rq_stride[0x3]; 3879 u8 xrcd[0x18]; 3880 3881 u8 page_offset[0x6]; 3882 u8 reserved_at_46[0x2]; 3883 u8 cqn[0x18]; 3884 3885 u8 reserved_at_60[0x20]; 3886 3887 u8 reserved_at_80[0x2]; 3888 u8 log_page_size[0x6]; 3889 u8 reserved_at_88[0x18]; 3890 3891 u8 reserved_at_a0[0x20]; 3892 3893 u8 reserved_at_c0[0x8]; 3894 u8 pd[0x18]; 3895 3896 u8 lwm[0x10]; 3897 u8 wqe_cnt[0x10]; 3898 3899 u8 reserved_at_100[0x40]; 3900 3901 u8 dbr_addr[0x40]; 3902 3903 u8 reserved_at_180[0x80]; 3904 }; 3905 3906 enum { 3907 MLX5_SQC_STATE_RST = 0x0, 3908 MLX5_SQC_STATE_RDY = 0x1, 3909 MLX5_SQC_STATE_ERR = 0x3, 3910 }; 3911 3912 struct mlx5_ifc_sqc_bits { 3913 u8 rlky[0x1]; 3914 u8 cd_master[0x1]; 3915 u8 fre[0x1]; 3916 u8 flush_in_error_en[0x1]; 3917 u8 allow_multi_pkt_send_wqe[0x1]; 3918 u8 min_wqe_inline_mode[0x3]; 3919 u8 state[0x4]; 3920 u8 reg_umr[0x1]; 3921 u8 allow_swp[0x1]; 3922 u8 hairpin[0x1]; 3923 u8 reserved_at_f[0xb]; 3924 u8 ts_format[0x2]; 3925 u8 reserved_at_1c[0x4]; 3926 3927 u8 reserved_at_20[0x8]; 3928 u8 user_index[0x18]; 3929 3930 u8 reserved_at_40[0x8]; 3931 u8 cqn[0x18]; 3932 3933 u8 reserved_at_60[0x8]; 3934 u8 hairpin_peer_rq[0x18]; 3935 3936 u8 reserved_at_80[0x10]; 3937 u8 hairpin_peer_vhca[0x10]; 3938 3939 u8 reserved_at_a0[0x20]; 3940 3941 u8 reserved_at_c0[0x8]; 3942 u8 ts_cqe_to_dest_cqn[0x18]; 3943 3944 u8 reserved_at_e0[0x10]; 3945 u8 packet_pacing_rate_limit_index[0x10]; 3946 u8 tis_lst_sz[0x10]; 3947 u8 qos_queue_group_id[0x10]; 3948 3949 u8 reserved_at_120[0x40]; 3950 3951 u8 reserved_at_160[0x8]; 3952 u8 tis_num_0[0x18]; 3953 3954 struct mlx5_ifc_wq_bits wq; 3955 }; 3956 3957 enum { 3958 SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0, 3959 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1, 3960 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2, 3961 SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3, 3962 SCHEDULING_CONTEXT_ELEMENT_TYPE_QUEUE_GROUP = 0x4, 3963 }; 3964 3965 enum { 3966 ELEMENT_TYPE_CAP_MASK_TSAR = 1 << 0, 3967 ELEMENT_TYPE_CAP_MASK_VPORT = 1 << 1, 3968 ELEMENT_TYPE_CAP_MASK_VPORT_TC = 1 << 2, 3969 ELEMENT_TYPE_CAP_MASK_PARA_VPORT_TC = 1 << 3, 3970 ELEMENT_TYPE_CAP_MASK_QUEUE_GROUP = 1 << 4, 3971 }; 3972 3973 struct mlx5_ifc_scheduling_context_bits { 3974 u8 element_type[0x8]; 3975 u8 reserved_at_8[0x18]; 3976 3977 u8 element_attributes[0x20]; 3978 3979 u8 parent_element_id[0x20]; 3980 3981 u8 reserved_at_60[0x40]; 3982 3983 u8 bw_share[0x20]; 3984 3985 u8 max_average_bw[0x20]; 3986 3987 u8 reserved_at_e0[0x120]; 3988 }; 3989 3990 struct mlx5_ifc_rqtc_bits { 3991 u8 reserved_at_0[0xa0]; 3992 3993 u8 reserved_at_a0[0x5]; 3994 u8 list_q_type[0x3]; 3995 u8 reserved_at_a8[0x8]; 3996 u8 rqt_max_size[0x10]; 3997 3998 u8 rq_vhca_id_format[0x1]; 3999 u8 reserved_at_c1[0xf]; 4000 u8 rqt_actual_size[0x10]; 4001 4002 u8 reserved_at_e0[0x6a0]; 4003 4004 union { 4005 DECLARE_FLEX_ARRAY(struct mlx5_ifc_rq_num_bits, rq_num); 4006 DECLARE_FLEX_ARRAY(struct mlx5_ifc_rq_vhca_bits, rq_vhca); 4007 }; 4008 }; 4009 4010 enum { 4011 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0, 4012 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1, 4013 }; 4014 4015 enum { 4016 MLX5_RQC_STATE_RST = 0x0, 4017 MLX5_RQC_STATE_RDY = 0x1, 4018 MLX5_RQC_STATE_ERR = 0x3, 4019 }; 4020 4021 enum { 4022 MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_BYTE = 0x0, 4023 MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_STRIDE = 0x1, 4024 MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_PAGE = 0x2, 4025 }; 4026 4027 enum { 4028 MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_NO_MATCH = 0x0, 4029 MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_EXTENDED = 0x1, 4030 MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_FIVE_TUPLE = 0x2, 4031 }; 4032 4033 struct mlx5_ifc_rqc_bits { 4034 u8 rlky[0x1]; 4035 u8 delay_drop_en[0x1]; 4036 u8 scatter_fcs[0x1]; 4037 u8 vsd[0x1]; 4038 u8 mem_rq_type[0x4]; 4039 u8 state[0x4]; 4040 u8 reserved_at_c[0x1]; 4041 u8 flush_in_error_en[0x1]; 4042 u8 hairpin[0x1]; 4043 u8 reserved_at_f[0xb]; 4044 u8 ts_format[0x2]; 4045 u8 reserved_at_1c[0x4]; 4046 4047 u8 reserved_at_20[0x8]; 4048 u8 user_index[0x18]; 4049 4050 u8 reserved_at_40[0x8]; 4051 u8 cqn[0x18]; 4052 4053 u8 counter_set_id[0x8]; 4054 u8 reserved_at_68[0x18]; 4055 4056 u8 reserved_at_80[0x8]; 4057 u8 rmpn[0x18]; 4058 4059 u8 reserved_at_a0[0x8]; 4060 u8 hairpin_peer_sq[0x18]; 4061 4062 u8 reserved_at_c0[0x10]; 4063 u8 hairpin_peer_vhca[0x10]; 4064 4065 u8 reserved_at_e0[0x46]; 4066 u8 shampo_no_match_alignment_granularity[0x2]; 4067 u8 reserved_at_128[0x6]; 4068 u8 shampo_match_criteria_type[0x2]; 4069 u8 reservation_timeout[0x10]; 4070 4071 u8 reserved_at_140[0x40]; 4072 4073 struct mlx5_ifc_wq_bits wq; 4074 }; 4075 4076 enum { 4077 MLX5_RMPC_STATE_RDY = 0x1, 4078 MLX5_RMPC_STATE_ERR = 0x3, 4079 }; 4080 4081 struct mlx5_ifc_rmpc_bits { 4082 u8 reserved_at_0[0x8]; 4083 u8 state[0x4]; 4084 u8 reserved_at_c[0x14]; 4085 4086 u8 basic_cyclic_rcv_wqe[0x1]; 4087 u8 reserved_at_21[0x1f]; 4088 4089 u8 reserved_at_40[0x140]; 4090 4091 struct mlx5_ifc_wq_bits wq; 4092 }; 4093 4094 enum { 4095 VHCA_ID_TYPE_HW = 0, 4096 VHCA_ID_TYPE_SW = 1, 4097 }; 4098 4099 struct mlx5_ifc_nic_vport_context_bits { 4100 u8 reserved_at_0[0x5]; 4101 u8 min_wqe_inline_mode[0x3]; 4102 u8 reserved_at_8[0x15]; 4103 u8 disable_mc_local_lb[0x1]; 4104 u8 disable_uc_local_lb[0x1]; 4105 u8 roce_en[0x1]; 4106 4107 u8 arm_change_event[0x1]; 4108 u8 reserved_at_21[0x1a]; 4109 u8 event_on_mtu[0x1]; 4110 u8 event_on_promisc_change[0x1]; 4111 u8 event_on_vlan_change[0x1]; 4112 u8 event_on_mc_address_change[0x1]; 4113 u8 event_on_uc_address_change[0x1]; 4114 4115 u8 vhca_id_type[0x1]; 4116 u8 reserved_at_41[0xb]; 4117 u8 affiliation_criteria[0x4]; 4118 u8 affiliated_vhca_id[0x10]; 4119 4120 u8 reserved_at_60[0xa0]; 4121 4122 u8 reserved_at_100[0x1]; 4123 u8 sd_group[0x3]; 4124 u8 reserved_at_104[0x1c]; 4125 4126 u8 reserved_at_120[0x10]; 4127 u8 mtu[0x10]; 4128 4129 u8 system_image_guid[0x40]; 4130 u8 port_guid[0x40]; 4131 u8 node_guid[0x40]; 4132 4133 u8 reserved_at_200[0x140]; 4134 u8 qkey_violation_counter[0x10]; 4135 u8 reserved_at_350[0x430]; 4136 4137 u8 promisc_uc[0x1]; 4138 u8 promisc_mc[0x1]; 4139 u8 promisc_all[0x1]; 4140 u8 reserved_at_783[0x2]; 4141 u8 allowed_list_type[0x3]; 4142 u8 reserved_at_788[0xc]; 4143 u8 allowed_list_size[0xc]; 4144 4145 struct mlx5_ifc_mac_address_layout_bits permanent_address; 4146 4147 u8 reserved_at_7e0[0x20]; 4148 4149 u8 current_uc_mac_address[][0x40]; 4150 }; 4151 4152 enum { 4153 MLX5_MKC_ACCESS_MODE_PA = 0x0, 4154 MLX5_MKC_ACCESS_MODE_MTT = 0x1, 4155 MLX5_MKC_ACCESS_MODE_KLMS = 0x2, 4156 MLX5_MKC_ACCESS_MODE_KSM = 0x3, 4157 MLX5_MKC_ACCESS_MODE_SW_ICM = 0x4, 4158 MLX5_MKC_ACCESS_MODE_MEMIC = 0x5, 4159 }; 4160 4161 struct mlx5_ifc_mkc_bits { 4162 u8 reserved_at_0[0x1]; 4163 u8 free[0x1]; 4164 u8 reserved_at_2[0x1]; 4165 u8 access_mode_4_2[0x3]; 4166 u8 reserved_at_6[0x7]; 4167 u8 relaxed_ordering_write[0x1]; 4168 u8 reserved_at_e[0x1]; 4169 u8 small_fence_on_rdma_read_response[0x1]; 4170 u8 umr_en[0x1]; 4171 u8 a[0x1]; 4172 u8 rw[0x1]; 4173 u8 rr[0x1]; 4174 u8 lw[0x1]; 4175 u8 lr[0x1]; 4176 u8 access_mode_1_0[0x2]; 4177 u8 reserved_at_18[0x2]; 4178 u8 ma_translation_mode[0x2]; 4179 u8 reserved_at_1c[0x4]; 4180 4181 u8 qpn[0x18]; 4182 u8 mkey_7_0[0x8]; 4183 4184 u8 reserved_at_40[0x20]; 4185 4186 u8 length64[0x1]; 4187 u8 bsf_en[0x1]; 4188 u8 sync_umr[0x1]; 4189 u8 reserved_at_63[0x2]; 4190 u8 expected_sigerr_count[0x1]; 4191 u8 reserved_at_66[0x1]; 4192 u8 en_rinval[0x1]; 4193 u8 pd[0x18]; 4194 4195 u8 start_addr[0x40]; 4196 4197 u8 len[0x40]; 4198 4199 u8 bsf_octword_size[0x20]; 4200 4201 u8 reserved_at_120[0x80]; 4202 4203 u8 translations_octword_size[0x20]; 4204 4205 u8 reserved_at_1c0[0x19]; 4206 u8 relaxed_ordering_read[0x1]; 4207 u8 reserved_at_1d9[0x1]; 4208 u8 log_page_size[0x5]; 4209 4210 u8 reserved_at_1e0[0x20]; 4211 }; 4212 4213 struct mlx5_ifc_pkey_bits { 4214 u8 reserved_at_0[0x10]; 4215 u8 pkey[0x10]; 4216 }; 4217 4218 struct mlx5_ifc_array128_auto_bits { 4219 u8 array128_auto[16][0x8]; 4220 }; 4221 4222 struct mlx5_ifc_hca_vport_context_bits { 4223 u8 field_select[0x20]; 4224 4225 u8 reserved_at_20[0xe0]; 4226 4227 u8 sm_virt_aware[0x1]; 4228 u8 has_smi[0x1]; 4229 u8 has_raw[0x1]; 4230 u8 grh_required[0x1]; 4231 u8 reserved_at_104[0x4]; 4232 u8 num_port_plane[0x8]; 4233 u8 port_physical_state[0x4]; 4234 u8 vport_state_policy[0x4]; 4235 u8 port_state[0x4]; 4236 u8 vport_state[0x4]; 4237 4238 u8 reserved_at_120[0x20]; 4239 4240 u8 system_image_guid[0x40]; 4241 4242 u8 port_guid[0x40]; 4243 4244 u8 node_guid[0x40]; 4245 4246 u8 cap_mask1[0x20]; 4247 4248 u8 cap_mask1_field_select[0x20]; 4249 4250 u8 cap_mask2[0x20]; 4251 4252 u8 cap_mask2_field_select[0x20]; 4253 4254 u8 reserved_at_280[0x80]; 4255 4256 u8 lid[0x10]; 4257 u8 reserved_at_310[0x4]; 4258 u8 init_type_reply[0x4]; 4259 u8 lmc[0x3]; 4260 u8 subnet_timeout[0x5]; 4261 4262 u8 sm_lid[0x10]; 4263 u8 sm_sl[0x4]; 4264 u8 reserved_at_334[0xc]; 4265 4266 u8 qkey_violation_counter[0x10]; 4267 u8 pkey_violation_counter[0x10]; 4268 4269 u8 reserved_at_360[0xca0]; 4270 }; 4271 4272 struct mlx5_ifc_esw_vport_context_bits { 4273 u8 fdb_to_vport_reg_c[0x1]; 4274 u8 reserved_at_1[0x2]; 4275 u8 vport_svlan_strip[0x1]; 4276 u8 vport_cvlan_strip[0x1]; 4277 u8 vport_svlan_insert[0x1]; 4278 u8 vport_cvlan_insert[0x2]; 4279 u8 fdb_to_vport_reg_c_id[0x8]; 4280 u8 reserved_at_10[0x10]; 4281 4282 u8 reserved_at_20[0x20]; 4283 4284 u8 svlan_cfi[0x1]; 4285 u8 svlan_pcp[0x3]; 4286 u8 svlan_id[0xc]; 4287 u8 cvlan_cfi[0x1]; 4288 u8 cvlan_pcp[0x3]; 4289 u8 cvlan_id[0xc]; 4290 4291 u8 reserved_at_60[0x720]; 4292 4293 u8 sw_steering_vport_icm_address_rx[0x40]; 4294 4295 u8 sw_steering_vport_icm_address_tx[0x40]; 4296 }; 4297 4298 enum { 4299 MLX5_EQC_STATUS_OK = 0x0, 4300 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa, 4301 }; 4302 4303 enum { 4304 MLX5_EQC_ST_ARMED = 0x9, 4305 MLX5_EQC_ST_FIRED = 0xa, 4306 }; 4307 4308 struct mlx5_ifc_eqc_bits { 4309 u8 status[0x4]; 4310 u8 reserved_at_4[0x9]; 4311 u8 ec[0x1]; 4312 u8 oi[0x1]; 4313 u8 reserved_at_f[0x5]; 4314 u8 st[0x4]; 4315 u8 reserved_at_18[0x8]; 4316 4317 u8 reserved_at_20[0x20]; 4318 4319 u8 reserved_at_40[0x14]; 4320 u8 page_offset[0x6]; 4321 u8 reserved_at_5a[0x6]; 4322 4323 u8 reserved_at_60[0x3]; 4324 u8 log_eq_size[0x5]; 4325 u8 uar_page[0x18]; 4326 4327 u8 reserved_at_80[0x20]; 4328 4329 u8 reserved_at_a0[0x14]; 4330 u8 intr[0xc]; 4331 4332 u8 reserved_at_c0[0x3]; 4333 u8 log_page_size[0x5]; 4334 u8 reserved_at_c8[0x18]; 4335 4336 u8 reserved_at_e0[0x60]; 4337 4338 u8 reserved_at_140[0x8]; 4339 u8 consumer_counter[0x18]; 4340 4341 u8 reserved_at_160[0x8]; 4342 u8 producer_counter[0x18]; 4343 4344 u8 reserved_at_180[0x80]; 4345 }; 4346 4347 enum { 4348 MLX5_DCTC_STATE_ACTIVE = 0x0, 4349 MLX5_DCTC_STATE_DRAINING = 0x1, 4350 MLX5_DCTC_STATE_DRAINED = 0x2, 4351 }; 4352 4353 enum { 4354 MLX5_DCTC_CS_RES_DISABLE = 0x0, 4355 MLX5_DCTC_CS_RES_NA = 0x1, 4356 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2, 4357 }; 4358 4359 enum { 4360 MLX5_DCTC_MTU_256_BYTES = 0x1, 4361 MLX5_DCTC_MTU_512_BYTES = 0x2, 4362 MLX5_DCTC_MTU_1K_BYTES = 0x3, 4363 MLX5_DCTC_MTU_2K_BYTES = 0x4, 4364 MLX5_DCTC_MTU_4K_BYTES = 0x5, 4365 }; 4366 4367 struct mlx5_ifc_dctc_bits { 4368 u8 reserved_at_0[0x4]; 4369 u8 state[0x4]; 4370 u8 reserved_at_8[0x18]; 4371 4372 u8 reserved_at_20[0x8]; 4373 u8 user_index[0x18]; 4374 4375 u8 reserved_at_40[0x8]; 4376 u8 cqn[0x18]; 4377 4378 u8 counter_set_id[0x8]; 4379 u8 atomic_mode[0x4]; 4380 u8 rre[0x1]; 4381 u8 rwe[0x1]; 4382 u8 rae[0x1]; 4383 u8 atomic_like_write_en[0x1]; 4384 u8 latency_sensitive[0x1]; 4385 u8 rlky[0x1]; 4386 u8 free_ar[0x1]; 4387 u8 reserved_at_73[0xd]; 4388 4389 u8 reserved_at_80[0x8]; 4390 u8 cs_res[0x8]; 4391 u8 reserved_at_90[0x3]; 4392 u8 min_rnr_nak[0x5]; 4393 u8 reserved_at_98[0x8]; 4394 4395 u8 reserved_at_a0[0x8]; 4396 u8 srqn_xrqn[0x18]; 4397 4398 u8 reserved_at_c0[0x8]; 4399 u8 pd[0x18]; 4400 4401 u8 tclass[0x8]; 4402 u8 reserved_at_e8[0x4]; 4403 u8 flow_label[0x14]; 4404 4405 u8 dc_access_key[0x40]; 4406 4407 u8 reserved_at_140[0x5]; 4408 u8 mtu[0x3]; 4409 u8 port[0x8]; 4410 u8 pkey_index[0x10]; 4411 4412 u8 reserved_at_160[0x8]; 4413 u8 my_addr_index[0x8]; 4414 u8 reserved_at_170[0x8]; 4415 u8 hop_limit[0x8]; 4416 4417 u8 dc_access_key_violation_count[0x20]; 4418 4419 u8 reserved_at_1a0[0x14]; 4420 u8 dei_cfi[0x1]; 4421 u8 eth_prio[0x3]; 4422 u8 ecn[0x2]; 4423 u8 dscp[0x6]; 4424 4425 u8 reserved_at_1c0[0x20]; 4426 u8 ece[0x20]; 4427 }; 4428 4429 enum { 4430 MLX5_CQC_STATUS_OK = 0x0, 4431 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9, 4432 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa, 4433 }; 4434 4435 enum { 4436 MLX5_CQC_CQE_SZ_64_BYTES = 0x0, 4437 MLX5_CQC_CQE_SZ_128_BYTES = 0x1, 4438 }; 4439 4440 enum { 4441 MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED = 0x6, 4442 MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED = 0x9, 4443 MLX5_CQC_ST_FIRED = 0xa, 4444 }; 4445 4446 enum mlx5_cq_period_mode { 4447 MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0, 4448 MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1, 4449 MLX5_CQ_PERIOD_NUM_MODES, 4450 }; 4451 4452 struct mlx5_ifc_cqc_bits { 4453 u8 status[0x4]; 4454 u8 reserved_at_4[0x2]; 4455 u8 dbr_umem_valid[0x1]; 4456 u8 apu_cq[0x1]; 4457 u8 cqe_sz[0x3]; 4458 u8 cc[0x1]; 4459 u8 reserved_at_c[0x1]; 4460 u8 scqe_break_moderation_en[0x1]; 4461 u8 oi[0x1]; 4462 u8 cq_period_mode[0x2]; 4463 u8 cqe_comp_en[0x1]; 4464 u8 mini_cqe_res_format[0x2]; 4465 u8 st[0x4]; 4466 u8 reserved_at_18[0x6]; 4467 u8 cqe_compression_layout[0x2]; 4468 4469 u8 reserved_at_20[0x20]; 4470 4471 u8 reserved_at_40[0x14]; 4472 u8 page_offset[0x6]; 4473 u8 reserved_at_5a[0x6]; 4474 4475 u8 reserved_at_60[0x3]; 4476 u8 log_cq_size[0x5]; 4477 u8 uar_page[0x18]; 4478 4479 u8 reserved_at_80[0x4]; 4480 u8 cq_period[0xc]; 4481 u8 cq_max_count[0x10]; 4482 4483 u8 c_eqn_or_apu_element[0x20]; 4484 4485 u8 reserved_at_c0[0x3]; 4486 u8 log_page_size[0x5]; 4487 u8 reserved_at_c8[0x18]; 4488 4489 u8 reserved_at_e0[0x20]; 4490 4491 u8 reserved_at_100[0x8]; 4492 u8 last_notified_index[0x18]; 4493 4494 u8 reserved_at_120[0x8]; 4495 u8 last_solicit_index[0x18]; 4496 4497 u8 reserved_at_140[0x8]; 4498 u8 consumer_counter[0x18]; 4499 4500 u8 reserved_at_160[0x8]; 4501 u8 producer_counter[0x18]; 4502 4503 u8 reserved_at_180[0x40]; 4504 4505 u8 dbr_addr[0x40]; 4506 }; 4507 4508 union mlx5_ifc_cong_control_roce_ecn_auto_bits { 4509 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp; 4510 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp; 4511 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np; 4512 struct mlx5_ifc_cong_control_r_roce_general_bits cong_control_r_roce_general; 4513 u8 reserved_at_0[0x800]; 4514 }; 4515 4516 struct mlx5_ifc_query_adapter_param_block_bits { 4517 u8 reserved_at_0[0xc0]; 4518 4519 u8 reserved_at_c0[0x8]; 4520 u8 ieee_vendor_id[0x18]; 4521 4522 u8 reserved_at_e0[0x10]; 4523 u8 vsd_vendor_id[0x10]; 4524 4525 u8 vsd[208][0x8]; 4526 4527 u8 vsd_contd_psid[16][0x8]; 4528 }; 4529 4530 enum { 4531 MLX5_XRQC_STATE_GOOD = 0x0, 4532 MLX5_XRQC_STATE_ERROR = 0x1, 4533 }; 4534 4535 enum { 4536 MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0, 4537 MLX5_XRQC_TOPOLOGY_TAG_MATCHING = 0x1, 4538 }; 4539 4540 enum { 4541 MLX5_XRQC_OFFLOAD_RNDV = 0x1, 4542 }; 4543 4544 struct mlx5_ifc_tag_matching_topology_context_bits { 4545 u8 log_matching_list_sz[0x4]; 4546 u8 reserved_at_4[0xc]; 4547 u8 append_next_index[0x10]; 4548 4549 u8 sw_phase_cnt[0x10]; 4550 u8 hw_phase_cnt[0x10]; 4551 4552 u8 reserved_at_40[0x40]; 4553 }; 4554 4555 struct mlx5_ifc_xrqc_bits { 4556 u8 state[0x4]; 4557 u8 rlkey[0x1]; 4558 u8 reserved_at_5[0xf]; 4559 u8 topology[0x4]; 4560 u8 reserved_at_18[0x4]; 4561 u8 offload[0x4]; 4562 4563 u8 reserved_at_20[0x8]; 4564 u8 user_index[0x18]; 4565 4566 u8 reserved_at_40[0x8]; 4567 u8 cqn[0x18]; 4568 4569 u8 reserved_at_60[0xa0]; 4570 4571 struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context; 4572 4573 u8 reserved_at_180[0x280]; 4574 4575 struct mlx5_ifc_wq_bits wq; 4576 }; 4577 4578 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits { 4579 struct mlx5_ifc_modify_field_select_bits modify_field_select; 4580 struct mlx5_ifc_resize_field_select_bits resize_field_select; 4581 u8 reserved_at_0[0x20]; 4582 }; 4583 4584 union mlx5_ifc_field_select_802_1_r_roce_auto_bits { 4585 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp; 4586 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp; 4587 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np; 4588 u8 reserved_at_0[0x20]; 4589 }; 4590 4591 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits { 4592 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 4593 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 4594 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 4595 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 4596 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 4597 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 4598 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout; 4599 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout; 4600 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 4601 struct mlx5_ifc_ib_ext_port_cntrs_grp_data_layout_bits ib_ext_port_cntrs_grp_data_layout; 4602 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 4603 struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs; 4604 u8 reserved_at_0[0x7c0]; 4605 }; 4606 4607 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits { 4608 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout; 4609 u8 reserved_at_0[0x7c0]; 4610 }; 4611 4612 union mlx5_ifc_event_auto_bits { 4613 struct mlx5_ifc_comp_event_bits comp_event; 4614 struct mlx5_ifc_dct_events_bits dct_events; 4615 struct mlx5_ifc_qp_events_bits qp_events; 4616 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event; 4617 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event; 4618 struct mlx5_ifc_cq_error_bits cq_error; 4619 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged; 4620 struct mlx5_ifc_port_state_change_event_bits port_state_change_event; 4621 struct mlx5_ifc_gpio_event_bits gpio_event; 4622 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event; 4623 struct mlx5_ifc_stall_vl_event_bits stall_vl_event; 4624 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event; 4625 u8 reserved_at_0[0xe0]; 4626 }; 4627 4628 struct mlx5_ifc_health_buffer_bits { 4629 u8 reserved_at_0[0x100]; 4630 4631 u8 assert_existptr[0x20]; 4632 4633 u8 assert_callra[0x20]; 4634 4635 u8 reserved_at_140[0x20]; 4636 4637 u8 time[0x20]; 4638 4639 u8 fw_version[0x20]; 4640 4641 u8 hw_id[0x20]; 4642 4643 u8 rfr[0x1]; 4644 u8 reserved_at_1c1[0x3]; 4645 u8 valid[0x1]; 4646 u8 severity[0x3]; 4647 u8 reserved_at_1c8[0x18]; 4648 4649 u8 irisc_index[0x8]; 4650 u8 synd[0x8]; 4651 u8 ext_synd[0x10]; 4652 }; 4653 4654 struct mlx5_ifc_register_loopback_control_bits { 4655 u8 no_lb[0x1]; 4656 u8 reserved_at_1[0x7]; 4657 u8 port[0x8]; 4658 u8 reserved_at_10[0x10]; 4659 4660 u8 reserved_at_20[0x60]; 4661 }; 4662 4663 struct mlx5_ifc_vport_tc_element_bits { 4664 u8 traffic_class[0x4]; 4665 u8 reserved_at_4[0xc]; 4666 u8 vport_number[0x10]; 4667 }; 4668 4669 struct mlx5_ifc_vport_element_bits { 4670 u8 reserved_at_0[0x10]; 4671 u8 vport_number[0x10]; 4672 }; 4673 4674 enum { 4675 TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0, 4676 TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1, 4677 TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2, 4678 }; 4679 4680 enum { 4681 TSAR_TYPE_CAP_MASK_DWRR = 1 << 0, 4682 TSAR_TYPE_CAP_MASK_ROUND_ROBIN = 1 << 1, 4683 TSAR_TYPE_CAP_MASK_ETS = 1 << 2, 4684 }; 4685 4686 struct mlx5_ifc_tsar_element_bits { 4687 u8 reserved_at_0[0x8]; 4688 u8 tsar_type[0x8]; 4689 u8 reserved_at_10[0x10]; 4690 }; 4691 4692 enum { 4693 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0, 4694 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1, 4695 }; 4696 4697 struct mlx5_ifc_teardown_hca_out_bits { 4698 u8 status[0x8]; 4699 u8 reserved_at_8[0x18]; 4700 4701 u8 syndrome[0x20]; 4702 4703 u8 reserved_at_40[0x3f]; 4704 4705 u8 state[0x1]; 4706 }; 4707 4708 enum { 4709 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0, 4710 MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE = 0x1, 4711 MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN = 0x2, 4712 }; 4713 4714 struct mlx5_ifc_teardown_hca_in_bits { 4715 u8 opcode[0x10]; 4716 u8 reserved_at_10[0x10]; 4717 4718 u8 reserved_at_20[0x10]; 4719 u8 op_mod[0x10]; 4720 4721 u8 reserved_at_40[0x10]; 4722 u8 profile[0x10]; 4723 4724 u8 reserved_at_60[0x20]; 4725 }; 4726 4727 struct mlx5_ifc_sqerr2rts_qp_out_bits { 4728 u8 status[0x8]; 4729 u8 reserved_at_8[0x18]; 4730 4731 u8 syndrome[0x20]; 4732 4733 u8 reserved_at_40[0x40]; 4734 }; 4735 4736 struct mlx5_ifc_sqerr2rts_qp_in_bits { 4737 u8 opcode[0x10]; 4738 u8 uid[0x10]; 4739 4740 u8 reserved_at_20[0x10]; 4741 u8 op_mod[0x10]; 4742 4743 u8 reserved_at_40[0x8]; 4744 u8 qpn[0x18]; 4745 4746 u8 reserved_at_60[0x20]; 4747 4748 u8 opt_param_mask[0x20]; 4749 4750 u8 reserved_at_a0[0x20]; 4751 4752 struct mlx5_ifc_qpc_bits qpc; 4753 4754 u8 reserved_at_800[0x80]; 4755 }; 4756 4757 struct mlx5_ifc_sqd2rts_qp_out_bits { 4758 u8 status[0x8]; 4759 u8 reserved_at_8[0x18]; 4760 4761 u8 syndrome[0x20]; 4762 4763 u8 reserved_at_40[0x40]; 4764 }; 4765 4766 struct mlx5_ifc_sqd2rts_qp_in_bits { 4767 u8 opcode[0x10]; 4768 u8 uid[0x10]; 4769 4770 u8 reserved_at_20[0x10]; 4771 u8 op_mod[0x10]; 4772 4773 u8 reserved_at_40[0x8]; 4774 u8 qpn[0x18]; 4775 4776 u8 reserved_at_60[0x20]; 4777 4778 u8 opt_param_mask[0x20]; 4779 4780 u8 reserved_at_a0[0x20]; 4781 4782 struct mlx5_ifc_qpc_bits qpc; 4783 4784 u8 reserved_at_800[0x80]; 4785 }; 4786 4787 struct mlx5_ifc_set_roce_address_out_bits { 4788 u8 status[0x8]; 4789 u8 reserved_at_8[0x18]; 4790 4791 u8 syndrome[0x20]; 4792 4793 u8 reserved_at_40[0x40]; 4794 }; 4795 4796 struct mlx5_ifc_set_roce_address_in_bits { 4797 u8 opcode[0x10]; 4798 u8 reserved_at_10[0x10]; 4799 4800 u8 reserved_at_20[0x10]; 4801 u8 op_mod[0x10]; 4802 4803 u8 roce_address_index[0x10]; 4804 u8 reserved_at_50[0xc]; 4805 u8 vhca_port_num[0x4]; 4806 4807 u8 reserved_at_60[0x20]; 4808 4809 struct mlx5_ifc_roce_addr_layout_bits roce_address; 4810 }; 4811 4812 struct mlx5_ifc_set_mad_demux_out_bits { 4813 u8 status[0x8]; 4814 u8 reserved_at_8[0x18]; 4815 4816 u8 syndrome[0x20]; 4817 4818 u8 reserved_at_40[0x40]; 4819 }; 4820 4821 enum { 4822 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0, 4823 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2, 4824 }; 4825 4826 struct mlx5_ifc_set_mad_demux_in_bits { 4827 u8 opcode[0x10]; 4828 u8 reserved_at_10[0x10]; 4829 4830 u8 reserved_at_20[0x10]; 4831 u8 op_mod[0x10]; 4832 4833 u8 reserved_at_40[0x20]; 4834 4835 u8 reserved_at_60[0x6]; 4836 u8 demux_mode[0x2]; 4837 u8 reserved_at_68[0x18]; 4838 }; 4839 4840 struct mlx5_ifc_set_l2_table_entry_out_bits { 4841 u8 status[0x8]; 4842 u8 reserved_at_8[0x18]; 4843 4844 u8 syndrome[0x20]; 4845 4846 u8 reserved_at_40[0x40]; 4847 }; 4848 4849 struct mlx5_ifc_set_l2_table_entry_in_bits { 4850 u8 opcode[0x10]; 4851 u8 reserved_at_10[0x10]; 4852 4853 u8 reserved_at_20[0x10]; 4854 u8 op_mod[0x10]; 4855 4856 u8 reserved_at_40[0x60]; 4857 4858 u8 reserved_at_a0[0x8]; 4859 u8 table_index[0x18]; 4860 4861 u8 reserved_at_c0[0x20]; 4862 4863 u8 reserved_at_e0[0x10]; 4864 u8 silent_mode_valid[0x1]; 4865 u8 silent_mode[0x1]; 4866 u8 reserved_at_f2[0x1]; 4867 u8 vlan_valid[0x1]; 4868 u8 vlan[0xc]; 4869 4870 struct mlx5_ifc_mac_address_layout_bits mac_address; 4871 4872 u8 reserved_at_140[0xc0]; 4873 }; 4874 4875 struct mlx5_ifc_set_issi_out_bits { 4876 u8 status[0x8]; 4877 u8 reserved_at_8[0x18]; 4878 4879 u8 syndrome[0x20]; 4880 4881 u8 reserved_at_40[0x40]; 4882 }; 4883 4884 struct mlx5_ifc_set_issi_in_bits { 4885 u8 opcode[0x10]; 4886 u8 reserved_at_10[0x10]; 4887 4888 u8 reserved_at_20[0x10]; 4889 u8 op_mod[0x10]; 4890 4891 u8 reserved_at_40[0x10]; 4892 u8 current_issi[0x10]; 4893 4894 u8 reserved_at_60[0x20]; 4895 }; 4896 4897 struct mlx5_ifc_set_hca_cap_out_bits { 4898 u8 status[0x8]; 4899 u8 reserved_at_8[0x18]; 4900 4901 u8 syndrome[0x20]; 4902 4903 u8 reserved_at_40[0x40]; 4904 }; 4905 4906 struct mlx5_ifc_set_hca_cap_in_bits { 4907 u8 opcode[0x10]; 4908 u8 reserved_at_10[0x10]; 4909 4910 u8 reserved_at_20[0x10]; 4911 u8 op_mod[0x10]; 4912 4913 u8 other_function[0x1]; 4914 u8 ec_vf_function[0x1]; 4915 u8 reserved_at_42[0xe]; 4916 u8 function_id[0x10]; 4917 4918 u8 reserved_at_60[0x20]; 4919 4920 union mlx5_ifc_hca_cap_union_bits capability; 4921 }; 4922 4923 enum { 4924 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0, 4925 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1, 4926 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2, 4927 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3, 4928 MLX5_SET_FTE_MODIFY_ENABLE_MASK_IPSEC_OBJ_ID = 0x4 4929 }; 4930 4931 struct mlx5_ifc_set_fte_out_bits { 4932 u8 status[0x8]; 4933 u8 reserved_at_8[0x18]; 4934 4935 u8 syndrome[0x20]; 4936 4937 u8 reserved_at_40[0x40]; 4938 }; 4939 4940 struct mlx5_ifc_set_fte_in_bits { 4941 u8 opcode[0x10]; 4942 u8 reserved_at_10[0x10]; 4943 4944 u8 reserved_at_20[0x10]; 4945 u8 op_mod[0x10]; 4946 4947 u8 other_vport[0x1]; 4948 u8 reserved_at_41[0xf]; 4949 u8 vport_number[0x10]; 4950 4951 u8 reserved_at_60[0x20]; 4952 4953 u8 table_type[0x8]; 4954 u8 reserved_at_88[0x18]; 4955 4956 u8 reserved_at_a0[0x8]; 4957 u8 table_id[0x18]; 4958 4959 u8 ignore_flow_level[0x1]; 4960 u8 reserved_at_c1[0x17]; 4961 u8 modify_enable_mask[0x8]; 4962 4963 u8 reserved_at_e0[0x20]; 4964 4965 u8 flow_index[0x20]; 4966 4967 u8 reserved_at_120[0xe0]; 4968 4969 struct mlx5_ifc_flow_context_bits flow_context; 4970 }; 4971 4972 struct mlx5_ifc_rts2rts_qp_out_bits { 4973 u8 status[0x8]; 4974 u8 reserved_at_8[0x18]; 4975 4976 u8 syndrome[0x20]; 4977 4978 u8 reserved_at_40[0x20]; 4979 u8 ece[0x20]; 4980 }; 4981 4982 struct mlx5_ifc_rts2rts_qp_in_bits { 4983 u8 opcode[0x10]; 4984 u8 uid[0x10]; 4985 4986 u8 reserved_at_20[0x10]; 4987 u8 op_mod[0x10]; 4988 4989 u8 reserved_at_40[0x8]; 4990 u8 qpn[0x18]; 4991 4992 u8 reserved_at_60[0x20]; 4993 4994 u8 opt_param_mask[0x20]; 4995 4996 u8 ece[0x20]; 4997 4998 struct mlx5_ifc_qpc_bits qpc; 4999 5000 u8 reserved_at_800[0x80]; 5001 }; 5002 5003 struct mlx5_ifc_rtr2rts_qp_out_bits { 5004 u8 status[0x8]; 5005 u8 reserved_at_8[0x18]; 5006 5007 u8 syndrome[0x20]; 5008 5009 u8 reserved_at_40[0x20]; 5010 u8 ece[0x20]; 5011 }; 5012 5013 struct mlx5_ifc_rtr2rts_qp_in_bits { 5014 u8 opcode[0x10]; 5015 u8 uid[0x10]; 5016 5017 u8 reserved_at_20[0x10]; 5018 u8 op_mod[0x10]; 5019 5020 u8 reserved_at_40[0x8]; 5021 u8 qpn[0x18]; 5022 5023 u8 reserved_at_60[0x20]; 5024 5025 u8 opt_param_mask[0x20]; 5026 5027 u8 ece[0x20]; 5028 5029 struct mlx5_ifc_qpc_bits qpc; 5030 5031 u8 reserved_at_800[0x80]; 5032 }; 5033 5034 struct mlx5_ifc_rst2init_qp_out_bits { 5035 u8 status[0x8]; 5036 u8 reserved_at_8[0x18]; 5037 5038 u8 syndrome[0x20]; 5039 5040 u8 reserved_at_40[0x20]; 5041 u8 ece[0x20]; 5042 }; 5043 5044 struct mlx5_ifc_rst2init_qp_in_bits { 5045 u8 opcode[0x10]; 5046 u8 uid[0x10]; 5047 5048 u8 reserved_at_20[0x10]; 5049 u8 op_mod[0x10]; 5050 5051 u8 reserved_at_40[0x8]; 5052 u8 qpn[0x18]; 5053 5054 u8 reserved_at_60[0x20]; 5055 5056 u8 opt_param_mask[0x20]; 5057 5058 u8 ece[0x20]; 5059 5060 struct mlx5_ifc_qpc_bits qpc; 5061 5062 u8 reserved_at_800[0x80]; 5063 }; 5064 5065 struct mlx5_ifc_query_xrq_out_bits { 5066 u8 status[0x8]; 5067 u8 reserved_at_8[0x18]; 5068 5069 u8 syndrome[0x20]; 5070 5071 u8 reserved_at_40[0x40]; 5072 5073 struct mlx5_ifc_xrqc_bits xrq_context; 5074 }; 5075 5076 struct mlx5_ifc_query_xrq_in_bits { 5077 u8 opcode[0x10]; 5078 u8 reserved_at_10[0x10]; 5079 5080 u8 reserved_at_20[0x10]; 5081 u8 op_mod[0x10]; 5082 5083 u8 reserved_at_40[0x8]; 5084 u8 xrqn[0x18]; 5085 5086 u8 reserved_at_60[0x20]; 5087 }; 5088 5089 struct mlx5_ifc_query_xrc_srq_out_bits { 5090 u8 status[0x8]; 5091 u8 reserved_at_8[0x18]; 5092 5093 u8 syndrome[0x20]; 5094 5095 u8 reserved_at_40[0x40]; 5096 5097 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 5098 5099 u8 reserved_at_280[0x600]; 5100 5101 u8 pas[][0x40]; 5102 }; 5103 5104 struct mlx5_ifc_query_xrc_srq_in_bits { 5105 u8 opcode[0x10]; 5106 u8 reserved_at_10[0x10]; 5107 5108 u8 reserved_at_20[0x10]; 5109 u8 op_mod[0x10]; 5110 5111 u8 reserved_at_40[0x8]; 5112 u8 xrc_srqn[0x18]; 5113 5114 u8 reserved_at_60[0x20]; 5115 }; 5116 5117 enum { 5118 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0, 5119 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1, 5120 }; 5121 5122 struct mlx5_ifc_query_vport_state_out_bits { 5123 u8 status[0x8]; 5124 u8 reserved_at_8[0x18]; 5125 5126 u8 syndrome[0x20]; 5127 5128 u8 reserved_at_40[0x20]; 5129 5130 u8 reserved_at_60[0x18]; 5131 u8 admin_state[0x4]; 5132 u8 state[0x4]; 5133 }; 5134 5135 enum { 5136 MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT = 0x0, 5137 MLX5_VPORT_STATE_OP_MOD_ESW_VPORT = 0x1, 5138 MLX5_VPORT_STATE_OP_MOD_UPLINK = 0x2, 5139 }; 5140 5141 struct mlx5_ifc_arm_monitor_counter_in_bits { 5142 u8 opcode[0x10]; 5143 u8 uid[0x10]; 5144 5145 u8 reserved_at_20[0x10]; 5146 u8 op_mod[0x10]; 5147 5148 u8 reserved_at_40[0x20]; 5149 5150 u8 reserved_at_60[0x20]; 5151 }; 5152 5153 struct mlx5_ifc_arm_monitor_counter_out_bits { 5154 u8 status[0x8]; 5155 u8 reserved_at_8[0x18]; 5156 5157 u8 syndrome[0x20]; 5158 5159 u8 reserved_at_40[0x40]; 5160 }; 5161 5162 enum { 5163 MLX5_QUERY_MONITOR_CNT_TYPE_PPCNT = 0x0, 5164 MLX5_QUERY_MONITOR_CNT_TYPE_Q_COUNTER = 0x1, 5165 }; 5166 5167 enum mlx5_monitor_counter_ppcnt { 5168 MLX5_QUERY_MONITOR_PPCNT_IN_RANGE_LENGTH_ERRORS = 0x0, 5169 MLX5_QUERY_MONITOR_PPCNT_OUT_OF_RANGE_LENGTH_FIELD = 0x1, 5170 MLX5_QUERY_MONITOR_PPCNT_FRAME_TOO_LONG_ERRORS = 0x2, 5171 MLX5_QUERY_MONITOR_PPCNT_FRAME_CHECK_SEQUENCE_ERRORS = 0x3, 5172 MLX5_QUERY_MONITOR_PPCNT_ALIGNMENT_ERRORS = 0x4, 5173 MLX5_QUERY_MONITOR_PPCNT_IF_OUT_DISCARDS = 0x5, 5174 }; 5175 5176 enum { 5177 MLX5_QUERY_MONITOR_Q_COUNTER_RX_OUT_OF_BUFFER = 0x4, 5178 }; 5179 5180 struct mlx5_ifc_monitor_counter_output_bits { 5181 u8 reserved_at_0[0x4]; 5182 u8 type[0x4]; 5183 u8 reserved_at_8[0x8]; 5184 u8 counter[0x10]; 5185 5186 u8 counter_group_id[0x20]; 5187 }; 5188 5189 #define MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 (6) 5190 #define MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1 (1) 5191 #define MLX5_CMD_SET_MONITOR_NUM_COUNTER (MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 +\ 5192 MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1) 5193 5194 struct mlx5_ifc_set_monitor_counter_in_bits { 5195 u8 opcode[0x10]; 5196 u8 uid[0x10]; 5197 5198 u8 reserved_at_20[0x10]; 5199 u8 op_mod[0x10]; 5200 5201 u8 reserved_at_40[0x10]; 5202 u8 num_of_counters[0x10]; 5203 5204 u8 reserved_at_60[0x20]; 5205 5206 struct mlx5_ifc_monitor_counter_output_bits monitor_counter[MLX5_CMD_SET_MONITOR_NUM_COUNTER]; 5207 }; 5208 5209 struct mlx5_ifc_set_monitor_counter_out_bits { 5210 u8 status[0x8]; 5211 u8 reserved_at_8[0x18]; 5212 5213 u8 syndrome[0x20]; 5214 5215 u8 reserved_at_40[0x40]; 5216 }; 5217 5218 struct mlx5_ifc_query_vport_state_in_bits { 5219 u8 opcode[0x10]; 5220 u8 reserved_at_10[0x10]; 5221 5222 u8 reserved_at_20[0x10]; 5223 u8 op_mod[0x10]; 5224 5225 u8 other_vport[0x1]; 5226 u8 reserved_at_41[0xf]; 5227 u8 vport_number[0x10]; 5228 5229 u8 reserved_at_60[0x20]; 5230 }; 5231 5232 struct mlx5_ifc_query_vnic_env_out_bits { 5233 u8 status[0x8]; 5234 u8 reserved_at_8[0x18]; 5235 5236 u8 syndrome[0x20]; 5237 5238 u8 reserved_at_40[0x40]; 5239 5240 struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env; 5241 }; 5242 5243 enum { 5244 MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS = 0x0, 5245 }; 5246 5247 struct mlx5_ifc_query_vnic_env_in_bits { 5248 u8 opcode[0x10]; 5249 u8 reserved_at_10[0x10]; 5250 5251 u8 reserved_at_20[0x10]; 5252 u8 op_mod[0x10]; 5253 5254 u8 other_vport[0x1]; 5255 u8 reserved_at_41[0xf]; 5256 u8 vport_number[0x10]; 5257 5258 u8 reserved_at_60[0x20]; 5259 }; 5260 5261 struct mlx5_ifc_query_vport_counter_out_bits { 5262 u8 status[0x8]; 5263 u8 reserved_at_8[0x18]; 5264 5265 u8 syndrome[0x20]; 5266 5267 u8 reserved_at_40[0x40]; 5268 5269 struct mlx5_ifc_traffic_counter_bits received_errors; 5270 5271 struct mlx5_ifc_traffic_counter_bits transmit_errors; 5272 5273 struct mlx5_ifc_traffic_counter_bits received_ib_unicast; 5274 5275 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast; 5276 5277 struct mlx5_ifc_traffic_counter_bits received_ib_multicast; 5278 5279 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast; 5280 5281 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast; 5282 5283 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast; 5284 5285 struct mlx5_ifc_traffic_counter_bits received_eth_unicast; 5286 5287 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast; 5288 5289 struct mlx5_ifc_traffic_counter_bits received_eth_multicast; 5290 5291 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast; 5292 5293 struct mlx5_ifc_traffic_counter_bits local_loopback; 5294 5295 u8 reserved_at_700[0x980]; 5296 }; 5297 5298 enum { 5299 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0, 5300 }; 5301 5302 struct mlx5_ifc_query_vport_counter_in_bits { 5303 u8 opcode[0x10]; 5304 u8 reserved_at_10[0x10]; 5305 5306 u8 reserved_at_20[0x10]; 5307 u8 op_mod[0x10]; 5308 5309 u8 other_vport[0x1]; 5310 u8 reserved_at_41[0xb]; 5311 u8 port_num[0x4]; 5312 u8 vport_number[0x10]; 5313 5314 u8 reserved_at_60[0x60]; 5315 5316 u8 clear[0x1]; 5317 u8 reserved_at_c1[0x1f]; 5318 5319 u8 reserved_at_e0[0x20]; 5320 }; 5321 5322 struct mlx5_ifc_query_tis_out_bits { 5323 u8 status[0x8]; 5324 u8 reserved_at_8[0x18]; 5325 5326 u8 syndrome[0x20]; 5327 5328 u8 reserved_at_40[0x40]; 5329 5330 struct mlx5_ifc_tisc_bits tis_context; 5331 }; 5332 5333 struct mlx5_ifc_query_tis_in_bits { 5334 u8 opcode[0x10]; 5335 u8 reserved_at_10[0x10]; 5336 5337 u8 reserved_at_20[0x10]; 5338 u8 op_mod[0x10]; 5339 5340 u8 reserved_at_40[0x8]; 5341 u8 tisn[0x18]; 5342 5343 u8 reserved_at_60[0x20]; 5344 }; 5345 5346 struct mlx5_ifc_query_tir_out_bits { 5347 u8 status[0x8]; 5348 u8 reserved_at_8[0x18]; 5349 5350 u8 syndrome[0x20]; 5351 5352 u8 reserved_at_40[0xc0]; 5353 5354 struct mlx5_ifc_tirc_bits tir_context; 5355 }; 5356 5357 struct mlx5_ifc_query_tir_in_bits { 5358 u8 opcode[0x10]; 5359 u8 reserved_at_10[0x10]; 5360 5361 u8 reserved_at_20[0x10]; 5362 u8 op_mod[0x10]; 5363 5364 u8 reserved_at_40[0x8]; 5365 u8 tirn[0x18]; 5366 5367 u8 reserved_at_60[0x20]; 5368 }; 5369 5370 struct mlx5_ifc_query_srq_out_bits { 5371 u8 status[0x8]; 5372 u8 reserved_at_8[0x18]; 5373 5374 u8 syndrome[0x20]; 5375 5376 u8 reserved_at_40[0x40]; 5377 5378 struct mlx5_ifc_srqc_bits srq_context_entry; 5379 5380 u8 reserved_at_280[0x600]; 5381 5382 u8 pas[][0x40]; 5383 }; 5384 5385 struct mlx5_ifc_query_srq_in_bits { 5386 u8 opcode[0x10]; 5387 u8 reserved_at_10[0x10]; 5388 5389 u8 reserved_at_20[0x10]; 5390 u8 op_mod[0x10]; 5391 5392 u8 reserved_at_40[0x8]; 5393 u8 srqn[0x18]; 5394 5395 u8 reserved_at_60[0x20]; 5396 }; 5397 5398 struct mlx5_ifc_query_sq_out_bits { 5399 u8 status[0x8]; 5400 u8 reserved_at_8[0x18]; 5401 5402 u8 syndrome[0x20]; 5403 5404 u8 reserved_at_40[0xc0]; 5405 5406 struct mlx5_ifc_sqc_bits sq_context; 5407 }; 5408 5409 struct mlx5_ifc_query_sq_in_bits { 5410 u8 opcode[0x10]; 5411 u8 reserved_at_10[0x10]; 5412 5413 u8 reserved_at_20[0x10]; 5414 u8 op_mod[0x10]; 5415 5416 u8 reserved_at_40[0x8]; 5417 u8 sqn[0x18]; 5418 5419 u8 reserved_at_60[0x20]; 5420 }; 5421 5422 struct mlx5_ifc_query_special_contexts_out_bits { 5423 u8 status[0x8]; 5424 u8 reserved_at_8[0x18]; 5425 5426 u8 syndrome[0x20]; 5427 5428 u8 dump_fill_mkey[0x20]; 5429 5430 u8 resd_lkey[0x20]; 5431 5432 u8 null_mkey[0x20]; 5433 5434 u8 terminate_scatter_list_mkey[0x20]; 5435 5436 u8 repeated_mkey[0x20]; 5437 5438 u8 reserved_at_a0[0x20]; 5439 }; 5440 5441 struct mlx5_ifc_query_special_contexts_in_bits { 5442 u8 opcode[0x10]; 5443 u8 reserved_at_10[0x10]; 5444 5445 u8 reserved_at_20[0x10]; 5446 u8 op_mod[0x10]; 5447 5448 u8 reserved_at_40[0x40]; 5449 }; 5450 5451 struct mlx5_ifc_query_scheduling_element_out_bits { 5452 u8 opcode[0x10]; 5453 u8 reserved_at_10[0x10]; 5454 5455 u8 reserved_at_20[0x10]; 5456 u8 op_mod[0x10]; 5457 5458 u8 reserved_at_40[0xc0]; 5459 5460 struct mlx5_ifc_scheduling_context_bits scheduling_context; 5461 5462 u8 reserved_at_300[0x100]; 5463 }; 5464 5465 enum { 5466 SCHEDULING_HIERARCHY_E_SWITCH = 0x2, 5467 SCHEDULING_HIERARCHY_NIC = 0x3, 5468 }; 5469 5470 struct mlx5_ifc_query_scheduling_element_in_bits { 5471 u8 opcode[0x10]; 5472 u8 reserved_at_10[0x10]; 5473 5474 u8 reserved_at_20[0x10]; 5475 u8 op_mod[0x10]; 5476 5477 u8 scheduling_hierarchy[0x8]; 5478 u8 reserved_at_48[0x18]; 5479 5480 u8 scheduling_element_id[0x20]; 5481 5482 u8 reserved_at_80[0x180]; 5483 }; 5484 5485 struct mlx5_ifc_query_rqt_out_bits { 5486 u8 status[0x8]; 5487 u8 reserved_at_8[0x18]; 5488 5489 u8 syndrome[0x20]; 5490 5491 u8 reserved_at_40[0xc0]; 5492 5493 struct mlx5_ifc_rqtc_bits rqt_context; 5494 }; 5495 5496 struct mlx5_ifc_query_rqt_in_bits { 5497 u8 opcode[0x10]; 5498 u8 reserved_at_10[0x10]; 5499 5500 u8 reserved_at_20[0x10]; 5501 u8 op_mod[0x10]; 5502 5503 u8 reserved_at_40[0x8]; 5504 u8 rqtn[0x18]; 5505 5506 u8 reserved_at_60[0x20]; 5507 }; 5508 5509 struct mlx5_ifc_query_rq_out_bits { 5510 u8 status[0x8]; 5511 u8 reserved_at_8[0x18]; 5512 5513 u8 syndrome[0x20]; 5514 5515 u8 reserved_at_40[0xc0]; 5516 5517 struct mlx5_ifc_rqc_bits rq_context; 5518 }; 5519 5520 struct mlx5_ifc_query_rq_in_bits { 5521 u8 opcode[0x10]; 5522 u8 reserved_at_10[0x10]; 5523 5524 u8 reserved_at_20[0x10]; 5525 u8 op_mod[0x10]; 5526 5527 u8 reserved_at_40[0x8]; 5528 u8 rqn[0x18]; 5529 5530 u8 reserved_at_60[0x20]; 5531 }; 5532 5533 struct mlx5_ifc_query_roce_address_out_bits { 5534 u8 status[0x8]; 5535 u8 reserved_at_8[0x18]; 5536 5537 u8 syndrome[0x20]; 5538 5539 u8 reserved_at_40[0x40]; 5540 5541 struct mlx5_ifc_roce_addr_layout_bits roce_address; 5542 }; 5543 5544 struct mlx5_ifc_query_roce_address_in_bits { 5545 u8 opcode[0x10]; 5546 u8 reserved_at_10[0x10]; 5547 5548 u8 reserved_at_20[0x10]; 5549 u8 op_mod[0x10]; 5550 5551 u8 roce_address_index[0x10]; 5552 u8 reserved_at_50[0xc]; 5553 u8 vhca_port_num[0x4]; 5554 5555 u8 reserved_at_60[0x20]; 5556 }; 5557 5558 struct mlx5_ifc_query_rmp_out_bits { 5559 u8 status[0x8]; 5560 u8 reserved_at_8[0x18]; 5561 5562 u8 syndrome[0x20]; 5563 5564 u8 reserved_at_40[0xc0]; 5565 5566 struct mlx5_ifc_rmpc_bits rmp_context; 5567 }; 5568 5569 struct mlx5_ifc_query_rmp_in_bits { 5570 u8 opcode[0x10]; 5571 u8 reserved_at_10[0x10]; 5572 5573 u8 reserved_at_20[0x10]; 5574 u8 op_mod[0x10]; 5575 5576 u8 reserved_at_40[0x8]; 5577 u8 rmpn[0x18]; 5578 5579 u8 reserved_at_60[0x20]; 5580 }; 5581 5582 struct mlx5_ifc_cqe_error_syndrome_bits { 5583 u8 hw_error_syndrome[0x8]; 5584 u8 hw_syndrome_type[0x4]; 5585 u8 reserved_at_c[0x4]; 5586 u8 vendor_error_syndrome[0x8]; 5587 u8 syndrome[0x8]; 5588 }; 5589 5590 struct mlx5_ifc_qp_context_extension_bits { 5591 u8 reserved_at_0[0x60]; 5592 5593 struct mlx5_ifc_cqe_error_syndrome_bits error_syndrome; 5594 5595 u8 reserved_at_80[0x580]; 5596 }; 5597 5598 struct mlx5_ifc_qpc_extension_and_pas_list_in_bits { 5599 struct mlx5_ifc_qp_context_extension_bits qpc_data_extension; 5600 5601 u8 pas[0][0x40]; 5602 }; 5603 5604 struct mlx5_ifc_qp_pas_list_in_bits { 5605 struct mlx5_ifc_cmd_pas_bits pas[0]; 5606 }; 5607 5608 union mlx5_ifc_qp_pas_or_qpc_ext_and_pas_bits { 5609 struct mlx5_ifc_qp_pas_list_in_bits qp_pas_list; 5610 struct mlx5_ifc_qpc_extension_and_pas_list_in_bits qpc_ext_and_pas_list; 5611 }; 5612 5613 struct mlx5_ifc_query_qp_out_bits { 5614 u8 status[0x8]; 5615 u8 reserved_at_8[0x18]; 5616 5617 u8 syndrome[0x20]; 5618 5619 u8 reserved_at_40[0x40]; 5620 5621 u8 opt_param_mask[0x20]; 5622 5623 u8 ece[0x20]; 5624 5625 struct mlx5_ifc_qpc_bits qpc; 5626 5627 u8 reserved_at_800[0x80]; 5628 5629 union mlx5_ifc_qp_pas_or_qpc_ext_and_pas_bits qp_pas_or_qpc_ext_and_pas; 5630 }; 5631 5632 struct mlx5_ifc_query_qp_in_bits { 5633 u8 opcode[0x10]; 5634 u8 reserved_at_10[0x10]; 5635 5636 u8 reserved_at_20[0x10]; 5637 u8 op_mod[0x10]; 5638 5639 u8 qpc_ext[0x1]; 5640 u8 reserved_at_41[0x7]; 5641 u8 qpn[0x18]; 5642 5643 u8 reserved_at_60[0x20]; 5644 }; 5645 5646 struct mlx5_ifc_query_q_counter_out_bits { 5647 u8 status[0x8]; 5648 u8 reserved_at_8[0x18]; 5649 5650 u8 syndrome[0x20]; 5651 5652 u8 reserved_at_40[0x40]; 5653 5654 u8 rx_write_requests[0x20]; 5655 5656 u8 reserved_at_a0[0x20]; 5657 5658 u8 rx_read_requests[0x20]; 5659 5660 u8 reserved_at_e0[0x20]; 5661 5662 u8 rx_atomic_requests[0x20]; 5663 5664 u8 reserved_at_120[0x20]; 5665 5666 u8 rx_dct_connect[0x20]; 5667 5668 u8 reserved_at_160[0x20]; 5669 5670 u8 out_of_buffer[0x20]; 5671 5672 u8 reserved_at_1a0[0x20]; 5673 5674 u8 out_of_sequence[0x20]; 5675 5676 u8 reserved_at_1e0[0x20]; 5677 5678 u8 duplicate_request[0x20]; 5679 5680 u8 reserved_at_220[0x20]; 5681 5682 u8 rnr_nak_retry_err[0x20]; 5683 5684 u8 reserved_at_260[0x20]; 5685 5686 u8 packet_seq_err[0x20]; 5687 5688 u8 reserved_at_2a0[0x20]; 5689 5690 u8 implied_nak_seq_err[0x20]; 5691 5692 u8 reserved_at_2e0[0x20]; 5693 5694 u8 local_ack_timeout_err[0x20]; 5695 5696 u8 reserved_at_320[0x60]; 5697 5698 u8 req_rnr_retries_exceeded[0x20]; 5699 5700 u8 reserved_at_3a0[0x20]; 5701 5702 u8 resp_local_length_error[0x20]; 5703 5704 u8 req_local_length_error[0x20]; 5705 5706 u8 resp_local_qp_error[0x20]; 5707 5708 u8 local_operation_error[0x20]; 5709 5710 u8 resp_local_protection[0x20]; 5711 5712 u8 req_local_protection[0x20]; 5713 5714 u8 resp_cqe_error[0x20]; 5715 5716 u8 req_cqe_error[0x20]; 5717 5718 u8 req_mw_binding[0x20]; 5719 5720 u8 req_bad_response[0x20]; 5721 5722 u8 req_remote_invalid_request[0x20]; 5723 5724 u8 resp_remote_invalid_request[0x20]; 5725 5726 u8 req_remote_access_errors[0x20]; 5727 5728 u8 resp_remote_access_errors[0x20]; 5729 5730 u8 req_remote_operation_errors[0x20]; 5731 5732 u8 req_transport_retries_exceeded[0x20]; 5733 5734 u8 cq_overflow[0x20]; 5735 5736 u8 resp_cqe_flush_error[0x20]; 5737 5738 u8 req_cqe_flush_error[0x20]; 5739 5740 u8 reserved_at_620[0x20]; 5741 5742 u8 roce_adp_retrans[0x20]; 5743 5744 u8 roce_adp_retrans_to[0x20]; 5745 5746 u8 roce_slow_restart[0x20]; 5747 5748 u8 roce_slow_restart_cnps[0x20]; 5749 5750 u8 roce_slow_restart_trans[0x20]; 5751 5752 u8 reserved_at_6e0[0x120]; 5753 }; 5754 5755 struct mlx5_ifc_query_q_counter_in_bits { 5756 u8 opcode[0x10]; 5757 u8 reserved_at_10[0x10]; 5758 5759 u8 reserved_at_20[0x10]; 5760 u8 op_mod[0x10]; 5761 5762 u8 other_vport[0x1]; 5763 u8 reserved_at_41[0xf]; 5764 u8 vport_number[0x10]; 5765 5766 u8 reserved_at_60[0x60]; 5767 5768 u8 clear[0x1]; 5769 u8 aggregate[0x1]; 5770 u8 reserved_at_c2[0x1e]; 5771 5772 u8 reserved_at_e0[0x18]; 5773 u8 counter_set_id[0x8]; 5774 }; 5775 5776 struct mlx5_ifc_query_pages_out_bits { 5777 u8 status[0x8]; 5778 u8 reserved_at_8[0x18]; 5779 5780 u8 syndrome[0x20]; 5781 5782 u8 embedded_cpu_function[0x1]; 5783 u8 reserved_at_41[0xf]; 5784 u8 function_id[0x10]; 5785 5786 u8 num_pages[0x20]; 5787 }; 5788 5789 enum { 5790 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1, 5791 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2, 5792 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3, 5793 }; 5794 5795 struct mlx5_ifc_query_pages_in_bits { 5796 u8 opcode[0x10]; 5797 u8 reserved_at_10[0x10]; 5798 5799 u8 reserved_at_20[0x10]; 5800 u8 op_mod[0x10]; 5801 5802 u8 embedded_cpu_function[0x1]; 5803 u8 reserved_at_41[0xf]; 5804 u8 function_id[0x10]; 5805 5806 u8 reserved_at_60[0x20]; 5807 }; 5808 5809 struct mlx5_ifc_query_nic_vport_context_out_bits { 5810 u8 status[0x8]; 5811 u8 reserved_at_8[0x18]; 5812 5813 u8 syndrome[0x20]; 5814 5815 u8 reserved_at_40[0x40]; 5816 5817 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 5818 }; 5819 5820 struct mlx5_ifc_query_nic_vport_context_in_bits { 5821 u8 opcode[0x10]; 5822 u8 reserved_at_10[0x10]; 5823 5824 u8 reserved_at_20[0x10]; 5825 u8 op_mod[0x10]; 5826 5827 u8 other_vport[0x1]; 5828 u8 reserved_at_41[0xf]; 5829 u8 vport_number[0x10]; 5830 5831 u8 reserved_at_60[0x5]; 5832 u8 allowed_list_type[0x3]; 5833 u8 reserved_at_68[0x18]; 5834 }; 5835 5836 struct mlx5_ifc_query_mkey_out_bits { 5837 u8 status[0x8]; 5838 u8 reserved_at_8[0x18]; 5839 5840 u8 syndrome[0x20]; 5841 5842 u8 reserved_at_40[0x40]; 5843 5844 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 5845 5846 u8 reserved_at_280[0x600]; 5847 5848 u8 bsf0_klm0_pas_mtt0_1[16][0x8]; 5849 5850 u8 bsf1_klm1_pas_mtt2_3[16][0x8]; 5851 }; 5852 5853 struct mlx5_ifc_query_mkey_in_bits { 5854 u8 opcode[0x10]; 5855 u8 reserved_at_10[0x10]; 5856 5857 u8 reserved_at_20[0x10]; 5858 u8 op_mod[0x10]; 5859 5860 u8 reserved_at_40[0x8]; 5861 u8 mkey_index[0x18]; 5862 5863 u8 pg_access[0x1]; 5864 u8 reserved_at_61[0x1f]; 5865 }; 5866 5867 struct mlx5_ifc_query_mad_demux_out_bits { 5868 u8 status[0x8]; 5869 u8 reserved_at_8[0x18]; 5870 5871 u8 syndrome[0x20]; 5872 5873 u8 reserved_at_40[0x40]; 5874 5875 u8 mad_dumux_parameters_block[0x20]; 5876 }; 5877 5878 struct mlx5_ifc_query_mad_demux_in_bits { 5879 u8 opcode[0x10]; 5880 u8 reserved_at_10[0x10]; 5881 5882 u8 reserved_at_20[0x10]; 5883 u8 op_mod[0x10]; 5884 5885 u8 reserved_at_40[0x40]; 5886 }; 5887 5888 struct mlx5_ifc_query_l2_table_entry_out_bits { 5889 u8 status[0x8]; 5890 u8 reserved_at_8[0x18]; 5891 5892 u8 syndrome[0x20]; 5893 5894 u8 reserved_at_40[0xa0]; 5895 5896 u8 reserved_at_e0[0x13]; 5897 u8 vlan_valid[0x1]; 5898 u8 vlan[0xc]; 5899 5900 struct mlx5_ifc_mac_address_layout_bits mac_address; 5901 5902 u8 reserved_at_140[0xc0]; 5903 }; 5904 5905 struct mlx5_ifc_query_l2_table_entry_in_bits { 5906 u8 opcode[0x10]; 5907 u8 reserved_at_10[0x10]; 5908 5909 u8 reserved_at_20[0x10]; 5910 u8 op_mod[0x10]; 5911 5912 u8 reserved_at_40[0x60]; 5913 5914 u8 reserved_at_a0[0x8]; 5915 u8 table_index[0x18]; 5916 5917 u8 reserved_at_c0[0x140]; 5918 }; 5919 5920 struct mlx5_ifc_query_issi_out_bits { 5921 u8 status[0x8]; 5922 u8 reserved_at_8[0x18]; 5923 5924 u8 syndrome[0x20]; 5925 5926 u8 reserved_at_40[0x10]; 5927 u8 current_issi[0x10]; 5928 5929 u8 reserved_at_60[0xa0]; 5930 5931 u8 reserved_at_100[76][0x8]; 5932 u8 supported_issi_dw0[0x20]; 5933 }; 5934 5935 struct mlx5_ifc_query_issi_in_bits { 5936 u8 opcode[0x10]; 5937 u8 reserved_at_10[0x10]; 5938 5939 u8 reserved_at_20[0x10]; 5940 u8 op_mod[0x10]; 5941 5942 u8 reserved_at_40[0x40]; 5943 }; 5944 5945 struct mlx5_ifc_set_driver_version_out_bits { 5946 u8 status[0x8]; 5947 u8 reserved_0[0x18]; 5948 5949 u8 syndrome[0x20]; 5950 u8 reserved_1[0x40]; 5951 }; 5952 5953 struct mlx5_ifc_set_driver_version_in_bits { 5954 u8 opcode[0x10]; 5955 u8 reserved_0[0x10]; 5956 5957 u8 reserved_1[0x10]; 5958 u8 op_mod[0x10]; 5959 5960 u8 reserved_2[0x40]; 5961 u8 driver_version[64][0x8]; 5962 }; 5963 5964 struct mlx5_ifc_query_hca_vport_pkey_out_bits { 5965 u8 status[0x8]; 5966 u8 reserved_at_8[0x18]; 5967 5968 u8 syndrome[0x20]; 5969 5970 u8 reserved_at_40[0x40]; 5971 5972 struct mlx5_ifc_pkey_bits pkey[]; 5973 }; 5974 5975 struct mlx5_ifc_query_hca_vport_pkey_in_bits { 5976 u8 opcode[0x10]; 5977 u8 reserved_at_10[0x10]; 5978 5979 u8 reserved_at_20[0x10]; 5980 u8 op_mod[0x10]; 5981 5982 u8 other_vport[0x1]; 5983 u8 reserved_at_41[0xb]; 5984 u8 port_num[0x4]; 5985 u8 vport_number[0x10]; 5986 5987 u8 reserved_at_60[0x10]; 5988 u8 pkey_index[0x10]; 5989 }; 5990 5991 enum { 5992 MLX5_HCA_VPORT_SEL_PORT_GUID = 1 << 0, 5993 MLX5_HCA_VPORT_SEL_NODE_GUID = 1 << 1, 5994 MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2, 5995 }; 5996 5997 struct mlx5_ifc_query_hca_vport_gid_out_bits { 5998 u8 status[0x8]; 5999 u8 reserved_at_8[0x18]; 6000 6001 u8 syndrome[0x20]; 6002 6003 u8 reserved_at_40[0x20]; 6004 6005 u8 gids_num[0x10]; 6006 u8 reserved_at_70[0x10]; 6007 6008 struct mlx5_ifc_array128_auto_bits gid[]; 6009 }; 6010 6011 struct mlx5_ifc_query_hca_vport_gid_in_bits { 6012 u8 opcode[0x10]; 6013 u8 reserved_at_10[0x10]; 6014 6015 u8 reserved_at_20[0x10]; 6016 u8 op_mod[0x10]; 6017 6018 u8 other_vport[0x1]; 6019 u8 reserved_at_41[0xb]; 6020 u8 port_num[0x4]; 6021 u8 vport_number[0x10]; 6022 6023 u8 reserved_at_60[0x10]; 6024 u8 gid_index[0x10]; 6025 }; 6026 6027 struct mlx5_ifc_query_hca_vport_context_out_bits { 6028 u8 status[0x8]; 6029 u8 reserved_at_8[0x18]; 6030 6031 u8 syndrome[0x20]; 6032 6033 u8 reserved_at_40[0x40]; 6034 6035 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 6036 }; 6037 6038 struct mlx5_ifc_query_hca_vport_context_in_bits { 6039 u8 opcode[0x10]; 6040 u8 reserved_at_10[0x10]; 6041 6042 u8 reserved_at_20[0x10]; 6043 u8 op_mod[0x10]; 6044 6045 u8 other_vport[0x1]; 6046 u8 reserved_at_41[0xb]; 6047 u8 port_num[0x4]; 6048 u8 vport_number[0x10]; 6049 6050 u8 reserved_at_60[0x20]; 6051 }; 6052 6053 struct mlx5_ifc_query_hca_cap_out_bits { 6054 u8 status[0x8]; 6055 u8 reserved_at_8[0x18]; 6056 6057 u8 syndrome[0x20]; 6058 6059 u8 reserved_at_40[0x40]; 6060 6061 union mlx5_ifc_hca_cap_union_bits capability; 6062 }; 6063 6064 struct mlx5_ifc_query_hca_cap_in_bits { 6065 u8 opcode[0x10]; 6066 u8 reserved_at_10[0x10]; 6067 6068 u8 reserved_at_20[0x10]; 6069 u8 op_mod[0x10]; 6070 6071 u8 other_function[0x1]; 6072 u8 ec_vf_function[0x1]; 6073 u8 reserved_at_42[0xe]; 6074 u8 function_id[0x10]; 6075 6076 u8 reserved_at_60[0x20]; 6077 }; 6078 6079 struct mlx5_ifc_other_hca_cap_bits { 6080 u8 roce[0x1]; 6081 u8 reserved_at_1[0x27f]; 6082 }; 6083 6084 struct mlx5_ifc_query_other_hca_cap_out_bits { 6085 u8 status[0x8]; 6086 u8 reserved_at_8[0x18]; 6087 6088 u8 syndrome[0x20]; 6089 6090 u8 reserved_at_40[0x40]; 6091 6092 struct mlx5_ifc_other_hca_cap_bits other_capability; 6093 }; 6094 6095 struct mlx5_ifc_query_other_hca_cap_in_bits { 6096 u8 opcode[0x10]; 6097 u8 reserved_at_10[0x10]; 6098 6099 u8 reserved_at_20[0x10]; 6100 u8 op_mod[0x10]; 6101 6102 u8 reserved_at_40[0x10]; 6103 u8 function_id[0x10]; 6104 6105 u8 reserved_at_60[0x20]; 6106 }; 6107 6108 struct mlx5_ifc_modify_other_hca_cap_out_bits { 6109 u8 status[0x8]; 6110 u8 reserved_at_8[0x18]; 6111 6112 u8 syndrome[0x20]; 6113 6114 u8 reserved_at_40[0x40]; 6115 }; 6116 6117 struct mlx5_ifc_modify_other_hca_cap_in_bits { 6118 u8 opcode[0x10]; 6119 u8 reserved_at_10[0x10]; 6120 6121 u8 reserved_at_20[0x10]; 6122 u8 op_mod[0x10]; 6123 6124 u8 reserved_at_40[0x10]; 6125 u8 function_id[0x10]; 6126 u8 field_select[0x20]; 6127 6128 struct mlx5_ifc_other_hca_cap_bits other_capability; 6129 }; 6130 6131 struct mlx5_ifc_flow_table_context_bits { 6132 u8 reformat_en[0x1]; 6133 u8 decap_en[0x1]; 6134 u8 sw_owner[0x1]; 6135 u8 termination_table[0x1]; 6136 u8 table_miss_action[0x4]; 6137 u8 level[0x8]; 6138 u8 reserved_at_10[0x8]; 6139 u8 log_size[0x8]; 6140 6141 u8 reserved_at_20[0x8]; 6142 u8 table_miss_id[0x18]; 6143 6144 u8 reserved_at_40[0x8]; 6145 u8 lag_master_next_table_id[0x18]; 6146 6147 u8 reserved_at_60[0x60]; 6148 6149 u8 sw_owner_icm_root_1[0x40]; 6150 6151 u8 sw_owner_icm_root_0[0x40]; 6152 6153 }; 6154 6155 struct mlx5_ifc_query_flow_table_out_bits { 6156 u8 status[0x8]; 6157 u8 reserved_at_8[0x18]; 6158 6159 u8 syndrome[0x20]; 6160 6161 u8 reserved_at_40[0x80]; 6162 6163 struct mlx5_ifc_flow_table_context_bits flow_table_context; 6164 }; 6165 6166 struct mlx5_ifc_query_flow_table_in_bits { 6167 u8 opcode[0x10]; 6168 u8 reserved_at_10[0x10]; 6169 6170 u8 reserved_at_20[0x10]; 6171 u8 op_mod[0x10]; 6172 6173 u8 reserved_at_40[0x40]; 6174 6175 u8 table_type[0x8]; 6176 u8 reserved_at_88[0x18]; 6177 6178 u8 reserved_at_a0[0x8]; 6179 u8 table_id[0x18]; 6180 6181 u8 reserved_at_c0[0x140]; 6182 }; 6183 6184 struct mlx5_ifc_query_fte_out_bits { 6185 u8 status[0x8]; 6186 u8 reserved_at_8[0x18]; 6187 6188 u8 syndrome[0x20]; 6189 6190 u8 reserved_at_40[0x1c0]; 6191 6192 struct mlx5_ifc_flow_context_bits flow_context; 6193 }; 6194 6195 struct mlx5_ifc_query_fte_in_bits { 6196 u8 opcode[0x10]; 6197 u8 reserved_at_10[0x10]; 6198 6199 u8 reserved_at_20[0x10]; 6200 u8 op_mod[0x10]; 6201 6202 u8 reserved_at_40[0x40]; 6203 6204 u8 table_type[0x8]; 6205 u8 reserved_at_88[0x18]; 6206 6207 u8 reserved_at_a0[0x8]; 6208 u8 table_id[0x18]; 6209 6210 u8 reserved_at_c0[0x40]; 6211 6212 u8 flow_index[0x20]; 6213 6214 u8 reserved_at_120[0xe0]; 6215 }; 6216 6217 struct mlx5_ifc_match_definer_format_0_bits { 6218 u8 reserved_at_0[0x100]; 6219 6220 u8 metadata_reg_c_0[0x20]; 6221 6222 u8 metadata_reg_c_1[0x20]; 6223 6224 u8 outer_dmac_47_16[0x20]; 6225 6226 u8 outer_dmac_15_0[0x10]; 6227 u8 outer_ethertype[0x10]; 6228 6229 u8 reserved_at_180[0x1]; 6230 u8 sx_sniffer[0x1]; 6231 u8 functional_lb[0x1]; 6232 u8 outer_ip_frag[0x1]; 6233 u8 outer_qp_type[0x2]; 6234 u8 outer_encap_type[0x2]; 6235 u8 port_number[0x2]; 6236 u8 outer_l3_type[0x2]; 6237 u8 outer_l4_type[0x2]; 6238 u8 outer_first_vlan_type[0x2]; 6239 u8 outer_first_vlan_prio[0x3]; 6240 u8 outer_first_vlan_cfi[0x1]; 6241 u8 outer_first_vlan_vid[0xc]; 6242 6243 u8 outer_l4_type_ext[0x4]; 6244 u8 reserved_at_1a4[0x2]; 6245 u8 outer_ipsec_layer[0x2]; 6246 u8 outer_l2_type[0x2]; 6247 u8 force_lb[0x1]; 6248 u8 outer_l2_ok[0x1]; 6249 u8 outer_l3_ok[0x1]; 6250 u8 outer_l4_ok[0x1]; 6251 u8 outer_second_vlan_type[0x2]; 6252 u8 outer_second_vlan_prio[0x3]; 6253 u8 outer_second_vlan_cfi[0x1]; 6254 u8 outer_second_vlan_vid[0xc]; 6255 6256 u8 outer_smac_47_16[0x20]; 6257 6258 u8 outer_smac_15_0[0x10]; 6259 u8 inner_ipv4_checksum_ok[0x1]; 6260 u8 inner_l4_checksum_ok[0x1]; 6261 u8 outer_ipv4_checksum_ok[0x1]; 6262 u8 outer_l4_checksum_ok[0x1]; 6263 u8 inner_l3_ok[0x1]; 6264 u8 inner_l4_ok[0x1]; 6265 u8 outer_l3_ok_duplicate[0x1]; 6266 u8 outer_l4_ok_duplicate[0x1]; 6267 u8 outer_tcp_cwr[0x1]; 6268 u8 outer_tcp_ece[0x1]; 6269 u8 outer_tcp_urg[0x1]; 6270 u8 outer_tcp_ack[0x1]; 6271 u8 outer_tcp_psh[0x1]; 6272 u8 outer_tcp_rst[0x1]; 6273 u8 outer_tcp_syn[0x1]; 6274 u8 outer_tcp_fin[0x1]; 6275 }; 6276 6277 struct mlx5_ifc_match_definer_format_22_bits { 6278 u8 reserved_at_0[0x100]; 6279 6280 u8 outer_ip_src_addr[0x20]; 6281 6282 u8 outer_ip_dest_addr[0x20]; 6283 6284 u8 outer_l4_sport[0x10]; 6285 u8 outer_l4_dport[0x10]; 6286 6287 u8 reserved_at_160[0x1]; 6288 u8 sx_sniffer[0x1]; 6289 u8 functional_lb[0x1]; 6290 u8 outer_ip_frag[0x1]; 6291 u8 outer_qp_type[0x2]; 6292 u8 outer_encap_type[0x2]; 6293 u8 port_number[0x2]; 6294 u8 outer_l3_type[0x2]; 6295 u8 outer_l4_type[0x2]; 6296 u8 outer_first_vlan_type[0x2]; 6297 u8 outer_first_vlan_prio[0x3]; 6298 u8 outer_first_vlan_cfi[0x1]; 6299 u8 outer_first_vlan_vid[0xc]; 6300 6301 u8 metadata_reg_c_0[0x20]; 6302 6303 u8 outer_dmac_47_16[0x20]; 6304 6305 u8 outer_smac_47_16[0x20]; 6306 6307 u8 outer_smac_15_0[0x10]; 6308 u8 outer_dmac_15_0[0x10]; 6309 }; 6310 6311 struct mlx5_ifc_match_definer_format_23_bits { 6312 u8 reserved_at_0[0x100]; 6313 6314 u8 inner_ip_src_addr[0x20]; 6315 6316 u8 inner_ip_dest_addr[0x20]; 6317 6318 u8 inner_l4_sport[0x10]; 6319 u8 inner_l4_dport[0x10]; 6320 6321 u8 reserved_at_160[0x1]; 6322 u8 sx_sniffer[0x1]; 6323 u8 functional_lb[0x1]; 6324 u8 inner_ip_frag[0x1]; 6325 u8 inner_qp_type[0x2]; 6326 u8 inner_encap_type[0x2]; 6327 u8 port_number[0x2]; 6328 u8 inner_l3_type[0x2]; 6329 u8 inner_l4_type[0x2]; 6330 u8 inner_first_vlan_type[0x2]; 6331 u8 inner_first_vlan_prio[0x3]; 6332 u8 inner_first_vlan_cfi[0x1]; 6333 u8 inner_first_vlan_vid[0xc]; 6334 6335 u8 tunnel_header_0[0x20]; 6336 6337 u8 inner_dmac_47_16[0x20]; 6338 6339 u8 inner_smac_47_16[0x20]; 6340 6341 u8 inner_smac_15_0[0x10]; 6342 u8 inner_dmac_15_0[0x10]; 6343 }; 6344 6345 struct mlx5_ifc_match_definer_format_29_bits { 6346 u8 reserved_at_0[0xc0]; 6347 6348 u8 outer_ip_dest_addr[0x80]; 6349 6350 u8 outer_ip_src_addr[0x80]; 6351 6352 u8 outer_l4_sport[0x10]; 6353 u8 outer_l4_dport[0x10]; 6354 6355 u8 reserved_at_1e0[0x20]; 6356 }; 6357 6358 struct mlx5_ifc_match_definer_format_30_bits { 6359 u8 reserved_at_0[0xa0]; 6360 6361 u8 outer_ip_dest_addr[0x80]; 6362 6363 u8 outer_ip_src_addr[0x80]; 6364 6365 u8 outer_dmac_47_16[0x20]; 6366 6367 u8 outer_smac_47_16[0x20]; 6368 6369 u8 outer_smac_15_0[0x10]; 6370 u8 outer_dmac_15_0[0x10]; 6371 }; 6372 6373 struct mlx5_ifc_match_definer_format_31_bits { 6374 u8 reserved_at_0[0xc0]; 6375 6376 u8 inner_ip_dest_addr[0x80]; 6377 6378 u8 inner_ip_src_addr[0x80]; 6379 6380 u8 inner_l4_sport[0x10]; 6381 u8 inner_l4_dport[0x10]; 6382 6383 u8 reserved_at_1e0[0x20]; 6384 }; 6385 6386 struct mlx5_ifc_match_definer_format_32_bits { 6387 u8 reserved_at_0[0xa0]; 6388 6389 u8 inner_ip_dest_addr[0x80]; 6390 6391 u8 inner_ip_src_addr[0x80]; 6392 6393 u8 inner_dmac_47_16[0x20]; 6394 6395 u8 inner_smac_47_16[0x20]; 6396 6397 u8 inner_smac_15_0[0x10]; 6398 u8 inner_dmac_15_0[0x10]; 6399 }; 6400 6401 enum { 6402 MLX5_IFC_DEFINER_FORMAT_ID_SELECT = 61, 6403 }; 6404 6405 #define MLX5_IFC_DEFINER_FORMAT_OFFSET_UNUSED 0x0 6406 #define MLX5_IFC_DEFINER_FORMAT_OFFSET_OUTER_ETH_PKT_LEN 0x48 6407 #define MLX5_IFC_DEFINER_DW_SELECTORS_NUM 9 6408 #define MLX5_IFC_DEFINER_BYTE_SELECTORS_NUM 8 6409 6410 struct mlx5_ifc_match_definer_match_mask_bits { 6411 u8 reserved_at_1c0[5][0x20]; 6412 u8 match_dw_8[0x20]; 6413 u8 match_dw_7[0x20]; 6414 u8 match_dw_6[0x20]; 6415 u8 match_dw_5[0x20]; 6416 u8 match_dw_4[0x20]; 6417 u8 match_dw_3[0x20]; 6418 u8 match_dw_2[0x20]; 6419 u8 match_dw_1[0x20]; 6420 u8 match_dw_0[0x20]; 6421 6422 u8 match_byte_7[0x8]; 6423 u8 match_byte_6[0x8]; 6424 u8 match_byte_5[0x8]; 6425 u8 match_byte_4[0x8]; 6426 6427 u8 match_byte_3[0x8]; 6428 u8 match_byte_2[0x8]; 6429 u8 match_byte_1[0x8]; 6430 u8 match_byte_0[0x8]; 6431 }; 6432 6433 struct mlx5_ifc_match_definer_bits { 6434 u8 modify_field_select[0x40]; 6435 6436 u8 reserved_at_40[0x40]; 6437 6438 u8 reserved_at_80[0x10]; 6439 u8 format_id[0x10]; 6440 6441 u8 reserved_at_a0[0x60]; 6442 6443 u8 format_select_dw3[0x8]; 6444 u8 format_select_dw2[0x8]; 6445 u8 format_select_dw1[0x8]; 6446 u8 format_select_dw0[0x8]; 6447 6448 u8 format_select_dw7[0x8]; 6449 u8 format_select_dw6[0x8]; 6450 u8 format_select_dw5[0x8]; 6451 u8 format_select_dw4[0x8]; 6452 6453 u8 reserved_at_100[0x18]; 6454 u8 format_select_dw8[0x8]; 6455 6456 u8 reserved_at_120[0x20]; 6457 6458 u8 format_select_byte3[0x8]; 6459 u8 format_select_byte2[0x8]; 6460 u8 format_select_byte1[0x8]; 6461 u8 format_select_byte0[0x8]; 6462 6463 u8 format_select_byte7[0x8]; 6464 u8 format_select_byte6[0x8]; 6465 u8 format_select_byte5[0x8]; 6466 u8 format_select_byte4[0x8]; 6467 6468 u8 reserved_at_180[0x40]; 6469 6470 union { 6471 struct { 6472 u8 match_mask[16][0x20]; 6473 }; 6474 struct mlx5_ifc_match_definer_match_mask_bits match_mask_format; 6475 }; 6476 }; 6477 6478 struct mlx5_ifc_general_obj_create_param_bits { 6479 u8 alias_object[0x1]; 6480 u8 reserved_at_1[0x2]; 6481 u8 log_obj_range[0x5]; 6482 u8 reserved_at_8[0x18]; 6483 }; 6484 6485 struct mlx5_ifc_general_obj_query_param_bits { 6486 u8 alias_object[0x1]; 6487 u8 obj_offset[0x1f]; 6488 }; 6489 6490 struct mlx5_ifc_general_obj_in_cmd_hdr_bits { 6491 u8 opcode[0x10]; 6492 u8 uid[0x10]; 6493 6494 u8 vhca_tunnel_id[0x10]; 6495 u8 obj_type[0x10]; 6496 6497 u8 obj_id[0x20]; 6498 6499 union { 6500 struct mlx5_ifc_general_obj_create_param_bits create; 6501 struct mlx5_ifc_general_obj_query_param_bits query; 6502 } op_param; 6503 }; 6504 6505 struct mlx5_ifc_general_obj_out_cmd_hdr_bits { 6506 u8 status[0x8]; 6507 u8 reserved_at_8[0x18]; 6508 6509 u8 syndrome[0x20]; 6510 6511 u8 obj_id[0x20]; 6512 6513 u8 reserved_at_60[0x20]; 6514 }; 6515 6516 struct mlx5_ifc_allow_other_vhca_access_in_bits { 6517 u8 opcode[0x10]; 6518 u8 uid[0x10]; 6519 u8 reserved_at_20[0x10]; 6520 u8 op_mod[0x10]; 6521 u8 reserved_at_40[0x50]; 6522 u8 object_type_to_be_accessed[0x10]; 6523 u8 object_id_to_be_accessed[0x20]; 6524 u8 reserved_at_c0[0x40]; 6525 union { 6526 u8 access_key_raw[0x100]; 6527 u8 access_key[8][0x20]; 6528 }; 6529 }; 6530 6531 struct mlx5_ifc_allow_other_vhca_access_out_bits { 6532 u8 status[0x8]; 6533 u8 reserved_at_8[0x18]; 6534 u8 syndrome[0x20]; 6535 u8 reserved_at_40[0x40]; 6536 }; 6537 6538 struct mlx5_ifc_modify_header_arg_bits { 6539 u8 reserved_at_0[0x80]; 6540 6541 u8 reserved_at_80[0x8]; 6542 u8 access_pd[0x18]; 6543 }; 6544 6545 struct mlx5_ifc_create_modify_header_arg_in_bits { 6546 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 6547 struct mlx5_ifc_modify_header_arg_bits arg; 6548 }; 6549 6550 struct mlx5_ifc_create_match_definer_in_bits { 6551 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 6552 6553 struct mlx5_ifc_match_definer_bits obj_context; 6554 }; 6555 6556 struct mlx5_ifc_create_match_definer_out_bits { 6557 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 6558 }; 6559 6560 struct mlx5_ifc_alias_context_bits { 6561 u8 vhca_id_to_be_accessed[0x10]; 6562 u8 reserved_at_10[0xd]; 6563 u8 status[0x3]; 6564 u8 object_id_to_be_accessed[0x20]; 6565 u8 reserved_at_40[0x40]; 6566 union { 6567 u8 access_key_raw[0x100]; 6568 u8 access_key[8][0x20]; 6569 }; 6570 u8 metadata[0x80]; 6571 }; 6572 6573 struct mlx5_ifc_create_alias_obj_in_bits { 6574 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 6575 struct mlx5_ifc_alias_context_bits alias_ctx; 6576 }; 6577 6578 enum { 6579 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 6580 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 6581 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 6582 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3, 6583 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_3 = 0x4, 6584 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_4 = 0x5, 6585 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_5 = 0x6, 6586 }; 6587 6588 struct mlx5_ifc_query_flow_group_out_bits { 6589 u8 status[0x8]; 6590 u8 reserved_at_8[0x18]; 6591 6592 u8 syndrome[0x20]; 6593 6594 u8 reserved_at_40[0xa0]; 6595 6596 u8 start_flow_index[0x20]; 6597 6598 u8 reserved_at_100[0x20]; 6599 6600 u8 end_flow_index[0x20]; 6601 6602 u8 reserved_at_140[0xa0]; 6603 6604 u8 reserved_at_1e0[0x18]; 6605 u8 match_criteria_enable[0x8]; 6606 6607 struct mlx5_ifc_fte_match_param_bits match_criteria; 6608 6609 u8 reserved_at_1200[0xe00]; 6610 }; 6611 6612 struct mlx5_ifc_query_flow_group_in_bits { 6613 u8 opcode[0x10]; 6614 u8 reserved_at_10[0x10]; 6615 6616 u8 reserved_at_20[0x10]; 6617 u8 op_mod[0x10]; 6618 6619 u8 reserved_at_40[0x40]; 6620 6621 u8 table_type[0x8]; 6622 u8 reserved_at_88[0x18]; 6623 6624 u8 reserved_at_a0[0x8]; 6625 u8 table_id[0x18]; 6626 6627 u8 group_id[0x20]; 6628 6629 u8 reserved_at_e0[0x120]; 6630 }; 6631 6632 struct mlx5_ifc_query_flow_counter_out_bits { 6633 u8 status[0x8]; 6634 u8 reserved_at_8[0x18]; 6635 6636 u8 syndrome[0x20]; 6637 6638 u8 reserved_at_40[0x40]; 6639 6640 struct mlx5_ifc_traffic_counter_bits flow_statistics[]; 6641 }; 6642 6643 struct mlx5_ifc_query_flow_counter_in_bits { 6644 u8 opcode[0x10]; 6645 u8 reserved_at_10[0x10]; 6646 6647 u8 reserved_at_20[0x10]; 6648 u8 op_mod[0x10]; 6649 6650 u8 reserved_at_40[0x80]; 6651 6652 u8 clear[0x1]; 6653 u8 reserved_at_c1[0xf]; 6654 u8 num_of_counters[0x10]; 6655 6656 u8 flow_counter_id[0x20]; 6657 }; 6658 6659 struct mlx5_ifc_query_esw_vport_context_out_bits { 6660 u8 status[0x8]; 6661 u8 reserved_at_8[0x18]; 6662 6663 u8 syndrome[0x20]; 6664 6665 u8 reserved_at_40[0x40]; 6666 6667 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 6668 }; 6669 6670 struct mlx5_ifc_query_esw_vport_context_in_bits { 6671 u8 opcode[0x10]; 6672 u8 reserved_at_10[0x10]; 6673 6674 u8 reserved_at_20[0x10]; 6675 u8 op_mod[0x10]; 6676 6677 u8 other_vport[0x1]; 6678 u8 reserved_at_41[0xf]; 6679 u8 vport_number[0x10]; 6680 6681 u8 reserved_at_60[0x20]; 6682 }; 6683 6684 struct mlx5_ifc_modify_esw_vport_context_out_bits { 6685 u8 status[0x8]; 6686 u8 reserved_at_8[0x18]; 6687 6688 u8 syndrome[0x20]; 6689 6690 u8 reserved_at_40[0x40]; 6691 }; 6692 6693 struct mlx5_ifc_esw_vport_context_fields_select_bits { 6694 u8 reserved_at_0[0x1b]; 6695 u8 fdb_to_vport_reg_c_id[0x1]; 6696 u8 vport_cvlan_insert[0x1]; 6697 u8 vport_svlan_insert[0x1]; 6698 u8 vport_cvlan_strip[0x1]; 6699 u8 vport_svlan_strip[0x1]; 6700 }; 6701 6702 struct mlx5_ifc_modify_esw_vport_context_in_bits { 6703 u8 opcode[0x10]; 6704 u8 reserved_at_10[0x10]; 6705 6706 u8 reserved_at_20[0x10]; 6707 u8 op_mod[0x10]; 6708 6709 u8 other_vport[0x1]; 6710 u8 reserved_at_41[0xf]; 6711 u8 vport_number[0x10]; 6712 6713 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select; 6714 6715 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 6716 }; 6717 6718 struct mlx5_ifc_query_eq_out_bits { 6719 u8 status[0x8]; 6720 u8 reserved_at_8[0x18]; 6721 6722 u8 syndrome[0x20]; 6723 6724 u8 reserved_at_40[0x40]; 6725 6726 struct mlx5_ifc_eqc_bits eq_context_entry; 6727 6728 u8 reserved_at_280[0x40]; 6729 6730 u8 event_bitmask[0x40]; 6731 6732 u8 reserved_at_300[0x580]; 6733 6734 u8 pas[][0x40]; 6735 }; 6736 6737 struct mlx5_ifc_query_eq_in_bits { 6738 u8 opcode[0x10]; 6739 u8 reserved_at_10[0x10]; 6740 6741 u8 reserved_at_20[0x10]; 6742 u8 op_mod[0x10]; 6743 6744 u8 reserved_at_40[0x18]; 6745 u8 eq_number[0x8]; 6746 6747 u8 reserved_at_60[0x20]; 6748 }; 6749 6750 struct mlx5_ifc_packet_reformat_context_in_bits { 6751 u8 reformat_type[0x8]; 6752 u8 reserved_at_8[0x4]; 6753 u8 reformat_param_0[0x4]; 6754 u8 reserved_at_10[0x6]; 6755 u8 reformat_data_size[0xa]; 6756 6757 u8 reformat_param_1[0x8]; 6758 u8 reserved_at_28[0x8]; 6759 u8 reformat_data[2][0x8]; 6760 6761 u8 more_reformat_data[][0x8]; 6762 }; 6763 6764 struct mlx5_ifc_query_packet_reformat_context_out_bits { 6765 u8 status[0x8]; 6766 u8 reserved_at_8[0x18]; 6767 6768 u8 syndrome[0x20]; 6769 6770 u8 reserved_at_40[0xa0]; 6771 6772 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context[]; 6773 }; 6774 6775 struct mlx5_ifc_query_packet_reformat_context_in_bits { 6776 u8 opcode[0x10]; 6777 u8 reserved_at_10[0x10]; 6778 6779 u8 reserved_at_20[0x10]; 6780 u8 op_mod[0x10]; 6781 6782 u8 packet_reformat_id[0x20]; 6783 6784 u8 reserved_at_60[0xa0]; 6785 }; 6786 6787 struct mlx5_ifc_alloc_packet_reformat_context_out_bits { 6788 u8 status[0x8]; 6789 u8 reserved_at_8[0x18]; 6790 6791 u8 syndrome[0x20]; 6792 6793 u8 packet_reformat_id[0x20]; 6794 6795 u8 reserved_at_60[0x20]; 6796 }; 6797 6798 enum { 6799 MLX5_REFORMAT_CONTEXT_ANCHOR_MAC_START = 0x1, 6800 MLX5_REFORMAT_CONTEXT_ANCHOR_IP_START = 0x7, 6801 MLX5_REFORMAT_CONTEXT_ANCHOR_TCP_UDP_START = 0x9, 6802 }; 6803 6804 enum mlx5_reformat_ctx_type { 6805 MLX5_REFORMAT_TYPE_L2_TO_VXLAN = 0x0, 6806 MLX5_REFORMAT_TYPE_L2_TO_NVGRE = 0x1, 6807 MLX5_REFORMAT_TYPE_L2_TO_L2_TUNNEL = 0x2, 6808 MLX5_REFORMAT_TYPE_L3_TUNNEL_TO_L2 = 0x3, 6809 MLX5_REFORMAT_TYPE_L2_TO_L3_TUNNEL = 0x4, 6810 MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_IPV4 = 0x5, 6811 MLX5_REFORMAT_TYPE_L2_TO_L3_ESP_TUNNEL = 0x6, 6812 MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_UDPV4 = 0x7, 6813 MLX5_REFORMAT_TYPE_DEL_ESP_TRANSPORT = 0x8, 6814 MLX5_REFORMAT_TYPE_L3_ESP_TUNNEL_TO_L2 = 0x9, 6815 MLX5_REFORMAT_TYPE_DEL_ESP_TRANSPORT_OVER_UDP = 0xa, 6816 MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_IPV6 = 0xb, 6817 MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_UDPV6 = 0xc, 6818 MLX5_REFORMAT_TYPE_INSERT_HDR = 0xf, 6819 MLX5_REFORMAT_TYPE_REMOVE_HDR = 0x10, 6820 MLX5_REFORMAT_TYPE_ADD_MACSEC = 0x11, 6821 MLX5_REFORMAT_TYPE_DEL_MACSEC = 0x12, 6822 }; 6823 6824 struct mlx5_ifc_alloc_packet_reformat_context_in_bits { 6825 u8 opcode[0x10]; 6826 u8 reserved_at_10[0x10]; 6827 6828 u8 reserved_at_20[0x10]; 6829 u8 op_mod[0x10]; 6830 6831 u8 reserved_at_40[0xa0]; 6832 6833 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context; 6834 }; 6835 6836 struct mlx5_ifc_dealloc_packet_reformat_context_out_bits { 6837 u8 status[0x8]; 6838 u8 reserved_at_8[0x18]; 6839 6840 u8 syndrome[0x20]; 6841 6842 u8 reserved_at_40[0x40]; 6843 }; 6844 6845 struct mlx5_ifc_dealloc_packet_reformat_context_in_bits { 6846 u8 opcode[0x10]; 6847 u8 reserved_at_10[0x10]; 6848 6849 u8 reserved_20[0x10]; 6850 u8 op_mod[0x10]; 6851 6852 u8 packet_reformat_id[0x20]; 6853 6854 u8 reserved_60[0x20]; 6855 }; 6856 6857 struct mlx5_ifc_set_action_in_bits { 6858 u8 action_type[0x4]; 6859 u8 field[0xc]; 6860 u8 reserved_at_10[0x3]; 6861 u8 offset[0x5]; 6862 u8 reserved_at_18[0x3]; 6863 u8 length[0x5]; 6864 6865 u8 data[0x20]; 6866 }; 6867 6868 struct mlx5_ifc_add_action_in_bits { 6869 u8 action_type[0x4]; 6870 u8 field[0xc]; 6871 u8 reserved_at_10[0x10]; 6872 6873 u8 data[0x20]; 6874 }; 6875 6876 struct mlx5_ifc_copy_action_in_bits { 6877 u8 action_type[0x4]; 6878 u8 src_field[0xc]; 6879 u8 reserved_at_10[0x3]; 6880 u8 src_offset[0x5]; 6881 u8 reserved_at_18[0x3]; 6882 u8 length[0x5]; 6883 6884 u8 reserved_at_20[0x4]; 6885 u8 dst_field[0xc]; 6886 u8 reserved_at_30[0x3]; 6887 u8 dst_offset[0x5]; 6888 u8 reserved_at_38[0x8]; 6889 }; 6890 6891 union mlx5_ifc_set_add_copy_action_in_auto_bits { 6892 struct mlx5_ifc_set_action_in_bits set_action_in; 6893 struct mlx5_ifc_add_action_in_bits add_action_in; 6894 struct mlx5_ifc_copy_action_in_bits copy_action_in; 6895 u8 reserved_at_0[0x40]; 6896 }; 6897 6898 enum { 6899 MLX5_ACTION_TYPE_SET = 0x1, 6900 MLX5_ACTION_TYPE_ADD = 0x2, 6901 MLX5_ACTION_TYPE_COPY = 0x3, 6902 }; 6903 6904 enum { 6905 MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16 = 0x1, 6906 MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0 = 0x2, 6907 MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE = 0x3, 6908 MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16 = 0x4, 6909 MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0 = 0x5, 6910 MLX5_ACTION_IN_FIELD_OUT_IP_DSCP = 0x6, 6911 MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS = 0x7, 6912 MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT = 0x8, 6913 MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT = 0x9, 6914 MLX5_ACTION_IN_FIELD_OUT_IP_TTL = 0xa, 6915 MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT = 0xb, 6916 MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT = 0xc, 6917 MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96 = 0xd, 6918 MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64 = 0xe, 6919 MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32 = 0xf, 6920 MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0 = 0x10, 6921 MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96 = 0x11, 6922 MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64 = 0x12, 6923 MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32 = 0x13, 6924 MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0 = 0x14, 6925 MLX5_ACTION_IN_FIELD_OUT_SIPV4 = 0x15, 6926 MLX5_ACTION_IN_FIELD_OUT_DIPV4 = 0x16, 6927 MLX5_ACTION_IN_FIELD_OUT_FIRST_VID = 0x17, 6928 MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47, 6929 MLX5_ACTION_IN_FIELD_METADATA_REG_A = 0x49, 6930 MLX5_ACTION_IN_FIELD_METADATA_REG_B = 0x50, 6931 MLX5_ACTION_IN_FIELD_METADATA_REG_C_0 = 0x51, 6932 MLX5_ACTION_IN_FIELD_METADATA_REG_C_1 = 0x52, 6933 MLX5_ACTION_IN_FIELD_METADATA_REG_C_2 = 0x53, 6934 MLX5_ACTION_IN_FIELD_METADATA_REG_C_3 = 0x54, 6935 MLX5_ACTION_IN_FIELD_METADATA_REG_C_4 = 0x55, 6936 MLX5_ACTION_IN_FIELD_METADATA_REG_C_5 = 0x56, 6937 MLX5_ACTION_IN_FIELD_METADATA_REG_C_6 = 0x57, 6938 MLX5_ACTION_IN_FIELD_METADATA_REG_C_7 = 0x58, 6939 MLX5_ACTION_IN_FIELD_OUT_TCP_SEQ_NUM = 0x59, 6940 MLX5_ACTION_IN_FIELD_OUT_TCP_ACK_NUM = 0x5B, 6941 MLX5_ACTION_IN_FIELD_IPSEC_SYNDROME = 0x5D, 6942 MLX5_ACTION_IN_FIELD_OUT_EMD_47_32 = 0x6F, 6943 MLX5_ACTION_IN_FIELD_OUT_EMD_31_0 = 0x70, 6944 }; 6945 6946 struct mlx5_ifc_alloc_modify_header_context_out_bits { 6947 u8 status[0x8]; 6948 u8 reserved_at_8[0x18]; 6949 6950 u8 syndrome[0x20]; 6951 6952 u8 modify_header_id[0x20]; 6953 6954 u8 reserved_at_60[0x20]; 6955 }; 6956 6957 struct mlx5_ifc_alloc_modify_header_context_in_bits { 6958 u8 opcode[0x10]; 6959 u8 reserved_at_10[0x10]; 6960 6961 u8 reserved_at_20[0x10]; 6962 u8 op_mod[0x10]; 6963 6964 u8 reserved_at_40[0x20]; 6965 6966 u8 table_type[0x8]; 6967 u8 reserved_at_68[0x10]; 6968 u8 num_of_actions[0x8]; 6969 6970 union mlx5_ifc_set_add_copy_action_in_auto_bits actions[]; 6971 }; 6972 6973 struct mlx5_ifc_dealloc_modify_header_context_out_bits { 6974 u8 status[0x8]; 6975 u8 reserved_at_8[0x18]; 6976 6977 u8 syndrome[0x20]; 6978 6979 u8 reserved_at_40[0x40]; 6980 }; 6981 6982 struct mlx5_ifc_dealloc_modify_header_context_in_bits { 6983 u8 opcode[0x10]; 6984 u8 reserved_at_10[0x10]; 6985 6986 u8 reserved_at_20[0x10]; 6987 u8 op_mod[0x10]; 6988 6989 u8 modify_header_id[0x20]; 6990 6991 u8 reserved_at_60[0x20]; 6992 }; 6993 6994 struct mlx5_ifc_query_modify_header_context_in_bits { 6995 u8 opcode[0x10]; 6996 u8 uid[0x10]; 6997 6998 u8 reserved_at_20[0x10]; 6999 u8 op_mod[0x10]; 7000 7001 u8 modify_header_id[0x20]; 7002 7003 u8 reserved_at_60[0xa0]; 7004 }; 7005 7006 struct mlx5_ifc_query_dct_out_bits { 7007 u8 status[0x8]; 7008 u8 reserved_at_8[0x18]; 7009 7010 u8 syndrome[0x20]; 7011 7012 u8 reserved_at_40[0x40]; 7013 7014 struct mlx5_ifc_dctc_bits dct_context_entry; 7015 7016 u8 reserved_at_280[0x180]; 7017 }; 7018 7019 struct mlx5_ifc_query_dct_in_bits { 7020 u8 opcode[0x10]; 7021 u8 reserved_at_10[0x10]; 7022 7023 u8 reserved_at_20[0x10]; 7024 u8 op_mod[0x10]; 7025 7026 u8 reserved_at_40[0x8]; 7027 u8 dctn[0x18]; 7028 7029 u8 reserved_at_60[0x20]; 7030 }; 7031 7032 struct mlx5_ifc_query_cq_out_bits { 7033 u8 status[0x8]; 7034 u8 reserved_at_8[0x18]; 7035 7036 u8 syndrome[0x20]; 7037 7038 u8 reserved_at_40[0x40]; 7039 7040 struct mlx5_ifc_cqc_bits cq_context; 7041 7042 u8 reserved_at_280[0x600]; 7043 7044 u8 pas[][0x40]; 7045 }; 7046 7047 struct mlx5_ifc_query_cq_in_bits { 7048 u8 opcode[0x10]; 7049 u8 reserved_at_10[0x10]; 7050 7051 u8 reserved_at_20[0x10]; 7052 u8 op_mod[0x10]; 7053 7054 u8 reserved_at_40[0x8]; 7055 u8 cqn[0x18]; 7056 7057 u8 reserved_at_60[0x20]; 7058 }; 7059 7060 struct mlx5_ifc_query_cong_status_out_bits { 7061 u8 status[0x8]; 7062 u8 reserved_at_8[0x18]; 7063 7064 u8 syndrome[0x20]; 7065 7066 u8 reserved_at_40[0x20]; 7067 7068 u8 enable[0x1]; 7069 u8 tag_enable[0x1]; 7070 u8 reserved_at_62[0x1e]; 7071 }; 7072 7073 struct mlx5_ifc_query_cong_status_in_bits { 7074 u8 opcode[0x10]; 7075 u8 reserved_at_10[0x10]; 7076 7077 u8 reserved_at_20[0x10]; 7078 u8 op_mod[0x10]; 7079 7080 u8 reserved_at_40[0x18]; 7081 u8 priority[0x4]; 7082 u8 cong_protocol[0x4]; 7083 7084 u8 reserved_at_60[0x20]; 7085 }; 7086 7087 struct mlx5_ifc_query_cong_statistics_out_bits { 7088 u8 status[0x8]; 7089 u8 reserved_at_8[0x18]; 7090 7091 u8 syndrome[0x20]; 7092 7093 u8 reserved_at_40[0x40]; 7094 7095 u8 rp_cur_flows[0x20]; 7096 7097 u8 sum_flows[0x20]; 7098 7099 u8 rp_cnp_ignored_high[0x20]; 7100 7101 u8 rp_cnp_ignored_low[0x20]; 7102 7103 u8 rp_cnp_handled_high[0x20]; 7104 7105 u8 rp_cnp_handled_low[0x20]; 7106 7107 u8 reserved_at_140[0x100]; 7108 7109 u8 time_stamp_high[0x20]; 7110 7111 u8 time_stamp_low[0x20]; 7112 7113 u8 accumulators_period[0x20]; 7114 7115 u8 np_ecn_marked_roce_packets_high[0x20]; 7116 7117 u8 np_ecn_marked_roce_packets_low[0x20]; 7118 7119 u8 np_cnp_sent_high[0x20]; 7120 7121 u8 np_cnp_sent_low[0x20]; 7122 7123 u8 reserved_at_320[0x560]; 7124 }; 7125 7126 struct mlx5_ifc_query_cong_statistics_in_bits { 7127 u8 opcode[0x10]; 7128 u8 reserved_at_10[0x10]; 7129 7130 u8 reserved_at_20[0x10]; 7131 u8 op_mod[0x10]; 7132 7133 u8 clear[0x1]; 7134 u8 reserved_at_41[0x1f]; 7135 7136 u8 reserved_at_60[0x20]; 7137 }; 7138 7139 struct mlx5_ifc_query_cong_params_out_bits { 7140 u8 status[0x8]; 7141 u8 reserved_at_8[0x18]; 7142 7143 u8 syndrome[0x20]; 7144 7145 u8 reserved_at_40[0x40]; 7146 7147 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 7148 }; 7149 7150 struct mlx5_ifc_query_cong_params_in_bits { 7151 u8 opcode[0x10]; 7152 u8 reserved_at_10[0x10]; 7153 7154 u8 reserved_at_20[0x10]; 7155 u8 op_mod[0x10]; 7156 7157 u8 reserved_at_40[0x1c]; 7158 u8 cong_protocol[0x4]; 7159 7160 u8 reserved_at_60[0x20]; 7161 }; 7162 7163 struct mlx5_ifc_query_adapter_out_bits { 7164 u8 status[0x8]; 7165 u8 reserved_at_8[0x18]; 7166 7167 u8 syndrome[0x20]; 7168 7169 u8 reserved_at_40[0x40]; 7170 7171 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct; 7172 }; 7173 7174 struct mlx5_ifc_query_adapter_in_bits { 7175 u8 opcode[0x10]; 7176 u8 reserved_at_10[0x10]; 7177 7178 u8 reserved_at_20[0x10]; 7179 u8 op_mod[0x10]; 7180 7181 u8 reserved_at_40[0x40]; 7182 }; 7183 7184 struct mlx5_ifc_qp_2rst_out_bits { 7185 u8 status[0x8]; 7186 u8 reserved_at_8[0x18]; 7187 7188 u8 syndrome[0x20]; 7189 7190 u8 reserved_at_40[0x40]; 7191 }; 7192 7193 struct mlx5_ifc_qp_2rst_in_bits { 7194 u8 opcode[0x10]; 7195 u8 uid[0x10]; 7196 7197 u8 reserved_at_20[0x10]; 7198 u8 op_mod[0x10]; 7199 7200 u8 reserved_at_40[0x8]; 7201 u8 qpn[0x18]; 7202 7203 u8 reserved_at_60[0x20]; 7204 }; 7205 7206 struct mlx5_ifc_qp_2err_out_bits { 7207 u8 status[0x8]; 7208 u8 reserved_at_8[0x18]; 7209 7210 u8 syndrome[0x20]; 7211 7212 u8 reserved_at_40[0x40]; 7213 }; 7214 7215 struct mlx5_ifc_qp_2err_in_bits { 7216 u8 opcode[0x10]; 7217 u8 uid[0x10]; 7218 7219 u8 reserved_at_20[0x10]; 7220 u8 op_mod[0x10]; 7221 7222 u8 reserved_at_40[0x8]; 7223 u8 qpn[0x18]; 7224 7225 u8 reserved_at_60[0x20]; 7226 }; 7227 7228 struct mlx5_ifc_page_fault_resume_out_bits { 7229 u8 status[0x8]; 7230 u8 reserved_at_8[0x18]; 7231 7232 u8 syndrome[0x20]; 7233 7234 u8 reserved_at_40[0x40]; 7235 }; 7236 7237 struct mlx5_ifc_page_fault_resume_in_bits { 7238 u8 opcode[0x10]; 7239 u8 reserved_at_10[0x10]; 7240 7241 u8 reserved_at_20[0x10]; 7242 u8 op_mod[0x10]; 7243 7244 u8 error[0x1]; 7245 u8 reserved_at_41[0x4]; 7246 u8 page_fault_type[0x3]; 7247 u8 wq_number[0x18]; 7248 7249 u8 reserved_at_60[0x8]; 7250 u8 token[0x18]; 7251 }; 7252 7253 struct mlx5_ifc_nop_out_bits { 7254 u8 status[0x8]; 7255 u8 reserved_at_8[0x18]; 7256 7257 u8 syndrome[0x20]; 7258 7259 u8 reserved_at_40[0x40]; 7260 }; 7261 7262 struct mlx5_ifc_nop_in_bits { 7263 u8 opcode[0x10]; 7264 u8 reserved_at_10[0x10]; 7265 7266 u8 reserved_at_20[0x10]; 7267 u8 op_mod[0x10]; 7268 7269 u8 reserved_at_40[0x40]; 7270 }; 7271 7272 struct mlx5_ifc_modify_vport_state_out_bits { 7273 u8 status[0x8]; 7274 u8 reserved_at_8[0x18]; 7275 7276 u8 syndrome[0x20]; 7277 7278 u8 reserved_at_40[0x40]; 7279 }; 7280 7281 struct mlx5_ifc_modify_vport_state_in_bits { 7282 u8 opcode[0x10]; 7283 u8 reserved_at_10[0x10]; 7284 7285 u8 reserved_at_20[0x10]; 7286 u8 op_mod[0x10]; 7287 7288 u8 other_vport[0x1]; 7289 u8 reserved_at_41[0xf]; 7290 u8 vport_number[0x10]; 7291 7292 u8 reserved_at_60[0x18]; 7293 u8 admin_state[0x4]; 7294 u8 reserved_at_7c[0x4]; 7295 }; 7296 7297 struct mlx5_ifc_modify_tis_out_bits { 7298 u8 status[0x8]; 7299 u8 reserved_at_8[0x18]; 7300 7301 u8 syndrome[0x20]; 7302 7303 u8 reserved_at_40[0x40]; 7304 }; 7305 7306 struct mlx5_ifc_modify_tis_bitmask_bits { 7307 u8 reserved_at_0[0x20]; 7308 7309 u8 reserved_at_20[0x1d]; 7310 u8 lag_tx_port_affinity[0x1]; 7311 u8 strict_lag_tx_port_affinity[0x1]; 7312 u8 prio[0x1]; 7313 }; 7314 7315 struct mlx5_ifc_modify_tis_in_bits { 7316 u8 opcode[0x10]; 7317 u8 uid[0x10]; 7318 7319 u8 reserved_at_20[0x10]; 7320 u8 op_mod[0x10]; 7321 7322 u8 reserved_at_40[0x8]; 7323 u8 tisn[0x18]; 7324 7325 u8 reserved_at_60[0x20]; 7326 7327 struct mlx5_ifc_modify_tis_bitmask_bits bitmask; 7328 7329 u8 reserved_at_c0[0x40]; 7330 7331 struct mlx5_ifc_tisc_bits ctx; 7332 }; 7333 7334 struct mlx5_ifc_modify_tir_bitmask_bits { 7335 u8 reserved_at_0[0x20]; 7336 7337 u8 reserved_at_20[0x1b]; 7338 u8 self_lb_en[0x1]; 7339 u8 reserved_at_3c[0x1]; 7340 u8 hash[0x1]; 7341 u8 reserved_at_3e[0x1]; 7342 u8 packet_merge[0x1]; 7343 }; 7344 7345 struct mlx5_ifc_modify_tir_out_bits { 7346 u8 status[0x8]; 7347 u8 reserved_at_8[0x18]; 7348 7349 u8 syndrome[0x20]; 7350 7351 u8 reserved_at_40[0x40]; 7352 }; 7353 7354 struct mlx5_ifc_modify_tir_in_bits { 7355 u8 opcode[0x10]; 7356 u8 uid[0x10]; 7357 7358 u8 reserved_at_20[0x10]; 7359 u8 op_mod[0x10]; 7360 7361 u8 reserved_at_40[0x8]; 7362 u8 tirn[0x18]; 7363 7364 u8 reserved_at_60[0x20]; 7365 7366 struct mlx5_ifc_modify_tir_bitmask_bits bitmask; 7367 7368 u8 reserved_at_c0[0x40]; 7369 7370 struct mlx5_ifc_tirc_bits ctx; 7371 }; 7372 7373 struct mlx5_ifc_modify_sq_out_bits { 7374 u8 status[0x8]; 7375 u8 reserved_at_8[0x18]; 7376 7377 u8 syndrome[0x20]; 7378 7379 u8 reserved_at_40[0x40]; 7380 }; 7381 7382 struct mlx5_ifc_modify_sq_in_bits { 7383 u8 opcode[0x10]; 7384 u8 uid[0x10]; 7385 7386 u8 reserved_at_20[0x10]; 7387 u8 op_mod[0x10]; 7388 7389 u8 sq_state[0x4]; 7390 u8 reserved_at_44[0x4]; 7391 u8 sqn[0x18]; 7392 7393 u8 reserved_at_60[0x20]; 7394 7395 u8 modify_bitmask[0x40]; 7396 7397 u8 reserved_at_c0[0x40]; 7398 7399 struct mlx5_ifc_sqc_bits ctx; 7400 }; 7401 7402 struct mlx5_ifc_modify_scheduling_element_out_bits { 7403 u8 status[0x8]; 7404 u8 reserved_at_8[0x18]; 7405 7406 u8 syndrome[0x20]; 7407 7408 u8 reserved_at_40[0x1c0]; 7409 }; 7410 7411 enum { 7412 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1, 7413 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2, 7414 }; 7415 7416 struct mlx5_ifc_modify_scheduling_element_in_bits { 7417 u8 opcode[0x10]; 7418 u8 reserved_at_10[0x10]; 7419 7420 u8 reserved_at_20[0x10]; 7421 u8 op_mod[0x10]; 7422 7423 u8 scheduling_hierarchy[0x8]; 7424 u8 reserved_at_48[0x18]; 7425 7426 u8 scheduling_element_id[0x20]; 7427 7428 u8 reserved_at_80[0x20]; 7429 7430 u8 modify_bitmask[0x20]; 7431 7432 u8 reserved_at_c0[0x40]; 7433 7434 struct mlx5_ifc_scheduling_context_bits scheduling_context; 7435 7436 u8 reserved_at_300[0x100]; 7437 }; 7438 7439 struct mlx5_ifc_modify_rqt_out_bits { 7440 u8 status[0x8]; 7441 u8 reserved_at_8[0x18]; 7442 7443 u8 syndrome[0x20]; 7444 7445 u8 reserved_at_40[0x40]; 7446 }; 7447 7448 struct mlx5_ifc_rqt_bitmask_bits { 7449 u8 reserved_at_0[0x20]; 7450 7451 u8 reserved_at_20[0x1f]; 7452 u8 rqn_list[0x1]; 7453 }; 7454 7455 struct mlx5_ifc_modify_rqt_in_bits { 7456 u8 opcode[0x10]; 7457 u8 uid[0x10]; 7458 7459 u8 reserved_at_20[0x10]; 7460 u8 op_mod[0x10]; 7461 7462 u8 reserved_at_40[0x8]; 7463 u8 rqtn[0x18]; 7464 7465 u8 reserved_at_60[0x20]; 7466 7467 struct mlx5_ifc_rqt_bitmask_bits bitmask; 7468 7469 u8 reserved_at_c0[0x40]; 7470 7471 struct mlx5_ifc_rqtc_bits ctx; 7472 }; 7473 7474 struct mlx5_ifc_modify_rq_out_bits { 7475 u8 status[0x8]; 7476 u8 reserved_at_8[0x18]; 7477 7478 u8 syndrome[0x20]; 7479 7480 u8 reserved_at_40[0x40]; 7481 }; 7482 7483 enum { 7484 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1, 7485 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2, 7486 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3, 7487 }; 7488 7489 struct mlx5_ifc_modify_rq_in_bits { 7490 u8 opcode[0x10]; 7491 u8 uid[0x10]; 7492 7493 u8 reserved_at_20[0x10]; 7494 u8 op_mod[0x10]; 7495 7496 u8 rq_state[0x4]; 7497 u8 reserved_at_44[0x4]; 7498 u8 rqn[0x18]; 7499 7500 u8 reserved_at_60[0x20]; 7501 7502 u8 modify_bitmask[0x40]; 7503 7504 u8 reserved_at_c0[0x40]; 7505 7506 struct mlx5_ifc_rqc_bits ctx; 7507 }; 7508 7509 struct mlx5_ifc_modify_rmp_out_bits { 7510 u8 status[0x8]; 7511 u8 reserved_at_8[0x18]; 7512 7513 u8 syndrome[0x20]; 7514 7515 u8 reserved_at_40[0x40]; 7516 }; 7517 7518 struct mlx5_ifc_rmp_bitmask_bits { 7519 u8 reserved_at_0[0x20]; 7520 7521 u8 reserved_at_20[0x1f]; 7522 u8 lwm[0x1]; 7523 }; 7524 7525 struct mlx5_ifc_modify_rmp_in_bits { 7526 u8 opcode[0x10]; 7527 u8 uid[0x10]; 7528 7529 u8 reserved_at_20[0x10]; 7530 u8 op_mod[0x10]; 7531 7532 u8 rmp_state[0x4]; 7533 u8 reserved_at_44[0x4]; 7534 u8 rmpn[0x18]; 7535 7536 u8 reserved_at_60[0x20]; 7537 7538 struct mlx5_ifc_rmp_bitmask_bits bitmask; 7539 7540 u8 reserved_at_c0[0x40]; 7541 7542 struct mlx5_ifc_rmpc_bits ctx; 7543 }; 7544 7545 struct mlx5_ifc_modify_nic_vport_context_out_bits { 7546 u8 status[0x8]; 7547 u8 reserved_at_8[0x18]; 7548 7549 u8 syndrome[0x20]; 7550 7551 u8 reserved_at_40[0x40]; 7552 }; 7553 7554 struct mlx5_ifc_modify_nic_vport_field_select_bits { 7555 u8 reserved_at_0[0x12]; 7556 u8 affiliation[0x1]; 7557 u8 reserved_at_13[0x1]; 7558 u8 disable_uc_local_lb[0x1]; 7559 u8 disable_mc_local_lb[0x1]; 7560 u8 node_guid[0x1]; 7561 u8 port_guid[0x1]; 7562 u8 min_inline[0x1]; 7563 u8 mtu[0x1]; 7564 u8 change_event[0x1]; 7565 u8 promisc[0x1]; 7566 u8 permanent_address[0x1]; 7567 u8 addresses_list[0x1]; 7568 u8 roce_en[0x1]; 7569 u8 reserved_at_1f[0x1]; 7570 }; 7571 7572 struct mlx5_ifc_modify_nic_vport_context_in_bits { 7573 u8 opcode[0x10]; 7574 u8 reserved_at_10[0x10]; 7575 7576 u8 reserved_at_20[0x10]; 7577 u8 op_mod[0x10]; 7578 7579 u8 other_vport[0x1]; 7580 u8 reserved_at_41[0xf]; 7581 u8 vport_number[0x10]; 7582 7583 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select; 7584 7585 u8 reserved_at_80[0x780]; 7586 7587 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 7588 }; 7589 7590 struct mlx5_ifc_modify_hca_vport_context_out_bits { 7591 u8 status[0x8]; 7592 u8 reserved_at_8[0x18]; 7593 7594 u8 syndrome[0x20]; 7595 7596 u8 reserved_at_40[0x40]; 7597 }; 7598 7599 struct mlx5_ifc_modify_hca_vport_context_in_bits { 7600 u8 opcode[0x10]; 7601 u8 reserved_at_10[0x10]; 7602 7603 u8 reserved_at_20[0x10]; 7604 u8 op_mod[0x10]; 7605 7606 u8 other_vport[0x1]; 7607 u8 reserved_at_41[0xb]; 7608 u8 port_num[0x4]; 7609 u8 vport_number[0x10]; 7610 7611 u8 reserved_at_60[0x20]; 7612 7613 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 7614 }; 7615 7616 struct mlx5_ifc_modify_cq_out_bits { 7617 u8 status[0x8]; 7618 u8 reserved_at_8[0x18]; 7619 7620 u8 syndrome[0x20]; 7621 7622 u8 reserved_at_40[0x40]; 7623 }; 7624 7625 enum { 7626 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0, 7627 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1, 7628 }; 7629 7630 struct mlx5_ifc_modify_cq_in_bits { 7631 u8 opcode[0x10]; 7632 u8 uid[0x10]; 7633 7634 u8 reserved_at_20[0x10]; 7635 u8 op_mod[0x10]; 7636 7637 u8 reserved_at_40[0x8]; 7638 u8 cqn[0x18]; 7639 7640 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select; 7641 7642 struct mlx5_ifc_cqc_bits cq_context; 7643 7644 u8 reserved_at_280[0x60]; 7645 7646 u8 cq_umem_valid[0x1]; 7647 u8 reserved_at_2e1[0x1f]; 7648 7649 u8 reserved_at_300[0x580]; 7650 7651 u8 pas[][0x40]; 7652 }; 7653 7654 struct mlx5_ifc_modify_cong_status_out_bits { 7655 u8 status[0x8]; 7656 u8 reserved_at_8[0x18]; 7657 7658 u8 syndrome[0x20]; 7659 7660 u8 reserved_at_40[0x40]; 7661 }; 7662 7663 struct mlx5_ifc_modify_cong_status_in_bits { 7664 u8 opcode[0x10]; 7665 u8 reserved_at_10[0x10]; 7666 7667 u8 reserved_at_20[0x10]; 7668 u8 op_mod[0x10]; 7669 7670 u8 reserved_at_40[0x18]; 7671 u8 priority[0x4]; 7672 u8 cong_protocol[0x4]; 7673 7674 u8 enable[0x1]; 7675 u8 tag_enable[0x1]; 7676 u8 reserved_at_62[0x1e]; 7677 }; 7678 7679 struct mlx5_ifc_modify_cong_params_out_bits { 7680 u8 status[0x8]; 7681 u8 reserved_at_8[0x18]; 7682 7683 u8 syndrome[0x20]; 7684 7685 u8 reserved_at_40[0x40]; 7686 }; 7687 7688 struct mlx5_ifc_modify_cong_params_in_bits { 7689 u8 opcode[0x10]; 7690 u8 reserved_at_10[0x10]; 7691 7692 u8 reserved_at_20[0x10]; 7693 u8 op_mod[0x10]; 7694 7695 u8 reserved_at_40[0x1c]; 7696 u8 cong_protocol[0x4]; 7697 7698 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select; 7699 7700 u8 reserved_at_80[0x80]; 7701 7702 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 7703 }; 7704 7705 struct mlx5_ifc_manage_pages_out_bits { 7706 u8 status[0x8]; 7707 u8 reserved_at_8[0x18]; 7708 7709 u8 syndrome[0x20]; 7710 7711 u8 output_num_entries[0x20]; 7712 7713 u8 reserved_at_60[0x20]; 7714 7715 u8 pas[][0x40]; 7716 }; 7717 7718 enum { 7719 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL = 0x0, 7720 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS = 0x1, 7721 MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES = 0x2, 7722 }; 7723 7724 struct mlx5_ifc_manage_pages_in_bits { 7725 u8 opcode[0x10]; 7726 u8 reserved_at_10[0x10]; 7727 7728 u8 reserved_at_20[0x10]; 7729 u8 op_mod[0x10]; 7730 7731 u8 embedded_cpu_function[0x1]; 7732 u8 reserved_at_41[0xf]; 7733 u8 function_id[0x10]; 7734 7735 u8 input_num_entries[0x20]; 7736 7737 u8 pas[][0x40]; 7738 }; 7739 7740 struct mlx5_ifc_mad_ifc_out_bits { 7741 u8 status[0x8]; 7742 u8 reserved_at_8[0x18]; 7743 7744 u8 syndrome[0x20]; 7745 7746 u8 reserved_at_40[0x40]; 7747 7748 u8 response_mad_packet[256][0x8]; 7749 }; 7750 7751 struct mlx5_ifc_mad_ifc_in_bits { 7752 u8 opcode[0x10]; 7753 u8 reserved_at_10[0x10]; 7754 7755 u8 reserved_at_20[0x10]; 7756 u8 op_mod[0x10]; 7757 7758 u8 remote_lid[0x10]; 7759 u8 plane_index[0x8]; 7760 u8 port[0x8]; 7761 7762 u8 reserved_at_60[0x20]; 7763 7764 u8 mad[256][0x8]; 7765 }; 7766 7767 struct mlx5_ifc_init_hca_out_bits { 7768 u8 status[0x8]; 7769 u8 reserved_at_8[0x18]; 7770 7771 u8 syndrome[0x20]; 7772 7773 u8 reserved_at_40[0x40]; 7774 }; 7775 7776 struct mlx5_ifc_init_hca_in_bits { 7777 u8 opcode[0x10]; 7778 u8 reserved_at_10[0x10]; 7779 7780 u8 reserved_at_20[0x10]; 7781 u8 op_mod[0x10]; 7782 7783 u8 reserved_at_40[0x20]; 7784 7785 u8 reserved_at_60[0x2]; 7786 u8 sw_vhca_id[0xe]; 7787 u8 reserved_at_70[0x10]; 7788 7789 u8 sw_owner_id[4][0x20]; 7790 }; 7791 7792 struct mlx5_ifc_init2rtr_qp_out_bits { 7793 u8 status[0x8]; 7794 u8 reserved_at_8[0x18]; 7795 7796 u8 syndrome[0x20]; 7797 7798 u8 reserved_at_40[0x20]; 7799 u8 ece[0x20]; 7800 }; 7801 7802 struct mlx5_ifc_init2rtr_qp_in_bits { 7803 u8 opcode[0x10]; 7804 u8 uid[0x10]; 7805 7806 u8 reserved_at_20[0x10]; 7807 u8 op_mod[0x10]; 7808 7809 u8 reserved_at_40[0x8]; 7810 u8 qpn[0x18]; 7811 7812 u8 reserved_at_60[0x20]; 7813 7814 u8 opt_param_mask[0x20]; 7815 7816 u8 ece[0x20]; 7817 7818 struct mlx5_ifc_qpc_bits qpc; 7819 7820 u8 reserved_at_800[0x80]; 7821 }; 7822 7823 struct mlx5_ifc_init2init_qp_out_bits { 7824 u8 status[0x8]; 7825 u8 reserved_at_8[0x18]; 7826 7827 u8 syndrome[0x20]; 7828 7829 u8 reserved_at_40[0x20]; 7830 u8 ece[0x20]; 7831 }; 7832 7833 struct mlx5_ifc_init2init_qp_in_bits { 7834 u8 opcode[0x10]; 7835 u8 uid[0x10]; 7836 7837 u8 reserved_at_20[0x10]; 7838 u8 op_mod[0x10]; 7839 7840 u8 reserved_at_40[0x8]; 7841 u8 qpn[0x18]; 7842 7843 u8 reserved_at_60[0x20]; 7844 7845 u8 opt_param_mask[0x20]; 7846 7847 u8 ece[0x20]; 7848 7849 struct mlx5_ifc_qpc_bits qpc; 7850 7851 u8 reserved_at_800[0x80]; 7852 }; 7853 7854 struct mlx5_ifc_get_dropped_packet_log_out_bits { 7855 u8 status[0x8]; 7856 u8 reserved_at_8[0x18]; 7857 7858 u8 syndrome[0x20]; 7859 7860 u8 reserved_at_40[0x40]; 7861 7862 u8 packet_headers_log[128][0x8]; 7863 7864 u8 packet_syndrome[64][0x8]; 7865 }; 7866 7867 struct mlx5_ifc_get_dropped_packet_log_in_bits { 7868 u8 opcode[0x10]; 7869 u8 reserved_at_10[0x10]; 7870 7871 u8 reserved_at_20[0x10]; 7872 u8 op_mod[0x10]; 7873 7874 u8 reserved_at_40[0x40]; 7875 }; 7876 7877 struct mlx5_ifc_gen_eqe_in_bits { 7878 u8 opcode[0x10]; 7879 u8 reserved_at_10[0x10]; 7880 7881 u8 reserved_at_20[0x10]; 7882 u8 op_mod[0x10]; 7883 7884 u8 reserved_at_40[0x18]; 7885 u8 eq_number[0x8]; 7886 7887 u8 reserved_at_60[0x20]; 7888 7889 u8 eqe[64][0x8]; 7890 }; 7891 7892 struct mlx5_ifc_gen_eq_out_bits { 7893 u8 status[0x8]; 7894 u8 reserved_at_8[0x18]; 7895 7896 u8 syndrome[0x20]; 7897 7898 u8 reserved_at_40[0x40]; 7899 }; 7900 7901 struct mlx5_ifc_enable_hca_out_bits { 7902 u8 status[0x8]; 7903 u8 reserved_at_8[0x18]; 7904 7905 u8 syndrome[0x20]; 7906 7907 u8 reserved_at_40[0x20]; 7908 }; 7909 7910 struct mlx5_ifc_enable_hca_in_bits { 7911 u8 opcode[0x10]; 7912 u8 reserved_at_10[0x10]; 7913 7914 u8 reserved_at_20[0x10]; 7915 u8 op_mod[0x10]; 7916 7917 u8 embedded_cpu_function[0x1]; 7918 u8 reserved_at_41[0xf]; 7919 u8 function_id[0x10]; 7920 7921 u8 reserved_at_60[0x20]; 7922 }; 7923 7924 struct mlx5_ifc_drain_dct_out_bits { 7925 u8 status[0x8]; 7926 u8 reserved_at_8[0x18]; 7927 7928 u8 syndrome[0x20]; 7929 7930 u8 reserved_at_40[0x40]; 7931 }; 7932 7933 struct mlx5_ifc_drain_dct_in_bits { 7934 u8 opcode[0x10]; 7935 u8 uid[0x10]; 7936 7937 u8 reserved_at_20[0x10]; 7938 u8 op_mod[0x10]; 7939 7940 u8 reserved_at_40[0x8]; 7941 u8 dctn[0x18]; 7942 7943 u8 reserved_at_60[0x20]; 7944 }; 7945 7946 struct mlx5_ifc_disable_hca_out_bits { 7947 u8 status[0x8]; 7948 u8 reserved_at_8[0x18]; 7949 7950 u8 syndrome[0x20]; 7951 7952 u8 reserved_at_40[0x20]; 7953 }; 7954 7955 struct mlx5_ifc_disable_hca_in_bits { 7956 u8 opcode[0x10]; 7957 u8 reserved_at_10[0x10]; 7958 7959 u8 reserved_at_20[0x10]; 7960 u8 op_mod[0x10]; 7961 7962 u8 embedded_cpu_function[0x1]; 7963 u8 reserved_at_41[0xf]; 7964 u8 function_id[0x10]; 7965 7966 u8 reserved_at_60[0x20]; 7967 }; 7968 7969 struct mlx5_ifc_detach_from_mcg_out_bits { 7970 u8 status[0x8]; 7971 u8 reserved_at_8[0x18]; 7972 7973 u8 syndrome[0x20]; 7974 7975 u8 reserved_at_40[0x40]; 7976 }; 7977 7978 struct mlx5_ifc_detach_from_mcg_in_bits { 7979 u8 opcode[0x10]; 7980 u8 uid[0x10]; 7981 7982 u8 reserved_at_20[0x10]; 7983 u8 op_mod[0x10]; 7984 7985 u8 reserved_at_40[0x8]; 7986 u8 qpn[0x18]; 7987 7988 u8 reserved_at_60[0x20]; 7989 7990 u8 multicast_gid[16][0x8]; 7991 }; 7992 7993 struct mlx5_ifc_destroy_xrq_out_bits { 7994 u8 status[0x8]; 7995 u8 reserved_at_8[0x18]; 7996 7997 u8 syndrome[0x20]; 7998 7999 u8 reserved_at_40[0x40]; 8000 }; 8001 8002 struct mlx5_ifc_destroy_xrq_in_bits { 8003 u8 opcode[0x10]; 8004 u8 uid[0x10]; 8005 8006 u8 reserved_at_20[0x10]; 8007 u8 op_mod[0x10]; 8008 8009 u8 reserved_at_40[0x8]; 8010 u8 xrqn[0x18]; 8011 8012 u8 reserved_at_60[0x20]; 8013 }; 8014 8015 struct mlx5_ifc_destroy_xrc_srq_out_bits { 8016 u8 status[0x8]; 8017 u8 reserved_at_8[0x18]; 8018 8019 u8 syndrome[0x20]; 8020 8021 u8 reserved_at_40[0x40]; 8022 }; 8023 8024 struct mlx5_ifc_destroy_xrc_srq_in_bits { 8025 u8 opcode[0x10]; 8026 u8 uid[0x10]; 8027 8028 u8 reserved_at_20[0x10]; 8029 u8 op_mod[0x10]; 8030 8031 u8 reserved_at_40[0x8]; 8032 u8 xrc_srqn[0x18]; 8033 8034 u8 reserved_at_60[0x20]; 8035 }; 8036 8037 struct mlx5_ifc_destroy_tis_out_bits { 8038 u8 status[0x8]; 8039 u8 reserved_at_8[0x18]; 8040 8041 u8 syndrome[0x20]; 8042 8043 u8 reserved_at_40[0x40]; 8044 }; 8045 8046 struct mlx5_ifc_destroy_tis_in_bits { 8047 u8 opcode[0x10]; 8048 u8 uid[0x10]; 8049 8050 u8 reserved_at_20[0x10]; 8051 u8 op_mod[0x10]; 8052 8053 u8 reserved_at_40[0x8]; 8054 u8 tisn[0x18]; 8055 8056 u8 reserved_at_60[0x20]; 8057 }; 8058 8059 struct mlx5_ifc_destroy_tir_out_bits { 8060 u8 status[0x8]; 8061 u8 reserved_at_8[0x18]; 8062 8063 u8 syndrome[0x20]; 8064 8065 u8 reserved_at_40[0x40]; 8066 }; 8067 8068 struct mlx5_ifc_destroy_tir_in_bits { 8069 u8 opcode[0x10]; 8070 u8 uid[0x10]; 8071 8072 u8 reserved_at_20[0x10]; 8073 u8 op_mod[0x10]; 8074 8075 u8 reserved_at_40[0x8]; 8076 u8 tirn[0x18]; 8077 8078 u8 reserved_at_60[0x20]; 8079 }; 8080 8081 struct mlx5_ifc_destroy_srq_out_bits { 8082 u8 status[0x8]; 8083 u8 reserved_at_8[0x18]; 8084 8085 u8 syndrome[0x20]; 8086 8087 u8 reserved_at_40[0x40]; 8088 }; 8089 8090 struct mlx5_ifc_destroy_srq_in_bits { 8091 u8 opcode[0x10]; 8092 u8 uid[0x10]; 8093 8094 u8 reserved_at_20[0x10]; 8095 u8 op_mod[0x10]; 8096 8097 u8 reserved_at_40[0x8]; 8098 u8 srqn[0x18]; 8099 8100 u8 reserved_at_60[0x20]; 8101 }; 8102 8103 struct mlx5_ifc_destroy_sq_out_bits { 8104 u8 status[0x8]; 8105 u8 reserved_at_8[0x18]; 8106 8107 u8 syndrome[0x20]; 8108 8109 u8 reserved_at_40[0x40]; 8110 }; 8111 8112 struct mlx5_ifc_destroy_sq_in_bits { 8113 u8 opcode[0x10]; 8114 u8 uid[0x10]; 8115 8116 u8 reserved_at_20[0x10]; 8117 u8 op_mod[0x10]; 8118 8119 u8 reserved_at_40[0x8]; 8120 u8 sqn[0x18]; 8121 8122 u8 reserved_at_60[0x20]; 8123 }; 8124 8125 struct mlx5_ifc_destroy_scheduling_element_out_bits { 8126 u8 status[0x8]; 8127 u8 reserved_at_8[0x18]; 8128 8129 u8 syndrome[0x20]; 8130 8131 u8 reserved_at_40[0x1c0]; 8132 }; 8133 8134 struct mlx5_ifc_destroy_scheduling_element_in_bits { 8135 u8 opcode[0x10]; 8136 u8 reserved_at_10[0x10]; 8137 8138 u8 reserved_at_20[0x10]; 8139 u8 op_mod[0x10]; 8140 8141 u8 scheduling_hierarchy[0x8]; 8142 u8 reserved_at_48[0x18]; 8143 8144 u8 scheduling_element_id[0x20]; 8145 8146 u8 reserved_at_80[0x180]; 8147 }; 8148 8149 struct mlx5_ifc_destroy_rqt_out_bits { 8150 u8 status[0x8]; 8151 u8 reserved_at_8[0x18]; 8152 8153 u8 syndrome[0x20]; 8154 8155 u8 reserved_at_40[0x40]; 8156 }; 8157 8158 struct mlx5_ifc_destroy_rqt_in_bits { 8159 u8 opcode[0x10]; 8160 u8 uid[0x10]; 8161 8162 u8 reserved_at_20[0x10]; 8163 u8 op_mod[0x10]; 8164 8165 u8 reserved_at_40[0x8]; 8166 u8 rqtn[0x18]; 8167 8168 u8 reserved_at_60[0x20]; 8169 }; 8170 8171 struct mlx5_ifc_destroy_rq_out_bits { 8172 u8 status[0x8]; 8173 u8 reserved_at_8[0x18]; 8174 8175 u8 syndrome[0x20]; 8176 8177 u8 reserved_at_40[0x40]; 8178 }; 8179 8180 struct mlx5_ifc_destroy_rq_in_bits { 8181 u8 opcode[0x10]; 8182 u8 uid[0x10]; 8183 8184 u8 reserved_at_20[0x10]; 8185 u8 op_mod[0x10]; 8186 8187 u8 reserved_at_40[0x8]; 8188 u8 rqn[0x18]; 8189 8190 u8 reserved_at_60[0x20]; 8191 }; 8192 8193 struct mlx5_ifc_set_delay_drop_params_in_bits { 8194 u8 opcode[0x10]; 8195 u8 reserved_at_10[0x10]; 8196 8197 u8 reserved_at_20[0x10]; 8198 u8 op_mod[0x10]; 8199 8200 u8 reserved_at_40[0x20]; 8201 8202 u8 reserved_at_60[0x10]; 8203 u8 delay_drop_timeout[0x10]; 8204 }; 8205 8206 struct mlx5_ifc_set_delay_drop_params_out_bits { 8207 u8 status[0x8]; 8208 u8 reserved_at_8[0x18]; 8209 8210 u8 syndrome[0x20]; 8211 8212 u8 reserved_at_40[0x40]; 8213 }; 8214 8215 struct mlx5_ifc_destroy_rmp_out_bits { 8216 u8 status[0x8]; 8217 u8 reserved_at_8[0x18]; 8218 8219 u8 syndrome[0x20]; 8220 8221 u8 reserved_at_40[0x40]; 8222 }; 8223 8224 struct mlx5_ifc_destroy_rmp_in_bits { 8225 u8 opcode[0x10]; 8226 u8 uid[0x10]; 8227 8228 u8 reserved_at_20[0x10]; 8229 u8 op_mod[0x10]; 8230 8231 u8 reserved_at_40[0x8]; 8232 u8 rmpn[0x18]; 8233 8234 u8 reserved_at_60[0x20]; 8235 }; 8236 8237 struct mlx5_ifc_destroy_qp_out_bits { 8238 u8 status[0x8]; 8239 u8 reserved_at_8[0x18]; 8240 8241 u8 syndrome[0x20]; 8242 8243 u8 reserved_at_40[0x40]; 8244 }; 8245 8246 struct mlx5_ifc_destroy_qp_in_bits { 8247 u8 opcode[0x10]; 8248 u8 uid[0x10]; 8249 8250 u8 reserved_at_20[0x10]; 8251 u8 op_mod[0x10]; 8252 8253 u8 reserved_at_40[0x8]; 8254 u8 qpn[0x18]; 8255 8256 u8 reserved_at_60[0x20]; 8257 }; 8258 8259 struct mlx5_ifc_destroy_psv_out_bits { 8260 u8 status[0x8]; 8261 u8 reserved_at_8[0x18]; 8262 8263 u8 syndrome[0x20]; 8264 8265 u8 reserved_at_40[0x40]; 8266 }; 8267 8268 struct mlx5_ifc_destroy_psv_in_bits { 8269 u8 opcode[0x10]; 8270 u8 reserved_at_10[0x10]; 8271 8272 u8 reserved_at_20[0x10]; 8273 u8 op_mod[0x10]; 8274 8275 u8 reserved_at_40[0x8]; 8276 u8 psvn[0x18]; 8277 8278 u8 reserved_at_60[0x20]; 8279 }; 8280 8281 struct mlx5_ifc_destroy_mkey_out_bits { 8282 u8 status[0x8]; 8283 u8 reserved_at_8[0x18]; 8284 8285 u8 syndrome[0x20]; 8286 8287 u8 reserved_at_40[0x40]; 8288 }; 8289 8290 struct mlx5_ifc_destroy_mkey_in_bits { 8291 u8 opcode[0x10]; 8292 u8 uid[0x10]; 8293 8294 u8 reserved_at_20[0x10]; 8295 u8 op_mod[0x10]; 8296 8297 u8 reserved_at_40[0x8]; 8298 u8 mkey_index[0x18]; 8299 8300 u8 reserved_at_60[0x20]; 8301 }; 8302 8303 struct mlx5_ifc_destroy_flow_table_out_bits { 8304 u8 status[0x8]; 8305 u8 reserved_at_8[0x18]; 8306 8307 u8 syndrome[0x20]; 8308 8309 u8 reserved_at_40[0x40]; 8310 }; 8311 8312 struct mlx5_ifc_destroy_flow_table_in_bits { 8313 u8 opcode[0x10]; 8314 u8 reserved_at_10[0x10]; 8315 8316 u8 reserved_at_20[0x10]; 8317 u8 op_mod[0x10]; 8318 8319 u8 other_vport[0x1]; 8320 u8 reserved_at_41[0xf]; 8321 u8 vport_number[0x10]; 8322 8323 u8 reserved_at_60[0x20]; 8324 8325 u8 table_type[0x8]; 8326 u8 reserved_at_88[0x18]; 8327 8328 u8 reserved_at_a0[0x8]; 8329 u8 table_id[0x18]; 8330 8331 u8 reserved_at_c0[0x140]; 8332 }; 8333 8334 struct mlx5_ifc_destroy_flow_group_out_bits { 8335 u8 status[0x8]; 8336 u8 reserved_at_8[0x18]; 8337 8338 u8 syndrome[0x20]; 8339 8340 u8 reserved_at_40[0x40]; 8341 }; 8342 8343 struct mlx5_ifc_destroy_flow_group_in_bits { 8344 u8 opcode[0x10]; 8345 u8 reserved_at_10[0x10]; 8346 8347 u8 reserved_at_20[0x10]; 8348 u8 op_mod[0x10]; 8349 8350 u8 other_vport[0x1]; 8351 u8 reserved_at_41[0xf]; 8352 u8 vport_number[0x10]; 8353 8354 u8 reserved_at_60[0x20]; 8355 8356 u8 table_type[0x8]; 8357 u8 reserved_at_88[0x18]; 8358 8359 u8 reserved_at_a0[0x8]; 8360 u8 table_id[0x18]; 8361 8362 u8 group_id[0x20]; 8363 8364 u8 reserved_at_e0[0x120]; 8365 }; 8366 8367 struct mlx5_ifc_destroy_eq_out_bits { 8368 u8 status[0x8]; 8369 u8 reserved_at_8[0x18]; 8370 8371 u8 syndrome[0x20]; 8372 8373 u8 reserved_at_40[0x40]; 8374 }; 8375 8376 struct mlx5_ifc_destroy_eq_in_bits { 8377 u8 opcode[0x10]; 8378 u8 reserved_at_10[0x10]; 8379 8380 u8 reserved_at_20[0x10]; 8381 u8 op_mod[0x10]; 8382 8383 u8 reserved_at_40[0x18]; 8384 u8 eq_number[0x8]; 8385 8386 u8 reserved_at_60[0x20]; 8387 }; 8388 8389 struct mlx5_ifc_destroy_dct_out_bits { 8390 u8 status[0x8]; 8391 u8 reserved_at_8[0x18]; 8392 8393 u8 syndrome[0x20]; 8394 8395 u8 reserved_at_40[0x40]; 8396 }; 8397 8398 struct mlx5_ifc_destroy_dct_in_bits { 8399 u8 opcode[0x10]; 8400 u8 uid[0x10]; 8401 8402 u8 reserved_at_20[0x10]; 8403 u8 op_mod[0x10]; 8404 8405 u8 reserved_at_40[0x8]; 8406 u8 dctn[0x18]; 8407 8408 u8 reserved_at_60[0x20]; 8409 }; 8410 8411 struct mlx5_ifc_destroy_cq_out_bits { 8412 u8 status[0x8]; 8413 u8 reserved_at_8[0x18]; 8414 8415 u8 syndrome[0x20]; 8416 8417 u8 reserved_at_40[0x40]; 8418 }; 8419 8420 struct mlx5_ifc_destroy_cq_in_bits { 8421 u8 opcode[0x10]; 8422 u8 uid[0x10]; 8423 8424 u8 reserved_at_20[0x10]; 8425 u8 op_mod[0x10]; 8426 8427 u8 reserved_at_40[0x8]; 8428 u8 cqn[0x18]; 8429 8430 u8 reserved_at_60[0x20]; 8431 }; 8432 8433 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits { 8434 u8 status[0x8]; 8435 u8 reserved_at_8[0x18]; 8436 8437 u8 syndrome[0x20]; 8438 8439 u8 reserved_at_40[0x40]; 8440 }; 8441 8442 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits { 8443 u8 opcode[0x10]; 8444 u8 reserved_at_10[0x10]; 8445 8446 u8 reserved_at_20[0x10]; 8447 u8 op_mod[0x10]; 8448 8449 u8 reserved_at_40[0x20]; 8450 8451 u8 reserved_at_60[0x10]; 8452 u8 vxlan_udp_port[0x10]; 8453 }; 8454 8455 struct mlx5_ifc_delete_l2_table_entry_out_bits { 8456 u8 status[0x8]; 8457 u8 reserved_at_8[0x18]; 8458 8459 u8 syndrome[0x20]; 8460 8461 u8 reserved_at_40[0x40]; 8462 }; 8463 8464 struct mlx5_ifc_delete_l2_table_entry_in_bits { 8465 u8 opcode[0x10]; 8466 u8 reserved_at_10[0x10]; 8467 8468 u8 reserved_at_20[0x10]; 8469 u8 op_mod[0x10]; 8470 8471 u8 reserved_at_40[0x60]; 8472 8473 u8 reserved_at_a0[0x8]; 8474 u8 table_index[0x18]; 8475 8476 u8 reserved_at_c0[0x140]; 8477 }; 8478 8479 struct mlx5_ifc_delete_fte_out_bits { 8480 u8 status[0x8]; 8481 u8 reserved_at_8[0x18]; 8482 8483 u8 syndrome[0x20]; 8484 8485 u8 reserved_at_40[0x40]; 8486 }; 8487 8488 struct mlx5_ifc_delete_fte_in_bits { 8489 u8 opcode[0x10]; 8490 u8 reserved_at_10[0x10]; 8491 8492 u8 reserved_at_20[0x10]; 8493 u8 op_mod[0x10]; 8494 8495 u8 other_vport[0x1]; 8496 u8 reserved_at_41[0xf]; 8497 u8 vport_number[0x10]; 8498 8499 u8 reserved_at_60[0x20]; 8500 8501 u8 table_type[0x8]; 8502 u8 reserved_at_88[0x18]; 8503 8504 u8 reserved_at_a0[0x8]; 8505 u8 table_id[0x18]; 8506 8507 u8 reserved_at_c0[0x40]; 8508 8509 u8 flow_index[0x20]; 8510 8511 u8 reserved_at_120[0xe0]; 8512 }; 8513 8514 struct mlx5_ifc_dealloc_xrcd_out_bits { 8515 u8 status[0x8]; 8516 u8 reserved_at_8[0x18]; 8517 8518 u8 syndrome[0x20]; 8519 8520 u8 reserved_at_40[0x40]; 8521 }; 8522 8523 struct mlx5_ifc_dealloc_xrcd_in_bits { 8524 u8 opcode[0x10]; 8525 u8 uid[0x10]; 8526 8527 u8 reserved_at_20[0x10]; 8528 u8 op_mod[0x10]; 8529 8530 u8 reserved_at_40[0x8]; 8531 u8 xrcd[0x18]; 8532 8533 u8 reserved_at_60[0x20]; 8534 }; 8535 8536 struct mlx5_ifc_dealloc_uar_out_bits { 8537 u8 status[0x8]; 8538 u8 reserved_at_8[0x18]; 8539 8540 u8 syndrome[0x20]; 8541 8542 u8 reserved_at_40[0x40]; 8543 }; 8544 8545 struct mlx5_ifc_dealloc_uar_in_bits { 8546 u8 opcode[0x10]; 8547 u8 uid[0x10]; 8548 8549 u8 reserved_at_20[0x10]; 8550 u8 op_mod[0x10]; 8551 8552 u8 reserved_at_40[0x8]; 8553 u8 uar[0x18]; 8554 8555 u8 reserved_at_60[0x20]; 8556 }; 8557 8558 struct mlx5_ifc_dealloc_transport_domain_out_bits { 8559 u8 status[0x8]; 8560 u8 reserved_at_8[0x18]; 8561 8562 u8 syndrome[0x20]; 8563 8564 u8 reserved_at_40[0x40]; 8565 }; 8566 8567 struct mlx5_ifc_dealloc_transport_domain_in_bits { 8568 u8 opcode[0x10]; 8569 u8 uid[0x10]; 8570 8571 u8 reserved_at_20[0x10]; 8572 u8 op_mod[0x10]; 8573 8574 u8 reserved_at_40[0x8]; 8575 u8 transport_domain[0x18]; 8576 8577 u8 reserved_at_60[0x20]; 8578 }; 8579 8580 struct mlx5_ifc_dealloc_q_counter_out_bits { 8581 u8 status[0x8]; 8582 u8 reserved_at_8[0x18]; 8583 8584 u8 syndrome[0x20]; 8585 8586 u8 reserved_at_40[0x40]; 8587 }; 8588 8589 struct mlx5_ifc_dealloc_q_counter_in_bits { 8590 u8 opcode[0x10]; 8591 u8 reserved_at_10[0x10]; 8592 8593 u8 reserved_at_20[0x10]; 8594 u8 op_mod[0x10]; 8595 8596 u8 reserved_at_40[0x18]; 8597 u8 counter_set_id[0x8]; 8598 8599 u8 reserved_at_60[0x20]; 8600 }; 8601 8602 struct mlx5_ifc_dealloc_pd_out_bits { 8603 u8 status[0x8]; 8604 u8 reserved_at_8[0x18]; 8605 8606 u8 syndrome[0x20]; 8607 8608 u8 reserved_at_40[0x40]; 8609 }; 8610 8611 struct mlx5_ifc_dealloc_pd_in_bits { 8612 u8 opcode[0x10]; 8613 u8 uid[0x10]; 8614 8615 u8 reserved_at_20[0x10]; 8616 u8 op_mod[0x10]; 8617 8618 u8 reserved_at_40[0x8]; 8619 u8 pd[0x18]; 8620 8621 u8 reserved_at_60[0x20]; 8622 }; 8623 8624 struct mlx5_ifc_dealloc_flow_counter_out_bits { 8625 u8 status[0x8]; 8626 u8 reserved_at_8[0x18]; 8627 8628 u8 syndrome[0x20]; 8629 8630 u8 reserved_at_40[0x40]; 8631 }; 8632 8633 struct mlx5_ifc_dealloc_flow_counter_in_bits { 8634 u8 opcode[0x10]; 8635 u8 reserved_at_10[0x10]; 8636 8637 u8 reserved_at_20[0x10]; 8638 u8 op_mod[0x10]; 8639 8640 u8 flow_counter_id[0x20]; 8641 8642 u8 reserved_at_60[0x20]; 8643 }; 8644 8645 struct mlx5_ifc_create_xrq_out_bits { 8646 u8 status[0x8]; 8647 u8 reserved_at_8[0x18]; 8648 8649 u8 syndrome[0x20]; 8650 8651 u8 reserved_at_40[0x8]; 8652 u8 xrqn[0x18]; 8653 8654 u8 reserved_at_60[0x20]; 8655 }; 8656 8657 struct mlx5_ifc_create_xrq_in_bits { 8658 u8 opcode[0x10]; 8659 u8 uid[0x10]; 8660 8661 u8 reserved_at_20[0x10]; 8662 u8 op_mod[0x10]; 8663 8664 u8 reserved_at_40[0x40]; 8665 8666 struct mlx5_ifc_xrqc_bits xrq_context; 8667 }; 8668 8669 struct mlx5_ifc_create_xrc_srq_out_bits { 8670 u8 status[0x8]; 8671 u8 reserved_at_8[0x18]; 8672 8673 u8 syndrome[0x20]; 8674 8675 u8 reserved_at_40[0x8]; 8676 u8 xrc_srqn[0x18]; 8677 8678 u8 reserved_at_60[0x20]; 8679 }; 8680 8681 struct mlx5_ifc_create_xrc_srq_in_bits { 8682 u8 opcode[0x10]; 8683 u8 uid[0x10]; 8684 8685 u8 reserved_at_20[0x10]; 8686 u8 op_mod[0x10]; 8687 8688 u8 reserved_at_40[0x40]; 8689 8690 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 8691 8692 u8 reserved_at_280[0x60]; 8693 8694 u8 xrc_srq_umem_valid[0x1]; 8695 u8 reserved_at_2e1[0x1f]; 8696 8697 u8 reserved_at_300[0x580]; 8698 8699 u8 pas[][0x40]; 8700 }; 8701 8702 struct mlx5_ifc_create_tis_out_bits { 8703 u8 status[0x8]; 8704 u8 reserved_at_8[0x18]; 8705 8706 u8 syndrome[0x20]; 8707 8708 u8 reserved_at_40[0x8]; 8709 u8 tisn[0x18]; 8710 8711 u8 reserved_at_60[0x20]; 8712 }; 8713 8714 struct mlx5_ifc_create_tis_in_bits { 8715 u8 opcode[0x10]; 8716 u8 uid[0x10]; 8717 8718 u8 reserved_at_20[0x10]; 8719 u8 op_mod[0x10]; 8720 8721 u8 reserved_at_40[0xc0]; 8722 8723 struct mlx5_ifc_tisc_bits ctx; 8724 }; 8725 8726 struct mlx5_ifc_create_tir_out_bits { 8727 u8 status[0x8]; 8728 u8 icm_address_63_40[0x18]; 8729 8730 u8 syndrome[0x20]; 8731 8732 u8 icm_address_39_32[0x8]; 8733 u8 tirn[0x18]; 8734 8735 u8 icm_address_31_0[0x20]; 8736 }; 8737 8738 struct mlx5_ifc_create_tir_in_bits { 8739 u8 opcode[0x10]; 8740 u8 uid[0x10]; 8741 8742 u8 reserved_at_20[0x10]; 8743 u8 op_mod[0x10]; 8744 8745 u8 reserved_at_40[0xc0]; 8746 8747 struct mlx5_ifc_tirc_bits ctx; 8748 }; 8749 8750 struct mlx5_ifc_create_srq_out_bits { 8751 u8 status[0x8]; 8752 u8 reserved_at_8[0x18]; 8753 8754 u8 syndrome[0x20]; 8755 8756 u8 reserved_at_40[0x8]; 8757 u8 srqn[0x18]; 8758 8759 u8 reserved_at_60[0x20]; 8760 }; 8761 8762 struct mlx5_ifc_create_srq_in_bits { 8763 u8 opcode[0x10]; 8764 u8 uid[0x10]; 8765 8766 u8 reserved_at_20[0x10]; 8767 u8 op_mod[0x10]; 8768 8769 u8 reserved_at_40[0x40]; 8770 8771 struct mlx5_ifc_srqc_bits srq_context_entry; 8772 8773 u8 reserved_at_280[0x600]; 8774 8775 u8 pas[][0x40]; 8776 }; 8777 8778 struct mlx5_ifc_create_sq_out_bits { 8779 u8 status[0x8]; 8780 u8 reserved_at_8[0x18]; 8781 8782 u8 syndrome[0x20]; 8783 8784 u8 reserved_at_40[0x8]; 8785 u8 sqn[0x18]; 8786 8787 u8 reserved_at_60[0x20]; 8788 }; 8789 8790 struct mlx5_ifc_create_sq_in_bits { 8791 u8 opcode[0x10]; 8792 u8 uid[0x10]; 8793 8794 u8 reserved_at_20[0x10]; 8795 u8 op_mod[0x10]; 8796 8797 u8 reserved_at_40[0xc0]; 8798 8799 struct mlx5_ifc_sqc_bits ctx; 8800 }; 8801 8802 struct mlx5_ifc_create_scheduling_element_out_bits { 8803 u8 status[0x8]; 8804 u8 reserved_at_8[0x18]; 8805 8806 u8 syndrome[0x20]; 8807 8808 u8 reserved_at_40[0x40]; 8809 8810 u8 scheduling_element_id[0x20]; 8811 8812 u8 reserved_at_a0[0x160]; 8813 }; 8814 8815 struct mlx5_ifc_create_scheduling_element_in_bits { 8816 u8 opcode[0x10]; 8817 u8 reserved_at_10[0x10]; 8818 8819 u8 reserved_at_20[0x10]; 8820 u8 op_mod[0x10]; 8821 8822 u8 scheduling_hierarchy[0x8]; 8823 u8 reserved_at_48[0x18]; 8824 8825 u8 reserved_at_60[0xa0]; 8826 8827 struct mlx5_ifc_scheduling_context_bits scheduling_context; 8828 8829 u8 reserved_at_300[0x100]; 8830 }; 8831 8832 struct mlx5_ifc_create_rqt_out_bits { 8833 u8 status[0x8]; 8834 u8 reserved_at_8[0x18]; 8835 8836 u8 syndrome[0x20]; 8837 8838 u8 reserved_at_40[0x8]; 8839 u8 rqtn[0x18]; 8840 8841 u8 reserved_at_60[0x20]; 8842 }; 8843 8844 struct mlx5_ifc_create_rqt_in_bits { 8845 u8 opcode[0x10]; 8846 u8 uid[0x10]; 8847 8848 u8 reserved_at_20[0x10]; 8849 u8 op_mod[0x10]; 8850 8851 u8 reserved_at_40[0xc0]; 8852 8853 struct mlx5_ifc_rqtc_bits rqt_context; 8854 }; 8855 8856 struct mlx5_ifc_create_rq_out_bits { 8857 u8 status[0x8]; 8858 u8 reserved_at_8[0x18]; 8859 8860 u8 syndrome[0x20]; 8861 8862 u8 reserved_at_40[0x8]; 8863 u8 rqn[0x18]; 8864 8865 u8 reserved_at_60[0x20]; 8866 }; 8867 8868 struct mlx5_ifc_create_rq_in_bits { 8869 u8 opcode[0x10]; 8870 u8 uid[0x10]; 8871 8872 u8 reserved_at_20[0x10]; 8873 u8 op_mod[0x10]; 8874 8875 u8 reserved_at_40[0xc0]; 8876 8877 struct mlx5_ifc_rqc_bits ctx; 8878 }; 8879 8880 struct mlx5_ifc_create_rmp_out_bits { 8881 u8 status[0x8]; 8882 u8 reserved_at_8[0x18]; 8883 8884 u8 syndrome[0x20]; 8885 8886 u8 reserved_at_40[0x8]; 8887 u8 rmpn[0x18]; 8888 8889 u8 reserved_at_60[0x20]; 8890 }; 8891 8892 struct mlx5_ifc_create_rmp_in_bits { 8893 u8 opcode[0x10]; 8894 u8 uid[0x10]; 8895 8896 u8 reserved_at_20[0x10]; 8897 u8 op_mod[0x10]; 8898 8899 u8 reserved_at_40[0xc0]; 8900 8901 struct mlx5_ifc_rmpc_bits ctx; 8902 }; 8903 8904 struct mlx5_ifc_create_qp_out_bits { 8905 u8 status[0x8]; 8906 u8 reserved_at_8[0x18]; 8907 8908 u8 syndrome[0x20]; 8909 8910 u8 reserved_at_40[0x8]; 8911 u8 qpn[0x18]; 8912 8913 u8 ece[0x20]; 8914 }; 8915 8916 struct mlx5_ifc_create_qp_in_bits { 8917 u8 opcode[0x10]; 8918 u8 uid[0x10]; 8919 8920 u8 reserved_at_20[0x10]; 8921 u8 op_mod[0x10]; 8922 8923 u8 qpc_ext[0x1]; 8924 u8 reserved_at_41[0x7]; 8925 u8 input_qpn[0x18]; 8926 8927 u8 reserved_at_60[0x20]; 8928 u8 opt_param_mask[0x20]; 8929 8930 u8 ece[0x20]; 8931 8932 struct mlx5_ifc_qpc_bits qpc; 8933 8934 u8 reserved_at_800[0x60]; 8935 8936 u8 wq_umem_valid[0x1]; 8937 u8 reserved_at_861[0x1f]; 8938 8939 u8 pas[][0x40]; 8940 }; 8941 8942 struct mlx5_ifc_create_psv_out_bits { 8943 u8 status[0x8]; 8944 u8 reserved_at_8[0x18]; 8945 8946 u8 syndrome[0x20]; 8947 8948 u8 reserved_at_40[0x40]; 8949 8950 u8 reserved_at_80[0x8]; 8951 u8 psv0_index[0x18]; 8952 8953 u8 reserved_at_a0[0x8]; 8954 u8 psv1_index[0x18]; 8955 8956 u8 reserved_at_c0[0x8]; 8957 u8 psv2_index[0x18]; 8958 8959 u8 reserved_at_e0[0x8]; 8960 u8 psv3_index[0x18]; 8961 }; 8962 8963 struct mlx5_ifc_create_psv_in_bits { 8964 u8 opcode[0x10]; 8965 u8 reserved_at_10[0x10]; 8966 8967 u8 reserved_at_20[0x10]; 8968 u8 op_mod[0x10]; 8969 8970 u8 num_psv[0x4]; 8971 u8 reserved_at_44[0x4]; 8972 u8 pd[0x18]; 8973 8974 u8 reserved_at_60[0x20]; 8975 }; 8976 8977 struct mlx5_ifc_create_mkey_out_bits { 8978 u8 status[0x8]; 8979 u8 reserved_at_8[0x18]; 8980 8981 u8 syndrome[0x20]; 8982 8983 u8 reserved_at_40[0x8]; 8984 u8 mkey_index[0x18]; 8985 8986 u8 reserved_at_60[0x20]; 8987 }; 8988 8989 struct mlx5_ifc_create_mkey_in_bits { 8990 u8 opcode[0x10]; 8991 u8 uid[0x10]; 8992 8993 u8 reserved_at_20[0x10]; 8994 u8 op_mod[0x10]; 8995 8996 u8 reserved_at_40[0x20]; 8997 8998 u8 pg_access[0x1]; 8999 u8 mkey_umem_valid[0x1]; 9000 u8 reserved_at_62[0x1e]; 9001 9002 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 9003 9004 u8 reserved_at_280[0x80]; 9005 9006 u8 translations_octword_actual_size[0x20]; 9007 9008 u8 reserved_at_320[0x560]; 9009 9010 u8 klm_pas_mtt[][0x20]; 9011 }; 9012 9013 enum { 9014 MLX5_FLOW_TABLE_TYPE_NIC_RX = 0x0, 9015 MLX5_FLOW_TABLE_TYPE_NIC_TX = 0x1, 9016 MLX5_FLOW_TABLE_TYPE_ESW_EGRESS_ACL = 0x2, 9017 MLX5_FLOW_TABLE_TYPE_ESW_INGRESS_ACL = 0x3, 9018 MLX5_FLOW_TABLE_TYPE_FDB = 0X4, 9019 MLX5_FLOW_TABLE_TYPE_SNIFFER_RX = 0X5, 9020 MLX5_FLOW_TABLE_TYPE_SNIFFER_TX = 0X6, 9021 }; 9022 9023 struct mlx5_ifc_create_flow_table_out_bits { 9024 u8 status[0x8]; 9025 u8 icm_address_63_40[0x18]; 9026 9027 u8 syndrome[0x20]; 9028 9029 u8 icm_address_39_32[0x8]; 9030 u8 table_id[0x18]; 9031 9032 u8 icm_address_31_0[0x20]; 9033 }; 9034 9035 struct mlx5_ifc_create_flow_table_in_bits { 9036 u8 opcode[0x10]; 9037 u8 uid[0x10]; 9038 9039 u8 reserved_at_20[0x10]; 9040 u8 op_mod[0x10]; 9041 9042 u8 other_vport[0x1]; 9043 u8 reserved_at_41[0xf]; 9044 u8 vport_number[0x10]; 9045 9046 u8 reserved_at_60[0x20]; 9047 9048 u8 table_type[0x8]; 9049 u8 reserved_at_88[0x18]; 9050 9051 u8 reserved_at_a0[0x20]; 9052 9053 struct mlx5_ifc_flow_table_context_bits flow_table_context; 9054 }; 9055 9056 struct mlx5_ifc_create_flow_group_out_bits { 9057 u8 status[0x8]; 9058 u8 reserved_at_8[0x18]; 9059 9060 u8 syndrome[0x20]; 9061 9062 u8 reserved_at_40[0x8]; 9063 u8 group_id[0x18]; 9064 9065 u8 reserved_at_60[0x20]; 9066 }; 9067 9068 enum { 9069 MLX5_CREATE_FLOW_GROUP_IN_GROUP_TYPE_TCAM_SUBTABLE = 0x0, 9070 MLX5_CREATE_FLOW_GROUP_IN_GROUP_TYPE_HASH_SPLIT = 0x1, 9071 }; 9072 9073 enum { 9074 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 9075 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 9076 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 9077 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3, 9078 }; 9079 9080 struct mlx5_ifc_create_flow_group_in_bits { 9081 u8 opcode[0x10]; 9082 u8 reserved_at_10[0x10]; 9083 9084 u8 reserved_at_20[0x10]; 9085 u8 op_mod[0x10]; 9086 9087 u8 other_vport[0x1]; 9088 u8 reserved_at_41[0xf]; 9089 u8 vport_number[0x10]; 9090 9091 u8 reserved_at_60[0x20]; 9092 9093 u8 table_type[0x8]; 9094 u8 reserved_at_88[0x4]; 9095 u8 group_type[0x4]; 9096 u8 reserved_at_90[0x10]; 9097 9098 u8 reserved_at_a0[0x8]; 9099 u8 table_id[0x18]; 9100 9101 u8 source_eswitch_owner_vhca_id_valid[0x1]; 9102 9103 u8 reserved_at_c1[0x1f]; 9104 9105 u8 start_flow_index[0x20]; 9106 9107 u8 reserved_at_100[0x20]; 9108 9109 u8 end_flow_index[0x20]; 9110 9111 u8 reserved_at_140[0x10]; 9112 u8 match_definer_id[0x10]; 9113 9114 u8 reserved_at_160[0x80]; 9115 9116 u8 reserved_at_1e0[0x18]; 9117 u8 match_criteria_enable[0x8]; 9118 9119 struct mlx5_ifc_fte_match_param_bits match_criteria; 9120 9121 u8 reserved_at_1200[0xe00]; 9122 }; 9123 9124 struct mlx5_ifc_create_eq_out_bits { 9125 u8 status[0x8]; 9126 u8 reserved_at_8[0x18]; 9127 9128 u8 syndrome[0x20]; 9129 9130 u8 reserved_at_40[0x18]; 9131 u8 eq_number[0x8]; 9132 9133 u8 reserved_at_60[0x20]; 9134 }; 9135 9136 struct mlx5_ifc_create_eq_in_bits { 9137 u8 opcode[0x10]; 9138 u8 uid[0x10]; 9139 9140 u8 reserved_at_20[0x10]; 9141 u8 op_mod[0x10]; 9142 9143 u8 reserved_at_40[0x40]; 9144 9145 struct mlx5_ifc_eqc_bits eq_context_entry; 9146 9147 u8 reserved_at_280[0x40]; 9148 9149 u8 event_bitmask[4][0x40]; 9150 9151 u8 reserved_at_3c0[0x4c0]; 9152 9153 u8 pas[][0x40]; 9154 }; 9155 9156 struct mlx5_ifc_create_dct_out_bits { 9157 u8 status[0x8]; 9158 u8 reserved_at_8[0x18]; 9159 9160 u8 syndrome[0x20]; 9161 9162 u8 reserved_at_40[0x8]; 9163 u8 dctn[0x18]; 9164 9165 u8 ece[0x20]; 9166 }; 9167 9168 struct mlx5_ifc_create_dct_in_bits { 9169 u8 opcode[0x10]; 9170 u8 uid[0x10]; 9171 9172 u8 reserved_at_20[0x10]; 9173 u8 op_mod[0x10]; 9174 9175 u8 reserved_at_40[0x40]; 9176 9177 struct mlx5_ifc_dctc_bits dct_context_entry; 9178 9179 u8 reserved_at_280[0x180]; 9180 }; 9181 9182 struct mlx5_ifc_create_cq_out_bits { 9183 u8 status[0x8]; 9184 u8 reserved_at_8[0x18]; 9185 9186 u8 syndrome[0x20]; 9187 9188 u8 reserved_at_40[0x8]; 9189 u8 cqn[0x18]; 9190 9191 u8 reserved_at_60[0x20]; 9192 }; 9193 9194 struct mlx5_ifc_create_cq_in_bits { 9195 u8 opcode[0x10]; 9196 u8 uid[0x10]; 9197 9198 u8 reserved_at_20[0x10]; 9199 u8 op_mod[0x10]; 9200 9201 u8 reserved_at_40[0x40]; 9202 9203 struct mlx5_ifc_cqc_bits cq_context; 9204 9205 u8 reserved_at_280[0x60]; 9206 9207 u8 cq_umem_valid[0x1]; 9208 u8 reserved_at_2e1[0x59f]; 9209 9210 u8 pas[][0x40]; 9211 }; 9212 9213 struct mlx5_ifc_config_int_moderation_out_bits { 9214 u8 status[0x8]; 9215 u8 reserved_at_8[0x18]; 9216 9217 u8 syndrome[0x20]; 9218 9219 u8 reserved_at_40[0x4]; 9220 u8 min_delay[0xc]; 9221 u8 int_vector[0x10]; 9222 9223 u8 reserved_at_60[0x20]; 9224 }; 9225 9226 enum { 9227 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0, 9228 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1, 9229 }; 9230 9231 struct mlx5_ifc_config_int_moderation_in_bits { 9232 u8 opcode[0x10]; 9233 u8 reserved_at_10[0x10]; 9234 9235 u8 reserved_at_20[0x10]; 9236 u8 op_mod[0x10]; 9237 9238 u8 reserved_at_40[0x4]; 9239 u8 min_delay[0xc]; 9240 u8 int_vector[0x10]; 9241 9242 u8 reserved_at_60[0x20]; 9243 }; 9244 9245 struct mlx5_ifc_attach_to_mcg_out_bits { 9246 u8 status[0x8]; 9247 u8 reserved_at_8[0x18]; 9248 9249 u8 syndrome[0x20]; 9250 9251 u8 reserved_at_40[0x40]; 9252 }; 9253 9254 struct mlx5_ifc_attach_to_mcg_in_bits { 9255 u8 opcode[0x10]; 9256 u8 uid[0x10]; 9257 9258 u8 reserved_at_20[0x10]; 9259 u8 op_mod[0x10]; 9260 9261 u8 reserved_at_40[0x8]; 9262 u8 qpn[0x18]; 9263 9264 u8 reserved_at_60[0x20]; 9265 9266 u8 multicast_gid[16][0x8]; 9267 }; 9268 9269 struct mlx5_ifc_arm_xrq_out_bits { 9270 u8 status[0x8]; 9271 u8 reserved_at_8[0x18]; 9272 9273 u8 syndrome[0x20]; 9274 9275 u8 reserved_at_40[0x40]; 9276 }; 9277 9278 struct mlx5_ifc_arm_xrq_in_bits { 9279 u8 opcode[0x10]; 9280 u8 reserved_at_10[0x10]; 9281 9282 u8 reserved_at_20[0x10]; 9283 u8 op_mod[0x10]; 9284 9285 u8 reserved_at_40[0x8]; 9286 u8 xrqn[0x18]; 9287 9288 u8 reserved_at_60[0x10]; 9289 u8 lwm[0x10]; 9290 }; 9291 9292 struct mlx5_ifc_arm_xrc_srq_out_bits { 9293 u8 status[0x8]; 9294 u8 reserved_at_8[0x18]; 9295 9296 u8 syndrome[0x20]; 9297 9298 u8 reserved_at_40[0x40]; 9299 }; 9300 9301 enum { 9302 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1, 9303 }; 9304 9305 struct mlx5_ifc_arm_xrc_srq_in_bits { 9306 u8 opcode[0x10]; 9307 u8 uid[0x10]; 9308 9309 u8 reserved_at_20[0x10]; 9310 u8 op_mod[0x10]; 9311 9312 u8 reserved_at_40[0x8]; 9313 u8 xrc_srqn[0x18]; 9314 9315 u8 reserved_at_60[0x10]; 9316 u8 lwm[0x10]; 9317 }; 9318 9319 struct mlx5_ifc_arm_rq_out_bits { 9320 u8 status[0x8]; 9321 u8 reserved_at_8[0x18]; 9322 9323 u8 syndrome[0x20]; 9324 9325 u8 reserved_at_40[0x40]; 9326 }; 9327 9328 enum { 9329 MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1, 9330 MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2, 9331 }; 9332 9333 struct mlx5_ifc_arm_rq_in_bits { 9334 u8 opcode[0x10]; 9335 u8 uid[0x10]; 9336 9337 u8 reserved_at_20[0x10]; 9338 u8 op_mod[0x10]; 9339 9340 u8 reserved_at_40[0x8]; 9341 u8 srq_number[0x18]; 9342 9343 u8 reserved_at_60[0x10]; 9344 u8 lwm[0x10]; 9345 }; 9346 9347 struct mlx5_ifc_arm_dct_out_bits { 9348 u8 status[0x8]; 9349 u8 reserved_at_8[0x18]; 9350 9351 u8 syndrome[0x20]; 9352 9353 u8 reserved_at_40[0x40]; 9354 }; 9355 9356 struct mlx5_ifc_arm_dct_in_bits { 9357 u8 opcode[0x10]; 9358 u8 reserved_at_10[0x10]; 9359 9360 u8 reserved_at_20[0x10]; 9361 u8 op_mod[0x10]; 9362 9363 u8 reserved_at_40[0x8]; 9364 u8 dct_number[0x18]; 9365 9366 u8 reserved_at_60[0x20]; 9367 }; 9368 9369 struct mlx5_ifc_alloc_xrcd_out_bits { 9370 u8 status[0x8]; 9371 u8 reserved_at_8[0x18]; 9372 9373 u8 syndrome[0x20]; 9374 9375 u8 reserved_at_40[0x8]; 9376 u8 xrcd[0x18]; 9377 9378 u8 reserved_at_60[0x20]; 9379 }; 9380 9381 struct mlx5_ifc_alloc_xrcd_in_bits { 9382 u8 opcode[0x10]; 9383 u8 uid[0x10]; 9384 9385 u8 reserved_at_20[0x10]; 9386 u8 op_mod[0x10]; 9387 9388 u8 reserved_at_40[0x40]; 9389 }; 9390 9391 struct mlx5_ifc_alloc_uar_out_bits { 9392 u8 status[0x8]; 9393 u8 reserved_at_8[0x18]; 9394 9395 u8 syndrome[0x20]; 9396 9397 u8 reserved_at_40[0x8]; 9398 u8 uar[0x18]; 9399 9400 u8 reserved_at_60[0x20]; 9401 }; 9402 9403 struct mlx5_ifc_alloc_uar_in_bits { 9404 u8 opcode[0x10]; 9405 u8 uid[0x10]; 9406 9407 u8 reserved_at_20[0x10]; 9408 u8 op_mod[0x10]; 9409 9410 u8 reserved_at_40[0x40]; 9411 }; 9412 9413 struct mlx5_ifc_alloc_transport_domain_out_bits { 9414 u8 status[0x8]; 9415 u8 reserved_at_8[0x18]; 9416 9417 u8 syndrome[0x20]; 9418 9419 u8 reserved_at_40[0x8]; 9420 u8 transport_domain[0x18]; 9421 9422 u8 reserved_at_60[0x20]; 9423 }; 9424 9425 struct mlx5_ifc_alloc_transport_domain_in_bits { 9426 u8 opcode[0x10]; 9427 u8 uid[0x10]; 9428 9429 u8 reserved_at_20[0x10]; 9430 u8 op_mod[0x10]; 9431 9432 u8 reserved_at_40[0x40]; 9433 }; 9434 9435 struct mlx5_ifc_alloc_q_counter_out_bits { 9436 u8 status[0x8]; 9437 u8 reserved_at_8[0x18]; 9438 9439 u8 syndrome[0x20]; 9440 9441 u8 reserved_at_40[0x18]; 9442 u8 counter_set_id[0x8]; 9443 9444 u8 reserved_at_60[0x20]; 9445 }; 9446 9447 struct mlx5_ifc_alloc_q_counter_in_bits { 9448 u8 opcode[0x10]; 9449 u8 uid[0x10]; 9450 9451 u8 reserved_at_20[0x10]; 9452 u8 op_mod[0x10]; 9453 9454 u8 reserved_at_40[0x40]; 9455 }; 9456 9457 struct mlx5_ifc_alloc_pd_out_bits { 9458 u8 status[0x8]; 9459 u8 reserved_at_8[0x18]; 9460 9461 u8 syndrome[0x20]; 9462 9463 u8 reserved_at_40[0x8]; 9464 u8 pd[0x18]; 9465 9466 u8 reserved_at_60[0x20]; 9467 }; 9468 9469 struct mlx5_ifc_alloc_pd_in_bits { 9470 u8 opcode[0x10]; 9471 u8 uid[0x10]; 9472 9473 u8 reserved_at_20[0x10]; 9474 u8 op_mod[0x10]; 9475 9476 u8 reserved_at_40[0x40]; 9477 }; 9478 9479 struct mlx5_ifc_alloc_flow_counter_out_bits { 9480 u8 status[0x8]; 9481 u8 reserved_at_8[0x18]; 9482 9483 u8 syndrome[0x20]; 9484 9485 u8 flow_counter_id[0x20]; 9486 9487 u8 reserved_at_60[0x20]; 9488 }; 9489 9490 struct mlx5_ifc_alloc_flow_counter_in_bits { 9491 u8 opcode[0x10]; 9492 u8 reserved_at_10[0x10]; 9493 9494 u8 reserved_at_20[0x10]; 9495 u8 op_mod[0x10]; 9496 9497 u8 reserved_at_40[0x33]; 9498 u8 flow_counter_bulk_log_size[0x5]; 9499 u8 flow_counter_bulk[0x8]; 9500 }; 9501 9502 struct mlx5_ifc_add_vxlan_udp_dport_out_bits { 9503 u8 status[0x8]; 9504 u8 reserved_at_8[0x18]; 9505 9506 u8 syndrome[0x20]; 9507 9508 u8 reserved_at_40[0x40]; 9509 }; 9510 9511 struct mlx5_ifc_add_vxlan_udp_dport_in_bits { 9512 u8 opcode[0x10]; 9513 u8 reserved_at_10[0x10]; 9514 9515 u8 reserved_at_20[0x10]; 9516 u8 op_mod[0x10]; 9517 9518 u8 reserved_at_40[0x20]; 9519 9520 u8 reserved_at_60[0x10]; 9521 u8 vxlan_udp_port[0x10]; 9522 }; 9523 9524 struct mlx5_ifc_set_pp_rate_limit_out_bits { 9525 u8 status[0x8]; 9526 u8 reserved_at_8[0x18]; 9527 9528 u8 syndrome[0x20]; 9529 9530 u8 reserved_at_40[0x40]; 9531 }; 9532 9533 struct mlx5_ifc_set_pp_rate_limit_context_bits { 9534 u8 rate_limit[0x20]; 9535 9536 u8 burst_upper_bound[0x20]; 9537 9538 u8 reserved_at_40[0x10]; 9539 u8 typical_packet_size[0x10]; 9540 9541 u8 reserved_at_60[0x120]; 9542 }; 9543 9544 struct mlx5_ifc_set_pp_rate_limit_in_bits { 9545 u8 opcode[0x10]; 9546 u8 uid[0x10]; 9547 9548 u8 reserved_at_20[0x10]; 9549 u8 op_mod[0x10]; 9550 9551 u8 reserved_at_40[0x10]; 9552 u8 rate_limit_index[0x10]; 9553 9554 u8 reserved_at_60[0x20]; 9555 9556 struct mlx5_ifc_set_pp_rate_limit_context_bits ctx; 9557 }; 9558 9559 struct mlx5_ifc_access_register_out_bits { 9560 u8 status[0x8]; 9561 u8 reserved_at_8[0x18]; 9562 9563 u8 syndrome[0x20]; 9564 9565 u8 reserved_at_40[0x40]; 9566 9567 u8 register_data[][0x20]; 9568 }; 9569 9570 enum { 9571 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0, 9572 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1, 9573 }; 9574 9575 struct mlx5_ifc_access_register_in_bits { 9576 u8 opcode[0x10]; 9577 u8 reserved_at_10[0x10]; 9578 9579 u8 reserved_at_20[0x10]; 9580 u8 op_mod[0x10]; 9581 9582 u8 reserved_at_40[0x10]; 9583 u8 register_id[0x10]; 9584 9585 u8 argument[0x20]; 9586 9587 u8 register_data[][0x20]; 9588 }; 9589 9590 struct mlx5_ifc_sltp_reg_bits { 9591 u8 status[0x4]; 9592 u8 version[0x4]; 9593 u8 local_port[0x8]; 9594 u8 pnat[0x2]; 9595 u8 reserved_at_12[0x2]; 9596 u8 lane[0x4]; 9597 u8 reserved_at_18[0x8]; 9598 9599 u8 reserved_at_20[0x20]; 9600 9601 u8 reserved_at_40[0x7]; 9602 u8 polarity[0x1]; 9603 u8 ob_tap0[0x8]; 9604 u8 ob_tap1[0x8]; 9605 u8 ob_tap2[0x8]; 9606 9607 u8 reserved_at_60[0xc]; 9608 u8 ob_preemp_mode[0x4]; 9609 u8 ob_reg[0x8]; 9610 u8 ob_bias[0x8]; 9611 9612 u8 reserved_at_80[0x20]; 9613 }; 9614 9615 struct mlx5_ifc_slrg_reg_bits { 9616 u8 status[0x4]; 9617 u8 version[0x4]; 9618 u8 local_port[0x8]; 9619 u8 pnat[0x2]; 9620 u8 reserved_at_12[0x2]; 9621 u8 lane[0x4]; 9622 u8 reserved_at_18[0x8]; 9623 9624 u8 time_to_link_up[0x10]; 9625 u8 reserved_at_30[0xc]; 9626 u8 grade_lane_speed[0x4]; 9627 9628 u8 grade_version[0x8]; 9629 u8 grade[0x18]; 9630 9631 u8 reserved_at_60[0x4]; 9632 u8 height_grade_type[0x4]; 9633 u8 height_grade[0x18]; 9634 9635 u8 height_dz[0x10]; 9636 u8 height_dv[0x10]; 9637 9638 u8 reserved_at_a0[0x10]; 9639 u8 height_sigma[0x10]; 9640 9641 u8 reserved_at_c0[0x20]; 9642 9643 u8 reserved_at_e0[0x4]; 9644 u8 phase_grade_type[0x4]; 9645 u8 phase_grade[0x18]; 9646 9647 u8 reserved_at_100[0x8]; 9648 u8 phase_eo_pos[0x8]; 9649 u8 reserved_at_110[0x8]; 9650 u8 phase_eo_neg[0x8]; 9651 9652 u8 ffe_set_tested[0x10]; 9653 u8 test_errors_per_lane[0x10]; 9654 }; 9655 9656 struct mlx5_ifc_pvlc_reg_bits { 9657 u8 reserved_at_0[0x8]; 9658 u8 local_port[0x8]; 9659 u8 reserved_at_10[0x10]; 9660 9661 u8 reserved_at_20[0x1c]; 9662 u8 vl_hw_cap[0x4]; 9663 9664 u8 reserved_at_40[0x1c]; 9665 u8 vl_admin[0x4]; 9666 9667 u8 reserved_at_60[0x1c]; 9668 u8 vl_operational[0x4]; 9669 }; 9670 9671 struct mlx5_ifc_pude_reg_bits { 9672 u8 swid[0x8]; 9673 u8 local_port[0x8]; 9674 u8 reserved_at_10[0x4]; 9675 u8 admin_status[0x4]; 9676 u8 reserved_at_18[0x4]; 9677 u8 oper_status[0x4]; 9678 9679 u8 reserved_at_20[0x60]; 9680 }; 9681 9682 struct mlx5_ifc_ptys_reg_bits { 9683 u8 reserved_at_0[0x1]; 9684 u8 an_disable_admin[0x1]; 9685 u8 an_disable_cap[0x1]; 9686 u8 reserved_at_3[0x5]; 9687 u8 local_port[0x8]; 9688 u8 reserved_at_10[0x8]; 9689 u8 plane_ind[0x4]; 9690 u8 reserved_at_1c[0x1]; 9691 u8 proto_mask[0x3]; 9692 9693 u8 an_status[0x4]; 9694 u8 reserved_at_24[0xc]; 9695 u8 data_rate_oper[0x10]; 9696 9697 u8 ext_eth_proto_capability[0x20]; 9698 9699 u8 eth_proto_capability[0x20]; 9700 9701 u8 ib_link_width_capability[0x10]; 9702 u8 ib_proto_capability[0x10]; 9703 9704 u8 ext_eth_proto_admin[0x20]; 9705 9706 u8 eth_proto_admin[0x20]; 9707 9708 u8 ib_link_width_admin[0x10]; 9709 u8 ib_proto_admin[0x10]; 9710 9711 u8 ext_eth_proto_oper[0x20]; 9712 9713 u8 eth_proto_oper[0x20]; 9714 9715 u8 ib_link_width_oper[0x10]; 9716 u8 ib_proto_oper[0x10]; 9717 9718 u8 reserved_at_160[0x1c]; 9719 u8 connector_type[0x4]; 9720 9721 u8 eth_proto_lp_advertise[0x20]; 9722 9723 u8 reserved_at_1a0[0x60]; 9724 }; 9725 9726 struct mlx5_ifc_mlcr_reg_bits { 9727 u8 reserved_at_0[0x8]; 9728 u8 local_port[0x8]; 9729 u8 reserved_at_10[0x20]; 9730 9731 u8 beacon_duration[0x10]; 9732 u8 reserved_at_40[0x10]; 9733 9734 u8 beacon_remain[0x10]; 9735 }; 9736 9737 struct mlx5_ifc_ptas_reg_bits { 9738 u8 reserved_at_0[0x20]; 9739 9740 u8 algorithm_options[0x10]; 9741 u8 reserved_at_30[0x4]; 9742 u8 repetitions_mode[0x4]; 9743 u8 num_of_repetitions[0x8]; 9744 9745 u8 grade_version[0x8]; 9746 u8 height_grade_type[0x4]; 9747 u8 phase_grade_type[0x4]; 9748 u8 height_grade_weight[0x8]; 9749 u8 phase_grade_weight[0x8]; 9750 9751 u8 gisim_measure_bits[0x10]; 9752 u8 adaptive_tap_measure_bits[0x10]; 9753 9754 u8 ber_bath_high_error_threshold[0x10]; 9755 u8 ber_bath_mid_error_threshold[0x10]; 9756 9757 u8 ber_bath_low_error_threshold[0x10]; 9758 u8 one_ratio_high_threshold[0x10]; 9759 9760 u8 one_ratio_high_mid_threshold[0x10]; 9761 u8 one_ratio_low_mid_threshold[0x10]; 9762 9763 u8 one_ratio_low_threshold[0x10]; 9764 u8 ndeo_error_threshold[0x10]; 9765 9766 u8 mixer_offset_step_size[0x10]; 9767 u8 reserved_at_110[0x8]; 9768 u8 mix90_phase_for_voltage_bath[0x8]; 9769 9770 u8 mixer_offset_start[0x10]; 9771 u8 mixer_offset_end[0x10]; 9772 9773 u8 reserved_at_140[0x15]; 9774 u8 ber_test_time[0xb]; 9775 }; 9776 9777 struct mlx5_ifc_pspa_reg_bits { 9778 u8 swid[0x8]; 9779 u8 local_port[0x8]; 9780 u8 sub_port[0x8]; 9781 u8 reserved_at_18[0x8]; 9782 9783 u8 reserved_at_20[0x20]; 9784 }; 9785 9786 struct mlx5_ifc_pqdr_reg_bits { 9787 u8 reserved_at_0[0x8]; 9788 u8 local_port[0x8]; 9789 u8 reserved_at_10[0x5]; 9790 u8 prio[0x3]; 9791 u8 reserved_at_18[0x6]; 9792 u8 mode[0x2]; 9793 9794 u8 reserved_at_20[0x20]; 9795 9796 u8 reserved_at_40[0x10]; 9797 u8 min_threshold[0x10]; 9798 9799 u8 reserved_at_60[0x10]; 9800 u8 max_threshold[0x10]; 9801 9802 u8 reserved_at_80[0x10]; 9803 u8 mark_probability_denominator[0x10]; 9804 9805 u8 reserved_at_a0[0x60]; 9806 }; 9807 9808 struct mlx5_ifc_ppsc_reg_bits { 9809 u8 reserved_at_0[0x8]; 9810 u8 local_port[0x8]; 9811 u8 reserved_at_10[0x10]; 9812 9813 u8 reserved_at_20[0x60]; 9814 9815 u8 reserved_at_80[0x1c]; 9816 u8 wrps_admin[0x4]; 9817 9818 u8 reserved_at_a0[0x1c]; 9819 u8 wrps_status[0x4]; 9820 9821 u8 reserved_at_c0[0x8]; 9822 u8 up_threshold[0x8]; 9823 u8 reserved_at_d0[0x8]; 9824 u8 down_threshold[0x8]; 9825 9826 u8 reserved_at_e0[0x20]; 9827 9828 u8 reserved_at_100[0x1c]; 9829 u8 srps_admin[0x4]; 9830 9831 u8 reserved_at_120[0x1c]; 9832 u8 srps_status[0x4]; 9833 9834 u8 reserved_at_140[0x40]; 9835 }; 9836 9837 struct mlx5_ifc_pplr_reg_bits { 9838 u8 reserved_at_0[0x8]; 9839 u8 local_port[0x8]; 9840 u8 reserved_at_10[0x10]; 9841 9842 u8 reserved_at_20[0x8]; 9843 u8 lb_cap[0x8]; 9844 u8 reserved_at_30[0x8]; 9845 u8 lb_en[0x8]; 9846 }; 9847 9848 struct mlx5_ifc_pplm_reg_bits { 9849 u8 reserved_at_0[0x8]; 9850 u8 local_port[0x8]; 9851 u8 reserved_at_10[0x10]; 9852 9853 u8 reserved_at_20[0x20]; 9854 9855 u8 port_profile_mode[0x8]; 9856 u8 static_port_profile[0x8]; 9857 u8 active_port_profile[0x8]; 9858 u8 reserved_at_58[0x8]; 9859 9860 u8 retransmission_active[0x8]; 9861 u8 fec_mode_active[0x18]; 9862 9863 u8 rs_fec_correction_bypass_cap[0x4]; 9864 u8 reserved_at_84[0x8]; 9865 u8 fec_override_cap_56g[0x4]; 9866 u8 fec_override_cap_100g[0x4]; 9867 u8 fec_override_cap_50g[0x4]; 9868 u8 fec_override_cap_25g[0x4]; 9869 u8 fec_override_cap_10g_40g[0x4]; 9870 9871 u8 rs_fec_correction_bypass_admin[0x4]; 9872 u8 reserved_at_a4[0x8]; 9873 u8 fec_override_admin_56g[0x4]; 9874 u8 fec_override_admin_100g[0x4]; 9875 u8 fec_override_admin_50g[0x4]; 9876 u8 fec_override_admin_25g[0x4]; 9877 u8 fec_override_admin_10g_40g[0x4]; 9878 9879 u8 fec_override_cap_400g_8x[0x10]; 9880 u8 fec_override_cap_200g_4x[0x10]; 9881 9882 u8 fec_override_cap_100g_2x[0x10]; 9883 u8 fec_override_cap_50g_1x[0x10]; 9884 9885 u8 fec_override_admin_400g_8x[0x10]; 9886 u8 fec_override_admin_200g_4x[0x10]; 9887 9888 u8 fec_override_admin_100g_2x[0x10]; 9889 u8 fec_override_admin_50g_1x[0x10]; 9890 9891 u8 fec_override_cap_800g_8x[0x10]; 9892 u8 fec_override_cap_400g_4x[0x10]; 9893 9894 u8 fec_override_cap_200g_2x[0x10]; 9895 u8 fec_override_cap_100g_1x[0x10]; 9896 9897 u8 reserved_at_180[0xa0]; 9898 9899 u8 fec_override_admin_800g_8x[0x10]; 9900 u8 fec_override_admin_400g_4x[0x10]; 9901 9902 u8 fec_override_admin_200g_2x[0x10]; 9903 u8 fec_override_admin_100g_1x[0x10]; 9904 9905 u8 reserved_at_260[0x20]; 9906 }; 9907 9908 struct mlx5_ifc_ppcnt_reg_bits { 9909 u8 swid[0x8]; 9910 u8 local_port[0x8]; 9911 u8 pnat[0x2]; 9912 u8 reserved_at_12[0x8]; 9913 u8 grp[0x6]; 9914 9915 u8 clr[0x1]; 9916 u8 reserved_at_21[0x13]; 9917 u8 plane_ind[0x4]; 9918 u8 reserved_at_38[0x3]; 9919 u8 prio_tc[0x5]; 9920 9921 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set; 9922 }; 9923 9924 struct mlx5_ifc_mpein_reg_bits { 9925 u8 reserved_at_0[0x2]; 9926 u8 depth[0x6]; 9927 u8 pcie_index[0x8]; 9928 u8 node[0x8]; 9929 u8 reserved_at_18[0x8]; 9930 9931 u8 capability_mask[0x20]; 9932 9933 u8 reserved_at_40[0x8]; 9934 u8 link_width_enabled[0x8]; 9935 u8 link_speed_enabled[0x10]; 9936 9937 u8 lane0_physical_position[0x8]; 9938 u8 link_width_active[0x8]; 9939 u8 link_speed_active[0x10]; 9940 9941 u8 num_of_pfs[0x10]; 9942 u8 num_of_vfs[0x10]; 9943 9944 u8 bdf0[0x10]; 9945 u8 reserved_at_b0[0x10]; 9946 9947 u8 max_read_request_size[0x4]; 9948 u8 max_payload_size[0x4]; 9949 u8 reserved_at_c8[0x5]; 9950 u8 pwr_status[0x3]; 9951 u8 port_type[0x4]; 9952 u8 reserved_at_d4[0xb]; 9953 u8 lane_reversal[0x1]; 9954 9955 u8 reserved_at_e0[0x14]; 9956 u8 pci_power[0xc]; 9957 9958 u8 reserved_at_100[0x20]; 9959 9960 u8 device_status[0x10]; 9961 u8 port_state[0x8]; 9962 u8 reserved_at_138[0x8]; 9963 9964 u8 reserved_at_140[0x10]; 9965 u8 receiver_detect_result[0x10]; 9966 9967 u8 reserved_at_160[0x20]; 9968 }; 9969 9970 struct mlx5_ifc_mpcnt_reg_bits { 9971 u8 reserved_at_0[0x8]; 9972 u8 pcie_index[0x8]; 9973 u8 reserved_at_10[0xa]; 9974 u8 grp[0x6]; 9975 9976 u8 clr[0x1]; 9977 u8 reserved_at_21[0x1f]; 9978 9979 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set; 9980 }; 9981 9982 struct mlx5_ifc_ppad_reg_bits { 9983 u8 reserved_at_0[0x3]; 9984 u8 single_mac[0x1]; 9985 u8 reserved_at_4[0x4]; 9986 u8 local_port[0x8]; 9987 u8 mac_47_32[0x10]; 9988 9989 u8 mac_31_0[0x20]; 9990 9991 u8 reserved_at_40[0x40]; 9992 }; 9993 9994 struct mlx5_ifc_pmtu_reg_bits { 9995 u8 reserved_at_0[0x8]; 9996 u8 local_port[0x8]; 9997 u8 reserved_at_10[0x10]; 9998 9999 u8 max_mtu[0x10]; 10000 u8 reserved_at_30[0x10]; 10001 10002 u8 admin_mtu[0x10]; 10003 u8 reserved_at_50[0x10]; 10004 10005 u8 oper_mtu[0x10]; 10006 u8 reserved_at_70[0x10]; 10007 }; 10008 10009 struct mlx5_ifc_pmpr_reg_bits { 10010 u8 reserved_at_0[0x8]; 10011 u8 module[0x8]; 10012 u8 reserved_at_10[0x10]; 10013 10014 u8 reserved_at_20[0x18]; 10015 u8 attenuation_5g[0x8]; 10016 10017 u8 reserved_at_40[0x18]; 10018 u8 attenuation_7g[0x8]; 10019 10020 u8 reserved_at_60[0x18]; 10021 u8 attenuation_12g[0x8]; 10022 }; 10023 10024 struct mlx5_ifc_pmpe_reg_bits { 10025 u8 reserved_at_0[0x8]; 10026 u8 module[0x8]; 10027 u8 reserved_at_10[0xc]; 10028 u8 module_status[0x4]; 10029 10030 u8 reserved_at_20[0x60]; 10031 }; 10032 10033 struct mlx5_ifc_pmpc_reg_bits { 10034 u8 module_state_updated[32][0x8]; 10035 }; 10036 10037 struct mlx5_ifc_pmlpn_reg_bits { 10038 u8 reserved_at_0[0x4]; 10039 u8 mlpn_status[0x4]; 10040 u8 local_port[0x8]; 10041 u8 reserved_at_10[0x10]; 10042 10043 u8 e[0x1]; 10044 u8 reserved_at_21[0x1f]; 10045 }; 10046 10047 struct mlx5_ifc_pmlp_reg_bits { 10048 u8 rxtx[0x1]; 10049 u8 reserved_at_1[0x7]; 10050 u8 local_port[0x8]; 10051 u8 reserved_at_10[0x8]; 10052 u8 width[0x8]; 10053 10054 u8 lane0_module_mapping[0x20]; 10055 10056 u8 lane1_module_mapping[0x20]; 10057 10058 u8 lane2_module_mapping[0x20]; 10059 10060 u8 lane3_module_mapping[0x20]; 10061 10062 u8 reserved_at_a0[0x160]; 10063 }; 10064 10065 struct mlx5_ifc_pmaos_reg_bits { 10066 u8 reserved_at_0[0x8]; 10067 u8 module[0x8]; 10068 u8 reserved_at_10[0x4]; 10069 u8 admin_status[0x4]; 10070 u8 reserved_at_18[0x4]; 10071 u8 oper_status[0x4]; 10072 10073 u8 ase[0x1]; 10074 u8 ee[0x1]; 10075 u8 reserved_at_22[0x1c]; 10076 u8 e[0x2]; 10077 10078 u8 reserved_at_40[0x40]; 10079 }; 10080 10081 struct mlx5_ifc_plpc_reg_bits { 10082 u8 reserved_at_0[0x4]; 10083 u8 profile_id[0xc]; 10084 u8 reserved_at_10[0x4]; 10085 u8 proto_mask[0x4]; 10086 u8 reserved_at_18[0x8]; 10087 10088 u8 reserved_at_20[0x10]; 10089 u8 lane_speed[0x10]; 10090 10091 u8 reserved_at_40[0x17]; 10092 u8 lpbf[0x1]; 10093 u8 fec_mode_policy[0x8]; 10094 10095 u8 retransmission_capability[0x8]; 10096 u8 fec_mode_capability[0x18]; 10097 10098 u8 retransmission_support_admin[0x8]; 10099 u8 fec_mode_support_admin[0x18]; 10100 10101 u8 retransmission_request_admin[0x8]; 10102 u8 fec_mode_request_admin[0x18]; 10103 10104 u8 reserved_at_c0[0x80]; 10105 }; 10106 10107 struct mlx5_ifc_plib_reg_bits { 10108 u8 reserved_at_0[0x8]; 10109 u8 local_port[0x8]; 10110 u8 reserved_at_10[0x8]; 10111 u8 ib_port[0x8]; 10112 10113 u8 reserved_at_20[0x60]; 10114 }; 10115 10116 struct mlx5_ifc_plbf_reg_bits { 10117 u8 reserved_at_0[0x8]; 10118 u8 local_port[0x8]; 10119 u8 reserved_at_10[0xd]; 10120 u8 lbf_mode[0x3]; 10121 10122 u8 reserved_at_20[0x20]; 10123 }; 10124 10125 struct mlx5_ifc_pipg_reg_bits { 10126 u8 reserved_at_0[0x8]; 10127 u8 local_port[0x8]; 10128 u8 reserved_at_10[0x10]; 10129 10130 u8 dic[0x1]; 10131 u8 reserved_at_21[0x19]; 10132 u8 ipg[0x4]; 10133 u8 reserved_at_3e[0x2]; 10134 }; 10135 10136 struct mlx5_ifc_pifr_reg_bits { 10137 u8 reserved_at_0[0x8]; 10138 u8 local_port[0x8]; 10139 u8 reserved_at_10[0x10]; 10140 10141 u8 reserved_at_20[0xe0]; 10142 10143 u8 port_filter[8][0x20]; 10144 10145 u8 port_filter_update_en[8][0x20]; 10146 }; 10147 10148 struct mlx5_ifc_pfcc_reg_bits { 10149 u8 reserved_at_0[0x8]; 10150 u8 local_port[0x8]; 10151 u8 reserved_at_10[0xb]; 10152 u8 ppan_mask_n[0x1]; 10153 u8 minor_stall_mask[0x1]; 10154 u8 critical_stall_mask[0x1]; 10155 u8 reserved_at_1e[0x2]; 10156 10157 u8 ppan[0x4]; 10158 u8 reserved_at_24[0x4]; 10159 u8 prio_mask_tx[0x8]; 10160 u8 reserved_at_30[0x8]; 10161 u8 prio_mask_rx[0x8]; 10162 10163 u8 pptx[0x1]; 10164 u8 aptx[0x1]; 10165 u8 pptx_mask_n[0x1]; 10166 u8 reserved_at_43[0x5]; 10167 u8 pfctx[0x8]; 10168 u8 reserved_at_50[0x10]; 10169 10170 u8 pprx[0x1]; 10171 u8 aprx[0x1]; 10172 u8 pprx_mask_n[0x1]; 10173 u8 reserved_at_63[0x5]; 10174 u8 pfcrx[0x8]; 10175 u8 reserved_at_70[0x10]; 10176 10177 u8 device_stall_minor_watermark[0x10]; 10178 u8 device_stall_critical_watermark[0x10]; 10179 10180 u8 reserved_at_a0[0x60]; 10181 }; 10182 10183 struct mlx5_ifc_pelc_reg_bits { 10184 u8 op[0x4]; 10185 u8 reserved_at_4[0x4]; 10186 u8 local_port[0x8]; 10187 u8 reserved_at_10[0x10]; 10188 10189 u8 op_admin[0x8]; 10190 u8 op_capability[0x8]; 10191 u8 op_request[0x8]; 10192 u8 op_active[0x8]; 10193 10194 u8 admin[0x40]; 10195 10196 u8 capability[0x40]; 10197 10198 u8 request[0x40]; 10199 10200 u8 active[0x40]; 10201 10202 u8 reserved_at_140[0x80]; 10203 }; 10204 10205 struct mlx5_ifc_peir_reg_bits { 10206 u8 reserved_at_0[0x8]; 10207 u8 local_port[0x8]; 10208 u8 reserved_at_10[0x10]; 10209 10210 u8 reserved_at_20[0xc]; 10211 u8 error_count[0x4]; 10212 u8 reserved_at_30[0x10]; 10213 10214 u8 reserved_at_40[0xc]; 10215 u8 lane[0x4]; 10216 u8 reserved_at_50[0x8]; 10217 u8 error_type[0x8]; 10218 }; 10219 10220 struct mlx5_ifc_mpegc_reg_bits { 10221 u8 reserved_at_0[0x30]; 10222 u8 field_select[0x10]; 10223 10224 u8 tx_overflow_sense[0x1]; 10225 u8 mark_cqe[0x1]; 10226 u8 mark_cnp[0x1]; 10227 u8 reserved_at_43[0x1b]; 10228 u8 tx_lossy_overflow_oper[0x2]; 10229 10230 u8 reserved_at_60[0x100]; 10231 }; 10232 10233 struct mlx5_ifc_mpir_reg_bits { 10234 u8 sdm[0x1]; 10235 u8 reserved_at_1[0x1b]; 10236 u8 host_buses[0x4]; 10237 10238 u8 reserved_at_20[0x20]; 10239 10240 u8 local_port[0x8]; 10241 u8 reserved_at_28[0x18]; 10242 10243 u8 reserved_at_60[0x20]; 10244 }; 10245 10246 enum { 10247 MLX5_MTUTC_FREQ_ADJ_UNITS_PPB = 0x0, 10248 MLX5_MTUTC_FREQ_ADJ_UNITS_SCALED_PPM = 0x1, 10249 }; 10250 10251 enum { 10252 MLX5_MTUTC_OPERATION_SET_TIME_IMMEDIATE = 0x1, 10253 MLX5_MTUTC_OPERATION_ADJUST_TIME = 0x2, 10254 MLX5_MTUTC_OPERATION_ADJUST_FREQ_UTC = 0x3, 10255 }; 10256 10257 struct mlx5_ifc_mtutc_reg_bits { 10258 u8 reserved_at_0[0x5]; 10259 u8 freq_adj_units[0x3]; 10260 u8 reserved_at_8[0x3]; 10261 u8 log_max_freq_adjustment[0x5]; 10262 10263 u8 reserved_at_10[0xc]; 10264 u8 operation[0x4]; 10265 10266 u8 freq_adjustment[0x20]; 10267 10268 u8 reserved_at_40[0x40]; 10269 10270 u8 utc_sec[0x20]; 10271 10272 u8 reserved_at_a0[0x2]; 10273 u8 utc_nsec[0x1e]; 10274 10275 u8 time_adjustment[0x20]; 10276 }; 10277 10278 struct mlx5_ifc_pcam_enhanced_features_bits { 10279 u8 reserved_at_0[0x48]; 10280 u8 fec_100G_per_lane_in_pplm[0x1]; 10281 u8 reserved_at_49[0x1f]; 10282 u8 fec_50G_per_lane_in_pplm[0x1]; 10283 u8 reserved_at_69[0x4]; 10284 u8 rx_icrc_encapsulated_counter[0x1]; 10285 u8 reserved_at_6e[0x4]; 10286 u8 ptys_extended_ethernet[0x1]; 10287 u8 reserved_at_73[0x3]; 10288 u8 pfcc_mask[0x1]; 10289 u8 reserved_at_77[0x3]; 10290 u8 per_lane_error_counters[0x1]; 10291 u8 rx_buffer_fullness_counters[0x1]; 10292 u8 ptys_connector_type[0x1]; 10293 u8 reserved_at_7d[0x1]; 10294 u8 ppcnt_discard_group[0x1]; 10295 u8 ppcnt_statistical_group[0x1]; 10296 }; 10297 10298 struct mlx5_ifc_pcam_regs_5000_to_507f_bits { 10299 u8 port_access_reg_cap_mask_127_to_96[0x20]; 10300 u8 port_access_reg_cap_mask_95_to_64[0x20]; 10301 10302 u8 port_access_reg_cap_mask_63_to_36[0x1c]; 10303 u8 pplm[0x1]; 10304 u8 port_access_reg_cap_mask_34_to_32[0x3]; 10305 10306 u8 port_access_reg_cap_mask_31_to_13[0x13]; 10307 u8 pbmc[0x1]; 10308 u8 pptb[0x1]; 10309 u8 port_access_reg_cap_mask_10_to_09[0x2]; 10310 u8 ppcnt[0x1]; 10311 u8 port_access_reg_cap_mask_07_to_00[0x8]; 10312 }; 10313 10314 struct mlx5_ifc_pcam_reg_bits { 10315 u8 reserved_at_0[0x8]; 10316 u8 feature_group[0x8]; 10317 u8 reserved_at_10[0x8]; 10318 u8 access_reg_group[0x8]; 10319 10320 u8 reserved_at_20[0x20]; 10321 10322 union { 10323 struct mlx5_ifc_pcam_regs_5000_to_507f_bits regs_5000_to_507f; 10324 u8 reserved_at_0[0x80]; 10325 } port_access_reg_cap_mask; 10326 10327 u8 reserved_at_c0[0x80]; 10328 10329 union { 10330 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features; 10331 u8 reserved_at_0[0x80]; 10332 } feature_cap_mask; 10333 10334 u8 reserved_at_1c0[0xc0]; 10335 }; 10336 10337 struct mlx5_ifc_mcam_enhanced_features_bits { 10338 u8 reserved_at_0[0x50]; 10339 u8 mtutc_freq_adj_units[0x1]; 10340 u8 mtutc_time_adjustment_extended_range[0x1]; 10341 u8 reserved_at_52[0xb]; 10342 u8 mcia_32dwords[0x1]; 10343 u8 out_pulse_duration_ns[0x1]; 10344 u8 npps_period[0x1]; 10345 u8 reserved_at_60[0xa]; 10346 u8 reset_state[0x1]; 10347 u8 ptpcyc2realtime_modify[0x1]; 10348 u8 reserved_at_6c[0x2]; 10349 u8 pci_status_and_power[0x1]; 10350 u8 reserved_at_6f[0x5]; 10351 u8 mark_tx_action_cnp[0x1]; 10352 u8 mark_tx_action_cqe[0x1]; 10353 u8 dynamic_tx_overflow[0x1]; 10354 u8 reserved_at_77[0x4]; 10355 u8 pcie_outbound_stalled[0x1]; 10356 u8 tx_overflow_buffer_pkt[0x1]; 10357 u8 mtpps_enh_out_per_adj[0x1]; 10358 u8 mtpps_fs[0x1]; 10359 u8 pcie_performance_group[0x1]; 10360 }; 10361 10362 struct mlx5_ifc_mcam_access_reg_bits { 10363 u8 reserved_at_0[0x1c]; 10364 u8 mcda[0x1]; 10365 u8 mcc[0x1]; 10366 u8 mcqi[0x1]; 10367 u8 mcqs[0x1]; 10368 10369 u8 regs_95_to_90[0x6]; 10370 u8 mpir[0x1]; 10371 u8 regs_88_to_87[0x2]; 10372 u8 mpegc[0x1]; 10373 u8 mtutc[0x1]; 10374 u8 regs_84_to_68[0x11]; 10375 u8 tracer_registers[0x4]; 10376 10377 u8 regs_63_to_46[0x12]; 10378 u8 mrtc[0x1]; 10379 u8 regs_44_to_41[0x4]; 10380 u8 mfrl[0x1]; 10381 u8 regs_39_to_32[0x8]; 10382 10383 u8 regs_31_to_11[0x15]; 10384 u8 mtmp[0x1]; 10385 u8 regs_9_to_0[0xa]; 10386 }; 10387 10388 struct mlx5_ifc_mcam_access_reg_bits1 { 10389 u8 regs_127_to_96[0x20]; 10390 10391 u8 regs_95_to_64[0x20]; 10392 10393 u8 regs_63_to_32[0x20]; 10394 10395 u8 regs_31_to_0[0x20]; 10396 }; 10397 10398 struct mlx5_ifc_mcam_access_reg_bits2 { 10399 u8 regs_127_to_99[0x1d]; 10400 u8 mirc[0x1]; 10401 u8 regs_97_to_96[0x2]; 10402 10403 u8 regs_95_to_87[0x09]; 10404 u8 synce_registers[0x2]; 10405 u8 regs_84_to_64[0x15]; 10406 10407 u8 regs_63_to_32[0x20]; 10408 10409 u8 regs_31_to_0[0x20]; 10410 }; 10411 10412 struct mlx5_ifc_mcam_reg_bits { 10413 u8 reserved_at_0[0x8]; 10414 u8 feature_group[0x8]; 10415 u8 reserved_at_10[0x8]; 10416 u8 access_reg_group[0x8]; 10417 10418 u8 reserved_at_20[0x20]; 10419 10420 union { 10421 struct mlx5_ifc_mcam_access_reg_bits access_regs; 10422 struct mlx5_ifc_mcam_access_reg_bits1 access_regs1; 10423 struct mlx5_ifc_mcam_access_reg_bits2 access_regs2; 10424 u8 reserved_at_0[0x80]; 10425 } mng_access_reg_cap_mask; 10426 10427 u8 reserved_at_c0[0x80]; 10428 10429 union { 10430 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features; 10431 u8 reserved_at_0[0x80]; 10432 } mng_feature_cap_mask; 10433 10434 u8 reserved_at_1c0[0x80]; 10435 }; 10436 10437 struct mlx5_ifc_qcam_access_reg_cap_mask { 10438 u8 qcam_access_reg_cap_mask_127_to_20[0x6C]; 10439 u8 qpdpm[0x1]; 10440 u8 qcam_access_reg_cap_mask_18_to_4[0x0F]; 10441 u8 qdpm[0x1]; 10442 u8 qpts[0x1]; 10443 u8 qcap[0x1]; 10444 u8 qcam_access_reg_cap_mask_0[0x1]; 10445 }; 10446 10447 struct mlx5_ifc_qcam_qos_feature_cap_mask { 10448 u8 qcam_qos_feature_cap_mask_127_to_1[0x7F]; 10449 u8 qpts_trust_both[0x1]; 10450 }; 10451 10452 struct mlx5_ifc_qcam_reg_bits { 10453 u8 reserved_at_0[0x8]; 10454 u8 feature_group[0x8]; 10455 u8 reserved_at_10[0x8]; 10456 u8 access_reg_group[0x8]; 10457 u8 reserved_at_20[0x20]; 10458 10459 union { 10460 struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap; 10461 u8 reserved_at_0[0x80]; 10462 } qos_access_reg_cap_mask; 10463 10464 u8 reserved_at_c0[0x80]; 10465 10466 union { 10467 struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap; 10468 u8 reserved_at_0[0x80]; 10469 } qos_feature_cap_mask; 10470 10471 u8 reserved_at_1c0[0x80]; 10472 }; 10473 10474 struct mlx5_ifc_core_dump_reg_bits { 10475 u8 reserved_at_0[0x18]; 10476 u8 core_dump_type[0x8]; 10477 10478 u8 reserved_at_20[0x30]; 10479 u8 vhca_id[0x10]; 10480 10481 u8 reserved_at_60[0x8]; 10482 u8 qpn[0x18]; 10483 u8 reserved_at_80[0x180]; 10484 }; 10485 10486 struct mlx5_ifc_pcap_reg_bits { 10487 u8 reserved_at_0[0x8]; 10488 u8 local_port[0x8]; 10489 u8 reserved_at_10[0x10]; 10490 10491 u8 port_capability_mask[4][0x20]; 10492 }; 10493 10494 struct mlx5_ifc_paos_reg_bits { 10495 u8 swid[0x8]; 10496 u8 local_port[0x8]; 10497 u8 reserved_at_10[0x4]; 10498 u8 admin_status[0x4]; 10499 u8 reserved_at_18[0x4]; 10500 u8 oper_status[0x4]; 10501 10502 u8 ase[0x1]; 10503 u8 ee[0x1]; 10504 u8 reserved_at_22[0x1c]; 10505 u8 e[0x2]; 10506 10507 u8 reserved_at_40[0x40]; 10508 }; 10509 10510 struct mlx5_ifc_pamp_reg_bits { 10511 u8 reserved_at_0[0x8]; 10512 u8 opamp_group[0x8]; 10513 u8 reserved_at_10[0xc]; 10514 u8 opamp_group_type[0x4]; 10515 10516 u8 start_index[0x10]; 10517 u8 reserved_at_30[0x4]; 10518 u8 num_of_indices[0xc]; 10519 10520 u8 index_data[18][0x10]; 10521 }; 10522 10523 struct mlx5_ifc_pcmr_reg_bits { 10524 u8 reserved_at_0[0x8]; 10525 u8 local_port[0x8]; 10526 u8 reserved_at_10[0x10]; 10527 10528 u8 entropy_force_cap[0x1]; 10529 u8 entropy_calc_cap[0x1]; 10530 u8 entropy_gre_calc_cap[0x1]; 10531 u8 reserved_at_23[0xf]; 10532 u8 rx_ts_over_crc_cap[0x1]; 10533 u8 reserved_at_33[0xb]; 10534 u8 fcs_cap[0x1]; 10535 u8 reserved_at_3f[0x1]; 10536 10537 u8 entropy_force[0x1]; 10538 u8 entropy_calc[0x1]; 10539 u8 entropy_gre_calc[0x1]; 10540 u8 reserved_at_43[0xf]; 10541 u8 rx_ts_over_crc[0x1]; 10542 u8 reserved_at_53[0xb]; 10543 u8 fcs_chk[0x1]; 10544 u8 reserved_at_5f[0x1]; 10545 }; 10546 10547 struct mlx5_ifc_lane_2_module_mapping_bits { 10548 u8 reserved_at_0[0x4]; 10549 u8 rx_lane[0x4]; 10550 u8 reserved_at_8[0x4]; 10551 u8 tx_lane[0x4]; 10552 u8 reserved_at_10[0x8]; 10553 u8 module[0x8]; 10554 }; 10555 10556 struct mlx5_ifc_bufferx_reg_bits { 10557 u8 reserved_at_0[0x6]; 10558 u8 lossy[0x1]; 10559 u8 epsb[0x1]; 10560 u8 reserved_at_8[0x8]; 10561 u8 size[0x10]; 10562 10563 u8 xoff_threshold[0x10]; 10564 u8 xon_threshold[0x10]; 10565 }; 10566 10567 struct mlx5_ifc_set_node_in_bits { 10568 u8 node_description[64][0x8]; 10569 }; 10570 10571 struct mlx5_ifc_register_power_settings_bits { 10572 u8 reserved_at_0[0x18]; 10573 u8 power_settings_level[0x8]; 10574 10575 u8 reserved_at_20[0x60]; 10576 }; 10577 10578 struct mlx5_ifc_register_host_endianness_bits { 10579 u8 he[0x1]; 10580 u8 reserved_at_1[0x1f]; 10581 10582 u8 reserved_at_20[0x60]; 10583 }; 10584 10585 struct mlx5_ifc_umr_pointer_desc_argument_bits { 10586 u8 reserved_at_0[0x20]; 10587 10588 u8 mkey[0x20]; 10589 10590 u8 addressh_63_32[0x20]; 10591 10592 u8 addressl_31_0[0x20]; 10593 }; 10594 10595 struct mlx5_ifc_ud_adrs_vector_bits { 10596 u8 dc_key[0x40]; 10597 10598 u8 ext[0x1]; 10599 u8 reserved_at_41[0x7]; 10600 u8 destination_qp_dct[0x18]; 10601 10602 u8 static_rate[0x4]; 10603 u8 sl_eth_prio[0x4]; 10604 u8 fl[0x1]; 10605 u8 mlid[0x7]; 10606 u8 rlid_udp_sport[0x10]; 10607 10608 u8 reserved_at_80[0x20]; 10609 10610 u8 rmac_47_16[0x20]; 10611 10612 u8 rmac_15_0[0x10]; 10613 u8 tclass[0x8]; 10614 u8 hop_limit[0x8]; 10615 10616 u8 reserved_at_e0[0x1]; 10617 u8 grh[0x1]; 10618 u8 reserved_at_e2[0x2]; 10619 u8 src_addr_index[0x8]; 10620 u8 flow_label[0x14]; 10621 10622 u8 rgid_rip[16][0x8]; 10623 }; 10624 10625 struct mlx5_ifc_pages_req_event_bits { 10626 u8 reserved_at_0[0x10]; 10627 u8 function_id[0x10]; 10628 10629 u8 num_pages[0x20]; 10630 10631 u8 reserved_at_40[0xa0]; 10632 }; 10633 10634 struct mlx5_ifc_eqe_bits { 10635 u8 reserved_at_0[0x8]; 10636 u8 event_type[0x8]; 10637 u8 reserved_at_10[0x8]; 10638 u8 event_sub_type[0x8]; 10639 10640 u8 reserved_at_20[0xe0]; 10641 10642 union mlx5_ifc_event_auto_bits event_data; 10643 10644 u8 reserved_at_1e0[0x10]; 10645 u8 signature[0x8]; 10646 u8 reserved_at_1f8[0x7]; 10647 u8 owner[0x1]; 10648 }; 10649 10650 enum { 10651 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7, 10652 }; 10653 10654 struct mlx5_ifc_cmd_queue_entry_bits { 10655 u8 type[0x8]; 10656 u8 reserved_at_8[0x18]; 10657 10658 u8 input_length[0x20]; 10659 10660 u8 input_mailbox_pointer_63_32[0x20]; 10661 10662 u8 input_mailbox_pointer_31_9[0x17]; 10663 u8 reserved_at_77[0x9]; 10664 10665 u8 command_input_inline_data[16][0x8]; 10666 10667 u8 command_output_inline_data[16][0x8]; 10668 10669 u8 output_mailbox_pointer_63_32[0x20]; 10670 10671 u8 output_mailbox_pointer_31_9[0x17]; 10672 u8 reserved_at_1b7[0x9]; 10673 10674 u8 output_length[0x20]; 10675 10676 u8 token[0x8]; 10677 u8 signature[0x8]; 10678 u8 reserved_at_1f0[0x8]; 10679 u8 status[0x7]; 10680 u8 ownership[0x1]; 10681 }; 10682 10683 struct mlx5_ifc_cmd_out_bits { 10684 u8 status[0x8]; 10685 u8 reserved_at_8[0x18]; 10686 10687 u8 syndrome[0x20]; 10688 10689 u8 command_output[0x20]; 10690 }; 10691 10692 struct mlx5_ifc_cmd_in_bits { 10693 u8 opcode[0x10]; 10694 u8 reserved_at_10[0x10]; 10695 10696 u8 reserved_at_20[0x10]; 10697 u8 op_mod[0x10]; 10698 10699 u8 command[][0x20]; 10700 }; 10701 10702 struct mlx5_ifc_cmd_if_box_bits { 10703 u8 mailbox_data[512][0x8]; 10704 10705 u8 reserved_at_1000[0x180]; 10706 10707 u8 next_pointer_63_32[0x20]; 10708 10709 u8 next_pointer_31_10[0x16]; 10710 u8 reserved_at_11b6[0xa]; 10711 10712 u8 block_number[0x20]; 10713 10714 u8 reserved_at_11e0[0x8]; 10715 u8 token[0x8]; 10716 u8 ctrl_signature[0x8]; 10717 u8 signature[0x8]; 10718 }; 10719 10720 struct mlx5_ifc_mtt_bits { 10721 u8 ptag_63_32[0x20]; 10722 10723 u8 ptag_31_8[0x18]; 10724 u8 reserved_at_38[0x6]; 10725 u8 wr_en[0x1]; 10726 u8 rd_en[0x1]; 10727 }; 10728 10729 struct mlx5_ifc_query_wol_rol_out_bits { 10730 u8 status[0x8]; 10731 u8 reserved_at_8[0x18]; 10732 10733 u8 syndrome[0x20]; 10734 10735 u8 reserved_at_40[0x10]; 10736 u8 rol_mode[0x8]; 10737 u8 wol_mode[0x8]; 10738 10739 u8 reserved_at_60[0x20]; 10740 }; 10741 10742 struct mlx5_ifc_query_wol_rol_in_bits { 10743 u8 opcode[0x10]; 10744 u8 reserved_at_10[0x10]; 10745 10746 u8 reserved_at_20[0x10]; 10747 u8 op_mod[0x10]; 10748 10749 u8 reserved_at_40[0x40]; 10750 }; 10751 10752 struct mlx5_ifc_set_wol_rol_out_bits { 10753 u8 status[0x8]; 10754 u8 reserved_at_8[0x18]; 10755 10756 u8 syndrome[0x20]; 10757 10758 u8 reserved_at_40[0x40]; 10759 }; 10760 10761 struct mlx5_ifc_set_wol_rol_in_bits { 10762 u8 opcode[0x10]; 10763 u8 reserved_at_10[0x10]; 10764 10765 u8 reserved_at_20[0x10]; 10766 u8 op_mod[0x10]; 10767 10768 u8 rol_mode_valid[0x1]; 10769 u8 wol_mode_valid[0x1]; 10770 u8 reserved_at_42[0xe]; 10771 u8 rol_mode[0x8]; 10772 u8 wol_mode[0x8]; 10773 10774 u8 reserved_at_60[0x20]; 10775 }; 10776 10777 enum { 10778 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0, 10779 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1, 10780 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2, 10781 MLX5_INITIAL_SEG_NIC_INTERFACE_SW_RESET = 0x7, 10782 }; 10783 10784 enum { 10785 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0, 10786 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1, 10787 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2, 10788 }; 10789 10790 enum { 10791 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR = 0x1, 10792 MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC = 0x7, 10793 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR = 0x8, 10794 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR = 0x9, 10795 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR = 0xa, 10796 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR = 0xb, 10797 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN = 0xc, 10798 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR = 0xd, 10799 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV = 0xe, 10800 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR = 0xf, 10801 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR = 0x10, 10802 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PCI_POISONED_ERR = 0x12, 10803 }; 10804 10805 struct mlx5_ifc_initial_seg_bits { 10806 u8 fw_rev_minor[0x10]; 10807 u8 fw_rev_major[0x10]; 10808 10809 u8 cmd_interface_rev[0x10]; 10810 u8 fw_rev_subminor[0x10]; 10811 10812 u8 reserved_at_40[0x40]; 10813 10814 u8 cmdq_phy_addr_63_32[0x20]; 10815 10816 u8 cmdq_phy_addr_31_12[0x14]; 10817 u8 reserved_at_b4[0x2]; 10818 u8 nic_interface[0x2]; 10819 u8 log_cmdq_size[0x4]; 10820 u8 log_cmdq_stride[0x4]; 10821 10822 u8 command_doorbell_vector[0x20]; 10823 10824 u8 reserved_at_e0[0xf00]; 10825 10826 u8 initializing[0x1]; 10827 u8 reserved_at_fe1[0x4]; 10828 u8 nic_interface_supported[0x3]; 10829 u8 embedded_cpu[0x1]; 10830 u8 reserved_at_fe9[0x17]; 10831 10832 struct mlx5_ifc_health_buffer_bits health_buffer; 10833 10834 u8 no_dram_nic_offset[0x20]; 10835 10836 u8 reserved_at_1220[0x6e40]; 10837 10838 u8 reserved_at_8060[0x1f]; 10839 u8 clear_int[0x1]; 10840 10841 u8 health_syndrome[0x8]; 10842 u8 health_counter[0x18]; 10843 10844 u8 reserved_at_80a0[0x17fc0]; 10845 }; 10846 10847 struct mlx5_ifc_mtpps_reg_bits { 10848 u8 reserved_at_0[0xc]; 10849 u8 cap_number_of_pps_pins[0x4]; 10850 u8 reserved_at_10[0x4]; 10851 u8 cap_max_num_of_pps_in_pins[0x4]; 10852 u8 reserved_at_18[0x4]; 10853 u8 cap_max_num_of_pps_out_pins[0x4]; 10854 10855 u8 reserved_at_20[0x13]; 10856 u8 cap_log_min_npps_period[0x5]; 10857 u8 reserved_at_38[0x3]; 10858 u8 cap_log_min_out_pulse_duration_ns[0x5]; 10859 10860 u8 reserved_at_40[0x4]; 10861 u8 cap_pin_3_mode[0x4]; 10862 u8 reserved_at_48[0x4]; 10863 u8 cap_pin_2_mode[0x4]; 10864 u8 reserved_at_50[0x4]; 10865 u8 cap_pin_1_mode[0x4]; 10866 u8 reserved_at_58[0x4]; 10867 u8 cap_pin_0_mode[0x4]; 10868 10869 u8 reserved_at_60[0x4]; 10870 u8 cap_pin_7_mode[0x4]; 10871 u8 reserved_at_68[0x4]; 10872 u8 cap_pin_6_mode[0x4]; 10873 u8 reserved_at_70[0x4]; 10874 u8 cap_pin_5_mode[0x4]; 10875 u8 reserved_at_78[0x4]; 10876 u8 cap_pin_4_mode[0x4]; 10877 10878 u8 field_select[0x20]; 10879 u8 reserved_at_a0[0x20]; 10880 10881 u8 npps_period[0x40]; 10882 10883 u8 enable[0x1]; 10884 u8 reserved_at_101[0xb]; 10885 u8 pattern[0x4]; 10886 u8 reserved_at_110[0x4]; 10887 u8 pin_mode[0x4]; 10888 u8 pin[0x8]; 10889 10890 u8 reserved_at_120[0x2]; 10891 u8 out_pulse_duration_ns[0x1e]; 10892 10893 u8 time_stamp[0x40]; 10894 10895 u8 out_pulse_duration[0x10]; 10896 u8 out_periodic_adjustment[0x10]; 10897 u8 enhanced_out_periodic_adjustment[0x20]; 10898 10899 u8 reserved_at_1c0[0x20]; 10900 }; 10901 10902 struct mlx5_ifc_mtppse_reg_bits { 10903 u8 reserved_at_0[0x18]; 10904 u8 pin[0x8]; 10905 u8 event_arm[0x1]; 10906 u8 reserved_at_21[0x1b]; 10907 u8 event_generation_mode[0x4]; 10908 u8 reserved_at_40[0x40]; 10909 }; 10910 10911 struct mlx5_ifc_mcqs_reg_bits { 10912 u8 last_index_flag[0x1]; 10913 u8 reserved_at_1[0x7]; 10914 u8 fw_device[0x8]; 10915 u8 component_index[0x10]; 10916 10917 u8 reserved_at_20[0x10]; 10918 u8 identifier[0x10]; 10919 10920 u8 reserved_at_40[0x17]; 10921 u8 component_status[0x5]; 10922 u8 component_update_state[0x4]; 10923 10924 u8 last_update_state_changer_type[0x4]; 10925 u8 last_update_state_changer_host_id[0x4]; 10926 u8 reserved_at_68[0x18]; 10927 }; 10928 10929 struct mlx5_ifc_mcqi_cap_bits { 10930 u8 supported_info_bitmask[0x20]; 10931 10932 u8 component_size[0x20]; 10933 10934 u8 max_component_size[0x20]; 10935 10936 u8 log_mcda_word_size[0x4]; 10937 u8 reserved_at_64[0xc]; 10938 u8 mcda_max_write_size[0x10]; 10939 10940 u8 rd_en[0x1]; 10941 u8 reserved_at_81[0x1]; 10942 u8 match_chip_id[0x1]; 10943 u8 match_psid[0x1]; 10944 u8 check_user_timestamp[0x1]; 10945 u8 match_base_guid_mac[0x1]; 10946 u8 reserved_at_86[0x1a]; 10947 }; 10948 10949 struct mlx5_ifc_mcqi_version_bits { 10950 u8 reserved_at_0[0x2]; 10951 u8 build_time_valid[0x1]; 10952 u8 user_defined_time_valid[0x1]; 10953 u8 reserved_at_4[0x14]; 10954 u8 version_string_length[0x8]; 10955 10956 u8 version[0x20]; 10957 10958 u8 build_time[0x40]; 10959 10960 u8 user_defined_time[0x40]; 10961 10962 u8 build_tool_version[0x20]; 10963 10964 u8 reserved_at_e0[0x20]; 10965 10966 u8 version_string[92][0x8]; 10967 }; 10968 10969 struct mlx5_ifc_mcqi_activation_method_bits { 10970 u8 pending_server_ac_power_cycle[0x1]; 10971 u8 pending_server_dc_power_cycle[0x1]; 10972 u8 pending_server_reboot[0x1]; 10973 u8 pending_fw_reset[0x1]; 10974 u8 auto_activate[0x1]; 10975 u8 all_hosts_sync[0x1]; 10976 u8 device_hw_reset[0x1]; 10977 u8 reserved_at_7[0x19]; 10978 }; 10979 10980 union mlx5_ifc_mcqi_reg_data_bits { 10981 struct mlx5_ifc_mcqi_cap_bits mcqi_caps; 10982 struct mlx5_ifc_mcqi_version_bits mcqi_version; 10983 struct mlx5_ifc_mcqi_activation_method_bits mcqi_activation_mathod; 10984 }; 10985 10986 struct mlx5_ifc_mcqi_reg_bits { 10987 u8 read_pending_component[0x1]; 10988 u8 reserved_at_1[0xf]; 10989 u8 component_index[0x10]; 10990 10991 u8 reserved_at_20[0x20]; 10992 10993 u8 reserved_at_40[0x1b]; 10994 u8 info_type[0x5]; 10995 10996 u8 info_size[0x20]; 10997 10998 u8 offset[0x20]; 10999 11000 u8 reserved_at_a0[0x10]; 11001 u8 data_size[0x10]; 11002 11003 union mlx5_ifc_mcqi_reg_data_bits data[]; 11004 }; 11005 11006 struct mlx5_ifc_mcc_reg_bits { 11007 u8 reserved_at_0[0x4]; 11008 u8 time_elapsed_since_last_cmd[0xc]; 11009 u8 reserved_at_10[0x8]; 11010 u8 instruction[0x8]; 11011 11012 u8 reserved_at_20[0x10]; 11013 u8 component_index[0x10]; 11014 11015 u8 reserved_at_40[0x8]; 11016 u8 update_handle[0x18]; 11017 11018 u8 handle_owner_type[0x4]; 11019 u8 handle_owner_host_id[0x4]; 11020 u8 reserved_at_68[0x1]; 11021 u8 control_progress[0x7]; 11022 u8 error_code[0x8]; 11023 u8 reserved_at_78[0x4]; 11024 u8 control_state[0x4]; 11025 11026 u8 component_size[0x20]; 11027 11028 u8 reserved_at_a0[0x60]; 11029 }; 11030 11031 struct mlx5_ifc_mcda_reg_bits { 11032 u8 reserved_at_0[0x8]; 11033 u8 update_handle[0x18]; 11034 11035 u8 offset[0x20]; 11036 11037 u8 reserved_at_40[0x10]; 11038 u8 size[0x10]; 11039 11040 u8 reserved_at_60[0x20]; 11041 11042 u8 data[][0x20]; 11043 }; 11044 11045 enum { 11046 MLX5_MFRL_REG_RESET_STATE_IDLE = 0, 11047 MLX5_MFRL_REG_RESET_STATE_IN_NEGOTIATION = 1, 11048 MLX5_MFRL_REG_RESET_STATE_RESET_IN_PROGRESS = 2, 11049 MLX5_MFRL_REG_RESET_STATE_NEG_TIMEOUT = 3, 11050 MLX5_MFRL_REG_RESET_STATE_NACK = 4, 11051 MLX5_MFRL_REG_RESET_STATE_UNLOAD_TIMEOUT = 5, 11052 }; 11053 11054 enum { 11055 MLX5_MFRL_REG_RESET_TYPE_FULL_CHIP = BIT(0), 11056 MLX5_MFRL_REG_RESET_TYPE_NET_PORT_ALIVE = BIT(1), 11057 }; 11058 11059 enum { 11060 MLX5_MFRL_REG_RESET_LEVEL0 = BIT(0), 11061 MLX5_MFRL_REG_RESET_LEVEL3 = BIT(3), 11062 MLX5_MFRL_REG_RESET_LEVEL6 = BIT(6), 11063 }; 11064 11065 struct mlx5_ifc_mfrl_reg_bits { 11066 u8 reserved_at_0[0x20]; 11067 11068 u8 reserved_at_20[0x2]; 11069 u8 pci_sync_for_fw_update_start[0x1]; 11070 u8 pci_sync_for_fw_update_resp[0x2]; 11071 u8 rst_type_sel[0x3]; 11072 u8 reserved_at_28[0x4]; 11073 u8 reset_state[0x4]; 11074 u8 reset_type[0x8]; 11075 u8 reset_level[0x8]; 11076 }; 11077 11078 struct mlx5_ifc_mirc_reg_bits { 11079 u8 reserved_at_0[0x18]; 11080 u8 status_code[0x8]; 11081 11082 u8 reserved_at_20[0x20]; 11083 }; 11084 11085 struct mlx5_ifc_pddr_monitor_opcode_bits { 11086 u8 reserved_at_0[0x10]; 11087 u8 monitor_opcode[0x10]; 11088 }; 11089 11090 union mlx5_ifc_pddr_troubleshooting_page_status_opcode_auto_bits { 11091 struct mlx5_ifc_pddr_monitor_opcode_bits pddr_monitor_opcode; 11092 u8 reserved_at_0[0x20]; 11093 }; 11094 11095 enum { 11096 /* Monitor opcodes */ 11097 MLX5_PDDR_REG_TRBLSH_GROUP_OPCODE_MONITOR = 0x0, 11098 }; 11099 11100 struct mlx5_ifc_pddr_troubleshooting_page_bits { 11101 u8 reserved_at_0[0x10]; 11102 u8 group_opcode[0x10]; 11103 11104 union mlx5_ifc_pddr_troubleshooting_page_status_opcode_auto_bits status_opcode; 11105 11106 u8 reserved_at_40[0x20]; 11107 11108 u8 status_message[59][0x20]; 11109 }; 11110 11111 union mlx5_ifc_pddr_reg_page_data_auto_bits { 11112 struct mlx5_ifc_pddr_troubleshooting_page_bits pddr_troubleshooting_page; 11113 u8 reserved_at_0[0x7c0]; 11114 }; 11115 11116 enum { 11117 MLX5_PDDR_REG_PAGE_SELECT_TROUBLESHOOTING_INFO_PAGE = 0x1, 11118 }; 11119 11120 struct mlx5_ifc_pddr_reg_bits { 11121 u8 reserved_at_0[0x8]; 11122 u8 local_port[0x8]; 11123 u8 pnat[0x2]; 11124 u8 reserved_at_12[0xe]; 11125 11126 u8 reserved_at_20[0x18]; 11127 u8 page_select[0x8]; 11128 11129 union mlx5_ifc_pddr_reg_page_data_auto_bits page_data; 11130 }; 11131 11132 struct mlx5_ifc_mrtc_reg_bits { 11133 u8 time_synced[0x1]; 11134 u8 reserved_at_1[0x1f]; 11135 11136 u8 reserved_at_20[0x20]; 11137 11138 u8 time_h[0x20]; 11139 11140 u8 time_l[0x20]; 11141 }; 11142 11143 struct mlx5_ifc_mtcap_reg_bits { 11144 u8 reserved_at_0[0x19]; 11145 u8 sensor_count[0x7]; 11146 11147 u8 reserved_at_20[0x20]; 11148 11149 u8 sensor_map[0x40]; 11150 }; 11151 11152 struct mlx5_ifc_mtmp_reg_bits { 11153 u8 reserved_at_0[0x14]; 11154 u8 sensor_index[0xc]; 11155 11156 u8 reserved_at_20[0x10]; 11157 u8 temperature[0x10]; 11158 11159 u8 mte[0x1]; 11160 u8 mtr[0x1]; 11161 u8 reserved_at_42[0xe]; 11162 u8 max_temperature[0x10]; 11163 11164 u8 tee[0x2]; 11165 u8 reserved_at_62[0xe]; 11166 u8 temp_threshold_hi[0x10]; 11167 11168 u8 reserved_at_80[0x10]; 11169 u8 temp_threshold_lo[0x10]; 11170 11171 u8 reserved_at_a0[0x20]; 11172 11173 u8 sensor_name_hi[0x20]; 11174 u8 sensor_name_lo[0x20]; 11175 }; 11176 11177 union mlx5_ifc_ports_control_registers_document_bits { 11178 struct mlx5_ifc_bufferx_reg_bits bufferx_reg; 11179 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 11180 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 11181 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 11182 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 11183 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 11184 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 11185 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout; 11186 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout; 11187 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping; 11188 struct mlx5_ifc_pamp_reg_bits pamp_reg; 11189 struct mlx5_ifc_paos_reg_bits paos_reg; 11190 struct mlx5_ifc_pcap_reg_bits pcap_reg; 11191 struct mlx5_ifc_pddr_monitor_opcode_bits pddr_monitor_opcode; 11192 struct mlx5_ifc_pddr_reg_bits pddr_reg; 11193 struct mlx5_ifc_pddr_troubleshooting_page_bits pddr_troubleshooting_page; 11194 struct mlx5_ifc_peir_reg_bits peir_reg; 11195 struct mlx5_ifc_pelc_reg_bits pelc_reg; 11196 struct mlx5_ifc_pfcc_reg_bits pfcc_reg; 11197 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 11198 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 11199 struct mlx5_ifc_pifr_reg_bits pifr_reg; 11200 struct mlx5_ifc_pipg_reg_bits pipg_reg; 11201 struct mlx5_ifc_plbf_reg_bits plbf_reg; 11202 struct mlx5_ifc_plib_reg_bits plib_reg; 11203 struct mlx5_ifc_plpc_reg_bits plpc_reg; 11204 struct mlx5_ifc_pmaos_reg_bits pmaos_reg; 11205 struct mlx5_ifc_pmlp_reg_bits pmlp_reg; 11206 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg; 11207 struct mlx5_ifc_pmpc_reg_bits pmpc_reg; 11208 struct mlx5_ifc_pmpe_reg_bits pmpe_reg; 11209 struct mlx5_ifc_pmpr_reg_bits pmpr_reg; 11210 struct mlx5_ifc_pmtu_reg_bits pmtu_reg; 11211 struct mlx5_ifc_ppad_reg_bits ppad_reg; 11212 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg; 11213 struct mlx5_ifc_mpein_reg_bits mpein_reg; 11214 struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg; 11215 struct mlx5_ifc_pplm_reg_bits pplm_reg; 11216 struct mlx5_ifc_pplr_reg_bits pplr_reg; 11217 struct mlx5_ifc_ppsc_reg_bits ppsc_reg; 11218 struct mlx5_ifc_pqdr_reg_bits pqdr_reg; 11219 struct mlx5_ifc_pspa_reg_bits pspa_reg; 11220 struct mlx5_ifc_ptas_reg_bits ptas_reg; 11221 struct mlx5_ifc_ptys_reg_bits ptys_reg; 11222 struct mlx5_ifc_mlcr_reg_bits mlcr_reg; 11223 struct mlx5_ifc_pude_reg_bits pude_reg; 11224 struct mlx5_ifc_pvlc_reg_bits pvlc_reg; 11225 struct mlx5_ifc_slrg_reg_bits slrg_reg; 11226 struct mlx5_ifc_sltp_reg_bits sltp_reg; 11227 struct mlx5_ifc_mtpps_reg_bits mtpps_reg; 11228 struct mlx5_ifc_mtppse_reg_bits mtppse_reg; 11229 struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg; 11230 struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits; 11231 struct mlx5_ifc_fpga_cap_bits fpga_cap_bits; 11232 struct mlx5_ifc_mcqi_reg_bits mcqi_reg; 11233 struct mlx5_ifc_mcc_reg_bits mcc_reg; 11234 struct mlx5_ifc_mcda_reg_bits mcda_reg; 11235 struct mlx5_ifc_mirc_reg_bits mirc_reg; 11236 struct mlx5_ifc_mfrl_reg_bits mfrl_reg; 11237 struct mlx5_ifc_mtutc_reg_bits mtutc_reg; 11238 struct mlx5_ifc_mrtc_reg_bits mrtc_reg; 11239 struct mlx5_ifc_mtcap_reg_bits mtcap_reg; 11240 struct mlx5_ifc_mtmp_reg_bits mtmp_reg; 11241 u8 reserved_at_0[0x60e0]; 11242 }; 11243 11244 union mlx5_ifc_debug_enhancements_document_bits { 11245 struct mlx5_ifc_health_buffer_bits health_buffer; 11246 u8 reserved_at_0[0x200]; 11247 }; 11248 11249 union mlx5_ifc_uplink_pci_interface_document_bits { 11250 struct mlx5_ifc_initial_seg_bits initial_seg; 11251 u8 reserved_at_0[0x20060]; 11252 }; 11253 11254 struct mlx5_ifc_set_flow_table_root_out_bits { 11255 u8 status[0x8]; 11256 u8 reserved_at_8[0x18]; 11257 11258 u8 syndrome[0x20]; 11259 11260 u8 reserved_at_40[0x40]; 11261 }; 11262 11263 struct mlx5_ifc_set_flow_table_root_in_bits { 11264 u8 opcode[0x10]; 11265 u8 reserved_at_10[0x10]; 11266 11267 u8 reserved_at_20[0x10]; 11268 u8 op_mod[0x10]; 11269 11270 u8 other_vport[0x1]; 11271 u8 reserved_at_41[0xf]; 11272 u8 vport_number[0x10]; 11273 11274 u8 reserved_at_60[0x20]; 11275 11276 u8 table_type[0x8]; 11277 u8 reserved_at_88[0x7]; 11278 u8 table_of_other_vport[0x1]; 11279 u8 table_vport_number[0x10]; 11280 11281 u8 reserved_at_a0[0x8]; 11282 u8 table_id[0x18]; 11283 11284 u8 reserved_at_c0[0x8]; 11285 u8 underlay_qpn[0x18]; 11286 u8 table_eswitch_owner_vhca_id_valid[0x1]; 11287 u8 reserved_at_e1[0xf]; 11288 u8 table_eswitch_owner_vhca_id[0x10]; 11289 u8 reserved_at_100[0x100]; 11290 }; 11291 11292 enum { 11293 MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = (1UL << 0), 11294 MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15), 11295 }; 11296 11297 struct mlx5_ifc_modify_flow_table_out_bits { 11298 u8 status[0x8]; 11299 u8 reserved_at_8[0x18]; 11300 11301 u8 syndrome[0x20]; 11302 11303 u8 reserved_at_40[0x40]; 11304 }; 11305 11306 struct mlx5_ifc_modify_flow_table_in_bits { 11307 u8 opcode[0x10]; 11308 u8 reserved_at_10[0x10]; 11309 11310 u8 reserved_at_20[0x10]; 11311 u8 op_mod[0x10]; 11312 11313 u8 other_vport[0x1]; 11314 u8 reserved_at_41[0xf]; 11315 u8 vport_number[0x10]; 11316 11317 u8 reserved_at_60[0x10]; 11318 u8 modify_field_select[0x10]; 11319 11320 u8 table_type[0x8]; 11321 u8 reserved_at_88[0x18]; 11322 11323 u8 reserved_at_a0[0x8]; 11324 u8 table_id[0x18]; 11325 11326 struct mlx5_ifc_flow_table_context_bits flow_table_context; 11327 }; 11328 11329 struct mlx5_ifc_ets_tcn_config_reg_bits { 11330 u8 g[0x1]; 11331 u8 b[0x1]; 11332 u8 r[0x1]; 11333 u8 reserved_at_3[0x9]; 11334 u8 group[0x4]; 11335 u8 reserved_at_10[0x9]; 11336 u8 bw_allocation[0x7]; 11337 11338 u8 reserved_at_20[0xc]; 11339 u8 max_bw_units[0x4]; 11340 u8 reserved_at_30[0x8]; 11341 u8 max_bw_value[0x8]; 11342 }; 11343 11344 struct mlx5_ifc_ets_global_config_reg_bits { 11345 u8 reserved_at_0[0x2]; 11346 u8 r[0x1]; 11347 u8 reserved_at_3[0x1d]; 11348 11349 u8 reserved_at_20[0xc]; 11350 u8 max_bw_units[0x4]; 11351 u8 reserved_at_30[0x8]; 11352 u8 max_bw_value[0x8]; 11353 }; 11354 11355 struct mlx5_ifc_qetc_reg_bits { 11356 u8 reserved_at_0[0x8]; 11357 u8 port_number[0x8]; 11358 u8 reserved_at_10[0x30]; 11359 11360 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8]; 11361 struct mlx5_ifc_ets_global_config_reg_bits global_configuration; 11362 }; 11363 11364 struct mlx5_ifc_qpdpm_dscp_reg_bits { 11365 u8 e[0x1]; 11366 u8 reserved_at_01[0x0b]; 11367 u8 prio[0x04]; 11368 }; 11369 11370 struct mlx5_ifc_qpdpm_reg_bits { 11371 u8 reserved_at_0[0x8]; 11372 u8 local_port[0x8]; 11373 u8 reserved_at_10[0x10]; 11374 struct mlx5_ifc_qpdpm_dscp_reg_bits dscp[64]; 11375 }; 11376 11377 struct mlx5_ifc_qpts_reg_bits { 11378 u8 reserved_at_0[0x8]; 11379 u8 local_port[0x8]; 11380 u8 reserved_at_10[0x2d]; 11381 u8 trust_state[0x3]; 11382 }; 11383 11384 struct mlx5_ifc_pptb_reg_bits { 11385 u8 reserved_at_0[0x2]; 11386 u8 mm[0x2]; 11387 u8 reserved_at_4[0x4]; 11388 u8 local_port[0x8]; 11389 u8 reserved_at_10[0x6]; 11390 u8 cm[0x1]; 11391 u8 um[0x1]; 11392 u8 pm[0x8]; 11393 11394 u8 prio_x_buff[0x20]; 11395 11396 u8 pm_msb[0x8]; 11397 u8 reserved_at_48[0x10]; 11398 u8 ctrl_buff[0x4]; 11399 u8 untagged_buff[0x4]; 11400 }; 11401 11402 struct mlx5_ifc_sbcam_reg_bits { 11403 u8 reserved_at_0[0x8]; 11404 u8 feature_group[0x8]; 11405 u8 reserved_at_10[0x8]; 11406 u8 access_reg_group[0x8]; 11407 11408 u8 reserved_at_20[0x20]; 11409 11410 u8 sb_access_reg_cap_mask[4][0x20]; 11411 11412 u8 reserved_at_c0[0x80]; 11413 11414 u8 sb_feature_cap_mask[4][0x20]; 11415 11416 u8 reserved_at_1c0[0x40]; 11417 11418 u8 cap_total_buffer_size[0x20]; 11419 11420 u8 cap_cell_size[0x10]; 11421 u8 cap_max_pg_buffers[0x8]; 11422 u8 cap_num_pool_supported[0x8]; 11423 11424 u8 reserved_at_240[0x8]; 11425 u8 cap_sbsr_stat_size[0x8]; 11426 u8 cap_max_tclass_data[0x8]; 11427 u8 cap_max_cpu_ingress_tclass_sb[0x8]; 11428 }; 11429 11430 struct mlx5_ifc_pbmc_reg_bits { 11431 u8 reserved_at_0[0x8]; 11432 u8 local_port[0x8]; 11433 u8 reserved_at_10[0x10]; 11434 11435 u8 xoff_timer_value[0x10]; 11436 u8 xoff_refresh[0x10]; 11437 11438 u8 reserved_at_40[0x9]; 11439 u8 fullness_threshold[0x7]; 11440 u8 port_buffer_size[0x10]; 11441 11442 struct mlx5_ifc_bufferx_reg_bits buffer[10]; 11443 11444 u8 reserved_at_2e0[0x80]; 11445 }; 11446 11447 struct mlx5_ifc_sbpr_reg_bits { 11448 u8 desc[0x1]; 11449 u8 snap[0x1]; 11450 u8 reserved_at_2[0x4]; 11451 u8 dir[0x2]; 11452 u8 reserved_at_8[0x14]; 11453 u8 pool[0x4]; 11454 11455 u8 infi_size[0x1]; 11456 u8 reserved_at_21[0x7]; 11457 u8 size[0x18]; 11458 11459 u8 reserved_at_40[0x1c]; 11460 u8 mode[0x4]; 11461 11462 u8 reserved_at_60[0x8]; 11463 u8 buff_occupancy[0x18]; 11464 11465 u8 clr[0x1]; 11466 u8 reserved_at_81[0x7]; 11467 u8 max_buff_occupancy[0x18]; 11468 11469 u8 reserved_at_a0[0x8]; 11470 u8 ext_buff_occupancy[0x18]; 11471 }; 11472 11473 struct mlx5_ifc_sbcm_reg_bits { 11474 u8 desc[0x1]; 11475 u8 snap[0x1]; 11476 u8 reserved_at_2[0x6]; 11477 u8 local_port[0x8]; 11478 u8 pnat[0x2]; 11479 u8 pg_buff[0x6]; 11480 u8 reserved_at_18[0x6]; 11481 u8 dir[0x2]; 11482 11483 u8 reserved_at_20[0x1f]; 11484 u8 exc[0x1]; 11485 11486 u8 reserved_at_40[0x40]; 11487 11488 u8 reserved_at_80[0x8]; 11489 u8 buff_occupancy[0x18]; 11490 11491 u8 clr[0x1]; 11492 u8 reserved_at_a1[0x7]; 11493 u8 max_buff_occupancy[0x18]; 11494 11495 u8 reserved_at_c0[0x8]; 11496 u8 min_buff[0x18]; 11497 11498 u8 infi_max[0x1]; 11499 u8 reserved_at_e1[0x7]; 11500 u8 max_buff[0x18]; 11501 11502 u8 reserved_at_100[0x20]; 11503 11504 u8 reserved_at_120[0x1c]; 11505 u8 pool[0x4]; 11506 }; 11507 11508 struct mlx5_ifc_qtct_reg_bits { 11509 u8 reserved_at_0[0x8]; 11510 u8 port_number[0x8]; 11511 u8 reserved_at_10[0xd]; 11512 u8 prio[0x3]; 11513 11514 u8 reserved_at_20[0x1d]; 11515 u8 tclass[0x3]; 11516 }; 11517 11518 struct mlx5_ifc_mcia_reg_bits { 11519 u8 l[0x1]; 11520 u8 reserved_at_1[0x7]; 11521 u8 module[0x8]; 11522 u8 reserved_at_10[0x8]; 11523 u8 status[0x8]; 11524 11525 u8 i2c_device_address[0x8]; 11526 u8 page_number[0x8]; 11527 u8 device_address[0x10]; 11528 11529 u8 reserved_at_40[0x10]; 11530 u8 size[0x10]; 11531 11532 u8 reserved_at_60[0x20]; 11533 11534 u8 dword_0[0x20]; 11535 u8 dword_1[0x20]; 11536 u8 dword_2[0x20]; 11537 u8 dword_3[0x20]; 11538 u8 dword_4[0x20]; 11539 u8 dword_5[0x20]; 11540 u8 dword_6[0x20]; 11541 u8 dword_7[0x20]; 11542 u8 dword_8[0x20]; 11543 u8 dword_9[0x20]; 11544 u8 dword_10[0x20]; 11545 u8 dword_11[0x20]; 11546 }; 11547 11548 struct mlx5_ifc_dcbx_param_bits { 11549 u8 dcbx_cee_cap[0x1]; 11550 u8 dcbx_ieee_cap[0x1]; 11551 u8 dcbx_standby_cap[0x1]; 11552 u8 reserved_at_3[0x5]; 11553 u8 port_number[0x8]; 11554 u8 reserved_at_10[0xa]; 11555 u8 max_application_table_size[6]; 11556 u8 reserved_at_20[0x15]; 11557 u8 version_oper[0x3]; 11558 u8 reserved_at_38[5]; 11559 u8 version_admin[0x3]; 11560 u8 willing_admin[0x1]; 11561 u8 reserved_at_41[0x3]; 11562 u8 pfc_cap_oper[0x4]; 11563 u8 reserved_at_48[0x4]; 11564 u8 pfc_cap_admin[0x4]; 11565 u8 reserved_at_50[0x4]; 11566 u8 num_of_tc_oper[0x4]; 11567 u8 reserved_at_58[0x4]; 11568 u8 num_of_tc_admin[0x4]; 11569 u8 remote_willing[0x1]; 11570 u8 reserved_at_61[3]; 11571 u8 remote_pfc_cap[4]; 11572 u8 reserved_at_68[0x14]; 11573 u8 remote_num_of_tc[0x4]; 11574 u8 reserved_at_80[0x18]; 11575 u8 error[0x8]; 11576 u8 reserved_at_a0[0x160]; 11577 }; 11578 11579 enum { 11580 MLX5_LAG_PORT_SELECT_MODE_QUEUE_AFFINITY = 0, 11581 MLX5_LAG_PORT_SELECT_MODE_PORT_SELECT_FT = 1, 11582 MLX5_LAG_PORT_SELECT_MODE_PORT_SELECT_MPESW = 2, 11583 }; 11584 11585 struct mlx5_ifc_lagc_bits { 11586 u8 fdb_selection_mode[0x1]; 11587 u8 reserved_at_1[0x14]; 11588 u8 port_select_mode[0x3]; 11589 u8 reserved_at_18[0x5]; 11590 u8 lag_state[0x3]; 11591 11592 u8 reserved_at_20[0xc]; 11593 u8 active_port[0x4]; 11594 u8 reserved_at_30[0x4]; 11595 u8 tx_remap_affinity_2[0x4]; 11596 u8 reserved_at_38[0x4]; 11597 u8 tx_remap_affinity_1[0x4]; 11598 }; 11599 11600 struct mlx5_ifc_create_lag_out_bits { 11601 u8 status[0x8]; 11602 u8 reserved_at_8[0x18]; 11603 11604 u8 syndrome[0x20]; 11605 11606 u8 reserved_at_40[0x40]; 11607 }; 11608 11609 struct mlx5_ifc_create_lag_in_bits { 11610 u8 opcode[0x10]; 11611 u8 reserved_at_10[0x10]; 11612 11613 u8 reserved_at_20[0x10]; 11614 u8 op_mod[0x10]; 11615 11616 struct mlx5_ifc_lagc_bits ctx; 11617 }; 11618 11619 struct mlx5_ifc_modify_lag_out_bits { 11620 u8 status[0x8]; 11621 u8 reserved_at_8[0x18]; 11622 11623 u8 syndrome[0x20]; 11624 11625 u8 reserved_at_40[0x40]; 11626 }; 11627 11628 struct mlx5_ifc_modify_lag_in_bits { 11629 u8 opcode[0x10]; 11630 u8 reserved_at_10[0x10]; 11631 11632 u8 reserved_at_20[0x10]; 11633 u8 op_mod[0x10]; 11634 11635 u8 reserved_at_40[0x20]; 11636 u8 field_select[0x20]; 11637 11638 struct mlx5_ifc_lagc_bits ctx; 11639 }; 11640 11641 struct mlx5_ifc_query_lag_out_bits { 11642 u8 status[0x8]; 11643 u8 reserved_at_8[0x18]; 11644 11645 u8 syndrome[0x20]; 11646 11647 struct mlx5_ifc_lagc_bits ctx; 11648 }; 11649 11650 struct mlx5_ifc_query_lag_in_bits { 11651 u8 opcode[0x10]; 11652 u8 reserved_at_10[0x10]; 11653 11654 u8 reserved_at_20[0x10]; 11655 u8 op_mod[0x10]; 11656 11657 u8 reserved_at_40[0x40]; 11658 }; 11659 11660 struct mlx5_ifc_destroy_lag_out_bits { 11661 u8 status[0x8]; 11662 u8 reserved_at_8[0x18]; 11663 11664 u8 syndrome[0x20]; 11665 11666 u8 reserved_at_40[0x40]; 11667 }; 11668 11669 struct mlx5_ifc_destroy_lag_in_bits { 11670 u8 opcode[0x10]; 11671 u8 reserved_at_10[0x10]; 11672 11673 u8 reserved_at_20[0x10]; 11674 u8 op_mod[0x10]; 11675 11676 u8 reserved_at_40[0x40]; 11677 }; 11678 11679 struct mlx5_ifc_create_vport_lag_out_bits { 11680 u8 status[0x8]; 11681 u8 reserved_at_8[0x18]; 11682 11683 u8 syndrome[0x20]; 11684 11685 u8 reserved_at_40[0x40]; 11686 }; 11687 11688 struct mlx5_ifc_create_vport_lag_in_bits { 11689 u8 opcode[0x10]; 11690 u8 reserved_at_10[0x10]; 11691 11692 u8 reserved_at_20[0x10]; 11693 u8 op_mod[0x10]; 11694 11695 u8 reserved_at_40[0x40]; 11696 }; 11697 11698 struct mlx5_ifc_destroy_vport_lag_out_bits { 11699 u8 status[0x8]; 11700 u8 reserved_at_8[0x18]; 11701 11702 u8 syndrome[0x20]; 11703 11704 u8 reserved_at_40[0x40]; 11705 }; 11706 11707 struct mlx5_ifc_destroy_vport_lag_in_bits { 11708 u8 opcode[0x10]; 11709 u8 reserved_at_10[0x10]; 11710 11711 u8 reserved_at_20[0x10]; 11712 u8 op_mod[0x10]; 11713 11714 u8 reserved_at_40[0x40]; 11715 }; 11716 11717 enum { 11718 MLX5_MODIFY_MEMIC_OP_MOD_ALLOC, 11719 MLX5_MODIFY_MEMIC_OP_MOD_DEALLOC, 11720 }; 11721 11722 struct mlx5_ifc_modify_memic_in_bits { 11723 u8 opcode[0x10]; 11724 u8 uid[0x10]; 11725 11726 u8 reserved_at_20[0x10]; 11727 u8 op_mod[0x10]; 11728 11729 u8 reserved_at_40[0x20]; 11730 11731 u8 reserved_at_60[0x18]; 11732 u8 memic_operation_type[0x8]; 11733 11734 u8 memic_start_addr[0x40]; 11735 11736 u8 reserved_at_c0[0x140]; 11737 }; 11738 11739 struct mlx5_ifc_modify_memic_out_bits { 11740 u8 status[0x8]; 11741 u8 reserved_at_8[0x18]; 11742 11743 u8 syndrome[0x20]; 11744 11745 u8 reserved_at_40[0x40]; 11746 11747 u8 memic_operation_addr[0x40]; 11748 11749 u8 reserved_at_c0[0x140]; 11750 }; 11751 11752 struct mlx5_ifc_alloc_memic_in_bits { 11753 u8 opcode[0x10]; 11754 u8 reserved_at_10[0x10]; 11755 11756 u8 reserved_at_20[0x10]; 11757 u8 op_mod[0x10]; 11758 11759 u8 reserved_at_30[0x20]; 11760 11761 u8 reserved_at_40[0x18]; 11762 u8 log_memic_addr_alignment[0x8]; 11763 11764 u8 range_start_addr[0x40]; 11765 11766 u8 range_size[0x20]; 11767 11768 u8 memic_size[0x20]; 11769 }; 11770 11771 struct mlx5_ifc_alloc_memic_out_bits { 11772 u8 status[0x8]; 11773 u8 reserved_at_8[0x18]; 11774 11775 u8 syndrome[0x20]; 11776 11777 u8 memic_start_addr[0x40]; 11778 }; 11779 11780 struct mlx5_ifc_dealloc_memic_in_bits { 11781 u8 opcode[0x10]; 11782 u8 reserved_at_10[0x10]; 11783 11784 u8 reserved_at_20[0x10]; 11785 u8 op_mod[0x10]; 11786 11787 u8 reserved_at_40[0x40]; 11788 11789 u8 memic_start_addr[0x40]; 11790 11791 u8 memic_size[0x20]; 11792 11793 u8 reserved_at_e0[0x20]; 11794 }; 11795 11796 struct mlx5_ifc_dealloc_memic_out_bits { 11797 u8 status[0x8]; 11798 u8 reserved_at_8[0x18]; 11799 11800 u8 syndrome[0x20]; 11801 11802 u8 reserved_at_40[0x40]; 11803 }; 11804 11805 struct mlx5_ifc_umem_bits { 11806 u8 reserved_at_0[0x80]; 11807 11808 u8 ats[0x1]; 11809 u8 reserved_at_81[0x1a]; 11810 u8 log_page_size[0x5]; 11811 11812 u8 page_offset[0x20]; 11813 11814 u8 num_of_mtt[0x40]; 11815 11816 struct mlx5_ifc_mtt_bits mtt[]; 11817 }; 11818 11819 struct mlx5_ifc_uctx_bits { 11820 u8 cap[0x20]; 11821 11822 u8 reserved_at_20[0x160]; 11823 }; 11824 11825 struct mlx5_ifc_sw_icm_bits { 11826 u8 modify_field_select[0x40]; 11827 11828 u8 reserved_at_40[0x18]; 11829 u8 log_sw_icm_size[0x8]; 11830 11831 u8 reserved_at_60[0x20]; 11832 11833 u8 sw_icm_start_addr[0x40]; 11834 11835 u8 reserved_at_c0[0x140]; 11836 }; 11837 11838 struct mlx5_ifc_geneve_tlv_option_bits { 11839 u8 modify_field_select[0x40]; 11840 11841 u8 reserved_at_40[0x18]; 11842 u8 geneve_option_fte_index[0x8]; 11843 11844 u8 option_class[0x10]; 11845 u8 option_type[0x8]; 11846 u8 reserved_at_78[0x3]; 11847 u8 option_data_length[0x5]; 11848 11849 u8 reserved_at_80[0x180]; 11850 }; 11851 11852 struct mlx5_ifc_create_umem_in_bits { 11853 u8 opcode[0x10]; 11854 u8 uid[0x10]; 11855 11856 u8 reserved_at_20[0x10]; 11857 u8 op_mod[0x10]; 11858 11859 u8 reserved_at_40[0x40]; 11860 11861 struct mlx5_ifc_umem_bits umem; 11862 }; 11863 11864 struct mlx5_ifc_create_umem_out_bits { 11865 u8 status[0x8]; 11866 u8 reserved_at_8[0x18]; 11867 11868 u8 syndrome[0x20]; 11869 11870 u8 reserved_at_40[0x8]; 11871 u8 umem_id[0x18]; 11872 11873 u8 reserved_at_60[0x20]; 11874 }; 11875 11876 struct mlx5_ifc_destroy_umem_in_bits { 11877 u8 opcode[0x10]; 11878 u8 uid[0x10]; 11879 11880 u8 reserved_at_20[0x10]; 11881 u8 op_mod[0x10]; 11882 11883 u8 reserved_at_40[0x8]; 11884 u8 umem_id[0x18]; 11885 11886 u8 reserved_at_60[0x20]; 11887 }; 11888 11889 struct mlx5_ifc_destroy_umem_out_bits { 11890 u8 status[0x8]; 11891 u8 reserved_at_8[0x18]; 11892 11893 u8 syndrome[0x20]; 11894 11895 u8 reserved_at_40[0x40]; 11896 }; 11897 11898 struct mlx5_ifc_create_uctx_in_bits { 11899 u8 opcode[0x10]; 11900 u8 reserved_at_10[0x10]; 11901 11902 u8 reserved_at_20[0x10]; 11903 u8 op_mod[0x10]; 11904 11905 u8 reserved_at_40[0x40]; 11906 11907 struct mlx5_ifc_uctx_bits uctx; 11908 }; 11909 11910 struct mlx5_ifc_create_uctx_out_bits { 11911 u8 status[0x8]; 11912 u8 reserved_at_8[0x18]; 11913 11914 u8 syndrome[0x20]; 11915 11916 u8 reserved_at_40[0x10]; 11917 u8 uid[0x10]; 11918 11919 u8 reserved_at_60[0x20]; 11920 }; 11921 11922 struct mlx5_ifc_destroy_uctx_in_bits { 11923 u8 opcode[0x10]; 11924 u8 reserved_at_10[0x10]; 11925 11926 u8 reserved_at_20[0x10]; 11927 u8 op_mod[0x10]; 11928 11929 u8 reserved_at_40[0x10]; 11930 u8 uid[0x10]; 11931 11932 u8 reserved_at_60[0x20]; 11933 }; 11934 11935 struct mlx5_ifc_destroy_uctx_out_bits { 11936 u8 status[0x8]; 11937 u8 reserved_at_8[0x18]; 11938 11939 u8 syndrome[0x20]; 11940 11941 u8 reserved_at_40[0x40]; 11942 }; 11943 11944 struct mlx5_ifc_create_sw_icm_in_bits { 11945 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 11946 struct mlx5_ifc_sw_icm_bits sw_icm; 11947 }; 11948 11949 struct mlx5_ifc_create_geneve_tlv_option_in_bits { 11950 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 11951 struct mlx5_ifc_geneve_tlv_option_bits geneve_tlv_opt; 11952 }; 11953 11954 struct mlx5_ifc_mtrc_string_db_param_bits { 11955 u8 string_db_base_address[0x20]; 11956 11957 u8 reserved_at_20[0x8]; 11958 u8 string_db_size[0x18]; 11959 }; 11960 11961 struct mlx5_ifc_mtrc_cap_bits { 11962 u8 trace_owner[0x1]; 11963 u8 trace_to_memory[0x1]; 11964 u8 reserved_at_2[0x4]; 11965 u8 trc_ver[0x2]; 11966 u8 reserved_at_8[0x14]; 11967 u8 num_string_db[0x4]; 11968 11969 u8 first_string_trace[0x8]; 11970 u8 num_string_trace[0x8]; 11971 u8 reserved_at_30[0x28]; 11972 11973 u8 log_max_trace_buffer_size[0x8]; 11974 11975 u8 reserved_at_60[0x20]; 11976 11977 struct mlx5_ifc_mtrc_string_db_param_bits string_db_param[8]; 11978 11979 u8 reserved_at_280[0x180]; 11980 }; 11981 11982 struct mlx5_ifc_mtrc_conf_bits { 11983 u8 reserved_at_0[0x1c]; 11984 u8 trace_mode[0x4]; 11985 u8 reserved_at_20[0x18]; 11986 u8 log_trace_buffer_size[0x8]; 11987 u8 trace_mkey[0x20]; 11988 u8 reserved_at_60[0x3a0]; 11989 }; 11990 11991 struct mlx5_ifc_mtrc_stdb_bits { 11992 u8 string_db_index[0x4]; 11993 u8 reserved_at_4[0x4]; 11994 u8 read_size[0x18]; 11995 u8 start_offset[0x20]; 11996 u8 string_db_data[]; 11997 }; 11998 11999 struct mlx5_ifc_mtrc_ctrl_bits { 12000 u8 trace_status[0x2]; 12001 u8 reserved_at_2[0x2]; 12002 u8 arm_event[0x1]; 12003 u8 reserved_at_5[0xb]; 12004 u8 modify_field_select[0x10]; 12005 u8 reserved_at_20[0x2b]; 12006 u8 current_timestamp52_32[0x15]; 12007 u8 current_timestamp31_0[0x20]; 12008 u8 reserved_at_80[0x180]; 12009 }; 12010 12011 struct mlx5_ifc_host_params_context_bits { 12012 u8 host_number[0x8]; 12013 u8 reserved_at_8[0x7]; 12014 u8 host_pf_disabled[0x1]; 12015 u8 host_num_of_vfs[0x10]; 12016 12017 u8 host_total_vfs[0x10]; 12018 u8 host_pci_bus[0x10]; 12019 12020 u8 reserved_at_40[0x10]; 12021 u8 host_pci_device[0x10]; 12022 12023 u8 reserved_at_60[0x10]; 12024 u8 host_pci_function[0x10]; 12025 12026 u8 reserved_at_80[0x180]; 12027 }; 12028 12029 struct mlx5_ifc_query_esw_functions_in_bits { 12030 u8 opcode[0x10]; 12031 u8 reserved_at_10[0x10]; 12032 12033 u8 reserved_at_20[0x10]; 12034 u8 op_mod[0x10]; 12035 12036 u8 reserved_at_40[0x40]; 12037 }; 12038 12039 struct mlx5_ifc_query_esw_functions_out_bits { 12040 u8 status[0x8]; 12041 u8 reserved_at_8[0x18]; 12042 12043 u8 syndrome[0x20]; 12044 12045 u8 reserved_at_40[0x40]; 12046 12047 struct mlx5_ifc_host_params_context_bits host_params_context; 12048 12049 u8 reserved_at_280[0x180]; 12050 u8 host_sf_enable[][0x40]; 12051 }; 12052 12053 struct mlx5_ifc_sf_partition_bits { 12054 u8 reserved_at_0[0x10]; 12055 u8 log_num_sf[0x8]; 12056 u8 log_sf_bar_size[0x8]; 12057 }; 12058 12059 struct mlx5_ifc_query_sf_partitions_out_bits { 12060 u8 status[0x8]; 12061 u8 reserved_at_8[0x18]; 12062 12063 u8 syndrome[0x20]; 12064 12065 u8 reserved_at_40[0x18]; 12066 u8 num_sf_partitions[0x8]; 12067 12068 u8 reserved_at_60[0x20]; 12069 12070 struct mlx5_ifc_sf_partition_bits sf_partition[]; 12071 }; 12072 12073 struct mlx5_ifc_query_sf_partitions_in_bits { 12074 u8 opcode[0x10]; 12075 u8 reserved_at_10[0x10]; 12076 12077 u8 reserved_at_20[0x10]; 12078 u8 op_mod[0x10]; 12079 12080 u8 reserved_at_40[0x40]; 12081 }; 12082 12083 struct mlx5_ifc_dealloc_sf_out_bits { 12084 u8 status[0x8]; 12085 u8 reserved_at_8[0x18]; 12086 12087 u8 syndrome[0x20]; 12088 12089 u8 reserved_at_40[0x40]; 12090 }; 12091 12092 struct mlx5_ifc_dealloc_sf_in_bits { 12093 u8 opcode[0x10]; 12094 u8 reserved_at_10[0x10]; 12095 12096 u8 reserved_at_20[0x10]; 12097 u8 op_mod[0x10]; 12098 12099 u8 reserved_at_40[0x10]; 12100 u8 function_id[0x10]; 12101 12102 u8 reserved_at_60[0x20]; 12103 }; 12104 12105 struct mlx5_ifc_alloc_sf_out_bits { 12106 u8 status[0x8]; 12107 u8 reserved_at_8[0x18]; 12108 12109 u8 syndrome[0x20]; 12110 12111 u8 reserved_at_40[0x40]; 12112 }; 12113 12114 struct mlx5_ifc_alloc_sf_in_bits { 12115 u8 opcode[0x10]; 12116 u8 reserved_at_10[0x10]; 12117 12118 u8 reserved_at_20[0x10]; 12119 u8 op_mod[0x10]; 12120 12121 u8 reserved_at_40[0x10]; 12122 u8 function_id[0x10]; 12123 12124 u8 reserved_at_60[0x20]; 12125 }; 12126 12127 struct mlx5_ifc_affiliated_event_header_bits { 12128 u8 reserved_at_0[0x10]; 12129 u8 obj_type[0x10]; 12130 12131 u8 obj_id[0x20]; 12132 }; 12133 12134 enum { 12135 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = BIT_ULL(0xc), 12136 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_IPSEC = BIT_ULL(0x13), 12137 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_SAMPLER = BIT_ULL(0x20), 12138 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_FLOW_METER_ASO = BIT_ULL(0x24), 12139 }; 12140 12141 enum { 12142 MLX5_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = 0xc, 12143 MLX5_GENERAL_OBJECT_TYPES_IPSEC = 0x13, 12144 MLX5_GENERAL_OBJECT_TYPES_SAMPLER = 0x20, 12145 MLX5_GENERAL_OBJECT_TYPES_FLOW_METER_ASO = 0x24, 12146 MLX5_GENERAL_OBJECT_TYPES_MACSEC = 0x27, 12147 MLX5_GENERAL_OBJECT_TYPES_INT_KEK = 0x47, 12148 MLX5_GENERAL_OBJECT_TYPES_FLOW_TABLE_ALIAS = 0xff15, 12149 }; 12150 12151 enum { 12152 MLX5_IPSEC_OBJECT_ICV_LEN_16B, 12153 }; 12154 12155 enum { 12156 MLX5_IPSEC_ASO_REG_C_0_1 = 0x0, 12157 MLX5_IPSEC_ASO_REG_C_2_3 = 0x1, 12158 MLX5_IPSEC_ASO_REG_C_4_5 = 0x2, 12159 MLX5_IPSEC_ASO_REG_C_6_7 = 0x3, 12160 }; 12161 12162 enum { 12163 MLX5_IPSEC_ASO_MODE = 0x0, 12164 MLX5_IPSEC_ASO_REPLAY_PROTECTION = 0x1, 12165 MLX5_IPSEC_ASO_INC_SN = 0x2, 12166 }; 12167 12168 enum { 12169 MLX5_IPSEC_ASO_REPLAY_WIN_32BIT = 0x0, 12170 MLX5_IPSEC_ASO_REPLAY_WIN_64BIT = 0x1, 12171 MLX5_IPSEC_ASO_REPLAY_WIN_128BIT = 0x2, 12172 MLX5_IPSEC_ASO_REPLAY_WIN_256BIT = 0x3, 12173 }; 12174 12175 struct mlx5_ifc_ipsec_aso_bits { 12176 u8 valid[0x1]; 12177 u8 reserved_at_201[0x1]; 12178 u8 mode[0x2]; 12179 u8 window_sz[0x2]; 12180 u8 soft_lft_arm[0x1]; 12181 u8 hard_lft_arm[0x1]; 12182 u8 remove_flow_enable[0x1]; 12183 u8 esn_event_arm[0x1]; 12184 u8 reserved_at_20a[0x16]; 12185 12186 u8 remove_flow_pkt_cnt[0x20]; 12187 12188 u8 remove_flow_soft_lft[0x20]; 12189 12190 u8 reserved_at_260[0x80]; 12191 12192 u8 mode_parameter[0x20]; 12193 12194 u8 replay_protection_window[0x100]; 12195 }; 12196 12197 struct mlx5_ifc_ipsec_obj_bits { 12198 u8 modify_field_select[0x40]; 12199 u8 full_offload[0x1]; 12200 u8 reserved_at_41[0x1]; 12201 u8 esn_en[0x1]; 12202 u8 esn_overlap[0x1]; 12203 u8 reserved_at_44[0x2]; 12204 u8 icv_length[0x2]; 12205 u8 reserved_at_48[0x4]; 12206 u8 aso_return_reg[0x4]; 12207 u8 reserved_at_50[0x10]; 12208 12209 u8 esn_msb[0x20]; 12210 12211 u8 reserved_at_80[0x8]; 12212 u8 dekn[0x18]; 12213 12214 u8 salt[0x20]; 12215 12216 u8 implicit_iv[0x40]; 12217 12218 u8 reserved_at_100[0x8]; 12219 u8 ipsec_aso_access_pd[0x18]; 12220 u8 reserved_at_120[0xe0]; 12221 12222 struct mlx5_ifc_ipsec_aso_bits ipsec_aso; 12223 }; 12224 12225 struct mlx5_ifc_create_ipsec_obj_in_bits { 12226 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12227 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 12228 }; 12229 12230 enum { 12231 MLX5_MODIFY_IPSEC_BITMASK_ESN_OVERLAP = BIT(0), 12232 MLX5_MODIFY_IPSEC_BITMASK_ESN_MSB = BIT(1), 12233 }; 12234 12235 struct mlx5_ifc_query_ipsec_obj_out_bits { 12236 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 12237 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 12238 }; 12239 12240 struct mlx5_ifc_modify_ipsec_obj_in_bits { 12241 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12242 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 12243 }; 12244 12245 enum { 12246 MLX5_MACSEC_ASO_REPLAY_PROTECTION = 0x1, 12247 }; 12248 12249 enum { 12250 MLX5_MACSEC_ASO_REPLAY_WIN_32BIT = 0x0, 12251 MLX5_MACSEC_ASO_REPLAY_WIN_64BIT = 0x1, 12252 MLX5_MACSEC_ASO_REPLAY_WIN_128BIT = 0x2, 12253 MLX5_MACSEC_ASO_REPLAY_WIN_256BIT = 0x3, 12254 }; 12255 12256 #define MLX5_MACSEC_ASO_INC_SN 0x2 12257 #define MLX5_MACSEC_ASO_REG_C_4_5 0x2 12258 12259 struct mlx5_ifc_macsec_aso_bits { 12260 u8 valid[0x1]; 12261 u8 reserved_at_1[0x1]; 12262 u8 mode[0x2]; 12263 u8 window_size[0x2]; 12264 u8 soft_lifetime_arm[0x1]; 12265 u8 hard_lifetime_arm[0x1]; 12266 u8 remove_flow_enable[0x1]; 12267 u8 epn_event_arm[0x1]; 12268 u8 reserved_at_a[0x16]; 12269 12270 u8 remove_flow_packet_count[0x20]; 12271 12272 u8 remove_flow_soft_lifetime[0x20]; 12273 12274 u8 reserved_at_60[0x80]; 12275 12276 u8 mode_parameter[0x20]; 12277 12278 u8 replay_protection_window[8][0x20]; 12279 }; 12280 12281 struct mlx5_ifc_macsec_offload_obj_bits { 12282 u8 modify_field_select[0x40]; 12283 12284 u8 confidentiality_en[0x1]; 12285 u8 reserved_at_41[0x1]; 12286 u8 epn_en[0x1]; 12287 u8 epn_overlap[0x1]; 12288 u8 reserved_at_44[0x2]; 12289 u8 confidentiality_offset[0x2]; 12290 u8 reserved_at_48[0x4]; 12291 u8 aso_return_reg[0x4]; 12292 u8 reserved_at_50[0x10]; 12293 12294 u8 epn_msb[0x20]; 12295 12296 u8 reserved_at_80[0x8]; 12297 u8 dekn[0x18]; 12298 12299 u8 reserved_at_a0[0x20]; 12300 12301 u8 sci[0x40]; 12302 12303 u8 reserved_at_100[0x8]; 12304 u8 macsec_aso_access_pd[0x18]; 12305 12306 u8 reserved_at_120[0x60]; 12307 12308 u8 salt[3][0x20]; 12309 12310 u8 reserved_at_1e0[0x20]; 12311 12312 struct mlx5_ifc_macsec_aso_bits macsec_aso; 12313 }; 12314 12315 struct mlx5_ifc_create_macsec_obj_in_bits { 12316 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12317 struct mlx5_ifc_macsec_offload_obj_bits macsec_object; 12318 }; 12319 12320 struct mlx5_ifc_modify_macsec_obj_in_bits { 12321 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12322 struct mlx5_ifc_macsec_offload_obj_bits macsec_object; 12323 }; 12324 12325 enum { 12326 MLX5_MODIFY_MACSEC_BITMASK_EPN_OVERLAP = BIT(0), 12327 MLX5_MODIFY_MACSEC_BITMASK_EPN_MSB = BIT(1), 12328 }; 12329 12330 struct mlx5_ifc_query_macsec_obj_out_bits { 12331 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 12332 struct mlx5_ifc_macsec_offload_obj_bits macsec_object; 12333 }; 12334 12335 struct mlx5_ifc_wrapped_dek_bits { 12336 u8 gcm_iv[0x60]; 12337 12338 u8 reserved_at_60[0x20]; 12339 12340 u8 const0[0x1]; 12341 u8 key_size[0x1]; 12342 u8 reserved_at_82[0x2]; 12343 u8 key2_invalid[0x1]; 12344 u8 reserved_at_85[0x3]; 12345 u8 pd[0x18]; 12346 12347 u8 key_purpose[0x5]; 12348 u8 reserved_at_a5[0x13]; 12349 u8 kek_id[0x8]; 12350 12351 u8 reserved_at_c0[0x40]; 12352 12353 u8 key1[0x8][0x20]; 12354 12355 u8 key2[0x8][0x20]; 12356 12357 u8 reserved_at_300[0x40]; 12358 12359 u8 const1[0x1]; 12360 u8 reserved_at_341[0x1f]; 12361 12362 u8 reserved_at_360[0x20]; 12363 12364 u8 auth_tag[0x80]; 12365 }; 12366 12367 struct mlx5_ifc_encryption_key_obj_bits { 12368 u8 modify_field_select[0x40]; 12369 12370 u8 state[0x8]; 12371 u8 sw_wrapped[0x1]; 12372 u8 reserved_at_49[0xb]; 12373 u8 key_size[0x4]; 12374 u8 reserved_at_58[0x4]; 12375 u8 key_purpose[0x4]; 12376 12377 u8 reserved_at_60[0x8]; 12378 u8 pd[0x18]; 12379 12380 u8 reserved_at_80[0x100]; 12381 12382 u8 opaque[0x40]; 12383 12384 u8 reserved_at_1c0[0x40]; 12385 12386 u8 key[8][0x80]; 12387 12388 u8 sw_wrapped_dek[8][0x80]; 12389 12390 u8 reserved_at_a00[0x600]; 12391 }; 12392 12393 struct mlx5_ifc_create_encryption_key_in_bits { 12394 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12395 struct mlx5_ifc_encryption_key_obj_bits encryption_key_object; 12396 }; 12397 12398 struct mlx5_ifc_modify_encryption_key_in_bits { 12399 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12400 struct mlx5_ifc_encryption_key_obj_bits encryption_key_object; 12401 }; 12402 12403 enum { 12404 MLX5_FLOW_METER_MODE_BYTES_IP_LENGTH = 0x0, 12405 MLX5_FLOW_METER_MODE_BYTES_CALC_WITH_L2 = 0x1, 12406 MLX5_FLOW_METER_MODE_BYTES_CALC_WITH_L2_IPG = 0x2, 12407 MLX5_FLOW_METER_MODE_NUM_PACKETS = 0x3, 12408 }; 12409 12410 struct mlx5_ifc_flow_meter_parameters_bits { 12411 u8 valid[0x1]; 12412 u8 bucket_overflow[0x1]; 12413 u8 start_color[0x2]; 12414 u8 both_buckets_on_green[0x1]; 12415 u8 reserved_at_5[0x1]; 12416 u8 meter_mode[0x2]; 12417 u8 reserved_at_8[0x18]; 12418 12419 u8 reserved_at_20[0x20]; 12420 12421 u8 reserved_at_40[0x3]; 12422 u8 cbs_exponent[0x5]; 12423 u8 cbs_mantissa[0x8]; 12424 u8 reserved_at_50[0x3]; 12425 u8 cir_exponent[0x5]; 12426 u8 cir_mantissa[0x8]; 12427 12428 u8 reserved_at_60[0x20]; 12429 12430 u8 reserved_at_80[0x3]; 12431 u8 ebs_exponent[0x5]; 12432 u8 ebs_mantissa[0x8]; 12433 u8 reserved_at_90[0x3]; 12434 u8 eir_exponent[0x5]; 12435 u8 eir_mantissa[0x8]; 12436 12437 u8 reserved_at_a0[0x60]; 12438 }; 12439 12440 struct mlx5_ifc_flow_meter_aso_obj_bits { 12441 u8 modify_field_select[0x40]; 12442 12443 u8 reserved_at_40[0x40]; 12444 12445 u8 reserved_at_80[0x8]; 12446 u8 meter_aso_access_pd[0x18]; 12447 12448 u8 reserved_at_a0[0x160]; 12449 12450 struct mlx5_ifc_flow_meter_parameters_bits flow_meter_parameters[2]; 12451 }; 12452 12453 struct mlx5_ifc_create_flow_meter_aso_obj_in_bits { 12454 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 12455 struct mlx5_ifc_flow_meter_aso_obj_bits flow_meter_aso_obj; 12456 }; 12457 12458 struct mlx5_ifc_int_kek_obj_bits { 12459 u8 modify_field_select[0x40]; 12460 12461 u8 state[0x8]; 12462 u8 auto_gen[0x1]; 12463 u8 reserved_at_49[0xb]; 12464 u8 key_size[0x4]; 12465 u8 reserved_at_58[0x8]; 12466 12467 u8 reserved_at_60[0x8]; 12468 u8 pd[0x18]; 12469 12470 u8 reserved_at_80[0x180]; 12471 u8 key[8][0x80]; 12472 12473 u8 reserved_at_600[0x200]; 12474 }; 12475 12476 struct mlx5_ifc_create_int_kek_obj_in_bits { 12477 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12478 struct mlx5_ifc_int_kek_obj_bits int_kek_object; 12479 }; 12480 12481 struct mlx5_ifc_create_int_kek_obj_out_bits { 12482 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 12483 struct mlx5_ifc_int_kek_obj_bits int_kek_object; 12484 }; 12485 12486 struct mlx5_ifc_sampler_obj_bits { 12487 u8 modify_field_select[0x40]; 12488 12489 u8 table_type[0x8]; 12490 u8 level[0x8]; 12491 u8 reserved_at_50[0xf]; 12492 u8 ignore_flow_level[0x1]; 12493 12494 u8 sample_ratio[0x20]; 12495 12496 u8 reserved_at_80[0x8]; 12497 u8 sample_table_id[0x18]; 12498 12499 u8 reserved_at_a0[0x8]; 12500 u8 default_table_id[0x18]; 12501 12502 u8 sw_steering_icm_address_rx[0x40]; 12503 u8 sw_steering_icm_address_tx[0x40]; 12504 12505 u8 reserved_at_140[0xa0]; 12506 }; 12507 12508 struct mlx5_ifc_create_sampler_obj_in_bits { 12509 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12510 struct mlx5_ifc_sampler_obj_bits sampler_object; 12511 }; 12512 12513 struct mlx5_ifc_query_sampler_obj_out_bits { 12514 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 12515 struct mlx5_ifc_sampler_obj_bits sampler_object; 12516 }; 12517 12518 enum { 12519 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_128 = 0x0, 12520 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_256 = 0x1, 12521 }; 12522 12523 enum { 12524 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_PURPOSE_TLS = 0x1, 12525 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_PURPOSE_IPSEC = 0x2, 12526 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_PURPOSE_MACSEC = 0x4, 12527 }; 12528 12529 struct mlx5_ifc_tls_static_params_bits { 12530 u8 const_2[0x2]; 12531 u8 tls_version[0x4]; 12532 u8 const_1[0x2]; 12533 u8 reserved_at_8[0x14]; 12534 u8 encryption_standard[0x4]; 12535 12536 u8 reserved_at_20[0x20]; 12537 12538 u8 initial_record_number[0x40]; 12539 12540 u8 resync_tcp_sn[0x20]; 12541 12542 u8 gcm_iv[0x20]; 12543 12544 u8 implicit_iv[0x40]; 12545 12546 u8 reserved_at_100[0x8]; 12547 u8 dek_index[0x18]; 12548 12549 u8 reserved_at_120[0xe0]; 12550 }; 12551 12552 struct mlx5_ifc_tls_progress_params_bits { 12553 u8 next_record_tcp_sn[0x20]; 12554 12555 u8 hw_resync_tcp_sn[0x20]; 12556 12557 u8 record_tracker_state[0x2]; 12558 u8 auth_state[0x2]; 12559 u8 reserved_at_44[0x4]; 12560 u8 hw_offset_record_number[0x18]; 12561 }; 12562 12563 enum { 12564 MLX5_MTT_PERM_READ = 1 << 0, 12565 MLX5_MTT_PERM_WRITE = 1 << 1, 12566 MLX5_MTT_PERM_RW = MLX5_MTT_PERM_READ | MLX5_MTT_PERM_WRITE, 12567 }; 12568 12569 enum { 12570 MLX5_SUSPEND_VHCA_IN_OP_MOD_SUSPEND_INITIATOR = 0x0, 12571 MLX5_SUSPEND_VHCA_IN_OP_MOD_SUSPEND_RESPONDER = 0x1, 12572 }; 12573 12574 struct mlx5_ifc_suspend_vhca_in_bits { 12575 u8 opcode[0x10]; 12576 u8 uid[0x10]; 12577 12578 u8 reserved_at_20[0x10]; 12579 u8 op_mod[0x10]; 12580 12581 u8 reserved_at_40[0x10]; 12582 u8 vhca_id[0x10]; 12583 12584 u8 reserved_at_60[0x20]; 12585 }; 12586 12587 struct mlx5_ifc_suspend_vhca_out_bits { 12588 u8 status[0x8]; 12589 u8 reserved_at_8[0x18]; 12590 12591 u8 syndrome[0x20]; 12592 12593 u8 reserved_at_40[0x40]; 12594 }; 12595 12596 enum { 12597 MLX5_RESUME_VHCA_IN_OP_MOD_RESUME_RESPONDER = 0x0, 12598 MLX5_RESUME_VHCA_IN_OP_MOD_RESUME_INITIATOR = 0x1, 12599 }; 12600 12601 struct mlx5_ifc_resume_vhca_in_bits { 12602 u8 opcode[0x10]; 12603 u8 uid[0x10]; 12604 12605 u8 reserved_at_20[0x10]; 12606 u8 op_mod[0x10]; 12607 12608 u8 reserved_at_40[0x10]; 12609 u8 vhca_id[0x10]; 12610 12611 u8 reserved_at_60[0x20]; 12612 }; 12613 12614 struct mlx5_ifc_resume_vhca_out_bits { 12615 u8 status[0x8]; 12616 u8 reserved_at_8[0x18]; 12617 12618 u8 syndrome[0x20]; 12619 12620 u8 reserved_at_40[0x40]; 12621 }; 12622 12623 struct mlx5_ifc_query_vhca_migration_state_in_bits { 12624 u8 opcode[0x10]; 12625 u8 uid[0x10]; 12626 12627 u8 reserved_at_20[0x10]; 12628 u8 op_mod[0x10]; 12629 12630 u8 incremental[0x1]; 12631 u8 chunk[0x1]; 12632 u8 reserved_at_42[0xe]; 12633 u8 vhca_id[0x10]; 12634 12635 u8 reserved_at_60[0x20]; 12636 }; 12637 12638 struct mlx5_ifc_query_vhca_migration_state_out_bits { 12639 u8 status[0x8]; 12640 u8 reserved_at_8[0x18]; 12641 12642 u8 syndrome[0x20]; 12643 12644 u8 reserved_at_40[0x40]; 12645 12646 u8 required_umem_size[0x20]; 12647 12648 u8 reserved_at_a0[0x20]; 12649 12650 u8 remaining_total_size[0x40]; 12651 12652 u8 reserved_at_100[0x100]; 12653 }; 12654 12655 struct mlx5_ifc_save_vhca_state_in_bits { 12656 u8 opcode[0x10]; 12657 u8 uid[0x10]; 12658 12659 u8 reserved_at_20[0x10]; 12660 u8 op_mod[0x10]; 12661 12662 u8 incremental[0x1]; 12663 u8 set_track[0x1]; 12664 u8 reserved_at_42[0xe]; 12665 u8 vhca_id[0x10]; 12666 12667 u8 reserved_at_60[0x20]; 12668 12669 u8 va[0x40]; 12670 12671 u8 mkey[0x20]; 12672 12673 u8 size[0x20]; 12674 }; 12675 12676 struct mlx5_ifc_save_vhca_state_out_bits { 12677 u8 status[0x8]; 12678 u8 reserved_at_8[0x18]; 12679 12680 u8 syndrome[0x20]; 12681 12682 u8 actual_image_size[0x20]; 12683 12684 u8 next_required_umem_size[0x20]; 12685 }; 12686 12687 struct mlx5_ifc_load_vhca_state_in_bits { 12688 u8 opcode[0x10]; 12689 u8 uid[0x10]; 12690 12691 u8 reserved_at_20[0x10]; 12692 u8 op_mod[0x10]; 12693 12694 u8 reserved_at_40[0x10]; 12695 u8 vhca_id[0x10]; 12696 12697 u8 reserved_at_60[0x20]; 12698 12699 u8 va[0x40]; 12700 12701 u8 mkey[0x20]; 12702 12703 u8 size[0x20]; 12704 }; 12705 12706 struct mlx5_ifc_load_vhca_state_out_bits { 12707 u8 status[0x8]; 12708 u8 reserved_at_8[0x18]; 12709 12710 u8 syndrome[0x20]; 12711 12712 u8 reserved_at_40[0x40]; 12713 }; 12714 12715 struct mlx5_ifc_adv_virtualization_cap_bits { 12716 u8 reserved_at_0[0x3]; 12717 u8 pg_track_log_max_num[0x5]; 12718 u8 pg_track_max_num_range[0x8]; 12719 u8 pg_track_log_min_addr_space[0x8]; 12720 u8 pg_track_log_max_addr_space[0x8]; 12721 12722 u8 reserved_at_20[0x3]; 12723 u8 pg_track_log_min_msg_size[0x5]; 12724 u8 reserved_at_28[0x3]; 12725 u8 pg_track_log_max_msg_size[0x5]; 12726 u8 reserved_at_30[0x3]; 12727 u8 pg_track_log_min_page_size[0x5]; 12728 u8 reserved_at_38[0x3]; 12729 u8 pg_track_log_max_page_size[0x5]; 12730 12731 u8 reserved_at_40[0x7c0]; 12732 }; 12733 12734 struct mlx5_ifc_page_track_report_entry_bits { 12735 u8 dirty_address_high[0x20]; 12736 12737 u8 dirty_address_low[0x20]; 12738 }; 12739 12740 enum { 12741 MLX5_PAGE_TRACK_STATE_TRACKING, 12742 MLX5_PAGE_TRACK_STATE_REPORTING, 12743 MLX5_PAGE_TRACK_STATE_ERROR, 12744 }; 12745 12746 struct mlx5_ifc_page_track_range_bits { 12747 u8 start_address[0x40]; 12748 12749 u8 length[0x40]; 12750 }; 12751 12752 struct mlx5_ifc_page_track_bits { 12753 u8 modify_field_select[0x40]; 12754 12755 u8 reserved_at_40[0x10]; 12756 u8 vhca_id[0x10]; 12757 12758 u8 reserved_at_60[0x20]; 12759 12760 u8 state[0x4]; 12761 u8 track_type[0x4]; 12762 u8 log_addr_space_size[0x8]; 12763 u8 reserved_at_90[0x3]; 12764 u8 log_page_size[0x5]; 12765 u8 reserved_at_98[0x3]; 12766 u8 log_msg_size[0x5]; 12767 12768 u8 reserved_at_a0[0x8]; 12769 u8 reporting_qpn[0x18]; 12770 12771 u8 reserved_at_c0[0x18]; 12772 u8 num_ranges[0x8]; 12773 12774 u8 reserved_at_e0[0x20]; 12775 12776 u8 range_start_address[0x40]; 12777 12778 u8 length[0x40]; 12779 12780 struct mlx5_ifc_page_track_range_bits track_range[0]; 12781 }; 12782 12783 struct mlx5_ifc_create_page_track_obj_in_bits { 12784 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12785 struct mlx5_ifc_page_track_bits obj_context; 12786 }; 12787 12788 struct mlx5_ifc_modify_page_track_obj_in_bits { 12789 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12790 struct mlx5_ifc_page_track_bits obj_context; 12791 }; 12792 12793 struct mlx5_ifc_query_page_track_obj_out_bits { 12794 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 12795 struct mlx5_ifc_page_track_bits obj_context; 12796 }; 12797 12798 struct mlx5_ifc_msecq_reg_bits { 12799 u8 reserved_at_0[0x20]; 12800 12801 u8 reserved_at_20[0x12]; 12802 u8 network_option[0x2]; 12803 u8 local_ssm_code[0x4]; 12804 u8 local_enhanced_ssm_code[0x8]; 12805 12806 u8 local_clock_identity[0x40]; 12807 12808 u8 reserved_at_80[0x180]; 12809 }; 12810 12811 enum { 12812 MLX5_MSEES_FIELD_SELECT_ENABLE = BIT(0), 12813 MLX5_MSEES_FIELD_SELECT_ADMIN_STATUS = BIT(1), 12814 MLX5_MSEES_FIELD_SELECT_ADMIN_FREQ_MEASURE = BIT(2), 12815 }; 12816 12817 enum mlx5_msees_admin_status { 12818 MLX5_MSEES_ADMIN_STATUS_FREE_RUNNING = 0x0, 12819 MLX5_MSEES_ADMIN_STATUS_TRACK = 0x1, 12820 }; 12821 12822 enum mlx5_msees_oper_status { 12823 MLX5_MSEES_OPER_STATUS_FREE_RUNNING = 0x0, 12824 MLX5_MSEES_OPER_STATUS_SELF_TRACK = 0x1, 12825 MLX5_MSEES_OPER_STATUS_OTHER_TRACK = 0x2, 12826 MLX5_MSEES_OPER_STATUS_HOLDOVER = 0x3, 12827 MLX5_MSEES_OPER_STATUS_FAIL_HOLDOVER = 0x4, 12828 MLX5_MSEES_OPER_STATUS_FAIL_FREE_RUNNING = 0x5, 12829 }; 12830 12831 enum mlx5_msees_failure_reason { 12832 MLX5_MSEES_FAILURE_REASON_UNDEFINED_ERROR = 0x0, 12833 MLX5_MSEES_FAILURE_REASON_PORT_DOWN = 0x1, 12834 MLX5_MSEES_FAILURE_REASON_TOO_HIGH_FREQUENCY_DIFF = 0x2, 12835 MLX5_MSEES_FAILURE_REASON_NET_SYNCHRONIZER_DEVICE_ERROR = 0x3, 12836 MLX5_MSEES_FAILURE_REASON_LACK_OF_RESOURCES = 0x4, 12837 }; 12838 12839 struct mlx5_ifc_msees_reg_bits { 12840 u8 reserved_at_0[0x8]; 12841 u8 local_port[0x8]; 12842 u8 pnat[0x2]; 12843 u8 lp_msb[0x2]; 12844 u8 reserved_at_14[0xc]; 12845 12846 u8 field_select[0x20]; 12847 12848 u8 admin_status[0x4]; 12849 u8 oper_status[0x4]; 12850 u8 ho_acq[0x1]; 12851 u8 reserved_at_49[0xc]; 12852 u8 admin_freq_measure[0x1]; 12853 u8 oper_freq_measure[0x1]; 12854 u8 failure_reason[0x9]; 12855 12856 u8 frequency_diff[0x20]; 12857 12858 u8 reserved_at_80[0x180]; 12859 }; 12860 12861 #endif /* MLX5_IFC_H */ 12862