1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 #ifndef MLX5_IFC_H 33 #define MLX5_IFC_H 34 35 #include "mlx5_ifc_fpga.h" 36 37 enum { 38 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0, 39 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1, 40 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2, 41 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3, 42 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13, 43 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14, 44 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c, 45 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d, 46 MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4, 47 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5, 48 MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED = 0x7, 49 MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT = 0xc, 50 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10, 51 MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR = 0x11, 52 MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR = 0x12, 53 MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR = 0x8, 54 MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE = 0x9, 55 MLX5_EVENT_TYPE_CODING_GPIO_EVENT = 0x15, 56 MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19, 57 MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a, 58 MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT = 0x1b, 59 MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT = 0x1f, 60 MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa, 61 MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb, 62 MLX5_EVENT_TYPE_CODING_FPGA_ERROR = 0x20, 63 MLX5_EVENT_TYPE_CODING_FPGA_QP_ERROR = 0x21 64 }; 65 66 enum { 67 MLX5_MODIFY_TIR_BITMASK_LRO = 0x0, 68 MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE = 0x1, 69 MLX5_MODIFY_TIR_BITMASK_HASH = 0x2, 70 MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN = 0x3 71 }; 72 73 enum { 74 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0, 75 MLX5_SET_HCA_CAP_OP_MOD_ODP = 0x2, 76 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3, 77 MLX5_SET_HCA_CAP_OP_MOD_ROCE = 0x4, 78 }; 79 80 enum { 81 MLX5_SHARED_RESOURCE_UID = 0xffff, 82 }; 83 84 enum { 85 MLX5_OBJ_TYPE_SW_ICM = 0x0008, 86 }; 87 88 enum { 89 MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM = (1ULL << MLX5_OBJ_TYPE_SW_ICM), 90 MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT = (1ULL << 11), 91 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q = (1ULL << 13), 92 }; 93 94 enum { 95 MLX5_OBJ_TYPE_GENEVE_TLV_OPT = 0x000b, 96 MLX5_OBJ_TYPE_VIRTIO_NET_Q = 0x000d, 97 MLX5_OBJ_TYPE_MKEY = 0xff01, 98 MLX5_OBJ_TYPE_QP = 0xff02, 99 MLX5_OBJ_TYPE_PSV = 0xff03, 100 MLX5_OBJ_TYPE_RMP = 0xff04, 101 MLX5_OBJ_TYPE_XRC_SRQ = 0xff05, 102 MLX5_OBJ_TYPE_RQ = 0xff06, 103 MLX5_OBJ_TYPE_SQ = 0xff07, 104 MLX5_OBJ_TYPE_TIR = 0xff08, 105 MLX5_OBJ_TYPE_TIS = 0xff09, 106 MLX5_OBJ_TYPE_DCT = 0xff0a, 107 MLX5_OBJ_TYPE_XRQ = 0xff0b, 108 MLX5_OBJ_TYPE_RQT = 0xff0e, 109 MLX5_OBJ_TYPE_FLOW_COUNTER = 0xff0f, 110 MLX5_OBJ_TYPE_CQ = 0xff10, 111 }; 112 113 enum { 114 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100, 115 MLX5_CMD_OP_QUERY_ADAPTER = 0x101, 116 MLX5_CMD_OP_INIT_HCA = 0x102, 117 MLX5_CMD_OP_TEARDOWN_HCA = 0x103, 118 MLX5_CMD_OP_ENABLE_HCA = 0x104, 119 MLX5_CMD_OP_DISABLE_HCA = 0x105, 120 MLX5_CMD_OP_QUERY_PAGES = 0x107, 121 MLX5_CMD_OP_MANAGE_PAGES = 0x108, 122 MLX5_CMD_OP_SET_HCA_CAP = 0x109, 123 MLX5_CMD_OP_QUERY_ISSI = 0x10a, 124 MLX5_CMD_OP_SET_ISSI = 0x10b, 125 MLX5_CMD_OP_SET_DRIVER_VERSION = 0x10d, 126 MLX5_CMD_OP_QUERY_SF_PARTITION = 0x111, 127 MLX5_CMD_OP_ALLOC_SF = 0x113, 128 MLX5_CMD_OP_DEALLOC_SF = 0x114, 129 MLX5_CMD_OP_CREATE_MKEY = 0x200, 130 MLX5_CMD_OP_QUERY_MKEY = 0x201, 131 MLX5_CMD_OP_DESTROY_MKEY = 0x202, 132 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203, 133 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204, 134 MLX5_CMD_OP_ALLOC_MEMIC = 0x205, 135 MLX5_CMD_OP_DEALLOC_MEMIC = 0x206, 136 MLX5_CMD_OP_CREATE_EQ = 0x301, 137 MLX5_CMD_OP_DESTROY_EQ = 0x302, 138 MLX5_CMD_OP_QUERY_EQ = 0x303, 139 MLX5_CMD_OP_GEN_EQE = 0x304, 140 MLX5_CMD_OP_CREATE_CQ = 0x400, 141 MLX5_CMD_OP_DESTROY_CQ = 0x401, 142 MLX5_CMD_OP_QUERY_CQ = 0x402, 143 MLX5_CMD_OP_MODIFY_CQ = 0x403, 144 MLX5_CMD_OP_CREATE_QP = 0x500, 145 MLX5_CMD_OP_DESTROY_QP = 0x501, 146 MLX5_CMD_OP_RST2INIT_QP = 0x502, 147 MLX5_CMD_OP_INIT2RTR_QP = 0x503, 148 MLX5_CMD_OP_RTR2RTS_QP = 0x504, 149 MLX5_CMD_OP_RTS2RTS_QP = 0x505, 150 MLX5_CMD_OP_SQERR2RTS_QP = 0x506, 151 MLX5_CMD_OP_2ERR_QP = 0x507, 152 MLX5_CMD_OP_2RST_QP = 0x50a, 153 MLX5_CMD_OP_QUERY_QP = 0x50b, 154 MLX5_CMD_OP_SQD_RTS_QP = 0x50c, 155 MLX5_CMD_OP_INIT2INIT_QP = 0x50e, 156 MLX5_CMD_OP_CREATE_PSV = 0x600, 157 MLX5_CMD_OP_DESTROY_PSV = 0x601, 158 MLX5_CMD_OP_CREATE_SRQ = 0x700, 159 MLX5_CMD_OP_DESTROY_SRQ = 0x701, 160 MLX5_CMD_OP_QUERY_SRQ = 0x702, 161 MLX5_CMD_OP_ARM_RQ = 0x703, 162 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705, 163 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706, 164 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707, 165 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708, 166 MLX5_CMD_OP_CREATE_DCT = 0x710, 167 MLX5_CMD_OP_DESTROY_DCT = 0x711, 168 MLX5_CMD_OP_DRAIN_DCT = 0x712, 169 MLX5_CMD_OP_QUERY_DCT = 0x713, 170 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714, 171 MLX5_CMD_OP_CREATE_XRQ = 0x717, 172 MLX5_CMD_OP_DESTROY_XRQ = 0x718, 173 MLX5_CMD_OP_QUERY_XRQ = 0x719, 174 MLX5_CMD_OP_ARM_XRQ = 0x71a, 175 MLX5_CMD_OP_QUERY_XRQ_DC_PARAMS_ENTRY = 0x725, 176 MLX5_CMD_OP_SET_XRQ_DC_PARAMS_ENTRY = 0x726, 177 MLX5_CMD_OP_QUERY_XRQ_ERROR_PARAMS = 0x727, 178 MLX5_CMD_OP_RELEASE_XRQ_ERROR = 0x729, 179 MLX5_CMD_OP_MODIFY_XRQ = 0x72a, 180 MLX5_CMD_OP_QUERY_ESW_FUNCTIONS = 0x740, 181 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750, 182 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751, 183 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752, 184 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753, 185 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754, 186 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755, 187 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760, 188 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761, 189 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762, 190 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763, 191 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764, 192 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765, 193 MLX5_CMD_OP_QUERY_VNIC_ENV = 0x76f, 194 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770, 195 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771, 196 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772, 197 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773, 198 MLX5_CMD_OP_SET_MONITOR_COUNTER = 0x774, 199 MLX5_CMD_OP_ARM_MONITOR_COUNTER = 0x775, 200 MLX5_CMD_OP_SET_PP_RATE_LIMIT = 0x780, 201 MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781, 202 MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT = 0x782, 203 MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT = 0x783, 204 MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT = 0x784, 205 MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT = 0x785, 206 MLX5_CMD_OP_CREATE_QOS_PARA_VPORT = 0x786, 207 MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT = 0x787, 208 MLX5_CMD_OP_ALLOC_PD = 0x800, 209 MLX5_CMD_OP_DEALLOC_PD = 0x801, 210 MLX5_CMD_OP_ALLOC_UAR = 0x802, 211 MLX5_CMD_OP_DEALLOC_UAR = 0x803, 212 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804, 213 MLX5_CMD_OP_ACCESS_REG = 0x805, 214 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806, 215 MLX5_CMD_OP_DETACH_FROM_MCG = 0x807, 216 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a, 217 MLX5_CMD_OP_MAD_IFC = 0x50d, 218 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b, 219 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c, 220 MLX5_CMD_OP_NOP = 0x80d, 221 MLX5_CMD_OP_ALLOC_XRCD = 0x80e, 222 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f, 223 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816, 224 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817, 225 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822, 226 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823, 227 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824, 228 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825, 229 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826, 230 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827, 231 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828, 232 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829, 233 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a, 234 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b, 235 MLX5_CMD_OP_SET_WOL_ROL = 0x830, 236 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831, 237 MLX5_CMD_OP_CREATE_LAG = 0x840, 238 MLX5_CMD_OP_MODIFY_LAG = 0x841, 239 MLX5_CMD_OP_QUERY_LAG = 0x842, 240 MLX5_CMD_OP_DESTROY_LAG = 0x843, 241 MLX5_CMD_OP_CREATE_VPORT_LAG = 0x844, 242 MLX5_CMD_OP_DESTROY_VPORT_LAG = 0x845, 243 MLX5_CMD_OP_CREATE_TIR = 0x900, 244 MLX5_CMD_OP_MODIFY_TIR = 0x901, 245 MLX5_CMD_OP_DESTROY_TIR = 0x902, 246 MLX5_CMD_OP_QUERY_TIR = 0x903, 247 MLX5_CMD_OP_CREATE_SQ = 0x904, 248 MLX5_CMD_OP_MODIFY_SQ = 0x905, 249 MLX5_CMD_OP_DESTROY_SQ = 0x906, 250 MLX5_CMD_OP_QUERY_SQ = 0x907, 251 MLX5_CMD_OP_CREATE_RQ = 0x908, 252 MLX5_CMD_OP_MODIFY_RQ = 0x909, 253 MLX5_CMD_OP_SET_DELAY_DROP_PARAMS = 0x910, 254 MLX5_CMD_OP_DESTROY_RQ = 0x90a, 255 MLX5_CMD_OP_QUERY_RQ = 0x90b, 256 MLX5_CMD_OP_CREATE_RMP = 0x90c, 257 MLX5_CMD_OP_MODIFY_RMP = 0x90d, 258 MLX5_CMD_OP_DESTROY_RMP = 0x90e, 259 MLX5_CMD_OP_QUERY_RMP = 0x90f, 260 MLX5_CMD_OP_CREATE_TIS = 0x912, 261 MLX5_CMD_OP_MODIFY_TIS = 0x913, 262 MLX5_CMD_OP_DESTROY_TIS = 0x914, 263 MLX5_CMD_OP_QUERY_TIS = 0x915, 264 MLX5_CMD_OP_CREATE_RQT = 0x916, 265 MLX5_CMD_OP_MODIFY_RQT = 0x917, 266 MLX5_CMD_OP_DESTROY_RQT = 0x918, 267 MLX5_CMD_OP_QUERY_RQT = 0x919, 268 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f, 269 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930, 270 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931, 271 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932, 272 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933, 273 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934, 274 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935, 275 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936, 276 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937, 277 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938, 278 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939, 279 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a, 280 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b, 281 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c, 282 MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT = 0x93d, 283 MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT = 0x93e, 284 MLX5_CMD_OP_QUERY_PACKET_REFORMAT_CONTEXT = 0x93f, 285 MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT = 0x940, 286 MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941, 287 MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT = 0x942, 288 MLX5_CMD_OP_FPGA_CREATE_QP = 0x960, 289 MLX5_CMD_OP_FPGA_MODIFY_QP = 0x961, 290 MLX5_CMD_OP_FPGA_QUERY_QP = 0x962, 291 MLX5_CMD_OP_FPGA_DESTROY_QP = 0x963, 292 MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS = 0x964, 293 MLX5_CMD_OP_CREATE_GENERAL_OBJECT = 0xa00, 294 MLX5_CMD_OP_MODIFY_GENERAL_OBJECT = 0xa01, 295 MLX5_CMD_OP_QUERY_GENERAL_OBJECT = 0xa02, 296 MLX5_CMD_OP_DESTROY_GENERAL_OBJECT = 0xa03, 297 MLX5_CMD_OP_CREATE_UCTX = 0xa04, 298 MLX5_CMD_OP_DESTROY_UCTX = 0xa06, 299 MLX5_CMD_OP_CREATE_UMEM = 0xa08, 300 MLX5_CMD_OP_DESTROY_UMEM = 0xa0a, 301 MLX5_CMD_OP_SYNC_STEERING = 0xb00, 302 MLX5_CMD_OP_QUERY_VHCA_STATE = 0xb0d, 303 MLX5_CMD_OP_MODIFY_VHCA_STATE = 0xb0e, 304 MLX5_CMD_OP_MAX 305 }; 306 307 /* Valid range for general commands that don't work over an object */ 308 enum { 309 MLX5_CMD_OP_GENERAL_START = 0xb00, 310 MLX5_CMD_OP_GENERAL_END = 0xd00, 311 }; 312 313 struct mlx5_ifc_flow_table_fields_supported_bits { 314 u8 outer_dmac[0x1]; 315 u8 outer_smac[0x1]; 316 u8 outer_ether_type[0x1]; 317 u8 outer_ip_version[0x1]; 318 u8 outer_first_prio[0x1]; 319 u8 outer_first_cfi[0x1]; 320 u8 outer_first_vid[0x1]; 321 u8 outer_ipv4_ttl[0x1]; 322 u8 outer_second_prio[0x1]; 323 u8 outer_second_cfi[0x1]; 324 u8 outer_second_vid[0x1]; 325 u8 reserved_at_b[0x1]; 326 u8 outer_sip[0x1]; 327 u8 outer_dip[0x1]; 328 u8 outer_frag[0x1]; 329 u8 outer_ip_protocol[0x1]; 330 u8 outer_ip_ecn[0x1]; 331 u8 outer_ip_dscp[0x1]; 332 u8 outer_udp_sport[0x1]; 333 u8 outer_udp_dport[0x1]; 334 u8 outer_tcp_sport[0x1]; 335 u8 outer_tcp_dport[0x1]; 336 u8 outer_tcp_flags[0x1]; 337 u8 outer_gre_protocol[0x1]; 338 u8 outer_gre_key[0x1]; 339 u8 outer_vxlan_vni[0x1]; 340 u8 outer_geneve_vni[0x1]; 341 u8 outer_geneve_oam[0x1]; 342 u8 outer_geneve_protocol_type[0x1]; 343 u8 outer_geneve_opt_len[0x1]; 344 u8 reserved_at_1e[0x1]; 345 u8 source_eswitch_port[0x1]; 346 347 u8 inner_dmac[0x1]; 348 u8 inner_smac[0x1]; 349 u8 inner_ether_type[0x1]; 350 u8 inner_ip_version[0x1]; 351 u8 inner_first_prio[0x1]; 352 u8 inner_first_cfi[0x1]; 353 u8 inner_first_vid[0x1]; 354 u8 reserved_at_27[0x1]; 355 u8 inner_second_prio[0x1]; 356 u8 inner_second_cfi[0x1]; 357 u8 inner_second_vid[0x1]; 358 u8 reserved_at_2b[0x1]; 359 u8 inner_sip[0x1]; 360 u8 inner_dip[0x1]; 361 u8 inner_frag[0x1]; 362 u8 inner_ip_protocol[0x1]; 363 u8 inner_ip_ecn[0x1]; 364 u8 inner_ip_dscp[0x1]; 365 u8 inner_udp_sport[0x1]; 366 u8 inner_udp_dport[0x1]; 367 u8 inner_tcp_sport[0x1]; 368 u8 inner_tcp_dport[0x1]; 369 u8 inner_tcp_flags[0x1]; 370 u8 reserved_at_37[0x9]; 371 372 u8 geneve_tlv_option_0_data[0x1]; 373 u8 reserved_at_41[0x4]; 374 u8 outer_first_mpls_over_udp[0x4]; 375 u8 outer_first_mpls_over_gre[0x4]; 376 u8 inner_first_mpls[0x4]; 377 u8 outer_first_mpls[0x4]; 378 u8 reserved_at_55[0x2]; 379 u8 outer_esp_spi[0x1]; 380 u8 reserved_at_58[0x2]; 381 u8 bth_dst_qp[0x1]; 382 u8 reserved_at_5b[0x5]; 383 384 u8 reserved_at_60[0x18]; 385 u8 metadata_reg_c_7[0x1]; 386 u8 metadata_reg_c_6[0x1]; 387 u8 metadata_reg_c_5[0x1]; 388 u8 metadata_reg_c_4[0x1]; 389 u8 metadata_reg_c_3[0x1]; 390 u8 metadata_reg_c_2[0x1]; 391 u8 metadata_reg_c_1[0x1]; 392 u8 metadata_reg_c_0[0x1]; 393 }; 394 395 struct mlx5_ifc_flow_table_prop_layout_bits { 396 u8 ft_support[0x1]; 397 u8 reserved_at_1[0x1]; 398 u8 flow_counter[0x1]; 399 u8 flow_modify_en[0x1]; 400 u8 modify_root[0x1]; 401 u8 identified_miss_table_mode[0x1]; 402 u8 flow_table_modify[0x1]; 403 u8 reformat[0x1]; 404 u8 decap[0x1]; 405 u8 reserved_at_9[0x1]; 406 u8 pop_vlan[0x1]; 407 u8 push_vlan[0x1]; 408 u8 reserved_at_c[0x1]; 409 u8 pop_vlan_2[0x1]; 410 u8 push_vlan_2[0x1]; 411 u8 reformat_and_vlan_action[0x1]; 412 u8 reserved_at_10[0x1]; 413 u8 sw_owner[0x1]; 414 u8 reformat_l3_tunnel_to_l2[0x1]; 415 u8 reformat_l2_to_l3_tunnel[0x1]; 416 u8 reformat_and_modify_action[0x1]; 417 u8 ignore_flow_level[0x1]; 418 u8 reserved_at_16[0x1]; 419 u8 table_miss_action_domain[0x1]; 420 u8 termination_table[0x1]; 421 u8 reformat_and_fwd_to_table[0x1]; 422 u8 reserved_at_1a[0x2]; 423 u8 ipsec_encrypt[0x1]; 424 u8 ipsec_decrypt[0x1]; 425 u8 sw_owner_v2[0x1]; 426 u8 reserved_at_1f[0x1]; 427 428 u8 termination_table_raw_traffic[0x1]; 429 u8 reserved_at_21[0x1]; 430 u8 log_max_ft_size[0x6]; 431 u8 log_max_modify_header_context[0x8]; 432 u8 max_modify_header_actions[0x8]; 433 u8 max_ft_level[0x8]; 434 435 u8 reserved_at_40[0x20]; 436 437 u8 reserved_at_60[0x18]; 438 u8 log_max_ft_num[0x8]; 439 440 u8 reserved_at_80[0x18]; 441 u8 log_max_destination[0x8]; 442 443 u8 log_max_flow_counter[0x8]; 444 u8 reserved_at_a8[0x10]; 445 u8 log_max_flow[0x8]; 446 447 u8 reserved_at_c0[0x40]; 448 449 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support; 450 451 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support; 452 }; 453 454 struct mlx5_ifc_odp_per_transport_service_cap_bits { 455 u8 send[0x1]; 456 u8 receive[0x1]; 457 u8 write[0x1]; 458 u8 read[0x1]; 459 u8 atomic[0x1]; 460 u8 srq_receive[0x1]; 461 u8 reserved_at_6[0x1a]; 462 }; 463 464 struct mlx5_ifc_fte_match_set_lyr_2_4_bits { 465 u8 smac_47_16[0x20]; 466 467 u8 smac_15_0[0x10]; 468 u8 ethertype[0x10]; 469 470 u8 dmac_47_16[0x20]; 471 472 u8 dmac_15_0[0x10]; 473 u8 first_prio[0x3]; 474 u8 first_cfi[0x1]; 475 u8 first_vid[0xc]; 476 477 u8 ip_protocol[0x8]; 478 u8 ip_dscp[0x6]; 479 u8 ip_ecn[0x2]; 480 u8 cvlan_tag[0x1]; 481 u8 svlan_tag[0x1]; 482 u8 frag[0x1]; 483 u8 ip_version[0x4]; 484 u8 tcp_flags[0x9]; 485 486 u8 tcp_sport[0x10]; 487 u8 tcp_dport[0x10]; 488 489 u8 reserved_at_c0[0x18]; 490 u8 ttl_hoplimit[0x8]; 491 492 u8 udp_sport[0x10]; 493 u8 udp_dport[0x10]; 494 495 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6; 496 497 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6; 498 }; 499 500 struct mlx5_ifc_nvgre_key_bits { 501 u8 hi[0x18]; 502 u8 lo[0x8]; 503 }; 504 505 union mlx5_ifc_gre_key_bits { 506 struct mlx5_ifc_nvgre_key_bits nvgre; 507 u8 key[0x20]; 508 }; 509 510 struct mlx5_ifc_fte_match_set_misc_bits { 511 u8 gre_c_present[0x1]; 512 u8 reserved_at_1[0x1]; 513 u8 gre_k_present[0x1]; 514 u8 gre_s_present[0x1]; 515 u8 source_vhca_port[0x4]; 516 u8 source_sqn[0x18]; 517 518 u8 source_eswitch_owner_vhca_id[0x10]; 519 u8 source_port[0x10]; 520 521 u8 outer_second_prio[0x3]; 522 u8 outer_second_cfi[0x1]; 523 u8 outer_second_vid[0xc]; 524 u8 inner_second_prio[0x3]; 525 u8 inner_second_cfi[0x1]; 526 u8 inner_second_vid[0xc]; 527 528 u8 outer_second_cvlan_tag[0x1]; 529 u8 inner_second_cvlan_tag[0x1]; 530 u8 outer_second_svlan_tag[0x1]; 531 u8 inner_second_svlan_tag[0x1]; 532 u8 reserved_at_64[0xc]; 533 u8 gre_protocol[0x10]; 534 535 union mlx5_ifc_gre_key_bits gre_key; 536 537 u8 vxlan_vni[0x18]; 538 u8 reserved_at_b8[0x8]; 539 540 u8 geneve_vni[0x18]; 541 u8 reserved_at_d8[0x7]; 542 u8 geneve_oam[0x1]; 543 544 u8 reserved_at_e0[0xc]; 545 u8 outer_ipv6_flow_label[0x14]; 546 547 u8 reserved_at_100[0xc]; 548 u8 inner_ipv6_flow_label[0x14]; 549 550 u8 reserved_at_120[0xa]; 551 u8 geneve_opt_len[0x6]; 552 u8 geneve_protocol_type[0x10]; 553 554 u8 reserved_at_140[0x8]; 555 u8 bth_dst_qp[0x18]; 556 u8 reserved_at_160[0x20]; 557 u8 outer_esp_spi[0x20]; 558 u8 reserved_at_1a0[0x60]; 559 }; 560 561 struct mlx5_ifc_fte_match_mpls_bits { 562 u8 mpls_label[0x14]; 563 u8 mpls_exp[0x3]; 564 u8 mpls_s_bos[0x1]; 565 u8 mpls_ttl[0x8]; 566 }; 567 568 struct mlx5_ifc_fte_match_set_misc2_bits { 569 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls; 570 571 struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls; 572 573 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre; 574 575 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp; 576 577 u8 metadata_reg_c_7[0x20]; 578 579 u8 metadata_reg_c_6[0x20]; 580 581 u8 metadata_reg_c_5[0x20]; 582 583 u8 metadata_reg_c_4[0x20]; 584 585 u8 metadata_reg_c_3[0x20]; 586 587 u8 metadata_reg_c_2[0x20]; 588 589 u8 metadata_reg_c_1[0x20]; 590 591 u8 metadata_reg_c_0[0x20]; 592 593 u8 metadata_reg_a[0x20]; 594 595 u8 reserved_at_1a0[0x60]; 596 }; 597 598 struct mlx5_ifc_fte_match_set_misc3_bits { 599 u8 inner_tcp_seq_num[0x20]; 600 601 u8 outer_tcp_seq_num[0x20]; 602 603 u8 inner_tcp_ack_num[0x20]; 604 605 u8 outer_tcp_ack_num[0x20]; 606 607 u8 reserved_at_80[0x8]; 608 u8 outer_vxlan_gpe_vni[0x18]; 609 610 u8 outer_vxlan_gpe_next_protocol[0x8]; 611 u8 outer_vxlan_gpe_flags[0x8]; 612 u8 reserved_at_b0[0x10]; 613 614 u8 icmp_header_data[0x20]; 615 616 u8 icmpv6_header_data[0x20]; 617 618 u8 icmp_type[0x8]; 619 u8 icmp_code[0x8]; 620 u8 icmpv6_type[0x8]; 621 u8 icmpv6_code[0x8]; 622 623 u8 geneve_tlv_option_0_data[0x20]; 624 625 u8 reserved_at_140[0xc0]; 626 }; 627 628 struct mlx5_ifc_fte_match_set_misc4_bits { 629 u8 prog_sample_field_value_0[0x20]; 630 631 u8 prog_sample_field_id_0[0x20]; 632 633 u8 prog_sample_field_value_1[0x20]; 634 635 u8 prog_sample_field_id_1[0x20]; 636 637 u8 prog_sample_field_value_2[0x20]; 638 639 u8 prog_sample_field_id_2[0x20]; 640 641 u8 prog_sample_field_value_3[0x20]; 642 643 u8 prog_sample_field_id_3[0x20]; 644 645 u8 reserved_at_100[0x100]; 646 }; 647 648 struct mlx5_ifc_cmd_pas_bits { 649 u8 pa_h[0x20]; 650 651 u8 pa_l[0x14]; 652 u8 reserved_at_34[0xc]; 653 }; 654 655 struct mlx5_ifc_uint64_bits { 656 u8 hi[0x20]; 657 658 u8 lo[0x20]; 659 }; 660 661 enum { 662 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0, 663 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7, 664 MLX5_ADS_STAT_RATE_10GBPS = 0x8, 665 MLX5_ADS_STAT_RATE_30GBPS = 0x9, 666 MLX5_ADS_STAT_RATE_5GBPS = 0xa, 667 MLX5_ADS_STAT_RATE_20GBPS = 0xb, 668 MLX5_ADS_STAT_RATE_40GBPS = 0xc, 669 MLX5_ADS_STAT_RATE_60GBPS = 0xd, 670 MLX5_ADS_STAT_RATE_80GBPS = 0xe, 671 MLX5_ADS_STAT_RATE_120GBPS = 0xf, 672 }; 673 674 struct mlx5_ifc_ads_bits { 675 u8 fl[0x1]; 676 u8 free_ar[0x1]; 677 u8 reserved_at_2[0xe]; 678 u8 pkey_index[0x10]; 679 680 u8 reserved_at_20[0x8]; 681 u8 grh[0x1]; 682 u8 mlid[0x7]; 683 u8 rlid[0x10]; 684 685 u8 ack_timeout[0x5]; 686 u8 reserved_at_45[0x3]; 687 u8 src_addr_index[0x8]; 688 u8 reserved_at_50[0x4]; 689 u8 stat_rate[0x4]; 690 u8 hop_limit[0x8]; 691 692 u8 reserved_at_60[0x4]; 693 u8 tclass[0x8]; 694 u8 flow_label[0x14]; 695 696 u8 rgid_rip[16][0x8]; 697 698 u8 reserved_at_100[0x4]; 699 u8 f_dscp[0x1]; 700 u8 f_ecn[0x1]; 701 u8 reserved_at_106[0x1]; 702 u8 f_eth_prio[0x1]; 703 u8 ecn[0x2]; 704 u8 dscp[0x6]; 705 u8 udp_sport[0x10]; 706 707 u8 dei_cfi[0x1]; 708 u8 eth_prio[0x3]; 709 u8 sl[0x4]; 710 u8 vhca_port_num[0x8]; 711 u8 rmac_47_32[0x10]; 712 713 u8 rmac_31_0[0x20]; 714 }; 715 716 struct mlx5_ifc_flow_table_nic_cap_bits { 717 u8 nic_rx_multi_path_tirs[0x1]; 718 u8 nic_rx_multi_path_tirs_fts[0x1]; 719 u8 allow_sniffer_and_nic_rx_shared_tir[0x1]; 720 u8 reserved_at_3[0x4]; 721 u8 sw_owner_reformat_supported[0x1]; 722 u8 reserved_at_8[0x18]; 723 724 u8 encap_general_header[0x1]; 725 u8 reserved_at_21[0xa]; 726 u8 log_max_packet_reformat_context[0x5]; 727 u8 reserved_at_30[0x6]; 728 u8 max_encap_header_size[0xa]; 729 u8 reserved_at_40[0x1c0]; 730 731 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive; 732 733 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_rdma; 734 735 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer; 736 737 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit; 738 739 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_rdma; 740 741 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer; 742 743 u8 reserved_at_e00[0x1200]; 744 745 u8 sw_steering_nic_rx_action_drop_icm_address[0x40]; 746 747 u8 sw_steering_nic_tx_action_drop_icm_address[0x40]; 748 749 u8 sw_steering_nic_tx_action_allow_icm_address[0x40]; 750 751 u8 reserved_at_20c0[0x5f40]; 752 }; 753 754 enum { 755 MLX5_FDB_TO_VPORT_REG_C_0 = 0x01, 756 MLX5_FDB_TO_VPORT_REG_C_1 = 0x02, 757 MLX5_FDB_TO_VPORT_REG_C_2 = 0x04, 758 MLX5_FDB_TO_VPORT_REG_C_3 = 0x08, 759 MLX5_FDB_TO_VPORT_REG_C_4 = 0x10, 760 MLX5_FDB_TO_VPORT_REG_C_5 = 0x20, 761 MLX5_FDB_TO_VPORT_REG_C_6 = 0x40, 762 MLX5_FDB_TO_VPORT_REG_C_7 = 0x80, 763 }; 764 765 struct mlx5_ifc_flow_table_eswitch_cap_bits { 766 u8 fdb_to_vport_reg_c_id[0x8]; 767 u8 reserved_at_8[0xd]; 768 u8 fdb_modify_header_fwd_to_table[0x1]; 769 u8 reserved_at_16[0x1]; 770 u8 flow_source[0x1]; 771 u8 reserved_at_18[0x2]; 772 u8 multi_fdb_encap[0x1]; 773 u8 egress_acl_forward_to_vport[0x1]; 774 u8 fdb_multi_path_to_table[0x1]; 775 u8 reserved_at_1d[0x3]; 776 777 u8 reserved_at_20[0x1e0]; 778 779 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb; 780 781 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress; 782 783 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress; 784 785 u8 reserved_at_800[0x1000]; 786 787 u8 sw_steering_fdb_action_drop_icm_address_rx[0x40]; 788 789 u8 sw_steering_fdb_action_drop_icm_address_tx[0x40]; 790 791 u8 sw_steering_uplink_icm_address_rx[0x40]; 792 793 u8 sw_steering_uplink_icm_address_tx[0x40]; 794 795 u8 reserved_at_1900[0x6700]; 796 }; 797 798 enum { 799 MLX5_COUNTER_SOURCE_ESWITCH = 0x0, 800 MLX5_COUNTER_FLOW_ESWITCH = 0x1, 801 }; 802 803 struct mlx5_ifc_e_switch_cap_bits { 804 u8 vport_svlan_strip[0x1]; 805 u8 vport_cvlan_strip[0x1]; 806 u8 vport_svlan_insert[0x1]; 807 u8 vport_cvlan_insert_if_not_exist[0x1]; 808 u8 vport_cvlan_insert_overwrite[0x1]; 809 u8 reserved_at_5[0x3]; 810 u8 esw_uplink_ingress_acl[0x1]; 811 u8 reserved_at_9[0x10]; 812 u8 esw_functions_changed[0x1]; 813 u8 reserved_at_1a[0x1]; 814 u8 ecpf_vport_exists[0x1]; 815 u8 counter_eswitch_affinity[0x1]; 816 u8 merged_eswitch[0x1]; 817 u8 nic_vport_node_guid_modify[0x1]; 818 u8 nic_vport_port_guid_modify[0x1]; 819 820 u8 vxlan_encap_decap[0x1]; 821 u8 nvgre_encap_decap[0x1]; 822 u8 reserved_at_22[0x1]; 823 u8 log_max_fdb_encap_uplink[0x5]; 824 u8 reserved_at_21[0x3]; 825 u8 log_max_packet_reformat_context[0x5]; 826 u8 reserved_2b[0x6]; 827 u8 max_encap_header_size[0xa]; 828 829 u8 reserved_at_40[0xb]; 830 u8 log_max_esw_sf[0x5]; 831 u8 esw_sf_base_id[0x10]; 832 833 u8 reserved_at_60[0x7a0]; 834 835 }; 836 837 struct mlx5_ifc_qos_cap_bits { 838 u8 packet_pacing[0x1]; 839 u8 esw_scheduling[0x1]; 840 u8 esw_bw_share[0x1]; 841 u8 esw_rate_limit[0x1]; 842 u8 reserved_at_4[0x1]; 843 u8 packet_pacing_burst_bound[0x1]; 844 u8 packet_pacing_typical_size[0x1]; 845 u8 reserved_at_7[0x1]; 846 u8 nic_sq_scheduling[0x1]; 847 u8 nic_bw_share[0x1]; 848 u8 nic_rate_limit[0x1]; 849 u8 packet_pacing_uid[0x1]; 850 u8 reserved_at_c[0x14]; 851 852 u8 reserved_at_20[0xb]; 853 u8 log_max_qos_nic_queue_group[0x5]; 854 u8 reserved_at_30[0x10]; 855 856 u8 packet_pacing_max_rate[0x20]; 857 858 u8 packet_pacing_min_rate[0x20]; 859 860 u8 reserved_at_80[0x10]; 861 u8 packet_pacing_rate_table_size[0x10]; 862 863 u8 esw_element_type[0x10]; 864 u8 esw_tsar_type[0x10]; 865 866 u8 reserved_at_c0[0x10]; 867 u8 max_qos_para_vport[0x10]; 868 869 u8 max_tsar_bw_share[0x20]; 870 871 u8 reserved_at_100[0x700]; 872 }; 873 874 struct mlx5_ifc_debug_cap_bits { 875 u8 core_dump_general[0x1]; 876 u8 core_dump_qp[0x1]; 877 u8 reserved_at_2[0x7]; 878 u8 resource_dump[0x1]; 879 u8 reserved_at_a[0x16]; 880 881 u8 reserved_at_20[0x2]; 882 u8 stall_detect[0x1]; 883 u8 reserved_at_23[0x1d]; 884 885 u8 reserved_at_40[0x7c0]; 886 }; 887 888 struct mlx5_ifc_per_protocol_networking_offload_caps_bits { 889 u8 csum_cap[0x1]; 890 u8 vlan_cap[0x1]; 891 u8 lro_cap[0x1]; 892 u8 lro_psh_flag[0x1]; 893 u8 lro_time_stamp[0x1]; 894 u8 reserved_at_5[0x2]; 895 u8 wqe_vlan_insert[0x1]; 896 u8 self_lb_en_modifiable[0x1]; 897 u8 reserved_at_9[0x2]; 898 u8 max_lso_cap[0x5]; 899 u8 multi_pkt_send_wqe[0x2]; 900 u8 wqe_inline_mode[0x2]; 901 u8 rss_ind_tbl_cap[0x4]; 902 u8 reg_umr_sq[0x1]; 903 u8 scatter_fcs[0x1]; 904 u8 enhanced_multi_pkt_send_wqe[0x1]; 905 u8 tunnel_lso_const_out_ip_id[0x1]; 906 u8 reserved_at_1c[0x2]; 907 u8 tunnel_stateless_gre[0x1]; 908 u8 tunnel_stateless_vxlan[0x1]; 909 910 u8 swp[0x1]; 911 u8 swp_csum[0x1]; 912 u8 swp_lso[0x1]; 913 u8 cqe_checksum_full[0x1]; 914 u8 tunnel_stateless_geneve_tx[0x1]; 915 u8 tunnel_stateless_mpls_over_udp[0x1]; 916 u8 tunnel_stateless_mpls_over_gre[0x1]; 917 u8 tunnel_stateless_vxlan_gpe[0x1]; 918 u8 tunnel_stateless_ipv4_over_vxlan[0x1]; 919 u8 tunnel_stateless_ip_over_ip[0x1]; 920 u8 insert_trailer[0x1]; 921 u8 reserved_at_2b[0x1]; 922 u8 tunnel_stateless_ip_over_ip_rx[0x1]; 923 u8 tunnel_stateless_ip_over_ip_tx[0x1]; 924 u8 reserved_at_2e[0x2]; 925 u8 max_vxlan_udp_ports[0x8]; 926 u8 reserved_at_38[0x6]; 927 u8 max_geneve_opt_len[0x1]; 928 u8 tunnel_stateless_geneve_rx[0x1]; 929 930 u8 reserved_at_40[0x10]; 931 u8 lro_min_mss_size[0x10]; 932 933 u8 reserved_at_60[0x120]; 934 935 u8 lro_timer_supported_periods[4][0x20]; 936 937 u8 reserved_at_200[0x600]; 938 }; 939 940 struct mlx5_ifc_roce_cap_bits { 941 u8 roce_apm[0x1]; 942 u8 reserved_at_1[0x3]; 943 u8 sw_r_roce_src_udp_port[0x1]; 944 u8 reserved_at_5[0x1b]; 945 946 u8 reserved_at_20[0x60]; 947 948 u8 reserved_at_80[0xc]; 949 u8 l3_type[0x4]; 950 u8 reserved_at_90[0x8]; 951 u8 roce_version[0x8]; 952 953 u8 reserved_at_a0[0x10]; 954 u8 r_roce_dest_udp_port[0x10]; 955 956 u8 r_roce_max_src_udp_port[0x10]; 957 u8 r_roce_min_src_udp_port[0x10]; 958 959 u8 reserved_at_e0[0x10]; 960 u8 roce_address_table_size[0x10]; 961 962 u8 reserved_at_100[0x700]; 963 }; 964 965 struct mlx5_ifc_sync_steering_in_bits { 966 u8 opcode[0x10]; 967 u8 uid[0x10]; 968 969 u8 reserved_at_20[0x10]; 970 u8 op_mod[0x10]; 971 972 u8 reserved_at_40[0xc0]; 973 }; 974 975 struct mlx5_ifc_sync_steering_out_bits { 976 u8 status[0x8]; 977 u8 reserved_at_8[0x18]; 978 979 u8 syndrome[0x20]; 980 981 u8 reserved_at_40[0x40]; 982 }; 983 984 struct mlx5_ifc_device_mem_cap_bits { 985 u8 memic[0x1]; 986 u8 reserved_at_1[0x1f]; 987 988 u8 reserved_at_20[0xb]; 989 u8 log_min_memic_alloc_size[0x5]; 990 u8 reserved_at_30[0x8]; 991 u8 log_max_memic_addr_alignment[0x8]; 992 993 u8 memic_bar_start_addr[0x40]; 994 995 u8 memic_bar_size[0x20]; 996 997 u8 max_memic_size[0x20]; 998 999 u8 steering_sw_icm_start_address[0x40]; 1000 1001 u8 reserved_at_100[0x8]; 1002 u8 log_header_modify_sw_icm_size[0x8]; 1003 u8 reserved_at_110[0x2]; 1004 u8 log_sw_icm_alloc_granularity[0x6]; 1005 u8 log_steering_sw_icm_size[0x8]; 1006 1007 u8 reserved_at_120[0x20]; 1008 1009 u8 header_modify_sw_icm_start_address[0x40]; 1010 1011 u8 reserved_at_180[0x680]; 1012 }; 1013 1014 struct mlx5_ifc_device_event_cap_bits { 1015 u8 user_affiliated_events[4][0x40]; 1016 1017 u8 user_unaffiliated_events[4][0x40]; 1018 }; 1019 1020 struct mlx5_ifc_virtio_emulation_cap_bits { 1021 u8 desc_tunnel_offload_type[0x1]; 1022 u8 eth_frame_offload_type[0x1]; 1023 u8 virtio_version_1_0[0x1]; 1024 u8 device_features_bits_mask[0xd]; 1025 u8 event_mode[0x8]; 1026 u8 virtio_queue_type[0x8]; 1027 1028 u8 max_tunnel_desc[0x10]; 1029 u8 reserved_at_30[0x3]; 1030 u8 log_doorbell_stride[0x5]; 1031 u8 reserved_at_38[0x3]; 1032 u8 log_doorbell_bar_size[0x5]; 1033 1034 u8 doorbell_bar_offset[0x40]; 1035 1036 u8 max_emulated_devices[0x8]; 1037 u8 max_num_virtio_queues[0x18]; 1038 1039 u8 reserved_at_a0[0x60]; 1040 1041 u8 umem_1_buffer_param_a[0x20]; 1042 1043 u8 umem_1_buffer_param_b[0x20]; 1044 1045 u8 umem_2_buffer_param_a[0x20]; 1046 1047 u8 umem_2_buffer_param_b[0x20]; 1048 1049 u8 umem_3_buffer_param_a[0x20]; 1050 1051 u8 umem_3_buffer_param_b[0x20]; 1052 1053 u8 reserved_at_1c0[0x640]; 1054 }; 1055 1056 enum { 1057 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0, 1058 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2, 1059 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4, 1060 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8, 1061 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10, 1062 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20, 1063 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40, 1064 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80, 1065 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100, 1066 }; 1067 1068 enum { 1069 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1, 1070 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2, 1071 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4, 1072 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8, 1073 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10, 1074 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20, 1075 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40, 1076 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80, 1077 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100, 1078 }; 1079 1080 struct mlx5_ifc_atomic_caps_bits { 1081 u8 reserved_at_0[0x40]; 1082 1083 u8 atomic_req_8B_endianness_mode[0x2]; 1084 u8 reserved_at_42[0x4]; 1085 u8 supported_atomic_req_8B_endianness_mode_1[0x1]; 1086 1087 u8 reserved_at_47[0x19]; 1088 1089 u8 reserved_at_60[0x20]; 1090 1091 u8 reserved_at_80[0x10]; 1092 u8 atomic_operations[0x10]; 1093 1094 u8 reserved_at_a0[0x10]; 1095 u8 atomic_size_qp[0x10]; 1096 1097 u8 reserved_at_c0[0x10]; 1098 u8 atomic_size_dc[0x10]; 1099 1100 u8 reserved_at_e0[0x720]; 1101 }; 1102 1103 struct mlx5_ifc_odp_cap_bits { 1104 u8 reserved_at_0[0x40]; 1105 1106 u8 sig[0x1]; 1107 u8 reserved_at_41[0x1f]; 1108 1109 u8 reserved_at_60[0x20]; 1110 1111 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps; 1112 1113 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps; 1114 1115 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps; 1116 1117 struct mlx5_ifc_odp_per_transport_service_cap_bits xrc_odp_caps; 1118 1119 struct mlx5_ifc_odp_per_transport_service_cap_bits dc_odp_caps; 1120 1121 u8 reserved_at_120[0x6E0]; 1122 }; 1123 1124 struct mlx5_ifc_calc_op { 1125 u8 reserved_at_0[0x10]; 1126 u8 reserved_at_10[0x9]; 1127 u8 op_swap_endianness[0x1]; 1128 u8 op_min[0x1]; 1129 u8 op_xor[0x1]; 1130 u8 op_or[0x1]; 1131 u8 op_and[0x1]; 1132 u8 op_max[0x1]; 1133 u8 op_add[0x1]; 1134 }; 1135 1136 struct mlx5_ifc_vector_calc_cap_bits { 1137 u8 calc_matrix[0x1]; 1138 u8 reserved_at_1[0x1f]; 1139 u8 reserved_at_20[0x8]; 1140 u8 max_vec_count[0x8]; 1141 u8 reserved_at_30[0xd]; 1142 u8 max_chunk_size[0x3]; 1143 struct mlx5_ifc_calc_op calc0; 1144 struct mlx5_ifc_calc_op calc1; 1145 struct mlx5_ifc_calc_op calc2; 1146 struct mlx5_ifc_calc_op calc3; 1147 1148 u8 reserved_at_c0[0x720]; 1149 }; 1150 1151 struct mlx5_ifc_tls_cap_bits { 1152 u8 tls_1_2_aes_gcm_128[0x1]; 1153 u8 tls_1_3_aes_gcm_128[0x1]; 1154 u8 tls_1_2_aes_gcm_256[0x1]; 1155 u8 tls_1_3_aes_gcm_256[0x1]; 1156 u8 reserved_at_4[0x1c]; 1157 1158 u8 reserved_at_20[0x7e0]; 1159 }; 1160 1161 struct mlx5_ifc_ipsec_cap_bits { 1162 u8 ipsec_full_offload[0x1]; 1163 u8 ipsec_crypto_offload[0x1]; 1164 u8 ipsec_esn[0x1]; 1165 u8 ipsec_crypto_esp_aes_gcm_256_encrypt[0x1]; 1166 u8 ipsec_crypto_esp_aes_gcm_128_encrypt[0x1]; 1167 u8 ipsec_crypto_esp_aes_gcm_256_decrypt[0x1]; 1168 u8 ipsec_crypto_esp_aes_gcm_128_decrypt[0x1]; 1169 u8 reserved_at_7[0x4]; 1170 u8 log_max_ipsec_offload[0x5]; 1171 u8 reserved_at_10[0x10]; 1172 1173 u8 min_log_ipsec_full_replay_window[0x8]; 1174 u8 max_log_ipsec_full_replay_window[0x8]; 1175 u8 reserved_at_30[0x7d0]; 1176 }; 1177 1178 enum { 1179 MLX5_WQ_TYPE_LINKED_LIST = 0x0, 1180 MLX5_WQ_TYPE_CYCLIC = 0x1, 1181 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2, 1182 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3, 1183 }; 1184 1185 enum { 1186 MLX5_WQ_END_PAD_MODE_NONE = 0x0, 1187 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1, 1188 }; 1189 1190 enum { 1191 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0, 1192 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1, 1193 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2, 1194 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3, 1195 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4, 1196 }; 1197 1198 enum { 1199 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0, 1200 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1, 1201 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2, 1202 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3, 1203 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4, 1204 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5, 1205 }; 1206 1207 enum { 1208 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0, 1209 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1, 1210 }; 1211 1212 enum { 1213 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0, 1214 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1, 1215 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3, 1216 }; 1217 1218 enum { 1219 MLX5_CAP_PORT_TYPE_IB = 0x0, 1220 MLX5_CAP_PORT_TYPE_ETH = 0x1, 1221 }; 1222 1223 enum { 1224 MLX5_CAP_UMR_FENCE_STRONG = 0x0, 1225 MLX5_CAP_UMR_FENCE_SMALL = 0x1, 1226 MLX5_CAP_UMR_FENCE_NONE = 0x2, 1227 }; 1228 1229 enum { 1230 MLX5_FLEX_PARSER_GENEVE_ENABLED = 1 << 3, 1231 MLX5_FLEX_PARSER_VXLAN_GPE_ENABLED = 1 << 7, 1232 MLX5_FLEX_PARSER_ICMP_V4_ENABLED = 1 << 8, 1233 MLX5_FLEX_PARSER_ICMP_V6_ENABLED = 1 << 9, 1234 }; 1235 1236 enum { 1237 MLX5_UCTX_CAP_RAW_TX = 1UL << 0, 1238 MLX5_UCTX_CAP_INTERNAL_DEV_RES = 1UL << 1, 1239 }; 1240 1241 #define MLX5_FC_BULK_SIZE_FACTOR 128 1242 1243 enum mlx5_fc_bulk_alloc_bitmask { 1244 MLX5_FC_BULK_128 = (1 << 0), 1245 MLX5_FC_BULK_256 = (1 << 1), 1246 MLX5_FC_BULK_512 = (1 << 2), 1247 MLX5_FC_BULK_1024 = (1 << 3), 1248 MLX5_FC_BULK_2048 = (1 << 4), 1249 MLX5_FC_BULK_4096 = (1 << 5), 1250 MLX5_FC_BULK_8192 = (1 << 6), 1251 MLX5_FC_BULK_16384 = (1 << 7), 1252 }; 1253 1254 #define MLX5_FC_BULK_NUM_FCS(fc_enum) (MLX5_FC_BULK_SIZE_FACTOR * (fc_enum)) 1255 1256 enum { 1257 MLX5_STEERING_FORMAT_CONNECTX_5 = 0, 1258 MLX5_STEERING_FORMAT_CONNECTX_6DX = 1, 1259 }; 1260 1261 struct mlx5_ifc_cmd_hca_cap_bits { 1262 u8 reserved_at_0[0x1f]; 1263 u8 vhca_resource_manager[0x1]; 1264 1265 u8 reserved_at_20[0x3]; 1266 u8 event_on_vhca_state_teardown_request[0x1]; 1267 u8 event_on_vhca_state_in_use[0x1]; 1268 u8 event_on_vhca_state_active[0x1]; 1269 u8 event_on_vhca_state_allocated[0x1]; 1270 u8 event_on_vhca_state_invalid[0x1]; 1271 u8 reserved_at_28[0x8]; 1272 u8 vhca_id[0x10]; 1273 1274 u8 reserved_at_40[0x40]; 1275 1276 u8 log_max_srq_sz[0x8]; 1277 u8 log_max_qp_sz[0x8]; 1278 u8 event_cap[0x1]; 1279 u8 reserved_at_91[0x7]; 1280 u8 prio_tag_required[0x1]; 1281 u8 reserved_at_99[0x2]; 1282 u8 log_max_qp[0x5]; 1283 1284 u8 reserved_at_a0[0x3]; 1285 u8 ece_support[0x1]; 1286 u8 reserved_at_a4[0x5]; 1287 u8 reg_c_preserve[0x1]; 1288 u8 reserved_at_aa[0x1]; 1289 u8 log_max_srq[0x5]; 1290 u8 reserved_at_b0[0x1]; 1291 u8 uplink_follow[0x1]; 1292 u8 ts_cqe_to_dest_cqn[0x1]; 1293 u8 reserved_at_b3[0xd]; 1294 1295 u8 max_sgl_for_optimized_performance[0x8]; 1296 u8 log_max_cq_sz[0x8]; 1297 u8 relaxed_ordering_write_umr[0x1]; 1298 u8 relaxed_ordering_read_umr[0x1]; 1299 u8 reserved_at_d2[0x7]; 1300 u8 virtio_net_device_emualtion_manager[0x1]; 1301 u8 virtio_blk_device_emualtion_manager[0x1]; 1302 u8 log_max_cq[0x5]; 1303 1304 u8 log_max_eq_sz[0x8]; 1305 u8 relaxed_ordering_write[0x1]; 1306 u8 relaxed_ordering_read[0x1]; 1307 u8 log_max_mkey[0x6]; 1308 u8 reserved_at_f0[0x8]; 1309 u8 dump_fill_mkey[0x1]; 1310 u8 reserved_at_f9[0x2]; 1311 u8 fast_teardown[0x1]; 1312 u8 log_max_eq[0x4]; 1313 1314 u8 max_indirection[0x8]; 1315 u8 fixed_buffer_size[0x1]; 1316 u8 log_max_mrw_sz[0x7]; 1317 u8 force_teardown[0x1]; 1318 u8 reserved_at_111[0x1]; 1319 u8 log_max_bsf_list_size[0x6]; 1320 u8 umr_extended_translation_offset[0x1]; 1321 u8 null_mkey[0x1]; 1322 u8 log_max_klm_list_size[0x6]; 1323 1324 u8 reserved_at_120[0xa]; 1325 u8 log_max_ra_req_dc[0x6]; 1326 u8 reserved_at_130[0xa]; 1327 u8 log_max_ra_res_dc[0x6]; 1328 1329 u8 reserved_at_140[0x6]; 1330 u8 release_all_pages[0x1]; 1331 u8 reserved_at_147[0x2]; 1332 u8 roce_accl[0x1]; 1333 u8 log_max_ra_req_qp[0x6]; 1334 u8 reserved_at_150[0xa]; 1335 u8 log_max_ra_res_qp[0x6]; 1336 1337 u8 end_pad[0x1]; 1338 u8 cc_query_allowed[0x1]; 1339 u8 cc_modify_allowed[0x1]; 1340 u8 start_pad[0x1]; 1341 u8 cache_line_128byte[0x1]; 1342 u8 reserved_at_165[0x4]; 1343 u8 rts2rts_qp_counters_set_id[0x1]; 1344 u8 reserved_at_16a[0x2]; 1345 u8 vnic_env_int_rq_oob[0x1]; 1346 u8 sbcam_reg[0x1]; 1347 u8 reserved_at_16e[0x1]; 1348 u8 qcam_reg[0x1]; 1349 u8 gid_table_size[0x10]; 1350 1351 u8 out_of_seq_cnt[0x1]; 1352 u8 vport_counters[0x1]; 1353 u8 retransmission_q_counters[0x1]; 1354 u8 debug[0x1]; 1355 u8 modify_rq_counter_set_id[0x1]; 1356 u8 rq_delay_drop[0x1]; 1357 u8 max_qp_cnt[0xa]; 1358 u8 pkey_table_size[0x10]; 1359 1360 u8 vport_group_manager[0x1]; 1361 u8 vhca_group_manager[0x1]; 1362 u8 ib_virt[0x1]; 1363 u8 eth_virt[0x1]; 1364 u8 vnic_env_queue_counters[0x1]; 1365 u8 ets[0x1]; 1366 u8 nic_flow_table[0x1]; 1367 u8 eswitch_manager[0x1]; 1368 u8 device_memory[0x1]; 1369 u8 mcam_reg[0x1]; 1370 u8 pcam_reg[0x1]; 1371 u8 local_ca_ack_delay[0x5]; 1372 u8 port_module_event[0x1]; 1373 u8 enhanced_error_q_counters[0x1]; 1374 u8 ports_check[0x1]; 1375 u8 reserved_at_1b3[0x1]; 1376 u8 disable_link_up[0x1]; 1377 u8 beacon_led[0x1]; 1378 u8 port_type[0x2]; 1379 u8 num_ports[0x8]; 1380 1381 u8 reserved_at_1c0[0x1]; 1382 u8 pps[0x1]; 1383 u8 pps_modify[0x1]; 1384 u8 log_max_msg[0x5]; 1385 u8 reserved_at_1c8[0x4]; 1386 u8 max_tc[0x4]; 1387 u8 temp_warn_event[0x1]; 1388 u8 dcbx[0x1]; 1389 u8 general_notification_event[0x1]; 1390 u8 reserved_at_1d3[0x2]; 1391 u8 fpga[0x1]; 1392 u8 rol_s[0x1]; 1393 u8 rol_g[0x1]; 1394 u8 reserved_at_1d8[0x1]; 1395 u8 wol_s[0x1]; 1396 u8 wol_g[0x1]; 1397 u8 wol_a[0x1]; 1398 u8 wol_b[0x1]; 1399 u8 wol_m[0x1]; 1400 u8 wol_u[0x1]; 1401 u8 wol_p[0x1]; 1402 1403 u8 stat_rate_support[0x10]; 1404 u8 reserved_at_1f0[0x1]; 1405 u8 pci_sync_for_fw_update_event[0x1]; 1406 u8 reserved_at_1f2[0x6]; 1407 u8 init2_lag_tx_port_affinity[0x1]; 1408 u8 reserved_at_1fa[0x3]; 1409 u8 cqe_version[0x4]; 1410 1411 u8 compact_address_vector[0x1]; 1412 u8 striding_rq[0x1]; 1413 u8 reserved_at_202[0x1]; 1414 u8 ipoib_enhanced_offloads[0x1]; 1415 u8 ipoib_basic_offloads[0x1]; 1416 u8 reserved_at_205[0x1]; 1417 u8 repeated_block_disabled[0x1]; 1418 u8 umr_modify_entity_size_disabled[0x1]; 1419 u8 umr_modify_atomic_disabled[0x1]; 1420 u8 umr_indirect_mkey_disabled[0x1]; 1421 u8 umr_fence[0x2]; 1422 u8 dc_req_scat_data_cqe[0x1]; 1423 u8 reserved_at_20d[0x2]; 1424 u8 drain_sigerr[0x1]; 1425 u8 cmdif_checksum[0x2]; 1426 u8 sigerr_cqe[0x1]; 1427 u8 reserved_at_213[0x1]; 1428 u8 wq_signature[0x1]; 1429 u8 sctr_data_cqe[0x1]; 1430 u8 reserved_at_216[0x1]; 1431 u8 sho[0x1]; 1432 u8 tph[0x1]; 1433 u8 rf[0x1]; 1434 u8 dct[0x1]; 1435 u8 qos[0x1]; 1436 u8 eth_net_offloads[0x1]; 1437 u8 roce[0x1]; 1438 u8 atomic[0x1]; 1439 u8 reserved_at_21f[0x1]; 1440 1441 u8 cq_oi[0x1]; 1442 u8 cq_resize[0x1]; 1443 u8 cq_moderation[0x1]; 1444 u8 reserved_at_223[0x3]; 1445 u8 cq_eq_remap[0x1]; 1446 u8 pg[0x1]; 1447 u8 block_lb_mc[0x1]; 1448 u8 reserved_at_229[0x1]; 1449 u8 scqe_break_moderation[0x1]; 1450 u8 cq_period_start_from_cqe[0x1]; 1451 u8 cd[0x1]; 1452 u8 reserved_at_22d[0x1]; 1453 u8 apm[0x1]; 1454 u8 vector_calc[0x1]; 1455 u8 umr_ptr_rlky[0x1]; 1456 u8 imaicl[0x1]; 1457 u8 qp_packet_based[0x1]; 1458 u8 reserved_at_233[0x3]; 1459 u8 qkv[0x1]; 1460 u8 pkv[0x1]; 1461 u8 set_deth_sqpn[0x1]; 1462 u8 reserved_at_239[0x3]; 1463 u8 xrc[0x1]; 1464 u8 ud[0x1]; 1465 u8 uc[0x1]; 1466 u8 rc[0x1]; 1467 1468 u8 uar_4k[0x1]; 1469 u8 reserved_at_241[0x9]; 1470 u8 uar_sz[0x6]; 1471 u8 reserved_at_250[0x8]; 1472 u8 log_pg_sz[0x8]; 1473 1474 u8 bf[0x1]; 1475 u8 driver_version[0x1]; 1476 u8 pad_tx_eth_packet[0x1]; 1477 u8 reserved_at_263[0x3]; 1478 u8 mkey_by_name[0x1]; 1479 u8 reserved_at_267[0x4]; 1480 1481 u8 log_bf_reg_size[0x5]; 1482 1483 u8 reserved_at_270[0x6]; 1484 u8 lag_dct[0x2]; 1485 u8 lag_tx_port_affinity[0x1]; 1486 u8 reserved_at_279[0x2]; 1487 u8 lag_master[0x1]; 1488 u8 num_lag_ports[0x4]; 1489 1490 u8 reserved_at_280[0x10]; 1491 u8 max_wqe_sz_sq[0x10]; 1492 1493 u8 reserved_at_2a0[0x10]; 1494 u8 max_wqe_sz_rq[0x10]; 1495 1496 u8 max_flow_counter_31_16[0x10]; 1497 u8 max_wqe_sz_sq_dc[0x10]; 1498 1499 u8 reserved_at_2e0[0x7]; 1500 u8 max_qp_mcg[0x19]; 1501 1502 u8 reserved_at_300[0x10]; 1503 u8 flow_counter_bulk_alloc[0x8]; 1504 u8 log_max_mcg[0x8]; 1505 1506 u8 reserved_at_320[0x3]; 1507 u8 log_max_transport_domain[0x5]; 1508 u8 reserved_at_328[0x3]; 1509 u8 log_max_pd[0x5]; 1510 u8 reserved_at_330[0xb]; 1511 u8 log_max_xrcd[0x5]; 1512 1513 u8 nic_receive_steering_discard[0x1]; 1514 u8 receive_discard_vport_down[0x1]; 1515 u8 transmit_discard_vport_down[0x1]; 1516 u8 reserved_at_343[0x5]; 1517 u8 log_max_flow_counter_bulk[0x8]; 1518 u8 max_flow_counter_15_0[0x10]; 1519 1520 1521 u8 reserved_at_360[0x3]; 1522 u8 log_max_rq[0x5]; 1523 u8 reserved_at_368[0x3]; 1524 u8 log_max_sq[0x5]; 1525 u8 reserved_at_370[0x3]; 1526 u8 log_max_tir[0x5]; 1527 u8 reserved_at_378[0x3]; 1528 u8 log_max_tis[0x5]; 1529 1530 u8 basic_cyclic_rcv_wqe[0x1]; 1531 u8 reserved_at_381[0x2]; 1532 u8 log_max_rmp[0x5]; 1533 u8 reserved_at_388[0x3]; 1534 u8 log_max_rqt[0x5]; 1535 u8 reserved_at_390[0x3]; 1536 u8 log_max_rqt_size[0x5]; 1537 u8 reserved_at_398[0x3]; 1538 u8 log_max_tis_per_sq[0x5]; 1539 1540 u8 ext_stride_num_range[0x1]; 1541 u8 reserved_at_3a1[0x2]; 1542 u8 log_max_stride_sz_rq[0x5]; 1543 u8 reserved_at_3a8[0x3]; 1544 u8 log_min_stride_sz_rq[0x5]; 1545 u8 reserved_at_3b0[0x3]; 1546 u8 log_max_stride_sz_sq[0x5]; 1547 u8 reserved_at_3b8[0x3]; 1548 u8 log_min_stride_sz_sq[0x5]; 1549 1550 u8 hairpin[0x1]; 1551 u8 reserved_at_3c1[0x2]; 1552 u8 log_max_hairpin_queues[0x5]; 1553 u8 reserved_at_3c8[0x3]; 1554 u8 log_max_hairpin_wq_data_sz[0x5]; 1555 u8 reserved_at_3d0[0x3]; 1556 u8 log_max_hairpin_num_packets[0x5]; 1557 u8 reserved_at_3d8[0x3]; 1558 u8 log_max_wq_sz[0x5]; 1559 1560 u8 nic_vport_change_event[0x1]; 1561 u8 disable_local_lb_uc[0x1]; 1562 u8 disable_local_lb_mc[0x1]; 1563 u8 log_min_hairpin_wq_data_sz[0x5]; 1564 u8 reserved_at_3e8[0x2]; 1565 u8 vhca_state[0x1]; 1566 u8 log_max_vlan_list[0x5]; 1567 u8 reserved_at_3f0[0x3]; 1568 u8 log_max_current_mc_list[0x5]; 1569 u8 reserved_at_3f8[0x3]; 1570 u8 log_max_current_uc_list[0x5]; 1571 1572 u8 general_obj_types[0x40]; 1573 1574 u8 reserved_at_440[0x4]; 1575 u8 steering_format_version[0x4]; 1576 u8 create_qp_start_hint[0x18]; 1577 1578 u8 reserved_at_460[0x3]; 1579 u8 log_max_uctx[0x5]; 1580 u8 reserved_at_468[0x2]; 1581 u8 ipsec_offload[0x1]; 1582 u8 log_max_umem[0x5]; 1583 u8 max_num_eqs[0x10]; 1584 1585 u8 reserved_at_480[0x1]; 1586 u8 tls_tx[0x1]; 1587 u8 tls_rx[0x1]; 1588 u8 log_max_l2_table[0x5]; 1589 u8 reserved_at_488[0x8]; 1590 u8 log_uar_page_sz[0x10]; 1591 1592 u8 reserved_at_4a0[0x20]; 1593 u8 device_frequency_mhz[0x20]; 1594 u8 device_frequency_khz[0x20]; 1595 1596 u8 reserved_at_500[0x20]; 1597 u8 num_of_uars_per_page[0x20]; 1598 1599 u8 flex_parser_protocols[0x20]; 1600 1601 u8 max_geneve_tlv_options[0x8]; 1602 u8 reserved_at_568[0x3]; 1603 u8 max_geneve_tlv_option_data_len[0x5]; 1604 u8 reserved_at_570[0x10]; 1605 1606 u8 reserved_at_580[0x33]; 1607 u8 log_max_dek[0x5]; 1608 u8 reserved_at_5b8[0x4]; 1609 u8 mini_cqe_resp_stride_index[0x1]; 1610 u8 cqe_128_always[0x1]; 1611 u8 cqe_compression_128[0x1]; 1612 u8 cqe_compression[0x1]; 1613 1614 u8 cqe_compression_timeout[0x10]; 1615 u8 cqe_compression_max_num[0x10]; 1616 1617 u8 reserved_at_5e0[0x10]; 1618 u8 tag_matching[0x1]; 1619 u8 rndv_offload_rc[0x1]; 1620 u8 rndv_offload_dc[0x1]; 1621 u8 log_tag_matching_list_sz[0x5]; 1622 u8 reserved_at_5f8[0x3]; 1623 u8 log_max_xrq[0x5]; 1624 1625 u8 affiliate_nic_vport_criteria[0x8]; 1626 u8 native_port_num[0x8]; 1627 u8 num_vhca_ports[0x8]; 1628 u8 reserved_at_618[0x6]; 1629 u8 sw_owner_id[0x1]; 1630 u8 reserved_at_61f[0x1]; 1631 1632 u8 max_num_of_monitor_counters[0x10]; 1633 u8 num_ppcnt_monitor_counters[0x10]; 1634 1635 u8 max_num_sf[0x10]; 1636 u8 num_q_monitor_counters[0x10]; 1637 1638 u8 reserved_at_660[0x20]; 1639 1640 u8 sf[0x1]; 1641 u8 sf_set_partition[0x1]; 1642 u8 reserved_at_682[0x1]; 1643 u8 log_max_sf[0x5]; 1644 u8 reserved_at_688[0x8]; 1645 u8 log_min_sf_size[0x8]; 1646 u8 max_num_sf_partitions[0x8]; 1647 1648 u8 uctx_cap[0x20]; 1649 1650 u8 reserved_at_6c0[0x4]; 1651 u8 flex_parser_id_geneve_tlv_option_0[0x4]; 1652 u8 flex_parser_id_icmp_dw1[0x4]; 1653 u8 flex_parser_id_icmp_dw0[0x4]; 1654 u8 flex_parser_id_icmpv6_dw1[0x4]; 1655 u8 flex_parser_id_icmpv6_dw0[0x4]; 1656 u8 flex_parser_id_outer_first_mpls_over_gre[0x4]; 1657 u8 flex_parser_id_outer_first_mpls_over_udp_label[0x4]; 1658 1659 u8 reserved_at_6e0[0x10]; 1660 u8 sf_base_id[0x10]; 1661 1662 u8 reserved_at_700[0x80]; 1663 u8 vhca_tunnel_commands[0x40]; 1664 u8 reserved_at_7c0[0x40]; 1665 }; 1666 1667 enum mlx5_flow_destination_type { 1668 MLX5_FLOW_DESTINATION_TYPE_VPORT = 0x0, 1669 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1, 1670 MLX5_FLOW_DESTINATION_TYPE_TIR = 0x2, 1671 MLX5_FLOW_DESTINATION_TYPE_FLOW_SAMPLER = 0x6, 1672 1673 MLX5_FLOW_DESTINATION_TYPE_PORT = 0x99, 1674 MLX5_FLOW_DESTINATION_TYPE_COUNTER = 0x100, 1675 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE_NUM = 0x101, 1676 }; 1677 1678 enum mlx5_flow_table_miss_action { 1679 MLX5_FLOW_TABLE_MISS_ACTION_DEF, 1680 MLX5_FLOW_TABLE_MISS_ACTION_FWD, 1681 MLX5_FLOW_TABLE_MISS_ACTION_SWITCH_DOMAIN, 1682 }; 1683 1684 struct mlx5_ifc_dest_format_struct_bits { 1685 u8 destination_type[0x8]; 1686 u8 destination_id[0x18]; 1687 1688 u8 destination_eswitch_owner_vhca_id_valid[0x1]; 1689 u8 packet_reformat[0x1]; 1690 u8 reserved_at_22[0xe]; 1691 u8 destination_eswitch_owner_vhca_id[0x10]; 1692 }; 1693 1694 struct mlx5_ifc_flow_counter_list_bits { 1695 u8 flow_counter_id[0x20]; 1696 1697 u8 reserved_at_20[0x20]; 1698 }; 1699 1700 struct mlx5_ifc_extended_dest_format_bits { 1701 struct mlx5_ifc_dest_format_struct_bits destination_entry; 1702 1703 u8 packet_reformat_id[0x20]; 1704 1705 u8 reserved_at_60[0x20]; 1706 }; 1707 1708 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits { 1709 struct mlx5_ifc_extended_dest_format_bits extended_dest_format; 1710 struct mlx5_ifc_flow_counter_list_bits flow_counter_list; 1711 }; 1712 1713 struct mlx5_ifc_fte_match_param_bits { 1714 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers; 1715 1716 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters; 1717 1718 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers; 1719 1720 struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2; 1721 1722 struct mlx5_ifc_fte_match_set_misc3_bits misc_parameters_3; 1723 1724 struct mlx5_ifc_fte_match_set_misc4_bits misc_parameters_4; 1725 1726 u8 reserved_at_c00[0x400]; 1727 }; 1728 1729 enum { 1730 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0, 1731 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1, 1732 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2, 1733 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3, 1734 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4, 1735 }; 1736 1737 struct mlx5_ifc_rx_hash_field_select_bits { 1738 u8 l3_prot_type[0x1]; 1739 u8 l4_prot_type[0x1]; 1740 u8 selected_fields[0x1e]; 1741 }; 1742 1743 enum { 1744 MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0, 1745 MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1, 1746 }; 1747 1748 enum { 1749 MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0, 1750 MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1, 1751 }; 1752 1753 struct mlx5_ifc_wq_bits { 1754 u8 wq_type[0x4]; 1755 u8 wq_signature[0x1]; 1756 u8 end_padding_mode[0x2]; 1757 u8 cd_slave[0x1]; 1758 u8 reserved_at_8[0x18]; 1759 1760 u8 hds_skip_first_sge[0x1]; 1761 u8 log2_hds_buf_size[0x3]; 1762 u8 reserved_at_24[0x7]; 1763 u8 page_offset[0x5]; 1764 u8 lwm[0x10]; 1765 1766 u8 reserved_at_40[0x8]; 1767 u8 pd[0x18]; 1768 1769 u8 reserved_at_60[0x8]; 1770 u8 uar_page[0x18]; 1771 1772 u8 dbr_addr[0x40]; 1773 1774 u8 hw_counter[0x20]; 1775 1776 u8 sw_counter[0x20]; 1777 1778 u8 reserved_at_100[0xc]; 1779 u8 log_wq_stride[0x4]; 1780 u8 reserved_at_110[0x3]; 1781 u8 log_wq_pg_sz[0x5]; 1782 u8 reserved_at_118[0x3]; 1783 u8 log_wq_sz[0x5]; 1784 1785 u8 dbr_umem_valid[0x1]; 1786 u8 wq_umem_valid[0x1]; 1787 u8 reserved_at_122[0x1]; 1788 u8 log_hairpin_num_packets[0x5]; 1789 u8 reserved_at_128[0x3]; 1790 u8 log_hairpin_data_sz[0x5]; 1791 1792 u8 reserved_at_130[0x4]; 1793 u8 log_wqe_num_of_strides[0x4]; 1794 u8 two_byte_shift_en[0x1]; 1795 u8 reserved_at_139[0x4]; 1796 u8 log_wqe_stride_size[0x3]; 1797 1798 u8 reserved_at_140[0x4c0]; 1799 1800 struct mlx5_ifc_cmd_pas_bits pas[]; 1801 }; 1802 1803 struct mlx5_ifc_rq_num_bits { 1804 u8 reserved_at_0[0x8]; 1805 u8 rq_num[0x18]; 1806 }; 1807 1808 struct mlx5_ifc_mac_address_layout_bits { 1809 u8 reserved_at_0[0x10]; 1810 u8 mac_addr_47_32[0x10]; 1811 1812 u8 mac_addr_31_0[0x20]; 1813 }; 1814 1815 struct mlx5_ifc_vlan_layout_bits { 1816 u8 reserved_at_0[0x14]; 1817 u8 vlan[0x0c]; 1818 1819 u8 reserved_at_20[0x20]; 1820 }; 1821 1822 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits { 1823 u8 reserved_at_0[0xa0]; 1824 1825 u8 min_time_between_cnps[0x20]; 1826 1827 u8 reserved_at_c0[0x12]; 1828 u8 cnp_dscp[0x6]; 1829 u8 reserved_at_d8[0x4]; 1830 u8 cnp_prio_mode[0x1]; 1831 u8 cnp_802p_prio[0x3]; 1832 1833 u8 reserved_at_e0[0x720]; 1834 }; 1835 1836 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits { 1837 u8 reserved_at_0[0x60]; 1838 1839 u8 reserved_at_60[0x4]; 1840 u8 clamp_tgt_rate[0x1]; 1841 u8 reserved_at_65[0x3]; 1842 u8 clamp_tgt_rate_after_time_inc[0x1]; 1843 u8 reserved_at_69[0x17]; 1844 1845 u8 reserved_at_80[0x20]; 1846 1847 u8 rpg_time_reset[0x20]; 1848 1849 u8 rpg_byte_reset[0x20]; 1850 1851 u8 rpg_threshold[0x20]; 1852 1853 u8 rpg_max_rate[0x20]; 1854 1855 u8 rpg_ai_rate[0x20]; 1856 1857 u8 rpg_hai_rate[0x20]; 1858 1859 u8 rpg_gd[0x20]; 1860 1861 u8 rpg_min_dec_fac[0x20]; 1862 1863 u8 rpg_min_rate[0x20]; 1864 1865 u8 reserved_at_1c0[0xe0]; 1866 1867 u8 rate_to_set_on_first_cnp[0x20]; 1868 1869 u8 dce_tcp_g[0x20]; 1870 1871 u8 dce_tcp_rtt[0x20]; 1872 1873 u8 rate_reduce_monitor_period[0x20]; 1874 1875 u8 reserved_at_320[0x20]; 1876 1877 u8 initial_alpha_value[0x20]; 1878 1879 u8 reserved_at_360[0x4a0]; 1880 }; 1881 1882 struct mlx5_ifc_cong_control_802_1qau_rp_bits { 1883 u8 reserved_at_0[0x80]; 1884 1885 u8 rppp_max_rps[0x20]; 1886 1887 u8 rpg_time_reset[0x20]; 1888 1889 u8 rpg_byte_reset[0x20]; 1890 1891 u8 rpg_threshold[0x20]; 1892 1893 u8 rpg_max_rate[0x20]; 1894 1895 u8 rpg_ai_rate[0x20]; 1896 1897 u8 rpg_hai_rate[0x20]; 1898 1899 u8 rpg_gd[0x20]; 1900 1901 u8 rpg_min_dec_fac[0x20]; 1902 1903 u8 rpg_min_rate[0x20]; 1904 1905 u8 reserved_at_1c0[0x640]; 1906 }; 1907 1908 enum { 1909 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1, 1910 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2, 1911 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4, 1912 }; 1913 1914 struct mlx5_ifc_resize_field_select_bits { 1915 u8 resize_field_select[0x20]; 1916 }; 1917 1918 struct mlx5_ifc_resource_dump_bits { 1919 u8 more_dump[0x1]; 1920 u8 inline_dump[0x1]; 1921 u8 reserved_at_2[0xa]; 1922 u8 seq_num[0x4]; 1923 u8 segment_type[0x10]; 1924 1925 u8 reserved_at_20[0x10]; 1926 u8 vhca_id[0x10]; 1927 1928 u8 index1[0x20]; 1929 1930 u8 index2[0x20]; 1931 1932 u8 num_of_obj1[0x10]; 1933 u8 num_of_obj2[0x10]; 1934 1935 u8 reserved_at_a0[0x20]; 1936 1937 u8 device_opaque[0x40]; 1938 1939 u8 mkey[0x20]; 1940 1941 u8 size[0x20]; 1942 1943 u8 address[0x40]; 1944 1945 u8 inline_data[52][0x20]; 1946 }; 1947 1948 struct mlx5_ifc_resource_dump_menu_record_bits { 1949 u8 reserved_at_0[0x4]; 1950 u8 num_of_obj2_supports_active[0x1]; 1951 u8 num_of_obj2_supports_all[0x1]; 1952 u8 must_have_num_of_obj2[0x1]; 1953 u8 support_num_of_obj2[0x1]; 1954 u8 num_of_obj1_supports_active[0x1]; 1955 u8 num_of_obj1_supports_all[0x1]; 1956 u8 must_have_num_of_obj1[0x1]; 1957 u8 support_num_of_obj1[0x1]; 1958 u8 must_have_index2[0x1]; 1959 u8 support_index2[0x1]; 1960 u8 must_have_index1[0x1]; 1961 u8 support_index1[0x1]; 1962 u8 segment_type[0x10]; 1963 1964 u8 segment_name[4][0x20]; 1965 1966 u8 index1_name[4][0x20]; 1967 1968 u8 index2_name[4][0x20]; 1969 }; 1970 1971 struct mlx5_ifc_resource_dump_segment_header_bits { 1972 u8 length_dw[0x10]; 1973 u8 segment_type[0x10]; 1974 }; 1975 1976 struct mlx5_ifc_resource_dump_command_segment_bits { 1977 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 1978 1979 u8 segment_called[0x10]; 1980 u8 vhca_id[0x10]; 1981 1982 u8 index1[0x20]; 1983 1984 u8 index2[0x20]; 1985 1986 u8 num_of_obj1[0x10]; 1987 u8 num_of_obj2[0x10]; 1988 }; 1989 1990 struct mlx5_ifc_resource_dump_error_segment_bits { 1991 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 1992 1993 u8 reserved_at_20[0x10]; 1994 u8 syndrome_id[0x10]; 1995 1996 u8 reserved_at_40[0x40]; 1997 1998 u8 error[8][0x20]; 1999 }; 2000 2001 struct mlx5_ifc_resource_dump_info_segment_bits { 2002 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2003 2004 u8 reserved_at_20[0x18]; 2005 u8 dump_version[0x8]; 2006 2007 u8 hw_version[0x20]; 2008 2009 u8 fw_version[0x20]; 2010 }; 2011 2012 struct mlx5_ifc_resource_dump_menu_segment_bits { 2013 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2014 2015 u8 reserved_at_20[0x10]; 2016 u8 num_of_records[0x10]; 2017 2018 struct mlx5_ifc_resource_dump_menu_record_bits record[]; 2019 }; 2020 2021 struct mlx5_ifc_resource_dump_resource_segment_bits { 2022 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2023 2024 u8 reserved_at_20[0x20]; 2025 2026 u8 index1[0x20]; 2027 2028 u8 index2[0x20]; 2029 2030 u8 payload[][0x20]; 2031 }; 2032 2033 struct mlx5_ifc_resource_dump_terminate_segment_bits { 2034 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2035 }; 2036 2037 struct mlx5_ifc_menu_resource_dump_response_bits { 2038 struct mlx5_ifc_resource_dump_info_segment_bits info; 2039 struct mlx5_ifc_resource_dump_command_segment_bits cmd; 2040 struct mlx5_ifc_resource_dump_menu_segment_bits menu; 2041 struct mlx5_ifc_resource_dump_terminate_segment_bits terminate; 2042 }; 2043 2044 enum { 2045 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1, 2046 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2, 2047 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4, 2048 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8, 2049 }; 2050 2051 struct mlx5_ifc_modify_field_select_bits { 2052 u8 modify_field_select[0x20]; 2053 }; 2054 2055 struct mlx5_ifc_field_select_r_roce_np_bits { 2056 u8 field_select_r_roce_np[0x20]; 2057 }; 2058 2059 struct mlx5_ifc_field_select_r_roce_rp_bits { 2060 u8 field_select_r_roce_rp[0x20]; 2061 }; 2062 2063 enum { 2064 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4, 2065 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8, 2066 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10, 2067 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20, 2068 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40, 2069 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80, 2070 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100, 2071 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200, 2072 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400, 2073 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800, 2074 }; 2075 2076 struct mlx5_ifc_field_select_802_1qau_rp_bits { 2077 u8 field_select_8021qaurp[0x20]; 2078 }; 2079 2080 struct mlx5_ifc_phys_layer_cntrs_bits { 2081 u8 time_since_last_clear_high[0x20]; 2082 2083 u8 time_since_last_clear_low[0x20]; 2084 2085 u8 symbol_errors_high[0x20]; 2086 2087 u8 symbol_errors_low[0x20]; 2088 2089 u8 sync_headers_errors_high[0x20]; 2090 2091 u8 sync_headers_errors_low[0x20]; 2092 2093 u8 edpl_bip_errors_lane0_high[0x20]; 2094 2095 u8 edpl_bip_errors_lane0_low[0x20]; 2096 2097 u8 edpl_bip_errors_lane1_high[0x20]; 2098 2099 u8 edpl_bip_errors_lane1_low[0x20]; 2100 2101 u8 edpl_bip_errors_lane2_high[0x20]; 2102 2103 u8 edpl_bip_errors_lane2_low[0x20]; 2104 2105 u8 edpl_bip_errors_lane3_high[0x20]; 2106 2107 u8 edpl_bip_errors_lane3_low[0x20]; 2108 2109 u8 fc_fec_corrected_blocks_lane0_high[0x20]; 2110 2111 u8 fc_fec_corrected_blocks_lane0_low[0x20]; 2112 2113 u8 fc_fec_corrected_blocks_lane1_high[0x20]; 2114 2115 u8 fc_fec_corrected_blocks_lane1_low[0x20]; 2116 2117 u8 fc_fec_corrected_blocks_lane2_high[0x20]; 2118 2119 u8 fc_fec_corrected_blocks_lane2_low[0x20]; 2120 2121 u8 fc_fec_corrected_blocks_lane3_high[0x20]; 2122 2123 u8 fc_fec_corrected_blocks_lane3_low[0x20]; 2124 2125 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20]; 2126 2127 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20]; 2128 2129 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20]; 2130 2131 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20]; 2132 2133 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20]; 2134 2135 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20]; 2136 2137 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20]; 2138 2139 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20]; 2140 2141 u8 rs_fec_corrected_blocks_high[0x20]; 2142 2143 u8 rs_fec_corrected_blocks_low[0x20]; 2144 2145 u8 rs_fec_uncorrectable_blocks_high[0x20]; 2146 2147 u8 rs_fec_uncorrectable_blocks_low[0x20]; 2148 2149 u8 rs_fec_no_errors_blocks_high[0x20]; 2150 2151 u8 rs_fec_no_errors_blocks_low[0x20]; 2152 2153 u8 rs_fec_single_error_blocks_high[0x20]; 2154 2155 u8 rs_fec_single_error_blocks_low[0x20]; 2156 2157 u8 rs_fec_corrected_symbols_total_high[0x20]; 2158 2159 u8 rs_fec_corrected_symbols_total_low[0x20]; 2160 2161 u8 rs_fec_corrected_symbols_lane0_high[0x20]; 2162 2163 u8 rs_fec_corrected_symbols_lane0_low[0x20]; 2164 2165 u8 rs_fec_corrected_symbols_lane1_high[0x20]; 2166 2167 u8 rs_fec_corrected_symbols_lane1_low[0x20]; 2168 2169 u8 rs_fec_corrected_symbols_lane2_high[0x20]; 2170 2171 u8 rs_fec_corrected_symbols_lane2_low[0x20]; 2172 2173 u8 rs_fec_corrected_symbols_lane3_high[0x20]; 2174 2175 u8 rs_fec_corrected_symbols_lane3_low[0x20]; 2176 2177 u8 link_down_events[0x20]; 2178 2179 u8 successful_recovery_events[0x20]; 2180 2181 u8 reserved_at_640[0x180]; 2182 }; 2183 2184 struct mlx5_ifc_phys_layer_statistical_cntrs_bits { 2185 u8 time_since_last_clear_high[0x20]; 2186 2187 u8 time_since_last_clear_low[0x20]; 2188 2189 u8 phy_received_bits_high[0x20]; 2190 2191 u8 phy_received_bits_low[0x20]; 2192 2193 u8 phy_symbol_errors_high[0x20]; 2194 2195 u8 phy_symbol_errors_low[0x20]; 2196 2197 u8 phy_corrected_bits_high[0x20]; 2198 2199 u8 phy_corrected_bits_low[0x20]; 2200 2201 u8 phy_corrected_bits_lane0_high[0x20]; 2202 2203 u8 phy_corrected_bits_lane0_low[0x20]; 2204 2205 u8 phy_corrected_bits_lane1_high[0x20]; 2206 2207 u8 phy_corrected_bits_lane1_low[0x20]; 2208 2209 u8 phy_corrected_bits_lane2_high[0x20]; 2210 2211 u8 phy_corrected_bits_lane2_low[0x20]; 2212 2213 u8 phy_corrected_bits_lane3_high[0x20]; 2214 2215 u8 phy_corrected_bits_lane3_low[0x20]; 2216 2217 u8 reserved_at_200[0x5c0]; 2218 }; 2219 2220 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits { 2221 u8 symbol_error_counter[0x10]; 2222 2223 u8 link_error_recovery_counter[0x8]; 2224 2225 u8 link_downed_counter[0x8]; 2226 2227 u8 port_rcv_errors[0x10]; 2228 2229 u8 port_rcv_remote_physical_errors[0x10]; 2230 2231 u8 port_rcv_switch_relay_errors[0x10]; 2232 2233 u8 port_xmit_discards[0x10]; 2234 2235 u8 port_xmit_constraint_errors[0x8]; 2236 2237 u8 port_rcv_constraint_errors[0x8]; 2238 2239 u8 reserved_at_70[0x8]; 2240 2241 u8 link_overrun_errors[0x8]; 2242 2243 u8 reserved_at_80[0x10]; 2244 2245 u8 vl_15_dropped[0x10]; 2246 2247 u8 reserved_at_a0[0x80]; 2248 2249 u8 port_xmit_wait[0x20]; 2250 }; 2251 2252 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits { 2253 u8 transmit_queue_high[0x20]; 2254 2255 u8 transmit_queue_low[0x20]; 2256 2257 u8 no_buffer_discard_uc_high[0x20]; 2258 2259 u8 no_buffer_discard_uc_low[0x20]; 2260 2261 u8 reserved_at_80[0x740]; 2262 }; 2263 2264 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits { 2265 u8 wred_discard_high[0x20]; 2266 2267 u8 wred_discard_low[0x20]; 2268 2269 u8 ecn_marked_tc_high[0x20]; 2270 2271 u8 ecn_marked_tc_low[0x20]; 2272 2273 u8 reserved_at_80[0x740]; 2274 }; 2275 2276 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits { 2277 u8 rx_octets_high[0x20]; 2278 2279 u8 rx_octets_low[0x20]; 2280 2281 u8 reserved_at_40[0xc0]; 2282 2283 u8 rx_frames_high[0x20]; 2284 2285 u8 rx_frames_low[0x20]; 2286 2287 u8 tx_octets_high[0x20]; 2288 2289 u8 tx_octets_low[0x20]; 2290 2291 u8 reserved_at_180[0xc0]; 2292 2293 u8 tx_frames_high[0x20]; 2294 2295 u8 tx_frames_low[0x20]; 2296 2297 u8 rx_pause_high[0x20]; 2298 2299 u8 rx_pause_low[0x20]; 2300 2301 u8 rx_pause_duration_high[0x20]; 2302 2303 u8 rx_pause_duration_low[0x20]; 2304 2305 u8 tx_pause_high[0x20]; 2306 2307 u8 tx_pause_low[0x20]; 2308 2309 u8 tx_pause_duration_high[0x20]; 2310 2311 u8 tx_pause_duration_low[0x20]; 2312 2313 u8 rx_pause_transition_high[0x20]; 2314 2315 u8 rx_pause_transition_low[0x20]; 2316 2317 u8 rx_discards_high[0x20]; 2318 2319 u8 rx_discards_low[0x20]; 2320 2321 u8 device_stall_minor_watermark_cnt_high[0x20]; 2322 2323 u8 device_stall_minor_watermark_cnt_low[0x20]; 2324 2325 u8 device_stall_critical_watermark_cnt_high[0x20]; 2326 2327 u8 device_stall_critical_watermark_cnt_low[0x20]; 2328 2329 u8 reserved_at_480[0x340]; 2330 }; 2331 2332 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits { 2333 u8 port_transmit_wait_high[0x20]; 2334 2335 u8 port_transmit_wait_low[0x20]; 2336 2337 u8 reserved_at_40[0x100]; 2338 2339 u8 rx_buffer_almost_full_high[0x20]; 2340 2341 u8 rx_buffer_almost_full_low[0x20]; 2342 2343 u8 rx_buffer_full_high[0x20]; 2344 2345 u8 rx_buffer_full_low[0x20]; 2346 2347 u8 rx_icrc_encapsulated_high[0x20]; 2348 2349 u8 rx_icrc_encapsulated_low[0x20]; 2350 2351 u8 reserved_at_200[0x5c0]; 2352 }; 2353 2354 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits { 2355 u8 dot3stats_alignment_errors_high[0x20]; 2356 2357 u8 dot3stats_alignment_errors_low[0x20]; 2358 2359 u8 dot3stats_fcs_errors_high[0x20]; 2360 2361 u8 dot3stats_fcs_errors_low[0x20]; 2362 2363 u8 dot3stats_single_collision_frames_high[0x20]; 2364 2365 u8 dot3stats_single_collision_frames_low[0x20]; 2366 2367 u8 dot3stats_multiple_collision_frames_high[0x20]; 2368 2369 u8 dot3stats_multiple_collision_frames_low[0x20]; 2370 2371 u8 dot3stats_sqe_test_errors_high[0x20]; 2372 2373 u8 dot3stats_sqe_test_errors_low[0x20]; 2374 2375 u8 dot3stats_deferred_transmissions_high[0x20]; 2376 2377 u8 dot3stats_deferred_transmissions_low[0x20]; 2378 2379 u8 dot3stats_late_collisions_high[0x20]; 2380 2381 u8 dot3stats_late_collisions_low[0x20]; 2382 2383 u8 dot3stats_excessive_collisions_high[0x20]; 2384 2385 u8 dot3stats_excessive_collisions_low[0x20]; 2386 2387 u8 dot3stats_internal_mac_transmit_errors_high[0x20]; 2388 2389 u8 dot3stats_internal_mac_transmit_errors_low[0x20]; 2390 2391 u8 dot3stats_carrier_sense_errors_high[0x20]; 2392 2393 u8 dot3stats_carrier_sense_errors_low[0x20]; 2394 2395 u8 dot3stats_frame_too_longs_high[0x20]; 2396 2397 u8 dot3stats_frame_too_longs_low[0x20]; 2398 2399 u8 dot3stats_internal_mac_receive_errors_high[0x20]; 2400 2401 u8 dot3stats_internal_mac_receive_errors_low[0x20]; 2402 2403 u8 dot3stats_symbol_errors_high[0x20]; 2404 2405 u8 dot3stats_symbol_errors_low[0x20]; 2406 2407 u8 dot3control_in_unknown_opcodes_high[0x20]; 2408 2409 u8 dot3control_in_unknown_opcodes_low[0x20]; 2410 2411 u8 dot3in_pause_frames_high[0x20]; 2412 2413 u8 dot3in_pause_frames_low[0x20]; 2414 2415 u8 dot3out_pause_frames_high[0x20]; 2416 2417 u8 dot3out_pause_frames_low[0x20]; 2418 2419 u8 reserved_at_400[0x3c0]; 2420 }; 2421 2422 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits { 2423 u8 ether_stats_drop_events_high[0x20]; 2424 2425 u8 ether_stats_drop_events_low[0x20]; 2426 2427 u8 ether_stats_octets_high[0x20]; 2428 2429 u8 ether_stats_octets_low[0x20]; 2430 2431 u8 ether_stats_pkts_high[0x20]; 2432 2433 u8 ether_stats_pkts_low[0x20]; 2434 2435 u8 ether_stats_broadcast_pkts_high[0x20]; 2436 2437 u8 ether_stats_broadcast_pkts_low[0x20]; 2438 2439 u8 ether_stats_multicast_pkts_high[0x20]; 2440 2441 u8 ether_stats_multicast_pkts_low[0x20]; 2442 2443 u8 ether_stats_crc_align_errors_high[0x20]; 2444 2445 u8 ether_stats_crc_align_errors_low[0x20]; 2446 2447 u8 ether_stats_undersize_pkts_high[0x20]; 2448 2449 u8 ether_stats_undersize_pkts_low[0x20]; 2450 2451 u8 ether_stats_oversize_pkts_high[0x20]; 2452 2453 u8 ether_stats_oversize_pkts_low[0x20]; 2454 2455 u8 ether_stats_fragments_high[0x20]; 2456 2457 u8 ether_stats_fragments_low[0x20]; 2458 2459 u8 ether_stats_jabbers_high[0x20]; 2460 2461 u8 ether_stats_jabbers_low[0x20]; 2462 2463 u8 ether_stats_collisions_high[0x20]; 2464 2465 u8 ether_stats_collisions_low[0x20]; 2466 2467 u8 ether_stats_pkts64octets_high[0x20]; 2468 2469 u8 ether_stats_pkts64octets_low[0x20]; 2470 2471 u8 ether_stats_pkts65to127octets_high[0x20]; 2472 2473 u8 ether_stats_pkts65to127octets_low[0x20]; 2474 2475 u8 ether_stats_pkts128to255octets_high[0x20]; 2476 2477 u8 ether_stats_pkts128to255octets_low[0x20]; 2478 2479 u8 ether_stats_pkts256to511octets_high[0x20]; 2480 2481 u8 ether_stats_pkts256to511octets_low[0x20]; 2482 2483 u8 ether_stats_pkts512to1023octets_high[0x20]; 2484 2485 u8 ether_stats_pkts512to1023octets_low[0x20]; 2486 2487 u8 ether_stats_pkts1024to1518octets_high[0x20]; 2488 2489 u8 ether_stats_pkts1024to1518octets_low[0x20]; 2490 2491 u8 ether_stats_pkts1519to2047octets_high[0x20]; 2492 2493 u8 ether_stats_pkts1519to2047octets_low[0x20]; 2494 2495 u8 ether_stats_pkts2048to4095octets_high[0x20]; 2496 2497 u8 ether_stats_pkts2048to4095octets_low[0x20]; 2498 2499 u8 ether_stats_pkts4096to8191octets_high[0x20]; 2500 2501 u8 ether_stats_pkts4096to8191octets_low[0x20]; 2502 2503 u8 ether_stats_pkts8192to10239octets_high[0x20]; 2504 2505 u8 ether_stats_pkts8192to10239octets_low[0x20]; 2506 2507 u8 reserved_at_540[0x280]; 2508 }; 2509 2510 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits { 2511 u8 if_in_octets_high[0x20]; 2512 2513 u8 if_in_octets_low[0x20]; 2514 2515 u8 if_in_ucast_pkts_high[0x20]; 2516 2517 u8 if_in_ucast_pkts_low[0x20]; 2518 2519 u8 if_in_discards_high[0x20]; 2520 2521 u8 if_in_discards_low[0x20]; 2522 2523 u8 if_in_errors_high[0x20]; 2524 2525 u8 if_in_errors_low[0x20]; 2526 2527 u8 if_in_unknown_protos_high[0x20]; 2528 2529 u8 if_in_unknown_protos_low[0x20]; 2530 2531 u8 if_out_octets_high[0x20]; 2532 2533 u8 if_out_octets_low[0x20]; 2534 2535 u8 if_out_ucast_pkts_high[0x20]; 2536 2537 u8 if_out_ucast_pkts_low[0x20]; 2538 2539 u8 if_out_discards_high[0x20]; 2540 2541 u8 if_out_discards_low[0x20]; 2542 2543 u8 if_out_errors_high[0x20]; 2544 2545 u8 if_out_errors_low[0x20]; 2546 2547 u8 if_in_multicast_pkts_high[0x20]; 2548 2549 u8 if_in_multicast_pkts_low[0x20]; 2550 2551 u8 if_in_broadcast_pkts_high[0x20]; 2552 2553 u8 if_in_broadcast_pkts_low[0x20]; 2554 2555 u8 if_out_multicast_pkts_high[0x20]; 2556 2557 u8 if_out_multicast_pkts_low[0x20]; 2558 2559 u8 if_out_broadcast_pkts_high[0x20]; 2560 2561 u8 if_out_broadcast_pkts_low[0x20]; 2562 2563 u8 reserved_at_340[0x480]; 2564 }; 2565 2566 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits { 2567 u8 a_frames_transmitted_ok_high[0x20]; 2568 2569 u8 a_frames_transmitted_ok_low[0x20]; 2570 2571 u8 a_frames_received_ok_high[0x20]; 2572 2573 u8 a_frames_received_ok_low[0x20]; 2574 2575 u8 a_frame_check_sequence_errors_high[0x20]; 2576 2577 u8 a_frame_check_sequence_errors_low[0x20]; 2578 2579 u8 a_alignment_errors_high[0x20]; 2580 2581 u8 a_alignment_errors_low[0x20]; 2582 2583 u8 a_octets_transmitted_ok_high[0x20]; 2584 2585 u8 a_octets_transmitted_ok_low[0x20]; 2586 2587 u8 a_octets_received_ok_high[0x20]; 2588 2589 u8 a_octets_received_ok_low[0x20]; 2590 2591 u8 a_multicast_frames_xmitted_ok_high[0x20]; 2592 2593 u8 a_multicast_frames_xmitted_ok_low[0x20]; 2594 2595 u8 a_broadcast_frames_xmitted_ok_high[0x20]; 2596 2597 u8 a_broadcast_frames_xmitted_ok_low[0x20]; 2598 2599 u8 a_multicast_frames_received_ok_high[0x20]; 2600 2601 u8 a_multicast_frames_received_ok_low[0x20]; 2602 2603 u8 a_broadcast_frames_received_ok_high[0x20]; 2604 2605 u8 a_broadcast_frames_received_ok_low[0x20]; 2606 2607 u8 a_in_range_length_errors_high[0x20]; 2608 2609 u8 a_in_range_length_errors_low[0x20]; 2610 2611 u8 a_out_of_range_length_field_high[0x20]; 2612 2613 u8 a_out_of_range_length_field_low[0x20]; 2614 2615 u8 a_frame_too_long_errors_high[0x20]; 2616 2617 u8 a_frame_too_long_errors_low[0x20]; 2618 2619 u8 a_symbol_error_during_carrier_high[0x20]; 2620 2621 u8 a_symbol_error_during_carrier_low[0x20]; 2622 2623 u8 a_mac_control_frames_transmitted_high[0x20]; 2624 2625 u8 a_mac_control_frames_transmitted_low[0x20]; 2626 2627 u8 a_mac_control_frames_received_high[0x20]; 2628 2629 u8 a_mac_control_frames_received_low[0x20]; 2630 2631 u8 a_unsupported_opcodes_received_high[0x20]; 2632 2633 u8 a_unsupported_opcodes_received_low[0x20]; 2634 2635 u8 a_pause_mac_ctrl_frames_received_high[0x20]; 2636 2637 u8 a_pause_mac_ctrl_frames_received_low[0x20]; 2638 2639 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20]; 2640 2641 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20]; 2642 2643 u8 reserved_at_4c0[0x300]; 2644 }; 2645 2646 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits { 2647 u8 life_time_counter_high[0x20]; 2648 2649 u8 life_time_counter_low[0x20]; 2650 2651 u8 rx_errors[0x20]; 2652 2653 u8 tx_errors[0x20]; 2654 2655 u8 l0_to_recovery_eieos[0x20]; 2656 2657 u8 l0_to_recovery_ts[0x20]; 2658 2659 u8 l0_to_recovery_framing[0x20]; 2660 2661 u8 l0_to_recovery_retrain[0x20]; 2662 2663 u8 crc_error_dllp[0x20]; 2664 2665 u8 crc_error_tlp[0x20]; 2666 2667 u8 tx_overflow_buffer_pkt_high[0x20]; 2668 2669 u8 tx_overflow_buffer_pkt_low[0x20]; 2670 2671 u8 outbound_stalled_reads[0x20]; 2672 2673 u8 outbound_stalled_writes[0x20]; 2674 2675 u8 outbound_stalled_reads_events[0x20]; 2676 2677 u8 outbound_stalled_writes_events[0x20]; 2678 2679 u8 reserved_at_200[0x5c0]; 2680 }; 2681 2682 struct mlx5_ifc_cmd_inter_comp_event_bits { 2683 u8 command_completion_vector[0x20]; 2684 2685 u8 reserved_at_20[0xc0]; 2686 }; 2687 2688 struct mlx5_ifc_stall_vl_event_bits { 2689 u8 reserved_at_0[0x18]; 2690 u8 port_num[0x1]; 2691 u8 reserved_at_19[0x3]; 2692 u8 vl[0x4]; 2693 2694 u8 reserved_at_20[0xa0]; 2695 }; 2696 2697 struct mlx5_ifc_db_bf_congestion_event_bits { 2698 u8 event_subtype[0x8]; 2699 u8 reserved_at_8[0x8]; 2700 u8 congestion_level[0x8]; 2701 u8 reserved_at_18[0x8]; 2702 2703 u8 reserved_at_20[0xa0]; 2704 }; 2705 2706 struct mlx5_ifc_gpio_event_bits { 2707 u8 reserved_at_0[0x60]; 2708 2709 u8 gpio_event_hi[0x20]; 2710 2711 u8 gpio_event_lo[0x20]; 2712 2713 u8 reserved_at_a0[0x40]; 2714 }; 2715 2716 struct mlx5_ifc_port_state_change_event_bits { 2717 u8 reserved_at_0[0x40]; 2718 2719 u8 port_num[0x4]; 2720 u8 reserved_at_44[0x1c]; 2721 2722 u8 reserved_at_60[0x80]; 2723 }; 2724 2725 struct mlx5_ifc_dropped_packet_logged_bits { 2726 u8 reserved_at_0[0xe0]; 2727 }; 2728 2729 enum { 2730 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1, 2731 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2, 2732 }; 2733 2734 struct mlx5_ifc_cq_error_bits { 2735 u8 reserved_at_0[0x8]; 2736 u8 cqn[0x18]; 2737 2738 u8 reserved_at_20[0x20]; 2739 2740 u8 reserved_at_40[0x18]; 2741 u8 syndrome[0x8]; 2742 2743 u8 reserved_at_60[0x80]; 2744 }; 2745 2746 struct mlx5_ifc_rdma_page_fault_event_bits { 2747 u8 bytes_committed[0x20]; 2748 2749 u8 r_key[0x20]; 2750 2751 u8 reserved_at_40[0x10]; 2752 u8 packet_len[0x10]; 2753 2754 u8 rdma_op_len[0x20]; 2755 2756 u8 rdma_va[0x40]; 2757 2758 u8 reserved_at_c0[0x5]; 2759 u8 rdma[0x1]; 2760 u8 write[0x1]; 2761 u8 requestor[0x1]; 2762 u8 qp_number[0x18]; 2763 }; 2764 2765 struct mlx5_ifc_wqe_associated_page_fault_event_bits { 2766 u8 bytes_committed[0x20]; 2767 2768 u8 reserved_at_20[0x10]; 2769 u8 wqe_index[0x10]; 2770 2771 u8 reserved_at_40[0x10]; 2772 u8 len[0x10]; 2773 2774 u8 reserved_at_60[0x60]; 2775 2776 u8 reserved_at_c0[0x5]; 2777 u8 rdma[0x1]; 2778 u8 write_read[0x1]; 2779 u8 requestor[0x1]; 2780 u8 qpn[0x18]; 2781 }; 2782 2783 struct mlx5_ifc_qp_events_bits { 2784 u8 reserved_at_0[0xa0]; 2785 2786 u8 type[0x8]; 2787 u8 reserved_at_a8[0x18]; 2788 2789 u8 reserved_at_c0[0x8]; 2790 u8 qpn_rqn_sqn[0x18]; 2791 }; 2792 2793 struct mlx5_ifc_dct_events_bits { 2794 u8 reserved_at_0[0xc0]; 2795 2796 u8 reserved_at_c0[0x8]; 2797 u8 dct_number[0x18]; 2798 }; 2799 2800 struct mlx5_ifc_comp_event_bits { 2801 u8 reserved_at_0[0xc0]; 2802 2803 u8 reserved_at_c0[0x8]; 2804 u8 cq_number[0x18]; 2805 }; 2806 2807 enum { 2808 MLX5_QPC_STATE_RST = 0x0, 2809 MLX5_QPC_STATE_INIT = 0x1, 2810 MLX5_QPC_STATE_RTR = 0x2, 2811 MLX5_QPC_STATE_RTS = 0x3, 2812 MLX5_QPC_STATE_SQER = 0x4, 2813 MLX5_QPC_STATE_ERR = 0x6, 2814 MLX5_QPC_STATE_SQD = 0x7, 2815 MLX5_QPC_STATE_SUSPENDED = 0x9, 2816 }; 2817 2818 enum { 2819 MLX5_QPC_ST_RC = 0x0, 2820 MLX5_QPC_ST_UC = 0x1, 2821 MLX5_QPC_ST_UD = 0x2, 2822 MLX5_QPC_ST_XRC = 0x3, 2823 MLX5_QPC_ST_DCI = 0x5, 2824 MLX5_QPC_ST_QP0 = 0x7, 2825 MLX5_QPC_ST_QP1 = 0x8, 2826 MLX5_QPC_ST_RAW_DATAGRAM = 0x9, 2827 MLX5_QPC_ST_REG_UMR = 0xc, 2828 }; 2829 2830 enum { 2831 MLX5_QPC_PM_STATE_ARMED = 0x0, 2832 MLX5_QPC_PM_STATE_REARM = 0x1, 2833 MLX5_QPC_PM_STATE_RESERVED = 0x2, 2834 MLX5_QPC_PM_STATE_MIGRATED = 0x3, 2835 }; 2836 2837 enum { 2838 MLX5_QPC_OFFLOAD_TYPE_RNDV = 0x1, 2839 }; 2840 2841 enum { 2842 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0, 2843 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1, 2844 }; 2845 2846 enum { 2847 MLX5_QPC_MTU_256_BYTES = 0x1, 2848 MLX5_QPC_MTU_512_BYTES = 0x2, 2849 MLX5_QPC_MTU_1K_BYTES = 0x3, 2850 MLX5_QPC_MTU_2K_BYTES = 0x4, 2851 MLX5_QPC_MTU_4K_BYTES = 0x5, 2852 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7, 2853 }; 2854 2855 enum { 2856 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1, 2857 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2, 2858 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3, 2859 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4, 2860 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5, 2861 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6, 2862 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7, 2863 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8, 2864 }; 2865 2866 enum { 2867 MLX5_QPC_CS_REQ_DISABLE = 0x0, 2868 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11, 2869 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22, 2870 }; 2871 2872 enum { 2873 MLX5_QPC_CS_RES_DISABLE = 0x0, 2874 MLX5_QPC_CS_RES_UP_TO_32B = 0x1, 2875 MLX5_QPC_CS_RES_UP_TO_64B = 0x2, 2876 }; 2877 2878 struct mlx5_ifc_qpc_bits { 2879 u8 state[0x4]; 2880 u8 lag_tx_port_affinity[0x4]; 2881 u8 st[0x8]; 2882 u8 reserved_at_10[0x3]; 2883 u8 pm_state[0x2]; 2884 u8 reserved_at_15[0x1]; 2885 u8 req_e2e_credit_mode[0x2]; 2886 u8 offload_type[0x4]; 2887 u8 end_padding_mode[0x2]; 2888 u8 reserved_at_1e[0x2]; 2889 2890 u8 wq_signature[0x1]; 2891 u8 block_lb_mc[0x1]; 2892 u8 atomic_like_write_en[0x1]; 2893 u8 latency_sensitive[0x1]; 2894 u8 reserved_at_24[0x1]; 2895 u8 drain_sigerr[0x1]; 2896 u8 reserved_at_26[0x2]; 2897 u8 pd[0x18]; 2898 2899 u8 mtu[0x3]; 2900 u8 log_msg_max[0x5]; 2901 u8 reserved_at_48[0x1]; 2902 u8 log_rq_size[0x4]; 2903 u8 log_rq_stride[0x3]; 2904 u8 no_sq[0x1]; 2905 u8 log_sq_size[0x4]; 2906 u8 reserved_at_55[0x6]; 2907 u8 rlky[0x1]; 2908 u8 ulp_stateless_offload_mode[0x4]; 2909 2910 u8 counter_set_id[0x8]; 2911 u8 uar_page[0x18]; 2912 2913 u8 reserved_at_80[0x8]; 2914 u8 user_index[0x18]; 2915 2916 u8 reserved_at_a0[0x3]; 2917 u8 log_page_size[0x5]; 2918 u8 remote_qpn[0x18]; 2919 2920 struct mlx5_ifc_ads_bits primary_address_path; 2921 2922 struct mlx5_ifc_ads_bits secondary_address_path; 2923 2924 u8 log_ack_req_freq[0x4]; 2925 u8 reserved_at_384[0x4]; 2926 u8 log_sra_max[0x3]; 2927 u8 reserved_at_38b[0x2]; 2928 u8 retry_count[0x3]; 2929 u8 rnr_retry[0x3]; 2930 u8 reserved_at_393[0x1]; 2931 u8 fre[0x1]; 2932 u8 cur_rnr_retry[0x3]; 2933 u8 cur_retry_count[0x3]; 2934 u8 reserved_at_39b[0x5]; 2935 2936 u8 reserved_at_3a0[0x20]; 2937 2938 u8 reserved_at_3c0[0x8]; 2939 u8 next_send_psn[0x18]; 2940 2941 u8 reserved_at_3e0[0x8]; 2942 u8 cqn_snd[0x18]; 2943 2944 u8 reserved_at_400[0x8]; 2945 u8 deth_sqpn[0x18]; 2946 2947 u8 reserved_at_420[0x20]; 2948 2949 u8 reserved_at_440[0x8]; 2950 u8 last_acked_psn[0x18]; 2951 2952 u8 reserved_at_460[0x8]; 2953 u8 ssn[0x18]; 2954 2955 u8 reserved_at_480[0x8]; 2956 u8 log_rra_max[0x3]; 2957 u8 reserved_at_48b[0x1]; 2958 u8 atomic_mode[0x4]; 2959 u8 rre[0x1]; 2960 u8 rwe[0x1]; 2961 u8 rae[0x1]; 2962 u8 reserved_at_493[0x1]; 2963 u8 page_offset[0x6]; 2964 u8 reserved_at_49a[0x3]; 2965 u8 cd_slave_receive[0x1]; 2966 u8 cd_slave_send[0x1]; 2967 u8 cd_master[0x1]; 2968 2969 u8 reserved_at_4a0[0x3]; 2970 u8 min_rnr_nak[0x5]; 2971 u8 next_rcv_psn[0x18]; 2972 2973 u8 reserved_at_4c0[0x8]; 2974 u8 xrcd[0x18]; 2975 2976 u8 reserved_at_4e0[0x8]; 2977 u8 cqn_rcv[0x18]; 2978 2979 u8 dbr_addr[0x40]; 2980 2981 u8 q_key[0x20]; 2982 2983 u8 reserved_at_560[0x5]; 2984 u8 rq_type[0x3]; 2985 u8 srqn_rmpn_xrqn[0x18]; 2986 2987 u8 reserved_at_580[0x8]; 2988 u8 rmsn[0x18]; 2989 2990 u8 hw_sq_wqebb_counter[0x10]; 2991 u8 sw_sq_wqebb_counter[0x10]; 2992 2993 u8 hw_rq_counter[0x20]; 2994 2995 u8 sw_rq_counter[0x20]; 2996 2997 u8 reserved_at_600[0x20]; 2998 2999 u8 reserved_at_620[0xf]; 3000 u8 cgs[0x1]; 3001 u8 cs_req[0x8]; 3002 u8 cs_res[0x8]; 3003 3004 u8 dc_access_key[0x40]; 3005 3006 u8 reserved_at_680[0x3]; 3007 u8 dbr_umem_valid[0x1]; 3008 3009 u8 reserved_at_684[0xbc]; 3010 }; 3011 3012 struct mlx5_ifc_roce_addr_layout_bits { 3013 u8 source_l3_address[16][0x8]; 3014 3015 u8 reserved_at_80[0x3]; 3016 u8 vlan_valid[0x1]; 3017 u8 vlan_id[0xc]; 3018 u8 source_mac_47_32[0x10]; 3019 3020 u8 source_mac_31_0[0x20]; 3021 3022 u8 reserved_at_c0[0x14]; 3023 u8 roce_l3_type[0x4]; 3024 u8 roce_version[0x8]; 3025 3026 u8 reserved_at_e0[0x20]; 3027 }; 3028 3029 union mlx5_ifc_hca_cap_union_bits { 3030 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap; 3031 struct mlx5_ifc_odp_cap_bits odp_cap; 3032 struct mlx5_ifc_atomic_caps_bits atomic_caps; 3033 struct mlx5_ifc_roce_cap_bits roce_cap; 3034 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps; 3035 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap; 3036 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap; 3037 struct mlx5_ifc_e_switch_cap_bits e_switch_cap; 3038 struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap; 3039 struct mlx5_ifc_qos_cap_bits qos_cap; 3040 struct mlx5_ifc_debug_cap_bits debug_cap; 3041 struct mlx5_ifc_fpga_cap_bits fpga_cap; 3042 struct mlx5_ifc_tls_cap_bits tls_cap; 3043 struct mlx5_ifc_device_mem_cap_bits device_mem_cap; 3044 struct mlx5_ifc_virtio_emulation_cap_bits virtio_emulation_cap; 3045 u8 reserved_at_0[0x8000]; 3046 }; 3047 3048 enum { 3049 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1, 3050 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2, 3051 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4, 3052 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8, 3053 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT = 0x10, 3054 MLX5_FLOW_CONTEXT_ACTION_DECAP = 0x20, 3055 MLX5_FLOW_CONTEXT_ACTION_MOD_HDR = 0x40, 3056 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP = 0x80, 3057 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100, 3058 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2 = 0x400, 3059 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2 = 0x800, 3060 MLX5_FLOW_CONTEXT_ACTION_IPSEC_DECRYPT = 0x1000, 3061 MLX5_FLOW_CONTEXT_ACTION_IPSEC_ENCRYPT = 0x2000, 3062 }; 3063 3064 enum { 3065 MLX5_FLOW_CONTEXT_FLOW_SOURCE_ANY_VPORT = 0x0, 3066 MLX5_FLOW_CONTEXT_FLOW_SOURCE_UPLINK = 0x1, 3067 MLX5_FLOW_CONTEXT_FLOW_SOURCE_LOCAL_VPORT = 0x2, 3068 }; 3069 3070 struct mlx5_ifc_vlan_bits { 3071 u8 ethtype[0x10]; 3072 u8 prio[0x3]; 3073 u8 cfi[0x1]; 3074 u8 vid[0xc]; 3075 }; 3076 3077 struct mlx5_ifc_flow_context_bits { 3078 struct mlx5_ifc_vlan_bits push_vlan; 3079 3080 u8 group_id[0x20]; 3081 3082 u8 reserved_at_40[0x8]; 3083 u8 flow_tag[0x18]; 3084 3085 u8 reserved_at_60[0x10]; 3086 u8 action[0x10]; 3087 3088 u8 extended_destination[0x1]; 3089 u8 reserved_at_81[0x1]; 3090 u8 flow_source[0x2]; 3091 u8 reserved_at_84[0x4]; 3092 u8 destination_list_size[0x18]; 3093 3094 u8 reserved_at_a0[0x8]; 3095 u8 flow_counter_list_size[0x18]; 3096 3097 u8 packet_reformat_id[0x20]; 3098 3099 u8 modify_header_id[0x20]; 3100 3101 struct mlx5_ifc_vlan_bits push_vlan_2; 3102 3103 u8 ipsec_obj_id[0x20]; 3104 u8 reserved_at_140[0xc0]; 3105 3106 struct mlx5_ifc_fte_match_param_bits match_value; 3107 3108 u8 reserved_at_1200[0x600]; 3109 3110 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[]; 3111 }; 3112 3113 enum { 3114 MLX5_XRC_SRQC_STATE_GOOD = 0x0, 3115 MLX5_XRC_SRQC_STATE_ERROR = 0x1, 3116 }; 3117 3118 struct mlx5_ifc_xrc_srqc_bits { 3119 u8 state[0x4]; 3120 u8 log_xrc_srq_size[0x4]; 3121 u8 reserved_at_8[0x18]; 3122 3123 u8 wq_signature[0x1]; 3124 u8 cont_srq[0x1]; 3125 u8 reserved_at_22[0x1]; 3126 u8 rlky[0x1]; 3127 u8 basic_cyclic_rcv_wqe[0x1]; 3128 u8 log_rq_stride[0x3]; 3129 u8 xrcd[0x18]; 3130 3131 u8 page_offset[0x6]; 3132 u8 reserved_at_46[0x1]; 3133 u8 dbr_umem_valid[0x1]; 3134 u8 cqn[0x18]; 3135 3136 u8 reserved_at_60[0x20]; 3137 3138 u8 user_index_equal_xrc_srqn[0x1]; 3139 u8 reserved_at_81[0x1]; 3140 u8 log_page_size[0x6]; 3141 u8 user_index[0x18]; 3142 3143 u8 reserved_at_a0[0x20]; 3144 3145 u8 reserved_at_c0[0x8]; 3146 u8 pd[0x18]; 3147 3148 u8 lwm[0x10]; 3149 u8 wqe_cnt[0x10]; 3150 3151 u8 reserved_at_100[0x40]; 3152 3153 u8 db_record_addr_h[0x20]; 3154 3155 u8 db_record_addr_l[0x1e]; 3156 u8 reserved_at_17e[0x2]; 3157 3158 u8 reserved_at_180[0x80]; 3159 }; 3160 3161 struct mlx5_ifc_vnic_diagnostic_statistics_bits { 3162 u8 counter_error_queues[0x20]; 3163 3164 u8 total_error_queues[0x20]; 3165 3166 u8 send_queue_priority_update_flow[0x20]; 3167 3168 u8 reserved_at_60[0x20]; 3169 3170 u8 nic_receive_steering_discard[0x40]; 3171 3172 u8 receive_discard_vport_down[0x40]; 3173 3174 u8 transmit_discard_vport_down[0x40]; 3175 3176 u8 reserved_at_140[0xa0]; 3177 3178 u8 internal_rq_out_of_buffer[0x20]; 3179 3180 u8 reserved_at_200[0xe00]; 3181 }; 3182 3183 struct mlx5_ifc_traffic_counter_bits { 3184 u8 packets[0x40]; 3185 3186 u8 octets[0x40]; 3187 }; 3188 3189 struct mlx5_ifc_tisc_bits { 3190 u8 strict_lag_tx_port_affinity[0x1]; 3191 u8 tls_en[0x1]; 3192 u8 reserved_at_2[0x2]; 3193 u8 lag_tx_port_affinity[0x04]; 3194 3195 u8 reserved_at_8[0x4]; 3196 u8 prio[0x4]; 3197 u8 reserved_at_10[0x10]; 3198 3199 u8 reserved_at_20[0x100]; 3200 3201 u8 reserved_at_120[0x8]; 3202 u8 transport_domain[0x18]; 3203 3204 u8 reserved_at_140[0x8]; 3205 u8 underlay_qpn[0x18]; 3206 3207 u8 reserved_at_160[0x8]; 3208 u8 pd[0x18]; 3209 3210 u8 reserved_at_180[0x380]; 3211 }; 3212 3213 enum { 3214 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0, 3215 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1, 3216 }; 3217 3218 enum { 3219 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO = 0x1, 3220 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO = 0x2, 3221 }; 3222 3223 enum { 3224 MLX5_RX_HASH_FN_NONE = 0x0, 3225 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1, 3226 MLX5_RX_HASH_FN_TOEPLITZ = 0x2, 3227 }; 3228 3229 enum { 3230 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST = 0x1, 3231 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST = 0x2, 3232 }; 3233 3234 struct mlx5_ifc_tirc_bits { 3235 u8 reserved_at_0[0x20]; 3236 3237 u8 disp_type[0x4]; 3238 u8 tls_en[0x1]; 3239 u8 reserved_at_25[0x1b]; 3240 3241 u8 reserved_at_40[0x40]; 3242 3243 u8 reserved_at_80[0x4]; 3244 u8 lro_timeout_period_usecs[0x10]; 3245 u8 lro_enable_mask[0x4]; 3246 u8 lro_max_ip_payload_size[0x8]; 3247 3248 u8 reserved_at_a0[0x40]; 3249 3250 u8 reserved_at_e0[0x8]; 3251 u8 inline_rqn[0x18]; 3252 3253 u8 rx_hash_symmetric[0x1]; 3254 u8 reserved_at_101[0x1]; 3255 u8 tunneled_offload_en[0x1]; 3256 u8 reserved_at_103[0x5]; 3257 u8 indirect_table[0x18]; 3258 3259 u8 rx_hash_fn[0x4]; 3260 u8 reserved_at_124[0x2]; 3261 u8 self_lb_block[0x2]; 3262 u8 transport_domain[0x18]; 3263 3264 u8 rx_hash_toeplitz_key[10][0x20]; 3265 3266 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer; 3267 3268 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner; 3269 3270 u8 reserved_at_2c0[0x4c0]; 3271 }; 3272 3273 enum { 3274 MLX5_SRQC_STATE_GOOD = 0x0, 3275 MLX5_SRQC_STATE_ERROR = 0x1, 3276 }; 3277 3278 struct mlx5_ifc_srqc_bits { 3279 u8 state[0x4]; 3280 u8 log_srq_size[0x4]; 3281 u8 reserved_at_8[0x18]; 3282 3283 u8 wq_signature[0x1]; 3284 u8 cont_srq[0x1]; 3285 u8 reserved_at_22[0x1]; 3286 u8 rlky[0x1]; 3287 u8 reserved_at_24[0x1]; 3288 u8 log_rq_stride[0x3]; 3289 u8 xrcd[0x18]; 3290 3291 u8 page_offset[0x6]; 3292 u8 reserved_at_46[0x2]; 3293 u8 cqn[0x18]; 3294 3295 u8 reserved_at_60[0x20]; 3296 3297 u8 reserved_at_80[0x2]; 3298 u8 log_page_size[0x6]; 3299 u8 reserved_at_88[0x18]; 3300 3301 u8 reserved_at_a0[0x20]; 3302 3303 u8 reserved_at_c0[0x8]; 3304 u8 pd[0x18]; 3305 3306 u8 lwm[0x10]; 3307 u8 wqe_cnt[0x10]; 3308 3309 u8 reserved_at_100[0x40]; 3310 3311 u8 dbr_addr[0x40]; 3312 3313 u8 reserved_at_180[0x80]; 3314 }; 3315 3316 enum { 3317 MLX5_SQC_STATE_RST = 0x0, 3318 MLX5_SQC_STATE_RDY = 0x1, 3319 MLX5_SQC_STATE_ERR = 0x3, 3320 }; 3321 3322 struct mlx5_ifc_sqc_bits { 3323 u8 rlky[0x1]; 3324 u8 cd_master[0x1]; 3325 u8 fre[0x1]; 3326 u8 flush_in_error_en[0x1]; 3327 u8 allow_multi_pkt_send_wqe[0x1]; 3328 u8 min_wqe_inline_mode[0x3]; 3329 u8 state[0x4]; 3330 u8 reg_umr[0x1]; 3331 u8 allow_swp[0x1]; 3332 u8 hairpin[0x1]; 3333 u8 reserved_at_f[0x11]; 3334 3335 u8 reserved_at_20[0x8]; 3336 u8 user_index[0x18]; 3337 3338 u8 reserved_at_40[0x8]; 3339 u8 cqn[0x18]; 3340 3341 u8 reserved_at_60[0x8]; 3342 u8 hairpin_peer_rq[0x18]; 3343 3344 u8 reserved_at_80[0x10]; 3345 u8 hairpin_peer_vhca[0x10]; 3346 3347 u8 reserved_at_a0[0x20]; 3348 3349 u8 reserved_at_c0[0x8]; 3350 u8 ts_cqe_to_dest_cqn[0x18]; 3351 3352 u8 reserved_at_e0[0x10]; 3353 u8 packet_pacing_rate_limit_index[0x10]; 3354 u8 tis_lst_sz[0x10]; 3355 u8 qos_queue_group_id[0x10]; 3356 3357 u8 reserved_at_120[0x40]; 3358 3359 u8 reserved_at_160[0x8]; 3360 u8 tis_num_0[0x18]; 3361 3362 struct mlx5_ifc_wq_bits wq; 3363 }; 3364 3365 enum { 3366 SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0, 3367 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1, 3368 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2, 3369 SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3, 3370 SCHEDULING_CONTEXT_ELEMENT_TYPE_QUEUE_GROUP = 0x4, 3371 }; 3372 3373 enum { 3374 ELEMENT_TYPE_CAP_MASK_TASR = 1 << 0, 3375 ELEMENT_TYPE_CAP_MASK_VPORT = 1 << 1, 3376 ELEMENT_TYPE_CAP_MASK_VPORT_TC = 1 << 2, 3377 ELEMENT_TYPE_CAP_MASK_PARA_VPORT_TC = 1 << 3, 3378 }; 3379 3380 struct mlx5_ifc_scheduling_context_bits { 3381 u8 element_type[0x8]; 3382 u8 reserved_at_8[0x18]; 3383 3384 u8 element_attributes[0x20]; 3385 3386 u8 parent_element_id[0x20]; 3387 3388 u8 reserved_at_60[0x40]; 3389 3390 u8 bw_share[0x20]; 3391 3392 u8 max_average_bw[0x20]; 3393 3394 u8 reserved_at_e0[0x120]; 3395 }; 3396 3397 struct mlx5_ifc_rqtc_bits { 3398 u8 reserved_at_0[0xa0]; 3399 3400 u8 reserved_at_a0[0x5]; 3401 u8 list_q_type[0x3]; 3402 u8 reserved_at_a8[0x8]; 3403 u8 rqt_max_size[0x10]; 3404 3405 u8 rq_vhca_id_format[0x1]; 3406 u8 reserved_at_c1[0xf]; 3407 u8 rqt_actual_size[0x10]; 3408 3409 u8 reserved_at_e0[0x6a0]; 3410 3411 struct mlx5_ifc_rq_num_bits rq_num[]; 3412 }; 3413 3414 enum { 3415 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0, 3416 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1, 3417 }; 3418 3419 enum { 3420 MLX5_RQC_STATE_RST = 0x0, 3421 MLX5_RQC_STATE_RDY = 0x1, 3422 MLX5_RQC_STATE_ERR = 0x3, 3423 }; 3424 3425 struct mlx5_ifc_rqc_bits { 3426 u8 rlky[0x1]; 3427 u8 delay_drop_en[0x1]; 3428 u8 scatter_fcs[0x1]; 3429 u8 vsd[0x1]; 3430 u8 mem_rq_type[0x4]; 3431 u8 state[0x4]; 3432 u8 reserved_at_c[0x1]; 3433 u8 flush_in_error_en[0x1]; 3434 u8 hairpin[0x1]; 3435 u8 reserved_at_f[0x11]; 3436 3437 u8 reserved_at_20[0x8]; 3438 u8 user_index[0x18]; 3439 3440 u8 reserved_at_40[0x8]; 3441 u8 cqn[0x18]; 3442 3443 u8 counter_set_id[0x8]; 3444 u8 reserved_at_68[0x18]; 3445 3446 u8 reserved_at_80[0x8]; 3447 u8 rmpn[0x18]; 3448 3449 u8 reserved_at_a0[0x8]; 3450 u8 hairpin_peer_sq[0x18]; 3451 3452 u8 reserved_at_c0[0x10]; 3453 u8 hairpin_peer_vhca[0x10]; 3454 3455 u8 reserved_at_e0[0xa0]; 3456 3457 struct mlx5_ifc_wq_bits wq; 3458 }; 3459 3460 enum { 3461 MLX5_RMPC_STATE_RDY = 0x1, 3462 MLX5_RMPC_STATE_ERR = 0x3, 3463 }; 3464 3465 struct mlx5_ifc_rmpc_bits { 3466 u8 reserved_at_0[0x8]; 3467 u8 state[0x4]; 3468 u8 reserved_at_c[0x14]; 3469 3470 u8 basic_cyclic_rcv_wqe[0x1]; 3471 u8 reserved_at_21[0x1f]; 3472 3473 u8 reserved_at_40[0x140]; 3474 3475 struct mlx5_ifc_wq_bits wq; 3476 }; 3477 3478 struct mlx5_ifc_nic_vport_context_bits { 3479 u8 reserved_at_0[0x5]; 3480 u8 min_wqe_inline_mode[0x3]; 3481 u8 reserved_at_8[0x15]; 3482 u8 disable_mc_local_lb[0x1]; 3483 u8 disable_uc_local_lb[0x1]; 3484 u8 roce_en[0x1]; 3485 3486 u8 arm_change_event[0x1]; 3487 u8 reserved_at_21[0x1a]; 3488 u8 event_on_mtu[0x1]; 3489 u8 event_on_promisc_change[0x1]; 3490 u8 event_on_vlan_change[0x1]; 3491 u8 event_on_mc_address_change[0x1]; 3492 u8 event_on_uc_address_change[0x1]; 3493 3494 u8 reserved_at_40[0xc]; 3495 3496 u8 affiliation_criteria[0x4]; 3497 u8 affiliated_vhca_id[0x10]; 3498 3499 u8 reserved_at_60[0xd0]; 3500 3501 u8 mtu[0x10]; 3502 3503 u8 system_image_guid[0x40]; 3504 u8 port_guid[0x40]; 3505 u8 node_guid[0x40]; 3506 3507 u8 reserved_at_200[0x140]; 3508 u8 qkey_violation_counter[0x10]; 3509 u8 reserved_at_350[0x430]; 3510 3511 u8 promisc_uc[0x1]; 3512 u8 promisc_mc[0x1]; 3513 u8 promisc_all[0x1]; 3514 u8 reserved_at_783[0x2]; 3515 u8 allowed_list_type[0x3]; 3516 u8 reserved_at_788[0xc]; 3517 u8 allowed_list_size[0xc]; 3518 3519 struct mlx5_ifc_mac_address_layout_bits permanent_address; 3520 3521 u8 reserved_at_7e0[0x20]; 3522 3523 u8 current_uc_mac_address[][0x40]; 3524 }; 3525 3526 enum { 3527 MLX5_MKC_ACCESS_MODE_PA = 0x0, 3528 MLX5_MKC_ACCESS_MODE_MTT = 0x1, 3529 MLX5_MKC_ACCESS_MODE_KLMS = 0x2, 3530 MLX5_MKC_ACCESS_MODE_KSM = 0x3, 3531 MLX5_MKC_ACCESS_MODE_SW_ICM = 0x4, 3532 MLX5_MKC_ACCESS_MODE_MEMIC = 0x5, 3533 }; 3534 3535 struct mlx5_ifc_mkc_bits { 3536 u8 reserved_at_0[0x1]; 3537 u8 free[0x1]; 3538 u8 reserved_at_2[0x1]; 3539 u8 access_mode_4_2[0x3]; 3540 u8 reserved_at_6[0x7]; 3541 u8 relaxed_ordering_write[0x1]; 3542 u8 reserved_at_e[0x1]; 3543 u8 small_fence_on_rdma_read_response[0x1]; 3544 u8 umr_en[0x1]; 3545 u8 a[0x1]; 3546 u8 rw[0x1]; 3547 u8 rr[0x1]; 3548 u8 lw[0x1]; 3549 u8 lr[0x1]; 3550 u8 access_mode_1_0[0x2]; 3551 u8 reserved_at_18[0x8]; 3552 3553 u8 qpn[0x18]; 3554 u8 mkey_7_0[0x8]; 3555 3556 u8 reserved_at_40[0x20]; 3557 3558 u8 length64[0x1]; 3559 u8 bsf_en[0x1]; 3560 u8 sync_umr[0x1]; 3561 u8 reserved_at_63[0x2]; 3562 u8 expected_sigerr_count[0x1]; 3563 u8 reserved_at_66[0x1]; 3564 u8 en_rinval[0x1]; 3565 u8 pd[0x18]; 3566 3567 u8 start_addr[0x40]; 3568 3569 u8 len[0x40]; 3570 3571 u8 bsf_octword_size[0x20]; 3572 3573 u8 reserved_at_120[0x80]; 3574 3575 u8 translations_octword_size[0x20]; 3576 3577 u8 reserved_at_1c0[0x19]; 3578 u8 relaxed_ordering_read[0x1]; 3579 u8 reserved_at_1d9[0x1]; 3580 u8 log_page_size[0x5]; 3581 3582 u8 reserved_at_1e0[0x20]; 3583 }; 3584 3585 struct mlx5_ifc_pkey_bits { 3586 u8 reserved_at_0[0x10]; 3587 u8 pkey[0x10]; 3588 }; 3589 3590 struct mlx5_ifc_array128_auto_bits { 3591 u8 array128_auto[16][0x8]; 3592 }; 3593 3594 struct mlx5_ifc_hca_vport_context_bits { 3595 u8 field_select[0x20]; 3596 3597 u8 reserved_at_20[0xe0]; 3598 3599 u8 sm_virt_aware[0x1]; 3600 u8 has_smi[0x1]; 3601 u8 has_raw[0x1]; 3602 u8 grh_required[0x1]; 3603 u8 reserved_at_104[0xc]; 3604 u8 port_physical_state[0x4]; 3605 u8 vport_state_policy[0x4]; 3606 u8 port_state[0x4]; 3607 u8 vport_state[0x4]; 3608 3609 u8 reserved_at_120[0x20]; 3610 3611 u8 system_image_guid[0x40]; 3612 3613 u8 port_guid[0x40]; 3614 3615 u8 node_guid[0x40]; 3616 3617 u8 cap_mask1[0x20]; 3618 3619 u8 cap_mask1_field_select[0x20]; 3620 3621 u8 cap_mask2[0x20]; 3622 3623 u8 cap_mask2_field_select[0x20]; 3624 3625 u8 reserved_at_280[0x80]; 3626 3627 u8 lid[0x10]; 3628 u8 reserved_at_310[0x4]; 3629 u8 init_type_reply[0x4]; 3630 u8 lmc[0x3]; 3631 u8 subnet_timeout[0x5]; 3632 3633 u8 sm_lid[0x10]; 3634 u8 sm_sl[0x4]; 3635 u8 reserved_at_334[0xc]; 3636 3637 u8 qkey_violation_counter[0x10]; 3638 u8 pkey_violation_counter[0x10]; 3639 3640 u8 reserved_at_360[0xca0]; 3641 }; 3642 3643 struct mlx5_ifc_esw_vport_context_bits { 3644 u8 fdb_to_vport_reg_c[0x1]; 3645 u8 reserved_at_1[0x2]; 3646 u8 vport_svlan_strip[0x1]; 3647 u8 vport_cvlan_strip[0x1]; 3648 u8 vport_svlan_insert[0x1]; 3649 u8 vport_cvlan_insert[0x2]; 3650 u8 fdb_to_vport_reg_c_id[0x8]; 3651 u8 reserved_at_10[0x10]; 3652 3653 u8 reserved_at_20[0x20]; 3654 3655 u8 svlan_cfi[0x1]; 3656 u8 svlan_pcp[0x3]; 3657 u8 svlan_id[0xc]; 3658 u8 cvlan_cfi[0x1]; 3659 u8 cvlan_pcp[0x3]; 3660 u8 cvlan_id[0xc]; 3661 3662 u8 reserved_at_60[0x720]; 3663 3664 u8 sw_steering_vport_icm_address_rx[0x40]; 3665 3666 u8 sw_steering_vport_icm_address_tx[0x40]; 3667 }; 3668 3669 enum { 3670 MLX5_EQC_STATUS_OK = 0x0, 3671 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa, 3672 }; 3673 3674 enum { 3675 MLX5_EQC_ST_ARMED = 0x9, 3676 MLX5_EQC_ST_FIRED = 0xa, 3677 }; 3678 3679 struct mlx5_ifc_eqc_bits { 3680 u8 status[0x4]; 3681 u8 reserved_at_4[0x9]; 3682 u8 ec[0x1]; 3683 u8 oi[0x1]; 3684 u8 reserved_at_f[0x5]; 3685 u8 st[0x4]; 3686 u8 reserved_at_18[0x8]; 3687 3688 u8 reserved_at_20[0x20]; 3689 3690 u8 reserved_at_40[0x14]; 3691 u8 page_offset[0x6]; 3692 u8 reserved_at_5a[0x6]; 3693 3694 u8 reserved_at_60[0x3]; 3695 u8 log_eq_size[0x5]; 3696 u8 uar_page[0x18]; 3697 3698 u8 reserved_at_80[0x20]; 3699 3700 u8 reserved_at_a0[0x18]; 3701 u8 intr[0x8]; 3702 3703 u8 reserved_at_c0[0x3]; 3704 u8 log_page_size[0x5]; 3705 u8 reserved_at_c8[0x18]; 3706 3707 u8 reserved_at_e0[0x60]; 3708 3709 u8 reserved_at_140[0x8]; 3710 u8 consumer_counter[0x18]; 3711 3712 u8 reserved_at_160[0x8]; 3713 u8 producer_counter[0x18]; 3714 3715 u8 reserved_at_180[0x80]; 3716 }; 3717 3718 enum { 3719 MLX5_DCTC_STATE_ACTIVE = 0x0, 3720 MLX5_DCTC_STATE_DRAINING = 0x1, 3721 MLX5_DCTC_STATE_DRAINED = 0x2, 3722 }; 3723 3724 enum { 3725 MLX5_DCTC_CS_RES_DISABLE = 0x0, 3726 MLX5_DCTC_CS_RES_NA = 0x1, 3727 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2, 3728 }; 3729 3730 enum { 3731 MLX5_DCTC_MTU_256_BYTES = 0x1, 3732 MLX5_DCTC_MTU_512_BYTES = 0x2, 3733 MLX5_DCTC_MTU_1K_BYTES = 0x3, 3734 MLX5_DCTC_MTU_2K_BYTES = 0x4, 3735 MLX5_DCTC_MTU_4K_BYTES = 0x5, 3736 }; 3737 3738 struct mlx5_ifc_dctc_bits { 3739 u8 reserved_at_0[0x4]; 3740 u8 state[0x4]; 3741 u8 reserved_at_8[0x18]; 3742 3743 u8 reserved_at_20[0x8]; 3744 u8 user_index[0x18]; 3745 3746 u8 reserved_at_40[0x8]; 3747 u8 cqn[0x18]; 3748 3749 u8 counter_set_id[0x8]; 3750 u8 atomic_mode[0x4]; 3751 u8 rre[0x1]; 3752 u8 rwe[0x1]; 3753 u8 rae[0x1]; 3754 u8 atomic_like_write_en[0x1]; 3755 u8 latency_sensitive[0x1]; 3756 u8 rlky[0x1]; 3757 u8 free_ar[0x1]; 3758 u8 reserved_at_73[0xd]; 3759 3760 u8 reserved_at_80[0x8]; 3761 u8 cs_res[0x8]; 3762 u8 reserved_at_90[0x3]; 3763 u8 min_rnr_nak[0x5]; 3764 u8 reserved_at_98[0x8]; 3765 3766 u8 reserved_at_a0[0x8]; 3767 u8 srqn_xrqn[0x18]; 3768 3769 u8 reserved_at_c0[0x8]; 3770 u8 pd[0x18]; 3771 3772 u8 tclass[0x8]; 3773 u8 reserved_at_e8[0x4]; 3774 u8 flow_label[0x14]; 3775 3776 u8 dc_access_key[0x40]; 3777 3778 u8 reserved_at_140[0x5]; 3779 u8 mtu[0x3]; 3780 u8 port[0x8]; 3781 u8 pkey_index[0x10]; 3782 3783 u8 reserved_at_160[0x8]; 3784 u8 my_addr_index[0x8]; 3785 u8 reserved_at_170[0x8]; 3786 u8 hop_limit[0x8]; 3787 3788 u8 dc_access_key_violation_count[0x20]; 3789 3790 u8 reserved_at_1a0[0x14]; 3791 u8 dei_cfi[0x1]; 3792 u8 eth_prio[0x3]; 3793 u8 ecn[0x2]; 3794 u8 dscp[0x6]; 3795 3796 u8 reserved_at_1c0[0x20]; 3797 u8 ece[0x20]; 3798 }; 3799 3800 enum { 3801 MLX5_CQC_STATUS_OK = 0x0, 3802 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9, 3803 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa, 3804 }; 3805 3806 enum { 3807 MLX5_CQC_CQE_SZ_64_BYTES = 0x0, 3808 MLX5_CQC_CQE_SZ_128_BYTES = 0x1, 3809 }; 3810 3811 enum { 3812 MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED = 0x6, 3813 MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED = 0x9, 3814 MLX5_CQC_ST_FIRED = 0xa, 3815 }; 3816 3817 enum { 3818 MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0, 3819 MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1, 3820 MLX5_CQ_PERIOD_NUM_MODES 3821 }; 3822 3823 struct mlx5_ifc_cqc_bits { 3824 u8 status[0x4]; 3825 u8 reserved_at_4[0x2]; 3826 u8 dbr_umem_valid[0x1]; 3827 u8 reserved_at_7[0x1]; 3828 u8 cqe_sz[0x3]; 3829 u8 cc[0x1]; 3830 u8 reserved_at_c[0x1]; 3831 u8 scqe_break_moderation_en[0x1]; 3832 u8 oi[0x1]; 3833 u8 cq_period_mode[0x2]; 3834 u8 cqe_comp_en[0x1]; 3835 u8 mini_cqe_res_format[0x2]; 3836 u8 st[0x4]; 3837 u8 reserved_at_18[0x8]; 3838 3839 u8 reserved_at_20[0x20]; 3840 3841 u8 reserved_at_40[0x14]; 3842 u8 page_offset[0x6]; 3843 u8 reserved_at_5a[0x6]; 3844 3845 u8 reserved_at_60[0x3]; 3846 u8 log_cq_size[0x5]; 3847 u8 uar_page[0x18]; 3848 3849 u8 reserved_at_80[0x4]; 3850 u8 cq_period[0xc]; 3851 u8 cq_max_count[0x10]; 3852 3853 u8 reserved_at_a0[0x18]; 3854 u8 c_eqn[0x8]; 3855 3856 u8 reserved_at_c0[0x3]; 3857 u8 log_page_size[0x5]; 3858 u8 reserved_at_c8[0x18]; 3859 3860 u8 reserved_at_e0[0x20]; 3861 3862 u8 reserved_at_100[0x8]; 3863 u8 last_notified_index[0x18]; 3864 3865 u8 reserved_at_120[0x8]; 3866 u8 last_solicit_index[0x18]; 3867 3868 u8 reserved_at_140[0x8]; 3869 u8 consumer_counter[0x18]; 3870 3871 u8 reserved_at_160[0x8]; 3872 u8 producer_counter[0x18]; 3873 3874 u8 reserved_at_180[0x40]; 3875 3876 u8 dbr_addr[0x40]; 3877 }; 3878 3879 union mlx5_ifc_cong_control_roce_ecn_auto_bits { 3880 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp; 3881 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp; 3882 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np; 3883 u8 reserved_at_0[0x800]; 3884 }; 3885 3886 struct mlx5_ifc_query_adapter_param_block_bits { 3887 u8 reserved_at_0[0xc0]; 3888 3889 u8 reserved_at_c0[0x8]; 3890 u8 ieee_vendor_id[0x18]; 3891 3892 u8 reserved_at_e0[0x10]; 3893 u8 vsd_vendor_id[0x10]; 3894 3895 u8 vsd[208][0x8]; 3896 3897 u8 vsd_contd_psid[16][0x8]; 3898 }; 3899 3900 enum { 3901 MLX5_XRQC_STATE_GOOD = 0x0, 3902 MLX5_XRQC_STATE_ERROR = 0x1, 3903 }; 3904 3905 enum { 3906 MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0, 3907 MLX5_XRQC_TOPOLOGY_TAG_MATCHING = 0x1, 3908 }; 3909 3910 enum { 3911 MLX5_XRQC_OFFLOAD_RNDV = 0x1, 3912 }; 3913 3914 struct mlx5_ifc_tag_matching_topology_context_bits { 3915 u8 log_matching_list_sz[0x4]; 3916 u8 reserved_at_4[0xc]; 3917 u8 append_next_index[0x10]; 3918 3919 u8 sw_phase_cnt[0x10]; 3920 u8 hw_phase_cnt[0x10]; 3921 3922 u8 reserved_at_40[0x40]; 3923 }; 3924 3925 struct mlx5_ifc_xrqc_bits { 3926 u8 state[0x4]; 3927 u8 rlkey[0x1]; 3928 u8 reserved_at_5[0xf]; 3929 u8 topology[0x4]; 3930 u8 reserved_at_18[0x4]; 3931 u8 offload[0x4]; 3932 3933 u8 reserved_at_20[0x8]; 3934 u8 user_index[0x18]; 3935 3936 u8 reserved_at_40[0x8]; 3937 u8 cqn[0x18]; 3938 3939 u8 reserved_at_60[0xa0]; 3940 3941 struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context; 3942 3943 u8 reserved_at_180[0x280]; 3944 3945 struct mlx5_ifc_wq_bits wq; 3946 }; 3947 3948 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits { 3949 struct mlx5_ifc_modify_field_select_bits modify_field_select; 3950 struct mlx5_ifc_resize_field_select_bits resize_field_select; 3951 u8 reserved_at_0[0x20]; 3952 }; 3953 3954 union mlx5_ifc_field_select_802_1_r_roce_auto_bits { 3955 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp; 3956 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp; 3957 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np; 3958 u8 reserved_at_0[0x20]; 3959 }; 3960 3961 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits { 3962 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 3963 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 3964 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 3965 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 3966 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 3967 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 3968 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout; 3969 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout; 3970 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 3971 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 3972 struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs; 3973 u8 reserved_at_0[0x7c0]; 3974 }; 3975 3976 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits { 3977 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout; 3978 u8 reserved_at_0[0x7c0]; 3979 }; 3980 3981 union mlx5_ifc_event_auto_bits { 3982 struct mlx5_ifc_comp_event_bits comp_event; 3983 struct mlx5_ifc_dct_events_bits dct_events; 3984 struct mlx5_ifc_qp_events_bits qp_events; 3985 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event; 3986 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event; 3987 struct mlx5_ifc_cq_error_bits cq_error; 3988 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged; 3989 struct mlx5_ifc_port_state_change_event_bits port_state_change_event; 3990 struct mlx5_ifc_gpio_event_bits gpio_event; 3991 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event; 3992 struct mlx5_ifc_stall_vl_event_bits stall_vl_event; 3993 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event; 3994 u8 reserved_at_0[0xe0]; 3995 }; 3996 3997 struct mlx5_ifc_health_buffer_bits { 3998 u8 reserved_at_0[0x100]; 3999 4000 u8 assert_existptr[0x20]; 4001 4002 u8 assert_callra[0x20]; 4003 4004 u8 reserved_at_140[0x40]; 4005 4006 u8 fw_version[0x20]; 4007 4008 u8 hw_id[0x20]; 4009 4010 u8 reserved_at_1c0[0x20]; 4011 4012 u8 irisc_index[0x8]; 4013 u8 synd[0x8]; 4014 u8 ext_synd[0x10]; 4015 }; 4016 4017 struct mlx5_ifc_register_loopback_control_bits { 4018 u8 no_lb[0x1]; 4019 u8 reserved_at_1[0x7]; 4020 u8 port[0x8]; 4021 u8 reserved_at_10[0x10]; 4022 4023 u8 reserved_at_20[0x60]; 4024 }; 4025 4026 struct mlx5_ifc_vport_tc_element_bits { 4027 u8 traffic_class[0x4]; 4028 u8 reserved_at_4[0xc]; 4029 u8 vport_number[0x10]; 4030 }; 4031 4032 struct mlx5_ifc_vport_element_bits { 4033 u8 reserved_at_0[0x10]; 4034 u8 vport_number[0x10]; 4035 }; 4036 4037 enum { 4038 TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0, 4039 TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1, 4040 TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2, 4041 }; 4042 4043 struct mlx5_ifc_tsar_element_bits { 4044 u8 reserved_at_0[0x8]; 4045 u8 tsar_type[0x8]; 4046 u8 reserved_at_10[0x10]; 4047 }; 4048 4049 enum { 4050 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0, 4051 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1, 4052 }; 4053 4054 struct mlx5_ifc_teardown_hca_out_bits { 4055 u8 status[0x8]; 4056 u8 reserved_at_8[0x18]; 4057 4058 u8 syndrome[0x20]; 4059 4060 u8 reserved_at_40[0x3f]; 4061 4062 u8 state[0x1]; 4063 }; 4064 4065 enum { 4066 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0, 4067 MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE = 0x1, 4068 MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN = 0x2, 4069 }; 4070 4071 struct mlx5_ifc_teardown_hca_in_bits { 4072 u8 opcode[0x10]; 4073 u8 reserved_at_10[0x10]; 4074 4075 u8 reserved_at_20[0x10]; 4076 u8 op_mod[0x10]; 4077 4078 u8 reserved_at_40[0x10]; 4079 u8 profile[0x10]; 4080 4081 u8 reserved_at_60[0x20]; 4082 }; 4083 4084 struct mlx5_ifc_sqerr2rts_qp_out_bits { 4085 u8 status[0x8]; 4086 u8 reserved_at_8[0x18]; 4087 4088 u8 syndrome[0x20]; 4089 4090 u8 reserved_at_40[0x40]; 4091 }; 4092 4093 struct mlx5_ifc_sqerr2rts_qp_in_bits { 4094 u8 opcode[0x10]; 4095 u8 uid[0x10]; 4096 4097 u8 reserved_at_20[0x10]; 4098 u8 op_mod[0x10]; 4099 4100 u8 reserved_at_40[0x8]; 4101 u8 qpn[0x18]; 4102 4103 u8 reserved_at_60[0x20]; 4104 4105 u8 opt_param_mask[0x20]; 4106 4107 u8 reserved_at_a0[0x20]; 4108 4109 struct mlx5_ifc_qpc_bits qpc; 4110 4111 u8 reserved_at_800[0x80]; 4112 }; 4113 4114 struct mlx5_ifc_sqd2rts_qp_out_bits { 4115 u8 status[0x8]; 4116 u8 reserved_at_8[0x18]; 4117 4118 u8 syndrome[0x20]; 4119 4120 u8 reserved_at_40[0x40]; 4121 }; 4122 4123 struct mlx5_ifc_sqd2rts_qp_in_bits { 4124 u8 opcode[0x10]; 4125 u8 uid[0x10]; 4126 4127 u8 reserved_at_20[0x10]; 4128 u8 op_mod[0x10]; 4129 4130 u8 reserved_at_40[0x8]; 4131 u8 qpn[0x18]; 4132 4133 u8 reserved_at_60[0x20]; 4134 4135 u8 opt_param_mask[0x20]; 4136 4137 u8 reserved_at_a0[0x20]; 4138 4139 struct mlx5_ifc_qpc_bits qpc; 4140 4141 u8 reserved_at_800[0x80]; 4142 }; 4143 4144 struct mlx5_ifc_set_roce_address_out_bits { 4145 u8 status[0x8]; 4146 u8 reserved_at_8[0x18]; 4147 4148 u8 syndrome[0x20]; 4149 4150 u8 reserved_at_40[0x40]; 4151 }; 4152 4153 struct mlx5_ifc_set_roce_address_in_bits { 4154 u8 opcode[0x10]; 4155 u8 reserved_at_10[0x10]; 4156 4157 u8 reserved_at_20[0x10]; 4158 u8 op_mod[0x10]; 4159 4160 u8 roce_address_index[0x10]; 4161 u8 reserved_at_50[0xc]; 4162 u8 vhca_port_num[0x4]; 4163 4164 u8 reserved_at_60[0x20]; 4165 4166 struct mlx5_ifc_roce_addr_layout_bits roce_address; 4167 }; 4168 4169 struct mlx5_ifc_set_mad_demux_out_bits { 4170 u8 status[0x8]; 4171 u8 reserved_at_8[0x18]; 4172 4173 u8 syndrome[0x20]; 4174 4175 u8 reserved_at_40[0x40]; 4176 }; 4177 4178 enum { 4179 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0, 4180 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2, 4181 }; 4182 4183 struct mlx5_ifc_set_mad_demux_in_bits { 4184 u8 opcode[0x10]; 4185 u8 reserved_at_10[0x10]; 4186 4187 u8 reserved_at_20[0x10]; 4188 u8 op_mod[0x10]; 4189 4190 u8 reserved_at_40[0x20]; 4191 4192 u8 reserved_at_60[0x6]; 4193 u8 demux_mode[0x2]; 4194 u8 reserved_at_68[0x18]; 4195 }; 4196 4197 struct mlx5_ifc_set_l2_table_entry_out_bits { 4198 u8 status[0x8]; 4199 u8 reserved_at_8[0x18]; 4200 4201 u8 syndrome[0x20]; 4202 4203 u8 reserved_at_40[0x40]; 4204 }; 4205 4206 struct mlx5_ifc_set_l2_table_entry_in_bits { 4207 u8 opcode[0x10]; 4208 u8 reserved_at_10[0x10]; 4209 4210 u8 reserved_at_20[0x10]; 4211 u8 op_mod[0x10]; 4212 4213 u8 reserved_at_40[0x60]; 4214 4215 u8 reserved_at_a0[0x8]; 4216 u8 table_index[0x18]; 4217 4218 u8 reserved_at_c0[0x20]; 4219 4220 u8 reserved_at_e0[0x13]; 4221 u8 vlan_valid[0x1]; 4222 u8 vlan[0xc]; 4223 4224 struct mlx5_ifc_mac_address_layout_bits mac_address; 4225 4226 u8 reserved_at_140[0xc0]; 4227 }; 4228 4229 struct mlx5_ifc_set_issi_out_bits { 4230 u8 status[0x8]; 4231 u8 reserved_at_8[0x18]; 4232 4233 u8 syndrome[0x20]; 4234 4235 u8 reserved_at_40[0x40]; 4236 }; 4237 4238 struct mlx5_ifc_set_issi_in_bits { 4239 u8 opcode[0x10]; 4240 u8 reserved_at_10[0x10]; 4241 4242 u8 reserved_at_20[0x10]; 4243 u8 op_mod[0x10]; 4244 4245 u8 reserved_at_40[0x10]; 4246 u8 current_issi[0x10]; 4247 4248 u8 reserved_at_60[0x20]; 4249 }; 4250 4251 struct mlx5_ifc_set_hca_cap_out_bits { 4252 u8 status[0x8]; 4253 u8 reserved_at_8[0x18]; 4254 4255 u8 syndrome[0x20]; 4256 4257 u8 reserved_at_40[0x40]; 4258 }; 4259 4260 struct mlx5_ifc_set_hca_cap_in_bits { 4261 u8 opcode[0x10]; 4262 u8 reserved_at_10[0x10]; 4263 4264 u8 reserved_at_20[0x10]; 4265 u8 op_mod[0x10]; 4266 4267 u8 other_function[0x1]; 4268 u8 reserved_at_41[0xf]; 4269 u8 function_id[0x10]; 4270 4271 u8 reserved_at_60[0x20]; 4272 4273 union mlx5_ifc_hca_cap_union_bits capability; 4274 }; 4275 4276 enum { 4277 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0, 4278 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1, 4279 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2, 4280 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3, 4281 MLX5_SET_FTE_MODIFY_ENABLE_MASK_IPSEC_OBJ_ID = 0x4 4282 }; 4283 4284 struct mlx5_ifc_set_fte_out_bits { 4285 u8 status[0x8]; 4286 u8 reserved_at_8[0x18]; 4287 4288 u8 syndrome[0x20]; 4289 4290 u8 reserved_at_40[0x40]; 4291 }; 4292 4293 struct mlx5_ifc_set_fte_in_bits { 4294 u8 opcode[0x10]; 4295 u8 reserved_at_10[0x10]; 4296 4297 u8 reserved_at_20[0x10]; 4298 u8 op_mod[0x10]; 4299 4300 u8 other_vport[0x1]; 4301 u8 reserved_at_41[0xf]; 4302 u8 vport_number[0x10]; 4303 4304 u8 reserved_at_60[0x20]; 4305 4306 u8 table_type[0x8]; 4307 u8 reserved_at_88[0x18]; 4308 4309 u8 reserved_at_a0[0x8]; 4310 u8 table_id[0x18]; 4311 4312 u8 ignore_flow_level[0x1]; 4313 u8 reserved_at_c1[0x17]; 4314 u8 modify_enable_mask[0x8]; 4315 4316 u8 reserved_at_e0[0x20]; 4317 4318 u8 flow_index[0x20]; 4319 4320 u8 reserved_at_120[0xe0]; 4321 4322 struct mlx5_ifc_flow_context_bits flow_context; 4323 }; 4324 4325 struct mlx5_ifc_rts2rts_qp_out_bits { 4326 u8 status[0x8]; 4327 u8 reserved_at_8[0x18]; 4328 4329 u8 syndrome[0x20]; 4330 4331 u8 reserved_at_40[0x20]; 4332 u8 ece[0x20]; 4333 }; 4334 4335 struct mlx5_ifc_rts2rts_qp_in_bits { 4336 u8 opcode[0x10]; 4337 u8 uid[0x10]; 4338 4339 u8 reserved_at_20[0x10]; 4340 u8 op_mod[0x10]; 4341 4342 u8 reserved_at_40[0x8]; 4343 u8 qpn[0x18]; 4344 4345 u8 reserved_at_60[0x20]; 4346 4347 u8 opt_param_mask[0x20]; 4348 4349 u8 ece[0x20]; 4350 4351 struct mlx5_ifc_qpc_bits qpc; 4352 4353 u8 reserved_at_800[0x80]; 4354 }; 4355 4356 struct mlx5_ifc_rtr2rts_qp_out_bits { 4357 u8 status[0x8]; 4358 u8 reserved_at_8[0x18]; 4359 4360 u8 syndrome[0x20]; 4361 4362 u8 reserved_at_40[0x20]; 4363 u8 ece[0x20]; 4364 }; 4365 4366 struct mlx5_ifc_rtr2rts_qp_in_bits { 4367 u8 opcode[0x10]; 4368 u8 uid[0x10]; 4369 4370 u8 reserved_at_20[0x10]; 4371 u8 op_mod[0x10]; 4372 4373 u8 reserved_at_40[0x8]; 4374 u8 qpn[0x18]; 4375 4376 u8 reserved_at_60[0x20]; 4377 4378 u8 opt_param_mask[0x20]; 4379 4380 u8 ece[0x20]; 4381 4382 struct mlx5_ifc_qpc_bits qpc; 4383 4384 u8 reserved_at_800[0x80]; 4385 }; 4386 4387 struct mlx5_ifc_rst2init_qp_out_bits { 4388 u8 status[0x8]; 4389 u8 reserved_at_8[0x18]; 4390 4391 u8 syndrome[0x20]; 4392 4393 u8 reserved_at_40[0x20]; 4394 u8 ece[0x20]; 4395 }; 4396 4397 struct mlx5_ifc_rst2init_qp_in_bits { 4398 u8 opcode[0x10]; 4399 u8 uid[0x10]; 4400 4401 u8 reserved_at_20[0x10]; 4402 u8 op_mod[0x10]; 4403 4404 u8 reserved_at_40[0x8]; 4405 u8 qpn[0x18]; 4406 4407 u8 reserved_at_60[0x20]; 4408 4409 u8 opt_param_mask[0x20]; 4410 4411 u8 ece[0x20]; 4412 4413 struct mlx5_ifc_qpc_bits qpc; 4414 4415 u8 reserved_at_800[0x80]; 4416 }; 4417 4418 struct mlx5_ifc_query_xrq_out_bits { 4419 u8 status[0x8]; 4420 u8 reserved_at_8[0x18]; 4421 4422 u8 syndrome[0x20]; 4423 4424 u8 reserved_at_40[0x40]; 4425 4426 struct mlx5_ifc_xrqc_bits xrq_context; 4427 }; 4428 4429 struct mlx5_ifc_query_xrq_in_bits { 4430 u8 opcode[0x10]; 4431 u8 reserved_at_10[0x10]; 4432 4433 u8 reserved_at_20[0x10]; 4434 u8 op_mod[0x10]; 4435 4436 u8 reserved_at_40[0x8]; 4437 u8 xrqn[0x18]; 4438 4439 u8 reserved_at_60[0x20]; 4440 }; 4441 4442 struct mlx5_ifc_query_xrc_srq_out_bits { 4443 u8 status[0x8]; 4444 u8 reserved_at_8[0x18]; 4445 4446 u8 syndrome[0x20]; 4447 4448 u8 reserved_at_40[0x40]; 4449 4450 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 4451 4452 u8 reserved_at_280[0x600]; 4453 4454 u8 pas[][0x40]; 4455 }; 4456 4457 struct mlx5_ifc_query_xrc_srq_in_bits { 4458 u8 opcode[0x10]; 4459 u8 reserved_at_10[0x10]; 4460 4461 u8 reserved_at_20[0x10]; 4462 u8 op_mod[0x10]; 4463 4464 u8 reserved_at_40[0x8]; 4465 u8 xrc_srqn[0x18]; 4466 4467 u8 reserved_at_60[0x20]; 4468 }; 4469 4470 enum { 4471 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0, 4472 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1, 4473 }; 4474 4475 struct mlx5_ifc_query_vport_state_out_bits { 4476 u8 status[0x8]; 4477 u8 reserved_at_8[0x18]; 4478 4479 u8 syndrome[0x20]; 4480 4481 u8 reserved_at_40[0x20]; 4482 4483 u8 reserved_at_60[0x18]; 4484 u8 admin_state[0x4]; 4485 u8 state[0x4]; 4486 }; 4487 4488 enum { 4489 MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT = 0x0, 4490 MLX5_VPORT_STATE_OP_MOD_ESW_VPORT = 0x1, 4491 MLX5_VPORT_STATE_OP_MOD_UPLINK = 0x2, 4492 }; 4493 4494 struct mlx5_ifc_arm_monitor_counter_in_bits { 4495 u8 opcode[0x10]; 4496 u8 uid[0x10]; 4497 4498 u8 reserved_at_20[0x10]; 4499 u8 op_mod[0x10]; 4500 4501 u8 reserved_at_40[0x20]; 4502 4503 u8 reserved_at_60[0x20]; 4504 }; 4505 4506 struct mlx5_ifc_arm_monitor_counter_out_bits { 4507 u8 status[0x8]; 4508 u8 reserved_at_8[0x18]; 4509 4510 u8 syndrome[0x20]; 4511 4512 u8 reserved_at_40[0x40]; 4513 }; 4514 4515 enum { 4516 MLX5_QUERY_MONITOR_CNT_TYPE_PPCNT = 0x0, 4517 MLX5_QUERY_MONITOR_CNT_TYPE_Q_COUNTER = 0x1, 4518 }; 4519 4520 enum mlx5_monitor_counter_ppcnt { 4521 MLX5_QUERY_MONITOR_PPCNT_IN_RANGE_LENGTH_ERRORS = 0x0, 4522 MLX5_QUERY_MONITOR_PPCNT_OUT_OF_RANGE_LENGTH_FIELD = 0x1, 4523 MLX5_QUERY_MONITOR_PPCNT_FRAME_TOO_LONG_ERRORS = 0x2, 4524 MLX5_QUERY_MONITOR_PPCNT_FRAME_CHECK_SEQUENCE_ERRORS = 0x3, 4525 MLX5_QUERY_MONITOR_PPCNT_ALIGNMENT_ERRORS = 0x4, 4526 MLX5_QUERY_MONITOR_PPCNT_IF_OUT_DISCARDS = 0x5, 4527 }; 4528 4529 enum { 4530 MLX5_QUERY_MONITOR_Q_COUNTER_RX_OUT_OF_BUFFER = 0x4, 4531 }; 4532 4533 struct mlx5_ifc_monitor_counter_output_bits { 4534 u8 reserved_at_0[0x4]; 4535 u8 type[0x4]; 4536 u8 reserved_at_8[0x8]; 4537 u8 counter[0x10]; 4538 4539 u8 counter_group_id[0x20]; 4540 }; 4541 4542 #define MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 (6) 4543 #define MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1 (1) 4544 #define MLX5_CMD_SET_MONITOR_NUM_COUNTER (MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 +\ 4545 MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1) 4546 4547 struct mlx5_ifc_set_monitor_counter_in_bits { 4548 u8 opcode[0x10]; 4549 u8 uid[0x10]; 4550 4551 u8 reserved_at_20[0x10]; 4552 u8 op_mod[0x10]; 4553 4554 u8 reserved_at_40[0x10]; 4555 u8 num_of_counters[0x10]; 4556 4557 u8 reserved_at_60[0x20]; 4558 4559 struct mlx5_ifc_monitor_counter_output_bits monitor_counter[MLX5_CMD_SET_MONITOR_NUM_COUNTER]; 4560 }; 4561 4562 struct mlx5_ifc_set_monitor_counter_out_bits { 4563 u8 status[0x8]; 4564 u8 reserved_at_8[0x18]; 4565 4566 u8 syndrome[0x20]; 4567 4568 u8 reserved_at_40[0x40]; 4569 }; 4570 4571 struct mlx5_ifc_query_vport_state_in_bits { 4572 u8 opcode[0x10]; 4573 u8 reserved_at_10[0x10]; 4574 4575 u8 reserved_at_20[0x10]; 4576 u8 op_mod[0x10]; 4577 4578 u8 other_vport[0x1]; 4579 u8 reserved_at_41[0xf]; 4580 u8 vport_number[0x10]; 4581 4582 u8 reserved_at_60[0x20]; 4583 }; 4584 4585 struct mlx5_ifc_query_vnic_env_out_bits { 4586 u8 status[0x8]; 4587 u8 reserved_at_8[0x18]; 4588 4589 u8 syndrome[0x20]; 4590 4591 u8 reserved_at_40[0x40]; 4592 4593 struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env; 4594 }; 4595 4596 enum { 4597 MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS = 0x0, 4598 }; 4599 4600 struct mlx5_ifc_query_vnic_env_in_bits { 4601 u8 opcode[0x10]; 4602 u8 reserved_at_10[0x10]; 4603 4604 u8 reserved_at_20[0x10]; 4605 u8 op_mod[0x10]; 4606 4607 u8 other_vport[0x1]; 4608 u8 reserved_at_41[0xf]; 4609 u8 vport_number[0x10]; 4610 4611 u8 reserved_at_60[0x20]; 4612 }; 4613 4614 struct mlx5_ifc_query_vport_counter_out_bits { 4615 u8 status[0x8]; 4616 u8 reserved_at_8[0x18]; 4617 4618 u8 syndrome[0x20]; 4619 4620 u8 reserved_at_40[0x40]; 4621 4622 struct mlx5_ifc_traffic_counter_bits received_errors; 4623 4624 struct mlx5_ifc_traffic_counter_bits transmit_errors; 4625 4626 struct mlx5_ifc_traffic_counter_bits received_ib_unicast; 4627 4628 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast; 4629 4630 struct mlx5_ifc_traffic_counter_bits received_ib_multicast; 4631 4632 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast; 4633 4634 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast; 4635 4636 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast; 4637 4638 struct mlx5_ifc_traffic_counter_bits received_eth_unicast; 4639 4640 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast; 4641 4642 struct mlx5_ifc_traffic_counter_bits received_eth_multicast; 4643 4644 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast; 4645 4646 u8 reserved_at_680[0xa00]; 4647 }; 4648 4649 enum { 4650 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0, 4651 }; 4652 4653 struct mlx5_ifc_query_vport_counter_in_bits { 4654 u8 opcode[0x10]; 4655 u8 reserved_at_10[0x10]; 4656 4657 u8 reserved_at_20[0x10]; 4658 u8 op_mod[0x10]; 4659 4660 u8 other_vport[0x1]; 4661 u8 reserved_at_41[0xb]; 4662 u8 port_num[0x4]; 4663 u8 vport_number[0x10]; 4664 4665 u8 reserved_at_60[0x60]; 4666 4667 u8 clear[0x1]; 4668 u8 reserved_at_c1[0x1f]; 4669 4670 u8 reserved_at_e0[0x20]; 4671 }; 4672 4673 struct mlx5_ifc_query_tis_out_bits { 4674 u8 status[0x8]; 4675 u8 reserved_at_8[0x18]; 4676 4677 u8 syndrome[0x20]; 4678 4679 u8 reserved_at_40[0x40]; 4680 4681 struct mlx5_ifc_tisc_bits tis_context; 4682 }; 4683 4684 struct mlx5_ifc_query_tis_in_bits { 4685 u8 opcode[0x10]; 4686 u8 reserved_at_10[0x10]; 4687 4688 u8 reserved_at_20[0x10]; 4689 u8 op_mod[0x10]; 4690 4691 u8 reserved_at_40[0x8]; 4692 u8 tisn[0x18]; 4693 4694 u8 reserved_at_60[0x20]; 4695 }; 4696 4697 struct mlx5_ifc_query_tir_out_bits { 4698 u8 status[0x8]; 4699 u8 reserved_at_8[0x18]; 4700 4701 u8 syndrome[0x20]; 4702 4703 u8 reserved_at_40[0xc0]; 4704 4705 struct mlx5_ifc_tirc_bits tir_context; 4706 }; 4707 4708 struct mlx5_ifc_query_tir_in_bits { 4709 u8 opcode[0x10]; 4710 u8 reserved_at_10[0x10]; 4711 4712 u8 reserved_at_20[0x10]; 4713 u8 op_mod[0x10]; 4714 4715 u8 reserved_at_40[0x8]; 4716 u8 tirn[0x18]; 4717 4718 u8 reserved_at_60[0x20]; 4719 }; 4720 4721 struct mlx5_ifc_query_srq_out_bits { 4722 u8 status[0x8]; 4723 u8 reserved_at_8[0x18]; 4724 4725 u8 syndrome[0x20]; 4726 4727 u8 reserved_at_40[0x40]; 4728 4729 struct mlx5_ifc_srqc_bits srq_context_entry; 4730 4731 u8 reserved_at_280[0x600]; 4732 4733 u8 pas[][0x40]; 4734 }; 4735 4736 struct mlx5_ifc_query_srq_in_bits { 4737 u8 opcode[0x10]; 4738 u8 reserved_at_10[0x10]; 4739 4740 u8 reserved_at_20[0x10]; 4741 u8 op_mod[0x10]; 4742 4743 u8 reserved_at_40[0x8]; 4744 u8 srqn[0x18]; 4745 4746 u8 reserved_at_60[0x20]; 4747 }; 4748 4749 struct mlx5_ifc_query_sq_out_bits { 4750 u8 status[0x8]; 4751 u8 reserved_at_8[0x18]; 4752 4753 u8 syndrome[0x20]; 4754 4755 u8 reserved_at_40[0xc0]; 4756 4757 struct mlx5_ifc_sqc_bits sq_context; 4758 }; 4759 4760 struct mlx5_ifc_query_sq_in_bits { 4761 u8 opcode[0x10]; 4762 u8 reserved_at_10[0x10]; 4763 4764 u8 reserved_at_20[0x10]; 4765 u8 op_mod[0x10]; 4766 4767 u8 reserved_at_40[0x8]; 4768 u8 sqn[0x18]; 4769 4770 u8 reserved_at_60[0x20]; 4771 }; 4772 4773 struct mlx5_ifc_query_special_contexts_out_bits { 4774 u8 status[0x8]; 4775 u8 reserved_at_8[0x18]; 4776 4777 u8 syndrome[0x20]; 4778 4779 u8 dump_fill_mkey[0x20]; 4780 4781 u8 resd_lkey[0x20]; 4782 4783 u8 null_mkey[0x20]; 4784 4785 u8 reserved_at_a0[0x60]; 4786 }; 4787 4788 struct mlx5_ifc_query_special_contexts_in_bits { 4789 u8 opcode[0x10]; 4790 u8 reserved_at_10[0x10]; 4791 4792 u8 reserved_at_20[0x10]; 4793 u8 op_mod[0x10]; 4794 4795 u8 reserved_at_40[0x40]; 4796 }; 4797 4798 struct mlx5_ifc_query_scheduling_element_out_bits { 4799 u8 opcode[0x10]; 4800 u8 reserved_at_10[0x10]; 4801 4802 u8 reserved_at_20[0x10]; 4803 u8 op_mod[0x10]; 4804 4805 u8 reserved_at_40[0xc0]; 4806 4807 struct mlx5_ifc_scheduling_context_bits scheduling_context; 4808 4809 u8 reserved_at_300[0x100]; 4810 }; 4811 4812 enum { 4813 SCHEDULING_HIERARCHY_E_SWITCH = 0x2, 4814 SCHEDULING_HIERARCHY_NIC = 0x3, 4815 }; 4816 4817 struct mlx5_ifc_query_scheduling_element_in_bits { 4818 u8 opcode[0x10]; 4819 u8 reserved_at_10[0x10]; 4820 4821 u8 reserved_at_20[0x10]; 4822 u8 op_mod[0x10]; 4823 4824 u8 scheduling_hierarchy[0x8]; 4825 u8 reserved_at_48[0x18]; 4826 4827 u8 scheduling_element_id[0x20]; 4828 4829 u8 reserved_at_80[0x180]; 4830 }; 4831 4832 struct mlx5_ifc_query_rqt_out_bits { 4833 u8 status[0x8]; 4834 u8 reserved_at_8[0x18]; 4835 4836 u8 syndrome[0x20]; 4837 4838 u8 reserved_at_40[0xc0]; 4839 4840 struct mlx5_ifc_rqtc_bits rqt_context; 4841 }; 4842 4843 struct mlx5_ifc_query_rqt_in_bits { 4844 u8 opcode[0x10]; 4845 u8 reserved_at_10[0x10]; 4846 4847 u8 reserved_at_20[0x10]; 4848 u8 op_mod[0x10]; 4849 4850 u8 reserved_at_40[0x8]; 4851 u8 rqtn[0x18]; 4852 4853 u8 reserved_at_60[0x20]; 4854 }; 4855 4856 struct mlx5_ifc_query_rq_out_bits { 4857 u8 status[0x8]; 4858 u8 reserved_at_8[0x18]; 4859 4860 u8 syndrome[0x20]; 4861 4862 u8 reserved_at_40[0xc0]; 4863 4864 struct mlx5_ifc_rqc_bits rq_context; 4865 }; 4866 4867 struct mlx5_ifc_query_rq_in_bits { 4868 u8 opcode[0x10]; 4869 u8 reserved_at_10[0x10]; 4870 4871 u8 reserved_at_20[0x10]; 4872 u8 op_mod[0x10]; 4873 4874 u8 reserved_at_40[0x8]; 4875 u8 rqn[0x18]; 4876 4877 u8 reserved_at_60[0x20]; 4878 }; 4879 4880 struct mlx5_ifc_query_roce_address_out_bits { 4881 u8 status[0x8]; 4882 u8 reserved_at_8[0x18]; 4883 4884 u8 syndrome[0x20]; 4885 4886 u8 reserved_at_40[0x40]; 4887 4888 struct mlx5_ifc_roce_addr_layout_bits roce_address; 4889 }; 4890 4891 struct mlx5_ifc_query_roce_address_in_bits { 4892 u8 opcode[0x10]; 4893 u8 reserved_at_10[0x10]; 4894 4895 u8 reserved_at_20[0x10]; 4896 u8 op_mod[0x10]; 4897 4898 u8 roce_address_index[0x10]; 4899 u8 reserved_at_50[0xc]; 4900 u8 vhca_port_num[0x4]; 4901 4902 u8 reserved_at_60[0x20]; 4903 }; 4904 4905 struct mlx5_ifc_query_rmp_out_bits { 4906 u8 status[0x8]; 4907 u8 reserved_at_8[0x18]; 4908 4909 u8 syndrome[0x20]; 4910 4911 u8 reserved_at_40[0xc0]; 4912 4913 struct mlx5_ifc_rmpc_bits rmp_context; 4914 }; 4915 4916 struct mlx5_ifc_query_rmp_in_bits { 4917 u8 opcode[0x10]; 4918 u8 reserved_at_10[0x10]; 4919 4920 u8 reserved_at_20[0x10]; 4921 u8 op_mod[0x10]; 4922 4923 u8 reserved_at_40[0x8]; 4924 u8 rmpn[0x18]; 4925 4926 u8 reserved_at_60[0x20]; 4927 }; 4928 4929 struct mlx5_ifc_query_qp_out_bits { 4930 u8 status[0x8]; 4931 u8 reserved_at_8[0x18]; 4932 4933 u8 syndrome[0x20]; 4934 4935 u8 reserved_at_40[0x20]; 4936 u8 ece[0x20]; 4937 4938 u8 opt_param_mask[0x20]; 4939 4940 u8 reserved_at_a0[0x20]; 4941 4942 struct mlx5_ifc_qpc_bits qpc; 4943 4944 u8 reserved_at_800[0x80]; 4945 4946 u8 pas[][0x40]; 4947 }; 4948 4949 struct mlx5_ifc_query_qp_in_bits { 4950 u8 opcode[0x10]; 4951 u8 reserved_at_10[0x10]; 4952 4953 u8 reserved_at_20[0x10]; 4954 u8 op_mod[0x10]; 4955 4956 u8 reserved_at_40[0x8]; 4957 u8 qpn[0x18]; 4958 4959 u8 reserved_at_60[0x20]; 4960 }; 4961 4962 struct mlx5_ifc_query_q_counter_out_bits { 4963 u8 status[0x8]; 4964 u8 reserved_at_8[0x18]; 4965 4966 u8 syndrome[0x20]; 4967 4968 u8 reserved_at_40[0x40]; 4969 4970 u8 rx_write_requests[0x20]; 4971 4972 u8 reserved_at_a0[0x20]; 4973 4974 u8 rx_read_requests[0x20]; 4975 4976 u8 reserved_at_e0[0x20]; 4977 4978 u8 rx_atomic_requests[0x20]; 4979 4980 u8 reserved_at_120[0x20]; 4981 4982 u8 rx_dct_connect[0x20]; 4983 4984 u8 reserved_at_160[0x20]; 4985 4986 u8 out_of_buffer[0x20]; 4987 4988 u8 reserved_at_1a0[0x20]; 4989 4990 u8 out_of_sequence[0x20]; 4991 4992 u8 reserved_at_1e0[0x20]; 4993 4994 u8 duplicate_request[0x20]; 4995 4996 u8 reserved_at_220[0x20]; 4997 4998 u8 rnr_nak_retry_err[0x20]; 4999 5000 u8 reserved_at_260[0x20]; 5001 5002 u8 packet_seq_err[0x20]; 5003 5004 u8 reserved_at_2a0[0x20]; 5005 5006 u8 implied_nak_seq_err[0x20]; 5007 5008 u8 reserved_at_2e0[0x20]; 5009 5010 u8 local_ack_timeout_err[0x20]; 5011 5012 u8 reserved_at_320[0xa0]; 5013 5014 u8 resp_local_length_error[0x20]; 5015 5016 u8 req_local_length_error[0x20]; 5017 5018 u8 resp_local_qp_error[0x20]; 5019 5020 u8 local_operation_error[0x20]; 5021 5022 u8 resp_local_protection[0x20]; 5023 5024 u8 req_local_protection[0x20]; 5025 5026 u8 resp_cqe_error[0x20]; 5027 5028 u8 req_cqe_error[0x20]; 5029 5030 u8 req_mw_binding[0x20]; 5031 5032 u8 req_bad_response[0x20]; 5033 5034 u8 req_remote_invalid_request[0x20]; 5035 5036 u8 resp_remote_invalid_request[0x20]; 5037 5038 u8 req_remote_access_errors[0x20]; 5039 5040 u8 resp_remote_access_errors[0x20]; 5041 5042 u8 req_remote_operation_errors[0x20]; 5043 5044 u8 req_transport_retries_exceeded[0x20]; 5045 5046 u8 cq_overflow[0x20]; 5047 5048 u8 resp_cqe_flush_error[0x20]; 5049 5050 u8 req_cqe_flush_error[0x20]; 5051 5052 u8 reserved_at_620[0x20]; 5053 5054 u8 roce_adp_retrans[0x20]; 5055 5056 u8 roce_adp_retrans_to[0x20]; 5057 5058 u8 roce_slow_restart[0x20]; 5059 5060 u8 roce_slow_restart_cnps[0x20]; 5061 5062 u8 roce_slow_restart_trans[0x20]; 5063 5064 u8 reserved_at_6e0[0x120]; 5065 }; 5066 5067 struct mlx5_ifc_query_q_counter_in_bits { 5068 u8 opcode[0x10]; 5069 u8 reserved_at_10[0x10]; 5070 5071 u8 reserved_at_20[0x10]; 5072 u8 op_mod[0x10]; 5073 5074 u8 reserved_at_40[0x80]; 5075 5076 u8 clear[0x1]; 5077 u8 reserved_at_c1[0x1f]; 5078 5079 u8 reserved_at_e0[0x18]; 5080 u8 counter_set_id[0x8]; 5081 }; 5082 5083 struct mlx5_ifc_query_pages_out_bits { 5084 u8 status[0x8]; 5085 u8 reserved_at_8[0x18]; 5086 5087 u8 syndrome[0x20]; 5088 5089 u8 embedded_cpu_function[0x1]; 5090 u8 reserved_at_41[0xf]; 5091 u8 function_id[0x10]; 5092 5093 u8 num_pages[0x20]; 5094 }; 5095 5096 enum { 5097 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1, 5098 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2, 5099 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3, 5100 }; 5101 5102 struct mlx5_ifc_query_pages_in_bits { 5103 u8 opcode[0x10]; 5104 u8 reserved_at_10[0x10]; 5105 5106 u8 reserved_at_20[0x10]; 5107 u8 op_mod[0x10]; 5108 5109 u8 embedded_cpu_function[0x1]; 5110 u8 reserved_at_41[0xf]; 5111 u8 function_id[0x10]; 5112 5113 u8 reserved_at_60[0x20]; 5114 }; 5115 5116 struct mlx5_ifc_query_nic_vport_context_out_bits { 5117 u8 status[0x8]; 5118 u8 reserved_at_8[0x18]; 5119 5120 u8 syndrome[0x20]; 5121 5122 u8 reserved_at_40[0x40]; 5123 5124 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 5125 }; 5126 5127 struct mlx5_ifc_query_nic_vport_context_in_bits { 5128 u8 opcode[0x10]; 5129 u8 reserved_at_10[0x10]; 5130 5131 u8 reserved_at_20[0x10]; 5132 u8 op_mod[0x10]; 5133 5134 u8 other_vport[0x1]; 5135 u8 reserved_at_41[0xf]; 5136 u8 vport_number[0x10]; 5137 5138 u8 reserved_at_60[0x5]; 5139 u8 allowed_list_type[0x3]; 5140 u8 reserved_at_68[0x18]; 5141 }; 5142 5143 struct mlx5_ifc_query_mkey_out_bits { 5144 u8 status[0x8]; 5145 u8 reserved_at_8[0x18]; 5146 5147 u8 syndrome[0x20]; 5148 5149 u8 reserved_at_40[0x40]; 5150 5151 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 5152 5153 u8 reserved_at_280[0x600]; 5154 5155 u8 bsf0_klm0_pas_mtt0_1[16][0x8]; 5156 5157 u8 bsf1_klm1_pas_mtt2_3[16][0x8]; 5158 }; 5159 5160 struct mlx5_ifc_query_mkey_in_bits { 5161 u8 opcode[0x10]; 5162 u8 reserved_at_10[0x10]; 5163 5164 u8 reserved_at_20[0x10]; 5165 u8 op_mod[0x10]; 5166 5167 u8 reserved_at_40[0x8]; 5168 u8 mkey_index[0x18]; 5169 5170 u8 pg_access[0x1]; 5171 u8 reserved_at_61[0x1f]; 5172 }; 5173 5174 struct mlx5_ifc_query_mad_demux_out_bits { 5175 u8 status[0x8]; 5176 u8 reserved_at_8[0x18]; 5177 5178 u8 syndrome[0x20]; 5179 5180 u8 reserved_at_40[0x40]; 5181 5182 u8 mad_dumux_parameters_block[0x20]; 5183 }; 5184 5185 struct mlx5_ifc_query_mad_demux_in_bits { 5186 u8 opcode[0x10]; 5187 u8 reserved_at_10[0x10]; 5188 5189 u8 reserved_at_20[0x10]; 5190 u8 op_mod[0x10]; 5191 5192 u8 reserved_at_40[0x40]; 5193 }; 5194 5195 struct mlx5_ifc_query_l2_table_entry_out_bits { 5196 u8 status[0x8]; 5197 u8 reserved_at_8[0x18]; 5198 5199 u8 syndrome[0x20]; 5200 5201 u8 reserved_at_40[0xa0]; 5202 5203 u8 reserved_at_e0[0x13]; 5204 u8 vlan_valid[0x1]; 5205 u8 vlan[0xc]; 5206 5207 struct mlx5_ifc_mac_address_layout_bits mac_address; 5208 5209 u8 reserved_at_140[0xc0]; 5210 }; 5211 5212 struct mlx5_ifc_query_l2_table_entry_in_bits { 5213 u8 opcode[0x10]; 5214 u8 reserved_at_10[0x10]; 5215 5216 u8 reserved_at_20[0x10]; 5217 u8 op_mod[0x10]; 5218 5219 u8 reserved_at_40[0x60]; 5220 5221 u8 reserved_at_a0[0x8]; 5222 u8 table_index[0x18]; 5223 5224 u8 reserved_at_c0[0x140]; 5225 }; 5226 5227 struct mlx5_ifc_query_issi_out_bits { 5228 u8 status[0x8]; 5229 u8 reserved_at_8[0x18]; 5230 5231 u8 syndrome[0x20]; 5232 5233 u8 reserved_at_40[0x10]; 5234 u8 current_issi[0x10]; 5235 5236 u8 reserved_at_60[0xa0]; 5237 5238 u8 reserved_at_100[76][0x8]; 5239 u8 supported_issi_dw0[0x20]; 5240 }; 5241 5242 struct mlx5_ifc_query_issi_in_bits { 5243 u8 opcode[0x10]; 5244 u8 reserved_at_10[0x10]; 5245 5246 u8 reserved_at_20[0x10]; 5247 u8 op_mod[0x10]; 5248 5249 u8 reserved_at_40[0x40]; 5250 }; 5251 5252 struct mlx5_ifc_set_driver_version_out_bits { 5253 u8 status[0x8]; 5254 u8 reserved_0[0x18]; 5255 5256 u8 syndrome[0x20]; 5257 u8 reserved_1[0x40]; 5258 }; 5259 5260 struct mlx5_ifc_set_driver_version_in_bits { 5261 u8 opcode[0x10]; 5262 u8 reserved_0[0x10]; 5263 5264 u8 reserved_1[0x10]; 5265 u8 op_mod[0x10]; 5266 5267 u8 reserved_2[0x40]; 5268 u8 driver_version[64][0x8]; 5269 }; 5270 5271 struct mlx5_ifc_query_hca_vport_pkey_out_bits { 5272 u8 status[0x8]; 5273 u8 reserved_at_8[0x18]; 5274 5275 u8 syndrome[0x20]; 5276 5277 u8 reserved_at_40[0x40]; 5278 5279 struct mlx5_ifc_pkey_bits pkey[]; 5280 }; 5281 5282 struct mlx5_ifc_query_hca_vport_pkey_in_bits { 5283 u8 opcode[0x10]; 5284 u8 reserved_at_10[0x10]; 5285 5286 u8 reserved_at_20[0x10]; 5287 u8 op_mod[0x10]; 5288 5289 u8 other_vport[0x1]; 5290 u8 reserved_at_41[0xb]; 5291 u8 port_num[0x4]; 5292 u8 vport_number[0x10]; 5293 5294 u8 reserved_at_60[0x10]; 5295 u8 pkey_index[0x10]; 5296 }; 5297 5298 enum { 5299 MLX5_HCA_VPORT_SEL_PORT_GUID = 1 << 0, 5300 MLX5_HCA_VPORT_SEL_NODE_GUID = 1 << 1, 5301 MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2, 5302 }; 5303 5304 struct mlx5_ifc_query_hca_vport_gid_out_bits { 5305 u8 status[0x8]; 5306 u8 reserved_at_8[0x18]; 5307 5308 u8 syndrome[0x20]; 5309 5310 u8 reserved_at_40[0x20]; 5311 5312 u8 gids_num[0x10]; 5313 u8 reserved_at_70[0x10]; 5314 5315 struct mlx5_ifc_array128_auto_bits gid[]; 5316 }; 5317 5318 struct mlx5_ifc_query_hca_vport_gid_in_bits { 5319 u8 opcode[0x10]; 5320 u8 reserved_at_10[0x10]; 5321 5322 u8 reserved_at_20[0x10]; 5323 u8 op_mod[0x10]; 5324 5325 u8 other_vport[0x1]; 5326 u8 reserved_at_41[0xb]; 5327 u8 port_num[0x4]; 5328 u8 vport_number[0x10]; 5329 5330 u8 reserved_at_60[0x10]; 5331 u8 gid_index[0x10]; 5332 }; 5333 5334 struct mlx5_ifc_query_hca_vport_context_out_bits { 5335 u8 status[0x8]; 5336 u8 reserved_at_8[0x18]; 5337 5338 u8 syndrome[0x20]; 5339 5340 u8 reserved_at_40[0x40]; 5341 5342 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 5343 }; 5344 5345 struct mlx5_ifc_query_hca_vport_context_in_bits { 5346 u8 opcode[0x10]; 5347 u8 reserved_at_10[0x10]; 5348 5349 u8 reserved_at_20[0x10]; 5350 u8 op_mod[0x10]; 5351 5352 u8 other_vport[0x1]; 5353 u8 reserved_at_41[0xb]; 5354 u8 port_num[0x4]; 5355 u8 vport_number[0x10]; 5356 5357 u8 reserved_at_60[0x20]; 5358 }; 5359 5360 struct mlx5_ifc_query_hca_cap_out_bits { 5361 u8 status[0x8]; 5362 u8 reserved_at_8[0x18]; 5363 5364 u8 syndrome[0x20]; 5365 5366 u8 reserved_at_40[0x40]; 5367 5368 union mlx5_ifc_hca_cap_union_bits capability; 5369 }; 5370 5371 struct mlx5_ifc_query_hca_cap_in_bits { 5372 u8 opcode[0x10]; 5373 u8 reserved_at_10[0x10]; 5374 5375 u8 reserved_at_20[0x10]; 5376 u8 op_mod[0x10]; 5377 5378 u8 other_function[0x1]; 5379 u8 reserved_at_41[0xf]; 5380 u8 function_id[0x10]; 5381 5382 u8 reserved_at_60[0x20]; 5383 }; 5384 5385 struct mlx5_ifc_other_hca_cap_bits { 5386 u8 roce[0x1]; 5387 u8 reserved_at_1[0x27f]; 5388 }; 5389 5390 struct mlx5_ifc_query_other_hca_cap_out_bits { 5391 u8 status[0x8]; 5392 u8 reserved_at_8[0x18]; 5393 5394 u8 syndrome[0x20]; 5395 5396 u8 reserved_at_40[0x40]; 5397 5398 struct mlx5_ifc_other_hca_cap_bits other_capability; 5399 }; 5400 5401 struct mlx5_ifc_query_other_hca_cap_in_bits { 5402 u8 opcode[0x10]; 5403 u8 reserved_at_10[0x10]; 5404 5405 u8 reserved_at_20[0x10]; 5406 u8 op_mod[0x10]; 5407 5408 u8 reserved_at_40[0x10]; 5409 u8 function_id[0x10]; 5410 5411 u8 reserved_at_60[0x20]; 5412 }; 5413 5414 struct mlx5_ifc_modify_other_hca_cap_out_bits { 5415 u8 status[0x8]; 5416 u8 reserved_at_8[0x18]; 5417 5418 u8 syndrome[0x20]; 5419 5420 u8 reserved_at_40[0x40]; 5421 }; 5422 5423 struct mlx5_ifc_modify_other_hca_cap_in_bits { 5424 u8 opcode[0x10]; 5425 u8 reserved_at_10[0x10]; 5426 5427 u8 reserved_at_20[0x10]; 5428 u8 op_mod[0x10]; 5429 5430 u8 reserved_at_40[0x10]; 5431 u8 function_id[0x10]; 5432 u8 field_select[0x20]; 5433 5434 struct mlx5_ifc_other_hca_cap_bits other_capability; 5435 }; 5436 5437 struct mlx5_ifc_flow_table_context_bits { 5438 u8 reformat_en[0x1]; 5439 u8 decap_en[0x1]; 5440 u8 sw_owner[0x1]; 5441 u8 termination_table[0x1]; 5442 u8 table_miss_action[0x4]; 5443 u8 level[0x8]; 5444 u8 reserved_at_10[0x8]; 5445 u8 log_size[0x8]; 5446 5447 u8 reserved_at_20[0x8]; 5448 u8 table_miss_id[0x18]; 5449 5450 u8 reserved_at_40[0x8]; 5451 u8 lag_master_next_table_id[0x18]; 5452 5453 u8 reserved_at_60[0x60]; 5454 5455 u8 sw_owner_icm_root_1[0x40]; 5456 5457 u8 sw_owner_icm_root_0[0x40]; 5458 5459 }; 5460 5461 struct mlx5_ifc_query_flow_table_out_bits { 5462 u8 status[0x8]; 5463 u8 reserved_at_8[0x18]; 5464 5465 u8 syndrome[0x20]; 5466 5467 u8 reserved_at_40[0x80]; 5468 5469 struct mlx5_ifc_flow_table_context_bits flow_table_context; 5470 }; 5471 5472 struct mlx5_ifc_query_flow_table_in_bits { 5473 u8 opcode[0x10]; 5474 u8 reserved_at_10[0x10]; 5475 5476 u8 reserved_at_20[0x10]; 5477 u8 op_mod[0x10]; 5478 5479 u8 reserved_at_40[0x40]; 5480 5481 u8 table_type[0x8]; 5482 u8 reserved_at_88[0x18]; 5483 5484 u8 reserved_at_a0[0x8]; 5485 u8 table_id[0x18]; 5486 5487 u8 reserved_at_c0[0x140]; 5488 }; 5489 5490 struct mlx5_ifc_query_fte_out_bits { 5491 u8 status[0x8]; 5492 u8 reserved_at_8[0x18]; 5493 5494 u8 syndrome[0x20]; 5495 5496 u8 reserved_at_40[0x1c0]; 5497 5498 struct mlx5_ifc_flow_context_bits flow_context; 5499 }; 5500 5501 struct mlx5_ifc_query_fte_in_bits { 5502 u8 opcode[0x10]; 5503 u8 reserved_at_10[0x10]; 5504 5505 u8 reserved_at_20[0x10]; 5506 u8 op_mod[0x10]; 5507 5508 u8 reserved_at_40[0x40]; 5509 5510 u8 table_type[0x8]; 5511 u8 reserved_at_88[0x18]; 5512 5513 u8 reserved_at_a0[0x8]; 5514 u8 table_id[0x18]; 5515 5516 u8 reserved_at_c0[0x40]; 5517 5518 u8 flow_index[0x20]; 5519 5520 u8 reserved_at_120[0xe0]; 5521 }; 5522 5523 enum { 5524 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 5525 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 5526 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 5527 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3, 5528 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_3 = 0x4, 5529 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_4 = 0x5, 5530 }; 5531 5532 struct mlx5_ifc_query_flow_group_out_bits { 5533 u8 status[0x8]; 5534 u8 reserved_at_8[0x18]; 5535 5536 u8 syndrome[0x20]; 5537 5538 u8 reserved_at_40[0xa0]; 5539 5540 u8 start_flow_index[0x20]; 5541 5542 u8 reserved_at_100[0x20]; 5543 5544 u8 end_flow_index[0x20]; 5545 5546 u8 reserved_at_140[0xa0]; 5547 5548 u8 reserved_at_1e0[0x18]; 5549 u8 match_criteria_enable[0x8]; 5550 5551 struct mlx5_ifc_fte_match_param_bits match_criteria; 5552 5553 u8 reserved_at_1200[0xe00]; 5554 }; 5555 5556 struct mlx5_ifc_query_flow_group_in_bits { 5557 u8 opcode[0x10]; 5558 u8 reserved_at_10[0x10]; 5559 5560 u8 reserved_at_20[0x10]; 5561 u8 op_mod[0x10]; 5562 5563 u8 reserved_at_40[0x40]; 5564 5565 u8 table_type[0x8]; 5566 u8 reserved_at_88[0x18]; 5567 5568 u8 reserved_at_a0[0x8]; 5569 u8 table_id[0x18]; 5570 5571 u8 group_id[0x20]; 5572 5573 u8 reserved_at_e0[0x120]; 5574 }; 5575 5576 struct mlx5_ifc_query_flow_counter_out_bits { 5577 u8 status[0x8]; 5578 u8 reserved_at_8[0x18]; 5579 5580 u8 syndrome[0x20]; 5581 5582 u8 reserved_at_40[0x40]; 5583 5584 struct mlx5_ifc_traffic_counter_bits flow_statistics[]; 5585 }; 5586 5587 struct mlx5_ifc_query_flow_counter_in_bits { 5588 u8 opcode[0x10]; 5589 u8 reserved_at_10[0x10]; 5590 5591 u8 reserved_at_20[0x10]; 5592 u8 op_mod[0x10]; 5593 5594 u8 reserved_at_40[0x80]; 5595 5596 u8 clear[0x1]; 5597 u8 reserved_at_c1[0xf]; 5598 u8 num_of_counters[0x10]; 5599 5600 u8 flow_counter_id[0x20]; 5601 }; 5602 5603 struct mlx5_ifc_query_esw_vport_context_out_bits { 5604 u8 status[0x8]; 5605 u8 reserved_at_8[0x18]; 5606 5607 u8 syndrome[0x20]; 5608 5609 u8 reserved_at_40[0x40]; 5610 5611 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 5612 }; 5613 5614 struct mlx5_ifc_query_esw_vport_context_in_bits { 5615 u8 opcode[0x10]; 5616 u8 reserved_at_10[0x10]; 5617 5618 u8 reserved_at_20[0x10]; 5619 u8 op_mod[0x10]; 5620 5621 u8 other_vport[0x1]; 5622 u8 reserved_at_41[0xf]; 5623 u8 vport_number[0x10]; 5624 5625 u8 reserved_at_60[0x20]; 5626 }; 5627 5628 struct mlx5_ifc_modify_esw_vport_context_out_bits { 5629 u8 status[0x8]; 5630 u8 reserved_at_8[0x18]; 5631 5632 u8 syndrome[0x20]; 5633 5634 u8 reserved_at_40[0x40]; 5635 }; 5636 5637 struct mlx5_ifc_esw_vport_context_fields_select_bits { 5638 u8 reserved_at_0[0x1b]; 5639 u8 fdb_to_vport_reg_c_id[0x1]; 5640 u8 vport_cvlan_insert[0x1]; 5641 u8 vport_svlan_insert[0x1]; 5642 u8 vport_cvlan_strip[0x1]; 5643 u8 vport_svlan_strip[0x1]; 5644 }; 5645 5646 struct mlx5_ifc_modify_esw_vport_context_in_bits { 5647 u8 opcode[0x10]; 5648 u8 reserved_at_10[0x10]; 5649 5650 u8 reserved_at_20[0x10]; 5651 u8 op_mod[0x10]; 5652 5653 u8 other_vport[0x1]; 5654 u8 reserved_at_41[0xf]; 5655 u8 vport_number[0x10]; 5656 5657 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select; 5658 5659 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 5660 }; 5661 5662 struct mlx5_ifc_query_eq_out_bits { 5663 u8 status[0x8]; 5664 u8 reserved_at_8[0x18]; 5665 5666 u8 syndrome[0x20]; 5667 5668 u8 reserved_at_40[0x40]; 5669 5670 struct mlx5_ifc_eqc_bits eq_context_entry; 5671 5672 u8 reserved_at_280[0x40]; 5673 5674 u8 event_bitmask[0x40]; 5675 5676 u8 reserved_at_300[0x580]; 5677 5678 u8 pas[][0x40]; 5679 }; 5680 5681 struct mlx5_ifc_query_eq_in_bits { 5682 u8 opcode[0x10]; 5683 u8 reserved_at_10[0x10]; 5684 5685 u8 reserved_at_20[0x10]; 5686 u8 op_mod[0x10]; 5687 5688 u8 reserved_at_40[0x18]; 5689 u8 eq_number[0x8]; 5690 5691 u8 reserved_at_60[0x20]; 5692 }; 5693 5694 struct mlx5_ifc_packet_reformat_context_in_bits { 5695 u8 reserved_at_0[0x5]; 5696 u8 reformat_type[0x3]; 5697 u8 reserved_at_8[0xe]; 5698 u8 reformat_data_size[0xa]; 5699 5700 u8 reserved_at_20[0x10]; 5701 u8 reformat_data[2][0x8]; 5702 5703 u8 more_reformat_data[][0x8]; 5704 }; 5705 5706 struct mlx5_ifc_query_packet_reformat_context_out_bits { 5707 u8 status[0x8]; 5708 u8 reserved_at_8[0x18]; 5709 5710 u8 syndrome[0x20]; 5711 5712 u8 reserved_at_40[0xa0]; 5713 5714 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context[]; 5715 }; 5716 5717 struct mlx5_ifc_query_packet_reformat_context_in_bits { 5718 u8 opcode[0x10]; 5719 u8 reserved_at_10[0x10]; 5720 5721 u8 reserved_at_20[0x10]; 5722 u8 op_mod[0x10]; 5723 5724 u8 packet_reformat_id[0x20]; 5725 5726 u8 reserved_at_60[0xa0]; 5727 }; 5728 5729 struct mlx5_ifc_alloc_packet_reformat_context_out_bits { 5730 u8 status[0x8]; 5731 u8 reserved_at_8[0x18]; 5732 5733 u8 syndrome[0x20]; 5734 5735 u8 packet_reformat_id[0x20]; 5736 5737 u8 reserved_at_60[0x20]; 5738 }; 5739 5740 enum mlx5_reformat_ctx_type { 5741 MLX5_REFORMAT_TYPE_L2_TO_VXLAN = 0x0, 5742 MLX5_REFORMAT_TYPE_L2_TO_NVGRE = 0x1, 5743 MLX5_REFORMAT_TYPE_L2_TO_L2_TUNNEL = 0x2, 5744 MLX5_REFORMAT_TYPE_L3_TUNNEL_TO_L2 = 0x3, 5745 MLX5_REFORMAT_TYPE_L2_TO_L3_TUNNEL = 0x4, 5746 }; 5747 5748 struct mlx5_ifc_alloc_packet_reformat_context_in_bits { 5749 u8 opcode[0x10]; 5750 u8 reserved_at_10[0x10]; 5751 5752 u8 reserved_at_20[0x10]; 5753 u8 op_mod[0x10]; 5754 5755 u8 reserved_at_40[0xa0]; 5756 5757 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context; 5758 }; 5759 5760 struct mlx5_ifc_dealloc_packet_reformat_context_out_bits { 5761 u8 status[0x8]; 5762 u8 reserved_at_8[0x18]; 5763 5764 u8 syndrome[0x20]; 5765 5766 u8 reserved_at_40[0x40]; 5767 }; 5768 5769 struct mlx5_ifc_dealloc_packet_reformat_context_in_bits { 5770 u8 opcode[0x10]; 5771 u8 reserved_at_10[0x10]; 5772 5773 u8 reserved_20[0x10]; 5774 u8 op_mod[0x10]; 5775 5776 u8 packet_reformat_id[0x20]; 5777 5778 u8 reserved_60[0x20]; 5779 }; 5780 5781 struct mlx5_ifc_set_action_in_bits { 5782 u8 action_type[0x4]; 5783 u8 field[0xc]; 5784 u8 reserved_at_10[0x3]; 5785 u8 offset[0x5]; 5786 u8 reserved_at_18[0x3]; 5787 u8 length[0x5]; 5788 5789 u8 data[0x20]; 5790 }; 5791 5792 struct mlx5_ifc_add_action_in_bits { 5793 u8 action_type[0x4]; 5794 u8 field[0xc]; 5795 u8 reserved_at_10[0x10]; 5796 5797 u8 data[0x20]; 5798 }; 5799 5800 struct mlx5_ifc_copy_action_in_bits { 5801 u8 action_type[0x4]; 5802 u8 src_field[0xc]; 5803 u8 reserved_at_10[0x3]; 5804 u8 src_offset[0x5]; 5805 u8 reserved_at_18[0x3]; 5806 u8 length[0x5]; 5807 5808 u8 reserved_at_20[0x4]; 5809 u8 dst_field[0xc]; 5810 u8 reserved_at_30[0x3]; 5811 u8 dst_offset[0x5]; 5812 u8 reserved_at_38[0x8]; 5813 }; 5814 5815 union mlx5_ifc_set_add_copy_action_in_auto_bits { 5816 struct mlx5_ifc_set_action_in_bits set_action_in; 5817 struct mlx5_ifc_add_action_in_bits add_action_in; 5818 struct mlx5_ifc_copy_action_in_bits copy_action_in; 5819 u8 reserved_at_0[0x40]; 5820 }; 5821 5822 enum { 5823 MLX5_ACTION_TYPE_SET = 0x1, 5824 MLX5_ACTION_TYPE_ADD = 0x2, 5825 MLX5_ACTION_TYPE_COPY = 0x3, 5826 }; 5827 5828 enum { 5829 MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16 = 0x1, 5830 MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0 = 0x2, 5831 MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE = 0x3, 5832 MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16 = 0x4, 5833 MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0 = 0x5, 5834 MLX5_ACTION_IN_FIELD_OUT_IP_DSCP = 0x6, 5835 MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS = 0x7, 5836 MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT = 0x8, 5837 MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT = 0x9, 5838 MLX5_ACTION_IN_FIELD_OUT_IP_TTL = 0xa, 5839 MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT = 0xb, 5840 MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT = 0xc, 5841 MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96 = 0xd, 5842 MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64 = 0xe, 5843 MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32 = 0xf, 5844 MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0 = 0x10, 5845 MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96 = 0x11, 5846 MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64 = 0x12, 5847 MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32 = 0x13, 5848 MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0 = 0x14, 5849 MLX5_ACTION_IN_FIELD_OUT_SIPV4 = 0x15, 5850 MLX5_ACTION_IN_FIELD_OUT_DIPV4 = 0x16, 5851 MLX5_ACTION_IN_FIELD_OUT_FIRST_VID = 0x17, 5852 MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47, 5853 MLX5_ACTION_IN_FIELD_METADATA_REG_A = 0x49, 5854 MLX5_ACTION_IN_FIELD_METADATA_REG_B = 0x50, 5855 MLX5_ACTION_IN_FIELD_METADATA_REG_C_0 = 0x51, 5856 MLX5_ACTION_IN_FIELD_METADATA_REG_C_1 = 0x52, 5857 MLX5_ACTION_IN_FIELD_METADATA_REG_C_2 = 0x53, 5858 MLX5_ACTION_IN_FIELD_METADATA_REG_C_3 = 0x54, 5859 MLX5_ACTION_IN_FIELD_METADATA_REG_C_4 = 0x55, 5860 MLX5_ACTION_IN_FIELD_METADATA_REG_C_5 = 0x56, 5861 MLX5_ACTION_IN_FIELD_METADATA_REG_C_6 = 0x57, 5862 MLX5_ACTION_IN_FIELD_METADATA_REG_C_7 = 0x58, 5863 MLX5_ACTION_IN_FIELD_OUT_TCP_SEQ_NUM = 0x59, 5864 MLX5_ACTION_IN_FIELD_OUT_TCP_ACK_NUM = 0x5B, 5865 MLX5_ACTION_IN_FIELD_IPSEC_SYNDROME = 0x5D, 5866 }; 5867 5868 struct mlx5_ifc_alloc_modify_header_context_out_bits { 5869 u8 status[0x8]; 5870 u8 reserved_at_8[0x18]; 5871 5872 u8 syndrome[0x20]; 5873 5874 u8 modify_header_id[0x20]; 5875 5876 u8 reserved_at_60[0x20]; 5877 }; 5878 5879 struct mlx5_ifc_alloc_modify_header_context_in_bits { 5880 u8 opcode[0x10]; 5881 u8 reserved_at_10[0x10]; 5882 5883 u8 reserved_at_20[0x10]; 5884 u8 op_mod[0x10]; 5885 5886 u8 reserved_at_40[0x20]; 5887 5888 u8 table_type[0x8]; 5889 u8 reserved_at_68[0x10]; 5890 u8 num_of_actions[0x8]; 5891 5892 union mlx5_ifc_set_add_copy_action_in_auto_bits actions[]; 5893 }; 5894 5895 struct mlx5_ifc_dealloc_modify_header_context_out_bits { 5896 u8 status[0x8]; 5897 u8 reserved_at_8[0x18]; 5898 5899 u8 syndrome[0x20]; 5900 5901 u8 reserved_at_40[0x40]; 5902 }; 5903 5904 struct mlx5_ifc_dealloc_modify_header_context_in_bits { 5905 u8 opcode[0x10]; 5906 u8 reserved_at_10[0x10]; 5907 5908 u8 reserved_at_20[0x10]; 5909 u8 op_mod[0x10]; 5910 5911 u8 modify_header_id[0x20]; 5912 5913 u8 reserved_at_60[0x20]; 5914 }; 5915 5916 struct mlx5_ifc_query_dct_out_bits { 5917 u8 status[0x8]; 5918 u8 reserved_at_8[0x18]; 5919 5920 u8 syndrome[0x20]; 5921 5922 u8 reserved_at_40[0x40]; 5923 5924 struct mlx5_ifc_dctc_bits dct_context_entry; 5925 5926 u8 reserved_at_280[0x180]; 5927 }; 5928 5929 struct mlx5_ifc_query_dct_in_bits { 5930 u8 opcode[0x10]; 5931 u8 reserved_at_10[0x10]; 5932 5933 u8 reserved_at_20[0x10]; 5934 u8 op_mod[0x10]; 5935 5936 u8 reserved_at_40[0x8]; 5937 u8 dctn[0x18]; 5938 5939 u8 reserved_at_60[0x20]; 5940 }; 5941 5942 struct mlx5_ifc_query_cq_out_bits { 5943 u8 status[0x8]; 5944 u8 reserved_at_8[0x18]; 5945 5946 u8 syndrome[0x20]; 5947 5948 u8 reserved_at_40[0x40]; 5949 5950 struct mlx5_ifc_cqc_bits cq_context; 5951 5952 u8 reserved_at_280[0x600]; 5953 5954 u8 pas[][0x40]; 5955 }; 5956 5957 struct mlx5_ifc_query_cq_in_bits { 5958 u8 opcode[0x10]; 5959 u8 reserved_at_10[0x10]; 5960 5961 u8 reserved_at_20[0x10]; 5962 u8 op_mod[0x10]; 5963 5964 u8 reserved_at_40[0x8]; 5965 u8 cqn[0x18]; 5966 5967 u8 reserved_at_60[0x20]; 5968 }; 5969 5970 struct mlx5_ifc_query_cong_status_out_bits { 5971 u8 status[0x8]; 5972 u8 reserved_at_8[0x18]; 5973 5974 u8 syndrome[0x20]; 5975 5976 u8 reserved_at_40[0x20]; 5977 5978 u8 enable[0x1]; 5979 u8 tag_enable[0x1]; 5980 u8 reserved_at_62[0x1e]; 5981 }; 5982 5983 struct mlx5_ifc_query_cong_status_in_bits { 5984 u8 opcode[0x10]; 5985 u8 reserved_at_10[0x10]; 5986 5987 u8 reserved_at_20[0x10]; 5988 u8 op_mod[0x10]; 5989 5990 u8 reserved_at_40[0x18]; 5991 u8 priority[0x4]; 5992 u8 cong_protocol[0x4]; 5993 5994 u8 reserved_at_60[0x20]; 5995 }; 5996 5997 struct mlx5_ifc_query_cong_statistics_out_bits { 5998 u8 status[0x8]; 5999 u8 reserved_at_8[0x18]; 6000 6001 u8 syndrome[0x20]; 6002 6003 u8 reserved_at_40[0x40]; 6004 6005 u8 rp_cur_flows[0x20]; 6006 6007 u8 sum_flows[0x20]; 6008 6009 u8 rp_cnp_ignored_high[0x20]; 6010 6011 u8 rp_cnp_ignored_low[0x20]; 6012 6013 u8 rp_cnp_handled_high[0x20]; 6014 6015 u8 rp_cnp_handled_low[0x20]; 6016 6017 u8 reserved_at_140[0x100]; 6018 6019 u8 time_stamp_high[0x20]; 6020 6021 u8 time_stamp_low[0x20]; 6022 6023 u8 accumulators_period[0x20]; 6024 6025 u8 np_ecn_marked_roce_packets_high[0x20]; 6026 6027 u8 np_ecn_marked_roce_packets_low[0x20]; 6028 6029 u8 np_cnp_sent_high[0x20]; 6030 6031 u8 np_cnp_sent_low[0x20]; 6032 6033 u8 reserved_at_320[0x560]; 6034 }; 6035 6036 struct mlx5_ifc_query_cong_statistics_in_bits { 6037 u8 opcode[0x10]; 6038 u8 reserved_at_10[0x10]; 6039 6040 u8 reserved_at_20[0x10]; 6041 u8 op_mod[0x10]; 6042 6043 u8 clear[0x1]; 6044 u8 reserved_at_41[0x1f]; 6045 6046 u8 reserved_at_60[0x20]; 6047 }; 6048 6049 struct mlx5_ifc_query_cong_params_out_bits { 6050 u8 status[0x8]; 6051 u8 reserved_at_8[0x18]; 6052 6053 u8 syndrome[0x20]; 6054 6055 u8 reserved_at_40[0x40]; 6056 6057 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 6058 }; 6059 6060 struct mlx5_ifc_query_cong_params_in_bits { 6061 u8 opcode[0x10]; 6062 u8 reserved_at_10[0x10]; 6063 6064 u8 reserved_at_20[0x10]; 6065 u8 op_mod[0x10]; 6066 6067 u8 reserved_at_40[0x1c]; 6068 u8 cong_protocol[0x4]; 6069 6070 u8 reserved_at_60[0x20]; 6071 }; 6072 6073 struct mlx5_ifc_query_adapter_out_bits { 6074 u8 status[0x8]; 6075 u8 reserved_at_8[0x18]; 6076 6077 u8 syndrome[0x20]; 6078 6079 u8 reserved_at_40[0x40]; 6080 6081 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct; 6082 }; 6083 6084 struct mlx5_ifc_query_adapter_in_bits { 6085 u8 opcode[0x10]; 6086 u8 reserved_at_10[0x10]; 6087 6088 u8 reserved_at_20[0x10]; 6089 u8 op_mod[0x10]; 6090 6091 u8 reserved_at_40[0x40]; 6092 }; 6093 6094 struct mlx5_ifc_qp_2rst_out_bits { 6095 u8 status[0x8]; 6096 u8 reserved_at_8[0x18]; 6097 6098 u8 syndrome[0x20]; 6099 6100 u8 reserved_at_40[0x40]; 6101 }; 6102 6103 struct mlx5_ifc_qp_2rst_in_bits { 6104 u8 opcode[0x10]; 6105 u8 uid[0x10]; 6106 6107 u8 reserved_at_20[0x10]; 6108 u8 op_mod[0x10]; 6109 6110 u8 reserved_at_40[0x8]; 6111 u8 qpn[0x18]; 6112 6113 u8 reserved_at_60[0x20]; 6114 }; 6115 6116 struct mlx5_ifc_qp_2err_out_bits { 6117 u8 status[0x8]; 6118 u8 reserved_at_8[0x18]; 6119 6120 u8 syndrome[0x20]; 6121 6122 u8 reserved_at_40[0x40]; 6123 }; 6124 6125 struct mlx5_ifc_qp_2err_in_bits { 6126 u8 opcode[0x10]; 6127 u8 uid[0x10]; 6128 6129 u8 reserved_at_20[0x10]; 6130 u8 op_mod[0x10]; 6131 6132 u8 reserved_at_40[0x8]; 6133 u8 qpn[0x18]; 6134 6135 u8 reserved_at_60[0x20]; 6136 }; 6137 6138 struct mlx5_ifc_page_fault_resume_out_bits { 6139 u8 status[0x8]; 6140 u8 reserved_at_8[0x18]; 6141 6142 u8 syndrome[0x20]; 6143 6144 u8 reserved_at_40[0x40]; 6145 }; 6146 6147 struct mlx5_ifc_page_fault_resume_in_bits { 6148 u8 opcode[0x10]; 6149 u8 reserved_at_10[0x10]; 6150 6151 u8 reserved_at_20[0x10]; 6152 u8 op_mod[0x10]; 6153 6154 u8 error[0x1]; 6155 u8 reserved_at_41[0x4]; 6156 u8 page_fault_type[0x3]; 6157 u8 wq_number[0x18]; 6158 6159 u8 reserved_at_60[0x8]; 6160 u8 token[0x18]; 6161 }; 6162 6163 struct mlx5_ifc_nop_out_bits { 6164 u8 status[0x8]; 6165 u8 reserved_at_8[0x18]; 6166 6167 u8 syndrome[0x20]; 6168 6169 u8 reserved_at_40[0x40]; 6170 }; 6171 6172 struct mlx5_ifc_nop_in_bits { 6173 u8 opcode[0x10]; 6174 u8 reserved_at_10[0x10]; 6175 6176 u8 reserved_at_20[0x10]; 6177 u8 op_mod[0x10]; 6178 6179 u8 reserved_at_40[0x40]; 6180 }; 6181 6182 struct mlx5_ifc_modify_vport_state_out_bits { 6183 u8 status[0x8]; 6184 u8 reserved_at_8[0x18]; 6185 6186 u8 syndrome[0x20]; 6187 6188 u8 reserved_at_40[0x40]; 6189 }; 6190 6191 struct mlx5_ifc_modify_vport_state_in_bits { 6192 u8 opcode[0x10]; 6193 u8 reserved_at_10[0x10]; 6194 6195 u8 reserved_at_20[0x10]; 6196 u8 op_mod[0x10]; 6197 6198 u8 other_vport[0x1]; 6199 u8 reserved_at_41[0xf]; 6200 u8 vport_number[0x10]; 6201 6202 u8 reserved_at_60[0x18]; 6203 u8 admin_state[0x4]; 6204 u8 reserved_at_7c[0x4]; 6205 }; 6206 6207 struct mlx5_ifc_modify_tis_out_bits { 6208 u8 status[0x8]; 6209 u8 reserved_at_8[0x18]; 6210 6211 u8 syndrome[0x20]; 6212 6213 u8 reserved_at_40[0x40]; 6214 }; 6215 6216 struct mlx5_ifc_modify_tis_bitmask_bits { 6217 u8 reserved_at_0[0x20]; 6218 6219 u8 reserved_at_20[0x1d]; 6220 u8 lag_tx_port_affinity[0x1]; 6221 u8 strict_lag_tx_port_affinity[0x1]; 6222 u8 prio[0x1]; 6223 }; 6224 6225 struct mlx5_ifc_modify_tis_in_bits { 6226 u8 opcode[0x10]; 6227 u8 uid[0x10]; 6228 6229 u8 reserved_at_20[0x10]; 6230 u8 op_mod[0x10]; 6231 6232 u8 reserved_at_40[0x8]; 6233 u8 tisn[0x18]; 6234 6235 u8 reserved_at_60[0x20]; 6236 6237 struct mlx5_ifc_modify_tis_bitmask_bits bitmask; 6238 6239 u8 reserved_at_c0[0x40]; 6240 6241 struct mlx5_ifc_tisc_bits ctx; 6242 }; 6243 6244 struct mlx5_ifc_modify_tir_bitmask_bits { 6245 u8 reserved_at_0[0x20]; 6246 6247 u8 reserved_at_20[0x1b]; 6248 u8 self_lb_en[0x1]; 6249 u8 reserved_at_3c[0x1]; 6250 u8 hash[0x1]; 6251 u8 reserved_at_3e[0x1]; 6252 u8 lro[0x1]; 6253 }; 6254 6255 struct mlx5_ifc_modify_tir_out_bits { 6256 u8 status[0x8]; 6257 u8 reserved_at_8[0x18]; 6258 6259 u8 syndrome[0x20]; 6260 6261 u8 reserved_at_40[0x40]; 6262 }; 6263 6264 struct mlx5_ifc_modify_tir_in_bits { 6265 u8 opcode[0x10]; 6266 u8 uid[0x10]; 6267 6268 u8 reserved_at_20[0x10]; 6269 u8 op_mod[0x10]; 6270 6271 u8 reserved_at_40[0x8]; 6272 u8 tirn[0x18]; 6273 6274 u8 reserved_at_60[0x20]; 6275 6276 struct mlx5_ifc_modify_tir_bitmask_bits bitmask; 6277 6278 u8 reserved_at_c0[0x40]; 6279 6280 struct mlx5_ifc_tirc_bits ctx; 6281 }; 6282 6283 struct mlx5_ifc_modify_sq_out_bits { 6284 u8 status[0x8]; 6285 u8 reserved_at_8[0x18]; 6286 6287 u8 syndrome[0x20]; 6288 6289 u8 reserved_at_40[0x40]; 6290 }; 6291 6292 struct mlx5_ifc_modify_sq_in_bits { 6293 u8 opcode[0x10]; 6294 u8 uid[0x10]; 6295 6296 u8 reserved_at_20[0x10]; 6297 u8 op_mod[0x10]; 6298 6299 u8 sq_state[0x4]; 6300 u8 reserved_at_44[0x4]; 6301 u8 sqn[0x18]; 6302 6303 u8 reserved_at_60[0x20]; 6304 6305 u8 modify_bitmask[0x40]; 6306 6307 u8 reserved_at_c0[0x40]; 6308 6309 struct mlx5_ifc_sqc_bits ctx; 6310 }; 6311 6312 struct mlx5_ifc_modify_scheduling_element_out_bits { 6313 u8 status[0x8]; 6314 u8 reserved_at_8[0x18]; 6315 6316 u8 syndrome[0x20]; 6317 6318 u8 reserved_at_40[0x1c0]; 6319 }; 6320 6321 enum { 6322 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1, 6323 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2, 6324 }; 6325 6326 struct mlx5_ifc_modify_scheduling_element_in_bits { 6327 u8 opcode[0x10]; 6328 u8 reserved_at_10[0x10]; 6329 6330 u8 reserved_at_20[0x10]; 6331 u8 op_mod[0x10]; 6332 6333 u8 scheduling_hierarchy[0x8]; 6334 u8 reserved_at_48[0x18]; 6335 6336 u8 scheduling_element_id[0x20]; 6337 6338 u8 reserved_at_80[0x20]; 6339 6340 u8 modify_bitmask[0x20]; 6341 6342 u8 reserved_at_c0[0x40]; 6343 6344 struct mlx5_ifc_scheduling_context_bits scheduling_context; 6345 6346 u8 reserved_at_300[0x100]; 6347 }; 6348 6349 struct mlx5_ifc_modify_rqt_out_bits { 6350 u8 status[0x8]; 6351 u8 reserved_at_8[0x18]; 6352 6353 u8 syndrome[0x20]; 6354 6355 u8 reserved_at_40[0x40]; 6356 }; 6357 6358 struct mlx5_ifc_rqt_bitmask_bits { 6359 u8 reserved_at_0[0x20]; 6360 6361 u8 reserved_at_20[0x1f]; 6362 u8 rqn_list[0x1]; 6363 }; 6364 6365 struct mlx5_ifc_modify_rqt_in_bits { 6366 u8 opcode[0x10]; 6367 u8 uid[0x10]; 6368 6369 u8 reserved_at_20[0x10]; 6370 u8 op_mod[0x10]; 6371 6372 u8 reserved_at_40[0x8]; 6373 u8 rqtn[0x18]; 6374 6375 u8 reserved_at_60[0x20]; 6376 6377 struct mlx5_ifc_rqt_bitmask_bits bitmask; 6378 6379 u8 reserved_at_c0[0x40]; 6380 6381 struct mlx5_ifc_rqtc_bits ctx; 6382 }; 6383 6384 struct mlx5_ifc_modify_rq_out_bits { 6385 u8 status[0x8]; 6386 u8 reserved_at_8[0x18]; 6387 6388 u8 syndrome[0x20]; 6389 6390 u8 reserved_at_40[0x40]; 6391 }; 6392 6393 enum { 6394 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1, 6395 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2, 6396 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3, 6397 }; 6398 6399 struct mlx5_ifc_modify_rq_in_bits { 6400 u8 opcode[0x10]; 6401 u8 uid[0x10]; 6402 6403 u8 reserved_at_20[0x10]; 6404 u8 op_mod[0x10]; 6405 6406 u8 rq_state[0x4]; 6407 u8 reserved_at_44[0x4]; 6408 u8 rqn[0x18]; 6409 6410 u8 reserved_at_60[0x20]; 6411 6412 u8 modify_bitmask[0x40]; 6413 6414 u8 reserved_at_c0[0x40]; 6415 6416 struct mlx5_ifc_rqc_bits ctx; 6417 }; 6418 6419 struct mlx5_ifc_modify_rmp_out_bits { 6420 u8 status[0x8]; 6421 u8 reserved_at_8[0x18]; 6422 6423 u8 syndrome[0x20]; 6424 6425 u8 reserved_at_40[0x40]; 6426 }; 6427 6428 struct mlx5_ifc_rmp_bitmask_bits { 6429 u8 reserved_at_0[0x20]; 6430 6431 u8 reserved_at_20[0x1f]; 6432 u8 lwm[0x1]; 6433 }; 6434 6435 struct mlx5_ifc_modify_rmp_in_bits { 6436 u8 opcode[0x10]; 6437 u8 uid[0x10]; 6438 6439 u8 reserved_at_20[0x10]; 6440 u8 op_mod[0x10]; 6441 6442 u8 rmp_state[0x4]; 6443 u8 reserved_at_44[0x4]; 6444 u8 rmpn[0x18]; 6445 6446 u8 reserved_at_60[0x20]; 6447 6448 struct mlx5_ifc_rmp_bitmask_bits bitmask; 6449 6450 u8 reserved_at_c0[0x40]; 6451 6452 struct mlx5_ifc_rmpc_bits ctx; 6453 }; 6454 6455 struct mlx5_ifc_modify_nic_vport_context_out_bits { 6456 u8 status[0x8]; 6457 u8 reserved_at_8[0x18]; 6458 6459 u8 syndrome[0x20]; 6460 6461 u8 reserved_at_40[0x40]; 6462 }; 6463 6464 struct mlx5_ifc_modify_nic_vport_field_select_bits { 6465 u8 reserved_at_0[0x12]; 6466 u8 affiliation[0x1]; 6467 u8 reserved_at_13[0x1]; 6468 u8 disable_uc_local_lb[0x1]; 6469 u8 disable_mc_local_lb[0x1]; 6470 u8 node_guid[0x1]; 6471 u8 port_guid[0x1]; 6472 u8 min_inline[0x1]; 6473 u8 mtu[0x1]; 6474 u8 change_event[0x1]; 6475 u8 promisc[0x1]; 6476 u8 permanent_address[0x1]; 6477 u8 addresses_list[0x1]; 6478 u8 roce_en[0x1]; 6479 u8 reserved_at_1f[0x1]; 6480 }; 6481 6482 struct mlx5_ifc_modify_nic_vport_context_in_bits { 6483 u8 opcode[0x10]; 6484 u8 reserved_at_10[0x10]; 6485 6486 u8 reserved_at_20[0x10]; 6487 u8 op_mod[0x10]; 6488 6489 u8 other_vport[0x1]; 6490 u8 reserved_at_41[0xf]; 6491 u8 vport_number[0x10]; 6492 6493 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select; 6494 6495 u8 reserved_at_80[0x780]; 6496 6497 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 6498 }; 6499 6500 struct mlx5_ifc_modify_hca_vport_context_out_bits { 6501 u8 status[0x8]; 6502 u8 reserved_at_8[0x18]; 6503 6504 u8 syndrome[0x20]; 6505 6506 u8 reserved_at_40[0x40]; 6507 }; 6508 6509 struct mlx5_ifc_modify_hca_vport_context_in_bits { 6510 u8 opcode[0x10]; 6511 u8 reserved_at_10[0x10]; 6512 6513 u8 reserved_at_20[0x10]; 6514 u8 op_mod[0x10]; 6515 6516 u8 other_vport[0x1]; 6517 u8 reserved_at_41[0xb]; 6518 u8 port_num[0x4]; 6519 u8 vport_number[0x10]; 6520 6521 u8 reserved_at_60[0x20]; 6522 6523 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 6524 }; 6525 6526 struct mlx5_ifc_modify_cq_out_bits { 6527 u8 status[0x8]; 6528 u8 reserved_at_8[0x18]; 6529 6530 u8 syndrome[0x20]; 6531 6532 u8 reserved_at_40[0x40]; 6533 }; 6534 6535 enum { 6536 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0, 6537 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1, 6538 }; 6539 6540 struct mlx5_ifc_modify_cq_in_bits { 6541 u8 opcode[0x10]; 6542 u8 uid[0x10]; 6543 6544 u8 reserved_at_20[0x10]; 6545 u8 op_mod[0x10]; 6546 6547 u8 reserved_at_40[0x8]; 6548 u8 cqn[0x18]; 6549 6550 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select; 6551 6552 struct mlx5_ifc_cqc_bits cq_context; 6553 6554 u8 reserved_at_280[0x60]; 6555 6556 u8 cq_umem_valid[0x1]; 6557 u8 reserved_at_2e1[0x1f]; 6558 6559 u8 reserved_at_300[0x580]; 6560 6561 u8 pas[][0x40]; 6562 }; 6563 6564 struct mlx5_ifc_modify_cong_status_out_bits { 6565 u8 status[0x8]; 6566 u8 reserved_at_8[0x18]; 6567 6568 u8 syndrome[0x20]; 6569 6570 u8 reserved_at_40[0x40]; 6571 }; 6572 6573 struct mlx5_ifc_modify_cong_status_in_bits { 6574 u8 opcode[0x10]; 6575 u8 reserved_at_10[0x10]; 6576 6577 u8 reserved_at_20[0x10]; 6578 u8 op_mod[0x10]; 6579 6580 u8 reserved_at_40[0x18]; 6581 u8 priority[0x4]; 6582 u8 cong_protocol[0x4]; 6583 6584 u8 enable[0x1]; 6585 u8 tag_enable[0x1]; 6586 u8 reserved_at_62[0x1e]; 6587 }; 6588 6589 struct mlx5_ifc_modify_cong_params_out_bits { 6590 u8 status[0x8]; 6591 u8 reserved_at_8[0x18]; 6592 6593 u8 syndrome[0x20]; 6594 6595 u8 reserved_at_40[0x40]; 6596 }; 6597 6598 struct mlx5_ifc_modify_cong_params_in_bits { 6599 u8 opcode[0x10]; 6600 u8 reserved_at_10[0x10]; 6601 6602 u8 reserved_at_20[0x10]; 6603 u8 op_mod[0x10]; 6604 6605 u8 reserved_at_40[0x1c]; 6606 u8 cong_protocol[0x4]; 6607 6608 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select; 6609 6610 u8 reserved_at_80[0x80]; 6611 6612 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 6613 }; 6614 6615 struct mlx5_ifc_manage_pages_out_bits { 6616 u8 status[0x8]; 6617 u8 reserved_at_8[0x18]; 6618 6619 u8 syndrome[0x20]; 6620 6621 u8 output_num_entries[0x20]; 6622 6623 u8 reserved_at_60[0x20]; 6624 6625 u8 pas[][0x40]; 6626 }; 6627 6628 enum { 6629 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL = 0x0, 6630 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS = 0x1, 6631 MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES = 0x2, 6632 }; 6633 6634 struct mlx5_ifc_manage_pages_in_bits { 6635 u8 opcode[0x10]; 6636 u8 reserved_at_10[0x10]; 6637 6638 u8 reserved_at_20[0x10]; 6639 u8 op_mod[0x10]; 6640 6641 u8 embedded_cpu_function[0x1]; 6642 u8 reserved_at_41[0xf]; 6643 u8 function_id[0x10]; 6644 6645 u8 input_num_entries[0x20]; 6646 6647 u8 pas[][0x40]; 6648 }; 6649 6650 struct mlx5_ifc_mad_ifc_out_bits { 6651 u8 status[0x8]; 6652 u8 reserved_at_8[0x18]; 6653 6654 u8 syndrome[0x20]; 6655 6656 u8 reserved_at_40[0x40]; 6657 6658 u8 response_mad_packet[256][0x8]; 6659 }; 6660 6661 struct mlx5_ifc_mad_ifc_in_bits { 6662 u8 opcode[0x10]; 6663 u8 reserved_at_10[0x10]; 6664 6665 u8 reserved_at_20[0x10]; 6666 u8 op_mod[0x10]; 6667 6668 u8 remote_lid[0x10]; 6669 u8 reserved_at_50[0x8]; 6670 u8 port[0x8]; 6671 6672 u8 reserved_at_60[0x20]; 6673 6674 u8 mad[256][0x8]; 6675 }; 6676 6677 struct mlx5_ifc_init_hca_out_bits { 6678 u8 status[0x8]; 6679 u8 reserved_at_8[0x18]; 6680 6681 u8 syndrome[0x20]; 6682 6683 u8 reserved_at_40[0x40]; 6684 }; 6685 6686 struct mlx5_ifc_init_hca_in_bits { 6687 u8 opcode[0x10]; 6688 u8 reserved_at_10[0x10]; 6689 6690 u8 reserved_at_20[0x10]; 6691 u8 op_mod[0x10]; 6692 6693 u8 reserved_at_40[0x40]; 6694 u8 sw_owner_id[4][0x20]; 6695 }; 6696 6697 struct mlx5_ifc_init2rtr_qp_out_bits { 6698 u8 status[0x8]; 6699 u8 reserved_at_8[0x18]; 6700 6701 u8 syndrome[0x20]; 6702 6703 u8 reserved_at_40[0x20]; 6704 u8 ece[0x20]; 6705 }; 6706 6707 struct mlx5_ifc_init2rtr_qp_in_bits { 6708 u8 opcode[0x10]; 6709 u8 uid[0x10]; 6710 6711 u8 reserved_at_20[0x10]; 6712 u8 op_mod[0x10]; 6713 6714 u8 reserved_at_40[0x8]; 6715 u8 qpn[0x18]; 6716 6717 u8 reserved_at_60[0x20]; 6718 6719 u8 opt_param_mask[0x20]; 6720 6721 u8 ece[0x20]; 6722 6723 struct mlx5_ifc_qpc_bits qpc; 6724 6725 u8 reserved_at_800[0x80]; 6726 }; 6727 6728 struct mlx5_ifc_init2init_qp_out_bits { 6729 u8 status[0x8]; 6730 u8 reserved_at_8[0x18]; 6731 6732 u8 syndrome[0x20]; 6733 6734 u8 reserved_at_40[0x20]; 6735 u8 ece[0x20]; 6736 }; 6737 6738 struct mlx5_ifc_init2init_qp_in_bits { 6739 u8 opcode[0x10]; 6740 u8 uid[0x10]; 6741 6742 u8 reserved_at_20[0x10]; 6743 u8 op_mod[0x10]; 6744 6745 u8 reserved_at_40[0x8]; 6746 u8 qpn[0x18]; 6747 6748 u8 reserved_at_60[0x20]; 6749 6750 u8 opt_param_mask[0x20]; 6751 6752 u8 ece[0x20]; 6753 6754 struct mlx5_ifc_qpc_bits qpc; 6755 6756 u8 reserved_at_800[0x80]; 6757 }; 6758 6759 struct mlx5_ifc_get_dropped_packet_log_out_bits { 6760 u8 status[0x8]; 6761 u8 reserved_at_8[0x18]; 6762 6763 u8 syndrome[0x20]; 6764 6765 u8 reserved_at_40[0x40]; 6766 6767 u8 packet_headers_log[128][0x8]; 6768 6769 u8 packet_syndrome[64][0x8]; 6770 }; 6771 6772 struct mlx5_ifc_get_dropped_packet_log_in_bits { 6773 u8 opcode[0x10]; 6774 u8 reserved_at_10[0x10]; 6775 6776 u8 reserved_at_20[0x10]; 6777 u8 op_mod[0x10]; 6778 6779 u8 reserved_at_40[0x40]; 6780 }; 6781 6782 struct mlx5_ifc_gen_eqe_in_bits { 6783 u8 opcode[0x10]; 6784 u8 reserved_at_10[0x10]; 6785 6786 u8 reserved_at_20[0x10]; 6787 u8 op_mod[0x10]; 6788 6789 u8 reserved_at_40[0x18]; 6790 u8 eq_number[0x8]; 6791 6792 u8 reserved_at_60[0x20]; 6793 6794 u8 eqe[64][0x8]; 6795 }; 6796 6797 struct mlx5_ifc_gen_eq_out_bits { 6798 u8 status[0x8]; 6799 u8 reserved_at_8[0x18]; 6800 6801 u8 syndrome[0x20]; 6802 6803 u8 reserved_at_40[0x40]; 6804 }; 6805 6806 struct mlx5_ifc_enable_hca_out_bits { 6807 u8 status[0x8]; 6808 u8 reserved_at_8[0x18]; 6809 6810 u8 syndrome[0x20]; 6811 6812 u8 reserved_at_40[0x20]; 6813 }; 6814 6815 struct mlx5_ifc_enable_hca_in_bits { 6816 u8 opcode[0x10]; 6817 u8 reserved_at_10[0x10]; 6818 6819 u8 reserved_at_20[0x10]; 6820 u8 op_mod[0x10]; 6821 6822 u8 embedded_cpu_function[0x1]; 6823 u8 reserved_at_41[0xf]; 6824 u8 function_id[0x10]; 6825 6826 u8 reserved_at_60[0x20]; 6827 }; 6828 6829 struct mlx5_ifc_drain_dct_out_bits { 6830 u8 status[0x8]; 6831 u8 reserved_at_8[0x18]; 6832 6833 u8 syndrome[0x20]; 6834 6835 u8 reserved_at_40[0x40]; 6836 }; 6837 6838 struct mlx5_ifc_drain_dct_in_bits { 6839 u8 opcode[0x10]; 6840 u8 uid[0x10]; 6841 6842 u8 reserved_at_20[0x10]; 6843 u8 op_mod[0x10]; 6844 6845 u8 reserved_at_40[0x8]; 6846 u8 dctn[0x18]; 6847 6848 u8 reserved_at_60[0x20]; 6849 }; 6850 6851 struct mlx5_ifc_disable_hca_out_bits { 6852 u8 status[0x8]; 6853 u8 reserved_at_8[0x18]; 6854 6855 u8 syndrome[0x20]; 6856 6857 u8 reserved_at_40[0x20]; 6858 }; 6859 6860 struct mlx5_ifc_disable_hca_in_bits { 6861 u8 opcode[0x10]; 6862 u8 reserved_at_10[0x10]; 6863 6864 u8 reserved_at_20[0x10]; 6865 u8 op_mod[0x10]; 6866 6867 u8 embedded_cpu_function[0x1]; 6868 u8 reserved_at_41[0xf]; 6869 u8 function_id[0x10]; 6870 6871 u8 reserved_at_60[0x20]; 6872 }; 6873 6874 struct mlx5_ifc_detach_from_mcg_out_bits { 6875 u8 status[0x8]; 6876 u8 reserved_at_8[0x18]; 6877 6878 u8 syndrome[0x20]; 6879 6880 u8 reserved_at_40[0x40]; 6881 }; 6882 6883 struct mlx5_ifc_detach_from_mcg_in_bits { 6884 u8 opcode[0x10]; 6885 u8 uid[0x10]; 6886 6887 u8 reserved_at_20[0x10]; 6888 u8 op_mod[0x10]; 6889 6890 u8 reserved_at_40[0x8]; 6891 u8 qpn[0x18]; 6892 6893 u8 reserved_at_60[0x20]; 6894 6895 u8 multicast_gid[16][0x8]; 6896 }; 6897 6898 struct mlx5_ifc_destroy_xrq_out_bits { 6899 u8 status[0x8]; 6900 u8 reserved_at_8[0x18]; 6901 6902 u8 syndrome[0x20]; 6903 6904 u8 reserved_at_40[0x40]; 6905 }; 6906 6907 struct mlx5_ifc_destroy_xrq_in_bits { 6908 u8 opcode[0x10]; 6909 u8 uid[0x10]; 6910 6911 u8 reserved_at_20[0x10]; 6912 u8 op_mod[0x10]; 6913 6914 u8 reserved_at_40[0x8]; 6915 u8 xrqn[0x18]; 6916 6917 u8 reserved_at_60[0x20]; 6918 }; 6919 6920 struct mlx5_ifc_destroy_xrc_srq_out_bits { 6921 u8 status[0x8]; 6922 u8 reserved_at_8[0x18]; 6923 6924 u8 syndrome[0x20]; 6925 6926 u8 reserved_at_40[0x40]; 6927 }; 6928 6929 struct mlx5_ifc_destroy_xrc_srq_in_bits { 6930 u8 opcode[0x10]; 6931 u8 uid[0x10]; 6932 6933 u8 reserved_at_20[0x10]; 6934 u8 op_mod[0x10]; 6935 6936 u8 reserved_at_40[0x8]; 6937 u8 xrc_srqn[0x18]; 6938 6939 u8 reserved_at_60[0x20]; 6940 }; 6941 6942 struct mlx5_ifc_destroy_tis_out_bits { 6943 u8 status[0x8]; 6944 u8 reserved_at_8[0x18]; 6945 6946 u8 syndrome[0x20]; 6947 6948 u8 reserved_at_40[0x40]; 6949 }; 6950 6951 struct mlx5_ifc_destroy_tis_in_bits { 6952 u8 opcode[0x10]; 6953 u8 uid[0x10]; 6954 6955 u8 reserved_at_20[0x10]; 6956 u8 op_mod[0x10]; 6957 6958 u8 reserved_at_40[0x8]; 6959 u8 tisn[0x18]; 6960 6961 u8 reserved_at_60[0x20]; 6962 }; 6963 6964 struct mlx5_ifc_destroy_tir_out_bits { 6965 u8 status[0x8]; 6966 u8 reserved_at_8[0x18]; 6967 6968 u8 syndrome[0x20]; 6969 6970 u8 reserved_at_40[0x40]; 6971 }; 6972 6973 struct mlx5_ifc_destroy_tir_in_bits { 6974 u8 opcode[0x10]; 6975 u8 uid[0x10]; 6976 6977 u8 reserved_at_20[0x10]; 6978 u8 op_mod[0x10]; 6979 6980 u8 reserved_at_40[0x8]; 6981 u8 tirn[0x18]; 6982 6983 u8 reserved_at_60[0x20]; 6984 }; 6985 6986 struct mlx5_ifc_destroy_srq_out_bits { 6987 u8 status[0x8]; 6988 u8 reserved_at_8[0x18]; 6989 6990 u8 syndrome[0x20]; 6991 6992 u8 reserved_at_40[0x40]; 6993 }; 6994 6995 struct mlx5_ifc_destroy_srq_in_bits { 6996 u8 opcode[0x10]; 6997 u8 uid[0x10]; 6998 6999 u8 reserved_at_20[0x10]; 7000 u8 op_mod[0x10]; 7001 7002 u8 reserved_at_40[0x8]; 7003 u8 srqn[0x18]; 7004 7005 u8 reserved_at_60[0x20]; 7006 }; 7007 7008 struct mlx5_ifc_destroy_sq_out_bits { 7009 u8 status[0x8]; 7010 u8 reserved_at_8[0x18]; 7011 7012 u8 syndrome[0x20]; 7013 7014 u8 reserved_at_40[0x40]; 7015 }; 7016 7017 struct mlx5_ifc_destroy_sq_in_bits { 7018 u8 opcode[0x10]; 7019 u8 uid[0x10]; 7020 7021 u8 reserved_at_20[0x10]; 7022 u8 op_mod[0x10]; 7023 7024 u8 reserved_at_40[0x8]; 7025 u8 sqn[0x18]; 7026 7027 u8 reserved_at_60[0x20]; 7028 }; 7029 7030 struct mlx5_ifc_destroy_scheduling_element_out_bits { 7031 u8 status[0x8]; 7032 u8 reserved_at_8[0x18]; 7033 7034 u8 syndrome[0x20]; 7035 7036 u8 reserved_at_40[0x1c0]; 7037 }; 7038 7039 struct mlx5_ifc_destroy_scheduling_element_in_bits { 7040 u8 opcode[0x10]; 7041 u8 reserved_at_10[0x10]; 7042 7043 u8 reserved_at_20[0x10]; 7044 u8 op_mod[0x10]; 7045 7046 u8 scheduling_hierarchy[0x8]; 7047 u8 reserved_at_48[0x18]; 7048 7049 u8 scheduling_element_id[0x20]; 7050 7051 u8 reserved_at_80[0x180]; 7052 }; 7053 7054 struct mlx5_ifc_destroy_rqt_out_bits { 7055 u8 status[0x8]; 7056 u8 reserved_at_8[0x18]; 7057 7058 u8 syndrome[0x20]; 7059 7060 u8 reserved_at_40[0x40]; 7061 }; 7062 7063 struct mlx5_ifc_destroy_rqt_in_bits { 7064 u8 opcode[0x10]; 7065 u8 uid[0x10]; 7066 7067 u8 reserved_at_20[0x10]; 7068 u8 op_mod[0x10]; 7069 7070 u8 reserved_at_40[0x8]; 7071 u8 rqtn[0x18]; 7072 7073 u8 reserved_at_60[0x20]; 7074 }; 7075 7076 struct mlx5_ifc_destroy_rq_out_bits { 7077 u8 status[0x8]; 7078 u8 reserved_at_8[0x18]; 7079 7080 u8 syndrome[0x20]; 7081 7082 u8 reserved_at_40[0x40]; 7083 }; 7084 7085 struct mlx5_ifc_destroy_rq_in_bits { 7086 u8 opcode[0x10]; 7087 u8 uid[0x10]; 7088 7089 u8 reserved_at_20[0x10]; 7090 u8 op_mod[0x10]; 7091 7092 u8 reserved_at_40[0x8]; 7093 u8 rqn[0x18]; 7094 7095 u8 reserved_at_60[0x20]; 7096 }; 7097 7098 struct mlx5_ifc_set_delay_drop_params_in_bits { 7099 u8 opcode[0x10]; 7100 u8 reserved_at_10[0x10]; 7101 7102 u8 reserved_at_20[0x10]; 7103 u8 op_mod[0x10]; 7104 7105 u8 reserved_at_40[0x20]; 7106 7107 u8 reserved_at_60[0x10]; 7108 u8 delay_drop_timeout[0x10]; 7109 }; 7110 7111 struct mlx5_ifc_set_delay_drop_params_out_bits { 7112 u8 status[0x8]; 7113 u8 reserved_at_8[0x18]; 7114 7115 u8 syndrome[0x20]; 7116 7117 u8 reserved_at_40[0x40]; 7118 }; 7119 7120 struct mlx5_ifc_destroy_rmp_out_bits { 7121 u8 status[0x8]; 7122 u8 reserved_at_8[0x18]; 7123 7124 u8 syndrome[0x20]; 7125 7126 u8 reserved_at_40[0x40]; 7127 }; 7128 7129 struct mlx5_ifc_destroy_rmp_in_bits { 7130 u8 opcode[0x10]; 7131 u8 uid[0x10]; 7132 7133 u8 reserved_at_20[0x10]; 7134 u8 op_mod[0x10]; 7135 7136 u8 reserved_at_40[0x8]; 7137 u8 rmpn[0x18]; 7138 7139 u8 reserved_at_60[0x20]; 7140 }; 7141 7142 struct mlx5_ifc_destroy_qp_out_bits { 7143 u8 status[0x8]; 7144 u8 reserved_at_8[0x18]; 7145 7146 u8 syndrome[0x20]; 7147 7148 u8 reserved_at_40[0x40]; 7149 }; 7150 7151 struct mlx5_ifc_destroy_qp_in_bits { 7152 u8 opcode[0x10]; 7153 u8 uid[0x10]; 7154 7155 u8 reserved_at_20[0x10]; 7156 u8 op_mod[0x10]; 7157 7158 u8 reserved_at_40[0x8]; 7159 u8 qpn[0x18]; 7160 7161 u8 reserved_at_60[0x20]; 7162 }; 7163 7164 struct mlx5_ifc_destroy_psv_out_bits { 7165 u8 status[0x8]; 7166 u8 reserved_at_8[0x18]; 7167 7168 u8 syndrome[0x20]; 7169 7170 u8 reserved_at_40[0x40]; 7171 }; 7172 7173 struct mlx5_ifc_destroy_psv_in_bits { 7174 u8 opcode[0x10]; 7175 u8 reserved_at_10[0x10]; 7176 7177 u8 reserved_at_20[0x10]; 7178 u8 op_mod[0x10]; 7179 7180 u8 reserved_at_40[0x8]; 7181 u8 psvn[0x18]; 7182 7183 u8 reserved_at_60[0x20]; 7184 }; 7185 7186 struct mlx5_ifc_destroy_mkey_out_bits { 7187 u8 status[0x8]; 7188 u8 reserved_at_8[0x18]; 7189 7190 u8 syndrome[0x20]; 7191 7192 u8 reserved_at_40[0x40]; 7193 }; 7194 7195 struct mlx5_ifc_destroy_mkey_in_bits { 7196 u8 opcode[0x10]; 7197 u8 uid[0x10]; 7198 7199 u8 reserved_at_20[0x10]; 7200 u8 op_mod[0x10]; 7201 7202 u8 reserved_at_40[0x8]; 7203 u8 mkey_index[0x18]; 7204 7205 u8 reserved_at_60[0x20]; 7206 }; 7207 7208 struct mlx5_ifc_destroy_flow_table_out_bits { 7209 u8 status[0x8]; 7210 u8 reserved_at_8[0x18]; 7211 7212 u8 syndrome[0x20]; 7213 7214 u8 reserved_at_40[0x40]; 7215 }; 7216 7217 struct mlx5_ifc_destroy_flow_table_in_bits { 7218 u8 opcode[0x10]; 7219 u8 reserved_at_10[0x10]; 7220 7221 u8 reserved_at_20[0x10]; 7222 u8 op_mod[0x10]; 7223 7224 u8 other_vport[0x1]; 7225 u8 reserved_at_41[0xf]; 7226 u8 vport_number[0x10]; 7227 7228 u8 reserved_at_60[0x20]; 7229 7230 u8 table_type[0x8]; 7231 u8 reserved_at_88[0x18]; 7232 7233 u8 reserved_at_a0[0x8]; 7234 u8 table_id[0x18]; 7235 7236 u8 reserved_at_c0[0x140]; 7237 }; 7238 7239 struct mlx5_ifc_destroy_flow_group_out_bits { 7240 u8 status[0x8]; 7241 u8 reserved_at_8[0x18]; 7242 7243 u8 syndrome[0x20]; 7244 7245 u8 reserved_at_40[0x40]; 7246 }; 7247 7248 struct mlx5_ifc_destroy_flow_group_in_bits { 7249 u8 opcode[0x10]; 7250 u8 reserved_at_10[0x10]; 7251 7252 u8 reserved_at_20[0x10]; 7253 u8 op_mod[0x10]; 7254 7255 u8 other_vport[0x1]; 7256 u8 reserved_at_41[0xf]; 7257 u8 vport_number[0x10]; 7258 7259 u8 reserved_at_60[0x20]; 7260 7261 u8 table_type[0x8]; 7262 u8 reserved_at_88[0x18]; 7263 7264 u8 reserved_at_a0[0x8]; 7265 u8 table_id[0x18]; 7266 7267 u8 group_id[0x20]; 7268 7269 u8 reserved_at_e0[0x120]; 7270 }; 7271 7272 struct mlx5_ifc_destroy_eq_out_bits { 7273 u8 status[0x8]; 7274 u8 reserved_at_8[0x18]; 7275 7276 u8 syndrome[0x20]; 7277 7278 u8 reserved_at_40[0x40]; 7279 }; 7280 7281 struct mlx5_ifc_destroy_eq_in_bits { 7282 u8 opcode[0x10]; 7283 u8 reserved_at_10[0x10]; 7284 7285 u8 reserved_at_20[0x10]; 7286 u8 op_mod[0x10]; 7287 7288 u8 reserved_at_40[0x18]; 7289 u8 eq_number[0x8]; 7290 7291 u8 reserved_at_60[0x20]; 7292 }; 7293 7294 struct mlx5_ifc_destroy_dct_out_bits { 7295 u8 status[0x8]; 7296 u8 reserved_at_8[0x18]; 7297 7298 u8 syndrome[0x20]; 7299 7300 u8 reserved_at_40[0x40]; 7301 }; 7302 7303 struct mlx5_ifc_destroy_dct_in_bits { 7304 u8 opcode[0x10]; 7305 u8 uid[0x10]; 7306 7307 u8 reserved_at_20[0x10]; 7308 u8 op_mod[0x10]; 7309 7310 u8 reserved_at_40[0x8]; 7311 u8 dctn[0x18]; 7312 7313 u8 reserved_at_60[0x20]; 7314 }; 7315 7316 struct mlx5_ifc_destroy_cq_out_bits { 7317 u8 status[0x8]; 7318 u8 reserved_at_8[0x18]; 7319 7320 u8 syndrome[0x20]; 7321 7322 u8 reserved_at_40[0x40]; 7323 }; 7324 7325 struct mlx5_ifc_destroy_cq_in_bits { 7326 u8 opcode[0x10]; 7327 u8 uid[0x10]; 7328 7329 u8 reserved_at_20[0x10]; 7330 u8 op_mod[0x10]; 7331 7332 u8 reserved_at_40[0x8]; 7333 u8 cqn[0x18]; 7334 7335 u8 reserved_at_60[0x20]; 7336 }; 7337 7338 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits { 7339 u8 status[0x8]; 7340 u8 reserved_at_8[0x18]; 7341 7342 u8 syndrome[0x20]; 7343 7344 u8 reserved_at_40[0x40]; 7345 }; 7346 7347 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits { 7348 u8 opcode[0x10]; 7349 u8 reserved_at_10[0x10]; 7350 7351 u8 reserved_at_20[0x10]; 7352 u8 op_mod[0x10]; 7353 7354 u8 reserved_at_40[0x20]; 7355 7356 u8 reserved_at_60[0x10]; 7357 u8 vxlan_udp_port[0x10]; 7358 }; 7359 7360 struct mlx5_ifc_delete_l2_table_entry_out_bits { 7361 u8 status[0x8]; 7362 u8 reserved_at_8[0x18]; 7363 7364 u8 syndrome[0x20]; 7365 7366 u8 reserved_at_40[0x40]; 7367 }; 7368 7369 struct mlx5_ifc_delete_l2_table_entry_in_bits { 7370 u8 opcode[0x10]; 7371 u8 reserved_at_10[0x10]; 7372 7373 u8 reserved_at_20[0x10]; 7374 u8 op_mod[0x10]; 7375 7376 u8 reserved_at_40[0x60]; 7377 7378 u8 reserved_at_a0[0x8]; 7379 u8 table_index[0x18]; 7380 7381 u8 reserved_at_c0[0x140]; 7382 }; 7383 7384 struct mlx5_ifc_delete_fte_out_bits { 7385 u8 status[0x8]; 7386 u8 reserved_at_8[0x18]; 7387 7388 u8 syndrome[0x20]; 7389 7390 u8 reserved_at_40[0x40]; 7391 }; 7392 7393 struct mlx5_ifc_delete_fte_in_bits { 7394 u8 opcode[0x10]; 7395 u8 reserved_at_10[0x10]; 7396 7397 u8 reserved_at_20[0x10]; 7398 u8 op_mod[0x10]; 7399 7400 u8 other_vport[0x1]; 7401 u8 reserved_at_41[0xf]; 7402 u8 vport_number[0x10]; 7403 7404 u8 reserved_at_60[0x20]; 7405 7406 u8 table_type[0x8]; 7407 u8 reserved_at_88[0x18]; 7408 7409 u8 reserved_at_a0[0x8]; 7410 u8 table_id[0x18]; 7411 7412 u8 reserved_at_c0[0x40]; 7413 7414 u8 flow_index[0x20]; 7415 7416 u8 reserved_at_120[0xe0]; 7417 }; 7418 7419 struct mlx5_ifc_dealloc_xrcd_out_bits { 7420 u8 status[0x8]; 7421 u8 reserved_at_8[0x18]; 7422 7423 u8 syndrome[0x20]; 7424 7425 u8 reserved_at_40[0x40]; 7426 }; 7427 7428 struct mlx5_ifc_dealloc_xrcd_in_bits { 7429 u8 opcode[0x10]; 7430 u8 uid[0x10]; 7431 7432 u8 reserved_at_20[0x10]; 7433 u8 op_mod[0x10]; 7434 7435 u8 reserved_at_40[0x8]; 7436 u8 xrcd[0x18]; 7437 7438 u8 reserved_at_60[0x20]; 7439 }; 7440 7441 struct mlx5_ifc_dealloc_uar_out_bits { 7442 u8 status[0x8]; 7443 u8 reserved_at_8[0x18]; 7444 7445 u8 syndrome[0x20]; 7446 7447 u8 reserved_at_40[0x40]; 7448 }; 7449 7450 struct mlx5_ifc_dealloc_uar_in_bits { 7451 u8 opcode[0x10]; 7452 u8 reserved_at_10[0x10]; 7453 7454 u8 reserved_at_20[0x10]; 7455 u8 op_mod[0x10]; 7456 7457 u8 reserved_at_40[0x8]; 7458 u8 uar[0x18]; 7459 7460 u8 reserved_at_60[0x20]; 7461 }; 7462 7463 struct mlx5_ifc_dealloc_transport_domain_out_bits { 7464 u8 status[0x8]; 7465 u8 reserved_at_8[0x18]; 7466 7467 u8 syndrome[0x20]; 7468 7469 u8 reserved_at_40[0x40]; 7470 }; 7471 7472 struct mlx5_ifc_dealloc_transport_domain_in_bits { 7473 u8 opcode[0x10]; 7474 u8 uid[0x10]; 7475 7476 u8 reserved_at_20[0x10]; 7477 u8 op_mod[0x10]; 7478 7479 u8 reserved_at_40[0x8]; 7480 u8 transport_domain[0x18]; 7481 7482 u8 reserved_at_60[0x20]; 7483 }; 7484 7485 struct mlx5_ifc_dealloc_q_counter_out_bits { 7486 u8 status[0x8]; 7487 u8 reserved_at_8[0x18]; 7488 7489 u8 syndrome[0x20]; 7490 7491 u8 reserved_at_40[0x40]; 7492 }; 7493 7494 struct mlx5_ifc_dealloc_q_counter_in_bits { 7495 u8 opcode[0x10]; 7496 u8 reserved_at_10[0x10]; 7497 7498 u8 reserved_at_20[0x10]; 7499 u8 op_mod[0x10]; 7500 7501 u8 reserved_at_40[0x18]; 7502 u8 counter_set_id[0x8]; 7503 7504 u8 reserved_at_60[0x20]; 7505 }; 7506 7507 struct mlx5_ifc_dealloc_pd_out_bits { 7508 u8 status[0x8]; 7509 u8 reserved_at_8[0x18]; 7510 7511 u8 syndrome[0x20]; 7512 7513 u8 reserved_at_40[0x40]; 7514 }; 7515 7516 struct mlx5_ifc_dealloc_pd_in_bits { 7517 u8 opcode[0x10]; 7518 u8 uid[0x10]; 7519 7520 u8 reserved_at_20[0x10]; 7521 u8 op_mod[0x10]; 7522 7523 u8 reserved_at_40[0x8]; 7524 u8 pd[0x18]; 7525 7526 u8 reserved_at_60[0x20]; 7527 }; 7528 7529 struct mlx5_ifc_dealloc_flow_counter_out_bits { 7530 u8 status[0x8]; 7531 u8 reserved_at_8[0x18]; 7532 7533 u8 syndrome[0x20]; 7534 7535 u8 reserved_at_40[0x40]; 7536 }; 7537 7538 struct mlx5_ifc_dealloc_flow_counter_in_bits { 7539 u8 opcode[0x10]; 7540 u8 reserved_at_10[0x10]; 7541 7542 u8 reserved_at_20[0x10]; 7543 u8 op_mod[0x10]; 7544 7545 u8 flow_counter_id[0x20]; 7546 7547 u8 reserved_at_60[0x20]; 7548 }; 7549 7550 struct mlx5_ifc_create_xrq_out_bits { 7551 u8 status[0x8]; 7552 u8 reserved_at_8[0x18]; 7553 7554 u8 syndrome[0x20]; 7555 7556 u8 reserved_at_40[0x8]; 7557 u8 xrqn[0x18]; 7558 7559 u8 reserved_at_60[0x20]; 7560 }; 7561 7562 struct mlx5_ifc_create_xrq_in_bits { 7563 u8 opcode[0x10]; 7564 u8 uid[0x10]; 7565 7566 u8 reserved_at_20[0x10]; 7567 u8 op_mod[0x10]; 7568 7569 u8 reserved_at_40[0x40]; 7570 7571 struct mlx5_ifc_xrqc_bits xrq_context; 7572 }; 7573 7574 struct mlx5_ifc_create_xrc_srq_out_bits { 7575 u8 status[0x8]; 7576 u8 reserved_at_8[0x18]; 7577 7578 u8 syndrome[0x20]; 7579 7580 u8 reserved_at_40[0x8]; 7581 u8 xrc_srqn[0x18]; 7582 7583 u8 reserved_at_60[0x20]; 7584 }; 7585 7586 struct mlx5_ifc_create_xrc_srq_in_bits { 7587 u8 opcode[0x10]; 7588 u8 uid[0x10]; 7589 7590 u8 reserved_at_20[0x10]; 7591 u8 op_mod[0x10]; 7592 7593 u8 reserved_at_40[0x40]; 7594 7595 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 7596 7597 u8 reserved_at_280[0x60]; 7598 7599 u8 xrc_srq_umem_valid[0x1]; 7600 u8 reserved_at_2e1[0x1f]; 7601 7602 u8 reserved_at_300[0x580]; 7603 7604 u8 pas[][0x40]; 7605 }; 7606 7607 struct mlx5_ifc_create_tis_out_bits { 7608 u8 status[0x8]; 7609 u8 reserved_at_8[0x18]; 7610 7611 u8 syndrome[0x20]; 7612 7613 u8 reserved_at_40[0x8]; 7614 u8 tisn[0x18]; 7615 7616 u8 reserved_at_60[0x20]; 7617 }; 7618 7619 struct mlx5_ifc_create_tis_in_bits { 7620 u8 opcode[0x10]; 7621 u8 uid[0x10]; 7622 7623 u8 reserved_at_20[0x10]; 7624 u8 op_mod[0x10]; 7625 7626 u8 reserved_at_40[0xc0]; 7627 7628 struct mlx5_ifc_tisc_bits ctx; 7629 }; 7630 7631 struct mlx5_ifc_create_tir_out_bits { 7632 u8 status[0x8]; 7633 u8 icm_address_63_40[0x18]; 7634 7635 u8 syndrome[0x20]; 7636 7637 u8 icm_address_39_32[0x8]; 7638 u8 tirn[0x18]; 7639 7640 u8 icm_address_31_0[0x20]; 7641 }; 7642 7643 struct mlx5_ifc_create_tir_in_bits { 7644 u8 opcode[0x10]; 7645 u8 uid[0x10]; 7646 7647 u8 reserved_at_20[0x10]; 7648 u8 op_mod[0x10]; 7649 7650 u8 reserved_at_40[0xc0]; 7651 7652 struct mlx5_ifc_tirc_bits ctx; 7653 }; 7654 7655 struct mlx5_ifc_create_srq_out_bits { 7656 u8 status[0x8]; 7657 u8 reserved_at_8[0x18]; 7658 7659 u8 syndrome[0x20]; 7660 7661 u8 reserved_at_40[0x8]; 7662 u8 srqn[0x18]; 7663 7664 u8 reserved_at_60[0x20]; 7665 }; 7666 7667 struct mlx5_ifc_create_srq_in_bits { 7668 u8 opcode[0x10]; 7669 u8 uid[0x10]; 7670 7671 u8 reserved_at_20[0x10]; 7672 u8 op_mod[0x10]; 7673 7674 u8 reserved_at_40[0x40]; 7675 7676 struct mlx5_ifc_srqc_bits srq_context_entry; 7677 7678 u8 reserved_at_280[0x600]; 7679 7680 u8 pas[][0x40]; 7681 }; 7682 7683 struct mlx5_ifc_create_sq_out_bits { 7684 u8 status[0x8]; 7685 u8 reserved_at_8[0x18]; 7686 7687 u8 syndrome[0x20]; 7688 7689 u8 reserved_at_40[0x8]; 7690 u8 sqn[0x18]; 7691 7692 u8 reserved_at_60[0x20]; 7693 }; 7694 7695 struct mlx5_ifc_create_sq_in_bits { 7696 u8 opcode[0x10]; 7697 u8 uid[0x10]; 7698 7699 u8 reserved_at_20[0x10]; 7700 u8 op_mod[0x10]; 7701 7702 u8 reserved_at_40[0xc0]; 7703 7704 struct mlx5_ifc_sqc_bits ctx; 7705 }; 7706 7707 struct mlx5_ifc_create_scheduling_element_out_bits { 7708 u8 status[0x8]; 7709 u8 reserved_at_8[0x18]; 7710 7711 u8 syndrome[0x20]; 7712 7713 u8 reserved_at_40[0x40]; 7714 7715 u8 scheduling_element_id[0x20]; 7716 7717 u8 reserved_at_a0[0x160]; 7718 }; 7719 7720 struct mlx5_ifc_create_scheduling_element_in_bits { 7721 u8 opcode[0x10]; 7722 u8 reserved_at_10[0x10]; 7723 7724 u8 reserved_at_20[0x10]; 7725 u8 op_mod[0x10]; 7726 7727 u8 scheduling_hierarchy[0x8]; 7728 u8 reserved_at_48[0x18]; 7729 7730 u8 reserved_at_60[0xa0]; 7731 7732 struct mlx5_ifc_scheduling_context_bits scheduling_context; 7733 7734 u8 reserved_at_300[0x100]; 7735 }; 7736 7737 struct mlx5_ifc_create_rqt_out_bits { 7738 u8 status[0x8]; 7739 u8 reserved_at_8[0x18]; 7740 7741 u8 syndrome[0x20]; 7742 7743 u8 reserved_at_40[0x8]; 7744 u8 rqtn[0x18]; 7745 7746 u8 reserved_at_60[0x20]; 7747 }; 7748 7749 struct mlx5_ifc_create_rqt_in_bits { 7750 u8 opcode[0x10]; 7751 u8 uid[0x10]; 7752 7753 u8 reserved_at_20[0x10]; 7754 u8 op_mod[0x10]; 7755 7756 u8 reserved_at_40[0xc0]; 7757 7758 struct mlx5_ifc_rqtc_bits rqt_context; 7759 }; 7760 7761 struct mlx5_ifc_create_rq_out_bits { 7762 u8 status[0x8]; 7763 u8 reserved_at_8[0x18]; 7764 7765 u8 syndrome[0x20]; 7766 7767 u8 reserved_at_40[0x8]; 7768 u8 rqn[0x18]; 7769 7770 u8 reserved_at_60[0x20]; 7771 }; 7772 7773 struct mlx5_ifc_create_rq_in_bits { 7774 u8 opcode[0x10]; 7775 u8 uid[0x10]; 7776 7777 u8 reserved_at_20[0x10]; 7778 u8 op_mod[0x10]; 7779 7780 u8 reserved_at_40[0xc0]; 7781 7782 struct mlx5_ifc_rqc_bits ctx; 7783 }; 7784 7785 struct mlx5_ifc_create_rmp_out_bits { 7786 u8 status[0x8]; 7787 u8 reserved_at_8[0x18]; 7788 7789 u8 syndrome[0x20]; 7790 7791 u8 reserved_at_40[0x8]; 7792 u8 rmpn[0x18]; 7793 7794 u8 reserved_at_60[0x20]; 7795 }; 7796 7797 struct mlx5_ifc_create_rmp_in_bits { 7798 u8 opcode[0x10]; 7799 u8 uid[0x10]; 7800 7801 u8 reserved_at_20[0x10]; 7802 u8 op_mod[0x10]; 7803 7804 u8 reserved_at_40[0xc0]; 7805 7806 struct mlx5_ifc_rmpc_bits ctx; 7807 }; 7808 7809 struct mlx5_ifc_create_qp_out_bits { 7810 u8 status[0x8]; 7811 u8 reserved_at_8[0x18]; 7812 7813 u8 syndrome[0x20]; 7814 7815 u8 reserved_at_40[0x8]; 7816 u8 qpn[0x18]; 7817 7818 u8 ece[0x20]; 7819 }; 7820 7821 struct mlx5_ifc_create_qp_in_bits { 7822 u8 opcode[0x10]; 7823 u8 uid[0x10]; 7824 7825 u8 reserved_at_20[0x10]; 7826 u8 op_mod[0x10]; 7827 7828 u8 reserved_at_40[0x8]; 7829 u8 input_qpn[0x18]; 7830 7831 u8 reserved_at_60[0x20]; 7832 u8 opt_param_mask[0x20]; 7833 7834 u8 ece[0x20]; 7835 7836 struct mlx5_ifc_qpc_bits qpc; 7837 7838 u8 reserved_at_800[0x60]; 7839 7840 u8 wq_umem_valid[0x1]; 7841 u8 reserved_at_861[0x1f]; 7842 7843 u8 pas[][0x40]; 7844 }; 7845 7846 struct mlx5_ifc_create_psv_out_bits { 7847 u8 status[0x8]; 7848 u8 reserved_at_8[0x18]; 7849 7850 u8 syndrome[0x20]; 7851 7852 u8 reserved_at_40[0x40]; 7853 7854 u8 reserved_at_80[0x8]; 7855 u8 psv0_index[0x18]; 7856 7857 u8 reserved_at_a0[0x8]; 7858 u8 psv1_index[0x18]; 7859 7860 u8 reserved_at_c0[0x8]; 7861 u8 psv2_index[0x18]; 7862 7863 u8 reserved_at_e0[0x8]; 7864 u8 psv3_index[0x18]; 7865 }; 7866 7867 struct mlx5_ifc_create_psv_in_bits { 7868 u8 opcode[0x10]; 7869 u8 reserved_at_10[0x10]; 7870 7871 u8 reserved_at_20[0x10]; 7872 u8 op_mod[0x10]; 7873 7874 u8 num_psv[0x4]; 7875 u8 reserved_at_44[0x4]; 7876 u8 pd[0x18]; 7877 7878 u8 reserved_at_60[0x20]; 7879 }; 7880 7881 struct mlx5_ifc_create_mkey_out_bits { 7882 u8 status[0x8]; 7883 u8 reserved_at_8[0x18]; 7884 7885 u8 syndrome[0x20]; 7886 7887 u8 reserved_at_40[0x8]; 7888 u8 mkey_index[0x18]; 7889 7890 u8 reserved_at_60[0x20]; 7891 }; 7892 7893 struct mlx5_ifc_create_mkey_in_bits { 7894 u8 opcode[0x10]; 7895 u8 uid[0x10]; 7896 7897 u8 reserved_at_20[0x10]; 7898 u8 op_mod[0x10]; 7899 7900 u8 reserved_at_40[0x20]; 7901 7902 u8 pg_access[0x1]; 7903 u8 mkey_umem_valid[0x1]; 7904 u8 reserved_at_62[0x1e]; 7905 7906 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 7907 7908 u8 reserved_at_280[0x80]; 7909 7910 u8 translations_octword_actual_size[0x20]; 7911 7912 u8 reserved_at_320[0x560]; 7913 7914 u8 klm_pas_mtt[][0x20]; 7915 }; 7916 7917 enum { 7918 MLX5_FLOW_TABLE_TYPE_NIC_RX = 0x0, 7919 MLX5_FLOW_TABLE_TYPE_NIC_TX = 0x1, 7920 MLX5_FLOW_TABLE_TYPE_ESW_EGRESS_ACL = 0x2, 7921 MLX5_FLOW_TABLE_TYPE_ESW_INGRESS_ACL = 0x3, 7922 MLX5_FLOW_TABLE_TYPE_FDB = 0X4, 7923 MLX5_FLOW_TABLE_TYPE_SNIFFER_RX = 0X5, 7924 MLX5_FLOW_TABLE_TYPE_SNIFFER_TX = 0X6, 7925 }; 7926 7927 struct mlx5_ifc_create_flow_table_out_bits { 7928 u8 status[0x8]; 7929 u8 icm_address_63_40[0x18]; 7930 7931 u8 syndrome[0x20]; 7932 7933 u8 icm_address_39_32[0x8]; 7934 u8 table_id[0x18]; 7935 7936 u8 icm_address_31_0[0x20]; 7937 }; 7938 7939 struct mlx5_ifc_create_flow_table_in_bits { 7940 u8 opcode[0x10]; 7941 u8 reserved_at_10[0x10]; 7942 7943 u8 reserved_at_20[0x10]; 7944 u8 op_mod[0x10]; 7945 7946 u8 other_vport[0x1]; 7947 u8 reserved_at_41[0xf]; 7948 u8 vport_number[0x10]; 7949 7950 u8 reserved_at_60[0x20]; 7951 7952 u8 table_type[0x8]; 7953 u8 reserved_at_88[0x18]; 7954 7955 u8 reserved_at_a0[0x20]; 7956 7957 struct mlx5_ifc_flow_table_context_bits flow_table_context; 7958 }; 7959 7960 struct mlx5_ifc_create_flow_group_out_bits { 7961 u8 status[0x8]; 7962 u8 reserved_at_8[0x18]; 7963 7964 u8 syndrome[0x20]; 7965 7966 u8 reserved_at_40[0x8]; 7967 u8 group_id[0x18]; 7968 7969 u8 reserved_at_60[0x20]; 7970 }; 7971 7972 enum { 7973 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 7974 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 7975 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 7976 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3, 7977 }; 7978 7979 struct mlx5_ifc_create_flow_group_in_bits { 7980 u8 opcode[0x10]; 7981 u8 reserved_at_10[0x10]; 7982 7983 u8 reserved_at_20[0x10]; 7984 u8 op_mod[0x10]; 7985 7986 u8 other_vport[0x1]; 7987 u8 reserved_at_41[0xf]; 7988 u8 vport_number[0x10]; 7989 7990 u8 reserved_at_60[0x20]; 7991 7992 u8 table_type[0x8]; 7993 u8 reserved_at_88[0x18]; 7994 7995 u8 reserved_at_a0[0x8]; 7996 u8 table_id[0x18]; 7997 7998 u8 source_eswitch_owner_vhca_id_valid[0x1]; 7999 8000 u8 reserved_at_c1[0x1f]; 8001 8002 u8 start_flow_index[0x20]; 8003 8004 u8 reserved_at_100[0x20]; 8005 8006 u8 end_flow_index[0x20]; 8007 8008 u8 reserved_at_140[0xa0]; 8009 8010 u8 reserved_at_1e0[0x18]; 8011 u8 match_criteria_enable[0x8]; 8012 8013 struct mlx5_ifc_fte_match_param_bits match_criteria; 8014 8015 u8 reserved_at_1200[0xe00]; 8016 }; 8017 8018 struct mlx5_ifc_create_eq_out_bits { 8019 u8 status[0x8]; 8020 u8 reserved_at_8[0x18]; 8021 8022 u8 syndrome[0x20]; 8023 8024 u8 reserved_at_40[0x18]; 8025 u8 eq_number[0x8]; 8026 8027 u8 reserved_at_60[0x20]; 8028 }; 8029 8030 struct mlx5_ifc_create_eq_in_bits { 8031 u8 opcode[0x10]; 8032 u8 uid[0x10]; 8033 8034 u8 reserved_at_20[0x10]; 8035 u8 op_mod[0x10]; 8036 8037 u8 reserved_at_40[0x40]; 8038 8039 struct mlx5_ifc_eqc_bits eq_context_entry; 8040 8041 u8 reserved_at_280[0x40]; 8042 8043 u8 event_bitmask[4][0x40]; 8044 8045 u8 reserved_at_3c0[0x4c0]; 8046 8047 u8 pas[][0x40]; 8048 }; 8049 8050 struct mlx5_ifc_create_dct_out_bits { 8051 u8 status[0x8]; 8052 u8 reserved_at_8[0x18]; 8053 8054 u8 syndrome[0x20]; 8055 8056 u8 reserved_at_40[0x8]; 8057 u8 dctn[0x18]; 8058 8059 u8 ece[0x20]; 8060 }; 8061 8062 struct mlx5_ifc_create_dct_in_bits { 8063 u8 opcode[0x10]; 8064 u8 uid[0x10]; 8065 8066 u8 reserved_at_20[0x10]; 8067 u8 op_mod[0x10]; 8068 8069 u8 reserved_at_40[0x40]; 8070 8071 struct mlx5_ifc_dctc_bits dct_context_entry; 8072 8073 u8 reserved_at_280[0x180]; 8074 }; 8075 8076 struct mlx5_ifc_create_cq_out_bits { 8077 u8 status[0x8]; 8078 u8 reserved_at_8[0x18]; 8079 8080 u8 syndrome[0x20]; 8081 8082 u8 reserved_at_40[0x8]; 8083 u8 cqn[0x18]; 8084 8085 u8 reserved_at_60[0x20]; 8086 }; 8087 8088 struct mlx5_ifc_create_cq_in_bits { 8089 u8 opcode[0x10]; 8090 u8 uid[0x10]; 8091 8092 u8 reserved_at_20[0x10]; 8093 u8 op_mod[0x10]; 8094 8095 u8 reserved_at_40[0x40]; 8096 8097 struct mlx5_ifc_cqc_bits cq_context; 8098 8099 u8 reserved_at_280[0x60]; 8100 8101 u8 cq_umem_valid[0x1]; 8102 u8 reserved_at_2e1[0x59f]; 8103 8104 u8 pas[][0x40]; 8105 }; 8106 8107 struct mlx5_ifc_config_int_moderation_out_bits { 8108 u8 status[0x8]; 8109 u8 reserved_at_8[0x18]; 8110 8111 u8 syndrome[0x20]; 8112 8113 u8 reserved_at_40[0x4]; 8114 u8 min_delay[0xc]; 8115 u8 int_vector[0x10]; 8116 8117 u8 reserved_at_60[0x20]; 8118 }; 8119 8120 enum { 8121 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0, 8122 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1, 8123 }; 8124 8125 struct mlx5_ifc_config_int_moderation_in_bits { 8126 u8 opcode[0x10]; 8127 u8 reserved_at_10[0x10]; 8128 8129 u8 reserved_at_20[0x10]; 8130 u8 op_mod[0x10]; 8131 8132 u8 reserved_at_40[0x4]; 8133 u8 min_delay[0xc]; 8134 u8 int_vector[0x10]; 8135 8136 u8 reserved_at_60[0x20]; 8137 }; 8138 8139 struct mlx5_ifc_attach_to_mcg_out_bits { 8140 u8 status[0x8]; 8141 u8 reserved_at_8[0x18]; 8142 8143 u8 syndrome[0x20]; 8144 8145 u8 reserved_at_40[0x40]; 8146 }; 8147 8148 struct mlx5_ifc_attach_to_mcg_in_bits { 8149 u8 opcode[0x10]; 8150 u8 uid[0x10]; 8151 8152 u8 reserved_at_20[0x10]; 8153 u8 op_mod[0x10]; 8154 8155 u8 reserved_at_40[0x8]; 8156 u8 qpn[0x18]; 8157 8158 u8 reserved_at_60[0x20]; 8159 8160 u8 multicast_gid[16][0x8]; 8161 }; 8162 8163 struct mlx5_ifc_arm_xrq_out_bits { 8164 u8 status[0x8]; 8165 u8 reserved_at_8[0x18]; 8166 8167 u8 syndrome[0x20]; 8168 8169 u8 reserved_at_40[0x40]; 8170 }; 8171 8172 struct mlx5_ifc_arm_xrq_in_bits { 8173 u8 opcode[0x10]; 8174 u8 reserved_at_10[0x10]; 8175 8176 u8 reserved_at_20[0x10]; 8177 u8 op_mod[0x10]; 8178 8179 u8 reserved_at_40[0x8]; 8180 u8 xrqn[0x18]; 8181 8182 u8 reserved_at_60[0x10]; 8183 u8 lwm[0x10]; 8184 }; 8185 8186 struct mlx5_ifc_arm_xrc_srq_out_bits { 8187 u8 status[0x8]; 8188 u8 reserved_at_8[0x18]; 8189 8190 u8 syndrome[0x20]; 8191 8192 u8 reserved_at_40[0x40]; 8193 }; 8194 8195 enum { 8196 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1, 8197 }; 8198 8199 struct mlx5_ifc_arm_xrc_srq_in_bits { 8200 u8 opcode[0x10]; 8201 u8 uid[0x10]; 8202 8203 u8 reserved_at_20[0x10]; 8204 u8 op_mod[0x10]; 8205 8206 u8 reserved_at_40[0x8]; 8207 u8 xrc_srqn[0x18]; 8208 8209 u8 reserved_at_60[0x10]; 8210 u8 lwm[0x10]; 8211 }; 8212 8213 struct mlx5_ifc_arm_rq_out_bits { 8214 u8 status[0x8]; 8215 u8 reserved_at_8[0x18]; 8216 8217 u8 syndrome[0x20]; 8218 8219 u8 reserved_at_40[0x40]; 8220 }; 8221 8222 enum { 8223 MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1, 8224 MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2, 8225 }; 8226 8227 struct mlx5_ifc_arm_rq_in_bits { 8228 u8 opcode[0x10]; 8229 u8 uid[0x10]; 8230 8231 u8 reserved_at_20[0x10]; 8232 u8 op_mod[0x10]; 8233 8234 u8 reserved_at_40[0x8]; 8235 u8 srq_number[0x18]; 8236 8237 u8 reserved_at_60[0x10]; 8238 u8 lwm[0x10]; 8239 }; 8240 8241 struct mlx5_ifc_arm_dct_out_bits { 8242 u8 status[0x8]; 8243 u8 reserved_at_8[0x18]; 8244 8245 u8 syndrome[0x20]; 8246 8247 u8 reserved_at_40[0x40]; 8248 }; 8249 8250 struct mlx5_ifc_arm_dct_in_bits { 8251 u8 opcode[0x10]; 8252 u8 reserved_at_10[0x10]; 8253 8254 u8 reserved_at_20[0x10]; 8255 u8 op_mod[0x10]; 8256 8257 u8 reserved_at_40[0x8]; 8258 u8 dct_number[0x18]; 8259 8260 u8 reserved_at_60[0x20]; 8261 }; 8262 8263 struct mlx5_ifc_alloc_xrcd_out_bits { 8264 u8 status[0x8]; 8265 u8 reserved_at_8[0x18]; 8266 8267 u8 syndrome[0x20]; 8268 8269 u8 reserved_at_40[0x8]; 8270 u8 xrcd[0x18]; 8271 8272 u8 reserved_at_60[0x20]; 8273 }; 8274 8275 struct mlx5_ifc_alloc_xrcd_in_bits { 8276 u8 opcode[0x10]; 8277 u8 uid[0x10]; 8278 8279 u8 reserved_at_20[0x10]; 8280 u8 op_mod[0x10]; 8281 8282 u8 reserved_at_40[0x40]; 8283 }; 8284 8285 struct mlx5_ifc_alloc_uar_out_bits { 8286 u8 status[0x8]; 8287 u8 reserved_at_8[0x18]; 8288 8289 u8 syndrome[0x20]; 8290 8291 u8 reserved_at_40[0x8]; 8292 u8 uar[0x18]; 8293 8294 u8 reserved_at_60[0x20]; 8295 }; 8296 8297 struct mlx5_ifc_alloc_uar_in_bits { 8298 u8 opcode[0x10]; 8299 u8 reserved_at_10[0x10]; 8300 8301 u8 reserved_at_20[0x10]; 8302 u8 op_mod[0x10]; 8303 8304 u8 reserved_at_40[0x40]; 8305 }; 8306 8307 struct mlx5_ifc_alloc_transport_domain_out_bits { 8308 u8 status[0x8]; 8309 u8 reserved_at_8[0x18]; 8310 8311 u8 syndrome[0x20]; 8312 8313 u8 reserved_at_40[0x8]; 8314 u8 transport_domain[0x18]; 8315 8316 u8 reserved_at_60[0x20]; 8317 }; 8318 8319 struct mlx5_ifc_alloc_transport_domain_in_bits { 8320 u8 opcode[0x10]; 8321 u8 uid[0x10]; 8322 8323 u8 reserved_at_20[0x10]; 8324 u8 op_mod[0x10]; 8325 8326 u8 reserved_at_40[0x40]; 8327 }; 8328 8329 struct mlx5_ifc_alloc_q_counter_out_bits { 8330 u8 status[0x8]; 8331 u8 reserved_at_8[0x18]; 8332 8333 u8 syndrome[0x20]; 8334 8335 u8 reserved_at_40[0x18]; 8336 u8 counter_set_id[0x8]; 8337 8338 u8 reserved_at_60[0x20]; 8339 }; 8340 8341 struct mlx5_ifc_alloc_q_counter_in_bits { 8342 u8 opcode[0x10]; 8343 u8 uid[0x10]; 8344 8345 u8 reserved_at_20[0x10]; 8346 u8 op_mod[0x10]; 8347 8348 u8 reserved_at_40[0x40]; 8349 }; 8350 8351 struct mlx5_ifc_alloc_pd_out_bits { 8352 u8 status[0x8]; 8353 u8 reserved_at_8[0x18]; 8354 8355 u8 syndrome[0x20]; 8356 8357 u8 reserved_at_40[0x8]; 8358 u8 pd[0x18]; 8359 8360 u8 reserved_at_60[0x20]; 8361 }; 8362 8363 struct mlx5_ifc_alloc_pd_in_bits { 8364 u8 opcode[0x10]; 8365 u8 uid[0x10]; 8366 8367 u8 reserved_at_20[0x10]; 8368 u8 op_mod[0x10]; 8369 8370 u8 reserved_at_40[0x40]; 8371 }; 8372 8373 struct mlx5_ifc_alloc_flow_counter_out_bits { 8374 u8 status[0x8]; 8375 u8 reserved_at_8[0x18]; 8376 8377 u8 syndrome[0x20]; 8378 8379 u8 flow_counter_id[0x20]; 8380 8381 u8 reserved_at_60[0x20]; 8382 }; 8383 8384 struct mlx5_ifc_alloc_flow_counter_in_bits { 8385 u8 opcode[0x10]; 8386 u8 reserved_at_10[0x10]; 8387 8388 u8 reserved_at_20[0x10]; 8389 u8 op_mod[0x10]; 8390 8391 u8 reserved_at_40[0x38]; 8392 u8 flow_counter_bulk[0x8]; 8393 }; 8394 8395 struct mlx5_ifc_add_vxlan_udp_dport_out_bits { 8396 u8 status[0x8]; 8397 u8 reserved_at_8[0x18]; 8398 8399 u8 syndrome[0x20]; 8400 8401 u8 reserved_at_40[0x40]; 8402 }; 8403 8404 struct mlx5_ifc_add_vxlan_udp_dport_in_bits { 8405 u8 opcode[0x10]; 8406 u8 reserved_at_10[0x10]; 8407 8408 u8 reserved_at_20[0x10]; 8409 u8 op_mod[0x10]; 8410 8411 u8 reserved_at_40[0x20]; 8412 8413 u8 reserved_at_60[0x10]; 8414 u8 vxlan_udp_port[0x10]; 8415 }; 8416 8417 struct mlx5_ifc_set_pp_rate_limit_out_bits { 8418 u8 status[0x8]; 8419 u8 reserved_at_8[0x18]; 8420 8421 u8 syndrome[0x20]; 8422 8423 u8 reserved_at_40[0x40]; 8424 }; 8425 8426 struct mlx5_ifc_set_pp_rate_limit_context_bits { 8427 u8 rate_limit[0x20]; 8428 8429 u8 burst_upper_bound[0x20]; 8430 8431 u8 reserved_at_40[0x10]; 8432 u8 typical_packet_size[0x10]; 8433 8434 u8 reserved_at_60[0x120]; 8435 }; 8436 8437 struct mlx5_ifc_set_pp_rate_limit_in_bits { 8438 u8 opcode[0x10]; 8439 u8 uid[0x10]; 8440 8441 u8 reserved_at_20[0x10]; 8442 u8 op_mod[0x10]; 8443 8444 u8 reserved_at_40[0x10]; 8445 u8 rate_limit_index[0x10]; 8446 8447 u8 reserved_at_60[0x20]; 8448 8449 struct mlx5_ifc_set_pp_rate_limit_context_bits ctx; 8450 }; 8451 8452 struct mlx5_ifc_access_register_out_bits { 8453 u8 status[0x8]; 8454 u8 reserved_at_8[0x18]; 8455 8456 u8 syndrome[0x20]; 8457 8458 u8 reserved_at_40[0x40]; 8459 8460 u8 register_data[][0x20]; 8461 }; 8462 8463 enum { 8464 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0, 8465 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1, 8466 }; 8467 8468 struct mlx5_ifc_access_register_in_bits { 8469 u8 opcode[0x10]; 8470 u8 reserved_at_10[0x10]; 8471 8472 u8 reserved_at_20[0x10]; 8473 u8 op_mod[0x10]; 8474 8475 u8 reserved_at_40[0x10]; 8476 u8 register_id[0x10]; 8477 8478 u8 argument[0x20]; 8479 8480 u8 register_data[][0x20]; 8481 }; 8482 8483 struct mlx5_ifc_sltp_reg_bits { 8484 u8 status[0x4]; 8485 u8 version[0x4]; 8486 u8 local_port[0x8]; 8487 u8 pnat[0x2]; 8488 u8 reserved_at_12[0x2]; 8489 u8 lane[0x4]; 8490 u8 reserved_at_18[0x8]; 8491 8492 u8 reserved_at_20[0x20]; 8493 8494 u8 reserved_at_40[0x7]; 8495 u8 polarity[0x1]; 8496 u8 ob_tap0[0x8]; 8497 u8 ob_tap1[0x8]; 8498 u8 ob_tap2[0x8]; 8499 8500 u8 reserved_at_60[0xc]; 8501 u8 ob_preemp_mode[0x4]; 8502 u8 ob_reg[0x8]; 8503 u8 ob_bias[0x8]; 8504 8505 u8 reserved_at_80[0x20]; 8506 }; 8507 8508 struct mlx5_ifc_slrg_reg_bits { 8509 u8 status[0x4]; 8510 u8 version[0x4]; 8511 u8 local_port[0x8]; 8512 u8 pnat[0x2]; 8513 u8 reserved_at_12[0x2]; 8514 u8 lane[0x4]; 8515 u8 reserved_at_18[0x8]; 8516 8517 u8 time_to_link_up[0x10]; 8518 u8 reserved_at_30[0xc]; 8519 u8 grade_lane_speed[0x4]; 8520 8521 u8 grade_version[0x8]; 8522 u8 grade[0x18]; 8523 8524 u8 reserved_at_60[0x4]; 8525 u8 height_grade_type[0x4]; 8526 u8 height_grade[0x18]; 8527 8528 u8 height_dz[0x10]; 8529 u8 height_dv[0x10]; 8530 8531 u8 reserved_at_a0[0x10]; 8532 u8 height_sigma[0x10]; 8533 8534 u8 reserved_at_c0[0x20]; 8535 8536 u8 reserved_at_e0[0x4]; 8537 u8 phase_grade_type[0x4]; 8538 u8 phase_grade[0x18]; 8539 8540 u8 reserved_at_100[0x8]; 8541 u8 phase_eo_pos[0x8]; 8542 u8 reserved_at_110[0x8]; 8543 u8 phase_eo_neg[0x8]; 8544 8545 u8 ffe_set_tested[0x10]; 8546 u8 test_errors_per_lane[0x10]; 8547 }; 8548 8549 struct mlx5_ifc_pvlc_reg_bits { 8550 u8 reserved_at_0[0x8]; 8551 u8 local_port[0x8]; 8552 u8 reserved_at_10[0x10]; 8553 8554 u8 reserved_at_20[0x1c]; 8555 u8 vl_hw_cap[0x4]; 8556 8557 u8 reserved_at_40[0x1c]; 8558 u8 vl_admin[0x4]; 8559 8560 u8 reserved_at_60[0x1c]; 8561 u8 vl_operational[0x4]; 8562 }; 8563 8564 struct mlx5_ifc_pude_reg_bits { 8565 u8 swid[0x8]; 8566 u8 local_port[0x8]; 8567 u8 reserved_at_10[0x4]; 8568 u8 admin_status[0x4]; 8569 u8 reserved_at_18[0x4]; 8570 u8 oper_status[0x4]; 8571 8572 u8 reserved_at_20[0x60]; 8573 }; 8574 8575 struct mlx5_ifc_ptys_reg_bits { 8576 u8 reserved_at_0[0x1]; 8577 u8 an_disable_admin[0x1]; 8578 u8 an_disable_cap[0x1]; 8579 u8 reserved_at_3[0x5]; 8580 u8 local_port[0x8]; 8581 u8 reserved_at_10[0xd]; 8582 u8 proto_mask[0x3]; 8583 8584 u8 an_status[0x4]; 8585 u8 reserved_at_24[0xc]; 8586 u8 data_rate_oper[0x10]; 8587 8588 u8 ext_eth_proto_capability[0x20]; 8589 8590 u8 eth_proto_capability[0x20]; 8591 8592 u8 ib_link_width_capability[0x10]; 8593 u8 ib_proto_capability[0x10]; 8594 8595 u8 ext_eth_proto_admin[0x20]; 8596 8597 u8 eth_proto_admin[0x20]; 8598 8599 u8 ib_link_width_admin[0x10]; 8600 u8 ib_proto_admin[0x10]; 8601 8602 u8 ext_eth_proto_oper[0x20]; 8603 8604 u8 eth_proto_oper[0x20]; 8605 8606 u8 ib_link_width_oper[0x10]; 8607 u8 ib_proto_oper[0x10]; 8608 8609 u8 reserved_at_160[0x1c]; 8610 u8 connector_type[0x4]; 8611 8612 u8 eth_proto_lp_advertise[0x20]; 8613 8614 u8 reserved_at_1a0[0x60]; 8615 }; 8616 8617 struct mlx5_ifc_mlcr_reg_bits { 8618 u8 reserved_at_0[0x8]; 8619 u8 local_port[0x8]; 8620 u8 reserved_at_10[0x20]; 8621 8622 u8 beacon_duration[0x10]; 8623 u8 reserved_at_40[0x10]; 8624 8625 u8 beacon_remain[0x10]; 8626 }; 8627 8628 struct mlx5_ifc_ptas_reg_bits { 8629 u8 reserved_at_0[0x20]; 8630 8631 u8 algorithm_options[0x10]; 8632 u8 reserved_at_30[0x4]; 8633 u8 repetitions_mode[0x4]; 8634 u8 num_of_repetitions[0x8]; 8635 8636 u8 grade_version[0x8]; 8637 u8 height_grade_type[0x4]; 8638 u8 phase_grade_type[0x4]; 8639 u8 height_grade_weight[0x8]; 8640 u8 phase_grade_weight[0x8]; 8641 8642 u8 gisim_measure_bits[0x10]; 8643 u8 adaptive_tap_measure_bits[0x10]; 8644 8645 u8 ber_bath_high_error_threshold[0x10]; 8646 u8 ber_bath_mid_error_threshold[0x10]; 8647 8648 u8 ber_bath_low_error_threshold[0x10]; 8649 u8 one_ratio_high_threshold[0x10]; 8650 8651 u8 one_ratio_high_mid_threshold[0x10]; 8652 u8 one_ratio_low_mid_threshold[0x10]; 8653 8654 u8 one_ratio_low_threshold[0x10]; 8655 u8 ndeo_error_threshold[0x10]; 8656 8657 u8 mixer_offset_step_size[0x10]; 8658 u8 reserved_at_110[0x8]; 8659 u8 mix90_phase_for_voltage_bath[0x8]; 8660 8661 u8 mixer_offset_start[0x10]; 8662 u8 mixer_offset_end[0x10]; 8663 8664 u8 reserved_at_140[0x15]; 8665 u8 ber_test_time[0xb]; 8666 }; 8667 8668 struct mlx5_ifc_pspa_reg_bits { 8669 u8 swid[0x8]; 8670 u8 local_port[0x8]; 8671 u8 sub_port[0x8]; 8672 u8 reserved_at_18[0x8]; 8673 8674 u8 reserved_at_20[0x20]; 8675 }; 8676 8677 struct mlx5_ifc_pqdr_reg_bits { 8678 u8 reserved_at_0[0x8]; 8679 u8 local_port[0x8]; 8680 u8 reserved_at_10[0x5]; 8681 u8 prio[0x3]; 8682 u8 reserved_at_18[0x6]; 8683 u8 mode[0x2]; 8684 8685 u8 reserved_at_20[0x20]; 8686 8687 u8 reserved_at_40[0x10]; 8688 u8 min_threshold[0x10]; 8689 8690 u8 reserved_at_60[0x10]; 8691 u8 max_threshold[0x10]; 8692 8693 u8 reserved_at_80[0x10]; 8694 u8 mark_probability_denominator[0x10]; 8695 8696 u8 reserved_at_a0[0x60]; 8697 }; 8698 8699 struct mlx5_ifc_ppsc_reg_bits { 8700 u8 reserved_at_0[0x8]; 8701 u8 local_port[0x8]; 8702 u8 reserved_at_10[0x10]; 8703 8704 u8 reserved_at_20[0x60]; 8705 8706 u8 reserved_at_80[0x1c]; 8707 u8 wrps_admin[0x4]; 8708 8709 u8 reserved_at_a0[0x1c]; 8710 u8 wrps_status[0x4]; 8711 8712 u8 reserved_at_c0[0x8]; 8713 u8 up_threshold[0x8]; 8714 u8 reserved_at_d0[0x8]; 8715 u8 down_threshold[0x8]; 8716 8717 u8 reserved_at_e0[0x20]; 8718 8719 u8 reserved_at_100[0x1c]; 8720 u8 srps_admin[0x4]; 8721 8722 u8 reserved_at_120[0x1c]; 8723 u8 srps_status[0x4]; 8724 8725 u8 reserved_at_140[0x40]; 8726 }; 8727 8728 struct mlx5_ifc_pplr_reg_bits { 8729 u8 reserved_at_0[0x8]; 8730 u8 local_port[0x8]; 8731 u8 reserved_at_10[0x10]; 8732 8733 u8 reserved_at_20[0x8]; 8734 u8 lb_cap[0x8]; 8735 u8 reserved_at_30[0x8]; 8736 u8 lb_en[0x8]; 8737 }; 8738 8739 struct mlx5_ifc_pplm_reg_bits { 8740 u8 reserved_at_0[0x8]; 8741 u8 local_port[0x8]; 8742 u8 reserved_at_10[0x10]; 8743 8744 u8 reserved_at_20[0x20]; 8745 8746 u8 port_profile_mode[0x8]; 8747 u8 static_port_profile[0x8]; 8748 u8 active_port_profile[0x8]; 8749 u8 reserved_at_58[0x8]; 8750 8751 u8 retransmission_active[0x8]; 8752 u8 fec_mode_active[0x18]; 8753 8754 u8 rs_fec_correction_bypass_cap[0x4]; 8755 u8 reserved_at_84[0x8]; 8756 u8 fec_override_cap_56g[0x4]; 8757 u8 fec_override_cap_100g[0x4]; 8758 u8 fec_override_cap_50g[0x4]; 8759 u8 fec_override_cap_25g[0x4]; 8760 u8 fec_override_cap_10g_40g[0x4]; 8761 8762 u8 rs_fec_correction_bypass_admin[0x4]; 8763 u8 reserved_at_a4[0x8]; 8764 u8 fec_override_admin_56g[0x4]; 8765 u8 fec_override_admin_100g[0x4]; 8766 u8 fec_override_admin_50g[0x4]; 8767 u8 fec_override_admin_25g[0x4]; 8768 u8 fec_override_admin_10g_40g[0x4]; 8769 8770 u8 fec_override_cap_400g_8x[0x10]; 8771 u8 fec_override_cap_200g_4x[0x10]; 8772 8773 u8 fec_override_cap_100g_2x[0x10]; 8774 u8 fec_override_cap_50g_1x[0x10]; 8775 8776 u8 fec_override_admin_400g_8x[0x10]; 8777 u8 fec_override_admin_200g_4x[0x10]; 8778 8779 u8 fec_override_admin_100g_2x[0x10]; 8780 u8 fec_override_admin_50g_1x[0x10]; 8781 }; 8782 8783 struct mlx5_ifc_ppcnt_reg_bits { 8784 u8 swid[0x8]; 8785 u8 local_port[0x8]; 8786 u8 pnat[0x2]; 8787 u8 reserved_at_12[0x8]; 8788 u8 grp[0x6]; 8789 8790 u8 clr[0x1]; 8791 u8 reserved_at_21[0x1c]; 8792 u8 prio_tc[0x3]; 8793 8794 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set; 8795 }; 8796 8797 struct mlx5_ifc_mpein_reg_bits { 8798 u8 reserved_at_0[0x2]; 8799 u8 depth[0x6]; 8800 u8 pcie_index[0x8]; 8801 u8 node[0x8]; 8802 u8 reserved_at_18[0x8]; 8803 8804 u8 capability_mask[0x20]; 8805 8806 u8 reserved_at_40[0x8]; 8807 u8 link_width_enabled[0x8]; 8808 u8 link_speed_enabled[0x10]; 8809 8810 u8 lane0_physical_position[0x8]; 8811 u8 link_width_active[0x8]; 8812 u8 link_speed_active[0x10]; 8813 8814 u8 num_of_pfs[0x10]; 8815 u8 num_of_vfs[0x10]; 8816 8817 u8 bdf0[0x10]; 8818 u8 reserved_at_b0[0x10]; 8819 8820 u8 max_read_request_size[0x4]; 8821 u8 max_payload_size[0x4]; 8822 u8 reserved_at_c8[0x5]; 8823 u8 pwr_status[0x3]; 8824 u8 port_type[0x4]; 8825 u8 reserved_at_d4[0xb]; 8826 u8 lane_reversal[0x1]; 8827 8828 u8 reserved_at_e0[0x14]; 8829 u8 pci_power[0xc]; 8830 8831 u8 reserved_at_100[0x20]; 8832 8833 u8 device_status[0x10]; 8834 u8 port_state[0x8]; 8835 u8 reserved_at_138[0x8]; 8836 8837 u8 reserved_at_140[0x10]; 8838 u8 receiver_detect_result[0x10]; 8839 8840 u8 reserved_at_160[0x20]; 8841 }; 8842 8843 struct mlx5_ifc_mpcnt_reg_bits { 8844 u8 reserved_at_0[0x8]; 8845 u8 pcie_index[0x8]; 8846 u8 reserved_at_10[0xa]; 8847 u8 grp[0x6]; 8848 8849 u8 clr[0x1]; 8850 u8 reserved_at_21[0x1f]; 8851 8852 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set; 8853 }; 8854 8855 struct mlx5_ifc_ppad_reg_bits { 8856 u8 reserved_at_0[0x3]; 8857 u8 single_mac[0x1]; 8858 u8 reserved_at_4[0x4]; 8859 u8 local_port[0x8]; 8860 u8 mac_47_32[0x10]; 8861 8862 u8 mac_31_0[0x20]; 8863 8864 u8 reserved_at_40[0x40]; 8865 }; 8866 8867 struct mlx5_ifc_pmtu_reg_bits { 8868 u8 reserved_at_0[0x8]; 8869 u8 local_port[0x8]; 8870 u8 reserved_at_10[0x10]; 8871 8872 u8 max_mtu[0x10]; 8873 u8 reserved_at_30[0x10]; 8874 8875 u8 admin_mtu[0x10]; 8876 u8 reserved_at_50[0x10]; 8877 8878 u8 oper_mtu[0x10]; 8879 u8 reserved_at_70[0x10]; 8880 }; 8881 8882 struct mlx5_ifc_pmpr_reg_bits { 8883 u8 reserved_at_0[0x8]; 8884 u8 module[0x8]; 8885 u8 reserved_at_10[0x10]; 8886 8887 u8 reserved_at_20[0x18]; 8888 u8 attenuation_5g[0x8]; 8889 8890 u8 reserved_at_40[0x18]; 8891 u8 attenuation_7g[0x8]; 8892 8893 u8 reserved_at_60[0x18]; 8894 u8 attenuation_12g[0x8]; 8895 }; 8896 8897 struct mlx5_ifc_pmpe_reg_bits { 8898 u8 reserved_at_0[0x8]; 8899 u8 module[0x8]; 8900 u8 reserved_at_10[0xc]; 8901 u8 module_status[0x4]; 8902 8903 u8 reserved_at_20[0x60]; 8904 }; 8905 8906 struct mlx5_ifc_pmpc_reg_bits { 8907 u8 module_state_updated[32][0x8]; 8908 }; 8909 8910 struct mlx5_ifc_pmlpn_reg_bits { 8911 u8 reserved_at_0[0x4]; 8912 u8 mlpn_status[0x4]; 8913 u8 local_port[0x8]; 8914 u8 reserved_at_10[0x10]; 8915 8916 u8 e[0x1]; 8917 u8 reserved_at_21[0x1f]; 8918 }; 8919 8920 struct mlx5_ifc_pmlp_reg_bits { 8921 u8 rxtx[0x1]; 8922 u8 reserved_at_1[0x7]; 8923 u8 local_port[0x8]; 8924 u8 reserved_at_10[0x8]; 8925 u8 width[0x8]; 8926 8927 u8 lane0_module_mapping[0x20]; 8928 8929 u8 lane1_module_mapping[0x20]; 8930 8931 u8 lane2_module_mapping[0x20]; 8932 8933 u8 lane3_module_mapping[0x20]; 8934 8935 u8 reserved_at_a0[0x160]; 8936 }; 8937 8938 struct mlx5_ifc_pmaos_reg_bits { 8939 u8 reserved_at_0[0x8]; 8940 u8 module[0x8]; 8941 u8 reserved_at_10[0x4]; 8942 u8 admin_status[0x4]; 8943 u8 reserved_at_18[0x4]; 8944 u8 oper_status[0x4]; 8945 8946 u8 ase[0x1]; 8947 u8 ee[0x1]; 8948 u8 reserved_at_22[0x1c]; 8949 u8 e[0x2]; 8950 8951 u8 reserved_at_40[0x40]; 8952 }; 8953 8954 struct mlx5_ifc_plpc_reg_bits { 8955 u8 reserved_at_0[0x4]; 8956 u8 profile_id[0xc]; 8957 u8 reserved_at_10[0x4]; 8958 u8 proto_mask[0x4]; 8959 u8 reserved_at_18[0x8]; 8960 8961 u8 reserved_at_20[0x10]; 8962 u8 lane_speed[0x10]; 8963 8964 u8 reserved_at_40[0x17]; 8965 u8 lpbf[0x1]; 8966 u8 fec_mode_policy[0x8]; 8967 8968 u8 retransmission_capability[0x8]; 8969 u8 fec_mode_capability[0x18]; 8970 8971 u8 retransmission_support_admin[0x8]; 8972 u8 fec_mode_support_admin[0x18]; 8973 8974 u8 retransmission_request_admin[0x8]; 8975 u8 fec_mode_request_admin[0x18]; 8976 8977 u8 reserved_at_c0[0x80]; 8978 }; 8979 8980 struct mlx5_ifc_plib_reg_bits { 8981 u8 reserved_at_0[0x8]; 8982 u8 local_port[0x8]; 8983 u8 reserved_at_10[0x8]; 8984 u8 ib_port[0x8]; 8985 8986 u8 reserved_at_20[0x60]; 8987 }; 8988 8989 struct mlx5_ifc_plbf_reg_bits { 8990 u8 reserved_at_0[0x8]; 8991 u8 local_port[0x8]; 8992 u8 reserved_at_10[0xd]; 8993 u8 lbf_mode[0x3]; 8994 8995 u8 reserved_at_20[0x20]; 8996 }; 8997 8998 struct mlx5_ifc_pipg_reg_bits { 8999 u8 reserved_at_0[0x8]; 9000 u8 local_port[0x8]; 9001 u8 reserved_at_10[0x10]; 9002 9003 u8 dic[0x1]; 9004 u8 reserved_at_21[0x19]; 9005 u8 ipg[0x4]; 9006 u8 reserved_at_3e[0x2]; 9007 }; 9008 9009 struct mlx5_ifc_pifr_reg_bits { 9010 u8 reserved_at_0[0x8]; 9011 u8 local_port[0x8]; 9012 u8 reserved_at_10[0x10]; 9013 9014 u8 reserved_at_20[0xe0]; 9015 9016 u8 port_filter[8][0x20]; 9017 9018 u8 port_filter_update_en[8][0x20]; 9019 }; 9020 9021 struct mlx5_ifc_pfcc_reg_bits { 9022 u8 reserved_at_0[0x8]; 9023 u8 local_port[0x8]; 9024 u8 reserved_at_10[0xb]; 9025 u8 ppan_mask_n[0x1]; 9026 u8 minor_stall_mask[0x1]; 9027 u8 critical_stall_mask[0x1]; 9028 u8 reserved_at_1e[0x2]; 9029 9030 u8 ppan[0x4]; 9031 u8 reserved_at_24[0x4]; 9032 u8 prio_mask_tx[0x8]; 9033 u8 reserved_at_30[0x8]; 9034 u8 prio_mask_rx[0x8]; 9035 9036 u8 pptx[0x1]; 9037 u8 aptx[0x1]; 9038 u8 pptx_mask_n[0x1]; 9039 u8 reserved_at_43[0x5]; 9040 u8 pfctx[0x8]; 9041 u8 reserved_at_50[0x10]; 9042 9043 u8 pprx[0x1]; 9044 u8 aprx[0x1]; 9045 u8 pprx_mask_n[0x1]; 9046 u8 reserved_at_63[0x5]; 9047 u8 pfcrx[0x8]; 9048 u8 reserved_at_70[0x10]; 9049 9050 u8 device_stall_minor_watermark[0x10]; 9051 u8 device_stall_critical_watermark[0x10]; 9052 9053 u8 reserved_at_a0[0x60]; 9054 }; 9055 9056 struct mlx5_ifc_pelc_reg_bits { 9057 u8 op[0x4]; 9058 u8 reserved_at_4[0x4]; 9059 u8 local_port[0x8]; 9060 u8 reserved_at_10[0x10]; 9061 9062 u8 op_admin[0x8]; 9063 u8 op_capability[0x8]; 9064 u8 op_request[0x8]; 9065 u8 op_active[0x8]; 9066 9067 u8 admin[0x40]; 9068 9069 u8 capability[0x40]; 9070 9071 u8 request[0x40]; 9072 9073 u8 active[0x40]; 9074 9075 u8 reserved_at_140[0x80]; 9076 }; 9077 9078 struct mlx5_ifc_peir_reg_bits { 9079 u8 reserved_at_0[0x8]; 9080 u8 local_port[0x8]; 9081 u8 reserved_at_10[0x10]; 9082 9083 u8 reserved_at_20[0xc]; 9084 u8 error_count[0x4]; 9085 u8 reserved_at_30[0x10]; 9086 9087 u8 reserved_at_40[0xc]; 9088 u8 lane[0x4]; 9089 u8 reserved_at_50[0x8]; 9090 u8 error_type[0x8]; 9091 }; 9092 9093 struct mlx5_ifc_mpegc_reg_bits { 9094 u8 reserved_at_0[0x30]; 9095 u8 field_select[0x10]; 9096 9097 u8 tx_overflow_sense[0x1]; 9098 u8 mark_cqe[0x1]; 9099 u8 mark_cnp[0x1]; 9100 u8 reserved_at_43[0x1b]; 9101 u8 tx_lossy_overflow_oper[0x2]; 9102 9103 u8 reserved_at_60[0x100]; 9104 }; 9105 9106 struct mlx5_ifc_pcam_enhanced_features_bits { 9107 u8 reserved_at_0[0x68]; 9108 u8 fec_50G_per_lane_in_pplm[0x1]; 9109 u8 reserved_at_69[0x4]; 9110 u8 rx_icrc_encapsulated_counter[0x1]; 9111 u8 reserved_at_6e[0x4]; 9112 u8 ptys_extended_ethernet[0x1]; 9113 u8 reserved_at_73[0x3]; 9114 u8 pfcc_mask[0x1]; 9115 u8 reserved_at_77[0x3]; 9116 u8 per_lane_error_counters[0x1]; 9117 u8 rx_buffer_fullness_counters[0x1]; 9118 u8 ptys_connector_type[0x1]; 9119 u8 reserved_at_7d[0x1]; 9120 u8 ppcnt_discard_group[0x1]; 9121 u8 ppcnt_statistical_group[0x1]; 9122 }; 9123 9124 struct mlx5_ifc_pcam_regs_5000_to_507f_bits { 9125 u8 port_access_reg_cap_mask_127_to_96[0x20]; 9126 u8 port_access_reg_cap_mask_95_to_64[0x20]; 9127 9128 u8 port_access_reg_cap_mask_63_to_36[0x1c]; 9129 u8 pplm[0x1]; 9130 u8 port_access_reg_cap_mask_34_to_32[0x3]; 9131 9132 u8 port_access_reg_cap_mask_31_to_13[0x13]; 9133 u8 pbmc[0x1]; 9134 u8 pptb[0x1]; 9135 u8 port_access_reg_cap_mask_10_to_09[0x2]; 9136 u8 ppcnt[0x1]; 9137 u8 port_access_reg_cap_mask_07_to_00[0x8]; 9138 }; 9139 9140 struct mlx5_ifc_pcam_reg_bits { 9141 u8 reserved_at_0[0x8]; 9142 u8 feature_group[0x8]; 9143 u8 reserved_at_10[0x8]; 9144 u8 access_reg_group[0x8]; 9145 9146 u8 reserved_at_20[0x20]; 9147 9148 union { 9149 struct mlx5_ifc_pcam_regs_5000_to_507f_bits regs_5000_to_507f; 9150 u8 reserved_at_0[0x80]; 9151 } port_access_reg_cap_mask; 9152 9153 u8 reserved_at_c0[0x80]; 9154 9155 union { 9156 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features; 9157 u8 reserved_at_0[0x80]; 9158 } feature_cap_mask; 9159 9160 u8 reserved_at_1c0[0xc0]; 9161 }; 9162 9163 struct mlx5_ifc_mcam_enhanced_features_bits { 9164 u8 reserved_at_0[0x6e]; 9165 u8 pci_status_and_power[0x1]; 9166 u8 reserved_at_6f[0x5]; 9167 u8 mark_tx_action_cnp[0x1]; 9168 u8 mark_tx_action_cqe[0x1]; 9169 u8 dynamic_tx_overflow[0x1]; 9170 u8 reserved_at_77[0x4]; 9171 u8 pcie_outbound_stalled[0x1]; 9172 u8 tx_overflow_buffer_pkt[0x1]; 9173 u8 mtpps_enh_out_per_adj[0x1]; 9174 u8 mtpps_fs[0x1]; 9175 u8 pcie_performance_group[0x1]; 9176 }; 9177 9178 struct mlx5_ifc_mcam_access_reg_bits { 9179 u8 reserved_at_0[0x1c]; 9180 u8 mcda[0x1]; 9181 u8 mcc[0x1]; 9182 u8 mcqi[0x1]; 9183 u8 mcqs[0x1]; 9184 9185 u8 regs_95_to_87[0x9]; 9186 u8 mpegc[0x1]; 9187 u8 regs_85_to_68[0x12]; 9188 u8 tracer_registers[0x4]; 9189 9190 u8 regs_63_to_32[0x20]; 9191 u8 regs_31_to_0[0x20]; 9192 }; 9193 9194 struct mlx5_ifc_mcam_access_reg_bits1 { 9195 u8 regs_127_to_96[0x20]; 9196 9197 u8 regs_95_to_64[0x20]; 9198 9199 u8 regs_63_to_32[0x20]; 9200 9201 u8 regs_31_to_0[0x20]; 9202 }; 9203 9204 struct mlx5_ifc_mcam_access_reg_bits2 { 9205 u8 regs_127_to_99[0x1d]; 9206 u8 mirc[0x1]; 9207 u8 regs_97_to_96[0x2]; 9208 9209 u8 regs_95_to_64[0x20]; 9210 9211 u8 regs_63_to_32[0x20]; 9212 9213 u8 regs_31_to_0[0x20]; 9214 }; 9215 9216 struct mlx5_ifc_mcam_reg_bits { 9217 u8 reserved_at_0[0x8]; 9218 u8 feature_group[0x8]; 9219 u8 reserved_at_10[0x8]; 9220 u8 access_reg_group[0x8]; 9221 9222 u8 reserved_at_20[0x20]; 9223 9224 union { 9225 struct mlx5_ifc_mcam_access_reg_bits access_regs; 9226 struct mlx5_ifc_mcam_access_reg_bits1 access_regs1; 9227 struct mlx5_ifc_mcam_access_reg_bits2 access_regs2; 9228 u8 reserved_at_0[0x80]; 9229 } mng_access_reg_cap_mask; 9230 9231 u8 reserved_at_c0[0x80]; 9232 9233 union { 9234 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features; 9235 u8 reserved_at_0[0x80]; 9236 } mng_feature_cap_mask; 9237 9238 u8 reserved_at_1c0[0x80]; 9239 }; 9240 9241 struct mlx5_ifc_qcam_access_reg_cap_mask { 9242 u8 qcam_access_reg_cap_mask_127_to_20[0x6C]; 9243 u8 qpdpm[0x1]; 9244 u8 qcam_access_reg_cap_mask_18_to_4[0x0F]; 9245 u8 qdpm[0x1]; 9246 u8 qpts[0x1]; 9247 u8 qcap[0x1]; 9248 u8 qcam_access_reg_cap_mask_0[0x1]; 9249 }; 9250 9251 struct mlx5_ifc_qcam_qos_feature_cap_mask { 9252 u8 qcam_qos_feature_cap_mask_127_to_1[0x7F]; 9253 u8 qpts_trust_both[0x1]; 9254 }; 9255 9256 struct mlx5_ifc_qcam_reg_bits { 9257 u8 reserved_at_0[0x8]; 9258 u8 feature_group[0x8]; 9259 u8 reserved_at_10[0x8]; 9260 u8 access_reg_group[0x8]; 9261 u8 reserved_at_20[0x20]; 9262 9263 union { 9264 struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap; 9265 u8 reserved_at_0[0x80]; 9266 } qos_access_reg_cap_mask; 9267 9268 u8 reserved_at_c0[0x80]; 9269 9270 union { 9271 struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap; 9272 u8 reserved_at_0[0x80]; 9273 } qos_feature_cap_mask; 9274 9275 u8 reserved_at_1c0[0x80]; 9276 }; 9277 9278 struct mlx5_ifc_core_dump_reg_bits { 9279 u8 reserved_at_0[0x18]; 9280 u8 core_dump_type[0x8]; 9281 9282 u8 reserved_at_20[0x30]; 9283 u8 vhca_id[0x10]; 9284 9285 u8 reserved_at_60[0x8]; 9286 u8 qpn[0x18]; 9287 u8 reserved_at_80[0x180]; 9288 }; 9289 9290 struct mlx5_ifc_pcap_reg_bits { 9291 u8 reserved_at_0[0x8]; 9292 u8 local_port[0x8]; 9293 u8 reserved_at_10[0x10]; 9294 9295 u8 port_capability_mask[4][0x20]; 9296 }; 9297 9298 struct mlx5_ifc_paos_reg_bits { 9299 u8 swid[0x8]; 9300 u8 local_port[0x8]; 9301 u8 reserved_at_10[0x4]; 9302 u8 admin_status[0x4]; 9303 u8 reserved_at_18[0x4]; 9304 u8 oper_status[0x4]; 9305 9306 u8 ase[0x1]; 9307 u8 ee[0x1]; 9308 u8 reserved_at_22[0x1c]; 9309 u8 e[0x2]; 9310 9311 u8 reserved_at_40[0x40]; 9312 }; 9313 9314 struct mlx5_ifc_pamp_reg_bits { 9315 u8 reserved_at_0[0x8]; 9316 u8 opamp_group[0x8]; 9317 u8 reserved_at_10[0xc]; 9318 u8 opamp_group_type[0x4]; 9319 9320 u8 start_index[0x10]; 9321 u8 reserved_at_30[0x4]; 9322 u8 num_of_indices[0xc]; 9323 9324 u8 index_data[18][0x10]; 9325 }; 9326 9327 struct mlx5_ifc_pcmr_reg_bits { 9328 u8 reserved_at_0[0x8]; 9329 u8 local_port[0x8]; 9330 u8 reserved_at_10[0x10]; 9331 u8 entropy_force_cap[0x1]; 9332 u8 entropy_calc_cap[0x1]; 9333 u8 entropy_gre_calc_cap[0x1]; 9334 u8 reserved_at_23[0x1b]; 9335 u8 fcs_cap[0x1]; 9336 u8 reserved_at_3f[0x1]; 9337 u8 entropy_force[0x1]; 9338 u8 entropy_calc[0x1]; 9339 u8 entropy_gre_calc[0x1]; 9340 u8 reserved_at_43[0x1b]; 9341 u8 fcs_chk[0x1]; 9342 u8 reserved_at_5f[0x1]; 9343 }; 9344 9345 struct mlx5_ifc_lane_2_module_mapping_bits { 9346 u8 reserved_at_0[0x6]; 9347 u8 rx_lane[0x2]; 9348 u8 reserved_at_8[0x6]; 9349 u8 tx_lane[0x2]; 9350 u8 reserved_at_10[0x8]; 9351 u8 module[0x8]; 9352 }; 9353 9354 struct mlx5_ifc_bufferx_reg_bits { 9355 u8 reserved_at_0[0x6]; 9356 u8 lossy[0x1]; 9357 u8 epsb[0x1]; 9358 u8 reserved_at_8[0xc]; 9359 u8 size[0xc]; 9360 9361 u8 xoff_threshold[0x10]; 9362 u8 xon_threshold[0x10]; 9363 }; 9364 9365 struct mlx5_ifc_set_node_in_bits { 9366 u8 node_description[64][0x8]; 9367 }; 9368 9369 struct mlx5_ifc_register_power_settings_bits { 9370 u8 reserved_at_0[0x18]; 9371 u8 power_settings_level[0x8]; 9372 9373 u8 reserved_at_20[0x60]; 9374 }; 9375 9376 struct mlx5_ifc_register_host_endianness_bits { 9377 u8 he[0x1]; 9378 u8 reserved_at_1[0x1f]; 9379 9380 u8 reserved_at_20[0x60]; 9381 }; 9382 9383 struct mlx5_ifc_umr_pointer_desc_argument_bits { 9384 u8 reserved_at_0[0x20]; 9385 9386 u8 mkey[0x20]; 9387 9388 u8 addressh_63_32[0x20]; 9389 9390 u8 addressl_31_0[0x20]; 9391 }; 9392 9393 struct mlx5_ifc_ud_adrs_vector_bits { 9394 u8 dc_key[0x40]; 9395 9396 u8 ext[0x1]; 9397 u8 reserved_at_41[0x7]; 9398 u8 destination_qp_dct[0x18]; 9399 9400 u8 static_rate[0x4]; 9401 u8 sl_eth_prio[0x4]; 9402 u8 fl[0x1]; 9403 u8 mlid[0x7]; 9404 u8 rlid_udp_sport[0x10]; 9405 9406 u8 reserved_at_80[0x20]; 9407 9408 u8 rmac_47_16[0x20]; 9409 9410 u8 rmac_15_0[0x10]; 9411 u8 tclass[0x8]; 9412 u8 hop_limit[0x8]; 9413 9414 u8 reserved_at_e0[0x1]; 9415 u8 grh[0x1]; 9416 u8 reserved_at_e2[0x2]; 9417 u8 src_addr_index[0x8]; 9418 u8 flow_label[0x14]; 9419 9420 u8 rgid_rip[16][0x8]; 9421 }; 9422 9423 struct mlx5_ifc_pages_req_event_bits { 9424 u8 reserved_at_0[0x10]; 9425 u8 function_id[0x10]; 9426 9427 u8 num_pages[0x20]; 9428 9429 u8 reserved_at_40[0xa0]; 9430 }; 9431 9432 struct mlx5_ifc_eqe_bits { 9433 u8 reserved_at_0[0x8]; 9434 u8 event_type[0x8]; 9435 u8 reserved_at_10[0x8]; 9436 u8 event_sub_type[0x8]; 9437 9438 u8 reserved_at_20[0xe0]; 9439 9440 union mlx5_ifc_event_auto_bits event_data; 9441 9442 u8 reserved_at_1e0[0x10]; 9443 u8 signature[0x8]; 9444 u8 reserved_at_1f8[0x7]; 9445 u8 owner[0x1]; 9446 }; 9447 9448 enum { 9449 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7, 9450 }; 9451 9452 struct mlx5_ifc_cmd_queue_entry_bits { 9453 u8 type[0x8]; 9454 u8 reserved_at_8[0x18]; 9455 9456 u8 input_length[0x20]; 9457 9458 u8 input_mailbox_pointer_63_32[0x20]; 9459 9460 u8 input_mailbox_pointer_31_9[0x17]; 9461 u8 reserved_at_77[0x9]; 9462 9463 u8 command_input_inline_data[16][0x8]; 9464 9465 u8 command_output_inline_data[16][0x8]; 9466 9467 u8 output_mailbox_pointer_63_32[0x20]; 9468 9469 u8 output_mailbox_pointer_31_9[0x17]; 9470 u8 reserved_at_1b7[0x9]; 9471 9472 u8 output_length[0x20]; 9473 9474 u8 token[0x8]; 9475 u8 signature[0x8]; 9476 u8 reserved_at_1f0[0x8]; 9477 u8 status[0x7]; 9478 u8 ownership[0x1]; 9479 }; 9480 9481 struct mlx5_ifc_cmd_out_bits { 9482 u8 status[0x8]; 9483 u8 reserved_at_8[0x18]; 9484 9485 u8 syndrome[0x20]; 9486 9487 u8 command_output[0x20]; 9488 }; 9489 9490 struct mlx5_ifc_cmd_in_bits { 9491 u8 opcode[0x10]; 9492 u8 reserved_at_10[0x10]; 9493 9494 u8 reserved_at_20[0x10]; 9495 u8 op_mod[0x10]; 9496 9497 u8 command[][0x20]; 9498 }; 9499 9500 struct mlx5_ifc_cmd_if_box_bits { 9501 u8 mailbox_data[512][0x8]; 9502 9503 u8 reserved_at_1000[0x180]; 9504 9505 u8 next_pointer_63_32[0x20]; 9506 9507 u8 next_pointer_31_10[0x16]; 9508 u8 reserved_at_11b6[0xa]; 9509 9510 u8 block_number[0x20]; 9511 9512 u8 reserved_at_11e0[0x8]; 9513 u8 token[0x8]; 9514 u8 ctrl_signature[0x8]; 9515 u8 signature[0x8]; 9516 }; 9517 9518 struct mlx5_ifc_mtt_bits { 9519 u8 ptag_63_32[0x20]; 9520 9521 u8 ptag_31_8[0x18]; 9522 u8 reserved_at_38[0x6]; 9523 u8 wr_en[0x1]; 9524 u8 rd_en[0x1]; 9525 }; 9526 9527 struct mlx5_ifc_query_wol_rol_out_bits { 9528 u8 status[0x8]; 9529 u8 reserved_at_8[0x18]; 9530 9531 u8 syndrome[0x20]; 9532 9533 u8 reserved_at_40[0x10]; 9534 u8 rol_mode[0x8]; 9535 u8 wol_mode[0x8]; 9536 9537 u8 reserved_at_60[0x20]; 9538 }; 9539 9540 struct mlx5_ifc_query_wol_rol_in_bits { 9541 u8 opcode[0x10]; 9542 u8 reserved_at_10[0x10]; 9543 9544 u8 reserved_at_20[0x10]; 9545 u8 op_mod[0x10]; 9546 9547 u8 reserved_at_40[0x40]; 9548 }; 9549 9550 struct mlx5_ifc_set_wol_rol_out_bits { 9551 u8 status[0x8]; 9552 u8 reserved_at_8[0x18]; 9553 9554 u8 syndrome[0x20]; 9555 9556 u8 reserved_at_40[0x40]; 9557 }; 9558 9559 struct mlx5_ifc_set_wol_rol_in_bits { 9560 u8 opcode[0x10]; 9561 u8 reserved_at_10[0x10]; 9562 9563 u8 reserved_at_20[0x10]; 9564 u8 op_mod[0x10]; 9565 9566 u8 rol_mode_valid[0x1]; 9567 u8 wol_mode_valid[0x1]; 9568 u8 reserved_at_42[0xe]; 9569 u8 rol_mode[0x8]; 9570 u8 wol_mode[0x8]; 9571 9572 u8 reserved_at_60[0x20]; 9573 }; 9574 9575 enum { 9576 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0, 9577 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1, 9578 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2, 9579 }; 9580 9581 enum { 9582 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0, 9583 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1, 9584 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2, 9585 }; 9586 9587 enum { 9588 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR = 0x1, 9589 MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC = 0x7, 9590 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR = 0x8, 9591 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR = 0x9, 9592 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR = 0xa, 9593 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR = 0xb, 9594 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN = 0xc, 9595 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR = 0xd, 9596 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV = 0xe, 9597 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR = 0xf, 9598 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR = 0x10, 9599 }; 9600 9601 struct mlx5_ifc_initial_seg_bits { 9602 u8 fw_rev_minor[0x10]; 9603 u8 fw_rev_major[0x10]; 9604 9605 u8 cmd_interface_rev[0x10]; 9606 u8 fw_rev_subminor[0x10]; 9607 9608 u8 reserved_at_40[0x40]; 9609 9610 u8 cmdq_phy_addr_63_32[0x20]; 9611 9612 u8 cmdq_phy_addr_31_12[0x14]; 9613 u8 reserved_at_b4[0x2]; 9614 u8 nic_interface[0x2]; 9615 u8 log_cmdq_size[0x4]; 9616 u8 log_cmdq_stride[0x4]; 9617 9618 u8 command_doorbell_vector[0x20]; 9619 9620 u8 reserved_at_e0[0xf00]; 9621 9622 u8 initializing[0x1]; 9623 u8 reserved_at_fe1[0x4]; 9624 u8 nic_interface_supported[0x3]; 9625 u8 embedded_cpu[0x1]; 9626 u8 reserved_at_fe9[0x17]; 9627 9628 struct mlx5_ifc_health_buffer_bits health_buffer; 9629 9630 u8 no_dram_nic_offset[0x20]; 9631 9632 u8 reserved_at_1220[0x6e40]; 9633 9634 u8 reserved_at_8060[0x1f]; 9635 u8 clear_int[0x1]; 9636 9637 u8 health_syndrome[0x8]; 9638 u8 health_counter[0x18]; 9639 9640 u8 reserved_at_80a0[0x17fc0]; 9641 }; 9642 9643 struct mlx5_ifc_mtpps_reg_bits { 9644 u8 reserved_at_0[0xc]; 9645 u8 cap_number_of_pps_pins[0x4]; 9646 u8 reserved_at_10[0x4]; 9647 u8 cap_max_num_of_pps_in_pins[0x4]; 9648 u8 reserved_at_18[0x4]; 9649 u8 cap_max_num_of_pps_out_pins[0x4]; 9650 9651 u8 reserved_at_20[0x24]; 9652 u8 cap_pin_3_mode[0x4]; 9653 u8 reserved_at_48[0x4]; 9654 u8 cap_pin_2_mode[0x4]; 9655 u8 reserved_at_50[0x4]; 9656 u8 cap_pin_1_mode[0x4]; 9657 u8 reserved_at_58[0x4]; 9658 u8 cap_pin_0_mode[0x4]; 9659 9660 u8 reserved_at_60[0x4]; 9661 u8 cap_pin_7_mode[0x4]; 9662 u8 reserved_at_68[0x4]; 9663 u8 cap_pin_6_mode[0x4]; 9664 u8 reserved_at_70[0x4]; 9665 u8 cap_pin_5_mode[0x4]; 9666 u8 reserved_at_78[0x4]; 9667 u8 cap_pin_4_mode[0x4]; 9668 9669 u8 field_select[0x20]; 9670 u8 reserved_at_a0[0x60]; 9671 9672 u8 enable[0x1]; 9673 u8 reserved_at_101[0xb]; 9674 u8 pattern[0x4]; 9675 u8 reserved_at_110[0x4]; 9676 u8 pin_mode[0x4]; 9677 u8 pin[0x8]; 9678 9679 u8 reserved_at_120[0x20]; 9680 9681 u8 time_stamp[0x40]; 9682 9683 u8 out_pulse_duration[0x10]; 9684 u8 out_periodic_adjustment[0x10]; 9685 u8 enhanced_out_periodic_adjustment[0x20]; 9686 9687 u8 reserved_at_1c0[0x20]; 9688 }; 9689 9690 struct mlx5_ifc_mtppse_reg_bits { 9691 u8 reserved_at_0[0x18]; 9692 u8 pin[0x8]; 9693 u8 event_arm[0x1]; 9694 u8 reserved_at_21[0x1b]; 9695 u8 event_generation_mode[0x4]; 9696 u8 reserved_at_40[0x40]; 9697 }; 9698 9699 struct mlx5_ifc_mcqs_reg_bits { 9700 u8 last_index_flag[0x1]; 9701 u8 reserved_at_1[0x7]; 9702 u8 fw_device[0x8]; 9703 u8 component_index[0x10]; 9704 9705 u8 reserved_at_20[0x10]; 9706 u8 identifier[0x10]; 9707 9708 u8 reserved_at_40[0x17]; 9709 u8 component_status[0x5]; 9710 u8 component_update_state[0x4]; 9711 9712 u8 last_update_state_changer_type[0x4]; 9713 u8 last_update_state_changer_host_id[0x4]; 9714 u8 reserved_at_68[0x18]; 9715 }; 9716 9717 struct mlx5_ifc_mcqi_cap_bits { 9718 u8 supported_info_bitmask[0x20]; 9719 9720 u8 component_size[0x20]; 9721 9722 u8 max_component_size[0x20]; 9723 9724 u8 log_mcda_word_size[0x4]; 9725 u8 reserved_at_64[0xc]; 9726 u8 mcda_max_write_size[0x10]; 9727 9728 u8 rd_en[0x1]; 9729 u8 reserved_at_81[0x1]; 9730 u8 match_chip_id[0x1]; 9731 u8 match_psid[0x1]; 9732 u8 check_user_timestamp[0x1]; 9733 u8 match_base_guid_mac[0x1]; 9734 u8 reserved_at_86[0x1a]; 9735 }; 9736 9737 struct mlx5_ifc_mcqi_version_bits { 9738 u8 reserved_at_0[0x2]; 9739 u8 build_time_valid[0x1]; 9740 u8 user_defined_time_valid[0x1]; 9741 u8 reserved_at_4[0x14]; 9742 u8 version_string_length[0x8]; 9743 9744 u8 version[0x20]; 9745 9746 u8 build_time[0x40]; 9747 9748 u8 user_defined_time[0x40]; 9749 9750 u8 build_tool_version[0x20]; 9751 9752 u8 reserved_at_e0[0x20]; 9753 9754 u8 version_string[92][0x8]; 9755 }; 9756 9757 struct mlx5_ifc_mcqi_activation_method_bits { 9758 u8 pending_server_ac_power_cycle[0x1]; 9759 u8 pending_server_dc_power_cycle[0x1]; 9760 u8 pending_server_reboot[0x1]; 9761 u8 pending_fw_reset[0x1]; 9762 u8 auto_activate[0x1]; 9763 u8 all_hosts_sync[0x1]; 9764 u8 device_hw_reset[0x1]; 9765 u8 reserved_at_7[0x19]; 9766 }; 9767 9768 union mlx5_ifc_mcqi_reg_data_bits { 9769 struct mlx5_ifc_mcqi_cap_bits mcqi_caps; 9770 struct mlx5_ifc_mcqi_version_bits mcqi_version; 9771 struct mlx5_ifc_mcqi_activation_method_bits mcqi_activation_mathod; 9772 }; 9773 9774 struct mlx5_ifc_mcqi_reg_bits { 9775 u8 read_pending_component[0x1]; 9776 u8 reserved_at_1[0xf]; 9777 u8 component_index[0x10]; 9778 9779 u8 reserved_at_20[0x20]; 9780 9781 u8 reserved_at_40[0x1b]; 9782 u8 info_type[0x5]; 9783 9784 u8 info_size[0x20]; 9785 9786 u8 offset[0x20]; 9787 9788 u8 reserved_at_a0[0x10]; 9789 u8 data_size[0x10]; 9790 9791 union mlx5_ifc_mcqi_reg_data_bits data[]; 9792 }; 9793 9794 struct mlx5_ifc_mcc_reg_bits { 9795 u8 reserved_at_0[0x4]; 9796 u8 time_elapsed_since_last_cmd[0xc]; 9797 u8 reserved_at_10[0x8]; 9798 u8 instruction[0x8]; 9799 9800 u8 reserved_at_20[0x10]; 9801 u8 component_index[0x10]; 9802 9803 u8 reserved_at_40[0x8]; 9804 u8 update_handle[0x18]; 9805 9806 u8 handle_owner_type[0x4]; 9807 u8 handle_owner_host_id[0x4]; 9808 u8 reserved_at_68[0x1]; 9809 u8 control_progress[0x7]; 9810 u8 error_code[0x8]; 9811 u8 reserved_at_78[0x4]; 9812 u8 control_state[0x4]; 9813 9814 u8 component_size[0x20]; 9815 9816 u8 reserved_at_a0[0x60]; 9817 }; 9818 9819 struct mlx5_ifc_mcda_reg_bits { 9820 u8 reserved_at_0[0x8]; 9821 u8 update_handle[0x18]; 9822 9823 u8 offset[0x20]; 9824 9825 u8 reserved_at_40[0x10]; 9826 u8 size[0x10]; 9827 9828 u8 reserved_at_60[0x20]; 9829 9830 u8 data[][0x20]; 9831 }; 9832 9833 enum { 9834 MLX5_MFRL_REG_RESET_TYPE_FULL_CHIP = BIT(0), 9835 MLX5_MFRL_REG_RESET_TYPE_NET_PORT_ALIVE = BIT(1), 9836 }; 9837 9838 enum { 9839 MLX5_MFRL_REG_RESET_LEVEL0 = BIT(0), 9840 MLX5_MFRL_REG_RESET_LEVEL3 = BIT(3), 9841 MLX5_MFRL_REG_RESET_LEVEL6 = BIT(6), 9842 }; 9843 9844 struct mlx5_ifc_mfrl_reg_bits { 9845 u8 reserved_at_0[0x20]; 9846 9847 u8 reserved_at_20[0x2]; 9848 u8 pci_sync_for_fw_update_start[0x1]; 9849 u8 pci_sync_for_fw_update_resp[0x2]; 9850 u8 rst_type_sel[0x3]; 9851 u8 reserved_at_28[0x8]; 9852 u8 reset_type[0x8]; 9853 u8 reset_level[0x8]; 9854 }; 9855 9856 struct mlx5_ifc_mirc_reg_bits { 9857 u8 reserved_at_0[0x18]; 9858 u8 status_code[0x8]; 9859 9860 u8 reserved_at_20[0x20]; 9861 }; 9862 9863 union mlx5_ifc_ports_control_registers_document_bits { 9864 struct mlx5_ifc_bufferx_reg_bits bufferx_reg; 9865 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 9866 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 9867 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 9868 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 9869 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 9870 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 9871 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout; 9872 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout; 9873 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping; 9874 struct mlx5_ifc_pamp_reg_bits pamp_reg; 9875 struct mlx5_ifc_paos_reg_bits paos_reg; 9876 struct mlx5_ifc_pcap_reg_bits pcap_reg; 9877 struct mlx5_ifc_peir_reg_bits peir_reg; 9878 struct mlx5_ifc_pelc_reg_bits pelc_reg; 9879 struct mlx5_ifc_pfcc_reg_bits pfcc_reg; 9880 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 9881 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 9882 struct mlx5_ifc_pifr_reg_bits pifr_reg; 9883 struct mlx5_ifc_pipg_reg_bits pipg_reg; 9884 struct mlx5_ifc_plbf_reg_bits plbf_reg; 9885 struct mlx5_ifc_plib_reg_bits plib_reg; 9886 struct mlx5_ifc_plpc_reg_bits plpc_reg; 9887 struct mlx5_ifc_pmaos_reg_bits pmaos_reg; 9888 struct mlx5_ifc_pmlp_reg_bits pmlp_reg; 9889 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg; 9890 struct mlx5_ifc_pmpc_reg_bits pmpc_reg; 9891 struct mlx5_ifc_pmpe_reg_bits pmpe_reg; 9892 struct mlx5_ifc_pmpr_reg_bits pmpr_reg; 9893 struct mlx5_ifc_pmtu_reg_bits pmtu_reg; 9894 struct mlx5_ifc_ppad_reg_bits ppad_reg; 9895 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg; 9896 struct mlx5_ifc_mpein_reg_bits mpein_reg; 9897 struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg; 9898 struct mlx5_ifc_pplm_reg_bits pplm_reg; 9899 struct mlx5_ifc_pplr_reg_bits pplr_reg; 9900 struct mlx5_ifc_ppsc_reg_bits ppsc_reg; 9901 struct mlx5_ifc_pqdr_reg_bits pqdr_reg; 9902 struct mlx5_ifc_pspa_reg_bits pspa_reg; 9903 struct mlx5_ifc_ptas_reg_bits ptas_reg; 9904 struct mlx5_ifc_ptys_reg_bits ptys_reg; 9905 struct mlx5_ifc_mlcr_reg_bits mlcr_reg; 9906 struct mlx5_ifc_pude_reg_bits pude_reg; 9907 struct mlx5_ifc_pvlc_reg_bits pvlc_reg; 9908 struct mlx5_ifc_slrg_reg_bits slrg_reg; 9909 struct mlx5_ifc_sltp_reg_bits sltp_reg; 9910 struct mlx5_ifc_mtpps_reg_bits mtpps_reg; 9911 struct mlx5_ifc_mtppse_reg_bits mtppse_reg; 9912 struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg; 9913 struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits; 9914 struct mlx5_ifc_fpga_cap_bits fpga_cap_bits; 9915 struct mlx5_ifc_mcqi_reg_bits mcqi_reg; 9916 struct mlx5_ifc_mcc_reg_bits mcc_reg; 9917 struct mlx5_ifc_mcda_reg_bits mcda_reg; 9918 struct mlx5_ifc_mirc_reg_bits mirc_reg; 9919 struct mlx5_ifc_mfrl_reg_bits mfrl_reg; 9920 u8 reserved_at_0[0x60e0]; 9921 }; 9922 9923 union mlx5_ifc_debug_enhancements_document_bits { 9924 struct mlx5_ifc_health_buffer_bits health_buffer; 9925 u8 reserved_at_0[0x200]; 9926 }; 9927 9928 union mlx5_ifc_uplink_pci_interface_document_bits { 9929 struct mlx5_ifc_initial_seg_bits initial_seg; 9930 u8 reserved_at_0[0x20060]; 9931 }; 9932 9933 struct mlx5_ifc_set_flow_table_root_out_bits { 9934 u8 status[0x8]; 9935 u8 reserved_at_8[0x18]; 9936 9937 u8 syndrome[0x20]; 9938 9939 u8 reserved_at_40[0x40]; 9940 }; 9941 9942 struct mlx5_ifc_set_flow_table_root_in_bits { 9943 u8 opcode[0x10]; 9944 u8 reserved_at_10[0x10]; 9945 9946 u8 reserved_at_20[0x10]; 9947 u8 op_mod[0x10]; 9948 9949 u8 other_vport[0x1]; 9950 u8 reserved_at_41[0xf]; 9951 u8 vport_number[0x10]; 9952 9953 u8 reserved_at_60[0x20]; 9954 9955 u8 table_type[0x8]; 9956 u8 reserved_at_88[0x18]; 9957 9958 u8 reserved_at_a0[0x8]; 9959 u8 table_id[0x18]; 9960 9961 u8 reserved_at_c0[0x8]; 9962 u8 underlay_qpn[0x18]; 9963 u8 reserved_at_e0[0x120]; 9964 }; 9965 9966 enum { 9967 MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = (1UL << 0), 9968 MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15), 9969 }; 9970 9971 struct mlx5_ifc_modify_flow_table_out_bits { 9972 u8 status[0x8]; 9973 u8 reserved_at_8[0x18]; 9974 9975 u8 syndrome[0x20]; 9976 9977 u8 reserved_at_40[0x40]; 9978 }; 9979 9980 struct mlx5_ifc_modify_flow_table_in_bits { 9981 u8 opcode[0x10]; 9982 u8 reserved_at_10[0x10]; 9983 9984 u8 reserved_at_20[0x10]; 9985 u8 op_mod[0x10]; 9986 9987 u8 other_vport[0x1]; 9988 u8 reserved_at_41[0xf]; 9989 u8 vport_number[0x10]; 9990 9991 u8 reserved_at_60[0x10]; 9992 u8 modify_field_select[0x10]; 9993 9994 u8 table_type[0x8]; 9995 u8 reserved_at_88[0x18]; 9996 9997 u8 reserved_at_a0[0x8]; 9998 u8 table_id[0x18]; 9999 10000 struct mlx5_ifc_flow_table_context_bits flow_table_context; 10001 }; 10002 10003 struct mlx5_ifc_ets_tcn_config_reg_bits { 10004 u8 g[0x1]; 10005 u8 b[0x1]; 10006 u8 r[0x1]; 10007 u8 reserved_at_3[0x9]; 10008 u8 group[0x4]; 10009 u8 reserved_at_10[0x9]; 10010 u8 bw_allocation[0x7]; 10011 10012 u8 reserved_at_20[0xc]; 10013 u8 max_bw_units[0x4]; 10014 u8 reserved_at_30[0x8]; 10015 u8 max_bw_value[0x8]; 10016 }; 10017 10018 struct mlx5_ifc_ets_global_config_reg_bits { 10019 u8 reserved_at_0[0x2]; 10020 u8 r[0x1]; 10021 u8 reserved_at_3[0x1d]; 10022 10023 u8 reserved_at_20[0xc]; 10024 u8 max_bw_units[0x4]; 10025 u8 reserved_at_30[0x8]; 10026 u8 max_bw_value[0x8]; 10027 }; 10028 10029 struct mlx5_ifc_qetc_reg_bits { 10030 u8 reserved_at_0[0x8]; 10031 u8 port_number[0x8]; 10032 u8 reserved_at_10[0x30]; 10033 10034 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8]; 10035 struct mlx5_ifc_ets_global_config_reg_bits global_configuration; 10036 }; 10037 10038 struct mlx5_ifc_qpdpm_dscp_reg_bits { 10039 u8 e[0x1]; 10040 u8 reserved_at_01[0x0b]; 10041 u8 prio[0x04]; 10042 }; 10043 10044 struct mlx5_ifc_qpdpm_reg_bits { 10045 u8 reserved_at_0[0x8]; 10046 u8 local_port[0x8]; 10047 u8 reserved_at_10[0x10]; 10048 struct mlx5_ifc_qpdpm_dscp_reg_bits dscp[64]; 10049 }; 10050 10051 struct mlx5_ifc_qpts_reg_bits { 10052 u8 reserved_at_0[0x8]; 10053 u8 local_port[0x8]; 10054 u8 reserved_at_10[0x2d]; 10055 u8 trust_state[0x3]; 10056 }; 10057 10058 struct mlx5_ifc_pptb_reg_bits { 10059 u8 reserved_at_0[0x2]; 10060 u8 mm[0x2]; 10061 u8 reserved_at_4[0x4]; 10062 u8 local_port[0x8]; 10063 u8 reserved_at_10[0x6]; 10064 u8 cm[0x1]; 10065 u8 um[0x1]; 10066 u8 pm[0x8]; 10067 10068 u8 prio_x_buff[0x20]; 10069 10070 u8 pm_msb[0x8]; 10071 u8 reserved_at_48[0x10]; 10072 u8 ctrl_buff[0x4]; 10073 u8 untagged_buff[0x4]; 10074 }; 10075 10076 struct mlx5_ifc_sbcam_reg_bits { 10077 u8 reserved_at_0[0x8]; 10078 u8 feature_group[0x8]; 10079 u8 reserved_at_10[0x8]; 10080 u8 access_reg_group[0x8]; 10081 10082 u8 reserved_at_20[0x20]; 10083 10084 u8 sb_access_reg_cap_mask[4][0x20]; 10085 10086 u8 reserved_at_c0[0x80]; 10087 10088 u8 sb_feature_cap_mask[4][0x20]; 10089 10090 u8 reserved_at_1c0[0x40]; 10091 10092 u8 cap_total_buffer_size[0x20]; 10093 10094 u8 cap_cell_size[0x10]; 10095 u8 cap_max_pg_buffers[0x8]; 10096 u8 cap_num_pool_supported[0x8]; 10097 10098 u8 reserved_at_240[0x8]; 10099 u8 cap_sbsr_stat_size[0x8]; 10100 u8 cap_max_tclass_data[0x8]; 10101 u8 cap_max_cpu_ingress_tclass_sb[0x8]; 10102 }; 10103 10104 struct mlx5_ifc_pbmc_reg_bits { 10105 u8 reserved_at_0[0x8]; 10106 u8 local_port[0x8]; 10107 u8 reserved_at_10[0x10]; 10108 10109 u8 xoff_timer_value[0x10]; 10110 u8 xoff_refresh[0x10]; 10111 10112 u8 reserved_at_40[0x9]; 10113 u8 fullness_threshold[0x7]; 10114 u8 port_buffer_size[0x10]; 10115 10116 struct mlx5_ifc_bufferx_reg_bits buffer[10]; 10117 10118 u8 reserved_at_2e0[0x40]; 10119 }; 10120 10121 struct mlx5_ifc_qtct_reg_bits { 10122 u8 reserved_at_0[0x8]; 10123 u8 port_number[0x8]; 10124 u8 reserved_at_10[0xd]; 10125 u8 prio[0x3]; 10126 10127 u8 reserved_at_20[0x1d]; 10128 u8 tclass[0x3]; 10129 }; 10130 10131 struct mlx5_ifc_mcia_reg_bits { 10132 u8 l[0x1]; 10133 u8 reserved_at_1[0x7]; 10134 u8 module[0x8]; 10135 u8 reserved_at_10[0x8]; 10136 u8 status[0x8]; 10137 10138 u8 i2c_device_address[0x8]; 10139 u8 page_number[0x8]; 10140 u8 device_address[0x10]; 10141 10142 u8 reserved_at_40[0x10]; 10143 u8 size[0x10]; 10144 10145 u8 reserved_at_60[0x20]; 10146 10147 u8 dword_0[0x20]; 10148 u8 dword_1[0x20]; 10149 u8 dword_2[0x20]; 10150 u8 dword_3[0x20]; 10151 u8 dword_4[0x20]; 10152 u8 dword_5[0x20]; 10153 u8 dword_6[0x20]; 10154 u8 dword_7[0x20]; 10155 u8 dword_8[0x20]; 10156 u8 dword_9[0x20]; 10157 u8 dword_10[0x20]; 10158 u8 dword_11[0x20]; 10159 }; 10160 10161 struct mlx5_ifc_dcbx_param_bits { 10162 u8 dcbx_cee_cap[0x1]; 10163 u8 dcbx_ieee_cap[0x1]; 10164 u8 dcbx_standby_cap[0x1]; 10165 u8 reserved_at_3[0x5]; 10166 u8 port_number[0x8]; 10167 u8 reserved_at_10[0xa]; 10168 u8 max_application_table_size[6]; 10169 u8 reserved_at_20[0x15]; 10170 u8 version_oper[0x3]; 10171 u8 reserved_at_38[5]; 10172 u8 version_admin[0x3]; 10173 u8 willing_admin[0x1]; 10174 u8 reserved_at_41[0x3]; 10175 u8 pfc_cap_oper[0x4]; 10176 u8 reserved_at_48[0x4]; 10177 u8 pfc_cap_admin[0x4]; 10178 u8 reserved_at_50[0x4]; 10179 u8 num_of_tc_oper[0x4]; 10180 u8 reserved_at_58[0x4]; 10181 u8 num_of_tc_admin[0x4]; 10182 u8 remote_willing[0x1]; 10183 u8 reserved_at_61[3]; 10184 u8 remote_pfc_cap[4]; 10185 u8 reserved_at_68[0x14]; 10186 u8 remote_num_of_tc[0x4]; 10187 u8 reserved_at_80[0x18]; 10188 u8 error[0x8]; 10189 u8 reserved_at_a0[0x160]; 10190 }; 10191 10192 struct mlx5_ifc_lagc_bits { 10193 u8 reserved_at_0[0x1d]; 10194 u8 lag_state[0x3]; 10195 10196 u8 reserved_at_20[0x14]; 10197 u8 tx_remap_affinity_2[0x4]; 10198 u8 reserved_at_38[0x4]; 10199 u8 tx_remap_affinity_1[0x4]; 10200 }; 10201 10202 struct mlx5_ifc_create_lag_out_bits { 10203 u8 status[0x8]; 10204 u8 reserved_at_8[0x18]; 10205 10206 u8 syndrome[0x20]; 10207 10208 u8 reserved_at_40[0x40]; 10209 }; 10210 10211 struct mlx5_ifc_create_lag_in_bits { 10212 u8 opcode[0x10]; 10213 u8 reserved_at_10[0x10]; 10214 10215 u8 reserved_at_20[0x10]; 10216 u8 op_mod[0x10]; 10217 10218 struct mlx5_ifc_lagc_bits ctx; 10219 }; 10220 10221 struct mlx5_ifc_modify_lag_out_bits { 10222 u8 status[0x8]; 10223 u8 reserved_at_8[0x18]; 10224 10225 u8 syndrome[0x20]; 10226 10227 u8 reserved_at_40[0x40]; 10228 }; 10229 10230 struct mlx5_ifc_modify_lag_in_bits { 10231 u8 opcode[0x10]; 10232 u8 reserved_at_10[0x10]; 10233 10234 u8 reserved_at_20[0x10]; 10235 u8 op_mod[0x10]; 10236 10237 u8 reserved_at_40[0x20]; 10238 u8 field_select[0x20]; 10239 10240 struct mlx5_ifc_lagc_bits ctx; 10241 }; 10242 10243 struct mlx5_ifc_query_lag_out_bits { 10244 u8 status[0x8]; 10245 u8 reserved_at_8[0x18]; 10246 10247 u8 syndrome[0x20]; 10248 10249 struct mlx5_ifc_lagc_bits ctx; 10250 }; 10251 10252 struct mlx5_ifc_query_lag_in_bits { 10253 u8 opcode[0x10]; 10254 u8 reserved_at_10[0x10]; 10255 10256 u8 reserved_at_20[0x10]; 10257 u8 op_mod[0x10]; 10258 10259 u8 reserved_at_40[0x40]; 10260 }; 10261 10262 struct mlx5_ifc_destroy_lag_out_bits { 10263 u8 status[0x8]; 10264 u8 reserved_at_8[0x18]; 10265 10266 u8 syndrome[0x20]; 10267 10268 u8 reserved_at_40[0x40]; 10269 }; 10270 10271 struct mlx5_ifc_destroy_lag_in_bits { 10272 u8 opcode[0x10]; 10273 u8 reserved_at_10[0x10]; 10274 10275 u8 reserved_at_20[0x10]; 10276 u8 op_mod[0x10]; 10277 10278 u8 reserved_at_40[0x40]; 10279 }; 10280 10281 struct mlx5_ifc_create_vport_lag_out_bits { 10282 u8 status[0x8]; 10283 u8 reserved_at_8[0x18]; 10284 10285 u8 syndrome[0x20]; 10286 10287 u8 reserved_at_40[0x40]; 10288 }; 10289 10290 struct mlx5_ifc_create_vport_lag_in_bits { 10291 u8 opcode[0x10]; 10292 u8 reserved_at_10[0x10]; 10293 10294 u8 reserved_at_20[0x10]; 10295 u8 op_mod[0x10]; 10296 10297 u8 reserved_at_40[0x40]; 10298 }; 10299 10300 struct mlx5_ifc_destroy_vport_lag_out_bits { 10301 u8 status[0x8]; 10302 u8 reserved_at_8[0x18]; 10303 10304 u8 syndrome[0x20]; 10305 10306 u8 reserved_at_40[0x40]; 10307 }; 10308 10309 struct mlx5_ifc_destroy_vport_lag_in_bits { 10310 u8 opcode[0x10]; 10311 u8 reserved_at_10[0x10]; 10312 10313 u8 reserved_at_20[0x10]; 10314 u8 op_mod[0x10]; 10315 10316 u8 reserved_at_40[0x40]; 10317 }; 10318 10319 struct mlx5_ifc_alloc_memic_in_bits { 10320 u8 opcode[0x10]; 10321 u8 reserved_at_10[0x10]; 10322 10323 u8 reserved_at_20[0x10]; 10324 u8 op_mod[0x10]; 10325 10326 u8 reserved_at_30[0x20]; 10327 10328 u8 reserved_at_40[0x18]; 10329 u8 log_memic_addr_alignment[0x8]; 10330 10331 u8 range_start_addr[0x40]; 10332 10333 u8 range_size[0x20]; 10334 10335 u8 memic_size[0x20]; 10336 }; 10337 10338 struct mlx5_ifc_alloc_memic_out_bits { 10339 u8 status[0x8]; 10340 u8 reserved_at_8[0x18]; 10341 10342 u8 syndrome[0x20]; 10343 10344 u8 memic_start_addr[0x40]; 10345 }; 10346 10347 struct mlx5_ifc_dealloc_memic_in_bits { 10348 u8 opcode[0x10]; 10349 u8 reserved_at_10[0x10]; 10350 10351 u8 reserved_at_20[0x10]; 10352 u8 op_mod[0x10]; 10353 10354 u8 reserved_at_40[0x40]; 10355 10356 u8 memic_start_addr[0x40]; 10357 10358 u8 memic_size[0x20]; 10359 10360 u8 reserved_at_e0[0x20]; 10361 }; 10362 10363 struct mlx5_ifc_dealloc_memic_out_bits { 10364 u8 status[0x8]; 10365 u8 reserved_at_8[0x18]; 10366 10367 u8 syndrome[0x20]; 10368 10369 u8 reserved_at_40[0x40]; 10370 }; 10371 10372 struct mlx5_ifc_general_obj_in_cmd_hdr_bits { 10373 u8 opcode[0x10]; 10374 u8 uid[0x10]; 10375 10376 u8 vhca_tunnel_id[0x10]; 10377 u8 obj_type[0x10]; 10378 10379 u8 obj_id[0x20]; 10380 10381 u8 reserved_at_60[0x20]; 10382 }; 10383 10384 struct mlx5_ifc_general_obj_out_cmd_hdr_bits { 10385 u8 status[0x8]; 10386 u8 reserved_at_8[0x18]; 10387 10388 u8 syndrome[0x20]; 10389 10390 u8 obj_id[0x20]; 10391 10392 u8 reserved_at_60[0x20]; 10393 }; 10394 10395 struct mlx5_ifc_umem_bits { 10396 u8 reserved_at_0[0x80]; 10397 10398 u8 reserved_at_80[0x1b]; 10399 u8 log_page_size[0x5]; 10400 10401 u8 page_offset[0x20]; 10402 10403 u8 num_of_mtt[0x40]; 10404 10405 struct mlx5_ifc_mtt_bits mtt[]; 10406 }; 10407 10408 struct mlx5_ifc_uctx_bits { 10409 u8 cap[0x20]; 10410 10411 u8 reserved_at_20[0x160]; 10412 }; 10413 10414 struct mlx5_ifc_sw_icm_bits { 10415 u8 modify_field_select[0x40]; 10416 10417 u8 reserved_at_40[0x18]; 10418 u8 log_sw_icm_size[0x8]; 10419 10420 u8 reserved_at_60[0x20]; 10421 10422 u8 sw_icm_start_addr[0x40]; 10423 10424 u8 reserved_at_c0[0x140]; 10425 }; 10426 10427 struct mlx5_ifc_geneve_tlv_option_bits { 10428 u8 modify_field_select[0x40]; 10429 10430 u8 reserved_at_40[0x18]; 10431 u8 geneve_option_fte_index[0x8]; 10432 10433 u8 option_class[0x10]; 10434 u8 option_type[0x8]; 10435 u8 reserved_at_78[0x3]; 10436 u8 option_data_length[0x5]; 10437 10438 u8 reserved_at_80[0x180]; 10439 }; 10440 10441 struct mlx5_ifc_create_umem_in_bits { 10442 u8 opcode[0x10]; 10443 u8 uid[0x10]; 10444 10445 u8 reserved_at_20[0x10]; 10446 u8 op_mod[0x10]; 10447 10448 u8 reserved_at_40[0x40]; 10449 10450 struct mlx5_ifc_umem_bits umem; 10451 }; 10452 10453 struct mlx5_ifc_create_umem_out_bits { 10454 u8 status[0x8]; 10455 u8 reserved_at_8[0x18]; 10456 10457 u8 syndrome[0x20]; 10458 10459 u8 reserved_at_40[0x8]; 10460 u8 umem_id[0x18]; 10461 10462 u8 reserved_at_60[0x20]; 10463 }; 10464 10465 struct mlx5_ifc_destroy_umem_in_bits { 10466 u8 opcode[0x10]; 10467 u8 uid[0x10]; 10468 10469 u8 reserved_at_20[0x10]; 10470 u8 op_mod[0x10]; 10471 10472 u8 reserved_at_40[0x8]; 10473 u8 umem_id[0x18]; 10474 10475 u8 reserved_at_60[0x20]; 10476 }; 10477 10478 struct mlx5_ifc_destroy_umem_out_bits { 10479 u8 status[0x8]; 10480 u8 reserved_at_8[0x18]; 10481 10482 u8 syndrome[0x20]; 10483 10484 u8 reserved_at_40[0x40]; 10485 }; 10486 10487 struct mlx5_ifc_create_uctx_in_bits { 10488 u8 opcode[0x10]; 10489 u8 reserved_at_10[0x10]; 10490 10491 u8 reserved_at_20[0x10]; 10492 u8 op_mod[0x10]; 10493 10494 u8 reserved_at_40[0x40]; 10495 10496 struct mlx5_ifc_uctx_bits uctx; 10497 }; 10498 10499 struct mlx5_ifc_create_uctx_out_bits { 10500 u8 status[0x8]; 10501 u8 reserved_at_8[0x18]; 10502 10503 u8 syndrome[0x20]; 10504 10505 u8 reserved_at_40[0x10]; 10506 u8 uid[0x10]; 10507 10508 u8 reserved_at_60[0x20]; 10509 }; 10510 10511 struct mlx5_ifc_destroy_uctx_in_bits { 10512 u8 opcode[0x10]; 10513 u8 reserved_at_10[0x10]; 10514 10515 u8 reserved_at_20[0x10]; 10516 u8 op_mod[0x10]; 10517 10518 u8 reserved_at_40[0x10]; 10519 u8 uid[0x10]; 10520 10521 u8 reserved_at_60[0x20]; 10522 }; 10523 10524 struct mlx5_ifc_destroy_uctx_out_bits { 10525 u8 status[0x8]; 10526 u8 reserved_at_8[0x18]; 10527 10528 u8 syndrome[0x20]; 10529 10530 u8 reserved_at_40[0x40]; 10531 }; 10532 10533 struct mlx5_ifc_create_sw_icm_in_bits { 10534 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 10535 struct mlx5_ifc_sw_icm_bits sw_icm; 10536 }; 10537 10538 struct mlx5_ifc_create_geneve_tlv_option_in_bits { 10539 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 10540 struct mlx5_ifc_geneve_tlv_option_bits geneve_tlv_opt; 10541 }; 10542 10543 struct mlx5_ifc_mtrc_string_db_param_bits { 10544 u8 string_db_base_address[0x20]; 10545 10546 u8 reserved_at_20[0x8]; 10547 u8 string_db_size[0x18]; 10548 }; 10549 10550 struct mlx5_ifc_mtrc_cap_bits { 10551 u8 trace_owner[0x1]; 10552 u8 trace_to_memory[0x1]; 10553 u8 reserved_at_2[0x4]; 10554 u8 trc_ver[0x2]; 10555 u8 reserved_at_8[0x14]; 10556 u8 num_string_db[0x4]; 10557 10558 u8 first_string_trace[0x8]; 10559 u8 num_string_trace[0x8]; 10560 u8 reserved_at_30[0x28]; 10561 10562 u8 log_max_trace_buffer_size[0x8]; 10563 10564 u8 reserved_at_60[0x20]; 10565 10566 struct mlx5_ifc_mtrc_string_db_param_bits string_db_param[8]; 10567 10568 u8 reserved_at_280[0x180]; 10569 }; 10570 10571 struct mlx5_ifc_mtrc_conf_bits { 10572 u8 reserved_at_0[0x1c]; 10573 u8 trace_mode[0x4]; 10574 u8 reserved_at_20[0x18]; 10575 u8 log_trace_buffer_size[0x8]; 10576 u8 trace_mkey[0x20]; 10577 u8 reserved_at_60[0x3a0]; 10578 }; 10579 10580 struct mlx5_ifc_mtrc_stdb_bits { 10581 u8 string_db_index[0x4]; 10582 u8 reserved_at_4[0x4]; 10583 u8 read_size[0x18]; 10584 u8 start_offset[0x20]; 10585 u8 string_db_data[]; 10586 }; 10587 10588 struct mlx5_ifc_mtrc_ctrl_bits { 10589 u8 trace_status[0x2]; 10590 u8 reserved_at_2[0x2]; 10591 u8 arm_event[0x1]; 10592 u8 reserved_at_5[0xb]; 10593 u8 modify_field_select[0x10]; 10594 u8 reserved_at_20[0x2b]; 10595 u8 current_timestamp52_32[0x15]; 10596 u8 current_timestamp31_0[0x20]; 10597 u8 reserved_at_80[0x180]; 10598 }; 10599 10600 struct mlx5_ifc_host_params_context_bits { 10601 u8 host_number[0x8]; 10602 u8 reserved_at_8[0x7]; 10603 u8 host_pf_disabled[0x1]; 10604 u8 host_num_of_vfs[0x10]; 10605 10606 u8 host_total_vfs[0x10]; 10607 u8 host_pci_bus[0x10]; 10608 10609 u8 reserved_at_40[0x10]; 10610 u8 host_pci_device[0x10]; 10611 10612 u8 reserved_at_60[0x10]; 10613 u8 host_pci_function[0x10]; 10614 10615 u8 reserved_at_80[0x180]; 10616 }; 10617 10618 struct mlx5_ifc_query_esw_functions_in_bits { 10619 u8 opcode[0x10]; 10620 u8 reserved_at_10[0x10]; 10621 10622 u8 reserved_at_20[0x10]; 10623 u8 op_mod[0x10]; 10624 10625 u8 reserved_at_40[0x40]; 10626 }; 10627 10628 struct mlx5_ifc_query_esw_functions_out_bits { 10629 u8 status[0x8]; 10630 u8 reserved_at_8[0x18]; 10631 10632 u8 syndrome[0x20]; 10633 10634 u8 reserved_at_40[0x40]; 10635 10636 struct mlx5_ifc_host_params_context_bits host_params_context; 10637 10638 u8 reserved_at_280[0x180]; 10639 u8 host_sf_enable[][0x40]; 10640 }; 10641 10642 struct mlx5_ifc_sf_partition_bits { 10643 u8 reserved_at_0[0x10]; 10644 u8 log_num_sf[0x8]; 10645 u8 log_sf_bar_size[0x8]; 10646 }; 10647 10648 struct mlx5_ifc_query_sf_partitions_out_bits { 10649 u8 status[0x8]; 10650 u8 reserved_at_8[0x18]; 10651 10652 u8 syndrome[0x20]; 10653 10654 u8 reserved_at_40[0x18]; 10655 u8 num_sf_partitions[0x8]; 10656 10657 u8 reserved_at_60[0x20]; 10658 10659 struct mlx5_ifc_sf_partition_bits sf_partition[]; 10660 }; 10661 10662 struct mlx5_ifc_query_sf_partitions_in_bits { 10663 u8 opcode[0x10]; 10664 u8 reserved_at_10[0x10]; 10665 10666 u8 reserved_at_20[0x10]; 10667 u8 op_mod[0x10]; 10668 10669 u8 reserved_at_40[0x40]; 10670 }; 10671 10672 struct mlx5_ifc_dealloc_sf_out_bits { 10673 u8 status[0x8]; 10674 u8 reserved_at_8[0x18]; 10675 10676 u8 syndrome[0x20]; 10677 10678 u8 reserved_at_40[0x40]; 10679 }; 10680 10681 struct mlx5_ifc_dealloc_sf_in_bits { 10682 u8 opcode[0x10]; 10683 u8 reserved_at_10[0x10]; 10684 10685 u8 reserved_at_20[0x10]; 10686 u8 op_mod[0x10]; 10687 10688 u8 reserved_at_40[0x10]; 10689 u8 function_id[0x10]; 10690 10691 u8 reserved_at_60[0x20]; 10692 }; 10693 10694 struct mlx5_ifc_alloc_sf_out_bits { 10695 u8 status[0x8]; 10696 u8 reserved_at_8[0x18]; 10697 10698 u8 syndrome[0x20]; 10699 10700 u8 reserved_at_40[0x40]; 10701 }; 10702 10703 struct mlx5_ifc_alloc_sf_in_bits { 10704 u8 opcode[0x10]; 10705 u8 reserved_at_10[0x10]; 10706 10707 u8 reserved_at_20[0x10]; 10708 u8 op_mod[0x10]; 10709 10710 u8 reserved_at_40[0x10]; 10711 u8 function_id[0x10]; 10712 10713 u8 reserved_at_60[0x20]; 10714 }; 10715 10716 struct mlx5_ifc_affiliated_event_header_bits { 10717 u8 reserved_at_0[0x10]; 10718 u8 obj_type[0x10]; 10719 10720 u8 obj_id[0x20]; 10721 }; 10722 10723 enum { 10724 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = BIT_ULL(0xc), 10725 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_IPSEC = BIT_ULL(0x13), 10726 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_SAMPLER = BIT_ULL(0x20), 10727 }; 10728 10729 enum { 10730 MLX5_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = 0xc, 10731 MLX5_GENERAL_OBJECT_TYPES_IPSEC = 0x13, 10732 MLX5_GENERAL_OBJECT_TYPES_SAMPLER = 0x20, 10733 }; 10734 10735 enum { 10736 MLX5_IPSEC_OBJECT_ICV_LEN_16B, 10737 MLX5_IPSEC_OBJECT_ICV_LEN_12B, 10738 MLX5_IPSEC_OBJECT_ICV_LEN_8B, 10739 }; 10740 10741 struct mlx5_ifc_ipsec_obj_bits { 10742 u8 modify_field_select[0x40]; 10743 u8 full_offload[0x1]; 10744 u8 reserved_at_41[0x1]; 10745 u8 esn_en[0x1]; 10746 u8 esn_overlap[0x1]; 10747 u8 reserved_at_44[0x2]; 10748 u8 icv_length[0x2]; 10749 u8 reserved_at_48[0x4]; 10750 u8 aso_return_reg[0x4]; 10751 u8 reserved_at_50[0x10]; 10752 10753 u8 esn_msb[0x20]; 10754 10755 u8 reserved_at_80[0x8]; 10756 u8 dekn[0x18]; 10757 10758 u8 salt[0x20]; 10759 10760 u8 implicit_iv[0x40]; 10761 10762 u8 reserved_at_100[0x700]; 10763 }; 10764 10765 struct mlx5_ifc_create_ipsec_obj_in_bits { 10766 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 10767 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 10768 }; 10769 10770 enum { 10771 MLX5_MODIFY_IPSEC_BITMASK_ESN_OVERLAP = BIT(0), 10772 MLX5_MODIFY_IPSEC_BITMASK_ESN_MSB = BIT(1), 10773 }; 10774 10775 struct mlx5_ifc_query_ipsec_obj_out_bits { 10776 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 10777 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 10778 }; 10779 10780 struct mlx5_ifc_modify_ipsec_obj_in_bits { 10781 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 10782 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 10783 }; 10784 10785 struct mlx5_ifc_encryption_key_obj_bits { 10786 u8 modify_field_select[0x40]; 10787 10788 u8 reserved_at_40[0x14]; 10789 u8 key_size[0x4]; 10790 u8 reserved_at_58[0x4]; 10791 u8 key_type[0x4]; 10792 10793 u8 reserved_at_60[0x8]; 10794 u8 pd[0x18]; 10795 10796 u8 reserved_at_80[0x180]; 10797 u8 key[8][0x20]; 10798 10799 u8 reserved_at_300[0x500]; 10800 }; 10801 10802 struct mlx5_ifc_create_encryption_key_in_bits { 10803 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 10804 struct mlx5_ifc_encryption_key_obj_bits encryption_key_object; 10805 }; 10806 10807 struct mlx5_ifc_sampler_obj_bits { 10808 u8 modify_field_select[0x40]; 10809 10810 u8 table_type[0x8]; 10811 u8 level[0x8]; 10812 u8 reserved_at_50[0xf]; 10813 u8 ignore_flow_level[0x1]; 10814 10815 u8 sample_ratio[0x20]; 10816 10817 u8 reserved_at_80[0x8]; 10818 u8 sample_table_id[0x18]; 10819 10820 u8 reserved_at_a0[0x8]; 10821 u8 default_table_id[0x18]; 10822 10823 u8 sw_steering_icm_address_rx[0x40]; 10824 u8 sw_steering_icm_address_tx[0x40]; 10825 10826 u8 reserved_at_140[0xa0]; 10827 }; 10828 10829 struct mlx5_ifc_create_sampler_obj_in_bits { 10830 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 10831 struct mlx5_ifc_sampler_obj_bits sampler_object; 10832 }; 10833 10834 enum { 10835 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_128 = 0x0, 10836 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_256 = 0x1, 10837 }; 10838 10839 enum { 10840 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_TYPE_TLS = 0x1, 10841 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_TYPE_IPSEC = 0x2, 10842 }; 10843 10844 struct mlx5_ifc_tls_static_params_bits { 10845 u8 const_2[0x2]; 10846 u8 tls_version[0x4]; 10847 u8 const_1[0x2]; 10848 u8 reserved_at_8[0x14]; 10849 u8 encryption_standard[0x4]; 10850 10851 u8 reserved_at_20[0x20]; 10852 10853 u8 initial_record_number[0x40]; 10854 10855 u8 resync_tcp_sn[0x20]; 10856 10857 u8 gcm_iv[0x20]; 10858 10859 u8 implicit_iv[0x40]; 10860 10861 u8 reserved_at_100[0x8]; 10862 u8 dek_index[0x18]; 10863 10864 u8 reserved_at_120[0xe0]; 10865 }; 10866 10867 struct mlx5_ifc_tls_progress_params_bits { 10868 u8 next_record_tcp_sn[0x20]; 10869 10870 u8 hw_resync_tcp_sn[0x20]; 10871 10872 u8 record_tracker_state[0x2]; 10873 u8 auth_state[0x2]; 10874 u8 reserved_at_44[0x4]; 10875 u8 hw_offset_record_number[0x18]; 10876 }; 10877 10878 enum { 10879 MLX5_MTT_PERM_READ = 1 << 0, 10880 MLX5_MTT_PERM_WRITE = 1 << 1, 10881 MLX5_MTT_PERM_RW = MLX5_MTT_PERM_READ | MLX5_MTT_PERM_WRITE, 10882 }; 10883 10884 #endif /* MLX5_IFC_H */ 10885