1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 #ifndef MLX5_IFC_H 33 #define MLX5_IFC_H 34 35 #include "mlx5_ifc_fpga.h" 36 37 enum { 38 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0, 39 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1, 40 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2, 41 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3, 42 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13, 43 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14, 44 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c, 45 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d, 46 MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4, 47 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5, 48 MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED = 0x7, 49 MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT = 0xc, 50 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10, 51 MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR = 0x11, 52 MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR = 0x12, 53 MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR = 0x8, 54 MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE = 0x9, 55 MLX5_EVENT_TYPE_CODING_GPIO_EVENT = 0x15, 56 MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19, 57 MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a, 58 MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT = 0x1b, 59 MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT = 0x1f, 60 MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa, 61 MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb, 62 MLX5_EVENT_TYPE_CODING_FPGA_ERROR = 0x20, 63 MLX5_EVENT_TYPE_CODING_FPGA_QP_ERROR = 0x21 64 }; 65 66 enum { 67 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0, 68 MLX5_SET_HCA_CAP_OP_MOD_ODP = 0x2, 69 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3, 70 MLX5_SET_HCA_CAP_OP_MOD_ROCE = 0x4, 71 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE2 = 0x20, 72 MLX5_SET_HCA_CAP_OP_MODE_PORT_SELECTION = 0x25, 73 }; 74 75 enum { 76 MLX5_SHARED_RESOURCE_UID = 0xffff, 77 }; 78 79 enum { 80 MLX5_OBJ_TYPE_SW_ICM = 0x0008, 81 }; 82 83 enum { 84 MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM = (1ULL << MLX5_OBJ_TYPE_SW_ICM), 85 MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT = (1ULL << 11), 86 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q = (1ULL << 13), 87 MLX5_GENERAL_OBJ_TYPES_CAP_MACSEC_OFFLOAD = (1ULL << 39), 88 }; 89 90 enum { 91 MLX5_OBJ_TYPE_GENEVE_TLV_OPT = 0x000b, 92 MLX5_OBJ_TYPE_VIRTIO_NET_Q = 0x000d, 93 MLX5_OBJ_TYPE_VIRTIO_Q_COUNTERS = 0x001c, 94 MLX5_OBJ_TYPE_MATCH_DEFINER = 0x0018, 95 MLX5_OBJ_TYPE_PAGE_TRACK = 0x46, 96 MLX5_OBJ_TYPE_MKEY = 0xff01, 97 MLX5_OBJ_TYPE_QP = 0xff02, 98 MLX5_OBJ_TYPE_PSV = 0xff03, 99 MLX5_OBJ_TYPE_RMP = 0xff04, 100 MLX5_OBJ_TYPE_XRC_SRQ = 0xff05, 101 MLX5_OBJ_TYPE_RQ = 0xff06, 102 MLX5_OBJ_TYPE_SQ = 0xff07, 103 MLX5_OBJ_TYPE_TIR = 0xff08, 104 MLX5_OBJ_TYPE_TIS = 0xff09, 105 MLX5_OBJ_TYPE_DCT = 0xff0a, 106 MLX5_OBJ_TYPE_XRQ = 0xff0b, 107 MLX5_OBJ_TYPE_RQT = 0xff0e, 108 MLX5_OBJ_TYPE_FLOW_COUNTER = 0xff0f, 109 MLX5_OBJ_TYPE_CQ = 0xff10, 110 }; 111 112 enum { 113 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100, 114 MLX5_CMD_OP_QUERY_ADAPTER = 0x101, 115 MLX5_CMD_OP_INIT_HCA = 0x102, 116 MLX5_CMD_OP_TEARDOWN_HCA = 0x103, 117 MLX5_CMD_OP_ENABLE_HCA = 0x104, 118 MLX5_CMD_OP_DISABLE_HCA = 0x105, 119 MLX5_CMD_OP_QUERY_PAGES = 0x107, 120 MLX5_CMD_OP_MANAGE_PAGES = 0x108, 121 MLX5_CMD_OP_SET_HCA_CAP = 0x109, 122 MLX5_CMD_OP_QUERY_ISSI = 0x10a, 123 MLX5_CMD_OP_SET_ISSI = 0x10b, 124 MLX5_CMD_OP_SET_DRIVER_VERSION = 0x10d, 125 MLX5_CMD_OP_QUERY_SF_PARTITION = 0x111, 126 MLX5_CMD_OP_ALLOC_SF = 0x113, 127 MLX5_CMD_OP_DEALLOC_SF = 0x114, 128 MLX5_CMD_OP_SUSPEND_VHCA = 0x115, 129 MLX5_CMD_OP_RESUME_VHCA = 0x116, 130 MLX5_CMD_OP_QUERY_VHCA_MIGRATION_STATE = 0x117, 131 MLX5_CMD_OP_SAVE_VHCA_STATE = 0x118, 132 MLX5_CMD_OP_LOAD_VHCA_STATE = 0x119, 133 MLX5_CMD_OP_CREATE_MKEY = 0x200, 134 MLX5_CMD_OP_QUERY_MKEY = 0x201, 135 MLX5_CMD_OP_DESTROY_MKEY = 0x202, 136 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203, 137 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204, 138 MLX5_CMD_OP_ALLOC_MEMIC = 0x205, 139 MLX5_CMD_OP_DEALLOC_MEMIC = 0x206, 140 MLX5_CMD_OP_MODIFY_MEMIC = 0x207, 141 MLX5_CMD_OP_CREATE_EQ = 0x301, 142 MLX5_CMD_OP_DESTROY_EQ = 0x302, 143 MLX5_CMD_OP_QUERY_EQ = 0x303, 144 MLX5_CMD_OP_GEN_EQE = 0x304, 145 MLX5_CMD_OP_CREATE_CQ = 0x400, 146 MLX5_CMD_OP_DESTROY_CQ = 0x401, 147 MLX5_CMD_OP_QUERY_CQ = 0x402, 148 MLX5_CMD_OP_MODIFY_CQ = 0x403, 149 MLX5_CMD_OP_CREATE_QP = 0x500, 150 MLX5_CMD_OP_DESTROY_QP = 0x501, 151 MLX5_CMD_OP_RST2INIT_QP = 0x502, 152 MLX5_CMD_OP_INIT2RTR_QP = 0x503, 153 MLX5_CMD_OP_RTR2RTS_QP = 0x504, 154 MLX5_CMD_OP_RTS2RTS_QP = 0x505, 155 MLX5_CMD_OP_SQERR2RTS_QP = 0x506, 156 MLX5_CMD_OP_2ERR_QP = 0x507, 157 MLX5_CMD_OP_2RST_QP = 0x50a, 158 MLX5_CMD_OP_QUERY_QP = 0x50b, 159 MLX5_CMD_OP_SQD_RTS_QP = 0x50c, 160 MLX5_CMD_OP_INIT2INIT_QP = 0x50e, 161 MLX5_CMD_OP_CREATE_PSV = 0x600, 162 MLX5_CMD_OP_DESTROY_PSV = 0x601, 163 MLX5_CMD_OP_CREATE_SRQ = 0x700, 164 MLX5_CMD_OP_DESTROY_SRQ = 0x701, 165 MLX5_CMD_OP_QUERY_SRQ = 0x702, 166 MLX5_CMD_OP_ARM_RQ = 0x703, 167 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705, 168 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706, 169 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707, 170 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708, 171 MLX5_CMD_OP_CREATE_DCT = 0x710, 172 MLX5_CMD_OP_DESTROY_DCT = 0x711, 173 MLX5_CMD_OP_DRAIN_DCT = 0x712, 174 MLX5_CMD_OP_QUERY_DCT = 0x713, 175 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714, 176 MLX5_CMD_OP_CREATE_XRQ = 0x717, 177 MLX5_CMD_OP_DESTROY_XRQ = 0x718, 178 MLX5_CMD_OP_QUERY_XRQ = 0x719, 179 MLX5_CMD_OP_ARM_XRQ = 0x71a, 180 MLX5_CMD_OP_QUERY_XRQ_DC_PARAMS_ENTRY = 0x725, 181 MLX5_CMD_OP_SET_XRQ_DC_PARAMS_ENTRY = 0x726, 182 MLX5_CMD_OP_QUERY_XRQ_ERROR_PARAMS = 0x727, 183 MLX5_CMD_OP_RELEASE_XRQ_ERROR = 0x729, 184 MLX5_CMD_OP_MODIFY_XRQ = 0x72a, 185 MLX5_CMD_OP_QUERY_ESW_FUNCTIONS = 0x740, 186 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750, 187 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751, 188 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752, 189 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753, 190 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754, 191 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755, 192 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760, 193 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761, 194 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762, 195 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763, 196 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764, 197 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765, 198 MLX5_CMD_OP_QUERY_VNIC_ENV = 0x76f, 199 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770, 200 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771, 201 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772, 202 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773, 203 MLX5_CMD_OP_SET_MONITOR_COUNTER = 0x774, 204 MLX5_CMD_OP_ARM_MONITOR_COUNTER = 0x775, 205 MLX5_CMD_OP_SET_PP_RATE_LIMIT = 0x780, 206 MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781, 207 MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT = 0x782, 208 MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT = 0x783, 209 MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT = 0x784, 210 MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT = 0x785, 211 MLX5_CMD_OP_CREATE_QOS_PARA_VPORT = 0x786, 212 MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT = 0x787, 213 MLX5_CMD_OP_ALLOC_PD = 0x800, 214 MLX5_CMD_OP_DEALLOC_PD = 0x801, 215 MLX5_CMD_OP_ALLOC_UAR = 0x802, 216 MLX5_CMD_OP_DEALLOC_UAR = 0x803, 217 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804, 218 MLX5_CMD_OP_ACCESS_REG = 0x805, 219 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806, 220 MLX5_CMD_OP_DETACH_FROM_MCG = 0x807, 221 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a, 222 MLX5_CMD_OP_MAD_IFC = 0x50d, 223 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b, 224 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c, 225 MLX5_CMD_OP_NOP = 0x80d, 226 MLX5_CMD_OP_ALLOC_XRCD = 0x80e, 227 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f, 228 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816, 229 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817, 230 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822, 231 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823, 232 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824, 233 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825, 234 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826, 235 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827, 236 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828, 237 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829, 238 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a, 239 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b, 240 MLX5_CMD_OP_SET_WOL_ROL = 0x830, 241 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831, 242 MLX5_CMD_OP_CREATE_LAG = 0x840, 243 MLX5_CMD_OP_MODIFY_LAG = 0x841, 244 MLX5_CMD_OP_QUERY_LAG = 0x842, 245 MLX5_CMD_OP_DESTROY_LAG = 0x843, 246 MLX5_CMD_OP_CREATE_VPORT_LAG = 0x844, 247 MLX5_CMD_OP_DESTROY_VPORT_LAG = 0x845, 248 MLX5_CMD_OP_CREATE_TIR = 0x900, 249 MLX5_CMD_OP_MODIFY_TIR = 0x901, 250 MLX5_CMD_OP_DESTROY_TIR = 0x902, 251 MLX5_CMD_OP_QUERY_TIR = 0x903, 252 MLX5_CMD_OP_CREATE_SQ = 0x904, 253 MLX5_CMD_OP_MODIFY_SQ = 0x905, 254 MLX5_CMD_OP_DESTROY_SQ = 0x906, 255 MLX5_CMD_OP_QUERY_SQ = 0x907, 256 MLX5_CMD_OP_CREATE_RQ = 0x908, 257 MLX5_CMD_OP_MODIFY_RQ = 0x909, 258 MLX5_CMD_OP_SET_DELAY_DROP_PARAMS = 0x910, 259 MLX5_CMD_OP_DESTROY_RQ = 0x90a, 260 MLX5_CMD_OP_QUERY_RQ = 0x90b, 261 MLX5_CMD_OP_CREATE_RMP = 0x90c, 262 MLX5_CMD_OP_MODIFY_RMP = 0x90d, 263 MLX5_CMD_OP_DESTROY_RMP = 0x90e, 264 MLX5_CMD_OP_QUERY_RMP = 0x90f, 265 MLX5_CMD_OP_CREATE_TIS = 0x912, 266 MLX5_CMD_OP_MODIFY_TIS = 0x913, 267 MLX5_CMD_OP_DESTROY_TIS = 0x914, 268 MLX5_CMD_OP_QUERY_TIS = 0x915, 269 MLX5_CMD_OP_CREATE_RQT = 0x916, 270 MLX5_CMD_OP_MODIFY_RQT = 0x917, 271 MLX5_CMD_OP_DESTROY_RQT = 0x918, 272 MLX5_CMD_OP_QUERY_RQT = 0x919, 273 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f, 274 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930, 275 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931, 276 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932, 277 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933, 278 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934, 279 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935, 280 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936, 281 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937, 282 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938, 283 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939, 284 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a, 285 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b, 286 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c, 287 MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT = 0x93d, 288 MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT = 0x93e, 289 MLX5_CMD_OP_QUERY_PACKET_REFORMAT_CONTEXT = 0x93f, 290 MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT = 0x940, 291 MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941, 292 MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT = 0x942, 293 MLX5_CMD_OP_FPGA_CREATE_QP = 0x960, 294 MLX5_CMD_OP_FPGA_MODIFY_QP = 0x961, 295 MLX5_CMD_OP_FPGA_QUERY_QP = 0x962, 296 MLX5_CMD_OP_FPGA_DESTROY_QP = 0x963, 297 MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS = 0x964, 298 MLX5_CMD_OP_CREATE_GENERAL_OBJECT = 0xa00, 299 MLX5_CMD_OP_MODIFY_GENERAL_OBJECT = 0xa01, 300 MLX5_CMD_OP_QUERY_GENERAL_OBJECT = 0xa02, 301 MLX5_CMD_OP_DESTROY_GENERAL_OBJECT = 0xa03, 302 MLX5_CMD_OP_CREATE_UCTX = 0xa04, 303 MLX5_CMD_OP_DESTROY_UCTX = 0xa06, 304 MLX5_CMD_OP_CREATE_UMEM = 0xa08, 305 MLX5_CMD_OP_DESTROY_UMEM = 0xa0a, 306 MLX5_CMD_OP_SYNC_STEERING = 0xb00, 307 MLX5_CMD_OP_QUERY_VHCA_STATE = 0xb0d, 308 MLX5_CMD_OP_MODIFY_VHCA_STATE = 0xb0e, 309 MLX5_CMD_OP_MAX 310 }; 311 312 /* Valid range for general commands that don't work over an object */ 313 enum { 314 MLX5_CMD_OP_GENERAL_START = 0xb00, 315 MLX5_CMD_OP_GENERAL_END = 0xd00, 316 }; 317 318 struct mlx5_ifc_flow_table_fields_supported_bits { 319 u8 outer_dmac[0x1]; 320 u8 outer_smac[0x1]; 321 u8 outer_ether_type[0x1]; 322 u8 outer_ip_version[0x1]; 323 u8 outer_first_prio[0x1]; 324 u8 outer_first_cfi[0x1]; 325 u8 outer_first_vid[0x1]; 326 u8 outer_ipv4_ttl[0x1]; 327 u8 outer_second_prio[0x1]; 328 u8 outer_second_cfi[0x1]; 329 u8 outer_second_vid[0x1]; 330 u8 reserved_at_b[0x1]; 331 u8 outer_sip[0x1]; 332 u8 outer_dip[0x1]; 333 u8 outer_frag[0x1]; 334 u8 outer_ip_protocol[0x1]; 335 u8 outer_ip_ecn[0x1]; 336 u8 outer_ip_dscp[0x1]; 337 u8 outer_udp_sport[0x1]; 338 u8 outer_udp_dport[0x1]; 339 u8 outer_tcp_sport[0x1]; 340 u8 outer_tcp_dport[0x1]; 341 u8 outer_tcp_flags[0x1]; 342 u8 outer_gre_protocol[0x1]; 343 u8 outer_gre_key[0x1]; 344 u8 outer_vxlan_vni[0x1]; 345 u8 outer_geneve_vni[0x1]; 346 u8 outer_geneve_oam[0x1]; 347 u8 outer_geneve_protocol_type[0x1]; 348 u8 outer_geneve_opt_len[0x1]; 349 u8 source_vhca_port[0x1]; 350 u8 source_eswitch_port[0x1]; 351 352 u8 inner_dmac[0x1]; 353 u8 inner_smac[0x1]; 354 u8 inner_ether_type[0x1]; 355 u8 inner_ip_version[0x1]; 356 u8 inner_first_prio[0x1]; 357 u8 inner_first_cfi[0x1]; 358 u8 inner_first_vid[0x1]; 359 u8 reserved_at_27[0x1]; 360 u8 inner_second_prio[0x1]; 361 u8 inner_second_cfi[0x1]; 362 u8 inner_second_vid[0x1]; 363 u8 reserved_at_2b[0x1]; 364 u8 inner_sip[0x1]; 365 u8 inner_dip[0x1]; 366 u8 inner_frag[0x1]; 367 u8 inner_ip_protocol[0x1]; 368 u8 inner_ip_ecn[0x1]; 369 u8 inner_ip_dscp[0x1]; 370 u8 inner_udp_sport[0x1]; 371 u8 inner_udp_dport[0x1]; 372 u8 inner_tcp_sport[0x1]; 373 u8 inner_tcp_dport[0x1]; 374 u8 inner_tcp_flags[0x1]; 375 u8 reserved_at_37[0x9]; 376 377 u8 geneve_tlv_option_0_data[0x1]; 378 u8 geneve_tlv_option_0_exist[0x1]; 379 u8 reserved_at_42[0x3]; 380 u8 outer_first_mpls_over_udp[0x4]; 381 u8 outer_first_mpls_over_gre[0x4]; 382 u8 inner_first_mpls[0x4]; 383 u8 outer_first_mpls[0x4]; 384 u8 reserved_at_55[0x2]; 385 u8 outer_esp_spi[0x1]; 386 u8 reserved_at_58[0x2]; 387 u8 bth_dst_qp[0x1]; 388 u8 reserved_at_5b[0x5]; 389 390 u8 reserved_at_60[0x18]; 391 u8 metadata_reg_c_7[0x1]; 392 u8 metadata_reg_c_6[0x1]; 393 u8 metadata_reg_c_5[0x1]; 394 u8 metadata_reg_c_4[0x1]; 395 u8 metadata_reg_c_3[0x1]; 396 u8 metadata_reg_c_2[0x1]; 397 u8 metadata_reg_c_1[0x1]; 398 u8 metadata_reg_c_0[0x1]; 399 }; 400 401 struct mlx5_ifc_flow_table_fields_supported_2_bits { 402 u8 reserved_at_0[0xe]; 403 u8 bth_opcode[0x1]; 404 u8 reserved_at_f[0x11]; 405 406 u8 reserved_at_20[0x60]; 407 }; 408 409 struct mlx5_ifc_flow_table_prop_layout_bits { 410 u8 ft_support[0x1]; 411 u8 reserved_at_1[0x1]; 412 u8 flow_counter[0x1]; 413 u8 flow_modify_en[0x1]; 414 u8 modify_root[0x1]; 415 u8 identified_miss_table_mode[0x1]; 416 u8 flow_table_modify[0x1]; 417 u8 reformat[0x1]; 418 u8 decap[0x1]; 419 u8 reserved_at_9[0x1]; 420 u8 pop_vlan[0x1]; 421 u8 push_vlan[0x1]; 422 u8 reserved_at_c[0x1]; 423 u8 pop_vlan_2[0x1]; 424 u8 push_vlan_2[0x1]; 425 u8 reformat_and_vlan_action[0x1]; 426 u8 reserved_at_10[0x1]; 427 u8 sw_owner[0x1]; 428 u8 reformat_l3_tunnel_to_l2[0x1]; 429 u8 reformat_l2_to_l3_tunnel[0x1]; 430 u8 reformat_and_modify_action[0x1]; 431 u8 ignore_flow_level[0x1]; 432 u8 reserved_at_16[0x1]; 433 u8 table_miss_action_domain[0x1]; 434 u8 termination_table[0x1]; 435 u8 reformat_and_fwd_to_table[0x1]; 436 u8 reserved_at_1a[0x2]; 437 u8 ipsec_encrypt[0x1]; 438 u8 ipsec_decrypt[0x1]; 439 u8 sw_owner_v2[0x1]; 440 u8 reserved_at_1f[0x1]; 441 442 u8 termination_table_raw_traffic[0x1]; 443 u8 reserved_at_21[0x1]; 444 u8 log_max_ft_size[0x6]; 445 u8 log_max_modify_header_context[0x8]; 446 u8 max_modify_header_actions[0x8]; 447 u8 max_ft_level[0x8]; 448 449 u8 reformat_add_esp_trasport[0x1]; 450 u8 reserved_at_41[0x2]; 451 u8 reformat_del_esp_trasport[0x1]; 452 u8 reserved_at_44[0x2]; 453 u8 execute_aso[0x1]; 454 u8 reserved_at_47[0x19]; 455 456 u8 reserved_at_60[0x2]; 457 u8 reformat_insert[0x1]; 458 u8 reformat_remove[0x1]; 459 u8 macsec_encrypt[0x1]; 460 u8 macsec_decrypt[0x1]; 461 u8 reserved_at_66[0x2]; 462 u8 reformat_add_macsec[0x1]; 463 u8 reformat_remove_macsec[0x1]; 464 u8 reserved_at_6a[0xe]; 465 u8 log_max_ft_num[0x8]; 466 467 u8 reserved_at_80[0x10]; 468 u8 log_max_flow_counter[0x8]; 469 u8 log_max_destination[0x8]; 470 471 u8 reserved_at_a0[0x18]; 472 u8 log_max_flow[0x8]; 473 474 u8 reserved_at_c0[0x40]; 475 476 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support; 477 478 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support; 479 }; 480 481 struct mlx5_ifc_odp_per_transport_service_cap_bits { 482 u8 send[0x1]; 483 u8 receive[0x1]; 484 u8 write[0x1]; 485 u8 read[0x1]; 486 u8 atomic[0x1]; 487 u8 srq_receive[0x1]; 488 u8 reserved_at_6[0x1a]; 489 }; 490 491 struct mlx5_ifc_ipv4_layout_bits { 492 u8 reserved_at_0[0x60]; 493 494 u8 ipv4[0x20]; 495 }; 496 497 struct mlx5_ifc_ipv6_layout_bits { 498 u8 ipv6[16][0x8]; 499 }; 500 501 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits { 502 struct mlx5_ifc_ipv6_layout_bits ipv6_layout; 503 struct mlx5_ifc_ipv4_layout_bits ipv4_layout; 504 u8 reserved_at_0[0x80]; 505 }; 506 507 struct mlx5_ifc_fte_match_set_lyr_2_4_bits { 508 u8 smac_47_16[0x20]; 509 510 u8 smac_15_0[0x10]; 511 u8 ethertype[0x10]; 512 513 u8 dmac_47_16[0x20]; 514 515 u8 dmac_15_0[0x10]; 516 u8 first_prio[0x3]; 517 u8 first_cfi[0x1]; 518 u8 first_vid[0xc]; 519 520 u8 ip_protocol[0x8]; 521 u8 ip_dscp[0x6]; 522 u8 ip_ecn[0x2]; 523 u8 cvlan_tag[0x1]; 524 u8 svlan_tag[0x1]; 525 u8 frag[0x1]; 526 u8 ip_version[0x4]; 527 u8 tcp_flags[0x9]; 528 529 u8 tcp_sport[0x10]; 530 u8 tcp_dport[0x10]; 531 532 u8 reserved_at_c0[0x10]; 533 u8 ipv4_ihl[0x4]; 534 u8 reserved_at_c4[0x4]; 535 536 u8 ttl_hoplimit[0x8]; 537 538 u8 udp_sport[0x10]; 539 u8 udp_dport[0x10]; 540 541 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6; 542 543 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6; 544 }; 545 546 struct mlx5_ifc_nvgre_key_bits { 547 u8 hi[0x18]; 548 u8 lo[0x8]; 549 }; 550 551 union mlx5_ifc_gre_key_bits { 552 struct mlx5_ifc_nvgre_key_bits nvgre; 553 u8 key[0x20]; 554 }; 555 556 struct mlx5_ifc_fte_match_set_misc_bits { 557 u8 gre_c_present[0x1]; 558 u8 reserved_at_1[0x1]; 559 u8 gre_k_present[0x1]; 560 u8 gre_s_present[0x1]; 561 u8 source_vhca_port[0x4]; 562 u8 source_sqn[0x18]; 563 564 u8 source_eswitch_owner_vhca_id[0x10]; 565 u8 source_port[0x10]; 566 567 u8 outer_second_prio[0x3]; 568 u8 outer_second_cfi[0x1]; 569 u8 outer_second_vid[0xc]; 570 u8 inner_second_prio[0x3]; 571 u8 inner_second_cfi[0x1]; 572 u8 inner_second_vid[0xc]; 573 574 u8 outer_second_cvlan_tag[0x1]; 575 u8 inner_second_cvlan_tag[0x1]; 576 u8 outer_second_svlan_tag[0x1]; 577 u8 inner_second_svlan_tag[0x1]; 578 u8 reserved_at_64[0xc]; 579 u8 gre_protocol[0x10]; 580 581 union mlx5_ifc_gre_key_bits gre_key; 582 583 u8 vxlan_vni[0x18]; 584 u8 bth_opcode[0x8]; 585 586 u8 geneve_vni[0x18]; 587 u8 reserved_at_d8[0x6]; 588 u8 geneve_tlv_option_0_exist[0x1]; 589 u8 geneve_oam[0x1]; 590 591 u8 reserved_at_e0[0xc]; 592 u8 outer_ipv6_flow_label[0x14]; 593 594 u8 reserved_at_100[0xc]; 595 u8 inner_ipv6_flow_label[0x14]; 596 597 u8 reserved_at_120[0xa]; 598 u8 geneve_opt_len[0x6]; 599 u8 geneve_protocol_type[0x10]; 600 601 u8 reserved_at_140[0x8]; 602 u8 bth_dst_qp[0x18]; 603 u8 reserved_at_160[0x20]; 604 u8 outer_esp_spi[0x20]; 605 u8 reserved_at_1a0[0x60]; 606 }; 607 608 struct mlx5_ifc_fte_match_mpls_bits { 609 u8 mpls_label[0x14]; 610 u8 mpls_exp[0x3]; 611 u8 mpls_s_bos[0x1]; 612 u8 mpls_ttl[0x8]; 613 }; 614 615 struct mlx5_ifc_fte_match_set_misc2_bits { 616 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls; 617 618 struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls; 619 620 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre; 621 622 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp; 623 624 u8 metadata_reg_c_7[0x20]; 625 626 u8 metadata_reg_c_6[0x20]; 627 628 u8 metadata_reg_c_5[0x20]; 629 630 u8 metadata_reg_c_4[0x20]; 631 632 u8 metadata_reg_c_3[0x20]; 633 634 u8 metadata_reg_c_2[0x20]; 635 636 u8 metadata_reg_c_1[0x20]; 637 638 u8 metadata_reg_c_0[0x20]; 639 640 u8 metadata_reg_a[0x20]; 641 642 u8 reserved_at_1a0[0x8]; 643 644 u8 macsec_syndrome[0x8]; 645 u8 ipsec_syndrome[0x8]; 646 u8 reserved_at_1b8[0x8]; 647 648 u8 reserved_at_1c0[0x40]; 649 }; 650 651 struct mlx5_ifc_fte_match_set_misc3_bits { 652 u8 inner_tcp_seq_num[0x20]; 653 654 u8 outer_tcp_seq_num[0x20]; 655 656 u8 inner_tcp_ack_num[0x20]; 657 658 u8 outer_tcp_ack_num[0x20]; 659 660 u8 reserved_at_80[0x8]; 661 u8 outer_vxlan_gpe_vni[0x18]; 662 663 u8 outer_vxlan_gpe_next_protocol[0x8]; 664 u8 outer_vxlan_gpe_flags[0x8]; 665 u8 reserved_at_b0[0x10]; 666 667 u8 icmp_header_data[0x20]; 668 669 u8 icmpv6_header_data[0x20]; 670 671 u8 icmp_type[0x8]; 672 u8 icmp_code[0x8]; 673 u8 icmpv6_type[0x8]; 674 u8 icmpv6_code[0x8]; 675 676 u8 geneve_tlv_option_0_data[0x20]; 677 678 u8 gtpu_teid[0x20]; 679 680 u8 gtpu_msg_type[0x8]; 681 u8 gtpu_msg_flags[0x8]; 682 u8 reserved_at_170[0x10]; 683 684 u8 gtpu_dw_2[0x20]; 685 686 u8 gtpu_first_ext_dw_0[0x20]; 687 688 u8 gtpu_dw_0[0x20]; 689 690 u8 reserved_at_1e0[0x20]; 691 }; 692 693 struct mlx5_ifc_fte_match_set_misc4_bits { 694 u8 prog_sample_field_value_0[0x20]; 695 696 u8 prog_sample_field_id_0[0x20]; 697 698 u8 prog_sample_field_value_1[0x20]; 699 700 u8 prog_sample_field_id_1[0x20]; 701 702 u8 prog_sample_field_value_2[0x20]; 703 704 u8 prog_sample_field_id_2[0x20]; 705 706 u8 prog_sample_field_value_3[0x20]; 707 708 u8 prog_sample_field_id_3[0x20]; 709 710 u8 reserved_at_100[0x100]; 711 }; 712 713 struct mlx5_ifc_fte_match_set_misc5_bits { 714 u8 macsec_tag_0[0x20]; 715 716 u8 macsec_tag_1[0x20]; 717 718 u8 macsec_tag_2[0x20]; 719 720 u8 macsec_tag_3[0x20]; 721 722 u8 tunnel_header_0[0x20]; 723 724 u8 tunnel_header_1[0x20]; 725 726 u8 tunnel_header_2[0x20]; 727 728 u8 tunnel_header_3[0x20]; 729 730 u8 reserved_at_100[0x100]; 731 }; 732 733 struct mlx5_ifc_cmd_pas_bits { 734 u8 pa_h[0x20]; 735 736 u8 pa_l[0x14]; 737 u8 reserved_at_34[0xc]; 738 }; 739 740 struct mlx5_ifc_uint64_bits { 741 u8 hi[0x20]; 742 743 u8 lo[0x20]; 744 }; 745 746 enum { 747 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0, 748 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7, 749 MLX5_ADS_STAT_RATE_10GBPS = 0x8, 750 MLX5_ADS_STAT_RATE_30GBPS = 0x9, 751 MLX5_ADS_STAT_RATE_5GBPS = 0xa, 752 MLX5_ADS_STAT_RATE_20GBPS = 0xb, 753 MLX5_ADS_STAT_RATE_40GBPS = 0xc, 754 MLX5_ADS_STAT_RATE_60GBPS = 0xd, 755 MLX5_ADS_STAT_RATE_80GBPS = 0xe, 756 MLX5_ADS_STAT_RATE_120GBPS = 0xf, 757 }; 758 759 struct mlx5_ifc_ads_bits { 760 u8 fl[0x1]; 761 u8 free_ar[0x1]; 762 u8 reserved_at_2[0xe]; 763 u8 pkey_index[0x10]; 764 765 u8 reserved_at_20[0x8]; 766 u8 grh[0x1]; 767 u8 mlid[0x7]; 768 u8 rlid[0x10]; 769 770 u8 ack_timeout[0x5]; 771 u8 reserved_at_45[0x3]; 772 u8 src_addr_index[0x8]; 773 u8 reserved_at_50[0x4]; 774 u8 stat_rate[0x4]; 775 u8 hop_limit[0x8]; 776 777 u8 reserved_at_60[0x4]; 778 u8 tclass[0x8]; 779 u8 flow_label[0x14]; 780 781 u8 rgid_rip[16][0x8]; 782 783 u8 reserved_at_100[0x4]; 784 u8 f_dscp[0x1]; 785 u8 f_ecn[0x1]; 786 u8 reserved_at_106[0x1]; 787 u8 f_eth_prio[0x1]; 788 u8 ecn[0x2]; 789 u8 dscp[0x6]; 790 u8 udp_sport[0x10]; 791 792 u8 dei_cfi[0x1]; 793 u8 eth_prio[0x3]; 794 u8 sl[0x4]; 795 u8 vhca_port_num[0x8]; 796 u8 rmac_47_32[0x10]; 797 798 u8 rmac_31_0[0x20]; 799 }; 800 801 struct mlx5_ifc_flow_table_nic_cap_bits { 802 u8 nic_rx_multi_path_tirs[0x1]; 803 u8 nic_rx_multi_path_tirs_fts[0x1]; 804 u8 allow_sniffer_and_nic_rx_shared_tir[0x1]; 805 u8 reserved_at_3[0x4]; 806 u8 sw_owner_reformat_supported[0x1]; 807 u8 reserved_at_8[0x18]; 808 809 u8 encap_general_header[0x1]; 810 u8 reserved_at_21[0xa]; 811 u8 log_max_packet_reformat_context[0x5]; 812 u8 reserved_at_30[0x6]; 813 u8 max_encap_header_size[0xa]; 814 u8 reserved_at_40[0x1c0]; 815 816 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive; 817 818 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_rdma; 819 820 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer; 821 822 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit; 823 824 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_rdma; 825 826 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer; 827 828 u8 reserved_at_e00[0x700]; 829 830 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_receive_rdma; 831 832 u8 reserved_at_1580[0x280]; 833 834 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_transmit_rdma; 835 836 u8 reserved_at_1880[0x780]; 837 838 u8 sw_steering_nic_rx_action_drop_icm_address[0x40]; 839 840 u8 sw_steering_nic_tx_action_drop_icm_address[0x40]; 841 842 u8 sw_steering_nic_tx_action_allow_icm_address[0x40]; 843 844 u8 reserved_at_20c0[0x5f40]; 845 }; 846 847 struct mlx5_ifc_port_selection_cap_bits { 848 u8 reserved_at_0[0x10]; 849 u8 port_select_flow_table[0x1]; 850 u8 reserved_at_11[0x1]; 851 u8 port_select_flow_table_bypass[0x1]; 852 u8 reserved_at_13[0xd]; 853 854 u8 reserved_at_20[0x1e0]; 855 856 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_port_selection; 857 858 u8 reserved_at_400[0x7c00]; 859 }; 860 861 enum { 862 MLX5_FDB_TO_VPORT_REG_C_0 = 0x01, 863 MLX5_FDB_TO_VPORT_REG_C_1 = 0x02, 864 MLX5_FDB_TO_VPORT_REG_C_2 = 0x04, 865 MLX5_FDB_TO_VPORT_REG_C_3 = 0x08, 866 MLX5_FDB_TO_VPORT_REG_C_4 = 0x10, 867 MLX5_FDB_TO_VPORT_REG_C_5 = 0x20, 868 MLX5_FDB_TO_VPORT_REG_C_6 = 0x40, 869 MLX5_FDB_TO_VPORT_REG_C_7 = 0x80, 870 }; 871 872 struct mlx5_ifc_flow_table_eswitch_cap_bits { 873 u8 fdb_to_vport_reg_c_id[0x8]; 874 u8 reserved_at_8[0xd]; 875 u8 fdb_modify_header_fwd_to_table[0x1]; 876 u8 fdb_ipv4_ttl_modify[0x1]; 877 u8 flow_source[0x1]; 878 u8 reserved_at_18[0x2]; 879 u8 multi_fdb_encap[0x1]; 880 u8 egress_acl_forward_to_vport[0x1]; 881 u8 fdb_multi_path_to_table[0x1]; 882 u8 reserved_at_1d[0x3]; 883 884 u8 reserved_at_20[0x1e0]; 885 886 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb; 887 888 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress; 889 890 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress; 891 892 u8 reserved_at_800[0x1000]; 893 894 u8 sw_steering_fdb_action_drop_icm_address_rx[0x40]; 895 896 u8 sw_steering_fdb_action_drop_icm_address_tx[0x40]; 897 898 u8 sw_steering_uplink_icm_address_rx[0x40]; 899 900 u8 sw_steering_uplink_icm_address_tx[0x40]; 901 902 u8 reserved_at_1900[0x6700]; 903 }; 904 905 enum { 906 MLX5_COUNTER_SOURCE_ESWITCH = 0x0, 907 MLX5_COUNTER_FLOW_ESWITCH = 0x1, 908 }; 909 910 struct mlx5_ifc_e_switch_cap_bits { 911 u8 vport_svlan_strip[0x1]; 912 u8 vport_cvlan_strip[0x1]; 913 u8 vport_svlan_insert[0x1]; 914 u8 vport_cvlan_insert_if_not_exist[0x1]; 915 u8 vport_cvlan_insert_overwrite[0x1]; 916 u8 reserved_at_5[0x2]; 917 u8 esw_shared_ingress_acl[0x1]; 918 u8 esw_uplink_ingress_acl[0x1]; 919 u8 root_ft_on_other_esw[0x1]; 920 u8 reserved_at_a[0xf]; 921 u8 esw_functions_changed[0x1]; 922 u8 reserved_at_1a[0x1]; 923 u8 ecpf_vport_exists[0x1]; 924 u8 counter_eswitch_affinity[0x1]; 925 u8 merged_eswitch[0x1]; 926 u8 nic_vport_node_guid_modify[0x1]; 927 u8 nic_vport_port_guid_modify[0x1]; 928 929 u8 vxlan_encap_decap[0x1]; 930 u8 nvgre_encap_decap[0x1]; 931 u8 reserved_at_22[0x1]; 932 u8 log_max_fdb_encap_uplink[0x5]; 933 u8 reserved_at_21[0x3]; 934 u8 log_max_packet_reformat_context[0x5]; 935 u8 reserved_2b[0x6]; 936 u8 max_encap_header_size[0xa]; 937 938 u8 reserved_at_40[0xb]; 939 u8 log_max_esw_sf[0x5]; 940 u8 esw_sf_base_id[0x10]; 941 942 u8 reserved_at_60[0x7a0]; 943 944 }; 945 946 struct mlx5_ifc_qos_cap_bits { 947 u8 packet_pacing[0x1]; 948 u8 esw_scheduling[0x1]; 949 u8 esw_bw_share[0x1]; 950 u8 esw_rate_limit[0x1]; 951 u8 reserved_at_4[0x1]; 952 u8 packet_pacing_burst_bound[0x1]; 953 u8 packet_pacing_typical_size[0x1]; 954 u8 reserved_at_7[0x1]; 955 u8 nic_sq_scheduling[0x1]; 956 u8 nic_bw_share[0x1]; 957 u8 nic_rate_limit[0x1]; 958 u8 packet_pacing_uid[0x1]; 959 u8 log_esw_max_sched_depth[0x4]; 960 u8 reserved_at_10[0x10]; 961 962 u8 reserved_at_20[0xb]; 963 u8 log_max_qos_nic_queue_group[0x5]; 964 u8 reserved_at_30[0x10]; 965 966 u8 packet_pacing_max_rate[0x20]; 967 968 u8 packet_pacing_min_rate[0x20]; 969 970 u8 reserved_at_80[0x10]; 971 u8 packet_pacing_rate_table_size[0x10]; 972 973 u8 esw_element_type[0x10]; 974 u8 esw_tsar_type[0x10]; 975 976 u8 reserved_at_c0[0x10]; 977 u8 max_qos_para_vport[0x10]; 978 979 u8 max_tsar_bw_share[0x20]; 980 981 u8 reserved_at_100[0x20]; 982 983 u8 reserved_at_120[0x3]; 984 u8 log_meter_aso_granularity[0x5]; 985 u8 reserved_at_128[0x3]; 986 u8 log_meter_aso_max_alloc[0x5]; 987 u8 reserved_at_130[0x3]; 988 u8 log_max_num_meter_aso[0x5]; 989 u8 reserved_at_138[0x8]; 990 991 u8 reserved_at_140[0x6c0]; 992 }; 993 994 struct mlx5_ifc_debug_cap_bits { 995 u8 core_dump_general[0x1]; 996 u8 core_dump_qp[0x1]; 997 u8 reserved_at_2[0x7]; 998 u8 resource_dump[0x1]; 999 u8 reserved_at_a[0x16]; 1000 1001 u8 reserved_at_20[0x2]; 1002 u8 stall_detect[0x1]; 1003 u8 reserved_at_23[0x1d]; 1004 1005 u8 reserved_at_40[0x7c0]; 1006 }; 1007 1008 struct mlx5_ifc_per_protocol_networking_offload_caps_bits { 1009 u8 csum_cap[0x1]; 1010 u8 vlan_cap[0x1]; 1011 u8 lro_cap[0x1]; 1012 u8 lro_psh_flag[0x1]; 1013 u8 lro_time_stamp[0x1]; 1014 u8 reserved_at_5[0x2]; 1015 u8 wqe_vlan_insert[0x1]; 1016 u8 self_lb_en_modifiable[0x1]; 1017 u8 reserved_at_9[0x2]; 1018 u8 max_lso_cap[0x5]; 1019 u8 multi_pkt_send_wqe[0x2]; 1020 u8 wqe_inline_mode[0x2]; 1021 u8 rss_ind_tbl_cap[0x4]; 1022 u8 reg_umr_sq[0x1]; 1023 u8 scatter_fcs[0x1]; 1024 u8 enhanced_multi_pkt_send_wqe[0x1]; 1025 u8 tunnel_lso_const_out_ip_id[0x1]; 1026 u8 tunnel_lro_gre[0x1]; 1027 u8 tunnel_lro_vxlan[0x1]; 1028 u8 tunnel_stateless_gre[0x1]; 1029 u8 tunnel_stateless_vxlan[0x1]; 1030 1031 u8 swp[0x1]; 1032 u8 swp_csum[0x1]; 1033 u8 swp_lso[0x1]; 1034 u8 cqe_checksum_full[0x1]; 1035 u8 tunnel_stateless_geneve_tx[0x1]; 1036 u8 tunnel_stateless_mpls_over_udp[0x1]; 1037 u8 tunnel_stateless_mpls_over_gre[0x1]; 1038 u8 tunnel_stateless_vxlan_gpe[0x1]; 1039 u8 tunnel_stateless_ipv4_over_vxlan[0x1]; 1040 u8 tunnel_stateless_ip_over_ip[0x1]; 1041 u8 insert_trailer[0x1]; 1042 u8 reserved_at_2b[0x1]; 1043 u8 tunnel_stateless_ip_over_ip_rx[0x1]; 1044 u8 tunnel_stateless_ip_over_ip_tx[0x1]; 1045 u8 reserved_at_2e[0x2]; 1046 u8 max_vxlan_udp_ports[0x8]; 1047 u8 reserved_at_38[0x6]; 1048 u8 max_geneve_opt_len[0x1]; 1049 u8 tunnel_stateless_geneve_rx[0x1]; 1050 1051 u8 reserved_at_40[0x10]; 1052 u8 lro_min_mss_size[0x10]; 1053 1054 u8 reserved_at_60[0x120]; 1055 1056 u8 lro_timer_supported_periods[4][0x20]; 1057 1058 u8 reserved_at_200[0x600]; 1059 }; 1060 1061 enum { 1062 MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING = 0x0, 1063 MLX5_TIMESTAMP_FORMAT_CAP_REAL_TIME = 0x1, 1064 MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING_AND_REAL_TIME = 0x2, 1065 }; 1066 1067 struct mlx5_ifc_roce_cap_bits { 1068 u8 roce_apm[0x1]; 1069 u8 reserved_at_1[0x3]; 1070 u8 sw_r_roce_src_udp_port[0x1]; 1071 u8 fl_rc_qp_when_roce_disabled[0x1]; 1072 u8 fl_rc_qp_when_roce_enabled[0x1]; 1073 u8 reserved_at_7[0x17]; 1074 u8 qp_ts_format[0x2]; 1075 1076 u8 reserved_at_20[0x60]; 1077 1078 u8 reserved_at_80[0xc]; 1079 u8 l3_type[0x4]; 1080 u8 reserved_at_90[0x8]; 1081 u8 roce_version[0x8]; 1082 1083 u8 reserved_at_a0[0x10]; 1084 u8 r_roce_dest_udp_port[0x10]; 1085 1086 u8 r_roce_max_src_udp_port[0x10]; 1087 u8 r_roce_min_src_udp_port[0x10]; 1088 1089 u8 reserved_at_e0[0x10]; 1090 u8 roce_address_table_size[0x10]; 1091 1092 u8 reserved_at_100[0x700]; 1093 }; 1094 1095 struct mlx5_ifc_sync_steering_in_bits { 1096 u8 opcode[0x10]; 1097 u8 uid[0x10]; 1098 1099 u8 reserved_at_20[0x10]; 1100 u8 op_mod[0x10]; 1101 1102 u8 reserved_at_40[0xc0]; 1103 }; 1104 1105 struct mlx5_ifc_sync_steering_out_bits { 1106 u8 status[0x8]; 1107 u8 reserved_at_8[0x18]; 1108 1109 u8 syndrome[0x20]; 1110 1111 u8 reserved_at_40[0x40]; 1112 }; 1113 1114 struct mlx5_ifc_device_mem_cap_bits { 1115 u8 memic[0x1]; 1116 u8 reserved_at_1[0x1f]; 1117 1118 u8 reserved_at_20[0xb]; 1119 u8 log_min_memic_alloc_size[0x5]; 1120 u8 reserved_at_30[0x8]; 1121 u8 log_max_memic_addr_alignment[0x8]; 1122 1123 u8 memic_bar_start_addr[0x40]; 1124 1125 u8 memic_bar_size[0x20]; 1126 1127 u8 max_memic_size[0x20]; 1128 1129 u8 steering_sw_icm_start_address[0x40]; 1130 1131 u8 reserved_at_100[0x8]; 1132 u8 log_header_modify_sw_icm_size[0x8]; 1133 u8 reserved_at_110[0x2]; 1134 u8 log_sw_icm_alloc_granularity[0x6]; 1135 u8 log_steering_sw_icm_size[0x8]; 1136 1137 u8 reserved_at_120[0x18]; 1138 u8 log_header_modify_pattern_sw_icm_size[0x8]; 1139 1140 u8 header_modify_sw_icm_start_address[0x40]; 1141 1142 u8 reserved_at_180[0x40]; 1143 1144 u8 header_modify_pattern_sw_icm_start_address[0x40]; 1145 1146 u8 memic_operations[0x20]; 1147 1148 u8 reserved_at_220[0x5e0]; 1149 }; 1150 1151 struct mlx5_ifc_device_event_cap_bits { 1152 u8 user_affiliated_events[4][0x40]; 1153 1154 u8 user_unaffiliated_events[4][0x40]; 1155 }; 1156 1157 struct mlx5_ifc_virtio_emulation_cap_bits { 1158 u8 desc_tunnel_offload_type[0x1]; 1159 u8 eth_frame_offload_type[0x1]; 1160 u8 virtio_version_1_0[0x1]; 1161 u8 device_features_bits_mask[0xd]; 1162 u8 event_mode[0x8]; 1163 u8 virtio_queue_type[0x8]; 1164 1165 u8 max_tunnel_desc[0x10]; 1166 u8 reserved_at_30[0x3]; 1167 u8 log_doorbell_stride[0x5]; 1168 u8 reserved_at_38[0x3]; 1169 u8 log_doorbell_bar_size[0x5]; 1170 1171 u8 doorbell_bar_offset[0x40]; 1172 1173 u8 max_emulated_devices[0x8]; 1174 u8 max_num_virtio_queues[0x18]; 1175 1176 u8 reserved_at_a0[0x60]; 1177 1178 u8 umem_1_buffer_param_a[0x20]; 1179 1180 u8 umem_1_buffer_param_b[0x20]; 1181 1182 u8 umem_2_buffer_param_a[0x20]; 1183 1184 u8 umem_2_buffer_param_b[0x20]; 1185 1186 u8 umem_3_buffer_param_a[0x20]; 1187 1188 u8 umem_3_buffer_param_b[0x20]; 1189 1190 u8 reserved_at_1c0[0x640]; 1191 }; 1192 1193 enum { 1194 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0, 1195 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2, 1196 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4, 1197 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8, 1198 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10, 1199 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20, 1200 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40, 1201 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80, 1202 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100, 1203 }; 1204 1205 enum { 1206 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1, 1207 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2, 1208 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4, 1209 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8, 1210 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10, 1211 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20, 1212 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40, 1213 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80, 1214 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100, 1215 }; 1216 1217 struct mlx5_ifc_atomic_caps_bits { 1218 u8 reserved_at_0[0x40]; 1219 1220 u8 atomic_req_8B_endianness_mode[0x2]; 1221 u8 reserved_at_42[0x4]; 1222 u8 supported_atomic_req_8B_endianness_mode_1[0x1]; 1223 1224 u8 reserved_at_47[0x19]; 1225 1226 u8 reserved_at_60[0x20]; 1227 1228 u8 reserved_at_80[0x10]; 1229 u8 atomic_operations[0x10]; 1230 1231 u8 reserved_at_a0[0x10]; 1232 u8 atomic_size_qp[0x10]; 1233 1234 u8 reserved_at_c0[0x10]; 1235 u8 atomic_size_dc[0x10]; 1236 1237 u8 reserved_at_e0[0x720]; 1238 }; 1239 1240 struct mlx5_ifc_odp_cap_bits { 1241 u8 reserved_at_0[0x40]; 1242 1243 u8 sig[0x1]; 1244 u8 reserved_at_41[0x1f]; 1245 1246 u8 reserved_at_60[0x20]; 1247 1248 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps; 1249 1250 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps; 1251 1252 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps; 1253 1254 struct mlx5_ifc_odp_per_transport_service_cap_bits xrc_odp_caps; 1255 1256 struct mlx5_ifc_odp_per_transport_service_cap_bits dc_odp_caps; 1257 1258 u8 reserved_at_120[0x6E0]; 1259 }; 1260 1261 struct mlx5_ifc_calc_op { 1262 u8 reserved_at_0[0x10]; 1263 u8 reserved_at_10[0x9]; 1264 u8 op_swap_endianness[0x1]; 1265 u8 op_min[0x1]; 1266 u8 op_xor[0x1]; 1267 u8 op_or[0x1]; 1268 u8 op_and[0x1]; 1269 u8 op_max[0x1]; 1270 u8 op_add[0x1]; 1271 }; 1272 1273 struct mlx5_ifc_vector_calc_cap_bits { 1274 u8 calc_matrix[0x1]; 1275 u8 reserved_at_1[0x1f]; 1276 u8 reserved_at_20[0x8]; 1277 u8 max_vec_count[0x8]; 1278 u8 reserved_at_30[0xd]; 1279 u8 max_chunk_size[0x3]; 1280 struct mlx5_ifc_calc_op calc0; 1281 struct mlx5_ifc_calc_op calc1; 1282 struct mlx5_ifc_calc_op calc2; 1283 struct mlx5_ifc_calc_op calc3; 1284 1285 u8 reserved_at_c0[0x720]; 1286 }; 1287 1288 struct mlx5_ifc_tls_cap_bits { 1289 u8 tls_1_2_aes_gcm_128[0x1]; 1290 u8 tls_1_3_aes_gcm_128[0x1]; 1291 u8 tls_1_2_aes_gcm_256[0x1]; 1292 u8 tls_1_3_aes_gcm_256[0x1]; 1293 u8 reserved_at_4[0x1c]; 1294 1295 u8 reserved_at_20[0x7e0]; 1296 }; 1297 1298 struct mlx5_ifc_ipsec_cap_bits { 1299 u8 ipsec_full_offload[0x1]; 1300 u8 ipsec_crypto_offload[0x1]; 1301 u8 ipsec_esn[0x1]; 1302 u8 ipsec_crypto_esp_aes_gcm_256_encrypt[0x1]; 1303 u8 ipsec_crypto_esp_aes_gcm_128_encrypt[0x1]; 1304 u8 ipsec_crypto_esp_aes_gcm_256_decrypt[0x1]; 1305 u8 ipsec_crypto_esp_aes_gcm_128_decrypt[0x1]; 1306 u8 reserved_at_7[0x4]; 1307 u8 log_max_ipsec_offload[0x5]; 1308 u8 reserved_at_10[0x10]; 1309 1310 u8 min_log_ipsec_full_replay_window[0x8]; 1311 u8 max_log_ipsec_full_replay_window[0x8]; 1312 u8 reserved_at_30[0x7d0]; 1313 }; 1314 1315 struct mlx5_ifc_macsec_cap_bits { 1316 u8 macsec_epn[0x1]; 1317 u8 reserved_at_1[0x2]; 1318 u8 macsec_crypto_esp_aes_gcm_256_encrypt[0x1]; 1319 u8 macsec_crypto_esp_aes_gcm_128_encrypt[0x1]; 1320 u8 macsec_crypto_esp_aes_gcm_256_decrypt[0x1]; 1321 u8 macsec_crypto_esp_aes_gcm_128_decrypt[0x1]; 1322 u8 reserved_at_7[0x4]; 1323 u8 log_max_macsec_offload[0x5]; 1324 u8 reserved_at_10[0x10]; 1325 1326 u8 min_log_macsec_full_replay_window[0x8]; 1327 u8 max_log_macsec_full_replay_window[0x8]; 1328 u8 reserved_at_30[0x10]; 1329 1330 u8 reserved_at_40[0x7c0]; 1331 }; 1332 1333 enum { 1334 MLX5_WQ_TYPE_LINKED_LIST = 0x0, 1335 MLX5_WQ_TYPE_CYCLIC = 0x1, 1336 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2, 1337 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3, 1338 }; 1339 1340 enum { 1341 MLX5_WQ_END_PAD_MODE_NONE = 0x0, 1342 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1, 1343 }; 1344 1345 enum { 1346 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0, 1347 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1, 1348 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2, 1349 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3, 1350 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4, 1351 }; 1352 1353 enum { 1354 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0, 1355 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1, 1356 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2, 1357 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3, 1358 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4, 1359 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5, 1360 }; 1361 1362 enum { 1363 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0, 1364 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1, 1365 }; 1366 1367 enum { 1368 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0, 1369 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1, 1370 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3, 1371 }; 1372 1373 enum { 1374 MLX5_CAP_PORT_TYPE_IB = 0x0, 1375 MLX5_CAP_PORT_TYPE_ETH = 0x1, 1376 }; 1377 1378 enum { 1379 MLX5_CAP_UMR_FENCE_STRONG = 0x0, 1380 MLX5_CAP_UMR_FENCE_SMALL = 0x1, 1381 MLX5_CAP_UMR_FENCE_NONE = 0x2, 1382 }; 1383 1384 enum { 1385 MLX5_FLEX_PARSER_GENEVE_ENABLED = 1 << 3, 1386 MLX5_FLEX_PARSER_MPLS_OVER_GRE_ENABLED = 1 << 4, 1387 MLX5_FLEX_PARSER_MPLS_OVER_UDP_ENABLED = 1 << 5, 1388 MLX5_FLEX_PARSER_VXLAN_GPE_ENABLED = 1 << 7, 1389 MLX5_FLEX_PARSER_ICMP_V4_ENABLED = 1 << 8, 1390 MLX5_FLEX_PARSER_ICMP_V6_ENABLED = 1 << 9, 1391 MLX5_FLEX_PARSER_GENEVE_TLV_OPTION_0_ENABLED = 1 << 10, 1392 MLX5_FLEX_PARSER_GTPU_ENABLED = 1 << 11, 1393 MLX5_FLEX_PARSER_GTPU_DW_2_ENABLED = 1 << 16, 1394 MLX5_FLEX_PARSER_GTPU_FIRST_EXT_DW_0_ENABLED = 1 << 17, 1395 MLX5_FLEX_PARSER_GTPU_DW_0_ENABLED = 1 << 18, 1396 MLX5_FLEX_PARSER_GTPU_TEID_ENABLED = 1 << 19, 1397 }; 1398 1399 enum { 1400 MLX5_UCTX_CAP_RAW_TX = 1UL << 0, 1401 MLX5_UCTX_CAP_INTERNAL_DEV_RES = 1UL << 1, 1402 }; 1403 1404 #define MLX5_FC_BULK_SIZE_FACTOR 128 1405 1406 enum mlx5_fc_bulk_alloc_bitmask { 1407 MLX5_FC_BULK_128 = (1 << 0), 1408 MLX5_FC_BULK_256 = (1 << 1), 1409 MLX5_FC_BULK_512 = (1 << 2), 1410 MLX5_FC_BULK_1024 = (1 << 3), 1411 MLX5_FC_BULK_2048 = (1 << 4), 1412 MLX5_FC_BULK_4096 = (1 << 5), 1413 MLX5_FC_BULK_8192 = (1 << 6), 1414 MLX5_FC_BULK_16384 = (1 << 7), 1415 }; 1416 1417 #define MLX5_FC_BULK_NUM_FCS(fc_enum) (MLX5_FC_BULK_SIZE_FACTOR * (fc_enum)) 1418 1419 #define MLX5_FT_MAX_MULTIPATH_LEVEL 63 1420 1421 enum { 1422 MLX5_STEERING_FORMAT_CONNECTX_5 = 0, 1423 MLX5_STEERING_FORMAT_CONNECTX_6DX = 1, 1424 MLX5_STEERING_FORMAT_CONNECTX_7 = 2, 1425 }; 1426 1427 struct mlx5_ifc_cmd_hca_cap_bits { 1428 u8 reserved_at_0[0x10]; 1429 u8 shared_object_to_user_object_allowed[0x1]; 1430 u8 reserved_at_13[0xe]; 1431 u8 vhca_resource_manager[0x1]; 1432 1433 u8 hca_cap_2[0x1]; 1434 u8 create_lag_when_not_master_up[0x1]; 1435 u8 dtor[0x1]; 1436 u8 event_on_vhca_state_teardown_request[0x1]; 1437 u8 event_on_vhca_state_in_use[0x1]; 1438 u8 event_on_vhca_state_active[0x1]; 1439 u8 event_on_vhca_state_allocated[0x1]; 1440 u8 event_on_vhca_state_invalid[0x1]; 1441 u8 reserved_at_28[0x8]; 1442 u8 vhca_id[0x10]; 1443 1444 u8 reserved_at_40[0x40]; 1445 1446 u8 log_max_srq_sz[0x8]; 1447 u8 log_max_qp_sz[0x8]; 1448 u8 event_cap[0x1]; 1449 u8 reserved_at_91[0x2]; 1450 u8 isolate_vl_tc_new[0x1]; 1451 u8 reserved_at_94[0x4]; 1452 u8 prio_tag_required[0x1]; 1453 u8 reserved_at_99[0x2]; 1454 u8 log_max_qp[0x5]; 1455 1456 u8 reserved_at_a0[0x3]; 1457 u8 ece_support[0x1]; 1458 u8 reserved_at_a4[0x5]; 1459 u8 reg_c_preserve[0x1]; 1460 u8 reserved_at_aa[0x1]; 1461 u8 log_max_srq[0x5]; 1462 u8 reserved_at_b0[0x1]; 1463 u8 uplink_follow[0x1]; 1464 u8 ts_cqe_to_dest_cqn[0x1]; 1465 u8 reserved_at_b3[0x7]; 1466 u8 shampo[0x1]; 1467 u8 reserved_at_bb[0x5]; 1468 1469 u8 max_sgl_for_optimized_performance[0x8]; 1470 u8 log_max_cq_sz[0x8]; 1471 u8 relaxed_ordering_write_umr[0x1]; 1472 u8 relaxed_ordering_read_umr[0x1]; 1473 u8 reserved_at_d2[0x7]; 1474 u8 virtio_net_device_emualtion_manager[0x1]; 1475 u8 virtio_blk_device_emualtion_manager[0x1]; 1476 u8 log_max_cq[0x5]; 1477 1478 u8 log_max_eq_sz[0x8]; 1479 u8 relaxed_ordering_write[0x1]; 1480 u8 relaxed_ordering_read[0x1]; 1481 u8 log_max_mkey[0x6]; 1482 u8 reserved_at_f0[0x8]; 1483 u8 dump_fill_mkey[0x1]; 1484 u8 reserved_at_f9[0x2]; 1485 u8 fast_teardown[0x1]; 1486 u8 log_max_eq[0x4]; 1487 1488 u8 max_indirection[0x8]; 1489 u8 fixed_buffer_size[0x1]; 1490 u8 log_max_mrw_sz[0x7]; 1491 u8 force_teardown[0x1]; 1492 u8 reserved_at_111[0x1]; 1493 u8 log_max_bsf_list_size[0x6]; 1494 u8 umr_extended_translation_offset[0x1]; 1495 u8 null_mkey[0x1]; 1496 u8 log_max_klm_list_size[0x6]; 1497 1498 u8 reserved_at_120[0xa]; 1499 u8 log_max_ra_req_dc[0x6]; 1500 u8 reserved_at_130[0x2]; 1501 u8 eth_wqe_too_small[0x1]; 1502 u8 reserved_at_133[0x6]; 1503 u8 vnic_env_cq_overrun[0x1]; 1504 u8 log_max_ra_res_dc[0x6]; 1505 1506 u8 reserved_at_140[0x5]; 1507 u8 release_all_pages[0x1]; 1508 u8 must_not_use[0x1]; 1509 u8 reserved_at_147[0x2]; 1510 u8 roce_accl[0x1]; 1511 u8 log_max_ra_req_qp[0x6]; 1512 u8 reserved_at_150[0xa]; 1513 u8 log_max_ra_res_qp[0x6]; 1514 1515 u8 end_pad[0x1]; 1516 u8 cc_query_allowed[0x1]; 1517 u8 cc_modify_allowed[0x1]; 1518 u8 start_pad[0x1]; 1519 u8 cache_line_128byte[0x1]; 1520 u8 reserved_at_165[0x4]; 1521 u8 rts2rts_qp_counters_set_id[0x1]; 1522 u8 reserved_at_16a[0x2]; 1523 u8 vnic_env_int_rq_oob[0x1]; 1524 u8 sbcam_reg[0x1]; 1525 u8 reserved_at_16e[0x1]; 1526 u8 qcam_reg[0x1]; 1527 u8 gid_table_size[0x10]; 1528 1529 u8 out_of_seq_cnt[0x1]; 1530 u8 vport_counters[0x1]; 1531 u8 retransmission_q_counters[0x1]; 1532 u8 debug[0x1]; 1533 u8 modify_rq_counter_set_id[0x1]; 1534 u8 rq_delay_drop[0x1]; 1535 u8 max_qp_cnt[0xa]; 1536 u8 pkey_table_size[0x10]; 1537 1538 u8 vport_group_manager[0x1]; 1539 u8 vhca_group_manager[0x1]; 1540 u8 ib_virt[0x1]; 1541 u8 eth_virt[0x1]; 1542 u8 vnic_env_queue_counters[0x1]; 1543 u8 ets[0x1]; 1544 u8 nic_flow_table[0x1]; 1545 u8 eswitch_manager[0x1]; 1546 u8 device_memory[0x1]; 1547 u8 mcam_reg[0x1]; 1548 u8 pcam_reg[0x1]; 1549 u8 local_ca_ack_delay[0x5]; 1550 u8 port_module_event[0x1]; 1551 u8 enhanced_error_q_counters[0x1]; 1552 u8 ports_check[0x1]; 1553 u8 reserved_at_1b3[0x1]; 1554 u8 disable_link_up[0x1]; 1555 u8 beacon_led[0x1]; 1556 u8 port_type[0x2]; 1557 u8 num_ports[0x8]; 1558 1559 u8 reserved_at_1c0[0x1]; 1560 u8 pps[0x1]; 1561 u8 pps_modify[0x1]; 1562 u8 log_max_msg[0x5]; 1563 u8 reserved_at_1c8[0x4]; 1564 u8 max_tc[0x4]; 1565 u8 temp_warn_event[0x1]; 1566 u8 dcbx[0x1]; 1567 u8 general_notification_event[0x1]; 1568 u8 reserved_at_1d3[0x2]; 1569 u8 fpga[0x1]; 1570 u8 rol_s[0x1]; 1571 u8 rol_g[0x1]; 1572 u8 reserved_at_1d8[0x1]; 1573 u8 wol_s[0x1]; 1574 u8 wol_g[0x1]; 1575 u8 wol_a[0x1]; 1576 u8 wol_b[0x1]; 1577 u8 wol_m[0x1]; 1578 u8 wol_u[0x1]; 1579 u8 wol_p[0x1]; 1580 1581 u8 stat_rate_support[0x10]; 1582 u8 reserved_at_1f0[0x1]; 1583 u8 pci_sync_for_fw_update_event[0x1]; 1584 u8 reserved_at_1f2[0x6]; 1585 u8 init2_lag_tx_port_affinity[0x1]; 1586 u8 reserved_at_1fa[0x3]; 1587 u8 cqe_version[0x4]; 1588 1589 u8 compact_address_vector[0x1]; 1590 u8 striding_rq[0x1]; 1591 u8 reserved_at_202[0x1]; 1592 u8 ipoib_enhanced_offloads[0x1]; 1593 u8 ipoib_basic_offloads[0x1]; 1594 u8 reserved_at_205[0x1]; 1595 u8 repeated_block_disabled[0x1]; 1596 u8 umr_modify_entity_size_disabled[0x1]; 1597 u8 umr_modify_atomic_disabled[0x1]; 1598 u8 umr_indirect_mkey_disabled[0x1]; 1599 u8 umr_fence[0x2]; 1600 u8 dc_req_scat_data_cqe[0x1]; 1601 u8 reserved_at_20d[0x2]; 1602 u8 drain_sigerr[0x1]; 1603 u8 cmdif_checksum[0x2]; 1604 u8 sigerr_cqe[0x1]; 1605 u8 reserved_at_213[0x1]; 1606 u8 wq_signature[0x1]; 1607 u8 sctr_data_cqe[0x1]; 1608 u8 reserved_at_216[0x1]; 1609 u8 sho[0x1]; 1610 u8 tph[0x1]; 1611 u8 rf[0x1]; 1612 u8 dct[0x1]; 1613 u8 qos[0x1]; 1614 u8 eth_net_offloads[0x1]; 1615 u8 roce[0x1]; 1616 u8 atomic[0x1]; 1617 u8 reserved_at_21f[0x1]; 1618 1619 u8 cq_oi[0x1]; 1620 u8 cq_resize[0x1]; 1621 u8 cq_moderation[0x1]; 1622 u8 reserved_at_223[0x3]; 1623 u8 cq_eq_remap[0x1]; 1624 u8 pg[0x1]; 1625 u8 block_lb_mc[0x1]; 1626 u8 reserved_at_229[0x1]; 1627 u8 scqe_break_moderation[0x1]; 1628 u8 cq_period_start_from_cqe[0x1]; 1629 u8 cd[0x1]; 1630 u8 reserved_at_22d[0x1]; 1631 u8 apm[0x1]; 1632 u8 vector_calc[0x1]; 1633 u8 umr_ptr_rlky[0x1]; 1634 u8 imaicl[0x1]; 1635 u8 qp_packet_based[0x1]; 1636 u8 reserved_at_233[0x3]; 1637 u8 qkv[0x1]; 1638 u8 pkv[0x1]; 1639 u8 set_deth_sqpn[0x1]; 1640 u8 reserved_at_239[0x3]; 1641 u8 xrc[0x1]; 1642 u8 ud[0x1]; 1643 u8 uc[0x1]; 1644 u8 rc[0x1]; 1645 1646 u8 uar_4k[0x1]; 1647 u8 reserved_at_241[0x9]; 1648 u8 uar_sz[0x6]; 1649 u8 port_selection_cap[0x1]; 1650 u8 reserved_at_248[0x1]; 1651 u8 umem_uid_0[0x1]; 1652 u8 reserved_at_250[0x5]; 1653 u8 log_pg_sz[0x8]; 1654 1655 u8 bf[0x1]; 1656 u8 driver_version[0x1]; 1657 u8 pad_tx_eth_packet[0x1]; 1658 u8 reserved_at_263[0x3]; 1659 u8 mkey_by_name[0x1]; 1660 u8 reserved_at_267[0x4]; 1661 1662 u8 log_bf_reg_size[0x5]; 1663 1664 u8 reserved_at_270[0x6]; 1665 u8 lag_dct[0x2]; 1666 u8 lag_tx_port_affinity[0x1]; 1667 u8 lag_native_fdb_selection[0x1]; 1668 u8 reserved_at_27a[0x1]; 1669 u8 lag_master[0x1]; 1670 u8 num_lag_ports[0x4]; 1671 1672 u8 reserved_at_280[0x10]; 1673 u8 max_wqe_sz_sq[0x10]; 1674 1675 u8 reserved_at_2a0[0x10]; 1676 u8 max_wqe_sz_rq[0x10]; 1677 1678 u8 max_flow_counter_31_16[0x10]; 1679 u8 max_wqe_sz_sq_dc[0x10]; 1680 1681 u8 reserved_at_2e0[0x7]; 1682 u8 max_qp_mcg[0x19]; 1683 1684 u8 reserved_at_300[0x10]; 1685 u8 flow_counter_bulk_alloc[0x8]; 1686 u8 log_max_mcg[0x8]; 1687 1688 u8 reserved_at_320[0x3]; 1689 u8 log_max_transport_domain[0x5]; 1690 u8 reserved_at_328[0x3]; 1691 u8 log_max_pd[0x5]; 1692 u8 reserved_at_330[0xb]; 1693 u8 log_max_xrcd[0x5]; 1694 1695 u8 nic_receive_steering_discard[0x1]; 1696 u8 receive_discard_vport_down[0x1]; 1697 u8 transmit_discard_vport_down[0x1]; 1698 u8 eq_overrun_count[0x1]; 1699 u8 reserved_at_344[0x1]; 1700 u8 invalid_command_count[0x1]; 1701 u8 quota_exceeded_count[0x1]; 1702 u8 reserved_at_347[0x1]; 1703 u8 log_max_flow_counter_bulk[0x8]; 1704 u8 max_flow_counter_15_0[0x10]; 1705 1706 1707 u8 reserved_at_360[0x3]; 1708 u8 log_max_rq[0x5]; 1709 u8 reserved_at_368[0x3]; 1710 u8 log_max_sq[0x5]; 1711 u8 reserved_at_370[0x3]; 1712 u8 log_max_tir[0x5]; 1713 u8 reserved_at_378[0x3]; 1714 u8 log_max_tis[0x5]; 1715 1716 u8 basic_cyclic_rcv_wqe[0x1]; 1717 u8 reserved_at_381[0x2]; 1718 u8 log_max_rmp[0x5]; 1719 u8 reserved_at_388[0x3]; 1720 u8 log_max_rqt[0x5]; 1721 u8 reserved_at_390[0x3]; 1722 u8 log_max_rqt_size[0x5]; 1723 u8 reserved_at_398[0x3]; 1724 u8 log_max_tis_per_sq[0x5]; 1725 1726 u8 ext_stride_num_range[0x1]; 1727 u8 roce_rw_supported[0x1]; 1728 u8 log_max_current_uc_list_wr_supported[0x1]; 1729 u8 log_max_stride_sz_rq[0x5]; 1730 u8 reserved_at_3a8[0x3]; 1731 u8 log_min_stride_sz_rq[0x5]; 1732 u8 reserved_at_3b0[0x3]; 1733 u8 log_max_stride_sz_sq[0x5]; 1734 u8 reserved_at_3b8[0x3]; 1735 u8 log_min_stride_sz_sq[0x5]; 1736 1737 u8 hairpin[0x1]; 1738 u8 reserved_at_3c1[0x2]; 1739 u8 log_max_hairpin_queues[0x5]; 1740 u8 reserved_at_3c8[0x3]; 1741 u8 log_max_hairpin_wq_data_sz[0x5]; 1742 u8 reserved_at_3d0[0x3]; 1743 u8 log_max_hairpin_num_packets[0x5]; 1744 u8 reserved_at_3d8[0x3]; 1745 u8 log_max_wq_sz[0x5]; 1746 1747 u8 nic_vport_change_event[0x1]; 1748 u8 disable_local_lb_uc[0x1]; 1749 u8 disable_local_lb_mc[0x1]; 1750 u8 log_min_hairpin_wq_data_sz[0x5]; 1751 u8 reserved_at_3e8[0x2]; 1752 u8 vhca_state[0x1]; 1753 u8 log_max_vlan_list[0x5]; 1754 u8 reserved_at_3f0[0x3]; 1755 u8 log_max_current_mc_list[0x5]; 1756 u8 reserved_at_3f8[0x3]; 1757 u8 log_max_current_uc_list[0x5]; 1758 1759 u8 general_obj_types[0x40]; 1760 1761 u8 sq_ts_format[0x2]; 1762 u8 rq_ts_format[0x2]; 1763 u8 steering_format_version[0x4]; 1764 u8 create_qp_start_hint[0x18]; 1765 1766 u8 reserved_at_460[0x1]; 1767 u8 ats[0x1]; 1768 u8 reserved_at_462[0x1]; 1769 u8 log_max_uctx[0x5]; 1770 u8 reserved_at_468[0x2]; 1771 u8 ipsec_offload[0x1]; 1772 u8 log_max_umem[0x5]; 1773 u8 max_num_eqs[0x10]; 1774 1775 u8 reserved_at_480[0x1]; 1776 u8 tls_tx[0x1]; 1777 u8 tls_rx[0x1]; 1778 u8 log_max_l2_table[0x5]; 1779 u8 reserved_at_488[0x8]; 1780 u8 log_uar_page_sz[0x10]; 1781 1782 u8 reserved_at_4a0[0x20]; 1783 u8 device_frequency_mhz[0x20]; 1784 u8 device_frequency_khz[0x20]; 1785 1786 u8 reserved_at_500[0x20]; 1787 u8 num_of_uars_per_page[0x20]; 1788 1789 u8 flex_parser_protocols[0x20]; 1790 1791 u8 max_geneve_tlv_options[0x8]; 1792 u8 reserved_at_568[0x3]; 1793 u8 max_geneve_tlv_option_data_len[0x5]; 1794 u8 reserved_at_570[0x9]; 1795 u8 adv_virtualization[0x1]; 1796 u8 reserved_at_57a[0x6]; 1797 1798 u8 reserved_at_580[0xb]; 1799 u8 log_max_dci_stream_channels[0x5]; 1800 u8 reserved_at_590[0x3]; 1801 u8 log_max_dci_errored_streams[0x5]; 1802 u8 reserved_at_598[0x8]; 1803 1804 u8 reserved_at_5a0[0x10]; 1805 u8 enhanced_cqe_compression[0x1]; 1806 u8 reserved_at_5b1[0x2]; 1807 u8 log_max_dek[0x5]; 1808 u8 reserved_at_5b8[0x4]; 1809 u8 mini_cqe_resp_stride_index[0x1]; 1810 u8 cqe_128_always[0x1]; 1811 u8 cqe_compression_128[0x1]; 1812 u8 cqe_compression[0x1]; 1813 1814 u8 cqe_compression_timeout[0x10]; 1815 u8 cqe_compression_max_num[0x10]; 1816 1817 u8 reserved_at_5e0[0x8]; 1818 u8 flex_parser_id_gtpu_dw_0[0x4]; 1819 u8 reserved_at_5ec[0x4]; 1820 u8 tag_matching[0x1]; 1821 u8 rndv_offload_rc[0x1]; 1822 u8 rndv_offload_dc[0x1]; 1823 u8 log_tag_matching_list_sz[0x5]; 1824 u8 reserved_at_5f8[0x3]; 1825 u8 log_max_xrq[0x5]; 1826 1827 u8 affiliate_nic_vport_criteria[0x8]; 1828 u8 native_port_num[0x8]; 1829 u8 num_vhca_ports[0x8]; 1830 u8 flex_parser_id_gtpu_teid[0x4]; 1831 u8 reserved_at_61c[0x2]; 1832 u8 sw_owner_id[0x1]; 1833 u8 reserved_at_61f[0x1]; 1834 1835 u8 max_num_of_monitor_counters[0x10]; 1836 u8 num_ppcnt_monitor_counters[0x10]; 1837 1838 u8 max_num_sf[0x10]; 1839 u8 num_q_monitor_counters[0x10]; 1840 1841 u8 reserved_at_660[0x20]; 1842 1843 u8 sf[0x1]; 1844 u8 sf_set_partition[0x1]; 1845 u8 reserved_at_682[0x1]; 1846 u8 log_max_sf[0x5]; 1847 u8 apu[0x1]; 1848 u8 reserved_at_689[0x4]; 1849 u8 migration[0x1]; 1850 u8 reserved_at_68e[0x2]; 1851 u8 log_min_sf_size[0x8]; 1852 u8 max_num_sf_partitions[0x8]; 1853 1854 u8 uctx_cap[0x20]; 1855 1856 u8 reserved_at_6c0[0x4]; 1857 u8 flex_parser_id_geneve_tlv_option_0[0x4]; 1858 u8 flex_parser_id_icmp_dw1[0x4]; 1859 u8 flex_parser_id_icmp_dw0[0x4]; 1860 u8 flex_parser_id_icmpv6_dw1[0x4]; 1861 u8 flex_parser_id_icmpv6_dw0[0x4]; 1862 u8 flex_parser_id_outer_first_mpls_over_gre[0x4]; 1863 u8 flex_parser_id_outer_first_mpls_over_udp_label[0x4]; 1864 1865 u8 max_num_match_definer[0x10]; 1866 u8 sf_base_id[0x10]; 1867 1868 u8 flex_parser_id_gtpu_dw_2[0x4]; 1869 u8 flex_parser_id_gtpu_first_ext_dw_0[0x4]; 1870 u8 num_total_dynamic_vf_msix[0x18]; 1871 u8 reserved_at_720[0x14]; 1872 u8 dynamic_msix_table_size[0xc]; 1873 u8 reserved_at_740[0xc]; 1874 u8 min_dynamic_vf_msix_table_size[0x4]; 1875 u8 reserved_at_750[0x4]; 1876 u8 max_dynamic_vf_msix_table_size[0xc]; 1877 1878 u8 reserved_at_760[0x20]; 1879 u8 vhca_tunnel_commands[0x40]; 1880 u8 match_definer_format_supported[0x40]; 1881 }; 1882 1883 struct mlx5_ifc_cmd_hca_cap_2_bits { 1884 u8 reserved_at_0[0x80]; 1885 1886 u8 migratable[0x1]; 1887 u8 reserved_at_81[0x1f]; 1888 1889 u8 max_reformat_insert_size[0x8]; 1890 u8 max_reformat_insert_offset[0x8]; 1891 u8 max_reformat_remove_size[0x8]; 1892 u8 max_reformat_remove_offset[0x8]; 1893 1894 u8 reserved_at_c0[0xe0]; 1895 1896 u8 reserved_at_1a0[0xb]; 1897 u8 log_min_mkey_entity_size[0x5]; 1898 u8 reserved_at_1b0[0x10]; 1899 1900 u8 reserved_at_1c0[0x60]; 1901 1902 u8 reserved_at_220[0x1]; 1903 u8 sw_vhca_id_valid[0x1]; 1904 u8 sw_vhca_id[0xe]; 1905 u8 reserved_at_230[0x10]; 1906 1907 u8 reserved_at_240[0xb]; 1908 u8 ts_cqe_metadata_size2wqe_counter[0x5]; 1909 u8 reserved_at_250[0x10]; 1910 1911 u8 reserved_at_260[0x5a0]; 1912 }; 1913 1914 enum mlx5_ifc_flow_destination_type { 1915 MLX5_IFC_FLOW_DESTINATION_TYPE_VPORT = 0x0, 1916 MLX5_IFC_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1, 1917 MLX5_IFC_FLOW_DESTINATION_TYPE_TIR = 0x2, 1918 MLX5_IFC_FLOW_DESTINATION_TYPE_FLOW_SAMPLER = 0x6, 1919 MLX5_IFC_FLOW_DESTINATION_TYPE_UPLINK = 0x8, 1920 }; 1921 1922 enum mlx5_flow_table_miss_action { 1923 MLX5_FLOW_TABLE_MISS_ACTION_DEF, 1924 MLX5_FLOW_TABLE_MISS_ACTION_FWD, 1925 MLX5_FLOW_TABLE_MISS_ACTION_SWITCH_DOMAIN, 1926 }; 1927 1928 struct mlx5_ifc_dest_format_struct_bits { 1929 u8 destination_type[0x8]; 1930 u8 destination_id[0x18]; 1931 1932 u8 destination_eswitch_owner_vhca_id_valid[0x1]; 1933 u8 packet_reformat[0x1]; 1934 u8 reserved_at_22[0xe]; 1935 u8 destination_eswitch_owner_vhca_id[0x10]; 1936 }; 1937 1938 struct mlx5_ifc_flow_counter_list_bits { 1939 u8 flow_counter_id[0x20]; 1940 1941 u8 reserved_at_20[0x20]; 1942 }; 1943 1944 struct mlx5_ifc_extended_dest_format_bits { 1945 struct mlx5_ifc_dest_format_struct_bits destination_entry; 1946 1947 u8 packet_reformat_id[0x20]; 1948 1949 u8 reserved_at_60[0x20]; 1950 }; 1951 1952 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits { 1953 struct mlx5_ifc_extended_dest_format_bits extended_dest_format; 1954 struct mlx5_ifc_flow_counter_list_bits flow_counter_list; 1955 }; 1956 1957 struct mlx5_ifc_fte_match_param_bits { 1958 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers; 1959 1960 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters; 1961 1962 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers; 1963 1964 struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2; 1965 1966 struct mlx5_ifc_fte_match_set_misc3_bits misc_parameters_3; 1967 1968 struct mlx5_ifc_fte_match_set_misc4_bits misc_parameters_4; 1969 1970 struct mlx5_ifc_fte_match_set_misc5_bits misc_parameters_5; 1971 1972 u8 reserved_at_e00[0x200]; 1973 }; 1974 1975 enum { 1976 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0, 1977 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1, 1978 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2, 1979 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3, 1980 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4, 1981 }; 1982 1983 struct mlx5_ifc_rx_hash_field_select_bits { 1984 u8 l3_prot_type[0x1]; 1985 u8 l4_prot_type[0x1]; 1986 u8 selected_fields[0x1e]; 1987 }; 1988 1989 enum { 1990 MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0, 1991 MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1, 1992 }; 1993 1994 enum { 1995 MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0, 1996 MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1, 1997 }; 1998 1999 struct mlx5_ifc_wq_bits { 2000 u8 wq_type[0x4]; 2001 u8 wq_signature[0x1]; 2002 u8 end_padding_mode[0x2]; 2003 u8 cd_slave[0x1]; 2004 u8 reserved_at_8[0x18]; 2005 2006 u8 hds_skip_first_sge[0x1]; 2007 u8 log2_hds_buf_size[0x3]; 2008 u8 reserved_at_24[0x7]; 2009 u8 page_offset[0x5]; 2010 u8 lwm[0x10]; 2011 2012 u8 reserved_at_40[0x8]; 2013 u8 pd[0x18]; 2014 2015 u8 reserved_at_60[0x8]; 2016 u8 uar_page[0x18]; 2017 2018 u8 dbr_addr[0x40]; 2019 2020 u8 hw_counter[0x20]; 2021 2022 u8 sw_counter[0x20]; 2023 2024 u8 reserved_at_100[0xc]; 2025 u8 log_wq_stride[0x4]; 2026 u8 reserved_at_110[0x3]; 2027 u8 log_wq_pg_sz[0x5]; 2028 u8 reserved_at_118[0x3]; 2029 u8 log_wq_sz[0x5]; 2030 2031 u8 dbr_umem_valid[0x1]; 2032 u8 wq_umem_valid[0x1]; 2033 u8 reserved_at_122[0x1]; 2034 u8 log_hairpin_num_packets[0x5]; 2035 u8 reserved_at_128[0x3]; 2036 u8 log_hairpin_data_sz[0x5]; 2037 2038 u8 reserved_at_130[0x4]; 2039 u8 log_wqe_num_of_strides[0x4]; 2040 u8 two_byte_shift_en[0x1]; 2041 u8 reserved_at_139[0x4]; 2042 u8 log_wqe_stride_size[0x3]; 2043 2044 u8 reserved_at_140[0x80]; 2045 2046 u8 headers_mkey[0x20]; 2047 2048 u8 shampo_enable[0x1]; 2049 u8 reserved_at_1e1[0x4]; 2050 u8 log_reservation_size[0x3]; 2051 u8 reserved_at_1e8[0x5]; 2052 u8 log_max_num_of_packets_per_reservation[0x3]; 2053 u8 reserved_at_1f0[0x6]; 2054 u8 log_headers_entry_size[0x2]; 2055 u8 reserved_at_1f8[0x4]; 2056 u8 log_headers_buffer_entry_num[0x4]; 2057 2058 u8 reserved_at_200[0x400]; 2059 2060 struct mlx5_ifc_cmd_pas_bits pas[]; 2061 }; 2062 2063 struct mlx5_ifc_rq_num_bits { 2064 u8 reserved_at_0[0x8]; 2065 u8 rq_num[0x18]; 2066 }; 2067 2068 struct mlx5_ifc_mac_address_layout_bits { 2069 u8 reserved_at_0[0x10]; 2070 u8 mac_addr_47_32[0x10]; 2071 2072 u8 mac_addr_31_0[0x20]; 2073 }; 2074 2075 struct mlx5_ifc_vlan_layout_bits { 2076 u8 reserved_at_0[0x14]; 2077 u8 vlan[0x0c]; 2078 2079 u8 reserved_at_20[0x20]; 2080 }; 2081 2082 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits { 2083 u8 reserved_at_0[0xa0]; 2084 2085 u8 min_time_between_cnps[0x20]; 2086 2087 u8 reserved_at_c0[0x12]; 2088 u8 cnp_dscp[0x6]; 2089 u8 reserved_at_d8[0x4]; 2090 u8 cnp_prio_mode[0x1]; 2091 u8 cnp_802p_prio[0x3]; 2092 2093 u8 reserved_at_e0[0x720]; 2094 }; 2095 2096 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits { 2097 u8 reserved_at_0[0x60]; 2098 2099 u8 reserved_at_60[0x4]; 2100 u8 clamp_tgt_rate[0x1]; 2101 u8 reserved_at_65[0x3]; 2102 u8 clamp_tgt_rate_after_time_inc[0x1]; 2103 u8 reserved_at_69[0x17]; 2104 2105 u8 reserved_at_80[0x20]; 2106 2107 u8 rpg_time_reset[0x20]; 2108 2109 u8 rpg_byte_reset[0x20]; 2110 2111 u8 rpg_threshold[0x20]; 2112 2113 u8 rpg_max_rate[0x20]; 2114 2115 u8 rpg_ai_rate[0x20]; 2116 2117 u8 rpg_hai_rate[0x20]; 2118 2119 u8 rpg_gd[0x20]; 2120 2121 u8 rpg_min_dec_fac[0x20]; 2122 2123 u8 rpg_min_rate[0x20]; 2124 2125 u8 reserved_at_1c0[0xe0]; 2126 2127 u8 rate_to_set_on_first_cnp[0x20]; 2128 2129 u8 dce_tcp_g[0x20]; 2130 2131 u8 dce_tcp_rtt[0x20]; 2132 2133 u8 rate_reduce_monitor_period[0x20]; 2134 2135 u8 reserved_at_320[0x20]; 2136 2137 u8 initial_alpha_value[0x20]; 2138 2139 u8 reserved_at_360[0x4a0]; 2140 }; 2141 2142 struct mlx5_ifc_cong_control_802_1qau_rp_bits { 2143 u8 reserved_at_0[0x80]; 2144 2145 u8 rppp_max_rps[0x20]; 2146 2147 u8 rpg_time_reset[0x20]; 2148 2149 u8 rpg_byte_reset[0x20]; 2150 2151 u8 rpg_threshold[0x20]; 2152 2153 u8 rpg_max_rate[0x20]; 2154 2155 u8 rpg_ai_rate[0x20]; 2156 2157 u8 rpg_hai_rate[0x20]; 2158 2159 u8 rpg_gd[0x20]; 2160 2161 u8 rpg_min_dec_fac[0x20]; 2162 2163 u8 rpg_min_rate[0x20]; 2164 2165 u8 reserved_at_1c0[0x640]; 2166 }; 2167 2168 enum { 2169 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1, 2170 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2, 2171 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4, 2172 }; 2173 2174 struct mlx5_ifc_resize_field_select_bits { 2175 u8 resize_field_select[0x20]; 2176 }; 2177 2178 struct mlx5_ifc_resource_dump_bits { 2179 u8 more_dump[0x1]; 2180 u8 inline_dump[0x1]; 2181 u8 reserved_at_2[0xa]; 2182 u8 seq_num[0x4]; 2183 u8 segment_type[0x10]; 2184 2185 u8 reserved_at_20[0x10]; 2186 u8 vhca_id[0x10]; 2187 2188 u8 index1[0x20]; 2189 2190 u8 index2[0x20]; 2191 2192 u8 num_of_obj1[0x10]; 2193 u8 num_of_obj2[0x10]; 2194 2195 u8 reserved_at_a0[0x20]; 2196 2197 u8 device_opaque[0x40]; 2198 2199 u8 mkey[0x20]; 2200 2201 u8 size[0x20]; 2202 2203 u8 address[0x40]; 2204 2205 u8 inline_data[52][0x20]; 2206 }; 2207 2208 struct mlx5_ifc_resource_dump_menu_record_bits { 2209 u8 reserved_at_0[0x4]; 2210 u8 num_of_obj2_supports_active[0x1]; 2211 u8 num_of_obj2_supports_all[0x1]; 2212 u8 must_have_num_of_obj2[0x1]; 2213 u8 support_num_of_obj2[0x1]; 2214 u8 num_of_obj1_supports_active[0x1]; 2215 u8 num_of_obj1_supports_all[0x1]; 2216 u8 must_have_num_of_obj1[0x1]; 2217 u8 support_num_of_obj1[0x1]; 2218 u8 must_have_index2[0x1]; 2219 u8 support_index2[0x1]; 2220 u8 must_have_index1[0x1]; 2221 u8 support_index1[0x1]; 2222 u8 segment_type[0x10]; 2223 2224 u8 segment_name[4][0x20]; 2225 2226 u8 index1_name[4][0x20]; 2227 2228 u8 index2_name[4][0x20]; 2229 }; 2230 2231 struct mlx5_ifc_resource_dump_segment_header_bits { 2232 u8 length_dw[0x10]; 2233 u8 segment_type[0x10]; 2234 }; 2235 2236 struct mlx5_ifc_resource_dump_command_segment_bits { 2237 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2238 2239 u8 segment_called[0x10]; 2240 u8 vhca_id[0x10]; 2241 2242 u8 index1[0x20]; 2243 2244 u8 index2[0x20]; 2245 2246 u8 num_of_obj1[0x10]; 2247 u8 num_of_obj2[0x10]; 2248 }; 2249 2250 struct mlx5_ifc_resource_dump_error_segment_bits { 2251 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2252 2253 u8 reserved_at_20[0x10]; 2254 u8 syndrome_id[0x10]; 2255 2256 u8 reserved_at_40[0x40]; 2257 2258 u8 error[8][0x20]; 2259 }; 2260 2261 struct mlx5_ifc_resource_dump_info_segment_bits { 2262 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2263 2264 u8 reserved_at_20[0x18]; 2265 u8 dump_version[0x8]; 2266 2267 u8 hw_version[0x20]; 2268 2269 u8 fw_version[0x20]; 2270 }; 2271 2272 struct mlx5_ifc_resource_dump_menu_segment_bits { 2273 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2274 2275 u8 reserved_at_20[0x10]; 2276 u8 num_of_records[0x10]; 2277 2278 struct mlx5_ifc_resource_dump_menu_record_bits record[]; 2279 }; 2280 2281 struct mlx5_ifc_resource_dump_resource_segment_bits { 2282 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2283 2284 u8 reserved_at_20[0x20]; 2285 2286 u8 index1[0x20]; 2287 2288 u8 index2[0x20]; 2289 2290 u8 payload[][0x20]; 2291 }; 2292 2293 struct mlx5_ifc_resource_dump_terminate_segment_bits { 2294 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2295 }; 2296 2297 struct mlx5_ifc_menu_resource_dump_response_bits { 2298 struct mlx5_ifc_resource_dump_info_segment_bits info; 2299 struct mlx5_ifc_resource_dump_command_segment_bits cmd; 2300 struct mlx5_ifc_resource_dump_menu_segment_bits menu; 2301 struct mlx5_ifc_resource_dump_terminate_segment_bits terminate; 2302 }; 2303 2304 enum { 2305 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1, 2306 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2, 2307 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4, 2308 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8, 2309 }; 2310 2311 struct mlx5_ifc_modify_field_select_bits { 2312 u8 modify_field_select[0x20]; 2313 }; 2314 2315 struct mlx5_ifc_field_select_r_roce_np_bits { 2316 u8 field_select_r_roce_np[0x20]; 2317 }; 2318 2319 struct mlx5_ifc_field_select_r_roce_rp_bits { 2320 u8 field_select_r_roce_rp[0x20]; 2321 }; 2322 2323 enum { 2324 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4, 2325 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8, 2326 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10, 2327 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20, 2328 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40, 2329 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80, 2330 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100, 2331 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200, 2332 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400, 2333 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800, 2334 }; 2335 2336 struct mlx5_ifc_field_select_802_1qau_rp_bits { 2337 u8 field_select_8021qaurp[0x20]; 2338 }; 2339 2340 struct mlx5_ifc_phys_layer_cntrs_bits { 2341 u8 time_since_last_clear_high[0x20]; 2342 2343 u8 time_since_last_clear_low[0x20]; 2344 2345 u8 symbol_errors_high[0x20]; 2346 2347 u8 symbol_errors_low[0x20]; 2348 2349 u8 sync_headers_errors_high[0x20]; 2350 2351 u8 sync_headers_errors_low[0x20]; 2352 2353 u8 edpl_bip_errors_lane0_high[0x20]; 2354 2355 u8 edpl_bip_errors_lane0_low[0x20]; 2356 2357 u8 edpl_bip_errors_lane1_high[0x20]; 2358 2359 u8 edpl_bip_errors_lane1_low[0x20]; 2360 2361 u8 edpl_bip_errors_lane2_high[0x20]; 2362 2363 u8 edpl_bip_errors_lane2_low[0x20]; 2364 2365 u8 edpl_bip_errors_lane3_high[0x20]; 2366 2367 u8 edpl_bip_errors_lane3_low[0x20]; 2368 2369 u8 fc_fec_corrected_blocks_lane0_high[0x20]; 2370 2371 u8 fc_fec_corrected_blocks_lane0_low[0x20]; 2372 2373 u8 fc_fec_corrected_blocks_lane1_high[0x20]; 2374 2375 u8 fc_fec_corrected_blocks_lane1_low[0x20]; 2376 2377 u8 fc_fec_corrected_blocks_lane2_high[0x20]; 2378 2379 u8 fc_fec_corrected_blocks_lane2_low[0x20]; 2380 2381 u8 fc_fec_corrected_blocks_lane3_high[0x20]; 2382 2383 u8 fc_fec_corrected_blocks_lane3_low[0x20]; 2384 2385 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20]; 2386 2387 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20]; 2388 2389 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20]; 2390 2391 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20]; 2392 2393 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20]; 2394 2395 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20]; 2396 2397 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20]; 2398 2399 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20]; 2400 2401 u8 rs_fec_corrected_blocks_high[0x20]; 2402 2403 u8 rs_fec_corrected_blocks_low[0x20]; 2404 2405 u8 rs_fec_uncorrectable_blocks_high[0x20]; 2406 2407 u8 rs_fec_uncorrectable_blocks_low[0x20]; 2408 2409 u8 rs_fec_no_errors_blocks_high[0x20]; 2410 2411 u8 rs_fec_no_errors_blocks_low[0x20]; 2412 2413 u8 rs_fec_single_error_blocks_high[0x20]; 2414 2415 u8 rs_fec_single_error_blocks_low[0x20]; 2416 2417 u8 rs_fec_corrected_symbols_total_high[0x20]; 2418 2419 u8 rs_fec_corrected_symbols_total_low[0x20]; 2420 2421 u8 rs_fec_corrected_symbols_lane0_high[0x20]; 2422 2423 u8 rs_fec_corrected_symbols_lane0_low[0x20]; 2424 2425 u8 rs_fec_corrected_symbols_lane1_high[0x20]; 2426 2427 u8 rs_fec_corrected_symbols_lane1_low[0x20]; 2428 2429 u8 rs_fec_corrected_symbols_lane2_high[0x20]; 2430 2431 u8 rs_fec_corrected_symbols_lane2_low[0x20]; 2432 2433 u8 rs_fec_corrected_symbols_lane3_high[0x20]; 2434 2435 u8 rs_fec_corrected_symbols_lane3_low[0x20]; 2436 2437 u8 link_down_events[0x20]; 2438 2439 u8 successful_recovery_events[0x20]; 2440 2441 u8 reserved_at_640[0x180]; 2442 }; 2443 2444 struct mlx5_ifc_phys_layer_statistical_cntrs_bits { 2445 u8 time_since_last_clear_high[0x20]; 2446 2447 u8 time_since_last_clear_low[0x20]; 2448 2449 u8 phy_received_bits_high[0x20]; 2450 2451 u8 phy_received_bits_low[0x20]; 2452 2453 u8 phy_symbol_errors_high[0x20]; 2454 2455 u8 phy_symbol_errors_low[0x20]; 2456 2457 u8 phy_corrected_bits_high[0x20]; 2458 2459 u8 phy_corrected_bits_low[0x20]; 2460 2461 u8 phy_corrected_bits_lane0_high[0x20]; 2462 2463 u8 phy_corrected_bits_lane0_low[0x20]; 2464 2465 u8 phy_corrected_bits_lane1_high[0x20]; 2466 2467 u8 phy_corrected_bits_lane1_low[0x20]; 2468 2469 u8 phy_corrected_bits_lane2_high[0x20]; 2470 2471 u8 phy_corrected_bits_lane2_low[0x20]; 2472 2473 u8 phy_corrected_bits_lane3_high[0x20]; 2474 2475 u8 phy_corrected_bits_lane3_low[0x20]; 2476 2477 u8 reserved_at_200[0x5c0]; 2478 }; 2479 2480 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits { 2481 u8 symbol_error_counter[0x10]; 2482 2483 u8 link_error_recovery_counter[0x8]; 2484 2485 u8 link_downed_counter[0x8]; 2486 2487 u8 port_rcv_errors[0x10]; 2488 2489 u8 port_rcv_remote_physical_errors[0x10]; 2490 2491 u8 port_rcv_switch_relay_errors[0x10]; 2492 2493 u8 port_xmit_discards[0x10]; 2494 2495 u8 port_xmit_constraint_errors[0x8]; 2496 2497 u8 port_rcv_constraint_errors[0x8]; 2498 2499 u8 reserved_at_70[0x8]; 2500 2501 u8 link_overrun_errors[0x8]; 2502 2503 u8 reserved_at_80[0x10]; 2504 2505 u8 vl_15_dropped[0x10]; 2506 2507 u8 reserved_at_a0[0x80]; 2508 2509 u8 port_xmit_wait[0x20]; 2510 }; 2511 2512 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits { 2513 u8 transmit_queue_high[0x20]; 2514 2515 u8 transmit_queue_low[0x20]; 2516 2517 u8 no_buffer_discard_uc_high[0x20]; 2518 2519 u8 no_buffer_discard_uc_low[0x20]; 2520 2521 u8 reserved_at_80[0x740]; 2522 }; 2523 2524 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits { 2525 u8 wred_discard_high[0x20]; 2526 2527 u8 wred_discard_low[0x20]; 2528 2529 u8 ecn_marked_tc_high[0x20]; 2530 2531 u8 ecn_marked_tc_low[0x20]; 2532 2533 u8 reserved_at_80[0x740]; 2534 }; 2535 2536 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits { 2537 u8 rx_octets_high[0x20]; 2538 2539 u8 rx_octets_low[0x20]; 2540 2541 u8 reserved_at_40[0xc0]; 2542 2543 u8 rx_frames_high[0x20]; 2544 2545 u8 rx_frames_low[0x20]; 2546 2547 u8 tx_octets_high[0x20]; 2548 2549 u8 tx_octets_low[0x20]; 2550 2551 u8 reserved_at_180[0xc0]; 2552 2553 u8 tx_frames_high[0x20]; 2554 2555 u8 tx_frames_low[0x20]; 2556 2557 u8 rx_pause_high[0x20]; 2558 2559 u8 rx_pause_low[0x20]; 2560 2561 u8 rx_pause_duration_high[0x20]; 2562 2563 u8 rx_pause_duration_low[0x20]; 2564 2565 u8 tx_pause_high[0x20]; 2566 2567 u8 tx_pause_low[0x20]; 2568 2569 u8 tx_pause_duration_high[0x20]; 2570 2571 u8 tx_pause_duration_low[0x20]; 2572 2573 u8 rx_pause_transition_high[0x20]; 2574 2575 u8 rx_pause_transition_low[0x20]; 2576 2577 u8 rx_discards_high[0x20]; 2578 2579 u8 rx_discards_low[0x20]; 2580 2581 u8 device_stall_minor_watermark_cnt_high[0x20]; 2582 2583 u8 device_stall_minor_watermark_cnt_low[0x20]; 2584 2585 u8 device_stall_critical_watermark_cnt_high[0x20]; 2586 2587 u8 device_stall_critical_watermark_cnt_low[0x20]; 2588 2589 u8 reserved_at_480[0x340]; 2590 }; 2591 2592 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits { 2593 u8 port_transmit_wait_high[0x20]; 2594 2595 u8 port_transmit_wait_low[0x20]; 2596 2597 u8 reserved_at_40[0x100]; 2598 2599 u8 rx_buffer_almost_full_high[0x20]; 2600 2601 u8 rx_buffer_almost_full_low[0x20]; 2602 2603 u8 rx_buffer_full_high[0x20]; 2604 2605 u8 rx_buffer_full_low[0x20]; 2606 2607 u8 rx_icrc_encapsulated_high[0x20]; 2608 2609 u8 rx_icrc_encapsulated_low[0x20]; 2610 2611 u8 reserved_at_200[0x5c0]; 2612 }; 2613 2614 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits { 2615 u8 dot3stats_alignment_errors_high[0x20]; 2616 2617 u8 dot3stats_alignment_errors_low[0x20]; 2618 2619 u8 dot3stats_fcs_errors_high[0x20]; 2620 2621 u8 dot3stats_fcs_errors_low[0x20]; 2622 2623 u8 dot3stats_single_collision_frames_high[0x20]; 2624 2625 u8 dot3stats_single_collision_frames_low[0x20]; 2626 2627 u8 dot3stats_multiple_collision_frames_high[0x20]; 2628 2629 u8 dot3stats_multiple_collision_frames_low[0x20]; 2630 2631 u8 dot3stats_sqe_test_errors_high[0x20]; 2632 2633 u8 dot3stats_sqe_test_errors_low[0x20]; 2634 2635 u8 dot3stats_deferred_transmissions_high[0x20]; 2636 2637 u8 dot3stats_deferred_transmissions_low[0x20]; 2638 2639 u8 dot3stats_late_collisions_high[0x20]; 2640 2641 u8 dot3stats_late_collisions_low[0x20]; 2642 2643 u8 dot3stats_excessive_collisions_high[0x20]; 2644 2645 u8 dot3stats_excessive_collisions_low[0x20]; 2646 2647 u8 dot3stats_internal_mac_transmit_errors_high[0x20]; 2648 2649 u8 dot3stats_internal_mac_transmit_errors_low[0x20]; 2650 2651 u8 dot3stats_carrier_sense_errors_high[0x20]; 2652 2653 u8 dot3stats_carrier_sense_errors_low[0x20]; 2654 2655 u8 dot3stats_frame_too_longs_high[0x20]; 2656 2657 u8 dot3stats_frame_too_longs_low[0x20]; 2658 2659 u8 dot3stats_internal_mac_receive_errors_high[0x20]; 2660 2661 u8 dot3stats_internal_mac_receive_errors_low[0x20]; 2662 2663 u8 dot3stats_symbol_errors_high[0x20]; 2664 2665 u8 dot3stats_symbol_errors_low[0x20]; 2666 2667 u8 dot3control_in_unknown_opcodes_high[0x20]; 2668 2669 u8 dot3control_in_unknown_opcodes_low[0x20]; 2670 2671 u8 dot3in_pause_frames_high[0x20]; 2672 2673 u8 dot3in_pause_frames_low[0x20]; 2674 2675 u8 dot3out_pause_frames_high[0x20]; 2676 2677 u8 dot3out_pause_frames_low[0x20]; 2678 2679 u8 reserved_at_400[0x3c0]; 2680 }; 2681 2682 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits { 2683 u8 ether_stats_drop_events_high[0x20]; 2684 2685 u8 ether_stats_drop_events_low[0x20]; 2686 2687 u8 ether_stats_octets_high[0x20]; 2688 2689 u8 ether_stats_octets_low[0x20]; 2690 2691 u8 ether_stats_pkts_high[0x20]; 2692 2693 u8 ether_stats_pkts_low[0x20]; 2694 2695 u8 ether_stats_broadcast_pkts_high[0x20]; 2696 2697 u8 ether_stats_broadcast_pkts_low[0x20]; 2698 2699 u8 ether_stats_multicast_pkts_high[0x20]; 2700 2701 u8 ether_stats_multicast_pkts_low[0x20]; 2702 2703 u8 ether_stats_crc_align_errors_high[0x20]; 2704 2705 u8 ether_stats_crc_align_errors_low[0x20]; 2706 2707 u8 ether_stats_undersize_pkts_high[0x20]; 2708 2709 u8 ether_stats_undersize_pkts_low[0x20]; 2710 2711 u8 ether_stats_oversize_pkts_high[0x20]; 2712 2713 u8 ether_stats_oversize_pkts_low[0x20]; 2714 2715 u8 ether_stats_fragments_high[0x20]; 2716 2717 u8 ether_stats_fragments_low[0x20]; 2718 2719 u8 ether_stats_jabbers_high[0x20]; 2720 2721 u8 ether_stats_jabbers_low[0x20]; 2722 2723 u8 ether_stats_collisions_high[0x20]; 2724 2725 u8 ether_stats_collisions_low[0x20]; 2726 2727 u8 ether_stats_pkts64octets_high[0x20]; 2728 2729 u8 ether_stats_pkts64octets_low[0x20]; 2730 2731 u8 ether_stats_pkts65to127octets_high[0x20]; 2732 2733 u8 ether_stats_pkts65to127octets_low[0x20]; 2734 2735 u8 ether_stats_pkts128to255octets_high[0x20]; 2736 2737 u8 ether_stats_pkts128to255octets_low[0x20]; 2738 2739 u8 ether_stats_pkts256to511octets_high[0x20]; 2740 2741 u8 ether_stats_pkts256to511octets_low[0x20]; 2742 2743 u8 ether_stats_pkts512to1023octets_high[0x20]; 2744 2745 u8 ether_stats_pkts512to1023octets_low[0x20]; 2746 2747 u8 ether_stats_pkts1024to1518octets_high[0x20]; 2748 2749 u8 ether_stats_pkts1024to1518octets_low[0x20]; 2750 2751 u8 ether_stats_pkts1519to2047octets_high[0x20]; 2752 2753 u8 ether_stats_pkts1519to2047octets_low[0x20]; 2754 2755 u8 ether_stats_pkts2048to4095octets_high[0x20]; 2756 2757 u8 ether_stats_pkts2048to4095octets_low[0x20]; 2758 2759 u8 ether_stats_pkts4096to8191octets_high[0x20]; 2760 2761 u8 ether_stats_pkts4096to8191octets_low[0x20]; 2762 2763 u8 ether_stats_pkts8192to10239octets_high[0x20]; 2764 2765 u8 ether_stats_pkts8192to10239octets_low[0x20]; 2766 2767 u8 reserved_at_540[0x280]; 2768 }; 2769 2770 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits { 2771 u8 if_in_octets_high[0x20]; 2772 2773 u8 if_in_octets_low[0x20]; 2774 2775 u8 if_in_ucast_pkts_high[0x20]; 2776 2777 u8 if_in_ucast_pkts_low[0x20]; 2778 2779 u8 if_in_discards_high[0x20]; 2780 2781 u8 if_in_discards_low[0x20]; 2782 2783 u8 if_in_errors_high[0x20]; 2784 2785 u8 if_in_errors_low[0x20]; 2786 2787 u8 if_in_unknown_protos_high[0x20]; 2788 2789 u8 if_in_unknown_protos_low[0x20]; 2790 2791 u8 if_out_octets_high[0x20]; 2792 2793 u8 if_out_octets_low[0x20]; 2794 2795 u8 if_out_ucast_pkts_high[0x20]; 2796 2797 u8 if_out_ucast_pkts_low[0x20]; 2798 2799 u8 if_out_discards_high[0x20]; 2800 2801 u8 if_out_discards_low[0x20]; 2802 2803 u8 if_out_errors_high[0x20]; 2804 2805 u8 if_out_errors_low[0x20]; 2806 2807 u8 if_in_multicast_pkts_high[0x20]; 2808 2809 u8 if_in_multicast_pkts_low[0x20]; 2810 2811 u8 if_in_broadcast_pkts_high[0x20]; 2812 2813 u8 if_in_broadcast_pkts_low[0x20]; 2814 2815 u8 if_out_multicast_pkts_high[0x20]; 2816 2817 u8 if_out_multicast_pkts_low[0x20]; 2818 2819 u8 if_out_broadcast_pkts_high[0x20]; 2820 2821 u8 if_out_broadcast_pkts_low[0x20]; 2822 2823 u8 reserved_at_340[0x480]; 2824 }; 2825 2826 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits { 2827 u8 a_frames_transmitted_ok_high[0x20]; 2828 2829 u8 a_frames_transmitted_ok_low[0x20]; 2830 2831 u8 a_frames_received_ok_high[0x20]; 2832 2833 u8 a_frames_received_ok_low[0x20]; 2834 2835 u8 a_frame_check_sequence_errors_high[0x20]; 2836 2837 u8 a_frame_check_sequence_errors_low[0x20]; 2838 2839 u8 a_alignment_errors_high[0x20]; 2840 2841 u8 a_alignment_errors_low[0x20]; 2842 2843 u8 a_octets_transmitted_ok_high[0x20]; 2844 2845 u8 a_octets_transmitted_ok_low[0x20]; 2846 2847 u8 a_octets_received_ok_high[0x20]; 2848 2849 u8 a_octets_received_ok_low[0x20]; 2850 2851 u8 a_multicast_frames_xmitted_ok_high[0x20]; 2852 2853 u8 a_multicast_frames_xmitted_ok_low[0x20]; 2854 2855 u8 a_broadcast_frames_xmitted_ok_high[0x20]; 2856 2857 u8 a_broadcast_frames_xmitted_ok_low[0x20]; 2858 2859 u8 a_multicast_frames_received_ok_high[0x20]; 2860 2861 u8 a_multicast_frames_received_ok_low[0x20]; 2862 2863 u8 a_broadcast_frames_received_ok_high[0x20]; 2864 2865 u8 a_broadcast_frames_received_ok_low[0x20]; 2866 2867 u8 a_in_range_length_errors_high[0x20]; 2868 2869 u8 a_in_range_length_errors_low[0x20]; 2870 2871 u8 a_out_of_range_length_field_high[0x20]; 2872 2873 u8 a_out_of_range_length_field_low[0x20]; 2874 2875 u8 a_frame_too_long_errors_high[0x20]; 2876 2877 u8 a_frame_too_long_errors_low[0x20]; 2878 2879 u8 a_symbol_error_during_carrier_high[0x20]; 2880 2881 u8 a_symbol_error_during_carrier_low[0x20]; 2882 2883 u8 a_mac_control_frames_transmitted_high[0x20]; 2884 2885 u8 a_mac_control_frames_transmitted_low[0x20]; 2886 2887 u8 a_mac_control_frames_received_high[0x20]; 2888 2889 u8 a_mac_control_frames_received_low[0x20]; 2890 2891 u8 a_unsupported_opcodes_received_high[0x20]; 2892 2893 u8 a_unsupported_opcodes_received_low[0x20]; 2894 2895 u8 a_pause_mac_ctrl_frames_received_high[0x20]; 2896 2897 u8 a_pause_mac_ctrl_frames_received_low[0x20]; 2898 2899 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20]; 2900 2901 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20]; 2902 2903 u8 reserved_at_4c0[0x300]; 2904 }; 2905 2906 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits { 2907 u8 life_time_counter_high[0x20]; 2908 2909 u8 life_time_counter_low[0x20]; 2910 2911 u8 rx_errors[0x20]; 2912 2913 u8 tx_errors[0x20]; 2914 2915 u8 l0_to_recovery_eieos[0x20]; 2916 2917 u8 l0_to_recovery_ts[0x20]; 2918 2919 u8 l0_to_recovery_framing[0x20]; 2920 2921 u8 l0_to_recovery_retrain[0x20]; 2922 2923 u8 crc_error_dllp[0x20]; 2924 2925 u8 crc_error_tlp[0x20]; 2926 2927 u8 tx_overflow_buffer_pkt_high[0x20]; 2928 2929 u8 tx_overflow_buffer_pkt_low[0x20]; 2930 2931 u8 outbound_stalled_reads[0x20]; 2932 2933 u8 outbound_stalled_writes[0x20]; 2934 2935 u8 outbound_stalled_reads_events[0x20]; 2936 2937 u8 outbound_stalled_writes_events[0x20]; 2938 2939 u8 reserved_at_200[0x5c0]; 2940 }; 2941 2942 struct mlx5_ifc_cmd_inter_comp_event_bits { 2943 u8 command_completion_vector[0x20]; 2944 2945 u8 reserved_at_20[0xc0]; 2946 }; 2947 2948 struct mlx5_ifc_stall_vl_event_bits { 2949 u8 reserved_at_0[0x18]; 2950 u8 port_num[0x1]; 2951 u8 reserved_at_19[0x3]; 2952 u8 vl[0x4]; 2953 2954 u8 reserved_at_20[0xa0]; 2955 }; 2956 2957 struct mlx5_ifc_db_bf_congestion_event_bits { 2958 u8 event_subtype[0x8]; 2959 u8 reserved_at_8[0x8]; 2960 u8 congestion_level[0x8]; 2961 u8 reserved_at_18[0x8]; 2962 2963 u8 reserved_at_20[0xa0]; 2964 }; 2965 2966 struct mlx5_ifc_gpio_event_bits { 2967 u8 reserved_at_0[0x60]; 2968 2969 u8 gpio_event_hi[0x20]; 2970 2971 u8 gpio_event_lo[0x20]; 2972 2973 u8 reserved_at_a0[0x40]; 2974 }; 2975 2976 struct mlx5_ifc_port_state_change_event_bits { 2977 u8 reserved_at_0[0x40]; 2978 2979 u8 port_num[0x4]; 2980 u8 reserved_at_44[0x1c]; 2981 2982 u8 reserved_at_60[0x80]; 2983 }; 2984 2985 struct mlx5_ifc_dropped_packet_logged_bits { 2986 u8 reserved_at_0[0xe0]; 2987 }; 2988 2989 struct mlx5_ifc_default_timeout_bits { 2990 u8 to_multiplier[0x3]; 2991 u8 reserved_at_3[0x9]; 2992 u8 to_value[0x14]; 2993 }; 2994 2995 struct mlx5_ifc_dtor_reg_bits { 2996 u8 reserved_at_0[0x20]; 2997 2998 struct mlx5_ifc_default_timeout_bits pcie_toggle_to; 2999 3000 u8 reserved_at_40[0x60]; 3001 3002 struct mlx5_ifc_default_timeout_bits health_poll_to; 3003 3004 struct mlx5_ifc_default_timeout_bits full_crdump_to; 3005 3006 struct mlx5_ifc_default_timeout_bits fw_reset_to; 3007 3008 struct mlx5_ifc_default_timeout_bits flush_on_err_to; 3009 3010 struct mlx5_ifc_default_timeout_bits pci_sync_update_to; 3011 3012 struct mlx5_ifc_default_timeout_bits tear_down_to; 3013 3014 struct mlx5_ifc_default_timeout_bits fsm_reactivate_to; 3015 3016 struct mlx5_ifc_default_timeout_bits reclaim_pages_to; 3017 3018 struct mlx5_ifc_default_timeout_bits reclaim_vfs_pages_to; 3019 3020 u8 reserved_at_1c0[0x40]; 3021 }; 3022 3023 enum { 3024 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1, 3025 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2, 3026 }; 3027 3028 struct mlx5_ifc_cq_error_bits { 3029 u8 reserved_at_0[0x8]; 3030 u8 cqn[0x18]; 3031 3032 u8 reserved_at_20[0x20]; 3033 3034 u8 reserved_at_40[0x18]; 3035 u8 syndrome[0x8]; 3036 3037 u8 reserved_at_60[0x80]; 3038 }; 3039 3040 struct mlx5_ifc_rdma_page_fault_event_bits { 3041 u8 bytes_committed[0x20]; 3042 3043 u8 r_key[0x20]; 3044 3045 u8 reserved_at_40[0x10]; 3046 u8 packet_len[0x10]; 3047 3048 u8 rdma_op_len[0x20]; 3049 3050 u8 rdma_va[0x40]; 3051 3052 u8 reserved_at_c0[0x5]; 3053 u8 rdma[0x1]; 3054 u8 write[0x1]; 3055 u8 requestor[0x1]; 3056 u8 qp_number[0x18]; 3057 }; 3058 3059 struct mlx5_ifc_wqe_associated_page_fault_event_bits { 3060 u8 bytes_committed[0x20]; 3061 3062 u8 reserved_at_20[0x10]; 3063 u8 wqe_index[0x10]; 3064 3065 u8 reserved_at_40[0x10]; 3066 u8 len[0x10]; 3067 3068 u8 reserved_at_60[0x60]; 3069 3070 u8 reserved_at_c0[0x5]; 3071 u8 rdma[0x1]; 3072 u8 write_read[0x1]; 3073 u8 requestor[0x1]; 3074 u8 qpn[0x18]; 3075 }; 3076 3077 struct mlx5_ifc_qp_events_bits { 3078 u8 reserved_at_0[0xa0]; 3079 3080 u8 type[0x8]; 3081 u8 reserved_at_a8[0x18]; 3082 3083 u8 reserved_at_c0[0x8]; 3084 u8 qpn_rqn_sqn[0x18]; 3085 }; 3086 3087 struct mlx5_ifc_dct_events_bits { 3088 u8 reserved_at_0[0xc0]; 3089 3090 u8 reserved_at_c0[0x8]; 3091 u8 dct_number[0x18]; 3092 }; 3093 3094 struct mlx5_ifc_comp_event_bits { 3095 u8 reserved_at_0[0xc0]; 3096 3097 u8 reserved_at_c0[0x8]; 3098 u8 cq_number[0x18]; 3099 }; 3100 3101 enum { 3102 MLX5_QPC_STATE_RST = 0x0, 3103 MLX5_QPC_STATE_INIT = 0x1, 3104 MLX5_QPC_STATE_RTR = 0x2, 3105 MLX5_QPC_STATE_RTS = 0x3, 3106 MLX5_QPC_STATE_SQER = 0x4, 3107 MLX5_QPC_STATE_ERR = 0x6, 3108 MLX5_QPC_STATE_SQD = 0x7, 3109 MLX5_QPC_STATE_SUSPENDED = 0x9, 3110 }; 3111 3112 enum { 3113 MLX5_QPC_ST_RC = 0x0, 3114 MLX5_QPC_ST_UC = 0x1, 3115 MLX5_QPC_ST_UD = 0x2, 3116 MLX5_QPC_ST_XRC = 0x3, 3117 MLX5_QPC_ST_DCI = 0x5, 3118 MLX5_QPC_ST_QP0 = 0x7, 3119 MLX5_QPC_ST_QP1 = 0x8, 3120 MLX5_QPC_ST_RAW_DATAGRAM = 0x9, 3121 MLX5_QPC_ST_REG_UMR = 0xc, 3122 }; 3123 3124 enum { 3125 MLX5_QPC_PM_STATE_ARMED = 0x0, 3126 MLX5_QPC_PM_STATE_REARM = 0x1, 3127 MLX5_QPC_PM_STATE_RESERVED = 0x2, 3128 MLX5_QPC_PM_STATE_MIGRATED = 0x3, 3129 }; 3130 3131 enum { 3132 MLX5_QPC_OFFLOAD_TYPE_RNDV = 0x1, 3133 }; 3134 3135 enum { 3136 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0, 3137 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1, 3138 }; 3139 3140 enum { 3141 MLX5_QPC_MTU_256_BYTES = 0x1, 3142 MLX5_QPC_MTU_512_BYTES = 0x2, 3143 MLX5_QPC_MTU_1K_BYTES = 0x3, 3144 MLX5_QPC_MTU_2K_BYTES = 0x4, 3145 MLX5_QPC_MTU_4K_BYTES = 0x5, 3146 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7, 3147 }; 3148 3149 enum { 3150 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1, 3151 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2, 3152 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3, 3153 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4, 3154 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5, 3155 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6, 3156 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7, 3157 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8, 3158 }; 3159 3160 enum { 3161 MLX5_QPC_CS_REQ_DISABLE = 0x0, 3162 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11, 3163 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22, 3164 }; 3165 3166 enum { 3167 MLX5_QPC_CS_RES_DISABLE = 0x0, 3168 MLX5_QPC_CS_RES_UP_TO_32B = 0x1, 3169 MLX5_QPC_CS_RES_UP_TO_64B = 0x2, 3170 }; 3171 3172 enum { 3173 MLX5_TIMESTAMP_FORMAT_FREE_RUNNING = 0x0, 3174 MLX5_TIMESTAMP_FORMAT_DEFAULT = 0x1, 3175 MLX5_TIMESTAMP_FORMAT_REAL_TIME = 0x2, 3176 }; 3177 3178 struct mlx5_ifc_qpc_bits { 3179 u8 state[0x4]; 3180 u8 lag_tx_port_affinity[0x4]; 3181 u8 st[0x8]; 3182 u8 reserved_at_10[0x2]; 3183 u8 isolate_vl_tc[0x1]; 3184 u8 pm_state[0x2]; 3185 u8 reserved_at_15[0x1]; 3186 u8 req_e2e_credit_mode[0x2]; 3187 u8 offload_type[0x4]; 3188 u8 end_padding_mode[0x2]; 3189 u8 reserved_at_1e[0x2]; 3190 3191 u8 wq_signature[0x1]; 3192 u8 block_lb_mc[0x1]; 3193 u8 atomic_like_write_en[0x1]; 3194 u8 latency_sensitive[0x1]; 3195 u8 reserved_at_24[0x1]; 3196 u8 drain_sigerr[0x1]; 3197 u8 reserved_at_26[0x2]; 3198 u8 pd[0x18]; 3199 3200 u8 mtu[0x3]; 3201 u8 log_msg_max[0x5]; 3202 u8 reserved_at_48[0x1]; 3203 u8 log_rq_size[0x4]; 3204 u8 log_rq_stride[0x3]; 3205 u8 no_sq[0x1]; 3206 u8 log_sq_size[0x4]; 3207 u8 reserved_at_55[0x3]; 3208 u8 ts_format[0x2]; 3209 u8 reserved_at_5a[0x1]; 3210 u8 rlky[0x1]; 3211 u8 ulp_stateless_offload_mode[0x4]; 3212 3213 u8 counter_set_id[0x8]; 3214 u8 uar_page[0x18]; 3215 3216 u8 reserved_at_80[0x8]; 3217 u8 user_index[0x18]; 3218 3219 u8 reserved_at_a0[0x3]; 3220 u8 log_page_size[0x5]; 3221 u8 remote_qpn[0x18]; 3222 3223 struct mlx5_ifc_ads_bits primary_address_path; 3224 3225 struct mlx5_ifc_ads_bits secondary_address_path; 3226 3227 u8 log_ack_req_freq[0x4]; 3228 u8 reserved_at_384[0x4]; 3229 u8 log_sra_max[0x3]; 3230 u8 reserved_at_38b[0x2]; 3231 u8 retry_count[0x3]; 3232 u8 rnr_retry[0x3]; 3233 u8 reserved_at_393[0x1]; 3234 u8 fre[0x1]; 3235 u8 cur_rnr_retry[0x3]; 3236 u8 cur_retry_count[0x3]; 3237 u8 reserved_at_39b[0x5]; 3238 3239 u8 reserved_at_3a0[0x20]; 3240 3241 u8 reserved_at_3c0[0x8]; 3242 u8 next_send_psn[0x18]; 3243 3244 u8 reserved_at_3e0[0x3]; 3245 u8 log_num_dci_stream_channels[0x5]; 3246 u8 cqn_snd[0x18]; 3247 3248 u8 reserved_at_400[0x3]; 3249 u8 log_num_dci_errored_streams[0x5]; 3250 u8 deth_sqpn[0x18]; 3251 3252 u8 reserved_at_420[0x20]; 3253 3254 u8 reserved_at_440[0x8]; 3255 u8 last_acked_psn[0x18]; 3256 3257 u8 reserved_at_460[0x8]; 3258 u8 ssn[0x18]; 3259 3260 u8 reserved_at_480[0x8]; 3261 u8 log_rra_max[0x3]; 3262 u8 reserved_at_48b[0x1]; 3263 u8 atomic_mode[0x4]; 3264 u8 rre[0x1]; 3265 u8 rwe[0x1]; 3266 u8 rae[0x1]; 3267 u8 reserved_at_493[0x1]; 3268 u8 page_offset[0x6]; 3269 u8 reserved_at_49a[0x3]; 3270 u8 cd_slave_receive[0x1]; 3271 u8 cd_slave_send[0x1]; 3272 u8 cd_master[0x1]; 3273 3274 u8 reserved_at_4a0[0x3]; 3275 u8 min_rnr_nak[0x5]; 3276 u8 next_rcv_psn[0x18]; 3277 3278 u8 reserved_at_4c0[0x8]; 3279 u8 xrcd[0x18]; 3280 3281 u8 reserved_at_4e0[0x8]; 3282 u8 cqn_rcv[0x18]; 3283 3284 u8 dbr_addr[0x40]; 3285 3286 u8 q_key[0x20]; 3287 3288 u8 reserved_at_560[0x5]; 3289 u8 rq_type[0x3]; 3290 u8 srqn_rmpn_xrqn[0x18]; 3291 3292 u8 reserved_at_580[0x8]; 3293 u8 rmsn[0x18]; 3294 3295 u8 hw_sq_wqebb_counter[0x10]; 3296 u8 sw_sq_wqebb_counter[0x10]; 3297 3298 u8 hw_rq_counter[0x20]; 3299 3300 u8 sw_rq_counter[0x20]; 3301 3302 u8 reserved_at_600[0x20]; 3303 3304 u8 reserved_at_620[0xf]; 3305 u8 cgs[0x1]; 3306 u8 cs_req[0x8]; 3307 u8 cs_res[0x8]; 3308 3309 u8 dc_access_key[0x40]; 3310 3311 u8 reserved_at_680[0x3]; 3312 u8 dbr_umem_valid[0x1]; 3313 3314 u8 reserved_at_684[0xbc]; 3315 }; 3316 3317 struct mlx5_ifc_roce_addr_layout_bits { 3318 u8 source_l3_address[16][0x8]; 3319 3320 u8 reserved_at_80[0x3]; 3321 u8 vlan_valid[0x1]; 3322 u8 vlan_id[0xc]; 3323 u8 source_mac_47_32[0x10]; 3324 3325 u8 source_mac_31_0[0x20]; 3326 3327 u8 reserved_at_c0[0x14]; 3328 u8 roce_l3_type[0x4]; 3329 u8 roce_version[0x8]; 3330 3331 u8 reserved_at_e0[0x20]; 3332 }; 3333 3334 struct mlx5_ifc_shampo_cap_bits { 3335 u8 reserved_at_0[0x3]; 3336 u8 shampo_log_max_reservation_size[0x5]; 3337 u8 reserved_at_8[0x3]; 3338 u8 shampo_log_min_reservation_size[0x5]; 3339 u8 shampo_min_mss_size[0x10]; 3340 3341 u8 reserved_at_20[0x3]; 3342 u8 shampo_max_log_headers_entry_size[0x5]; 3343 u8 reserved_at_28[0x18]; 3344 3345 u8 reserved_at_40[0x7c0]; 3346 }; 3347 3348 union mlx5_ifc_hca_cap_union_bits { 3349 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap; 3350 struct mlx5_ifc_cmd_hca_cap_2_bits cmd_hca_cap_2; 3351 struct mlx5_ifc_odp_cap_bits odp_cap; 3352 struct mlx5_ifc_atomic_caps_bits atomic_caps; 3353 struct mlx5_ifc_roce_cap_bits roce_cap; 3354 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps; 3355 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap; 3356 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap; 3357 struct mlx5_ifc_e_switch_cap_bits e_switch_cap; 3358 struct mlx5_ifc_port_selection_cap_bits port_selection_cap; 3359 struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap; 3360 struct mlx5_ifc_qos_cap_bits qos_cap; 3361 struct mlx5_ifc_debug_cap_bits debug_cap; 3362 struct mlx5_ifc_fpga_cap_bits fpga_cap; 3363 struct mlx5_ifc_tls_cap_bits tls_cap; 3364 struct mlx5_ifc_device_mem_cap_bits device_mem_cap; 3365 struct mlx5_ifc_virtio_emulation_cap_bits virtio_emulation_cap; 3366 struct mlx5_ifc_shampo_cap_bits shampo_cap; 3367 struct mlx5_ifc_macsec_cap_bits macsec_cap; 3368 u8 reserved_at_0[0x8000]; 3369 }; 3370 3371 enum { 3372 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1, 3373 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2, 3374 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4, 3375 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8, 3376 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT = 0x10, 3377 MLX5_FLOW_CONTEXT_ACTION_DECAP = 0x20, 3378 MLX5_FLOW_CONTEXT_ACTION_MOD_HDR = 0x40, 3379 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP = 0x80, 3380 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100, 3381 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2 = 0x400, 3382 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2 = 0x800, 3383 MLX5_FLOW_CONTEXT_ACTION_CRYPTO_DECRYPT = 0x1000, 3384 MLX5_FLOW_CONTEXT_ACTION_CRYPTO_ENCRYPT = 0x2000, 3385 MLX5_FLOW_CONTEXT_ACTION_EXECUTE_ASO = 0x4000, 3386 }; 3387 3388 enum { 3389 MLX5_FLOW_CONTEXT_FLOW_SOURCE_ANY_VPORT = 0x0, 3390 MLX5_FLOW_CONTEXT_FLOW_SOURCE_UPLINK = 0x1, 3391 MLX5_FLOW_CONTEXT_FLOW_SOURCE_LOCAL_VPORT = 0x2, 3392 }; 3393 3394 enum { 3395 MLX5_FLOW_CONTEXT_ENCRYPT_DECRYPT_TYPE_IPSEC = 0x0, 3396 MLX5_FLOW_CONTEXT_ENCRYPT_DECRYPT_TYPE_MACSEC = 0x1, 3397 }; 3398 3399 struct mlx5_ifc_vlan_bits { 3400 u8 ethtype[0x10]; 3401 u8 prio[0x3]; 3402 u8 cfi[0x1]; 3403 u8 vid[0xc]; 3404 }; 3405 3406 enum { 3407 MLX5_FLOW_METER_COLOR_RED = 0x0, 3408 MLX5_FLOW_METER_COLOR_YELLOW = 0x1, 3409 MLX5_FLOW_METER_COLOR_GREEN = 0x2, 3410 MLX5_FLOW_METER_COLOR_UNDEFINED = 0x3, 3411 }; 3412 3413 enum { 3414 MLX5_EXE_ASO_FLOW_METER = 0x2, 3415 }; 3416 3417 struct mlx5_ifc_exe_aso_ctrl_flow_meter_bits { 3418 u8 return_reg_id[0x4]; 3419 u8 aso_type[0x4]; 3420 u8 reserved_at_8[0x14]; 3421 u8 action[0x1]; 3422 u8 init_color[0x2]; 3423 u8 meter_id[0x1]; 3424 }; 3425 3426 union mlx5_ifc_exe_aso_ctrl { 3427 struct mlx5_ifc_exe_aso_ctrl_flow_meter_bits exe_aso_ctrl_flow_meter; 3428 }; 3429 3430 struct mlx5_ifc_execute_aso_bits { 3431 u8 valid[0x1]; 3432 u8 reserved_at_1[0x7]; 3433 u8 aso_object_id[0x18]; 3434 3435 union mlx5_ifc_exe_aso_ctrl exe_aso_ctrl; 3436 }; 3437 3438 struct mlx5_ifc_flow_context_bits { 3439 struct mlx5_ifc_vlan_bits push_vlan; 3440 3441 u8 group_id[0x20]; 3442 3443 u8 reserved_at_40[0x8]; 3444 u8 flow_tag[0x18]; 3445 3446 u8 reserved_at_60[0x10]; 3447 u8 action[0x10]; 3448 3449 u8 extended_destination[0x1]; 3450 u8 reserved_at_81[0x1]; 3451 u8 flow_source[0x2]; 3452 u8 encrypt_decrypt_type[0x4]; 3453 u8 destination_list_size[0x18]; 3454 3455 u8 reserved_at_a0[0x8]; 3456 u8 flow_counter_list_size[0x18]; 3457 3458 u8 packet_reformat_id[0x20]; 3459 3460 u8 modify_header_id[0x20]; 3461 3462 struct mlx5_ifc_vlan_bits push_vlan_2; 3463 3464 u8 encrypt_decrypt_obj_id[0x20]; 3465 u8 reserved_at_140[0xc0]; 3466 3467 struct mlx5_ifc_fte_match_param_bits match_value; 3468 3469 struct mlx5_ifc_execute_aso_bits execute_aso[4]; 3470 3471 u8 reserved_at_1300[0x500]; 3472 3473 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[]; 3474 }; 3475 3476 enum { 3477 MLX5_XRC_SRQC_STATE_GOOD = 0x0, 3478 MLX5_XRC_SRQC_STATE_ERROR = 0x1, 3479 }; 3480 3481 struct mlx5_ifc_xrc_srqc_bits { 3482 u8 state[0x4]; 3483 u8 log_xrc_srq_size[0x4]; 3484 u8 reserved_at_8[0x18]; 3485 3486 u8 wq_signature[0x1]; 3487 u8 cont_srq[0x1]; 3488 u8 reserved_at_22[0x1]; 3489 u8 rlky[0x1]; 3490 u8 basic_cyclic_rcv_wqe[0x1]; 3491 u8 log_rq_stride[0x3]; 3492 u8 xrcd[0x18]; 3493 3494 u8 page_offset[0x6]; 3495 u8 reserved_at_46[0x1]; 3496 u8 dbr_umem_valid[0x1]; 3497 u8 cqn[0x18]; 3498 3499 u8 reserved_at_60[0x20]; 3500 3501 u8 user_index_equal_xrc_srqn[0x1]; 3502 u8 reserved_at_81[0x1]; 3503 u8 log_page_size[0x6]; 3504 u8 user_index[0x18]; 3505 3506 u8 reserved_at_a0[0x20]; 3507 3508 u8 reserved_at_c0[0x8]; 3509 u8 pd[0x18]; 3510 3511 u8 lwm[0x10]; 3512 u8 wqe_cnt[0x10]; 3513 3514 u8 reserved_at_100[0x40]; 3515 3516 u8 db_record_addr_h[0x20]; 3517 3518 u8 db_record_addr_l[0x1e]; 3519 u8 reserved_at_17e[0x2]; 3520 3521 u8 reserved_at_180[0x80]; 3522 }; 3523 3524 struct mlx5_ifc_vnic_diagnostic_statistics_bits { 3525 u8 counter_error_queues[0x20]; 3526 3527 u8 total_error_queues[0x20]; 3528 3529 u8 send_queue_priority_update_flow[0x20]; 3530 3531 u8 reserved_at_60[0x20]; 3532 3533 u8 nic_receive_steering_discard[0x40]; 3534 3535 u8 receive_discard_vport_down[0x40]; 3536 3537 u8 transmit_discard_vport_down[0x40]; 3538 3539 u8 async_eq_overrun[0x20]; 3540 3541 u8 comp_eq_overrun[0x20]; 3542 3543 u8 reserved_at_180[0x20]; 3544 3545 u8 invalid_command[0x20]; 3546 3547 u8 quota_exceeded_command[0x20]; 3548 3549 u8 internal_rq_out_of_buffer[0x20]; 3550 3551 u8 cq_overrun[0x20]; 3552 3553 u8 eth_wqe_too_small[0x20]; 3554 3555 u8 reserved_at_220[0xdc0]; 3556 }; 3557 3558 struct mlx5_ifc_traffic_counter_bits { 3559 u8 packets[0x40]; 3560 3561 u8 octets[0x40]; 3562 }; 3563 3564 struct mlx5_ifc_tisc_bits { 3565 u8 strict_lag_tx_port_affinity[0x1]; 3566 u8 tls_en[0x1]; 3567 u8 reserved_at_2[0x2]; 3568 u8 lag_tx_port_affinity[0x04]; 3569 3570 u8 reserved_at_8[0x4]; 3571 u8 prio[0x4]; 3572 u8 reserved_at_10[0x10]; 3573 3574 u8 reserved_at_20[0x100]; 3575 3576 u8 reserved_at_120[0x8]; 3577 u8 transport_domain[0x18]; 3578 3579 u8 reserved_at_140[0x8]; 3580 u8 underlay_qpn[0x18]; 3581 3582 u8 reserved_at_160[0x8]; 3583 u8 pd[0x18]; 3584 3585 u8 reserved_at_180[0x380]; 3586 }; 3587 3588 enum { 3589 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0, 3590 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1, 3591 }; 3592 3593 enum { 3594 MLX5_TIRC_PACKET_MERGE_MASK_IPV4_LRO = BIT(0), 3595 MLX5_TIRC_PACKET_MERGE_MASK_IPV6_LRO = BIT(1), 3596 }; 3597 3598 enum { 3599 MLX5_RX_HASH_FN_NONE = 0x0, 3600 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1, 3601 MLX5_RX_HASH_FN_TOEPLITZ = 0x2, 3602 }; 3603 3604 enum { 3605 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST = 0x1, 3606 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST = 0x2, 3607 }; 3608 3609 struct mlx5_ifc_tirc_bits { 3610 u8 reserved_at_0[0x20]; 3611 3612 u8 disp_type[0x4]; 3613 u8 tls_en[0x1]; 3614 u8 reserved_at_25[0x1b]; 3615 3616 u8 reserved_at_40[0x40]; 3617 3618 u8 reserved_at_80[0x4]; 3619 u8 lro_timeout_period_usecs[0x10]; 3620 u8 packet_merge_mask[0x4]; 3621 u8 lro_max_ip_payload_size[0x8]; 3622 3623 u8 reserved_at_a0[0x40]; 3624 3625 u8 reserved_at_e0[0x8]; 3626 u8 inline_rqn[0x18]; 3627 3628 u8 rx_hash_symmetric[0x1]; 3629 u8 reserved_at_101[0x1]; 3630 u8 tunneled_offload_en[0x1]; 3631 u8 reserved_at_103[0x5]; 3632 u8 indirect_table[0x18]; 3633 3634 u8 rx_hash_fn[0x4]; 3635 u8 reserved_at_124[0x2]; 3636 u8 self_lb_block[0x2]; 3637 u8 transport_domain[0x18]; 3638 3639 u8 rx_hash_toeplitz_key[10][0x20]; 3640 3641 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer; 3642 3643 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner; 3644 3645 u8 reserved_at_2c0[0x4c0]; 3646 }; 3647 3648 enum { 3649 MLX5_SRQC_STATE_GOOD = 0x0, 3650 MLX5_SRQC_STATE_ERROR = 0x1, 3651 }; 3652 3653 struct mlx5_ifc_srqc_bits { 3654 u8 state[0x4]; 3655 u8 log_srq_size[0x4]; 3656 u8 reserved_at_8[0x18]; 3657 3658 u8 wq_signature[0x1]; 3659 u8 cont_srq[0x1]; 3660 u8 reserved_at_22[0x1]; 3661 u8 rlky[0x1]; 3662 u8 reserved_at_24[0x1]; 3663 u8 log_rq_stride[0x3]; 3664 u8 xrcd[0x18]; 3665 3666 u8 page_offset[0x6]; 3667 u8 reserved_at_46[0x2]; 3668 u8 cqn[0x18]; 3669 3670 u8 reserved_at_60[0x20]; 3671 3672 u8 reserved_at_80[0x2]; 3673 u8 log_page_size[0x6]; 3674 u8 reserved_at_88[0x18]; 3675 3676 u8 reserved_at_a0[0x20]; 3677 3678 u8 reserved_at_c0[0x8]; 3679 u8 pd[0x18]; 3680 3681 u8 lwm[0x10]; 3682 u8 wqe_cnt[0x10]; 3683 3684 u8 reserved_at_100[0x40]; 3685 3686 u8 dbr_addr[0x40]; 3687 3688 u8 reserved_at_180[0x80]; 3689 }; 3690 3691 enum { 3692 MLX5_SQC_STATE_RST = 0x0, 3693 MLX5_SQC_STATE_RDY = 0x1, 3694 MLX5_SQC_STATE_ERR = 0x3, 3695 }; 3696 3697 struct mlx5_ifc_sqc_bits { 3698 u8 rlky[0x1]; 3699 u8 cd_master[0x1]; 3700 u8 fre[0x1]; 3701 u8 flush_in_error_en[0x1]; 3702 u8 allow_multi_pkt_send_wqe[0x1]; 3703 u8 min_wqe_inline_mode[0x3]; 3704 u8 state[0x4]; 3705 u8 reg_umr[0x1]; 3706 u8 allow_swp[0x1]; 3707 u8 hairpin[0x1]; 3708 u8 reserved_at_f[0xb]; 3709 u8 ts_format[0x2]; 3710 u8 reserved_at_1c[0x4]; 3711 3712 u8 reserved_at_20[0x8]; 3713 u8 user_index[0x18]; 3714 3715 u8 reserved_at_40[0x8]; 3716 u8 cqn[0x18]; 3717 3718 u8 reserved_at_60[0x8]; 3719 u8 hairpin_peer_rq[0x18]; 3720 3721 u8 reserved_at_80[0x10]; 3722 u8 hairpin_peer_vhca[0x10]; 3723 3724 u8 reserved_at_a0[0x20]; 3725 3726 u8 reserved_at_c0[0x8]; 3727 u8 ts_cqe_to_dest_cqn[0x18]; 3728 3729 u8 reserved_at_e0[0x10]; 3730 u8 packet_pacing_rate_limit_index[0x10]; 3731 u8 tis_lst_sz[0x10]; 3732 u8 qos_queue_group_id[0x10]; 3733 3734 u8 reserved_at_120[0x40]; 3735 3736 u8 reserved_at_160[0x8]; 3737 u8 tis_num_0[0x18]; 3738 3739 struct mlx5_ifc_wq_bits wq; 3740 }; 3741 3742 enum { 3743 SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0, 3744 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1, 3745 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2, 3746 SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3, 3747 SCHEDULING_CONTEXT_ELEMENT_TYPE_QUEUE_GROUP = 0x4, 3748 }; 3749 3750 enum { 3751 ELEMENT_TYPE_CAP_MASK_TASR = 1 << 0, 3752 ELEMENT_TYPE_CAP_MASK_VPORT = 1 << 1, 3753 ELEMENT_TYPE_CAP_MASK_VPORT_TC = 1 << 2, 3754 ELEMENT_TYPE_CAP_MASK_PARA_VPORT_TC = 1 << 3, 3755 }; 3756 3757 struct mlx5_ifc_scheduling_context_bits { 3758 u8 element_type[0x8]; 3759 u8 reserved_at_8[0x18]; 3760 3761 u8 element_attributes[0x20]; 3762 3763 u8 parent_element_id[0x20]; 3764 3765 u8 reserved_at_60[0x40]; 3766 3767 u8 bw_share[0x20]; 3768 3769 u8 max_average_bw[0x20]; 3770 3771 u8 reserved_at_e0[0x120]; 3772 }; 3773 3774 struct mlx5_ifc_rqtc_bits { 3775 u8 reserved_at_0[0xa0]; 3776 3777 u8 reserved_at_a0[0x5]; 3778 u8 list_q_type[0x3]; 3779 u8 reserved_at_a8[0x8]; 3780 u8 rqt_max_size[0x10]; 3781 3782 u8 rq_vhca_id_format[0x1]; 3783 u8 reserved_at_c1[0xf]; 3784 u8 rqt_actual_size[0x10]; 3785 3786 u8 reserved_at_e0[0x6a0]; 3787 3788 struct mlx5_ifc_rq_num_bits rq_num[]; 3789 }; 3790 3791 enum { 3792 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0, 3793 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1, 3794 }; 3795 3796 enum { 3797 MLX5_RQC_STATE_RST = 0x0, 3798 MLX5_RQC_STATE_RDY = 0x1, 3799 MLX5_RQC_STATE_ERR = 0x3, 3800 }; 3801 3802 enum { 3803 MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_BYTE = 0x0, 3804 MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_STRIDE = 0x1, 3805 MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_PAGE = 0x2, 3806 }; 3807 3808 enum { 3809 MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_NO_MATCH = 0x0, 3810 MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_EXTENDED = 0x1, 3811 MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_FIVE_TUPLE = 0x2, 3812 }; 3813 3814 struct mlx5_ifc_rqc_bits { 3815 u8 rlky[0x1]; 3816 u8 delay_drop_en[0x1]; 3817 u8 scatter_fcs[0x1]; 3818 u8 vsd[0x1]; 3819 u8 mem_rq_type[0x4]; 3820 u8 state[0x4]; 3821 u8 reserved_at_c[0x1]; 3822 u8 flush_in_error_en[0x1]; 3823 u8 hairpin[0x1]; 3824 u8 reserved_at_f[0xb]; 3825 u8 ts_format[0x2]; 3826 u8 reserved_at_1c[0x4]; 3827 3828 u8 reserved_at_20[0x8]; 3829 u8 user_index[0x18]; 3830 3831 u8 reserved_at_40[0x8]; 3832 u8 cqn[0x18]; 3833 3834 u8 counter_set_id[0x8]; 3835 u8 reserved_at_68[0x18]; 3836 3837 u8 reserved_at_80[0x8]; 3838 u8 rmpn[0x18]; 3839 3840 u8 reserved_at_a0[0x8]; 3841 u8 hairpin_peer_sq[0x18]; 3842 3843 u8 reserved_at_c0[0x10]; 3844 u8 hairpin_peer_vhca[0x10]; 3845 3846 u8 reserved_at_e0[0x46]; 3847 u8 shampo_no_match_alignment_granularity[0x2]; 3848 u8 reserved_at_128[0x6]; 3849 u8 shampo_match_criteria_type[0x2]; 3850 u8 reservation_timeout[0x10]; 3851 3852 u8 reserved_at_140[0x40]; 3853 3854 struct mlx5_ifc_wq_bits wq; 3855 }; 3856 3857 enum { 3858 MLX5_RMPC_STATE_RDY = 0x1, 3859 MLX5_RMPC_STATE_ERR = 0x3, 3860 }; 3861 3862 struct mlx5_ifc_rmpc_bits { 3863 u8 reserved_at_0[0x8]; 3864 u8 state[0x4]; 3865 u8 reserved_at_c[0x14]; 3866 3867 u8 basic_cyclic_rcv_wqe[0x1]; 3868 u8 reserved_at_21[0x1f]; 3869 3870 u8 reserved_at_40[0x140]; 3871 3872 struct mlx5_ifc_wq_bits wq; 3873 }; 3874 3875 enum { 3876 VHCA_ID_TYPE_HW = 0, 3877 VHCA_ID_TYPE_SW = 1, 3878 }; 3879 3880 struct mlx5_ifc_nic_vport_context_bits { 3881 u8 reserved_at_0[0x5]; 3882 u8 min_wqe_inline_mode[0x3]; 3883 u8 reserved_at_8[0x15]; 3884 u8 disable_mc_local_lb[0x1]; 3885 u8 disable_uc_local_lb[0x1]; 3886 u8 roce_en[0x1]; 3887 3888 u8 arm_change_event[0x1]; 3889 u8 reserved_at_21[0x1a]; 3890 u8 event_on_mtu[0x1]; 3891 u8 event_on_promisc_change[0x1]; 3892 u8 event_on_vlan_change[0x1]; 3893 u8 event_on_mc_address_change[0x1]; 3894 u8 event_on_uc_address_change[0x1]; 3895 3896 u8 vhca_id_type[0x1]; 3897 u8 reserved_at_41[0xb]; 3898 u8 affiliation_criteria[0x4]; 3899 u8 affiliated_vhca_id[0x10]; 3900 3901 u8 reserved_at_60[0xd0]; 3902 3903 u8 mtu[0x10]; 3904 3905 u8 system_image_guid[0x40]; 3906 u8 port_guid[0x40]; 3907 u8 node_guid[0x40]; 3908 3909 u8 reserved_at_200[0x140]; 3910 u8 qkey_violation_counter[0x10]; 3911 u8 reserved_at_350[0x430]; 3912 3913 u8 promisc_uc[0x1]; 3914 u8 promisc_mc[0x1]; 3915 u8 promisc_all[0x1]; 3916 u8 reserved_at_783[0x2]; 3917 u8 allowed_list_type[0x3]; 3918 u8 reserved_at_788[0xc]; 3919 u8 allowed_list_size[0xc]; 3920 3921 struct mlx5_ifc_mac_address_layout_bits permanent_address; 3922 3923 u8 reserved_at_7e0[0x20]; 3924 3925 u8 current_uc_mac_address[][0x40]; 3926 }; 3927 3928 enum { 3929 MLX5_MKC_ACCESS_MODE_PA = 0x0, 3930 MLX5_MKC_ACCESS_MODE_MTT = 0x1, 3931 MLX5_MKC_ACCESS_MODE_KLMS = 0x2, 3932 MLX5_MKC_ACCESS_MODE_KSM = 0x3, 3933 MLX5_MKC_ACCESS_MODE_SW_ICM = 0x4, 3934 MLX5_MKC_ACCESS_MODE_MEMIC = 0x5, 3935 }; 3936 3937 struct mlx5_ifc_mkc_bits { 3938 u8 reserved_at_0[0x1]; 3939 u8 free[0x1]; 3940 u8 reserved_at_2[0x1]; 3941 u8 access_mode_4_2[0x3]; 3942 u8 reserved_at_6[0x7]; 3943 u8 relaxed_ordering_write[0x1]; 3944 u8 reserved_at_e[0x1]; 3945 u8 small_fence_on_rdma_read_response[0x1]; 3946 u8 umr_en[0x1]; 3947 u8 a[0x1]; 3948 u8 rw[0x1]; 3949 u8 rr[0x1]; 3950 u8 lw[0x1]; 3951 u8 lr[0x1]; 3952 u8 access_mode_1_0[0x2]; 3953 u8 reserved_at_18[0x2]; 3954 u8 ma_translation_mode[0x2]; 3955 u8 reserved_at_1c[0x4]; 3956 3957 u8 qpn[0x18]; 3958 u8 mkey_7_0[0x8]; 3959 3960 u8 reserved_at_40[0x20]; 3961 3962 u8 length64[0x1]; 3963 u8 bsf_en[0x1]; 3964 u8 sync_umr[0x1]; 3965 u8 reserved_at_63[0x2]; 3966 u8 expected_sigerr_count[0x1]; 3967 u8 reserved_at_66[0x1]; 3968 u8 en_rinval[0x1]; 3969 u8 pd[0x18]; 3970 3971 u8 start_addr[0x40]; 3972 3973 u8 len[0x40]; 3974 3975 u8 bsf_octword_size[0x20]; 3976 3977 u8 reserved_at_120[0x80]; 3978 3979 u8 translations_octword_size[0x20]; 3980 3981 u8 reserved_at_1c0[0x19]; 3982 u8 relaxed_ordering_read[0x1]; 3983 u8 reserved_at_1d9[0x1]; 3984 u8 log_page_size[0x5]; 3985 3986 u8 reserved_at_1e0[0x20]; 3987 }; 3988 3989 struct mlx5_ifc_pkey_bits { 3990 u8 reserved_at_0[0x10]; 3991 u8 pkey[0x10]; 3992 }; 3993 3994 struct mlx5_ifc_array128_auto_bits { 3995 u8 array128_auto[16][0x8]; 3996 }; 3997 3998 struct mlx5_ifc_hca_vport_context_bits { 3999 u8 field_select[0x20]; 4000 4001 u8 reserved_at_20[0xe0]; 4002 4003 u8 sm_virt_aware[0x1]; 4004 u8 has_smi[0x1]; 4005 u8 has_raw[0x1]; 4006 u8 grh_required[0x1]; 4007 u8 reserved_at_104[0xc]; 4008 u8 port_physical_state[0x4]; 4009 u8 vport_state_policy[0x4]; 4010 u8 port_state[0x4]; 4011 u8 vport_state[0x4]; 4012 4013 u8 reserved_at_120[0x20]; 4014 4015 u8 system_image_guid[0x40]; 4016 4017 u8 port_guid[0x40]; 4018 4019 u8 node_guid[0x40]; 4020 4021 u8 cap_mask1[0x20]; 4022 4023 u8 cap_mask1_field_select[0x20]; 4024 4025 u8 cap_mask2[0x20]; 4026 4027 u8 cap_mask2_field_select[0x20]; 4028 4029 u8 reserved_at_280[0x80]; 4030 4031 u8 lid[0x10]; 4032 u8 reserved_at_310[0x4]; 4033 u8 init_type_reply[0x4]; 4034 u8 lmc[0x3]; 4035 u8 subnet_timeout[0x5]; 4036 4037 u8 sm_lid[0x10]; 4038 u8 sm_sl[0x4]; 4039 u8 reserved_at_334[0xc]; 4040 4041 u8 qkey_violation_counter[0x10]; 4042 u8 pkey_violation_counter[0x10]; 4043 4044 u8 reserved_at_360[0xca0]; 4045 }; 4046 4047 struct mlx5_ifc_esw_vport_context_bits { 4048 u8 fdb_to_vport_reg_c[0x1]; 4049 u8 reserved_at_1[0x2]; 4050 u8 vport_svlan_strip[0x1]; 4051 u8 vport_cvlan_strip[0x1]; 4052 u8 vport_svlan_insert[0x1]; 4053 u8 vport_cvlan_insert[0x2]; 4054 u8 fdb_to_vport_reg_c_id[0x8]; 4055 u8 reserved_at_10[0x10]; 4056 4057 u8 reserved_at_20[0x20]; 4058 4059 u8 svlan_cfi[0x1]; 4060 u8 svlan_pcp[0x3]; 4061 u8 svlan_id[0xc]; 4062 u8 cvlan_cfi[0x1]; 4063 u8 cvlan_pcp[0x3]; 4064 u8 cvlan_id[0xc]; 4065 4066 u8 reserved_at_60[0x720]; 4067 4068 u8 sw_steering_vport_icm_address_rx[0x40]; 4069 4070 u8 sw_steering_vport_icm_address_tx[0x40]; 4071 }; 4072 4073 enum { 4074 MLX5_EQC_STATUS_OK = 0x0, 4075 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa, 4076 }; 4077 4078 enum { 4079 MLX5_EQC_ST_ARMED = 0x9, 4080 MLX5_EQC_ST_FIRED = 0xa, 4081 }; 4082 4083 struct mlx5_ifc_eqc_bits { 4084 u8 status[0x4]; 4085 u8 reserved_at_4[0x9]; 4086 u8 ec[0x1]; 4087 u8 oi[0x1]; 4088 u8 reserved_at_f[0x5]; 4089 u8 st[0x4]; 4090 u8 reserved_at_18[0x8]; 4091 4092 u8 reserved_at_20[0x20]; 4093 4094 u8 reserved_at_40[0x14]; 4095 u8 page_offset[0x6]; 4096 u8 reserved_at_5a[0x6]; 4097 4098 u8 reserved_at_60[0x3]; 4099 u8 log_eq_size[0x5]; 4100 u8 uar_page[0x18]; 4101 4102 u8 reserved_at_80[0x20]; 4103 4104 u8 reserved_at_a0[0x14]; 4105 u8 intr[0xc]; 4106 4107 u8 reserved_at_c0[0x3]; 4108 u8 log_page_size[0x5]; 4109 u8 reserved_at_c8[0x18]; 4110 4111 u8 reserved_at_e0[0x60]; 4112 4113 u8 reserved_at_140[0x8]; 4114 u8 consumer_counter[0x18]; 4115 4116 u8 reserved_at_160[0x8]; 4117 u8 producer_counter[0x18]; 4118 4119 u8 reserved_at_180[0x80]; 4120 }; 4121 4122 enum { 4123 MLX5_DCTC_STATE_ACTIVE = 0x0, 4124 MLX5_DCTC_STATE_DRAINING = 0x1, 4125 MLX5_DCTC_STATE_DRAINED = 0x2, 4126 }; 4127 4128 enum { 4129 MLX5_DCTC_CS_RES_DISABLE = 0x0, 4130 MLX5_DCTC_CS_RES_NA = 0x1, 4131 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2, 4132 }; 4133 4134 enum { 4135 MLX5_DCTC_MTU_256_BYTES = 0x1, 4136 MLX5_DCTC_MTU_512_BYTES = 0x2, 4137 MLX5_DCTC_MTU_1K_BYTES = 0x3, 4138 MLX5_DCTC_MTU_2K_BYTES = 0x4, 4139 MLX5_DCTC_MTU_4K_BYTES = 0x5, 4140 }; 4141 4142 struct mlx5_ifc_dctc_bits { 4143 u8 reserved_at_0[0x4]; 4144 u8 state[0x4]; 4145 u8 reserved_at_8[0x18]; 4146 4147 u8 reserved_at_20[0x8]; 4148 u8 user_index[0x18]; 4149 4150 u8 reserved_at_40[0x8]; 4151 u8 cqn[0x18]; 4152 4153 u8 counter_set_id[0x8]; 4154 u8 atomic_mode[0x4]; 4155 u8 rre[0x1]; 4156 u8 rwe[0x1]; 4157 u8 rae[0x1]; 4158 u8 atomic_like_write_en[0x1]; 4159 u8 latency_sensitive[0x1]; 4160 u8 rlky[0x1]; 4161 u8 free_ar[0x1]; 4162 u8 reserved_at_73[0xd]; 4163 4164 u8 reserved_at_80[0x8]; 4165 u8 cs_res[0x8]; 4166 u8 reserved_at_90[0x3]; 4167 u8 min_rnr_nak[0x5]; 4168 u8 reserved_at_98[0x8]; 4169 4170 u8 reserved_at_a0[0x8]; 4171 u8 srqn_xrqn[0x18]; 4172 4173 u8 reserved_at_c0[0x8]; 4174 u8 pd[0x18]; 4175 4176 u8 tclass[0x8]; 4177 u8 reserved_at_e8[0x4]; 4178 u8 flow_label[0x14]; 4179 4180 u8 dc_access_key[0x40]; 4181 4182 u8 reserved_at_140[0x5]; 4183 u8 mtu[0x3]; 4184 u8 port[0x8]; 4185 u8 pkey_index[0x10]; 4186 4187 u8 reserved_at_160[0x8]; 4188 u8 my_addr_index[0x8]; 4189 u8 reserved_at_170[0x8]; 4190 u8 hop_limit[0x8]; 4191 4192 u8 dc_access_key_violation_count[0x20]; 4193 4194 u8 reserved_at_1a0[0x14]; 4195 u8 dei_cfi[0x1]; 4196 u8 eth_prio[0x3]; 4197 u8 ecn[0x2]; 4198 u8 dscp[0x6]; 4199 4200 u8 reserved_at_1c0[0x20]; 4201 u8 ece[0x20]; 4202 }; 4203 4204 enum { 4205 MLX5_CQC_STATUS_OK = 0x0, 4206 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9, 4207 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa, 4208 }; 4209 4210 enum { 4211 MLX5_CQC_CQE_SZ_64_BYTES = 0x0, 4212 MLX5_CQC_CQE_SZ_128_BYTES = 0x1, 4213 }; 4214 4215 enum { 4216 MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED = 0x6, 4217 MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED = 0x9, 4218 MLX5_CQC_ST_FIRED = 0xa, 4219 }; 4220 4221 enum { 4222 MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0, 4223 MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1, 4224 MLX5_CQ_PERIOD_NUM_MODES 4225 }; 4226 4227 struct mlx5_ifc_cqc_bits { 4228 u8 status[0x4]; 4229 u8 reserved_at_4[0x2]; 4230 u8 dbr_umem_valid[0x1]; 4231 u8 apu_cq[0x1]; 4232 u8 cqe_sz[0x3]; 4233 u8 cc[0x1]; 4234 u8 reserved_at_c[0x1]; 4235 u8 scqe_break_moderation_en[0x1]; 4236 u8 oi[0x1]; 4237 u8 cq_period_mode[0x2]; 4238 u8 cqe_comp_en[0x1]; 4239 u8 mini_cqe_res_format[0x2]; 4240 u8 st[0x4]; 4241 u8 reserved_at_18[0x6]; 4242 u8 cqe_compression_layout[0x2]; 4243 4244 u8 reserved_at_20[0x20]; 4245 4246 u8 reserved_at_40[0x14]; 4247 u8 page_offset[0x6]; 4248 u8 reserved_at_5a[0x6]; 4249 4250 u8 reserved_at_60[0x3]; 4251 u8 log_cq_size[0x5]; 4252 u8 uar_page[0x18]; 4253 4254 u8 reserved_at_80[0x4]; 4255 u8 cq_period[0xc]; 4256 u8 cq_max_count[0x10]; 4257 4258 u8 c_eqn_or_apu_element[0x20]; 4259 4260 u8 reserved_at_c0[0x3]; 4261 u8 log_page_size[0x5]; 4262 u8 reserved_at_c8[0x18]; 4263 4264 u8 reserved_at_e0[0x20]; 4265 4266 u8 reserved_at_100[0x8]; 4267 u8 last_notified_index[0x18]; 4268 4269 u8 reserved_at_120[0x8]; 4270 u8 last_solicit_index[0x18]; 4271 4272 u8 reserved_at_140[0x8]; 4273 u8 consumer_counter[0x18]; 4274 4275 u8 reserved_at_160[0x8]; 4276 u8 producer_counter[0x18]; 4277 4278 u8 reserved_at_180[0x40]; 4279 4280 u8 dbr_addr[0x40]; 4281 }; 4282 4283 union mlx5_ifc_cong_control_roce_ecn_auto_bits { 4284 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp; 4285 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp; 4286 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np; 4287 u8 reserved_at_0[0x800]; 4288 }; 4289 4290 struct mlx5_ifc_query_adapter_param_block_bits { 4291 u8 reserved_at_0[0xc0]; 4292 4293 u8 reserved_at_c0[0x8]; 4294 u8 ieee_vendor_id[0x18]; 4295 4296 u8 reserved_at_e0[0x10]; 4297 u8 vsd_vendor_id[0x10]; 4298 4299 u8 vsd[208][0x8]; 4300 4301 u8 vsd_contd_psid[16][0x8]; 4302 }; 4303 4304 enum { 4305 MLX5_XRQC_STATE_GOOD = 0x0, 4306 MLX5_XRQC_STATE_ERROR = 0x1, 4307 }; 4308 4309 enum { 4310 MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0, 4311 MLX5_XRQC_TOPOLOGY_TAG_MATCHING = 0x1, 4312 }; 4313 4314 enum { 4315 MLX5_XRQC_OFFLOAD_RNDV = 0x1, 4316 }; 4317 4318 struct mlx5_ifc_tag_matching_topology_context_bits { 4319 u8 log_matching_list_sz[0x4]; 4320 u8 reserved_at_4[0xc]; 4321 u8 append_next_index[0x10]; 4322 4323 u8 sw_phase_cnt[0x10]; 4324 u8 hw_phase_cnt[0x10]; 4325 4326 u8 reserved_at_40[0x40]; 4327 }; 4328 4329 struct mlx5_ifc_xrqc_bits { 4330 u8 state[0x4]; 4331 u8 rlkey[0x1]; 4332 u8 reserved_at_5[0xf]; 4333 u8 topology[0x4]; 4334 u8 reserved_at_18[0x4]; 4335 u8 offload[0x4]; 4336 4337 u8 reserved_at_20[0x8]; 4338 u8 user_index[0x18]; 4339 4340 u8 reserved_at_40[0x8]; 4341 u8 cqn[0x18]; 4342 4343 u8 reserved_at_60[0xa0]; 4344 4345 struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context; 4346 4347 u8 reserved_at_180[0x280]; 4348 4349 struct mlx5_ifc_wq_bits wq; 4350 }; 4351 4352 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits { 4353 struct mlx5_ifc_modify_field_select_bits modify_field_select; 4354 struct mlx5_ifc_resize_field_select_bits resize_field_select; 4355 u8 reserved_at_0[0x20]; 4356 }; 4357 4358 union mlx5_ifc_field_select_802_1_r_roce_auto_bits { 4359 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp; 4360 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp; 4361 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np; 4362 u8 reserved_at_0[0x20]; 4363 }; 4364 4365 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits { 4366 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 4367 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 4368 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 4369 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 4370 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 4371 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 4372 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout; 4373 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout; 4374 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 4375 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 4376 struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs; 4377 u8 reserved_at_0[0x7c0]; 4378 }; 4379 4380 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits { 4381 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout; 4382 u8 reserved_at_0[0x7c0]; 4383 }; 4384 4385 union mlx5_ifc_event_auto_bits { 4386 struct mlx5_ifc_comp_event_bits comp_event; 4387 struct mlx5_ifc_dct_events_bits dct_events; 4388 struct mlx5_ifc_qp_events_bits qp_events; 4389 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event; 4390 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event; 4391 struct mlx5_ifc_cq_error_bits cq_error; 4392 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged; 4393 struct mlx5_ifc_port_state_change_event_bits port_state_change_event; 4394 struct mlx5_ifc_gpio_event_bits gpio_event; 4395 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event; 4396 struct mlx5_ifc_stall_vl_event_bits stall_vl_event; 4397 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event; 4398 u8 reserved_at_0[0xe0]; 4399 }; 4400 4401 struct mlx5_ifc_health_buffer_bits { 4402 u8 reserved_at_0[0x100]; 4403 4404 u8 assert_existptr[0x20]; 4405 4406 u8 assert_callra[0x20]; 4407 4408 u8 reserved_at_140[0x20]; 4409 4410 u8 time[0x20]; 4411 4412 u8 fw_version[0x20]; 4413 4414 u8 hw_id[0x20]; 4415 4416 u8 rfr[0x1]; 4417 u8 reserved_at_1c1[0x3]; 4418 u8 valid[0x1]; 4419 u8 severity[0x3]; 4420 u8 reserved_at_1c8[0x18]; 4421 4422 u8 irisc_index[0x8]; 4423 u8 synd[0x8]; 4424 u8 ext_synd[0x10]; 4425 }; 4426 4427 struct mlx5_ifc_register_loopback_control_bits { 4428 u8 no_lb[0x1]; 4429 u8 reserved_at_1[0x7]; 4430 u8 port[0x8]; 4431 u8 reserved_at_10[0x10]; 4432 4433 u8 reserved_at_20[0x60]; 4434 }; 4435 4436 struct mlx5_ifc_vport_tc_element_bits { 4437 u8 traffic_class[0x4]; 4438 u8 reserved_at_4[0xc]; 4439 u8 vport_number[0x10]; 4440 }; 4441 4442 struct mlx5_ifc_vport_element_bits { 4443 u8 reserved_at_0[0x10]; 4444 u8 vport_number[0x10]; 4445 }; 4446 4447 enum { 4448 TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0, 4449 TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1, 4450 TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2, 4451 }; 4452 4453 struct mlx5_ifc_tsar_element_bits { 4454 u8 reserved_at_0[0x8]; 4455 u8 tsar_type[0x8]; 4456 u8 reserved_at_10[0x10]; 4457 }; 4458 4459 enum { 4460 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0, 4461 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1, 4462 }; 4463 4464 struct mlx5_ifc_teardown_hca_out_bits { 4465 u8 status[0x8]; 4466 u8 reserved_at_8[0x18]; 4467 4468 u8 syndrome[0x20]; 4469 4470 u8 reserved_at_40[0x3f]; 4471 4472 u8 state[0x1]; 4473 }; 4474 4475 enum { 4476 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0, 4477 MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE = 0x1, 4478 MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN = 0x2, 4479 }; 4480 4481 struct mlx5_ifc_teardown_hca_in_bits { 4482 u8 opcode[0x10]; 4483 u8 reserved_at_10[0x10]; 4484 4485 u8 reserved_at_20[0x10]; 4486 u8 op_mod[0x10]; 4487 4488 u8 reserved_at_40[0x10]; 4489 u8 profile[0x10]; 4490 4491 u8 reserved_at_60[0x20]; 4492 }; 4493 4494 struct mlx5_ifc_sqerr2rts_qp_out_bits { 4495 u8 status[0x8]; 4496 u8 reserved_at_8[0x18]; 4497 4498 u8 syndrome[0x20]; 4499 4500 u8 reserved_at_40[0x40]; 4501 }; 4502 4503 struct mlx5_ifc_sqerr2rts_qp_in_bits { 4504 u8 opcode[0x10]; 4505 u8 uid[0x10]; 4506 4507 u8 reserved_at_20[0x10]; 4508 u8 op_mod[0x10]; 4509 4510 u8 reserved_at_40[0x8]; 4511 u8 qpn[0x18]; 4512 4513 u8 reserved_at_60[0x20]; 4514 4515 u8 opt_param_mask[0x20]; 4516 4517 u8 reserved_at_a0[0x20]; 4518 4519 struct mlx5_ifc_qpc_bits qpc; 4520 4521 u8 reserved_at_800[0x80]; 4522 }; 4523 4524 struct mlx5_ifc_sqd2rts_qp_out_bits { 4525 u8 status[0x8]; 4526 u8 reserved_at_8[0x18]; 4527 4528 u8 syndrome[0x20]; 4529 4530 u8 reserved_at_40[0x40]; 4531 }; 4532 4533 struct mlx5_ifc_sqd2rts_qp_in_bits { 4534 u8 opcode[0x10]; 4535 u8 uid[0x10]; 4536 4537 u8 reserved_at_20[0x10]; 4538 u8 op_mod[0x10]; 4539 4540 u8 reserved_at_40[0x8]; 4541 u8 qpn[0x18]; 4542 4543 u8 reserved_at_60[0x20]; 4544 4545 u8 opt_param_mask[0x20]; 4546 4547 u8 reserved_at_a0[0x20]; 4548 4549 struct mlx5_ifc_qpc_bits qpc; 4550 4551 u8 reserved_at_800[0x80]; 4552 }; 4553 4554 struct mlx5_ifc_set_roce_address_out_bits { 4555 u8 status[0x8]; 4556 u8 reserved_at_8[0x18]; 4557 4558 u8 syndrome[0x20]; 4559 4560 u8 reserved_at_40[0x40]; 4561 }; 4562 4563 struct mlx5_ifc_set_roce_address_in_bits { 4564 u8 opcode[0x10]; 4565 u8 reserved_at_10[0x10]; 4566 4567 u8 reserved_at_20[0x10]; 4568 u8 op_mod[0x10]; 4569 4570 u8 roce_address_index[0x10]; 4571 u8 reserved_at_50[0xc]; 4572 u8 vhca_port_num[0x4]; 4573 4574 u8 reserved_at_60[0x20]; 4575 4576 struct mlx5_ifc_roce_addr_layout_bits roce_address; 4577 }; 4578 4579 struct mlx5_ifc_set_mad_demux_out_bits { 4580 u8 status[0x8]; 4581 u8 reserved_at_8[0x18]; 4582 4583 u8 syndrome[0x20]; 4584 4585 u8 reserved_at_40[0x40]; 4586 }; 4587 4588 enum { 4589 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0, 4590 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2, 4591 }; 4592 4593 struct mlx5_ifc_set_mad_demux_in_bits { 4594 u8 opcode[0x10]; 4595 u8 reserved_at_10[0x10]; 4596 4597 u8 reserved_at_20[0x10]; 4598 u8 op_mod[0x10]; 4599 4600 u8 reserved_at_40[0x20]; 4601 4602 u8 reserved_at_60[0x6]; 4603 u8 demux_mode[0x2]; 4604 u8 reserved_at_68[0x18]; 4605 }; 4606 4607 struct mlx5_ifc_set_l2_table_entry_out_bits { 4608 u8 status[0x8]; 4609 u8 reserved_at_8[0x18]; 4610 4611 u8 syndrome[0x20]; 4612 4613 u8 reserved_at_40[0x40]; 4614 }; 4615 4616 struct mlx5_ifc_set_l2_table_entry_in_bits { 4617 u8 opcode[0x10]; 4618 u8 reserved_at_10[0x10]; 4619 4620 u8 reserved_at_20[0x10]; 4621 u8 op_mod[0x10]; 4622 4623 u8 reserved_at_40[0x60]; 4624 4625 u8 reserved_at_a0[0x8]; 4626 u8 table_index[0x18]; 4627 4628 u8 reserved_at_c0[0x20]; 4629 4630 u8 reserved_at_e0[0x13]; 4631 u8 vlan_valid[0x1]; 4632 u8 vlan[0xc]; 4633 4634 struct mlx5_ifc_mac_address_layout_bits mac_address; 4635 4636 u8 reserved_at_140[0xc0]; 4637 }; 4638 4639 struct mlx5_ifc_set_issi_out_bits { 4640 u8 status[0x8]; 4641 u8 reserved_at_8[0x18]; 4642 4643 u8 syndrome[0x20]; 4644 4645 u8 reserved_at_40[0x40]; 4646 }; 4647 4648 struct mlx5_ifc_set_issi_in_bits { 4649 u8 opcode[0x10]; 4650 u8 reserved_at_10[0x10]; 4651 4652 u8 reserved_at_20[0x10]; 4653 u8 op_mod[0x10]; 4654 4655 u8 reserved_at_40[0x10]; 4656 u8 current_issi[0x10]; 4657 4658 u8 reserved_at_60[0x20]; 4659 }; 4660 4661 struct mlx5_ifc_set_hca_cap_out_bits { 4662 u8 status[0x8]; 4663 u8 reserved_at_8[0x18]; 4664 4665 u8 syndrome[0x20]; 4666 4667 u8 reserved_at_40[0x40]; 4668 }; 4669 4670 struct mlx5_ifc_set_hca_cap_in_bits { 4671 u8 opcode[0x10]; 4672 u8 reserved_at_10[0x10]; 4673 4674 u8 reserved_at_20[0x10]; 4675 u8 op_mod[0x10]; 4676 4677 u8 other_function[0x1]; 4678 u8 reserved_at_41[0xf]; 4679 u8 function_id[0x10]; 4680 4681 u8 reserved_at_60[0x20]; 4682 4683 union mlx5_ifc_hca_cap_union_bits capability; 4684 }; 4685 4686 enum { 4687 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0, 4688 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1, 4689 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2, 4690 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3, 4691 MLX5_SET_FTE_MODIFY_ENABLE_MASK_IPSEC_OBJ_ID = 0x4 4692 }; 4693 4694 struct mlx5_ifc_set_fte_out_bits { 4695 u8 status[0x8]; 4696 u8 reserved_at_8[0x18]; 4697 4698 u8 syndrome[0x20]; 4699 4700 u8 reserved_at_40[0x40]; 4701 }; 4702 4703 struct mlx5_ifc_set_fte_in_bits { 4704 u8 opcode[0x10]; 4705 u8 reserved_at_10[0x10]; 4706 4707 u8 reserved_at_20[0x10]; 4708 u8 op_mod[0x10]; 4709 4710 u8 other_vport[0x1]; 4711 u8 reserved_at_41[0xf]; 4712 u8 vport_number[0x10]; 4713 4714 u8 reserved_at_60[0x20]; 4715 4716 u8 table_type[0x8]; 4717 u8 reserved_at_88[0x18]; 4718 4719 u8 reserved_at_a0[0x8]; 4720 u8 table_id[0x18]; 4721 4722 u8 ignore_flow_level[0x1]; 4723 u8 reserved_at_c1[0x17]; 4724 u8 modify_enable_mask[0x8]; 4725 4726 u8 reserved_at_e0[0x20]; 4727 4728 u8 flow_index[0x20]; 4729 4730 u8 reserved_at_120[0xe0]; 4731 4732 struct mlx5_ifc_flow_context_bits flow_context; 4733 }; 4734 4735 struct mlx5_ifc_rts2rts_qp_out_bits { 4736 u8 status[0x8]; 4737 u8 reserved_at_8[0x18]; 4738 4739 u8 syndrome[0x20]; 4740 4741 u8 reserved_at_40[0x20]; 4742 u8 ece[0x20]; 4743 }; 4744 4745 struct mlx5_ifc_rts2rts_qp_in_bits { 4746 u8 opcode[0x10]; 4747 u8 uid[0x10]; 4748 4749 u8 reserved_at_20[0x10]; 4750 u8 op_mod[0x10]; 4751 4752 u8 reserved_at_40[0x8]; 4753 u8 qpn[0x18]; 4754 4755 u8 reserved_at_60[0x20]; 4756 4757 u8 opt_param_mask[0x20]; 4758 4759 u8 ece[0x20]; 4760 4761 struct mlx5_ifc_qpc_bits qpc; 4762 4763 u8 reserved_at_800[0x80]; 4764 }; 4765 4766 struct mlx5_ifc_rtr2rts_qp_out_bits { 4767 u8 status[0x8]; 4768 u8 reserved_at_8[0x18]; 4769 4770 u8 syndrome[0x20]; 4771 4772 u8 reserved_at_40[0x20]; 4773 u8 ece[0x20]; 4774 }; 4775 4776 struct mlx5_ifc_rtr2rts_qp_in_bits { 4777 u8 opcode[0x10]; 4778 u8 uid[0x10]; 4779 4780 u8 reserved_at_20[0x10]; 4781 u8 op_mod[0x10]; 4782 4783 u8 reserved_at_40[0x8]; 4784 u8 qpn[0x18]; 4785 4786 u8 reserved_at_60[0x20]; 4787 4788 u8 opt_param_mask[0x20]; 4789 4790 u8 ece[0x20]; 4791 4792 struct mlx5_ifc_qpc_bits qpc; 4793 4794 u8 reserved_at_800[0x80]; 4795 }; 4796 4797 struct mlx5_ifc_rst2init_qp_out_bits { 4798 u8 status[0x8]; 4799 u8 reserved_at_8[0x18]; 4800 4801 u8 syndrome[0x20]; 4802 4803 u8 reserved_at_40[0x20]; 4804 u8 ece[0x20]; 4805 }; 4806 4807 struct mlx5_ifc_rst2init_qp_in_bits { 4808 u8 opcode[0x10]; 4809 u8 uid[0x10]; 4810 4811 u8 reserved_at_20[0x10]; 4812 u8 op_mod[0x10]; 4813 4814 u8 reserved_at_40[0x8]; 4815 u8 qpn[0x18]; 4816 4817 u8 reserved_at_60[0x20]; 4818 4819 u8 opt_param_mask[0x20]; 4820 4821 u8 ece[0x20]; 4822 4823 struct mlx5_ifc_qpc_bits qpc; 4824 4825 u8 reserved_at_800[0x80]; 4826 }; 4827 4828 struct mlx5_ifc_query_xrq_out_bits { 4829 u8 status[0x8]; 4830 u8 reserved_at_8[0x18]; 4831 4832 u8 syndrome[0x20]; 4833 4834 u8 reserved_at_40[0x40]; 4835 4836 struct mlx5_ifc_xrqc_bits xrq_context; 4837 }; 4838 4839 struct mlx5_ifc_query_xrq_in_bits { 4840 u8 opcode[0x10]; 4841 u8 reserved_at_10[0x10]; 4842 4843 u8 reserved_at_20[0x10]; 4844 u8 op_mod[0x10]; 4845 4846 u8 reserved_at_40[0x8]; 4847 u8 xrqn[0x18]; 4848 4849 u8 reserved_at_60[0x20]; 4850 }; 4851 4852 struct mlx5_ifc_query_xrc_srq_out_bits { 4853 u8 status[0x8]; 4854 u8 reserved_at_8[0x18]; 4855 4856 u8 syndrome[0x20]; 4857 4858 u8 reserved_at_40[0x40]; 4859 4860 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 4861 4862 u8 reserved_at_280[0x600]; 4863 4864 u8 pas[][0x40]; 4865 }; 4866 4867 struct mlx5_ifc_query_xrc_srq_in_bits { 4868 u8 opcode[0x10]; 4869 u8 reserved_at_10[0x10]; 4870 4871 u8 reserved_at_20[0x10]; 4872 u8 op_mod[0x10]; 4873 4874 u8 reserved_at_40[0x8]; 4875 u8 xrc_srqn[0x18]; 4876 4877 u8 reserved_at_60[0x20]; 4878 }; 4879 4880 enum { 4881 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0, 4882 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1, 4883 }; 4884 4885 struct mlx5_ifc_query_vport_state_out_bits { 4886 u8 status[0x8]; 4887 u8 reserved_at_8[0x18]; 4888 4889 u8 syndrome[0x20]; 4890 4891 u8 reserved_at_40[0x20]; 4892 4893 u8 reserved_at_60[0x18]; 4894 u8 admin_state[0x4]; 4895 u8 state[0x4]; 4896 }; 4897 4898 enum { 4899 MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT = 0x0, 4900 MLX5_VPORT_STATE_OP_MOD_ESW_VPORT = 0x1, 4901 MLX5_VPORT_STATE_OP_MOD_UPLINK = 0x2, 4902 }; 4903 4904 struct mlx5_ifc_arm_monitor_counter_in_bits { 4905 u8 opcode[0x10]; 4906 u8 uid[0x10]; 4907 4908 u8 reserved_at_20[0x10]; 4909 u8 op_mod[0x10]; 4910 4911 u8 reserved_at_40[0x20]; 4912 4913 u8 reserved_at_60[0x20]; 4914 }; 4915 4916 struct mlx5_ifc_arm_monitor_counter_out_bits { 4917 u8 status[0x8]; 4918 u8 reserved_at_8[0x18]; 4919 4920 u8 syndrome[0x20]; 4921 4922 u8 reserved_at_40[0x40]; 4923 }; 4924 4925 enum { 4926 MLX5_QUERY_MONITOR_CNT_TYPE_PPCNT = 0x0, 4927 MLX5_QUERY_MONITOR_CNT_TYPE_Q_COUNTER = 0x1, 4928 }; 4929 4930 enum mlx5_monitor_counter_ppcnt { 4931 MLX5_QUERY_MONITOR_PPCNT_IN_RANGE_LENGTH_ERRORS = 0x0, 4932 MLX5_QUERY_MONITOR_PPCNT_OUT_OF_RANGE_LENGTH_FIELD = 0x1, 4933 MLX5_QUERY_MONITOR_PPCNT_FRAME_TOO_LONG_ERRORS = 0x2, 4934 MLX5_QUERY_MONITOR_PPCNT_FRAME_CHECK_SEQUENCE_ERRORS = 0x3, 4935 MLX5_QUERY_MONITOR_PPCNT_ALIGNMENT_ERRORS = 0x4, 4936 MLX5_QUERY_MONITOR_PPCNT_IF_OUT_DISCARDS = 0x5, 4937 }; 4938 4939 enum { 4940 MLX5_QUERY_MONITOR_Q_COUNTER_RX_OUT_OF_BUFFER = 0x4, 4941 }; 4942 4943 struct mlx5_ifc_monitor_counter_output_bits { 4944 u8 reserved_at_0[0x4]; 4945 u8 type[0x4]; 4946 u8 reserved_at_8[0x8]; 4947 u8 counter[0x10]; 4948 4949 u8 counter_group_id[0x20]; 4950 }; 4951 4952 #define MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 (6) 4953 #define MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1 (1) 4954 #define MLX5_CMD_SET_MONITOR_NUM_COUNTER (MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 +\ 4955 MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1) 4956 4957 struct mlx5_ifc_set_monitor_counter_in_bits { 4958 u8 opcode[0x10]; 4959 u8 uid[0x10]; 4960 4961 u8 reserved_at_20[0x10]; 4962 u8 op_mod[0x10]; 4963 4964 u8 reserved_at_40[0x10]; 4965 u8 num_of_counters[0x10]; 4966 4967 u8 reserved_at_60[0x20]; 4968 4969 struct mlx5_ifc_monitor_counter_output_bits monitor_counter[MLX5_CMD_SET_MONITOR_NUM_COUNTER]; 4970 }; 4971 4972 struct mlx5_ifc_set_monitor_counter_out_bits { 4973 u8 status[0x8]; 4974 u8 reserved_at_8[0x18]; 4975 4976 u8 syndrome[0x20]; 4977 4978 u8 reserved_at_40[0x40]; 4979 }; 4980 4981 struct mlx5_ifc_query_vport_state_in_bits { 4982 u8 opcode[0x10]; 4983 u8 reserved_at_10[0x10]; 4984 4985 u8 reserved_at_20[0x10]; 4986 u8 op_mod[0x10]; 4987 4988 u8 other_vport[0x1]; 4989 u8 reserved_at_41[0xf]; 4990 u8 vport_number[0x10]; 4991 4992 u8 reserved_at_60[0x20]; 4993 }; 4994 4995 struct mlx5_ifc_query_vnic_env_out_bits { 4996 u8 status[0x8]; 4997 u8 reserved_at_8[0x18]; 4998 4999 u8 syndrome[0x20]; 5000 5001 u8 reserved_at_40[0x40]; 5002 5003 struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env; 5004 }; 5005 5006 enum { 5007 MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS = 0x0, 5008 }; 5009 5010 struct mlx5_ifc_query_vnic_env_in_bits { 5011 u8 opcode[0x10]; 5012 u8 reserved_at_10[0x10]; 5013 5014 u8 reserved_at_20[0x10]; 5015 u8 op_mod[0x10]; 5016 5017 u8 other_vport[0x1]; 5018 u8 reserved_at_41[0xf]; 5019 u8 vport_number[0x10]; 5020 5021 u8 reserved_at_60[0x20]; 5022 }; 5023 5024 struct mlx5_ifc_query_vport_counter_out_bits { 5025 u8 status[0x8]; 5026 u8 reserved_at_8[0x18]; 5027 5028 u8 syndrome[0x20]; 5029 5030 u8 reserved_at_40[0x40]; 5031 5032 struct mlx5_ifc_traffic_counter_bits received_errors; 5033 5034 struct mlx5_ifc_traffic_counter_bits transmit_errors; 5035 5036 struct mlx5_ifc_traffic_counter_bits received_ib_unicast; 5037 5038 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast; 5039 5040 struct mlx5_ifc_traffic_counter_bits received_ib_multicast; 5041 5042 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast; 5043 5044 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast; 5045 5046 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast; 5047 5048 struct mlx5_ifc_traffic_counter_bits received_eth_unicast; 5049 5050 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast; 5051 5052 struct mlx5_ifc_traffic_counter_bits received_eth_multicast; 5053 5054 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast; 5055 5056 u8 reserved_at_680[0xa00]; 5057 }; 5058 5059 enum { 5060 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0, 5061 }; 5062 5063 struct mlx5_ifc_query_vport_counter_in_bits { 5064 u8 opcode[0x10]; 5065 u8 reserved_at_10[0x10]; 5066 5067 u8 reserved_at_20[0x10]; 5068 u8 op_mod[0x10]; 5069 5070 u8 other_vport[0x1]; 5071 u8 reserved_at_41[0xb]; 5072 u8 port_num[0x4]; 5073 u8 vport_number[0x10]; 5074 5075 u8 reserved_at_60[0x60]; 5076 5077 u8 clear[0x1]; 5078 u8 reserved_at_c1[0x1f]; 5079 5080 u8 reserved_at_e0[0x20]; 5081 }; 5082 5083 struct mlx5_ifc_query_tis_out_bits { 5084 u8 status[0x8]; 5085 u8 reserved_at_8[0x18]; 5086 5087 u8 syndrome[0x20]; 5088 5089 u8 reserved_at_40[0x40]; 5090 5091 struct mlx5_ifc_tisc_bits tis_context; 5092 }; 5093 5094 struct mlx5_ifc_query_tis_in_bits { 5095 u8 opcode[0x10]; 5096 u8 reserved_at_10[0x10]; 5097 5098 u8 reserved_at_20[0x10]; 5099 u8 op_mod[0x10]; 5100 5101 u8 reserved_at_40[0x8]; 5102 u8 tisn[0x18]; 5103 5104 u8 reserved_at_60[0x20]; 5105 }; 5106 5107 struct mlx5_ifc_query_tir_out_bits { 5108 u8 status[0x8]; 5109 u8 reserved_at_8[0x18]; 5110 5111 u8 syndrome[0x20]; 5112 5113 u8 reserved_at_40[0xc0]; 5114 5115 struct mlx5_ifc_tirc_bits tir_context; 5116 }; 5117 5118 struct mlx5_ifc_query_tir_in_bits { 5119 u8 opcode[0x10]; 5120 u8 reserved_at_10[0x10]; 5121 5122 u8 reserved_at_20[0x10]; 5123 u8 op_mod[0x10]; 5124 5125 u8 reserved_at_40[0x8]; 5126 u8 tirn[0x18]; 5127 5128 u8 reserved_at_60[0x20]; 5129 }; 5130 5131 struct mlx5_ifc_query_srq_out_bits { 5132 u8 status[0x8]; 5133 u8 reserved_at_8[0x18]; 5134 5135 u8 syndrome[0x20]; 5136 5137 u8 reserved_at_40[0x40]; 5138 5139 struct mlx5_ifc_srqc_bits srq_context_entry; 5140 5141 u8 reserved_at_280[0x600]; 5142 5143 u8 pas[][0x40]; 5144 }; 5145 5146 struct mlx5_ifc_query_srq_in_bits { 5147 u8 opcode[0x10]; 5148 u8 reserved_at_10[0x10]; 5149 5150 u8 reserved_at_20[0x10]; 5151 u8 op_mod[0x10]; 5152 5153 u8 reserved_at_40[0x8]; 5154 u8 srqn[0x18]; 5155 5156 u8 reserved_at_60[0x20]; 5157 }; 5158 5159 struct mlx5_ifc_query_sq_out_bits { 5160 u8 status[0x8]; 5161 u8 reserved_at_8[0x18]; 5162 5163 u8 syndrome[0x20]; 5164 5165 u8 reserved_at_40[0xc0]; 5166 5167 struct mlx5_ifc_sqc_bits sq_context; 5168 }; 5169 5170 struct mlx5_ifc_query_sq_in_bits { 5171 u8 opcode[0x10]; 5172 u8 reserved_at_10[0x10]; 5173 5174 u8 reserved_at_20[0x10]; 5175 u8 op_mod[0x10]; 5176 5177 u8 reserved_at_40[0x8]; 5178 u8 sqn[0x18]; 5179 5180 u8 reserved_at_60[0x20]; 5181 }; 5182 5183 struct mlx5_ifc_query_special_contexts_out_bits { 5184 u8 status[0x8]; 5185 u8 reserved_at_8[0x18]; 5186 5187 u8 syndrome[0x20]; 5188 5189 u8 dump_fill_mkey[0x20]; 5190 5191 u8 resd_lkey[0x20]; 5192 5193 u8 null_mkey[0x20]; 5194 5195 u8 reserved_at_a0[0x60]; 5196 }; 5197 5198 struct mlx5_ifc_query_special_contexts_in_bits { 5199 u8 opcode[0x10]; 5200 u8 reserved_at_10[0x10]; 5201 5202 u8 reserved_at_20[0x10]; 5203 u8 op_mod[0x10]; 5204 5205 u8 reserved_at_40[0x40]; 5206 }; 5207 5208 struct mlx5_ifc_query_scheduling_element_out_bits { 5209 u8 opcode[0x10]; 5210 u8 reserved_at_10[0x10]; 5211 5212 u8 reserved_at_20[0x10]; 5213 u8 op_mod[0x10]; 5214 5215 u8 reserved_at_40[0xc0]; 5216 5217 struct mlx5_ifc_scheduling_context_bits scheduling_context; 5218 5219 u8 reserved_at_300[0x100]; 5220 }; 5221 5222 enum { 5223 SCHEDULING_HIERARCHY_E_SWITCH = 0x2, 5224 SCHEDULING_HIERARCHY_NIC = 0x3, 5225 }; 5226 5227 struct mlx5_ifc_query_scheduling_element_in_bits { 5228 u8 opcode[0x10]; 5229 u8 reserved_at_10[0x10]; 5230 5231 u8 reserved_at_20[0x10]; 5232 u8 op_mod[0x10]; 5233 5234 u8 scheduling_hierarchy[0x8]; 5235 u8 reserved_at_48[0x18]; 5236 5237 u8 scheduling_element_id[0x20]; 5238 5239 u8 reserved_at_80[0x180]; 5240 }; 5241 5242 struct mlx5_ifc_query_rqt_out_bits { 5243 u8 status[0x8]; 5244 u8 reserved_at_8[0x18]; 5245 5246 u8 syndrome[0x20]; 5247 5248 u8 reserved_at_40[0xc0]; 5249 5250 struct mlx5_ifc_rqtc_bits rqt_context; 5251 }; 5252 5253 struct mlx5_ifc_query_rqt_in_bits { 5254 u8 opcode[0x10]; 5255 u8 reserved_at_10[0x10]; 5256 5257 u8 reserved_at_20[0x10]; 5258 u8 op_mod[0x10]; 5259 5260 u8 reserved_at_40[0x8]; 5261 u8 rqtn[0x18]; 5262 5263 u8 reserved_at_60[0x20]; 5264 }; 5265 5266 struct mlx5_ifc_query_rq_out_bits { 5267 u8 status[0x8]; 5268 u8 reserved_at_8[0x18]; 5269 5270 u8 syndrome[0x20]; 5271 5272 u8 reserved_at_40[0xc0]; 5273 5274 struct mlx5_ifc_rqc_bits rq_context; 5275 }; 5276 5277 struct mlx5_ifc_query_rq_in_bits { 5278 u8 opcode[0x10]; 5279 u8 reserved_at_10[0x10]; 5280 5281 u8 reserved_at_20[0x10]; 5282 u8 op_mod[0x10]; 5283 5284 u8 reserved_at_40[0x8]; 5285 u8 rqn[0x18]; 5286 5287 u8 reserved_at_60[0x20]; 5288 }; 5289 5290 struct mlx5_ifc_query_roce_address_out_bits { 5291 u8 status[0x8]; 5292 u8 reserved_at_8[0x18]; 5293 5294 u8 syndrome[0x20]; 5295 5296 u8 reserved_at_40[0x40]; 5297 5298 struct mlx5_ifc_roce_addr_layout_bits roce_address; 5299 }; 5300 5301 struct mlx5_ifc_query_roce_address_in_bits { 5302 u8 opcode[0x10]; 5303 u8 reserved_at_10[0x10]; 5304 5305 u8 reserved_at_20[0x10]; 5306 u8 op_mod[0x10]; 5307 5308 u8 roce_address_index[0x10]; 5309 u8 reserved_at_50[0xc]; 5310 u8 vhca_port_num[0x4]; 5311 5312 u8 reserved_at_60[0x20]; 5313 }; 5314 5315 struct mlx5_ifc_query_rmp_out_bits { 5316 u8 status[0x8]; 5317 u8 reserved_at_8[0x18]; 5318 5319 u8 syndrome[0x20]; 5320 5321 u8 reserved_at_40[0xc0]; 5322 5323 struct mlx5_ifc_rmpc_bits rmp_context; 5324 }; 5325 5326 struct mlx5_ifc_query_rmp_in_bits { 5327 u8 opcode[0x10]; 5328 u8 reserved_at_10[0x10]; 5329 5330 u8 reserved_at_20[0x10]; 5331 u8 op_mod[0x10]; 5332 5333 u8 reserved_at_40[0x8]; 5334 u8 rmpn[0x18]; 5335 5336 u8 reserved_at_60[0x20]; 5337 }; 5338 5339 struct mlx5_ifc_query_qp_out_bits { 5340 u8 status[0x8]; 5341 u8 reserved_at_8[0x18]; 5342 5343 u8 syndrome[0x20]; 5344 5345 u8 reserved_at_40[0x40]; 5346 5347 u8 opt_param_mask[0x20]; 5348 5349 u8 ece[0x20]; 5350 5351 struct mlx5_ifc_qpc_bits qpc; 5352 5353 u8 reserved_at_800[0x80]; 5354 5355 u8 pas[][0x40]; 5356 }; 5357 5358 struct mlx5_ifc_query_qp_in_bits { 5359 u8 opcode[0x10]; 5360 u8 reserved_at_10[0x10]; 5361 5362 u8 reserved_at_20[0x10]; 5363 u8 op_mod[0x10]; 5364 5365 u8 reserved_at_40[0x8]; 5366 u8 qpn[0x18]; 5367 5368 u8 reserved_at_60[0x20]; 5369 }; 5370 5371 struct mlx5_ifc_query_q_counter_out_bits { 5372 u8 status[0x8]; 5373 u8 reserved_at_8[0x18]; 5374 5375 u8 syndrome[0x20]; 5376 5377 u8 reserved_at_40[0x40]; 5378 5379 u8 rx_write_requests[0x20]; 5380 5381 u8 reserved_at_a0[0x20]; 5382 5383 u8 rx_read_requests[0x20]; 5384 5385 u8 reserved_at_e0[0x20]; 5386 5387 u8 rx_atomic_requests[0x20]; 5388 5389 u8 reserved_at_120[0x20]; 5390 5391 u8 rx_dct_connect[0x20]; 5392 5393 u8 reserved_at_160[0x20]; 5394 5395 u8 out_of_buffer[0x20]; 5396 5397 u8 reserved_at_1a0[0x20]; 5398 5399 u8 out_of_sequence[0x20]; 5400 5401 u8 reserved_at_1e0[0x20]; 5402 5403 u8 duplicate_request[0x20]; 5404 5405 u8 reserved_at_220[0x20]; 5406 5407 u8 rnr_nak_retry_err[0x20]; 5408 5409 u8 reserved_at_260[0x20]; 5410 5411 u8 packet_seq_err[0x20]; 5412 5413 u8 reserved_at_2a0[0x20]; 5414 5415 u8 implied_nak_seq_err[0x20]; 5416 5417 u8 reserved_at_2e0[0x20]; 5418 5419 u8 local_ack_timeout_err[0x20]; 5420 5421 u8 reserved_at_320[0xa0]; 5422 5423 u8 resp_local_length_error[0x20]; 5424 5425 u8 req_local_length_error[0x20]; 5426 5427 u8 resp_local_qp_error[0x20]; 5428 5429 u8 local_operation_error[0x20]; 5430 5431 u8 resp_local_protection[0x20]; 5432 5433 u8 req_local_protection[0x20]; 5434 5435 u8 resp_cqe_error[0x20]; 5436 5437 u8 req_cqe_error[0x20]; 5438 5439 u8 req_mw_binding[0x20]; 5440 5441 u8 req_bad_response[0x20]; 5442 5443 u8 req_remote_invalid_request[0x20]; 5444 5445 u8 resp_remote_invalid_request[0x20]; 5446 5447 u8 req_remote_access_errors[0x20]; 5448 5449 u8 resp_remote_access_errors[0x20]; 5450 5451 u8 req_remote_operation_errors[0x20]; 5452 5453 u8 req_transport_retries_exceeded[0x20]; 5454 5455 u8 cq_overflow[0x20]; 5456 5457 u8 resp_cqe_flush_error[0x20]; 5458 5459 u8 req_cqe_flush_error[0x20]; 5460 5461 u8 reserved_at_620[0x20]; 5462 5463 u8 roce_adp_retrans[0x20]; 5464 5465 u8 roce_adp_retrans_to[0x20]; 5466 5467 u8 roce_slow_restart[0x20]; 5468 5469 u8 roce_slow_restart_cnps[0x20]; 5470 5471 u8 roce_slow_restart_trans[0x20]; 5472 5473 u8 reserved_at_6e0[0x120]; 5474 }; 5475 5476 struct mlx5_ifc_query_q_counter_in_bits { 5477 u8 opcode[0x10]; 5478 u8 reserved_at_10[0x10]; 5479 5480 u8 reserved_at_20[0x10]; 5481 u8 op_mod[0x10]; 5482 5483 u8 reserved_at_40[0x80]; 5484 5485 u8 clear[0x1]; 5486 u8 reserved_at_c1[0x1f]; 5487 5488 u8 reserved_at_e0[0x18]; 5489 u8 counter_set_id[0x8]; 5490 }; 5491 5492 struct mlx5_ifc_query_pages_out_bits { 5493 u8 status[0x8]; 5494 u8 reserved_at_8[0x18]; 5495 5496 u8 syndrome[0x20]; 5497 5498 u8 embedded_cpu_function[0x1]; 5499 u8 reserved_at_41[0xf]; 5500 u8 function_id[0x10]; 5501 5502 u8 num_pages[0x20]; 5503 }; 5504 5505 enum { 5506 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1, 5507 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2, 5508 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3, 5509 }; 5510 5511 struct mlx5_ifc_query_pages_in_bits { 5512 u8 opcode[0x10]; 5513 u8 reserved_at_10[0x10]; 5514 5515 u8 reserved_at_20[0x10]; 5516 u8 op_mod[0x10]; 5517 5518 u8 embedded_cpu_function[0x1]; 5519 u8 reserved_at_41[0xf]; 5520 u8 function_id[0x10]; 5521 5522 u8 reserved_at_60[0x20]; 5523 }; 5524 5525 struct mlx5_ifc_query_nic_vport_context_out_bits { 5526 u8 status[0x8]; 5527 u8 reserved_at_8[0x18]; 5528 5529 u8 syndrome[0x20]; 5530 5531 u8 reserved_at_40[0x40]; 5532 5533 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 5534 }; 5535 5536 struct mlx5_ifc_query_nic_vport_context_in_bits { 5537 u8 opcode[0x10]; 5538 u8 reserved_at_10[0x10]; 5539 5540 u8 reserved_at_20[0x10]; 5541 u8 op_mod[0x10]; 5542 5543 u8 other_vport[0x1]; 5544 u8 reserved_at_41[0xf]; 5545 u8 vport_number[0x10]; 5546 5547 u8 reserved_at_60[0x5]; 5548 u8 allowed_list_type[0x3]; 5549 u8 reserved_at_68[0x18]; 5550 }; 5551 5552 struct mlx5_ifc_query_mkey_out_bits { 5553 u8 status[0x8]; 5554 u8 reserved_at_8[0x18]; 5555 5556 u8 syndrome[0x20]; 5557 5558 u8 reserved_at_40[0x40]; 5559 5560 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 5561 5562 u8 reserved_at_280[0x600]; 5563 5564 u8 bsf0_klm0_pas_mtt0_1[16][0x8]; 5565 5566 u8 bsf1_klm1_pas_mtt2_3[16][0x8]; 5567 }; 5568 5569 struct mlx5_ifc_query_mkey_in_bits { 5570 u8 opcode[0x10]; 5571 u8 reserved_at_10[0x10]; 5572 5573 u8 reserved_at_20[0x10]; 5574 u8 op_mod[0x10]; 5575 5576 u8 reserved_at_40[0x8]; 5577 u8 mkey_index[0x18]; 5578 5579 u8 pg_access[0x1]; 5580 u8 reserved_at_61[0x1f]; 5581 }; 5582 5583 struct mlx5_ifc_query_mad_demux_out_bits { 5584 u8 status[0x8]; 5585 u8 reserved_at_8[0x18]; 5586 5587 u8 syndrome[0x20]; 5588 5589 u8 reserved_at_40[0x40]; 5590 5591 u8 mad_dumux_parameters_block[0x20]; 5592 }; 5593 5594 struct mlx5_ifc_query_mad_demux_in_bits { 5595 u8 opcode[0x10]; 5596 u8 reserved_at_10[0x10]; 5597 5598 u8 reserved_at_20[0x10]; 5599 u8 op_mod[0x10]; 5600 5601 u8 reserved_at_40[0x40]; 5602 }; 5603 5604 struct mlx5_ifc_query_l2_table_entry_out_bits { 5605 u8 status[0x8]; 5606 u8 reserved_at_8[0x18]; 5607 5608 u8 syndrome[0x20]; 5609 5610 u8 reserved_at_40[0xa0]; 5611 5612 u8 reserved_at_e0[0x13]; 5613 u8 vlan_valid[0x1]; 5614 u8 vlan[0xc]; 5615 5616 struct mlx5_ifc_mac_address_layout_bits mac_address; 5617 5618 u8 reserved_at_140[0xc0]; 5619 }; 5620 5621 struct mlx5_ifc_query_l2_table_entry_in_bits { 5622 u8 opcode[0x10]; 5623 u8 reserved_at_10[0x10]; 5624 5625 u8 reserved_at_20[0x10]; 5626 u8 op_mod[0x10]; 5627 5628 u8 reserved_at_40[0x60]; 5629 5630 u8 reserved_at_a0[0x8]; 5631 u8 table_index[0x18]; 5632 5633 u8 reserved_at_c0[0x140]; 5634 }; 5635 5636 struct mlx5_ifc_query_issi_out_bits { 5637 u8 status[0x8]; 5638 u8 reserved_at_8[0x18]; 5639 5640 u8 syndrome[0x20]; 5641 5642 u8 reserved_at_40[0x10]; 5643 u8 current_issi[0x10]; 5644 5645 u8 reserved_at_60[0xa0]; 5646 5647 u8 reserved_at_100[76][0x8]; 5648 u8 supported_issi_dw0[0x20]; 5649 }; 5650 5651 struct mlx5_ifc_query_issi_in_bits { 5652 u8 opcode[0x10]; 5653 u8 reserved_at_10[0x10]; 5654 5655 u8 reserved_at_20[0x10]; 5656 u8 op_mod[0x10]; 5657 5658 u8 reserved_at_40[0x40]; 5659 }; 5660 5661 struct mlx5_ifc_set_driver_version_out_bits { 5662 u8 status[0x8]; 5663 u8 reserved_0[0x18]; 5664 5665 u8 syndrome[0x20]; 5666 u8 reserved_1[0x40]; 5667 }; 5668 5669 struct mlx5_ifc_set_driver_version_in_bits { 5670 u8 opcode[0x10]; 5671 u8 reserved_0[0x10]; 5672 5673 u8 reserved_1[0x10]; 5674 u8 op_mod[0x10]; 5675 5676 u8 reserved_2[0x40]; 5677 u8 driver_version[64][0x8]; 5678 }; 5679 5680 struct mlx5_ifc_query_hca_vport_pkey_out_bits { 5681 u8 status[0x8]; 5682 u8 reserved_at_8[0x18]; 5683 5684 u8 syndrome[0x20]; 5685 5686 u8 reserved_at_40[0x40]; 5687 5688 struct mlx5_ifc_pkey_bits pkey[]; 5689 }; 5690 5691 struct mlx5_ifc_query_hca_vport_pkey_in_bits { 5692 u8 opcode[0x10]; 5693 u8 reserved_at_10[0x10]; 5694 5695 u8 reserved_at_20[0x10]; 5696 u8 op_mod[0x10]; 5697 5698 u8 other_vport[0x1]; 5699 u8 reserved_at_41[0xb]; 5700 u8 port_num[0x4]; 5701 u8 vport_number[0x10]; 5702 5703 u8 reserved_at_60[0x10]; 5704 u8 pkey_index[0x10]; 5705 }; 5706 5707 enum { 5708 MLX5_HCA_VPORT_SEL_PORT_GUID = 1 << 0, 5709 MLX5_HCA_VPORT_SEL_NODE_GUID = 1 << 1, 5710 MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2, 5711 }; 5712 5713 struct mlx5_ifc_query_hca_vport_gid_out_bits { 5714 u8 status[0x8]; 5715 u8 reserved_at_8[0x18]; 5716 5717 u8 syndrome[0x20]; 5718 5719 u8 reserved_at_40[0x20]; 5720 5721 u8 gids_num[0x10]; 5722 u8 reserved_at_70[0x10]; 5723 5724 struct mlx5_ifc_array128_auto_bits gid[]; 5725 }; 5726 5727 struct mlx5_ifc_query_hca_vport_gid_in_bits { 5728 u8 opcode[0x10]; 5729 u8 reserved_at_10[0x10]; 5730 5731 u8 reserved_at_20[0x10]; 5732 u8 op_mod[0x10]; 5733 5734 u8 other_vport[0x1]; 5735 u8 reserved_at_41[0xb]; 5736 u8 port_num[0x4]; 5737 u8 vport_number[0x10]; 5738 5739 u8 reserved_at_60[0x10]; 5740 u8 gid_index[0x10]; 5741 }; 5742 5743 struct mlx5_ifc_query_hca_vport_context_out_bits { 5744 u8 status[0x8]; 5745 u8 reserved_at_8[0x18]; 5746 5747 u8 syndrome[0x20]; 5748 5749 u8 reserved_at_40[0x40]; 5750 5751 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 5752 }; 5753 5754 struct mlx5_ifc_query_hca_vport_context_in_bits { 5755 u8 opcode[0x10]; 5756 u8 reserved_at_10[0x10]; 5757 5758 u8 reserved_at_20[0x10]; 5759 u8 op_mod[0x10]; 5760 5761 u8 other_vport[0x1]; 5762 u8 reserved_at_41[0xb]; 5763 u8 port_num[0x4]; 5764 u8 vport_number[0x10]; 5765 5766 u8 reserved_at_60[0x20]; 5767 }; 5768 5769 struct mlx5_ifc_query_hca_cap_out_bits { 5770 u8 status[0x8]; 5771 u8 reserved_at_8[0x18]; 5772 5773 u8 syndrome[0x20]; 5774 5775 u8 reserved_at_40[0x40]; 5776 5777 union mlx5_ifc_hca_cap_union_bits capability; 5778 }; 5779 5780 struct mlx5_ifc_query_hca_cap_in_bits { 5781 u8 opcode[0x10]; 5782 u8 reserved_at_10[0x10]; 5783 5784 u8 reserved_at_20[0x10]; 5785 u8 op_mod[0x10]; 5786 5787 u8 other_function[0x1]; 5788 u8 reserved_at_41[0xf]; 5789 u8 function_id[0x10]; 5790 5791 u8 reserved_at_60[0x20]; 5792 }; 5793 5794 struct mlx5_ifc_other_hca_cap_bits { 5795 u8 roce[0x1]; 5796 u8 reserved_at_1[0x27f]; 5797 }; 5798 5799 struct mlx5_ifc_query_other_hca_cap_out_bits { 5800 u8 status[0x8]; 5801 u8 reserved_at_8[0x18]; 5802 5803 u8 syndrome[0x20]; 5804 5805 u8 reserved_at_40[0x40]; 5806 5807 struct mlx5_ifc_other_hca_cap_bits other_capability; 5808 }; 5809 5810 struct mlx5_ifc_query_other_hca_cap_in_bits { 5811 u8 opcode[0x10]; 5812 u8 reserved_at_10[0x10]; 5813 5814 u8 reserved_at_20[0x10]; 5815 u8 op_mod[0x10]; 5816 5817 u8 reserved_at_40[0x10]; 5818 u8 function_id[0x10]; 5819 5820 u8 reserved_at_60[0x20]; 5821 }; 5822 5823 struct mlx5_ifc_modify_other_hca_cap_out_bits { 5824 u8 status[0x8]; 5825 u8 reserved_at_8[0x18]; 5826 5827 u8 syndrome[0x20]; 5828 5829 u8 reserved_at_40[0x40]; 5830 }; 5831 5832 struct mlx5_ifc_modify_other_hca_cap_in_bits { 5833 u8 opcode[0x10]; 5834 u8 reserved_at_10[0x10]; 5835 5836 u8 reserved_at_20[0x10]; 5837 u8 op_mod[0x10]; 5838 5839 u8 reserved_at_40[0x10]; 5840 u8 function_id[0x10]; 5841 u8 field_select[0x20]; 5842 5843 struct mlx5_ifc_other_hca_cap_bits other_capability; 5844 }; 5845 5846 struct mlx5_ifc_flow_table_context_bits { 5847 u8 reformat_en[0x1]; 5848 u8 decap_en[0x1]; 5849 u8 sw_owner[0x1]; 5850 u8 termination_table[0x1]; 5851 u8 table_miss_action[0x4]; 5852 u8 level[0x8]; 5853 u8 reserved_at_10[0x8]; 5854 u8 log_size[0x8]; 5855 5856 u8 reserved_at_20[0x8]; 5857 u8 table_miss_id[0x18]; 5858 5859 u8 reserved_at_40[0x8]; 5860 u8 lag_master_next_table_id[0x18]; 5861 5862 u8 reserved_at_60[0x60]; 5863 5864 u8 sw_owner_icm_root_1[0x40]; 5865 5866 u8 sw_owner_icm_root_0[0x40]; 5867 5868 }; 5869 5870 struct mlx5_ifc_query_flow_table_out_bits { 5871 u8 status[0x8]; 5872 u8 reserved_at_8[0x18]; 5873 5874 u8 syndrome[0x20]; 5875 5876 u8 reserved_at_40[0x80]; 5877 5878 struct mlx5_ifc_flow_table_context_bits flow_table_context; 5879 }; 5880 5881 struct mlx5_ifc_query_flow_table_in_bits { 5882 u8 opcode[0x10]; 5883 u8 reserved_at_10[0x10]; 5884 5885 u8 reserved_at_20[0x10]; 5886 u8 op_mod[0x10]; 5887 5888 u8 reserved_at_40[0x40]; 5889 5890 u8 table_type[0x8]; 5891 u8 reserved_at_88[0x18]; 5892 5893 u8 reserved_at_a0[0x8]; 5894 u8 table_id[0x18]; 5895 5896 u8 reserved_at_c0[0x140]; 5897 }; 5898 5899 struct mlx5_ifc_query_fte_out_bits { 5900 u8 status[0x8]; 5901 u8 reserved_at_8[0x18]; 5902 5903 u8 syndrome[0x20]; 5904 5905 u8 reserved_at_40[0x1c0]; 5906 5907 struct mlx5_ifc_flow_context_bits flow_context; 5908 }; 5909 5910 struct mlx5_ifc_query_fte_in_bits { 5911 u8 opcode[0x10]; 5912 u8 reserved_at_10[0x10]; 5913 5914 u8 reserved_at_20[0x10]; 5915 u8 op_mod[0x10]; 5916 5917 u8 reserved_at_40[0x40]; 5918 5919 u8 table_type[0x8]; 5920 u8 reserved_at_88[0x18]; 5921 5922 u8 reserved_at_a0[0x8]; 5923 u8 table_id[0x18]; 5924 5925 u8 reserved_at_c0[0x40]; 5926 5927 u8 flow_index[0x20]; 5928 5929 u8 reserved_at_120[0xe0]; 5930 }; 5931 5932 struct mlx5_ifc_match_definer_format_0_bits { 5933 u8 reserved_at_0[0x100]; 5934 5935 u8 metadata_reg_c_0[0x20]; 5936 5937 u8 metadata_reg_c_1[0x20]; 5938 5939 u8 outer_dmac_47_16[0x20]; 5940 5941 u8 outer_dmac_15_0[0x10]; 5942 u8 outer_ethertype[0x10]; 5943 5944 u8 reserved_at_180[0x1]; 5945 u8 sx_sniffer[0x1]; 5946 u8 functional_lb[0x1]; 5947 u8 outer_ip_frag[0x1]; 5948 u8 outer_qp_type[0x2]; 5949 u8 outer_encap_type[0x2]; 5950 u8 port_number[0x2]; 5951 u8 outer_l3_type[0x2]; 5952 u8 outer_l4_type[0x2]; 5953 u8 outer_first_vlan_type[0x2]; 5954 u8 outer_first_vlan_prio[0x3]; 5955 u8 outer_first_vlan_cfi[0x1]; 5956 u8 outer_first_vlan_vid[0xc]; 5957 5958 u8 outer_l4_type_ext[0x4]; 5959 u8 reserved_at_1a4[0x2]; 5960 u8 outer_ipsec_layer[0x2]; 5961 u8 outer_l2_type[0x2]; 5962 u8 force_lb[0x1]; 5963 u8 outer_l2_ok[0x1]; 5964 u8 outer_l3_ok[0x1]; 5965 u8 outer_l4_ok[0x1]; 5966 u8 outer_second_vlan_type[0x2]; 5967 u8 outer_second_vlan_prio[0x3]; 5968 u8 outer_second_vlan_cfi[0x1]; 5969 u8 outer_second_vlan_vid[0xc]; 5970 5971 u8 outer_smac_47_16[0x20]; 5972 5973 u8 outer_smac_15_0[0x10]; 5974 u8 inner_ipv4_checksum_ok[0x1]; 5975 u8 inner_l4_checksum_ok[0x1]; 5976 u8 outer_ipv4_checksum_ok[0x1]; 5977 u8 outer_l4_checksum_ok[0x1]; 5978 u8 inner_l3_ok[0x1]; 5979 u8 inner_l4_ok[0x1]; 5980 u8 outer_l3_ok_duplicate[0x1]; 5981 u8 outer_l4_ok_duplicate[0x1]; 5982 u8 outer_tcp_cwr[0x1]; 5983 u8 outer_tcp_ece[0x1]; 5984 u8 outer_tcp_urg[0x1]; 5985 u8 outer_tcp_ack[0x1]; 5986 u8 outer_tcp_psh[0x1]; 5987 u8 outer_tcp_rst[0x1]; 5988 u8 outer_tcp_syn[0x1]; 5989 u8 outer_tcp_fin[0x1]; 5990 }; 5991 5992 struct mlx5_ifc_match_definer_format_22_bits { 5993 u8 reserved_at_0[0x100]; 5994 5995 u8 outer_ip_src_addr[0x20]; 5996 5997 u8 outer_ip_dest_addr[0x20]; 5998 5999 u8 outer_l4_sport[0x10]; 6000 u8 outer_l4_dport[0x10]; 6001 6002 u8 reserved_at_160[0x1]; 6003 u8 sx_sniffer[0x1]; 6004 u8 functional_lb[0x1]; 6005 u8 outer_ip_frag[0x1]; 6006 u8 outer_qp_type[0x2]; 6007 u8 outer_encap_type[0x2]; 6008 u8 port_number[0x2]; 6009 u8 outer_l3_type[0x2]; 6010 u8 outer_l4_type[0x2]; 6011 u8 outer_first_vlan_type[0x2]; 6012 u8 outer_first_vlan_prio[0x3]; 6013 u8 outer_first_vlan_cfi[0x1]; 6014 u8 outer_first_vlan_vid[0xc]; 6015 6016 u8 metadata_reg_c_0[0x20]; 6017 6018 u8 outer_dmac_47_16[0x20]; 6019 6020 u8 outer_smac_47_16[0x20]; 6021 6022 u8 outer_smac_15_0[0x10]; 6023 u8 outer_dmac_15_0[0x10]; 6024 }; 6025 6026 struct mlx5_ifc_match_definer_format_23_bits { 6027 u8 reserved_at_0[0x100]; 6028 6029 u8 inner_ip_src_addr[0x20]; 6030 6031 u8 inner_ip_dest_addr[0x20]; 6032 6033 u8 inner_l4_sport[0x10]; 6034 u8 inner_l4_dport[0x10]; 6035 6036 u8 reserved_at_160[0x1]; 6037 u8 sx_sniffer[0x1]; 6038 u8 functional_lb[0x1]; 6039 u8 inner_ip_frag[0x1]; 6040 u8 inner_qp_type[0x2]; 6041 u8 inner_encap_type[0x2]; 6042 u8 port_number[0x2]; 6043 u8 inner_l3_type[0x2]; 6044 u8 inner_l4_type[0x2]; 6045 u8 inner_first_vlan_type[0x2]; 6046 u8 inner_first_vlan_prio[0x3]; 6047 u8 inner_first_vlan_cfi[0x1]; 6048 u8 inner_first_vlan_vid[0xc]; 6049 6050 u8 tunnel_header_0[0x20]; 6051 6052 u8 inner_dmac_47_16[0x20]; 6053 6054 u8 inner_smac_47_16[0x20]; 6055 6056 u8 inner_smac_15_0[0x10]; 6057 u8 inner_dmac_15_0[0x10]; 6058 }; 6059 6060 struct mlx5_ifc_match_definer_format_29_bits { 6061 u8 reserved_at_0[0xc0]; 6062 6063 u8 outer_ip_dest_addr[0x80]; 6064 6065 u8 outer_ip_src_addr[0x80]; 6066 6067 u8 outer_l4_sport[0x10]; 6068 u8 outer_l4_dport[0x10]; 6069 6070 u8 reserved_at_1e0[0x20]; 6071 }; 6072 6073 struct mlx5_ifc_match_definer_format_30_bits { 6074 u8 reserved_at_0[0xa0]; 6075 6076 u8 outer_ip_dest_addr[0x80]; 6077 6078 u8 outer_ip_src_addr[0x80]; 6079 6080 u8 outer_dmac_47_16[0x20]; 6081 6082 u8 outer_smac_47_16[0x20]; 6083 6084 u8 outer_smac_15_0[0x10]; 6085 u8 outer_dmac_15_0[0x10]; 6086 }; 6087 6088 struct mlx5_ifc_match_definer_format_31_bits { 6089 u8 reserved_at_0[0xc0]; 6090 6091 u8 inner_ip_dest_addr[0x80]; 6092 6093 u8 inner_ip_src_addr[0x80]; 6094 6095 u8 inner_l4_sport[0x10]; 6096 u8 inner_l4_dport[0x10]; 6097 6098 u8 reserved_at_1e0[0x20]; 6099 }; 6100 6101 struct mlx5_ifc_match_definer_format_32_bits { 6102 u8 reserved_at_0[0xa0]; 6103 6104 u8 inner_ip_dest_addr[0x80]; 6105 6106 u8 inner_ip_src_addr[0x80]; 6107 6108 u8 inner_dmac_47_16[0x20]; 6109 6110 u8 inner_smac_47_16[0x20]; 6111 6112 u8 inner_smac_15_0[0x10]; 6113 u8 inner_dmac_15_0[0x10]; 6114 }; 6115 6116 enum { 6117 MLX5_IFC_DEFINER_FORMAT_ID_SELECT = 61, 6118 }; 6119 6120 #define MLX5_IFC_DEFINER_FORMAT_OFFSET_UNUSED 0x0 6121 #define MLX5_IFC_DEFINER_FORMAT_OFFSET_OUTER_ETH_PKT_LEN 0x48 6122 #define MLX5_IFC_DEFINER_DW_SELECTORS_NUM 9 6123 #define MLX5_IFC_DEFINER_BYTE_SELECTORS_NUM 8 6124 6125 struct mlx5_ifc_match_definer_match_mask_bits { 6126 u8 reserved_at_1c0[5][0x20]; 6127 u8 match_dw_8[0x20]; 6128 u8 match_dw_7[0x20]; 6129 u8 match_dw_6[0x20]; 6130 u8 match_dw_5[0x20]; 6131 u8 match_dw_4[0x20]; 6132 u8 match_dw_3[0x20]; 6133 u8 match_dw_2[0x20]; 6134 u8 match_dw_1[0x20]; 6135 u8 match_dw_0[0x20]; 6136 6137 u8 match_byte_7[0x8]; 6138 u8 match_byte_6[0x8]; 6139 u8 match_byte_5[0x8]; 6140 u8 match_byte_4[0x8]; 6141 6142 u8 match_byte_3[0x8]; 6143 u8 match_byte_2[0x8]; 6144 u8 match_byte_1[0x8]; 6145 u8 match_byte_0[0x8]; 6146 }; 6147 6148 struct mlx5_ifc_match_definer_bits { 6149 u8 modify_field_select[0x40]; 6150 6151 u8 reserved_at_40[0x40]; 6152 6153 u8 reserved_at_80[0x10]; 6154 u8 format_id[0x10]; 6155 6156 u8 reserved_at_a0[0x60]; 6157 6158 u8 format_select_dw3[0x8]; 6159 u8 format_select_dw2[0x8]; 6160 u8 format_select_dw1[0x8]; 6161 u8 format_select_dw0[0x8]; 6162 6163 u8 format_select_dw7[0x8]; 6164 u8 format_select_dw6[0x8]; 6165 u8 format_select_dw5[0x8]; 6166 u8 format_select_dw4[0x8]; 6167 6168 u8 reserved_at_100[0x18]; 6169 u8 format_select_dw8[0x8]; 6170 6171 u8 reserved_at_120[0x20]; 6172 6173 u8 format_select_byte3[0x8]; 6174 u8 format_select_byte2[0x8]; 6175 u8 format_select_byte1[0x8]; 6176 u8 format_select_byte0[0x8]; 6177 6178 u8 format_select_byte7[0x8]; 6179 u8 format_select_byte6[0x8]; 6180 u8 format_select_byte5[0x8]; 6181 u8 format_select_byte4[0x8]; 6182 6183 u8 reserved_at_180[0x40]; 6184 6185 union { 6186 struct { 6187 u8 match_mask[16][0x20]; 6188 }; 6189 struct mlx5_ifc_match_definer_match_mask_bits match_mask_format; 6190 }; 6191 }; 6192 6193 struct mlx5_ifc_general_obj_in_cmd_hdr_bits { 6194 u8 opcode[0x10]; 6195 u8 uid[0x10]; 6196 6197 u8 vhca_tunnel_id[0x10]; 6198 u8 obj_type[0x10]; 6199 6200 u8 obj_id[0x20]; 6201 6202 u8 reserved_at_60[0x3]; 6203 u8 log_obj_range[0x5]; 6204 u8 reserved_at_68[0x18]; 6205 }; 6206 6207 struct mlx5_ifc_general_obj_out_cmd_hdr_bits { 6208 u8 status[0x8]; 6209 u8 reserved_at_8[0x18]; 6210 6211 u8 syndrome[0x20]; 6212 6213 u8 obj_id[0x20]; 6214 6215 u8 reserved_at_60[0x20]; 6216 }; 6217 6218 struct mlx5_ifc_create_match_definer_in_bits { 6219 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 6220 6221 struct mlx5_ifc_match_definer_bits obj_context; 6222 }; 6223 6224 struct mlx5_ifc_create_match_definer_out_bits { 6225 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 6226 }; 6227 6228 enum { 6229 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 6230 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 6231 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 6232 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3, 6233 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_3 = 0x4, 6234 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_4 = 0x5, 6235 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_5 = 0x6, 6236 }; 6237 6238 struct mlx5_ifc_query_flow_group_out_bits { 6239 u8 status[0x8]; 6240 u8 reserved_at_8[0x18]; 6241 6242 u8 syndrome[0x20]; 6243 6244 u8 reserved_at_40[0xa0]; 6245 6246 u8 start_flow_index[0x20]; 6247 6248 u8 reserved_at_100[0x20]; 6249 6250 u8 end_flow_index[0x20]; 6251 6252 u8 reserved_at_140[0xa0]; 6253 6254 u8 reserved_at_1e0[0x18]; 6255 u8 match_criteria_enable[0x8]; 6256 6257 struct mlx5_ifc_fte_match_param_bits match_criteria; 6258 6259 u8 reserved_at_1200[0xe00]; 6260 }; 6261 6262 struct mlx5_ifc_query_flow_group_in_bits { 6263 u8 opcode[0x10]; 6264 u8 reserved_at_10[0x10]; 6265 6266 u8 reserved_at_20[0x10]; 6267 u8 op_mod[0x10]; 6268 6269 u8 reserved_at_40[0x40]; 6270 6271 u8 table_type[0x8]; 6272 u8 reserved_at_88[0x18]; 6273 6274 u8 reserved_at_a0[0x8]; 6275 u8 table_id[0x18]; 6276 6277 u8 group_id[0x20]; 6278 6279 u8 reserved_at_e0[0x120]; 6280 }; 6281 6282 struct mlx5_ifc_query_flow_counter_out_bits { 6283 u8 status[0x8]; 6284 u8 reserved_at_8[0x18]; 6285 6286 u8 syndrome[0x20]; 6287 6288 u8 reserved_at_40[0x40]; 6289 6290 struct mlx5_ifc_traffic_counter_bits flow_statistics[]; 6291 }; 6292 6293 struct mlx5_ifc_query_flow_counter_in_bits { 6294 u8 opcode[0x10]; 6295 u8 reserved_at_10[0x10]; 6296 6297 u8 reserved_at_20[0x10]; 6298 u8 op_mod[0x10]; 6299 6300 u8 reserved_at_40[0x80]; 6301 6302 u8 clear[0x1]; 6303 u8 reserved_at_c1[0xf]; 6304 u8 num_of_counters[0x10]; 6305 6306 u8 flow_counter_id[0x20]; 6307 }; 6308 6309 struct mlx5_ifc_query_esw_vport_context_out_bits { 6310 u8 status[0x8]; 6311 u8 reserved_at_8[0x18]; 6312 6313 u8 syndrome[0x20]; 6314 6315 u8 reserved_at_40[0x40]; 6316 6317 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 6318 }; 6319 6320 struct mlx5_ifc_query_esw_vport_context_in_bits { 6321 u8 opcode[0x10]; 6322 u8 reserved_at_10[0x10]; 6323 6324 u8 reserved_at_20[0x10]; 6325 u8 op_mod[0x10]; 6326 6327 u8 other_vport[0x1]; 6328 u8 reserved_at_41[0xf]; 6329 u8 vport_number[0x10]; 6330 6331 u8 reserved_at_60[0x20]; 6332 }; 6333 6334 struct mlx5_ifc_modify_esw_vport_context_out_bits { 6335 u8 status[0x8]; 6336 u8 reserved_at_8[0x18]; 6337 6338 u8 syndrome[0x20]; 6339 6340 u8 reserved_at_40[0x40]; 6341 }; 6342 6343 struct mlx5_ifc_esw_vport_context_fields_select_bits { 6344 u8 reserved_at_0[0x1b]; 6345 u8 fdb_to_vport_reg_c_id[0x1]; 6346 u8 vport_cvlan_insert[0x1]; 6347 u8 vport_svlan_insert[0x1]; 6348 u8 vport_cvlan_strip[0x1]; 6349 u8 vport_svlan_strip[0x1]; 6350 }; 6351 6352 struct mlx5_ifc_modify_esw_vport_context_in_bits { 6353 u8 opcode[0x10]; 6354 u8 reserved_at_10[0x10]; 6355 6356 u8 reserved_at_20[0x10]; 6357 u8 op_mod[0x10]; 6358 6359 u8 other_vport[0x1]; 6360 u8 reserved_at_41[0xf]; 6361 u8 vport_number[0x10]; 6362 6363 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select; 6364 6365 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 6366 }; 6367 6368 struct mlx5_ifc_query_eq_out_bits { 6369 u8 status[0x8]; 6370 u8 reserved_at_8[0x18]; 6371 6372 u8 syndrome[0x20]; 6373 6374 u8 reserved_at_40[0x40]; 6375 6376 struct mlx5_ifc_eqc_bits eq_context_entry; 6377 6378 u8 reserved_at_280[0x40]; 6379 6380 u8 event_bitmask[0x40]; 6381 6382 u8 reserved_at_300[0x580]; 6383 6384 u8 pas[][0x40]; 6385 }; 6386 6387 struct mlx5_ifc_query_eq_in_bits { 6388 u8 opcode[0x10]; 6389 u8 reserved_at_10[0x10]; 6390 6391 u8 reserved_at_20[0x10]; 6392 u8 op_mod[0x10]; 6393 6394 u8 reserved_at_40[0x18]; 6395 u8 eq_number[0x8]; 6396 6397 u8 reserved_at_60[0x20]; 6398 }; 6399 6400 struct mlx5_ifc_packet_reformat_context_in_bits { 6401 u8 reformat_type[0x8]; 6402 u8 reserved_at_8[0x4]; 6403 u8 reformat_param_0[0x4]; 6404 u8 reserved_at_10[0x6]; 6405 u8 reformat_data_size[0xa]; 6406 6407 u8 reformat_param_1[0x8]; 6408 u8 reserved_at_28[0x8]; 6409 u8 reformat_data[2][0x8]; 6410 6411 u8 more_reformat_data[][0x8]; 6412 }; 6413 6414 struct mlx5_ifc_query_packet_reformat_context_out_bits { 6415 u8 status[0x8]; 6416 u8 reserved_at_8[0x18]; 6417 6418 u8 syndrome[0x20]; 6419 6420 u8 reserved_at_40[0xa0]; 6421 6422 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context[]; 6423 }; 6424 6425 struct mlx5_ifc_query_packet_reformat_context_in_bits { 6426 u8 opcode[0x10]; 6427 u8 reserved_at_10[0x10]; 6428 6429 u8 reserved_at_20[0x10]; 6430 u8 op_mod[0x10]; 6431 6432 u8 packet_reformat_id[0x20]; 6433 6434 u8 reserved_at_60[0xa0]; 6435 }; 6436 6437 struct mlx5_ifc_alloc_packet_reformat_context_out_bits { 6438 u8 status[0x8]; 6439 u8 reserved_at_8[0x18]; 6440 6441 u8 syndrome[0x20]; 6442 6443 u8 packet_reformat_id[0x20]; 6444 6445 u8 reserved_at_60[0x20]; 6446 }; 6447 6448 enum { 6449 MLX5_REFORMAT_CONTEXT_ANCHOR_MAC_START = 0x1, 6450 MLX5_REFORMAT_CONTEXT_ANCHOR_IP_START = 0x7, 6451 MLX5_REFORMAT_CONTEXT_ANCHOR_TCP_UDP_START = 0x9, 6452 }; 6453 6454 enum mlx5_reformat_ctx_type { 6455 MLX5_REFORMAT_TYPE_L2_TO_VXLAN = 0x0, 6456 MLX5_REFORMAT_TYPE_L2_TO_NVGRE = 0x1, 6457 MLX5_REFORMAT_TYPE_L2_TO_L2_TUNNEL = 0x2, 6458 MLX5_REFORMAT_TYPE_L3_TUNNEL_TO_L2 = 0x3, 6459 MLX5_REFORMAT_TYPE_L2_TO_L3_TUNNEL = 0x4, 6460 MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_IPV4 = 0x5, 6461 MLX5_REFORMAT_TYPE_DEL_ESP_TRANSPORT = 0x8, 6462 MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_IPV6 = 0xb, 6463 MLX5_REFORMAT_TYPE_INSERT_HDR = 0xf, 6464 MLX5_REFORMAT_TYPE_REMOVE_HDR = 0x10, 6465 MLX5_REFORMAT_TYPE_ADD_MACSEC = 0x11, 6466 MLX5_REFORMAT_TYPE_DEL_MACSEC = 0x12, 6467 }; 6468 6469 struct mlx5_ifc_alloc_packet_reformat_context_in_bits { 6470 u8 opcode[0x10]; 6471 u8 reserved_at_10[0x10]; 6472 6473 u8 reserved_at_20[0x10]; 6474 u8 op_mod[0x10]; 6475 6476 u8 reserved_at_40[0xa0]; 6477 6478 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context; 6479 }; 6480 6481 struct mlx5_ifc_dealloc_packet_reformat_context_out_bits { 6482 u8 status[0x8]; 6483 u8 reserved_at_8[0x18]; 6484 6485 u8 syndrome[0x20]; 6486 6487 u8 reserved_at_40[0x40]; 6488 }; 6489 6490 struct mlx5_ifc_dealloc_packet_reformat_context_in_bits { 6491 u8 opcode[0x10]; 6492 u8 reserved_at_10[0x10]; 6493 6494 u8 reserved_20[0x10]; 6495 u8 op_mod[0x10]; 6496 6497 u8 packet_reformat_id[0x20]; 6498 6499 u8 reserved_60[0x20]; 6500 }; 6501 6502 struct mlx5_ifc_set_action_in_bits { 6503 u8 action_type[0x4]; 6504 u8 field[0xc]; 6505 u8 reserved_at_10[0x3]; 6506 u8 offset[0x5]; 6507 u8 reserved_at_18[0x3]; 6508 u8 length[0x5]; 6509 6510 u8 data[0x20]; 6511 }; 6512 6513 struct mlx5_ifc_add_action_in_bits { 6514 u8 action_type[0x4]; 6515 u8 field[0xc]; 6516 u8 reserved_at_10[0x10]; 6517 6518 u8 data[0x20]; 6519 }; 6520 6521 struct mlx5_ifc_copy_action_in_bits { 6522 u8 action_type[0x4]; 6523 u8 src_field[0xc]; 6524 u8 reserved_at_10[0x3]; 6525 u8 src_offset[0x5]; 6526 u8 reserved_at_18[0x3]; 6527 u8 length[0x5]; 6528 6529 u8 reserved_at_20[0x4]; 6530 u8 dst_field[0xc]; 6531 u8 reserved_at_30[0x3]; 6532 u8 dst_offset[0x5]; 6533 u8 reserved_at_38[0x8]; 6534 }; 6535 6536 union mlx5_ifc_set_add_copy_action_in_auto_bits { 6537 struct mlx5_ifc_set_action_in_bits set_action_in; 6538 struct mlx5_ifc_add_action_in_bits add_action_in; 6539 struct mlx5_ifc_copy_action_in_bits copy_action_in; 6540 u8 reserved_at_0[0x40]; 6541 }; 6542 6543 enum { 6544 MLX5_ACTION_TYPE_SET = 0x1, 6545 MLX5_ACTION_TYPE_ADD = 0x2, 6546 MLX5_ACTION_TYPE_COPY = 0x3, 6547 }; 6548 6549 enum { 6550 MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16 = 0x1, 6551 MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0 = 0x2, 6552 MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE = 0x3, 6553 MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16 = 0x4, 6554 MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0 = 0x5, 6555 MLX5_ACTION_IN_FIELD_OUT_IP_DSCP = 0x6, 6556 MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS = 0x7, 6557 MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT = 0x8, 6558 MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT = 0x9, 6559 MLX5_ACTION_IN_FIELD_OUT_IP_TTL = 0xa, 6560 MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT = 0xb, 6561 MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT = 0xc, 6562 MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96 = 0xd, 6563 MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64 = 0xe, 6564 MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32 = 0xf, 6565 MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0 = 0x10, 6566 MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96 = 0x11, 6567 MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64 = 0x12, 6568 MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32 = 0x13, 6569 MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0 = 0x14, 6570 MLX5_ACTION_IN_FIELD_OUT_SIPV4 = 0x15, 6571 MLX5_ACTION_IN_FIELD_OUT_DIPV4 = 0x16, 6572 MLX5_ACTION_IN_FIELD_OUT_FIRST_VID = 0x17, 6573 MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47, 6574 MLX5_ACTION_IN_FIELD_METADATA_REG_A = 0x49, 6575 MLX5_ACTION_IN_FIELD_METADATA_REG_B = 0x50, 6576 MLX5_ACTION_IN_FIELD_METADATA_REG_C_0 = 0x51, 6577 MLX5_ACTION_IN_FIELD_METADATA_REG_C_1 = 0x52, 6578 MLX5_ACTION_IN_FIELD_METADATA_REG_C_2 = 0x53, 6579 MLX5_ACTION_IN_FIELD_METADATA_REG_C_3 = 0x54, 6580 MLX5_ACTION_IN_FIELD_METADATA_REG_C_4 = 0x55, 6581 MLX5_ACTION_IN_FIELD_METADATA_REG_C_5 = 0x56, 6582 MLX5_ACTION_IN_FIELD_METADATA_REG_C_6 = 0x57, 6583 MLX5_ACTION_IN_FIELD_METADATA_REG_C_7 = 0x58, 6584 MLX5_ACTION_IN_FIELD_OUT_TCP_SEQ_NUM = 0x59, 6585 MLX5_ACTION_IN_FIELD_OUT_TCP_ACK_NUM = 0x5B, 6586 MLX5_ACTION_IN_FIELD_IPSEC_SYNDROME = 0x5D, 6587 MLX5_ACTION_IN_FIELD_OUT_EMD_47_32 = 0x6F, 6588 MLX5_ACTION_IN_FIELD_OUT_EMD_31_0 = 0x70, 6589 }; 6590 6591 struct mlx5_ifc_alloc_modify_header_context_out_bits { 6592 u8 status[0x8]; 6593 u8 reserved_at_8[0x18]; 6594 6595 u8 syndrome[0x20]; 6596 6597 u8 modify_header_id[0x20]; 6598 6599 u8 reserved_at_60[0x20]; 6600 }; 6601 6602 struct mlx5_ifc_alloc_modify_header_context_in_bits { 6603 u8 opcode[0x10]; 6604 u8 reserved_at_10[0x10]; 6605 6606 u8 reserved_at_20[0x10]; 6607 u8 op_mod[0x10]; 6608 6609 u8 reserved_at_40[0x20]; 6610 6611 u8 table_type[0x8]; 6612 u8 reserved_at_68[0x10]; 6613 u8 num_of_actions[0x8]; 6614 6615 union mlx5_ifc_set_add_copy_action_in_auto_bits actions[]; 6616 }; 6617 6618 struct mlx5_ifc_dealloc_modify_header_context_out_bits { 6619 u8 status[0x8]; 6620 u8 reserved_at_8[0x18]; 6621 6622 u8 syndrome[0x20]; 6623 6624 u8 reserved_at_40[0x40]; 6625 }; 6626 6627 struct mlx5_ifc_dealloc_modify_header_context_in_bits { 6628 u8 opcode[0x10]; 6629 u8 reserved_at_10[0x10]; 6630 6631 u8 reserved_at_20[0x10]; 6632 u8 op_mod[0x10]; 6633 6634 u8 modify_header_id[0x20]; 6635 6636 u8 reserved_at_60[0x20]; 6637 }; 6638 6639 struct mlx5_ifc_query_modify_header_context_in_bits { 6640 u8 opcode[0x10]; 6641 u8 uid[0x10]; 6642 6643 u8 reserved_at_20[0x10]; 6644 u8 op_mod[0x10]; 6645 6646 u8 modify_header_id[0x20]; 6647 6648 u8 reserved_at_60[0xa0]; 6649 }; 6650 6651 struct mlx5_ifc_query_dct_out_bits { 6652 u8 status[0x8]; 6653 u8 reserved_at_8[0x18]; 6654 6655 u8 syndrome[0x20]; 6656 6657 u8 reserved_at_40[0x40]; 6658 6659 struct mlx5_ifc_dctc_bits dct_context_entry; 6660 6661 u8 reserved_at_280[0x180]; 6662 }; 6663 6664 struct mlx5_ifc_query_dct_in_bits { 6665 u8 opcode[0x10]; 6666 u8 reserved_at_10[0x10]; 6667 6668 u8 reserved_at_20[0x10]; 6669 u8 op_mod[0x10]; 6670 6671 u8 reserved_at_40[0x8]; 6672 u8 dctn[0x18]; 6673 6674 u8 reserved_at_60[0x20]; 6675 }; 6676 6677 struct mlx5_ifc_query_cq_out_bits { 6678 u8 status[0x8]; 6679 u8 reserved_at_8[0x18]; 6680 6681 u8 syndrome[0x20]; 6682 6683 u8 reserved_at_40[0x40]; 6684 6685 struct mlx5_ifc_cqc_bits cq_context; 6686 6687 u8 reserved_at_280[0x600]; 6688 6689 u8 pas[][0x40]; 6690 }; 6691 6692 struct mlx5_ifc_query_cq_in_bits { 6693 u8 opcode[0x10]; 6694 u8 reserved_at_10[0x10]; 6695 6696 u8 reserved_at_20[0x10]; 6697 u8 op_mod[0x10]; 6698 6699 u8 reserved_at_40[0x8]; 6700 u8 cqn[0x18]; 6701 6702 u8 reserved_at_60[0x20]; 6703 }; 6704 6705 struct mlx5_ifc_query_cong_status_out_bits { 6706 u8 status[0x8]; 6707 u8 reserved_at_8[0x18]; 6708 6709 u8 syndrome[0x20]; 6710 6711 u8 reserved_at_40[0x20]; 6712 6713 u8 enable[0x1]; 6714 u8 tag_enable[0x1]; 6715 u8 reserved_at_62[0x1e]; 6716 }; 6717 6718 struct mlx5_ifc_query_cong_status_in_bits { 6719 u8 opcode[0x10]; 6720 u8 reserved_at_10[0x10]; 6721 6722 u8 reserved_at_20[0x10]; 6723 u8 op_mod[0x10]; 6724 6725 u8 reserved_at_40[0x18]; 6726 u8 priority[0x4]; 6727 u8 cong_protocol[0x4]; 6728 6729 u8 reserved_at_60[0x20]; 6730 }; 6731 6732 struct mlx5_ifc_query_cong_statistics_out_bits { 6733 u8 status[0x8]; 6734 u8 reserved_at_8[0x18]; 6735 6736 u8 syndrome[0x20]; 6737 6738 u8 reserved_at_40[0x40]; 6739 6740 u8 rp_cur_flows[0x20]; 6741 6742 u8 sum_flows[0x20]; 6743 6744 u8 rp_cnp_ignored_high[0x20]; 6745 6746 u8 rp_cnp_ignored_low[0x20]; 6747 6748 u8 rp_cnp_handled_high[0x20]; 6749 6750 u8 rp_cnp_handled_low[0x20]; 6751 6752 u8 reserved_at_140[0x100]; 6753 6754 u8 time_stamp_high[0x20]; 6755 6756 u8 time_stamp_low[0x20]; 6757 6758 u8 accumulators_period[0x20]; 6759 6760 u8 np_ecn_marked_roce_packets_high[0x20]; 6761 6762 u8 np_ecn_marked_roce_packets_low[0x20]; 6763 6764 u8 np_cnp_sent_high[0x20]; 6765 6766 u8 np_cnp_sent_low[0x20]; 6767 6768 u8 reserved_at_320[0x560]; 6769 }; 6770 6771 struct mlx5_ifc_query_cong_statistics_in_bits { 6772 u8 opcode[0x10]; 6773 u8 reserved_at_10[0x10]; 6774 6775 u8 reserved_at_20[0x10]; 6776 u8 op_mod[0x10]; 6777 6778 u8 clear[0x1]; 6779 u8 reserved_at_41[0x1f]; 6780 6781 u8 reserved_at_60[0x20]; 6782 }; 6783 6784 struct mlx5_ifc_query_cong_params_out_bits { 6785 u8 status[0x8]; 6786 u8 reserved_at_8[0x18]; 6787 6788 u8 syndrome[0x20]; 6789 6790 u8 reserved_at_40[0x40]; 6791 6792 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 6793 }; 6794 6795 struct mlx5_ifc_query_cong_params_in_bits { 6796 u8 opcode[0x10]; 6797 u8 reserved_at_10[0x10]; 6798 6799 u8 reserved_at_20[0x10]; 6800 u8 op_mod[0x10]; 6801 6802 u8 reserved_at_40[0x1c]; 6803 u8 cong_protocol[0x4]; 6804 6805 u8 reserved_at_60[0x20]; 6806 }; 6807 6808 struct mlx5_ifc_query_adapter_out_bits { 6809 u8 status[0x8]; 6810 u8 reserved_at_8[0x18]; 6811 6812 u8 syndrome[0x20]; 6813 6814 u8 reserved_at_40[0x40]; 6815 6816 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct; 6817 }; 6818 6819 struct mlx5_ifc_query_adapter_in_bits { 6820 u8 opcode[0x10]; 6821 u8 reserved_at_10[0x10]; 6822 6823 u8 reserved_at_20[0x10]; 6824 u8 op_mod[0x10]; 6825 6826 u8 reserved_at_40[0x40]; 6827 }; 6828 6829 struct mlx5_ifc_qp_2rst_out_bits { 6830 u8 status[0x8]; 6831 u8 reserved_at_8[0x18]; 6832 6833 u8 syndrome[0x20]; 6834 6835 u8 reserved_at_40[0x40]; 6836 }; 6837 6838 struct mlx5_ifc_qp_2rst_in_bits { 6839 u8 opcode[0x10]; 6840 u8 uid[0x10]; 6841 6842 u8 reserved_at_20[0x10]; 6843 u8 op_mod[0x10]; 6844 6845 u8 reserved_at_40[0x8]; 6846 u8 qpn[0x18]; 6847 6848 u8 reserved_at_60[0x20]; 6849 }; 6850 6851 struct mlx5_ifc_qp_2err_out_bits { 6852 u8 status[0x8]; 6853 u8 reserved_at_8[0x18]; 6854 6855 u8 syndrome[0x20]; 6856 6857 u8 reserved_at_40[0x40]; 6858 }; 6859 6860 struct mlx5_ifc_qp_2err_in_bits { 6861 u8 opcode[0x10]; 6862 u8 uid[0x10]; 6863 6864 u8 reserved_at_20[0x10]; 6865 u8 op_mod[0x10]; 6866 6867 u8 reserved_at_40[0x8]; 6868 u8 qpn[0x18]; 6869 6870 u8 reserved_at_60[0x20]; 6871 }; 6872 6873 struct mlx5_ifc_page_fault_resume_out_bits { 6874 u8 status[0x8]; 6875 u8 reserved_at_8[0x18]; 6876 6877 u8 syndrome[0x20]; 6878 6879 u8 reserved_at_40[0x40]; 6880 }; 6881 6882 struct mlx5_ifc_page_fault_resume_in_bits { 6883 u8 opcode[0x10]; 6884 u8 reserved_at_10[0x10]; 6885 6886 u8 reserved_at_20[0x10]; 6887 u8 op_mod[0x10]; 6888 6889 u8 error[0x1]; 6890 u8 reserved_at_41[0x4]; 6891 u8 page_fault_type[0x3]; 6892 u8 wq_number[0x18]; 6893 6894 u8 reserved_at_60[0x8]; 6895 u8 token[0x18]; 6896 }; 6897 6898 struct mlx5_ifc_nop_out_bits { 6899 u8 status[0x8]; 6900 u8 reserved_at_8[0x18]; 6901 6902 u8 syndrome[0x20]; 6903 6904 u8 reserved_at_40[0x40]; 6905 }; 6906 6907 struct mlx5_ifc_nop_in_bits { 6908 u8 opcode[0x10]; 6909 u8 reserved_at_10[0x10]; 6910 6911 u8 reserved_at_20[0x10]; 6912 u8 op_mod[0x10]; 6913 6914 u8 reserved_at_40[0x40]; 6915 }; 6916 6917 struct mlx5_ifc_modify_vport_state_out_bits { 6918 u8 status[0x8]; 6919 u8 reserved_at_8[0x18]; 6920 6921 u8 syndrome[0x20]; 6922 6923 u8 reserved_at_40[0x40]; 6924 }; 6925 6926 struct mlx5_ifc_modify_vport_state_in_bits { 6927 u8 opcode[0x10]; 6928 u8 reserved_at_10[0x10]; 6929 6930 u8 reserved_at_20[0x10]; 6931 u8 op_mod[0x10]; 6932 6933 u8 other_vport[0x1]; 6934 u8 reserved_at_41[0xf]; 6935 u8 vport_number[0x10]; 6936 6937 u8 reserved_at_60[0x18]; 6938 u8 admin_state[0x4]; 6939 u8 reserved_at_7c[0x4]; 6940 }; 6941 6942 struct mlx5_ifc_modify_tis_out_bits { 6943 u8 status[0x8]; 6944 u8 reserved_at_8[0x18]; 6945 6946 u8 syndrome[0x20]; 6947 6948 u8 reserved_at_40[0x40]; 6949 }; 6950 6951 struct mlx5_ifc_modify_tis_bitmask_bits { 6952 u8 reserved_at_0[0x20]; 6953 6954 u8 reserved_at_20[0x1d]; 6955 u8 lag_tx_port_affinity[0x1]; 6956 u8 strict_lag_tx_port_affinity[0x1]; 6957 u8 prio[0x1]; 6958 }; 6959 6960 struct mlx5_ifc_modify_tis_in_bits { 6961 u8 opcode[0x10]; 6962 u8 uid[0x10]; 6963 6964 u8 reserved_at_20[0x10]; 6965 u8 op_mod[0x10]; 6966 6967 u8 reserved_at_40[0x8]; 6968 u8 tisn[0x18]; 6969 6970 u8 reserved_at_60[0x20]; 6971 6972 struct mlx5_ifc_modify_tis_bitmask_bits bitmask; 6973 6974 u8 reserved_at_c0[0x40]; 6975 6976 struct mlx5_ifc_tisc_bits ctx; 6977 }; 6978 6979 struct mlx5_ifc_modify_tir_bitmask_bits { 6980 u8 reserved_at_0[0x20]; 6981 6982 u8 reserved_at_20[0x1b]; 6983 u8 self_lb_en[0x1]; 6984 u8 reserved_at_3c[0x1]; 6985 u8 hash[0x1]; 6986 u8 reserved_at_3e[0x1]; 6987 u8 packet_merge[0x1]; 6988 }; 6989 6990 struct mlx5_ifc_modify_tir_out_bits { 6991 u8 status[0x8]; 6992 u8 reserved_at_8[0x18]; 6993 6994 u8 syndrome[0x20]; 6995 6996 u8 reserved_at_40[0x40]; 6997 }; 6998 6999 struct mlx5_ifc_modify_tir_in_bits { 7000 u8 opcode[0x10]; 7001 u8 uid[0x10]; 7002 7003 u8 reserved_at_20[0x10]; 7004 u8 op_mod[0x10]; 7005 7006 u8 reserved_at_40[0x8]; 7007 u8 tirn[0x18]; 7008 7009 u8 reserved_at_60[0x20]; 7010 7011 struct mlx5_ifc_modify_tir_bitmask_bits bitmask; 7012 7013 u8 reserved_at_c0[0x40]; 7014 7015 struct mlx5_ifc_tirc_bits ctx; 7016 }; 7017 7018 struct mlx5_ifc_modify_sq_out_bits { 7019 u8 status[0x8]; 7020 u8 reserved_at_8[0x18]; 7021 7022 u8 syndrome[0x20]; 7023 7024 u8 reserved_at_40[0x40]; 7025 }; 7026 7027 struct mlx5_ifc_modify_sq_in_bits { 7028 u8 opcode[0x10]; 7029 u8 uid[0x10]; 7030 7031 u8 reserved_at_20[0x10]; 7032 u8 op_mod[0x10]; 7033 7034 u8 sq_state[0x4]; 7035 u8 reserved_at_44[0x4]; 7036 u8 sqn[0x18]; 7037 7038 u8 reserved_at_60[0x20]; 7039 7040 u8 modify_bitmask[0x40]; 7041 7042 u8 reserved_at_c0[0x40]; 7043 7044 struct mlx5_ifc_sqc_bits ctx; 7045 }; 7046 7047 struct mlx5_ifc_modify_scheduling_element_out_bits { 7048 u8 status[0x8]; 7049 u8 reserved_at_8[0x18]; 7050 7051 u8 syndrome[0x20]; 7052 7053 u8 reserved_at_40[0x1c0]; 7054 }; 7055 7056 enum { 7057 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1, 7058 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2, 7059 }; 7060 7061 struct mlx5_ifc_modify_scheduling_element_in_bits { 7062 u8 opcode[0x10]; 7063 u8 reserved_at_10[0x10]; 7064 7065 u8 reserved_at_20[0x10]; 7066 u8 op_mod[0x10]; 7067 7068 u8 scheduling_hierarchy[0x8]; 7069 u8 reserved_at_48[0x18]; 7070 7071 u8 scheduling_element_id[0x20]; 7072 7073 u8 reserved_at_80[0x20]; 7074 7075 u8 modify_bitmask[0x20]; 7076 7077 u8 reserved_at_c0[0x40]; 7078 7079 struct mlx5_ifc_scheduling_context_bits scheduling_context; 7080 7081 u8 reserved_at_300[0x100]; 7082 }; 7083 7084 struct mlx5_ifc_modify_rqt_out_bits { 7085 u8 status[0x8]; 7086 u8 reserved_at_8[0x18]; 7087 7088 u8 syndrome[0x20]; 7089 7090 u8 reserved_at_40[0x40]; 7091 }; 7092 7093 struct mlx5_ifc_rqt_bitmask_bits { 7094 u8 reserved_at_0[0x20]; 7095 7096 u8 reserved_at_20[0x1f]; 7097 u8 rqn_list[0x1]; 7098 }; 7099 7100 struct mlx5_ifc_modify_rqt_in_bits { 7101 u8 opcode[0x10]; 7102 u8 uid[0x10]; 7103 7104 u8 reserved_at_20[0x10]; 7105 u8 op_mod[0x10]; 7106 7107 u8 reserved_at_40[0x8]; 7108 u8 rqtn[0x18]; 7109 7110 u8 reserved_at_60[0x20]; 7111 7112 struct mlx5_ifc_rqt_bitmask_bits bitmask; 7113 7114 u8 reserved_at_c0[0x40]; 7115 7116 struct mlx5_ifc_rqtc_bits ctx; 7117 }; 7118 7119 struct mlx5_ifc_modify_rq_out_bits { 7120 u8 status[0x8]; 7121 u8 reserved_at_8[0x18]; 7122 7123 u8 syndrome[0x20]; 7124 7125 u8 reserved_at_40[0x40]; 7126 }; 7127 7128 enum { 7129 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1, 7130 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2, 7131 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3, 7132 }; 7133 7134 struct mlx5_ifc_modify_rq_in_bits { 7135 u8 opcode[0x10]; 7136 u8 uid[0x10]; 7137 7138 u8 reserved_at_20[0x10]; 7139 u8 op_mod[0x10]; 7140 7141 u8 rq_state[0x4]; 7142 u8 reserved_at_44[0x4]; 7143 u8 rqn[0x18]; 7144 7145 u8 reserved_at_60[0x20]; 7146 7147 u8 modify_bitmask[0x40]; 7148 7149 u8 reserved_at_c0[0x40]; 7150 7151 struct mlx5_ifc_rqc_bits ctx; 7152 }; 7153 7154 struct mlx5_ifc_modify_rmp_out_bits { 7155 u8 status[0x8]; 7156 u8 reserved_at_8[0x18]; 7157 7158 u8 syndrome[0x20]; 7159 7160 u8 reserved_at_40[0x40]; 7161 }; 7162 7163 struct mlx5_ifc_rmp_bitmask_bits { 7164 u8 reserved_at_0[0x20]; 7165 7166 u8 reserved_at_20[0x1f]; 7167 u8 lwm[0x1]; 7168 }; 7169 7170 struct mlx5_ifc_modify_rmp_in_bits { 7171 u8 opcode[0x10]; 7172 u8 uid[0x10]; 7173 7174 u8 reserved_at_20[0x10]; 7175 u8 op_mod[0x10]; 7176 7177 u8 rmp_state[0x4]; 7178 u8 reserved_at_44[0x4]; 7179 u8 rmpn[0x18]; 7180 7181 u8 reserved_at_60[0x20]; 7182 7183 struct mlx5_ifc_rmp_bitmask_bits bitmask; 7184 7185 u8 reserved_at_c0[0x40]; 7186 7187 struct mlx5_ifc_rmpc_bits ctx; 7188 }; 7189 7190 struct mlx5_ifc_modify_nic_vport_context_out_bits { 7191 u8 status[0x8]; 7192 u8 reserved_at_8[0x18]; 7193 7194 u8 syndrome[0x20]; 7195 7196 u8 reserved_at_40[0x40]; 7197 }; 7198 7199 struct mlx5_ifc_modify_nic_vport_field_select_bits { 7200 u8 reserved_at_0[0x12]; 7201 u8 affiliation[0x1]; 7202 u8 reserved_at_13[0x1]; 7203 u8 disable_uc_local_lb[0x1]; 7204 u8 disable_mc_local_lb[0x1]; 7205 u8 node_guid[0x1]; 7206 u8 port_guid[0x1]; 7207 u8 min_inline[0x1]; 7208 u8 mtu[0x1]; 7209 u8 change_event[0x1]; 7210 u8 promisc[0x1]; 7211 u8 permanent_address[0x1]; 7212 u8 addresses_list[0x1]; 7213 u8 roce_en[0x1]; 7214 u8 reserved_at_1f[0x1]; 7215 }; 7216 7217 struct mlx5_ifc_modify_nic_vport_context_in_bits { 7218 u8 opcode[0x10]; 7219 u8 reserved_at_10[0x10]; 7220 7221 u8 reserved_at_20[0x10]; 7222 u8 op_mod[0x10]; 7223 7224 u8 other_vport[0x1]; 7225 u8 reserved_at_41[0xf]; 7226 u8 vport_number[0x10]; 7227 7228 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select; 7229 7230 u8 reserved_at_80[0x780]; 7231 7232 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 7233 }; 7234 7235 struct mlx5_ifc_modify_hca_vport_context_out_bits { 7236 u8 status[0x8]; 7237 u8 reserved_at_8[0x18]; 7238 7239 u8 syndrome[0x20]; 7240 7241 u8 reserved_at_40[0x40]; 7242 }; 7243 7244 struct mlx5_ifc_modify_hca_vport_context_in_bits { 7245 u8 opcode[0x10]; 7246 u8 reserved_at_10[0x10]; 7247 7248 u8 reserved_at_20[0x10]; 7249 u8 op_mod[0x10]; 7250 7251 u8 other_vport[0x1]; 7252 u8 reserved_at_41[0xb]; 7253 u8 port_num[0x4]; 7254 u8 vport_number[0x10]; 7255 7256 u8 reserved_at_60[0x20]; 7257 7258 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 7259 }; 7260 7261 struct mlx5_ifc_modify_cq_out_bits { 7262 u8 status[0x8]; 7263 u8 reserved_at_8[0x18]; 7264 7265 u8 syndrome[0x20]; 7266 7267 u8 reserved_at_40[0x40]; 7268 }; 7269 7270 enum { 7271 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0, 7272 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1, 7273 }; 7274 7275 struct mlx5_ifc_modify_cq_in_bits { 7276 u8 opcode[0x10]; 7277 u8 uid[0x10]; 7278 7279 u8 reserved_at_20[0x10]; 7280 u8 op_mod[0x10]; 7281 7282 u8 reserved_at_40[0x8]; 7283 u8 cqn[0x18]; 7284 7285 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select; 7286 7287 struct mlx5_ifc_cqc_bits cq_context; 7288 7289 u8 reserved_at_280[0x60]; 7290 7291 u8 cq_umem_valid[0x1]; 7292 u8 reserved_at_2e1[0x1f]; 7293 7294 u8 reserved_at_300[0x580]; 7295 7296 u8 pas[][0x40]; 7297 }; 7298 7299 struct mlx5_ifc_modify_cong_status_out_bits { 7300 u8 status[0x8]; 7301 u8 reserved_at_8[0x18]; 7302 7303 u8 syndrome[0x20]; 7304 7305 u8 reserved_at_40[0x40]; 7306 }; 7307 7308 struct mlx5_ifc_modify_cong_status_in_bits { 7309 u8 opcode[0x10]; 7310 u8 reserved_at_10[0x10]; 7311 7312 u8 reserved_at_20[0x10]; 7313 u8 op_mod[0x10]; 7314 7315 u8 reserved_at_40[0x18]; 7316 u8 priority[0x4]; 7317 u8 cong_protocol[0x4]; 7318 7319 u8 enable[0x1]; 7320 u8 tag_enable[0x1]; 7321 u8 reserved_at_62[0x1e]; 7322 }; 7323 7324 struct mlx5_ifc_modify_cong_params_out_bits { 7325 u8 status[0x8]; 7326 u8 reserved_at_8[0x18]; 7327 7328 u8 syndrome[0x20]; 7329 7330 u8 reserved_at_40[0x40]; 7331 }; 7332 7333 struct mlx5_ifc_modify_cong_params_in_bits { 7334 u8 opcode[0x10]; 7335 u8 reserved_at_10[0x10]; 7336 7337 u8 reserved_at_20[0x10]; 7338 u8 op_mod[0x10]; 7339 7340 u8 reserved_at_40[0x1c]; 7341 u8 cong_protocol[0x4]; 7342 7343 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select; 7344 7345 u8 reserved_at_80[0x80]; 7346 7347 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 7348 }; 7349 7350 struct mlx5_ifc_manage_pages_out_bits { 7351 u8 status[0x8]; 7352 u8 reserved_at_8[0x18]; 7353 7354 u8 syndrome[0x20]; 7355 7356 u8 output_num_entries[0x20]; 7357 7358 u8 reserved_at_60[0x20]; 7359 7360 u8 pas[][0x40]; 7361 }; 7362 7363 enum { 7364 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL = 0x0, 7365 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS = 0x1, 7366 MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES = 0x2, 7367 }; 7368 7369 struct mlx5_ifc_manage_pages_in_bits { 7370 u8 opcode[0x10]; 7371 u8 reserved_at_10[0x10]; 7372 7373 u8 reserved_at_20[0x10]; 7374 u8 op_mod[0x10]; 7375 7376 u8 embedded_cpu_function[0x1]; 7377 u8 reserved_at_41[0xf]; 7378 u8 function_id[0x10]; 7379 7380 u8 input_num_entries[0x20]; 7381 7382 u8 pas[][0x40]; 7383 }; 7384 7385 struct mlx5_ifc_mad_ifc_out_bits { 7386 u8 status[0x8]; 7387 u8 reserved_at_8[0x18]; 7388 7389 u8 syndrome[0x20]; 7390 7391 u8 reserved_at_40[0x40]; 7392 7393 u8 response_mad_packet[256][0x8]; 7394 }; 7395 7396 struct mlx5_ifc_mad_ifc_in_bits { 7397 u8 opcode[0x10]; 7398 u8 reserved_at_10[0x10]; 7399 7400 u8 reserved_at_20[0x10]; 7401 u8 op_mod[0x10]; 7402 7403 u8 remote_lid[0x10]; 7404 u8 reserved_at_50[0x8]; 7405 u8 port[0x8]; 7406 7407 u8 reserved_at_60[0x20]; 7408 7409 u8 mad[256][0x8]; 7410 }; 7411 7412 struct mlx5_ifc_init_hca_out_bits { 7413 u8 status[0x8]; 7414 u8 reserved_at_8[0x18]; 7415 7416 u8 syndrome[0x20]; 7417 7418 u8 reserved_at_40[0x40]; 7419 }; 7420 7421 struct mlx5_ifc_init_hca_in_bits { 7422 u8 opcode[0x10]; 7423 u8 reserved_at_10[0x10]; 7424 7425 u8 reserved_at_20[0x10]; 7426 u8 op_mod[0x10]; 7427 7428 u8 reserved_at_40[0x20]; 7429 7430 u8 reserved_at_60[0x2]; 7431 u8 sw_vhca_id[0xe]; 7432 u8 reserved_at_70[0x10]; 7433 7434 u8 sw_owner_id[4][0x20]; 7435 }; 7436 7437 struct mlx5_ifc_init2rtr_qp_out_bits { 7438 u8 status[0x8]; 7439 u8 reserved_at_8[0x18]; 7440 7441 u8 syndrome[0x20]; 7442 7443 u8 reserved_at_40[0x20]; 7444 u8 ece[0x20]; 7445 }; 7446 7447 struct mlx5_ifc_init2rtr_qp_in_bits { 7448 u8 opcode[0x10]; 7449 u8 uid[0x10]; 7450 7451 u8 reserved_at_20[0x10]; 7452 u8 op_mod[0x10]; 7453 7454 u8 reserved_at_40[0x8]; 7455 u8 qpn[0x18]; 7456 7457 u8 reserved_at_60[0x20]; 7458 7459 u8 opt_param_mask[0x20]; 7460 7461 u8 ece[0x20]; 7462 7463 struct mlx5_ifc_qpc_bits qpc; 7464 7465 u8 reserved_at_800[0x80]; 7466 }; 7467 7468 struct mlx5_ifc_init2init_qp_out_bits { 7469 u8 status[0x8]; 7470 u8 reserved_at_8[0x18]; 7471 7472 u8 syndrome[0x20]; 7473 7474 u8 reserved_at_40[0x20]; 7475 u8 ece[0x20]; 7476 }; 7477 7478 struct mlx5_ifc_init2init_qp_in_bits { 7479 u8 opcode[0x10]; 7480 u8 uid[0x10]; 7481 7482 u8 reserved_at_20[0x10]; 7483 u8 op_mod[0x10]; 7484 7485 u8 reserved_at_40[0x8]; 7486 u8 qpn[0x18]; 7487 7488 u8 reserved_at_60[0x20]; 7489 7490 u8 opt_param_mask[0x20]; 7491 7492 u8 ece[0x20]; 7493 7494 struct mlx5_ifc_qpc_bits qpc; 7495 7496 u8 reserved_at_800[0x80]; 7497 }; 7498 7499 struct mlx5_ifc_get_dropped_packet_log_out_bits { 7500 u8 status[0x8]; 7501 u8 reserved_at_8[0x18]; 7502 7503 u8 syndrome[0x20]; 7504 7505 u8 reserved_at_40[0x40]; 7506 7507 u8 packet_headers_log[128][0x8]; 7508 7509 u8 packet_syndrome[64][0x8]; 7510 }; 7511 7512 struct mlx5_ifc_get_dropped_packet_log_in_bits { 7513 u8 opcode[0x10]; 7514 u8 reserved_at_10[0x10]; 7515 7516 u8 reserved_at_20[0x10]; 7517 u8 op_mod[0x10]; 7518 7519 u8 reserved_at_40[0x40]; 7520 }; 7521 7522 struct mlx5_ifc_gen_eqe_in_bits { 7523 u8 opcode[0x10]; 7524 u8 reserved_at_10[0x10]; 7525 7526 u8 reserved_at_20[0x10]; 7527 u8 op_mod[0x10]; 7528 7529 u8 reserved_at_40[0x18]; 7530 u8 eq_number[0x8]; 7531 7532 u8 reserved_at_60[0x20]; 7533 7534 u8 eqe[64][0x8]; 7535 }; 7536 7537 struct mlx5_ifc_gen_eq_out_bits { 7538 u8 status[0x8]; 7539 u8 reserved_at_8[0x18]; 7540 7541 u8 syndrome[0x20]; 7542 7543 u8 reserved_at_40[0x40]; 7544 }; 7545 7546 struct mlx5_ifc_enable_hca_out_bits { 7547 u8 status[0x8]; 7548 u8 reserved_at_8[0x18]; 7549 7550 u8 syndrome[0x20]; 7551 7552 u8 reserved_at_40[0x20]; 7553 }; 7554 7555 struct mlx5_ifc_enable_hca_in_bits { 7556 u8 opcode[0x10]; 7557 u8 reserved_at_10[0x10]; 7558 7559 u8 reserved_at_20[0x10]; 7560 u8 op_mod[0x10]; 7561 7562 u8 embedded_cpu_function[0x1]; 7563 u8 reserved_at_41[0xf]; 7564 u8 function_id[0x10]; 7565 7566 u8 reserved_at_60[0x20]; 7567 }; 7568 7569 struct mlx5_ifc_drain_dct_out_bits { 7570 u8 status[0x8]; 7571 u8 reserved_at_8[0x18]; 7572 7573 u8 syndrome[0x20]; 7574 7575 u8 reserved_at_40[0x40]; 7576 }; 7577 7578 struct mlx5_ifc_drain_dct_in_bits { 7579 u8 opcode[0x10]; 7580 u8 uid[0x10]; 7581 7582 u8 reserved_at_20[0x10]; 7583 u8 op_mod[0x10]; 7584 7585 u8 reserved_at_40[0x8]; 7586 u8 dctn[0x18]; 7587 7588 u8 reserved_at_60[0x20]; 7589 }; 7590 7591 struct mlx5_ifc_disable_hca_out_bits { 7592 u8 status[0x8]; 7593 u8 reserved_at_8[0x18]; 7594 7595 u8 syndrome[0x20]; 7596 7597 u8 reserved_at_40[0x20]; 7598 }; 7599 7600 struct mlx5_ifc_disable_hca_in_bits { 7601 u8 opcode[0x10]; 7602 u8 reserved_at_10[0x10]; 7603 7604 u8 reserved_at_20[0x10]; 7605 u8 op_mod[0x10]; 7606 7607 u8 embedded_cpu_function[0x1]; 7608 u8 reserved_at_41[0xf]; 7609 u8 function_id[0x10]; 7610 7611 u8 reserved_at_60[0x20]; 7612 }; 7613 7614 struct mlx5_ifc_detach_from_mcg_out_bits { 7615 u8 status[0x8]; 7616 u8 reserved_at_8[0x18]; 7617 7618 u8 syndrome[0x20]; 7619 7620 u8 reserved_at_40[0x40]; 7621 }; 7622 7623 struct mlx5_ifc_detach_from_mcg_in_bits { 7624 u8 opcode[0x10]; 7625 u8 uid[0x10]; 7626 7627 u8 reserved_at_20[0x10]; 7628 u8 op_mod[0x10]; 7629 7630 u8 reserved_at_40[0x8]; 7631 u8 qpn[0x18]; 7632 7633 u8 reserved_at_60[0x20]; 7634 7635 u8 multicast_gid[16][0x8]; 7636 }; 7637 7638 struct mlx5_ifc_destroy_xrq_out_bits { 7639 u8 status[0x8]; 7640 u8 reserved_at_8[0x18]; 7641 7642 u8 syndrome[0x20]; 7643 7644 u8 reserved_at_40[0x40]; 7645 }; 7646 7647 struct mlx5_ifc_destroy_xrq_in_bits { 7648 u8 opcode[0x10]; 7649 u8 uid[0x10]; 7650 7651 u8 reserved_at_20[0x10]; 7652 u8 op_mod[0x10]; 7653 7654 u8 reserved_at_40[0x8]; 7655 u8 xrqn[0x18]; 7656 7657 u8 reserved_at_60[0x20]; 7658 }; 7659 7660 struct mlx5_ifc_destroy_xrc_srq_out_bits { 7661 u8 status[0x8]; 7662 u8 reserved_at_8[0x18]; 7663 7664 u8 syndrome[0x20]; 7665 7666 u8 reserved_at_40[0x40]; 7667 }; 7668 7669 struct mlx5_ifc_destroy_xrc_srq_in_bits { 7670 u8 opcode[0x10]; 7671 u8 uid[0x10]; 7672 7673 u8 reserved_at_20[0x10]; 7674 u8 op_mod[0x10]; 7675 7676 u8 reserved_at_40[0x8]; 7677 u8 xrc_srqn[0x18]; 7678 7679 u8 reserved_at_60[0x20]; 7680 }; 7681 7682 struct mlx5_ifc_destroy_tis_out_bits { 7683 u8 status[0x8]; 7684 u8 reserved_at_8[0x18]; 7685 7686 u8 syndrome[0x20]; 7687 7688 u8 reserved_at_40[0x40]; 7689 }; 7690 7691 struct mlx5_ifc_destroy_tis_in_bits { 7692 u8 opcode[0x10]; 7693 u8 uid[0x10]; 7694 7695 u8 reserved_at_20[0x10]; 7696 u8 op_mod[0x10]; 7697 7698 u8 reserved_at_40[0x8]; 7699 u8 tisn[0x18]; 7700 7701 u8 reserved_at_60[0x20]; 7702 }; 7703 7704 struct mlx5_ifc_destroy_tir_out_bits { 7705 u8 status[0x8]; 7706 u8 reserved_at_8[0x18]; 7707 7708 u8 syndrome[0x20]; 7709 7710 u8 reserved_at_40[0x40]; 7711 }; 7712 7713 struct mlx5_ifc_destroy_tir_in_bits { 7714 u8 opcode[0x10]; 7715 u8 uid[0x10]; 7716 7717 u8 reserved_at_20[0x10]; 7718 u8 op_mod[0x10]; 7719 7720 u8 reserved_at_40[0x8]; 7721 u8 tirn[0x18]; 7722 7723 u8 reserved_at_60[0x20]; 7724 }; 7725 7726 struct mlx5_ifc_destroy_srq_out_bits { 7727 u8 status[0x8]; 7728 u8 reserved_at_8[0x18]; 7729 7730 u8 syndrome[0x20]; 7731 7732 u8 reserved_at_40[0x40]; 7733 }; 7734 7735 struct mlx5_ifc_destroy_srq_in_bits { 7736 u8 opcode[0x10]; 7737 u8 uid[0x10]; 7738 7739 u8 reserved_at_20[0x10]; 7740 u8 op_mod[0x10]; 7741 7742 u8 reserved_at_40[0x8]; 7743 u8 srqn[0x18]; 7744 7745 u8 reserved_at_60[0x20]; 7746 }; 7747 7748 struct mlx5_ifc_destroy_sq_out_bits { 7749 u8 status[0x8]; 7750 u8 reserved_at_8[0x18]; 7751 7752 u8 syndrome[0x20]; 7753 7754 u8 reserved_at_40[0x40]; 7755 }; 7756 7757 struct mlx5_ifc_destroy_sq_in_bits { 7758 u8 opcode[0x10]; 7759 u8 uid[0x10]; 7760 7761 u8 reserved_at_20[0x10]; 7762 u8 op_mod[0x10]; 7763 7764 u8 reserved_at_40[0x8]; 7765 u8 sqn[0x18]; 7766 7767 u8 reserved_at_60[0x20]; 7768 }; 7769 7770 struct mlx5_ifc_destroy_scheduling_element_out_bits { 7771 u8 status[0x8]; 7772 u8 reserved_at_8[0x18]; 7773 7774 u8 syndrome[0x20]; 7775 7776 u8 reserved_at_40[0x1c0]; 7777 }; 7778 7779 struct mlx5_ifc_destroy_scheduling_element_in_bits { 7780 u8 opcode[0x10]; 7781 u8 reserved_at_10[0x10]; 7782 7783 u8 reserved_at_20[0x10]; 7784 u8 op_mod[0x10]; 7785 7786 u8 scheduling_hierarchy[0x8]; 7787 u8 reserved_at_48[0x18]; 7788 7789 u8 scheduling_element_id[0x20]; 7790 7791 u8 reserved_at_80[0x180]; 7792 }; 7793 7794 struct mlx5_ifc_destroy_rqt_out_bits { 7795 u8 status[0x8]; 7796 u8 reserved_at_8[0x18]; 7797 7798 u8 syndrome[0x20]; 7799 7800 u8 reserved_at_40[0x40]; 7801 }; 7802 7803 struct mlx5_ifc_destroy_rqt_in_bits { 7804 u8 opcode[0x10]; 7805 u8 uid[0x10]; 7806 7807 u8 reserved_at_20[0x10]; 7808 u8 op_mod[0x10]; 7809 7810 u8 reserved_at_40[0x8]; 7811 u8 rqtn[0x18]; 7812 7813 u8 reserved_at_60[0x20]; 7814 }; 7815 7816 struct mlx5_ifc_destroy_rq_out_bits { 7817 u8 status[0x8]; 7818 u8 reserved_at_8[0x18]; 7819 7820 u8 syndrome[0x20]; 7821 7822 u8 reserved_at_40[0x40]; 7823 }; 7824 7825 struct mlx5_ifc_destroy_rq_in_bits { 7826 u8 opcode[0x10]; 7827 u8 uid[0x10]; 7828 7829 u8 reserved_at_20[0x10]; 7830 u8 op_mod[0x10]; 7831 7832 u8 reserved_at_40[0x8]; 7833 u8 rqn[0x18]; 7834 7835 u8 reserved_at_60[0x20]; 7836 }; 7837 7838 struct mlx5_ifc_set_delay_drop_params_in_bits { 7839 u8 opcode[0x10]; 7840 u8 reserved_at_10[0x10]; 7841 7842 u8 reserved_at_20[0x10]; 7843 u8 op_mod[0x10]; 7844 7845 u8 reserved_at_40[0x20]; 7846 7847 u8 reserved_at_60[0x10]; 7848 u8 delay_drop_timeout[0x10]; 7849 }; 7850 7851 struct mlx5_ifc_set_delay_drop_params_out_bits { 7852 u8 status[0x8]; 7853 u8 reserved_at_8[0x18]; 7854 7855 u8 syndrome[0x20]; 7856 7857 u8 reserved_at_40[0x40]; 7858 }; 7859 7860 struct mlx5_ifc_destroy_rmp_out_bits { 7861 u8 status[0x8]; 7862 u8 reserved_at_8[0x18]; 7863 7864 u8 syndrome[0x20]; 7865 7866 u8 reserved_at_40[0x40]; 7867 }; 7868 7869 struct mlx5_ifc_destroy_rmp_in_bits { 7870 u8 opcode[0x10]; 7871 u8 uid[0x10]; 7872 7873 u8 reserved_at_20[0x10]; 7874 u8 op_mod[0x10]; 7875 7876 u8 reserved_at_40[0x8]; 7877 u8 rmpn[0x18]; 7878 7879 u8 reserved_at_60[0x20]; 7880 }; 7881 7882 struct mlx5_ifc_destroy_qp_out_bits { 7883 u8 status[0x8]; 7884 u8 reserved_at_8[0x18]; 7885 7886 u8 syndrome[0x20]; 7887 7888 u8 reserved_at_40[0x40]; 7889 }; 7890 7891 struct mlx5_ifc_destroy_qp_in_bits { 7892 u8 opcode[0x10]; 7893 u8 uid[0x10]; 7894 7895 u8 reserved_at_20[0x10]; 7896 u8 op_mod[0x10]; 7897 7898 u8 reserved_at_40[0x8]; 7899 u8 qpn[0x18]; 7900 7901 u8 reserved_at_60[0x20]; 7902 }; 7903 7904 struct mlx5_ifc_destroy_psv_out_bits { 7905 u8 status[0x8]; 7906 u8 reserved_at_8[0x18]; 7907 7908 u8 syndrome[0x20]; 7909 7910 u8 reserved_at_40[0x40]; 7911 }; 7912 7913 struct mlx5_ifc_destroy_psv_in_bits { 7914 u8 opcode[0x10]; 7915 u8 reserved_at_10[0x10]; 7916 7917 u8 reserved_at_20[0x10]; 7918 u8 op_mod[0x10]; 7919 7920 u8 reserved_at_40[0x8]; 7921 u8 psvn[0x18]; 7922 7923 u8 reserved_at_60[0x20]; 7924 }; 7925 7926 struct mlx5_ifc_destroy_mkey_out_bits { 7927 u8 status[0x8]; 7928 u8 reserved_at_8[0x18]; 7929 7930 u8 syndrome[0x20]; 7931 7932 u8 reserved_at_40[0x40]; 7933 }; 7934 7935 struct mlx5_ifc_destroy_mkey_in_bits { 7936 u8 opcode[0x10]; 7937 u8 uid[0x10]; 7938 7939 u8 reserved_at_20[0x10]; 7940 u8 op_mod[0x10]; 7941 7942 u8 reserved_at_40[0x8]; 7943 u8 mkey_index[0x18]; 7944 7945 u8 reserved_at_60[0x20]; 7946 }; 7947 7948 struct mlx5_ifc_destroy_flow_table_out_bits { 7949 u8 status[0x8]; 7950 u8 reserved_at_8[0x18]; 7951 7952 u8 syndrome[0x20]; 7953 7954 u8 reserved_at_40[0x40]; 7955 }; 7956 7957 struct mlx5_ifc_destroy_flow_table_in_bits { 7958 u8 opcode[0x10]; 7959 u8 reserved_at_10[0x10]; 7960 7961 u8 reserved_at_20[0x10]; 7962 u8 op_mod[0x10]; 7963 7964 u8 other_vport[0x1]; 7965 u8 reserved_at_41[0xf]; 7966 u8 vport_number[0x10]; 7967 7968 u8 reserved_at_60[0x20]; 7969 7970 u8 table_type[0x8]; 7971 u8 reserved_at_88[0x18]; 7972 7973 u8 reserved_at_a0[0x8]; 7974 u8 table_id[0x18]; 7975 7976 u8 reserved_at_c0[0x140]; 7977 }; 7978 7979 struct mlx5_ifc_destroy_flow_group_out_bits { 7980 u8 status[0x8]; 7981 u8 reserved_at_8[0x18]; 7982 7983 u8 syndrome[0x20]; 7984 7985 u8 reserved_at_40[0x40]; 7986 }; 7987 7988 struct mlx5_ifc_destroy_flow_group_in_bits { 7989 u8 opcode[0x10]; 7990 u8 reserved_at_10[0x10]; 7991 7992 u8 reserved_at_20[0x10]; 7993 u8 op_mod[0x10]; 7994 7995 u8 other_vport[0x1]; 7996 u8 reserved_at_41[0xf]; 7997 u8 vport_number[0x10]; 7998 7999 u8 reserved_at_60[0x20]; 8000 8001 u8 table_type[0x8]; 8002 u8 reserved_at_88[0x18]; 8003 8004 u8 reserved_at_a0[0x8]; 8005 u8 table_id[0x18]; 8006 8007 u8 group_id[0x20]; 8008 8009 u8 reserved_at_e0[0x120]; 8010 }; 8011 8012 struct mlx5_ifc_destroy_eq_out_bits { 8013 u8 status[0x8]; 8014 u8 reserved_at_8[0x18]; 8015 8016 u8 syndrome[0x20]; 8017 8018 u8 reserved_at_40[0x40]; 8019 }; 8020 8021 struct mlx5_ifc_destroy_eq_in_bits { 8022 u8 opcode[0x10]; 8023 u8 reserved_at_10[0x10]; 8024 8025 u8 reserved_at_20[0x10]; 8026 u8 op_mod[0x10]; 8027 8028 u8 reserved_at_40[0x18]; 8029 u8 eq_number[0x8]; 8030 8031 u8 reserved_at_60[0x20]; 8032 }; 8033 8034 struct mlx5_ifc_destroy_dct_out_bits { 8035 u8 status[0x8]; 8036 u8 reserved_at_8[0x18]; 8037 8038 u8 syndrome[0x20]; 8039 8040 u8 reserved_at_40[0x40]; 8041 }; 8042 8043 struct mlx5_ifc_destroy_dct_in_bits { 8044 u8 opcode[0x10]; 8045 u8 uid[0x10]; 8046 8047 u8 reserved_at_20[0x10]; 8048 u8 op_mod[0x10]; 8049 8050 u8 reserved_at_40[0x8]; 8051 u8 dctn[0x18]; 8052 8053 u8 reserved_at_60[0x20]; 8054 }; 8055 8056 struct mlx5_ifc_destroy_cq_out_bits { 8057 u8 status[0x8]; 8058 u8 reserved_at_8[0x18]; 8059 8060 u8 syndrome[0x20]; 8061 8062 u8 reserved_at_40[0x40]; 8063 }; 8064 8065 struct mlx5_ifc_destroy_cq_in_bits { 8066 u8 opcode[0x10]; 8067 u8 uid[0x10]; 8068 8069 u8 reserved_at_20[0x10]; 8070 u8 op_mod[0x10]; 8071 8072 u8 reserved_at_40[0x8]; 8073 u8 cqn[0x18]; 8074 8075 u8 reserved_at_60[0x20]; 8076 }; 8077 8078 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits { 8079 u8 status[0x8]; 8080 u8 reserved_at_8[0x18]; 8081 8082 u8 syndrome[0x20]; 8083 8084 u8 reserved_at_40[0x40]; 8085 }; 8086 8087 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits { 8088 u8 opcode[0x10]; 8089 u8 reserved_at_10[0x10]; 8090 8091 u8 reserved_at_20[0x10]; 8092 u8 op_mod[0x10]; 8093 8094 u8 reserved_at_40[0x20]; 8095 8096 u8 reserved_at_60[0x10]; 8097 u8 vxlan_udp_port[0x10]; 8098 }; 8099 8100 struct mlx5_ifc_delete_l2_table_entry_out_bits { 8101 u8 status[0x8]; 8102 u8 reserved_at_8[0x18]; 8103 8104 u8 syndrome[0x20]; 8105 8106 u8 reserved_at_40[0x40]; 8107 }; 8108 8109 struct mlx5_ifc_delete_l2_table_entry_in_bits { 8110 u8 opcode[0x10]; 8111 u8 reserved_at_10[0x10]; 8112 8113 u8 reserved_at_20[0x10]; 8114 u8 op_mod[0x10]; 8115 8116 u8 reserved_at_40[0x60]; 8117 8118 u8 reserved_at_a0[0x8]; 8119 u8 table_index[0x18]; 8120 8121 u8 reserved_at_c0[0x140]; 8122 }; 8123 8124 struct mlx5_ifc_delete_fte_out_bits { 8125 u8 status[0x8]; 8126 u8 reserved_at_8[0x18]; 8127 8128 u8 syndrome[0x20]; 8129 8130 u8 reserved_at_40[0x40]; 8131 }; 8132 8133 struct mlx5_ifc_delete_fte_in_bits { 8134 u8 opcode[0x10]; 8135 u8 reserved_at_10[0x10]; 8136 8137 u8 reserved_at_20[0x10]; 8138 u8 op_mod[0x10]; 8139 8140 u8 other_vport[0x1]; 8141 u8 reserved_at_41[0xf]; 8142 u8 vport_number[0x10]; 8143 8144 u8 reserved_at_60[0x20]; 8145 8146 u8 table_type[0x8]; 8147 u8 reserved_at_88[0x18]; 8148 8149 u8 reserved_at_a0[0x8]; 8150 u8 table_id[0x18]; 8151 8152 u8 reserved_at_c0[0x40]; 8153 8154 u8 flow_index[0x20]; 8155 8156 u8 reserved_at_120[0xe0]; 8157 }; 8158 8159 struct mlx5_ifc_dealloc_xrcd_out_bits { 8160 u8 status[0x8]; 8161 u8 reserved_at_8[0x18]; 8162 8163 u8 syndrome[0x20]; 8164 8165 u8 reserved_at_40[0x40]; 8166 }; 8167 8168 struct mlx5_ifc_dealloc_xrcd_in_bits { 8169 u8 opcode[0x10]; 8170 u8 uid[0x10]; 8171 8172 u8 reserved_at_20[0x10]; 8173 u8 op_mod[0x10]; 8174 8175 u8 reserved_at_40[0x8]; 8176 u8 xrcd[0x18]; 8177 8178 u8 reserved_at_60[0x20]; 8179 }; 8180 8181 struct mlx5_ifc_dealloc_uar_out_bits { 8182 u8 status[0x8]; 8183 u8 reserved_at_8[0x18]; 8184 8185 u8 syndrome[0x20]; 8186 8187 u8 reserved_at_40[0x40]; 8188 }; 8189 8190 struct mlx5_ifc_dealloc_uar_in_bits { 8191 u8 opcode[0x10]; 8192 u8 uid[0x10]; 8193 8194 u8 reserved_at_20[0x10]; 8195 u8 op_mod[0x10]; 8196 8197 u8 reserved_at_40[0x8]; 8198 u8 uar[0x18]; 8199 8200 u8 reserved_at_60[0x20]; 8201 }; 8202 8203 struct mlx5_ifc_dealloc_transport_domain_out_bits { 8204 u8 status[0x8]; 8205 u8 reserved_at_8[0x18]; 8206 8207 u8 syndrome[0x20]; 8208 8209 u8 reserved_at_40[0x40]; 8210 }; 8211 8212 struct mlx5_ifc_dealloc_transport_domain_in_bits { 8213 u8 opcode[0x10]; 8214 u8 uid[0x10]; 8215 8216 u8 reserved_at_20[0x10]; 8217 u8 op_mod[0x10]; 8218 8219 u8 reserved_at_40[0x8]; 8220 u8 transport_domain[0x18]; 8221 8222 u8 reserved_at_60[0x20]; 8223 }; 8224 8225 struct mlx5_ifc_dealloc_q_counter_out_bits { 8226 u8 status[0x8]; 8227 u8 reserved_at_8[0x18]; 8228 8229 u8 syndrome[0x20]; 8230 8231 u8 reserved_at_40[0x40]; 8232 }; 8233 8234 struct mlx5_ifc_dealloc_q_counter_in_bits { 8235 u8 opcode[0x10]; 8236 u8 reserved_at_10[0x10]; 8237 8238 u8 reserved_at_20[0x10]; 8239 u8 op_mod[0x10]; 8240 8241 u8 reserved_at_40[0x18]; 8242 u8 counter_set_id[0x8]; 8243 8244 u8 reserved_at_60[0x20]; 8245 }; 8246 8247 struct mlx5_ifc_dealloc_pd_out_bits { 8248 u8 status[0x8]; 8249 u8 reserved_at_8[0x18]; 8250 8251 u8 syndrome[0x20]; 8252 8253 u8 reserved_at_40[0x40]; 8254 }; 8255 8256 struct mlx5_ifc_dealloc_pd_in_bits { 8257 u8 opcode[0x10]; 8258 u8 uid[0x10]; 8259 8260 u8 reserved_at_20[0x10]; 8261 u8 op_mod[0x10]; 8262 8263 u8 reserved_at_40[0x8]; 8264 u8 pd[0x18]; 8265 8266 u8 reserved_at_60[0x20]; 8267 }; 8268 8269 struct mlx5_ifc_dealloc_flow_counter_out_bits { 8270 u8 status[0x8]; 8271 u8 reserved_at_8[0x18]; 8272 8273 u8 syndrome[0x20]; 8274 8275 u8 reserved_at_40[0x40]; 8276 }; 8277 8278 struct mlx5_ifc_dealloc_flow_counter_in_bits { 8279 u8 opcode[0x10]; 8280 u8 reserved_at_10[0x10]; 8281 8282 u8 reserved_at_20[0x10]; 8283 u8 op_mod[0x10]; 8284 8285 u8 flow_counter_id[0x20]; 8286 8287 u8 reserved_at_60[0x20]; 8288 }; 8289 8290 struct mlx5_ifc_create_xrq_out_bits { 8291 u8 status[0x8]; 8292 u8 reserved_at_8[0x18]; 8293 8294 u8 syndrome[0x20]; 8295 8296 u8 reserved_at_40[0x8]; 8297 u8 xrqn[0x18]; 8298 8299 u8 reserved_at_60[0x20]; 8300 }; 8301 8302 struct mlx5_ifc_create_xrq_in_bits { 8303 u8 opcode[0x10]; 8304 u8 uid[0x10]; 8305 8306 u8 reserved_at_20[0x10]; 8307 u8 op_mod[0x10]; 8308 8309 u8 reserved_at_40[0x40]; 8310 8311 struct mlx5_ifc_xrqc_bits xrq_context; 8312 }; 8313 8314 struct mlx5_ifc_create_xrc_srq_out_bits { 8315 u8 status[0x8]; 8316 u8 reserved_at_8[0x18]; 8317 8318 u8 syndrome[0x20]; 8319 8320 u8 reserved_at_40[0x8]; 8321 u8 xrc_srqn[0x18]; 8322 8323 u8 reserved_at_60[0x20]; 8324 }; 8325 8326 struct mlx5_ifc_create_xrc_srq_in_bits { 8327 u8 opcode[0x10]; 8328 u8 uid[0x10]; 8329 8330 u8 reserved_at_20[0x10]; 8331 u8 op_mod[0x10]; 8332 8333 u8 reserved_at_40[0x40]; 8334 8335 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 8336 8337 u8 reserved_at_280[0x60]; 8338 8339 u8 xrc_srq_umem_valid[0x1]; 8340 u8 reserved_at_2e1[0x1f]; 8341 8342 u8 reserved_at_300[0x580]; 8343 8344 u8 pas[][0x40]; 8345 }; 8346 8347 struct mlx5_ifc_create_tis_out_bits { 8348 u8 status[0x8]; 8349 u8 reserved_at_8[0x18]; 8350 8351 u8 syndrome[0x20]; 8352 8353 u8 reserved_at_40[0x8]; 8354 u8 tisn[0x18]; 8355 8356 u8 reserved_at_60[0x20]; 8357 }; 8358 8359 struct mlx5_ifc_create_tis_in_bits { 8360 u8 opcode[0x10]; 8361 u8 uid[0x10]; 8362 8363 u8 reserved_at_20[0x10]; 8364 u8 op_mod[0x10]; 8365 8366 u8 reserved_at_40[0xc0]; 8367 8368 struct mlx5_ifc_tisc_bits ctx; 8369 }; 8370 8371 struct mlx5_ifc_create_tir_out_bits { 8372 u8 status[0x8]; 8373 u8 icm_address_63_40[0x18]; 8374 8375 u8 syndrome[0x20]; 8376 8377 u8 icm_address_39_32[0x8]; 8378 u8 tirn[0x18]; 8379 8380 u8 icm_address_31_0[0x20]; 8381 }; 8382 8383 struct mlx5_ifc_create_tir_in_bits { 8384 u8 opcode[0x10]; 8385 u8 uid[0x10]; 8386 8387 u8 reserved_at_20[0x10]; 8388 u8 op_mod[0x10]; 8389 8390 u8 reserved_at_40[0xc0]; 8391 8392 struct mlx5_ifc_tirc_bits ctx; 8393 }; 8394 8395 struct mlx5_ifc_create_srq_out_bits { 8396 u8 status[0x8]; 8397 u8 reserved_at_8[0x18]; 8398 8399 u8 syndrome[0x20]; 8400 8401 u8 reserved_at_40[0x8]; 8402 u8 srqn[0x18]; 8403 8404 u8 reserved_at_60[0x20]; 8405 }; 8406 8407 struct mlx5_ifc_create_srq_in_bits { 8408 u8 opcode[0x10]; 8409 u8 uid[0x10]; 8410 8411 u8 reserved_at_20[0x10]; 8412 u8 op_mod[0x10]; 8413 8414 u8 reserved_at_40[0x40]; 8415 8416 struct mlx5_ifc_srqc_bits srq_context_entry; 8417 8418 u8 reserved_at_280[0x600]; 8419 8420 u8 pas[][0x40]; 8421 }; 8422 8423 struct mlx5_ifc_create_sq_out_bits { 8424 u8 status[0x8]; 8425 u8 reserved_at_8[0x18]; 8426 8427 u8 syndrome[0x20]; 8428 8429 u8 reserved_at_40[0x8]; 8430 u8 sqn[0x18]; 8431 8432 u8 reserved_at_60[0x20]; 8433 }; 8434 8435 struct mlx5_ifc_create_sq_in_bits { 8436 u8 opcode[0x10]; 8437 u8 uid[0x10]; 8438 8439 u8 reserved_at_20[0x10]; 8440 u8 op_mod[0x10]; 8441 8442 u8 reserved_at_40[0xc0]; 8443 8444 struct mlx5_ifc_sqc_bits ctx; 8445 }; 8446 8447 struct mlx5_ifc_create_scheduling_element_out_bits { 8448 u8 status[0x8]; 8449 u8 reserved_at_8[0x18]; 8450 8451 u8 syndrome[0x20]; 8452 8453 u8 reserved_at_40[0x40]; 8454 8455 u8 scheduling_element_id[0x20]; 8456 8457 u8 reserved_at_a0[0x160]; 8458 }; 8459 8460 struct mlx5_ifc_create_scheduling_element_in_bits { 8461 u8 opcode[0x10]; 8462 u8 reserved_at_10[0x10]; 8463 8464 u8 reserved_at_20[0x10]; 8465 u8 op_mod[0x10]; 8466 8467 u8 scheduling_hierarchy[0x8]; 8468 u8 reserved_at_48[0x18]; 8469 8470 u8 reserved_at_60[0xa0]; 8471 8472 struct mlx5_ifc_scheduling_context_bits scheduling_context; 8473 8474 u8 reserved_at_300[0x100]; 8475 }; 8476 8477 struct mlx5_ifc_create_rqt_out_bits { 8478 u8 status[0x8]; 8479 u8 reserved_at_8[0x18]; 8480 8481 u8 syndrome[0x20]; 8482 8483 u8 reserved_at_40[0x8]; 8484 u8 rqtn[0x18]; 8485 8486 u8 reserved_at_60[0x20]; 8487 }; 8488 8489 struct mlx5_ifc_create_rqt_in_bits { 8490 u8 opcode[0x10]; 8491 u8 uid[0x10]; 8492 8493 u8 reserved_at_20[0x10]; 8494 u8 op_mod[0x10]; 8495 8496 u8 reserved_at_40[0xc0]; 8497 8498 struct mlx5_ifc_rqtc_bits rqt_context; 8499 }; 8500 8501 struct mlx5_ifc_create_rq_out_bits { 8502 u8 status[0x8]; 8503 u8 reserved_at_8[0x18]; 8504 8505 u8 syndrome[0x20]; 8506 8507 u8 reserved_at_40[0x8]; 8508 u8 rqn[0x18]; 8509 8510 u8 reserved_at_60[0x20]; 8511 }; 8512 8513 struct mlx5_ifc_create_rq_in_bits { 8514 u8 opcode[0x10]; 8515 u8 uid[0x10]; 8516 8517 u8 reserved_at_20[0x10]; 8518 u8 op_mod[0x10]; 8519 8520 u8 reserved_at_40[0xc0]; 8521 8522 struct mlx5_ifc_rqc_bits ctx; 8523 }; 8524 8525 struct mlx5_ifc_create_rmp_out_bits { 8526 u8 status[0x8]; 8527 u8 reserved_at_8[0x18]; 8528 8529 u8 syndrome[0x20]; 8530 8531 u8 reserved_at_40[0x8]; 8532 u8 rmpn[0x18]; 8533 8534 u8 reserved_at_60[0x20]; 8535 }; 8536 8537 struct mlx5_ifc_create_rmp_in_bits { 8538 u8 opcode[0x10]; 8539 u8 uid[0x10]; 8540 8541 u8 reserved_at_20[0x10]; 8542 u8 op_mod[0x10]; 8543 8544 u8 reserved_at_40[0xc0]; 8545 8546 struct mlx5_ifc_rmpc_bits ctx; 8547 }; 8548 8549 struct mlx5_ifc_create_qp_out_bits { 8550 u8 status[0x8]; 8551 u8 reserved_at_8[0x18]; 8552 8553 u8 syndrome[0x20]; 8554 8555 u8 reserved_at_40[0x8]; 8556 u8 qpn[0x18]; 8557 8558 u8 ece[0x20]; 8559 }; 8560 8561 struct mlx5_ifc_create_qp_in_bits { 8562 u8 opcode[0x10]; 8563 u8 uid[0x10]; 8564 8565 u8 reserved_at_20[0x10]; 8566 u8 op_mod[0x10]; 8567 8568 u8 reserved_at_40[0x8]; 8569 u8 input_qpn[0x18]; 8570 8571 u8 reserved_at_60[0x20]; 8572 u8 opt_param_mask[0x20]; 8573 8574 u8 ece[0x20]; 8575 8576 struct mlx5_ifc_qpc_bits qpc; 8577 8578 u8 reserved_at_800[0x60]; 8579 8580 u8 wq_umem_valid[0x1]; 8581 u8 reserved_at_861[0x1f]; 8582 8583 u8 pas[][0x40]; 8584 }; 8585 8586 struct mlx5_ifc_create_psv_out_bits { 8587 u8 status[0x8]; 8588 u8 reserved_at_8[0x18]; 8589 8590 u8 syndrome[0x20]; 8591 8592 u8 reserved_at_40[0x40]; 8593 8594 u8 reserved_at_80[0x8]; 8595 u8 psv0_index[0x18]; 8596 8597 u8 reserved_at_a0[0x8]; 8598 u8 psv1_index[0x18]; 8599 8600 u8 reserved_at_c0[0x8]; 8601 u8 psv2_index[0x18]; 8602 8603 u8 reserved_at_e0[0x8]; 8604 u8 psv3_index[0x18]; 8605 }; 8606 8607 struct mlx5_ifc_create_psv_in_bits { 8608 u8 opcode[0x10]; 8609 u8 reserved_at_10[0x10]; 8610 8611 u8 reserved_at_20[0x10]; 8612 u8 op_mod[0x10]; 8613 8614 u8 num_psv[0x4]; 8615 u8 reserved_at_44[0x4]; 8616 u8 pd[0x18]; 8617 8618 u8 reserved_at_60[0x20]; 8619 }; 8620 8621 struct mlx5_ifc_create_mkey_out_bits { 8622 u8 status[0x8]; 8623 u8 reserved_at_8[0x18]; 8624 8625 u8 syndrome[0x20]; 8626 8627 u8 reserved_at_40[0x8]; 8628 u8 mkey_index[0x18]; 8629 8630 u8 reserved_at_60[0x20]; 8631 }; 8632 8633 struct mlx5_ifc_create_mkey_in_bits { 8634 u8 opcode[0x10]; 8635 u8 uid[0x10]; 8636 8637 u8 reserved_at_20[0x10]; 8638 u8 op_mod[0x10]; 8639 8640 u8 reserved_at_40[0x20]; 8641 8642 u8 pg_access[0x1]; 8643 u8 mkey_umem_valid[0x1]; 8644 u8 reserved_at_62[0x1e]; 8645 8646 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 8647 8648 u8 reserved_at_280[0x80]; 8649 8650 u8 translations_octword_actual_size[0x20]; 8651 8652 u8 reserved_at_320[0x560]; 8653 8654 u8 klm_pas_mtt[][0x20]; 8655 }; 8656 8657 enum { 8658 MLX5_FLOW_TABLE_TYPE_NIC_RX = 0x0, 8659 MLX5_FLOW_TABLE_TYPE_NIC_TX = 0x1, 8660 MLX5_FLOW_TABLE_TYPE_ESW_EGRESS_ACL = 0x2, 8661 MLX5_FLOW_TABLE_TYPE_ESW_INGRESS_ACL = 0x3, 8662 MLX5_FLOW_TABLE_TYPE_FDB = 0X4, 8663 MLX5_FLOW_TABLE_TYPE_SNIFFER_RX = 0X5, 8664 MLX5_FLOW_TABLE_TYPE_SNIFFER_TX = 0X6, 8665 }; 8666 8667 struct mlx5_ifc_create_flow_table_out_bits { 8668 u8 status[0x8]; 8669 u8 icm_address_63_40[0x18]; 8670 8671 u8 syndrome[0x20]; 8672 8673 u8 icm_address_39_32[0x8]; 8674 u8 table_id[0x18]; 8675 8676 u8 icm_address_31_0[0x20]; 8677 }; 8678 8679 struct mlx5_ifc_create_flow_table_in_bits { 8680 u8 opcode[0x10]; 8681 u8 uid[0x10]; 8682 8683 u8 reserved_at_20[0x10]; 8684 u8 op_mod[0x10]; 8685 8686 u8 other_vport[0x1]; 8687 u8 reserved_at_41[0xf]; 8688 u8 vport_number[0x10]; 8689 8690 u8 reserved_at_60[0x20]; 8691 8692 u8 table_type[0x8]; 8693 u8 reserved_at_88[0x18]; 8694 8695 u8 reserved_at_a0[0x20]; 8696 8697 struct mlx5_ifc_flow_table_context_bits flow_table_context; 8698 }; 8699 8700 struct mlx5_ifc_create_flow_group_out_bits { 8701 u8 status[0x8]; 8702 u8 reserved_at_8[0x18]; 8703 8704 u8 syndrome[0x20]; 8705 8706 u8 reserved_at_40[0x8]; 8707 u8 group_id[0x18]; 8708 8709 u8 reserved_at_60[0x20]; 8710 }; 8711 8712 enum { 8713 MLX5_CREATE_FLOW_GROUP_IN_GROUP_TYPE_TCAM_SUBTABLE = 0x0, 8714 MLX5_CREATE_FLOW_GROUP_IN_GROUP_TYPE_HASH_SPLIT = 0x1, 8715 }; 8716 8717 enum { 8718 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 8719 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 8720 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 8721 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3, 8722 }; 8723 8724 struct mlx5_ifc_create_flow_group_in_bits { 8725 u8 opcode[0x10]; 8726 u8 reserved_at_10[0x10]; 8727 8728 u8 reserved_at_20[0x10]; 8729 u8 op_mod[0x10]; 8730 8731 u8 other_vport[0x1]; 8732 u8 reserved_at_41[0xf]; 8733 u8 vport_number[0x10]; 8734 8735 u8 reserved_at_60[0x20]; 8736 8737 u8 table_type[0x8]; 8738 u8 reserved_at_88[0x4]; 8739 u8 group_type[0x4]; 8740 u8 reserved_at_90[0x10]; 8741 8742 u8 reserved_at_a0[0x8]; 8743 u8 table_id[0x18]; 8744 8745 u8 source_eswitch_owner_vhca_id_valid[0x1]; 8746 8747 u8 reserved_at_c1[0x1f]; 8748 8749 u8 start_flow_index[0x20]; 8750 8751 u8 reserved_at_100[0x20]; 8752 8753 u8 end_flow_index[0x20]; 8754 8755 u8 reserved_at_140[0x10]; 8756 u8 match_definer_id[0x10]; 8757 8758 u8 reserved_at_160[0x80]; 8759 8760 u8 reserved_at_1e0[0x18]; 8761 u8 match_criteria_enable[0x8]; 8762 8763 struct mlx5_ifc_fte_match_param_bits match_criteria; 8764 8765 u8 reserved_at_1200[0xe00]; 8766 }; 8767 8768 struct mlx5_ifc_create_eq_out_bits { 8769 u8 status[0x8]; 8770 u8 reserved_at_8[0x18]; 8771 8772 u8 syndrome[0x20]; 8773 8774 u8 reserved_at_40[0x18]; 8775 u8 eq_number[0x8]; 8776 8777 u8 reserved_at_60[0x20]; 8778 }; 8779 8780 struct mlx5_ifc_create_eq_in_bits { 8781 u8 opcode[0x10]; 8782 u8 uid[0x10]; 8783 8784 u8 reserved_at_20[0x10]; 8785 u8 op_mod[0x10]; 8786 8787 u8 reserved_at_40[0x40]; 8788 8789 struct mlx5_ifc_eqc_bits eq_context_entry; 8790 8791 u8 reserved_at_280[0x40]; 8792 8793 u8 event_bitmask[4][0x40]; 8794 8795 u8 reserved_at_3c0[0x4c0]; 8796 8797 u8 pas[][0x40]; 8798 }; 8799 8800 struct mlx5_ifc_create_dct_out_bits { 8801 u8 status[0x8]; 8802 u8 reserved_at_8[0x18]; 8803 8804 u8 syndrome[0x20]; 8805 8806 u8 reserved_at_40[0x8]; 8807 u8 dctn[0x18]; 8808 8809 u8 ece[0x20]; 8810 }; 8811 8812 struct mlx5_ifc_create_dct_in_bits { 8813 u8 opcode[0x10]; 8814 u8 uid[0x10]; 8815 8816 u8 reserved_at_20[0x10]; 8817 u8 op_mod[0x10]; 8818 8819 u8 reserved_at_40[0x40]; 8820 8821 struct mlx5_ifc_dctc_bits dct_context_entry; 8822 8823 u8 reserved_at_280[0x180]; 8824 }; 8825 8826 struct mlx5_ifc_create_cq_out_bits { 8827 u8 status[0x8]; 8828 u8 reserved_at_8[0x18]; 8829 8830 u8 syndrome[0x20]; 8831 8832 u8 reserved_at_40[0x8]; 8833 u8 cqn[0x18]; 8834 8835 u8 reserved_at_60[0x20]; 8836 }; 8837 8838 struct mlx5_ifc_create_cq_in_bits { 8839 u8 opcode[0x10]; 8840 u8 uid[0x10]; 8841 8842 u8 reserved_at_20[0x10]; 8843 u8 op_mod[0x10]; 8844 8845 u8 reserved_at_40[0x40]; 8846 8847 struct mlx5_ifc_cqc_bits cq_context; 8848 8849 u8 reserved_at_280[0x60]; 8850 8851 u8 cq_umem_valid[0x1]; 8852 u8 reserved_at_2e1[0x59f]; 8853 8854 u8 pas[][0x40]; 8855 }; 8856 8857 struct mlx5_ifc_config_int_moderation_out_bits { 8858 u8 status[0x8]; 8859 u8 reserved_at_8[0x18]; 8860 8861 u8 syndrome[0x20]; 8862 8863 u8 reserved_at_40[0x4]; 8864 u8 min_delay[0xc]; 8865 u8 int_vector[0x10]; 8866 8867 u8 reserved_at_60[0x20]; 8868 }; 8869 8870 enum { 8871 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0, 8872 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1, 8873 }; 8874 8875 struct mlx5_ifc_config_int_moderation_in_bits { 8876 u8 opcode[0x10]; 8877 u8 reserved_at_10[0x10]; 8878 8879 u8 reserved_at_20[0x10]; 8880 u8 op_mod[0x10]; 8881 8882 u8 reserved_at_40[0x4]; 8883 u8 min_delay[0xc]; 8884 u8 int_vector[0x10]; 8885 8886 u8 reserved_at_60[0x20]; 8887 }; 8888 8889 struct mlx5_ifc_attach_to_mcg_out_bits { 8890 u8 status[0x8]; 8891 u8 reserved_at_8[0x18]; 8892 8893 u8 syndrome[0x20]; 8894 8895 u8 reserved_at_40[0x40]; 8896 }; 8897 8898 struct mlx5_ifc_attach_to_mcg_in_bits { 8899 u8 opcode[0x10]; 8900 u8 uid[0x10]; 8901 8902 u8 reserved_at_20[0x10]; 8903 u8 op_mod[0x10]; 8904 8905 u8 reserved_at_40[0x8]; 8906 u8 qpn[0x18]; 8907 8908 u8 reserved_at_60[0x20]; 8909 8910 u8 multicast_gid[16][0x8]; 8911 }; 8912 8913 struct mlx5_ifc_arm_xrq_out_bits { 8914 u8 status[0x8]; 8915 u8 reserved_at_8[0x18]; 8916 8917 u8 syndrome[0x20]; 8918 8919 u8 reserved_at_40[0x40]; 8920 }; 8921 8922 struct mlx5_ifc_arm_xrq_in_bits { 8923 u8 opcode[0x10]; 8924 u8 reserved_at_10[0x10]; 8925 8926 u8 reserved_at_20[0x10]; 8927 u8 op_mod[0x10]; 8928 8929 u8 reserved_at_40[0x8]; 8930 u8 xrqn[0x18]; 8931 8932 u8 reserved_at_60[0x10]; 8933 u8 lwm[0x10]; 8934 }; 8935 8936 struct mlx5_ifc_arm_xrc_srq_out_bits { 8937 u8 status[0x8]; 8938 u8 reserved_at_8[0x18]; 8939 8940 u8 syndrome[0x20]; 8941 8942 u8 reserved_at_40[0x40]; 8943 }; 8944 8945 enum { 8946 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1, 8947 }; 8948 8949 struct mlx5_ifc_arm_xrc_srq_in_bits { 8950 u8 opcode[0x10]; 8951 u8 uid[0x10]; 8952 8953 u8 reserved_at_20[0x10]; 8954 u8 op_mod[0x10]; 8955 8956 u8 reserved_at_40[0x8]; 8957 u8 xrc_srqn[0x18]; 8958 8959 u8 reserved_at_60[0x10]; 8960 u8 lwm[0x10]; 8961 }; 8962 8963 struct mlx5_ifc_arm_rq_out_bits { 8964 u8 status[0x8]; 8965 u8 reserved_at_8[0x18]; 8966 8967 u8 syndrome[0x20]; 8968 8969 u8 reserved_at_40[0x40]; 8970 }; 8971 8972 enum { 8973 MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1, 8974 MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2, 8975 }; 8976 8977 struct mlx5_ifc_arm_rq_in_bits { 8978 u8 opcode[0x10]; 8979 u8 uid[0x10]; 8980 8981 u8 reserved_at_20[0x10]; 8982 u8 op_mod[0x10]; 8983 8984 u8 reserved_at_40[0x8]; 8985 u8 srq_number[0x18]; 8986 8987 u8 reserved_at_60[0x10]; 8988 u8 lwm[0x10]; 8989 }; 8990 8991 struct mlx5_ifc_arm_dct_out_bits { 8992 u8 status[0x8]; 8993 u8 reserved_at_8[0x18]; 8994 8995 u8 syndrome[0x20]; 8996 8997 u8 reserved_at_40[0x40]; 8998 }; 8999 9000 struct mlx5_ifc_arm_dct_in_bits { 9001 u8 opcode[0x10]; 9002 u8 reserved_at_10[0x10]; 9003 9004 u8 reserved_at_20[0x10]; 9005 u8 op_mod[0x10]; 9006 9007 u8 reserved_at_40[0x8]; 9008 u8 dct_number[0x18]; 9009 9010 u8 reserved_at_60[0x20]; 9011 }; 9012 9013 struct mlx5_ifc_alloc_xrcd_out_bits { 9014 u8 status[0x8]; 9015 u8 reserved_at_8[0x18]; 9016 9017 u8 syndrome[0x20]; 9018 9019 u8 reserved_at_40[0x8]; 9020 u8 xrcd[0x18]; 9021 9022 u8 reserved_at_60[0x20]; 9023 }; 9024 9025 struct mlx5_ifc_alloc_xrcd_in_bits { 9026 u8 opcode[0x10]; 9027 u8 uid[0x10]; 9028 9029 u8 reserved_at_20[0x10]; 9030 u8 op_mod[0x10]; 9031 9032 u8 reserved_at_40[0x40]; 9033 }; 9034 9035 struct mlx5_ifc_alloc_uar_out_bits { 9036 u8 status[0x8]; 9037 u8 reserved_at_8[0x18]; 9038 9039 u8 syndrome[0x20]; 9040 9041 u8 reserved_at_40[0x8]; 9042 u8 uar[0x18]; 9043 9044 u8 reserved_at_60[0x20]; 9045 }; 9046 9047 struct mlx5_ifc_alloc_uar_in_bits { 9048 u8 opcode[0x10]; 9049 u8 uid[0x10]; 9050 9051 u8 reserved_at_20[0x10]; 9052 u8 op_mod[0x10]; 9053 9054 u8 reserved_at_40[0x40]; 9055 }; 9056 9057 struct mlx5_ifc_alloc_transport_domain_out_bits { 9058 u8 status[0x8]; 9059 u8 reserved_at_8[0x18]; 9060 9061 u8 syndrome[0x20]; 9062 9063 u8 reserved_at_40[0x8]; 9064 u8 transport_domain[0x18]; 9065 9066 u8 reserved_at_60[0x20]; 9067 }; 9068 9069 struct mlx5_ifc_alloc_transport_domain_in_bits { 9070 u8 opcode[0x10]; 9071 u8 uid[0x10]; 9072 9073 u8 reserved_at_20[0x10]; 9074 u8 op_mod[0x10]; 9075 9076 u8 reserved_at_40[0x40]; 9077 }; 9078 9079 struct mlx5_ifc_alloc_q_counter_out_bits { 9080 u8 status[0x8]; 9081 u8 reserved_at_8[0x18]; 9082 9083 u8 syndrome[0x20]; 9084 9085 u8 reserved_at_40[0x18]; 9086 u8 counter_set_id[0x8]; 9087 9088 u8 reserved_at_60[0x20]; 9089 }; 9090 9091 struct mlx5_ifc_alloc_q_counter_in_bits { 9092 u8 opcode[0x10]; 9093 u8 uid[0x10]; 9094 9095 u8 reserved_at_20[0x10]; 9096 u8 op_mod[0x10]; 9097 9098 u8 reserved_at_40[0x40]; 9099 }; 9100 9101 struct mlx5_ifc_alloc_pd_out_bits { 9102 u8 status[0x8]; 9103 u8 reserved_at_8[0x18]; 9104 9105 u8 syndrome[0x20]; 9106 9107 u8 reserved_at_40[0x8]; 9108 u8 pd[0x18]; 9109 9110 u8 reserved_at_60[0x20]; 9111 }; 9112 9113 struct mlx5_ifc_alloc_pd_in_bits { 9114 u8 opcode[0x10]; 9115 u8 uid[0x10]; 9116 9117 u8 reserved_at_20[0x10]; 9118 u8 op_mod[0x10]; 9119 9120 u8 reserved_at_40[0x40]; 9121 }; 9122 9123 struct mlx5_ifc_alloc_flow_counter_out_bits { 9124 u8 status[0x8]; 9125 u8 reserved_at_8[0x18]; 9126 9127 u8 syndrome[0x20]; 9128 9129 u8 flow_counter_id[0x20]; 9130 9131 u8 reserved_at_60[0x20]; 9132 }; 9133 9134 struct mlx5_ifc_alloc_flow_counter_in_bits { 9135 u8 opcode[0x10]; 9136 u8 reserved_at_10[0x10]; 9137 9138 u8 reserved_at_20[0x10]; 9139 u8 op_mod[0x10]; 9140 9141 u8 reserved_at_40[0x38]; 9142 u8 flow_counter_bulk[0x8]; 9143 }; 9144 9145 struct mlx5_ifc_add_vxlan_udp_dport_out_bits { 9146 u8 status[0x8]; 9147 u8 reserved_at_8[0x18]; 9148 9149 u8 syndrome[0x20]; 9150 9151 u8 reserved_at_40[0x40]; 9152 }; 9153 9154 struct mlx5_ifc_add_vxlan_udp_dport_in_bits { 9155 u8 opcode[0x10]; 9156 u8 reserved_at_10[0x10]; 9157 9158 u8 reserved_at_20[0x10]; 9159 u8 op_mod[0x10]; 9160 9161 u8 reserved_at_40[0x20]; 9162 9163 u8 reserved_at_60[0x10]; 9164 u8 vxlan_udp_port[0x10]; 9165 }; 9166 9167 struct mlx5_ifc_set_pp_rate_limit_out_bits { 9168 u8 status[0x8]; 9169 u8 reserved_at_8[0x18]; 9170 9171 u8 syndrome[0x20]; 9172 9173 u8 reserved_at_40[0x40]; 9174 }; 9175 9176 struct mlx5_ifc_set_pp_rate_limit_context_bits { 9177 u8 rate_limit[0x20]; 9178 9179 u8 burst_upper_bound[0x20]; 9180 9181 u8 reserved_at_40[0x10]; 9182 u8 typical_packet_size[0x10]; 9183 9184 u8 reserved_at_60[0x120]; 9185 }; 9186 9187 struct mlx5_ifc_set_pp_rate_limit_in_bits { 9188 u8 opcode[0x10]; 9189 u8 uid[0x10]; 9190 9191 u8 reserved_at_20[0x10]; 9192 u8 op_mod[0x10]; 9193 9194 u8 reserved_at_40[0x10]; 9195 u8 rate_limit_index[0x10]; 9196 9197 u8 reserved_at_60[0x20]; 9198 9199 struct mlx5_ifc_set_pp_rate_limit_context_bits ctx; 9200 }; 9201 9202 struct mlx5_ifc_access_register_out_bits { 9203 u8 status[0x8]; 9204 u8 reserved_at_8[0x18]; 9205 9206 u8 syndrome[0x20]; 9207 9208 u8 reserved_at_40[0x40]; 9209 9210 u8 register_data[][0x20]; 9211 }; 9212 9213 enum { 9214 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0, 9215 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1, 9216 }; 9217 9218 struct mlx5_ifc_access_register_in_bits { 9219 u8 opcode[0x10]; 9220 u8 reserved_at_10[0x10]; 9221 9222 u8 reserved_at_20[0x10]; 9223 u8 op_mod[0x10]; 9224 9225 u8 reserved_at_40[0x10]; 9226 u8 register_id[0x10]; 9227 9228 u8 argument[0x20]; 9229 9230 u8 register_data[][0x20]; 9231 }; 9232 9233 struct mlx5_ifc_sltp_reg_bits { 9234 u8 status[0x4]; 9235 u8 version[0x4]; 9236 u8 local_port[0x8]; 9237 u8 pnat[0x2]; 9238 u8 reserved_at_12[0x2]; 9239 u8 lane[0x4]; 9240 u8 reserved_at_18[0x8]; 9241 9242 u8 reserved_at_20[0x20]; 9243 9244 u8 reserved_at_40[0x7]; 9245 u8 polarity[0x1]; 9246 u8 ob_tap0[0x8]; 9247 u8 ob_tap1[0x8]; 9248 u8 ob_tap2[0x8]; 9249 9250 u8 reserved_at_60[0xc]; 9251 u8 ob_preemp_mode[0x4]; 9252 u8 ob_reg[0x8]; 9253 u8 ob_bias[0x8]; 9254 9255 u8 reserved_at_80[0x20]; 9256 }; 9257 9258 struct mlx5_ifc_slrg_reg_bits { 9259 u8 status[0x4]; 9260 u8 version[0x4]; 9261 u8 local_port[0x8]; 9262 u8 pnat[0x2]; 9263 u8 reserved_at_12[0x2]; 9264 u8 lane[0x4]; 9265 u8 reserved_at_18[0x8]; 9266 9267 u8 time_to_link_up[0x10]; 9268 u8 reserved_at_30[0xc]; 9269 u8 grade_lane_speed[0x4]; 9270 9271 u8 grade_version[0x8]; 9272 u8 grade[0x18]; 9273 9274 u8 reserved_at_60[0x4]; 9275 u8 height_grade_type[0x4]; 9276 u8 height_grade[0x18]; 9277 9278 u8 height_dz[0x10]; 9279 u8 height_dv[0x10]; 9280 9281 u8 reserved_at_a0[0x10]; 9282 u8 height_sigma[0x10]; 9283 9284 u8 reserved_at_c0[0x20]; 9285 9286 u8 reserved_at_e0[0x4]; 9287 u8 phase_grade_type[0x4]; 9288 u8 phase_grade[0x18]; 9289 9290 u8 reserved_at_100[0x8]; 9291 u8 phase_eo_pos[0x8]; 9292 u8 reserved_at_110[0x8]; 9293 u8 phase_eo_neg[0x8]; 9294 9295 u8 ffe_set_tested[0x10]; 9296 u8 test_errors_per_lane[0x10]; 9297 }; 9298 9299 struct mlx5_ifc_pvlc_reg_bits { 9300 u8 reserved_at_0[0x8]; 9301 u8 local_port[0x8]; 9302 u8 reserved_at_10[0x10]; 9303 9304 u8 reserved_at_20[0x1c]; 9305 u8 vl_hw_cap[0x4]; 9306 9307 u8 reserved_at_40[0x1c]; 9308 u8 vl_admin[0x4]; 9309 9310 u8 reserved_at_60[0x1c]; 9311 u8 vl_operational[0x4]; 9312 }; 9313 9314 struct mlx5_ifc_pude_reg_bits { 9315 u8 swid[0x8]; 9316 u8 local_port[0x8]; 9317 u8 reserved_at_10[0x4]; 9318 u8 admin_status[0x4]; 9319 u8 reserved_at_18[0x4]; 9320 u8 oper_status[0x4]; 9321 9322 u8 reserved_at_20[0x60]; 9323 }; 9324 9325 struct mlx5_ifc_ptys_reg_bits { 9326 u8 reserved_at_0[0x1]; 9327 u8 an_disable_admin[0x1]; 9328 u8 an_disable_cap[0x1]; 9329 u8 reserved_at_3[0x5]; 9330 u8 local_port[0x8]; 9331 u8 reserved_at_10[0xd]; 9332 u8 proto_mask[0x3]; 9333 9334 u8 an_status[0x4]; 9335 u8 reserved_at_24[0xc]; 9336 u8 data_rate_oper[0x10]; 9337 9338 u8 ext_eth_proto_capability[0x20]; 9339 9340 u8 eth_proto_capability[0x20]; 9341 9342 u8 ib_link_width_capability[0x10]; 9343 u8 ib_proto_capability[0x10]; 9344 9345 u8 ext_eth_proto_admin[0x20]; 9346 9347 u8 eth_proto_admin[0x20]; 9348 9349 u8 ib_link_width_admin[0x10]; 9350 u8 ib_proto_admin[0x10]; 9351 9352 u8 ext_eth_proto_oper[0x20]; 9353 9354 u8 eth_proto_oper[0x20]; 9355 9356 u8 ib_link_width_oper[0x10]; 9357 u8 ib_proto_oper[0x10]; 9358 9359 u8 reserved_at_160[0x1c]; 9360 u8 connector_type[0x4]; 9361 9362 u8 eth_proto_lp_advertise[0x20]; 9363 9364 u8 reserved_at_1a0[0x60]; 9365 }; 9366 9367 struct mlx5_ifc_mlcr_reg_bits { 9368 u8 reserved_at_0[0x8]; 9369 u8 local_port[0x8]; 9370 u8 reserved_at_10[0x20]; 9371 9372 u8 beacon_duration[0x10]; 9373 u8 reserved_at_40[0x10]; 9374 9375 u8 beacon_remain[0x10]; 9376 }; 9377 9378 struct mlx5_ifc_ptas_reg_bits { 9379 u8 reserved_at_0[0x20]; 9380 9381 u8 algorithm_options[0x10]; 9382 u8 reserved_at_30[0x4]; 9383 u8 repetitions_mode[0x4]; 9384 u8 num_of_repetitions[0x8]; 9385 9386 u8 grade_version[0x8]; 9387 u8 height_grade_type[0x4]; 9388 u8 phase_grade_type[0x4]; 9389 u8 height_grade_weight[0x8]; 9390 u8 phase_grade_weight[0x8]; 9391 9392 u8 gisim_measure_bits[0x10]; 9393 u8 adaptive_tap_measure_bits[0x10]; 9394 9395 u8 ber_bath_high_error_threshold[0x10]; 9396 u8 ber_bath_mid_error_threshold[0x10]; 9397 9398 u8 ber_bath_low_error_threshold[0x10]; 9399 u8 one_ratio_high_threshold[0x10]; 9400 9401 u8 one_ratio_high_mid_threshold[0x10]; 9402 u8 one_ratio_low_mid_threshold[0x10]; 9403 9404 u8 one_ratio_low_threshold[0x10]; 9405 u8 ndeo_error_threshold[0x10]; 9406 9407 u8 mixer_offset_step_size[0x10]; 9408 u8 reserved_at_110[0x8]; 9409 u8 mix90_phase_for_voltage_bath[0x8]; 9410 9411 u8 mixer_offset_start[0x10]; 9412 u8 mixer_offset_end[0x10]; 9413 9414 u8 reserved_at_140[0x15]; 9415 u8 ber_test_time[0xb]; 9416 }; 9417 9418 struct mlx5_ifc_pspa_reg_bits { 9419 u8 swid[0x8]; 9420 u8 local_port[0x8]; 9421 u8 sub_port[0x8]; 9422 u8 reserved_at_18[0x8]; 9423 9424 u8 reserved_at_20[0x20]; 9425 }; 9426 9427 struct mlx5_ifc_pqdr_reg_bits { 9428 u8 reserved_at_0[0x8]; 9429 u8 local_port[0x8]; 9430 u8 reserved_at_10[0x5]; 9431 u8 prio[0x3]; 9432 u8 reserved_at_18[0x6]; 9433 u8 mode[0x2]; 9434 9435 u8 reserved_at_20[0x20]; 9436 9437 u8 reserved_at_40[0x10]; 9438 u8 min_threshold[0x10]; 9439 9440 u8 reserved_at_60[0x10]; 9441 u8 max_threshold[0x10]; 9442 9443 u8 reserved_at_80[0x10]; 9444 u8 mark_probability_denominator[0x10]; 9445 9446 u8 reserved_at_a0[0x60]; 9447 }; 9448 9449 struct mlx5_ifc_ppsc_reg_bits { 9450 u8 reserved_at_0[0x8]; 9451 u8 local_port[0x8]; 9452 u8 reserved_at_10[0x10]; 9453 9454 u8 reserved_at_20[0x60]; 9455 9456 u8 reserved_at_80[0x1c]; 9457 u8 wrps_admin[0x4]; 9458 9459 u8 reserved_at_a0[0x1c]; 9460 u8 wrps_status[0x4]; 9461 9462 u8 reserved_at_c0[0x8]; 9463 u8 up_threshold[0x8]; 9464 u8 reserved_at_d0[0x8]; 9465 u8 down_threshold[0x8]; 9466 9467 u8 reserved_at_e0[0x20]; 9468 9469 u8 reserved_at_100[0x1c]; 9470 u8 srps_admin[0x4]; 9471 9472 u8 reserved_at_120[0x1c]; 9473 u8 srps_status[0x4]; 9474 9475 u8 reserved_at_140[0x40]; 9476 }; 9477 9478 struct mlx5_ifc_pplr_reg_bits { 9479 u8 reserved_at_0[0x8]; 9480 u8 local_port[0x8]; 9481 u8 reserved_at_10[0x10]; 9482 9483 u8 reserved_at_20[0x8]; 9484 u8 lb_cap[0x8]; 9485 u8 reserved_at_30[0x8]; 9486 u8 lb_en[0x8]; 9487 }; 9488 9489 struct mlx5_ifc_pplm_reg_bits { 9490 u8 reserved_at_0[0x8]; 9491 u8 local_port[0x8]; 9492 u8 reserved_at_10[0x10]; 9493 9494 u8 reserved_at_20[0x20]; 9495 9496 u8 port_profile_mode[0x8]; 9497 u8 static_port_profile[0x8]; 9498 u8 active_port_profile[0x8]; 9499 u8 reserved_at_58[0x8]; 9500 9501 u8 retransmission_active[0x8]; 9502 u8 fec_mode_active[0x18]; 9503 9504 u8 rs_fec_correction_bypass_cap[0x4]; 9505 u8 reserved_at_84[0x8]; 9506 u8 fec_override_cap_56g[0x4]; 9507 u8 fec_override_cap_100g[0x4]; 9508 u8 fec_override_cap_50g[0x4]; 9509 u8 fec_override_cap_25g[0x4]; 9510 u8 fec_override_cap_10g_40g[0x4]; 9511 9512 u8 rs_fec_correction_bypass_admin[0x4]; 9513 u8 reserved_at_a4[0x8]; 9514 u8 fec_override_admin_56g[0x4]; 9515 u8 fec_override_admin_100g[0x4]; 9516 u8 fec_override_admin_50g[0x4]; 9517 u8 fec_override_admin_25g[0x4]; 9518 u8 fec_override_admin_10g_40g[0x4]; 9519 9520 u8 fec_override_cap_400g_8x[0x10]; 9521 u8 fec_override_cap_200g_4x[0x10]; 9522 9523 u8 fec_override_cap_100g_2x[0x10]; 9524 u8 fec_override_cap_50g_1x[0x10]; 9525 9526 u8 fec_override_admin_400g_8x[0x10]; 9527 u8 fec_override_admin_200g_4x[0x10]; 9528 9529 u8 fec_override_admin_100g_2x[0x10]; 9530 u8 fec_override_admin_50g_1x[0x10]; 9531 9532 u8 reserved_at_140[0x140]; 9533 }; 9534 9535 struct mlx5_ifc_ppcnt_reg_bits { 9536 u8 swid[0x8]; 9537 u8 local_port[0x8]; 9538 u8 pnat[0x2]; 9539 u8 reserved_at_12[0x8]; 9540 u8 grp[0x6]; 9541 9542 u8 clr[0x1]; 9543 u8 reserved_at_21[0x1c]; 9544 u8 prio_tc[0x3]; 9545 9546 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set; 9547 }; 9548 9549 struct mlx5_ifc_mpein_reg_bits { 9550 u8 reserved_at_0[0x2]; 9551 u8 depth[0x6]; 9552 u8 pcie_index[0x8]; 9553 u8 node[0x8]; 9554 u8 reserved_at_18[0x8]; 9555 9556 u8 capability_mask[0x20]; 9557 9558 u8 reserved_at_40[0x8]; 9559 u8 link_width_enabled[0x8]; 9560 u8 link_speed_enabled[0x10]; 9561 9562 u8 lane0_physical_position[0x8]; 9563 u8 link_width_active[0x8]; 9564 u8 link_speed_active[0x10]; 9565 9566 u8 num_of_pfs[0x10]; 9567 u8 num_of_vfs[0x10]; 9568 9569 u8 bdf0[0x10]; 9570 u8 reserved_at_b0[0x10]; 9571 9572 u8 max_read_request_size[0x4]; 9573 u8 max_payload_size[0x4]; 9574 u8 reserved_at_c8[0x5]; 9575 u8 pwr_status[0x3]; 9576 u8 port_type[0x4]; 9577 u8 reserved_at_d4[0xb]; 9578 u8 lane_reversal[0x1]; 9579 9580 u8 reserved_at_e0[0x14]; 9581 u8 pci_power[0xc]; 9582 9583 u8 reserved_at_100[0x20]; 9584 9585 u8 device_status[0x10]; 9586 u8 port_state[0x8]; 9587 u8 reserved_at_138[0x8]; 9588 9589 u8 reserved_at_140[0x10]; 9590 u8 receiver_detect_result[0x10]; 9591 9592 u8 reserved_at_160[0x20]; 9593 }; 9594 9595 struct mlx5_ifc_mpcnt_reg_bits { 9596 u8 reserved_at_0[0x8]; 9597 u8 pcie_index[0x8]; 9598 u8 reserved_at_10[0xa]; 9599 u8 grp[0x6]; 9600 9601 u8 clr[0x1]; 9602 u8 reserved_at_21[0x1f]; 9603 9604 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set; 9605 }; 9606 9607 struct mlx5_ifc_ppad_reg_bits { 9608 u8 reserved_at_0[0x3]; 9609 u8 single_mac[0x1]; 9610 u8 reserved_at_4[0x4]; 9611 u8 local_port[0x8]; 9612 u8 mac_47_32[0x10]; 9613 9614 u8 mac_31_0[0x20]; 9615 9616 u8 reserved_at_40[0x40]; 9617 }; 9618 9619 struct mlx5_ifc_pmtu_reg_bits { 9620 u8 reserved_at_0[0x8]; 9621 u8 local_port[0x8]; 9622 u8 reserved_at_10[0x10]; 9623 9624 u8 max_mtu[0x10]; 9625 u8 reserved_at_30[0x10]; 9626 9627 u8 admin_mtu[0x10]; 9628 u8 reserved_at_50[0x10]; 9629 9630 u8 oper_mtu[0x10]; 9631 u8 reserved_at_70[0x10]; 9632 }; 9633 9634 struct mlx5_ifc_pmpr_reg_bits { 9635 u8 reserved_at_0[0x8]; 9636 u8 module[0x8]; 9637 u8 reserved_at_10[0x10]; 9638 9639 u8 reserved_at_20[0x18]; 9640 u8 attenuation_5g[0x8]; 9641 9642 u8 reserved_at_40[0x18]; 9643 u8 attenuation_7g[0x8]; 9644 9645 u8 reserved_at_60[0x18]; 9646 u8 attenuation_12g[0x8]; 9647 }; 9648 9649 struct mlx5_ifc_pmpe_reg_bits { 9650 u8 reserved_at_0[0x8]; 9651 u8 module[0x8]; 9652 u8 reserved_at_10[0xc]; 9653 u8 module_status[0x4]; 9654 9655 u8 reserved_at_20[0x60]; 9656 }; 9657 9658 struct mlx5_ifc_pmpc_reg_bits { 9659 u8 module_state_updated[32][0x8]; 9660 }; 9661 9662 struct mlx5_ifc_pmlpn_reg_bits { 9663 u8 reserved_at_0[0x4]; 9664 u8 mlpn_status[0x4]; 9665 u8 local_port[0x8]; 9666 u8 reserved_at_10[0x10]; 9667 9668 u8 e[0x1]; 9669 u8 reserved_at_21[0x1f]; 9670 }; 9671 9672 struct mlx5_ifc_pmlp_reg_bits { 9673 u8 rxtx[0x1]; 9674 u8 reserved_at_1[0x7]; 9675 u8 local_port[0x8]; 9676 u8 reserved_at_10[0x8]; 9677 u8 width[0x8]; 9678 9679 u8 lane0_module_mapping[0x20]; 9680 9681 u8 lane1_module_mapping[0x20]; 9682 9683 u8 lane2_module_mapping[0x20]; 9684 9685 u8 lane3_module_mapping[0x20]; 9686 9687 u8 reserved_at_a0[0x160]; 9688 }; 9689 9690 struct mlx5_ifc_pmaos_reg_bits { 9691 u8 reserved_at_0[0x8]; 9692 u8 module[0x8]; 9693 u8 reserved_at_10[0x4]; 9694 u8 admin_status[0x4]; 9695 u8 reserved_at_18[0x4]; 9696 u8 oper_status[0x4]; 9697 9698 u8 ase[0x1]; 9699 u8 ee[0x1]; 9700 u8 reserved_at_22[0x1c]; 9701 u8 e[0x2]; 9702 9703 u8 reserved_at_40[0x40]; 9704 }; 9705 9706 struct mlx5_ifc_plpc_reg_bits { 9707 u8 reserved_at_0[0x4]; 9708 u8 profile_id[0xc]; 9709 u8 reserved_at_10[0x4]; 9710 u8 proto_mask[0x4]; 9711 u8 reserved_at_18[0x8]; 9712 9713 u8 reserved_at_20[0x10]; 9714 u8 lane_speed[0x10]; 9715 9716 u8 reserved_at_40[0x17]; 9717 u8 lpbf[0x1]; 9718 u8 fec_mode_policy[0x8]; 9719 9720 u8 retransmission_capability[0x8]; 9721 u8 fec_mode_capability[0x18]; 9722 9723 u8 retransmission_support_admin[0x8]; 9724 u8 fec_mode_support_admin[0x18]; 9725 9726 u8 retransmission_request_admin[0x8]; 9727 u8 fec_mode_request_admin[0x18]; 9728 9729 u8 reserved_at_c0[0x80]; 9730 }; 9731 9732 struct mlx5_ifc_plib_reg_bits { 9733 u8 reserved_at_0[0x8]; 9734 u8 local_port[0x8]; 9735 u8 reserved_at_10[0x8]; 9736 u8 ib_port[0x8]; 9737 9738 u8 reserved_at_20[0x60]; 9739 }; 9740 9741 struct mlx5_ifc_plbf_reg_bits { 9742 u8 reserved_at_0[0x8]; 9743 u8 local_port[0x8]; 9744 u8 reserved_at_10[0xd]; 9745 u8 lbf_mode[0x3]; 9746 9747 u8 reserved_at_20[0x20]; 9748 }; 9749 9750 struct mlx5_ifc_pipg_reg_bits { 9751 u8 reserved_at_0[0x8]; 9752 u8 local_port[0x8]; 9753 u8 reserved_at_10[0x10]; 9754 9755 u8 dic[0x1]; 9756 u8 reserved_at_21[0x19]; 9757 u8 ipg[0x4]; 9758 u8 reserved_at_3e[0x2]; 9759 }; 9760 9761 struct mlx5_ifc_pifr_reg_bits { 9762 u8 reserved_at_0[0x8]; 9763 u8 local_port[0x8]; 9764 u8 reserved_at_10[0x10]; 9765 9766 u8 reserved_at_20[0xe0]; 9767 9768 u8 port_filter[8][0x20]; 9769 9770 u8 port_filter_update_en[8][0x20]; 9771 }; 9772 9773 struct mlx5_ifc_pfcc_reg_bits { 9774 u8 reserved_at_0[0x8]; 9775 u8 local_port[0x8]; 9776 u8 reserved_at_10[0xb]; 9777 u8 ppan_mask_n[0x1]; 9778 u8 minor_stall_mask[0x1]; 9779 u8 critical_stall_mask[0x1]; 9780 u8 reserved_at_1e[0x2]; 9781 9782 u8 ppan[0x4]; 9783 u8 reserved_at_24[0x4]; 9784 u8 prio_mask_tx[0x8]; 9785 u8 reserved_at_30[0x8]; 9786 u8 prio_mask_rx[0x8]; 9787 9788 u8 pptx[0x1]; 9789 u8 aptx[0x1]; 9790 u8 pptx_mask_n[0x1]; 9791 u8 reserved_at_43[0x5]; 9792 u8 pfctx[0x8]; 9793 u8 reserved_at_50[0x10]; 9794 9795 u8 pprx[0x1]; 9796 u8 aprx[0x1]; 9797 u8 pprx_mask_n[0x1]; 9798 u8 reserved_at_63[0x5]; 9799 u8 pfcrx[0x8]; 9800 u8 reserved_at_70[0x10]; 9801 9802 u8 device_stall_minor_watermark[0x10]; 9803 u8 device_stall_critical_watermark[0x10]; 9804 9805 u8 reserved_at_a0[0x60]; 9806 }; 9807 9808 struct mlx5_ifc_pelc_reg_bits { 9809 u8 op[0x4]; 9810 u8 reserved_at_4[0x4]; 9811 u8 local_port[0x8]; 9812 u8 reserved_at_10[0x10]; 9813 9814 u8 op_admin[0x8]; 9815 u8 op_capability[0x8]; 9816 u8 op_request[0x8]; 9817 u8 op_active[0x8]; 9818 9819 u8 admin[0x40]; 9820 9821 u8 capability[0x40]; 9822 9823 u8 request[0x40]; 9824 9825 u8 active[0x40]; 9826 9827 u8 reserved_at_140[0x80]; 9828 }; 9829 9830 struct mlx5_ifc_peir_reg_bits { 9831 u8 reserved_at_0[0x8]; 9832 u8 local_port[0x8]; 9833 u8 reserved_at_10[0x10]; 9834 9835 u8 reserved_at_20[0xc]; 9836 u8 error_count[0x4]; 9837 u8 reserved_at_30[0x10]; 9838 9839 u8 reserved_at_40[0xc]; 9840 u8 lane[0x4]; 9841 u8 reserved_at_50[0x8]; 9842 u8 error_type[0x8]; 9843 }; 9844 9845 struct mlx5_ifc_mpegc_reg_bits { 9846 u8 reserved_at_0[0x30]; 9847 u8 field_select[0x10]; 9848 9849 u8 tx_overflow_sense[0x1]; 9850 u8 mark_cqe[0x1]; 9851 u8 mark_cnp[0x1]; 9852 u8 reserved_at_43[0x1b]; 9853 u8 tx_lossy_overflow_oper[0x2]; 9854 9855 u8 reserved_at_60[0x100]; 9856 }; 9857 9858 enum { 9859 MLX5_MTUTC_OPERATION_SET_TIME_IMMEDIATE = 0x1, 9860 MLX5_MTUTC_OPERATION_ADJUST_TIME = 0x2, 9861 MLX5_MTUTC_OPERATION_ADJUST_FREQ_UTC = 0x3, 9862 }; 9863 9864 struct mlx5_ifc_mtutc_reg_bits { 9865 u8 reserved_at_0[0x1c]; 9866 u8 operation[0x4]; 9867 9868 u8 freq_adjustment[0x20]; 9869 9870 u8 reserved_at_40[0x40]; 9871 9872 u8 utc_sec[0x20]; 9873 9874 u8 reserved_at_a0[0x2]; 9875 u8 utc_nsec[0x1e]; 9876 9877 u8 time_adjustment[0x20]; 9878 }; 9879 9880 struct mlx5_ifc_pcam_enhanced_features_bits { 9881 u8 reserved_at_0[0x68]; 9882 u8 fec_50G_per_lane_in_pplm[0x1]; 9883 u8 reserved_at_69[0x4]; 9884 u8 rx_icrc_encapsulated_counter[0x1]; 9885 u8 reserved_at_6e[0x4]; 9886 u8 ptys_extended_ethernet[0x1]; 9887 u8 reserved_at_73[0x3]; 9888 u8 pfcc_mask[0x1]; 9889 u8 reserved_at_77[0x3]; 9890 u8 per_lane_error_counters[0x1]; 9891 u8 rx_buffer_fullness_counters[0x1]; 9892 u8 ptys_connector_type[0x1]; 9893 u8 reserved_at_7d[0x1]; 9894 u8 ppcnt_discard_group[0x1]; 9895 u8 ppcnt_statistical_group[0x1]; 9896 }; 9897 9898 struct mlx5_ifc_pcam_regs_5000_to_507f_bits { 9899 u8 port_access_reg_cap_mask_127_to_96[0x20]; 9900 u8 port_access_reg_cap_mask_95_to_64[0x20]; 9901 9902 u8 port_access_reg_cap_mask_63_to_36[0x1c]; 9903 u8 pplm[0x1]; 9904 u8 port_access_reg_cap_mask_34_to_32[0x3]; 9905 9906 u8 port_access_reg_cap_mask_31_to_13[0x13]; 9907 u8 pbmc[0x1]; 9908 u8 pptb[0x1]; 9909 u8 port_access_reg_cap_mask_10_to_09[0x2]; 9910 u8 ppcnt[0x1]; 9911 u8 port_access_reg_cap_mask_07_to_00[0x8]; 9912 }; 9913 9914 struct mlx5_ifc_pcam_reg_bits { 9915 u8 reserved_at_0[0x8]; 9916 u8 feature_group[0x8]; 9917 u8 reserved_at_10[0x8]; 9918 u8 access_reg_group[0x8]; 9919 9920 u8 reserved_at_20[0x20]; 9921 9922 union { 9923 struct mlx5_ifc_pcam_regs_5000_to_507f_bits regs_5000_to_507f; 9924 u8 reserved_at_0[0x80]; 9925 } port_access_reg_cap_mask; 9926 9927 u8 reserved_at_c0[0x80]; 9928 9929 union { 9930 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features; 9931 u8 reserved_at_0[0x80]; 9932 } feature_cap_mask; 9933 9934 u8 reserved_at_1c0[0xc0]; 9935 }; 9936 9937 struct mlx5_ifc_mcam_enhanced_features_bits { 9938 u8 reserved_at_0[0x5d]; 9939 u8 mcia_32dwords[0x1]; 9940 u8 out_pulse_duration_ns[0x1]; 9941 u8 npps_period[0x1]; 9942 u8 reserved_at_60[0xa]; 9943 u8 reset_state[0x1]; 9944 u8 ptpcyc2realtime_modify[0x1]; 9945 u8 reserved_at_6c[0x2]; 9946 u8 pci_status_and_power[0x1]; 9947 u8 reserved_at_6f[0x5]; 9948 u8 mark_tx_action_cnp[0x1]; 9949 u8 mark_tx_action_cqe[0x1]; 9950 u8 dynamic_tx_overflow[0x1]; 9951 u8 reserved_at_77[0x4]; 9952 u8 pcie_outbound_stalled[0x1]; 9953 u8 tx_overflow_buffer_pkt[0x1]; 9954 u8 mtpps_enh_out_per_adj[0x1]; 9955 u8 mtpps_fs[0x1]; 9956 u8 pcie_performance_group[0x1]; 9957 }; 9958 9959 struct mlx5_ifc_mcam_access_reg_bits { 9960 u8 reserved_at_0[0x1c]; 9961 u8 mcda[0x1]; 9962 u8 mcc[0x1]; 9963 u8 mcqi[0x1]; 9964 u8 mcqs[0x1]; 9965 9966 u8 regs_95_to_87[0x9]; 9967 u8 mpegc[0x1]; 9968 u8 mtutc[0x1]; 9969 u8 regs_84_to_68[0x11]; 9970 u8 tracer_registers[0x4]; 9971 9972 u8 regs_63_to_46[0x12]; 9973 u8 mrtc[0x1]; 9974 u8 regs_44_to_32[0xd]; 9975 9976 u8 regs_31_to_0[0x20]; 9977 }; 9978 9979 struct mlx5_ifc_mcam_access_reg_bits1 { 9980 u8 regs_127_to_96[0x20]; 9981 9982 u8 regs_95_to_64[0x20]; 9983 9984 u8 regs_63_to_32[0x20]; 9985 9986 u8 regs_31_to_0[0x20]; 9987 }; 9988 9989 struct mlx5_ifc_mcam_access_reg_bits2 { 9990 u8 regs_127_to_99[0x1d]; 9991 u8 mirc[0x1]; 9992 u8 regs_97_to_96[0x2]; 9993 9994 u8 regs_95_to_64[0x20]; 9995 9996 u8 regs_63_to_32[0x20]; 9997 9998 u8 regs_31_to_0[0x20]; 9999 }; 10000 10001 struct mlx5_ifc_mcam_reg_bits { 10002 u8 reserved_at_0[0x8]; 10003 u8 feature_group[0x8]; 10004 u8 reserved_at_10[0x8]; 10005 u8 access_reg_group[0x8]; 10006 10007 u8 reserved_at_20[0x20]; 10008 10009 union { 10010 struct mlx5_ifc_mcam_access_reg_bits access_regs; 10011 struct mlx5_ifc_mcam_access_reg_bits1 access_regs1; 10012 struct mlx5_ifc_mcam_access_reg_bits2 access_regs2; 10013 u8 reserved_at_0[0x80]; 10014 } mng_access_reg_cap_mask; 10015 10016 u8 reserved_at_c0[0x80]; 10017 10018 union { 10019 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features; 10020 u8 reserved_at_0[0x80]; 10021 } mng_feature_cap_mask; 10022 10023 u8 reserved_at_1c0[0x80]; 10024 }; 10025 10026 struct mlx5_ifc_qcam_access_reg_cap_mask { 10027 u8 qcam_access_reg_cap_mask_127_to_20[0x6C]; 10028 u8 qpdpm[0x1]; 10029 u8 qcam_access_reg_cap_mask_18_to_4[0x0F]; 10030 u8 qdpm[0x1]; 10031 u8 qpts[0x1]; 10032 u8 qcap[0x1]; 10033 u8 qcam_access_reg_cap_mask_0[0x1]; 10034 }; 10035 10036 struct mlx5_ifc_qcam_qos_feature_cap_mask { 10037 u8 qcam_qos_feature_cap_mask_127_to_1[0x7F]; 10038 u8 qpts_trust_both[0x1]; 10039 }; 10040 10041 struct mlx5_ifc_qcam_reg_bits { 10042 u8 reserved_at_0[0x8]; 10043 u8 feature_group[0x8]; 10044 u8 reserved_at_10[0x8]; 10045 u8 access_reg_group[0x8]; 10046 u8 reserved_at_20[0x20]; 10047 10048 union { 10049 struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap; 10050 u8 reserved_at_0[0x80]; 10051 } qos_access_reg_cap_mask; 10052 10053 u8 reserved_at_c0[0x80]; 10054 10055 union { 10056 struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap; 10057 u8 reserved_at_0[0x80]; 10058 } qos_feature_cap_mask; 10059 10060 u8 reserved_at_1c0[0x80]; 10061 }; 10062 10063 struct mlx5_ifc_core_dump_reg_bits { 10064 u8 reserved_at_0[0x18]; 10065 u8 core_dump_type[0x8]; 10066 10067 u8 reserved_at_20[0x30]; 10068 u8 vhca_id[0x10]; 10069 10070 u8 reserved_at_60[0x8]; 10071 u8 qpn[0x18]; 10072 u8 reserved_at_80[0x180]; 10073 }; 10074 10075 struct mlx5_ifc_pcap_reg_bits { 10076 u8 reserved_at_0[0x8]; 10077 u8 local_port[0x8]; 10078 u8 reserved_at_10[0x10]; 10079 10080 u8 port_capability_mask[4][0x20]; 10081 }; 10082 10083 struct mlx5_ifc_paos_reg_bits { 10084 u8 swid[0x8]; 10085 u8 local_port[0x8]; 10086 u8 reserved_at_10[0x4]; 10087 u8 admin_status[0x4]; 10088 u8 reserved_at_18[0x4]; 10089 u8 oper_status[0x4]; 10090 10091 u8 ase[0x1]; 10092 u8 ee[0x1]; 10093 u8 reserved_at_22[0x1c]; 10094 u8 e[0x2]; 10095 10096 u8 reserved_at_40[0x40]; 10097 }; 10098 10099 struct mlx5_ifc_pamp_reg_bits { 10100 u8 reserved_at_0[0x8]; 10101 u8 opamp_group[0x8]; 10102 u8 reserved_at_10[0xc]; 10103 u8 opamp_group_type[0x4]; 10104 10105 u8 start_index[0x10]; 10106 u8 reserved_at_30[0x4]; 10107 u8 num_of_indices[0xc]; 10108 10109 u8 index_data[18][0x10]; 10110 }; 10111 10112 struct mlx5_ifc_pcmr_reg_bits { 10113 u8 reserved_at_0[0x8]; 10114 u8 local_port[0x8]; 10115 u8 reserved_at_10[0x10]; 10116 10117 u8 entropy_force_cap[0x1]; 10118 u8 entropy_calc_cap[0x1]; 10119 u8 entropy_gre_calc_cap[0x1]; 10120 u8 reserved_at_23[0xf]; 10121 u8 rx_ts_over_crc_cap[0x1]; 10122 u8 reserved_at_33[0xb]; 10123 u8 fcs_cap[0x1]; 10124 u8 reserved_at_3f[0x1]; 10125 10126 u8 entropy_force[0x1]; 10127 u8 entropy_calc[0x1]; 10128 u8 entropy_gre_calc[0x1]; 10129 u8 reserved_at_43[0xf]; 10130 u8 rx_ts_over_crc[0x1]; 10131 u8 reserved_at_53[0xb]; 10132 u8 fcs_chk[0x1]; 10133 u8 reserved_at_5f[0x1]; 10134 }; 10135 10136 struct mlx5_ifc_lane_2_module_mapping_bits { 10137 u8 reserved_at_0[0x4]; 10138 u8 rx_lane[0x4]; 10139 u8 reserved_at_8[0x4]; 10140 u8 tx_lane[0x4]; 10141 u8 reserved_at_10[0x8]; 10142 u8 module[0x8]; 10143 }; 10144 10145 struct mlx5_ifc_bufferx_reg_bits { 10146 u8 reserved_at_0[0x6]; 10147 u8 lossy[0x1]; 10148 u8 epsb[0x1]; 10149 u8 reserved_at_8[0x8]; 10150 u8 size[0x10]; 10151 10152 u8 xoff_threshold[0x10]; 10153 u8 xon_threshold[0x10]; 10154 }; 10155 10156 struct mlx5_ifc_set_node_in_bits { 10157 u8 node_description[64][0x8]; 10158 }; 10159 10160 struct mlx5_ifc_register_power_settings_bits { 10161 u8 reserved_at_0[0x18]; 10162 u8 power_settings_level[0x8]; 10163 10164 u8 reserved_at_20[0x60]; 10165 }; 10166 10167 struct mlx5_ifc_register_host_endianness_bits { 10168 u8 he[0x1]; 10169 u8 reserved_at_1[0x1f]; 10170 10171 u8 reserved_at_20[0x60]; 10172 }; 10173 10174 struct mlx5_ifc_umr_pointer_desc_argument_bits { 10175 u8 reserved_at_0[0x20]; 10176 10177 u8 mkey[0x20]; 10178 10179 u8 addressh_63_32[0x20]; 10180 10181 u8 addressl_31_0[0x20]; 10182 }; 10183 10184 struct mlx5_ifc_ud_adrs_vector_bits { 10185 u8 dc_key[0x40]; 10186 10187 u8 ext[0x1]; 10188 u8 reserved_at_41[0x7]; 10189 u8 destination_qp_dct[0x18]; 10190 10191 u8 static_rate[0x4]; 10192 u8 sl_eth_prio[0x4]; 10193 u8 fl[0x1]; 10194 u8 mlid[0x7]; 10195 u8 rlid_udp_sport[0x10]; 10196 10197 u8 reserved_at_80[0x20]; 10198 10199 u8 rmac_47_16[0x20]; 10200 10201 u8 rmac_15_0[0x10]; 10202 u8 tclass[0x8]; 10203 u8 hop_limit[0x8]; 10204 10205 u8 reserved_at_e0[0x1]; 10206 u8 grh[0x1]; 10207 u8 reserved_at_e2[0x2]; 10208 u8 src_addr_index[0x8]; 10209 u8 flow_label[0x14]; 10210 10211 u8 rgid_rip[16][0x8]; 10212 }; 10213 10214 struct mlx5_ifc_pages_req_event_bits { 10215 u8 reserved_at_0[0x10]; 10216 u8 function_id[0x10]; 10217 10218 u8 num_pages[0x20]; 10219 10220 u8 reserved_at_40[0xa0]; 10221 }; 10222 10223 struct mlx5_ifc_eqe_bits { 10224 u8 reserved_at_0[0x8]; 10225 u8 event_type[0x8]; 10226 u8 reserved_at_10[0x8]; 10227 u8 event_sub_type[0x8]; 10228 10229 u8 reserved_at_20[0xe0]; 10230 10231 union mlx5_ifc_event_auto_bits event_data; 10232 10233 u8 reserved_at_1e0[0x10]; 10234 u8 signature[0x8]; 10235 u8 reserved_at_1f8[0x7]; 10236 u8 owner[0x1]; 10237 }; 10238 10239 enum { 10240 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7, 10241 }; 10242 10243 struct mlx5_ifc_cmd_queue_entry_bits { 10244 u8 type[0x8]; 10245 u8 reserved_at_8[0x18]; 10246 10247 u8 input_length[0x20]; 10248 10249 u8 input_mailbox_pointer_63_32[0x20]; 10250 10251 u8 input_mailbox_pointer_31_9[0x17]; 10252 u8 reserved_at_77[0x9]; 10253 10254 u8 command_input_inline_data[16][0x8]; 10255 10256 u8 command_output_inline_data[16][0x8]; 10257 10258 u8 output_mailbox_pointer_63_32[0x20]; 10259 10260 u8 output_mailbox_pointer_31_9[0x17]; 10261 u8 reserved_at_1b7[0x9]; 10262 10263 u8 output_length[0x20]; 10264 10265 u8 token[0x8]; 10266 u8 signature[0x8]; 10267 u8 reserved_at_1f0[0x8]; 10268 u8 status[0x7]; 10269 u8 ownership[0x1]; 10270 }; 10271 10272 struct mlx5_ifc_cmd_out_bits { 10273 u8 status[0x8]; 10274 u8 reserved_at_8[0x18]; 10275 10276 u8 syndrome[0x20]; 10277 10278 u8 command_output[0x20]; 10279 }; 10280 10281 struct mlx5_ifc_cmd_in_bits { 10282 u8 opcode[0x10]; 10283 u8 reserved_at_10[0x10]; 10284 10285 u8 reserved_at_20[0x10]; 10286 u8 op_mod[0x10]; 10287 10288 u8 command[][0x20]; 10289 }; 10290 10291 struct mlx5_ifc_cmd_if_box_bits { 10292 u8 mailbox_data[512][0x8]; 10293 10294 u8 reserved_at_1000[0x180]; 10295 10296 u8 next_pointer_63_32[0x20]; 10297 10298 u8 next_pointer_31_10[0x16]; 10299 u8 reserved_at_11b6[0xa]; 10300 10301 u8 block_number[0x20]; 10302 10303 u8 reserved_at_11e0[0x8]; 10304 u8 token[0x8]; 10305 u8 ctrl_signature[0x8]; 10306 u8 signature[0x8]; 10307 }; 10308 10309 struct mlx5_ifc_mtt_bits { 10310 u8 ptag_63_32[0x20]; 10311 10312 u8 ptag_31_8[0x18]; 10313 u8 reserved_at_38[0x6]; 10314 u8 wr_en[0x1]; 10315 u8 rd_en[0x1]; 10316 }; 10317 10318 struct mlx5_ifc_query_wol_rol_out_bits { 10319 u8 status[0x8]; 10320 u8 reserved_at_8[0x18]; 10321 10322 u8 syndrome[0x20]; 10323 10324 u8 reserved_at_40[0x10]; 10325 u8 rol_mode[0x8]; 10326 u8 wol_mode[0x8]; 10327 10328 u8 reserved_at_60[0x20]; 10329 }; 10330 10331 struct mlx5_ifc_query_wol_rol_in_bits { 10332 u8 opcode[0x10]; 10333 u8 reserved_at_10[0x10]; 10334 10335 u8 reserved_at_20[0x10]; 10336 u8 op_mod[0x10]; 10337 10338 u8 reserved_at_40[0x40]; 10339 }; 10340 10341 struct mlx5_ifc_set_wol_rol_out_bits { 10342 u8 status[0x8]; 10343 u8 reserved_at_8[0x18]; 10344 10345 u8 syndrome[0x20]; 10346 10347 u8 reserved_at_40[0x40]; 10348 }; 10349 10350 struct mlx5_ifc_set_wol_rol_in_bits { 10351 u8 opcode[0x10]; 10352 u8 reserved_at_10[0x10]; 10353 10354 u8 reserved_at_20[0x10]; 10355 u8 op_mod[0x10]; 10356 10357 u8 rol_mode_valid[0x1]; 10358 u8 wol_mode_valid[0x1]; 10359 u8 reserved_at_42[0xe]; 10360 u8 rol_mode[0x8]; 10361 u8 wol_mode[0x8]; 10362 10363 u8 reserved_at_60[0x20]; 10364 }; 10365 10366 enum { 10367 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0, 10368 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1, 10369 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2, 10370 }; 10371 10372 enum { 10373 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0, 10374 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1, 10375 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2, 10376 }; 10377 10378 enum { 10379 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR = 0x1, 10380 MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC = 0x7, 10381 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR = 0x8, 10382 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR = 0x9, 10383 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR = 0xa, 10384 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR = 0xb, 10385 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN = 0xc, 10386 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR = 0xd, 10387 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV = 0xe, 10388 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR = 0xf, 10389 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR = 0x10, 10390 }; 10391 10392 struct mlx5_ifc_initial_seg_bits { 10393 u8 fw_rev_minor[0x10]; 10394 u8 fw_rev_major[0x10]; 10395 10396 u8 cmd_interface_rev[0x10]; 10397 u8 fw_rev_subminor[0x10]; 10398 10399 u8 reserved_at_40[0x40]; 10400 10401 u8 cmdq_phy_addr_63_32[0x20]; 10402 10403 u8 cmdq_phy_addr_31_12[0x14]; 10404 u8 reserved_at_b4[0x2]; 10405 u8 nic_interface[0x2]; 10406 u8 log_cmdq_size[0x4]; 10407 u8 log_cmdq_stride[0x4]; 10408 10409 u8 command_doorbell_vector[0x20]; 10410 10411 u8 reserved_at_e0[0xf00]; 10412 10413 u8 initializing[0x1]; 10414 u8 reserved_at_fe1[0x4]; 10415 u8 nic_interface_supported[0x3]; 10416 u8 embedded_cpu[0x1]; 10417 u8 reserved_at_fe9[0x17]; 10418 10419 struct mlx5_ifc_health_buffer_bits health_buffer; 10420 10421 u8 no_dram_nic_offset[0x20]; 10422 10423 u8 reserved_at_1220[0x6e40]; 10424 10425 u8 reserved_at_8060[0x1f]; 10426 u8 clear_int[0x1]; 10427 10428 u8 health_syndrome[0x8]; 10429 u8 health_counter[0x18]; 10430 10431 u8 reserved_at_80a0[0x17fc0]; 10432 }; 10433 10434 struct mlx5_ifc_mtpps_reg_bits { 10435 u8 reserved_at_0[0xc]; 10436 u8 cap_number_of_pps_pins[0x4]; 10437 u8 reserved_at_10[0x4]; 10438 u8 cap_max_num_of_pps_in_pins[0x4]; 10439 u8 reserved_at_18[0x4]; 10440 u8 cap_max_num_of_pps_out_pins[0x4]; 10441 10442 u8 reserved_at_20[0x13]; 10443 u8 cap_log_min_npps_period[0x5]; 10444 u8 reserved_at_38[0x3]; 10445 u8 cap_log_min_out_pulse_duration_ns[0x5]; 10446 10447 u8 reserved_at_40[0x4]; 10448 u8 cap_pin_3_mode[0x4]; 10449 u8 reserved_at_48[0x4]; 10450 u8 cap_pin_2_mode[0x4]; 10451 u8 reserved_at_50[0x4]; 10452 u8 cap_pin_1_mode[0x4]; 10453 u8 reserved_at_58[0x4]; 10454 u8 cap_pin_0_mode[0x4]; 10455 10456 u8 reserved_at_60[0x4]; 10457 u8 cap_pin_7_mode[0x4]; 10458 u8 reserved_at_68[0x4]; 10459 u8 cap_pin_6_mode[0x4]; 10460 u8 reserved_at_70[0x4]; 10461 u8 cap_pin_5_mode[0x4]; 10462 u8 reserved_at_78[0x4]; 10463 u8 cap_pin_4_mode[0x4]; 10464 10465 u8 field_select[0x20]; 10466 u8 reserved_at_a0[0x20]; 10467 10468 u8 npps_period[0x40]; 10469 10470 u8 enable[0x1]; 10471 u8 reserved_at_101[0xb]; 10472 u8 pattern[0x4]; 10473 u8 reserved_at_110[0x4]; 10474 u8 pin_mode[0x4]; 10475 u8 pin[0x8]; 10476 10477 u8 reserved_at_120[0x2]; 10478 u8 out_pulse_duration_ns[0x1e]; 10479 10480 u8 time_stamp[0x40]; 10481 10482 u8 out_pulse_duration[0x10]; 10483 u8 out_periodic_adjustment[0x10]; 10484 u8 enhanced_out_periodic_adjustment[0x20]; 10485 10486 u8 reserved_at_1c0[0x20]; 10487 }; 10488 10489 struct mlx5_ifc_mtppse_reg_bits { 10490 u8 reserved_at_0[0x18]; 10491 u8 pin[0x8]; 10492 u8 event_arm[0x1]; 10493 u8 reserved_at_21[0x1b]; 10494 u8 event_generation_mode[0x4]; 10495 u8 reserved_at_40[0x40]; 10496 }; 10497 10498 struct mlx5_ifc_mcqs_reg_bits { 10499 u8 last_index_flag[0x1]; 10500 u8 reserved_at_1[0x7]; 10501 u8 fw_device[0x8]; 10502 u8 component_index[0x10]; 10503 10504 u8 reserved_at_20[0x10]; 10505 u8 identifier[0x10]; 10506 10507 u8 reserved_at_40[0x17]; 10508 u8 component_status[0x5]; 10509 u8 component_update_state[0x4]; 10510 10511 u8 last_update_state_changer_type[0x4]; 10512 u8 last_update_state_changer_host_id[0x4]; 10513 u8 reserved_at_68[0x18]; 10514 }; 10515 10516 struct mlx5_ifc_mcqi_cap_bits { 10517 u8 supported_info_bitmask[0x20]; 10518 10519 u8 component_size[0x20]; 10520 10521 u8 max_component_size[0x20]; 10522 10523 u8 log_mcda_word_size[0x4]; 10524 u8 reserved_at_64[0xc]; 10525 u8 mcda_max_write_size[0x10]; 10526 10527 u8 rd_en[0x1]; 10528 u8 reserved_at_81[0x1]; 10529 u8 match_chip_id[0x1]; 10530 u8 match_psid[0x1]; 10531 u8 check_user_timestamp[0x1]; 10532 u8 match_base_guid_mac[0x1]; 10533 u8 reserved_at_86[0x1a]; 10534 }; 10535 10536 struct mlx5_ifc_mcqi_version_bits { 10537 u8 reserved_at_0[0x2]; 10538 u8 build_time_valid[0x1]; 10539 u8 user_defined_time_valid[0x1]; 10540 u8 reserved_at_4[0x14]; 10541 u8 version_string_length[0x8]; 10542 10543 u8 version[0x20]; 10544 10545 u8 build_time[0x40]; 10546 10547 u8 user_defined_time[0x40]; 10548 10549 u8 build_tool_version[0x20]; 10550 10551 u8 reserved_at_e0[0x20]; 10552 10553 u8 version_string[92][0x8]; 10554 }; 10555 10556 struct mlx5_ifc_mcqi_activation_method_bits { 10557 u8 pending_server_ac_power_cycle[0x1]; 10558 u8 pending_server_dc_power_cycle[0x1]; 10559 u8 pending_server_reboot[0x1]; 10560 u8 pending_fw_reset[0x1]; 10561 u8 auto_activate[0x1]; 10562 u8 all_hosts_sync[0x1]; 10563 u8 device_hw_reset[0x1]; 10564 u8 reserved_at_7[0x19]; 10565 }; 10566 10567 union mlx5_ifc_mcqi_reg_data_bits { 10568 struct mlx5_ifc_mcqi_cap_bits mcqi_caps; 10569 struct mlx5_ifc_mcqi_version_bits mcqi_version; 10570 struct mlx5_ifc_mcqi_activation_method_bits mcqi_activation_mathod; 10571 }; 10572 10573 struct mlx5_ifc_mcqi_reg_bits { 10574 u8 read_pending_component[0x1]; 10575 u8 reserved_at_1[0xf]; 10576 u8 component_index[0x10]; 10577 10578 u8 reserved_at_20[0x20]; 10579 10580 u8 reserved_at_40[0x1b]; 10581 u8 info_type[0x5]; 10582 10583 u8 info_size[0x20]; 10584 10585 u8 offset[0x20]; 10586 10587 u8 reserved_at_a0[0x10]; 10588 u8 data_size[0x10]; 10589 10590 union mlx5_ifc_mcqi_reg_data_bits data[]; 10591 }; 10592 10593 struct mlx5_ifc_mcc_reg_bits { 10594 u8 reserved_at_0[0x4]; 10595 u8 time_elapsed_since_last_cmd[0xc]; 10596 u8 reserved_at_10[0x8]; 10597 u8 instruction[0x8]; 10598 10599 u8 reserved_at_20[0x10]; 10600 u8 component_index[0x10]; 10601 10602 u8 reserved_at_40[0x8]; 10603 u8 update_handle[0x18]; 10604 10605 u8 handle_owner_type[0x4]; 10606 u8 handle_owner_host_id[0x4]; 10607 u8 reserved_at_68[0x1]; 10608 u8 control_progress[0x7]; 10609 u8 error_code[0x8]; 10610 u8 reserved_at_78[0x4]; 10611 u8 control_state[0x4]; 10612 10613 u8 component_size[0x20]; 10614 10615 u8 reserved_at_a0[0x60]; 10616 }; 10617 10618 struct mlx5_ifc_mcda_reg_bits { 10619 u8 reserved_at_0[0x8]; 10620 u8 update_handle[0x18]; 10621 10622 u8 offset[0x20]; 10623 10624 u8 reserved_at_40[0x10]; 10625 u8 size[0x10]; 10626 10627 u8 reserved_at_60[0x20]; 10628 10629 u8 data[][0x20]; 10630 }; 10631 10632 enum { 10633 MLX5_MFRL_REG_RESET_STATE_IDLE = 0, 10634 MLX5_MFRL_REG_RESET_STATE_IN_NEGOTIATION = 1, 10635 MLX5_MFRL_REG_RESET_STATE_RESET_IN_PROGRESS = 2, 10636 MLX5_MFRL_REG_RESET_STATE_TIMEOUT = 3, 10637 MLX5_MFRL_REG_RESET_STATE_NACK = 4, 10638 }; 10639 10640 enum { 10641 MLX5_MFRL_REG_RESET_TYPE_FULL_CHIP = BIT(0), 10642 MLX5_MFRL_REG_RESET_TYPE_NET_PORT_ALIVE = BIT(1), 10643 }; 10644 10645 enum { 10646 MLX5_MFRL_REG_RESET_LEVEL0 = BIT(0), 10647 MLX5_MFRL_REG_RESET_LEVEL3 = BIT(3), 10648 MLX5_MFRL_REG_RESET_LEVEL6 = BIT(6), 10649 }; 10650 10651 struct mlx5_ifc_mfrl_reg_bits { 10652 u8 reserved_at_0[0x20]; 10653 10654 u8 reserved_at_20[0x2]; 10655 u8 pci_sync_for_fw_update_start[0x1]; 10656 u8 pci_sync_for_fw_update_resp[0x2]; 10657 u8 rst_type_sel[0x3]; 10658 u8 reserved_at_28[0x4]; 10659 u8 reset_state[0x4]; 10660 u8 reset_type[0x8]; 10661 u8 reset_level[0x8]; 10662 }; 10663 10664 struct mlx5_ifc_mirc_reg_bits { 10665 u8 reserved_at_0[0x18]; 10666 u8 status_code[0x8]; 10667 10668 u8 reserved_at_20[0x20]; 10669 }; 10670 10671 struct mlx5_ifc_pddr_monitor_opcode_bits { 10672 u8 reserved_at_0[0x10]; 10673 u8 monitor_opcode[0x10]; 10674 }; 10675 10676 union mlx5_ifc_pddr_troubleshooting_page_status_opcode_auto_bits { 10677 struct mlx5_ifc_pddr_monitor_opcode_bits pddr_monitor_opcode; 10678 u8 reserved_at_0[0x20]; 10679 }; 10680 10681 enum { 10682 /* Monitor opcodes */ 10683 MLX5_PDDR_REG_TRBLSH_GROUP_OPCODE_MONITOR = 0x0, 10684 }; 10685 10686 struct mlx5_ifc_pddr_troubleshooting_page_bits { 10687 u8 reserved_at_0[0x10]; 10688 u8 group_opcode[0x10]; 10689 10690 union mlx5_ifc_pddr_troubleshooting_page_status_opcode_auto_bits status_opcode; 10691 10692 u8 reserved_at_40[0x20]; 10693 10694 u8 status_message[59][0x20]; 10695 }; 10696 10697 union mlx5_ifc_pddr_reg_page_data_auto_bits { 10698 struct mlx5_ifc_pddr_troubleshooting_page_bits pddr_troubleshooting_page; 10699 u8 reserved_at_0[0x7c0]; 10700 }; 10701 10702 enum { 10703 MLX5_PDDR_REG_PAGE_SELECT_TROUBLESHOOTING_INFO_PAGE = 0x1, 10704 }; 10705 10706 struct mlx5_ifc_pddr_reg_bits { 10707 u8 reserved_at_0[0x8]; 10708 u8 local_port[0x8]; 10709 u8 pnat[0x2]; 10710 u8 reserved_at_12[0xe]; 10711 10712 u8 reserved_at_20[0x18]; 10713 u8 page_select[0x8]; 10714 10715 union mlx5_ifc_pddr_reg_page_data_auto_bits page_data; 10716 }; 10717 10718 struct mlx5_ifc_mrtc_reg_bits { 10719 u8 time_synced[0x1]; 10720 u8 reserved_at_1[0x1f]; 10721 10722 u8 reserved_at_20[0x20]; 10723 10724 u8 time_h[0x20]; 10725 10726 u8 time_l[0x20]; 10727 }; 10728 10729 union mlx5_ifc_ports_control_registers_document_bits { 10730 struct mlx5_ifc_bufferx_reg_bits bufferx_reg; 10731 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 10732 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 10733 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 10734 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 10735 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 10736 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 10737 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout; 10738 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout; 10739 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping; 10740 struct mlx5_ifc_pamp_reg_bits pamp_reg; 10741 struct mlx5_ifc_paos_reg_bits paos_reg; 10742 struct mlx5_ifc_pcap_reg_bits pcap_reg; 10743 struct mlx5_ifc_pddr_monitor_opcode_bits pddr_monitor_opcode; 10744 struct mlx5_ifc_pddr_reg_bits pddr_reg; 10745 struct mlx5_ifc_pddr_troubleshooting_page_bits pddr_troubleshooting_page; 10746 struct mlx5_ifc_peir_reg_bits peir_reg; 10747 struct mlx5_ifc_pelc_reg_bits pelc_reg; 10748 struct mlx5_ifc_pfcc_reg_bits pfcc_reg; 10749 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 10750 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 10751 struct mlx5_ifc_pifr_reg_bits pifr_reg; 10752 struct mlx5_ifc_pipg_reg_bits pipg_reg; 10753 struct mlx5_ifc_plbf_reg_bits plbf_reg; 10754 struct mlx5_ifc_plib_reg_bits plib_reg; 10755 struct mlx5_ifc_plpc_reg_bits plpc_reg; 10756 struct mlx5_ifc_pmaos_reg_bits pmaos_reg; 10757 struct mlx5_ifc_pmlp_reg_bits pmlp_reg; 10758 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg; 10759 struct mlx5_ifc_pmpc_reg_bits pmpc_reg; 10760 struct mlx5_ifc_pmpe_reg_bits pmpe_reg; 10761 struct mlx5_ifc_pmpr_reg_bits pmpr_reg; 10762 struct mlx5_ifc_pmtu_reg_bits pmtu_reg; 10763 struct mlx5_ifc_ppad_reg_bits ppad_reg; 10764 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg; 10765 struct mlx5_ifc_mpein_reg_bits mpein_reg; 10766 struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg; 10767 struct mlx5_ifc_pplm_reg_bits pplm_reg; 10768 struct mlx5_ifc_pplr_reg_bits pplr_reg; 10769 struct mlx5_ifc_ppsc_reg_bits ppsc_reg; 10770 struct mlx5_ifc_pqdr_reg_bits pqdr_reg; 10771 struct mlx5_ifc_pspa_reg_bits pspa_reg; 10772 struct mlx5_ifc_ptas_reg_bits ptas_reg; 10773 struct mlx5_ifc_ptys_reg_bits ptys_reg; 10774 struct mlx5_ifc_mlcr_reg_bits mlcr_reg; 10775 struct mlx5_ifc_pude_reg_bits pude_reg; 10776 struct mlx5_ifc_pvlc_reg_bits pvlc_reg; 10777 struct mlx5_ifc_slrg_reg_bits slrg_reg; 10778 struct mlx5_ifc_sltp_reg_bits sltp_reg; 10779 struct mlx5_ifc_mtpps_reg_bits mtpps_reg; 10780 struct mlx5_ifc_mtppse_reg_bits mtppse_reg; 10781 struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg; 10782 struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits; 10783 struct mlx5_ifc_fpga_cap_bits fpga_cap_bits; 10784 struct mlx5_ifc_mcqi_reg_bits mcqi_reg; 10785 struct mlx5_ifc_mcc_reg_bits mcc_reg; 10786 struct mlx5_ifc_mcda_reg_bits mcda_reg; 10787 struct mlx5_ifc_mirc_reg_bits mirc_reg; 10788 struct mlx5_ifc_mfrl_reg_bits mfrl_reg; 10789 struct mlx5_ifc_mtutc_reg_bits mtutc_reg; 10790 struct mlx5_ifc_mrtc_reg_bits mrtc_reg; 10791 u8 reserved_at_0[0x60e0]; 10792 }; 10793 10794 union mlx5_ifc_debug_enhancements_document_bits { 10795 struct mlx5_ifc_health_buffer_bits health_buffer; 10796 u8 reserved_at_0[0x200]; 10797 }; 10798 10799 union mlx5_ifc_uplink_pci_interface_document_bits { 10800 struct mlx5_ifc_initial_seg_bits initial_seg; 10801 u8 reserved_at_0[0x20060]; 10802 }; 10803 10804 struct mlx5_ifc_set_flow_table_root_out_bits { 10805 u8 status[0x8]; 10806 u8 reserved_at_8[0x18]; 10807 10808 u8 syndrome[0x20]; 10809 10810 u8 reserved_at_40[0x40]; 10811 }; 10812 10813 struct mlx5_ifc_set_flow_table_root_in_bits { 10814 u8 opcode[0x10]; 10815 u8 reserved_at_10[0x10]; 10816 10817 u8 reserved_at_20[0x10]; 10818 u8 op_mod[0x10]; 10819 10820 u8 other_vport[0x1]; 10821 u8 reserved_at_41[0xf]; 10822 u8 vport_number[0x10]; 10823 10824 u8 reserved_at_60[0x20]; 10825 10826 u8 table_type[0x8]; 10827 u8 reserved_at_88[0x7]; 10828 u8 table_of_other_vport[0x1]; 10829 u8 table_vport_number[0x10]; 10830 10831 u8 reserved_at_a0[0x8]; 10832 u8 table_id[0x18]; 10833 10834 u8 reserved_at_c0[0x8]; 10835 u8 underlay_qpn[0x18]; 10836 u8 table_eswitch_owner_vhca_id_valid[0x1]; 10837 u8 reserved_at_e1[0xf]; 10838 u8 table_eswitch_owner_vhca_id[0x10]; 10839 u8 reserved_at_100[0x100]; 10840 }; 10841 10842 enum { 10843 MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = (1UL << 0), 10844 MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15), 10845 }; 10846 10847 struct mlx5_ifc_modify_flow_table_out_bits { 10848 u8 status[0x8]; 10849 u8 reserved_at_8[0x18]; 10850 10851 u8 syndrome[0x20]; 10852 10853 u8 reserved_at_40[0x40]; 10854 }; 10855 10856 struct mlx5_ifc_modify_flow_table_in_bits { 10857 u8 opcode[0x10]; 10858 u8 reserved_at_10[0x10]; 10859 10860 u8 reserved_at_20[0x10]; 10861 u8 op_mod[0x10]; 10862 10863 u8 other_vport[0x1]; 10864 u8 reserved_at_41[0xf]; 10865 u8 vport_number[0x10]; 10866 10867 u8 reserved_at_60[0x10]; 10868 u8 modify_field_select[0x10]; 10869 10870 u8 table_type[0x8]; 10871 u8 reserved_at_88[0x18]; 10872 10873 u8 reserved_at_a0[0x8]; 10874 u8 table_id[0x18]; 10875 10876 struct mlx5_ifc_flow_table_context_bits flow_table_context; 10877 }; 10878 10879 struct mlx5_ifc_ets_tcn_config_reg_bits { 10880 u8 g[0x1]; 10881 u8 b[0x1]; 10882 u8 r[0x1]; 10883 u8 reserved_at_3[0x9]; 10884 u8 group[0x4]; 10885 u8 reserved_at_10[0x9]; 10886 u8 bw_allocation[0x7]; 10887 10888 u8 reserved_at_20[0xc]; 10889 u8 max_bw_units[0x4]; 10890 u8 reserved_at_30[0x8]; 10891 u8 max_bw_value[0x8]; 10892 }; 10893 10894 struct mlx5_ifc_ets_global_config_reg_bits { 10895 u8 reserved_at_0[0x2]; 10896 u8 r[0x1]; 10897 u8 reserved_at_3[0x1d]; 10898 10899 u8 reserved_at_20[0xc]; 10900 u8 max_bw_units[0x4]; 10901 u8 reserved_at_30[0x8]; 10902 u8 max_bw_value[0x8]; 10903 }; 10904 10905 struct mlx5_ifc_qetc_reg_bits { 10906 u8 reserved_at_0[0x8]; 10907 u8 port_number[0x8]; 10908 u8 reserved_at_10[0x30]; 10909 10910 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8]; 10911 struct mlx5_ifc_ets_global_config_reg_bits global_configuration; 10912 }; 10913 10914 struct mlx5_ifc_qpdpm_dscp_reg_bits { 10915 u8 e[0x1]; 10916 u8 reserved_at_01[0x0b]; 10917 u8 prio[0x04]; 10918 }; 10919 10920 struct mlx5_ifc_qpdpm_reg_bits { 10921 u8 reserved_at_0[0x8]; 10922 u8 local_port[0x8]; 10923 u8 reserved_at_10[0x10]; 10924 struct mlx5_ifc_qpdpm_dscp_reg_bits dscp[64]; 10925 }; 10926 10927 struct mlx5_ifc_qpts_reg_bits { 10928 u8 reserved_at_0[0x8]; 10929 u8 local_port[0x8]; 10930 u8 reserved_at_10[0x2d]; 10931 u8 trust_state[0x3]; 10932 }; 10933 10934 struct mlx5_ifc_pptb_reg_bits { 10935 u8 reserved_at_0[0x2]; 10936 u8 mm[0x2]; 10937 u8 reserved_at_4[0x4]; 10938 u8 local_port[0x8]; 10939 u8 reserved_at_10[0x6]; 10940 u8 cm[0x1]; 10941 u8 um[0x1]; 10942 u8 pm[0x8]; 10943 10944 u8 prio_x_buff[0x20]; 10945 10946 u8 pm_msb[0x8]; 10947 u8 reserved_at_48[0x10]; 10948 u8 ctrl_buff[0x4]; 10949 u8 untagged_buff[0x4]; 10950 }; 10951 10952 struct mlx5_ifc_sbcam_reg_bits { 10953 u8 reserved_at_0[0x8]; 10954 u8 feature_group[0x8]; 10955 u8 reserved_at_10[0x8]; 10956 u8 access_reg_group[0x8]; 10957 10958 u8 reserved_at_20[0x20]; 10959 10960 u8 sb_access_reg_cap_mask[4][0x20]; 10961 10962 u8 reserved_at_c0[0x80]; 10963 10964 u8 sb_feature_cap_mask[4][0x20]; 10965 10966 u8 reserved_at_1c0[0x40]; 10967 10968 u8 cap_total_buffer_size[0x20]; 10969 10970 u8 cap_cell_size[0x10]; 10971 u8 cap_max_pg_buffers[0x8]; 10972 u8 cap_num_pool_supported[0x8]; 10973 10974 u8 reserved_at_240[0x8]; 10975 u8 cap_sbsr_stat_size[0x8]; 10976 u8 cap_max_tclass_data[0x8]; 10977 u8 cap_max_cpu_ingress_tclass_sb[0x8]; 10978 }; 10979 10980 struct mlx5_ifc_pbmc_reg_bits { 10981 u8 reserved_at_0[0x8]; 10982 u8 local_port[0x8]; 10983 u8 reserved_at_10[0x10]; 10984 10985 u8 xoff_timer_value[0x10]; 10986 u8 xoff_refresh[0x10]; 10987 10988 u8 reserved_at_40[0x9]; 10989 u8 fullness_threshold[0x7]; 10990 u8 port_buffer_size[0x10]; 10991 10992 struct mlx5_ifc_bufferx_reg_bits buffer[10]; 10993 10994 u8 reserved_at_2e0[0x80]; 10995 }; 10996 10997 struct mlx5_ifc_qtct_reg_bits { 10998 u8 reserved_at_0[0x8]; 10999 u8 port_number[0x8]; 11000 u8 reserved_at_10[0xd]; 11001 u8 prio[0x3]; 11002 11003 u8 reserved_at_20[0x1d]; 11004 u8 tclass[0x3]; 11005 }; 11006 11007 struct mlx5_ifc_mcia_reg_bits { 11008 u8 l[0x1]; 11009 u8 reserved_at_1[0x7]; 11010 u8 module[0x8]; 11011 u8 reserved_at_10[0x8]; 11012 u8 status[0x8]; 11013 11014 u8 i2c_device_address[0x8]; 11015 u8 page_number[0x8]; 11016 u8 device_address[0x10]; 11017 11018 u8 reserved_at_40[0x10]; 11019 u8 size[0x10]; 11020 11021 u8 reserved_at_60[0x20]; 11022 11023 u8 dword_0[0x20]; 11024 u8 dword_1[0x20]; 11025 u8 dword_2[0x20]; 11026 u8 dword_3[0x20]; 11027 u8 dword_4[0x20]; 11028 u8 dword_5[0x20]; 11029 u8 dword_6[0x20]; 11030 u8 dword_7[0x20]; 11031 u8 dword_8[0x20]; 11032 u8 dword_9[0x20]; 11033 u8 dword_10[0x20]; 11034 u8 dword_11[0x20]; 11035 }; 11036 11037 struct mlx5_ifc_dcbx_param_bits { 11038 u8 dcbx_cee_cap[0x1]; 11039 u8 dcbx_ieee_cap[0x1]; 11040 u8 dcbx_standby_cap[0x1]; 11041 u8 reserved_at_3[0x5]; 11042 u8 port_number[0x8]; 11043 u8 reserved_at_10[0xa]; 11044 u8 max_application_table_size[6]; 11045 u8 reserved_at_20[0x15]; 11046 u8 version_oper[0x3]; 11047 u8 reserved_at_38[5]; 11048 u8 version_admin[0x3]; 11049 u8 willing_admin[0x1]; 11050 u8 reserved_at_41[0x3]; 11051 u8 pfc_cap_oper[0x4]; 11052 u8 reserved_at_48[0x4]; 11053 u8 pfc_cap_admin[0x4]; 11054 u8 reserved_at_50[0x4]; 11055 u8 num_of_tc_oper[0x4]; 11056 u8 reserved_at_58[0x4]; 11057 u8 num_of_tc_admin[0x4]; 11058 u8 remote_willing[0x1]; 11059 u8 reserved_at_61[3]; 11060 u8 remote_pfc_cap[4]; 11061 u8 reserved_at_68[0x14]; 11062 u8 remote_num_of_tc[0x4]; 11063 u8 reserved_at_80[0x18]; 11064 u8 error[0x8]; 11065 u8 reserved_at_a0[0x160]; 11066 }; 11067 11068 enum { 11069 MLX5_LAG_PORT_SELECT_MODE_QUEUE_AFFINITY = 0, 11070 MLX5_LAG_PORT_SELECT_MODE_PORT_SELECT_FT = 1, 11071 MLX5_LAG_PORT_SELECT_MODE_PORT_SELECT_MPESW = 2, 11072 }; 11073 11074 struct mlx5_ifc_lagc_bits { 11075 u8 fdb_selection_mode[0x1]; 11076 u8 reserved_at_1[0x14]; 11077 u8 port_select_mode[0x3]; 11078 u8 reserved_at_18[0x5]; 11079 u8 lag_state[0x3]; 11080 11081 u8 reserved_at_20[0xc]; 11082 u8 active_port[0x4]; 11083 u8 reserved_at_30[0x4]; 11084 u8 tx_remap_affinity_2[0x4]; 11085 u8 reserved_at_38[0x4]; 11086 u8 tx_remap_affinity_1[0x4]; 11087 }; 11088 11089 struct mlx5_ifc_create_lag_out_bits { 11090 u8 status[0x8]; 11091 u8 reserved_at_8[0x18]; 11092 11093 u8 syndrome[0x20]; 11094 11095 u8 reserved_at_40[0x40]; 11096 }; 11097 11098 struct mlx5_ifc_create_lag_in_bits { 11099 u8 opcode[0x10]; 11100 u8 reserved_at_10[0x10]; 11101 11102 u8 reserved_at_20[0x10]; 11103 u8 op_mod[0x10]; 11104 11105 struct mlx5_ifc_lagc_bits ctx; 11106 }; 11107 11108 struct mlx5_ifc_modify_lag_out_bits { 11109 u8 status[0x8]; 11110 u8 reserved_at_8[0x18]; 11111 11112 u8 syndrome[0x20]; 11113 11114 u8 reserved_at_40[0x40]; 11115 }; 11116 11117 struct mlx5_ifc_modify_lag_in_bits { 11118 u8 opcode[0x10]; 11119 u8 reserved_at_10[0x10]; 11120 11121 u8 reserved_at_20[0x10]; 11122 u8 op_mod[0x10]; 11123 11124 u8 reserved_at_40[0x20]; 11125 u8 field_select[0x20]; 11126 11127 struct mlx5_ifc_lagc_bits ctx; 11128 }; 11129 11130 struct mlx5_ifc_query_lag_out_bits { 11131 u8 status[0x8]; 11132 u8 reserved_at_8[0x18]; 11133 11134 u8 syndrome[0x20]; 11135 11136 struct mlx5_ifc_lagc_bits ctx; 11137 }; 11138 11139 struct mlx5_ifc_query_lag_in_bits { 11140 u8 opcode[0x10]; 11141 u8 reserved_at_10[0x10]; 11142 11143 u8 reserved_at_20[0x10]; 11144 u8 op_mod[0x10]; 11145 11146 u8 reserved_at_40[0x40]; 11147 }; 11148 11149 struct mlx5_ifc_destroy_lag_out_bits { 11150 u8 status[0x8]; 11151 u8 reserved_at_8[0x18]; 11152 11153 u8 syndrome[0x20]; 11154 11155 u8 reserved_at_40[0x40]; 11156 }; 11157 11158 struct mlx5_ifc_destroy_lag_in_bits { 11159 u8 opcode[0x10]; 11160 u8 reserved_at_10[0x10]; 11161 11162 u8 reserved_at_20[0x10]; 11163 u8 op_mod[0x10]; 11164 11165 u8 reserved_at_40[0x40]; 11166 }; 11167 11168 struct mlx5_ifc_create_vport_lag_out_bits { 11169 u8 status[0x8]; 11170 u8 reserved_at_8[0x18]; 11171 11172 u8 syndrome[0x20]; 11173 11174 u8 reserved_at_40[0x40]; 11175 }; 11176 11177 struct mlx5_ifc_create_vport_lag_in_bits { 11178 u8 opcode[0x10]; 11179 u8 reserved_at_10[0x10]; 11180 11181 u8 reserved_at_20[0x10]; 11182 u8 op_mod[0x10]; 11183 11184 u8 reserved_at_40[0x40]; 11185 }; 11186 11187 struct mlx5_ifc_destroy_vport_lag_out_bits { 11188 u8 status[0x8]; 11189 u8 reserved_at_8[0x18]; 11190 11191 u8 syndrome[0x20]; 11192 11193 u8 reserved_at_40[0x40]; 11194 }; 11195 11196 struct mlx5_ifc_destroy_vport_lag_in_bits { 11197 u8 opcode[0x10]; 11198 u8 reserved_at_10[0x10]; 11199 11200 u8 reserved_at_20[0x10]; 11201 u8 op_mod[0x10]; 11202 11203 u8 reserved_at_40[0x40]; 11204 }; 11205 11206 enum { 11207 MLX5_MODIFY_MEMIC_OP_MOD_ALLOC, 11208 MLX5_MODIFY_MEMIC_OP_MOD_DEALLOC, 11209 }; 11210 11211 struct mlx5_ifc_modify_memic_in_bits { 11212 u8 opcode[0x10]; 11213 u8 uid[0x10]; 11214 11215 u8 reserved_at_20[0x10]; 11216 u8 op_mod[0x10]; 11217 11218 u8 reserved_at_40[0x20]; 11219 11220 u8 reserved_at_60[0x18]; 11221 u8 memic_operation_type[0x8]; 11222 11223 u8 memic_start_addr[0x40]; 11224 11225 u8 reserved_at_c0[0x140]; 11226 }; 11227 11228 struct mlx5_ifc_modify_memic_out_bits { 11229 u8 status[0x8]; 11230 u8 reserved_at_8[0x18]; 11231 11232 u8 syndrome[0x20]; 11233 11234 u8 reserved_at_40[0x40]; 11235 11236 u8 memic_operation_addr[0x40]; 11237 11238 u8 reserved_at_c0[0x140]; 11239 }; 11240 11241 struct mlx5_ifc_alloc_memic_in_bits { 11242 u8 opcode[0x10]; 11243 u8 reserved_at_10[0x10]; 11244 11245 u8 reserved_at_20[0x10]; 11246 u8 op_mod[0x10]; 11247 11248 u8 reserved_at_30[0x20]; 11249 11250 u8 reserved_at_40[0x18]; 11251 u8 log_memic_addr_alignment[0x8]; 11252 11253 u8 range_start_addr[0x40]; 11254 11255 u8 range_size[0x20]; 11256 11257 u8 memic_size[0x20]; 11258 }; 11259 11260 struct mlx5_ifc_alloc_memic_out_bits { 11261 u8 status[0x8]; 11262 u8 reserved_at_8[0x18]; 11263 11264 u8 syndrome[0x20]; 11265 11266 u8 memic_start_addr[0x40]; 11267 }; 11268 11269 struct mlx5_ifc_dealloc_memic_in_bits { 11270 u8 opcode[0x10]; 11271 u8 reserved_at_10[0x10]; 11272 11273 u8 reserved_at_20[0x10]; 11274 u8 op_mod[0x10]; 11275 11276 u8 reserved_at_40[0x40]; 11277 11278 u8 memic_start_addr[0x40]; 11279 11280 u8 memic_size[0x20]; 11281 11282 u8 reserved_at_e0[0x20]; 11283 }; 11284 11285 struct mlx5_ifc_dealloc_memic_out_bits { 11286 u8 status[0x8]; 11287 u8 reserved_at_8[0x18]; 11288 11289 u8 syndrome[0x20]; 11290 11291 u8 reserved_at_40[0x40]; 11292 }; 11293 11294 struct mlx5_ifc_umem_bits { 11295 u8 reserved_at_0[0x80]; 11296 11297 u8 ats[0x1]; 11298 u8 reserved_at_81[0x1a]; 11299 u8 log_page_size[0x5]; 11300 11301 u8 page_offset[0x20]; 11302 11303 u8 num_of_mtt[0x40]; 11304 11305 struct mlx5_ifc_mtt_bits mtt[]; 11306 }; 11307 11308 struct mlx5_ifc_uctx_bits { 11309 u8 cap[0x20]; 11310 11311 u8 reserved_at_20[0x160]; 11312 }; 11313 11314 struct mlx5_ifc_sw_icm_bits { 11315 u8 modify_field_select[0x40]; 11316 11317 u8 reserved_at_40[0x18]; 11318 u8 log_sw_icm_size[0x8]; 11319 11320 u8 reserved_at_60[0x20]; 11321 11322 u8 sw_icm_start_addr[0x40]; 11323 11324 u8 reserved_at_c0[0x140]; 11325 }; 11326 11327 struct mlx5_ifc_geneve_tlv_option_bits { 11328 u8 modify_field_select[0x40]; 11329 11330 u8 reserved_at_40[0x18]; 11331 u8 geneve_option_fte_index[0x8]; 11332 11333 u8 option_class[0x10]; 11334 u8 option_type[0x8]; 11335 u8 reserved_at_78[0x3]; 11336 u8 option_data_length[0x5]; 11337 11338 u8 reserved_at_80[0x180]; 11339 }; 11340 11341 struct mlx5_ifc_create_umem_in_bits { 11342 u8 opcode[0x10]; 11343 u8 uid[0x10]; 11344 11345 u8 reserved_at_20[0x10]; 11346 u8 op_mod[0x10]; 11347 11348 u8 reserved_at_40[0x40]; 11349 11350 struct mlx5_ifc_umem_bits umem; 11351 }; 11352 11353 struct mlx5_ifc_create_umem_out_bits { 11354 u8 status[0x8]; 11355 u8 reserved_at_8[0x18]; 11356 11357 u8 syndrome[0x20]; 11358 11359 u8 reserved_at_40[0x8]; 11360 u8 umem_id[0x18]; 11361 11362 u8 reserved_at_60[0x20]; 11363 }; 11364 11365 struct mlx5_ifc_destroy_umem_in_bits { 11366 u8 opcode[0x10]; 11367 u8 uid[0x10]; 11368 11369 u8 reserved_at_20[0x10]; 11370 u8 op_mod[0x10]; 11371 11372 u8 reserved_at_40[0x8]; 11373 u8 umem_id[0x18]; 11374 11375 u8 reserved_at_60[0x20]; 11376 }; 11377 11378 struct mlx5_ifc_destroy_umem_out_bits { 11379 u8 status[0x8]; 11380 u8 reserved_at_8[0x18]; 11381 11382 u8 syndrome[0x20]; 11383 11384 u8 reserved_at_40[0x40]; 11385 }; 11386 11387 struct mlx5_ifc_create_uctx_in_bits { 11388 u8 opcode[0x10]; 11389 u8 reserved_at_10[0x10]; 11390 11391 u8 reserved_at_20[0x10]; 11392 u8 op_mod[0x10]; 11393 11394 u8 reserved_at_40[0x40]; 11395 11396 struct mlx5_ifc_uctx_bits uctx; 11397 }; 11398 11399 struct mlx5_ifc_create_uctx_out_bits { 11400 u8 status[0x8]; 11401 u8 reserved_at_8[0x18]; 11402 11403 u8 syndrome[0x20]; 11404 11405 u8 reserved_at_40[0x10]; 11406 u8 uid[0x10]; 11407 11408 u8 reserved_at_60[0x20]; 11409 }; 11410 11411 struct mlx5_ifc_destroy_uctx_in_bits { 11412 u8 opcode[0x10]; 11413 u8 reserved_at_10[0x10]; 11414 11415 u8 reserved_at_20[0x10]; 11416 u8 op_mod[0x10]; 11417 11418 u8 reserved_at_40[0x10]; 11419 u8 uid[0x10]; 11420 11421 u8 reserved_at_60[0x20]; 11422 }; 11423 11424 struct mlx5_ifc_destroy_uctx_out_bits { 11425 u8 status[0x8]; 11426 u8 reserved_at_8[0x18]; 11427 11428 u8 syndrome[0x20]; 11429 11430 u8 reserved_at_40[0x40]; 11431 }; 11432 11433 struct mlx5_ifc_create_sw_icm_in_bits { 11434 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 11435 struct mlx5_ifc_sw_icm_bits sw_icm; 11436 }; 11437 11438 struct mlx5_ifc_create_geneve_tlv_option_in_bits { 11439 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 11440 struct mlx5_ifc_geneve_tlv_option_bits geneve_tlv_opt; 11441 }; 11442 11443 struct mlx5_ifc_mtrc_string_db_param_bits { 11444 u8 string_db_base_address[0x20]; 11445 11446 u8 reserved_at_20[0x8]; 11447 u8 string_db_size[0x18]; 11448 }; 11449 11450 struct mlx5_ifc_mtrc_cap_bits { 11451 u8 trace_owner[0x1]; 11452 u8 trace_to_memory[0x1]; 11453 u8 reserved_at_2[0x4]; 11454 u8 trc_ver[0x2]; 11455 u8 reserved_at_8[0x14]; 11456 u8 num_string_db[0x4]; 11457 11458 u8 first_string_trace[0x8]; 11459 u8 num_string_trace[0x8]; 11460 u8 reserved_at_30[0x28]; 11461 11462 u8 log_max_trace_buffer_size[0x8]; 11463 11464 u8 reserved_at_60[0x20]; 11465 11466 struct mlx5_ifc_mtrc_string_db_param_bits string_db_param[8]; 11467 11468 u8 reserved_at_280[0x180]; 11469 }; 11470 11471 struct mlx5_ifc_mtrc_conf_bits { 11472 u8 reserved_at_0[0x1c]; 11473 u8 trace_mode[0x4]; 11474 u8 reserved_at_20[0x18]; 11475 u8 log_trace_buffer_size[0x8]; 11476 u8 trace_mkey[0x20]; 11477 u8 reserved_at_60[0x3a0]; 11478 }; 11479 11480 struct mlx5_ifc_mtrc_stdb_bits { 11481 u8 string_db_index[0x4]; 11482 u8 reserved_at_4[0x4]; 11483 u8 read_size[0x18]; 11484 u8 start_offset[0x20]; 11485 u8 string_db_data[]; 11486 }; 11487 11488 struct mlx5_ifc_mtrc_ctrl_bits { 11489 u8 trace_status[0x2]; 11490 u8 reserved_at_2[0x2]; 11491 u8 arm_event[0x1]; 11492 u8 reserved_at_5[0xb]; 11493 u8 modify_field_select[0x10]; 11494 u8 reserved_at_20[0x2b]; 11495 u8 current_timestamp52_32[0x15]; 11496 u8 current_timestamp31_0[0x20]; 11497 u8 reserved_at_80[0x180]; 11498 }; 11499 11500 struct mlx5_ifc_host_params_context_bits { 11501 u8 host_number[0x8]; 11502 u8 reserved_at_8[0x7]; 11503 u8 host_pf_disabled[0x1]; 11504 u8 host_num_of_vfs[0x10]; 11505 11506 u8 host_total_vfs[0x10]; 11507 u8 host_pci_bus[0x10]; 11508 11509 u8 reserved_at_40[0x10]; 11510 u8 host_pci_device[0x10]; 11511 11512 u8 reserved_at_60[0x10]; 11513 u8 host_pci_function[0x10]; 11514 11515 u8 reserved_at_80[0x180]; 11516 }; 11517 11518 struct mlx5_ifc_query_esw_functions_in_bits { 11519 u8 opcode[0x10]; 11520 u8 reserved_at_10[0x10]; 11521 11522 u8 reserved_at_20[0x10]; 11523 u8 op_mod[0x10]; 11524 11525 u8 reserved_at_40[0x40]; 11526 }; 11527 11528 struct mlx5_ifc_query_esw_functions_out_bits { 11529 u8 status[0x8]; 11530 u8 reserved_at_8[0x18]; 11531 11532 u8 syndrome[0x20]; 11533 11534 u8 reserved_at_40[0x40]; 11535 11536 struct mlx5_ifc_host_params_context_bits host_params_context; 11537 11538 u8 reserved_at_280[0x180]; 11539 u8 host_sf_enable[][0x40]; 11540 }; 11541 11542 struct mlx5_ifc_sf_partition_bits { 11543 u8 reserved_at_0[0x10]; 11544 u8 log_num_sf[0x8]; 11545 u8 log_sf_bar_size[0x8]; 11546 }; 11547 11548 struct mlx5_ifc_query_sf_partitions_out_bits { 11549 u8 status[0x8]; 11550 u8 reserved_at_8[0x18]; 11551 11552 u8 syndrome[0x20]; 11553 11554 u8 reserved_at_40[0x18]; 11555 u8 num_sf_partitions[0x8]; 11556 11557 u8 reserved_at_60[0x20]; 11558 11559 struct mlx5_ifc_sf_partition_bits sf_partition[]; 11560 }; 11561 11562 struct mlx5_ifc_query_sf_partitions_in_bits { 11563 u8 opcode[0x10]; 11564 u8 reserved_at_10[0x10]; 11565 11566 u8 reserved_at_20[0x10]; 11567 u8 op_mod[0x10]; 11568 11569 u8 reserved_at_40[0x40]; 11570 }; 11571 11572 struct mlx5_ifc_dealloc_sf_out_bits { 11573 u8 status[0x8]; 11574 u8 reserved_at_8[0x18]; 11575 11576 u8 syndrome[0x20]; 11577 11578 u8 reserved_at_40[0x40]; 11579 }; 11580 11581 struct mlx5_ifc_dealloc_sf_in_bits { 11582 u8 opcode[0x10]; 11583 u8 reserved_at_10[0x10]; 11584 11585 u8 reserved_at_20[0x10]; 11586 u8 op_mod[0x10]; 11587 11588 u8 reserved_at_40[0x10]; 11589 u8 function_id[0x10]; 11590 11591 u8 reserved_at_60[0x20]; 11592 }; 11593 11594 struct mlx5_ifc_alloc_sf_out_bits { 11595 u8 status[0x8]; 11596 u8 reserved_at_8[0x18]; 11597 11598 u8 syndrome[0x20]; 11599 11600 u8 reserved_at_40[0x40]; 11601 }; 11602 11603 struct mlx5_ifc_alloc_sf_in_bits { 11604 u8 opcode[0x10]; 11605 u8 reserved_at_10[0x10]; 11606 11607 u8 reserved_at_20[0x10]; 11608 u8 op_mod[0x10]; 11609 11610 u8 reserved_at_40[0x10]; 11611 u8 function_id[0x10]; 11612 11613 u8 reserved_at_60[0x20]; 11614 }; 11615 11616 struct mlx5_ifc_affiliated_event_header_bits { 11617 u8 reserved_at_0[0x10]; 11618 u8 obj_type[0x10]; 11619 11620 u8 obj_id[0x20]; 11621 }; 11622 11623 enum { 11624 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = BIT_ULL(0xc), 11625 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_IPSEC = BIT_ULL(0x13), 11626 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_SAMPLER = BIT_ULL(0x20), 11627 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_FLOW_METER_ASO = BIT_ULL(0x24), 11628 }; 11629 11630 enum { 11631 MLX5_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = 0xc, 11632 MLX5_GENERAL_OBJECT_TYPES_IPSEC = 0x13, 11633 MLX5_GENERAL_OBJECT_TYPES_SAMPLER = 0x20, 11634 MLX5_GENERAL_OBJECT_TYPES_FLOW_METER_ASO = 0x24, 11635 MLX5_GENERAL_OBJECT_TYPES_MACSEC = 0x27, 11636 }; 11637 11638 enum { 11639 MLX5_IPSEC_OBJECT_ICV_LEN_16B, 11640 }; 11641 11642 enum { 11643 MLX5_IPSEC_ASO_REG_C_0_1 = 0x0, 11644 MLX5_IPSEC_ASO_REG_C_2_3 = 0x1, 11645 MLX5_IPSEC_ASO_REG_C_4_5 = 0x2, 11646 MLX5_IPSEC_ASO_REG_C_6_7 = 0x3, 11647 }; 11648 11649 enum { 11650 MLX5_IPSEC_ASO_MODE = 0x0, 11651 MLX5_IPSEC_ASO_REPLAY_PROTECTION = 0x1, 11652 MLX5_IPSEC_ASO_INC_SN = 0x2, 11653 }; 11654 11655 struct mlx5_ifc_ipsec_aso_bits { 11656 u8 valid[0x1]; 11657 u8 reserved_at_201[0x1]; 11658 u8 mode[0x2]; 11659 u8 window_sz[0x2]; 11660 u8 soft_lft_arm[0x1]; 11661 u8 hard_lft_arm[0x1]; 11662 u8 remove_flow_enable[0x1]; 11663 u8 esn_event_arm[0x1]; 11664 u8 reserved_at_20a[0x16]; 11665 11666 u8 remove_flow_pkt_cnt[0x20]; 11667 11668 u8 remove_flow_soft_lft[0x20]; 11669 11670 u8 reserved_at_260[0x80]; 11671 11672 u8 mode_parameter[0x20]; 11673 11674 u8 replay_protection_window[0x100]; 11675 }; 11676 11677 struct mlx5_ifc_ipsec_obj_bits { 11678 u8 modify_field_select[0x40]; 11679 u8 full_offload[0x1]; 11680 u8 reserved_at_41[0x1]; 11681 u8 esn_en[0x1]; 11682 u8 esn_overlap[0x1]; 11683 u8 reserved_at_44[0x2]; 11684 u8 icv_length[0x2]; 11685 u8 reserved_at_48[0x4]; 11686 u8 aso_return_reg[0x4]; 11687 u8 reserved_at_50[0x10]; 11688 11689 u8 esn_msb[0x20]; 11690 11691 u8 reserved_at_80[0x8]; 11692 u8 dekn[0x18]; 11693 11694 u8 salt[0x20]; 11695 11696 u8 implicit_iv[0x40]; 11697 11698 u8 reserved_at_100[0x8]; 11699 u8 ipsec_aso_access_pd[0x18]; 11700 u8 reserved_at_120[0xe0]; 11701 11702 struct mlx5_ifc_ipsec_aso_bits ipsec_aso; 11703 }; 11704 11705 struct mlx5_ifc_create_ipsec_obj_in_bits { 11706 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 11707 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 11708 }; 11709 11710 enum { 11711 MLX5_MODIFY_IPSEC_BITMASK_ESN_OVERLAP = BIT(0), 11712 MLX5_MODIFY_IPSEC_BITMASK_ESN_MSB = BIT(1), 11713 }; 11714 11715 struct mlx5_ifc_query_ipsec_obj_out_bits { 11716 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 11717 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 11718 }; 11719 11720 struct mlx5_ifc_modify_ipsec_obj_in_bits { 11721 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 11722 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 11723 }; 11724 11725 enum { 11726 MLX5_MACSEC_ASO_REPLAY_PROTECTION = 0x1, 11727 }; 11728 11729 enum { 11730 MLX5_MACSEC_ASO_REPLAY_WIN_32BIT = 0x0, 11731 MLX5_MACSEC_ASO_REPLAY_WIN_64BIT = 0x1, 11732 MLX5_MACSEC_ASO_REPLAY_WIN_128BIT = 0x2, 11733 MLX5_MACSEC_ASO_REPLAY_WIN_256BIT = 0x3, 11734 }; 11735 11736 #define MLX5_MACSEC_ASO_INC_SN 0x2 11737 #define MLX5_MACSEC_ASO_REG_C_4_5 0x2 11738 11739 struct mlx5_ifc_macsec_aso_bits { 11740 u8 valid[0x1]; 11741 u8 reserved_at_1[0x1]; 11742 u8 mode[0x2]; 11743 u8 window_size[0x2]; 11744 u8 soft_lifetime_arm[0x1]; 11745 u8 hard_lifetime_arm[0x1]; 11746 u8 remove_flow_enable[0x1]; 11747 u8 epn_event_arm[0x1]; 11748 u8 reserved_at_a[0x16]; 11749 11750 u8 remove_flow_packet_count[0x20]; 11751 11752 u8 remove_flow_soft_lifetime[0x20]; 11753 11754 u8 reserved_at_60[0x80]; 11755 11756 u8 mode_parameter[0x20]; 11757 11758 u8 replay_protection_window[8][0x20]; 11759 }; 11760 11761 struct mlx5_ifc_macsec_offload_obj_bits { 11762 u8 modify_field_select[0x40]; 11763 11764 u8 confidentiality_en[0x1]; 11765 u8 reserved_at_41[0x1]; 11766 u8 epn_en[0x1]; 11767 u8 epn_overlap[0x1]; 11768 u8 reserved_at_44[0x2]; 11769 u8 confidentiality_offset[0x2]; 11770 u8 reserved_at_48[0x4]; 11771 u8 aso_return_reg[0x4]; 11772 u8 reserved_at_50[0x10]; 11773 11774 u8 epn_msb[0x20]; 11775 11776 u8 reserved_at_80[0x8]; 11777 u8 dekn[0x18]; 11778 11779 u8 reserved_at_a0[0x20]; 11780 11781 u8 sci[0x40]; 11782 11783 u8 reserved_at_100[0x8]; 11784 u8 macsec_aso_access_pd[0x18]; 11785 11786 u8 reserved_at_120[0x60]; 11787 11788 u8 salt[3][0x20]; 11789 11790 u8 reserved_at_1e0[0x20]; 11791 11792 struct mlx5_ifc_macsec_aso_bits macsec_aso; 11793 }; 11794 11795 struct mlx5_ifc_create_macsec_obj_in_bits { 11796 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 11797 struct mlx5_ifc_macsec_offload_obj_bits macsec_object; 11798 }; 11799 11800 struct mlx5_ifc_modify_macsec_obj_in_bits { 11801 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 11802 struct mlx5_ifc_macsec_offload_obj_bits macsec_object; 11803 }; 11804 11805 enum { 11806 MLX5_MODIFY_MACSEC_BITMASK_EPN_OVERLAP = BIT(0), 11807 MLX5_MODIFY_MACSEC_BITMASK_EPN_MSB = BIT(1), 11808 }; 11809 11810 struct mlx5_ifc_query_macsec_obj_out_bits { 11811 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 11812 struct mlx5_ifc_macsec_offload_obj_bits macsec_object; 11813 }; 11814 11815 struct mlx5_ifc_encryption_key_obj_bits { 11816 u8 modify_field_select[0x40]; 11817 11818 u8 reserved_at_40[0x14]; 11819 u8 key_size[0x4]; 11820 u8 reserved_at_58[0x4]; 11821 u8 key_type[0x4]; 11822 11823 u8 reserved_at_60[0x8]; 11824 u8 pd[0x18]; 11825 11826 u8 reserved_at_80[0x180]; 11827 u8 key[8][0x20]; 11828 11829 u8 reserved_at_300[0x500]; 11830 }; 11831 11832 struct mlx5_ifc_create_encryption_key_in_bits { 11833 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 11834 struct mlx5_ifc_encryption_key_obj_bits encryption_key_object; 11835 }; 11836 11837 enum { 11838 MLX5_FLOW_METER_MODE_BYTES_IP_LENGTH = 0x0, 11839 MLX5_FLOW_METER_MODE_BYTES_CALC_WITH_L2 = 0x1, 11840 MLX5_FLOW_METER_MODE_BYTES_CALC_WITH_L2_IPG = 0x2, 11841 MLX5_FLOW_METER_MODE_NUM_PACKETS = 0x3, 11842 }; 11843 11844 struct mlx5_ifc_flow_meter_parameters_bits { 11845 u8 valid[0x1]; 11846 u8 bucket_overflow[0x1]; 11847 u8 start_color[0x2]; 11848 u8 both_buckets_on_green[0x1]; 11849 u8 reserved_at_5[0x1]; 11850 u8 meter_mode[0x2]; 11851 u8 reserved_at_8[0x18]; 11852 11853 u8 reserved_at_20[0x20]; 11854 11855 u8 reserved_at_40[0x3]; 11856 u8 cbs_exponent[0x5]; 11857 u8 cbs_mantissa[0x8]; 11858 u8 reserved_at_50[0x3]; 11859 u8 cir_exponent[0x5]; 11860 u8 cir_mantissa[0x8]; 11861 11862 u8 reserved_at_60[0x20]; 11863 11864 u8 reserved_at_80[0x3]; 11865 u8 ebs_exponent[0x5]; 11866 u8 ebs_mantissa[0x8]; 11867 u8 reserved_at_90[0x3]; 11868 u8 eir_exponent[0x5]; 11869 u8 eir_mantissa[0x8]; 11870 11871 u8 reserved_at_a0[0x60]; 11872 }; 11873 11874 struct mlx5_ifc_flow_meter_aso_obj_bits { 11875 u8 modify_field_select[0x40]; 11876 11877 u8 reserved_at_40[0x40]; 11878 11879 u8 reserved_at_80[0x8]; 11880 u8 meter_aso_access_pd[0x18]; 11881 11882 u8 reserved_at_a0[0x160]; 11883 11884 struct mlx5_ifc_flow_meter_parameters_bits flow_meter_parameters[2]; 11885 }; 11886 11887 struct mlx5_ifc_create_flow_meter_aso_obj_in_bits { 11888 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 11889 struct mlx5_ifc_flow_meter_aso_obj_bits flow_meter_aso_obj; 11890 }; 11891 11892 struct mlx5_ifc_sampler_obj_bits { 11893 u8 modify_field_select[0x40]; 11894 11895 u8 table_type[0x8]; 11896 u8 level[0x8]; 11897 u8 reserved_at_50[0xf]; 11898 u8 ignore_flow_level[0x1]; 11899 11900 u8 sample_ratio[0x20]; 11901 11902 u8 reserved_at_80[0x8]; 11903 u8 sample_table_id[0x18]; 11904 11905 u8 reserved_at_a0[0x8]; 11906 u8 default_table_id[0x18]; 11907 11908 u8 sw_steering_icm_address_rx[0x40]; 11909 u8 sw_steering_icm_address_tx[0x40]; 11910 11911 u8 reserved_at_140[0xa0]; 11912 }; 11913 11914 struct mlx5_ifc_create_sampler_obj_in_bits { 11915 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 11916 struct mlx5_ifc_sampler_obj_bits sampler_object; 11917 }; 11918 11919 struct mlx5_ifc_query_sampler_obj_out_bits { 11920 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 11921 struct mlx5_ifc_sampler_obj_bits sampler_object; 11922 }; 11923 11924 enum { 11925 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_128 = 0x0, 11926 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_256 = 0x1, 11927 }; 11928 11929 enum { 11930 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_TYPE_TLS = 0x1, 11931 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_TYPE_IPSEC = 0x2, 11932 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_TYPE_MACSEC = 0x4, 11933 }; 11934 11935 struct mlx5_ifc_tls_static_params_bits { 11936 u8 const_2[0x2]; 11937 u8 tls_version[0x4]; 11938 u8 const_1[0x2]; 11939 u8 reserved_at_8[0x14]; 11940 u8 encryption_standard[0x4]; 11941 11942 u8 reserved_at_20[0x20]; 11943 11944 u8 initial_record_number[0x40]; 11945 11946 u8 resync_tcp_sn[0x20]; 11947 11948 u8 gcm_iv[0x20]; 11949 11950 u8 implicit_iv[0x40]; 11951 11952 u8 reserved_at_100[0x8]; 11953 u8 dek_index[0x18]; 11954 11955 u8 reserved_at_120[0xe0]; 11956 }; 11957 11958 struct mlx5_ifc_tls_progress_params_bits { 11959 u8 next_record_tcp_sn[0x20]; 11960 11961 u8 hw_resync_tcp_sn[0x20]; 11962 11963 u8 record_tracker_state[0x2]; 11964 u8 auth_state[0x2]; 11965 u8 reserved_at_44[0x4]; 11966 u8 hw_offset_record_number[0x18]; 11967 }; 11968 11969 enum { 11970 MLX5_MTT_PERM_READ = 1 << 0, 11971 MLX5_MTT_PERM_WRITE = 1 << 1, 11972 MLX5_MTT_PERM_RW = MLX5_MTT_PERM_READ | MLX5_MTT_PERM_WRITE, 11973 }; 11974 11975 enum { 11976 MLX5_SUSPEND_VHCA_IN_OP_MOD_SUSPEND_INITIATOR = 0x0, 11977 MLX5_SUSPEND_VHCA_IN_OP_MOD_SUSPEND_RESPONDER = 0x1, 11978 }; 11979 11980 struct mlx5_ifc_suspend_vhca_in_bits { 11981 u8 opcode[0x10]; 11982 u8 uid[0x10]; 11983 11984 u8 reserved_at_20[0x10]; 11985 u8 op_mod[0x10]; 11986 11987 u8 reserved_at_40[0x10]; 11988 u8 vhca_id[0x10]; 11989 11990 u8 reserved_at_60[0x20]; 11991 }; 11992 11993 struct mlx5_ifc_suspend_vhca_out_bits { 11994 u8 status[0x8]; 11995 u8 reserved_at_8[0x18]; 11996 11997 u8 syndrome[0x20]; 11998 11999 u8 reserved_at_40[0x40]; 12000 }; 12001 12002 enum { 12003 MLX5_RESUME_VHCA_IN_OP_MOD_RESUME_RESPONDER = 0x0, 12004 MLX5_RESUME_VHCA_IN_OP_MOD_RESUME_INITIATOR = 0x1, 12005 }; 12006 12007 struct mlx5_ifc_resume_vhca_in_bits { 12008 u8 opcode[0x10]; 12009 u8 uid[0x10]; 12010 12011 u8 reserved_at_20[0x10]; 12012 u8 op_mod[0x10]; 12013 12014 u8 reserved_at_40[0x10]; 12015 u8 vhca_id[0x10]; 12016 12017 u8 reserved_at_60[0x20]; 12018 }; 12019 12020 struct mlx5_ifc_resume_vhca_out_bits { 12021 u8 status[0x8]; 12022 u8 reserved_at_8[0x18]; 12023 12024 u8 syndrome[0x20]; 12025 12026 u8 reserved_at_40[0x40]; 12027 }; 12028 12029 struct mlx5_ifc_query_vhca_migration_state_in_bits { 12030 u8 opcode[0x10]; 12031 u8 uid[0x10]; 12032 12033 u8 reserved_at_20[0x10]; 12034 u8 op_mod[0x10]; 12035 12036 u8 reserved_at_40[0x10]; 12037 u8 vhca_id[0x10]; 12038 12039 u8 reserved_at_60[0x20]; 12040 }; 12041 12042 struct mlx5_ifc_query_vhca_migration_state_out_bits { 12043 u8 status[0x8]; 12044 u8 reserved_at_8[0x18]; 12045 12046 u8 syndrome[0x20]; 12047 12048 u8 reserved_at_40[0x40]; 12049 12050 u8 required_umem_size[0x20]; 12051 12052 u8 reserved_at_a0[0x160]; 12053 }; 12054 12055 struct mlx5_ifc_save_vhca_state_in_bits { 12056 u8 opcode[0x10]; 12057 u8 uid[0x10]; 12058 12059 u8 reserved_at_20[0x10]; 12060 u8 op_mod[0x10]; 12061 12062 u8 reserved_at_40[0x10]; 12063 u8 vhca_id[0x10]; 12064 12065 u8 reserved_at_60[0x20]; 12066 12067 u8 va[0x40]; 12068 12069 u8 mkey[0x20]; 12070 12071 u8 size[0x20]; 12072 }; 12073 12074 struct mlx5_ifc_save_vhca_state_out_bits { 12075 u8 status[0x8]; 12076 u8 reserved_at_8[0x18]; 12077 12078 u8 syndrome[0x20]; 12079 12080 u8 actual_image_size[0x20]; 12081 12082 u8 reserved_at_60[0x20]; 12083 }; 12084 12085 struct mlx5_ifc_load_vhca_state_in_bits { 12086 u8 opcode[0x10]; 12087 u8 uid[0x10]; 12088 12089 u8 reserved_at_20[0x10]; 12090 u8 op_mod[0x10]; 12091 12092 u8 reserved_at_40[0x10]; 12093 u8 vhca_id[0x10]; 12094 12095 u8 reserved_at_60[0x20]; 12096 12097 u8 va[0x40]; 12098 12099 u8 mkey[0x20]; 12100 12101 u8 size[0x20]; 12102 }; 12103 12104 struct mlx5_ifc_load_vhca_state_out_bits { 12105 u8 status[0x8]; 12106 u8 reserved_at_8[0x18]; 12107 12108 u8 syndrome[0x20]; 12109 12110 u8 reserved_at_40[0x40]; 12111 }; 12112 12113 struct mlx5_ifc_adv_virtualization_cap_bits { 12114 u8 reserved_at_0[0x3]; 12115 u8 pg_track_log_max_num[0x5]; 12116 u8 pg_track_max_num_range[0x8]; 12117 u8 pg_track_log_min_addr_space[0x8]; 12118 u8 pg_track_log_max_addr_space[0x8]; 12119 12120 u8 reserved_at_20[0x3]; 12121 u8 pg_track_log_min_msg_size[0x5]; 12122 u8 reserved_at_28[0x3]; 12123 u8 pg_track_log_max_msg_size[0x5]; 12124 u8 reserved_at_30[0x3]; 12125 u8 pg_track_log_min_page_size[0x5]; 12126 u8 reserved_at_38[0x3]; 12127 u8 pg_track_log_max_page_size[0x5]; 12128 12129 u8 reserved_at_40[0x7c0]; 12130 }; 12131 12132 struct mlx5_ifc_page_track_report_entry_bits { 12133 u8 dirty_address_high[0x20]; 12134 12135 u8 dirty_address_low[0x20]; 12136 }; 12137 12138 enum { 12139 MLX5_PAGE_TRACK_STATE_TRACKING, 12140 MLX5_PAGE_TRACK_STATE_REPORTING, 12141 MLX5_PAGE_TRACK_STATE_ERROR, 12142 }; 12143 12144 struct mlx5_ifc_page_track_range_bits { 12145 u8 start_address[0x40]; 12146 12147 u8 length[0x40]; 12148 }; 12149 12150 struct mlx5_ifc_page_track_bits { 12151 u8 modify_field_select[0x40]; 12152 12153 u8 reserved_at_40[0x10]; 12154 u8 vhca_id[0x10]; 12155 12156 u8 reserved_at_60[0x20]; 12157 12158 u8 state[0x4]; 12159 u8 track_type[0x4]; 12160 u8 log_addr_space_size[0x8]; 12161 u8 reserved_at_90[0x3]; 12162 u8 log_page_size[0x5]; 12163 u8 reserved_at_98[0x3]; 12164 u8 log_msg_size[0x5]; 12165 12166 u8 reserved_at_a0[0x8]; 12167 u8 reporting_qpn[0x18]; 12168 12169 u8 reserved_at_c0[0x18]; 12170 u8 num_ranges[0x8]; 12171 12172 u8 reserved_at_e0[0x20]; 12173 12174 u8 range_start_address[0x40]; 12175 12176 u8 length[0x40]; 12177 12178 struct mlx5_ifc_page_track_range_bits track_range[0]; 12179 }; 12180 12181 struct mlx5_ifc_create_page_track_obj_in_bits { 12182 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12183 struct mlx5_ifc_page_track_bits obj_context; 12184 }; 12185 12186 struct mlx5_ifc_modify_page_track_obj_in_bits { 12187 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12188 struct mlx5_ifc_page_track_bits obj_context; 12189 }; 12190 12191 #endif /* MLX5_IFC_H */ 12192