1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 #ifndef MLX5_IFC_H 33 #define MLX5_IFC_H 34 35 enum { 36 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0, 37 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1, 38 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2, 39 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3, 40 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13, 41 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14, 42 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c, 43 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d, 44 MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4, 45 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5, 46 MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED = 0x7, 47 MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT = 0xc, 48 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10, 49 MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR = 0x11, 50 MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR = 0x12, 51 MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR = 0x8, 52 MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE = 0x9, 53 MLX5_EVENT_TYPE_CODING_GPIO_EVENT = 0x15, 54 MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19, 55 MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a, 56 MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT = 0x1b, 57 MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT = 0x1f, 58 MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa, 59 MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb 60 }; 61 62 enum { 63 MLX5_MODIFY_TIR_BITMASK_LRO = 0x0, 64 MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE = 0x1, 65 MLX5_MODIFY_TIR_BITMASK_HASH = 0x2, 66 MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN = 0x3 67 }; 68 69 enum { 70 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0, 71 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3, 72 }; 73 74 enum { 75 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100, 76 MLX5_CMD_OP_QUERY_ADAPTER = 0x101, 77 MLX5_CMD_OP_INIT_HCA = 0x102, 78 MLX5_CMD_OP_TEARDOWN_HCA = 0x103, 79 MLX5_CMD_OP_ENABLE_HCA = 0x104, 80 MLX5_CMD_OP_DISABLE_HCA = 0x105, 81 MLX5_CMD_OP_QUERY_PAGES = 0x107, 82 MLX5_CMD_OP_MANAGE_PAGES = 0x108, 83 MLX5_CMD_OP_SET_HCA_CAP = 0x109, 84 MLX5_CMD_OP_QUERY_ISSI = 0x10a, 85 MLX5_CMD_OP_SET_ISSI = 0x10b, 86 MLX5_CMD_OP_SET_DRIVER_VERSION = 0x10d, 87 MLX5_CMD_OP_CREATE_MKEY = 0x200, 88 MLX5_CMD_OP_QUERY_MKEY = 0x201, 89 MLX5_CMD_OP_DESTROY_MKEY = 0x202, 90 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203, 91 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204, 92 MLX5_CMD_OP_CREATE_EQ = 0x301, 93 MLX5_CMD_OP_DESTROY_EQ = 0x302, 94 MLX5_CMD_OP_QUERY_EQ = 0x303, 95 MLX5_CMD_OP_GEN_EQE = 0x304, 96 MLX5_CMD_OP_CREATE_CQ = 0x400, 97 MLX5_CMD_OP_DESTROY_CQ = 0x401, 98 MLX5_CMD_OP_QUERY_CQ = 0x402, 99 MLX5_CMD_OP_MODIFY_CQ = 0x403, 100 MLX5_CMD_OP_CREATE_QP = 0x500, 101 MLX5_CMD_OP_DESTROY_QP = 0x501, 102 MLX5_CMD_OP_RST2INIT_QP = 0x502, 103 MLX5_CMD_OP_INIT2RTR_QP = 0x503, 104 MLX5_CMD_OP_RTR2RTS_QP = 0x504, 105 MLX5_CMD_OP_RTS2RTS_QP = 0x505, 106 MLX5_CMD_OP_SQERR2RTS_QP = 0x506, 107 MLX5_CMD_OP_2ERR_QP = 0x507, 108 MLX5_CMD_OP_2RST_QP = 0x50a, 109 MLX5_CMD_OP_QUERY_QP = 0x50b, 110 MLX5_CMD_OP_SQD_RTS_QP = 0x50c, 111 MLX5_CMD_OP_INIT2INIT_QP = 0x50e, 112 MLX5_CMD_OP_CREATE_PSV = 0x600, 113 MLX5_CMD_OP_DESTROY_PSV = 0x601, 114 MLX5_CMD_OP_CREATE_SRQ = 0x700, 115 MLX5_CMD_OP_DESTROY_SRQ = 0x701, 116 MLX5_CMD_OP_QUERY_SRQ = 0x702, 117 MLX5_CMD_OP_ARM_RQ = 0x703, 118 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705, 119 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706, 120 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707, 121 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708, 122 MLX5_CMD_OP_CREATE_DCT = 0x710, 123 MLX5_CMD_OP_DESTROY_DCT = 0x711, 124 MLX5_CMD_OP_DRAIN_DCT = 0x712, 125 MLX5_CMD_OP_QUERY_DCT = 0x713, 126 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714, 127 MLX5_CMD_OP_CREATE_XRQ = 0x717, 128 MLX5_CMD_OP_DESTROY_XRQ = 0x718, 129 MLX5_CMD_OP_QUERY_XRQ = 0x719, 130 MLX5_CMD_OP_ARM_XRQ = 0x71a, 131 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750, 132 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751, 133 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752, 134 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753, 135 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754, 136 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755, 137 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760, 138 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761, 139 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762, 140 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763, 141 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764, 142 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765, 143 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770, 144 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771, 145 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772, 146 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773, 147 MLX5_CMD_OP_SET_RATE_LIMIT = 0x780, 148 MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781, 149 MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT = 0x782, 150 MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT = 0x783, 151 MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT = 0x784, 152 MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT = 0x785, 153 MLX5_CMD_OP_CREATE_QOS_PARA_VPORT = 0x786, 154 MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT = 0x787, 155 MLX5_CMD_OP_ALLOC_PD = 0x800, 156 MLX5_CMD_OP_DEALLOC_PD = 0x801, 157 MLX5_CMD_OP_ALLOC_UAR = 0x802, 158 MLX5_CMD_OP_DEALLOC_UAR = 0x803, 159 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804, 160 MLX5_CMD_OP_ACCESS_REG = 0x805, 161 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806, 162 MLX5_CMD_OP_DETACH_FROM_MCG = 0x807, 163 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a, 164 MLX5_CMD_OP_MAD_IFC = 0x50d, 165 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b, 166 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c, 167 MLX5_CMD_OP_NOP = 0x80d, 168 MLX5_CMD_OP_ALLOC_XRCD = 0x80e, 169 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f, 170 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816, 171 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817, 172 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822, 173 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823, 174 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824, 175 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825, 176 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826, 177 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827, 178 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828, 179 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829, 180 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a, 181 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b, 182 MLX5_CMD_OP_SET_WOL_ROL = 0x830, 183 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831, 184 MLX5_CMD_OP_CREATE_LAG = 0x840, 185 MLX5_CMD_OP_MODIFY_LAG = 0x841, 186 MLX5_CMD_OP_QUERY_LAG = 0x842, 187 MLX5_CMD_OP_DESTROY_LAG = 0x843, 188 MLX5_CMD_OP_CREATE_VPORT_LAG = 0x844, 189 MLX5_CMD_OP_DESTROY_VPORT_LAG = 0x845, 190 MLX5_CMD_OP_CREATE_TIR = 0x900, 191 MLX5_CMD_OP_MODIFY_TIR = 0x901, 192 MLX5_CMD_OP_DESTROY_TIR = 0x902, 193 MLX5_CMD_OP_QUERY_TIR = 0x903, 194 MLX5_CMD_OP_CREATE_SQ = 0x904, 195 MLX5_CMD_OP_MODIFY_SQ = 0x905, 196 MLX5_CMD_OP_DESTROY_SQ = 0x906, 197 MLX5_CMD_OP_QUERY_SQ = 0x907, 198 MLX5_CMD_OP_CREATE_RQ = 0x908, 199 MLX5_CMD_OP_MODIFY_RQ = 0x909, 200 MLX5_CMD_OP_DESTROY_RQ = 0x90a, 201 MLX5_CMD_OP_QUERY_RQ = 0x90b, 202 MLX5_CMD_OP_CREATE_RMP = 0x90c, 203 MLX5_CMD_OP_MODIFY_RMP = 0x90d, 204 MLX5_CMD_OP_DESTROY_RMP = 0x90e, 205 MLX5_CMD_OP_QUERY_RMP = 0x90f, 206 MLX5_CMD_OP_CREATE_TIS = 0x912, 207 MLX5_CMD_OP_MODIFY_TIS = 0x913, 208 MLX5_CMD_OP_DESTROY_TIS = 0x914, 209 MLX5_CMD_OP_QUERY_TIS = 0x915, 210 MLX5_CMD_OP_CREATE_RQT = 0x916, 211 MLX5_CMD_OP_MODIFY_RQT = 0x917, 212 MLX5_CMD_OP_DESTROY_RQT = 0x918, 213 MLX5_CMD_OP_QUERY_RQT = 0x919, 214 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f, 215 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930, 216 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931, 217 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932, 218 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933, 219 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934, 220 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935, 221 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936, 222 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937, 223 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938, 224 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939, 225 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a, 226 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b, 227 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c, 228 MLX5_CMD_OP_ALLOC_ENCAP_HEADER = 0x93d, 229 MLX5_CMD_OP_DEALLOC_ENCAP_HEADER = 0x93e, 230 MLX5_CMD_OP_MAX 231 }; 232 233 struct mlx5_ifc_flow_table_fields_supported_bits { 234 u8 outer_dmac[0x1]; 235 u8 outer_smac[0x1]; 236 u8 outer_ether_type[0x1]; 237 u8 reserved_at_3[0x1]; 238 u8 outer_first_prio[0x1]; 239 u8 outer_first_cfi[0x1]; 240 u8 outer_first_vid[0x1]; 241 u8 reserved_at_7[0x1]; 242 u8 outer_second_prio[0x1]; 243 u8 outer_second_cfi[0x1]; 244 u8 outer_second_vid[0x1]; 245 u8 reserved_at_b[0x1]; 246 u8 outer_sip[0x1]; 247 u8 outer_dip[0x1]; 248 u8 outer_frag[0x1]; 249 u8 outer_ip_protocol[0x1]; 250 u8 outer_ip_ecn[0x1]; 251 u8 outer_ip_dscp[0x1]; 252 u8 outer_udp_sport[0x1]; 253 u8 outer_udp_dport[0x1]; 254 u8 outer_tcp_sport[0x1]; 255 u8 outer_tcp_dport[0x1]; 256 u8 outer_tcp_flags[0x1]; 257 u8 outer_gre_protocol[0x1]; 258 u8 outer_gre_key[0x1]; 259 u8 outer_vxlan_vni[0x1]; 260 u8 reserved_at_1a[0x5]; 261 u8 source_eswitch_port[0x1]; 262 263 u8 inner_dmac[0x1]; 264 u8 inner_smac[0x1]; 265 u8 inner_ether_type[0x1]; 266 u8 reserved_at_23[0x1]; 267 u8 inner_first_prio[0x1]; 268 u8 inner_first_cfi[0x1]; 269 u8 inner_first_vid[0x1]; 270 u8 reserved_at_27[0x1]; 271 u8 inner_second_prio[0x1]; 272 u8 inner_second_cfi[0x1]; 273 u8 inner_second_vid[0x1]; 274 u8 reserved_at_2b[0x1]; 275 u8 inner_sip[0x1]; 276 u8 inner_dip[0x1]; 277 u8 inner_frag[0x1]; 278 u8 inner_ip_protocol[0x1]; 279 u8 inner_ip_ecn[0x1]; 280 u8 inner_ip_dscp[0x1]; 281 u8 inner_udp_sport[0x1]; 282 u8 inner_udp_dport[0x1]; 283 u8 inner_tcp_sport[0x1]; 284 u8 inner_tcp_dport[0x1]; 285 u8 inner_tcp_flags[0x1]; 286 u8 reserved_at_37[0x9]; 287 288 u8 reserved_at_40[0x40]; 289 }; 290 291 struct mlx5_ifc_flow_table_prop_layout_bits { 292 u8 ft_support[0x1]; 293 u8 reserved_at_1[0x1]; 294 u8 flow_counter[0x1]; 295 u8 flow_modify_en[0x1]; 296 u8 modify_root[0x1]; 297 u8 identified_miss_table_mode[0x1]; 298 u8 flow_table_modify[0x1]; 299 u8 encap[0x1]; 300 u8 decap[0x1]; 301 u8 reserved_at_9[0x17]; 302 303 u8 reserved_at_20[0x2]; 304 u8 log_max_ft_size[0x6]; 305 u8 reserved_at_28[0x10]; 306 u8 max_ft_level[0x8]; 307 308 u8 reserved_at_40[0x20]; 309 310 u8 reserved_at_60[0x18]; 311 u8 log_max_ft_num[0x8]; 312 313 u8 reserved_at_80[0x18]; 314 u8 log_max_destination[0x8]; 315 316 u8 reserved_at_a0[0x18]; 317 u8 log_max_flow[0x8]; 318 319 u8 reserved_at_c0[0x40]; 320 321 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support; 322 323 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support; 324 }; 325 326 struct mlx5_ifc_odp_per_transport_service_cap_bits { 327 u8 send[0x1]; 328 u8 receive[0x1]; 329 u8 write[0x1]; 330 u8 read[0x1]; 331 u8 atomic[0x1]; 332 u8 srq_receive[0x1]; 333 u8 reserved_at_6[0x1a]; 334 }; 335 336 struct mlx5_ifc_ipv4_layout_bits { 337 u8 reserved_at_0[0x60]; 338 339 u8 ipv4[0x20]; 340 }; 341 342 struct mlx5_ifc_ipv6_layout_bits { 343 u8 ipv6[16][0x8]; 344 }; 345 346 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits { 347 struct mlx5_ifc_ipv6_layout_bits ipv6_layout; 348 struct mlx5_ifc_ipv4_layout_bits ipv4_layout; 349 u8 reserved_at_0[0x80]; 350 }; 351 352 struct mlx5_ifc_fte_match_set_lyr_2_4_bits { 353 u8 smac_47_16[0x20]; 354 355 u8 smac_15_0[0x10]; 356 u8 ethertype[0x10]; 357 358 u8 dmac_47_16[0x20]; 359 360 u8 dmac_15_0[0x10]; 361 u8 first_prio[0x3]; 362 u8 first_cfi[0x1]; 363 u8 first_vid[0xc]; 364 365 u8 ip_protocol[0x8]; 366 u8 ip_dscp[0x6]; 367 u8 ip_ecn[0x2]; 368 u8 cvlan_tag[0x1]; 369 u8 svlan_tag[0x1]; 370 u8 frag[0x1]; 371 u8 reserved_at_93[0x4]; 372 u8 tcp_flags[0x9]; 373 374 u8 tcp_sport[0x10]; 375 u8 tcp_dport[0x10]; 376 377 u8 reserved_at_c0[0x20]; 378 379 u8 udp_sport[0x10]; 380 u8 udp_dport[0x10]; 381 382 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6; 383 384 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6; 385 }; 386 387 struct mlx5_ifc_fte_match_set_misc_bits { 388 u8 reserved_at_0[0x8]; 389 u8 source_sqn[0x18]; 390 391 u8 reserved_at_20[0x10]; 392 u8 source_port[0x10]; 393 394 u8 outer_second_prio[0x3]; 395 u8 outer_second_cfi[0x1]; 396 u8 outer_second_vid[0xc]; 397 u8 inner_second_prio[0x3]; 398 u8 inner_second_cfi[0x1]; 399 u8 inner_second_vid[0xc]; 400 401 u8 outer_second_cvlan_tag[0x1]; 402 u8 inner_second_cvlan_tag[0x1]; 403 u8 outer_second_svlan_tag[0x1]; 404 u8 inner_second_svlan_tag[0x1]; 405 u8 reserved_at_64[0xc]; 406 u8 gre_protocol[0x10]; 407 408 u8 gre_key_h[0x18]; 409 u8 gre_key_l[0x8]; 410 411 u8 vxlan_vni[0x18]; 412 u8 reserved_at_b8[0x8]; 413 414 u8 reserved_at_c0[0x20]; 415 416 u8 reserved_at_e0[0xc]; 417 u8 outer_ipv6_flow_label[0x14]; 418 419 u8 reserved_at_100[0xc]; 420 u8 inner_ipv6_flow_label[0x14]; 421 422 u8 reserved_at_120[0xe0]; 423 }; 424 425 struct mlx5_ifc_cmd_pas_bits { 426 u8 pa_h[0x20]; 427 428 u8 pa_l[0x14]; 429 u8 reserved_at_34[0xc]; 430 }; 431 432 struct mlx5_ifc_uint64_bits { 433 u8 hi[0x20]; 434 435 u8 lo[0x20]; 436 }; 437 438 enum { 439 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0, 440 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7, 441 MLX5_ADS_STAT_RATE_10GBPS = 0x8, 442 MLX5_ADS_STAT_RATE_30GBPS = 0x9, 443 MLX5_ADS_STAT_RATE_5GBPS = 0xa, 444 MLX5_ADS_STAT_RATE_20GBPS = 0xb, 445 MLX5_ADS_STAT_RATE_40GBPS = 0xc, 446 MLX5_ADS_STAT_RATE_60GBPS = 0xd, 447 MLX5_ADS_STAT_RATE_80GBPS = 0xe, 448 MLX5_ADS_STAT_RATE_120GBPS = 0xf, 449 }; 450 451 struct mlx5_ifc_ads_bits { 452 u8 fl[0x1]; 453 u8 free_ar[0x1]; 454 u8 reserved_at_2[0xe]; 455 u8 pkey_index[0x10]; 456 457 u8 reserved_at_20[0x8]; 458 u8 grh[0x1]; 459 u8 mlid[0x7]; 460 u8 rlid[0x10]; 461 462 u8 ack_timeout[0x5]; 463 u8 reserved_at_45[0x3]; 464 u8 src_addr_index[0x8]; 465 u8 reserved_at_50[0x4]; 466 u8 stat_rate[0x4]; 467 u8 hop_limit[0x8]; 468 469 u8 reserved_at_60[0x4]; 470 u8 tclass[0x8]; 471 u8 flow_label[0x14]; 472 473 u8 rgid_rip[16][0x8]; 474 475 u8 reserved_at_100[0x4]; 476 u8 f_dscp[0x1]; 477 u8 f_ecn[0x1]; 478 u8 reserved_at_106[0x1]; 479 u8 f_eth_prio[0x1]; 480 u8 ecn[0x2]; 481 u8 dscp[0x6]; 482 u8 udp_sport[0x10]; 483 484 u8 dei_cfi[0x1]; 485 u8 eth_prio[0x3]; 486 u8 sl[0x4]; 487 u8 port[0x8]; 488 u8 rmac_47_32[0x10]; 489 490 u8 rmac_31_0[0x20]; 491 }; 492 493 struct mlx5_ifc_flow_table_nic_cap_bits { 494 u8 nic_rx_multi_path_tirs[0x1]; 495 u8 nic_rx_multi_path_tirs_fts[0x1]; 496 u8 allow_sniffer_and_nic_rx_shared_tir[0x1]; 497 u8 reserved_at_3[0x1fd]; 498 499 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive; 500 501 u8 reserved_at_400[0x200]; 502 503 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer; 504 505 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit; 506 507 u8 reserved_at_a00[0x200]; 508 509 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer; 510 511 u8 reserved_at_e00[0x7200]; 512 }; 513 514 struct mlx5_ifc_flow_table_eswitch_cap_bits { 515 u8 reserved_at_0[0x200]; 516 517 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb; 518 519 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress; 520 521 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress; 522 523 u8 reserved_at_800[0x7800]; 524 }; 525 526 struct mlx5_ifc_e_switch_cap_bits { 527 u8 vport_svlan_strip[0x1]; 528 u8 vport_cvlan_strip[0x1]; 529 u8 vport_svlan_insert[0x1]; 530 u8 vport_cvlan_insert_if_not_exist[0x1]; 531 u8 vport_cvlan_insert_overwrite[0x1]; 532 u8 reserved_at_5[0x19]; 533 u8 nic_vport_node_guid_modify[0x1]; 534 u8 nic_vport_port_guid_modify[0x1]; 535 536 u8 vxlan_encap_decap[0x1]; 537 u8 nvgre_encap_decap[0x1]; 538 u8 reserved_at_22[0x9]; 539 u8 log_max_encap_headers[0x5]; 540 u8 reserved_2b[0x6]; 541 u8 max_encap_header_size[0xa]; 542 543 u8 reserved_40[0x7c0]; 544 545 }; 546 547 struct mlx5_ifc_qos_cap_bits { 548 u8 packet_pacing[0x1]; 549 u8 esw_scheduling[0x1]; 550 u8 esw_bw_share[0x1]; 551 u8 esw_rate_limit[0x1]; 552 u8 reserved_at_4[0x1c]; 553 554 u8 reserved_at_20[0x20]; 555 556 u8 packet_pacing_max_rate[0x20]; 557 558 u8 packet_pacing_min_rate[0x20]; 559 560 u8 reserved_at_80[0x10]; 561 u8 packet_pacing_rate_table_size[0x10]; 562 563 u8 esw_element_type[0x10]; 564 u8 esw_tsar_type[0x10]; 565 566 u8 reserved_at_c0[0x10]; 567 u8 max_qos_para_vport[0x10]; 568 569 u8 max_tsar_bw_share[0x20]; 570 571 u8 reserved_at_100[0x700]; 572 }; 573 574 struct mlx5_ifc_per_protocol_networking_offload_caps_bits { 575 u8 csum_cap[0x1]; 576 u8 vlan_cap[0x1]; 577 u8 lro_cap[0x1]; 578 u8 lro_psh_flag[0x1]; 579 u8 lro_time_stamp[0x1]; 580 u8 reserved_at_5[0x2]; 581 u8 wqe_vlan_insert[0x1]; 582 u8 self_lb_en_modifiable[0x1]; 583 u8 reserved_at_9[0x2]; 584 u8 max_lso_cap[0x5]; 585 u8 multi_pkt_send_wqe[0x2]; 586 u8 wqe_inline_mode[0x2]; 587 u8 rss_ind_tbl_cap[0x4]; 588 u8 reg_umr_sq[0x1]; 589 u8 scatter_fcs[0x1]; 590 u8 reserved_at_1a[0x1]; 591 u8 tunnel_lso_const_out_ip_id[0x1]; 592 u8 reserved_at_1c[0x2]; 593 u8 tunnel_statless_gre[0x1]; 594 u8 tunnel_stateless_vxlan[0x1]; 595 596 u8 reserved_at_20[0x20]; 597 598 u8 reserved_at_40[0x10]; 599 u8 lro_min_mss_size[0x10]; 600 601 u8 reserved_at_60[0x120]; 602 603 u8 lro_timer_supported_periods[4][0x20]; 604 605 u8 reserved_at_200[0x600]; 606 }; 607 608 struct mlx5_ifc_roce_cap_bits { 609 u8 roce_apm[0x1]; 610 u8 reserved_at_1[0x1f]; 611 612 u8 reserved_at_20[0x60]; 613 614 u8 reserved_at_80[0xc]; 615 u8 l3_type[0x4]; 616 u8 reserved_at_90[0x8]; 617 u8 roce_version[0x8]; 618 619 u8 reserved_at_a0[0x10]; 620 u8 r_roce_dest_udp_port[0x10]; 621 622 u8 r_roce_max_src_udp_port[0x10]; 623 u8 r_roce_min_src_udp_port[0x10]; 624 625 u8 reserved_at_e0[0x10]; 626 u8 roce_address_table_size[0x10]; 627 628 u8 reserved_at_100[0x700]; 629 }; 630 631 enum { 632 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0, 633 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2, 634 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4, 635 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8, 636 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10, 637 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20, 638 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40, 639 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80, 640 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100, 641 }; 642 643 enum { 644 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1, 645 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2, 646 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4, 647 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8, 648 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10, 649 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20, 650 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40, 651 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80, 652 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100, 653 }; 654 655 struct mlx5_ifc_atomic_caps_bits { 656 u8 reserved_at_0[0x40]; 657 658 u8 atomic_req_8B_endianess_mode[0x2]; 659 u8 reserved_at_42[0x4]; 660 u8 supported_atomic_req_8B_endianess_mode_1[0x1]; 661 662 u8 reserved_at_47[0x19]; 663 664 u8 reserved_at_60[0x20]; 665 666 u8 reserved_at_80[0x10]; 667 u8 atomic_operations[0x10]; 668 669 u8 reserved_at_a0[0x10]; 670 u8 atomic_size_qp[0x10]; 671 672 u8 reserved_at_c0[0x10]; 673 u8 atomic_size_dc[0x10]; 674 675 u8 reserved_at_e0[0x720]; 676 }; 677 678 struct mlx5_ifc_odp_cap_bits { 679 u8 reserved_at_0[0x40]; 680 681 u8 sig[0x1]; 682 u8 reserved_at_41[0x1f]; 683 684 u8 reserved_at_60[0x20]; 685 686 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps; 687 688 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps; 689 690 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps; 691 692 u8 reserved_at_e0[0x720]; 693 }; 694 695 struct mlx5_ifc_calc_op { 696 u8 reserved_at_0[0x10]; 697 u8 reserved_at_10[0x9]; 698 u8 op_swap_endianness[0x1]; 699 u8 op_min[0x1]; 700 u8 op_xor[0x1]; 701 u8 op_or[0x1]; 702 u8 op_and[0x1]; 703 u8 op_max[0x1]; 704 u8 op_add[0x1]; 705 }; 706 707 struct mlx5_ifc_vector_calc_cap_bits { 708 u8 calc_matrix[0x1]; 709 u8 reserved_at_1[0x1f]; 710 u8 reserved_at_20[0x8]; 711 u8 max_vec_count[0x8]; 712 u8 reserved_at_30[0xd]; 713 u8 max_chunk_size[0x3]; 714 struct mlx5_ifc_calc_op calc0; 715 struct mlx5_ifc_calc_op calc1; 716 struct mlx5_ifc_calc_op calc2; 717 struct mlx5_ifc_calc_op calc3; 718 719 u8 reserved_at_e0[0x720]; 720 }; 721 722 enum { 723 MLX5_WQ_TYPE_LINKED_LIST = 0x0, 724 MLX5_WQ_TYPE_CYCLIC = 0x1, 725 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2, 726 }; 727 728 enum { 729 MLX5_WQ_END_PAD_MODE_NONE = 0x0, 730 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1, 731 }; 732 733 enum { 734 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0, 735 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1, 736 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2, 737 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3, 738 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4, 739 }; 740 741 enum { 742 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0, 743 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1, 744 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2, 745 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3, 746 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4, 747 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5, 748 }; 749 750 enum { 751 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0, 752 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1, 753 }; 754 755 enum { 756 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0, 757 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1, 758 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3, 759 }; 760 761 enum { 762 MLX5_CAP_PORT_TYPE_IB = 0x0, 763 MLX5_CAP_PORT_TYPE_ETH = 0x1, 764 }; 765 766 struct mlx5_ifc_cmd_hca_cap_bits { 767 u8 reserved_at_0[0x80]; 768 769 u8 log_max_srq_sz[0x8]; 770 u8 log_max_qp_sz[0x8]; 771 u8 reserved_at_90[0xb]; 772 u8 log_max_qp[0x5]; 773 774 u8 reserved_at_a0[0xb]; 775 u8 log_max_srq[0x5]; 776 u8 reserved_at_b0[0x10]; 777 778 u8 reserved_at_c0[0x8]; 779 u8 log_max_cq_sz[0x8]; 780 u8 reserved_at_d0[0xb]; 781 u8 log_max_cq[0x5]; 782 783 u8 log_max_eq_sz[0x8]; 784 u8 reserved_at_e8[0x2]; 785 u8 log_max_mkey[0x6]; 786 u8 reserved_at_f0[0xc]; 787 u8 log_max_eq[0x4]; 788 789 u8 max_indirection[0x8]; 790 u8 fixed_buffer_size[0x1]; 791 u8 log_max_mrw_sz[0x7]; 792 u8 reserved_at_110[0x2]; 793 u8 log_max_bsf_list_size[0x6]; 794 u8 umr_extended_translation_offset[0x1]; 795 u8 null_mkey[0x1]; 796 u8 log_max_klm_list_size[0x6]; 797 798 u8 reserved_at_120[0xa]; 799 u8 log_max_ra_req_dc[0x6]; 800 u8 reserved_at_130[0xa]; 801 u8 log_max_ra_res_dc[0x6]; 802 803 u8 reserved_at_140[0xa]; 804 u8 log_max_ra_req_qp[0x6]; 805 u8 reserved_at_150[0xa]; 806 u8 log_max_ra_res_qp[0x6]; 807 808 u8 end_pad[0x1]; 809 u8 cc_query_allowed[0x1]; 810 u8 cc_modify_allowed[0x1]; 811 u8 start_pad[0x1]; 812 u8 cache_line_128byte[0x1]; 813 u8 reserved_at_163[0xb]; 814 u8 gid_table_size[0x10]; 815 816 u8 out_of_seq_cnt[0x1]; 817 u8 vport_counters[0x1]; 818 u8 retransmission_q_counters[0x1]; 819 u8 reserved_at_183[0x1]; 820 u8 modify_rq_counter_set_id[0x1]; 821 u8 reserved_at_185[0x1]; 822 u8 max_qp_cnt[0xa]; 823 u8 pkey_table_size[0x10]; 824 825 u8 vport_group_manager[0x1]; 826 u8 vhca_group_manager[0x1]; 827 u8 ib_virt[0x1]; 828 u8 eth_virt[0x1]; 829 u8 reserved_at_1a4[0x1]; 830 u8 ets[0x1]; 831 u8 nic_flow_table[0x1]; 832 u8 eswitch_flow_table[0x1]; 833 u8 early_vf_enable[0x1]; 834 u8 mcam_reg[0x1]; 835 u8 pcam_reg[0x1]; 836 u8 local_ca_ack_delay[0x5]; 837 u8 port_module_event[0x1]; 838 u8 reserved_at_1b1[0x1]; 839 u8 ports_check[0x1]; 840 u8 reserved_at_1b3[0x1]; 841 u8 disable_link_up[0x1]; 842 u8 beacon_led[0x1]; 843 u8 port_type[0x2]; 844 u8 num_ports[0x8]; 845 846 u8 reserved_at_1c0[0x1]; 847 u8 pps[0x1]; 848 u8 pps_modify[0x1]; 849 u8 log_max_msg[0x5]; 850 u8 reserved_at_1c8[0x4]; 851 u8 max_tc[0x4]; 852 u8 reserved_at_1d0[0x1]; 853 u8 dcbx[0x1]; 854 u8 reserved_at_1d2[0x4]; 855 u8 rol_s[0x1]; 856 u8 rol_g[0x1]; 857 u8 reserved_at_1d8[0x1]; 858 u8 wol_s[0x1]; 859 u8 wol_g[0x1]; 860 u8 wol_a[0x1]; 861 u8 wol_b[0x1]; 862 u8 wol_m[0x1]; 863 u8 wol_u[0x1]; 864 u8 wol_p[0x1]; 865 866 u8 stat_rate_support[0x10]; 867 u8 reserved_at_1f0[0xc]; 868 u8 cqe_version[0x4]; 869 870 u8 compact_address_vector[0x1]; 871 u8 striding_rq[0x1]; 872 u8 reserved_at_202[0x2]; 873 u8 ipoib_basic_offloads[0x1]; 874 u8 reserved_at_205[0xa]; 875 u8 drain_sigerr[0x1]; 876 u8 cmdif_checksum[0x2]; 877 u8 sigerr_cqe[0x1]; 878 u8 reserved_at_213[0x1]; 879 u8 wq_signature[0x1]; 880 u8 sctr_data_cqe[0x1]; 881 u8 reserved_at_216[0x1]; 882 u8 sho[0x1]; 883 u8 tph[0x1]; 884 u8 rf[0x1]; 885 u8 dct[0x1]; 886 u8 qos[0x1]; 887 u8 eth_net_offloads[0x1]; 888 u8 roce[0x1]; 889 u8 atomic[0x1]; 890 u8 reserved_at_21f[0x1]; 891 892 u8 cq_oi[0x1]; 893 u8 cq_resize[0x1]; 894 u8 cq_moderation[0x1]; 895 u8 reserved_at_223[0x3]; 896 u8 cq_eq_remap[0x1]; 897 u8 pg[0x1]; 898 u8 block_lb_mc[0x1]; 899 u8 reserved_at_229[0x1]; 900 u8 scqe_break_moderation[0x1]; 901 u8 cq_period_start_from_cqe[0x1]; 902 u8 cd[0x1]; 903 u8 reserved_at_22d[0x1]; 904 u8 apm[0x1]; 905 u8 vector_calc[0x1]; 906 u8 umr_ptr_rlky[0x1]; 907 u8 imaicl[0x1]; 908 u8 reserved_at_232[0x4]; 909 u8 qkv[0x1]; 910 u8 pkv[0x1]; 911 u8 set_deth_sqpn[0x1]; 912 u8 reserved_at_239[0x3]; 913 u8 xrc[0x1]; 914 u8 ud[0x1]; 915 u8 uc[0x1]; 916 u8 rc[0x1]; 917 918 u8 uar_4k[0x1]; 919 u8 reserved_at_241[0x9]; 920 u8 uar_sz[0x6]; 921 u8 reserved_at_250[0x8]; 922 u8 log_pg_sz[0x8]; 923 924 u8 bf[0x1]; 925 u8 driver_version[0x1]; 926 u8 pad_tx_eth_packet[0x1]; 927 u8 reserved_at_263[0x8]; 928 u8 log_bf_reg_size[0x5]; 929 930 u8 reserved_at_270[0xb]; 931 u8 lag_master[0x1]; 932 u8 num_lag_ports[0x4]; 933 934 u8 reserved_at_280[0x10]; 935 u8 max_wqe_sz_sq[0x10]; 936 937 u8 reserved_at_2a0[0x10]; 938 u8 max_wqe_sz_rq[0x10]; 939 940 u8 reserved_at_2c0[0x10]; 941 u8 max_wqe_sz_sq_dc[0x10]; 942 943 u8 reserved_at_2e0[0x7]; 944 u8 max_qp_mcg[0x19]; 945 946 u8 reserved_at_300[0x18]; 947 u8 log_max_mcg[0x8]; 948 949 u8 reserved_at_320[0x3]; 950 u8 log_max_transport_domain[0x5]; 951 u8 reserved_at_328[0x3]; 952 u8 log_max_pd[0x5]; 953 u8 reserved_at_330[0xb]; 954 u8 log_max_xrcd[0x5]; 955 956 u8 reserved_at_340[0x8]; 957 u8 log_max_flow_counter_bulk[0x8]; 958 u8 max_flow_counter[0x10]; 959 960 961 u8 reserved_at_360[0x3]; 962 u8 log_max_rq[0x5]; 963 u8 reserved_at_368[0x3]; 964 u8 log_max_sq[0x5]; 965 u8 reserved_at_370[0x3]; 966 u8 log_max_tir[0x5]; 967 u8 reserved_at_378[0x3]; 968 u8 log_max_tis[0x5]; 969 970 u8 basic_cyclic_rcv_wqe[0x1]; 971 u8 reserved_at_381[0x2]; 972 u8 log_max_rmp[0x5]; 973 u8 reserved_at_388[0x3]; 974 u8 log_max_rqt[0x5]; 975 u8 reserved_at_390[0x3]; 976 u8 log_max_rqt_size[0x5]; 977 u8 reserved_at_398[0x3]; 978 u8 log_max_tis_per_sq[0x5]; 979 980 u8 reserved_at_3a0[0x3]; 981 u8 log_max_stride_sz_rq[0x5]; 982 u8 reserved_at_3a8[0x3]; 983 u8 log_min_stride_sz_rq[0x5]; 984 u8 reserved_at_3b0[0x3]; 985 u8 log_max_stride_sz_sq[0x5]; 986 u8 reserved_at_3b8[0x3]; 987 u8 log_min_stride_sz_sq[0x5]; 988 989 u8 reserved_at_3c0[0x1b]; 990 u8 log_max_wq_sz[0x5]; 991 992 u8 nic_vport_change_event[0x1]; 993 u8 reserved_at_3e1[0xa]; 994 u8 log_max_vlan_list[0x5]; 995 u8 reserved_at_3f0[0x3]; 996 u8 log_max_current_mc_list[0x5]; 997 u8 reserved_at_3f8[0x3]; 998 u8 log_max_current_uc_list[0x5]; 999 1000 u8 reserved_at_400[0x80]; 1001 1002 u8 reserved_at_480[0x3]; 1003 u8 log_max_l2_table[0x5]; 1004 u8 reserved_at_488[0x8]; 1005 u8 log_uar_page_sz[0x10]; 1006 1007 u8 reserved_at_4a0[0x20]; 1008 u8 device_frequency_mhz[0x20]; 1009 u8 device_frequency_khz[0x20]; 1010 1011 u8 reserved_at_500[0x20]; 1012 u8 num_of_uars_per_page[0x20]; 1013 u8 reserved_at_540[0x40]; 1014 1015 u8 reserved_at_580[0x3f]; 1016 u8 cqe_compression[0x1]; 1017 1018 u8 cqe_compression_timeout[0x10]; 1019 u8 cqe_compression_max_num[0x10]; 1020 1021 u8 reserved_at_5e0[0x10]; 1022 u8 tag_matching[0x1]; 1023 u8 rndv_offload_rc[0x1]; 1024 u8 rndv_offload_dc[0x1]; 1025 u8 log_tag_matching_list_sz[0x5]; 1026 u8 reserved_at_5f8[0x3]; 1027 u8 log_max_xrq[0x5]; 1028 1029 u8 reserved_at_600[0x200]; 1030 }; 1031 1032 enum mlx5_flow_destination_type { 1033 MLX5_FLOW_DESTINATION_TYPE_VPORT = 0x0, 1034 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1, 1035 MLX5_FLOW_DESTINATION_TYPE_TIR = 0x2, 1036 1037 MLX5_FLOW_DESTINATION_TYPE_COUNTER = 0x100, 1038 }; 1039 1040 struct mlx5_ifc_dest_format_struct_bits { 1041 u8 destination_type[0x8]; 1042 u8 destination_id[0x18]; 1043 1044 u8 reserved_at_20[0x20]; 1045 }; 1046 1047 struct mlx5_ifc_flow_counter_list_bits { 1048 u8 clear[0x1]; 1049 u8 num_of_counters[0xf]; 1050 u8 flow_counter_id[0x10]; 1051 1052 u8 reserved_at_20[0x20]; 1053 }; 1054 1055 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits { 1056 struct mlx5_ifc_dest_format_struct_bits dest_format_struct; 1057 struct mlx5_ifc_flow_counter_list_bits flow_counter_list; 1058 u8 reserved_at_0[0x40]; 1059 }; 1060 1061 struct mlx5_ifc_fte_match_param_bits { 1062 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers; 1063 1064 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters; 1065 1066 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers; 1067 1068 u8 reserved_at_600[0xa00]; 1069 }; 1070 1071 enum { 1072 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0, 1073 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1, 1074 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2, 1075 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3, 1076 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4, 1077 }; 1078 1079 struct mlx5_ifc_rx_hash_field_select_bits { 1080 u8 l3_prot_type[0x1]; 1081 u8 l4_prot_type[0x1]; 1082 u8 selected_fields[0x1e]; 1083 }; 1084 1085 enum { 1086 MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0, 1087 MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1, 1088 }; 1089 1090 enum { 1091 MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0, 1092 MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1, 1093 }; 1094 1095 struct mlx5_ifc_wq_bits { 1096 u8 wq_type[0x4]; 1097 u8 wq_signature[0x1]; 1098 u8 end_padding_mode[0x2]; 1099 u8 cd_slave[0x1]; 1100 u8 reserved_at_8[0x18]; 1101 1102 u8 hds_skip_first_sge[0x1]; 1103 u8 log2_hds_buf_size[0x3]; 1104 u8 reserved_at_24[0x7]; 1105 u8 page_offset[0x5]; 1106 u8 lwm[0x10]; 1107 1108 u8 reserved_at_40[0x8]; 1109 u8 pd[0x18]; 1110 1111 u8 reserved_at_60[0x8]; 1112 u8 uar_page[0x18]; 1113 1114 u8 dbr_addr[0x40]; 1115 1116 u8 hw_counter[0x20]; 1117 1118 u8 sw_counter[0x20]; 1119 1120 u8 reserved_at_100[0xc]; 1121 u8 log_wq_stride[0x4]; 1122 u8 reserved_at_110[0x3]; 1123 u8 log_wq_pg_sz[0x5]; 1124 u8 reserved_at_118[0x3]; 1125 u8 log_wq_sz[0x5]; 1126 1127 u8 reserved_at_120[0x15]; 1128 u8 log_wqe_num_of_strides[0x3]; 1129 u8 two_byte_shift_en[0x1]; 1130 u8 reserved_at_139[0x4]; 1131 u8 log_wqe_stride_size[0x3]; 1132 1133 u8 reserved_at_140[0x4c0]; 1134 1135 struct mlx5_ifc_cmd_pas_bits pas[0]; 1136 }; 1137 1138 struct mlx5_ifc_rq_num_bits { 1139 u8 reserved_at_0[0x8]; 1140 u8 rq_num[0x18]; 1141 }; 1142 1143 struct mlx5_ifc_mac_address_layout_bits { 1144 u8 reserved_at_0[0x10]; 1145 u8 mac_addr_47_32[0x10]; 1146 1147 u8 mac_addr_31_0[0x20]; 1148 }; 1149 1150 struct mlx5_ifc_vlan_layout_bits { 1151 u8 reserved_at_0[0x14]; 1152 u8 vlan[0x0c]; 1153 1154 u8 reserved_at_20[0x20]; 1155 }; 1156 1157 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits { 1158 u8 reserved_at_0[0xa0]; 1159 1160 u8 min_time_between_cnps[0x20]; 1161 1162 u8 reserved_at_c0[0x12]; 1163 u8 cnp_dscp[0x6]; 1164 u8 reserved_at_d8[0x5]; 1165 u8 cnp_802p_prio[0x3]; 1166 1167 u8 reserved_at_e0[0x720]; 1168 }; 1169 1170 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits { 1171 u8 reserved_at_0[0x60]; 1172 1173 u8 reserved_at_60[0x4]; 1174 u8 clamp_tgt_rate[0x1]; 1175 u8 reserved_at_65[0x3]; 1176 u8 clamp_tgt_rate_after_time_inc[0x1]; 1177 u8 reserved_at_69[0x17]; 1178 1179 u8 reserved_at_80[0x20]; 1180 1181 u8 rpg_time_reset[0x20]; 1182 1183 u8 rpg_byte_reset[0x20]; 1184 1185 u8 rpg_threshold[0x20]; 1186 1187 u8 rpg_max_rate[0x20]; 1188 1189 u8 rpg_ai_rate[0x20]; 1190 1191 u8 rpg_hai_rate[0x20]; 1192 1193 u8 rpg_gd[0x20]; 1194 1195 u8 rpg_min_dec_fac[0x20]; 1196 1197 u8 rpg_min_rate[0x20]; 1198 1199 u8 reserved_at_1c0[0xe0]; 1200 1201 u8 rate_to_set_on_first_cnp[0x20]; 1202 1203 u8 dce_tcp_g[0x20]; 1204 1205 u8 dce_tcp_rtt[0x20]; 1206 1207 u8 rate_reduce_monitor_period[0x20]; 1208 1209 u8 reserved_at_320[0x20]; 1210 1211 u8 initial_alpha_value[0x20]; 1212 1213 u8 reserved_at_360[0x4a0]; 1214 }; 1215 1216 struct mlx5_ifc_cong_control_802_1qau_rp_bits { 1217 u8 reserved_at_0[0x80]; 1218 1219 u8 rppp_max_rps[0x20]; 1220 1221 u8 rpg_time_reset[0x20]; 1222 1223 u8 rpg_byte_reset[0x20]; 1224 1225 u8 rpg_threshold[0x20]; 1226 1227 u8 rpg_max_rate[0x20]; 1228 1229 u8 rpg_ai_rate[0x20]; 1230 1231 u8 rpg_hai_rate[0x20]; 1232 1233 u8 rpg_gd[0x20]; 1234 1235 u8 rpg_min_dec_fac[0x20]; 1236 1237 u8 rpg_min_rate[0x20]; 1238 1239 u8 reserved_at_1c0[0x640]; 1240 }; 1241 1242 enum { 1243 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1, 1244 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2, 1245 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4, 1246 }; 1247 1248 struct mlx5_ifc_resize_field_select_bits { 1249 u8 resize_field_select[0x20]; 1250 }; 1251 1252 enum { 1253 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1, 1254 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2, 1255 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4, 1256 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8, 1257 }; 1258 1259 struct mlx5_ifc_modify_field_select_bits { 1260 u8 modify_field_select[0x20]; 1261 }; 1262 1263 struct mlx5_ifc_field_select_r_roce_np_bits { 1264 u8 field_select_r_roce_np[0x20]; 1265 }; 1266 1267 struct mlx5_ifc_field_select_r_roce_rp_bits { 1268 u8 field_select_r_roce_rp[0x20]; 1269 }; 1270 1271 enum { 1272 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4, 1273 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8, 1274 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10, 1275 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20, 1276 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40, 1277 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80, 1278 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100, 1279 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200, 1280 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400, 1281 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800, 1282 }; 1283 1284 struct mlx5_ifc_field_select_802_1qau_rp_bits { 1285 u8 field_select_8021qaurp[0x20]; 1286 }; 1287 1288 struct mlx5_ifc_phys_layer_cntrs_bits { 1289 u8 time_since_last_clear_high[0x20]; 1290 1291 u8 time_since_last_clear_low[0x20]; 1292 1293 u8 symbol_errors_high[0x20]; 1294 1295 u8 symbol_errors_low[0x20]; 1296 1297 u8 sync_headers_errors_high[0x20]; 1298 1299 u8 sync_headers_errors_low[0x20]; 1300 1301 u8 edpl_bip_errors_lane0_high[0x20]; 1302 1303 u8 edpl_bip_errors_lane0_low[0x20]; 1304 1305 u8 edpl_bip_errors_lane1_high[0x20]; 1306 1307 u8 edpl_bip_errors_lane1_low[0x20]; 1308 1309 u8 edpl_bip_errors_lane2_high[0x20]; 1310 1311 u8 edpl_bip_errors_lane2_low[0x20]; 1312 1313 u8 edpl_bip_errors_lane3_high[0x20]; 1314 1315 u8 edpl_bip_errors_lane3_low[0x20]; 1316 1317 u8 fc_fec_corrected_blocks_lane0_high[0x20]; 1318 1319 u8 fc_fec_corrected_blocks_lane0_low[0x20]; 1320 1321 u8 fc_fec_corrected_blocks_lane1_high[0x20]; 1322 1323 u8 fc_fec_corrected_blocks_lane1_low[0x20]; 1324 1325 u8 fc_fec_corrected_blocks_lane2_high[0x20]; 1326 1327 u8 fc_fec_corrected_blocks_lane2_low[0x20]; 1328 1329 u8 fc_fec_corrected_blocks_lane3_high[0x20]; 1330 1331 u8 fc_fec_corrected_blocks_lane3_low[0x20]; 1332 1333 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20]; 1334 1335 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20]; 1336 1337 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20]; 1338 1339 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20]; 1340 1341 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20]; 1342 1343 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20]; 1344 1345 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20]; 1346 1347 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20]; 1348 1349 u8 rs_fec_corrected_blocks_high[0x20]; 1350 1351 u8 rs_fec_corrected_blocks_low[0x20]; 1352 1353 u8 rs_fec_uncorrectable_blocks_high[0x20]; 1354 1355 u8 rs_fec_uncorrectable_blocks_low[0x20]; 1356 1357 u8 rs_fec_no_errors_blocks_high[0x20]; 1358 1359 u8 rs_fec_no_errors_blocks_low[0x20]; 1360 1361 u8 rs_fec_single_error_blocks_high[0x20]; 1362 1363 u8 rs_fec_single_error_blocks_low[0x20]; 1364 1365 u8 rs_fec_corrected_symbols_total_high[0x20]; 1366 1367 u8 rs_fec_corrected_symbols_total_low[0x20]; 1368 1369 u8 rs_fec_corrected_symbols_lane0_high[0x20]; 1370 1371 u8 rs_fec_corrected_symbols_lane0_low[0x20]; 1372 1373 u8 rs_fec_corrected_symbols_lane1_high[0x20]; 1374 1375 u8 rs_fec_corrected_symbols_lane1_low[0x20]; 1376 1377 u8 rs_fec_corrected_symbols_lane2_high[0x20]; 1378 1379 u8 rs_fec_corrected_symbols_lane2_low[0x20]; 1380 1381 u8 rs_fec_corrected_symbols_lane3_high[0x20]; 1382 1383 u8 rs_fec_corrected_symbols_lane3_low[0x20]; 1384 1385 u8 link_down_events[0x20]; 1386 1387 u8 successful_recovery_events[0x20]; 1388 1389 u8 reserved_at_640[0x180]; 1390 }; 1391 1392 struct mlx5_ifc_phys_layer_statistical_cntrs_bits { 1393 u8 time_since_last_clear_high[0x20]; 1394 1395 u8 time_since_last_clear_low[0x20]; 1396 1397 u8 phy_received_bits_high[0x20]; 1398 1399 u8 phy_received_bits_low[0x20]; 1400 1401 u8 phy_symbol_errors_high[0x20]; 1402 1403 u8 phy_symbol_errors_low[0x20]; 1404 1405 u8 phy_corrected_bits_high[0x20]; 1406 1407 u8 phy_corrected_bits_low[0x20]; 1408 1409 u8 phy_corrected_bits_lane0_high[0x20]; 1410 1411 u8 phy_corrected_bits_lane0_low[0x20]; 1412 1413 u8 phy_corrected_bits_lane1_high[0x20]; 1414 1415 u8 phy_corrected_bits_lane1_low[0x20]; 1416 1417 u8 phy_corrected_bits_lane2_high[0x20]; 1418 1419 u8 phy_corrected_bits_lane2_low[0x20]; 1420 1421 u8 phy_corrected_bits_lane3_high[0x20]; 1422 1423 u8 phy_corrected_bits_lane3_low[0x20]; 1424 1425 u8 reserved_at_200[0x5c0]; 1426 }; 1427 1428 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits { 1429 u8 symbol_error_counter[0x10]; 1430 1431 u8 link_error_recovery_counter[0x8]; 1432 1433 u8 link_downed_counter[0x8]; 1434 1435 u8 port_rcv_errors[0x10]; 1436 1437 u8 port_rcv_remote_physical_errors[0x10]; 1438 1439 u8 port_rcv_switch_relay_errors[0x10]; 1440 1441 u8 port_xmit_discards[0x10]; 1442 1443 u8 port_xmit_constraint_errors[0x8]; 1444 1445 u8 port_rcv_constraint_errors[0x8]; 1446 1447 u8 reserved_at_70[0x8]; 1448 1449 u8 link_overrun_errors[0x8]; 1450 1451 u8 reserved_at_80[0x10]; 1452 1453 u8 vl_15_dropped[0x10]; 1454 1455 u8 reserved_at_a0[0xa0]; 1456 }; 1457 1458 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits { 1459 u8 transmit_queue_high[0x20]; 1460 1461 u8 transmit_queue_low[0x20]; 1462 1463 u8 reserved_at_40[0x780]; 1464 }; 1465 1466 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits { 1467 u8 rx_octets_high[0x20]; 1468 1469 u8 rx_octets_low[0x20]; 1470 1471 u8 reserved_at_40[0xc0]; 1472 1473 u8 rx_frames_high[0x20]; 1474 1475 u8 rx_frames_low[0x20]; 1476 1477 u8 tx_octets_high[0x20]; 1478 1479 u8 tx_octets_low[0x20]; 1480 1481 u8 reserved_at_180[0xc0]; 1482 1483 u8 tx_frames_high[0x20]; 1484 1485 u8 tx_frames_low[0x20]; 1486 1487 u8 rx_pause_high[0x20]; 1488 1489 u8 rx_pause_low[0x20]; 1490 1491 u8 rx_pause_duration_high[0x20]; 1492 1493 u8 rx_pause_duration_low[0x20]; 1494 1495 u8 tx_pause_high[0x20]; 1496 1497 u8 tx_pause_low[0x20]; 1498 1499 u8 tx_pause_duration_high[0x20]; 1500 1501 u8 tx_pause_duration_low[0x20]; 1502 1503 u8 rx_pause_transition_high[0x20]; 1504 1505 u8 rx_pause_transition_low[0x20]; 1506 1507 u8 reserved_at_3c0[0x400]; 1508 }; 1509 1510 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits { 1511 u8 port_transmit_wait_high[0x20]; 1512 1513 u8 port_transmit_wait_low[0x20]; 1514 1515 u8 reserved_at_40[0x780]; 1516 }; 1517 1518 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits { 1519 u8 dot3stats_alignment_errors_high[0x20]; 1520 1521 u8 dot3stats_alignment_errors_low[0x20]; 1522 1523 u8 dot3stats_fcs_errors_high[0x20]; 1524 1525 u8 dot3stats_fcs_errors_low[0x20]; 1526 1527 u8 dot3stats_single_collision_frames_high[0x20]; 1528 1529 u8 dot3stats_single_collision_frames_low[0x20]; 1530 1531 u8 dot3stats_multiple_collision_frames_high[0x20]; 1532 1533 u8 dot3stats_multiple_collision_frames_low[0x20]; 1534 1535 u8 dot3stats_sqe_test_errors_high[0x20]; 1536 1537 u8 dot3stats_sqe_test_errors_low[0x20]; 1538 1539 u8 dot3stats_deferred_transmissions_high[0x20]; 1540 1541 u8 dot3stats_deferred_transmissions_low[0x20]; 1542 1543 u8 dot3stats_late_collisions_high[0x20]; 1544 1545 u8 dot3stats_late_collisions_low[0x20]; 1546 1547 u8 dot3stats_excessive_collisions_high[0x20]; 1548 1549 u8 dot3stats_excessive_collisions_low[0x20]; 1550 1551 u8 dot3stats_internal_mac_transmit_errors_high[0x20]; 1552 1553 u8 dot3stats_internal_mac_transmit_errors_low[0x20]; 1554 1555 u8 dot3stats_carrier_sense_errors_high[0x20]; 1556 1557 u8 dot3stats_carrier_sense_errors_low[0x20]; 1558 1559 u8 dot3stats_frame_too_longs_high[0x20]; 1560 1561 u8 dot3stats_frame_too_longs_low[0x20]; 1562 1563 u8 dot3stats_internal_mac_receive_errors_high[0x20]; 1564 1565 u8 dot3stats_internal_mac_receive_errors_low[0x20]; 1566 1567 u8 dot3stats_symbol_errors_high[0x20]; 1568 1569 u8 dot3stats_symbol_errors_low[0x20]; 1570 1571 u8 dot3control_in_unknown_opcodes_high[0x20]; 1572 1573 u8 dot3control_in_unknown_opcodes_low[0x20]; 1574 1575 u8 dot3in_pause_frames_high[0x20]; 1576 1577 u8 dot3in_pause_frames_low[0x20]; 1578 1579 u8 dot3out_pause_frames_high[0x20]; 1580 1581 u8 dot3out_pause_frames_low[0x20]; 1582 1583 u8 reserved_at_400[0x3c0]; 1584 }; 1585 1586 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits { 1587 u8 ether_stats_drop_events_high[0x20]; 1588 1589 u8 ether_stats_drop_events_low[0x20]; 1590 1591 u8 ether_stats_octets_high[0x20]; 1592 1593 u8 ether_stats_octets_low[0x20]; 1594 1595 u8 ether_stats_pkts_high[0x20]; 1596 1597 u8 ether_stats_pkts_low[0x20]; 1598 1599 u8 ether_stats_broadcast_pkts_high[0x20]; 1600 1601 u8 ether_stats_broadcast_pkts_low[0x20]; 1602 1603 u8 ether_stats_multicast_pkts_high[0x20]; 1604 1605 u8 ether_stats_multicast_pkts_low[0x20]; 1606 1607 u8 ether_stats_crc_align_errors_high[0x20]; 1608 1609 u8 ether_stats_crc_align_errors_low[0x20]; 1610 1611 u8 ether_stats_undersize_pkts_high[0x20]; 1612 1613 u8 ether_stats_undersize_pkts_low[0x20]; 1614 1615 u8 ether_stats_oversize_pkts_high[0x20]; 1616 1617 u8 ether_stats_oversize_pkts_low[0x20]; 1618 1619 u8 ether_stats_fragments_high[0x20]; 1620 1621 u8 ether_stats_fragments_low[0x20]; 1622 1623 u8 ether_stats_jabbers_high[0x20]; 1624 1625 u8 ether_stats_jabbers_low[0x20]; 1626 1627 u8 ether_stats_collisions_high[0x20]; 1628 1629 u8 ether_stats_collisions_low[0x20]; 1630 1631 u8 ether_stats_pkts64octets_high[0x20]; 1632 1633 u8 ether_stats_pkts64octets_low[0x20]; 1634 1635 u8 ether_stats_pkts65to127octets_high[0x20]; 1636 1637 u8 ether_stats_pkts65to127octets_low[0x20]; 1638 1639 u8 ether_stats_pkts128to255octets_high[0x20]; 1640 1641 u8 ether_stats_pkts128to255octets_low[0x20]; 1642 1643 u8 ether_stats_pkts256to511octets_high[0x20]; 1644 1645 u8 ether_stats_pkts256to511octets_low[0x20]; 1646 1647 u8 ether_stats_pkts512to1023octets_high[0x20]; 1648 1649 u8 ether_stats_pkts512to1023octets_low[0x20]; 1650 1651 u8 ether_stats_pkts1024to1518octets_high[0x20]; 1652 1653 u8 ether_stats_pkts1024to1518octets_low[0x20]; 1654 1655 u8 ether_stats_pkts1519to2047octets_high[0x20]; 1656 1657 u8 ether_stats_pkts1519to2047octets_low[0x20]; 1658 1659 u8 ether_stats_pkts2048to4095octets_high[0x20]; 1660 1661 u8 ether_stats_pkts2048to4095octets_low[0x20]; 1662 1663 u8 ether_stats_pkts4096to8191octets_high[0x20]; 1664 1665 u8 ether_stats_pkts4096to8191octets_low[0x20]; 1666 1667 u8 ether_stats_pkts8192to10239octets_high[0x20]; 1668 1669 u8 ether_stats_pkts8192to10239octets_low[0x20]; 1670 1671 u8 reserved_at_540[0x280]; 1672 }; 1673 1674 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits { 1675 u8 if_in_octets_high[0x20]; 1676 1677 u8 if_in_octets_low[0x20]; 1678 1679 u8 if_in_ucast_pkts_high[0x20]; 1680 1681 u8 if_in_ucast_pkts_low[0x20]; 1682 1683 u8 if_in_discards_high[0x20]; 1684 1685 u8 if_in_discards_low[0x20]; 1686 1687 u8 if_in_errors_high[0x20]; 1688 1689 u8 if_in_errors_low[0x20]; 1690 1691 u8 if_in_unknown_protos_high[0x20]; 1692 1693 u8 if_in_unknown_protos_low[0x20]; 1694 1695 u8 if_out_octets_high[0x20]; 1696 1697 u8 if_out_octets_low[0x20]; 1698 1699 u8 if_out_ucast_pkts_high[0x20]; 1700 1701 u8 if_out_ucast_pkts_low[0x20]; 1702 1703 u8 if_out_discards_high[0x20]; 1704 1705 u8 if_out_discards_low[0x20]; 1706 1707 u8 if_out_errors_high[0x20]; 1708 1709 u8 if_out_errors_low[0x20]; 1710 1711 u8 if_in_multicast_pkts_high[0x20]; 1712 1713 u8 if_in_multicast_pkts_low[0x20]; 1714 1715 u8 if_in_broadcast_pkts_high[0x20]; 1716 1717 u8 if_in_broadcast_pkts_low[0x20]; 1718 1719 u8 if_out_multicast_pkts_high[0x20]; 1720 1721 u8 if_out_multicast_pkts_low[0x20]; 1722 1723 u8 if_out_broadcast_pkts_high[0x20]; 1724 1725 u8 if_out_broadcast_pkts_low[0x20]; 1726 1727 u8 reserved_at_340[0x480]; 1728 }; 1729 1730 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits { 1731 u8 a_frames_transmitted_ok_high[0x20]; 1732 1733 u8 a_frames_transmitted_ok_low[0x20]; 1734 1735 u8 a_frames_received_ok_high[0x20]; 1736 1737 u8 a_frames_received_ok_low[0x20]; 1738 1739 u8 a_frame_check_sequence_errors_high[0x20]; 1740 1741 u8 a_frame_check_sequence_errors_low[0x20]; 1742 1743 u8 a_alignment_errors_high[0x20]; 1744 1745 u8 a_alignment_errors_low[0x20]; 1746 1747 u8 a_octets_transmitted_ok_high[0x20]; 1748 1749 u8 a_octets_transmitted_ok_low[0x20]; 1750 1751 u8 a_octets_received_ok_high[0x20]; 1752 1753 u8 a_octets_received_ok_low[0x20]; 1754 1755 u8 a_multicast_frames_xmitted_ok_high[0x20]; 1756 1757 u8 a_multicast_frames_xmitted_ok_low[0x20]; 1758 1759 u8 a_broadcast_frames_xmitted_ok_high[0x20]; 1760 1761 u8 a_broadcast_frames_xmitted_ok_low[0x20]; 1762 1763 u8 a_multicast_frames_received_ok_high[0x20]; 1764 1765 u8 a_multicast_frames_received_ok_low[0x20]; 1766 1767 u8 a_broadcast_frames_received_ok_high[0x20]; 1768 1769 u8 a_broadcast_frames_received_ok_low[0x20]; 1770 1771 u8 a_in_range_length_errors_high[0x20]; 1772 1773 u8 a_in_range_length_errors_low[0x20]; 1774 1775 u8 a_out_of_range_length_field_high[0x20]; 1776 1777 u8 a_out_of_range_length_field_low[0x20]; 1778 1779 u8 a_frame_too_long_errors_high[0x20]; 1780 1781 u8 a_frame_too_long_errors_low[0x20]; 1782 1783 u8 a_symbol_error_during_carrier_high[0x20]; 1784 1785 u8 a_symbol_error_during_carrier_low[0x20]; 1786 1787 u8 a_mac_control_frames_transmitted_high[0x20]; 1788 1789 u8 a_mac_control_frames_transmitted_low[0x20]; 1790 1791 u8 a_mac_control_frames_received_high[0x20]; 1792 1793 u8 a_mac_control_frames_received_low[0x20]; 1794 1795 u8 a_unsupported_opcodes_received_high[0x20]; 1796 1797 u8 a_unsupported_opcodes_received_low[0x20]; 1798 1799 u8 a_pause_mac_ctrl_frames_received_high[0x20]; 1800 1801 u8 a_pause_mac_ctrl_frames_received_low[0x20]; 1802 1803 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20]; 1804 1805 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20]; 1806 1807 u8 reserved_at_4c0[0x300]; 1808 }; 1809 1810 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits { 1811 u8 life_time_counter_high[0x20]; 1812 1813 u8 life_time_counter_low[0x20]; 1814 1815 u8 rx_errors[0x20]; 1816 1817 u8 tx_errors[0x20]; 1818 1819 u8 l0_to_recovery_eieos[0x20]; 1820 1821 u8 l0_to_recovery_ts[0x20]; 1822 1823 u8 l0_to_recovery_framing[0x20]; 1824 1825 u8 l0_to_recovery_retrain[0x20]; 1826 1827 u8 crc_error_dllp[0x20]; 1828 1829 u8 crc_error_tlp[0x20]; 1830 1831 u8 reserved_at_140[0x680]; 1832 }; 1833 1834 struct mlx5_ifc_cmd_inter_comp_event_bits { 1835 u8 command_completion_vector[0x20]; 1836 1837 u8 reserved_at_20[0xc0]; 1838 }; 1839 1840 struct mlx5_ifc_stall_vl_event_bits { 1841 u8 reserved_at_0[0x18]; 1842 u8 port_num[0x1]; 1843 u8 reserved_at_19[0x3]; 1844 u8 vl[0x4]; 1845 1846 u8 reserved_at_20[0xa0]; 1847 }; 1848 1849 struct mlx5_ifc_db_bf_congestion_event_bits { 1850 u8 event_subtype[0x8]; 1851 u8 reserved_at_8[0x8]; 1852 u8 congestion_level[0x8]; 1853 u8 reserved_at_18[0x8]; 1854 1855 u8 reserved_at_20[0xa0]; 1856 }; 1857 1858 struct mlx5_ifc_gpio_event_bits { 1859 u8 reserved_at_0[0x60]; 1860 1861 u8 gpio_event_hi[0x20]; 1862 1863 u8 gpio_event_lo[0x20]; 1864 1865 u8 reserved_at_a0[0x40]; 1866 }; 1867 1868 struct mlx5_ifc_port_state_change_event_bits { 1869 u8 reserved_at_0[0x40]; 1870 1871 u8 port_num[0x4]; 1872 u8 reserved_at_44[0x1c]; 1873 1874 u8 reserved_at_60[0x80]; 1875 }; 1876 1877 struct mlx5_ifc_dropped_packet_logged_bits { 1878 u8 reserved_at_0[0xe0]; 1879 }; 1880 1881 enum { 1882 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1, 1883 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2, 1884 }; 1885 1886 struct mlx5_ifc_cq_error_bits { 1887 u8 reserved_at_0[0x8]; 1888 u8 cqn[0x18]; 1889 1890 u8 reserved_at_20[0x20]; 1891 1892 u8 reserved_at_40[0x18]; 1893 u8 syndrome[0x8]; 1894 1895 u8 reserved_at_60[0x80]; 1896 }; 1897 1898 struct mlx5_ifc_rdma_page_fault_event_bits { 1899 u8 bytes_committed[0x20]; 1900 1901 u8 r_key[0x20]; 1902 1903 u8 reserved_at_40[0x10]; 1904 u8 packet_len[0x10]; 1905 1906 u8 rdma_op_len[0x20]; 1907 1908 u8 rdma_va[0x40]; 1909 1910 u8 reserved_at_c0[0x5]; 1911 u8 rdma[0x1]; 1912 u8 write[0x1]; 1913 u8 requestor[0x1]; 1914 u8 qp_number[0x18]; 1915 }; 1916 1917 struct mlx5_ifc_wqe_associated_page_fault_event_bits { 1918 u8 bytes_committed[0x20]; 1919 1920 u8 reserved_at_20[0x10]; 1921 u8 wqe_index[0x10]; 1922 1923 u8 reserved_at_40[0x10]; 1924 u8 len[0x10]; 1925 1926 u8 reserved_at_60[0x60]; 1927 1928 u8 reserved_at_c0[0x5]; 1929 u8 rdma[0x1]; 1930 u8 write_read[0x1]; 1931 u8 requestor[0x1]; 1932 u8 qpn[0x18]; 1933 }; 1934 1935 struct mlx5_ifc_qp_events_bits { 1936 u8 reserved_at_0[0xa0]; 1937 1938 u8 type[0x8]; 1939 u8 reserved_at_a8[0x18]; 1940 1941 u8 reserved_at_c0[0x8]; 1942 u8 qpn_rqn_sqn[0x18]; 1943 }; 1944 1945 struct mlx5_ifc_dct_events_bits { 1946 u8 reserved_at_0[0xc0]; 1947 1948 u8 reserved_at_c0[0x8]; 1949 u8 dct_number[0x18]; 1950 }; 1951 1952 struct mlx5_ifc_comp_event_bits { 1953 u8 reserved_at_0[0xc0]; 1954 1955 u8 reserved_at_c0[0x8]; 1956 u8 cq_number[0x18]; 1957 }; 1958 1959 enum { 1960 MLX5_QPC_STATE_RST = 0x0, 1961 MLX5_QPC_STATE_INIT = 0x1, 1962 MLX5_QPC_STATE_RTR = 0x2, 1963 MLX5_QPC_STATE_RTS = 0x3, 1964 MLX5_QPC_STATE_SQER = 0x4, 1965 MLX5_QPC_STATE_ERR = 0x6, 1966 MLX5_QPC_STATE_SQD = 0x7, 1967 MLX5_QPC_STATE_SUSPENDED = 0x9, 1968 }; 1969 1970 enum { 1971 MLX5_QPC_ST_RC = 0x0, 1972 MLX5_QPC_ST_UC = 0x1, 1973 MLX5_QPC_ST_UD = 0x2, 1974 MLX5_QPC_ST_XRC = 0x3, 1975 MLX5_QPC_ST_DCI = 0x5, 1976 MLX5_QPC_ST_QP0 = 0x7, 1977 MLX5_QPC_ST_QP1 = 0x8, 1978 MLX5_QPC_ST_RAW_DATAGRAM = 0x9, 1979 MLX5_QPC_ST_REG_UMR = 0xc, 1980 }; 1981 1982 enum { 1983 MLX5_QPC_PM_STATE_ARMED = 0x0, 1984 MLX5_QPC_PM_STATE_REARM = 0x1, 1985 MLX5_QPC_PM_STATE_RESERVED = 0x2, 1986 MLX5_QPC_PM_STATE_MIGRATED = 0x3, 1987 }; 1988 1989 enum { 1990 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0, 1991 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1, 1992 }; 1993 1994 enum { 1995 MLX5_QPC_MTU_256_BYTES = 0x1, 1996 MLX5_QPC_MTU_512_BYTES = 0x2, 1997 MLX5_QPC_MTU_1K_BYTES = 0x3, 1998 MLX5_QPC_MTU_2K_BYTES = 0x4, 1999 MLX5_QPC_MTU_4K_BYTES = 0x5, 2000 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7, 2001 }; 2002 2003 enum { 2004 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1, 2005 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2, 2006 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3, 2007 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4, 2008 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5, 2009 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6, 2010 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7, 2011 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8, 2012 }; 2013 2014 enum { 2015 MLX5_QPC_CS_REQ_DISABLE = 0x0, 2016 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11, 2017 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22, 2018 }; 2019 2020 enum { 2021 MLX5_QPC_CS_RES_DISABLE = 0x0, 2022 MLX5_QPC_CS_RES_UP_TO_32B = 0x1, 2023 MLX5_QPC_CS_RES_UP_TO_64B = 0x2, 2024 }; 2025 2026 struct mlx5_ifc_qpc_bits { 2027 u8 state[0x4]; 2028 u8 lag_tx_port_affinity[0x4]; 2029 u8 st[0x8]; 2030 u8 reserved_at_10[0x3]; 2031 u8 pm_state[0x2]; 2032 u8 reserved_at_15[0x7]; 2033 u8 end_padding_mode[0x2]; 2034 u8 reserved_at_1e[0x2]; 2035 2036 u8 wq_signature[0x1]; 2037 u8 block_lb_mc[0x1]; 2038 u8 atomic_like_write_en[0x1]; 2039 u8 latency_sensitive[0x1]; 2040 u8 reserved_at_24[0x1]; 2041 u8 drain_sigerr[0x1]; 2042 u8 reserved_at_26[0x2]; 2043 u8 pd[0x18]; 2044 2045 u8 mtu[0x3]; 2046 u8 log_msg_max[0x5]; 2047 u8 reserved_at_48[0x1]; 2048 u8 log_rq_size[0x4]; 2049 u8 log_rq_stride[0x3]; 2050 u8 no_sq[0x1]; 2051 u8 log_sq_size[0x4]; 2052 u8 reserved_at_55[0x6]; 2053 u8 rlky[0x1]; 2054 u8 ulp_stateless_offload_mode[0x4]; 2055 2056 u8 counter_set_id[0x8]; 2057 u8 uar_page[0x18]; 2058 2059 u8 reserved_at_80[0x8]; 2060 u8 user_index[0x18]; 2061 2062 u8 reserved_at_a0[0x3]; 2063 u8 log_page_size[0x5]; 2064 u8 remote_qpn[0x18]; 2065 2066 struct mlx5_ifc_ads_bits primary_address_path; 2067 2068 struct mlx5_ifc_ads_bits secondary_address_path; 2069 2070 u8 log_ack_req_freq[0x4]; 2071 u8 reserved_at_384[0x4]; 2072 u8 log_sra_max[0x3]; 2073 u8 reserved_at_38b[0x2]; 2074 u8 retry_count[0x3]; 2075 u8 rnr_retry[0x3]; 2076 u8 reserved_at_393[0x1]; 2077 u8 fre[0x1]; 2078 u8 cur_rnr_retry[0x3]; 2079 u8 cur_retry_count[0x3]; 2080 u8 reserved_at_39b[0x5]; 2081 2082 u8 reserved_at_3a0[0x20]; 2083 2084 u8 reserved_at_3c0[0x8]; 2085 u8 next_send_psn[0x18]; 2086 2087 u8 reserved_at_3e0[0x8]; 2088 u8 cqn_snd[0x18]; 2089 2090 u8 reserved_at_400[0x8]; 2091 u8 deth_sqpn[0x18]; 2092 2093 u8 reserved_at_420[0x20]; 2094 2095 u8 reserved_at_440[0x8]; 2096 u8 last_acked_psn[0x18]; 2097 2098 u8 reserved_at_460[0x8]; 2099 u8 ssn[0x18]; 2100 2101 u8 reserved_at_480[0x8]; 2102 u8 log_rra_max[0x3]; 2103 u8 reserved_at_48b[0x1]; 2104 u8 atomic_mode[0x4]; 2105 u8 rre[0x1]; 2106 u8 rwe[0x1]; 2107 u8 rae[0x1]; 2108 u8 reserved_at_493[0x1]; 2109 u8 page_offset[0x6]; 2110 u8 reserved_at_49a[0x3]; 2111 u8 cd_slave_receive[0x1]; 2112 u8 cd_slave_send[0x1]; 2113 u8 cd_master[0x1]; 2114 2115 u8 reserved_at_4a0[0x3]; 2116 u8 min_rnr_nak[0x5]; 2117 u8 next_rcv_psn[0x18]; 2118 2119 u8 reserved_at_4c0[0x8]; 2120 u8 xrcd[0x18]; 2121 2122 u8 reserved_at_4e0[0x8]; 2123 u8 cqn_rcv[0x18]; 2124 2125 u8 dbr_addr[0x40]; 2126 2127 u8 q_key[0x20]; 2128 2129 u8 reserved_at_560[0x5]; 2130 u8 rq_type[0x3]; 2131 u8 srqn_rmpn_xrqn[0x18]; 2132 2133 u8 reserved_at_580[0x8]; 2134 u8 rmsn[0x18]; 2135 2136 u8 hw_sq_wqebb_counter[0x10]; 2137 u8 sw_sq_wqebb_counter[0x10]; 2138 2139 u8 hw_rq_counter[0x20]; 2140 2141 u8 sw_rq_counter[0x20]; 2142 2143 u8 reserved_at_600[0x20]; 2144 2145 u8 reserved_at_620[0xf]; 2146 u8 cgs[0x1]; 2147 u8 cs_req[0x8]; 2148 u8 cs_res[0x8]; 2149 2150 u8 dc_access_key[0x40]; 2151 2152 u8 reserved_at_680[0xc0]; 2153 }; 2154 2155 struct mlx5_ifc_roce_addr_layout_bits { 2156 u8 source_l3_address[16][0x8]; 2157 2158 u8 reserved_at_80[0x3]; 2159 u8 vlan_valid[0x1]; 2160 u8 vlan_id[0xc]; 2161 u8 source_mac_47_32[0x10]; 2162 2163 u8 source_mac_31_0[0x20]; 2164 2165 u8 reserved_at_c0[0x14]; 2166 u8 roce_l3_type[0x4]; 2167 u8 roce_version[0x8]; 2168 2169 u8 reserved_at_e0[0x20]; 2170 }; 2171 2172 union mlx5_ifc_hca_cap_union_bits { 2173 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap; 2174 struct mlx5_ifc_odp_cap_bits odp_cap; 2175 struct mlx5_ifc_atomic_caps_bits atomic_caps; 2176 struct mlx5_ifc_roce_cap_bits roce_cap; 2177 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps; 2178 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap; 2179 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap; 2180 struct mlx5_ifc_e_switch_cap_bits e_switch_cap; 2181 struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap; 2182 struct mlx5_ifc_qos_cap_bits qos_cap; 2183 u8 reserved_at_0[0x8000]; 2184 }; 2185 2186 enum { 2187 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1, 2188 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2, 2189 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4, 2190 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8, 2191 MLX5_FLOW_CONTEXT_ACTION_ENCAP = 0x10, 2192 MLX5_FLOW_CONTEXT_ACTION_DECAP = 0x20, 2193 }; 2194 2195 struct mlx5_ifc_flow_context_bits { 2196 u8 reserved_at_0[0x20]; 2197 2198 u8 group_id[0x20]; 2199 2200 u8 reserved_at_40[0x8]; 2201 u8 flow_tag[0x18]; 2202 2203 u8 reserved_at_60[0x10]; 2204 u8 action[0x10]; 2205 2206 u8 reserved_at_80[0x8]; 2207 u8 destination_list_size[0x18]; 2208 2209 u8 reserved_at_a0[0x8]; 2210 u8 flow_counter_list_size[0x18]; 2211 2212 u8 encap_id[0x20]; 2213 2214 u8 reserved_at_e0[0x120]; 2215 2216 struct mlx5_ifc_fte_match_param_bits match_value; 2217 2218 u8 reserved_at_1200[0x600]; 2219 2220 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[0]; 2221 }; 2222 2223 enum { 2224 MLX5_XRC_SRQC_STATE_GOOD = 0x0, 2225 MLX5_XRC_SRQC_STATE_ERROR = 0x1, 2226 }; 2227 2228 struct mlx5_ifc_xrc_srqc_bits { 2229 u8 state[0x4]; 2230 u8 log_xrc_srq_size[0x4]; 2231 u8 reserved_at_8[0x18]; 2232 2233 u8 wq_signature[0x1]; 2234 u8 cont_srq[0x1]; 2235 u8 reserved_at_22[0x1]; 2236 u8 rlky[0x1]; 2237 u8 basic_cyclic_rcv_wqe[0x1]; 2238 u8 log_rq_stride[0x3]; 2239 u8 xrcd[0x18]; 2240 2241 u8 page_offset[0x6]; 2242 u8 reserved_at_46[0x2]; 2243 u8 cqn[0x18]; 2244 2245 u8 reserved_at_60[0x20]; 2246 2247 u8 user_index_equal_xrc_srqn[0x1]; 2248 u8 reserved_at_81[0x1]; 2249 u8 log_page_size[0x6]; 2250 u8 user_index[0x18]; 2251 2252 u8 reserved_at_a0[0x20]; 2253 2254 u8 reserved_at_c0[0x8]; 2255 u8 pd[0x18]; 2256 2257 u8 lwm[0x10]; 2258 u8 wqe_cnt[0x10]; 2259 2260 u8 reserved_at_100[0x40]; 2261 2262 u8 db_record_addr_h[0x20]; 2263 2264 u8 db_record_addr_l[0x1e]; 2265 u8 reserved_at_17e[0x2]; 2266 2267 u8 reserved_at_180[0x80]; 2268 }; 2269 2270 struct mlx5_ifc_traffic_counter_bits { 2271 u8 packets[0x40]; 2272 2273 u8 octets[0x40]; 2274 }; 2275 2276 struct mlx5_ifc_tisc_bits { 2277 u8 strict_lag_tx_port_affinity[0x1]; 2278 u8 reserved_at_1[0x3]; 2279 u8 lag_tx_port_affinity[0x04]; 2280 2281 u8 reserved_at_8[0x4]; 2282 u8 prio[0x4]; 2283 u8 reserved_at_10[0x10]; 2284 2285 u8 reserved_at_20[0x100]; 2286 2287 u8 reserved_at_120[0x8]; 2288 u8 transport_domain[0x18]; 2289 2290 u8 reserved_at_140[0x3c0]; 2291 }; 2292 2293 enum { 2294 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0, 2295 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1, 2296 }; 2297 2298 enum { 2299 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO = 0x1, 2300 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO = 0x2, 2301 }; 2302 2303 enum { 2304 MLX5_RX_HASH_FN_NONE = 0x0, 2305 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1, 2306 MLX5_RX_HASH_FN_TOEPLITZ = 0x2, 2307 }; 2308 2309 enum { 2310 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST_ = 0x1, 2311 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST_ = 0x2, 2312 }; 2313 2314 struct mlx5_ifc_tirc_bits { 2315 u8 reserved_at_0[0x20]; 2316 2317 u8 disp_type[0x4]; 2318 u8 reserved_at_24[0x1c]; 2319 2320 u8 reserved_at_40[0x40]; 2321 2322 u8 reserved_at_80[0x4]; 2323 u8 lro_timeout_period_usecs[0x10]; 2324 u8 lro_enable_mask[0x4]; 2325 u8 lro_max_ip_payload_size[0x8]; 2326 2327 u8 reserved_at_a0[0x40]; 2328 2329 u8 reserved_at_e0[0x8]; 2330 u8 inline_rqn[0x18]; 2331 2332 u8 rx_hash_symmetric[0x1]; 2333 u8 reserved_at_101[0x1]; 2334 u8 tunneled_offload_en[0x1]; 2335 u8 reserved_at_103[0x5]; 2336 u8 indirect_table[0x18]; 2337 2338 u8 rx_hash_fn[0x4]; 2339 u8 reserved_at_124[0x2]; 2340 u8 self_lb_block[0x2]; 2341 u8 transport_domain[0x18]; 2342 2343 u8 rx_hash_toeplitz_key[10][0x20]; 2344 2345 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer; 2346 2347 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner; 2348 2349 u8 reserved_at_2c0[0x4c0]; 2350 }; 2351 2352 enum { 2353 MLX5_SRQC_STATE_GOOD = 0x0, 2354 MLX5_SRQC_STATE_ERROR = 0x1, 2355 }; 2356 2357 struct mlx5_ifc_srqc_bits { 2358 u8 state[0x4]; 2359 u8 log_srq_size[0x4]; 2360 u8 reserved_at_8[0x18]; 2361 2362 u8 wq_signature[0x1]; 2363 u8 cont_srq[0x1]; 2364 u8 reserved_at_22[0x1]; 2365 u8 rlky[0x1]; 2366 u8 reserved_at_24[0x1]; 2367 u8 log_rq_stride[0x3]; 2368 u8 xrcd[0x18]; 2369 2370 u8 page_offset[0x6]; 2371 u8 reserved_at_46[0x2]; 2372 u8 cqn[0x18]; 2373 2374 u8 reserved_at_60[0x20]; 2375 2376 u8 reserved_at_80[0x2]; 2377 u8 log_page_size[0x6]; 2378 u8 reserved_at_88[0x18]; 2379 2380 u8 reserved_at_a0[0x20]; 2381 2382 u8 reserved_at_c0[0x8]; 2383 u8 pd[0x18]; 2384 2385 u8 lwm[0x10]; 2386 u8 wqe_cnt[0x10]; 2387 2388 u8 reserved_at_100[0x40]; 2389 2390 u8 dbr_addr[0x40]; 2391 2392 u8 reserved_at_180[0x80]; 2393 }; 2394 2395 enum { 2396 MLX5_SQC_STATE_RST = 0x0, 2397 MLX5_SQC_STATE_RDY = 0x1, 2398 MLX5_SQC_STATE_ERR = 0x3, 2399 }; 2400 2401 struct mlx5_ifc_sqc_bits { 2402 u8 rlky[0x1]; 2403 u8 cd_master[0x1]; 2404 u8 fre[0x1]; 2405 u8 flush_in_error_en[0x1]; 2406 u8 reserved_at_4[0x1]; 2407 u8 min_wqe_inline_mode[0x3]; 2408 u8 state[0x4]; 2409 u8 reg_umr[0x1]; 2410 u8 reserved_at_d[0x13]; 2411 2412 u8 reserved_at_20[0x8]; 2413 u8 user_index[0x18]; 2414 2415 u8 reserved_at_40[0x8]; 2416 u8 cqn[0x18]; 2417 2418 u8 reserved_at_60[0x90]; 2419 2420 u8 packet_pacing_rate_limit_index[0x10]; 2421 u8 tis_lst_sz[0x10]; 2422 u8 reserved_at_110[0x10]; 2423 2424 u8 reserved_at_120[0x40]; 2425 2426 u8 reserved_at_160[0x8]; 2427 u8 tis_num_0[0x18]; 2428 2429 struct mlx5_ifc_wq_bits wq; 2430 }; 2431 2432 enum { 2433 SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0, 2434 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1, 2435 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2, 2436 SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3, 2437 }; 2438 2439 struct mlx5_ifc_scheduling_context_bits { 2440 u8 element_type[0x8]; 2441 u8 reserved_at_8[0x18]; 2442 2443 u8 element_attributes[0x20]; 2444 2445 u8 parent_element_id[0x20]; 2446 2447 u8 reserved_at_60[0x40]; 2448 2449 u8 bw_share[0x20]; 2450 2451 u8 max_average_bw[0x20]; 2452 2453 u8 reserved_at_e0[0x120]; 2454 }; 2455 2456 struct mlx5_ifc_rqtc_bits { 2457 u8 reserved_at_0[0xa0]; 2458 2459 u8 reserved_at_a0[0x10]; 2460 u8 rqt_max_size[0x10]; 2461 2462 u8 reserved_at_c0[0x10]; 2463 u8 rqt_actual_size[0x10]; 2464 2465 u8 reserved_at_e0[0x6a0]; 2466 2467 struct mlx5_ifc_rq_num_bits rq_num[0]; 2468 }; 2469 2470 enum { 2471 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0, 2472 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1, 2473 }; 2474 2475 enum { 2476 MLX5_RQC_STATE_RST = 0x0, 2477 MLX5_RQC_STATE_RDY = 0x1, 2478 MLX5_RQC_STATE_ERR = 0x3, 2479 }; 2480 2481 struct mlx5_ifc_rqc_bits { 2482 u8 rlky[0x1]; 2483 u8 reserved_at_1[0x1]; 2484 u8 scatter_fcs[0x1]; 2485 u8 vsd[0x1]; 2486 u8 mem_rq_type[0x4]; 2487 u8 state[0x4]; 2488 u8 reserved_at_c[0x1]; 2489 u8 flush_in_error_en[0x1]; 2490 u8 reserved_at_e[0x12]; 2491 2492 u8 reserved_at_20[0x8]; 2493 u8 user_index[0x18]; 2494 2495 u8 reserved_at_40[0x8]; 2496 u8 cqn[0x18]; 2497 2498 u8 counter_set_id[0x8]; 2499 u8 reserved_at_68[0x18]; 2500 2501 u8 reserved_at_80[0x8]; 2502 u8 rmpn[0x18]; 2503 2504 u8 reserved_at_a0[0xe0]; 2505 2506 struct mlx5_ifc_wq_bits wq; 2507 }; 2508 2509 enum { 2510 MLX5_RMPC_STATE_RDY = 0x1, 2511 MLX5_RMPC_STATE_ERR = 0x3, 2512 }; 2513 2514 struct mlx5_ifc_rmpc_bits { 2515 u8 reserved_at_0[0x8]; 2516 u8 state[0x4]; 2517 u8 reserved_at_c[0x14]; 2518 2519 u8 basic_cyclic_rcv_wqe[0x1]; 2520 u8 reserved_at_21[0x1f]; 2521 2522 u8 reserved_at_40[0x140]; 2523 2524 struct mlx5_ifc_wq_bits wq; 2525 }; 2526 2527 struct mlx5_ifc_nic_vport_context_bits { 2528 u8 reserved_at_0[0x5]; 2529 u8 min_wqe_inline_mode[0x3]; 2530 u8 reserved_at_8[0x17]; 2531 u8 roce_en[0x1]; 2532 2533 u8 arm_change_event[0x1]; 2534 u8 reserved_at_21[0x1a]; 2535 u8 event_on_mtu[0x1]; 2536 u8 event_on_promisc_change[0x1]; 2537 u8 event_on_vlan_change[0x1]; 2538 u8 event_on_mc_address_change[0x1]; 2539 u8 event_on_uc_address_change[0x1]; 2540 2541 u8 reserved_at_40[0xf0]; 2542 2543 u8 mtu[0x10]; 2544 2545 u8 system_image_guid[0x40]; 2546 u8 port_guid[0x40]; 2547 u8 node_guid[0x40]; 2548 2549 u8 reserved_at_200[0x140]; 2550 u8 qkey_violation_counter[0x10]; 2551 u8 reserved_at_350[0x430]; 2552 2553 u8 promisc_uc[0x1]; 2554 u8 promisc_mc[0x1]; 2555 u8 promisc_all[0x1]; 2556 u8 reserved_at_783[0x2]; 2557 u8 allowed_list_type[0x3]; 2558 u8 reserved_at_788[0xc]; 2559 u8 allowed_list_size[0xc]; 2560 2561 struct mlx5_ifc_mac_address_layout_bits permanent_address; 2562 2563 u8 reserved_at_7e0[0x20]; 2564 2565 u8 current_uc_mac_address[0][0x40]; 2566 }; 2567 2568 enum { 2569 MLX5_MKC_ACCESS_MODE_PA = 0x0, 2570 MLX5_MKC_ACCESS_MODE_MTT = 0x1, 2571 MLX5_MKC_ACCESS_MODE_KLMS = 0x2, 2572 MLX5_MKC_ACCESS_MODE_KSM = 0x3, 2573 }; 2574 2575 struct mlx5_ifc_mkc_bits { 2576 u8 reserved_at_0[0x1]; 2577 u8 free[0x1]; 2578 u8 reserved_at_2[0xd]; 2579 u8 small_fence_on_rdma_read_response[0x1]; 2580 u8 umr_en[0x1]; 2581 u8 a[0x1]; 2582 u8 rw[0x1]; 2583 u8 rr[0x1]; 2584 u8 lw[0x1]; 2585 u8 lr[0x1]; 2586 u8 access_mode[0x2]; 2587 u8 reserved_at_18[0x8]; 2588 2589 u8 qpn[0x18]; 2590 u8 mkey_7_0[0x8]; 2591 2592 u8 reserved_at_40[0x20]; 2593 2594 u8 length64[0x1]; 2595 u8 bsf_en[0x1]; 2596 u8 sync_umr[0x1]; 2597 u8 reserved_at_63[0x2]; 2598 u8 expected_sigerr_count[0x1]; 2599 u8 reserved_at_66[0x1]; 2600 u8 en_rinval[0x1]; 2601 u8 pd[0x18]; 2602 2603 u8 start_addr[0x40]; 2604 2605 u8 len[0x40]; 2606 2607 u8 bsf_octword_size[0x20]; 2608 2609 u8 reserved_at_120[0x80]; 2610 2611 u8 translations_octword_size[0x20]; 2612 2613 u8 reserved_at_1c0[0x1b]; 2614 u8 log_page_size[0x5]; 2615 2616 u8 reserved_at_1e0[0x20]; 2617 }; 2618 2619 struct mlx5_ifc_pkey_bits { 2620 u8 reserved_at_0[0x10]; 2621 u8 pkey[0x10]; 2622 }; 2623 2624 struct mlx5_ifc_array128_auto_bits { 2625 u8 array128_auto[16][0x8]; 2626 }; 2627 2628 struct mlx5_ifc_hca_vport_context_bits { 2629 u8 field_select[0x20]; 2630 2631 u8 reserved_at_20[0xe0]; 2632 2633 u8 sm_virt_aware[0x1]; 2634 u8 has_smi[0x1]; 2635 u8 has_raw[0x1]; 2636 u8 grh_required[0x1]; 2637 u8 reserved_at_104[0xc]; 2638 u8 port_physical_state[0x4]; 2639 u8 vport_state_policy[0x4]; 2640 u8 port_state[0x4]; 2641 u8 vport_state[0x4]; 2642 2643 u8 reserved_at_120[0x20]; 2644 2645 u8 system_image_guid[0x40]; 2646 2647 u8 port_guid[0x40]; 2648 2649 u8 node_guid[0x40]; 2650 2651 u8 cap_mask1[0x20]; 2652 2653 u8 cap_mask1_field_select[0x20]; 2654 2655 u8 cap_mask2[0x20]; 2656 2657 u8 cap_mask2_field_select[0x20]; 2658 2659 u8 reserved_at_280[0x80]; 2660 2661 u8 lid[0x10]; 2662 u8 reserved_at_310[0x4]; 2663 u8 init_type_reply[0x4]; 2664 u8 lmc[0x3]; 2665 u8 subnet_timeout[0x5]; 2666 2667 u8 sm_lid[0x10]; 2668 u8 sm_sl[0x4]; 2669 u8 reserved_at_334[0xc]; 2670 2671 u8 qkey_violation_counter[0x10]; 2672 u8 pkey_violation_counter[0x10]; 2673 2674 u8 reserved_at_360[0xca0]; 2675 }; 2676 2677 struct mlx5_ifc_esw_vport_context_bits { 2678 u8 reserved_at_0[0x3]; 2679 u8 vport_svlan_strip[0x1]; 2680 u8 vport_cvlan_strip[0x1]; 2681 u8 vport_svlan_insert[0x1]; 2682 u8 vport_cvlan_insert[0x2]; 2683 u8 reserved_at_8[0x18]; 2684 2685 u8 reserved_at_20[0x20]; 2686 2687 u8 svlan_cfi[0x1]; 2688 u8 svlan_pcp[0x3]; 2689 u8 svlan_id[0xc]; 2690 u8 cvlan_cfi[0x1]; 2691 u8 cvlan_pcp[0x3]; 2692 u8 cvlan_id[0xc]; 2693 2694 u8 reserved_at_60[0x7a0]; 2695 }; 2696 2697 enum { 2698 MLX5_EQC_STATUS_OK = 0x0, 2699 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa, 2700 }; 2701 2702 enum { 2703 MLX5_EQC_ST_ARMED = 0x9, 2704 MLX5_EQC_ST_FIRED = 0xa, 2705 }; 2706 2707 struct mlx5_ifc_eqc_bits { 2708 u8 status[0x4]; 2709 u8 reserved_at_4[0x9]; 2710 u8 ec[0x1]; 2711 u8 oi[0x1]; 2712 u8 reserved_at_f[0x5]; 2713 u8 st[0x4]; 2714 u8 reserved_at_18[0x8]; 2715 2716 u8 reserved_at_20[0x20]; 2717 2718 u8 reserved_at_40[0x14]; 2719 u8 page_offset[0x6]; 2720 u8 reserved_at_5a[0x6]; 2721 2722 u8 reserved_at_60[0x3]; 2723 u8 log_eq_size[0x5]; 2724 u8 uar_page[0x18]; 2725 2726 u8 reserved_at_80[0x20]; 2727 2728 u8 reserved_at_a0[0x18]; 2729 u8 intr[0x8]; 2730 2731 u8 reserved_at_c0[0x3]; 2732 u8 log_page_size[0x5]; 2733 u8 reserved_at_c8[0x18]; 2734 2735 u8 reserved_at_e0[0x60]; 2736 2737 u8 reserved_at_140[0x8]; 2738 u8 consumer_counter[0x18]; 2739 2740 u8 reserved_at_160[0x8]; 2741 u8 producer_counter[0x18]; 2742 2743 u8 reserved_at_180[0x80]; 2744 }; 2745 2746 enum { 2747 MLX5_DCTC_STATE_ACTIVE = 0x0, 2748 MLX5_DCTC_STATE_DRAINING = 0x1, 2749 MLX5_DCTC_STATE_DRAINED = 0x2, 2750 }; 2751 2752 enum { 2753 MLX5_DCTC_CS_RES_DISABLE = 0x0, 2754 MLX5_DCTC_CS_RES_NA = 0x1, 2755 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2, 2756 }; 2757 2758 enum { 2759 MLX5_DCTC_MTU_256_BYTES = 0x1, 2760 MLX5_DCTC_MTU_512_BYTES = 0x2, 2761 MLX5_DCTC_MTU_1K_BYTES = 0x3, 2762 MLX5_DCTC_MTU_2K_BYTES = 0x4, 2763 MLX5_DCTC_MTU_4K_BYTES = 0x5, 2764 }; 2765 2766 struct mlx5_ifc_dctc_bits { 2767 u8 reserved_at_0[0x4]; 2768 u8 state[0x4]; 2769 u8 reserved_at_8[0x18]; 2770 2771 u8 reserved_at_20[0x8]; 2772 u8 user_index[0x18]; 2773 2774 u8 reserved_at_40[0x8]; 2775 u8 cqn[0x18]; 2776 2777 u8 counter_set_id[0x8]; 2778 u8 atomic_mode[0x4]; 2779 u8 rre[0x1]; 2780 u8 rwe[0x1]; 2781 u8 rae[0x1]; 2782 u8 atomic_like_write_en[0x1]; 2783 u8 latency_sensitive[0x1]; 2784 u8 rlky[0x1]; 2785 u8 free_ar[0x1]; 2786 u8 reserved_at_73[0xd]; 2787 2788 u8 reserved_at_80[0x8]; 2789 u8 cs_res[0x8]; 2790 u8 reserved_at_90[0x3]; 2791 u8 min_rnr_nak[0x5]; 2792 u8 reserved_at_98[0x8]; 2793 2794 u8 reserved_at_a0[0x8]; 2795 u8 srqn_xrqn[0x18]; 2796 2797 u8 reserved_at_c0[0x8]; 2798 u8 pd[0x18]; 2799 2800 u8 tclass[0x8]; 2801 u8 reserved_at_e8[0x4]; 2802 u8 flow_label[0x14]; 2803 2804 u8 dc_access_key[0x40]; 2805 2806 u8 reserved_at_140[0x5]; 2807 u8 mtu[0x3]; 2808 u8 port[0x8]; 2809 u8 pkey_index[0x10]; 2810 2811 u8 reserved_at_160[0x8]; 2812 u8 my_addr_index[0x8]; 2813 u8 reserved_at_170[0x8]; 2814 u8 hop_limit[0x8]; 2815 2816 u8 dc_access_key_violation_count[0x20]; 2817 2818 u8 reserved_at_1a0[0x14]; 2819 u8 dei_cfi[0x1]; 2820 u8 eth_prio[0x3]; 2821 u8 ecn[0x2]; 2822 u8 dscp[0x6]; 2823 2824 u8 reserved_at_1c0[0x40]; 2825 }; 2826 2827 enum { 2828 MLX5_CQC_STATUS_OK = 0x0, 2829 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9, 2830 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa, 2831 }; 2832 2833 enum { 2834 MLX5_CQC_CQE_SZ_64_BYTES = 0x0, 2835 MLX5_CQC_CQE_SZ_128_BYTES = 0x1, 2836 }; 2837 2838 enum { 2839 MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED = 0x6, 2840 MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED = 0x9, 2841 MLX5_CQC_ST_FIRED = 0xa, 2842 }; 2843 2844 enum { 2845 MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0, 2846 MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1, 2847 MLX5_CQ_PERIOD_NUM_MODES 2848 }; 2849 2850 struct mlx5_ifc_cqc_bits { 2851 u8 status[0x4]; 2852 u8 reserved_at_4[0x4]; 2853 u8 cqe_sz[0x3]; 2854 u8 cc[0x1]; 2855 u8 reserved_at_c[0x1]; 2856 u8 scqe_break_moderation_en[0x1]; 2857 u8 oi[0x1]; 2858 u8 cq_period_mode[0x2]; 2859 u8 cqe_comp_en[0x1]; 2860 u8 mini_cqe_res_format[0x2]; 2861 u8 st[0x4]; 2862 u8 reserved_at_18[0x8]; 2863 2864 u8 reserved_at_20[0x20]; 2865 2866 u8 reserved_at_40[0x14]; 2867 u8 page_offset[0x6]; 2868 u8 reserved_at_5a[0x6]; 2869 2870 u8 reserved_at_60[0x3]; 2871 u8 log_cq_size[0x5]; 2872 u8 uar_page[0x18]; 2873 2874 u8 reserved_at_80[0x4]; 2875 u8 cq_period[0xc]; 2876 u8 cq_max_count[0x10]; 2877 2878 u8 reserved_at_a0[0x18]; 2879 u8 c_eqn[0x8]; 2880 2881 u8 reserved_at_c0[0x3]; 2882 u8 log_page_size[0x5]; 2883 u8 reserved_at_c8[0x18]; 2884 2885 u8 reserved_at_e0[0x20]; 2886 2887 u8 reserved_at_100[0x8]; 2888 u8 last_notified_index[0x18]; 2889 2890 u8 reserved_at_120[0x8]; 2891 u8 last_solicit_index[0x18]; 2892 2893 u8 reserved_at_140[0x8]; 2894 u8 consumer_counter[0x18]; 2895 2896 u8 reserved_at_160[0x8]; 2897 u8 producer_counter[0x18]; 2898 2899 u8 reserved_at_180[0x40]; 2900 2901 u8 dbr_addr[0x40]; 2902 }; 2903 2904 union mlx5_ifc_cong_control_roce_ecn_auto_bits { 2905 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp; 2906 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp; 2907 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np; 2908 u8 reserved_at_0[0x800]; 2909 }; 2910 2911 struct mlx5_ifc_query_adapter_param_block_bits { 2912 u8 reserved_at_0[0xc0]; 2913 2914 u8 reserved_at_c0[0x8]; 2915 u8 ieee_vendor_id[0x18]; 2916 2917 u8 reserved_at_e0[0x10]; 2918 u8 vsd_vendor_id[0x10]; 2919 2920 u8 vsd[208][0x8]; 2921 2922 u8 vsd_contd_psid[16][0x8]; 2923 }; 2924 2925 enum { 2926 MLX5_XRQC_STATE_GOOD = 0x0, 2927 MLX5_XRQC_STATE_ERROR = 0x1, 2928 }; 2929 2930 enum { 2931 MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0, 2932 MLX5_XRQC_TOPOLOGY_TAG_MATCHING = 0x1, 2933 }; 2934 2935 enum { 2936 MLX5_XRQC_OFFLOAD_RNDV = 0x1, 2937 }; 2938 2939 struct mlx5_ifc_tag_matching_topology_context_bits { 2940 u8 log_matching_list_sz[0x4]; 2941 u8 reserved_at_4[0xc]; 2942 u8 append_next_index[0x10]; 2943 2944 u8 sw_phase_cnt[0x10]; 2945 u8 hw_phase_cnt[0x10]; 2946 2947 u8 reserved_at_40[0x40]; 2948 }; 2949 2950 struct mlx5_ifc_xrqc_bits { 2951 u8 state[0x4]; 2952 u8 rlkey[0x1]; 2953 u8 reserved_at_5[0xf]; 2954 u8 topology[0x4]; 2955 u8 reserved_at_18[0x4]; 2956 u8 offload[0x4]; 2957 2958 u8 reserved_at_20[0x8]; 2959 u8 user_index[0x18]; 2960 2961 u8 reserved_at_40[0x8]; 2962 u8 cqn[0x18]; 2963 2964 u8 reserved_at_60[0xa0]; 2965 2966 struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context; 2967 2968 u8 reserved_at_180[0x880]; 2969 2970 struct mlx5_ifc_wq_bits wq; 2971 }; 2972 2973 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits { 2974 struct mlx5_ifc_modify_field_select_bits modify_field_select; 2975 struct mlx5_ifc_resize_field_select_bits resize_field_select; 2976 u8 reserved_at_0[0x20]; 2977 }; 2978 2979 union mlx5_ifc_field_select_802_1_r_roce_auto_bits { 2980 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp; 2981 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp; 2982 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np; 2983 u8 reserved_at_0[0x20]; 2984 }; 2985 2986 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits { 2987 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 2988 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 2989 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 2990 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 2991 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 2992 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 2993 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout; 2994 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 2995 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 2996 struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs; 2997 u8 reserved_at_0[0x7c0]; 2998 }; 2999 3000 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits { 3001 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout; 3002 u8 reserved_at_0[0x7c0]; 3003 }; 3004 3005 union mlx5_ifc_event_auto_bits { 3006 struct mlx5_ifc_comp_event_bits comp_event; 3007 struct mlx5_ifc_dct_events_bits dct_events; 3008 struct mlx5_ifc_qp_events_bits qp_events; 3009 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event; 3010 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event; 3011 struct mlx5_ifc_cq_error_bits cq_error; 3012 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged; 3013 struct mlx5_ifc_port_state_change_event_bits port_state_change_event; 3014 struct mlx5_ifc_gpio_event_bits gpio_event; 3015 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event; 3016 struct mlx5_ifc_stall_vl_event_bits stall_vl_event; 3017 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event; 3018 u8 reserved_at_0[0xe0]; 3019 }; 3020 3021 struct mlx5_ifc_health_buffer_bits { 3022 u8 reserved_at_0[0x100]; 3023 3024 u8 assert_existptr[0x20]; 3025 3026 u8 assert_callra[0x20]; 3027 3028 u8 reserved_at_140[0x40]; 3029 3030 u8 fw_version[0x20]; 3031 3032 u8 hw_id[0x20]; 3033 3034 u8 reserved_at_1c0[0x20]; 3035 3036 u8 irisc_index[0x8]; 3037 u8 synd[0x8]; 3038 u8 ext_synd[0x10]; 3039 }; 3040 3041 struct mlx5_ifc_register_loopback_control_bits { 3042 u8 no_lb[0x1]; 3043 u8 reserved_at_1[0x7]; 3044 u8 port[0x8]; 3045 u8 reserved_at_10[0x10]; 3046 3047 u8 reserved_at_20[0x60]; 3048 }; 3049 3050 struct mlx5_ifc_vport_tc_element_bits { 3051 u8 traffic_class[0x4]; 3052 u8 reserved_at_4[0xc]; 3053 u8 vport_number[0x10]; 3054 }; 3055 3056 struct mlx5_ifc_vport_element_bits { 3057 u8 reserved_at_0[0x10]; 3058 u8 vport_number[0x10]; 3059 }; 3060 3061 enum { 3062 TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0, 3063 TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1, 3064 TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2, 3065 }; 3066 3067 struct mlx5_ifc_tsar_element_bits { 3068 u8 reserved_at_0[0x8]; 3069 u8 tsar_type[0x8]; 3070 u8 reserved_at_10[0x10]; 3071 }; 3072 3073 struct mlx5_ifc_teardown_hca_out_bits { 3074 u8 status[0x8]; 3075 u8 reserved_at_8[0x18]; 3076 3077 u8 syndrome[0x20]; 3078 3079 u8 reserved_at_40[0x40]; 3080 }; 3081 3082 enum { 3083 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0, 3084 MLX5_TEARDOWN_HCA_IN_PROFILE_PANIC_CLOSE = 0x1, 3085 }; 3086 3087 struct mlx5_ifc_teardown_hca_in_bits { 3088 u8 opcode[0x10]; 3089 u8 reserved_at_10[0x10]; 3090 3091 u8 reserved_at_20[0x10]; 3092 u8 op_mod[0x10]; 3093 3094 u8 reserved_at_40[0x10]; 3095 u8 profile[0x10]; 3096 3097 u8 reserved_at_60[0x20]; 3098 }; 3099 3100 struct mlx5_ifc_sqerr2rts_qp_out_bits { 3101 u8 status[0x8]; 3102 u8 reserved_at_8[0x18]; 3103 3104 u8 syndrome[0x20]; 3105 3106 u8 reserved_at_40[0x40]; 3107 }; 3108 3109 struct mlx5_ifc_sqerr2rts_qp_in_bits { 3110 u8 opcode[0x10]; 3111 u8 reserved_at_10[0x10]; 3112 3113 u8 reserved_at_20[0x10]; 3114 u8 op_mod[0x10]; 3115 3116 u8 reserved_at_40[0x8]; 3117 u8 qpn[0x18]; 3118 3119 u8 reserved_at_60[0x20]; 3120 3121 u8 opt_param_mask[0x20]; 3122 3123 u8 reserved_at_a0[0x20]; 3124 3125 struct mlx5_ifc_qpc_bits qpc; 3126 3127 u8 reserved_at_800[0x80]; 3128 }; 3129 3130 struct mlx5_ifc_sqd2rts_qp_out_bits { 3131 u8 status[0x8]; 3132 u8 reserved_at_8[0x18]; 3133 3134 u8 syndrome[0x20]; 3135 3136 u8 reserved_at_40[0x40]; 3137 }; 3138 3139 struct mlx5_ifc_sqd2rts_qp_in_bits { 3140 u8 opcode[0x10]; 3141 u8 reserved_at_10[0x10]; 3142 3143 u8 reserved_at_20[0x10]; 3144 u8 op_mod[0x10]; 3145 3146 u8 reserved_at_40[0x8]; 3147 u8 qpn[0x18]; 3148 3149 u8 reserved_at_60[0x20]; 3150 3151 u8 opt_param_mask[0x20]; 3152 3153 u8 reserved_at_a0[0x20]; 3154 3155 struct mlx5_ifc_qpc_bits qpc; 3156 3157 u8 reserved_at_800[0x80]; 3158 }; 3159 3160 struct mlx5_ifc_set_roce_address_out_bits { 3161 u8 status[0x8]; 3162 u8 reserved_at_8[0x18]; 3163 3164 u8 syndrome[0x20]; 3165 3166 u8 reserved_at_40[0x40]; 3167 }; 3168 3169 struct mlx5_ifc_set_roce_address_in_bits { 3170 u8 opcode[0x10]; 3171 u8 reserved_at_10[0x10]; 3172 3173 u8 reserved_at_20[0x10]; 3174 u8 op_mod[0x10]; 3175 3176 u8 roce_address_index[0x10]; 3177 u8 reserved_at_50[0x10]; 3178 3179 u8 reserved_at_60[0x20]; 3180 3181 struct mlx5_ifc_roce_addr_layout_bits roce_address; 3182 }; 3183 3184 struct mlx5_ifc_set_mad_demux_out_bits { 3185 u8 status[0x8]; 3186 u8 reserved_at_8[0x18]; 3187 3188 u8 syndrome[0x20]; 3189 3190 u8 reserved_at_40[0x40]; 3191 }; 3192 3193 enum { 3194 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0, 3195 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2, 3196 }; 3197 3198 struct mlx5_ifc_set_mad_demux_in_bits { 3199 u8 opcode[0x10]; 3200 u8 reserved_at_10[0x10]; 3201 3202 u8 reserved_at_20[0x10]; 3203 u8 op_mod[0x10]; 3204 3205 u8 reserved_at_40[0x20]; 3206 3207 u8 reserved_at_60[0x6]; 3208 u8 demux_mode[0x2]; 3209 u8 reserved_at_68[0x18]; 3210 }; 3211 3212 struct mlx5_ifc_set_l2_table_entry_out_bits { 3213 u8 status[0x8]; 3214 u8 reserved_at_8[0x18]; 3215 3216 u8 syndrome[0x20]; 3217 3218 u8 reserved_at_40[0x40]; 3219 }; 3220 3221 struct mlx5_ifc_set_l2_table_entry_in_bits { 3222 u8 opcode[0x10]; 3223 u8 reserved_at_10[0x10]; 3224 3225 u8 reserved_at_20[0x10]; 3226 u8 op_mod[0x10]; 3227 3228 u8 reserved_at_40[0x60]; 3229 3230 u8 reserved_at_a0[0x8]; 3231 u8 table_index[0x18]; 3232 3233 u8 reserved_at_c0[0x20]; 3234 3235 u8 reserved_at_e0[0x13]; 3236 u8 vlan_valid[0x1]; 3237 u8 vlan[0xc]; 3238 3239 struct mlx5_ifc_mac_address_layout_bits mac_address; 3240 3241 u8 reserved_at_140[0xc0]; 3242 }; 3243 3244 struct mlx5_ifc_set_issi_out_bits { 3245 u8 status[0x8]; 3246 u8 reserved_at_8[0x18]; 3247 3248 u8 syndrome[0x20]; 3249 3250 u8 reserved_at_40[0x40]; 3251 }; 3252 3253 struct mlx5_ifc_set_issi_in_bits { 3254 u8 opcode[0x10]; 3255 u8 reserved_at_10[0x10]; 3256 3257 u8 reserved_at_20[0x10]; 3258 u8 op_mod[0x10]; 3259 3260 u8 reserved_at_40[0x10]; 3261 u8 current_issi[0x10]; 3262 3263 u8 reserved_at_60[0x20]; 3264 }; 3265 3266 struct mlx5_ifc_set_hca_cap_out_bits { 3267 u8 status[0x8]; 3268 u8 reserved_at_8[0x18]; 3269 3270 u8 syndrome[0x20]; 3271 3272 u8 reserved_at_40[0x40]; 3273 }; 3274 3275 struct mlx5_ifc_set_hca_cap_in_bits { 3276 u8 opcode[0x10]; 3277 u8 reserved_at_10[0x10]; 3278 3279 u8 reserved_at_20[0x10]; 3280 u8 op_mod[0x10]; 3281 3282 u8 reserved_at_40[0x40]; 3283 3284 union mlx5_ifc_hca_cap_union_bits capability; 3285 }; 3286 3287 enum { 3288 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0, 3289 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1, 3290 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2, 3291 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3 3292 }; 3293 3294 struct mlx5_ifc_set_fte_out_bits { 3295 u8 status[0x8]; 3296 u8 reserved_at_8[0x18]; 3297 3298 u8 syndrome[0x20]; 3299 3300 u8 reserved_at_40[0x40]; 3301 }; 3302 3303 struct mlx5_ifc_set_fte_in_bits { 3304 u8 opcode[0x10]; 3305 u8 reserved_at_10[0x10]; 3306 3307 u8 reserved_at_20[0x10]; 3308 u8 op_mod[0x10]; 3309 3310 u8 other_vport[0x1]; 3311 u8 reserved_at_41[0xf]; 3312 u8 vport_number[0x10]; 3313 3314 u8 reserved_at_60[0x20]; 3315 3316 u8 table_type[0x8]; 3317 u8 reserved_at_88[0x18]; 3318 3319 u8 reserved_at_a0[0x8]; 3320 u8 table_id[0x18]; 3321 3322 u8 reserved_at_c0[0x18]; 3323 u8 modify_enable_mask[0x8]; 3324 3325 u8 reserved_at_e0[0x20]; 3326 3327 u8 flow_index[0x20]; 3328 3329 u8 reserved_at_120[0xe0]; 3330 3331 struct mlx5_ifc_flow_context_bits flow_context; 3332 }; 3333 3334 struct mlx5_ifc_rts2rts_qp_out_bits { 3335 u8 status[0x8]; 3336 u8 reserved_at_8[0x18]; 3337 3338 u8 syndrome[0x20]; 3339 3340 u8 reserved_at_40[0x40]; 3341 }; 3342 3343 struct mlx5_ifc_rts2rts_qp_in_bits { 3344 u8 opcode[0x10]; 3345 u8 reserved_at_10[0x10]; 3346 3347 u8 reserved_at_20[0x10]; 3348 u8 op_mod[0x10]; 3349 3350 u8 reserved_at_40[0x8]; 3351 u8 qpn[0x18]; 3352 3353 u8 reserved_at_60[0x20]; 3354 3355 u8 opt_param_mask[0x20]; 3356 3357 u8 reserved_at_a0[0x20]; 3358 3359 struct mlx5_ifc_qpc_bits qpc; 3360 3361 u8 reserved_at_800[0x80]; 3362 }; 3363 3364 struct mlx5_ifc_rtr2rts_qp_out_bits { 3365 u8 status[0x8]; 3366 u8 reserved_at_8[0x18]; 3367 3368 u8 syndrome[0x20]; 3369 3370 u8 reserved_at_40[0x40]; 3371 }; 3372 3373 struct mlx5_ifc_rtr2rts_qp_in_bits { 3374 u8 opcode[0x10]; 3375 u8 reserved_at_10[0x10]; 3376 3377 u8 reserved_at_20[0x10]; 3378 u8 op_mod[0x10]; 3379 3380 u8 reserved_at_40[0x8]; 3381 u8 qpn[0x18]; 3382 3383 u8 reserved_at_60[0x20]; 3384 3385 u8 opt_param_mask[0x20]; 3386 3387 u8 reserved_at_a0[0x20]; 3388 3389 struct mlx5_ifc_qpc_bits qpc; 3390 3391 u8 reserved_at_800[0x80]; 3392 }; 3393 3394 struct mlx5_ifc_rst2init_qp_out_bits { 3395 u8 status[0x8]; 3396 u8 reserved_at_8[0x18]; 3397 3398 u8 syndrome[0x20]; 3399 3400 u8 reserved_at_40[0x40]; 3401 }; 3402 3403 struct mlx5_ifc_rst2init_qp_in_bits { 3404 u8 opcode[0x10]; 3405 u8 reserved_at_10[0x10]; 3406 3407 u8 reserved_at_20[0x10]; 3408 u8 op_mod[0x10]; 3409 3410 u8 reserved_at_40[0x8]; 3411 u8 qpn[0x18]; 3412 3413 u8 reserved_at_60[0x20]; 3414 3415 u8 opt_param_mask[0x20]; 3416 3417 u8 reserved_at_a0[0x20]; 3418 3419 struct mlx5_ifc_qpc_bits qpc; 3420 3421 u8 reserved_at_800[0x80]; 3422 }; 3423 3424 struct mlx5_ifc_query_xrq_out_bits { 3425 u8 status[0x8]; 3426 u8 reserved_at_8[0x18]; 3427 3428 u8 syndrome[0x20]; 3429 3430 u8 reserved_at_40[0x40]; 3431 3432 struct mlx5_ifc_xrqc_bits xrq_context; 3433 }; 3434 3435 struct mlx5_ifc_query_xrq_in_bits { 3436 u8 opcode[0x10]; 3437 u8 reserved_at_10[0x10]; 3438 3439 u8 reserved_at_20[0x10]; 3440 u8 op_mod[0x10]; 3441 3442 u8 reserved_at_40[0x8]; 3443 u8 xrqn[0x18]; 3444 3445 u8 reserved_at_60[0x20]; 3446 }; 3447 3448 struct mlx5_ifc_query_xrc_srq_out_bits { 3449 u8 status[0x8]; 3450 u8 reserved_at_8[0x18]; 3451 3452 u8 syndrome[0x20]; 3453 3454 u8 reserved_at_40[0x40]; 3455 3456 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 3457 3458 u8 reserved_at_280[0x600]; 3459 3460 u8 pas[0][0x40]; 3461 }; 3462 3463 struct mlx5_ifc_query_xrc_srq_in_bits { 3464 u8 opcode[0x10]; 3465 u8 reserved_at_10[0x10]; 3466 3467 u8 reserved_at_20[0x10]; 3468 u8 op_mod[0x10]; 3469 3470 u8 reserved_at_40[0x8]; 3471 u8 xrc_srqn[0x18]; 3472 3473 u8 reserved_at_60[0x20]; 3474 }; 3475 3476 enum { 3477 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0, 3478 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1, 3479 }; 3480 3481 struct mlx5_ifc_query_vport_state_out_bits { 3482 u8 status[0x8]; 3483 u8 reserved_at_8[0x18]; 3484 3485 u8 syndrome[0x20]; 3486 3487 u8 reserved_at_40[0x20]; 3488 3489 u8 reserved_at_60[0x18]; 3490 u8 admin_state[0x4]; 3491 u8 state[0x4]; 3492 }; 3493 3494 enum { 3495 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT = 0x0, 3496 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_ESW_VPORT = 0x1, 3497 }; 3498 3499 struct mlx5_ifc_query_vport_state_in_bits { 3500 u8 opcode[0x10]; 3501 u8 reserved_at_10[0x10]; 3502 3503 u8 reserved_at_20[0x10]; 3504 u8 op_mod[0x10]; 3505 3506 u8 other_vport[0x1]; 3507 u8 reserved_at_41[0xf]; 3508 u8 vport_number[0x10]; 3509 3510 u8 reserved_at_60[0x20]; 3511 }; 3512 3513 struct mlx5_ifc_query_vport_counter_out_bits { 3514 u8 status[0x8]; 3515 u8 reserved_at_8[0x18]; 3516 3517 u8 syndrome[0x20]; 3518 3519 u8 reserved_at_40[0x40]; 3520 3521 struct mlx5_ifc_traffic_counter_bits received_errors; 3522 3523 struct mlx5_ifc_traffic_counter_bits transmit_errors; 3524 3525 struct mlx5_ifc_traffic_counter_bits received_ib_unicast; 3526 3527 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast; 3528 3529 struct mlx5_ifc_traffic_counter_bits received_ib_multicast; 3530 3531 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast; 3532 3533 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast; 3534 3535 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast; 3536 3537 struct mlx5_ifc_traffic_counter_bits received_eth_unicast; 3538 3539 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast; 3540 3541 struct mlx5_ifc_traffic_counter_bits received_eth_multicast; 3542 3543 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast; 3544 3545 u8 reserved_at_680[0xa00]; 3546 }; 3547 3548 enum { 3549 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0, 3550 }; 3551 3552 struct mlx5_ifc_query_vport_counter_in_bits { 3553 u8 opcode[0x10]; 3554 u8 reserved_at_10[0x10]; 3555 3556 u8 reserved_at_20[0x10]; 3557 u8 op_mod[0x10]; 3558 3559 u8 other_vport[0x1]; 3560 u8 reserved_at_41[0xb]; 3561 u8 port_num[0x4]; 3562 u8 vport_number[0x10]; 3563 3564 u8 reserved_at_60[0x60]; 3565 3566 u8 clear[0x1]; 3567 u8 reserved_at_c1[0x1f]; 3568 3569 u8 reserved_at_e0[0x20]; 3570 }; 3571 3572 struct mlx5_ifc_query_tis_out_bits { 3573 u8 status[0x8]; 3574 u8 reserved_at_8[0x18]; 3575 3576 u8 syndrome[0x20]; 3577 3578 u8 reserved_at_40[0x40]; 3579 3580 struct mlx5_ifc_tisc_bits tis_context; 3581 }; 3582 3583 struct mlx5_ifc_query_tis_in_bits { 3584 u8 opcode[0x10]; 3585 u8 reserved_at_10[0x10]; 3586 3587 u8 reserved_at_20[0x10]; 3588 u8 op_mod[0x10]; 3589 3590 u8 reserved_at_40[0x8]; 3591 u8 tisn[0x18]; 3592 3593 u8 reserved_at_60[0x20]; 3594 }; 3595 3596 struct mlx5_ifc_query_tir_out_bits { 3597 u8 status[0x8]; 3598 u8 reserved_at_8[0x18]; 3599 3600 u8 syndrome[0x20]; 3601 3602 u8 reserved_at_40[0xc0]; 3603 3604 struct mlx5_ifc_tirc_bits tir_context; 3605 }; 3606 3607 struct mlx5_ifc_query_tir_in_bits { 3608 u8 opcode[0x10]; 3609 u8 reserved_at_10[0x10]; 3610 3611 u8 reserved_at_20[0x10]; 3612 u8 op_mod[0x10]; 3613 3614 u8 reserved_at_40[0x8]; 3615 u8 tirn[0x18]; 3616 3617 u8 reserved_at_60[0x20]; 3618 }; 3619 3620 struct mlx5_ifc_query_srq_out_bits { 3621 u8 status[0x8]; 3622 u8 reserved_at_8[0x18]; 3623 3624 u8 syndrome[0x20]; 3625 3626 u8 reserved_at_40[0x40]; 3627 3628 struct mlx5_ifc_srqc_bits srq_context_entry; 3629 3630 u8 reserved_at_280[0x600]; 3631 3632 u8 pas[0][0x40]; 3633 }; 3634 3635 struct mlx5_ifc_query_srq_in_bits { 3636 u8 opcode[0x10]; 3637 u8 reserved_at_10[0x10]; 3638 3639 u8 reserved_at_20[0x10]; 3640 u8 op_mod[0x10]; 3641 3642 u8 reserved_at_40[0x8]; 3643 u8 srqn[0x18]; 3644 3645 u8 reserved_at_60[0x20]; 3646 }; 3647 3648 struct mlx5_ifc_query_sq_out_bits { 3649 u8 status[0x8]; 3650 u8 reserved_at_8[0x18]; 3651 3652 u8 syndrome[0x20]; 3653 3654 u8 reserved_at_40[0xc0]; 3655 3656 struct mlx5_ifc_sqc_bits sq_context; 3657 }; 3658 3659 struct mlx5_ifc_query_sq_in_bits { 3660 u8 opcode[0x10]; 3661 u8 reserved_at_10[0x10]; 3662 3663 u8 reserved_at_20[0x10]; 3664 u8 op_mod[0x10]; 3665 3666 u8 reserved_at_40[0x8]; 3667 u8 sqn[0x18]; 3668 3669 u8 reserved_at_60[0x20]; 3670 }; 3671 3672 struct mlx5_ifc_query_special_contexts_out_bits { 3673 u8 status[0x8]; 3674 u8 reserved_at_8[0x18]; 3675 3676 u8 syndrome[0x20]; 3677 3678 u8 dump_fill_mkey[0x20]; 3679 3680 u8 resd_lkey[0x20]; 3681 3682 u8 null_mkey[0x20]; 3683 3684 u8 reserved_at_a0[0x60]; 3685 }; 3686 3687 struct mlx5_ifc_query_special_contexts_in_bits { 3688 u8 opcode[0x10]; 3689 u8 reserved_at_10[0x10]; 3690 3691 u8 reserved_at_20[0x10]; 3692 u8 op_mod[0x10]; 3693 3694 u8 reserved_at_40[0x40]; 3695 }; 3696 3697 struct mlx5_ifc_query_scheduling_element_out_bits { 3698 u8 opcode[0x10]; 3699 u8 reserved_at_10[0x10]; 3700 3701 u8 reserved_at_20[0x10]; 3702 u8 op_mod[0x10]; 3703 3704 u8 reserved_at_40[0xc0]; 3705 3706 struct mlx5_ifc_scheduling_context_bits scheduling_context; 3707 3708 u8 reserved_at_300[0x100]; 3709 }; 3710 3711 enum { 3712 SCHEDULING_HIERARCHY_E_SWITCH = 0x2, 3713 }; 3714 3715 struct mlx5_ifc_query_scheduling_element_in_bits { 3716 u8 opcode[0x10]; 3717 u8 reserved_at_10[0x10]; 3718 3719 u8 reserved_at_20[0x10]; 3720 u8 op_mod[0x10]; 3721 3722 u8 scheduling_hierarchy[0x8]; 3723 u8 reserved_at_48[0x18]; 3724 3725 u8 scheduling_element_id[0x20]; 3726 3727 u8 reserved_at_80[0x180]; 3728 }; 3729 3730 struct mlx5_ifc_query_rqt_out_bits { 3731 u8 status[0x8]; 3732 u8 reserved_at_8[0x18]; 3733 3734 u8 syndrome[0x20]; 3735 3736 u8 reserved_at_40[0xc0]; 3737 3738 struct mlx5_ifc_rqtc_bits rqt_context; 3739 }; 3740 3741 struct mlx5_ifc_query_rqt_in_bits { 3742 u8 opcode[0x10]; 3743 u8 reserved_at_10[0x10]; 3744 3745 u8 reserved_at_20[0x10]; 3746 u8 op_mod[0x10]; 3747 3748 u8 reserved_at_40[0x8]; 3749 u8 rqtn[0x18]; 3750 3751 u8 reserved_at_60[0x20]; 3752 }; 3753 3754 struct mlx5_ifc_query_rq_out_bits { 3755 u8 status[0x8]; 3756 u8 reserved_at_8[0x18]; 3757 3758 u8 syndrome[0x20]; 3759 3760 u8 reserved_at_40[0xc0]; 3761 3762 struct mlx5_ifc_rqc_bits rq_context; 3763 }; 3764 3765 struct mlx5_ifc_query_rq_in_bits { 3766 u8 opcode[0x10]; 3767 u8 reserved_at_10[0x10]; 3768 3769 u8 reserved_at_20[0x10]; 3770 u8 op_mod[0x10]; 3771 3772 u8 reserved_at_40[0x8]; 3773 u8 rqn[0x18]; 3774 3775 u8 reserved_at_60[0x20]; 3776 }; 3777 3778 struct mlx5_ifc_query_roce_address_out_bits { 3779 u8 status[0x8]; 3780 u8 reserved_at_8[0x18]; 3781 3782 u8 syndrome[0x20]; 3783 3784 u8 reserved_at_40[0x40]; 3785 3786 struct mlx5_ifc_roce_addr_layout_bits roce_address; 3787 }; 3788 3789 struct mlx5_ifc_query_roce_address_in_bits { 3790 u8 opcode[0x10]; 3791 u8 reserved_at_10[0x10]; 3792 3793 u8 reserved_at_20[0x10]; 3794 u8 op_mod[0x10]; 3795 3796 u8 roce_address_index[0x10]; 3797 u8 reserved_at_50[0x10]; 3798 3799 u8 reserved_at_60[0x20]; 3800 }; 3801 3802 struct mlx5_ifc_query_rmp_out_bits { 3803 u8 status[0x8]; 3804 u8 reserved_at_8[0x18]; 3805 3806 u8 syndrome[0x20]; 3807 3808 u8 reserved_at_40[0xc0]; 3809 3810 struct mlx5_ifc_rmpc_bits rmp_context; 3811 }; 3812 3813 struct mlx5_ifc_query_rmp_in_bits { 3814 u8 opcode[0x10]; 3815 u8 reserved_at_10[0x10]; 3816 3817 u8 reserved_at_20[0x10]; 3818 u8 op_mod[0x10]; 3819 3820 u8 reserved_at_40[0x8]; 3821 u8 rmpn[0x18]; 3822 3823 u8 reserved_at_60[0x20]; 3824 }; 3825 3826 struct mlx5_ifc_query_qp_out_bits { 3827 u8 status[0x8]; 3828 u8 reserved_at_8[0x18]; 3829 3830 u8 syndrome[0x20]; 3831 3832 u8 reserved_at_40[0x40]; 3833 3834 u8 opt_param_mask[0x20]; 3835 3836 u8 reserved_at_a0[0x20]; 3837 3838 struct mlx5_ifc_qpc_bits qpc; 3839 3840 u8 reserved_at_800[0x80]; 3841 3842 u8 pas[0][0x40]; 3843 }; 3844 3845 struct mlx5_ifc_query_qp_in_bits { 3846 u8 opcode[0x10]; 3847 u8 reserved_at_10[0x10]; 3848 3849 u8 reserved_at_20[0x10]; 3850 u8 op_mod[0x10]; 3851 3852 u8 reserved_at_40[0x8]; 3853 u8 qpn[0x18]; 3854 3855 u8 reserved_at_60[0x20]; 3856 }; 3857 3858 struct mlx5_ifc_query_q_counter_out_bits { 3859 u8 status[0x8]; 3860 u8 reserved_at_8[0x18]; 3861 3862 u8 syndrome[0x20]; 3863 3864 u8 reserved_at_40[0x40]; 3865 3866 u8 rx_write_requests[0x20]; 3867 3868 u8 reserved_at_a0[0x20]; 3869 3870 u8 rx_read_requests[0x20]; 3871 3872 u8 reserved_at_e0[0x20]; 3873 3874 u8 rx_atomic_requests[0x20]; 3875 3876 u8 reserved_at_120[0x20]; 3877 3878 u8 rx_dct_connect[0x20]; 3879 3880 u8 reserved_at_160[0x20]; 3881 3882 u8 out_of_buffer[0x20]; 3883 3884 u8 reserved_at_1a0[0x20]; 3885 3886 u8 out_of_sequence[0x20]; 3887 3888 u8 reserved_at_1e0[0x20]; 3889 3890 u8 duplicate_request[0x20]; 3891 3892 u8 reserved_at_220[0x20]; 3893 3894 u8 rnr_nak_retry_err[0x20]; 3895 3896 u8 reserved_at_260[0x20]; 3897 3898 u8 packet_seq_err[0x20]; 3899 3900 u8 reserved_at_2a0[0x20]; 3901 3902 u8 implied_nak_seq_err[0x20]; 3903 3904 u8 reserved_at_2e0[0x20]; 3905 3906 u8 local_ack_timeout_err[0x20]; 3907 3908 u8 reserved_at_320[0x4e0]; 3909 }; 3910 3911 struct mlx5_ifc_query_q_counter_in_bits { 3912 u8 opcode[0x10]; 3913 u8 reserved_at_10[0x10]; 3914 3915 u8 reserved_at_20[0x10]; 3916 u8 op_mod[0x10]; 3917 3918 u8 reserved_at_40[0x80]; 3919 3920 u8 clear[0x1]; 3921 u8 reserved_at_c1[0x1f]; 3922 3923 u8 reserved_at_e0[0x18]; 3924 u8 counter_set_id[0x8]; 3925 }; 3926 3927 struct mlx5_ifc_query_pages_out_bits { 3928 u8 status[0x8]; 3929 u8 reserved_at_8[0x18]; 3930 3931 u8 syndrome[0x20]; 3932 3933 u8 reserved_at_40[0x10]; 3934 u8 function_id[0x10]; 3935 3936 u8 num_pages[0x20]; 3937 }; 3938 3939 enum { 3940 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1, 3941 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2, 3942 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3, 3943 }; 3944 3945 struct mlx5_ifc_query_pages_in_bits { 3946 u8 opcode[0x10]; 3947 u8 reserved_at_10[0x10]; 3948 3949 u8 reserved_at_20[0x10]; 3950 u8 op_mod[0x10]; 3951 3952 u8 reserved_at_40[0x10]; 3953 u8 function_id[0x10]; 3954 3955 u8 reserved_at_60[0x20]; 3956 }; 3957 3958 struct mlx5_ifc_query_nic_vport_context_out_bits { 3959 u8 status[0x8]; 3960 u8 reserved_at_8[0x18]; 3961 3962 u8 syndrome[0x20]; 3963 3964 u8 reserved_at_40[0x40]; 3965 3966 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 3967 }; 3968 3969 struct mlx5_ifc_query_nic_vport_context_in_bits { 3970 u8 opcode[0x10]; 3971 u8 reserved_at_10[0x10]; 3972 3973 u8 reserved_at_20[0x10]; 3974 u8 op_mod[0x10]; 3975 3976 u8 other_vport[0x1]; 3977 u8 reserved_at_41[0xf]; 3978 u8 vport_number[0x10]; 3979 3980 u8 reserved_at_60[0x5]; 3981 u8 allowed_list_type[0x3]; 3982 u8 reserved_at_68[0x18]; 3983 }; 3984 3985 struct mlx5_ifc_query_mkey_out_bits { 3986 u8 status[0x8]; 3987 u8 reserved_at_8[0x18]; 3988 3989 u8 syndrome[0x20]; 3990 3991 u8 reserved_at_40[0x40]; 3992 3993 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 3994 3995 u8 reserved_at_280[0x600]; 3996 3997 u8 bsf0_klm0_pas_mtt0_1[16][0x8]; 3998 3999 u8 bsf1_klm1_pas_mtt2_3[16][0x8]; 4000 }; 4001 4002 struct mlx5_ifc_query_mkey_in_bits { 4003 u8 opcode[0x10]; 4004 u8 reserved_at_10[0x10]; 4005 4006 u8 reserved_at_20[0x10]; 4007 u8 op_mod[0x10]; 4008 4009 u8 reserved_at_40[0x8]; 4010 u8 mkey_index[0x18]; 4011 4012 u8 pg_access[0x1]; 4013 u8 reserved_at_61[0x1f]; 4014 }; 4015 4016 struct mlx5_ifc_query_mad_demux_out_bits { 4017 u8 status[0x8]; 4018 u8 reserved_at_8[0x18]; 4019 4020 u8 syndrome[0x20]; 4021 4022 u8 reserved_at_40[0x40]; 4023 4024 u8 mad_dumux_parameters_block[0x20]; 4025 }; 4026 4027 struct mlx5_ifc_query_mad_demux_in_bits { 4028 u8 opcode[0x10]; 4029 u8 reserved_at_10[0x10]; 4030 4031 u8 reserved_at_20[0x10]; 4032 u8 op_mod[0x10]; 4033 4034 u8 reserved_at_40[0x40]; 4035 }; 4036 4037 struct mlx5_ifc_query_l2_table_entry_out_bits { 4038 u8 status[0x8]; 4039 u8 reserved_at_8[0x18]; 4040 4041 u8 syndrome[0x20]; 4042 4043 u8 reserved_at_40[0xa0]; 4044 4045 u8 reserved_at_e0[0x13]; 4046 u8 vlan_valid[0x1]; 4047 u8 vlan[0xc]; 4048 4049 struct mlx5_ifc_mac_address_layout_bits mac_address; 4050 4051 u8 reserved_at_140[0xc0]; 4052 }; 4053 4054 struct mlx5_ifc_query_l2_table_entry_in_bits { 4055 u8 opcode[0x10]; 4056 u8 reserved_at_10[0x10]; 4057 4058 u8 reserved_at_20[0x10]; 4059 u8 op_mod[0x10]; 4060 4061 u8 reserved_at_40[0x60]; 4062 4063 u8 reserved_at_a0[0x8]; 4064 u8 table_index[0x18]; 4065 4066 u8 reserved_at_c0[0x140]; 4067 }; 4068 4069 struct mlx5_ifc_query_issi_out_bits { 4070 u8 status[0x8]; 4071 u8 reserved_at_8[0x18]; 4072 4073 u8 syndrome[0x20]; 4074 4075 u8 reserved_at_40[0x10]; 4076 u8 current_issi[0x10]; 4077 4078 u8 reserved_at_60[0xa0]; 4079 4080 u8 reserved_at_100[76][0x8]; 4081 u8 supported_issi_dw0[0x20]; 4082 }; 4083 4084 struct mlx5_ifc_query_issi_in_bits { 4085 u8 opcode[0x10]; 4086 u8 reserved_at_10[0x10]; 4087 4088 u8 reserved_at_20[0x10]; 4089 u8 op_mod[0x10]; 4090 4091 u8 reserved_at_40[0x40]; 4092 }; 4093 4094 struct mlx5_ifc_set_driver_version_out_bits { 4095 u8 status[0x8]; 4096 u8 reserved_0[0x18]; 4097 4098 u8 syndrome[0x20]; 4099 u8 reserved_1[0x40]; 4100 }; 4101 4102 struct mlx5_ifc_set_driver_version_in_bits { 4103 u8 opcode[0x10]; 4104 u8 reserved_0[0x10]; 4105 4106 u8 reserved_1[0x10]; 4107 u8 op_mod[0x10]; 4108 4109 u8 reserved_2[0x40]; 4110 u8 driver_version[64][0x8]; 4111 }; 4112 4113 struct mlx5_ifc_query_hca_vport_pkey_out_bits { 4114 u8 status[0x8]; 4115 u8 reserved_at_8[0x18]; 4116 4117 u8 syndrome[0x20]; 4118 4119 u8 reserved_at_40[0x40]; 4120 4121 struct mlx5_ifc_pkey_bits pkey[0]; 4122 }; 4123 4124 struct mlx5_ifc_query_hca_vport_pkey_in_bits { 4125 u8 opcode[0x10]; 4126 u8 reserved_at_10[0x10]; 4127 4128 u8 reserved_at_20[0x10]; 4129 u8 op_mod[0x10]; 4130 4131 u8 other_vport[0x1]; 4132 u8 reserved_at_41[0xb]; 4133 u8 port_num[0x4]; 4134 u8 vport_number[0x10]; 4135 4136 u8 reserved_at_60[0x10]; 4137 u8 pkey_index[0x10]; 4138 }; 4139 4140 enum { 4141 MLX5_HCA_VPORT_SEL_PORT_GUID = 1 << 0, 4142 MLX5_HCA_VPORT_SEL_NODE_GUID = 1 << 1, 4143 MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2, 4144 }; 4145 4146 struct mlx5_ifc_query_hca_vport_gid_out_bits { 4147 u8 status[0x8]; 4148 u8 reserved_at_8[0x18]; 4149 4150 u8 syndrome[0x20]; 4151 4152 u8 reserved_at_40[0x20]; 4153 4154 u8 gids_num[0x10]; 4155 u8 reserved_at_70[0x10]; 4156 4157 struct mlx5_ifc_array128_auto_bits gid[0]; 4158 }; 4159 4160 struct mlx5_ifc_query_hca_vport_gid_in_bits { 4161 u8 opcode[0x10]; 4162 u8 reserved_at_10[0x10]; 4163 4164 u8 reserved_at_20[0x10]; 4165 u8 op_mod[0x10]; 4166 4167 u8 other_vport[0x1]; 4168 u8 reserved_at_41[0xb]; 4169 u8 port_num[0x4]; 4170 u8 vport_number[0x10]; 4171 4172 u8 reserved_at_60[0x10]; 4173 u8 gid_index[0x10]; 4174 }; 4175 4176 struct mlx5_ifc_query_hca_vport_context_out_bits { 4177 u8 status[0x8]; 4178 u8 reserved_at_8[0x18]; 4179 4180 u8 syndrome[0x20]; 4181 4182 u8 reserved_at_40[0x40]; 4183 4184 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 4185 }; 4186 4187 struct mlx5_ifc_query_hca_vport_context_in_bits { 4188 u8 opcode[0x10]; 4189 u8 reserved_at_10[0x10]; 4190 4191 u8 reserved_at_20[0x10]; 4192 u8 op_mod[0x10]; 4193 4194 u8 other_vport[0x1]; 4195 u8 reserved_at_41[0xb]; 4196 u8 port_num[0x4]; 4197 u8 vport_number[0x10]; 4198 4199 u8 reserved_at_60[0x20]; 4200 }; 4201 4202 struct mlx5_ifc_query_hca_cap_out_bits { 4203 u8 status[0x8]; 4204 u8 reserved_at_8[0x18]; 4205 4206 u8 syndrome[0x20]; 4207 4208 u8 reserved_at_40[0x40]; 4209 4210 union mlx5_ifc_hca_cap_union_bits capability; 4211 }; 4212 4213 struct mlx5_ifc_query_hca_cap_in_bits { 4214 u8 opcode[0x10]; 4215 u8 reserved_at_10[0x10]; 4216 4217 u8 reserved_at_20[0x10]; 4218 u8 op_mod[0x10]; 4219 4220 u8 reserved_at_40[0x40]; 4221 }; 4222 4223 struct mlx5_ifc_query_flow_table_out_bits { 4224 u8 status[0x8]; 4225 u8 reserved_at_8[0x18]; 4226 4227 u8 syndrome[0x20]; 4228 4229 u8 reserved_at_40[0x80]; 4230 4231 u8 reserved_at_c0[0x8]; 4232 u8 level[0x8]; 4233 u8 reserved_at_d0[0x8]; 4234 u8 log_size[0x8]; 4235 4236 u8 reserved_at_e0[0x120]; 4237 }; 4238 4239 struct mlx5_ifc_query_flow_table_in_bits { 4240 u8 opcode[0x10]; 4241 u8 reserved_at_10[0x10]; 4242 4243 u8 reserved_at_20[0x10]; 4244 u8 op_mod[0x10]; 4245 4246 u8 reserved_at_40[0x40]; 4247 4248 u8 table_type[0x8]; 4249 u8 reserved_at_88[0x18]; 4250 4251 u8 reserved_at_a0[0x8]; 4252 u8 table_id[0x18]; 4253 4254 u8 reserved_at_c0[0x140]; 4255 }; 4256 4257 struct mlx5_ifc_query_fte_out_bits { 4258 u8 status[0x8]; 4259 u8 reserved_at_8[0x18]; 4260 4261 u8 syndrome[0x20]; 4262 4263 u8 reserved_at_40[0x1c0]; 4264 4265 struct mlx5_ifc_flow_context_bits flow_context; 4266 }; 4267 4268 struct mlx5_ifc_query_fte_in_bits { 4269 u8 opcode[0x10]; 4270 u8 reserved_at_10[0x10]; 4271 4272 u8 reserved_at_20[0x10]; 4273 u8 op_mod[0x10]; 4274 4275 u8 reserved_at_40[0x40]; 4276 4277 u8 table_type[0x8]; 4278 u8 reserved_at_88[0x18]; 4279 4280 u8 reserved_at_a0[0x8]; 4281 u8 table_id[0x18]; 4282 4283 u8 reserved_at_c0[0x40]; 4284 4285 u8 flow_index[0x20]; 4286 4287 u8 reserved_at_120[0xe0]; 4288 }; 4289 4290 enum { 4291 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 4292 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 4293 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 4294 }; 4295 4296 struct mlx5_ifc_query_flow_group_out_bits { 4297 u8 status[0x8]; 4298 u8 reserved_at_8[0x18]; 4299 4300 u8 syndrome[0x20]; 4301 4302 u8 reserved_at_40[0xa0]; 4303 4304 u8 start_flow_index[0x20]; 4305 4306 u8 reserved_at_100[0x20]; 4307 4308 u8 end_flow_index[0x20]; 4309 4310 u8 reserved_at_140[0xa0]; 4311 4312 u8 reserved_at_1e0[0x18]; 4313 u8 match_criteria_enable[0x8]; 4314 4315 struct mlx5_ifc_fte_match_param_bits match_criteria; 4316 4317 u8 reserved_at_1200[0xe00]; 4318 }; 4319 4320 struct mlx5_ifc_query_flow_group_in_bits { 4321 u8 opcode[0x10]; 4322 u8 reserved_at_10[0x10]; 4323 4324 u8 reserved_at_20[0x10]; 4325 u8 op_mod[0x10]; 4326 4327 u8 reserved_at_40[0x40]; 4328 4329 u8 table_type[0x8]; 4330 u8 reserved_at_88[0x18]; 4331 4332 u8 reserved_at_a0[0x8]; 4333 u8 table_id[0x18]; 4334 4335 u8 group_id[0x20]; 4336 4337 u8 reserved_at_e0[0x120]; 4338 }; 4339 4340 struct mlx5_ifc_query_flow_counter_out_bits { 4341 u8 status[0x8]; 4342 u8 reserved_at_8[0x18]; 4343 4344 u8 syndrome[0x20]; 4345 4346 u8 reserved_at_40[0x40]; 4347 4348 struct mlx5_ifc_traffic_counter_bits flow_statistics[0]; 4349 }; 4350 4351 struct mlx5_ifc_query_flow_counter_in_bits { 4352 u8 opcode[0x10]; 4353 u8 reserved_at_10[0x10]; 4354 4355 u8 reserved_at_20[0x10]; 4356 u8 op_mod[0x10]; 4357 4358 u8 reserved_at_40[0x80]; 4359 4360 u8 clear[0x1]; 4361 u8 reserved_at_c1[0xf]; 4362 u8 num_of_counters[0x10]; 4363 4364 u8 reserved_at_e0[0x10]; 4365 u8 flow_counter_id[0x10]; 4366 }; 4367 4368 struct mlx5_ifc_query_esw_vport_context_out_bits { 4369 u8 status[0x8]; 4370 u8 reserved_at_8[0x18]; 4371 4372 u8 syndrome[0x20]; 4373 4374 u8 reserved_at_40[0x40]; 4375 4376 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 4377 }; 4378 4379 struct mlx5_ifc_query_esw_vport_context_in_bits { 4380 u8 opcode[0x10]; 4381 u8 reserved_at_10[0x10]; 4382 4383 u8 reserved_at_20[0x10]; 4384 u8 op_mod[0x10]; 4385 4386 u8 other_vport[0x1]; 4387 u8 reserved_at_41[0xf]; 4388 u8 vport_number[0x10]; 4389 4390 u8 reserved_at_60[0x20]; 4391 }; 4392 4393 struct mlx5_ifc_modify_esw_vport_context_out_bits { 4394 u8 status[0x8]; 4395 u8 reserved_at_8[0x18]; 4396 4397 u8 syndrome[0x20]; 4398 4399 u8 reserved_at_40[0x40]; 4400 }; 4401 4402 struct mlx5_ifc_esw_vport_context_fields_select_bits { 4403 u8 reserved_at_0[0x1c]; 4404 u8 vport_cvlan_insert[0x1]; 4405 u8 vport_svlan_insert[0x1]; 4406 u8 vport_cvlan_strip[0x1]; 4407 u8 vport_svlan_strip[0x1]; 4408 }; 4409 4410 struct mlx5_ifc_modify_esw_vport_context_in_bits { 4411 u8 opcode[0x10]; 4412 u8 reserved_at_10[0x10]; 4413 4414 u8 reserved_at_20[0x10]; 4415 u8 op_mod[0x10]; 4416 4417 u8 other_vport[0x1]; 4418 u8 reserved_at_41[0xf]; 4419 u8 vport_number[0x10]; 4420 4421 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select; 4422 4423 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 4424 }; 4425 4426 struct mlx5_ifc_query_eq_out_bits { 4427 u8 status[0x8]; 4428 u8 reserved_at_8[0x18]; 4429 4430 u8 syndrome[0x20]; 4431 4432 u8 reserved_at_40[0x40]; 4433 4434 struct mlx5_ifc_eqc_bits eq_context_entry; 4435 4436 u8 reserved_at_280[0x40]; 4437 4438 u8 event_bitmask[0x40]; 4439 4440 u8 reserved_at_300[0x580]; 4441 4442 u8 pas[0][0x40]; 4443 }; 4444 4445 struct mlx5_ifc_query_eq_in_bits { 4446 u8 opcode[0x10]; 4447 u8 reserved_at_10[0x10]; 4448 4449 u8 reserved_at_20[0x10]; 4450 u8 op_mod[0x10]; 4451 4452 u8 reserved_at_40[0x18]; 4453 u8 eq_number[0x8]; 4454 4455 u8 reserved_at_60[0x20]; 4456 }; 4457 4458 struct mlx5_ifc_encap_header_in_bits { 4459 u8 reserved_at_0[0x5]; 4460 u8 header_type[0x3]; 4461 u8 reserved_at_8[0xe]; 4462 u8 encap_header_size[0xa]; 4463 4464 u8 reserved_at_20[0x10]; 4465 u8 encap_header[2][0x8]; 4466 4467 u8 more_encap_header[0][0x8]; 4468 }; 4469 4470 struct mlx5_ifc_query_encap_header_out_bits { 4471 u8 status[0x8]; 4472 u8 reserved_at_8[0x18]; 4473 4474 u8 syndrome[0x20]; 4475 4476 u8 reserved_at_40[0xa0]; 4477 4478 struct mlx5_ifc_encap_header_in_bits encap_header[0]; 4479 }; 4480 4481 struct mlx5_ifc_query_encap_header_in_bits { 4482 u8 opcode[0x10]; 4483 u8 reserved_at_10[0x10]; 4484 4485 u8 reserved_at_20[0x10]; 4486 u8 op_mod[0x10]; 4487 4488 u8 encap_id[0x20]; 4489 4490 u8 reserved_at_60[0xa0]; 4491 }; 4492 4493 struct mlx5_ifc_alloc_encap_header_out_bits { 4494 u8 status[0x8]; 4495 u8 reserved_at_8[0x18]; 4496 4497 u8 syndrome[0x20]; 4498 4499 u8 encap_id[0x20]; 4500 4501 u8 reserved_at_60[0x20]; 4502 }; 4503 4504 struct mlx5_ifc_alloc_encap_header_in_bits { 4505 u8 opcode[0x10]; 4506 u8 reserved_at_10[0x10]; 4507 4508 u8 reserved_at_20[0x10]; 4509 u8 op_mod[0x10]; 4510 4511 u8 reserved_at_40[0xa0]; 4512 4513 struct mlx5_ifc_encap_header_in_bits encap_header; 4514 }; 4515 4516 struct mlx5_ifc_dealloc_encap_header_out_bits { 4517 u8 status[0x8]; 4518 u8 reserved_at_8[0x18]; 4519 4520 u8 syndrome[0x20]; 4521 4522 u8 reserved_at_40[0x40]; 4523 }; 4524 4525 struct mlx5_ifc_dealloc_encap_header_in_bits { 4526 u8 opcode[0x10]; 4527 u8 reserved_at_10[0x10]; 4528 4529 u8 reserved_20[0x10]; 4530 u8 op_mod[0x10]; 4531 4532 u8 encap_id[0x20]; 4533 4534 u8 reserved_60[0x20]; 4535 }; 4536 4537 struct mlx5_ifc_query_dct_out_bits { 4538 u8 status[0x8]; 4539 u8 reserved_at_8[0x18]; 4540 4541 u8 syndrome[0x20]; 4542 4543 u8 reserved_at_40[0x40]; 4544 4545 struct mlx5_ifc_dctc_bits dct_context_entry; 4546 4547 u8 reserved_at_280[0x180]; 4548 }; 4549 4550 struct mlx5_ifc_query_dct_in_bits { 4551 u8 opcode[0x10]; 4552 u8 reserved_at_10[0x10]; 4553 4554 u8 reserved_at_20[0x10]; 4555 u8 op_mod[0x10]; 4556 4557 u8 reserved_at_40[0x8]; 4558 u8 dctn[0x18]; 4559 4560 u8 reserved_at_60[0x20]; 4561 }; 4562 4563 struct mlx5_ifc_query_cq_out_bits { 4564 u8 status[0x8]; 4565 u8 reserved_at_8[0x18]; 4566 4567 u8 syndrome[0x20]; 4568 4569 u8 reserved_at_40[0x40]; 4570 4571 struct mlx5_ifc_cqc_bits cq_context; 4572 4573 u8 reserved_at_280[0x600]; 4574 4575 u8 pas[0][0x40]; 4576 }; 4577 4578 struct mlx5_ifc_query_cq_in_bits { 4579 u8 opcode[0x10]; 4580 u8 reserved_at_10[0x10]; 4581 4582 u8 reserved_at_20[0x10]; 4583 u8 op_mod[0x10]; 4584 4585 u8 reserved_at_40[0x8]; 4586 u8 cqn[0x18]; 4587 4588 u8 reserved_at_60[0x20]; 4589 }; 4590 4591 struct mlx5_ifc_query_cong_status_out_bits { 4592 u8 status[0x8]; 4593 u8 reserved_at_8[0x18]; 4594 4595 u8 syndrome[0x20]; 4596 4597 u8 reserved_at_40[0x20]; 4598 4599 u8 enable[0x1]; 4600 u8 tag_enable[0x1]; 4601 u8 reserved_at_62[0x1e]; 4602 }; 4603 4604 struct mlx5_ifc_query_cong_status_in_bits { 4605 u8 opcode[0x10]; 4606 u8 reserved_at_10[0x10]; 4607 4608 u8 reserved_at_20[0x10]; 4609 u8 op_mod[0x10]; 4610 4611 u8 reserved_at_40[0x18]; 4612 u8 priority[0x4]; 4613 u8 cong_protocol[0x4]; 4614 4615 u8 reserved_at_60[0x20]; 4616 }; 4617 4618 struct mlx5_ifc_query_cong_statistics_out_bits { 4619 u8 status[0x8]; 4620 u8 reserved_at_8[0x18]; 4621 4622 u8 syndrome[0x20]; 4623 4624 u8 reserved_at_40[0x40]; 4625 4626 u8 cur_flows[0x20]; 4627 4628 u8 sum_flows[0x20]; 4629 4630 u8 cnp_ignored_high[0x20]; 4631 4632 u8 cnp_ignored_low[0x20]; 4633 4634 u8 cnp_handled_high[0x20]; 4635 4636 u8 cnp_handled_low[0x20]; 4637 4638 u8 reserved_at_140[0x100]; 4639 4640 u8 time_stamp_high[0x20]; 4641 4642 u8 time_stamp_low[0x20]; 4643 4644 u8 accumulators_period[0x20]; 4645 4646 u8 ecn_marked_roce_packets_high[0x20]; 4647 4648 u8 ecn_marked_roce_packets_low[0x20]; 4649 4650 u8 cnps_sent_high[0x20]; 4651 4652 u8 cnps_sent_low[0x20]; 4653 4654 u8 reserved_at_320[0x560]; 4655 }; 4656 4657 struct mlx5_ifc_query_cong_statistics_in_bits { 4658 u8 opcode[0x10]; 4659 u8 reserved_at_10[0x10]; 4660 4661 u8 reserved_at_20[0x10]; 4662 u8 op_mod[0x10]; 4663 4664 u8 clear[0x1]; 4665 u8 reserved_at_41[0x1f]; 4666 4667 u8 reserved_at_60[0x20]; 4668 }; 4669 4670 struct mlx5_ifc_query_cong_params_out_bits { 4671 u8 status[0x8]; 4672 u8 reserved_at_8[0x18]; 4673 4674 u8 syndrome[0x20]; 4675 4676 u8 reserved_at_40[0x40]; 4677 4678 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 4679 }; 4680 4681 struct mlx5_ifc_query_cong_params_in_bits { 4682 u8 opcode[0x10]; 4683 u8 reserved_at_10[0x10]; 4684 4685 u8 reserved_at_20[0x10]; 4686 u8 op_mod[0x10]; 4687 4688 u8 reserved_at_40[0x1c]; 4689 u8 cong_protocol[0x4]; 4690 4691 u8 reserved_at_60[0x20]; 4692 }; 4693 4694 struct mlx5_ifc_query_adapter_out_bits { 4695 u8 status[0x8]; 4696 u8 reserved_at_8[0x18]; 4697 4698 u8 syndrome[0x20]; 4699 4700 u8 reserved_at_40[0x40]; 4701 4702 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct; 4703 }; 4704 4705 struct mlx5_ifc_query_adapter_in_bits { 4706 u8 opcode[0x10]; 4707 u8 reserved_at_10[0x10]; 4708 4709 u8 reserved_at_20[0x10]; 4710 u8 op_mod[0x10]; 4711 4712 u8 reserved_at_40[0x40]; 4713 }; 4714 4715 struct mlx5_ifc_qp_2rst_out_bits { 4716 u8 status[0x8]; 4717 u8 reserved_at_8[0x18]; 4718 4719 u8 syndrome[0x20]; 4720 4721 u8 reserved_at_40[0x40]; 4722 }; 4723 4724 struct mlx5_ifc_qp_2rst_in_bits { 4725 u8 opcode[0x10]; 4726 u8 reserved_at_10[0x10]; 4727 4728 u8 reserved_at_20[0x10]; 4729 u8 op_mod[0x10]; 4730 4731 u8 reserved_at_40[0x8]; 4732 u8 qpn[0x18]; 4733 4734 u8 reserved_at_60[0x20]; 4735 }; 4736 4737 struct mlx5_ifc_qp_2err_out_bits { 4738 u8 status[0x8]; 4739 u8 reserved_at_8[0x18]; 4740 4741 u8 syndrome[0x20]; 4742 4743 u8 reserved_at_40[0x40]; 4744 }; 4745 4746 struct mlx5_ifc_qp_2err_in_bits { 4747 u8 opcode[0x10]; 4748 u8 reserved_at_10[0x10]; 4749 4750 u8 reserved_at_20[0x10]; 4751 u8 op_mod[0x10]; 4752 4753 u8 reserved_at_40[0x8]; 4754 u8 qpn[0x18]; 4755 4756 u8 reserved_at_60[0x20]; 4757 }; 4758 4759 struct mlx5_ifc_page_fault_resume_out_bits { 4760 u8 status[0x8]; 4761 u8 reserved_at_8[0x18]; 4762 4763 u8 syndrome[0x20]; 4764 4765 u8 reserved_at_40[0x40]; 4766 }; 4767 4768 struct mlx5_ifc_page_fault_resume_in_bits { 4769 u8 opcode[0x10]; 4770 u8 reserved_at_10[0x10]; 4771 4772 u8 reserved_at_20[0x10]; 4773 u8 op_mod[0x10]; 4774 4775 u8 error[0x1]; 4776 u8 reserved_at_41[0x4]; 4777 u8 page_fault_type[0x3]; 4778 u8 wq_number[0x18]; 4779 4780 u8 reserved_at_60[0x8]; 4781 u8 token[0x18]; 4782 }; 4783 4784 struct mlx5_ifc_nop_out_bits { 4785 u8 status[0x8]; 4786 u8 reserved_at_8[0x18]; 4787 4788 u8 syndrome[0x20]; 4789 4790 u8 reserved_at_40[0x40]; 4791 }; 4792 4793 struct mlx5_ifc_nop_in_bits { 4794 u8 opcode[0x10]; 4795 u8 reserved_at_10[0x10]; 4796 4797 u8 reserved_at_20[0x10]; 4798 u8 op_mod[0x10]; 4799 4800 u8 reserved_at_40[0x40]; 4801 }; 4802 4803 struct mlx5_ifc_modify_vport_state_out_bits { 4804 u8 status[0x8]; 4805 u8 reserved_at_8[0x18]; 4806 4807 u8 syndrome[0x20]; 4808 4809 u8 reserved_at_40[0x40]; 4810 }; 4811 4812 struct mlx5_ifc_modify_vport_state_in_bits { 4813 u8 opcode[0x10]; 4814 u8 reserved_at_10[0x10]; 4815 4816 u8 reserved_at_20[0x10]; 4817 u8 op_mod[0x10]; 4818 4819 u8 other_vport[0x1]; 4820 u8 reserved_at_41[0xf]; 4821 u8 vport_number[0x10]; 4822 4823 u8 reserved_at_60[0x18]; 4824 u8 admin_state[0x4]; 4825 u8 reserved_at_7c[0x4]; 4826 }; 4827 4828 struct mlx5_ifc_modify_tis_out_bits { 4829 u8 status[0x8]; 4830 u8 reserved_at_8[0x18]; 4831 4832 u8 syndrome[0x20]; 4833 4834 u8 reserved_at_40[0x40]; 4835 }; 4836 4837 struct mlx5_ifc_modify_tis_bitmask_bits { 4838 u8 reserved_at_0[0x20]; 4839 4840 u8 reserved_at_20[0x1d]; 4841 u8 lag_tx_port_affinity[0x1]; 4842 u8 strict_lag_tx_port_affinity[0x1]; 4843 u8 prio[0x1]; 4844 }; 4845 4846 struct mlx5_ifc_modify_tis_in_bits { 4847 u8 opcode[0x10]; 4848 u8 reserved_at_10[0x10]; 4849 4850 u8 reserved_at_20[0x10]; 4851 u8 op_mod[0x10]; 4852 4853 u8 reserved_at_40[0x8]; 4854 u8 tisn[0x18]; 4855 4856 u8 reserved_at_60[0x20]; 4857 4858 struct mlx5_ifc_modify_tis_bitmask_bits bitmask; 4859 4860 u8 reserved_at_c0[0x40]; 4861 4862 struct mlx5_ifc_tisc_bits ctx; 4863 }; 4864 4865 struct mlx5_ifc_modify_tir_bitmask_bits { 4866 u8 reserved_at_0[0x20]; 4867 4868 u8 reserved_at_20[0x1b]; 4869 u8 self_lb_en[0x1]; 4870 u8 reserved_at_3c[0x1]; 4871 u8 hash[0x1]; 4872 u8 reserved_at_3e[0x1]; 4873 u8 lro[0x1]; 4874 }; 4875 4876 struct mlx5_ifc_modify_tir_out_bits { 4877 u8 status[0x8]; 4878 u8 reserved_at_8[0x18]; 4879 4880 u8 syndrome[0x20]; 4881 4882 u8 reserved_at_40[0x40]; 4883 }; 4884 4885 struct mlx5_ifc_modify_tir_in_bits { 4886 u8 opcode[0x10]; 4887 u8 reserved_at_10[0x10]; 4888 4889 u8 reserved_at_20[0x10]; 4890 u8 op_mod[0x10]; 4891 4892 u8 reserved_at_40[0x8]; 4893 u8 tirn[0x18]; 4894 4895 u8 reserved_at_60[0x20]; 4896 4897 struct mlx5_ifc_modify_tir_bitmask_bits bitmask; 4898 4899 u8 reserved_at_c0[0x40]; 4900 4901 struct mlx5_ifc_tirc_bits ctx; 4902 }; 4903 4904 struct mlx5_ifc_modify_sq_out_bits { 4905 u8 status[0x8]; 4906 u8 reserved_at_8[0x18]; 4907 4908 u8 syndrome[0x20]; 4909 4910 u8 reserved_at_40[0x40]; 4911 }; 4912 4913 struct mlx5_ifc_modify_sq_in_bits { 4914 u8 opcode[0x10]; 4915 u8 reserved_at_10[0x10]; 4916 4917 u8 reserved_at_20[0x10]; 4918 u8 op_mod[0x10]; 4919 4920 u8 sq_state[0x4]; 4921 u8 reserved_at_44[0x4]; 4922 u8 sqn[0x18]; 4923 4924 u8 reserved_at_60[0x20]; 4925 4926 u8 modify_bitmask[0x40]; 4927 4928 u8 reserved_at_c0[0x40]; 4929 4930 struct mlx5_ifc_sqc_bits ctx; 4931 }; 4932 4933 struct mlx5_ifc_modify_scheduling_element_out_bits { 4934 u8 status[0x8]; 4935 u8 reserved_at_8[0x18]; 4936 4937 u8 syndrome[0x20]; 4938 4939 u8 reserved_at_40[0x1c0]; 4940 }; 4941 4942 enum { 4943 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1, 4944 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2, 4945 }; 4946 4947 struct mlx5_ifc_modify_scheduling_element_in_bits { 4948 u8 opcode[0x10]; 4949 u8 reserved_at_10[0x10]; 4950 4951 u8 reserved_at_20[0x10]; 4952 u8 op_mod[0x10]; 4953 4954 u8 scheduling_hierarchy[0x8]; 4955 u8 reserved_at_48[0x18]; 4956 4957 u8 scheduling_element_id[0x20]; 4958 4959 u8 reserved_at_80[0x20]; 4960 4961 u8 modify_bitmask[0x20]; 4962 4963 u8 reserved_at_c0[0x40]; 4964 4965 struct mlx5_ifc_scheduling_context_bits scheduling_context; 4966 4967 u8 reserved_at_300[0x100]; 4968 }; 4969 4970 struct mlx5_ifc_modify_rqt_out_bits { 4971 u8 status[0x8]; 4972 u8 reserved_at_8[0x18]; 4973 4974 u8 syndrome[0x20]; 4975 4976 u8 reserved_at_40[0x40]; 4977 }; 4978 4979 struct mlx5_ifc_rqt_bitmask_bits { 4980 u8 reserved_at_0[0x20]; 4981 4982 u8 reserved_at_20[0x1f]; 4983 u8 rqn_list[0x1]; 4984 }; 4985 4986 struct mlx5_ifc_modify_rqt_in_bits { 4987 u8 opcode[0x10]; 4988 u8 reserved_at_10[0x10]; 4989 4990 u8 reserved_at_20[0x10]; 4991 u8 op_mod[0x10]; 4992 4993 u8 reserved_at_40[0x8]; 4994 u8 rqtn[0x18]; 4995 4996 u8 reserved_at_60[0x20]; 4997 4998 struct mlx5_ifc_rqt_bitmask_bits bitmask; 4999 5000 u8 reserved_at_c0[0x40]; 5001 5002 struct mlx5_ifc_rqtc_bits ctx; 5003 }; 5004 5005 struct mlx5_ifc_modify_rq_out_bits { 5006 u8 status[0x8]; 5007 u8 reserved_at_8[0x18]; 5008 5009 u8 syndrome[0x20]; 5010 5011 u8 reserved_at_40[0x40]; 5012 }; 5013 5014 enum { 5015 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1, 5016 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3, 5017 }; 5018 5019 struct mlx5_ifc_modify_rq_in_bits { 5020 u8 opcode[0x10]; 5021 u8 reserved_at_10[0x10]; 5022 5023 u8 reserved_at_20[0x10]; 5024 u8 op_mod[0x10]; 5025 5026 u8 rq_state[0x4]; 5027 u8 reserved_at_44[0x4]; 5028 u8 rqn[0x18]; 5029 5030 u8 reserved_at_60[0x20]; 5031 5032 u8 modify_bitmask[0x40]; 5033 5034 u8 reserved_at_c0[0x40]; 5035 5036 struct mlx5_ifc_rqc_bits ctx; 5037 }; 5038 5039 struct mlx5_ifc_modify_rmp_out_bits { 5040 u8 status[0x8]; 5041 u8 reserved_at_8[0x18]; 5042 5043 u8 syndrome[0x20]; 5044 5045 u8 reserved_at_40[0x40]; 5046 }; 5047 5048 struct mlx5_ifc_rmp_bitmask_bits { 5049 u8 reserved_at_0[0x20]; 5050 5051 u8 reserved_at_20[0x1f]; 5052 u8 lwm[0x1]; 5053 }; 5054 5055 struct mlx5_ifc_modify_rmp_in_bits { 5056 u8 opcode[0x10]; 5057 u8 reserved_at_10[0x10]; 5058 5059 u8 reserved_at_20[0x10]; 5060 u8 op_mod[0x10]; 5061 5062 u8 rmp_state[0x4]; 5063 u8 reserved_at_44[0x4]; 5064 u8 rmpn[0x18]; 5065 5066 u8 reserved_at_60[0x20]; 5067 5068 struct mlx5_ifc_rmp_bitmask_bits bitmask; 5069 5070 u8 reserved_at_c0[0x40]; 5071 5072 struct mlx5_ifc_rmpc_bits ctx; 5073 }; 5074 5075 struct mlx5_ifc_modify_nic_vport_context_out_bits { 5076 u8 status[0x8]; 5077 u8 reserved_at_8[0x18]; 5078 5079 u8 syndrome[0x20]; 5080 5081 u8 reserved_at_40[0x40]; 5082 }; 5083 5084 struct mlx5_ifc_modify_nic_vport_field_select_bits { 5085 u8 reserved_at_0[0x16]; 5086 u8 node_guid[0x1]; 5087 u8 port_guid[0x1]; 5088 u8 min_inline[0x1]; 5089 u8 mtu[0x1]; 5090 u8 change_event[0x1]; 5091 u8 promisc[0x1]; 5092 u8 permanent_address[0x1]; 5093 u8 addresses_list[0x1]; 5094 u8 roce_en[0x1]; 5095 u8 reserved_at_1f[0x1]; 5096 }; 5097 5098 struct mlx5_ifc_modify_nic_vport_context_in_bits { 5099 u8 opcode[0x10]; 5100 u8 reserved_at_10[0x10]; 5101 5102 u8 reserved_at_20[0x10]; 5103 u8 op_mod[0x10]; 5104 5105 u8 other_vport[0x1]; 5106 u8 reserved_at_41[0xf]; 5107 u8 vport_number[0x10]; 5108 5109 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select; 5110 5111 u8 reserved_at_80[0x780]; 5112 5113 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 5114 }; 5115 5116 struct mlx5_ifc_modify_hca_vport_context_out_bits { 5117 u8 status[0x8]; 5118 u8 reserved_at_8[0x18]; 5119 5120 u8 syndrome[0x20]; 5121 5122 u8 reserved_at_40[0x40]; 5123 }; 5124 5125 struct mlx5_ifc_modify_hca_vport_context_in_bits { 5126 u8 opcode[0x10]; 5127 u8 reserved_at_10[0x10]; 5128 5129 u8 reserved_at_20[0x10]; 5130 u8 op_mod[0x10]; 5131 5132 u8 other_vport[0x1]; 5133 u8 reserved_at_41[0xb]; 5134 u8 port_num[0x4]; 5135 u8 vport_number[0x10]; 5136 5137 u8 reserved_at_60[0x20]; 5138 5139 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 5140 }; 5141 5142 struct mlx5_ifc_modify_cq_out_bits { 5143 u8 status[0x8]; 5144 u8 reserved_at_8[0x18]; 5145 5146 u8 syndrome[0x20]; 5147 5148 u8 reserved_at_40[0x40]; 5149 }; 5150 5151 enum { 5152 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0, 5153 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1, 5154 }; 5155 5156 struct mlx5_ifc_modify_cq_in_bits { 5157 u8 opcode[0x10]; 5158 u8 reserved_at_10[0x10]; 5159 5160 u8 reserved_at_20[0x10]; 5161 u8 op_mod[0x10]; 5162 5163 u8 reserved_at_40[0x8]; 5164 u8 cqn[0x18]; 5165 5166 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select; 5167 5168 struct mlx5_ifc_cqc_bits cq_context; 5169 5170 u8 reserved_at_280[0x600]; 5171 5172 u8 pas[0][0x40]; 5173 }; 5174 5175 struct mlx5_ifc_modify_cong_status_out_bits { 5176 u8 status[0x8]; 5177 u8 reserved_at_8[0x18]; 5178 5179 u8 syndrome[0x20]; 5180 5181 u8 reserved_at_40[0x40]; 5182 }; 5183 5184 struct mlx5_ifc_modify_cong_status_in_bits { 5185 u8 opcode[0x10]; 5186 u8 reserved_at_10[0x10]; 5187 5188 u8 reserved_at_20[0x10]; 5189 u8 op_mod[0x10]; 5190 5191 u8 reserved_at_40[0x18]; 5192 u8 priority[0x4]; 5193 u8 cong_protocol[0x4]; 5194 5195 u8 enable[0x1]; 5196 u8 tag_enable[0x1]; 5197 u8 reserved_at_62[0x1e]; 5198 }; 5199 5200 struct mlx5_ifc_modify_cong_params_out_bits { 5201 u8 status[0x8]; 5202 u8 reserved_at_8[0x18]; 5203 5204 u8 syndrome[0x20]; 5205 5206 u8 reserved_at_40[0x40]; 5207 }; 5208 5209 struct mlx5_ifc_modify_cong_params_in_bits { 5210 u8 opcode[0x10]; 5211 u8 reserved_at_10[0x10]; 5212 5213 u8 reserved_at_20[0x10]; 5214 u8 op_mod[0x10]; 5215 5216 u8 reserved_at_40[0x1c]; 5217 u8 cong_protocol[0x4]; 5218 5219 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select; 5220 5221 u8 reserved_at_80[0x80]; 5222 5223 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 5224 }; 5225 5226 struct mlx5_ifc_manage_pages_out_bits { 5227 u8 status[0x8]; 5228 u8 reserved_at_8[0x18]; 5229 5230 u8 syndrome[0x20]; 5231 5232 u8 output_num_entries[0x20]; 5233 5234 u8 reserved_at_60[0x20]; 5235 5236 u8 pas[0][0x40]; 5237 }; 5238 5239 enum { 5240 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL = 0x0, 5241 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS = 0x1, 5242 MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES = 0x2, 5243 }; 5244 5245 struct mlx5_ifc_manage_pages_in_bits { 5246 u8 opcode[0x10]; 5247 u8 reserved_at_10[0x10]; 5248 5249 u8 reserved_at_20[0x10]; 5250 u8 op_mod[0x10]; 5251 5252 u8 reserved_at_40[0x10]; 5253 u8 function_id[0x10]; 5254 5255 u8 input_num_entries[0x20]; 5256 5257 u8 pas[0][0x40]; 5258 }; 5259 5260 struct mlx5_ifc_mad_ifc_out_bits { 5261 u8 status[0x8]; 5262 u8 reserved_at_8[0x18]; 5263 5264 u8 syndrome[0x20]; 5265 5266 u8 reserved_at_40[0x40]; 5267 5268 u8 response_mad_packet[256][0x8]; 5269 }; 5270 5271 struct mlx5_ifc_mad_ifc_in_bits { 5272 u8 opcode[0x10]; 5273 u8 reserved_at_10[0x10]; 5274 5275 u8 reserved_at_20[0x10]; 5276 u8 op_mod[0x10]; 5277 5278 u8 remote_lid[0x10]; 5279 u8 reserved_at_50[0x8]; 5280 u8 port[0x8]; 5281 5282 u8 reserved_at_60[0x20]; 5283 5284 u8 mad[256][0x8]; 5285 }; 5286 5287 struct mlx5_ifc_init_hca_out_bits { 5288 u8 status[0x8]; 5289 u8 reserved_at_8[0x18]; 5290 5291 u8 syndrome[0x20]; 5292 5293 u8 reserved_at_40[0x40]; 5294 }; 5295 5296 struct mlx5_ifc_init_hca_in_bits { 5297 u8 opcode[0x10]; 5298 u8 reserved_at_10[0x10]; 5299 5300 u8 reserved_at_20[0x10]; 5301 u8 op_mod[0x10]; 5302 5303 u8 reserved_at_40[0x40]; 5304 }; 5305 5306 struct mlx5_ifc_init2rtr_qp_out_bits { 5307 u8 status[0x8]; 5308 u8 reserved_at_8[0x18]; 5309 5310 u8 syndrome[0x20]; 5311 5312 u8 reserved_at_40[0x40]; 5313 }; 5314 5315 struct mlx5_ifc_init2rtr_qp_in_bits { 5316 u8 opcode[0x10]; 5317 u8 reserved_at_10[0x10]; 5318 5319 u8 reserved_at_20[0x10]; 5320 u8 op_mod[0x10]; 5321 5322 u8 reserved_at_40[0x8]; 5323 u8 qpn[0x18]; 5324 5325 u8 reserved_at_60[0x20]; 5326 5327 u8 opt_param_mask[0x20]; 5328 5329 u8 reserved_at_a0[0x20]; 5330 5331 struct mlx5_ifc_qpc_bits qpc; 5332 5333 u8 reserved_at_800[0x80]; 5334 }; 5335 5336 struct mlx5_ifc_init2init_qp_out_bits { 5337 u8 status[0x8]; 5338 u8 reserved_at_8[0x18]; 5339 5340 u8 syndrome[0x20]; 5341 5342 u8 reserved_at_40[0x40]; 5343 }; 5344 5345 struct mlx5_ifc_init2init_qp_in_bits { 5346 u8 opcode[0x10]; 5347 u8 reserved_at_10[0x10]; 5348 5349 u8 reserved_at_20[0x10]; 5350 u8 op_mod[0x10]; 5351 5352 u8 reserved_at_40[0x8]; 5353 u8 qpn[0x18]; 5354 5355 u8 reserved_at_60[0x20]; 5356 5357 u8 opt_param_mask[0x20]; 5358 5359 u8 reserved_at_a0[0x20]; 5360 5361 struct mlx5_ifc_qpc_bits qpc; 5362 5363 u8 reserved_at_800[0x80]; 5364 }; 5365 5366 struct mlx5_ifc_get_dropped_packet_log_out_bits { 5367 u8 status[0x8]; 5368 u8 reserved_at_8[0x18]; 5369 5370 u8 syndrome[0x20]; 5371 5372 u8 reserved_at_40[0x40]; 5373 5374 u8 packet_headers_log[128][0x8]; 5375 5376 u8 packet_syndrome[64][0x8]; 5377 }; 5378 5379 struct mlx5_ifc_get_dropped_packet_log_in_bits { 5380 u8 opcode[0x10]; 5381 u8 reserved_at_10[0x10]; 5382 5383 u8 reserved_at_20[0x10]; 5384 u8 op_mod[0x10]; 5385 5386 u8 reserved_at_40[0x40]; 5387 }; 5388 5389 struct mlx5_ifc_gen_eqe_in_bits { 5390 u8 opcode[0x10]; 5391 u8 reserved_at_10[0x10]; 5392 5393 u8 reserved_at_20[0x10]; 5394 u8 op_mod[0x10]; 5395 5396 u8 reserved_at_40[0x18]; 5397 u8 eq_number[0x8]; 5398 5399 u8 reserved_at_60[0x20]; 5400 5401 u8 eqe[64][0x8]; 5402 }; 5403 5404 struct mlx5_ifc_gen_eq_out_bits { 5405 u8 status[0x8]; 5406 u8 reserved_at_8[0x18]; 5407 5408 u8 syndrome[0x20]; 5409 5410 u8 reserved_at_40[0x40]; 5411 }; 5412 5413 struct mlx5_ifc_enable_hca_out_bits { 5414 u8 status[0x8]; 5415 u8 reserved_at_8[0x18]; 5416 5417 u8 syndrome[0x20]; 5418 5419 u8 reserved_at_40[0x20]; 5420 }; 5421 5422 struct mlx5_ifc_enable_hca_in_bits { 5423 u8 opcode[0x10]; 5424 u8 reserved_at_10[0x10]; 5425 5426 u8 reserved_at_20[0x10]; 5427 u8 op_mod[0x10]; 5428 5429 u8 reserved_at_40[0x10]; 5430 u8 function_id[0x10]; 5431 5432 u8 reserved_at_60[0x20]; 5433 }; 5434 5435 struct mlx5_ifc_drain_dct_out_bits { 5436 u8 status[0x8]; 5437 u8 reserved_at_8[0x18]; 5438 5439 u8 syndrome[0x20]; 5440 5441 u8 reserved_at_40[0x40]; 5442 }; 5443 5444 struct mlx5_ifc_drain_dct_in_bits { 5445 u8 opcode[0x10]; 5446 u8 reserved_at_10[0x10]; 5447 5448 u8 reserved_at_20[0x10]; 5449 u8 op_mod[0x10]; 5450 5451 u8 reserved_at_40[0x8]; 5452 u8 dctn[0x18]; 5453 5454 u8 reserved_at_60[0x20]; 5455 }; 5456 5457 struct mlx5_ifc_disable_hca_out_bits { 5458 u8 status[0x8]; 5459 u8 reserved_at_8[0x18]; 5460 5461 u8 syndrome[0x20]; 5462 5463 u8 reserved_at_40[0x20]; 5464 }; 5465 5466 struct mlx5_ifc_disable_hca_in_bits { 5467 u8 opcode[0x10]; 5468 u8 reserved_at_10[0x10]; 5469 5470 u8 reserved_at_20[0x10]; 5471 u8 op_mod[0x10]; 5472 5473 u8 reserved_at_40[0x10]; 5474 u8 function_id[0x10]; 5475 5476 u8 reserved_at_60[0x20]; 5477 }; 5478 5479 struct mlx5_ifc_detach_from_mcg_out_bits { 5480 u8 status[0x8]; 5481 u8 reserved_at_8[0x18]; 5482 5483 u8 syndrome[0x20]; 5484 5485 u8 reserved_at_40[0x40]; 5486 }; 5487 5488 struct mlx5_ifc_detach_from_mcg_in_bits { 5489 u8 opcode[0x10]; 5490 u8 reserved_at_10[0x10]; 5491 5492 u8 reserved_at_20[0x10]; 5493 u8 op_mod[0x10]; 5494 5495 u8 reserved_at_40[0x8]; 5496 u8 qpn[0x18]; 5497 5498 u8 reserved_at_60[0x20]; 5499 5500 u8 multicast_gid[16][0x8]; 5501 }; 5502 5503 struct mlx5_ifc_destroy_xrq_out_bits { 5504 u8 status[0x8]; 5505 u8 reserved_at_8[0x18]; 5506 5507 u8 syndrome[0x20]; 5508 5509 u8 reserved_at_40[0x40]; 5510 }; 5511 5512 struct mlx5_ifc_destroy_xrq_in_bits { 5513 u8 opcode[0x10]; 5514 u8 reserved_at_10[0x10]; 5515 5516 u8 reserved_at_20[0x10]; 5517 u8 op_mod[0x10]; 5518 5519 u8 reserved_at_40[0x8]; 5520 u8 xrqn[0x18]; 5521 5522 u8 reserved_at_60[0x20]; 5523 }; 5524 5525 struct mlx5_ifc_destroy_xrc_srq_out_bits { 5526 u8 status[0x8]; 5527 u8 reserved_at_8[0x18]; 5528 5529 u8 syndrome[0x20]; 5530 5531 u8 reserved_at_40[0x40]; 5532 }; 5533 5534 struct mlx5_ifc_destroy_xrc_srq_in_bits { 5535 u8 opcode[0x10]; 5536 u8 reserved_at_10[0x10]; 5537 5538 u8 reserved_at_20[0x10]; 5539 u8 op_mod[0x10]; 5540 5541 u8 reserved_at_40[0x8]; 5542 u8 xrc_srqn[0x18]; 5543 5544 u8 reserved_at_60[0x20]; 5545 }; 5546 5547 struct mlx5_ifc_destroy_tis_out_bits { 5548 u8 status[0x8]; 5549 u8 reserved_at_8[0x18]; 5550 5551 u8 syndrome[0x20]; 5552 5553 u8 reserved_at_40[0x40]; 5554 }; 5555 5556 struct mlx5_ifc_destroy_tis_in_bits { 5557 u8 opcode[0x10]; 5558 u8 reserved_at_10[0x10]; 5559 5560 u8 reserved_at_20[0x10]; 5561 u8 op_mod[0x10]; 5562 5563 u8 reserved_at_40[0x8]; 5564 u8 tisn[0x18]; 5565 5566 u8 reserved_at_60[0x20]; 5567 }; 5568 5569 struct mlx5_ifc_destroy_tir_out_bits { 5570 u8 status[0x8]; 5571 u8 reserved_at_8[0x18]; 5572 5573 u8 syndrome[0x20]; 5574 5575 u8 reserved_at_40[0x40]; 5576 }; 5577 5578 struct mlx5_ifc_destroy_tir_in_bits { 5579 u8 opcode[0x10]; 5580 u8 reserved_at_10[0x10]; 5581 5582 u8 reserved_at_20[0x10]; 5583 u8 op_mod[0x10]; 5584 5585 u8 reserved_at_40[0x8]; 5586 u8 tirn[0x18]; 5587 5588 u8 reserved_at_60[0x20]; 5589 }; 5590 5591 struct mlx5_ifc_destroy_srq_out_bits { 5592 u8 status[0x8]; 5593 u8 reserved_at_8[0x18]; 5594 5595 u8 syndrome[0x20]; 5596 5597 u8 reserved_at_40[0x40]; 5598 }; 5599 5600 struct mlx5_ifc_destroy_srq_in_bits { 5601 u8 opcode[0x10]; 5602 u8 reserved_at_10[0x10]; 5603 5604 u8 reserved_at_20[0x10]; 5605 u8 op_mod[0x10]; 5606 5607 u8 reserved_at_40[0x8]; 5608 u8 srqn[0x18]; 5609 5610 u8 reserved_at_60[0x20]; 5611 }; 5612 5613 struct mlx5_ifc_destroy_sq_out_bits { 5614 u8 status[0x8]; 5615 u8 reserved_at_8[0x18]; 5616 5617 u8 syndrome[0x20]; 5618 5619 u8 reserved_at_40[0x40]; 5620 }; 5621 5622 struct mlx5_ifc_destroy_sq_in_bits { 5623 u8 opcode[0x10]; 5624 u8 reserved_at_10[0x10]; 5625 5626 u8 reserved_at_20[0x10]; 5627 u8 op_mod[0x10]; 5628 5629 u8 reserved_at_40[0x8]; 5630 u8 sqn[0x18]; 5631 5632 u8 reserved_at_60[0x20]; 5633 }; 5634 5635 struct mlx5_ifc_destroy_scheduling_element_out_bits { 5636 u8 status[0x8]; 5637 u8 reserved_at_8[0x18]; 5638 5639 u8 syndrome[0x20]; 5640 5641 u8 reserved_at_40[0x1c0]; 5642 }; 5643 5644 struct mlx5_ifc_destroy_scheduling_element_in_bits { 5645 u8 opcode[0x10]; 5646 u8 reserved_at_10[0x10]; 5647 5648 u8 reserved_at_20[0x10]; 5649 u8 op_mod[0x10]; 5650 5651 u8 scheduling_hierarchy[0x8]; 5652 u8 reserved_at_48[0x18]; 5653 5654 u8 scheduling_element_id[0x20]; 5655 5656 u8 reserved_at_80[0x180]; 5657 }; 5658 5659 struct mlx5_ifc_destroy_rqt_out_bits { 5660 u8 status[0x8]; 5661 u8 reserved_at_8[0x18]; 5662 5663 u8 syndrome[0x20]; 5664 5665 u8 reserved_at_40[0x40]; 5666 }; 5667 5668 struct mlx5_ifc_destroy_rqt_in_bits { 5669 u8 opcode[0x10]; 5670 u8 reserved_at_10[0x10]; 5671 5672 u8 reserved_at_20[0x10]; 5673 u8 op_mod[0x10]; 5674 5675 u8 reserved_at_40[0x8]; 5676 u8 rqtn[0x18]; 5677 5678 u8 reserved_at_60[0x20]; 5679 }; 5680 5681 struct mlx5_ifc_destroy_rq_out_bits { 5682 u8 status[0x8]; 5683 u8 reserved_at_8[0x18]; 5684 5685 u8 syndrome[0x20]; 5686 5687 u8 reserved_at_40[0x40]; 5688 }; 5689 5690 struct mlx5_ifc_destroy_rq_in_bits { 5691 u8 opcode[0x10]; 5692 u8 reserved_at_10[0x10]; 5693 5694 u8 reserved_at_20[0x10]; 5695 u8 op_mod[0x10]; 5696 5697 u8 reserved_at_40[0x8]; 5698 u8 rqn[0x18]; 5699 5700 u8 reserved_at_60[0x20]; 5701 }; 5702 5703 struct mlx5_ifc_destroy_rmp_out_bits { 5704 u8 status[0x8]; 5705 u8 reserved_at_8[0x18]; 5706 5707 u8 syndrome[0x20]; 5708 5709 u8 reserved_at_40[0x40]; 5710 }; 5711 5712 struct mlx5_ifc_destroy_rmp_in_bits { 5713 u8 opcode[0x10]; 5714 u8 reserved_at_10[0x10]; 5715 5716 u8 reserved_at_20[0x10]; 5717 u8 op_mod[0x10]; 5718 5719 u8 reserved_at_40[0x8]; 5720 u8 rmpn[0x18]; 5721 5722 u8 reserved_at_60[0x20]; 5723 }; 5724 5725 struct mlx5_ifc_destroy_qp_out_bits { 5726 u8 status[0x8]; 5727 u8 reserved_at_8[0x18]; 5728 5729 u8 syndrome[0x20]; 5730 5731 u8 reserved_at_40[0x40]; 5732 }; 5733 5734 struct mlx5_ifc_destroy_qp_in_bits { 5735 u8 opcode[0x10]; 5736 u8 reserved_at_10[0x10]; 5737 5738 u8 reserved_at_20[0x10]; 5739 u8 op_mod[0x10]; 5740 5741 u8 reserved_at_40[0x8]; 5742 u8 qpn[0x18]; 5743 5744 u8 reserved_at_60[0x20]; 5745 }; 5746 5747 struct mlx5_ifc_destroy_psv_out_bits { 5748 u8 status[0x8]; 5749 u8 reserved_at_8[0x18]; 5750 5751 u8 syndrome[0x20]; 5752 5753 u8 reserved_at_40[0x40]; 5754 }; 5755 5756 struct mlx5_ifc_destroy_psv_in_bits { 5757 u8 opcode[0x10]; 5758 u8 reserved_at_10[0x10]; 5759 5760 u8 reserved_at_20[0x10]; 5761 u8 op_mod[0x10]; 5762 5763 u8 reserved_at_40[0x8]; 5764 u8 psvn[0x18]; 5765 5766 u8 reserved_at_60[0x20]; 5767 }; 5768 5769 struct mlx5_ifc_destroy_mkey_out_bits { 5770 u8 status[0x8]; 5771 u8 reserved_at_8[0x18]; 5772 5773 u8 syndrome[0x20]; 5774 5775 u8 reserved_at_40[0x40]; 5776 }; 5777 5778 struct mlx5_ifc_destroy_mkey_in_bits { 5779 u8 opcode[0x10]; 5780 u8 reserved_at_10[0x10]; 5781 5782 u8 reserved_at_20[0x10]; 5783 u8 op_mod[0x10]; 5784 5785 u8 reserved_at_40[0x8]; 5786 u8 mkey_index[0x18]; 5787 5788 u8 reserved_at_60[0x20]; 5789 }; 5790 5791 struct mlx5_ifc_destroy_flow_table_out_bits { 5792 u8 status[0x8]; 5793 u8 reserved_at_8[0x18]; 5794 5795 u8 syndrome[0x20]; 5796 5797 u8 reserved_at_40[0x40]; 5798 }; 5799 5800 struct mlx5_ifc_destroy_flow_table_in_bits { 5801 u8 opcode[0x10]; 5802 u8 reserved_at_10[0x10]; 5803 5804 u8 reserved_at_20[0x10]; 5805 u8 op_mod[0x10]; 5806 5807 u8 other_vport[0x1]; 5808 u8 reserved_at_41[0xf]; 5809 u8 vport_number[0x10]; 5810 5811 u8 reserved_at_60[0x20]; 5812 5813 u8 table_type[0x8]; 5814 u8 reserved_at_88[0x18]; 5815 5816 u8 reserved_at_a0[0x8]; 5817 u8 table_id[0x18]; 5818 5819 u8 reserved_at_c0[0x140]; 5820 }; 5821 5822 struct mlx5_ifc_destroy_flow_group_out_bits { 5823 u8 status[0x8]; 5824 u8 reserved_at_8[0x18]; 5825 5826 u8 syndrome[0x20]; 5827 5828 u8 reserved_at_40[0x40]; 5829 }; 5830 5831 struct mlx5_ifc_destroy_flow_group_in_bits { 5832 u8 opcode[0x10]; 5833 u8 reserved_at_10[0x10]; 5834 5835 u8 reserved_at_20[0x10]; 5836 u8 op_mod[0x10]; 5837 5838 u8 other_vport[0x1]; 5839 u8 reserved_at_41[0xf]; 5840 u8 vport_number[0x10]; 5841 5842 u8 reserved_at_60[0x20]; 5843 5844 u8 table_type[0x8]; 5845 u8 reserved_at_88[0x18]; 5846 5847 u8 reserved_at_a0[0x8]; 5848 u8 table_id[0x18]; 5849 5850 u8 group_id[0x20]; 5851 5852 u8 reserved_at_e0[0x120]; 5853 }; 5854 5855 struct mlx5_ifc_destroy_eq_out_bits { 5856 u8 status[0x8]; 5857 u8 reserved_at_8[0x18]; 5858 5859 u8 syndrome[0x20]; 5860 5861 u8 reserved_at_40[0x40]; 5862 }; 5863 5864 struct mlx5_ifc_destroy_eq_in_bits { 5865 u8 opcode[0x10]; 5866 u8 reserved_at_10[0x10]; 5867 5868 u8 reserved_at_20[0x10]; 5869 u8 op_mod[0x10]; 5870 5871 u8 reserved_at_40[0x18]; 5872 u8 eq_number[0x8]; 5873 5874 u8 reserved_at_60[0x20]; 5875 }; 5876 5877 struct mlx5_ifc_destroy_dct_out_bits { 5878 u8 status[0x8]; 5879 u8 reserved_at_8[0x18]; 5880 5881 u8 syndrome[0x20]; 5882 5883 u8 reserved_at_40[0x40]; 5884 }; 5885 5886 struct mlx5_ifc_destroy_dct_in_bits { 5887 u8 opcode[0x10]; 5888 u8 reserved_at_10[0x10]; 5889 5890 u8 reserved_at_20[0x10]; 5891 u8 op_mod[0x10]; 5892 5893 u8 reserved_at_40[0x8]; 5894 u8 dctn[0x18]; 5895 5896 u8 reserved_at_60[0x20]; 5897 }; 5898 5899 struct mlx5_ifc_destroy_cq_out_bits { 5900 u8 status[0x8]; 5901 u8 reserved_at_8[0x18]; 5902 5903 u8 syndrome[0x20]; 5904 5905 u8 reserved_at_40[0x40]; 5906 }; 5907 5908 struct mlx5_ifc_destroy_cq_in_bits { 5909 u8 opcode[0x10]; 5910 u8 reserved_at_10[0x10]; 5911 5912 u8 reserved_at_20[0x10]; 5913 u8 op_mod[0x10]; 5914 5915 u8 reserved_at_40[0x8]; 5916 u8 cqn[0x18]; 5917 5918 u8 reserved_at_60[0x20]; 5919 }; 5920 5921 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits { 5922 u8 status[0x8]; 5923 u8 reserved_at_8[0x18]; 5924 5925 u8 syndrome[0x20]; 5926 5927 u8 reserved_at_40[0x40]; 5928 }; 5929 5930 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits { 5931 u8 opcode[0x10]; 5932 u8 reserved_at_10[0x10]; 5933 5934 u8 reserved_at_20[0x10]; 5935 u8 op_mod[0x10]; 5936 5937 u8 reserved_at_40[0x20]; 5938 5939 u8 reserved_at_60[0x10]; 5940 u8 vxlan_udp_port[0x10]; 5941 }; 5942 5943 struct mlx5_ifc_delete_l2_table_entry_out_bits { 5944 u8 status[0x8]; 5945 u8 reserved_at_8[0x18]; 5946 5947 u8 syndrome[0x20]; 5948 5949 u8 reserved_at_40[0x40]; 5950 }; 5951 5952 struct mlx5_ifc_delete_l2_table_entry_in_bits { 5953 u8 opcode[0x10]; 5954 u8 reserved_at_10[0x10]; 5955 5956 u8 reserved_at_20[0x10]; 5957 u8 op_mod[0x10]; 5958 5959 u8 reserved_at_40[0x60]; 5960 5961 u8 reserved_at_a0[0x8]; 5962 u8 table_index[0x18]; 5963 5964 u8 reserved_at_c0[0x140]; 5965 }; 5966 5967 struct mlx5_ifc_delete_fte_out_bits { 5968 u8 status[0x8]; 5969 u8 reserved_at_8[0x18]; 5970 5971 u8 syndrome[0x20]; 5972 5973 u8 reserved_at_40[0x40]; 5974 }; 5975 5976 struct mlx5_ifc_delete_fte_in_bits { 5977 u8 opcode[0x10]; 5978 u8 reserved_at_10[0x10]; 5979 5980 u8 reserved_at_20[0x10]; 5981 u8 op_mod[0x10]; 5982 5983 u8 other_vport[0x1]; 5984 u8 reserved_at_41[0xf]; 5985 u8 vport_number[0x10]; 5986 5987 u8 reserved_at_60[0x20]; 5988 5989 u8 table_type[0x8]; 5990 u8 reserved_at_88[0x18]; 5991 5992 u8 reserved_at_a0[0x8]; 5993 u8 table_id[0x18]; 5994 5995 u8 reserved_at_c0[0x40]; 5996 5997 u8 flow_index[0x20]; 5998 5999 u8 reserved_at_120[0xe0]; 6000 }; 6001 6002 struct mlx5_ifc_dealloc_xrcd_out_bits { 6003 u8 status[0x8]; 6004 u8 reserved_at_8[0x18]; 6005 6006 u8 syndrome[0x20]; 6007 6008 u8 reserved_at_40[0x40]; 6009 }; 6010 6011 struct mlx5_ifc_dealloc_xrcd_in_bits { 6012 u8 opcode[0x10]; 6013 u8 reserved_at_10[0x10]; 6014 6015 u8 reserved_at_20[0x10]; 6016 u8 op_mod[0x10]; 6017 6018 u8 reserved_at_40[0x8]; 6019 u8 xrcd[0x18]; 6020 6021 u8 reserved_at_60[0x20]; 6022 }; 6023 6024 struct mlx5_ifc_dealloc_uar_out_bits { 6025 u8 status[0x8]; 6026 u8 reserved_at_8[0x18]; 6027 6028 u8 syndrome[0x20]; 6029 6030 u8 reserved_at_40[0x40]; 6031 }; 6032 6033 struct mlx5_ifc_dealloc_uar_in_bits { 6034 u8 opcode[0x10]; 6035 u8 reserved_at_10[0x10]; 6036 6037 u8 reserved_at_20[0x10]; 6038 u8 op_mod[0x10]; 6039 6040 u8 reserved_at_40[0x8]; 6041 u8 uar[0x18]; 6042 6043 u8 reserved_at_60[0x20]; 6044 }; 6045 6046 struct mlx5_ifc_dealloc_transport_domain_out_bits { 6047 u8 status[0x8]; 6048 u8 reserved_at_8[0x18]; 6049 6050 u8 syndrome[0x20]; 6051 6052 u8 reserved_at_40[0x40]; 6053 }; 6054 6055 struct mlx5_ifc_dealloc_transport_domain_in_bits { 6056 u8 opcode[0x10]; 6057 u8 reserved_at_10[0x10]; 6058 6059 u8 reserved_at_20[0x10]; 6060 u8 op_mod[0x10]; 6061 6062 u8 reserved_at_40[0x8]; 6063 u8 transport_domain[0x18]; 6064 6065 u8 reserved_at_60[0x20]; 6066 }; 6067 6068 struct mlx5_ifc_dealloc_q_counter_out_bits { 6069 u8 status[0x8]; 6070 u8 reserved_at_8[0x18]; 6071 6072 u8 syndrome[0x20]; 6073 6074 u8 reserved_at_40[0x40]; 6075 }; 6076 6077 struct mlx5_ifc_dealloc_q_counter_in_bits { 6078 u8 opcode[0x10]; 6079 u8 reserved_at_10[0x10]; 6080 6081 u8 reserved_at_20[0x10]; 6082 u8 op_mod[0x10]; 6083 6084 u8 reserved_at_40[0x18]; 6085 u8 counter_set_id[0x8]; 6086 6087 u8 reserved_at_60[0x20]; 6088 }; 6089 6090 struct mlx5_ifc_dealloc_pd_out_bits { 6091 u8 status[0x8]; 6092 u8 reserved_at_8[0x18]; 6093 6094 u8 syndrome[0x20]; 6095 6096 u8 reserved_at_40[0x40]; 6097 }; 6098 6099 struct mlx5_ifc_dealloc_pd_in_bits { 6100 u8 opcode[0x10]; 6101 u8 reserved_at_10[0x10]; 6102 6103 u8 reserved_at_20[0x10]; 6104 u8 op_mod[0x10]; 6105 6106 u8 reserved_at_40[0x8]; 6107 u8 pd[0x18]; 6108 6109 u8 reserved_at_60[0x20]; 6110 }; 6111 6112 struct mlx5_ifc_dealloc_flow_counter_out_bits { 6113 u8 status[0x8]; 6114 u8 reserved_at_8[0x18]; 6115 6116 u8 syndrome[0x20]; 6117 6118 u8 reserved_at_40[0x40]; 6119 }; 6120 6121 struct mlx5_ifc_dealloc_flow_counter_in_bits { 6122 u8 opcode[0x10]; 6123 u8 reserved_at_10[0x10]; 6124 6125 u8 reserved_at_20[0x10]; 6126 u8 op_mod[0x10]; 6127 6128 u8 reserved_at_40[0x10]; 6129 u8 flow_counter_id[0x10]; 6130 6131 u8 reserved_at_60[0x20]; 6132 }; 6133 6134 struct mlx5_ifc_create_xrq_out_bits { 6135 u8 status[0x8]; 6136 u8 reserved_at_8[0x18]; 6137 6138 u8 syndrome[0x20]; 6139 6140 u8 reserved_at_40[0x8]; 6141 u8 xrqn[0x18]; 6142 6143 u8 reserved_at_60[0x20]; 6144 }; 6145 6146 struct mlx5_ifc_create_xrq_in_bits { 6147 u8 opcode[0x10]; 6148 u8 reserved_at_10[0x10]; 6149 6150 u8 reserved_at_20[0x10]; 6151 u8 op_mod[0x10]; 6152 6153 u8 reserved_at_40[0x40]; 6154 6155 struct mlx5_ifc_xrqc_bits xrq_context; 6156 }; 6157 6158 struct mlx5_ifc_create_xrc_srq_out_bits { 6159 u8 status[0x8]; 6160 u8 reserved_at_8[0x18]; 6161 6162 u8 syndrome[0x20]; 6163 6164 u8 reserved_at_40[0x8]; 6165 u8 xrc_srqn[0x18]; 6166 6167 u8 reserved_at_60[0x20]; 6168 }; 6169 6170 struct mlx5_ifc_create_xrc_srq_in_bits { 6171 u8 opcode[0x10]; 6172 u8 reserved_at_10[0x10]; 6173 6174 u8 reserved_at_20[0x10]; 6175 u8 op_mod[0x10]; 6176 6177 u8 reserved_at_40[0x40]; 6178 6179 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 6180 6181 u8 reserved_at_280[0x600]; 6182 6183 u8 pas[0][0x40]; 6184 }; 6185 6186 struct mlx5_ifc_create_tis_out_bits { 6187 u8 status[0x8]; 6188 u8 reserved_at_8[0x18]; 6189 6190 u8 syndrome[0x20]; 6191 6192 u8 reserved_at_40[0x8]; 6193 u8 tisn[0x18]; 6194 6195 u8 reserved_at_60[0x20]; 6196 }; 6197 6198 struct mlx5_ifc_create_tis_in_bits { 6199 u8 opcode[0x10]; 6200 u8 reserved_at_10[0x10]; 6201 6202 u8 reserved_at_20[0x10]; 6203 u8 op_mod[0x10]; 6204 6205 u8 reserved_at_40[0xc0]; 6206 6207 struct mlx5_ifc_tisc_bits ctx; 6208 }; 6209 6210 struct mlx5_ifc_create_tir_out_bits { 6211 u8 status[0x8]; 6212 u8 reserved_at_8[0x18]; 6213 6214 u8 syndrome[0x20]; 6215 6216 u8 reserved_at_40[0x8]; 6217 u8 tirn[0x18]; 6218 6219 u8 reserved_at_60[0x20]; 6220 }; 6221 6222 struct mlx5_ifc_create_tir_in_bits { 6223 u8 opcode[0x10]; 6224 u8 reserved_at_10[0x10]; 6225 6226 u8 reserved_at_20[0x10]; 6227 u8 op_mod[0x10]; 6228 6229 u8 reserved_at_40[0xc0]; 6230 6231 struct mlx5_ifc_tirc_bits ctx; 6232 }; 6233 6234 struct mlx5_ifc_create_srq_out_bits { 6235 u8 status[0x8]; 6236 u8 reserved_at_8[0x18]; 6237 6238 u8 syndrome[0x20]; 6239 6240 u8 reserved_at_40[0x8]; 6241 u8 srqn[0x18]; 6242 6243 u8 reserved_at_60[0x20]; 6244 }; 6245 6246 struct mlx5_ifc_create_srq_in_bits { 6247 u8 opcode[0x10]; 6248 u8 reserved_at_10[0x10]; 6249 6250 u8 reserved_at_20[0x10]; 6251 u8 op_mod[0x10]; 6252 6253 u8 reserved_at_40[0x40]; 6254 6255 struct mlx5_ifc_srqc_bits srq_context_entry; 6256 6257 u8 reserved_at_280[0x600]; 6258 6259 u8 pas[0][0x40]; 6260 }; 6261 6262 struct mlx5_ifc_create_sq_out_bits { 6263 u8 status[0x8]; 6264 u8 reserved_at_8[0x18]; 6265 6266 u8 syndrome[0x20]; 6267 6268 u8 reserved_at_40[0x8]; 6269 u8 sqn[0x18]; 6270 6271 u8 reserved_at_60[0x20]; 6272 }; 6273 6274 struct mlx5_ifc_create_sq_in_bits { 6275 u8 opcode[0x10]; 6276 u8 reserved_at_10[0x10]; 6277 6278 u8 reserved_at_20[0x10]; 6279 u8 op_mod[0x10]; 6280 6281 u8 reserved_at_40[0xc0]; 6282 6283 struct mlx5_ifc_sqc_bits ctx; 6284 }; 6285 6286 struct mlx5_ifc_create_scheduling_element_out_bits { 6287 u8 status[0x8]; 6288 u8 reserved_at_8[0x18]; 6289 6290 u8 syndrome[0x20]; 6291 6292 u8 reserved_at_40[0x40]; 6293 6294 u8 scheduling_element_id[0x20]; 6295 6296 u8 reserved_at_a0[0x160]; 6297 }; 6298 6299 struct mlx5_ifc_create_scheduling_element_in_bits { 6300 u8 opcode[0x10]; 6301 u8 reserved_at_10[0x10]; 6302 6303 u8 reserved_at_20[0x10]; 6304 u8 op_mod[0x10]; 6305 6306 u8 scheduling_hierarchy[0x8]; 6307 u8 reserved_at_48[0x18]; 6308 6309 u8 reserved_at_60[0xa0]; 6310 6311 struct mlx5_ifc_scheduling_context_bits scheduling_context; 6312 6313 u8 reserved_at_300[0x100]; 6314 }; 6315 6316 struct mlx5_ifc_create_rqt_out_bits { 6317 u8 status[0x8]; 6318 u8 reserved_at_8[0x18]; 6319 6320 u8 syndrome[0x20]; 6321 6322 u8 reserved_at_40[0x8]; 6323 u8 rqtn[0x18]; 6324 6325 u8 reserved_at_60[0x20]; 6326 }; 6327 6328 struct mlx5_ifc_create_rqt_in_bits { 6329 u8 opcode[0x10]; 6330 u8 reserved_at_10[0x10]; 6331 6332 u8 reserved_at_20[0x10]; 6333 u8 op_mod[0x10]; 6334 6335 u8 reserved_at_40[0xc0]; 6336 6337 struct mlx5_ifc_rqtc_bits rqt_context; 6338 }; 6339 6340 struct mlx5_ifc_create_rq_out_bits { 6341 u8 status[0x8]; 6342 u8 reserved_at_8[0x18]; 6343 6344 u8 syndrome[0x20]; 6345 6346 u8 reserved_at_40[0x8]; 6347 u8 rqn[0x18]; 6348 6349 u8 reserved_at_60[0x20]; 6350 }; 6351 6352 struct mlx5_ifc_create_rq_in_bits { 6353 u8 opcode[0x10]; 6354 u8 reserved_at_10[0x10]; 6355 6356 u8 reserved_at_20[0x10]; 6357 u8 op_mod[0x10]; 6358 6359 u8 reserved_at_40[0xc0]; 6360 6361 struct mlx5_ifc_rqc_bits ctx; 6362 }; 6363 6364 struct mlx5_ifc_create_rmp_out_bits { 6365 u8 status[0x8]; 6366 u8 reserved_at_8[0x18]; 6367 6368 u8 syndrome[0x20]; 6369 6370 u8 reserved_at_40[0x8]; 6371 u8 rmpn[0x18]; 6372 6373 u8 reserved_at_60[0x20]; 6374 }; 6375 6376 struct mlx5_ifc_create_rmp_in_bits { 6377 u8 opcode[0x10]; 6378 u8 reserved_at_10[0x10]; 6379 6380 u8 reserved_at_20[0x10]; 6381 u8 op_mod[0x10]; 6382 6383 u8 reserved_at_40[0xc0]; 6384 6385 struct mlx5_ifc_rmpc_bits ctx; 6386 }; 6387 6388 struct mlx5_ifc_create_qp_out_bits { 6389 u8 status[0x8]; 6390 u8 reserved_at_8[0x18]; 6391 6392 u8 syndrome[0x20]; 6393 6394 u8 reserved_at_40[0x8]; 6395 u8 qpn[0x18]; 6396 6397 u8 reserved_at_60[0x20]; 6398 }; 6399 6400 struct mlx5_ifc_create_qp_in_bits { 6401 u8 opcode[0x10]; 6402 u8 reserved_at_10[0x10]; 6403 6404 u8 reserved_at_20[0x10]; 6405 u8 op_mod[0x10]; 6406 6407 u8 reserved_at_40[0x40]; 6408 6409 u8 opt_param_mask[0x20]; 6410 6411 u8 reserved_at_a0[0x20]; 6412 6413 struct mlx5_ifc_qpc_bits qpc; 6414 6415 u8 reserved_at_800[0x80]; 6416 6417 u8 pas[0][0x40]; 6418 }; 6419 6420 struct mlx5_ifc_create_psv_out_bits { 6421 u8 status[0x8]; 6422 u8 reserved_at_8[0x18]; 6423 6424 u8 syndrome[0x20]; 6425 6426 u8 reserved_at_40[0x40]; 6427 6428 u8 reserved_at_80[0x8]; 6429 u8 psv0_index[0x18]; 6430 6431 u8 reserved_at_a0[0x8]; 6432 u8 psv1_index[0x18]; 6433 6434 u8 reserved_at_c0[0x8]; 6435 u8 psv2_index[0x18]; 6436 6437 u8 reserved_at_e0[0x8]; 6438 u8 psv3_index[0x18]; 6439 }; 6440 6441 struct mlx5_ifc_create_psv_in_bits { 6442 u8 opcode[0x10]; 6443 u8 reserved_at_10[0x10]; 6444 6445 u8 reserved_at_20[0x10]; 6446 u8 op_mod[0x10]; 6447 6448 u8 num_psv[0x4]; 6449 u8 reserved_at_44[0x4]; 6450 u8 pd[0x18]; 6451 6452 u8 reserved_at_60[0x20]; 6453 }; 6454 6455 struct mlx5_ifc_create_mkey_out_bits { 6456 u8 status[0x8]; 6457 u8 reserved_at_8[0x18]; 6458 6459 u8 syndrome[0x20]; 6460 6461 u8 reserved_at_40[0x8]; 6462 u8 mkey_index[0x18]; 6463 6464 u8 reserved_at_60[0x20]; 6465 }; 6466 6467 struct mlx5_ifc_create_mkey_in_bits { 6468 u8 opcode[0x10]; 6469 u8 reserved_at_10[0x10]; 6470 6471 u8 reserved_at_20[0x10]; 6472 u8 op_mod[0x10]; 6473 6474 u8 reserved_at_40[0x20]; 6475 6476 u8 pg_access[0x1]; 6477 u8 reserved_at_61[0x1f]; 6478 6479 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 6480 6481 u8 reserved_at_280[0x80]; 6482 6483 u8 translations_octword_actual_size[0x20]; 6484 6485 u8 reserved_at_320[0x560]; 6486 6487 u8 klm_pas_mtt[0][0x20]; 6488 }; 6489 6490 struct mlx5_ifc_create_flow_table_out_bits { 6491 u8 status[0x8]; 6492 u8 reserved_at_8[0x18]; 6493 6494 u8 syndrome[0x20]; 6495 6496 u8 reserved_at_40[0x8]; 6497 u8 table_id[0x18]; 6498 6499 u8 reserved_at_60[0x20]; 6500 }; 6501 6502 struct mlx5_ifc_create_flow_table_in_bits { 6503 u8 opcode[0x10]; 6504 u8 reserved_at_10[0x10]; 6505 6506 u8 reserved_at_20[0x10]; 6507 u8 op_mod[0x10]; 6508 6509 u8 other_vport[0x1]; 6510 u8 reserved_at_41[0xf]; 6511 u8 vport_number[0x10]; 6512 6513 u8 reserved_at_60[0x20]; 6514 6515 u8 table_type[0x8]; 6516 u8 reserved_at_88[0x18]; 6517 6518 u8 reserved_at_a0[0x20]; 6519 6520 u8 encap_en[0x1]; 6521 u8 decap_en[0x1]; 6522 u8 reserved_at_c2[0x2]; 6523 u8 table_miss_mode[0x4]; 6524 u8 level[0x8]; 6525 u8 reserved_at_d0[0x8]; 6526 u8 log_size[0x8]; 6527 6528 u8 reserved_at_e0[0x8]; 6529 u8 table_miss_id[0x18]; 6530 6531 u8 reserved_at_100[0x8]; 6532 u8 lag_master_next_table_id[0x18]; 6533 6534 u8 reserved_at_120[0x80]; 6535 }; 6536 6537 struct mlx5_ifc_create_flow_group_out_bits { 6538 u8 status[0x8]; 6539 u8 reserved_at_8[0x18]; 6540 6541 u8 syndrome[0x20]; 6542 6543 u8 reserved_at_40[0x8]; 6544 u8 group_id[0x18]; 6545 6546 u8 reserved_at_60[0x20]; 6547 }; 6548 6549 enum { 6550 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 6551 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 6552 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 6553 }; 6554 6555 struct mlx5_ifc_create_flow_group_in_bits { 6556 u8 opcode[0x10]; 6557 u8 reserved_at_10[0x10]; 6558 6559 u8 reserved_at_20[0x10]; 6560 u8 op_mod[0x10]; 6561 6562 u8 other_vport[0x1]; 6563 u8 reserved_at_41[0xf]; 6564 u8 vport_number[0x10]; 6565 6566 u8 reserved_at_60[0x20]; 6567 6568 u8 table_type[0x8]; 6569 u8 reserved_at_88[0x18]; 6570 6571 u8 reserved_at_a0[0x8]; 6572 u8 table_id[0x18]; 6573 6574 u8 reserved_at_c0[0x20]; 6575 6576 u8 start_flow_index[0x20]; 6577 6578 u8 reserved_at_100[0x20]; 6579 6580 u8 end_flow_index[0x20]; 6581 6582 u8 reserved_at_140[0xa0]; 6583 6584 u8 reserved_at_1e0[0x18]; 6585 u8 match_criteria_enable[0x8]; 6586 6587 struct mlx5_ifc_fte_match_param_bits match_criteria; 6588 6589 u8 reserved_at_1200[0xe00]; 6590 }; 6591 6592 struct mlx5_ifc_create_eq_out_bits { 6593 u8 status[0x8]; 6594 u8 reserved_at_8[0x18]; 6595 6596 u8 syndrome[0x20]; 6597 6598 u8 reserved_at_40[0x18]; 6599 u8 eq_number[0x8]; 6600 6601 u8 reserved_at_60[0x20]; 6602 }; 6603 6604 struct mlx5_ifc_create_eq_in_bits { 6605 u8 opcode[0x10]; 6606 u8 reserved_at_10[0x10]; 6607 6608 u8 reserved_at_20[0x10]; 6609 u8 op_mod[0x10]; 6610 6611 u8 reserved_at_40[0x40]; 6612 6613 struct mlx5_ifc_eqc_bits eq_context_entry; 6614 6615 u8 reserved_at_280[0x40]; 6616 6617 u8 event_bitmask[0x40]; 6618 6619 u8 reserved_at_300[0x580]; 6620 6621 u8 pas[0][0x40]; 6622 }; 6623 6624 struct mlx5_ifc_create_dct_out_bits { 6625 u8 status[0x8]; 6626 u8 reserved_at_8[0x18]; 6627 6628 u8 syndrome[0x20]; 6629 6630 u8 reserved_at_40[0x8]; 6631 u8 dctn[0x18]; 6632 6633 u8 reserved_at_60[0x20]; 6634 }; 6635 6636 struct mlx5_ifc_create_dct_in_bits { 6637 u8 opcode[0x10]; 6638 u8 reserved_at_10[0x10]; 6639 6640 u8 reserved_at_20[0x10]; 6641 u8 op_mod[0x10]; 6642 6643 u8 reserved_at_40[0x40]; 6644 6645 struct mlx5_ifc_dctc_bits dct_context_entry; 6646 6647 u8 reserved_at_280[0x180]; 6648 }; 6649 6650 struct mlx5_ifc_create_cq_out_bits { 6651 u8 status[0x8]; 6652 u8 reserved_at_8[0x18]; 6653 6654 u8 syndrome[0x20]; 6655 6656 u8 reserved_at_40[0x8]; 6657 u8 cqn[0x18]; 6658 6659 u8 reserved_at_60[0x20]; 6660 }; 6661 6662 struct mlx5_ifc_create_cq_in_bits { 6663 u8 opcode[0x10]; 6664 u8 reserved_at_10[0x10]; 6665 6666 u8 reserved_at_20[0x10]; 6667 u8 op_mod[0x10]; 6668 6669 u8 reserved_at_40[0x40]; 6670 6671 struct mlx5_ifc_cqc_bits cq_context; 6672 6673 u8 reserved_at_280[0x600]; 6674 6675 u8 pas[0][0x40]; 6676 }; 6677 6678 struct mlx5_ifc_config_int_moderation_out_bits { 6679 u8 status[0x8]; 6680 u8 reserved_at_8[0x18]; 6681 6682 u8 syndrome[0x20]; 6683 6684 u8 reserved_at_40[0x4]; 6685 u8 min_delay[0xc]; 6686 u8 int_vector[0x10]; 6687 6688 u8 reserved_at_60[0x20]; 6689 }; 6690 6691 enum { 6692 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0, 6693 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1, 6694 }; 6695 6696 struct mlx5_ifc_config_int_moderation_in_bits { 6697 u8 opcode[0x10]; 6698 u8 reserved_at_10[0x10]; 6699 6700 u8 reserved_at_20[0x10]; 6701 u8 op_mod[0x10]; 6702 6703 u8 reserved_at_40[0x4]; 6704 u8 min_delay[0xc]; 6705 u8 int_vector[0x10]; 6706 6707 u8 reserved_at_60[0x20]; 6708 }; 6709 6710 struct mlx5_ifc_attach_to_mcg_out_bits { 6711 u8 status[0x8]; 6712 u8 reserved_at_8[0x18]; 6713 6714 u8 syndrome[0x20]; 6715 6716 u8 reserved_at_40[0x40]; 6717 }; 6718 6719 struct mlx5_ifc_attach_to_mcg_in_bits { 6720 u8 opcode[0x10]; 6721 u8 reserved_at_10[0x10]; 6722 6723 u8 reserved_at_20[0x10]; 6724 u8 op_mod[0x10]; 6725 6726 u8 reserved_at_40[0x8]; 6727 u8 qpn[0x18]; 6728 6729 u8 reserved_at_60[0x20]; 6730 6731 u8 multicast_gid[16][0x8]; 6732 }; 6733 6734 struct mlx5_ifc_arm_xrq_out_bits { 6735 u8 status[0x8]; 6736 u8 reserved_at_8[0x18]; 6737 6738 u8 syndrome[0x20]; 6739 6740 u8 reserved_at_40[0x40]; 6741 }; 6742 6743 struct mlx5_ifc_arm_xrq_in_bits { 6744 u8 opcode[0x10]; 6745 u8 reserved_at_10[0x10]; 6746 6747 u8 reserved_at_20[0x10]; 6748 u8 op_mod[0x10]; 6749 6750 u8 reserved_at_40[0x8]; 6751 u8 xrqn[0x18]; 6752 6753 u8 reserved_at_60[0x10]; 6754 u8 lwm[0x10]; 6755 }; 6756 6757 struct mlx5_ifc_arm_xrc_srq_out_bits { 6758 u8 status[0x8]; 6759 u8 reserved_at_8[0x18]; 6760 6761 u8 syndrome[0x20]; 6762 6763 u8 reserved_at_40[0x40]; 6764 }; 6765 6766 enum { 6767 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1, 6768 }; 6769 6770 struct mlx5_ifc_arm_xrc_srq_in_bits { 6771 u8 opcode[0x10]; 6772 u8 reserved_at_10[0x10]; 6773 6774 u8 reserved_at_20[0x10]; 6775 u8 op_mod[0x10]; 6776 6777 u8 reserved_at_40[0x8]; 6778 u8 xrc_srqn[0x18]; 6779 6780 u8 reserved_at_60[0x10]; 6781 u8 lwm[0x10]; 6782 }; 6783 6784 struct mlx5_ifc_arm_rq_out_bits { 6785 u8 status[0x8]; 6786 u8 reserved_at_8[0x18]; 6787 6788 u8 syndrome[0x20]; 6789 6790 u8 reserved_at_40[0x40]; 6791 }; 6792 6793 enum { 6794 MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1, 6795 MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2, 6796 }; 6797 6798 struct mlx5_ifc_arm_rq_in_bits { 6799 u8 opcode[0x10]; 6800 u8 reserved_at_10[0x10]; 6801 6802 u8 reserved_at_20[0x10]; 6803 u8 op_mod[0x10]; 6804 6805 u8 reserved_at_40[0x8]; 6806 u8 srq_number[0x18]; 6807 6808 u8 reserved_at_60[0x10]; 6809 u8 lwm[0x10]; 6810 }; 6811 6812 struct mlx5_ifc_arm_dct_out_bits { 6813 u8 status[0x8]; 6814 u8 reserved_at_8[0x18]; 6815 6816 u8 syndrome[0x20]; 6817 6818 u8 reserved_at_40[0x40]; 6819 }; 6820 6821 struct mlx5_ifc_arm_dct_in_bits { 6822 u8 opcode[0x10]; 6823 u8 reserved_at_10[0x10]; 6824 6825 u8 reserved_at_20[0x10]; 6826 u8 op_mod[0x10]; 6827 6828 u8 reserved_at_40[0x8]; 6829 u8 dct_number[0x18]; 6830 6831 u8 reserved_at_60[0x20]; 6832 }; 6833 6834 struct mlx5_ifc_alloc_xrcd_out_bits { 6835 u8 status[0x8]; 6836 u8 reserved_at_8[0x18]; 6837 6838 u8 syndrome[0x20]; 6839 6840 u8 reserved_at_40[0x8]; 6841 u8 xrcd[0x18]; 6842 6843 u8 reserved_at_60[0x20]; 6844 }; 6845 6846 struct mlx5_ifc_alloc_xrcd_in_bits { 6847 u8 opcode[0x10]; 6848 u8 reserved_at_10[0x10]; 6849 6850 u8 reserved_at_20[0x10]; 6851 u8 op_mod[0x10]; 6852 6853 u8 reserved_at_40[0x40]; 6854 }; 6855 6856 struct mlx5_ifc_alloc_uar_out_bits { 6857 u8 status[0x8]; 6858 u8 reserved_at_8[0x18]; 6859 6860 u8 syndrome[0x20]; 6861 6862 u8 reserved_at_40[0x8]; 6863 u8 uar[0x18]; 6864 6865 u8 reserved_at_60[0x20]; 6866 }; 6867 6868 struct mlx5_ifc_alloc_uar_in_bits { 6869 u8 opcode[0x10]; 6870 u8 reserved_at_10[0x10]; 6871 6872 u8 reserved_at_20[0x10]; 6873 u8 op_mod[0x10]; 6874 6875 u8 reserved_at_40[0x40]; 6876 }; 6877 6878 struct mlx5_ifc_alloc_transport_domain_out_bits { 6879 u8 status[0x8]; 6880 u8 reserved_at_8[0x18]; 6881 6882 u8 syndrome[0x20]; 6883 6884 u8 reserved_at_40[0x8]; 6885 u8 transport_domain[0x18]; 6886 6887 u8 reserved_at_60[0x20]; 6888 }; 6889 6890 struct mlx5_ifc_alloc_transport_domain_in_bits { 6891 u8 opcode[0x10]; 6892 u8 reserved_at_10[0x10]; 6893 6894 u8 reserved_at_20[0x10]; 6895 u8 op_mod[0x10]; 6896 6897 u8 reserved_at_40[0x40]; 6898 }; 6899 6900 struct mlx5_ifc_alloc_q_counter_out_bits { 6901 u8 status[0x8]; 6902 u8 reserved_at_8[0x18]; 6903 6904 u8 syndrome[0x20]; 6905 6906 u8 reserved_at_40[0x18]; 6907 u8 counter_set_id[0x8]; 6908 6909 u8 reserved_at_60[0x20]; 6910 }; 6911 6912 struct mlx5_ifc_alloc_q_counter_in_bits { 6913 u8 opcode[0x10]; 6914 u8 reserved_at_10[0x10]; 6915 6916 u8 reserved_at_20[0x10]; 6917 u8 op_mod[0x10]; 6918 6919 u8 reserved_at_40[0x40]; 6920 }; 6921 6922 struct mlx5_ifc_alloc_pd_out_bits { 6923 u8 status[0x8]; 6924 u8 reserved_at_8[0x18]; 6925 6926 u8 syndrome[0x20]; 6927 6928 u8 reserved_at_40[0x8]; 6929 u8 pd[0x18]; 6930 6931 u8 reserved_at_60[0x20]; 6932 }; 6933 6934 struct mlx5_ifc_alloc_pd_in_bits { 6935 u8 opcode[0x10]; 6936 u8 reserved_at_10[0x10]; 6937 6938 u8 reserved_at_20[0x10]; 6939 u8 op_mod[0x10]; 6940 6941 u8 reserved_at_40[0x40]; 6942 }; 6943 6944 struct mlx5_ifc_alloc_flow_counter_out_bits { 6945 u8 status[0x8]; 6946 u8 reserved_at_8[0x18]; 6947 6948 u8 syndrome[0x20]; 6949 6950 u8 reserved_at_40[0x10]; 6951 u8 flow_counter_id[0x10]; 6952 6953 u8 reserved_at_60[0x20]; 6954 }; 6955 6956 struct mlx5_ifc_alloc_flow_counter_in_bits { 6957 u8 opcode[0x10]; 6958 u8 reserved_at_10[0x10]; 6959 6960 u8 reserved_at_20[0x10]; 6961 u8 op_mod[0x10]; 6962 6963 u8 reserved_at_40[0x40]; 6964 }; 6965 6966 struct mlx5_ifc_add_vxlan_udp_dport_out_bits { 6967 u8 status[0x8]; 6968 u8 reserved_at_8[0x18]; 6969 6970 u8 syndrome[0x20]; 6971 6972 u8 reserved_at_40[0x40]; 6973 }; 6974 6975 struct mlx5_ifc_add_vxlan_udp_dport_in_bits { 6976 u8 opcode[0x10]; 6977 u8 reserved_at_10[0x10]; 6978 6979 u8 reserved_at_20[0x10]; 6980 u8 op_mod[0x10]; 6981 6982 u8 reserved_at_40[0x20]; 6983 6984 u8 reserved_at_60[0x10]; 6985 u8 vxlan_udp_port[0x10]; 6986 }; 6987 6988 struct mlx5_ifc_set_rate_limit_out_bits { 6989 u8 status[0x8]; 6990 u8 reserved_at_8[0x18]; 6991 6992 u8 syndrome[0x20]; 6993 6994 u8 reserved_at_40[0x40]; 6995 }; 6996 6997 struct mlx5_ifc_set_rate_limit_in_bits { 6998 u8 opcode[0x10]; 6999 u8 reserved_at_10[0x10]; 7000 7001 u8 reserved_at_20[0x10]; 7002 u8 op_mod[0x10]; 7003 7004 u8 reserved_at_40[0x10]; 7005 u8 rate_limit_index[0x10]; 7006 7007 u8 reserved_at_60[0x20]; 7008 7009 u8 rate_limit[0x20]; 7010 }; 7011 7012 struct mlx5_ifc_access_register_out_bits { 7013 u8 status[0x8]; 7014 u8 reserved_at_8[0x18]; 7015 7016 u8 syndrome[0x20]; 7017 7018 u8 reserved_at_40[0x40]; 7019 7020 u8 register_data[0][0x20]; 7021 }; 7022 7023 enum { 7024 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0, 7025 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1, 7026 }; 7027 7028 struct mlx5_ifc_access_register_in_bits { 7029 u8 opcode[0x10]; 7030 u8 reserved_at_10[0x10]; 7031 7032 u8 reserved_at_20[0x10]; 7033 u8 op_mod[0x10]; 7034 7035 u8 reserved_at_40[0x10]; 7036 u8 register_id[0x10]; 7037 7038 u8 argument[0x20]; 7039 7040 u8 register_data[0][0x20]; 7041 }; 7042 7043 struct mlx5_ifc_sltp_reg_bits { 7044 u8 status[0x4]; 7045 u8 version[0x4]; 7046 u8 local_port[0x8]; 7047 u8 pnat[0x2]; 7048 u8 reserved_at_12[0x2]; 7049 u8 lane[0x4]; 7050 u8 reserved_at_18[0x8]; 7051 7052 u8 reserved_at_20[0x20]; 7053 7054 u8 reserved_at_40[0x7]; 7055 u8 polarity[0x1]; 7056 u8 ob_tap0[0x8]; 7057 u8 ob_tap1[0x8]; 7058 u8 ob_tap2[0x8]; 7059 7060 u8 reserved_at_60[0xc]; 7061 u8 ob_preemp_mode[0x4]; 7062 u8 ob_reg[0x8]; 7063 u8 ob_bias[0x8]; 7064 7065 u8 reserved_at_80[0x20]; 7066 }; 7067 7068 struct mlx5_ifc_slrg_reg_bits { 7069 u8 status[0x4]; 7070 u8 version[0x4]; 7071 u8 local_port[0x8]; 7072 u8 pnat[0x2]; 7073 u8 reserved_at_12[0x2]; 7074 u8 lane[0x4]; 7075 u8 reserved_at_18[0x8]; 7076 7077 u8 time_to_link_up[0x10]; 7078 u8 reserved_at_30[0xc]; 7079 u8 grade_lane_speed[0x4]; 7080 7081 u8 grade_version[0x8]; 7082 u8 grade[0x18]; 7083 7084 u8 reserved_at_60[0x4]; 7085 u8 height_grade_type[0x4]; 7086 u8 height_grade[0x18]; 7087 7088 u8 height_dz[0x10]; 7089 u8 height_dv[0x10]; 7090 7091 u8 reserved_at_a0[0x10]; 7092 u8 height_sigma[0x10]; 7093 7094 u8 reserved_at_c0[0x20]; 7095 7096 u8 reserved_at_e0[0x4]; 7097 u8 phase_grade_type[0x4]; 7098 u8 phase_grade[0x18]; 7099 7100 u8 reserved_at_100[0x8]; 7101 u8 phase_eo_pos[0x8]; 7102 u8 reserved_at_110[0x8]; 7103 u8 phase_eo_neg[0x8]; 7104 7105 u8 ffe_set_tested[0x10]; 7106 u8 test_errors_per_lane[0x10]; 7107 }; 7108 7109 struct mlx5_ifc_pvlc_reg_bits { 7110 u8 reserved_at_0[0x8]; 7111 u8 local_port[0x8]; 7112 u8 reserved_at_10[0x10]; 7113 7114 u8 reserved_at_20[0x1c]; 7115 u8 vl_hw_cap[0x4]; 7116 7117 u8 reserved_at_40[0x1c]; 7118 u8 vl_admin[0x4]; 7119 7120 u8 reserved_at_60[0x1c]; 7121 u8 vl_operational[0x4]; 7122 }; 7123 7124 struct mlx5_ifc_pude_reg_bits { 7125 u8 swid[0x8]; 7126 u8 local_port[0x8]; 7127 u8 reserved_at_10[0x4]; 7128 u8 admin_status[0x4]; 7129 u8 reserved_at_18[0x4]; 7130 u8 oper_status[0x4]; 7131 7132 u8 reserved_at_20[0x60]; 7133 }; 7134 7135 struct mlx5_ifc_ptys_reg_bits { 7136 u8 reserved_at_0[0x1]; 7137 u8 an_disable_admin[0x1]; 7138 u8 an_disable_cap[0x1]; 7139 u8 reserved_at_3[0x5]; 7140 u8 local_port[0x8]; 7141 u8 reserved_at_10[0xd]; 7142 u8 proto_mask[0x3]; 7143 7144 u8 an_status[0x4]; 7145 u8 reserved_at_24[0x3c]; 7146 7147 u8 eth_proto_capability[0x20]; 7148 7149 u8 ib_link_width_capability[0x10]; 7150 u8 ib_proto_capability[0x10]; 7151 7152 u8 reserved_at_a0[0x20]; 7153 7154 u8 eth_proto_admin[0x20]; 7155 7156 u8 ib_link_width_admin[0x10]; 7157 u8 ib_proto_admin[0x10]; 7158 7159 u8 reserved_at_100[0x20]; 7160 7161 u8 eth_proto_oper[0x20]; 7162 7163 u8 ib_link_width_oper[0x10]; 7164 u8 ib_proto_oper[0x10]; 7165 7166 u8 reserved_at_160[0x20]; 7167 7168 u8 eth_proto_lp_advertise[0x20]; 7169 7170 u8 reserved_at_1a0[0x60]; 7171 }; 7172 7173 struct mlx5_ifc_mlcr_reg_bits { 7174 u8 reserved_at_0[0x8]; 7175 u8 local_port[0x8]; 7176 u8 reserved_at_10[0x20]; 7177 7178 u8 beacon_duration[0x10]; 7179 u8 reserved_at_40[0x10]; 7180 7181 u8 beacon_remain[0x10]; 7182 }; 7183 7184 struct mlx5_ifc_ptas_reg_bits { 7185 u8 reserved_at_0[0x20]; 7186 7187 u8 algorithm_options[0x10]; 7188 u8 reserved_at_30[0x4]; 7189 u8 repetitions_mode[0x4]; 7190 u8 num_of_repetitions[0x8]; 7191 7192 u8 grade_version[0x8]; 7193 u8 height_grade_type[0x4]; 7194 u8 phase_grade_type[0x4]; 7195 u8 height_grade_weight[0x8]; 7196 u8 phase_grade_weight[0x8]; 7197 7198 u8 gisim_measure_bits[0x10]; 7199 u8 adaptive_tap_measure_bits[0x10]; 7200 7201 u8 ber_bath_high_error_threshold[0x10]; 7202 u8 ber_bath_mid_error_threshold[0x10]; 7203 7204 u8 ber_bath_low_error_threshold[0x10]; 7205 u8 one_ratio_high_threshold[0x10]; 7206 7207 u8 one_ratio_high_mid_threshold[0x10]; 7208 u8 one_ratio_low_mid_threshold[0x10]; 7209 7210 u8 one_ratio_low_threshold[0x10]; 7211 u8 ndeo_error_threshold[0x10]; 7212 7213 u8 mixer_offset_step_size[0x10]; 7214 u8 reserved_at_110[0x8]; 7215 u8 mix90_phase_for_voltage_bath[0x8]; 7216 7217 u8 mixer_offset_start[0x10]; 7218 u8 mixer_offset_end[0x10]; 7219 7220 u8 reserved_at_140[0x15]; 7221 u8 ber_test_time[0xb]; 7222 }; 7223 7224 struct mlx5_ifc_pspa_reg_bits { 7225 u8 swid[0x8]; 7226 u8 local_port[0x8]; 7227 u8 sub_port[0x8]; 7228 u8 reserved_at_18[0x8]; 7229 7230 u8 reserved_at_20[0x20]; 7231 }; 7232 7233 struct mlx5_ifc_pqdr_reg_bits { 7234 u8 reserved_at_0[0x8]; 7235 u8 local_port[0x8]; 7236 u8 reserved_at_10[0x5]; 7237 u8 prio[0x3]; 7238 u8 reserved_at_18[0x6]; 7239 u8 mode[0x2]; 7240 7241 u8 reserved_at_20[0x20]; 7242 7243 u8 reserved_at_40[0x10]; 7244 u8 min_threshold[0x10]; 7245 7246 u8 reserved_at_60[0x10]; 7247 u8 max_threshold[0x10]; 7248 7249 u8 reserved_at_80[0x10]; 7250 u8 mark_probability_denominator[0x10]; 7251 7252 u8 reserved_at_a0[0x60]; 7253 }; 7254 7255 struct mlx5_ifc_ppsc_reg_bits { 7256 u8 reserved_at_0[0x8]; 7257 u8 local_port[0x8]; 7258 u8 reserved_at_10[0x10]; 7259 7260 u8 reserved_at_20[0x60]; 7261 7262 u8 reserved_at_80[0x1c]; 7263 u8 wrps_admin[0x4]; 7264 7265 u8 reserved_at_a0[0x1c]; 7266 u8 wrps_status[0x4]; 7267 7268 u8 reserved_at_c0[0x8]; 7269 u8 up_threshold[0x8]; 7270 u8 reserved_at_d0[0x8]; 7271 u8 down_threshold[0x8]; 7272 7273 u8 reserved_at_e0[0x20]; 7274 7275 u8 reserved_at_100[0x1c]; 7276 u8 srps_admin[0x4]; 7277 7278 u8 reserved_at_120[0x1c]; 7279 u8 srps_status[0x4]; 7280 7281 u8 reserved_at_140[0x40]; 7282 }; 7283 7284 struct mlx5_ifc_pplr_reg_bits { 7285 u8 reserved_at_0[0x8]; 7286 u8 local_port[0x8]; 7287 u8 reserved_at_10[0x10]; 7288 7289 u8 reserved_at_20[0x8]; 7290 u8 lb_cap[0x8]; 7291 u8 reserved_at_30[0x8]; 7292 u8 lb_en[0x8]; 7293 }; 7294 7295 struct mlx5_ifc_pplm_reg_bits { 7296 u8 reserved_at_0[0x8]; 7297 u8 local_port[0x8]; 7298 u8 reserved_at_10[0x10]; 7299 7300 u8 reserved_at_20[0x20]; 7301 7302 u8 port_profile_mode[0x8]; 7303 u8 static_port_profile[0x8]; 7304 u8 active_port_profile[0x8]; 7305 u8 reserved_at_58[0x8]; 7306 7307 u8 retransmission_active[0x8]; 7308 u8 fec_mode_active[0x18]; 7309 7310 u8 reserved_at_80[0x20]; 7311 }; 7312 7313 struct mlx5_ifc_ppcnt_reg_bits { 7314 u8 swid[0x8]; 7315 u8 local_port[0x8]; 7316 u8 pnat[0x2]; 7317 u8 reserved_at_12[0x8]; 7318 u8 grp[0x6]; 7319 7320 u8 clr[0x1]; 7321 u8 reserved_at_21[0x1c]; 7322 u8 prio_tc[0x3]; 7323 7324 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set; 7325 }; 7326 7327 struct mlx5_ifc_mpcnt_reg_bits { 7328 u8 reserved_at_0[0x8]; 7329 u8 pcie_index[0x8]; 7330 u8 reserved_at_10[0xa]; 7331 u8 grp[0x6]; 7332 7333 u8 clr[0x1]; 7334 u8 reserved_at_21[0x1f]; 7335 7336 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set; 7337 }; 7338 7339 struct mlx5_ifc_ppad_reg_bits { 7340 u8 reserved_at_0[0x3]; 7341 u8 single_mac[0x1]; 7342 u8 reserved_at_4[0x4]; 7343 u8 local_port[0x8]; 7344 u8 mac_47_32[0x10]; 7345 7346 u8 mac_31_0[0x20]; 7347 7348 u8 reserved_at_40[0x40]; 7349 }; 7350 7351 struct mlx5_ifc_pmtu_reg_bits { 7352 u8 reserved_at_0[0x8]; 7353 u8 local_port[0x8]; 7354 u8 reserved_at_10[0x10]; 7355 7356 u8 max_mtu[0x10]; 7357 u8 reserved_at_30[0x10]; 7358 7359 u8 admin_mtu[0x10]; 7360 u8 reserved_at_50[0x10]; 7361 7362 u8 oper_mtu[0x10]; 7363 u8 reserved_at_70[0x10]; 7364 }; 7365 7366 struct mlx5_ifc_pmpr_reg_bits { 7367 u8 reserved_at_0[0x8]; 7368 u8 module[0x8]; 7369 u8 reserved_at_10[0x10]; 7370 7371 u8 reserved_at_20[0x18]; 7372 u8 attenuation_5g[0x8]; 7373 7374 u8 reserved_at_40[0x18]; 7375 u8 attenuation_7g[0x8]; 7376 7377 u8 reserved_at_60[0x18]; 7378 u8 attenuation_12g[0x8]; 7379 }; 7380 7381 struct mlx5_ifc_pmpe_reg_bits { 7382 u8 reserved_at_0[0x8]; 7383 u8 module[0x8]; 7384 u8 reserved_at_10[0xc]; 7385 u8 module_status[0x4]; 7386 7387 u8 reserved_at_20[0x60]; 7388 }; 7389 7390 struct mlx5_ifc_pmpc_reg_bits { 7391 u8 module_state_updated[32][0x8]; 7392 }; 7393 7394 struct mlx5_ifc_pmlpn_reg_bits { 7395 u8 reserved_at_0[0x4]; 7396 u8 mlpn_status[0x4]; 7397 u8 local_port[0x8]; 7398 u8 reserved_at_10[0x10]; 7399 7400 u8 e[0x1]; 7401 u8 reserved_at_21[0x1f]; 7402 }; 7403 7404 struct mlx5_ifc_pmlp_reg_bits { 7405 u8 rxtx[0x1]; 7406 u8 reserved_at_1[0x7]; 7407 u8 local_port[0x8]; 7408 u8 reserved_at_10[0x8]; 7409 u8 width[0x8]; 7410 7411 u8 lane0_module_mapping[0x20]; 7412 7413 u8 lane1_module_mapping[0x20]; 7414 7415 u8 lane2_module_mapping[0x20]; 7416 7417 u8 lane3_module_mapping[0x20]; 7418 7419 u8 reserved_at_a0[0x160]; 7420 }; 7421 7422 struct mlx5_ifc_pmaos_reg_bits { 7423 u8 reserved_at_0[0x8]; 7424 u8 module[0x8]; 7425 u8 reserved_at_10[0x4]; 7426 u8 admin_status[0x4]; 7427 u8 reserved_at_18[0x4]; 7428 u8 oper_status[0x4]; 7429 7430 u8 ase[0x1]; 7431 u8 ee[0x1]; 7432 u8 reserved_at_22[0x1c]; 7433 u8 e[0x2]; 7434 7435 u8 reserved_at_40[0x40]; 7436 }; 7437 7438 struct mlx5_ifc_plpc_reg_bits { 7439 u8 reserved_at_0[0x4]; 7440 u8 profile_id[0xc]; 7441 u8 reserved_at_10[0x4]; 7442 u8 proto_mask[0x4]; 7443 u8 reserved_at_18[0x8]; 7444 7445 u8 reserved_at_20[0x10]; 7446 u8 lane_speed[0x10]; 7447 7448 u8 reserved_at_40[0x17]; 7449 u8 lpbf[0x1]; 7450 u8 fec_mode_policy[0x8]; 7451 7452 u8 retransmission_capability[0x8]; 7453 u8 fec_mode_capability[0x18]; 7454 7455 u8 retransmission_support_admin[0x8]; 7456 u8 fec_mode_support_admin[0x18]; 7457 7458 u8 retransmission_request_admin[0x8]; 7459 u8 fec_mode_request_admin[0x18]; 7460 7461 u8 reserved_at_c0[0x80]; 7462 }; 7463 7464 struct mlx5_ifc_plib_reg_bits { 7465 u8 reserved_at_0[0x8]; 7466 u8 local_port[0x8]; 7467 u8 reserved_at_10[0x8]; 7468 u8 ib_port[0x8]; 7469 7470 u8 reserved_at_20[0x60]; 7471 }; 7472 7473 struct mlx5_ifc_plbf_reg_bits { 7474 u8 reserved_at_0[0x8]; 7475 u8 local_port[0x8]; 7476 u8 reserved_at_10[0xd]; 7477 u8 lbf_mode[0x3]; 7478 7479 u8 reserved_at_20[0x20]; 7480 }; 7481 7482 struct mlx5_ifc_pipg_reg_bits { 7483 u8 reserved_at_0[0x8]; 7484 u8 local_port[0x8]; 7485 u8 reserved_at_10[0x10]; 7486 7487 u8 dic[0x1]; 7488 u8 reserved_at_21[0x19]; 7489 u8 ipg[0x4]; 7490 u8 reserved_at_3e[0x2]; 7491 }; 7492 7493 struct mlx5_ifc_pifr_reg_bits { 7494 u8 reserved_at_0[0x8]; 7495 u8 local_port[0x8]; 7496 u8 reserved_at_10[0x10]; 7497 7498 u8 reserved_at_20[0xe0]; 7499 7500 u8 port_filter[8][0x20]; 7501 7502 u8 port_filter_update_en[8][0x20]; 7503 }; 7504 7505 struct mlx5_ifc_pfcc_reg_bits { 7506 u8 reserved_at_0[0x8]; 7507 u8 local_port[0x8]; 7508 u8 reserved_at_10[0x10]; 7509 7510 u8 ppan[0x4]; 7511 u8 reserved_at_24[0x4]; 7512 u8 prio_mask_tx[0x8]; 7513 u8 reserved_at_30[0x8]; 7514 u8 prio_mask_rx[0x8]; 7515 7516 u8 pptx[0x1]; 7517 u8 aptx[0x1]; 7518 u8 reserved_at_42[0x6]; 7519 u8 pfctx[0x8]; 7520 u8 reserved_at_50[0x10]; 7521 7522 u8 pprx[0x1]; 7523 u8 aprx[0x1]; 7524 u8 reserved_at_62[0x6]; 7525 u8 pfcrx[0x8]; 7526 u8 reserved_at_70[0x10]; 7527 7528 u8 reserved_at_80[0x80]; 7529 }; 7530 7531 struct mlx5_ifc_pelc_reg_bits { 7532 u8 op[0x4]; 7533 u8 reserved_at_4[0x4]; 7534 u8 local_port[0x8]; 7535 u8 reserved_at_10[0x10]; 7536 7537 u8 op_admin[0x8]; 7538 u8 op_capability[0x8]; 7539 u8 op_request[0x8]; 7540 u8 op_active[0x8]; 7541 7542 u8 admin[0x40]; 7543 7544 u8 capability[0x40]; 7545 7546 u8 request[0x40]; 7547 7548 u8 active[0x40]; 7549 7550 u8 reserved_at_140[0x80]; 7551 }; 7552 7553 struct mlx5_ifc_peir_reg_bits { 7554 u8 reserved_at_0[0x8]; 7555 u8 local_port[0x8]; 7556 u8 reserved_at_10[0x10]; 7557 7558 u8 reserved_at_20[0xc]; 7559 u8 error_count[0x4]; 7560 u8 reserved_at_30[0x10]; 7561 7562 u8 reserved_at_40[0xc]; 7563 u8 lane[0x4]; 7564 u8 reserved_at_50[0x8]; 7565 u8 error_type[0x8]; 7566 }; 7567 7568 struct mlx5_ifc_pcam_enhanced_features_bits { 7569 u8 reserved_at_0[0x7e]; 7570 7571 u8 ppcnt_discard_group[0x1]; 7572 u8 ppcnt_statistical_group[0x1]; 7573 }; 7574 7575 struct mlx5_ifc_pcam_reg_bits { 7576 u8 reserved_at_0[0x8]; 7577 u8 feature_group[0x8]; 7578 u8 reserved_at_10[0x8]; 7579 u8 access_reg_group[0x8]; 7580 7581 u8 reserved_at_20[0x20]; 7582 7583 union { 7584 u8 reserved_at_0[0x80]; 7585 } port_access_reg_cap_mask; 7586 7587 u8 reserved_at_c0[0x80]; 7588 7589 union { 7590 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features; 7591 u8 reserved_at_0[0x80]; 7592 } feature_cap_mask; 7593 7594 u8 reserved_at_1c0[0xc0]; 7595 }; 7596 7597 struct mlx5_ifc_mcam_enhanced_features_bits { 7598 u8 reserved_at_0[0x7f]; 7599 7600 u8 pcie_performance_group[0x1]; 7601 }; 7602 7603 struct mlx5_ifc_mcam_reg_bits { 7604 u8 reserved_at_0[0x8]; 7605 u8 feature_group[0x8]; 7606 u8 reserved_at_10[0x8]; 7607 u8 access_reg_group[0x8]; 7608 7609 u8 reserved_at_20[0x20]; 7610 7611 union { 7612 u8 reserved_at_0[0x80]; 7613 } mng_access_reg_cap_mask; 7614 7615 u8 reserved_at_c0[0x80]; 7616 7617 union { 7618 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features; 7619 u8 reserved_at_0[0x80]; 7620 } mng_feature_cap_mask; 7621 7622 u8 reserved_at_1c0[0x80]; 7623 }; 7624 7625 struct mlx5_ifc_pcap_reg_bits { 7626 u8 reserved_at_0[0x8]; 7627 u8 local_port[0x8]; 7628 u8 reserved_at_10[0x10]; 7629 7630 u8 port_capability_mask[4][0x20]; 7631 }; 7632 7633 struct mlx5_ifc_paos_reg_bits { 7634 u8 swid[0x8]; 7635 u8 local_port[0x8]; 7636 u8 reserved_at_10[0x4]; 7637 u8 admin_status[0x4]; 7638 u8 reserved_at_18[0x4]; 7639 u8 oper_status[0x4]; 7640 7641 u8 ase[0x1]; 7642 u8 ee[0x1]; 7643 u8 reserved_at_22[0x1c]; 7644 u8 e[0x2]; 7645 7646 u8 reserved_at_40[0x40]; 7647 }; 7648 7649 struct mlx5_ifc_pamp_reg_bits { 7650 u8 reserved_at_0[0x8]; 7651 u8 opamp_group[0x8]; 7652 u8 reserved_at_10[0xc]; 7653 u8 opamp_group_type[0x4]; 7654 7655 u8 start_index[0x10]; 7656 u8 reserved_at_30[0x4]; 7657 u8 num_of_indices[0xc]; 7658 7659 u8 index_data[18][0x10]; 7660 }; 7661 7662 struct mlx5_ifc_pcmr_reg_bits { 7663 u8 reserved_at_0[0x8]; 7664 u8 local_port[0x8]; 7665 u8 reserved_at_10[0x2e]; 7666 u8 fcs_cap[0x1]; 7667 u8 reserved_at_3f[0x1f]; 7668 u8 fcs_chk[0x1]; 7669 u8 reserved_at_5f[0x1]; 7670 }; 7671 7672 struct mlx5_ifc_lane_2_module_mapping_bits { 7673 u8 reserved_at_0[0x6]; 7674 u8 rx_lane[0x2]; 7675 u8 reserved_at_8[0x6]; 7676 u8 tx_lane[0x2]; 7677 u8 reserved_at_10[0x8]; 7678 u8 module[0x8]; 7679 }; 7680 7681 struct mlx5_ifc_bufferx_reg_bits { 7682 u8 reserved_at_0[0x6]; 7683 u8 lossy[0x1]; 7684 u8 epsb[0x1]; 7685 u8 reserved_at_8[0xc]; 7686 u8 size[0xc]; 7687 7688 u8 xoff_threshold[0x10]; 7689 u8 xon_threshold[0x10]; 7690 }; 7691 7692 struct mlx5_ifc_set_node_in_bits { 7693 u8 node_description[64][0x8]; 7694 }; 7695 7696 struct mlx5_ifc_register_power_settings_bits { 7697 u8 reserved_at_0[0x18]; 7698 u8 power_settings_level[0x8]; 7699 7700 u8 reserved_at_20[0x60]; 7701 }; 7702 7703 struct mlx5_ifc_register_host_endianness_bits { 7704 u8 he[0x1]; 7705 u8 reserved_at_1[0x1f]; 7706 7707 u8 reserved_at_20[0x60]; 7708 }; 7709 7710 struct mlx5_ifc_umr_pointer_desc_argument_bits { 7711 u8 reserved_at_0[0x20]; 7712 7713 u8 mkey[0x20]; 7714 7715 u8 addressh_63_32[0x20]; 7716 7717 u8 addressl_31_0[0x20]; 7718 }; 7719 7720 struct mlx5_ifc_ud_adrs_vector_bits { 7721 u8 dc_key[0x40]; 7722 7723 u8 ext[0x1]; 7724 u8 reserved_at_41[0x7]; 7725 u8 destination_qp_dct[0x18]; 7726 7727 u8 static_rate[0x4]; 7728 u8 sl_eth_prio[0x4]; 7729 u8 fl[0x1]; 7730 u8 mlid[0x7]; 7731 u8 rlid_udp_sport[0x10]; 7732 7733 u8 reserved_at_80[0x20]; 7734 7735 u8 rmac_47_16[0x20]; 7736 7737 u8 rmac_15_0[0x10]; 7738 u8 tclass[0x8]; 7739 u8 hop_limit[0x8]; 7740 7741 u8 reserved_at_e0[0x1]; 7742 u8 grh[0x1]; 7743 u8 reserved_at_e2[0x2]; 7744 u8 src_addr_index[0x8]; 7745 u8 flow_label[0x14]; 7746 7747 u8 rgid_rip[16][0x8]; 7748 }; 7749 7750 struct mlx5_ifc_pages_req_event_bits { 7751 u8 reserved_at_0[0x10]; 7752 u8 function_id[0x10]; 7753 7754 u8 num_pages[0x20]; 7755 7756 u8 reserved_at_40[0xa0]; 7757 }; 7758 7759 struct mlx5_ifc_eqe_bits { 7760 u8 reserved_at_0[0x8]; 7761 u8 event_type[0x8]; 7762 u8 reserved_at_10[0x8]; 7763 u8 event_sub_type[0x8]; 7764 7765 u8 reserved_at_20[0xe0]; 7766 7767 union mlx5_ifc_event_auto_bits event_data; 7768 7769 u8 reserved_at_1e0[0x10]; 7770 u8 signature[0x8]; 7771 u8 reserved_at_1f8[0x7]; 7772 u8 owner[0x1]; 7773 }; 7774 7775 enum { 7776 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7, 7777 }; 7778 7779 struct mlx5_ifc_cmd_queue_entry_bits { 7780 u8 type[0x8]; 7781 u8 reserved_at_8[0x18]; 7782 7783 u8 input_length[0x20]; 7784 7785 u8 input_mailbox_pointer_63_32[0x20]; 7786 7787 u8 input_mailbox_pointer_31_9[0x17]; 7788 u8 reserved_at_77[0x9]; 7789 7790 u8 command_input_inline_data[16][0x8]; 7791 7792 u8 command_output_inline_data[16][0x8]; 7793 7794 u8 output_mailbox_pointer_63_32[0x20]; 7795 7796 u8 output_mailbox_pointer_31_9[0x17]; 7797 u8 reserved_at_1b7[0x9]; 7798 7799 u8 output_length[0x20]; 7800 7801 u8 token[0x8]; 7802 u8 signature[0x8]; 7803 u8 reserved_at_1f0[0x8]; 7804 u8 status[0x7]; 7805 u8 ownership[0x1]; 7806 }; 7807 7808 struct mlx5_ifc_cmd_out_bits { 7809 u8 status[0x8]; 7810 u8 reserved_at_8[0x18]; 7811 7812 u8 syndrome[0x20]; 7813 7814 u8 command_output[0x20]; 7815 }; 7816 7817 struct mlx5_ifc_cmd_in_bits { 7818 u8 opcode[0x10]; 7819 u8 reserved_at_10[0x10]; 7820 7821 u8 reserved_at_20[0x10]; 7822 u8 op_mod[0x10]; 7823 7824 u8 command[0][0x20]; 7825 }; 7826 7827 struct mlx5_ifc_cmd_if_box_bits { 7828 u8 mailbox_data[512][0x8]; 7829 7830 u8 reserved_at_1000[0x180]; 7831 7832 u8 next_pointer_63_32[0x20]; 7833 7834 u8 next_pointer_31_10[0x16]; 7835 u8 reserved_at_11b6[0xa]; 7836 7837 u8 block_number[0x20]; 7838 7839 u8 reserved_at_11e0[0x8]; 7840 u8 token[0x8]; 7841 u8 ctrl_signature[0x8]; 7842 u8 signature[0x8]; 7843 }; 7844 7845 struct mlx5_ifc_mtt_bits { 7846 u8 ptag_63_32[0x20]; 7847 7848 u8 ptag_31_8[0x18]; 7849 u8 reserved_at_38[0x6]; 7850 u8 wr_en[0x1]; 7851 u8 rd_en[0x1]; 7852 }; 7853 7854 struct mlx5_ifc_query_wol_rol_out_bits { 7855 u8 status[0x8]; 7856 u8 reserved_at_8[0x18]; 7857 7858 u8 syndrome[0x20]; 7859 7860 u8 reserved_at_40[0x10]; 7861 u8 rol_mode[0x8]; 7862 u8 wol_mode[0x8]; 7863 7864 u8 reserved_at_60[0x20]; 7865 }; 7866 7867 struct mlx5_ifc_query_wol_rol_in_bits { 7868 u8 opcode[0x10]; 7869 u8 reserved_at_10[0x10]; 7870 7871 u8 reserved_at_20[0x10]; 7872 u8 op_mod[0x10]; 7873 7874 u8 reserved_at_40[0x40]; 7875 }; 7876 7877 struct mlx5_ifc_set_wol_rol_out_bits { 7878 u8 status[0x8]; 7879 u8 reserved_at_8[0x18]; 7880 7881 u8 syndrome[0x20]; 7882 7883 u8 reserved_at_40[0x40]; 7884 }; 7885 7886 struct mlx5_ifc_set_wol_rol_in_bits { 7887 u8 opcode[0x10]; 7888 u8 reserved_at_10[0x10]; 7889 7890 u8 reserved_at_20[0x10]; 7891 u8 op_mod[0x10]; 7892 7893 u8 rol_mode_valid[0x1]; 7894 u8 wol_mode_valid[0x1]; 7895 u8 reserved_at_42[0xe]; 7896 u8 rol_mode[0x8]; 7897 u8 wol_mode[0x8]; 7898 7899 u8 reserved_at_60[0x20]; 7900 }; 7901 7902 enum { 7903 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0, 7904 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1, 7905 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2, 7906 }; 7907 7908 enum { 7909 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0, 7910 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1, 7911 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2, 7912 }; 7913 7914 enum { 7915 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR = 0x1, 7916 MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC = 0x7, 7917 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR = 0x8, 7918 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR = 0x9, 7919 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR = 0xa, 7920 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR = 0xb, 7921 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN = 0xc, 7922 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR = 0xd, 7923 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV = 0xe, 7924 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR = 0xf, 7925 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR = 0x10, 7926 }; 7927 7928 struct mlx5_ifc_initial_seg_bits { 7929 u8 fw_rev_minor[0x10]; 7930 u8 fw_rev_major[0x10]; 7931 7932 u8 cmd_interface_rev[0x10]; 7933 u8 fw_rev_subminor[0x10]; 7934 7935 u8 reserved_at_40[0x40]; 7936 7937 u8 cmdq_phy_addr_63_32[0x20]; 7938 7939 u8 cmdq_phy_addr_31_12[0x14]; 7940 u8 reserved_at_b4[0x2]; 7941 u8 nic_interface[0x2]; 7942 u8 log_cmdq_size[0x4]; 7943 u8 log_cmdq_stride[0x4]; 7944 7945 u8 command_doorbell_vector[0x20]; 7946 7947 u8 reserved_at_e0[0xf00]; 7948 7949 u8 initializing[0x1]; 7950 u8 reserved_at_fe1[0x4]; 7951 u8 nic_interface_supported[0x3]; 7952 u8 reserved_at_fe8[0x18]; 7953 7954 struct mlx5_ifc_health_buffer_bits health_buffer; 7955 7956 u8 no_dram_nic_offset[0x20]; 7957 7958 u8 reserved_at_1220[0x6e40]; 7959 7960 u8 reserved_at_8060[0x1f]; 7961 u8 clear_int[0x1]; 7962 7963 u8 health_syndrome[0x8]; 7964 u8 health_counter[0x18]; 7965 7966 u8 reserved_at_80a0[0x17fc0]; 7967 }; 7968 7969 struct mlx5_ifc_mtpps_reg_bits { 7970 u8 reserved_at_0[0xc]; 7971 u8 cap_number_of_pps_pins[0x4]; 7972 u8 reserved_at_10[0x4]; 7973 u8 cap_max_num_of_pps_in_pins[0x4]; 7974 u8 reserved_at_18[0x4]; 7975 u8 cap_max_num_of_pps_out_pins[0x4]; 7976 7977 u8 reserved_at_20[0x24]; 7978 u8 cap_pin_3_mode[0x4]; 7979 u8 reserved_at_48[0x4]; 7980 u8 cap_pin_2_mode[0x4]; 7981 u8 reserved_at_50[0x4]; 7982 u8 cap_pin_1_mode[0x4]; 7983 u8 reserved_at_58[0x4]; 7984 u8 cap_pin_0_mode[0x4]; 7985 7986 u8 reserved_at_60[0x4]; 7987 u8 cap_pin_7_mode[0x4]; 7988 u8 reserved_at_68[0x4]; 7989 u8 cap_pin_6_mode[0x4]; 7990 u8 reserved_at_70[0x4]; 7991 u8 cap_pin_5_mode[0x4]; 7992 u8 reserved_at_78[0x4]; 7993 u8 cap_pin_4_mode[0x4]; 7994 7995 u8 reserved_at_80[0x80]; 7996 7997 u8 enable[0x1]; 7998 u8 reserved_at_101[0xb]; 7999 u8 pattern[0x4]; 8000 u8 reserved_at_110[0x4]; 8001 u8 pin_mode[0x4]; 8002 u8 pin[0x8]; 8003 8004 u8 reserved_at_120[0x20]; 8005 8006 u8 time_stamp[0x40]; 8007 8008 u8 out_pulse_duration[0x10]; 8009 u8 out_periodic_adjustment[0x10]; 8010 8011 u8 reserved_at_1a0[0x60]; 8012 }; 8013 8014 struct mlx5_ifc_mtppse_reg_bits { 8015 u8 reserved_at_0[0x18]; 8016 u8 pin[0x8]; 8017 u8 event_arm[0x1]; 8018 u8 reserved_at_21[0x1b]; 8019 u8 event_generation_mode[0x4]; 8020 u8 reserved_at_40[0x40]; 8021 }; 8022 8023 union mlx5_ifc_ports_control_registers_document_bits { 8024 struct mlx5_ifc_bufferx_reg_bits bufferx_reg; 8025 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 8026 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 8027 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 8028 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 8029 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 8030 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 8031 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout; 8032 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping; 8033 struct mlx5_ifc_pamp_reg_bits pamp_reg; 8034 struct mlx5_ifc_paos_reg_bits paos_reg; 8035 struct mlx5_ifc_pcap_reg_bits pcap_reg; 8036 struct mlx5_ifc_peir_reg_bits peir_reg; 8037 struct mlx5_ifc_pelc_reg_bits pelc_reg; 8038 struct mlx5_ifc_pfcc_reg_bits pfcc_reg; 8039 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 8040 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 8041 struct mlx5_ifc_pifr_reg_bits pifr_reg; 8042 struct mlx5_ifc_pipg_reg_bits pipg_reg; 8043 struct mlx5_ifc_plbf_reg_bits plbf_reg; 8044 struct mlx5_ifc_plib_reg_bits plib_reg; 8045 struct mlx5_ifc_plpc_reg_bits plpc_reg; 8046 struct mlx5_ifc_pmaos_reg_bits pmaos_reg; 8047 struct mlx5_ifc_pmlp_reg_bits pmlp_reg; 8048 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg; 8049 struct mlx5_ifc_pmpc_reg_bits pmpc_reg; 8050 struct mlx5_ifc_pmpe_reg_bits pmpe_reg; 8051 struct mlx5_ifc_pmpr_reg_bits pmpr_reg; 8052 struct mlx5_ifc_pmtu_reg_bits pmtu_reg; 8053 struct mlx5_ifc_ppad_reg_bits ppad_reg; 8054 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg; 8055 struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg; 8056 struct mlx5_ifc_pplm_reg_bits pplm_reg; 8057 struct mlx5_ifc_pplr_reg_bits pplr_reg; 8058 struct mlx5_ifc_ppsc_reg_bits ppsc_reg; 8059 struct mlx5_ifc_pqdr_reg_bits pqdr_reg; 8060 struct mlx5_ifc_pspa_reg_bits pspa_reg; 8061 struct mlx5_ifc_ptas_reg_bits ptas_reg; 8062 struct mlx5_ifc_ptys_reg_bits ptys_reg; 8063 struct mlx5_ifc_mlcr_reg_bits mlcr_reg; 8064 struct mlx5_ifc_pude_reg_bits pude_reg; 8065 struct mlx5_ifc_pvlc_reg_bits pvlc_reg; 8066 struct mlx5_ifc_slrg_reg_bits slrg_reg; 8067 struct mlx5_ifc_sltp_reg_bits sltp_reg; 8068 struct mlx5_ifc_mtpps_reg_bits mtpps_reg; 8069 struct mlx5_ifc_mtppse_reg_bits mtppse_reg; 8070 u8 reserved_at_0[0x60e0]; 8071 }; 8072 8073 union mlx5_ifc_debug_enhancements_document_bits { 8074 struct mlx5_ifc_health_buffer_bits health_buffer; 8075 u8 reserved_at_0[0x200]; 8076 }; 8077 8078 union mlx5_ifc_uplink_pci_interface_document_bits { 8079 struct mlx5_ifc_initial_seg_bits initial_seg; 8080 u8 reserved_at_0[0x20060]; 8081 }; 8082 8083 struct mlx5_ifc_set_flow_table_root_out_bits { 8084 u8 status[0x8]; 8085 u8 reserved_at_8[0x18]; 8086 8087 u8 syndrome[0x20]; 8088 8089 u8 reserved_at_40[0x40]; 8090 }; 8091 8092 struct mlx5_ifc_set_flow_table_root_in_bits { 8093 u8 opcode[0x10]; 8094 u8 reserved_at_10[0x10]; 8095 8096 u8 reserved_at_20[0x10]; 8097 u8 op_mod[0x10]; 8098 8099 u8 other_vport[0x1]; 8100 u8 reserved_at_41[0xf]; 8101 u8 vport_number[0x10]; 8102 8103 u8 reserved_at_60[0x20]; 8104 8105 u8 table_type[0x8]; 8106 u8 reserved_at_88[0x18]; 8107 8108 u8 reserved_at_a0[0x8]; 8109 u8 table_id[0x18]; 8110 8111 u8 reserved_at_c0[0x140]; 8112 }; 8113 8114 enum { 8115 MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = (1UL << 0), 8116 MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15), 8117 }; 8118 8119 struct mlx5_ifc_modify_flow_table_out_bits { 8120 u8 status[0x8]; 8121 u8 reserved_at_8[0x18]; 8122 8123 u8 syndrome[0x20]; 8124 8125 u8 reserved_at_40[0x40]; 8126 }; 8127 8128 struct mlx5_ifc_modify_flow_table_in_bits { 8129 u8 opcode[0x10]; 8130 u8 reserved_at_10[0x10]; 8131 8132 u8 reserved_at_20[0x10]; 8133 u8 op_mod[0x10]; 8134 8135 u8 other_vport[0x1]; 8136 u8 reserved_at_41[0xf]; 8137 u8 vport_number[0x10]; 8138 8139 u8 reserved_at_60[0x10]; 8140 u8 modify_field_select[0x10]; 8141 8142 u8 table_type[0x8]; 8143 u8 reserved_at_88[0x18]; 8144 8145 u8 reserved_at_a0[0x8]; 8146 u8 table_id[0x18]; 8147 8148 u8 reserved_at_c0[0x4]; 8149 u8 table_miss_mode[0x4]; 8150 u8 reserved_at_c8[0x18]; 8151 8152 u8 reserved_at_e0[0x8]; 8153 u8 table_miss_id[0x18]; 8154 8155 u8 reserved_at_100[0x8]; 8156 u8 lag_master_next_table_id[0x18]; 8157 8158 u8 reserved_at_120[0x80]; 8159 }; 8160 8161 struct mlx5_ifc_ets_tcn_config_reg_bits { 8162 u8 g[0x1]; 8163 u8 b[0x1]; 8164 u8 r[0x1]; 8165 u8 reserved_at_3[0x9]; 8166 u8 group[0x4]; 8167 u8 reserved_at_10[0x9]; 8168 u8 bw_allocation[0x7]; 8169 8170 u8 reserved_at_20[0xc]; 8171 u8 max_bw_units[0x4]; 8172 u8 reserved_at_30[0x8]; 8173 u8 max_bw_value[0x8]; 8174 }; 8175 8176 struct mlx5_ifc_ets_global_config_reg_bits { 8177 u8 reserved_at_0[0x2]; 8178 u8 r[0x1]; 8179 u8 reserved_at_3[0x1d]; 8180 8181 u8 reserved_at_20[0xc]; 8182 u8 max_bw_units[0x4]; 8183 u8 reserved_at_30[0x8]; 8184 u8 max_bw_value[0x8]; 8185 }; 8186 8187 struct mlx5_ifc_qetc_reg_bits { 8188 u8 reserved_at_0[0x8]; 8189 u8 port_number[0x8]; 8190 u8 reserved_at_10[0x30]; 8191 8192 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8]; 8193 struct mlx5_ifc_ets_global_config_reg_bits global_configuration; 8194 }; 8195 8196 struct mlx5_ifc_qtct_reg_bits { 8197 u8 reserved_at_0[0x8]; 8198 u8 port_number[0x8]; 8199 u8 reserved_at_10[0xd]; 8200 u8 prio[0x3]; 8201 8202 u8 reserved_at_20[0x1d]; 8203 u8 tclass[0x3]; 8204 }; 8205 8206 struct mlx5_ifc_mcia_reg_bits { 8207 u8 l[0x1]; 8208 u8 reserved_at_1[0x7]; 8209 u8 module[0x8]; 8210 u8 reserved_at_10[0x8]; 8211 u8 status[0x8]; 8212 8213 u8 i2c_device_address[0x8]; 8214 u8 page_number[0x8]; 8215 u8 device_address[0x10]; 8216 8217 u8 reserved_at_40[0x10]; 8218 u8 size[0x10]; 8219 8220 u8 reserved_at_60[0x20]; 8221 8222 u8 dword_0[0x20]; 8223 u8 dword_1[0x20]; 8224 u8 dword_2[0x20]; 8225 u8 dword_3[0x20]; 8226 u8 dword_4[0x20]; 8227 u8 dword_5[0x20]; 8228 u8 dword_6[0x20]; 8229 u8 dword_7[0x20]; 8230 u8 dword_8[0x20]; 8231 u8 dword_9[0x20]; 8232 u8 dword_10[0x20]; 8233 u8 dword_11[0x20]; 8234 }; 8235 8236 struct mlx5_ifc_dcbx_param_bits { 8237 u8 dcbx_cee_cap[0x1]; 8238 u8 dcbx_ieee_cap[0x1]; 8239 u8 dcbx_standby_cap[0x1]; 8240 u8 reserved_at_0[0x5]; 8241 u8 port_number[0x8]; 8242 u8 reserved_at_10[0xa]; 8243 u8 max_application_table_size[6]; 8244 u8 reserved_at_20[0x15]; 8245 u8 version_oper[0x3]; 8246 u8 reserved_at_38[5]; 8247 u8 version_admin[0x3]; 8248 u8 willing_admin[0x1]; 8249 u8 reserved_at_41[0x3]; 8250 u8 pfc_cap_oper[0x4]; 8251 u8 reserved_at_48[0x4]; 8252 u8 pfc_cap_admin[0x4]; 8253 u8 reserved_at_50[0x4]; 8254 u8 num_of_tc_oper[0x4]; 8255 u8 reserved_at_58[0x4]; 8256 u8 num_of_tc_admin[0x4]; 8257 u8 remote_willing[0x1]; 8258 u8 reserved_at_61[3]; 8259 u8 remote_pfc_cap[4]; 8260 u8 reserved_at_68[0x14]; 8261 u8 remote_num_of_tc[0x4]; 8262 u8 reserved_at_80[0x18]; 8263 u8 error[0x8]; 8264 u8 reserved_at_a0[0x160]; 8265 }; 8266 8267 struct mlx5_ifc_lagc_bits { 8268 u8 reserved_at_0[0x1d]; 8269 u8 lag_state[0x3]; 8270 8271 u8 reserved_at_20[0x14]; 8272 u8 tx_remap_affinity_2[0x4]; 8273 u8 reserved_at_38[0x4]; 8274 u8 tx_remap_affinity_1[0x4]; 8275 }; 8276 8277 struct mlx5_ifc_create_lag_out_bits { 8278 u8 status[0x8]; 8279 u8 reserved_at_8[0x18]; 8280 8281 u8 syndrome[0x20]; 8282 8283 u8 reserved_at_40[0x40]; 8284 }; 8285 8286 struct mlx5_ifc_create_lag_in_bits { 8287 u8 opcode[0x10]; 8288 u8 reserved_at_10[0x10]; 8289 8290 u8 reserved_at_20[0x10]; 8291 u8 op_mod[0x10]; 8292 8293 struct mlx5_ifc_lagc_bits ctx; 8294 }; 8295 8296 struct mlx5_ifc_modify_lag_out_bits { 8297 u8 status[0x8]; 8298 u8 reserved_at_8[0x18]; 8299 8300 u8 syndrome[0x20]; 8301 8302 u8 reserved_at_40[0x40]; 8303 }; 8304 8305 struct mlx5_ifc_modify_lag_in_bits { 8306 u8 opcode[0x10]; 8307 u8 reserved_at_10[0x10]; 8308 8309 u8 reserved_at_20[0x10]; 8310 u8 op_mod[0x10]; 8311 8312 u8 reserved_at_40[0x20]; 8313 u8 field_select[0x20]; 8314 8315 struct mlx5_ifc_lagc_bits ctx; 8316 }; 8317 8318 struct mlx5_ifc_query_lag_out_bits { 8319 u8 status[0x8]; 8320 u8 reserved_at_8[0x18]; 8321 8322 u8 syndrome[0x20]; 8323 8324 u8 reserved_at_40[0x40]; 8325 8326 struct mlx5_ifc_lagc_bits ctx; 8327 }; 8328 8329 struct mlx5_ifc_query_lag_in_bits { 8330 u8 opcode[0x10]; 8331 u8 reserved_at_10[0x10]; 8332 8333 u8 reserved_at_20[0x10]; 8334 u8 op_mod[0x10]; 8335 8336 u8 reserved_at_40[0x40]; 8337 }; 8338 8339 struct mlx5_ifc_destroy_lag_out_bits { 8340 u8 status[0x8]; 8341 u8 reserved_at_8[0x18]; 8342 8343 u8 syndrome[0x20]; 8344 8345 u8 reserved_at_40[0x40]; 8346 }; 8347 8348 struct mlx5_ifc_destroy_lag_in_bits { 8349 u8 opcode[0x10]; 8350 u8 reserved_at_10[0x10]; 8351 8352 u8 reserved_at_20[0x10]; 8353 u8 op_mod[0x10]; 8354 8355 u8 reserved_at_40[0x40]; 8356 }; 8357 8358 struct mlx5_ifc_create_vport_lag_out_bits { 8359 u8 status[0x8]; 8360 u8 reserved_at_8[0x18]; 8361 8362 u8 syndrome[0x20]; 8363 8364 u8 reserved_at_40[0x40]; 8365 }; 8366 8367 struct mlx5_ifc_create_vport_lag_in_bits { 8368 u8 opcode[0x10]; 8369 u8 reserved_at_10[0x10]; 8370 8371 u8 reserved_at_20[0x10]; 8372 u8 op_mod[0x10]; 8373 8374 u8 reserved_at_40[0x40]; 8375 }; 8376 8377 struct mlx5_ifc_destroy_vport_lag_out_bits { 8378 u8 status[0x8]; 8379 u8 reserved_at_8[0x18]; 8380 8381 u8 syndrome[0x20]; 8382 8383 u8 reserved_at_40[0x40]; 8384 }; 8385 8386 struct mlx5_ifc_destroy_vport_lag_in_bits { 8387 u8 opcode[0x10]; 8388 u8 reserved_at_10[0x10]; 8389 8390 u8 reserved_at_20[0x10]; 8391 u8 op_mod[0x10]; 8392 8393 u8 reserved_at_40[0x40]; 8394 }; 8395 8396 #endif /* MLX5_IFC_H */ 8397