1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 #ifndef MLX5_IFC_H 33 #define MLX5_IFC_H 34 35 #include "mlx5_ifc_fpga.h" 36 37 enum { 38 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0, 39 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1, 40 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2, 41 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3, 42 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13, 43 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14, 44 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c, 45 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d, 46 MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4, 47 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5, 48 MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED = 0x7, 49 MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT = 0xc, 50 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10, 51 MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR = 0x11, 52 MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR = 0x12, 53 MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR = 0x8, 54 MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE = 0x9, 55 MLX5_EVENT_TYPE_CODING_GPIO_EVENT = 0x15, 56 MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19, 57 MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a, 58 MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT = 0x1b, 59 MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT = 0x1f, 60 MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa, 61 MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb, 62 MLX5_EVENT_TYPE_CODING_FPGA_ERROR = 0x20, 63 MLX5_EVENT_TYPE_CODING_FPGA_QP_ERROR = 0x21 64 }; 65 66 enum { 67 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0, 68 MLX5_SET_HCA_CAP_OP_MOD_ETHERNET_OFFLOADS = 0x1, 69 MLX5_SET_HCA_CAP_OP_MOD_ODP = 0x2, 70 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3, 71 MLX5_SET_HCA_CAP_OP_MOD_ROCE = 0x4, 72 MLX5_SET_HCA_CAP_OP_MOD_IPSEC = 0x15, 73 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE2 = 0x20, 74 MLX5_SET_HCA_CAP_OP_MOD_PORT_SELECTION = 0x25, 75 }; 76 77 enum { 78 MLX5_SHARED_RESOURCE_UID = 0xffff, 79 }; 80 81 enum { 82 MLX5_OBJ_TYPE_SW_ICM = 0x0008, 83 MLX5_OBJ_TYPE_GENEVE_TLV_OPT = 0x000b, 84 MLX5_OBJ_TYPE_VIRTIO_NET_Q = 0x000d, 85 MLX5_OBJ_TYPE_VIRTIO_Q_COUNTERS = 0x001c, 86 MLX5_OBJ_TYPE_MATCH_DEFINER = 0x0018, 87 MLX5_OBJ_TYPE_HEADER_MODIFY_ARGUMENT = 0x23, 88 MLX5_OBJ_TYPE_STC = 0x0040, 89 MLX5_OBJ_TYPE_RTC = 0x0041, 90 MLX5_OBJ_TYPE_STE = 0x0042, 91 MLX5_OBJ_TYPE_MODIFY_HDR_PATTERN = 0x0043, 92 MLX5_OBJ_TYPE_PAGE_TRACK = 0x46, 93 MLX5_OBJ_TYPE_MKEY = 0xff01, 94 MLX5_OBJ_TYPE_QP = 0xff02, 95 MLX5_OBJ_TYPE_PSV = 0xff03, 96 MLX5_OBJ_TYPE_RMP = 0xff04, 97 MLX5_OBJ_TYPE_XRC_SRQ = 0xff05, 98 MLX5_OBJ_TYPE_RQ = 0xff06, 99 MLX5_OBJ_TYPE_SQ = 0xff07, 100 MLX5_OBJ_TYPE_TIR = 0xff08, 101 MLX5_OBJ_TYPE_TIS = 0xff09, 102 MLX5_OBJ_TYPE_DCT = 0xff0a, 103 MLX5_OBJ_TYPE_XRQ = 0xff0b, 104 MLX5_OBJ_TYPE_RQT = 0xff0e, 105 MLX5_OBJ_TYPE_FLOW_COUNTER = 0xff0f, 106 MLX5_OBJ_TYPE_CQ = 0xff10, 107 MLX5_OBJ_TYPE_FT_ALIAS = 0xff15, 108 }; 109 110 enum { 111 MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM = (1ULL << MLX5_OBJ_TYPE_SW_ICM), 112 MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT = (1ULL << 11), 113 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q = (1ULL << 13), 114 MLX5_GENERAL_OBJ_TYPES_CAP_HEADER_MODIFY_ARGUMENT = 115 (1ULL << MLX5_OBJ_TYPE_HEADER_MODIFY_ARGUMENT), 116 MLX5_GENERAL_OBJ_TYPES_CAP_MACSEC_OFFLOAD = (1ULL << 39), 117 }; 118 119 enum { 120 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100, 121 MLX5_CMD_OP_QUERY_ADAPTER = 0x101, 122 MLX5_CMD_OP_INIT_HCA = 0x102, 123 MLX5_CMD_OP_TEARDOWN_HCA = 0x103, 124 MLX5_CMD_OP_ENABLE_HCA = 0x104, 125 MLX5_CMD_OP_DISABLE_HCA = 0x105, 126 MLX5_CMD_OP_QUERY_PAGES = 0x107, 127 MLX5_CMD_OP_MANAGE_PAGES = 0x108, 128 MLX5_CMD_OP_SET_HCA_CAP = 0x109, 129 MLX5_CMD_OP_QUERY_ISSI = 0x10a, 130 MLX5_CMD_OP_SET_ISSI = 0x10b, 131 MLX5_CMD_OP_SET_DRIVER_VERSION = 0x10d, 132 MLX5_CMD_OP_QUERY_SF_PARTITION = 0x111, 133 MLX5_CMD_OP_ALLOC_SF = 0x113, 134 MLX5_CMD_OP_DEALLOC_SF = 0x114, 135 MLX5_CMD_OP_SUSPEND_VHCA = 0x115, 136 MLX5_CMD_OP_RESUME_VHCA = 0x116, 137 MLX5_CMD_OP_QUERY_VHCA_MIGRATION_STATE = 0x117, 138 MLX5_CMD_OP_SAVE_VHCA_STATE = 0x118, 139 MLX5_CMD_OP_LOAD_VHCA_STATE = 0x119, 140 MLX5_CMD_OP_CREATE_MKEY = 0x200, 141 MLX5_CMD_OP_QUERY_MKEY = 0x201, 142 MLX5_CMD_OP_DESTROY_MKEY = 0x202, 143 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203, 144 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204, 145 MLX5_CMD_OP_ALLOC_MEMIC = 0x205, 146 MLX5_CMD_OP_DEALLOC_MEMIC = 0x206, 147 MLX5_CMD_OP_MODIFY_MEMIC = 0x207, 148 MLX5_CMD_OP_CREATE_EQ = 0x301, 149 MLX5_CMD_OP_DESTROY_EQ = 0x302, 150 MLX5_CMD_OP_QUERY_EQ = 0x303, 151 MLX5_CMD_OP_GEN_EQE = 0x304, 152 MLX5_CMD_OP_CREATE_CQ = 0x400, 153 MLX5_CMD_OP_DESTROY_CQ = 0x401, 154 MLX5_CMD_OP_QUERY_CQ = 0x402, 155 MLX5_CMD_OP_MODIFY_CQ = 0x403, 156 MLX5_CMD_OP_CREATE_QP = 0x500, 157 MLX5_CMD_OP_DESTROY_QP = 0x501, 158 MLX5_CMD_OP_RST2INIT_QP = 0x502, 159 MLX5_CMD_OP_INIT2RTR_QP = 0x503, 160 MLX5_CMD_OP_RTR2RTS_QP = 0x504, 161 MLX5_CMD_OP_RTS2RTS_QP = 0x505, 162 MLX5_CMD_OP_SQERR2RTS_QP = 0x506, 163 MLX5_CMD_OP_2ERR_QP = 0x507, 164 MLX5_CMD_OP_2RST_QP = 0x50a, 165 MLX5_CMD_OP_QUERY_QP = 0x50b, 166 MLX5_CMD_OP_SQD_RTS_QP = 0x50c, 167 MLX5_CMD_OP_INIT2INIT_QP = 0x50e, 168 MLX5_CMD_OP_CREATE_PSV = 0x600, 169 MLX5_CMD_OP_DESTROY_PSV = 0x601, 170 MLX5_CMD_OP_CREATE_SRQ = 0x700, 171 MLX5_CMD_OP_DESTROY_SRQ = 0x701, 172 MLX5_CMD_OP_QUERY_SRQ = 0x702, 173 MLX5_CMD_OP_ARM_RQ = 0x703, 174 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705, 175 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706, 176 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707, 177 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708, 178 MLX5_CMD_OP_CREATE_DCT = 0x710, 179 MLX5_CMD_OP_DESTROY_DCT = 0x711, 180 MLX5_CMD_OP_DRAIN_DCT = 0x712, 181 MLX5_CMD_OP_QUERY_DCT = 0x713, 182 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714, 183 MLX5_CMD_OP_CREATE_XRQ = 0x717, 184 MLX5_CMD_OP_DESTROY_XRQ = 0x718, 185 MLX5_CMD_OP_QUERY_XRQ = 0x719, 186 MLX5_CMD_OP_ARM_XRQ = 0x71a, 187 MLX5_CMD_OP_QUERY_XRQ_DC_PARAMS_ENTRY = 0x725, 188 MLX5_CMD_OP_SET_XRQ_DC_PARAMS_ENTRY = 0x726, 189 MLX5_CMD_OP_QUERY_XRQ_ERROR_PARAMS = 0x727, 190 MLX5_CMD_OP_RELEASE_XRQ_ERROR = 0x729, 191 MLX5_CMD_OP_MODIFY_XRQ = 0x72a, 192 MLX5_CMD_OPCODE_QUERY_DELEGATED_VHCA = 0x732, 193 MLX5_CMD_OPCODE_CREATE_ESW_VPORT = 0x733, 194 MLX5_CMD_OPCODE_DESTROY_ESW_VPORT = 0x734, 195 MLX5_CMD_OP_QUERY_ESW_FUNCTIONS = 0x740, 196 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750, 197 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751, 198 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752, 199 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753, 200 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754, 201 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755, 202 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760, 203 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761, 204 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762, 205 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763, 206 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764, 207 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765, 208 MLX5_CMD_OP_QUERY_VNIC_ENV = 0x76f, 209 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770, 210 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771, 211 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772, 212 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773, 213 MLX5_CMD_OP_SET_MONITOR_COUNTER = 0x774, 214 MLX5_CMD_OP_ARM_MONITOR_COUNTER = 0x775, 215 MLX5_CMD_OP_SET_PP_RATE_LIMIT = 0x780, 216 MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781, 217 MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT = 0x782, 218 MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT = 0x783, 219 MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT = 0x784, 220 MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT = 0x785, 221 MLX5_CMD_OP_CREATE_QOS_PARA_VPORT = 0x786, 222 MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT = 0x787, 223 MLX5_CMD_OP_ALLOC_PD = 0x800, 224 MLX5_CMD_OP_DEALLOC_PD = 0x801, 225 MLX5_CMD_OP_ALLOC_UAR = 0x802, 226 MLX5_CMD_OP_DEALLOC_UAR = 0x803, 227 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804, 228 MLX5_CMD_OP_ACCESS_REG = 0x805, 229 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806, 230 MLX5_CMD_OP_DETACH_FROM_MCG = 0x807, 231 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a, 232 MLX5_CMD_OP_MAD_IFC = 0x50d, 233 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b, 234 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c, 235 MLX5_CMD_OP_NOP = 0x80d, 236 MLX5_CMD_OP_ALLOC_XRCD = 0x80e, 237 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f, 238 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816, 239 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817, 240 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822, 241 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823, 242 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824, 243 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825, 244 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826, 245 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827, 246 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828, 247 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829, 248 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a, 249 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b, 250 MLX5_CMD_OP_SET_WOL_ROL = 0x830, 251 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831, 252 MLX5_CMD_OP_CREATE_LAG = 0x840, 253 MLX5_CMD_OP_MODIFY_LAG = 0x841, 254 MLX5_CMD_OP_QUERY_LAG = 0x842, 255 MLX5_CMD_OP_DESTROY_LAG = 0x843, 256 MLX5_CMD_OP_CREATE_VPORT_LAG = 0x844, 257 MLX5_CMD_OP_DESTROY_VPORT_LAG = 0x845, 258 MLX5_CMD_OP_CREATE_TIR = 0x900, 259 MLX5_CMD_OP_MODIFY_TIR = 0x901, 260 MLX5_CMD_OP_DESTROY_TIR = 0x902, 261 MLX5_CMD_OP_QUERY_TIR = 0x903, 262 MLX5_CMD_OP_CREATE_SQ = 0x904, 263 MLX5_CMD_OP_MODIFY_SQ = 0x905, 264 MLX5_CMD_OP_DESTROY_SQ = 0x906, 265 MLX5_CMD_OP_QUERY_SQ = 0x907, 266 MLX5_CMD_OP_CREATE_RQ = 0x908, 267 MLX5_CMD_OP_MODIFY_RQ = 0x909, 268 MLX5_CMD_OP_SET_DELAY_DROP_PARAMS = 0x910, 269 MLX5_CMD_OP_DESTROY_RQ = 0x90a, 270 MLX5_CMD_OP_QUERY_RQ = 0x90b, 271 MLX5_CMD_OP_CREATE_RMP = 0x90c, 272 MLX5_CMD_OP_MODIFY_RMP = 0x90d, 273 MLX5_CMD_OP_DESTROY_RMP = 0x90e, 274 MLX5_CMD_OP_QUERY_RMP = 0x90f, 275 MLX5_CMD_OP_CREATE_TIS = 0x912, 276 MLX5_CMD_OP_MODIFY_TIS = 0x913, 277 MLX5_CMD_OP_DESTROY_TIS = 0x914, 278 MLX5_CMD_OP_QUERY_TIS = 0x915, 279 MLX5_CMD_OP_CREATE_RQT = 0x916, 280 MLX5_CMD_OP_MODIFY_RQT = 0x917, 281 MLX5_CMD_OP_DESTROY_RQT = 0x918, 282 MLX5_CMD_OP_QUERY_RQT = 0x919, 283 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f, 284 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930, 285 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931, 286 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932, 287 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933, 288 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934, 289 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935, 290 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936, 291 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937, 292 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938, 293 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939, 294 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a, 295 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b, 296 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c, 297 MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT = 0x93d, 298 MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT = 0x93e, 299 MLX5_CMD_OP_QUERY_PACKET_REFORMAT_CONTEXT = 0x93f, 300 MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT = 0x940, 301 MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941, 302 MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT = 0x942, 303 MLX5_CMD_OP_FPGA_CREATE_QP = 0x960, 304 MLX5_CMD_OP_FPGA_MODIFY_QP = 0x961, 305 MLX5_CMD_OP_FPGA_QUERY_QP = 0x962, 306 MLX5_CMD_OP_FPGA_DESTROY_QP = 0x963, 307 MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS = 0x964, 308 MLX5_CMD_OP_CREATE_GENERAL_OBJECT = 0xa00, 309 MLX5_CMD_OP_MODIFY_GENERAL_OBJECT = 0xa01, 310 MLX5_CMD_OP_QUERY_GENERAL_OBJECT = 0xa02, 311 MLX5_CMD_OP_DESTROY_GENERAL_OBJECT = 0xa03, 312 MLX5_CMD_OP_CREATE_UCTX = 0xa04, 313 MLX5_CMD_OP_DESTROY_UCTX = 0xa06, 314 MLX5_CMD_OP_CREATE_UMEM = 0xa08, 315 MLX5_CMD_OP_DESTROY_UMEM = 0xa0a, 316 MLX5_CMD_OP_SYNC_STEERING = 0xb00, 317 MLX5_CMD_OP_PSP_GEN_SPI = 0xb10, 318 MLX5_CMD_OP_PSP_ROTATE_KEY = 0xb11, 319 MLX5_CMD_OP_QUERY_VHCA_STATE = 0xb0d, 320 MLX5_CMD_OP_MODIFY_VHCA_STATE = 0xb0e, 321 MLX5_CMD_OP_SYNC_CRYPTO = 0xb12, 322 MLX5_CMD_OP_ALLOW_OTHER_VHCA_ACCESS = 0xb16, 323 MLX5_CMD_OP_GENERATE_WQE = 0xb17, 324 MLX5_CMD_OPCODE_QUERY_VUID = 0xb22, 325 MLX5_CMD_OP_MAX 326 }; 327 328 /* Valid range for general commands that don't work over an object */ 329 enum { 330 MLX5_CMD_OP_GENERAL_START = 0xb00, 331 MLX5_CMD_OP_GENERAL_END = 0xd00, 332 }; 333 334 enum { 335 MLX5_FT_NIC_RX_2_NIC_RX_RDMA = BIT(0), 336 MLX5_FT_NIC_TX_RDMA_2_NIC_TX = BIT(1), 337 }; 338 339 enum { 340 MLX5_CMD_OP_MOD_UPDATE_HEADER_MODIFY_ARGUMENT = 0x1, 341 }; 342 343 struct mlx5_ifc_flow_table_fields_supported_bits { 344 u8 outer_dmac[0x1]; 345 u8 outer_smac[0x1]; 346 u8 outer_ether_type[0x1]; 347 u8 outer_ip_version[0x1]; 348 u8 outer_first_prio[0x1]; 349 u8 outer_first_cfi[0x1]; 350 u8 outer_first_vid[0x1]; 351 u8 outer_ipv4_ttl[0x1]; 352 u8 outer_second_prio[0x1]; 353 u8 outer_second_cfi[0x1]; 354 u8 outer_second_vid[0x1]; 355 u8 reserved_at_b[0x1]; 356 u8 outer_sip[0x1]; 357 u8 outer_dip[0x1]; 358 u8 outer_frag[0x1]; 359 u8 outer_ip_protocol[0x1]; 360 u8 outer_ip_ecn[0x1]; 361 u8 outer_ip_dscp[0x1]; 362 u8 outer_udp_sport[0x1]; 363 u8 outer_udp_dport[0x1]; 364 u8 outer_tcp_sport[0x1]; 365 u8 outer_tcp_dport[0x1]; 366 u8 outer_tcp_flags[0x1]; 367 u8 outer_gre_protocol[0x1]; 368 u8 outer_gre_key[0x1]; 369 u8 outer_vxlan_vni[0x1]; 370 u8 outer_geneve_vni[0x1]; 371 u8 outer_geneve_oam[0x1]; 372 u8 outer_geneve_protocol_type[0x1]; 373 u8 outer_geneve_opt_len[0x1]; 374 u8 source_vhca_port[0x1]; 375 u8 source_eswitch_port[0x1]; 376 377 u8 inner_dmac[0x1]; 378 u8 inner_smac[0x1]; 379 u8 inner_ether_type[0x1]; 380 u8 inner_ip_version[0x1]; 381 u8 inner_first_prio[0x1]; 382 u8 inner_first_cfi[0x1]; 383 u8 inner_first_vid[0x1]; 384 u8 reserved_at_27[0x1]; 385 u8 inner_second_prio[0x1]; 386 u8 inner_second_cfi[0x1]; 387 u8 inner_second_vid[0x1]; 388 u8 reserved_at_2b[0x1]; 389 u8 inner_sip[0x1]; 390 u8 inner_dip[0x1]; 391 u8 inner_frag[0x1]; 392 u8 inner_ip_protocol[0x1]; 393 u8 inner_ip_ecn[0x1]; 394 u8 inner_ip_dscp[0x1]; 395 u8 inner_udp_sport[0x1]; 396 u8 inner_udp_dport[0x1]; 397 u8 inner_tcp_sport[0x1]; 398 u8 inner_tcp_dport[0x1]; 399 u8 inner_tcp_flags[0x1]; 400 u8 reserved_at_37[0x9]; 401 402 u8 geneve_tlv_option_0_data[0x1]; 403 u8 geneve_tlv_option_0_exist[0x1]; 404 u8 reserved_at_42[0x3]; 405 u8 outer_first_mpls_over_udp[0x4]; 406 u8 outer_first_mpls_over_gre[0x4]; 407 u8 inner_first_mpls[0x4]; 408 u8 outer_first_mpls[0x4]; 409 u8 reserved_at_55[0x2]; 410 u8 outer_esp_spi[0x1]; 411 u8 reserved_at_58[0x2]; 412 u8 bth_dst_qp[0x1]; 413 u8 reserved_at_5b[0x5]; 414 415 u8 reserved_at_60[0x18]; 416 u8 metadata_reg_c_7[0x1]; 417 u8 metadata_reg_c_6[0x1]; 418 u8 metadata_reg_c_5[0x1]; 419 u8 metadata_reg_c_4[0x1]; 420 u8 metadata_reg_c_3[0x1]; 421 u8 metadata_reg_c_2[0x1]; 422 u8 metadata_reg_c_1[0x1]; 423 u8 metadata_reg_c_0[0x1]; 424 }; 425 426 /* Table 2170 - Flow Table Fields Supported 2 Format */ 427 struct mlx5_ifc_flow_table_fields_supported_2_bits { 428 u8 inner_l4_type_ext[0x1]; 429 u8 outer_l4_type_ext[0x1]; 430 u8 inner_l4_type[0x1]; 431 u8 outer_l4_type[0x1]; 432 u8 reserved_at_4[0xa]; 433 u8 bth_opcode[0x1]; 434 u8 reserved_at_f[0x1]; 435 u8 tunnel_header_0_1[0x1]; 436 u8 reserved_at_11[0xf]; 437 438 u8 reserved_at_20[0xf]; 439 u8 ipsec_next_header[0x1]; 440 u8 reserved_at_30[0x10]; 441 442 u8 reserved_at_40[0x40]; 443 }; 444 445 struct mlx5_ifc_flow_table_prop_layout_bits { 446 u8 ft_support[0x1]; 447 u8 reserved_at_1[0x1]; 448 u8 flow_counter[0x1]; 449 u8 flow_modify_en[0x1]; 450 u8 modify_root[0x1]; 451 u8 identified_miss_table_mode[0x1]; 452 u8 flow_table_modify[0x1]; 453 u8 reformat[0x1]; 454 u8 decap[0x1]; 455 u8 reset_root_to_default[0x1]; 456 u8 pop_vlan[0x1]; 457 u8 push_vlan[0x1]; 458 u8 reserved_at_c[0x1]; 459 u8 pop_vlan_2[0x1]; 460 u8 push_vlan_2[0x1]; 461 u8 reformat_and_vlan_action[0x1]; 462 u8 reserved_at_10[0x1]; 463 u8 sw_owner[0x1]; 464 u8 reformat_l3_tunnel_to_l2[0x1]; 465 u8 reformat_l2_to_l3_tunnel[0x1]; 466 u8 reformat_and_modify_action[0x1]; 467 u8 ignore_flow_level[0x1]; 468 u8 reserved_at_16[0x1]; 469 u8 table_miss_action_domain[0x1]; 470 u8 termination_table[0x1]; 471 u8 reformat_and_fwd_to_table[0x1]; 472 u8 forward_vhca_rx[0x1]; 473 u8 reserved_at_1b[0x1]; 474 u8 ipsec_encrypt[0x1]; 475 u8 ipsec_decrypt[0x1]; 476 u8 sw_owner_v2[0x1]; 477 u8 reserved_at_1f[0x1]; 478 479 u8 termination_table_raw_traffic[0x1]; 480 u8 reserved_at_21[0x1]; 481 u8 log_max_ft_size[0x6]; 482 u8 log_max_modify_header_context[0x8]; 483 u8 max_modify_header_actions[0x8]; 484 u8 max_ft_level[0x8]; 485 486 u8 reformat_add_esp_trasport[0x1]; 487 u8 reformat_l2_to_l3_esp_tunnel[0x1]; 488 u8 reformat_add_esp_transport_over_udp[0x1]; 489 u8 reformat_del_esp_trasport[0x1]; 490 u8 reformat_l3_esp_tunnel_to_l2[0x1]; 491 u8 reformat_del_esp_transport_over_udp[0x1]; 492 u8 execute_aso[0x1]; 493 u8 reserved_at_47[0x19]; 494 495 u8 reformat_l2_to_l3_psp_tunnel[0x1]; 496 u8 reformat_l3_psp_tunnel_to_l2[0x1]; 497 u8 reformat_insert[0x1]; 498 u8 reformat_remove[0x1]; 499 u8 macsec_encrypt[0x1]; 500 u8 macsec_decrypt[0x1]; 501 u8 psp_encrypt[0x1]; 502 u8 psp_decrypt[0x1]; 503 u8 reformat_add_macsec[0x1]; 504 u8 reformat_remove_macsec[0x1]; 505 u8 reparse[0x1]; 506 u8 reserved_at_6b[0x1]; 507 u8 cross_vhca_object[0x1]; 508 u8 reformat_l2_to_l3_audp_tunnel[0x1]; 509 u8 reformat_l3_audp_tunnel_to_l2[0x1]; 510 u8 ignore_flow_level_rtc_valid[0x1]; 511 u8 reserved_at_70[0x8]; 512 u8 log_max_ft_num[0x8]; 513 514 u8 reserved_at_80[0x10]; 515 u8 log_max_flow_counter[0x8]; 516 u8 log_max_destination[0x8]; 517 518 u8 reserved_at_a0[0x18]; 519 u8 log_max_flow[0x8]; 520 521 u8 reserved_at_c0[0x40]; 522 523 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support; 524 525 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support; 526 }; 527 528 struct mlx5_ifc_odp_per_transport_service_cap_bits { 529 u8 send[0x1]; 530 u8 receive[0x1]; 531 u8 write[0x1]; 532 u8 read[0x1]; 533 u8 atomic[0x1]; 534 u8 srq_receive[0x1]; 535 u8 reserved_at_6[0x1a]; 536 }; 537 538 struct mlx5_ifc_ipv4_layout_bits { 539 u8 reserved_at_0[0x60]; 540 541 u8 ipv4[0x20]; 542 }; 543 544 struct mlx5_ifc_ipv6_layout_bits { 545 u8 ipv6[16][0x8]; 546 }; 547 548 struct mlx5_ifc_ipv6_simple_layout_bits { 549 u8 ipv6_127_96[0x20]; 550 u8 ipv6_95_64[0x20]; 551 u8 ipv6_63_32[0x20]; 552 u8 ipv6_31_0[0x20]; 553 }; 554 555 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits { 556 struct mlx5_ifc_ipv6_simple_layout_bits ipv6_simple_layout; 557 struct mlx5_ifc_ipv6_layout_bits ipv6_layout; 558 struct mlx5_ifc_ipv4_layout_bits ipv4_layout; 559 u8 reserved_at_0[0x80]; 560 }; 561 562 enum { 563 MLX5_PACKET_L4_TYPE_NONE, 564 MLX5_PACKET_L4_TYPE_TCP, 565 MLX5_PACKET_L4_TYPE_UDP, 566 }; 567 568 enum { 569 MLX5_PACKET_L4_TYPE_EXT_NONE, 570 MLX5_PACKET_L4_TYPE_EXT_TCP, 571 MLX5_PACKET_L4_TYPE_EXT_UDP, 572 MLX5_PACKET_L4_TYPE_EXT_ICMP, 573 }; 574 575 struct mlx5_ifc_fte_match_set_lyr_2_4_bits { 576 u8 smac_47_16[0x20]; 577 578 u8 smac_15_0[0x10]; 579 u8 ethertype[0x10]; 580 581 u8 dmac_47_16[0x20]; 582 583 u8 dmac_15_0[0x10]; 584 u8 first_prio[0x3]; 585 u8 first_cfi[0x1]; 586 u8 first_vid[0xc]; 587 588 u8 ip_protocol[0x8]; 589 u8 ip_dscp[0x6]; 590 u8 ip_ecn[0x2]; 591 u8 cvlan_tag[0x1]; 592 u8 svlan_tag[0x1]; 593 u8 frag[0x1]; 594 u8 ip_version[0x4]; 595 u8 tcp_flags[0x9]; 596 597 u8 tcp_sport[0x10]; 598 u8 tcp_dport[0x10]; 599 600 u8 l4_type[0x2]; 601 u8 l4_type_ext[0x4]; 602 u8 reserved_at_c6[0xa]; 603 u8 ipv4_ihl[0x4]; 604 u8 reserved_at_d4[0x4]; 605 u8 ttl_hoplimit[0x8]; 606 607 u8 udp_sport[0x10]; 608 u8 udp_dport[0x10]; 609 610 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6; 611 612 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6; 613 }; 614 615 struct mlx5_ifc_nvgre_key_bits { 616 u8 hi[0x18]; 617 u8 lo[0x8]; 618 }; 619 620 union mlx5_ifc_gre_key_bits { 621 struct mlx5_ifc_nvgre_key_bits nvgre; 622 u8 key[0x20]; 623 }; 624 625 struct mlx5_ifc_fte_match_set_misc_bits { 626 u8 gre_c_present[0x1]; 627 u8 reserved_at_1[0x1]; 628 u8 gre_k_present[0x1]; 629 u8 gre_s_present[0x1]; 630 u8 source_vhca_port[0x4]; 631 u8 source_sqn[0x18]; 632 633 u8 source_eswitch_owner_vhca_id[0x10]; 634 u8 source_port[0x10]; 635 636 u8 outer_second_prio[0x3]; 637 u8 outer_second_cfi[0x1]; 638 u8 outer_second_vid[0xc]; 639 u8 inner_second_prio[0x3]; 640 u8 inner_second_cfi[0x1]; 641 u8 inner_second_vid[0xc]; 642 643 u8 outer_second_cvlan_tag[0x1]; 644 u8 inner_second_cvlan_tag[0x1]; 645 u8 outer_second_svlan_tag[0x1]; 646 u8 inner_second_svlan_tag[0x1]; 647 u8 reserved_at_64[0xc]; 648 u8 gre_protocol[0x10]; 649 650 union mlx5_ifc_gre_key_bits gre_key; 651 652 u8 vxlan_vni[0x18]; 653 u8 bth_opcode[0x8]; 654 655 u8 geneve_vni[0x18]; 656 u8 reserved_at_d8[0x6]; 657 u8 geneve_tlv_option_0_exist[0x1]; 658 u8 geneve_oam[0x1]; 659 660 u8 reserved_at_e0[0xc]; 661 u8 outer_ipv6_flow_label[0x14]; 662 663 u8 reserved_at_100[0xc]; 664 u8 inner_ipv6_flow_label[0x14]; 665 666 u8 reserved_at_120[0xa]; 667 u8 geneve_opt_len[0x6]; 668 u8 geneve_protocol_type[0x10]; 669 670 u8 reserved_at_140[0x8]; 671 u8 bth_dst_qp[0x18]; 672 u8 inner_esp_spi[0x20]; 673 u8 outer_esp_spi[0x20]; 674 u8 reserved_at_1a0[0x60]; 675 }; 676 677 struct mlx5_ifc_fte_match_mpls_bits { 678 u8 mpls_label[0x14]; 679 u8 mpls_exp[0x3]; 680 u8 mpls_s_bos[0x1]; 681 u8 mpls_ttl[0x8]; 682 }; 683 684 struct mlx5_ifc_fte_match_set_misc2_bits { 685 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls; 686 687 struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls; 688 689 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre; 690 691 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp; 692 693 u8 metadata_reg_c_7[0x20]; 694 695 u8 metadata_reg_c_6[0x20]; 696 697 u8 metadata_reg_c_5[0x20]; 698 699 u8 metadata_reg_c_4[0x20]; 700 701 u8 metadata_reg_c_3[0x20]; 702 703 u8 metadata_reg_c_2[0x20]; 704 705 u8 metadata_reg_c_1[0x20]; 706 707 u8 metadata_reg_c_0[0x20]; 708 709 u8 metadata_reg_a[0x20]; 710 711 u8 psp_syndrome[0x8]; 712 u8 macsec_syndrome[0x8]; 713 u8 ipsec_syndrome[0x8]; 714 u8 ipsec_next_header[0x8]; 715 716 u8 reserved_at_1c0[0x40]; 717 }; 718 719 struct mlx5_ifc_fte_match_set_misc3_bits { 720 u8 inner_tcp_seq_num[0x20]; 721 722 u8 outer_tcp_seq_num[0x20]; 723 724 u8 inner_tcp_ack_num[0x20]; 725 726 u8 outer_tcp_ack_num[0x20]; 727 728 u8 reserved_at_80[0x8]; 729 u8 outer_vxlan_gpe_vni[0x18]; 730 731 u8 outer_vxlan_gpe_next_protocol[0x8]; 732 u8 outer_vxlan_gpe_flags[0x8]; 733 u8 reserved_at_b0[0x10]; 734 735 u8 icmp_header_data[0x20]; 736 737 u8 icmpv6_header_data[0x20]; 738 739 u8 icmp_type[0x8]; 740 u8 icmp_code[0x8]; 741 u8 icmpv6_type[0x8]; 742 u8 icmpv6_code[0x8]; 743 744 u8 geneve_tlv_option_0_data[0x20]; 745 746 u8 gtpu_teid[0x20]; 747 748 u8 gtpu_msg_type[0x8]; 749 u8 gtpu_msg_flags[0x8]; 750 u8 reserved_at_170[0x10]; 751 752 u8 gtpu_dw_2[0x20]; 753 754 u8 gtpu_first_ext_dw_0[0x20]; 755 756 u8 gtpu_dw_0[0x20]; 757 758 u8 reserved_at_1e0[0x20]; 759 }; 760 761 struct mlx5_ifc_fte_match_set_misc4_bits { 762 u8 prog_sample_field_value_0[0x20]; 763 764 u8 prog_sample_field_id_0[0x20]; 765 766 u8 prog_sample_field_value_1[0x20]; 767 768 u8 prog_sample_field_id_1[0x20]; 769 770 u8 prog_sample_field_value_2[0x20]; 771 772 u8 prog_sample_field_id_2[0x20]; 773 774 u8 prog_sample_field_value_3[0x20]; 775 776 u8 prog_sample_field_id_3[0x20]; 777 778 u8 reserved_at_100[0x100]; 779 }; 780 781 struct mlx5_ifc_fte_match_set_misc5_bits { 782 u8 macsec_tag_0[0x20]; 783 784 u8 macsec_tag_1[0x20]; 785 786 u8 macsec_tag_2[0x20]; 787 788 u8 macsec_tag_3[0x20]; 789 790 u8 tunnel_header_0[0x20]; 791 792 u8 tunnel_header_1[0x20]; 793 794 u8 tunnel_header_2[0x20]; 795 796 u8 tunnel_header_3[0x20]; 797 798 u8 reserved_at_100[0x100]; 799 }; 800 801 struct mlx5_ifc_cmd_pas_bits { 802 u8 pa_h[0x20]; 803 804 u8 pa_l[0x14]; 805 u8 reserved_at_34[0xc]; 806 }; 807 808 struct mlx5_ifc_uint64_bits { 809 u8 hi[0x20]; 810 811 u8 lo[0x20]; 812 }; 813 814 enum { 815 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0, 816 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7, 817 MLX5_ADS_STAT_RATE_10GBPS = 0x8, 818 MLX5_ADS_STAT_RATE_30GBPS = 0x9, 819 MLX5_ADS_STAT_RATE_5GBPS = 0xa, 820 MLX5_ADS_STAT_RATE_20GBPS = 0xb, 821 MLX5_ADS_STAT_RATE_40GBPS = 0xc, 822 MLX5_ADS_STAT_RATE_60GBPS = 0xd, 823 MLX5_ADS_STAT_RATE_80GBPS = 0xe, 824 MLX5_ADS_STAT_RATE_120GBPS = 0xf, 825 }; 826 827 struct mlx5_ifc_ads_bits { 828 u8 fl[0x1]; 829 u8 free_ar[0x1]; 830 u8 reserved_at_2[0xe]; 831 u8 pkey_index[0x10]; 832 833 u8 plane_index[0x8]; 834 u8 grh[0x1]; 835 u8 mlid[0x7]; 836 u8 rlid[0x10]; 837 838 u8 ack_timeout[0x5]; 839 u8 reserved_at_45[0x3]; 840 u8 src_addr_index[0x8]; 841 u8 reserved_at_50[0x4]; 842 u8 stat_rate[0x4]; 843 u8 hop_limit[0x8]; 844 845 u8 reserved_at_60[0x4]; 846 u8 tclass[0x8]; 847 u8 flow_label[0x14]; 848 849 u8 rgid_rip[16][0x8]; 850 851 u8 reserved_at_100[0x4]; 852 u8 f_dscp[0x1]; 853 u8 f_ecn[0x1]; 854 u8 reserved_at_106[0x1]; 855 u8 f_eth_prio[0x1]; 856 u8 ecn[0x2]; 857 u8 dscp[0x6]; 858 u8 udp_sport[0x10]; 859 860 u8 dei_cfi[0x1]; 861 u8 eth_prio[0x3]; 862 u8 sl[0x4]; 863 u8 vhca_port_num[0x8]; 864 u8 rmac_47_32[0x10]; 865 866 u8 rmac_31_0[0x20]; 867 }; 868 869 struct mlx5_ifc_flow_table_nic_cap_bits { 870 u8 nic_rx_multi_path_tirs[0x1]; 871 u8 nic_rx_multi_path_tirs_fts[0x1]; 872 u8 allow_sniffer_and_nic_rx_shared_tir[0x1]; 873 u8 reserved_at_3[0x4]; 874 u8 sw_owner_reformat_supported[0x1]; 875 u8 reserved_at_8[0x18]; 876 877 u8 encap_general_header[0x1]; 878 u8 reserved_at_21[0xa]; 879 u8 log_max_packet_reformat_context[0x5]; 880 u8 reserved_at_30[0x6]; 881 u8 max_encap_header_size[0xa]; 882 u8 reserved_at_40[0x1c0]; 883 884 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive; 885 886 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_rdma; 887 888 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer; 889 890 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit; 891 892 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_rdma; 893 894 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer; 895 896 u8 reserved_at_e00[0x600]; 897 898 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_receive; 899 900 u8 reserved_at_1480[0x80]; 901 902 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_receive_rdma; 903 904 u8 reserved_at_1580[0x280]; 905 906 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_transmit_rdma; 907 908 u8 reserved_at_1880[0x780]; 909 910 u8 sw_steering_nic_rx_action_drop_icm_address[0x40]; 911 912 u8 sw_steering_nic_tx_action_drop_icm_address[0x40]; 913 914 u8 sw_steering_nic_tx_action_allow_icm_address[0x40]; 915 916 u8 reserved_at_20c0[0x5f40]; 917 }; 918 919 struct mlx5_ifc_port_selection_cap_bits { 920 u8 reserved_at_0[0x10]; 921 u8 port_select_flow_table[0x1]; 922 u8 reserved_at_11[0x1]; 923 u8 port_select_flow_table_bypass[0x1]; 924 u8 reserved_at_13[0xd]; 925 926 u8 reserved_at_20[0x1e0]; 927 928 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_port_selection; 929 930 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_port_selection; 931 932 u8 reserved_at_480[0x7b80]; 933 }; 934 935 enum { 936 MLX5_FDB_TO_VPORT_REG_C_0 = 0x01, 937 MLX5_FDB_TO_VPORT_REG_C_1 = 0x02, 938 MLX5_FDB_TO_VPORT_REG_C_2 = 0x04, 939 MLX5_FDB_TO_VPORT_REG_C_3 = 0x08, 940 MLX5_FDB_TO_VPORT_REG_C_4 = 0x10, 941 MLX5_FDB_TO_VPORT_REG_C_5 = 0x20, 942 MLX5_FDB_TO_VPORT_REG_C_6 = 0x40, 943 MLX5_FDB_TO_VPORT_REG_C_7 = 0x80, 944 }; 945 946 struct mlx5_ifc_flow_table_eswitch_cap_bits { 947 u8 fdb_to_vport_reg_c_id[0x8]; 948 u8 reserved_at_8[0x5]; 949 u8 fdb_uplink_hairpin[0x1]; 950 u8 fdb_multi_path_any_table_limit_regc[0x1]; 951 u8 reserved_at_f[0x1]; 952 u8 fdb_dynamic_tunnel[0x1]; 953 u8 reserved_at_11[0x1]; 954 u8 fdb_multi_path_any_table[0x1]; 955 u8 reserved_at_13[0x2]; 956 u8 fdb_modify_header_fwd_to_table[0x1]; 957 u8 fdb_ipv4_ttl_modify[0x1]; 958 u8 flow_source[0x1]; 959 u8 reserved_at_18[0x2]; 960 u8 multi_fdb_encap[0x1]; 961 u8 egress_acl_forward_to_vport[0x1]; 962 u8 fdb_multi_path_to_table[0x1]; 963 u8 reserved_at_1d[0x3]; 964 965 u8 reserved_at_20[0x1e0]; 966 967 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb; 968 969 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress; 970 971 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress; 972 973 u8 reserved_at_800[0xC00]; 974 975 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_esw_fdb; 976 977 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_bitmask_support_2_esw_fdb; 978 979 u8 reserved_at_1500[0x300]; 980 981 u8 sw_steering_fdb_action_drop_icm_address_rx[0x40]; 982 983 u8 sw_steering_fdb_action_drop_icm_address_tx[0x40]; 984 985 u8 sw_steering_uplink_icm_address_rx[0x40]; 986 987 u8 sw_steering_uplink_icm_address_tx[0x40]; 988 989 u8 reserved_at_1900[0x6700]; 990 }; 991 992 struct mlx5_ifc_wqe_based_flow_table_cap_bits { 993 u8 reserved_at_0[0x3]; 994 u8 log_max_num_ste[0x5]; 995 u8 reserved_at_8[0x3]; 996 u8 log_max_num_stc[0x5]; 997 u8 reserved_at_10[0x3]; 998 u8 log_max_num_rtc[0x5]; 999 u8 reserved_at_18[0x3]; 1000 u8 log_max_num_header_modify_pattern[0x5]; 1001 1002 u8 rtc_hash_split_table[0x1]; 1003 u8 rtc_linear_lookup_table[0x1]; 1004 u8 reserved_at_22[0x1]; 1005 u8 stc_alloc_log_granularity[0x5]; 1006 u8 reserved_at_28[0x3]; 1007 u8 stc_alloc_log_max[0x5]; 1008 u8 reserved_at_30[0x3]; 1009 u8 ste_alloc_log_granularity[0x5]; 1010 u8 reserved_at_38[0x3]; 1011 u8 ste_alloc_log_max[0x5]; 1012 1013 u8 reserved_at_40[0xb]; 1014 u8 rtc_reparse_mode[0x5]; 1015 u8 reserved_at_50[0x3]; 1016 u8 rtc_index_mode[0x5]; 1017 u8 reserved_at_58[0x3]; 1018 u8 rtc_log_depth_max[0x5]; 1019 1020 u8 reserved_at_60[0x10]; 1021 u8 ste_format[0x10]; 1022 1023 u8 stc_action_type[0x80]; 1024 1025 u8 header_insert_type[0x10]; 1026 u8 header_remove_type[0x10]; 1027 1028 u8 trivial_match_definer[0x20]; 1029 1030 u8 reserved_at_140[0x1b]; 1031 u8 rtc_max_num_hash_definer_gen_wqe[0x5]; 1032 1033 u8 reserved_at_160[0x18]; 1034 u8 access_index_mode[0x8]; 1035 1036 u8 reserved_at_180[0x10]; 1037 u8 ste_format_gen_wqe[0x10]; 1038 1039 u8 linear_match_definer_reg_c3[0x20]; 1040 1041 u8 fdb_jump_to_tir_stc[0x1]; 1042 u8 reserved_at_1c1[0x1f]; 1043 }; 1044 1045 struct mlx5_ifc_esw_cap_bits { 1046 u8 reserved_at_0[0x1d]; 1047 u8 merged_eswitch[0x1]; 1048 u8 reserved_at_1e[0x2]; 1049 1050 u8 reserved_at_20[0x40]; 1051 1052 u8 esw_manager_vport_number_valid[0x1]; 1053 u8 reserved_at_61[0xf]; 1054 u8 esw_manager_vport_number[0x10]; 1055 1056 u8 reserved_at_80[0x780]; 1057 }; 1058 1059 enum { 1060 MLX5_COUNTER_SOURCE_ESWITCH = 0x0, 1061 MLX5_COUNTER_FLOW_ESWITCH = 0x1, 1062 }; 1063 1064 struct mlx5_ifc_e_switch_cap_bits { 1065 u8 vport_svlan_strip[0x1]; 1066 u8 vport_cvlan_strip[0x1]; 1067 u8 vport_svlan_insert[0x1]; 1068 u8 vport_cvlan_insert_if_not_exist[0x1]; 1069 u8 vport_cvlan_insert_overwrite[0x1]; 1070 u8 reserved_at_5[0x1]; 1071 u8 vport_cvlan_insert_always[0x1]; 1072 u8 esw_shared_ingress_acl[0x1]; 1073 u8 esw_uplink_ingress_acl[0x1]; 1074 u8 root_ft_on_other_esw[0x1]; 1075 u8 reserved_at_a[0x1]; 1076 u8 esw_vport_state_max_tx_speed[0x1]; 1077 u8 reserved_at_c[0xd]; 1078 u8 esw_functions_changed[0x1]; 1079 u8 reserved_at_1a[0x1]; 1080 u8 ecpf_vport_exists[0x1]; 1081 u8 counter_eswitch_affinity[0x1]; 1082 u8 merged_eswitch[0x1]; 1083 u8 nic_vport_node_guid_modify[0x1]; 1084 u8 nic_vport_port_guid_modify[0x1]; 1085 1086 u8 vxlan_encap_decap[0x1]; 1087 u8 nvgre_encap_decap[0x1]; 1088 u8 reserved_at_22[0x1]; 1089 u8 log_max_fdb_encap_uplink[0x5]; 1090 u8 reserved_at_21[0x3]; 1091 u8 log_max_packet_reformat_context[0x5]; 1092 u8 reserved_2b[0x6]; 1093 u8 max_encap_header_size[0xa]; 1094 1095 u8 reserved_at_40[0xb]; 1096 u8 log_max_esw_sf[0x5]; 1097 u8 esw_sf_base_id[0x10]; 1098 1099 u8 reserved_at_60[0x7a0]; 1100 1101 }; 1102 1103 struct mlx5_ifc_qos_cap_bits { 1104 u8 packet_pacing[0x1]; 1105 u8 esw_scheduling[0x1]; 1106 u8 esw_bw_share[0x1]; 1107 u8 esw_rate_limit[0x1]; 1108 u8 reserved_at_4[0x1]; 1109 u8 packet_pacing_burst_bound[0x1]; 1110 u8 packet_pacing_typical_size[0x1]; 1111 u8 reserved_at_7[0x1]; 1112 u8 nic_sq_scheduling[0x1]; 1113 u8 nic_bw_share[0x1]; 1114 u8 nic_rate_limit[0x1]; 1115 u8 packet_pacing_uid[0x1]; 1116 u8 log_esw_max_sched_depth[0x4]; 1117 u8 reserved_at_10[0x10]; 1118 1119 u8 reserved_at_20[0x9]; 1120 u8 esw_cross_esw_sched[0x1]; 1121 u8 reserved_at_2a[0x1]; 1122 u8 log_max_qos_nic_queue_group[0x5]; 1123 u8 reserved_at_30[0x10]; 1124 1125 u8 packet_pacing_max_rate[0x20]; 1126 1127 u8 packet_pacing_min_rate[0x20]; 1128 1129 u8 reserved_at_80[0xb]; 1130 u8 log_esw_max_rate_limit[0x5]; 1131 u8 packet_pacing_rate_table_size[0x10]; 1132 1133 u8 esw_element_type[0x10]; 1134 u8 esw_tsar_type[0x10]; 1135 1136 u8 reserved_at_c0[0x10]; 1137 u8 max_qos_para_vport[0x10]; 1138 1139 u8 max_tsar_bw_share[0x20]; 1140 1141 u8 nic_element_type[0x10]; 1142 u8 nic_tsar_type[0x10]; 1143 1144 u8 reserved_at_120[0x3]; 1145 u8 log_meter_aso_granularity[0x5]; 1146 u8 reserved_at_128[0x3]; 1147 u8 log_meter_aso_max_alloc[0x5]; 1148 u8 reserved_at_130[0x3]; 1149 u8 log_max_num_meter_aso[0x5]; 1150 u8 reserved_at_138[0x8]; 1151 1152 u8 reserved_at_140[0x6c0]; 1153 }; 1154 1155 struct mlx5_ifc_debug_cap_bits { 1156 u8 core_dump_general[0x1]; 1157 u8 core_dump_qp[0x1]; 1158 u8 reserved_at_2[0x7]; 1159 u8 resource_dump[0x1]; 1160 u8 reserved_at_a[0x16]; 1161 1162 u8 reserved_at_20[0x2]; 1163 u8 stall_detect[0x1]; 1164 u8 reserved_at_23[0x1d]; 1165 1166 u8 reserved_at_40[0x7c0]; 1167 }; 1168 1169 struct mlx5_ifc_per_protocol_networking_offload_caps_bits { 1170 u8 csum_cap[0x1]; 1171 u8 vlan_cap[0x1]; 1172 u8 lro_cap[0x1]; 1173 u8 lro_psh_flag[0x1]; 1174 u8 lro_time_stamp[0x1]; 1175 u8 reserved_at_5[0x2]; 1176 u8 wqe_vlan_insert[0x1]; 1177 u8 self_lb_en_modifiable[0x1]; 1178 u8 reserved_at_9[0x2]; 1179 u8 max_lso_cap[0x5]; 1180 u8 multi_pkt_send_wqe[0x2]; 1181 u8 wqe_inline_mode[0x2]; 1182 u8 rss_ind_tbl_cap[0x4]; 1183 u8 reg_umr_sq[0x1]; 1184 u8 scatter_fcs[0x1]; 1185 u8 enhanced_multi_pkt_send_wqe[0x1]; 1186 u8 tunnel_lso_const_out_ip_id[0x1]; 1187 u8 tunnel_lro_gre[0x1]; 1188 u8 tunnel_lro_vxlan[0x1]; 1189 u8 tunnel_stateless_gre[0x1]; 1190 u8 tunnel_stateless_vxlan[0x1]; 1191 1192 u8 swp[0x1]; 1193 u8 swp_csum[0x1]; 1194 u8 swp_lso[0x1]; 1195 u8 cqe_checksum_full[0x1]; 1196 u8 tunnel_stateless_geneve_tx[0x1]; 1197 u8 tunnel_stateless_mpls_over_udp[0x1]; 1198 u8 tunnel_stateless_mpls_over_gre[0x1]; 1199 u8 tunnel_stateless_vxlan_gpe[0x1]; 1200 u8 tunnel_stateless_ipv4_over_vxlan[0x1]; 1201 u8 tunnel_stateless_ip_over_ip[0x1]; 1202 u8 insert_trailer[0x1]; 1203 u8 reserved_at_2b[0x1]; 1204 u8 tunnel_stateless_ip_over_ip_rx[0x1]; 1205 u8 tunnel_stateless_ip_over_ip_tx[0x1]; 1206 u8 reserved_at_2e[0x2]; 1207 u8 max_vxlan_udp_ports[0x8]; 1208 u8 swp_csum_l4_partial[0x1]; 1209 u8 reserved_at_39[0x5]; 1210 u8 max_geneve_opt_len[0x1]; 1211 u8 tunnel_stateless_geneve_rx[0x1]; 1212 1213 u8 reserved_at_40[0x10]; 1214 u8 lro_min_mss_size[0x10]; 1215 1216 u8 reserved_at_60[0x120]; 1217 1218 u8 lro_timer_supported_periods[4][0x20]; 1219 1220 u8 reserved_at_200[0x600]; 1221 }; 1222 1223 enum { 1224 MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING = 0x0, 1225 MLX5_TIMESTAMP_FORMAT_CAP_REAL_TIME = 0x1, 1226 MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING_AND_REAL_TIME = 0x2, 1227 }; 1228 1229 struct mlx5_ifc_roce_cap_bits { 1230 u8 roce_apm[0x1]; 1231 u8 reserved_at_1[0x3]; 1232 u8 sw_r_roce_src_udp_port[0x1]; 1233 u8 fl_rc_qp_when_roce_disabled[0x1]; 1234 u8 fl_rc_qp_when_roce_enabled[0x1]; 1235 u8 roce_cc_general[0x1]; 1236 u8 qp_ooo_transmit_default[0x1]; 1237 u8 reserved_at_9[0x15]; 1238 u8 qp_ts_format[0x2]; 1239 1240 u8 reserved_at_20[0x60]; 1241 1242 u8 reserved_at_80[0xc]; 1243 u8 l3_type[0x4]; 1244 u8 reserved_at_90[0x8]; 1245 u8 roce_version[0x8]; 1246 1247 u8 reserved_at_a0[0x10]; 1248 u8 r_roce_dest_udp_port[0x10]; 1249 1250 u8 r_roce_max_src_udp_port[0x10]; 1251 u8 r_roce_min_src_udp_port[0x10]; 1252 1253 u8 reserved_at_e0[0x10]; 1254 u8 roce_address_table_size[0x10]; 1255 1256 u8 reserved_at_100[0x700]; 1257 }; 1258 1259 struct mlx5_ifc_sync_steering_in_bits { 1260 u8 opcode[0x10]; 1261 u8 uid[0x10]; 1262 1263 u8 reserved_at_20[0x10]; 1264 u8 op_mod[0x10]; 1265 1266 u8 reserved_at_40[0xc0]; 1267 }; 1268 1269 struct mlx5_ifc_sync_steering_out_bits { 1270 u8 status[0x8]; 1271 u8 reserved_at_8[0x18]; 1272 1273 u8 syndrome[0x20]; 1274 1275 u8 reserved_at_40[0x40]; 1276 }; 1277 1278 struct mlx5_ifc_sync_crypto_in_bits { 1279 u8 opcode[0x10]; 1280 u8 uid[0x10]; 1281 1282 u8 reserved_at_20[0x10]; 1283 u8 op_mod[0x10]; 1284 1285 u8 reserved_at_40[0x20]; 1286 1287 u8 reserved_at_60[0x10]; 1288 u8 crypto_type[0x10]; 1289 1290 u8 reserved_at_80[0x80]; 1291 }; 1292 1293 struct mlx5_ifc_sync_crypto_out_bits { 1294 u8 status[0x8]; 1295 u8 reserved_at_8[0x18]; 1296 1297 u8 syndrome[0x20]; 1298 1299 u8 reserved_at_40[0x40]; 1300 }; 1301 1302 struct mlx5_ifc_device_mem_cap_bits { 1303 u8 memic[0x1]; 1304 u8 reserved_at_1[0x1f]; 1305 1306 u8 reserved_at_20[0xb]; 1307 u8 log_min_memic_alloc_size[0x5]; 1308 u8 reserved_at_30[0x8]; 1309 u8 log_max_memic_addr_alignment[0x8]; 1310 1311 u8 memic_bar_start_addr[0x40]; 1312 1313 u8 memic_bar_size[0x20]; 1314 1315 u8 max_memic_size[0x20]; 1316 1317 u8 steering_sw_icm_start_address[0x40]; 1318 1319 u8 reserved_at_100[0x8]; 1320 u8 log_header_modify_sw_icm_size[0x8]; 1321 u8 reserved_at_110[0x2]; 1322 u8 log_sw_icm_alloc_granularity[0x6]; 1323 u8 log_steering_sw_icm_size[0x8]; 1324 1325 u8 log_indirect_encap_sw_icm_size[0x8]; 1326 u8 reserved_at_128[0x10]; 1327 u8 log_header_modify_pattern_sw_icm_size[0x8]; 1328 1329 u8 header_modify_sw_icm_start_address[0x40]; 1330 1331 u8 reserved_at_180[0x40]; 1332 1333 u8 header_modify_pattern_sw_icm_start_address[0x40]; 1334 1335 u8 memic_operations[0x20]; 1336 1337 u8 reserved_at_220[0x20]; 1338 1339 u8 indirect_encap_sw_icm_start_address[0x40]; 1340 1341 u8 reserved_at_280[0x580]; 1342 }; 1343 1344 struct mlx5_ifc_device_event_cap_bits { 1345 u8 user_affiliated_events[4][0x40]; 1346 1347 u8 user_unaffiliated_events[4][0x40]; 1348 }; 1349 1350 struct mlx5_ifc_virtio_emulation_cap_bits { 1351 u8 desc_tunnel_offload_type[0x1]; 1352 u8 eth_frame_offload_type[0x1]; 1353 u8 virtio_version_1_0[0x1]; 1354 u8 device_features_bits_mask[0xd]; 1355 u8 event_mode[0x8]; 1356 u8 virtio_queue_type[0x8]; 1357 1358 u8 max_tunnel_desc[0x10]; 1359 u8 reserved_at_30[0x3]; 1360 u8 log_doorbell_stride[0x5]; 1361 u8 reserved_at_38[0x3]; 1362 u8 log_doorbell_bar_size[0x5]; 1363 1364 u8 doorbell_bar_offset[0x40]; 1365 1366 u8 max_emulated_devices[0x8]; 1367 u8 max_num_virtio_queues[0x18]; 1368 1369 u8 reserved_at_a0[0x20]; 1370 1371 u8 reserved_at_c0[0x13]; 1372 u8 desc_group_mkey_supported[0x1]; 1373 u8 freeze_to_rdy_supported[0x1]; 1374 u8 reserved_at_d5[0xb]; 1375 1376 u8 reserved_at_e0[0x20]; 1377 1378 u8 umem_1_buffer_param_a[0x20]; 1379 1380 u8 umem_1_buffer_param_b[0x20]; 1381 1382 u8 umem_2_buffer_param_a[0x20]; 1383 1384 u8 umem_2_buffer_param_b[0x20]; 1385 1386 u8 umem_3_buffer_param_a[0x20]; 1387 1388 u8 umem_3_buffer_param_b[0x20]; 1389 1390 u8 reserved_at_1c0[0x640]; 1391 }; 1392 1393 struct mlx5_ifc_tlp_dev_emu_capabilities_bits { 1394 u8 reserved_at_0[0x20]; 1395 1396 u8 reserved_at_20[0x13]; 1397 u8 log_tlp_rsp_gw_page_stride[0x5]; 1398 u8 reserved_at_38[0x8]; 1399 1400 u8 reserved_at_40[0xc0]; 1401 1402 u8 reserved_at_100[0xc]; 1403 u8 tlp_rsp_gw_num_pages[0x4]; 1404 u8 reserved_at_110[0x10]; 1405 1406 u8 reserved_at_120[0xa0]; 1407 1408 u8 tlp_rsp_gw_pages_bar_offset[0x40]; 1409 1410 u8 reserved_at_200[0x600]; 1411 }; 1412 1413 enum { 1414 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0, 1415 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2, 1416 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4, 1417 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8, 1418 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10, 1419 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20, 1420 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40, 1421 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80, 1422 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100, 1423 }; 1424 1425 enum { 1426 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1, 1427 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2, 1428 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4, 1429 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8, 1430 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10, 1431 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20, 1432 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40, 1433 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80, 1434 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100, 1435 }; 1436 1437 struct mlx5_ifc_atomic_caps_bits { 1438 u8 reserved_at_0[0x40]; 1439 1440 u8 atomic_req_8B_endianness_mode[0x2]; 1441 u8 reserved_at_42[0x4]; 1442 u8 supported_atomic_req_8B_endianness_mode_1[0x1]; 1443 1444 u8 reserved_at_47[0x19]; 1445 1446 u8 reserved_at_60[0x20]; 1447 1448 u8 reserved_at_80[0x10]; 1449 u8 atomic_operations[0x10]; 1450 1451 u8 reserved_at_a0[0x10]; 1452 u8 atomic_size_qp[0x10]; 1453 1454 u8 reserved_at_c0[0x10]; 1455 u8 atomic_size_dc[0x10]; 1456 1457 u8 reserved_at_e0[0x720]; 1458 }; 1459 1460 struct mlx5_ifc_odp_scheme_cap_bits { 1461 u8 reserved_at_0[0x40]; 1462 1463 u8 sig[0x1]; 1464 u8 reserved_at_41[0x4]; 1465 u8 page_prefetch[0x1]; 1466 u8 reserved_at_46[0x1a]; 1467 1468 u8 reserved_at_60[0x20]; 1469 1470 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps; 1471 1472 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps; 1473 1474 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps; 1475 1476 struct mlx5_ifc_odp_per_transport_service_cap_bits xrc_odp_caps; 1477 1478 struct mlx5_ifc_odp_per_transport_service_cap_bits dc_odp_caps; 1479 1480 u8 reserved_at_120[0xe0]; 1481 }; 1482 1483 struct mlx5_ifc_odp_cap_bits { 1484 struct mlx5_ifc_odp_scheme_cap_bits transport_page_fault_scheme_cap; 1485 1486 struct mlx5_ifc_odp_scheme_cap_bits memory_page_fault_scheme_cap; 1487 1488 u8 reserved_at_400[0x200]; 1489 1490 u8 mem_page_fault[0x1]; 1491 u8 reserved_at_601[0x1f]; 1492 1493 u8 reserved_at_620[0x1e0]; 1494 }; 1495 1496 struct mlx5_ifc_tls_cap_bits { 1497 u8 tls_1_2_aes_gcm_128[0x1]; 1498 u8 tls_1_3_aes_gcm_128[0x1]; 1499 u8 tls_1_2_aes_gcm_256[0x1]; 1500 u8 tls_1_3_aes_gcm_256[0x1]; 1501 u8 reserved_at_4[0x1c]; 1502 1503 u8 reserved_at_20[0x7e0]; 1504 }; 1505 1506 struct mlx5_ifc_ipsec_cap_bits { 1507 u8 ipsec_full_offload[0x1]; 1508 u8 ipsec_crypto_offload[0x1]; 1509 u8 ipsec_esn[0x1]; 1510 u8 ipsec_crypto_esp_aes_gcm_256_encrypt[0x1]; 1511 u8 ipsec_crypto_esp_aes_gcm_128_encrypt[0x1]; 1512 u8 ipsec_crypto_esp_aes_gcm_256_decrypt[0x1]; 1513 u8 ipsec_crypto_esp_aes_gcm_128_decrypt[0x1]; 1514 u8 reserved_at_7[0x4]; 1515 u8 log_max_ipsec_offload[0x5]; 1516 u8 reserved_at_10[0x10]; 1517 1518 u8 min_log_ipsec_full_replay_window[0x8]; 1519 u8 max_log_ipsec_full_replay_window[0x8]; 1520 u8 reserved_at_30[0x7d0]; 1521 }; 1522 1523 struct mlx5_ifc_macsec_cap_bits { 1524 u8 macsec_epn[0x1]; 1525 u8 reserved_at_1[0x2]; 1526 u8 macsec_crypto_esp_aes_gcm_256_encrypt[0x1]; 1527 u8 macsec_crypto_esp_aes_gcm_128_encrypt[0x1]; 1528 u8 macsec_crypto_esp_aes_gcm_256_decrypt[0x1]; 1529 u8 macsec_crypto_esp_aes_gcm_128_decrypt[0x1]; 1530 u8 reserved_at_7[0x4]; 1531 u8 log_max_macsec_offload[0x5]; 1532 u8 reserved_at_10[0x10]; 1533 1534 u8 min_log_macsec_full_replay_window[0x8]; 1535 u8 max_log_macsec_full_replay_window[0x8]; 1536 u8 reserved_at_30[0x10]; 1537 1538 u8 reserved_at_40[0x7c0]; 1539 }; 1540 1541 struct mlx5_ifc_psp_cap_bits { 1542 u8 reserved_at_0[0x1]; 1543 u8 psp_crypto_offload[0x1]; 1544 u8 reserved_at_2[0x1]; 1545 u8 psp_crypto_esp_aes_gcm_256_encrypt[0x1]; 1546 u8 psp_crypto_esp_aes_gcm_128_encrypt[0x1]; 1547 u8 psp_crypto_esp_aes_gcm_256_decrypt[0x1]; 1548 u8 psp_crypto_esp_aes_gcm_128_decrypt[0x1]; 1549 u8 reserved_at_7[0x4]; 1550 u8 log_max_num_of_psp_spi[0x5]; 1551 u8 reserved_at_10[0x10]; 1552 1553 u8 reserved_at_20[0x7e0]; 1554 }; 1555 1556 enum { 1557 MLX5_WQ_TYPE_LINKED_LIST = 0x0, 1558 MLX5_WQ_TYPE_CYCLIC = 0x1, 1559 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2, 1560 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3, 1561 }; 1562 1563 enum { 1564 MLX5_WQ_END_PAD_MODE_NONE = 0x0, 1565 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1, 1566 }; 1567 1568 enum { 1569 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0, 1570 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1, 1571 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2, 1572 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3, 1573 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4, 1574 }; 1575 1576 enum { 1577 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0, 1578 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1, 1579 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2, 1580 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3, 1581 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4, 1582 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5, 1583 }; 1584 1585 enum { 1586 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0, 1587 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1, 1588 }; 1589 1590 enum { 1591 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0, 1592 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1, 1593 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3, 1594 }; 1595 1596 enum { 1597 MLX5_CAP_PORT_TYPE_IB = 0x0, 1598 MLX5_CAP_PORT_TYPE_ETH = 0x1, 1599 }; 1600 1601 enum { 1602 MLX5_CAP_UMR_FENCE_STRONG = 0x0, 1603 MLX5_CAP_UMR_FENCE_SMALL = 0x1, 1604 MLX5_CAP_UMR_FENCE_NONE = 0x2, 1605 }; 1606 1607 enum { 1608 MLX5_FLEX_IPV4_OVER_VXLAN_ENABLED = 1 << 0, 1609 MLX5_FLEX_IPV6_OVER_VXLAN_ENABLED = 1 << 1, 1610 MLX5_FLEX_IPV6_OVER_IP_ENABLED = 1 << 2, 1611 MLX5_FLEX_PARSER_GENEVE_ENABLED = 1 << 3, 1612 MLX5_FLEX_PARSER_MPLS_OVER_GRE_ENABLED = 1 << 4, 1613 MLX5_FLEX_PARSER_MPLS_OVER_UDP_ENABLED = 1 << 5, 1614 MLX5_FLEX_P_BIT_VXLAN_GPE_ENABLED = 1 << 6, 1615 MLX5_FLEX_PARSER_VXLAN_GPE_ENABLED = 1 << 7, 1616 MLX5_FLEX_PARSER_ICMP_V4_ENABLED = 1 << 8, 1617 MLX5_FLEX_PARSER_ICMP_V6_ENABLED = 1 << 9, 1618 MLX5_FLEX_PARSER_GENEVE_TLV_OPTION_0_ENABLED = 1 << 10, 1619 MLX5_FLEX_PARSER_GTPU_ENABLED = 1 << 11, 1620 MLX5_FLEX_PARSER_GTPU_DW_2_ENABLED = 1 << 16, 1621 MLX5_FLEX_PARSER_GTPU_FIRST_EXT_DW_0_ENABLED = 1 << 17, 1622 MLX5_FLEX_PARSER_GTPU_DW_0_ENABLED = 1 << 18, 1623 MLX5_FLEX_PARSER_GTPU_TEID_ENABLED = 1 << 19, 1624 }; 1625 1626 enum { 1627 MLX5_UCTX_CAP_RAW_TX = 1UL << 0, 1628 MLX5_UCTX_CAP_INTERNAL_DEV_RES = 1UL << 1, 1629 MLX5_UCTX_CAP_RDMA_CTRL = 1UL << 3, 1630 MLX5_UCTX_CAP_RDMA_CTRL_OTHER_VHCA = 1UL << 4, 1631 }; 1632 1633 #define MLX5_FC_BULK_SIZE_FACTOR 128 1634 1635 enum mlx5_fc_bulk_alloc_bitmask { 1636 MLX5_FC_BULK_128 = (1 << 0), 1637 MLX5_FC_BULK_256 = (1 << 1), 1638 MLX5_FC_BULK_512 = (1 << 2), 1639 MLX5_FC_BULK_1024 = (1 << 3), 1640 MLX5_FC_BULK_2048 = (1 << 4), 1641 MLX5_FC_BULK_4096 = (1 << 5), 1642 MLX5_FC_BULK_8192 = (1 << 6), 1643 MLX5_FC_BULK_16384 = (1 << 7), 1644 }; 1645 1646 #define MLX5_FC_BULK_NUM_FCS(fc_enum) (MLX5_FC_BULK_SIZE_FACTOR * (fc_enum)) 1647 1648 #define MLX5_FT_MAX_MULTIPATH_LEVEL 63 1649 1650 enum { 1651 MLX5_STEERING_FORMAT_CONNECTX_5 = 0, 1652 MLX5_STEERING_FORMAT_CONNECTX_6DX = 1, 1653 MLX5_STEERING_FORMAT_CONNECTX_7 = 2, 1654 MLX5_STEERING_FORMAT_CONNECTX_8 = 3, 1655 }; 1656 1657 struct mlx5_ifc_cmd_hca_cap_bits { 1658 u8 reserved_at_0[0x6]; 1659 u8 page_request_disable[0x1]; 1660 u8 abs_native_port_num[0x1]; 1661 u8 reserved_at_8[0x8]; 1662 u8 shared_object_to_user_object_allowed[0x1]; 1663 u8 reserved_at_13[0xe]; 1664 u8 vhca_resource_manager[0x1]; 1665 1666 u8 hca_cap_2[0x1]; 1667 u8 create_lag_when_not_master_up[0x1]; 1668 u8 dtor[0x1]; 1669 u8 event_on_vhca_state_teardown_request[0x1]; 1670 u8 event_on_vhca_state_in_use[0x1]; 1671 u8 event_on_vhca_state_active[0x1]; 1672 u8 event_on_vhca_state_allocated[0x1]; 1673 u8 event_on_vhca_state_invalid[0x1]; 1674 u8 reserved_at_28[0x8]; 1675 u8 vhca_id[0x10]; 1676 1677 u8 reserved_at_40[0x40]; 1678 1679 u8 log_max_srq_sz[0x8]; 1680 u8 log_max_qp_sz[0x8]; 1681 u8 event_cap[0x1]; 1682 u8 reserved_at_91[0x2]; 1683 u8 isolate_vl_tc_new[0x1]; 1684 u8 reserved_at_94[0x4]; 1685 u8 prio_tag_required[0x1]; 1686 u8 reserved_at_99[0x2]; 1687 u8 log_max_qp[0x5]; 1688 1689 u8 reserved_at_a0[0x3]; 1690 u8 ece_support[0x1]; 1691 u8 reserved_at_a4[0x5]; 1692 u8 reg_c_preserve[0x1]; 1693 u8 reserved_at_aa[0x1]; 1694 u8 log_max_srq[0x5]; 1695 u8 reserved_at_b0[0x1]; 1696 u8 uplink_follow[0x1]; 1697 u8 ts_cqe_to_dest_cqn[0x1]; 1698 u8 reserved_at_b3[0x6]; 1699 u8 go_back_n[0x1]; 1700 u8 reserved_at_ba[0x6]; 1701 1702 u8 max_sgl_for_optimized_performance[0x8]; 1703 u8 log_max_cq_sz[0x8]; 1704 u8 relaxed_ordering_write_umr[0x1]; 1705 u8 relaxed_ordering_read_umr[0x1]; 1706 u8 reserved_at_d2[0x7]; 1707 u8 virtio_net_device_emualtion_manager[0x1]; 1708 u8 virtio_blk_device_emualtion_manager[0x1]; 1709 u8 log_max_cq[0x5]; 1710 1711 u8 log_max_eq_sz[0x8]; 1712 u8 relaxed_ordering_write[0x1]; 1713 u8 relaxed_ordering_read_pci_enabled[0x1]; 1714 u8 log_max_mkey[0x6]; 1715 u8 reserved_at_f0[0x6]; 1716 u8 terminate_scatter_list_mkey[0x1]; 1717 u8 repeated_mkey[0x1]; 1718 u8 dump_fill_mkey[0x1]; 1719 u8 reserved_at_f9[0x2]; 1720 u8 fast_teardown[0x1]; 1721 u8 log_max_eq[0x4]; 1722 1723 u8 max_indirection[0x8]; 1724 u8 fixed_buffer_size[0x1]; 1725 u8 log_max_mrw_sz[0x7]; 1726 u8 force_teardown[0x1]; 1727 u8 reserved_at_111[0x1]; 1728 u8 log_max_bsf_list_size[0x6]; 1729 u8 umr_extended_translation_offset[0x1]; 1730 u8 null_mkey[0x1]; 1731 u8 log_max_klm_list_size[0x6]; 1732 1733 u8 reserved_at_120[0x2]; 1734 u8 qpc_extension[0x1]; 1735 u8 reserved_at_123[0x7]; 1736 u8 log_max_ra_req_dc[0x6]; 1737 u8 reserved_at_130[0x2]; 1738 u8 eth_wqe_too_small[0x1]; 1739 u8 reserved_at_133[0x6]; 1740 u8 vnic_env_cq_overrun[0x1]; 1741 u8 log_max_ra_res_dc[0x6]; 1742 1743 u8 reserved_at_140[0x5]; 1744 u8 release_all_pages[0x1]; 1745 u8 must_not_use[0x1]; 1746 u8 reserved_at_147[0x2]; 1747 u8 roce_accl[0x1]; 1748 u8 log_max_ra_req_qp[0x6]; 1749 u8 reserved_at_150[0xa]; 1750 u8 log_max_ra_res_qp[0x6]; 1751 1752 u8 end_pad[0x1]; 1753 u8 cc_query_allowed[0x1]; 1754 u8 cc_modify_allowed[0x1]; 1755 u8 start_pad[0x1]; 1756 u8 cache_line_128byte[0x1]; 1757 u8 reserved_at_165[0x4]; 1758 u8 rts2rts_qp_counters_set_id[0x1]; 1759 u8 reserved_at_16a[0x2]; 1760 u8 vnic_env_int_rq_oob[0x1]; 1761 u8 sbcam_reg[0x1]; 1762 u8 reserved_at_16e[0x1]; 1763 u8 qcam_reg[0x1]; 1764 u8 gid_table_size[0x10]; 1765 1766 u8 out_of_seq_cnt[0x1]; 1767 u8 vport_counters[0x1]; 1768 u8 retransmission_q_counters[0x1]; 1769 u8 debug[0x1]; 1770 u8 modify_rq_counter_set_id[0x1]; 1771 u8 rq_delay_drop[0x1]; 1772 u8 max_qp_cnt[0xa]; 1773 u8 pkey_table_size[0x10]; 1774 1775 u8 vport_group_manager[0x1]; 1776 u8 vhca_group_manager[0x1]; 1777 u8 ib_virt[0x1]; 1778 u8 eth_virt[0x1]; 1779 u8 vnic_env_queue_counters[0x1]; 1780 u8 ets[0x1]; 1781 u8 nic_flow_table[0x1]; 1782 u8 eswitch_manager[0x1]; 1783 u8 device_memory[0x1]; 1784 u8 mcam_reg[0x1]; 1785 u8 pcam_reg[0x1]; 1786 u8 local_ca_ack_delay[0x5]; 1787 u8 port_module_event[0x1]; 1788 u8 enhanced_error_q_counters[0x1]; 1789 u8 ports_check[0x1]; 1790 u8 reserved_at_1b3[0x1]; 1791 u8 disable_link_up[0x1]; 1792 u8 beacon_led[0x1]; 1793 u8 port_type[0x2]; 1794 u8 num_ports[0x8]; 1795 1796 u8 reserved_at_1c0[0x1]; 1797 u8 pps[0x1]; 1798 u8 pps_modify[0x1]; 1799 u8 log_max_msg[0x5]; 1800 u8 reserved_at_1c8[0x4]; 1801 u8 max_tc[0x4]; 1802 u8 temp_warn_event[0x1]; 1803 u8 dcbx[0x1]; 1804 u8 general_notification_event[0x1]; 1805 u8 reserved_at_1d3[0x2]; 1806 u8 fpga[0x1]; 1807 u8 rol_s[0x1]; 1808 u8 rol_g[0x1]; 1809 u8 reserved_at_1d8[0x1]; 1810 u8 wol_s[0x1]; 1811 u8 wol_g[0x1]; 1812 u8 wol_a[0x1]; 1813 u8 wol_b[0x1]; 1814 u8 wol_m[0x1]; 1815 u8 wol_u[0x1]; 1816 u8 wol_p[0x1]; 1817 1818 u8 stat_rate_support[0x10]; 1819 u8 reserved_at_1f0[0x1]; 1820 u8 pci_sync_for_fw_update_event[0x1]; 1821 u8 reserved_at_1f2[0x6]; 1822 u8 init2_lag_tx_port_affinity[0x1]; 1823 u8 reserved_at_1fa[0x2]; 1824 u8 wqe_based_flow_table_update_cap[0x1]; 1825 u8 cqe_version[0x4]; 1826 1827 u8 compact_address_vector[0x1]; 1828 u8 striding_rq[0x1]; 1829 u8 reserved_at_202[0x1]; 1830 u8 ipoib_enhanced_offloads[0x1]; 1831 u8 ipoib_basic_offloads[0x1]; 1832 u8 reserved_at_205[0x1]; 1833 u8 repeated_block_disabled[0x1]; 1834 u8 umr_modify_entity_size_disabled[0x1]; 1835 u8 umr_modify_atomic_disabled[0x1]; 1836 u8 umr_indirect_mkey_disabled[0x1]; 1837 u8 umr_fence[0x2]; 1838 u8 dc_req_scat_data_cqe[0x1]; 1839 u8 reserved_at_20d[0x2]; 1840 u8 drain_sigerr[0x1]; 1841 u8 cmdif_checksum[0x2]; 1842 u8 sigerr_cqe[0x1]; 1843 u8 reserved_at_213[0x1]; 1844 u8 wq_signature[0x1]; 1845 u8 sctr_data_cqe[0x1]; 1846 u8 reserved_at_216[0x1]; 1847 u8 sho[0x1]; 1848 u8 tph[0x1]; 1849 u8 rf[0x1]; 1850 u8 dct[0x1]; 1851 u8 qos[0x1]; 1852 u8 eth_net_offloads[0x1]; 1853 u8 roce[0x1]; 1854 u8 atomic[0x1]; 1855 u8 reserved_at_21f[0x1]; 1856 1857 u8 cq_oi[0x1]; 1858 u8 cq_resize[0x1]; 1859 u8 cq_moderation[0x1]; 1860 u8 cq_period_mode_modify[0x1]; 1861 u8 reserved_at_224[0x2]; 1862 u8 cq_eq_remap[0x1]; 1863 u8 pg[0x1]; 1864 u8 block_lb_mc[0x1]; 1865 u8 reserved_at_229[0x1]; 1866 u8 scqe_break_moderation[0x1]; 1867 u8 cq_period_start_from_cqe[0x1]; 1868 u8 cd[0x1]; 1869 u8 reserved_at_22d[0x1]; 1870 u8 apm[0x1]; 1871 u8 vector_calc[0x1]; 1872 u8 umr_ptr_rlky[0x1]; 1873 u8 imaicl[0x1]; 1874 u8 qp_packet_based[0x1]; 1875 u8 reserved_at_233[0x3]; 1876 u8 qkv[0x1]; 1877 u8 pkv[0x1]; 1878 u8 set_deth_sqpn[0x1]; 1879 u8 reserved_at_239[0x3]; 1880 u8 xrc[0x1]; 1881 u8 ud[0x1]; 1882 u8 uc[0x1]; 1883 u8 rc[0x1]; 1884 1885 u8 uar_4k[0x1]; 1886 u8 reserved_at_241[0x7]; 1887 u8 fl_rc_qp_when_roce_disabled[0x1]; 1888 u8 regexp_params[0x1]; 1889 u8 uar_sz[0x6]; 1890 u8 port_selection_cap[0x1]; 1891 u8 nic_cap_reg[0x1]; 1892 u8 umem_uid_0[0x1]; 1893 u8 reserved_at_253[0x5]; 1894 u8 log_pg_sz[0x8]; 1895 1896 u8 bf[0x1]; 1897 u8 driver_version[0x1]; 1898 u8 pad_tx_eth_packet[0x1]; 1899 u8 reserved_at_263[0x3]; 1900 u8 mkey_by_name[0x1]; 1901 u8 reserved_at_267[0x4]; 1902 1903 u8 log_bf_reg_size[0x5]; 1904 1905 u8 disciplined_fr_counter[0x1]; 1906 u8 reserved_at_271[0x2]; 1907 u8 qp_error_syndrome[0x1]; 1908 u8 reserved_at_274[0x2]; 1909 u8 lag_dct[0x2]; 1910 u8 lag_tx_port_affinity[0x1]; 1911 u8 lag_native_fdb_selection[0x1]; 1912 u8 reserved_at_27a[0x1]; 1913 u8 lag_master[0x1]; 1914 u8 num_lag_ports[0x4]; 1915 1916 u8 reserved_at_280[0x10]; 1917 u8 max_wqe_sz_sq[0x10]; 1918 1919 u8 reserved_at_2a0[0x7]; 1920 u8 mkey_pcie_tph[0x1]; 1921 u8 reserved_at_2a8[0x1]; 1922 u8 tis_tir_td_order[0x1]; 1923 1924 u8 psp[0x1]; 1925 u8 shampo[0x1]; 1926 u8 reserved_at_2ac[0x4]; 1927 u8 max_wqe_sz_rq[0x10]; 1928 1929 u8 max_flow_counter_31_16[0x10]; 1930 u8 max_wqe_sz_sq_dc[0x10]; 1931 1932 u8 reserved_at_2e0[0x7]; 1933 u8 max_qp_mcg[0x19]; 1934 1935 u8 reserved_at_300[0x10]; 1936 u8 flow_counter_bulk_alloc[0x8]; 1937 u8 log_max_mcg[0x8]; 1938 1939 u8 reserved_at_320[0x3]; 1940 u8 log_max_transport_domain[0x5]; 1941 u8 reserved_at_328[0x2]; 1942 u8 relaxed_ordering_read[0x1]; 1943 u8 log_max_pd[0x5]; 1944 u8 dp_ordering_ooo_all_ud[0x1]; 1945 u8 dp_ordering_ooo_all_uc[0x1]; 1946 u8 dp_ordering_ooo_all_xrc[0x1]; 1947 u8 dp_ordering_ooo_all_dc[0x1]; 1948 u8 dp_ordering_ooo_all_rc[0x1]; 1949 u8 pcie_reset_using_hotreset_method[0x1]; 1950 u8 pci_sync_for_fw_update_with_driver_unload[0x1]; 1951 u8 vnic_env_cnt_steering_fail[0x1]; 1952 u8 vport_counter_local_loopback[0x1]; 1953 u8 q_counter_aggregation[0x1]; 1954 u8 q_counter_other_vport[0x1]; 1955 u8 log_max_xrcd[0x5]; 1956 1957 u8 nic_receive_steering_discard[0x1]; 1958 u8 receive_discard_vport_down[0x1]; 1959 u8 transmit_discard_vport_down[0x1]; 1960 u8 eq_overrun_count[0x1]; 1961 u8 reserved_at_344[0x1]; 1962 u8 invalid_command_count[0x1]; 1963 u8 quota_exceeded_count[0x1]; 1964 u8 reserved_at_347[0x1]; 1965 u8 log_max_flow_counter_bulk[0x8]; 1966 u8 max_flow_counter_15_0[0x10]; 1967 1968 1969 u8 reserved_at_360[0x3]; 1970 u8 log_max_rq[0x5]; 1971 u8 reserved_at_368[0x3]; 1972 u8 log_max_sq[0x5]; 1973 u8 reserved_at_370[0x3]; 1974 u8 log_max_tir[0x5]; 1975 u8 reserved_at_378[0x3]; 1976 u8 log_max_tis[0x5]; 1977 1978 u8 basic_cyclic_rcv_wqe[0x1]; 1979 u8 reserved_at_381[0x2]; 1980 u8 log_max_rmp[0x5]; 1981 u8 reserved_at_388[0x3]; 1982 u8 log_max_rqt[0x5]; 1983 u8 reserved_at_390[0x3]; 1984 u8 log_max_rqt_size[0x5]; 1985 u8 tlp_device_emulation_manager[0x1]; 1986 u8 vnic_env_cnt_bar_uar_access[0x1]; 1987 u8 vnic_env_cnt_odp_page_fault[0x1]; 1988 u8 log_max_tis_per_sq[0x5]; 1989 1990 u8 ext_stride_num_range[0x1]; 1991 u8 roce_rw_supported[0x1]; 1992 u8 log_max_current_uc_list_wr_supported[0x1]; 1993 u8 log_max_stride_sz_rq[0x5]; 1994 u8 reserved_at_3a8[0x3]; 1995 u8 log_min_stride_sz_rq[0x5]; 1996 u8 reserved_at_3b0[0x3]; 1997 u8 log_max_stride_sz_sq[0x5]; 1998 u8 reserved_at_3b8[0x3]; 1999 u8 log_min_stride_sz_sq[0x5]; 2000 2001 u8 hairpin[0x1]; 2002 u8 reserved_at_3c1[0x2]; 2003 u8 log_max_hairpin_queues[0x5]; 2004 u8 reserved_at_3c8[0x3]; 2005 u8 log_max_hairpin_wq_data_sz[0x5]; 2006 u8 reserved_at_3d0[0x3]; 2007 u8 log_max_hairpin_num_packets[0x5]; 2008 u8 reserved_at_3d8[0x3]; 2009 u8 log_max_wq_sz[0x5]; 2010 2011 u8 nic_vport_change_event[0x1]; 2012 u8 disable_local_lb_uc[0x1]; 2013 u8 disable_local_lb_mc[0x1]; 2014 u8 log_min_hairpin_wq_data_sz[0x5]; 2015 u8 reserved_at_3e8[0x1]; 2016 u8 silent_mode_set[0x1]; 2017 u8 vhca_state[0x1]; 2018 u8 log_max_vlan_list[0x5]; 2019 u8 reserved_at_3f0[0x3]; 2020 u8 log_max_current_mc_list[0x5]; 2021 u8 reserved_at_3f8[0x1]; 2022 u8 silent_mode_query[0x1]; 2023 u8 reserved_at_3fa[0x1]; 2024 u8 log_max_current_uc_list[0x5]; 2025 2026 u8 general_obj_types[0x40]; 2027 2028 u8 sq_ts_format[0x2]; 2029 u8 rq_ts_format[0x2]; 2030 u8 steering_format_version[0x4]; 2031 u8 create_qp_start_hint[0x18]; 2032 2033 u8 reserved_at_460[0x1]; 2034 u8 ats[0x1]; 2035 u8 cross_vhca_rqt[0x1]; 2036 u8 log_max_uctx[0x5]; 2037 u8 reserved_at_468[0x1]; 2038 u8 crypto[0x1]; 2039 u8 ipsec_offload[0x1]; 2040 u8 log_max_umem[0x5]; 2041 u8 max_num_eqs[0x10]; 2042 2043 u8 reserved_at_480[0x1]; 2044 u8 tls_tx[0x1]; 2045 u8 tls_rx[0x1]; 2046 u8 log_max_l2_table[0x5]; 2047 u8 reserved_at_488[0x8]; 2048 u8 log_uar_page_sz[0x10]; 2049 2050 u8 reserved_at_4a0[0x20]; 2051 u8 device_frequency_mhz[0x20]; 2052 u8 device_frequency_khz[0x20]; 2053 2054 u8 reserved_at_500[0x20]; 2055 u8 num_of_uars_per_page[0x20]; 2056 2057 u8 flex_parser_protocols[0x20]; 2058 2059 u8 max_geneve_tlv_options[0x8]; 2060 u8 reserved_at_568[0x3]; 2061 u8 max_geneve_tlv_option_data_len[0x5]; 2062 u8 reserved_at_570[0x1]; 2063 u8 adv_rdma[0x1]; 2064 u8 reserved_at_572[0x7]; 2065 u8 adv_virtualization[0x1]; 2066 u8 reserved_at_57a[0x6]; 2067 2068 u8 reserved_at_580[0xb]; 2069 u8 log_max_dci_stream_channels[0x5]; 2070 u8 reserved_at_590[0x3]; 2071 u8 log_max_dci_errored_streams[0x5]; 2072 u8 reserved_at_598[0x8]; 2073 2074 u8 reserved_at_5a0[0x10]; 2075 u8 enhanced_cqe_compression[0x1]; 2076 u8 reserved_at_5b1[0x1]; 2077 u8 crossing_vhca_mkey[0x1]; 2078 u8 log_max_dek[0x5]; 2079 u8 reserved_at_5b8[0x4]; 2080 u8 mini_cqe_resp_stride_index[0x1]; 2081 u8 cqe_128_always[0x1]; 2082 u8 cqe_compression_128[0x1]; 2083 u8 cqe_compression[0x1]; 2084 2085 u8 cqe_compression_timeout[0x10]; 2086 u8 cqe_compression_max_num[0x10]; 2087 2088 u8 reserved_at_5e0[0x8]; 2089 u8 flex_parser_id_gtpu_dw_0[0x4]; 2090 u8 reserved_at_5ec[0x4]; 2091 u8 tag_matching[0x1]; 2092 u8 rndv_offload_rc[0x1]; 2093 u8 rndv_offload_dc[0x1]; 2094 u8 log_tag_matching_list_sz[0x5]; 2095 u8 reserved_at_5f8[0x3]; 2096 u8 log_max_xrq[0x5]; 2097 2098 u8 affiliate_nic_vport_criteria[0x8]; 2099 u8 native_port_num[0x8]; 2100 u8 num_vhca_ports[0x8]; 2101 u8 flex_parser_id_gtpu_teid[0x4]; 2102 u8 reserved_at_61c[0x2]; 2103 u8 sw_owner_id[0x1]; 2104 u8 reserved_at_61f[0x1]; 2105 2106 u8 max_num_of_monitor_counters[0x10]; 2107 u8 num_ppcnt_monitor_counters[0x10]; 2108 2109 u8 max_num_sf[0x10]; 2110 u8 num_q_monitor_counters[0x10]; 2111 2112 u8 reserved_at_660[0x20]; 2113 2114 u8 sf[0x1]; 2115 u8 sf_set_partition[0x1]; 2116 u8 reserved_at_682[0x1]; 2117 u8 log_max_sf[0x5]; 2118 u8 apu[0x1]; 2119 u8 reserved_at_689[0x4]; 2120 u8 migration[0x1]; 2121 u8 reserved_at_68e[0x2]; 2122 u8 log_min_sf_size[0x8]; 2123 u8 max_num_sf_partitions[0x8]; 2124 2125 u8 uctx_cap[0x20]; 2126 2127 u8 reserved_at_6c0[0x4]; 2128 u8 flex_parser_id_geneve_tlv_option_0[0x4]; 2129 u8 flex_parser_id_icmp_dw1[0x4]; 2130 u8 flex_parser_id_icmp_dw0[0x4]; 2131 u8 flex_parser_id_icmpv6_dw1[0x4]; 2132 u8 flex_parser_id_icmpv6_dw0[0x4]; 2133 u8 flex_parser_id_outer_first_mpls_over_gre[0x4]; 2134 u8 flex_parser_id_outer_first_mpls_over_udp_label[0x4]; 2135 2136 u8 max_num_match_definer[0x10]; 2137 u8 sf_base_id[0x10]; 2138 2139 u8 flex_parser_id_gtpu_dw_2[0x4]; 2140 u8 flex_parser_id_gtpu_first_ext_dw_0[0x4]; 2141 u8 num_total_dynamic_vf_msix[0x18]; 2142 u8 reserved_at_720[0x14]; 2143 u8 dynamic_msix_table_size[0xc]; 2144 u8 reserved_at_740[0xc]; 2145 u8 min_dynamic_vf_msix_table_size[0x4]; 2146 u8 reserved_at_750[0x2]; 2147 u8 data_direct[0x1]; 2148 u8 reserved_at_753[0x1]; 2149 u8 max_dynamic_vf_msix_table_size[0xc]; 2150 2151 u8 reserved_at_760[0x3]; 2152 u8 log_max_num_header_modify_argument[0x5]; 2153 u8 log_header_modify_argument_granularity_offset[0x4]; 2154 u8 log_header_modify_argument_granularity[0x4]; 2155 u8 reserved_at_770[0x3]; 2156 u8 log_header_modify_argument_max_alloc[0x5]; 2157 u8 reserved_at_778[0x8]; 2158 2159 u8 vhca_tunnel_commands[0x40]; 2160 u8 match_definer_format_supported[0x40]; 2161 }; 2162 2163 enum { 2164 MLX5_CROSS_VHCA_OBJ_TO_OBJ_SUPPORTED_LOCAL_FLOW_TABLE_TO_REMOTE_FLOW_TABLE_MISS = 0x80000, 2165 MLX5_CROSS_VHCA_OBJ_TO_OBJ_SUPPORTED_LOCAL_FLOW_TABLE_ROOT_TO_REMOTE_FLOW_TABLE = (1ULL << 20), 2166 }; 2167 2168 enum { 2169 MLX5_ALLOWED_OBJ_FOR_OTHER_VHCA_ACCESS_FLOW_TABLE = 0x200, 2170 }; 2171 2172 struct mlx5_ifc_cmd_hca_cap_2_bits { 2173 u8 reserved_at_0[0x80]; 2174 2175 u8 migratable[0x1]; 2176 u8 reserved_at_81[0x7]; 2177 u8 dp_ordering_force[0x1]; 2178 u8 reserved_at_89[0x9]; 2179 u8 query_vuid[0x1]; 2180 u8 reserved_at_93[0x5]; 2181 u8 umr_log_entity_size_5[0x1]; 2182 u8 reserved_at_99[0x7]; 2183 2184 u8 max_reformat_insert_size[0x8]; 2185 u8 max_reformat_insert_offset[0x8]; 2186 u8 max_reformat_remove_size[0x8]; 2187 u8 max_reformat_remove_offset[0x8]; 2188 2189 u8 reserved_at_c0[0x8]; 2190 u8 migration_multi_load[0x1]; 2191 u8 migration_tracking_state[0x1]; 2192 u8 multiplane_qp_ud[0x1]; 2193 u8 reserved_at_cb[0x5]; 2194 u8 migration_in_chunks[0x1]; 2195 u8 reserved_at_d1[0x1]; 2196 u8 sf_eq_usage[0x1]; 2197 u8 reserved_at_d3[0x5]; 2198 u8 multiplane[0x1]; 2199 u8 reserved_at_d9[0x7]; 2200 2201 u8 cross_vhca_object_to_object_supported[0x20]; 2202 2203 u8 allowed_object_for_other_vhca_access[0x40]; 2204 2205 u8 reserved_at_140[0x60]; 2206 2207 u8 flow_table_type_2_type[0x8]; 2208 u8 reserved_at_1a8[0x2]; 2209 u8 format_select_dw_8_6_ext[0x1]; 2210 u8 log_min_mkey_entity_size[0x5]; 2211 u8 reserved_at_1b0[0x10]; 2212 2213 u8 general_obj_types_127_64[0x40]; 2214 u8 reserved_at_200[0x20]; 2215 2216 u8 reserved_at_220[0x1]; 2217 u8 sw_vhca_id_valid[0x1]; 2218 u8 sw_vhca_id[0xe]; 2219 u8 reserved_at_230[0x10]; 2220 2221 u8 reserved_at_240[0xb]; 2222 u8 ts_cqe_metadata_size2wqe_counter[0x5]; 2223 u8 reserved_at_250[0x10]; 2224 2225 u8 reserved_at_260[0x20]; 2226 2227 u8 format_select_dw_gtpu_dw_0[0x8]; 2228 u8 format_select_dw_gtpu_dw_1[0x8]; 2229 u8 format_select_dw_gtpu_dw_2[0x8]; 2230 u8 format_select_dw_gtpu_first_ext_dw_0[0x8]; 2231 2232 u8 generate_wqe_type[0x20]; 2233 2234 u8 reserved_at_2c0[0xc0]; 2235 2236 u8 reserved_at_380[0xb]; 2237 u8 min_mkey_log_entity_size_fixed_buffer[0x5]; 2238 u8 ec_vf_vport_base[0x10]; 2239 2240 u8 reserved_at_3a0[0x2]; 2241 u8 max_mkey_log_entity_size_fixed_buffer[0x6]; 2242 u8 reserved_at_3a8[0x2]; 2243 u8 max_mkey_log_entity_size_mtt[0x6]; 2244 u8 max_rqt_vhca_id[0x10]; 2245 2246 u8 reserved_at_3c0[0x20]; 2247 2248 u8 reserved_at_3e0[0x10]; 2249 u8 pcc_ifa2[0x1]; 2250 u8 reserved_at_3f1[0xf]; 2251 2252 u8 reserved_at_400[0x1]; 2253 u8 min_mkey_log_entity_size_fixed_buffer_valid[0x1]; 2254 u8 reserved_at_402[0xe]; 2255 u8 return_reg_id[0x10]; 2256 2257 u8 reserved_at_420[0x1c]; 2258 u8 flow_table_hash_type[0x4]; 2259 2260 u8 reserved_at_440[0x8]; 2261 u8 max_num_eqs_24b[0x18]; 2262 2263 u8 reserved_at_460[0x144]; 2264 u8 load_balance_id[0x4]; 2265 u8 reserved_at_5a8[0x18]; 2266 2267 u8 query_adjacent_functions_id[0x1]; 2268 u8 ingress_egress_esw_vport_connect[0x1]; 2269 u8 function_id_type_vhca_id[0x1]; 2270 u8 reserved_at_5c3[0x1]; 2271 u8 lag_per_mp_group[0x1]; 2272 u8 reserved_at_5c5[0xb]; 2273 u8 delegate_vhca_management_profiles[0x10]; 2274 2275 u8 delegated_vhca_max[0x10]; 2276 u8 delegate_vhca_max[0x10]; 2277 2278 u8 reserved_at_600[0x200]; 2279 }; 2280 2281 enum mlx5_ifc_flow_destination_type { 2282 MLX5_IFC_FLOW_DESTINATION_TYPE_VPORT = 0x0, 2283 MLX5_IFC_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1, 2284 MLX5_IFC_FLOW_DESTINATION_TYPE_TIR = 0x2, 2285 MLX5_IFC_FLOW_DESTINATION_TYPE_VHCA_RX = 0x4, 2286 MLX5_IFC_FLOW_DESTINATION_TYPE_FLOW_SAMPLER = 0x6, 2287 MLX5_IFC_FLOW_DESTINATION_TYPE_UPLINK = 0x8, 2288 MLX5_IFC_FLOW_DESTINATION_TYPE_TABLE_TYPE = 0xA, 2289 }; 2290 2291 enum mlx5_flow_table_miss_action { 2292 MLX5_FLOW_TABLE_MISS_ACTION_DEF, 2293 MLX5_FLOW_TABLE_MISS_ACTION_FWD, 2294 MLX5_FLOW_TABLE_MISS_ACTION_SWITCH_DOMAIN, 2295 }; 2296 2297 struct mlx5_ifc_dest_format_struct_bits { 2298 u8 destination_type[0x8]; 2299 u8 destination_id[0x18]; 2300 2301 u8 destination_eswitch_owner_vhca_id_valid[0x1]; 2302 u8 packet_reformat[0x1]; 2303 u8 reserved_at_22[0x6]; 2304 u8 destination_table_type[0x8]; 2305 u8 destination_eswitch_owner_vhca_id[0x10]; 2306 }; 2307 2308 struct mlx5_ifc_flow_counter_list_bits { 2309 u8 flow_counter_id[0x20]; 2310 2311 u8 reserved_at_20[0x20]; 2312 }; 2313 2314 struct mlx5_ifc_extended_dest_format_bits { 2315 struct mlx5_ifc_dest_format_struct_bits destination_entry; 2316 2317 u8 packet_reformat_id[0x20]; 2318 2319 u8 reserved_at_60[0x20]; 2320 }; 2321 2322 union mlx5_ifc_dest_format_flow_counter_list_auto_bits { 2323 struct mlx5_ifc_extended_dest_format_bits extended_dest_format; 2324 struct mlx5_ifc_flow_counter_list_bits flow_counter_list; 2325 }; 2326 2327 struct mlx5_ifc_fte_match_param_bits { 2328 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers; 2329 2330 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters; 2331 2332 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers; 2333 2334 struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2; 2335 2336 struct mlx5_ifc_fte_match_set_misc3_bits misc_parameters_3; 2337 2338 struct mlx5_ifc_fte_match_set_misc4_bits misc_parameters_4; 2339 2340 struct mlx5_ifc_fte_match_set_misc5_bits misc_parameters_5; 2341 2342 u8 reserved_at_e00[0x200]; 2343 }; 2344 2345 enum { 2346 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0, 2347 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1, 2348 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2, 2349 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3, 2350 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4, 2351 }; 2352 2353 struct mlx5_ifc_rx_hash_field_select_bits { 2354 u8 l3_prot_type[0x1]; 2355 u8 l4_prot_type[0x1]; 2356 u8 selected_fields[0x1e]; 2357 }; 2358 2359 enum { 2360 MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0, 2361 MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1, 2362 }; 2363 2364 enum { 2365 MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0, 2366 MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1, 2367 }; 2368 2369 struct mlx5_ifc_wq_bits { 2370 u8 wq_type[0x4]; 2371 u8 wq_signature[0x1]; 2372 u8 end_padding_mode[0x2]; 2373 u8 cd_slave[0x1]; 2374 u8 reserved_at_8[0x18]; 2375 2376 u8 hds_skip_first_sge[0x1]; 2377 u8 log2_hds_buf_size[0x3]; 2378 u8 reserved_at_24[0x7]; 2379 u8 page_offset[0x5]; 2380 u8 lwm[0x10]; 2381 2382 u8 reserved_at_40[0x8]; 2383 u8 pd[0x18]; 2384 2385 u8 reserved_at_60[0x8]; 2386 u8 uar_page[0x18]; 2387 2388 u8 dbr_addr[0x40]; 2389 2390 u8 hw_counter[0x20]; 2391 2392 u8 sw_counter[0x20]; 2393 2394 u8 reserved_at_100[0xc]; 2395 u8 log_wq_stride[0x4]; 2396 u8 reserved_at_110[0x3]; 2397 u8 log_wq_pg_sz[0x5]; 2398 u8 reserved_at_118[0x3]; 2399 u8 log_wq_sz[0x5]; 2400 2401 u8 dbr_umem_valid[0x1]; 2402 u8 wq_umem_valid[0x1]; 2403 u8 reserved_at_122[0x1]; 2404 u8 log_hairpin_num_packets[0x5]; 2405 u8 reserved_at_128[0x3]; 2406 u8 log_hairpin_data_sz[0x5]; 2407 2408 u8 reserved_at_130[0x4]; 2409 u8 log_wqe_num_of_strides[0x4]; 2410 u8 two_byte_shift_en[0x1]; 2411 u8 reserved_at_139[0x4]; 2412 u8 log_wqe_stride_size[0x3]; 2413 2414 u8 dbr_umem_id[0x20]; 2415 u8 wq_umem_id[0x20]; 2416 2417 u8 wq_umem_offset[0x40]; 2418 2419 u8 headers_mkey[0x20]; 2420 2421 u8 shampo_enable[0x1]; 2422 u8 reserved_at_1e1[0x1]; 2423 u8 shampo_mode[0x2]; 2424 u8 reserved_at_1e4[0x1]; 2425 u8 log_reservation_size[0x3]; 2426 u8 reserved_at_1e8[0x5]; 2427 u8 log_max_num_of_packets_per_reservation[0x3]; 2428 u8 reserved_at_1f0[0x6]; 2429 u8 log_headers_entry_size[0x2]; 2430 u8 reserved_at_1f8[0x4]; 2431 u8 log_headers_buffer_entry_num[0x4]; 2432 2433 u8 reserved_at_200[0x400]; 2434 2435 struct mlx5_ifc_cmd_pas_bits pas[]; 2436 }; 2437 2438 struct mlx5_ifc_rq_num_bits { 2439 u8 reserved_at_0[0x8]; 2440 u8 rq_num[0x18]; 2441 }; 2442 2443 struct mlx5_ifc_rq_vhca_bits { 2444 u8 reserved_at_0[0x8]; 2445 u8 rq_num[0x18]; 2446 u8 reserved_at_20[0x10]; 2447 u8 rq_vhca_id[0x10]; 2448 }; 2449 2450 struct mlx5_ifc_mac_address_layout_bits { 2451 u8 reserved_at_0[0x10]; 2452 u8 mac_addr_47_32[0x10]; 2453 2454 u8 mac_addr_31_0[0x20]; 2455 }; 2456 2457 struct mlx5_ifc_vlan_layout_bits { 2458 u8 reserved_at_0[0x14]; 2459 u8 vlan[0x0c]; 2460 2461 u8 reserved_at_20[0x20]; 2462 }; 2463 2464 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits { 2465 u8 reserved_at_0[0xa0]; 2466 2467 u8 min_time_between_cnps[0x20]; 2468 2469 u8 reserved_at_c0[0x12]; 2470 u8 cnp_dscp[0x6]; 2471 u8 reserved_at_d8[0x4]; 2472 u8 cnp_prio_mode[0x1]; 2473 u8 cnp_802p_prio[0x3]; 2474 2475 u8 reserved_at_e0[0x720]; 2476 }; 2477 2478 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits { 2479 u8 reserved_at_0[0x60]; 2480 2481 u8 reserved_at_60[0x4]; 2482 u8 clamp_tgt_rate[0x1]; 2483 u8 reserved_at_65[0x3]; 2484 u8 clamp_tgt_rate_after_time_inc[0x1]; 2485 u8 reserved_at_69[0x17]; 2486 2487 u8 reserved_at_80[0x20]; 2488 2489 u8 rpg_time_reset[0x20]; 2490 2491 u8 rpg_byte_reset[0x20]; 2492 2493 u8 rpg_threshold[0x20]; 2494 2495 u8 rpg_max_rate[0x20]; 2496 2497 u8 rpg_ai_rate[0x20]; 2498 2499 u8 rpg_hai_rate[0x20]; 2500 2501 u8 rpg_gd[0x20]; 2502 2503 u8 rpg_min_dec_fac[0x20]; 2504 2505 u8 rpg_min_rate[0x20]; 2506 2507 u8 reserved_at_1c0[0xe0]; 2508 2509 u8 rate_to_set_on_first_cnp[0x20]; 2510 2511 u8 dce_tcp_g[0x20]; 2512 2513 u8 dce_tcp_rtt[0x20]; 2514 2515 u8 rate_reduce_monitor_period[0x20]; 2516 2517 u8 reserved_at_320[0x20]; 2518 2519 u8 initial_alpha_value[0x20]; 2520 2521 u8 reserved_at_360[0x4a0]; 2522 }; 2523 2524 struct mlx5_ifc_cong_control_r_roce_general_bits { 2525 u8 reserved_at_0[0x80]; 2526 2527 u8 reserved_at_80[0x10]; 2528 u8 rtt_resp_dscp_valid[0x1]; 2529 u8 reserved_at_91[0x9]; 2530 u8 rtt_resp_dscp[0x6]; 2531 2532 u8 reserved_at_a0[0x760]; 2533 }; 2534 2535 struct mlx5_ifc_cong_control_802_1qau_rp_bits { 2536 u8 reserved_at_0[0x80]; 2537 2538 u8 rppp_max_rps[0x20]; 2539 2540 u8 rpg_time_reset[0x20]; 2541 2542 u8 rpg_byte_reset[0x20]; 2543 2544 u8 rpg_threshold[0x20]; 2545 2546 u8 rpg_max_rate[0x20]; 2547 2548 u8 rpg_ai_rate[0x20]; 2549 2550 u8 rpg_hai_rate[0x20]; 2551 2552 u8 rpg_gd[0x20]; 2553 2554 u8 rpg_min_dec_fac[0x20]; 2555 2556 u8 rpg_min_rate[0x20]; 2557 2558 u8 reserved_at_1c0[0x640]; 2559 }; 2560 2561 enum { 2562 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1, 2563 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2, 2564 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4, 2565 }; 2566 2567 struct mlx5_ifc_resize_field_select_bits { 2568 u8 resize_field_select[0x20]; 2569 }; 2570 2571 struct mlx5_ifc_resource_dump_bits { 2572 u8 more_dump[0x1]; 2573 u8 inline_dump[0x1]; 2574 u8 reserved_at_2[0xa]; 2575 u8 seq_num[0x4]; 2576 u8 segment_type[0x10]; 2577 2578 u8 reserved_at_20[0x10]; 2579 u8 vhca_id[0x10]; 2580 2581 u8 index1[0x20]; 2582 2583 u8 index2[0x20]; 2584 2585 u8 num_of_obj1[0x10]; 2586 u8 num_of_obj2[0x10]; 2587 2588 u8 reserved_at_a0[0x20]; 2589 2590 u8 device_opaque[0x40]; 2591 2592 u8 mkey[0x20]; 2593 2594 u8 size[0x20]; 2595 2596 u8 address[0x40]; 2597 2598 u8 inline_data[52][0x20]; 2599 }; 2600 2601 struct mlx5_ifc_resource_dump_menu_record_bits { 2602 u8 reserved_at_0[0x4]; 2603 u8 num_of_obj2_supports_active[0x1]; 2604 u8 num_of_obj2_supports_all[0x1]; 2605 u8 must_have_num_of_obj2[0x1]; 2606 u8 support_num_of_obj2[0x1]; 2607 u8 num_of_obj1_supports_active[0x1]; 2608 u8 num_of_obj1_supports_all[0x1]; 2609 u8 must_have_num_of_obj1[0x1]; 2610 u8 support_num_of_obj1[0x1]; 2611 u8 must_have_index2[0x1]; 2612 u8 support_index2[0x1]; 2613 u8 must_have_index1[0x1]; 2614 u8 support_index1[0x1]; 2615 u8 segment_type[0x10]; 2616 2617 u8 segment_name[4][0x20]; 2618 2619 u8 index1_name[4][0x20]; 2620 2621 u8 index2_name[4][0x20]; 2622 }; 2623 2624 struct mlx5_ifc_resource_dump_segment_header_bits { 2625 u8 length_dw[0x10]; 2626 u8 segment_type[0x10]; 2627 }; 2628 2629 struct mlx5_ifc_resource_dump_command_segment_bits { 2630 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2631 2632 u8 segment_called[0x10]; 2633 u8 vhca_id[0x10]; 2634 2635 u8 index1[0x20]; 2636 2637 u8 index2[0x20]; 2638 2639 u8 num_of_obj1[0x10]; 2640 u8 num_of_obj2[0x10]; 2641 }; 2642 2643 struct mlx5_ifc_resource_dump_error_segment_bits { 2644 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2645 2646 u8 reserved_at_20[0x10]; 2647 u8 syndrome_id[0x10]; 2648 2649 u8 reserved_at_40[0x40]; 2650 2651 u8 error[8][0x20]; 2652 }; 2653 2654 struct mlx5_ifc_resource_dump_info_segment_bits { 2655 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2656 2657 u8 reserved_at_20[0x18]; 2658 u8 dump_version[0x8]; 2659 2660 u8 hw_version[0x20]; 2661 2662 u8 fw_version[0x20]; 2663 }; 2664 2665 struct mlx5_ifc_resource_dump_menu_segment_bits { 2666 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2667 2668 u8 reserved_at_20[0x10]; 2669 u8 num_of_records[0x10]; 2670 2671 struct mlx5_ifc_resource_dump_menu_record_bits record[]; 2672 }; 2673 2674 struct mlx5_ifc_resource_dump_resource_segment_bits { 2675 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2676 2677 u8 reserved_at_20[0x20]; 2678 2679 u8 index1[0x20]; 2680 2681 u8 index2[0x20]; 2682 2683 u8 payload[][0x20]; 2684 }; 2685 2686 struct mlx5_ifc_resource_dump_terminate_segment_bits { 2687 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2688 }; 2689 2690 struct mlx5_ifc_menu_resource_dump_response_bits { 2691 struct mlx5_ifc_resource_dump_info_segment_bits info; 2692 struct mlx5_ifc_resource_dump_command_segment_bits cmd; 2693 struct mlx5_ifc_resource_dump_menu_segment_bits menu; 2694 struct mlx5_ifc_resource_dump_terminate_segment_bits terminate; 2695 }; 2696 2697 enum { 2698 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1, 2699 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2, 2700 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4, 2701 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8, 2702 }; 2703 2704 struct mlx5_ifc_modify_field_select_bits { 2705 u8 modify_field_select[0x20]; 2706 }; 2707 2708 struct mlx5_ifc_field_select_r_roce_np_bits { 2709 u8 field_select_r_roce_np[0x20]; 2710 }; 2711 2712 struct mlx5_ifc_field_select_r_roce_rp_bits { 2713 u8 field_select_r_roce_rp[0x20]; 2714 }; 2715 2716 enum { 2717 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4, 2718 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8, 2719 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10, 2720 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20, 2721 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40, 2722 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80, 2723 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100, 2724 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200, 2725 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400, 2726 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800, 2727 }; 2728 2729 struct mlx5_ifc_field_select_802_1qau_rp_bits { 2730 u8 field_select_8021qaurp[0x20]; 2731 }; 2732 2733 struct mlx5_ifc_phys_layer_recovery_cntrs_bits { 2734 u8 total_successful_recovery_events[0x20]; 2735 2736 u8 reserved_at_20[0x7a0]; 2737 }; 2738 2739 struct mlx5_ifc_phys_layer_cntrs_bits { 2740 u8 time_since_last_clear_high[0x20]; 2741 2742 u8 time_since_last_clear_low[0x20]; 2743 2744 u8 symbol_errors_high[0x20]; 2745 2746 u8 symbol_errors_low[0x20]; 2747 2748 u8 sync_headers_errors_high[0x20]; 2749 2750 u8 sync_headers_errors_low[0x20]; 2751 2752 u8 edpl_bip_errors_lane0_high[0x20]; 2753 2754 u8 edpl_bip_errors_lane0_low[0x20]; 2755 2756 u8 edpl_bip_errors_lane1_high[0x20]; 2757 2758 u8 edpl_bip_errors_lane1_low[0x20]; 2759 2760 u8 edpl_bip_errors_lane2_high[0x20]; 2761 2762 u8 edpl_bip_errors_lane2_low[0x20]; 2763 2764 u8 edpl_bip_errors_lane3_high[0x20]; 2765 2766 u8 edpl_bip_errors_lane3_low[0x20]; 2767 2768 u8 fc_fec_corrected_blocks_lane0_high[0x20]; 2769 2770 u8 fc_fec_corrected_blocks_lane0_low[0x20]; 2771 2772 u8 fc_fec_corrected_blocks_lane1_high[0x20]; 2773 2774 u8 fc_fec_corrected_blocks_lane1_low[0x20]; 2775 2776 u8 fc_fec_corrected_blocks_lane2_high[0x20]; 2777 2778 u8 fc_fec_corrected_blocks_lane2_low[0x20]; 2779 2780 u8 fc_fec_corrected_blocks_lane3_high[0x20]; 2781 2782 u8 fc_fec_corrected_blocks_lane3_low[0x20]; 2783 2784 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20]; 2785 2786 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20]; 2787 2788 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20]; 2789 2790 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20]; 2791 2792 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20]; 2793 2794 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20]; 2795 2796 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20]; 2797 2798 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20]; 2799 2800 u8 rs_fec_corrected_blocks_high[0x20]; 2801 2802 u8 rs_fec_corrected_blocks_low[0x20]; 2803 2804 u8 rs_fec_uncorrectable_blocks_high[0x20]; 2805 2806 u8 rs_fec_uncorrectable_blocks_low[0x20]; 2807 2808 u8 rs_fec_no_errors_blocks_high[0x20]; 2809 2810 u8 rs_fec_no_errors_blocks_low[0x20]; 2811 2812 u8 rs_fec_single_error_blocks_high[0x20]; 2813 2814 u8 rs_fec_single_error_blocks_low[0x20]; 2815 2816 u8 rs_fec_corrected_symbols_total_high[0x20]; 2817 2818 u8 rs_fec_corrected_symbols_total_low[0x20]; 2819 2820 u8 rs_fec_corrected_symbols_lane0_high[0x20]; 2821 2822 u8 rs_fec_corrected_symbols_lane0_low[0x20]; 2823 2824 u8 rs_fec_corrected_symbols_lane1_high[0x20]; 2825 2826 u8 rs_fec_corrected_symbols_lane1_low[0x20]; 2827 2828 u8 rs_fec_corrected_symbols_lane2_high[0x20]; 2829 2830 u8 rs_fec_corrected_symbols_lane2_low[0x20]; 2831 2832 u8 rs_fec_corrected_symbols_lane3_high[0x20]; 2833 2834 u8 rs_fec_corrected_symbols_lane3_low[0x20]; 2835 2836 u8 link_down_events[0x20]; 2837 2838 u8 successful_recovery_events[0x20]; 2839 2840 u8 reserved_at_640[0x180]; 2841 }; 2842 2843 struct mlx5_ifc_phys_layer_statistical_cntrs_bits { 2844 u8 time_since_last_clear_high[0x20]; 2845 2846 u8 time_since_last_clear_low[0x20]; 2847 2848 u8 phy_received_bits_high[0x20]; 2849 2850 u8 phy_received_bits_low[0x20]; 2851 2852 u8 phy_symbol_errors_high[0x20]; 2853 2854 u8 phy_symbol_errors_low[0x20]; 2855 2856 u8 phy_corrected_bits_high[0x20]; 2857 2858 u8 phy_corrected_bits_low[0x20]; 2859 2860 u8 phy_corrected_bits_lane0_high[0x20]; 2861 2862 u8 phy_corrected_bits_lane0_low[0x20]; 2863 2864 u8 phy_corrected_bits_lane1_high[0x20]; 2865 2866 u8 phy_corrected_bits_lane1_low[0x20]; 2867 2868 u8 phy_corrected_bits_lane2_high[0x20]; 2869 2870 u8 phy_corrected_bits_lane2_low[0x20]; 2871 2872 u8 phy_corrected_bits_lane3_high[0x20]; 2873 2874 u8 phy_corrected_bits_lane3_low[0x20]; 2875 2876 u8 reserved_at_200[0x5c0]; 2877 }; 2878 2879 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits { 2880 u8 symbol_error_counter[0x10]; 2881 2882 u8 link_error_recovery_counter[0x8]; 2883 2884 u8 link_downed_counter[0x8]; 2885 2886 u8 port_rcv_errors[0x10]; 2887 2888 u8 port_rcv_remote_physical_errors[0x10]; 2889 2890 u8 port_rcv_switch_relay_errors[0x10]; 2891 2892 u8 port_xmit_discards[0x10]; 2893 2894 u8 port_xmit_constraint_errors[0x8]; 2895 2896 u8 port_rcv_constraint_errors[0x8]; 2897 2898 u8 reserved_at_70[0x8]; 2899 2900 u8 link_overrun_errors[0x8]; 2901 2902 u8 reserved_at_80[0x10]; 2903 2904 u8 vl_15_dropped[0x10]; 2905 2906 u8 reserved_at_a0[0x80]; 2907 2908 u8 port_xmit_wait[0x20]; 2909 }; 2910 2911 struct mlx5_ifc_ib_ext_port_cntrs_grp_data_layout_bits { 2912 u8 reserved_at_0[0x300]; 2913 2914 u8 port_xmit_data_high[0x20]; 2915 2916 u8 port_xmit_data_low[0x20]; 2917 2918 u8 port_rcv_data_high[0x20]; 2919 2920 u8 port_rcv_data_low[0x20]; 2921 2922 u8 port_xmit_pkts_high[0x20]; 2923 2924 u8 port_xmit_pkts_low[0x20]; 2925 2926 u8 port_rcv_pkts_high[0x20]; 2927 2928 u8 port_rcv_pkts_low[0x20]; 2929 2930 u8 reserved_at_400[0x80]; 2931 2932 u8 port_unicast_xmit_pkts_high[0x20]; 2933 2934 u8 port_unicast_xmit_pkts_low[0x20]; 2935 2936 u8 port_multicast_xmit_pkts_high[0x20]; 2937 2938 u8 port_multicast_xmit_pkts_low[0x20]; 2939 2940 u8 port_unicast_rcv_pkts_high[0x20]; 2941 2942 u8 port_unicast_rcv_pkts_low[0x20]; 2943 2944 u8 port_multicast_rcv_pkts_high[0x20]; 2945 2946 u8 port_multicast_rcv_pkts_low[0x20]; 2947 2948 u8 reserved_at_580[0x240]; 2949 }; 2950 2951 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits { 2952 u8 transmit_queue_high[0x20]; 2953 2954 u8 transmit_queue_low[0x20]; 2955 2956 u8 no_buffer_discard_uc_high[0x20]; 2957 2958 u8 no_buffer_discard_uc_low[0x20]; 2959 2960 u8 reserved_at_80[0x740]; 2961 }; 2962 2963 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits { 2964 u8 wred_discard_high[0x20]; 2965 2966 u8 wred_discard_low[0x20]; 2967 2968 u8 ecn_marked_tc_high[0x20]; 2969 2970 u8 ecn_marked_tc_low[0x20]; 2971 2972 u8 reserved_at_80[0x740]; 2973 }; 2974 2975 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits { 2976 u8 rx_octets_high[0x20]; 2977 2978 u8 rx_octets_low[0x20]; 2979 2980 u8 reserved_at_40[0xc0]; 2981 2982 u8 rx_frames_high[0x20]; 2983 2984 u8 rx_frames_low[0x20]; 2985 2986 u8 tx_octets_high[0x20]; 2987 2988 u8 tx_octets_low[0x20]; 2989 2990 u8 reserved_at_180[0xc0]; 2991 2992 u8 tx_frames_high[0x20]; 2993 2994 u8 tx_frames_low[0x20]; 2995 2996 u8 rx_pause_high[0x20]; 2997 2998 u8 rx_pause_low[0x20]; 2999 3000 u8 rx_pause_duration_high[0x20]; 3001 3002 u8 rx_pause_duration_low[0x20]; 3003 3004 u8 tx_pause_high[0x20]; 3005 3006 u8 tx_pause_low[0x20]; 3007 3008 u8 tx_pause_duration_high[0x20]; 3009 3010 u8 tx_pause_duration_low[0x20]; 3011 3012 u8 rx_pause_transition_high[0x20]; 3013 3014 u8 rx_pause_transition_low[0x20]; 3015 3016 u8 rx_discards_high[0x20]; 3017 3018 u8 rx_discards_low[0x20]; 3019 3020 u8 device_stall_minor_watermark_cnt_high[0x20]; 3021 3022 u8 device_stall_minor_watermark_cnt_low[0x20]; 3023 3024 u8 device_stall_critical_watermark_cnt_high[0x20]; 3025 3026 u8 device_stall_critical_watermark_cnt_low[0x20]; 3027 3028 u8 reserved_at_480[0x340]; 3029 }; 3030 3031 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits { 3032 u8 port_transmit_wait_high[0x20]; 3033 3034 u8 port_transmit_wait_low[0x20]; 3035 3036 u8 reserved_at_40[0x100]; 3037 3038 u8 rx_buffer_almost_full_high[0x20]; 3039 3040 u8 rx_buffer_almost_full_low[0x20]; 3041 3042 u8 rx_buffer_full_high[0x20]; 3043 3044 u8 rx_buffer_full_low[0x20]; 3045 3046 u8 rx_icrc_encapsulated_high[0x20]; 3047 3048 u8 rx_icrc_encapsulated_low[0x20]; 3049 3050 u8 reserved_at_200[0x5c0]; 3051 }; 3052 3053 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits { 3054 u8 dot3stats_alignment_errors_high[0x20]; 3055 3056 u8 dot3stats_alignment_errors_low[0x20]; 3057 3058 u8 dot3stats_fcs_errors_high[0x20]; 3059 3060 u8 dot3stats_fcs_errors_low[0x20]; 3061 3062 u8 dot3stats_single_collision_frames_high[0x20]; 3063 3064 u8 dot3stats_single_collision_frames_low[0x20]; 3065 3066 u8 dot3stats_multiple_collision_frames_high[0x20]; 3067 3068 u8 dot3stats_multiple_collision_frames_low[0x20]; 3069 3070 u8 dot3stats_sqe_test_errors_high[0x20]; 3071 3072 u8 dot3stats_sqe_test_errors_low[0x20]; 3073 3074 u8 dot3stats_deferred_transmissions_high[0x20]; 3075 3076 u8 dot3stats_deferred_transmissions_low[0x20]; 3077 3078 u8 dot3stats_late_collisions_high[0x20]; 3079 3080 u8 dot3stats_late_collisions_low[0x20]; 3081 3082 u8 dot3stats_excessive_collisions_high[0x20]; 3083 3084 u8 dot3stats_excessive_collisions_low[0x20]; 3085 3086 u8 dot3stats_internal_mac_transmit_errors_high[0x20]; 3087 3088 u8 dot3stats_internal_mac_transmit_errors_low[0x20]; 3089 3090 u8 dot3stats_carrier_sense_errors_high[0x20]; 3091 3092 u8 dot3stats_carrier_sense_errors_low[0x20]; 3093 3094 u8 dot3stats_frame_too_longs_high[0x20]; 3095 3096 u8 dot3stats_frame_too_longs_low[0x20]; 3097 3098 u8 dot3stats_internal_mac_receive_errors_high[0x20]; 3099 3100 u8 dot3stats_internal_mac_receive_errors_low[0x20]; 3101 3102 u8 dot3stats_symbol_errors_high[0x20]; 3103 3104 u8 dot3stats_symbol_errors_low[0x20]; 3105 3106 u8 dot3control_in_unknown_opcodes_high[0x20]; 3107 3108 u8 dot3control_in_unknown_opcodes_low[0x20]; 3109 3110 u8 dot3in_pause_frames_high[0x20]; 3111 3112 u8 dot3in_pause_frames_low[0x20]; 3113 3114 u8 dot3out_pause_frames_high[0x20]; 3115 3116 u8 dot3out_pause_frames_low[0x20]; 3117 3118 u8 reserved_at_400[0x3c0]; 3119 }; 3120 3121 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits { 3122 u8 ether_stats_drop_events_high[0x20]; 3123 3124 u8 ether_stats_drop_events_low[0x20]; 3125 3126 u8 ether_stats_octets_high[0x20]; 3127 3128 u8 ether_stats_octets_low[0x20]; 3129 3130 u8 ether_stats_pkts_high[0x20]; 3131 3132 u8 ether_stats_pkts_low[0x20]; 3133 3134 u8 ether_stats_broadcast_pkts_high[0x20]; 3135 3136 u8 ether_stats_broadcast_pkts_low[0x20]; 3137 3138 u8 ether_stats_multicast_pkts_high[0x20]; 3139 3140 u8 ether_stats_multicast_pkts_low[0x20]; 3141 3142 u8 ether_stats_crc_align_errors_high[0x20]; 3143 3144 u8 ether_stats_crc_align_errors_low[0x20]; 3145 3146 u8 ether_stats_undersize_pkts_high[0x20]; 3147 3148 u8 ether_stats_undersize_pkts_low[0x20]; 3149 3150 u8 ether_stats_oversize_pkts_high[0x20]; 3151 3152 u8 ether_stats_oversize_pkts_low[0x20]; 3153 3154 u8 ether_stats_fragments_high[0x20]; 3155 3156 u8 ether_stats_fragments_low[0x20]; 3157 3158 u8 ether_stats_jabbers_high[0x20]; 3159 3160 u8 ether_stats_jabbers_low[0x20]; 3161 3162 u8 ether_stats_collisions_high[0x20]; 3163 3164 u8 ether_stats_collisions_low[0x20]; 3165 3166 u8 ether_stats_pkts64octets_high[0x20]; 3167 3168 u8 ether_stats_pkts64octets_low[0x20]; 3169 3170 u8 ether_stats_pkts65to127octets_high[0x20]; 3171 3172 u8 ether_stats_pkts65to127octets_low[0x20]; 3173 3174 u8 ether_stats_pkts128to255octets_high[0x20]; 3175 3176 u8 ether_stats_pkts128to255octets_low[0x20]; 3177 3178 u8 ether_stats_pkts256to511octets_high[0x20]; 3179 3180 u8 ether_stats_pkts256to511octets_low[0x20]; 3181 3182 u8 ether_stats_pkts512to1023octets_high[0x20]; 3183 3184 u8 ether_stats_pkts512to1023octets_low[0x20]; 3185 3186 u8 ether_stats_pkts1024to1518octets_high[0x20]; 3187 3188 u8 ether_stats_pkts1024to1518octets_low[0x20]; 3189 3190 u8 ether_stats_pkts1519to2047octets_high[0x20]; 3191 3192 u8 ether_stats_pkts1519to2047octets_low[0x20]; 3193 3194 u8 ether_stats_pkts2048to4095octets_high[0x20]; 3195 3196 u8 ether_stats_pkts2048to4095octets_low[0x20]; 3197 3198 u8 ether_stats_pkts4096to8191octets_high[0x20]; 3199 3200 u8 ether_stats_pkts4096to8191octets_low[0x20]; 3201 3202 u8 ether_stats_pkts8192to10239octets_high[0x20]; 3203 3204 u8 ether_stats_pkts8192to10239octets_low[0x20]; 3205 3206 u8 reserved_at_540[0x280]; 3207 }; 3208 3209 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits { 3210 u8 if_in_octets_high[0x20]; 3211 3212 u8 if_in_octets_low[0x20]; 3213 3214 u8 if_in_ucast_pkts_high[0x20]; 3215 3216 u8 if_in_ucast_pkts_low[0x20]; 3217 3218 u8 if_in_discards_high[0x20]; 3219 3220 u8 if_in_discards_low[0x20]; 3221 3222 u8 if_in_errors_high[0x20]; 3223 3224 u8 if_in_errors_low[0x20]; 3225 3226 u8 if_in_unknown_protos_high[0x20]; 3227 3228 u8 if_in_unknown_protos_low[0x20]; 3229 3230 u8 if_out_octets_high[0x20]; 3231 3232 u8 if_out_octets_low[0x20]; 3233 3234 u8 if_out_ucast_pkts_high[0x20]; 3235 3236 u8 if_out_ucast_pkts_low[0x20]; 3237 3238 u8 if_out_discards_high[0x20]; 3239 3240 u8 if_out_discards_low[0x20]; 3241 3242 u8 if_out_errors_high[0x20]; 3243 3244 u8 if_out_errors_low[0x20]; 3245 3246 u8 if_in_multicast_pkts_high[0x20]; 3247 3248 u8 if_in_multicast_pkts_low[0x20]; 3249 3250 u8 if_in_broadcast_pkts_high[0x20]; 3251 3252 u8 if_in_broadcast_pkts_low[0x20]; 3253 3254 u8 if_out_multicast_pkts_high[0x20]; 3255 3256 u8 if_out_multicast_pkts_low[0x20]; 3257 3258 u8 if_out_broadcast_pkts_high[0x20]; 3259 3260 u8 if_out_broadcast_pkts_low[0x20]; 3261 3262 u8 reserved_at_340[0x480]; 3263 }; 3264 3265 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits { 3266 u8 a_frames_transmitted_ok_high[0x20]; 3267 3268 u8 a_frames_transmitted_ok_low[0x20]; 3269 3270 u8 a_frames_received_ok_high[0x20]; 3271 3272 u8 a_frames_received_ok_low[0x20]; 3273 3274 u8 a_frame_check_sequence_errors_high[0x20]; 3275 3276 u8 a_frame_check_sequence_errors_low[0x20]; 3277 3278 u8 a_alignment_errors_high[0x20]; 3279 3280 u8 a_alignment_errors_low[0x20]; 3281 3282 u8 a_octets_transmitted_ok_high[0x20]; 3283 3284 u8 a_octets_transmitted_ok_low[0x20]; 3285 3286 u8 a_octets_received_ok_high[0x20]; 3287 3288 u8 a_octets_received_ok_low[0x20]; 3289 3290 u8 a_multicast_frames_xmitted_ok_high[0x20]; 3291 3292 u8 a_multicast_frames_xmitted_ok_low[0x20]; 3293 3294 u8 a_broadcast_frames_xmitted_ok_high[0x20]; 3295 3296 u8 a_broadcast_frames_xmitted_ok_low[0x20]; 3297 3298 u8 a_multicast_frames_received_ok_high[0x20]; 3299 3300 u8 a_multicast_frames_received_ok_low[0x20]; 3301 3302 u8 a_broadcast_frames_received_ok_high[0x20]; 3303 3304 u8 a_broadcast_frames_received_ok_low[0x20]; 3305 3306 u8 a_in_range_length_errors_high[0x20]; 3307 3308 u8 a_in_range_length_errors_low[0x20]; 3309 3310 u8 a_out_of_range_length_field_high[0x20]; 3311 3312 u8 a_out_of_range_length_field_low[0x20]; 3313 3314 u8 a_frame_too_long_errors_high[0x20]; 3315 3316 u8 a_frame_too_long_errors_low[0x20]; 3317 3318 u8 a_symbol_error_during_carrier_high[0x20]; 3319 3320 u8 a_symbol_error_during_carrier_low[0x20]; 3321 3322 u8 a_mac_control_frames_transmitted_high[0x20]; 3323 3324 u8 a_mac_control_frames_transmitted_low[0x20]; 3325 3326 u8 a_mac_control_frames_received_high[0x20]; 3327 3328 u8 a_mac_control_frames_received_low[0x20]; 3329 3330 u8 a_unsupported_opcodes_received_high[0x20]; 3331 3332 u8 a_unsupported_opcodes_received_low[0x20]; 3333 3334 u8 a_pause_mac_ctrl_frames_received_high[0x20]; 3335 3336 u8 a_pause_mac_ctrl_frames_received_low[0x20]; 3337 3338 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20]; 3339 3340 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20]; 3341 3342 u8 reserved_at_4c0[0x300]; 3343 }; 3344 3345 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits { 3346 u8 life_time_counter_high[0x20]; 3347 3348 u8 life_time_counter_low[0x20]; 3349 3350 u8 rx_errors[0x20]; 3351 3352 u8 tx_errors[0x20]; 3353 3354 u8 l0_to_recovery_eieos[0x20]; 3355 3356 u8 l0_to_recovery_ts[0x20]; 3357 3358 u8 l0_to_recovery_framing[0x20]; 3359 3360 u8 l0_to_recovery_retrain[0x20]; 3361 3362 u8 crc_error_dllp[0x20]; 3363 3364 u8 crc_error_tlp[0x20]; 3365 3366 u8 tx_overflow_buffer_pkt_high[0x20]; 3367 3368 u8 tx_overflow_buffer_pkt_low[0x20]; 3369 3370 u8 outbound_stalled_reads[0x20]; 3371 3372 u8 outbound_stalled_writes[0x20]; 3373 3374 u8 outbound_stalled_reads_events[0x20]; 3375 3376 u8 outbound_stalled_writes_events[0x20]; 3377 3378 u8 reserved_at_200[0x5c0]; 3379 }; 3380 3381 struct mlx5_ifc_cmd_inter_comp_event_bits { 3382 u8 command_completion_vector[0x20]; 3383 3384 u8 reserved_at_20[0xc0]; 3385 }; 3386 3387 struct mlx5_ifc_stall_vl_event_bits { 3388 u8 reserved_at_0[0x18]; 3389 u8 port_num[0x1]; 3390 u8 reserved_at_19[0x3]; 3391 u8 vl[0x4]; 3392 3393 u8 reserved_at_20[0xa0]; 3394 }; 3395 3396 struct mlx5_ifc_db_bf_congestion_event_bits { 3397 u8 event_subtype[0x8]; 3398 u8 reserved_at_8[0x8]; 3399 u8 congestion_level[0x8]; 3400 u8 reserved_at_18[0x8]; 3401 3402 u8 reserved_at_20[0xa0]; 3403 }; 3404 3405 struct mlx5_ifc_gpio_event_bits { 3406 u8 reserved_at_0[0x60]; 3407 3408 u8 gpio_event_hi[0x20]; 3409 3410 u8 gpio_event_lo[0x20]; 3411 3412 u8 reserved_at_a0[0x40]; 3413 }; 3414 3415 struct mlx5_ifc_port_state_change_event_bits { 3416 u8 reserved_at_0[0x40]; 3417 3418 u8 port_num[0x4]; 3419 u8 reserved_at_44[0x1c]; 3420 3421 u8 reserved_at_60[0x80]; 3422 }; 3423 3424 struct mlx5_ifc_dropped_packet_logged_bits { 3425 u8 reserved_at_0[0xe0]; 3426 }; 3427 3428 struct mlx5_ifc_nic_cap_reg_bits { 3429 u8 reserved_at_0[0x1a]; 3430 u8 vhca_icm_ctrl[0x1]; 3431 u8 reserved_at_1b[0x5]; 3432 3433 u8 reserved_at_20[0x60]; 3434 }; 3435 3436 struct mlx5_ifc_default_timeout_bits { 3437 u8 to_multiplier[0x3]; 3438 u8 reserved_at_3[0x9]; 3439 u8 to_value[0x14]; 3440 }; 3441 3442 struct mlx5_ifc_dtor_reg_bits { 3443 u8 reserved_at_0[0x20]; 3444 3445 struct mlx5_ifc_default_timeout_bits pcie_toggle_to; 3446 3447 u8 reserved_at_40[0x60]; 3448 3449 struct mlx5_ifc_default_timeout_bits health_poll_to; 3450 3451 struct mlx5_ifc_default_timeout_bits full_crdump_to; 3452 3453 struct mlx5_ifc_default_timeout_bits fw_reset_to; 3454 3455 struct mlx5_ifc_default_timeout_bits flush_on_err_to; 3456 3457 struct mlx5_ifc_default_timeout_bits pci_sync_update_to; 3458 3459 struct mlx5_ifc_default_timeout_bits tear_down_to; 3460 3461 struct mlx5_ifc_default_timeout_bits fsm_reactivate_to; 3462 3463 struct mlx5_ifc_default_timeout_bits reclaim_pages_to; 3464 3465 struct mlx5_ifc_default_timeout_bits reclaim_vfs_pages_to; 3466 3467 struct mlx5_ifc_default_timeout_bits reset_unload_to; 3468 3469 u8 reserved_at_1c0[0x20]; 3470 }; 3471 3472 struct mlx5_ifc_vhca_icm_ctrl_reg_bits { 3473 u8 vhca_id_valid[0x1]; 3474 u8 reserved_at_1[0xf]; 3475 u8 vhca_id[0x10]; 3476 3477 u8 reserved_at_20[0xa0]; 3478 3479 u8 cur_alloc_icm[0x20]; 3480 3481 u8 reserved_at_e0[0x120]; 3482 }; 3483 3484 enum { 3485 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1, 3486 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2, 3487 }; 3488 3489 struct mlx5_ifc_cq_error_bits { 3490 u8 reserved_at_0[0x8]; 3491 u8 cqn[0x18]; 3492 3493 u8 reserved_at_20[0x20]; 3494 3495 u8 reserved_at_40[0x18]; 3496 u8 syndrome[0x8]; 3497 3498 u8 reserved_at_60[0x80]; 3499 }; 3500 3501 struct mlx5_ifc_rdma_page_fault_event_bits { 3502 u8 bytes_committed[0x20]; 3503 3504 u8 r_key[0x20]; 3505 3506 u8 reserved_at_40[0x10]; 3507 u8 packet_len[0x10]; 3508 3509 u8 rdma_op_len[0x20]; 3510 3511 u8 rdma_va[0x40]; 3512 3513 u8 reserved_at_c0[0x5]; 3514 u8 rdma[0x1]; 3515 u8 write[0x1]; 3516 u8 requestor[0x1]; 3517 u8 qp_number[0x18]; 3518 }; 3519 3520 struct mlx5_ifc_wqe_associated_page_fault_event_bits { 3521 u8 bytes_committed[0x20]; 3522 3523 u8 reserved_at_20[0x10]; 3524 u8 wqe_index[0x10]; 3525 3526 u8 reserved_at_40[0x10]; 3527 u8 len[0x10]; 3528 3529 u8 reserved_at_60[0x60]; 3530 3531 u8 reserved_at_c0[0x5]; 3532 u8 rdma[0x1]; 3533 u8 write_read[0x1]; 3534 u8 requestor[0x1]; 3535 u8 qpn[0x18]; 3536 }; 3537 3538 struct mlx5_ifc_qp_events_bits { 3539 u8 reserved_at_0[0xa0]; 3540 3541 u8 type[0x8]; 3542 u8 reserved_at_a8[0x18]; 3543 3544 u8 reserved_at_c0[0x8]; 3545 u8 qpn_rqn_sqn[0x18]; 3546 }; 3547 3548 struct mlx5_ifc_dct_events_bits { 3549 u8 reserved_at_0[0xc0]; 3550 3551 u8 reserved_at_c0[0x8]; 3552 u8 dct_number[0x18]; 3553 }; 3554 3555 struct mlx5_ifc_comp_event_bits { 3556 u8 reserved_at_0[0xc0]; 3557 3558 u8 reserved_at_c0[0x8]; 3559 u8 cq_number[0x18]; 3560 }; 3561 3562 enum { 3563 MLX5_QPC_STATE_RST = 0x0, 3564 MLX5_QPC_STATE_INIT = 0x1, 3565 MLX5_QPC_STATE_RTR = 0x2, 3566 MLX5_QPC_STATE_RTS = 0x3, 3567 MLX5_QPC_STATE_SQER = 0x4, 3568 MLX5_QPC_STATE_ERR = 0x6, 3569 MLX5_QPC_STATE_SQD = 0x7, 3570 MLX5_QPC_STATE_SUSPENDED = 0x9, 3571 }; 3572 3573 enum { 3574 MLX5_QPC_ST_RC = 0x0, 3575 MLX5_QPC_ST_UC = 0x1, 3576 MLX5_QPC_ST_UD = 0x2, 3577 MLX5_QPC_ST_XRC = 0x3, 3578 MLX5_QPC_ST_DCI = 0x5, 3579 MLX5_QPC_ST_QP0 = 0x7, 3580 MLX5_QPC_ST_QP1 = 0x8, 3581 MLX5_QPC_ST_RAW_DATAGRAM = 0x9, 3582 MLX5_QPC_ST_REG_UMR = 0xc, 3583 }; 3584 3585 enum { 3586 MLX5_QPC_PM_STATE_ARMED = 0x0, 3587 MLX5_QPC_PM_STATE_REARM = 0x1, 3588 MLX5_QPC_PM_STATE_RESERVED = 0x2, 3589 MLX5_QPC_PM_STATE_MIGRATED = 0x3, 3590 }; 3591 3592 enum { 3593 MLX5_QPC_OFFLOAD_TYPE_RNDV = 0x1, 3594 }; 3595 3596 enum { 3597 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0, 3598 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1, 3599 }; 3600 3601 enum { 3602 MLX5_QPC_MTU_256_BYTES = 0x1, 3603 MLX5_QPC_MTU_512_BYTES = 0x2, 3604 MLX5_QPC_MTU_1K_BYTES = 0x3, 3605 MLX5_QPC_MTU_2K_BYTES = 0x4, 3606 MLX5_QPC_MTU_4K_BYTES = 0x5, 3607 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7, 3608 }; 3609 3610 enum { 3611 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1, 3612 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2, 3613 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3, 3614 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4, 3615 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5, 3616 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6, 3617 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7, 3618 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8, 3619 }; 3620 3621 enum { 3622 MLX5_QPC_CS_REQ_DISABLE = 0x0, 3623 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11, 3624 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22, 3625 }; 3626 3627 enum { 3628 MLX5_QPC_CS_RES_DISABLE = 0x0, 3629 MLX5_QPC_CS_RES_UP_TO_32B = 0x1, 3630 MLX5_QPC_CS_RES_UP_TO_64B = 0x2, 3631 }; 3632 3633 enum { 3634 MLX5_TIMESTAMP_FORMAT_FREE_RUNNING = 0x0, 3635 MLX5_TIMESTAMP_FORMAT_DEFAULT = 0x1, 3636 MLX5_TIMESTAMP_FORMAT_REAL_TIME = 0x2, 3637 }; 3638 3639 struct mlx5_ifc_qpc_bits { 3640 u8 state[0x4]; 3641 u8 lag_tx_port_affinity[0x4]; 3642 u8 st[0x8]; 3643 u8 reserved_at_10[0x2]; 3644 u8 isolate_vl_tc[0x1]; 3645 u8 pm_state[0x2]; 3646 u8 reserved_at_15[0x1]; 3647 u8 req_e2e_credit_mode[0x2]; 3648 u8 offload_type[0x4]; 3649 u8 end_padding_mode[0x2]; 3650 u8 reserved_at_1e[0x2]; 3651 3652 u8 wq_signature[0x1]; 3653 u8 block_lb_mc[0x1]; 3654 u8 atomic_like_write_en[0x1]; 3655 u8 latency_sensitive[0x1]; 3656 u8 reserved_at_24[0x1]; 3657 u8 drain_sigerr[0x1]; 3658 u8 reserved_at_26[0x1]; 3659 u8 dp_ordering_force[0x1]; 3660 u8 pd[0x18]; 3661 3662 u8 mtu[0x3]; 3663 u8 log_msg_max[0x5]; 3664 u8 reserved_at_48[0x1]; 3665 u8 log_rq_size[0x4]; 3666 u8 log_rq_stride[0x3]; 3667 u8 no_sq[0x1]; 3668 u8 log_sq_size[0x4]; 3669 u8 reserved_at_55[0x1]; 3670 u8 retry_mode[0x2]; 3671 u8 ts_format[0x2]; 3672 u8 reserved_at_5a[0x1]; 3673 u8 rlky[0x1]; 3674 u8 ulp_stateless_offload_mode[0x4]; 3675 3676 u8 counter_set_id[0x8]; 3677 u8 uar_page[0x18]; 3678 3679 u8 reserved_at_80[0x8]; 3680 u8 user_index[0x18]; 3681 3682 u8 reserved_at_a0[0x3]; 3683 u8 log_page_size[0x5]; 3684 u8 remote_qpn[0x18]; 3685 3686 struct mlx5_ifc_ads_bits primary_address_path; 3687 3688 struct mlx5_ifc_ads_bits secondary_address_path; 3689 3690 u8 log_ack_req_freq[0x4]; 3691 u8 reserved_at_384[0x4]; 3692 u8 log_sra_max[0x3]; 3693 u8 reserved_at_38b[0x2]; 3694 u8 retry_count[0x3]; 3695 u8 rnr_retry[0x3]; 3696 u8 reserved_at_393[0x1]; 3697 u8 fre[0x1]; 3698 u8 cur_rnr_retry[0x3]; 3699 u8 cur_retry_count[0x3]; 3700 u8 reserved_at_39b[0x5]; 3701 3702 u8 reserved_at_3a0[0x20]; 3703 3704 u8 reserved_at_3c0[0x8]; 3705 u8 next_send_psn[0x18]; 3706 3707 u8 reserved_at_3e0[0x3]; 3708 u8 log_num_dci_stream_channels[0x5]; 3709 u8 cqn_snd[0x18]; 3710 3711 u8 reserved_at_400[0x3]; 3712 u8 log_num_dci_errored_streams[0x5]; 3713 u8 deth_sqpn[0x18]; 3714 3715 u8 reserved_at_420[0x20]; 3716 3717 u8 reserved_at_440[0x8]; 3718 u8 last_acked_psn[0x18]; 3719 3720 u8 reserved_at_460[0x8]; 3721 u8 ssn[0x18]; 3722 3723 u8 reserved_at_480[0x8]; 3724 u8 log_rra_max[0x3]; 3725 u8 reserved_at_48b[0x1]; 3726 u8 atomic_mode[0x4]; 3727 u8 rre[0x1]; 3728 u8 rwe[0x1]; 3729 u8 rae[0x1]; 3730 u8 reserved_at_493[0x1]; 3731 u8 page_offset[0x6]; 3732 u8 reserved_at_49a[0x2]; 3733 u8 dp_ordering_1[0x1]; 3734 u8 cd_slave_receive[0x1]; 3735 u8 cd_slave_send[0x1]; 3736 u8 cd_master[0x1]; 3737 3738 u8 reserved_at_4a0[0x3]; 3739 u8 min_rnr_nak[0x5]; 3740 u8 next_rcv_psn[0x18]; 3741 3742 u8 reserved_at_4c0[0x8]; 3743 u8 xrcd[0x18]; 3744 3745 u8 reserved_at_4e0[0x8]; 3746 u8 cqn_rcv[0x18]; 3747 3748 u8 dbr_addr[0x40]; 3749 3750 u8 q_key[0x20]; 3751 3752 u8 reserved_at_560[0x5]; 3753 u8 rq_type[0x3]; 3754 u8 srqn_rmpn_xrqn[0x18]; 3755 3756 u8 reserved_at_580[0x8]; 3757 u8 rmsn[0x18]; 3758 3759 u8 hw_sq_wqebb_counter[0x10]; 3760 u8 sw_sq_wqebb_counter[0x10]; 3761 3762 u8 hw_rq_counter[0x20]; 3763 3764 u8 sw_rq_counter[0x20]; 3765 3766 u8 reserved_at_600[0x20]; 3767 3768 u8 reserved_at_620[0xf]; 3769 u8 cgs[0x1]; 3770 u8 cs_req[0x8]; 3771 u8 cs_res[0x8]; 3772 3773 u8 dc_access_key[0x40]; 3774 3775 u8 reserved_at_680[0x3]; 3776 u8 dbr_umem_valid[0x1]; 3777 3778 u8 reserved_at_684[0xbc]; 3779 }; 3780 3781 struct mlx5_ifc_roce_addr_layout_bits { 3782 u8 source_l3_address[16][0x8]; 3783 3784 u8 reserved_at_80[0x3]; 3785 u8 vlan_valid[0x1]; 3786 u8 vlan_id[0xc]; 3787 u8 source_mac_47_32[0x10]; 3788 3789 u8 source_mac_31_0[0x20]; 3790 3791 u8 reserved_at_c0[0x14]; 3792 u8 roce_l3_type[0x4]; 3793 u8 roce_version[0x8]; 3794 3795 u8 reserved_at_e0[0x20]; 3796 }; 3797 3798 struct mlx5_ifc_crypto_cap_bits { 3799 u8 reserved_at_0[0x3]; 3800 u8 synchronize_dek[0x1]; 3801 u8 int_kek_manual[0x1]; 3802 u8 int_kek_auto[0x1]; 3803 u8 reserved_at_6[0x1a]; 3804 3805 u8 reserved_at_20[0x3]; 3806 u8 log_dek_max_alloc[0x5]; 3807 u8 reserved_at_28[0x3]; 3808 u8 log_max_num_deks[0x5]; 3809 u8 reserved_at_30[0x10]; 3810 3811 u8 reserved_at_40[0x20]; 3812 3813 u8 reserved_at_60[0x3]; 3814 u8 log_dek_granularity[0x5]; 3815 u8 reserved_at_68[0x3]; 3816 u8 log_max_num_int_kek[0x5]; 3817 u8 sw_wrapped_dek[0x10]; 3818 3819 u8 reserved_at_80[0x780]; 3820 }; 3821 3822 struct mlx5_ifc_shampo_cap_bits { 3823 u8 reserved_at_0[0x3]; 3824 u8 shampo_log_max_reservation_size[0x5]; 3825 u8 reserved_at_8[0x3]; 3826 u8 shampo_log_min_reservation_size[0x5]; 3827 u8 shampo_min_mss_size[0x10]; 3828 3829 u8 shampo_header_split[0x1]; 3830 u8 shampo_header_split_data_merge[0x1]; 3831 u8 reserved_at_22[0x1]; 3832 u8 shampo_log_max_headers_entry_size[0x5]; 3833 u8 reserved_at_28[0x18]; 3834 3835 u8 reserved_at_40[0x7c0]; 3836 }; 3837 3838 union mlx5_ifc_hca_cap_union_bits { 3839 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap; 3840 struct mlx5_ifc_cmd_hca_cap_2_bits cmd_hca_cap_2; 3841 struct mlx5_ifc_odp_cap_bits odp_cap; 3842 struct mlx5_ifc_atomic_caps_bits atomic_caps; 3843 struct mlx5_ifc_roce_cap_bits roce_cap; 3844 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps; 3845 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap; 3846 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap; 3847 struct mlx5_ifc_wqe_based_flow_table_cap_bits wqe_based_flow_table_cap; 3848 struct mlx5_ifc_esw_cap_bits esw_cap; 3849 struct mlx5_ifc_e_switch_cap_bits e_switch_cap; 3850 struct mlx5_ifc_port_selection_cap_bits port_selection_cap; 3851 struct mlx5_ifc_qos_cap_bits qos_cap; 3852 struct mlx5_ifc_debug_cap_bits debug_cap; 3853 struct mlx5_ifc_fpga_cap_bits fpga_cap; 3854 struct mlx5_ifc_tls_cap_bits tls_cap; 3855 struct mlx5_ifc_device_mem_cap_bits device_mem_cap; 3856 struct mlx5_ifc_virtio_emulation_cap_bits virtio_emulation_cap; 3857 struct mlx5_ifc_tlp_dev_emu_capabilities_bits tlp_dev_emu_capabilities; 3858 struct mlx5_ifc_macsec_cap_bits macsec_cap; 3859 struct mlx5_ifc_crypto_cap_bits crypto_cap; 3860 struct mlx5_ifc_ipsec_cap_bits ipsec_cap; 3861 struct mlx5_ifc_psp_cap_bits psp_cap; 3862 u8 reserved_at_0[0x8000]; 3863 }; 3864 3865 enum { 3866 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1, 3867 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2, 3868 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4, 3869 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8, 3870 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT = 0x10, 3871 MLX5_FLOW_CONTEXT_ACTION_DECAP = 0x20, 3872 MLX5_FLOW_CONTEXT_ACTION_MOD_HDR = 0x40, 3873 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP = 0x80, 3874 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100, 3875 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2 = 0x400, 3876 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2 = 0x800, 3877 MLX5_FLOW_CONTEXT_ACTION_CRYPTO_DECRYPT = 0x1000, 3878 MLX5_FLOW_CONTEXT_ACTION_CRYPTO_ENCRYPT = 0x2000, 3879 MLX5_FLOW_CONTEXT_ACTION_EXECUTE_ASO = 0x4000, 3880 }; 3881 3882 enum { 3883 MLX5_FLOW_CONTEXT_FLOW_SOURCE_ANY_VPORT = 0x0, 3884 MLX5_FLOW_CONTEXT_FLOW_SOURCE_UPLINK = 0x1, 3885 MLX5_FLOW_CONTEXT_FLOW_SOURCE_LOCAL_VPORT = 0x2, 3886 }; 3887 3888 enum { 3889 MLX5_FLOW_CONTEXT_ENCRYPT_DECRYPT_TYPE_IPSEC = 0x0, 3890 MLX5_FLOW_CONTEXT_ENCRYPT_DECRYPT_TYPE_MACSEC = 0x1, 3891 MLX5_FLOW_CONTEXT_ENCRYPT_DECRYPT_TYPE_PSP = 0x2, 3892 }; 3893 3894 struct mlx5_ifc_vlan_bits { 3895 u8 ethtype[0x10]; 3896 u8 prio[0x3]; 3897 u8 cfi[0x1]; 3898 u8 vid[0xc]; 3899 }; 3900 3901 enum { 3902 MLX5_FLOW_METER_COLOR_RED = 0x0, 3903 MLX5_FLOW_METER_COLOR_YELLOW = 0x1, 3904 MLX5_FLOW_METER_COLOR_GREEN = 0x2, 3905 MLX5_FLOW_METER_COLOR_UNDEFINED = 0x3, 3906 }; 3907 3908 enum { 3909 MLX5_EXE_ASO_FLOW_METER = 0x2, 3910 }; 3911 3912 struct mlx5_ifc_exe_aso_ctrl_flow_meter_bits { 3913 u8 return_reg_id[0x4]; 3914 u8 aso_type[0x4]; 3915 u8 reserved_at_8[0x14]; 3916 u8 action[0x1]; 3917 u8 init_color[0x2]; 3918 u8 meter_id[0x1]; 3919 }; 3920 3921 union mlx5_ifc_exe_aso_ctrl { 3922 struct mlx5_ifc_exe_aso_ctrl_flow_meter_bits exe_aso_ctrl_flow_meter; 3923 }; 3924 3925 struct mlx5_ifc_execute_aso_bits { 3926 u8 valid[0x1]; 3927 u8 reserved_at_1[0x7]; 3928 u8 aso_object_id[0x18]; 3929 3930 union mlx5_ifc_exe_aso_ctrl exe_aso_ctrl; 3931 }; 3932 3933 struct mlx5_ifc_flow_context_bits { 3934 struct mlx5_ifc_vlan_bits push_vlan; 3935 3936 u8 group_id[0x20]; 3937 3938 u8 reserved_at_40[0x8]; 3939 u8 flow_tag[0x18]; 3940 3941 u8 reserved_at_60[0x10]; 3942 u8 action[0x10]; 3943 3944 u8 extended_destination[0x1]; 3945 u8 uplink_hairpin_en[0x1]; 3946 u8 flow_source[0x2]; 3947 u8 encrypt_decrypt_type[0x4]; 3948 u8 destination_list_size[0x18]; 3949 3950 u8 reserved_at_a0[0x8]; 3951 u8 flow_counter_list_size[0x18]; 3952 3953 u8 packet_reformat_id[0x20]; 3954 3955 u8 modify_header_id[0x20]; 3956 3957 struct mlx5_ifc_vlan_bits push_vlan_2; 3958 3959 u8 encrypt_decrypt_obj_id[0x20]; 3960 u8 reserved_at_140[0xc0]; 3961 3962 struct mlx5_ifc_fte_match_param_bits match_value; 3963 3964 struct mlx5_ifc_execute_aso_bits execute_aso[4]; 3965 3966 u8 reserved_at_1300[0x500]; 3967 3968 union mlx5_ifc_dest_format_flow_counter_list_auto_bits destination[]; 3969 }; 3970 3971 enum { 3972 MLX5_XRC_SRQC_STATE_GOOD = 0x0, 3973 MLX5_XRC_SRQC_STATE_ERROR = 0x1, 3974 }; 3975 3976 struct mlx5_ifc_xrc_srqc_bits { 3977 u8 state[0x4]; 3978 u8 log_xrc_srq_size[0x4]; 3979 u8 reserved_at_8[0x18]; 3980 3981 u8 wq_signature[0x1]; 3982 u8 cont_srq[0x1]; 3983 u8 reserved_at_22[0x1]; 3984 u8 rlky[0x1]; 3985 u8 basic_cyclic_rcv_wqe[0x1]; 3986 u8 log_rq_stride[0x3]; 3987 u8 xrcd[0x18]; 3988 3989 u8 page_offset[0x6]; 3990 u8 reserved_at_46[0x1]; 3991 u8 dbr_umem_valid[0x1]; 3992 u8 cqn[0x18]; 3993 3994 u8 reserved_at_60[0x20]; 3995 3996 u8 user_index_equal_xrc_srqn[0x1]; 3997 u8 reserved_at_81[0x1]; 3998 u8 log_page_size[0x6]; 3999 u8 user_index[0x18]; 4000 4001 u8 reserved_at_a0[0x20]; 4002 4003 u8 reserved_at_c0[0x8]; 4004 u8 pd[0x18]; 4005 4006 u8 lwm[0x10]; 4007 u8 wqe_cnt[0x10]; 4008 4009 u8 reserved_at_100[0x40]; 4010 4011 u8 db_record_addr_h[0x20]; 4012 4013 u8 db_record_addr_l[0x1e]; 4014 u8 reserved_at_17e[0x2]; 4015 4016 u8 reserved_at_180[0x80]; 4017 }; 4018 4019 struct mlx5_ifc_vnic_diagnostic_statistics_bits { 4020 u8 counter_error_queues[0x20]; 4021 4022 u8 total_error_queues[0x20]; 4023 4024 u8 send_queue_priority_update_flow[0x20]; 4025 4026 u8 reserved_at_60[0x20]; 4027 4028 u8 nic_receive_steering_discard[0x40]; 4029 4030 u8 receive_discard_vport_down[0x40]; 4031 4032 u8 transmit_discard_vport_down[0x40]; 4033 4034 u8 async_eq_overrun[0x20]; 4035 4036 u8 comp_eq_overrun[0x20]; 4037 4038 u8 reserved_at_180[0x20]; 4039 4040 u8 invalid_command[0x20]; 4041 4042 u8 quota_exceeded_command[0x20]; 4043 4044 u8 internal_rq_out_of_buffer[0x20]; 4045 4046 u8 cq_overrun[0x20]; 4047 4048 u8 eth_wqe_too_small[0x20]; 4049 4050 u8 reserved_at_220[0xc0]; 4051 4052 u8 generated_pkt_steering_fail[0x40]; 4053 4054 u8 handled_pkt_steering_fail[0x40]; 4055 4056 u8 bar_uar_access[0x20]; 4057 4058 u8 odp_local_triggered_page_fault[0x20]; 4059 4060 u8 odp_remote_triggered_page_fault[0x20]; 4061 4062 u8 reserved_at_3c0[0xc20]; 4063 }; 4064 4065 struct mlx5_ifc_traffic_counter_bits { 4066 u8 packets[0x40]; 4067 4068 u8 octets[0x40]; 4069 }; 4070 4071 struct mlx5_ifc_tisc_bits { 4072 u8 strict_lag_tx_port_affinity[0x1]; 4073 u8 tls_en[0x1]; 4074 u8 reserved_at_2[0x2]; 4075 u8 lag_tx_port_affinity[0x04]; 4076 4077 u8 reserved_at_8[0x4]; 4078 u8 prio[0x4]; 4079 u8 reserved_at_10[0x10]; 4080 4081 u8 reserved_at_20[0x100]; 4082 4083 u8 reserved_at_120[0x8]; 4084 u8 transport_domain[0x18]; 4085 4086 u8 reserved_at_140[0x8]; 4087 u8 underlay_qpn[0x18]; 4088 4089 u8 reserved_at_160[0x8]; 4090 u8 pd[0x18]; 4091 4092 u8 reserved_at_180[0x380]; 4093 }; 4094 4095 enum { 4096 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0, 4097 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1, 4098 }; 4099 4100 enum { 4101 MLX5_TIRC_PACKET_MERGE_MASK_IPV4_LRO = BIT(0), 4102 MLX5_TIRC_PACKET_MERGE_MASK_IPV6_LRO = BIT(1), 4103 }; 4104 4105 enum { 4106 MLX5_RX_HASH_FN_NONE = 0x0, 4107 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1, 4108 MLX5_RX_HASH_FN_TOEPLITZ = 0x2, 4109 }; 4110 4111 enum { 4112 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST = 0x1, 4113 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST = 0x2, 4114 }; 4115 4116 struct mlx5_ifc_tirc_bits { 4117 u8 reserved_at_0[0x20]; 4118 4119 u8 disp_type[0x4]; 4120 u8 tls_en[0x1]; 4121 u8 reserved_at_25[0x1b]; 4122 4123 u8 reserved_at_40[0x40]; 4124 4125 u8 reserved_at_80[0x4]; 4126 u8 lro_timeout_period_usecs[0x10]; 4127 u8 packet_merge_mask[0x4]; 4128 u8 lro_max_ip_payload_size[0x8]; 4129 4130 u8 reserved_at_a0[0x40]; 4131 4132 u8 reserved_at_e0[0x8]; 4133 u8 inline_rqn[0x18]; 4134 4135 u8 rx_hash_symmetric[0x1]; 4136 u8 reserved_at_101[0x1]; 4137 u8 tunneled_offload_en[0x1]; 4138 u8 reserved_at_103[0x5]; 4139 u8 indirect_table[0x18]; 4140 4141 u8 rx_hash_fn[0x4]; 4142 u8 reserved_at_124[0x2]; 4143 u8 self_lb_block[0x2]; 4144 u8 transport_domain[0x18]; 4145 4146 u8 rx_hash_toeplitz_key[10][0x20]; 4147 4148 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer; 4149 4150 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner; 4151 4152 u8 reserved_at_2c0[0x4c0]; 4153 }; 4154 4155 enum { 4156 MLX5_SRQC_STATE_GOOD = 0x0, 4157 MLX5_SRQC_STATE_ERROR = 0x1, 4158 }; 4159 4160 struct mlx5_ifc_srqc_bits { 4161 u8 state[0x4]; 4162 u8 log_srq_size[0x4]; 4163 u8 reserved_at_8[0x18]; 4164 4165 u8 wq_signature[0x1]; 4166 u8 cont_srq[0x1]; 4167 u8 reserved_at_22[0x1]; 4168 u8 rlky[0x1]; 4169 u8 reserved_at_24[0x1]; 4170 u8 log_rq_stride[0x3]; 4171 u8 xrcd[0x18]; 4172 4173 u8 page_offset[0x6]; 4174 u8 reserved_at_46[0x2]; 4175 u8 cqn[0x18]; 4176 4177 u8 reserved_at_60[0x20]; 4178 4179 u8 reserved_at_80[0x2]; 4180 u8 log_page_size[0x6]; 4181 u8 reserved_at_88[0x18]; 4182 4183 u8 reserved_at_a0[0x20]; 4184 4185 u8 reserved_at_c0[0x8]; 4186 u8 pd[0x18]; 4187 4188 u8 lwm[0x10]; 4189 u8 wqe_cnt[0x10]; 4190 4191 u8 reserved_at_100[0x40]; 4192 4193 u8 dbr_addr[0x40]; 4194 4195 u8 reserved_at_180[0x80]; 4196 }; 4197 4198 enum { 4199 MLX5_SQC_STATE_RST = 0x0, 4200 MLX5_SQC_STATE_RDY = 0x1, 4201 MLX5_SQC_STATE_ERR = 0x3, 4202 }; 4203 4204 struct mlx5_ifc_sqc_bits { 4205 u8 rlky[0x1]; 4206 u8 cd_master[0x1]; 4207 u8 fre[0x1]; 4208 u8 flush_in_error_en[0x1]; 4209 u8 allow_multi_pkt_send_wqe[0x1]; 4210 u8 min_wqe_inline_mode[0x3]; 4211 u8 state[0x4]; 4212 u8 reg_umr[0x1]; 4213 u8 allow_swp[0x1]; 4214 u8 hairpin[0x1]; 4215 u8 non_wire[0x1]; 4216 u8 reserved_at_10[0xa]; 4217 u8 ts_format[0x2]; 4218 u8 reserved_at_1c[0x4]; 4219 4220 u8 reserved_at_20[0x8]; 4221 u8 user_index[0x18]; 4222 4223 u8 reserved_at_40[0x8]; 4224 u8 cqn[0x18]; 4225 4226 u8 reserved_at_60[0x8]; 4227 u8 hairpin_peer_rq[0x18]; 4228 4229 u8 reserved_at_80[0x10]; 4230 u8 hairpin_peer_vhca[0x10]; 4231 4232 u8 reserved_at_a0[0x20]; 4233 4234 u8 reserved_at_c0[0x8]; 4235 u8 ts_cqe_to_dest_cqn[0x18]; 4236 4237 u8 reserved_at_e0[0x10]; 4238 u8 packet_pacing_rate_limit_index[0x10]; 4239 u8 tis_lst_sz[0x10]; 4240 u8 qos_queue_group_id[0x10]; 4241 4242 u8 reserved_at_120[0x40]; 4243 4244 u8 reserved_at_160[0x8]; 4245 u8 tis_num_0[0x18]; 4246 4247 struct mlx5_ifc_wq_bits wq; 4248 }; 4249 4250 enum { 4251 SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0, 4252 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1, 4253 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2, 4254 SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3, 4255 SCHEDULING_CONTEXT_ELEMENT_TYPE_QUEUE_GROUP = 0x4, 4256 SCHEDULING_CONTEXT_ELEMENT_TYPE_RATE_LIMIT = 0x5, 4257 }; 4258 4259 enum { 4260 ELEMENT_TYPE_CAP_MASK_TSAR = 1 << 0, 4261 ELEMENT_TYPE_CAP_MASK_VPORT = 1 << 1, 4262 ELEMENT_TYPE_CAP_MASK_VPORT_TC = 1 << 2, 4263 ELEMENT_TYPE_CAP_MASK_PARA_VPORT_TC = 1 << 3, 4264 ELEMENT_TYPE_CAP_MASK_QUEUE_GROUP = 1 << 4, 4265 ELEMENT_TYPE_CAP_MASK_RATE_LIMIT = 1 << 5, 4266 }; 4267 4268 enum { 4269 TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0, 4270 TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1, 4271 TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2, 4272 TSAR_ELEMENT_TSAR_TYPE_TC_ARB = 0x3, 4273 }; 4274 4275 enum { 4276 TSAR_TYPE_CAP_MASK_DWRR = 1 << 0, 4277 TSAR_TYPE_CAP_MASK_ROUND_ROBIN = 1 << 1, 4278 TSAR_TYPE_CAP_MASK_ETS = 1 << 2, 4279 TSAR_TYPE_CAP_MASK_TC_ARB = 1 << 3, 4280 }; 4281 4282 struct mlx5_ifc_tsar_element_bits { 4283 u8 traffic_class[0x4]; 4284 u8 reserved_at_4[0x4]; 4285 u8 tsar_type[0x8]; 4286 u8 reserved_at_10[0x10]; 4287 }; 4288 4289 struct mlx5_ifc_vport_element_bits { 4290 u8 reserved_at_0[0x4]; 4291 u8 eswitch_owner_vhca_id_valid[0x1]; 4292 u8 eswitch_owner_vhca_id[0xb]; 4293 u8 vport_number[0x10]; 4294 }; 4295 4296 struct mlx5_ifc_vport_tc_element_bits { 4297 u8 traffic_class[0x4]; 4298 u8 eswitch_owner_vhca_id_valid[0x1]; 4299 u8 eswitch_owner_vhca_id[0xb]; 4300 u8 vport_number[0x10]; 4301 }; 4302 4303 union mlx5_ifc_element_attributes_bits { 4304 struct mlx5_ifc_tsar_element_bits tsar; 4305 struct mlx5_ifc_vport_element_bits vport; 4306 struct mlx5_ifc_vport_tc_element_bits vport_tc; 4307 u8 reserved_at_0[0x20]; 4308 }; 4309 4310 struct mlx5_ifc_scheduling_context_bits { 4311 u8 element_type[0x8]; 4312 u8 reserved_at_8[0x18]; 4313 4314 union mlx5_ifc_element_attributes_bits element_attributes; 4315 4316 u8 parent_element_id[0x20]; 4317 4318 u8 reserved_at_60[0x40]; 4319 4320 u8 bw_share[0x20]; 4321 4322 u8 max_average_bw[0x20]; 4323 4324 u8 max_bw_obj_id[0x20]; 4325 4326 u8 reserved_at_100[0x100]; 4327 }; 4328 4329 struct mlx5_ifc_rqtc_bits { 4330 u8 reserved_at_0[0xa0]; 4331 4332 u8 reserved_at_a0[0x5]; 4333 u8 list_q_type[0x3]; 4334 u8 reserved_at_a8[0x8]; 4335 u8 rqt_max_size[0x10]; 4336 4337 u8 rq_vhca_id_format[0x1]; 4338 u8 reserved_at_c1[0xf]; 4339 u8 rqt_actual_size[0x10]; 4340 4341 u8 reserved_at_e0[0x6a0]; 4342 4343 union { 4344 DECLARE_FLEX_ARRAY(struct mlx5_ifc_rq_num_bits, rq_num); 4345 DECLARE_FLEX_ARRAY(struct mlx5_ifc_rq_vhca_bits, rq_vhca); 4346 }; 4347 }; 4348 4349 enum { 4350 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0, 4351 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1, 4352 }; 4353 4354 enum { 4355 MLX5_RQC_STATE_RST = 0x0, 4356 MLX5_RQC_STATE_RDY = 0x1, 4357 MLX5_RQC_STATE_ERR = 0x3, 4358 }; 4359 4360 enum { 4361 MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_BYTE = 0x0, 4362 MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_STRIDE = 0x1, 4363 MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_PAGE = 0x2, 4364 }; 4365 4366 enum { 4367 MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_NO_MATCH = 0x0, 4368 MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_EXTENDED = 0x1, 4369 MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_FIVE_TUPLE = 0x2, 4370 }; 4371 4372 struct mlx5_ifc_rqc_bits { 4373 u8 rlky[0x1]; 4374 u8 delay_drop_en[0x1]; 4375 u8 scatter_fcs[0x1]; 4376 u8 vsd[0x1]; 4377 u8 mem_rq_type[0x4]; 4378 u8 state[0x4]; 4379 u8 reserved_at_c[0x1]; 4380 u8 flush_in_error_en[0x1]; 4381 u8 hairpin[0x1]; 4382 u8 reserved_at_f[0xb]; 4383 u8 ts_format[0x2]; 4384 u8 reserved_at_1c[0x4]; 4385 4386 u8 reserved_at_20[0x8]; 4387 u8 user_index[0x18]; 4388 4389 u8 reserved_at_40[0x8]; 4390 u8 cqn[0x18]; 4391 4392 u8 counter_set_id[0x8]; 4393 u8 reserved_at_68[0x18]; 4394 4395 u8 reserved_at_80[0x8]; 4396 u8 rmpn[0x18]; 4397 4398 u8 reserved_at_a0[0x8]; 4399 u8 hairpin_peer_sq[0x18]; 4400 4401 u8 reserved_at_c0[0x10]; 4402 u8 hairpin_peer_vhca[0x10]; 4403 4404 u8 reserved_at_e0[0x46]; 4405 u8 shampo_no_match_alignment_granularity[0x2]; 4406 u8 reserved_at_128[0x6]; 4407 u8 shampo_match_criteria_type[0x2]; 4408 u8 reservation_timeout[0x10]; 4409 4410 u8 reserved_at_140[0x40]; 4411 4412 struct mlx5_ifc_wq_bits wq; 4413 }; 4414 4415 enum { 4416 MLX5_RMPC_STATE_RDY = 0x1, 4417 MLX5_RMPC_STATE_ERR = 0x3, 4418 }; 4419 4420 struct mlx5_ifc_rmpc_bits { 4421 u8 reserved_at_0[0x8]; 4422 u8 state[0x4]; 4423 u8 reserved_at_c[0x14]; 4424 4425 u8 basic_cyclic_rcv_wqe[0x1]; 4426 u8 reserved_at_21[0x1f]; 4427 4428 u8 reserved_at_40[0x140]; 4429 4430 struct mlx5_ifc_wq_bits wq; 4431 }; 4432 4433 enum { 4434 VHCA_ID_TYPE_HW = 0, 4435 VHCA_ID_TYPE_SW = 1, 4436 }; 4437 4438 struct mlx5_ifc_nic_vport_context_bits { 4439 u8 reserved_at_0[0x5]; 4440 u8 min_wqe_inline_mode[0x3]; 4441 u8 reserved_at_8[0x15]; 4442 u8 disable_mc_local_lb[0x1]; 4443 u8 disable_uc_local_lb[0x1]; 4444 u8 roce_en[0x1]; 4445 4446 u8 arm_change_event[0x1]; 4447 u8 reserved_at_21[0x1a]; 4448 u8 event_on_mtu[0x1]; 4449 u8 event_on_promisc_change[0x1]; 4450 u8 event_on_vlan_change[0x1]; 4451 u8 event_on_mc_address_change[0x1]; 4452 u8 event_on_uc_address_change[0x1]; 4453 4454 u8 vhca_id_type[0x1]; 4455 u8 reserved_at_41[0xb]; 4456 u8 affiliation_criteria[0x4]; 4457 u8 affiliated_vhca_id[0x10]; 4458 4459 u8 reserved_at_60[0xa0]; 4460 4461 u8 reserved_at_100[0x1]; 4462 u8 sd_group[0x3]; 4463 u8 reserved_at_104[0x1c]; 4464 4465 u8 reserved_at_120[0x10]; 4466 u8 mtu[0x10]; 4467 4468 u8 system_image_guid[0x40]; 4469 u8 port_guid[0x40]; 4470 u8 node_guid[0x40]; 4471 4472 u8 reserved_at_200[0x140]; 4473 u8 qkey_violation_counter[0x10]; 4474 u8 reserved_at_350[0x430]; 4475 4476 u8 promisc_uc[0x1]; 4477 u8 promisc_mc[0x1]; 4478 u8 promisc_all[0x1]; 4479 u8 reserved_at_783[0x2]; 4480 u8 allowed_list_type[0x3]; 4481 u8 reserved_at_788[0xc]; 4482 u8 allowed_list_size[0xc]; 4483 4484 struct mlx5_ifc_mac_address_layout_bits permanent_address; 4485 4486 u8 reserved_at_7e0[0x20]; 4487 4488 u8 current_uc_mac_address[][0x40]; 4489 }; 4490 4491 enum { 4492 MLX5_MKC_ACCESS_MODE_PA = 0x0, 4493 MLX5_MKC_ACCESS_MODE_MTT = 0x1, 4494 MLX5_MKC_ACCESS_MODE_KLMS = 0x2, 4495 MLX5_MKC_ACCESS_MODE_KSM = 0x3, 4496 MLX5_MKC_ACCESS_MODE_SW_ICM = 0x4, 4497 MLX5_MKC_ACCESS_MODE_MEMIC = 0x5, 4498 MLX5_MKC_ACCESS_MODE_CROSSING = 0x6, 4499 }; 4500 4501 enum { 4502 MLX5_MKC_PCIE_TPH_NO_STEERING_TAG_INDEX = 0, 4503 }; 4504 4505 struct mlx5_ifc_mkc_bits { 4506 u8 reserved_at_0[0x1]; 4507 u8 free[0x1]; 4508 u8 reserved_at_2[0x1]; 4509 u8 access_mode_4_2[0x3]; 4510 u8 reserved_at_6[0x7]; 4511 u8 relaxed_ordering_write[0x1]; 4512 u8 reserved_at_e[0x1]; 4513 u8 small_fence_on_rdma_read_response[0x1]; 4514 u8 umr_en[0x1]; 4515 u8 a[0x1]; 4516 u8 rw[0x1]; 4517 u8 rr[0x1]; 4518 u8 lw[0x1]; 4519 u8 lr[0x1]; 4520 u8 access_mode_1_0[0x2]; 4521 u8 reserved_at_18[0x2]; 4522 u8 ma_translation_mode[0x2]; 4523 u8 reserved_at_1c[0x4]; 4524 4525 u8 qpn[0x18]; 4526 u8 mkey_7_0[0x8]; 4527 4528 u8 reserved_at_40[0x20]; 4529 4530 u8 length64[0x1]; 4531 u8 bsf_en[0x1]; 4532 u8 sync_umr[0x1]; 4533 u8 reserved_at_63[0x2]; 4534 u8 expected_sigerr_count[0x1]; 4535 u8 reserved_at_66[0x1]; 4536 u8 en_rinval[0x1]; 4537 u8 pd[0x18]; 4538 4539 u8 start_addr[0x40]; 4540 4541 u8 len[0x40]; 4542 4543 u8 bsf_octword_size[0x20]; 4544 4545 u8 reserved_at_120[0x60]; 4546 4547 u8 crossing_target_vhca_id[0x10]; 4548 u8 reserved_at_190[0x10]; 4549 4550 u8 translations_octword_size[0x20]; 4551 4552 u8 reserved_at_1c0[0x19]; 4553 u8 relaxed_ordering_read[0x1]; 4554 u8 log_page_size[0x6]; 4555 4556 u8 reserved_at_1e0[0x5]; 4557 u8 pcie_tph_en[0x1]; 4558 u8 pcie_tph_ph[0x2]; 4559 u8 pcie_tph_steering_tag_index[0x8]; 4560 u8 reserved_at_1f0[0x10]; 4561 }; 4562 4563 struct mlx5_ifc_pkey_bits { 4564 u8 reserved_at_0[0x10]; 4565 u8 pkey[0x10]; 4566 }; 4567 4568 struct mlx5_ifc_array128_auto_bits { 4569 u8 array128_auto[16][0x8]; 4570 }; 4571 4572 struct mlx5_ifc_hca_vport_context_bits { 4573 u8 field_select[0x20]; 4574 4575 u8 reserved_at_20[0xe0]; 4576 4577 u8 sm_virt_aware[0x1]; 4578 u8 has_smi[0x1]; 4579 u8 has_raw[0x1]; 4580 u8 grh_required[0x1]; 4581 u8 reserved_at_104[0x4]; 4582 u8 num_port_plane[0x8]; 4583 u8 port_physical_state[0x4]; 4584 u8 vport_state_policy[0x4]; 4585 u8 port_state[0x4]; 4586 u8 vport_state[0x4]; 4587 4588 u8 reserved_at_120[0x20]; 4589 4590 u8 system_image_guid[0x40]; 4591 4592 u8 port_guid[0x40]; 4593 4594 u8 node_guid[0x40]; 4595 4596 u8 cap_mask1[0x20]; 4597 4598 u8 cap_mask1_field_select[0x20]; 4599 4600 u8 cap_mask2[0x20]; 4601 4602 u8 cap_mask2_field_select[0x20]; 4603 4604 u8 reserved_at_280[0x80]; 4605 4606 u8 lid[0x10]; 4607 u8 reserved_at_310[0x4]; 4608 u8 init_type_reply[0x4]; 4609 u8 lmc[0x3]; 4610 u8 subnet_timeout[0x5]; 4611 4612 u8 sm_lid[0x10]; 4613 u8 sm_sl[0x4]; 4614 u8 reserved_at_334[0xc]; 4615 4616 u8 qkey_violation_counter[0x10]; 4617 u8 pkey_violation_counter[0x10]; 4618 4619 u8 reserved_at_360[0xca0]; 4620 }; 4621 4622 struct mlx5_ifc_esw_vport_context_bits { 4623 u8 fdb_to_vport_reg_c[0x1]; 4624 u8 reserved_at_1[0x2]; 4625 u8 vport_svlan_strip[0x1]; 4626 u8 vport_cvlan_strip[0x1]; 4627 u8 vport_svlan_insert[0x1]; 4628 u8 vport_cvlan_insert[0x2]; 4629 u8 fdb_to_vport_reg_c_id[0x8]; 4630 u8 reserved_at_10[0x10]; 4631 4632 u8 reserved_at_20[0x20]; 4633 4634 u8 svlan_cfi[0x1]; 4635 u8 svlan_pcp[0x3]; 4636 u8 svlan_id[0xc]; 4637 u8 cvlan_cfi[0x1]; 4638 u8 cvlan_pcp[0x3]; 4639 u8 cvlan_id[0xc]; 4640 4641 u8 reserved_at_60[0x720]; 4642 4643 u8 sw_steering_vport_icm_address_rx[0x40]; 4644 4645 u8 sw_steering_vport_icm_address_tx[0x40]; 4646 }; 4647 4648 enum { 4649 MLX5_EQC_STATUS_OK = 0x0, 4650 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa, 4651 }; 4652 4653 enum { 4654 MLX5_EQC_ST_ARMED = 0x9, 4655 MLX5_EQC_ST_FIRED = 0xa, 4656 }; 4657 4658 struct mlx5_ifc_eqc_bits { 4659 u8 status[0x4]; 4660 u8 reserved_at_4[0x9]; 4661 u8 ec[0x1]; 4662 u8 oi[0x1]; 4663 u8 reserved_at_f[0x5]; 4664 u8 st[0x4]; 4665 u8 reserved_at_18[0x8]; 4666 4667 u8 reserved_at_20[0x20]; 4668 4669 u8 reserved_at_40[0x14]; 4670 u8 page_offset[0x6]; 4671 u8 reserved_at_5a[0x6]; 4672 4673 u8 reserved_at_60[0x3]; 4674 u8 log_eq_size[0x5]; 4675 u8 uar_page[0x18]; 4676 4677 u8 reserved_at_80[0x20]; 4678 4679 u8 reserved_at_a0[0x14]; 4680 u8 intr[0xc]; 4681 4682 u8 reserved_at_c0[0x3]; 4683 u8 log_page_size[0x5]; 4684 u8 reserved_at_c8[0x18]; 4685 4686 u8 reserved_at_e0[0x60]; 4687 4688 u8 reserved_at_140[0x8]; 4689 u8 consumer_counter[0x18]; 4690 4691 u8 reserved_at_160[0x8]; 4692 u8 producer_counter[0x18]; 4693 4694 u8 reserved_at_180[0x80]; 4695 }; 4696 4697 enum { 4698 MLX5_DCTC_STATE_ACTIVE = 0x0, 4699 MLX5_DCTC_STATE_DRAINING = 0x1, 4700 MLX5_DCTC_STATE_DRAINED = 0x2, 4701 }; 4702 4703 enum { 4704 MLX5_DCTC_CS_RES_DISABLE = 0x0, 4705 MLX5_DCTC_CS_RES_NA = 0x1, 4706 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2, 4707 }; 4708 4709 enum { 4710 MLX5_DCTC_MTU_256_BYTES = 0x1, 4711 MLX5_DCTC_MTU_512_BYTES = 0x2, 4712 MLX5_DCTC_MTU_1K_BYTES = 0x3, 4713 MLX5_DCTC_MTU_2K_BYTES = 0x4, 4714 MLX5_DCTC_MTU_4K_BYTES = 0x5, 4715 }; 4716 4717 struct mlx5_ifc_dctc_bits { 4718 u8 reserved_at_0[0x4]; 4719 u8 state[0x4]; 4720 u8 reserved_at_8[0x18]; 4721 4722 u8 reserved_at_20[0x7]; 4723 u8 dp_ordering_force[0x1]; 4724 u8 user_index[0x18]; 4725 4726 u8 reserved_at_40[0x8]; 4727 u8 cqn[0x18]; 4728 4729 u8 counter_set_id[0x8]; 4730 u8 atomic_mode[0x4]; 4731 u8 rre[0x1]; 4732 u8 rwe[0x1]; 4733 u8 rae[0x1]; 4734 u8 atomic_like_write_en[0x1]; 4735 u8 latency_sensitive[0x1]; 4736 u8 rlky[0x1]; 4737 u8 free_ar[0x1]; 4738 u8 reserved_at_73[0x1]; 4739 u8 dp_ordering_1[0x1]; 4740 u8 reserved_at_75[0xb]; 4741 4742 u8 reserved_at_80[0x8]; 4743 u8 cs_res[0x8]; 4744 u8 reserved_at_90[0x3]; 4745 u8 min_rnr_nak[0x5]; 4746 u8 reserved_at_98[0x8]; 4747 4748 u8 reserved_at_a0[0x8]; 4749 u8 srqn_xrqn[0x18]; 4750 4751 u8 reserved_at_c0[0x8]; 4752 u8 pd[0x18]; 4753 4754 u8 tclass[0x8]; 4755 u8 reserved_at_e8[0x4]; 4756 u8 flow_label[0x14]; 4757 4758 u8 dc_access_key[0x40]; 4759 4760 u8 reserved_at_140[0x5]; 4761 u8 mtu[0x3]; 4762 u8 port[0x8]; 4763 u8 pkey_index[0x10]; 4764 4765 u8 reserved_at_160[0x8]; 4766 u8 my_addr_index[0x8]; 4767 u8 reserved_at_170[0x8]; 4768 u8 hop_limit[0x8]; 4769 4770 u8 dc_access_key_violation_count[0x20]; 4771 4772 u8 reserved_at_1a0[0x14]; 4773 u8 dei_cfi[0x1]; 4774 u8 eth_prio[0x3]; 4775 u8 ecn[0x2]; 4776 u8 dscp[0x6]; 4777 4778 u8 reserved_at_1c0[0x20]; 4779 u8 ece[0x20]; 4780 }; 4781 4782 enum { 4783 MLX5_CQC_STATUS_OK = 0x0, 4784 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9, 4785 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa, 4786 }; 4787 4788 enum { 4789 MLX5_CQC_CQE_SZ_64_BYTES = 0x0, 4790 MLX5_CQC_CQE_SZ_128_BYTES = 0x1, 4791 }; 4792 4793 enum { 4794 MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED = 0x6, 4795 MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED = 0x9, 4796 MLX5_CQC_ST_FIRED = 0xa, 4797 }; 4798 4799 enum mlx5_cq_period_mode { 4800 MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0, 4801 MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1, 4802 MLX5_CQ_PERIOD_NUM_MODES, 4803 }; 4804 4805 struct mlx5_ifc_cqc_bits { 4806 u8 status[0x4]; 4807 u8 reserved_at_4[0x2]; 4808 u8 dbr_umem_valid[0x1]; 4809 u8 apu_cq[0x1]; 4810 u8 cqe_sz[0x3]; 4811 u8 cc[0x1]; 4812 u8 reserved_at_c[0x1]; 4813 u8 scqe_break_moderation_en[0x1]; 4814 u8 oi[0x1]; 4815 u8 cq_period_mode[0x2]; 4816 u8 cqe_comp_en[0x1]; 4817 u8 mini_cqe_res_format[0x2]; 4818 u8 st[0x4]; 4819 u8 reserved_at_18[0x6]; 4820 u8 cqe_compression_layout[0x2]; 4821 4822 u8 reserved_at_20[0x20]; 4823 4824 u8 reserved_at_40[0x14]; 4825 u8 page_offset[0x6]; 4826 u8 reserved_at_5a[0x6]; 4827 4828 u8 reserved_at_60[0x3]; 4829 u8 log_cq_size[0x5]; 4830 u8 uar_page[0x18]; 4831 4832 u8 reserved_at_80[0x4]; 4833 u8 cq_period[0xc]; 4834 u8 cq_max_count[0x10]; 4835 4836 u8 c_eqn_or_apu_element[0x20]; 4837 4838 u8 reserved_at_c0[0x3]; 4839 u8 log_page_size[0x5]; 4840 u8 reserved_at_c8[0x18]; 4841 4842 u8 reserved_at_e0[0x20]; 4843 4844 u8 reserved_at_100[0x8]; 4845 u8 last_notified_index[0x18]; 4846 4847 u8 reserved_at_120[0x8]; 4848 u8 last_solicit_index[0x18]; 4849 4850 u8 reserved_at_140[0x8]; 4851 u8 consumer_counter[0x18]; 4852 4853 u8 reserved_at_160[0x8]; 4854 u8 producer_counter[0x18]; 4855 4856 u8 reserved_at_180[0x40]; 4857 4858 u8 dbr_addr[0x40]; 4859 }; 4860 4861 union mlx5_ifc_cong_control_roce_ecn_auto_bits { 4862 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp; 4863 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp; 4864 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np; 4865 struct mlx5_ifc_cong_control_r_roce_general_bits cong_control_r_roce_general; 4866 u8 reserved_at_0[0x800]; 4867 }; 4868 4869 struct mlx5_ifc_query_adapter_param_block_bits { 4870 u8 reserved_at_0[0xc0]; 4871 4872 u8 reserved_at_c0[0x8]; 4873 u8 ieee_vendor_id[0x18]; 4874 4875 u8 reserved_at_e0[0x10]; 4876 u8 vsd_vendor_id[0x10]; 4877 4878 u8 vsd[208][0x8]; 4879 4880 u8 vsd_contd_psid[16][0x8]; 4881 }; 4882 4883 enum { 4884 MLX5_XRQC_STATE_GOOD = 0x0, 4885 MLX5_XRQC_STATE_ERROR = 0x1, 4886 }; 4887 4888 enum { 4889 MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0, 4890 MLX5_XRQC_TOPOLOGY_TAG_MATCHING = 0x1, 4891 }; 4892 4893 enum { 4894 MLX5_XRQC_OFFLOAD_RNDV = 0x1, 4895 }; 4896 4897 struct mlx5_ifc_tag_matching_topology_context_bits { 4898 u8 log_matching_list_sz[0x4]; 4899 u8 reserved_at_4[0xc]; 4900 u8 append_next_index[0x10]; 4901 4902 u8 sw_phase_cnt[0x10]; 4903 u8 hw_phase_cnt[0x10]; 4904 4905 u8 reserved_at_40[0x40]; 4906 }; 4907 4908 struct mlx5_ifc_xrqc_bits { 4909 u8 state[0x4]; 4910 u8 rlkey[0x1]; 4911 u8 reserved_at_5[0xf]; 4912 u8 topology[0x4]; 4913 u8 reserved_at_18[0x4]; 4914 u8 offload[0x4]; 4915 4916 u8 reserved_at_20[0x8]; 4917 u8 user_index[0x18]; 4918 4919 u8 reserved_at_40[0x8]; 4920 u8 cqn[0x18]; 4921 4922 u8 reserved_at_60[0xa0]; 4923 4924 struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context; 4925 4926 u8 reserved_at_180[0x280]; 4927 4928 struct mlx5_ifc_wq_bits wq; 4929 }; 4930 4931 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits { 4932 struct mlx5_ifc_modify_field_select_bits modify_field_select; 4933 struct mlx5_ifc_resize_field_select_bits resize_field_select; 4934 u8 reserved_at_0[0x20]; 4935 }; 4936 4937 union mlx5_ifc_field_select_802_1_r_roce_auto_bits { 4938 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp; 4939 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp; 4940 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np; 4941 u8 reserved_at_0[0x20]; 4942 }; 4943 4944 struct mlx5_ifc_rs_histogram_cntrs_bits { 4945 u8 hist[16][0x40]; 4946 u8 reserved_at_400[0x2c0]; 4947 }; 4948 4949 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits { 4950 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 4951 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 4952 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 4953 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 4954 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 4955 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 4956 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout; 4957 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout; 4958 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 4959 struct mlx5_ifc_ib_ext_port_cntrs_grp_data_layout_bits ib_ext_port_cntrs_grp_data_layout; 4960 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 4961 struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs; 4962 struct mlx5_ifc_phys_layer_recovery_cntrs_bits phys_layer_recovery_cntrs; 4963 struct mlx5_ifc_rs_histogram_cntrs_bits rs_histogram_cntrs; 4964 u8 reserved_at_0[0x7c0]; 4965 }; 4966 4967 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits { 4968 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout; 4969 u8 reserved_at_0[0x7c0]; 4970 }; 4971 4972 union mlx5_ifc_event_auto_bits { 4973 struct mlx5_ifc_comp_event_bits comp_event; 4974 struct mlx5_ifc_dct_events_bits dct_events; 4975 struct mlx5_ifc_qp_events_bits qp_events; 4976 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event; 4977 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event; 4978 struct mlx5_ifc_cq_error_bits cq_error; 4979 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged; 4980 struct mlx5_ifc_port_state_change_event_bits port_state_change_event; 4981 struct mlx5_ifc_gpio_event_bits gpio_event; 4982 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event; 4983 struct mlx5_ifc_stall_vl_event_bits stall_vl_event; 4984 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event; 4985 u8 reserved_at_0[0xe0]; 4986 }; 4987 4988 struct mlx5_ifc_health_buffer_bits { 4989 u8 reserved_at_0[0x100]; 4990 4991 u8 assert_existptr[0x20]; 4992 4993 u8 assert_callra[0x20]; 4994 4995 u8 reserved_at_140[0x20]; 4996 4997 u8 time[0x20]; 4998 4999 u8 fw_version[0x20]; 5000 5001 u8 hw_id[0x20]; 5002 5003 u8 rfr[0x1]; 5004 u8 reserved_at_1c1[0x3]; 5005 u8 valid[0x1]; 5006 u8 severity[0x3]; 5007 u8 reserved_at_1c8[0x18]; 5008 5009 u8 irisc_index[0x8]; 5010 u8 synd[0x8]; 5011 u8 ext_synd[0x10]; 5012 }; 5013 5014 struct mlx5_ifc_register_loopback_control_bits { 5015 u8 no_lb[0x1]; 5016 u8 reserved_at_1[0x7]; 5017 u8 port[0x8]; 5018 u8 reserved_at_10[0x10]; 5019 5020 u8 reserved_at_20[0x60]; 5021 }; 5022 5023 enum { 5024 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0, 5025 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1, 5026 }; 5027 5028 struct mlx5_ifc_teardown_hca_out_bits { 5029 u8 status[0x8]; 5030 u8 reserved_at_8[0x18]; 5031 5032 u8 syndrome[0x20]; 5033 5034 u8 reserved_at_40[0x3f]; 5035 5036 u8 state[0x1]; 5037 }; 5038 5039 enum { 5040 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0, 5041 MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE = 0x1, 5042 MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN = 0x2, 5043 }; 5044 5045 struct mlx5_ifc_teardown_hca_in_bits { 5046 u8 opcode[0x10]; 5047 u8 reserved_at_10[0x10]; 5048 5049 u8 reserved_at_20[0x10]; 5050 u8 op_mod[0x10]; 5051 5052 u8 reserved_at_40[0x10]; 5053 u8 profile[0x10]; 5054 5055 u8 reserved_at_60[0x20]; 5056 }; 5057 5058 struct mlx5_ifc_sqerr2rts_qp_out_bits { 5059 u8 status[0x8]; 5060 u8 reserved_at_8[0x18]; 5061 5062 u8 syndrome[0x20]; 5063 5064 u8 reserved_at_40[0x40]; 5065 }; 5066 5067 struct mlx5_ifc_sqerr2rts_qp_in_bits { 5068 u8 opcode[0x10]; 5069 u8 uid[0x10]; 5070 5071 u8 reserved_at_20[0x10]; 5072 u8 op_mod[0x10]; 5073 5074 u8 reserved_at_40[0x8]; 5075 u8 qpn[0x18]; 5076 5077 u8 reserved_at_60[0x20]; 5078 5079 u8 opt_param_mask[0x20]; 5080 5081 u8 reserved_at_a0[0x20]; 5082 5083 struct mlx5_ifc_qpc_bits qpc; 5084 5085 u8 reserved_at_800[0x80]; 5086 }; 5087 5088 struct mlx5_ifc_sqd2rts_qp_out_bits { 5089 u8 status[0x8]; 5090 u8 reserved_at_8[0x18]; 5091 5092 u8 syndrome[0x20]; 5093 5094 u8 reserved_at_40[0x40]; 5095 }; 5096 5097 struct mlx5_ifc_sqd2rts_qp_in_bits { 5098 u8 opcode[0x10]; 5099 u8 uid[0x10]; 5100 5101 u8 reserved_at_20[0x10]; 5102 u8 op_mod[0x10]; 5103 5104 u8 reserved_at_40[0x8]; 5105 u8 qpn[0x18]; 5106 5107 u8 reserved_at_60[0x20]; 5108 5109 u8 opt_param_mask[0x20]; 5110 5111 u8 reserved_at_a0[0x20]; 5112 5113 struct mlx5_ifc_qpc_bits qpc; 5114 5115 u8 reserved_at_800[0x80]; 5116 }; 5117 5118 struct mlx5_ifc_set_roce_address_out_bits { 5119 u8 status[0x8]; 5120 u8 reserved_at_8[0x18]; 5121 5122 u8 syndrome[0x20]; 5123 5124 u8 reserved_at_40[0x40]; 5125 }; 5126 5127 struct mlx5_ifc_set_roce_address_in_bits { 5128 u8 opcode[0x10]; 5129 u8 reserved_at_10[0x10]; 5130 5131 u8 reserved_at_20[0x10]; 5132 u8 op_mod[0x10]; 5133 5134 u8 roce_address_index[0x10]; 5135 u8 reserved_at_50[0xc]; 5136 u8 vhca_port_num[0x4]; 5137 5138 u8 reserved_at_60[0x20]; 5139 5140 struct mlx5_ifc_roce_addr_layout_bits roce_address; 5141 }; 5142 5143 struct mlx5_ifc_set_mad_demux_out_bits { 5144 u8 status[0x8]; 5145 u8 reserved_at_8[0x18]; 5146 5147 u8 syndrome[0x20]; 5148 5149 u8 reserved_at_40[0x40]; 5150 }; 5151 5152 enum { 5153 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0, 5154 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2, 5155 }; 5156 5157 struct mlx5_ifc_set_mad_demux_in_bits { 5158 u8 opcode[0x10]; 5159 u8 reserved_at_10[0x10]; 5160 5161 u8 reserved_at_20[0x10]; 5162 u8 op_mod[0x10]; 5163 5164 u8 reserved_at_40[0x20]; 5165 5166 u8 reserved_at_60[0x6]; 5167 u8 demux_mode[0x2]; 5168 u8 reserved_at_68[0x18]; 5169 }; 5170 5171 struct mlx5_ifc_set_l2_table_entry_out_bits { 5172 u8 status[0x8]; 5173 u8 reserved_at_8[0x18]; 5174 5175 u8 syndrome[0x20]; 5176 5177 u8 reserved_at_40[0x40]; 5178 }; 5179 5180 struct mlx5_ifc_set_l2_table_entry_in_bits { 5181 u8 opcode[0x10]; 5182 u8 reserved_at_10[0x10]; 5183 5184 u8 reserved_at_20[0x10]; 5185 u8 op_mod[0x10]; 5186 5187 u8 reserved_at_40[0x60]; 5188 5189 u8 reserved_at_a0[0x8]; 5190 u8 table_index[0x18]; 5191 5192 u8 reserved_at_c0[0x20]; 5193 5194 u8 reserved_at_e0[0x10]; 5195 u8 silent_mode_valid[0x1]; 5196 u8 silent_mode[0x1]; 5197 u8 reserved_at_f2[0x1]; 5198 u8 vlan_valid[0x1]; 5199 u8 vlan[0xc]; 5200 5201 struct mlx5_ifc_mac_address_layout_bits mac_address; 5202 5203 u8 reserved_at_140[0xc0]; 5204 }; 5205 5206 struct mlx5_ifc_set_issi_out_bits { 5207 u8 status[0x8]; 5208 u8 reserved_at_8[0x18]; 5209 5210 u8 syndrome[0x20]; 5211 5212 u8 reserved_at_40[0x40]; 5213 }; 5214 5215 struct mlx5_ifc_set_issi_in_bits { 5216 u8 opcode[0x10]; 5217 u8 reserved_at_10[0x10]; 5218 5219 u8 reserved_at_20[0x10]; 5220 u8 op_mod[0x10]; 5221 5222 u8 reserved_at_40[0x10]; 5223 u8 current_issi[0x10]; 5224 5225 u8 reserved_at_60[0x20]; 5226 }; 5227 5228 struct mlx5_ifc_set_hca_cap_out_bits { 5229 u8 status[0x8]; 5230 u8 reserved_at_8[0x18]; 5231 5232 u8 syndrome[0x20]; 5233 5234 u8 reserved_at_40[0x40]; 5235 }; 5236 5237 struct mlx5_ifc_set_hca_cap_in_bits { 5238 u8 opcode[0x10]; 5239 u8 reserved_at_10[0x10]; 5240 5241 u8 reserved_at_20[0x10]; 5242 u8 op_mod[0x10]; 5243 5244 u8 other_function[0x1]; 5245 u8 ec_vf_function[0x1]; 5246 u8 reserved_at_42[0x1]; 5247 u8 function_id_type[0x1]; 5248 u8 reserved_at_44[0xc]; 5249 u8 function_id[0x10]; 5250 5251 u8 reserved_at_60[0x20]; 5252 5253 union mlx5_ifc_hca_cap_union_bits capability; 5254 }; 5255 5256 enum { 5257 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0, 5258 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1, 5259 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2, 5260 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3, 5261 MLX5_SET_FTE_MODIFY_ENABLE_MASK_IPSEC_OBJ_ID = 0x4 5262 }; 5263 5264 struct mlx5_ifc_set_fte_out_bits { 5265 u8 status[0x8]; 5266 u8 reserved_at_8[0x18]; 5267 5268 u8 syndrome[0x20]; 5269 5270 u8 reserved_at_40[0x40]; 5271 }; 5272 5273 struct mlx5_ifc_set_fte_in_bits { 5274 u8 opcode[0x10]; 5275 u8 reserved_at_10[0x10]; 5276 5277 u8 reserved_at_20[0x10]; 5278 u8 op_mod[0x10]; 5279 5280 u8 other_vport[0x1]; 5281 u8 other_eswitch[0x1]; 5282 u8 reserved_at_42[0xe]; 5283 u8 vport_number[0x10]; 5284 5285 u8 reserved_at_60[0x20]; 5286 5287 u8 table_type[0x8]; 5288 u8 reserved_at_88[0x8]; 5289 u8 eswitch_owner_vhca_id[0x10]; 5290 5291 u8 reserved_at_a0[0x8]; 5292 u8 table_id[0x18]; 5293 5294 u8 ignore_flow_level[0x1]; 5295 u8 reserved_at_c1[0x17]; 5296 u8 modify_enable_mask[0x8]; 5297 5298 u8 reserved_at_e0[0x20]; 5299 5300 u8 flow_index[0x20]; 5301 5302 u8 reserved_at_120[0xe0]; 5303 5304 struct mlx5_ifc_flow_context_bits flow_context; 5305 }; 5306 5307 struct mlx5_ifc_dest_format_bits { 5308 u8 destination_type[0x8]; 5309 u8 destination_id[0x18]; 5310 5311 u8 destination_eswitch_owner_vhca_id_valid[0x1]; 5312 u8 packet_reformat[0x1]; 5313 u8 reserved_at_22[0xe]; 5314 u8 destination_eswitch_owner_vhca_id[0x10]; 5315 }; 5316 5317 struct mlx5_ifc_rts2rts_qp_out_bits { 5318 u8 status[0x8]; 5319 u8 reserved_at_8[0x18]; 5320 5321 u8 syndrome[0x20]; 5322 5323 u8 reserved_at_40[0x20]; 5324 u8 ece[0x20]; 5325 }; 5326 5327 struct mlx5_ifc_rts2rts_qp_in_bits { 5328 u8 opcode[0x10]; 5329 u8 uid[0x10]; 5330 5331 u8 reserved_at_20[0x10]; 5332 u8 op_mod[0x10]; 5333 5334 u8 reserved_at_40[0x8]; 5335 u8 qpn[0x18]; 5336 5337 u8 reserved_at_60[0x20]; 5338 5339 u8 opt_param_mask[0x20]; 5340 5341 u8 ece[0x20]; 5342 5343 struct mlx5_ifc_qpc_bits qpc; 5344 5345 u8 reserved_at_800[0x80]; 5346 }; 5347 5348 struct mlx5_ifc_rtr2rts_qp_out_bits { 5349 u8 status[0x8]; 5350 u8 reserved_at_8[0x18]; 5351 5352 u8 syndrome[0x20]; 5353 5354 u8 reserved_at_40[0x20]; 5355 u8 ece[0x20]; 5356 }; 5357 5358 struct mlx5_ifc_rtr2rts_qp_in_bits { 5359 u8 opcode[0x10]; 5360 u8 uid[0x10]; 5361 5362 u8 reserved_at_20[0x10]; 5363 u8 op_mod[0x10]; 5364 5365 u8 reserved_at_40[0x8]; 5366 u8 qpn[0x18]; 5367 5368 u8 reserved_at_60[0x20]; 5369 5370 u8 opt_param_mask[0x20]; 5371 5372 u8 ece[0x20]; 5373 5374 struct mlx5_ifc_qpc_bits qpc; 5375 5376 u8 reserved_at_800[0x80]; 5377 }; 5378 5379 struct mlx5_ifc_rst2init_qp_out_bits { 5380 u8 status[0x8]; 5381 u8 reserved_at_8[0x18]; 5382 5383 u8 syndrome[0x20]; 5384 5385 u8 reserved_at_40[0x20]; 5386 u8 ece[0x20]; 5387 }; 5388 5389 struct mlx5_ifc_rst2init_qp_in_bits { 5390 u8 opcode[0x10]; 5391 u8 uid[0x10]; 5392 5393 u8 reserved_at_20[0x10]; 5394 u8 op_mod[0x10]; 5395 5396 u8 reserved_at_40[0x8]; 5397 u8 qpn[0x18]; 5398 5399 u8 reserved_at_60[0x20]; 5400 5401 u8 opt_param_mask[0x20]; 5402 5403 u8 ece[0x20]; 5404 5405 struct mlx5_ifc_qpc_bits qpc; 5406 5407 u8 reserved_at_800[0x80]; 5408 }; 5409 5410 struct mlx5_ifc_query_xrq_out_bits { 5411 u8 status[0x8]; 5412 u8 reserved_at_8[0x18]; 5413 5414 u8 syndrome[0x20]; 5415 5416 u8 reserved_at_40[0x40]; 5417 5418 struct mlx5_ifc_xrqc_bits xrq_context; 5419 }; 5420 5421 struct mlx5_ifc_query_xrq_in_bits { 5422 u8 opcode[0x10]; 5423 u8 reserved_at_10[0x10]; 5424 5425 u8 reserved_at_20[0x10]; 5426 u8 op_mod[0x10]; 5427 5428 u8 reserved_at_40[0x8]; 5429 u8 xrqn[0x18]; 5430 5431 u8 reserved_at_60[0x20]; 5432 }; 5433 5434 struct mlx5_ifc_query_xrc_srq_out_bits { 5435 u8 status[0x8]; 5436 u8 reserved_at_8[0x18]; 5437 5438 u8 syndrome[0x20]; 5439 5440 u8 reserved_at_40[0x40]; 5441 5442 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 5443 5444 u8 reserved_at_280[0x600]; 5445 5446 u8 pas[][0x40]; 5447 }; 5448 5449 struct mlx5_ifc_query_xrc_srq_in_bits { 5450 u8 opcode[0x10]; 5451 u8 reserved_at_10[0x10]; 5452 5453 u8 reserved_at_20[0x10]; 5454 u8 op_mod[0x10]; 5455 5456 u8 reserved_at_40[0x8]; 5457 u8 xrc_srqn[0x18]; 5458 5459 u8 reserved_at_60[0x20]; 5460 }; 5461 5462 enum { 5463 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0, 5464 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1, 5465 }; 5466 5467 struct mlx5_ifc_query_vport_state_out_bits { 5468 u8 status[0x8]; 5469 u8 reserved_at_8[0x18]; 5470 5471 u8 syndrome[0x20]; 5472 5473 u8 reserved_at_40[0x20]; 5474 5475 u8 max_tx_speed[0x10]; 5476 u8 reserved_at_70[0x8]; 5477 u8 admin_state[0x4]; 5478 u8 state[0x4]; 5479 }; 5480 5481 struct mlx5_ifc_array1024_auto_bits { 5482 u8 array1024_auto[32][0x20]; 5483 }; 5484 5485 struct mlx5_ifc_query_vuid_in_bits { 5486 u8 opcode[0x10]; 5487 u8 uid[0x10]; 5488 5489 u8 reserved_at_20[0x40]; 5490 5491 u8 query_vfs_vuid[0x1]; 5492 u8 data_direct[0x1]; 5493 u8 reserved_at_62[0xe]; 5494 u8 vhca_id[0x10]; 5495 }; 5496 5497 struct mlx5_ifc_query_vuid_out_bits { 5498 u8 status[0x8]; 5499 u8 reserved_at_8[0x18]; 5500 5501 u8 syndrome[0x20]; 5502 5503 u8 reserved_at_40[0x1a0]; 5504 5505 u8 reserved_at_1e0[0x10]; 5506 u8 num_of_entries[0x10]; 5507 5508 struct mlx5_ifc_array1024_auto_bits vuid[]; 5509 }; 5510 5511 enum { 5512 MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT = 0x0, 5513 MLX5_VPORT_STATE_OP_MOD_ESW_VPORT = 0x1, 5514 MLX5_VPORT_STATE_OP_MOD_UPLINK = 0x2, 5515 }; 5516 5517 struct mlx5_ifc_arm_monitor_counter_in_bits { 5518 u8 opcode[0x10]; 5519 u8 uid[0x10]; 5520 5521 u8 reserved_at_20[0x10]; 5522 u8 op_mod[0x10]; 5523 5524 u8 reserved_at_40[0x20]; 5525 5526 u8 reserved_at_60[0x20]; 5527 }; 5528 5529 struct mlx5_ifc_arm_monitor_counter_out_bits { 5530 u8 status[0x8]; 5531 u8 reserved_at_8[0x18]; 5532 5533 u8 syndrome[0x20]; 5534 5535 u8 reserved_at_40[0x40]; 5536 }; 5537 5538 enum { 5539 MLX5_QUERY_MONITOR_CNT_TYPE_PPCNT = 0x0, 5540 MLX5_QUERY_MONITOR_CNT_TYPE_Q_COUNTER = 0x1, 5541 }; 5542 5543 enum mlx5_monitor_counter_ppcnt { 5544 MLX5_QUERY_MONITOR_PPCNT_IN_RANGE_LENGTH_ERRORS = 0x0, 5545 MLX5_QUERY_MONITOR_PPCNT_OUT_OF_RANGE_LENGTH_FIELD = 0x1, 5546 MLX5_QUERY_MONITOR_PPCNT_FRAME_TOO_LONG_ERRORS = 0x2, 5547 MLX5_QUERY_MONITOR_PPCNT_FRAME_CHECK_SEQUENCE_ERRORS = 0x3, 5548 MLX5_QUERY_MONITOR_PPCNT_ALIGNMENT_ERRORS = 0x4, 5549 MLX5_QUERY_MONITOR_PPCNT_IF_OUT_DISCARDS = 0x5, 5550 }; 5551 5552 enum { 5553 MLX5_QUERY_MONITOR_Q_COUNTER_RX_OUT_OF_BUFFER = 0x4, 5554 }; 5555 5556 struct mlx5_ifc_monitor_counter_output_bits { 5557 u8 reserved_at_0[0x4]; 5558 u8 type[0x4]; 5559 u8 reserved_at_8[0x8]; 5560 u8 counter[0x10]; 5561 5562 u8 counter_group_id[0x20]; 5563 }; 5564 5565 #define MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 (6) 5566 #define MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1 (1) 5567 #define MLX5_CMD_SET_MONITOR_NUM_COUNTER (MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 +\ 5568 MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1) 5569 5570 struct mlx5_ifc_set_monitor_counter_in_bits { 5571 u8 opcode[0x10]; 5572 u8 uid[0x10]; 5573 5574 u8 reserved_at_20[0x10]; 5575 u8 op_mod[0x10]; 5576 5577 u8 reserved_at_40[0x10]; 5578 u8 num_of_counters[0x10]; 5579 5580 u8 reserved_at_60[0x20]; 5581 5582 struct mlx5_ifc_monitor_counter_output_bits monitor_counter[MLX5_CMD_SET_MONITOR_NUM_COUNTER]; 5583 }; 5584 5585 struct mlx5_ifc_set_monitor_counter_out_bits { 5586 u8 status[0x8]; 5587 u8 reserved_at_8[0x18]; 5588 5589 u8 syndrome[0x20]; 5590 5591 u8 reserved_at_40[0x40]; 5592 }; 5593 5594 struct mlx5_ifc_query_vport_state_in_bits { 5595 u8 opcode[0x10]; 5596 u8 reserved_at_10[0x10]; 5597 5598 u8 reserved_at_20[0x10]; 5599 u8 op_mod[0x10]; 5600 5601 u8 other_vport[0x1]; 5602 u8 reserved_at_41[0xf]; 5603 u8 vport_number[0x10]; 5604 5605 u8 reserved_at_60[0x20]; 5606 }; 5607 5608 struct mlx5_ifc_query_vnic_env_out_bits { 5609 u8 status[0x8]; 5610 u8 reserved_at_8[0x18]; 5611 5612 u8 syndrome[0x20]; 5613 5614 u8 reserved_at_40[0x40]; 5615 5616 struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env; 5617 }; 5618 5619 enum { 5620 MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS = 0x0, 5621 }; 5622 5623 struct mlx5_ifc_query_vnic_env_in_bits { 5624 u8 opcode[0x10]; 5625 u8 reserved_at_10[0x10]; 5626 5627 u8 reserved_at_20[0x10]; 5628 u8 op_mod[0x10]; 5629 5630 u8 other_vport[0x1]; 5631 u8 reserved_at_41[0xf]; 5632 u8 vport_number[0x10]; 5633 5634 u8 reserved_at_60[0x20]; 5635 }; 5636 5637 struct mlx5_ifc_query_vport_counter_out_bits { 5638 u8 status[0x8]; 5639 u8 reserved_at_8[0x18]; 5640 5641 u8 syndrome[0x20]; 5642 5643 u8 reserved_at_40[0x40]; 5644 5645 struct mlx5_ifc_traffic_counter_bits received_errors; 5646 5647 struct mlx5_ifc_traffic_counter_bits transmit_errors; 5648 5649 struct mlx5_ifc_traffic_counter_bits received_ib_unicast; 5650 5651 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast; 5652 5653 struct mlx5_ifc_traffic_counter_bits received_ib_multicast; 5654 5655 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast; 5656 5657 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast; 5658 5659 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast; 5660 5661 struct mlx5_ifc_traffic_counter_bits received_eth_unicast; 5662 5663 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast; 5664 5665 struct mlx5_ifc_traffic_counter_bits received_eth_multicast; 5666 5667 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast; 5668 5669 struct mlx5_ifc_traffic_counter_bits local_loopback; 5670 5671 u8 reserved_at_700[0x980]; 5672 }; 5673 5674 enum { 5675 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0, 5676 }; 5677 5678 struct mlx5_ifc_query_vport_counter_in_bits { 5679 u8 opcode[0x10]; 5680 u8 reserved_at_10[0x10]; 5681 5682 u8 reserved_at_20[0x10]; 5683 u8 op_mod[0x10]; 5684 5685 u8 other_vport[0x1]; 5686 u8 reserved_at_41[0xb]; 5687 u8 port_num[0x4]; 5688 u8 vport_number[0x10]; 5689 5690 u8 reserved_at_60[0x60]; 5691 5692 u8 clear[0x1]; 5693 u8 reserved_at_c1[0x1f]; 5694 5695 u8 reserved_at_e0[0x20]; 5696 }; 5697 5698 struct mlx5_ifc_query_tis_out_bits { 5699 u8 status[0x8]; 5700 u8 reserved_at_8[0x18]; 5701 5702 u8 syndrome[0x20]; 5703 5704 u8 reserved_at_40[0x40]; 5705 5706 struct mlx5_ifc_tisc_bits tis_context; 5707 }; 5708 5709 struct mlx5_ifc_query_tis_in_bits { 5710 u8 opcode[0x10]; 5711 u8 reserved_at_10[0x10]; 5712 5713 u8 reserved_at_20[0x10]; 5714 u8 op_mod[0x10]; 5715 5716 u8 reserved_at_40[0x8]; 5717 u8 tisn[0x18]; 5718 5719 u8 reserved_at_60[0x20]; 5720 }; 5721 5722 struct mlx5_ifc_query_tir_out_bits { 5723 u8 status[0x8]; 5724 u8 reserved_at_8[0x18]; 5725 5726 u8 syndrome[0x20]; 5727 5728 u8 reserved_at_40[0xc0]; 5729 5730 struct mlx5_ifc_tirc_bits tir_context; 5731 }; 5732 5733 struct mlx5_ifc_query_tir_in_bits { 5734 u8 opcode[0x10]; 5735 u8 reserved_at_10[0x10]; 5736 5737 u8 reserved_at_20[0x10]; 5738 u8 op_mod[0x10]; 5739 5740 u8 reserved_at_40[0x8]; 5741 u8 tirn[0x18]; 5742 5743 u8 reserved_at_60[0x20]; 5744 }; 5745 5746 struct mlx5_ifc_query_srq_out_bits { 5747 u8 status[0x8]; 5748 u8 reserved_at_8[0x18]; 5749 5750 u8 syndrome[0x20]; 5751 5752 u8 reserved_at_40[0x40]; 5753 5754 struct mlx5_ifc_srqc_bits srq_context_entry; 5755 5756 u8 reserved_at_280[0x600]; 5757 5758 u8 pas[][0x40]; 5759 }; 5760 5761 struct mlx5_ifc_query_srq_in_bits { 5762 u8 opcode[0x10]; 5763 u8 reserved_at_10[0x10]; 5764 5765 u8 reserved_at_20[0x10]; 5766 u8 op_mod[0x10]; 5767 5768 u8 reserved_at_40[0x8]; 5769 u8 srqn[0x18]; 5770 5771 u8 reserved_at_60[0x20]; 5772 }; 5773 5774 struct mlx5_ifc_query_sq_out_bits { 5775 u8 status[0x8]; 5776 u8 reserved_at_8[0x18]; 5777 5778 u8 syndrome[0x20]; 5779 5780 u8 reserved_at_40[0xc0]; 5781 5782 struct mlx5_ifc_sqc_bits sq_context; 5783 }; 5784 5785 struct mlx5_ifc_query_sq_in_bits { 5786 u8 opcode[0x10]; 5787 u8 reserved_at_10[0x10]; 5788 5789 u8 reserved_at_20[0x10]; 5790 u8 op_mod[0x10]; 5791 5792 u8 reserved_at_40[0x8]; 5793 u8 sqn[0x18]; 5794 5795 u8 reserved_at_60[0x20]; 5796 }; 5797 5798 struct mlx5_ifc_query_special_contexts_out_bits { 5799 u8 status[0x8]; 5800 u8 reserved_at_8[0x18]; 5801 5802 u8 syndrome[0x20]; 5803 5804 u8 dump_fill_mkey[0x20]; 5805 5806 u8 resd_lkey[0x20]; 5807 5808 u8 null_mkey[0x20]; 5809 5810 u8 terminate_scatter_list_mkey[0x20]; 5811 5812 u8 repeated_mkey[0x20]; 5813 5814 u8 reserved_at_a0[0x20]; 5815 }; 5816 5817 struct mlx5_ifc_query_special_contexts_in_bits { 5818 u8 opcode[0x10]; 5819 u8 reserved_at_10[0x10]; 5820 5821 u8 reserved_at_20[0x10]; 5822 u8 op_mod[0x10]; 5823 5824 u8 reserved_at_40[0x40]; 5825 }; 5826 5827 struct mlx5_ifc_query_scheduling_element_out_bits { 5828 u8 opcode[0x10]; 5829 u8 reserved_at_10[0x10]; 5830 5831 u8 reserved_at_20[0x10]; 5832 u8 op_mod[0x10]; 5833 5834 u8 reserved_at_40[0xc0]; 5835 5836 struct mlx5_ifc_scheduling_context_bits scheduling_context; 5837 5838 u8 reserved_at_300[0x100]; 5839 }; 5840 5841 enum { 5842 SCHEDULING_HIERARCHY_E_SWITCH = 0x2, 5843 SCHEDULING_HIERARCHY_NIC = 0x3, 5844 }; 5845 5846 struct mlx5_ifc_query_scheduling_element_in_bits { 5847 u8 opcode[0x10]; 5848 u8 reserved_at_10[0x10]; 5849 5850 u8 reserved_at_20[0x10]; 5851 u8 op_mod[0x10]; 5852 5853 u8 scheduling_hierarchy[0x8]; 5854 u8 reserved_at_48[0x18]; 5855 5856 u8 scheduling_element_id[0x20]; 5857 5858 u8 reserved_at_80[0x180]; 5859 }; 5860 5861 struct mlx5_ifc_query_rqt_out_bits { 5862 u8 status[0x8]; 5863 u8 reserved_at_8[0x18]; 5864 5865 u8 syndrome[0x20]; 5866 5867 u8 reserved_at_40[0xc0]; 5868 5869 struct mlx5_ifc_rqtc_bits rqt_context; 5870 }; 5871 5872 struct mlx5_ifc_query_rqt_in_bits { 5873 u8 opcode[0x10]; 5874 u8 reserved_at_10[0x10]; 5875 5876 u8 reserved_at_20[0x10]; 5877 u8 op_mod[0x10]; 5878 5879 u8 reserved_at_40[0x8]; 5880 u8 rqtn[0x18]; 5881 5882 u8 reserved_at_60[0x20]; 5883 }; 5884 5885 struct mlx5_ifc_query_rq_out_bits { 5886 u8 status[0x8]; 5887 u8 reserved_at_8[0x18]; 5888 5889 u8 syndrome[0x20]; 5890 5891 u8 reserved_at_40[0xc0]; 5892 5893 struct mlx5_ifc_rqc_bits rq_context; 5894 }; 5895 5896 struct mlx5_ifc_query_rq_in_bits { 5897 u8 opcode[0x10]; 5898 u8 reserved_at_10[0x10]; 5899 5900 u8 reserved_at_20[0x10]; 5901 u8 op_mod[0x10]; 5902 5903 u8 reserved_at_40[0x8]; 5904 u8 rqn[0x18]; 5905 5906 u8 reserved_at_60[0x20]; 5907 }; 5908 5909 struct mlx5_ifc_query_roce_address_out_bits { 5910 u8 status[0x8]; 5911 u8 reserved_at_8[0x18]; 5912 5913 u8 syndrome[0x20]; 5914 5915 u8 reserved_at_40[0x40]; 5916 5917 struct mlx5_ifc_roce_addr_layout_bits roce_address; 5918 }; 5919 5920 struct mlx5_ifc_query_roce_address_in_bits { 5921 u8 opcode[0x10]; 5922 u8 reserved_at_10[0x10]; 5923 5924 u8 reserved_at_20[0x10]; 5925 u8 op_mod[0x10]; 5926 5927 u8 roce_address_index[0x10]; 5928 u8 reserved_at_50[0xc]; 5929 u8 vhca_port_num[0x4]; 5930 5931 u8 reserved_at_60[0x20]; 5932 }; 5933 5934 struct mlx5_ifc_query_rmp_out_bits { 5935 u8 status[0x8]; 5936 u8 reserved_at_8[0x18]; 5937 5938 u8 syndrome[0x20]; 5939 5940 u8 reserved_at_40[0xc0]; 5941 5942 struct mlx5_ifc_rmpc_bits rmp_context; 5943 }; 5944 5945 struct mlx5_ifc_query_rmp_in_bits { 5946 u8 opcode[0x10]; 5947 u8 reserved_at_10[0x10]; 5948 5949 u8 reserved_at_20[0x10]; 5950 u8 op_mod[0x10]; 5951 5952 u8 reserved_at_40[0x8]; 5953 u8 rmpn[0x18]; 5954 5955 u8 reserved_at_60[0x20]; 5956 }; 5957 5958 struct mlx5_ifc_cqe_error_syndrome_bits { 5959 u8 hw_error_syndrome[0x8]; 5960 u8 hw_syndrome_type[0x4]; 5961 u8 reserved_at_c[0x4]; 5962 u8 vendor_error_syndrome[0x8]; 5963 u8 syndrome[0x8]; 5964 }; 5965 5966 struct mlx5_ifc_qp_context_extension_bits { 5967 u8 reserved_at_0[0x60]; 5968 5969 struct mlx5_ifc_cqe_error_syndrome_bits error_syndrome; 5970 5971 u8 reserved_at_80[0x580]; 5972 }; 5973 5974 struct mlx5_ifc_qpc_extension_and_pas_list_in_bits { 5975 struct mlx5_ifc_qp_context_extension_bits qpc_data_extension; 5976 5977 u8 pas[0][0x40]; 5978 }; 5979 5980 struct mlx5_ifc_qp_pas_list_in_bits { 5981 struct mlx5_ifc_cmd_pas_bits pas[0]; 5982 }; 5983 5984 union mlx5_ifc_qp_pas_or_qpc_ext_and_pas_bits { 5985 struct mlx5_ifc_qp_pas_list_in_bits qp_pas_list; 5986 struct mlx5_ifc_qpc_extension_and_pas_list_in_bits qpc_ext_and_pas_list; 5987 }; 5988 5989 struct mlx5_ifc_query_qp_out_bits { 5990 u8 status[0x8]; 5991 u8 reserved_at_8[0x18]; 5992 5993 u8 syndrome[0x20]; 5994 5995 u8 reserved_at_40[0x40]; 5996 5997 u8 opt_param_mask[0x20]; 5998 5999 u8 ece[0x20]; 6000 6001 struct mlx5_ifc_qpc_bits qpc; 6002 6003 u8 reserved_at_800[0x80]; 6004 6005 union mlx5_ifc_qp_pas_or_qpc_ext_and_pas_bits qp_pas_or_qpc_ext_and_pas; 6006 }; 6007 6008 struct mlx5_ifc_query_qp_in_bits { 6009 u8 opcode[0x10]; 6010 u8 reserved_at_10[0x10]; 6011 6012 u8 reserved_at_20[0x10]; 6013 u8 op_mod[0x10]; 6014 6015 u8 qpc_ext[0x1]; 6016 u8 reserved_at_41[0x7]; 6017 u8 qpn[0x18]; 6018 6019 u8 reserved_at_60[0x20]; 6020 }; 6021 6022 struct mlx5_ifc_query_q_counter_out_bits { 6023 u8 status[0x8]; 6024 u8 reserved_at_8[0x18]; 6025 6026 u8 syndrome[0x20]; 6027 6028 u8 reserved_at_40[0x40]; 6029 6030 u8 rx_write_requests[0x20]; 6031 6032 u8 reserved_at_a0[0x20]; 6033 6034 u8 rx_read_requests[0x20]; 6035 6036 u8 reserved_at_e0[0x20]; 6037 6038 u8 rx_atomic_requests[0x20]; 6039 6040 u8 reserved_at_120[0x20]; 6041 6042 u8 rx_dct_connect[0x20]; 6043 6044 u8 reserved_at_160[0x20]; 6045 6046 u8 out_of_buffer[0x20]; 6047 6048 u8 reserved_at_1a0[0x20]; 6049 6050 u8 out_of_sequence[0x20]; 6051 6052 u8 reserved_at_1e0[0x20]; 6053 6054 u8 duplicate_request[0x20]; 6055 6056 u8 reserved_at_220[0x20]; 6057 6058 u8 rnr_nak_retry_err[0x20]; 6059 6060 u8 reserved_at_260[0x20]; 6061 6062 u8 packet_seq_err[0x20]; 6063 6064 u8 reserved_at_2a0[0x20]; 6065 6066 u8 implied_nak_seq_err[0x20]; 6067 6068 u8 reserved_at_2e0[0x20]; 6069 6070 u8 local_ack_timeout_err[0x20]; 6071 6072 u8 reserved_at_320[0x60]; 6073 6074 u8 req_rnr_retries_exceeded[0x20]; 6075 6076 u8 reserved_at_3a0[0x20]; 6077 6078 u8 resp_local_length_error[0x20]; 6079 6080 u8 req_local_length_error[0x20]; 6081 6082 u8 resp_local_qp_error[0x20]; 6083 6084 u8 local_operation_error[0x20]; 6085 6086 u8 resp_local_protection[0x20]; 6087 6088 u8 req_local_protection[0x20]; 6089 6090 u8 resp_cqe_error[0x20]; 6091 6092 u8 req_cqe_error[0x20]; 6093 6094 u8 req_mw_binding[0x20]; 6095 6096 u8 req_bad_response[0x20]; 6097 6098 u8 req_remote_invalid_request[0x20]; 6099 6100 u8 resp_remote_invalid_request[0x20]; 6101 6102 u8 req_remote_access_errors[0x20]; 6103 6104 u8 resp_remote_access_errors[0x20]; 6105 6106 u8 req_remote_operation_errors[0x20]; 6107 6108 u8 req_transport_retries_exceeded[0x20]; 6109 6110 u8 cq_overflow[0x20]; 6111 6112 u8 resp_cqe_flush_error[0x20]; 6113 6114 u8 req_cqe_flush_error[0x20]; 6115 6116 u8 reserved_at_620[0x20]; 6117 6118 u8 roce_adp_retrans[0x20]; 6119 6120 u8 roce_adp_retrans_to[0x20]; 6121 6122 u8 roce_slow_restart[0x20]; 6123 6124 u8 roce_slow_restart_cnps[0x20]; 6125 6126 u8 roce_slow_restart_trans[0x20]; 6127 6128 u8 reserved_at_6e0[0x120]; 6129 }; 6130 6131 struct mlx5_ifc_query_q_counter_in_bits { 6132 u8 opcode[0x10]; 6133 u8 reserved_at_10[0x10]; 6134 6135 u8 reserved_at_20[0x10]; 6136 u8 op_mod[0x10]; 6137 6138 u8 other_vport[0x1]; 6139 u8 reserved_at_41[0xf]; 6140 u8 vport_number[0x10]; 6141 6142 u8 reserved_at_60[0x60]; 6143 6144 u8 clear[0x1]; 6145 u8 aggregate[0x1]; 6146 u8 reserved_at_c2[0x1e]; 6147 6148 u8 reserved_at_e0[0x18]; 6149 u8 counter_set_id[0x8]; 6150 }; 6151 6152 struct mlx5_ifc_query_pages_out_bits { 6153 u8 status[0x8]; 6154 u8 reserved_at_8[0x18]; 6155 6156 u8 syndrome[0x20]; 6157 6158 u8 embedded_cpu_function[0x1]; 6159 u8 reserved_at_41[0xf]; 6160 u8 function_id[0x10]; 6161 6162 u8 num_pages[0x20]; 6163 }; 6164 6165 enum { 6166 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1, 6167 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2, 6168 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3, 6169 }; 6170 6171 struct mlx5_ifc_query_pages_in_bits { 6172 u8 opcode[0x10]; 6173 u8 reserved_at_10[0x10]; 6174 6175 u8 reserved_at_20[0x10]; 6176 u8 op_mod[0x10]; 6177 6178 u8 embedded_cpu_function[0x1]; 6179 u8 reserved_at_41[0xf]; 6180 u8 function_id[0x10]; 6181 6182 u8 reserved_at_60[0x20]; 6183 }; 6184 6185 struct mlx5_ifc_query_nic_vport_context_out_bits { 6186 u8 status[0x8]; 6187 u8 reserved_at_8[0x18]; 6188 6189 u8 syndrome[0x20]; 6190 6191 u8 reserved_at_40[0x40]; 6192 6193 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 6194 }; 6195 6196 struct mlx5_ifc_query_nic_vport_context_in_bits { 6197 u8 opcode[0x10]; 6198 u8 reserved_at_10[0x10]; 6199 6200 u8 reserved_at_20[0x10]; 6201 u8 op_mod[0x10]; 6202 6203 u8 other_vport[0x1]; 6204 u8 reserved_at_41[0xf]; 6205 u8 vport_number[0x10]; 6206 6207 u8 reserved_at_60[0x5]; 6208 u8 allowed_list_type[0x3]; 6209 u8 reserved_at_68[0x18]; 6210 }; 6211 6212 struct mlx5_ifc_query_mkey_out_bits { 6213 u8 status[0x8]; 6214 u8 reserved_at_8[0x18]; 6215 6216 u8 syndrome[0x20]; 6217 6218 u8 reserved_at_40[0x40]; 6219 6220 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 6221 6222 u8 reserved_at_280[0x600]; 6223 6224 u8 bsf0_klm0_pas_mtt0_1[16][0x8]; 6225 6226 u8 bsf1_klm1_pas_mtt2_3[16][0x8]; 6227 }; 6228 6229 struct mlx5_ifc_query_mkey_in_bits { 6230 u8 opcode[0x10]; 6231 u8 reserved_at_10[0x10]; 6232 6233 u8 reserved_at_20[0x10]; 6234 u8 op_mod[0x10]; 6235 6236 u8 reserved_at_40[0x8]; 6237 u8 mkey_index[0x18]; 6238 6239 u8 pg_access[0x1]; 6240 u8 reserved_at_61[0x1f]; 6241 }; 6242 6243 struct mlx5_ifc_query_mad_demux_out_bits { 6244 u8 status[0x8]; 6245 u8 reserved_at_8[0x18]; 6246 6247 u8 syndrome[0x20]; 6248 6249 u8 reserved_at_40[0x40]; 6250 6251 u8 mad_dumux_parameters_block[0x20]; 6252 }; 6253 6254 struct mlx5_ifc_query_mad_demux_in_bits { 6255 u8 opcode[0x10]; 6256 u8 reserved_at_10[0x10]; 6257 6258 u8 reserved_at_20[0x10]; 6259 u8 op_mod[0x10]; 6260 6261 u8 reserved_at_40[0x40]; 6262 }; 6263 6264 struct mlx5_ifc_query_l2_table_entry_out_bits { 6265 u8 status[0x8]; 6266 u8 reserved_at_8[0x18]; 6267 6268 u8 syndrome[0x20]; 6269 6270 u8 reserved_at_40[0xa0]; 6271 6272 u8 reserved_at_e0[0x11]; 6273 u8 silent_mode[0x1]; 6274 u8 reserved_at_f2[0x1]; 6275 u8 vlan_valid[0x1]; 6276 u8 vlan[0xc]; 6277 6278 struct mlx5_ifc_mac_address_layout_bits mac_address; 6279 6280 u8 reserved_at_140[0xc0]; 6281 }; 6282 6283 struct mlx5_ifc_query_l2_table_entry_in_bits { 6284 u8 opcode[0x10]; 6285 u8 reserved_at_10[0x10]; 6286 6287 u8 reserved_at_20[0x10]; 6288 u8 op_mod[0x10]; 6289 6290 u8 reserved_at_40[0x40]; 6291 6292 u8 silent_mode_query[0x1]; 6293 u8 reserved_at_81[0x1f]; 6294 6295 u8 reserved_at_a0[0x8]; 6296 u8 table_index[0x18]; 6297 6298 u8 reserved_at_c0[0x140]; 6299 }; 6300 6301 struct mlx5_ifc_query_issi_out_bits { 6302 u8 status[0x8]; 6303 u8 reserved_at_8[0x18]; 6304 6305 u8 syndrome[0x20]; 6306 6307 u8 reserved_at_40[0x10]; 6308 u8 current_issi[0x10]; 6309 6310 u8 reserved_at_60[0xa0]; 6311 6312 u8 reserved_at_100[76][0x8]; 6313 u8 supported_issi_dw0[0x20]; 6314 }; 6315 6316 struct mlx5_ifc_query_issi_in_bits { 6317 u8 opcode[0x10]; 6318 u8 reserved_at_10[0x10]; 6319 6320 u8 reserved_at_20[0x10]; 6321 u8 op_mod[0x10]; 6322 6323 u8 reserved_at_40[0x40]; 6324 }; 6325 6326 struct mlx5_ifc_set_driver_version_out_bits { 6327 u8 status[0x8]; 6328 u8 reserved_0[0x18]; 6329 6330 u8 syndrome[0x20]; 6331 u8 reserved_1[0x40]; 6332 }; 6333 6334 struct mlx5_ifc_set_driver_version_in_bits { 6335 u8 opcode[0x10]; 6336 u8 reserved_0[0x10]; 6337 6338 u8 reserved_1[0x10]; 6339 u8 op_mod[0x10]; 6340 6341 u8 reserved_2[0x40]; 6342 u8 driver_version[64][0x8]; 6343 }; 6344 6345 struct mlx5_ifc_query_hca_vport_pkey_out_bits { 6346 u8 status[0x8]; 6347 u8 reserved_at_8[0x18]; 6348 6349 u8 syndrome[0x20]; 6350 6351 u8 reserved_at_40[0x40]; 6352 6353 struct mlx5_ifc_pkey_bits pkey[]; 6354 }; 6355 6356 struct mlx5_ifc_query_hca_vport_pkey_in_bits { 6357 u8 opcode[0x10]; 6358 u8 reserved_at_10[0x10]; 6359 6360 u8 reserved_at_20[0x10]; 6361 u8 op_mod[0x10]; 6362 6363 u8 other_vport[0x1]; 6364 u8 reserved_at_41[0xb]; 6365 u8 port_num[0x4]; 6366 u8 vport_number[0x10]; 6367 6368 u8 reserved_at_60[0x10]; 6369 u8 pkey_index[0x10]; 6370 }; 6371 6372 enum { 6373 MLX5_HCA_VPORT_SEL_PORT_GUID = 1 << 0, 6374 MLX5_HCA_VPORT_SEL_NODE_GUID = 1 << 1, 6375 MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2, 6376 }; 6377 6378 struct mlx5_ifc_query_hca_vport_gid_out_bits { 6379 u8 status[0x8]; 6380 u8 reserved_at_8[0x18]; 6381 6382 u8 syndrome[0x20]; 6383 6384 u8 reserved_at_40[0x20]; 6385 6386 u8 gids_num[0x10]; 6387 u8 reserved_at_70[0x10]; 6388 6389 struct mlx5_ifc_array128_auto_bits gid[]; 6390 }; 6391 6392 struct mlx5_ifc_query_hca_vport_gid_in_bits { 6393 u8 opcode[0x10]; 6394 u8 reserved_at_10[0x10]; 6395 6396 u8 reserved_at_20[0x10]; 6397 u8 op_mod[0x10]; 6398 6399 u8 other_vport[0x1]; 6400 u8 reserved_at_41[0xb]; 6401 u8 port_num[0x4]; 6402 u8 vport_number[0x10]; 6403 6404 u8 reserved_at_60[0x10]; 6405 u8 gid_index[0x10]; 6406 }; 6407 6408 struct mlx5_ifc_query_hca_vport_context_out_bits { 6409 u8 status[0x8]; 6410 u8 reserved_at_8[0x18]; 6411 6412 u8 syndrome[0x20]; 6413 6414 u8 reserved_at_40[0x40]; 6415 6416 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 6417 }; 6418 6419 struct mlx5_ifc_query_hca_vport_context_in_bits { 6420 u8 opcode[0x10]; 6421 u8 reserved_at_10[0x10]; 6422 6423 u8 reserved_at_20[0x10]; 6424 u8 op_mod[0x10]; 6425 6426 u8 other_vport[0x1]; 6427 u8 reserved_at_41[0xb]; 6428 u8 port_num[0x4]; 6429 u8 vport_number[0x10]; 6430 6431 u8 reserved_at_60[0x20]; 6432 }; 6433 6434 struct mlx5_ifc_query_hca_cap_out_bits { 6435 u8 status[0x8]; 6436 u8 reserved_at_8[0x18]; 6437 6438 u8 syndrome[0x20]; 6439 6440 u8 reserved_at_40[0x40]; 6441 6442 union mlx5_ifc_hca_cap_union_bits capability; 6443 }; 6444 6445 struct mlx5_ifc_query_hca_cap_in_bits { 6446 u8 opcode[0x10]; 6447 u8 reserved_at_10[0x10]; 6448 6449 u8 reserved_at_20[0x10]; 6450 u8 op_mod[0x10]; 6451 6452 u8 other_function[0x1]; 6453 u8 ec_vf_function[0x1]; 6454 u8 reserved_at_42[0x1]; 6455 u8 function_id_type[0x1]; 6456 u8 reserved_at_44[0xc]; 6457 u8 function_id[0x10]; 6458 6459 u8 reserved_at_60[0x20]; 6460 }; 6461 6462 struct mlx5_ifc_other_hca_cap_bits { 6463 u8 roce[0x1]; 6464 u8 reserved_at_1[0x27f]; 6465 }; 6466 6467 struct mlx5_ifc_query_other_hca_cap_out_bits { 6468 u8 status[0x8]; 6469 u8 reserved_at_8[0x18]; 6470 6471 u8 syndrome[0x20]; 6472 6473 u8 reserved_at_40[0x40]; 6474 6475 struct mlx5_ifc_other_hca_cap_bits other_capability; 6476 }; 6477 6478 struct mlx5_ifc_query_other_hca_cap_in_bits { 6479 u8 opcode[0x10]; 6480 u8 reserved_at_10[0x10]; 6481 6482 u8 reserved_at_20[0x10]; 6483 u8 op_mod[0x10]; 6484 6485 u8 reserved_at_40[0x10]; 6486 u8 function_id[0x10]; 6487 6488 u8 reserved_at_60[0x20]; 6489 }; 6490 6491 struct mlx5_ifc_modify_other_hca_cap_out_bits { 6492 u8 status[0x8]; 6493 u8 reserved_at_8[0x18]; 6494 6495 u8 syndrome[0x20]; 6496 6497 u8 reserved_at_40[0x40]; 6498 }; 6499 6500 struct mlx5_ifc_modify_other_hca_cap_in_bits { 6501 u8 opcode[0x10]; 6502 u8 reserved_at_10[0x10]; 6503 6504 u8 reserved_at_20[0x10]; 6505 u8 op_mod[0x10]; 6506 6507 u8 reserved_at_40[0x10]; 6508 u8 function_id[0x10]; 6509 u8 field_select[0x20]; 6510 6511 struct mlx5_ifc_other_hca_cap_bits other_capability; 6512 }; 6513 6514 struct mlx5_ifc_sw_owner_icm_root_params_bits { 6515 u8 sw_owner_icm_root_1[0x40]; 6516 6517 u8 sw_owner_icm_root_0[0x40]; 6518 }; 6519 6520 struct mlx5_ifc_rtc_params_bits { 6521 u8 rtc_id_0[0x20]; 6522 6523 u8 rtc_id_1[0x20]; 6524 6525 u8 reserved_at_40[0x40]; 6526 }; 6527 6528 struct mlx5_ifc_flow_table_context_bits { 6529 u8 reformat_en[0x1]; 6530 u8 decap_en[0x1]; 6531 u8 sw_owner[0x1]; 6532 u8 termination_table[0x1]; 6533 u8 table_miss_action[0x4]; 6534 u8 level[0x8]; 6535 u8 rtc_valid[0x1]; 6536 u8 reserved_at_11[0x7]; 6537 u8 log_size[0x8]; 6538 6539 u8 reserved_at_20[0x8]; 6540 u8 table_miss_id[0x18]; 6541 6542 u8 reserved_at_40[0x8]; 6543 u8 lag_master_next_table_id[0x18]; 6544 6545 u8 reserved_at_60[0x60]; 6546 6547 union { 6548 struct mlx5_ifc_sw_owner_icm_root_params_bits sws; 6549 struct mlx5_ifc_rtc_params_bits hws; 6550 }; 6551 }; 6552 6553 struct mlx5_ifc_query_flow_table_out_bits { 6554 u8 status[0x8]; 6555 u8 reserved_at_8[0x18]; 6556 6557 u8 syndrome[0x20]; 6558 6559 u8 reserved_at_40[0x80]; 6560 6561 struct mlx5_ifc_flow_table_context_bits flow_table_context; 6562 }; 6563 6564 struct mlx5_ifc_query_flow_table_in_bits { 6565 u8 opcode[0x10]; 6566 u8 reserved_at_10[0x10]; 6567 6568 u8 reserved_at_20[0x10]; 6569 u8 op_mod[0x10]; 6570 6571 u8 reserved_at_40[0x40]; 6572 6573 u8 table_type[0x8]; 6574 u8 reserved_at_88[0x18]; 6575 6576 u8 reserved_at_a0[0x8]; 6577 u8 table_id[0x18]; 6578 6579 u8 reserved_at_c0[0x140]; 6580 }; 6581 6582 struct mlx5_ifc_query_fte_out_bits { 6583 u8 status[0x8]; 6584 u8 reserved_at_8[0x18]; 6585 6586 u8 syndrome[0x20]; 6587 6588 u8 reserved_at_40[0x1c0]; 6589 6590 struct mlx5_ifc_flow_context_bits flow_context; 6591 }; 6592 6593 struct mlx5_ifc_query_fte_in_bits { 6594 u8 opcode[0x10]; 6595 u8 reserved_at_10[0x10]; 6596 6597 u8 reserved_at_20[0x10]; 6598 u8 op_mod[0x10]; 6599 6600 u8 reserved_at_40[0x40]; 6601 6602 u8 table_type[0x8]; 6603 u8 reserved_at_88[0x18]; 6604 6605 u8 reserved_at_a0[0x8]; 6606 u8 table_id[0x18]; 6607 6608 u8 reserved_at_c0[0x40]; 6609 6610 u8 flow_index[0x20]; 6611 6612 u8 reserved_at_120[0xe0]; 6613 }; 6614 6615 struct mlx5_ifc_match_definer_format_0_bits { 6616 u8 reserved_at_0[0x100]; 6617 6618 u8 metadata_reg_c_0[0x20]; 6619 6620 u8 metadata_reg_c_1[0x20]; 6621 6622 u8 outer_dmac_47_16[0x20]; 6623 6624 u8 outer_dmac_15_0[0x10]; 6625 u8 outer_ethertype[0x10]; 6626 6627 u8 reserved_at_180[0x1]; 6628 u8 sx_sniffer[0x1]; 6629 u8 functional_lb[0x1]; 6630 u8 outer_ip_frag[0x1]; 6631 u8 outer_qp_type[0x2]; 6632 u8 outer_encap_type[0x2]; 6633 u8 port_number[0x2]; 6634 u8 outer_l3_type[0x2]; 6635 u8 outer_l4_type[0x2]; 6636 u8 outer_first_vlan_type[0x2]; 6637 u8 outer_first_vlan_prio[0x3]; 6638 u8 outer_first_vlan_cfi[0x1]; 6639 u8 outer_first_vlan_vid[0xc]; 6640 6641 u8 outer_l4_type_ext[0x4]; 6642 u8 reserved_at_1a4[0x2]; 6643 u8 outer_ipsec_layer[0x2]; 6644 u8 outer_l2_type[0x2]; 6645 u8 force_lb[0x1]; 6646 u8 outer_l2_ok[0x1]; 6647 u8 outer_l3_ok[0x1]; 6648 u8 outer_l4_ok[0x1]; 6649 u8 outer_second_vlan_type[0x2]; 6650 u8 outer_second_vlan_prio[0x3]; 6651 u8 outer_second_vlan_cfi[0x1]; 6652 u8 outer_second_vlan_vid[0xc]; 6653 6654 u8 outer_smac_47_16[0x20]; 6655 6656 u8 outer_smac_15_0[0x10]; 6657 u8 inner_ipv4_checksum_ok[0x1]; 6658 u8 inner_l4_checksum_ok[0x1]; 6659 u8 outer_ipv4_checksum_ok[0x1]; 6660 u8 outer_l4_checksum_ok[0x1]; 6661 u8 inner_l3_ok[0x1]; 6662 u8 inner_l4_ok[0x1]; 6663 u8 outer_l3_ok_duplicate[0x1]; 6664 u8 outer_l4_ok_duplicate[0x1]; 6665 u8 outer_tcp_cwr[0x1]; 6666 u8 outer_tcp_ece[0x1]; 6667 u8 outer_tcp_urg[0x1]; 6668 u8 outer_tcp_ack[0x1]; 6669 u8 outer_tcp_psh[0x1]; 6670 u8 outer_tcp_rst[0x1]; 6671 u8 outer_tcp_syn[0x1]; 6672 u8 outer_tcp_fin[0x1]; 6673 }; 6674 6675 struct mlx5_ifc_match_definer_format_22_bits { 6676 u8 reserved_at_0[0x100]; 6677 6678 u8 outer_ip_src_addr[0x20]; 6679 6680 u8 outer_ip_dest_addr[0x20]; 6681 6682 u8 outer_l4_sport[0x10]; 6683 u8 outer_l4_dport[0x10]; 6684 6685 u8 reserved_at_160[0x1]; 6686 u8 sx_sniffer[0x1]; 6687 u8 functional_lb[0x1]; 6688 u8 outer_ip_frag[0x1]; 6689 u8 outer_qp_type[0x2]; 6690 u8 outer_encap_type[0x2]; 6691 u8 port_number[0x2]; 6692 u8 outer_l3_type[0x2]; 6693 u8 outer_l4_type[0x2]; 6694 u8 outer_first_vlan_type[0x2]; 6695 u8 outer_first_vlan_prio[0x3]; 6696 u8 outer_first_vlan_cfi[0x1]; 6697 u8 outer_first_vlan_vid[0xc]; 6698 6699 u8 metadata_reg_c_0[0x20]; 6700 6701 u8 outer_dmac_47_16[0x20]; 6702 6703 u8 outer_smac_47_16[0x20]; 6704 6705 u8 outer_smac_15_0[0x10]; 6706 u8 outer_dmac_15_0[0x10]; 6707 }; 6708 6709 struct mlx5_ifc_match_definer_format_23_bits { 6710 u8 reserved_at_0[0x100]; 6711 6712 u8 inner_ip_src_addr[0x20]; 6713 6714 u8 inner_ip_dest_addr[0x20]; 6715 6716 u8 inner_l4_sport[0x10]; 6717 u8 inner_l4_dport[0x10]; 6718 6719 u8 reserved_at_160[0x1]; 6720 u8 sx_sniffer[0x1]; 6721 u8 functional_lb[0x1]; 6722 u8 inner_ip_frag[0x1]; 6723 u8 inner_qp_type[0x2]; 6724 u8 inner_encap_type[0x2]; 6725 u8 port_number[0x2]; 6726 u8 inner_l3_type[0x2]; 6727 u8 inner_l4_type[0x2]; 6728 u8 inner_first_vlan_type[0x2]; 6729 u8 inner_first_vlan_prio[0x3]; 6730 u8 inner_first_vlan_cfi[0x1]; 6731 u8 inner_first_vlan_vid[0xc]; 6732 6733 u8 tunnel_header_0[0x20]; 6734 6735 u8 inner_dmac_47_16[0x20]; 6736 6737 u8 inner_smac_47_16[0x20]; 6738 6739 u8 inner_smac_15_0[0x10]; 6740 u8 inner_dmac_15_0[0x10]; 6741 }; 6742 6743 struct mlx5_ifc_match_definer_format_29_bits { 6744 u8 reserved_at_0[0xc0]; 6745 6746 u8 outer_ip_dest_addr[0x80]; 6747 6748 u8 outer_ip_src_addr[0x80]; 6749 6750 u8 outer_l4_sport[0x10]; 6751 u8 outer_l4_dport[0x10]; 6752 6753 u8 reserved_at_1e0[0x20]; 6754 }; 6755 6756 struct mlx5_ifc_match_definer_format_30_bits { 6757 u8 reserved_at_0[0xa0]; 6758 6759 u8 outer_ip_dest_addr[0x80]; 6760 6761 u8 outer_ip_src_addr[0x80]; 6762 6763 u8 outer_dmac_47_16[0x20]; 6764 6765 u8 outer_smac_47_16[0x20]; 6766 6767 u8 outer_smac_15_0[0x10]; 6768 u8 outer_dmac_15_0[0x10]; 6769 }; 6770 6771 struct mlx5_ifc_match_definer_format_31_bits { 6772 u8 reserved_at_0[0xc0]; 6773 6774 u8 inner_ip_dest_addr[0x80]; 6775 6776 u8 inner_ip_src_addr[0x80]; 6777 6778 u8 inner_l4_sport[0x10]; 6779 u8 inner_l4_dport[0x10]; 6780 6781 u8 reserved_at_1e0[0x20]; 6782 }; 6783 6784 struct mlx5_ifc_match_definer_format_32_bits { 6785 u8 reserved_at_0[0xa0]; 6786 6787 u8 inner_ip_dest_addr[0x80]; 6788 6789 u8 inner_ip_src_addr[0x80]; 6790 6791 u8 inner_dmac_47_16[0x20]; 6792 6793 u8 inner_smac_47_16[0x20]; 6794 6795 u8 inner_smac_15_0[0x10]; 6796 u8 inner_dmac_15_0[0x10]; 6797 }; 6798 6799 enum { 6800 MLX5_IFC_DEFINER_FORMAT_ID_SELECT = 61, 6801 }; 6802 6803 #define MLX5_IFC_DEFINER_FORMAT_OFFSET_UNUSED 0x0 6804 #define MLX5_IFC_DEFINER_FORMAT_OFFSET_OUTER_ETH_PKT_LEN 0x48 6805 #define MLX5_IFC_DEFINER_DW_SELECTORS_NUM 9 6806 #define MLX5_IFC_DEFINER_BYTE_SELECTORS_NUM 8 6807 6808 struct mlx5_ifc_match_definer_match_mask_bits { 6809 u8 reserved_at_1c0[5][0x20]; 6810 u8 match_dw_8[0x20]; 6811 u8 match_dw_7[0x20]; 6812 u8 match_dw_6[0x20]; 6813 u8 match_dw_5[0x20]; 6814 u8 match_dw_4[0x20]; 6815 u8 match_dw_3[0x20]; 6816 u8 match_dw_2[0x20]; 6817 u8 match_dw_1[0x20]; 6818 u8 match_dw_0[0x20]; 6819 6820 u8 match_byte_7[0x8]; 6821 u8 match_byte_6[0x8]; 6822 u8 match_byte_5[0x8]; 6823 u8 match_byte_4[0x8]; 6824 6825 u8 match_byte_3[0x8]; 6826 u8 match_byte_2[0x8]; 6827 u8 match_byte_1[0x8]; 6828 u8 match_byte_0[0x8]; 6829 }; 6830 6831 struct mlx5_ifc_match_definer_bits { 6832 u8 modify_field_select[0x40]; 6833 6834 u8 reserved_at_40[0x40]; 6835 6836 u8 reserved_at_80[0x10]; 6837 u8 format_id[0x10]; 6838 6839 u8 reserved_at_a0[0x60]; 6840 6841 u8 format_select_dw3[0x8]; 6842 u8 format_select_dw2[0x8]; 6843 u8 format_select_dw1[0x8]; 6844 u8 format_select_dw0[0x8]; 6845 6846 u8 format_select_dw7[0x8]; 6847 u8 format_select_dw6[0x8]; 6848 u8 format_select_dw5[0x8]; 6849 u8 format_select_dw4[0x8]; 6850 6851 u8 reserved_at_100[0x18]; 6852 u8 format_select_dw8[0x8]; 6853 6854 u8 reserved_at_120[0x20]; 6855 6856 u8 format_select_byte3[0x8]; 6857 u8 format_select_byte2[0x8]; 6858 u8 format_select_byte1[0x8]; 6859 u8 format_select_byte0[0x8]; 6860 6861 u8 format_select_byte7[0x8]; 6862 u8 format_select_byte6[0x8]; 6863 u8 format_select_byte5[0x8]; 6864 u8 format_select_byte4[0x8]; 6865 6866 u8 reserved_at_180[0x40]; 6867 6868 union { 6869 struct { 6870 u8 match_mask[16][0x20]; 6871 }; 6872 struct mlx5_ifc_match_definer_match_mask_bits match_mask_format; 6873 }; 6874 }; 6875 6876 struct mlx5_ifc_general_obj_create_param_bits { 6877 u8 alias_object[0x1]; 6878 u8 reserved_at_1[0x2]; 6879 u8 log_obj_range[0x5]; 6880 u8 reserved_at_8[0x18]; 6881 }; 6882 6883 struct mlx5_ifc_general_obj_query_param_bits { 6884 u8 alias_object[0x1]; 6885 u8 obj_offset[0x1f]; 6886 }; 6887 6888 struct mlx5_ifc_general_obj_in_cmd_hdr_bits { 6889 u8 opcode[0x10]; 6890 u8 uid[0x10]; 6891 6892 u8 vhca_tunnel_id[0x10]; 6893 u8 obj_type[0x10]; 6894 6895 u8 obj_id[0x20]; 6896 6897 union { 6898 struct mlx5_ifc_general_obj_create_param_bits create; 6899 struct mlx5_ifc_general_obj_query_param_bits query; 6900 } op_param; 6901 }; 6902 6903 struct mlx5_ifc_general_obj_out_cmd_hdr_bits { 6904 u8 status[0x8]; 6905 u8 reserved_at_8[0x18]; 6906 6907 u8 syndrome[0x20]; 6908 6909 u8 obj_id[0x20]; 6910 6911 u8 reserved_at_60[0x20]; 6912 }; 6913 6914 struct mlx5_ifc_allow_other_vhca_access_in_bits { 6915 u8 opcode[0x10]; 6916 u8 uid[0x10]; 6917 u8 reserved_at_20[0x10]; 6918 u8 op_mod[0x10]; 6919 u8 reserved_at_40[0x50]; 6920 u8 object_type_to_be_accessed[0x10]; 6921 u8 object_id_to_be_accessed[0x20]; 6922 u8 reserved_at_c0[0x40]; 6923 union { 6924 u8 access_key_raw[0x100]; 6925 u8 access_key[8][0x20]; 6926 }; 6927 }; 6928 6929 struct mlx5_ifc_allow_other_vhca_access_out_bits { 6930 u8 status[0x8]; 6931 u8 reserved_at_8[0x18]; 6932 u8 syndrome[0x20]; 6933 u8 reserved_at_40[0x40]; 6934 }; 6935 6936 struct mlx5_ifc_modify_header_arg_bits { 6937 u8 reserved_at_0[0x80]; 6938 6939 u8 reserved_at_80[0x8]; 6940 u8 access_pd[0x18]; 6941 }; 6942 6943 struct mlx5_ifc_create_modify_header_arg_in_bits { 6944 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 6945 struct mlx5_ifc_modify_header_arg_bits arg; 6946 }; 6947 6948 struct mlx5_ifc_create_match_definer_in_bits { 6949 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 6950 6951 struct mlx5_ifc_match_definer_bits obj_context; 6952 }; 6953 6954 struct mlx5_ifc_create_match_definer_out_bits { 6955 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 6956 }; 6957 6958 struct mlx5_ifc_alias_context_bits { 6959 u8 vhca_id_to_be_accessed[0x10]; 6960 u8 reserved_at_10[0xd]; 6961 u8 status[0x3]; 6962 u8 object_id_to_be_accessed[0x20]; 6963 u8 reserved_at_40[0x40]; 6964 union { 6965 u8 access_key_raw[0x100]; 6966 u8 access_key[8][0x20]; 6967 }; 6968 u8 metadata[0x80]; 6969 }; 6970 6971 struct mlx5_ifc_create_alias_obj_in_bits { 6972 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 6973 struct mlx5_ifc_alias_context_bits alias_ctx; 6974 }; 6975 6976 enum { 6977 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 6978 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 6979 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 6980 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3, 6981 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_3 = 0x4, 6982 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_4 = 0x5, 6983 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_5 = 0x6, 6984 }; 6985 6986 struct mlx5_ifc_query_flow_group_out_bits { 6987 u8 status[0x8]; 6988 u8 reserved_at_8[0x18]; 6989 6990 u8 syndrome[0x20]; 6991 6992 u8 reserved_at_40[0xa0]; 6993 6994 u8 start_flow_index[0x20]; 6995 6996 u8 reserved_at_100[0x20]; 6997 6998 u8 end_flow_index[0x20]; 6999 7000 u8 reserved_at_140[0xa0]; 7001 7002 u8 reserved_at_1e0[0x18]; 7003 u8 match_criteria_enable[0x8]; 7004 7005 struct mlx5_ifc_fte_match_param_bits match_criteria; 7006 7007 u8 reserved_at_1200[0xe00]; 7008 }; 7009 7010 struct mlx5_ifc_query_flow_group_in_bits { 7011 u8 opcode[0x10]; 7012 u8 reserved_at_10[0x10]; 7013 7014 u8 reserved_at_20[0x10]; 7015 u8 op_mod[0x10]; 7016 7017 u8 reserved_at_40[0x40]; 7018 7019 u8 table_type[0x8]; 7020 u8 reserved_at_88[0x18]; 7021 7022 u8 reserved_at_a0[0x8]; 7023 u8 table_id[0x18]; 7024 7025 u8 group_id[0x20]; 7026 7027 u8 reserved_at_e0[0x120]; 7028 }; 7029 7030 struct mlx5_ifc_query_flow_counter_out_bits { 7031 u8 status[0x8]; 7032 u8 reserved_at_8[0x18]; 7033 7034 u8 syndrome[0x20]; 7035 7036 u8 reserved_at_40[0x40]; 7037 7038 struct mlx5_ifc_traffic_counter_bits flow_statistics[]; 7039 }; 7040 7041 struct mlx5_ifc_query_flow_counter_in_bits { 7042 u8 opcode[0x10]; 7043 u8 reserved_at_10[0x10]; 7044 7045 u8 reserved_at_20[0x10]; 7046 u8 op_mod[0x10]; 7047 7048 u8 reserved_at_40[0x80]; 7049 7050 u8 clear[0x1]; 7051 u8 reserved_at_c1[0xf]; 7052 u8 num_of_counters[0x10]; 7053 7054 u8 flow_counter_id[0x20]; 7055 }; 7056 7057 struct mlx5_ifc_query_esw_vport_context_out_bits { 7058 u8 status[0x8]; 7059 u8 reserved_at_8[0x18]; 7060 7061 u8 syndrome[0x20]; 7062 7063 u8 reserved_at_40[0x40]; 7064 7065 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 7066 }; 7067 7068 struct mlx5_ifc_query_esw_vport_context_in_bits { 7069 u8 opcode[0x10]; 7070 u8 reserved_at_10[0x10]; 7071 7072 u8 reserved_at_20[0x10]; 7073 u8 op_mod[0x10]; 7074 7075 u8 other_vport[0x1]; 7076 u8 reserved_at_41[0xf]; 7077 u8 vport_number[0x10]; 7078 7079 u8 reserved_at_60[0x20]; 7080 }; 7081 7082 struct mlx5_ifc_destroy_esw_vport_out_bits { 7083 u8 status[0x8]; 7084 u8 reserved_at_8[0x18]; 7085 7086 u8 syndrome[0x20]; 7087 7088 u8 reserved_at_40[0x20]; 7089 }; 7090 7091 struct mlx5_ifc_destroy_esw_vport_in_bits { 7092 u8 opcode[0x10]; 7093 u8 uid[0x10]; 7094 7095 u8 reserved_at_20[0x10]; 7096 u8 op_mod[0x10]; 7097 7098 u8 reserved_at_40[0x10]; 7099 u8 vport_num[0x10]; 7100 7101 u8 reserved_at_60[0x20]; 7102 }; 7103 7104 struct mlx5_ifc_modify_esw_vport_context_out_bits { 7105 u8 status[0x8]; 7106 u8 reserved_at_8[0x18]; 7107 7108 u8 syndrome[0x20]; 7109 7110 u8 reserved_at_40[0x40]; 7111 }; 7112 7113 struct mlx5_ifc_esw_vport_context_fields_select_bits { 7114 u8 reserved_at_0[0x1b]; 7115 u8 fdb_to_vport_reg_c_id[0x1]; 7116 u8 vport_cvlan_insert[0x1]; 7117 u8 vport_svlan_insert[0x1]; 7118 u8 vport_cvlan_strip[0x1]; 7119 u8 vport_svlan_strip[0x1]; 7120 }; 7121 7122 struct mlx5_ifc_modify_esw_vport_context_in_bits { 7123 u8 opcode[0x10]; 7124 u8 reserved_at_10[0x10]; 7125 7126 u8 reserved_at_20[0x10]; 7127 u8 op_mod[0x10]; 7128 7129 u8 other_vport[0x1]; 7130 u8 reserved_at_41[0xf]; 7131 u8 vport_number[0x10]; 7132 7133 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select; 7134 7135 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 7136 }; 7137 7138 struct mlx5_ifc_query_eq_out_bits { 7139 u8 status[0x8]; 7140 u8 reserved_at_8[0x18]; 7141 7142 u8 syndrome[0x20]; 7143 7144 u8 reserved_at_40[0x40]; 7145 7146 struct mlx5_ifc_eqc_bits eq_context_entry; 7147 7148 u8 reserved_at_280[0x40]; 7149 7150 u8 event_bitmask[0x40]; 7151 7152 u8 reserved_at_300[0x580]; 7153 7154 u8 pas[][0x40]; 7155 }; 7156 7157 struct mlx5_ifc_query_eq_in_bits { 7158 u8 opcode[0x10]; 7159 u8 reserved_at_10[0x10]; 7160 7161 u8 reserved_at_20[0x10]; 7162 u8 op_mod[0x10]; 7163 7164 u8 reserved_at_40[0x18]; 7165 u8 eq_number[0x8]; 7166 7167 u8 reserved_at_60[0x20]; 7168 }; 7169 7170 struct mlx5_ifc_packet_reformat_context_in_bits { 7171 u8 reformat_type[0x8]; 7172 u8 reserved_at_8[0x4]; 7173 u8 reformat_param_0[0x4]; 7174 u8 reserved_at_10[0x6]; 7175 u8 reformat_data_size[0xa]; 7176 7177 u8 reformat_param_1[0x8]; 7178 u8 reserved_at_28[0x8]; 7179 u8 reformat_data[2][0x8]; 7180 7181 u8 more_reformat_data[][0x8]; 7182 }; 7183 7184 struct mlx5_ifc_query_packet_reformat_context_out_bits { 7185 u8 status[0x8]; 7186 u8 reserved_at_8[0x18]; 7187 7188 u8 syndrome[0x20]; 7189 7190 u8 reserved_at_40[0xa0]; 7191 7192 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context[]; 7193 }; 7194 7195 struct mlx5_ifc_query_packet_reformat_context_in_bits { 7196 u8 opcode[0x10]; 7197 u8 reserved_at_10[0x10]; 7198 7199 u8 reserved_at_20[0x10]; 7200 u8 op_mod[0x10]; 7201 7202 u8 packet_reformat_id[0x20]; 7203 7204 u8 reserved_at_60[0xa0]; 7205 }; 7206 7207 struct mlx5_ifc_alloc_packet_reformat_context_out_bits { 7208 u8 status[0x8]; 7209 u8 reserved_at_8[0x18]; 7210 7211 u8 syndrome[0x20]; 7212 7213 u8 packet_reformat_id[0x20]; 7214 7215 u8 reserved_at_60[0x20]; 7216 }; 7217 7218 enum { 7219 MLX5_REFORMAT_CONTEXT_ANCHOR_MAC_START = 0x1, 7220 MLX5_REFORMAT_CONTEXT_ANCHOR_VLAN_START = 0x2, 7221 MLX5_REFORMAT_CONTEXT_ANCHOR_IP_START = 0x7, 7222 MLX5_REFORMAT_CONTEXT_ANCHOR_TCP_UDP_START = 0x9, 7223 }; 7224 7225 enum mlx5_reformat_ctx_type { 7226 MLX5_REFORMAT_TYPE_L2_TO_VXLAN = 0x0, 7227 MLX5_REFORMAT_TYPE_L2_TO_NVGRE = 0x1, 7228 MLX5_REFORMAT_TYPE_L2_TO_L2_TUNNEL = 0x2, 7229 MLX5_REFORMAT_TYPE_L3_TUNNEL_TO_L2 = 0x3, 7230 MLX5_REFORMAT_TYPE_L2_TO_L3_TUNNEL = 0x4, 7231 MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_IPV4 = 0x5, 7232 MLX5_REFORMAT_TYPE_L2_TO_L3_ESP_TUNNEL = 0x6, 7233 MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_UDPV4 = 0x7, 7234 MLX5_REFORMAT_TYPE_DEL_ESP_TRANSPORT = 0x8, 7235 MLX5_REFORMAT_TYPE_L3_ESP_TUNNEL_TO_L2 = 0x9, 7236 MLX5_REFORMAT_TYPE_DEL_ESP_TRANSPORT_OVER_UDP = 0xa, 7237 MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_IPV6 = 0xb, 7238 MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_UDPV6 = 0xc, 7239 MLX5_REFORMAT_TYPE_ADD_PSP_TUNNEL = 0xd, 7240 MLX5_REFORMAT_TYPE_DEL_PSP_TUNNEL = 0xe, 7241 MLX5_REFORMAT_TYPE_INSERT_HDR = 0xf, 7242 MLX5_REFORMAT_TYPE_REMOVE_HDR = 0x10, 7243 MLX5_REFORMAT_TYPE_ADD_MACSEC = 0x11, 7244 MLX5_REFORMAT_TYPE_DEL_MACSEC = 0x12, 7245 }; 7246 7247 struct mlx5_ifc_alloc_packet_reformat_context_in_bits { 7248 u8 opcode[0x10]; 7249 u8 reserved_at_10[0x10]; 7250 7251 u8 reserved_at_20[0x10]; 7252 u8 op_mod[0x10]; 7253 7254 u8 reserved_at_40[0xa0]; 7255 7256 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context; 7257 }; 7258 7259 struct mlx5_ifc_dealloc_packet_reformat_context_out_bits { 7260 u8 status[0x8]; 7261 u8 reserved_at_8[0x18]; 7262 7263 u8 syndrome[0x20]; 7264 7265 u8 reserved_at_40[0x40]; 7266 }; 7267 7268 struct mlx5_ifc_dealloc_packet_reformat_context_in_bits { 7269 u8 opcode[0x10]; 7270 u8 reserved_at_10[0x10]; 7271 7272 u8 reserved_20[0x10]; 7273 u8 op_mod[0x10]; 7274 7275 u8 packet_reformat_id[0x20]; 7276 7277 u8 reserved_60[0x20]; 7278 }; 7279 7280 struct mlx5_ifc_set_action_in_bits { 7281 u8 action_type[0x4]; 7282 u8 field[0xc]; 7283 u8 reserved_at_10[0x3]; 7284 u8 offset[0x5]; 7285 u8 reserved_at_18[0x3]; 7286 u8 length[0x5]; 7287 7288 u8 data[0x20]; 7289 }; 7290 7291 struct mlx5_ifc_add_action_in_bits { 7292 u8 action_type[0x4]; 7293 u8 field[0xc]; 7294 u8 reserved_at_10[0x10]; 7295 7296 u8 data[0x20]; 7297 }; 7298 7299 struct mlx5_ifc_copy_action_in_bits { 7300 u8 action_type[0x4]; 7301 u8 src_field[0xc]; 7302 u8 reserved_at_10[0x3]; 7303 u8 src_offset[0x5]; 7304 u8 reserved_at_18[0x3]; 7305 u8 length[0x5]; 7306 7307 u8 reserved_at_20[0x4]; 7308 u8 dst_field[0xc]; 7309 u8 reserved_at_30[0x3]; 7310 u8 dst_offset[0x5]; 7311 u8 reserved_at_38[0x8]; 7312 }; 7313 7314 union mlx5_ifc_set_add_copy_action_in_auto_bits { 7315 struct mlx5_ifc_set_action_in_bits set_action_in; 7316 struct mlx5_ifc_add_action_in_bits add_action_in; 7317 struct mlx5_ifc_copy_action_in_bits copy_action_in; 7318 u8 reserved_at_0[0x40]; 7319 }; 7320 7321 enum { 7322 MLX5_ACTION_TYPE_SET = 0x1, 7323 MLX5_ACTION_TYPE_ADD = 0x2, 7324 MLX5_ACTION_TYPE_COPY = 0x3, 7325 }; 7326 7327 enum { 7328 MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16 = 0x1, 7329 MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0 = 0x2, 7330 MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE = 0x3, 7331 MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16 = 0x4, 7332 MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0 = 0x5, 7333 MLX5_ACTION_IN_FIELD_OUT_IP_DSCP = 0x6, 7334 MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS = 0x7, 7335 MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT = 0x8, 7336 MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT = 0x9, 7337 MLX5_ACTION_IN_FIELD_OUT_IP_TTL = 0xa, 7338 MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT = 0xb, 7339 MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT = 0xc, 7340 MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96 = 0xd, 7341 MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64 = 0xe, 7342 MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32 = 0xf, 7343 MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0 = 0x10, 7344 MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96 = 0x11, 7345 MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64 = 0x12, 7346 MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32 = 0x13, 7347 MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0 = 0x14, 7348 MLX5_ACTION_IN_FIELD_OUT_SIPV4 = 0x15, 7349 MLX5_ACTION_IN_FIELD_OUT_DIPV4 = 0x16, 7350 MLX5_ACTION_IN_FIELD_OUT_FIRST_VID = 0x17, 7351 MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47, 7352 MLX5_ACTION_IN_FIELD_METADATA_REG_A = 0x49, 7353 MLX5_ACTION_IN_FIELD_METADATA_REG_B = 0x50, 7354 MLX5_ACTION_IN_FIELD_METADATA_REG_C_0 = 0x51, 7355 MLX5_ACTION_IN_FIELD_METADATA_REG_C_1 = 0x52, 7356 MLX5_ACTION_IN_FIELD_METADATA_REG_C_2 = 0x53, 7357 MLX5_ACTION_IN_FIELD_METADATA_REG_C_3 = 0x54, 7358 MLX5_ACTION_IN_FIELD_METADATA_REG_C_4 = 0x55, 7359 MLX5_ACTION_IN_FIELD_METADATA_REG_C_5 = 0x56, 7360 MLX5_ACTION_IN_FIELD_METADATA_REG_C_6 = 0x57, 7361 MLX5_ACTION_IN_FIELD_METADATA_REG_C_7 = 0x58, 7362 MLX5_ACTION_IN_FIELD_OUT_TCP_SEQ_NUM = 0x59, 7363 MLX5_ACTION_IN_FIELD_OUT_TCP_ACK_NUM = 0x5B, 7364 MLX5_ACTION_IN_FIELD_IPSEC_SYNDROME = 0x5D, 7365 MLX5_ACTION_IN_FIELD_OUT_EMD_47_32 = 0x6F, 7366 MLX5_ACTION_IN_FIELD_OUT_EMD_31_0 = 0x70, 7367 MLX5_ACTION_IN_FIELD_PSP_SYNDROME = 0x71, 7368 }; 7369 7370 struct mlx5_ifc_alloc_modify_header_context_out_bits { 7371 u8 status[0x8]; 7372 u8 reserved_at_8[0x18]; 7373 7374 u8 syndrome[0x20]; 7375 7376 u8 modify_header_id[0x20]; 7377 7378 u8 reserved_at_60[0x20]; 7379 }; 7380 7381 struct mlx5_ifc_alloc_modify_header_context_in_bits { 7382 u8 opcode[0x10]; 7383 u8 reserved_at_10[0x10]; 7384 7385 u8 reserved_at_20[0x10]; 7386 u8 op_mod[0x10]; 7387 7388 u8 reserved_at_40[0x20]; 7389 7390 u8 table_type[0x8]; 7391 u8 reserved_at_68[0x10]; 7392 u8 num_of_actions[0x8]; 7393 7394 union mlx5_ifc_set_add_copy_action_in_auto_bits actions[]; 7395 }; 7396 7397 struct mlx5_ifc_dealloc_modify_header_context_out_bits { 7398 u8 status[0x8]; 7399 u8 reserved_at_8[0x18]; 7400 7401 u8 syndrome[0x20]; 7402 7403 u8 reserved_at_40[0x40]; 7404 }; 7405 7406 struct mlx5_ifc_dealloc_modify_header_context_in_bits { 7407 u8 opcode[0x10]; 7408 u8 reserved_at_10[0x10]; 7409 7410 u8 reserved_at_20[0x10]; 7411 u8 op_mod[0x10]; 7412 7413 u8 modify_header_id[0x20]; 7414 7415 u8 reserved_at_60[0x20]; 7416 }; 7417 7418 struct mlx5_ifc_query_modify_header_context_in_bits { 7419 u8 opcode[0x10]; 7420 u8 uid[0x10]; 7421 7422 u8 reserved_at_20[0x10]; 7423 u8 op_mod[0x10]; 7424 7425 u8 modify_header_id[0x20]; 7426 7427 u8 reserved_at_60[0xa0]; 7428 }; 7429 7430 struct mlx5_ifc_query_dct_out_bits { 7431 u8 status[0x8]; 7432 u8 reserved_at_8[0x18]; 7433 7434 u8 syndrome[0x20]; 7435 7436 u8 reserved_at_40[0x40]; 7437 7438 struct mlx5_ifc_dctc_bits dct_context_entry; 7439 7440 u8 reserved_at_280[0x180]; 7441 }; 7442 7443 struct mlx5_ifc_query_dct_in_bits { 7444 u8 opcode[0x10]; 7445 u8 reserved_at_10[0x10]; 7446 7447 u8 reserved_at_20[0x10]; 7448 u8 op_mod[0x10]; 7449 7450 u8 reserved_at_40[0x8]; 7451 u8 dctn[0x18]; 7452 7453 u8 reserved_at_60[0x20]; 7454 }; 7455 7456 struct mlx5_ifc_query_cq_out_bits { 7457 u8 status[0x8]; 7458 u8 reserved_at_8[0x18]; 7459 7460 u8 syndrome[0x20]; 7461 7462 u8 reserved_at_40[0x40]; 7463 7464 struct mlx5_ifc_cqc_bits cq_context; 7465 7466 u8 reserved_at_280[0x600]; 7467 7468 u8 pas[][0x40]; 7469 }; 7470 7471 struct mlx5_ifc_query_cq_in_bits { 7472 u8 opcode[0x10]; 7473 u8 reserved_at_10[0x10]; 7474 7475 u8 reserved_at_20[0x10]; 7476 u8 op_mod[0x10]; 7477 7478 u8 reserved_at_40[0x8]; 7479 u8 cqn[0x18]; 7480 7481 u8 reserved_at_60[0x20]; 7482 }; 7483 7484 struct mlx5_ifc_query_cong_status_out_bits { 7485 u8 status[0x8]; 7486 u8 reserved_at_8[0x18]; 7487 7488 u8 syndrome[0x20]; 7489 7490 u8 reserved_at_40[0x20]; 7491 7492 u8 enable[0x1]; 7493 u8 tag_enable[0x1]; 7494 u8 reserved_at_62[0x1e]; 7495 }; 7496 7497 struct mlx5_ifc_query_cong_status_in_bits { 7498 u8 opcode[0x10]; 7499 u8 reserved_at_10[0x10]; 7500 7501 u8 reserved_at_20[0x10]; 7502 u8 op_mod[0x10]; 7503 7504 u8 reserved_at_40[0x18]; 7505 u8 priority[0x4]; 7506 u8 cong_protocol[0x4]; 7507 7508 u8 reserved_at_60[0x20]; 7509 }; 7510 7511 struct mlx5_ifc_query_cong_statistics_out_bits { 7512 u8 status[0x8]; 7513 u8 reserved_at_8[0x18]; 7514 7515 u8 syndrome[0x20]; 7516 7517 u8 reserved_at_40[0x40]; 7518 7519 u8 rp_cur_flows[0x20]; 7520 7521 u8 sum_flows[0x20]; 7522 7523 u8 rp_cnp_ignored_high[0x20]; 7524 7525 u8 rp_cnp_ignored_low[0x20]; 7526 7527 u8 rp_cnp_handled_high[0x20]; 7528 7529 u8 rp_cnp_handled_low[0x20]; 7530 7531 u8 reserved_at_140[0x100]; 7532 7533 u8 time_stamp_high[0x20]; 7534 7535 u8 time_stamp_low[0x20]; 7536 7537 u8 accumulators_period[0x20]; 7538 7539 u8 np_ecn_marked_roce_packets_high[0x20]; 7540 7541 u8 np_ecn_marked_roce_packets_low[0x20]; 7542 7543 u8 np_cnp_sent_high[0x20]; 7544 7545 u8 np_cnp_sent_low[0x20]; 7546 7547 u8 reserved_at_320[0x560]; 7548 }; 7549 7550 struct mlx5_ifc_query_cong_statistics_in_bits { 7551 u8 opcode[0x10]; 7552 u8 reserved_at_10[0x10]; 7553 7554 u8 reserved_at_20[0x10]; 7555 u8 op_mod[0x10]; 7556 7557 u8 clear[0x1]; 7558 u8 reserved_at_41[0x1f]; 7559 7560 u8 reserved_at_60[0x20]; 7561 }; 7562 7563 struct mlx5_ifc_query_cong_params_out_bits { 7564 u8 status[0x8]; 7565 u8 reserved_at_8[0x18]; 7566 7567 u8 syndrome[0x20]; 7568 7569 u8 reserved_at_40[0x40]; 7570 7571 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 7572 }; 7573 7574 struct mlx5_ifc_query_cong_params_in_bits { 7575 u8 opcode[0x10]; 7576 u8 reserved_at_10[0x10]; 7577 7578 u8 reserved_at_20[0x10]; 7579 u8 op_mod[0x10]; 7580 7581 u8 reserved_at_40[0x1c]; 7582 u8 cong_protocol[0x4]; 7583 7584 u8 reserved_at_60[0x20]; 7585 }; 7586 7587 struct mlx5_ifc_query_adapter_out_bits { 7588 u8 status[0x8]; 7589 u8 reserved_at_8[0x18]; 7590 7591 u8 syndrome[0x20]; 7592 7593 u8 reserved_at_40[0x40]; 7594 7595 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct; 7596 }; 7597 7598 struct mlx5_ifc_query_adapter_in_bits { 7599 u8 opcode[0x10]; 7600 u8 reserved_at_10[0x10]; 7601 7602 u8 reserved_at_20[0x10]; 7603 u8 op_mod[0x10]; 7604 7605 u8 reserved_at_40[0x40]; 7606 }; 7607 7608 struct mlx5_ifc_function_vhca_rid_info_reg_bits { 7609 u8 host_number[0x8]; 7610 u8 host_pci_device_function[0x8]; 7611 u8 host_pci_bus[0x8]; 7612 u8 reserved_at_18[0x3]; 7613 u8 pci_bus_assigned[0x1]; 7614 u8 function_type[0x4]; 7615 7616 u8 parent_pci_device_function[0x8]; 7617 u8 parent_pci_bus[0x8]; 7618 u8 vhca_id[0x10]; 7619 7620 u8 reserved_at_40[0x10]; 7621 u8 function_id[0x10]; 7622 7623 u8 reserved_at_60[0x20]; 7624 }; 7625 7626 struct mlx5_ifc_delegated_function_vhca_rid_info_bits { 7627 struct mlx5_ifc_function_vhca_rid_info_reg_bits function_vhca_rid_info; 7628 7629 u8 reserved_at_80[0x18]; 7630 u8 manage_profile[0x8]; 7631 7632 u8 reserved_at_a0[0x60]; 7633 }; 7634 7635 struct mlx5_ifc_query_delegated_vhca_out_bits { 7636 u8 status[0x8]; 7637 u8 reserved_at_8[0x18]; 7638 7639 u8 syndrome[0x20]; 7640 7641 u8 reserved_at_40[0x20]; 7642 7643 u8 reserved_at_60[0x10]; 7644 u8 functions_count[0x10]; 7645 7646 u8 reserved_at_80[0x80]; 7647 7648 struct mlx5_ifc_delegated_function_vhca_rid_info_bits 7649 delegated_function_vhca_rid_info[]; 7650 }; 7651 7652 struct mlx5_ifc_query_delegated_vhca_in_bits { 7653 u8 opcode[0x10]; 7654 u8 uid[0x10]; 7655 7656 u8 reserved_at_20[0x10]; 7657 u8 op_mod[0x10]; 7658 7659 u8 reserved_at_40[0x40]; 7660 }; 7661 7662 struct mlx5_ifc_create_esw_vport_out_bits { 7663 u8 status[0x8]; 7664 u8 reserved_at_8[0x18]; 7665 7666 u8 syndrome[0x20]; 7667 7668 u8 reserved_at_40[0x20]; 7669 7670 u8 reserved_at_60[0x10]; 7671 u8 vport_num[0x10]; 7672 }; 7673 7674 struct mlx5_ifc_create_esw_vport_in_bits { 7675 u8 opcode[0x10]; 7676 u8 reserved_at_10[0x10]; 7677 7678 u8 reserved_at_20[0x10]; 7679 u8 op_mod[0x10]; 7680 7681 u8 reserved_at_40[0x10]; 7682 u8 managed_vhca_id[0x10]; 7683 7684 u8 reserved_at_60[0x20]; 7685 }; 7686 7687 struct mlx5_ifc_qp_2rst_out_bits { 7688 u8 status[0x8]; 7689 u8 reserved_at_8[0x18]; 7690 7691 u8 syndrome[0x20]; 7692 7693 u8 reserved_at_40[0x40]; 7694 }; 7695 7696 struct mlx5_ifc_qp_2rst_in_bits { 7697 u8 opcode[0x10]; 7698 u8 uid[0x10]; 7699 7700 u8 reserved_at_20[0x10]; 7701 u8 op_mod[0x10]; 7702 7703 u8 reserved_at_40[0x8]; 7704 u8 qpn[0x18]; 7705 7706 u8 reserved_at_60[0x20]; 7707 }; 7708 7709 struct mlx5_ifc_qp_2err_out_bits { 7710 u8 status[0x8]; 7711 u8 reserved_at_8[0x18]; 7712 7713 u8 syndrome[0x20]; 7714 7715 u8 reserved_at_40[0x40]; 7716 }; 7717 7718 struct mlx5_ifc_qp_2err_in_bits { 7719 u8 opcode[0x10]; 7720 u8 uid[0x10]; 7721 7722 u8 reserved_at_20[0x10]; 7723 u8 op_mod[0x10]; 7724 7725 u8 reserved_at_40[0x8]; 7726 u8 qpn[0x18]; 7727 7728 u8 reserved_at_60[0x20]; 7729 }; 7730 7731 struct mlx5_ifc_trans_page_fault_info_bits { 7732 u8 error[0x1]; 7733 u8 reserved_at_1[0x4]; 7734 u8 page_fault_type[0x3]; 7735 u8 wq_number[0x18]; 7736 7737 u8 reserved_at_20[0x8]; 7738 u8 fault_token[0x18]; 7739 }; 7740 7741 struct mlx5_ifc_mem_page_fault_info_bits { 7742 u8 error[0x1]; 7743 u8 reserved_at_1[0xf]; 7744 u8 fault_token_47_32[0x10]; 7745 7746 u8 fault_token_31_0[0x20]; 7747 }; 7748 7749 union mlx5_ifc_page_fault_resume_in_page_fault_info_auto_bits { 7750 struct mlx5_ifc_trans_page_fault_info_bits trans_page_fault_info; 7751 struct mlx5_ifc_mem_page_fault_info_bits mem_page_fault_info; 7752 u8 reserved_at_0[0x40]; 7753 }; 7754 7755 struct mlx5_ifc_page_fault_resume_out_bits { 7756 u8 status[0x8]; 7757 u8 reserved_at_8[0x18]; 7758 7759 u8 syndrome[0x20]; 7760 7761 u8 reserved_at_40[0x40]; 7762 }; 7763 7764 struct mlx5_ifc_page_fault_resume_in_bits { 7765 u8 opcode[0x10]; 7766 u8 reserved_at_10[0x10]; 7767 7768 u8 reserved_at_20[0x10]; 7769 u8 op_mod[0x10]; 7770 7771 union mlx5_ifc_page_fault_resume_in_page_fault_info_auto_bits 7772 page_fault_info; 7773 }; 7774 7775 struct mlx5_ifc_nop_out_bits { 7776 u8 status[0x8]; 7777 u8 reserved_at_8[0x18]; 7778 7779 u8 syndrome[0x20]; 7780 7781 u8 reserved_at_40[0x40]; 7782 }; 7783 7784 struct mlx5_ifc_nop_in_bits { 7785 u8 opcode[0x10]; 7786 u8 reserved_at_10[0x10]; 7787 7788 u8 reserved_at_20[0x10]; 7789 u8 op_mod[0x10]; 7790 7791 u8 reserved_at_40[0x40]; 7792 }; 7793 7794 struct mlx5_ifc_modify_vport_state_out_bits { 7795 u8 status[0x8]; 7796 u8 reserved_at_8[0x18]; 7797 7798 u8 syndrome[0x20]; 7799 7800 u8 reserved_at_40[0x40]; 7801 }; 7802 7803 struct mlx5_ifc_modify_vport_state_in_bits { 7804 u8 opcode[0x10]; 7805 u8 reserved_at_10[0x10]; 7806 7807 u8 reserved_at_20[0x10]; 7808 u8 op_mod[0x10]; 7809 7810 u8 other_vport[0x1]; 7811 u8 reserved_at_41[0xf]; 7812 u8 vport_number[0x10]; 7813 7814 u8 max_tx_speed[0x10]; 7815 u8 ingress_connect[0x1]; 7816 u8 egress_connect[0x1]; 7817 u8 ingress_connect_valid[0x1]; 7818 u8 egress_connect_valid[0x1]; 7819 u8 reserved_at_74[0x4]; 7820 u8 admin_state[0x4]; 7821 u8 reserved_at_7c[0x4]; 7822 }; 7823 7824 struct mlx5_ifc_modify_tis_out_bits { 7825 u8 status[0x8]; 7826 u8 reserved_at_8[0x18]; 7827 7828 u8 syndrome[0x20]; 7829 7830 u8 reserved_at_40[0x40]; 7831 }; 7832 7833 struct mlx5_ifc_modify_tis_bitmask_bits { 7834 u8 reserved_at_0[0x20]; 7835 7836 u8 reserved_at_20[0x1d]; 7837 u8 lag_tx_port_affinity[0x1]; 7838 u8 strict_lag_tx_port_affinity[0x1]; 7839 u8 prio[0x1]; 7840 }; 7841 7842 struct mlx5_ifc_modify_tis_in_bits { 7843 u8 opcode[0x10]; 7844 u8 uid[0x10]; 7845 7846 u8 reserved_at_20[0x10]; 7847 u8 op_mod[0x10]; 7848 7849 u8 reserved_at_40[0x8]; 7850 u8 tisn[0x18]; 7851 7852 u8 reserved_at_60[0x20]; 7853 7854 struct mlx5_ifc_modify_tis_bitmask_bits bitmask; 7855 7856 u8 reserved_at_c0[0x40]; 7857 7858 struct mlx5_ifc_tisc_bits ctx; 7859 }; 7860 7861 struct mlx5_ifc_modify_tir_bitmask_bits { 7862 u8 reserved_at_0[0x20]; 7863 7864 u8 reserved_at_20[0x1b]; 7865 u8 self_lb_en[0x1]; 7866 u8 reserved_at_3c[0x1]; 7867 u8 hash[0x1]; 7868 u8 reserved_at_3e[0x1]; 7869 u8 packet_merge[0x1]; 7870 }; 7871 7872 struct mlx5_ifc_modify_tir_out_bits { 7873 u8 status[0x8]; 7874 u8 reserved_at_8[0x18]; 7875 7876 u8 syndrome[0x20]; 7877 7878 u8 reserved_at_40[0x40]; 7879 }; 7880 7881 struct mlx5_ifc_modify_tir_in_bits { 7882 u8 opcode[0x10]; 7883 u8 uid[0x10]; 7884 7885 u8 reserved_at_20[0x10]; 7886 u8 op_mod[0x10]; 7887 7888 u8 reserved_at_40[0x8]; 7889 u8 tirn[0x18]; 7890 7891 u8 reserved_at_60[0x20]; 7892 7893 struct mlx5_ifc_modify_tir_bitmask_bits bitmask; 7894 7895 u8 reserved_at_c0[0x40]; 7896 7897 struct mlx5_ifc_tirc_bits ctx; 7898 }; 7899 7900 struct mlx5_ifc_modify_sq_out_bits { 7901 u8 status[0x8]; 7902 u8 reserved_at_8[0x18]; 7903 7904 u8 syndrome[0x20]; 7905 7906 u8 reserved_at_40[0x40]; 7907 }; 7908 7909 struct mlx5_ifc_modify_sq_in_bits { 7910 u8 opcode[0x10]; 7911 u8 uid[0x10]; 7912 7913 u8 reserved_at_20[0x10]; 7914 u8 op_mod[0x10]; 7915 7916 u8 sq_state[0x4]; 7917 u8 reserved_at_44[0x4]; 7918 u8 sqn[0x18]; 7919 7920 u8 reserved_at_60[0x20]; 7921 7922 u8 modify_bitmask[0x40]; 7923 7924 u8 reserved_at_c0[0x40]; 7925 7926 struct mlx5_ifc_sqc_bits ctx; 7927 }; 7928 7929 struct mlx5_ifc_modify_scheduling_element_out_bits { 7930 u8 status[0x8]; 7931 u8 reserved_at_8[0x18]; 7932 7933 u8 syndrome[0x20]; 7934 7935 u8 reserved_at_40[0x1c0]; 7936 }; 7937 7938 enum { 7939 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1, 7940 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2, 7941 }; 7942 7943 struct mlx5_ifc_modify_scheduling_element_in_bits { 7944 u8 opcode[0x10]; 7945 u8 reserved_at_10[0x10]; 7946 7947 u8 reserved_at_20[0x10]; 7948 u8 op_mod[0x10]; 7949 7950 u8 scheduling_hierarchy[0x8]; 7951 u8 reserved_at_48[0x18]; 7952 7953 u8 scheduling_element_id[0x20]; 7954 7955 u8 reserved_at_80[0x20]; 7956 7957 u8 modify_bitmask[0x20]; 7958 7959 u8 reserved_at_c0[0x40]; 7960 7961 struct mlx5_ifc_scheduling_context_bits scheduling_context; 7962 7963 u8 reserved_at_300[0x100]; 7964 }; 7965 7966 struct mlx5_ifc_modify_rqt_out_bits { 7967 u8 status[0x8]; 7968 u8 reserved_at_8[0x18]; 7969 7970 u8 syndrome[0x20]; 7971 7972 u8 reserved_at_40[0x40]; 7973 }; 7974 7975 struct mlx5_ifc_rqt_bitmask_bits { 7976 u8 reserved_at_0[0x20]; 7977 7978 u8 reserved_at_20[0x1f]; 7979 u8 rqn_list[0x1]; 7980 }; 7981 7982 struct mlx5_ifc_modify_rqt_in_bits { 7983 u8 opcode[0x10]; 7984 u8 uid[0x10]; 7985 7986 u8 reserved_at_20[0x10]; 7987 u8 op_mod[0x10]; 7988 7989 u8 reserved_at_40[0x8]; 7990 u8 rqtn[0x18]; 7991 7992 u8 reserved_at_60[0x20]; 7993 7994 struct mlx5_ifc_rqt_bitmask_bits bitmask; 7995 7996 u8 reserved_at_c0[0x40]; 7997 7998 struct mlx5_ifc_rqtc_bits ctx; 7999 }; 8000 8001 struct mlx5_ifc_modify_rq_out_bits { 8002 u8 status[0x8]; 8003 u8 reserved_at_8[0x18]; 8004 8005 u8 syndrome[0x20]; 8006 8007 u8 reserved_at_40[0x40]; 8008 }; 8009 8010 enum { 8011 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1, 8012 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2, 8013 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3, 8014 }; 8015 8016 struct mlx5_ifc_modify_rq_in_bits { 8017 u8 opcode[0x10]; 8018 u8 uid[0x10]; 8019 8020 u8 reserved_at_20[0x10]; 8021 u8 op_mod[0x10]; 8022 8023 u8 rq_state[0x4]; 8024 u8 reserved_at_44[0x4]; 8025 u8 rqn[0x18]; 8026 8027 u8 reserved_at_60[0x20]; 8028 8029 u8 modify_bitmask[0x40]; 8030 8031 u8 reserved_at_c0[0x40]; 8032 8033 struct mlx5_ifc_rqc_bits ctx; 8034 }; 8035 8036 struct mlx5_ifc_modify_rmp_out_bits { 8037 u8 status[0x8]; 8038 u8 reserved_at_8[0x18]; 8039 8040 u8 syndrome[0x20]; 8041 8042 u8 reserved_at_40[0x40]; 8043 }; 8044 8045 struct mlx5_ifc_rmp_bitmask_bits { 8046 u8 reserved_at_0[0x20]; 8047 8048 u8 reserved_at_20[0x1f]; 8049 u8 lwm[0x1]; 8050 }; 8051 8052 struct mlx5_ifc_modify_rmp_in_bits { 8053 u8 opcode[0x10]; 8054 u8 uid[0x10]; 8055 8056 u8 reserved_at_20[0x10]; 8057 u8 op_mod[0x10]; 8058 8059 u8 rmp_state[0x4]; 8060 u8 reserved_at_44[0x4]; 8061 u8 rmpn[0x18]; 8062 8063 u8 reserved_at_60[0x20]; 8064 8065 struct mlx5_ifc_rmp_bitmask_bits bitmask; 8066 8067 u8 reserved_at_c0[0x40]; 8068 8069 struct mlx5_ifc_rmpc_bits ctx; 8070 }; 8071 8072 struct mlx5_ifc_modify_nic_vport_context_out_bits { 8073 u8 status[0x8]; 8074 u8 reserved_at_8[0x18]; 8075 8076 u8 syndrome[0x20]; 8077 8078 u8 reserved_at_40[0x40]; 8079 }; 8080 8081 struct mlx5_ifc_modify_nic_vport_field_select_bits { 8082 u8 reserved_at_0[0x12]; 8083 u8 affiliation[0x1]; 8084 u8 reserved_at_13[0x1]; 8085 u8 disable_uc_local_lb[0x1]; 8086 u8 disable_mc_local_lb[0x1]; 8087 u8 node_guid[0x1]; 8088 u8 port_guid[0x1]; 8089 u8 min_inline[0x1]; 8090 u8 mtu[0x1]; 8091 u8 change_event[0x1]; 8092 u8 promisc[0x1]; 8093 u8 permanent_address[0x1]; 8094 u8 addresses_list[0x1]; 8095 u8 roce_en[0x1]; 8096 u8 reserved_at_1f[0x1]; 8097 }; 8098 8099 struct mlx5_ifc_modify_nic_vport_context_in_bits { 8100 u8 opcode[0x10]; 8101 u8 reserved_at_10[0x10]; 8102 8103 u8 reserved_at_20[0x10]; 8104 u8 op_mod[0x10]; 8105 8106 u8 other_vport[0x1]; 8107 u8 reserved_at_41[0xf]; 8108 u8 vport_number[0x10]; 8109 8110 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select; 8111 8112 u8 reserved_at_80[0x780]; 8113 8114 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 8115 }; 8116 8117 struct mlx5_ifc_modify_hca_vport_context_out_bits { 8118 u8 status[0x8]; 8119 u8 reserved_at_8[0x18]; 8120 8121 u8 syndrome[0x20]; 8122 8123 u8 reserved_at_40[0x40]; 8124 }; 8125 8126 struct mlx5_ifc_modify_hca_vport_context_in_bits { 8127 u8 opcode[0x10]; 8128 u8 reserved_at_10[0x10]; 8129 8130 u8 reserved_at_20[0x10]; 8131 u8 op_mod[0x10]; 8132 8133 u8 other_vport[0x1]; 8134 u8 reserved_at_41[0xb]; 8135 u8 port_num[0x4]; 8136 u8 vport_number[0x10]; 8137 8138 u8 reserved_at_60[0x20]; 8139 8140 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 8141 }; 8142 8143 struct mlx5_ifc_modify_cq_out_bits { 8144 u8 status[0x8]; 8145 u8 reserved_at_8[0x18]; 8146 8147 u8 syndrome[0x20]; 8148 8149 u8 reserved_at_40[0x40]; 8150 }; 8151 8152 enum { 8153 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0, 8154 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1, 8155 }; 8156 8157 struct mlx5_ifc_modify_cq_in_bits { 8158 u8 opcode[0x10]; 8159 u8 uid[0x10]; 8160 8161 u8 reserved_at_20[0x10]; 8162 u8 op_mod[0x10]; 8163 8164 u8 reserved_at_40[0x8]; 8165 u8 cqn[0x18]; 8166 8167 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select; 8168 8169 struct mlx5_ifc_cqc_bits cq_context; 8170 8171 u8 reserved_at_280[0x60]; 8172 8173 u8 cq_umem_valid[0x1]; 8174 u8 reserved_at_2e1[0x1f]; 8175 8176 u8 reserved_at_300[0x580]; 8177 8178 u8 pas[][0x40]; 8179 }; 8180 8181 struct mlx5_ifc_modify_cong_status_out_bits { 8182 u8 status[0x8]; 8183 u8 reserved_at_8[0x18]; 8184 8185 u8 syndrome[0x20]; 8186 8187 u8 reserved_at_40[0x40]; 8188 }; 8189 8190 struct mlx5_ifc_modify_cong_status_in_bits { 8191 u8 opcode[0x10]; 8192 u8 reserved_at_10[0x10]; 8193 8194 u8 reserved_at_20[0x10]; 8195 u8 op_mod[0x10]; 8196 8197 u8 reserved_at_40[0x18]; 8198 u8 priority[0x4]; 8199 u8 cong_protocol[0x4]; 8200 8201 u8 enable[0x1]; 8202 u8 tag_enable[0x1]; 8203 u8 reserved_at_62[0x1e]; 8204 }; 8205 8206 struct mlx5_ifc_modify_cong_params_out_bits { 8207 u8 status[0x8]; 8208 u8 reserved_at_8[0x18]; 8209 8210 u8 syndrome[0x20]; 8211 8212 u8 reserved_at_40[0x40]; 8213 }; 8214 8215 struct mlx5_ifc_modify_cong_params_in_bits { 8216 u8 opcode[0x10]; 8217 u8 reserved_at_10[0x10]; 8218 8219 u8 reserved_at_20[0x10]; 8220 u8 op_mod[0x10]; 8221 8222 u8 reserved_at_40[0x1c]; 8223 u8 cong_protocol[0x4]; 8224 8225 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select; 8226 8227 u8 reserved_at_80[0x80]; 8228 8229 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 8230 }; 8231 8232 struct mlx5_ifc_manage_pages_out_bits { 8233 u8 status[0x8]; 8234 u8 reserved_at_8[0x18]; 8235 8236 u8 syndrome[0x20]; 8237 8238 u8 output_num_entries[0x20]; 8239 8240 u8 reserved_at_60[0x20]; 8241 8242 u8 pas[][0x40]; 8243 }; 8244 8245 enum { 8246 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL = 0x0, 8247 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS = 0x1, 8248 MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES = 0x2, 8249 }; 8250 8251 struct mlx5_ifc_manage_pages_in_bits { 8252 u8 opcode[0x10]; 8253 u8 reserved_at_10[0x10]; 8254 8255 u8 reserved_at_20[0x10]; 8256 u8 op_mod[0x10]; 8257 8258 u8 embedded_cpu_function[0x1]; 8259 u8 reserved_at_41[0xf]; 8260 u8 function_id[0x10]; 8261 8262 u8 input_num_entries[0x20]; 8263 8264 u8 pas[][0x40]; 8265 }; 8266 8267 struct mlx5_ifc_mad_ifc_out_bits { 8268 u8 status[0x8]; 8269 u8 reserved_at_8[0x18]; 8270 8271 u8 syndrome[0x20]; 8272 8273 u8 reserved_at_40[0x40]; 8274 8275 u8 response_mad_packet[256][0x8]; 8276 }; 8277 8278 struct mlx5_ifc_mad_ifc_in_bits { 8279 u8 opcode[0x10]; 8280 u8 reserved_at_10[0x10]; 8281 8282 u8 reserved_at_20[0x10]; 8283 u8 op_mod[0x10]; 8284 8285 u8 remote_lid[0x10]; 8286 u8 plane_index[0x8]; 8287 u8 port[0x8]; 8288 8289 u8 reserved_at_60[0x20]; 8290 8291 u8 mad[256][0x8]; 8292 }; 8293 8294 struct mlx5_ifc_init_hca_out_bits { 8295 u8 status[0x8]; 8296 u8 reserved_at_8[0x18]; 8297 8298 u8 syndrome[0x20]; 8299 8300 u8 reserved_at_40[0x40]; 8301 }; 8302 8303 struct mlx5_ifc_init_hca_in_bits { 8304 u8 opcode[0x10]; 8305 u8 reserved_at_10[0x10]; 8306 8307 u8 reserved_at_20[0x10]; 8308 u8 op_mod[0x10]; 8309 8310 u8 reserved_at_40[0x20]; 8311 8312 u8 reserved_at_60[0x2]; 8313 u8 sw_vhca_id[0xe]; 8314 u8 reserved_at_70[0x10]; 8315 8316 u8 sw_owner_id[4][0x20]; 8317 }; 8318 8319 struct mlx5_ifc_init2rtr_qp_out_bits { 8320 u8 status[0x8]; 8321 u8 reserved_at_8[0x18]; 8322 8323 u8 syndrome[0x20]; 8324 8325 u8 reserved_at_40[0x20]; 8326 u8 ece[0x20]; 8327 }; 8328 8329 struct mlx5_ifc_init2rtr_qp_in_bits { 8330 u8 opcode[0x10]; 8331 u8 uid[0x10]; 8332 8333 u8 reserved_at_20[0x10]; 8334 u8 op_mod[0x10]; 8335 8336 u8 reserved_at_40[0x8]; 8337 u8 qpn[0x18]; 8338 8339 u8 reserved_at_60[0x20]; 8340 8341 u8 opt_param_mask[0x20]; 8342 8343 u8 ece[0x20]; 8344 8345 struct mlx5_ifc_qpc_bits qpc; 8346 8347 u8 reserved_at_800[0x80]; 8348 }; 8349 8350 struct mlx5_ifc_init2init_qp_out_bits { 8351 u8 status[0x8]; 8352 u8 reserved_at_8[0x18]; 8353 8354 u8 syndrome[0x20]; 8355 8356 u8 reserved_at_40[0x20]; 8357 u8 ece[0x20]; 8358 }; 8359 8360 struct mlx5_ifc_init2init_qp_in_bits { 8361 u8 opcode[0x10]; 8362 u8 uid[0x10]; 8363 8364 u8 reserved_at_20[0x10]; 8365 u8 op_mod[0x10]; 8366 8367 u8 reserved_at_40[0x8]; 8368 u8 qpn[0x18]; 8369 8370 u8 reserved_at_60[0x20]; 8371 8372 u8 opt_param_mask[0x20]; 8373 8374 u8 ece[0x20]; 8375 8376 struct mlx5_ifc_qpc_bits qpc; 8377 8378 u8 reserved_at_800[0x80]; 8379 }; 8380 8381 struct mlx5_ifc_get_dropped_packet_log_out_bits { 8382 u8 status[0x8]; 8383 u8 reserved_at_8[0x18]; 8384 8385 u8 syndrome[0x20]; 8386 8387 u8 reserved_at_40[0x40]; 8388 8389 u8 packet_headers_log[128][0x8]; 8390 8391 u8 packet_syndrome[64][0x8]; 8392 }; 8393 8394 struct mlx5_ifc_get_dropped_packet_log_in_bits { 8395 u8 opcode[0x10]; 8396 u8 reserved_at_10[0x10]; 8397 8398 u8 reserved_at_20[0x10]; 8399 u8 op_mod[0x10]; 8400 8401 u8 reserved_at_40[0x40]; 8402 }; 8403 8404 struct mlx5_ifc_gen_eqe_in_bits { 8405 u8 opcode[0x10]; 8406 u8 reserved_at_10[0x10]; 8407 8408 u8 reserved_at_20[0x10]; 8409 u8 op_mod[0x10]; 8410 8411 u8 reserved_at_40[0x18]; 8412 u8 eq_number[0x8]; 8413 8414 u8 reserved_at_60[0x20]; 8415 8416 u8 eqe[64][0x8]; 8417 }; 8418 8419 struct mlx5_ifc_gen_eq_out_bits { 8420 u8 status[0x8]; 8421 u8 reserved_at_8[0x18]; 8422 8423 u8 syndrome[0x20]; 8424 8425 u8 reserved_at_40[0x40]; 8426 }; 8427 8428 struct mlx5_ifc_enable_hca_out_bits { 8429 u8 status[0x8]; 8430 u8 reserved_at_8[0x18]; 8431 8432 u8 syndrome[0x20]; 8433 8434 u8 reserved_at_40[0x20]; 8435 }; 8436 8437 struct mlx5_ifc_enable_hca_in_bits { 8438 u8 opcode[0x10]; 8439 u8 reserved_at_10[0x10]; 8440 8441 u8 reserved_at_20[0x10]; 8442 u8 op_mod[0x10]; 8443 8444 u8 embedded_cpu_function[0x1]; 8445 u8 reserved_at_41[0xf]; 8446 u8 function_id[0x10]; 8447 8448 u8 reserved_at_60[0x20]; 8449 }; 8450 8451 struct mlx5_ifc_drain_dct_out_bits { 8452 u8 status[0x8]; 8453 u8 reserved_at_8[0x18]; 8454 8455 u8 syndrome[0x20]; 8456 8457 u8 reserved_at_40[0x40]; 8458 }; 8459 8460 struct mlx5_ifc_drain_dct_in_bits { 8461 u8 opcode[0x10]; 8462 u8 uid[0x10]; 8463 8464 u8 reserved_at_20[0x10]; 8465 u8 op_mod[0x10]; 8466 8467 u8 reserved_at_40[0x8]; 8468 u8 dctn[0x18]; 8469 8470 u8 reserved_at_60[0x20]; 8471 }; 8472 8473 struct mlx5_ifc_disable_hca_out_bits { 8474 u8 status[0x8]; 8475 u8 reserved_at_8[0x18]; 8476 8477 u8 syndrome[0x20]; 8478 8479 u8 reserved_at_40[0x20]; 8480 }; 8481 8482 struct mlx5_ifc_disable_hca_in_bits { 8483 u8 opcode[0x10]; 8484 u8 reserved_at_10[0x10]; 8485 8486 u8 reserved_at_20[0x10]; 8487 u8 op_mod[0x10]; 8488 8489 u8 embedded_cpu_function[0x1]; 8490 u8 reserved_at_41[0xf]; 8491 u8 function_id[0x10]; 8492 8493 u8 reserved_at_60[0x20]; 8494 }; 8495 8496 struct mlx5_ifc_detach_from_mcg_out_bits { 8497 u8 status[0x8]; 8498 u8 reserved_at_8[0x18]; 8499 8500 u8 syndrome[0x20]; 8501 8502 u8 reserved_at_40[0x40]; 8503 }; 8504 8505 struct mlx5_ifc_detach_from_mcg_in_bits { 8506 u8 opcode[0x10]; 8507 u8 uid[0x10]; 8508 8509 u8 reserved_at_20[0x10]; 8510 u8 op_mod[0x10]; 8511 8512 u8 reserved_at_40[0x8]; 8513 u8 qpn[0x18]; 8514 8515 u8 reserved_at_60[0x20]; 8516 8517 u8 multicast_gid[16][0x8]; 8518 }; 8519 8520 struct mlx5_ifc_destroy_xrq_out_bits { 8521 u8 status[0x8]; 8522 u8 reserved_at_8[0x18]; 8523 8524 u8 syndrome[0x20]; 8525 8526 u8 reserved_at_40[0x40]; 8527 }; 8528 8529 struct mlx5_ifc_destroy_xrq_in_bits { 8530 u8 opcode[0x10]; 8531 u8 uid[0x10]; 8532 8533 u8 reserved_at_20[0x10]; 8534 u8 op_mod[0x10]; 8535 8536 u8 reserved_at_40[0x8]; 8537 u8 xrqn[0x18]; 8538 8539 u8 reserved_at_60[0x20]; 8540 }; 8541 8542 struct mlx5_ifc_destroy_xrc_srq_out_bits { 8543 u8 status[0x8]; 8544 u8 reserved_at_8[0x18]; 8545 8546 u8 syndrome[0x20]; 8547 8548 u8 reserved_at_40[0x40]; 8549 }; 8550 8551 struct mlx5_ifc_destroy_xrc_srq_in_bits { 8552 u8 opcode[0x10]; 8553 u8 uid[0x10]; 8554 8555 u8 reserved_at_20[0x10]; 8556 u8 op_mod[0x10]; 8557 8558 u8 reserved_at_40[0x8]; 8559 u8 xrc_srqn[0x18]; 8560 8561 u8 reserved_at_60[0x20]; 8562 }; 8563 8564 struct mlx5_ifc_destroy_tis_out_bits { 8565 u8 status[0x8]; 8566 u8 reserved_at_8[0x18]; 8567 8568 u8 syndrome[0x20]; 8569 8570 u8 reserved_at_40[0x40]; 8571 }; 8572 8573 struct mlx5_ifc_destroy_tis_in_bits { 8574 u8 opcode[0x10]; 8575 u8 uid[0x10]; 8576 8577 u8 reserved_at_20[0x10]; 8578 u8 op_mod[0x10]; 8579 8580 u8 reserved_at_40[0x8]; 8581 u8 tisn[0x18]; 8582 8583 u8 reserved_at_60[0x20]; 8584 }; 8585 8586 struct mlx5_ifc_destroy_tir_out_bits { 8587 u8 status[0x8]; 8588 u8 reserved_at_8[0x18]; 8589 8590 u8 syndrome[0x20]; 8591 8592 u8 reserved_at_40[0x40]; 8593 }; 8594 8595 struct mlx5_ifc_destroy_tir_in_bits { 8596 u8 opcode[0x10]; 8597 u8 uid[0x10]; 8598 8599 u8 reserved_at_20[0x10]; 8600 u8 op_mod[0x10]; 8601 8602 u8 reserved_at_40[0x8]; 8603 u8 tirn[0x18]; 8604 8605 u8 reserved_at_60[0x20]; 8606 }; 8607 8608 struct mlx5_ifc_destroy_srq_out_bits { 8609 u8 status[0x8]; 8610 u8 reserved_at_8[0x18]; 8611 8612 u8 syndrome[0x20]; 8613 8614 u8 reserved_at_40[0x40]; 8615 }; 8616 8617 struct mlx5_ifc_destroy_srq_in_bits { 8618 u8 opcode[0x10]; 8619 u8 uid[0x10]; 8620 8621 u8 reserved_at_20[0x10]; 8622 u8 op_mod[0x10]; 8623 8624 u8 reserved_at_40[0x8]; 8625 u8 srqn[0x18]; 8626 8627 u8 reserved_at_60[0x20]; 8628 }; 8629 8630 struct mlx5_ifc_destroy_sq_out_bits { 8631 u8 status[0x8]; 8632 u8 reserved_at_8[0x18]; 8633 8634 u8 syndrome[0x20]; 8635 8636 u8 reserved_at_40[0x40]; 8637 }; 8638 8639 struct mlx5_ifc_destroy_sq_in_bits { 8640 u8 opcode[0x10]; 8641 u8 uid[0x10]; 8642 8643 u8 reserved_at_20[0x10]; 8644 u8 op_mod[0x10]; 8645 8646 u8 reserved_at_40[0x8]; 8647 u8 sqn[0x18]; 8648 8649 u8 reserved_at_60[0x20]; 8650 }; 8651 8652 struct mlx5_ifc_destroy_scheduling_element_out_bits { 8653 u8 status[0x8]; 8654 u8 reserved_at_8[0x18]; 8655 8656 u8 syndrome[0x20]; 8657 8658 u8 reserved_at_40[0x1c0]; 8659 }; 8660 8661 struct mlx5_ifc_destroy_scheduling_element_in_bits { 8662 u8 opcode[0x10]; 8663 u8 reserved_at_10[0x10]; 8664 8665 u8 reserved_at_20[0x10]; 8666 u8 op_mod[0x10]; 8667 8668 u8 scheduling_hierarchy[0x8]; 8669 u8 reserved_at_48[0x18]; 8670 8671 u8 scheduling_element_id[0x20]; 8672 8673 u8 reserved_at_80[0x180]; 8674 }; 8675 8676 struct mlx5_ifc_destroy_rqt_out_bits { 8677 u8 status[0x8]; 8678 u8 reserved_at_8[0x18]; 8679 8680 u8 syndrome[0x20]; 8681 8682 u8 reserved_at_40[0x40]; 8683 }; 8684 8685 struct mlx5_ifc_destroy_rqt_in_bits { 8686 u8 opcode[0x10]; 8687 u8 uid[0x10]; 8688 8689 u8 reserved_at_20[0x10]; 8690 u8 op_mod[0x10]; 8691 8692 u8 reserved_at_40[0x8]; 8693 u8 rqtn[0x18]; 8694 8695 u8 reserved_at_60[0x20]; 8696 }; 8697 8698 struct mlx5_ifc_destroy_rq_out_bits { 8699 u8 status[0x8]; 8700 u8 reserved_at_8[0x18]; 8701 8702 u8 syndrome[0x20]; 8703 8704 u8 reserved_at_40[0x40]; 8705 }; 8706 8707 struct mlx5_ifc_destroy_rq_in_bits { 8708 u8 opcode[0x10]; 8709 u8 uid[0x10]; 8710 8711 u8 reserved_at_20[0x10]; 8712 u8 op_mod[0x10]; 8713 8714 u8 reserved_at_40[0x8]; 8715 u8 rqn[0x18]; 8716 8717 u8 reserved_at_60[0x20]; 8718 }; 8719 8720 struct mlx5_ifc_set_delay_drop_params_in_bits { 8721 u8 opcode[0x10]; 8722 u8 reserved_at_10[0x10]; 8723 8724 u8 reserved_at_20[0x10]; 8725 u8 op_mod[0x10]; 8726 8727 u8 reserved_at_40[0x20]; 8728 8729 u8 reserved_at_60[0x10]; 8730 u8 delay_drop_timeout[0x10]; 8731 }; 8732 8733 struct mlx5_ifc_set_delay_drop_params_out_bits { 8734 u8 status[0x8]; 8735 u8 reserved_at_8[0x18]; 8736 8737 u8 syndrome[0x20]; 8738 8739 u8 reserved_at_40[0x40]; 8740 }; 8741 8742 struct mlx5_ifc_destroy_rmp_out_bits { 8743 u8 status[0x8]; 8744 u8 reserved_at_8[0x18]; 8745 8746 u8 syndrome[0x20]; 8747 8748 u8 reserved_at_40[0x40]; 8749 }; 8750 8751 struct mlx5_ifc_destroy_rmp_in_bits { 8752 u8 opcode[0x10]; 8753 u8 uid[0x10]; 8754 8755 u8 reserved_at_20[0x10]; 8756 u8 op_mod[0x10]; 8757 8758 u8 reserved_at_40[0x8]; 8759 u8 rmpn[0x18]; 8760 8761 u8 reserved_at_60[0x20]; 8762 }; 8763 8764 struct mlx5_ifc_destroy_qp_out_bits { 8765 u8 status[0x8]; 8766 u8 reserved_at_8[0x18]; 8767 8768 u8 syndrome[0x20]; 8769 8770 u8 reserved_at_40[0x40]; 8771 }; 8772 8773 struct mlx5_ifc_destroy_qp_in_bits { 8774 u8 opcode[0x10]; 8775 u8 uid[0x10]; 8776 8777 u8 reserved_at_20[0x10]; 8778 u8 op_mod[0x10]; 8779 8780 u8 reserved_at_40[0x8]; 8781 u8 qpn[0x18]; 8782 8783 u8 reserved_at_60[0x20]; 8784 }; 8785 8786 struct mlx5_ifc_destroy_psv_out_bits { 8787 u8 status[0x8]; 8788 u8 reserved_at_8[0x18]; 8789 8790 u8 syndrome[0x20]; 8791 8792 u8 reserved_at_40[0x40]; 8793 }; 8794 8795 struct mlx5_ifc_destroy_psv_in_bits { 8796 u8 opcode[0x10]; 8797 u8 reserved_at_10[0x10]; 8798 8799 u8 reserved_at_20[0x10]; 8800 u8 op_mod[0x10]; 8801 8802 u8 reserved_at_40[0x8]; 8803 u8 psvn[0x18]; 8804 8805 u8 reserved_at_60[0x20]; 8806 }; 8807 8808 struct mlx5_ifc_destroy_mkey_out_bits { 8809 u8 status[0x8]; 8810 u8 reserved_at_8[0x18]; 8811 8812 u8 syndrome[0x20]; 8813 8814 u8 reserved_at_40[0x40]; 8815 }; 8816 8817 struct mlx5_ifc_destroy_mkey_in_bits { 8818 u8 opcode[0x10]; 8819 u8 uid[0x10]; 8820 8821 u8 reserved_at_20[0x10]; 8822 u8 op_mod[0x10]; 8823 8824 u8 reserved_at_40[0x8]; 8825 u8 mkey_index[0x18]; 8826 8827 u8 reserved_at_60[0x20]; 8828 }; 8829 8830 struct mlx5_ifc_destroy_flow_table_out_bits { 8831 u8 status[0x8]; 8832 u8 reserved_at_8[0x18]; 8833 8834 u8 syndrome[0x20]; 8835 8836 u8 reserved_at_40[0x40]; 8837 }; 8838 8839 struct mlx5_ifc_destroy_flow_table_in_bits { 8840 u8 opcode[0x10]; 8841 u8 reserved_at_10[0x10]; 8842 8843 u8 reserved_at_20[0x10]; 8844 u8 op_mod[0x10]; 8845 8846 u8 other_vport[0x1]; 8847 u8 other_eswitch[0x1]; 8848 u8 reserved_at_42[0xe]; 8849 u8 vport_number[0x10]; 8850 8851 u8 reserved_at_60[0x20]; 8852 8853 u8 table_type[0x8]; 8854 u8 reserved_at_88[0x8]; 8855 u8 eswitch_owner_vhca_id[0x10]; 8856 8857 u8 reserved_at_a0[0x8]; 8858 u8 table_id[0x18]; 8859 8860 u8 reserved_at_c0[0x140]; 8861 }; 8862 8863 struct mlx5_ifc_destroy_flow_group_out_bits { 8864 u8 status[0x8]; 8865 u8 reserved_at_8[0x18]; 8866 8867 u8 syndrome[0x20]; 8868 8869 u8 reserved_at_40[0x40]; 8870 }; 8871 8872 struct mlx5_ifc_destroy_flow_group_in_bits { 8873 u8 opcode[0x10]; 8874 u8 reserved_at_10[0x10]; 8875 8876 u8 reserved_at_20[0x10]; 8877 u8 op_mod[0x10]; 8878 8879 u8 other_vport[0x1]; 8880 u8 other_eswitch[0x1]; 8881 u8 reserved_at_42[0xe]; 8882 u8 vport_number[0x10]; 8883 8884 u8 reserved_at_60[0x20]; 8885 8886 u8 table_type[0x8]; 8887 u8 reserved_at_88[0x8]; 8888 u8 eswitch_owner_vhca_id[0x10]; 8889 8890 u8 reserved_at_a0[0x8]; 8891 u8 table_id[0x18]; 8892 8893 u8 group_id[0x20]; 8894 8895 u8 reserved_at_e0[0x120]; 8896 }; 8897 8898 struct mlx5_ifc_destroy_eq_out_bits { 8899 u8 status[0x8]; 8900 u8 reserved_at_8[0x18]; 8901 8902 u8 syndrome[0x20]; 8903 8904 u8 reserved_at_40[0x40]; 8905 }; 8906 8907 struct mlx5_ifc_destroy_eq_in_bits { 8908 u8 opcode[0x10]; 8909 u8 reserved_at_10[0x10]; 8910 8911 u8 reserved_at_20[0x10]; 8912 u8 op_mod[0x10]; 8913 8914 u8 reserved_at_40[0x18]; 8915 u8 eq_number[0x8]; 8916 8917 u8 reserved_at_60[0x20]; 8918 }; 8919 8920 struct mlx5_ifc_destroy_dct_out_bits { 8921 u8 status[0x8]; 8922 u8 reserved_at_8[0x18]; 8923 8924 u8 syndrome[0x20]; 8925 8926 u8 reserved_at_40[0x40]; 8927 }; 8928 8929 struct mlx5_ifc_destroy_dct_in_bits { 8930 u8 opcode[0x10]; 8931 u8 uid[0x10]; 8932 8933 u8 reserved_at_20[0x10]; 8934 u8 op_mod[0x10]; 8935 8936 u8 reserved_at_40[0x8]; 8937 u8 dctn[0x18]; 8938 8939 u8 reserved_at_60[0x20]; 8940 }; 8941 8942 struct mlx5_ifc_destroy_cq_out_bits { 8943 u8 status[0x8]; 8944 u8 reserved_at_8[0x18]; 8945 8946 u8 syndrome[0x20]; 8947 8948 u8 reserved_at_40[0x40]; 8949 }; 8950 8951 struct mlx5_ifc_destroy_cq_in_bits { 8952 u8 opcode[0x10]; 8953 u8 uid[0x10]; 8954 8955 u8 reserved_at_20[0x10]; 8956 u8 op_mod[0x10]; 8957 8958 u8 reserved_at_40[0x8]; 8959 u8 cqn[0x18]; 8960 8961 u8 reserved_at_60[0x20]; 8962 }; 8963 8964 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits { 8965 u8 status[0x8]; 8966 u8 reserved_at_8[0x18]; 8967 8968 u8 syndrome[0x20]; 8969 8970 u8 reserved_at_40[0x40]; 8971 }; 8972 8973 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits { 8974 u8 opcode[0x10]; 8975 u8 reserved_at_10[0x10]; 8976 8977 u8 reserved_at_20[0x10]; 8978 u8 op_mod[0x10]; 8979 8980 u8 reserved_at_40[0x20]; 8981 8982 u8 reserved_at_60[0x10]; 8983 u8 vxlan_udp_port[0x10]; 8984 }; 8985 8986 struct mlx5_ifc_delete_l2_table_entry_out_bits { 8987 u8 status[0x8]; 8988 u8 reserved_at_8[0x18]; 8989 8990 u8 syndrome[0x20]; 8991 8992 u8 reserved_at_40[0x40]; 8993 }; 8994 8995 struct mlx5_ifc_delete_l2_table_entry_in_bits { 8996 u8 opcode[0x10]; 8997 u8 reserved_at_10[0x10]; 8998 8999 u8 reserved_at_20[0x10]; 9000 u8 op_mod[0x10]; 9001 9002 u8 reserved_at_40[0x60]; 9003 9004 u8 reserved_at_a0[0x8]; 9005 u8 table_index[0x18]; 9006 9007 u8 reserved_at_c0[0x140]; 9008 }; 9009 9010 struct mlx5_ifc_delete_fte_out_bits { 9011 u8 status[0x8]; 9012 u8 reserved_at_8[0x18]; 9013 9014 u8 syndrome[0x20]; 9015 9016 u8 reserved_at_40[0x40]; 9017 }; 9018 9019 struct mlx5_ifc_delete_fte_in_bits { 9020 u8 opcode[0x10]; 9021 u8 reserved_at_10[0x10]; 9022 9023 u8 reserved_at_20[0x10]; 9024 u8 op_mod[0x10]; 9025 9026 u8 other_vport[0x1]; 9027 u8 other_eswitch[0x1]; 9028 u8 reserved_at_42[0xe]; 9029 u8 vport_number[0x10]; 9030 9031 u8 reserved_at_60[0x20]; 9032 9033 u8 table_type[0x8]; 9034 u8 reserved_at_88[0x8]; 9035 u8 eswitch_owner_vhca_id[0x10]; 9036 9037 u8 reserved_at_a0[0x8]; 9038 u8 table_id[0x18]; 9039 9040 u8 reserved_at_c0[0x40]; 9041 9042 u8 flow_index[0x20]; 9043 9044 u8 reserved_at_120[0xe0]; 9045 }; 9046 9047 struct mlx5_ifc_dealloc_xrcd_out_bits { 9048 u8 status[0x8]; 9049 u8 reserved_at_8[0x18]; 9050 9051 u8 syndrome[0x20]; 9052 9053 u8 reserved_at_40[0x40]; 9054 }; 9055 9056 struct mlx5_ifc_dealloc_xrcd_in_bits { 9057 u8 opcode[0x10]; 9058 u8 uid[0x10]; 9059 9060 u8 reserved_at_20[0x10]; 9061 u8 op_mod[0x10]; 9062 9063 u8 reserved_at_40[0x8]; 9064 u8 xrcd[0x18]; 9065 9066 u8 reserved_at_60[0x20]; 9067 }; 9068 9069 struct mlx5_ifc_dealloc_uar_out_bits { 9070 u8 status[0x8]; 9071 u8 reserved_at_8[0x18]; 9072 9073 u8 syndrome[0x20]; 9074 9075 u8 reserved_at_40[0x40]; 9076 }; 9077 9078 struct mlx5_ifc_dealloc_uar_in_bits { 9079 u8 opcode[0x10]; 9080 u8 uid[0x10]; 9081 9082 u8 reserved_at_20[0x10]; 9083 u8 op_mod[0x10]; 9084 9085 u8 reserved_at_40[0x8]; 9086 u8 uar[0x18]; 9087 9088 u8 reserved_at_60[0x20]; 9089 }; 9090 9091 struct mlx5_ifc_dealloc_transport_domain_out_bits { 9092 u8 status[0x8]; 9093 u8 reserved_at_8[0x18]; 9094 9095 u8 syndrome[0x20]; 9096 9097 u8 reserved_at_40[0x40]; 9098 }; 9099 9100 struct mlx5_ifc_dealloc_transport_domain_in_bits { 9101 u8 opcode[0x10]; 9102 u8 uid[0x10]; 9103 9104 u8 reserved_at_20[0x10]; 9105 u8 op_mod[0x10]; 9106 9107 u8 reserved_at_40[0x8]; 9108 u8 transport_domain[0x18]; 9109 9110 u8 reserved_at_60[0x20]; 9111 }; 9112 9113 struct mlx5_ifc_dealloc_q_counter_out_bits { 9114 u8 status[0x8]; 9115 u8 reserved_at_8[0x18]; 9116 9117 u8 syndrome[0x20]; 9118 9119 u8 reserved_at_40[0x40]; 9120 }; 9121 9122 struct mlx5_ifc_dealloc_q_counter_in_bits { 9123 u8 opcode[0x10]; 9124 u8 reserved_at_10[0x10]; 9125 9126 u8 reserved_at_20[0x10]; 9127 u8 op_mod[0x10]; 9128 9129 u8 reserved_at_40[0x18]; 9130 u8 counter_set_id[0x8]; 9131 9132 u8 reserved_at_60[0x20]; 9133 }; 9134 9135 struct mlx5_ifc_dealloc_pd_out_bits { 9136 u8 status[0x8]; 9137 u8 reserved_at_8[0x18]; 9138 9139 u8 syndrome[0x20]; 9140 9141 u8 reserved_at_40[0x40]; 9142 }; 9143 9144 struct mlx5_ifc_dealloc_pd_in_bits { 9145 u8 opcode[0x10]; 9146 u8 uid[0x10]; 9147 9148 u8 reserved_at_20[0x10]; 9149 u8 op_mod[0x10]; 9150 9151 u8 reserved_at_40[0x8]; 9152 u8 pd[0x18]; 9153 9154 u8 reserved_at_60[0x20]; 9155 }; 9156 9157 struct mlx5_ifc_dealloc_flow_counter_out_bits { 9158 u8 status[0x8]; 9159 u8 reserved_at_8[0x18]; 9160 9161 u8 syndrome[0x20]; 9162 9163 u8 reserved_at_40[0x40]; 9164 }; 9165 9166 struct mlx5_ifc_dealloc_flow_counter_in_bits { 9167 u8 opcode[0x10]; 9168 u8 reserved_at_10[0x10]; 9169 9170 u8 reserved_at_20[0x10]; 9171 u8 op_mod[0x10]; 9172 9173 u8 flow_counter_id[0x20]; 9174 9175 u8 reserved_at_60[0x20]; 9176 }; 9177 9178 struct mlx5_ifc_create_xrq_out_bits { 9179 u8 status[0x8]; 9180 u8 reserved_at_8[0x18]; 9181 9182 u8 syndrome[0x20]; 9183 9184 u8 reserved_at_40[0x8]; 9185 u8 xrqn[0x18]; 9186 9187 u8 reserved_at_60[0x20]; 9188 }; 9189 9190 struct mlx5_ifc_create_xrq_in_bits { 9191 u8 opcode[0x10]; 9192 u8 uid[0x10]; 9193 9194 u8 reserved_at_20[0x10]; 9195 u8 op_mod[0x10]; 9196 9197 u8 reserved_at_40[0x40]; 9198 9199 struct mlx5_ifc_xrqc_bits xrq_context; 9200 }; 9201 9202 struct mlx5_ifc_create_xrc_srq_out_bits { 9203 u8 status[0x8]; 9204 u8 reserved_at_8[0x18]; 9205 9206 u8 syndrome[0x20]; 9207 9208 u8 reserved_at_40[0x8]; 9209 u8 xrc_srqn[0x18]; 9210 9211 u8 reserved_at_60[0x20]; 9212 }; 9213 9214 struct mlx5_ifc_create_xrc_srq_in_bits { 9215 u8 opcode[0x10]; 9216 u8 uid[0x10]; 9217 9218 u8 reserved_at_20[0x10]; 9219 u8 op_mod[0x10]; 9220 9221 u8 reserved_at_40[0x40]; 9222 9223 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 9224 9225 u8 reserved_at_280[0x60]; 9226 9227 u8 xrc_srq_umem_valid[0x1]; 9228 u8 reserved_at_2e1[0x1f]; 9229 9230 u8 reserved_at_300[0x580]; 9231 9232 u8 pas[][0x40]; 9233 }; 9234 9235 struct mlx5_ifc_create_tis_out_bits { 9236 u8 status[0x8]; 9237 u8 reserved_at_8[0x18]; 9238 9239 u8 syndrome[0x20]; 9240 9241 u8 reserved_at_40[0x8]; 9242 u8 tisn[0x18]; 9243 9244 u8 reserved_at_60[0x20]; 9245 }; 9246 9247 struct mlx5_ifc_create_tis_in_bits { 9248 u8 opcode[0x10]; 9249 u8 uid[0x10]; 9250 9251 u8 reserved_at_20[0x10]; 9252 u8 op_mod[0x10]; 9253 9254 u8 reserved_at_40[0xc0]; 9255 9256 struct mlx5_ifc_tisc_bits ctx; 9257 }; 9258 9259 struct mlx5_ifc_create_tir_out_bits { 9260 u8 status[0x8]; 9261 u8 icm_address_63_40[0x18]; 9262 9263 u8 syndrome[0x20]; 9264 9265 u8 icm_address_39_32[0x8]; 9266 u8 tirn[0x18]; 9267 9268 u8 icm_address_31_0[0x20]; 9269 }; 9270 9271 struct mlx5_ifc_create_tir_in_bits { 9272 u8 opcode[0x10]; 9273 u8 uid[0x10]; 9274 9275 u8 reserved_at_20[0x10]; 9276 u8 op_mod[0x10]; 9277 9278 u8 reserved_at_40[0xc0]; 9279 9280 struct mlx5_ifc_tirc_bits ctx; 9281 }; 9282 9283 struct mlx5_ifc_create_srq_out_bits { 9284 u8 status[0x8]; 9285 u8 reserved_at_8[0x18]; 9286 9287 u8 syndrome[0x20]; 9288 9289 u8 reserved_at_40[0x8]; 9290 u8 srqn[0x18]; 9291 9292 u8 reserved_at_60[0x20]; 9293 }; 9294 9295 struct mlx5_ifc_create_srq_in_bits { 9296 u8 opcode[0x10]; 9297 u8 uid[0x10]; 9298 9299 u8 reserved_at_20[0x10]; 9300 u8 op_mod[0x10]; 9301 9302 u8 reserved_at_40[0x40]; 9303 9304 struct mlx5_ifc_srqc_bits srq_context_entry; 9305 9306 u8 reserved_at_280[0x600]; 9307 9308 u8 pas[][0x40]; 9309 }; 9310 9311 struct mlx5_ifc_create_sq_out_bits { 9312 u8 status[0x8]; 9313 u8 reserved_at_8[0x18]; 9314 9315 u8 syndrome[0x20]; 9316 9317 u8 reserved_at_40[0x8]; 9318 u8 sqn[0x18]; 9319 9320 u8 reserved_at_60[0x20]; 9321 }; 9322 9323 struct mlx5_ifc_create_sq_in_bits { 9324 u8 opcode[0x10]; 9325 u8 uid[0x10]; 9326 9327 u8 reserved_at_20[0x10]; 9328 u8 op_mod[0x10]; 9329 9330 u8 reserved_at_40[0xc0]; 9331 9332 struct mlx5_ifc_sqc_bits ctx; 9333 }; 9334 9335 struct mlx5_ifc_create_scheduling_element_out_bits { 9336 u8 status[0x8]; 9337 u8 reserved_at_8[0x18]; 9338 9339 u8 syndrome[0x20]; 9340 9341 u8 reserved_at_40[0x40]; 9342 9343 u8 scheduling_element_id[0x20]; 9344 9345 u8 reserved_at_a0[0x160]; 9346 }; 9347 9348 struct mlx5_ifc_create_scheduling_element_in_bits { 9349 u8 opcode[0x10]; 9350 u8 reserved_at_10[0x10]; 9351 9352 u8 reserved_at_20[0x10]; 9353 u8 op_mod[0x10]; 9354 9355 u8 scheduling_hierarchy[0x8]; 9356 u8 reserved_at_48[0x18]; 9357 9358 u8 reserved_at_60[0xa0]; 9359 9360 struct mlx5_ifc_scheduling_context_bits scheduling_context; 9361 9362 u8 reserved_at_300[0x100]; 9363 }; 9364 9365 struct mlx5_ifc_create_rqt_out_bits { 9366 u8 status[0x8]; 9367 u8 reserved_at_8[0x18]; 9368 9369 u8 syndrome[0x20]; 9370 9371 u8 reserved_at_40[0x8]; 9372 u8 rqtn[0x18]; 9373 9374 u8 reserved_at_60[0x20]; 9375 }; 9376 9377 struct mlx5_ifc_create_rqt_in_bits { 9378 u8 opcode[0x10]; 9379 u8 uid[0x10]; 9380 9381 u8 reserved_at_20[0x10]; 9382 u8 op_mod[0x10]; 9383 9384 u8 reserved_at_40[0xc0]; 9385 9386 struct mlx5_ifc_rqtc_bits rqt_context; 9387 }; 9388 9389 struct mlx5_ifc_create_rq_out_bits { 9390 u8 status[0x8]; 9391 u8 reserved_at_8[0x18]; 9392 9393 u8 syndrome[0x20]; 9394 9395 u8 reserved_at_40[0x8]; 9396 u8 rqn[0x18]; 9397 9398 u8 reserved_at_60[0x20]; 9399 }; 9400 9401 struct mlx5_ifc_create_rq_in_bits { 9402 u8 opcode[0x10]; 9403 u8 uid[0x10]; 9404 9405 u8 reserved_at_20[0x10]; 9406 u8 op_mod[0x10]; 9407 9408 u8 reserved_at_40[0xc0]; 9409 9410 struct mlx5_ifc_rqc_bits ctx; 9411 }; 9412 9413 struct mlx5_ifc_create_rmp_out_bits { 9414 u8 status[0x8]; 9415 u8 reserved_at_8[0x18]; 9416 9417 u8 syndrome[0x20]; 9418 9419 u8 reserved_at_40[0x8]; 9420 u8 rmpn[0x18]; 9421 9422 u8 reserved_at_60[0x20]; 9423 }; 9424 9425 struct mlx5_ifc_create_rmp_in_bits { 9426 u8 opcode[0x10]; 9427 u8 uid[0x10]; 9428 9429 u8 reserved_at_20[0x10]; 9430 u8 op_mod[0x10]; 9431 9432 u8 reserved_at_40[0xc0]; 9433 9434 struct mlx5_ifc_rmpc_bits ctx; 9435 }; 9436 9437 struct mlx5_ifc_create_qp_out_bits { 9438 u8 status[0x8]; 9439 u8 reserved_at_8[0x18]; 9440 9441 u8 syndrome[0x20]; 9442 9443 u8 reserved_at_40[0x8]; 9444 u8 qpn[0x18]; 9445 9446 u8 ece[0x20]; 9447 }; 9448 9449 struct mlx5_ifc_create_qp_in_bits { 9450 u8 opcode[0x10]; 9451 u8 uid[0x10]; 9452 9453 u8 reserved_at_20[0x10]; 9454 u8 op_mod[0x10]; 9455 9456 u8 qpc_ext[0x1]; 9457 u8 reserved_at_41[0x7]; 9458 u8 input_qpn[0x18]; 9459 9460 u8 reserved_at_60[0x20]; 9461 u8 opt_param_mask[0x20]; 9462 9463 u8 ece[0x20]; 9464 9465 struct mlx5_ifc_qpc_bits qpc; 9466 9467 u8 wq_umem_offset[0x40]; 9468 9469 u8 wq_umem_id[0x20]; 9470 9471 u8 wq_umem_valid[0x1]; 9472 u8 reserved_at_861[0x1f]; 9473 9474 u8 pas[][0x40]; 9475 }; 9476 9477 struct mlx5_ifc_create_psv_out_bits { 9478 u8 status[0x8]; 9479 u8 reserved_at_8[0x18]; 9480 9481 u8 syndrome[0x20]; 9482 9483 u8 reserved_at_40[0x40]; 9484 9485 u8 reserved_at_80[0x8]; 9486 u8 psv0_index[0x18]; 9487 9488 u8 reserved_at_a0[0x8]; 9489 u8 psv1_index[0x18]; 9490 9491 u8 reserved_at_c0[0x8]; 9492 u8 psv2_index[0x18]; 9493 9494 u8 reserved_at_e0[0x8]; 9495 u8 psv3_index[0x18]; 9496 }; 9497 9498 struct mlx5_ifc_create_psv_in_bits { 9499 u8 opcode[0x10]; 9500 u8 reserved_at_10[0x10]; 9501 9502 u8 reserved_at_20[0x10]; 9503 u8 op_mod[0x10]; 9504 9505 u8 num_psv[0x4]; 9506 u8 reserved_at_44[0x4]; 9507 u8 pd[0x18]; 9508 9509 u8 reserved_at_60[0x20]; 9510 }; 9511 9512 struct mlx5_ifc_create_mkey_out_bits { 9513 u8 status[0x8]; 9514 u8 reserved_at_8[0x18]; 9515 9516 u8 syndrome[0x20]; 9517 9518 u8 reserved_at_40[0x8]; 9519 u8 mkey_index[0x18]; 9520 9521 u8 reserved_at_60[0x20]; 9522 }; 9523 9524 struct mlx5_ifc_create_mkey_in_bits { 9525 u8 opcode[0x10]; 9526 u8 uid[0x10]; 9527 9528 u8 reserved_at_20[0x10]; 9529 u8 op_mod[0x10]; 9530 9531 u8 reserved_at_40[0x20]; 9532 9533 u8 pg_access[0x1]; 9534 u8 mkey_umem_valid[0x1]; 9535 u8 data_direct[0x1]; 9536 u8 reserved_at_63[0x1d]; 9537 9538 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 9539 9540 u8 reserved_at_280[0x80]; 9541 9542 u8 translations_octword_actual_size[0x20]; 9543 9544 u8 reserved_at_320[0x560]; 9545 9546 u8 klm_pas_mtt[][0x20]; 9547 }; 9548 9549 enum { 9550 MLX5_FLOW_TABLE_TYPE_NIC_RX = 0x0, 9551 MLX5_FLOW_TABLE_TYPE_NIC_TX = 0x1, 9552 MLX5_FLOW_TABLE_TYPE_ESW_EGRESS_ACL = 0x2, 9553 MLX5_FLOW_TABLE_TYPE_ESW_INGRESS_ACL = 0x3, 9554 MLX5_FLOW_TABLE_TYPE_FDB = 0X4, 9555 MLX5_FLOW_TABLE_TYPE_SNIFFER_RX = 0X5, 9556 MLX5_FLOW_TABLE_TYPE_SNIFFER_TX = 0X6, 9557 }; 9558 9559 struct mlx5_ifc_create_flow_table_out_bits { 9560 u8 status[0x8]; 9561 u8 icm_address_63_40[0x18]; 9562 9563 u8 syndrome[0x20]; 9564 9565 u8 icm_address_39_32[0x8]; 9566 u8 table_id[0x18]; 9567 9568 u8 icm_address_31_0[0x20]; 9569 }; 9570 9571 struct mlx5_ifc_create_flow_table_in_bits { 9572 u8 opcode[0x10]; 9573 u8 uid[0x10]; 9574 9575 u8 reserved_at_20[0x10]; 9576 u8 op_mod[0x10]; 9577 9578 u8 other_vport[0x1]; 9579 u8 other_eswitch[0x1]; 9580 u8 reserved_at_42[0xe]; 9581 u8 vport_number[0x10]; 9582 9583 u8 reserved_at_60[0x20]; 9584 9585 u8 table_type[0x8]; 9586 u8 reserved_at_88[0x8]; 9587 u8 eswitch_owner_vhca_id[0x10]; 9588 9589 u8 reserved_at_a0[0x20]; 9590 9591 struct mlx5_ifc_flow_table_context_bits flow_table_context; 9592 }; 9593 9594 struct mlx5_ifc_create_flow_group_out_bits { 9595 u8 status[0x8]; 9596 u8 reserved_at_8[0x18]; 9597 9598 u8 syndrome[0x20]; 9599 9600 u8 reserved_at_40[0x8]; 9601 u8 group_id[0x18]; 9602 9603 u8 reserved_at_60[0x20]; 9604 }; 9605 9606 enum { 9607 MLX5_CREATE_FLOW_GROUP_IN_GROUP_TYPE_TCAM_SUBTABLE = 0x0, 9608 MLX5_CREATE_FLOW_GROUP_IN_GROUP_TYPE_HASH_SPLIT = 0x1, 9609 }; 9610 9611 enum { 9612 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 9613 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 9614 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 9615 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3, 9616 }; 9617 9618 struct mlx5_ifc_create_flow_group_in_bits { 9619 u8 opcode[0x10]; 9620 u8 reserved_at_10[0x10]; 9621 9622 u8 reserved_at_20[0x10]; 9623 u8 op_mod[0x10]; 9624 9625 u8 other_vport[0x1]; 9626 u8 other_eswitch[0x1]; 9627 u8 reserved_at_42[0xe]; 9628 u8 vport_number[0x10]; 9629 9630 u8 reserved_at_60[0x20]; 9631 9632 u8 table_type[0x8]; 9633 u8 reserved_at_88[0x4]; 9634 u8 group_type[0x4]; 9635 u8 eswitch_owner_vhca_id[0x10]; 9636 9637 u8 reserved_at_a0[0x8]; 9638 u8 table_id[0x18]; 9639 9640 u8 source_eswitch_owner_vhca_id_valid[0x1]; 9641 9642 u8 reserved_at_c1[0x1f]; 9643 9644 u8 start_flow_index[0x20]; 9645 9646 u8 reserved_at_100[0x20]; 9647 9648 u8 end_flow_index[0x20]; 9649 9650 u8 reserved_at_140[0x10]; 9651 u8 match_definer_id[0x10]; 9652 9653 u8 reserved_at_160[0x80]; 9654 9655 u8 reserved_at_1e0[0x18]; 9656 u8 match_criteria_enable[0x8]; 9657 9658 struct mlx5_ifc_fte_match_param_bits match_criteria; 9659 9660 u8 reserved_at_1200[0xe00]; 9661 }; 9662 9663 struct mlx5_ifc_create_eq_out_bits { 9664 u8 status[0x8]; 9665 u8 reserved_at_8[0x18]; 9666 9667 u8 syndrome[0x20]; 9668 9669 u8 reserved_at_40[0x18]; 9670 u8 eq_number[0x8]; 9671 9672 u8 reserved_at_60[0x20]; 9673 }; 9674 9675 struct mlx5_ifc_create_eq_in_bits { 9676 u8 opcode[0x10]; 9677 u8 uid[0x10]; 9678 9679 u8 reserved_at_20[0x10]; 9680 u8 op_mod[0x10]; 9681 9682 u8 reserved_at_40[0x40]; 9683 9684 struct mlx5_ifc_eqc_bits eq_context_entry; 9685 9686 u8 reserved_at_280[0x40]; 9687 9688 u8 event_bitmask[4][0x40]; 9689 9690 u8 reserved_at_3c0[0x4c0]; 9691 9692 u8 pas[][0x40]; 9693 }; 9694 9695 struct mlx5_ifc_create_dct_out_bits { 9696 u8 status[0x8]; 9697 u8 reserved_at_8[0x18]; 9698 9699 u8 syndrome[0x20]; 9700 9701 u8 reserved_at_40[0x8]; 9702 u8 dctn[0x18]; 9703 9704 u8 ece[0x20]; 9705 }; 9706 9707 struct mlx5_ifc_create_dct_in_bits { 9708 u8 opcode[0x10]; 9709 u8 uid[0x10]; 9710 9711 u8 reserved_at_20[0x10]; 9712 u8 op_mod[0x10]; 9713 9714 u8 reserved_at_40[0x40]; 9715 9716 struct mlx5_ifc_dctc_bits dct_context_entry; 9717 9718 u8 reserved_at_280[0x180]; 9719 }; 9720 9721 struct mlx5_ifc_create_cq_out_bits { 9722 u8 status[0x8]; 9723 u8 reserved_at_8[0x18]; 9724 9725 u8 syndrome[0x20]; 9726 9727 u8 reserved_at_40[0x8]; 9728 u8 cqn[0x18]; 9729 9730 u8 reserved_at_60[0x20]; 9731 }; 9732 9733 struct mlx5_ifc_create_cq_in_bits { 9734 u8 opcode[0x10]; 9735 u8 uid[0x10]; 9736 9737 u8 reserved_at_20[0x10]; 9738 u8 op_mod[0x10]; 9739 9740 u8 reserved_at_40[0x40]; 9741 9742 struct mlx5_ifc_cqc_bits cq_context; 9743 9744 u8 reserved_at_280[0x60]; 9745 9746 u8 cq_umem_valid[0x1]; 9747 u8 reserved_at_2e1[0x59f]; 9748 9749 u8 pas[][0x40]; 9750 }; 9751 9752 struct mlx5_ifc_config_int_moderation_out_bits { 9753 u8 status[0x8]; 9754 u8 reserved_at_8[0x18]; 9755 9756 u8 syndrome[0x20]; 9757 9758 u8 reserved_at_40[0x4]; 9759 u8 min_delay[0xc]; 9760 u8 int_vector[0x10]; 9761 9762 u8 reserved_at_60[0x20]; 9763 }; 9764 9765 enum { 9766 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0, 9767 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1, 9768 }; 9769 9770 struct mlx5_ifc_config_int_moderation_in_bits { 9771 u8 opcode[0x10]; 9772 u8 reserved_at_10[0x10]; 9773 9774 u8 reserved_at_20[0x10]; 9775 u8 op_mod[0x10]; 9776 9777 u8 reserved_at_40[0x4]; 9778 u8 min_delay[0xc]; 9779 u8 int_vector[0x10]; 9780 9781 u8 reserved_at_60[0x20]; 9782 }; 9783 9784 struct mlx5_ifc_attach_to_mcg_out_bits { 9785 u8 status[0x8]; 9786 u8 reserved_at_8[0x18]; 9787 9788 u8 syndrome[0x20]; 9789 9790 u8 reserved_at_40[0x40]; 9791 }; 9792 9793 struct mlx5_ifc_attach_to_mcg_in_bits { 9794 u8 opcode[0x10]; 9795 u8 uid[0x10]; 9796 9797 u8 reserved_at_20[0x10]; 9798 u8 op_mod[0x10]; 9799 9800 u8 reserved_at_40[0x8]; 9801 u8 qpn[0x18]; 9802 9803 u8 reserved_at_60[0x20]; 9804 9805 u8 multicast_gid[16][0x8]; 9806 }; 9807 9808 struct mlx5_ifc_arm_xrq_out_bits { 9809 u8 status[0x8]; 9810 u8 reserved_at_8[0x18]; 9811 9812 u8 syndrome[0x20]; 9813 9814 u8 reserved_at_40[0x40]; 9815 }; 9816 9817 struct mlx5_ifc_arm_xrq_in_bits { 9818 u8 opcode[0x10]; 9819 u8 reserved_at_10[0x10]; 9820 9821 u8 reserved_at_20[0x10]; 9822 u8 op_mod[0x10]; 9823 9824 u8 reserved_at_40[0x8]; 9825 u8 xrqn[0x18]; 9826 9827 u8 reserved_at_60[0x10]; 9828 u8 lwm[0x10]; 9829 }; 9830 9831 struct mlx5_ifc_arm_xrc_srq_out_bits { 9832 u8 status[0x8]; 9833 u8 reserved_at_8[0x18]; 9834 9835 u8 syndrome[0x20]; 9836 9837 u8 reserved_at_40[0x40]; 9838 }; 9839 9840 enum { 9841 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1, 9842 }; 9843 9844 struct mlx5_ifc_arm_xrc_srq_in_bits { 9845 u8 opcode[0x10]; 9846 u8 uid[0x10]; 9847 9848 u8 reserved_at_20[0x10]; 9849 u8 op_mod[0x10]; 9850 9851 u8 reserved_at_40[0x8]; 9852 u8 xrc_srqn[0x18]; 9853 9854 u8 reserved_at_60[0x10]; 9855 u8 lwm[0x10]; 9856 }; 9857 9858 struct mlx5_ifc_arm_rq_out_bits { 9859 u8 status[0x8]; 9860 u8 reserved_at_8[0x18]; 9861 9862 u8 syndrome[0x20]; 9863 9864 u8 reserved_at_40[0x40]; 9865 }; 9866 9867 enum { 9868 MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1, 9869 MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2, 9870 }; 9871 9872 struct mlx5_ifc_arm_rq_in_bits { 9873 u8 opcode[0x10]; 9874 u8 uid[0x10]; 9875 9876 u8 reserved_at_20[0x10]; 9877 u8 op_mod[0x10]; 9878 9879 u8 reserved_at_40[0x8]; 9880 u8 srq_number[0x18]; 9881 9882 u8 reserved_at_60[0x10]; 9883 u8 lwm[0x10]; 9884 }; 9885 9886 struct mlx5_ifc_arm_dct_out_bits { 9887 u8 status[0x8]; 9888 u8 reserved_at_8[0x18]; 9889 9890 u8 syndrome[0x20]; 9891 9892 u8 reserved_at_40[0x40]; 9893 }; 9894 9895 struct mlx5_ifc_arm_dct_in_bits { 9896 u8 opcode[0x10]; 9897 u8 reserved_at_10[0x10]; 9898 9899 u8 reserved_at_20[0x10]; 9900 u8 op_mod[0x10]; 9901 9902 u8 reserved_at_40[0x8]; 9903 u8 dct_number[0x18]; 9904 9905 u8 reserved_at_60[0x20]; 9906 }; 9907 9908 struct mlx5_ifc_alloc_xrcd_out_bits { 9909 u8 status[0x8]; 9910 u8 reserved_at_8[0x18]; 9911 9912 u8 syndrome[0x20]; 9913 9914 u8 reserved_at_40[0x8]; 9915 u8 xrcd[0x18]; 9916 9917 u8 reserved_at_60[0x20]; 9918 }; 9919 9920 struct mlx5_ifc_alloc_xrcd_in_bits { 9921 u8 opcode[0x10]; 9922 u8 uid[0x10]; 9923 9924 u8 reserved_at_20[0x10]; 9925 u8 op_mod[0x10]; 9926 9927 u8 reserved_at_40[0x40]; 9928 }; 9929 9930 struct mlx5_ifc_alloc_uar_out_bits { 9931 u8 status[0x8]; 9932 u8 reserved_at_8[0x18]; 9933 9934 u8 syndrome[0x20]; 9935 9936 u8 reserved_at_40[0x8]; 9937 u8 uar[0x18]; 9938 9939 u8 reserved_at_60[0x20]; 9940 }; 9941 9942 struct mlx5_ifc_alloc_uar_in_bits { 9943 u8 opcode[0x10]; 9944 u8 uid[0x10]; 9945 9946 u8 reserved_at_20[0x10]; 9947 u8 op_mod[0x10]; 9948 9949 u8 reserved_at_40[0x40]; 9950 }; 9951 9952 struct mlx5_ifc_alloc_transport_domain_out_bits { 9953 u8 status[0x8]; 9954 u8 reserved_at_8[0x18]; 9955 9956 u8 syndrome[0x20]; 9957 9958 u8 reserved_at_40[0x8]; 9959 u8 transport_domain[0x18]; 9960 9961 u8 reserved_at_60[0x20]; 9962 }; 9963 9964 struct mlx5_ifc_alloc_transport_domain_in_bits { 9965 u8 opcode[0x10]; 9966 u8 uid[0x10]; 9967 9968 u8 reserved_at_20[0x10]; 9969 u8 op_mod[0x10]; 9970 9971 u8 reserved_at_40[0x40]; 9972 }; 9973 9974 struct mlx5_ifc_alloc_q_counter_out_bits { 9975 u8 status[0x8]; 9976 u8 reserved_at_8[0x18]; 9977 9978 u8 syndrome[0x20]; 9979 9980 u8 reserved_at_40[0x18]; 9981 u8 counter_set_id[0x8]; 9982 9983 u8 reserved_at_60[0x20]; 9984 }; 9985 9986 struct mlx5_ifc_alloc_q_counter_in_bits { 9987 u8 opcode[0x10]; 9988 u8 uid[0x10]; 9989 9990 u8 reserved_at_20[0x10]; 9991 u8 op_mod[0x10]; 9992 9993 u8 reserved_at_40[0x40]; 9994 }; 9995 9996 struct mlx5_ifc_alloc_pd_out_bits { 9997 u8 status[0x8]; 9998 u8 reserved_at_8[0x18]; 9999 10000 u8 syndrome[0x20]; 10001 10002 u8 reserved_at_40[0x8]; 10003 u8 pd[0x18]; 10004 10005 u8 reserved_at_60[0x20]; 10006 }; 10007 10008 struct mlx5_ifc_alloc_pd_in_bits { 10009 u8 opcode[0x10]; 10010 u8 uid[0x10]; 10011 10012 u8 reserved_at_20[0x10]; 10013 u8 op_mod[0x10]; 10014 10015 u8 reserved_at_40[0x40]; 10016 }; 10017 10018 struct mlx5_ifc_alloc_flow_counter_out_bits { 10019 u8 status[0x8]; 10020 u8 reserved_at_8[0x18]; 10021 10022 u8 syndrome[0x20]; 10023 10024 u8 flow_counter_id[0x20]; 10025 10026 u8 reserved_at_60[0x20]; 10027 }; 10028 10029 struct mlx5_ifc_alloc_flow_counter_in_bits { 10030 u8 opcode[0x10]; 10031 u8 reserved_at_10[0x10]; 10032 10033 u8 reserved_at_20[0x10]; 10034 u8 op_mod[0x10]; 10035 10036 u8 reserved_at_40[0x33]; 10037 u8 flow_counter_bulk_log_size[0x5]; 10038 u8 flow_counter_bulk[0x8]; 10039 }; 10040 10041 struct mlx5_ifc_add_vxlan_udp_dport_out_bits { 10042 u8 status[0x8]; 10043 u8 reserved_at_8[0x18]; 10044 10045 u8 syndrome[0x20]; 10046 10047 u8 reserved_at_40[0x40]; 10048 }; 10049 10050 struct mlx5_ifc_add_vxlan_udp_dport_in_bits { 10051 u8 opcode[0x10]; 10052 u8 reserved_at_10[0x10]; 10053 10054 u8 reserved_at_20[0x10]; 10055 u8 op_mod[0x10]; 10056 10057 u8 reserved_at_40[0x20]; 10058 10059 u8 reserved_at_60[0x10]; 10060 u8 vxlan_udp_port[0x10]; 10061 }; 10062 10063 struct mlx5_ifc_set_pp_rate_limit_out_bits { 10064 u8 status[0x8]; 10065 u8 reserved_at_8[0x18]; 10066 10067 u8 syndrome[0x20]; 10068 10069 u8 reserved_at_40[0x40]; 10070 }; 10071 10072 struct mlx5_ifc_set_pp_rate_limit_context_bits { 10073 u8 rate_limit[0x20]; 10074 10075 u8 burst_upper_bound[0x20]; 10076 10077 u8 reserved_at_40[0x10]; 10078 u8 typical_packet_size[0x10]; 10079 10080 u8 reserved_at_60[0x120]; 10081 }; 10082 10083 struct mlx5_ifc_set_pp_rate_limit_in_bits { 10084 u8 opcode[0x10]; 10085 u8 uid[0x10]; 10086 10087 u8 reserved_at_20[0x10]; 10088 u8 op_mod[0x10]; 10089 10090 u8 reserved_at_40[0x10]; 10091 u8 rate_limit_index[0x10]; 10092 10093 u8 reserved_at_60[0x20]; 10094 10095 struct mlx5_ifc_set_pp_rate_limit_context_bits ctx; 10096 }; 10097 10098 struct mlx5_ifc_access_register_out_bits { 10099 u8 status[0x8]; 10100 u8 reserved_at_8[0x18]; 10101 10102 u8 syndrome[0x20]; 10103 10104 u8 reserved_at_40[0x40]; 10105 10106 u8 register_data[][0x20]; 10107 }; 10108 10109 enum { 10110 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0, 10111 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1, 10112 }; 10113 10114 struct mlx5_ifc_access_register_in_bits { 10115 u8 opcode[0x10]; 10116 u8 reserved_at_10[0x10]; 10117 10118 u8 reserved_at_20[0x10]; 10119 u8 op_mod[0x10]; 10120 10121 u8 reserved_at_40[0x10]; 10122 u8 register_id[0x10]; 10123 10124 u8 argument[0x20]; 10125 10126 u8 register_data[][0x20]; 10127 }; 10128 10129 struct mlx5_ifc_sltp_reg_bits { 10130 u8 status[0x4]; 10131 u8 version[0x4]; 10132 u8 local_port[0x8]; 10133 u8 pnat[0x2]; 10134 u8 reserved_at_12[0x2]; 10135 u8 lane[0x4]; 10136 u8 reserved_at_18[0x8]; 10137 10138 u8 reserved_at_20[0x20]; 10139 10140 u8 reserved_at_40[0x7]; 10141 u8 polarity[0x1]; 10142 u8 ob_tap0[0x8]; 10143 u8 ob_tap1[0x8]; 10144 u8 ob_tap2[0x8]; 10145 10146 u8 reserved_at_60[0xc]; 10147 u8 ob_preemp_mode[0x4]; 10148 u8 ob_reg[0x8]; 10149 u8 ob_bias[0x8]; 10150 10151 u8 reserved_at_80[0x20]; 10152 }; 10153 10154 struct mlx5_ifc_slrg_reg_bits { 10155 u8 status[0x4]; 10156 u8 version[0x4]; 10157 u8 local_port[0x8]; 10158 u8 pnat[0x2]; 10159 u8 reserved_at_12[0x2]; 10160 u8 lane[0x4]; 10161 u8 reserved_at_18[0x8]; 10162 10163 u8 time_to_link_up[0x10]; 10164 u8 reserved_at_30[0xc]; 10165 u8 grade_lane_speed[0x4]; 10166 10167 u8 grade_version[0x8]; 10168 u8 grade[0x18]; 10169 10170 u8 reserved_at_60[0x4]; 10171 u8 height_grade_type[0x4]; 10172 u8 height_grade[0x18]; 10173 10174 u8 height_dz[0x10]; 10175 u8 height_dv[0x10]; 10176 10177 u8 reserved_at_a0[0x10]; 10178 u8 height_sigma[0x10]; 10179 10180 u8 reserved_at_c0[0x20]; 10181 10182 u8 reserved_at_e0[0x4]; 10183 u8 phase_grade_type[0x4]; 10184 u8 phase_grade[0x18]; 10185 10186 u8 reserved_at_100[0x8]; 10187 u8 phase_eo_pos[0x8]; 10188 u8 reserved_at_110[0x8]; 10189 u8 phase_eo_neg[0x8]; 10190 10191 u8 ffe_set_tested[0x10]; 10192 u8 test_errors_per_lane[0x10]; 10193 }; 10194 10195 struct mlx5_ifc_pvlc_reg_bits { 10196 u8 reserved_at_0[0x8]; 10197 u8 local_port[0x8]; 10198 u8 reserved_at_10[0x10]; 10199 10200 u8 reserved_at_20[0x1c]; 10201 u8 vl_hw_cap[0x4]; 10202 10203 u8 reserved_at_40[0x1c]; 10204 u8 vl_admin[0x4]; 10205 10206 u8 reserved_at_60[0x1c]; 10207 u8 vl_operational[0x4]; 10208 }; 10209 10210 struct mlx5_ifc_pude_reg_bits { 10211 u8 swid[0x8]; 10212 u8 local_port[0x8]; 10213 u8 reserved_at_10[0x4]; 10214 u8 admin_status[0x4]; 10215 u8 reserved_at_18[0x4]; 10216 u8 oper_status[0x4]; 10217 10218 u8 reserved_at_20[0x60]; 10219 }; 10220 10221 enum { 10222 MLX5_PTYS_CONNECTOR_TYPE_PORT_DA = 0x7, 10223 }; 10224 10225 struct mlx5_ifc_ptys_reg_bits { 10226 u8 reserved_at_0[0x1]; 10227 u8 an_disable_admin[0x1]; 10228 u8 an_disable_cap[0x1]; 10229 u8 reserved_at_3[0x5]; 10230 u8 local_port[0x8]; 10231 u8 reserved_at_10[0x8]; 10232 u8 plane_ind[0x4]; 10233 u8 reserved_at_1c[0x1]; 10234 u8 proto_mask[0x3]; 10235 10236 u8 an_status[0x4]; 10237 u8 reserved_at_24[0xc]; 10238 u8 data_rate_oper[0x10]; 10239 10240 u8 ext_eth_proto_capability[0x20]; 10241 10242 u8 eth_proto_capability[0x20]; 10243 10244 u8 ib_link_width_capability[0x10]; 10245 u8 ib_proto_capability[0x10]; 10246 10247 u8 ext_eth_proto_admin[0x20]; 10248 10249 u8 eth_proto_admin[0x20]; 10250 10251 u8 ib_link_width_admin[0x10]; 10252 u8 ib_proto_admin[0x10]; 10253 10254 u8 ext_eth_proto_oper[0x20]; 10255 10256 u8 eth_proto_oper[0x20]; 10257 10258 u8 ib_link_width_oper[0x10]; 10259 u8 ib_proto_oper[0x10]; 10260 10261 u8 reserved_at_160[0x8]; 10262 u8 lane_rate_oper[0x14]; 10263 u8 connector_type[0x4]; 10264 10265 u8 eth_proto_lp_advertise[0x20]; 10266 10267 u8 reserved_at_1a0[0x60]; 10268 }; 10269 10270 struct mlx5_ifc_mlcr_reg_bits { 10271 u8 reserved_at_0[0x8]; 10272 u8 local_port[0x8]; 10273 u8 reserved_at_10[0x20]; 10274 10275 u8 beacon_duration[0x10]; 10276 u8 reserved_at_40[0x10]; 10277 10278 u8 beacon_remain[0x10]; 10279 }; 10280 10281 struct mlx5_ifc_ptas_reg_bits { 10282 u8 reserved_at_0[0x20]; 10283 10284 u8 algorithm_options[0x10]; 10285 u8 reserved_at_30[0x4]; 10286 u8 repetitions_mode[0x4]; 10287 u8 num_of_repetitions[0x8]; 10288 10289 u8 grade_version[0x8]; 10290 u8 height_grade_type[0x4]; 10291 u8 phase_grade_type[0x4]; 10292 u8 height_grade_weight[0x8]; 10293 u8 phase_grade_weight[0x8]; 10294 10295 u8 gisim_measure_bits[0x10]; 10296 u8 adaptive_tap_measure_bits[0x10]; 10297 10298 u8 ber_bath_high_error_threshold[0x10]; 10299 u8 ber_bath_mid_error_threshold[0x10]; 10300 10301 u8 ber_bath_low_error_threshold[0x10]; 10302 u8 one_ratio_high_threshold[0x10]; 10303 10304 u8 one_ratio_high_mid_threshold[0x10]; 10305 u8 one_ratio_low_mid_threshold[0x10]; 10306 10307 u8 one_ratio_low_threshold[0x10]; 10308 u8 ndeo_error_threshold[0x10]; 10309 10310 u8 mixer_offset_step_size[0x10]; 10311 u8 reserved_at_110[0x8]; 10312 u8 mix90_phase_for_voltage_bath[0x8]; 10313 10314 u8 mixer_offset_start[0x10]; 10315 u8 mixer_offset_end[0x10]; 10316 10317 u8 reserved_at_140[0x15]; 10318 u8 ber_test_time[0xb]; 10319 }; 10320 10321 struct mlx5_ifc_pspa_reg_bits { 10322 u8 swid[0x8]; 10323 u8 local_port[0x8]; 10324 u8 sub_port[0x8]; 10325 u8 reserved_at_18[0x8]; 10326 10327 u8 reserved_at_20[0x20]; 10328 }; 10329 10330 struct mlx5_ifc_pqdr_reg_bits { 10331 u8 reserved_at_0[0x8]; 10332 u8 local_port[0x8]; 10333 u8 reserved_at_10[0x5]; 10334 u8 prio[0x3]; 10335 u8 reserved_at_18[0x6]; 10336 u8 mode[0x2]; 10337 10338 u8 reserved_at_20[0x20]; 10339 10340 u8 reserved_at_40[0x10]; 10341 u8 min_threshold[0x10]; 10342 10343 u8 reserved_at_60[0x10]; 10344 u8 max_threshold[0x10]; 10345 10346 u8 reserved_at_80[0x10]; 10347 u8 mark_probability_denominator[0x10]; 10348 10349 u8 reserved_at_a0[0x60]; 10350 }; 10351 10352 struct mlx5_ifc_ppsc_reg_bits { 10353 u8 reserved_at_0[0x8]; 10354 u8 local_port[0x8]; 10355 u8 reserved_at_10[0x10]; 10356 10357 u8 reserved_at_20[0x60]; 10358 10359 u8 reserved_at_80[0x1c]; 10360 u8 wrps_admin[0x4]; 10361 10362 u8 reserved_at_a0[0x1c]; 10363 u8 wrps_status[0x4]; 10364 10365 u8 reserved_at_c0[0x8]; 10366 u8 up_threshold[0x8]; 10367 u8 reserved_at_d0[0x8]; 10368 u8 down_threshold[0x8]; 10369 10370 u8 reserved_at_e0[0x20]; 10371 10372 u8 reserved_at_100[0x1c]; 10373 u8 srps_admin[0x4]; 10374 10375 u8 reserved_at_120[0x1c]; 10376 u8 srps_status[0x4]; 10377 10378 u8 reserved_at_140[0x40]; 10379 }; 10380 10381 struct mlx5_ifc_pplr_reg_bits { 10382 u8 reserved_at_0[0x8]; 10383 u8 local_port[0x8]; 10384 u8 reserved_at_10[0x10]; 10385 10386 u8 reserved_at_20[0x8]; 10387 u8 lb_cap[0x8]; 10388 u8 reserved_at_30[0x8]; 10389 u8 lb_en[0x8]; 10390 }; 10391 10392 struct mlx5_ifc_pplm_reg_bits { 10393 u8 reserved_at_0[0x8]; 10394 u8 local_port[0x8]; 10395 u8 reserved_at_10[0x10]; 10396 10397 u8 reserved_at_20[0x20]; 10398 10399 u8 port_profile_mode[0x8]; 10400 u8 static_port_profile[0x8]; 10401 u8 active_port_profile[0x8]; 10402 u8 reserved_at_58[0x8]; 10403 10404 u8 retransmission_active[0x8]; 10405 u8 fec_mode_active[0x18]; 10406 10407 u8 rs_fec_correction_bypass_cap[0x4]; 10408 u8 reserved_at_84[0x8]; 10409 u8 fec_override_cap_56g[0x4]; 10410 u8 fec_override_cap_100g[0x4]; 10411 u8 fec_override_cap_50g[0x4]; 10412 u8 fec_override_cap_25g[0x4]; 10413 u8 fec_override_cap_10g_40g[0x4]; 10414 10415 u8 rs_fec_correction_bypass_admin[0x4]; 10416 u8 reserved_at_a4[0x8]; 10417 u8 fec_override_admin_56g[0x4]; 10418 u8 fec_override_admin_100g[0x4]; 10419 u8 fec_override_admin_50g[0x4]; 10420 u8 fec_override_admin_25g[0x4]; 10421 u8 fec_override_admin_10g_40g[0x4]; 10422 10423 u8 fec_override_cap_400g_8x[0x10]; 10424 u8 fec_override_cap_200g_4x[0x10]; 10425 10426 u8 fec_override_cap_100g_2x[0x10]; 10427 u8 fec_override_cap_50g_1x[0x10]; 10428 10429 u8 fec_override_admin_400g_8x[0x10]; 10430 u8 fec_override_admin_200g_4x[0x10]; 10431 10432 u8 fec_override_admin_100g_2x[0x10]; 10433 u8 fec_override_admin_50g_1x[0x10]; 10434 10435 u8 fec_override_cap_800g_8x[0x10]; 10436 u8 fec_override_cap_400g_4x[0x10]; 10437 10438 u8 fec_override_cap_200g_2x[0x10]; 10439 u8 fec_override_cap_100g_1x[0x10]; 10440 10441 u8 reserved_at_180[0xa0]; 10442 10443 u8 fec_override_admin_800g_8x[0x10]; 10444 u8 fec_override_admin_400g_4x[0x10]; 10445 10446 u8 fec_override_admin_200g_2x[0x10]; 10447 u8 fec_override_admin_100g_1x[0x10]; 10448 10449 u8 reserved_at_260[0x60]; 10450 10451 u8 fec_override_cap_1600g_8x[0x10]; 10452 u8 fec_override_cap_800g_4x[0x10]; 10453 10454 u8 fec_override_cap_400g_2x[0x10]; 10455 u8 fec_override_cap_200g_1x[0x10]; 10456 10457 u8 fec_override_admin_1600g_8x[0x10]; 10458 u8 fec_override_admin_800g_4x[0x10]; 10459 10460 u8 fec_override_admin_400g_2x[0x10]; 10461 u8 fec_override_admin_200g_1x[0x10]; 10462 10463 u8 reserved_at_340[0x80]; 10464 }; 10465 10466 struct mlx5_ifc_ppcnt_reg_bits { 10467 u8 swid[0x8]; 10468 u8 local_port[0x8]; 10469 u8 pnat[0x2]; 10470 u8 reserved_at_12[0x8]; 10471 u8 grp[0x6]; 10472 10473 u8 clr[0x1]; 10474 u8 reserved_at_21[0x13]; 10475 u8 plane_ind[0x4]; 10476 u8 reserved_at_38[0x3]; 10477 u8 prio_tc[0x5]; 10478 10479 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set; 10480 }; 10481 10482 struct mlx5_ifc_mpein_reg_bits { 10483 u8 reserved_at_0[0x2]; 10484 u8 depth[0x6]; 10485 u8 pcie_index[0x8]; 10486 u8 node[0x8]; 10487 u8 reserved_at_18[0x8]; 10488 10489 u8 capability_mask[0x20]; 10490 10491 u8 reserved_at_40[0x8]; 10492 u8 link_width_enabled[0x8]; 10493 u8 link_speed_enabled[0x10]; 10494 10495 u8 lane0_physical_position[0x8]; 10496 u8 link_width_active[0x8]; 10497 u8 link_speed_active[0x10]; 10498 10499 u8 num_of_pfs[0x10]; 10500 u8 num_of_vfs[0x10]; 10501 10502 u8 bdf0[0x10]; 10503 u8 reserved_at_b0[0x10]; 10504 10505 u8 max_read_request_size[0x4]; 10506 u8 max_payload_size[0x4]; 10507 u8 reserved_at_c8[0x5]; 10508 u8 pwr_status[0x3]; 10509 u8 port_type[0x4]; 10510 u8 reserved_at_d4[0xb]; 10511 u8 lane_reversal[0x1]; 10512 10513 u8 reserved_at_e0[0x14]; 10514 u8 pci_power[0xc]; 10515 10516 u8 reserved_at_100[0x20]; 10517 10518 u8 device_status[0x10]; 10519 u8 port_state[0x8]; 10520 u8 reserved_at_138[0x8]; 10521 10522 u8 reserved_at_140[0x10]; 10523 u8 receiver_detect_result[0x10]; 10524 10525 u8 reserved_at_160[0x20]; 10526 }; 10527 10528 struct mlx5_ifc_mpcnt_reg_bits { 10529 u8 reserved_at_0[0x8]; 10530 u8 pcie_index[0x8]; 10531 u8 reserved_at_10[0xa]; 10532 u8 grp[0x6]; 10533 10534 u8 clr[0x1]; 10535 u8 reserved_at_21[0x1f]; 10536 10537 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set; 10538 }; 10539 10540 struct mlx5_ifc_ppad_reg_bits { 10541 u8 reserved_at_0[0x3]; 10542 u8 single_mac[0x1]; 10543 u8 reserved_at_4[0x4]; 10544 u8 local_port[0x8]; 10545 u8 mac_47_32[0x10]; 10546 10547 u8 mac_31_0[0x20]; 10548 10549 u8 reserved_at_40[0x40]; 10550 }; 10551 10552 struct mlx5_ifc_pmtu_reg_bits { 10553 u8 reserved_at_0[0x8]; 10554 u8 local_port[0x8]; 10555 u8 reserved_at_10[0x10]; 10556 10557 u8 max_mtu[0x10]; 10558 u8 reserved_at_30[0x10]; 10559 10560 u8 admin_mtu[0x10]; 10561 u8 reserved_at_50[0x10]; 10562 10563 u8 oper_mtu[0x10]; 10564 u8 reserved_at_70[0x10]; 10565 }; 10566 10567 struct mlx5_ifc_pmpr_reg_bits { 10568 u8 reserved_at_0[0x8]; 10569 u8 module[0x8]; 10570 u8 reserved_at_10[0x10]; 10571 10572 u8 reserved_at_20[0x18]; 10573 u8 attenuation_5g[0x8]; 10574 10575 u8 reserved_at_40[0x18]; 10576 u8 attenuation_7g[0x8]; 10577 10578 u8 reserved_at_60[0x18]; 10579 u8 attenuation_12g[0x8]; 10580 }; 10581 10582 struct mlx5_ifc_pmpe_reg_bits { 10583 u8 reserved_at_0[0x8]; 10584 u8 module[0x8]; 10585 u8 reserved_at_10[0xc]; 10586 u8 module_status[0x4]; 10587 10588 u8 reserved_at_20[0x60]; 10589 }; 10590 10591 struct mlx5_ifc_pmpc_reg_bits { 10592 u8 module_state_updated[32][0x8]; 10593 }; 10594 10595 struct mlx5_ifc_pmlpn_reg_bits { 10596 u8 reserved_at_0[0x4]; 10597 u8 mlpn_status[0x4]; 10598 u8 local_port[0x8]; 10599 u8 reserved_at_10[0x10]; 10600 10601 u8 e[0x1]; 10602 u8 reserved_at_21[0x1f]; 10603 }; 10604 10605 struct mlx5_ifc_pmlp_reg_bits { 10606 u8 rxtx[0x1]; 10607 u8 reserved_at_1[0x7]; 10608 u8 local_port[0x8]; 10609 u8 reserved_at_10[0x8]; 10610 u8 width[0x8]; 10611 10612 u8 lane0_module_mapping[0x20]; 10613 10614 u8 lane1_module_mapping[0x20]; 10615 10616 u8 lane2_module_mapping[0x20]; 10617 10618 u8 lane3_module_mapping[0x20]; 10619 10620 u8 reserved_at_a0[0x160]; 10621 }; 10622 10623 struct mlx5_ifc_pmaos_reg_bits { 10624 u8 reserved_at_0[0x8]; 10625 u8 module[0x8]; 10626 u8 reserved_at_10[0x4]; 10627 u8 admin_status[0x4]; 10628 u8 reserved_at_18[0x4]; 10629 u8 oper_status[0x4]; 10630 10631 u8 ase[0x1]; 10632 u8 ee[0x1]; 10633 u8 reserved_at_22[0x1c]; 10634 u8 e[0x2]; 10635 10636 u8 reserved_at_40[0x40]; 10637 }; 10638 10639 struct mlx5_ifc_plpc_reg_bits { 10640 u8 reserved_at_0[0x4]; 10641 u8 profile_id[0xc]; 10642 u8 reserved_at_10[0x4]; 10643 u8 proto_mask[0x4]; 10644 u8 reserved_at_18[0x8]; 10645 10646 u8 reserved_at_20[0x10]; 10647 u8 lane_speed[0x10]; 10648 10649 u8 reserved_at_40[0x17]; 10650 u8 lpbf[0x1]; 10651 u8 fec_mode_policy[0x8]; 10652 10653 u8 retransmission_capability[0x8]; 10654 u8 fec_mode_capability[0x18]; 10655 10656 u8 retransmission_support_admin[0x8]; 10657 u8 fec_mode_support_admin[0x18]; 10658 10659 u8 retransmission_request_admin[0x8]; 10660 u8 fec_mode_request_admin[0x18]; 10661 10662 u8 reserved_at_c0[0x80]; 10663 }; 10664 10665 struct mlx5_ifc_plib_reg_bits { 10666 u8 reserved_at_0[0x8]; 10667 u8 local_port[0x8]; 10668 u8 reserved_at_10[0x8]; 10669 u8 ib_port[0x8]; 10670 10671 u8 reserved_at_20[0x60]; 10672 }; 10673 10674 struct mlx5_ifc_plbf_reg_bits { 10675 u8 reserved_at_0[0x8]; 10676 u8 local_port[0x8]; 10677 u8 reserved_at_10[0xd]; 10678 u8 lbf_mode[0x3]; 10679 10680 u8 reserved_at_20[0x20]; 10681 }; 10682 10683 struct mlx5_ifc_pipg_reg_bits { 10684 u8 reserved_at_0[0x8]; 10685 u8 local_port[0x8]; 10686 u8 reserved_at_10[0x10]; 10687 10688 u8 dic[0x1]; 10689 u8 reserved_at_21[0x19]; 10690 u8 ipg[0x4]; 10691 u8 reserved_at_3e[0x2]; 10692 }; 10693 10694 struct mlx5_ifc_pifr_reg_bits { 10695 u8 reserved_at_0[0x8]; 10696 u8 local_port[0x8]; 10697 u8 reserved_at_10[0x10]; 10698 10699 u8 reserved_at_20[0xe0]; 10700 10701 u8 port_filter[8][0x20]; 10702 10703 u8 port_filter_update_en[8][0x20]; 10704 }; 10705 10706 enum { 10707 MLX5_BUF_OWNERSHIP_UNKNOWN = 0x0, 10708 MLX5_BUF_OWNERSHIP_FW_OWNED = 0x1, 10709 MLX5_BUF_OWNERSHIP_SW_OWNED = 0x2, 10710 }; 10711 10712 struct mlx5_ifc_pfcc_reg_bits { 10713 u8 reserved_at_0[0x4]; 10714 u8 buf_ownership[0x2]; 10715 u8 reserved_at_6[0x2]; 10716 u8 local_port[0x8]; 10717 u8 reserved_at_10[0xa]; 10718 u8 cable_length_mask[0x1]; 10719 u8 ppan_mask_n[0x1]; 10720 u8 minor_stall_mask[0x1]; 10721 u8 critical_stall_mask[0x1]; 10722 u8 reserved_at_1e[0x2]; 10723 10724 u8 ppan[0x4]; 10725 u8 reserved_at_24[0x4]; 10726 u8 prio_mask_tx[0x8]; 10727 u8 reserved_at_30[0x8]; 10728 u8 prio_mask_rx[0x8]; 10729 10730 u8 pptx[0x1]; 10731 u8 aptx[0x1]; 10732 u8 pptx_mask_n[0x1]; 10733 u8 reserved_at_43[0x5]; 10734 u8 pfctx[0x8]; 10735 u8 reserved_at_50[0x10]; 10736 10737 u8 pprx[0x1]; 10738 u8 aprx[0x1]; 10739 u8 pprx_mask_n[0x1]; 10740 u8 reserved_at_63[0x5]; 10741 u8 pfcrx[0x8]; 10742 u8 reserved_at_70[0x10]; 10743 10744 u8 device_stall_minor_watermark[0x10]; 10745 u8 device_stall_critical_watermark[0x10]; 10746 10747 u8 reserved_at_a0[0x18]; 10748 u8 cable_length[0x8]; 10749 10750 u8 reserved_at_c0[0x40]; 10751 }; 10752 10753 struct mlx5_ifc_pelc_reg_bits { 10754 u8 op[0x4]; 10755 u8 reserved_at_4[0x4]; 10756 u8 local_port[0x8]; 10757 u8 reserved_at_10[0x10]; 10758 10759 u8 op_admin[0x8]; 10760 u8 op_capability[0x8]; 10761 u8 op_request[0x8]; 10762 u8 op_active[0x8]; 10763 10764 u8 admin[0x40]; 10765 10766 u8 capability[0x40]; 10767 10768 u8 request[0x40]; 10769 10770 u8 active[0x40]; 10771 10772 u8 reserved_at_140[0x80]; 10773 }; 10774 10775 struct mlx5_ifc_peir_reg_bits { 10776 u8 reserved_at_0[0x8]; 10777 u8 local_port[0x8]; 10778 u8 reserved_at_10[0x10]; 10779 10780 u8 reserved_at_20[0xc]; 10781 u8 error_count[0x4]; 10782 u8 reserved_at_30[0x10]; 10783 10784 u8 reserved_at_40[0xc]; 10785 u8 lane[0x4]; 10786 u8 reserved_at_50[0x8]; 10787 u8 error_type[0x8]; 10788 }; 10789 10790 struct mlx5_ifc_mpegc_reg_bits { 10791 u8 reserved_at_0[0x30]; 10792 u8 field_select[0x10]; 10793 10794 u8 tx_overflow_sense[0x1]; 10795 u8 mark_cqe[0x1]; 10796 u8 mark_cnp[0x1]; 10797 u8 reserved_at_43[0x1b]; 10798 u8 tx_lossy_overflow_oper[0x2]; 10799 10800 u8 reserved_at_60[0x100]; 10801 }; 10802 10803 struct mlx5_ifc_mpir_reg_bits { 10804 u8 sdm[0x1]; 10805 u8 reserved_at_1[0x1b]; 10806 u8 host_buses[0x4]; 10807 10808 u8 reserved_at_20[0x20]; 10809 10810 u8 local_port[0x8]; 10811 u8 reserved_at_28[0x18]; 10812 10813 u8 reserved_at_60[0x20]; 10814 }; 10815 10816 enum { 10817 MLX5_MTUTC_FREQ_ADJ_UNITS_PPB = 0x0, 10818 MLX5_MTUTC_FREQ_ADJ_UNITS_SCALED_PPM = 0x1, 10819 }; 10820 10821 enum { 10822 MLX5_MTUTC_OPERATION_SET_TIME_IMMEDIATE = 0x1, 10823 MLX5_MTUTC_OPERATION_ADJUST_TIME = 0x2, 10824 MLX5_MTUTC_OPERATION_ADJUST_FREQ_UTC = 0x3, 10825 }; 10826 10827 struct mlx5_ifc_mtutc_reg_bits { 10828 u8 reserved_at_0[0x5]; 10829 u8 freq_adj_units[0x3]; 10830 u8 reserved_at_8[0x3]; 10831 u8 log_max_freq_adjustment[0x5]; 10832 10833 u8 reserved_at_10[0xc]; 10834 u8 operation[0x4]; 10835 10836 u8 freq_adjustment[0x20]; 10837 10838 u8 reserved_at_40[0x40]; 10839 10840 u8 utc_sec[0x20]; 10841 10842 u8 reserved_at_a0[0x2]; 10843 u8 utc_nsec[0x1e]; 10844 10845 u8 time_adjustment[0x20]; 10846 }; 10847 10848 struct mlx5_ifc_pcam_enhanced_features_bits { 10849 u8 reserved_at_0[0x10]; 10850 u8 ppcnt_recovery_counters[0x1]; 10851 u8 reserved_at_11[0x7]; 10852 u8 cable_length[0x1]; 10853 u8 reserved_at_19[0x4]; 10854 u8 fec_200G_per_lane_in_pplm[0x1]; 10855 u8 reserved_at_1e[0x2a]; 10856 u8 fec_100G_per_lane_in_pplm[0x1]; 10857 u8 reserved_at_49[0x2]; 10858 u8 shp_pbmc_pbsr_support[0x1]; 10859 u8 reserved_at_4c[0x7]; 10860 u8 buffer_ownership[0x1]; 10861 u8 resereved_at_54[0x14]; 10862 u8 fec_50G_per_lane_in_pplm[0x1]; 10863 u8 reserved_at_69[0x4]; 10864 u8 rx_icrc_encapsulated_counter[0x1]; 10865 u8 reserved_at_6e[0x4]; 10866 u8 ptys_extended_ethernet[0x1]; 10867 u8 reserved_at_73[0x3]; 10868 u8 pfcc_mask[0x1]; 10869 u8 reserved_at_77[0x3]; 10870 u8 per_lane_error_counters[0x1]; 10871 u8 rx_buffer_fullness_counters[0x1]; 10872 u8 ptys_connector_type[0x1]; 10873 u8 reserved_at_7d[0x1]; 10874 u8 ppcnt_discard_group[0x1]; 10875 u8 ppcnt_statistical_group[0x1]; 10876 }; 10877 10878 struct mlx5_ifc_pcam_regs_5000_to_507f_bits { 10879 u8 port_access_reg_cap_mask_127_to_96[0x20]; 10880 u8 port_access_reg_cap_mask_95_to_64[0x20]; 10881 10882 u8 port_access_reg_cap_mask_63[0x1]; 10883 u8 pphcr[0x1]; 10884 u8 port_access_reg_cap_mask_61_to_36[0x1a]; 10885 u8 pplm[0x1]; 10886 u8 port_access_reg_cap_mask_34_to_32[0x3]; 10887 10888 u8 port_access_reg_cap_mask_31_to_13[0x13]; 10889 u8 pbmc[0x1]; 10890 u8 pptb[0x1]; 10891 u8 port_access_reg_cap_mask_10_to_09[0x2]; 10892 u8 ppcnt[0x1]; 10893 u8 port_access_reg_cap_mask_07_to_00[0x8]; 10894 }; 10895 10896 struct mlx5_ifc_pcam_reg_bits { 10897 u8 reserved_at_0[0x8]; 10898 u8 feature_group[0x8]; 10899 u8 reserved_at_10[0x8]; 10900 u8 access_reg_group[0x8]; 10901 10902 u8 reserved_at_20[0x20]; 10903 10904 union { 10905 struct mlx5_ifc_pcam_regs_5000_to_507f_bits regs_5000_to_507f; 10906 u8 reserved_at_0[0x80]; 10907 } port_access_reg_cap_mask; 10908 10909 u8 reserved_at_c0[0x80]; 10910 10911 union { 10912 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features; 10913 u8 reserved_at_0[0x80]; 10914 } feature_cap_mask; 10915 10916 u8 reserved_at_1c0[0xc0]; 10917 }; 10918 10919 struct mlx5_ifc_mcam_enhanced_features_bits { 10920 u8 reserved_at_0[0x50]; 10921 u8 mtutc_freq_adj_units[0x1]; 10922 u8 mtutc_time_adjustment_extended_range[0x1]; 10923 u8 reserved_at_52[0xb]; 10924 u8 mcia_32dwords[0x1]; 10925 u8 out_pulse_duration_ns[0x1]; 10926 u8 npps_period[0x1]; 10927 u8 reserved_at_60[0xa]; 10928 u8 reset_state[0x1]; 10929 u8 ptpcyc2realtime_modify[0x1]; 10930 u8 reserved_at_6c[0x2]; 10931 u8 pci_status_and_power[0x1]; 10932 u8 reserved_at_6f[0x5]; 10933 u8 mark_tx_action_cnp[0x1]; 10934 u8 mark_tx_action_cqe[0x1]; 10935 u8 dynamic_tx_overflow[0x1]; 10936 u8 reserved_at_77[0x4]; 10937 u8 pcie_outbound_stalled[0x1]; 10938 u8 tx_overflow_buffer_pkt[0x1]; 10939 u8 mtpps_enh_out_per_adj[0x1]; 10940 u8 mtpps_fs[0x1]; 10941 u8 pcie_performance_group[0x1]; 10942 }; 10943 10944 struct mlx5_ifc_mcam_access_reg_bits { 10945 u8 reserved_at_0[0x1c]; 10946 u8 mcda[0x1]; 10947 u8 mcc[0x1]; 10948 u8 mcqi[0x1]; 10949 u8 mcqs[0x1]; 10950 10951 u8 regs_95_to_90[0x6]; 10952 u8 mpir[0x1]; 10953 u8 regs_88_to_87[0x2]; 10954 u8 mpegc[0x1]; 10955 u8 mtutc[0x1]; 10956 u8 regs_84_to_68[0x11]; 10957 u8 tracer_registers[0x4]; 10958 10959 u8 regs_63_to_46[0x12]; 10960 u8 mrtc[0x1]; 10961 u8 regs_44_to_41[0x4]; 10962 u8 mfrl[0x1]; 10963 u8 regs_39_to_32[0x8]; 10964 10965 u8 regs_31_to_11[0x15]; 10966 u8 mtmp[0x1]; 10967 u8 regs_9_to_0[0xa]; 10968 }; 10969 10970 struct mlx5_ifc_mcam_access_reg_bits1 { 10971 u8 regs_127_to_96[0x20]; 10972 10973 u8 regs_95_to_64[0x20]; 10974 10975 u8 regs_63_to_32[0x20]; 10976 10977 u8 regs_31_to_0[0x20]; 10978 }; 10979 10980 struct mlx5_ifc_mcam_access_reg_bits2 { 10981 u8 regs_127_to_99[0x1d]; 10982 u8 mirc[0x1]; 10983 u8 regs_97_to_96[0x2]; 10984 10985 u8 regs_95_to_87[0x09]; 10986 u8 synce_registers[0x2]; 10987 u8 regs_84_to_64[0x15]; 10988 10989 u8 regs_63_to_32[0x20]; 10990 10991 u8 regs_31_to_0[0x20]; 10992 }; 10993 10994 struct mlx5_ifc_mcam_access_reg_bits3 { 10995 u8 regs_127_to_96[0x20]; 10996 10997 u8 regs_95_to_64[0x20]; 10998 10999 u8 regs_63_to_32[0x20]; 11000 11001 u8 regs_31_to_3[0x1d]; 11002 u8 mrtcq[0x1]; 11003 u8 mtctr[0x1]; 11004 u8 mtptm[0x1]; 11005 }; 11006 11007 struct mlx5_ifc_mcam_reg_bits { 11008 u8 reserved_at_0[0x8]; 11009 u8 feature_group[0x8]; 11010 u8 reserved_at_10[0x8]; 11011 u8 access_reg_group[0x8]; 11012 11013 u8 reserved_at_20[0x20]; 11014 11015 union { 11016 struct mlx5_ifc_mcam_access_reg_bits access_regs; 11017 struct mlx5_ifc_mcam_access_reg_bits1 access_regs1; 11018 struct mlx5_ifc_mcam_access_reg_bits2 access_regs2; 11019 struct mlx5_ifc_mcam_access_reg_bits3 access_regs3; 11020 u8 reserved_at_0[0x80]; 11021 } mng_access_reg_cap_mask; 11022 11023 u8 reserved_at_c0[0x80]; 11024 11025 union { 11026 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features; 11027 u8 reserved_at_0[0x80]; 11028 } mng_feature_cap_mask; 11029 11030 u8 reserved_at_1c0[0x80]; 11031 }; 11032 11033 struct mlx5_ifc_qcam_access_reg_cap_mask { 11034 u8 qcam_access_reg_cap_mask_127_to_20[0x6C]; 11035 u8 qpdpm[0x1]; 11036 u8 qcam_access_reg_cap_mask_18_to_4[0x0F]; 11037 u8 qdpm[0x1]; 11038 u8 qpts[0x1]; 11039 u8 qcap[0x1]; 11040 u8 qcam_access_reg_cap_mask_0[0x1]; 11041 }; 11042 11043 struct mlx5_ifc_qcam_qos_feature_cap_mask { 11044 u8 qcam_qos_feature_cap_mask_127_to_5[0x7B]; 11045 u8 qetcr_qshr_max_bw_val_msb[0x1]; 11046 u8 qcam_qos_feature_cap_mask_3_to_1[0x3]; 11047 u8 qpts_trust_both[0x1]; 11048 }; 11049 11050 struct mlx5_ifc_qcam_reg_bits { 11051 u8 reserved_at_0[0x8]; 11052 u8 feature_group[0x8]; 11053 u8 reserved_at_10[0x8]; 11054 u8 access_reg_group[0x8]; 11055 u8 reserved_at_20[0x20]; 11056 11057 union { 11058 struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap; 11059 u8 reserved_at_0[0x80]; 11060 } qos_access_reg_cap_mask; 11061 11062 u8 reserved_at_c0[0x80]; 11063 11064 union { 11065 struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap; 11066 u8 reserved_at_0[0x80]; 11067 } qos_feature_cap_mask; 11068 11069 u8 reserved_at_1c0[0x80]; 11070 }; 11071 11072 struct mlx5_ifc_core_dump_reg_bits { 11073 u8 reserved_at_0[0x18]; 11074 u8 core_dump_type[0x8]; 11075 11076 u8 reserved_at_20[0x30]; 11077 u8 vhca_id[0x10]; 11078 11079 u8 reserved_at_60[0x8]; 11080 u8 qpn[0x18]; 11081 u8 reserved_at_80[0x180]; 11082 }; 11083 11084 struct mlx5_ifc_pcap_reg_bits { 11085 u8 reserved_at_0[0x8]; 11086 u8 local_port[0x8]; 11087 u8 reserved_at_10[0x10]; 11088 11089 u8 port_capability_mask[4][0x20]; 11090 }; 11091 11092 struct mlx5_ifc_paos_reg_bits { 11093 u8 swid[0x8]; 11094 u8 local_port[0x8]; 11095 u8 reserved_at_10[0x4]; 11096 u8 admin_status[0x4]; 11097 u8 reserved_at_18[0x4]; 11098 u8 oper_status[0x4]; 11099 11100 u8 ase[0x1]; 11101 u8 ee[0x1]; 11102 u8 reserved_at_22[0x1c]; 11103 u8 e[0x2]; 11104 11105 u8 reserved_at_40[0x40]; 11106 }; 11107 11108 struct mlx5_ifc_pamp_reg_bits { 11109 u8 reserved_at_0[0x8]; 11110 u8 opamp_group[0x8]; 11111 u8 reserved_at_10[0xc]; 11112 u8 opamp_group_type[0x4]; 11113 11114 u8 start_index[0x10]; 11115 u8 reserved_at_30[0x4]; 11116 u8 num_of_indices[0xc]; 11117 11118 u8 index_data[18][0x10]; 11119 }; 11120 11121 struct mlx5_ifc_pcmr_reg_bits { 11122 u8 reserved_at_0[0x8]; 11123 u8 local_port[0x8]; 11124 u8 reserved_at_10[0x10]; 11125 11126 u8 entropy_force_cap[0x1]; 11127 u8 entropy_calc_cap[0x1]; 11128 u8 entropy_gre_calc_cap[0x1]; 11129 u8 reserved_at_23[0xf]; 11130 u8 rx_ts_over_crc_cap[0x1]; 11131 u8 reserved_at_33[0xb]; 11132 u8 fcs_cap[0x1]; 11133 u8 reserved_at_3f[0x1]; 11134 11135 u8 entropy_force[0x1]; 11136 u8 entropy_calc[0x1]; 11137 u8 entropy_gre_calc[0x1]; 11138 u8 reserved_at_43[0xf]; 11139 u8 rx_ts_over_crc[0x1]; 11140 u8 reserved_at_53[0xb]; 11141 u8 fcs_chk[0x1]; 11142 u8 reserved_at_5f[0x1]; 11143 }; 11144 11145 struct mlx5_ifc_lane_2_module_mapping_bits { 11146 u8 reserved_at_0[0x4]; 11147 u8 rx_lane[0x4]; 11148 u8 reserved_at_8[0x4]; 11149 u8 tx_lane[0x4]; 11150 u8 reserved_at_10[0x8]; 11151 u8 module[0x8]; 11152 }; 11153 11154 struct mlx5_ifc_bufferx_reg_bits { 11155 u8 reserved_at_0[0x6]; 11156 u8 lossy[0x1]; 11157 u8 epsb[0x1]; 11158 u8 reserved_at_8[0x8]; 11159 u8 size[0x10]; 11160 11161 u8 xoff_threshold[0x10]; 11162 u8 xon_threshold[0x10]; 11163 }; 11164 11165 struct mlx5_ifc_set_node_in_bits { 11166 u8 node_description[64][0x8]; 11167 }; 11168 11169 struct mlx5_ifc_register_power_settings_bits { 11170 u8 reserved_at_0[0x18]; 11171 u8 power_settings_level[0x8]; 11172 11173 u8 reserved_at_20[0x60]; 11174 }; 11175 11176 struct mlx5_ifc_register_host_endianness_bits { 11177 u8 he[0x1]; 11178 u8 reserved_at_1[0x1f]; 11179 11180 u8 reserved_at_20[0x60]; 11181 }; 11182 11183 struct mlx5_ifc_umr_pointer_desc_argument_bits { 11184 u8 reserved_at_0[0x20]; 11185 11186 u8 mkey[0x20]; 11187 11188 u8 addressh_63_32[0x20]; 11189 11190 u8 addressl_31_0[0x20]; 11191 }; 11192 11193 struct mlx5_ifc_ud_adrs_vector_bits { 11194 u8 dc_key[0x40]; 11195 11196 u8 ext[0x1]; 11197 u8 reserved_at_41[0x7]; 11198 u8 destination_qp_dct[0x18]; 11199 11200 u8 static_rate[0x4]; 11201 u8 sl_eth_prio[0x4]; 11202 u8 fl[0x1]; 11203 u8 mlid[0x7]; 11204 u8 rlid_udp_sport[0x10]; 11205 11206 u8 reserved_at_80[0x20]; 11207 11208 u8 rmac_47_16[0x20]; 11209 11210 u8 rmac_15_0[0x10]; 11211 u8 tclass[0x8]; 11212 u8 hop_limit[0x8]; 11213 11214 u8 reserved_at_e0[0x1]; 11215 u8 grh[0x1]; 11216 u8 reserved_at_e2[0x2]; 11217 u8 src_addr_index[0x8]; 11218 u8 flow_label[0x14]; 11219 11220 u8 rgid_rip[16][0x8]; 11221 }; 11222 11223 struct mlx5_ifc_pages_req_event_bits { 11224 u8 reserved_at_0[0x10]; 11225 u8 function_id[0x10]; 11226 11227 u8 num_pages[0x20]; 11228 11229 u8 reserved_at_40[0xa0]; 11230 }; 11231 11232 struct mlx5_ifc_eqe_bits { 11233 u8 reserved_at_0[0x8]; 11234 u8 event_type[0x8]; 11235 u8 reserved_at_10[0x8]; 11236 u8 event_sub_type[0x8]; 11237 11238 u8 reserved_at_20[0xe0]; 11239 11240 union mlx5_ifc_event_auto_bits event_data; 11241 11242 u8 reserved_at_1e0[0x10]; 11243 u8 signature[0x8]; 11244 u8 reserved_at_1f8[0x7]; 11245 u8 owner[0x1]; 11246 }; 11247 11248 enum { 11249 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7, 11250 }; 11251 11252 struct mlx5_ifc_cmd_queue_entry_bits { 11253 u8 type[0x8]; 11254 u8 reserved_at_8[0x18]; 11255 11256 u8 input_length[0x20]; 11257 11258 u8 input_mailbox_pointer_63_32[0x20]; 11259 11260 u8 input_mailbox_pointer_31_9[0x17]; 11261 u8 reserved_at_77[0x9]; 11262 11263 u8 command_input_inline_data[16][0x8]; 11264 11265 u8 command_output_inline_data[16][0x8]; 11266 11267 u8 output_mailbox_pointer_63_32[0x20]; 11268 11269 u8 output_mailbox_pointer_31_9[0x17]; 11270 u8 reserved_at_1b7[0x9]; 11271 11272 u8 output_length[0x20]; 11273 11274 u8 token[0x8]; 11275 u8 signature[0x8]; 11276 u8 reserved_at_1f0[0x8]; 11277 u8 status[0x7]; 11278 u8 ownership[0x1]; 11279 }; 11280 11281 struct mlx5_ifc_cmd_out_bits { 11282 u8 status[0x8]; 11283 u8 reserved_at_8[0x18]; 11284 11285 u8 syndrome[0x20]; 11286 11287 u8 command_output[0x20]; 11288 }; 11289 11290 struct mlx5_ifc_cmd_in_bits { 11291 u8 opcode[0x10]; 11292 u8 reserved_at_10[0x10]; 11293 11294 u8 reserved_at_20[0x10]; 11295 u8 op_mod[0x10]; 11296 11297 u8 command[][0x20]; 11298 }; 11299 11300 struct mlx5_ifc_cmd_if_box_bits { 11301 u8 mailbox_data[512][0x8]; 11302 11303 u8 reserved_at_1000[0x180]; 11304 11305 u8 next_pointer_63_32[0x20]; 11306 11307 u8 next_pointer_31_10[0x16]; 11308 u8 reserved_at_11b6[0xa]; 11309 11310 u8 block_number[0x20]; 11311 11312 u8 reserved_at_11e0[0x8]; 11313 u8 token[0x8]; 11314 u8 ctrl_signature[0x8]; 11315 u8 signature[0x8]; 11316 }; 11317 11318 struct mlx5_ifc_mtt_bits { 11319 u8 ptag_63_32[0x20]; 11320 11321 u8 ptag_31_8[0x18]; 11322 u8 reserved_at_38[0x6]; 11323 u8 wr_en[0x1]; 11324 u8 rd_en[0x1]; 11325 }; 11326 11327 struct mlx5_ifc_query_wol_rol_out_bits { 11328 u8 status[0x8]; 11329 u8 reserved_at_8[0x18]; 11330 11331 u8 syndrome[0x20]; 11332 11333 u8 reserved_at_40[0x10]; 11334 u8 rol_mode[0x8]; 11335 u8 wol_mode[0x8]; 11336 11337 u8 reserved_at_60[0x20]; 11338 }; 11339 11340 struct mlx5_ifc_query_wol_rol_in_bits { 11341 u8 opcode[0x10]; 11342 u8 reserved_at_10[0x10]; 11343 11344 u8 reserved_at_20[0x10]; 11345 u8 op_mod[0x10]; 11346 11347 u8 reserved_at_40[0x40]; 11348 }; 11349 11350 struct mlx5_ifc_set_wol_rol_out_bits { 11351 u8 status[0x8]; 11352 u8 reserved_at_8[0x18]; 11353 11354 u8 syndrome[0x20]; 11355 11356 u8 reserved_at_40[0x40]; 11357 }; 11358 11359 struct mlx5_ifc_set_wol_rol_in_bits { 11360 u8 opcode[0x10]; 11361 u8 reserved_at_10[0x10]; 11362 11363 u8 reserved_at_20[0x10]; 11364 u8 op_mod[0x10]; 11365 11366 u8 rol_mode_valid[0x1]; 11367 u8 wol_mode_valid[0x1]; 11368 u8 reserved_at_42[0xe]; 11369 u8 rol_mode[0x8]; 11370 u8 wol_mode[0x8]; 11371 11372 u8 reserved_at_60[0x20]; 11373 }; 11374 11375 enum { 11376 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0, 11377 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1, 11378 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2, 11379 MLX5_INITIAL_SEG_NIC_INTERFACE_SW_RESET = 0x7, 11380 }; 11381 11382 enum { 11383 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0, 11384 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1, 11385 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2, 11386 }; 11387 11388 enum { 11389 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR = 0x1, 11390 MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC = 0x7, 11391 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR = 0x8, 11392 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR = 0x9, 11393 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR = 0xa, 11394 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR = 0xb, 11395 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN = 0xc, 11396 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR = 0xd, 11397 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV = 0xe, 11398 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR = 0xf, 11399 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR = 0x10, 11400 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PCI_POISONED_ERR = 0x12, 11401 MLX5_INITIAL_SEG_HEALTH_SYNDROME_TRUST_LOCKDOWN_ERR = 0x13, 11402 }; 11403 11404 struct mlx5_ifc_initial_seg_bits { 11405 u8 fw_rev_minor[0x10]; 11406 u8 fw_rev_major[0x10]; 11407 11408 u8 cmd_interface_rev[0x10]; 11409 u8 fw_rev_subminor[0x10]; 11410 11411 u8 reserved_at_40[0x40]; 11412 11413 u8 cmdq_phy_addr_63_32[0x20]; 11414 11415 u8 cmdq_phy_addr_31_12[0x14]; 11416 u8 reserved_at_b4[0x2]; 11417 u8 nic_interface[0x2]; 11418 u8 log_cmdq_size[0x4]; 11419 u8 log_cmdq_stride[0x4]; 11420 11421 u8 command_doorbell_vector[0x20]; 11422 11423 u8 reserved_at_e0[0xf00]; 11424 11425 u8 initializing[0x1]; 11426 u8 reserved_at_fe1[0x4]; 11427 u8 nic_interface_supported[0x3]; 11428 u8 embedded_cpu[0x1]; 11429 u8 reserved_at_fe9[0x17]; 11430 11431 struct mlx5_ifc_health_buffer_bits health_buffer; 11432 11433 u8 no_dram_nic_offset[0x20]; 11434 11435 u8 reserved_at_1220[0x6e40]; 11436 11437 u8 reserved_at_8060[0x1f]; 11438 u8 clear_int[0x1]; 11439 11440 u8 health_syndrome[0x8]; 11441 u8 health_counter[0x18]; 11442 11443 u8 reserved_at_80a0[0x17fc0]; 11444 }; 11445 11446 struct mlx5_ifc_mtpps_reg_bits { 11447 u8 reserved_at_0[0xc]; 11448 u8 cap_number_of_pps_pins[0x4]; 11449 u8 reserved_at_10[0x4]; 11450 u8 cap_max_num_of_pps_in_pins[0x4]; 11451 u8 reserved_at_18[0x4]; 11452 u8 cap_max_num_of_pps_out_pins[0x4]; 11453 11454 u8 reserved_at_20[0x13]; 11455 u8 cap_log_min_npps_period[0x5]; 11456 u8 reserved_at_38[0x3]; 11457 u8 cap_log_min_out_pulse_duration_ns[0x5]; 11458 11459 u8 reserved_at_40[0x4]; 11460 u8 cap_pin_3_mode[0x4]; 11461 u8 reserved_at_48[0x4]; 11462 u8 cap_pin_2_mode[0x4]; 11463 u8 reserved_at_50[0x4]; 11464 u8 cap_pin_1_mode[0x4]; 11465 u8 reserved_at_58[0x4]; 11466 u8 cap_pin_0_mode[0x4]; 11467 11468 u8 reserved_at_60[0x4]; 11469 u8 cap_pin_7_mode[0x4]; 11470 u8 reserved_at_68[0x4]; 11471 u8 cap_pin_6_mode[0x4]; 11472 u8 reserved_at_70[0x4]; 11473 u8 cap_pin_5_mode[0x4]; 11474 u8 reserved_at_78[0x4]; 11475 u8 cap_pin_4_mode[0x4]; 11476 11477 u8 field_select[0x20]; 11478 u8 reserved_at_a0[0x20]; 11479 11480 u8 npps_period[0x40]; 11481 11482 u8 enable[0x1]; 11483 u8 reserved_at_101[0xb]; 11484 u8 pattern[0x4]; 11485 u8 reserved_at_110[0x4]; 11486 u8 pin_mode[0x4]; 11487 u8 pin[0x8]; 11488 11489 u8 reserved_at_120[0x2]; 11490 u8 out_pulse_duration_ns[0x1e]; 11491 11492 u8 time_stamp[0x40]; 11493 11494 u8 out_pulse_duration[0x10]; 11495 u8 out_periodic_adjustment[0x10]; 11496 u8 enhanced_out_periodic_adjustment[0x20]; 11497 11498 u8 reserved_at_1c0[0x20]; 11499 }; 11500 11501 struct mlx5_ifc_mtppse_reg_bits { 11502 u8 reserved_at_0[0x18]; 11503 u8 pin[0x8]; 11504 u8 event_arm[0x1]; 11505 u8 reserved_at_21[0x1b]; 11506 u8 event_generation_mode[0x4]; 11507 u8 reserved_at_40[0x40]; 11508 }; 11509 11510 struct mlx5_ifc_mcqs_reg_bits { 11511 u8 last_index_flag[0x1]; 11512 u8 reserved_at_1[0x7]; 11513 u8 fw_device[0x8]; 11514 u8 component_index[0x10]; 11515 11516 u8 reserved_at_20[0x10]; 11517 u8 identifier[0x10]; 11518 11519 u8 reserved_at_40[0x17]; 11520 u8 component_status[0x5]; 11521 u8 component_update_state[0x4]; 11522 11523 u8 last_update_state_changer_type[0x4]; 11524 u8 last_update_state_changer_host_id[0x4]; 11525 u8 reserved_at_68[0x18]; 11526 }; 11527 11528 struct mlx5_ifc_mcqi_cap_bits { 11529 u8 supported_info_bitmask[0x20]; 11530 11531 u8 component_size[0x20]; 11532 11533 u8 max_component_size[0x20]; 11534 11535 u8 log_mcda_word_size[0x4]; 11536 u8 reserved_at_64[0xc]; 11537 u8 mcda_max_write_size[0x10]; 11538 11539 u8 rd_en[0x1]; 11540 u8 reserved_at_81[0x1]; 11541 u8 match_chip_id[0x1]; 11542 u8 match_psid[0x1]; 11543 u8 check_user_timestamp[0x1]; 11544 u8 match_base_guid_mac[0x1]; 11545 u8 reserved_at_86[0x1a]; 11546 }; 11547 11548 struct mlx5_ifc_mcqi_version_bits { 11549 u8 reserved_at_0[0x2]; 11550 u8 build_time_valid[0x1]; 11551 u8 user_defined_time_valid[0x1]; 11552 u8 reserved_at_4[0x14]; 11553 u8 version_string_length[0x8]; 11554 11555 u8 version[0x20]; 11556 11557 u8 build_time[0x40]; 11558 11559 u8 user_defined_time[0x40]; 11560 11561 u8 build_tool_version[0x20]; 11562 11563 u8 reserved_at_e0[0x20]; 11564 11565 u8 version_string[92][0x8]; 11566 }; 11567 11568 struct mlx5_ifc_mcqi_activation_method_bits { 11569 u8 pending_server_ac_power_cycle[0x1]; 11570 u8 pending_server_dc_power_cycle[0x1]; 11571 u8 pending_server_reboot[0x1]; 11572 u8 pending_fw_reset[0x1]; 11573 u8 auto_activate[0x1]; 11574 u8 all_hosts_sync[0x1]; 11575 u8 device_hw_reset[0x1]; 11576 u8 reserved_at_7[0x19]; 11577 }; 11578 11579 union mlx5_ifc_mcqi_reg_data_bits { 11580 struct mlx5_ifc_mcqi_cap_bits mcqi_caps; 11581 struct mlx5_ifc_mcqi_version_bits mcqi_version; 11582 struct mlx5_ifc_mcqi_activation_method_bits mcqi_activation_mathod; 11583 }; 11584 11585 struct mlx5_ifc_mcqi_reg_bits { 11586 u8 read_pending_component[0x1]; 11587 u8 reserved_at_1[0xf]; 11588 u8 component_index[0x10]; 11589 11590 u8 reserved_at_20[0x20]; 11591 11592 u8 reserved_at_40[0x1b]; 11593 u8 info_type[0x5]; 11594 11595 u8 info_size[0x20]; 11596 11597 u8 offset[0x20]; 11598 11599 u8 reserved_at_a0[0x10]; 11600 u8 data_size[0x10]; 11601 11602 union mlx5_ifc_mcqi_reg_data_bits data[]; 11603 }; 11604 11605 struct mlx5_ifc_mcc_reg_bits { 11606 u8 reserved_at_0[0x4]; 11607 u8 time_elapsed_since_last_cmd[0xc]; 11608 u8 reserved_at_10[0x8]; 11609 u8 instruction[0x8]; 11610 11611 u8 reserved_at_20[0x10]; 11612 u8 component_index[0x10]; 11613 11614 u8 reserved_at_40[0x8]; 11615 u8 update_handle[0x18]; 11616 11617 u8 handle_owner_type[0x4]; 11618 u8 handle_owner_host_id[0x4]; 11619 u8 reserved_at_68[0x1]; 11620 u8 control_progress[0x7]; 11621 u8 error_code[0x8]; 11622 u8 reserved_at_78[0x4]; 11623 u8 control_state[0x4]; 11624 11625 u8 component_size[0x20]; 11626 11627 u8 reserved_at_a0[0x60]; 11628 }; 11629 11630 struct mlx5_ifc_mcda_reg_bits { 11631 u8 reserved_at_0[0x8]; 11632 u8 update_handle[0x18]; 11633 11634 u8 offset[0x20]; 11635 11636 u8 reserved_at_40[0x10]; 11637 u8 size[0x10]; 11638 11639 u8 reserved_at_60[0x20]; 11640 11641 u8 data[][0x20]; 11642 }; 11643 11644 enum { 11645 MLX5_MFRL_REG_PCI_RESET_METHOD_LINK_TOGGLE = 0, 11646 MLX5_MFRL_REG_PCI_RESET_METHOD_HOT_RESET = 1, 11647 }; 11648 11649 enum { 11650 MLX5_MFRL_REG_RESET_STATE_IDLE = 0, 11651 MLX5_MFRL_REG_RESET_STATE_IN_NEGOTIATION = 1, 11652 MLX5_MFRL_REG_RESET_STATE_RESET_IN_PROGRESS = 2, 11653 MLX5_MFRL_REG_RESET_STATE_NEG_TIMEOUT = 3, 11654 MLX5_MFRL_REG_RESET_STATE_NACK = 4, 11655 MLX5_MFRL_REG_RESET_STATE_UNLOAD_TIMEOUT = 5, 11656 }; 11657 11658 enum { 11659 MLX5_MFRL_REG_RESET_TYPE_FULL_CHIP = BIT(0), 11660 MLX5_MFRL_REG_RESET_TYPE_NET_PORT_ALIVE = BIT(1), 11661 }; 11662 11663 enum { 11664 MLX5_MFRL_REG_RESET_LEVEL0 = BIT(0), 11665 MLX5_MFRL_REG_RESET_LEVEL3 = BIT(3), 11666 MLX5_MFRL_REG_RESET_LEVEL6 = BIT(6), 11667 }; 11668 11669 struct mlx5_ifc_mfrl_reg_bits { 11670 u8 reserved_at_0[0x20]; 11671 11672 u8 reserved_at_20[0x2]; 11673 u8 pci_sync_for_fw_update_start[0x1]; 11674 u8 pci_sync_for_fw_update_resp[0x2]; 11675 u8 rst_type_sel[0x3]; 11676 u8 pci_reset_req_method[0x3]; 11677 u8 reserved_at_2b[0x1]; 11678 u8 reset_state[0x4]; 11679 u8 reset_type[0x8]; 11680 u8 reset_level[0x8]; 11681 }; 11682 11683 struct mlx5_ifc_mirc_reg_bits { 11684 u8 reserved_at_0[0x18]; 11685 u8 status_code[0x8]; 11686 11687 u8 reserved_at_20[0x20]; 11688 }; 11689 11690 struct mlx5_ifc_pddr_monitor_opcode_bits { 11691 u8 reserved_at_0[0x10]; 11692 u8 monitor_opcode[0x10]; 11693 }; 11694 11695 union mlx5_ifc_pddr_troubleshooting_page_status_opcode_auto_bits { 11696 struct mlx5_ifc_pddr_monitor_opcode_bits pddr_monitor_opcode; 11697 u8 reserved_at_0[0x20]; 11698 }; 11699 11700 enum { 11701 /* Monitor opcodes */ 11702 MLX5_PDDR_REG_TRBLSH_GROUP_OPCODE_MONITOR = 0x0, 11703 }; 11704 11705 struct mlx5_ifc_pddr_troubleshooting_page_bits { 11706 u8 reserved_at_0[0x10]; 11707 u8 group_opcode[0x10]; 11708 11709 union mlx5_ifc_pddr_troubleshooting_page_status_opcode_auto_bits status_opcode; 11710 11711 u8 reserved_at_40[0x20]; 11712 11713 u8 status_message[59][0x20]; 11714 }; 11715 11716 union mlx5_ifc_pddr_reg_page_data_auto_bits { 11717 struct mlx5_ifc_pddr_troubleshooting_page_bits pddr_troubleshooting_page; 11718 u8 reserved_at_0[0x7c0]; 11719 }; 11720 11721 enum { 11722 MLX5_PDDR_REG_PAGE_SELECT_TROUBLESHOOTING_INFO_PAGE = 0x1, 11723 }; 11724 11725 struct mlx5_ifc_pddr_reg_bits { 11726 u8 reserved_at_0[0x8]; 11727 u8 local_port[0x8]; 11728 u8 pnat[0x2]; 11729 u8 reserved_at_12[0xe]; 11730 11731 u8 reserved_at_20[0x18]; 11732 u8 page_select[0x8]; 11733 11734 union mlx5_ifc_pddr_reg_page_data_auto_bits page_data; 11735 }; 11736 11737 struct mlx5_ifc_mrtc_reg_bits { 11738 u8 time_synced[0x1]; 11739 u8 reserved_at_1[0x1f]; 11740 11741 u8 reserved_at_20[0x20]; 11742 11743 u8 time_h[0x20]; 11744 11745 u8 time_l[0x20]; 11746 }; 11747 11748 struct mlx5_ifc_mtcap_reg_bits { 11749 u8 reserved_at_0[0x19]; 11750 u8 sensor_count[0x7]; 11751 11752 u8 reserved_at_20[0x20]; 11753 11754 u8 sensor_map[0x40]; 11755 }; 11756 11757 struct mlx5_ifc_mtmp_reg_bits { 11758 u8 reserved_at_0[0x14]; 11759 u8 sensor_index[0xc]; 11760 11761 u8 reserved_at_20[0x10]; 11762 u8 temperature[0x10]; 11763 11764 u8 mte[0x1]; 11765 u8 mtr[0x1]; 11766 u8 reserved_at_42[0xe]; 11767 u8 max_temperature[0x10]; 11768 11769 u8 tee[0x2]; 11770 u8 reserved_at_62[0xe]; 11771 u8 temp_threshold_hi[0x10]; 11772 11773 u8 reserved_at_80[0x10]; 11774 u8 temp_threshold_lo[0x10]; 11775 11776 u8 reserved_at_a0[0x20]; 11777 11778 u8 sensor_name_hi[0x20]; 11779 u8 sensor_name_lo[0x20]; 11780 }; 11781 11782 struct mlx5_ifc_mtptm_reg_bits { 11783 u8 reserved_at_0[0x10]; 11784 u8 psta[0x1]; 11785 u8 reserved_at_11[0xf]; 11786 11787 u8 reserved_at_20[0x60]; 11788 }; 11789 11790 enum { 11791 MLX5_MTCTR_REQUEST_NOP = 0x0, 11792 MLX5_MTCTR_REQUEST_PTM_ROOT_CLOCK = 0x1, 11793 MLX5_MTCTR_REQUEST_FREE_RUNNING_COUNTER = 0x2, 11794 MLX5_MTCTR_REQUEST_REAL_TIME_CLOCK = 0x3, 11795 }; 11796 11797 struct mlx5_ifc_mtctr_reg_bits { 11798 u8 first_clock_timestamp_request[0x8]; 11799 u8 second_clock_timestamp_request[0x8]; 11800 u8 reserved_at_10[0x10]; 11801 11802 u8 first_clock_valid[0x1]; 11803 u8 second_clock_valid[0x1]; 11804 u8 reserved_at_22[0x1e]; 11805 11806 u8 first_clock_timestamp[0x40]; 11807 u8 second_clock_timestamp[0x40]; 11808 }; 11809 11810 struct mlx5_ifc_bin_range_layout_bits { 11811 u8 reserved_at_0[0xa]; 11812 u8 high_val[0x6]; 11813 u8 reserved_at_10[0xa]; 11814 u8 low_val[0x6]; 11815 }; 11816 11817 struct mlx5_ifc_pphcr_reg_bits { 11818 u8 active_hist_type[0x4]; 11819 u8 reserved_at_4[0x4]; 11820 u8 local_port[0x8]; 11821 u8 reserved_at_10[0x10]; 11822 11823 u8 reserved_at_20[0x8]; 11824 u8 num_of_bins[0x8]; 11825 u8 reserved_at_30[0x10]; 11826 11827 u8 reserved_at_40[0x40]; 11828 11829 struct mlx5_ifc_bin_range_layout_bits bin_range[16]; 11830 }; 11831 11832 union mlx5_ifc_ports_control_registers_document_bits { 11833 struct mlx5_ifc_bufferx_reg_bits bufferx_reg; 11834 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 11835 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 11836 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 11837 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 11838 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 11839 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 11840 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout; 11841 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout; 11842 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping; 11843 struct mlx5_ifc_pamp_reg_bits pamp_reg; 11844 struct mlx5_ifc_paos_reg_bits paos_reg; 11845 struct mlx5_ifc_pcap_reg_bits pcap_reg; 11846 struct mlx5_ifc_pddr_monitor_opcode_bits pddr_monitor_opcode; 11847 struct mlx5_ifc_pddr_reg_bits pddr_reg; 11848 struct mlx5_ifc_pddr_troubleshooting_page_bits pddr_troubleshooting_page; 11849 struct mlx5_ifc_peir_reg_bits peir_reg; 11850 struct mlx5_ifc_pelc_reg_bits pelc_reg; 11851 struct mlx5_ifc_pfcc_reg_bits pfcc_reg; 11852 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 11853 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 11854 struct mlx5_ifc_pifr_reg_bits pifr_reg; 11855 struct mlx5_ifc_pipg_reg_bits pipg_reg; 11856 struct mlx5_ifc_plbf_reg_bits plbf_reg; 11857 struct mlx5_ifc_plib_reg_bits plib_reg; 11858 struct mlx5_ifc_plpc_reg_bits plpc_reg; 11859 struct mlx5_ifc_pmaos_reg_bits pmaos_reg; 11860 struct mlx5_ifc_pmlp_reg_bits pmlp_reg; 11861 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg; 11862 struct mlx5_ifc_pmpc_reg_bits pmpc_reg; 11863 struct mlx5_ifc_pmpe_reg_bits pmpe_reg; 11864 struct mlx5_ifc_pmpr_reg_bits pmpr_reg; 11865 struct mlx5_ifc_pmtu_reg_bits pmtu_reg; 11866 struct mlx5_ifc_ppad_reg_bits ppad_reg; 11867 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg; 11868 struct mlx5_ifc_mpein_reg_bits mpein_reg; 11869 struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg; 11870 struct mlx5_ifc_pplm_reg_bits pplm_reg; 11871 struct mlx5_ifc_pplr_reg_bits pplr_reg; 11872 struct mlx5_ifc_ppsc_reg_bits ppsc_reg; 11873 struct mlx5_ifc_pqdr_reg_bits pqdr_reg; 11874 struct mlx5_ifc_pspa_reg_bits pspa_reg; 11875 struct mlx5_ifc_ptas_reg_bits ptas_reg; 11876 struct mlx5_ifc_ptys_reg_bits ptys_reg; 11877 struct mlx5_ifc_mlcr_reg_bits mlcr_reg; 11878 struct mlx5_ifc_pude_reg_bits pude_reg; 11879 struct mlx5_ifc_pvlc_reg_bits pvlc_reg; 11880 struct mlx5_ifc_slrg_reg_bits slrg_reg; 11881 struct mlx5_ifc_sltp_reg_bits sltp_reg; 11882 struct mlx5_ifc_mtpps_reg_bits mtpps_reg; 11883 struct mlx5_ifc_mtppse_reg_bits mtppse_reg; 11884 struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg; 11885 struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits; 11886 struct mlx5_ifc_fpga_cap_bits fpga_cap_bits; 11887 struct mlx5_ifc_mcqi_reg_bits mcqi_reg; 11888 struct mlx5_ifc_mcc_reg_bits mcc_reg; 11889 struct mlx5_ifc_mcda_reg_bits mcda_reg; 11890 struct mlx5_ifc_mirc_reg_bits mirc_reg; 11891 struct mlx5_ifc_mfrl_reg_bits mfrl_reg; 11892 struct mlx5_ifc_mtutc_reg_bits mtutc_reg; 11893 struct mlx5_ifc_mrtc_reg_bits mrtc_reg; 11894 struct mlx5_ifc_mtcap_reg_bits mtcap_reg; 11895 struct mlx5_ifc_mtmp_reg_bits mtmp_reg; 11896 struct mlx5_ifc_mtptm_reg_bits mtptm_reg; 11897 struct mlx5_ifc_mtctr_reg_bits mtctr_reg; 11898 struct mlx5_ifc_pphcr_reg_bits pphcr_reg; 11899 u8 reserved_at_0[0x60e0]; 11900 }; 11901 11902 union mlx5_ifc_debug_enhancements_document_bits { 11903 struct mlx5_ifc_health_buffer_bits health_buffer; 11904 u8 reserved_at_0[0x200]; 11905 }; 11906 11907 union mlx5_ifc_uplink_pci_interface_document_bits { 11908 struct mlx5_ifc_initial_seg_bits initial_seg; 11909 u8 reserved_at_0[0x20060]; 11910 }; 11911 11912 struct mlx5_ifc_set_flow_table_root_out_bits { 11913 u8 status[0x8]; 11914 u8 reserved_at_8[0x18]; 11915 11916 u8 syndrome[0x20]; 11917 11918 u8 reserved_at_40[0x40]; 11919 }; 11920 11921 struct mlx5_ifc_set_flow_table_root_in_bits { 11922 u8 opcode[0x10]; 11923 u8 reserved_at_10[0x10]; 11924 11925 u8 reserved_at_20[0x10]; 11926 u8 op_mod[0x10]; 11927 11928 u8 other_vport[0x1]; 11929 u8 other_eswitch[0x1]; 11930 u8 reserved_at_42[0xe]; 11931 u8 vport_number[0x10]; 11932 11933 u8 reserved_at_60[0x10]; 11934 u8 eswitch_owner_vhca_id[0x10]; 11935 11936 u8 table_type[0x8]; 11937 u8 reserved_at_88[0x7]; 11938 u8 table_of_other_vport[0x1]; 11939 u8 table_vport_number[0x10]; 11940 11941 u8 reserved_at_a0[0x8]; 11942 u8 table_id[0x18]; 11943 11944 u8 reserved_at_c0[0x8]; 11945 u8 underlay_qpn[0x18]; 11946 u8 table_eswitch_owner_vhca_id_valid[0x1]; 11947 u8 reserved_at_e1[0xf]; 11948 u8 table_eswitch_owner_vhca_id[0x10]; 11949 u8 reserved_at_100[0x100]; 11950 }; 11951 11952 enum { 11953 MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = (1UL << 0), 11954 MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15), 11955 }; 11956 11957 struct mlx5_ifc_modify_flow_table_out_bits { 11958 u8 status[0x8]; 11959 u8 reserved_at_8[0x18]; 11960 11961 u8 syndrome[0x20]; 11962 11963 u8 reserved_at_40[0x40]; 11964 }; 11965 11966 struct mlx5_ifc_modify_flow_table_in_bits { 11967 u8 opcode[0x10]; 11968 u8 reserved_at_10[0x10]; 11969 11970 u8 reserved_at_20[0x10]; 11971 u8 op_mod[0x10]; 11972 11973 u8 other_vport[0x1]; 11974 u8 other_eswitch[0x1]; 11975 u8 reserved_at_42[0xe]; 11976 u8 vport_number[0x10]; 11977 11978 u8 reserved_at_60[0x10]; 11979 u8 modify_field_select[0x10]; 11980 11981 u8 table_type[0x8]; 11982 u8 reserved_at_88[0x8]; 11983 u8 eswitch_owner_vhca_id[0x10]; 11984 11985 u8 reserved_at_a0[0x8]; 11986 u8 table_id[0x18]; 11987 11988 struct mlx5_ifc_flow_table_context_bits flow_table_context; 11989 }; 11990 11991 struct mlx5_ifc_ets_tcn_config_reg_bits { 11992 u8 g[0x1]; 11993 u8 b[0x1]; 11994 u8 r[0x1]; 11995 u8 reserved_at_3[0x9]; 11996 u8 group[0x4]; 11997 u8 reserved_at_10[0x9]; 11998 u8 bw_allocation[0x7]; 11999 12000 u8 reserved_at_20[0xc]; 12001 u8 max_bw_units[0x4]; 12002 u8 max_bw_value[0x10]; 12003 }; 12004 12005 struct mlx5_ifc_ets_global_config_reg_bits { 12006 u8 reserved_at_0[0x2]; 12007 u8 r[0x1]; 12008 u8 reserved_at_3[0x1d]; 12009 12010 u8 reserved_at_20[0xc]; 12011 u8 max_bw_units[0x4]; 12012 u8 reserved_at_30[0x8]; 12013 u8 max_bw_value[0x8]; 12014 }; 12015 12016 struct mlx5_ifc_qetc_reg_bits { 12017 u8 reserved_at_0[0x8]; 12018 u8 port_number[0x8]; 12019 u8 reserved_at_10[0x30]; 12020 12021 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8]; 12022 struct mlx5_ifc_ets_global_config_reg_bits global_configuration; 12023 }; 12024 12025 struct mlx5_ifc_qpdpm_dscp_reg_bits { 12026 u8 e[0x1]; 12027 u8 reserved_at_01[0x0b]; 12028 u8 prio[0x04]; 12029 }; 12030 12031 struct mlx5_ifc_qpdpm_reg_bits { 12032 u8 reserved_at_0[0x8]; 12033 u8 local_port[0x8]; 12034 u8 reserved_at_10[0x10]; 12035 struct mlx5_ifc_qpdpm_dscp_reg_bits dscp[64]; 12036 }; 12037 12038 struct mlx5_ifc_qpts_reg_bits { 12039 u8 reserved_at_0[0x8]; 12040 u8 local_port[0x8]; 12041 u8 reserved_at_10[0x2d]; 12042 u8 trust_state[0x3]; 12043 }; 12044 12045 struct mlx5_ifc_pptb_reg_bits { 12046 u8 reserved_at_0[0x2]; 12047 u8 mm[0x2]; 12048 u8 reserved_at_4[0x4]; 12049 u8 local_port[0x8]; 12050 u8 reserved_at_10[0x6]; 12051 u8 cm[0x1]; 12052 u8 um[0x1]; 12053 u8 pm[0x8]; 12054 12055 u8 prio_x_buff[0x20]; 12056 12057 u8 pm_msb[0x8]; 12058 u8 reserved_at_48[0x10]; 12059 u8 ctrl_buff[0x4]; 12060 u8 untagged_buff[0x4]; 12061 }; 12062 12063 struct mlx5_ifc_sbcam_reg_bits { 12064 u8 reserved_at_0[0x8]; 12065 u8 feature_group[0x8]; 12066 u8 reserved_at_10[0x8]; 12067 u8 access_reg_group[0x8]; 12068 12069 u8 reserved_at_20[0x20]; 12070 12071 u8 sb_access_reg_cap_mask[4][0x20]; 12072 12073 u8 reserved_at_c0[0x80]; 12074 12075 u8 sb_feature_cap_mask[4][0x20]; 12076 12077 u8 reserved_at_1c0[0x40]; 12078 12079 u8 cap_total_buffer_size[0x20]; 12080 12081 u8 cap_cell_size[0x10]; 12082 u8 cap_max_pg_buffers[0x8]; 12083 u8 cap_num_pool_supported[0x8]; 12084 12085 u8 reserved_at_240[0x8]; 12086 u8 cap_sbsr_stat_size[0x8]; 12087 u8 cap_max_tclass_data[0x8]; 12088 u8 cap_max_cpu_ingress_tclass_sb[0x8]; 12089 }; 12090 12091 struct mlx5_ifc_pbmc_reg_bits { 12092 u8 reserved_at_0[0x8]; 12093 u8 local_port[0x8]; 12094 u8 reserved_at_10[0x10]; 12095 12096 u8 xoff_timer_value[0x10]; 12097 u8 xoff_refresh[0x10]; 12098 12099 u8 reserved_at_40[0x9]; 12100 u8 fullness_threshold[0x7]; 12101 u8 port_buffer_size[0x10]; 12102 12103 struct mlx5_ifc_bufferx_reg_bits buffer[10]; 12104 struct mlx5_ifc_bufferx_reg_bits shared_headroom_pool; 12105 12106 u8 reserved_at_320[0x40]; 12107 }; 12108 12109 struct mlx5_ifc_sbpr_reg_bits { 12110 u8 desc[0x1]; 12111 u8 snap[0x1]; 12112 u8 reserved_at_2[0x4]; 12113 u8 dir[0x2]; 12114 u8 reserved_at_8[0x14]; 12115 u8 pool[0x4]; 12116 12117 u8 infi_size[0x1]; 12118 u8 reserved_at_21[0x7]; 12119 u8 size[0x18]; 12120 12121 u8 reserved_at_40[0x1c]; 12122 u8 mode[0x4]; 12123 12124 u8 reserved_at_60[0x8]; 12125 u8 buff_occupancy[0x18]; 12126 12127 u8 clr[0x1]; 12128 u8 reserved_at_81[0x7]; 12129 u8 max_buff_occupancy[0x18]; 12130 12131 u8 reserved_at_a0[0x8]; 12132 u8 ext_buff_occupancy[0x18]; 12133 }; 12134 12135 struct mlx5_ifc_sbcm_reg_bits { 12136 u8 desc[0x1]; 12137 u8 snap[0x1]; 12138 u8 reserved_at_2[0x6]; 12139 u8 local_port[0x8]; 12140 u8 pnat[0x2]; 12141 u8 pg_buff[0x6]; 12142 u8 reserved_at_18[0x6]; 12143 u8 dir[0x2]; 12144 12145 u8 reserved_at_20[0x1f]; 12146 u8 exc[0x1]; 12147 12148 u8 reserved_at_40[0x40]; 12149 12150 u8 reserved_at_80[0x8]; 12151 u8 buff_occupancy[0x18]; 12152 12153 u8 clr[0x1]; 12154 u8 reserved_at_a1[0x7]; 12155 u8 max_buff_occupancy[0x18]; 12156 12157 u8 reserved_at_c0[0x8]; 12158 u8 min_buff[0x18]; 12159 12160 u8 infi_max[0x1]; 12161 u8 reserved_at_e1[0x7]; 12162 u8 max_buff[0x18]; 12163 12164 u8 reserved_at_100[0x20]; 12165 12166 u8 reserved_at_120[0x1c]; 12167 u8 pool[0x4]; 12168 }; 12169 12170 struct mlx5_ifc_qtct_reg_bits { 12171 u8 reserved_at_0[0x8]; 12172 u8 port_number[0x8]; 12173 u8 reserved_at_10[0xd]; 12174 u8 prio[0x3]; 12175 12176 u8 reserved_at_20[0x1d]; 12177 u8 tclass[0x3]; 12178 }; 12179 12180 struct mlx5_ifc_mcia_reg_bits { 12181 u8 l[0x1]; 12182 u8 reserved_at_1[0x7]; 12183 u8 module[0x8]; 12184 u8 reserved_at_10[0x8]; 12185 u8 status[0x8]; 12186 12187 u8 i2c_device_address[0x8]; 12188 u8 page_number[0x8]; 12189 u8 device_address[0x10]; 12190 12191 u8 reserved_at_40[0x10]; 12192 u8 size[0x10]; 12193 12194 u8 reserved_at_60[0x20]; 12195 12196 u8 dword_0[0x20]; 12197 u8 dword_1[0x20]; 12198 u8 dword_2[0x20]; 12199 u8 dword_3[0x20]; 12200 u8 dword_4[0x20]; 12201 u8 dword_5[0x20]; 12202 u8 dword_6[0x20]; 12203 u8 dword_7[0x20]; 12204 u8 dword_8[0x20]; 12205 u8 dword_9[0x20]; 12206 u8 dword_10[0x20]; 12207 u8 dword_11[0x20]; 12208 }; 12209 12210 struct mlx5_ifc_dcbx_param_bits { 12211 u8 dcbx_cee_cap[0x1]; 12212 u8 dcbx_ieee_cap[0x1]; 12213 u8 dcbx_standby_cap[0x1]; 12214 u8 reserved_at_3[0x5]; 12215 u8 port_number[0x8]; 12216 u8 reserved_at_10[0xa]; 12217 u8 max_application_table_size[6]; 12218 u8 reserved_at_20[0x15]; 12219 u8 version_oper[0x3]; 12220 u8 reserved_at_38[5]; 12221 u8 version_admin[0x3]; 12222 u8 willing_admin[0x1]; 12223 u8 reserved_at_41[0x3]; 12224 u8 pfc_cap_oper[0x4]; 12225 u8 reserved_at_48[0x4]; 12226 u8 pfc_cap_admin[0x4]; 12227 u8 reserved_at_50[0x4]; 12228 u8 num_of_tc_oper[0x4]; 12229 u8 reserved_at_58[0x4]; 12230 u8 num_of_tc_admin[0x4]; 12231 u8 remote_willing[0x1]; 12232 u8 reserved_at_61[3]; 12233 u8 remote_pfc_cap[4]; 12234 u8 reserved_at_68[0x14]; 12235 u8 remote_num_of_tc[0x4]; 12236 u8 reserved_at_80[0x18]; 12237 u8 error[0x8]; 12238 u8 reserved_at_a0[0x160]; 12239 }; 12240 12241 enum { 12242 MLX5_LAG_PORT_SELECT_MODE_QUEUE_AFFINITY = 0, 12243 MLX5_LAG_PORT_SELECT_MODE_PORT_SELECT_FT = 1, 12244 MLX5_LAG_PORT_SELECT_MODE_PORT_SELECT_MPESW = 2, 12245 }; 12246 12247 struct mlx5_ifc_lagc_bits { 12248 u8 fdb_selection_mode[0x1]; 12249 u8 reserved_at_1[0x14]; 12250 u8 port_select_mode[0x3]; 12251 u8 reserved_at_18[0x5]; 12252 u8 lag_state[0x3]; 12253 12254 u8 reserved_at_20[0xc]; 12255 u8 active_port[0x4]; 12256 u8 reserved_at_30[0x4]; 12257 u8 tx_remap_affinity_2[0x4]; 12258 u8 reserved_at_38[0x4]; 12259 u8 tx_remap_affinity_1[0x4]; 12260 }; 12261 12262 struct mlx5_ifc_create_lag_out_bits { 12263 u8 status[0x8]; 12264 u8 reserved_at_8[0x18]; 12265 12266 u8 syndrome[0x20]; 12267 12268 u8 reserved_at_40[0x40]; 12269 }; 12270 12271 struct mlx5_ifc_create_lag_in_bits { 12272 u8 opcode[0x10]; 12273 u8 reserved_at_10[0x10]; 12274 12275 u8 reserved_at_20[0x10]; 12276 u8 op_mod[0x10]; 12277 12278 struct mlx5_ifc_lagc_bits ctx; 12279 }; 12280 12281 struct mlx5_ifc_modify_lag_out_bits { 12282 u8 status[0x8]; 12283 u8 reserved_at_8[0x18]; 12284 12285 u8 syndrome[0x20]; 12286 12287 u8 reserved_at_40[0x40]; 12288 }; 12289 12290 struct mlx5_ifc_modify_lag_in_bits { 12291 u8 opcode[0x10]; 12292 u8 reserved_at_10[0x10]; 12293 12294 u8 reserved_at_20[0x10]; 12295 u8 op_mod[0x10]; 12296 12297 u8 reserved_at_40[0x20]; 12298 u8 field_select[0x20]; 12299 12300 struct mlx5_ifc_lagc_bits ctx; 12301 }; 12302 12303 struct mlx5_ifc_query_lag_out_bits { 12304 u8 status[0x8]; 12305 u8 reserved_at_8[0x18]; 12306 12307 u8 syndrome[0x20]; 12308 12309 struct mlx5_ifc_lagc_bits ctx; 12310 }; 12311 12312 struct mlx5_ifc_query_lag_in_bits { 12313 u8 opcode[0x10]; 12314 u8 reserved_at_10[0x10]; 12315 12316 u8 reserved_at_20[0x10]; 12317 u8 op_mod[0x10]; 12318 12319 u8 reserved_at_40[0x40]; 12320 }; 12321 12322 struct mlx5_ifc_destroy_lag_out_bits { 12323 u8 status[0x8]; 12324 u8 reserved_at_8[0x18]; 12325 12326 u8 syndrome[0x20]; 12327 12328 u8 reserved_at_40[0x40]; 12329 }; 12330 12331 struct mlx5_ifc_destroy_lag_in_bits { 12332 u8 opcode[0x10]; 12333 u8 reserved_at_10[0x10]; 12334 12335 u8 reserved_at_20[0x10]; 12336 u8 op_mod[0x10]; 12337 12338 u8 reserved_at_40[0x40]; 12339 }; 12340 12341 struct mlx5_ifc_create_vport_lag_out_bits { 12342 u8 status[0x8]; 12343 u8 reserved_at_8[0x18]; 12344 12345 u8 syndrome[0x20]; 12346 12347 u8 reserved_at_40[0x40]; 12348 }; 12349 12350 struct mlx5_ifc_create_vport_lag_in_bits { 12351 u8 opcode[0x10]; 12352 u8 reserved_at_10[0x10]; 12353 12354 u8 reserved_at_20[0x10]; 12355 u8 op_mod[0x10]; 12356 12357 u8 reserved_at_40[0x40]; 12358 }; 12359 12360 struct mlx5_ifc_destroy_vport_lag_out_bits { 12361 u8 status[0x8]; 12362 u8 reserved_at_8[0x18]; 12363 12364 u8 syndrome[0x20]; 12365 12366 u8 reserved_at_40[0x40]; 12367 }; 12368 12369 struct mlx5_ifc_destroy_vport_lag_in_bits { 12370 u8 opcode[0x10]; 12371 u8 reserved_at_10[0x10]; 12372 12373 u8 reserved_at_20[0x10]; 12374 u8 op_mod[0x10]; 12375 12376 u8 reserved_at_40[0x40]; 12377 }; 12378 12379 enum { 12380 MLX5_MODIFY_MEMIC_OP_MOD_ALLOC, 12381 MLX5_MODIFY_MEMIC_OP_MOD_DEALLOC, 12382 }; 12383 12384 struct mlx5_ifc_modify_memic_in_bits { 12385 u8 opcode[0x10]; 12386 u8 uid[0x10]; 12387 12388 u8 reserved_at_20[0x10]; 12389 u8 op_mod[0x10]; 12390 12391 u8 reserved_at_40[0x20]; 12392 12393 u8 reserved_at_60[0x18]; 12394 u8 memic_operation_type[0x8]; 12395 12396 u8 memic_start_addr[0x40]; 12397 12398 u8 reserved_at_c0[0x140]; 12399 }; 12400 12401 struct mlx5_ifc_modify_memic_out_bits { 12402 u8 status[0x8]; 12403 u8 reserved_at_8[0x18]; 12404 12405 u8 syndrome[0x20]; 12406 12407 u8 reserved_at_40[0x40]; 12408 12409 u8 memic_operation_addr[0x40]; 12410 12411 u8 reserved_at_c0[0x140]; 12412 }; 12413 12414 struct mlx5_ifc_alloc_memic_in_bits { 12415 u8 opcode[0x10]; 12416 u8 reserved_at_10[0x10]; 12417 12418 u8 reserved_at_20[0x10]; 12419 u8 op_mod[0x10]; 12420 12421 u8 reserved_at_30[0x20]; 12422 12423 u8 reserved_at_40[0x18]; 12424 u8 log_memic_addr_alignment[0x8]; 12425 12426 u8 range_start_addr[0x40]; 12427 12428 u8 range_size[0x20]; 12429 12430 u8 memic_size[0x20]; 12431 }; 12432 12433 struct mlx5_ifc_alloc_memic_out_bits { 12434 u8 status[0x8]; 12435 u8 reserved_at_8[0x18]; 12436 12437 u8 syndrome[0x20]; 12438 12439 u8 memic_start_addr[0x40]; 12440 }; 12441 12442 struct mlx5_ifc_dealloc_memic_in_bits { 12443 u8 opcode[0x10]; 12444 u8 reserved_at_10[0x10]; 12445 12446 u8 reserved_at_20[0x10]; 12447 u8 op_mod[0x10]; 12448 12449 u8 reserved_at_40[0x40]; 12450 12451 u8 memic_start_addr[0x40]; 12452 12453 u8 memic_size[0x20]; 12454 12455 u8 reserved_at_e0[0x20]; 12456 }; 12457 12458 struct mlx5_ifc_dealloc_memic_out_bits { 12459 u8 status[0x8]; 12460 u8 reserved_at_8[0x18]; 12461 12462 u8 syndrome[0x20]; 12463 12464 u8 reserved_at_40[0x40]; 12465 }; 12466 12467 struct mlx5_ifc_umem_bits { 12468 u8 reserved_at_0[0x80]; 12469 12470 u8 ats[0x1]; 12471 u8 reserved_at_81[0x1a]; 12472 u8 log_page_size[0x5]; 12473 12474 u8 page_offset[0x20]; 12475 12476 u8 num_of_mtt[0x40]; 12477 12478 struct mlx5_ifc_mtt_bits mtt[]; 12479 }; 12480 12481 struct mlx5_ifc_uctx_bits { 12482 u8 cap[0x20]; 12483 12484 u8 reserved_at_20[0x160]; 12485 }; 12486 12487 struct mlx5_ifc_sw_icm_bits { 12488 u8 modify_field_select[0x40]; 12489 12490 u8 reserved_at_40[0x18]; 12491 u8 log_sw_icm_size[0x8]; 12492 12493 u8 reserved_at_60[0x20]; 12494 12495 u8 sw_icm_start_addr[0x40]; 12496 12497 u8 reserved_at_c0[0x140]; 12498 }; 12499 12500 struct mlx5_ifc_geneve_tlv_option_bits { 12501 u8 modify_field_select[0x40]; 12502 12503 u8 reserved_at_40[0x18]; 12504 u8 geneve_option_fte_index[0x8]; 12505 12506 u8 option_class[0x10]; 12507 u8 option_type[0x8]; 12508 u8 reserved_at_78[0x3]; 12509 u8 option_data_length[0x5]; 12510 12511 u8 reserved_at_80[0x180]; 12512 }; 12513 12514 struct mlx5_ifc_create_umem_in_bits { 12515 u8 opcode[0x10]; 12516 u8 uid[0x10]; 12517 12518 u8 reserved_at_20[0x10]; 12519 u8 op_mod[0x10]; 12520 12521 u8 reserved_at_40[0x40]; 12522 12523 struct mlx5_ifc_umem_bits umem; 12524 }; 12525 12526 struct mlx5_ifc_create_umem_out_bits { 12527 u8 status[0x8]; 12528 u8 reserved_at_8[0x18]; 12529 12530 u8 syndrome[0x20]; 12531 12532 u8 reserved_at_40[0x8]; 12533 u8 umem_id[0x18]; 12534 12535 u8 reserved_at_60[0x20]; 12536 }; 12537 12538 struct mlx5_ifc_destroy_umem_in_bits { 12539 u8 opcode[0x10]; 12540 u8 uid[0x10]; 12541 12542 u8 reserved_at_20[0x10]; 12543 u8 op_mod[0x10]; 12544 12545 u8 reserved_at_40[0x8]; 12546 u8 umem_id[0x18]; 12547 12548 u8 reserved_at_60[0x20]; 12549 }; 12550 12551 struct mlx5_ifc_destroy_umem_out_bits { 12552 u8 status[0x8]; 12553 u8 reserved_at_8[0x18]; 12554 12555 u8 syndrome[0x20]; 12556 12557 u8 reserved_at_40[0x40]; 12558 }; 12559 12560 struct mlx5_ifc_create_uctx_in_bits { 12561 u8 opcode[0x10]; 12562 u8 reserved_at_10[0x10]; 12563 12564 u8 reserved_at_20[0x10]; 12565 u8 op_mod[0x10]; 12566 12567 u8 reserved_at_40[0x40]; 12568 12569 struct mlx5_ifc_uctx_bits uctx; 12570 }; 12571 12572 struct mlx5_ifc_create_uctx_out_bits { 12573 u8 status[0x8]; 12574 u8 reserved_at_8[0x18]; 12575 12576 u8 syndrome[0x20]; 12577 12578 u8 reserved_at_40[0x10]; 12579 u8 uid[0x10]; 12580 12581 u8 reserved_at_60[0x20]; 12582 }; 12583 12584 struct mlx5_ifc_destroy_uctx_in_bits { 12585 u8 opcode[0x10]; 12586 u8 reserved_at_10[0x10]; 12587 12588 u8 reserved_at_20[0x10]; 12589 u8 op_mod[0x10]; 12590 12591 u8 reserved_at_40[0x10]; 12592 u8 uid[0x10]; 12593 12594 u8 reserved_at_60[0x20]; 12595 }; 12596 12597 struct mlx5_ifc_destroy_uctx_out_bits { 12598 u8 status[0x8]; 12599 u8 reserved_at_8[0x18]; 12600 12601 u8 syndrome[0x20]; 12602 12603 u8 reserved_at_40[0x40]; 12604 }; 12605 12606 struct mlx5_ifc_create_sw_icm_in_bits { 12607 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 12608 struct mlx5_ifc_sw_icm_bits sw_icm; 12609 }; 12610 12611 struct mlx5_ifc_create_geneve_tlv_option_in_bits { 12612 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 12613 struct mlx5_ifc_geneve_tlv_option_bits geneve_tlv_opt; 12614 }; 12615 12616 struct mlx5_ifc_mtrc_string_db_param_bits { 12617 u8 string_db_base_address[0x20]; 12618 12619 u8 reserved_at_20[0x8]; 12620 u8 string_db_size[0x18]; 12621 }; 12622 12623 struct mlx5_ifc_mtrc_cap_bits { 12624 u8 trace_owner[0x1]; 12625 u8 trace_to_memory[0x1]; 12626 u8 reserved_at_2[0x4]; 12627 u8 trc_ver[0x2]; 12628 u8 reserved_at_8[0x14]; 12629 u8 num_string_db[0x4]; 12630 12631 u8 first_string_trace[0x8]; 12632 u8 num_string_trace[0x8]; 12633 u8 reserved_at_30[0x28]; 12634 12635 u8 log_max_trace_buffer_size[0x8]; 12636 12637 u8 reserved_at_60[0x20]; 12638 12639 struct mlx5_ifc_mtrc_string_db_param_bits string_db_param[8]; 12640 12641 u8 reserved_at_280[0x180]; 12642 }; 12643 12644 struct mlx5_ifc_mtrc_conf_bits { 12645 u8 reserved_at_0[0x1c]; 12646 u8 trace_mode[0x4]; 12647 u8 reserved_at_20[0x18]; 12648 u8 log_trace_buffer_size[0x8]; 12649 u8 trace_mkey[0x20]; 12650 u8 reserved_at_60[0x3a0]; 12651 }; 12652 12653 struct mlx5_ifc_mtrc_stdb_bits { 12654 u8 string_db_index[0x4]; 12655 u8 reserved_at_4[0x4]; 12656 u8 read_size[0x18]; 12657 u8 start_offset[0x20]; 12658 u8 string_db_data[]; 12659 }; 12660 12661 struct mlx5_ifc_mtrc_ctrl_bits { 12662 u8 trace_status[0x2]; 12663 u8 reserved_at_2[0x2]; 12664 u8 arm_event[0x1]; 12665 u8 reserved_at_5[0xb]; 12666 u8 modify_field_select[0x10]; 12667 u8 reserved_at_20[0x2b]; 12668 u8 current_timestamp52_32[0x15]; 12669 u8 current_timestamp31_0[0x20]; 12670 u8 reserved_at_80[0x180]; 12671 }; 12672 12673 struct mlx5_ifc_host_params_context_bits { 12674 u8 host_number[0x8]; 12675 u8 reserved_at_8[0x5]; 12676 u8 host_pf_not_exist[0x1]; 12677 u8 reserved_at_14[0x1]; 12678 u8 host_pf_disabled[0x1]; 12679 u8 host_num_of_vfs[0x10]; 12680 12681 u8 host_total_vfs[0x10]; 12682 u8 host_pci_bus[0x10]; 12683 12684 u8 reserved_at_40[0x10]; 12685 u8 host_pci_device[0x10]; 12686 12687 u8 reserved_at_60[0x10]; 12688 u8 host_pci_function[0x10]; 12689 12690 u8 reserved_at_80[0x180]; 12691 }; 12692 12693 struct mlx5_ifc_query_esw_functions_in_bits { 12694 u8 opcode[0x10]; 12695 u8 reserved_at_10[0x10]; 12696 12697 u8 reserved_at_20[0x10]; 12698 u8 op_mod[0x10]; 12699 12700 u8 reserved_at_40[0x40]; 12701 }; 12702 12703 struct mlx5_ifc_query_esw_functions_out_bits { 12704 u8 status[0x8]; 12705 u8 reserved_at_8[0x18]; 12706 12707 u8 syndrome[0x20]; 12708 12709 u8 reserved_at_40[0x40]; 12710 12711 struct mlx5_ifc_host_params_context_bits host_params_context; 12712 12713 u8 reserved_at_280[0x180]; 12714 u8 host_sf_enable[][0x40]; 12715 }; 12716 12717 struct mlx5_ifc_sf_partition_bits { 12718 u8 reserved_at_0[0x10]; 12719 u8 log_num_sf[0x8]; 12720 u8 log_sf_bar_size[0x8]; 12721 }; 12722 12723 struct mlx5_ifc_query_sf_partitions_out_bits { 12724 u8 status[0x8]; 12725 u8 reserved_at_8[0x18]; 12726 12727 u8 syndrome[0x20]; 12728 12729 u8 reserved_at_40[0x18]; 12730 u8 num_sf_partitions[0x8]; 12731 12732 u8 reserved_at_60[0x20]; 12733 12734 struct mlx5_ifc_sf_partition_bits sf_partition[]; 12735 }; 12736 12737 struct mlx5_ifc_query_sf_partitions_in_bits { 12738 u8 opcode[0x10]; 12739 u8 reserved_at_10[0x10]; 12740 12741 u8 reserved_at_20[0x10]; 12742 u8 op_mod[0x10]; 12743 12744 u8 reserved_at_40[0x40]; 12745 }; 12746 12747 struct mlx5_ifc_dealloc_sf_out_bits { 12748 u8 status[0x8]; 12749 u8 reserved_at_8[0x18]; 12750 12751 u8 syndrome[0x20]; 12752 12753 u8 reserved_at_40[0x40]; 12754 }; 12755 12756 struct mlx5_ifc_dealloc_sf_in_bits { 12757 u8 opcode[0x10]; 12758 u8 reserved_at_10[0x10]; 12759 12760 u8 reserved_at_20[0x10]; 12761 u8 op_mod[0x10]; 12762 12763 u8 reserved_at_40[0x10]; 12764 u8 function_id[0x10]; 12765 12766 u8 reserved_at_60[0x20]; 12767 }; 12768 12769 struct mlx5_ifc_alloc_sf_out_bits { 12770 u8 status[0x8]; 12771 u8 reserved_at_8[0x18]; 12772 12773 u8 syndrome[0x20]; 12774 12775 u8 reserved_at_40[0x40]; 12776 }; 12777 12778 struct mlx5_ifc_alloc_sf_in_bits { 12779 u8 opcode[0x10]; 12780 u8 reserved_at_10[0x10]; 12781 12782 u8 reserved_at_20[0x10]; 12783 u8 op_mod[0x10]; 12784 12785 u8 reserved_at_40[0x10]; 12786 u8 function_id[0x10]; 12787 12788 u8 reserved_at_60[0x20]; 12789 }; 12790 12791 struct mlx5_ifc_affiliated_event_header_bits { 12792 u8 reserved_at_0[0x10]; 12793 u8 obj_type[0x10]; 12794 12795 u8 obj_id[0x20]; 12796 }; 12797 12798 enum { 12799 MLX5_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = 0xc, 12800 MLX5_GENERAL_OBJECT_TYPES_IPSEC = 0x13, 12801 MLX5_GENERAL_OBJECT_TYPES_SAMPLER = 0x20, 12802 MLX5_GENERAL_OBJECT_TYPES_FLOW_METER_ASO = 0x24, 12803 MLX5_GENERAL_OBJECT_TYPES_MACSEC = 0x27, 12804 MLX5_GENERAL_OBJECT_TYPES_INT_KEK = 0x47, 12805 MLX5_GENERAL_OBJECT_TYPES_RDMA_CTRL = 0x53, 12806 MLX5_GENERAL_OBJECT_TYPES_PCIE_CONG_EVENT = 0x58, 12807 MLX5_GENERAL_OBJECT_TYPES_FLOW_TABLE_ALIAS = 0xff15, 12808 }; 12809 12810 enum { 12811 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = 12812 BIT_ULL(MLX5_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY), 12813 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_IPSEC = 12814 BIT_ULL(MLX5_GENERAL_OBJECT_TYPES_IPSEC), 12815 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_SAMPLER = 12816 BIT_ULL(MLX5_GENERAL_OBJECT_TYPES_SAMPLER), 12817 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_FLOW_METER_ASO = 12818 BIT_ULL(MLX5_GENERAL_OBJECT_TYPES_FLOW_METER_ASO), 12819 }; 12820 12821 enum { 12822 MLX5_HCA_CAP_2_GENERAL_OBJECT_TYPES_RDMA_CTRL = 12823 BIT_ULL(MLX5_GENERAL_OBJECT_TYPES_RDMA_CTRL - 0x40), 12824 MLX5_HCA_CAP_2_GENERAL_OBJECT_TYPES_PCIE_CONG_EVENT = 12825 BIT_ULL(MLX5_GENERAL_OBJECT_TYPES_PCIE_CONG_EVENT - 0x40), 12826 }; 12827 12828 enum { 12829 MLX5_IPSEC_OBJECT_ICV_LEN_16B, 12830 }; 12831 12832 enum { 12833 MLX5_IPSEC_ASO_REG_C_0_1 = 0x0, 12834 MLX5_IPSEC_ASO_REG_C_2_3 = 0x1, 12835 MLX5_IPSEC_ASO_REG_C_4_5 = 0x2, 12836 MLX5_IPSEC_ASO_REG_C_6_7 = 0x3, 12837 }; 12838 12839 enum { 12840 MLX5_IPSEC_ASO_MODE = 0x0, 12841 MLX5_IPSEC_ASO_REPLAY_PROTECTION = 0x1, 12842 MLX5_IPSEC_ASO_INC_SN = 0x2, 12843 }; 12844 12845 enum { 12846 MLX5_IPSEC_ASO_REPLAY_WIN_32BIT = 0x0, 12847 MLX5_IPSEC_ASO_REPLAY_WIN_64BIT = 0x1, 12848 MLX5_IPSEC_ASO_REPLAY_WIN_128BIT = 0x2, 12849 MLX5_IPSEC_ASO_REPLAY_WIN_256BIT = 0x3, 12850 }; 12851 12852 struct mlx5_ifc_ipsec_aso_bits { 12853 u8 valid[0x1]; 12854 u8 reserved_at_201[0x1]; 12855 u8 mode[0x2]; 12856 u8 window_sz[0x2]; 12857 u8 soft_lft_arm[0x1]; 12858 u8 hard_lft_arm[0x1]; 12859 u8 remove_flow_enable[0x1]; 12860 u8 esn_event_arm[0x1]; 12861 u8 reserved_at_20a[0x16]; 12862 12863 u8 remove_flow_pkt_cnt[0x20]; 12864 12865 u8 remove_flow_soft_lft[0x20]; 12866 12867 u8 reserved_at_260[0x80]; 12868 12869 u8 mode_parameter[0x20]; 12870 12871 u8 replay_protection_window[0x100]; 12872 }; 12873 12874 struct mlx5_ifc_ipsec_obj_bits { 12875 u8 modify_field_select[0x40]; 12876 u8 full_offload[0x1]; 12877 u8 reserved_at_41[0x1]; 12878 u8 esn_en[0x1]; 12879 u8 esn_overlap[0x1]; 12880 u8 reserved_at_44[0x2]; 12881 u8 icv_length[0x2]; 12882 u8 reserved_at_48[0x4]; 12883 u8 aso_return_reg[0x4]; 12884 u8 reserved_at_50[0x10]; 12885 12886 u8 esn_msb[0x20]; 12887 12888 u8 reserved_at_80[0x8]; 12889 u8 dekn[0x18]; 12890 12891 u8 salt[0x20]; 12892 12893 u8 implicit_iv[0x40]; 12894 12895 u8 reserved_at_100[0x8]; 12896 u8 ipsec_aso_access_pd[0x18]; 12897 u8 reserved_at_120[0xe0]; 12898 12899 struct mlx5_ifc_ipsec_aso_bits ipsec_aso; 12900 }; 12901 12902 struct mlx5_ifc_create_ipsec_obj_in_bits { 12903 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12904 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 12905 }; 12906 12907 enum { 12908 MLX5_MODIFY_IPSEC_BITMASK_ESN_OVERLAP = BIT(0), 12909 MLX5_MODIFY_IPSEC_BITMASK_ESN_MSB = BIT(1), 12910 }; 12911 12912 struct mlx5_ifc_query_ipsec_obj_out_bits { 12913 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 12914 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 12915 }; 12916 12917 struct mlx5_ifc_modify_ipsec_obj_in_bits { 12918 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12919 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 12920 }; 12921 12922 enum { 12923 MLX5_MACSEC_ASO_REPLAY_PROTECTION = 0x1, 12924 }; 12925 12926 enum { 12927 MLX5_MACSEC_ASO_REPLAY_WIN_32BIT = 0x0, 12928 MLX5_MACSEC_ASO_REPLAY_WIN_64BIT = 0x1, 12929 MLX5_MACSEC_ASO_REPLAY_WIN_128BIT = 0x2, 12930 MLX5_MACSEC_ASO_REPLAY_WIN_256BIT = 0x3, 12931 }; 12932 12933 #define MLX5_MACSEC_ASO_INC_SN 0x2 12934 #define MLX5_MACSEC_ASO_REG_C_4_5 0x2 12935 12936 struct mlx5_ifc_macsec_aso_bits { 12937 u8 valid[0x1]; 12938 u8 reserved_at_1[0x1]; 12939 u8 mode[0x2]; 12940 u8 window_size[0x2]; 12941 u8 soft_lifetime_arm[0x1]; 12942 u8 hard_lifetime_arm[0x1]; 12943 u8 remove_flow_enable[0x1]; 12944 u8 epn_event_arm[0x1]; 12945 u8 reserved_at_a[0x16]; 12946 12947 u8 remove_flow_packet_count[0x20]; 12948 12949 u8 remove_flow_soft_lifetime[0x20]; 12950 12951 u8 reserved_at_60[0x80]; 12952 12953 u8 mode_parameter[0x20]; 12954 12955 u8 replay_protection_window[8][0x20]; 12956 }; 12957 12958 struct mlx5_ifc_macsec_offload_obj_bits { 12959 u8 modify_field_select[0x40]; 12960 12961 u8 confidentiality_en[0x1]; 12962 u8 reserved_at_41[0x1]; 12963 u8 epn_en[0x1]; 12964 u8 epn_overlap[0x1]; 12965 u8 reserved_at_44[0x2]; 12966 u8 confidentiality_offset[0x2]; 12967 u8 reserved_at_48[0x4]; 12968 u8 aso_return_reg[0x4]; 12969 u8 reserved_at_50[0x10]; 12970 12971 u8 epn_msb[0x20]; 12972 12973 u8 reserved_at_80[0x8]; 12974 u8 dekn[0x18]; 12975 12976 u8 reserved_at_a0[0x20]; 12977 12978 u8 sci[0x40]; 12979 12980 u8 reserved_at_100[0x8]; 12981 u8 macsec_aso_access_pd[0x18]; 12982 12983 u8 reserved_at_120[0x60]; 12984 12985 u8 salt[3][0x20]; 12986 12987 u8 reserved_at_1e0[0x20]; 12988 12989 struct mlx5_ifc_macsec_aso_bits macsec_aso; 12990 }; 12991 12992 struct mlx5_ifc_create_macsec_obj_in_bits { 12993 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12994 struct mlx5_ifc_macsec_offload_obj_bits macsec_object; 12995 }; 12996 12997 struct mlx5_ifc_modify_macsec_obj_in_bits { 12998 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12999 struct mlx5_ifc_macsec_offload_obj_bits macsec_object; 13000 }; 13001 13002 enum { 13003 MLX5_MODIFY_MACSEC_BITMASK_EPN_OVERLAP = BIT(0), 13004 MLX5_MODIFY_MACSEC_BITMASK_EPN_MSB = BIT(1), 13005 }; 13006 13007 struct mlx5_ifc_query_macsec_obj_out_bits { 13008 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 13009 struct mlx5_ifc_macsec_offload_obj_bits macsec_object; 13010 }; 13011 13012 struct mlx5_ifc_wrapped_dek_bits { 13013 u8 gcm_iv[0x60]; 13014 13015 u8 reserved_at_60[0x20]; 13016 13017 u8 const0[0x1]; 13018 u8 key_size[0x1]; 13019 u8 reserved_at_82[0x2]; 13020 u8 key2_invalid[0x1]; 13021 u8 reserved_at_85[0x3]; 13022 u8 pd[0x18]; 13023 13024 u8 key_purpose[0x5]; 13025 u8 reserved_at_a5[0x13]; 13026 u8 kek_id[0x8]; 13027 13028 u8 reserved_at_c0[0x40]; 13029 13030 u8 key1[0x8][0x20]; 13031 13032 u8 key2[0x8][0x20]; 13033 13034 u8 reserved_at_300[0x40]; 13035 13036 u8 const1[0x1]; 13037 u8 reserved_at_341[0x1f]; 13038 13039 u8 reserved_at_360[0x20]; 13040 13041 u8 auth_tag[0x80]; 13042 }; 13043 13044 struct mlx5_ifc_encryption_key_obj_bits { 13045 u8 modify_field_select[0x40]; 13046 13047 u8 state[0x8]; 13048 u8 sw_wrapped[0x1]; 13049 u8 reserved_at_49[0xb]; 13050 u8 key_size[0x4]; 13051 u8 reserved_at_58[0x4]; 13052 u8 key_purpose[0x4]; 13053 13054 u8 reserved_at_60[0x8]; 13055 u8 pd[0x18]; 13056 13057 u8 reserved_at_80[0x100]; 13058 13059 u8 opaque[0x40]; 13060 13061 u8 reserved_at_1c0[0x40]; 13062 13063 u8 key[8][0x80]; 13064 13065 u8 sw_wrapped_dek[8][0x80]; 13066 13067 u8 reserved_at_a00[0x600]; 13068 }; 13069 13070 struct mlx5_ifc_create_encryption_key_in_bits { 13071 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 13072 struct mlx5_ifc_encryption_key_obj_bits encryption_key_object; 13073 }; 13074 13075 struct mlx5_ifc_modify_encryption_key_in_bits { 13076 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 13077 struct mlx5_ifc_encryption_key_obj_bits encryption_key_object; 13078 }; 13079 13080 enum { 13081 MLX5_FLOW_METER_MODE_BYTES_IP_LENGTH = 0x0, 13082 MLX5_FLOW_METER_MODE_BYTES_CALC_WITH_L2 = 0x1, 13083 MLX5_FLOW_METER_MODE_BYTES_CALC_WITH_L2_IPG = 0x2, 13084 MLX5_FLOW_METER_MODE_NUM_PACKETS = 0x3, 13085 }; 13086 13087 struct mlx5_ifc_flow_meter_parameters_bits { 13088 u8 valid[0x1]; 13089 u8 bucket_overflow[0x1]; 13090 u8 start_color[0x2]; 13091 u8 both_buckets_on_green[0x1]; 13092 u8 reserved_at_5[0x1]; 13093 u8 meter_mode[0x2]; 13094 u8 reserved_at_8[0x18]; 13095 13096 u8 reserved_at_20[0x20]; 13097 13098 u8 reserved_at_40[0x3]; 13099 u8 cbs_exponent[0x5]; 13100 u8 cbs_mantissa[0x8]; 13101 u8 reserved_at_50[0x3]; 13102 u8 cir_exponent[0x5]; 13103 u8 cir_mantissa[0x8]; 13104 13105 u8 reserved_at_60[0x20]; 13106 13107 u8 reserved_at_80[0x3]; 13108 u8 ebs_exponent[0x5]; 13109 u8 ebs_mantissa[0x8]; 13110 u8 reserved_at_90[0x3]; 13111 u8 eir_exponent[0x5]; 13112 u8 eir_mantissa[0x8]; 13113 13114 u8 reserved_at_a0[0x60]; 13115 }; 13116 13117 struct mlx5_ifc_flow_meter_aso_obj_bits { 13118 u8 modify_field_select[0x40]; 13119 13120 u8 reserved_at_40[0x40]; 13121 13122 u8 reserved_at_80[0x8]; 13123 u8 meter_aso_access_pd[0x18]; 13124 13125 u8 reserved_at_a0[0x160]; 13126 13127 struct mlx5_ifc_flow_meter_parameters_bits flow_meter_parameters[2]; 13128 }; 13129 13130 struct mlx5_ifc_create_flow_meter_aso_obj_in_bits { 13131 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 13132 struct mlx5_ifc_flow_meter_aso_obj_bits flow_meter_aso_obj; 13133 }; 13134 13135 struct mlx5_ifc_int_kek_obj_bits { 13136 u8 modify_field_select[0x40]; 13137 13138 u8 state[0x8]; 13139 u8 auto_gen[0x1]; 13140 u8 reserved_at_49[0xb]; 13141 u8 key_size[0x4]; 13142 u8 reserved_at_58[0x8]; 13143 13144 u8 reserved_at_60[0x8]; 13145 u8 pd[0x18]; 13146 13147 u8 reserved_at_80[0x180]; 13148 u8 key[8][0x80]; 13149 13150 u8 reserved_at_600[0x200]; 13151 }; 13152 13153 struct mlx5_ifc_create_int_kek_obj_in_bits { 13154 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 13155 struct mlx5_ifc_int_kek_obj_bits int_kek_object; 13156 }; 13157 13158 struct mlx5_ifc_create_int_kek_obj_out_bits { 13159 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 13160 struct mlx5_ifc_int_kek_obj_bits int_kek_object; 13161 }; 13162 13163 struct mlx5_ifc_sampler_obj_bits { 13164 u8 modify_field_select[0x40]; 13165 13166 u8 table_type[0x8]; 13167 u8 level[0x8]; 13168 u8 reserved_at_50[0xf]; 13169 u8 ignore_flow_level[0x1]; 13170 13171 u8 sample_ratio[0x20]; 13172 13173 u8 reserved_at_80[0x8]; 13174 u8 sample_table_id[0x18]; 13175 13176 u8 reserved_at_a0[0x8]; 13177 u8 default_table_id[0x18]; 13178 13179 u8 sw_steering_icm_address_rx[0x40]; 13180 u8 sw_steering_icm_address_tx[0x40]; 13181 13182 u8 reserved_at_140[0xa0]; 13183 }; 13184 13185 struct mlx5_ifc_create_sampler_obj_in_bits { 13186 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 13187 struct mlx5_ifc_sampler_obj_bits sampler_object; 13188 }; 13189 13190 struct mlx5_ifc_query_sampler_obj_out_bits { 13191 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 13192 struct mlx5_ifc_sampler_obj_bits sampler_object; 13193 }; 13194 13195 enum { 13196 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_128 = 0x0, 13197 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_256 = 0x1, 13198 }; 13199 13200 enum { 13201 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_PURPOSE_TLS = 0x1, 13202 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_PURPOSE_IPSEC = 0x2, 13203 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_PURPOSE_MACSEC = 0x4, 13204 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_PURPOSE_PSP = 0x6, 13205 }; 13206 13207 struct mlx5_ifc_tls_static_params_bits { 13208 u8 const_2[0x2]; 13209 u8 tls_version[0x4]; 13210 u8 const_1[0x2]; 13211 u8 reserved_at_8[0x14]; 13212 u8 encryption_standard[0x4]; 13213 13214 u8 reserved_at_20[0x20]; 13215 13216 u8 initial_record_number[0x40]; 13217 13218 u8 resync_tcp_sn[0x20]; 13219 13220 u8 gcm_iv[0x20]; 13221 13222 u8 implicit_iv[0x40]; 13223 13224 u8 reserved_at_100[0x8]; 13225 u8 dek_index[0x18]; 13226 13227 u8 reserved_at_120[0xe0]; 13228 }; 13229 13230 struct mlx5_ifc_tls_progress_params_bits { 13231 u8 next_record_tcp_sn[0x20]; 13232 13233 u8 hw_resync_tcp_sn[0x20]; 13234 13235 u8 record_tracker_state[0x2]; 13236 u8 auth_state[0x2]; 13237 u8 reserved_at_44[0x4]; 13238 u8 hw_offset_record_number[0x18]; 13239 }; 13240 13241 enum { 13242 MLX5_MTT_PERM_READ = 1 << 0, 13243 MLX5_MTT_PERM_WRITE = 1 << 1, 13244 MLX5_MTT_PERM_RW = MLX5_MTT_PERM_READ | MLX5_MTT_PERM_WRITE, 13245 }; 13246 13247 enum { 13248 MLX5_SUSPEND_VHCA_IN_OP_MOD_SUSPEND_INITIATOR = 0x0, 13249 MLX5_SUSPEND_VHCA_IN_OP_MOD_SUSPEND_RESPONDER = 0x1, 13250 }; 13251 13252 struct mlx5_ifc_suspend_vhca_in_bits { 13253 u8 opcode[0x10]; 13254 u8 uid[0x10]; 13255 13256 u8 reserved_at_20[0x10]; 13257 u8 op_mod[0x10]; 13258 13259 u8 reserved_at_40[0x10]; 13260 u8 vhca_id[0x10]; 13261 13262 u8 reserved_at_60[0x20]; 13263 }; 13264 13265 struct mlx5_ifc_suspend_vhca_out_bits { 13266 u8 status[0x8]; 13267 u8 reserved_at_8[0x18]; 13268 13269 u8 syndrome[0x20]; 13270 13271 u8 reserved_at_40[0x40]; 13272 }; 13273 13274 enum { 13275 MLX5_RESUME_VHCA_IN_OP_MOD_RESUME_RESPONDER = 0x0, 13276 MLX5_RESUME_VHCA_IN_OP_MOD_RESUME_INITIATOR = 0x1, 13277 }; 13278 13279 struct mlx5_ifc_resume_vhca_in_bits { 13280 u8 opcode[0x10]; 13281 u8 uid[0x10]; 13282 13283 u8 reserved_at_20[0x10]; 13284 u8 op_mod[0x10]; 13285 13286 u8 reserved_at_40[0x10]; 13287 u8 vhca_id[0x10]; 13288 13289 u8 reserved_at_60[0x20]; 13290 }; 13291 13292 struct mlx5_ifc_resume_vhca_out_bits { 13293 u8 status[0x8]; 13294 u8 reserved_at_8[0x18]; 13295 13296 u8 syndrome[0x20]; 13297 13298 u8 reserved_at_40[0x40]; 13299 }; 13300 13301 struct mlx5_ifc_query_vhca_migration_state_in_bits { 13302 u8 opcode[0x10]; 13303 u8 uid[0x10]; 13304 13305 u8 reserved_at_20[0x10]; 13306 u8 op_mod[0x10]; 13307 13308 u8 incremental[0x1]; 13309 u8 chunk[0x1]; 13310 u8 reserved_at_42[0xe]; 13311 u8 vhca_id[0x10]; 13312 13313 u8 reserved_at_60[0x20]; 13314 }; 13315 13316 struct mlx5_ifc_query_vhca_migration_state_out_bits { 13317 u8 status[0x8]; 13318 u8 reserved_at_8[0x18]; 13319 13320 u8 syndrome[0x20]; 13321 13322 u8 reserved_at_40[0x40]; 13323 13324 u8 required_umem_size[0x20]; 13325 13326 u8 reserved_at_a0[0x20]; 13327 13328 u8 remaining_total_size[0x40]; 13329 13330 u8 reserved_at_100[0x100]; 13331 }; 13332 13333 struct mlx5_ifc_save_vhca_state_in_bits { 13334 u8 opcode[0x10]; 13335 u8 uid[0x10]; 13336 13337 u8 reserved_at_20[0x10]; 13338 u8 op_mod[0x10]; 13339 13340 u8 incremental[0x1]; 13341 u8 set_track[0x1]; 13342 u8 reserved_at_42[0xe]; 13343 u8 vhca_id[0x10]; 13344 13345 u8 reserved_at_60[0x20]; 13346 13347 u8 va[0x40]; 13348 13349 u8 mkey[0x20]; 13350 13351 u8 size[0x20]; 13352 }; 13353 13354 struct mlx5_ifc_save_vhca_state_out_bits { 13355 u8 status[0x8]; 13356 u8 reserved_at_8[0x18]; 13357 13358 u8 syndrome[0x20]; 13359 13360 u8 actual_image_size[0x20]; 13361 13362 u8 next_required_umem_size[0x20]; 13363 }; 13364 13365 struct mlx5_ifc_load_vhca_state_in_bits { 13366 u8 opcode[0x10]; 13367 u8 uid[0x10]; 13368 13369 u8 reserved_at_20[0x10]; 13370 u8 op_mod[0x10]; 13371 13372 u8 reserved_at_40[0x10]; 13373 u8 vhca_id[0x10]; 13374 13375 u8 reserved_at_60[0x20]; 13376 13377 u8 va[0x40]; 13378 13379 u8 mkey[0x20]; 13380 13381 u8 size[0x20]; 13382 }; 13383 13384 struct mlx5_ifc_load_vhca_state_out_bits { 13385 u8 status[0x8]; 13386 u8 reserved_at_8[0x18]; 13387 13388 u8 syndrome[0x20]; 13389 13390 u8 reserved_at_40[0x40]; 13391 }; 13392 13393 struct mlx5_ifc_adv_rdma_cap_bits { 13394 u8 rdma_transport_manager[0x1]; 13395 u8 rdma_transport_manager_other_eswitch[0x1]; 13396 u8 reserved_at_2[0x1e]; 13397 13398 u8 rcx_type[0x8]; 13399 u8 reserved_at_28[0x2]; 13400 u8 ps_entry_log_max_value[0x6]; 13401 u8 reserved_at_30[0x6]; 13402 u8 qp_max_ps_num_entry[0xa]; 13403 13404 u8 mp_max_num_queues[0x8]; 13405 u8 ps_user_context_max_log_size[0x8]; 13406 u8 message_based_qp_and_striding_wq[0x8]; 13407 u8 reserved_at_58[0x8]; 13408 13409 u8 max_receive_send_message_size_stride[0x10]; 13410 u8 reserved_at_70[0x10]; 13411 13412 u8 max_receive_send_message_size_byte[0x20]; 13413 13414 u8 reserved_at_a0[0x160]; 13415 13416 struct mlx5_ifc_flow_table_prop_layout_bits rdma_transport_rx_flow_table_properties; 13417 13418 struct mlx5_ifc_flow_table_prop_layout_bits rdma_transport_tx_flow_table_properties; 13419 13420 struct mlx5_ifc_flow_table_fields_supported_2_bits rdma_transport_rx_ft_field_support_2; 13421 13422 struct mlx5_ifc_flow_table_fields_supported_2_bits rdma_transport_tx_ft_field_support_2; 13423 13424 struct mlx5_ifc_flow_table_fields_supported_2_bits rdma_transport_rx_ft_field_bitmask_support_2; 13425 13426 struct mlx5_ifc_flow_table_fields_supported_2_bits rdma_transport_tx_ft_field_bitmask_support_2; 13427 13428 u8 reserved_at_800[0x3800]; 13429 }; 13430 13431 struct mlx5_ifc_adv_virtualization_cap_bits { 13432 u8 reserved_at_0[0x3]; 13433 u8 pg_track_log_max_num[0x5]; 13434 u8 pg_track_max_num_range[0x8]; 13435 u8 pg_track_log_min_addr_space[0x8]; 13436 u8 pg_track_log_max_addr_space[0x8]; 13437 13438 u8 reserved_at_20[0x3]; 13439 u8 pg_track_log_min_msg_size[0x5]; 13440 u8 reserved_at_28[0x3]; 13441 u8 pg_track_log_max_msg_size[0x5]; 13442 u8 reserved_at_30[0x3]; 13443 u8 pg_track_log_min_page_size[0x5]; 13444 u8 reserved_at_38[0x3]; 13445 u8 pg_track_log_max_page_size[0x5]; 13446 13447 u8 reserved_at_40[0x7c0]; 13448 }; 13449 13450 struct mlx5_ifc_page_track_report_entry_bits { 13451 u8 dirty_address_high[0x20]; 13452 13453 u8 dirty_address_low[0x20]; 13454 }; 13455 13456 enum { 13457 MLX5_PAGE_TRACK_STATE_TRACKING, 13458 MLX5_PAGE_TRACK_STATE_REPORTING, 13459 MLX5_PAGE_TRACK_STATE_ERROR, 13460 }; 13461 13462 struct mlx5_ifc_page_track_range_bits { 13463 u8 start_address[0x40]; 13464 13465 u8 length[0x40]; 13466 }; 13467 13468 struct mlx5_ifc_page_track_bits { 13469 u8 modify_field_select[0x40]; 13470 13471 u8 reserved_at_40[0x10]; 13472 u8 vhca_id[0x10]; 13473 13474 u8 reserved_at_60[0x20]; 13475 13476 u8 state[0x4]; 13477 u8 track_type[0x4]; 13478 u8 log_addr_space_size[0x8]; 13479 u8 reserved_at_90[0x3]; 13480 u8 log_page_size[0x5]; 13481 u8 reserved_at_98[0x3]; 13482 u8 log_msg_size[0x5]; 13483 13484 u8 reserved_at_a0[0x8]; 13485 u8 reporting_qpn[0x18]; 13486 13487 u8 reserved_at_c0[0x18]; 13488 u8 num_ranges[0x8]; 13489 13490 u8 reserved_at_e0[0x20]; 13491 13492 u8 range_start_address[0x40]; 13493 13494 u8 length[0x40]; 13495 13496 struct mlx5_ifc_page_track_range_bits track_range[0]; 13497 }; 13498 13499 struct mlx5_ifc_create_page_track_obj_in_bits { 13500 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 13501 struct mlx5_ifc_page_track_bits obj_context; 13502 }; 13503 13504 struct mlx5_ifc_modify_page_track_obj_in_bits { 13505 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 13506 struct mlx5_ifc_page_track_bits obj_context; 13507 }; 13508 13509 struct mlx5_ifc_query_page_track_obj_out_bits { 13510 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 13511 struct mlx5_ifc_page_track_bits obj_context; 13512 }; 13513 13514 struct mlx5_ifc_msecq_reg_bits { 13515 u8 reserved_at_0[0x20]; 13516 13517 u8 reserved_at_20[0x12]; 13518 u8 network_option[0x2]; 13519 u8 local_ssm_code[0x4]; 13520 u8 local_enhanced_ssm_code[0x8]; 13521 13522 u8 local_clock_identity[0x40]; 13523 13524 u8 reserved_at_80[0x180]; 13525 }; 13526 13527 enum { 13528 MLX5_MSEES_FIELD_SELECT_ENABLE = BIT(0), 13529 MLX5_MSEES_FIELD_SELECT_ADMIN_STATUS = BIT(1), 13530 MLX5_MSEES_FIELD_SELECT_ADMIN_FREQ_MEASURE = BIT(2), 13531 }; 13532 13533 enum mlx5_msees_admin_status { 13534 MLX5_MSEES_ADMIN_STATUS_FREE_RUNNING = 0x0, 13535 MLX5_MSEES_ADMIN_STATUS_TRACK = 0x1, 13536 }; 13537 13538 enum mlx5_msees_oper_status { 13539 MLX5_MSEES_OPER_STATUS_FREE_RUNNING = 0x0, 13540 MLX5_MSEES_OPER_STATUS_SELF_TRACK = 0x1, 13541 MLX5_MSEES_OPER_STATUS_OTHER_TRACK = 0x2, 13542 MLX5_MSEES_OPER_STATUS_HOLDOVER = 0x3, 13543 MLX5_MSEES_OPER_STATUS_FAIL_HOLDOVER = 0x4, 13544 MLX5_MSEES_OPER_STATUS_FAIL_FREE_RUNNING = 0x5, 13545 }; 13546 13547 enum mlx5_msees_failure_reason { 13548 MLX5_MSEES_FAILURE_REASON_UNDEFINED_ERROR = 0x0, 13549 MLX5_MSEES_FAILURE_REASON_PORT_DOWN = 0x1, 13550 MLX5_MSEES_FAILURE_REASON_TOO_HIGH_FREQUENCY_DIFF = 0x2, 13551 MLX5_MSEES_FAILURE_REASON_NET_SYNCHRONIZER_DEVICE_ERROR = 0x3, 13552 MLX5_MSEES_FAILURE_REASON_LACK_OF_RESOURCES = 0x4, 13553 }; 13554 13555 struct mlx5_ifc_msees_reg_bits { 13556 u8 reserved_at_0[0x8]; 13557 u8 local_port[0x8]; 13558 u8 pnat[0x2]; 13559 u8 lp_msb[0x2]; 13560 u8 reserved_at_14[0xc]; 13561 13562 u8 field_select[0x20]; 13563 13564 u8 admin_status[0x4]; 13565 u8 oper_status[0x4]; 13566 u8 ho_acq[0x1]; 13567 u8 reserved_at_49[0xc]; 13568 u8 admin_freq_measure[0x1]; 13569 u8 oper_freq_measure[0x1]; 13570 u8 failure_reason[0x9]; 13571 13572 u8 frequency_diff[0x20]; 13573 13574 u8 reserved_at_80[0x180]; 13575 }; 13576 13577 struct mlx5_ifc_mrtcq_reg_bits { 13578 u8 reserved_at_0[0x40]; 13579 13580 u8 rt_clock_identity[0x40]; 13581 13582 u8 reserved_at_80[0x180]; 13583 }; 13584 13585 struct mlx5_ifc_pcie_cong_event_obj_bits { 13586 u8 modify_select_field[0x40]; 13587 13588 u8 inbound_event_en[0x1]; 13589 u8 outbound_event_en[0x1]; 13590 u8 reserved_at_42[0x1e]; 13591 13592 u8 reserved_at_60[0x1]; 13593 u8 inbound_cong_state[0x3]; 13594 u8 reserved_at_64[0x1]; 13595 u8 outbound_cong_state[0x3]; 13596 u8 reserved_at_68[0x18]; 13597 13598 u8 inbound_cong_low_threshold[0x10]; 13599 u8 inbound_cong_high_threshold[0x10]; 13600 13601 u8 outbound_cong_low_threshold[0x10]; 13602 u8 outbound_cong_high_threshold[0x10]; 13603 13604 u8 reserved_at_e0[0x340]; 13605 }; 13606 13607 struct mlx5_ifc_pcie_cong_event_cmd_in_bits { 13608 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 13609 struct mlx5_ifc_pcie_cong_event_obj_bits cong_obj; 13610 }; 13611 13612 struct mlx5_ifc_pcie_cong_event_cmd_out_bits { 13613 struct mlx5_ifc_general_obj_out_cmd_hdr_bits hdr; 13614 struct mlx5_ifc_pcie_cong_event_obj_bits cong_obj; 13615 }; 13616 13617 enum mlx5e_pcie_cong_event_mod_field { 13618 MLX5_PCIE_CONG_EVENT_MOD_EVENT_EN = BIT(0), 13619 MLX5_PCIE_CONG_EVENT_MOD_THRESH = BIT(2), 13620 }; 13621 13622 struct mlx5_ifc_psp_rotate_key_in_bits { 13623 u8 opcode[0x10]; 13624 u8 uid[0x10]; 13625 13626 u8 reserved_at_20[0x10]; 13627 u8 op_mod[0x10]; 13628 13629 u8 reserved_at_40[0x40]; 13630 }; 13631 13632 struct mlx5_ifc_psp_rotate_key_out_bits { 13633 u8 status[0x8]; 13634 u8 reserved_at_8[0x18]; 13635 13636 u8 syndrome[0x20]; 13637 13638 u8 reserved_at_40[0x40]; 13639 }; 13640 13641 enum mlx5_psp_gen_spi_in_key_size { 13642 MLX5_PSP_GEN_SPI_IN_KEY_SIZE_128 = 0x0, 13643 MLX5_PSP_GEN_SPI_IN_KEY_SIZE_256 = 0x1, 13644 }; 13645 13646 struct mlx5_ifc_key_spi_bits { 13647 u8 spi[0x20]; 13648 13649 u8 reserved_at_20[0x60]; 13650 13651 u8 key[8][0x20]; 13652 }; 13653 13654 struct mlx5_ifc_psp_gen_spi_in_bits { 13655 u8 opcode[0x10]; 13656 u8 uid[0x10]; 13657 13658 u8 reserved_at_20[0x10]; 13659 u8 op_mod[0x10]; 13660 13661 u8 reserved_at_40[0x20]; 13662 13663 u8 key_size[0x2]; 13664 u8 reserved_at_62[0xe]; 13665 u8 num_of_spi[0x10]; 13666 }; 13667 13668 struct mlx5_ifc_psp_gen_spi_out_bits { 13669 u8 status[0x8]; 13670 u8 reserved_at_8[0x18]; 13671 13672 u8 syndrome[0x20]; 13673 13674 u8 reserved_at_40[0x10]; 13675 u8 num_of_spi[0x10]; 13676 13677 u8 reserved_at_60[0x20]; 13678 13679 struct mlx5_ifc_key_spi_bits key_spi[]; 13680 }; 13681 13682 #endif /* MLX5_IFC_H */ 13683