1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 #ifndef MLX5_IFC_H 33 #define MLX5_IFC_H 34 35 #include "mlx5_ifc_fpga.h" 36 37 enum { 38 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0, 39 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1, 40 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2, 41 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3, 42 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13, 43 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14, 44 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c, 45 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d, 46 MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4, 47 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5, 48 MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED = 0x7, 49 MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT = 0xc, 50 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10, 51 MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR = 0x11, 52 MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR = 0x12, 53 MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR = 0x8, 54 MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE = 0x9, 55 MLX5_EVENT_TYPE_CODING_GPIO_EVENT = 0x15, 56 MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19, 57 MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a, 58 MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT = 0x1b, 59 MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT = 0x1f, 60 MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa, 61 MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb, 62 MLX5_EVENT_TYPE_CODING_FPGA_ERROR = 0x20, 63 MLX5_EVENT_TYPE_CODING_FPGA_QP_ERROR = 0x21 64 }; 65 66 enum { 67 MLX5_MODIFY_TIR_BITMASK_LRO = 0x0, 68 MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE = 0x1, 69 MLX5_MODIFY_TIR_BITMASK_HASH = 0x2, 70 MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN = 0x3 71 }; 72 73 enum { 74 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0, 75 MLX5_SET_HCA_CAP_OP_MOD_ODP = 0x2, 76 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3, 77 MLX5_SET_HCA_CAP_OP_MOD_ROCE = 0x4, 78 }; 79 80 enum { 81 MLX5_SHARED_RESOURCE_UID = 0xffff, 82 }; 83 84 enum { 85 MLX5_OBJ_TYPE_SW_ICM = 0x0008, 86 }; 87 88 enum { 89 MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM = (1ULL << MLX5_OBJ_TYPE_SW_ICM), 90 MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT = (1ULL << 11), 91 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q = (1ULL << 13), 92 }; 93 94 enum { 95 MLX5_OBJ_TYPE_GENEVE_TLV_OPT = 0x000b, 96 MLX5_OBJ_TYPE_VIRTIO_NET_Q = 0x000d, 97 MLX5_OBJ_TYPE_MKEY = 0xff01, 98 MLX5_OBJ_TYPE_QP = 0xff02, 99 MLX5_OBJ_TYPE_PSV = 0xff03, 100 MLX5_OBJ_TYPE_RMP = 0xff04, 101 MLX5_OBJ_TYPE_XRC_SRQ = 0xff05, 102 MLX5_OBJ_TYPE_RQ = 0xff06, 103 MLX5_OBJ_TYPE_SQ = 0xff07, 104 MLX5_OBJ_TYPE_TIR = 0xff08, 105 MLX5_OBJ_TYPE_TIS = 0xff09, 106 MLX5_OBJ_TYPE_DCT = 0xff0a, 107 MLX5_OBJ_TYPE_XRQ = 0xff0b, 108 MLX5_OBJ_TYPE_RQT = 0xff0e, 109 MLX5_OBJ_TYPE_FLOW_COUNTER = 0xff0f, 110 MLX5_OBJ_TYPE_CQ = 0xff10, 111 }; 112 113 enum { 114 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100, 115 MLX5_CMD_OP_QUERY_ADAPTER = 0x101, 116 MLX5_CMD_OP_INIT_HCA = 0x102, 117 MLX5_CMD_OP_TEARDOWN_HCA = 0x103, 118 MLX5_CMD_OP_ENABLE_HCA = 0x104, 119 MLX5_CMD_OP_DISABLE_HCA = 0x105, 120 MLX5_CMD_OP_QUERY_PAGES = 0x107, 121 MLX5_CMD_OP_MANAGE_PAGES = 0x108, 122 MLX5_CMD_OP_SET_HCA_CAP = 0x109, 123 MLX5_CMD_OP_QUERY_ISSI = 0x10a, 124 MLX5_CMD_OP_SET_ISSI = 0x10b, 125 MLX5_CMD_OP_SET_DRIVER_VERSION = 0x10d, 126 MLX5_CMD_OP_QUERY_SF_PARTITION = 0x111, 127 MLX5_CMD_OP_ALLOC_SF = 0x113, 128 MLX5_CMD_OP_DEALLOC_SF = 0x114, 129 MLX5_CMD_OP_CREATE_MKEY = 0x200, 130 MLX5_CMD_OP_QUERY_MKEY = 0x201, 131 MLX5_CMD_OP_DESTROY_MKEY = 0x202, 132 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203, 133 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204, 134 MLX5_CMD_OP_ALLOC_MEMIC = 0x205, 135 MLX5_CMD_OP_DEALLOC_MEMIC = 0x206, 136 MLX5_CMD_OP_MODIFY_MEMIC = 0x207, 137 MLX5_CMD_OP_CREATE_EQ = 0x301, 138 MLX5_CMD_OP_DESTROY_EQ = 0x302, 139 MLX5_CMD_OP_QUERY_EQ = 0x303, 140 MLX5_CMD_OP_GEN_EQE = 0x304, 141 MLX5_CMD_OP_CREATE_CQ = 0x400, 142 MLX5_CMD_OP_DESTROY_CQ = 0x401, 143 MLX5_CMD_OP_QUERY_CQ = 0x402, 144 MLX5_CMD_OP_MODIFY_CQ = 0x403, 145 MLX5_CMD_OP_CREATE_QP = 0x500, 146 MLX5_CMD_OP_DESTROY_QP = 0x501, 147 MLX5_CMD_OP_RST2INIT_QP = 0x502, 148 MLX5_CMD_OP_INIT2RTR_QP = 0x503, 149 MLX5_CMD_OP_RTR2RTS_QP = 0x504, 150 MLX5_CMD_OP_RTS2RTS_QP = 0x505, 151 MLX5_CMD_OP_SQERR2RTS_QP = 0x506, 152 MLX5_CMD_OP_2ERR_QP = 0x507, 153 MLX5_CMD_OP_2RST_QP = 0x50a, 154 MLX5_CMD_OP_QUERY_QP = 0x50b, 155 MLX5_CMD_OP_SQD_RTS_QP = 0x50c, 156 MLX5_CMD_OP_INIT2INIT_QP = 0x50e, 157 MLX5_CMD_OP_CREATE_PSV = 0x600, 158 MLX5_CMD_OP_DESTROY_PSV = 0x601, 159 MLX5_CMD_OP_CREATE_SRQ = 0x700, 160 MLX5_CMD_OP_DESTROY_SRQ = 0x701, 161 MLX5_CMD_OP_QUERY_SRQ = 0x702, 162 MLX5_CMD_OP_ARM_RQ = 0x703, 163 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705, 164 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706, 165 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707, 166 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708, 167 MLX5_CMD_OP_CREATE_DCT = 0x710, 168 MLX5_CMD_OP_DESTROY_DCT = 0x711, 169 MLX5_CMD_OP_DRAIN_DCT = 0x712, 170 MLX5_CMD_OP_QUERY_DCT = 0x713, 171 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714, 172 MLX5_CMD_OP_CREATE_XRQ = 0x717, 173 MLX5_CMD_OP_DESTROY_XRQ = 0x718, 174 MLX5_CMD_OP_QUERY_XRQ = 0x719, 175 MLX5_CMD_OP_ARM_XRQ = 0x71a, 176 MLX5_CMD_OP_QUERY_XRQ_DC_PARAMS_ENTRY = 0x725, 177 MLX5_CMD_OP_SET_XRQ_DC_PARAMS_ENTRY = 0x726, 178 MLX5_CMD_OP_QUERY_XRQ_ERROR_PARAMS = 0x727, 179 MLX5_CMD_OP_RELEASE_XRQ_ERROR = 0x729, 180 MLX5_CMD_OP_MODIFY_XRQ = 0x72a, 181 MLX5_CMD_OP_QUERY_ESW_FUNCTIONS = 0x740, 182 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750, 183 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751, 184 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752, 185 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753, 186 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754, 187 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755, 188 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760, 189 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761, 190 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762, 191 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763, 192 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764, 193 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765, 194 MLX5_CMD_OP_QUERY_VNIC_ENV = 0x76f, 195 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770, 196 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771, 197 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772, 198 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773, 199 MLX5_CMD_OP_SET_MONITOR_COUNTER = 0x774, 200 MLX5_CMD_OP_ARM_MONITOR_COUNTER = 0x775, 201 MLX5_CMD_OP_SET_PP_RATE_LIMIT = 0x780, 202 MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781, 203 MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT = 0x782, 204 MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT = 0x783, 205 MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT = 0x784, 206 MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT = 0x785, 207 MLX5_CMD_OP_CREATE_QOS_PARA_VPORT = 0x786, 208 MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT = 0x787, 209 MLX5_CMD_OP_ALLOC_PD = 0x800, 210 MLX5_CMD_OP_DEALLOC_PD = 0x801, 211 MLX5_CMD_OP_ALLOC_UAR = 0x802, 212 MLX5_CMD_OP_DEALLOC_UAR = 0x803, 213 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804, 214 MLX5_CMD_OP_ACCESS_REG = 0x805, 215 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806, 216 MLX5_CMD_OP_DETACH_FROM_MCG = 0x807, 217 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a, 218 MLX5_CMD_OP_MAD_IFC = 0x50d, 219 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b, 220 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c, 221 MLX5_CMD_OP_NOP = 0x80d, 222 MLX5_CMD_OP_ALLOC_XRCD = 0x80e, 223 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f, 224 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816, 225 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817, 226 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822, 227 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823, 228 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824, 229 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825, 230 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826, 231 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827, 232 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828, 233 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829, 234 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a, 235 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b, 236 MLX5_CMD_OP_SET_WOL_ROL = 0x830, 237 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831, 238 MLX5_CMD_OP_CREATE_LAG = 0x840, 239 MLX5_CMD_OP_MODIFY_LAG = 0x841, 240 MLX5_CMD_OP_QUERY_LAG = 0x842, 241 MLX5_CMD_OP_DESTROY_LAG = 0x843, 242 MLX5_CMD_OP_CREATE_VPORT_LAG = 0x844, 243 MLX5_CMD_OP_DESTROY_VPORT_LAG = 0x845, 244 MLX5_CMD_OP_CREATE_TIR = 0x900, 245 MLX5_CMD_OP_MODIFY_TIR = 0x901, 246 MLX5_CMD_OP_DESTROY_TIR = 0x902, 247 MLX5_CMD_OP_QUERY_TIR = 0x903, 248 MLX5_CMD_OP_CREATE_SQ = 0x904, 249 MLX5_CMD_OP_MODIFY_SQ = 0x905, 250 MLX5_CMD_OP_DESTROY_SQ = 0x906, 251 MLX5_CMD_OP_QUERY_SQ = 0x907, 252 MLX5_CMD_OP_CREATE_RQ = 0x908, 253 MLX5_CMD_OP_MODIFY_RQ = 0x909, 254 MLX5_CMD_OP_SET_DELAY_DROP_PARAMS = 0x910, 255 MLX5_CMD_OP_DESTROY_RQ = 0x90a, 256 MLX5_CMD_OP_QUERY_RQ = 0x90b, 257 MLX5_CMD_OP_CREATE_RMP = 0x90c, 258 MLX5_CMD_OP_MODIFY_RMP = 0x90d, 259 MLX5_CMD_OP_DESTROY_RMP = 0x90e, 260 MLX5_CMD_OP_QUERY_RMP = 0x90f, 261 MLX5_CMD_OP_CREATE_TIS = 0x912, 262 MLX5_CMD_OP_MODIFY_TIS = 0x913, 263 MLX5_CMD_OP_DESTROY_TIS = 0x914, 264 MLX5_CMD_OP_QUERY_TIS = 0x915, 265 MLX5_CMD_OP_CREATE_RQT = 0x916, 266 MLX5_CMD_OP_MODIFY_RQT = 0x917, 267 MLX5_CMD_OP_DESTROY_RQT = 0x918, 268 MLX5_CMD_OP_QUERY_RQT = 0x919, 269 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f, 270 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930, 271 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931, 272 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932, 273 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933, 274 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934, 275 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935, 276 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936, 277 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937, 278 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938, 279 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939, 280 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a, 281 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b, 282 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c, 283 MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT = 0x93d, 284 MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT = 0x93e, 285 MLX5_CMD_OP_QUERY_PACKET_REFORMAT_CONTEXT = 0x93f, 286 MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT = 0x940, 287 MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941, 288 MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT = 0x942, 289 MLX5_CMD_OP_FPGA_CREATE_QP = 0x960, 290 MLX5_CMD_OP_FPGA_MODIFY_QP = 0x961, 291 MLX5_CMD_OP_FPGA_QUERY_QP = 0x962, 292 MLX5_CMD_OP_FPGA_DESTROY_QP = 0x963, 293 MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS = 0x964, 294 MLX5_CMD_OP_CREATE_GENERAL_OBJECT = 0xa00, 295 MLX5_CMD_OP_MODIFY_GENERAL_OBJECT = 0xa01, 296 MLX5_CMD_OP_QUERY_GENERAL_OBJECT = 0xa02, 297 MLX5_CMD_OP_DESTROY_GENERAL_OBJECT = 0xa03, 298 MLX5_CMD_OP_CREATE_UCTX = 0xa04, 299 MLX5_CMD_OP_DESTROY_UCTX = 0xa06, 300 MLX5_CMD_OP_CREATE_UMEM = 0xa08, 301 MLX5_CMD_OP_DESTROY_UMEM = 0xa0a, 302 MLX5_CMD_OP_SYNC_STEERING = 0xb00, 303 MLX5_CMD_OP_QUERY_VHCA_STATE = 0xb0d, 304 MLX5_CMD_OP_MODIFY_VHCA_STATE = 0xb0e, 305 MLX5_CMD_OP_MAX 306 }; 307 308 /* Valid range for general commands that don't work over an object */ 309 enum { 310 MLX5_CMD_OP_GENERAL_START = 0xb00, 311 MLX5_CMD_OP_GENERAL_END = 0xd00, 312 }; 313 314 struct mlx5_ifc_flow_table_fields_supported_bits { 315 u8 outer_dmac[0x1]; 316 u8 outer_smac[0x1]; 317 u8 outer_ether_type[0x1]; 318 u8 outer_ip_version[0x1]; 319 u8 outer_first_prio[0x1]; 320 u8 outer_first_cfi[0x1]; 321 u8 outer_first_vid[0x1]; 322 u8 outer_ipv4_ttl[0x1]; 323 u8 outer_second_prio[0x1]; 324 u8 outer_second_cfi[0x1]; 325 u8 outer_second_vid[0x1]; 326 u8 reserved_at_b[0x1]; 327 u8 outer_sip[0x1]; 328 u8 outer_dip[0x1]; 329 u8 outer_frag[0x1]; 330 u8 outer_ip_protocol[0x1]; 331 u8 outer_ip_ecn[0x1]; 332 u8 outer_ip_dscp[0x1]; 333 u8 outer_udp_sport[0x1]; 334 u8 outer_udp_dport[0x1]; 335 u8 outer_tcp_sport[0x1]; 336 u8 outer_tcp_dport[0x1]; 337 u8 outer_tcp_flags[0x1]; 338 u8 outer_gre_protocol[0x1]; 339 u8 outer_gre_key[0x1]; 340 u8 outer_vxlan_vni[0x1]; 341 u8 outer_geneve_vni[0x1]; 342 u8 outer_geneve_oam[0x1]; 343 u8 outer_geneve_protocol_type[0x1]; 344 u8 outer_geneve_opt_len[0x1]; 345 u8 reserved_at_1e[0x1]; 346 u8 source_eswitch_port[0x1]; 347 348 u8 inner_dmac[0x1]; 349 u8 inner_smac[0x1]; 350 u8 inner_ether_type[0x1]; 351 u8 inner_ip_version[0x1]; 352 u8 inner_first_prio[0x1]; 353 u8 inner_first_cfi[0x1]; 354 u8 inner_first_vid[0x1]; 355 u8 reserved_at_27[0x1]; 356 u8 inner_second_prio[0x1]; 357 u8 inner_second_cfi[0x1]; 358 u8 inner_second_vid[0x1]; 359 u8 reserved_at_2b[0x1]; 360 u8 inner_sip[0x1]; 361 u8 inner_dip[0x1]; 362 u8 inner_frag[0x1]; 363 u8 inner_ip_protocol[0x1]; 364 u8 inner_ip_ecn[0x1]; 365 u8 inner_ip_dscp[0x1]; 366 u8 inner_udp_sport[0x1]; 367 u8 inner_udp_dport[0x1]; 368 u8 inner_tcp_sport[0x1]; 369 u8 inner_tcp_dport[0x1]; 370 u8 inner_tcp_flags[0x1]; 371 u8 reserved_at_37[0x9]; 372 373 u8 geneve_tlv_option_0_data[0x1]; 374 u8 reserved_at_41[0x4]; 375 u8 outer_first_mpls_over_udp[0x4]; 376 u8 outer_first_mpls_over_gre[0x4]; 377 u8 inner_first_mpls[0x4]; 378 u8 outer_first_mpls[0x4]; 379 u8 reserved_at_55[0x2]; 380 u8 outer_esp_spi[0x1]; 381 u8 reserved_at_58[0x2]; 382 u8 bth_dst_qp[0x1]; 383 u8 reserved_at_5b[0x5]; 384 385 u8 reserved_at_60[0x18]; 386 u8 metadata_reg_c_7[0x1]; 387 u8 metadata_reg_c_6[0x1]; 388 u8 metadata_reg_c_5[0x1]; 389 u8 metadata_reg_c_4[0x1]; 390 u8 metadata_reg_c_3[0x1]; 391 u8 metadata_reg_c_2[0x1]; 392 u8 metadata_reg_c_1[0x1]; 393 u8 metadata_reg_c_0[0x1]; 394 }; 395 396 struct mlx5_ifc_flow_table_prop_layout_bits { 397 u8 ft_support[0x1]; 398 u8 reserved_at_1[0x1]; 399 u8 flow_counter[0x1]; 400 u8 flow_modify_en[0x1]; 401 u8 modify_root[0x1]; 402 u8 identified_miss_table_mode[0x1]; 403 u8 flow_table_modify[0x1]; 404 u8 reformat[0x1]; 405 u8 decap[0x1]; 406 u8 reserved_at_9[0x1]; 407 u8 pop_vlan[0x1]; 408 u8 push_vlan[0x1]; 409 u8 reserved_at_c[0x1]; 410 u8 pop_vlan_2[0x1]; 411 u8 push_vlan_2[0x1]; 412 u8 reformat_and_vlan_action[0x1]; 413 u8 reserved_at_10[0x1]; 414 u8 sw_owner[0x1]; 415 u8 reformat_l3_tunnel_to_l2[0x1]; 416 u8 reformat_l2_to_l3_tunnel[0x1]; 417 u8 reformat_and_modify_action[0x1]; 418 u8 ignore_flow_level[0x1]; 419 u8 reserved_at_16[0x1]; 420 u8 table_miss_action_domain[0x1]; 421 u8 termination_table[0x1]; 422 u8 reformat_and_fwd_to_table[0x1]; 423 u8 reserved_at_1a[0x2]; 424 u8 ipsec_encrypt[0x1]; 425 u8 ipsec_decrypt[0x1]; 426 u8 sw_owner_v2[0x1]; 427 u8 reserved_at_1f[0x1]; 428 429 u8 termination_table_raw_traffic[0x1]; 430 u8 reserved_at_21[0x1]; 431 u8 log_max_ft_size[0x6]; 432 u8 log_max_modify_header_context[0x8]; 433 u8 max_modify_header_actions[0x8]; 434 u8 max_ft_level[0x8]; 435 436 u8 reserved_at_40[0x20]; 437 438 u8 reserved_at_60[0x2]; 439 u8 reformat_insert[0x1]; 440 u8 reformat_remove[0x1]; 441 u8 reserver_at_64[0x14]; 442 u8 log_max_ft_num[0x8]; 443 444 u8 reserved_at_80[0x10]; 445 u8 log_max_flow_counter[0x8]; 446 u8 log_max_destination[0x8]; 447 448 u8 reserved_at_a0[0x18]; 449 u8 log_max_flow[0x8]; 450 451 u8 reserved_at_c0[0x40]; 452 453 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support; 454 455 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support; 456 }; 457 458 struct mlx5_ifc_odp_per_transport_service_cap_bits { 459 u8 send[0x1]; 460 u8 receive[0x1]; 461 u8 write[0x1]; 462 u8 read[0x1]; 463 u8 atomic[0x1]; 464 u8 srq_receive[0x1]; 465 u8 reserved_at_6[0x1a]; 466 }; 467 468 struct mlx5_ifc_fte_match_set_lyr_2_4_bits { 469 u8 smac_47_16[0x20]; 470 471 u8 smac_15_0[0x10]; 472 u8 ethertype[0x10]; 473 474 u8 dmac_47_16[0x20]; 475 476 u8 dmac_15_0[0x10]; 477 u8 first_prio[0x3]; 478 u8 first_cfi[0x1]; 479 u8 first_vid[0xc]; 480 481 u8 ip_protocol[0x8]; 482 u8 ip_dscp[0x6]; 483 u8 ip_ecn[0x2]; 484 u8 cvlan_tag[0x1]; 485 u8 svlan_tag[0x1]; 486 u8 frag[0x1]; 487 u8 ip_version[0x4]; 488 u8 tcp_flags[0x9]; 489 490 u8 tcp_sport[0x10]; 491 u8 tcp_dport[0x10]; 492 493 u8 reserved_at_c0[0x18]; 494 u8 ttl_hoplimit[0x8]; 495 496 u8 udp_sport[0x10]; 497 u8 udp_dport[0x10]; 498 499 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6; 500 501 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6; 502 }; 503 504 struct mlx5_ifc_nvgre_key_bits { 505 u8 hi[0x18]; 506 u8 lo[0x8]; 507 }; 508 509 union mlx5_ifc_gre_key_bits { 510 struct mlx5_ifc_nvgre_key_bits nvgre; 511 u8 key[0x20]; 512 }; 513 514 struct mlx5_ifc_fte_match_set_misc_bits { 515 u8 gre_c_present[0x1]; 516 u8 reserved_at_1[0x1]; 517 u8 gre_k_present[0x1]; 518 u8 gre_s_present[0x1]; 519 u8 source_vhca_port[0x4]; 520 u8 source_sqn[0x18]; 521 522 u8 source_eswitch_owner_vhca_id[0x10]; 523 u8 source_port[0x10]; 524 525 u8 outer_second_prio[0x3]; 526 u8 outer_second_cfi[0x1]; 527 u8 outer_second_vid[0xc]; 528 u8 inner_second_prio[0x3]; 529 u8 inner_second_cfi[0x1]; 530 u8 inner_second_vid[0xc]; 531 532 u8 outer_second_cvlan_tag[0x1]; 533 u8 inner_second_cvlan_tag[0x1]; 534 u8 outer_second_svlan_tag[0x1]; 535 u8 inner_second_svlan_tag[0x1]; 536 u8 reserved_at_64[0xc]; 537 u8 gre_protocol[0x10]; 538 539 union mlx5_ifc_gre_key_bits gre_key; 540 541 u8 vxlan_vni[0x18]; 542 u8 reserved_at_b8[0x8]; 543 544 u8 geneve_vni[0x18]; 545 u8 reserved_at_d8[0x7]; 546 u8 geneve_oam[0x1]; 547 548 u8 reserved_at_e0[0xc]; 549 u8 outer_ipv6_flow_label[0x14]; 550 551 u8 reserved_at_100[0xc]; 552 u8 inner_ipv6_flow_label[0x14]; 553 554 u8 reserved_at_120[0xa]; 555 u8 geneve_opt_len[0x6]; 556 u8 geneve_protocol_type[0x10]; 557 558 u8 reserved_at_140[0x8]; 559 u8 bth_dst_qp[0x18]; 560 u8 reserved_at_160[0x20]; 561 u8 outer_esp_spi[0x20]; 562 u8 reserved_at_1a0[0x60]; 563 }; 564 565 struct mlx5_ifc_fte_match_mpls_bits { 566 u8 mpls_label[0x14]; 567 u8 mpls_exp[0x3]; 568 u8 mpls_s_bos[0x1]; 569 u8 mpls_ttl[0x8]; 570 }; 571 572 struct mlx5_ifc_fte_match_set_misc2_bits { 573 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls; 574 575 struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls; 576 577 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre; 578 579 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp; 580 581 u8 metadata_reg_c_7[0x20]; 582 583 u8 metadata_reg_c_6[0x20]; 584 585 u8 metadata_reg_c_5[0x20]; 586 587 u8 metadata_reg_c_4[0x20]; 588 589 u8 metadata_reg_c_3[0x20]; 590 591 u8 metadata_reg_c_2[0x20]; 592 593 u8 metadata_reg_c_1[0x20]; 594 595 u8 metadata_reg_c_0[0x20]; 596 597 u8 metadata_reg_a[0x20]; 598 599 u8 reserved_at_1a0[0x60]; 600 }; 601 602 struct mlx5_ifc_fte_match_set_misc3_bits { 603 u8 inner_tcp_seq_num[0x20]; 604 605 u8 outer_tcp_seq_num[0x20]; 606 607 u8 inner_tcp_ack_num[0x20]; 608 609 u8 outer_tcp_ack_num[0x20]; 610 611 u8 reserved_at_80[0x8]; 612 u8 outer_vxlan_gpe_vni[0x18]; 613 614 u8 outer_vxlan_gpe_next_protocol[0x8]; 615 u8 outer_vxlan_gpe_flags[0x8]; 616 u8 reserved_at_b0[0x10]; 617 618 u8 icmp_header_data[0x20]; 619 620 u8 icmpv6_header_data[0x20]; 621 622 u8 icmp_type[0x8]; 623 u8 icmp_code[0x8]; 624 u8 icmpv6_type[0x8]; 625 u8 icmpv6_code[0x8]; 626 627 u8 geneve_tlv_option_0_data[0x20]; 628 629 u8 gtpu_teid[0x20]; 630 631 u8 gtpu_msg_type[0x8]; 632 u8 gtpu_msg_flags[0x8]; 633 u8 reserved_at_170[0x10]; 634 635 u8 gtpu_dw_2[0x20]; 636 637 u8 gtpu_first_ext_dw_0[0x20]; 638 639 u8 gtpu_dw_0[0x20]; 640 641 u8 reserved_at_1e0[0x20]; 642 }; 643 644 struct mlx5_ifc_fte_match_set_misc4_bits { 645 u8 prog_sample_field_value_0[0x20]; 646 647 u8 prog_sample_field_id_0[0x20]; 648 649 u8 prog_sample_field_value_1[0x20]; 650 651 u8 prog_sample_field_id_1[0x20]; 652 653 u8 prog_sample_field_value_2[0x20]; 654 655 u8 prog_sample_field_id_2[0x20]; 656 657 u8 prog_sample_field_value_3[0x20]; 658 659 u8 prog_sample_field_id_3[0x20]; 660 661 u8 reserved_at_100[0x100]; 662 }; 663 664 struct mlx5_ifc_cmd_pas_bits { 665 u8 pa_h[0x20]; 666 667 u8 pa_l[0x14]; 668 u8 reserved_at_34[0xc]; 669 }; 670 671 struct mlx5_ifc_uint64_bits { 672 u8 hi[0x20]; 673 674 u8 lo[0x20]; 675 }; 676 677 enum { 678 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0, 679 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7, 680 MLX5_ADS_STAT_RATE_10GBPS = 0x8, 681 MLX5_ADS_STAT_RATE_30GBPS = 0x9, 682 MLX5_ADS_STAT_RATE_5GBPS = 0xa, 683 MLX5_ADS_STAT_RATE_20GBPS = 0xb, 684 MLX5_ADS_STAT_RATE_40GBPS = 0xc, 685 MLX5_ADS_STAT_RATE_60GBPS = 0xd, 686 MLX5_ADS_STAT_RATE_80GBPS = 0xe, 687 MLX5_ADS_STAT_RATE_120GBPS = 0xf, 688 }; 689 690 struct mlx5_ifc_ads_bits { 691 u8 fl[0x1]; 692 u8 free_ar[0x1]; 693 u8 reserved_at_2[0xe]; 694 u8 pkey_index[0x10]; 695 696 u8 reserved_at_20[0x8]; 697 u8 grh[0x1]; 698 u8 mlid[0x7]; 699 u8 rlid[0x10]; 700 701 u8 ack_timeout[0x5]; 702 u8 reserved_at_45[0x3]; 703 u8 src_addr_index[0x8]; 704 u8 reserved_at_50[0x4]; 705 u8 stat_rate[0x4]; 706 u8 hop_limit[0x8]; 707 708 u8 reserved_at_60[0x4]; 709 u8 tclass[0x8]; 710 u8 flow_label[0x14]; 711 712 u8 rgid_rip[16][0x8]; 713 714 u8 reserved_at_100[0x4]; 715 u8 f_dscp[0x1]; 716 u8 f_ecn[0x1]; 717 u8 reserved_at_106[0x1]; 718 u8 f_eth_prio[0x1]; 719 u8 ecn[0x2]; 720 u8 dscp[0x6]; 721 u8 udp_sport[0x10]; 722 723 u8 dei_cfi[0x1]; 724 u8 eth_prio[0x3]; 725 u8 sl[0x4]; 726 u8 vhca_port_num[0x8]; 727 u8 rmac_47_32[0x10]; 728 729 u8 rmac_31_0[0x20]; 730 }; 731 732 struct mlx5_ifc_flow_table_nic_cap_bits { 733 u8 nic_rx_multi_path_tirs[0x1]; 734 u8 nic_rx_multi_path_tirs_fts[0x1]; 735 u8 allow_sniffer_and_nic_rx_shared_tir[0x1]; 736 u8 reserved_at_3[0x4]; 737 u8 sw_owner_reformat_supported[0x1]; 738 u8 reserved_at_8[0x18]; 739 740 u8 encap_general_header[0x1]; 741 u8 reserved_at_21[0xa]; 742 u8 log_max_packet_reformat_context[0x5]; 743 u8 reserved_at_30[0x6]; 744 u8 max_encap_header_size[0xa]; 745 u8 reserved_at_40[0x1c0]; 746 747 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive; 748 749 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_rdma; 750 751 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer; 752 753 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit; 754 755 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_rdma; 756 757 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer; 758 759 u8 reserved_at_e00[0x1200]; 760 761 u8 sw_steering_nic_rx_action_drop_icm_address[0x40]; 762 763 u8 sw_steering_nic_tx_action_drop_icm_address[0x40]; 764 765 u8 sw_steering_nic_tx_action_allow_icm_address[0x40]; 766 767 u8 reserved_at_20c0[0x5f40]; 768 }; 769 770 enum { 771 MLX5_FDB_TO_VPORT_REG_C_0 = 0x01, 772 MLX5_FDB_TO_VPORT_REG_C_1 = 0x02, 773 MLX5_FDB_TO_VPORT_REG_C_2 = 0x04, 774 MLX5_FDB_TO_VPORT_REG_C_3 = 0x08, 775 MLX5_FDB_TO_VPORT_REG_C_4 = 0x10, 776 MLX5_FDB_TO_VPORT_REG_C_5 = 0x20, 777 MLX5_FDB_TO_VPORT_REG_C_6 = 0x40, 778 MLX5_FDB_TO_VPORT_REG_C_7 = 0x80, 779 }; 780 781 struct mlx5_ifc_flow_table_eswitch_cap_bits { 782 u8 fdb_to_vport_reg_c_id[0x8]; 783 u8 reserved_at_8[0xd]; 784 u8 fdb_modify_header_fwd_to_table[0x1]; 785 u8 reserved_at_16[0x1]; 786 u8 flow_source[0x1]; 787 u8 reserved_at_18[0x2]; 788 u8 multi_fdb_encap[0x1]; 789 u8 egress_acl_forward_to_vport[0x1]; 790 u8 fdb_multi_path_to_table[0x1]; 791 u8 reserved_at_1d[0x3]; 792 793 u8 reserved_at_20[0x1e0]; 794 795 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb; 796 797 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress; 798 799 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress; 800 801 u8 reserved_at_800[0x1000]; 802 803 u8 sw_steering_fdb_action_drop_icm_address_rx[0x40]; 804 805 u8 sw_steering_fdb_action_drop_icm_address_tx[0x40]; 806 807 u8 sw_steering_uplink_icm_address_rx[0x40]; 808 809 u8 sw_steering_uplink_icm_address_tx[0x40]; 810 811 u8 reserved_at_1900[0x6700]; 812 }; 813 814 enum { 815 MLX5_COUNTER_SOURCE_ESWITCH = 0x0, 816 MLX5_COUNTER_FLOW_ESWITCH = 0x1, 817 }; 818 819 struct mlx5_ifc_e_switch_cap_bits { 820 u8 vport_svlan_strip[0x1]; 821 u8 vport_cvlan_strip[0x1]; 822 u8 vport_svlan_insert[0x1]; 823 u8 vport_cvlan_insert_if_not_exist[0x1]; 824 u8 vport_cvlan_insert_overwrite[0x1]; 825 u8 reserved_at_5[0x2]; 826 u8 esw_shared_ingress_acl[0x1]; 827 u8 esw_uplink_ingress_acl[0x1]; 828 u8 root_ft_on_other_esw[0x1]; 829 u8 reserved_at_a[0xf]; 830 u8 esw_functions_changed[0x1]; 831 u8 reserved_at_1a[0x1]; 832 u8 ecpf_vport_exists[0x1]; 833 u8 counter_eswitch_affinity[0x1]; 834 u8 merged_eswitch[0x1]; 835 u8 nic_vport_node_guid_modify[0x1]; 836 u8 nic_vport_port_guid_modify[0x1]; 837 838 u8 vxlan_encap_decap[0x1]; 839 u8 nvgre_encap_decap[0x1]; 840 u8 reserved_at_22[0x1]; 841 u8 log_max_fdb_encap_uplink[0x5]; 842 u8 reserved_at_21[0x3]; 843 u8 log_max_packet_reformat_context[0x5]; 844 u8 reserved_2b[0x6]; 845 u8 max_encap_header_size[0xa]; 846 847 u8 reserved_at_40[0xb]; 848 u8 log_max_esw_sf[0x5]; 849 u8 esw_sf_base_id[0x10]; 850 851 u8 reserved_at_60[0x7a0]; 852 853 }; 854 855 struct mlx5_ifc_qos_cap_bits { 856 u8 packet_pacing[0x1]; 857 u8 esw_scheduling[0x1]; 858 u8 esw_bw_share[0x1]; 859 u8 esw_rate_limit[0x1]; 860 u8 reserved_at_4[0x1]; 861 u8 packet_pacing_burst_bound[0x1]; 862 u8 packet_pacing_typical_size[0x1]; 863 u8 reserved_at_7[0x1]; 864 u8 nic_sq_scheduling[0x1]; 865 u8 nic_bw_share[0x1]; 866 u8 nic_rate_limit[0x1]; 867 u8 packet_pacing_uid[0x1]; 868 u8 reserved_at_c[0x14]; 869 870 u8 reserved_at_20[0xb]; 871 u8 log_max_qos_nic_queue_group[0x5]; 872 u8 reserved_at_30[0x10]; 873 874 u8 packet_pacing_max_rate[0x20]; 875 876 u8 packet_pacing_min_rate[0x20]; 877 878 u8 reserved_at_80[0x10]; 879 u8 packet_pacing_rate_table_size[0x10]; 880 881 u8 esw_element_type[0x10]; 882 u8 esw_tsar_type[0x10]; 883 884 u8 reserved_at_c0[0x10]; 885 u8 max_qos_para_vport[0x10]; 886 887 u8 max_tsar_bw_share[0x20]; 888 889 u8 reserved_at_100[0x700]; 890 }; 891 892 struct mlx5_ifc_debug_cap_bits { 893 u8 core_dump_general[0x1]; 894 u8 core_dump_qp[0x1]; 895 u8 reserved_at_2[0x7]; 896 u8 resource_dump[0x1]; 897 u8 reserved_at_a[0x16]; 898 899 u8 reserved_at_20[0x2]; 900 u8 stall_detect[0x1]; 901 u8 reserved_at_23[0x1d]; 902 903 u8 reserved_at_40[0x7c0]; 904 }; 905 906 struct mlx5_ifc_per_protocol_networking_offload_caps_bits { 907 u8 csum_cap[0x1]; 908 u8 vlan_cap[0x1]; 909 u8 lro_cap[0x1]; 910 u8 lro_psh_flag[0x1]; 911 u8 lro_time_stamp[0x1]; 912 u8 reserved_at_5[0x2]; 913 u8 wqe_vlan_insert[0x1]; 914 u8 self_lb_en_modifiable[0x1]; 915 u8 reserved_at_9[0x2]; 916 u8 max_lso_cap[0x5]; 917 u8 multi_pkt_send_wqe[0x2]; 918 u8 wqe_inline_mode[0x2]; 919 u8 rss_ind_tbl_cap[0x4]; 920 u8 reg_umr_sq[0x1]; 921 u8 scatter_fcs[0x1]; 922 u8 enhanced_multi_pkt_send_wqe[0x1]; 923 u8 tunnel_lso_const_out_ip_id[0x1]; 924 u8 reserved_at_1c[0x2]; 925 u8 tunnel_stateless_gre[0x1]; 926 u8 tunnel_stateless_vxlan[0x1]; 927 928 u8 swp[0x1]; 929 u8 swp_csum[0x1]; 930 u8 swp_lso[0x1]; 931 u8 cqe_checksum_full[0x1]; 932 u8 tunnel_stateless_geneve_tx[0x1]; 933 u8 tunnel_stateless_mpls_over_udp[0x1]; 934 u8 tunnel_stateless_mpls_over_gre[0x1]; 935 u8 tunnel_stateless_vxlan_gpe[0x1]; 936 u8 tunnel_stateless_ipv4_over_vxlan[0x1]; 937 u8 tunnel_stateless_ip_over_ip[0x1]; 938 u8 insert_trailer[0x1]; 939 u8 reserved_at_2b[0x1]; 940 u8 tunnel_stateless_ip_over_ip_rx[0x1]; 941 u8 tunnel_stateless_ip_over_ip_tx[0x1]; 942 u8 reserved_at_2e[0x2]; 943 u8 max_vxlan_udp_ports[0x8]; 944 u8 reserved_at_38[0x6]; 945 u8 max_geneve_opt_len[0x1]; 946 u8 tunnel_stateless_geneve_rx[0x1]; 947 948 u8 reserved_at_40[0x10]; 949 u8 lro_min_mss_size[0x10]; 950 951 u8 reserved_at_60[0x120]; 952 953 u8 lro_timer_supported_periods[4][0x20]; 954 955 u8 reserved_at_200[0x600]; 956 }; 957 958 enum { 959 MLX5_QP_TIMESTAMP_FORMAT_CAP_FREE_RUNNING = 0x0, 960 MLX5_QP_TIMESTAMP_FORMAT_CAP_REAL_TIME = 0x1, 961 MLX5_QP_TIMESTAMP_FORMAT_CAP_FREE_RUNNING_AND_REAL_TIME = 0x2, 962 }; 963 964 struct mlx5_ifc_roce_cap_bits { 965 u8 roce_apm[0x1]; 966 u8 reserved_at_1[0x3]; 967 u8 sw_r_roce_src_udp_port[0x1]; 968 u8 fl_rc_qp_when_roce_disabled[0x1]; 969 u8 fl_rc_qp_when_roce_enabled[0x1]; 970 u8 reserved_at_7[0x17]; 971 u8 qp_ts_format[0x2]; 972 973 u8 reserved_at_20[0x60]; 974 975 u8 reserved_at_80[0xc]; 976 u8 l3_type[0x4]; 977 u8 reserved_at_90[0x8]; 978 u8 roce_version[0x8]; 979 980 u8 reserved_at_a0[0x10]; 981 u8 r_roce_dest_udp_port[0x10]; 982 983 u8 r_roce_max_src_udp_port[0x10]; 984 u8 r_roce_min_src_udp_port[0x10]; 985 986 u8 reserved_at_e0[0x10]; 987 u8 roce_address_table_size[0x10]; 988 989 u8 reserved_at_100[0x700]; 990 }; 991 992 struct mlx5_ifc_sync_steering_in_bits { 993 u8 opcode[0x10]; 994 u8 uid[0x10]; 995 996 u8 reserved_at_20[0x10]; 997 u8 op_mod[0x10]; 998 999 u8 reserved_at_40[0xc0]; 1000 }; 1001 1002 struct mlx5_ifc_sync_steering_out_bits { 1003 u8 status[0x8]; 1004 u8 reserved_at_8[0x18]; 1005 1006 u8 syndrome[0x20]; 1007 1008 u8 reserved_at_40[0x40]; 1009 }; 1010 1011 struct mlx5_ifc_device_mem_cap_bits { 1012 u8 memic[0x1]; 1013 u8 reserved_at_1[0x1f]; 1014 1015 u8 reserved_at_20[0xb]; 1016 u8 log_min_memic_alloc_size[0x5]; 1017 u8 reserved_at_30[0x8]; 1018 u8 log_max_memic_addr_alignment[0x8]; 1019 1020 u8 memic_bar_start_addr[0x40]; 1021 1022 u8 memic_bar_size[0x20]; 1023 1024 u8 max_memic_size[0x20]; 1025 1026 u8 steering_sw_icm_start_address[0x40]; 1027 1028 u8 reserved_at_100[0x8]; 1029 u8 log_header_modify_sw_icm_size[0x8]; 1030 u8 reserved_at_110[0x2]; 1031 u8 log_sw_icm_alloc_granularity[0x6]; 1032 u8 log_steering_sw_icm_size[0x8]; 1033 1034 u8 reserved_at_120[0x20]; 1035 1036 u8 header_modify_sw_icm_start_address[0x40]; 1037 1038 u8 reserved_at_180[0x80]; 1039 1040 u8 memic_operations[0x20]; 1041 1042 u8 reserved_at_220[0x5e0]; 1043 }; 1044 1045 struct mlx5_ifc_device_event_cap_bits { 1046 u8 user_affiliated_events[4][0x40]; 1047 1048 u8 user_unaffiliated_events[4][0x40]; 1049 }; 1050 1051 struct mlx5_ifc_virtio_emulation_cap_bits { 1052 u8 desc_tunnel_offload_type[0x1]; 1053 u8 eth_frame_offload_type[0x1]; 1054 u8 virtio_version_1_0[0x1]; 1055 u8 device_features_bits_mask[0xd]; 1056 u8 event_mode[0x8]; 1057 u8 virtio_queue_type[0x8]; 1058 1059 u8 max_tunnel_desc[0x10]; 1060 u8 reserved_at_30[0x3]; 1061 u8 log_doorbell_stride[0x5]; 1062 u8 reserved_at_38[0x3]; 1063 u8 log_doorbell_bar_size[0x5]; 1064 1065 u8 doorbell_bar_offset[0x40]; 1066 1067 u8 max_emulated_devices[0x8]; 1068 u8 max_num_virtio_queues[0x18]; 1069 1070 u8 reserved_at_a0[0x60]; 1071 1072 u8 umem_1_buffer_param_a[0x20]; 1073 1074 u8 umem_1_buffer_param_b[0x20]; 1075 1076 u8 umem_2_buffer_param_a[0x20]; 1077 1078 u8 umem_2_buffer_param_b[0x20]; 1079 1080 u8 umem_3_buffer_param_a[0x20]; 1081 1082 u8 umem_3_buffer_param_b[0x20]; 1083 1084 u8 reserved_at_1c0[0x640]; 1085 }; 1086 1087 enum { 1088 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0, 1089 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2, 1090 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4, 1091 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8, 1092 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10, 1093 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20, 1094 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40, 1095 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80, 1096 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100, 1097 }; 1098 1099 enum { 1100 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1, 1101 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2, 1102 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4, 1103 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8, 1104 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10, 1105 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20, 1106 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40, 1107 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80, 1108 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100, 1109 }; 1110 1111 struct mlx5_ifc_atomic_caps_bits { 1112 u8 reserved_at_0[0x40]; 1113 1114 u8 atomic_req_8B_endianness_mode[0x2]; 1115 u8 reserved_at_42[0x4]; 1116 u8 supported_atomic_req_8B_endianness_mode_1[0x1]; 1117 1118 u8 reserved_at_47[0x19]; 1119 1120 u8 reserved_at_60[0x20]; 1121 1122 u8 reserved_at_80[0x10]; 1123 u8 atomic_operations[0x10]; 1124 1125 u8 reserved_at_a0[0x10]; 1126 u8 atomic_size_qp[0x10]; 1127 1128 u8 reserved_at_c0[0x10]; 1129 u8 atomic_size_dc[0x10]; 1130 1131 u8 reserved_at_e0[0x720]; 1132 }; 1133 1134 struct mlx5_ifc_odp_cap_bits { 1135 u8 reserved_at_0[0x40]; 1136 1137 u8 sig[0x1]; 1138 u8 reserved_at_41[0x1f]; 1139 1140 u8 reserved_at_60[0x20]; 1141 1142 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps; 1143 1144 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps; 1145 1146 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps; 1147 1148 struct mlx5_ifc_odp_per_transport_service_cap_bits xrc_odp_caps; 1149 1150 struct mlx5_ifc_odp_per_transport_service_cap_bits dc_odp_caps; 1151 1152 u8 reserved_at_120[0x6E0]; 1153 }; 1154 1155 struct mlx5_ifc_calc_op { 1156 u8 reserved_at_0[0x10]; 1157 u8 reserved_at_10[0x9]; 1158 u8 op_swap_endianness[0x1]; 1159 u8 op_min[0x1]; 1160 u8 op_xor[0x1]; 1161 u8 op_or[0x1]; 1162 u8 op_and[0x1]; 1163 u8 op_max[0x1]; 1164 u8 op_add[0x1]; 1165 }; 1166 1167 struct mlx5_ifc_vector_calc_cap_bits { 1168 u8 calc_matrix[0x1]; 1169 u8 reserved_at_1[0x1f]; 1170 u8 reserved_at_20[0x8]; 1171 u8 max_vec_count[0x8]; 1172 u8 reserved_at_30[0xd]; 1173 u8 max_chunk_size[0x3]; 1174 struct mlx5_ifc_calc_op calc0; 1175 struct mlx5_ifc_calc_op calc1; 1176 struct mlx5_ifc_calc_op calc2; 1177 struct mlx5_ifc_calc_op calc3; 1178 1179 u8 reserved_at_c0[0x720]; 1180 }; 1181 1182 struct mlx5_ifc_tls_cap_bits { 1183 u8 tls_1_2_aes_gcm_128[0x1]; 1184 u8 tls_1_3_aes_gcm_128[0x1]; 1185 u8 tls_1_2_aes_gcm_256[0x1]; 1186 u8 tls_1_3_aes_gcm_256[0x1]; 1187 u8 reserved_at_4[0x1c]; 1188 1189 u8 reserved_at_20[0x7e0]; 1190 }; 1191 1192 struct mlx5_ifc_ipsec_cap_bits { 1193 u8 ipsec_full_offload[0x1]; 1194 u8 ipsec_crypto_offload[0x1]; 1195 u8 ipsec_esn[0x1]; 1196 u8 ipsec_crypto_esp_aes_gcm_256_encrypt[0x1]; 1197 u8 ipsec_crypto_esp_aes_gcm_128_encrypt[0x1]; 1198 u8 ipsec_crypto_esp_aes_gcm_256_decrypt[0x1]; 1199 u8 ipsec_crypto_esp_aes_gcm_128_decrypt[0x1]; 1200 u8 reserved_at_7[0x4]; 1201 u8 log_max_ipsec_offload[0x5]; 1202 u8 reserved_at_10[0x10]; 1203 1204 u8 min_log_ipsec_full_replay_window[0x8]; 1205 u8 max_log_ipsec_full_replay_window[0x8]; 1206 u8 reserved_at_30[0x7d0]; 1207 }; 1208 1209 enum { 1210 MLX5_WQ_TYPE_LINKED_LIST = 0x0, 1211 MLX5_WQ_TYPE_CYCLIC = 0x1, 1212 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2, 1213 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3, 1214 }; 1215 1216 enum { 1217 MLX5_WQ_END_PAD_MODE_NONE = 0x0, 1218 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1, 1219 }; 1220 1221 enum { 1222 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0, 1223 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1, 1224 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2, 1225 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3, 1226 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4, 1227 }; 1228 1229 enum { 1230 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0, 1231 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1, 1232 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2, 1233 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3, 1234 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4, 1235 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5, 1236 }; 1237 1238 enum { 1239 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0, 1240 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1, 1241 }; 1242 1243 enum { 1244 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0, 1245 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1, 1246 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3, 1247 }; 1248 1249 enum { 1250 MLX5_CAP_PORT_TYPE_IB = 0x0, 1251 MLX5_CAP_PORT_TYPE_ETH = 0x1, 1252 }; 1253 1254 enum { 1255 MLX5_CAP_UMR_FENCE_STRONG = 0x0, 1256 MLX5_CAP_UMR_FENCE_SMALL = 0x1, 1257 MLX5_CAP_UMR_FENCE_NONE = 0x2, 1258 }; 1259 1260 enum { 1261 MLX5_FLEX_PARSER_GENEVE_ENABLED = 1 << 3, 1262 MLX5_FLEX_PARSER_MPLS_OVER_GRE_ENABLED = 1 << 4, 1263 mlx5_FLEX_PARSER_MPLS_OVER_UDP_ENABLED = 1 << 5, 1264 MLX5_FLEX_PARSER_VXLAN_GPE_ENABLED = 1 << 7, 1265 MLX5_FLEX_PARSER_ICMP_V4_ENABLED = 1 << 8, 1266 MLX5_FLEX_PARSER_ICMP_V6_ENABLED = 1 << 9, 1267 MLX5_FLEX_PARSER_GENEVE_TLV_OPTION_0_ENABLED = 1 << 10, 1268 MLX5_FLEX_PARSER_GTPU_ENABLED = 1 << 11, 1269 MLX5_FLEX_PARSER_GTPU_DW_2_ENABLED = 1 << 16, 1270 MLX5_FLEX_PARSER_GTPU_FIRST_EXT_DW_0_ENABLED = 1 << 17, 1271 MLX5_FLEX_PARSER_GTPU_DW_0_ENABLED = 1 << 18, 1272 MLX5_FLEX_PARSER_GTPU_TEID_ENABLED = 1 << 19, 1273 }; 1274 1275 enum { 1276 MLX5_UCTX_CAP_RAW_TX = 1UL << 0, 1277 MLX5_UCTX_CAP_INTERNAL_DEV_RES = 1UL << 1, 1278 }; 1279 1280 #define MLX5_FC_BULK_SIZE_FACTOR 128 1281 1282 enum mlx5_fc_bulk_alloc_bitmask { 1283 MLX5_FC_BULK_128 = (1 << 0), 1284 MLX5_FC_BULK_256 = (1 << 1), 1285 MLX5_FC_BULK_512 = (1 << 2), 1286 MLX5_FC_BULK_1024 = (1 << 3), 1287 MLX5_FC_BULK_2048 = (1 << 4), 1288 MLX5_FC_BULK_4096 = (1 << 5), 1289 MLX5_FC_BULK_8192 = (1 << 6), 1290 MLX5_FC_BULK_16384 = (1 << 7), 1291 }; 1292 1293 #define MLX5_FC_BULK_NUM_FCS(fc_enum) (MLX5_FC_BULK_SIZE_FACTOR * (fc_enum)) 1294 1295 #define MLX5_FT_MAX_MULTIPATH_LEVEL 63 1296 1297 enum { 1298 MLX5_STEERING_FORMAT_CONNECTX_5 = 0, 1299 MLX5_STEERING_FORMAT_CONNECTX_6DX = 1, 1300 }; 1301 1302 enum { 1303 MLX5_SQ_TIMESTAMP_FORMAT_CAP_FREE_RUNNING = 0x0, 1304 MLX5_SQ_TIMESTAMP_FORMAT_CAP_REAL_TIME = 0x1, 1305 MLX5_SQ_TIMESTAMP_FORMAT_CAP_FREE_RUNNING_AND_REAL_TIME = 0x2, 1306 }; 1307 1308 enum { 1309 MLX5_RQ_TIMESTAMP_FORMAT_CAP_FREE_RUNNING = 0x0, 1310 MLX5_RQ_TIMESTAMP_FORMAT_CAP_REAL_TIME = 0x1, 1311 MLX5_RQ_TIMESTAMP_FORMAT_CAP_FREE_RUNNING_AND_REAL_TIME = 0x2, 1312 }; 1313 1314 struct mlx5_ifc_cmd_hca_cap_bits { 1315 u8 reserved_at_0[0x1f]; 1316 u8 vhca_resource_manager[0x1]; 1317 1318 u8 hca_cap_2[0x1]; 1319 u8 reserved_at_21[0x2]; 1320 u8 event_on_vhca_state_teardown_request[0x1]; 1321 u8 event_on_vhca_state_in_use[0x1]; 1322 u8 event_on_vhca_state_active[0x1]; 1323 u8 event_on_vhca_state_allocated[0x1]; 1324 u8 event_on_vhca_state_invalid[0x1]; 1325 u8 reserved_at_28[0x8]; 1326 u8 vhca_id[0x10]; 1327 1328 u8 reserved_at_40[0x40]; 1329 1330 u8 log_max_srq_sz[0x8]; 1331 u8 log_max_qp_sz[0x8]; 1332 u8 event_cap[0x1]; 1333 u8 reserved_at_91[0x2]; 1334 u8 isolate_vl_tc_new[0x1]; 1335 u8 reserved_at_94[0x4]; 1336 u8 prio_tag_required[0x1]; 1337 u8 reserved_at_99[0x2]; 1338 u8 log_max_qp[0x5]; 1339 1340 u8 reserved_at_a0[0x3]; 1341 u8 ece_support[0x1]; 1342 u8 reserved_at_a4[0x5]; 1343 u8 reg_c_preserve[0x1]; 1344 u8 reserved_at_aa[0x1]; 1345 u8 log_max_srq[0x5]; 1346 u8 reserved_at_b0[0x1]; 1347 u8 uplink_follow[0x1]; 1348 u8 ts_cqe_to_dest_cqn[0x1]; 1349 u8 reserved_at_b3[0xd]; 1350 1351 u8 max_sgl_for_optimized_performance[0x8]; 1352 u8 log_max_cq_sz[0x8]; 1353 u8 relaxed_ordering_write_umr[0x1]; 1354 u8 relaxed_ordering_read_umr[0x1]; 1355 u8 reserved_at_d2[0x7]; 1356 u8 virtio_net_device_emualtion_manager[0x1]; 1357 u8 virtio_blk_device_emualtion_manager[0x1]; 1358 u8 log_max_cq[0x5]; 1359 1360 u8 log_max_eq_sz[0x8]; 1361 u8 relaxed_ordering_write[0x1]; 1362 u8 relaxed_ordering_read[0x1]; 1363 u8 log_max_mkey[0x6]; 1364 u8 reserved_at_f0[0x8]; 1365 u8 dump_fill_mkey[0x1]; 1366 u8 reserved_at_f9[0x2]; 1367 u8 fast_teardown[0x1]; 1368 u8 log_max_eq[0x4]; 1369 1370 u8 max_indirection[0x8]; 1371 u8 fixed_buffer_size[0x1]; 1372 u8 log_max_mrw_sz[0x7]; 1373 u8 force_teardown[0x1]; 1374 u8 reserved_at_111[0x1]; 1375 u8 log_max_bsf_list_size[0x6]; 1376 u8 umr_extended_translation_offset[0x1]; 1377 u8 null_mkey[0x1]; 1378 u8 log_max_klm_list_size[0x6]; 1379 1380 u8 reserved_at_120[0xa]; 1381 u8 log_max_ra_req_dc[0x6]; 1382 u8 reserved_at_130[0xa]; 1383 u8 log_max_ra_res_dc[0x6]; 1384 1385 u8 reserved_at_140[0x6]; 1386 u8 release_all_pages[0x1]; 1387 u8 reserved_at_147[0x2]; 1388 u8 roce_accl[0x1]; 1389 u8 log_max_ra_req_qp[0x6]; 1390 u8 reserved_at_150[0xa]; 1391 u8 log_max_ra_res_qp[0x6]; 1392 1393 u8 end_pad[0x1]; 1394 u8 cc_query_allowed[0x1]; 1395 u8 cc_modify_allowed[0x1]; 1396 u8 start_pad[0x1]; 1397 u8 cache_line_128byte[0x1]; 1398 u8 reserved_at_165[0x4]; 1399 u8 rts2rts_qp_counters_set_id[0x1]; 1400 u8 reserved_at_16a[0x2]; 1401 u8 vnic_env_int_rq_oob[0x1]; 1402 u8 sbcam_reg[0x1]; 1403 u8 reserved_at_16e[0x1]; 1404 u8 qcam_reg[0x1]; 1405 u8 gid_table_size[0x10]; 1406 1407 u8 out_of_seq_cnt[0x1]; 1408 u8 vport_counters[0x1]; 1409 u8 retransmission_q_counters[0x1]; 1410 u8 debug[0x1]; 1411 u8 modify_rq_counter_set_id[0x1]; 1412 u8 rq_delay_drop[0x1]; 1413 u8 max_qp_cnt[0xa]; 1414 u8 pkey_table_size[0x10]; 1415 1416 u8 vport_group_manager[0x1]; 1417 u8 vhca_group_manager[0x1]; 1418 u8 ib_virt[0x1]; 1419 u8 eth_virt[0x1]; 1420 u8 vnic_env_queue_counters[0x1]; 1421 u8 ets[0x1]; 1422 u8 nic_flow_table[0x1]; 1423 u8 eswitch_manager[0x1]; 1424 u8 device_memory[0x1]; 1425 u8 mcam_reg[0x1]; 1426 u8 pcam_reg[0x1]; 1427 u8 local_ca_ack_delay[0x5]; 1428 u8 port_module_event[0x1]; 1429 u8 enhanced_error_q_counters[0x1]; 1430 u8 ports_check[0x1]; 1431 u8 reserved_at_1b3[0x1]; 1432 u8 disable_link_up[0x1]; 1433 u8 beacon_led[0x1]; 1434 u8 port_type[0x2]; 1435 u8 num_ports[0x8]; 1436 1437 u8 reserved_at_1c0[0x1]; 1438 u8 pps[0x1]; 1439 u8 pps_modify[0x1]; 1440 u8 log_max_msg[0x5]; 1441 u8 reserved_at_1c8[0x4]; 1442 u8 max_tc[0x4]; 1443 u8 temp_warn_event[0x1]; 1444 u8 dcbx[0x1]; 1445 u8 general_notification_event[0x1]; 1446 u8 reserved_at_1d3[0x2]; 1447 u8 fpga[0x1]; 1448 u8 rol_s[0x1]; 1449 u8 rol_g[0x1]; 1450 u8 reserved_at_1d8[0x1]; 1451 u8 wol_s[0x1]; 1452 u8 wol_g[0x1]; 1453 u8 wol_a[0x1]; 1454 u8 wol_b[0x1]; 1455 u8 wol_m[0x1]; 1456 u8 wol_u[0x1]; 1457 u8 wol_p[0x1]; 1458 1459 u8 stat_rate_support[0x10]; 1460 u8 reserved_at_1f0[0x1]; 1461 u8 pci_sync_for_fw_update_event[0x1]; 1462 u8 reserved_at_1f2[0x6]; 1463 u8 init2_lag_tx_port_affinity[0x1]; 1464 u8 reserved_at_1fa[0x3]; 1465 u8 cqe_version[0x4]; 1466 1467 u8 compact_address_vector[0x1]; 1468 u8 striding_rq[0x1]; 1469 u8 reserved_at_202[0x1]; 1470 u8 ipoib_enhanced_offloads[0x1]; 1471 u8 ipoib_basic_offloads[0x1]; 1472 u8 reserved_at_205[0x1]; 1473 u8 repeated_block_disabled[0x1]; 1474 u8 umr_modify_entity_size_disabled[0x1]; 1475 u8 umr_modify_atomic_disabled[0x1]; 1476 u8 umr_indirect_mkey_disabled[0x1]; 1477 u8 umr_fence[0x2]; 1478 u8 dc_req_scat_data_cqe[0x1]; 1479 u8 reserved_at_20d[0x2]; 1480 u8 drain_sigerr[0x1]; 1481 u8 cmdif_checksum[0x2]; 1482 u8 sigerr_cqe[0x1]; 1483 u8 reserved_at_213[0x1]; 1484 u8 wq_signature[0x1]; 1485 u8 sctr_data_cqe[0x1]; 1486 u8 reserved_at_216[0x1]; 1487 u8 sho[0x1]; 1488 u8 tph[0x1]; 1489 u8 rf[0x1]; 1490 u8 dct[0x1]; 1491 u8 qos[0x1]; 1492 u8 eth_net_offloads[0x1]; 1493 u8 roce[0x1]; 1494 u8 atomic[0x1]; 1495 u8 reserved_at_21f[0x1]; 1496 1497 u8 cq_oi[0x1]; 1498 u8 cq_resize[0x1]; 1499 u8 cq_moderation[0x1]; 1500 u8 reserved_at_223[0x3]; 1501 u8 cq_eq_remap[0x1]; 1502 u8 pg[0x1]; 1503 u8 block_lb_mc[0x1]; 1504 u8 reserved_at_229[0x1]; 1505 u8 scqe_break_moderation[0x1]; 1506 u8 cq_period_start_from_cqe[0x1]; 1507 u8 cd[0x1]; 1508 u8 reserved_at_22d[0x1]; 1509 u8 apm[0x1]; 1510 u8 vector_calc[0x1]; 1511 u8 umr_ptr_rlky[0x1]; 1512 u8 imaicl[0x1]; 1513 u8 qp_packet_based[0x1]; 1514 u8 reserved_at_233[0x3]; 1515 u8 qkv[0x1]; 1516 u8 pkv[0x1]; 1517 u8 set_deth_sqpn[0x1]; 1518 u8 reserved_at_239[0x3]; 1519 u8 xrc[0x1]; 1520 u8 ud[0x1]; 1521 u8 uc[0x1]; 1522 u8 rc[0x1]; 1523 1524 u8 uar_4k[0x1]; 1525 u8 reserved_at_241[0x9]; 1526 u8 uar_sz[0x6]; 1527 u8 reserved_at_250[0x8]; 1528 u8 log_pg_sz[0x8]; 1529 1530 u8 bf[0x1]; 1531 u8 driver_version[0x1]; 1532 u8 pad_tx_eth_packet[0x1]; 1533 u8 reserved_at_263[0x3]; 1534 u8 mkey_by_name[0x1]; 1535 u8 reserved_at_267[0x4]; 1536 1537 u8 log_bf_reg_size[0x5]; 1538 1539 u8 reserved_at_270[0x6]; 1540 u8 lag_dct[0x2]; 1541 u8 lag_tx_port_affinity[0x1]; 1542 u8 lag_native_fdb_selection[0x1]; 1543 u8 reserved_at_27a[0x1]; 1544 u8 lag_master[0x1]; 1545 u8 num_lag_ports[0x4]; 1546 1547 u8 reserved_at_280[0x10]; 1548 u8 max_wqe_sz_sq[0x10]; 1549 1550 u8 reserved_at_2a0[0x10]; 1551 u8 max_wqe_sz_rq[0x10]; 1552 1553 u8 max_flow_counter_31_16[0x10]; 1554 u8 max_wqe_sz_sq_dc[0x10]; 1555 1556 u8 reserved_at_2e0[0x7]; 1557 u8 max_qp_mcg[0x19]; 1558 1559 u8 reserved_at_300[0x10]; 1560 u8 flow_counter_bulk_alloc[0x8]; 1561 u8 log_max_mcg[0x8]; 1562 1563 u8 reserved_at_320[0x3]; 1564 u8 log_max_transport_domain[0x5]; 1565 u8 reserved_at_328[0x3]; 1566 u8 log_max_pd[0x5]; 1567 u8 reserved_at_330[0xb]; 1568 u8 log_max_xrcd[0x5]; 1569 1570 u8 nic_receive_steering_discard[0x1]; 1571 u8 receive_discard_vport_down[0x1]; 1572 u8 transmit_discard_vport_down[0x1]; 1573 u8 reserved_at_343[0x5]; 1574 u8 log_max_flow_counter_bulk[0x8]; 1575 u8 max_flow_counter_15_0[0x10]; 1576 1577 1578 u8 reserved_at_360[0x3]; 1579 u8 log_max_rq[0x5]; 1580 u8 reserved_at_368[0x3]; 1581 u8 log_max_sq[0x5]; 1582 u8 reserved_at_370[0x3]; 1583 u8 log_max_tir[0x5]; 1584 u8 reserved_at_378[0x3]; 1585 u8 log_max_tis[0x5]; 1586 1587 u8 basic_cyclic_rcv_wqe[0x1]; 1588 u8 reserved_at_381[0x2]; 1589 u8 log_max_rmp[0x5]; 1590 u8 reserved_at_388[0x3]; 1591 u8 log_max_rqt[0x5]; 1592 u8 reserved_at_390[0x3]; 1593 u8 log_max_rqt_size[0x5]; 1594 u8 reserved_at_398[0x3]; 1595 u8 log_max_tis_per_sq[0x5]; 1596 1597 u8 ext_stride_num_range[0x1]; 1598 u8 reserved_at_3a1[0x2]; 1599 u8 log_max_stride_sz_rq[0x5]; 1600 u8 reserved_at_3a8[0x3]; 1601 u8 log_min_stride_sz_rq[0x5]; 1602 u8 reserved_at_3b0[0x3]; 1603 u8 log_max_stride_sz_sq[0x5]; 1604 u8 reserved_at_3b8[0x3]; 1605 u8 log_min_stride_sz_sq[0x5]; 1606 1607 u8 hairpin[0x1]; 1608 u8 reserved_at_3c1[0x2]; 1609 u8 log_max_hairpin_queues[0x5]; 1610 u8 reserved_at_3c8[0x3]; 1611 u8 log_max_hairpin_wq_data_sz[0x5]; 1612 u8 reserved_at_3d0[0x3]; 1613 u8 log_max_hairpin_num_packets[0x5]; 1614 u8 reserved_at_3d8[0x3]; 1615 u8 log_max_wq_sz[0x5]; 1616 1617 u8 nic_vport_change_event[0x1]; 1618 u8 disable_local_lb_uc[0x1]; 1619 u8 disable_local_lb_mc[0x1]; 1620 u8 log_min_hairpin_wq_data_sz[0x5]; 1621 u8 reserved_at_3e8[0x2]; 1622 u8 vhca_state[0x1]; 1623 u8 log_max_vlan_list[0x5]; 1624 u8 reserved_at_3f0[0x3]; 1625 u8 log_max_current_mc_list[0x5]; 1626 u8 reserved_at_3f8[0x3]; 1627 u8 log_max_current_uc_list[0x5]; 1628 1629 u8 general_obj_types[0x40]; 1630 1631 u8 sq_ts_format[0x2]; 1632 u8 rq_ts_format[0x2]; 1633 u8 steering_format_version[0x4]; 1634 u8 create_qp_start_hint[0x18]; 1635 1636 u8 reserved_at_460[0x3]; 1637 u8 log_max_uctx[0x5]; 1638 u8 reserved_at_468[0x2]; 1639 u8 ipsec_offload[0x1]; 1640 u8 log_max_umem[0x5]; 1641 u8 max_num_eqs[0x10]; 1642 1643 u8 reserved_at_480[0x1]; 1644 u8 tls_tx[0x1]; 1645 u8 tls_rx[0x1]; 1646 u8 log_max_l2_table[0x5]; 1647 u8 reserved_at_488[0x8]; 1648 u8 log_uar_page_sz[0x10]; 1649 1650 u8 reserved_at_4a0[0x20]; 1651 u8 device_frequency_mhz[0x20]; 1652 u8 device_frequency_khz[0x20]; 1653 1654 u8 reserved_at_500[0x20]; 1655 u8 num_of_uars_per_page[0x20]; 1656 1657 u8 flex_parser_protocols[0x20]; 1658 1659 u8 max_geneve_tlv_options[0x8]; 1660 u8 reserved_at_568[0x3]; 1661 u8 max_geneve_tlv_option_data_len[0x5]; 1662 u8 reserved_at_570[0x10]; 1663 1664 u8 reserved_at_580[0x33]; 1665 u8 log_max_dek[0x5]; 1666 u8 reserved_at_5b8[0x4]; 1667 u8 mini_cqe_resp_stride_index[0x1]; 1668 u8 cqe_128_always[0x1]; 1669 u8 cqe_compression_128[0x1]; 1670 u8 cqe_compression[0x1]; 1671 1672 u8 cqe_compression_timeout[0x10]; 1673 u8 cqe_compression_max_num[0x10]; 1674 1675 u8 reserved_at_5e0[0x8]; 1676 u8 flex_parser_id_gtpu_dw_0[0x4]; 1677 u8 reserved_at_5ec[0x4]; 1678 u8 tag_matching[0x1]; 1679 u8 rndv_offload_rc[0x1]; 1680 u8 rndv_offload_dc[0x1]; 1681 u8 log_tag_matching_list_sz[0x5]; 1682 u8 reserved_at_5f8[0x3]; 1683 u8 log_max_xrq[0x5]; 1684 1685 u8 affiliate_nic_vport_criteria[0x8]; 1686 u8 native_port_num[0x8]; 1687 u8 num_vhca_ports[0x8]; 1688 u8 flex_parser_id_gtpu_teid[0x4]; 1689 u8 reserved_at_61c[0x2]; 1690 u8 sw_owner_id[0x1]; 1691 u8 reserved_at_61f[0x1]; 1692 1693 u8 max_num_of_monitor_counters[0x10]; 1694 u8 num_ppcnt_monitor_counters[0x10]; 1695 1696 u8 max_num_sf[0x10]; 1697 u8 num_q_monitor_counters[0x10]; 1698 1699 u8 reserved_at_660[0x20]; 1700 1701 u8 sf[0x1]; 1702 u8 sf_set_partition[0x1]; 1703 u8 reserved_at_682[0x1]; 1704 u8 log_max_sf[0x5]; 1705 u8 apu[0x1]; 1706 u8 reserved_at_689[0x7]; 1707 u8 log_min_sf_size[0x8]; 1708 u8 max_num_sf_partitions[0x8]; 1709 1710 u8 uctx_cap[0x20]; 1711 1712 u8 reserved_at_6c0[0x4]; 1713 u8 flex_parser_id_geneve_tlv_option_0[0x4]; 1714 u8 flex_parser_id_icmp_dw1[0x4]; 1715 u8 flex_parser_id_icmp_dw0[0x4]; 1716 u8 flex_parser_id_icmpv6_dw1[0x4]; 1717 u8 flex_parser_id_icmpv6_dw0[0x4]; 1718 u8 flex_parser_id_outer_first_mpls_over_gre[0x4]; 1719 u8 flex_parser_id_outer_first_mpls_over_udp_label[0x4]; 1720 1721 u8 reserved_at_6e0[0x10]; 1722 u8 sf_base_id[0x10]; 1723 1724 u8 flex_parser_id_gtpu_dw_2[0x4]; 1725 u8 flex_parser_id_gtpu_first_ext_dw_0[0x4]; 1726 u8 num_total_dynamic_vf_msix[0x18]; 1727 u8 reserved_at_720[0x14]; 1728 u8 dynamic_msix_table_size[0xc]; 1729 u8 reserved_at_740[0xc]; 1730 u8 min_dynamic_vf_msix_table_size[0x4]; 1731 u8 reserved_at_750[0x4]; 1732 u8 max_dynamic_vf_msix_table_size[0xc]; 1733 1734 u8 reserved_at_760[0x20]; 1735 u8 vhca_tunnel_commands[0x40]; 1736 u8 reserved_at_7c0[0x40]; 1737 }; 1738 1739 struct mlx5_ifc_cmd_hca_cap_2_bits { 1740 u8 reserved_at_0[0xa0]; 1741 1742 u8 max_reformat_insert_size[0x8]; 1743 u8 max_reformat_insert_offset[0x8]; 1744 u8 max_reformat_remove_size[0x8]; 1745 u8 max_reformat_remove_offset[0x8]; 1746 1747 u8 reserved_at_c0[0x740]; 1748 }; 1749 1750 enum mlx5_flow_destination_type { 1751 MLX5_FLOW_DESTINATION_TYPE_VPORT = 0x0, 1752 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1, 1753 MLX5_FLOW_DESTINATION_TYPE_TIR = 0x2, 1754 MLX5_FLOW_DESTINATION_TYPE_FLOW_SAMPLER = 0x6, 1755 1756 MLX5_FLOW_DESTINATION_TYPE_PORT = 0x99, 1757 MLX5_FLOW_DESTINATION_TYPE_COUNTER = 0x100, 1758 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE_NUM = 0x101, 1759 }; 1760 1761 enum mlx5_flow_table_miss_action { 1762 MLX5_FLOW_TABLE_MISS_ACTION_DEF, 1763 MLX5_FLOW_TABLE_MISS_ACTION_FWD, 1764 MLX5_FLOW_TABLE_MISS_ACTION_SWITCH_DOMAIN, 1765 }; 1766 1767 struct mlx5_ifc_dest_format_struct_bits { 1768 u8 destination_type[0x8]; 1769 u8 destination_id[0x18]; 1770 1771 u8 destination_eswitch_owner_vhca_id_valid[0x1]; 1772 u8 packet_reformat[0x1]; 1773 u8 reserved_at_22[0xe]; 1774 u8 destination_eswitch_owner_vhca_id[0x10]; 1775 }; 1776 1777 struct mlx5_ifc_flow_counter_list_bits { 1778 u8 flow_counter_id[0x20]; 1779 1780 u8 reserved_at_20[0x20]; 1781 }; 1782 1783 struct mlx5_ifc_extended_dest_format_bits { 1784 struct mlx5_ifc_dest_format_struct_bits destination_entry; 1785 1786 u8 packet_reformat_id[0x20]; 1787 1788 u8 reserved_at_60[0x20]; 1789 }; 1790 1791 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits { 1792 struct mlx5_ifc_extended_dest_format_bits extended_dest_format; 1793 struct mlx5_ifc_flow_counter_list_bits flow_counter_list; 1794 }; 1795 1796 struct mlx5_ifc_fte_match_param_bits { 1797 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers; 1798 1799 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters; 1800 1801 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers; 1802 1803 struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2; 1804 1805 struct mlx5_ifc_fte_match_set_misc3_bits misc_parameters_3; 1806 1807 struct mlx5_ifc_fte_match_set_misc4_bits misc_parameters_4; 1808 1809 u8 reserved_at_c00[0x400]; 1810 }; 1811 1812 enum { 1813 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0, 1814 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1, 1815 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2, 1816 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3, 1817 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4, 1818 }; 1819 1820 struct mlx5_ifc_rx_hash_field_select_bits { 1821 u8 l3_prot_type[0x1]; 1822 u8 l4_prot_type[0x1]; 1823 u8 selected_fields[0x1e]; 1824 }; 1825 1826 enum { 1827 MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0, 1828 MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1, 1829 }; 1830 1831 enum { 1832 MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0, 1833 MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1, 1834 }; 1835 1836 struct mlx5_ifc_wq_bits { 1837 u8 wq_type[0x4]; 1838 u8 wq_signature[0x1]; 1839 u8 end_padding_mode[0x2]; 1840 u8 cd_slave[0x1]; 1841 u8 reserved_at_8[0x18]; 1842 1843 u8 hds_skip_first_sge[0x1]; 1844 u8 log2_hds_buf_size[0x3]; 1845 u8 reserved_at_24[0x7]; 1846 u8 page_offset[0x5]; 1847 u8 lwm[0x10]; 1848 1849 u8 reserved_at_40[0x8]; 1850 u8 pd[0x18]; 1851 1852 u8 reserved_at_60[0x8]; 1853 u8 uar_page[0x18]; 1854 1855 u8 dbr_addr[0x40]; 1856 1857 u8 hw_counter[0x20]; 1858 1859 u8 sw_counter[0x20]; 1860 1861 u8 reserved_at_100[0xc]; 1862 u8 log_wq_stride[0x4]; 1863 u8 reserved_at_110[0x3]; 1864 u8 log_wq_pg_sz[0x5]; 1865 u8 reserved_at_118[0x3]; 1866 u8 log_wq_sz[0x5]; 1867 1868 u8 dbr_umem_valid[0x1]; 1869 u8 wq_umem_valid[0x1]; 1870 u8 reserved_at_122[0x1]; 1871 u8 log_hairpin_num_packets[0x5]; 1872 u8 reserved_at_128[0x3]; 1873 u8 log_hairpin_data_sz[0x5]; 1874 1875 u8 reserved_at_130[0x4]; 1876 u8 log_wqe_num_of_strides[0x4]; 1877 u8 two_byte_shift_en[0x1]; 1878 u8 reserved_at_139[0x4]; 1879 u8 log_wqe_stride_size[0x3]; 1880 1881 u8 reserved_at_140[0x4c0]; 1882 1883 struct mlx5_ifc_cmd_pas_bits pas[]; 1884 }; 1885 1886 struct mlx5_ifc_rq_num_bits { 1887 u8 reserved_at_0[0x8]; 1888 u8 rq_num[0x18]; 1889 }; 1890 1891 struct mlx5_ifc_mac_address_layout_bits { 1892 u8 reserved_at_0[0x10]; 1893 u8 mac_addr_47_32[0x10]; 1894 1895 u8 mac_addr_31_0[0x20]; 1896 }; 1897 1898 struct mlx5_ifc_vlan_layout_bits { 1899 u8 reserved_at_0[0x14]; 1900 u8 vlan[0x0c]; 1901 1902 u8 reserved_at_20[0x20]; 1903 }; 1904 1905 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits { 1906 u8 reserved_at_0[0xa0]; 1907 1908 u8 min_time_between_cnps[0x20]; 1909 1910 u8 reserved_at_c0[0x12]; 1911 u8 cnp_dscp[0x6]; 1912 u8 reserved_at_d8[0x4]; 1913 u8 cnp_prio_mode[0x1]; 1914 u8 cnp_802p_prio[0x3]; 1915 1916 u8 reserved_at_e0[0x720]; 1917 }; 1918 1919 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits { 1920 u8 reserved_at_0[0x60]; 1921 1922 u8 reserved_at_60[0x4]; 1923 u8 clamp_tgt_rate[0x1]; 1924 u8 reserved_at_65[0x3]; 1925 u8 clamp_tgt_rate_after_time_inc[0x1]; 1926 u8 reserved_at_69[0x17]; 1927 1928 u8 reserved_at_80[0x20]; 1929 1930 u8 rpg_time_reset[0x20]; 1931 1932 u8 rpg_byte_reset[0x20]; 1933 1934 u8 rpg_threshold[0x20]; 1935 1936 u8 rpg_max_rate[0x20]; 1937 1938 u8 rpg_ai_rate[0x20]; 1939 1940 u8 rpg_hai_rate[0x20]; 1941 1942 u8 rpg_gd[0x20]; 1943 1944 u8 rpg_min_dec_fac[0x20]; 1945 1946 u8 rpg_min_rate[0x20]; 1947 1948 u8 reserved_at_1c0[0xe0]; 1949 1950 u8 rate_to_set_on_first_cnp[0x20]; 1951 1952 u8 dce_tcp_g[0x20]; 1953 1954 u8 dce_tcp_rtt[0x20]; 1955 1956 u8 rate_reduce_monitor_period[0x20]; 1957 1958 u8 reserved_at_320[0x20]; 1959 1960 u8 initial_alpha_value[0x20]; 1961 1962 u8 reserved_at_360[0x4a0]; 1963 }; 1964 1965 struct mlx5_ifc_cong_control_802_1qau_rp_bits { 1966 u8 reserved_at_0[0x80]; 1967 1968 u8 rppp_max_rps[0x20]; 1969 1970 u8 rpg_time_reset[0x20]; 1971 1972 u8 rpg_byte_reset[0x20]; 1973 1974 u8 rpg_threshold[0x20]; 1975 1976 u8 rpg_max_rate[0x20]; 1977 1978 u8 rpg_ai_rate[0x20]; 1979 1980 u8 rpg_hai_rate[0x20]; 1981 1982 u8 rpg_gd[0x20]; 1983 1984 u8 rpg_min_dec_fac[0x20]; 1985 1986 u8 rpg_min_rate[0x20]; 1987 1988 u8 reserved_at_1c0[0x640]; 1989 }; 1990 1991 enum { 1992 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1, 1993 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2, 1994 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4, 1995 }; 1996 1997 struct mlx5_ifc_resize_field_select_bits { 1998 u8 resize_field_select[0x20]; 1999 }; 2000 2001 struct mlx5_ifc_resource_dump_bits { 2002 u8 more_dump[0x1]; 2003 u8 inline_dump[0x1]; 2004 u8 reserved_at_2[0xa]; 2005 u8 seq_num[0x4]; 2006 u8 segment_type[0x10]; 2007 2008 u8 reserved_at_20[0x10]; 2009 u8 vhca_id[0x10]; 2010 2011 u8 index1[0x20]; 2012 2013 u8 index2[0x20]; 2014 2015 u8 num_of_obj1[0x10]; 2016 u8 num_of_obj2[0x10]; 2017 2018 u8 reserved_at_a0[0x20]; 2019 2020 u8 device_opaque[0x40]; 2021 2022 u8 mkey[0x20]; 2023 2024 u8 size[0x20]; 2025 2026 u8 address[0x40]; 2027 2028 u8 inline_data[52][0x20]; 2029 }; 2030 2031 struct mlx5_ifc_resource_dump_menu_record_bits { 2032 u8 reserved_at_0[0x4]; 2033 u8 num_of_obj2_supports_active[0x1]; 2034 u8 num_of_obj2_supports_all[0x1]; 2035 u8 must_have_num_of_obj2[0x1]; 2036 u8 support_num_of_obj2[0x1]; 2037 u8 num_of_obj1_supports_active[0x1]; 2038 u8 num_of_obj1_supports_all[0x1]; 2039 u8 must_have_num_of_obj1[0x1]; 2040 u8 support_num_of_obj1[0x1]; 2041 u8 must_have_index2[0x1]; 2042 u8 support_index2[0x1]; 2043 u8 must_have_index1[0x1]; 2044 u8 support_index1[0x1]; 2045 u8 segment_type[0x10]; 2046 2047 u8 segment_name[4][0x20]; 2048 2049 u8 index1_name[4][0x20]; 2050 2051 u8 index2_name[4][0x20]; 2052 }; 2053 2054 struct mlx5_ifc_resource_dump_segment_header_bits { 2055 u8 length_dw[0x10]; 2056 u8 segment_type[0x10]; 2057 }; 2058 2059 struct mlx5_ifc_resource_dump_command_segment_bits { 2060 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2061 2062 u8 segment_called[0x10]; 2063 u8 vhca_id[0x10]; 2064 2065 u8 index1[0x20]; 2066 2067 u8 index2[0x20]; 2068 2069 u8 num_of_obj1[0x10]; 2070 u8 num_of_obj2[0x10]; 2071 }; 2072 2073 struct mlx5_ifc_resource_dump_error_segment_bits { 2074 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2075 2076 u8 reserved_at_20[0x10]; 2077 u8 syndrome_id[0x10]; 2078 2079 u8 reserved_at_40[0x40]; 2080 2081 u8 error[8][0x20]; 2082 }; 2083 2084 struct mlx5_ifc_resource_dump_info_segment_bits { 2085 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2086 2087 u8 reserved_at_20[0x18]; 2088 u8 dump_version[0x8]; 2089 2090 u8 hw_version[0x20]; 2091 2092 u8 fw_version[0x20]; 2093 }; 2094 2095 struct mlx5_ifc_resource_dump_menu_segment_bits { 2096 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2097 2098 u8 reserved_at_20[0x10]; 2099 u8 num_of_records[0x10]; 2100 2101 struct mlx5_ifc_resource_dump_menu_record_bits record[]; 2102 }; 2103 2104 struct mlx5_ifc_resource_dump_resource_segment_bits { 2105 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2106 2107 u8 reserved_at_20[0x20]; 2108 2109 u8 index1[0x20]; 2110 2111 u8 index2[0x20]; 2112 2113 u8 payload[][0x20]; 2114 }; 2115 2116 struct mlx5_ifc_resource_dump_terminate_segment_bits { 2117 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2118 }; 2119 2120 struct mlx5_ifc_menu_resource_dump_response_bits { 2121 struct mlx5_ifc_resource_dump_info_segment_bits info; 2122 struct mlx5_ifc_resource_dump_command_segment_bits cmd; 2123 struct mlx5_ifc_resource_dump_menu_segment_bits menu; 2124 struct mlx5_ifc_resource_dump_terminate_segment_bits terminate; 2125 }; 2126 2127 enum { 2128 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1, 2129 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2, 2130 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4, 2131 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8, 2132 }; 2133 2134 struct mlx5_ifc_modify_field_select_bits { 2135 u8 modify_field_select[0x20]; 2136 }; 2137 2138 struct mlx5_ifc_field_select_r_roce_np_bits { 2139 u8 field_select_r_roce_np[0x20]; 2140 }; 2141 2142 struct mlx5_ifc_field_select_r_roce_rp_bits { 2143 u8 field_select_r_roce_rp[0x20]; 2144 }; 2145 2146 enum { 2147 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4, 2148 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8, 2149 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10, 2150 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20, 2151 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40, 2152 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80, 2153 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100, 2154 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200, 2155 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400, 2156 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800, 2157 }; 2158 2159 struct mlx5_ifc_field_select_802_1qau_rp_bits { 2160 u8 field_select_8021qaurp[0x20]; 2161 }; 2162 2163 struct mlx5_ifc_phys_layer_cntrs_bits { 2164 u8 time_since_last_clear_high[0x20]; 2165 2166 u8 time_since_last_clear_low[0x20]; 2167 2168 u8 symbol_errors_high[0x20]; 2169 2170 u8 symbol_errors_low[0x20]; 2171 2172 u8 sync_headers_errors_high[0x20]; 2173 2174 u8 sync_headers_errors_low[0x20]; 2175 2176 u8 edpl_bip_errors_lane0_high[0x20]; 2177 2178 u8 edpl_bip_errors_lane0_low[0x20]; 2179 2180 u8 edpl_bip_errors_lane1_high[0x20]; 2181 2182 u8 edpl_bip_errors_lane1_low[0x20]; 2183 2184 u8 edpl_bip_errors_lane2_high[0x20]; 2185 2186 u8 edpl_bip_errors_lane2_low[0x20]; 2187 2188 u8 edpl_bip_errors_lane3_high[0x20]; 2189 2190 u8 edpl_bip_errors_lane3_low[0x20]; 2191 2192 u8 fc_fec_corrected_blocks_lane0_high[0x20]; 2193 2194 u8 fc_fec_corrected_blocks_lane0_low[0x20]; 2195 2196 u8 fc_fec_corrected_blocks_lane1_high[0x20]; 2197 2198 u8 fc_fec_corrected_blocks_lane1_low[0x20]; 2199 2200 u8 fc_fec_corrected_blocks_lane2_high[0x20]; 2201 2202 u8 fc_fec_corrected_blocks_lane2_low[0x20]; 2203 2204 u8 fc_fec_corrected_blocks_lane3_high[0x20]; 2205 2206 u8 fc_fec_corrected_blocks_lane3_low[0x20]; 2207 2208 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20]; 2209 2210 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20]; 2211 2212 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20]; 2213 2214 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20]; 2215 2216 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20]; 2217 2218 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20]; 2219 2220 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20]; 2221 2222 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20]; 2223 2224 u8 rs_fec_corrected_blocks_high[0x20]; 2225 2226 u8 rs_fec_corrected_blocks_low[0x20]; 2227 2228 u8 rs_fec_uncorrectable_blocks_high[0x20]; 2229 2230 u8 rs_fec_uncorrectable_blocks_low[0x20]; 2231 2232 u8 rs_fec_no_errors_blocks_high[0x20]; 2233 2234 u8 rs_fec_no_errors_blocks_low[0x20]; 2235 2236 u8 rs_fec_single_error_blocks_high[0x20]; 2237 2238 u8 rs_fec_single_error_blocks_low[0x20]; 2239 2240 u8 rs_fec_corrected_symbols_total_high[0x20]; 2241 2242 u8 rs_fec_corrected_symbols_total_low[0x20]; 2243 2244 u8 rs_fec_corrected_symbols_lane0_high[0x20]; 2245 2246 u8 rs_fec_corrected_symbols_lane0_low[0x20]; 2247 2248 u8 rs_fec_corrected_symbols_lane1_high[0x20]; 2249 2250 u8 rs_fec_corrected_symbols_lane1_low[0x20]; 2251 2252 u8 rs_fec_corrected_symbols_lane2_high[0x20]; 2253 2254 u8 rs_fec_corrected_symbols_lane2_low[0x20]; 2255 2256 u8 rs_fec_corrected_symbols_lane3_high[0x20]; 2257 2258 u8 rs_fec_corrected_symbols_lane3_low[0x20]; 2259 2260 u8 link_down_events[0x20]; 2261 2262 u8 successful_recovery_events[0x20]; 2263 2264 u8 reserved_at_640[0x180]; 2265 }; 2266 2267 struct mlx5_ifc_phys_layer_statistical_cntrs_bits { 2268 u8 time_since_last_clear_high[0x20]; 2269 2270 u8 time_since_last_clear_low[0x20]; 2271 2272 u8 phy_received_bits_high[0x20]; 2273 2274 u8 phy_received_bits_low[0x20]; 2275 2276 u8 phy_symbol_errors_high[0x20]; 2277 2278 u8 phy_symbol_errors_low[0x20]; 2279 2280 u8 phy_corrected_bits_high[0x20]; 2281 2282 u8 phy_corrected_bits_low[0x20]; 2283 2284 u8 phy_corrected_bits_lane0_high[0x20]; 2285 2286 u8 phy_corrected_bits_lane0_low[0x20]; 2287 2288 u8 phy_corrected_bits_lane1_high[0x20]; 2289 2290 u8 phy_corrected_bits_lane1_low[0x20]; 2291 2292 u8 phy_corrected_bits_lane2_high[0x20]; 2293 2294 u8 phy_corrected_bits_lane2_low[0x20]; 2295 2296 u8 phy_corrected_bits_lane3_high[0x20]; 2297 2298 u8 phy_corrected_bits_lane3_low[0x20]; 2299 2300 u8 reserved_at_200[0x5c0]; 2301 }; 2302 2303 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits { 2304 u8 symbol_error_counter[0x10]; 2305 2306 u8 link_error_recovery_counter[0x8]; 2307 2308 u8 link_downed_counter[0x8]; 2309 2310 u8 port_rcv_errors[0x10]; 2311 2312 u8 port_rcv_remote_physical_errors[0x10]; 2313 2314 u8 port_rcv_switch_relay_errors[0x10]; 2315 2316 u8 port_xmit_discards[0x10]; 2317 2318 u8 port_xmit_constraint_errors[0x8]; 2319 2320 u8 port_rcv_constraint_errors[0x8]; 2321 2322 u8 reserved_at_70[0x8]; 2323 2324 u8 link_overrun_errors[0x8]; 2325 2326 u8 reserved_at_80[0x10]; 2327 2328 u8 vl_15_dropped[0x10]; 2329 2330 u8 reserved_at_a0[0x80]; 2331 2332 u8 port_xmit_wait[0x20]; 2333 }; 2334 2335 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits { 2336 u8 transmit_queue_high[0x20]; 2337 2338 u8 transmit_queue_low[0x20]; 2339 2340 u8 no_buffer_discard_uc_high[0x20]; 2341 2342 u8 no_buffer_discard_uc_low[0x20]; 2343 2344 u8 reserved_at_80[0x740]; 2345 }; 2346 2347 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits { 2348 u8 wred_discard_high[0x20]; 2349 2350 u8 wred_discard_low[0x20]; 2351 2352 u8 ecn_marked_tc_high[0x20]; 2353 2354 u8 ecn_marked_tc_low[0x20]; 2355 2356 u8 reserved_at_80[0x740]; 2357 }; 2358 2359 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits { 2360 u8 rx_octets_high[0x20]; 2361 2362 u8 rx_octets_low[0x20]; 2363 2364 u8 reserved_at_40[0xc0]; 2365 2366 u8 rx_frames_high[0x20]; 2367 2368 u8 rx_frames_low[0x20]; 2369 2370 u8 tx_octets_high[0x20]; 2371 2372 u8 tx_octets_low[0x20]; 2373 2374 u8 reserved_at_180[0xc0]; 2375 2376 u8 tx_frames_high[0x20]; 2377 2378 u8 tx_frames_low[0x20]; 2379 2380 u8 rx_pause_high[0x20]; 2381 2382 u8 rx_pause_low[0x20]; 2383 2384 u8 rx_pause_duration_high[0x20]; 2385 2386 u8 rx_pause_duration_low[0x20]; 2387 2388 u8 tx_pause_high[0x20]; 2389 2390 u8 tx_pause_low[0x20]; 2391 2392 u8 tx_pause_duration_high[0x20]; 2393 2394 u8 tx_pause_duration_low[0x20]; 2395 2396 u8 rx_pause_transition_high[0x20]; 2397 2398 u8 rx_pause_transition_low[0x20]; 2399 2400 u8 rx_discards_high[0x20]; 2401 2402 u8 rx_discards_low[0x20]; 2403 2404 u8 device_stall_minor_watermark_cnt_high[0x20]; 2405 2406 u8 device_stall_minor_watermark_cnt_low[0x20]; 2407 2408 u8 device_stall_critical_watermark_cnt_high[0x20]; 2409 2410 u8 device_stall_critical_watermark_cnt_low[0x20]; 2411 2412 u8 reserved_at_480[0x340]; 2413 }; 2414 2415 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits { 2416 u8 port_transmit_wait_high[0x20]; 2417 2418 u8 port_transmit_wait_low[0x20]; 2419 2420 u8 reserved_at_40[0x100]; 2421 2422 u8 rx_buffer_almost_full_high[0x20]; 2423 2424 u8 rx_buffer_almost_full_low[0x20]; 2425 2426 u8 rx_buffer_full_high[0x20]; 2427 2428 u8 rx_buffer_full_low[0x20]; 2429 2430 u8 rx_icrc_encapsulated_high[0x20]; 2431 2432 u8 rx_icrc_encapsulated_low[0x20]; 2433 2434 u8 reserved_at_200[0x5c0]; 2435 }; 2436 2437 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits { 2438 u8 dot3stats_alignment_errors_high[0x20]; 2439 2440 u8 dot3stats_alignment_errors_low[0x20]; 2441 2442 u8 dot3stats_fcs_errors_high[0x20]; 2443 2444 u8 dot3stats_fcs_errors_low[0x20]; 2445 2446 u8 dot3stats_single_collision_frames_high[0x20]; 2447 2448 u8 dot3stats_single_collision_frames_low[0x20]; 2449 2450 u8 dot3stats_multiple_collision_frames_high[0x20]; 2451 2452 u8 dot3stats_multiple_collision_frames_low[0x20]; 2453 2454 u8 dot3stats_sqe_test_errors_high[0x20]; 2455 2456 u8 dot3stats_sqe_test_errors_low[0x20]; 2457 2458 u8 dot3stats_deferred_transmissions_high[0x20]; 2459 2460 u8 dot3stats_deferred_transmissions_low[0x20]; 2461 2462 u8 dot3stats_late_collisions_high[0x20]; 2463 2464 u8 dot3stats_late_collisions_low[0x20]; 2465 2466 u8 dot3stats_excessive_collisions_high[0x20]; 2467 2468 u8 dot3stats_excessive_collisions_low[0x20]; 2469 2470 u8 dot3stats_internal_mac_transmit_errors_high[0x20]; 2471 2472 u8 dot3stats_internal_mac_transmit_errors_low[0x20]; 2473 2474 u8 dot3stats_carrier_sense_errors_high[0x20]; 2475 2476 u8 dot3stats_carrier_sense_errors_low[0x20]; 2477 2478 u8 dot3stats_frame_too_longs_high[0x20]; 2479 2480 u8 dot3stats_frame_too_longs_low[0x20]; 2481 2482 u8 dot3stats_internal_mac_receive_errors_high[0x20]; 2483 2484 u8 dot3stats_internal_mac_receive_errors_low[0x20]; 2485 2486 u8 dot3stats_symbol_errors_high[0x20]; 2487 2488 u8 dot3stats_symbol_errors_low[0x20]; 2489 2490 u8 dot3control_in_unknown_opcodes_high[0x20]; 2491 2492 u8 dot3control_in_unknown_opcodes_low[0x20]; 2493 2494 u8 dot3in_pause_frames_high[0x20]; 2495 2496 u8 dot3in_pause_frames_low[0x20]; 2497 2498 u8 dot3out_pause_frames_high[0x20]; 2499 2500 u8 dot3out_pause_frames_low[0x20]; 2501 2502 u8 reserved_at_400[0x3c0]; 2503 }; 2504 2505 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits { 2506 u8 ether_stats_drop_events_high[0x20]; 2507 2508 u8 ether_stats_drop_events_low[0x20]; 2509 2510 u8 ether_stats_octets_high[0x20]; 2511 2512 u8 ether_stats_octets_low[0x20]; 2513 2514 u8 ether_stats_pkts_high[0x20]; 2515 2516 u8 ether_stats_pkts_low[0x20]; 2517 2518 u8 ether_stats_broadcast_pkts_high[0x20]; 2519 2520 u8 ether_stats_broadcast_pkts_low[0x20]; 2521 2522 u8 ether_stats_multicast_pkts_high[0x20]; 2523 2524 u8 ether_stats_multicast_pkts_low[0x20]; 2525 2526 u8 ether_stats_crc_align_errors_high[0x20]; 2527 2528 u8 ether_stats_crc_align_errors_low[0x20]; 2529 2530 u8 ether_stats_undersize_pkts_high[0x20]; 2531 2532 u8 ether_stats_undersize_pkts_low[0x20]; 2533 2534 u8 ether_stats_oversize_pkts_high[0x20]; 2535 2536 u8 ether_stats_oversize_pkts_low[0x20]; 2537 2538 u8 ether_stats_fragments_high[0x20]; 2539 2540 u8 ether_stats_fragments_low[0x20]; 2541 2542 u8 ether_stats_jabbers_high[0x20]; 2543 2544 u8 ether_stats_jabbers_low[0x20]; 2545 2546 u8 ether_stats_collisions_high[0x20]; 2547 2548 u8 ether_stats_collisions_low[0x20]; 2549 2550 u8 ether_stats_pkts64octets_high[0x20]; 2551 2552 u8 ether_stats_pkts64octets_low[0x20]; 2553 2554 u8 ether_stats_pkts65to127octets_high[0x20]; 2555 2556 u8 ether_stats_pkts65to127octets_low[0x20]; 2557 2558 u8 ether_stats_pkts128to255octets_high[0x20]; 2559 2560 u8 ether_stats_pkts128to255octets_low[0x20]; 2561 2562 u8 ether_stats_pkts256to511octets_high[0x20]; 2563 2564 u8 ether_stats_pkts256to511octets_low[0x20]; 2565 2566 u8 ether_stats_pkts512to1023octets_high[0x20]; 2567 2568 u8 ether_stats_pkts512to1023octets_low[0x20]; 2569 2570 u8 ether_stats_pkts1024to1518octets_high[0x20]; 2571 2572 u8 ether_stats_pkts1024to1518octets_low[0x20]; 2573 2574 u8 ether_stats_pkts1519to2047octets_high[0x20]; 2575 2576 u8 ether_stats_pkts1519to2047octets_low[0x20]; 2577 2578 u8 ether_stats_pkts2048to4095octets_high[0x20]; 2579 2580 u8 ether_stats_pkts2048to4095octets_low[0x20]; 2581 2582 u8 ether_stats_pkts4096to8191octets_high[0x20]; 2583 2584 u8 ether_stats_pkts4096to8191octets_low[0x20]; 2585 2586 u8 ether_stats_pkts8192to10239octets_high[0x20]; 2587 2588 u8 ether_stats_pkts8192to10239octets_low[0x20]; 2589 2590 u8 reserved_at_540[0x280]; 2591 }; 2592 2593 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits { 2594 u8 if_in_octets_high[0x20]; 2595 2596 u8 if_in_octets_low[0x20]; 2597 2598 u8 if_in_ucast_pkts_high[0x20]; 2599 2600 u8 if_in_ucast_pkts_low[0x20]; 2601 2602 u8 if_in_discards_high[0x20]; 2603 2604 u8 if_in_discards_low[0x20]; 2605 2606 u8 if_in_errors_high[0x20]; 2607 2608 u8 if_in_errors_low[0x20]; 2609 2610 u8 if_in_unknown_protos_high[0x20]; 2611 2612 u8 if_in_unknown_protos_low[0x20]; 2613 2614 u8 if_out_octets_high[0x20]; 2615 2616 u8 if_out_octets_low[0x20]; 2617 2618 u8 if_out_ucast_pkts_high[0x20]; 2619 2620 u8 if_out_ucast_pkts_low[0x20]; 2621 2622 u8 if_out_discards_high[0x20]; 2623 2624 u8 if_out_discards_low[0x20]; 2625 2626 u8 if_out_errors_high[0x20]; 2627 2628 u8 if_out_errors_low[0x20]; 2629 2630 u8 if_in_multicast_pkts_high[0x20]; 2631 2632 u8 if_in_multicast_pkts_low[0x20]; 2633 2634 u8 if_in_broadcast_pkts_high[0x20]; 2635 2636 u8 if_in_broadcast_pkts_low[0x20]; 2637 2638 u8 if_out_multicast_pkts_high[0x20]; 2639 2640 u8 if_out_multicast_pkts_low[0x20]; 2641 2642 u8 if_out_broadcast_pkts_high[0x20]; 2643 2644 u8 if_out_broadcast_pkts_low[0x20]; 2645 2646 u8 reserved_at_340[0x480]; 2647 }; 2648 2649 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits { 2650 u8 a_frames_transmitted_ok_high[0x20]; 2651 2652 u8 a_frames_transmitted_ok_low[0x20]; 2653 2654 u8 a_frames_received_ok_high[0x20]; 2655 2656 u8 a_frames_received_ok_low[0x20]; 2657 2658 u8 a_frame_check_sequence_errors_high[0x20]; 2659 2660 u8 a_frame_check_sequence_errors_low[0x20]; 2661 2662 u8 a_alignment_errors_high[0x20]; 2663 2664 u8 a_alignment_errors_low[0x20]; 2665 2666 u8 a_octets_transmitted_ok_high[0x20]; 2667 2668 u8 a_octets_transmitted_ok_low[0x20]; 2669 2670 u8 a_octets_received_ok_high[0x20]; 2671 2672 u8 a_octets_received_ok_low[0x20]; 2673 2674 u8 a_multicast_frames_xmitted_ok_high[0x20]; 2675 2676 u8 a_multicast_frames_xmitted_ok_low[0x20]; 2677 2678 u8 a_broadcast_frames_xmitted_ok_high[0x20]; 2679 2680 u8 a_broadcast_frames_xmitted_ok_low[0x20]; 2681 2682 u8 a_multicast_frames_received_ok_high[0x20]; 2683 2684 u8 a_multicast_frames_received_ok_low[0x20]; 2685 2686 u8 a_broadcast_frames_received_ok_high[0x20]; 2687 2688 u8 a_broadcast_frames_received_ok_low[0x20]; 2689 2690 u8 a_in_range_length_errors_high[0x20]; 2691 2692 u8 a_in_range_length_errors_low[0x20]; 2693 2694 u8 a_out_of_range_length_field_high[0x20]; 2695 2696 u8 a_out_of_range_length_field_low[0x20]; 2697 2698 u8 a_frame_too_long_errors_high[0x20]; 2699 2700 u8 a_frame_too_long_errors_low[0x20]; 2701 2702 u8 a_symbol_error_during_carrier_high[0x20]; 2703 2704 u8 a_symbol_error_during_carrier_low[0x20]; 2705 2706 u8 a_mac_control_frames_transmitted_high[0x20]; 2707 2708 u8 a_mac_control_frames_transmitted_low[0x20]; 2709 2710 u8 a_mac_control_frames_received_high[0x20]; 2711 2712 u8 a_mac_control_frames_received_low[0x20]; 2713 2714 u8 a_unsupported_opcodes_received_high[0x20]; 2715 2716 u8 a_unsupported_opcodes_received_low[0x20]; 2717 2718 u8 a_pause_mac_ctrl_frames_received_high[0x20]; 2719 2720 u8 a_pause_mac_ctrl_frames_received_low[0x20]; 2721 2722 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20]; 2723 2724 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20]; 2725 2726 u8 reserved_at_4c0[0x300]; 2727 }; 2728 2729 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits { 2730 u8 life_time_counter_high[0x20]; 2731 2732 u8 life_time_counter_low[0x20]; 2733 2734 u8 rx_errors[0x20]; 2735 2736 u8 tx_errors[0x20]; 2737 2738 u8 l0_to_recovery_eieos[0x20]; 2739 2740 u8 l0_to_recovery_ts[0x20]; 2741 2742 u8 l0_to_recovery_framing[0x20]; 2743 2744 u8 l0_to_recovery_retrain[0x20]; 2745 2746 u8 crc_error_dllp[0x20]; 2747 2748 u8 crc_error_tlp[0x20]; 2749 2750 u8 tx_overflow_buffer_pkt_high[0x20]; 2751 2752 u8 tx_overflow_buffer_pkt_low[0x20]; 2753 2754 u8 outbound_stalled_reads[0x20]; 2755 2756 u8 outbound_stalled_writes[0x20]; 2757 2758 u8 outbound_stalled_reads_events[0x20]; 2759 2760 u8 outbound_stalled_writes_events[0x20]; 2761 2762 u8 reserved_at_200[0x5c0]; 2763 }; 2764 2765 struct mlx5_ifc_cmd_inter_comp_event_bits { 2766 u8 command_completion_vector[0x20]; 2767 2768 u8 reserved_at_20[0xc0]; 2769 }; 2770 2771 struct mlx5_ifc_stall_vl_event_bits { 2772 u8 reserved_at_0[0x18]; 2773 u8 port_num[0x1]; 2774 u8 reserved_at_19[0x3]; 2775 u8 vl[0x4]; 2776 2777 u8 reserved_at_20[0xa0]; 2778 }; 2779 2780 struct mlx5_ifc_db_bf_congestion_event_bits { 2781 u8 event_subtype[0x8]; 2782 u8 reserved_at_8[0x8]; 2783 u8 congestion_level[0x8]; 2784 u8 reserved_at_18[0x8]; 2785 2786 u8 reserved_at_20[0xa0]; 2787 }; 2788 2789 struct mlx5_ifc_gpio_event_bits { 2790 u8 reserved_at_0[0x60]; 2791 2792 u8 gpio_event_hi[0x20]; 2793 2794 u8 gpio_event_lo[0x20]; 2795 2796 u8 reserved_at_a0[0x40]; 2797 }; 2798 2799 struct mlx5_ifc_port_state_change_event_bits { 2800 u8 reserved_at_0[0x40]; 2801 2802 u8 port_num[0x4]; 2803 u8 reserved_at_44[0x1c]; 2804 2805 u8 reserved_at_60[0x80]; 2806 }; 2807 2808 struct mlx5_ifc_dropped_packet_logged_bits { 2809 u8 reserved_at_0[0xe0]; 2810 }; 2811 2812 enum { 2813 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1, 2814 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2, 2815 }; 2816 2817 struct mlx5_ifc_cq_error_bits { 2818 u8 reserved_at_0[0x8]; 2819 u8 cqn[0x18]; 2820 2821 u8 reserved_at_20[0x20]; 2822 2823 u8 reserved_at_40[0x18]; 2824 u8 syndrome[0x8]; 2825 2826 u8 reserved_at_60[0x80]; 2827 }; 2828 2829 struct mlx5_ifc_rdma_page_fault_event_bits { 2830 u8 bytes_committed[0x20]; 2831 2832 u8 r_key[0x20]; 2833 2834 u8 reserved_at_40[0x10]; 2835 u8 packet_len[0x10]; 2836 2837 u8 rdma_op_len[0x20]; 2838 2839 u8 rdma_va[0x40]; 2840 2841 u8 reserved_at_c0[0x5]; 2842 u8 rdma[0x1]; 2843 u8 write[0x1]; 2844 u8 requestor[0x1]; 2845 u8 qp_number[0x18]; 2846 }; 2847 2848 struct mlx5_ifc_wqe_associated_page_fault_event_bits { 2849 u8 bytes_committed[0x20]; 2850 2851 u8 reserved_at_20[0x10]; 2852 u8 wqe_index[0x10]; 2853 2854 u8 reserved_at_40[0x10]; 2855 u8 len[0x10]; 2856 2857 u8 reserved_at_60[0x60]; 2858 2859 u8 reserved_at_c0[0x5]; 2860 u8 rdma[0x1]; 2861 u8 write_read[0x1]; 2862 u8 requestor[0x1]; 2863 u8 qpn[0x18]; 2864 }; 2865 2866 struct mlx5_ifc_qp_events_bits { 2867 u8 reserved_at_0[0xa0]; 2868 2869 u8 type[0x8]; 2870 u8 reserved_at_a8[0x18]; 2871 2872 u8 reserved_at_c0[0x8]; 2873 u8 qpn_rqn_sqn[0x18]; 2874 }; 2875 2876 struct mlx5_ifc_dct_events_bits { 2877 u8 reserved_at_0[0xc0]; 2878 2879 u8 reserved_at_c0[0x8]; 2880 u8 dct_number[0x18]; 2881 }; 2882 2883 struct mlx5_ifc_comp_event_bits { 2884 u8 reserved_at_0[0xc0]; 2885 2886 u8 reserved_at_c0[0x8]; 2887 u8 cq_number[0x18]; 2888 }; 2889 2890 enum { 2891 MLX5_QPC_STATE_RST = 0x0, 2892 MLX5_QPC_STATE_INIT = 0x1, 2893 MLX5_QPC_STATE_RTR = 0x2, 2894 MLX5_QPC_STATE_RTS = 0x3, 2895 MLX5_QPC_STATE_SQER = 0x4, 2896 MLX5_QPC_STATE_ERR = 0x6, 2897 MLX5_QPC_STATE_SQD = 0x7, 2898 MLX5_QPC_STATE_SUSPENDED = 0x9, 2899 }; 2900 2901 enum { 2902 MLX5_QPC_ST_RC = 0x0, 2903 MLX5_QPC_ST_UC = 0x1, 2904 MLX5_QPC_ST_UD = 0x2, 2905 MLX5_QPC_ST_XRC = 0x3, 2906 MLX5_QPC_ST_DCI = 0x5, 2907 MLX5_QPC_ST_QP0 = 0x7, 2908 MLX5_QPC_ST_QP1 = 0x8, 2909 MLX5_QPC_ST_RAW_DATAGRAM = 0x9, 2910 MLX5_QPC_ST_REG_UMR = 0xc, 2911 }; 2912 2913 enum { 2914 MLX5_QPC_PM_STATE_ARMED = 0x0, 2915 MLX5_QPC_PM_STATE_REARM = 0x1, 2916 MLX5_QPC_PM_STATE_RESERVED = 0x2, 2917 MLX5_QPC_PM_STATE_MIGRATED = 0x3, 2918 }; 2919 2920 enum { 2921 MLX5_QPC_OFFLOAD_TYPE_RNDV = 0x1, 2922 }; 2923 2924 enum { 2925 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0, 2926 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1, 2927 }; 2928 2929 enum { 2930 MLX5_QPC_MTU_256_BYTES = 0x1, 2931 MLX5_QPC_MTU_512_BYTES = 0x2, 2932 MLX5_QPC_MTU_1K_BYTES = 0x3, 2933 MLX5_QPC_MTU_2K_BYTES = 0x4, 2934 MLX5_QPC_MTU_4K_BYTES = 0x5, 2935 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7, 2936 }; 2937 2938 enum { 2939 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1, 2940 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2, 2941 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3, 2942 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4, 2943 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5, 2944 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6, 2945 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7, 2946 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8, 2947 }; 2948 2949 enum { 2950 MLX5_QPC_CS_REQ_DISABLE = 0x0, 2951 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11, 2952 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22, 2953 }; 2954 2955 enum { 2956 MLX5_QPC_CS_RES_DISABLE = 0x0, 2957 MLX5_QPC_CS_RES_UP_TO_32B = 0x1, 2958 MLX5_QPC_CS_RES_UP_TO_64B = 0x2, 2959 }; 2960 2961 enum { 2962 MLX5_QPC_TIMESTAMP_FORMAT_FREE_RUNNING = 0x0, 2963 MLX5_QPC_TIMESTAMP_FORMAT_DEFAULT = 0x1, 2964 MLX5_QPC_TIMESTAMP_FORMAT_REAL_TIME = 0x2, 2965 }; 2966 2967 struct mlx5_ifc_qpc_bits { 2968 u8 state[0x4]; 2969 u8 lag_tx_port_affinity[0x4]; 2970 u8 st[0x8]; 2971 u8 reserved_at_10[0x2]; 2972 u8 isolate_vl_tc[0x1]; 2973 u8 pm_state[0x2]; 2974 u8 reserved_at_15[0x1]; 2975 u8 req_e2e_credit_mode[0x2]; 2976 u8 offload_type[0x4]; 2977 u8 end_padding_mode[0x2]; 2978 u8 reserved_at_1e[0x2]; 2979 2980 u8 wq_signature[0x1]; 2981 u8 block_lb_mc[0x1]; 2982 u8 atomic_like_write_en[0x1]; 2983 u8 latency_sensitive[0x1]; 2984 u8 reserved_at_24[0x1]; 2985 u8 drain_sigerr[0x1]; 2986 u8 reserved_at_26[0x2]; 2987 u8 pd[0x18]; 2988 2989 u8 mtu[0x3]; 2990 u8 log_msg_max[0x5]; 2991 u8 reserved_at_48[0x1]; 2992 u8 log_rq_size[0x4]; 2993 u8 log_rq_stride[0x3]; 2994 u8 no_sq[0x1]; 2995 u8 log_sq_size[0x4]; 2996 u8 reserved_at_55[0x3]; 2997 u8 ts_format[0x2]; 2998 u8 reserved_at_5a[0x1]; 2999 u8 rlky[0x1]; 3000 u8 ulp_stateless_offload_mode[0x4]; 3001 3002 u8 counter_set_id[0x8]; 3003 u8 uar_page[0x18]; 3004 3005 u8 reserved_at_80[0x8]; 3006 u8 user_index[0x18]; 3007 3008 u8 reserved_at_a0[0x3]; 3009 u8 log_page_size[0x5]; 3010 u8 remote_qpn[0x18]; 3011 3012 struct mlx5_ifc_ads_bits primary_address_path; 3013 3014 struct mlx5_ifc_ads_bits secondary_address_path; 3015 3016 u8 log_ack_req_freq[0x4]; 3017 u8 reserved_at_384[0x4]; 3018 u8 log_sra_max[0x3]; 3019 u8 reserved_at_38b[0x2]; 3020 u8 retry_count[0x3]; 3021 u8 rnr_retry[0x3]; 3022 u8 reserved_at_393[0x1]; 3023 u8 fre[0x1]; 3024 u8 cur_rnr_retry[0x3]; 3025 u8 cur_retry_count[0x3]; 3026 u8 reserved_at_39b[0x5]; 3027 3028 u8 reserved_at_3a0[0x20]; 3029 3030 u8 reserved_at_3c0[0x8]; 3031 u8 next_send_psn[0x18]; 3032 3033 u8 reserved_at_3e0[0x8]; 3034 u8 cqn_snd[0x18]; 3035 3036 u8 reserved_at_400[0x8]; 3037 u8 deth_sqpn[0x18]; 3038 3039 u8 reserved_at_420[0x20]; 3040 3041 u8 reserved_at_440[0x8]; 3042 u8 last_acked_psn[0x18]; 3043 3044 u8 reserved_at_460[0x8]; 3045 u8 ssn[0x18]; 3046 3047 u8 reserved_at_480[0x8]; 3048 u8 log_rra_max[0x3]; 3049 u8 reserved_at_48b[0x1]; 3050 u8 atomic_mode[0x4]; 3051 u8 rre[0x1]; 3052 u8 rwe[0x1]; 3053 u8 rae[0x1]; 3054 u8 reserved_at_493[0x1]; 3055 u8 page_offset[0x6]; 3056 u8 reserved_at_49a[0x3]; 3057 u8 cd_slave_receive[0x1]; 3058 u8 cd_slave_send[0x1]; 3059 u8 cd_master[0x1]; 3060 3061 u8 reserved_at_4a0[0x3]; 3062 u8 min_rnr_nak[0x5]; 3063 u8 next_rcv_psn[0x18]; 3064 3065 u8 reserved_at_4c0[0x8]; 3066 u8 xrcd[0x18]; 3067 3068 u8 reserved_at_4e0[0x8]; 3069 u8 cqn_rcv[0x18]; 3070 3071 u8 dbr_addr[0x40]; 3072 3073 u8 q_key[0x20]; 3074 3075 u8 reserved_at_560[0x5]; 3076 u8 rq_type[0x3]; 3077 u8 srqn_rmpn_xrqn[0x18]; 3078 3079 u8 reserved_at_580[0x8]; 3080 u8 rmsn[0x18]; 3081 3082 u8 hw_sq_wqebb_counter[0x10]; 3083 u8 sw_sq_wqebb_counter[0x10]; 3084 3085 u8 hw_rq_counter[0x20]; 3086 3087 u8 sw_rq_counter[0x20]; 3088 3089 u8 reserved_at_600[0x20]; 3090 3091 u8 reserved_at_620[0xf]; 3092 u8 cgs[0x1]; 3093 u8 cs_req[0x8]; 3094 u8 cs_res[0x8]; 3095 3096 u8 dc_access_key[0x40]; 3097 3098 u8 reserved_at_680[0x3]; 3099 u8 dbr_umem_valid[0x1]; 3100 3101 u8 reserved_at_684[0xbc]; 3102 }; 3103 3104 struct mlx5_ifc_roce_addr_layout_bits { 3105 u8 source_l3_address[16][0x8]; 3106 3107 u8 reserved_at_80[0x3]; 3108 u8 vlan_valid[0x1]; 3109 u8 vlan_id[0xc]; 3110 u8 source_mac_47_32[0x10]; 3111 3112 u8 source_mac_31_0[0x20]; 3113 3114 u8 reserved_at_c0[0x14]; 3115 u8 roce_l3_type[0x4]; 3116 u8 roce_version[0x8]; 3117 3118 u8 reserved_at_e0[0x20]; 3119 }; 3120 3121 union mlx5_ifc_hca_cap_union_bits { 3122 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap; 3123 struct mlx5_ifc_cmd_hca_cap_2_bits cmd_hca_cap_2; 3124 struct mlx5_ifc_odp_cap_bits odp_cap; 3125 struct mlx5_ifc_atomic_caps_bits atomic_caps; 3126 struct mlx5_ifc_roce_cap_bits roce_cap; 3127 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps; 3128 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap; 3129 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap; 3130 struct mlx5_ifc_e_switch_cap_bits e_switch_cap; 3131 struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap; 3132 struct mlx5_ifc_qos_cap_bits qos_cap; 3133 struct mlx5_ifc_debug_cap_bits debug_cap; 3134 struct mlx5_ifc_fpga_cap_bits fpga_cap; 3135 struct mlx5_ifc_tls_cap_bits tls_cap; 3136 struct mlx5_ifc_device_mem_cap_bits device_mem_cap; 3137 struct mlx5_ifc_virtio_emulation_cap_bits virtio_emulation_cap; 3138 u8 reserved_at_0[0x8000]; 3139 }; 3140 3141 enum { 3142 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1, 3143 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2, 3144 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4, 3145 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8, 3146 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT = 0x10, 3147 MLX5_FLOW_CONTEXT_ACTION_DECAP = 0x20, 3148 MLX5_FLOW_CONTEXT_ACTION_MOD_HDR = 0x40, 3149 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP = 0x80, 3150 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100, 3151 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2 = 0x400, 3152 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2 = 0x800, 3153 MLX5_FLOW_CONTEXT_ACTION_IPSEC_DECRYPT = 0x1000, 3154 MLX5_FLOW_CONTEXT_ACTION_IPSEC_ENCRYPT = 0x2000, 3155 }; 3156 3157 enum { 3158 MLX5_FLOW_CONTEXT_FLOW_SOURCE_ANY_VPORT = 0x0, 3159 MLX5_FLOW_CONTEXT_FLOW_SOURCE_UPLINK = 0x1, 3160 MLX5_FLOW_CONTEXT_FLOW_SOURCE_LOCAL_VPORT = 0x2, 3161 }; 3162 3163 struct mlx5_ifc_vlan_bits { 3164 u8 ethtype[0x10]; 3165 u8 prio[0x3]; 3166 u8 cfi[0x1]; 3167 u8 vid[0xc]; 3168 }; 3169 3170 struct mlx5_ifc_flow_context_bits { 3171 struct mlx5_ifc_vlan_bits push_vlan; 3172 3173 u8 group_id[0x20]; 3174 3175 u8 reserved_at_40[0x8]; 3176 u8 flow_tag[0x18]; 3177 3178 u8 reserved_at_60[0x10]; 3179 u8 action[0x10]; 3180 3181 u8 extended_destination[0x1]; 3182 u8 reserved_at_81[0x1]; 3183 u8 flow_source[0x2]; 3184 u8 reserved_at_84[0x4]; 3185 u8 destination_list_size[0x18]; 3186 3187 u8 reserved_at_a0[0x8]; 3188 u8 flow_counter_list_size[0x18]; 3189 3190 u8 packet_reformat_id[0x20]; 3191 3192 u8 modify_header_id[0x20]; 3193 3194 struct mlx5_ifc_vlan_bits push_vlan_2; 3195 3196 u8 ipsec_obj_id[0x20]; 3197 u8 reserved_at_140[0xc0]; 3198 3199 struct mlx5_ifc_fte_match_param_bits match_value; 3200 3201 u8 reserved_at_1200[0x600]; 3202 3203 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[]; 3204 }; 3205 3206 enum { 3207 MLX5_XRC_SRQC_STATE_GOOD = 0x0, 3208 MLX5_XRC_SRQC_STATE_ERROR = 0x1, 3209 }; 3210 3211 struct mlx5_ifc_xrc_srqc_bits { 3212 u8 state[0x4]; 3213 u8 log_xrc_srq_size[0x4]; 3214 u8 reserved_at_8[0x18]; 3215 3216 u8 wq_signature[0x1]; 3217 u8 cont_srq[0x1]; 3218 u8 reserved_at_22[0x1]; 3219 u8 rlky[0x1]; 3220 u8 basic_cyclic_rcv_wqe[0x1]; 3221 u8 log_rq_stride[0x3]; 3222 u8 xrcd[0x18]; 3223 3224 u8 page_offset[0x6]; 3225 u8 reserved_at_46[0x1]; 3226 u8 dbr_umem_valid[0x1]; 3227 u8 cqn[0x18]; 3228 3229 u8 reserved_at_60[0x20]; 3230 3231 u8 user_index_equal_xrc_srqn[0x1]; 3232 u8 reserved_at_81[0x1]; 3233 u8 log_page_size[0x6]; 3234 u8 user_index[0x18]; 3235 3236 u8 reserved_at_a0[0x20]; 3237 3238 u8 reserved_at_c0[0x8]; 3239 u8 pd[0x18]; 3240 3241 u8 lwm[0x10]; 3242 u8 wqe_cnt[0x10]; 3243 3244 u8 reserved_at_100[0x40]; 3245 3246 u8 db_record_addr_h[0x20]; 3247 3248 u8 db_record_addr_l[0x1e]; 3249 u8 reserved_at_17e[0x2]; 3250 3251 u8 reserved_at_180[0x80]; 3252 }; 3253 3254 struct mlx5_ifc_vnic_diagnostic_statistics_bits { 3255 u8 counter_error_queues[0x20]; 3256 3257 u8 total_error_queues[0x20]; 3258 3259 u8 send_queue_priority_update_flow[0x20]; 3260 3261 u8 reserved_at_60[0x20]; 3262 3263 u8 nic_receive_steering_discard[0x40]; 3264 3265 u8 receive_discard_vport_down[0x40]; 3266 3267 u8 transmit_discard_vport_down[0x40]; 3268 3269 u8 reserved_at_140[0xa0]; 3270 3271 u8 internal_rq_out_of_buffer[0x20]; 3272 3273 u8 reserved_at_200[0xe00]; 3274 }; 3275 3276 struct mlx5_ifc_traffic_counter_bits { 3277 u8 packets[0x40]; 3278 3279 u8 octets[0x40]; 3280 }; 3281 3282 struct mlx5_ifc_tisc_bits { 3283 u8 strict_lag_tx_port_affinity[0x1]; 3284 u8 tls_en[0x1]; 3285 u8 reserved_at_2[0x2]; 3286 u8 lag_tx_port_affinity[0x04]; 3287 3288 u8 reserved_at_8[0x4]; 3289 u8 prio[0x4]; 3290 u8 reserved_at_10[0x10]; 3291 3292 u8 reserved_at_20[0x100]; 3293 3294 u8 reserved_at_120[0x8]; 3295 u8 transport_domain[0x18]; 3296 3297 u8 reserved_at_140[0x8]; 3298 u8 underlay_qpn[0x18]; 3299 3300 u8 reserved_at_160[0x8]; 3301 u8 pd[0x18]; 3302 3303 u8 reserved_at_180[0x380]; 3304 }; 3305 3306 enum { 3307 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0, 3308 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1, 3309 }; 3310 3311 enum { 3312 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO = 0x1, 3313 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO = 0x2, 3314 }; 3315 3316 enum { 3317 MLX5_RX_HASH_FN_NONE = 0x0, 3318 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1, 3319 MLX5_RX_HASH_FN_TOEPLITZ = 0x2, 3320 }; 3321 3322 enum { 3323 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST = 0x1, 3324 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST = 0x2, 3325 }; 3326 3327 struct mlx5_ifc_tirc_bits { 3328 u8 reserved_at_0[0x20]; 3329 3330 u8 disp_type[0x4]; 3331 u8 tls_en[0x1]; 3332 u8 reserved_at_25[0x1b]; 3333 3334 u8 reserved_at_40[0x40]; 3335 3336 u8 reserved_at_80[0x4]; 3337 u8 lro_timeout_period_usecs[0x10]; 3338 u8 lro_enable_mask[0x4]; 3339 u8 lro_max_ip_payload_size[0x8]; 3340 3341 u8 reserved_at_a0[0x40]; 3342 3343 u8 reserved_at_e0[0x8]; 3344 u8 inline_rqn[0x18]; 3345 3346 u8 rx_hash_symmetric[0x1]; 3347 u8 reserved_at_101[0x1]; 3348 u8 tunneled_offload_en[0x1]; 3349 u8 reserved_at_103[0x5]; 3350 u8 indirect_table[0x18]; 3351 3352 u8 rx_hash_fn[0x4]; 3353 u8 reserved_at_124[0x2]; 3354 u8 self_lb_block[0x2]; 3355 u8 transport_domain[0x18]; 3356 3357 u8 rx_hash_toeplitz_key[10][0x20]; 3358 3359 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer; 3360 3361 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner; 3362 3363 u8 reserved_at_2c0[0x4c0]; 3364 }; 3365 3366 enum { 3367 MLX5_SRQC_STATE_GOOD = 0x0, 3368 MLX5_SRQC_STATE_ERROR = 0x1, 3369 }; 3370 3371 struct mlx5_ifc_srqc_bits { 3372 u8 state[0x4]; 3373 u8 log_srq_size[0x4]; 3374 u8 reserved_at_8[0x18]; 3375 3376 u8 wq_signature[0x1]; 3377 u8 cont_srq[0x1]; 3378 u8 reserved_at_22[0x1]; 3379 u8 rlky[0x1]; 3380 u8 reserved_at_24[0x1]; 3381 u8 log_rq_stride[0x3]; 3382 u8 xrcd[0x18]; 3383 3384 u8 page_offset[0x6]; 3385 u8 reserved_at_46[0x2]; 3386 u8 cqn[0x18]; 3387 3388 u8 reserved_at_60[0x20]; 3389 3390 u8 reserved_at_80[0x2]; 3391 u8 log_page_size[0x6]; 3392 u8 reserved_at_88[0x18]; 3393 3394 u8 reserved_at_a0[0x20]; 3395 3396 u8 reserved_at_c0[0x8]; 3397 u8 pd[0x18]; 3398 3399 u8 lwm[0x10]; 3400 u8 wqe_cnt[0x10]; 3401 3402 u8 reserved_at_100[0x40]; 3403 3404 u8 dbr_addr[0x40]; 3405 3406 u8 reserved_at_180[0x80]; 3407 }; 3408 3409 enum { 3410 MLX5_SQC_STATE_RST = 0x0, 3411 MLX5_SQC_STATE_RDY = 0x1, 3412 MLX5_SQC_STATE_ERR = 0x3, 3413 }; 3414 3415 enum { 3416 MLX5_SQC_TIMESTAMP_FORMAT_FREE_RUNNING = 0x0, 3417 MLX5_SQC_TIMESTAMP_FORMAT_DEFAULT = 0x1, 3418 MLX5_SQC_TIMESTAMP_FORMAT_REAL_TIME = 0x2, 3419 }; 3420 3421 struct mlx5_ifc_sqc_bits { 3422 u8 rlky[0x1]; 3423 u8 cd_master[0x1]; 3424 u8 fre[0x1]; 3425 u8 flush_in_error_en[0x1]; 3426 u8 allow_multi_pkt_send_wqe[0x1]; 3427 u8 min_wqe_inline_mode[0x3]; 3428 u8 state[0x4]; 3429 u8 reg_umr[0x1]; 3430 u8 allow_swp[0x1]; 3431 u8 hairpin[0x1]; 3432 u8 reserved_at_f[0xb]; 3433 u8 ts_format[0x2]; 3434 u8 reserved_at_1c[0x4]; 3435 3436 u8 reserved_at_20[0x8]; 3437 u8 user_index[0x18]; 3438 3439 u8 reserved_at_40[0x8]; 3440 u8 cqn[0x18]; 3441 3442 u8 reserved_at_60[0x8]; 3443 u8 hairpin_peer_rq[0x18]; 3444 3445 u8 reserved_at_80[0x10]; 3446 u8 hairpin_peer_vhca[0x10]; 3447 3448 u8 reserved_at_a0[0x20]; 3449 3450 u8 reserved_at_c0[0x8]; 3451 u8 ts_cqe_to_dest_cqn[0x18]; 3452 3453 u8 reserved_at_e0[0x10]; 3454 u8 packet_pacing_rate_limit_index[0x10]; 3455 u8 tis_lst_sz[0x10]; 3456 u8 qos_queue_group_id[0x10]; 3457 3458 u8 reserved_at_120[0x40]; 3459 3460 u8 reserved_at_160[0x8]; 3461 u8 tis_num_0[0x18]; 3462 3463 struct mlx5_ifc_wq_bits wq; 3464 }; 3465 3466 enum { 3467 SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0, 3468 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1, 3469 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2, 3470 SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3, 3471 SCHEDULING_CONTEXT_ELEMENT_TYPE_QUEUE_GROUP = 0x4, 3472 }; 3473 3474 enum { 3475 ELEMENT_TYPE_CAP_MASK_TASR = 1 << 0, 3476 ELEMENT_TYPE_CAP_MASK_VPORT = 1 << 1, 3477 ELEMENT_TYPE_CAP_MASK_VPORT_TC = 1 << 2, 3478 ELEMENT_TYPE_CAP_MASK_PARA_VPORT_TC = 1 << 3, 3479 }; 3480 3481 struct mlx5_ifc_scheduling_context_bits { 3482 u8 element_type[0x8]; 3483 u8 reserved_at_8[0x18]; 3484 3485 u8 element_attributes[0x20]; 3486 3487 u8 parent_element_id[0x20]; 3488 3489 u8 reserved_at_60[0x40]; 3490 3491 u8 bw_share[0x20]; 3492 3493 u8 max_average_bw[0x20]; 3494 3495 u8 reserved_at_e0[0x120]; 3496 }; 3497 3498 struct mlx5_ifc_rqtc_bits { 3499 u8 reserved_at_0[0xa0]; 3500 3501 u8 reserved_at_a0[0x5]; 3502 u8 list_q_type[0x3]; 3503 u8 reserved_at_a8[0x8]; 3504 u8 rqt_max_size[0x10]; 3505 3506 u8 rq_vhca_id_format[0x1]; 3507 u8 reserved_at_c1[0xf]; 3508 u8 rqt_actual_size[0x10]; 3509 3510 u8 reserved_at_e0[0x6a0]; 3511 3512 struct mlx5_ifc_rq_num_bits rq_num[]; 3513 }; 3514 3515 enum { 3516 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0, 3517 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1, 3518 }; 3519 3520 enum { 3521 MLX5_RQC_STATE_RST = 0x0, 3522 MLX5_RQC_STATE_RDY = 0x1, 3523 MLX5_RQC_STATE_ERR = 0x3, 3524 }; 3525 3526 enum { 3527 MLX5_RQC_TIMESTAMP_FORMAT_FREE_RUNNING = 0x0, 3528 MLX5_RQC_TIMESTAMP_FORMAT_DEFAULT = 0x1, 3529 MLX5_RQC_TIMESTAMP_FORMAT_REAL_TIME = 0x2, 3530 }; 3531 3532 struct mlx5_ifc_rqc_bits { 3533 u8 rlky[0x1]; 3534 u8 delay_drop_en[0x1]; 3535 u8 scatter_fcs[0x1]; 3536 u8 vsd[0x1]; 3537 u8 mem_rq_type[0x4]; 3538 u8 state[0x4]; 3539 u8 reserved_at_c[0x1]; 3540 u8 flush_in_error_en[0x1]; 3541 u8 hairpin[0x1]; 3542 u8 reserved_at_f[0xb]; 3543 u8 ts_format[0x2]; 3544 u8 reserved_at_1c[0x4]; 3545 3546 u8 reserved_at_20[0x8]; 3547 u8 user_index[0x18]; 3548 3549 u8 reserved_at_40[0x8]; 3550 u8 cqn[0x18]; 3551 3552 u8 counter_set_id[0x8]; 3553 u8 reserved_at_68[0x18]; 3554 3555 u8 reserved_at_80[0x8]; 3556 u8 rmpn[0x18]; 3557 3558 u8 reserved_at_a0[0x8]; 3559 u8 hairpin_peer_sq[0x18]; 3560 3561 u8 reserved_at_c0[0x10]; 3562 u8 hairpin_peer_vhca[0x10]; 3563 3564 u8 reserved_at_e0[0xa0]; 3565 3566 struct mlx5_ifc_wq_bits wq; 3567 }; 3568 3569 enum { 3570 MLX5_RMPC_STATE_RDY = 0x1, 3571 MLX5_RMPC_STATE_ERR = 0x3, 3572 }; 3573 3574 struct mlx5_ifc_rmpc_bits { 3575 u8 reserved_at_0[0x8]; 3576 u8 state[0x4]; 3577 u8 reserved_at_c[0x14]; 3578 3579 u8 basic_cyclic_rcv_wqe[0x1]; 3580 u8 reserved_at_21[0x1f]; 3581 3582 u8 reserved_at_40[0x140]; 3583 3584 struct mlx5_ifc_wq_bits wq; 3585 }; 3586 3587 struct mlx5_ifc_nic_vport_context_bits { 3588 u8 reserved_at_0[0x5]; 3589 u8 min_wqe_inline_mode[0x3]; 3590 u8 reserved_at_8[0x15]; 3591 u8 disable_mc_local_lb[0x1]; 3592 u8 disable_uc_local_lb[0x1]; 3593 u8 roce_en[0x1]; 3594 3595 u8 arm_change_event[0x1]; 3596 u8 reserved_at_21[0x1a]; 3597 u8 event_on_mtu[0x1]; 3598 u8 event_on_promisc_change[0x1]; 3599 u8 event_on_vlan_change[0x1]; 3600 u8 event_on_mc_address_change[0x1]; 3601 u8 event_on_uc_address_change[0x1]; 3602 3603 u8 reserved_at_40[0xc]; 3604 3605 u8 affiliation_criteria[0x4]; 3606 u8 affiliated_vhca_id[0x10]; 3607 3608 u8 reserved_at_60[0xd0]; 3609 3610 u8 mtu[0x10]; 3611 3612 u8 system_image_guid[0x40]; 3613 u8 port_guid[0x40]; 3614 u8 node_guid[0x40]; 3615 3616 u8 reserved_at_200[0x140]; 3617 u8 qkey_violation_counter[0x10]; 3618 u8 reserved_at_350[0x430]; 3619 3620 u8 promisc_uc[0x1]; 3621 u8 promisc_mc[0x1]; 3622 u8 promisc_all[0x1]; 3623 u8 reserved_at_783[0x2]; 3624 u8 allowed_list_type[0x3]; 3625 u8 reserved_at_788[0xc]; 3626 u8 allowed_list_size[0xc]; 3627 3628 struct mlx5_ifc_mac_address_layout_bits permanent_address; 3629 3630 u8 reserved_at_7e0[0x20]; 3631 3632 u8 current_uc_mac_address[][0x40]; 3633 }; 3634 3635 enum { 3636 MLX5_MKC_ACCESS_MODE_PA = 0x0, 3637 MLX5_MKC_ACCESS_MODE_MTT = 0x1, 3638 MLX5_MKC_ACCESS_MODE_KLMS = 0x2, 3639 MLX5_MKC_ACCESS_MODE_KSM = 0x3, 3640 MLX5_MKC_ACCESS_MODE_SW_ICM = 0x4, 3641 MLX5_MKC_ACCESS_MODE_MEMIC = 0x5, 3642 }; 3643 3644 struct mlx5_ifc_mkc_bits { 3645 u8 reserved_at_0[0x1]; 3646 u8 free[0x1]; 3647 u8 reserved_at_2[0x1]; 3648 u8 access_mode_4_2[0x3]; 3649 u8 reserved_at_6[0x7]; 3650 u8 relaxed_ordering_write[0x1]; 3651 u8 reserved_at_e[0x1]; 3652 u8 small_fence_on_rdma_read_response[0x1]; 3653 u8 umr_en[0x1]; 3654 u8 a[0x1]; 3655 u8 rw[0x1]; 3656 u8 rr[0x1]; 3657 u8 lw[0x1]; 3658 u8 lr[0x1]; 3659 u8 access_mode_1_0[0x2]; 3660 u8 reserved_at_18[0x8]; 3661 3662 u8 qpn[0x18]; 3663 u8 mkey_7_0[0x8]; 3664 3665 u8 reserved_at_40[0x20]; 3666 3667 u8 length64[0x1]; 3668 u8 bsf_en[0x1]; 3669 u8 sync_umr[0x1]; 3670 u8 reserved_at_63[0x2]; 3671 u8 expected_sigerr_count[0x1]; 3672 u8 reserved_at_66[0x1]; 3673 u8 en_rinval[0x1]; 3674 u8 pd[0x18]; 3675 3676 u8 start_addr[0x40]; 3677 3678 u8 len[0x40]; 3679 3680 u8 bsf_octword_size[0x20]; 3681 3682 u8 reserved_at_120[0x80]; 3683 3684 u8 translations_octword_size[0x20]; 3685 3686 u8 reserved_at_1c0[0x19]; 3687 u8 relaxed_ordering_read[0x1]; 3688 u8 reserved_at_1d9[0x1]; 3689 u8 log_page_size[0x5]; 3690 3691 u8 reserved_at_1e0[0x20]; 3692 }; 3693 3694 struct mlx5_ifc_pkey_bits { 3695 u8 reserved_at_0[0x10]; 3696 u8 pkey[0x10]; 3697 }; 3698 3699 struct mlx5_ifc_array128_auto_bits { 3700 u8 array128_auto[16][0x8]; 3701 }; 3702 3703 struct mlx5_ifc_hca_vport_context_bits { 3704 u8 field_select[0x20]; 3705 3706 u8 reserved_at_20[0xe0]; 3707 3708 u8 sm_virt_aware[0x1]; 3709 u8 has_smi[0x1]; 3710 u8 has_raw[0x1]; 3711 u8 grh_required[0x1]; 3712 u8 reserved_at_104[0xc]; 3713 u8 port_physical_state[0x4]; 3714 u8 vport_state_policy[0x4]; 3715 u8 port_state[0x4]; 3716 u8 vport_state[0x4]; 3717 3718 u8 reserved_at_120[0x20]; 3719 3720 u8 system_image_guid[0x40]; 3721 3722 u8 port_guid[0x40]; 3723 3724 u8 node_guid[0x40]; 3725 3726 u8 cap_mask1[0x20]; 3727 3728 u8 cap_mask1_field_select[0x20]; 3729 3730 u8 cap_mask2[0x20]; 3731 3732 u8 cap_mask2_field_select[0x20]; 3733 3734 u8 reserved_at_280[0x80]; 3735 3736 u8 lid[0x10]; 3737 u8 reserved_at_310[0x4]; 3738 u8 init_type_reply[0x4]; 3739 u8 lmc[0x3]; 3740 u8 subnet_timeout[0x5]; 3741 3742 u8 sm_lid[0x10]; 3743 u8 sm_sl[0x4]; 3744 u8 reserved_at_334[0xc]; 3745 3746 u8 qkey_violation_counter[0x10]; 3747 u8 pkey_violation_counter[0x10]; 3748 3749 u8 reserved_at_360[0xca0]; 3750 }; 3751 3752 struct mlx5_ifc_esw_vport_context_bits { 3753 u8 fdb_to_vport_reg_c[0x1]; 3754 u8 reserved_at_1[0x2]; 3755 u8 vport_svlan_strip[0x1]; 3756 u8 vport_cvlan_strip[0x1]; 3757 u8 vport_svlan_insert[0x1]; 3758 u8 vport_cvlan_insert[0x2]; 3759 u8 fdb_to_vport_reg_c_id[0x8]; 3760 u8 reserved_at_10[0x10]; 3761 3762 u8 reserved_at_20[0x20]; 3763 3764 u8 svlan_cfi[0x1]; 3765 u8 svlan_pcp[0x3]; 3766 u8 svlan_id[0xc]; 3767 u8 cvlan_cfi[0x1]; 3768 u8 cvlan_pcp[0x3]; 3769 u8 cvlan_id[0xc]; 3770 3771 u8 reserved_at_60[0x720]; 3772 3773 u8 sw_steering_vport_icm_address_rx[0x40]; 3774 3775 u8 sw_steering_vport_icm_address_tx[0x40]; 3776 }; 3777 3778 enum { 3779 MLX5_EQC_STATUS_OK = 0x0, 3780 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa, 3781 }; 3782 3783 enum { 3784 MLX5_EQC_ST_ARMED = 0x9, 3785 MLX5_EQC_ST_FIRED = 0xa, 3786 }; 3787 3788 struct mlx5_ifc_eqc_bits { 3789 u8 status[0x4]; 3790 u8 reserved_at_4[0x9]; 3791 u8 ec[0x1]; 3792 u8 oi[0x1]; 3793 u8 reserved_at_f[0x5]; 3794 u8 st[0x4]; 3795 u8 reserved_at_18[0x8]; 3796 3797 u8 reserved_at_20[0x20]; 3798 3799 u8 reserved_at_40[0x14]; 3800 u8 page_offset[0x6]; 3801 u8 reserved_at_5a[0x6]; 3802 3803 u8 reserved_at_60[0x3]; 3804 u8 log_eq_size[0x5]; 3805 u8 uar_page[0x18]; 3806 3807 u8 reserved_at_80[0x20]; 3808 3809 u8 reserved_at_a0[0x14]; 3810 u8 intr[0xc]; 3811 3812 u8 reserved_at_c0[0x3]; 3813 u8 log_page_size[0x5]; 3814 u8 reserved_at_c8[0x18]; 3815 3816 u8 reserved_at_e0[0x60]; 3817 3818 u8 reserved_at_140[0x8]; 3819 u8 consumer_counter[0x18]; 3820 3821 u8 reserved_at_160[0x8]; 3822 u8 producer_counter[0x18]; 3823 3824 u8 reserved_at_180[0x80]; 3825 }; 3826 3827 enum { 3828 MLX5_DCTC_STATE_ACTIVE = 0x0, 3829 MLX5_DCTC_STATE_DRAINING = 0x1, 3830 MLX5_DCTC_STATE_DRAINED = 0x2, 3831 }; 3832 3833 enum { 3834 MLX5_DCTC_CS_RES_DISABLE = 0x0, 3835 MLX5_DCTC_CS_RES_NA = 0x1, 3836 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2, 3837 }; 3838 3839 enum { 3840 MLX5_DCTC_MTU_256_BYTES = 0x1, 3841 MLX5_DCTC_MTU_512_BYTES = 0x2, 3842 MLX5_DCTC_MTU_1K_BYTES = 0x3, 3843 MLX5_DCTC_MTU_2K_BYTES = 0x4, 3844 MLX5_DCTC_MTU_4K_BYTES = 0x5, 3845 }; 3846 3847 struct mlx5_ifc_dctc_bits { 3848 u8 reserved_at_0[0x4]; 3849 u8 state[0x4]; 3850 u8 reserved_at_8[0x18]; 3851 3852 u8 reserved_at_20[0x8]; 3853 u8 user_index[0x18]; 3854 3855 u8 reserved_at_40[0x8]; 3856 u8 cqn[0x18]; 3857 3858 u8 counter_set_id[0x8]; 3859 u8 atomic_mode[0x4]; 3860 u8 rre[0x1]; 3861 u8 rwe[0x1]; 3862 u8 rae[0x1]; 3863 u8 atomic_like_write_en[0x1]; 3864 u8 latency_sensitive[0x1]; 3865 u8 rlky[0x1]; 3866 u8 free_ar[0x1]; 3867 u8 reserved_at_73[0xd]; 3868 3869 u8 reserved_at_80[0x8]; 3870 u8 cs_res[0x8]; 3871 u8 reserved_at_90[0x3]; 3872 u8 min_rnr_nak[0x5]; 3873 u8 reserved_at_98[0x8]; 3874 3875 u8 reserved_at_a0[0x8]; 3876 u8 srqn_xrqn[0x18]; 3877 3878 u8 reserved_at_c0[0x8]; 3879 u8 pd[0x18]; 3880 3881 u8 tclass[0x8]; 3882 u8 reserved_at_e8[0x4]; 3883 u8 flow_label[0x14]; 3884 3885 u8 dc_access_key[0x40]; 3886 3887 u8 reserved_at_140[0x5]; 3888 u8 mtu[0x3]; 3889 u8 port[0x8]; 3890 u8 pkey_index[0x10]; 3891 3892 u8 reserved_at_160[0x8]; 3893 u8 my_addr_index[0x8]; 3894 u8 reserved_at_170[0x8]; 3895 u8 hop_limit[0x8]; 3896 3897 u8 dc_access_key_violation_count[0x20]; 3898 3899 u8 reserved_at_1a0[0x14]; 3900 u8 dei_cfi[0x1]; 3901 u8 eth_prio[0x3]; 3902 u8 ecn[0x2]; 3903 u8 dscp[0x6]; 3904 3905 u8 reserved_at_1c0[0x20]; 3906 u8 ece[0x20]; 3907 }; 3908 3909 enum { 3910 MLX5_CQC_STATUS_OK = 0x0, 3911 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9, 3912 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa, 3913 }; 3914 3915 enum { 3916 MLX5_CQC_CQE_SZ_64_BYTES = 0x0, 3917 MLX5_CQC_CQE_SZ_128_BYTES = 0x1, 3918 }; 3919 3920 enum { 3921 MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED = 0x6, 3922 MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED = 0x9, 3923 MLX5_CQC_ST_FIRED = 0xa, 3924 }; 3925 3926 enum { 3927 MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0, 3928 MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1, 3929 MLX5_CQ_PERIOD_NUM_MODES 3930 }; 3931 3932 struct mlx5_ifc_cqc_bits { 3933 u8 status[0x4]; 3934 u8 reserved_at_4[0x2]; 3935 u8 dbr_umem_valid[0x1]; 3936 u8 apu_thread_cq[0x1]; 3937 u8 cqe_sz[0x3]; 3938 u8 cc[0x1]; 3939 u8 reserved_at_c[0x1]; 3940 u8 scqe_break_moderation_en[0x1]; 3941 u8 oi[0x1]; 3942 u8 cq_period_mode[0x2]; 3943 u8 cqe_comp_en[0x1]; 3944 u8 mini_cqe_res_format[0x2]; 3945 u8 st[0x4]; 3946 u8 reserved_at_18[0x8]; 3947 3948 u8 reserved_at_20[0x20]; 3949 3950 u8 reserved_at_40[0x14]; 3951 u8 page_offset[0x6]; 3952 u8 reserved_at_5a[0x6]; 3953 3954 u8 reserved_at_60[0x3]; 3955 u8 log_cq_size[0x5]; 3956 u8 uar_page[0x18]; 3957 3958 u8 reserved_at_80[0x4]; 3959 u8 cq_period[0xc]; 3960 u8 cq_max_count[0x10]; 3961 3962 u8 reserved_at_a0[0x18]; 3963 u8 c_eqn[0x8]; 3964 3965 u8 reserved_at_c0[0x3]; 3966 u8 log_page_size[0x5]; 3967 u8 reserved_at_c8[0x18]; 3968 3969 u8 reserved_at_e0[0x20]; 3970 3971 u8 reserved_at_100[0x8]; 3972 u8 last_notified_index[0x18]; 3973 3974 u8 reserved_at_120[0x8]; 3975 u8 last_solicit_index[0x18]; 3976 3977 u8 reserved_at_140[0x8]; 3978 u8 consumer_counter[0x18]; 3979 3980 u8 reserved_at_160[0x8]; 3981 u8 producer_counter[0x18]; 3982 3983 u8 reserved_at_180[0x40]; 3984 3985 u8 dbr_addr[0x40]; 3986 }; 3987 3988 union mlx5_ifc_cong_control_roce_ecn_auto_bits { 3989 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp; 3990 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp; 3991 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np; 3992 u8 reserved_at_0[0x800]; 3993 }; 3994 3995 struct mlx5_ifc_query_adapter_param_block_bits { 3996 u8 reserved_at_0[0xc0]; 3997 3998 u8 reserved_at_c0[0x8]; 3999 u8 ieee_vendor_id[0x18]; 4000 4001 u8 reserved_at_e0[0x10]; 4002 u8 vsd_vendor_id[0x10]; 4003 4004 u8 vsd[208][0x8]; 4005 4006 u8 vsd_contd_psid[16][0x8]; 4007 }; 4008 4009 enum { 4010 MLX5_XRQC_STATE_GOOD = 0x0, 4011 MLX5_XRQC_STATE_ERROR = 0x1, 4012 }; 4013 4014 enum { 4015 MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0, 4016 MLX5_XRQC_TOPOLOGY_TAG_MATCHING = 0x1, 4017 }; 4018 4019 enum { 4020 MLX5_XRQC_OFFLOAD_RNDV = 0x1, 4021 }; 4022 4023 struct mlx5_ifc_tag_matching_topology_context_bits { 4024 u8 log_matching_list_sz[0x4]; 4025 u8 reserved_at_4[0xc]; 4026 u8 append_next_index[0x10]; 4027 4028 u8 sw_phase_cnt[0x10]; 4029 u8 hw_phase_cnt[0x10]; 4030 4031 u8 reserved_at_40[0x40]; 4032 }; 4033 4034 struct mlx5_ifc_xrqc_bits { 4035 u8 state[0x4]; 4036 u8 rlkey[0x1]; 4037 u8 reserved_at_5[0xf]; 4038 u8 topology[0x4]; 4039 u8 reserved_at_18[0x4]; 4040 u8 offload[0x4]; 4041 4042 u8 reserved_at_20[0x8]; 4043 u8 user_index[0x18]; 4044 4045 u8 reserved_at_40[0x8]; 4046 u8 cqn[0x18]; 4047 4048 u8 reserved_at_60[0xa0]; 4049 4050 struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context; 4051 4052 u8 reserved_at_180[0x280]; 4053 4054 struct mlx5_ifc_wq_bits wq; 4055 }; 4056 4057 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits { 4058 struct mlx5_ifc_modify_field_select_bits modify_field_select; 4059 struct mlx5_ifc_resize_field_select_bits resize_field_select; 4060 u8 reserved_at_0[0x20]; 4061 }; 4062 4063 union mlx5_ifc_field_select_802_1_r_roce_auto_bits { 4064 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp; 4065 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp; 4066 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np; 4067 u8 reserved_at_0[0x20]; 4068 }; 4069 4070 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits { 4071 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 4072 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 4073 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 4074 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 4075 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 4076 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 4077 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout; 4078 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout; 4079 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 4080 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 4081 struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs; 4082 u8 reserved_at_0[0x7c0]; 4083 }; 4084 4085 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits { 4086 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout; 4087 u8 reserved_at_0[0x7c0]; 4088 }; 4089 4090 union mlx5_ifc_event_auto_bits { 4091 struct mlx5_ifc_comp_event_bits comp_event; 4092 struct mlx5_ifc_dct_events_bits dct_events; 4093 struct mlx5_ifc_qp_events_bits qp_events; 4094 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event; 4095 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event; 4096 struct mlx5_ifc_cq_error_bits cq_error; 4097 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged; 4098 struct mlx5_ifc_port_state_change_event_bits port_state_change_event; 4099 struct mlx5_ifc_gpio_event_bits gpio_event; 4100 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event; 4101 struct mlx5_ifc_stall_vl_event_bits stall_vl_event; 4102 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event; 4103 u8 reserved_at_0[0xe0]; 4104 }; 4105 4106 struct mlx5_ifc_health_buffer_bits { 4107 u8 reserved_at_0[0x100]; 4108 4109 u8 assert_existptr[0x20]; 4110 4111 u8 assert_callra[0x20]; 4112 4113 u8 reserved_at_140[0x40]; 4114 4115 u8 fw_version[0x20]; 4116 4117 u8 hw_id[0x20]; 4118 4119 u8 reserved_at_1c0[0x20]; 4120 4121 u8 irisc_index[0x8]; 4122 u8 synd[0x8]; 4123 u8 ext_synd[0x10]; 4124 }; 4125 4126 struct mlx5_ifc_register_loopback_control_bits { 4127 u8 no_lb[0x1]; 4128 u8 reserved_at_1[0x7]; 4129 u8 port[0x8]; 4130 u8 reserved_at_10[0x10]; 4131 4132 u8 reserved_at_20[0x60]; 4133 }; 4134 4135 struct mlx5_ifc_vport_tc_element_bits { 4136 u8 traffic_class[0x4]; 4137 u8 reserved_at_4[0xc]; 4138 u8 vport_number[0x10]; 4139 }; 4140 4141 struct mlx5_ifc_vport_element_bits { 4142 u8 reserved_at_0[0x10]; 4143 u8 vport_number[0x10]; 4144 }; 4145 4146 enum { 4147 TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0, 4148 TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1, 4149 TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2, 4150 }; 4151 4152 struct mlx5_ifc_tsar_element_bits { 4153 u8 reserved_at_0[0x8]; 4154 u8 tsar_type[0x8]; 4155 u8 reserved_at_10[0x10]; 4156 }; 4157 4158 enum { 4159 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0, 4160 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1, 4161 }; 4162 4163 struct mlx5_ifc_teardown_hca_out_bits { 4164 u8 status[0x8]; 4165 u8 reserved_at_8[0x18]; 4166 4167 u8 syndrome[0x20]; 4168 4169 u8 reserved_at_40[0x3f]; 4170 4171 u8 state[0x1]; 4172 }; 4173 4174 enum { 4175 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0, 4176 MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE = 0x1, 4177 MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN = 0x2, 4178 }; 4179 4180 struct mlx5_ifc_teardown_hca_in_bits { 4181 u8 opcode[0x10]; 4182 u8 reserved_at_10[0x10]; 4183 4184 u8 reserved_at_20[0x10]; 4185 u8 op_mod[0x10]; 4186 4187 u8 reserved_at_40[0x10]; 4188 u8 profile[0x10]; 4189 4190 u8 reserved_at_60[0x20]; 4191 }; 4192 4193 struct mlx5_ifc_sqerr2rts_qp_out_bits { 4194 u8 status[0x8]; 4195 u8 reserved_at_8[0x18]; 4196 4197 u8 syndrome[0x20]; 4198 4199 u8 reserved_at_40[0x40]; 4200 }; 4201 4202 struct mlx5_ifc_sqerr2rts_qp_in_bits { 4203 u8 opcode[0x10]; 4204 u8 uid[0x10]; 4205 4206 u8 reserved_at_20[0x10]; 4207 u8 op_mod[0x10]; 4208 4209 u8 reserved_at_40[0x8]; 4210 u8 qpn[0x18]; 4211 4212 u8 reserved_at_60[0x20]; 4213 4214 u8 opt_param_mask[0x20]; 4215 4216 u8 reserved_at_a0[0x20]; 4217 4218 struct mlx5_ifc_qpc_bits qpc; 4219 4220 u8 reserved_at_800[0x80]; 4221 }; 4222 4223 struct mlx5_ifc_sqd2rts_qp_out_bits { 4224 u8 status[0x8]; 4225 u8 reserved_at_8[0x18]; 4226 4227 u8 syndrome[0x20]; 4228 4229 u8 reserved_at_40[0x40]; 4230 }; 4231 4232 struct mlx5_ifc_sqd2rts_qp_in_bits { 4233 u8 opcode[0x10]; 4234 u8 uid[0x10]; 4235 4236 u8 reserved_at_20[0x10]; 4237 u8 op_mod[0x10]; 4238 4239 u8 reserved_at_40[0x8]; 4240 u8 qpn[0x18]; 4241 4242 u8 reserved_at_60[0x20]; 4243 4244 u8 opt_param_mask[0x20]; 4245 4246 u8 reserved_at_a0[0x20]; 4247 4248 struct mlx5_ifc_qpc_bits qpc; 4249 4250 u8 reserved_at_800[0x80]; 4251 }; 4252 4253 struct mlx5_ifc_set_roce_address_out_bits { 4254 u8 status[0x8]; 4255 u8 reserved_at_8[0x18]; 4256 4257 u8 syndrome[0x20]; 4258 4259 u8 reserved_at_40[0x40]; 4260 }; 4261 4262 struct mlx5_ifc_set_roce_address_in_bits { 4263 u8 opcode[0x10]; 4264 u8 reserved_at_10[0x10]; 4265 4266 u8 reserved_at_20[0x10]; 4267 u8 op_mod[0x10]; 4268 4269 u8 roce_address_index[0x10]; 4270 u8 reserved_at_50[0xc]; 4271 u8 vhca_port_num[0x4]; 4272 4273 u8 reserved_at_60[0x20]; 4274 4275 struct mlx5_ifc_roce_addr_layout_bits roce_address; 4276 }; 4277 4278 struct mlx5_ifc_set_mad_demux_out_bits { 4279 u8 status[0x8]; 4280 u8 reserved_at_8[0x18]; 4281 4282 u8 syndrome[0x20]; 4283 4284 u8 reserved_at_40[0x40]; 4285 }; 4286 4287 enum { 4288 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0, 4289 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2, 4290 }; 4291 4292 struct mlx5_ifc_set_mad_demux_in_bits { 4293 u8 opcode[0x10]; 4294 u8 reserved_at_10[0x10]; 4295 4296 u8 reserved_at_20[0x10]; 4297 u8 op_mod[0x10]; 4298 4299 u8 reserved_at_40[0x20]; 4300 4301 u8 reserved_at_60[0x6]; 4302 u8 demux_mode[0x2]; 4303 u8 reserved_at_68[0x18]; 4304 }; 4305 4306 struct mlx5_ifc_set_l2_table_entry_out_bits { 4307 u8 status[0x8]; 4308 u8 reserved_at_8[0x18]; 4309 4310 u8 syndrome[0x20]; 4311 4312 u8 reserved_at_40[0x40]; 4313 }; 4314 4315 struct mlx5_ifc_set_l2_table_entry_in_bits { 4316 u8 opcode[0x10]; 4317 u8 reserved_at_10[0x10]; 4318 4319 u8 reserved_at_20[0x10]; 4320 u8 op_mod[0x10]; 4321 4322 u8 reserved_at_40[0x60]; 4323 4324 u8 reserved_at_a0[0x8]; 4325 u8 table_index[0x18]; 4326 4327 u8 reserved_at_c0[0x20]; 4328 4329 u8 reserved_at_e0[0x13]; 4330 u8 vlan_valid[0x1]; 4331 u8 vlan[0xc]; 4332 4333 struct mlx5_ifc_mac_address_layout_bits mac_address; 4334 4335 u8 reserved_at_140[0xc0]; 4336 }; 4337 4338 struct mlx5_ifc_set_issi_out_bits { 4339 u8 status[0x8]; 4340 u8 reserved_at_8[0x18]; 4341 4342 u8 syndrome[0x20]; 4343 4344 u8 reserved_at_40[0x40]; 4345 }; 4346 4347 struct mlx5_ifc_set_issi_in_bits { 4348 u8 opcode[0x10]; 4349 u8 reserved_at_10[0x10]; 4350 4351 u8 reserved_at_20[0x10]; 4352 u8 op_mod[0x10]; 4353 4354 u8 reserved_at_40[0x10]; 4355 u8 current_issi[0x10]; 4356 4357 u8 reserved_at_60[0x20]; 4358 }; 4359 4360 struct mlx5_ifc_set_hca_cap_out_bits { 4361 u8 status[0x8]; 4362 u8 reserved_at_8[0x18]; 4363 4364 u8 syndrome[0x20]; 4365 4366 u8 reserved_at_40[0x40]; 4367 }; 4368 4369 struct mlx5_ifc_set_hca_cap_in_bits { 4370 u8 opcode[0x10]; 4371 u8 reserved_at_10[0x10]; 4372 4373 u8 reserved_at_20[0x10]; 4374 u8 op_mod[0x10]; 4375 4376 u8 other_function[0x1]; 4377 u8 reserved_at_41[0xf]; 4378 u8 function_id[0x10]; 4379 4380 u8 reserved_at_60[0x20]; 4381 4382 union mlx5_ifc_hca_cap_union_bits capability; 4383 }; 4384 4385 enum { 4386 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0, 4387 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1, 4388 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2, 4389 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3, 4390 MLX5_SET_FTE_MODIFY_ENABLE_MASK_IPSEC_OBJ_ID = 0x4 4391 }; 4392 4393 struct mlx5_ifc_set_fte_out_bits { 4394 u8 status[0x8]; 4395 u8 reserved_at_8[0x18]; 4396 4397 u8 syndrome[0x20]; 4398 4399 u8 reserved_at_40[0x40]; 4400 }; 4401 4402 struct mlx5_ifc_set_fte_in_bits { 4403 u8 opcode[0x10]; 4404 u8 reserved_at_10[0x10]; 4405 4406 u8 reserved_at_20[0x10]; 4407 u8 op_mod[0x10]; 4408 4409 u8 other_vport[0x1]; 4410 u8 reserved_at_41[0xf]; 4411 u8 vport_number[0x10]; 4412 4413 u8 reserved_at_60[0x20]; 4414 4415 u8 table_type[0x8]; 4416 u8 reserved_at_88[0x18]; 4417 4418 u8 reserved_at_a0[0x8]; 4419 u8 table_id[0x18]; 4420 4421 u8 ignore_flow_level[0x1]; 4422 u8 reserved_at_c1[0x17]; 4423 u8 modify_enable_mask[0x8]; 4424 4425 u8 reserved_at_e0[0x20]; 4426 4427 u8 flow_index[0x20]; 4428 4429 u8 reserved_at_120[0xe0]; 4430 4431 struct mlx5_ifc_flow_context_bits flow_context; 4432 }; 4433 4434 struct mlx5_ifc_rts2rts_qp_out_bits { 4435 u8 status[0x8]; 4436 u8 reserved_at_8[0x18]; 4437 4438 u8 syndrome[0x20]; 4439 4440 u8 reserved_at_40[0x20]; 4441 u8 ece[0x20]; 4442 }; 4443 4444 struct mlx5_ifc_rts2rts_qp_in_bits { 4445 u8 opcode[0x10]; 4446 u8 uid[0x10]; 4447 4448 u8 reserved_at_20[0x10]; 4449 u8 op_mod[0x10]; 4450 4451 u8 reserved_at_40[0x8]; 4452 u8 qpn[0x18]; 4453 4454 u8 reserved_at_60[0x20]; 4455 4456 u8 opt_param_mask[0x20]; 4457 4458 u8 ece[0x20]; 4459 4460 struct mlx5_ifc_qpc_bits qpc; 4461 4462 u8 reserved_at_800[0x80]; 4463 }; 4464 4465 struct mlx5_ifc_rtr2rts_qp_out_bits { 4466 u8 status[0x8]; 4467 u8 reserved_at_8[0x18]; 4468 4469 u8 syndrome[0x20]; 4470 4471 u8 reserved_at_40[0x20]; 4472 u8 ece[0x20]; 4473 }; 4474 4475 struct mlx5_ifc_rtr2rts_qp_in_bits { 4476 u8 opcode[0x10]; 4477 u8 uid[0x10]; 4478 4479 u8 reserved_at_20[0x10]; 4480 u8 op_mod[0x10]; 4481 4482 u8 reserved_at_40[0x8]; 4483 u8 qpn[0x18]; 4484 4485 u8 reserved_at_60[0x20]; 4486 4487 u8 opt_param_mask[0x20]; 4488 4489 u8 ece[0x20]; 4490 4491 struct mlx5_ifc_qpc_bits qpc; 4492 4493 u8 reserved_at_800[0x80]; 4494 }; 4495 4496 struct mlx5_ifc_rst2init_qp_out_bits { 4497 u8 status[0x8]; 4498 u8 reserved_at_8[0x18]; 4499 4500 u8 syndrome[0x20]; 4501 4502 u8 reserved_at_40[0x20]; 4503 u8 ece[0x20]; 4504 }; 4505 4506 struct mlx5_ifc_rst2init_qp_in_bits { 4507 u8 opcode[0x10]; 4508 u8 uid[0x10]; 4509 4510 u8 reserved_at_20[0x10]; 4511 u8 op_mod[0x10]; 4512 4513 u8 reserved_at_40[0x8]; 4514 u8 qpn[0x18]; 4515 4516 u8 reserved_at_60[0x20]; 4517 4518 u8 opt_param_mask[0x20]; 4519 4520 u8 ece[0x20]; 4521 4522 struct mlx5_ifc_qpc_bits qpc; 4523 4524 u8 reserved_at_800[0x80]; 4525 }; 4526 4527 struct mlx5_ifc_query_xrq_out_bits { 4528 u8 status[0x8]; 4529 u8 reserved_at_8[0x18]; 4530 4531 u8 syndrome[0x20]; 4532 4533 u8 reserved_at_40[0x40]; 4534 4535 struct mlx5_ifc_xrqc_bits xrq_context; 4536 }; 4537 4538 struct mlx5_ifc_query_xrq_in_bits { 4539 u8 opcode[0x10]; 4540 u8 reserved_at_10[0x10]; 4541 4542 u8 reserved_at_20[0x10]; 4543 u8 op_mod[0x10]; 4544 4545 u8 reserved_at_40[0x8]; 4546 u8 xrqn[0x18]; 4547 4548 u8 reserved_at_60[0x20]; 4549 }; 4550 4551 struct mlx5_ifc_query_xrc_srq_out_bits { 4552 u8 status[0x8]; 4553 u8 reserved_at_8[0x18]; 4554 4555 u8 syndrome[0x20]; 4556 4557 u8 reserved_at_40[0x40]; 4558 4559 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 4560 4561 u8 reserved_at_280[0x600]; 4562 4563 u8 pas[][0x40]; 4564 }; 4565 4566 struct mlx5_ifc_query_xrc_srq_in_bits { 4567 u8 opcode[0x10]; 4568 u8 reserved_at_10[0x10]; 4569 4570 u8 reserved_at_20[0x10]; 4571 u8 op_mod[0x10]; 4572 4573 u8 reserved_at_40[0x8]; 4574 u8 xrc_srqn[0x18]; 4575 4576 u8 reserved_at_60[0x20]; 4577 }; 4578 4579 enum { 4580 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0, 4581 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1, 4582 }; 4583 4584 struct mlx5_ifc_query_vport_state_out_bits { 4585 u8 status[0x8]; 4586 u8 reserved_at_8[0x18]; 4587 4588 u8 syndrome[0x20]; 4589 4590 u8 reserved_at_40[0x20]; 4591 4592 u8 reserved_at_60[0x18]; 4593 u8 admin_state[0x4]; 4594 u8 state[0x4]; 4595 }; 4596 4597 enum { 4598 MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT = 0x0, 4599 MLX5_VPORT_STATE_OP_MOD_ESW_VPORT = 0x1, 4600 MLX5_VPORT_STATE_OP_MOD_UPLINK = 0x2, 4601 }; 4602 4603 struct mlx5_ifc_arm_monitor_counter_in_bits { 4604 u8 opcode[0x10]; 4605 u8 uid[0x10]; 4606 4607 u8 reserved_at_20[0x10]; 4608 u8 op_mod[0x10]; 4609 4610 u8 reserved_at_40[0x20]; 4611 4612 u8 reserved_at_60[0x20]; 4613 }; 4614 4615 struct mlx5_ifc_arm_monitor_counter_out_bits { 4616 u8 status[0x8]; 4617 u8 reserved_at_8[0x18]; 4618 4619 u8 syndrome[0x20]; 4620 4621 u8 reserved_at_40[0x40]; 4622 }; 4623 4624 enum { 4625 MLX5_QUERY_MONITOR_CNT_TYPE_PPCNT = 0x0, 4626 MLX5_QUERY_MONITOR_CNT_TYPE_Q_COUNTER = 0x1, 4627 }; 4628 4629 enum mlx5_monitor_counter_ppcnt { 4630 MLX5_QUERY_MONITOR_PPCNT_IN_RANGE_LENGTH_ERRORS = 0x0, 4631 MLX5_QUERY_MONITOR_PPCNT_OUT_OF_RANGE_LENGTH_FIELD = 0x1, 4632 MLX5_QUERY_MONITOR_PPCNT_FRAME_TOO_LONG_ERRORS = 0x2, 4633 MLX5_QUERY_MONITOR_PPCNT_FRAME_CHECK_SEQUENCE_ERRORS = 0x3, 4634 MLX5_QUERY_MONITOR_PPCNT_ALIGNMENT_ERRORS = 0x4, 4635 MLX5_QUERY_MONITOR_PPCNT_IF_OUT_DISCARDS = 0x5, 4636 }; 4637 4638 enum { 4639 MLX5_QUERY_MONITOR_Q_COUNTER_RX_OUT_OF_BUFFER = 0x4, 4640 }; 4641 4642 struct mlx5_ifc_monitor_counter_output_bits { 4643 u8 reserved_at_0[0x4]; 4644 u8 type[0x4]; 4645 u8 reserved_at_8[0x8]; 4646 u8 counter[0x10]; 4647 4648 u8 counter_group_id[0x20]; 4649 }; 4650 4651 #define MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 (6) 4652 #define MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1 (1) 4653 #define MLX5_CMD_SET_MONITOR_NUM_COUNTER (MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 +\ 4654 MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1) 4655 4656 struct mlx5_ifc_set_monitor_counter_in_bits { 4657 u8 opcode[0x10]; 4658 u8 uid[0x10]; 4659 4660 u8 reserved_at_20[0x10]; 4661 u8 op_mod[0x10]; 4662 4663 u8 reserved_at_40[0x10]; 4664 u8 num_of_counters[0x10]; 4665 4666 u8 reserved_at_60[0x20]; 4667 4668 struct mlx5_ifc_monitor_counter_output_bits monitor_counter[MLX5_CMD_SET_MONITOR_NUM_COUNTER]; 4669 }; 4670 4671 struct mlx5_ifc_set_monitor_counter_out_bits { 4672 u8 status[0x8]; 4673 u8 reserved_at_8[0x18]; 4674 4675 u8 syndrome[0x20]; 4676 4677 u8 reserved_at_40[0x40]; 4678 }; 4679 4680 struct mlx5_ifc_query_vport_state_in_bits { 4681 u8 opcode[0x10]; 4682 u8 reserved_at_10[0x10]; 4683 4684 u8 reserved_at_20[0x10]; 4685 u8 op_mod[0x10]; 4686 4687 u8 other_vport[0x1]; 4688 u8 reserved_at_41[0xf]; 4689 u8 vport_number[0x10]; 4690 4691 u8 reserved_at_60[0x20]; 4692 }; 4693 4694 struct mlx5_ifc_query_vnic_env_out_bits { 4695 u8 status[0x8]; 4696 u8 reserved_at_8[0x18]; 4697 4698 u8 syndrome[0x20]; 4699 4700 u8 reserved_at_40[0x40]; 4701 4702 struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env; 4703 }; 4704 4705 enum { 4706 MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS = 0x0, 4707 }; 4708 4709 struct mlx5_ifc_query_vnic_env_in_bits { 4710 u8 opcode[0x10]; 4711 u8 reserved_at_10[0x10]; 4712 4713 u8 reserved_at_20[0x10]; 4714 u8 op_mod[0x10]; 4715 4716 u8 other_vport[0x1]; 4717 u8 reserved_at_41[0xf]; 4718 u8 vport_number[0x10]; 4719 4720 u8 reserved_at_60[0x20]; 4721 }; 4722 4723 struct mlx5_ifc_query_vport_counter_out_bits { 4724 u8 status[0x8]; 4725 u8 reserved_at_8[0x18]; 4726 4727 u8 syndrome[0x20]; 4728 4729 u8 reserved_at_40[0x40]; 4730 4731 struct mlx5_ifc_traffic_counter_bits received_errors; 4732 4733 struct mlx5_ifc_traffic_counter_bits transmit_errors; 4734 4735 struct mlx5_ifc_traffic_counter_bits received_ib_unicast; 4736 4737 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast; 4738 4739 struct mlx5_ifc_traffic_counter_bits received_ib_multicast; 4740 4741 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast; 4742 4743 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast; 4744 4745 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast; 4746 4747 struct mlx5_ifc_traffic_counter_bits received_eth_unicast; 4748 4749 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast; 4750 4751 struct mlx5_ifc_traffic_counter_bits received_eth_multicast; 4752 4753 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast; 4754 4755 u8 reserved_at_680[0xa00]; 4756 }; 4757 4758 enum { 4759 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0, 4760 }; 4761 4762 struct mlx5_ifc_query_vport_counter_in_bits { 4763 u8 opcode[0x10]; 4764 u8 reserved_at_10[0x10]; 4765 4766 u8 reserved_at_20[0x10]; 4767 u8 op_mod[0x10]; 4768 4769 u8 other_vport[0x1]; 4770 u8 reserved_at_41[0xb]; 4771 u8 port_num[0x4]; 4772 u8 vport_number[0x10]; 4773 4774 u8 reserved_at_60[0x60]; 4775 4776 u8 clear[0x1]; 4777 u8 reserved_at_c1[0x1f]; 4778 4779 u8 reserved_at_e0[0x20]; 4780 }; 4781 4782 struct mlx5_ifc_query_tis_out_bits { 4783 u8 status[0x8]; 4784 u8 reserved_at_8[0x18]; 4785 4786 u8 syndrome[0x20]; 4787 4788 u8 reserved_at_40[0x40]; 4789 4790 struct mlx5_ifc_tisc_bits tis_context; 4791 }; 4792 4793 struct mlx5_ifc_query_tis_in_bits { 4794 u8 opcode[0x10]; 4795 u8 reserved_at_10[0x10]; 4796 4797 u8 reserved_at_20[0x10]; 4798 u8 op_mod[0x10]; 4799 4800 u8 reserved_at_40[0x8]; 4801 u8 tisn[0x18]; 4802 4803 u8 reserved_at_60[0x20]; 4804 }; 4805 4806 struct mlx5_ifc_query_tir_out_bits { 4807 u8 status[0x8]; 4808 u8 reserved_at_8[0x18]; 4809 4810 u8 syndrome[0x20]; 4811 4812 u8 reserved_at_40[0xc0]; 4813 4814 struct mlx5_ifc_tirc_bits tir_context; 4815 }; 4816 4817 struct mlx5_ifc_query_tir_in_bits { 4818 u8 opcode[0x10]; 4819 u8 reserved_at_10[0x10]; 4820 4821 u8 reserved_at_20[0x10]; 4822 u8 op_mod[0x10]; 4823 4824 u8 reserved_at_40[0x8]; 4825 u8 tirn[0x18]; 4826 4827 u8 reserved_at_60[0x20]; 4828 }; 4829 4830 struct mlx5_ifc_query_srq_out_bits { 4831 u8 status[0x8]; 4832 u8 reserved_at_8[0x18]; 4833 4834 u8 syndrome[0x20]; 4835 4836 u8 reserved_at_40[0x40]; 4837 4838 struct mlx5_ifc_srqc_bits srq_context_entry; 4839 4840 u8 reserved_at_280[0x600]; 4841 4842 u8 pas[][0x40]; 4843 }; 4844 4845 struct mlx5_ifc_query_srq_in_bits { 4846 u8 opcode[0x10]; 4847 u8 reserved_at_10[0x10]; 4848 4849 u8 reserved_at_20[0x10]; 4850 u8 op_mod[0x10]; 4851 4852 u8 reserved_at_40[0x8]; 4853 u8 srqn[0x18]; 4854 4855 u8 reserved_at_60[0x20]; 4856 }; 4857 4858 struct mlx5_ifc_query_sq_out_bits { 4859 u8 status[0x8]; 4860 u8 reserved_at_8[0x18]; 4861 4862 u8 syndrome[0x20]; 4863 4864 u8 reserved_at_40[0xc0]; 4865 4866 struct mlx5_ifc_sqc_bits sq_context; 4867 }; 4868 4869 struct mlx5_ifc_query_sq_in_bits { 4870 u8 opcode[0x10]; 4871 u8 reserved_at_10[0x10]; 4872 4873 u8 reserved_at_20[0x10]; 4874 u8 op_mod[0x10]; 4875 4876 u8 reserved_at_40[0x8]; 4877 u8 sqn[0x18]; 4878 4879 u8 reserved_at_60[0x20]; 4880 }; 4881 4882 struct mlx5_ifc_query_special_contexts_out_bits { 4883 u8 status[0x8]; 4884 u8 reserved_at_8[0x18]; 4885 4886 u8 syndrome[0x20]; 4887 4888 u8 dump_fill_mkey[0x20]; 4889 4890 u8 resd_lkey[0x20]; 4891 4892 u8 null_mkey[0x20]; 4893 4894 u8 reserved_at_a0[0x60]; 4895 }; 4896 4897 struct mlx5_ifc_query_special_contexts_in_bits { 4898 u8 opcode[0x10]; 4899 u8 reserved_at_10[0x10]; 4900 4901 u8 reserved_at_20[0x10]; 4902 u8 op_mod[0x10]; 4903 4904 u8 reserved_at_40[0x40]; 4905 }; 4906 4907 struct mlx5_ifc_query_scheduling_element_out_bits { 4908 u8 opcode[0x10]; 4909 u8 reserved_at_10[0x10]; 4910 4911 u8 reserved_at_20[0x10]; 4912 u8 op_mod[0x10]; 4913 4914 u8 reserved_at_40[0xc0]; 4915 4916 struct mlx5_ifc_scheduling_context_bits scheduling_context; 4917 4918 u8 reserved_at_300[0x100]; 4919 }; 4920 4921 enum { 4922 SCHEDULING_HIERARCHY_E_SWITCH = 0x2, 4923 SCHEDULING_HIERARCHY_NIC = 0x3, 4924 }; 4925 4926 struct mlx5_ifc_query_scheduling_element_in_bits { 4927 u8 opcode[0x10]; 4928 u8 reserved_at_10[0x10]; 4929 4930 u8 reserved_at_20[0x10]; 4931 u8 op_mod[0x10]; 4932 4933 u8 scheduling_hierarchy[0x8]; 4934 u8 reserved_at_48[0x18]; 4935 4936 u8 scheduling_element_id[0x20]; 4937 4938 u8 reserved_at_80[0x180]; 4939 }; 4940 4941 struct mlx5_ifc_query_rqt_out_bits { 4942 u8 status[0x8]; 4943 u8 reserved_at_8[0x18]; 4944 4945 u8 syndrome[0x20]; 4946 4947 u8 reserved_at_40[0xc0]; 4948 4949 struct mlx5_ifc_rqtc_bits rqt_context; 4950 }; 4951 4952 struct mlx5_ifc_query_rqt_in_bits { 4953 u8 opcode[0x10]; 4954 u8 reserved_at_10[0x10]; 4955 4956 u8 reserved_at_20[0x10]; 4957 u8 op_mod[0x10]; 4958 4959 u8 reserved_at_40[0x8]; 4960 u8 rqtn[0x18]; 4961 4962 u8 reserved_at_60[0x20]; 4963 }; 4964 4965 struct mlx5_ifc_query_rq_out_bits { 4966 u8 status[0x8]; 4967 u8 reserved_at_8[0x18]; 4968 4969 u8 syndrome[0x20]; 4970 4971 u8 reserved_at_40[0xc0]; 4972 4973 struct mlx5_ifc_rqc_bits rq_context; 4974 }; 4975 4976 struct mlx5_ifc_query_rq_in_bits { 4977 u8 opcode[0x10]; 4978 u8 reserved_at_10[0x10]; 4979 4980 u8 reserved_at_20[0x10]; 4981 u8 op_mod[0x10]; 4982 4983 u8 reserved_at_40[0x8]; 4984 u8 rqn[0x18]; 4985 4986 u8 reserved_at_60[0x20]; 4987 }; 4988 4989 struct mlx5_ifc_query_roce_address_out_bits { 4990 u8 status[0x8]; 4991 u8 reserved_at_8[0x18]; 4992 4993 u8 syndrome[0x20]; 4994 4995 u8 reserved_at_40[0x40]; 4996 4997 struct mlx5_ifc_roce_addr_layout_bits roce_address; 4998 }; 4999 5000 struct mlx5_ifc_query_roce_address_in_bits { 5001 u8 opcode[0x10]; 5002 u8 reserved_at_10[0x10]; 5003 5004 u8 reserved_at_20[0x10]; 5005 u8 op_mod[0x10]; 5006 5007 u8 roce_address_index[0x10]; 5008 u8 reserved_at_50[0xc]; 5009 u8 vhca_port_num[0x4]; 5010 5011 u8 reserved_at_60[0x20]; 5012 }; 5013 5014 struct mlx5_ifc_query_rmp_out_bits { 5015 u8 status[0x8]; 5016 u8 reserved_at_8[0x18]; 5017 5018 u8 syndrome[0x20]; 5019 5020 u8 reserved_at_40[0xc0]; 5021 5022 struct mlx5_ifc_rmpc_bits rmp_context; 5023 }; 5024 5025 struct mlx5_ifc_query_rmp_in_bits { 5026 u8 opcode[0x10]; 5027 u8 reserved_at_10[0x10]; 5028 5029 u8 reserved_at_20[0x10]; 5030 u8 op_mod[0x10]; 5031 5032 u8 reserved_at_40[0x8]; 5033 u8 rmpn[0x18]; 5034 5035 u8 reserved_at_60[0x20]; 5036 }; 5037 5038 struct mlx5_ifc_query_qp_out_bits { 5039 u8 status[0x8]; 5040 u8 reserved_at_8[0x18]; 5041 5042 u8 syndrome[0x20]; 5043 5044 u8 reserved_at_40[0x20]; 5045 u8 ece[0x20]; 5046 5047 u8 opt_param_mask[0x20]; 5048 5049 u8 reserved_at_a0[0x20]; 5050 5051 struct mlx5_ifc_qpc_bits qpc; 5052 5053 u8 reserved_at_800[0x80]; 5054 5055 u8 pas[][0x40]; 5056 }; 5057 5058 struct mlx5_ifc_query_qp_in_bits { 5059 u8 opcode[0x10]; 5060 u8 reserved_at_10[0x10]; 5061 5062 u8 reserved_at_20[0x10]; 5063 u8 op_mod[0x10]; 5064 5065 u8 reserved_at_40[0x8]; 5066 u8 qpn[0x18]; 5067 5068 u8 reserved_at_60[0x20]; 5069 }; 5070 5071 struct mlx5_ifc_query_q_counter_out_bits { 5072 u8 status[0x8]; 5073 u8 reserved_at_8[0x18]; 5074 5075 u8 syndrome[0x20]; 5076 5077 u8 reserved_at_40[0x40]; 5078 5079 u8 rx_write_requests[0x20]; 5080 5081 u8 reserved_at_a0[0x20]; 5082 5083 u8 rx_read_requests[0x20]; 5084 5085 u8 reserved_at_e0[0x20]; 5086 5087 u8 rx_atomic_requests[0x20]; 5088 5089 u8 reserved_at_120[0x20]; 5090 5091 u8 rx_dct_connect[0x20]; 5092 5093 u8 reserved_at_160[0x20]; 5094 5095 u8 out_of_buffer[0x20]; 5096 5097 u8 reserved_at_1a0[0x20]; 5098 5099 u8 out_of_sequence[0x20]; 5100 5101 u8 reserved_at_1e0[0x20]; 5102 5103 u8 duplicate_request[0x20]; 5104 5105 u8 reserved_at_220[0x20]; 5106 5107 u8 rnr_nak_retry_err[0x20]; 5108 5109 u8 reserved_at_260[0x20]; 5110 5111 u8 packet_seq_err[0x20]; 5112 5113 u8 reserved_at_2a0[0x20]; 5114 5115 u8 implied_nak_seq_err[0x20]; 5116 5117 u8 reserved_at_2e0[0x20]; 5118 5119 u8 local_ack_timeout_err[0x20]; 5120 5121 u8 reserved_at_320[0xa0]; 5122 5123 u8 resp_local_length_error[0x20]; 5124 5125 u8 req_local_length_error[0x20]; 5126 5127 u8 resp_local_qp_error[0x20]; 5128 5129 u8 local_operation_error[0x20]; 5130 5131 u8 resp_local_protection[0x20]; 5132 5133 u8 req_local_protection[0x20]; 5134 5135 u8 resp_cqe_error[0x20]; 5136 5137 u8 req_cqe_error[0x20]; 5138 5139 u8 req_mw_binding[0x20]; 5140 5141 u8 req_bad_response[0x20]; 5142 5143 u8 req_remote_invalid_request[0x20]; 5144 5145 u8 resp_remote_invalid_request[0x20]; 5146 5147 u8 req_remote_access_errors[0x20]; 5148 5149 u8 resp_remote_access_errors[0x20]; 5150 5151 u8 req_remote_operation_errors[0x20]; 5152 5153 u8 req_transport_retries_exceeded[0x20]; 5154 5155 u8 cq_overflow[0x20]; 5156 5157 u8 resp_cqe_flush_error[0x20]; 5158 5159 u8 req_cqe_flush_error[0x20]; 5160 5161 u8 reserved_at_620[0x20]; 5162 5163 u8 roce_adp_retrans[0x20]; 5164 5165 u8 roce_adp_retrans_to[0x20]; 5166 5167 u8 roce_slow_restart[0x20]; 5168 5169 u8 roce_slow_restart_cnps[0x20]; 5170 5171 u8 roce_slow_restart_trans[0x20]; 5172 5173 u8 reserved_at_6e0[0x120]; 5174 }; 5175 5176 struct mlx5_ifc_query_q_counter_in_bits { 5177 u8 opcode[0x10]; 5178 u8 reserved_at_10[0x10]; 5179 5180 u8 reserved_at_20[0x10]; 5181 u8 op_mod[0x10]; 5182 5183 u8 reserved_at_40[0x80]; 5184 5185 u8 clear[0x1]; 5186 u8 reserved_at_c1[0x1f]; 5187 5188 u8 reserved_at_e0[0x18]; 5189 u8 counter_set_id[0x8]; 5190 }; 5191 5192 struct mlx5_ifc_query_pages_out_bits { 5193 u8 status[0x8]; 5194 u8 reserved_at_8[0x18]; 5195 5196 u8 syndrome[0x20]; 5197 5198 u8 embedded_cpu_function[0x1]; 5199 u8 reserved_at_41[0xf]; 5200 u8 function_id[0x10]; 5201 5202 u8 num_pages[0x20]; 5203 }; 5204 5205 enum { 5206 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1, 5207 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2, 5208 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3, 5209 }; 5210 5211 struct mlx5_ifc_query_pages_in_bits { 5212 u8 opcode[0x10]; 5213 u8 reserved_at_10[0x10]; 5214 5215 u8 reserved_at_20[0x10]; 5216 u8 op_mod[0x10]; 5217 5218 u8 embedded_cpu_function[0x1]; 5219 u8 reserved_at_41[0xf]; 5220 u8 function_id[0x10]; 5221 5222 u8 reserved_at_60[0x20]; 5223 }; 5224 5225 struct mlx5_ifc_query_nic_vport_context_out_bits { 5226 u8 status[0x8]; 5227 u8 reserved_at_8[0x18]; 5228 5229 u8 syndrome[0x20]; 5230 5231 u8 reserved_at_40[0x40]; 5232 5233 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 5234 }; 5235 5236 struct mlx5_ifc_query_nic_vport_context_in_bits { 5237 u8 opcode[0x10]; 5238 u8 reserved_at_10[0x10]; 5239 5240 u8 reserved_at_20[0x10]; 5241 u8 op_mod[0x10]; 5242 5243 u8 other_vport[0x1]; 5244 u8 reserved_at_41[0xf]; 5245 u8 vport_number[0x10]; 5246 5247 u8 reserved_at_60[0x5]; 5248 u8 allowed_list_type[0x3]; 5249 u8 reserved_at_68[0x18]; 5250 }; 5251 5252 struct mlx5_ifc_query_mkey_out_bits { 5253 u8 status[0x8]; 5254 u8 reserved_at_8[0x18]; 5255 5256 u8 syndrome[0x20]; 5257 5258 u8 reserved_at_40[0x40]; 5259 5260 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 5261 5262 u8 reserved_at_280[0x600]; 5263 5264 u8 bsf0_klm0_pas_mtt0_1[16][0x8]; 5265 5266 u8 bsf1_klm1_pas_mtt2_3[16][0x8]; 5267 }; 5268 5269 struct mlx5_ifc_query_mkey_in_bits { 5270 u8 opcode[0x10]; 5271 u8 reserved_at_10[0x10]; 5272 5273 u8 reserved_at_20[0x10]; 5274 u8 op_mod[0x10]; 5275 5276 u8 reserved_at_40[0x8]; 5277 u8 mkey_index[0x18]; 5278 5279 u8 pg_access[0x1]; 5280 u8 reserved_at_61[0x1f]; 5281 }; 5282 5283 struct mlx5_ifc_query_mad_demux_out_bits { 5284 u8 status[0x8]; 5285 u8 reserved_at_8[0x18]; 5286 5287 u8 syndrome[0x20]; 5288 5289 u8 reserved_at_40[0x40]; 5290 5291 u8 mad_dumux_parameters_block[0x20]; 5292 }; 5293 5294 struct mlx5_ifc_query_mad_demux_in_bits { 5295 u8 opcode[0x10]; 5296 u8 reserved_at_10[0x10]; 5297 5298 u8 reserved_at_20[0x10]; 5299 u8 op_mod[0x10]; 5300 5301 u8 reserved_at_40[0x40]; 5302 }; 5303 5304 struct mlx5_ifc_query_l2_table_entry_out_bits { 5305 u8 status[0x8]; 5306 u8 reserved_at_8[0x18]; 5307 5308 u8 syndrome[0x20]; 5309 5310 u8 reserved_at_40[0xa0]; 5311 5312 u8 reserved_at_e0[0x13]; 5313 u8 vlan_valid[0x1]; 5314 u8 vlan[0xc]; 5315 5316 struct mlx5_ifc_mac_address_layout_bits mac_address; 5317 5318 u8 reserved_at_140[0xc0]; 5319 }; 5320 5321 struct mlx5_ifc_query_l2_table_entry_in_bits { 5322 u8 opcode[0x10]; 5323 u8 reserved_at_10[0x10]; 5324 5325 u8 reserved_at_20[0x10]; 5326 u8 op_mod[0x10]; 5327 5328 u8 reserved_at_40[0x60]; 5329 5330 u8 reserved_at_a0[0x8]; 5331 u8 table_index[0x18]; 5332 5333 u8 reserved_at_c0[0x140]; 5334 }; 5335 5336 struct mlx5_ifc_query_issi_out_bits { 5337 u8 status[0x8]; 5338 u8 reserved_at_8[0x18]; 5339 5340 u8 syndrome[0x20]; 5341 5342 u8 reserved_at_40[0x10]; 5343 u8 current_issi[0x10]; 5344 5345 u8 reserved_at_60[0xa0]; 5346 5347 u8 reserved_at_100[76][0x8]; 5348 u8 supported_issi_dw0[0x20]; 5349 }; 5350 5351 struct mlx5_ifc_query_issi_in_bits { 5352 u8 opcode[0x10]; 5353 u8 reserved_at_10[0x10]; 5354 5355 u8 reserved_at_20[0x10]; 5356 u8 op_mod[0x10]; 5357 5358 u8 reserved_at_40[0x40]; 5359 }; 5360 5361 struct mlx5_ifc_set_driver_version_out_bits { 5362 u8 status[0x8]; 5363 u8 reserved_0[0x18]; 5364 5365 u8 syndrome[0x20]; 5366 u8 reserved_1[0x40]; 5367 }; 5368 5369 struct mlx5_ifc_set_driver_version_in_bits { 5370 u8 opcode[0x10]; 5371 u8 reserved_0[0x10]; 5372 5373 u8 reserved_1[0x10]; 5374 u8 op_mod[0x10]; 5375 5376 u8 reserved_2[0x40]; 5377 u8 driver_version[64][0x8]; 5378 }; 5379 5380 struct mlx5_ifc_query_hca_vport_pkey_out_bits { 5381 u8 status[0x8]; 5382 u8 reserved_at_8[0x18]; 5383 5384 u8 syndrome[0x20]; 5385 5386 u8 reserved_at_40[0x40]; 5387 5388 struct mlx5_ifc_pkey_bits pkey[]; 5389 }; 5390 5391 struct mlx5_ifc_query_hca_vport_pkey_in_bits { 5392 u8 opcode[0x10]; 5393 u8 reserved_at_10[0x10]; 5394 5395 u8 reserved_at_20[0x10]; 5396 u8 op_mod[0x10]; 5397 5398 u8 other_vport[0x1]; 5399 u8 reserved_at_41[0xb]; 5400 u8 port_num[0x4]; 5401 u8 vport_number[0x10]; 5402 5403 u8 reserved_at_60[0x10]; 5404 u8 pkey_index[0x10]; 5405 }; 5406 5407 enum { 5408 MLX5_HCA_VPORT_SEL_PORT_GUID = 1 << 0, 5409 MLX5_HCA_VPORT_SEL_NODE_GUID = 1 << 1, 5410 MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2, 5411 }; 5412 5413 struct mlx5_ifc_query_hca_vport_gid_out_bits { 5414 u8 status[0x8]; 5415 u8 reserved_at_8[0x18]; 5416 5417 u8 syndrome[0x20]; 5418 5419 u8 reserved_at_40[0x20]; 5420 5421 u8 gids_num[0x10]; 5422 u8 reserved_at_70[0x10]; 5423 5424 struct mlx5_ifc_array128_auto_bits gid[]; 5425 }; 5426 5427 struct mlx5_ifc_query_hca_vport_gid_in_bits { 5428 u8 opcode[0x10]; 5429 u8 reserved_at_10[0x10]; 5430 5431 u8 reserved_at_20[0x10]; 5432 u8 op_mod[0x10]; 5433 5434 u8 other_vport[0x1]; 5435 u8 reserved_at_41[0xb]; 5436 u8 port_num[0x4]; 5437 u8 vport_number[0x10]; 5438 5439 u8 reserved_at_60[0x10]; 5440 u8 gid_index[0x10]; 5441 }; 5442 5443 struct mlx5_ifc_query_hca_vport_context_out_bits { 5444 u8 status[0x8]; 5445 u8 reserved_at_8[0x18]; 5446 5447 u8 syndrome[0x20]; 5448 5449 u8 reserved_at_40[0x40]; 5450 5451 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 5452 }; 5453 5454 struct mlx5_ifc_query_hca_vport_context_in_bits { 5455 u8 opcode[0x10]; 5456 u8 reserved_at_10[0x10]; 5457 5458 u8 reserved_at_20[0x10]; 5459 u8 op_mod[0x10]; 5460 5461 u8 other_vport[0x1]; 5462 u8 reserved_at_41[0xb]; 5463 u8 port_num[0x4]; 5464 u8 vport_number[0x10]; 5465 5466 u8 reserved_at_60[0x20]; 5467 }; 5468 5469 struct mlx5_ifc_query_hca_cap_out_bits { 5470 u8 status[0x8]; 5471 u8 reserved_at_8[0x18]; 5472 5473 u8 syndrome[0x20]; 5474 5475 u8 reserved_at_40[0x40]; 5476 5477 union mlx5_ifc_hca_cap_union_bits capability; 5478 }; 5479 5480 struct mlx5_ifc_query_hca_cap_in_bits { 5481 u8 opcode[0x10]; 5482 u8 reserved_at_10[0x10]; 5483 5484 u8 reserved_at_20[0x10]; 5485 u8 op_mod[0x10]; 5486 5487 u8 other_function[0x1]; 5488 u8 reserved_at_41[0xf]; 5489 u8 function_id[0x10]; 5490 5491 u8 reserved_at_60[0x20]; 5492 }; 5493 5494 struct mlx5_ifc_other_hca_cap_bits { 5495 u8 roce[0x1]; 5496 u8 reserved_at_1[0x27f]; 5497 }; 5498 5499 struct mlx5_ifc_query_other_hca_cap_out_bits { 5500 u8 status[0x8]; 5501 u8 reserved_at_8[0x18]; 5502 5503 u8 syndrome[0x20]; 5504 5505 u8 reserved_at_40[0x40]; 5506 5507 struct mlx5_ifc_other_hca_cap_bits other_capability; 5508 }; 5509 5510 struct mlx5_ifc_query_other_hca_cap_in_bits { 5511 u8 opcode[0x10]; 5512 u8 reserved_at_10[0x10]; 5513 5514 u8 reserved_at_20[0x10]; 5515 u8 op_mod[0x10]; 5516 5517 u8 reserved_at_40[0x10]; 5518 u8 function_id[0x10]; 5519 5520 u8 reserved_at_60[0x20]; 5521 }; 5522 5523 struct mlx5_ifc_modify_other_hca_cap_out_bits { 5524 u8 status[0x8]; 5525 u8 reserved_at_8[0x18]; 5526 5527 u8 syndrome[0x20]; 5528 5529 u8 reserved_at_40[0x40]; 5530 }; 5531 5532 struct mlx5_ifc_modify_other_hca_cap_in_bits { 5533 u8 opcode[0x10]; 5534 u8 reserved_at_10[0x10]; 5535 5536 u8 reserved_at_20[0x10]; 5537 u8 op_mod[0x10]; 5538 5539 u8 reserved_at_40[0x10]; 5540 u8 function_id[0x10]; 5541 u8 field_select[0x20]; 5542 5543 struct mlx5_ifc_other_hca_cap_bits other_capability; 5544 }; 5545 5546 struct mlx5_ifc_flow_table_context_bits { 5547 u8 reformat_en[0x1]; 5548 u8 decap_en[0x1]; 5549 u8 sw_owner[0x1]; 5550 u8 termination_table[0x1]; 5551 u8 table_miss_action[0x4]; 5552 u8 level[0x8]; 5553 u8 reserved_at_10[0x8]; 5554 u8 log_size[0x8]; 5555 5556 u8 reserved_at_20[0x8]; 5557 u8 table_miss_id[0x18]; 5558 5559 u8 reserved_at_40[0x8]; 5560 u8 lag_master_next_table_id[0x18]; 5561 5562 u8 reserved_at_60[0x60]; 5563 5564 u8 sw_owner_icm_root_1[0x40]; 5565 5566 u8 sw_owner_icm_root_0[0x40]; 5567 5568 }; 5569 5570 struct mlx5_ifc_query_flow_table_out_bits { 5571 u8 status[0x8]; 5572 u8 reserved_at_8[0x18]; 5573 5574 u8 syndrome[0x20]; 5575 5576 u8 reserved_at_40[0x80]; 5577 5578 struct mlx5_ifc_flow_table_context_bits flow_table_context; 5579 }; 5580 5581 struct mlx5_ifc_query_flow_table_in_bits { 5582 u8 opcode[0x10]; 5583 u8 reserved_at_10[0x10]; 5584 5585 u8 reserved_at_20[0x10]; 5586 u8 op_mod[0x10]; 5587 5588 u8 reserved_at_40[0x40]; 5589 5590 u8 table_type[0x8]; 5591 u8 reserved_at_88[0x18]; 5592 5593 u8 reserved_at_a0[0x8]; 5594 u8 table_id[0x18]; 5595 5596 u8 reserved_at_c0[0x140]; 5597 }; 5598 5599 struct mlx5_ifc_query_fte_out_bits { 5600 u8 status[0x8]; 5601 u8 reserved_at_8[0x18]; 5602 5603 u8 syndrome[0x20]; 5604 5605 u8 reserved_at_40[0x1c0]; 5606 5607 struct mlx5_ifc_flow_context_bits flow_context; 5608 }; 5609 5610 struct mlx5_ifc_query_fte_in_bits { 5611 u8 opcode[0x10]; 5612 u8 reserved_at_10[0x10]; 5613 5614 u8 reserved_at_20[0x10]; 5615 u8 op_mod[0x10]; 5616 5617 u8 reserved_at_40[0x40]; 5618 5619 u8 table_type[0x8]; 5620 u8 reserved_at_88[0x18]; 5621 5622 u8 reserved_at_a0[0x8]; 5623 u8 table_id[0x18]; 5624 5625 u8 reserved_at_c0[0x40]; 5626 5627 u8 flow_index[0x20]; 5628 5629 u8 reserved_at_120[0xe0]; 5630 }; 5631 5632 enum { 5633 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 5634 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 5635 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 5636 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3, 5637 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_3 = 0x4, 5638 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_4 = 0x5, 5639 }; 5640 5641 struct mlx5_ifc_query_flow_group_out_bits { 5642 u8 status[0x8]; 5643 u8 reserved_at_8[0x18]; 5644 5645 u8 syndrome[0x20]; 5646 5647 u8 reserved_at_40[0xa0]; 5648 5649 u8 start_flow_index[0x20]; 5650 5651 u8 reserved_at_100[0x20]; 5652 5653 u8 end_flow_index[0x20]; 5654 5655 u8 reserved_at_140[0xa0]; 5656 5657 u8 reserved_at_1e0[0x18]; 5658 u8 match_criteria_enable[0x8]; 5659 5660 struct mlx5_ifc_fte_match_param_bits match_criteria; 5661 5662 u8 reserved_at_1200[0xe00]; 5663 }; 5664 5665 struct mlx5_ifc_query_flow_group_in_bits { 5666 u8 opcode[0x10]; 5667 u8 reserved_at_10[0x10]; 5668 5669 u8 reserved_at_20[0x10]; 5670 u8 op_mod[0x10]; 5671 5672 u8 reserved_at_40[0x40]; 5673 5674 u8 table_type[0x8]; 5675 u8 reserved_at_88[0x18]; 5676 5677 u8 reserved_at_a0[0x8]; 5678 u8 table_id[0x18]; 5679 5680 u8 group_id[0x20]; 5681 5682 u8 reserved_at_e0[0x120]; 5683 }; 5684 5685 struct mlx5_ifc_query_flow_counter_out_bits { 5686 u8 status[0x8]; 5687 u8 reserved_at_8[0x18]; 5688 5689 u8 syndrome[0x20]; 5690 5691 u8 reserved_at_40[0x40]; 5692 5693 struct mlx5_ifc_traffic_counter_bits flow_statistics[]; 5694 }; 5695 5696 struct mlx5_ifc_query_flow_counter_in_bits { 5697 u8 opcode[0x10]; 5698 u8 reserved_at_10[0x10]; 5699 5700 u8 reserved_at_20[0x10]; 5701 u8 op_mod[0x10]; 5702 5703 u8 reserved_at_40[0x80]; 5704 5705 u8 clear[0x1]; 5706 u8 reserved_at_c1[0xf]; 5707 u8 num_of_counters[0x10]; 5708 5709 u8 flow_counter_id[0x20]; 5710 }; 5711 5712 struct mlx5_ifc_query_esw_vport_context_out_bits { 5713 u8 status[0x8]; 5714 u8 reserved_at_8[0x18]; 5715 5716 u8 syndrome[0x20]; 5717 5718 u8 reserved_at_40[0x40]; 5719 5720 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 5721 }; 5722 5723 struct mlx5_ifc_query_esw_vport_context_in_bits { 5724 u8 opcode[0x10]; 5725 u8 reserved_at_10[0x10]; 5726 5727 u8 reserved_at_20[0x10]; 5728 u8 op_mod[0x10]; 5729 5730 u8 other_vport[0x1]; 5731 u8 reserved_at_41[0xf]; 5732 u8 vport_number[0x10]; 5733 5734 u8 reserved_at_60[0x20]; 5735 }; 5736 5737 struct mlx5_ifc_modify_esw_vport_context_out_bits { 5738 u8 status[0x8]; 5739 u8 reserved_at_8[0x18]; 5740 5741 u8 syndrome[0x20]; 5742 5743 u8 reserved_at_40[0x40]; 5744 }; 5745 5746 struct mlx5_ifc_esw_vport_context_fields_select_bits { 5747 u8 reserved_at_0[0x1b]; 5748 u8 fdb_to_vport_reg_c_id[0x1]; 5749 u8 vport_cvlan_insert[0x1]; 5750 u8 vport_svlan_insert[0x1]; 5751 u8 vport_cvlan_strip[0x1]; 5752 u8 vport_svlan_strip[0x1]; 5753 }; 5754 5755 struct mlx5_ifc_modify_esw_vport_context_in_bits { 5756 u8 opcode[0x10]; 5757 u8 reserved_at_10[0x10]; 5758 5759 u8 reserved_at_20[0x10]; 5760 u8 op_mod[0x10]; 5761 5762 u8 other_vport[0x1]; 5763 u8 reserved_at_41[0xf]; 5764 u8 vport_number[0x10]; 5765 5766 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select; 5767 5768 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 5769 }; 5770 5771 struct mlx5_ifc_query_eq_out_bits { 5772 u8 status[0x8]; 5773 u8 reserved_at_8[0x18]; 5774 5775 u8 syndrome[0x20]; 5776 5777 u8 reserved_at_40[0x40]; 5778 5779 struct mlx5_ifc_eqc_bits eq_context_entry; 5780 5781 u8 reserved_at_280[0x40]; 5782 5783 u8 event_bitmask[0x40]; 5784 5785 u8 reserved_at_300[0x580]; 5786 5787 u8 pas[][0x40]; 5788 }; 5789 5790 struct mlx5_ifc_query_eq_in_bits { 5791 u8 opcode[0x10]; 5792 u8 reserved_at_10[0x10]; 5793 5794 u8 reserved_at_20[0x10]; 5795 u8 op_mod[0x10]; 5796 5797 u8 reserved_at_40[0x18]; 5798 u8 eq_number[0x8]; 5799 5800 u8 reserved_at_60[0x20]; 5801 }; 5802 5803 struct mlx5_ifc_packet_reformat_context_in_bits { 5804 u8 reformat_type[0x8]; 5805 u8 reserved_at_8[0x4]; 5806 u8 reformat_param_0[0x4]; 5807 u8 reserved_at_10[0x6]; 5808 u8 reformat_data_size[0xa]; 5809 5810 u8 reformat_param_1[0x8]; 5811 u8 reserved_at_28[0x8]; 5812 u8 reformat_data[2][0x8]; 5813 5814 u8 more_reformat_data[][0x8]; 5815 }; 5816 5817 struct mlx5_ifc_query_packet_reformat_context_out_bits { 5818 u8 status[0x8]; 5819 u8 reserved_at_8[0x18]; 5820 5821 u8 syndrome[0x20]; 5822 5823 u8 reserved_at_40[0xa0]; 5824 5825 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context[]; 5826 }; 5827 5828 struct mlx5_ifc_query_packet_reformat_context_in_bits { 5829 u8 opcode[0x10]; 5830 u8 reserved_at_10[0x10]; 5831 5832 u8 reserved_at_20[0x10]; 5833 u8 op_mod[0x10]; 5834 5835 u8 packet_reformat_id[0x20]; 5836 5837 u8 reserved_at_60[0xa0]; 5838 }; 5839 5840 struct mlx5_ifc_alloc_packet_reformat_context_out_bits { 5841 u8 status[0x8]; 5842 u8 reserved_at_8[0x18]; 5843 5844 u8 syndrome[0x20]; 5845 5846 u8 packet_reformat_id[0x20]; 5847 5848 u8 reserved_at_60[0x20]; 5849 }; 5850 5851 enum { 5852 MLX5_REFORMAT_CONTEXT_ANCHOR_MAC_START = 0x1, 5853 MLX5_REFORMAT_CONTEXT_ANCHOR_IP_START = 0x7, 5854 MLX5_REFORMAT_CONTEXT_ANCHOR_TCP_UDP_START = 0x9, 5855 }; 5856 5857 enum mlx5_reformat_ctx_type { 5858 MLX5_REFORMAT_TYPE_L2_TO_VXLAN = 0x0, 5859 MLX5_REFORMAT_TYPE_L2_TO_NVGRE = 0x1, 5860 MLX5_REFORMAT_TYPE_L2_TO_L2_TUNNEL = 0x2, 5861 MLX5_REFORMAT_TYPE_L3_TUNNEL_TO_L2 = 0x3, 5862 MLX5_REFORMAT_TYPE_L2_TO_L3_TUNNEL = 0x4, 5863 MLX5_REFORMAT_TYPE_INSERT_HDR = 0xf, 5864 MLX5_REFORMAT_TYPE_REMOVE_HDR = 0x10, 5865 }; 5866 5867 struct mlx5_ifc_alloc_packet_reformat_context_in_bits { 5868 u8 opcode[0x10]; 5869 u8 reserved_at_10[0x10]; 5870 5871 u8 reserved_at_20[0x10]; 5872 u8 op_mod[0x10]; 5873 5874 u8 reserved_at_40[0xa0]; 5875 5876 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context; 5877 }; 5878 5879 struct mlx5_ifc_dealloc_packet_reformat_context_out_bits { 5880 u8 status[0x8]; 5881 u8 reserved_at_8[0x18]; 5882 5883 u8 syndrome[0x20]; 5884 5885 u8 reserved_at_40[0x40]; 5886 }; 5887 5888 struct mlx5_ifc_dealloc_packet_reformat_context_in_bits { 5889 u8 opcode[0x10]; 5890 u8 reserved_at_10[0x10]; 5891 5892 u8 reserved_20[0x10]; 5893 u8 op_mod[0x10]; 5894 5895 u8 packet_reformat_id[0x20]; 5896 5897 u8 reserved_60[0x20]; 5898 }; 5899 5900 struct mlx5_ifc_set_action_in_bits { 5901 u8 action_type[0x4]; 5902 u8 field[0xc]; 5903 u8 reserved_at_10[0x3]; 5904 u8 offset[0x5]; 5905 u8 reserved_at_18[0x3]; 5906 u8 length[0x5]; 5907 5908 u8 data[0x20]; 5909 }; 5910 5911 struct mlx5_ifc_add_action_in_bits { 5912 u8 action_type[0x4]; 5913 u8 field[0xc]; 5914 u8 reserved_at_10[0x10]; 5915 5916 u8 data[0x20]; 5917 }; 5918 5919 struct mlx5_ifc_copy_action_in_bits { 5920 u8 action_type[0x4]; 5921 u8 src_field[0xc]; 5922 u8 reserved_at_10[0x3]; 5923 u8 src_offset[0x5]; 5924 u8 reserved_at_18[0x3]; 5925 u8 length[0x5]; 5926 5927 u8 reserved_at_20[0x4]; 5928 u8 dst_field[0xc]; 5929 u8 reserved_at_30[0x3]; 5930 u8 dst_offset[0x5]; 5931 u8 reserved_at_38[0x8]; 5932 }; 5933 5934 union mlx5_ifc_set_add_copy_action_in_auto_bits { 5935 struct mlx5_ifc_set_action_in_bits set_action_in; 5936 struct mlx5_ifc_add_action_in_bits add_action_in; 5937 struct mlx5_ifc_copy_action_in_bits copy_action_in; 5938 u8 reserved_at_0[0x40]; 5939 }; 5940 5941 enum { 5942 MLX5_ACTION_TYPE_SET = 0x1, 5943 MLX5_ACTION_TYPE_ADD = 0x2, 5944 MLX5_ACTION_TYPE_COPY = 0x3, 5945 }; 5946 5947 enum { 5948 MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16 = 0x1, 5949 MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0 = 0x2, 5950 MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE = 0x3, 5951 MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16 = 0x4, 5952 MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0 = 0x5, 5953 MLX5_ACTION_IN_FIELD_OUT_IP_DSCP = 0x6, 5954 MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS = 0x7, 5955 MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT = 0x8, 5956 MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT = 0x9, 5957 MLX5_ACTION_IN_FIELD_OUT_IP_TTL = 0xa, 5958 MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT = 0xb, 5959 MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT = 0xc, 5960 MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96 = 0xd, 5961 MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64 = 0xe, 5962 MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32 = 0xf, 5963 MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0 = 0x10, 5964 MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96 = 0x11, 5965 MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64 = 0x12, 5966 MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32 = 0x13, 5967 MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0 = 0x14, 5968 MLX5_ACTION_IN_FIELD_OUT_SIPV4 = 0x15, 5969 MLX5_ACTION_IN_FIELD_OUT_DIPV4 = 0x16, 5970 MLX5_ACTION_IN_FIELD_OUT_FIRST_VID = 0x17, 5971 MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47, 5972 MLX5_ACTION_IN_FIELD_METADATA_REG_A = 0x49, 5973 MLX5_ACTION_IN_FIELD_METADATA_REG_B = 0x50, 5974 MLX5_ACTION_IN_FIELD_METADATA_REG_C_0 = 0x51, 5975 MLX5_ACTION_IN_FIELD_METADATA_REG_C_1 = 0x52, 5976 MLX5_ACTION_IN_FIELD_METADATA_REG_C_2 = 0x53, 5977 MLX5_ACTION_IN_FIELD_METADATA_REG_C_3 = 0x54, 5978 MLX5_ACTION_IN_FIELD_METADATA_REG_C_4 = 0x55, 5979 MLX5_ACTION_IN_FIELD_METADATA_REG_C_5 = 0x56, 5980 MLX5_ACTION_IN_FIELD_METADATA_REG_C_6 = 0x57, 5981 MLX5_ACTION_IN_FIELD_METADATA_REG_C_7 = 0x58, 5982 MLX5_ACTION_IN_FIELD_OUT_TCP_SEQ_NUM = 0x59, 5983 MLX5_ACTION_IN_FIELD_OUT_TCP_ACK_NUM = 0x5B, 5984 MLX5_ACTION_IN_FIELD_IPSEC_SYNDROME = 0x5D, 5985 MLX5_ACTION_IN_FIELD_OUT_EMD_47_32 = 0x6F, 5986 MLX5_ACTION_IN_FIELD_OUT_EMD_31_0 = 0x70, 5987 }; 5988 5989 struct mlx5_ifc_alloc_modify_header_context_out_bits { 5990 u8 status[0x8]; 5991 u8 reserved_at_8[0x18]; 5992 5993 u8 syndrome[0x20]; 5994 5995 u8 modify_header_id[0x20]; 5996 5997 u8 reserved_at_60[0x20]; 5998 }; 5999 6000 struct mlx5_ifc_alloc_modify_header_context_in_bits { 6001 u8 opcode[0x10]; 6002 u8 reserved_at_10[0x10]; 6003 6004 u8 reserved_at_20[0x10]; 6005 u8 op_mod[0x10]; 6006 6007 u8 reserved_at_40[0x20]; 6008 6009 u8 table_type[0x8]; 6010 u8 reserved_at_68[0x10]; 6011 u8 num_of_actions[0x8]; 6012 6013 union mlx5_ifc_set_add_copy_action_in_auto_bits actions[]; 6014 }; 6015 6016 struct mlx5_ifc_dealloc_modify_header_context_out_bits { 6017 u8 status[0x8]; 6018 u8 reserved_at_8[0x18]; 6019 6020 u8 syndrome[0x20]; 6021 6022 u8 reserved_at_40[0x40]; 6023 }; 6024 6025 struct mlx5_ifc_dealloc_modify_header_context_in_bits { 6026 u8 opcode[0x10]; 6027 u8 reserved_at_10[0x10]; 6028 6029 u8 reserved_at_20[0x10]; 6030 u8 op_mod[0x10]; 6031 6032 u8 modify_header_id[0x20]; 6033 6034 u8 reserved_at_60[0x20]; 6035 }; 6036 6037 struct mlx5_ifc_query_modify_header_context_in_bits { 6038 u8 opcode[0x10]; 6039 u8 uid[0x10]; 6040 6041 u8 reserved_at_20[0x10]; 6042 u8 op_mod[0x10]; 6043 6044 u8 modify_header_id[0x20]; 6045 6046 u8 reserved_at_60[0xa0]; 6047 }; 6048 6049 struct mlx5_ifc_query_dct_out_bits { 6050 u8 status[0x8]; 6051 u8 reserved_at_8[0x18]; 6052 6053 u8 syndrome[0x20]; 6054 6055 u8 reserved_at_40[0x40]; 6056 6057 struct mlx5_ifc_dctc_bits dct_context_entry; 6058 6059 u8 reserved_at_280[0x180]; 6060 }; 6061 6062 struct mlx5_ifc_query_dct_in_bits { 6063 u8 opcode[0x10]; 6064 u8 reserved_at_10[0x10]; 6065 6066 u8 reserved_at_20[0x10]; 6067 u8 op_mod[0x10]; 6068 6069 u8 reserved_at_40[0x8]; 6070 u8 dctn[0x18]; 6071 6072 u8 reserved_at_60[0x20]; 6073 }; 6074 6075 struct mlx5_ifc_query_cq_out_bits { 6076 u8 status[0x8]; 6077 u8 reserved_at_8[0x18]; 6078 6079 u8 syndrome[0x20]; 6080 6081 u8 reserved_at_40[0x40]; 6082 6083 struct mlx5_ifc_cqc_bits cq_context; 6084 6085 u8 reserved_at_280[0x600]; 6086 6087 u8 pas[][0x40]; 6088 }; 6089 6090 struct mlx5_ifc_query_cq_in_bits { 6091 u8 opcode[0x10]; 6092 u8 reserved_at_10[0x10]; 6093 6094 u8 reserved_at_20[0x10]; 6095 u8 op_mod[0x10]; 6096 6097 u8 reserved_at_40[0x8]; 6098 u8 cqn[0x18]; 6099 6100 u8 reserved_at_60[0x20]; 6101 }; 6102 6103 struct mlx5_ifc_query_cong_status_out_bits { 6104 u8 status[0x8]; 6105 u8 reserved_at_8[0x18]; 6106 6107 u8 syndrome[0x20]; 6108 6109 u8 reserved_at_40[0x20]; 6110 6111 u8 enable[0x1]; 6112 u8 tag_enable[0x1]; 6113 u8 reserved_at_62[0x1e]; 6114 }; 6115 6116 struct mlx5_ifc_query_cong_status_in_bits { 6117 u8 opcode[0x10]; 6118 u8 reserved_at_10[0x10]; 6119 6120 u8 reserved_at_20[0x10]; 6121 u8 op_mod[0x10]; 6122 6123 u8 reserved_at_40[0x18]; 6124 u8 priority[0x4]; 6125 u8 cong_protocol[0x4]; 6126 6127 u8 reserved_at_60[0x20]; 6128 }; 6129 6130 struct mlx5_ifc_query_cong_statistics_out_bits { 6131 u8 status[0x8]; 6132 u8 reserved_at_8[0x18]; 6133 6134 u8 syndrome[0x20]; 6135 6136 u8 reserved_at_40[0x40]; 6137 6138 u8 rp_cur_flows[0x20]; 6139 6140 u8 sum_flows[0x20]; 6141 6142 u8 rp_cnp_ignored_high[0x20]; 6143 6144 u8 rp_cnp_ignored_low[0x20]; 6145 6146 u8 rp_cnp_handled_high[0x20]; 6147 6148 u8 rp_cnp_handled_low[0x20]; 6149 6150 u8 reserved_at_140[0x100]; 6151 6152 u8 time_stamp_high[0x20]; 6153 6154 u8 time_stamp_low[0x20]; 6155 6156 u8 accumulators_period[0x20]; 6157 6158 u8 np_ecn_marked_roce_packets_high[0x20]; 6159 6160 u8 np_ecn_marked_roce_packets_low[0x20]; 6161 6162 u8 np_cnp_sent_high[0x20]; 6163 6164 u8 np_cnp_sent_low[0x20]; 6165 6166 u8 reserved_at_320[0x560]; 6167 }; 6168 6169 struct mlx5_ifc_query_cong_statistics_in_bits { 6170 u8 opcode[0x10]; 6171 u8 reserved_at_10[0x10]; 6172 6173 u8 reserved_at_20[0x10]; 6174 u8 op_mod[0x10]; 6175 6176 u8 clear[0x1]; 6177 u8 reserved_at_41[0x1f]; 6178 6179 u8 reserved_at_60[0x20]; 6180 }; 6181 6182 struct mlx5_ifc_query_cong_params_out_bits { 6183 u8 status[0x8]; 6184 u8 reserved_at_8[0x18]; 6185 6186 u8 syndrome[0x20]; 6187 6188 u8 reserved_at_40[0x40]; 6189 6190 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 6191 }; 6192 6193 struct mlx5_ifc_query_cong_params_in_bits { 6194 u8 opcode[0x10]; 6195 u8 reserved_at_10[0x10]; 6196 6197 u8 reserved_at_20[0x10]; 6198 u8 op_mod[0x10]; 6199 6200 u8 reserved_at_40[0x1c]; 6201 u8 cong_protocol[0x4]; 6202 6203 u8 reserved_at_60[0x20]; 6204 }; 6205 6206 struct mlx5_ifc_query_adapter_out_bits { 6207 u8 status[0x8]; 6208 u8 reserved_at_8[0x18]; 6209 6210 u8 syndrome[0x20]; 6211 6212 u8 reserved_at_40[0x40]; 6213 6214 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct; 6215 }; 6216 6217 struct mlx5_ifc_query_adapter_in_bits { 6218 u8 opcode[0x10]; 6219 u8 reserved_at_10[0x10]; 6220 6221 u8 reserved_at_20[0x10]; 6222 u8 op_mod[0x10]; 6223 6224 u8 reserved_at_40[0x40]; 6225 }; 6226 6227 struct mlx5_ifc_qp_2rst_out_bits { 6228 u8 status[0x8]; 6229 u8 reserved_at_8[0x18]; 6230 6231 u8 syndrome[0x20]; 6232 6233 u8 reserved_at_40[0x40]; 6234 }; 6235 6236 struct mlx5_ifc_qp_2rst_in_bits { 6237 u8 opcode[0x10]; 6238 u8 uid[0x10]; 6239 6240 u8 reserved_at_20[0x10]; 6241 u8 op_mod[0x10]; 6242 6243 u8 reserved_at_40[0x8]; 6244 u8 qpn[0x18]; 6245 6246 u8 reserved_at_60[0x20]; 6247 }; 6248 6249 struct mlx5_ifc_qp_2err_out_bits { 6250 u8 status[0x8]; 6251 u8 reserved_at_8[0x18]; 6252 6253 u8 syndrome[0x20]; 6254 6255 u8 reserved_at_40[0x40]; 6256 }; 6257 6258 struct mlx5_ifc_qp_2err_in_bits { 6259 u8 opcode[0x10]; 6260 u8 uid[0x10]; 6261 6262 u8 reserved_at_20[0x10]; 6263 u8 op_mod[0x10]; 6264 6265 u8 reserved_at_40[0x8]; 6266 u8 qpn[0x18]; 6267 6268 u8 reserved_at_60[0x20]; 6269 }; 6270 6271 struct mlx5_ifc_page_fault_resume_out_bits { 6272 u8 status[0x8]; 6273 u8 reserved_at_8[0x18]; 6274 6275 u8 syndrome[0x20]; 6276 6277 u8 reserved_at_40[0x40]; 6278 }; 6279 6280 struct mlx5_ifc_page_fault_resume_in_bits { 6281 u8 opcode[0x10]; 6282 u8 reserved_at_10[0x10]; 6283 6284 u8 reserved_at_20[0x10]; 6285 u8 op_mod[0x10]; 6286 6287 u8 error[0x1]; 6288 u8 reserved_at_41[0x4]; 6289 u8 page_fault_type[0x3]; 6290 u8 wq_number[0x18]; 6291 6292 u8 reserved_at_60[0x8]; 6293 u8 token[0x18]; 6294 }; 6295 6296 struct mlx5_ifc_nop_out_bits { 6297 u8 status[0x8]; 6298 u8 reserved_at_8[0x18]; 6299 6300 u8 syndrome[0x20]; 6301 6302 u8 reserved_at_40[0x40]; 6303 }; 6304 6305 struct mlx5_ifc_nop_in_bits { 6306 u8 opcode[0x10]; 6307 u8 reserved_at_10[0x10]; 6308 6309 u8 reserved_at_20[0x10]; 6310 u8 op_mod[0x10]; 6311 6312 u8 reserved_at_40[0x40]; 6313 }; 6314 6315 struct mlx5_ifc_modify_vport_state_out_bits { 6316 u8 status[0x8]; 6317 u8 reserved_at_8[0x18]; 6318 6319 u8 syndrome[0x20]; 6320 6321 u8 reserved_at_40[0x40]; 6322 }; 6323 6324 struct mlx5_ifc_modify_vport_state_in_bits { 6325 u8 opcode[0x10]; 6326 u8 reserved_at_10[0x10]; 6327 6328 u8 reserved_at_20[0x10]; 6329 u8 op_mod[0x10]; 6330 6331 u8 other_vport[0x1]; 6332 u8 reserved_at_41[0xf]; 6333 u8 vport_number[0x10]; 6334 6335 u8 reserved_at_60[0x18]; 6336 u8 admin_state[0x4]; 6337 u8 reserved_at_7c[0x4]; 6338 }; 6339 6340 struct mlx5_ifc_modify_tis_out_bits { 6341 u8 status[0x8]; 6342 u8 reserved_at_8[0x18]; 6343 6344 u8 syndrome[0x20]; 6345 6346 u8 reserved_at_40[0x40]; 6347 }; 6348 6349 struct mlx5_ifc_modify_tis_bitmask_bits { 6350 u8 reserved_at_0[0x20]; 6351 6352 u8 reserved_at_20[0x1d]; 6353 u8 lag_tx_port_affinity[0x1]; 6354 u8 strict_lag_tx_port_affinity[0x1]; 6355 u8 prio[0x1]; 6356 }; 6357 6358 struct mlx5_ifc_modify_tis_in_bits { 6359 u8 opcode[0x10]; 6360 u8 uid[0x10]; 6361 6362 u8 reserved_at_20[0x10]; 6363 u8 op_mod[0x10]; 6364 6365 u8 reserved_at_40[0x8]; 6366 u8 tisn[0x18]; 6367 6368 u8 reserved_at_60[0x20]; 6369 6370 struct mlx5_ifc_modify_tis_bitmask_bits bitmask; 6371 6372 u8 reserved_at_c0[0x40]; 6373 6374 struct mlx5_ifc_tisc_bits ctx; 6375 }; 6376 6377 struct mlx5_ifc_modify_tir_bitmask_bits { 6378 u8 reserved_at_0[0x20]; 6379 6380 u8 reserved_at_20[0x1b]; 6381 u8 self_lb_en[0x1]; 6382 u8 reserved_at_3c[0x1]; 6383 u8 hash[0x1]; 6384 u8 reserved_at_3e[0x1]; 6385 u8 lro[0x1]; 6386 }; 6387 6388 struct mlx5_ifc_modify_tir_out_bits { 6389 u8 status[0x8]; 6390 u8 reserved_at_8[0x18]; 6391 6392 u8 syndrome[0x20]; 6393 6394 u8 reserved_at_40[0x40]; 6395 }; 6396 6397 struct mlx5_ifc_modify_tir_in_bits { 6398 u8 opcode[0x10]; 6399 u8 uid[0x10]; 6400 6401 u8 reserved_at_20[0x10]; 6402 u8 op_mod[0x10]; 6403 6404 u8 reserved_at_40[0x8]; 6405 u8 tirn[0x18]; 6406 6407 u8 reserved_at_60[0x20]; 6408 6409 struct mlx5_ifc_modify_tir_bitmask_bits bitmask; 6410 6411 u8 reserved_at_c0[0x40]; 6412 6413 struct mlx5_ifc_tirc_bits ctx; 6414 }; 6415 6416 struct mlx5_ifc_modify_sq_out_bits { 6417 u8 status[0x8]; 6418 u8 reserved_at_8[0x18]; 6419 6420 u8 syndrome[0x20]; 6421 6422 u8 reserved_at_40[0x40]; 6423 }; 6424 6425 struct mlx5_ifc_modify_sq_in_bits { 6426 u8 opcode[0x10]; 6427 u8 uid[0x10]; 6428 6429 u8 reserved_at_20[0x10]; 6430 u8 op_mod[0x10]; 6431 6432 u8 sq_state[0x4]; 6433 u8 reserved_at_44[0x4]; 6434 u8 sqn[0x18]; 6435 6436 u8 reserved_at_60[0x20]; 6437 6438 u8 modify_bitmask[0x40]; 6439 6440 u8 reserved_at_c0[0x40]; 6441 6442 struct mlx5_ifc_sqc_bits ctx; 6443 }; 6444 6445 struct mlx5_ifc_modify_scheduling_element_out_bits { 6446 u8 status[0x8]; 6447 u8 reserved_at_8[0x18]; 6448 6449 u8 syndrome[0x20]; 6450 6451 u8 reserved_at_40[0x1c0]; 6452 }; 6453 6454 enum { 6455 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1, 6456 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2, 6457 }; 6458 6459 struct mlx5_ifc_modify_scheduling_element_in_bits { 6460 u8 opcode[0x10]; 6461 u8 reserved_at_10[0x10]; 6462 6463 u8 reserved_at_20[0x10]; 6464 u8 op_mod[0x10]; 6465 6466 u8 scheduling_hierarchy[0x8]; 6467 u8 reserved_at_48[0x18]; 6468 6469 u8 scheduling_element_id[0x20]; 6470 6471 u8 reserved_at_80[0x20]; 6472 6473 u8 modify_bitmask[0x20]; 6474 6475 u8 reserved_at_c0[0x40]; 6476 6477 struct mlx5_ifc_scheduling_context_bits scheduling_context; 6478 6479 u8 reserved_at_300[0x100]; 6480 }; 6481 6482 struct mlx5_ifc_modify_rqt_out_bits { 6483 u8 status[0x8]; 6484 u8 reserved_at_8[0x18]; 6485 6486 u8 syndrome[0x20]; 6487 6488 u8 reserved_at_40[0x40]; 6489 }; 6490 6491 struct mlx5_ifc_rqt_bitmask_bits { 6492 u8 reserved_at_0[0x20]; 6493 6494 u8 reserved_at_20[0x1f]; 6495 u8 rqn_list[0x1]; 6496 }; 6497 6498 struct mlx5_ifc_modify_rqt_in_bits { 6499 u8 opcode[0x10]; 6500 u8 uid[0x10]; 6501 6502 u8 reserved_at_20[0x10]; 6503 u8 op_mod[0x10]; 6504 6505 u8 reserved_at_40[0x8]; 6506 u8 rqtn[0x18]; 6507 6508 u8 reserved_at_60[0x20]; 6509 6510 struct mlx5_ifc_rqt_bitmask_bits bitmask; 6511 6512 u8 reserved_at_c0[0x40]; 6513 6514 struct mlx5_ifc_rqtc_bits ctx; 6515 }; 6516 6517 struct mlx5_ifc_modify_rq_out_bits { 6518 u8 status[0x8]; 6519 u8 reserved_at_8[0x18]; 6520 6521 u8 syndrome[0x20]; 6522 6523 u8 reserved_at_40[0x40]; 6524 }; 6525 6526 enum { 6527 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1, 6528 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2, 6529 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3, 6530 }; 6531 6532 struct mlx5_ifc_modify_rq_in_bits { 6533 u8 opcode[0x10]; 6534 u8 uid[0x10]; 6535 6536 u8 reserved_at_20[0x10]; 6537 u8 op_mod[0x10]; 6538 6539 u8 rq_state[0x4]; 6540 u8 reserved_at_44[0x4]; 6541 u8 rqn[0x18]; 6542 6543 u8 reserved_at_60[0x20]; 6544 6545 u8 modify_bitmask[0x40]; 6546 6547 u8 reserved_at_c0[0x40]; 6548 6549 struct mlx5_ifc_rqc_bits ctx; 6550 }; 6551 6552 struct mlx5_ifc_modify_rmp_out_bits { 6553 u8 status[0x8]; 6554 u8 reserved_at_8[0x18]; 6555 6556 u8 syndrome[0x20]; 6557 6558 u8 reserved_at_40[0x40]; 6559 }; 6560 6561 struct mlx5_ifc_rmp_bitmask_bits { 6562 u8 reserved_at_0[0x20]; 6563 6564 u8 reserved_at_20[0x1f]; 6565 u8 lwm[0x1]; 6566 }; 6567 6568 struct mlx5_ifc_modify_rmp_in_bits { 6569 u8 opcode[0x10]; 6570 u8 uid[0x10]; 6571 6572 u8 reserved_at_20[0x10]; 6573 u8 op_mod[0x10]; 6574 6575 u8 rmp_state[0x4]; 6576 u8 reserved_at_44[0x4]; 6577 u8 rmpn[0x18]; 6578 6579 u8 reserved_at_60[0x20]; 6580 6581 struct mlx5_ifc_rmp_bitmask_bits bitmask; 6582 6583 u8 reserved_at_c0[0x40]; 6584 6585 struct mlx5_ifc_rmpc_bits ctx; 6586 }; 6587 6588 struct mlx5_ifc_modify_nic_vport_context_out_bits { 6589 u8 status[0x8]; 6590 u8 reserved_at_8[0x18]; 6591 6592 u8 syndrome[0x20]; 6593 6594 u8 reserved_at_40[0x40]; 6595 }; 6596 6597 struct mlx5_ifc_modify_nic_vport_field_select_bits { 6598 u8 reserved_at_0[0x12]; 6599 u8 affiliation[0x1]; 6600 u8 reserved_at_13[0x1]; 6601 u8 disable_uc_local_lb[0x1]; 6602 u8 disable_mc_local_lb[0x1]; 6603 u8 node_guid[0x1]; 6604 u8 port_guid[0x1]; 6605 u8 min_inline[0x1]; 6606 u8 mtu[0x1]; 6607 u8 change_event[0x1]; 6608 u8 promisc[0x1]; 6609 u8 permanent_address[0x1]; 6610 u8 addresses_list[0x1]; 6611 u8 roce_en[0x1]; 6612 u8 reserved_at_1f[0x1]; 6613 }; 6614 6615 struct mlx5_ifc_modify_nic_vport_context_in_bits { 6616 u8 opcode[0x10]; 6617 u8 reserved_at_10[0x10]; 6618 6619 u8 reserved_at_20[0x10]; 6620 u8 op_mod[0x10]; 6621 6622 u8 other_vport[0x1]; 6623 u8 reserved_at_41[0xf]; 6624 u8 vport_number[0x10]; 6625 6626 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select; 6627 6628 u8 reserved_at_80[0x780]; 6629 6630 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 6631 }; 6632 6633 struct mlx5_ifc_modify_hca_vport_context_out_bits { 6634 u8 status[0x8]; 6635 u8 reserved_at_8[0x18]; 6636 6637 u8 syndrome[0x20]; 6638 6639 u8 reserved_at_40[0x40]; 6640 }; 6641 6642 struct mlx5_ifc_modify_hca_vport_context_in_bits { 6643 u8 opcode[0x10]; 6644 u8 reserved_at_10[0x10]; 6645 6646 u8 reserved_at_20[0x10]; 6647 u8 op_mod[0x10]; 6648 6649 u8 other_vport[0x1]; 6650 u8 reserved_at_41[0xb]; 6651 u8 port_num[0x4]; 6652 u8 vport_number[0x10]; 6653 6654 u8 reserved_at_60[0x20]; 6655 6656 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 6657 }; 6658 6659 struct mlx5_ifc_modify_cq_out_bits { 6660 u8 status[0x8]; 6661 u8 reserved_at_8[0x18]; 6662 6663 u8 syndrome[0x20]; 6664 6665 u8 reserved_at_40[0x40]; 6666 }; 6667 6668 enum { 6669 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0, 6670 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1, 6671 }; 6672 6673 struct mlx5_ifc_modify_cq_in_bits { 6674 u8 opcode[0x10]; 6675 u8 uid[0x10]; 6676 6677 u8 reserved_at_20[0x10]; 6678 u8 op_mod[0x10]; 6679 6680 u8 reserved_at_40[0x8]; 6681 u8 cqn[0x18]; 6682 6683 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select; 6684 6685 struct mlx5_ifc_cqc_bits cq_context; 6686 6687 u8 reserved_at_280[0x60]; 6688 6689 u8 cq_umem_valid[0x1]; 6690 u8 reserved_at_2e1[0x1f]; 6691 6692 u8 reserved_at_300[0x580]; 6693 6694 u8 pas[][0x40]; 6695 }; 6696 6697 struct mlx5_ifc_modify_cong_status_out_bits { 6698 u8 status[0x8]; 6699 u8 reserved_at_8[0x18]; 6700 6701 u8 syndrome[0x20]; 6702 6703 u8 reserved_at_40[0x40]; 6704 }; 6705 6706 struct mlx5_ifc_modify_cong_status_in_bits { 6707 u8 opcode[0x10]; 6708 u8 reserved_at_10[0x10]; 6709 6710 u8 reserved_at_20[0x10]; 6711 u8 op_mod[0x10]; 6712 6713 u8 reserved_at_40[0x18]; 6714 u8 priority[0x4]; 6715 u8 cong_protocol[0x4]; 6716 6717 u8 enable[0x1]; 6718 u8 tag_enable[0x1]; 6719 u8 reserved_at_62[0x1e]; 6720 }; 6721 6722 struct mlx5_ifc_modify_cong_params_out_bits { 6723 u8 status[0x8]; 6724 u8 reserved_at_8[0x18]; 6725 6726 u8 syndrome[0x20]; 6727 6728 u8 reserved_at_40[0x40]; 6729 }; 6730 6731 struct mlx5_ifc_modify_cong_params_in_bits { 6732 u8 opcode[0x10]; 6733 u8 reserved_at_10[0x10]; 6734 6735 u8 reserved_at_20[0x10]; 6736 u8 op_mod[0x10]; 6737 6738 u8 reserved_at_40[0x1c]; 6739 u8 cong_protocol[0x4]; 6740 6741 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select; 6742 6743 u8 reserved_at_80[0x80]; 6744 6745 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 6746 }; 6747 6748 struct mlx5_ifc_manage_pages_out_bits { 6749 u8 status[0x8]; 6750 u8 reserved_at_8[0x18]; 6751 6752 u8 syndrome[0x20]; 6753 6754 u8 output_num_entries[0x20]; 6755 6756 u8 reserved_at_60[0x20]; 6757 6758 u8 pas[][0x40]; 6759 }; 6760 6761 enum { 6762 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL = 0x0, 6763 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS = 0x1, 6764 MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES = 0x2, 6765 }; 6766 6767 struct mlx5_ifc_manage_pages_in_bits { 6768 u8 opcode[0x10]; 6769 u8 reserved_at_10[0x10]; 6770 6771 u8 reserved_at_20[0x10]; 6772 u8 op_mod[0x10]; 6773 6774 u8 embedded_cpu_function[0x1]; 6775 u8 reserved_at_41[0xf]; 6776 u8 function_id[0x10]; 6777 6778 u8 input_num_entries[0x20]; 6779 6780 u8 pas[][0x40]; 6781 }; 6782 6783 struct mlx5_ifc_mad_ifc_out_bits { 6784 u8 status[0x8]; 6785 u8 reserved_at_8[0x18]; 6786 6787 u8 syndrome[0x20]; 6788 6789 u8 reserved_at_40[0x40]; 6790 6791 u8 response_mad_packet[256][0x8]; 6792 }; 6793 6794 struct mlx5_ifc_mad_ifc_in_bits { 6795 u8 opcode[0x10]; 6796 u8 reserved_at_10[0x10]; 6797 6798 u8 reserved_at_20[0x10]; 6799 u8 op_mod[0x10]; 6800 6801 u8 remote_lid[0x10]; 6802 u8 reserved_at_50[0x8]; 6803 u8 port[0x8]; 6804 6805 u8 reserved_at_60[0x20]; 6806 6807 u8 mad[256][0x8]; 6808 }; 6809 6810 struct mlx5_ifc_init_hca_out_bits { 6811 u8 status[0x8]; 6812 u8 reserved_at_8[0x18]; 6813 6814 u8 syndrome[0x20]; 6815 6816 u8 reserved_at_40[0x40]; 6817 }; 6818 6819 struct mlx5_ifc_init_hca_in_bits { 6820 u8 opcode[0x10]; 6821 u8 reserved_at_10[0x10]; 6822 6823 u8 reserved_at_20[0x10]; 6824 u8 op_mod[0x10]; 6825 6826 u8 reserved_at_40[0x40]; 6827 u8 sw_owner_id[4][0x20]; 6828 }; 6829 6830 struct mlx5_ifc_init2rtr_qp_out_bits { 6831 u8 status[0x8]; 6832 u8 reserved_at_8[0x18]; 6833 6834 u8 syndrome[0x20]; 6835 6836 u8 reserved_at_40[0x20]; 6837 u8 ece[0x20]; 6838 }; 6839 6840 struct mlx5_ifc_init2rtr_qp_in_bits { 6841 u8 opcode[0x10]; 6842 u8 uid[0x10]; 6843 6844 u8 reserved_at_20[0x10]; 6845 u8 op_mod[0x10]; 6846 6847 u8 reserved_at_40[0x8]; 6848 u8 qpn[0x18]; 6849 6850 u8 reserved_at_60[0x20]; 6851 6852 u8 opt_param_mask[0x20]; 6853 6854 u8 ece[0x20]; 6855 6856 struct mlx5_ifc_qpc_bits qpc; 6857 6858 u8 reserved_at_800[0x80]; 6859 }; 6860 6861 struct mlx5_ifc_init2init_qp_out_bits { 6862 u8 status[0x8]; 6863 u8 reserved_at_8[0x18]; 6864 6865 u8 syndrome[0x20]; 6866 6867 u8 reserved_at_40[0x20]; 6868 u8 ece[0x20]; 6869 }; 6870 6871 struct mlx5_ifc_init2init_qp_in_bits { 6872 u8 opcode[0x10]; 6873 u8 uid[0x10]; 6874 6875 u8 reserved_at_20[0x10]; 6876 u8 op_mod[0x10]; 6877 6878 u8 reserved_at_40[0x8]; 6879 u8 qpn[0x18]; 6880 6881 u8 reserved_at_60[0x20]; 6882 6883 u8 opt_param_mask[0x20]; 6884 6885 u8 ece[0x20]; 6886 6887 struct mlx5_ifc_qpc_bits qpc; 6888 6889 u8 reserved_at_800[0x80]; 6890 }; 6891 6892 struct mlx5_ifc_get_dropped_packet_log_out_bits { 6893 u8 status[0x8]; 6894 u8 reserved_at_8[0x18]; 6895 6896 u8 syndrome[0x20]; 6897 6898 u8 reserved_at_40[0x40]; 6899 6900 u8 packet_headers_log[128][0x8]; 6901 6902 u8 packet_syndrome[64][0x8]; 6903 }; 6904 6905 struct mlx5_ifc_get_dropped_packet_log_in_bits { 6906 u8 opcode[0x10]; 6907 u8 reserved_at_10[0x10]; 6908 6909 u8 reserved_at_20[0x10]; 6910 u8 op_mod[0x10]; 6911 6912 u8 reserved_at_40[0x40]; 6913 }; 6914 6915 struct mlx5_ifc_gen_eqe_in_bits { 6916 u8 opcode[0x10]; 6917 u8 reserved_at_10[0x10]; 6918 6919 u8 reserved_at_20[0x10]; 6920 u8 op_mod[0x10]; 6921 6922 u8 reserved_at_40[0x18]; 6923 u8 eq_number[0x8]; 6924 6925 u8 reserved_at_60[0x20]; 6926 6927 u8 eqe[64][0x8]; 6928 }; 6929 6930 struct mlx5_ifc_gen_eq_out_bits { 6931 u8 status[0x8]; 6932 u8 reserved_at_8[0x18]; 6933 6934 u8 syndrome[0x20]; 6935 6936 u8 reserved_at_40[0x40]; 6937 }; 6938 6939 struct mlx5_ifc_enable_hca_out_bits { 6940 u8 status[0x8]; 6941 u8 reserved_at_8[0x18]; 6942 6943 u8 syndrome[0x20]; 6944 6945 u8 reserved_at_40[0x20]; 6946 }; 6947 6948 struct mlx5_ifc_enable_hca_in_bits { 6949 u8 opcode[0x10]; 6950 u8 reserved_at_10[0x10]; 6951 6952 u8 reserved_at_20[0x10]; 6953 u8 op_mod[0x10]; 6954 6955 u8 embedded_cpu_function[0x1]; 6956 u8 reserved_at_41[0xf]; 6957 u8 function_id[0x10]; 6958 6959 u8 reserved_at_60[0x20]; 6960 }; 6961 6962 struct mlx5_ifc_drain_dct_out_bits { 6963 u8 status[0x8]; 6964 u8 reserved_at_8[0x18]; 6965 6966 u8 syndrome[0x20]; 6967 6968 u8 reserved_at_40[0x40]; 6969 }; 6970 6971 struct mlx5_ifc_drain_dct_in_bits { 6972 u8 opcode[0x10]; 6973 u8 uid[0x10]; 6974 6975 u8 reserved_at_20[0x10]; 6976 u8 op_mod[0x10]; 6977 6978 u8 reserved_at_40[0x8]; 6979 u8 dctn[0x18]; 6980 6981 u8 reserved_at_60[0x20]; 6982 }; 6983 6984 struct mlx5_ifc_disable_hca_out_bits { 6985 u8 status[0x8]; 6986 u8 reserved_at_8[0x18]; 6987 6988 u8 syndrome[0x20]; 6989 6990 u8 reserved_at_40[0x20]; 6991 }; 6992 6993 struct mlx5_ifc_disable_hca_in_bits { 6994 u8 opcode[0x10]; 6995 u8 reserved_at_10[0x10]; 6996 6997 u8 reserved_at_20[0x10]; 6998 u8 op_mod[0x10]; 6999 7000 u8 embedded_cpu_function[0x1]; 7001 u8 reserved_at_41[0xf]; 7002 u8 function_id[0x10]; 7003 7004 u8 reserved_at_60[0x20]; 7005 }; 7006 7007 struct mlx5_ifc_detach_from_mcg_out_bits { 7008 u8 status[0x8]; 7009 u8 reserved_at_8[0x18]; 7010 7011 u8 syndrome[0x20]; 7012 7013 u8 reserved_at_40[0x40]; 7014 }; 7015 7016 struct mlx5_ifc_detach_from_mcg_in_bits { 7017 u8 opcode[0x10]; 7018 u8 uid[0x10]; 7019 7020 u8 reserved_at_20[0x10]; 7021 u8 op_mod[0x10]; 7022 7023 u8 reserved_at_40[0x8]; 7024 u8 qpn[0x18]; 7025 7026 u8 reserved_at_60[0x20]; 7027 7028 u8 multicast_gid[16][0x8]; 7029 }; 7030 7031 struct mlx5_ifc_destroy_xrq_out_bits { 7032 u8 status[0x8]; 7033 u8 reserved_at_8[0x18]; 7034 7035 u8 syndrome[0x20]; 7036 7037 u8 reserved_at_40[0x40]; 7038 }; 7039 7040 struct mlx5_ifc_destroy_xrq_in_bits { 7041 u8 opcode[0x10]; 7042 u8 uid[0x10]; 7043 7044 u8 reserved_at_20[0x10]; 7045 u8 op_mod[0x10]; 7046 7047 u8 reserved_at_40[0x8]; 7048 u8 xrqn[0x18]; 7049 7050 u8 reserved_at_60[0x20]; 7051 }; 7052 7053 struct mlx5_ifc_destroy_xrc_srq_out_bits { 7054 u8 status[0x8]; 7055 u8 reserved_at_8[0x18]; 7056 7057 u8 syndrome[0x20]; 7058 7059 u8 reserved_at_40[0x40]; 7060 }; 7061 7062 struct mlx5_ifc_destroy_xrc_srq_in_bits { 7063 u8 opcode[0x10]; 7064 u8 uid[0x10]; 7065 7066 u8 reserved_at_20[0x10]; 7067 u8 op_mod[0x10]; 7068 7069 u8 reserved_at_40[0x8]; 7070 u8 xrc_srqn[0x18]; 7071 7072 u8 reserved_at_60[0x20]; 7073 }; 7074 7075 struct mlx5_ifc_destroy_tis_out_bits { 7076 u8 status[0x8]; 7077 u8 reserved_at_8[0x18]; 7078 7079 u8 syndrome[0x20]; 7080 7081 u8 reserved_at_40[0x40]; 7082 }; 7083 7084 struct mlx5_ifc_destroy_tis_in_bits { 7085 u8 opcode[0x10]; 7086 u8 uid[0x10]; 7087 7088 u8 reserved_at_20[0x10]; 7089 u8 op_mod[0x10]; 7090 7091 u8 reserved_at_40[0x8]; 7092 u8 tisn[0x18]; 7093 7094 u8 reserved_at_60[0x20]; 7095 }; 7096 7097 struct mlx5_ifc_destroy_tir_out_bits { 7098 u8 status[0x8]; 7099 u8 reserved_at_8[0x18]; 7100 7101 u8 syndrome[0x20]; 7102 7103 u8 reserved_at_40[0x40]; 7104 }; 7105 7106 struct mlx5_ifc_destroy_tir_in_bits { 7107 u8 opcode[0x10]; 7108 u8 uid[0x10]; 7109 7110 u8 reserved_at_20[0x10]; 7111 u8 op_mod[0x10]; 7112 7113 u8 reserved_at_40[0x8]; 7114 u8 tirn[0x18]; 7115 7116 u8 reserved_at_60[0x20]; 7117 }; 7118 7119 struct mlx5_ifc_destroy_srq_out_bits { 7120 u8 status[0x8]; 7121 u8 reserved_at_8[0x18]; 7122 7123 u8 syndrome[0x20]; 7124 7125 u8 reserved_at_40[0x40]; 7126 }; 7127 7128 struct mlx5_ifc_destroy_srq_in_bits { 7129 u8 opcode[0x10]; 7130 u8 uid[0x10]; 7131 7132 u8 reserved_at_20[0x10]; 7133 u8 op_mod[0x10]; 7134 7135 u8 reserved_at_40[0x8]; 7136 u8 srqn[0x18]; 7137 7138 u8 reserved_at_60[0x20]; 7139 }; 7140 7141 struct mlx5_ifc_destroy_sq_out_bits { 7142 u8 status[0x8]; 7143 u8 reserved_at_8[0x18]; 7144 7145 u8 syndrome[0x20]; 7146 7147 u8 reserved_at_40[0x40]; 7148 }; 7149 7150 struct mlx5_ifc_destroy_sq_in_bits { 7151 u8 opcode[0x10]; 7152 u8 uid[0x10]; 7153 7154 u8 reserved_at_20[0x10]; 7155 u8 op_mod[0x10]; 7156 7157 u8 reserved_at_40[0x8]; 7158 u8 sqn[0x18]; 7159 7160 u8 reserved_at_60[0x20]; 7161 }; 7162 7163 struct mlx5_ifc_destroy_scheduling_element_out_bits { 7164 u8 status[0x8]; 7165 u8 reserved_at_8[0x18]; 7166 7167 u8 syndrome[0x20]; 7168 7169 u8 reserved_at_40[0x1c0]; 7170 }; 7171 7172 struct mlx5_ifc_destroy_scheduling_element_in_bits { 7173 u8 opcode[0x10]; 7174 u8 reserved_at_10[0x10]; 7175 7176 u8 reserved_at_20[0x10]; 7177 u8 op_mod[0x10]; 7178 7179 u8 scheduling_hierarchy[0x8]; 7180 u8 reserved_at_48[0x18]; 7181 7182 u8 scheduling_element_id[0x20]; 7183 7184 u8 reserved_at_80[0x180]; 7185 }; 7186 7187 struct mlx5_ifc_destroy_rqt_out_bits { 7188 u8 status[0x8]; 7189 u8 reserved_at_8[0x18]; 7190 7191 u8 syndrome[0x20]; 7192 7193 u8 reserved_at_40[0x40]; 7194 }; 7195 7196 struct mlx5_ifc_destroy_rqt_in_bits { 7197 u8 opcode[0x10]; 7198 u8 uid[0x10]; 7199 7200 u8 reserved_at_20[0x10]; 7201 u8 op_mod[0x10]; 7202 7203 u8 reserved_at_40[0x8]; 7204 u8 rqtn[0x18]; 7205 7206 u8 reserved_at_60[0x20]; 7207 }; 7208 7209 struct mlx5_ifc_destroy_rq_out_bits { 7210 u8 status[0x8]; 7211 u8 reserved_at_8[0x18]; 7212 7213 u8 syndrome[0x20]; 7214 7215 u8 reserved_at_40[0x40]; 7216 }; 7217 7218 struct mlx5_ifc_destroy_rq_in_bits { 7219 u8 opcode[0x10]; 7220 u8 uid[0x10]; 7221 7222 u8 reserved_at_20[0x10]; 7223 u8 op_mod[0x10]; 7224 7225 u8 reserved_at_40[0x8]; 7226 u8 rqn[0x18]; 7227 7228 u8 reserved_at_60[0x20]; 7229 }; 7230 7231 struct mlx5_ifc_set_delay_drop_params_in_bits { 7232 u8 opcode[0x10]; 7233 u8 reserved_at_10[0x10]; 7234 7235 u8 reserved_at_20[0x10]; 7236 u8 op_mod[0x10]; 7237 7238 u8 reserved_at_40[0x20]; 7239 7240 u8 reserved_at_60[0x10]; 7241 u8 delay_drop_timeout[0x10]; 7242 }; 7243 7244 struct mlx5_ifc_set_delay_drop_params_out_bits { 7245 u8 status[0x8]; 7246 u8 reserved_at_8[0x18]; 7247 7248 u8 syndrome[0x20]; 7249 7250 u8 reserved_at_40[0x40]; 7251 }; 7252 7253 struct mlx5_ifc_destroy_rmp_out_bits { 7254 u8 status[0x8]; 7255 u8 reserved_at_8[0x18]; 7256 7257 u8 syndrome[0x20]; 7258 7259 u8 reserved_at_40[0x40]; 7260 }; 7261 7262 struct mlx5_ifc_destroy_rmp_in_bits { 7263 u8 opcode[0x10]; 7264 u8 uid[0x10]; 7265 7266 u8 reserved_at_20[0x10]; 7267 u8 op_mod[0x10]; 7268 7269 u8 reserved_at_40[0x8]; 7270 u8 rmpn[0x18]; 7271 7272 u8 reserved_at_60[0x20]; 7273 }; 7274 7275 struct mlx5_ifc_destroy_qp_out_bits { 7276 u8 status[0x8]; 7277 u8 reserved_at_8[0x18]; 7278 7279 u8 syndrome[0x20]; 7280 7281 u8 reserved_at_40[0x40]; 7282 }; 7283 7284 struct mlx5_ifc_destroy_qp_in_bits { 7285 u8 opcode[0x10]; 7286 u8 uid[0x10]; 7287 7288 u8 reserved_at_20[0x10]; 7289 u8 op_mod[0x10]; 7290 7291 u8 reserved_at_40[0x8]; 7292 u8 qpn[0x18]; 7293 7294 u8 reserved_at_60[0x20]; 7295 }; 7296 7297 struct mlx5_ifc_destroy_psv_out_bits { 7298 u8 status[0x8]; 7299 u8 reserved_at_8[0x18]; 7300 7301 u8 syndrome[0x20]; 7302 7303 u8 reserved_at_40[0x40]; 7304 }; 7305 7306 struct mlx5_ifc_destroy_psv_in_bits { 7307 u8 opcode[0x10]; 7308 u8 reserved_at_10[0x10]; 7309 7310 u8 reserved_at_20[0x10]; 7311 u8 op_mod[0x10]; 7312 7313 u8 reserved_at_40[0x8]; 7314 u8 psvn[0x18]; 7315 7316 u8 reserved_at_60[0x20]; 7317 }; 7318 7319 struct mlx5_ifc_destroy_mkey_out_bits { 7320 u8 status[0x8]; 7321 u8 reserved_at_8[0x18]; 7322 7323 u8 syndrome[0x20]; 7324 7325 u8 reserved_at_40[0x40]; 7326 }; 7327 7328 struct mlx5_ifc_destroy_mkey_in_bits { 7329 u8 opcode[0x10]; 7330 u8 uid[0x10]; 7331 7332 u8 reserved_at_20[0x10]; 7333 u8 op_mod[0x10]; 7334 7335 u8 reserved_at_40[0x8]; 7336 u8 mkey_index[0x18]; 7337 7338 u8 reserved_at_60[0x20]; 7339 }; 7340 7341 struct mlx5_ifc_destroy_flow_table_out_bits { 7342 u8 status[0x8]; 7343 u8 reserved_at_8[0x18]; 7344 7345 u8 syndrome[0x20]; 7346 7347 u8 reserved_at_40[0x40]; 7348 }; 7349 7350 struct mlx5_ifc_destroy_flow_table_in_bits { 7351 u8 opcode[0x10]; 7352 u8 reserved_at_10[0x10]; 7353 7354 u8 reserved_at_20[0x10]; 7355 u8 op_mod[0x10]; 7356 7357 u8 other_vport[0x1]; 7358 u8 reserved_at_41[0xf]; 7359 u8 vport_number[0x10]; 7360 7361 u8 reserved_at_60[0x20]; 7362 7363 u8 table_type[0x8]; 7364 u8 reserved_at_88[0x18]; 7365 7366 u8 reserved_at_a0[0x8]; 7367 u8 table_id[0x18]; 7368 7369 u8 reserved_at_c0[0x140]; 7370 }; 7371 7372 struct mlx5_ifc_destroy_flow_group_out_bits { 7373 u8 status[0x8]; 7374 u8 reserved_at_8[0x18]; 7375 7376 u8 syndrome[0x20]; 7377 7378 u8 reserved_at_40[0x40]; 7379 }; 7380 7381 struct mlx5_ifc_destroy_flow_group_in_bits { 7382 u8 opcode[0x10]; 7383 u8 reserved_at_10[0x10]; 7384 7385 u8 reserved_at_20[0x10]; 7386 u8 op_mod[0x10]; 7387 7388 u8 other_vport[0x1]; 7389 u8 reserved_at_41[0xf]; 7390 u8 vport_number[0x10]; 7391 7392 u8 reserved_at_60[0x20]; 7393 7394 u8 table_type[0x8]; 7395 u8 reserved_at_88[0x18]; 7396 7397 u8 reserved_at_a0[0x8]; 7398 u8 table_id[0x18]; 7399 7400 u8 group_id[0x20]; 7401 7402 u8 reserved_at_e0[0x120]; 7403 }; 7404 7405 struct mlx5_ifc_destroy_eq_out_bits { 7406 u8 status[0x8]; 7407 u8 reserved_at_8[0x18]; 7408 7409 u8 syndrome[0x20]; 7410 7411 u8 reserved_at_40[0x40]; 7412 }; 7413 7414 struct mlx5_ifc_destroy_eq_in_bits { 7415 u8 opcode[0x10]; 7416 u8 reserved_at_10[0x10]; 7417 7418 u8 reserved_at_20[0x10]; 7419 u8 op_mod[0x10]; 7420 7421 u8 reserved_at_40[0x18]; 7422 u8 eq_number[0x8]; 7423 7424 u8 reserved_at_60[0x20]; 7425 }; 7426 7427 struct mlx5_ifc_destroy_dct_out_bits { 7428 u8 status[0x8]; 7429 u8 reserved_at_8[0x18]; 7430 7431 u8 syndrome[0x20]; 7432 7433 u8 reserved_at_40[0x40]; 7434 }; 7435 7436 struct mlx5_ifc_destroy_dct_in_bits { 7437 u8 opcode[0x10]; 7438 u8 uid[0x10]; 7439 7440 u8 reserved_at_20[0x10]; 7441 u8 op_mod[0x10]; 7442 7443 u8 reserved_at_40[0x8]; 7444 u8 dctn[0x18]; 7445 7446 u8 reserved_at_60[0x20]; 7447 }; 7448 7449 struct mlx5_ifc_destroy_cq_out_bits { 7450 u8 status[0x8]; 7451 u8 reserved_at_8[0x18]; 7452 7453 u8 syndrome[0x20]; 7454 7455 u8 reserved_at_40[0x40]; 7456 }; 7457 7458 struct mlx5_ifc_destroy_cq_in_bits { 7459 u8 opcode[0x10]; 7460 u8 uid[0x10]; 7461 7462 u8 reserved_at_20[0x10]; 7463 u8 op_mod[0x10]; 7464 7465 u8 reserved_at_40[0x8]; 7466 u8 cqn[0x18]; 7467 7468 u8 reserved_at_60[0x20]; 7469 }; 7470 7471 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits { 7472 u8 status[0x8]; 7473 u8 reserved_at_8[0x18]; 7474 7475 u8 syndrome[0x20]; 7476 7477 u8 reserved_at_40[0x40]; 7478 }; 7479 7480 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits { 7481 u8 opcode[0x10]; 7482 u8 reserved_at_10[0x10]; 7483 7484 u8 reserved_at_20[0x10]; 7485 u8 op_mod[0x10]; 7486 7487 u8 reserved_at_40[0x20]; 7488 7489 u8 reserved_at_60[0x10]; 7490 u8 vxlan_udp_port[0x10]; 7491 }; 7492 7493 struct mlx5_ifc_delete_l2_table_entry_out_bits { 7494 u8 status[0x8]; 7495 u8 reserved_at_8[0x18]; 7496 7497 u8 syndrome[0x20]; 7498 7499 u8 reserved_at_40[0x40]; 7500 }; 7501 7502 struct mlx5_ifc_delete_l2_table_entry_in_bits { 7503 u8 opcode[0x10]; 7504 u8 reserved_at_10[0x10]; 7505 7506 u8 reserved_at_20[0x10]; 7507 u8 op_mod[0x10]; 7508 7509 u8 reserved_at_40[0x60]; 7510 7511 u8 reserved_at_a0[0x8]; 7512 u8 table_index[0x18]; 7513 7514 u8 reserved_at_c0[0x140]; 7515 }; 7516 7517 struct mlx5_ifc_delete_fte_out_bits { 7518 u8 status[0x8]; 7519 u8 reserved_at_8[0x18]; 7520 7521 u8 syndrome[0x20]; 7522 7523 u8 reserved_at_40[0x40]; 7524 }; 7525 7526 struct mlx5_ifc_delete_fte_in_bits { 7527 u8 opcode[0x10]; 7528 u8 reserved_at_10[0x10]; 7529 7530 u8 reserved_at_20[0x10]; 7531 u8 op_mod[0x10]; 7532 7533 u8 other_vport[0x1]; 7534 u8 reserved_at_41[0xf]; 7535 u8 vport_number[0x10]; 7536 7537 u8 reserved_at_60[0x20]; 7538 7539 u8 table_type[0x8]; 7540 u8 reserved_at_88[0x18]; 7541 7542 u8 reserved_at_a0[0x8]; 7543 u8 table_id[0x18]; 7544 7545 u8 reserved_at_c0[0x40]; 7546 7547 u8 flow_index[0x20]; 7548 7549 u8 reserved_at_120[0xe0]; 7550 }; 7551 7552 struct mlx5_ifc_dealloc_xrcd_out_bits { 7553 u8 status[0x8]; 7554 u8 reserved_at_8[0x18]; 7555 7556 u8 syndrome[0x20]; 7557 7558 u8 reserved_at_40[0x40]; 7559 }; 7560 7561 struct mlx5_ifc_dealloc_xrcd_in_bits { 7562 u8 opcode[0x10]; 7563 u8 uid[0x10]; 7564 7565 u8 reserved_at_20[0x10]; 7566 u8 op_mod[0x10]; 7567 7568 u8 reserved_at_40[0x8]; 7569 u8 xrcd[0x18]; 7570 7571 u8 reserved_at_60[0x20]; 7572 }; 7573 7574 struct mlx5_ifc_dealloc_uar_out_bits { 7575 u8 status[0x8]; 7576 u8 reserved_at_8[0x18]; 7577 7578 u8 syndrome[0x20]; 7579 7580 u8 reserved_at_40[0x40]; 7581 }; 7582 7583 struct mlx5_ifc_dealloc_uar_in_bits { 7584 u8 opcode[0x10]; 7585 u8 reserved_at_10[0x10]; 7586 7587 u8 reserved_at_20[0x10]; 7588 u8 op_mod[0x10]; 7589 7590 u8 reserved_at_40[0x8]; 7591 u8 uar[0x18]; 7592 7593 u8 reserved_at_60[0x20]; 7594 }; 7595 7596 struct mlx5_ifc_dealloc_transport_domain_out_bits { 7597 u8 status[0x8]; 7598 u8 reserved_at_8[0x18]; 7599 7600 u8 syndrome[0x20]; 7601 7602 u8 reserved_at_40[0x40]; 7603 }; 7604 7605 struct mlx5_ifc_dealloc_transport_domain_in_bits { 7606 u8 opcode[0x10]; 7607 u8 uid[0x10]; 7608 7609 u8 reserved_at_20[0x10]; 7610 u8 op_mod[0x10]; 7611 7612 u8 reserved_at_40[0x8]; 7613 u8 transport_domain[0x18]; 7614 7615 u8 reserved_at_60[0x20]; 7616 }; 7617 7618 struct mlx5_ifc_dealloc_q_counter_out_bits { 7619 u8 status[0x8]; 7620 u8 reserved_at_8[0x18]; 7621 7622 u8 syndrome[0x20]; 7623 7624 u8 reserved_at_40[0x40]; 7625 }; 7626 7627 struct mlx5_ifc_dealloc_q_counter_in_bits { 7628 u8 opcode[0x10]; 7629 u8 reserved_at_10[0x10]; 7630 7631 u8 reserved_at_20[0x10]; 7632 u8 op_mod[0x10]; 7633 7634 u8 reserved_at_40[0x18]; 7635 u8 counter_set_id[0x8]; 7636 7637 u8 reserved_at_60[0x20]; 7638 }; 7639 7640 struct mlx5_ifc_dealloc_pd_out_bits { 7641 u8 status[0x8]; 7642 u8 reserved_at_8[0x18]; 7643 7644 u8 syndrome[0x20]; 7645 7646 u8 reserved_at_40[0x40]; 7647 }; 7648 7649 struct mlx5_ifc_dealloc_pd_in_bits { 7650 u8 opcode[0x10]; 7651 u8 uid[0x10]; 7652 7653 u8 reserved_at_20[0x10]; 7654 u8 op_mod[0x10]; 7655 7656 u8 reserved_at_40[0x8]; 7657 u8 pd[0x18]; 7658 7659 u8 reserved_at_60[0x20]; 7660 }; 7661 7662 struct mlx5_ifc_dealloc_flow_counter_out_bits { 7663 u8 status[0x8]; 7664 u8 reserved_at_8[0x18]; 7665 7666 u8 syndrome[0x20]; 7667 7668 u8 reserved_at_40[0x40]; 7669 }; 7670 7671 struct mlx5_ifc_dealloc_flow_counter_in_bits { 7672 u8 opcode[0x10]; 7673 u8 reserved_at_10[0x10]; 7674 7675 u8 reserved_at_20[0x10]; 7676 u8 op_mod[0x10]; 7677 7678 u8 flow_counter_id[0x20]; 7679 7680 u8 reserved_at_60[0x20]; 7681 }; 7682 7683 struct mlx5_ifc_create_xrq_out_bits { 7684 u8 status[0x8]; 7685 u8 reserved_at_8[0x18]; 7686 7687 u8 syndrome[0x20]; 7688 7689 u8 reserved_at_40[0x8]; 7690 u8 xrqn[0x18]; 7691 7692 u8 reserved_at_60[0x20]; 7693 }; 7694 7695 struct mlx5_ifc_create_xrq_in_bits { 7696 u8 opcode[0x10]; 7697 u8 uid[0x10]; 7698 7699 u8 reserved_at_20[0x10]; 7700 u8 op_mod[0x10]; 7701 7702 u8 reserved_at_40[0x40]; 7703 7704 struct mlx5_ifc_xrqc_bits xrq_context; 7705 }; 7706 7707 struct mlx5_ifc_create_xrc_srq_out_bits { 7708 u8 status[0x8]; 7709 u8 reserved_at_8[0x18]; 7710 7711 u8 syndrome[0x20]; 7712 7713 u8 reserved_at_40[0x8]; 7714 u8 xrc_srqn[0x18]; 7715 7716 u8 reserved_at_60[0x20]; 7717 }; 7718 7719 struct mlx5_ifc_create_xrc_srq_in_bits { 7720 u8 opcode[0x10]; 7721 u8 uid[0x10]; 7722 7723 u8 reserved_at_20[0x10]; 7724 u8 op_mod[0x10]; 7725 7726 u8 reserved_at_40[0x40]; 7727 7728 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 7729 7730 u8 reserved_at_280[0x60]; 7731 7732 u8 xrc_srq_umem_valid[0x1]; 7733 u8 reserved_at_2e1[0x1f]; 7734 7735 u8 reserved_at_300[0x580]; 7736 7737 u8 pas[][0x40]; 7738 }; 7739 7740 struct mlx5_ifc_create_tis_out_bits { 7741 u8 status[0x8]; 7742 u8 reserved_at_8[0x18]; 7743 7744 u8 syndrome[0x20]; 7745 7746 u8 reserved_at_40[0x8]; 7747 u8 tisn[0x18]; 7748 7749 u8 reserved_at_60[0x20]; 7750 }; 7751 7752 struct mlx5_ifc_create_tis_in_bits { 7753 u8 opcode[0x10]; 7754 u8 uid[0x10]; 7755 7756 u8 reserved_at_20[0x10]; 7757 u8 op_mod[0x10]; 7758 7759 u8 reserved_at_40[0xc0]; 7760 7761 struct mlx5_ifc_tisc_bits ctx; 7762 }; 7763 7764 struct mlx5_ifc_create_tir_out_bits { 7765 u8 status[0x8]; 7766 u8 icm_address_63_40[0x18]; 7767 7768 u8 syndrome[0x20]; 7769 7770 u8 icm_address_39_32[0x8]; 7771 u8 tirn[0x18]; 7772 7773 u8 icm_address_31_0[0x20]; 7774 }; 7775 7776 struct mlx5_ifc_create_tir_in_bits { 7777 u8 opcode[0x10]; 7778 u8 uid[0x10]; 7779 7780 u8 reserved_at_20[0x10]; 7781 u8 op_mod[0x10]; 7782 7783 u8 reserved_at_40[0xc0]; 7784 7785 struct mlx5_ifc_tirc_bits ctx; 7786 }; 7787 7788 struct mlx5_ifc_create_srq_out_bits { 7789 u8 status[0x8]; 7790 u8 reserved_at_8[0x18]; 7791 7792 u8 syndrome[0x20]; 7793 7794 u8 reserved_at_40[0x8]; 7795 u8 srqn[0x18]; 7796 7797 u8 reserved_at_60[0x20]; 7798 }; 7799 7800 struct mlx5_ifc_create_srq_in_bits { 7801 u8 opcode[0x10]; 7802 u8 uid[0x10]; 7803 7804 u8 reserved_at_20[0x10]; 7805 u8 op_mod[0x10]; 7806 7807 u8 reserved_at_40[0x40]; 7808 7809 struct mlx5_ifc_srqc_bits srq_context_entry; 7810 7811 u8 reserved_at_280[0x600]; 7812 7813 u8 pas[][0x40]; 7814 }; 7815 7816 struct mlx5_ifc_create_sq_out_bits { 7817 u8 status[0x8]; 7818 u8 reserved_at_8[0x18]; 7819 7820 u8 syndrome[0x20]; 7821 7822 u8 reserved_at_40[0x8]; 7823 u8 sqn[0x18]; 7824 7825 u8 reserved_at_60[0x20]; 7826 }; 7827 7828 struct mlx5_ifc_create_sq_in_bits { 7829 u8 opcode[0x10]; 7830 u8 uid[0x10]; 7831 7832 u8 reserved_at_20[0x10]; 7833 u8 op_mod[0x10]; 7834 7835 u8 reserved_at_40[0xc0]; 7836 7837 struct mlx5_ifc_sqc_bits ctx; 7838 }; 7839 7840 struct mlx5_ifc_create_scheduling_element_out_bits { 7841 u8 status[0x8]; 7842 u8 reserved_at_8[0x18]; 7843 7844 u8 syndrome[0x20]; 7845 7846 u8 reserved_at_40[0x40]; 7847 7848 u8 scheduling_element_id[0x20]; 7849 7850 u8 reserved_at_a0[0x160]; 7851 }; 7852 7853 struct mlx5_ifc_create_scheduling_element_in_bits { 7854 u8 opcode[0x10]; 7855 u8 reserved_at_10[0x10]; 7856 7857 u8 reserved_at_20[0x10]; 7858 u8 op_mod[0x10]; 7859 7860 u8 scheduling_hierarchy[0x8]; 7861 u8 reserved_at_48[0x18]; 7862 7863 u8 reserved_at_60[0xa0]; 7864 7865 struct mlx5_ifc_scheduling_context_bits scheduling_context; 7866 7867 u8 reserved_at_300[0x100]; 7868 }; 7869 7870 struct mlx5_ifc_create_rqt_out_bits { 7871 u8 status[0x8]; 7872 u8 reserved_at_8[0x18]; 7873 7874 u8 syndrome[0x20]; 7875 7876 u8 reserved_at_40[0x8]; 7877 u8 rqtn[0x18]; 7878 7879 u8 reserved_at_60[0x20]; 7880 }; 7881 7882 struct mlx5_ifc_create_rqt_in_bits { 7883 u8 opcode[0x10]; 7884 u8 uid[0x10]; 7885 7886 u8 reserved_at_20[0x10]; 7887 u8 op_mod[0x10]; 7888 7889 u8 reserved_at_40[0xc0]; 7890 7891 struct mlx5_ifc_rqtc_bits rqt_context; 7892 }; 7893 7894 struct mlx5_ifc_create_rq_out_bits { 7895 u8 status[0x8]; 7896 u8 reserved_at_8[0x18]; 7897 7898 u8 syndrome[0x20]; 7899 7900 u8 reserved_at_40[0x8]; 7901 u8 rqn[0x18]; 7902 7903 u8 reserved_at_60[0x20]; 7904 }; 7905 7906 struct mlx5_ifc_create_rq_in_bits { 7907 u8 opcode[0x10]; 7908 u8 uid[0x10]; 7909 7910 u8 reserved_at_20[0x10]; 7911 u8 op_mod[0x10]; 7912 7913 u8 reserved_at_40[0xc0]; 7914 7915 struct mlx5_ifc_rqc_bits ctx; 7916 }; 7917 7918 struct mlx5_ifc_create_rmp_out_bits { 7919 u8 status[0x8]; 7920 u8 reserved_at_8[0x18]; 7921 7922 u8 syndrome[0x20]; 7923 7924 u8 reserved_at_40[0x8]; 7925 u8 rmpn[0x18]; 7926 7927 u8 reserved_at_60[0x20]; 7928 }; 7929 7930 struct mlx5_ifc_create_rmp_in_bits { 7931 u8 opcode[0x10]; 7932 u8 uid[0x10]; 7933 7934 u8 reserved_at_20[0x10]; 7935 u8 op_mod[0x10]; 7936 7937 u8 reserved_at_40[0xc0]; 7938 7939 struct mlx5_ifc_rmpc_bits ctx; 7940 }; 7941 7942 struct mlx5_ifc_create_qp_out_bits { 7943 u8 status[0x8]; 7944 u8 reserved_at_8[0x18]; 7945 7946 u8 syndrome[0x20]; 7947 7948 u8 reserved_at_40[0x8]; 7949 u8 qpn[0x18]; 7950 7951 u8 ece[0x20]; 7952 }; 7953 7954 struct mlx5_ifc_create_qp_in_bits { 7955 u8 opcode[0x10]; 7956 u8 uid[0x10]; 7957 7958 u8 reserved_at_20[0x10]; 7959 u8 op_mod[0x10]; 7960 7961 u8 reserved_at_40[0x8]; 7962 u8 input_qpn[0x18]; 7963 7964 u8 reserved_at_60[0x20]; 7965 u8 opt_param_mask[0x20]; 7966 7967 u8 ece[0x20]; 7968 7969 struct mlx5_ifc_qpc_bits qpc; 7970 7971 u8 reserved_at_800[0x60]; 7972 7973 u8 wq_umem_valid[0x1]; 7974 u8 reserved_at_861[0x1f]; 7975 7976 u8 pas[][0x40]; 7977 }; 7978 7979 struct mlx5_ifc_create_psv_out_bits { 7980 u8 status[0x8]; 7981 u8 reserved_at_8[0x18]; 7982 7983 u8 syndrome[0x20]; 7984 7985 u8 reserved_at_40[0x40]; 7986 7987 u8 reserved_at_80[0x8]; 7988 u8 psv0_index[0x18]; 7989 7990 u8 reserved_at_a0[0x8]; 7991 u8 psv1_index[0x18]; 7992 7993 u8 reserved_at_c0[0x8]; 7994 u8 psv2_index[0x18]; 7995 7996 u8 reserved_at_e0[0x8]; 7997 u8 psv3_index[0x18]; 7998 }; 7999 8000 struct mlx5_ifc_create_psv_in_bits { 8001 u8 opcode[0x10]; 8002 u8 reserved_at_10[0x10]; 8003 8004 u8 reserved_at_20[0x10]; 8005 u8 op_mod[0x10]; 8006 8007 u8 num_psv[0x4]; 8008 u8 reserved_at_44[0x4]; 8009 u8 pd[0x18]; 8010 8011 u8 reserved_at_60[0x20]; 8012 }; 8013 8014 struct mlx5_ifc_create_mkey_out_bits { 8015 u8 status[0x8]; 8016 u8 reserved_at_8[0x18]; 8017 8018 u8 syndrome[0x20]; 8019 8020 u8 reserved_at_40[0x8]; 8021 u8 mkey_index[0x18]; 8022 8023 u8 reserved_at_60[0x20]; 8024 }; 8025 8026 struct mlx5_ifc_create_mkey_in_bits { 8027 u8 opcode[0x10]; 8028 u8 uid[0x10]; 8029 8030 u8 reserved_at_20[0x10]; 8031 u8 op_mod[0x10]; 8032 8033 u8 reserved_at_40[0x20]; 8034 8035 u8 pg_access[0x1]; 8036 u8 mkey_umem_valid[0x1]; 8037 u8 reserved_at_62[0x1e]; 8038 8039 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 8040 8041 u8 reserved_at_280[0x80]; 8042 8043 u8 translations_octword_actual_size[0x20]; 8044 8045 u8 reserved_at_320[0x560]; 8046 8047 u8 klm_pas_mtt[][0x20]; 8048 }; 8049 8050 enum { 8051 MLX5_FLOW_TABLE_TYPE_NIC_RX = 0x0, 8052 MLX5_FLOW_TABLE_TYPE_NIC_TX = 0x1, 8053 MLX5_FLOW_TABLE_TYPE_ESW_EGRESS_ACL = 0x2, 8054 MLX5_FLOW_TABLE_TYPE_ESW_INGRESS_ACL = 0x3, 8055 MLX5_FLOW_TABLE_TYPE_FDB = 0X4, 8056 MLX5_FLOW_TABLE_TYPE_SNIFFER_RX = 0X5, 8057 MLX5_FLOW_TABLE_TYPE_SNIFFER_TX = 0X6, 8058 }; 8059 8060 struct mlx5_ifc_create_flow_table_out_bits { 8061 u8 status[0x8]; 8062 u8 icm_address_63_40[0x18]; 8063 8064 u8 syndrome[0x20]; 8065 8066 u8 icm_address_39_32[0x8]; 8067 u8 table_id[0x18]; 8068 8069 u8 icm_address_31_0[0x20]; 8070 }; 8071 8072 struct mlx5_ifc_create_flow_table_in_bits { 8073 u8 opcode[0x10]; 8074 u8 reserved_at_10[0x10]; 8075 8076 u8 reserved_at_20[0x10]; 8077 u8 op_mod[0x10]; 8078 8079 u8 other_vport[0x1]; 8080 u8 reserved_at_41[0xf]; 8081 u8 vport_number[0x10]; 8082 8083 u8 reserved_at_60[0x20]; 8084 8085 u8 table_type[0x8]; 8086 u8 reserved_at_88[0x18]; 8087 8088 u8 reserved_at_a0[0x20]; 8089 8090 struct mlx5_ifc_flow_table_context_bits flow_table_context; 8091 }; 8092 8093 struct mlx5_ifc_create_flow_group_out_bits { 8094 u8 status[0x8]; 8095 u8 reserved_at_8[0x18]; 8096 8097 u8 syndrome[0x20]; 8098 8099 u8 reserved_at_40[0x8]; 8100 u8 group_id[0x18]; 8101 8102 u8 reserved_at_60[0x20]; 8103 }; 8104 8105 enum { 8106 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 8107 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 8108 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 8109 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3, 8110 }; 8111 8112 struct mlx5_ifc_create_flow_group_in_bits { 8113 u8 opcode[0x10]; 8114 u8 reserved_at_10[0x10]; 8115 8116 u8 reserved_at_20[0x10]; 8117 u8 op_mod[0x10]; 8118 8119 u8 other_vport[0x1]; 8120 u8 reserved_at_41[0xf]; 8121 u8 vport_number[0x10]; 8122 8123 u8 reserved_at_60[0x20]; 8124 8125 u8 table_type[0x8]; 8126 u8 reserved_at_88[0x18]; 8127 8128 u8 reserved_at_a0[0x8]; 8129 u8 table_id[0x18]; 8130 8131 u8 source_eswitch_owner_vhca_id_valid[0x1]; 8132 8133 u8 reserved_at_c1[0x1f]; 8134 8135 u8 start_flow_index[0x20]; 8136 8137 u8 reserved_at_100[0x20]; 8138 8139 u8 end_flow_index[0x20]; 8140 8141 u8 reserved_at_140[0xa0]; 8142 8143 u8 reserved_at_1e0[0x18]; 8144 u8 match_criteria_enable[0x8]; 8145 8146 struct mlx5_ifc_fte_match_param_bits match_criteria; 8147 8148 u8 reserved_at_1200[0xe00]; 8149 }; 8150 8151 struct mlx5_ifc_create_eq_out_bits { 8152 u8 status[0x8]; 8153 u8 reserved_at_8[0x18]; 8154 8155 u8 syndrome[0x20]; 8156 8157 u8 reserved_at_40[0x18]; 8158 u8 eq_number[0x8]; 8159 8160 u8 reserved_at_60[0x20]; 8161 }; 8162 8163 struct mlx5_ifc_create_eq_in_bits { 8164 u8 opcode[0x10]; 8165 u8 uid[0x10]; 8166 8167 u8 reserved_at_20[0x10]; 8168 u8 op_mod[0x10]; 8169 8170 u8 reserved_at_40[0x40]; 8171 8172 struct mlx5_ifc_eqc_bits eq_context_entry; 8173 8174 u8 reserved_at_280[0x40]; 8175 8176 u8 event_bitmask[4][0x40]; 8177 8178 u8 reserved_at_3c0[0x4c0]; 8179 8180 u8 pas[][0x40]; 8181 }; 8182 8183 struct mlx5_ifc_create_dct_out_bits { 8184 u8 status[0x8]; 8185 u8 reserved_at_8[0x18]; 8186 8187 u8 syndrome[0x20]; 8188 8189 u8 reserved_at_40[0x8]; 8190 u8 dctn[0x18]; 8191 8192 u8 ece[0x20]; 8193 }; 8194 8195 struct mlx5_ifc_create_dct_in_bits { 8196 u8 opcode[0x10]; 8197 u8 uid[0x10]; 8198 8199 u8 reserved_at_20[0x10]; 8200 u8 op_mod[0x10]; 8201 8202 u8 reserved_at_40[0x40]; 8203 8204 struct mlx5_ifc_dctc_bits dct_context_entry; 8205 8206 u8 reserved_at_280[0x180]; 8207 }; 8208 8209 struct mlx5_ifc_create_cq_out_bits { 8210 u8 status[0x8]; 8211 u8 reserved_at_8[0x18]; 8212 8213 u8 syndrome[0x20]; 8214 8215 u8 reserved_at_40[0x8]; 8216 u8 cqn[0x18]; 8217 8218 u8 reserved_at_60[0x20]; 8219 }; 8220 8221 struct mlx5_ifc_create_cq_in_bits { 8222 u8 opcode[0x10]; 8223 u8 uid[0x10]; 8224 8225 u8 reserved_at_20[0x10]; 8226 u8 op_mod[0x10]; 8227 8228 u8 reserved_at_40[0x40]; 8229 8230 struct mlx5_ifc_cqc_bits cq_context; 8231 8232 u8 reserved_at_280[0x60]; 8233 8234 u8 cq_umem_valid[0x1]; 8235 u8 reserved_at_2e1[0x59f]; 8236 8237 u8 pas[][0x40]; 8238 }; 8239 8240 struct mlx5_ifc_config_int_moderation_out_bits { 8241 u8 status[0x8]; 8242 u8 reserved_at_8[0x18]; 8243 8244 u8 syndrome[0x20]; 8245 8246 u8 reserved_at_40[0x4]; 8247 u8 min_delay[0xc]; 8248 u8 int_vector[0x10]; 8249 8250 u8 reserved_at_60[0x20]; 8251 }; 8252 8253 enum { 8254 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0, 8255 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1, 8256 }; 8257 8258 struct mlx5_ifc_config_int_moderation_in_bits { 8259 u8 opcode[0x10]; 8260 u8 reserved_at_10[0x10]; 8261 8262 u8 reserved_at_20[0x10]; 8263 u8 op_mod[0x10]; 8264 8265 u8 reserved_at_40[0x4]; 8266 u8 min_delay[0xc]; 8267 u8 int_vector[0x10]; 8268 8269 u8 reserved_at_60[0x20]; 8270 }; 8271 8272 struct mlx5_ifc_attach_to_mcg_out_bits { 8273 u8 status[0x8]; 8274 u8 reserved_at_8[0x18]; 8275 8276 u8 syndrome[0x20]; 8277 8278 u8 reserved_at_40[0x40]; 8279 }; 8280 8281 struct mlx5_ifc_attach_to_mcg_in_bits { 8282 u8 opcode[0x10]; 8283 u8 uid[0x10]; 8284 8285 u8 reserved_at_20[0x10]; 8286 u8 op_mod[0x10]; 8287 8288 u8 reserved_at_40[0x8]; 8289 u8 qpn[0x18]; 8290 8291 u8 reserved_at_60[0x20]; 8292 8293 u8 multicast_gid[16][0x8]; 8294 }; 8295 8296 struct mlx5_ifc_arm_xrq_out_bits { 8297 u8 status[0x8]; 8298 u8 reserved_at_8[0x18]; 8299 8300 u8 syndrome[0x20]; 8301 8302 u8 reserved_at_40[0x40]; 8303 }; 8304 8305 struct mlx5_ifc_arm_xrq_in_bits { 8306 u8 opcode[0x10]; 8307 u8 reserved_at_10[0x10]; 8308 8309 u8 reserved_at_20[0x10]; 8310 u8 op_mod[0x10]; 8311 8312 u8 reserved_at_40[0x8]; 8313 u8 xrqn[0x18]; 8314 8315 u8 reserved_at_60[0x10]; 8316 u8 lwm[0x10]; 8317 }; 8318 8319 struct mlx5_ifc_arm_xrc_srq_out_bits { 8320 u8 status[0x8]; 8321 u8 reserved_at_8[0x18]; 8322 8323 u8 syndrome[0x20]; 8324 8325 u8 reserved_at_40[0x40]; 8326 }; 8327 8328 enum { 8329 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1, 8330 }; 8331 8332 struct mlx5_ifc_arm_xrc_srq_in_bits { 8333 u8 opcode[0x10]; 8334 u8 uid[0x10]; 8335 8336 u8 reserved_at_20[0x10]; 8337 u8 op_mod[0x10]; 8338 8339 u8 reserved_at_40[0x8]; 8340 u8 xrc_srqn[0x18]; 8341 8342 u8 reserved_at_60[0x10]; 8343 u8 lwm[0x10]; 8344 }; 8345 8346 struct mlx5_ifc_arm_rq_out_bits { 8347 u8 status[0x8]; 8348 u8 reserved_at_8[0x18]; 8349 8350 u8 syndrome[0x20]; 8351 8352 u8 reserved_at_40[0x40]; 8353 }; 8354 8355 enum { 8356 MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1, 8357 MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2, 8358 }; 8359 8360 struct mlx5_ifc_arm_rq_in_bits { 8361 u8 opcode[0x10]; 8362 u8 uid[0x10]; 8363 8364 u8 reserved_at_20[0x10]; 8365 u8 op_mod[0x10]; 8366 8367 u8 reserved_at_40[0x8]; 8368 u8 srq_number[0x18]; 8369 8370 u8 reserved_at_60[0x10]; 8371 u8 lwm[0x10]; 8372 }; 8373 8374 struct mlx5_ifc_arm_dct_out_bits { 8375 u8 status[0x8]; 8376 u8 reserved_at_8[0x18]; 8377 8378 u8 syndrome[0x20]; 8379 8380 u8 reserved_at_40[0x40]; 8381 }; 8382 8383 struct mlx5_ifc_arm_dct_in_bits { 8384 u8 opcode[0x10]; 8385 u8 reserved_at_10[0x10]; 8386 8387 u8 reserved_at_20[0x10]; 8388 u8 op_mod[0x10]; 8389 8390 u8 reserved_at_40[0x8]; 8391 u8 dct_number[0x18]; 8392 8393 u8 reserved_at_60[0x20]; 8394 }; 8395 8396 struct mlx5_ifc_alloc_xrcd_out_bits { 8397 u8 status[0x8]; 8398 u8 reserved_at_8[0x18]; 8399 8400 u8 syndrome[0x20]; 8401 8402 u8 reserved_at_40[0x8]; 8403 u8 xrcd[0x18]; 8404 8405 u8 reserved_at_60[0x20]; 8406 }; 8407 8408 struct mlx5_ifc_alloc_xrcd_in_bits { 8409 u8 opcode[0x10]; 8410 u8 uid[0x10]; 8411 8412 u8 reserved_at_20[0x10]; 8413 u8 op_mod[0x10]; 8414 8415 u8 reserved_at_40[0x40]; 8416 }; 8417 8418 struct mlx5_ifc_alloc_uar_out_bits { 8419 u8 status[0x8]; 8420 u8 reserved_at_8[0x18]; 8421 8422 u8 syndrome[0x20]; 8423 8424 u8 reserved_at_40[0x8]; 8425 u8 uar[0x18]; 8426 8427 u8 reserved_at_60[0x20]; 8428 }; 8429 8430 struct mlx5_ifc_alloc_uar_in_bits { 8431 u8 opcode[0x10]; 8432 u8 reserved_at_10[0x10]; 8433 8434 u8 reserved_at_20[0x10]; 8435 u8 op_mod[0x10]; 8436 8437 u8 reserved_at_40[0x40]; 8438 }; 8439 8440 struct mlx5_ifc_alloc_transport_domain_out_bits { 8441 u8 status[0x8]; 8442 u8 reserved_at_8[0x18]; 8443 8444 u8 syndrome[0x20]; 8445 8446 u8 reserved_at_40[0x8]; 8447 u8 transport_domain[0x18]; 8448 8449 u8 reserved_at_60[0x20]; 8450 }; 8451 8452 struct mlx5_ifc_alloc_transport_domain_in_bits { 8453 u8 opcode[0x10]; 8454 u8 uid[0x10]; 8455 8456 u8 reserved_at_20[0x10]; 8457 u8 op_mod[0x10]; 8458 8459 u8 reserved_at_40[0x40]; 8460 }; 8461 8462 struct mlx5_ifc_alloc_q_counter_out_bits { 8463 u8 status[0x8]; 8464 u8 reserved_at_8[0x18]; 8465 8466 u8 syndrome[0x20]; 8467 8468 u8 reserved_at_40[0x18]; 8469 u8 counter_set_id[0x8]; 8470 8471 u8 reserved_at_60[0x20]; 8472 }; 8473 8474 struct mlx5_ifc_alloc_q_counter_in_bits { 8475 u8 opcode[0x10]; 8476 u8 uid[0x10]; 8477 8478 u8 reserved_at_20[0x10]; 8479 u8 op_mod[0x10]; 8480 8481 u8 reserved_at_40[0x40]; 8482 }; 8483 8484 struct mlx5_ifc_alloc_pd_out_bits { 8485 u8 status[0x8]; 8486 u8 reserved_at_8[0x18]; 8487 8488 u8 syndrome[0x20]; 8489 8490 u8 reserved_at_40[0x8]; 8491 u8 pd[0x18]; 8492 8493 u8 reserved_at_60[0x20]; 8494 }; 8495 8496 struct mlx5_ifc_alloc_pd_in_bits { 8497 u8 opcode[0x10]; 8498 u8 uid[0x10]; 8499 8500 u8 reserved_at_20[0x10]; 8501 u8 op_mod[0x10]; 8502 8503 u8 reserved_at_40[0x40]; 8504 }; 8505 8506 struct mlx5_ifc_alloc_flow_counter_out_bits { 8507 u8 status[0x8]; 8508 u8 reserved_at_8[0x18]; 8509 8510 u8 syndrome[0x20]; 8511 8512 u8 flow_counter_id[0x20]; 8513 8514 u8 reserved_at_60[0x20]; 8515 }; 8516 8517 struct mlx5_ifc_alloc_flow_counter_in_bits { 8518 u8 opcode[0x10]; 8519 u8 reserved_at_10[0x10]; 8520 8521 u8 reserved_at_20[0x10]; 8522 u8 op_mod[0x10]; 8523 8524 u8 reserved_at_40[0x38]; 8525 u8 flow_counter_bulk[0x8]; 8526 }; 8527 8528 struct mlx5_ifc_add_vxlan_udp_dport_out_bits { 8529 u8 status[0x8]; 8530 u8 reserved_at_8[0x18]; 8531 8532 u8 syndrome[0x20]; 8533 8534 u8 reserved_at_40[0x40]; 8535 }; 8536 8537 struct mlx5_ifc_add_vxlan_udp_dport_in_bits { 8538 u8 opcode[0x10]; 8539 u8 reserved_at_10[0x10]; 8540 8541 u8 reserved_at_20[0x10]; 8542 u8 op_mod[0x10]; 8543 8544 u8 reserved_at_40[0x20]; 8545 8546 u8 reserved_at_60[0x10]; 8547 u8 vxlan_udp_port[0x10]; 8548 }; 8549 8550 struct mlx5_ifc_set_pp_rate_limit_out_bits { 8551 u8 status[0x8]; 8552 u8 reserved_at_8[0x18]; 8553 8554 u8 syndrome[0x20]; 8555 8556 u8 reserved_at_40[0x40]; 8557 }; 8558 8559 struct mlx5_ifc_set_pp_rate_limit_context_bits { 8560 u8 rate_limit[0x20]; 8561 8562 u8 burst_upper_bound[0x20]; 8563 8564 u8 reserved_at_40[0x10]; 8565 u8 typical_packet_size[0x10]; 8566 8567 u8 reserved_at_60[0x120]; 8568 }; 8569 8570 struct mlx5_ifc_set_pp_rate_limit_in_bits { 8571 u8 opcode[0x10]; 8572 u8 uid[0x10]; 8573 8574 u8 reserved_at_20[0x10]; 8575 u8 op_mod[0x10]; 8576 8577 u8 reserved_at_40[0x10]; 8578 u8 rate_limit_index[0x10]; 8579 8580 u8 reserved_at_60[0x20]; 8581 8582 struct mlx5_ifc_set_pp_rate_limit_context_bits ctx; 8583 }; 8584 8585 struct mlx5_ifc_access_register_out_bits { 8586 u8 status[0x8]; 8587 u8 reserved_at_8[0x18]; 8588 8589 u8 syndrome[0x20]; 8590 8591 u8 reserved_at_40[0x40]; 8592 8593 u8 register_data[][0x20]; 8594 }; 8595 8596 enum { 8597 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0, 8598 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1, 8599 }; 8600 8601 struct mlx5_ifc_access_register_in_bits { 8602 u8 opcode[0x10]; 8603 u8 reserved_at_10[0x10]; 8604 8605 u8 reserved_at_20[0x10]; 8606 u8 op_mod[0x10]; 8607 8608 u8 reserved_at_40[0x10]; 8609 u8 register_id[0x10]; 8610 8611 u8 argument[0x20]; 8612 8613 u8 register_data[][0x20]; 8614 }; 8615 8616 struct mlx5_ifc_sltp_reg_bits { 8617 u8 status[0x4]; 8618 u8 version[0x4]; 8619 u8 local_port[0x8]; 8620 u8 pnat[0x2]; 8621 u8 reserved_at_12[0x2]; 8622 u8 lane[0x4]; 8623 u8 reserved_at_18[0x8]; 8624 8625 u8 reserved_at_20[0x20]; 8626 8627 u8 reserved_at_40[0x7]; 8628 u8 polarity[0x1]; 8629 u8 ob_tap0[0x8]; 8630 u8 ob_tap1[0x8]; 8631 u8 ob_tap2[0x8]; 8632 8633 u8 reserved_at_60[0xc]; 8634 u8 ob_preemp_mode[0x4]; 8635 u8 ob_reg[0x8]; 8636 u8 ob_bias[0x8]; 8637 8638 u8 reserved_at_80[0x20]; 8639 }; 8640 8641 struct mlx5_ifc_slrg_reg_bits { 8642 u8 status[0x4]; 8643 u8 version[0x4]; 8644 u8 local_port[0x8]; 8645 u8 pnat[0x2]; 8646 u8 reserved_at_12[0x2]; 8647 u8 lane[0x4]; 8648 u8 reserved_at_18[0x8]; 8649 8650 u8 time_to_link_up[0x10]; 8651 u8 reserved_at_30[0xc]; 8652 u8 grade_lane_speed[0x4]; 8653 8654 u8 grade_version[0x8]; 8655 u8 grade[0x18]; 8656 8657 u8 reserved_at_60[0x4]; 8658 u8 height_grade_type[0x4]; 8659 u8 height_grade[0x18]; 8660 8661 u8 height_dz[0x10]; 8662 u8 height_dv[0x10]; 8663 8664 u8 reserved_at_a0[0x10]; 8665 u8 height_sigma[0x10]; 8666 8667 u8 reserved_at_c0[0x20]; 8668 8669 u8 reserved_at_e0[0x4]; 8670 u8 phase_grade_type[0x4]; 8671 u8 phase_grade[0x18]; 8672 8673 u8 reserved_at_100[0x8]; 8674 u8 phase_eo_pos[0x8]; 8675 u8 reserved_at_110[0x8]; 8676 u8 phase_eo_neg[0x8]; 8677 8678 u8 ffe_set_tested[0x10]; 8679 u8 test_errors_per_lane[0x10]; 8680 }; 8681 8682 struct mlx5_ifc_pvlc_reg_bits { 8683 u8 reserved_at_0[0x8]; 8684 u8 local_port[0x8]; 8685 u8 reserved_at_10[0x10]; 8686 8687 u8 reserved_at_20[0x1c]; 8688 u8 vl_hw_cap[0x4]; 8689 8690 u8 reserved_at_40[0x1c]; 8691 u8 vl_admin[0x4]; 8692 8693 u8 reserved_at_60[0x1c]; 8694 u8 vl_operational[0x4]; 8695 }; 8696 8697 struct mlx5_ifc_pude_reg_bits { 8698 u8 swid[0x8]; 8699 u8 local_port[0x8]; 8700 u8 reserved_at_10[0x4]; 8701 u8 admin_status[0x4]; 8702 u8 reserved_at_18[0x4]; 8703 u8 oper_status[0x4]; 8704 8705 u8 reserved_at_20[0x60]; 8706 }; 8707 8708 struct mlx5_ifc_ptys_reg_bits { 8709 u8 reserved_at_0[0x1]; 8710 u8 an_disable_admin[0x1]; 8711 u8 an_disable_cap[0x1]; 8712 u8 reserved_at_3[0x5]; 8713 u8 local_port[0x8]; 8714 u8 reserved_at_10[0xd]; 8715 u8 proto_mask[0x3]; 8716 8717 u8 an_status[0x4]; 8718 u8 reserved_at_24[0xc]; 8719 u8 data_rate_oper[0x10]; 8720 8721 u8 ext_eth_proto_capability[0x20]; 8722 8723 u8 eth_proto_capability[0x20]; 8724 8725 u8 ib_link_width_capability[0x10]; 8726 u8 ib_proto_capability[0x10]; 8727 8728 u8 ext_eth_proto_admin[0x20]; 8729 8730 u8 eth_proto_admin[0x20]; 8731 8732 u8 ib_link_width_admin[0x10]; 8733 u8 ib_proto_admin[0x10]; 8734 8735 u8 ext_eth_proto_oper[0x20]; 8736 8737 u8 eth_proto_oper[0x20]; 8738 8739 u8 ib_link_width_oper[0x10]; 8740 u8 ib_proto_oper[0x10]; 8741 8742 u8 reserved_at_160[0x1c]; 8743 u8 connector_type[0x4]; 8744 8745 u8 eth_proto_lp_advertise[0x20]; 8746 8747 u8 reserved_at_1a0[0x60]; 8748 }; 8749 8750 struct mlx5_ifc_mlcr_reg_bits { 8751 u8 reserved_at_0[0x8]; 8752 u8 local_port[0x8]; 8753 u8 reserved_at_10[0x20]; 8754 8755 u8 beacon_duration[0x10]; 8756 u8 reserved_at_40[0x10]; 8757 8758 u8 beacon_remain[0x10]; 8759 }; 8760 8761 struct mlx5_ifc_ptas_reg_bits { 8762 u8 reserved_at_0[0x20]; 8763 8764 u8 algorithm_options[0x10]; 8765 u8 reserved_at_30[0x4]; 8766 u8 repetitions_mode[0x4]; 8767 u8 num_of_repetitions[0x8]; 8768 8769 u8 grade_version[0x8]; 8770 u8 height_grade_type[0x4]; 8771 u8 phase_grade_type[0x4]; 8772 u8 height_grade_weight[0x8]; 8773 u8 phase_grade_weight[0x8]; 8774 8775 u8 gisim_measure_bits[0x10]; 8776 u8 adaptive_tap_measure_bits[0x10]; 8777 8778 u8 ber_bath_high_error_threshold[0x10]; 8779 u8 ber_bath_mid_error_threshold[0x10]; 8780 8781 u8 ber_bath_low_error_threshold[0x10]; 8782 u8 one_ratio_high_threshold[0x10]; 8783 8784 u8 one_ratio_high_mid_threshold[0x10]; 8785 u8 one_ratio_low_mid_threshold[0x10]; 8786 8787 u8 one_ratio_low_threshold[0x10]; 8788 u8 ndeo_error_threshold[0x10]; 8789 8790 u8 mixer_offset_step_size[0x10]; 8791 u8 reserved_at_110[0x8]; 8792 u8 mix90_phase_for_voltage_bath[0x8]; 8793 8794 u8 mixer_offset_start[0x10]; 8795 u8 mixer_offset_end[0x10]; 8796 8797 u8 reserved_at_140[0x15]; 8798 u8 ber_test_time[0xb]; 8799 }; 8800 8801 struct mlx5_ifc_pspa_reg_bits { 8802 u8 swid[0x8]; 8803 u8 local_port[0x8]; 8804 u8 sub_port[0x8]; 8805 u8 reserved_at_18[0x8]; 8806 8807 u8 reserved_at_20[0x20]; 8808 }; 8809 8810 struct mlx5_ifc_pqdr_reg_bits { 8811 u8 reserved_at_0[0x8]; 8812 u8 local_port[0x8]; 8813 u8 reserved_at_10[0x5]; 8814 u8 prio[0x3]; 8815 u8 reserved_at_18[0x6]; 8816 u8 mode[0x2]; 8817 8818 u8 reserved_at_20[0x20]; 8819 8820 u8 reserved_at_40[0x10]; 8821 u8 min_threshold[0x10]; 8822 8823 u8 reserved_at_60[0x10]; 8824 u8 max_threshold[0x10]; 8825 8826 u8 reserved_at_80[0x10]; 8827 u8 mark_probability_denominator[0x10]; 8828 8829 u8 reserved_at_a0[0x60]; 8830 }; 8831 8832 struct mlx5_ifc_ppsc_reg_bits { 8833 u8 reserved_at_0[0x8]; 8834 u8 local_port[0x8]; 8835 u8 reserved_at_10[0x10]; 8836 8837 u8 reserved_at_20[0x60]; 8838 8839 u8 reserved_at_80[0x1c]; 8840 u8 wrps_admin[0x4]; 8841 8842 u8 reserved_at_a0[0x1c]; 8843 u8 wrps_status[0x4]; 8844 8845 u8 reserved_at_c0[0x8]; 8846 u8 up_threshold[0x8]; 8847 u8 reserved_at_d0[0x8]; 8848 u8 down_threshold[0x8]; 8849 8850 u8 reserved_at_e0[0x20]; 8851 8852 u8 reserved_at_100[0x1c]; 8853 u8 srps_admin[0x4]; 8854 8855 u8 reserved_at_120[0x1c]; 8856 u8 srps_status[0x4]; 8857 8858 u8 reserved_at_140[0x40]; 8859 }; 8860 8861 struct mlx5_ifc_pplr_reg_bits { 8862 u8 reserved_at_0[0x8]; 8863 u8 local_port[0x8]; 8864 u8 reserved_at_10[0x10]; 8865 8866 u8 reserved_at_20[0x8]; 8867 u8 lb_cap[0x8]; 8868 u8 reserved_at_30[0x8]; 8869 u8 lb_en[0x8]; 8870 }; 8871 8872 struct mlx5_ifc_pplm_reg_bits { 8873 u8 reserved_at_0[0x8]; 8874 u8 local_port[0x8]; 8875 u8 reserved_at_10[0x10]; 8876 8877 u8 reserved_at_20[0x20]; 8878 8879 u8 port_profile_mode[0x8]; 8880 u8 static_port_profile[0x8]; 8881 u8 active_port_profile[0x8]; 8882 u8 reserved_at_58[0x8]; 8883 8884 u8 retransmission_active[0x8]; 8885 u8 fec_mode_active[0x18]; 8886 8887 u8 rs_fec_correction_bypass_cap[0x4]; 8888 u8 reserved_at_84[0x8]; 8889 u8 fec_override_cap_56g[0x4]; 8890 u8 fec_override_cap_100g[0x4]; 8891 u8 fec_override_cap_50g[0x4]; 8892 u8 fec_override_cap_25g[0x4]; 8893 u8 fec_override_cap_10g_40g[0x4]; 8894 8895 u8 rs_fec_correction_bypass_admin[0x4]; 8896 u8 reserved_at_a4[0x8]; 8897 u8 fec_override_admin_56g[0x4]; 8898 u8 fec_override_admin_100g[0x4]; 8899 u8 fec_override_admin_50g[0x4]; 8900 u8 fec_override_admin_25g[0x4]; 8901 u8 fec_override_admin_10g_40g[0x4]; 8902 8903 u8 fec_override_cap_400g_8x[0x10]; 8904 u8 fec_override_cap_200g_4x[0x10]; 8905 8906 u8 fec_override_cap_100g_2x[0x10]; 8907 u8 fec_override_cap_50g_1x[0x10]; 8908 8909 u8 fec_override_admin_400g_8x[0x10]; 8910 u8 fec_override_admin_200g_4x[0x10]; 8911 8912 u8 fec_override_admin_100g_2x[0x10]; 8913 u8 fec_override_admin_50g_1x[0x10]; 8914 8915 u8 reserved_at_140[0x140]; 8916 }; 8917 8918 struct mlx5_ifc_ppcnt_reg_bits { 8919 u8 swid[0x8]; 8920 u8 local_port[0x8]; 8921 u8 pnat[0x2]; 8922 u8 reserved_at_12[0x8]; 8923 u8 grp[0x6]; 8924 8925 u8 clr[0x1]; 8926 u8 reserved_at_21[0x1c]; 8927 u8 prio_tc[0x3]; 8928 8929 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set; 8930 }; 8931 8932 struct mlx5_ifc_mpein_reg_bits { 8933 u8 reserved_at_0[0x2]; 8934 u8 depth[0x6]; 8935 u8 pcie_index[0x8]; 8936 u8 node[0x8]; 8937 u8 reserved_at_18[0x8]; 8938 8939 u8 capability_mask[0x20]; 8940 8941 u8 reserved_at_40[0x8]; 8942 u8 link_width_enabled[0x8]; 8943 u8 link_speed_enabled[0x10]; 8944 8945 u8 lane0_physical_position[0x8]; 8946 u8 link_width_active[0x8]; 8947 u8 link_speed_active[0x10]; 8948 8949 u8 num_of_pfs[0x10]; 8950 u8 num_of_vfs[0x10]; 8951 8952 u8 bdf0[0x10]; 8953 u8 reserved_at_b0[0x10]; 8954 8955 u8 max_read_request_size[0x4]; 8956 u8 max_payload_size[0x4]; 8957 u8 reserved_at_c8[0x5]; 8958 u8 pwr_status[0x3]; 8959 u8 port_type[0x4]; 8960 u8 reserved_at_d4[0xb]; 8961 u8 lane_reversal[0x1]; 8962 8963 u8 reserved_at_e0[0x14]; 8964 u8 pci_power[0xc]; 8965 8966 u8 reserved_at_100[0x20]; 8967 8968 u8 device_status[0x10]; 8969 u8 port_state[0x8]; 8970 u8 reserved_at_138[0x8]; 8971 8972 u8 reserved_at_140[0x10]; 8973 u8 receiver_detect_result[0x10]; 8974 8975 u8 reserved_at_160[0x20]; 8976 }; 8977 8978 struct mlx5_ifc_mpcnt_reg_bits { 8979 u8 reserved_at_0[0x8]; 8980 u8 pcie_index[0x8]; 8981 u8 reserved_at_10[0xa]; 8982 u8 grp[0x6]; 8983 8984 u8 clr[0x1]; 8985 u8 reserved_at_21[0x1f]; 8986 8987 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set; 8988 }; 8989 8990 struct mlx5_ifc_ppad_reg_bits { 8991 u8 reserved_at_0[0x3]; 8992 u8 single_mac[0x1]; 8993 u8 reserved_at_4[0x4]; 8994 u8 local_port[0x8]; 8995 u8 mac_47_32[0x10]; 8996 8997 u8 mac_31_0[0x20]; 8998 8999 u8 reserved_at_40[0x40]; 9000 }; 9001 9002 struct mlx5_ifc_pmtu_reg_bits { 9003 u8 reserved_at_0[0x8]; 9004 u8 local_port[0x8]; 9005 u8 reserved_at_10[0x10]; 9006 9007 u8 max_mtu[0x10]; 9008 u8 reserved_at_30[0x10]; 9009 9010 u8 admin_mtu[0x10]; 9011 u8 reserved_at_50[0x10]; 9012 9013 u8 oper_mtu[0x10]; 9014 u8 reserved_at_70[0x10]; 9015 }; 9016 9017 struct mlx5_ifc_pmpr_reg_bits { 9018 u8 reserved_at_0[0x8]; 9019 u8 module[0x8]; 9020 u8 reserved_at_10[0x10]; 9021 9022 u8 reserved_at_20[0x18]; 9023 u8 attenuation_5g[0x8]; 9024 9025 u8 reserved_at_40[0x18]; 9026 u8 attenuation_7g[0x8]; 9027 9028 u8 reserved_at_60[0x18]; 9029 u8 attenuation_12g[0x8]; 9030 }; 9031 9032 struct mlx5_ifc_pmpe_reg_bits { 9033 u8 reserved_at_0[0x8]; 9034 u8 module[0x8]; 9035 u8 reserved_at_10[0xc]; 9036 u8 module_status[0x4]; 9037 9038 u8 reserved_at_20[0x60]; 9039 }; 9040 9041 struct mlx5_ifc_pmpc_reg_bits { 9042 u8 module_state_updated[32][0x8]; 9043 }; 9044 9045 struct mlx5_ifc_pmlpn_reg_bits { 9046 u8 reserved_at_0[0x4]; 9047 u8 mlpn_status[0x4]; 9048 u8 local_port[0x8]; 9049 u8 reserved_at_10[0x10]; 9050 9051 u8 e[0x1]; 9052 u8 reserved_at_21[0x1f]; 9053 }; 9054 9055 struct mlx5_ifc_pmlp_reg_bits { 9056 u8 rxtx[0x1]; 9057 u8 reserved_at_1[0x7]; 9058 u8 local_port[0x8]; 9059 u8 reserved_at_10[0x8]; 9060 u8 width[0x8]; 9061 9062 u8 lane0_module_mapping[0x20]; 9063 9064 u8 lane1_module_mapping[0x20]; 9065 9066 u8 lane2_module_mapping[0x20]; 9067 9068 u8 lane3_module_mapping[0x20]; 9069 9070 u8 reserved_at_a0[0x160]; 9071 }; 9072 9073 struct mlx5_ifc_pmaos_reg_bits { 9074 u8 reserved_at_0[0x8]; 9075 u8 module[0x8]; 9076 u8 reserved_at_10[0x4]; 9077 u8 admin_status[0x4]; 9078 u8 reserved_at_18[0x4]; 9079 u8 oper_status[0x4]; 9080 9081 u8 ase[0x1]; 9082 u8 ee[0x1]; 9083 u8 reserved_at_22[0x1c]; 9084 u8 e[0x2]; 9085 9086 u8 reserved_at_40[0x40]; 9087 }; 9088 9089 struct mlx5_ifc_plpc_reg_bits { 9090 u8 reserved_at_0[0x4]; 9091 u8 profile_id[0xc]; 9092 u8 reserved_at_10[0x4]; 9093 u8 proto_mask[0x4]; 9094 u8 reserved_at_18[0x8]; 9095 9096 u8 reserved_at_20[0x10]; 9097 u8 lane_speed[0x10]; 9098 9099 u8 reserved_at_40[0x17]; 9100 u8 lpbf[0x1]; 9101 u8 fec_mode_policy[0x8]; 9102 9103 u8 retransmission_capability[0x8]; 9104 u8 fec_mode_capability[0x18]; 9105 9106 u8 retransmission_support_admin[0x8]; 9107 u8 fec_mode_support_admin[0x18]; 9108 9109 u8 retransmission_request_admin[0x8]; 9110 u8 fec_mode_request_admin[0x18]; 9111 9112 u8 reserved_at_c0[0x80]; 9113 }; 9114 9115 struct mlx5_ifc_plib_reg_bits { 9116 u8 reserved_at_0[0x8]; 9117 u8 local_port[0x8]; 9118 u8 reserved_at_10[0x8]; 9119 u8 ib_port[0x8]; 9120 9121 u8 reserved_at_20[0x60]; 9122 }; 9123 9124 struct mlx5_ifc_plbf_reg_bits { 9125 u8 reserved_at_0[0x8]; 9126 u8 local_port[0x8]; 9127 u8 reserved_at_10[0xd]; 9128 u8 lbf_mode[0x3]; 9129 9130 u8 reserved_at_20[0x20]; 9131 }; 9132 9133 struct mlx5_ifc_pipg_reg_bits { 9134 u8 reserved_at_0[0x8]; 9135 u8 local_port[0x8]; 9136 u8 reserved_at_10[0x10]; 9137 9138 u8 dic[0x1]; 9139 u8 reserved_at_21[0x19]; 9140 u8 ipg[0x4]; 9141 u8 reserved_at_3e[0x2]; 9142 }; 9143 9144 struct mlx5_ifc_pifr_reg_bits { 9145 u8 reserved_at_0[0x8]; 9146 u8 local_port[0x8]; 9147 u8 reserved_at_10[0x10]; 9148 9149 u8 reserved_at_20[0xe0]; 9150 9151 u8 port_filter[8][0x20]; 9152 9153 u8 port_filter_update_en[8][0x20]; 9154 }; 9155 9156 struct mlx5_ifc_pfcc_reg_bits { 9157 u8 reserved_at_0[0x8]; 9158 u8 local_port[0x8]; 9159 u8 reserved_at_10[0xb]; 9160 u8 ppan_mask_n[0x1]; 9161 u8 minor_stall_mask[0x1]; 9162 u8 critical_stall_mask[0x1]; 9163 u8 reserved_at_1e[0x2]; 9164 9165 u8 ppan[0x4]; 9166 u8 reserved_at_24[0x4]; 9167 u8 prio_mask_tx[0x8]; 9168 u8 reserved_at_30[0x8]; 9169 u8 prio_mask_rx[0x8]; 9170 9171 u8 pptx[0x1]; 9172 u8 aptx[0x1]; 9173 u8 pptx_mask_n[0x1]; 9174 u8 reserved_at_43[0x5]; 9175 u8 pfctx[0x8]; 9176 u8 reserved_at_50[0x10]; 9177 9178 u8 pprx[0x1]; 9179 u8 aprx[0x1]; 9180 u8 pprx_mask_n[0x1]; 9181 u8 reserved_at_63[0x5]; 9182 u8 pfcrx[0x8]; 9183 u8 reserved_at_70[0x10]; 9184 9185 u8 device_stall_minor_watermark[0x10]; 9186 u8 device_stall_critical_watermark[0x10]; 9187 9188 u8 reserved_at_a0[0x60]; 9189 }; 9190 9191 struct mlx5_ifc_pelc_reg_bits { 9192 u8 op[0x4]; 9193 u8 reserved_at_4[0x4]; 9194 u8 local_port[0x8]; 9195 u8 reserved_at_10[0x10]; 9196 9197 u8 op_admin[0x8]; 9198 u8 op_capability[0x8]; 9199 u8 op_request[0x8]; 9200 u8 op_active[0x8]; 9201 9202 u8 admin[0x40]; 9203 9204 u8 capability[0x40]; 9205 9206 u8 request[0x40]; 9207 9208 u8 active[0x40]; 9209 9210 u8 reserved_at_140[0x80]; 9211 }; 9212 9213 struct mlx5_ifc_peir_reg_bits { 9214 u8 reserved_at_0[0x8]; 9215 u8 local_port[0x8]; 9216 u8 reserved_at_10[0x10]; 9217 9218 u8 reserved_at_20[0xc]; 9219 u8 error_count[0x4]; 9220 u8 reserved_at_30[0x10]; 9221 9222 u8 reserved_at_40[0xc]; 9223 u8 lane[0x4]; 9224 u8 reserved_at_50[0x8]; 9225 u8 error_type[0x8]; 9226 }; 9227 9228 struct mlx5_ifc_mpegc_reg_bits { 9229 u8 reserved_at_0[0x30]; 9230 u8 field_select[0x10]; 9231 9232 u8 tx_overflow_sense[0x1]; 9233 u8 mark_cqe[0x1]; 9234 u8 mark_cnp[0x1]; 9235 u8 reserved_at_43[0x1b]; 9236 u8 tx_lossy_overflow_oper[0x2]; 9237 9238 u8 reserved_at_60[0x100]; 9239 }; 9240 9241 enum { 9242 MLX5_MTUTC_OPERATION_SET_TIME_IMMEDIATE = 0x1, 9243 MLX5_MTUTC_OPERATION_ADJUST_TIME = 0x2, 9244 MLX5_MTUTC_OPERATION_ADJUST_FREQ_UTC = 0x3, 9245 }; 9246 9247 struct mlx5_ifc_mtutc_reg_bits { 9248 u8 reserved_at_0[0x1c]; 9249 u8 operation[0x4]; 9250 9251 u8 freq_adjustment[0x20]; 9252 9253 u8 reserved_at_40[0x40]; 9254 9255 u8 utc_sec[0x20]; 9256 9257 u8 reserved_at_a0[0x2]; 9258 u8 utc_nsec[0x1e]; 9259 9260 u8 time_adjustment[0x20]; 9261 }; 9262 9263 struct mlx5_ifc_pcam_enhanced_features_bits { 9264 u8 reserved_at_0[0x68]; 9265 u8 fec_50G_per_lane_in_pplm[0x1]; 9266 u8 reserved_at_69[0x4]; 9267 u8 rx_icrc_encapsulated_counter[0x1]; 9268 u8 reserved_at_6e[0x4]; 9269 u8 ptys_extended_ethernet[0x1]; 9270 u8 reserved_at_73[0x3]; 9271 u8 pfcc_mask[0x1]; 9272 u8 reserved_at_77[0x3]; 9273 u8 per_lane_error_counters[0x1]; 9274 u8 rx_buffer_fullness_counters[0x1]; 9275 u8 ptys_connector_type[0x1]; 9276 u8 reserved_at_7d[0x1]; 9277 u8 ppcnt_discard_group[0x1]; 9278 u8 ppcnt_statistical_group[0x1]; 9279 }; 9280 9281 struct mlx5_ifc_pcam_regs_5000_to_507f_bits { 9282 u8 port_access_reg_cap_mask_127_to_96[0x20]; 9283 u8 port_access_reg_cap_mask_95_to_64[0x20]; 9284 9285 u8 port_access_reg_cap_mask_63_to_36[0x1c]; 9286 u8 pplm[0x1]; 9287 u8 port_access_reg_cap_mask_34_to_32[0x3]; 9288 9289 u8 port_access_reg_cap_mask_31_to_13[0x13]; 9290 u8 pbmc[0x1]; 9291 u8 pptb[0x1]; 9292 u8 port_access_reg_cap_mask_10_to_09[0x2]; 9293 u8 ppcnt[0x1]; 9294 u8 port_access_reg_cap_mask_07_to_00[0x8]; 9295 }; 9296 9297 struct mlx5_ifc_pcam_reg_bits { 9298 u8 reserved_at_0[0x8]; 9299 u8 feature_group[0x8]; 9300 u8 reserved_at_10[0x8]; 9301 u8 access_reg_group[0x8]; 9302 9303 u8 reserved_at_20[0x20]; 9304 9305 union { 9306 struct mlx5_ifc_pcam_regs_5000_to_507f_bits regs_5000_to_507f; 9307 u8 reserved_at_0[0x80]; 9308 } port_access_reg_cap_mask; 9309 9310 u8 reserved_at_c0[0x80]; 9311 9312 union { 9313 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features; 9314 u8 reserved_at_0[0x80]; 9315 } feature_cap_mask; 9316 9317 u8 reserved_at_1c0[0xc0]; 9318 }; 9319 9320 struct mlx5_ifc_mcam_enhanced_features_bits { 9321 u8 reserved_at_0[0x6b]; 9322 u8 ptpcyc2realtime_modify[0x1]; 9323 u8 reserved_at_6c[0x2]; 9324 u8 pci_status_and_power[0x1]; 9325 u8 reserved_at_6f[0x5]; 9326 u8 mark_tx_action_cnp[0x1]; 9327 u8 mark_tx_action_cqe[0x1]; 9328 u8 dynamic_tx_overflow[0x1]; 9329 u8 reserved_at_77[0x4]; 9330 u8 pcie_outbound_stalled[0x1]; 9331 u8 tx_overflow_buffer_pkt[0x1]; 9332 u8 mtpps_enh_out_per_adj[0x1]; 9333 u8 mtpps_fs[0x1]; 9334 u8 pcie_performance_group[0x1]; 9335 }; 9336 9337 struct mlx5_ifc_mcam_access_reg_bits { 9338 u8 reserved_at_0[0x1c]; 9339 u8 mcda[0x1]; 9340 u8 mcc[0x1]; 9341 u8 mcqi[0x1]; 9342 u8 mcqs[0x1]; 9343 9344 u8 regs_95_to_87[0x9]; 9345 u8 mpegc[0x1]; 9346 u8 mtutc[0x1]; 9347 u8 regs_84_to_68[0x11]; 9348 u8 tracer_registers[0x4]; 9349 9350 u8 regs_63_to_32[0x20]; 9351 u8 regs_31_to_0[0x20]; 9352 }; 9353 9354 struct mlx5_ifc_mcam_access_reg_bits1 { 9355 u8 regs_127_to_96[0x20]; 9356 9357 u8 regs_95_to_64[0x20]; 9358 9359 u8 regs_63_to_32[0x20]; 9360 9361 u8 regs_31_to_0[0x20]; 9362 }; 9363 9364 struct mlx5_ifc_mcam_access_reg_bits2 { 9365 u8 regs_127_to_99[0x1d]; 9366 u8 mirc[0x1]; 9367 u8 regs_97_to_96[0x2]; 9368 9369 u8 regs_95_to_64[0x20]; 9370 9371 u8 regs_63_to_32[0x20]; 9372 9373 u8 regs_31_to_0[0x20]; 9374 }; 9375 9376 struct mlx5_ifc_mcam_reg_bits { 9377 u8 reserved_at_0[0x8]; 9378 u8 feature_group[0x8]; 9379 u8 reserved_at_10[0x8]; 9380 u8 access_reg_group[0x8]; 9381 9382 u8 reserved_at_20[0x20]; 9383 9384 union { 9385 struct mlx5_ifc_mcam_access_reg_bits access_regs; 9386 struct mlx5_ifc_mcam_access_reg_bits1 access_regs1; 9387 struct mlx5_ifc_mcam_access_reg_bits2 access_regs2; 9388 u8 reserved_at_0[0x80]; 9389 } mng_access_reg_cap_mask; 9390 9391 u8 reserved_at_c0[0x80]; 9392 9393 union { 9394 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features; 9395 u8 reserved_at_0[0x80]; 9396 } mng_feature_cap_mask; 9397 9398 u8 reserved_at_1c0[0x80]; 9399 }; 9400 9401 struct mlx5_ifc_qcam_access_reg_cap_mask { 9402 u8 qcam_access_reg_cap_mask_127_to_20[0x6C]; 9403 u8 qpdpm[0x1]; 9404 u8 qcam_access_reg_cap_mask_18_to_4[0x0F]; 9405 u8 qdpm[0x1]; 9406 u8 qpts[0x1]; 9407 u8 qcap[0x1]; 9408 u8 qcam_access_reg_cap_mask_0[0x1]; 9409 }; 9410 9411 struct mlx5_ifc_qcam_qos_feature_cap_mask { 9412 u8 qcam_qos_feature_cap_mask_127_to_1[0x7F]; 9413 u8 qpts_trust_both[0x1]; 9414 }; 9415 9416 struct mlx5_ifc_qcam_reg_bits { 9417 u8 reserved_at_0[0x8]; 9418 u8 feature_group[0x8]; 9419 u8 reserved_at_10[0x8]; 9420 u8 access_reg_group[0x8]; 9421 u8 reserved_at_20[0x20]; 9422 9423 union { 9424 struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap; 9425 u8 reserved_at_0[0x80]; 9426 } qos_access_reg_cap_mask; 9427 9428 u8 reserved_at_c0[0x80]; 9429 9430 union { 9431 struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap; 9432 u8 reserved_at_0[0x80]; 9433 } qos_feature_cap_mask; 9434 9435 u8 reserved_at_1c0[0x80]; 9436 }; 9437 9438 struct mlx5_ifc_core_dump_reg_bits { 9439 u8 reserved_at_0[0x18]; 9440 u8 core_dump_type[0x8]; 9441 9442 u8 reserved_at_20[0x30]; 9443 u8 vhca_id[0x10]; 9444 9445 u8 reserved_at_60[0x8]; 9446 u8 qpn[0x18]; 9447 u8 reserved_at_80[0x180]; 9448 }; 9449 9450 struct mlx5_ifc_pcap_reg_bits { 9451 u8 reserved_at_0[0x8]; 9452 u8 local_port[0x8]; 9453 u8 reserved_at_10[0x10]; 9454 9455 u8 port_capability_mask[4][0x20]; 9456 }; 9457 9458 struct mlx5_ifc_paos_reg_bits { 9459 u8 swid[0x8]; 9460 u8 local_port[0x8]; 9461 u8 reserved_at_10[0x4]; 9462 u8 admin_status[0x4]; 9463 u8 reserved_at_18[0x4]; 9464 u8 oper_status[0x4]; 9465 9466 u8 ase[0x1]; 9467 u8 ee[0x1]; 9468 u8 reserved_at_22[0x1c]; 9469 u8 e[0x2]; 9470 9471 u8 reserved_at_40[0x40]; 9472 }; 9473 9474 struct mlx5_ifc_pamp_reg_bits { 9475 u8 reserved_at_0[0x8]; 9476 u8 opamp_group[0x8]; 9477 u8 reserved_at_10[0xc]; 9478 u8 opamp_group_type[0x4]; 9479 9480 u8 start_index[0x10]; 9481 u8 reserved_at_30[0x4]; 9482 u8 num_of_indices[0xc]; 9483 9484 u8 index_data[18][0x10]; 9485 }; 9486 9487 struct mlx5_ifc_pcmr_reg_bits { 9488 u8 reserved_at_0[0x8]; 9489 u8 local_port[0x8]; 9490 u8 reserved_at_10[0x10]; 9491 u8 entropy_force_cap[0x1]; 9492 u8 entropy_calc_cap[0x1]; 9493 u8 entropy_gre_calc_cap[0x1]; 9494 u8 reserved_at_23[0x1b]; 9495 u8 fcs_cap[0x1]; 9496 u8 reserved_at_3f[0x1]; 9497 u8 entropy_force[0x1]; 9498 u8 entropy_calc[0x1]; 9499 u8 entropy_gre_calc[0x1]; 9500 u8 reserved_at_43[0x1b]; 9501 u8 fcs_chk[0x1]; 9502 u8 reserved_at_5f[0x1]; 9503 }; 9504 9505 struct mlx5_ifc_lane_2_module_mapping_bits { 9506 u8 reserved_at_0[0x6]; 9507 u8 rx_lane[0x2]; 9508 u8 reserved_at_8[0x6]; 9509 u8 tx_lane[0x2]; 9510 u8 reserved_at_10[0x8]; 9511 u8 module[0x8]; 9512 }; 9513 9514 struct mlx5_ifc_bufferx_reg_bits { 9515 u8 reserved_at_0[0x6]; 9516 u8 lossy[0x1]; 9517 u8 epsb[0x1]; 9518 u8 reserved_at_8[0xc]; 9519 u8 size[0xc]; 9520 9521 u8 xoff_threshold[0x10]; 9522 u8 xon_threshold[0x10]; 9523 }; 9524 9525 struct mlx5_ifc_set_node_in_bits { 9526 u8 node_description[64][0x8]; 9527 }; 9528 9529 struct mlx5_ifc_register_power_settings_bits { 9530 u8 reserved_at_0[0x18]; 9531 u8 power_settings_level[0x8]; 9532 9533 u8 reserved_at_20[0x60]; 9534 }; 9535 9536 struct mlx5_ifc_register_host_endianness_bits { 9537 u8 he[0x1]; 9538 u8 reserved_at_1[0x1f]; 9539 9540 u8 reserved_at_20[0x60]; 9541 }; 9542 9543 struct mlx5_ifc_umr_pointer_desc_argument_bits { 9544 u8 reserved_at_0[0x20]; 9545 9546 u8 mkey[0x20]; 9547 9548 u8 addressh_63_32[0x20]; 9549 9550 u8 addressl_31_0[0x20]; 9551 }; 9552 9553 struct mlx5_ifc_ud_adrs_vector_bits { 9554 u8 dc_key[0x40]; 9555 9556 u8 ext[0x1]; 9557 u8 reserved_at_41[0x7]; 9558 u8 destination_qp_dct[0x18]; 9559 9560 u8 static_rate[0x4]; 9561 u8 sl_eth_prio[0x4]; 9562 u8 fl[0x1]; 9563 u8 mlid[0x7]; 9564 u8 rlid_udp_sport[0x10]; 9565 9566 u8 reserved_at_80[0x20]; 9567 9568 u8 rmac_47_16[0x20]; 9569 9570 u8 rmac_15_0[0x10]; 9571 u8 tclass[0x8]; 9572 u8 hop_limit[0x8]; 9573 9574 u8 reserved_at_e0[0x1]; 9575 u8 grh[0x1]; 9576 u8 reserved_at_e2[0x2]; 9577 u8 src_addr_index[0x8]; 9578 u8 flow_label[0x14]; 9579 9580 u8 rgid_rip[16][0x8]; 9581 }; 9582 9583 struct mlx5_ifc_pages_req_event_bits { 9584 u8 reserved_at_0[0x10]; 9585 u8 function_id[0x10]; 9586 9587 u8 num_pages[0x20]; 9588 9589 u8 reserved_at_40[0xa0]; 9590 }; 9591 9592 struct mlx5_ifc_eqe_bits { 9593 u8 reserved_at_0[0x8]; 9594 u8 event_type[0x8]; 9595 u8 reserved_at_10[0x8]; 9596 u8 event_sub_type[0x8]; 9597 9598 u8 reserved_at_20[0xe0]; 9599 9600 union mlx5_ifc_event_auto_bits event_data; 9601 9602 u8 reserved_at_1e0[0x10]; 9603 u8 signature[0x8]; 9604 u8 reserved_at_1f8[0x7]; 9605 u8 owner[0x1]; 9606 }; 9607 9608 enum { 9609 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7, 9610 }; 9611 9612 struct mlx5_ifc_cmd_queue_entry_bits { 9613 u8 type[0x8]; 9614 u8 reserved_at_8[0x18]; 9615 9616 u8 input_length[0x20]; 9617 9618 u8 input_mailbox_pointer_63_32[0x20]; 9619 9620 u8 input_mailbox_pointer_31_9[0x17]; 9621 u8 reserved_at_77[0x9]; 9622 9623 u8 command_input_inline_data[16][0x8]; 9624 9625 u8 command_output_inline_data[16][0x8]; 9626 9627 u8 output_mailbox_pointer_63_32[0x20]; 9628 9629 u8 output_mailbox_pointer_31_9[0x17]; 9630 u8 reserved_at_1b7[0x9]; 9631 9632 u8 output_length[0x20]; 9633 9634 u8 token[0x8]; 9635 u8 signature[0x8]; 9636 u8 reserved_at_1f0[0x8]; 9637 u8 status[0x7]; 9638 u8 ownership[0x1]; 9639 }; 9640 9641 struct mlx5_ifc_cmd_out_bits { 9642 u8 status[0x8]; 9643 u8 reserved_at_8[0x18]; 9644 9645 u8 syndrome[0x20]; 9646 9647 u8 command_output[0x20]; 9648 }; 9649 9650 struct mlx5_ifc_cmd_in_bits { 9651 u8 opcode[0x10]; 9652 u8 reserved_at_10[0x10]; 9653 9654 u8 reserved_at_20[0x10]; 9655 u8 op_mod[0x10]; 9656 9657 u8 command[][0x20]; 9658 }; 9659 9660 struct mlx5_ifc_cmd_if_box_bits { 9661 u8 mailbox_data[512][0x8]; 9662 9663 u8 reserved_at_1000[0x180]; 9664 9665 u8 next_pointer_63_32[0x20]; 9666 9667 u8 next_pointer_31_10[0x16]; 9668 u8 reserved_at_11b6[0xa]; 9669 9670 u8 block_number[0x20]; 9671 9672 u8 reserved_at_11e0[0x8]; 9673 u8 token[0x8]; 9674 u8 ctrl_signature[0x8]; 9675 u8 signature[0x8]; 9676 }; 9677 9678 struct mlx5_ifc_mtt_bits { 9679 u8 ptag_63_32[0x20]; 9680 9681 u8 ptag_31_8[0x18]; 9682 u8 reserved_at_38[0x6]; 9683 u8 wr_en[0x1]; 9684 u8 rd_en[0x1]; 9685 }; 9686 9687 struct mlx5_ifc_query_wol_rol_out_bits { 9688 u8 status[0x8]; 9689 u8 reserved_at_8[0x18]; 9690 9691 u8 syndrome[0x20]; 9692 9693 u8 reserved_at_40[0x10]; 9694 u8 rol_mode[0x8]; 9695 u8 wol_mode[0x8]; 9696 9697 u8 reserved_at_60[0x20]; 9698 }; 9699 9700 struct mlx5_ifc_query_wol_rol_in_bits { 9701 u8 opcode[0x10]; 9702 u8 reserved_at_10[0x10]; 9703 9704 u8 reserved_at_20[0x10]; 9705 u8 op_mod[0x10]; 9706 9707 u8 reserved_at_40[0x40]; 9708 }; 9709 9710 struct mlx5_ifc_set_wol_rol_out_bits { 9711 u8 status[0x8]; 9712 u8 reserved_at_8[0x18]; 9713 9714 u8 syndrome[0x20]; 9715 9716 u8 reserved_at_40[0x40]; 9717 }; 9718 9719 struct mlx5_ifc_set_wol_rol_in_bits { 9720 u8 opcode[0x10]; 9721 u8 reserved_at_10[0x10]; 9722 9723 u8 reserved_at_20[0x10]; 9724 u8 op_mod[0x10]; 9725 9726 u8 rol_mode_valid[0x1]; 9727 u8 wol_mode_valid[0x1]; 9728 u8 reserved_at_42[0xe]; 9729 u8 rol_mode[0x8]; 9730 u8 wol_mode[0x8]; 9731 9732 u8 reserved_at_60[0x20]; 9733 }; 9734 9735 enum { 9736 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0, 9737 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1, 9738 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2, 9739 }; 9740 9741 enum { 9742 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0, 9743 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1, 9744 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2, 9745 }; 9746 9747 enum { 9748 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR = 0x1, 9749 MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC = 0x7, 9750 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR = 0x8, 9751 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR = 0x9, 9752 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR = 0xa, 9753 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR = 0xb, 9754 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN = 0xc, 9755 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR = 0xd, 9756 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV = 0xe, 9757 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR = 0xf, 9758 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR = 0x10, 9759 }; 9760 9761 struct mlx5_ifc_initial_seg_bits { 9762 u8 fw_rev_minor[0x10]; 9763 u8 fw_rev_major[0x10]; 9764 9765 u8 cmd_interface_rev[0x10]; 9766 u8 fw_rev_subminor[0x10]; 9767 9768 u8 reserved_at_40[0x40]; 9769 9770 u8 cmdq_phy_addr_63_32[0x20]; 9771 9772 u8 cmdq_phy_addr_31_12[0x14]; 9773 u8 reserved_at_b4[0x2]; 9774 u8 nic_interface[0x2]; 9775 u8 log_cmdq_size[0x4]; 9776 u8 log_cmdq_stride[0x4]; 9777 9778 u8 command_doorbell_vector[0x20]; 9779 9780 u8 reserved_at_e0[0xf00]; 9781 9782 u8 initializing[0x1]; 9783 u8 reserved_at_fe1[0x4]; 9784 u8 nic_interface_supported[0x3]; 9785 u8 embedded_cpu[0x1]; 9786 u8 reserved_at_fe9[0x17]; 9787 9788 struct mlx5_ifc_health_buffer_bits health_buffer; 9789 9790 u8 no_dram_nic_offset[0x20]; 9791 9792 u8 reserved_at_1220[0x6e40]; 9793 9794 u8 reserved_at_8060[0x1f]; 9795 u8 clear_int[0x1]; 9796 9797 u8 health_syndrome[0x8]; 9798 u8 health_counter[0x18]; 9799 9800 u8 reserved_at_80a0[0x17fc0]; 9801 }; 9802 9803 struct mlx5_ifc_mtpps_reg_bits { 9804 u8 reserved_at_0[0xc]; 9805 u8 cap_number_of_pps_pins[0x4]; 9806 u8 reserved_at_10[0x4]; 9807 u8 cap_max_num_of_pps_in_pins[0x4]; 9808 u8 reserved_at_18[0x4]; 9809 u8 cap_max_num_of_pps_out_pins[0x4]; 9810 9811 u8 reserved_at_20[0x24]; 9812 u8 cap_pin_3_mode[0x4]; 9813 u8 reserved_at_48[0x4]; 9814 u8 cap_pin_2_mode[0x4]; 9815 u8 reserved_at_50[0x4]; 9816 u8 cap_pin_1_mode[0x4]; 9817 u8 reserved_at_58[0x4]; 9818 u8 cap_pin_0_mode[0x4]; 9819 9820 u8 reserved_at_60[0x4]; 9821 u8 cap_pin_7_mode[0x4]; 9822 u8 reserved_at_68[0x4]; 9823 u8 cap_pin_6_mode[0x4]; 9824 u8 reserved_at_70[0x4]; 9825 u8 cap_pin_5_mode[0x4]; 9826 u8 reserved_at_78[0x4]; 9827 u8 cap_pin_4_mode[0x4]; 9828 9829 u8 field_select[0x20]; 9830 u8 reserved_at_a0[0x60]; 9831 9832 u8 enable[0x1]; 9833 u8 reserved_at_101[0xb]; 9834 u8 pattern[0x4]; 9835 u8 reserved_at_110[0x4]; 9836 u8 pin_mode[0x4]; 9837 u8 pin[0x8]; 9838 9839 u8 reserved_at_120[0x20]; 9840 9841 u8 time_stamp[0x40]; 9842 9843 u8 out_pulse_duration[0x10]; 9844 u8 out_periodic_adjustment[0x10]; 9845 u8 enhanced_out_periodic_adjustment[0x20]; 9846 9847 u8 reserved_at_1c0[0x20]; 9848 }; 9849 9850 struct mlx5_ifc_mtppse_reg_bits { 9851 u8 reserved_at_0[0x18]; 9852 u8 pin[0x8]; 9853 u8 event_arm[0x1]; 9854 u8 reserved_at_21[0x1b]; 9855 u8 event_generation_mode[0x4]; 9856 u8 reserved_at_40[0x40]; 9857 }; 9858 9859 struct mlx5_ifc_mcqs_reg_bits { 9860 u8 last_index_flag[0x1]; 9861 u8 reserved_at_1[0x7]; 9862 u8 fw_device[0x8]; 9863 u8 component_index[0x10]; 9864 9865 u8 reserved_at_20[0x10]; 9866 u8 identifier[0x10]; 9867 9868 u8 reserved_at_40[0x17]; 9869 u8 component_status[0x5]; 9870 u8 component_update_state[0x4]; 9871 9872 u8 last_update_state_changer_type[0x4]; 9873 u8 last_update_state_changer_host_id[0x4]; 9874 u8 reserved_at_68[0x18]; 9875 }; 9876 9877 struct mlx5_ifc_mcqi_cap_bits { 9878 u8 supported_info_bitmask[0x20]; 9879 9880 u8 component_size[0x20]; 9881 9882 u8 max_component_size[0x20]; 9883 9884 u8 log_mcda_word_size[0x4]; 9885 u8 reserved_at_64[0xc]; 9886 u8 mcda_max_write_size[0x10]; 9887 9888 u8 rd_en[0x1]; 9889 u8 reserved_at_81[0x1]; 9890 u8 match_chip_id[0x1]; 9891 u8 match_psid[0x1]; 9892 u8 check_user_timestamp[0x1]; 9893 u8 match_base_guid_mac[0x1]; 9894 u8 reserved_at_86[0x1a]; 9895 }; 9896 9897 struct mlx5_ifc_mcqi_version_bits { 9898 u8 reserved_at_0[0x2]; 9899 u8 build_time_valid[0x1]; 9900 u8 user_defined_time_valid[0x1]; 9901 u8 reserved_at_4[0x14]; 9902 u8 version_string_length[0x8]; 9903 9904 u8 version[0x20]; 9905 9906 u8 build_time[0x40]; 9907 9908 u8 user_defined_time[0x40]; 9909 9910 u8 build_tool_version[0x20]; 9911 9912 u8 reserved_at_e0[0x20]; 9913 9914 u8 version_string[92][0x8]; 9915 }; 9916 9917 struct mlx5_ifc_mcqi_activation_method_bits { 9918 u8 pending_server_ac_power_cycle[0x1]; 9919 u8 pending_server_dc_power_cycle[0x1]; 9920 u8 pending_server_reboot[0x1]; 9921 u8 pending_fw_reset[0x1]; 9922 u8 auto_activate[0x1]; 9923 u8 all_hosts_sync[0x1]; 9924 u8 device_hw_reset[0x1]; 9925 u8 reserved_at_7[0x19]; 9926 }; 9927 9928 union mlx5_ifc_mcqi_reg_data_bits { 9929 struct mlx5_ifc_mcqi_cap_bits mcqi_caps; 9930 struct mlx5_ifc_mcqi_version_bits mcqi_version; 9931 struct mlx5_ifc_mcqi_activation_method_bits mcqi_activation_mathod; 9932 }; 9933 9934 struct mlx5_ifc_mcqi_reg_bits { 9935 u8 read_pending_component[0x1]; 9936 u8 reserved_at_1[0xf]; 9937 u8 component_index[0x10]; 9938 9939 u8 reserved_at_20[0x20]; 9940 9941 u8 reserved_at_40[0x1b]; 9942 u8 info_type[0x5]; 9943 9944 u8 info_size[0x20]; 9945 9946 u8 offset[0x20]; 9947 9948 u8 reserved_at_a0[0x10]; 9949 u8 data_size[0x10]; 9950 9951 union mlx5_ifc_mcqi_reg_data_bits data[]; 9952 }; 9953 9954 struct mlx5_ifc_mcc_reg_bits { 9955 u8 reserved_at_0[0x4]; 9956 u8 time_elapsed_since_last_cmd[0xc]; 9957 u8 reserved_at_10[0x8]; 9958 u8 instruction[0x8]; 9959 9960 u8 reserved_at_20[0x10]; 9961 u8 component_index[0x10]; 9962 9963 u8 reserved_at_40[0x8]; 9964 u8 update_handle[0x18]; 9965 9966 u8 handle_owner_type[0x4]; 9967 u8 handle_owner_host_id[0x4]; 9968 u8 reserved_at_68[0x1]; 9969 u8 control_progress[0x7]; 9970 u8 error_code[0x8]; 9971 u8 reserved_at_78[0x4]; 9972 u8 control_state[0x4]; 9973 9974 u8 component_size[0x20]; 9975 9976 u8 reserved_at_a0[0x60]; 9977 }; 9978 9979 struct mlx5_ifc_mcda_reg_bits { 9980 u8 reserved_at_0[0x8]; 9981 u8 update_handle[0x18]; 9982 9983 u8 offset[0x20]; 9984 9985 u8 reserved_at_40[0x10]; 9986 u8 size[0x10]; 9987 9988 u8 reserved_at_60[0x20]; 9989 9990 u8 data[][0x20]; 9991 }; 9992 9993 enum { 9994 MLX5_MFRL_REG_RESET_TYPE_FULL_CHIP = BIT(0), 9995 MLX5_MFRL_REG_RESET_TYPE_NET_PORT_ALIVE = BIT(1), 9996 }; 9997 9998 enum { 9999 MLX5_MFRL_REG_RESET_LEVEL0 = BIT(0), 10000 MLX5_MFRL_REG_RESET_LEVEL3 = BIT(3), 10001 MLX5_MFRL_REG_RESET_LEVEL6 = BIT(6), 10002 }; 10003 10004 struct mlx5_ifc_mfrl_reg_bits { 10005 u8 reserved_at_0[0x20]; 10006 10007 u8 reserved_at_20[0x2]; 10008 u8 pci_sync_for_fw_update_start[0x1]; 10009 u8 pci_sync_for_fw_update_resp[0x2]; 10010 u8 rst_type_sel[0x3]; 10011 u8 reserved_at_28[0x8]; 10012 u8 reset_type[0x8]; 10013 u8 reset_level[0x8]; 10014 }; 10015 10016 struct mlx5_ifc_mirc_reg_bits { 10017 u8 reserved_at_0[0x18]; 10018 u8 status_code[0x8]; 10019 10020 u8 reserved_at_20[0x20]; 10021 }; 10022 10023 struct mlx5_ifc_pddr_monitor_opcode_bits { 10024 u8 reserved_at_0[0x10]; 10025 u8 monitor_opcode[0x10]; 10026 }; 10027 10028 union mlx5_ifc_pddr_troubleshooting_page_status_opcode_auto_bits { 10029 struct mlx5_ifc_pddr_monitor_opcode_bits pddr_monitor_opcode; 10030 u8 reserved_at_0[0x20]; 10031 }; 10032 10033 enum { 10034 /* Monitor opcodes */ 10035 MLX5_PDDR_REG_TRBLSH_GROUP_OPCODE_MONITOR = 0x0, 10036 }; 10037 10038 struct mlx5_ifc_pddr_troubleshooting_page_bits { 10039 u8 reserved_at_0[0x10]; 10040 u8 group_opcode[0x10]; 10041 10042 union mlx5_ifc_pddr_troubleshooting_page_status_opcode_auto_bits status_opcode; 10043 10044 u8 reserved_at_40[0x20]; 10045 10046 u8 status_message[59][0x20]; 10047 }; 10048 10049 union mlx5_ifc_pddr_reg_page_data_auto_bits { 10050 struct mlx5_ifc_pddr_troubleshooting_page_bits pddr_troubleshooting_page; 10051 u8 reserved_at_0[0x7c0]; 10052 }; 10053 10054 enum { 10055 MLX5_PDDR_REG_PAGE_SELECT_TROUBLESHOOTING_INFO_PAGE = 0x1, 10056 }; 10057 10058 struct mlx5_ifc_pddr_reg_bits { 10059 u8 reserved_at_0[0x8]; 10060 u8 local_port[0x8]; 10061 u8 pnat[0x2]; 10062 u8 reserved_at_12[0xe]; 10063 10064 u8 reserved_at_20[0x18]; 10065 u8 page_select[0x8]; 10066 10067 union mlx5_ifc_pddr_reg_page_data_auto_bits page_data; 10068 }; 10069 10070 union mlx5_ifc_ports_control_registers_document_bits { 10071 struct mlx5_ifc_bufferx_reg_bits bufferx_reg; 10072 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 10073 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 10074 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 10075 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 10076 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 10077 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 10078 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout; 10079 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout; 10080 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping; 10081 struct mlx5_ifc_pamp_reg_bits pamp_reg; 10082 struct mlx5_ifc_paos_reg_bits paos_reg; 10083 struct mlx5_ifc_pcap_reg_bits pcap_reg; 10084 struct mlx5_ifc_pddr_monitor_opcode_bits pddr_monitor_opcode; 10085 struct mlx5_ifc_pddr_reg_bits pddr_reg; 10086 struct mlx5_ifc_pddr_troubleshooting_page_bits pddr_troubleshooting_page; 10087 struct mlx5_ifc_peir_reg_bits peir_reg; 10088 struct mlx5_ifc_pelc_reg_bits pelc_reg; 10089 struct mlx5_ifc_pfcc_reg_bits pfcc_reg; 10090 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 10091 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 10092 struct mlx5_ifc_pifr_reg_bits pifr_reg; 10093 struct mlx5_ifc_pipg_reg_bits pipg_reg; 10094 struct mlx5_ifc_plbf_reg_bits plbf_reg; 10095 struct mlx5_ifc_plib_reg_bits plib_reg; 10096 struct mlx5_ifc_plpc_reg_bits plpc_reg; 10097 struct mlx5_ifc_pmaos_reg_bits pmaos_reg; 10098 struct mlx5_ifc_pmlp_reg_bits pmlp_reg; 10099 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg; 10100 struct mlx5_ifc_pmpc_reg_bits pmpc_reg; 10101 struct mlx5_ifc_pmpe_reg_bits pmpe_reg; 10102 struct mlx5_ifc_pmpr_reg_bits pmpr_reg; 10103 struct mlx5_ifc_pmtu_reg_bits pmtu_reg; 10104 struct mlx5_ifc_ppad_reg_bits ppad_reg; 10105 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg; 10106 struct mlx5_ifc_mpein_reg_bits mpein_reg; 10107 struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg; 10108 struct mlx5_ifc_pplm_reg_bits pplm_reg; 10109 struct mlx5_ifc_pplr_reg_bits pplr_reg; 10110 struct mlx5_ifc_ppsc_reg_bits ppsc_reg; 10111 struct mlx5_ifc_pqdr_reg_bits pqdr_reg; 10112 struct mlx5_ifc_pspa_reg_bits pspa_reg; 10113 struct mlx5_ifc_ptas_reg_bits ptas_reg; 10114 struct mlx5_ifc_ptys_reg_bits ptys_reg; 10115 struct mlx5_ifc_mlcr_reg_bits mlcr_reg; 10116 struct mlx5_ifc_pude_reg_bits pude_reg; 10117 struct mlx5_ifc_pvlc_reg_bits pvlc_reg; 10118 struct mlx5_ifc_slrg_reg_bits slrg_reg; 10119 struct mlx5_ifc_sltp_reg_bits sltp_reg; 10120 struct mlx5_ifc_mtpps_reg_bits mtpps_reg; 10121 struct mlx5_ifc_mtppse_reg_bits mtppse_reg; 10122 struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg; 10123 struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits; 10124 struct mlx5_ifc_fpga_cap_bits fpga_cap_bits; 10125 struct mlx5_ifc_mcqi_reg_bits mcqi_reg; 10126 struct mlx5_ifc_mcc_reg_bits mcc_reg; 10127 struct mlx5_ifc_mcda_reg_bits mcda_reg; 10128 struct mlx5_ifc_mirc_reg_bits mirc_reg; 10129 struct mlx5_ifc_mfrl_reg_bits mfrl_reg; 10130 struct mlx5_ifc_mtutc_reg_bits mtutc_reg; 10131 u8 reserved_at_0[0x60e0]; 10132 }; 10133 10134 union mlx5_ifc_debug_enhancements_document_bits { 10135 struct mlx5_ifc_health_buffer_bits health_buffer; 10136 u8 reserved_at_0[0x200]; 10137 }; 10138 10139 union mlx5_ifc_uplink_pci_interface_document_bits { 10140 struct mlx5_ifc_initial_seg_bits initial_seg; 10141 u8 reserved_at_0[0x20060]; 10142 }; 10143 10144 struct mlx5_ifc_set_flow_table_root_out_bits { 10145 u8 status[0x8]; 10146 u8 reserved_at_8[0x18]; 10147 10148 u8 syndrome[0x20]; 10149 10150 u8 reserved_at_40[0x40]; 10151 }; 10152 10153 struct mlx5_ifc_set_flow_table_root_in_bits { 10154 u8 opcode[0x10]; 10155 u8 reserved_at_10[0x10]; 10156 10157 u8 reserved_at_20[0x10]; 10158 u8 op_mod[0x10]; 10159 10160 u8 other_vport[0x1]; 10161 u8 reserved_at_41[0xf]; 10162 u8 vport_number[0x10]; 10163 10164 u8 reserved_at_60[0x20]; 10165 10166 u8 table_type[0x8]; 10167 u8 reserved_at_88[0x7]; 10168 u8 table_of_other_vport[0x1]; 10169 u8 table_vport_number[0x10]; 10170 10171 u8 reserved_at_a0[0x8]; 10172 u8 table_id[0x18]; 10173 10174 u8 reserved_at_c0[0x8]; 10175 u8 underlay_qpn[0x18]; 10176 u8 table_eswitch_owner_vhca_id_valid[0x1]; 10177 u8 reserved_at_e1[0xf]; 10178 u8 table_eswitch_owner_vhca_id[0x10]; 10179 u8 reserved_at_100[0x100]; 10180 }; 10181 10182 enum { 10183 MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = (1UL << 0), 10184 MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15), 10185 }; 10186 10187 struct mlx5_ifc_modify_flow_table_out_bits { 10188 u8 status[0x8]; 10189 u8 reserved_at_8[0x18]; 10190 10191 u8 syndrome[0x20]; 10192 10193 u8 reserved_at_40[0x40]; 10194 }; 10195 10196 struct mlx5_ifc_modify_flow_table_in_bits { 10197 u8 opcode[0x10]; 10198 u8 reserved_at_10[0x10]; 10199 10200 u8 reserved_at_20[0x10]; 10201 u8 op_mod[0x10]; 10202 10203 u8 other_vport[0x1]; 10204 u8 reserved_at_41[0xf]; 10205 u8 vport_number[0x10]; 10206 10207 u8 reserved_at_60[0x10]; 10208 u8 modify_field_select[0x10]; 10209 10210 u8 table_type[0x8]; 10211 u8 reserved_at_88[0x18]; 10212 10213 u8 reserved_at_a0[0x8]; 10214 u8 table_id[0x18]; 10215 10216 struct mlx5_ifc_flow_table_context_bits flow_table_context; 10217 }; 10218 10219 struct mlx5_ifc_ets_tcn_config_reg_bits { 10220 u8 g[0x1]; 10221 u8 b[0x1]; 10222 u8 r[0x1]; 10223 u8 reserved_at_3[0x9]; 10224 u8 group[0x4]; 10225 u8 reserved_at_10[0x9]; 10226 u8 bw_allocation[0x7]; 10227 10228 u8 reserved_at_20[0xc]; 10229 u8 max_bw_units[0x4]; 10230 u8 reserved_at_30[0x8]; 10231 u8 max_bw_value[0x8]; 10232 }; 10233 10234 struct mlx5_ifc_ets_global_config_reg_bits { 10235 u8 reserved_at_0[0x2]; 10236 u8 r[0x1]; 10237 u8 reserved_at_3[0x1d]; 10238 10239 u8 reserved_at_20[0xc]; 10240 u8 max_bw_units[0x4]; 10241 u8 reserved_at_30[0x8]; 10242 u8 max_bw_value[0x8]; 10243 }; 10244 10245 struct mlx5_ifc_qetc_reg_bits { 10246 u8 reserved_at_0[0x8]; 10247 u8 port_number[0x8]; 10248 u8 reserved_at_10[0x30]; 10249 10250 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8]; 10251 struct mlx5_ifc_ets_global_config_reg_bits global_configuration; 10252 }; 10253 10254 struct mlx5_ifc_qpdpm_dscp_reg_bits { 10255 u8 e[0x1]; 10256 u8 reserved_at_01[0x0b]; 10257 u8 prio[0x04]; 10258 }; 10259 10260 struct mlx5_ifc_qpdpm_reg_bits { 10261 u8 reserved_at_0[0x8]; 10262 u8 local_port[0x8]; 10263 u8 reserved_at_10[0x10]; 10264 struct mlx5_ifc_qpdpm_dscp_reg_bits dscp[64]; 10265 }; 10266 10267 struct mlx5_ifc_qpts_reg_bits { 10268 u8 reserved_at_0[0x8]; 10269 u8 local_port[0x8]; 10270 u8 reserved_at_10[0x2d]; 10271 u8 trust_state[0x3]; 10272 }; 10273 10274 struct mlx5_ifc_pptb_reg_bits { 10275 u8 reserved_at_0[0x2]; 10276 u8 mm[0x2]; 10277 u8 reserved_at_4[0x4]; 10278 u8 local_port[0x8]; 10279 u8 reserved_at_10[0x6]; 10280 u8 cm[0x1]; 10281 u8 um[0x1]; 10282 u8 pm[0x8]; 10283 10284 u8 prio_x_buff[0x20]; 10285 10286 u8 pm_msb[0x8]; 10287 u8 reserved_at_48[0x10]; 10288 u8 ctrl_buff[0x4]; 10289 u8 untagged_buff[0x4]; 10290 }; 10291 10292 struct mlx5_ifc_sbcam_reg_bits { 10293 u8 reserved_at_0[0x8]; 10294 u8 feature_group[0x8]; 10295 u8 reserved_at_10[0x8]; 10296 u8 access_reg_group[0x8]; 10297 10298 u8 reserved_at_20[0x20]; 10299 10300 u8 sb_access_reg_cap_mask[4][0x20]; 10301 10302 u8 reserved_at_c0[0x80]; 10303 10304 u8 sb_feature_cap_mask[4][0x20]; 10305 10306 u8 reserved_at_1c0[0x40]; 10307 10308 u8 cap_total_buffer_size[0x20]; 10309 10310 u8 cap_cell_size[0x10]; 10311 u8 cap_max_pg_buffers[0x8]; 10312 u8 cap_num_pool_supported[0x8]; 10313 10314 u8 reserved_at_240[0x8]; 10315 u8 cap_sbsr_stat_size[0x8]; 10316 u8 cap_max_tclass_data[0x8]; 10317 u8 cap_max_cpu_ingress_tclass_sb[0x8]; 10318 }; 10319 10320 struct mlx5_ifc_pbmc_reg_bits { 10321 u8 reserved_at_0[0x8]; 10322 u8 local_port[0x8]; 10323 u8 reserved_at_10[0x10]; 10324 10325 u8 xoff_timer_value[0x10]; 10326 u8 xoff_refresh[0x10]; 10327 10328 u8 reserved_at_40[0x9]; 10329 u8 fullness_threshold[0x7]; 10330 u8 port_buffer_size[0x10]; 10331 10332 struct mlx5_ifc_bufferx_reg_bits buffer[10]; 10333 10334 u8 reserved_at_2e0[0x80]; 10335 }; 10336 10337 struct mlx5_ifc_qtct_reg_bits { 10338 u8 reserved_at_0[0x8]; 10339 u8 port_number[0x8]; 10340 u8 reserved_at_10[0xd]; 10341 u8 prio[0x3]; 10342 10343 u8 reserved_at_20[0x1d]; 10344 u8 tclass[0x3]; 10345 }; 10346 10347 struct mlx5_ifc_mcia_reg_bits { 10348 u8 l[0x1]; 10349 u8 reserved_at_1[0x7]; 10350 u8 module[0x8]; 10351 u8 reserved_at_10[0x8]; 10352 u8 status[0x8]; 10353 10354 u8 i2c_device_address[0x8]; 10355 u8 page_number[0x8]; 10356 u8 device_address[0x10]; 10357 10358 u8 reserved_at_40[0x10]; 10359 u8 size[0x10]; 10360 10361 u8 reserved_at_60[0x20]; 10362 10363 u8 dword_0[0x20]; 10364 u8 dword_1[0x20]; 10365 u8 dword_2[0x20]; 10366 u8 dword_3[0x20]; 10367 u8 dword_4[0x20]; 10368 u8 dword_5[0x20]; 10369 u8 dword_6[0x20]; 10370 u8 dword_7[0x20]; 10371 u8 dword_8[0x20]; 10372 u8 dword_9[0x20]; 10373 u8 dword_10[0x20]; 10374 u8 dword_11[0x20]; 10375 }; 10376 10377 struct mlx5_ifc_dcbx_param_bits { 10378 u8 dcbx_cee_cap[0x1]; 10379 u8 dcbx_ieee_cap[0x1]; 10380 u8 dcbx_standby_cap[0x1]; 10381 u8 reserved_at_3[0x5]; 10382 u8 port_number[0x8]; 10383 u8 reserved_at_10[0xa]; 10384 u8 max_application_table_size[6]; 10385 u8 reserved_at_20[0x15]; 10386 u8 version_oper[0x3]; 10387 u8 reserved_at_38[5]; 10388 u8 version_admin[0x3]; 10389 u8 willing_admin[0x1]; 10390 u8 reserved_at_41[0x3]; 10391 u8 pfc_cap_oper[0x4]; 10392 u8 reserved_at_48[0x4]; 10393 u8 pfc_cap_admin[0x4]; 10394 u8 reserved_at_50[0x4]; 10395 u8 num_of_tc_oper[0x4]; 10396 u8 reserved_at_58[0x4]; 10397 u8 num_of_tc_admin[0x4]; 10398 u8 remote_willing[0x1]; 10399 u8 reserved_at_61[3]; 10400 u8 remote_pfc_cap[4]; 10401 u8 reserved_at_68[0x14]; 10402 u8 remote_num_of_tc[0x4]; 10403 u8 reserved_at_80[0x18]; 10404 u8 error[0x8]; 10405 u8 reserved_at_a0[0x160]; 10406 }; 10407 10408 struct mlx5_ifc_lagc_bits { 10409 u8 fdb_selection_mode[0x1]; 10410 u8 reserved_at_1[0x1c]; 10411 u8 lag_state[0x3]; 10412 10413 u8 reserved_at_20[0x14]; 10414 u8 tx_remap_affinity_2[0x4]; 10415 u8 reserved_at_38[0x4]; 10416 u8 tx_remap_affinity_1[0x4]; 10417 }; 10418 10419 struct mlx5_ifc_create_lag_out_bits { 10420 u8 status[0x8]; 10421 u8 reserved_at_8[0x18]; 10422 10423 u8 syndrome[0x20]; 10424 10425 u8 reserved_at_40[0x40]; 10426 }; 10427 10428 struct mlx5_ifc_create_lag_in_bits { 10429 u8 opcode[0x10]; 10430 u8 reserved_at_10[0x10]; 10431 10432 u8 reserved_at_20[0x10]; 10433 u8 op_mod[0x10]; 10434 10435 struct mlx5_ifc_lagc_bits ctx; 10436 }; 10437 10438 struct mlx5_ifc_modify_lag_out_bits { 10439 u8 status[0x8]; 10440 u8 reserved_at_8[0x18]; 10441 10442 u8 syndrome[0x20]; 10443 10444 u8 reserved_at_40[0x40]; 10445 }; 10446 10447 struct mlx5_ifc_modify_lag_in_bits { 10448 u8 opcode[0x10]; 10449 u8 reserved_at_10[0x10]; 10450 10451 u8 reserved_at_20[0x10]; 10452 u8 op_mod[0x10]; 10453 10454 u8 reserved_at_40[0x20]; 10455 u8 field_select[0x20]; 10456 10457 struct mlx5_ifc_lagc_bits ctx; 10458 }; 10459 10460 struct mlx5_ifc_query_lag_out_bits { 10461 u8 status[0x8]; 10462 u8 reserved_at_8[0x18]; 10463 10464 u8 syndrome[0x20]; 10465 10466 struct mlx5_ifc_lagc_bits ctx; 10467 }; 10468 10469 struct mlx5_ifc_query_lag_in_bits { 10470 u8 opcode[0x10]; 10471 u8 reserved_at_10[0x10]; 10472 10473 u8 reserved_at_20[0x10]; 10474 u8 op_mod[0x10]; 10475 10476 u8 reserved_at_40[0x40]; 10477 }; 10478 10479 struct mlx5_ifc_destroy_lag_out_bits { 10480 u8 status[0x8]; 10481 u8 reserved_at_8[0x18]; 10482 10483 u8 syndrome[0x20]; 10484 10485 u8 reserved_at_40[0x40]; 10486 }; 10487 10488 struct mlx5_ifc_destroy_lag_in_bits { 10489 u8 opcode[0x10]; 10490 u8 reserved_at_10[0x10]; 10491 10492 u8 reserved_at_20[0x10]; 10493 u8 op_mod[0x10]; 10494 10495 u8 reserved_at_40[0x40]; 10496 }; 10497 10498 struct mlx5_ifc_create_vport_lag_out_bits { 10499 u8 status[0x8]; 10500 u8 reserved_at_8[0x18]; 10501 10502 u8 syndrome[0x20]; 10503 10504 u8 reserved_at_40[0x40]; 10505 }; 10506 10507 struct mlx5_ifc_create_vport_lag_in_bits { 10508 u8 opcode[0x10]; 10509 u8 reserved_at_10[0x10]; 10510 10511 u8 reserved_at_20[0x10]; 10512 u8 op_mod[0x10]; 10513 10514 u8 reserved_at_40[0x40]; 10515 }; 10516 10517 struct mlx5_ifc_destroy_vport_lag_out_bits { 10518 u8 status[0x8]; 10519 u8 reserved_at_8[0x18]; 10520 10521 u8 syndrome[0x20]; 10522 10523 u8 reserved_at_40[0x40]; 10524 }; 10525 10526 struct mlx5_ifc_destroy_vport_lag_in_bits { 10527 u8 opcode[0x10]; 10528 u8 reserved_at_10[0x10]; 10529 10530 u8 reserved_at_20[0x10]; 10531 u8 op_mod[0x10]; 10532 10533 u8 reserved_at_40[0x40]; 10534 }; 10535 10536 enum { 10537 MLX5_MODIFY_MEMIC_OP_MOD_ALLOC, 10538 MLX5_MODIFY_MEMIC_OP_MOD_DEALLOC, 10539 }; 10540 10541 struct mlx5_ifc_modify_memic_in_bits { 10542 u8 opcode[0x10]; 10543 u8 uid[0x10]; 10544 10545 u8 reserved_at_20[0x10]; 10546 u8 op_mod[0x10]; 10547 10548 u8 reserved_at_40[0x20]; 10549 10550 u8 reserved_at_60[0x18]; 10551 u8 memic_operation_type[0x8]; 10552 10553 u8 memic_start_addr[0x40]; 10554 10555 u8 reserved_at_c0[0x140]; 10556 }; 10557 10558 struct mlx5_ifc_modify_memic_out_bits { 10559 u8 status[0x8]; 10560 u8 reserved_at_8[0x18]; 10561 10562 u8 syndrome[0x20]; 10563 10564 u8 reserved_at_40[0x40]; 10565 10566 u8 memic_operation_addr[0x40]; 10567 10568 u8 reserved_at_c0[0x140]; 10569 }; 10570 10571 struct mlx5_ifc_alloc_memic_in_bits { 10572 u8 opcode[0x10]; 10573 u8 reserved_at_10[0x10]; 10574 10575 u8 reserved_at_20[0x10]; 10576 u8 op_mod[0x10]; 10577 10578 u8 reserved_at_30[0x20]; 10579 10580 u8 reserved_at_40[0x18]; 10581 u8 log_memic_addr_alignment[0x8]; 10582 10583 u8 range_start_addr[0x40]; 10584 10585 u8 range_size[0x20]; 10586 10587 u8 memic_size[0x20]; 10588 }; 10589 10590 struct mlx5_ifc_alloc_memic_out_bits { 10591 u8 status[0x8]; 10592 u8 reserved_at_8[0x18]; 10593 10594 u8 syndrome[0x20]; 10595 10596 u8 memic_start_addr[0x40]; 10597 }; 10598 10599 struct mlx5_ifc_dealloc_memic_in_bits { 10600 u8 opcode[0x10]; 10601 u8 reserved_at_10[0x10]; 10602 10603 u8 reserved_at_20[0x10]; 10604 u8 op_mod[0x10]; 10605 10606 u8 reserved_at_40[0x40]; 10607 10608 u8 memic_start_addr[0x40]; 10609 10610 u8 memic_size[0x20]; 10611 10612 u8 reserved_at_e0[0x20]; 10613 }; 10614 10615 struct mlx5_ifc_dealloc_memic_out_bits { 10616 u8 status[0x8]; 10617 u8 reserved_at_8[0x18]; 10618 10619 u8 syndrome[0x20]; 10620 10621 u8 reserved_at_40[0x40]; 10622 }; 10623 10624 struct mlx5_ifc_general_obj_in_cmd_hdr_bits { 10625 u8 opcode[0x10]; 10626 u8 uid[0x10]; 10627 10628 u8 vhca_tunnel_id[0x10]; 10629 u8 obj_type[0x10]; 10630 10631 u8 obj_id[0x20]; 10632 10633 u8 reserved_at_60[0x20]; 10634 }; 10635 10636 struct mlx5_ifc_general_obj_out_cmd_hdr_bits { 10637 u8 status[0x8]; 10638 u8 reserved_at_8[0x18]; 10639 10640 u8 syndrome[0x20]; 10641 10642 u8 obj_id[0x20]; 10643 10644 u8 reserved_at_60[0x20]; 10645 }; 10646 10647 struct mlx5_ifc_umem_bits { 10648 u8 reserved_at_0[0x80]; 10649 10650 u8 reserved_at_80[0x1b]; 10651 u8 log_page_size[0x5]; 10652 10653 u8 page_offset[0x20]; 10654 10655 u8 num_of_mtt[0x40]; 10656 10657 struct mlx5_ifc_mtt_bits mtt[]; 10658 }; 10659 10660 struct mlx5_ifc_uctx_bits { 10661 u8 cap[0x20]; 10662 10663 u8 reserved_at_20[0x160]; 10664 }; 10665 10666 struct mlx5_ifc_sw_icm_bits { 10667 u8 modify_field_select[0x40]; 10668 10669 u8 reserved_at_40[0x18]; 10670 u8 log_sw_icm_size[0x8]; 10671 10672 u8 reserved_at_60[0x20]; 10673 10674 u8 sw_icm_start_addr[0x40]; 10675 10676 u8 reserved_at_c0[0x140]; 10677 }; 10678 10679 struct mlx5_ifc_geneve_tlv_option_bits { 10680 u8 modify_field_select[0x40]; 10681 10682 u8 reserved_at_40[0x18]; 10683 u8 geneve_option_fte_index[0x8]; 10684 10685 u8 option_class[0x10]; 10686 u8 option_type[0x8]; 10687 u8 reserved_at_78[0x3]; 10688 u8 option_data_length[0x5]; 10689 10690 u8 reserved_at_80[0x180]; 10691 }; 10692 10693 struct mlx5_ifc_create_umem_in_bits { 10694 u8 opcode[0x10]; 10695 u8 uid[0x10]; 10696 10697 u8 reserved_at_20[0x10]; 10698 u8 op_mod[0x10]; 10699 10700 u8 reserved_at_40[0x40]; 10701 10702 struct mlx5_ifc_umem_bits umem; 10703 }; 10704 10705 struct mlx5_ifc_create_umem_out_bits { 10706 u8 status[0x8]; 10707 u8 reserved_at_8[0x18]; 10708 10709 u8 syndrome[0x20]; 10710 10711 u8 reserved_at_40[0x8]; 10712 u8 umem_id[0x18]; 10713 10714 u8 reserved_at_60[0x20]; 10715 }; 10716 10717 struct mlx5_ifc_destroy_umem_in_bits { 10718 u8 opcode[0x10]; 10719 u8 uid[0x10]; 10720 10721 u8 reserved_at_20[0x10]; 10722 u8 op_mod[0x10]; 10723 10724 u8 reserved_at_40[0x8]; 10725 u8 umem_id[0x18]; 10726 10727 u8 reserved_at_60[0x20]; 10728 }; 10729 10730 struct mlx5_ifc_destroy_umem_out_bits { 10731 u8 status[0x8]; 10732 u8 reserved_at_8[0x18]; 10733 10734 u8 syndrome[0x20]; 10735 10736 u8 reserved_at_40[0x40]; 10737 }; 10738 10739 struct mlx5_ifc_create_uctx_in_bits { 10740 u8 opcode[0x10]; 10741 u8 reserved_at_10[0x10]; 10742 10743 u8 reserved_at_20[0x10]; 10744 u8 op_mod[0x10]; 10745 10746 u8 reserved_at_40[0x40]; 10747 10748 struct mlx5_ifc_uctx_bits uctx; 10749 }; 10750 10751 struct mlx5_ifc_create_uctx_out_bits { 10752 u8 status[0x8]; 10753 u8 reserved_at_8[0x18]; 10754 10755 u8 syndrome[0x20]; 10756 10757 u8 reserved_at_40[0x10]; 10758 u8 uid[0x10]; 10759 10760 u8 reserved_at_60[0x20]; 10761 }; 10762 10763 struct mlx5_ifc_destroy_uctx_in_bits { 10764 u8 opcode[0x10]; 10765 u8 reserved_at_10[0x10]; 10766 10767 u8 reserved_at_20[0x10]; 10768 u8 op_mod[0x10]; 10769 10770 u8 reserved_at_40[0x10]; 10771 u8 uid[0x10]; 10772 10773 u8 reserved_at_60[0x20]; 10774 }; 10775 10776 struct mlx5_ifc_destroy_uctx_out_bits { 10777 u8 status[0x8]; 10778 u8 reserved_at_8[0x18]; 10779 10780 u8 syndrome[0x20]; 10781 10782 u8 reserved_at_40[0x40]; 10783 }; 10784 10785 struct mlx5_ifc_create_sw_icm_in_bits { 10786 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 10787 struct mlx5_ifc_sw_icm_bits sw_icm; 10788 }; 10789 10790 struct mlx5_ifc_create_geneve_tlv_option_in_bits { 10791 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 10792 struct mlx5_ifc_geneve_tlv_option_bits geneve_tlv_opt; 10793 }; 10794 10795 struct mlx5_ifc_mtrc_string_db_param_bits { 10796 u8 string_db_base_address[0x20]; 10797 10798 u8 reserved_at_20[0x8]; 10799 u8 string_db_size[0x18]; 10800 }; 10801 10802 struct mlx5_ifc_mtrc_cap_bits { 10803 u8 trace_owner[0x1]; 10804 u8 trace_to_memory[0x1]; 10805 u8 reserved_at_2[0x4]; 10806 u8 trc_ver[0x2]; 10807 u8 reserved_at_8[0x14]; 10808 u8 num_string_db[0x4]; 10809 10810 u8 first_string_trace[0x8]; 10811 u8 num_string_trace[0x8]; 10812 u8 reserved_at_30[0x28]; 10813 10814 u8 log_max_trace_buffer_size[0x8]; 10815 10816 u8 reserved_at_60[0x20]; 10817 10818 struct mlx5_ifc_mtrc_string_db_param_bits string_db_param[8]; 10819 10820 u8 reserved_at_280[0x180]; 10821 }; 10822 10823 struct mlx5_ifc_mtrc_conf_bits { 10824 u8 reserved_at_0[0x1c]; 10825 u8 trace_mode[0x4]; 10826 u8 reserved_at_20[0x18]; 10827 u8 log_trace_buffer_size[0x8]; 10828 u8 trace_mkey[0x20]; 10829 u8 reserved_at_60[0x3a0]; 10830 }; 10831 10832 struct mlx5_ifc_mtrc_stdb_bits { 10833 u8 string_db_index[0x4]; 10834 u8 reserved_at_4[0x4]; 10835 u8 read_size[0x18]; 10836 u8 start_offset[0x20]; 10837 u8 string_db_data[]; 10838 }; 10839 10840 struct mlx5_ifc_mtrc_ctrl_bits { 10841 u8 trace_status[0x2]; 10842 u8 reserved_at_2[0x2]; 10843 u8 arm_event[0x1]; 10844 u8 reserved_at_5[0xb]; 10845 u8 modify_field_select[0x10]; 10846 u8 reserved_at_20[0x2b]; 10847 u8 current_timestamp52_32[0x15]; 10848 u8 current_timestamp31_0[0x20]; 10849 u8 reserved_at_80[0x180]; 10850 }; 10851 10852 struct mlx5_ifc_host_params_context_bits { 10853 u8 host_number[0x8]; 10854 u8 reserved_at_8[0x7]; 10855 u8 host_pf_disabled[0x1]; 10856 u8 host_num_of_vfs[0x10]; 10857 10858 u8 host_total_vfs[0x10]; 10859 u8 host_pci_bus[0x10]; 10860 10861 u8 reserved_at_40[0x10]; 10862 u8 host_pci_device[0x10]; 10863 10864 u8 reserved_at_60[0x10]; 10865 u8 host_pci_function[0x10]; 10866 10867 u8 reserved_at_80[0x180]; 10868 }; 10869 10870 struct mlx5_ifc_query_esw_functions_in_bits { 10871 u8 opcode[0x10]; 10872 u8 reserved_at_10[0x10]; 10873 10874 u8 reserved_at_20[0x10]; 10875 u8 op_mod[0x10]; 10876 10877 u8 reserved_at_40[0x40]; 10878 }; 10879 10880 struct mlx5_ifc_query_esw_functions_out_bits { 10881 u8 status[0x8]; 10882 u8 reserved_at_8[0x18]; 10883 10884 u8 syndrome[0x20]; 10885 10886 u8 reserved_at_40[0x40]; 10887 10888 struct mlx5_ifc_host_params_context_bits host_params_context; 10889 10890 u8 reserved_at_280[0x180]; 10891 u8 host_sf_enable[][0x40]; 10892 }; 10893 10894 struct mlx5_ifc_sf_partition_bits { 10895 u8 reserved_at_0[0x10]; 10896 u8 log_num_sf[0x8]; 10897 u8 log_sf_bar_size[0x8]; 10898 }; 10899 10900 struct mlx5_ifc_query_sf_partitions_out_bits { 10901 u8 status[0x8]; 10902 u8 reserved_at_8[0x18]; 10903 10904 u8 syndrome[0x20]; 10905 10906 u8 reserved_at_40[0x18]; 10907 u8 num_sf_partitions[0x8]; 10908 10909 u8 reserved_at_60[0x20]; 10910 10911 struct mlx5_ifc_sf_partition_bits sf_partition[]; 10912 }; 10913 10914 struct mlx5_ifc_query_sf_partitions_in_bits { 10915 u8 opcode[0x10]; 10916 u8 reserved_at_10[0x10]; 10917 10918 u8 reserved_at_20[0x10]; 10919 u8 op_mod[0x10]; 10920 10921 u8 reserved_at_40[0x40]; 10922 }; 10923 10924 struct mlx5_ifc_dealloc_sf_out_bits { 10925 u8 status[0x8]; 10926 u8 reserved_at_8[0x18]; 10927 10928 u8 syndrome[0x20]; 10929 10930 u8 reserved_at_40[0x40]; 10931 }; 10932 10933 struct mlx5_ifc_dealloc_sf_in_bits { 10934 u8 opcode[0x10]; 10935 u8 reserved_at_10[0x10]; 10936 10937 u8 reserved_at_20[0x10]; 10938 u8 op_mod[0x10]; 10939 10940 u8 reserved_at_40[0x10]; 10941 u8 function_id[0x10]; 10942 10943 u8 reserved_at_60[0x20]; 10944 }; 10945 10946 struct mlx5_ifc_alloc_sf_out_bits { 10947 u8 status[0x8]; 10948 u8 reserved_at_8[0x18]; 10949 10950 u8 syndrome[0x20]; 10951 10952 u8 reserved_at_40[0x40]; 10953 }; 10954 10955 struct mlx5_ifc_alloc_sf_in_bits { 10956 u8 opcode[0x10]; 10957 u8 reserved_at_10[0x10]; 10958 10959 u8 reserved_at_20[0x10]; 10960 u8 op_mod[0x10]; 10961 10962 u8 reserved_at_40[0x10]; 10963 u8 function_id[0x10]; 10964 10965 u8 reserved_at_60[0x20]; 10966 }; 10967 10968 struct mlx5_ifc_affiliated_event_header_bits { 10969 u8 reserved_at_0[0x10]; 10970 u8 obj_type[0x10]; 10971 10972 u8 obj_id[0x20]; 10973 }; 10974 10975 enum { 10976 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = BIT_ULL(0xc), 10977 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_IPSEC = BIT_ULL(0x13), 10978 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_SAMPLER = BIT_ULL(0x20), 10979 }; 10980 10981 enum { 10982 MLX5_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = 0xc, 10983 MLX5_GENERAL_OBJECT_TYPES_IPSEC = 0x13, 10984 MLX5_GENERAL_OBJECT_TYPES_SAMPLER = 0x20, 10985 }; 10986 10987 enum { 10988 MLX5_IPSEC_OBJECT_ICV_LEN_16B, 10989 MLX5_IPSEC_OBJECT_ICV_LEN_12B, 10990 MLX5_IPSEC_OBJECT_ICV_LEN_8B, 10991 }; 10992 10993 struct mlx5_ifc_ipsec_obj_bits { 10994 u8 modify_field_select[0x40]; 10995 u8 full_offload[0x1]; 10996 u8 reserved_at_41[0x1]; 10997 u8 esn_en[0x1]; 10998 u8 esn_overlap[0x1]; 10999 u8 reserved_at_44[0x2]; 11000 u8 icv_length[0x2]; 11001 u8 reserved_at_48[0x4]; 11002 u8 aso_return_reg[0x4]; 11003 u8 reserved_at_50[0x10]; 11004 11005 u8 esn_msb[0x20]; 11006 11007 u8 reserved_at_80[0x8]; 11008 u8 dekn[0x18]; 11009 11010 u8 salt[0x20]; 11011 11012 u8 implicit_iv[0x40]; 11013 11014 u8 reserved_at_100[0x700]; 11015 }; 11016 11017 struct mlx5_ifc_create_ipsec_obj_in_bits { 11018 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 11019 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 11020 }; 11021 11022 enum { 11023 MLX5_MODIFY_IPSEC_BITMASK_ESN_OVERLAP = BIT(0), 11024 MLX5_MODIFY_IPSEC_BITMASK_ESN_MSB = BIT(1), 11025 }; 11026 11027 struct mlx5_ifc_query_ipsec_obj_out_bits { 11028 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 11029 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 11030 }; 11031 11032 struct mlx5_ifc_modify_ipsec_obj_in_bits { 11033 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 11034 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 11035 }; 11036 11037 struct mlx5_ifc_encryption_key_obj_bits { 11038 u8 modify_field_select[0x40]; 11039 11040 u8 reserved_at_40[0x14]; 11041 u8 key_size[0x4]; 11042 u8 reserved_at_58[0x4]; 11043 u8 key_type[0x4]; 11044 11045 u8 reserved_at_60[0x8]; 11046 u8 pd[0x18]; 11047 11048 u8 reserved_at_80[0x180]; 11049 u8 key[8][0x20]; 11050 11051 u8 reserved_at_300[0x500]; 11052 }; 11053 11054 struct mlx5_ifc_create_encryption_key_in_bits { 11055 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 11056 struct mlx5_ifc_encryption_key_obj_bits encryption_key_object; 11057 }; 11058 11059 struct mlx5_ifc_sampler_obj_bits { 11060 u8 modify_field_select[0x40]; 11061 11062 u8 table_type[0x8]; 11063 u8 level[0x8]; 11064 u8 reserved_at_50[0xf]; 11065 u8 ignore_flow_level[0x1]; 11066 11067 u8 sample_ratio[0x20]; 11068 11069 u8 reserved_at_80[0x8]; 11070 u8 sample_table_id[0x18]; 11071 11072 u8 reserved_at_a0[0x8]; 11073 u8 default_table_id[0x18]; 11074 11075 u8 sw_steering_icm_address_rx[0x40]; 11076 u8 sw_steering_icm_address_tx[0x40]; 11077 11078 u8 reserved_at_140[0xa0]; 11079 }; 11080 11081 struct mlx5_ifc_create_sampler_obj_in_bits { 11082 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 11083 struct mlx5_ifc_sampler_obj_bits sampler_object; 11084 }; 11085 11086 enum { 11087 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_128 = 0x0, 11088 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_256 = 0x1, 11089 }; 11090 11091 enum { 11092 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_TYPE_TLS = 0x1, 11093 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_TYPE_IPSEC = 0x2, 11094 }; 11095 11096 struct mlx5_ifc_tls_static_params_bits { 11097 u8 const_2[0x2]; 11098 u8 tls_version[0x4]; 11099 u8 const_1[0x2]; 11100 u8 reserved_at_8[0x14]; 11101 u8 encryption_standard[0x4]; 11102 11103 u8 reserved_at_20[0x20]; 11104 11105 u8 initial_record_number[0x40]; 11106 11107 u8 resync_tcp_sn[0x20]; 11108 11109 u8 gcm_iv[0x20]; 11110 11111 u8 implicit_iv[0x40]; 11112 11113 u8 reserved_at_100[0x8]; 11114 u8 dek_index[0x18]; 11115 11116 u8 reserved_at_120[0xe0]; 11117 }; 11118 11119 struct mlx5_ifc_tls_progress_params_bits { 11120 u8 next_record_tcp_sn[0x20]; 11121 11122 u8 hw_resync_tcp_sn[0x20]; 11123 11124 u8 record_tracker_state[0x2]; 11125 u8 auth_state[0x2]; 11126 u8 reserved_at_44[0x4]; 11127 u8 hw_offset_record_number[0x18]; 11128 }; 11129 11130 enum { 11131 MLX5_MTT_PERM_READ = 1 << 0, 11132 MLX5_MTT_PERM_WRITE = 1 << 1, 11133 MLX5_MTT_PERM_RW = MLX5_MTT_PERM_READ | MLX5_MTT_PERM_WRITE, 11134 }; 11135 11136 #endif /* MLX5_IFC_H */ 11137