1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 #ifndef MLX5_IFC_H 33 #define MLX5_IFC_H 34 35 #include "mlx5_ifc_fpga.h" 36 37 enum { 38 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0, 39 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1, 40 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2, 41 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3, 42 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13, 43 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14, 44 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c, 45 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d, 46 MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4, 47 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5, 48 MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED = 0x7, 49 MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT = 0xc, 50 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10, 51 MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR = 0x11, 52 MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR = 0x12, 53 MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR = 0x8, 54 MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE = 0x9, 55 MLX5_EVENT_TYPE_CODING_GPIO_EVENT = 0x15, 56 MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19, 57 MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a, 58 MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT = 0x1b, 59 MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT = 0x1f, 60 MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa, 61 MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb, 62 MLX5_EVENT_TYPE_CODING_FPGA_ERROR = 0x20, 63 MLX5_EVENT_TYPE_CODING_FPGA_QP_ERROR = 0x21 64 }; 65 66 enum { 67 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0, 68 MLX5_SET_HCA_CAP_OP_MOD_ETHERNET_OFFLOADS = 0x1, 69 MLX5_SET_HCA_CAP_OP_MOD_ODP = 0x2, 70 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3, 71 MLX5_SET_HCA_CAP_OP_MOD_ROCE = 0x4, 72 MLX5_SET_HCA_CAP_OP_MOD_IPSEC = 0x15, 73 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE2 = 0x20, 74 MLX5_SET_HCA_CAP_OP_MOD_PORT_SELECTION = 0x25, 75 }; 76 77 enum { 78 MLX5_SHARED_RESOURCE_UID = 0xffff, 79 }; 80 81 enum { 82 MLX5_OBJ_TYPE_SW_ICM = 0x0008, 83 MLX5_OBJ_TYPE_GENEVE_TLV_OPT = 0x000b, 84 MLX5_OBJ_TYPE_VIRTIO_NET_Q = 0x000d, 85 MLX5_OBJ_TYPE_VIRTIO_Q_COUNTERS = 0x001c, 86 MLX5_OBJ_TYPE_MATCH_DEFINER = 0x0018, 87 MLX5_OBJ_TYPE_HEADER_MODIFY_ARGUMENT = 0x23, 88 MLX5_OBJ_TYPE_STC = 0x0040, 89 MLX5_OBJ_TYPE_RTC = 0x0041, 90 MLX5_OBJ_TYPE_STE = 0x0042, 91 MLX5_OBJ_TYPE_MODIFY_HDR_PATTERN = 0x0043, 92 MLX5_OBJ_TYPE_PAGE_TRACK = 0x46, 93 MLX5_OBJ_TYPE_MKEY = 0xff01, 94 MLX5_OBJ_TYPE_QP = 0xff02, 95 MLX5_OBJ_TYPE_PSV = 0xff03, 96 MLX5_OBJ_TYPE_RMP = 0xff04, 97 MLX5_OBJ_TYPE_XRC_SRQ = 0xff05, 98 MLX5_OBJ_TYPE_RQ = 0xff06, 99 MLX5_OBJ_TYPE_SQ = 0xff07, 100 MLX5_OBJ_TYPE_TIR = 0xff08, 101 MLX5_OBJ_TYPE_TIS = 0xff09, 102 MLX5_OBJ_TYPE_DCT = 0xff0a, 103 MLX5_OBJ_TYPE_XRQ = 0xff0b, 104 MLX5_OBJ_TYPE_RQT = 0xff0e, 105 MLX5_OBJ_TYPE_FLOW_COUNTER = 0xff0f, 106 MLX5_OBJ_TYPE_CQ = 0xff10, 107 MLX5_OBJ_TYPE_FT_ALIAS = 0xff15, 108 }; 109 110 enum { 111 MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM = (1ULL << MLX5_OBJ_TYPE_SW_ICM), 112 MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT = (1ULL << 11), 113 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q = (1ULL << 13), 114 MLX5_GENERAL_OBJ_TYPES_CAP_HEADER_MODIFY_ARGUMENT = 115 (1ULL << MLX5_OBJ_TYPE_HEADER_MODIFY_ARGUMENT), 116 MLX5_GENERAL_OBJ_TYPES_CAP_MACSEC_OFFLOAD = (1ULL << 39), 117 }; 118 119 enum { 120 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100, 121 MLX5_CMD_OP_QUERY_ADAPTER = 0x101, 122 MLX5_CMD_OP_INIT_HCA = 0x102, 123 MLX5_CMD_OP_TEARDOWN_HCA = 0x103, 124 MLX5_CMD_OP_ENABLE_HCA = 0x104, 125 MLX5_CMD_OP_DISABLE_HCA = 0x105, 126 MLX5_CMD_OP_QUERY_PAGES = 0x107, 127 MLX5_CMD_OP_MANAGE_PAGES = 0x108, 128 MLX5_CMD_OP_SET_HCA_CAP = 0x109, 129 MLX5_CMD_OP_QUERY_ISSI = 0x10a, 130 MLX5_CMD_OP_SET_ISSI = 0x10b, 131 MLX5_CMD_OP_SET_DRIVER_VERSION = 0x10d, 132 MLX5_CMD_OP_QUERY_SF_PARTITION = 0x111, 133 MLX5_CMD_OP_ALLOC_SF = 0x113, 134 MLX5_CMD_OP_DEALLOC_SF = 0x114, 135 MLX5_CMD_OP_SUSPEND_VHCA = 0x115, 136 MLX5_CMD_OP_RESUME_VHCA = 0x116, 137 MLX5_CMD_OP_QUERY_VHCA_MIGRATION_STATE = 0x117, 138 MLX5_CMD_OP_SAVE_VHCA_STATE = 0x118, 139 MLX5_CMD_OP_LOAD_VHCA_STATE = 0x119, 140 MLX5_CMD_OP_CREATE_MKEY = 0x200, 141 MLX5_CMD_OP_QUERY_MKEY = 0x201, 142 MLX5_CMD_OP_DESTROY_MKEY = 0x202, 143 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203, 144 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204, 145 MLX5_CMD_OP_ALLOC_MEMIC = 0x205, 146 MLX5_CMD_OP_DEALLOC_MEMIC = 0x206, 147 MLX5_CMD_OP_MODIFY_MEMIC = 0x207, 148 MLX5_CMD_OP_CREATE_EQ = 0x301, 149 MLX5_CMD_OP_DESTROY_EQ = 0x302, 150 MLX5_CMD_OP_QUERY_EQ = 0x303, 151 MLX5_CMD_OP_GEN_EQE = 0x304, 152 MLX5_CMD_OP_CREATE_CQ = 0x400, 153 MLX5_CMD_OP_DESTROY_CQ = 0x401, 154 MLX5_CMD_OP_QUERY_CQ = 0x402, 155 MLX5_CMD_OP_MODIFY_CQ = 0x403, 156 MLX5_CMD_OP_CREATE_QP = 0x500, 157 MLX5_CMD_OP_DESTROY_QP = 0x501, 158 MLX5_CMD_OP_RST2INIT_QP = 0x502, 159 MLX5_CMD_OP_INIT2RTR_QP = 0x503, 160 MLX5_CMD_OP_RTR2RTS_QP = 0x504, 161 MLX5_CMD_OP_RTS2RTS_QP = 0x505, 162 MLX5_CMD_OP_SQERR2RTS_QP = 0x506, 163 MLX5_CMD_OP_2ERR_QP = 0x507, 164 MLX5_CMD_OP_2RST_QP = 0x50a, 165 MLX5_CMD_OP_QUERY_QP = 0x50b, 166 MLX5_CMD_OP_SQD_RTS_QP = 0x50c, 167 MLX5_CMD_OP_INIT2INIT_QP = 0x50e, 168 MLX5_CMD_OP_CREATE_PSV = 0x600, 169 MLX5_CMD_OP_DESTROY_PSV = 0x601, 170 MLX5_CMD_OP_CREATE_SRQ = 0x700, 171 MLX5_CMD_OP_DESTROY_SRQ = 0x701, 172 MLX5_CMD_OP_QUERY_SRQ = 0x702, 173 MLX5_CMD_OP_ARM_RQ = 0x703, 174 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705, 175 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706, 176 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707, 177 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708, 178 MLX5_CMD_OP_CREATE_DCT = 0x710, 179 MLX5_CMD_OP_DESTROY_DCT = 0x711, 180 MLX5_CMD_OP_DRAIN_DCT = 0x712, 181 MLX5_CMD_OP_QUERY_DCT = 0x713, 182 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714, 183 MLX5_CMD_OP_CREATE_XRQ = 0x717, 184 MLX5_CMD_OP_DESTROY_XRQ = 0x718, 185 MLX5_CMD_OP_QUERY_XRQ = 0x719, 186 MLX5_CMD_OP_ARM_XRQ = 0x71a, 187 MLX5_CMD_OP_QUERY_XRQ_DC_PARAMS_ENTRY = 0x725, 188 MLX5_CMD_OP_SET_XRQ_DC_PARAMS_ENTRY = 0x726, 189 MLX5_CMD_OP_QUERY_XRQ_ERROR_PARAMS = 0x727, 190 MLX5_CMD_OP_RELEASE_XRQ_ERROR = 0x729, 191 MLX5_CMD_OP_MODIFY_XRQ = 0x72a, 192 MLX5_CMD_OPCODE_QUERY_DELEGATED_VHCA = 0x732, 193 MLX5_CMD_OPCODE_CREATE_ESW_VPORT = 0x733, 194 MLX5_CMD_OPCODE_DESTROY_ESW_VPORT = 0x734, 195 MLX5_CMD_OP_QUERY_ESW_FUNCTIONS = 0x740, 196 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750, 197 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751, 198 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752, 199 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753, 200 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754, 201 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755, 202 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760, 203 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761, 204 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762, 205 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763, 206 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764, 207 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765, 208 MLX5_CMD_OP_QUERY_VNIC_ENV = 0x76f, 209 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770, 210 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771, 211 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772, 212 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773, 213 MLX5_CMD_OP_SET_MONITOR_COUNTER = 0x774, 214 MLX5_CMD_OP_ARM_MONITOR_COUNTER = 0x775, 215 MLX5_CMD_OP_SET_PP_RATE_LIMIT = 0x780, 216 MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781, 217 MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT = 0x782, 218 MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT = 0x783, 219 MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT = 0x784, 220 MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT = 0x785, 221 MLX5_CMD_OP_CREATE_QOS_PARA_VPORT = 0x786, 222 MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT = 0x787, 223 MLX5_CMD_OP_ALLOC_PD = 0x800, 224 MLX5_CMD_OP_DEALLOC_PD = 0x801, 225 MLX5_CMD_OP_ALLOC_UAR = 0x802, 226 MLX5_CMD_OP_DEALLOC_UAR = 0x803, 227 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804, 228 MLX5_CMD_OP_ACCESS_REG = 0x805, 229 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806, 230 MLX5_CMD_OP_DETACH_FROM_MCG = 0x807, 231 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a, 232 MLX5_CMD_OP_MAD_IFC = 0x50d, 233 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b, 234 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c, 235 MLX5_CMD_OP_NOP = 0x80d, 236 MLX5_CMD_OP_ALLOC_XRCD = 0x80e, 237 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f, 238 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816, 239 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817, 240 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822, 241 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823, 242 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824, 243 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825, 244 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826, 245 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827, 246 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828, 247 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829, 248 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a, 249 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b, 250 MLX5_CMD_OP_SET_WOL_ROL = 0x830, 251 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831, 252 MLX5_CMD_OP_CREATE_LAG = 0x840, 253 MLX5_CMD_OP_MODIFY_LAG = 0x841, 254 MLX5_CMD_OP_QUERY_LAG = 0x842, 255 MLX5_CMD_OP_DESTROY_LAG = 0x843, 256 MLX5_CMD_OP_CREATE_VPORT_LAG = 0x844, 257 MLX5_CMD_OP_DESTROY_VPORT_LAG = 0x845, 258 MLX5_CMD_OP_CREATE_TIR = 0x900, 259 MLX5_CMD_OP_MODIFY_TIR = 0x901, 260 MLX5_CMD_OP_DESTROY_TIR = 0x902, 261 MLX5_CMD_OP_QUERY_TIR = 0x903, 262 MLX5_CMD_OP_CREATE_SQ = 0x904, 263 MLX5_CMD_OP_MODIFY_SQ = 0x905, 264 MLX5_CMD_OP_DESTROY_SQ = 0x906, 265 MLX5_CMD_OP_QUERY_SQ = 0x907, 266 MLX5_CMD_OP_CREATE_RQ = 0x908, 267 MLX5_CMD_OP_MODIFY_RQ = 0x909, 268 MLX5_CMD_OP_SET_DELAY_DROP_PARAMS = 0x910, 269 MLX5_CMD_OP_DESTROY_RQ = 0x90a, 270 MLX5_CMD_OP_QUERY_RQ = 0x90b, 271 MLX5_CMD_OP_CREATE_RMP = 0x90c, 272 MLX5_CMD_OP_MODIFY_RMP = 0x90d, 273 MLX5_CMD_OP_DESTROY_RMP = 0x90e, 274 MLX5_CMD_OP_QUERY_RMP = 0x90f, 275 MLX5_CMD_OP_CREATE_TIS = 0x912, 276 MLX5_CMD_OP_MODIFY_TIS = 0x913, 277 MLX5_CMD_OP_DESTROY_TIS = 0x914, 278 MLX5_CMD_OP_QUERY_TIS = 0x915, 279 MLX5_CMD_OP_CREATE_RQT = 0x916, 280 MLX5_CMD_OP_MODIFY_RQT = 0x917, 281 MLX5_CMD_OP_DESTROY_RQT = 0x918, 282 MLX5_CMD_OP_QUERY_RQT = 0x919, 283 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f, 284 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930, 285 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931, 286 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932, 287 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933, 288 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934, 289 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935, 290 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936, 291 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937, 292 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938, 293 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939, 294 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a, 295 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b, 296 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c, 297 MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT = 0x93d, 298 MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT = 0x93e, 299 MLX5_CMD_OP_QUERY_PACKET_REFORMAT_CONTEXT = 0x93f, 300 MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT = 0x940, 301 MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941, 302 MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT = 0x942, 303 MLX5_CMD_OP_FPGA_CREATE_QP = 0x960, 304 MLX5_CMD_OP_FPGA_MODIFY_QP = 0x961, 305 MLX5_CMD_OP_FPGA_QUERY_QP = 0x962, 306 MLX5_CMD_OP_FPGA_DESTROY_QP = 0x963, 307 MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS = 0x964, 308 MLX5_CMD_OP_CREATE_GENERAL_OBJECT = 0xa00, 309 MLX5_CMD_OP_MODIFY_GENERAL_OBJECT = 0xa01, 310 MLX5_CMD_OP_QUERY_GENERAL_OBJECT = 0xa02, 311 MLX5_CMD_OP_DESTROY_GENERAL_OBJECT = 0xa03, 312 MLX5_CMD_OP_CREATE_UCTX = 0xa04, 313 MLX5_CMD_OP_DESTROY_UCTX = 0xa06, 314 MLX5_CMD_OP_CREATE_UMEM = 0xa08, 315 MLX5_CMD_OP_DESTROY_UMEM = 0xa0a, 316 MLX5_CMD_OP_SYNC_STEERING = 0xb00, 317 MLX5_CMD_OP_PSP_GEN_SPI = 0xb10, 318 MLX5_CMD_OP_PSP_ROTATE_KEY = 0xb11, 319 MLX5_CMD_OP_QUERY_VHCA_STATE = 0xb0d, 320 MLX5_CMD_OP_MODIFY_VHCA_STATE = 0xb0e, 321 MLX5_CMD_OP_SYNC_CRYPTO = 0xb12, 322 MLX5_CMD_OP_ALLOW_OTHER_VHCA_ACCESS = 0xb16, 323 MLX5_CMD_OP_GENERATE_WQE = 0xb17, 324 MLX5_CMD_OPCODE_QUERY_VUID = 0xb22, 325 MLX5_CMD_OP_MAX 326 }; 327 328 /* Valid range for general commands that don't work over an object */ 329 enum { 330 MLX5_CMD_OP_GENERAL_START = 0xb00, 331 MLX5_CMD_OP_GENERAL_END = 0xd00, 332 }; 333 334 enum { 335 MLX5_FT_NIC_RX_2_NIC_RX_RDMA = BIT(0), 336 MLX5_FT_NIC_TX_RDMA_2_NIC_TX = BIT(1), 337 }; 338 339 enum { 340 MLX5_CMD_OP_MOD_UPDATE_HEADER_MODIFY_ARGUMENT = 0x1, 341 }; 342 343 struct mlx5_ifc_flow_table_fields_supported_bits { 344 u8 outer_dmac[0x1]; 345 u8 outer_smac[0x1]; 346 u8 outer_ether_type[0x1]; 347 u8 outer_ip_version[0x1]; 348 u8 outer_first_prio[0x1]; 349 u8 outer_first_cfi[0x1]; 350 u8 outer_first_vid[0x1]; 351 u8 outer_ipv4_ttl[0x1]; 352 u8 outer_second_prio[0x1]; 353 u8 outer_second_cfi[0x1]; 354 u8 outer_second_vid[0x1]; 355 u8 reserved_at_b[0x1]; 356 u8 outer_sip[0x1]; 357 u8 outer_dip[0x1]; 358 u8 outer_frag[0x1]; 359 u8 outer_ip_protocol[0x1]; 360 u8 outer_ip_ecn[0x1]; 361 u8 outer_ip_dscp[0x1]; 362 u8 outer_udp_sport[0x1]; 363 u8 outer_udp_dport[0x1]; 364 u8 outer_tcp_sport[0x1]; 365 u8 outer_tcp_dport[0x1]; 366 u8 outer_tcp_flags[0x1]; 367 u8 outer_gre_protocol[0x1]; 368 u8 outer_gre_key[0x1]; 369 u8 outer_vxlan_vni[0x1]; 370 u8 outer_geneve_vni[0x1]; 371 u8 outer_geneve_oam[0x1]; 372 u8 outer_geneve_protocol_type[0x1]; 373 u8 outer_geneve_opt_len[0x1]; 374 u8 source_vhca_port[0x1]; 375 u8 source_eswitch_port[0x1]; 376 377 u8 inner_dmac[0x1]; 378 u8 inner_smac[0x1]; 379 u8 inner_ether_type[0x1]; 380 u8 inner_ip_version[0x1]; 381 u8 inner_first_prio[0x1]; 382 u8 inner_first_cfi[0x1]; 383 u8 inner_first_vid[0x1]; 384 u8 reserved_at_27[0x1]; 385 u8 inner_second_prio[0x1]; 386 u8 inner_second_cfi[0x1]; 387 u8 inner_second_vid[0x1]; 388 u8 reserved_at_2b[0x1]; 389 u8 inner_sip[0x1]; 390 u8 inner_dip[0x1]; 391 u8 inner_frag[0x1]; 392 u8 inner_ip_protocol[0x1]; 393 u8 inner_ip_ecn[0x1]; 394 u8 inner_ip_dscp[0x1]; 395 u8 inner_udp_sport[0x1]; 396 u8 inner_udp_dport[0x1]; 397 u8 inner_tcp_sport[0x1]; 398 u8 inner_tcp_dport[0x1]; 399 u8 inner_tcp_flags[0x1]; 400 u8 reserved_at_37[0x9]; 401 402 u8 geneve_tlv_option_0_data[0x1]; 403 u8 geneve_tlv_option_0_exist[0x1]; 404 u8 reserved_at_42[0x3]; 405 u8 outer_first_mpls_over_udp[0x4]; 406 u8 outer_first_mpls_over_gre[0x4]; 407 u8 inner_first_mpls[0x4]; 408 u8 outer_first_mpls[0x4]; 409 u8 reserved_at_55[0x2]; 410 u8 outer_esp_spi[0x1]; 411 u8 reserved_at_58[0x2]; 412 u8 bth_dst_qp[0x1]; 413 u8 reserved_at_5b[0x5]; 414 415 u8 reserved_at_60[0x18]; 416 u8 metadata_reg_c_7[0x1]; 417 u8 metadata_reg_c_6[0x1]; 418 u8 metadata_reg_c_5[0x1]; 419 u8 metadata_reg_c_4[0x1]; 420 u8 metadata_reg_c_3[0x1]; 421 u8 metadata_reg_c_2[0x1]; 422 u8 metadata_reg_c_1[0x1]; 423 u8 metadata_reg_c_0[0x1]; 424 }; 425 426 /* Table 2170 - Flow Table Fields Supported 2 Format */ 427 struct mlx5_ifc_flow_table_fields_supported_2_bits { 428 u8 inner_l4_type_ext[0x1]; 429 u8 outer_l4_type_ext[0x1]; 430 u8 inner_l4_type[0x1]; 431 u8 outer_l4_type[0x1]; 432 u8 reserved_at_4[0xa]; 433 u8 bth_opcode[0x1]; 434 u8 reserved_at_f[0x1]; 435 u8 tunnel_header_0_1[0x1]; 436 u8 reserved_at_11[0xf]; 437 438 u8 reserved_at_20[0xf]; 439 u8 ipsec_next_header[0x1]; 440 u8 reserved_at_30[0x10]; 441 442 u8 reserved_at_40[0x40]; 443 }; 444 445 struct mlx5_ifc_flow_table_prop_layout_bits { 446 u8 ft_support[0x1]; 447 u8 reserved_at_1[0x1]; 448 u8 flow_counter[0x1]; 449 u8 flow_modify_en[0x1]; 450 u8 modify_root[0x1]; 451 u8 identified_miss_table_mode[0x1]; 452 u8 flow_table_modify[0x1]; 453 u8 reformat[0x1]; 454 u8 decap[0x1]; 455 u8 reset_root_to_default[0x1]; 456 u8 pop_vlan[0x1]; 457 u8 push_vlan[0x1]; 458 u8 reserved_at_c[0x1]; 459 u8 pop_vlan_2[0x1]; 460 u8 push_vlan_2[0x1]; 461 u8 reformat_and_vlan_action[0x1]; 462 u8 reserved_at_10[0x1]; 463 u8 sw_owner[0x1]; 464 u8 reformat_l3_tunnel_to_l2[0x1]; 465 u8 reformat_l2_to_l3_tunnel[0x1]; 466 u8 reformat_and_modify_action[0x1]; 467 u8 ignore_flow_level[0x1]; 468 u8 reserved_at_16[0x1]; 469 u8 table_miss_action_domain[0x1]; 470 u8 termination_table[0x1]; 471 u8 reformat_and_fwd_to_table[0x1]; 472 u8 reserved_at_1a[0x2]; 473 u8 ipsec_encrypt[0x1]; 474 u8 ipsec_decrypt[0x1]; 475 u8 sw_owner_v2[0x1]; 476 u8 reserved_at_1f[0x1]; 477 478 u8 termination_table_raw_traffic[0x1]; 479 u8 reserved_at_21[0x1]; 480 u8 log_max_ft_size[0x6]; 481 u8 log_max_modify_header_context[0x8]; 482 u8 max_modify_header_actions[0x8]; 483 u8 max_ft_level[0x8]; 484 485 u8 reformat_add_esp_trasport[0x1]; 486 u8 reformat_l2_to_l3_esp_tunnel[0x1]; 487 u8 reformat_add_esp_transport_over_udp[0x1]; 488 u8 reformat_del_esp_trasport[0x1]; 489 u8 reformat_l3_esp_tunnel_to_l2[0x1]; 490 u8 reformat_del_esp_transport_over_udp[0x1]; 491 u8 execute_aso[0x1]; 492 u8 reserved_at_47[0x19]; 493 494 u8 reformat_l2_to_l3_psp_tunnel[0x1]; 495 u8 reformat_l3_psp_tunnel_to_l2[0x1]; 496 u8 reformat_insert[0x1]; 497 u8 reformat_remove[0x1]; 498 u8 macsec_encrypt[0x1]; 499 u8 macsec_decrypt[0x1]; 500 u8 psp_encrypt[0x1]; 501 u8 psp_decrypt[0x1]; 502 u8 reformat_add_macsec[0x1]; 503 u8 reformat_remove_macsec[0x1]; 504 u8 reparse[0x1]; 505 u8 reserved_at_6b[0x1]; 506 u8 cross_vhca_object[0x1]; 507 u8 reformat_l2_to_l3_audp_tunnel[0x1]; 508 u8 reformat_l3_audp_tunnel_to_l2[0x1]; 509 u8 ignore_flow_level_rtc_valid[0x1]; 510 u8 reserved_at_70[0x8]; 511 u8 log_max_ft_num[0x8]; 512 513 u8 reserved_at_80[0x10]; 514 u8 log_max_flow_counter[0x8]; 515 u8 log_max_destination[0x8]; 516 517 u8 reserved_at_a0[0x18]; 518 u8 log_max_flow[0x8]; 519 520 u8 reserved_at_c0[0x40]; 521 522 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support; 523 524 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support; 525 }; 526 527 struct mlx5_ifc_odp_per_transport_service_cap_bits { 528 u8 send[0x1]; 529 u8 receive[0x1]; 530 u8 write[0x1]; 531 u8 read[0x1]; 532 u8 atomic[0x1]; 533 u8 srq_receive[0x1]; 534 u8 reserved_at_6[0x1a]; 535 }; 536 537 struct mlx5_ifc_ipv4_layout_bits { 538 u8 reserved_at_0[0x60]; 539 540 u8 ipv4[0x20]; 541 }; 542 543 struct mlx5_ifc_ipv6_layout_bits { 544 u8 ipv6[16][0x8]; 545 }; 546 547 struct mlx5_ifc_ipv6_simple_layout_bits { 548 u8 ipv6_127_96[0x20]; 549 u8 ipv6_95_64[0x20]; 550 u8 ipv6_63_32[0x20]; 551 u8 ipv6_31_0[0x20]; 552 }; 553 554 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits { 555 struct mlx5_ifc_ipv6_simple_layout_bits ipv6_simple_layout; 556 struct mlx5_ifc_ipv6_layout_bits ipv6_layout; 557 struct mlx5_ifc_ipv4_layout_bits ipv4_layout; 558 u8 reserved_at_0[0x80]; 559 }; 560 561 enum { 562 MLX5_PACKET_L4_TYPE_NONE, 563 MLX5_PACKET_L4_TYPE_TCP, 564 MLX5_PACKET_L4_TYPE_UDP, 565 }; 566 567 enum { 568 MLX5_PACKET_L4_TYPE_EXT_NONE, 569 MLX5_PACKET_L4_TYPE_EXT_TCP, 570 MLX5_PACKET_L4_TYPE_EXT_UDP, 571 MLX5_PACKET_L4_TYPE_EXT_ICMP, 572 }; 573 574 struct mlx5_ifc_fte_match_set_lyr_2_4_bits { 575 u8 smac_47_16[0x20]; 576 577 u8 smac_15_0[0x10]; 578 u8 ethertype[0x10]; 579 580 u8 dmac_47_16[0x20]; 581 582 u8 dmac_15_0[0x10]; 583 u8 first_prio[0x3]; 584 u8 first_cfi[0x1]; 585 u8 first_vid[0xc]; 586 587 u8 ip_protocol[0x8]; 588 u8 ip_dscp[0x6]; 589 u8 ip_ecn[0x2]; 590 u8 cvlan_tag[0x1]; 591 u8 svlan_tag[0x1]; 592 u8 frag[0x1]; 593 u8 ip_version[0x4]; 594 u8 tcp_flags[0x9]; 595 596 u8 tcp_sport[0x10]; 597 u8 tcp_dport[0x10]; 598 599 u8 l4_type[0x2]; 600 u8 l4_type_ext[0x4]; 601 u8 reserved_at_c6[0xa]; 602 u8 ipv4_ihl[0x4]; 603 u8 reserved_at_d4[0x4]; 604 u8 ttl_hoplimit[0x8]; 605 606 u8 udp_sport[0x10]; 607 u8 udp_dport[0x10]; 608 609 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6; 610 611 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6; 612 }; 613 614 struct mlx5_ifc_nvgre_key_bits { 615 u8 hi[0x18]; 616 u8 lo[0x8]; 617 }; 618 619 union mlx5_ifc_gre_key_bits { 620 struct mlx5_ifc_nvgre_key_bits nvgre; 621 u8 key[0x20]; 622 }; 623 624 struct mlx5_ifc_fte_match_set_misc_bits { 625 u8 gre_c_present[0x1]; 626 u8 reserved_at_1[0x1]; 627 u8 gre_k_present[0x1]; 628 u8 gre_s_present[0x1]; 629 u8 source_vhca_port[0x4]; 630 u8 source_sqn[0x18]; 631 632 u8 source_eswitch_owner_vhca_id[0x10]; 633 u8 source_port[0x10]; 634 635 u8 outer_second_prio[0x3]; 636 u8 outer_second_cfi[0x1]; 637 u8 outer_second_vid[0xc]; 638 u8 inner_second_prio[0x3]; 639 u8 inner_second_cfi[0x1]; 640 u8 inner_second_vid[0xc]; 641 642 u8 outer_second_cvlan_tag[0x1]; 643 u8 inner_second_cvlan_tag[0x1]; 644 u8 outer_second_svlan_tag[0x1]; 645 u8 inner_second_svlan_tag[0x1]; 646 u8 reserved_at_64[0xc]; 647 u8 gre_protocol[0x10]; 648 649 union mlx5_ifc_gre_key_bits gre_key; 650 651 u8 vxlan_vni[0x18]; 652 u8 bth_opcode[0x8]; 653 654 u8 geneve_vni[0x18]; 655 u8 reserved_at_d8[0x6]; 656 u8 geneve_tlv_option_0_exist[0x1]; 657 u8 geneve_oam[0x1]; 658 659 u8 reserved_at_e0[0xc]; 660 u8 outer_ipv6_flow_label[0x14]; 661 662 u8 reserved_at_100[0xc]; 663 u8 inner_ipv6_flow_label[0x14]; 664 665 u8 reserved_at_120[0xa]; 666 u8 geneve_opt_len[0x6]; 667 u8 geneve_protocol_type[0x10]; 668 669 u8 reserved_at_140[0x8]; 670 u8 bth_dst_qp[0x18]; 671 u8 inner_esp_spi[0x20]; 672 u8 outer_esp_spi[0x20]; 673 u8 reserved_at_1a0[0x60]; 674 }; 675 676 struct mlx5_ifc_fte_match_mpls_bits { 677 u8 mpls_label[0x14]; 678 u8 mpls_exp[0x3]; 679 u8 mpls_s_bos[0x1]; 680 u8 mpls_ttl[0x8]; 681 }; 682 683 struct mlx5_ifc_fte_match_set_misc2_bits { 684 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls; 685 686 struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls; 687 688 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre; 689 690 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp; 691 692 u8 metadata_reg_c_7[0x20]; 693 694 u8 metadata_reg_c_6[0x20]; 695 696 u8 metadata_reg_c_5[0x20]; 697 698 u8 metadata_reg_c_4[0x20]; 699 700 u8 metadata_reg_c_3[0x20]; 701 702 u8 metadata_reg_c_2[0x20]; 703 704 u8 metadata_reg_c_1[0x20]; 705 706 u8 metadata_reg_c_0[0x20]; 707 708 u8 metadata_reg_a[0x20]; 709 710 u8 psp_syndrome[0x8]; 711 u8 macsec_syndrome[0x8]; 712 u8 ipsec_syndrome[0x8]; 713 u8 ipsec_next_header[0x8]; 714 715 u8 reserved_at_1c0[0x40]; 716 }; 717 718 struct mlx5_ifc_fte_match_set_misc3_bits { 719 u8 inner_tcp_seq_num[0x20]; 720 721 u8 outer_tcp_seq_num[0x20]; 722 723 u8 inner_tcp_ack_num[0x20]; 724 725 u8 outer_tcp_ack_num[0x20]; 726 727 u8 reserved_at_80[0x8]; 728 u8 outer_vxlan_gpe_vni[0x18]; 729 730 u8 outer_vxlan_gpe_next_protocol[0x8]; 731 u8 outer_vxlan_gpe_flags[0x8]; 732 u8 reserved_at_b0[0x10]; 733 734 u8 icmp_header_data[0x20]; 735 736 u8 icmpv6_header_data[0x20]; 737 738 u8 icmp_type[0x8]; 739 u8 icmp_code[0x8]; 740 u8 icmpv6_type[0x8]; 741 u8 icmpv6_code[0x8]; 742 743 u8 geneve_tlv_option_0_data[0x20]; 744 745 u8 gtpu_teid[0x20]; 746 747 u8 gtpu_msg_type[0x8]; 748 u8 gtpu_msg_flags[0x8]; 749 u8 reserved_at_170[0x10]; 750 751 u8 gtpu_dw_2[0x20]; 752 753 u8 gtpu_first_ext_dw_0[0x20]; 754 755 u8 gtpu_dw_0[0x20]; 756 757 u8 reserved_at_1e0[0x20]; 758 }; 759 760 struct mlx5_ifc_fte_match_set_misc4_bits { 761 u8 prog_sample_field_value_0[0x20]; 762 763 u8 prog_sample_field_id_0[0x20]; 764 765 u8 prog_sample_field_value_1[0x20]; 766 767 u8 prog_sample_field_id_1[0x20]; 768 769 u8 prog_sample_field_value_2[0x20]; 770 771 u8 prog_sample_field_id_2[0x20]; 772 773 u8 prog_sample_field_value_3[0x20]; 774 775 u8 prog_sample_field_id_3[0x20]; 776 777 u8 reserved_at_100[0x100]; 778 }; 779 780 struct mlx5_ifc_fte_match_set_misc5_bits { 781 u8 macsec_tag_0[0x20]; 782 783 u8 macsec_tag_1[0x20]; 784 785 u8 macsec_tag_2[0x20]; 786 787 u8 macsec_tag_3[0x20]; 788 789 u8 tunnel_header_0[0x20]; 790 791 u8 tunnel_header_1[0x20]; 792 793 u8 tunnel_header_2[0x20]; 794 795 u8 tunnel_header_3[0x20]; 796 797 u8 reserved_at_100[0x100]; 798 }; 799 800 struct mlx5_ifc_cmd_pas_bits { 801 u8 pa_h[0x20]; 802 803 u8 pa_l[0x14]; 804 u8 reserved_at_34[0xc]; 805 }; 806 807 struct mlx5_ifc_uint64_bits { 808 u8 hi[0x20]; 809 810 u8 lo[0x20]; 811 }; 812 813 enum { 814 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0, 815 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7, 816 MLX5_ADS_STAT_RATE_10GBPS = 0x8, 817 MLX5_ADS_STAT_RATE_30GBPS = 0x9, 818 MLX5_ADS_STAT_RATE_5GBPS = 0xa, 819 MLX5_ADS_STAT_RATE_20GBPS = 0xb, 820 MLX5_ADS_STAT_RATE_40GBPS = 0xc, 821 MLX5_ADS_STAT_RATE_60GBPS = 0xd, 822 MLX5_ADS_STAT_RATE_80GBPS = 0xe, 823 MLX5_ADS_STAT_RATE_120GBPS = 0xf, 824 }; 825 826 struct mlx5_ifc_ads_bits { 827 u8 fl[0x1]; 828 u8 free_ar[0x1]; 829 u8 reserved_at_2[0xe]; 830 u8 pkey_index[0x10]; 831 832 u8 plane_index[0x8]; 833 u8 grh[0x1]; 834 u8 mlid[0x7]; 835 u8 rlid[0x10]; 836 837 u8 ack_timeout[0x5]; 838 u8 reserved_at_45[0x3]; 839 u8 src_addr_index[0x8]; 840 u8 reserved_at_50[0x4]; 841 u8 stat_rate[0x4]; 842 u8 hop_limit[0x8]; 843 844 u8 reserved_at_60[0x4]; 845 u8 tclass[0x8]; 846 u8 flow_label[0x14]; 847 848 u8 rgid_rip[16][0x8]; 849 850 u8 reserved_at_100[0x4]; 851 u8 f_dscp[0x1]; 852 u8 f_ecn[0x1]; 853 u8 reserved_at_106[0x1]; 854 u8 f_eth_prio[0x1]; 855 u8 ecn[0x2]; 856 u8 dscp[0x6]; 857 u8 udp_sport[0x10]; 858 859 u8 dei_cfi[0x1]; 860 u8 eth_prio[0x3]; 861 u8 sl[0x4]; 862 u8 vhca_port_num[0x8]; 863 u8 rmac_47_32[0x10]; 864 865 u8 rmac_31_0[0x20]; 866 }; 867 868 struct mlx5_ifc_flow_table_nic_cap_bits { 869 u8 nic_rx_multi_path_tirs[0x1]; 870 u8 nic_rx_multi_path_tirs_fts[0x1]; 871 u8 allow_sniffer_and_nic_rx_shared_tir[0x1]; 872 u8 reserved_at_3[0x4]; 873 u8 sw_owner_reformat_supported[0x1]; 874 u8 reserved_at_8[0x18]; 875 876 u8 encap_general_header[0x1]; 877 u8 reserved_at_21[0xa]; 878 u8 log_max_packet_reformat_context[0x5]; 879 u8 reserved_at_30[0x6]; 880 u8 max_encap_header_size[0xa]; 881 u8 reserved_at_40[0x1c0]; 882 883 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive; 884 885 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_rdma; 886 887 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer; 888 889 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit; 890 891 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_rdma; 892 893 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer; 894 895 u8 reserved_at_e00[0x600]; 896 897 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_receive; 898 899 u8 reserved_at_1480[0x80]; 900 901 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_receive_rdma; 902 903 u8 reserved_at_1580[0x280]; 904 905 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_transmit_rdma; 906 907 u8 reserved_at_1880[0x780]; 908 909 u8 sw_steering_nic_rx_action_drop_icm_address[0x40]; 910 911 u8 sw_steering_nic_tx_action_drop_icm_address[0x40]; 912 913 u8 sw_steering_nic_tx_action_allow_icm_address[0x40]; 914 915 u8 reserved_at_20c0[0x5f40]; 916 }; 917 918 struct mlx5_ifc_port_selection_cap_bits { 919 u8 reserved_at_0[0x10]; 920 u8 port_select_flow_table[0x1]; 921 u8 reserved_at_11[0x1]; 922 u8 port_select_flow_table_bypass[0x1]; 923 u8 reserved_at_13[0xd]; 924 925 u8 reserved_at_20[0x1e0]; 926 927 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_port_selection; 928 929 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_port_selection; 930 931 u8 reserved_at_480[0x7b80]; 932 }; 933 934 enum { 935 MLX5_FDB_TO_VPORT_REG_C_0 = 0x01, 936 MLX5_FDB_TO_VPORT_REG_C_1 = 0x02, 937 MLX5_FDB_TO_VPORT_REG_C_2 = 0x04, 938 MLX5_FDB_TO_VPORT_REG_C_3 = 0x08, 939 MLX5_FDB_TO_VPORT_REG_C_4 = 0x10, 940 MLX5_FDB_TO_VPORT_REG_C_5 = 0x20, 941 MLX5_FDB_TO_VPORT_REG_C_6 = 0x40, 942 MLX5_FDB_TO_VPORT_REG_C_7 = 0x80, 943 }; 944 945 struct mlx5_ifc_flow_table_eswitch_cap_bits { 946 u8 fdb_to_vport_reg_c_id[0x8]; 947 u8 reserved_at_8[0x5]; 948 u8 fdb_uplink_hairpin[0x1]; 949 u8 fdb_multi_path_any_table_limit_regc[0x1]; 950 u8 reserved_at_f[0x1]; 951 u8 fdb_dynamic_tunnel[0x1]; 952 u8 reserved_at_11[0x1]; 953 u8 fdb_multi_path_any_table[0x1]; 954 u8 reserved_at_13[0x2]; 955 u8 fdb_modify_header_fwd_to_table[0x1]; 956 u8 fdb_ipv4_ttl_modify[0x1]; 957 u8 flow_source[0x1]; 958 u8 reserved_at_18[0x2]; 959 u8 multi_fdb_encap[0x1]; 960 u8 egress_acl_forward_to_vport[0x1]; 961 u8 fdb_multi_path_to_table[0x1]; 962 u8 reserved_at_1d[0x3]; 963 964 u8 reserved_at_20[0x1e0]; 965 966 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb; 967 968 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress; 969 970 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress; 971 972 u8 reserved_at_800[0xC00]; 973 974 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_esw_fdb; 975 976 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_bitmask_support_2_esw_fdb; 977 978 u8 reserved_at_1500[0x300]; 979 980 u8 sw_steering_fdb_action_drop_icm_address_rx[0x40]; 981 982 u8 sw_steering_fdb_action_drop_icm_address_tx[0x40]; 983 984 u8 sw_steering_uplink_icm_address_rx[0x40]; 985 986 u8 sw_steering_uplink_icm_address_tx[0x40]; 987 988 u8 reserved_at_1900[0x6700]; 989 }; 990 991 struct mlx5_ifc_wqe_based_flow_table_cap_bits { 992 u8 reserved_at_0[0x3]; 993 u8 log_max_num_ste[0x5]; 994 u8 reserved_at_8[0x3]; 995 u8 log_max_num_stc[0x5]; 996 u8 reserved_at_10[0x3]; 997 u8 log_max_num_rtc[0x5]; 998 u8 reserved_at_18[0x3]; 999 u8 log_max_num_header_modify_pattern[0x5]; 1000 1001 u8 rtc_hash_split_table[0x1]; 1002 u8 rtc_linear_lookup_table[0x1]; 1003 u8 reserved_at_22[0x1]; 1004 u8 stc_alloc_log_granularity[0x5]; 1005 u8 reserved_at_28[0x3]; 1006 u8 stc_alloc_log_max[0x5]; 1007 u8 reserved_at_30[0x3]; 1008 u8 ste_alloc_log_granularity[0x5]; 1009 u8 reserved_at_38[0x3]; 1010 u8 ste_alloc_log_max[0x5]; 1011 1012 u8 reserved_at_40[0xb]; 1013 u8 rtc_reparse_mode[0x5]; 1014 u8 reserved_at_50[0x3]; 1015 u8 rtc_index_mode[0x5]; 1016 u8 reserved_at_58[0x3]; 1017 u8 rtc_log_depth_max[0x5]; 1018 1019 u8 reserved_at_60[0x10]; 1020 u8 ste_format[0x10]; 1021 1022 u8 stc_action_type[0x80]; 1023 1024 u8 header_insert_type[0x10]; 1025 u8 header_remove_type[0x10]; 1026 1027 u8 trivial_match_definer[0x20]; 1028 1029 u8 reserved_at_140[0x1b]; 1030 u8 rtc_max_num_hash_definer_gen_wqe[0x5]; 1031 1032 u8 reserved_at_160[0x18]; 1033 u8 access_index_mode[0x8]; 1034 1035 u8 reserved_at_180[0x10]; 1036 u8 ste_format_gen_wqe[0x10]; 1037 1038 u8 linear_match_definer_reg_c3[0x20]; 1039 1040 u8 fdb_jump_to_tir_stc[0x1]; 1041 u8 reserved_at_1c1[0x1f]; 1042 }; 1043 1044 struct mlx5_ifc_esw_cap_bits { 1045 u8 reserved_at_0[0x1d]; 1046 u8 merged_eswitch[0x1]; 1047 u8 reserved_at_1e[0x2]; 1048 1049 u8 reserved_at_20[0x40]; 1050 1051 u8 esw_manager_vport_number_valid[0x1]; 1052 u8 reserved_at_61[0xf]; 1053 u8 esw_manager_vport_number[0x10]; 1054 1055 u8 reserved_at_80[0x780]; 1056 }; 1057 1058 enum { 1059 MLX5_COUNTER_SOURCE_ESWITCH = 0x0, 1060 MLX5_COUNTER_FLOW_ESWITCH = 0x1, 1061 }; 1062 1063 struct mlx5_ifc_e_switch_cap_bits { 1064 u8 vport_svlan_strip[0x1]; 1065 u8 vport_cvlan_strip[0x1]; 1066 u8 vport_svlan_insert[0x1]; 1067 u8 vport_cvlan_insert_if_not_exist[0x1]; 1068 u8 vport_cvlan_insert_overwrite[0x1]; 1069 u8 reserved_at_5[0x1]; 1070 u8 vport_cvlan_insert_always[0x1]; 1071 u8 esw_shared_ingress_acl[0x1]; 1072 u8 esw_uplink_ingress_acl[0x1]; 1073 u8 root_ft_on_other_esw[0x1]; 1074 u8 reserved_at_a[0xf]; 1075 u8 esw_functions_changed[0x1]; 1076 u8 reserved_at_1a[0x1]; 1077 u8 ecpf_vport_exists[0x1]; 1078 u8 counter_eswitch_affinity[0x1]; 1079 u8 merged_eswitch[0x1]; 1080 u8 nic_vport_node_guid_modify[0x1]; 1081 u8 nic_vport_port_guid_modify[0x1]; 1082 1083 u8 vxlan_encap_decap[0x1]; 1084 u8 nvgre_encap_decap[0x1]; 1085 u8 reserved_at_22[0x1]; 1086 u8 log_max_fdb_encap_uplink[0x5]; 1087 u8 reserved_at_21[0x3]; 1088 u8 log_max_packet_reformat_context[0x5]; 1089 u8 reserved_2b[0x6]; 1090 u8 max_encap_header_size[0xa]; 1091 1092 u8 reserved_at_40[0xb]; 1093 u8 log_max_esw_sf[0x5]; 1094 u8 esw_sf_base_id[0x10]; 1095 1096 u8 reserved_at_60[0x7a0]; 1097 1098 }; 1099 1100 struct mlx5_ifc_qos_cap_bits { 1101 u8 packet_pacing[0x1]; 1102 u8 esw_scheduling[0x1]; 1103 u8 esw_bw_share[0x1]; 1104 u8 esw_rate_limit[0x1]; 1105 u8 reserved_at_4[0x1]; 1106 u8 packet_pacing_burst_bound[0x1]; 1107 u8 packet_pacing_typical_size[0x1]; 1108 u8 reserved_at_7[0x1]; 1109 u8 nic_sq_scheduling[0x1]; 1110 u8 nic_bw_share[0x1]; 1111 u8 nic_rate_limit[0x1]; 1112 u8 packet_pacing_uid[0x1]; 1113 u8 log_esw_max_sched_depth[0x4]; 1114 u8 reserved_at_10[0x10]; 1115 1116 u8 reserved_at_20[0x9]; 1117 u8 esw_cross_esw_sched[0x1]; 1118 u8 reserved_at_2a[0x1]; 1119 u8 log_max_qos_nic_queue_group[0x5]; 1120 u8 reserved_at_30[0x10]; 1121 1122 u8 packet_pacing_max_rate[0x20]; 1123 1124 u8 packet_pacing_min_rate[0x20]; 1125 1126 u8 reserved_at_80[0xb]; 1127 u8 log_esw_max_rate_limit[0x5]; 1128 u8 packet_pacing_rate_table_size[0x10]; 1129 1130 u8 esw_element_type[0x10]; 1131 u8 esw_tsar_type[0x10]; 1132 1133 u8 reserved_at_c0[0x10]; 1134 u8 max_qos_para_vport[0x10]; 1135 1136 u8 max_tsar_bw_share[0x20]; 1137 1138 u8 nic_element_type[0x10]; 1139 u8 nic_tsar_type[0x10]; 1140 1141 u8 reserved_at_120[0x3]; 1142 u8 log_meter_aso_granularity[0x5]; 1143 u8 reserved_at_128[0x3]; 1144 u8 log_meter_aso_max_alloc[0x5]; 1145 u8 reserved_at_130[0x3]; 1146 u8 log_max_num_meter_aso[0x5]; 1147 u8 reserved_at_138[0x8]; 1148 1149 u8 reserved_at_140[0x6c0]; 1150 }; 1151 1152 struct mlx5_ifc_debug_cap_bits { 1153 u8 core_dump_general[0x1]; 1154 u8 core_dump_qp[0x1]; 1155 u8 reserved_at_2[0x7]; 1156 u8 resource_dump[0x1]; 1157 u8 reserved_at_a[0x16]; 1158 1159 u8 reserved_at_20[0x2]; 1160 u8 stall_detect[0x1]; 1161 u8 reserved_at_23[0x1d]; 1162 1163 u8 reserved_at_40[0x7c0]; 1164 }; 1165 1166 struct mlx5_ifc_per_protocol_networking_offload_caps_bits { 1167 u8 csum_cap[0x1]; 1168 u8 vlan_cap[0x1]; 1169 u8 lro_cap[0x1]; 1170 u8 lro_psh_flag[0x1]; 1171 u8 lro_time_stamp[0x1]; 1172 u8 reserved_at_5[0x2]; 1173 u8 wqe_vlan_insert[0x1]; 1174 u8 self_lb_en_modifiable[0x1]; 1175 u8 reserved_at_9[0x2]; 1176 u8 max_lso_cap[0x5]; 1177 u8 multi_pkt_send_wqe[0x2]; 1178 u8 wqe_inline_mode[0x2]; 1179 u8 rss_ind_tbl_cap[0x4]; 1180 u8 reg_umr_sq[0x1]; 1181 u8 scatter_fcs[0x1]; 1182 u8 enhanced_multi_pkt_send_wqe[0x1]; 1183 u8 tunnel_lso_const_out_ip_id[0x1]; 1184 u8 tunnel_lro_gre[0x1]; 1185 u8 tunnel_lro_vxlan[0x1]; 1186 u8 tunnel_stateless_gre[0x1]; 1187 u8 tunnel_stateless_vxlan[0x1]; 1188 1189 u8 swp[0x1]; 1190 u8 swp_csum[0x1]; 1191 u8 swp_lso[0x1]; 1192 u8 cqe_checksum_full[0x1]; 1193 u8 tunnel_stateless_geneve_tx[0x1]; 1194 u8 tunnel_stateless_mpls_over_udp[0x1]; 1195 u8 tunnel_stateless_mpls_over_gre[0x1]; 1196 u8 tunnel_stateless_vxlan_gpe[0x1]; 1197 u8 tunnel_stateless_ipv4_over_vxlan[0x1]; 1198 u8 tunnel_stateless_ip_over_ip[0x1]; 1199 u8 insert_trailer[0x1]; 1200 u8 reserved_at_2b[0x1]; 1201 u8 tunnel_stateless_ip_over_ip_rx[0x1]; 1202 u8 tunnel_stateless_ip_over_ip_tx[0x1]; 1203 u8 reserved_at_2e[0x2]; 1204 u8 max_vxlan_udp_ports[0x8]; 1205 u8 swp_csum_l4_partial[0x1]; 1206 u8 reserved_at_39[0x5]; 1207 u8 max_geneve_opt_len[0x1]; 1208 u8 tunnel_stateless_geneve_rx[0x1]; 1209 1210 u8 reserved_at_40[0x10]; 1211 u8 lro_min_mss_size[0x10]; 1212 1213 u8 reserved_at_60[0x120]; 1214 1215 u8 lro_timer_supported_periods[4][0x20]; 1216 1217 u8 reserved_at_200[0x600]; 1218 }; 1219 1220 enum { 1221 MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING = 0x0, 1222 MLX5_TIMESTAMP_FORMAT_CAP_REAL_TIME = 0x1, 1223 MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING_AND_REAL_TIME = 0x2, 1224 }; 1225 1226 struct mlx5_ifc_roce_cap_bits { 1227 u8 roce_apm[0x1]; 1228 u8 reserved_at_1[0x3]; 1229 u8 sw_r_roce_src_udp_port[0x1]; 1230 u8 fl_rc_qp_when_roce_disabled[0x1]; 1231 u8 fl_rc_qp_when_roce_enabled[0x1]; 1232 u8 roce_cc_general[0x1]; 1233 u8 qp_ooo_transmit_default[0x1]; 1234 u8 reserved_at_9[0x15]; 1235 u8 qp_ts_format[0x2]; 1236 1237 u8 reserved_at_20[0x60]; 1238 1239 u8 reserved_at_80[0xc]; 1240 u8 l3_type[0x4]; 1241 u8 reserved_at_90[0x8]; 1242 u8 roce_version[0x8]; 1243 1244 u8 reserved_at_a0[0x10]; 1245 u8 r_roce_dest_udp_port[0x10]; 1246 1247 u8 r_roce_max_src_udp_port[0x10]; 1248 u8 r_roce_min_src_udp_port[0x10]; 1249 1250 u8 reserved_at_e0[0x10]; 1251 u8 roce_address_table_size[0x10]; 1252 1253 u8 reserved_at_100[0x700]; 1254 }; 1255 1256 struct mlx5_ifc_sync_steering_in_bits { 1257 u8 opcode[0x10]; 1258 u8 uid[0x10]; 1259 1260 u8 reserved_at_20[0x10]; 1261 u8 op_mod[0x10]; 1262 1263 u8 reserved_at_40[0xc0]; 1264 }; 1265 1266 struct mlx5_ifc_sync_steering_out_bits { 1267 u8 status[0x8]; 1268 u8 reserved_at_8[0x18]; 1269 1270 u8 syndrome[0x20]; 1271 1272 u8 reserved_at_40[0x40]; 1273 }; 1274 1275 struct mlx5_ifc_sync_crypto_in_bits { 1276 u8 opcode[0x10]; 1277 u8 uid[0x10]; 1278 1279 u8 reserved_at_20[0x10]; 1280 u8 op_mod[0x10]; 1281 1282 u8 reserved_at_40[0x20]; 1283 1284 u8 reserved_at_60[0x10]; 1285 u8 crypto_type[0x10]; 1286 1287 u8 reserved_at_80[0x80]; 1288 }; 1289 1290 struct mlx5_ifc_sync_crypto_out_bits { 1291 u8 status[0x8]; 1292 u8 reserved_at_8[0x18]; 1293 1294 u8 syndrome[0x20]; 1295 1296 u8 reserved_at_40[0x40]; 1297 }; 1298 1299 struct mlx5_ifc_device_mem_cap_bits { 1300 u8 memic[0x1]; 1301 u8 reserved_at_1[0x1f]; 1302 1303 u8 reserved_at_20[0xb]; 1304 u8 log_min_memic_alloc_size[0x5]; 1305 u8 reserved_at_30[0x8]; 1306 u8 log_max_memic_addr_alignment[0x8]; 1307 1308 u8 memic_bar_start_addr[0x40]; 1309 1310 u8 memic_bar_size[0x20]; 1311 1312 u8 max_memic_size[0x20]; 1313 1314 u8 steering_sw_icm_start_address[0x40]; 1315 1316 u8 reserved_at_100[0x8]; 1317 u8 log_header_modify_sw_icm_size[0x8]; 1318 u8 reserved_at_110[0x2]; 1319 u8 log_sw_icm_alloc_granularity[0x6]; 1320 u8 log_steering_sw_icm_size[0x8]; 1321 1322 u8 log_indirect_encap_sw_icm_size[0x8]; 1323 u8 reserved_at_128[0x10]; 1324 u8 log_header_modify_pattern_sw_icm_size[0x8]; 1325 1326 u8 header_modify_sw_icm_start_address[0x40]; 1327 1328 u8 reserved_at_180[0x40]; 1329 1330 u8 header_modify_pattern_sw_icm_start_address[0x40]; 1331 1332 u8 memic_operations[0x20]; 1333 1334 u8 reserved_at_220[0x20]; 1335 1336 u8 indirect_encap_sw_icm_start_address[0x40]; 1337 1338 u8 reserved_at_280[0x580]; 1339 }; 1340 1341 struct mlx5_ifc_device_event_cap_bits { 1342 u8 user_affiliated_events[4][0x40]; 1343 1344 u8 user_unaffiliated_events[4][0x40]; 1345 }; 1346 1347 struct mlx5_ifc_virtio_emulation_cap_bits { 1348 u8 desc_tunnel_offload_type[0x1]; 1349 u8 eth_frame_offload_type[0x1]; 1350 u8 virtio_version_1_0[0x1]; 1351 u8 device_features_bits_mask[0xd]; 1352 u8 event_mode[0x8]; 1353 u8 virtio_queue_type[0x8]; 1354 1355 u8 max_tunnel_desc[0x10]; 1356 u8 reserved_at_30[0x3]; 1357 u8 log_doorbell_stride[0x5]; 1358 u8 reserved_at_38[0x3]; 1359 u8 log_doorbell_bar_size[0x5]; 1360 1361 u8 doorbell_bar_offset[0x40]; 1362 1363 u8 max_emulated_devices[0x8]; 1364 u8 max_num_virtio_queues[0x18]; 1365 1366 u8 reserved_at_a0[0x20]; 1367 1368 u8 reserved_at_c0[0x13]; 1369 u8 desc_group_mkey_supported[0x1]; 1370 u8 freeze_to_rdy_supported[0x1]; 1371 u8 reserved_at_d5[0xb]; 1372 1373 u8 reserved_at_e0[0x20]; 1374 1375 u8 umem_1_buffer_param_a[0x20]; 1376 1377 u8 umem_1_buffer_param_b[0x20]; 1378 1379 u8 umem_2_buffer_param_a[0x20]; 1380 1381 u8 umem_2_buffer_param_b[0x20]; 1382 1383 u8 umem_3_buffer_param_a[0x20]; 1384 1385 u8 umem_3_buffer_param_b[0x20]; 1386 1387 u8 reserved_at_1c0[0x640]; 1388 }; 1389 1390 enum { 1391 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0, 1392 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2, 1393 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4, 1394 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8, 1395 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10, 1396 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20, 1397 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40, 1398 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80, 1399 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100, 1400 }; 1401 1402 enum { 1403 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1, 1404 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2, 1405 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4, 1406 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8, 1407 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10, 1408 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20, 1409 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40, 1410 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80, 1411 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100, 1412 }; 1413 1414 struct mlx5_ifc_atomic_caps_bits { 1415 u8 reserved_at_0[0x40]; 1416 1417 u8 atomic_req_8B_endianness_mode[0x2]; 1418 u8 reserved_at_42[0x4]; 1419 u8 supported_atomic_req_8B_endianness_mode_1[0x1]; 1420 1421 u8 reserved_at_47[0x19]; 1422 1423 u8 reserved_at_60[0x20]; 1424 1425 u8 reserved_at_80[0x10]; 1426 u8 atomic_operations[0x10]; 1427 1428 u8 reserved_at_a0[0x10]; 1429 u8 atomic_size_qp[0x10]; 1430 1431 u8 reserved_at_c0[0x10]; 1432 u8 atomic_size_dc[0x10]; 1433 1434 u8 reserved_at_e0[0x720]; 1435 }; 1436 1437 struct mlx5_ifc_odp_scheme_cap_bits { 1438 u8 reserved_at_0[0x40]; 1439 1440 u8 sig[0x1]; 1441 u8 reserved_at_41[0x4]; 1442 u8 page_prefetch[0x1]; 1443 u8 reserved_at_46[0x1a]; 1444 1445 u8 reserved_at_60[0x20]; 1446 1447 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps; 1448 1449 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps; 1450 1451 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps; 1452 1453 struct mlx5_ifc_odp_per_transport_service_cap_bits xrc_odp_caps; 1454 1455 struct mlx5_ifc_odp_per_transport_service_cap_bits dc_odp_caps; 1456 1457 u8 reserved_at_120[0xe0]; 1458 }; 1459 1460 struct mlx5_ifc_odp_cap_bits { 1461 struct mlx5_ifc_odp_scheme_cap_bits transport_page_fault_scheme_cap; 1462 1463 struct mlx5_ifc_odp_scheme_cap_bits memory_page_fault_scheme_cap; 1464 1465 u8 reserved_at_400[0x200]; 1466 1467 u8 mem_page_fault[0x1]; 1468 u8 reserved_at_601[0x1f]; 1469 1470 u8 reserved_at_620[0x1e0]; 1471 }; 1472 1473 struct mlx5_ifc_tls_cap_bits { 1474 u8 tls_1_2_aes_gcm_128[0x1]; 1475 u8 tls_1_3_aes_gcm_128[0x1]; 1476 u8 tls_1_2_aes_gcm_256[0x1]; 1477 u8 tls_1_3_aes_gcm_256[0x1]; 1478 u8 reserved_at_4[0x1c]; 1479 1480 u8 reserved_at_20[0x7e0]; 1481 }; 1482 1483 struct mlx5_ifc_ipsec_cap_bits { 1484 u8 ipsec_full_offload[0x1]; 1485 u8 ipsec_crypto_offload[0x1]; 1486 u8 ipsec_esn[0x1]; 1487 u8 ipsec_crypto_esp_aes_gcm_256_encrypt[0x1]; 1488 u8 ipsec_crypto_esp_aes_gcm_128_encrypt[0x1]; 1489 u8 ipsec_crypto_esp_aes_gcm_256_decrypt[0x1]; 1490 u8 ipsec_crypto_esp_aes_gcm_128_decrypt[0x1]; 1491 u8 reserved_at_7[0x4]; 1492 u8 log_max_ipsec_offload[0x5]; 1493 u8 reserved_at_10[0x10]; 1494 1495 u8 min_log_ipsec_full_replay_window[0x8]; 1496 u8 max_log_ipsec_full_replay_window[0x8]; 1497 u8 reserved_at_30[0x7d0]; 1498 }; 1499 1500 struct mlx5_ifc_macsec_cap_bits { 1501 u8 macsec_epn[0x1]; 1502 u8 reserved_at_1[0x2]; 1503 u8 macsec_crypto_esp_aes_gcm_256_encrypt[0x1]; 1504 u8 macsec_crypto_esp_aes_gcm_128_encrypt[0x1]; 1505 u8 macsec_crypto_esp_aes_gcm_256_decrypt[0x1]; 1506 u8 macsec_crypto_esp_aes_gcm_128_decrypt[0x1]; 1507 u8 reserved_at_7[0x4]; 1508 u8 log_max_macsec_offload[0x5]; 1509 u8 reserved_at_10[0x10]; 1510 1511 u8 min_log_macsec_full_replay_window[0x8]; 1512 u8 max_log_macsec_full_replay_window[0x8]; 1513 u8 reserved_at_30[0x10]; 1514 1515 u8 reserved_at_40[0x7c0]; 1516 }; 1517 1518 struct mlx5_ifc_psp_cap_bits { 1519 u8 reserved_at_0[0x1]; 1520 u8 psp_crypto_offload[0x1]; 1521 u8 reserved_at_2[0x1]; 1522 u8 psp_crypto_esp_aes_gcm_256_encrypt[0x1]; 1523 u8 psp_crypto_esp_aes_gcm_128_encrypt[0x1]; 1524 u8 psp_crypto_esp_aes_gcm_256_decrypt[0x1]; 1525 u8 psp_crypto_esp_aes_gcm_128_decrypt[0x1]; 1526 u8 reserved_at_7[0x4]; 1527 u8 log_max_num_of_psp_spi[0x5]; 1528 u8 reserved_at_10[0x10]; 1529 1530 u8 reserved_at_20[0x7e0]; 1531 }; 1532 1533 enum { 1534 MLX5_WQ_TYPE_LINKED_LIST = 0x0, 1535 MLX5_WQ_TYPE_CYCLIC = 0x1, 1536 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2, 1537 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3, 1538 }; 1539 1540 enum { 1541 MLX5_WQ_END_PAD_MODE_NONE = 0x0, 1542 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1, 1543 }; 1544 1545 enum { 1546 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0, 1547 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1, 1548 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2, 1549 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3, 1550 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4, 1551 }; 1552 1553 enum { 1554 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0, 1555 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1, 1556 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2, 1557 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3, 1558 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4, 1559 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5, 1560 }; 1561 1562 enum { 1563 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0, 1564 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1, 1565 }; 1566 1567 enum { 1568 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0, 1569 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1, 1570 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3, 1571 }; 1572 1573 enum { 1574 MLX5_CAP_PORT_TYPE_IB = 0x0, 1575 MLX5_CAP_PORT_TYPE_ETH = 0x1, 1576 }; 1577 1578 enum { 1579 MLX5_CAP_UMR_FENCE_STRONG = 0x0, 1580 MLX5_CAP_UMR_FENCE_SMALL = 0x1, 1581 MLX5_CAP_UMR_FENCE_NONE = 0x2, 1582 }; 1583 1584 enum { 1585 MLX5_FLEX_IPV4_OVER_VXLAN_ENABLED = 1 << 0, 1586 MLX5_FLEX_IPV6_OVER_VXLAN_ENABLED = 1 << 1, 1587 MLX5_FLEX_IPV6_OVER_IP_ENABLED = 1 << 2, 1588 MLX5_FLEX_PARSER_GENEVE_ENABLED = 1 << 3, 1589 MLX5_FLEX_PARSER_MPLS_OVER_GRE_ENABLED = 1 << 4, 1590 MLX5_FLEX_PARSER_MPLS_OVER_UDP_ENABLED = 1 << 5, 1591 MLX5_FLEX_P_BIT_VXLAN_GPE_ENABLED = 1 << 6, 1592 MLX5_FLEX_PARSER_VXLAN_GPE_ENABLED = 1 << 7, 1593 MLX5_FLEX_PARSER_ICMP_V4_ENABLED = 1 << 8, 1594 MLX5_FLEX_PARSER_ICMP_V6_ENABLED = 1 << 9, 1595 MLX5_FLEX_PARSER_GENEVE_TLV_OPTION_0_ENABLED = 1 << 10, 1596 MLX5_FLEX_PARSER_GTPU_ENABLED = 1 << 11, 1597 MLX5_FLEX_PARSER_GTPU_DW_2_ENABLED = 1 << 16, 1598 MLX5_FLEX_PARSER_GTPU_FIRST_EXT_DW_0_ENABLED = 1 << 17, 1599 MLX5_FLEX_PARSER_GTPU_DW_0_ENABLED = 1 << 18, 1600 MLX5_FLEX_PARSER_GTPU_TEID_ENABLED = 1 << 19, 1601 }; 1602 1603 enum { 1604 MLX5_UCTX_CAP_RAW_TX = 1UL << 0, 1605 MLX5_UCTX_CAP_INTERNAL_DEV_RES = 1UL << 1, 1606 MLX5_UCTX_CAP_RDMA_CTRL = 1UL << 3, 1607 MLX5_UCTX_CAP_RDMA_CTRL_OTHER_VHCA = 1UL << 4, 1608 }; 1609 1610 #define MLX5_FC_BULK_SIZE_FACTOR 128 1611 1612 enum mlx5_fc_bulk_alloc_bitmask { 1613 MLX5_FC_BULK_128 = (1 << 0), 1614 MLX5_FC_BULK_256 = (1 << 1), 1615 MLX5_FC_BULK_512 = (1 << 2), 1616 MLX5_FC_BULK_1024 = (1 << 3), 1617 MLX5_FC_BULK_2048 = (1 << 4), 1618 MLX5_FC_BULK_4096 = (1 << 5), 1619 MLX5_FC_BULK_8192 = (1 << 6), 1620 MLX5_FC_BULK_16384 = (1 << 7), 1621 }; 1622 1623 #define MLX5_FC_BULK_NUM_FCS(fc_enum) (MLX5_FC_BULK_SIZE_FACTOR * (fc_enum)) 1624 1625 #define MLX5_FT_MAX_MULTIPATH_LEVEL 63 1626 1627 enum { 1628 MLX5_STEERING_FORMAT_CONNECTX_5 = 0, 1629 MLX5_STEERING_FORMAT_CONNECTX_6DX = 1, 1630 MLX5_STEERING_FORMAT_CONNECTX_7 = 2, 1631 MLX5_STEERING_FORMAT_CONNECTX_8 = 3, 1632 }; 1633 1634 struct mlx5_ifc_cmd_hca_cap_bits { 1635 u8 reserved_at_0[0x6]; 1636 u8 page_request_disable[0x1]; 1637 u8 abs_native_port_num[0x1]; 1638 u8 reserved_at_8[0x8]; 1639 u8 shared_object_to_user_object_allowed[0x1]; 1640 u8 reserved_at_13[0xe]; 1641 u8 vhca_resource_manager[0x1]; 1642 1643 u8 hca_cap_2[0x1]; 1644 u8 create_lag_when_not_master_up[0x1]; 1645 u8 dtor[0x1]; 1646 u8 event_on_vhca_state_teardown_request[0x1]; 1647 u8 event_on_vhca_state_in_use[0x1]; 1648 u8 event_on_vhca_state_active[0x1]; 1649 u8 event_on_vhca_state_allocated[0x1]; 1650 u8 event_on_vhca_state_invalid[0x1]; 1651 u8 reserved_at_28[0x8]; 1652 u8 vhca_id[0x10]; 1653 1654 u8 reserved_at_40[0x40]; 1655 1656 u8 log_max_srq_sz[0x8]; 1657 u8 log_max_qp_sz[0x8]; 1658 u8 event_cap[0x1]; 1659 u8 reserved_at_91[0x2]; 1660 u8 isolate_vl_tc_new[0x1]; 1661 u8 reserved_at_94[0x4]; 1662 u8 prio_tag_required[0x1]; 1663 u8 reserved_at_99[0x2]; 1664 u8 log_max_qp[0x5]; 1665 1666 u8 reserved_at_a0[0x3]; 1667 u8 ece_support[0x1]; 1668 u8 reserved_at_a4[0x5]; 1669 u8 reg_c_preserve[0x1]; 1670 u8 reserved_at_aa[0x1]; 1671 u8 log_max_srq[0x5]; 1672 u8 reserved_at_b0[0x1]; 1673 u8 uplink_follow[0x1]; 1674 u8 ts_cqe_to_dest_cqn[0x1]; 1675 u8 reserved_at_b3[0x6]; 1676 u8 go_back_n[0x1]; 1677 u8 reserved_at_ba[0x6]; 1678 1679 u8 max_sgl_for_optimized_performance[0x8]; 1680 u8 log_max_cq_sz[0x8]; 1681 u8 relaxed_ordering_write_umr[0x1]; 1682 u8 relaxed_ordering_read_umr[0x1]; 1683 u8 reserved_at_d2[0x7]; 1684 u8 virtio_net_device_emualtion_manager[0x1]; 1685 u8 virtio_blk_device_emualtion_manager[0x1]; 1686 u8 log_max_cq[0x5]; 1687 1688 u8 log_max_eq_sz[0x8]; 1689 u8 relaxed_ordering_write[0x1]; 1690 u8 relaxed_ordering_read_pci_enabled[0x1]; 1691 u8 log_max_mkey[0x6]; 1692 u8 reserved_at_f0[0x6]; 1693 u8 terminate_scatter_list_mkey[0x1]; 1694 u8 repeated_mkey[0x1]; 1695 u8 dump_fill_mkey[0x1]; 1696 u8 reserved_at_f9[0x2]; 1697 u8 fast_teardown[0x1]; 1698 u8 log_max_eq[0x4]; 1699 1700 u8 max_indirection[0x8]; 1701 u8 fixed_buffer_size[0x1]; 1702 u8 log_max_mrw_sz[0x7]; 1703 u8 force_teardown[0x1]; 1704 u8 reserved_at_111[0x1]; 1705 u8 log_max_bsf_list_size[0x6]; 1706 u8 umr_extended_translation_offset[0x1]; 1707 u8 null_mkey[0x1]; 1708 u8 log_max_klm_list_size[0x6]; 1709 1710 u8 reserved_at_120[0x2]; 1711 u8 qpc_extension[0x1]; 1712 u8 reserved_at_123[0x7]; 1713 u8 log_max_ra_req_dc[0x6]; 1714 u8 reserved_at_130[0x2]; 1715 u8 eth_wqe_too_small[0x1]; 1716 u8 reserved_at_133[0x6]; 1717 u8 vnic_env_cq_overrun[0x1]; 1718 u8 log_max_ra_res_dc[0x6]; 1719 1720 u8 reserved_at_140[0x5]; 1721 u8 release_all_pages[0x1]; 1722 u8 must_not_use[0x1]; 1723 u8 reserved_at_147[0x2]; 1724 u8 roce_accl[0x1]; 1725 u8 log_max_ra_req_qp[0x6]; 1726 u8 reserved_at_150[0xa]; 1727 u8 log_max_ra_res_qp[0x6]; 1728 1729 u8 end_pad[0x1]; 1730 u8 cc_query_allowed[0x1]; 1731 u8 cc_modify_allowed[0x1]; 1732 u8 start_pad[0x1]; 1733 u8 cache_line_128byte[0x1]; 1734 u8 reserved_at_165[0x4]; 1735 u8 rts2rts_qp_counters_set_id[0x1]; 1736 u8 reserved_at_16a[0x2]; 1737 u8 vnic_env_int_rq_oob[0x1]; 1738 u8 sbcam_reg[0x1]; 1739 u8 reserved_at_16e[0x1]; 1740 u8 qcam_reg[0x1]; 1741 u8 gid_table_size[0x10]; 1742 1743 u8 out_of_seq_cnt[0x1]; 1744 u8 vport_counters[0x1]; 1745 u8 retransmission_q_counters[0x1]; 1746 u8 debug[0x1]; 1747 u8 modify_rq_counter_set_id[0x1]; 1748 u8 rq_delay_drop[0x1]; 1749 u8 max_qp_cnt[0xa]; 1750 u8 pkey_table_size[0x10]; 1751 1752 u8 vport_group_manager[0x1]; 1753 u8 vhca_group_manager[0x1]; 1754 u8 ib_virt[0x1]; 1755 u8 eth_virt[0x1]; 1756 u8 vnic_env_queue_counters[0x1]; 1757 u8 ets[0x1]; 1758 u8 nic_flow_table[0x1]; 1759 u8 eswitch_manager[0x1]; 1760 u8 device_memory[0x1]; 1761 u8 mcam_reg[0x1]; 1762 u8 pcam_reg[0x1]; 1763 u8 local_ca_ack_delay[0x5]; 1764 u8 port_module_event[0x1]; 1765 u8 enhanced_error_q_counters[0x1]; 1766 u8 ports_check[0x1]; 1767 u8 reserved_at_1b3[0x1]; 1768 u8 disable_link_up[0x1]; 1769 u8 beacon_led[0x1]; 1770 u8 port_type[0x2]; 1771 u8 num_ports[0x8]; 1772 1773 u8 reserved_at_1c0[0x1]; 1774 u8 pps[0x1]; 1775 u8 pps_modify[0x1]; 1776 u8 log_max_msg[0x5]; 1777 u8 reserved_at_1c8[0x4]; 1778 u8 max_tc[0x4]; 1779 u8 temp_warn_event[0x1]; 1780 u8 dcbx[0x1]; 1781 u8 general_notification_event[0x1]; 1782 u8 reserved_at_1d3[0x2]; 1783 u8 fpga[0x1]; 1784 u8 rol_s[0x1]; 1785 u8 rol_g[0x1]; 1786 u8 reserved_at_1d8[0x1]; 1787 u8 wol_s[0x1]; 1788 u8 wol_g[0x1]; 1789 u8 wol_a[0x1]; 1790 u8 wol_b[0x1]; 1791 u8 wol_m[0x1]; 1792 u8 wol_u[0x1]; 1793 u8 wol_p[0x1]; 1794 1795 u8 stat_rate_support[0x10]; 1796 u8 reserved_at_1f0[0x1]; 1797 u8 pci_sync_for_fw_update_event[0x1]; 1798 u8 reserved_at_1f2[0x6]; 1799 u8 init2_lag_tx_port_affinity[0x1]; 1800 u8 reserved_at_1fa[0x2]; 1801 u8 wqe_based_flow_table_update_cap[0x1]; 1802 u8 cqe_version[0x4]; 1803 1804 u8 compact_address_vector[0x1]; 1805 u8 striding_rq[0x1]; 1806 u8 reserved_at_202[0x1]; 1807 u8 ipoib_enhanced_offloads[0x1]; 1808 u8 ipoib_basic_offloads[0x1]; 1809 u8 reserved_at_205[0x1]; 1810 u8 repeated_block_disabled[0x1]; 1811 u8 umr_modify_entity_size_disabled[0x1]; 1812 u8 umr_modify_atomic_disabled[0x1]; 1813 u8 umr_indirect_mkey_disabled[0x1]; 1814 u8 umr_fence[0x2]; 1815 u8 dc_req_scat_data_cqe[0x1]; 1816 u8 reserved_at_20d[0x2]; 1817 u8 drain_sigerr[0x1]; 1818 u8 cmdif_checksum[0x2]; 1819 u8 sigerr_cqe[0x1]; 1820 u8 reserved_at_213[0x1]; 1821 u8 wq_signature[0x1]; 1822 u8 sctr_data_cqe[0x1]; 1823 u8 reserved_at_216[0x1]; 1824 u8 sho[0x1]; 1825 u8 tph[0x1]; 1826 u8 rf[0x1]; 1827 u8 dct[0x1]; 1828 u8 qos[0x1]; 1829 u8 eth_net_offloads[0x1]; 1830 u8 roce[0x1]; 1831 u8 atomic[0x1]; 1832 u8 reserved_at_21f[0x1]; 1833 1834 u8 cq_oi[0x1]; 1835 u8 cq_resize[0x1]; 1836 u8 cq_moderation[0x1]; 1837 u8 cq_period_mode_modify[0x1]; 1838 u8 reserved_at_224[0x2]; 1839 u8 cq_eq_remap[0x1]; 1840 u8 pg[0x1]; 1841 u8 block_lb_mc[0x1]; 1842 u8 reserved_at_229[0x1]; 1843 u8 scqe_break_moderation[0x1]; 1844 u8 cq_period_start_from_cqe[0x1]; 1845 u8 cd[0x1]; 1846 u8 reserved_at_22d[0x1]; 1847 u8 apm[0x1]; 1848 u8 vector_calc[0x1]; 1849 u8 umr_ptr_rlky[0x1]; 1850 u8 imaicl[0x1]; 1851 u8 qp_packet_based[0x1]; 1852 u8 reserved_at_233[0x3]; 1853 u8 qkv[0x1]; 1854 u8 pkv[0x1]; 1855 u8 set_deth_sqpn[0x1]; 1856 u8 reserved_at_239[0x3]; 1857 u8 xrc[0x1]; 1858 u8 ud[0x1]; 1859 u8 uc[0x1]; 1860 u8 rc[0x1]; 1861 1862 u8 uar_4k[0x1]; 1863 u8 reserved_at_241[0x7]; 1864 u8 fl_rc_qp_when_roce_disabled[0x1]; 1865 u8 regexp_params[0x1]; 1866 u8 uar_sz[0x6]; 1867 u8 port_selection_cap[0x1]; 1868 u8 nic_cap_reg[0x1]; 1869 u8 umem_uid_0[0x1]; 1870 u8 reserved_at_253[0x5]; 1871 u8 log_pg_sz[0x8]; 1872 1873 u8 bf[0x1]; 1874 u8 driver_version[0x1]; 1875 u8 pad_tx_eth_packet[0x1]; 1876 u8 reserved_at_263[0x3]; 1877 u8 mkey_by_name[0x1]; 1878 u8 reserved_at_267[0x4]; 1879 1880 u8 log_bf_reg_size[0x5]; 1881 1882 u8 disciplined_fr_counter[0x1]; 1883 u8 reserved_at_271[0x2]; 1884 u8 qp_error_syndrome[0x1]; 1885 u8 reserved_at_274[0x2]; 1886 u8 lag_dct[0x2]; 1887 u8 lag_tx_port_affinity[0x1]; 1888 u8 lag_native_fdb_selection[0x1]; 1889 u8 reserved_at_27a[0x1]; 1890 u8 lag_master[0x1]; 1891 u8 num_lag_ports[0x4]; 1892 1893 u8 reserved_at_280[0x10]; 1894 u8 max_wqe_sz_sq[0x10]; 1895 1896 u8 reserved_at_2a0[0x7]; 1897 u8 mkey_pcie_tph[0x1]; 1898 u8 reserved_at_2a8[0x2]; 1899 1900 u8 psp[0x1]; 1901 u8 shampo[0x1]; 1902 u8 reserved_at_2ac[0x4]; 1903 u8 max_wqe_sz_rq[0x10]; 1904 1905 u8 max_flow_counter_31_16[0x10]; 1906 u8 max_wqe_sz_sq_dc[0x10]; 1907 1908 u8 reserved_at_2e0[0x7]; 1909 u8 max_qp_mcg[0x19]; 1910 1911 u8 reserved_at_300[0x10]; 1912 u8 flow_counter_bulk_alloc[0x8]; 1913 u8 log_max_mcg[0x8]; 1914 1915 u8 reserved_at_320[0x3]; 1916 u8 log_max_transport_domain[0x5]; 1917 u8 reserved_at_328[0x2]; 1918 u8 relaxed_ordering_read[0x1]; 1919 u8 log_max_pd[0x5]; 1920 u8 dp_ordering_ooo_all_ud[0x1]; 1921 u8 dp_ordering_ooo_all_uc[0x1]; 1922 u8 dp_ordering_ooo_all_xrc[0x1]; 1923 u8 dp_ordering_ooo_all_dc[0x1]; 1924 u8 dp_ordering_ooo_all_rc[0x1]; 1925 u8 pcie_reset_using_hotreset_method[0x1]; 1926 u8 pci_sync_for_fw_update_with_driver_unload[0x1]; 1927 u8 vnic_env_cnt_steering_fail[0x1]; 1928 u8 vport_counter_local_loopback[0x1]; 1929 u8 q_counter_aggregation[0x1]; 1930 u8 q_counter_other_vport[0x1]; 1931 u8 log_max_xrcd[0x5]; 1932 1933 u8 nic_receive_steering_discard[0x1]; 1934 u8 receive_discard_vport_down[0x1]; 1935 u8 transmit_discard_vport_down[0x1]; 1936 u8 eq_overrun_count[0x1]; 1937 u8 reserved_at_344[0x1]; 1938 u8 invalid_command_count[0x1]; 1939 u8 quota_exceeded_count[0x1]; 1940 u8 reserved_at_347[0x1]; 1941 u8 log_max_flow_counter_bulk[0x8]; 1942 u8 max_flow_counter_15_0[0x10]; 1943 1944 1945 u8 reserved_at_360[0x3]; 1946 u8 log_max_rq[0x5]; 1947 u8 reserved_at_368[0x3]; 1948 u8 log_max_sq[0x5]; 1949 u8 reserved_at_370[0x3]; 1950 u8 log_max_tir[0x5]; 1951 u8 reserved_at_378[0x3]; 1952 u8 log_max_tis[0x5]; 1953 1954 u8 basic_cyclic_rcv_wqe[0x1]; 1955 u8 reserved_at_381[0x2]; 1956 u8 log_max_rmp[0x5]; 1957 u8 reserved_at_388[0x3]; 1958 u8 log_max_rqt[0x5]; 1959 u8 reserved_at_390[0x3]; 1960 u8 log_max_rqt_size[0x5]; 1961 u8 reserved_at_398[0x3]; 1962 u8 log_max_tis_per_sq[0x5]; 1963 1964 u8 ext_stride_num_range[0x1]; 1965 u8 roce_rw_supported[0x1]; 1966 u8 log_max_current_uc_list_wr_supported[0x1]; 1967 u8 log_max_stride_sz_rq[0x5]; 1968 u8 reserved_at_3a8[0x3]; 1969 u8 log_min_stride_sz_rq[0x5]; 1970 u8 reserved_at_3b0[0x3]; 1971 u8 log_max_stride_sz_sq[0x5]; 1972 u8 reserved_at_3b8[0x3]; 1973 u8 log_min_stride_sz_sq[0x5]; 1974 1975 u8 hairpin[0x1]; 1976 u8 reserved_at_3c1[0x2]; 1977 u8 log_max_hairpin_queues[0x5]; 1978 u8 reserved_at_3c8[0x3]; 1979 u8 log_max_hairpin_wq_data_sz[0x5]; 1980 u8 reserved_at_3d0[0x3]; 1981 u8 log_max_hairpin_num_packets[0x5]; 1982 u8 reserved_at_3d8[0x3]; 1983 u8 log_max_wq_sz[0x5]; 1984 1985 u8 nic_vport_change_event[0x1]; 1986 u8 disable_local_lb_uc[0x1]; 1987 u8 disable_local_lb_mc[0x1]; 1988 u8 log_min_hairpin_wq_data_sz[0x5]; 1989 u8 reserved_at_3e8[0x1]; 1990 u8 silent_mode[0x1]; 1991 u8 vhca_state[0x1]; 1992 u8 log_max_vlan_list[0x5]; 1993 u8 reserved_at_3f0[0x3]; 1994 u8 log_max_current_mc_list[0x5]; 1995 u8 reserved_at_3f8[0x3]; 1996 u8 log_max_current_uc_list[0x5]; 1997 1998 u8 general_obj_types[0x40]; 1999 2000 u8 sq_ts_format[0x2]; 2001 u8 rq_ts_format[0x2]; 2002 u8 steering_format_version[0x4]; 2003 u8 create_qp_start_hint[0x18]; 2004 2005 u8 reserved_at_460[0x1]; 2006 u8 ats[0x1]; 2007 u8 cross_vhca_rqt[0x1]; 2008 u8 log_max_uctx[0x5]; 2009 u8 reserved_at_468[0x1]; 2010 u8 crypto[0x1]; 2011 u8 ipsec_offload[0x1]; 2012 u8 log_max_umem[0x5]; 2013 u8 max_num_eqs[0x10]; 2014 2015 u8 reserved_at_480[0x1]; 2016 u8 tls_tx[0x1]; 2017 u8 tls_rx[0x1]; 2018 u8 log_max_l2_table[0x5]; 2019 u8 reserved_at_488[0x8]; 2020 u8 log_uar_page_sz[0x10]; 2021 2022 u8 reserved_at_4a0[0x20]; 2023 u8 device_frequency_mhz[0x20]; 2024 u8 device_frequency_khz[0x20]; 2025 2026 u8 reserved_at_500[0x20]; 2027 u8 num_of_uars_per_page[0x20]; 2028 2029 u8 flex_parser_protocols[0x20]; 2030 2031 u8 max_geneve_tlv_options[0x8]; 2032 u8 reserved_at_568[0x3]; 2033 u8 max_geneve_tlv_option_data_len[0x5]; 2034 u8 reserved_at_570[0x1]; 2035 u8 adv_rdma[0x1]; 2036 u8 reserved_at_572[0x7]; 2037 u8 adv_virtualization[0x1]; 2038 u8 reserved_at_57a[0x6]; 2039 2040 u8 reserved_at_580[0xb]; 2041 u8 log_max_dci_stream_channels[0x5]; 2042 u8 reserved_at_590[0x3]; 2043 u8 log_max_dci_errored_streams[0x5]; 2044 u8 reserved_at_598[0x8]; 2045 2046 u8 reserved_at_5a0[0x10]; 2047 u8 enhanced_cqe_compression[0x1]; 2048 u8 reserved_at_5b1[0x1]; 2049 u8 crossing_vhca_mkey[0x1]; 2050 u8 log_max_dek[0x5]; 2051 u8 reserved_at_5b8[0x4]; 2052 u8 mini_cqe_resp_stride_index[0x1]; 2053 u8 cqe_128_always[0x1]; 2054 u8 cqe_compression_128[0x1]; 2055 u8 cqe_compression[0x1]; 2056 2057 u8 cqe_compression_timeout[0x10]; 2058 u8 cqe_compression_max_num[0x10]; 2059 2060 u8 reserved_at_5e0[0x8]; 2061 u8 flex_parser_id_gtpu_dw_0[0x4]; 2062 u8 reserved_at_5ec[0x4]; 2063 u8 tag_matching[0x1]; 2064 u8 rndv_offload_rc[0x1]; 2065 u8 rndv_offload_dc[0x1]; 2066 u8 log_tag_matching_list_sz[0x5]; 2067 u8 reserved_at_5f8[0x3]; 2068 u8 log_max_xrq[0x5]; 2069 2070 u8 affiliate_nic_vport_criteria[0x8]; 2071 u8 native_port_num[0x8]; 2072 u8 num_vhca_ports[0x8]; 2073 u8 flex_parser_id_gtpu_teid[0x4]; 2074 u8 reserved_at_61c[0x2]; 2075 u8 sw_owner_id[0x1]; 2076 u8 reserved_at_61f[0x1]; 2077 2078 u8 max_num_of_monitor_counters[0x10]; 2079 u8 num_ppcnt_monitor_counters[0x10]; 2080 2081 u8 max_num_sf[0x10]; 2082 u8 num_q_monitor_counters[0x10]; 2083 2084 u8 reserved_at_660[0x20]; 2085 2086 u8 sf[0x1]; 2087 u8 sf_set_partition[0x1]; 2088 u8 reserved_at_682[0x1]; 2089 u8 log_max_sf[0x5]; 2090 u8 apu[0x1]; 2091 u8 reserved_at_689[0x4]; 2092 u8 migration[0x1]; 2093 u8 reserved_at_68e[0x2]; 2094 u8 log_min_sf_size[0x8]; 2095 u8 max_num_sf_partitions[0x8]; 2096 2097 u8 uctx_cap[0x20]; 2098 2099 u8 reserved_at_6c0[0x4]; 2100 u8 flex_parser_id_geneve_tlv_option_0[0x4]; 2101 u8 flex_parser_id_icmp_dw1[0x4]; 2102 u8 flex_parser_id_icmp_dw0[0x4]; 2103 u8 flex_parser_id_icmpv6_dw1[0x4]; 2104 u8 flex_parser_id_icmpv6_dw0[0x4]; 2105 u8 flex_parser_id_outer_first_mpls_over_gre[0x4]; 2106 u8 flex_parser_id_outer_first_mpls_over_udp_label[0x4]; 2107 2108 u8 max_num_match_definer[0x10]; 2109 u8 sf_base_id[0x10]; 2110 2111 u8 flex_parser_id_gtpu_dw_2[0x4]; 2112 u8 flex_parser_id_gtpu_first_ext_dw_0[0x4]; 2113 u8 num_total_dynamic_vf_msix[0x18]; 2114 u8 reserved_at_720[0x14]; 2115 u8 dynamic_msix_table_size[0xc]; 2116 u8 reserved_at_740[0xc]; 2117 u8 min_dynamic_vf_msix_table_size[0x4]; 2118 u8 reserved_at_750[0x2]; 2119 u8 data_direct[0x1]; 2120 u8 reserved_at_753[0x1]; 2121 u8 max_dynamic_vf_msix_table_size[0xc]; 2122 2123 u8 reserved_at_760[0x3]; 2124 u8 log_max_num_header_modify_argument[0x5]; 2125 u8 log_header_modify_argument_granularity_offset[0x4]; 2126 u8 log_header_modify_argument_granularity[0x4]; 2127 u8 reserved_at_770[0x3]; 2128 u8 log_header_modify_argument_max_alloc[0x5]; 2129 u8 reserved_at_778[0x8]; 2130 2131 u8 vhca_tunnel_commands[0x40]; 2132 u8 match_definer_format_supported[0x40]; 2133 }; 2134 2135 enum { 2136 MLX5_CROSS_VHCA_OBJ_TO_OBJ_SUPPORTED_LOCAL_FLOW_TABLE_TO_REMOTE_FLOW_TABLE_MISS = 0x80000, 2137 MLX5_CROSS_VHCA_OBJ_TO_OBJ_SUPPORTED_LOCAL_FLOW_TABLE_ROOT_TO_REMOTE_FLOW_TABLE = (1ULL << 20), 2138 }; 2139 2140 enum { 2141 MLX5_ALLOWED_OBJ_FOR_OTHER_VHCA_ACCESS_FLOW_TABLE = 0x200, 2142 }; 2143 2144 struct mlx5_ifc_cmd_hca_cap_2_bits { 2145 u8 reserved_at_0[0x80]; 2146 2147 u8 migratable[0x1]; 2148 u8 reserved_at_81[0x7]; 2149 u8 dp_ordering_force[0x1]; 2150 u8 reserved_at_89[0x9]; 2151 u8 query_vuid[0x1]; 2152 u8 reserved_at_93[0x5]; 2153 u8 umr_log_entity_size_5[0x1]; 2154 u8 reserved_at_99[0x7]; 2155 2156 u8 max_reformat_insert_size[0x8]; 2157 u8 max_reformat_insert_offset[0x8]; 2158 u8 max_reformat_remove_size[0x8]; 2159 u8 max_reformat_remove_offset[0x8]; 2160 2161 u8 reserved_at_c0[0x8]; 2162 u8 migration_multi_load[0x1]; 2163 u8 migration_tracking_state[0x1]; 2164 u8 multiplane_qp_ud[0x1]; 2165 u8 reserved_at_cb[0x5]; 2166 u8 migration_in_chunks[0x1]; 2167 u8 reserved_at_d1[0x1]; 2168 u8 sf_eq_usage[0x1]; 2169 u8 reserved_at_d3[0x5]; 2170 u8 multiplane[0x1]; 2171 u8 reserved_at_d9[0x7]; 2172 2173 u8 cross_vhca_object_to_object_supported[0x20]; 2174 2175 u8 allowed_object_for_other_vhca_access[0x40]; 2176 2177 u8 reserved_at_140[0x60]; 2178 2179 u8 flow_table_type_2_type[0x8]; 2180 u8 reserved_at_1a8[0x2]; 2181 u8 format_select_dw_8_6_ext[0x1]; 2182 u8 log_min_mkey_entity_size[0x5]; 2183 u8 reserved_at_1b0[0x10]; 2184 2185 u8 general_obj_types_127_64[0x40]; 2186 u8 reserved_at_200[0x20]; 2187 2188 u8 reserved_at_220[0x1]; 2189 u8 sw_vhca_id_valid[0x1]; 2190 u8 sw_vhca_id[0xe]; 2191 u8 reserved_at_230[0x10]; 2192 2193 u8 reserved_at_240[0xb]; 2194 u8 ts_cqe_metadata_size2wqe_counter[0x5]; 2195 u8 reserved_at_250[0x10]; 2196 2197 u8 reserved_at_260[0x20]; 2198 2199 u8 format_select_dw_gtpu_dw_0[0x8]; 2200 u8 format_select_dw_gtpu_dw_1[0x8]; 2201 u8 format_select_dw_gtpu_dw_2[0x8]; 2202 u8 format_select_dw_gtpu_first_ext_dw_0[0x8]; 2203 2204 u8 generate_wqe_type[0x20]; 2205 2206 u8 reserved_at_2c0[0xc0]; 2207 2208 u8 reserved_at_380[0xb]; 2209 u8 min_mkey_log_entity_size_fixed_buffer[0x5]; 2210 u8 ec_vf_vport_base[0x10]; 2211 2212 u8 reserved_at_3a0[0x2]; 2213 u8 max_mkey_log_entity_size_fixed_buffer[0x6]; 2214 u8 reserved_at_3a8[0x2]; 2215 u8 max_mkey_log_entity_size_mtt[0x6]; 2216 u8 max_rqt_vhca_id[0x10]; 2217 2218 u8 reserved_at_3c0[0x20]; 2219 2220 u8 reserved_at_3e0[0x10]; 2221 u8 pcc_ifa2[0x1]; 2222 u8 reserved_at_3f1[0xf]; 2223 2224 u8 reserved_at_400[0x1]; 2225 u8 min_mkey_log_entity_size_fixed_buffer_valid[0x1]; 2226 u8 reserved_at_402[0xe]; 2227 u8 return_reg_id[0x10]; 2228 2229 u8 reserved_at_420[0x1c]; 2230 u8 flow_table_hash_type[0x4]; 2231 2232 u8 reserved_at_440[0x8]; 2233 u8 max_num_eqs_24b[0x18]; 2234 2235 u8 reserved_at_460[0x160]; 2236 2237 u8 query_adjacent_functions_id[0x1]; 2238 u8 ingress_egress_esw_vport_connect[0x1]; 2239 u8 function_id_type_vhca_id[0x1]; 2240 u8 reserved_at_5c3[0xd]; 2241 u8 delegate_vhca_management_profiles[0x10]; 2242 2243 u8 delegated_vhca_max[0x10]; 2244 u8 delegate_vhca_max[0x10]; 2245 2246 u8 reserved_at_600[0x200]; 2247 }; 2248 2249 enum mlx5_ifc_flow_destination_type { 2250 MLX5_IFC_FLOW_DESTINATION_TYPE_VPORT = 0x0, 2251 MLX5_IFC_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1, 2252 MLX5_IFC_FLOW_DESTINATION_TYPE_TIR = 0x2, 2253 MLX5_IFC_FLOW_DESTINATION_TYPE_FLOW_SAMPLER = 0x6, 2254 MLX5_IFC_FLOW_DESTINATION_TYPE_UPLINK = 0x8, 2255 MLX5_IFC_FLOW_DESTINATION_TYPE_TABLE_TYPE = 0xA, 2256 }; 2257 2258 enum mlx5_flow_table_miss_action { 2259 MLX5_FLOW_TABLE_MISS_ACTION_DEF, 2260 MLX5_FLOW_TABLE_MISS_ACTION_FWD, 2261 MLX5_FLOW_TABLE_MISS_ACTION_SWITCH_DOMAIN, 2262 }; 2263 2264 struct mlx5_ifc_dest_format_struct_bits { 2265 u8 destination_type[0x8]; 2266 u8 destination_id[0x18]; 2267 2268 u8 destination_eswitch_owner_vhca_id_valid[0x1]; 2269 u8 packet_reformat[0x1]; 2270 u8 reserved_at_22[0x6]; 2271 u8 destination_table_type[0x8]; 2272 u8 destination_eswitch_owner_vhca_id[0x10]; 2273 }; 2274 2275 struct mlx5_ifc_flow_counter_list_bits { 2276 u8 flow_counter_id[0x20]; 2277 2278 u8 reserved_at_20[0x20]; 2279 }; 2280 2281 struct mlx5_ifc_extended_dest_format_bits { 2282 struct mlx5_ifc_dest_format_struct_bits destination_entry; 2283 2284 u8 packet_reformat_id[0x20]; 2285 2286 u8 reserved_at_60[0x20]; 2287 }; 2288 2289 union mlx5_ifc_dest_format_flow_counter_list_auto_bits { 2290 struct mlx5_ifc_extended_dest_format_bits extended_dest_format; 2291 struct mlx5_ifc_flow_counter_list_bits flow_counter_list; 2292 }; 2293 2294 struct mlx5_ifc_fte_match_param_bits { 2295 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers; 2296 2297 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters; 2298 2299 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers; 2300 2301 struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2; 2302 2303 struct mlx5_ifc_fte_match_set_misc3_bits misc_parameters_3; 2304 2305 struct mlx5_ifc_fte_match_set_misc4_bits misc_parameters_4; 2306 2307 struct mlx5_ifc_fte_match_set_misc5_bits misc_parameters_5; 2308 2309 u8 reserved_at_e00[0x200]; 2310 }; 2311 2312 enum { 2313 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0, 2314 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1, 2315 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2, 2316 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3, 2317 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4, 2318 }; 2319 2320 struct mlx5_ifc_rx_hash_field_select_bits { 2321 u8 l3_prot_type[0x1]; 2322 u8 l4_prot_type[0x1]; 2323 u8 selected_fields[0x1e]; 2324 }; 2325 2326 enum { 2327 MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0, 2328 MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1, 2329 }; 2330 2331 enum { 2332 MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0, 2333 MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1, 2334 }; 2335 2336 struct mlx5_ifc_wq_bits { 2337 u8 wq_type[0x4]; 2338 u8 wq_signature[0x1]; 2339 u8 end_padding_mode[0x2]; 2340 u8 cd_slave[0x1]; 2341 u8 reserved_at_8[0x18]; 2342 2343 u8 hds_skip_first_sge[0x1]; 2344 u8 log2_hds_buf_size[0x3]; 2345 u8 reserved_at_24[0x7]; 2346 u8 page_offset[0x5]; 2347 u8 lwm[0x10]; 2348 2349 u8 reserved_at_40[0x8]; 2350 u8 pd[0x18]; 2351 2352 u8 reserved_at_60[0x8]; 2353 u8 uar_page[0x18]; 2354 2355 u8 dbr_addr[0x40]; 2356 2357 u8 hw_counter[0x20]; 2358 2359 u8 sw_counter[0x20]; 2360 2361 u8 reserved_at_100[0xc]; 2362 u8 log_wq_stride[0x4]; 2363 u8 reserved_at_110[0x3]; 2364 u8 log_wq_pg_sz[0x5]; 2365 u8 reserved_at_118[0x3]; 2366 u8 log_wq_sz[0x5]; 2367 2368 u8 dbr_umem_valid[0x1]; 2369 u8 wq_umem_valid[0x1]; 2370 u8 reserved_at_122[0x1]; 2371 u8 log_hairpin_num_packets[0x5]; 2372 u8 reserved_at_128[0x3]; 2373 u8 log_hairpin_data_sz[0x5]; 2374 2375 u8 reserved_at_130[0x4]; 2376 u8 log_wqe_num_of_strides[0x4]; 2377 u8 two_byte_shift_en[0x1]; 2378 u8 reserved_at_139[0x4]; 2379 u8 log_wqe_stride_size[0x3]; 2380 2381 u8 dbr_umem_id[0x20]; 2382 u8 wq_umem_id[0x20]; 2383 2384 u8 wq_umem_offset[0x40]; 2385 2386 u8 headers_mkey[0x20]; 2387 2388 u8 shampo_enable[0x1]; 2389 u8 reserved_at_1e1[0x1]; 2390 u8 shampo_mode[0x2]; 2391 u8 reserved_at_1e4[0x1]; 2392 u8 log_reservation_size[0x3]; 2393 u8 reserved_at_1e8[0x5]; 2394 u8 log_max_num_of_packets_per_reservation[0x3]; 2395 u8 reserved_at_1f0[0x6]; 2396 u8 log_headers_entry_size[0x2]; 2397 u8 reserved_at_1f8[0x4]; 2398 u8 log_headers_buffer_entry_num[0x4]; 2399 2400 u8 reserved_at_200[0x400]; 2401 2402 struct mlx5_ifc_cmd_pas_bits pas[]; 2403 }; 2404 2405 struct mlx5_ifc_rq_num_bits { 2406 u8 reserved_at_0[0x8]; 2407 u8 rq_num[0x18]; 2408 }; 2409 2410 struct mlx5_ifc_rq_vhca_bits { 2411 u8 reserved_at_0[0x8]; 2412 u8 rq_num[0x18]; 2413 u8 reserved_at_20[0x10]; 2414 u8 rq_vhca_id[0x10]; 2415 }; 2416 2417 struct mlx5_ifc_mac_address_layout_bits { 2418 u8 reserved_at_0[0x10]; 2419 u8 mac_addr_47_32[0x10]; 2420 2421 u8 mac_addr_31_0[0x20]; 2422 }; 2423 2424 struct mlx5_ifc_vlan_layout_bits { 2425 u8 reserved_at_0[0x14]; 2426 u8 vlan[0x0c]; 2427 2428 u8 reserved_at_20[0x20]; 2429 }; 2430 2431 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits { 2432 u8 reserved_at_0[0xa0]; 2433 2434 u8 min_time_between_cnps[0x20]; 2435 2436 u8 reserved_at_c0[0x12]; 2437 u8 cnp_dscp[0x6]; 2438 u8 reserved_at_d8[0x4]; 2439 u8 cnp_prio_mode[0x1]; 2440 u8 cnp_802p_prio[0x3]; 2441 2442 u8 reserved_at_e0[0x720]; 2443 }; 2444 2445 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits { 2446 u8 reserved_at_0[0x60]; 2447 2448 u8 reserved_at_60[0x4]; 2449 u8 clamp_tgt_rate[0x1]; 2450 u8 reserved_at_65[0x3]; 2451 u8 clamp_tgt_rate_after_time_inc[0x1]; 2452 u8 reserved_at_69[0x17]; 2453 2454 u8 reserved_at_80[0x20]; 2455 2456 u8 rpg_time_reset[0x20]; 2457 2458 u8 rpg_byte_reset[0x20]; 2459 2460 u8 rpg_threshold[0x20]; 2461 2462 u8 rpg_max_rate[0x20]; 2463 2464 u8 rpg_ai_rate[0x20]; 2465 2466 u8 rpg_hai_rate[0x20]; 2467 2468 u8 rpg_gd[0x20]; 2469 2470 u8 rpg_min_dec_fac[0x20]; 2471 2472 u8 rpg_min_rate[0x20]; 2473 2474 u8 reserved_at_1c0[0xe0]; 2475 2476 u8 rate_to_set_on_first_cnp[0x20]; 2477 2478 u8 dce_tcp_g[0x20]; 2479 2480 u8 dce_tcp_rtt[0x20]; 2481 2482 u8 rate_reduce_monitor_period[0x20]; 2483 2484 u8 reserved_at_320[0x20]; 2485 2486 u8 initial_alpha_value[0x20]; 2487 2488 u8 reserved_at_360[0x4a0]; 2489 }; 2490 2491 struct mlx5_ifc_cong_control_r_roce_general_bits { 2492 u8 reserved_at_0[0x80]; 2493 2494 u8 reserved_at_80[0x10]; 2495 u8 rtt_resp_dscp_valid[0x1]; 2496 u8 reserved_at_91[0x9]; 2497 u8 rtt_resp_dscp[0x6]; 2498 2499 u8 reserved_at_a0[0x760]; 2500 }; 2501 2502 struct mlx5_ifc_cong_control_802_1qau_rp_bits { 2503 u8 reserved_at_0[0x80]; 2504 2505 u8 rppp_max_rps[0x20]; 2506 2507 u8 rpg_time_reset[0x20]; 2508 2509 u8 rpg_byte_reset[0x20]; 2510 2511 u8 rpg_threshold[0x20]; 2512 2513 u8 rpg_max_rate[0x20]; 2514 2515 u8 rpg_ai_rate[0x20]; 2516 2517 u8 rpg_hai_rate[0x20]; 2518 2519 u8 rpg_gd[0x20]; 2520 2521 u8 rpg_min_dec_fac[0x20]; 2522 2523 u8 rpg_min_rate[0x20]; 2524 2525 u8 reserved_at_1c0[0x640]; 2526 }; 2527 2528 enum { 2529 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1, 2530 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2, 2531 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4, 2532 }; 2533 2534 struct mlx5_ifc_resize_field_select_bits { 2535 u8 resize_field_select[0x20]; 2536 }; 2537 2538 struct mlx5_ifc_resource_dump_bits { 2539 u8 more_dump[0x1]; 2540 u8 inline_dump[0x1]; 2541 u8 reserved_at_2[0xa]; 2542 u8 seq_num[0x4]; 2543 u8 segment_type[0x10]; 2544 2545 u8 reserved_at_20[0x10]; 2546 u8 vhca_id[0x10]; 2547 2548 u8 index1[0x20]; 2549 2550 u8 index2[0x20]; 2551 2552 u8 num_of_obj1[0x10]; 2553 u8 num_of_obj2[0x10]; 2554 2555 u8 reserved_at_a0[0x20]; 2556 2557 u8 device_opaque[0x40]; 2558 2559 u8 mkey[0x20]; 2560 2561 u8 size[0x20]; 2562 2563 u8 address[0x40]; 2564 2565 u8 inline_data[52][0x20]; 2566 }; 2567 2568 struct mlx5_ifc_resource_dump_menu_record_bits { 2569 u8 reserved_at_0[0x4]; 2570 u8 num_of_obj2_supports_active[0x1]; 2571 u8 num_of_obj2_supports_all[0x1]; 2572 u8 must_have_num_of_obj2[0x1]; 2573 u8 support_num_of_obj2[0x1]; 2574 u8 num_of_obj1_supports_active[0x1]; 2575 u8 num_of_obj1_supports_all[0x1]; 2576 u8 must_have_num_of_obj1[0x1]; 2577 u8 support_num_of_obj1[0x1]; 2578 u8 must_have_index2[0x1]; 2579 u8 support_index2[0x1]; 2580 u8 must_have_index1[0x1]; 2581 u8 support_index1[0x1]; 2582 u8 segment_type[0x10]; 2583 2584 u8 segment_name[4][0x20]; 2585 2586 u8 index1_name[4][0x20]; 2587 2588 u8 index2_name[4][0x20]; 2589 }; 2590 2591 struct mlx5_ifc_resource_dump_segment_header_bits { 2592 u8 length_dw[0x10]; 2593 u8 segment_type[0x10]; 2594 }; 2595 2596 struct mlx5_ifc_resource_dump_command_segment_bits { 2597 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2598 2599 u8 segment_called[0x10]; 2600 u8 vhca_id[0x10]; 2601 2602 u8 index1[0x20]; 2603 2604 u8 index2[0x20]; 2605 2606 u8 num_of_obj1[0x10]; 2607 u8 num_of_obj2[0x10]; 2608 }; 2609 2610 struct mlx5_ifc_resource_dump_error_segment_bits { 2611 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2612 2613 u8 reserved_at_20[0x10]; 2614 u8 syndrome_id[0x10]; 2615 2616 u8 reserved_at_40[0x40]; 2617 2618 u8 error[8][0x20]; 2619 }; 2620 2621 struct mlx5_ifc_resource_dump_info_segment_bits { 2622 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2623 2624 u8 reserved_at_20[0x18]; 2625 u8 dump_version[0x8]; 2626 2627 u8 hw_version[0x20]; 2628 2629 u8 fw_version[0x20]; 2630 }; 2631 2632 struct mlx5_ifc_resource_dump_menu_segment_bits { 2633 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2634 2635 u8 reserved_at_20[0x10]; 2636 u8 num_of_records[0x10]; 2637 2638 struct mlx5_ifc_resource_dump_menu_record_bits record[]; 2639 }; 2640 2641 struct mlx5_ifc_resource_dump_resource_segment_bits { 2642 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2643 2644 u8 reserved_at_20[0x20]; 2645 2646 u8 index1[0x20]; 2647 2648 u8 index2[0x20]; 2649 2650 u8 payload[][0x20]; 2651 }; 2652 2653 struct mlx5_ifc_resource_dump_terminate_segment_bits { 2654 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2655 }; 2656 2657 struct mlx5_ifc_menu_resource_dump_response_bits { 2658 struct mlx5_ifc_resource_dump_info_segment_bits info; 2659 struct mlx5_ifc_resource_dump_command_segment_bits cmd; 2660 struct mlx5_ifc_resource_dump_menu_segment_bits menu; 2661 struct mlx5_ifc_resource_dump_terminate_segment_bits terminate; 2662 }; 2663 2664 enum { 2665 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1, 2666 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2, 2667 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4, 2668 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8, 2669 }; 2670 2671 struct mlx5_ifc_modify_field_select_bits { 2672 u8 modify_field_select[0x20]; 2673 }; 2674 2675 struct mlx5_ifc_field_select_r_roce_np_bits { 2676 u8 field_select_r_roce_np[0x20]; 2677 }; 2678 2679 struct mlx5_ifc_field_select_r_roce_rp_bits { 2680 u8 field_select_r_roce_rp[0x20]; 2681 }; 2682 2683 enum { 2684 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4, 2685 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8, 2686 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10, 2687 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20, 2688 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40, 2689 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80, 2690 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100, 2691 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200, 2692 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400, 2693 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800, 2694 }; 2695 2696 struct mlx5_ifc_field_select_802_1qau_rp_bits { 2697 u8 field_select_8021qaurp[0x20]; 2698 }; 2699 2700 struct mlx5_ifc_phys_layer_recovery_cntrs_bits { 2701 u8 total_successful_recovery_events[0x20]; 2702 2703 u8 reserved_at_20[0x7a0]; 2704 }; 2705 2706 struct mlx5_ifc_phys_layer_cntrs_bits { 2707 u8 time_since_last_clear_high[0x20]; 2708 2709 u8 time_since_last_clear_low[0x20]; 2710 2711 u8 symbol_errors_high[0x20]; 2712 2713 u8 symbol_errors_low[0x20]; 2714 2715 u8 sync_headers_errors_high[0x20]; 2716 2717 u8 sync_headers_errors_low[0x20]; 2718 2719 u8 edpl_bip_errors_lane0_high[0x20]; 2720 2721 u8 edpl_bip_errors_lane0_low[0x20]; 2722 2723 u8 edpl_bip_errors_lane1_high[0x20]; 2724 2725 u8 edpl_bip_errors_lane1_low[0x20]; 2726 2727 u8 edpl_bip_errors_lane2_high[0x20]; 2728 2729 u8 edpl_bip_errors_lane2_low[0x20]; 2730 2731 u8 edpl_bip_errors_lane3_high[0x20]; 2732 2733 u8 edpl_bip_errors_lane3_low[0x20]; 2734 2735 u8 fc_fec_corrected_blocks_lane0_high[0x20]; 2736 2737 u8 fc_fec_corrected_blocks_lane0_low[0x20]; 2738 2739 u8 fc_fec_corrected_blocks_lane1_high[0x20]; 2740 2741 u8 fc_fec_corrected_blocks_lane1_low[0x20]; 2742 2743 u8 fc_fec_corrected_blocks_lane2_high[0x20]; 2744 2745 u8 fc_fec_corrected_blocks_lane2_low[0x20]; 2746 2747 u8 fc_fec_corrected_blocks_lane3_high[0x20]; 2748 2749 u8 fc_fec_corrected_blocks_lane3_low[0x20]; 2750 2751 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20]; 2752 2753 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20]; 2754 2755 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20]; 2756 2757 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20]; 2758 2759 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20]; 2760 2761 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20]; 2762 2763 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20]; 2764 2765 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20]; 2766 2767 u8 rs_fec_corrected_blocks_high[0x20]; 2768 2769 u8 rs_fec_corrected_blocks_low[0x20]; 2770 2771 u8 rs_fec_uncorrectable_blocks_high[0x20]; 2772 2773 u8 rs_fec_uncorrectable_blocks_low[0x20]; 2774 2775 u8 rs_fec_no_errors_blocks_high[0x20]; 2776 2777 u8 rs_fec_no_errors_blocks_low[0x20]; 2778 2779 u8 rs_fec_single_error_blocks_high[0x20]; 2780 2781 u8 rs_fec_single_error_blocks_low[0x20]; 2782 2783 u8 rs_fec_corrected_symbols_total_high[0x20]; 2784 2785 u8 rs_fec_corrected_symbols_total_low[0x20]; 2786 2787 u8 rs_fec_corrected_symbols_lane0_high[0x20]; 2788 2789 u8 rs_fec_corrected_symbols_lane0_low[0x20]; 2790 2791 u8 rs_fec_corrected_symbols_lane1_high[0x20]; 2792 2793 u8 rs_fec_corrected_symbols_lane1_low[0x20]; 2794 2795 u8 rs_fec_corrected_symbols_lane2_high[0x20]; 2796 2797 u8 rs_fec_corrected_symbols_lane2_low[0x20]; 2798 2799 u8 rs_fec_corrected_symbols_lane3_high[0x20]; 2800 2801 u8 rs_fec_corrected_symbols_lane3_low[0x20]; 2802 2803 u8 link_down_events[0x20]; 2804 2805 u8 successful_recovery_events[0x20]; 2806 2807 u8 reserved_at_640[0x180]; 2808 }; 2809 2810 struct mlx5_ifc_phys_layer_statistical_cntrs_bits { 2811 u8 time_since_last_clear_high[0x20]; 2812 2813 u8 time_since_last_clear_low[0x20]; 2814 2815 u8 phy_received_bits_high[0x20]; 2816 2817 u8 phy_received_bits_low[0x20]; 2818 2819 u8 phy_symbol_errors_high[0x20]; 2820 2821 u8 phy_symbol_errors_low[0x20]; 2822 2823 u8 phy_corrected_bits_high[0x20]; 2824 2825 u8 phy_corrected_bits_low[0x20]; 2826 2827 u8 phy_corrected_bits_lane0_high[0x20]; 2828 2829 u8 phy_corrected_bits_lane0_low[0x20]; 2830 2831 u8 phy_corrected_bits_lane1_high[0x20]; 2832 2833 u8 phy_corrected_bits_lane1_low[0x20]; 2834 2835 u8 phy_corrected_bits_lane2_high[0x20]; 2836 2837 u8 phy_corrected_bits_lane2_low[0x20]; 2838 2839 u8 phy_corrected_bits_lane3_high[0x20]; 2840 2841 u8 phy_corrected_bits_lane3_low[0x20]; 2842 2843 u8 reserved_at_200[0x5c0]; 2844 }; 2845 2846 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits { 2847 u8 symbol_error_counter[0x10]; 2848 2849 u8 link_error_recovery_counter[0x8]; 2850 2851 u8 link_downed_counter[0x8]; 2852 2853 u8 port_rcv_errors[0x10]; 2854 2855 u8 port_rcv_remote_physical_errors[0x10]; 2856 2857 u8 port_rcv_switch_relay_errors[0x10]; 2858 2859 u8 port_xmit_discards[0x10]; 2860 2861 u8 port_xmit_constraint_errors[0x8]; 2862 2863 u8 port_rcv_constraint_errors[0x8]; 2864 2865 u8 reserved_at_70[0x8]; 2866 2867 u8 link_overrun_errors[0x8]; 2868 2869 u8 reserved_at_80[0x10]; 2870 2871 u8 vl_15_dropped[0x10]; 2872 2873 u8 reserved_at_a0[0x80]; 2874 2875 u8 port_xmit_wait[0x20]; 2876 }; 2877 2878 struct mlx5_ifc_ib_ext_port_cntrs_grp_data_layout_bits { 2879 u8 reserved_at_0[0x300]; 2880 2881 u8 port_xmit_data_high[0x20]; 2882 2883 u8 port_xmit_data_low[0x20]; 2884 2885 u8 port_rcv_data_high[0x20]; 2886 2887 u8 port_rcv_data_low[0x20]; 2888 2889 u8 port_xmit_pkts_high[0x20]; 2890 2891 u8 port_xmit_pkts_low[0x20]; 2892 2893 u8 port_rcv_pkts_high[0x20]; 2894 2895 u8 port_rcv_pkts_low[0x20]; 2896 2897 u8 reserved_at_400[0x80]; 2898 2899 u8 port_unicast_xmit_pkts_high[0x20]; 2900 2901 u8 port_unicast_xmit_pkts_low[0x20]; 2902 2903 u8 port_multicast_xmit_pkts_high[0x20]; 2904 2905 u8 port_multicast_xmit_pkts_low[0x20]; 2906 2907 u8 port_unicast_rcv_pkts_high[0x20]; 2908 2909 u8 port_unicast_rcv_pkts_low[0x20]; 2910 2911 u8 port_multicast_rcv_pkts_high[0x20]; 2912 2913 u8 port_multicast_rcv_pkts_low[0x20]; 2914 2915 u8 reserved_at_580[0x240]; 2916 }; 2917 2918 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits { 2919 u8 transmit_queue_high[0x20]; 2920 2921 u8 transmit_queue_low[0x20]; 2922 2923 u8 no_buffer_discard_uc_high[0x20]; 2924 2925 u8 no_buffer_discard_uc_low[0x20]; 2926 2927 u8 reserved_at_80[0x740]; 2928 }; 2929 2930 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits { 2931 u8 wred_discard_high[0x20]; 2932 2933 u8 wred_discard_low[0x20]; 2934 2935 u8 ecn_marked_tc_high[0x20]; 2936 2937 u8 ecn_marked_tc_low[0x20]; 2938 2939 u8 reserved_at_80[0x740]; 2940 }; 2941 2942 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits { 2943 u8 rx_octets_high[0x20]; 2944 2945 u8 rx_octets_low[0x20]; 2946 2947 u8 reserved_at_40[0xc0]; 2948 2949 u8 rx_frames_high[0x20]; 2950 2951 u8 rx_frames_low[0x20]; 2952 2953 u8 tx_octets_high[0x20]; 2954 2955 u8 tx_octets_low[0x20]; 2956 2957 u8 reserved_at_180[0xc0]; 2958 2959 u8 tx_frames_high[0x20]; 2960 2961 u8 tx_frames_low[0x20]; 2962 2963 u8 rx_pause_high[0x20]; 2964 2965 u8 rx_pause_low[0x20]; 2966 2967 u8 rx_pause_duration_high[0x20]; 2968 2969 u8 rx_pause_duration_low[0x20]; 2970 2971 u8 tx_pause_high[0x20]; 2972 2973 u8 tx_pause_low[0x20]; 2974 2975 u8 tx_pause_duration_high[0x20]; 2976 2977 u8 tx_pause_duration_low[0x20]; 2978 2979 u8 rx_pause_transition_high[0x20]; 2980 2981 u8 rx_pause_transition_low[0x20]; 2982 2983 u8 rx_discards_high[0x20]; 2984 2985 u8 rx_discards_low[0x20]; 2986 2987 u8 device_stall_minor_watermark_cnt_high[0x20]; 2988 2989 u8 device_stall_minor_watermark_cnt_low[0x20]; 2990 2991 u8 device_stall_critical_watermark_cnt_high[0x20]; 2992 2993 u8 device_stall_critical_watermark_cnt_low[0x20]; 2994 2995 u8 reserved_at_480[0x340]; 2996 }; 2997 2998 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits { 2999 u8 port_transmit_wait_high[0x20]; 3000 3001 u8 port_transmit_wait_low[0x20]; 3002 3003 u8 reserved_at_40[0x100]; 3004 3005 u8 rx_buffer_almost_full_high[0x20]; 3006 3007 u8 rx_buffer_almost_full_low[0x20]; 3008 3009 u8 rx_buffer_full_high[0x20]; 3010 3011 u8 rx_buffer_full_low[0x20]; 3012 3013 u8 rx_icrc_encapsulated_high[0x20]; 3014 3015 u8 rx_icrc_encapsulated_low[0x20]; 3016 3017 u8 reserved_at_200[0x5c0]; 3018 }; 3019 3020 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits { 3021 u8 dot3stats_alignment_errors_high[0x20]; 3022 3023 u8 dot3stats_alignment_errors_low[0x20]; 3024 3025 u8 dot3stats_fcs_errors_high[0x20]; 3026 3027 u8 dot3stats_fcs_errors_low[0x20]; 3028 3029 u8 dot3stats_single_collision_frames_high[0x20]; 3030 3031 u8 dot3stats_single_collision_frames_low[0x20]; 3032 3033 u8 dot3stats_multiple_collision_frames_high[0x20]; 3034 3035 u8 dot3stats_multiple_collision_frames_low[0x20]; 3036 3037 u8 dot3stats_sqe_test_errors_high[0x20]; 3038 3039 u8 dot3stats_sqe_test_errors_low[0x20]; 3040 3041 u8 dot3stats_deferred_transmissions_high[0x20]; 3042 3043 u8 dot3stats_deferred_transmissions_low[0x20]; 3044 3045 u8 dot3stats_late_collisions_high[0x20]; 3046 3047 u8 dot3stats_late_collisions_low[0x20]; 3048 3049 u8 dot3stats_excessive_collisions_high[0x20]; 3050 3051 u8 dot3stats_excessive_collisions_low[0x20]; 3052 3053 u8 dot3stats_internal_mac_transmit_errors_high[0x20]; 3054 3055 u8 dot3stats_internal_mac_transmit_errors_low[0x20]; 3056 3057 u8 dot3stats_carrier_sense_errors_high[0x20]; 3058 3059 u8 dot3stats_carrier_sense_errors_low[0x20]; 3060 3061 u8 dot3stats_frame_too_longs_high[0x20]; 3062 3063 u8 dot3stats_frame_too_longs_low[0x20]; 3064 3065 u8 dot3stats_internal_mac_receive_errors_high[0x20]; 3066 3067 u8 dot3stats_internal_mac_receive_errors_low[0x20]; 3068 3069 u8 dot3stats_symbol_errors_high[0x20]; 3070 3071 u8 dot3stats_symbol_errors_low[0x20]; 3072 3073 u8 dot3control_in_unknown_opcodes_high[0x20]; 3074 3075 u8 dot3control_in_unknown_opcodes_low[0x20]; 3076 3077 u8 dot3in_pause_frames_high[0x20]; 3078 3079 u8 dot3in_pause_frames_low[0x20]; 3080 3081 u8 dot3out_pause_frames_high[0x20]; 3082 3083 u8 dot3out_pause_frames_low[0x20]; 3084 3085 u8 reserved_at_400[0x3c0]; 3086 }; 3087 3088 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits { 3089 u8 ether_stats_drop_events_high[0x20]; 3090 3091 u8 ether_stats_drop_events_low[0x20]; 3092 3093 u8 ether_stats_octets_high[0x20]; 3094 3095 u8 ether_stats_octets_low[0x20]; 3096 3097 u8 ether_stats_pkts_high[0x20]; 3098 3099 u8 ether_stats_pkts_low[0x20]; 3100 3101 u8 ether_stats_broadcast_pkts_high[0x20]; 3102 3103 u8 ether_stats_broadcast_pkts_low[0x20]; 3104 3105 u8 ether_stats_multicast_pkts_high[0x20]; 3106 3107 u8 ether_stats_multicast_pkts_low[0x20]; 3108 3109 u8 ether_stats_crc_align_errors_high[0x20]; 3110 3111 u8 ether_stats_crc_align_errors_low[0x20]; 3112 3113 u8 ether_stats_undersize_pkts_high[0x20]; 3114 3115 u8 ether_stats_undersize_pkts_low[0x20]; 3116 3117 u8 ether_stats_oversize_pkts_high[0x20]; 3118 3119 u8 ether_stats_oversize_pkts_low[0x20]; 3120 3121 u8 ether_stats_fragments_high[0x20]; 3122 3123 u8 ether_stats_fragments_low[0x20]; 3124 3125 u8 ether_stats_jabbers_high[0x20]; 3126 3127 u8 ether_stats_jabbers_low[0x20]; 3128 3129 u8 ether_stats_collisions_high[0x20]; 3130 3131 u8 ether_stats_collisions_low[0x20]; 3132 3133 u8 ether_stats_pkts64octets_high[0x20]; 3134 3135 u8 ether_stats_pkts64octets_low[0x20]; 3136 3137 u8 ether_stats_pkts65to127octets_high[0x20]; 3138 3139 u8 ether_stats_pkts65to127octets_low[0x20]; 3140 3141 u8 ether_stats_pkts128to255octets_high[0x20]; 3142 3143 u8 ether_stats_pkts128to255octets_low[0x20]; 3144 3145 u8 ether_stats_pkts256to511octets_high[0x20]; 3146 3147 u8 ether_stats_pkts256to511octets_low[0x20]; 3148 3149 u8 ether_stats_pkts512to1023octets_high[0x20]; 3150 3151 u8 ether_stats_pkts512to1023octets_low[0x20]; 3152 3153 u8 ether_stats_pkts1024to1518octets_high[0x20]; 3154 3155 u8 ether_stats_pkts1024to1518octets_low[0x20]; 3156 3157 u8 ether_stats_pkts1519to2047octets_high[0x20]; 3158 3159 u8 ether_stats_pkts1519to2047octets_low[0x20]; 3160 3161 u8 ether_stats_pkts2048to4095octets_high[0x20]; 3162 3163 u8 ether_stats_pkts2048to4095octets_low[0x20]; 3164 3165 u8 ether_stats_pkts4096to8191octets_high[0x20]; 3166 3167 u8 ether_stats_pkts4096to8191octets_low[0x20]; 3168 3169 u8 ether_stats_pkts8192to10239octets_high[0x20]; 3170 3171 u8 ether_stats_pkts8192to10239octets_low[0x20]; 3172 3173 u8 reserved_at_540[0x280]; 3174 }; 3175 3176 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits { 3177 u8 if_in_octets_high[0x20]; 3178 3179 u8 if_in_octets_low[0x20]; 3180 3181 u8 if_in_ucast_pkts_high[0x20]; 3182 3183 u8 if_in_ucast_pkts_low[0x20]; 3184 3185 u8 if_in_discards_high[0x20]; 3186 3187 u8 if_in_discards_low[0x20]; 3188 3189 u8 if_in_errors_high[0x20]; 3190 3191 u8 if_in_errors_low[0x20]; 3192 3193 u8 if_in_unknown_protos_high[0x20]; 3194 3195 u8 if_in_unknown_protos_low[0x20]; 3196 3197 u8 if_out_octets_high[0x20]; 3198 3199 u8 if_out_octets_low[0x20]; 3200 3201 u8 if_out_ucast_pkts_high[0x20]; 3202 3203 u8 if_out_ucast_pkts_low[0x20]; 3204 3205 u8 if_out_discards_high[0x20]; 3206 3207 u8 if_out_discards_low[0x20]; 3208 3209 u8 if_out_errors_high[0x20]; 3210 3211 u8 if_out_errors_low[0x20]; 3212 3213 u8 if_in_multicast_pkts_high[0x20]; 3214 3215 u8 if_in_multicast_pkts_low[0x20]; 3216 3217 u8 if_in_broadcast_pkts_high[0x20]; 3218 3219 u8 if_in_broadcast_pkts_low[0x20]; 3220 3221 u8 if_out_multicast_pkts_high[0x20]; 3222 3223 u8 if_out_multicast_pkts_low[0x20]; 3224 3225 u8 if_out_broadcast_pkts_high[0x20]; 3226 3227 u8 if_out_broadcast_pkts_low[0x20]; 3228 3229 u8 reserved_at_340[0x480]; 3230 }; 3231 3232 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits { 3233 u8 a_frames_transmitted_ok_high[0x20]; 3234 3235 u8 a_frames_transmitted_ok_low[0x20]; 3236 3237 u8 a_frames_received_ok_high[0x20]; 3238 3239 u8 a_frames_received_ok_low[0x20]; 3240 3241 u8 a_frame_check_sequence_errors_high[0x20]; 3242 3243 u8 a_frame_check_sequence_errors_low[0x20]; 3244 3245 u8 a_alignment_errors_high[0x20]; 3246 3247 u8 a_alignment_errors_low[0x20]; 3248 3249 u8 a_octets_transmitted_ok_high[0x20]; 3250 3251 u8 a_octets_transmitted_ok_low[0x20]; 3252 3253 u8 a_octets_received_ok_high[0x20]; 3254 3255 u8 a_octets_received_ok_low[0x20]; 3256 3257 u8 a_multicast_frames_xmitted_ok_high[0x20]; 3258 3259 u8 a_multicast_frames_xmitted_ok_low[0x20]; 3260 3261 u8 a_broadcast_frames_xmitted_ok_high[0x20]; 3262 3263 u8 a_broadcast_frames_xmitted_ok_low[0x20]; 3264 3265 u8 a_multicast_frames_received_ok_high[0x20]; 3266 3267 u8 a_multicast_frames_received_ok_low[0x20]; 3268 3269 u8 a_broadcast_frames_received_ok_high[0x20]; 3270 3271 u8 a_broadcast_frames_received_ok_low[0x20]; 3272 3273 u8 a_in_range_length_errors_high[0x20]; 3274 3275 u8 a_in_range_length_errors_low[0x20]; 3276 3277 u8 a_out_of_range_length_field_high[0x20]; 3278 3279 u8 a_out_of_range_length_field_low[0x20]; 3280 3281 u8 a_frame_too_long_errors_high[0x20]; 3282 3283 u8 a_frame_too_long_errors_low[0x20]; 3284 3285 u8 a_symbol_error_during_carrier_high[0x20]; 3286 3287 u8 a_symbol_error_during_carrier_low[0x20]; 3288 3289 u8 a_mac_control_frames_transmitted_high[0x20]; 3290 3291 u8 a_mac_control_frames_transmitted_low[0x20]; 3292 3293 u8 a_mac_control_frames_received_high[0x20]; 3294 3295 u8 a_mac_control_frames_received_low[0x20]; 3296 3297 u8 a_unsupported_opcodes_received_high[0x20]; 3298 3299 u8 a_unsupported_opcodes_received_low[0x20]; 3300 3301 u8 a_pause_mac_ctrl_frames_received_high[0x20]; 3302 3303 u8 a_pause_mac_ctrl_frames_received_low[0x20]; 3304 3305 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20]; 3306 3307 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20]; 3308 3309 u8 reserved_at_4c0[0x300]; 3310 }; 3311 3312 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits { 3313 u8 life_time_counter_high[0x20]; 3314 3315 u8 life_time_counter_low[0x20]; 3316 3317 u8 rx_errors[0x20]; 3318 3319 u8 tx_errors[0x20]; 3320 3321 u8 l0_to_recovery_eieos[0x20]; 3322 3323 u8 l0_to_recovery_ts[0x20]; 3324 3325 u8 l0_to_recovery_framing[0x20]; 3326 3327 u8 l0_to_recovery_retrain[0x20]; 3328 3329 u8 crc_error_dllp[0x20]; 3330 3331 u8 crc_error_tlp[0x20]; 3332 3333 u8 tx_overflow_buffer_pkt_high[0x20]; 3334 3335 u8 tx_overflow_buffer_pkt_low[0x20]; 3336 3337 u8 outbound_stalled_reads[0x20]; 3338 3339 u8 outbound_stalled_writes[0x20]; 3340 3341 u8 outbound_stalled_reads_events[0x20]; 3342 3343 u8 outbound_stalled_writes_events[0x20]; 3344 3345 u8 reserved_at_200[0x5c0]; 3346 }; 3347 3348 struct mlx5_ifc_cmd_inter_comp_event_bits { 3349 u8 command_completion_vector[0x20]; 3350 3351 u8 reserved_at_20[0xc0]; 3352 }; 3353 3354 struct mlx5_ifc_stall_vl_event_bits { 3355 u8 reserved_at_0[0x18]; 3356 u8 port_num[0x1]; 3357 u8 reserved_at_19[0x3]; 3358 u8 vl[0x4]; 3359 3360 u8 reserved_at_20[0xa0]; 3361 }; 3362 3363 struct mlx5_ifc_db_bf_congestion_event_bits { 3364 u8 event_subtype[0x8]; 3365 u8 reserved_at_8[0x8]; 3366 u8 congestion_level[0x8]; 3367 u8 reserved_at_18[0x8]; 3368 3369 u8 reserved_at_20[0xa0]; 3370 }; 3371 3372 struct mlx5_ifc_gpio_event_bits { 3373 u8 reserved_at_0[0x60]; 3374 3375 u8 gpio_event_hi[0x20]; 3376 3377 u8 gpio_event_lo[0x20]; 3378 3379 u8 reserved_at_a0[0x40]; 3380 }; 3381 3382 struct mlx5_ifc_port_state_change_event_bits { 3383 u8 reserved_at_0[0x40]; 3384 3385 u8 port_num[0x4]; 3386 u8 reserved_at_44[0x1c]; 3387 3388 u8 reserved_at_60[0x80]; 3389 }; 3390 3391 struct mlx5_ifc_dropped_packet_logged_bits { 3392 u8 reserved_at_0[0xe0]; 3393 }; 3394 3395 struct mlx5_ifc_nic_cap_reg_bits { 3396 u8 reserved_at_0[0x1a]; 3397 u8 vhca_icm_ctrl[0x1]; 3398 u8 reserved_at_1b[0x5]; 3399 3400 u8 reserved_at_20[0x60]; 3401 }; 3402 3403 struct mlx5_ifc_default_timeout_bits { 3404 u8 to_multiplier[0x3]; 3405 u8 reserved_at_3[0x9]; 3406 u8 to_value[0x14]; 3407 }; 3408 3409 struct mlx5_ifc_dtor_reg_bits { 3410 u8 reserved_at_0[0x20]; 3411 3412 struct mlx5_ifc_default_timeout_bits pcie_toggle_to; 3413 3414 u8 reserved_at_40[0x60]; 3415 3416 struct mlx5_ifc_default_timeout_bits health_poll_to; 3417 3418 struct mlx5_ifc_default_timeout_bits full_crdump_to; 3419 3420 struct mlx5_ifc_default_timeout_bits fw_reset_to; 3421 3422 struct mlx5_ifc_default_timeout_bits flush_on_err_to; 3423 3424 struct mlx5_ifc_default_timeout_bits pci_sync_update_to; 3425 3426 struct mlx5_ifc_default_timeout_bits tear_down_to; 3427 3428 struct mlx5_ifc_default_timeout_bits fsm_reactivate_to; 3429 3430 struct mlx5_ifc_default_timeout_bits reclaim_pages_to; 3431 3432 struct mlx5_ifc_default_timeout_bits reclaim_vfs_pages_to; 3433 3434 struct mlx5_ifc_default_timeout_bits reset_unload_to; 3435 3436 u8 reserved_at_1c0[0x20]; 3437 }; 3438 3439 struct mlx5_ifc_vhca_icm_ctrl_reg_bits { 3440 u8 vhca_id_valid[0x1]; 3441 u8 reserved_at_1[0xf]; 3442 u8 vhca_id[0x10]; 3443 3444 u8 reserved_at_20[0xa0]; 3445 3446 u8 cur_alloc_icm[0x20]; 3447 3448 u8 reserved_at_e0[0x120]; 3449 }; 3450 3451 enum { 3452 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1, 3453 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2, 3454 }; 3455 3456 struct mlx5_ifc_cq_error_bits { 3457 u8 reserved_at_0[0x8]; 3458 u8 cqn[0x18]; 3459 3460 u8 reserved_at_20[0x20]; 3461 3462 u8 reserved_at_40[0x18]; 3463 u8 syndrome[0x8]; 3464 3465 u8 reserved_at_60[0x80]; 3466 }; 3467 3468 struct mlx5_ifc_rdma_page_fault_event_bits { 3469 u8 bytes_committed[0x20]; 3470 3471 u8 r_key[0x20]; 3472 3473 u8 reserved_at_40[0x10]; 3474 u8 packet_len[0x10]; 3475 3476 u8 rdma_op_len[0x20]; 3477 3478 u8 rdma_va[0x40]; 3479 3480 u8 reserved_at_c0[0x5]; 3481 u8 rdma[0x1]; 3482 u8 write[0x1]; 3483 u8 requestor[0x1]; 3484 u8 qp_number[0x18]; 3485 }; 3486 3487 struct mlx5_ifc_wqe_associated_page_fault_event_bits { 3488 u8 bytes_committed[0x20]; 3489 3490 u8 reserved_at_20[0x10]; 3491 u8 wqe_index[0x10]; 3492 3493 u8 reserved_at_40[0x10]; 3494 u8 len[0x10]; 3495 3496 u8 reserved_at_60[0x60]; 3497 3498 u8 reserved_at_c0[0x5]; 3499 u8 rdma[0x1]; 3500 u8 write_read[0x1]; 3501 u8 requestor[0x1]; 3502 u8 qpn[0x18]; 3503 }; 3504 3505 struct mlx5_ifc_qp_events_bits { 3506 u8 reserved_at_0[0xa0]; 3507 3508 u8 type[0x8]; 3509 u8 reserved_at_a8[0x18]; 3510 3511 u8 reserved_at_c0[0x8]; 3512 u8 qpn_rqn_sqn[0x18]; 3513 }; 3514 3515 struct mlx5_ifc_dct_events_bits { 3516 u8 reserved_at_0[0xc0]; 3517 3518 u8 reserved_at_c0[0x8]; 3519 u8 dct_number[0x18]; 3520 }; 3521 3522 struct mlx5_ifc_comp_event_bits { 3523 u8 reserved_at_0[0xc0]; 3524 3525 u8 reserved_at_c0[0x8]; 3526 u8 cq_number[0x18]; 3527 }; 3528 3529 enum { 3530 MLX5_QPC_STATE_RST = 0x0, 3531 MLX5_QPC_STATE_INIT = 0x1, 3532 MLX5_QPC_STATE_RTR = 0x2, 3533 MLX5_QPC_STATE_RTS = 0x3, 3534 MLX5_QPC_STATE_SQER = 0x4, 3535 MLX5_QPC_STATE_ERR = 0x6, 3536 MLX5_QPC_STATE_SQD = 0x7, 3537 MLX5_QPC_STATE_SUSPENDED = 0x9, 3538 }; 3539 3540 enum { 3541 MLX5_QPC_ST_RC = 0x0, 3542 MLX5_QPC_ST_UC = 0x1, 3543 MLX5_QPC_ST_UD = 0x2, 3544 MLX5_QPC_ST_XRC = 0x3, 3545 MLX5_QPC_ST_DCI = 0x5, 3546 MLX5_QPC_ST_QP0 = 0x7, 3547 MLX5_QPC_ST_QP1 = 0x8, 3548 MLX5_QPC_ST_RAW_DATAGRAM = 0x9, 3549 MLX5_QPC_ST_REG_UMR = 0xc, 3550 }; 3551 3552 enum { 3553 MLX5_QPC_PM_STATE_ARMED = 0x0, 3554 MLX5_QPC_PM_STATE_REARM = 0x1, 3555 MLX5_QPC_PM_STATE_RESERVED = 0x2, 3556 MLX5_QPC_PM_STATE_MIGRATED = 0x3, 3557 }; 3558 3559 enum { 3560 MLX5_QPC_OFFLOAD_TYPE_RNDV = 0x1, 3561 }; 3562 3563 enum { 3564 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0, 3565 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1, 3566 }; 3567 3568 enum { 3569 MLX5_QPC_MTU_256_BYTES = 0x1, 3570 MLX5_QPC_MTU_512_BYTES = 0x2, 3571 MLX5_QPC_MTU_1K_BYTES = 0x3, 3572 MLX5_QPC_MTU_2K_BYTES = 0x4, 3573 MLX5_QPC_MTU_4K_BYTES = 0x5, 3574 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7, 3575 }; 3576 3577 enum { 3578 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1, 3579 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2, 3580 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3, 3581 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4, 3582 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5, 3583 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6, 3584 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7, 3585 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8, 3586 }; 3587 3588 enum { 3589 MLX5_QPC_CS_REQ_DISABLE = 0x0, 3590 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11, 3591 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22, 3592 }; 3593 3594 enum { 3595 MLX5_QPC_CS_RES_DISABLE = 0x0, 3596 MLX5_QPC_CS_RES_UP_TO_32B = 0x1, 3597 MLX5_QPC_CS_RES_UP_TO_64B = 0x2, 3598 }; 3599 3600 enum { 3601 MLX5_TIMESTAMP_FORMAT_FREE_RUNNING = 0x0, 3602 MLX5_TIMESTAMP_FORMAT_DEFAULT = 0x1, 3603 MLX5_TIMESTAMP_FORMAT_REAL_TIME = 0x2, 3604 }; 3605 3606 struct mlx5_ifc_qpc_bits { 3607 u8 state[0x4]; 3608 u8 lag_tx_port_affinity[0x4]; 3609 u8 st[0x8]; 3610 u8 reserved_at_10[0x2]; 3611 u8 isolate_vl_tc[0x1]; 3612 u8 pm_state[0x2]; 3613 u8 reserved_at_15[0x1]; 3614 u8 req_e2e_credit_mode[0x2]; 3615 u8 offload_type[0x4]; 3616 u8 end_padding_mode[0x2]; 3617 u8 reserved_at_1e[0x2]; 3618 3619 u8 wq_signature[0x1]; 3620 u8 block_lb_mc[0x1]; 3621 u8 atomic_like_write_en[0x1]; 3622 u8 latency_sensitive[0x1]; 3623 u8 reserved_at_24[0x1]; 3624 u8 drain_sigerr[0x1]; 3625 u8 reserved_at_26[0x1]; 3626 u8 dp_ordering_force[0x1]; 3627 u8 pd[0x18]; 3628 3629 u8 mtu[0x3]; 3630 u8 log_msg_max[0x5]; 3631 u8 reserved_at_48[0x1]; 3632 u8 log_rq_size[0x4]; 3633 u8 log_rq_stride[0x3]; 3634 u8 no_sq[0x1]; 3635 u8 log_sq_size[0x4]; 3636 u8 reserved_at_55[0x1]; 3637 u8 retry_mode[0x2]; 3638 u8 ts_format[0x2]; 3639 u8 reserved_at_5a[0x1]; 3640 u8 rlky[0x1]; 3641 u8 ulp_stateless_offload_mode[0x4]; 3642 3643 u8 counter_set_id[0x8]; 3644 u8 uar_page[0x18]; 3645 3646 u8 reserved_at_80[0x8]; 3647 u8 user_index[0x18]; 3648 3649 u8 reserved_at_a0[0x3]; 3650 u8 log_page_size[0x5]; 3651 u8 remote_qpn[0x18]; 3652 3653 struct mlx5_ifc_ads_bits primary_address_path; 3654 3655 struct mlx5_ifc_ads_bits secondary_address_path; 3656 3657 u8 log_ack_req_freq[0x4]; 3658 u8 reserved_at_384[0x4]; 3659 u8 log_sra_max[0x3]; 3660 u8 reserved_at_38b[0x2]; 3661 u8 retry_count[0x3]; 3662 u8 rnr_retry[0x3]; 3663 u8 reserved_at_393[0x1]; 3664 u8 fre[0x1]; 3665 u8 cur_rnr_retry[0x3]; 3666 u8 cur_retry_count[0x3]; 3667 u8 reserved_at_39b[0x5]; 3668 3669 u8 reserved_at_3a0[0x20]; 3670 3671 u8 reserved_at_3c0[0x8]; 3672 u8 next_send_psn[0x18]; 3673 3674 u8 reserved_at_3e0[0x3]; 3675 u8 log_num_dci_stream_channels[0x5]; 3676 u8 cqn_snd[0x18]; 3677 3678 u8 reserved_at_400[0x3]; 3679 u8 log_num_dci_errored_streams[0x5]; 3680 u8 deth_sqpn[0x18]; 3681 3682 u8 reserved_at_420[0x20]; 3683 3684 u8 reserved_at_440[0x8]; 3685 u8 last_acked_psn[0x18]; 3686 3687 u8 reserved_at_460[0x8]; 3688 u8 ssn[0x18]; 3689 3690 u8 reserved_at_480[0x8]; 3691 u8 log_rra_max[0x3]; 3692 u8 reserved_at_48b[0x1]; 3693 u8 atomic_mode[0x4]; 3694 u8 rre[0x1]; 3695 u8 rwe[0x1]; 3696 u8 rae[0x1]; 3697 u8 reserved_at_493[0x1]; 3698 u8 page_offset[0x6]; 3699 u8 reserved_at_49a[0x2]; 3700 u8 dp_ordering_1[0x1]; 3701 u8 cd_slave_receive[0x1]; 3702 u8 cd_slave_send[0x1]; 3703 u8 cd_master[0x1]; 3704 3705 u8 reserved_at_4a0[0x3]; 3706 u8 min_rnr_nak[0x5]; 3707 u8 next_rcv_psn[0x18]; 3708 3709 u8 reserved_at_4c0[0x8]; 3710 u8 xrcd[0x18]; 3711 3712 u8 reserved_at_4e0[0x8]; 3713 u8 cqn_rcv[0x18]; 3714 3715 u8 dbr_addr[0x40]; 3716 3717 u8 q_key[0x20]; 3718 3719 u8 reserved_at_560[0x5]; 3720 u8 rq_type[0x3]; 3721 u8 srqn_rmpn_xrqn[0x18]; 3722 3723 u8 reserved_at_580[0x8]; 3724 u8 rmsn[0x18]; 3725 3726 u8 hw_sq_wqebb_counter[0x10]; 3727 u8 sw_sq_wqebb_counter[0x10]; 3728 3729 u8 hw_rq_counter[0x20]; 3730 3731 u8 sw_rq_counter[0x20]; 3732 3733 u8 reserved_at_600[0x20]; 3734 3735 u8 reserved_at_620[0xf]; 3736 u8 cgs[0x1]; 3737 u8 cs_req[0x8]; 3738 u8 cs_res[0x8]; 3739 3740 u8 dc_access_key[0x40]; 3741 3742 u8 reserved_at_680[0x3]; 3743 u8 dbr_umem_valid[0x1]; 3744 3745 u8 reserved_at_684[0xbc]; 3746 }; 3747 3748 struct mlx5_ifc_roce_addr_layout_bits { 3749 u8 source_l3_address[16][0x8]; 3750 3751 u8 reserved_at_80[0x3]; 3752 u8 vlan_valid[0x1]; 3753 u8 vlan_id[0xc]; 3754 u8 source_mac_47_32[0x10]; 3755 3756 u8 source_mac_31_0[0x20]; 3757 3758 u8 reserved_at_c0[0x14]; 3759 u8 roce_l3_type[0x4]; 3760 u8 roce_version[0x8]; 3761 3762 u8 reserved_at_e0[0x20]; 3763 }; 3764 3765 struct mlx5_ifc_crypto_cap_bits { 3766 u8 reserved_at_0[0x3]; 3767 u8 synchronize_dek[0x1]; 3768 u8 int_kek_manual[0x1]; 3769 u8 int_kek_auto[0x1]; 3770 u8 reserved_at_6[0x1a]; 3771 3772 u8 reserved_at_20[0x3]; 3773 u8 log_dek_max_alloc[0x5]; 3774 u8 reserved_at_28[0x3]; 3775 u8 log_max_num_deks[0x5]; 3776 u8 reserved_at_30[0x10]; 3777 3778 u8 reserved_at_40[0x20]; 3779 3780 u8 reserved_at_60[0x3]; 3781 u8 log_dek_granularity[0x5]; 3782 u8 reserved_at_68[0x3]; 3783 u8 log_max_num_int_kek[0x5]; 3784 u8 sw_wrapped_dek[0x10]; 3785 3786 u8 reserved_at_80[0x780]; 3787 }; 3788 3789 struct mlx5_ifc_shampo_cap_bits { 3790 u8 reserved_at_0[0x3]; 3791 u8 shampo_log_max_reservation_size[0x5]; 3792 u8 reserved_at_8[0x3]; 3793 u8 shampo_log_min_reservation_size[0x5]; 3794 u8 shampo_min_mss_size[0x10]; 3795 3796 u8 shampo_header_split[0x1]; 3797 u8 shampo_header_split_data_merge[0x1]; 3798 u8 reserved_at_22[0x1]; 3799 u8 shampo_log_max_headers_entry_size[0x5]; 3800 u8 reserved_at_28[0x18]; 3801 3802 u8 reserved_at_40[0x7c0]; 3803 }; 3804 3805 union mlx5_ifc_hca_cap_union_bits { 3806 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap; 3807 struct mlx5_ifc_cmd_hca_cap_2_bits cmd_hca_cap_2; 3808 struct mlx5_ifc_odp_cap_bits odp_cap; 3809 struct mlx5_ifc_atomic_caps_bits atomic_caps; 3810 struct mlx5_ifc_roce_cap_bits roce_cap; 3811 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps; 3812 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap; 3813 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap; 3814 struct mlx5_ifc_wqe_based_flow_table_cap_bits wqe_based_flow_table_cap; 3815 struct mlx5_ifc_esw_cap_bits esw_cap; 3816 struct mlx5_ifc_e_switch_cap_bits e_switch_cap; 3817 struct mlx5_ifc_port_selection_cap_bits port_selection_cap; 3818 struct mlx5_ifc_qos_cap_bits qos_cap; 3819 struct mlx5_ifc_debug_cap_bits debug_cap; 3820 struct mlx5_ifc_fpga_cap_bits fpga_cap; 3821 struct mlx5_ifc_tls_cap_bits tls_cap; 3822 struct mlx5_ifc_device_mem_cap_bits device_mem_cap; 3823 struct mlx5_ifc_virtio_emulation_cap_bits virtio_emulation_cap; 3824 struct mlx5_ifc_macsec_cap_bits macsec_cap; 3825 struct mlx5_ifc_crypto_cap_bits crypto_cap; 3826 struct mlx5_ifc_ipsec_cap_bits ipsec_cap; 3827 struct mlx5_ifc_psp_cap_bits psp_cap; 3828 u8 reserved_at_0[0x8000]; 3829 }; 3830 3831 enum { 3832 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1, 3833 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2, 3834 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4, 3835 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8, 3836 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT = 0x10, 3837 MLX5_FLOW_CONTEXT_ACTION_DECAP = 0x20, 3838 MLX5_FLOW_CONTEXT_ACTION_MOD_HDR = 0x40, 3839 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP = 0x80, 3840 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100, 3841 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2 = 0x400, 3842 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2 = 0x800, 3843 MLX5_FLOW_CONTEXT_ACTION_CRYPTO_DECRYPT = 0x1000, 3844 MLX5_FLOW_CONTEXT_ACTION_CRYPTO_ENCRYPT = 0x2000, 3845 MLX5_FLOW_CONTEXT_ACTION_EXECUTE_ASO = 0x4000, 3846 }; 3847 3848 enum { 3849 MLX5_FLOW_CONTEXT_FLOW_SOURCE_ANY_VPORT = 0x0, 3850 MLX5_FLOW_CONTEXT_FLOW_SOURCE_UPLINK = 0x1, 3851 MLX5_FLOW_CONTEXT_FLOW_SOURCE_LOCAL_VPORT = 0x2, 3852 }; 3853 3854 enum { 3855 MLX5_FLOW_CONTEXT_ENCRYPT_DECRYPT_TYPE_IPSEC = 0x0, 3856 MLX5_FLOW_CONTEXT_ENCRYPT_DECRYPT_TYPE_MACSEC = 0x1, 3857 MLX5_FLOW_CONTEXT_ENCRYPT_DECRYPT_TYPE_PSP = 0x2, 3858 }; 3859 3860 struct mlx5_ifc_vlan_bits { 3861 u8 ethtype[0x10]; 3862 u8 prio[0x3]; 3863 u8 cfi[0x1]; 3864 u8 vid[0xc]; 3865 }; 3866 3867 enum { 3868 MLX5_FLOW_METER_COLOR_RED = 0x0, 3869 MLX5_FLOW_METER_COLOR_YELLOW = 0x1, 3870 MLX5_FLOW_METER_COLOR_GREEN = 0x2, 3871 MLX5_FLOW_METER_COLOR_UNDEFINED = 0x3, 3872 }; 3873 3874 enum { 3875 MLX5_EXE_ASO_FLOW_METER = 0x2, 3876 }; 3877 3878 struct mlx5_ifc_exe_aso_ctrl_flow_meter_bits { 3879 u8 return_reg_id[0x4]; 3880 u8 aso_type[0x4]; 3881 u8 reserved_at_8[0x14]; 3882 u8 action[0x1]; 3883 u8 init_color[0x2]; 3884 u8 meter_id[0x1]; 3885 }; 3886 3887 union mlx5_ifc_exe_aso_ctrl { 3888 struct mlx5_ifc_exe_aso_ctrl_flow_meter_bits exe_aso_ctrl_flow_meter; 3889 }; 3890 3891 struct mlx5_ifc_execute_aso_bits { 3892 u8 valid[0x1]; 3893 u8 reserved_at_1[0x7]; 3894 u8 aso_object_id[0x18]; 3895 3896 union mlx5_ifc_exe_aso_ctrl exe_aso_ctrl; 3897 }; 3898 3899 struct mlx5_ifc_flow_context_bits { 3900 struct mlx5_ifc_vlan_bits push_vlan; 3901 3902 u8 group_id[0x20]; 3903 3904 u8 reserved_at_40[0x8]; 3905 u8 flow_tag[0x18]; 3906 3907 u8 reserved_at_60[0x10]; 3908 u8 action[0x10]; 3909 3910 u8 extended_destination[0x1]; 3911 u8 uplink_hairpin_en[0x1]; 3912 u8 flow_source[0x2]; 3913 u8 encrypt_decrypt_type[0x4]; 3914 u8 destination_list_size[0x18]; 3915 3916 u8 reserved_at_a0[0x8]; 3917 u8 flow_counter_list_size[0x18]; 3918 3919 u8 packet_reformat_id[0x20]; 3920 3921 u8 modify_header_id[0x20]; 3922 3923 struct mlx5_ifc_vlan_bits push_vlan_2; 3924 3925 u8 encrypt_decrypt_obj_id[0x20]; 3926 u8 reserved_at_140[0xc0]; 3927 3928 struct mlx5_ifc_fte_match_param_bits match_value; 3929 3930 struct mlx5_ifc_execute_aso_bits execute_aso[4]; 3931 3932 u8 reserved_at_1300[0x500]; 3933 3934 union mlx5_ifc_dest_format_flow_counter_list_auto_bits destination[]; 3935 }; 3936 3937 enum { 3938 MLX5_XRC_SRQC_STATE_GOOD = 0x0, 3939 MLX5_XRC_SRQC_STATE_ERROR = 0x1, 3940 }; 3941 3942 struct mlx5_ifc_xrc_srqc_bits { 3943 u8 state[0x4]; 3944 u8 log_xrc_srq_size[0x4]; 3945 u8 reserved_at_8[0x18]; 3946 3947 u8 wq_signature[0x1]; 3948 u8 cont_srq[0x1]; 3949 u8 reserved_at_22[0x1]; 3950 u8 rlky[0x1]; 3951 u8 basic_cyclic_rcv_wqe[0x1]; 3952 u8 log_rq_stride[0x3]; 3953 u8 xrcd[0x18]; 3954 3955 u8 page_offset[0x6]; 3956 u8 reserved_at_46[0x1]; 3957 u8 dbr_umem_valid[0x1]; 3958 u8 cqn[0x18]; 3959 3960 u8 reserved_at_60[0x20]; 3961 3962 u8 user_index_equal_xrc_srqn[0x1]; 3963 u8 reserved_at_81[0x1]; 3964 u8 log_page_size[0x6]; 3965 u8 user_index[0x18]; 3966 3967 u8 reserved_at_a0[0x20]; 3968 3969 u8 reserved_at_c0[0x8]; 3970 u8 pd[0x18]; 3971 3972 u8 lwm[0x10]; 3973 u8 wqe_cnt[0x10]; 3974 3975 u8 reserved_at_100[0x40]; 3976 3977 u8 db_record_addr_h[0x20]; 3978 3979 u8 db_record_addr_l[0x1e]; 3980 u8 reserved_at_17e[0x2]; 3981 3982 u8 reserved_at_180[0x80]; 3983 }; 3984 3985 struct mlx5_ifc_vnic_diagnostic_statistics_bits { 3986 u8 counter_error_queues[0x20]; 3987 3988 u8 total_error_queues[0x20]; 3989 3990 u8 send_queue_priority_update_flow[0x20]; 3991 3992 u8 reserved_at_60[0x20]; 3993 3994 u8 nic_receive_steering_discard[0x40]; 3995 3996 u8 receive_discard_vport_down[0x40]; 3997 3998 u8 transmit_discard_vport_down[0x40]; 3999 4000 u8 async_eq_overrun[0x20]; 4001 4002 u8 comp_eq_overrun[0x20]; 4003 4004 u8 reserved_at_180[0x20]; 4005 4006 u8 invalid_command[0x20]; 4007 4008 u8 quota_exceeded_command[0x20]; 4009 4010 u8 internal_rq_out_of_buffer[0x20]; 4011 4012 u8 cq_overrun[0x20]; 4013 4014 u8 eth_wqe_too_small[0x20]; 4015 4016 u8 reserved_at_220[0xc0]; 4017 4018 u8 generated_pkt_steering_fail[0x40]; 4019 4020 u8 handled_pkt_steering_fail[0x40]; 4021 4022 u8 reserved_at_360[0xc80]; 4023 }; 4024 4025 struct mlx5_ifc_traffic_counter_bits { 4026 u8 packets[0x40]; 4027 4028 u8 octets[0x40]; 4029 }; 4030 4031 struct mlx5_ifc_tisc_bits { 4032 u8 strict_lag_tx_port_affinity[0x1]; 4033 u8 tls_en[0x1]; 4034 u8 reserved_at_2[0x2]; 4035 u8 lag_tx_port_affinity[0x04]; 4036 4037 u8 reserved_at_8[0x4]; 4038 u8 prio[0x4]; 4039 u8 reserved_at_10[0x10]; 4040 4041 u8 reserved_at_20[0x100]; 4042 4043 u8 reserved_at_120[0x8]; 4044 u8 transport_domain[0x18]; 4045 4046 u8 reserved_at_140[0x8]; 4047 u8 underlay_qpn[0x18]; 4048 4049 u8 reserved_at_160[0x8]; 4050 u8 pd[0x18]; 4051 4052 u8 reserved_at_180[0x380]; 4053 }; 4054 4055 enum { 4056 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0, 4057 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1, 4058 }; 4059 4060 enum { 4061 MLX5_TIRC_PACKET_MERGE_MASK_IPV4_LRO = BIT(0), 4062 MLX5_TIRC_PACKET_MERGE_MASK_IPV6_LRO = BIT(1), 4063 }; 4064 4065 enum { 4066 MLX5_RX_HASH_FN_NONE = 0x0, 4067 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1, 4068 MLX5_RX_HASH_FN_TOEPLITZ = 0x2, 4069 }; 4070 4071 enum { 4072 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST = 0x1, 4073 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST = 0x2, 4074 }; 4075 4076 struct mlx5_ifc_tirc_bits { 4077 u8 reserved_at_0[0x20]; 4078 4079 u8 disp_type[0x4]; 4080 u8 tls_en[0x1]; 4081 u8 reserved_at_25[0x1b]; 4082 4083 u8 reserved_at_40[0x40]; 4084 4085 u8 reserved_at_80[0x4]; 4086 u8 lro_timeout_period_usecs[0x10]; 4087 u8 packet_merge_mask[0x4]; 4088 u8 lro_max_ip_payload_size[0x8]; 4089 4090 u8 reserved_at_a0[0x40]; 4091 4092 u8 reserved_at_e0[0x8]; 4093 u8 inline_rqn[0x18]; 4094 4095 u8 rx_hash_symmetric[0x1]; 4096 u8 reserved_at_101[0x1]; 4097 u8 tunneled_offload_en[0x1]; 4098 u8 reserved_at_103[0x5]; 4099 u8 indirect_table[0x18]; 4100 4101 u8 rx_hash_fn[0x4]; 4102 u8 reserved_at_124[0x2]; 4103 u8 self_lb_block[0x2]; 4104 u8 transport_domain[0x18]; 4105 4106 u8 rx_hash_toeplitz_key[10][0x20]; 4107 4108 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer; 4109 4110 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner; 4111 4112 u8 reserved_at_2c0[0x4c0]; 4113 }; 4114 4115 enum { 4116 MLX5_SRQC_STATE_GOOD = 0x0, 4117 MLX5_SRQC_STATE_ERROR = 0x1, 4118 }; 4119 4120 struct mlx5_ifc_srqc_bits { 4121 u8 state[0x4]; 4122 u8 log_srq_size[0x4]; 4123 u8 reserved_at_8[0x18]; 4124 4125 u8 wq_signature[0x1]; 4126 u8 cont_srq[0x1]; 4127 u8 reserved_at_22[0x1]; 4128 u8 rlky[0x1]; 4129 u8 reserved_at_24[0x1]; 4130 u8 log_rq_stride[0x3]; 4131 u8 xrcd[0x18]; 4132 4133 u8 page_offset[0x6]; 4134 u8 reserved_at_46[0x2]; 4135 u8 cqn[0x18]; 4136 4137 u8 reserved_at_60[0x20]; 4138 4139 u8 reserved_at_80[0x2]; 4140 u8 log_page_size[0x6]; 4141 u8 reserved_at_88[0x18]; 4142 4143 u8 reserved_at_a0[0x20]; 4144 4145 u8 reserved_at_c0[0x8]; 4146 u8 pd[0x18]; 4147 4148 u8 lwm[0x10]; 4149 u8 wqe_cnt[0x10]; 4150 4151 u8 reserved_at_100[0x40]; 4152 4153 u8 dbr_addr[0x40]; 4154 4155 u8 reserved_at_180[0x80]; 4156 }; 4157 4158 enum { 4159 MLX5_SQC_STATE_RST = 0x0, 4160 MLX5_SQC_STATE_RDY = 0x1, 4161 MLX5_SQC_STATE_ERR = 0x3, 4162 }; 4163 4164 struct mlx5_ifc_sqc_bits { 4165 u8 rlky[0x1]; 4166 u8 cd_master[0x1]; 4167 u8 fre[0x1]; 4168 u8 flush_in_error_en[0x1]; 4169 u8 allow_multi_pkt_send_wqe[0x1]; 4170 u8 min_wqe_inline_mode[0x3]; 4171 u8 state[0x4]; 4172 u8 reg_umr[0x1]; 4173 u8 allow_swp[0x1]; 4174 u8 hairpin[0x1]; 4175 u8 non_wire[0x1]; 4176 u8 reserved_at_10[0xa]; 4177 u8 ts_format[0x2]; 4178 u8 reserved_at_1c[0x4]; 4179 4180 u8 reserved_at_20[0x8]; 4181 u8 user_index[0x18]; 4182 4183 u8 reserved_at_40[0x8]; 4184 u8 cqn[0x18]; 4185 4186 u8 reserved_at_60[0x8]; 4187 u8 hairpin_peer_rq[0x18]; 4188 4189 u8 reserved_at_80[0x10]; 4190 u8 hairpin_peer_vhca[0x10]; 4191 4192 u8 reserved_at_a0[0x20]; 4193 4194 u8 reserved_at_c0[0x8]; 4195 u8 ts_cqe_to_dest_cqn[0x18]; 4196 4197 u8 reserved_at_e0[0x10]; 4198 u8 packet_pacing_rate_limit_index[0x10]; 4199 u8 tis_lst_sz[0x10]; 4200 u8 qos_queue_group_id[0x10]; 4201 4202 u8 reserved_at_120[0x40]; 4203 4204 u8 reserved_at_160[0x8]; 4205 u8 tis_num_0[0x18]; 4206 4207 struct mlx5_ifc_wq_bits wq; 4208 }; 4209 4210 enum { 4211 SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0, 4212 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1, 4213 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2, 4214 SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3, 4215 SCHEDULING_CONTEXT_ELEMENT_TYPE_QUEUE_GROUP = 0x4, 4216 SCHEDULING_CONTEXT_ELEMENT_TYPE_RATE_LIMIT = 0x5, 4217 }; 4218 4219 enum { 4220 ELEMENT_TYPE_CAP_MASK_TSAR = 1 << 0, 4221 ELEMENT_TYPE_CAP_MASK_VPORT = 1 << 1, 4222 ELEMENT_TYPE_CAP_MASK_VPORT_TC = 1 << 2, 4223 ELEMENT_TYPE_CAP_MASK_PARA_VPORT_TC = 1 << 3, 4224 ELEMENT_TYPE_CAP_MASK_QUEUE_GROUP = 1 << 4, 4225 ELEMENT_TYPE_CAP_MASK_RATE_LIMIT = 1 << 5, 4226 }; 4227 4228 enum { 4229 TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0, 4230 TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1, 4231 TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2, 4232 TSAR_ELEMENT_TSAR_TYPE_TC_ARB = 0x3, 4233 }; 4234 4235 enum { 4236 TSAR_TYPE_CAP_MASK_DWRR = 1 << 0, 4237 TSAR_TYPE_CAP_MASK_ROUND_ROBIN = 1 << 1, 4238 TSAR_TYPE_CAP_MASK_ETS = 1 << 2, 4239 TSAR_TYPE_CAP_MASK_TC_ARB = 1 << 3, 4240 }; 4241 4242 struct mlx5_ifc_tsar_element_bits { 4243 u8 traffic_class[0x4]; 4244 u8 reserved_at_4[0x4]; 4245 u8 tsar_type[0x8]; 4246 u8 reserved_at_10[0x10]; 4247 }; 4248 4249 struct mlx5_ifc_vport_element_bits { 4250 u8 reserved_at_0[0x4]; 4251 u8 eswitch_owner_vhca_id_valid[0x1]; 4252 u8 eswitch_owner_vhca_id[0xb]; 4253 u8 vport_number[0x10]; 4254 }; 4255 4256 struct mlx5_ifc_vport_tc_element_bits { 4257 u8 traffic_class[0x4]; 4258 u8 eswitch_owner_vhca_id_valid[0x1]; 4259 u8 eswitch_owner_vhca_id[0xb]; 4260 u8 vport_number[0x10]; 4261 }; 4262 4263 union mlx5_ifc_element_attributes_bits { 4264 struct mlx5_ifc_tsar_element_bits tsar; 4265 struct mlx5_ifc_vport_element_bits vport; 4266 struct mlx5_ifc_vport_tc_element_bits vport_tc; 4267 u8 reserved_at_0[0x20]; 4268 }; 4269 4270 struct mlx5_ifc_scheduling_context_bits { 4271 u8 element_type[0x8]; 4272 u8 reserved_at_8[0x18]; 4273 4274 union mlx5_ifc_element_attributes_bits element_attributes; 4275 4276 u8 parent_element_id[0x20]; 4277 4278 u8 reserved_at_60[0x40]; 4279 4280 u8 bw_share[0x20]; 4281 4282 u8 max_average_bw[0x20]; 4283 4284 u8 max_bw_obj_id[0x20]; 4285 4286 u8 reserved_at_100[0x100]; 4287 }; 4288 4289 struct mlx5_ifc_rqtc_bits { 4290 u8 reserved_at_0[0xa0]; 4291 4292 u8 reserved_at_a0[0x5]; 4293 u8 list_q_type[0x3]; 4294 u8 reserved_at_a8[0x8]; 4295 u8 rqt_max_size[0x10]; 4296 4297 u8 rq_vhca_id_format[0x1]; 4298 u8 reserved_at_c1[0xf]; 4299 u8 rqt_actual_size[0x10]; 4300 4301 u8 reserved_at_e0[0x6a0]; 4302 4303 union { 4304 DECLARE_FLEX_ARRAY(struct mlx5_ifc_rq_num_bits, rq_num); 4305 DECLARE_FLEX_ARRAY(struct mlx5_ifc_rq_vhca_bits, rq_vhca); 4306 }; 4307 }; 4308 4309 enum { 4310 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0, 4311 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1, 4312 }; 4313 4314 enum { 4315 MLX5_RQC_STATE_RST = 0x0, 4316 MLX5_RQC_STATE_RDY = 0x1, 4317 MLX5_RQC_STATE_ERR = 0x3, 4318 }; 4319 4320 enum { 4321 MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_BYTE = 0x0, 4322 MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_STRIDE = 0x1, 4323 MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_PAGE = 0x2, 4324 }; 4325 4326 enum { 4327 MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_NO_MATCH = 0x0, 4328 MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_EXTENDED = 0x1, 4329 MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_FIVE_TUPLE = 0x2, 4330 }; 4331 4332 struct mlx5_ifc_rqc_bits { 4333 u8 rlky[0x1]; 4334 u8 delay_drop_en[0x1]; 4335 u8 scatter_fcs[0x1]; 4336 u8 vsd[0x1]; 4337 u8 mem_rq_type[0x4]; 4338 u8 state[0x4]; 4339 u8 reserved_at_c[0x1]; 4340 u8 flush_in_error_en[0x1]; 4341 u8 hairpin[0x1]; 4342 u8 reserved_at_f[0xb]; 4343 u8 ts_format[0x2]; 4344 u8 reserved_at_1c[0x4]; 4345 4346 u8 reserved_at_20[0x8]; 4347 u8 user_index[0x18]; 4348 4349 u8 reserved_at_40[0x8]; 4350 u8 cqn[0x18]; 4351 4352 u8 counter_set_id[0x8]; 4353 u8 reserved_at_68[0x18]; 4354 4355 u8 reserved_at_80[0x8]; 4356 u8 rmpn[0x18]; 4357 4358 u8 reserved_at_a0[0x8]; 4359 u8 hairpin_peer_sq[0x18]; 4360 4361 u8 reserved_at_c0[0x10]; 4362 u8 hairpin_peer_vhca[0x10]; 4363 4364 u8 reserved_at_e0[0x46]; 4365 u8 shampo_no_match_alignment_granularity[0x2]; 4366 u8 reserved_at_128[0x6]; 4367 u8 shampo_match_criteria_type[0x2]; 4368 u8 reservation_timeout[0x10]; 4369 4370 u8 reserved_at_140[0x40]; 4371 4372 struct mlx5_ifc_wq_bits wq; 4373 }; 4374 4375 enum { 4376 MLX5_RMPC_STATE_RDY = 0x1, 4377 MLX5_RMPC_STATE_ERR = 0x3, 4378 }; 4379 4380 struct mlx5_ifc_rmpc_bits { 4381 u8 reserved_at_0[0x8]; 4382 u8 state[0x4]; 4383 u8 reserved_at_c[0x14]; 4384 4385 u8 basic_cyclic_rcv_wqe[0x1]; 4386 u8 reserved_at_21[0x1f]; 4387 4388 u8 reserved_at_40[0x140]; 4389 4390 struct mlx5_ifc_wq_bits wq; 4391 }; 4392 4393 enum { 4394 VHCA_ID_TYPE_HW = 0, 4395 VHCA_ID_TYPE_SW = 1, 4396 }; 4397 4398 struct mlx5_ifc_nic_vport_context_bits { 4399 u8 reserved_at_0[0x5]; 4400 u8 min_wqe_inline_mode[0x3]; 4401 u8 reserved_at_8[0x15]; 4402 u8 disable_mc_local_lb[0x1]; 4403 u8 disable_uc_local_lb[0x1]; 4404 u8 roce_en[0x1]; 4405 4406 u8 arm_change_event[0x1]; 4407 u8 reserved_at_21[0x1a]; 4408 u8 event_on_mtu[0x1]; 4409 u8 event_on_promisc_change[0x1]; 4410 u8 event_on_vlan_change[0x1]; 4411 u8 event_on_mc_address_change[0x1]; 4412 u8 event_on_uc_address_change[0x1]; 4413 4414 u8 vhca_id_type[0x1]; 4415 u8 reserved_at_41[0xb]; 4416 u8 affiliation_criteria[0x4]; 4417 u8 affiliated_vhca_id[0x10]; 4418 4419 u8 reserved_at_60[0xa0]; 4420 4421 u8 reserved_at_100[0x1]; 4422 u8 sd_group[0x3]; 4423 u8 reserved_at_104[0x1c]; 4424 4425 u8 reserved_at_120[0x10]; 4426 u8 mtu[0x10]; 4427 4428 u8 system_image_guid[0x40]; 4429 u8 port_guid[0x40]; 4430 u8 node_guid[0x40]; 4431 4432 u8 reserved_at_200[0x140]; 4433 u8 qkey_violation_counter[0x10]; 4434 u8 reserved_at_350[0x430]; 4435 4436 u8 promisc_uc[0x1]; 4437 u8 promisc_mc[0x1]; 4438 u8 promisc_all[0x1]; 4439 u8 reserved_at_783[0x2]; 4440 u8 allowed_list_type[0x3]; 4441 u8 reserved_at_788[0xc]; 4442 u8 allowed_list_size[0xc]; 4443 4444 struct mlx5_ifc_mac_address_layout_bits permanent_address; 4445 4446 u8 reserved_at_7e0[0x20]; 4447 4448 u8 current_uc_mac_address[][0x40]; 4449 }; 4450 4451 enum { 4452 MLX5_MKC_ACCESS_MODE_PA = 0x0, 4453 MLX5_MKC_ACCESS_MODE_MTT = 0x1, 4454 MLX5_MKC_ACCESS_MODE_KLMS = 0x2, 4455 MLX5_MKC_ACCESS_MODE_KSM = 0x3, 4456 MLX5_MKC_ACCESS_MODE_SW_ICM = 0x4, 4457 MLX5_MKC_ACCESS_MODE_MEMIC = 0x5, 4458 MLX5_MKC_ACCESS_MODE_CROSSING = 0x6, 4459 }; 4460 4461 enum { 4462 MLX5_MKC_PCIE_TPH_NO_STEERING_TAG_INDEX = 0, 4463 }; 4464 4465 struct mlx5_ifc_mkc_bits { 4466 u8 reserved_at_0[0x1]; 4467 u8 free[0x1]; 4468 u8 reserved_at_2[0x1]; 4469 u8 access_mode_4_2[0x3]; 4470 u8 reserved_at_6[0x7]; 4471 u8 relaxed_ordering_write[0x1]; 4472 u8 reserved_at_e[0x1]; 4473 u8 small_fence_on_rdma_read_response[0x1]; 4474 u8 umr_en[0x1]; 4475 u8 a[0x1]; 4476 u8 rw[0x1]; 4477 u8 rr[0x1]; 4478 u8 lw[0x1]; 4479 u8 lr[0x1]; 4480 u8 access_mode_1_0[0x2]; 4481 u8 reserved_at_18[0x2]; 4482 u8 ma_translation_mode[0x2]; 4483 u8 reserved_at_1c[0x4]; 4484 4485 u8 qpn[0x18]; 4486 u8 mkey_7_0[0x8]; 4487 4488 u8 reserved_at_40[0x20]; 4489 4490 u8 length64[0x1]; 4491 u8 bsf_en[0x1]; 4492 u8 sync_umr[0x1]; 4493 u8 reserved_at_63[0x2]; 4494 u8 expected_sigerr_count[0x1]; 4495 u8 reserved_at_66[0x1]; 4496 u8 en_rinval[0x1]; 4497 u8 pd[0x18]; 4498 4499 u8 start_addr[0x40]; 4500 4501 u8 len[0x40]; 4502 4503 u8 bsf_octword_size[0x20]; 4504 4505 u8 reserved_at_120[0x60]; 4506 4507 u8 crossing_target_vhca_id[0x10]; 4508 u8 reserved_at_190[0x10]; 4509 4510 u8 translations_octword_size[0x20]; 4511 4512 u8 reserved_at_1c0[0x19]; 4513 u8 relaxed_ordering_read[0x1]; 4514 u8 log_page_size[0x6]; 4515 4516 u8 reserved_at_1e0[0x5]; 4517 u8 pcie_tph_en[0x1]; 4518 u8 pcie_tph_ph[0x2]; 4519 u8 pcie_tph_steering_tag_index[0x8]; 4520 u8 reserved_at_1f0[0x10]; 4521 }; 4522 4523 struct mlx5_ifc_pkey_bits { 4524 u8 reserved_at_0[0x10]; 4525 u8 pkey[0x10]; 4526 }; 4527 4528 struct mlx5_ifc_array128_auto_bits { 4529 u8 array128_auto[16][0x8]; 4530 }; 4531 4532 struct mlx5_ifc_hca_vport_context_bits { 4533 u8 field_select[0x20]; 4534 4535 u8 reserved_at_20[0xe0]; 4536 4537 u8 sm_virt_aware[0x1]; 4538 u8 has_smi[0x1]; 4539 u8 has_raw[0x1]; 4540 u8 grh_required[0x1]; 4541 u8 reserved_at_104[0x4]; 4542 u8 num_port_plane[0x8]; 4543 u8 port_physical_state[0x4]; 4544 u8 vport_state_policy[0x4]; 4545 u8 port_state[0x4]; 4546 u8 vport_state[0x4]; 4547 4548 u8 reserved_at_120[0x20]; 4549 4550 u8 system_image_guid[0x40]; 4551 4552 u8 port_guid[0x40]; 4553 4554 u8 node_guid[0x40]; 4555 4556 u8 cap_mask1[0x20]; 4557 4558 u8 cap_mask1_field_select[0x20]; 4559 4560 u8 cap_mask2[0x20]; 4561 4562 u8 cap_mask2_field_select[0x20]; 4563 4564 u8 reserved_at_280[0x80]; 4565 4566 u8 lid[0x10]; 4567 u8 reserved_at_310[0x4]; 4568 u8 init_type_reply[0x4]; 4569 u8 lmc[0x3]; 4570 u8 subnet_timeout[0x5]; 4571 4572 u8 sm_lid[0x10]; 4573 u8 sm_sl[0x4]; 4574 u8 reserved_at_334[0xc]; 4575 4576 u8 qkey_violation_counter[0x10]; 4577 u8 pkey_violation_counter[0x10]; 4578 4579 u8 reserved_at_360[0xca0]; 4580 }; 4581 4582 struct mlx5_ifc_esw_vport_context_bits { 4583 u8 fdb_to_vport_reg_c[0x1]; 4584 u8 reserved_at_1[0x2]; 4585 u8 vport_svlan_strip[0x1]; 4586 u8 vport_cvlan_strip[0x1]; 4587 u8 vport_svlan_insert[0x1]; 4588 u8 vport_cvlan_insert[0x2]; 4589 u8 fdb_to_vport_reg_c_id[0x8]; 4590 u8 reserved_at_10[0x10]; 4591 4592 u8 reserved_at_20[0x20]; 4593 4594 u8 svlan_cfi[0x1]; 4595 u8 svlan_pcp[0x3]; 4596 u8 svlan_id[0xc]; 4597 u8 cvlan_cfi[0x1]; 4598 u8 cvlan_pcp[0x3]; 4599 u8 cvlan_id[0xc]; 4600 4601 u8 reserved_at_60[0x720]; 4602 4603 u8 sw_steering_vport_icm_address_rx[0x40]; 4604 4605 u8 sw_steering_vport_icm_address_tx[0x40]; 4606 }; 4607 4608 enum { 4609 MLX5_EQC_STATUS_OK = 0x0, 4610 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa, 4611 }; 4612 4613 enum { 4614 MLX5_EQC_ST_ARMED = 0x9, 4615 MLX5_EQC_ST_FIRED = 0xa, 4616 }; 4617 4618 struct mlx5_ifc_eqc_bits { 4619 u8 status[0x4]; 4620 u8 reserved_at_4[0x9]; 4621 u8 ec[0x1]; 4622 u8 oi[0x1]; 4623 u8 reserved_at_f[0x5]; 4624 u8 st[0x4]; 4625 u8 reserved_at_18[0x8]; 4626 4627 u8 reserved_at_20[0x20]; 4628 4629 u8 reserved_at_40[0x14]; 4630 u8 page_offset[0x6]; 4631 u8 reserved_at_5a[0x6]; 4632 4633 u8 reserved_at_60[0x3]; 4634 u8 log_eq_size[0x5]; 4635 u8 uar_page[0x18]; 4636 4637 u8 reserved_at_80[0x20]; 4638 4639 u8 reserved_at_a0[0x14]; 4640 u8 intr[0xc]; 4641 4642 u8 reserved_at_c0[0x3]; 4643 u8 log_page_size[0x5]; 4644 u8 reserved_at_c8[0x18]; 4645 4646 u8 reserved_at_e0[0x60]; 4647 4648 u8 reserved_at_140[0x8]; 4649 u8 consumer_counter[0x18]; 4650 4651 u8 reserved_at_160[0x8]; 4652 u8 producer_counter[0x18]; 4653 4654 u8 reserved_at_180[0x80]; 4655 }; 4656 4657 enum { 4658 MLX5_DCTC_STATE_ACTIVE = 0x0, 4659 MLX5_DCTC_STATE_DRAINING = 0x1, 4660 MLX5_DCTC_STATE_DRAINED = 0x2, 4661 }; 4662 4663 enum { 4664 MLX5_DCTC_CS_RES_DISABLE = 0x0, 4665 MLX5_DCTC_CS_RES_NA = 0x1, 4666 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2, 4667 }; 4668 4669 enum { 4670 MLX5_DCTC_MTU_256_BYTES = 0x1, 4671 MLX5_DCTC_MTU_512_BYTES = 0x2, 4672 MLX5_DCTC_MTU_1K_BYTES = 0x3, 4673 MLX5_DCTC_MTU_2K_BYTES = 0x4, 4674 MLX5_DCTC_MTU_4K_BYTES = 0x5, 4675 }; 4676 4677 struct mlx5_ifc_dctc_bits { 4678 u8 reserved_at_0[0x4]; 4679 u8 state[0x4]; 4680 u8 reserved_at_8[0x18]; 4681 4682 u8 reserved_at_20[0x7]; 4683 u8 dp_ordering_force[0x1]; 4684 u8 user_index[0x18]; 4685 4686 u8 reserved_at_40[0x8]; 4687 u8 cqn[0x18]; 4688 4689 u8 counter_set_id[0x8]; 4690 u8 atomic_mode[0x4]; 4691 u8 rre[0x1]; 4692 u8 rwe[0x1]; 4693 u8 rae[0x1]; 4694 u8 atomic_like_write_en[0x1]; 4695 u8 latency_sensitive[0x1]; 4696 u8 rlky[0x1]; 4697 u8 free_ar[0x1]; 4698 u8 reserved_at_73[0x1]; 4699 u8 dp_ordering_1[0x1]; 4700 u8 reserved_at_75[0xb]; 4701 4702 u8 reserved_at_80[0x8]; 4703 u8 cs_res[0x8]; 4704 u8 reserved_at_90[0x3]; 4705 u8 min_rnr_nak[0x5]; 4706 u8 reserved_at_98[0x8]; 4707 4708 u8 reserved_at_a0[0x8]; 4709 u8 srqn_xrqn[0x18]; 4710 4711 u8 reserved_at_c0[0x8]; 4712 u8 pd[0x18]; 4713 4714 u8 tclass[0x8]; 4715 u8 reserved_at_e8[0x4]; 4716 u8 flow_label[0x14]; 4717 4718 u8 dc_access_key[0x40]; 4719 4720 u8 reserved_at_140[0x5]; 4721 u8 mtu[0x3]; 4722 u8 port[0x8]; 4723 u8 pkey_index[0x10]; 4724 4725 u8 reserved_at_160[0x8]; 4726 u8 my_addr_index[0x8]; 4727 u8 reserved_at_170[0x8]; 4728 u8 hop_limit[0x8]; 4729 4730 u8 dc_access_key_violation_count[0x20]; 4731 4732 u8 reserved_at_1a0[0x14]; 4733 u8 dei_cfi[0x1]; 4734 u8 eth_prio[0x3]; 4735 u8 ecn[0x2]; 4736 u8 dscp[0x6]; 4737 4738 u8 reserved_at_1c0[0x20]; 4739 u8 ece[0x20]; 4740 }; 4741 4742 enum { 4743 MLX5_CQC_STATUS_OK = 0x0, 4744 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9, 4745 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa, 4746 }; 4747 4748 enum { 4749 MLX5_CQC_CQE_SZ_64_BYTES = 0x0, 4750 MLX5_CQC_CQE_SZ_128_BYTES = 0x1, 4751 }; 4752 4753 enum { 4754 MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED = 0x6, 4755 MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED = 0x9, 4756 MLX5_CQC_ST_FIRED = 0xa, 4757 }; 4758 4759 enum mlx5_cq_period_mode { 4760 MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0, 4761 MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1, 4762 MLX5_CQ_PERIOD_NUM_MODES, 4763 }; 4764 4765 struct mlx5_ifc_cqc_bits { 4766 u8 status[0x4]; 4767 u8 reserved_at_4[0x2]; 4768 u8 dbr_umem_valid[0x1]; 4769 u8 apu_cq[0x1]; 4770 u8 cqe_sz[0x3]; 4771 u8 cc[0x1]; 4772 u8 reserved_at_c[0x1]; 4773 u8 scqe_break_moderation_en[0x1]; 4774 u8 oi[0x1]; 4775 u8 cq_period_mode[0x2]; 4776 u8 cqe_comp_en[0x1]; 4777 u8 mini_cqe_res_format[0x2]; 4778 u8 st[0x4]; 4779 u8 reserved_at_18[0x6]; 4780 u8 cqe_compression_layout[0x2]; 4781 4782 u8 reserved_at_20[0x20]; 4783 4784 u8 reserved_at_40[0x14]; 4785 u8 page_offset[0x6]; 4786 u8 reserved_at_5a[0x6]; 4787 4788 u8 reserved_at_60[0x3]; 4789 u8 log_cq_size[0x5]; 4790 u8 uar_page[0x18]; 4791 4792 u8 reserved_at_80[0x4]; 4793 u8 cq_period[0xc]; 4794 u8 cq_max_count[0x10]; 4795 4796 u8 c_eqn_or_apu_element[0x20]; 4797 4798 u8 reserved_at_c0[0x3]; 4799 u8 log_page_size[0x5]; 4800 u8 reserved_at_c8[0x18]; 4801 4802 u8 reserved_at_e0[0x20]; 4803 4804 u8 reserved_at_100[0x8]; 4805 u8 last_notified_index[0x18]; 4806 4807 u8 reserved_at_120[0x8]; 4808 u8 last_solicit_index[0x18]; 4809 4810 u8 reserved_at_140[0x8]; 4811 u8 consumer_counter[0x18]; 4812 4813 u8 reserved_at_160[0x8]; 4814 u8 producer_counter[0x18]; 4815 4816 u8 reserved_at_180[0x40]; 4817 4818 u8 dbr_addr[0x40]; 4819 }; 4820 4821 union mlx5_ifc_cong_control_roce_ecn_auto_bits { 4822 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp; 4823 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp; 4824 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np; 4825 struct mlx5_ifc_cong_control_r_roce_general_bits cong_control_r_roce_general; 4826 u8 reserved_at_0[0x800]; 4827 }; 4828 4829 struct mlx5_ifc_query_adapter_param_block_bits { 4830 u8 reserved_at_0[0xc0]; 4831 4832 u8 reserved_at_c0[0x8]; 4833 u8 ieee_vendor_id[0x18]; 4834 4835 u8 reserved_at_e0[0x10]; 4836 u8 vsd_vendor_id[0x10]; 4837 4838 u8 vsd[208][0x8]; 4839 4840 u8 vsd_contd_psid[16][0x8]; 4841 }; 4842 4843 enum { 4844 MLX5_XRQC_STATE_GOOD = 0x0, 4845 MLX5_XRQC_STATE_ERROR = 0x1, 4846 }; 4847 4848 enum { 4849 MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0, 4850 MLX5_XRQC_TOPOLOGY_TAG_MATCHING = 0x1, 4851 }; 4852 4853 enum { 4854 MLX5_XRQC_OFFLOAD_RNDV = 0x1, 4855 }; 4856 4857 struct mlx5_ifc_tag_matching_topology_context_bits { 4858 u8 log_matching_list_sz[0x4]; 4859 u8 reserved_at_4[0xc]; 4860 u8 append_next_index[0x10]; 4861 4862 u8 sw_phase_cnt[0x10]; 4863 u8 hw_phase_cnt[0x10]; 4864 4865 u8 reserved_at_40[0x40]; 4866 }; 4867 4868 struct mlx5_ifc_xrqc_bits { 4869 u8 state[0x4]; 4870 u8 rlkey[0x1]; 4871 u8 reserved_at_5[0xf]; 4872 u8 topology[0x4]; 4873 u8 reserved_at_18[0x4]; 4874 u8 offload[0x4]; 4875 4876 u8 reserved_at_20[0x8]; 4877 u8 user_index[0x18]; 4878 4879 u8 reserved_at_40[0x8]; 4880 u8 cqn[0x18]; 4881 4882 u8 reserved_at_60[0xa0]; 4883 4884 struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context; 4885 4886 u8 reserved_at_180[0x280]; 4887 4888 struct mlx5_ifc_wq_bits wq; 4889 }; 4890 4891 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits { 4892 struct mlx5_ifc_modify_field_select_bits modify_field_select; 4893 struct mlx5_ifc_resize_field_select_bits resize_field_select; 4894 u8 reserved_at_0[0x20]; 4895 }; 4896 4897 union mlx5_ifc_field_select_802_1_r_roce_auto_bits { 4898 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp; 4899 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp; 4900 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np; 4901 u8 reserved_at_0[0x20]; 4902 }; 4903 4904 struct mlx5_ifc_rs_histogram_cntrs_bits { 4905 u8 hist[16][0x40]; 4906 u8 reserved_at_400[0x2c0]; 4907 }; 4908 4909 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits { 4910 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 4911 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 4912 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 4913 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 4914 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 4915 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 4916 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout; 4917 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout; 4918 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 4919 struct mlx5_ifc_ib_ext_port_cntrs_grp_data_layout_bits ib_ext_port_cntrs_grp_data_layout; 4920 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 4921 struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs; 4922 struct mlx5_ifc_phys_layer_recovery_cntrs_bits phys_layer_recovery_cntrs; 4923 struct mlx5_ifc_rs_histogram_cntrs_bits rs_histogram_cntrs; 4924 u8 reserved_at_0[0x7c0]; 4925 }; 4926 4927 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits { 4928 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout; 4929 u8 reserved_at_0[0x7c0]; 4930 }; 4931 4932 union mlx5_ifc_event_auto_bits { 4933 struct mlx5_ifc_comp_event_bits comp_event; 4934 struct mlx5_ifc_dct_events_bits dct_events; 4935 struct mlx5_ifc_qp_events_bits qp_events; 4936 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event; 4937 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event; 4938 struct mlx5_ifc_cq_error_bits cq_error; 4939 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged; 4940 struct mlx5_ifc_port_state_change_event_bits port_state_change_event; 4941 struct mlx5_ifc_gpio_event_bits gpio_event; 4942 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event; 4943 struct mlx5_ifc_stall_vl_event_bits stall_vl_event; 4944 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event; 4945 u8 reserved_at_0[0xe0]; 4946 }; 4947 4948 struct mlx5_ifc_health_buffer_bits { 4949 u8 reserved_at_0[0x100]; 4950 4951 u8 assert_existptr[0x20]; 4952 4953 u8 assert_callra[0x20]; 4954 4955 u8 reserved_at_140[0x20]; 4956 4957 u8 time[0x20]; 4958 4959 u8 fw_version[0x20]; 4960 4961 u8 hw_id[0x20]; 4962 4963 u8 rfr[0x1]; 4964 u8 reserved_at_1c1[0x3]; 4965 u8 valid[0x1]; 4966 u8 severity[0x3]; 4967 u8 reserved_at_1c8[0x18]; 4968 4969 u8 irisc_index[0x8]; 4970 u8 synd[0x8]; 4971 u8 ext_synd[0x10]; 4972 }; 4973 4974 struct mlx5_ifc_register_loopback_control_bits { 4975 u8 no_lb[0x1]; 4976 u8 reserved_at_1[0x7]; 4977 u8 port[0x8]; 4978 u8 reserved_at_10[0x10]; 4979 4980 u8 reserved_at_20[0x60]; 4981 }; 4982 4983 enum { 4984 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0, 4985 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1, 4986 }; 4987 4988 struct mlx5_ifc_teardown_hca_out_bits { 4989 u8 status[0x8]; 4990 u8 reserved_at_8[0x18]; 4991 4992 u8 syndrome[0x20]; 4993 4994 u8 reserved_at_40[0x3f]; 4995 4996 u8 state[0x1]; 4997 }; 4998 4999 enum { 5000 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0, 5001 MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE = 0x1, 5002 MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN = 0x2, 5003 }; 5004 5005 struct mlx5_ifc_teardown_hca_in_bits { 5006 u8 opcode[0x10]; 5007 u8 reserved_at_10[0x10]; 5008 5009 u8 reserved_at_20[0x10]; 5010 u8 op_mod[0x10]; 5011 5012 u8 reserved_at_40[0x10]; 5013 u8 profile[0x10]; 5014 5015 u8 reserved_at_60[0x20]; 5016 }; 5017 5018 struct mlx5_ifc_sqerr2rts_qp_out_bits { 5019 u8 status[0x8]; 5020 u8 reserved_at_8[0x18]; 5021 5022 u8 syndrome[0x20]; 5023 5024 u8 reserved_at_40[0x40]; 5025 }; 5026 5027 struct mlx5_ifc_sqerr2rts_qp_in_bits { 5028 u8 opcode[0x10]; 5029 u8 uid[0x10]; 5030 5031 u8 reserved_at_20[0x10]; 5032 u8 op_mod[0x10]; 5033 5034 u8 reserved_at_40[0x8]; 5035 u8 qpn[0x18]; 5036 5037 u8 reserved_at_60[0x20]; 5038 5039 u8 opt_param_mask[0x20]; 5040 5041 u8 reserved_at_a0[0x20]; 5042 5043 struct mlx5_ifc_qpc_bits qpc; 5044 5045 u8 reserved_at_800[0x80]; 5046 }; 5047 5048 struct mlx5_ifc_sqd2rts_qp_out_bits { 5049 u8 status[0x8]; 5050 u8 reserved_at_8[0x18]; 5051 5052 u8 syndrome[0x20]; 5053 5054 u8 reserved_at_40[0x40]; 5055 }; 5056 5057 struct mlx5_ifc_sqd2rts_qp_in_bits { 5058 u8 opcode[0x10]; 5059 u8 uid[0x10]; 5060 5061 u8 reserved_at_20[0x10]; 5062 u8 op_mod[0x10]; 5063 5064 u8 reserved_at_40[0x8]; 5065 u8 qpn[0x18]; 5066 5067 u8 reserved_at_60[0x20]; 5068 5069 u8 opt_param_mask[0x20]; 5070 5071 u8 reserved_at_a0[0x20]; 5072 5073 struct mlx5_ifc_qpc_bits qpc; 5074 5075 u8 reserved_at_800[0x80]; 5076 }; 5077 5078 struct mlx5_ifc_set_roce_address_out_bits { 5079 u8 status[0x8]; 5080 u8 reserved_at_8[0x18]; 5081 5082 u8 syndrome[0x20]; 5083 5084 u8 reserved_at_40[0x40]; 5085 }; 5086 5087 struct mlx5_ifc_set_roce_address_in_bits { 5088 u8 opcode[0x10]; 5089 u8 reserved_at_10[0x10]; 5090 5091 u8 reserved_at_20[0x10]; 5092 u8 op_mod[0x10]; 5093 5094 u8 roce_address_index[0x10]; 5095 u8 reserved_at_50[0xc]; 5096 u8 vhca_port_num[0x4]; 5097 5098 u8 reserved_at_60[0x20]; 5099 5100 struct mlx5_ifc_roce_addr_layout_bits roce_address; 5101 }; 5102 5103 struct mlx5_ifc_set_mad_demux_out_bits { 5104 u8 status[0x8]; 5105 u8 reserved_at_8[0x18]; 5106 5107 u8 syndrome[0x20]; 5108 5109 u8 reserved_at_40[0x40]; 5110 }; 5111 5112 enum { 5113 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0, 5114 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2, 5115 }; 5116 5117 struct mlx5_ifc_set_mad_demux_in_bits { 5118 u8 opcode[0x10]; 5119 u8 reserved_at_10[0x10]; 5120 5121 u8 reserved_at_20[0x10]; 5122 u8 op_mod[0x10]; 5123 5124 u8 reserved_at_40[0x20]; 5125 5126 u8 reserved_at_60[0x6]; 5127 u8 demux_mode[0x2]; 5128 u8 reserved_at_68[0x18]; 5129 }; 5130 5131 struct mlx5_ifc_set_l2_table_entry_out_bits { 5132 u8 status[0x8]; 5133 u8 reserved_at_8[0x18]; 5134 5135 u8 syndrome[0x20]; 5136 5137 u8 reserved_at_40[0x40]; 5138 }; 5139 5140 struct mlx5_ifc_set_l2_table_entry_in_bits { 5141 u8 opcode[0x10]; 5142 u8 reserved_at_10[0x10]; 5143 5144 u8 reserved_at_20[0x10]; 5145 u8 op_mod[0x10]; 5146 5147 u8 reserved_at_40[0x60]; 5148 5149 u8 reserved_at_a0[0x8]; 5150 u8 table_index[0x18]; 5151 5152 u8 reserved_at_c0[0x20]; 5153 5154 u8 reserved_at_e0[0x10]; 5155 u8 silent_mode_valid[0x1]; 5156 u8 silent_mode[0x1]; 5157 u8 reserved_at_f2[0x1]; 5158 u8 vlan_valid[0x1]; 5159 u8 vlan[0xc]; 5160 5161 struct mlx5_ifc_mac_address_layout_bits mac_address; 5162 5163 u8 reserved_at_140[0xc0]; 5164 }; 5165 5166 struct mlx5_ifc_set_issi_out_bits { 5167 u8 status[0x8]; 5168 u8 reserved_at_8[0x18]; 5169 5170 u8 syndrome[0x20]; 5171 5172 u8 reserved_at_40[0x40]; 5173 }; 5174 5175 struct mlx5_ifc_set_issi_in_bits { 5176 u8 opcode[0x10]; 5177 u8 reserved_at_10[0x10]; 5178 5179 u8 reserved_at_20[0x10]; 5180 u8 op_mod[0x10]; 5181 5182 u8 reserved_at_40[0x10]; 5183 u8 current_issi[0x10]; 5184 5185 u8 reserved_at_60[0x20]; 5186 }; 5187 5188 struct mlx5_ifc_set_hca_cap_out_bits { 5189 u8 status[0x8]; 5190 u8 reserved_at_8[0x18]; 5191 5192 u8 syndrome[0x20]; 5193 5194 u8 reserved_at_40[0x40]; 5195 }; 5196 5197 struct mlx5_ifc_set_hca_cap_in_bits { 5198 u8 opcode[0x10]; 5199 u8 reserved_at_10[0x10]; 5200 5201 u8 reserved_at_20[0x10]; 5202 u8 op_mod[0x10]; 5203 5204 u8 other_function[0x1]; 5205 u8 ec_vf_function[0x1]; 5206 u8 reserved_at_42[0x1]; 5207 u8 function_id_type[0x1]; 5208 u8 reserved_at_44[0xc]; 5209 u8 function_id[0x10]; 5210 5211 u8 reserved_at_60[0x20]; 5212 5213 union mlx5_ifc_hca_cap_union_bits capability; 5214 }; 5215 5216 enum { 5217 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0, 5218 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1, 5219 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2, 5220 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3, 5221 MLX5_SET_FTE_MODIFY_ENABLE_MASK_IPSEC_OBJ_ID = 0x4 5222 }; 5223 5224 struct mlx5_ifc_set_fte_out_bits { 5225 u8 status[0x8]; 5226 u8 reserved_at_8[0x18]; 5227 5228 u8 syndrome[0x20]; 5229 5230 u8 reserved_at_40[0x40]; 5231 }; 5232 5233 struct mlx5_ifc_set_fte_in_bits { 5234 u8 opcode[0x10]; 5235 u8 reserved_at_10[0x10]; 5236 5237 u8 reserved_at_20[0x10]; 5238 u8 op_mod[0x10]; 5239 5240 u8 other_vport[0x1]; 5241 u8 reserved_at_41[0xf]; 5242 u8 vport_number[0x10]; 5243 5244 u8 reserved_at_60[0x20]; 5245 5246 u8 table_type[0x8]; 5247 u8 reserved_at_88[0x18]; 5248 5249 u8 reserved_at_a0[0x8]; 5250 u8 table_id[0x18]; 5251 5252 u8 ignore_flow_level[0x1]; 5253 u8 reserved_at_c1[0x17]; 5254 u8 modify_enable_mask[0x8]; 5255 5256 u8 reserved_at_e0[0x20]; 5257 5258 u8 flow_index[0x20]; 5259 5260 u8 reserved_at_120[0xe0]; 5261 5262 struct mlx5_ifc_flow_context_bits flow_context; 5263 }; 5264 5265 struct mlx5_ifc_dest_format_bits { 5266 u8 destination_type[0x8]; 5267 u8 destination_id[0x18]; 5268 5269 u8 destination_eswitch_owner_vhca_id_valid[0x1]; 5270 u8 packet_reformat[0x1]; 5271 u8 reserved_at_22[0xe]; 5272 u8 destination_eswitch_owner_vhca_id[0x10]; 5273 }; 5274 5275 struct mlx5_ifc_rts2rts_qp_out_bits { 5276 u8 status[0x8]; 5277 u8 reserved_at_8[0x18]; 5278 5279 u8 syndrome[0x20]; 5280 5281 u8 reserved_at_40[0x20]; 5282 u8 ece[0x20]; 5283 }; 5284 5285 struct mlx5_ifc_rts2rts_qp_in_bits { 5286 u8 opcode[0x10]; 5287 u8 uid[0x10]; 5288 5289 u8 reserved_at_20[0x10]; 5290 u8 op_mod[0x10]; 5291 5292 u8 reserved_at_40[0x8]; 5293 u8 qpn[0x18]; 5294 5295 u8 reserved_at_60[0x20]; 5296 5297 u8 opt_param_mask[0x20]; 5298 5299 u8 ece[0x20]; 5300 5301 struct mlx5_ifc_qpc_bits qpc; 5302 5303 u8 reserved_at_800[0x80]; 5304 }; 5305 5306 struct mlx5_ifc_rtr2rts_qp_out_bits { 5307 u8 status[0x8]; 5308 u8 reserved_at_8[0x18]; 5309 5310 u8 syndrome[0x20]; 5311 5312 u8 reserved_at_40[0x20]; 5313 u8 ece[0x20]; 5314 }; 5315 5316 struct mlx5_ifc_rtr2rts_qp_in_bits { 5317 u8 opcode[0x10]; 5318 u8 uid[0x10]; 5319 5320 u8 reserved_at_20[0x10]; 5321 u8 op_mod[0x10]; 5322 5323 u8 reserved_at_40[0x8]; 5324 u8 qpn[0x18]; 5325 5326 u8 reserved_at_60[0x20]; 5327 5328 u8 opt_param_mask[0x20]; 5329 5330 u8 ece[0x20]; 5331 5332 struct mlx5_ifc_qpc_bits qpc; 5333 5334 u8 reserved_at_800[0x80]; 5335 }; 5336 5337 struct mlx5_ifc_rst2init_qp_out_bits { 5338 u8 status[0x8]; 5339 u8 reserved_at_8[0x18]; 5340 5341 u8 syndrome[0x20]; 5342 5343 u8 reserved_at_40[0x20]; 5344 u8 ece[0x20]; 5345 }; 5346 5347 struct mlx5_ifc_rst2init_qp_in_bits { 5348 u8 opcode[0x10]; 5349 u8 uid[0x10]; 5350 5351 u8 reserved_at_20[0x10]; 5352 u8 op_mod[0x10]; 5353 5354 u8 reserved_at_40[0x8]; 5355 u8 qpn[0x18]; 5356 5357 u8 reserved_at_60[0x20]; 5358 5359 u8 opt_param_mask[0x20]; 5360 5361 u8 ece[0x20]; 5362 5363 struct mlx5_ifc_qpc_bits qpc; 5364 5365 u8 reserved_at_800[0x80]; 5366 }; 5367 5368 struct mlx5_ifc_query_xrq_out_bits { 5369 u8 status[0x8]; 5370 u8 reserved_at_8[0x18]; 5371 5372 u8 syndrome[0x20]; 5373 5374 u8 reserved_at_40[0x40]; 5375 5376 struct mlx5_ifc_xrqc_bits xrq_context; 5377 }; 5378 5379 struct mlx5_ifc_query_xrq_in_bits { 5380 u8 opcode[0x10]; 5381 u8 reserved_at_10[0x10]; 5382 5383 u8 reserved_at_20[0x10]; 5384 u8 op_mod[0x10]; 5385 5386 u8 reserved_at_40[0x8]; 5387 u8 xrqn[0x18]; 5388 5389 u8 reserved_at_60[0x20]; 5390 }; 5391 5392 struct mlx5_ifc_query_xrc_srq_out_bits { 5393 u8 status[0x8]; 5394 u8 reserved_at_8[0x18]; 5395 5396 u8 syndrome[0x20]; 5397 5398 u8 reserved_at_40[0x40]; 5399 5400 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 5401 5402 u8 reserved_at_280[0x600]; 5403 5404 u8 pas[][0x40]; 5405 }; 5406 5407 struct mlx5_ifc_query_xrc_srq_in_bits { 5408 u8 opcode[0x10]; 5409 u8 reserved_at_10[0x10]; 5410 5411 u8 reserved_at_20[0x10]; 5412 u8 op_mod[0x10]; 5413 5414 u8 reserved_at_40[0x8]; 5415 u8 xrc_srqn[0x18]; 5416 5417 u8 reserved_at_60[0x20]; 5418 }; 5419 5420 enum { 5421 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0, 5422 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1, 5423 }; 5424 5425 struct mlx5_ifc_query_vport_state_out_bits { 5426 u8 status[0x8]; 5427 u8 reserved_at_8[0x18]; 5428 5429 u8 syndrome[0x20]; 5430 5431 u8 reserved_at_40[0x20]; 5432 5433 u8 reserved_at_60[0x18]; 5434 u8 admin_state[0x4]; 5435 u8 state[0x4]; 5436 }; 5437 5438 struct mlx5_ifc_array1024_auto_bits { 5439 u8 array1024_auto[32][0x20]; 5440 }; 5441 5442 struct mlx5_ifc_query_vuid_in_bits { 5443 u8 opcode[0x10]; 5444 u8 uid[0x10]; 5445 5446 u8 reserved_at_20[0x40]; 5447 5448 u8 query_vfs_vuid[0x1]; 5449 u8 data_direct[0x1]; 5450 u8 reserved_at_62[0xe]; 5451 u8 vhca_id[0x10]; 5452 }; 5453 5454 struct mlx5_ifc_query_vuid_out_bits { 5455 u8 status[0x8]; 5456 u8 reserved_at_8[0x18]; 5457 5458 u8 syndrome[0x20]; 5459 5460 u8 reserved_at_40[0x1a0]; 5461 5462 u8 reserved_at_1e0[0x10]; 5463 u8 num_of_entries[0x10]; 5464 5465 struct mlx5_ifc_array1024_auto_bits vuid[]; 5466 }; 5467 5468 enum { 5469 MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT = 0x0, 5470 MLX5_VPORT_STATE_OP_MOD_ESW_VPORT = 0x1, 5471 MLX5_VPORT_STATE_OP_MOD_UPLINK = 0x2, 5472 }; 5473 5474 struct mlx5_ifc_arm_monitor_counter_in_bits { 5475 u8 opcode[0x10]; 5476 u8 uid[0x10]; 5477 5478 u8 reserved_at_20[0x10]; 5479 u8 op_mod[0x10]; 5480 5481 u8 reserved_at_40[0x20]; 5482 5483 u8 reserved_at_60[0x20]; 5484 }; 5485 5486 struct mlx5_ifc_arm_monitor_counter_out_bits { 5487 u8 status[0x8]; 5488 u8 reserved_at_8[0x18]; 5489 5490 u8 syndrome[0x20]; 5491 5492 u8 reserved_at_40[0x40]; 5493 }; 5494 5495 enum { 5496 MLX5_QUERY_MONITOR_CNT_TYPE_PPCNT = 0x0, 5497 MLX5_QUERY_MONITOR_CNT_TYPE_Q_COUNTER = 0x1, 5498 }; 5499 5500 enum mlx5_monitor_counter_ppcnt { 5501 MLX5_QUERY_MONITOR_PPCNT_IN_RANGE_LENGTH_ERRORS = 0x0, 5502 MLX5_QUERY_MONITOR_PPCNT_OUT_OF_RANGE_LENGTH_FIELD = 0x1, 5503 MLX5_QUERY_MONITOR_PPCNT_FRAME_TOO_LONG_ERRORS = 0x2, 5504 MLX5_QUERY_MONITOR_PPCNT_FRAME_CHECK_SEQUENCE_ERRORS = 0x3, 5505 MLX5_QUERY_MONITOR_PPCNT_ALIGNMENT_ERRORS = 0x4, 5506 MLX5_QUERY_MONITOR_PPCNT_IF_OUT_DISCARDS = 0x5, 5507 }; 5508 5509 enum { 5510 MLX5_QUERY_MONITOR_Q_COUNTER_RX_OUT_OF_BUFFER = 0x4, 5511 }; 5512 5513 struct mlx5_ifc_monitor_counter_output_bits { 5514 u8 reserved_at_0[0x4]; 5515 u8 type[0x4]; 5516 u8 reserved_at_8[0x8]; 5517 u8 counter[0x10]; 5518 5519 u8 counter_group_id[0x20]; 5520 }; 5521 5522 #define MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 (6) 5523 #define MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1 (1) 5524 #define MLX5_CMD_SET_MONITOR_NUM_COUNTER (MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 +\ 5525 MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1) 5526 5527 struct mlx5_ifc_set_monitor_counter_in_bits { 5528 u8 opcode[0x10]; 5529 u8 uid[0x10]; 5530 5531 u8 reserved_at_20[0x10]; 5532 u8 op_mod[0x10]; 5533 5534 u8 reserved_at_40[0x10]; 5535 u8 num_of_counters[0x10]; 5536 5537 u8 reserved_at_60[0x20]; 5538 5539 struct mlx5_ifc_monitor_counter_output_bits monitor_counter[MLX5_CMD_SET_MONITOR_NUM_COUNTER]; 5540 }; 5541 5542 struct mlx5_ifc_set_monitor_counter_out_bits { 5543 u8 status[0x8]; 5544 u8 reserved_at_8[0x18]; 5545 5546 u8 syndrome[0x20]; 5547 5548 u8 reserved_at_40[0x40]; 5549 }; 5550 5551 struct mlx5_ifc_query_vport_state_in_bits { 5552 u8 opcode[0x10]; 5553 u8 reserved_at_10[0x10]; 5554 5555 u8 reserved_at_20[0x10]; 5556 u8 op_mod[0x10]; 5557 5558 u8 other_vport[0x1]; 5559 u8 reserved_at_41[0xf]; 5560 u8 vport_number[0x10]; 5561 5562 u8 reserved_at_60[0x20]; 5563 }; 5564 5565 struct mlx5_ifc_query_vnic_env_out_bits { 5566 u8 status[0x8]; 5567 u8 reserved_at_8[0x18]; 5568 5569 u8 syndrome[0x20]; 5570 5571 u8 reserved_at_40[0x40]; 5572 5573 struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env; 5574 }; 5575 5576 enum { 5577 MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS = 0x0, 5578 }; 5579 5580 struct mlx5_ifc_query_vnic_env_in_bits { 5581 u8 opcode[0x10]; 5582 u8 reserved_at_10[0x10]; 5583 5584 u8 reserved_at_20[0x10]; 5585 u8 op_mod[0x10]; 5586 5587 u8 other_vport[0x1]; 5588 u8 reserved_at_41[0xf]; 5589 u8 vport_number[0x10]; 5590 5591 u8 reserved_at_60[0x20]; 5592 }; 5593 5594 struct mlx5_ifc_query_vport_counter_out_bits { 5595 u8 status[0x8]; 5596 u8 reserved_at_8[0x18]; 5597 5598 u8 syndrome[0x20]; 5599 5600 u8 reserved_at_40[0x40]; 5601 5602 struct mlx5_ifc_traffic_counter_bits received_errors; 5603 5604 struct mlx5_ifc_traffic_counter_bits transmit_errors; 5605 5606 struct mlx5_ifc_traffic_counter_bits received_ib_unicast; 5607 5608 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast; 5609 5610 struct mlx5_ifc_traffic_counter_bits received_ib_multicast; 5611 5612 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast; 5613 5614 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast; 5615 5616 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast; 5617 5618 struct mlx5_ifc_traffic_counter_bits received_eth_unicast; 5619 5620 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast; 5621 5622 struct mlx5_ifc_traffic_counter_bits received_eth_multicast; 5623 5624 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast; 5625 5626 struct mlx5_ifc_traffic_counter_bits local_loopback; 5627 5628 u8 reserved_at_700[0x980]; 5629 }; 5630 5631 enum { 5632 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0, 5633 }; 5634 5635 struct mlx5_ifc_query_vport_counter_in_bits { 5636 u8 opcode[0x10]; 5637 u8 reserved_at_10[0x10]; 5638 5639 u8 reserved_at_20[0x10]; 5640 u8 op_mod[0x10]; 5641 5642 u8 other_vport[0x1]; 5643 u8 reserved_at_41[0xb]; 5644 u8 port_num[0x4]; 5645 u8 vport_number[0x10]; 5646 5647 u8 reserved_at_60[0x60]; 5648 5649 u8 clear[0x1]; 5650 u8 reserved_at_c1[0x1f]; 5651 5652 u8 reserved_at_e0[0x20]; 5653 }; 5654 5655 struct mlx5_ifc_query_tis_out_bits { 5656 u8 status[0x8]; 5657 u8 reserved_at_8[0x18]; 5658 5659 u8 syndrome[0x20]; 5660 5661 u8 reserved_at_40[0x40]; 5662 5663 struct mlx5_ifc_tisc_bits tis_context; 5664 }; 5665 5666 struct mlx5_ifc_query_tis_in_bits { 5667 u8 opcode[0x10]; 5668 u8 reserved_at_10[0x10]; 5669 5670 u8 reserved_at_20[0x10]; 5671 u8 op_mod[0x10]; 5672 5673 u8 reserved_at_40[0x8]; 5674 u8 tisn[0x18]; 5675 5676 u8 reserved_at_60[0x20]; 5677 }; 5678 5679 struct mlx5_ifc_query_tir_out_bits { 5680 u8 status[0x8]; 5681 u8 reserved_at_8[0x18]; 5682 5683 u8 syndrome[0x20]; 5684 5685 u8 reserved_at_40[0xc0]; 5686 5687 struct mlx5_ifc_tirc_bits tir_context; 5688 }; 5689 5690 struct mlx5_ifc_query_tir_in_bits { 5691 u8 opcode[0x10]; 5692 u8 reserved_at_10[0x10]; 5693 5694 u8 reserved_at_20[0x10]; 5695 u8 op_mod[0x10]; 5696 5697 u8 reserved_at_40[0x8]; 5698 u8 tirn[0x18]; 5699 5700 u8 reserved_at_60[0x20]; 5701 }; 5702 5703 struct mlx5_ifc_query_srq_out_bits { 5704 u8 status[0x8]; 5705 u8 reserved_at_8[0x18]; 5706 5707 u8 syndrome[0x20]; 5708 5709 u8 reserved_at_40[0x40]; 5710 5711 struct mlx5_ifc_srqc_bits srq_context_entry; 5712 5713 u8 reserved_at_280[0x600]; 5714 5715 u8 pas[][0x40]; 5716 }; 5717 5718 struct mlx5_ifc_query_srq_in_bits { 5719 u8 opcode[0x10]; 5720 u8 reserved_at_10[0x10]; 5721 5722 u8 reserved_at_20[0x10]; 5723 u8 op_mod[0x10]; 5724 5725 u8 reserved_at_40[0x8]; 5726 u8 srqn[0x18]; 5727 5728 u8 reserved_at_60[0x20]; 5729 }; 5730 5731 struct mlx5_ifc_query_sq_out_bits { 5732 u8 status[0x8]; 5733 u8 reserved_at_8[0x18]; 5734 5735 u8 syndrome[0x20]; 5736 5737 u8 reserved_at_40[0xc0]; 5738 5739 struct mlx5_ifc_sqc_bits sq_context; 5740 }; 5741 5742 struct mlx5_ifc_query_sq_in_bits { 5743 u8 opcode[0x10]; 5744 u8 reserved_at_10[0x10]; 5745 5746 u8 reserved_at_20[0x10]; 5747 u8 op_mod[0x10]; 5748 5749 u8 reserved_at_40[0x8]; 5750 u8 sqn[0x18]; 5751 5752 u8 reserved_at_60[0x20]; 5753 }; 5754 5755 struct mlx5_ifc_query_special_contexts_out_bits { 5756 u8 status[0x8]; 5757 u8 reserved_at_8[0x18]; 5758 5759 u8 syndrome[0x20]; 5760 5761 u8 dump_fill_mkey[0x20]; 5762 5763 u8 resd_lkey[0x20]; 5764 5765 u8 null_mkey[0x20]; 5766 5767 u8 terminate_scatter_list_mkey[0x20]; 5768 5769 u8 repeated_mkey[0x20]; 5770 5771 u8 reserved_at_a0[0x20]; 5772 }; 5773 5774 struct mlx5_ifc_query_special_contexts_in_bits { 5775 u8 opcode[0x10]; 5776 u8 reserved_at_10[0x10]; 5777 5778 u8 reserved_at_20[0x10]; 5779 u8 op_mod[0x10]; 5780 5781 u8 reserved_at_40[0x40]; 5782 }; 5783 5784 struct mlx5_ifc_query_scheduling_element_out_bits { 5785 u8 opcode[0x10]; 5786 u8 reserved_at_10[0x10]; 5787 5788 u8 reserved_at_20[0x10]; 5789 u8 op_mod[0x10]; 5790 5791 u8 reserved_at_40[0xc0]; 5792 5793 struct mlx5_ifc_scheduling_context_bits scheduling_context; 5794 5795 u8 reserved_at_300[0x100]; 5796 }; 5797 5798 enum { 5799 SCHEDULING_HIERARCHY_E_SWITCH = 0x2, 5800 SCHEDULING_HIERARCHY_NIC = 0x3, 5801 }; 5802 5803 struct mlx5_ifc_query_scheduling_element_in_bits { 5804 u8 opcode[0x10]; 5805 u8 reserved_at_10[0x10]; 5806 5807 u8 reserved_at_20[0x10]; 5808 u8 op_mod[0x10]; 5809 5810 u8 scheduling_hierarchy[0x8]; 5811 u8 reserved_at_48[0x18]; 5812 5813 u8 scheduling_element_id[0x20]; 5814 5815 u8 reserved_at_80[0x180]; 5816 }; 5817 5818 struct mlx5_ifc_query_rqt_out_bits { 5819 u8 status[0x8]; 5820 u8 reserved_at_8[0x18]; 5821 5822 u8 syndrome[0x20]; 5823 5824 u8 reserved_at_40[0xc0]; 5825 5826 struct mlx5_ifc_rqtc_bits rqt_context; 5827 }; 5828 5829 struct mlx5_ifc_query_rqt_in_bits { 5830 u8 opcode[0x10]; 5831 u8 reserved_at_10[0x10]; 5832 5833 u8 reserved_at_20[0x10]; 5834 u8 op_mod[0x10]; 5835 5836 u8 reserved_at_40[0x8]; 5837 u8 rqtn[0x18]; 5838 5839 u8 reserved_at_60[0x20]; 5840 }; 5841 5842 struct mlx5_ifc_query_rq_out_bits { 5843 u8 status[0x8]; 5844 u8 reserved_at_8[0x18]; 5845 5846 u8 syndrome[0x20]; 5847 5848 u8 reserved_at_40[0xc0]; 5849 5850 struct mlx5_ifc_rqc_bits rq_context; 5851 }; 5852 5853 struct mlx5_ifc_query_rq_in_bits { 5854 u8 opcode[0x10]; 5855 u8 reserved_at_10[0x10]; 5856 5857 u8 reserved_at_20[0x10]; 5858 u8 op_mod[0x10]; 5859 5860 u8 reserved_at_40[0x8]; 5861 u8 rqn[0x18]; 5862 5863 u8 reserved_at_60[0x20]; 5864 }; 5865 5866 struct mlx5_ifc_query_roce_address_out_bits { 5867 u8 status[0x8]; 5868 u8 reserved_at_8[0x18]; 5869 5870 u8 syndrome[0x20]; 5871 5872 u8 reserved_at_40[0x40]; 5873 5874 struct mlx5_ifc_roce_addr_layout_bits roce_address; 5875 }; 5876 5877 struct mlx5_ifc_query_roce_address_in_bits { 5878 u8 opcode[0x10]; 5879 u8 reserved_at_10[0x10]; 5880 5881 u8 reserved_at_20[0x10]; 5882 u8 op_mod[0x10]; 5883 5884 u8 roce_address_index[0x10]; 5885 u8 reserved_at_50[0xc]; 5886 u8 vhca_port_num[0x4]; 5887 5888 u8 reserved_at_60[0x20]; 5889 }; 5890 5891 struct mlx5_ifc_query_rmp_out_bits { 5892 u8 status[0x8]; 5893 u8 reserved_at_8[0x18]; 5894 5895 u8 syndrome[0x20]; 5896 5897 u8 reserved_at_40[0xc0]; 5898 5899 struct mlx5_ifc_rmpc_bits rmp_context; 5900 }; 5901 5902 struct mlx5_ifc_query_rmp_in_bits { 5903 u8 opcode[0x10]; 5904 u8 reserved_at_10[0x10]; 5905 5906 u8 reserved_at_20[0x10]; 5907 u8 op_mod[0x10]; 5908 5909 u8 reserved_at_40[0x8]; 5910 u8 rmpn[0x18]; 5911 5912 u8 reserved_at_60[0x20]; 5913 }; 5914 5915 struct mlx5_ifc_cqe_error_syndrome_bits { 5916 u8 hw_error_syndrome[0x8]; 5917 u8 hw_syndrome_type[0x4]; 5918 u8 reserved_at_c[0x4]; 5919 u8 vendor_error_syndrome[0x8]; 5920 u8 syndrome[0x8]; 5921 }; 5922 5923 struct mlx5_ifc_qp_context_extension_bits { 5924 u8 reserved_at_0[0x60]; 5925 5926 struct mlx5_ifc_cqe_error_syndrome_bits error_syndrome; 5927 5928 u8 reserved_at_80[0x580]; 5929 }; 5930 5931 struct mlx5_ifc_qpc_extension_and_pas_list_in_bits { 5932 struct mlx5_ifc_qp_context_extension_bits qpc_data_extension; 5933 5934 u8 pas[0][0x40]; 5935 }; 5936 5937 struct mlx5_ifc_qp_pas_list_in_bits { 5938 struct mlx5_ifc_cmd_pas_bits pas[0]; 5939 }; 5940 5941 union mlx5_ifc_qp_pas_or_qpc_ext_and_pas_bits { 5942 struct mlx5_ifc_qp_pas_list_in_bits qp_pas_list; 5943 struct mlx5_ifc_qpc_extension_and_pas_list_in_bits qpc_ext_and_pas_list; 5944 }; 5945 5946 struct mlx5_ifc_query_qp_out_bits { 5947 u8 status[0x8]; 5948 u8 reserved_at_8[0x18]; 5949 5950 u8 syndrome[0x20]; 5951 5952 u8 reserved_at_40[0x40]; 5953 5954 u8 opt_param_mask[0x20]; 5955 5956 u8 ece[0x20]; 5957 5958 struct mlx5_ifc_qpc_bits qpc; 5959 5960 u8 reserved_at_800[0x80]; 5961 5962 union mlx5_ifc_qp_pas_or_qpc_ext_and_pas_bits qp_pas_or_qpc_ext_and_pas; 5963 }; 5964 5965 struct mlx5_ifc_query_qp_in_bits { 5966 u8 opcode[0x10]; 5967 u8 reserved_at_10[0x10]; 5968 5969 u8 reserved_at_20[0x10]; 5970 u8 op_mod[0x10]; 5971 5972 u8 qpc_ext[0x1]; 5973 u8 reserved_at_41[0x7]; 5974 u8 qpn[0x18]; 5975 5976 u8 reserved_at_60[0x20]; 5977 }; 5978 5979 struct mlx5_ifc_query_q_counter_out_bits { 5980 u8 status[0x8]; 5981 u8 reserved_at_8[0x18]; 5982 5983 u8 syndrome[0x20]; 5984 5985 u8 reserved_at_40[0x40]; 5986 5987 u8 rx_write_requests[0x20]; 5988 5989 u8 reserved_at_a0[0x20]; 5990 5991 u8 rx_read_requests[0x20]; 5992 5993 u8 reserved_at_e0[0x20]; 5994 5995 u8 rx_atomic_requests[0x20]; 5996 5997 u8 reserved_at_120[0x20]; 5998 5999 u8 rx_dct_connect[0x20]; 6000 6001 u8 reserved_at_160[0x20]; 6002 6003 u8 out_of_buffer[0x20]; 6004 6005 u8 reserved_at_1a0[0x20]; 6006 6007 u8 out_of_sequence[0x20]; 6008 6009 u8 reserved_at_1e0[0x20]; 6010 6011 u8 duplicate_request[0x20]; 6012 6013 u8 reserved_at_220[0x20]; 6014 6015 u8 rnr_nak_retry_err[0x20]; 6016 6017 u8 reserved_at_260[0x20]; 6018 6019 u8 packet_seq_err[0x20]; 6020 6021 u8 reserved_at_2a0[0x20]; 6022 6023 u8 implied_nak_seq_err[0x20]; 6024 6025 u8 reserved_at_2e0[0x20]; 6026 6027 u8 local_ack_timeout_err[0x20]; 6028 6029 u8 reserved_at_320[0x60]; 6030 6031 u8 req_rnr_retries_exceeded[0x20]; 6032 6033 u8 reserved_at_3a0[0x20]; 6034 6035 u8 resp_local_length_error[0x20]; 6036 6037 u8 req_local_length_error[0x20]; 6038 6039 u8 resp_local_qp_error[0x20]; 6040 6041 u8 local_operation_error[0x20]; 6042 6043 u8 resp_local_protection[0x20]; 6044 6045 u8 req_local_protection[0x20]; 6046 6047 u8 resp_cqe_error[0x20]; 6048 6049 u8 req_cqe_error[0x20]; 6050 6051 u8 req_mw_binding[0x20]; 6052 6053 u8 req_bad_response[0x20]; 6054 6055 u8 req_remote_invalid_request[0x20]; 6056 6057 u8 resp_remote_invalid_request[0x20]; 6058 6059 u8 req_remote_access_errors[0x20]; 6060 6061 u8 resp_remote_access_errors[0x20]; 6062 6063 u8 req_remote_operation_errors[0x20]; 6064 6065 u8 req_transport_retries_exceeded[0x20]; 6066 6067 u8 cq_overflow[0x20]; 6068 6069 u8 resp_cqe_flush_error[0x20]; 6070 6071 u8 req_cqe_flush_error[0x20]; 6072 6073 u8 reserved_at_620[0x20]; 6074 6075 u8 roce_adp_retrans[0x20]; 6076 6077 u8 roce_adp_retrans_to[0x20]; 6078 6079 u8 roce_slow_restart[0x20]; 6080 6081 u8 roce_slow_restart_cnps[0x20]; 6082 6083 u8 roce_slow_restart_trans[0x20]; 6084 6085 u8 reserved_at_6e0[0x120]; 6086 }; 6087 6088 struct mlx5_ifc_query_q_counter_in_bits { 6089 u8 opcode[0x10]; 6090 u8 reserved_at_10[0x10]; 6091 6092 u8 reserved_at_20[0x10]; 6093 u8 op_mod[0x10]; 6094 6095 u8 other_vport[0x1]; 6096 u8 reserved_at_41[0xf]; 6097 u8 vport_number[0x10]; 6098 6099 u8 reserved_at_60[0x60]; 6100 6101 u8 clear[0x1]; 6102 u8 aggregate[0x1]; 6103 u8 reserved_at_c2[0x1e]; 6104 6105 u8 reserved_at_e0[0x18]; 6106 u8 counter_set_id[0x8]; 6107 }; 6108 6109 struct mlx5_ifc_query_pages_out_bits { 6110 u8 status[0x8]; 6111 u8 reserved_at_8[0x18]; 6112 6113 u8 syndrome[0x20]; 6114 6115 u8 embedded_cpu_function[0x1]; 6116 u8 reserved_at_41[0xf]; 6117 u8 function_id[0x10]; 6118 6119 u8 num_pages[0x20]; 6120 }; 6121 6122 enum { 6123 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1, 6124 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2, 6125 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3, 6126 }; 6127 6128 struct mlx5_ifc_query_pages_in_bits { 6129 u8 opcode[0x10]; 6130 u8 reserved_at_10[0x10]; 6131 6132 u8 reserved_at_20[0x10]; 6133 u8 op_mod[0x10]; 6134 6135 u8 embedded_cpu_function[0x1]; 6136 u8 reserved_at_41[0xf]; 6137 u8 function_id[0x10]; 6138 6139 u8 reserved_at_60[0x20]; 6140 }; 6141 6142 struct mlx5_ifc_query_nic_vport_context_out_bits { 6143 u8 status[0x8]; 6144 u8 reserved_at_8[0x18]; 6145 6146 u8 syndrome[0x20]; 6147 6148 u8 reserved_at_40[0x40]; 6149 6150 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 6151 }; 6152 6153 struct mlx5_ifc_query_nic_vport_context_in_bits { 6154 u8 opcode[0x10]; 6155 u8 reserved_at_10[0x10]; 6156 6157 u8 reserved_at_20[0x10]; 6158 u8 op_mod[0x10]; 6159 6160 u8 other_vport[0x1]; 6161 u8 reserved_at_41[0xf]; 6162 u8 vport_number[0x10]; 6163 6164 u8 reserved_at_60[0x5]; 6165 u8 allowed_list_type[0x3]; 6166 u8 reserved_at_68[0x18]; 6167 }; 6168 6169 struct mlx5_ifc_query_mkey_out_bits { 6170 u8 status[0x8]; 6171 u8 reserved_at_8[0x18]; 6172 6173 u8 syndrome[0x20]; 6174 6175 u8 reserved_at_40[0x40]; 6176 6177 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 6178 6179 u8 reserved_at_280[0x600]; 6180 6181 u8 bsf0_klm0_pas_mtt0_1[16][0x8]; 6182 6183 u8 bsf1_klm1_pas_mtt2_3[16][0x8]; 6184 }; 6185 6186 struct mlx5_ifc_query_mkey_in_bits { 6187 u8 opcode[0x10]; 6188 u8 reserved_at_10[0x10]; 6189 6190 u8 reserved_at_20[0x10]; 6191 u8 op_mod[0x10]; 6192 6193 u8 reserved_at_40[0x8]; 6194 u8 mkey_index[0x18]; 6195 6196 u8 pg_access[0x1]; 6197 u8 reserved_at_61[0x1f]; 6198 }; 6199 6200 struct mlx5_ifc_query_mad_demux_out_bits { 6201 u8 status[0x8]; 6202 u8 reserved_at_8[0x18]; 6203 6204 u8 syndrome[0x20]; 6205 6206 u8 reserved_at_40[0x40]; 6207 6208 u8 mad_dumux_parameters_block[0x20]; 6209 }; 6210 6211 struct mlx5_ifc_query_mad_demux_in_bits { 6212 u8 opcode[0x10]; 6213 u8 reserved_at_10[0x10]; 6214 6215 u8 reserved_at_20[0x10]; 6216 u8 op_mod[0x10]; 6217 6218 u8 reserved_at_40[0x40]; 6219 }; 6220 6221 struct mlx5_ifc_query_l2_table_entry_out_bits { 6222 u8 status[0x8]; 6223 u8 reserved_at_8[0x18]; 6224 6225 u8 syndrome[0x20]; 6226 6227 u8 reserved_at_40[0xa0]; 6228 6229 u8 reserved_at_e0[0x13]; 6230 u8 vlan_valid[0x1]; 6231 u8 vlan[0xc]; 6232 6233 struct mlx5_ifc_mac_address_layout_bits mac_address; 6234 6235 u8 reserved_at_140[0xc0]; 6236 }; 6237 6238 struct mlx5_ifc_query_l2_table_entry_in_bits { 6239 u8 opcode[0x10]; 6240 u8 reserved_at_10[0x10]; 6241 6242 u8 reserved_at_20[0x10]; 6243 u8 op_mod[0x10]; 6244 6245 u8 reserved_at_40[0x60]; 6246 6247 u8 reserved_at_a0[0x8]; 6248 u8 table_index[0x18]; 6249 6250 u8 reserved_at_c0[0x140]; 6251 }; 6252 6253 struct mlx5_ifc_query_issi_out_bits { 6254 u8 status[0x8]; 6255 u8 reserved_at_8[0x18]; 6256 6257 u8 syndrome[0x20]; 6258 6259 u8 reserved_at_40[0x10]; 6260 u8 current_issi[0x10]; 6261 6262 u8 reserved_at_60[0xa0]; 6263 6264 u8 reserved_at_100[76][0x8]; 6265 u8 supported_issi_dw0[0x20]; 6266 }; 6267 6268 struct mlx5_ifc_query_issi_in_bits { 6269 u8 opcode[0x10]; 6270 u8 reserved_at_10[0x10]; 6271 6272 u8 reserved_at_20[0x10]; 6273 u8 op_mod[0x10]; 6274 6275 u8 reserved_at_40[0x40]; 6276 }; 6277 6278 struct mlx5_ifc_set_driver_version_out_bits { 6279 u8 status[0x8]; 6280 u8 reserved_0[0x18]; 6281 6282 u8 syndrome[0x20]; 6283 u8 reserved_1[0x40]; 6284 }; 6285 6286 struct mlx5_ifc_set_driver_version_in_bits { 6287 u8 opcode[0x10]; 6288 u8 reserved_0[0x10]; 6289 6290 u8 reserved_1[0x10]; 6291 u8 op_mod[0x10]; 6292 6293 u8 reserved_2[0x40]; 6294 u8 driver_version[64][0x8]; 6295 }; 6296 6297 struct mlx5_ifc_query_hca_vport_pkey_out_bits { 6298 u8 status[0x8]; 6299 u8 reserved_at_8[0x18]; 6300 6301 u8 syndrome[0x20]; 6302 6303 u8 reserved_at_40[0x40]; 6304 6305 struct mlx5_ifc_pkey_bits pkey[]; 6306 }; 6307 6308 struct mlx5_ifc_query_hca_vport_pkey_in_bits { 6309 u8 opcode[0x10]; 6310 u8 reserved_at_10[0x10]; 6311 6312 u8 reserved_at_20[0x10]; 6313 u8 op_mod[0x10]; 6314 6315 u8 other_vport[0x1]; 6316 u8 reserved_at_41[0xb]; 6317 u8 port_num[0x4]; 6318 u8 vport_number[0x10]; 6319 6320 u8 reserved_at_60[0x10]; 6321 u8 pkey_index[0x10]; 6322 }; 6323 6324 enum { 6325 MLX5_HCA_VPORT_SEL_PORT_GUID = 1 << 0, 6326 MLX5_HCA_VPORT_SEL_NODE_GUID = 1 << 1, 6327 MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2, 6328 }; 6329 6330 struct mlx5_ifc_query_hca_vport_gid_out_bits { 6331 u8 status[0x8]; 6332 u8 reserved_at_8[0x18]; 6333 6334 u8 syndrome[0x20]; 6335 6336 u8 reserved_at_40[0x20]; 6337 6338 u8 gids_num[0x10]; 6339 u8 reserved_at_70[0x10]; 6340 6341 struct mlx5_ifc_array128_auto_bits gid[]; 6342 }; 6343 6344 struct mlx5_ifc_query_hca_vport_gid_in_bits { 6345 u8 opcode[0x10]; 6346 u8 reserved_at_10[0x10]; 6347 6348 u8 reserved_at_20[0x10]; 6349 u8 op_mod[0x10]; 6350 6351 u8 other_vport[0x1]; 6352 u8 reserved_at_41[0xb]; 6353 u8 port_num[0x4]; 6354 u8 vport_number[0x10]; 6355 6356 u8 reserved_at_60[0x10]; 6357 u8 gid_index[0x10]; 6358 }; 6359 6360 struct mlx5_ifc_query_hca_vport_context_out_bits { 6361 u8 status[0x8]; 6362 u8 reserved_at_8[0x18]; 6363 6364 u8 syndrome[0x20]; 6365 6366 u8 reserved_at_40[0x40]; 6367 6368 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 6369 }; 6370 6371 struct mlx5_ifc_query_hca_vport_context_in_bits { 6372 u8 opcode[0x10]; 6373 u8 reserved_at_10[0x10]; 6374 6375 u8 reserved_at_20[0x10]; 6376 u8 op_mod[0x10]; 6377 6378 u8 other_vport[0x1]; 6379 u8 reserved_at_41[0xb]; 6380 u8 port_num[0x4]; 6381 u8 vport_number[0x10]; 6382 6383 u8 reserved_at_60[0x20]; 6384 }; 6385 6386 struct mlx5_ifc_query_hca_cap_out_bits { 6387 u8 status[0x8]; 6388 u8 reserved_at_8[0x18]; 6389 6390 u8 syndrome[0x20]; 6391 6392 u8 reserved_at_40[0x40]; 6393 6394 union mlx5_ifc_hca_cap_union_bits capability; 6395 }; 6396 6397 struct mlx5_ifc_query_hca_cap_in_bits { 6398 u8 opcode[0x10]; 6399 u8 reserved_at_10[0x10]; 6400 6401 u8 reserved_at_20[0x10]; 6402 u8 op_mod[0x10]; 6403 6404 u8 other_function[0x1]; 6405 u8 ec_vf_function[0x1]; 6406 u8 reserved_at_42[0x1]; 6407 u8 function_id_type[0x1]; 6408 u8 reserved_at_44[0xc]; 6409 u8 function_id[0x10]; 6410 6411 u8 reserved_at_60[0x20]; 6412 }; 6413 6414 struct mlx5_ifc_other_hca_cap_bits { 6415 u8 roce[0x1]; 6416 u8 reserved_at_1[0x27f]; 6417 }; 6418 6419 struct mlx5_ifc_query_other_hca_cap_out_bits { 6420 u8 status[0x8]; 6421 u8 reserved_at_8[0x18]; 6422 6423 u8 syndrome[0x20]; 6424 6425 u8 reserved_at_40[0x40]; 6426 6427 struct mlx5_ifc_other_hca_cap_bits other_capability; 6428 }; 6429 6430 struct mlx5_ifc_query_other_hca_cap_in_bits { 6431 u8 opcode[0x10]; 6432 u8 reserved_at_10[0x10]; 6433 6434 u8 reserved_at_20[0x10]; 6435 u8 op_mod[0x10]; 6436 6437 u8 reserved_at_40[0x10]; 6438 u8 function_id[0x10]; 6439 6440 u8 reserved_at_60[0x20]; 6441 }; 6442 6443 struct mlx5_ifc_modify_other_hca_cap_out_bits { 6444 u8 status[0x8]; 6445 u8 reserved_at_8[0x18]; 6446 6447 u8 syndrome[0x20]; 6448 6449 u8 reserved_at_40[0x40]; 6450 }; 6451 6452 struct mlx5_ifc_modify_other_hca_cap_in_bits { 6453 u8 opcode[0x10]; 6454 u8 reserved_at_10[0x10]; 6455 6456 u8 reserved_at_20[0x10]; 6457 u8 op_mod[0x10]; 6458 6459 u8 reserved_at_40[0x10]; 6460 u8 function_id[0x10]; 6461 u8 field_select[0x20]; 6462 6463 struct mlx5_ifc_other_hca_cap_bits other_capability; 6464 }; 6465 6466 struct mlx5_ifc_sw_owner_icm_root_params_bits { 6467 u8 sw_owner_icm_root_1[0x40]; 6468 6469 u8 sw_owner_icm_root_0[0x40]; 6470 }; 6471 6472 struct mlx5_ifc_rtc_params_bits { 6473 u8 rtc_id_0[0x20]; 6474 6475 u8 rtc_id_1[0x20]; 6476 6477 u8 reserved_at_40[0x40]; 6478 }; 6479 6480 struct mlx5_ifc_flow_table_context_bits { 6481 u8 reformat_en[0x1]; 6482 u8 decap_en[0x1]; 6483 u8 sw_owner[0x1]; 6484 u8 termination_table[0x1]; 6485 u8 table_miss_action[0x4]; 6486 u8 level[0x8]; 6487 u8 rtc_valid[0x1]; 6488 u8 reserved_at_11[0x7]; 6489 u8 log_size[0x8]; 6490 6491 u8 reserved_at_20[0x8]; 6492 u8 table_miss_id[0x18]; 6493 6494 u8 reserved_at_40[0x8]; 6495 u8 lag_master_next_table_id[0x18]; 6496 6497 u8 reserved_at_60[0x60]; 6498 6499 union { 6500 struct mlx5_ifc_sw_owner_icm_root_params_bits sws; 6501 struct mlx5_ifc_rtc_params_bits hws; 6502 }; 6503 }; 6504 6505 struct mlx5_ifc_query_flow_table_out_bits { 6506 u8 status[0x8]; 6507 u8 reserved_at_8[0x18]; 6508 6509 u8 syndrome[0x20]; 6510 6511 u8 reserved_at_40[0x80]; 6512 6513 struct mlx5_ifc_flow_table_context_bits flow_table_context; 6514 }; 6515 6516 struct mlx5_ifc_query_flow_table_in_bits { 6517 u8 opcode[0x10]; 6518 u8 reserved_at_10[0x10]; 6519 6520 u8 reserved_at_20[0x10]; 6521 u8 op_mod[0x10]; 6522 6523 u8 reserved_at_40[0x40]; 6524 6525 u8 table_type[0x8]; 6526 u8 reserved_at_88[0x18]; 6527 6528 u8 reserved_at_a0[0x8]; 6529 u8 table_id[0x18]; 6530 6531 u8 reserved_at_c0[0x140]; 6532 }; 6533 6534 struct mlx5_ifc_query_fte_out_bits { 6535 u8 status[0x8]; 6536 u8 reserved_at_8[0x18]; 6537 6538 u8 syndrome[0x20]; 6539 6540 u8 reserved_at_40[0x1c0]; 6541 6542 struct mlx5_ifc_flow_context_bits flow_context; 6543 }; 6544 6545 struct mlx5_ifc_query_fte_in_bits { 6546 u8 opcode[0x10]; 6547 u8 reserved_at_10[0x10]; 6548 6549 u8 reserved_at_20[0x10]; 6550 u8 op_mod[0x10]; 6551 6552 u8 reserved_at_40[0x40]; 6553 6554 u8 table_type[0x8]; 6555 u8 reserved_at_88[0x18]; 6556 6557 u8 reserved_at_a0[0x8]; 6558 u8 table_id[0x18]; 6559 6560 u8 reserved_at_c0[0x40]; 6561 6562 u8 flow_index[0x20]; 6563 6564 u8 reserved_at_120[0xe0]; 6565 }; 6566 6567 struct mlx5_ifc_match_definer_format_0_bits { 6568 u8 reserved_at_0[0x100]; 6569 6570 u8 metadata_reg_c_0[0x20]; 6571 6572 u8 metadata_reg_c_1[0x20]; 6573 6574 u8 outer_dmac_47_16[0x20]; 6575 6576 u8 outer_dmac_15_0[0x10]; 6577 u8 outer_ethertype[0x10]; 6578 6579 u8 reserved_at_180[0x1]; 6580 u8 sx_sniffer[0x1]; 6581 u8 functional_lb[0x1]; 6582 u8 outer_ip_frag[0x1]; 6583 u8 outer_qp_type[0x2]; 6584 u8 outer_encap_type[0x2]; 6585 u8 port_number[0x2]; 6586 u8 outer_l3_type[0x2]; 6587 u8 outer_l4_type[0x2]; 6588 u8 outer_first_vlan_type[0x2]; 6589 u8 outer_first_vlan_prio[0x3]; 6590 u8 outer_first_vlan_cfi[0x1]; 6591 u8 outer_first_vlan_vid[0xc]; 6592 6593 u8 outer_l4_type_ext[0x4]; 6594 u8 reserved_at_1a4[0x2]; 6595 u8 outer_ipsec_layer[0x2]; 6596 u8 outer_l2_type[0x2]; 6597 u8 force_lb[0x1]; 6598 u8 outer_l2_ok[0x1]; 6599 u8 outer_l3_ok[0x1]; 6600 u8 outer_l4_ok[0x1]; 6601 u8 outer_second_vlan_type[0x2]; 6602 u8 outer_second_vlan_prio[0x3]; 6603 u8 outer_second_vlan_cfi[0x1]; 6604 u8 outer_second_vlan_vid[0xc]; 6605 6606 u8 outer_smac_47_16[0x20]; 6607 6608 u8 outer_smac_15_0[0x10]; 6609 u8 inner_ipv4_checksum_ok[0x1]; 6610 u8 inner_l4_checksum_ok[0x1]; 6611 u8 outer_ipv4_checksum_ok[0x1]; 6612 u8 outer_l4_checksum_ok[0x1]; 6613 u8 inner_l3_ok[0x1]; 6614 u8 inner_l4_ok[0x1]; 6615 u8 outer_l3_ok_duplicate[0x1]; 6616 u8 outer_l4_ok_duplicate[0x1]; 6617 u8 outer_tcp_cwr[0x1]; 6618 u8 outer_tcp_ece[0x1]; 6619 u8 outer_tcp_urg[0x1]; 6620 u8 outer_tcp_ack[0x1]; 6621 u8 outer_tcp_psh[0x1]; 6622 u8 outer_tcp_rst[0x1]; 6623 u8 outer_tcp_syn[0x1]; 6624 u8 outer_tcp_fin[0x1]; 6625 }; 6626 6627 struct mlx5_ifc_match_definer_format_22_bits { 6628 u8 reserved_at_0[0x100]; 6629 6630 u8 outer_ip_src_addr[0x20]; 6631 6632 u8 outer_ip_dest_addr[0x20]; 6633 6634 u8 outer_l4_sport[0x10]; 6635 u8 outer_l4_dport[0x10]; 6636 6637 u8 reserved_at_160[0x1]; 6638 u8 sx_sniffer[0x1]; 6639 u8 functional_lb[0x1]; 6640 u8 outer_ip_frag[0x1]; 6641 u8 outer_qp_type[0x2]; 6642 u8 outer_encap_type[0x2]; 6643 u8 port_number[0x2]; 6644 u8 outer_l3_type[0x2]; 6645 u8 outer_l4_type[0x2]; 6646 u8 outer_first_vlan_type[0x2]; 6647 u8 outer_first_vlan_prio[0x3]; 6648 u8 outer_first_vlan_cfi[0x1]; 6649 u8 outer_first_vlan_vid[0xc]; 6650 6651 u8 metadata_reg_c_0[0x20]; 6652 6653 u8 outer_dmac_47_16[0x20]; 6654 6655 u8 outer_smac_47_16[0x20]; 6656 6657 u8 outer_smac_15_0[0x10]; 6658 u8 outer_dmac_15_0[0x10]; 6659 }; 6660 6661 struct mlx5_ifc_match_definer_format_23_bits { 6662 u8 reserved_at_0[0x100]; 6663 6664 u8 inner_ip_src_addr[0x20]; 6665 6666 u8 inner_ip_dest_addr[0x20]; 6667 6668 u8 inner_l4_sport[0x10]; 6669 u8 inner_l4_dport[0x10]; 6670 6671 u8 reserved_at_160[0x1]; 6672 u8 sx_sniffer[0x1]; 6673 u8 functional_lb[0x1]; 6674 u8 inner_ip_frag[0x1]; 6675 u8 inner_qp_type[0x2]; 6676 u8 inner_encap_type[0x2]; 6677 u8 port_number[0x2]; 6678 u8 inner_l3_type[0x2]; 6679 u8 inner_l4_type[0x2]; 6680 u8 inner_first_vlan_type[0x2]; 6681 u8 inner_first_vlan_prio[0x3]; 6682 u8 inner_first_vlan_cfi[0x1]; 6683 u8 inner_first_vlan_vid[0xc]; 6684 6685 u8 tunnel_header_0[0x20]; 6686 6687 u8 inner_dmac_47_16[0x20]; 6688 6689 u8 inner_smac_47_16[0x20]; 6690 6691 u8 inner_smac_15_0[0x10]; 6692 u8 inner_dmac_15_0[0x10]; 6693 }; 6694 6695 struct mlx5_ifc_match_definer_format_29_bits { 6696 u8 reserved_at_0[0xc0]; 6697 6698 u8 outer_ip_dest_addr[0x80]; 6699 6700 u8 outer_ip_src_addr[0x80]; 6701 6702 u8 outer_l4_sport[0x10]; 6703 u8 outer_l4_dport[0x10]; 6704 6705 u8 reserved_at_1e0[0x20]; 6706 }; 6707 6708 struct mlx5_ifc_match_definer_format_30_bits { 6709 u8 reserved_at_0[0xa0]; 6710 6711 u8 outer_ip_dest_addr[0x80]; 6712 6713 u8 outer_ip_src_addr[0x80]; 6714 6715 u8 outer_dmac_47_16[0x20]; 6716 6717 u8 outer_smac_47_16[0x20]; 6718 6719 u8 outer_smac_15_0[0x10]; 6720 u8 outer_dmac_15_0[0x10]; 6721 }; 6722 6723 struct mlx5_ifc_match_definer_format_31_bits { 6724 u8 reserved_at_0[0xc0]; 6725 6726 u8 inner_ip_dest_addr[0x80]; 6727 6728 u8 inner_ip_src_addr[0x80]; 6729 6730 u8 inner_l4_sport[0x10]; 6731 u8 inner_l4_dport[0x10]; 6732 6733 u8 reserved_at_1e0[0x20]; 6734 }; 6735 6736 struct mlx5_ifc_match_definer_format_32_bits { 6737 u8 reserved_at_0[0xa0]; 6738 6739 u8 inner_ip_dest_addr[0x80]; 6740 6741 u8 inner_ip_src_addr[0x80]; 6742 6743 u8 inner_dmac_47_16[0x20]; 6744 6745 u8 inner_smac_47_16[0x20]; 6746 6747 u8 inner_smac_15_0[0x10]; 6748 u8 inner_dmac_15_0[0x10]; 6749 }; 6750 6751 enum { 6752 MLX5_IFC_DEFINER_FORMAT_ID_SELECT = 61, 6753 }; 6754 6755 #define MLX5_IFC_DEFINER_FORMAT_OFFSET_UNUSED 0x0 6756 #define MLX5_IFC_DEFINER_FORMAT_OFFSET_OUTER_ETH_PKT_LEN 0x48 6757 #define MLX5_IFC_DEFINER_DW_SELECTORS_NUM 9 6758 #define MLX5_IFC_DEFINER_BYTE_SELECTORS_NUM 8 6759 6760 struct mlx5_ifc_match_definer_match_mask_bits { 6761 u8 reserved_at_1c0[5][0x20]; 6762 u8 match_dw_8[0x20]; 6763 u8 match_dw_7[0x20]; 6764 u8 match_dw_6[0x20]; 6765 u8 match_dw_5[0x20]; 6766 u8 match_dw_4[0x20]; 6767 u8 match_dw_3[0x20]; 6768 u8 match_dw_2[0x20]; 6769 u8 match_dw_1[0x20]; 6770 u8 match_dw_0[0x20]; 6771 6772 u8 match_byte_7[0x8]; 6773 u8 match_byte_6[0x8]; 6774 u8 match_byte_5[0x8]; 6775 u8 match_byte_4[0x8]; 6776 6777 u8 match_byte_3[0x8]; 6778 u8 match_byte_2[0x8]; 6779 u8 match_byte_1[0x8]; 6780 u8 match_byte_0[0x8]; 6781 }; 6782 6783 struct mlx5_ifc_match_definer_bits { 6784 u8 modify_field_select[0x40]; 6785 6786 u8 reserved_at_40[0x40]; 6787 6788 u8 reserved_at_80[0x10]; 6789 u8 format_id[0x10]; 6790 6791 u8 reserved_at_a0[0x60]; 6792 6793 u8 format_select_dw3[0x8]; 6794 u8 format_select_dw2[0x8]; 6795 u8 format_select_dw1[0x8]; 6796 u8 format_select_dw0[0x8]; 6797 6798 u8 format_select_dw7[0x8]; 6799 u8 format_select_dw6[0x8]; 6800 u8 format_select_dw5[0x8]; 6801 u8 format_select_dw4[0x8]; 6802 6803 u8 reserved_at_100[0x18]; 6804 u8 format_select_dw8[0x8]; 6805 6806 u8 reserved_at_120[0x20]; 6807 6808 u8 format_select_byte3[0x8]; 6809 u8 format_select_byte2[0x8]; 6810 u8 format_select_byte1[0x8]; 6811 u8 format_select_byte0[0x8]; 6812 6813 u8 format_select_byte7[0x8]; 6814 u8 format_select_byte6[0x8]; 6815 u8 format_select_byte5[0x8]; 6816 u8 format_select_byte4[0x8]; 6817 6818 u8 reserved_at_180[0x40]; 6819 6820 union { 6821 struct { 6822 u8 match_mask[16][0x20]; 6823 }; 6824 struct mlx5_ifc_match_definer_match_mask_bits match_mask_format; 6825 }; 6826 }; 6827 6828 struct mlx5_ifc_general_obj_create_param_bits { 6829 u8 alias_object[0x1]; 6830 u8 reserved_at_1[0x2]; 6831 u8 log_obj_range[0x5]; 6832 u8 reserved_at_8[0x18]; 6833 }; 6834 6835 struct mlx5_ifc_general_obj_query_param_bits { 6836 u8 alias_object[0x1]; 6837 u8 obj_offset[0x1f]; 6838 }; 6839 6840 struct mlx5_ifc_general_obj_in_cmd_hdr_bits { 6841 u8 opcode[0x10]; 6842 u8 uid[0x10]; 6843 6844 u8 vhca_tunnel_id[0x10]; 6845 u8 obj_type[0x10]; 6846 6847 u8 obj_id[0x20]; 6848 6849 union { 6850 struct mlx5_ifc_general_obj_create_param_bits create; 6851 struct mlx5_ifc_general_obj_query_param_bits query; 6852 } op_param; 6853 }; 6854 6855 struct mlx5_ifc_general_obj_out_cmd_hdr_bits { 6856 u8 status[0x8]; 6857 u8 reserved_at_8[0x18]; 6858 6859 u8 syndrome[0x20]; 6860 6861 u8 obj_id[0x20]; 6862 6863 u8 reserved_at_60[0x20]; 6864 }; 6865 6866 struct mlx5_ifc_allow_other_vhca_access_in_bits { 6867 u8 opcode[0x10]; 6868 u8 uid[0x10]; 6869 u8 reserved_at_20[0x10]; 6870 u8 op_mod[0x10]; 6871 u8 reserved_at_40[0x50]; 6872 u8 object_type_to_be_accessed[0x10]; 6873 u8 object_id_to_be_accessed[0x20]; 6874 u8 reserved_at_c0[0x40]; 6875 union { 6876 u8 access_key_raw[0x100]; 6877 u8 access_key[8][0x20]; 6878 }; 6879 }; 6880 6881 struct mlx5_ifc_allow_other_vhca_access_out_bits { 6882 u8 status[0x8]; 6883 u8 reserved_at_8[0x18]; 6884 u8 syndrome[0x20]; 6885 u8 reserved_at_40[0x40]; 6886 }; 6887 6888 struct mlx5_ifc_modify_header_arg_bits { 6889 u8 reserved_at_0[0x80]; 6890 6891 u8 reserved_at_80[0x8]; 6892 u8 access_pd[0x18]; 6893 }; 6894 6895 struct mlx5_ifc_create_modify_header_arg_in_bits { 6896 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 6897 struct mlx5_ifc_modify_header_arg_bits arg; 6898 }; 6899 6900 struct mlx5_ifc_create_match_definer_in_bits { 6901 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 6902 6903 struct mlx5_ifc_match_definer_bits obj_context; 6904 }; 6905 6906 struct mlx5_ifc_create_match_definer_out_bits { 6907 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 6908 }; 6909 6910 struct mlx5_ifc_alias_context_bits { 6911 u8 vhca_id_to_be_accessed[0x10]; 6912 u8 reserved_at_10[0xd]; 6913 u8 status[0x3]; 6914 u8 object_id_to_be_accessed[0x20]; 6915 u8 reserved_at_40[0x40]; 6916 union { 6917 u8 access_key_raw[0x100]; 6918 u8 access_key[8][0x20]; 6919 }; 6920 u8 metadata[0x80]; 6921 }; 6922 6923 struct mlx5_ifc_create_alias_obj_in_bits { 6924 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 6925 struct mlx5_ifc_alias_context_bits alias_ctx; 6926 }; 6927 6928 enum { 6929 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 6930 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 6931 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 6932 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3, 6933 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_3 = 0x4, 6934 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_4 = 0x5, 6935 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_5 = 0x6, 6936 }; 6937 6938 struct mlx5_ifc_query_flow_group_out_bits { 6939 u8 status[0x8]; 6940 u8 reserved_at_8[0x18]; 6941 6942 u8 syndrome[0x20]; 6943 6944 u8 reserved_at_40[0xa0]; 6945 6946 u8 start_flow_index[0x20]; 6947 6948 u8 reserved_at_100[0x20]; 6949 6950 u8 end_flow_index[0x20]; 6951 6952 u8 reserved_at_140[0xa0]; 6953 6954 u8 reserved_at_1e0[0x18]; 6955 u8 match_criteria_enable[0x8]; 6956 6957 struct mlx5_ifc_fte_match_param_bits match_criteria; 6958 6959 u8 reserved_at_1200[0xe00]; 6960 }; 6961 6962 struct mlx5_ifc_query_flow_group_in_bits { 6963 u8 opcode[0x10]; 6964 u8 reserved_at_10[0x10]; 6965 6966 u8 reserved_at_20[0x10]; 6967 u8 op_mod[0x10]; 6968 6969 u8 reserved_at_40[0x40]; 6970 6971 u8 table_type[0x8]; 6972 u8 reserved_at_88[0x18]; 6973 6974 u8 reserved_at_a0[0x8]; 6975 u8 table_id[0x18]; 6976 6977 u8 group_id[0x20]; 6978 6979 u8 reserved_at_e0[0x120]; 6980 }; 6981 6982 struct mlx5_ifc_query_flow_counter_out_bits { 6983 u8 status[0x8]; 6984 u8 reserved_at_8[0x18]; 6985 6986 u8 syndrome[0x20]; 6987 6988 u8 reserved_at_40[0x40]; 6989 6990 struct mlx5_ifc_traffic_counter_bits flow_statistics[]; 6991 }; 6992 6993 struct mlx5_ifc_query_flow_counter_in_bits { 6994 u8 opcode[0x10]; 6995 u8 reserved_at_10[0x10]; 6996 6997 u8 reserved_at_20[0x10]; 6998 u8 op_mod[0x10]; 6999 7000 u8 reserved_at_40[0x80]; 7001 7002 u8 clear[0x1]; 7003 u8 reserved_at_c1[0xf]; 7004 u8 num_of_counters[0x10]; 7005 7006 u8 flow_counter_id[0x20]; 7007 }; 7008 7009 struct mlx5_ifc_query_esw_vport_context_out_bits { 7010 u8 status[0x8]; 7011 u8 reserved_at_8[0x18]; 7012 7013 u8 syndrome[0x20]; 7014 7015 u8 reserved_at_40[0x40]; 7016 7017 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 7018 }; 7019 7020 struct mlx5_ifc_query_esw_vport_context_in_bits { 7021 u8 opcode[0x10]; 7022 u8 reserved_at_10[0x10]; 7023 7024 u8 reserved_at_20[0x10]; 7025 u8 op_mod[0x10]; 7026 7027 u8 other_vport[0x1]; 7028 u8 reserved_at_41[0xf]; 7029 u8 vport_number[0x10]; 7030 7031 u8 reserved_at_60[0x20]; 7032 }; 7033 7034 struct mlx5_ifc_destroy_esw_vport_out_bits { 7035 u8 status[0x8]; 7036 u8 reserved_at_8[0x18]; 7037 7038 u8 syndrome[0x20]; 7039 7040 u8 reserved_at_40[0x20]; 7041 }; 7042 7043 struct mlx5_ifc_destroy_esw_vport_in_bits { 7044 u8 opcode[0x10]; 7045 u8 uid[0x10]; 7046 7047 u8 reserved_at_20[0x10]; 7048 u8 op_mod[0x10]; 7049 7050 u8 reserved_at_40[0x10]; 7051 u8 vport_num[0x10]; 7052 7053 u8 reserved_at_60[0x20]; 7054 }; 7055 7056 struct mlx5_ifc_modify_esw_vport_context_out_bits { 7057 u8 status[0x8]; 7058 u8 reserved_at_8[0x18]; 7059 7060 u8 syndrome[0x20]; 7061 7062 u8 reserved_at_40[0x40]; 7063 }; 7064 7065 struct mlx5_ifc_esw_vport_context_fields_select_bits { 7066 u8 reserved_at_0[0x1b]; 7067 u8 fdb_to_vport_reg_c_id[0x1]; 7068 u8 vport_cvlan_insert[0x1]; 7069 u8 vport_svlan_insert[0x1]; 7070 u8 vport_cvlan_strip[0x1]; 7071 u8 vport_svlan_strip[0x1]; 7072 }; 7073 7074 struct mlx5_ifc_modify_esw_vport_context_in_bits { 7075 u8 opcode[0x10]; 7076 u8 reserved_at_10[0x10]; 7077 7078 u8 reserved_at_20[0x10]; 7079 u8 op_mod[0x10]; 7080 7081 u8 other_vport[0x1]; 7082 u8 reserved_at_41[0xf]; 7083 u8 vport_number[0x10]; 7084 7085 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select; 7086 7087 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 7088 }; 7089 7090 struct mlx5_ifc_query_eq_out_bits { 7091 u8 status[0x8]; 7092 u8 reserved_at_8[0x18]; 7093 7094 u8 syndrome[0x20]; 7095 7096 u8 reserved_at_40[0x40]; 7097 7098 struct mlx5_ifc_eqc_bits eq_context_entry; 7099 7100 u8 reserved_at_280[0x40]; 7101 7102 u8 event_bitmask[0x40]; 7103 7104 u8 reserved_at_300[0x580]; 7105 7106 u8 pas[][0x40]; 7107 }; 7108 7109 struct mlx5_ifc_query_eq_in_bits { 7110 u8 opcode[0x10]; 7111 u8 reserved_at_10[0x10]; 7112 7113 u8 reserved_at_20[0x10]; 7114 u8 op_mod[0x10]; 7115 7116 u8 reserved_at_40[0x18]; 7117 u8 eq_number[0x8]; 7118 7119 u8 reserved_at_60[0x20]; 7120 }; 7121 7122 struct mlx5_ifc_packet_reformat_context_in_bits { 7123 u8 reformat_type[0x8]; 7124 u8 reserved_at_8[0x4]; 7125 u8 reformat_param_0[0x4]; 7126 u8 reserved_at_10[0x6]; 7127 u8 reformat_data_size[0xa]; 7128 7129 u8 reformat_param_1[0x8]; 7130 u8 reserved_at_28[0x8]; 7131 u8 reformat_data[2][0x8]; 7132 7133 u8 more_reformat_data[][0x8]; 7134 }; 7135 7136 struct mlx5_ifc_query_packet_reformat_context_out_bits { 7137 u8 status[0x8]; 7138 u8 reserved_at_8[0x18]; 7139 7140 u8 syndrome[0x20]; 7141 7142 u8 reserved_at_40[0xa0]; 7143 7144 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context[]; 7145 }; 7146 7147 struct mlx5_ifc_query_packet_reformat_context_in_bits { 7148 u8 opcode[0x10]; 7149 u8 reserved_at_10[0x10]; 7150 7151 u8 reserved_at_20[0x10]; 7152 u8 op_mod[0x10]; 7153 7154 u8 packet_reformat_id[0x20]; 7155 7156 u8 reserved_at_60[0xa0]; 7157 }; 7158 7159 struct mlx5_ifc_alloc_packet_reformat_context_out_bits { 7160 u8 status[0x8]; 7161 u8 reserved_at_8[0x18]; 7162 7163 u8 syndrome[0x20]; 7164 7165 u8 packet_reformat_id[0x20]; 7166 7167 u8 reserved_at_60[0x20]; 7168 }; 7169 7170 enum { 7171 MLX5_REFORMAT_CONTEXT_ANCHOR_MAC_START = 0x1, 7172 MLX5_REFORMAT_CONTEXT_ANCHOR_VLAN_START = 0x2, 7173 MLX5_REFORMAT_CONTEXT_ANCHOR_IP_START = 0x7, 7174 MLX5_REFORMAT_CONTEXT_ANCHOR_TCP_UDP_START = 0x9, 7175 }; 7176 7177 enum mlx5_reformat_ctx_type { 7178 MLX5_REFORMAT_TYPE_L2_TO_VXLAN = 0x0, 7179 MLX5_REFORMAT_TYPE_L2_TO_NVGRE = 0x1, 7180 MLX5_REFORMAT_TYPE_L2_TO_L2_TUNNEL = 0x2, 7181 MLX5_REFORMAT_TYPE_L3_TUNNEL_TO_L2 = 0x3, 7182 MLX5_REFORMAT_TYPE_L2_TO_L3_TUNNEL = 0x4, 7183 MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_IPV4 = 0x5, 7184 MLX5_REFORMAT_TYPE_L2_TO_L3_ESP_TUNNEL = 0x6, 7185 MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_UDPV4 = 0x7, 7186 MLX5_REFORMAT_TYPE_DEL_ESP_TRANSPORT = 0x8, 7187 MLX5_REFORMAT_TYPE_L3_ESP_TUNNEL_TO_L2 = 0x9, 7188 MLX5_REFORMAT_TYPE_DEL_ESP_TRANSPORT_OVER_UDP = 0xa, 7189 MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_IPV6 = 0xb, 7190 MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_UDPV6 = 0xc, 7191 MLX5_REFORMAT_TYPE_ADD_PSP_TUNNEL = 0xd, 7192 MLX5_REFORMAT_TYPE_DEL_PSP_TUNNEL = 0xe, 7193 MLX5_REFORMAT_TYPE_INSERT_HDR = 0xf, 7194 MLX5_REFORMAT_TYPE_REMOVE_HDR = 0x10, 7195 MLX5_REFORMAT_TYPE_ADD_MACSEC = 0x11, 7196 MLX5_REFORMAT_TYPE_DEL_MACSEC = 0x12, 7197 }; 7198 7199 struct mlx5_ifc_alloc_packet_reformat_context_in_bits { 7200 u8 opcode[0x10]; 7201 u8 reserved_at_10[0x10]; 7202 7203 u8 reserved_at_20[0x10]; 7204 u8 op_mod[0x10]; 7205 7206 u8 reserved_at_40[0xa0]; 7207 7208 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context; 7209 }; 7210 7211 struct mlx5_ifc_dealloc_packet_reformat_context_out_bits { 7212 u8 status[0x8]; 7213 u8 reserved_at_8[0x18]; 7214 7215 u8 syndrome[0x20]; 7216 7217 u8 reserved_at_40[0x40]; 7218 }; 7219 7220 struct mlx5_ifc_dealloc_packet_reformat_context_in_bits { 7221 u8 opcode[0x10]; 7222 u8 reserved_at_10[0x10]; 7223 7224 u8 reserved_20[0x10]; 7225 u8 op_mod[0x10]; 7226 7227 u8 packet_reformat_id[0x20]; 7228 7229 u8 reserved_60[0x20]; 7230 }; 7231 7232 struct mlx5_ifc_set_action_in_bits { 7233 u8 action_type[0x4]; 7234 u8 field[0xc]; 7235 u8 reserved_at_10[0x3]; 7236 u8 offset[0x5]; 7237 u8 reserved_at_18[0x3]; 7238 u8 length[0x5]; 7239 7240 u8 data[0x20]; 7241 }; 7242 7243 struct mlx5_ifc_add_action_in_bits { 7244 u8 action_type[0x4]; 7245 u8 field[0xc]; 7246 u8 reserved_at_10[0x10]; 7247 7248 u8 data[0x20]; 7249 }; 7250 7251 struct mlx5_ifc_copy_action_in_bits { 7252 u8 action_type[0x4]; 7253 u8 src_field[0xc]; 7254 u8 reserved_at_10[0x3]; 7255 u8 src_offset[0x5]; 7256 u8 reserved_at_18[0x3]; 7257 u8 length[0x5]; 7258 7259 u8 reserved_at_20[0x4]; 7260 u8 dst_field[0xc]; 7261 u8 reserved_at_30[0x3]; 7262 u8 dst_offset[0x5]; 7263 u8 reserved_at_38[0x8]; 7264 }; 7265 7266 union mlx5_ifc_set_add_copy_action_in_auto_bits { 7267 struct mlx5_ifc_set_action_in_bits set_action_in; 7268 struct mlx5_ifc_add_action_in_bits add_action_in; 7269 struct mlx5_ifc_copy_action_in_bits copy_action_in; 7270 u8 reserved_at_0[0x40]; 7271 }; 7272 7273 enum { 7274 MLX5_ACTION_TYPE_SET = 0x1, 7275 MLX5_ACTION_TYPE_ADD = 0x2, 7276 MLX5_ACTION_TYPE_COPY = 0x3, 7277 }; 7278 7279 enum { 7280 MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16 = 0x1, 7281 MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0 = 0x2, 7282 MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE = 0x3, 7283 MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16 = 0x4, 7284 MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0 = 0x5, 7285 MLX5_ACTION_IN_FIELD_OUT_IP_DSCP = 0x6, 7286 MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS = 0x7, 7287 MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT = 0x8, 7288 MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT = 0x9, 7289 MLX5_ACTION_IN_FIELD_OUT_IP_TTL = 0xa, 7290 MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT = 0xb, 7291 MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT = 0xc, 7292 MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96 = 0xd, 7293 MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64 = 0xe, 7294 MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32 = 0xf, 7295 MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0 = 0x10, 7296 MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96 = 0x11, 7297 MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64 = 0x12, 7298 MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32 = 0x13, 7299 MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0 = 0x14, 7300 MLX5_ACTION_IN_FIELD_OUT_SIPV4 = 0x15, 7301 MLX5_ACTION_IN_FIELD_OUT_DIPV4 = 0x16, 7302 MLX5_ACTION_IN_FIELD_OUT_FIRST_VID = 0x17, 7303 MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47, 7304 MLX5_ACTION_IN_FIELD_METADATA_REG_A = 0x49, 7305 MLX5_ACTION_IN_FIELD_METADATA_REG_B = 0x50, 7306 MLX5_ACTION_IN_FIELD_METADATA_REG_C_0 = 0x51, 7307 MLX5_ACTION_IN_FIELD_METADATA_REG_C_1 = 0x52, 7308 MLX5_ACTION_IN_FIELD_METADATA_REG_C_2 = 0x53, 7309 MLX5_ACTION_IN_FIELD_METADATA_REG_C_3 = 0x54, 7310 MLX5_ACTION_IN_FIELD_METADATA_REG_C_4 = 0x55, 7311 MLX5_ACTION_IN_FIELD_METADATA_REG_C_5 = 0x56, 7312 MLX5_ACTION_IN_FIELD_METADATA_REG_C_6 = 0x57, 7313 MLX5_ACTION_IN_FIELD_METADATA_REG_C_7 = 0x58, 7314 MLX5_ACTION_IN_FIELD_OUT_TCP_SEQ_NUM = 0x59, 7315 MLX5_ACTION_IN_FIELD_OUT_TCP_ACK_NUM = 0x5B, 7316 MLX5_ACTION_IN_FIELD_IPSEC_SYNDROME = 0x5D, 7317 MLX5_ACTION_IN_FIELD_OUT_EMD_47_32 = 0x6F, 7318 MLX5_ACTION_IN_FIELD_OUT_EMD_31_0 = 0x70, 7319 MLX5_ACTION_IN_FIELD_PSP_SYNDROME = 0x71, 7320 }; 7321 7322 struct mlx5_ifc_alloc_modify_header_context_out_bits { 7323 u8 status[0x8]; 7324 u8 reserved_at_8[0x18]; 7325 7326 u8 syndrome[0x20]; 7327 7328 u8 modify_header_id[0x20]; 7329 7330 u8 reserved_at_60[0x20]; 7331 }; 7332 7333 struct mlx5_ifc_alloc_modify_header_context_in_bits { 7334 u8 opcode[0x10]; 7335 u8 reserved_at_10[0x10]; 7336 7337 u8 reserved_at_20[0x10]; 7338 u8 op_mod[0x10]; 7339 7340 u8 reserved_at_40[0x20]; 7341 7342 u8 table_type[0x8]; 7343 u8 reserved_at_68[0x10]; 7344 u8 num_of_actions[0x8]; 7345 7346 union mlx5_ifc_set_add_copy_action_in_auto_bits actions[]; 7347 }; 7348 7349 struct mlx5_ifc_dealloc_modify_header_context_out_bits { 7350 u8 status[0x8]; 7351 u8 reserved_at_8[0x18]; 7352 7353 u8 syndrome[0x20]; 7354 7355 u8 reserved_at_40[0x40]; 7356 }; 7357 7358 struct mlx5_ifc_dealloc_modify_header_context_in_bits { 7359 u8 opcode[0x10]; 7360 u8 reserved_at_10[0x10]; 7361 7362 u8 reserved_at_20[0x10]; 7363 u8 op_mod[0x10]; 7364 7365 u8 modify_header_id[0x20]; 7366 7367 u8 reserved_at_60[0x20]; 7368 }; 7369 7370 struct mlx5_ifc_query_modify_header_context_in_bits { 7371 u8 opcode[0x10]; 7372 u8 uid[0x10]; 7373 7374 u8 reserved_at_20[0x10]; 7375 u8 op_mod[0x10]; 7376 7377 u8 modify_header_id[0x20]; 7378 7379 u8 reserved_at_60[0xa0]; 7380 }; 7381 7382 struct mlx5_ifc_query_dct_out_bits { 7383 u8 status[0x8]; 7384 u8 reserved_at_8[0x18]; 7385 7386 u8 syndrome[0x20]; 7387 7388 u8 reserved_at_40[0x40]; 7389 7390 struct mlx5_ifc_dctc_bits dct_context_entry; 7391 7392 u8 reserved_at_280[0x180]; 7393 }; 7394 7395 struct mlx5_ifc_query_dct_in_bits { 7396 u8 opcode[0x10]; 7397 u8 reserved_at_10[0x10]; 7398 7399 u8 reserved_at_20[0x10]; 7400 u8 op_mod[0x10]; 7401 7402 u8 reserved_at_40[0x8]; 7403 u8 dctn[0x18]; 7404 7405 u8 reserved_at_60[0x20]; 7406 }; 7407 7408 struct mlx5_ifc_query_cq_out_bits { 7409 u8 status[0x8]; 7410 u8 reserved_at_8[0x18]; 7411 7412 u8 syndrome[0x20]; 7413 7414 u8 reserved_at_40[0x40]; 7415 7416 struct mlx5_ifc_cqc_bits cq_context; 7417 7418 u8 reserved_at_280[0x600]; 7419 7420 u8 pas[][0x40]; 7421 }; 7422 7423 struct mlx5_ifc_query_cq_in_bits { 7424 u8 opcode[0x10]; 7425 u8 reserved_at_10[0x10]; 7426 7427 u8 reserved_at_20[0x10]; 7428 u8 op_mod[0x10]; 7429 7430 u8 reserved_at_40[0x8]; 7431 u8 cqn[0x18]; 7432 7433 u8 reserved_at_60[0x20]; 7434 }; 7435 7436 struct mlx5_ifc_query_cong_status_out_bits { 7437 u8 status[0x8]; 7438 u8 reserved_at_8[0x18]; 7439 7440 u8 syndrome[0x20]; 7441 7442 u8 reserved_at_40[0x20]; 7443 7444 u8 enable[0x1]; 7445 u8 tag_enable[0x1]; 7446 u8 reserved_at_62[0x1e]; 7447 }; 7448 7449 struct mlx5_ifc_query_cong_status_in_bits { 7450 u8 opcode[0x10]; 7451 u8 reserved_at_10[0x10]; 7452 7453 u8 reserved_at_20[0x10]; 7454 u8 op_mod[0x10]; 7455 7456 u8 reserved_at_40[0x18]; 7457 u8 priority[0x4]; 7458 u8 cong_protocol[0x4]; 7459 7460 u8 reserved_at_60[0x20]; 7461 }; 7462 7463 struct mlx5_ifc_query_cong_statistics_out_bits { 7464 u8 status[0x8]; 7465 u8 reserved_at_8[0x18]; 7466 7467 u8 syndrome[0x20]; 7468 7469 u8 reserved_at_40[0x40]; 7470 7471 u8 rp_cur_flows[0x20]; 7472 7473 u8 sum_flows[0x20]; 7474 7475 u8 rp_cnp_ignored_high[0x20]; 7476 7477 u8 rp_cnp_ignored_low[0x20]; 7478 7479 u8 rp_cnp_handled_high[0x20]; 7480 7481 u8 rp_cnp_handled_low[0x20]; 7482 7483 u8 reserved_at_140[0x100]; 7484 7485 u8 time_stamp_high[0x20]; 7486 7487 u8 time_stamp_low[0x20]; 7488 7489 u8 accumulators_period[0x20]; 7490 7491 u8 np_ecn_marked_roce_packets_high[0x20]; 7492 7493 u8 np_ecn_marked_roce_packets_low[0x20]; 7494 7495 u8 np_cnp_sent_high[0x20]; 7496 7497 u8 np_cnp_sent_low[0x20]; 7498 7499 u8 reserved_at_320[0x560]; 7500 }; 7501 7502 struct mlx5_ifc_query_cong_statistics_in_bits { 7503 u8 opcode[0x10]; 7504 u8 reserved_at_10[0x10]; 7505 7506 u8 reserved_at_20[0x10]; 7507 u8 op_mod[0x10]; 7508 7509 u8 clear[0x1]; 7510 u8 reserved_at_41[0x1f]; 7511 7512 u8 reserved_at_60[0x20]; 7513 }; 7514 7515 struct mlx5_ifc_query_cong_params_out_bits { 7516 u8 status[0x8]; 7517 u8 reserved_at_8[0x18]; 7518 7519 u8 syndrome[0x20]; 7520 7521 u8 reserved_at_40[0x40]; 7522 7523 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 7524 }; 7525 7526 struct mlx5_ifc_query_cong_params_in_bits { 7527 u8 opcode[0x10]; 7528 u8 reserved_at_10[0x10]; 7529 7530 u8 reserved_at_20[0x10]; 7531 u8 op_mod[0x10]; 7532 7533 u8 reserved_at_40[0x1c]; 7534 u8 cong_protocol[0x4]; 7535 7536 u8 reserved_at_60[0x20]; 7537 }; 7538 7539 struct mlx5_ifc_query_adapter_out_bits { 7540 u8 status[0x8]; 7541 u8 reserved_at_8[0x18]; 7542 7543 u8 syndrome[0x20]; 7544 7545 u8 reserved_at_40[0x40]; 7546 7547 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct; 7548 }; 7549 7550 struct mlx5_ifc_query_adapter_in_bits { 7551 u8 opcode[0x10]; 7552 u8 reserved_at_10[0x10]; 7553 7554 u8 reserved_at_20[0x10]; 7555 u8 op_mod[0x10]; 7556 7557 u8 reserved_at_40[0x40]; 7558 }; 7559 7560 struct mlx5_ifc_function_vhca_rid_info_reg_bits { 7561 u8 host_number[0x8]; 7562 u8 host_pci_device_function[0x8]; 7563 u8 host_pci_bus[0x8]; 7564 u8 reserved_at_18[0x3]; 7565 u8 pci_bus_assigned[0x1]; 7566 u8 function_type[0x4]; 7567 7568 u8 parent_pci_device_function[0x8]; 7569 u8 parent_pci_bus[0x8]; 7570 u8 vhca_id[0x10]; 7571 7572 u8 reserved_at_40[0x10]; 7573 u8 function_id[0x10]; 7574 7575 u8 reserved_at_60[0x20]; 7576 }; 7577 7578 struct mlx5_ifc_delegated_function_vhca_rid_info_bits { 7579 struct mlx5_ifc_function_vhca_rid_info_reg_bits function_vhca_rid_info; 7580 7581 u8 reserved_at_80[0x18]; 7582 u8 manage_profile[0x8]; 7583 7584 u8 reserved_at_a0[0x60]; 7585 }; 7586 7587 struct mlx5_ifc_query_delegated_vhca_out_bits { 7588 u8 status[0x8]; 7589 u8 reserved_at_8[0x18]; 7590 7591 u8 syndrome[0x20]; 7592 7593 u8 reserved_at_40[0x20]; 7594 7595 u8 reserved_at_60[0x10]; 7596 u8 functions_count[0x10]; 7597 7598 u8 reserved_at_80[0x80]; 7599 7600 struct mlx5_ifc_delegated_function_vhca_rid_info_bits 7601 delegated_function_vhca_rid_info[]; 7602 }; 7603 7604 struct mlx5_ifc_query_delegated_vhca_in_bits { 7605 u8 opcode[0x10]; 7606 u8 uid[0x10]; 7607 7608 u8 reserved_at_20[0x10]; 7609 u8 op_mod[0x10]; 7610 7611 u8 reserved_at_40[0x40]; 7612 }; 7613 7614 struct mlx5_ifc_create_esw_vport_out_bits { 7615 u8 status[0x8]; 7616 u8 reserved_at_8[0x18]; 7617 7618 u8 syndrome[0x20]; 7619 7620 u8 reserved_at_40[0x20]; 7621 7622 u8 reserved_at_60[0x10]; 7623 u8 vport_num[0x10]; 7624 }; 7625 7626 struct mlx5_ifc_create_esw_vport_in_bits { 7627 u8 opcode[0x10]; 7628 u8 reserved_at_10[0x10]; 7629 7630 u8 reserved_at_20[0x10]; 7631 u8 op_mod[0x10]; 7632 7633 u8 reserved_at_40[0x10]; 7634 u8 managed_vhca_id[0x10]; 7635 7636 u8 reserved_at_60[0x20]; 7637 }; 7638 7639 struct mlx5_ifc_qp_2rst_out_bits { 7640 u8 status[0x8]; 7641 u8 reserved_at_8[0x18]; 7642 7643 u8 syndrome[0x20]; 7644 7645 u8 reserved_at_40[0x40]; 7646 }; 7647 7648 struct mlx5_ifc_qp_2rst_in_bits { 7649 u8 opcode[0x10]; 7650 u8 uid[0x10]; 7651 7652 u8 reserved_at_20[0x10]; 7653 u8 op_mod[0x10]; 7654 7655 u8 reserved_at_40[0x8]; 7656 u8 qpn[0x18]; 7657 7658 u8 reserved_at_60[0x20]; 7659 }; 7660 7661 struct mlx5_ifc_qp_2err_out_bits { 7662 u8 status[0x8]; 7663 u8 reserved_at_8[0x18]; 7664 7665 u8 syndrome[0x20]; 7666 7667 u8 reserved_at_40[0x40]; 7668 }; 7669 7670 struct mlx5_ifc_qp_2err_in_bits { 7671 u8 opcode[0x10]; 7672 u8 uid[0x10]; 7673 7674 u8 reserved_at_20[0x10]; 7675 u8 op_mod[0x10]; 7676 7677 u8 reserved_at_40[0x8]; 7678 u8 qpn[0x18]; 7679 7680 u8 reserved_at_60[0x20]; 7681 }; 7682 7683 struct mlx5_ifc_trans_page_fault_info_bits { 7684 u8 error[0x1]; 7685 u8 reserved_at_1[0x4]; 7686 u8 page_fault_type[0x3]; 7687 u8 wq_number[0x18]; 7688 7689 u8 reserved_at_20[0x8]; 7690 u8 fault_token[0x18]; 7691 }; 7692 7693 struct mlx5_ifc_mem_page_fault_info_bits { 7694 u8 error[0x1]; 7695 u8 reserved_at_1[0xf]; 7696 u8 fault_token_47_32[0x10]; 7697 7698 u8 fault_token_31_0[0x20]; 7699 }; 7700 7701 union mlx5_ifc_page_fault_resume_in_page_fault_info_auto_bits { 7702 struct mlx5_ifc_trans_page_fault_info_bits trans_page_fault_info; 7703 struct mlx5_ifc_mem_page_fault_info_bits mem_page_fault_info; 7704 u8 reserved_at_0[0x40]; 7705 }; 7706 7707 struct mlx5_ifc_page_fault_resume_out_bits { 7708 u8 status[0x8]; 7709 u8 reserved_at_8[0x18]; 7710 7711 u8 syndrome[0x20]; 7712 7713 u8 reserved_at_40[0x40]; 7714 }; 7715 7716 struct mlx5_ifc_page_fault_resume_in_bits { 7717 u8 opcode[0x10]; 7718 u8 reserved_at_10[0x10]; 7719 7720 u8 reserved_at_20[0x10]; 7721 u8 op_mod[0x10]; 7722 7723 union mlx5_ifc_page_fault_resume_in_page_fault_info_auto_bits 7724 page_fault_info; 7725 }; 7726 7727 struct mlx5_ifc_nop_out_bits { 7728 u8 status[0x8]; 7729 u8 reserved_at_8[0x18]; 7730 7731 u8 syndrome[0x20]; 7732 7733 u8 reserved_at_40[0x40]; 7734 }; 7735 7736 struct mlx5_ifc_nop_in_bits { 7737 u8 opcode[0x10]; 7738 u8 reserved_at_10[0x10]; 7739 7740 u8 reserved_at_20[0x10]; 7741 u8 op_mod[0x10]; 7742 7743 u8 reserved_at_40[0x40]; 7744 }; 7745 7746 struct mlx5_ifc_modify_vport_state_out_bits { 7747 u8 status[0x8]; 7748 u8 reserved_at_8[0x18]; 7749 7750 u8 syndrome[0x20]; 7751 7752 u8 reserved_at_40[0x40]; 7753 }; 7754 7755 struct mlx5_ifc_modify_vport_state_in_bits { 7756 u8 opcode[0x10]; 7757 u8 reserved_at_10[0x10]; 7758 7759 u8 reserved_at_20[0x10]; 7760 u8 op_mod[0x10]; 7761 7762 u8 other_vport[0x1]; 7763 u8 reserved_at_41[0xf]; 7764 u8 vport_number[0x10]; 7765 7766 u8 reserved_at_60[0x10]; 7767 u8 ingress_connect[0x1]; 7768 u8 egress_connect[0x1]; 7769 u8 ingress_connect_valid[0x1]; 7770 u8 egress_connect_valid[0x1]; 7771 u8 reserved_at_74[0x4]; 7772 u8 admin_state[0x4]; 7773 u8 reserved_at_7c[0x4]; 7774 }; 7775 7776 struct mlx5_ifc_modify_tis_out_bits { 7777 u8 status[0x8]; 7778 u8 reserved_at_8[0x18]; 7779 7780 u8 syndrome[0x20]; 7781 7782 u8 reserved_at_40[0x40]; 7783 }; 7784 7785 struct mlx5_ifc_modify_tis_bitmask_bits { 7786 u8 reserved_at_0[0x20]; 7787 7788 u8 reserved_at_20[0x1d]; 7789 u8 lag_tx_port_affinity[0x1]; 7790 u8 strict_lag_tx_port_affinity[0x1]; 7791 u8 prio[0x1]; 7792 }; 7793 7794 struct mlx5_ifc_modify_tis_in_bits { 7795 u8 opcode[0x10]; 7796 u8 uid[0x10]; 7797 7798 u8 reserved_at_20[0x10]; 7799 u8 op_mod[0x10]; 7800 7801 u8 reserved_at_40[0x8]; 7802 u8 tisn[0x18]; 7803 7804 u8 reserved_at_60[0x20]; 7805 7806 struct mlx5_ifc_modify_tis_bitmask_bits bitmask; 7807 7808 u8 reserved_at_c0[0x40]; 7809 7810 struct mlx5_ifc_tisc_bits ctx; 7811 }; 7812 7813 struct mlx5_ifc_modify_tir_bitmask_bits { 7814 u8 reserved_at_0[0x20]; 7815 7816 u8 reserved_at_20[0x1b]; 7817 u8 self_lb_en[0x1]; 7818 u8 reserved_at_3c[0x1]; 7819 u8 hash[0x1]; 7820 u8 reserved_at_3e[0x1]; 7821 u8 packet_merge[0x1]; 7822 }; 7823 7824 struct mlx5_ifc_modify_tir_out_bits { 7825 u8 status[0x8]; 7826 u8 reserved_at_8[0x18]; 7827 7828 u8 syndrome[0x20]; 7829 7830 u8 reserved_at_40[0x40]; 7831 }; 7832 7833 struct mlx5_ifc_modify_tir_in_bits { 7834 u8 opcode[0x10]; 7835 u8 uid[0x10]; 7836 7837 u8 reserved_at_20[0x10]; 7838 u8 op_mod[0x10]; 7839 7840 u8 reserved_at_40[0x8]; 7841 u8 tirn[0x18]; 7842 7843 u8 reserved_at_60[0x20]; 7844 7845 struct mlx5_ifc_modify_tir_bitmask_bits bitmask; 7846 7847 u8 reserved_at_c0[0x40]; 7848 7849 struct mlx5_ifc_tirc_bits ctx; 7850 }; 7851 7852 struct mlx5_ifc_modify_sq_out_bits { 7853 u8 status[0x8]; 7854 u8 reserved_at_8[0x18]; 7855 7856 u8 syndrome[0x20]; 7857 7858 u8 reserved_at_40[0x40]; 7859 }; 7860 7861 struct mlx5_ifc_modify_sq_in_bits { 7862 u8 opcode[0x10]; 7863 u8 uid[0x10]; 7864 7865 u8 reserved_at_20[0x10]; 7866 u8 op_mod[0x10]; 7867 7868 u8 sq_state[0x4]; 7869 u8 reserved_at_44[0x4]; 7870 u8 sqn[0x18]; 7871 7872 u8 reserved_at_60[0x20]; 7873 7874 u8 modify_bitmask[0x40]; 7875 7876 u8 reserved_at_c0[0x40]; 7877 7878 struct mlx5_ifc_sqc_bits ctx; 7879 }; 7880 7881 struct mlx5_ifc_modify_scheduling_element_out_bits { 7882 u8 status[0x8]; 7883 u8 reserved_at_8[0x18]; 7884 7885 u8 syndrome[0x20]; 7886 7887 u8 reserved_at_40[0x1c0]; 7888 }; 7889 7890 enum { 7891 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1, 7892 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2, 7893 }; 7894 7895 struct mlx5_ifc_modify_scheduling_element_in_bits { 7896 u8 opcode[0x10]; 7897 u8 reserved_at_10[0x10]; 7898 7899 u8 reserved_at_20[0x10]; 7900 u8 op_mod[0x10]; 7901 7902 u8 scheduling_hierarchy[0x8]; 7903 u8 reserved_at_48[0x18]; 7904 7905 u8 scheduling_element_id[0x20]; 7906 7907 u8 reserved_at_80[0x20]; 7908 7909 u8 modify_bitmask[0x20]; 7910 7911 u8 reserved_at_c0[0x40]; 7912 7913 struct mlx5_ifc_scheduling_context_bits scheduling_context; 7914 7915 u8 reserved_at_300[0x100]; 7916 }; 7917 7918 struct mlx5_ifc_modify_rqt_out_bits { 7919 u8 status[0x8]; 7920 u8 reserved_at_8[0x18]; 7921 7922 u8 syndrome[0x20]; 7923 7924 u8 reserved_at_40[0x40]; 7925 }; 7926 7927 struct mlx5_ifc_rqt_bitmask_bits { 7928 u8 reserved_at_0[0x20]; 7929 7930 u8 reserved_at_20[0x1f]; 7931 u8 rqn_list[0x1]; 7932 }; 7933 7934 struct mlx5_ifc_modify_rqt_in_bits { 7935 u8 opcode[0x10]; 7936 u8 uid[0x10]; 7937 7938 u8 reserved_at_20[0x10]; 7939 u8 op_mod[0x10]; 7940 7941 u8 reserved_at_40[0x8]; 7942 u8 rqtn[0x18]; 7943 7944 u8 reserved_at_60[0x20]; 7945 7946 struct mlx5_ifc_rqt_bitmask_bits bitmask; 7947 7948 u8 reserved_at_c0[0x40]; 7949 7950 struct mlx5_ifc_rqtc_bits ctx; 7951 }; 7952 7953 struct mlx5_ifc_modify_rq_out_bits { 7954 u8 status[0x8]; 7955 u8 reserved_at_8[0x18]; 7956 7957 u8 syndrome[0x20]; 7958 7959 u8 reserved_at_40[0x40]; 7960 }; 7961 7962 enum { 7963 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1, 7964 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2, 7965 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3, 7966 }; 7967 7968 struct mlx5_ifc_modify_rq_in_bits { 7969 u8 opcode[0x10]; 7970 u8 uid[0x10]; 7971 7972 u8 reserved_at_20[0x10]; 7973 u8 op_mod[0x10]; 7974 7975 u8 rq_state[0x4]; 7976 u8 reserved_at_44[0x4]; 7977 u8 rqn[0x18]; 7978 7979 u8 reserved_at_60[0x20]; 7980 7981 u8 modify_bitmask[0x40]; 7982 7983 u8 reserved_at_c0[0x40]; 7984 7985 struct mlx5_ifc_rqc_bits ctx; 7986 }; 7987 7988 struct mlx5_ifc_modify_rmp_out_bits { 7989 u8 status[0x8]; 7990 u8 reserved_at_8[0x18]; 7991 7992 u8 syndrome[0x20]; 7993 7994 u8 reserved_at_40[0x40]; 7995 }; 7996 7997 struct mlx5_ifc_rmp_bitmask_bits { 7998 u8 reserved_at_0[0x20]; 7999 8000 u8 reserved_at_20[0x1f]; 8001 u8 lwm[0x1]; 8002 }; 8003 8004 struct mlx5_ifc_modify_rmp_in_bits { 8005 u8 opcode[0x10]; 8006 u8 uid[0x10]; 8007 8008 u8 reserved_at_20[0x10]; 8009 u8 op_mod[0x10]; 8010 8011 u8 rmp_state[0x4]; 8012 u8 reserved_at_44[0x4]; 8013 u8 rmpn[0x18]; 8014 8015 u8 reserved_at_60[0x20]; 8016 8017 struct mlx5_ifc_rmp_bitmask_bits bitmask; 8018 8019 u8 reserved_at_c0[0x40]; 8020 8021 struct mlx5_ifc_rmpc_bits ctx; 8022 }; 8023 8024 struct mlx5_ifc_modify_nic_vport_context_out_bits { 8025 u8 status[0x8]; 8026 u8 reserved_at_8[0x18]; 8027 8028 u8 syndrome[0x20]; 8029 8030 u8 reserved_at_40[0x40]; 8031 }; 8032 8033 struct mlx5_ifc_modify_nic_vport_field_select_bits { 8034 u8 reserved_at_0[0x12]; 8035 u8 affiliation[0x1]; 8036 u8 reserved_at_13[0x1]; 8037 u8 disable_uc_local_lb[0x1]; 8038 u8 disable_mc_local_lb[0x1]; 8039 u8 node_guid[0x1]; 8040 u8 port_guid[0x1]; 8041 u8 min_inline[0x1]; 8042 u8 mtu[0x1]; 8043 u8 change_event[0x1]; 8044 u8 promisc[0x1]; 8045 u8 permanent_address[0x1]; 8046 u8 addresses_list[0x1]; 8047 u8 roce_en[0x1]; 8048 u8 reserved_at_1f[0x1]; 8049 }; 8050 8051 struct mlx5_ifc_modify_nic_vport_context_in_bits { 8052 u8 opcode[0x10]; 8053 u8 reserved_at_10[0x10]; 8054 8055 u8 reserved_at_20[0x10]; 8056 u8 op_mod[0x10]; 8057 8058 u8 other_vport[0x1]; 8059 u8 reserved_at_41[0xf]; 8060 u8 vport_number[0x10]; 8061 8062 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select; 8063 8064 u8 reserved_at_80[0x780]; 8065 8066 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 8067 }; 8068 8069 struct mlx5_ifc_modify_hca_vport_context_out_bits { 8070 u8 status[0x8]; 8071 u8 reserved_at_8[0x18]; 8072 8073 u8 syndrome[0x20]; 8074 8075 u8 reserved_at_40[0x40]; 8076 }; 8077 8078 struct mlx5_ifc_modify_hca_vport_context_in_bits { 8079 u8 opcode[0x10]; 8080 u8 reserved_at_10[0x10]; 8081 8082 u8 reserved_at_20[0x10]; 8083 u8 op_mod[0x10]; 8084 8085 u8 other_vport[0x1]; 8086 u8 reserved_at_41[0xb]; 8087 u8 port_num[0x4]; 8088 u8 vport_number[0x10]; 8089 8090 u8 reserved_at_60[0x20]; 8091 8092 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 8093 }; 8094 8095 struct mlx5_ifc_modify_cq_out_bits { 8096 u8 status[0x8]; 8097 u8 reserved_at_8[0x18]; 8098 8099 u8 syndrome[0x20]; 8100 8101 u8 reserved_at_40[0x40]; 8102 }; 8103 8104 enum { 8105 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0, 8106 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1, 8107 }; 8108 8109 struct mlx5_ifc_modify_cq_in_bits { 8110 u8 opcode[0x10]; 8111 u8 uid[0x10]; 8112 8113 u8 reserved_at_20[0x10]; 8114 u8 op_mod[0x10]; 8115 8116 u8 reserved_at_40[0x8]; 8117 u8 cqn[0x18]; 8118 8119 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select; 8120 8121 struct mlx5_ifc_cqc_bits cq_context; 8122 8123 u8 reserved_at_280[0x60]; 8124 8125 u8 cq_umem_valid[0x1]; 8126 u8 reserved_at_2e1[0x1f]; 8127 8128 u8 reserved_at_300[0x580]; 8129 8130 u8 pas[][0x40]; 8131 }; 8132 8133 struct mlx5_ifc_modify_cong_status_out_bits { 8134 u8 status[0x8]; 8135 u8 reserved_at_8[0x18]; 8136 8137 u8 syndrome[0x20]; 8138 8139 u8 reserved_at_40[0x40]; 8140 }; 8141 8142 struct mlx5_ifc_modify_cong_status_in_bits { 8143 u8 opcode[0x10]; 8144 u8 reserved_at_10[0x10]; 8145 8146 u8 reserved_at_20[0x10]; 8147 u8 op_mod[0x10]; 8148 8149 u8 reserved_at_40[0x18]; 8150 u8 priority[0x4]; 8151 u8 cong_protocol[0x4]; 8152 8153 u8 enable[0x1]; 8154 u8 tag_enable[0x1]; 8155 u8 reserved_at_62[0x1e]; 8156 }; 8157 8158 struct mlx5_ifc_modify_cong_params_out_bits { 8159 u8 status[0x8]; 8160 u8 reserved_at_8[0x18]; 8161 8162 u8 syndrome[0x20]; 8163 8164 u8 reserved_at_40[0x40]; 8165 }; 8166 8167 struct mlx5_ifc_modify_cong_params_in_bits { 8168 u8 opcode[0x10]; 8169 u8 reserved_at_10[0x10]; 8170 8171 u8 reserved_at_20[0x10]; 8172 u8 op_mod[0x10]; 8173 8174 u8 reserved_at_40[0x1c]; 8175 u8 cong_protocol[0x4]; 8176 8177 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select; 8178 8179 u8 reserved_at_80[0x80]; 8180 8181 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 8182 }; 8183 8184 struct mlx5_ifc_manage_pages_out_bits { 8185 u8 status[0x8]; 8186 u8 reserved_at_8[0x18]; 8187 8188 u8 syndrome[0x20]; 8189 8190 u8 output_num_entries[0x20]; 8191 8192 u8 reserved_at_60[0x20]; 8193 8194 u8 pas[][0x40]; 8195 }; 8196 8197 enum { 8198 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL = 0x0, 8199 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS = 0x1, 8200 MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES = 0x2, 8201 }; 8202 8203 struct mlx5_ifc_manage_pages_in_bits { 8204 u8 opcode[0x10]; 8205 u8 reserved_at_10[0x10]; 8206 8207 u8 reserved_at_20[0x10]; 8208 u8 op_mod[0x10]; 8209 8210 u8 embedded_cpu_function[0x1]; 8211 u8 reserved_at_41[0xf]; 8212 u8 function_id[0x10]; 8213 8214 u8 input_num_entries[0x20]; 8215 8216 u8 pas[][0x40]; 8217 }; 8218 8219 struct mlx5_ifc_mad_ifc_out_bits { 8220 u8 status[0x8]; 8221 u8 reserved_at_8[0x18]; 8222 8223 u8 syndrome[0x20]; 8224 8225 u8 reserved_at_40[0x40]; 8226 8227 u8 response_mad_packet[256][0x8]; 8228 }; 8229 8230 struct mlx5_ifc_mad_ifc_in_bits { 8231 u8 opcode[0x10]; 8232 u8 reserved_at_10[0x10]; 8233 8234 u8 reserved_at_20[0x10]; 8235 u8 op_mod[0x10]; 8236 8237 u8 remote_lid[0x10]; 8238 u8 plane_index[0x8]; 8239 u8 port[0x8]; 8240 8241 u8 reserved_at_60[0x20]; 8242 8243 u8 mad[256][0x8]; 8244 }; 8245 8246 struct mlx5_ifc_init_hca_out_bits { 8247 u8 status[0x8]; 8248 u8 reserved_at_8[0x18]; 8249 8250 u8 syndrome[0x20]; 8251 8252 u8 reserved_at_40[0x40]; 8253 }; 8254 8255 struct mlx5_ifc_init_hca_in_bits { 8256 u8 opcode[0x10]; 8257 u8 reserved_at_10[0x10]; 8258 8259 u8 reserved_at_20[0x10]; 8260 u8 op_mod[0x10]; 8261 8262 u8 reserved_at_40[0x20]; 8263 8264 u8 reserved_at_60[0x2]; 8265 u8 sw_vhca_id[0xe]; 8266 u8 reserved_at_70[0x10]; 8267 8268 u8 sw_owner_id[4][0x20]; 8269 }; 8270 8271 struct mlx5_ifc_init2rtr_qp_out_bits { 8272 u8 status[0x8]; 8273 u8 reserved_at_8[0x18]; 8274 8275 u8 syndrome[0x20]; 8276 8277 u8 reserved_at_40[0x20]; 8278 u8 ece[0x20]; 8279 }; 8280 8281 struct mlx5_ifc_init2rtr_qp_in_bits { 8282 u8 opcode[0x10]; 8283 u8 uid[0x10]; 8284 8285 u8 reserved_at_20[0x10]; 8286 u8 op_mod[0x10]; 8287 8288 u8 reserved_at_40[0x8]; 8289 u8 qpn[0x18]; 8290 8291 u8 reserved_at_60[0x20]; 8292 8293 u8 opt_param_mask[0x20]; 8294 8295 u8 ece[0x20]; 8296 8297 struct mlx5_ifc_qpc_bits qpc; 8298 8299 u8 reserved_at_800[0x80]; 8300 }; 8301 8302 struct mlx5_ifc_init2init_qp_out_bits { 8303 u8 status[0x8]; 8304 u8 reserved_at_8[0x18]; 8305 8306 u8 syndrome[0x20]; 8307 8308 u8 reserved_at_40[0x20]; 8309 u8 ece[0x20]; 8310 }; 8311 8312 struct mlx5_ifc_init2init_qp_in_bits { 8313 u8 opcode[0x10]; 8314 u8 uid[0x10]; 8315 8316 u8 reserved_at_20[0x10]; 8317 u8 op_mod[0x10]; 8318 8319 u8 reserved_at_40[0x8]; 8320 u8 qpn[0x18]; 8321 8322 u8 reserved_at_60[0x20]; 8323 8324 u8 opt_param_mask[0x20]; 8325 8326 u8 ece[0x20]; 8327 8328 struct mlx5_ifc_qpc_bits qpc; 8329 8330 u8 reserved_at_800[0x80]; 8331 }; 8332 8333 struct mlx5_ifc_get_dropped_packet_log_out_bits { 8334 u8 status[0x8]; 8335 u8 reserved_at_8[0x18]; 8336 8337 u8 syndrome[0x20]; 8338 8339 u8 reserved_at_40[0x40]; 8340 8341 u8 packet_headers_log[128][0x8]; 8342 8343 u8 packet_syndrome[64][0x8]; 8344 }; 8345 8346 struct mlx5_ifc_get_dropped_packet_log_in_bits { 8347 u8 opcode[0x10]; 8348 u8 reserved_at_10[0x10]; 8349 8350 u8 reserved_at_20[0x10]; 8351 u8 op_mod[0x10]; 8352 8353 u8 reserved_at_40[0x40]; 8354 }; 8355 8356 struct mlx5_ifc_gen_eqe_in_bits { 8357 u8 opcode[0x10]; 8358 u8 reserved_at_10[0x10]; 8359 8360 u8 reserved_at_20[0x10]; 8361 u8 op_mod[0x10]; 8362 8363 u8 reserved_at_40[0x18]; 8364 u8 eq_number[0x8]; 8365 8366 u8 reserved_at_60[0x20]; 8367 8368 u8 eqe[64][0x8]; 8369 }; 8370 8371 struct mlx5_ifc_gen_eq_out_bits { 8372 u8 status[0x8]; 8373 u8 reserved_at_8[0x18]; 8374 8375 u8 syndrome[0x20]; 8376 8377 u8 reserved_at_40[0x40]; 8378 }; 8379 8380 struct mlx5_ifc_enable_hca_out_bits { 8381 u8 status[0x8]; 8382 u8 reserved_at_8[0x18]; 8383 8384 u8 syndrome[0x20]; 8385 8386 u8 reserved_at_40[0x20]; 8387 }; 8388 8389 struct mlx5_ifc_enable_hca_in_bits { 8390 u8 opcode[0x10]; 8391 u8 reserved_at_10[0x10]; 8392 8393 u8 reserved_at_20[0x10]; 8394 u8 op_mod[0x10]; 8395 8396 u8 embedded_cpu_function[0x1]; 8397 u8 reserved_at_41[0xf]; 8398 u8 function_id[0x10]; 8399 8400 u8 reserved_at_60[0x20]; 8401 }; 8402 8403 struct mlx5_ifc_drain_dct_out_bits { 8404 u8 status[0x8]; 8405 u8 reserved_at_8[0x18]; 8406 8407 u8 syndrome[0x20]; 8408 8409 u8 reserved_at_40[0x40]; 8410 }; 8411 8412 struct mlx5_ifc_drain_dct_in_bits { 8413 u8 opcode[0x10]; 8414 u8 uid[0x10]; 8415 8416 u8 reserved_at_20[0x10]; 8417 u8 op_mod[0x10]; 8418 8419 u8 reserved_at_40[0x8]; 8420 u8 dctn[0x18]; 8421 8422 u8 reserved_at_60[0x20]; 8423 }; 8424 8425 struct mlx5_ifc_disable_hca_out_bits { 8426 u8 status[0x8]; 8427 u8 reserved_at_8[0x18]; 8428 8429 u8 syndrome[0x20]; 8430 8431 u8 reserved_at_40[0x20]; 8432 }; 8433 8434 struct mlx5_ifc_disable_hca_in_bits { 8435 u8 opcode[0x10]; 8436 u8 reserved_at_10[0x10]; 8437 8438 u8 reserved_at_20[0x10]; 8439 u8 op_mod[0x10]; 8440 8441 u8 embedded_cpu_function[0x1]; 8442 u8 reserved_at_41[0xf]; 8443 u8 function_id[0x10]; 8444 8445 u8 reserved_at_60[0x20]; 8446 }; 8447 8448 struct mlx5_ifc_detach_from_mcg_out_bits { 8449 u8 status[0x8]; 8450 u8 reserved_at_8[0x18]; 8451 8452 u8 syndrome[0x20]; 8453 8454 u8 reserved_at_40[0x40]; 8455 }; 8456 8457 struct mlx5_ifc_detach_from_mcg_in_bits { 8458 u8 opcode[0x10]; 8459 u8 uid[0x10]; 8460 8461 u8 reserved_at_20[0x10]; 8462 u8 op_mod[0x10]; 8463 8464 u8 reserved_at_40[0x8]; 8465 u8 qpn[0x18]; 8466 8467 u8 reserved_at_60[0x20]; 8468 8469 u8 multicast_gid[16][0x8]; 8470 }; 8471 8472 struct mlx5_ifc_destroy_xrq_out_bits { 8473 u8 status[0x8]; 8474 u8 reserved_at_8[0x18]; 8475 8476 u8 syndrome[0x20]; 8477 8478 u8 reserved_at_40[0x40]; 8479 }; 8480 8481 struct mlx5_ifc_destroy_xrq_in_bits { 8482 u8 opcode[0x10]; 8483 u8 uid[0x10]; 8484 8485 u8 reserved_at_20[0x10]; 8486 u8 op_mod[0x10]; 8487 8488 u8 reserved_at_40[0x8]; 8489 u8 xrqn[0x18]; 8490 8491 u8 reserved_at_60[0x20]; 8492 }; 8493 8494 struct mlx5_ifc_destroy_xrc_srq_out_bits { 8495 u8 status[0x8]; 8496 u8 reserved_at_8[0x18]; 8497 8498 u8 syndrome[0x20]; 8499 8500 u8 reserved_at_40[0x40]; 8501 }; 8502 8503 struct mlx5_ifc_destroy_xrc_srq_in_bits { 8504 u8 opcode[0x10]; 8505 u8 uid[0x10]; 8506 8507 u8 reserved_at_20[0x10]; 8508 u8 op_mod[0x10]; 8509 8510 u8 reserved_at_40[0x8]; 8511 u8 xrc_srqn[0x18]; 8512 8513 u8 reserved_at_60[0x20]; 8514 }; 8515 8516 struct mlx5_ifc_destroy_tis_out_bits { 8517 u8 status[0x8]; 8518 u8 reserved_at_8[0x18]; 8519 8520 u8 syndrome[0x20]; 8521 8522 u8 reserved_at_40[0x40]; 8523 }; 8524 8525 struct mlx5_ifc_destroy_tis_in_bits { 8526 u8 opcode[0x10]; 8527 u8 uid[0x10]; 8528 8529 u8 reserved_at_20[0x10]; 8530 u8 op_mod[0x10]; 8531 8532 u8 reserved_at_40[0x8]; 8533 u8 tisn[0x18]; 8534 8535 u8 reserved_at_60[0x20]; 8536 }; 8537 8538 struct mlx5_ifc_destroy_tir_out_bits { 8539 u8 status[0x8]; 8540 u8 reserved_at_8[0x18]; 8541 8542 u8 syndrome[0x20]; 8543 8544 u8 reserved_at_40[0x40]; 8545 }; 8546 8547 struct mlx5_ifc_destroy_tir_in_bits { 8548 u8 opcode[0x10]; 8549 u8 uid[0x10]; 8550 8551 u8 reserved_at_20[0x10]; 8552 u8 op_mod[0x10]; 8553 8554 u8 reserved_at_40[0x8]; 8555 u8 tirn[0x18]; 8556 8557 u8 reserved_at_60[0x20]; 8558 }; 8559 8560 struct mlx5_ifc_destroy_srq_out_bits { 8561 u8 status[0x8]; 8562 u8 reserved_at_8[0x18]; 8563 8564 u8 syndrome[0x20]; 8565 8566 u8 reserved_at_40[0x40]; 8567 }; 8568 8569 struct mlx5_ifc_destroy_srq_in_bits { 8570 u8 opcode[0x10]; 8571 u8 uid[0x10]; 8572 8573 u8 reserved_at_20[0x10]; 8574 u8 op_mod[0x10]; 8575 8576 u8 reserved_at_40[0x8]; 8577 u8 srqn[0x18]; 8578 8579 u8 reserved_at_60[0x20]; 8580 }; 8581 8582 struct mlx5_ifc_destroy_sq_out_bits { 8583 u8 status[0x8]; 8584 u8 reserved_at_8[0x18]; 8585 8586 u8 syndrome[0x20]; 8587 8588 u8 reserved_at_40[0x40]; 8589 }; 8590 8591 struct mlx5_ifc_destroy_sq_in_bits { 8592 u8 opcode[0x10]; 8593 u8 uid[0x10]; 8594 8595 u8 reserved_at_20[0x10]; 8596 u8 op_mod[0x10]; 8597 8598 u8 reserved_at_40[0x8]; 8599 u8 sqn[0x18]; 8600 8601 u8 reserved_at_60[0x20]; 8602 }; 8603 8604 struct mlx5_ifc_destroy_scheduling_element_out_bits { 8605 u8 status[0x8]; 8606 u8 reserved_at_8[0x18]; 8607 8608 u8 syndrome[0x20]; 8609 8610 u8 reserved_at_40[0x1c0]; 8611 }; 8612 8613 struct mlx5_ifc_destroy_scheduling_element_in_bits { 8614 u8 opcode[0x10]; 8615 u8 reserved_at_10[0x10]; 8616 8617 u8 reserved_at_20[0x10]; 8618 u8 op_mod[0x10]; 8619 8620 u8 scheduling_hierarchy[0x8]; 8621 u8 reserved_at_48[0x18]; 8622 8623 u8 scheduling_element_id[0x20]; 8624 8625 u8 reserved_at_80[0x180]; 8626 }; 8627 8628 struct mlx5_ifc_destroy_rqt_out_bits { 8629 u8 status[0x8]; 8630 u8 reserved_at_8[0x18]; 8631 8632 u8 syndrome[0x20]; 8633 8634 u8 reserved_at_40[0x40]; 8635 }; 8636 8637 struct mlx5_ifc_destroy_rqt_in_bits { 8638 u8 opcode[0x10]; 8639 u8 uid[0x10]; 8640 8641 u8 reserved_at_20[0x10]; 8642 u8 op_mod[0x10]; 8643 8644 u8 reserved_at_40[0x8]; 8645 u8 rqtn[0x18]; 8646 8647 u8 reserved_at_60[0x20]; 8648 }; 8649 8650 struct mlx5_ifc_destroy_rq_out_bits { 8651 u8 status[0x8]; 8652 u8 reserved_at_8[0x18]; 8653 8654 u8 syndrome[0x20]; 8655 8656 u8 reserved_at_40[0x40]; 8657 }; 8658 8659 struct mlx5_ifc_destroy_rq_in_bits { 8660 u8 opcode[0x10]; 8661 u8 uid[0x10]; 8662 8663 u8 reserved_at_20[0x10]; 8664 u8 op_mod[0x10]; 8665 8666 u8 reserved_at_40[0x8]; 8667 u8 rqn[0x18]; 8668 8669 u8 reserved_at_60[0x20]; 8670 }; 8671 8672 struct mlx5_ifc_set_delay_drop_params_in_bits { 8673 u8 opcode[0x10]; 8674 u8 reserved_at_10[0x10]; 8675 8676 u8 reserved_at_20[0x10]; 8677 u8 op_mod[0x10]; 8678 8679 u8 reserved_at_40[0x20]; 8680 8681 u8 reserved_at_60[0x10]; 8682 u8 delay_drop_timeout[0x10]; 8683 }; 8684 8685 struct mlx5_ifc_set_delay_drop_params_out_bits { 8686 u8 status[0x8]; 8687 u8 reserved_at_8[0x18]; 8688 8689 u8 syndrome[0x20]; 8690 8691 u8 reserved_at_40[0x40]; 8692 }; 8693 8694 struct mlx5_ifc_destroy_rmp_out_bits { 8695 u8 status[0x8]; 8696 u8 reserved_at_8[0x18]; 8697 8698 u8 syndrome[0x20]; 8699 8700 u8 reserved_at_40[0x40]; 8701 }; 8702 8703 struct mlx5_ifc_destroy_rmp_in_bits { 8704 u8 opcode[0x10]; 8705 u8 uid[0x10]; 8706 8707 u8 reserved_at_20[0x10]; 8708 u8 op_mod[0x10]; 8709 8710 u8 reserved_at_40[0x8]; 8711 u8 rmpn[0x18]; 8712 8713 u8 reserved_at_60[0x20]; 8714 }; 8715 8716 struct mlx5_ifc_destroy_qp_out_bits { 8717 u8 status[0x8]; 8718 u8 reserved_at_8[0x18]; 8719 8720 u8 syndrome[0x20]; 8721 8722 u8 reserved_at_40[0x40]; 8723 }; 8724 8725 struct mlx5_ifc_destroy_qp_in_bits { 8726 u8 opcode[0x10]; 8727 u8 uid[0x10]; 8728 8729 u8 reserved_at_20[0x10]; 8730 u8 op_mod[0x10]; 8731 8732 u8 reserved_at_40[0x8]; 8733 u8 qpn[0x18]; 8734 8735 u8 reserved_at_60[0x20]; 8736 }; 8737 8738 struct mlx5_ifc_destroy_psv_out_bits { 8739 u8 status[0x8]; 8740 u8 reserved_at_8[0x18]; 8741 8742 u8 syndrome[0x20]; 8743 8744 u8 reserved_at_40[0x40]; 8745 }; 8746 8747 struct mlx5_ifc_destroy_psv_in_bits { 8748 u8 opcode[0x10]; 8749 u8 reserved_at_10[0x10]; 8750 8751 u8 reserved_at_20[0x10]; 8752 u8 op_mod[0x10]; 8753 8754 u8 reserved_at_40[0x8]; 8755 u8 psvn[0x18]; 8756 8757 u8 reserved_at_60[0x20]; 8758 }; 8759 8760 struct mlx5_ifc_destroy_mkey_out_bits { 8761 u8 status[0x8]; 8762 u8 reserved_at_8[0x18]; 8763 8764 u8 syndrome[0x20]; 8765 8766 u8 reserved_at_40[0x40]; 8767 }; 8768 8769 struct mlx5_ifc_destroy_mkey_in_bits { 8770 u8 opcode[0x10]; 8771 u8 uid[0x10]; 8772 8773 u8 reserved_at_20[0x10]; 8774 u8 op_mod[0x10]; 8775 8776 u8 reserved_at_40[0x8]; 8777 u8 mkey_index[0x18]; 8778 8779 u8 reserved_at_60[0x20]; 8780 }; 8781 8782 struct mlx5_ifc_destroy_flow_table_out_bits { 8783 u8 status[0x8]; 8784 u8 reserved_at_8[0x18]; 8785 8786 u8 syndrome[0x20]; 8787 8788 u8 reserved_at_40[0x40]; 8789 }; 8790 8791 struct mlx5_ifc_destroy_flow_table_in_bits { 8792 u8 opcode[0x10]; 8793 u8 reserved_at_10[0x10]; 8794 8795 u8 reserved_at_20[0x10]; 8796 u8 op_mod[0x10]; 8797 8798 u8 other_vport[0x1]; 8799 u8 reserved_at_41[0xf]; 8800 u8 vport_number[0x10]; 8801 8802 u8 reserved_at_60[0x20]; 8803 8804 u8 table_type[0x8]; 8805 u8 reserved_at_88[0x18]; 8806 8807 u8 reserved_at_a0[0x8]; 8808 u8 table_id[0x18]; 8809 8810 u8 reserved_at_c0[0x140]; 8811 }; 8812 8813 struct mlx5_ifc_destroy_flow_group_out_bits { 8814 u8 status[0x8]; 8815 u8 reserved_at_8[0x18]; 8816 8817 u8 syndrome[0x20]; 8818 8819 u8 reserved_at_40[0x40]; 8820 }; 8821 8822 struct mlx5_ifc_destroy_flow_group_in_bits { 8823 u8 opcode[0x10]; 8824 u8 reserved_at_10[0x10]; 8825 8826 u8 reserved_at_20[0x10]; 8827 u8 op_mod[0x10]; 8828 8829 u8 other_vport[0x1]; 8830 u8 reserved_at_41[0xf]; 8831 u8 vport_number[0x10]; 8832 8833 u8 reserved_at_60[0x20]; 8834 8835 u8 table_type[0x8]; 8836 u8 reserved_at_88[0x18]; 8837 8838 u8 reserved_at_a0[0x8]; 8839 u8 table_id[0x18]; 8840 8841 u8 group_id[0x20]; 8842 8843 u8 reserved_at_e0[0x120]; 8844 }; 8845 8846 struct mlx5_ifc_destroy_eq_out_bits { 8847 u8 status[0x8]; 8848 u8 reserved_at_8[0x18]; 8849 8850 u8 syndrome[0x20]; 8851 8852 u8 reserved_at_40[0x40]; 8853 }; 8854 8855 struct mlx5_ifc_destroy_eq_in_bits { 8856 u8 opcode[0x10]; 8857 u8 reserved_at_10[0x10]; 8858 8859 u8 reserved_at_20[0x10]; 8860 u8 op_mod[0x10]; 8861 8862 u8 reserved_at_40[0x18]; 8863 u8 eq_number[0x8]; 8864 8865 u8 reserved_at_60[0x20]; 8866 }; 8867 8868 struct mlx5_ifc_destroy_dct_out_bits { 8869 u8 status[0x8]; 8870 u8 reserved_at_8[0x18]; 8871 8872 u8 syndrome[0x20]; 8873 8874 u8 reserved_at_40[0x40]; 8875 }; 8876 8877 struct mlx5_ifc_destroy_dct_in_bits { 8878 u8 opcode[0x10]; 8879 u8 uid[0x10]; 8880 8881 u8 reserved_at_20[0x10]; 8882 u8 op_mod[0x10]; 8883 8884 u8 reserved_at_40[0x8]; 8885 u8 dctn[0x18]; 8886 8887 u8 reserved_at_60[0x20]; 8888 }; 8889 8890 struct mlx5_ifc_destroy_cq_out_bits { 8891 u8 status[0x8]; 8892 u8 reserved_at_8[0x18]; 8893 8894 u8 syndrome[0x20]; 8895 8896 u8 reserved_at_40[0x40]; 8897 }; 8898 8899 struct mlx5_ifc_destroy_cq_in_bits { 8900 u8 opcode[0x10]; 8901 u8 uid[0x10]; 8902 8903 u8 reserved_at_20[0x10]; 8904 u8 op_mod[0x10]; 8905 8906 u8 reserved_at_40[0x8]; 8907 u8 cqn[0x18]; 8908 8909 u8 reserved_at_60[0x20]; 8910 }; 8911 8912 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits { 8913 u8 status[0x8]; 8914 u8 reserved_at_8[0x18]; 8915 8916 u8 syndrome[0x20]; 8917 8918 u8 reserved_at_40[0x40]; 8919 }; 8920 8921 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits { 8922 u8 opcode[0x10]; 8923 u8 reserved_at_10[0x10]; 8924 8925 u8 reserved_at_20[0x10]; 8926 u8 op_mod[0x10]; 8927 8928 u8 reserved_at_40[0x20]; 8929 8930 u8 reserved_at_60[0x10]; 8931 u8 vxlan_udp_port[0x10]; 8932 }; 8933 8934 struct mlx5_ifc_delete_l2_table_entry_out_bits { 8935 u8 status[0x8]; 8936 u8 reserved_at_8[0x18]; 8937 8938 u8 syndrome[0x20]; 8939 8940 u8 reserved_at_40[0x40]; 8941 }; 8942 8943 struct mlx5_ifc_delete_l2_table_entry_in_bits { 8944 u8 opcode[0x10]; 8945 u8 reserved_at_10[0x10]; 8946 8947 u8 reserved_at_20[0x10]; 8948 u8 op_mod[0x10]; 8949 8950 u8 reserved_at_40[0x60]; 8951 8952 u8 reserved_at_a0[0x8]; 8953 u8 table_index[0x18]; 8954 8955 u8 reserved_at_c0[0x140]; 8956 }; 8957 8958 struct mlx5_ifc_delete_fte_out_bits { 8959 u8 status[0x8]; 8960 u8 reserved_at_8[0x18]; 8961 8962 u8 syndrome[0x20]; 8963 8964 u8 reserved_at_40[0x40]; 8965 }; 8966 8967 struct mlx5_ifc_delete_fte_in_bits { 8968 u8 opcode[0x10]; 8969 u8 reserved_at_10[0x10]; 8970 8971 u8 reserved_at_20[0x10]; 8972 u8 op_mod[0x10]; 8973 8974 u8 other_vport[0x1]; 8975 u8 reserved_at_41[0xf]; 8976 u8 vport_number[0x10]; 8977 8978 u8 reserved_at_60[0x20]; 8979 8980 u8 table_type[0x8]; 8981 u8 reserved_at_88[0x18]; 8982 8983 u8 reserved_at_a0[0x8]; 8984 u8 table_id[0x18]; 8985 8986 u8 reserved_at_c0[0x40]; 8987 8988 u8 flow_index[0x20]; 8989 8990 u8 reserved_at_120[0xe0]; 8991 }; 8992 8993 struct mlx5_ifc_dealloc_xrcd_out_bits { 8994 u8 status[0x8]; 8995 u8 reserved_at_8[0x18]; 8996 8997 u8 syndrome[0x20]; 8998 8999 u8 reserved_at_40[0x40]; 9000 }; 9001 9002 struct mlx5_ifc_dealloc_xrcd_in_bits { 9003 u8 opcode[0x10]; 9004 u8 uid[0x10]; 9005 9006 u8 reserved_at_20[0x10]; 9007 u8 op_mod[0x10]; 9008 9009 u8 reserved_at_40[0x8]; 9010 u8 xrcd[0x18]; 9011 9012 u8 reserved_at_60[0x20]; 9013 }; 9014 9015 struct mlx5_ifc_dealloc_uar_out_bits { 9016 u8 status[0x8]; 9017 u8 reserved_at_8[0x18]; 9018 9019 u8 syndrome[0x20]; 9020 9021 u8 reserved_at_40[0x40]; 9022 }; 9023 9024 struct mlx5_ifc_dealloc_uar_in_bits { 9025 u8 opcode[0x10]; 9026 u8 uid[0x10]; 9027 9028 u8 reserved_at_20[0x10]; 9029 u8 op_mod[0x10]; 9030 9031 u8 reserved_at_40[0x8]; 9032 u8 uar[0x18]; 9033 9034 u8 reserved_at_60[0x20]; 9035 }; 9036 9037 struct mlx5_ifc_dealloc_transport_domain_out_bits { 9038 u8 status[0x8]; 9039 u8 reserved_at_8[0x18]; 9040 9041 u8 syndrome[0x20]; 9042 9043 u8 reserved_at_40[0x40]; 9044 }; 9045 9046 struct mlx5_ifc_dealloc_transport_domain_in_bits { 9047 u8 opcode[0x10]; 9048 u8 uid[0x10]; 9049 9050 u8 reserved_at_20[0x10]; 9051 u8 op_mod[0x10]; 9052 9053 u8 reserved_at_40[0x8]; 9054 u8 transport_domain[0x18]; 9055 9056 u8 reserved_at_60[0x20]; 9057 }; 9058 9059 struct mlx5_ifc_dealloc_q_counter_out_bits { 9060 u8 status[0x8]; 9061 u8 reserved_at_8[0x18]; 9062 9063 u8 syndrome[0x20]; 9064 9065 u8 reserved_at_40[0x40]; 9066 }; 9067 9068 struct mlx5_ifc_dealloc_q_counter_in_bits { 9069 u8 opcode[0x10]; 9070 u8 reserved_at_10[0x10]; 9071 9072 u8 reserved_at_20[0x10]; 9073 u8 op_mod[0x10]; 9074 9075 u8 reserved_at_40[0x18]; 9076 u8 counter_set_id[0x8]; 9077 9078 u8 reserved_at_60[0x20]; 9079 }; 9080 9081 struct mlx5_ifc_dealloc_pd_out_bits { 9082 u8 status[0x8]; 9083 u8 reserved_at_8[0x18]; 9084 9085 u8 syndrome[0x20]; 9086 9087 u8 reserved_at_40[0x40]; 9088 }; 9089 9090 struct mlx5_ifc_dealloc_pd_in_bits { 9091 u8 opcode[0x10]; 9092 u8 uid[0x10]; 9093 9094 u8 reserved_at_20[0x10]; 9095 u8 op_mod[0x10]; 9096 9097 u8 reserved_at_40[0x8]; 9098 u8 pd[0x18]; 9099 9100 u8 reserved_at_60[0x20]; 9101 }; 9102 9103 struct mlx5_ifc_dealloc_flow_counter_out_bits { 9104 u8 status[0x8]; 9105 u8 reserved_at_8[0x18]; 9106 9107 u8 syndrome[0x20]; 9108 9109 u8 reserved_at_40[0x40]; 9110 }; 9111 9112 struct mlx5_ifc_dealloc_flow_counter_in_bits { 9113 u8 opcode[0x10]; 9114 u8 reserved_at_10[0x10]; 9115 9116 u8 reserved_at_20[0x10]; 9117 u8 op_mod[0x10]; 9118 9119 u8 flow_counter_id[0x20]; 9120 9121 u8 reserved_at_60[0x20]; 9122 }; 9123 9124 struct mlx5_ifc_create_xrq_out_bits { 9125 u8 status[0x8]; 9126 u8 reserved_at_8[0x18]; 9127 9128 u8 syndrome[0x20]; 9129 9130 u8 reserved_at_40[0x8]; 9131 u8 xrqn[0x18]; 9132 9133 u8 reserved_at_60[0x20]; 9134 }; 9135 9136 struct mlx5_ifc_create_xrq_in_bits { 9137 u8 opcode[0x10]; 9138 u8 uid[0x10]; 9139 9140 u8 reserved_at_20[0x10]; 9141 u8 op_mod[0x10]; 9142 9143 u8 reserved_at_40[0x40]; 9144 9145 struct mlx5_ifc_xrqc_bits xrq_context; 9146 }; 9147 9148 struct mlx5_ifc_create_xrc_srq_out_bits { 9149 u8 status[0x8]; 9150 u8 reserved_at_8[0x18]; 9151 9152 u8 syndrome[0x20]; 9153 9154 u8 reserved_at_40[0x8]; 9155 u8 xrc_srqn[0x18]; 9156 9157 u8 reserved_at_60[0x20]; 9158 }; 9159 9160 struct mlx5_ifc_create_xrc_srq_in_bits { 9161 u8 opcode[0x10]; 9162 u8 uid[0x10]; 9163 9164 u8 reserved_at_20[0x10]; 9165 u8 op_mod[0x10]; 9166 9167 u8 reserved_at_40[0x40]; 9168 9169 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 9170 9171 u8 reserved_at_280[0x60]; 9172 9173 u8 xrc_srq_umem_valid[0x1]; 9174 u8 reserved_at_2e1[0x1f]; 9175 9176 u8 reserved_at_300[0x580]; 9177 9178 u8 pas[][0x40]; 9179 }; 9180 9181 struct mlx5_ifc_create_tis_out_bits { 9182 u8 status[0x8]; 9183 u8 reserved_at_8[0x18]; 9184 9185 u8 syndrome[0x20]; 9186 9187 u8 reserved_at_40[0x8]; 9188 u8 tisn[0x18]; 9189 9190 u8 reserved_at_60[0x20]; 9191 }; 9192 9193 struct mlx5_ifc_create_tis_in_bits { 9194 u8 opcode[0x10]; 9195 u8 uid[0x10]; 9196 9197 u8 reserved_at_20[0x10]; 9198 u8 op_mod[0x10]; 9199 9200 u8 reserved_at_40[0xc0]; 9201 9202 struct mlx5_ifc_tisc_bits ctx; 9203 }; 9204 9205 struct mlx5_ifc_create_tir_out_bits { 9206 u8 status[0x8]; 9207 u8 icm_address_63_40[0x18]; 9208 9209 u8 syndrome[0x20]; 9210 9211 u8 icm_address_39_32[0x8]; 9212 u8 tirn[0x18]; 9213 9214 u8 icm_address_31_0[0x20]; 9215 }; 9216 9217 struct mlx5_ifc_create_tir_in_bits { 9218 u8 opcode[0x10]; 9219 u8 uid[0x10]; 9220 9221 u8 reserved_at_20[0x10]; 9222 u8 op_mod[0x10]; 9223 9224 u8 reserved_at_40[0xc0]; 9225 9226 struct mlx5_ifc_tirc_bits ctx; 9227 }; 9228 9229 struct mlx5_ifc_create_srq_out_bits { 9230 u8 status[0x8]; 9231 u8 reserved_at_8[0x18]; 9232 9233 u8 syndrome[0x20]; 9234 9235 u8 reserved_at_40[0x8]; 9236 u8 srqn[0x18]; 9237 9238 u8 reserved_at_60[0x20]; 9239 }; 9240 9241 struct mlx5_ifc_create_srq_in_bits { 9242 u8 opcode[0x10]; 9243 u8 uid[0x10]; 9244 9245 u8 reserved_at_20[0x10]; 9246 u8 op_mod[0x10]; 9247 9248 u8 reserved_at_40[0x40]; 9249 9250 struct mlx5_ifc_srqc_bits srq_context_entry; 9251 9252 u8 reserved_at_280[0x600]; 9253 9254 u8 pas[][0x40]; 9255 }; 9256 9257 struct mlx5_ifc_create_sq_out_bits { 9258 u8 status[0x8]; 9259 u8 reserved_at_8[0x18]; 9260 9261 u8 syndrome[0x20]; 9262 9263 u8 reserved_at_40[0x8]; 9264 u8 sqn[0x18]; 9265 9266 u8 reserved_at_60[0x20]; 9267 }; 9268 9269 struct mlx5_ifc_create_sq_in_bits { 9270 u8 opcode[0x10]; 9271 u8 uid[0x10]; 9272 9273 u8 reserved_at_20[0x10]; 9274 u8 op_mod[0x10]; 9275 9276 u8 reserved_at_40[0xc0]; 9277 9278 struct mlx5_ifc_sqc_bits ctx; 9279 }; 9280 9281 struct mlx5_ifc_create_scheduling_element_out_bits { 9282 u8 status[0x8]; 9283 u8 reserved_at_8[0x18]; 9284 9285 u8 syndrome[0x20]; 9286 9287 u8 reserved_at_40[0x40]; 9288 9289 u8 scheduling_element_id[0x20]; 9290 9291 u8 reserved_at_a0[0x160]; 9292 }; 9293 9294 struct mlx5_ifc_create_scheduling_element_in_bits { 9295 u8 opcode[0x10]; 9296 u8 reserved_at_10[0x10]; 9297 9298 u8 reserved_at_20[0x10]; 9299 u8 op_mod[0x10]; 9300 9301 u8 scheduling_hierarchy[0x8]; 9302 u8 reserved_at_48[0x18]; 9303 9304 u8 reserved_at_60[0xa0]; 9305 9306 struct mlx5_ifc_scheduling_context_bits scheduling_context; 9307 9308 u8 reserved_at_300[0x100]; 9309 }; 9310 9311 struct mlx5_ifc_create_rqt_out_bits { 9312 u8 status[0x8]; 9313 u8 reserved_at_8[0x18]; 9314 9315 u8 syndrome[0x20]; 9316 9317 u8 reserved_at_40[0x8]; 9318 u8 rqtn[0x18]; 9319 9320 u8 reserved_at_60[0x20]; 9321 }; 9322 9323 struct mlx5_ifc_create_rqt_in_bits { 9324 u8 opcode[0x10]; 9325 u8 uid[0x10]; 9326 9327 u8 reserved_at_20[0x10]; 9328 u8 op_mod[0x10]; 9329 9330 u8 reserved_at_40[0xc0]; 9331 9332 struct mlx5_ifc_rqtc_bits rqt_context; 9333 }; 9334 9335 struct mlx5_ifc_create_rq_out_bits { 9336 u8 status[0x8]; 9337 u8 reserved_at_8[0x18]; 9338 9339 u8 syndrome[0x20]; 9340 9341 u8 reserved_at_40[0x8]; 9342 u8 rqn[0x18]; 9343 9344 u8 reserved_at_60[0x20]; 9345 }; 9346 9347 struct mlx5_ifc_create_rq_in_bits { 9348 u8 opcode[0x10]; 9349 u8 uid[0x10]; 9350 9351 u8 reserved_at_20[0x10]; 9352 u8 op_mod[0x10]; 9353 9354 u8 reserved_at_40[0xc0]; 9355 9356 struct mlx5_ifc_rqc_bits ctx; 9357 }; 9358 9359 struct mlx5_ifc_create_rmp_out_bits { 9360 u8 status[0x8]; 9361 u8 reserved_at_8[0x18]; 9362 9363 u8 syndrome[0x20]; 9364 9365 u8 reserved_at_40[0x8]; 9366 u8 rmpn[0x18]; 9367 9368 u8 reserved_at_60[0x20]; 9369 }; 9370 9371 struct mlx5_ifc_create_rmp_in_bits { 9372 u8 opcode[0x10]; 9373 u8 uid[0x10]; 9374 9375 u8 reserved_at_20[0x10]; 9376 u8 op_mod[0x10]; 9377 9378 u8 reserved_at_40[0xc0]; 9379 9380 struct mlx5_ifc_rmpc_bits ctx; 9381 }; 9382 9383 struct mlx5_ifc_create_qp_out_bits { 9384 u8 status[0x8]; 9385 u8 reserved_at_8[0x18]; 9386 9387 u8 syndrome[0x20]; 9388 9389 u8 reserved_at_40[0x8]; 9390 u8 qpn[0x18]; 9391 9392 u8 ece[0x20]; 9393 }; 9394 9395 struct mlx5_ifc_create_qp_in_bits { 9396 u8 opcode[0x10]; 9397 u8 uid[0x10]; 9398 9399 u8 reserved_at_20[0x10]; 9400 u8 op_mod[0x10]; 9401 9402 u8 qpc_ext[0x1]; 9403 u8 reserved_at_41[0x7]; 9404 u8 input_qpn[0x18]; 9405 9406 u8 reserved_at_60[0x20]; 9407 u8 opt_param_mask[0x20]; 9408 9409 u8 ece[0x20]; 9410 9411 struct mlx5_ifc_qpc_bits qpc; 9412 9413 u8 wq_umem_offset[0x40]; 9414 9415 u8 wq_umem_id[0x20]; 9416 9417 u8 wq_umem_valid[0x1]; 9418 u8 reserved_at_861[0x1f]; 9419 9420 u8 pas[][0x40]; 9421 }; 9422 9423 struct mlx5_ifc_create_psv_out_bits { 9424 u8 status[0x8]; 9425 u8 reserved_at_8[0x18]; 9426 9427 u8 syndrome[0x20]; 9428 9429 u8 reserved_at_40[0x40]; 9430 9431 u8 reserved_at_80[0x8]; 9432 u8 psv0_index[0x18]; 9433 9434 u8 reserved_at_a0[0x8]; 9435 u8 psv1_index[0x18]; 9436 9437 u8 reserved_at_c0[0x8]; 9438 u8 psv2_index[0x18]; 9439 9440 u8 reserved_at_e0[0x8]; 9441 u8 psv3_index[0x18]; 9442 }; 9443 9444 struct mlx5_ifc_create_psv_in_bits { 9445 u8 opcode[0x10]; 9446 u8 reserved_at_10[0x10]; 9447 9448 u8 reserved_at_20[0x10]; 9449 u8 op_mod[0x10]; 9450 9451 u8 num_psv[0x4]; 9452 u8 reserved_at_44[0x4]; 9453 u8 pd[0x18]; 9454 9455 u8 reserved_at_60[0x20]; 9456 }; 9457 9458 struct mlx5_ifc_create_mkey_out_bits { 9459 u8 status[0x8]; 9460 u8 reserved_at_8[0x18]; 9461 9462 u8 syndrome[0x20]; 9463 9464 u8 reserved_at_40[0x8]; 9465 u8 mkey_index[0x18]; 9466 9467 u8 reserved_at_60[0x20]; 9468 }; 9469 9470 struct mlx5_ifc_create_mkey_in_bits { 9471 u8 opcode[0x10]; 9472 u8 uid[0x10]; 9473 9474 u8 reserved_at_20[0x10]; 9475 u8 op_mod[0x10]; 9476 9477 u8 reserved_at_40[0x20]; 9478 9479 u8 pg_access[0x1]; 9480 u8 mkey_umem_valid[0x1]; 9481 u8 data_direct[0x1]; 9482 u8 reserved_at_63[0x1d]; 9483 9484 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 9485 9486 u8 reserved_at_280[0x80]; 9487 9488 u8 translations_octword_actual_size[0x20]; 9489 9490 u8 reserved_at_320[0x560]; 9491 9492 u8 klm_pas_mtt[][0x20]; 9493 }; 9494 9495 enum { 9496 MLX5_FLOW_TABLE_TYPE_NIC_RX = 0x0, 9497 MLX5_FLOW_TABLE_TYPE_NIC_TX = 0x1, 9498 MLX5_FLOW_TABLE_TYPE_ESW_EGRESS_ACL = 0x2, 9499 MLX5_FLOW_TABLE_TYPE_ESW_INGRESS_ACL = 0x3, 9500 MLX5_FLOW_TABLE_TYPE_FDB = 0X4, 9501 MLX5_FLOW_TABLE_TYPE_SNIFFER_RX = 0X5, 9502 MLX5_FLOW_TABLE_TYPE_SNIFFER_TX = 0X6, 9503 }; 9504 9505 struct mlx5_ifc_create_flow_table_out_bits { 9506 u8 status[0x8]; 9507 u8 icm_address_63_40[0x18]; 9508 9509 u8 syndrome[0x20]; 9510 9511 u8 icm_address_39_32[0x8]; 9512 u8 table_id[0x18]; 9513 9514 u8 icm_address_31_0[0x20]; 9515 }; 9516 9517 struct mlx5_ifc_create_flow_table_in_bits { 9518 u8 opcode[0x10]; 9519 u8 uid[0x10]; 9520 9521 u8 reserved_at_20[0x10]; 9522 u8 op_mod[0x10]; 9523 9524 u8 other_vport[0x1]; 9525 u8 reserved_at_41[0xf]; 9526 u8 vport_number[0x10]; 9527 9528 u8 reserved_at_60[0x20]; 9529 9530 u8 table_type[0x8]; 9531 u8 reserved_at_88[0x18]; 9532 9533 u8 reserved_at_a0[0x20]; 9534 9535 struct mlx5_ifc_flow_table_context_bits flow_table_context; 9536 }; 9537 9538 struct mlx5_ifc_create_flow_group_out_bits { 9539 u8 status[0x8]; 9540 u8 reserved_at_8[0x18]; 9541 9542 u8 syndrome[0x20]; 9543 9544 u8 reserved_at_40[0x8]; 9545 u8 group_id[0x18]; 9546 9547 u8 reserved_at_60[0x20]; 9548 }; 9549 9550 enum { 9551 MLX5_CREATE_FLOW_GROUP_IN_GROUP_TYPE_TCAM_SUBTABLE = 0x0, 9552 MLX5_CREATE_FLOW_GROUP_IN_GROUP_TYPE_HASH_SPLIT = 0x1, 9553 }; 9554 9555 enum { 9556 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 9557 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 9558 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 9559 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3, 9560 }; 9561 9562 struct mlx5_ifc_create_flow_group_in_bits { 9563 u8 opcode[0x10]; 9564 u8 reserved_at_10[0x10]; 9565 9566 u8 reserved_at_20[0x10]; 9567 u8 op_mod[0x10]; 9568 9569 u8 other_vport[0x1]; 9570 u8 reserved_at_41[0xf]; 9571 u8 vport_number[0x10]; 9572 9573 u8 reserved_at_60[0x20]; 9574 9575 u8 table_type[0x8]; 9576 u8 reserved_at_88[0x4]; 9577 u8 group_type[0x4]; 9578 u8 reserved_at_90[0x10]; 9579 9580 u8 reserved_at_a0[0x8]; 9581 u8 table_id[0x18]; 9582 9583 u8 source_eswitch_owner_vhca_id_valid[0x1]; 9584 9585 u8 reserved_at_c1[0x1f]; 9586 9587 u8 start_flow_index[0x20]; 9588 9589 u8 reserved_at_100[0x20]; 9590 9591 u8 end_flow_index[0x20]; 9592 9593 u8 reserved_at_140[0x10]; 9594 u8 match_definer_id[0x10]; 9595 9596 u8 reserved_at_160[0x80]; 9597 9598 u8 reserved_at_1e0[0x18]; 9599 u8 match_criteria_enable[0x8]; 9600 9601 struct mlx5_ifc_fte_match_param_bits match_criteria; 9602 9603 u8 reserved_at_1200[0xe00]; 9604 }; 9605 9606 struct mlx5_ifc_create_eq_out_bits { 9607 u8 status[0x8]; 9608 u8 reserved_at_8[0x18]; 9609 9610 u8 syndrome[0x20]; 9611 9612 u8 reserved_at_40[0x18]; 9613 u8 eq_number[0x8]; 9614 9615 u8 reserved_at_60[0x20]; 9616 }; 9617 9618 struct mlx5_ifc_create_eq_in_bits { 9619 u8 opcode[0x10]; 9620 u8 uid[0x10]; 9621 9622 u8 reserved_at_20[0x10]; 9623 u8 op_mod[0x10]; 9624 9625 u8 reserved_at_40[0x40]; 9626 9627 struct mlx5_ifc_eqc_bits eq_context_entry; 9628 9629 u8 reserved_at_280[0x40]; 9630 9631 u8 event_bitmask[4][0x40]; 9632 9633 u8 reserved_at_3c0[0x4c0]; 9634 9635 u8 pas[][0x40]; 9636 }; 9637 9638 struct mlx5_ifc_create_dct_out_bits { 9639 u8 status[0x8]; 9640 u8 reserved_at_8[0x18]; 9641 9642 u8 syndrome[0x20]; 9643 9644 u8 reserved_at_40[0x8]; 9645 u8 dctn[0x18]; 9646 9647 u8 ece[0x20]; 9648 }; 9649 9650 struct mlx5_ifc_create_dct_in_bits { 9651 u8 opcode[0x10]; 9652 u8 uid[0x10]; 9653 9654 u8 reserved_at_20[0x10]; 9655 u8 op_mod[0x10]; 9656 9657 u8 reserved_at_40[0x40]; 9658 9659 struct mlx5_ifc_dctc_bits dct_context_entry; 9660 9661 u8 reserved_at_280[0x180]; 9662 }; 9663 9664 struct mlx5_ifc_create_cq_out_bits { 9665 u8 status[0x8]; 9666 u8 reserved_at_8[0x18]; 9667 9668 u8 syndrome[0x20]; 9669 9670 u8 reserved_at_40[0x8]; 9671 u8 cqn[0x18]; 9672 9673 u8 reserved_at_60[0x20]; 9674 }; 9675 9676 struct mlx5_ifc_create_cq_in_bits { 9677 u8 opcode[0x10]; 9678 u8 uid[0x10]; 9679 9680 u8 reserved_at_20[0x10]; 9681 u8 op_mod[0x10]; 9682 9683 u8 reserved_at_40[0x40]; 9684 9685 struct mlx5_ifc_cqc_bits cq_context; 9686 9687 u8 reserved_at_280[0x60]; 9688 9689 u8 cq_umem_valid[0x1]; 9690 u8 reserved_at_2e1[0x59f]; 9691 9692 u8 pas[][0x40]; 9693 }; 9694 9695 struct mlx5_ifc_config_int_moderation_out_bits { 9696 u8 status[0x8]; 9697 u8 reserved_at_8[0x18]; 9698 9699 u8 syndrome[0x20]; 9700 9701 u8 reserved_at_40[0x4]; 9702 u8 min_delay[0xc]; 9703 u8 int_vector[0x10]; 9704 9705 u8 reserved_at_60[0x20]; 9706 }; 9707 9708 enum { 9709 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0, 9710 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1, 9711 }; 9712 9713 struct mlx5_ifc_config_int_moderation_in_bits { 9714 u8 opcode[0x10]; 9715 u8 reserved_at_10[0x10]; 9716 9717 u8 reserved_at_20[0x10]; 9718 u8 op_mod[0x10]; 9719 9720 u8 reserved_at_40[0x4]; 9721 u8 min_delay[0xc]; 9722 u8 int_vector[0x10]; 9723 9724 u8 reserved_at_60[0x20]; 9725 }; 9726 9727 struct mlx5_ifc_attach_to_mcg_out_bits { 9728 u8 status[0x8]; 9729 u8 reserved_at_8[0x18]; 9730 9731 u8 syndrome[0x20]; 9732 9733 u8 reserved_at_40[0x40]; 9734 }; 9735 9736 struct mlx5_ifc_attach_to_mcg_in_bits { 9737 u8 opcode[0x10]; 9738 u8 uid[0x10]; 9739 9740 u8 reserved_at_20[0x10]; 9741 u8 op_mod[0x10]; 9742 9743 u8 reserved_at_40[0x8]; 9744 u8 qpn[0x18]; 9745 9746 u8 reserved_at_60[0x20]; 9747 9748 u8 multicast_gid[16][0x8]; 9749 }; 9750 9751 struct mlx5_ifc_arm_xrq_out_bits { 9752 u8 status[0x8]; 9753 u8 reserved_at_8[0x18]; 9754 9755 u8 syndrome[0x20]; 9756 9757 u8 reserved_at_40[0x40]; 9758 }; 9759 9760 struct mlx5_ifc_arm_xrq_in_bits { 9761 u8 opcode[0x10]; 9762 u8 reserved_at_10[0x10]; 9763 9764 u8 reserved_at_20[0x10]; 9765 u8 op_mod[0x10]; 9766 9767 u8 reserved_at_40[0x8]; 9768 u8 xrqn[0x18]; 9769 9770 u8 reserved_at_60[0x10]; 9771 u8 lwm[0x10]; 9772 }; 9773 9774 struct mlx5_ifc_arm_xrc_srq_out_bits { 9775 u8 status[0x8]; 9776 u8 reserved_at_8[0x18]; 9777 9778 u8 syndrome[0x20]; 9779 9780 u8 reserved_at_40[0x40]; 9781 }; 9782 9783 enum { 9784 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1, 9785 }; 9786 9787 struct mlx5_ifc_arm_xrc_srq_in_bits { 9788 u8 opcode[0x10]; 9789 u8 uid[0x10]; 9790 9791 u8 reserved_at_20[0x10]; 9792 u8 op_mod[0x10]; 9793 9794 u8 reserved_at_40[0x8]; 9795 u8 xrc_srqn[0x18]; 9796 9797 u8 reserved_at_60[0x10]; 9798 u8 lwm[0x10]; 9799 }; 9800 9801 struct mlx5_ifc_arm_rq_out_bits { 9802 u8 status[0x8]; 9803 u8 reserved_at_8[0x18]; 9804 9805 u8 syndrome[0x20]; 9806 9807 u8 reserved_at_40[0x40]; 9808 }; 9809 9810 enum { 9811 MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1, 9812 MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2, 9813 }; 9814 9815 struct mlx5_ifc_arm_rq_in_bits { 9816 u8 opcode[0x10]; 9817 u8 uid[0x10]; 9818 9819 u8 reserved_at_20[0x10]; 9820 u8 op_mod[0x10]; 9821 9822 u8 reserved_at_40[0x8]; 9823 u8 srq_number[0x18]; 9824 9825 u8 reserved_at_60[0x10]; 9826 u8 lwm[0x10]; 9827 }; 9828 9829 struct mlx5_ifc_arm_dct_out_bits { 9830 u8 status[0x8]; 9831 u8 reserved_at_8[0x18]; 9832 9833 u8 syndrome[0x20]; 9834 9835 u8 reserved_at_40[0x40]; 9836 }; 9837 9838 struct mlx5_ifc_arm_dct_in_bits { 9839 u8 opcode[0x10]; 9840 u8 reserved_at_10[0x10]; 9841 9842 u8 reserved_at_20[0x10]; 9843 u8 op_mod[0x10]; 9844 9845 u8 reserved_at_40[0x8]; 9846 u8 dct_number[0x18]; 9847 9848 u8 reserved_at_60[0x20]; 9849 }; 9850 9851 struct mlx5_ifc_alloc_xrcd_out_bits { 9852 u8 status[0x8]; 9853 u8 reserved_at_8[0x18]; 9854 9855 u8 syndrome[0x20]; 9856 9857 u8 reserved_at_40[0x8]; 9858 u8 xrcd[0x18]; 9859 9860 u8 reserved_at_60[0x20]; 9861 }; 9862 9863 struct mlx5_ifc_alloc_xrcd_in_bits { 9864 u8 opcode[0x10]; 9865 u8 uid[0x10]; 9866 9867 u8 reserved_at_20[0x10]; 9868 u8 op_mod[0x10]; 9869 9870 u8 reserved_at_40[0x40]; 9871 }; 9872 9873 struct mlx5_ifc_alloc_uar_out_bits { 9874 u8 status[0x8]; 9875 u8 reserved_at_8[0x18]; 9876 9877 u8 syndrome[0x20]; 9878 9879 u8 reserved_at_40[0x8]; 9880 u8 uar[0x18]; 9881 9882 u8 reserved_at_60[0x20]; 9883 }; 9884 9885 struct mlx5_ifc_alloc_uar_in_bits { 9886 u8 opcode[0x10]; 9887 u8 uid[0x10]; 9888 9889 u8 reserved_at_20[0x10]; 9890 u8 op_mod[0x10]; 9891 9892 u8 reserved_at_40[0x40]; 9893 }; 9894 9895 struct mlx5_ifc_alloc_transport_domain_out_bits { 9896 u8 status[0x8]; 9897 u8 reserved_at_8[0x18]; 9898 9899 u8 syndrome[0x20]; 9900 9901 u8 reserved_at_40[0x8]; 9902 u8 transport_domain[0x18]; 9903 9904 u8 reserved_at_60[0x20]; 9905 }; 9906 9907 struct mlx5_ifc_alloc_transport_domain_in_bits { 9908 u8 opcode[0x10]; 9909 u8 uid[0x10]; 9910 9911 u8 reserved_at_20[0x10]; 9912 u8 op_mod[0x10]; 9913 9914 u8 reserved_at_40[0x40]; 9915 }; 9916 9917 struct mlx5_ifc_alloc_q_counter_out_bits { 9918 u8 status[0x8]; 9919 u8 reserved_at_8[0x18]; 9920 9921 u8 syndrome[0x20]; 9922 9923 u8 reserved_at_40[0x18]; 9924 u8 counter_set_id[0x8]; 9925 9926 u8 reserved_at_60[0x20]; 9927 }; 9928 9929 struct mlx5_ifc_alloc_q_counter_in_bits { 9930 u8 opcode[0x10]; 9931 u8 uid[0x10]; 9932 9933 u8 reserved_at_20[0x10]; 9934 u8 op_mod[0x10]; 9935 9936 u8 reserved_at_40[0x40]; 9937 }; 9938 9939 struct mlx5_ifc_alloc_pd_out_bits { 9940 u8 status[0x8]; 9941 u8 reserved_at_8[0x18]; 9942 9943 u8 syndrome[0x20]; 9944 9945 u8 reserved_at_40[0x8]; 9946 u8 pd[0x18]; 9947 9948 u8 reserved_at_60[0x20]; 9949 }; 9950 9951 struct mlx5_ifc_alloc_pd_in_bits { 9952 u8 opcode[0x10]; 9953 u8 uid[0x10]; 9954 9955 u8 reserved_at_20[0x10]; 9956 u8 op_mod[0x10]; 9957 9958 u8 reserved_at_40[0x40]; 9959 }; 9960 9961 struct mlx5_ifc_alloc_flow_counter_out_bits { 9962 u8 status[0x8]; 9963 u8 reserved_at_8[0x18]; 9964 9965 u8 syndrome[0x20]; 9966 9967 u8 flow_counter_id[0x20]; 9968 9969 u8 reserved_at_60[0x20]; 9970 }; 9971 9972 struct mlx5_ifc_alloc_flow_counter_in_bits { 9973 u8 opcode[0x10]; 9974 u8 reserved_at_10[0x10]; 9975 9976 u8 reserved_at_20[0x10]; 9977 u8 op_mod[0x10]; 9978 9979 u8 reserved_at_40[0x33]; 9980 u8 flow_counter_bulk_log_size[0x5]; 9981 u8 flow_counter_bulk[0x8]; 9982 }; 9983 9984 struct mlx5_ifc_add_vxlan_udp_dport_out_bits { 9985 u8 status[0x8]; 9986 u8 reserved_at_8[0x18]; 9987 9988 u8 syndrome[0x20]; 9989 9990 u8 reserved_at_40[0x40]; 9991 }; 9992 9993 struct mlx5_ifc_add_vxlan_udp_dport_in_bits { 9994 u8 opcode[0x10]; 9995 u8 reserved_at_10[0x10]; 9996 9997 u8 reserved_at_20[0x10]; 9998 u8 op_mod[0x10]; 9999 10000 u8 reserved_at_40[0x20]; 10001 10002 u8 reserved_at_60[0x10]; 10003 u8 vxlan_udp_port[0x10]; 10004 }; 10005 10006 struct mlx5_ifc_set_pp_rate_limit_out_bits { 10007 u8 status[0x8]; 10008 u8 reserved_at_8[0x18]; 10009 10010 u8 syndrome[0x20]; 10011 10012 u8 reserved_at_40[0x40]; 10013 }; 10014 10015 struct mlx5_ifc_set_pp_rate_limit_context_bits { 10016 u8 rate_limit[0x20]; 10017 10018 u8 burst_upper_bound[0x20]; 10019 10020 u8 reserved_at_40[0x10]; 10021 u8 typical_packet_size[0x10]; 10022 10023 u8 reserved_at_60[0x120]; 10024 }; 10025 10026 struct mlx5_ifc_set_pp_rate_limit_in_bits { 10027 u8 opcode[0x10]; 10028 u8 uid[0x10]; 10029 10030 u8 reserved_at_20[0x10]; 10031 u8 op_mod[0x10]; 10032 10033 u8 reserved_at_40[0x10]; 10034 u8 rate_limit_index[0x10]; 10035 10036 u8 reserved_at_60[0x20]; 10037 10038 struct mlx5_ifc_set_pp_rate_limit_context_bits ctx; 10039 }; 10040 10041 struct mlx5_ifc_access_register_out_bits { 10042 u8 status[0x8]; 10043 u8 reserved_at_8[0x18]; 10044 10045 u8 syndrome[0x20]; 10046 10047 u8 reserved_at_40[0x40]; 10048 10049 u8 register_data[][0x20]; 10050 }; 10051 10052 enum { 10053 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0, 10054 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1, 10055 }; 10056 10057 struct mlx5_ifc_access_register_in_bits { 10058 u8 opcode[0x10]; 10059 u8 reserved_at_10[0x10]; 10060 10061 u8 reserved_at_20[0x10]; 10062 u8 op_mod[0x10]; 10063 10064 u8 reserved_at_40[0x10]; 10065 u8 register_id[0x10]; 10066 10067 u8 argument[0x20]; 10068 10069 u8 register_data[][0x20]; 10070 }; 10071 10072 struct mlx5_ifc_sltp_reg_bits { 10073 u8 status[0x4]; 10074 u8 version[0x4]; 10075 u8 local_port[0x8]; 10076 u8 pnat[0x2]; 10077 u8 reserved_at_12[0x2]; 10078 u8 lane[0x4]; 10079 u8 reserved_at_18[0x8]; 10080 10081 u8 reserved_at_20[0x20]; 10082 10083 u8 reserved_at_40[0x7]; 10084 u8 polarity[0x1]; 10085 u8 ob_tap0[0x8]; 10086 u8 ob_tap1[0x8]; 10087 u8 ob_tap2[0x8]; 10088 10089 u8 reserved_at_60[0xc]; 10090 u8 ob_preemp_mode[0x4]; 10091 u8 ob_reg[0x8]; 10092 u8 ob_bias[0x8]; 10093 10094 u8 reserved_at_80[0x20]; 10095 }; 10096 10097 struct mlx5_ifc_slrg_reg_bits { 10098 u8 status[0x4]; 10099 u8 version[0x4]; 10100 u8 local_port[0x8]; 10101 u8 pnat[0x2]; 10102 u8 reserved_at_12[0x2]; 10103 u8 lane[0x4]; 10104 u8 reserved_at_18[0x8]; 10105 10106 u8 time_to_link_up[0x10]; 10107 u8 reserved_at_30[0xc]; 10108 u8 grade_lane_speed[0x4]; 10109 10110 u8 grade_version[0x8]; 10111 u8 grade[0x18]; 10112 10113 u8 reserved_at_60[0x4]; 10114 u8 height_grade_type[0x4]; 10115 u8 height_grade[0x18]; 10116 10117 u8 height_dz[0x10]; 10118 u8 height_dv[0x10]; 10119 10120 u8 reserved_at_a0[0x10]; 10121 u8 height_sigma[0x10]; 10122 10123 u8 reserved_at_c0[0x20]; 10124 10125 u8 reserved_at_e0[0x4]; 10126 u8 phase_grade_type[0x4]; 10127 u8 phase_grade[0x18]; 10128 10129 u8 reserved_at_100[0x8]; 10130 u8 phase_eo_pos[0x8]; 10131 u8 reserved_at_110[0x8]; 10132 u8 phase_eo_neg[0x8]; 10133 10134 u8 ffe_set_tested[0x10]; 10135 u8 test_errors_per_lane[0x10]; 10136 }; 10137 10138 struct mlx5_ifc_pvlc_reg_bits { 10139 u8 reserved_at_0[0x8]; 10140 u8 local_port[0x8]; 10141 u8 reserved_at_10[0x10]; 10142 10143 u8 reserved_at_20[0x1c]; 10144 u8 vl_hw_cap[0x4]; 10145 10146 u8 reserved_at_40[0x1c]; 10147 u8 vl_admin[0x4]; 10148 10149 u8 reserved_at_60[0x1c]; 10150 u8 vl_operational[0x4]; 10151 }; 10152 10153 struct mlx5_ifc_pude_reg_bits { 10154 u8 swid[0x8]; 10155 u8 local_port[0x8]; 10156 u8 reserved_at_10[0x4]; 10157 u8 admin_status[0x4]; 10158 u8 reserved_at_18[0x4]; 10159 u8 oper_status[0x4]; 10160 10161 u8 reserved_at_20[0x60]; 10162 }; 10163 10164 enum { 10165 MLX5_PTYS_CONNECTOR_TYPE_PORT_DA = 0x7, 10166 }; 10167 10168 struct mlx5_ifc_ptys_reg_bits { 10169 u8 reserved_at_0[0x1]; 10170 u8 an_disable_admin[0x1]; 10171 u8 an_disable_cap[0x1]; 10172 u8 reserved_at_3[0x5]; 10173 u8 local_port[0x8]; 10174 u8 reserved_at_10[0x8]; 10175 u8 plane_ind[0x4]; 10176 u8 reserved_at_1c[0x1]; 10177 u8 proto_mask[0x3]; 10178 10179 u8 an_status[0x4]; 10180 u8 reserved_at_24[0xc]; 10181 u8 data_rate_oper[0x10]; 10182 10183 u8 ext_eth_proto_capability[0x20]; 10184 10185 u8 eth_proto_capability[0x20]; 10186 10187 u8 ib_link_width_capability[0x10]; 10188 u8 ib_proto_capability[0x10]; 10189 10190 u8 ext_eth_proto_admin[0x20]; 10191 10192 u8 eth_proto_admin[0x20]; 10193 10194 u8 ib_link_width_admin[0x10]; 10195 u8 ib_proto_admin[0x10]; 10196 10197 u8 ext_eth_proto_oper[0x20]; 10198 10199 u8 eth_proto_oper[0x20]; 10200 10201 u8 ib_link_width_oper[0x10]; 10202 u8 ib_proto_oper[0x10]; 10203 10204 u8 reserved_at_160[0x8]; 10205 u8 lane_rate_oper[0x14]; 10206 u8 connector_type[0x4]; 10207 10208 u8 eth_proto_lp_advertise[0x20]; 10209 10210 u8 reserved_at_1a0[0x60]; 10211 }; 10212 10213 struct mlx5_ifc_mlcr_reg_bits { 10214 u8 reserved_at_0[0x8]; 10215 u8 local_port[0x8]; 10216 u8 reserved_at_10[0x20]; 10217 10218 u8 beacon_duration[0x10]; 10219 u8 reserved_at_40[0x10]; 10220 10221 u8 beacon_remain[0x10]; 10222 }; 10223 10224 struct mlx5_ifc_ptas_reg_bits { 10225 u8 reserved_at_0[0x20]; 10226 10227 u8 algorithm_options[0x10]; 10228 u8 reserved_at_30[0x4]; 10229 u8 repetitions_mode[0x4]; 10230 u8 num_of_repetitions[0x8]; 10231 10232 u8 grade_version[0x8]; 10233 u8 height_grade_type[0x4]; 10234 u8 phase_grade_type[0x4]; 10235 u8 height_grade_weight[0x8]; 10236 u8 phase_grade_weight[0x8]; 10237 10238 u8 gisim_measure_bits[0x10]; 10239 u8 adaptive_tap_measure_bits[0x10]; 10240 10241 u8 ber_bath_high_error_threshold[0x10]; 10242 u8 ber_bath_mid_error_threshold[0x10]; 10243 10244 u8 ber_bath_low_error_threshold[0x10]; 10245 u8 one_ratio_high_threshold[0x10]; 10246 10247 u8 one_ratio_high_mid_threshold[0x10]; 10248 u8 one_ratio_low_mid_threshold[0x10]; 10249 10250 u8 one_ratio_low_threshold[0x10]; 10251 u8 ndeo_error_threshold[0x10]; 10252 10253 u8 mixer_offset_step_size[0x10]; 10254 u8 reserved_at_110[0x8]; 10255 u8 mix90_phase_for_voltage_bath[0x8]; 10256 10257 u8 mixer_offset_start[0x10]; 10258 u8 mixer_offset_end[0x10]; 10259 10260 u8 reserved_at_140[0x15]; 10261 u8 ber_test_time[0xb]; 10262 }; 10263 10264 struct mlx5_ifc_pspa_reg_bits { 10265 u8 swid[0x8]; 10266 u8 local_port[0x8]; 10267 u8 sub_port[0x8]; 10268 u8 reserved_at_18[0x8]; 10269 10270 u8 reserved_at_20[0x20]; 10271 }; 10272 10273 struct mlx5_ifc_pqdr_reg_bits { 10274 u8 reserved_at_0[0x8]; 10275 u8 local_port[0x8]; 10276 u8 reserved_at_10[0x5]; 10277 u8 prio[0x3]; 10278 u8 reserved_at_18[0x6]; 10279 u8 mode[0x2]; 10280 10281 u8 reserved_at_20[0x20]; 10282 10283 u8 reserved_at_40[0x10]; 10284 u8 min_threshold[0x10]; 10285 10286 u8 reserved_at_60[0x10]; 10287 u8 max_threshold[0x10]; 10288 10289 u8 reserved_at_80[0x10]; 10290 u8 mark_probability_denominator[0x10]; 10291 10292 u8 reserved_at_a0[0x60]; 10293 }; 10294 10295 struct mlx5_ifc_ppsc_reg_bits { 10296 u8 reserved_at_0[0x8]; 10297 u8 local_port[0x8]; 10298 u8 reserved_at_10[0x10]; 10299 10300 u8 reserved_at_20[0x60]; 10301 10302 u8 reserved_at_80[0x1c]; 10303 u8 wrps_admin[0x4]; 10304 10305 u8 reserved_at_a0[0x1c]; 10306 u8 wrps_status[0x4]; 10307 10308 u8 reserved_at_c0[0x8]; 10309 u8 up_threshold[0x8]; 10310 u8 reserved_at_d0[0x8]; 10311 u8 down_threshold[0x8]; 10312 10313 u8 reserved_at_e0[0x20]; 10314 10315 u8 reserved_at_100[0x1c]; 10316 u8 srps_admin[0x4]; 10317 10318 u8 reserved_at_120[0x1c]; 10319 u8 srps_status[0x4]; 10320 10321 u8 reserved_at_140[0x40]; 10322 }; 10323 10324 struct mlx5_ifc_pplr_reg_bits { 10325 u8 reserved_at_0[0x8]; 10326 u8 local_port[0x8]; 10327 u8 reserved_at_10[0x10]; 10328 10329 u8 reserved_at_20[0x8]; 10330 u8 lb_cap[0x8]; 10331 u8 reserved_at_30[0x8]; 10332 u8 lb_en[0x8]; 10333 }; 10334 10335 struct mlx5_ifc_pplm_reg_bits { 10336 u8 reserved_at_0[0x8]; 10337 u8 local_port[0x8]; 10338 u8 reserved_at_10[0x10]; 10339 10340 u8 reserved_at_20[0x20]; 10341 10342 u8 port_profile_mode[0x8]; 10343 u8 static_port_profile[0x8]; 10344 u8 active_port_profile[0x8]; 10345 u8 reserved_at_58[0x8]; 10346 10347 u8 retransmission_active[0x8]; 10348 u8 fec_mode_active[0x18]; 10349 10350 u8 rs_fec_correction_bypass_cap[0x4]; 10351 u8 reserved_at_84[0x8]; 10352 u8 fec_override_cap_56g[0x4]; 10353 u8 fec_override_cap_100g[0x4]; 10354 u8 fec_override_cap_50g[0x4]; 10355 u8 fec_override_cap_25g[0x4]; 10356 u8 fec_override_cap_10g_40g[0x4]; 10357 10358 u8 rs_fec_correction_bypass_admin[0x4]; 10359 u8 reserved_at_a4[0x8]; 10360 u8 fec_override_admin_56g[0x4]; 10361 u8 fec_override_admin_100g[0x4]; 10362 u8 fec_override_admin_50g[0x4]; 10363 u8 fec_override_admin_25g[0x4]; 10364 u8 fec_override_admin_10g_40g[0x4]; 10365 10366 u8 fec_override_cap_400g_8x[0x10]; 10367 u8 fec_override_cap_200g_4x[0x10]; 10368 10369 u8 fec_override_cap_100g_2x[0x10]; 10370 u8 fec_override_cap_50g_1x[0x10]; 10371 10372 u8 fec_override_admin_400g_8x[0x10]; 10373 u8 fec_override_admin_200g_4x[0x10]; 10374 10375 u8 fec_override_admin_100g_2x[0x10]; 10376 u8 fec_override_admin_50g_1x[0x10]; 10377 10378 u8 fec_override_cap_800g_8x[0x10]; 10379 u8 fec_override_cap_400g_4x[0x10]; 10380 10381 u8 fec_override_cap_200g_2x[0x10]; 10382 u8 fec_override_cap_100g_1x[0x10]; 10383 10384 u8 reserved_at_180[0xa0]; 10385 10386 u8 fec_override_admin_800g_8x[0x10]; 10387 u8 fec_override_admin_400g_4x[0x10]; 10388 10389 u8 fec_override_admin_200g_2x[0x10]; 10390 u8 fec_override_admin_100g_1x[0x10]; 10391 10392 u8 reserved_at_260[0x60]; 10393 10394 u8 fec_override_cap_1600g_8x[0x10]; 10395 u8 fec_override_cap_800g_4x[0x10]; 10396 10397 u8 fec_override_cap_400g_2x[0x10]; 10398 u8 fec_override_cap_200g_1x[0x10]; 10399 10400 u8 fec_override_admin_1600g_8x[0x10]; 10401 u8 fec_override_admin_800g_4x[0x10]; 10402 10403 u8 fec_override_admin_400g_2x[0x10]; 10404 u8 fec_override_admin_200g_1x[0x10]; 10405 10406 u8 reserved_at_340[0x80]; 10407 }; 10408 10409 struct mlx5_ifc_ppcnt_reg_bits { 10410 u8 swid[0x8]; 10411 u8 local_port[0x8]; 10412 u8 pnat[0x2]; 10413 u8 reserved_at_12[0x8]; 10414 u8 grp[0x6]; 10415 10416 u8 clr[0x1]; 10417 u8 reserved_at_21[0x13]; 10418 u8 plane_ind[0x4]; 10419 u8 reserved_at_38[0x3]; 10420 u8 prio_tc[0x5]; 10421 10422 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set; 10423 }; 10424 10425 struct mlx5_ifc_mpein_reg_bits { 10426 u8 reserved_at_0[0x2]; 10427 u8 depth[0x6]; 10428 u8 pcie_index[0x8]; 10429 u8 node[0x8]; 10430 u8 reserved_at_18[0x8]; 10431 10432 u8 capability_mask[0x20]; 10433 10434 u8 reserved_at_40[0x8]; 10435 u8 link_width_enabled[0x8]; 10436 u8 link_speed_enabled[0x10]; 10437 10438 u8 lane0_physical_position[0x8]; 10439 u8 link_width_active[0x8]; 10440 u8 link_speed_active[0x10]; 10441 10442 u8 num_of_pfs[0x10]; 10443 u8 num_of_vfs[0x10]; 10444 10445 u8 bdf0[0x10]; 10446 u8 reserved_at_b0[0x10]; 10447 10448 u8 max_read_request_size[0x4]; 10449 u8 max_payload_size[0x4]; 10450 u8 reserved_at_c8[0x5]; 10451 u8 pwr_status[0x3]; 10452 u8 port_type[0x4]; 10453 u8 reserved_at_d4[0xb]; 10454 u8 lane_reversal[0x1]; 10455 10456 u8 reserved_at_e0[0x14]; 10457 u8 pci_power[0xc]; 10458 10459 u8 reserved_at_100[0x20]; 10460 10461 u8 device_status[0x10]; 10462 u8 port_state[0x8]; 10463 u8 reserved_at_138[0x8]; 10464 10465 u8 reserved_at_140[0x10]; 10466 u8 receiver_detect_result[0x10]; 10467 10468 u8 reserved_at_160[0x20]; 10469 }; 10470 10471 struct mlx5_ifc_mpcnt_reg_bits { 10472 u8 reserved_at_0[0x8]; 10473 u8 pcie_index[0x8]; 10474 u8 reserved_at_10[0xa]; 10475 u8 grp[0x6]; 10476 10477 u8 clr[0x1]; 10478 u8 reserved_at_21[0x1f]; 10479 10480 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set; 10481 }; 10482 10483 struct mlx5_ifc_ppad_reg_bits { 10484 u8 reserved_at_0[0x3]; 10485 u8 single_mac[0x1]; 10486 u8 reserved_at_4[0x4]; 10487 u8 local_port[0x8]; 10488 u8 mac_47_32[0x10]; 10489 10490 u8 mac_31_0[0x20]; 10491 10492 u8 reserved_at_40[0x40]; 10493 }; 10494 10495 struct mlx5_ifc_pmtu_reg_bits { 10496 u8 reserved_at_0[0x8]; 10497 u8 local_port[0x8]; 10498 u8 reserved_at_10[0x10]; 10499 10500 u8 max_mtu[0x10]; 10501 u8 reserved_at_30[0x10]; 10502 10503 u8 admin_mtu[0x10]; 10504 u8 reserved_at_50[0x10]; 10505 10506 u8 oper_mtu[0x10]; 10507 u8 reserved_at_70[0x10]; 10508 }; 10509 10510 struct mlx5_ifc_pmpr_reg_bits { 10511 u8 reserved_at_0[0x8]; 10512 u8 module[0x8]; 10513 u8 reserved_at_10[0x10]; 10514 10515 u8 reserved_at_20[0x18]; 10516 u8 attenuation_5g[0x8]; 10517 10518 u8 reserved_at_40[0x18]; 10519 u8 attenuation_7g[0x8]; 10520 10521 u8 reserved_at_60[0x18]; 10522 u8 attenuation_12g[0x8]; 10523 }; 10524 10525 struct mlx5_ifc_pmpe_reg_bits { 10526 u8 reserved_at_0[0x8]; 10527 u8 module[0x8]; 10528 u8 reserved_at_10[0xc]; 10529 u8 module_status[0x4]; 10530 10531 u8 reserved_at_20[0x60]; 10532 }; 10533 10534 struct mlx5_ifc_pmpc_reg_bits { 10535 u8 module_state_updated[32][0x8]; 10536 }; 10537 10538 struct mlx5_ifc_pmlpn_reg_bits { 10539 u8 reserved_at_0[0x4]; 10540 u8 mlpn_status[0x4]; 10541 u8 local_port[0x8]; 10542 u8 reserved_at_10[0x10]; 10543 10544 u8 e[0x1]; 10545 u8 reserved_at_21[0x1f]; 10546 }; 10547 10548 struct mlx5_ifc_pmlp_reg_bits { 10549 u8 rxtx[0x1]; 10550 u8 reserved_at_1[0x7]; 10551 u8 local_port[0x8]; 10552 u8 reserved_at_10[0x8]; 10553 u8 width[0x8]; 10554 10555 u8 lane0_module_mapping[0x20]; 10556 10557 u8 lane1_module_mapping[0x20]; 10558 10559 u8 lane2_module_mapping[0x20]; 10560 10561 u8 lane3_module_mapping[0x20]; 10562 10563 u8 reserved_at_a0[0x160]; 10564 }; 10565 10566 struct mlx5_ifc_pmaos_reg_bits { 10567 u8 reserved_at_0[0x8]; 10568 u8 module[0x8]; 10569 u8 reserved_at_10[0x4]; 10570 u8 admin_status[0x4]; 10571 u8 reserved_at_18[0x4]; 10572 u8 oper_status[0x4]; 10573 10574 u8 ase[0x1]; 10575 u8 ee[0x1]; 10576 u8 reserved_at_22[0x1c]; 10577 u8 e[0x2]; 10578 10579 u8 reserved_at_40[0x40]; 10580 }; 10581 10582 struct mlx5_ifc_plpc_reg_bits { 10583 u8 reserved_at_0[0x4]; 10584 u8 profile_id[0xc]; 10585 u8 reserved_at_10[0x4]; 10586 u8 proto_mask[0x4]; 10587 u8 reserved_at_18[0x8]; 10588 10589 u8 reserved_at_20[0x10]; 10590 u8 lane_speed[0x10]; 10591 10592 u8 reserved_at_40[0x17]; 10593 u8 lpbf[0x1]; 10594 u8 fec_mode_policy[0x8]; 10595 10596 u8 retransmission_capability[0x8]; 10597 u8 fec_mode_capability[0x18]; 10598 10599 u8 retransmission_support_admin[0x8]; 10600 u8 fec_mode_support_admin[0x18]; 10601 10602 u8 retransmission_request_admin[0x8]; 10603 u8 fec_mode_request_admin[0x18]; 10604 10605 u8 reserved_at_c0[0x80]; 10606 }; 10607 10608 struct mlx5_ifc_plib_reg_bits { 10609 u8 reserved_at_0[0x8]; 10610 u8 local_port[0x8]; 10611 u8 reserved_at_10[0x8]; 10612 u8 ib_port[0x8]; 10613 10614 u8 reserved_at_20[0x60]; 10615 }; 10616 10617 struct mlx5_ifc_plbf_reg_bits { 10618 u8 reserved_at_0[0x8]; 10619 u8 local_port[0x8]; 10620 u8 reserved_at_10[0xd]; 10621 u8 lbf_mode[0x3]; 10622 10623 u8 reserved_at_20[0x20]; 10624 }; 10625 10626 struct mlx5_ifc_pipg_reg_bits { 10627 u8 reserved_at_0[0x8]; 10628 u8 local_port[0x8]; 10629 u8 reserved_at_10[0x10]; 10630 10631 u8 dic[0x1]; 10632 u8 reserved_at_21[0x19]; 10633 u8 ipg[0x4]; 10634 u8 reserved_at_3e[0x2]; 10635 }; 10636 10637 struct mlx5_ifc_pifr_reg_bits { 10638 u8 reserved_at_0[0x8]; 10639 u8 local_port[0x8]; 10640 u8 reserved_at_10[0x10]; 10641 10642 u8 reserved_at_20[0xe0]; 10643 10644 u8 port_filter[8][0x20]; 10645 10646 u8 port_filter_update_en[8][0x20]; 10647 }; 10648 10649 enum { 10650 MLX5_BUF_OWNERSHIP_UNKNOWN = 0x0, 10651 MLX5_BUF_OWNERSHIP_FW_OWNED = 0x1, 10652 MLX5_BUF_OWNERSHIP_SW_OWNED = 0x2, 10653 }; 10654 10655 struct mlx5_ifc_pfcc_reg_bits { 10656 u8 reserved_at_0[0x4]; 10657 u8 buf_ownership[0x2]; 10658 u8 reserved_at_6[0x2]; 10659 u8 local_port[0x8]; 10660 u8 reserved_at_10[0xa]; 10661 u8 cable_length_mask[0x1]; 10662 u8 ppan_mask_n[0x1]; 10663 u8 minor_stall_mask[0x1]; 10664 u8 critical_stall_mask[0x1]; 10665 u8 reserved_at_1e[0x2]; 10666 10667 u8 ppan[0x4]; 10668 u8 reserved_at_24[0x4]; 10669 u8 prio_mask_tx[0x8]; 10670 u8 reserved_at_30[0x8]; 10671 u8 prio_mask_rx[0x8]; 10672 10673 u8 pptx[0x1]; 10674 u8 aptx[0x1]; 10675 u8 pptx_mask_n[0x1]; 10676 u8 reserved_at_43[0x5]; 10677 u8 pfctx[0x8]; 10678 u8 reserved_at_50[0x10]; 10679 10680 u8 pprx[0x1]; 10681 u8 aprx[0x1]; 10682 u8 pprx_mask_n[0x1]; 10683 u8 reserved_at_63[0x5]; 10684 u8 pfcrx[0x8]; 10685 u8 reserved_at_70[0x10]; 10686 10687 u8 device_stall_minor_watermark[0x10]; 10688 u8 device_stall_critical_watermark[0x10]; 10689 10690 u8 reserved_at_a0[0x18]; 10691 u8 cable_length[0x8]; 10692 10693 u8 reserved_at_c0[0x40]; 10694 }; 10695 10696 struct mlx5_ifc_pelc_reg_bits { 10697 u8 op[0x4]; 10698 u8 reserved_at_4[0x4]; 10699 u8 local_port[0x8]; 10700 u8 reserved_at_10[0x10]; 10701 10702 u8 op_admin[0x8]; 10703 u8 op_capability[0x8]; 10704 u8 op_request[0x8]; 10705 u8 op_active[0x8]; 10706 10707 u8 admin[0x40]; 10708 10709 u8 capability[0x40]; 10710 10711 u8 request[0x40]; 10712 10713 u8 active[0x40]; 10714 10715 u8 reserved_at_140[0x80]; 10716 }; 10717 10718 struct mlx5_ifc_peir_reg_bits { 10719 u8 reserved_at_0[0x8]; 10720 u8 local_port[0x8]; 10721 u8 reserved_at_10[0x10]; 10722 10723 u8 reserved_at_20[0xc]; 10724 u8 error_count[0x4]; 10725 u8 reserved_at_30[0x10]; 10726 10727 u8 reserved_at_40[0xc]; 10728 u8 lane[0x4]; 10729 u8 reserved_at_50[0x8]; 10730 u8 error_type[0x8]; 10731 }; 10732 10733 struct mlx5_ifc_mpegc_reg_bits { 10734 u8 reserved_at_0[0x30]; 10735 u8 field_select[0x10]; 10736 10737 u8 tx_overflow_sense[0x1]; 10738 u8 mark_cqe[0x1]; 10739 u8 mark_cnp[0x1]; 10740 u8 reserved_at_43[0x1b]; 10741 u8 tx_lossy_overflow_oper[0x2]; 10742 10743 u8 reserved_at_60[0x100]; 10744 }; 10745 10746 struct mlx5_ifc_mpir_reg_bits { 10747 u8 sdm[0x1]; 10748 u8 reserved_at_1[0x1b]; 10749 u8 host_buses[0x4]; 10750 10751 u8 reserved_at_20[0x20]; 10752 10753 u8 local_port[0x8]; 10754 u8 reserved_at_28[0x18]; 10755 10756 u8 reserved_at_60[0x20]; 10757 }; 10758 10759 enum { 10760 MLX5_MTUTC_FREQ_ADJ_UNITS_PPB = 0x0, 10761 MLX5_MTUTC_FREQ_ADJ_UNITS_SCALED_PPM = 0x1, 10762 }; 10763 10764 enum { 10765 MLX5_MTUTC_OPERATION_SET_TIME_IMMEDIATE = 0x1, 10766 MLX5_MTUTC_OPERATION_ADJUST_TIME = 0x2, 10767 MLX5_MTUTC_OPERATION_ADJUST_FREQ_UTC = 0x3, 10768 }; 10769 10770 struct mlx5_ifc_mtutc_reg_bits { 10771 u8 reserved_at_0[0x5]; 10772 u8 freq_adj_units[0x3]; 10773 u8 reserved_at_8[0x3]; 10774 u8 log_max_freq_adjustment[0x5]; 10775 10776 u8 reserved_at_10[0xc]; 10777 u8 operation[0x4]; 10778 10779 u8 freq_adjustment[0x20]; 10780 10781 u8 reserved_at_40[0x40]; 10782 10783 u8 utc_sec[0x20]; 10784 10785 u8 reserved_at_a0[0x2]; 10786 u8 utc_nsec[0x1e]; 10787 10788 u8 time_adjustment[0x20]; 10789 }; 10790 10791 struct mlx5_ifc_pcam_enhanced_features_bits { 10792 u8 reserved_at_0[0x10]; 10793 u8 ppcnt_recovery_counters[0x1]; 10794 u8 reserved_at_11[0x7]; 10795 u8 cable_length[0x1]; 10796 u8 reserved_at_19[0x4]; 10797 u8 fec_200G_per_lane_in_pplm[0x1]; 10798 u8 reserved_at_1e[0x2a]; 10799 u8 fec_100G_per_lane_in_pplm[0x1]; 10800 u8 reserved_at_49[0xa]; 10801 u8 buffer_ownership[0x1]; 10802 u8 resereved_at_54[0x14]; 10803 u8 fec_50G_per_lane_in_pplm[0x1]; 10804 u8 reserved_at_69[0x4]; 10805 u8 rx_icrc_encapsulated_counter[0x1]; 10806 u8 reserved_at_6e[0x4]; 10807 u8 ptys_extended_ethernet[0x1]; 10808 u8 reserved_at_73[0x3]; 10809 u8 pfcc_mask[0x1]; 10810 u8 reserved_at_77[0x3]; 10811 u8 per_lane_error_counters[0x1]; 10812 u8 rx_buffer_fullness_counters[0x1]; 10813 u8 ptys_connector_type[0x1]; 10814 u8 reserved_at_7d[0x1]; 10815 u8 ppcnt_discard_group[0x1]; 10816 u8 ppcnt_statistical_group[0x1]; 10817 }; 10818 10819 struct mlx5_ifc_pcam_regs_5000_to_507f_bits { 10820 u8 port_access_reg_cap_mask_127_to_96[0x20]; 10821 u8 port_access_reg_cap_mask_95_to_64[0x20]; 10822 10823 u8 port_access_reg_cap_mask_63_to_36[0x1c]; 10824 u8 pplm[0x1]; 10825 u8 port_access_reg_cap_mask_34_to_32[0x3]; 10826 10827 u8 port_access_reg_cap_mask_31_to_13[0x13]; 10828 u8 pbmc[0x1]; 10829 u8 pptb[0x1]; 10830 u8 port_access_reg_cap_mask_10_to_09[0x2]; 10831 u8 ppcnt[0x1]; 10832 u8 port_access_reg_cap_mask_07_to_00[0x8]; 10833 }; 10834 10835 struct mlx5_ifc_pcam_reg_bits { 10836 u8 reserved_at_0[0x8]; 10837 u8 feature_group[0x8]; 10838 u8 reserved_at_10[0x8]; 10839 u8 access_reg_group[0x8]; 10840 10841 u8 reserved_at_20[0x20]; 10842 10843 union { 10844 struct mlx5_ifc_pcam_regs_5000_to_507f_bits regs_5000_to_507f; 10845 u8 reserved_at_0[0x80]; 10846 } port_access_reg_cap_mask; 10847 10848 u8 reserved_at_c0[0x80]; 10849 10850 union { 10851 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features; 10852 u8 reserved_at_0[0x80]; 10853 } feature_cap_mask; 10854 10855 u8 reserved_at_1c0[0xc0]; 10856 }; 10857 10858 struct mlx5_ifc_mcam_enhanced_features_bits { 10859 u8 reserved_at_0[0x50]; 10860 u8 mtutc_freq_adj_units[0x1]; 10861 u8 mtutc_time_adjustment_extended_range[0x1]; 10862 u8 reserved_at_52[0xb]; 10863 u8 mcia_32dwords[0x1]; 10864 u8 out_pulse_duration_ns[0x1]; 10865 u8 npps_period[0x1]; 10866 u8 reserved_at_60[0xa]; 10867 u8 reset_state[0x1]; 10868 u8 ptpcyc2realtime_modify[0x1]; 10869 u8 reserved_at_6c[0x2]; 10870 u8 pci_status_and_power[0x1]; 10871 u8 reserved_at_6f[0x5]; 10872 u8 mark_tx_action_cnp[0x1]; 10873 u8 mark_tx_action_cqe[0x1]; 10874 u8 dynamic_tx_overflow[0x1]; 10875 u8 reserved_at_77[0x4]; 10876 u8 pcie_outbound_stalled[0x1]; 10877 u8 tx_overflow_buffer_pkt[0x1]; 10878 u8 mtpps_enh_out_per_adj[0x1]; 10879 u8 mtpps_fs[0x1]; 10880 u8 pcie_performance_group[0x1]; 10881 }; 10882 10883 struct mlx5_ifc_mcam_access_reg_bits { 10884 u8 reserved_at_0[0x1c]; 10885 u8 mcda[0x1]; 10886 u8 mcc[0x1]; 10887 u8 mcqi[0x1]; 10888 u8 mcqs[0x1]; 10889 10890 u8 regs_95_to_90[0x6]; 10891 u8 mpir[0x1]; 10892 u8 regs_88_to_87[0x2]; 10893 u8 mpegc[0x1]; 10894 u8 mtutc[0x1]; 10895 u8 regs_84_to_68[0x11]; 10896 u8 tracer_registers[0x4]; 10897 10898 u8 regs_63_to_46[0x12]; 10899 u8 mrtc[0x1]; 10900 u8 regs_44_to_41[0x4]; 10901 u8 mfrl[0x1]; 10902 u8 regs_39_to_32[0x8]; 10903 10904 u8 regs_31_to_11[0x15]; 10905 u8 mtmp[0x1]; 10906 u8 regs_9_to_0[0xa]; 10907 }; 10908 10909 struct mlx5_ifc_mcam_access_reg_bits1 { 10910 u8 regs_127_to_96[0x20]; 10911 10912 u8 regs_95_to_64[0x20]; 10913 10914 u8 regs_63_to_32[0x20]; 10915 10916 u8 regs_31_to_0[0x20]; 10917 }; 10918 10919 struct mlx5_ifc_mcam_access_reg_bits2 { 10920 u8 regs_127_to_99[0x1d]; 10921 u8 mirc[0x1]; 10922 u8 regs_97_to_96[0x2]; 10923 10924 u8 regs_95_to_87[0x09]; 10925 u8 synce_registers[0x2]; 10926 u8 regs_84_to_64[0x15]; 10927 10928 u8 regs_63_to_32[0x20]; 10929 10930 u8 regs_31_to_0[0x20]; 10931 }; 10932 10933 struct mlx5_ifc_mcam_access_reg_bits3 { 10934 u8 regs_127_to_96[0x20]; 10935 10936 u8 regs_95_to_64[0x20]; 10937 10938 u8 regs_63_to_32[0x20]; 10939 10940 u8 regs_31_to_3[0x1d]; 10941 u8 mrtcq[0x1]; 10942 u8 mtctr[0x1]; 10943 u8 mtptm[0x1]; 10944 }; 10945 10946 struct mlx5_ifc_mcam_reg_bits { 10947 u8 reserved_at_0[0x8]; 10948 u8 feature_group[0x8]; 10949 u8 reserved_at_10[0x8]; 10950 u8 access_reg_group[0x8]; 10951 10952 u8 reserved_at_20[0x20]; 10953 10954 union { 10955 struct mlx5_ifc_mcam_access_reg_bits access_regs; 10956 struct mlx5_ifc_mcam_access_reg_bits1 access_regs1; 10957 struct mlx5_ifc_mcam_access_reg_bits2 access_regs2; 10958 struct mlx5_ifc_mcam_access_reg_bits3 access_regs3; 10959 u8 reserved_at_0[0x80]; 10960 } mng_access_reg_cap_mask; 10961 10962 u8 reserved_at_c0[0x80]; 10963 10964 union { 10965 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features; 10966 u8 reserved_at_0[0x80]; 10967 } mng_feature_cap_mask; 10968 10969 u8 reserved_at_1c0[0x80]; 10970 }; 10971 10972 struct mlx5_ifc_qcam_access_reg_cap_mask { 10973 u8 qcam_access_reg_cap_mask_127_to_20[0x6C]; 10974 u8 qpdpm[0x1]; 10975 u8 qcam_access_reg_cap_mask_18_to_4[0x0F]; 10976 u8 qdpm[0x1]; 10977 u8 qpts[0x1]; 10978 u8 qcap[0x1]; 10979 u8 qcam_access_reg_cap_mask_0[0x1]; 10980 }; 10981 10982 struct mlx5_ifc_qcam_qos_feature_cap_mask { 10983 u8 qcam_qos_feature_cap_mask_127_to_1[0x7F]; 10984 u8 qpts_trust_both[0x1]; 10985 }; 10986 10987 struct mlx5_ifc_qcam_reg_bits { 10988 u8 reserved_at_0[0x8]; 10989 u8 feature_group[0x8]; 10990 u8 reserved_at_10[0x8]; 10991 u8 access_reg_group[0x8]; 10992 u8 reserved_at_20[0x20]; 10993 10994 union { 10995 struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap; 10996 u8 reserved_at_0[0x80]; 10997 } qos_access_reg_cap_mask; 10998 10999 u8 reserved_at_c0[0x80]; 11000 11001 union { 11002 struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap; 11003 u8 reserved_at_0[0x80]; 11004 } qos_feature_cap_mask; 11005 11006 u8 reserved_at_1c0[0x80]; 11007 }; 11008 11009 struct mlx5_ifc_core_dump_reg_bits { 11010 u8 reserved_at_0[0x18]; 11011 u8 core_dump_type[0x8]; 11012 11013 u8 reserved_at_20[0x30]; 11014 u8 vhca_id[0x10]; 11015 11016 u8 reserved_at_60[0x8]; 11017 u8 qpn[0x18]; 11018 u8 reserved_at_80[0x180]; 11019 }; 11020 11021 struct mlx5_ifc_pcap_reg_bits { 11022 u8 reserved_at_0[0x8]; 11023 u8 local_port[0x8]; 11024 u8 reserved_at_10[0x10]; 11025 11026 u8 port_capability_mask[4][0x20]; 11027 }; 11028 11029 struct mlx5_ifc_paos_reg_bits { 11030 u8 swid[0x8]; 11031 u8 local_port[0x8]; 11032 u8 reserved_at_10[0x4]; 11033 u8 admin_status[0x4]; 11034 u8 reserved_at_18[0x4]; 11035 u8 oper_status[0x4]; 11036 11037 u8 ase[0x1]; 11038 u8 ee[0x1]; 11039 u8 reserved_at_22[0x1c]; 11040 u8 e[0x2]; 11041 11042 u8 reserved_at_40[0x40]; 11043 }; 11044 11045 struct mlx5_ifc_pamp_reg_bits { 11046 u8 reserved_at_0[0x8]; 11047 u8 opamp_group[0x8]; 11048 u8 reserved_at_10[0xc]; 11049 u8 opamp_group_type[0x4]; 11050 11051 u8 start_index[0x10]; 11052 u8 reserved_at_30[0x4]; 11053 u8 num_of_indices[0xc]; 11054 11055 u8 index_data[18][0x10]; 11056 }; 11057 11058 struct mlx5_ifc_pcmr_reg_bits { 11059 u8 reserved_at_0[0x8]; 11060 u8 local_port[0x8]; 11061 u8 reserved_at_10[0x10]; 11062 11063 u8 entropy_force_cap[0x1]; 11064 u8 entropy_calc_cap[0x1]; 11065 u8 entropy_gre_calc_cap[0x1]; 11066 u8 reserved_at_23[0xf]; 11067 u8 rx_ts_over_crc_cap[0x1]; 11068 u8 reserved_at_33[0xb]; 11069 u8 fcs_cap[0x1]; 11070 u8 reserved_at_3f[0x1]; 11071 11072 u8 entropy_force[0x1]; 11073 u8 entropy_calc[0x1]; 11074 u8 entropy_gre_calc[0x1]; 11075 u8 reserved_at_43[0xf]; 11076 u8 rx_ts_over_crc[0x1]; 11077 u8 reserved_at_53[0xb]; 11078 u8 fcs_chk[0x1]; 11079 u8 reserved_at_5f[0x1]; 11080 }; 11081 11082 struct mlx5_ifc_lane_2_module_mapping_bits { 11083 u8 reserved_at_0[0x4]; 11084 u8 rx_lane[0x4]; 11085 u8 reserved_at_8[0x4]; 11086 u8 tx_lane[0x4]; 11087 u8 reserved_at_10[0x8]; 11088 u8 module[0x8]; 11089 }; 11090 11091 struct mlx5_ifc_bufferx_reg_bits { 11092 u8 reserved_at_0[0x6]; 11093 u8 lossy[0x1]; 11094 u8 epsb[0x1]; 11095 u8 reserved_at_8[0x8]; 11096 u8 size[0x10]; 11097 11098 u8 xoff_threshold[0x10]; 11099 u8 xon_threshold[0x10]; 11100 }; 11101 11102 struct mlx5_ifc_set_node_in_bits { 11103 u8 node_description[64][0x8]; 11104 }; 11105 11106 struct mlx5_ifc_register_power_settings_bits { 11107 u8 reserved_at_0[0x18]; 11108 u8 power_settings_level[0x8]; 11109 11110 u8 reserved_at_20[0x60]; 11111 }; 11112 11113 struct mlx5_ifc_register_host_endianness_bits { 11114 u8 he[0x1]; 11115 u8 reserved_at_1[0x1f]; 11116 11117 u8 reserved_at_20[0x60]; 11118 }; 11119 11120 struct mlx5_ifc_umr_pointer_desc_argument_bits { 11121 u8 reserved_at_0[0x20]; 11122 11123 u8 mkey[0x20]; 11124 11125 u8 addressh_63_32[0x20]; 11126 11127 u8 addressl_31_0[0x20]; 11128 }; 11129 11130 struct mlx5_ifc_ud_adrs_vector_bits { 11131 u8 dc_key[0x40]; 11132 11133 u8 ext[0x1]; 11134 u8 reserved_at_41[0x7]; 11135 u8 destination_qp_dct[0x18]; 11136 11137 u8 static_rate[0x4]; 11138 u8 sl_eth_prio[0x4]; 11139 u8 fl[0x1]; 11140 u8 mlid[0x7]; 11141 u8 rlid_udp_sport[0x10]; 11142 11143 u8 reserved_at_80[0x20]; 11144 11145 u8 rmac_47_16[0x20]; 11146 11147 u8 rmac_15_0[0x10]; 11148 u8 tclass[0x8]; 11149 u8 hop_limit[0x8]; 11150 11151 u8 reserved_at_e0[0x1]; 11152 u8 grh[0x1]; 11153 u8 reserved_at_e2[0x2]; 11154 u8 src_addr_index[0x8]; 11155 u8 flow_label[0x14]; 11156 11157 u8 rgid_rip[16][0x8]; 11158 }; 11159 11160 struct mlx5_ifc_pages_req_event_bits { 11161 u8 reserved_at_0[0x10]; 11162 u8 function_id[0x10]; 11163 11164 u8 num_pages[0x20]; 11165 11166 u8 reserved_at_40[0xa0]; 11167 }; 11168 11169 struct mlx5_ifc_eqe_bits { 11170 u8 reserved_at_0[0x8]; 11171 u8 event_type[0x8]; 11172 u8 reserved_at_10[0x8]; 11173 u8 event_sub_type[0x8]; 11174 11175 u8 reserved_at_20[0xe0]; 11176 11177 union mlx5_ifc_event_auto_bits event_data; 11178 11179 u8 reserved_at_1e0[0x10]; 11180 u8 signature[0x8]; 11181 u8 reserved_at_1f8[0x7]; 11182 u8 owner[0x1]; 11183 }; 11184 11185 enum { 11186 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7, 11187 }; 11188 11189 struct mlx5_ifc_cmd_queue_entry_bits { 11190 u8 type[0x8]; 11191 u8 reserved_at_8[0x18]; 11192 11193 u8 input_length[0x20]; 11194 11195 u8 input_mailbox_pointer_63_32[0x20]; 11196 11197 u8 input_mailbox_pointer_31_9[0x17]; 11198 u8 reserved_at_77[0x9]; 11199 11200 u8 command_input_inline_data[16][0x8]; 11201 11202 u8 command_output_inline_data[16][0x8]; 11203 11204 u8 output_mailbox_pointer_63_32[0x20]; 11205 11206 u8 output_mailbox_pointer_31_9[0x17]; 11207 u8 reserved_at_1b7[0x9]; 11208 11209 u8 output_length[0x20]; 11210 11211 u8 token[0x8]; 11212 u8 signature[0x8]; 11213 u8 reserved_at_1f0[0x8]; 11214 u8 status[0x7]; 11215 u8 ownership[0x1]; 11216 }; 11217 11218 struct mlx5_ifc_cmd_out_bits { 11219 u8 status[0x8]; 11220 u8 reserved_at_8[0x18]; 11221 11222 u8 syndrome[0x20]; 11223 11224 u8 command_output[0x20]; 11225 }; 11226 11227 struct mlx5_ifc_cmd_in_bits { 11228 u8 opcode[0x10]; 11229 u8 reserved_at_10[0x10]; 11230 11231 u8 reserved_at_20[0x10]; 11232 u8 op_mod[0x10]; 11233 11234 u8 command[][0x20]; 11235 }; 11236 11237 struct mlx5_ifc_cmd_if_box_bits { 11238 u8 mailbox_data[512][0x8]; 11239 11240 u8 reserved_at_1000[0x180]; 11241 11242 u8 next_pointer_63_32[0x20]; 11243 11244 u8 next_pointer_31_10[0x16]; 11245 u8 reserved_at_11b6[0xa]; 11246 11247 u8 block_number[0x20]; 11248 11249 u8 reserved_at_11e0[0x8]; 11250 u8 token[0x8]; 11251 u8 ctrl_signature[0x8]; 11252 u8 signature[0x8]; 11253 }; 11254 11255 struct mlx5_ifc_mtt_bits { 11256 u8 ptag_63_32[0x20]; 11257 11258 u8 ptag_31_8[0x18]; 11259 u8 reserved_at_38[0x6]; 11260 u8 wr_en[0x1]; 11261 u8 rd_en[0x1]; 11262 }; 11263 11264 struct mlx5_ifc_query_wol_rol_out_bits { 11265 u8 status[0x8]; 11266 u8 reserved_at_8[0x18]; 11267 11268 u8 syndrome[0x20]; 11269 11270 u8 reserved_at_40[0x10]; 11271 u8 rol_mode[0x8]; 11272 u8 wol_mode[0x8]; 11273 11274 u8 reserved_at_60[0x20]; 11275 }; 11276 11277 struct mlx5_ifc_query_wol_rol_in_bits { 11278 u8 opcode[0x10]; 11279 u8 reserved_at_10[0x10]; 11280 11281 u8 reserved_at_20[0x10]; 11282 u8 op_mod[0x10]; 11283 11284 u8 reserved_at_40[0x40]; 11285 }; 11286 11287 struct mlx5_ifc_set_wol_rol_out_bits { 11288 u8 status[0x8]; 11289 u8 reserved_at_8[0x18]; 11290 11291 u8 syndrome[0x20]; 11292 11293 u8 reserved_at_40[0x40]; 11294 }; 11295 11296 struct mlx5_ifc_set_wol_rol_in_bits { 11297 u8 opcode[0x10]; 11298 u8 reserved_at_10[0x10]; 11299 11300 u8 reserved_at_20[0x10]; 11301 u8 op_mod[0x10]; 11302 11303 u8 rol_mode_valid[0x1]; 11304 u8 wol_mode_valid[0x1]; 11305 u8 reserved_at_42[0xe]; 11306 u8 rol_mode[0x8]; 11307 u8 wol_mode[0x8]; 11308 11309 u8 reserved_at_60[0x20]; 11310 }; 11311 11312 enum { 11313 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0, 11314 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1, 11315 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2, 11316 MLX5_INITIAL_SEG_NIC_INTERFACE_SW_RESET = 0x7, 11317 }; 11318 11319 enum { 11320 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0, 11321 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1, 11322 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2, 11323 }; 11324 11325 enum { 11326 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR = 0x1, 11327 MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC = 0x7, 11328 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR = 0x8, 11329 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR = 0x9, 11330 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR = 0xa, 11331 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR = 0xb, 11332 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN = 0xc, 11333 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR = 0xd, 11334 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV = 0xe, 11335 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR = 0xf, 11336 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR = 0x10, 11337 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PCI_POISONED_ERR = 0x12, 11338 MLX5_INITIAL_SEG_HEALTH_SYNDROME_TRUST_LOCKDOWN_ERR = 0x13, 11339 }; 11340 11341 struct mlx5_ifc_initial_seg_bits { 11342 u8 fw_rev_minor[0x10]; 11343 u8 fw_rev_major[0x10]; 11344 11345 u8 cmd_interface_rev[0x10]; 11346 u8 fw_rev_subminor[0x10]; 11347 11348 u8 reserved_at_40[0x40]; 11349 11350 u8 cmdq_phy_addr_63_32[0x20]; 11351 11352 u8 cmdq_phy_addr_31_12[0x14]; 11353 u8 reserved_at_b4[0x2]; 11354 u8 nic_interface[0x2]; 11355 u8 log_cmdq_size[0x4]; 11356 u8 log_cmdq_stride[0x4]; 11357 11358 u8 command_doorbell_vector[0x20]; 11359 11360 u8 reserved_at_e0[0xf00]; 11361 11362 u8 initializing[0x1]; 11363 u8 reserved_at_fe1[0x4]; 11364 u8 nic_interface_supported[0x3]; 11365 u8 embedded_cpu[0x1]; 11366 u8 reserved_at_fe9[0x17]; 11367 11368 struct mlx5_ifc_health_buffer_bits health_buffer; 11369 11370 u8 no_dram_nic_offset[0x20]; 11371 11372 u8 reserved_at_1220[0x6e40]; 11373 11374 u8 reserved_at_8060[0x1f]; 11375 u8 clear_int[0x1]; 11376 11377 u8 health_syndrome[0x8]; 11378 u8 health_counter[0x18]; 11379 11380 u8 reserved_at_80a0[0x17fc0]; 11381 }; 11382 11383 struct mlx5_ifc_mtpps_reg_bits { 11384 u8 reserved_at_0[0xc]; 11385 u8 cap_number_of_pps_pins[0x4]; 11386 u8 reserved_at_10[0x4]; 11387 u8 cap_max_num_of_pps_in_pins[0x4]; 11388 u8 reserved_at_18[0x4]; 11389 u8 cap_max_num_of_pps_out_pins[0x4]; 11390 11391 u8 reserved_at_20[0x13]; 11392 u8 cap_log_min_npps_period[0x5]; 11393 u8 reserved_at_38[0x3]; 11394 u8 cap_log_min_out_pulse_duration_ns[0x5]; 11395 11396 u8 reserved_at_40[0x4]; 11397 u8 cap_pin_3_mode[0x4]; 11398 u8 reserved_at_48[0x4]; 11399 u8 cap_pin_2_mode[0x4]; 11400 u8 reserved_at_50[0x4]; 11401 u8 cap_pin_1_mode[0x4]; 11402 u8 reserved_at_58[0x4]; 11403 u8 cap_pin_0_mode[0x4]; 11404 11405 u8 reserved_at_60[0x4]; 11406 u8 cap_pin_7_mode[0x4]; 11407 u8 reserved_at_68[0x4]; 11408 u8 cap_pin_6_mode[0x4]; 11409 u8 reserved_at_70[0x4]; 11410 u8 cap_pin_5_mode[0x4]; 11411 u8 reserved_at_78[0x4]; 11412 u8 cap_pin_4_mode[0x4]; 11413 11414 u8 field_select[0x20]; 11415 u8 reserved_at_a0[0x20]; 11416 11417 u8 npps_period[0x40]; 11418 11419 u8 enable[0x1]; 11420 u8 reserved_at_101[0xb]; 11421 u8 pattern[0x4]; 11422 u8 reserved_at_110[0x4]; 11423 u8 pin_mode[0x4]; 11424 u8 pin[0x8]; 11425 11426 u8 reserved_at_120[0x2]; 11427 u8 out_pulse_duration_ns[0x1e]; 11428 11429 u8 time_stamp[0x40]; 11430 11431 u8 out_pulse_duration[0x10]; 11432 u8 out_periodic_adjustment[0x10]; 11433 u8 enhanced_out_periodic_adjustment[0x20]; 11434 11435 u8 reserved_at_1c0[0x20]; 11436 }; 11437 11438 struct mlx5_ifc_mtppse_reg_bits { 11439 u8 reserved_at_0[0x18]; 11440 u8 pin[0x8]; 11441 u8 event_arm[0x1]; 11442 u8 reserved_at_21[0x1b]; 11443 u8 event_generation_mode[0x4]; 11444 u8 reserved_at_40[0x40]; 11445 }; 11446 11447 struct mlx5_ifc_mcqs_reg_bits { 11448 u8 last_index_flag[0x1]; 11449 u8 reserved_at_1[0x7]; 11450 u8 fw_device[0x8]; 11451 u8 component_index[0x10]; 11452 11453 u8 reserved_at_20[0x10]; 11454 u8 identifier[0x10]; 11455 11456 u8 reserved_at_40[0x17]; 11457 u8 component_status[0x5]; 11458 u8 component_update_state[0x4]; 11459 11460 u8 last_update_state_changer_type[0x4]; 11461 u8 last_update_state_changer_host_id[0x4]; 11462 u8 reserved_at_68[0x18]; 11463 }; 11464 11465 struct mlx5_ifc_mcqi_cap_bits { 11466 u8 supported_info_bitmask[0x20]; 11467 11468 u8 component_size[0x20]; 11469 11470 u8 max_component_size[0x20]; 11471 11472 u8 log_mcda_word_size[0x4]; 11473 u8 reserved_at_64[0xc]; 11474 u8 mcda_max_write_size[0x10]; 11475 11476 u8 rd_en[0x1]; 11477 u8 reserved_at_81[0x1]; 11478 u8 match_chip_id[0x1]; 11479 u8 match_psid[0x1]; 11480 u8 check_user_timestamp[0x1]; 11481 u8 match_base_guid_mac[0x1]; 11482 u8 reserved_at_86[0x1a]; 11483 }; 11484 11485 struct mlx5_ifc_mcqi_version_bits { 11486 u8 reserved_at_0[0x2]; 11487 u8 build_time_valid[0x1]; 11488 u8 user_defined_time_valid[0x1]; 11489 u8 reserved_at_4[0x14]; 11490 u8 version_string_length[0x8]; 11491 11492 u8 version[0x20]; 11493 11494 u8 build_time[0x40]; 11495 11496 u8 user_defined_time[0x40]; 11497 11498 u8 build_tool_version[0x20]; 11499 11500 u8 reserved_at_e0[0x20]; 11501 11502 u8 version_string[92][0x8]; 11503 }; 11504 11505 struct mlx5_ifc_mcqi_activation_method_bits { 11506 u8 pending_server_ac_power_cycle[0x1]; 11507 u8 pending_server_dc_power_cycle[0x1]; 11508 u8 pending_server_reboot[0x1]; 11509 u8 pending_fw_reset[0x1]; 11510 u8 auto_activate[0x1]; 11511 u8 all_hosts_sync[0x1]; 11512 u8 device_hw_reset[0x1]; 11513 u8 reserved_at_7[0x19]; 11514 }; 11515 11516 union mlx5_ifc_mcqi_reg_data_bits { 11517 struct mlx5_ifc_mcqi_cap_bits mcqi_caps; 11518 struct mlx5_ifc_mcqi_version_bits mcqi_version; 11519 struct mlx5_ifc_mcqi_activation_method_bits mcqi_activation_mathod; 11520 }; 11521 11522 struct mlx5_ifc_mcqi_reg_bits { 11523 u8 read_pending_component[0x1]; 11524 u8 reserved_at_1[0xf]; 11525 u8 component_index[0x10]; 11526 11527 u8 reserved_at_20[0x20]; 11528 11529 u8 reserved_at_40[0x1b]; 11530 u8 info_type[0x5]; 11531 11532 u8 info_size[0x20]; 11533 11534 u8 offset[0x20]; 11535 11536 u8 reserved_at_a0[0x10]; 11537 u8 data_size[0x10]; 11538 11539 union mlx5_ifc_mcqi_reg_data_bits data[]; 11540 }; 11541 11542 struct mlx5_ifc_mcc_reg_bits { 11543 u8 reserved_at_0[0x4]; 11544 u8 time_elapsed_since_last_cmd[0xc]; 11545 u8 reserved_at_10[0x8]; 11546 u8 instruction[0x8]; 11547 11548 u8 reserved_at_20[0x10]; 11549 u8 component_index[0x10]; 11550 11551 u8 reserved_at_40[0x8]; 11552 u8 update_handle[0x18]; 11553 11554 u8 handle_owner_type[0x4]; 11555 u8 handle_owner_host_id[0x4]; 11556 u8 reserved_at_68[0x1]; 11557 u8 control_progress[0x7]; 11558 u8 error_code[0x8]; 11559 u8 reserved_at_78[0x4]; 11560 u8 control_state[0x4]; 11561 11562 u8 component_size[0x20]; 11563 11564 u8 reserved_at_a0[0x60]; 11565 }; 11566 11567 struct mlx5_ifc_mcda_reg_bits { 11568 u8 reserved_at_0[0x8]; 11569 u8 update_handle[0x18]; 11570 11571 u8 offset[0x20]; 11572 11573 u8 reserved_at_40[0x10]; 11574 u8 size[0x10]; 11575 11576 u8 reserved_at_60[0x20]; 11577 11578 u8 data[][0x20]; 11579 }; 11580 11581 enum { 11582 MLX5_MFRL_REG_PCI_RESET_METHOD_LINK_TOGGLE = 0, 11583 MLX5_MFRL_REG_PCI_RESET_METHOD_HOT_RESET = 1, 11584 }; 11585 11586 enum { 11587 MLX5_MFRL_REG_RESET_STATE_IDLE = 0, 11588 MLX5_MFRL_REG_RESET_STATE_IN_NEGOTIATION = 1, 11589 MLX5_MFRL_REG_RESET_STATE_RESET_IN_PROGRESS = 2, 11590 MLX5_MFRL_REG_RESET_STATE_NEG_TIMEOUT = 3, 11591 MLX5_MFRL_REG_RESET_STATE_NACK = 4, 11592 MLX5_MFRL_REG_RESET_STATE_UNLOAD_TIMEOUT = 5, 11593 }; 11594 11595 enum { 11596 MLX5_MFRL_REG_RESET_TYPE_FULL_CHIP = BIT(0), 11597 MLX5_MFRL_REG_RESET_TYPE_NET_PORT_ALIVE = BIT(1), 11598 }; 11599 11600 enum { 11601 MLX5_MFRL_REG_RESET_LEVEL0 = BIT(0), 11602 MLX5_MFRL_REG_RESET_LEVEL3 = BIT(3), 11603 MLX5_MFRL_REG_RESET_LEVEL6 = BIT(6), 11604 }; 11605 11606 struct mlx5_ifc_mfrl_reg_bits { 11607 u8 reserved_at_0[0x20]; 11608 11609 u8 reserved_at_20[0x2]; 11610 u8 pci_sync_for_fw_update_start[0x1]; 11611 u8 pci_sync_for_fw_update_resp[0x2]; 11612 u8 rst_type_sel[0x3]; 11613 u8 pci_reset_req_method[0x3]; 11614 u8 reserved_at_2b[0x1]; 11615 u8 reset_state[0x4]; 11616 u8 reset_type[0x8]; 11617 u8 reset_level[0x8]; 11618 }; 11619 11620 struct mlx5_ifc_mirc_reg_bits { 11621 u8 reserved_at_0[0x18]; 11622 u8 status_code[0x8]; 11623 11624 u8 reserved_at_20[0x20]; 11625 }; 11626 11627 struct mlx5_ifc_pddr_monitor_opcode_bits { 11628 u8 reserved_at_0[0x10]; 11629 u8 monitor_opcode[0x10]; 11630 }; 11631 11632 union mlx5_ifc_pddr_troubleshooting_page_status_opcode_auto_bits { 11633 struct mlx5_ifc_pddr_monitor_opcode_bits pddr_monitor_opcode; 11634 u8 reserved_at_0[0x20]; 11635 }; 11636 11637 enum { 11638 /* Monitor opcodes */ 11639 MLX5_PDDR_REG_TRBLSH_GROUP_OPCODE_MONITOR = 0x0, 11640 }; 11641 11642 struct mlx5_ifc_pddr_troubleshooting_page_bits { 11643 u8 reserved_at_0[0x10]; 11644 u8 group_opcode[0x10]; 11645 11646 union mlx5_ifc_pddr_troubleshooting_page_status_opcode_auto_bits status_opcode; 11647 11648 u8 reserved_at_40[0x20]; 11649 11650 u8 status_message[59][0x20]; 11651 }; 11652 11653 union mlx5_ifc_pddr_reg_page_data_auto_bits { 11654 struct mlx5_ifc_pddr_troubleshooting_page_bits pddr_troubleshooting_page; 11655 u8 reserved_at_0[0x7c0]; 11656 }; 11657 11658 enum { 11659 MLX5_PDDR_REG_PAGE_SELECT_TROUBLESHOOTING_INFO_PAGE = 0x1, 11660 }; 11661 11662 struct mlx5_ifc_pddr_reg_bits { 11663 u8 reserved_at_0[0x8]; 11664 u8 local_port[0x8]; 11665 u8 pnat[0x2]; 11666 u8 reserved_at_12[0xe]; 11667 11668 u8 reserved_at_20[0x18]; 11669 u8 page_select[0x8]; 11670 11671 union mlx5_ifc_pddr_reg_page_data_auto_bits page_data; 11672 }; 11673 11674 struct mlx5_ifc_mrtc_reg_bits { 11675 u8 time_synced[0x1]; 11676 u8 reserved_at_1[0x1f]; 11677 11678 u8 reserved_at_20[0x20]; 11679 11680 u8 time_h[0x20]; 11681 11682 u8 time_l[0x20]; 11683 }; 11684 11685 struct mlx5_ifc_mtcap_reg_bits { 11686 u8 reserved_at_0[0x19]; 11687 u8 sensor_count[0x7]; 11688 11689 u8 reserved_at_20[0x20]; 11690 11691 u8 sensor_map[0x40]; 11692 }; 11693 11694 struct mlx5_ifc_mtmp_reg_bits { 11695 u8 reserved_at_0[0x14]; 11696 u8 sensor_index[0xc]; 11697 11698 u8 reserved_at_20[0x10]; 11699 u8 temperature[0x10]; 11700 11701 u8 mte[0x1]; 11702 u8 mtr[0x1]; 11703 u8 reserved_at_42[0xe]; 11704 u8 max_temperature[0x10]; 11705 11706 u8 tee[0x2]; 11707 u8 reserved_at_62[0xe]; 11708 u8 temp_threshold_hi[0x10]; 11709 11710 u8 reserved_at_80[0x10]; 11711 u8 temp_threshold_lo[0x10]; 11712 11713 u8 reserved_at_a0[0x20]; 11714 11715 u8 sensor_name_hi[0x20]; 11716 u8 sensor_name_lo[0x20]; 11717 }; 11718 11719 struct mlx5_ifc_mtptm_reg_bits { 11720 u8 reserved_at_0[0x10]; 11721 u8 psta[0x1]; 11722 u8 reserved_at_11[0xf]; 11723 11724 u8 reserved_at_20[0x60]; 11725 }; 11726 11727 enum { 11728 MLX5_MTCTR_REQUEST_NOP = 0x0, 11729 MLX5_MTCTR_REQUEST_PTM_ROOT_CLOCK = 0x1, 11730 MLX5_MTCTR_REQUEST_FREE_RUNNING_COUNTER = 0x2, 11731 MLX5_MTCTR_REQUEST_REAL_TIME_CLOCK = 0x3, 11732 }; 11733 11734 struct mlx5_ifc_mtctr_reg_bits { 11735 u8 first_clock_timestamp_request[0x8]; 11736 u8 second_clock_timestamp_request[0x8]; 11737 u8 reserved_at_10[0x10]; 11738 11739 u8 first_clock_valid[0x1]; 11740 u8 second_clock_valid[0x1]; 11741 u8 reserved_at_22[0x1e]; 11742 11743 u8 first_clock_timestamp[0x40]; 11744 u8 second_clock_timestamp[0x40]; 11745 }; 11746 11747 struct mlx5_ifc_bin_range_layout_bits { 11748 u8 reserved_at_0[0xa]; 11749 u8 high_val[0x6]; 11750 u8 reserved_at_10[0xa]; 11751 u8 low_val[0x6]; 11752 }; 11753 11754 struct mlx5_ifc_pphcr_reg_bits { 11755 u8 active_hist_type[0x4]; 11756 u8 reserved_at_4[0x4]; 11757 u8 local_port[0x8]; 11758 u8 reserved_at_10[0x10]; 11759 11760 u8 reserved_at_20[0x8]; 11761 u8 num_of_bins[0x8]; 11762 u8 reserved_at_30[0x10]; 11763 11764 u8 reserved_at_40[0x40]; 11765 11766 struct mlx5_ifc_bin_range_layout_bits bin_range[16]; 11767 }; 11768 11769 union mlx5_ifc_ports_control_registers_document_bits { 11770 struct mlx5_ifc_bufferx_reg_bits bufferx_reg; 11771 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 11772 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 11773 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 11774 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 11775 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 11776 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 11777 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout; 11778 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout; 11779 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping; 11780 struct mlx5_ifc_pamp_reg_bits pamp_reg; 11781 struct mlx5_ifc_paos_reg_bits paos_reg; 11782 struct mlx5_ifc_pcap_reg_bits pcap_reg; 11783 struct mlx5_ifc_pddr_monitor_opcode_bits pddr_monitor_opcode; 11784 struct mlx5_ifc_pddr_reg_bits pddr_reg; 11785 struct mlx5_ifc_pddr_troubleshooting_page_bits pddr_troubleshooting_page; 11786 struct mlx5_ifc_peir_reg_bits peir_reg; 11787 struct mlx5_ifc_pelc_reg_bits pelc_reg; 11788 struct mlx5_ifc_pfcc_reg_bits pfcc_reg; 11789 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 11790 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 11791 struct mlx5_ifc_pifr_reg_bits pifr_reg; 11792 struct mlx5_ifc_pipg_reg_bits pipg_reg; 11793 struct mlx5_ifc_plbf_reg_bits plbf_reg; 11794 struct mlx5_ifc_plib_reg_bits plib_reg; 11795 struct mlx5_ifc_plpc_reg_bits plpc_reg; 11796 struct mlx5_ifc_pmaos_reg_bits pmaos_reg; 11797 struct mlx5_ifc_pmlp_reg_bits pmlp_reg; 11798 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg; 11799 struct mlx5_ifc_pmpc_reg_bits pmpc_reg; 11800 struct mlx5_ifc_pmpe_reg_bits pmpe_reg; 11801 struct mlx5_ifc_pmpr_reg_bits pmpr_reg; 11802 struct mlx5_ifc_pmtu_reg_bits pmtu_reg; 11803 struct mlx5_ifc_ppad_reg_bits ppad_reg; 11804 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg; 11805 struct mlx5_ifc_mpein_reg_bits mpein_reg; 11806 struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg; 11807 struct mlx5_ifc_pplm_reg_bits pplm_reg; 11808 struct mlx5_ifc_pplr_reg_bits pplr_reg; 11809 struct mlx5_ifc_ppsc_reg_bits ppsc_reg; 11810 struct mlx5_ifc_pqdr_reg_bits pqdr_reg; 11811 struct mlx5_ifc_pspa_reg_bits pspa_reg; 11812 struct mlx5_ifc_ptas_reg_bits ptas_reg; 11813 struct mlx5_ifc_ptys_reg_bits ptys_reg; 11814 struct mlx5_ifc_mlcr_reg_bits mlcr_reg; 11815 struct mlx5_ifc_pude_reg_bits pude_reg; 11816 struct mlx5_ifc_pvlc_reg_bits pvlc_reg; 11817 struct mlx5_ifc_slrg_reg_bits slrg_reg; 11818 struct mlx5_ifc_sltp_reg_bits sltp_reg; 11819 struct mlx5_ifc_mtpps_reg_bits mtpps_reg; 11820 struct mlx5_ifc_mtppse_reg_bits mtppse_reg; 11821 struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg; 11822 struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits; 11823 struct mlx5_ifc_fpga_cap_bits fpga_cap_bits; 11824 struct mlx5_ifc_mcqi_reg_bits mcqi_reg; 11825 struct mlx5_ifc_mcc_reg_bits mcc_reg; 11826 struct mlx5_ifc_mcda_reg_bits mcda_reg; 11827 struct mlx5_ifc_mirc_reg_bits mirc_reg; 11828 struct mlx5_ifc_mfrl_reg_bits mfrl_reg; 11829 struct mlx5_ifc_mtutc_reg_bits mtutc_reg; 11830 struct mlx5_ifc_mrtc_reg_bits mrtc_reg; 11831 struct mlx5_ifc_mtcap_reg_bits mtcap_reg; 11832 struct mlx5_ifc_mtmp_reg_bits mtmp_reg; 11833 struct mlx5_ifc_mtptm_reg_bits mtptm_reg; 11834 struct mlx5_ifc_mtctr_reg_bits mtctr_reg; 11835 struct mlx5_ifc_pphcr_reg_bits pphcr_reg; 11836 u8 reserved_at_0[0x60e0]; 11837 }; 11838 11839 union mlx5_ifc_debug_enhancements_document_bits { 11840 struct mlx5_ifc_health_buffer_bits health_buffer; 11841 u8 reserved_at_0[0x200]; 11842 }; 11843 11844 union mlx5_ifc_uplink_pci_interface_document_bits { 11845 struct mlx5_ifc_initial_seg_bits initial_seg; 11846 u8 reserved_at_0[0x20060]; 11847 }; 11848 11849 struct mlx5_ifc_set_flow_table_root_out_bits { 11850 u8 status[0x8]; 11851 u8 reserved_at_8[0x18]; 11852 11853 u8 syndrome[0x20]; 11854 11855 u8 reserved_at_40[0x40]; 11856 }; 11857 11858 struct mlx5_ifc_set_flow_table_root_in_bits { 11859 u8 opcode[0x10]; 11860 u8 reserved_at_10[0x10]; 11861 11862 u8 reserved_at_20[0x10]; 11863 u8 op_mod[0x10]; 11864 11865 u8 other_vport[0x1]; 11866 u8 reserved_at_41[0xf]; 11867 u8 vport_number[0x10]; 11868 11869 u8 reserved_at_60[0x20]; 11870 11871 u8 table_type[0x8]; 11872 u8 reserved_at_88[0x7]; 11873 u8 table_of_other_vport[0x1]; 11874 u8 table_vport_number[0x10]; 11875 11876 u8 reserved_at_a0[0x8]; 11877 u8 table_id[0x18]; 11878 11879 u8 reserved_at_c0[0x8]; 11880 u8 underlay_qpn[0x18]; 11881 u8 table_eswitch_owner_vhca_id_valid[0x1]; 11882 u8 reserved_at_e1[0xf]; 11883 u8 table_eswitch_owner_vhca_id[0x10]; 11884 u8 reserved_at_100[0x100]; 11885 }; 11886 11887 enum { 11888 MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = (1UL << 0), 11889 MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15), 11890 }; 11891 11892 struct mlx5_ifc_modify_flow_table_out_bits { 11893 u8 status[0x8]; 11894 u8 reserved_at_8[0x18]; 11895 11896 u8 syndrome[0x20]; 11897 11898 u8 reserved_at_40[0x40]; 11899 }; 11900 11901 struct mlx5_ifc_modify_flow_table_in_bits { 11902 u8 opcode[0x10]; 11903 u8 reserved_at_10[0x10]; 11904 11905 u8 reserved_at_20[0x10]; 11906 u8 op_mod[0x10]; 11907 11908 u8 other_vport[0x1]; 11909 u8 reserved_at_41[0xf]; 11910 u8 vport_number[0x10]; 11911 11912 u8 reserved_at_60[0x10]; 11913 u8 modify_field_select[0x10]; 11914 11915 u8 table_type[0x8]; 11916 u8 reserved_at_88[0x18]; 11917 11918 u8 reserved_at_a0[0x8]; 11919 u8 table_id[0x18]; 11920 11921 struct mlx5_ifc_flow_table_context_bits flow_table_context; 11922 }; 11923 11924 struct mlx5_ifc_ets_tcn_config_reg_bits { 11925 u8 g[0x1]; 11926 u8 b[0x1]; 11927 u8 r[0x1]; 11928 u8 reserved_at_3[0x9]; 11929 u8 group[0x4]; 11930 u8 reserved_at_10[0x9]; 11931 u8 bw_allocation[0x7]; 11932 11933 u8 reserved_at_20[0xc]; 11934 u8 max_bw_units[0x4]; 11935 u8 reserved_at_30[0x8]; 11936 u8 max_bw_value[0x8]; 11937 }; 11938 11939 struct mlx5_ifc_ets_global_config_reg_bits { 11940 u8 reserved_at_0[0x2]; 11941 u8 r[0x1]; 11942 u8 reserved_at_3[0x1d]; 11943 11944 u8 reserved_at_20[0xc]; 11945 u8 max_bw_units[0x4]; 11946 u8 reserved_at_30[0x8]; 11947 u8 max_bw_value[0x8]; 11948 }; 11949 11950 struct mlx5_ifc_qetc_reg_bits { 11951 u8 reserved_at_0[0x8]; 11952 u8 port_number[0x8]; 11953 u8 reserved_at_10[0x30]; 11954 11955 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8]; 11956 struct mlx5_ifc_ets_global_config_reg_bits global_configuration; 11957 }; 11958 11959 struct mlx5_ifc_qpdpm_dscp_reg_bits { 11960 u8 e[0x1]; 11961 u8 reserved_at_01[0x0b]; 11962 u8 prio[0x04]; 11963 }; 11964 11965 struct mlx5_ifc_qpdpm_reg_bits { 11966 u8 reserved_at_0[0x8]; 11967 u8 local_port[0x8]; 11968 u8 reserved_at_10[0x10]; 11969 struct mlx5_ifc_qpdpm_dscp_reg_bits dscp[64]; 11970 }; 11971 11972 struct mlx5_ifc_qpts_reg_bits { 11973 u8 reserved_at_0[0x8]; 11974 u8 local_port[0x8]; 11975 u8 reserved_at_10[0x2d]; 11976 u8 trust_state[0x3]; 11977 }; 11978 11979 struct mlx5_ifc_pptb_reg_bits { 11980 u8 reserved_at_0[0x2]; 11981 u8 mm[0x2]; 11982 u8 reserved_at_4[0x4]; 11983 u8 local_port[0x8]; 11984 u8 reserved_at_10[0x6]; 11985 u8 cm[0x1]; 11986 u8 um[0x1]; 11987 u8 pm[0x8]; 11988 11989 u8 prio_x_buff[0x20]; 11990 11991 u8 pm_msb[0x8]; 11992 u8 reserved_at_48[0x10]; 11993 u8 ctrl_buff[0x4]; 11994 u8 untagged_buff[0x4]; 11995 }; 11996 11997 struct mlx5_ifc_sbcam_reg_bits { 11998 u8 reserved_at_0[0x8]; 11999 u8 feature_group[0x8]; 12000 u8 reserved_at_10[0x8]; 12001 u8 access_reg_group[0x8]; 12002 12003 u8 reserved_at_20[0x20]; 12004 12005 u8 sb_access_reg_cap_mask[4][0x20]; 12006 12007 u8 reserved_at_c0[0x80]; 12008 12009 u8 sb_feature_cap_mask[4][0x20]; 12010 12011 u8 reserved_at_1c0[0x40]; 12012 12013 u8 cap_total_buffer_size[0x20]; 12014 12015 u8 cap_cell_size[0x10]; 12016 u8 cap_max_pg_buffers[0x8]; 12017 u8 cap_num_pool_supported[0x8]; 12018 12019 u8 reserved_at_240[0x8]; 12020 u8 cap_sbsr_stat_size[0x8]; 12021 u8 cap_max_tclass_data[0x8]; 12022 u8 cap_max_cpu_ingress_tclass_sb[0x8]; 12023 }; 12024 12025 struct mlx5_ifc_pbmc_reg_bits { 12026 u8 reserved_at_0[0x8]; 12027 u8 local_port[0x8]; 12028 u8 reserved_at_10[0x10]; 12029 12030 u8 xoff_timer_value[0x10]; 12031 u8 xoff_refresh[0x10]; 12032 12033 u8 reserved_at_40[0x9]; 12034 u8 fullness_threshold[0x7]; 12035 u8 port_buffer_size[0x10]; 12036 12037 struct mlx5_ifc_bufferx_reg_bits buffer[10]; 12038 12039 u8 reserved_at_2e0[0x80]; 12040 }; 12041 12042 struct mlx5_ifc_sbpr_reg_bits { 12043 u8 desc[0x1]; 12044 u8 snap[0x1]; 12045 u8 reserved_at_2[0x4]; 12046 u8 dir[0x2]; 12047 u8 reserved_at_8[0x14]; 12048 u8 pool[0x4]; 12049 12050 u8 infi_size[0x1]; 12051 u8 reserved_at_21[0x7]; 12052 u8 size[0x18]; 12053 12054 u8 reserved_at_40[0x1c]; 12055 u8 mode[0x4]; 12056 12057 u8 reserved_at_60[0x8]; 12058 u8 buff_occupancy[0x18]; 12059 12060 u8 clr[0x1]; 12061 u8 reserved_at_81[0x7]; 12062 u8 max_buff_occupancy[0x18]; 12063 12064 u8 reserved_at_a0[0x8]; 12065 u8 ext_buff_occupancy[0x18]; 12066 }; 12067 12068 struct mlx5_ifc_sbcm_reg_bits { 12069 u8 desc[0x1]; 12070 u8 snap[0x1]; 12071 u8 reserved_at_2[0x6]; 12072 u8 local_port[0x8]; 12073 u8 pnat[0x2]; 12074 u8 pg_buff[0x6]; 12075 u8 reserved_at_18[0x6]; 12076 u8 dir[0x2]; 12077 12078 u8 reserved_at_20[0x1f]; 12079 u8 exc[0x1]; 12080 12081 u8 reserved_at_40[0x40]; 12082 12083 u8 reserved_at_80[0x8]; 12084 u8 buff_occupancy[0x18]; 12085 12086 u8 clr[0x1]; 12087 u8 reserved_at_a1[0x7]; 12088 u8 max_buff_occupancy[0x18]; 12089 12090 u8 reserved_at_c0[0x8]; 12091 u8 min_buff[0x18]; 12092 12093 u8 infi_max[0x1]; 12094 u8 reserved_at_e1[0x7]; 12095 u8 max_buff[0x18]; 12096 12097 u8 reserved_at_100[0x20]; 12098 12099 u8 reserved_at_120[0x1c]; 12100 u8 pool[0x4]; 12101 }; 12102 12103 struct mlx5_ifc_qtct_reg_bits { 12104 u8 reserved_at_0[0x8]; 12105 u8 port_number[0x8]; 12106 u8 reserved_at_10[0xd]; 12107 u8 prio[0x3]; 12108 12109 u8 reserved_at_20[0x1d]; 12110 u8 tclass[0x3]; 12111 }; 12112 12113 struct mlx5_ifc_mcia_reg_bits { 12114 u8 l[0x1]; 12115 u8 reserved_at_1[0x7]; 12116 u8 module[0x8]; 12117 u8 reserved_at_10[0x8]; 12118 u8 status[0x8]; 12119 12120 u8 i2c_device_address[0x8]; 12121 u8 page_number[0x8]; 12122 u8 device_address[0x10]; 12123 12124 u8 reserved_at_40[0x10]; 12125 u8 size[0x10]; 12126 12127 u8 reserved_at_60[0x20]; 12128 12129 u8 dword_0[0x20]; 12130 u8 dword_1[0x20]; 12131 u8 dword_2[0x20]; 12132 u8 dword_3[0x20]; 12133 u8 dword_4[0x20]; 12134 u8 dword_5[0x20]; 12135 u8 dword_6[0x20]; 12136 u8 dword_7[0x20]; 12137 u8 dword_8[0x20]; 12138 u8 dword_9[0x20]; 12139 u8 dword_10[0x20]; 12140 u8 dword_11[0x20]; 12141 }; 12142 12143 struct mlx5_ifc_dcbx_param_bits { 12144 u8 dcbx_cee_cap[0x1]; 12145 u8 dcbx_ieee_cap[0x1]; 12146 u8 dcbx_standby_cap[0x1]; 12147 u8 reserved_at_3[0x5]; 12148 u8 port_number[0x8]; 12149 u8 reserved_at_10[0xa]; 12150 u8 max_application_table_size[6]; 12151 u8 reserved_at_20[0x15]; 12152 u8 version_oper[0x3]; 12153 u8 reserved_at_38[5]; 12154 u8 version_admin[0x3]; 12155 u8 willing_admin[0x1]; 12156 u8 reserved_at_41[0x3]; 12157 u8 pfc_cap_oper[0x4]; 12158 u8 reserved_at_48[0x4]; 12159 u8 pfc_cap_admin[0x4]; 12160 u8 reserved_at_50[0x4]; 12161 u8 num_of_tc_oper[0x4]; 12162 u8 reserved_at_58[0x4]; 12163 u8 num_of_tc_admin[0x4]; 12164 u8 remote_willing[0x1]; 12165 u8 reserved_at_61[3]; 12166 u8 remote_pfc_cap[4]; 12167 u8 reserved_at_68[0x14]; 12168 u8 remote_num_of_tc[0x4]; 12169 u8 reserved_at_80[0x18]; 12170 u8 error[0x8]; 12171 u8 reserved_at_a0[0x160]; 12172 }; 12173 12174 enum { 12175 MLX5_LAG_PORT_SELECT_MODE_QUEUE_AFFINITY = 0, 12176 MLX5_LAG_PORT_SELECT_MODE_PORT_SELECT_FT = 1, 12177 MLX5_LAG_PORT_SELECT_MODE_PORT_SELECT_MPESW = 2, 12178 }; 12179 12180 struct mlx5_ifc_lagc_bits { 12181 u8 fdb_selection_mode[0x1]; 12182 u8 reserved_at_1[0x14]; 12183 u8 port_select_mode[0x3]; 12184 u8 reserved_at_18[0x5]; 12185 u8 lag_state[0x3]; 12186 12187 u8 reserved_at_20[0xc]; 12188 u8 active_port[0x4]; 12189 u8 reserved_at_30[0x4]; 12190 u8 tx_remap_affinity_2[0x4]; 12191 u8 reserved_at_38[0x4]; 12192 u8 tx_remap_affinity_1[0x4]; 12193 }; 12194 12195 struct mlx5_ifc_create_lag_out_bits { 12196 u8 status[0x8]; 12197 u8 reserved_at_8[0x18]; 12198 12199 u8 syndrome[0x20]; 12200 12201 u8 reserved_at_40[0x40]; 12202 }; 12203 12204 struct mlx5_ifc_create_lag_in_bits { 12205 u8 opcode[0x10]; 12206 u8 reserved_at_10[0x10]; 12207 12208 u8 reserved_at_20[0x10]; 12209 u8 op_mod[0x10]; 12210 12211 struct mlx5_ifc_lagc_bits ctx; 12212 }; 12213 12214 struct mlx5_ifc_modify_lag_out_bits { 12215 u8 status[0x8]; 12216 u8 reserved_at_8[0x18]; 12217 12218 u8 syndrome[0x20]; 12219 12220 u8 reserved_at_40[0x40]; 12221 }; 12222 12223 struct mlx5_ifc_modify_lag_in_bits { 12224 u8 opcode[0x10]; 12225 u8 reserved_at_10[0x10]; 12226 12227 u8 reserved_at_20[0x10]; 12228 u8 op_mod[0x10]; 12229 12230 u8 reserved_at_40[0x20]; 12231 u8 field_select[0x20]; 12232 12233 struct mlx5_ifc_lagc_bits ctx; 12234 }; 12235 12236 struct mlx5_ifc_query_lag_out_bits { 12237 u8 status[0x8]; 12238 u8 reserved_at_8[0x18]; 12239 12240 u8 syndrome[0x20]; 12241 12242 struct mlx5_ifc_lagc_bits ctx; 12243 }; 12244 12245 struct mlx5_ifc_query_lag_in_bits { 12246 u8 opcode[0x10]; 12247 u8 reserved_at_10[0x10]; 12248 12249 u8 reserved_at_20[0x10]; 12250 u8 op_mod[0x10]; 12251 12252 u8 reserved_at_40[0x40]; 12253 }; 12254 12255 struct mlx5_ifc_destroy_lag_out_bits { 12256 u8 status[0x8]; 12257 u8 reserved_at_8[0x18]; 12258 12259 u8 syndrome[0x20]; 12260 12261 u8 reserved_at_40[0x40]; 12262 }; 12263 12264 struct mlx5_ifc_destroy_lag_in_bits { 12265 u8 opcode[0x10]; 12266 u8 reserved_at_10[0x10]; 12267 12268 u8 reserved_at_20[0x10]; 12269 u8 op_mod[0x10]; 12270 12271 u8 reserved_at_40[0x40]; 12272 }; 12273 12274 struct mlx5_ifc_create_vport_lag_out_bits { 12275 u8 status[0x8]; 12276 u8 reserved_at_8[0x18]; 12277 12278 u8 syndrome[0x20]; 12279 12280 u8 reserved_at_40[0x40]; 12281 }; 12282 12283 struct mlx5_ifc_create_vport_lag_in_bits { 12284 u8 opcode[0x10]; 12285 u8 reserved_at_10[0x10]; 12286 12287 u8 reserved_at_20[0x10]; 12288 u8 op_mod[0x10]; 12289 12290 u8 reserved_at_40[0x40]; 12291 }; 12292 12293 struct mlx5_ifc_destroy_vport_lag_out_bits { 12294 u8 status[0x8]; 12295 u8 reserved_at_8[0x18]; 12296 12297 u8 syndrome[0x20]; 12298 12299 u8 reserved_at_40[0x40]; 12300 }; 12301 12302 struct mlx5_ifc_destroy_vport_lag_in_bits { 12303 u8 opcode[0x10]; 12304 u8 reserved_at_10[0x10]; 12305 12306 u8 reserved_at_20[0x10]; 12307 u8 op_mod[0x10]; 12308 12309 u8 reserved_at_40[0x40]; 12310 }; 12311 12312 enum { 12313 MLX5_MODIFY_MEMIC_OP_MOD_ALLOC, 12314 MLX5_MODIFY_MEMIC_OP_MOD_DEALLOC, 12315 }; 12316 12317 struct mlx5_ifc_modify_memic_in_bits { 12318 u8 opcode[0x10]; 12319 u8 uid[0x10]; 12320 12321 u8 reserved_at_20[0x10]; 12322 u8 op_mod[0x10]; 12323 12324 u8 reserved_at_40[0x20]; 12325 12326 u8 reserved_at_60[0x18]; 12327 u8 memic_operation_type[0x8]; 12328 12329 u8 memic_start_addr[0x40]; 12330 12331 u8 reserved_at_c0[0x140]; 12332 }; 12333 12334 struct mlx5_ifc_modify_memic_out_bits { 12335 u8 status[0x8]; 12336 u8 reserved_at_8[0x18]; 12337 12338 u8 syndrome[0x20]; 12339 12340 u8 reserved_at_40[0x40]; 12341 12342 u8 memic_operation_addr[0x40]; 12343 12344 u8 reserved_at_c0[0x140]; 12345 }; 12346 12347 struct mlx5_ifc_alloc_memic_in_bits { 12348 u8 opcode[0x10]; 12349 u8 reserved_at_10[0x10]; 12350 12351 u8 reserved_at_20[0x10]; 12352 u8 op_mod[0x10]; 12353 12354 u8 reserved_at_30[0x20]; 12355 12356 u8 reserved_at_40[0x18]; 12357 u8 log_memic_addr_alignment[0x8]; 12358 12359 u8 range_start_addr[0x40]; 12360 12361 u8 range_size[0x20]; 12362 12363 u8 memic_size[0x20]; 12364 }; 12365 12366 struct mlx5_ifc_alloc_memic_out_bits { 12367 u8 status[0x8]; 12368 u8 reserved_at_8[0x18]; 12369 12370 u8 syndrome[0x20]; 12371 12372 u8 memic_start_addr[0x40]; 12373 }; 12374 12375 struct mlx5_ifc_dealloc_memic_in_bits { 12376 u8 opcode[0x10]; 12377 u8 reserved_at_10[0x10]; 12378 12379 u8 reserved_at_20[0x10]; 12380 u8 op_mod[0x10]; 12381 12382 u8 reserved_at_40[0x40]; 12383 12384 u8 memic_start_addr[0x40]; 12385 12386 u8 memic_size[0x20]; 12387 12388 u8 reserved_at_e0[0x20]; 12389 }; 12390 12391 struct mlx5_ifc_dealloc_memic_out_bits { 12392 u8 status[0x8]; 12393 u8 reserved_at_8[0x18]; 12394 12395 u8 syndrome[0x20]; 12396 12397 u8 reserved_at_40[0x40]; 12398 }; 12399 12400 struct mlx5_ifc_umem_bits { 12401 u8 reserved_at_0[0x80]; 12402 12403 u8 ats[0x1]; 12404 u8 reserved_at_81[0x1a]; 12405 u8 log_page_size[0x5]; 12406 12407 u8 page_offset[0x20]; 12408 12409 u8 num_of_mtt[0x40]; 12410 12411 struct mlx5_ifc_mtt_bits mtt[]; 12412 }; 12413 12414 struct mlx5_ifc_uctx_bits { 12415 u8 cap[0x20]; 12416 12417 u8 reserved_at_20[0x160]; 12418 }; 12419 12420 struct mlx5_ifc_sw_icm_bits { 12421 u8 modify_field_select[0x40]; 12422 12423 u8 reserved_at_40[0x18]; 12424 u8 log_sw_icm_size[0x8]; 12425 12426 u8 reserved_at_60[0x20]; 12427 12428 u8 sw_icm_start_addr[0x40]; 12429 12430 u8 reserved_at_c0[0x140]; 12431 }; 12432 12433 struct mlx5_ifc_geneve_tlv_option_bits { 12434 u8 modify_field_select[0x40]; 12435 12436 u8 reserved_at_40[0x18]; 12437 u8 geneve_option_fte_index[0x8]; 12438 12439 u8 option_class[0x10]; 12440 u8 option_type[0x8]; 12441 u8 reserved_at_78[0x3]; 12442 u8 option_data_length[0x5]; 12443 12444 u8 reserved_at_80[0x180]; 12445 }; 12446 12447 struct mlx5_ifc_create_umem_in_bits { 12448 u8 opcode[0x10]; 12449 u8 uid[0x10]; 12450 12451 u8 reserved_at_20[0x10]; 12452 u8 op_mod[0x10]; 12453 12454 u8 reserved_at_40[0x40]; 12455 12456 struct mlx5_ifc_umem_bits umem; 12457 }; 12458 12459 struct mlx5_ifc_create_umem_out_bits { 12460 u8 status[0x8]; 12461 u8 reserved_at_8[0x18]; 12462 12463 u8 syndrome[0x20]; 12464 12465 u8 reserved_at_40[0x8]; 12466 u8 umem_id[0x18]; 12467 12468 u8 reserved_at_60[0x20]; 12469 }; 12470 12471 struct mlx5_ifc_destroy_umem_in_bits { 12472 u8 opcode[0x10]; 12473 u8 uid[0x10]; 12474 12475 u8 reserved_at_20[0x10]; 12476 u8 op_mod[0x10]; 12477 12478 u8 reserved_at_40[0x8]; 12479 u8 umem_id[0x18]; 12480 12481 u8 reserved_at_60[0x20]; 12482 }; 12483 12484 struct mlx5_ifc_destroy_umem_out_bits { 12485 u8 status[0x8]; 12486 u8 reserved_at_8[0x18]; 12487 12488 u8 syndrome[0x20]; 12489 12490 u8 reserved_at_40[0x40]; 12491 }; 12492 12493 struct mlx5_ifc_create_uctx_in_bits { 12494 u8 opcode[0x10]; 12495 u8 reserved_at_10[0x10]; 12496 12497 u8 reserved_at_20[0x10]; 12498 u8 op_mod[0x10]; 12499 12500 u8 reserved_at_40[0x40]; 12501 12502 struct mlx5_ifc_uctx_bits uctx; 12503 }; 12504 12505 struct mlx5_ifc_create_uctx_out_bits { 12506 u8 status[0x8]; 12507 u8 reserved_at_8[0x18]; 12508 12509 u8 syndrome[0x20]; 12510 12511 u8 reserved_at_40[0x10]; 12512 u8 uid[0x10]; 12513 12514 u8 reserved_at_60[0x20]; 12515 }; 12516 12517 struct mlx5_ifc_destroy_uctx_in_bits { 12518 u8 opcode[0x10]; 12519 u8 reserved_at_10[0x10]; 12520 12521 u8 reserved_at_20[0x10]; 12522 u8 op_mod[0x10]; 12523 12524 u8 reserved_at_40[0x10]; 12525 u8 uid[0x10]; 12526 12527 u8 reserved_at_60[0x20]; 12528 }; 12529 12530 struct mlx5_ifc_destroy_uctx_out_bits { 12531 u8 status[0x8]; 12532 u8 reserved_at_8[0x18]; 12533 12534 u8 syndrome[0x20]; 12535 12536 u8 reserved_at_40[0x40]; 12537 }; 12538 12539 struct mlx5_ifc_create_sw_icm_in_bits { 12540 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 12541 struct mlx5_ifc_sw_icm_bits sw_icm; 12542 }; 12543 12544 struct mlx5_ifc_create_geneve_tlv_option_in_bits { 12545 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 12546 struct mlx5_ifc_geneve_tlv_option_bits geneve_tlv_opt; 12547 }; 12548 12549 struct mlx5_ifc_mtrc_string_db_param_bits { 12550 u8 string_db_base_address[0x20]; 12551 12552 u8 reserved_at_20[0x8]; 12553 u8 string_db_size[0x18]; 12554 }; 12555 12556 struct mlx5_ifc_mtrc_cap_bits { 12557 u8 trace_owner[0x1]; 12558 u8 trace_to_memory[0x1]; 12559 u8 reserved_at_2[0x4]; 12560 u8 trc_ver[0x2]; 12561 u8 reserved_at_8[0x14]; 12562 u8 num_string_db[0x4]; 12563 12564 u8 first_string_trace[0x8]; 12565 u8 num_string_trace[0x8]; 12566 u8 reserved_at_30[0x28]; 12567 12568 u8 log_max_trace_buffer_size[0x8]; 12569 12570 u8 reserved_at_60[0x20]; 12571 12572 struct mlx5_ifc_mtrc_string_db_param_bits string_db_param[8]; 12573 12574 u8 reserved_at_280[0x180]; 12575 }; 12576 12577 struct mlx5_ifc_mtrc_conf_bits { 12578 u8 reserved_at_0[0x1c]; 12579 u8 trace_mode[0x4]; 12580 u8 reserved_at_20[0x18]; 12581 u8 log_trace_buffer_size[0x8]; 12582 u8 trace_mkey[0x20]; 12583 u8 reserved_at_60[0x3a0]; 12584 }; 12585 12586 struct mlx5_ifc_mtrc_stdb_bits { 12587 u8 string_db_index[0x4]; 12588 u8 reserved_at_4[0x4]; 12589 u8 read_size[0x18]; 12590 u8 start_offset[0x20]; 12591 u8 string_db_data[]; 12592 }; 12593 12594 struct mlx5_ifc_mtrc_ctrl_bits { 12595 u8 trace_status[0x2]; 12596 u8 reserved_at_2[0x2]; 12597 u8 arm_event[0x1]; 12598 u8 reserved_at_5[0xb]; 12599 u8 modify_field_select[0x10]; 12600 u8 reserved_at_20[0x2b]; 12601 u8 current_timestamp52_32[0x15]; 12602 u8 current_timestamp31_0[0x20]; 12603 u8 reserved_at_80[0x180]; 12604 }; 12605 12606 struct mlx5_ifc_host_params_context_bits { 12607 u8 host_number[0x8]; 12608 u8 reserved_at_8[0x5]; 12609 u8 host_pf_not_exist[0x1]; 12610 u8 reserved_at_14[0x1]; 12611 u8 host_pf_disabled[0x1]; 12612 u8 host_num_of_vfs[0x10]; 12613 12614 u8 host_total_vfs[0x10]; 12615 u8 host_pci_bus[0x10]; 12616 12617 u8 reserved_at_40[0x10]; 12618 u8 host_pci_device[0x10]; 12619 12620 u8 reserved_at_60[0x10]; 12621 u8 host_pci_function[0x10]; 12622 12623 u8 reserved_at_80[0x180]; 12624 }; 12625 12626 struct mlx5_ifc_query_esw_functions_in_bits { 12627 u8 opcode[0x10]; 12628 u8 reserved_at_10[0x10]; 12629 12630 u8 reserved_at_20[0x10]; 12631 u8 op_mod[0x10]; 12632 12633 u8 reserved_at_40[0x40]; 12634 }; 12635 12636 struct mlx5_ifc_query_esw_functions_out_bits { 12637 u8 status[0x8]; 12638 u8 reserved_at_8[0x18]; 12639 12640 u8 syndrome[0x20]; 12641 12642 u8 reserved_at_40[0x40]; 12643 12644 struct mlx5_ifc_host_params_context_bits host_params_context; 12645 12646 u8 reserved_at_280[0x180]; 12647 u8 host_sf_enable[][0x40]; 12648 }; 12649 12650 struct mlx5_ifc_sf_partition_bits { 12651 u8 reserved_at_0[0x10]; 12652 u8 log_num_sf[0x8]; 12653 u8 log_sf_bar_size[0x8]; 12654 }; 12655 12656 struct mlx5_ifc_query_sf_partitions_out_bits { 12657 u8 status[0x8]; 12658 u8 reserved_at_8[0x18]; 12659 12660 u8 syndrome[0x20]; 12661 12662 u8 reserved_at_40[0x18]; 12663 u8 num_sf_partitions[0x8]; 12664 12665 u8 reserved_at_60[0x20]; 12666 12667 struct mlx5_ifc_sf_partition_bits sf_partition[]; 12668 }; 12669 12670 struct mlx5_ifc_query_sf_partitions_in_bits { 12671 u8 opcode[0x10]; 12672 u8 reserved_at_10[0x10]; 12673 12674 u8 reserved_at_20[0x10]; 12675 u8 op_mod[0x10]; 12676 12677 u8 reserved_at_40[0x40]; 12678 }; 12679 12680 struct mlx5_ifc_dealloc_sf_out_bits { 12681 u8 status[0x8]; 12682 u8 reserved_at_8[0x18]; 12683 12684 u8 syndrome[0x20]; 12685 12686 u8 reserved_at_40[0x40]; 12687 }; 12688 12689 struct mlx5_ifc_dealloc_sf_in_bits { 12690 u8 opcode[0x10]; 12691 u8 reserved_at_10[0x10]; 12692 12693 u8 reserved_at_20[0x10]; 12694 u8 op_mod[0x10]; 12695 12696 u8 reserved_at_40[0x10]; 12697 u8 function_id[0x10]; 12698 12699 u8 reserved_at_60[0x20]; 12700 }; 12701 12702 struct mlx5_ifc_alloc_sf_out_bits { 12703 u8 status[0x8]; 12704 u8 reserved_at_8[0x18]; 12705 12706 u8 syndrome[0x20]; 12707 12708 u8 reserved_at_40[0x40]; 12709 }; 12710 12711 struct mlx5_ifc_alloc_sf_in_bits { 12712 u8 opcode[0x10]; 12713 u8 reserved_at_10[0x10]; 12714 12715 u8 reserved_at_20[0x10]; 12716 u8 op_mod[0x10]; 12717 12718 u8 reserved_at_40[0x10]; 12719 u8 function_id[0x10]; 12720 12721 u8 reserved_at_60[0x20]; 12722 }; 12723 12724 struct mlx5_ifc_affiliated_event_header_bits { 12725 u8 reserved_at_0[0x10]; 12726 u8 obj_type[0x10]; 12727 12728 u8 obj_id[0x20]; 12729 }; 12730 12731 enum { 12732 MLX5_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = 0xc, 12733 MLX5_GENERAL_OBJECT_TYPES_IPSEC = 0x13, 12734 MLX5_GENERAL_OBJECT_TYPES_SAMPLER = 0x20, 12735 MLX5_GENERAL_OBJECT_TYPES_FLOW_METER_ASO = 0x24, 12736 MLX5_GENERAL_OBJECT_TYPES_MACSEC = 0x27, 12737 MLX5_GENERAL_OBJECT_TYPES_INT_KEK = 0x47, 12738 MLX5_GENERAL_OBJECT_TYPES_RDMA_CTRL = 0x53, 12739 MLX5_GENERAL_OBJECT_TYPES_PCIE_CONG_EVENT = 0x58, 12740 MLX5_GENERAL_OBJECT_TYPES_FLOW_TABLE_ALIAS = 0xff15, 12741 }; 12742 12743 enum { 12744 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = 12745 BIT_ULL(MLX5_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY), 12746 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_IPSEC = 12747 BIT_ULL(MLX5_GENERAL_OBJECT_TYPES_IPSEC), 12748 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_SAMPLER = 12749 BIT_ULL(MLX5_GENERAL_OBJECT_TYPES_SAMPLER), 12750 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_FLOW_METER_ASO = 12751 BIT_ULL(MLX5_GENERAL_OBJECT_TYPES_FLOW_METER_ASO), 12752 }; 12753 12754 enum { 12755 MLX5_HCA_CAP_2_GENERAL_OBJECT_TYPES_RDMA_CTRL = 12756 BIT_ULL(MLX5_GENERAL_OBJECT_TYPES_RDMA_CTRL - 0x40), 12757 MLX5_HCA_CAP_2_GENERAL_OBJECT_TYPES_PCIE_CONG_EVENT = 12758 BIT_ULL(MLX5_GENERAL_OBJECT_TYPES_PCIE_CONG_EVENT - 0x40), 12759 }; 12760 12761 enum { 12762 MLX5_IPSEC_OBJECT_ICV_LEN_16B, 12763 }; 12764 12765 enum { 12766 MLX5_IPSEC_ASO_REG_C_0_1 = 0x0, 12767 MLX5_IPSEC_ASO_REG_C_2_3 = 0x1, 12768 MLX5_IPSEC_ASO_REG_C_4_5 = 0x2, 12769 MLX5_IPSEC_ASO_REG_C_6_7 = 0x3, 12770 }; 12771 12772 enum { 12773 MLX5_IPSEC_ASO_MODE = 0x0, 12774 MLX5_IPSEC_ASO_REPLAY_PROTECTION = 0x1, 12775 MLX5_IPSEC_ASO_INC_SN = 0x2, 12776 }; 12777 12778 enum { 12779 MLX5_IPSEC_ASO_REPLAY_WIN_32BIT = 0x0, 12780 MLX5_IPSEC_ASO_REPLAY_WIN_64BIT = 0x1, 12781 MLX5_IPSEC_ASO_REPLAY_WIN_128BIT = 0x2, 12782 MLX5_IPSEC_ASO_REPLAY_WIN_256BIT = 0x3, 12783 }; 12784 12785 struct mlx5_ifc_ipsec_aso_bits { 12786 u8 valid[0x1]; 12787 u8 reserved_at_201[0x1]; 12788 u8 mode[0x2]; 12789 u8 window_sz[0x2]; 12790 u8 soft_lft_arm[0x1]; 12791 u8 hard_lft_arm[0x1]; 12792 u8 remove_flow_enable[0x1]; 12793 u8 esn_event_arm[0x1]; 12794 u8 reserved_at_20a[0x16]; 12795 12796 u8 remove_flow_pkt_cnt[0x20]; 12797 12798 u8 remove_flow_soft_lft[0x20]; 12799 12800 u8 reserved_at_260[0x80]; 12801 12802 u8 mode_parameter[0x20]; 12803 12804 u8 replay_protection_window[0x100]; 12805 }; 12806 12807 struct mlx5_ifc_ipsec_obj_bits { 12808 u8 modify_field_select[0x40]; 12809 u8 full_offload[0x1]; 12810 u8 reserved_at_41[0x1]; 12811 u8 esn_en[0x1]; 12812 u8 esn_overlap[0x1]; 12813 u8 reserved_at_44[0x2]; 12814 u8 icv_length[0x2]; 12815 u8 reserved_at_48[0x4]; 12816 u8 aso_return_reg[0x4]; 12817 u8 reserved_at_50[0x10]; 12818 12819 u8 esn_msb[0x20]; 12820 12821 u8 reserved_at_80[0x8]; 12822 u8 dekn[0x18]; 12823 12824 u8 salt[0x20]; 12825 12826 u8 implicit_iv[0x40]; 12827 12828 u8 reserved_at_100[0x8]; 12829 u8 ipsec_aso_access_pd[0x18]; 12830 u8 reserved_at_120[0xe0]; 12831 12832 struct mlx5_ifc_ipsec_aso_bits ipsec_aso; 12833 }; 12834 12835 struct mlx5_ifc_create_ipsec_obj_in_bits { 12836 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12837 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 12838 }; 12839 12840 enum { 12841 MLX5_MODIFY_IPSEC_BITMASK_ESN_OVERLAP = BIT(0), 12842 MLX5_MODIFY_IPSEC_BITMASK_ESN_MSB = BIT(1), 12843 }; 12844 12845 struct mlx5_ifc_query_ipsec_obj_out_bits { 12846 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 12847 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 12848 }; 12849 12850 struct mlx5_ifc_modify_ipsec_obj_in_bits { 12851 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12852 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 12853 }; 12854 12855 enum { 12856 MLX5_MACSEC_ASO_REPLAY_PROTECTION = 0x1, 12857 }; 12858 12859 enum { 12860 MLX5_MACSEC_ASO_REPLAY_WIN_32BIT = 0x0, 12861 MLX5_MACSEC_ASO_REPLAY_WIN_64BIT = 0x1, 12862 MLX5_MACSEC_ASO_REPLAY_WIN_128BIT = 0x2, 12863 MLX5_MACSEC_ASO_REPLAY_WIN_256BIT = 0x3, 12864 }; 12865 12866 #define MLX5_MACSEC_ASO_INC_SN 0x2 12867 #define MLX5_MACSEC_ASO_REG_C_4_5 0x2 12868 12869 struct mlx5_ifc_macsec_aso_bits { 12870 u8 valid[0x1]; 12871 u8 reserved_at_1[0x1]; 12872 u8 mode[0x2]; 12873 u8 window_size[0x2]; 12874 u8 soft_lifetime_arm[0x1]; 12875 u8 hard_lifetime_arm[0x1]; 12876 u8 remove_flow_enable[0x1]; 12877 u8 epn_event_arm[0x1]; 12878 u8 reserved_at_a[0x16]; 12879 12880 u8 remove_flow_packet_count[0x20]; 12881 12882 u8 remove_flow_soft_lifetime[0x20]; 12883 12884 u8 reserved_at_60[0x80]; 12885 12886 u8 mode_parameter[0x20]; 12887 12888 u8 replay_protection_window[8][0x20]; 12889 }; 12890 12891 struct mlx5_ifc_macsec_offload_obj_bits { 12892 u8 modify_field_select[0x40]; 12893 12894 u8 confidentiality_en[0x1]; 12895 u8 reserved_at_41[0x1]; 12896 u8 epn_en[0x1]; 12897 u8 epn_overlap[0x1]; 12898 u8 reserved_at_44[0x2]; 12899 u8 confidentiality_offset[0x2]; 12900 u8 reserved_at_48[0x4]; 12901 u8 aso_return_reg[0x4]; 12902 u8 reserved_at_50[0x10]; 12903 12904 u8 epn_msb[0x20]; 12905 12906 u8 reserved_at_80[0x8]; 12907 u8 dekn[0x18]; 12908 12909 u8 reserved_at_a0[0x20]; 12910 12911 u8 sci[0x40]; 12912 12913 u8 reserved_at_100[0x8]; 12914 u8 macsec_aso_access_pd[0x18]; 12915 12916 u8 reserved_at_120[0x60]; 12917 12918 u8 salt[3][0x20]; 12919 12920 u8 reserved_at_1e0[0x20]; 12921 12922 struct mlx5_ifc_macsec_aso_bits macsec_aso; 12923 }; 12924 12925 struct mlx5_ifc_create_macsec_obj_in_bits { 12926 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12927 struct mlx5_ifc_macsec_offload_obj_bits macsec_object; 12928 }; 12929 12930 struct mlx5_ifc_modify_macsec_obj_in_bits { 12931 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12932 struct mlx5_ifc_macsec_offload_obj_bits macsec_object; 12933 }; 12934 12935 enum { 12936 MLX5_MODIFY_MACSEC_BITMASK_EPN_OVERLAP = BIT(0), 12937 MLX5_MODIFY_MACSEC_BITMASK_EPN_MSB = BIT(1), 12938 }; 12939 12940 struct mlx5_ifc_query_macsec_obj_out_bits { 12941 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 12942 struct mlx5_ifc_macsec_offload_obj_bits macsec_object; 12943 }; 12944 12945 struct mlx5_ifc_wrapped_dek_bits { 12946 u8 gcm_iv[0x60]; 12947 12948 u8 reserved_at_60[0x20]; 12949 12950 u8 const0[0x1]; 12951 u8 key_size[0x1]; 12952 u8 reserved_at_82[0x2]; 12953 u8 key2_invalid[0x1]; 12954 u8 reserved_at_85[0x3]; 12955 u8 pd[0x18]; 12956 12957 u8 key_purpose[0x5]; 12958 u8 reserved_at_a5[0x13]; 12959 u8 kek_id[0x8]; 12960 12961 u8 reserved_at_c0[0x40]; 12962 12963 u8 key1[0x8][0x20]; 12964 12965 u8 key2[0x8][0x20]; 12966 12967 u8 reserved_at_300[0x40]; 12968 12969 u8 const1[0x1]; 12970 u8 reserved_at_341[0x1f]; 12971 12972 u8 reserved_at_360[0x20]; 12973 12974 u8 auth_tag[0x80]; 12975 }; 12976 12977 struct mlx5_ifc_encryption_key_obj_bits { 12978 u8 modify_field_select[0x40]; 12979 12980 u8 state[0x8]; 12981 u8 sw_wrapped[0x1]; 12982 u8 reserved_at_49[0xb]; 12983 u8 key_size[0x4]; 12984 u8 reserved_at_58[0x4]; 12985 u8 key_purpose[0x4]; 12986 12987 u8 reserved_at_60[0x8]; 12988 u8 pd[0x18]; 12989 12990 u8 reserved_at_80[0x100]; 12991 12992 u8 opaque[0x40]; 12993 12994 u8 reserved_at_1c0[0x40]; 12995 12996 u8 key[8][0x80]; 12997 12998 u8 sw_wrapped_dek[8][0x80]; 12999 13000 u8 reserved_at_a00[0x600]; 13001 }; 13002 13003 struct mlx5_ifc_create_encryption_key_in_bits { 13004 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 13005 struct mlx5_ifc_encryption_key_obj_bits encryption_key_object; 13006 }; 13007 13008 struct mlx5_ifc_modify_encryption_key_in_bits { 13009 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 13010 struct mlx5_ifc_encryption_key_obj_bits encryption_key_object; 13011 }; 13012 13013 enum { 13014 MLX5_FLOW_METER_MODE_BYTES_IP_LENGTH = 0x0, 13015 MLX5_FLOW_METER_MODE_BYTES_CALC_WITH_L2 = 0x1, 13016 MLX5_FLOW_METER_MODE_BYTES_CALC_WITH_L2_IPG = 0x2, 13017 MLX5_FLOW_METER_MODE_NUM_PACKETS = 0x3, 13018 }; 13019 13020 struct mlx5_ifc_flow_meter_parameters_bits { 13021 u8 valid[0x1]; 13022 u8 bucket_overflow[0x1]; 13023 u8 start_color[0x2]; 13024 u8 both_buckets_on_green[0x1]; 13025 u8 reserved_at_5[0x1]; 13026 u8 meter_mode[0x2]; 13027 u8 reserved_at_8[0x18]; 13028 13029 u8 reserved_at_20[0x20]; 13030 13031 u8 reserved_at_40[0x3]; 13032 u8 cbs_exponent[0x5]; 13033 u8 cbs_mantissa[0x8]; 13034 u8 reserved_at_50[0x3]; 13035 u8 cir_exponent[0x5]; 13036 u8 cir_mantissa[0x8]; 13037 13038 u8 reserved_at_60[0x20]; 13039 13040 u8 reserved_at_80[0x3]; 13041 u8 ebs_exponent[0x5]; 13042 u8 ebs_mantissa[0x8]; 13043 u8 reserved_at_90[0x3]; 13044 u8 eir_exponent[0x5]; 13045 u8 eir_mantissa[0x8]; 13046 13047 u8 reserved_at_a0[0x60]; 13048 }; 13049 13050 struct mlx5_ifc_flow_meter_aso_obj_bits { 13051 u8 modify_field_select[0x40]; 13052 13053 u8 reserved_at_40[0x40]; 13054 13055 u8 reserved_at_80[0x8]; 13056 u8 meter_aso_access_pd[0x18]; 13057 13058 u8 reserved_at_a0[0x160]; 13059 13060 struct mlx5_ifc_flow_meter_parameters_bits flow_meter_parameters[2]; 13061 }; 13062 13063 struct mlx5_ifc_create_flow_meter_aso_obj_in_bits { 13064 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 13065 struct mlx5_ifc_flow_meter_aso_obj_bits flow_meter_aso_obj; 13066 }; 13067 13068 struct mlx5_ifc_int_kek_obj_bits { 13069 u8 modify_field_select[0x40]; 13070 13071 u8 state[0x8]; 13072 u8 auto_gen[0x1]; 13073 u8 reserved_at_49[0xb]; 13074 u8 key_size[0x4]; 13075 u8 reserved_at_58[0x8]; 13076 13077 u8 reserved_at_60[0x8]; 13078 u8 pd[0x18]; 13079 13080 u8 reserved_at_80[0x180]; 13081 u8 key[8][0x80]; 13082 13083 u8 reserved_at_600[0x200]; 13084 }; 13085 13086 struct mlx5_ifc_create_int_kek_obj_in_bits { 13087 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 13088 struct mlx5_ifc_int_kek_obj_bits int_kek_object; 13089 }; 13090 13091 struct mlx5_ifc_create_int_kek_obj_out_bits { 13092 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 13093 struct mlx5_ifc_int_kek_obj_bits int_kek_object; 13094 }; 13095 13096 struct mlx5_ifc_sampler_obj_bits { 13097 u8 modify_field_select[0x40]; 13098 13099 u8 table_type[0x8]; 13100 u8 level[0x8]; 13101 u8 reserved_at_50[0xf]; 13102 u8 ignore_flow_level[0x1]; 13103 13104 u8 sample_ratio[0x20]; 13105 13106 u8 reserved_at_80[0x8]; 13107 u8 sample_table_id[0x18]; 13108 13109 u8 reserved_at_a0[0x8]; 13110 u8 default_table_id[0x18]; 13111 13112 u8 sw_steering_icm_address_rx[0x40]; 13113 u8 sw_steering_icm_address_tx[0x40]; 13114 13115 u8 reserved_at_140[0xa0]; 13116 }; 13117 13118 struct mlx5_ifc_create_sampler_obj_in_bits { 13119 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 13120 struct mlx5_ifc_sampler_obj_bits sampler_object; 13121 }; 13122 13123 struct mlx5_ifc_query_sampler_obj_out_bits { 13124 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 13125 struct mlx5_ifc_sampler_obj_bits sampler_object; 13126 }; 13127 13128 enum { 13129 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_128 = 0x0, 13130 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_256 = 0x1, 13131 }; 13132 13133 enum { 13134 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_PURPOSE_TLS = 0x1, 13135 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_PURPOSE_IPSEC = 0x2, 13136 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_PURPOSE_MACSEC = 0x4, 13137 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_PURPOSE_PSP = 0x6, 13138 }; 13139 13140 struct mlx5_ifc_tls_static_params_bits { 13141 u8 const_2[0x2]; 13142 u8 tls_version[0x4]; 13143 u8 const_1[0x2]; 13144 u8 reserved_at_8[0x14]; 13145 u8 encryption_standard[0x4]; 13146 13147 u8 reserved_at_20[0x20]; 13148 13149 u8 initial_record_number[0x40]; 13150 13151 u8 resync_tcp_sn[0x20]; 13152 13153 u8 gcm_iv[0x20]; 13154 13155 u8 implicit_iv[0x40]; 13156 13157 u8 reserved_at_100[0x8]; 13158 u8 dek_index[0x18]; 13159 13160 u8 reserved_at_120[0xe0]; 13161 }; 13162 13163 struct mlx5_ifc_tls_progress_params_bits { 13164 u8 next_record_tcp_sn[0x20]; 13165 13166 u8 hw_resync_tcp_sn[0x20]; 13167 13168 u8 record_tracker_state[0x2]; 13169 u8 auth_state[0x2]; 13170 u8 reserved_at_44[0x4]; 13171 u8 hw_offset_record_number[0x18]; 13172 }; 13173 13174 enum { 13175 MLX5_MTT_PERM_READ = 1 << 0, 13176 MLX5_MTT_PERM_WRITE = 1 << 1, 13177 MLX5_MTT_PERM_RW = MLX5_MTT_PERM_READ | MLX5_MTT_PERM_WRITE, 13178 }; 13179 13180 enum { 13181 MLX5_SUSPEND_VHCA_IN_OP_MOD_SUSPEND_INITIATOR = 0x0, 13182 MLX5_SUSPEND_VHCA_IN_OP_MOD_SUSPEND_RESPONDER = 0x1, 13183 }; 13184 13185 struct mlx5_ifc_suspend_vhca_in_bits { 13186 u8 opcode[0x10]; 13187 u8 uid[0x10]; 13188 13189 u8 reserved_at_20[0x10]; 13190 u8 op_mod[0x10]; 13191 13192 u8 reserved_at_40[0x10]; 13193 u8 vhca_id[0x10]; 13194 13195 u8 reserved_at_60[0x20]; 13196 }; 13197 13198 struct mlx5_ifc_suspend_vhca_out_bits { 13199 u8 status[0x8]; 13200 u8 reserved_at_8[0x18]; 13201 13202 u8 syndrome[0x20]; 13203 13204 u8 reserved_at_40[0x40]; 13205 }; 13206 13207 enum { 13208 MLX5_RESUME_VHCA_IN_OP_MOD_RESUME_RESPONDER = 0x0, 13209 MLX5_RESUME_VHCA_IN_OP_MOD_RESUME_INITIATOR = 0x1, 13210 }; 13211 13212 struct mlx5_ifc_resume_vhca_in_bits { 13213 u8 opcode[0x10]; 13214 u8 uid[0x10]; 13215 13216 u8 reserved_at_20[0x10]; 13217 u8 op_mod[0x10]; 13218 13219 u8 reserved_at_40[0x10]; 13220 u8 vhca_id[0x10]; 13221 13222 u8 reserved_at_60[0x20]; 13223 }; 13224 13225 struct mlx5_ifc_resume_vhca_out_bits { 13226 u8 status[0x8]; 13227 u8 reserved_at_8[0x18]; 13228 13229 u8 syndrome[0x20]; 13230 13231 u8 reserved_at_40[0x40]; 13232 }; 13233 13234 struct mlx5_ifc_query_vhca_migration_state_in_bits { 13235 u8 opcode[0x10]; 13236 u8 uid[0x10]; 13237 13238 u8 reserved_at_20[0x10]; 13239 u8 op_mod[0x10]; 13240 13241 u8 incremental[0x1]; 13242 u8 chunk[0x1]; 13243 u8 reserved_at_42[0xe]; 13244 u8 vhca_id[0x10]; 13245 13246 u8 reserved_at_60[0x20]; 13247 }; 13248 13249 struct mlx5_ifc_query_vhca_migration_state_out_bits { 13250 u8 status[0x8]; 13251 u8 reserved_at_8[0x18]; 13252 13253 u8 syndrome[0x20]; 13254 13255 u8 reserved_at_40[0x40]; 13256 13257 u8 required_umem_size[0x20]; 13258 13259 u8 reserved_at_a0[0x20]; 13260 13261 u8 remaining_total_size[0x40]; 13262 13263 u8 reserved_at_100[0x100]; 13264 }; 13265 13266 struct mlx5_ifc_save_vhca_state_in_bits { 13267 u8 opcode[0x10]; 13268 u8 uid[0x10]; 13269 13270 u8 reserved_at_20[0x10]; 13271 u8 op_mod[0x10]; 13272 13273 u8 incremental[0x1]; 13274 u8 set_track[0x1]; 13275 u8 reserved_at_42[0xe]; 13276 u8 vhca_id[0x10]; 13277 13278 u8 reserved_at_60[0x20]; 13279 13280 u8 va[0x40]; 13281 13282 u8 mkey[0x20]; 13283 13284 u8 size[0x20]; 13285 }; 13286 13287 struct mlx5_ifc_save_vhca_state_out_bits { 13288 u8 status[0x8]; 13289 u8 reserved_at_8[0x18]; 13290 13291 u8 syndrome[0x20]; 13292 13293 u8 actual_image_size[0x20]; 13294 13295 u8 next_required_umem_size[0x20]; 13296 }; 13297 13298 struct mlx5_ifc_load_vhca_state_in_bits { 13299 u8 opcode[0x10]; 13300 u8 uid[0x10]; 13301 13302 u8 reserved_at_20[0x10]; 13303 u8 op_mod[0x10]; 13304 13305 u8 reserved_at_40[0x10]; 13306 u8 vhca_id[0x10]; 13307 13308 u8 reserved_at_60[0x20]; 13309 13310 u8 va[0x40]; 13311 13312 u8 mkey[0x20]; 13313 13314 u8 size[0x20]; 13315 }; 13316 13317 struct mlx5_ifc_load_vhca_state_out_bits { 13318 u8 status[0x8]; 13319 u8 reserved_at_8[0x18]; 13320 13321 u8 syndrome[0x20]; 13322 13323 u8 reserved_at_40[0x40]; 13324 }; 13325 13326 struct mlx5_ifc_adv_rdma_cap_bits { 13327 u8 rdma_transport_manager[0x1]; 13328 u8 rdma_transport_manager_other_eswitch[0x1]; 13329 u8 reserved_at_2[0x1e]; 13330 13331 u8 rcx_type[0x8]; 13332 u8 reserved_at_28[0x2]; 13333 u8 ps_entry_log_max_value[0x6]; 13334 u8 reserved_at_30[0x6]; 13335 u8 qp_max_ps_num_entry[0xa]; 13336 13337 u8 mp_max_num_queues[0x8]; 13338 u8 ps_user_context_max_log_size[0x8]; 13339 u8 message_based_qp_and_striding_wq[0x8]; 13340 u8 reserved_at_58[0x8]; 13341 13342 u8 max_receive_send_message_size_stride[0x10]; 13343 u8 reserved_at_70[0x10]; 13344 13345 u8 max_receive_send_message_size_byte[0x20]; 13346 13347 u8 reserved_at_a0[0x160]; 13348 13349 struct mlx5_ifc_flow_table_prop_layout_bits rdma_transport_rx_flow_table_properties; 13350 13351 struct mlx5_ifc_flow_table_prop_layout_bits rdma_transport_tx_flow_table_properties; 13352 13353 struct mlx5_ifc_flow_table_fields_supported_2_bits rdma_transport_rx_ft_field_support_2; 13354 13355 struct mlx5_ifc_flow_table_fields_supported_2_bits rdma_transport_tx_ft_field_support_2; 13356 13357 struct mlx5_ifc_flow_table_fields_supported_2_bits rdma_transport_rx_ft_field_bitmask_support_2; 13358 13359 struct mlx5_ifc_flow_table_fields_supported_2_bits rdma_transport_tx_ft_field_bitmask_support_2; 13360 13361 u8 reserved_at_800[0x3800]; 13362 }; 13363 13364 struct mlx5_ifc_adv_virtualization_cap_bits { 13365 u8 reserved_at_0[0x3]; 13366 u8 pg_track_log_max_num[0x5]; 13367 u8 pg_track_max_num_range[0x8]; 13368 u8 pg_track_log_min_addr_space[0x8]; 13369 u8 pg_track_log_max_addr_space[0x8]; 13370 13371 u8 reserved_at_20[0x3]; 13372 u8 pg_track_log_min_msg_size[0x5]; 13373 u8 reserved_at_28[0x3]; 13374 u8 pg_track_log_max_msg_size[0x5]; 13375 u8 reserved_at_30[0x3]; 13376 u8 pg_track_log_min_page_size[0x5]; 13377 u8 reserved_at_38[0x3]; 13378 u8 pg_track_log_max_page_size[0x5]; 13379 13380 u8 reserved_at_40[0x7c0]; 13381 }; 13382 13383 struct mlx5_ifc_page_track_report_entry_bits { 13384 u8 dirty_address_high[0x20]; 13385 13386 u8 dirty_address_low[0x20]; 13387 }; 13388 13389 enum { 13390 MLX5_PAGE_TRACK_STATE_TRACKING, 13391 MLX5_PAGE_TRACK_STATE_REPORTING, 13392 MLX5_PAGE_TRACK_STATE_ERROR, 13393 }; 13394 13395 struct mlx5_ifc_page_track_range_bits { 13396 u8 start_address[0x40]; 13397 13398 u8 length[0x40]; 13399 }; 13400 13401 struct mlx5_ifc_page_track_bits { 13402 u8 modify_field_select[0x40]; 13403 13404 u8 reserved_at_40[0x10]; 13405 u8 vhca_id[0x10]; 13406 13407 u8 reserved_at_60[0x20]; 13408 13409 u8 state[0x4]; 13410 u8 track_type[0x4]; 13411 u8 log_addr_space_size[0x8]; 13412 u8 reserved_at_90[0x3]; 13413 u8 log_page_size[0x5]; 13414 u8 reserved_at_98[0x3]; 13415 u8 log_msg_size[0x5]; 13416 13417 u8 reserved_at_a0[0x8]; 13418 u8 reporting_qpn[0x18]; 13419 13420 u8 reserved_at_c0[0x18]; 13421 u8 num_ranges[0x8]; 13422 13423 u8 reserved_at_e0[0x20]; 13424 13425 u8 range_start_address[0x40]; 13426 13427 u8 length[0x40]; 13428 13429 struct mlx5_ifc_page_track_range_bits track_range[0]; 13430 }; 13431 13432 struct mlx5_ifc_create_page_track_obj_in_bits { 13433 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 13434 struct mlx5_ifc_page_track_bits obj_context; 13435 }; 13436 13437 struct mlx5_ifc_modify_page_track_obj_in_bits { 13438 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 13439 struct mlx5_ifc_page_track_bits obj_context; 13440 }; 13441 13442 struct mlx5_ifc_query_page_track_obj_out_bits { 13443 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 13444 struct mlx5_ifc_page_track_bits obj_context; 13445 }; 13446 13447 struct mlx5_ifc_msecq_reg_bits { 13448 u8 reserved_at_0[0x20]; 13449 13450 u8 reserved_at_20[0x12]; 13451 u8 network_option[0x2]; 13452 u8 local_ssm_code[0x4]; 13453 u8 local_enhanced_ssm_code[0x8]; 13454 13455 u8 local_clock_identity[0x40]; 13456 13457 u8 reserved_at_80[0x180]; 13458 }; 13459 13460 enum { 13461 MLX5_MSEES_FIELD_SELECT_ENABLE = BIT(0), 13462 MLX5_MSEES_FIELD_SELECT_ADMIN_STATUS = BIT(1), 13463 MLX5_MSEES_FIELD_SELECT_ADMIN_FREQ_MEASURE = BIT(2), 13464 }; 13465 13466 enum mlx5_msees_admin_status { 13467 MLX5_MSEES_ADMIN_STATUS_FREE_RUNNING = 0x0, 13468 MLX5_MSEES_ADMIN_STATUS_TRACK = 0x1, 13469 }; 13470 13471 enum mlx5_msees_oper_status { 13472 MLX5_MSEES_OPER_STATUS_FREE_RUNNING = 0x0, 13473 MLX5_MSEES_OPER_STATUS_SELF_TRACK = 0x1, 13474 MLX5_MSEES_OPER_STATUS_OTHER_TRACK = 0x2, 13475 MLX5_MSEES_OPER_STATUS_HOLDOVER = 0x3, 13476 MLX5_MSEES_OPER_STATUS_FAIL_HOLDOVER = 0x4, 13477 MLX5_MSEES_OPER_STATUS_FAIL_FREE_RUNNING = 0x5, 13478 }; 13479 13480 enum mlx5_msees_failure_reason { 13481 MLX5_MSEES_FAILURE_REASON_UNDEFINED_ERROR = 0x0, 13482 MLX5_MSEES_FAILURE_REASON_PORT_DOWN = 0x1, 13483 MLX5_MSEES_FAILURE_REASON_TOO_HIGH_FREQUENCY_DIFF = 0x2, 13484 MLX5_MSEES_FAILURE_REASON_NET_SYNCHRONIZER_DEVICE_ERROR = 0x3, 13485 MLX5_MSEES_FAILURE_REASON_LACK_OF_RESOURCES = 0x4, 13486 }; 13487 13488 struct mlx5_ifc_msees_reg_bits { 13489 u8 reserved_at_0[0x8]; 13490 u8 local_port[0x8]; 13491 u8 pnat[0x2]; 13492 u8 lp_msb[0x2]; 13493 u8 reserved_at_14[0xc]; 13494 13495 u8 field_select[0x20]; 13496 13497 u8 admin_status[0x4]; 13498 u8 oper_status[0x4]; 13499 u8 ho_acq[0x1]; 13500 u8 reserved_at_49[0xc]; 13501 u8 admin_freq_measure[0x1]; 13502 u8 oper_freq_measure[0x1]; 13503 u8 failure_reason[0x9]; 13504 13505 u8 frequency_diff[0x20]; 13506 13507 u8 reserved_at_80[0x180]; 13508 }; 13509 13510 struct mlx5_ifc_mrtcq_reg_bits { 13511 u8 reserved_at_0[0x40]; 13512 13513 u8 rt_clock_identity[0x40]; 13514 13515 u8 reserved_at_80[0x180]; 13516 }; 13517 13518 struct mlx5_ifc_pcie_cong_event_obj_bits { 13519 u8 modify_select_field[0x40]; 13520 13521 u8 inbound_event_en[0x1]; 13522 u8 outbound_event_en[0x1]; 13523 u8 reserved_at_42[0x1e]; 13524 13525 u8 reserved_at_60[0x1]; 13526 u8 inbound_cong_state[0x3]; 13527 u8 reserved_at_64[0x1]; 13528 u8 outbound_cong_state[0x3]; 13529 u8 reserved_at_68[0x18]; 13530 13531 u8 inbound_cong_low_threshold[0x10]; 13532 u8 inbound_cong_high_threshold[0x10]; 13533 13534 u8 outbound_cong_low_threshold[0x10]; 13535 u8 outbound_cong_high_threshold[0x10]; 13536 13537 u8 reserved_at_e0[0x340]; 13538 }; 13539 13540 struct mlx5_ifc_pcie_cong_event_cmd_in_bits { 13541 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 13542 struct mlx5_ifc_pcie_cong_event_obj_bits cong_obj; 13543 }; 13544 13545 struct mlx5_ifc_pcie_cong_event_cmd_out_bits { 13546 struct mlx5_ifc_general_obj_out_cmd_hdr_bits hdr; 13547 struct mlx5_ifc_pcie_cong_event_obj_bits cong_obj; 13548 }; 13549 13550 enum mlx5e_pcie_cong_event_mod_field { 13551 MLX5_PCIE_CONG_EVENT_MOD_EVENT_EN = BIT(0), 13552 MLX5_PCIE_CONG_EVENT_MOD_THRESH = BIT(2), 13553 }; 13554 13555 struct mlx5_ifc_psp_rotate_key_in_bits { 13556 u8 opcode[0x10]; 13557 u8 uid[0x10]; 13558 13559 u8 reserved_at_20[0x10]; 13560 u8 op_mod[0x10]; 13561 13562 u8 reserved_at_40[0x40]; 13563 }; 13564 13565 struct mlx5_ifc_psp_rotate_key_out_bits { 13566 u8 status[0x8]; 13567 u8 reserved_at_8[0x18]; 13568 13569 u8 syndrome[0x20]; 13570 13571 u8 reserved_at_40[0x40]; 13572 }; 13573 13574 enum mlx5_psp_gen_spi_in_key_size { 13575 MLX5_PSP_GEN_SPI_IN_KEY_SIZE_128 = 0x0, 13576 MLX5_PSP_GEN_SPI_IN_KEY_SIZE_256 = 0x1, 13577 }; 13578 13579 struct mlx5_ifc_key_spi_bits { 13580 u8 spi[0x20]; 13581 13582 u8 reserved_at_20[0x60]; 13583 13584 u8 key[8][0x20]; 13585 }; 13586 13587 struct mlx5_ifc_psp_gen_spi_in_bits { 13588 u8 opcode[0x10]; 13589 u8 uid[0x10]; 13590 13591 u8 reserved_at_20[0x10]; 13592 u8 op_mod[0x10]; 13593 13594 u8 reserved_at_40[0x20]; 13595 13596 u8 key_size[0x2]; 13597 u8 reserved_at_62[0xe]; 13598 u8 num_of_spi[0x10]; 13599 }; 13600 13601 struct mlx5_ifc_psp_gen_spi_out_bits { 13602 u8 status[0x8]; 13603 u8 reserved_at_8[0x18]; 13604 13605 u8 syndrome[0x20]; 13606 13607 u8 reserved_at_40[0x10]; 13608 u8 num_of_spi[0x10]; 13609 13610 u8 reserved_at_60[0x20]; 13611 13612 struct mlx5_ifc_key_spi_bits key_spi[]; 13613 }; 13614 13615 #endif /* MLX5_IFC_H */ 13616