xref: /linux/include/linux/mlx5/mlx5_ifc.h (revision cc2f08129925b437bf28f7f7822f20dac083a87c) 
1 /*
2  * Copyright (c) 2013-2015, Mellanox Technologies, Ltd.  All rights reserved.
3  *
4  * This software is available to you under a choice of one of two
5  * licenses.  You may choose to be licensed under the terms of the GNU
6  * General Public License (GPL) Version 2, available from the file
7  * COPYING in the main directory of this source tree, or the
8  * OpenIB.org BSD license below:
9  *
10  *     Redistribution and use in source and binary forms, with or
11  *     without modification, are permitted provided that the following
12  *     conditions are met:
13  *
14  *      - Redistributions of source code must retain the above
15  *        copyright notice, this list of conditions and the following
16  *        disclaimer.
17  *
18  *      - Redistributions in binary form must reproduce the above
19  *        copyright notice, this list of conditions and the following
20  *        disclaimer in the documentation and/or other materials
21  *        provided with the distribution.
22  *
23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30  * SOFTWARE.
31 */
32 #ifndef MLX5_IFC_H
33 #define MLX5_IFC_H
34 
35 #include "mlx5_ifc_fpga.h"
36 
37 enum {
38 	MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS                   = 0x0,
39 	MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED             = 0x1,
40 	MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED           = 0x2,
41 	MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED                  = 0x3,
42 	MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED                    = 0x13,
43 	MLX5_EVENT_TYPE_CODING_SRQ_LIMIT                           = 0x14,
44 	MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED          = 0x1c,
45 	MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION            = 0x1d,
46 	MLX5_EVENT_TYPE_CODING_CQ_ERROR                            = 0x4,
47 	MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR         = 0x5,
48 	MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED               = 0x7,
49 	MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT                    = 0xc,
50 	MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR      = 0x10,
51 	MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR     = 0x11,
52 	MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR        = 0x12,
53 	MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR                      = 0x8,
54 	MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE                   = 0x9,
55 	MLX5_EVENT_TYPE_CODING_GPIO_EVENT                          = 0x15,
56 	MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19,
57 	MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a,
58 	MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT                      = 0x1b,
59 	MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT         = 0x1f,
60 	MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION        = 0xa,
61 	MLX5_EVENT_TYPE_CODING_PAGE_REQUEST                        = 0xb,
62 	MLX5_EVENT_TYPE_CODING_FPGA_ERROR                          = 0x20,
63 	MLX5_EVENT_TYPE_CODING_FPGA_QP_ERROR                       = 0x21
64 };
65 
66 enum {
67 	MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE        = 0x0,
68 	MLX5_SET_HCA_CAP_OP_MOD_ETHERNET_OFFLOADS     = 0x1,
69 	MLX5_SET_HCA_CAP_OP_MOD_ODP                   = 0x2,
70 	MLX5_SET_HCA_CAP_OP_MOD_ATOMIC                = 0x3,
71 	MLX5_SET_HCA_CAP_OP_MOD_ROCE                  = 0x4,
72 	MLX5_SET_HCA_CAP_OP_MOD_IPSEC                 = 0x15,
73 	MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE2       = 0x20,
74 	MLX5_SET_HCA_CAP_OP_MOD_PORT_SELECTION        = 0x25,
75 };
76 
77 enum {
78 	MLX5_SHARED_RESOURCE_UID = 0xffff,
79 };
80 
81 enum {
82 	MLX5_OBJ_TYPE_SW_ICM = 0x0008,
83 	MLX5_OBJ_TYPE_GENEVE_TLV_OPT = 0x000b,
84 	MLX5_OBJ_TYPE_VIRTIO_NET_Q = 0x000d,
85 	MLX5_OBJ_TYPE_VIRTIO_Q_COUNTERS = 0x001c,
86 	MLX5_OBJ_TYPE_MATCH_DEFINER = 0x0018,
87 	MLX5_OBJ_TYPE_HEADER_MODIFY_ARGUMENT  = 0x23,
88 	MLX5_OBJ_TYPE_STC = 0x0040,
89 	MLX5_OBJ_TYPE_RTC = 0x0041,
90 	MLX5_OBJ_TYPE_STE = 0x0042,
91 	MLX5_OBJ_TYPE_MODIFY_HDR_PATTERN = 0x0043,
92 	MLX5_OBJ_TYPE_PAGE_TRACK = 0x46,
93 	MLX5_OBJ_TYPE_MKEY = 0xff01,
94 	MLX5_OBJ_TYPE_QP = 0xff02,
95 	MLX5_OBJ_TYPE_PSV = 0xff03,
96 	MLX5_OBJ_TYPE_RMP = 0xff04,
97 	MLX5_OBJ_TYPE_XRC_SRQ = 0xff05,
98 	MLX5_OBJ_TYPE_RQ = 0xff06,
99 	MLX5_OBJ_TYPE_SQ = 0xff07,
100 	MLX5_OBJ_TYPE_TIR = 0xff08,
101 	MLX5_OBJ_TYPE_TIS = 0xff09,
102 	MLX5_OBJ_TYPE_DCT = 0xff0a,
103 	MLX5_OBJ_TYPE_XRQ = 0xff0b,
104 	MLX5_OBJ_TYPE_RQT = 0xff0e,
105 	MLX5_OBJ_TYPE_FLOW_COUNTER = 0xff0f,
106 	MLX5_OBJ_TYPE_CQ = 0xff10,
107 	MLX5_OBJ_TYPE_FT_ALIAS = 0xff15,
108 };
109 
110 enum {
111 	MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM = (1ULL << MLX5_OBJ_TYPE_SW_ICM),
112 	MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT = (1ULL << 11),
113 	MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q = (1ULL << 13),
114 	MLX5_GENERAL_OBJ_TYPES_CAP_HEADER_MODIFY_ARGUMENT =
115 		(1ULL << MLX5_OBJ_TYPE_HEADER_MODIFY_ARGUMENT),
116 	MLX5_GENERAL_OBJ_TYPES_CAP_MACSEC_OFFLOAD = (1ULL << 39),
117 };
118 
119 enum {
120 	MLX5_CMD_OP_QUERY_HCA_CAP                 = 0x100,
121 	MLX5_CMD_OP_QUERY_ADAPTER                 = 0x101,
122 	MLX5_CMD_OP_INIT_HCA                      = 0x102,
123 	MLX5_CMD_OP_TEARDOWN_HCA                  = 0x103,
124 	MLX5_CMD_OP_ENABLE_HCA                    = 0x104,
125 	MLX5_CMD_OP_DISABLE_HCA                   = 0x105,
126 	MLX5_CMD_OP_QUERY_PAGES                   = 0x107,
127 	MLX5_CMD_OP_MANAGE_PAGES                  = 0x108,
128 	MLX5_CMD_OP_SET_HCA_CAP                   = 0x109,
129 	MLX5_CMD_OP_QUERY_ISSI                    = 0x10a,
130 	MLX5_CMD_OP_SET_ISSI                      = 0x10b,
131 	MLX5_CMD_OP_SET_DRIVER_VERSION            = 0x10d,
132 	MLX5_CMD_OP_QUERY_SF_PARTITION            = 0x111,
133 	MLX5_CMD_OP_ALLOC_SF                      = 0x113,
134 	MLX5_CMD_OP_DEALLOC_SF                    = 0x114,
135 	MLX5_CMD_OP_SUSPEND_VHCA                  = 0x115,
136 	MLX5_CMD_OP_RESUME_VHCA                   = 0x116,
137 	MLX5_CMD_OP_QUERY_VHCA_MIGRATION_STATE    = 0x117,
138 	MLX5_CMD_OP_SAVE_VHCA_STATE               = 0x118,
139 	MLX5_CMD_OP_LOAD_VHCA_STATE               = 0x119,
140 	MLX5_CMD_OP_CREATE_MKEY                   = 0x200,
141 	MLX5_CMD_OP_QUERY_MKEY                    = 0x201,
142 	MLX5_CMD_OP_DESTROY_MKEY                  = 0x202,
143 	MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS        = 0x203,
144 	MLX5_CMD_OP_PAGE_FAULT_RESUME             = 0x204,
145 	MLX5_CMD_OP_ALLOC_MEMIC                   = 0x205,
146 	MLX5_CMD_OP_DEALLOC_MEMIC                 = 0x206,
147 	MLX5_CMD_OP_MODIFY_MEMIC                  = 0x207,
148 	MLX5_CMD_OP_CREATE_EQ                     = 0x301,
149 	MLX5_CMD_OP_DESTROY_EQ                    = 0x302,
150 	MLX5_CMD_OP_QUERY_EQ                      = 0x303,
151 	MLX5_CMD_OP_GEN_EQE                       = 0x304,
152 	MLX5_CMD_OP_CREATE_CQ                     = 0x400,
153 	MLX5_CMD_OP_DESTROY_CQ                    = 0x401,
154 	MLX5_CMD_OP_QUERY_CQ                      = 0x402,
155 	MLX5_CMD_OP_MODIFY_CQ                     = 0x403,
156 	MLX5_CMD_OP_CREATE_QP                     = 0x500,
157 	MLX5_CMD_OP_DESTROY_QP                    = 0x501,
158 	MLX5_CMD_OP_RST2INIT_QP                   = 0x502,
159 	MLX5_CMD_OP_INIT2RTR_QP                   = 0x503,
160 	MLX5_CMD_OP_RTR2RTS_QP                    = 0x504,
161 	MLX5_CMD_OP_RTS2RTS_QP                    = 0x505,
162 	MLX5_CMD_OP_SQERR2RTS_QP                  = 0x506,
163 	MLX5_CMD_OP_2ERR_QP                       = 0x507,
164 	MLX5_CMD_OP_2RST_QP                       = 0x50a,
165 	MLX5_CMD_OP_QUERY_QP                      = 0x50b,
166 	MLX5_CMD_OP_SQD_RTS_QP                    = 0x50c,
167 	MLX5_CMD_OP_INIT2INIT_QP                  = 0x50e,
168 	MLX5_CMD_OP_CREATE_PSV                    = 0x600,
169 	MLX5_CMD_OP_DESTROY_PSV                   = 0x601,
170 	MLX5_CMD_OP_CREATE_SRQ                    = 0x700,
171 	MLX5_CMD_OP_DESTROY_SRQ                   = 0x701,
172 	MLX5_CMD_OP_QUERY_SRQ                     = 0x702,
173 	MLX5_CMD_OP_ARM_RQ                        = 0x703,
174 	MLX5_CMD_OP_CREATE_XRC_SRQ                = 0x705,
175 	MLX5_CMD_OP_DESTROY_XRC_SRQ               = 0x706,
176 	MLX5_CMD_OP_QUERY_XRC_SRQ                 = 0x707,
177 	MLX5_CMD_OP_ARM_XRC_SRQ                   = 0x708,
178 	MLX5_CMD_OP_CREATE_DCT                    = 0x710,
179 	MLX5_CMD_OP_DESTROY_DCT                   = 0x711,
180 	MLX5_CMD_OP_DRAIN_DCT                     = 0x712,
181 	MLX5_CMD_OP_QUERY_DCT                     = 0x713,
182 	MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION     = 0x714,
183 	MLX5_CMD_OP_CREATE_XRQ                    = 0x717,
184 	MLX5_CMD_OP_DESTROY_XRQ                   = 0x718,
185 	MLX5_CMD_OP_QUERY_XRQ                     = 0x719,
186 	MLX5_CMD_OP_ARM_XRQ                       = 0x71a,
187 	MLX5_CMD_OP_QUERY_XRQ_DC_PARAMS_ENTRY     = 0x725,
188 	MLX5_CMD_OP_SET_XRQ_DC_PARAMS_ENTRY       = 0x726,
189 	MLX5_CMD_OP_QUERY_XRQ_ERROR_PARAMS        = 0x727,
190 	MLX5_CMD_OP_RELEASE_XRQ_ERROR             = 0x729,
191 	MLX5_CMD_OP_MODIFY_XRQ                    = 0x72a,
192 	MLX5_CMD_OPCODE_QUERY_DELEGATED_VHCA      = 0x732,
193 	MLX5_CMD_OPCODE_CREATE_ESW_VPORT          = 0x733,
194 	MLX5_CMD_OPCODE_DESTROY_ESW_VPORT         = 0x734,
195 	MLX5_CMD_OP_QUERY_ESW_FUNCTIONS           = 0x740,
196 	MLX5_CMD_OP_QUERY_VPORT_STATE             = 0x750,
197 	MLX5_CMD_OP_MODIFY_VPORT_STATE            = 0x751,
198 	MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT       = 0x752,
199 	MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT      = 0x753,
200 	MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT       = 0x754,
201 	MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT      = 0x755,
202 	MLX5_CMD_OP_QUERY_ROCE_ADDRESS            = 0x760,
203 	MLX5_CMD_OP_SET_ROCE_ADDRESS              = 0x761,
204 	MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT       = 0x762,
205 	MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT      = 0x763,
206 	MLX5_CMD_OP_QUERY_HCA_VPORT_GID           = 0x764,
207 	MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY          = 0x765,
208 	MLX5_CMD_OP_QUERY_VNIC_ENV                = 0x76f,
209 	MLX5_CMD_OP_QUERY_VPORT_COUNTER           = 0x770,
210 	MLX5_CMD_OP_ALLOC_Q_COUNTER               = 0x771,
211 	MLX5_CMD_OP_DEALLOC_Q_COUNTER             = 0x772,
212 	MLX5_CMD_OP_QUERY_Q_COUNTER               = 0x773,
213 	MLX5_CMD_OP_SET_MONITOR_COUNTER           = 0x774,
214 	MLX5_CMD_OP_ARM_MONITOR_COUNTER           = 0x775,
215 	MLX5_CMD_OP_SET_PP_RATE_LIMIT             = 0x780,
216 	MLX5_CMD_OP_QUERY_RATE_LIMIT              = 0x781,
217 	MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT      = 0x782,
218 	MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT     = 0x783,
219 	MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT       = 0x784,
220 	MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT      = 0x785,
221 	MLX5_CMD_OP_CREATE_QOS_PARA_VPORT         = 0x786,
222 	MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT        = 0x787,
223 	MLX5_CMD_OP_ALLOC_PD                      = 0x800,
224 	MLX5_CMD_OP_DEALLOC_PD                    = 0x801,
225 	MLX5_CMD_OP_ALLOC_UAR                     = 0x802,
226 	MLX5_CMD_OP_DEALLOC_UAR                   = 0x803,
227 	MLX5_CMD_OP_CONFIG_INT_MODERATION         = 0x804,
228 	MLX5_CMD_OP_ACCESS_REG                    = 0x805,
229 	MLX5_CMD_OP_ATTACH_TO_MCG                 = 0x806,
230 	MLX5_CMD_OP_DETACH_FROM_MCG               = 0x807,
231 	MLX5_CMD_OP_GET_DROPPED_PACKET_LOG        = 0x80a,
232 	MLX5_CMD_OP_MAD_IFC                       = 0x50d,
233 	MLX5_CMD_OP_QUERY_MAD_DEMUX               = 0x80b,
234 	MLX5_CMD_OP_SET_MAD_DEMUX                 = 0x80c,
235 	MLX5_CMD_OP_NOP                           = 0x80d,
236 	MLX5_CMD_OP_ALLOC_XRCD                    = 0x80e,
237 	MLX5_CMD_OP_DEALLOC_XRCD                  = 0x80f,
238 	MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN        = 0x816,
239 	MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN      = 0x817,
240 	MLX5_CMD_OP_QUERY_CONG_STATUS             = 0x822,
241 	MLX5_CMD_OP_MODIFY_CONG_STATUS            = 0x823,
242 	MLX5_CMD_OP_QUERY_CONG_PARAMS             = 0x824,
243 	MLX5_CMD_OP_MODIFY_CONG_PARAMS            = 0x825,
244 	MLX5_CMD_OP_QUERY_CONG_STATISTICS         = 0x826,
245 	MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT           = 0x827,
246 	MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT        = 0x828,
247 	MLX5_CMD_OP_SET_L2_TABLE_ENTRY            = 0x829,
248 	MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY          = 0x82a,
249 	MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY         = 0x82b,
250 	MLX5_CMD_OP_SET_WOL_ROL                   = 0x830,
251 	MLX5_CMD_OP_QUERY_WOL_ROL                 = 0x831,
252 	MLX5_CMD_OP_CREATE_LAG                    = 0x840,
253 	MLX5_CMD_OP_MODIFY_LAG                    = 0x841,
254 	MLX5_CMD_OP_QUERY_LAG                     = 0x842,
255 	MLX5_CMD_OP_DESTROY_LAG                   = 0x843,
256 	MLX5_CMD_OP_CREATE_VPORT_LAG              = 0x844,
257 	MLX5_CMD_OP_DESTROY_VPORT_LAG             = 0x845,
258 	MLX5_CMD_OP_CREATE_TIR                    = 0x900,
259 	MLX5_CMD_OP_MODIFY_TIR                    = 0x901,
260 	MLX5_CMD_OP_DESTROY_TIR                   = 0x902,
261 	MLX5_CMD_OP_QUERY_TIR                     = 0x903,
262 	MLX5_CMD_OP_CREATE_SQ                     = 0x904,
263 	MLX5_CMD_OP_MODIFY_SQ                     = 0x905,
264 	MLX5_CMD_OP_DESTROY_SQ                    = 0x906,
265 	MLX5_CMD_OP_QUERY_SQ                      = 0x907,
266 	MLX5_CMD_OP_CREATE_RQ                     = 0x908,
267 	MLX5_CMD_OP_MODIFY_RQ                     = 0x909,
268 	MLX5_CMD_OP_SET_DELAY_DROP_PARAMS         = 0x910,
269 	MLX5_CMD_OP_DESTROY_RQ                    = 0x90a,
270 	MLX5_CMD_OP_QUERY_RQ                      = 0x90b,
271 	MLX5_CMD_OP_CREATE_RMP                    = 0x90c,
272 	MLX5_CMD_OP_MODIFY_RMP                    = 0x90d,
273 	MLX5_CMD_OP_DESTROY_RMP                   = 0x90e,
274 	MLX5_CMD_OP_QUERY_RMP                     = 0x90f,
275 	MLX5_CMD_OP_CREATE_TIS                    = 0x912,
276 	MLX5_CMD_OP_MODIFY_TIS                    = 0x913,
277 	MLX5_CMD_OP_DESTROY_TIS                   = 0x914,
278 	MLX5_CMD_OP_QUERY_TIS                     = 0x915,
279 	MLX5_CMD_OP_CREATE_RQT                    = 0x916,
280 	MLX5_CMD_OP_MODIFY_RQT                    = 0x917,
281 	MLX5_CMD_OP_DESTROY_RQT                   = 0x918,
282 	MLX5_CMD_OP_QUERY_RQT                     = 0x919,
283 	MLX5_CMD_OP_SET_FLOW_TABLE_ROOT		  = 0x92f,
284 	MLX5_CMD_OP_CREATE_FLOW_TABLE             = 0x930,
285 	MLX5_CMD_OP_DESTROY_FLOW_TABLE            = 0x931,
286 	MLX5_CMD_OP_QUERY_FLOW_TABLE              = 0x932,
287 	MLX5_CMD_OP_CREATE_FLOW_GROUP             = 0x933,
288 	MLX5_CMD_OP_DESTROY_FLOW_GROUP            = 0x934,
289 	MLX5_CMD_OP_QUERY_FLOW_GROUP              = 0x935,
290 	MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY          = 0x936,
291 	MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY        = 0x937,
292 	MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY       = 0x938,
293 	MLX5_CMD_OP_ALLOC_FLOW_COUNTER            = 0x939,
294 	MLX5_CMD_OP_DEALLOC_FLOW_COUNTER          = 0x93a,
295 	MLX5_CMD_OP_QUERY_FLOW_COUNTER            = 0x93b,
296 	MLX5_CMD_OP_MODIFY_FLOW_TABLE             = 0x93c,
297 	MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT = 0x93d,
298 	MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT = 0x93e,
299 	MLX5_CMD_OP_QUERY_PACKET_REFORMAT_CONTEXT = 0x93f,
300 	MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT   = 0x940,
301 	MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941,
302 	MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT   = 0x942,
303 	MLX5_CMD_OP_FPGA_CREATE_QP                = 0x960,
304 	MLX5_CMD_OP_FPGA_MODIFY_QP                = 0x961,
305 	MLX5_CMD_OP_FPGA_QUERY_QP                 = 0x962,
306 	MLX5_CMD_OP_FPGA_DESTROY_QP               = 0x963,
307 	MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS        = 0x964,
308 	MLX5_CMD_OP_CREATE_GENERAL_OBJECT         = 0xa00,
309 	MLX5_CMD_OP_MODIFY_GENERAL_OBJECT         = 0xa01,
310 	MLX5_CMD_OP_QUERY_GENERAL_OBJECT          = 0xa02,
311 	MLX5_CMD_OP_DESTROY_GENERAL_OBJECT        = 0xa03,
312 	MLX5_CMD_OP_CREATE_UCTX                   = 0xa04,
313 	MLX5_CMD_OP_DESTROY_UCTX                  = 0xa06,
314 	MLX5_CMD_OP_CREATE_UMEM                   = 0xa08,
315 	MLX5_CMD_OP_DESTROY_UMEM                  = 0xa0a,
316 	MLX5_CMD_OP_SYNC_STEERING                 = 0xb00,
317 	MLX5_CMD_OP_PSP_GEN_SPI                   = 0xb10,
318 	MLX5_CMD_OP_PSP_ROTATE_KEY                = 0xb11,
319 	MLX5_CMD_OP_QUERY_VHCA_STATE              = 0xb0d,
320 	MLX5_CMD_OP_MODIFY_VHCA_STATE             = 0xb0e,
321 	MLX5_CMD_OP_SYNC_CRYPTO                   = 0xb12,
322 	MLX5_CMD_OP_ALLOW_OTHER_VHCA_ACCESS       = 0xb16,
323 	MLX5_CMD_OP_GENERATE_WQE                  = 0xb17,
324 	MLX5_CMD_OPCODE_QUERY_VUID                = 0xb22,
325 	MLX5_CMD_OP_MAX
326 };
327 
328 /* Valid range for general commands that don't work over an object */
329 enum {
330 	MLX5_CMD_OP_GENERAL_START = 0xb00,
331 	MLX5_CMD_OP_GENERAL_END = 0xd00,
332 };
333 
334 enum {
335 	MLX5_FT_NIC_RX_2_NIC_RX_RDMA = BIT(0),
336 	MLX5_FT_NIC_TX_RDMA_2_NIC_TX = BIT(1),
337 };
338 
339 enum {
340 	MLX5_CMD_OP_MOD_UPDATE_HEADER_MODIFY_ARGUMENT = 0x1,
341 };
342 
343 struct mlx5_ifc_flow_table_fields_supported_bits {
344 	u8         outer_dmac[0x1];
345 	u8         outer_smac[0x1];
346 	u8         outer_ether_type[0x1];
347 	u8         outer_ip_version[0x1];
348 	u8         outer_first_prio[0x1];
349 	u8         outer_first_cfi[0x1];
350 	u8         outer_first_vid[0x1];
351 	u8         outer_ipv4_ttl[0x1];
352 	u8         outer_second_prio[0x1];
353 	u8         outer_second_cfi[0x1];
354 	u8         outer_second_vid[0x1];
355 	u8         reserved_at_b[0x1];
356 	u8         outer_sip[0x1];
357 	u8         outer_dip[0x1];
358 	u8         outer_frag[0x1];
359 	u8         outer_ip_protocol[0x1];
360 	u8         outer_ip_ecn[0x1];
361 	u8         outer_ip_dscp[0x1];
362 	u8         outer_udp_sport[0x1];
363 	u8         outer_udp_dport[0x1];
364 	u8         outer_tcp_sport[0x1];
365 	u8         outer_tcp_dport[0x1];
366 	u8         outer_tcp_flags[0x1];
367 	u8         outer_gre_protocol[0x1];
368 	u8         outer_gre_key[0x1];
369 	u8         outer_vxlan_vni[0x1];
370 	u8         outer_geneve_vni[0x1];
371 	u8         outer_geneve_oam[0x1];
372 	u8         outer_geneve_protocol_type[0x1];
373 	u8         outer_geneve_opt_len[0x1];
374 	u8         source_vhca_port[0x1];
375 	u8         source_eswitch_port[0x1];
376 
377 	u8         inner_dmac[0x1];
378 	u8         inner_smac[0x1];
379 	u8         inner_ether_type[0x1];
380 	u8         inner_ip_version[0x1];
381 	u8         inner_first_prio[0x1];
382 	u8         inner_first_cfi[0x1];
383 	u8         inner_first_vid[0x1];
384 	u8         reserved_at_27[0x1];
385 	u8         inner_second_prio[0x1];
386 	u8         inner_second_cfi[0x1];
387 	u8         inner_second_vid[0x1];
388 	u8         reserved_at_2b[0x1];
389 	u8         inner_sip[0x1];
390 	u8         inner_dip[0x1];
391 	u8         inner_frag[0x1];
392 	u8         inner_ip_protocol[0x1];
393 	u8         inner_ip_ecn[0x1];
394 	u8         inner_ip_dscp[0x1];
395 	u8         inner_udp_sport[0x1];
396 	u8         inner_udp_dport[0x1];
397 	u8         inner_tcp_sport[0x1];
398 	u8         inner_tcp_dport[0x1];
399 	u8         inner_tcp_flags[0x1];
400 	u8         reserved_at_37[0x9];
401 
402 	u8         geneve_tlv_option_0_data[0x1];
403 	u8         geneve_tlv_option_0_exist[0x1];
404 	u8         reserved_at_42[0x3];
405 	u8         outer_first_mpls_over_udp[0x4];
406 	u8         outer_first_mpls_over_gre[0x4];
407 	u8         inner_first_mpls[0x4];
408 	u8         outer_first_mpls[0x4];
409 	u8         reserved_at_55[0x2];
410 	u8	   outer_esp_spi[0x1];
411 	u8         reserved_at_58[0x2];
412 	u8         bth_dst_qp[0x1];
413 	u8         reserved_at_5b[0x5];
414 
415 	u8         reserved_at_60[0x18];
416 	u8         metadata_reg_c_7[0x1];
417 	u8         metadata_reg_c_6[0x1];
418 	u8         metadata_reg_c_5[0x1];
419 	u8         metadata_reg_c_4[0x1];
420 	u8         metadata_reg_c_3[0x1];
421 	u8         metadata_reg_c_2[0x1];
422 	u8         metadata_reg_c_1[0x1];
423 	u8         metadata_reg_c_0[0x1];
424 };
425 
426 /* Table 2170 - Flow Table Fields Supported 2 Format */
427 struct mlx5_ifc_flow_table_fields_supported_2_bits {
428 	u8         inner_l4_type_ext[0x1];
429 	u8         outer_l4_type_ext[0x1];
430 	u8         inner_l4_type[0x1];
431 	u8         outer_l4_type[0x1];
432 	u8         reserved_at_4[0xa];
433 	u8         bth_opcode[0x1];
434 	u8         reserved_at_f[0x1];
435 	u8         tunnel_header_0_1[0x1];
436 	u8         reserved_at_11[0xf];
437 
438 	u8         reserved_at_20[0xf];
439 	u8         ipsec_next_header[0x1];
440 	u8         reserved_at_30[0x10];
441 
442 	u8         reserved_at_40[0x40];
443 };
444 
445 struct mlx5_ifc_flow_table_prop_layout_bits {
446 	u8         ft_support[0x1];
447 	u8         reserved_at_1[0x1];
448 	u8         flow_counter[0x1];
449 	u8	   flow_modify_en[0x1];
450 	u8         modify_root[0x1];
451 	u8         identified_miss_table_mode[0x1];
452 	u8         flow_table_modify[0x1];
453 	u8         reformat[0x1];
454 	u8         decap[0x1];
455 	u8         reset_root_to_default[0x1];
456 	u8         pop_vlan[0x1];
457 	u8         push_vlan[0x1];
458 	u8         reserved_at_c[0x1];
459 	u8         pop_vlan_2[0x1];
460 	u8         push_vlan_2[0x1];
461 	u8	   reformat_and_vlan_action[0x1];
462 	u8	   reserved_at_10[0x1];
463 	u8         sw_owner[0x1];
464 	u8	   reformat_l3_tunnel_to_l2[0x1];
465 	u8	   reformat_l2_to_l3_tunnel[0x1];
466 	u8	   reformat_and_modify_action[0x1];
467 	u8	   ignore_flow_level[0x1];
468 	u8         reserved_at_16[0x1];
469 	u8	   table_miss_action_domain[0x1];
470 	u8         termination_table[0x1];
471 	u8         reformat_and_fwd_to_table[0x1];
472 	u8         reserved_at_1a[0x2];
473 	u8         ipsec_encrypt[0x1];
474 	u8         ipsec_decrypt[0x1];
475 	u8         sw_owner_v2[0x1];
476 	u8         reserved_at_1f[0x1];
477 
478 	u8         termination_table_raw_traffic[0x1];
479 	u8         reserved_at_21[0x1];
480 	u8         log_max_ft_size[0x6];
481 	u8         log_max_modify_header_context[0x8];
482 	u8         max_modify_header_actions[0x8];
483 	u8         max_ft_level[0x8];
484 
485 	u8         reformat_add_esp_trasport[0x1];
486 	u8         reformat_l2_to_l3_esp_tunnel[0x1];
487 	u8         reformat_add_esp_transport_over_udp[0x1];
488 	u8         reformat_del_esp_trasport[0x1];
489 	u8         reformat_l3_esp_tunnel_to_l2[0x1];
490 	u8         reformat_del_esp_transport_over_udp[0x1];
491 	u8         execute_aso[0x1];
492 	u8         reserved_at_47[0x19];
493 
494 	u8         reformat_l2_to_l3_psp_tunnel[0x1];
495 	u8         reformat_l3_psp_tunnel_to_l2[0x1];
496 	u8         reformat_insert[0x1];
497 	u8         reformat_remove[0x1];
498 	u8         macsec_encrypt[0x1];
499 	u8         macsec_decrypt[0x1];
500 	u8         psp_encrypt[0x1];
501 	u8         psp_decrypt[0x1];
502 	u8         reformat_add_macsec[0x1];
503 	u8         reformat_remove_macsec[0x1];
504 	u8         reparse[0x1];
505 	u8         reserved_at_6b[0x1];
506 	u8         cross_vhca_object[0x1];
507 	u8         reformat_l2_to_l3_audp_tunnel[0x1];
508 	u8         reformat_l3_audp_tunnel_to_l2[0x1];
509 	u8         ignore_flow_level_rtc_valid[0x1];
510 	u8         reserved_at_70[0x8];
511 	u8         log_max_ft_num[0x8];
512 
513 	u8         reserved_at_80[0x10];
514 	u8         log_max_flow_counter[0x8];
515 	u8         log_max_destination[0x8];
516 
517 	u8         reserved_at_a0[0x18];
518 	u8         log_max_flow[0x8];
519 
520 	u8         reserved_at_c0[0x40];
521 
522 	struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
523 
524 	struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
525 };
526 
527 struct mlx5_ifc_odp_per_transport_service_cap_bits {
528 	u8         send[0x1];
529 	u8         receive[0x1];
530 	u8         write[0x1];
531 	u8         read[0x1];
532 	u8         atomic[0x1];
533 	u8         srq_receive[0x1];
534 	u8         reserved_at_6[0x1a];
535 };
536 
537 struct mlx5_ifc_ipv4_layout_bits {
538 	u8         reserved_at_0[0x60];
539 
540 	u8         ipv4[0x20];
541 };
542 
543 struct mlx5_ifc_ipv6_layout_bits {
544 	u8         ipv6[16][0x8];
545 };
546 
547 struct mlx5_ifc_ipv6_simple_layout_bits {
548 	u8         ipv6_127_96[0x20];
549 	u8         ipv6_95_64[0x20];
550 	u8         ipv6_63_32[0x20];
551 	u8         ipv6_31_0[0x20];
552 };
553 
554 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits {
555 	struct mlx5_ifc_ipv6_simple_layout_bits ipv6_simple_layout;
556 	struct mlx5_ifc_ipv6_layout_bits ipv6_layout;
557 	struct mlx5_ifc_ipv4_layout_bits ipv4_layout;
558 	u8         reserved_at_0[0x80];
559 };
560 
561 enum {
562 	MLX5_PACKET_L4_TYPE_NONE,
563 	MLX5_PACKET_L4_TYPE_TCP,
564 	MLX5_PACKET_L4_TYPE_UDP,
565 };
566 
567 enum {
568 	MLX5_PACKET_L4_TYPE_EXT_NONE,
569 	MLX5_PACKET_L4_TYPE_EXT_TCP,
570 	MLX5_PACKET_L4_TYPE_EXT_UDP,
571 	MLX5_PACKET_L4_TYPE_EXT_ICMP,
572 };
573 
574 struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
575 	u8         smac_47_16[0x20];
576 
577 	u8         smac_15_0[0x10];
578 	u8         ethertype[0x10];
579 
580 	u8         dmac_47_16[0x20];
581 
582 	u8         dmac_15_0[0x10];
583 	u8         first_prio[0x3];
584 	u8         first_cfi[0x1];
585 	u8         first_vid[0xc];
586 
587 	u8         ip_protocol[0x8];
588 	u8         ip_dscp[0x6];
589 	u8         ip_ecn[0x2];
590 	u8         cvlan_tag[0x1];
591 	u8         svlan_tag[0x1];
592 	u8         frag[0x1];
593 	u8         ip_version[0x4];
594 	u8         tcp_flags[0x9];
595 
596 	u8         tcp_sport[0x10];
597 	u8         tcp_dport[0x10];
598 
599 	u8         l4_type[0x2];
600 	u8         l4_type_ext[0x4];
601 	u8         reserved_at_c6[0xa];
602 	u8         ipv4_ihl[0x4];
603 	u8         reserved_at_d4[0x4];
604 	u8         ttl_hoplimit[0x8];
605 
606 	u8         udp_sport[0x10];
607 	u8         udp_dport[0x10];
608 
609 	union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
610 
611 	union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
612 };
613 
614 struct mlx5_ifc_nvgre_key_bits {
615 	u8 hi[0x18];
616 	u8 lo[0x8];
617 };
618 
619 union mlx5_ifc_gre_key_bits {
620 	struct mlx5_ifc_nvgre_key_bits nvgre;
621 	u8 key[0x20];
622 };
623 
624 struct mlx5_ifc_fte_match_set_misc_bits {
625 	u8         gre_c_present[0x1];
626 	u8         reserved_at_1[0x1];
627 	u8         gre_k_present[0x1];
628 	u8         gre_s_present[0x1];
629 	u8         source_vhca_port[0x4];
630 	u8         source_sqn[0x18];
631 
632 	u8         source_eswitch_owner_vhca_id[0x10];
633 	u8         source_port[0x10];
634 
635 	u8         outer_second_prio[0x3];
636 	u8         outer_second_cfi[0x1];
637 	u8         outer_second_vid[0xc];
638 	u8         inner_second_prio[0x3];
639 	u8         inner_second_cfi[0x1];
640 	u8         inner_second_vid[0xc];
641 
642 	u8         outer_second_cvlan_tag[0x1];
643 	u8         inner_second_cvlan_tag[0x1];
644 	u8         outer_second_svlan_tag[0x1];
645 	u8         inner_second_svlan_tag[0x1];
646 	u8         reserved_at_64[0xc];
647 	u8         gre_protocol[0x10];
648 
649 	union mlx5_ifc_gre_key_bits gre_key;
650 
651 	u8         vxlan_vni[0x18];
652 	u8         bth_opcode[0x8];
653 
654 	u8         geneve_vni[0x18];
655 	u8         reserved_at_d8[0x6];
656 	u8         geneve_tlv_option_0_exist[0x1];
657 	u8         geneve_oam[0x1];
658 
659 	u8         reserved_at_e0[0xc];
660 	u8         outer_ipv6_flow_label[0x14];
661 
662 	u8         reserved_at_100[0xc];
663 	u8         inner_ipv6_flow_label[0x14];
664 
665 	u8         reserved_at_120[0xa];
666 	u8         geneve_opt_len[0x6];
667 	u8         geneve_protocol_type[0x10];
668 
669 	u8         reserved_at_140[0x8];
670 	u8         bth_dst_qp[0x18];
671 	u8	   inner_esp_spi[0x20];
672 	u8	   outer_esp_spi[0x20];
673 	u8         reserved_at_1a0[0x60];
674 };
675 
676 struct mlx5_ifc_fte_match_mpls_bits {
677 	u8         mpls_label[0x14];
678 	u8         mpls_exp[0x3];
679 	u8         mpls_s_bos[0x1];
680 	u8         mpls_ttl[0x8];
681 };
682 
683 struct mlx5_ifc_fte_match_set_misc2_bits {
684 	struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls;
685 
686 	struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls;
687 
688 	struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre;
689 
690 	struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp;
691 
692 	u8         metadata_reg_c_7[0x20];
693 
694 	u8         metadata_reg_c_6[0x20];
695 
696 	u8         metadata_reg_c_5[0x20];
697 
698 	u8         metadata_reg_c_4[0x20];
699 
700 	u8         metadata_reg_c_3[0x20];
701 
702 	u8         metadata_reg_c_2[0x20];
703 
704 	u8         metadata_reg_c_1[0x20];
705 
706 	u8         metadata_reg_c_0[0x20];
707 
708 	u8         metadata_reg_a[0x20];
709 
710 	u8         psp_syndrome[0x8];
711 	u8         macsec_syndrome[0x8];
712 	u8         ipsec_syndrome[0x8];
713 	u8         ipsec_next_header[0x8];
714 
715 	u8         reserved_at_1c0[0x40];
716 };
717 
718 struct mlx5_ifc_fte_match_set_misc3_bits {
719 	u8         inner_tcp_seq_num[0x20];
720 
721 	u8         outer_tcp_seq_num[0x20];
722 
723 	u8         inner_tcp_ack_num[0x20];
724 
725 	u8         outer_tcp_ack_num[0x20];
726 
727 	u8	   reserved_at_80[0x8];
728 	u8         outer_vxlan_gpe_vni[0x18];
729 
730 	u8         outer_vxlan_gpe_next_protocol[0x8];
731 	u8         outer_vxlan_gpe_flags[0x8];
732 	u8	   reserved_at_b0[0x10];
733 
734 	u8	   icmp_header_data[0x20];
735 
736 	u8	   icmpv6_header_data[0x20];
737 
738 	u8	   icmp_type[0x8];
739 	u8	   icmp_code[0x8];
740 	u8	   icmpv6_type[0x8];
741 	u8	   icmpv6_code[0x8];
742 
743 	u8         geneve_tlv_option_0_data[0x20];
744 
745 	u8	   gtpu_teid[0x20];
746 
747 	u8	   gtpu_msg_type[0x8];
748 	u8	   gtpu_msg_flags[0x8];
749 	u8	   reserved_at_170[0x10];
750 
751 	u8	   gtpu_dw_2[0x20];
752 
753 	u8	   gtpu_first_ext_dw_0[0x20];
754 
755 	u8	   gtpu_dw_0[0x20];
756 
757 	u8	   reserved_at_1e0[0x20];
758 };
759 
760 struct mlx5_ifc_fte_match_set_misc4_bits {
761 	u8         prog_sample_field_value_0[0x20];
762 
763 	u8         prog_sample_field_id_0[0x20];
764 
765 	u8         prog_sample_field_value_1[0x20];
766 
767 	u8         prog_sample_field_id_1[0x20];
768 
769 	u8         prog_sample_field_value_2[0x20];
770 
771 	u8         prog_sample_field_id_2[0x20];
772 
773 	u8         prog_sample_field_value_3[0x20];
774 
775 	u8         prog_sample_field_id_3[0x20];
776 
777 	u8         reserved_at_100[0x100];
778 };
779 
780 struct mlx5_ifc_fte_match_set_misc5_bits {
781 	u8         macsec_tag_0[0x20];
782 
783 	u8         macsec_tag_1[0x20];
784 
785 	u8         macsec_tag_2[0x20];
786 
787 	u8         macsec_tag_3[0x20];
788 
789 	u8         tunnel_header_0[0x20];
790 
791 	u8         tunnel_header_1[0x20];
792 
793 	u8         tunnel_header_2[0x20];
794 
795 	u8         tunnel_header_3[0x20];
796 
797 	u8         reserved_at_100[0x100];
798 };
799 
800 struct mlx5_ifc_cmd_pas_bits {
801 	u8         pa_h[0x20];
802 
803 	u8         pa_l[0x14];
804 	u8         reserved_at_34[0xc];
805 };
806 
807 struct mlx5_ifc_uint64_bits {
808 	u8         hi[0x20];
809 
810 	u8         lo[0x20];
811 };
812 
813 enum {
814 	MLX5_ADS_STAT_RATE_NO_LIMIT  = 0x0,
815 	MLX5_ADS_STAT_RATE_2_5GBPS   = 0x7,
816 	MLX5_ADS_STAT_RATE_10GBPS    = 0x8,
817 	MLX5_ADS_STAT_RATE_30GBPS    = 0x9,
818 	MLX5_ADS_STAT_RATE_5GBPS     = 0xa,
819 	MLX5_ADS_STAT_RATE_20GBPS    = 0xb,
820 	MLX5_ADS_STAT_RATE_40GBPS    = 0xc,
821 	MLX5_ADS_STAT_RATE_60GBPS    = 0xd,
822 	MLX5_ADS_STAT_RATE_80GBPS    = 0xe,
823 	MLX5_ADS_STAT_RATE_120GBPS   = 0xf,
824 };
825 
826 struct mlx5_ifc_ads_bits {
827 	u8         fl[0x1];
828 	u8         free_ar[0x1];
829 	u8         reserved_at_2[0xe];
830 	u8         pkey_index[0x10];
831 
832 	u8         plane_index[0x8];
833 	u8         grh[0x1];
834 	u8         mlid[0x7];
835 	u8         rlid[0x10];
836 
837 	u8         ack_timeout[0x5];
838 	u8         reserved_at_45[0x3];
839 	u8         src_addr_index[0x8];
840 	u8         reserved_at_50[0x4];
841 	u8         stat_rate[0x4];
842 	u8         hop_limit[0x8];
843 
844 	u8         reserved_at_60[0x4];
845 	u8         tclass[0x8];
846 	u8         flow_label[0x14];
847 
848 	u8         rgid_rip[16][0x8];
849 
850 	u8         reserved_at_100[0x4];
851 	u8         f_dscp[0x1];
852 	u8         f_ecn[0x1];
853 	u8         reserved_at_106[0x1];
854 	u8         f_eth_prio[0x1];
855 	u8         ecn[0x2];
856 	u8         dscp[0x6];
857 	u8         udp_sport[0x10];
858 
859 	u8         dei_cfi[0x1];
860 	u8         eth_prio[0x3];
861 	u8         sl[0x4];
862 	u8         vhca_port_num[0x8];
863 	u8         rmac_47_32[0x10];
864 
865 	u8         rmac_31_0[0x20];
866 };
867 
868 struct mlx5_ifc_flow_table_nic_cap_bits {
869 	u8         nic_rx_multi_path_tirs[0x1];
870 	u8         nic_rx_multi_path_tirs_fts[0x1];
871 	u8         allow_sniffer_and_nic_rx_shared_tir[0x1];
872 	u8	   reserved_at_3[0x4];
873 	u8	   sw_owner_reformat_supported[0x1];
874 	u8	   reserved_at_8[0x18];
875 
876 	u8	   encap_general_header[0x1];
877 	u8	   reserved_at_21[0xa];
878 	u8	   log_max_packet_reformat_context[0x5];
879 	u8	   reserved_at_30[0x6];
880 	u8	   max_encap_header_size[0xa];
881 	u8	   reserved_at_40[0x1c0];
882 
883 	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
884 
885 	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_rdma;
886 
887 	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
888 
889 	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
890 
891 	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_rdma;
892 
893 	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
894 
895 	u8         reserved_at_e00[0x600];
896 
897 	struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_receive;
898 
899 	u8         reserved_at_1480[0x80];
900 
901 	struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_receive_rdma;
902 
903 	u8         reserved_at_1580[0x280];
904 
905 	struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_transmit_rdma;
906 
907 	u8         reserved_at_1880[0x780];
908 
909 	u8         sw_steering_nic_rx_action_drop_icm_address[0x40];
910 
911 	u8         sw_steering_nic_tx_action_drop_icm_address[0x40];
912 
913 	u8         sw_steering_nic_tx_action_allow_icm_address[0x40];
914 
915 	u8         reserved_at_20c0[0x5f40];
916 };
917 
918 struct mlx5_ifc_port_selection_cap_bits {
919 	u8         reserved_at_0[0x10];
920 	u8         port_select_flow_table[0x1];
921 	u8         reserved_at_11[0x1];
922 	u8         port_select_flow_table_bypass[0x1];
923 	u8         reserved_at_13[0xd];
924 
925 	u8         reserved_at_20[0x1e0];
926 
927 	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_port_selection;
928 
929 	struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_port_selection;
930 
931 	u8         reserved_at_480[0x7b80];
932 };
933 
934 enum {
935 	MLX5_FDB_TO_VPORT_REG_C_0 = 0x01,
936 	MLX5_FDB_TO_VPORT_REG_C_1 = 0x02,
937 	MLX5_FDB_TO_VPORT_REG_C_2 = 0x04,
938 	MLX5_FDB_TO_VPORT_REG_C_3 = 0x08,
939 	MLX5_FDB_TO_VPORT_REG_C_4 = 0x10,
940 	MLX5_FDB_TO_VPORT_REG_C_5 = 0x20,
941 	MLX5_FDB_TO_VPORT_REG_C_6 = 0x40,
942 	MLX5_FDB_TO_VPORT_REG_C_7 = 0x80,
943 };
944 
945 struct mlx5_ifc_flow_table_eswitch_cap_bits {
946 	u8      fdb_to_vport_reg_c_id[0x8];
947 	u8      reserved_at_8[0x5];
948 	u8      fdb_uplink_hairpin[0x1];
949 	u8      fdb_multi_path_any_table_limit_regc[0x1];
950 	u8      reserved_at_f[0x1];
951 	u8      fdb_dynamic_tunnel[0x1];
952 	u8      reserved_at_11[0x1];
953 	u8      fdb_multi_path_any_table[0x1];
954 	u8      reserved_at_13[0x2];
955 	u8      fdb_modify_header_fwd_to_table[0x1];
956 	u8      fdb_ipv4_ttl_modify[0x1];
957 	u8      flow_source[0x1];
958 	u8      reserved_at_18[0x2];
959 	u8      multi_fdb_encap[0x1];
960 	u8      egress_acl_forward_to_vport[0x1];
961 	u8      fdb_multi_path_to_table[0x1];
962 	u8      reserved_at_1d[0x3];
963 
964 	u8      reserved_at_20[0x1e0];
965 
966 	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb;
967 
968 	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress;
969 
970 	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress;
971 
972 	u8      reserved_at_800[0xC00];
973 
974 	struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_esw_fdb;
975 
976 	struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_bitmask_support_2_esw_fdb;
977 
978 	u8      reserved_at_1500[0x300];
979 
980 	u8      sw_steering_fdb_action_drop_icm_address_rx[0x40];
981 
982 	u8      sw_steering_fdb_action_drop_icm_address_tx[0x40];
983 
984 	u8      sw_steering_uplink_icm_address_rx[0x40];
985 
986 	u8      sw_steering_uplink_icm_address_tx[0x40];
987 
988 	u8      reserved_at_1900[0x6700];
989 };
990 
991 struct mlx5_ifc_wqe_based_flow_table_cap_bits {
992 	u8         reserved_at_0[0x3];
993 	u8         log_max_num_ste[0x5];
994 	u8         reserved_at_8[0x3];
995 	u8         log_max_num_stc[0x5];
996 	u8         reserved_at_10[0x3];
997 	u8         log_max_num_rtc[0x5];
998 	u8         reserved_at_18[0x3];
999 	u8         log_max_num_header_modify_pattern[0x5];
1000 
1001 	u8         rtc_hash_split_table[0x1];
1002 	u8         rtc_linear_lookup_table[0x1];
1003 	u8         reserved_at_22[0x1];
1004 	u8         stc_alloc_log_granularity[0x5];
1005 	u8         reserved_at_28[0x3];
1006 	u8         stc_alloc_log_max[0x5];
1007 	u8         reserved_at_30[0x3];
1008 	u8         ste_alloc_log_granularity[0x5];
1009 	u8         reserved_at_38[0x3];
1010 	u8         ste_alloc_log_max[0x5];
1011 
1012 	u8         reserved_at_40[0xb];
1013 	u8         rtc_reparse_mode[0x5];
1014 	u8         reserved_at_50[0x3];
1015 	u8         rtc_index_mode[0x5];
1016 	u8         reserved_at_58[0x3];
1017 	u8         rtc_log_depth_max[0x5];
1018 
1019 	u8         reserved_at_60[0x10];
1020 	u8         ste_format[0x10];
1021 
1022 	u8         stc_action_type[0x80];
1023 
1024 	u8         header_insert_type[0x10];
1025 	u8         header_remove_type[0x10];
1026 
1027 	u8         trivial_match_definer[0x20];
1028 
1029 	u8         reserved_at_140[0x1b];
1030 	u8         rtc_max_num_hash_definer_gen_wqe[0x5];
1031 
1032 	u8         reserved_at_160[0x18];
1033 	u8         access_index_mode[0x8];
1034 
1035 	u8         reserved_at_180[0x10];
1036 	u8         ste_format_gen_wqe[0x10];
1037 
1038 	u8         linear_match_definer_reg_c3[0x20];
1039 
1040 	u8         fdb_jump_to_tir_stc[0x1];
1041 	u8         reserved_at_1c1[0x1f];
1042 };
1043 
1044 struct mlx5_ifc_esw_cap_bits {
1045 	u8         reserved_at_0[0x1d];
1046 	u8         merged_eswitch[0x1];
1047 	u8         reserved_at_1e[0x2];
1048 
1049 	u8         reserved_at_20[0x40];
1050 
1051 	u8         esw_manager_vport_number_valid[0x1];
1052 	u8         reserved_at_61[0xf];
1053 	u8         esw_manager_vport_number[0x10];
1054 
1055 	u8         reserved_at_80[0x780];
1056 };
1057 
1058 enum {
1059 	MLX5_COUNTER_SOURCE_ESWITCH = 0x0,
1060 	MLX5_COUNTER_FLOW_ESWITCH   = 0x1,
1061 };
1062 
1063 struct mlx5_ifc_e_switch_cap_bits {
1064 	u8         vport_svlan_strip[0x1];
1065 	u8         vport_cvlan_strip[0x1];
1066 	u8         vport_svlan_insert[0x1];
1067 	u8         vport_cvlan_insert_if_not_exist[0x1];
1068 	u8         vport_cvlan_insert_overwrite[0x1];
1069 	u8         reserved_at_5[0x1];
1070 	u8         vport_cvlan_insert_always[0x1];
1071 	u8         esw_shared_ingress_acl[0x1];
1072 	u8         esw_uplink_ingress_acl[0x1];
1073 	u8         root_ft_on_other_esw[0x1];
1074 	u8         reserved_at_a[0xf];
1075 	u8         esw_functions_changed[0x1];
1076 	u8         reserved_at_1a[0x1];
1077 	u8         ecpf_vport_exists[0x1];
1078 	u8         counter_eswitch_affinity[0x1];
1079 	u8         merged_eswitch[0x1];
1080 	u8         nic_vport_node_guid_modify[0x1];
1081 	u8         nic_vport_port_guid_modify[0x1];
1082 
1083 	u8         vxlan_encap_decap[0x1];
1084 	u8         nvgre_encap_decap[0x1];
1085 	u8         reserved_at_22[0x1];
1086 	u8         log_max_fdb_encap_uplink[0x5];
1087 	u8         reserved_at_21[0x3];
1088 	u8         log_max_packet_reformat_context[0x5];
1089 	u8         reserved_2b[0x6];
1090 	u8         max_encap_header_size[0xa];
1091 
1092 	u8         reserved_at_40[0xb];
1093 	u8         log_max_esw_sf[0x5];
1094 	u8         esw_sf_base_id[0x10];
1095 
1096 	u8         reserved_at_60[0x7a0];
1097 
1098 };
1099 
1100 struct mlx5_ifc_qos_cap_bits {
1101 	u8         packet_pacing[0x1];
1102 	u8         esw_scheduling[0x1];
1103 	u8         esw_bw_share[0x1];
1104 	u8         esw_rate_limit[0x1];
1105 	u8         reserved_at_4[0x1];
1106 	u8         packet_pacing_burst_bound[0x1];
1107 	u8         packet_pacing_typical_size[0x1];
1108 	u8         reserved_at_7[0x1];
1109 	u8         nic_sq_scheduling[0x1];
1110 	u8         nic_bw_share[0x1];
1111 	u8         nic_rate_limit[0x1];
1112 	u8         packet_pacing_uid[0x1];
1113 	u8         log_esw_max_sched_depth[0x4];
1114 	u8         reserved_at_10[0x10];
1115 
1116 	u8         reserved_at_20[0x9];
1117 	u8         esw_cross_esw_sched[0x1];
1118 	u8         reserved_at_2a[0x1];
1119 	u8         log_max_qos_nic_queue_group[0x5];
1120 	u8         reserved_at_30[0x10];
1121 
1122 	u8         packet_pacing_max_rate[0x20];
1123 
1124 	u8         packet_pacing_min_rate[0x20];
1125 
1126 	u8         reserved_at_80[0xb];
1127 	u8         log_esw_max_rate_limit[0x5];
1128 	u8         packet_pacing_rate_table_size[0x10];
1129 
1130 	u8         esw_element_type[0x10];
1131 	u8         esw_tsar_type[0x10];
1132 
1133 	u8         reserved_at_c0[0x10];
1134 	u8         max_qos_para_vport[0x10];
1135 
1136 	u8         max_tsar_bw_share[0x20];
1137 
1138 	u8         nic_element_type[0x10];
1139 	u8         nic_tsar_type[0x10];
1140 
1141 	u8         reserved_at_120[0x3];
1142 	u8         log_meter_aso_granularity[0x5];
1143 	u8         reserved_at_128[0x3];
1144 	u8         log_meter_aso_max_alloc[0x5];
1145 	u8         reserved_at_130[0x3];
1146 	u8         log_max_num_meter_aso[0x5];
1147 	u8         reserved_at_138[0x8];
1148 
1149 	u8         reserved_at_140[0x6c0];
1150 };
1151 
1152 struct mlx5_ifc_debug_cap_bits {
1153 	u8         core_dump_general[0x1];
1154 	u8         core_dump_qp[0x1];
1155 	u8         reserved_at_2[0x7];
1156 	u8         resource_dump[0x1];
1157 	u8         reserved_at_a[0x16];
1158 
1159 	u8         reserved_at_20[0x2];
1160 	u8         stall_detect[0x1];
1161 	u8         reserved_at_23[0x1d];
1162 
1163 	u8         reserved_at_40[0x7c0];
1164 };
1165 
1166 struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
1167 	u8         csum_cap[0x1];
1168 	u8         vlan_cap[0x1];
1169 	u8         lro_cap[0x1];
1170 	u8         lro_psh_flag[0x1];
1171 	u8         lro_time_stamp[0x1];
1172 	u8         reserved_at_5[0x2];
1173 	u8         wqe_vlan_insert[0x1];
1174 	u8         self_lb_en_modifiable[0x1];
1175 	u8         reserved_at_9[0x2];
1176 	u8         max_lso_cap[0x5];
1177 	u8         multi_pkt_send_wqe[0x2];
1178 	u8	   wqe_inline_mode[0x2];
1179 	u8         rss_ind_tbl_cap[0x4];
1180 	u8         reg_umr_sq[0x1];
1181 	u8         scatter_fcs[0x1];
1182 	u8         enhanced_multi_pkt_send_wqe[0x1];
1183 	u8         tunnel_lso_const_out_ip_id[0x1];
1184 	u8         tunnel_lro_gre[0x1];
1185 	u8         tunnel_lro_vxlan[0x1];
1186 	u8         tunnel_stateless_gre[0x1];
1187 	u8         tunnel_stateless_vxlan[0x1];
1188 
1189 	u8         swp[0x1];
1190 	u8         swp_csum[0x1];
1191 	u8         swp_lso[0x1];
1192 	u8         cqe_checksum_full[0x1];
1193 	u8         tunnel_stateless_geneve_tx[0x1];
1194 	u8         tunnel_stateless_mpls_over_udp[0x1];
1195 	u8         tunnel_stateless_mpls_over_gre[0x1];
1196 	u8         tunnel_stateless_vxlan_gpe[0x1];
1197 	u8         tunnel_stateless_ipv4_over_vxlan[0x1];
1198 	u8         tunnel_stateless_ip_over_ip[0x1];
1199 	u8         insert_trailer[0x1];
1200 	u8         reserved_at_2b[0x1];
1201 	u8         tunnel_stateless_ip_over_ip_rx[0x1];
1202 	u8         tunnel_stateless_ip_over_ip_tx[0x1];
1203 	u8         reserved_at_2e[0x2];
1204 	u8         max_vxlan_udp_ports[0x8];
1205 	u8         swp_csum_l4_partial[0x1];
1206 	u8         reserved_at_39[0x5];
1207 	u8         max_geneve_opt_len[0x1];
1208 	u8         tunnel_stateless_geneve_rx[0x1];
1209 
1210 	u8         reserved_at_40[0x10];
1211 	u8         lro_min_mss_size[0x10];
1212 
1213 	u8         reserved_at_60[0x120];
1214 
1215 	u8         lro_timer_supported_periods[4][0x20];
1216 
1217 	u8         reserved_at_200[0x600];
1218 };
1219 
1220 enum {
1221 	MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING               = 0x0,
1222 	MLX5_TIMESTAMP_FORMAT_CAP_REAL_TIME                  = 0x1,
1223 	MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING_AND_REAL_TIME = 0x2,
1224 };
1225 
1226 struct mlx5_ifc_roce_cap_bits {
1227 	u8         roce_apm[0x1];
1228 	u8         reserved_at_1[0x3];
1229 	u8         sw_r_roce_src_udp_port[0x1];
1230 	u8         fl_rc_qp_when_roce_disabled[0x1];
1231 	u8         fl_rc_qp_when_roce_enabled[0x1];
1232 	u8         roce_cc_general[0x1];
1233 	u8	   qp_ooo_transmit_default[0x1];
1234 	u8         reserved_at_9[0x15];
1235 	u8	   qp_ts_format[0x2];
1236 
1237 	u8         reserved_at_20[0x60];
1238 
1239 	u8         reserved_at_80[0xc];
1240 	u8         l3_type[0x4];
1241 	u8         reserved_at_90[0x8];
1242 	u8         roce_version[0x8];
1243 
1244 	u8         reserved_at_a0[0x10];
1245 	u8         r_roce_dest_udp_port[0x10];
1246 
1247 	u8         r_roce_max_src_udp_port[0x10];
1248 	u8         r_roce_min_src_udp_port[0x10];
1249 
1250 	u8         reserved_at_e0[0x10];
1251 	u8         roce_address_table_size[0x10];
1252 
1253 	u8         reserved_at_100[0x700];
1254 };
1255 
1256 struct mlx5_ifc_sync_steering_in_bits {
1257 	u8         opcode[0x10];
1258 	u8         uid[0x10];
1259 
1260 	u8         reserved_at_20[0x10];
1261 	u8         op_mod[0x10];
1262 
1263 	u8         reserved_at_40[0xc0];
1264 };
1265 
1266 struct mlx5_ifc_sync_steering_out_bits {
1267 	u8         status[0x8];
1268 	u8         reserved_at_8[0x18];
1269 
1270 	u8         syndrome[0x20];
1271 
1272 	u8         reserved_at_40[0x40];
1273 };
1274 
1275 struct mlx5_ifc_sync_crypto_in_bits {
1276 	u8         opcode[0x10];
1277 	u8         uid[0x10];
1278 
1279 	u8         reserved_at_20[0x10];
1280 	u8         op_mod[0x10];
1281 
1282 	u8         reserved_at_40[0x20];
1283 
1284 	u8         reserved_at_60[0x10];
1285 	u8         crypto_type[0x10];
1286 
1287 	u8         reserved_at_80[0x80];
1288 };
1289 
1290 struct mlx5_ifc_sync_crypto_out_bits {
1291 	u8         status[0x8];
1292 	u8         reserved_at_8[0x18];
1293 
1294 	u8         syndrome[0x20];
1295 
1296 	u8         reserved_at_40[0x40];
1297 };
1298 
1299 struct mlx5_ifc_device_mem_cap_bits {
1300 	u8         memic[0x1];
1301 	u8         reserved_at_1[0x1f];
1302 
1303 	u8         reserved_at_20[0xb];
1304 	u8         log_min_memic_alloc_size[0x5];
1305 	u8         reserved_at_30[0x8];
1306 	u8	   log_max_memic_addr_alignment[0x8];
1307 
1308 	u8         memic_bar_start_addr[0x40];
1309 
1310 	u8         memic_bar_size[0x20];
1311 
1312 	u8         max_memic_size[0x20];
1313 
1314 	u8         steering_sw_icm_start_address[0x40];
1315 
1316 	u8         reserved_at_100[0x8];
1317 	u8         log_header_modify_sw_icm_size[0x8];
1318 	u8         reserved_at_110[0x2];
1319 	u8         log_sw_icm_alloc_granularity[0x6];
1320 	u8         log_steering_sw_icm_size[0x8];
1321 
1322 	u8         log_indirect_encap_sw_icm_size[0x8];
1323 	u8         reserved_at_128[0x10];
1324 	u8         log_header_modify_pattern_sw_icm_size[0x8];
1325 
1326 	u8         header_modify_sw_icm_start_address[0x40];
1327 
1328 	u8         reserved_at_180[0x40];
1329 
1330 	u8         header_modify_pattern_sw_icm_start_address[0x40];
1331 
1332 	u8         memic_operations[0x20];
1333 
1334 	u8         reserved_at_220[0x20];
1335 
1336 	u8         indirect_encap_sw_icm_start_address[0x40];
1337 
1338 	u8         reserved_at_280[0x580];
1339 };
1340 
1341 struct mlx5_ifc_device_event_cap_bits {
1342 	u8         user_affiliated_events[4][0x40];
1343 
1344 	u8         user_unaffiliated_events[4][0x40];
1345 };
1346 
1347 struct mlx5_ifc_virtio_emulation_cap_bits {
1348 	u8         desc_tunnel_offload_type[0x1];
1349 	u8         eth_frame_offload_type[0x1];
1350 	u8         virtio_version_1_0[0x1];
1351 	u8         device_features_bits_mask[0xd];
1352 	u8         event_mode[0x8];
1353 	u8         virtio_queue_type[0x8];
1354 
1355 	u8         max_tunnel_desc[0x10];
1356 	u8         reserved_at_30[0x3];
1357 	u8         log_doorbell_stride[0x5];
1358 	u8         reserved_at_38[0x3];
1359 	u8         log_doorbell_bar_size[0x5];
1360 
1361 	u8         doorbell_bar_offset[0x40];
1362 
1363 	u8         max_emulated_devices[0x8];
1364 	u8         max_num_virtio_queues[0x18];
1365 
1366 	u8         reserved_at_a0[0x20];
1367 
1368 	u8	   reserved_at_c0[0x13];
1369 	u8         desc_group_mkey_supported[0x1];
1370 	u8         freeze_to_rdy_supported[0x1];
1371 	u8         reserved_at_d5[0xb];
1372 
1373 	u8         reserved_at_e0[0x20];
1374 
1375 	u8         umem_1_buffer_param_a[0x20];
1376 
1377 	u8         umem_1_buffer_param_b[0x20];
1378 
1379 	u8         umem_2_buffer_param_a[0x20];
1380 
1381 	u8         umem_2_buffer_param_b[0x20];
1382 
1383 	u8         umem_3_buffer_param_a[0x20];
1384 
1385 	u8         umem_3_buffer_param_b[0x20];
1386 
1387 	u8         reserved_at_1c0[0x640];
1388 };
1389 
1390 enum {
1391 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE     = 0x0,
1392 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES    = 0x2,
1393 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES    = 0x4,
1394 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES    = 0x8,
1395 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES   = 0x10,
1396 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES   = 0x20,
1397 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES   = 0x40,
1398 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES  = 0x80,
1399 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES  = 0x100,
1400 };
1401 
1402 enum {
1403 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE     = 0x1,
1404 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES    = 0x2,
1405 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES    = 0x4,
1406 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES    = 0x8,
1407 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES   = 0x10,
1408 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES   = 0x20,
1409 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES   = 0x40,
1410 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES  = 0x80,
1411 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES  = 0x100,
1412 };
1413 
1414 struct mlx5_ifc_atomic_caps_bits {
1415 	u8         reserved_at_0[0x40];
1416 
1417 	u8         atomic_req_8B_endianness_mode[0x2];
1418 	u8         reserved_at_42[0x4];
1419 	u8         supported_atomic_req_8B_endianness_mode_1[0x1];
1420 
1421 	u8         reserved_at_47[0x19];
1422 
1423 	u8         reserved_at_60[0x20];
1424 
1425 	u8         reserved_at_80[0x10];
1426 	u8         atomic_operations[0x10];
1427 
1428 	u8         reserved_at_a0[0x10];
1429 	u8         atomic_size_qp[0x10];
1430 
1431 	u8         reserved_at_c0[0x10];
1432 	u8         atomic_size_dc[0x10];
1433 
1434 	u8         reserved_at_e0[0x720];
1435 };
1436 
1437 struct mlx5_ifc_odp_scheme_cap_bits {
1438 	u8         reserved_at_0[0x40];
1439 
1440 	u8         sig[0x1];
1441 	u8         reserved_at_41[0x4];
1442 	u8         page_prefetch[0x1];
1443 	u8         reserved_at_46[0x1a];
1444 
1445 	u8         reserved_at_60[0x20];
1446 
1447 	struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
1448 
1449 	struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
1450 
1451 	struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
1452 
1453 	struct mlx5_ifc_odp_per_transport_service_cap_bits xrc_odp_caps;
1454 
1455 	struct mlx5_ifc_odp_per_transport_service_cap_bits dc_odp_caps;
1456 
1457 	u8         reserved_at_120[0xe0];
1458 };
1459 
1460 struct mlx5_ifc_odp_cap_bits {
1461 	struct mlx5_ifc_odp_scheme_cap_bits transport_page_fault_scheme_cap;
1462 
1463 	struct mlx5_ifc_odp_scheme_cap_bits memory_page_fault_scheme_cap;
1464 
1465 	u8         reserved_at_400[0x200];
1466 
1467 	u8         mem_page_fault[0x1];
1468 	u8         reserved_at_601[0x1f];
1469 
1470 	u8         reserved_at_620[0x1e0];
1471 };
1472 
1473 struct mlx5_ifc_tls_cap_bits {
1474 	u8         tls_1_2_aes_gcm_128[0x1];
1475 	u8         tls_1_3_aes_gcm_128[0x1];
1476 	u8         tls_1_2_aes_gcm_256[0x1];
1477 	u8         tls_1_3_aes_gcm_256[0x1];
1478 	u8         reserved_at_4[0x1c];
1479 
1480 	u8         reserved_at_20[0x7e0];
1481 };
1482 
1483 struct mlx5_ifc_ipsec_cap_bits {
1484 	u8         ipsec_full_offload[0x1];
1485 	u8         ipsec_crypto_offload[0x1];
1486 	u8         ipsec_esn[0x1];
1487 	u8         ipsec_crypto_esp_aes_gcm_256_encrypt[0x1];
1488 	u8         ipsec_crypto_esp_aes_gcm_128_encrypt[0x1];
1489 	u8         ipsec_crypto_esp_aes_gcm_256_decrypt[0x1];
1490 	u8         ipsec_crypto_esp_aes_gcm_128_decrypt[0x1];
1491 	u8         reserved_at_7[0x4];
1492 	u8         log_max_ipsec_offload[0x5];
1493 	u8         reserved_at_10[0x10];
1494 
1495 	u8         min_log_ipsec_full_replay_window[0x8];
1496 	u8         max_log_ipsec_full_replay_window[0x8];
1497 	u8         reserved_at_30[0x7d0];
1498 };
1499 
1500 struct mlx5_ifc_macsec_cap_bits {
1501 	u8    macsec_epn[0x1];
1502 	u8    reserved_at_1[0x2];
1503 	u8    macsec_crypto_esp_aes_gcm_256_encrypt[0x1];
1504 	u8    macsec_crypto_esp_aes_gcm_128_encrypt[0x1];
1505 	u8    macsec_crypto_esp_aes_gcm_256_decrypt[0x1];
1506 	u8    macsec_crypto_esp_aes_gcm_128_decrypt[0x1];
1507 	u8    reserved_at_7[0x4];
1508 	u8    log_max_macsec_offload[0x5];
1509 	u8    reserved_at_10[0x10];
1510 
1511 	u8    min_log_macsec_full_replay_window[0x8];
1512 	u8    max_log_macsec_full_replay_window[0x8];
1513 	u8    reserved_at_30[0x10];
1514 
1515 	u8    reserved_at_40[0x7c0];
1516 };
1517 
1518 struct mlx5_ifc_psp_cap_bits {
1519 	u8         reserved_at_0[0x1];
1520 	u8         psp_crypto_offload[0x1];
1521 	u8         reserved_at_2[0x1];
1522 	u8         psp_crypto_esp_aes_gcm_256_encrypt[0x1];
1523 	u8         psp_crypto_esp_aes_gcm_128_encrypt[0x1];
1524 	u8         psp_crypto_esp_aes_gcm_256_decrypt[0x1];
1525 	u8         psp_crypto_esp_aes_gcm_128_decrypt[0x1];
1526 	u8         reserved_at_7[0x4];
1527 	u8         log_max_num_of_psp_spi[0x5];
1528 	u8         reserved_at_10[0x10];
1529 
1530 	u8         reserved_at_20[0x7e0];
1531 };
1532 
1533 enum {
1534 	MLX5_WQ_TYPE_LINKED_LIST  = 0x0,
1535 	MLX5_WQ_TYPE_CYCLIC       = 0x1,
1536 	MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2,
1537 	MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3,
1538 };
1539 
1540 enum {
1541 	MLX5_WQ_END_PAD_MODE_NONE   = 0x0,
1542 	MLX5_WQ_END_PAD_MODE_ALIGN  = 0x1,
1543 };
1544 
1545 enum {
1546 	MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES    = 0x0,
1547 	MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES   = 0x1,
1548 	MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES   = 0x2,
1549 	MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES   = 0x3,
1550 	MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES  = 0x4,
1551 };
1552 
1553 enum {
1554 	MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES  = 0x0,
1555 	MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES  = 0x1,
1556 	MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES  = 0x2,
1557 	MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES   = 0x3,
1558 	MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES   = 0x4,
1559 	MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES   = 0x5,
1560 };
1561 
1562 enum {
1563 	MLX5_CMD_HCA_CAP_PORT_TYPE_IB        = 0x0,
1564 	MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET  = 0x1,
1565 };
1566 
1567 enum {
1568 	MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED       = 0x0,
1569 	MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE  = 0x1,
1570 	MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED        = 0x3,
1571 };
1572 
1573 enum {
1574 	MLX5_CAP_PORT_TYPE_IB  = 0x0,
1575 	MLX5_CAP_PORT_TYPE_ETH = 0x1,
1576 };
1577 
1578 enum {
1579 	MLX5_CAP_UMR_FENCE_STRONG	= 0x0,
1580 	MLX5_CAP_UMR_FENCE_SMALL	= 0x1,
1581 	MLX5_CAP_UMR_FENCE_NONE		= 0x2,
1582 };
1583 
1584 enum {
1585 	MLX5_FLEX_IPV4_OVER_VXLAN_ENABLED	= 1 << 0,
1586 	MLX5_FLEX_IPV6_OVER_VXLAN_ENABLED	= 1 << 1,
1587 	MLX5_FLEX_IPV6_OVER_IP_ENABLED		= 1 << 2,
1588 	MLX5_FLEX_PARSER_GENEVE_ENABLED		= 1 << 3,
1589 	MLX5_FLEX_PARSER_MPLS_OVER_GRE_ENABLED	= 1 << 4,
1590 	MLX5_FLEX_PARSER_MPLS_OVER_UDP_ENABLED	= 1 << 5,
1591 	MLX5_FLEX_P_BIT_VXLAN_GPE_ENABLED	= 1 << 6,
1592 	MLX5_FLEX_PARSER_VXLAN_GPE_ENABLED	= 1 << 7,
1593 	MLX5_FLEX_PARSER_ICMP_V4_ENABLED	= 1 << 8,
1594 	MLX5_FLEX_PARSER_ICMP_V6_ENABLED	= 1 << 9,
1595 	MLX5_FLEX_PARSER_GENEVE_TLV_OPTION_0_ENABLED = 1 << 10,
1596 	MLX5_FLEX_PARSER_GTPU_ENABLED		= 1 << 11,
1597 	MLX5_FLEX_PARSER_GTPU_DW_2_ENABLED	= 1 << 16,
1598 	MLX5_FLEX_PARSER_GTPU_FIRST_EXT_DW_0_ENABLED = 1 << 17,
1599 	MLX5_FLEX_PARSER_GTPU_DW_0_ENABLED	= 1 << 18,
1600 	MLX5_FLEX_PARSER_GTPU_TEID_ENABLED	= 1 << 19,
1601 };
1602 
1603 enum {
1604 	MLX5_UCTX_CAP_RAW_TX = 1UL << 0,
1605 	MLX5_UCTX_CAP_INTERNAL_DEV_RES = 1UL << 1,
1606 	MLX5_UCTX_CAP_RDMA_CTRL = 1UL << 3,
1607 	MLX5_UCTX_CAP_RDMA_CTRL_OTHER_VHCA = 1UL << 4,
1608 };
1609 
1610 #define MLX5_FC_BULK_SIZE_FACTOR 128
1611 
1612 enum mlx5_fc_bulk_alloc_bitmask {
1613 	MLX5_FC_BULK_128   = (1 << 0),
1614 	MLX5_FC_BULK_256   = (1 << 1),
1615 	MLX5_FC_BULK_512   = (1 << 2),
1616 	MLX5_FC_BULK_1024  = (1 << 3),
1617 	MLX5_FC_BULK_2048  = (1 << 4),
1618 	MLX5_FC_BULK_4096  = (1 << 5),
1619 	MLX5_FC_BULK_8192  = (1 << 6),
1620 	MLX5_FC_BULK_16384 = (1 << 7),
1621 };
1622 
1623 #define MLX5_FC_BULK_NUM_FCS(fc_enum) (MLX5_FC_BULK_SIZE_FACTOR * (fc_enum))
1624 
1625 #define MLX5_FT_MAX_MULTIPATH_LEVEL 63
1626 
1627 enum {
1628 	MLX5_STEERING_FORMAT_CONNECTX_5   = 0,
1629 	MLX5_STEERING_FORMAT_CONNECTX_6DX = 1,
1630 	MLX5_STEERING_FORMAT_CONNECTX_7   = 2,
1631 	MLX5_STEERING_FORMAT_CONNECTX_8   = 3,
1632 };
1633 
1634 struct mlx5_ifc_cmd_hca_cap_bits {
1635 	u8         reserved_at_0[0x6];
1636 	u8         page_request_disable[0x1];
1637 	u8         abs_native_port_num[0x1];
1638 	u8         reserved_at_8[0x8];
1639 	u8         shared_object_to_user_object_allowed[0x1];
1640 	u8         reserved_at_13[0xe];
1641 	u8         vhca_resource_manager[0x1];
1642 
1643 	u8         hca_cap_2[0x1];
1644 	u8         create_lag_when_not_master_up[0x1];
1645 	u8         dtor[0x1];
1646 	u8         event_on_vhca_state_teardown_request[0x1];
1647 	u8         event_on_vhca_state_in_use[0x1];
1648 	u8         event_on_vhca_state_active[0x1];
1649 	u8         event_on_vhca_state_allocated[0x1];
1650 	u8         event_on_vhca_state_invalid[0x1];
1651 	u8         reserved_at_28[0x8];
1652 	u8         vhca_id[0x10];
1653 
1654 	u8         reserved_at_40[0x40];
1655 
1656 	u8         log_max_srq_sz[0x8];
1657 	u8         log_max_qp_sz[0x8];
1658 	u8         event_cap[0x1];
1659 	u8         reserved_at_91[0x2];
1660 	u8         isolate_vl_tc_new[0x1];
1661 	u8         reserved_at_94[0x4];
1662 	u8         prio_tag_required[0x1];
1663 	u8         reserved_at_99[0x2];
1664 	u8         log_max_qp[0x5];
1665 
1666 	u8         reserved_at_a0[0x3];
1667 	u8	   ece_support[0x1];
1668 	u8	   reserved_at_a4[0x5];
1669 	u8         reg_c_preserve[0x1];
1670 	u8         reserved_at_aa[0x1];
1671 	u8         log_max_srq[0x5];
1672 	u8         reserved_at_b0[0x1];
1673 	u8         uplink_follow[0x1];
1674 	u8         ts_cqe_to_dest_cqn[0x1];
1675 	u8         reserved_at_b3[0x6];
1676 	u8         go_back_n[0x1];
1677 	u8         reserved_at_ba[0x6];
1678 
1679 	u8         max_sgl_for_optimized_performance[0x8];
1680 	u8         log_max_cq_sz[0x8];
1681 	u8         relaxed_ordering_write_umr[0x1];
1682 	u8         relaxed_ordering_read_umr[0x1];
1683 	u8         reserved_at_d2[0x7];
1684 	u8         virtio_net_device_emualtion_manager[0x1];
1685 	u8         virtio_blk_device_emualtion_manager[0x1];
1686 	u8         log_max_cq[0x5];
1687 
1688 	u8         log_max_eq_sz[0x8];
1689 	u8         relaxed_ordering_write[0x1];
1690 	u8         relaxed_ordering_read_pci_enabled[0x1];
1691 	u8         log_max_mkey[0x6];
1692 	u8         reserved_at_f0[0x6];
1693 	u8	   terminate_scatter_list_mkey[0x1];
1694 	u8	   repeated_mkey[0x1];
1695 	u8         dump_fill_mkey[0x1];
1696 	u8         reserved_at_f9[0x2];
1697 	u8         fast_teardown[0x1];
1698 	u8         log_max_eq[0x4];
1699 
1700 	u8         max_indirection[0x8];
1701 	u8         fixed_buffer_size[0x1];
1702 	u8         log_max_mrw_sz[0x7];
1703 	u8         force_teardown[0x1];
1704 	u8         reserved_at_111[0x1];
1705 	u8         log_max_bsf_list_size[0x6];
1706 	u8         umr_extended_translation_offset[0x1];
1707 	u8         null_mkey[0x1];
1708 	u8         log_max_klm_list_size[0x6];
1709 
1710 	u8         reserved_at_120[0x2];
1711 	u8	   qpc_extension[0x1];
1712 	u8	   reserved_at_123[0x7];
1713 	u8         log_max_ra_req_dc[0x6];
1714 	u8         reserved_at_130[0x2];
1715 	u8         eth_wqe_too_small[0x1];
1716 	u8         reserved_at_133[0x6];
1717 	u8         vnic_env_cq_overrun[0x1];
1718 	u8         log_max_ra_res_dc[0x6];
1719 
1720 	u8         reserved_at_140[0x5];
1721 	u8         release_all_pages[0x1];
1722 	u8         must_not_use[0x1];
1723 	u8         reserved_at_147[0x2];
1724 	u8         roce_accl[0x1];
1725 	u8         log_max_ra_req_qp[0x6];
1726 	u8         reserved_at_150[0xa];
1727 	u8         log_max_ra_res_qp[0x6];
1728 
1729 	u8         end_pad[0x1];
1730 	u8         cc_query_allowed[0x1];
1731 	u8         cc_modify_allowed[0x1];
1732 	u8         start_pad[0x1];
1733 	u8         cache_line_128byte[0x1];
1734 	u8         reserved_at_165[0x4];
1735 	u8         rts2rts_qp_counters_set_id[0x1];
1736 	u8         reserved_at_16a[0x2];
1737 	u8         vnic_env_int_rq_oob[0x1];
1738 	u8         sbcam_reg[0x1];
1739 	u8         reserved_at_16e[0x1];
1740 	u8         qcam_reg[0x1];
1741 	u8         gid_table_size[0x10];
1742 
1743 	u8         out_of_seq_cnt[0x1];
1744 	u8         vport_counters[0x1];
1745 	u8         retransmission_q_counters[0x1];
1746 	u8         debug[0x1];
1747 	u8         modify_rq_counter_set_id[0x1];
1748 	u8         rq_delay_drop[0x1];
1749 	u8         max_qp_cnt[0xa];
1750 	u8         pkey_table_size[0x10];
1751 
1752 	u8         vport_group_manager[0x1];
1753 	u8         vhca_group_manager[0x1];
1754 	u8         ib_virt[0x1];
1755 	u8         eth_virt[0x1];
1756 	u8         vnic_env_queue_counters[0x1];
1757 	u8         ets[0x1];
1758 	u8         nic_flow_table[0x1];
1759 	u8         eswitch_manager[0x1];
1760 	u8         device_memory[0x1];
1761 	u8         mcam_reg[0x1];
1762 	u8         pcam_reg[0x1];
1763 	u8         local_ca_ack_delay[0x5];
1764 	u8         port_module_event[0x1];
1765 	u8         enhanced_error_q_counters[0x1];
1766 	u8         ports_check[0x1];
1767 	u8         reserved_at_1b3[0x1];
1768 	u8         disable_link_up[0x1];
1769 	u8         beacon_led[0x1];
1770 	u8         port_type[0x2];
1771 	u8         num_ports[0x8];
1772 
1773 	u8         reserved_at_1c0[0x1];
1774 	u8         pps[0x1];
1775 	u8         pps_modify[0x1];
1776 	u8         log_max_msg[0x5];
1777 	u8         reserved_at_1c8[0x4];
1778 	u8         max_tc[0x4];
1779 	u8         temp_warn_event[0x1];
1780 	u8         dcbx[0x1];
1781 	u8         general_notification_event[0x1];
1782 	u8         reserved_at_1d3[0x2];
1783 	u8         fpga[0x1];
1784 	u8         rol_s[0x1];
1785 	u8         rol_g[0x1];
1786 	u8         reserved_at_1d8[0x1];
1787 	u8         wol_s[0x1];
1788 	u8         wol_g[0x1];
1789 	u8         wol_a[0x1];
1790 	u8         wol_b[0x1];
1791 	u8         wol_m[0x1];
1792 	u8         wol_u[0x1];
1793 	u8         wol_p[0x1];
1794 
1795 	u8         stat_rate_support[0x10];
1796 	u8         reserved_at_1f0[0x1];
1797 	u8         pci_sync_for_fw_update_event[0x1];
1798 	u8         reserved_at_1f2[0x6];
1799 	u8         init2_lag_tx_port_affinity[0x1];
1800 	u8         reserved_at_1fa[0x2];
1801 	u8         wqe_based_flow_table_update_cap[0x1];
1802 	u8         cqe_version[0x4];
1803 
1804 	u8         compact_address_vector[0x1];
1805 	u8         striding_rq[0x1];
1806 	u8         reserved_at_202[0x1];
1807 	u8         ipoib_enhanced_offloads[0x1];
1808 	u8         ipoib_basic_offloads[0x1];
1809 	u8         reserved_at_205[0x1];
1810 	u8         repeated_block_disabled[0x1];
1811 	u8         umr_modify_entity_size_disabled[0x1];
1812 	u8         umr_modify_atomic_disabled[0x1];
1813 	u8         umr_indirect_mkey_disabled[0x1];
1814 	u8         umr_fence[0x2];
1815 	u8         dc_req_scat_data_cqe[0x1];
1816 	u8         reserved_at_20d[0x2];
1817 	u8         drain_sigerr[0x1];
1818 	u8         cmdif_checksum[0x2];
1819 	u8         sigerr_cqe[0x1];
1820 	u8         reserved_at_213[0x1];
1821 	u8         wq_signature[0x1];
1822 	u8         sctr_data_cqe[0x1];
1823 	u8         reserved_at_216[0x1];
1824 	u8         sho[0x1];
1825 	u8         tph[0x1];
1826 	u8         rf[0x1];
1827 	u8         dct[0x1];
1828 	u8         qos[0x1];
1829 	u8         eth_net_offloads[0x1];
1830 	u8         roce[0x1];
1831 	u8         atomic[0x1];
1832 	u8         reserved_at_21f[0x1];
1833 
1834 	u8         cq_oi[0x1];
1835 	u8         cq_resize[0x1];
1836 	u8         cq_moderation[0x1];
1837 	u8         cq_period_mode_modify[0x1];
1838 	u8         reserved_at_224[0x2];
1839 	u8         cq_eq_remap[0x1];
1840 	u8         pg[0x1];
1841 	u8         block_lb_mc[0x1];
1842 	u8         reserved_at_229[0x1];
1843 	u8         scqe_break_moderation[0x1];
1844 	u8         cq_period_start_from_cqe[0x1];
1845 	u8         cd[0x1];
1846 	u8         reserved_at_22d[0x1];
1847 	u8         apm[0x1];
1848 	u8         vector_calc[0x1];
1849 	u8         umr_ptr_rlky[0x1];
1850 	u8	   imaicl[0x1];
1851 	u8	   qp_packet_based[0x1];
1852 	u8         reserved_at_233[0x3];
1853 	u8         qkv[0x1];
1854 	u8         pkv[0x1];
1855 	u8         set_deth_sqpn[0x1];
1856 	u8         reserved_at_239[0x3];
1857 	u8         xrc[0x1];
1858 	u8         ud[0x1];
1859 	u8         uc[0x1];
1860 	u8         rc[0x1];
1861 
1862 	u8         uar_4k[0x1];
1863 	u8         reserved_at_241[0x7];
1864 	u8         fl_rc_qp_when_roce_disabled[0x1];
1865 	u8         regexp_params[0x1];
1866 	u8         uar_sz[0x6];
1867 	u8         port_selection_cap[0x1];
1868 	u8         nic_cap_reg[0x1];
1869 	u8         umem_uid_0[0x1];
1870 	u8         reserved_at_253[0x5];
1871 	u8         log_pg_sz[0x8];
1872 
1873 	u8         bf[0x1];
1874 	u8         driver_version[0x1];
1875 	u8         pad_tx_eth_packet[0x1];
1876 	u8         reserved_at_263[0x3];
1877 	u8         mkey_by_name[0x1];
1878 	u8         reserved_at_267[0x4];
1879 
1880 	u8         log_bf_reg_size[0x5];
1881 
1882 	u8         disciplined_fr_counter[0x1];
1883 	u8         reserved_at_271[0x2];
1884 	u8	   qp_error_syndrome[0x1];
1885 	u8	   reserved_at_274[0x2];
1886 	u8         lag_dct[0x2];
1887 	u8         lag_tx_port_affinity[0x1];
1888 	u8         lag_native_fdb_selection[0x1];
1889 	u8         reserved_at_27a[0x1];
1890 	u8         lag_master[0x1];
1891 	u8         num_lag_ports[0x4];
1892 
1893 	u8         reserved_at_280[0x10];
1894 	u8         max_wqe_sz_sq[0x10];
1895 
1896 	u8         reserved_at_2a0[0x7];
1897 	u8         mkey_pcie_tph[0x1];
1898 	u8         reserved_at_2a8[0x2];
1899 
1900 	u8         psp[0x1];
1901 	u8         shampo[0x1];
1902 	u8         reserved_at_2ac[0x4];
1903 	u8         max_wqe_sz_rq[0x10];
1904 
1905 	u8         max_flow_counter_31_16[0x10];
1906 	u8         max_wqe_sz_sq_dc[0x10];
1907 
1908 	u8         reserved_at_2e0[0x7];
1909 	u8         max_qp_mcg[0x19];
1910 
1911 	u8         reserved_at_300[0x10];
1912 	u8         flow_counter_bulk_alloc[0x8];
1913 	u8         log_max_mcg[0x8];
1914 
1915 	u8         reserved_at_320[0x3];
1916 	u8         log_max_transport_domain[0x5];
1917 	u8         reserved_at_328[0x2];
1918 	u8	   relaxed_ordering_read[0x1];
1919 	u8         log_max_pd[0x5];
1920 	u8         dp_ordering_ooo_all_ud[0x1];
1921 	u8         dp_ordering_ooo_all_uc[0x1];
1922 	u8         dp_ordering_ooo_all_xrc[0x1];
1923 	u8         dp_ordering_ooo_all_dc[0x1];
1924 	u8         dp_ordering_ooo_all_rc[0x1];
1925 	u8         pcie_reset_using_hotreset_method[0x1];
1926 	u8         pci_sync_for_fw_update_with_driver_unload[0x1];
1927 	u8         vnic_env_cnt_steering_fail[0x1];
1928 	u8         vport_counter_local_loopback[0x1];
1929 	u8         q_counter_aggregation[0x1];
1930 	u8         q_counter_other_vport[0x1];
1931 	u8         log_max_xrcd[0x5];
1932 
1933 	u8         nic_receive_steering_discard[0x1];
1934 	u8         receive_discard_vport_down[0x1];
1935 	u8         transmit_discard_vport_down[0x1];
1936 	u8         eq_overrun_count[0x1];
1937 	u8         reserved_at_344[0x1];
1938 	u8         invalid_command_count[0x1];
1939 	u8         quota_exceeded_count[0x1];
1940 	u8         reserved_at_347[0x1];
1941 	u8         log_max_flow_counter_bulk[0x8];
1942 	u8         max_flow_counter_15_0[0x10];
1943 
1944 
1945 	u8         reserved_at_360[0x3];
1946 	u8         log_max_rq[0x5];
1947 	u8         reserved_at_368[0x3];
1948 	u8         log_max_sq[0x5];
1949 	u8         reserved_at_370[0x3];
1950 	u8         log_max_tir[0x5];
1951 	u8         reserved_at_378[0x3];
1952 	u8         log_max_tis[0x5];
1953 
1954 	u8         basic_cyclic_rcv_wqe[0x1];
1955 	u8         reserved_at_381[0x2];
1956 	u8         log_max_rmp[0x5];
1957 	u8         reserved_at_388[0x3];
1958 	u8         log_max_rqt[0x5];
1959 	u8         reserved_at_390[0x3];
1960 	u8         log_max_rqt_size[0x5];
1961 	u8         reserved_at_398[0x1];
1962 	u8	   vnic_env_cnt_bar_uar_access[0x1];
1963 	u8	   vnic_env_cnt_odp_page_fault[0x1];
1964 	u8         log_max_tis_per_sq[0x5];
1965 
1966 	u8         ext_stride_num_range[0x1];
1967 	u8         roce_rw_supported[0x1];
1968 	u8         log_max_current_uc_list_wr_supported[0x1];
1969 	u8         log_max_stride_sz_rq[0x5];
1970 	u8         reserved_at_3a8[0x3];
1971 	u8         log_min_stride_sz_rq[0x5];
1972 	u8         reserved_at_3b0[0x3];
1973 	u8         log_max_stride_sz_sq[0x5];
1974 	u8         reserved_at_3b8[0x3];
1975 	u8         log_min_stride_sz_sq[0x5];
1976 
1977 	u8         hairpin[0x1];
1978 	u8         reserved_at_3c1[0x2];
1979 	u8         log_max_hairpin_queues[0x5];
1980 	u8         reserved_at_3c8[0x3];
1981 	u8         log_max_hairpin_wq_data_sz[0x5];
1982 	u8         reserved_at_3d0[0x3];
1983 	u8         log_max_hairpin_num_packets[0x5];
1984 	u8         reserved_at_3d8[0x3];
1985 	u8         log_max_wq_sz[0x5];
1986 
1987 	u8         nic_vport_change_event[0x1];
1988 	u8         disable_local_lb_uc[0x1];
1989 	u8         disable_local_lb_mc[0x1];
1990 	u8         log_min_hairpin_wq_data_sz[0x5];
1991 	u8         reserved_at_3e8[0x1];
1992 	u8         silent_mode[0x1];
1993 	u8         vhca_state[0x1];
1994 	u8         log_max_vlan_list[0x5];
1995 	u8         reserved_at_3f0[0x3];
1996 	u8         log_max_current_mc_list[0x5];
1997 	u8         reserved_at_3f8[0x3];
1998 	u8         log_max_current_uc_list[0x5];
1999 
2000 	u8         general_obj_types[0x40];
2001 
2002 	u8         sq_ts_format[0x2];
2003 	u8         rq_ts_format[0x2];
2004 	u8         steering_format_version[0x4];
2005 	u8         create_qp_start_hint[0x18];
2006 
2007 	u8         reserved_at_460[0x1];
2008 	u8         ats[0x1];
2009 	u8         cross_vhca_rqt[0x1];
2010 	u8         log_max_uctx[0x5];
2011 	u8         reserved_at_468[0x1];
2012 	u8         crypto[0x1];
2013 	u8         ipsec_offload[0x1];
2014 	u8         log_max_umem[0x5];
2015 	u8         max_num_eqs[0x10];
2016 
2017 	u8         reserved_at_480[0x1];
2018 	u8         tls_tx[0x1];
2019 	u8         tls_rx[0x1];
2020 	u8         log_max_l2_table[0x5];
2021 	u8         reserved_at_488[0x8];
2022 	u8         log_uar_page_sz[0x10];
2023 
2024 	u8         reserved_at_4a0[0x20];
2025 	u8         device_frequency_mhz[0x20];
2026 	u8         device_frequency_khz[0x20];
2027 
2028 	u8         reserved_at_500[0x20];
2029 	u8	   num_of_uars_per_page[0x20];
2030 
2031 	u8         flex_parser_protocols[0x20];
2032 
2033 	u8         max_geneve_tlv_options[0x8];
2034 	u8         reserved_at_568[0x3];
2035 	u8         max_geneve_tlv_option_data_len[0x5];
2036 	u8         reserved_at_570[0x1];
2037 	u8         adv_rdma[0x1];
2038 	u8         reserved_at_572[0x7];
2039 	u8         adv_virtualization[0x1];
2040 	u8         reserved_at_57a[0x6];
2041 
2042 	u8	   reserved_at_580[0xb];
2043 	u8	   log_max_dci_stream_channels[0x5];
2044 	u8	   reserved_at_590[0x3];
2045 	u8	   log_max_dci_errored_streams[0x5];
2046 	u8	   reserved_at_598[0x8];
2047 
2048 	u8         reserved_at_5a0[0x10];
2049 	u8         enhanced_cqe_compression[0x1];
2050 	u8         reserved_at_5b1[0x1];
2051 	u8         crossing_vhca_mkey[0x1];
2052 	u8         log_max_dek[0x5];
2053 	u8         reserved_at_5b8[0x4];
2054 	u8         mini_cqe_resp_stride_index[0x1];
2055 	u8         cqe_128_always[0x1];
2056 	u8         cqe_compression_128[0x1];
2057 	u8         cqe_compression[0x1];
2058 
2059 	u8         cqe_compression_timeout[0x10];
2060 	u8         cqe_compression_max_num[0x10];
2061 
2062 	u8         reserved_at_5e0[0x8];
2063 	u8         flex_parser_id_gtpu_dw_0[0x4];
2064 	u8         reserved_at_5ec[0x4];
2065 	u8         tag_matching[0x1];
2066 	u8         rndv_offload_rc[0x1];
2067 	u8         rndv_offload_dc[0x1];
2068 	u8         log_tag_matching_list_sz[0x5];
2069 	u8         reserved_at_5f8[0x3];
2070 	u8         log_max_xrq[0x5];
2071 
2072 	u8	   affiliate_nic_vport_criteria[0x8];
2073 	u8	   native_port_num[0x8];
2074 	u8	   num_vhca_ports[0x8];
2075 	u8         flex_parser_id_gtpu_teid[0x4];
2076 	u8         reserved_at_61c[0x2];
2077 	u8	   sw_owner_id[0x1];
2078 	u8         reserved_at_61f[0x1];
2079 
2080 	u8         max_num_of_monitor_counters[0x10];
2081 	u8         num_ppcnt_monitor_counters[0x10];
2082 
2083 	u8         max_num_sf[0x10];
2084 	u8         num_q_monitor_counters[0x10];
2085 
2086 	u8         reserved_at_660[0x20];
2087 
2088 	u8         sf[0x1];
2089 	u8         sf_set_partition[0x1];
2090 	u8         reserved_at_682[0x1];
2091 	u8         log_max_sf[0x5];
2092 	u8         apu[0x1];
2093 	u8         reserved_at_689[0x4];
2094 	u8         migration[0x1];
2095 	u8         reserved_at_68e[0x2];
2096 	u8         log_min_sf_size[0x8];
2097 	u8         max_num_sf_partitions[0x8];
2098 
2099 	u8         uctx_cap[0x20];
2100 
2101 	u8         reserved_at_6c0[0x4];
2102 	u8         flex_parser_id_geneve_tlv_option_0[0x4];
2103 	u8         flex_parser_id_icmp_dw1[0x4];
2104 	u8         flex_parser_id_icmp_dw0[0x4];
2105 	u8         flex_parser_id_icmpv6_dw1[0x4];
2106 	u8         flex_parser_id_icmpv6_dw0[0x4];
2107 	u8         flex_parser_id_outer_first_mpls_over_gre[0x4];
2108 	u8         flex_parser_id_outer_first_mpls_over_udp_label[0x4];
2109 
2110 	u8         max_num_match_definer[0x10];
2111 	u8	   sf_base_id[0x10];
2112 
2113 	u8         flex_parser_id_gtpu_dw_2[0x4];
2114 	u8         flex_parser_id_gtpu_first_ext_dw_0[0x4];
2115 	u8	   num_total_dynamic_vf_msix[0x18];
2116 	u8	   reserved_at_720[0x14];
2117 	u8	   dynamic_msix_table_size[0xc];
2118 	u8	   reserved_at_740[0xc];
2119 	u8	   min_dynamic_vf_msix_table_size[0x4];
2120 	u8	   reserved_at_750[0x2];
2121 	u8	   data_direct[0x1];
2122 	u8	   reserved_at_753[0x1];
2123 	u8	   max_dynamic_vf_msix_table_size[0xc];
2124 
2125 	u8         reserved_at_760[0x3];
2126 	u8         log_max_num_header_modify_argument[0x5];
2127 	u8         log_header_modify_argument_granularity_offset[0x4];
2128 	u8         log_header_modify_argument_granularity[0x4];
2129 	u8         reserved_at_770[0x3];
2130 	u8         log_header_modify_argument_max_alloc[0x5];
2131 	u8         reserved_at_778[0x8];
2132 
2133 	u8	   vhca_tunnel_commands[0x40];
2134 	u8         match_definer_format_supported[0x40];
2135 };
2136 
2137 enum {
2138 	MLX5_CROSS_VHCA_OBJ_TO_OBJ_SUPPORTED_LOCAL_FLOW_TABLE_TO_REMOTE_FLOW_TABLE_MISS  = 0x80000,
2139 	MLX5_CROSS_VHCA_OBJ_TO_OBJ_SUPPORTED_LOCAL_FLOW_TABLE_ROOT_TO_REMOTE_FLOW_TABLE  = (1ULL << 20),
2140 };
2141 
2142 enum {
2143 	MLX5_ALLOWED_OBJ_FOR_OTHER_VHCA_ACCESS_FLOW_TABLE       = 0x200,
2144 };
2145 
2146 struct mlx5_ifc_cmd_hca_cap_2_bits {
2147 	u8	   reserved_at_0[0x80];
2148 
2149 	u8         migratable[0x1];
2150 	u8         reserved_at_81[0x7];
2151 	u8         dp_ordering_force[0x1];
2152 	u8         reserved_at_89[0x9];
2153 	u8         query_vuid[0x1];
2154 	u8         reserved_at_93[0x5];
2155 	u8         umr_log_entity_size_5[0x1];
2156 	u8         reserved_at_99[0x7];
2157 
2158 	u8	   max_reformat_insert_size[0x8];
2159 	u8	   max_reformat_insert_offset[0x8];
2160 	u8	   max_reformat_remove_size[0x8];
2161 	u8	   max_reformat_remove_offset[0x8];
2162 
2163 	u8	   reserved_at_c0[0x8];
2164 	u8	   migration_multi_load[0x1];
2165 	u8	   migration_tracking_state[0x1];
2166 	u8	   multiplane_qp_ud[0x1];
2167 	u8	   reserved_at_cb[0x5];
2168 	u8	   migration_in_chunks[0x1];
2169 	u8	   reserved_at_d1[0x1];
2170 	u8	   sf_eq_usage[0x1];
2171 	u8	   reserved_at_d3[0x5];
2172 	u8	   multiplane[0x1];
2173 	u8	   reserved_at_d9[0x7];
2174 
2175 	u8	   cross_vhca_object_to_object_supported[0x20];
2176 
2177 	u8	   allowed_object_for_other_vhca_access[0x40];
2178 
2179 	u8	   reserved_at_140[0x60];
2180 
2181 	u8	   flow_table_type_2_type[0x8];
2182 	u8	   reserved_at_1a8[0x2];
2183 	u8         format_select_dw_8_6_ext[0x1];
2184 	u8	   log_min_mkey_entity_size[0x5];
2185 	u8	   reserved_at_1b0[0x10];
2186 
2187 	u8	   general_obj_types_127_64[0x40];
2188 	u8	   reserved_at_200[0x20];
2189 
2190 	u8	   reserved_at_220[0x1];
2191 	u8	   sw_vhca_id_valid[0x1];
2192 	u8	   sw_vhca_id[0xe];
2193 	u8	   reserved_at_230[0x10];
2194 
2195 	u8	   reserved_at_240[0xb];
2196 	u8	   ts_cqe_metadata_size2wqe_counter[0x5];
2197 	u8	   reserved_at_250[0x10];
2198 
2199 	u8	   reserved_at_260[0x20];
2200 
2201 	u8	   format_select_dw_gtpu_dw_0[0x8];
2202 	u8	   format_select_dw_gtpu_dw_1[0x8];
2203 	u8	   format_select_dw_gtpu_dw_2[0x8];
2204 	u8	   format_select_dw_gtpu_first_ext_dw_0[0x8];
2205 
2206 	u8	   generate_wqe_type[0x20];
2207 
2208 	u8	   reserved_at_2c0[0xc0];
2209 
2210 	u8	   reserved_at_380[0xb];
2211 	u8	   min_mkey_log_entity_size_fixed_buffer[0x5];
2212 	u8	   ec_vf_vport_base[0x10];
2213 
2214 	u8	   reserved_at_3a0[0x2];
2215 	u8	   max_mkey_log_entity_size_fixed_buffer[0x6];
2216 	u8	   reserved_at_3a8[0x2];
2217 	u8	   max_mkey_log_entity_size_mtt[0x6];
2218 	u8	   max_rqt_vhca_id[0x10];
2219 
2220 	u8	   reserved_at_3c0[0x20];
2221 
2222 	u8	   reserved_at_3e0[0x10];
2223 	u8	   pcc_ifa2[0x1];
2224 	u8	   reserved_at_3f1[0xf];
2225 
2226 	u8	   reserved_at_400[0x1];
2227 	u8	   min_mkey_log_entity_size_fixed_buffer_valid[0x1];
2228 	u8	   reserved_at_402[0xe];
2229 	u8	   return_reg_id[0x10];
2230 
2231 	u8	   reserved_at_420[0x1c];
2232 	u8	   flow_table_hash_type[0x4];
2233 
2234 	u8	   reserved_at_440[0x8];
2235 	u8	   max_num_eqs_24b[0x18];
2236 
2237 	u8         reserved_at_460[0x160];
2238 
2239 	u8         query_adjacent_functions_id[0x1];
2240 	u8         ingress_egress_esw_vport_connect[0x1];
2241 	u8         function_id_type_vhca_id[0x1];
2242 	u8         reserved_at_5c3[0xd];
2243 	u8         delegate_vhca_management_profiles[0x10];
2244 
2245 	u8         delegated_vhca_max[0x10];
2246 	u8         delegate_vhca_max[0x10];
2247 
2248 	u8         reserved_at_600[0x200];
2249 };
2250 
2251 enum mlx5_ifc_flow_destination_type {
2252 	MLX5_IFC_FLOW_DESTINATION_TYPE_VPORT        = 0x0,
2253 	MLX5_IFC_FLOW_DESTINATION_TYPE_FLOW_TABLE   = 0x1,
2254 	MLX5_IFC_FLOW_DESTINATION_TYPE_TIR          = 0x2,
2255 	MLX5_IFC_FLOW_DESTINATION_TYPE_FLOW_SAMPLER = 0x6,
2256 	MLX5_IFC_FLOW_DESTINATION_TYPE_UPLINK       = 0x8,
2257 	MLX5_IFC_FLOW_DESTINATION_TYPE_TABLE_TYPE   = 0xA,
2258 };
2259 
2260 enum mlx5_flow_table_miss_action {
2261 	MLX5_FLOW_TABLE_MISS_ACTION_DEF,
2262 	MLX5_FLOW_TABLE_MISS_ACTION_FWD,
2263 	MLX5_FLOW_TABLE_MISS_ACTION_SWITCH_DOMAIN,
2264 };
2265 
2266 struct mlx5_ifc_dest_format_struct_bits {
2267 	u8         destination_type[0x8];
2268 	u8         destination_id[0x18];
2269 
2270 	u8         destination_eswitch_owner_vhca_id_valid[0x1];
2271 	u8         packet_reformat[0x1];
2272 	u8         reserved_at_22[0x6];
2273 	u8         destination_table_type[0x8];
2274 	u8         destination_eswitch_owner_vhca_id[0x10];
2275 };
2276 
2277 struct mlx5_ifc_flow_counter_list_bits {
2278 	u8         flow_counter_id[0x20];
2279 
2280 	u8         reserved_at_20[0x20];
2281 };
2282 
2283 struct mlx5_ifc_extended_dest_format_bits {
2284 	struct mlx5_ifc_dest_format_struct_bits destination_entry;
2285 
2286 	u8         packet_reformat_id[0x20];
2287 
2288 	u8         reserved_at_60[0x20];
2289 };
2290 
2291 union mlx5_ifc_dest_format_flow_counter_list_auto_bits {
2292 	struct mlx5_ifc_extended_dest_format_bits extended_dest_format;
2293 	struct mlx5_ifc_flow_counter_list_bits flow_counter_list;
2294 };
2295 
2296 struct mlx5_ifc_fte_match_param_bits {
2297 	struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
2298 
2299 	struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
2300 
2301 	struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
2302 
2303 	struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2;
2304 
2305 	struct mlx5_ifc_fte_match_set_misc3_bits misc_parameters_3;
2306 
2307 	struct mlx5_ifc_fte_match_set_misc4_bits misc_parameters_4;
2308 
2309 	struct mlx5_ifc_fte_match_set_misc5_bits misc_parameters_5;
2310 
2311 	u8         reserved_at_e00[0x200];
2312 };
2313 
2314 enum {
2315 	MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP     = 0x0,
2316 	MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP     = 0x1,
2317 	MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT   = 0x2,
2318 	MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT   = 0x3,
2319 	MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI  = 0x4,
2320 };
2321 
2322 struct mlx5_ifc_rx_hash_field_select_bits {
2323 	u8         l3_prot_type[0x1];
2324 	u8         l4_prot_type[0x1];
2325 	u8         selected_fields[0x1e];
2326 };
2327 
2328 enum {
2329 	MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST  = 0x0,
2330 	MLX5_WQ_WQ_TYPE_WQ_CYCLIC       = 0x1,
2331 };
2332 
2333 enum {
2334 	MLX5_WQ_END_PADDING_MODE_END_PAD_NONE   = 0x0,
2335 	MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN  = 0x1,
2336 };
2337 
2338 struct mlx5_ifc_wq_bits {
2339 	u8         wq_type[0x4];
2340 	u8         wq_signature[0x1];
2341 	u8         end_padding_mode[0x2];
2342 	u8         cd_slave[0x1];
2343 	u8         reserved_at_8[0x18];
2344 
2345 	u8         hds_skip_first_sge[0x1];
2346 	u8         log2_hds_buf_size[0x3];
2347 	u8         reserved_at_24[0x7];
2348 	u8         page_offset[0x5];
2349 	u8         lwm[0x10];
2350 
2351 	u8         reserved_at_40[0x8];
2352 	u8         pd[0x18];
2353 
2354 	u8         reserved_at_60[0x8];
2355 	u8         uar_page[0x18];
2356 
2357 	u8         dbr_addr[0x40];
2358 
2359 	u8         hw_counter[0x20];
2360 
2361 	u8         sw_counter[0x20];
2362 
2363 	u8         reserved_at_100[0xc];
2364 	u8         log_wq_stride[0x4];
2365 	u8         reserved_at_110[0x3];
2366 	u8         log_wq_pg_sz[0x5];
2367 	u8         reserved_at_118[0x3];
2368 	u8         log_wq_sz[0x5];
2369 
2370 	u8         dbr_umem_valid[0x1];
2371 	u8         wq_umem_valid[0x1];
2372 	u8         reserved_at_122[0x1];
2373 	u8         log_hairpin_num_packets[0x5];
2374 	u8         reserved_at_128[0x3];
2375 	u8         log_hairpin_data_sz[0x5];
2376 
2377 	u8         reserved_at_130[0x4];
2378 	u8         log_wqe_num_of_strides[0x4];
2379 	u8         two_byte_shift_en[0x1];
2380 	u8         reserved_at_139[0x4];
2381 	u8         log_wqe_stride_size[0x3];
2382 
2383 	u8         dbr_umem_id[0x20];
2384 	u8         wq_umem_id[0x20];
2385 
2386 	u8         wq_umem_offset[0x40];
2387 
2388 	u8         headers_mkey[0x20];
2389 
2390 	u8         shampo_enable[0x1];
2391 	u8         reserved_at_1e1[0x1];
2392 	u8         shampo_mode[0x2];
2393 	u8         reserved_at_1e4[0x1];
2394 	u8         log_reservation_size[0x3];
2395 	u8         reserved_at_1e8[0x5];
2396 	u8         log_max_num_of_packets_per_reservation[0x3];
2397 	u8         reserved_at_1f0[0x6];
2398 	u8         log_headers_entry_size[0x2];
2399 	u8         reserved_at_1f8[0x4];
2400 	u8         log_headers_buffer_entry_num[0x4];
2401 
2402 	u8         reserved_at_200[0x400];
2403 
2404 	struct mlx5_ifc_cmd_pas_bits pas[];
2405 };
2406 
2407 struct mlx5_ifc_rq_num_bits {
2408 	u8         reserved_at_0[0x8];
2409 	u8         rq_num[0x18];
2410 };
2411 
2412 struct mlx5_ifc_rq_vhca_bits {
2413 	u8         reserved_at_0[0x8];
2414 	u8         rq_num[0x18];
2415 	u8         reserved_at_20[0x10];
2416 	u8         rq_vhca_id[0x10];
2417 };
2418 
2419 struct mlx5_ifc_mac_address_layout_bits {
2420 	u8         reserved_at_0[0x10];
2421 	u8         mac_addr_47_32[0x10];
2422 
2423 	u8         mac_addr_31_0[0x20];
2424 };
2425 
2426 struct mlx5_ifc_vlan_layout_bits {
2427 	u8         reserved_at_0[0x14];
2428 	u8         vlan[0x0c];
2429 
2430 	u8         reserved_at_20[0x20];
2431 };
2432 
2433 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
2434 	u8         reserved_at_0[0xa0];
2435 
2436 	u8         min_time_between_cnps[0x20];
2437 
2438 	u8         reserved_at_c0[0x12];
2439 	u8         cnp_dscp[0x6];
2440 	u8         reserved_at_d8[0x4];
2441 	u8         cnp_prio_mode[0x1];
2442 	u8         cnp_802p_prio[0x3];
2443 
2444 	u8         reserved_at_e0[0x720];
2445 };
2446 
2447 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
2448 	u8         reserved_at_0[0x60];
2449 
2450 	u8         reserved_at_60[0x4];
2451 	u8         clamp_tgt_rate[0x1];
2452 	u8         reserved_at_65[0x3];
2453 	u8         clamp_tgt_rate_after_time_inc[0x1];
2454 	u8         reserved_at_69[0x17];
2455 
2456 	u8         reserved_at_80[0x20];
2457 
2458 	u8         rpg_time_reset[0x20];
2459 
2460 	u8         rpg_byte_reset[0x20];
2461 
2462 	u8         rpg_threshold[0x20];
2463 
2464 	u8         rpg_max_rate[0x20];
2465 
2466 	u8         rpg_ai_rate[0x20];
2467 
2468 	u8         rpg_hai_rate[0x20];
2469 
2470 	u8         rpg_gd[0x20];
2471 
2472 	u8         rpg_min_dec_fac[0x20];
2473 
2474 	u8         rpg_min_rate[0x20];
2475 
2476 	u8         reserved_at_1c0[0xe0];
2477 
2478 	u8         rate_to_set_on_first_cnp[0x20];
2479 
2480 	u8         dce_tcp_g[0x20];
2481 
2482 	u8         dce_tcp_rtt[0x20];
2483 
2484 	u8         rate_reduce_monitor_period[0x20];
2485 
2486 	u8         reserved_at_320[0x20];
2487 
2488 	u8         initial_alpha_value[0x20];
2489 
2490 	u8         reserved_at_360[0x4a0];
2491 };
2492 
2493 struct mlx5_ifc_cong_control_r_roce_general_bits {
2494 	u8         reserved_at_0[0x80];
2495 
2496 	u8         reserved_at_80[0x10];
2497 	u8         rtt_resp_dscp_valid[0x1];
2498 	u8         reserved_at_91[0x9];
2499 	u8         rtt_resp_dscp[0x6];
2500 
2501 	u8         reserved_at_a0[0x760];
2502 };
2503 
2504 struct mlx5_ifc_cong_control_802_1qau_rp_bits {
2505 	u8         reserved_at_0[0x80];
2506 
2507 	u8         rppp_max_rps[0x20];
2508 
2509 	u8         rpg_time_reset[0x20];
2510 
2511 	u8         rpg_byte_reset[0x20];
2512 
2513 	u8         rpg_threshold[0x20];
2514 
2515 	u8         rpg_max_rate[0x20];
2516 
2517 	u8         rpg_ai_rate[0x20];
2518 
2519 	u8         rpg_hai_rate[0x20];
2520 
2521 	u8         rpg_gd[0x20];
2522 
2523 	u8         rpg_min_dec_fac[0x20];
2524 
2525 	u8         rpg_min_rate[0x20];
2526 
2527 	u8         reserved_at_1c0[0x640];
2528 };
2529 
2530 enum {
2531 	MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE    = 0x1,
2532 	MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET    = 0x2,
2533 	MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE  = 0x4,
2534 };
2535 
2536 struct mlx5_ifc_resize_field_select_bits {
2537 	u8         resize_field_select[0x20];
2538 };
2539 
2540 struct mlx5_ifc_resource_dump_bits {
2541 	u8         more_dump[0x1];
2542 	u8         inline_dump[0x1];
2543 	u8         reserved_at_2[0xa];
2544 	u8         seq_num[0x4];
2545 	u8         segment_type[0x10];
2546 
2547 	u8         reserved_at_20[0x10];
2548 	u8         vhca_id[0x10];
2549 
2550 	u8         index1[0x20];
2551 
2552 	u8         index2[0x20];
2553 
2554 	u8         num_of_obj1[0x10];
2555 	u8         num_of_obj2[0x10];
2556 
2557 	u8         reserved_at_a0[0x20];
2558 
2559 	u8         device_opaque[0x40];
2560 
2561 	u8         mkey[0x20];
2562 
2563 	u8         size[0x20];
2564 
2565 	u8         address[0x40];
2566 
2567 	u8         inline_data[52][0x20];
2568 };
2569 
2570 struct mlx5_ifc_resource_dump_menu_record_bits {
2571 	u8         reserved_at_0[0x4];
2572 	u8         num_of_obj2_supports_active[0x1];
2573 	u8         num_of_obj2_supports_all[0x1];
2574 	u8         must_have_num_of_obj2[0x1];
2575 	u8         support_num_of_obj2[0x1];
2576 	u8         num_of_obj1_supports_active[0x1];
2577 	u8         num_of_obj1_supports_all[0x1];
2578 	u8         must_have_num_of_obj1[0x1];
2579 	u8         support_num_of_obj1[0x1];
2580 	u8         must_have_index2[0x1];
2581 	u8         support_index2[0x1];
2582 	u8         must_have_index1[0x1];
2583 	u8         support_index1[0x1];
2584 	u8         segment_type[0x10];
2585 
2586 	u8         segment_name[4][0x20];
2587 
2588 	u8         index1_name[4][0x20];
2589 
2590 	u8         index2_name[4][0x20];
2591 };
2592 
2593 struct mlx5_ifc_resource_dump_segment_header_bits {
2594 	u8         length_dw[0x10];
2595 	u8         segment_type[0x10];
2596 };
2597 
2598 struct mlx5_ifc_resource_dump_command_segment_bits {
2599 	struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2600 
2601 	u8         segment_called[0x10];
2602 	u8         vhca_id[0x10];
2603 
2604 	u8         index1[0x20];
2605 
2606 	u8         index2[0x20];
2607 
2608 	u8         num_of_obj1[0x10];
2609 	u8         num_of_obj2[0x10];
2610 };
2611 
2612 struct mlx5_ifc_resource_dump_error_segment_bits {
2613 	struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2614 
2615 	u8         reserved_at_20[0x10];
2616 	u8         syndrome_id[0x10];
2617 
2618 	u8         reserved_at_40[0x40];
2619 
2620 	u8         error[8][0x20];
2621 };
2622 
2623 struct mlx5_ifc_resource_dump_info_segment_bits {
2624 	struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2625 
2626 	u8         reserved_at_20[0x18];
2627 	u8         dump_version[0x8];
2628 
2629 	u8         hw_version[0x20];
2630 
2631 	u8         fw_version[0x20];
2632 };
2633 
2634 struct mlx5_ifc_resource_dump_menu_segment_bits {
2635 	struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2636 
2637 	u8         reserved_at_20[0x10];
2638 	u8         num_of_records[0x10];
2639 
2640 	struct mlx5_ifc_resource_dump_menu_record_bits record[];
2641 };
2642 
2643 struct mlx5_ifc_resource_dump_resource_segment_bits {
2644 	struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2645 
2646 	u8         reserved_at_20[0x20];
2647 
2648 	u8         index1[0x20];
2649 
2650 	u8         index2[0x20];
2651 
2652 	u8         payload[][0x20];
2653 };
2654 
2655 struct mlx5_ifc_resource_dump_terminate_segment_bits {
2656 	struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2657 };
2658 
2659 struct mlx5_ifc_menu_resource_dump_response_bits {
2660 	struct mlx5_ifc_resource_dump_info_segment_bits info;
2661 	struct mlx5_ifc_resource_dump_command_segment_bits cmd;
2662 	struct mlx5_ifc_resource_dump_menu_segment_bits menu;
2663 	struct mlx5_ifc_resource_dump_terminate_segment_bits terminate;
2664 };
2665 
2666 enum {
2667 	MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD     = 0x1,
2668 	MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT  = 0x2,
2669 	MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI            = 0x4,
2670 	MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN         = 0x8,
2671 };
2672 
2673 struct mlx5_ifc_modify_field_select_bits {
2674 	u8         modify_field_select[0x20];
2675 };
2676 
2677 struct mlx5_ifc_field_select_r_roce_np_bits {
2678 	u8         field_select_r_roce_np[0x20];
2679 };
2680 
2681 struct mlx5_ifc_field_select_r_roce_rp_bits {
2682 	u8         field_select_r_roce_rp[0x20];
2683 };
2684 
2685 enum {
2686 	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS     = 0x4,
2687 	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET   = 0x8,
2688 	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET   = 0x10,
2689 	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD    = 0x20,
2690 	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE     = 0x40,
2691 	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE      = 0x80,
2692 	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE     = 0x100,
2693 	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD           = 0x200,
2694 	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC  = 0x400,
2695 	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE     = 0x800,
2696 };
2697 
2698 struct mlx5_ifc_field_select_802_1qau_rp_bits {
2699 	u8         field_select_8021qaurp[0x20];
2700 };
2701 
2702 struct mlx5_ifc_phys_layer_recovery_cntrs_bits {
2703 	u8         total_successful_recovery_events[0x20];
2704 
2705 	u8         reserved_at_20[0x7a0];
2706 };
2707 
2708 struct mlx5_ifc_phys_layer_cntrs_bits {
2709 	u8         time_since_last_clear_high[0x20];
2710 
2711 	u8         time_since_last_clear_low[0x20];
2712 
2713 	u8         symbol_errors_high[0x20];
2714 
2715 	u8         symbol_errors_low[0x20];
2716 
2717 	u8         sync_headers_errors_high[0x20];
2718 
2719 	u8         sync_headers_errors_low[0x20];
2720 
2721 	u8         edpl_bip_errors_lane0_high[0x20];
2722 
2723 	u8         edpl_bip_errors_lane0_low[0x20];
2724 
2725 	u8         edpl_bip_errors_lane1_high[0x20];
2726 
2727 	u8         edpl_bip_errors_lane1_low[0x20];
2728 
2729 	u8         edpl_bip_errors_lane2_high[0x20];
2730 
2731 	u8         edpl_bip_errors_lane2_low[0x20];
2732 
2733 	u8         edpl_bip_errors_lane3_high[0x20];
2734 
2735 	u8         edpl_bip_errors_lane3_low[0x20];
2736 
2737 	u8         fc_fec_corrected_blocks_lane0_high[0x20];
2738 
2739 	u8         fc_fec_corrected_blocks_lane0_low[0x20];
2740 
2741 	u8         fc_fec_corrected_blocks_lane1_high[0x20];
2742 
2743 	u8         fc_fec_corrected_blocks_lane1_low[0x20];
2744 
2745 	u8         fc_fec_corrected_blocks_lane2_high[0x20];
2746 
2747 	u8         fc_fec_corrected_blocks_lane2_low[0x20];
2748 
2749 	u8         fc_fec_corrected_blocks_lane3_high[0x20];
2750 
2751 	u8         fc_fec_corrected_blocks_lane3_low[0x20];
2752 
2753 	u8         fc_fec_uncorrectable_blocks_lane0_high[0x20];
2754 
2755 	u8         fc_fec_uncorrectable_blocks_lane0_low[0x20];
2756 
2757 	u8         fc_fec_uncorrectable_blocks_lane1_high[0x20];
2758 
2759 	u8         fc_fec_uncorrectable_blocks_lane1_low[0x20];
2760 
2761 	u8         fc_fec_uncorrectable_blocks_lane2_high[0x20];
2762 
2763 	u8         fc_fec_uncorrectable_blocks_lane2_low[0x20];
2764 
2765 	u8         fc_fec_uncorrectable_blocks_lane3_high[0x20];
2766 
2767 	u8         fc_fec_uncorrectable_blocks_lane3_low[0x20];
2768 
2769 	u8         rs_fec_corrected_blocks_high[0x20];
2770 
2771 	u8         rs_fec_corrected_blocks_low[0x20];
2772 
2773 	u8         rs_fec_uncorrectable_blocks_high[0x20];
2774 
2775 	u8         rs_fec_uncorrectable_blocks_low[0x20];
2776 
2777 	u8         rs_fec_no_errors_blocks_high[0x20];
2778 
2779 	u8         rs_fec_no_errors_blocks_low[0x20];
2780 
2781 	u8         rs_fec_single_error_blocks_high[0x20];
2782 
2783 	u8         rs_fec_single_error_blocks_low[0x20];
2784 
2785 	u8         rs_fec_corrected_symbols_total_high[0x20];
2786 
2787 	u8         rs_fec_corrected_symbols_total_low[0x20];
2788 
2789 	u8         rs_fec_corrected_symbols_lane0_high[0x20];
2790 
2791 	u8         rs_fec_corrected_symbols_lane0_low[0x20];
2792 
2793 	u8         rs_fec_corrected_symbols_lane1_high[0x20];
2794 
2795 	u8         rs_fec_corrected_symbols_lane1_low[0x20];
2796 
2797 	u8         rs_fec_corrected_symbols_lane2_high[0x20];
2798 
2799 	u8         rs_fec_corrected_symbols_lane2_low[0x20];
2800 
2801 	u8         rs_fec_corrected_symbols_lane3_high[0x20];
2802 
2803 	u8         rs_fec_corrected_symbols_lane3_low[0x20];
2804 
2805 	u8         link_down_events[0x20];
2806 
2807 	u8         successful_recovery_events[0x20];
2808 
2809 	u8         reserved_at_640[0x180];
2810 };
2811 
2812 struct mlx5_ifc_phys_layer_statistical_cntrs_bits {
2813 	u8         time_since_last_clear_high[0x20];
2814 
2815 	u8         time_since_last_clear_low[0x20];
2816 
2817 	u8         phy_received_bits_high[0x20];
2818 
2819 	u8         phy_received_bits_low[0x20];
2820 
2821 	u8         phy_symbol_errors_high[0x20];
2822 
2823 	u8         phy_symbol_errors_low[0x20];
2824 
2825 	u8         phy_corrected_bits_high[0x20];
2826 
2827 	u8         phy_corrected_bits_low[0x20];
2828 
2829 	u8         phy_corrected_bits_lane0_high[0x20];
2830 
2831 	u8         phy_corrected_bits_lane0_low[0x20];
2832 
2833 	u8         phy_corrected_bits_lane1_high[0x20];
2834 
2835 	u8         phy_corrected_bits_lane1_low[0x20];
2836 
2837 	u8         phy_corrected_bits_lane2_high[0x20];
2838 
2839 	u8         phy_corrected_bits_lane2_low[0x20];
2840 
2841 	u8         phy_corrected_bits_lane3_high[0x20];
2842 
2843 	u8         phy_corrected_bits_lane3_low[0x20];
2844 
2845 	u8         reserved_at_200[0x5c0];
2846 };
2847 
2848 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits {
2849 	u8	   symbol_error_counter[0x10];
2850 
2851 	u8         link_error_recovery_counter[0x8];
2852 
2853 	u8         link_downed_counter[0x8];
2854 
2855 	u8         port_rcv_errors[0x10];
2856 
2857 	u8         port_rcv_remote_physical_errors[0x10];
2858 
2859 	u8         port_rcv_switch_relay_errors[0x10];
2860 
2861 	u8         port_xmit_discards[0x10];
2862 
2863 	u8         port_xmit_constraint_errors[0x8];
2864 
2865 	u8         port_rcv_constraint_errors[0x8];
2866 
2867 	u8         reserved_at_70[0x8];
2868 
2869 	u8         link_overrun_errors[0x8];
2870 
2871 	u8	   reserved_at_80[0x10];
2872 
2873 	u8         vl_15_dropped[0x10];
2874 
2875 	u8	   reserved_at_a0[0x80];
2876 
2877 	u8         port_xmit_wait[0x20];
2878 };
2879 
2880 struct mlx5_ifc_ib_ext_port_cntrs_grp_data_layout_bits {
2881 	u8         reserved_at_0[0x300];
2882 
2883 	u8         port_xmit_data_high[0x20];
2884 
2885 	u8         port_xmit_data_low[0x20];
2886 
2887 	u8         port_rcv_data_high[0x20];
2888 
2889 	u8         port_rcv_data_low[0x20];
2890 
2891 	u8         port_xmit_pkts_high[0x20];
2892 
2893 	u8         port_xmit_pkts_low[0x20];
2894 
2895 	u8         port_rcv_pkts_high[0x20];
2896 
2897 	u8         port_rcv_pkts_low[0x20];
2898 
2899 	u8         reserved_at_400[0x80];
2900 
2901 	u8         port_unicast_xmit_pkts_high[0x20];
2902 
2903 	u8         port_unicast_xmit_pkts_low[0x20];
2904 
2905 	u8         port_multicast_xmit_pkts_high[0x20];
2906 
2907 	u8         port_multicast_xmit_pkts_low[0x20];
2908 
2909 	u8         port_unicast_rcv_pkts_high[0x20];
2910 
2911 	u8         port_unicast_rcv_pkts_low[0x20];
2912 
2913 	u8         port_multicast_rcv_pkts_high[0x20];
2914 
2915 	u8         port_multicast_rcv_pkts_low[0x20];
2916 
2917 	u8         reserved_at_580[0x240];
2918 };
2919 
2920 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits {
2921 	u8         transmit_queue_high[0x20];
2922 
2923 	u8         transmit_queue_low[0x20];
2924 
2925 	u8         no_buffer_discard_uc_high[0x20];
2926 
2927 	u8         no_buffer_discard_uc_low[0x20];
2928 
2929 	u8         reserved_at_80[0x740];
2930 };
2931 
2932 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits {
2933 	u8         wred_discard_high[0x20];
2934 
2935 	u8         wred_discard_low[0x20];
2936 
2937 	u8         ecn_marked_tc_high[0x20];
2938 
2939 	u8         ecn_marked_tc_low[0x20];
2940 
2941 	u8         reserved_at_80[0x740];
2942 };
2943 
2944 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
2945 	u8         rx_octets_high[0x20];
2946 
2947 	u8         rx_octets_low[0x20];
2948 
2949 	u8         reserved_at_40[0xc0];
2950 
2951 	u8         rx_frames_high[0x20];
2952 
2953 	u8         rx_frames_low[0x20];
2954 
2955 	u8         tx_octets_high[0x20];
2956 
2957 	u8         tx_octets_low[0x20];
2958 
2959 	u8         reserved_at_180[0xc0];
2960 
2961 	u8         tx_frames_high[0x20];
2962 
2963 	u8         tx_frames_low[0x20];
2964 
2965 	u8         rx_pause_high[0x20];
2966 
2967 	u8         rx_pause_low[0x20];
2968 
2969 	u8         rx_pause_duration_high[0x20];
2970 
2971 	u8         rx_pause_duration_low[0x20];
2972 
2973 	u8         tx_pause_high[0x20];
2974 
2975 	u8         tx_pause_low[0x20];
2976 
2977 	u8         tx_pause_duration_high[0x20];
2978 
2979 	u8         tx_pause_duration_low[0x20];
2980 
2981 	u8         rx_pause_transition_high[0x20];
2982 
2983 	u8         rx_pause_transition_low[0x20];
2984 
2985 	u8         rx_discards_high[0x20];
2986 
2987 	u8         rx_discards_low[0x20];
2988 
2989 	u8         device_stall_minor_watermark_cnt_high[0x20];
2990 
2991 	u8         device_stall_minor_watermark_cnt_low[0x20];
2992 
2993 	u8         device_stall_critical_watermark_cnt_high[0x20];
2994 
2995 	u8         device_stall_critical_watermark_cnt_low[0x20];
2996 
2997 	u8         reserved_at_480[0x340];
2998 };
2999 
3000 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
3001 	u8         port_transmit_wait_high[0x20];
3002 
3003 	u8         port_transmit_wait_low[0x20];
3004 
3005 	u8         reserved_at_40[0x100];
3006 
3007 	u8         rx_buffer_almost_full_high[0x20];
3008 
3009 	u8         rx_buffer_almost_full_low[0x20];
3010 
3011 	u8         rx_buffer_full_high[0x20];
3012 
3013 	u8         rx_buffer_full_low[0x20];
3014 
3015 	u8         rx_icrc_encapsulated_high[0x20];
3016 
3017 	u8         rx_icrc_encapsulated_low[0x20];
3018 
3019 	u8         reserved_at_200[0x5c0];
3020 };
3021 
3022 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
3023 	u8         dot3stats_alignment_errors_high[0x20];
3024 
3025 	u8         dot3stats_alignment_errors_low[0x20];
3026 
3027 	u8         dot3stats_fcs_errors_high[0x20];
3028 
3029 	u8         dot3stats_fcs_errors_low[0x20];
3030 
3031 	u8         dot3stats_single_collision_frames_high[0x20];
3032 
3033 	u8         dot3stats_single_collision_frames_low[0x20];
3034 
3035 	u8         dot3stats_multiple_collision_frames_high[0x20];
3036 
3037 	u8         dot3stats_multiple_collision_frames_low[0x20];
3038 
3039 	u8         dot3stats_sqe_test_errors_high[0x20];
3040 
3041 	u8         dot3stats_sqe_test_errors_low[0x20];
3042 
3043 	u8         dot3stats_deferred_transmissions_high[0x20];
3044 
3045 	u8         dot3stats_deferred_transmissions_low[0x20];
3046 
3047 	u8         dot3stats_late_collisions_high[0x20];
3048 
3049 	u8         dot3stats_late_collisions_low[0x20];
3050 
3051 	u8         dot3stats_excessive_collisions_high[0x20];
3052 
3053 	u8         dot3stats_excessive_collisions_low[0x20];
3054 
3055 	u8         dot3stats_internal_mac_transmit_errors_high[0x20];
3056 
3057 	u8         dot3stats_internal_mac_transmit_errors_low[0x20];
3058 
3059 	u8         dot3stats_carrier_sense_errors_high[0x20];
3060 
3061 	u8         dot3stats_carrier_sense_errors_low[0x20];
3062 
3063 	u8         dot3stats_frame_too_longs_high[0x20];
3064 
3065 	u8         dot3stats_frame_too_longs_low[0x20];
3066 
3067 	u8         dot3stats_internal_mac_receive_errors_high[0x20];
3068 
3069 	u8         dot3stats_internal_mac_receive_errors_low[0x20];
3070 
3071 	u8         dot3stats_symbol_errors_high[0x20];
3072 
3073 	u8         dot3stats_symbol_errors_low[0x20];
3074 
3075 	u8         dot3control_in_unknown_opcodes_high[0x20];
3076 
3077 	u8         dot3control_in_unknown_opcodes_low[0x20];
3078 
3079 	u8         dot3in_pause_frames_high[0x20];
3080 
3081 	u8         dot3in_pause_frames_low[0x20];
3082 
3083 	u8         dot3out_pause_frames_high[0x20];
3084 
3085 	u8         dot3out_pause_frames_low[0x20];
3086 
3087 	u8         reserved_at_400[0x3c0];
3088 };
3089 
3090 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
3091 	u8         ether_stats_drop_events_high[0x20];
3092 
3093 	u8         ether_stats_drop_events_low[0x20];
3094 
3095 	u8         ether_stats_octets_high[0x20];
3096 
3097 	u8         ether_stats_octets_low[0x20];
3098 
3099 	u8         ether_stats_pkts_high[0x20];
3100 
3101 	u8         ether_stats_pkts_low[0x20];
3102 
3103 	u8         ether_stats_broadcast_pkts_high[0x20];
3104 
3105 	u8         ether_stats_broadcast_pkts_low[0x20];
3106 
3107 	u8         ether_stats_multicast_pkts_high[0x20];
3108 
3109 	u8         ether_stats_multicast_pkts_low[0x20];
3110 
3111 	u8         ether_stats_crc_align_errors_high[0x20];
3112 
3113 	u8         ether_stats_crc_align_errors_low[0x20];
3114 
3115 	u8         ether_stats_undersize_pkts_high[0x20];
3116 
3117 	u8         ether_stats_undersize_pkts_low[0x20];
3118 
3119 	u8         ether_stats_oversize_pkts_high[0x20];
3120 
3121 	u8         ether_stats_oversize_pkts_low[0x20];
3122 
3123 	u8         ether_stats_fragments_high[0x20];
3124 
3125 	u8         ether_stats_fragments_low[0x20];
3126 
3127 	u8         ether_stats_jabbers_high[0x20];
3128 
3129 	u8         ether_stats_jabbers_low[0x20];
3130 
3131 	u8         ether_stats_collisions_high[0x20];
3132 
3133 	u8         ether_stats_collisions_low[0x20];
3134 
3135 	u8         ether_stats_pkts64octets_high[0x20];
3136 
3137 	u8         ether_stats_pkts64octets_low[0x20];
3138 
3139 	u8         ether_stats_pkts65to127octets_high[0x20];
3140 
3141 	u8         ether_stats_pkts65to127octets_low[0x20];
3142 
3143 	u8         ether_stats_pkts128to255octets_high[0x20];
3144 
3145 	u8         ether_stats_pkts128to255octets_low[0x20];
3146 
3147 	u8         ether_stats_pkts256to511octets_high[0x20];
3148 
3149 	u8         ether_stats_pkts256to511octets_low[0x20];
3150 
3151 	u8         ether_stats_pkts512to1023octets_high[0x20];
3152 
3153 	u8         ether_stats_pkts512to1023octets_low[0x20];
3154 
3155 	u8         ether_stats_pkts1024to1518octets_high[0x20];
3156 
3157 	u8         ether_stats_pkts1024to1518octets_low[0x20];
3158 
3159 	u8         ether_stats_pkts1519to2047octets_high[0x20];
3160 
3161 	u8         ether_stats_pkts1519to2047octets_low[0x20];
3162 
3163 	u8         ether_stats_pkts2048to4095octets_high[0x20];
3164 
3165 	u8         ether_stats_pkts2048to4095octets_low[0x20];
3166 
3167 	u8         ether_stats_pkts4096to8191octets_high[0x20];
3168 
3169 	u8         ether_stats_pkts4096to8191octets_low[0x20];
3170 
3171 	u8         ether_stats_pkts8192to10239octets_high[0x20];
3172 
3173 	u8         ether_stats_pkts8192to10239octets_low[0x20];
3174 
3175 	u8         reserved_at_540[0x280];
3176 };
3177 
3178 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
3179 	u8         if_in_octets_high[0x20];
3180 
3181 	u8         if_in_octets_low[0x20];
3182 
3183 	u8         if_in_ucast_pkts_high[0x20];
3184 
3185 	u8         if_in_ucast_pkts_low[0x20];
3186 
3187 	u8         if_in_discards_high[0x20];
3188 
3189 	u8         if_in_discards_low[0x20];
3190 
3191 	u8         if_in_errors_high[0x20];
3192 
3193 	u8         if_in_errors_low[0x20];
3194 
3195 	u8         if_in_unknown_protos_high[0x20];
3196 
3197 	u8         if_in_unknown_protos_low[0x20];
3198 
3199 	u8         if_out_octets_high[0x20];
3200 
3201 	u8         if_out_octets_low[0x20];
3202 
3203 	u8         if_out_ucast_pkts_high[0x20];
3204 
3205 	u8         if_out_ucast_pkts_low[0x20];
3206 
3207 	u8         if_out_discards_high[0x20];
3208 
3209 	u8         if_out_discards_low[0x20];
3210 
3211 	u8         if_out_errors_high[0x20];
3212 
3213 	u8         if_out_errors_low[0x20];
3214 
3215 	u8         if_in_multicast_pkts_high[0x20];
3216 
3217 	u8         if_in_multicast_pkts_low[0x20];
3218 
3219 	u8         if_in_broadcast_pkts_high[0x20];
3220 
3221 	u8         if_in_broadcast_pkts_low[0x20];
3222 
3223 	u8         if_out_multicast_pkts_high[0x20];
3224 
3225 	u8         if_out_multicast_pkts_low[0x20];
3226 
3227 	u8         if_out_broadcast_pkts_high[0x20];
3228 
3229 	u8         if_out_broadcast_pkts_low[0x20];
3230 
3231 	u8         reserved_at_340[0x480];
3232 };
3233 
3234 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
3235 	u8         a_frames_transmitted_ok_high[0x20];
3236 
3237 	u8         a_frames_transmitted_ok_low[0x20];
3238 
3239 	u8         a_frames_received_ok_high[0x20];
3240 
3241 	u8         a_frames_received_ok_low[0x20];
3242 
3243 	u8         a_frame_check_sequence_errors_high[0x20];
3244 
3245 	u8         a_frame_check_sequence_errors_low[0x20];
3246 
3247 	u8         a_alignment_errors_high[0x20];
3248 
3249 	u8         a_alignment_errors_low[0x20];
3250 
3251 	u8         a_octets_transmitted_ok_high[0x20];
3252 
3253 	u8         a_octets_transmitted_ok_low[0x20];
3254 
3255 	u8         a_octets_received_ok_high[0x20];
3256 
3257 	u8         a_octets_received_ok_low[0x20];
3258 
3259 	u8         a_multicast_frames_xmitted_ok_high[0x20];
3260 
3261 	u8         a_multicast_frames_xmitted_ok_low[0x20];
3262 
3263 	u8         a_broadcast_frames_xmitted_ok_high[0x20];
3264 
3265 	u8         a_broadcast_frames_xmitted_ok_low[0x20];
3266 
3267 	u8         a_multicast_frames_received_ok_high[0x20];
3268 
3269 	u8         a_multicast_frames_received_ok_low[0x20];
3270 
3271 	u8         a_broadcast_frames_received_ok_high[0x20];
3272 
3273 	u8         a_broadcast_frames_received_ok_low[0x20];
3274 
3275 	u8         a_in_range_length_errors_high[0x20];
3276 
3277 	u8         a_in_range_length_errors_low[0x20];
3278 
3279 	u8         a_out_of_range_length_field_high[0x20];
3280 
3281 	u8         a_out_of_range_length_field_low[0x20];
3282 
3283 	u8         a_frame_too_long_errors_high[0x20];
3284 
3285 	u8         a_frame_too_long_errors_low[0x20];
3286 
3287 	u8         a_symbol_error_during_carrier_high[0x20];
3288 
3289 	u8         a_symbol_error_during_carrier_low[0x20];
3290 
3291 	u8         a_mac_control_frames_transmitted_high[0x20];
3292 
3293 	u8         a_mac_control_frames_transmitted_low[0x20];
3294 
3295 	u8         a_mac_control_frames_received_high[0x20];
3296 
3297 	u8         a_mac_control_frames_received_low[0x20];
3298 
3299 	u8         a_unsupported_opcodes_received_high[0x20];
3300 
3301 	u8         a_unsupported_opcodes_received_low[0x20];
3302 
3303 	u8         a_pause_mac_ctrl_frames_received_high[0x20];
3304 
3305 	u8         a_pause_mac_ctrl_frames_received_low[0x20];
3306 
3307 	u8         a_pause_mac_ctrl_frames_transmitted_high[0x20];
3308 
3309 	u8         a_pause_mac_ctrl_frames_transmitted_low[0x20];
3310 
3311 	u8         reserved_at_4c0[0x300];
3312 };
3313 
3314 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits {
3315 	u8         life_time_counter_high[0x20];
3316 
3317 	u8         life_time_counter_low[0x20];
3318 
3319 	u8         rx_errors[0x20];
3320 
3321 	u8         tx_errors[0x20];
3322 
3323 	u8         l0_to_recovery_eieos[0x20];
3324 
3325 	u8         l0_to_recovery_ts[0x20];
3326 
3327 	u8         l0_to_recovery_framing[0x20];
3328 
3329 	u8         l0_to_recovery_retrain[0x20];
3330 
3331 	u8         crc_error_dllp[0x20];
3332 
3333 	u8         crc_error_tlp[0x20];
3334 
3335 	u8         tx_overflow_buffer_pkt_high[0x20];
3336 
3337 	u8         tx_overflow_buffer_pkt_low[0x20];
3338 
3339 	u8         outbound_stalled_reads[0x20];
3340 
3341 	u8         outbound_stalled_writes[0x20];
3342 
3343 	u8         outbound_stalled_reads_events[0x20];
3344 
3345 	u8         outbound_stalled_writes_events[0x20];
3346 
3347 	u8         reserved_at_200[0x5c0];
3348 };
3349 
3350 struct mlx5_ifc_cmd_inter_comp_event_bits {
3351 	u8         command_completion_vector[0x20];
3352 
3353 	u8         reserved_at_20[0xc0];
3354 };
3355 
3356 struct mlx5_ifc_stall_vl_event_bits {
3357 	u8         reserved_at_0[0x18];
3358 	u8         port_num[0x1];
3359 	u8         reserved_at_19[0x3];
3360 	u8         vl[0x4];
3361 
3362 	u8         reserved_at_20[0xa0];
3363 };
3364 
3365 struct mlx5_ifc_db_bf_congestion_event_bits {
3366 	u8         event_subtype[0x8];
3367 	u8         reserved_at_8[0x8];
3368 	u8         congestion_level[0x8];
3369 	u8         reserved_at_18[0x8];
3370 
3371 	u8         reserved_at_20[0xa0];
3372 };
3373 
3374 struct mlx5_ifc_gpio_event_bits {
3375 	u8         reserved_at_0[0x60];
3376 
3377 	u8         gpio_event_hi[0x20];
3378 
3379 	u8         gpio_event_lo[0x20];
3380 
3381 	u8         reserved_at_a0[0x40];
3382 };
3383 
3384 struct mlx5_ifc_port_state_change_event_bits {
3385 	u8         reserved_at_0[0x40];
3386 
3387 	u8         port_num[0x4];
3388 	u8         reserved_at_44[0x1c];
3389 
3390 	u8         reserved_at_60[0x80];
3391 };
3392 
3393 struct mlx5_ifc_dropped_packet_logged_bits {
3394 	u8         reserved_at_0[0xe0];
3395 };
3396 
3397 struct mlx5_ifc_nic_cap_reg_bits {
3398 	u8	   reserved_at_0[0x1a];
3399 	u8	   vhca_icm_ctrl[0x1];
3400 	u8	   reserved_at_1b[0x5];
3401 
3402 	u8	   reserved_at_20[0x60];
3403 };
3404 
3405 struct mlx5_ifc_default_timeout_bits {
3406 	u8         to_multiplier[0x3];
3407 	u8         reserved_at_3[0x9];
3408 	u8         to_value[0x14];
3409 };
3410 
3411 struct mlx5_ifc_dtor_reg_bits {
3412 	u8         reserved_at_0[0x20];
3413 
3414 	struct mlx5_ifc_default_timeout_bits pcie_toggle_to;
3415 
3416 	u8         reserved_at_40[0x60];
3417 
3418 	struct mlx5_ifc_default_timeout_bits health_poll_to;
3419 
3420 	struct mlx5_ifc_default_timeout_bits full_crdump_to;
3421 
3422 	struct mlx5_ifc_default_timeout_bits fw_reset_to;
3423 
3424 	struct mlx5_ifc_default_timeout_bits flush_on_err_to;
3425 
3426 	struct mlx5_ifc_default_timeout_bits pci_sync_update_to;
3427 
3428 	struct mlx5_ifc_default_timeout_bits tear_down_to;
3429 
3430 	struct mlx5_ifc_default_timeout_bits fsm_reactivate_to;
3431 
3432 	struct mlx5_ifc_default_timeout_bits reclaim_pages_to;
3433 
3434 	struct mlx5_ifc_default_timeout_bits reclaim_vfs_pages_to;
3435 
3436 	struct mlx5_ifc_default_timeout_bits reset_unload_to;
3437 
3438 	u8         reserved_at_1c0[0x20];
3439 };
3440 
3441 struct mlx5_ifc_vhca_icm_ctrl_reg_bits {
3442 	u8	   vhca_id_valid[0x1];
3443 	u8	   reserved_at_1[0xf];
3444 	u8	   vhca_id[0x10];
3445 
3446 	u8	   reserved_at_20[0xa0];
3447 
3448 	u8	   cur_alloc_icm[0x20];
3449 
3450 	u8	   reserved_at_e0[0x120];
3451 };
3452 
3453 enum {
3454 	MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN                 = 0x1,
3455 	MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR  = 0x2,
3456 };
3457 
3458 struct mlx5_ifc_cq_error_bits {
3459 	u8         reserved_at_0[0x8];
3460 	u8         cqn[0x18];
3461 
3462 	u8         reserved_at_20[0x20];
3463 
3464 	u8         reserved_at_40[0x18];
3465 	u8         syndrome[0x8];
3466 
3467 	u8         reserved_at_60[0x80];
3468 };
3469 
3470 struct mlx5_ifc_rdma_page_fault_event_bits {
3471 	u8         bytes_committed[0x20];
3472 
3473 	u8         r_key[0x20];
3474 
3475 	u8         reserved_at_40[0x10];
3476 	u8         packet_len[0x10];
3477 
3478 	u8         rdma_op_len[0x20];
3479 
3480 	u8         rdma_va[0x40];
3481 
3482 	u8         reserved_at_c0[0x5];
3483 	u8         rdma[0x1];
3484 	u8         write[0x1];
3485 	u8         requestor[0x1];
3486 	u8         qp_number[0x18];
3487 };
3488 
3489 struct mlx5_ifc_wqe_associated_page_fault_event_bits {
3490 	u8         bytes_committed[0x20];
3491 
3492 	u8         reserved_at_20[0x10];
3493 	u8         wqe_index[0x10];
3494 
3495 	u8         reserved_at_40[0x10];
3496 	u8         len[0x10];
3497 
3498 	u8         reserved_at_60[0x60];
3499 
3500 	u8         reserved_at_c0[0x5];
3501 	u8         rdma[0x1];
3502 	u8         write_read[0x1];
3503 	u8         requestor[0x1];
3504 	u8         qpn[0x18];
3505 };
3506 
3507 struct mlx5_ifc_qp_events_bits {
3508 	u8         reserved_at_0[0xa0];
3509 
3510 	u8         type[0x8];
3511 	u8         reserved_at_a8[0x18];
3512 
3513 	u8         reserved_at_c0[0x8];
3514 	u8         qpn_rqn_sqn[0x18];
3515 };
3516 
3517 struct mlx5_ifc_dct_events_bits {
3518 	u8         reserved_at_0[0xc0];
3519 
3520 	u8         reserved_at_c0[0x8];
3521 	u8         dct_number[0x18];
3522 };
3523 
3524 struct mlx5_ifc_comp_event_bits {
3525 	u8         reserved_at_0[0xc0];
3526 
3527 	u8         reserved_at_c0[0x8];
3528 	u8         cq_number[0x18];
3529 };
3530 
3531 enum {
3532 	MLX5_QPC_STATE_RST        = 0x0,
3533 	MLX5_QPC_STATE_INIT       = 0x1,
3534 	MLX5_QPC_STATE_RTR        = 0x2,
3535 	MLX5_QPC_STATE_RTS        = 0x3,
3536 	MLX5_QPC_STATE_SQER       = 0x4,
3537 	MLX5_QPC_STATE_ERR        = 0x6,
3538 	MLX5_QPC_STATE_SQD        = 0x7,
3539 	MLX5_QPC_STATE_SUSPENDED  = 0x9,
3540 };
3541 
3542 enum {
3543 	MLX5_QPC_ST_RC            = 0x0,
3544 	MLX5_QPC_ST_UC            = 0x1,
3545 	MLX5_QPC_ST_UD            = 0x2,
3546 	MLX5_QPC_ST_XRC           = 0x3,
3547 	MLX5_QPC_ST_DCI           = 0x5,
3548 	MLX5_QPC_ST_QP0           = 0x7,
3549 	MLX5_QPC_ST_QP1           = 0x8,
3550 	MLX5_QPC_ST_RAW_DATAGRAM  = 0x9,
3551 	MLX5_QPC_ST_REG_UMR       = 0xc,
3552 };
3553 
3554 enum {
3555 	MLX5_QPC_PM_STATE_ARMED     = 0x0,
3556 	MLX5_QPC_PM_STATE_REARM     = 0x1,
3557 	MLX5_QPC_PM_STATE_RESERVED  = 0x2,
3558 	MLX5_QPC_PM_STATE_MIGRATED  = 0x3,
3559 };
3560 
3561 enum {
3562 	MLX5_QPC_OFFLOAD_TYPE_RNDV  = 0x1,
3563 };
3564 
3565 enum {
3566 	MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS                = 0x0,
3567 	MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT  = 0x1,
3568 };
3569 
3570 enum {
3571 	MLX5_QPC_MTU_256_BYTES        = 0x1,
3572 	MLX5_QPC_MTU_512_BYTES        = 0x2,
3573 	MLX5_QPC_MTU_1K_BYTES         = 0x3,
3574 	MLX5_QPC_MTU_2K_BYTES         = 0x4,
3575 	MLX5_QPC_MTU_4K_BYTES         = 0x5,
3576 	MLX5_QPC_MTU_RAW_ETHERNET_QP  = 0x7,
3577 };
3578 
3579 enum {
3580 	MLX5_QPC_ATOMIC_MODE_IB_SPEC     = 0x1,
3581 	MLX5_QPC_ATOMIC_MODE_ONLY_8B     = 0x2,
3582 	MLX5_QPC_ATOMIC_MODE_UP_TO_8B    = 0x3,
3583 	MLX5_QPC_ATOMIC_MODE_UP_TO_16B   = 0x4,
3584 	MLX5_QPC_ATOMIC_MODE_UP_TO_32B   = 0x5,
3585 	MLX5_QPC_ATOMIC_MODE_UP_TO_64B   = 0x6,
3586 	MLX5_QPC_ATOMIC_MODE_UP_TO_128B  = 0x7,
3587 	MLX5_QPC_ATOMIC_MODE_UP_TO_256B  = 0x8,
3588 };
3589 
3590 enum {
3591 	MLX5_QPC_CS_REQ_DISABLE    = 0x0,
3592 	MLX5_QPC_CS_REQ_UP_TO_32B  = 0x11,
3593 	MLX5_QPC_CS_REQ_UP_TO_64B  = 0x22,
3594 };
3595 
3596 enum {
3597 	MLX5_QPC_CS_RES_DISABLE    = 0x0,
3598 	MLX5_QPC_CS_RES_UP_TO_32B  = 0x1,
3599 	MLX5_QPC_CS_RES_UP_TO_64B  = 0x2,
3600 };
3601 
3602 enum {
3603 	MLX5_TIMESTAMP_FORMAT_FREE_RUNNING = 0x0,
3604 	MLX5_TIMESTAMP_FORMAT_DEFAULT      = 0x1,
3605 	MLX5_TIMESTAMP_FORMAT_REAL_TIME    = 0x2,
3606 };
3607 
3608 struct mlx5_ifc_qpc_bits {
3609 	u8         state[0x4];
3610 	u8         lag_tx_port_affinity[0x4];
3611 	u8         st[0x8];
3612 	u8         reserved_at_10[0x2];
3613 	u8	   isolate_vl_tc[0x1];
3614 	u8         pm_state[0x2];
3615 	u8         reserved_at_15[0x1];
3616 	u8         req_e2e_credit_mode[0x2];
3617 	u8         offload_type[0x4];
3618 	u8         end_padding_mode[0x2];
3619 	u8         reserved_at_1e[0x2];
3620 
3621 	u8         wq_signature[0x1];
3622 	u8         block_lb_mc[0x1];
3623 	u8         atomic_like_write_en[0x1];
3624 	u8         latency_sensitive[0x1];
3625 	u8         reserved_at_24[0x1];
3626 	u8         drain_sigerr[0x1];
3627 	u8         reserved_at_26[0x1];
3628 	u8         dp_ordering_force[0x1];
3629 	u8         pd[0x18];
3630 
3631 	u8         mtu[0x3];
3632 	u8         log_msg_max[0x5];
3633 	u8         reserved_at_48[0x1];
3634 	u8         log_rq_size[0x4];
3635 	u8         log_rq_stride[0x3];
3636 	u8         no_sq[0x1];
3637 	u8         log_sq_size[0x4];
3638 	u8         reserved_at_55[0x1];
3639 	u8	   retry_mode[0x2];
3640 	u8	   ts_format[0x2];
3641 	u8         reserved_at_5a[0x1];
3642 	u8         rlky[0x1];
3643 	u8         ulp_stateless_offload_mode[0x4];
3644 
3645 	u8         counter_set_id[0x8];
3646 	u8         uar_page[0x18];
3647 
3648 	u8         reserved_at_80[0x8];
3649 	u8         user_index[0x18];
3650 
3651 	u8         reserved_at_a0[0x3];
3652 	u8         log_page_size[0x5];
3653 	u8         remote_qpn[0x18];
3654 
3655 	struct mlx5_ifc_ads_bits primary_address_path;
3656 
3657 	struct mlx5_ifc_ads_bits secondary_address_path;
3658 
3659 	u8         log_ack_req_freq[0x4];
3660 	u8         reserved_at_384[0x4];
3661 	u8         log_sra_max[0x3];
3662 	u8         reserved_at_38b[0x2];
3663 	u8         retry_count[0x3];
3664 	u8         rnr_retry[0x3];
3665 	u8         reserved_at_393[0x1];
3666 	u8         fre[0x1];
3667 	u8         cur_rnr_retry[0x3];
3668 	u8         cur_retry_count[0x3];
3669 	u8         reserved_at_39b[0x5];
3670 
3671 	u8         reserved_at_3a0[0x20];
3672 
3673 	u8         reserved_at_3c0[0x8];
3674 	u8         next_send_psn[0x18];
3675 
3676 	u8         reserved_at_3e0[0x3];
3677 	u8	   log_num_dci_stream_channels[0x5];
3678 	u8         cqn_snd[0x18];
3679 
3680 	u8         reserved_at_400[0x3];
3681 	u8	   log_num_dci_errored_streams[0x5];
3682 	u8         deth_sqpn[0x18];
3683 
3684 	u8         reserved_at_420[0x20];
3685 
3686 	u8         reserved_at_440[0x8];
3687 	u8         last_acked_psn[0x18];
3688 
3689 	u8         reserved_at_460[0x8];
3690 	u8         ssn[0x18];
3691 
3692 	u8         reserved_at_480[0x8];
3693 	u8         log_rra_max[0x3];
3694 	u8         reserved_at_48b[0x1];
3695 	u8         atomic_mode[0x4];
3696 	u8         rre[0x1];
3697 	u8         rwe[0x1];
3698 	u8         rae[0x1];
3699 	u8         reserved_at_493[0x1];
3700 	u8         page_offset[0x6];
3701 	u8         reserved_at_49a[0x2];
3702 	u8         dp_ordering_1[0x1];
3703 	u8         cd_slave_receive[0x1];
3704 	u8         cd_slave_send[0x1];
3705 	u8         cd_master[0x1];
3706 
3707 	u8         reserved_at_4a0[0x3];
3708 	u8         min_rnr_nak[0x5];
3709 	u8         next_rcv_psn[0x18];
3710 
3711 	u8         reserved_at_4c0[0x8];
3712 	u8         xrcd[0x18];
3713 
3714 	u8         reserved_at_4e0[0x8];
3715 	u8         cqn_rcv[0x18];
3716 
3717 	u8         dbr_addr[0x40];
3718 
3719 	u8         q_key[0x20];
3720 
3721 	u8         reserved_at_560[0x5];
3722 	u8         rq_type[0x3];
3723 	u8         srqn_rmpn_xrqn[0x18];
3724 
3725 	u8         reserved_at_580[0x8];
3726 	u8         rmsn[0x18];
3727 
3728 	u8         hw_sq_wqebb_counter[0x10];
3729 	u8         sw_sq_wqebb_counter[0x10];
3730 
3731 	u8         hw_rq_counter[0x20];
3732 
3733 	u8         sw_rq_counter[0x20];
3734 
3735 	u8         reserved_at_600[0x20];
3736 
3737 	u8         reserved_at_620[0xf];
3738 	u8         cgs[0x1];
3739 	u8         cs_req[0x8];
3740 	u8         cs_res[0x8];
3741 
3742 	u8         dc_access_key[0x40];
3743 
3744 	u8         reserved_at_680[0x3];
3745 	u8         dbr_umem_valid[0x1];
3746 
3747 	u8         reserved_at_684[0xbc];
3748 };
3749 
3750 struct mlx5_ifc_roce_addr_layout_bits {
3751 	u8         source_l3_address[16][0x8];
3752 
3753 	u8         reserved_at_80[0x3];
3754 	u8         vlan_valid[0x1];
3755 	u8         vlan_id[0xc];
3756 	u8         source_mac_47_32[0x10];
3757 
3758 	u8         source_mac_31_0[0x20];
3759 
3760 	u8         reserved_at_c0[0x14];
3761 	u8         roce_l3_type[0x4];
3762 	u8         roce_version[0x8];
3763 
3764 	u8         reserved_at_e0[0x20];
3765 };
3766 
3767 struct mlx5_ifc_crypto_cap_bits {
3768 	u8    reserved_at_0[0x3];
3769 	u8    synchronize_dek[0x1];
3770 	u8    int_kek_manual[0x1];
3771 	u8    int_kek_auto[0x1];
3772 	u8    reserved_at_6[0x1a];
3773 
3774 	u8    reserved_at_20[0x3];
3775 	u8    log_dek_max_alloc[0x5];
3776 	u8    reserved_at_28[0x3];
3777 	u8    log_max_num_deks[0x5];
3778 	u8    reserved_at_30[0x10];
3779 
3780 	u8    reserved_at_40[0x20];
3781 
3782 	u8    reserved_at_60[0x3];
3783 	u8    log_dek_granularity[0x5];
3784 	u8    reserved_at_68[0x3];
3785 	u8    log_max_num_int_kek[0x5];
3786 	u8    sw_wrapped_dek[0x10];
3787 
3788 	u8    reserved_at_80[0x780];
3789 };
3790 
3791 struct mlx5_ifc_shampo_cap_bits {
3792 	u8    reserved_at_0[0x3];
3793 	u8    shampo_log_max_reservation_size[0x5];
3794 	u8    reserved_at_8[0x3];
3795 	u8    shampo_log_min_reservation_size[0x5];
3796 	u8    shampo_min_mss_size[0x10];
3797 
3798 	u8    shampo_header_split[0x1];
3799 	u8    shampo_header_split_data_merge[0x1];
3800 	u8    reserved_at_22[0x1];
3801 	u8    shampo_log_max_headers_entry_size[0x5];
3802 	u8    reserved_at_28[0x18];
3803 
3804 	u8    reserved_at_40[0x7c0];
3805 };
3806 
3807 union mlx5_ifc_hca_cap_union_bits {
3808 	struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
3809 	struct mlx5_ifc_cmd_hca_cap_2_bits cmd_hca_cap_2;
3810 	struct mlx5_ifc_odp_cap_bits odp_cap;
3811 	struct mlx5_ifc_atomic_caps_bits atomic_caps;
3812 	struct mlx5_ifc_roce_cap_bits roce_cap;
3813 	struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
3814 	struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
3815 	struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap;
3816 	struct mlx5_ifc_wqe_based_flow_table_cap_bits wqe_based_flow_table_cap;
3817 	struct mlx5_ifc_esw_cap_bits esw_cap;
3818 	struct mlx5_ifc_e_switch_cap_bits e_switch_cap;
3819 	struct mlx5_ifc_port_selection_cap_bits port_selection_cap;
3820 	struct mlx5_ifc_qos_cap_bits qos_cap;
3821 	struct mlx5_ifc_debug_cap_bits debug_cap;
3822 	struct mlx5_ifc_fpga_cap_bits fpga_cap;
3823 	struct mlx5_ifc_tls_cap_bits tls_cap;
3824 	struct mlx5_ifc_device_mem_cap_bits device_mem_cap;
3825 	struct mlx5_ifc_virtio_emulation_cap_bits virtio_emulation_cap;
3826 	struct mlx5_ifc_macsec_cap_bits macsec_cap;
3827 	struct mlx5_ifc_crypto_cap_bits crypto_cap;
3828 	struct mlx5_ifc_ipsec_cap_bits ipsec_cap;
3829 	struct mlx5_ifc_psp_cap_bits psp_cap;
3830 	u8         reserved_at_0[0x8000];
3831 };
3832 
3833 enum {
3834 	MLX5_FLOW_CONTEXT_ACTION_ALLOW     = 0x1,
3835 	MLX5_FLOW_CONTEXT_ACTION_DROP      = 0x2,
3836 	MLX5_FLOW_CONTEXT_ACTION_FWD_DEST  = 0x4,
3837 	MLX5_FLOW_CONTEXT_ACTION_COUNT     = 0x8,
3838 	MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT = 0x10,
3839 	MLX5_FLOW_CONTEXT_ACTION_DECAP     = 0x20,
3840 	MLX5_FLOW_CONTEXT_ACTION_MOD_HDR   = 0x40,
3841 	MLX5_FLOW_CONTEXT_ACTION_VLAN_POP  = 0x80,
3842 	MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100,
3843 	MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2  = 0x400,
3844 	MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2 = 0x800,
3845 	MLX5_FLOW_CONTEXT_ACTION_CRYPTO_DECRYPT = 0x1000,
3846 	MLX5_FLOW_CONTEXT_ACTION_CRYPTO_ENCRYPT = 0x2000,
3847 	MLX5_FLOW_CONTEXT_ACTION_EXECUTE_ASO = 0x4000,
3848 };
3849 
3850 enum {
3851 	MLX5_FLOW_CONTEXT_FLOW_SOURCE_ANY_VPORT         = 0x0,
3852 	MLX5_FLOW_CONTEXT_FLOW_SOURCE_UPLINK            = 0x1,
3853 	MLX5_FLOW_CONTEXT_FLOW_SOURCE_LOCAL_VPORT       = 0x2,
3854 };
3855 
3856 enum {
3857 	MLX5_FLOW_CONTEXT_ENCRYPT_DECRYPT_TYPE_IPSEC   = 0x0,
3858 	MLX5_FLOW_CONTEXT_ENCRYPT_DECRYPT_TYPE_MACSEC  = 0x1,
3859 	MLX5_FLOW_CONTEXT_ENCRYPT_DECRYPT_TYPE_PSP     = 0x2,
3860 };
3861 
3862 struct mlx5_ifc_vlan_bits {
3863 	u8         ethtype[0x10];
3864 	u8         prio[0x3];
3865 	u8         cfi[0x1];
3866 	u8         vid[0xc];
3867 };
3868 
3869 enum {
3870 	MLX5_FLOW_METER_COLOR_RED	= 0x0,
3871 	MLX5_FLOW_METER_COLOR_YELLOW	= 0x1,
3872 	MLX5_FLOW_METER_COLOR_GREEN	= 0x2,
3873 	MLX5_FLOW_METER_COLOR_UNDEFINED	= 0x3,
3874 };
3875 
3876 enum {
3877 	MLX5_EXE_ASO_FLOW_METER		= 0x2,
3878 };
3879 
3880 struct mlx5_ifc_exe_aso_ctrl_flow_meter_bits {
3881 	u8        return_reg_id[0x4];
3882 	u8        aso_type[0x4];
3883 	u8        reserved_at_8[0x14];
3884 	u8        action[0x1];
3885 	u8        init_color[0x2];
3886 	u8        meter_id[0x1];
3887 };
3888 
3889 union mlx5_ifc_exe_aso_ctrl {
3890 	struct mlx5_ifc_exe_aso_ctrl_flow_meter_bits exe_aso_ctrl_flow_meter;
3891 };
3892 
3893 struct mlx5_ifc_execute_aso_bits {
3894 	u8        valid[0x1];
3895 	u8        reserved_at_1[0x7];
3896 	u8        aso_object_id[0x18];
3897 
3898 	union mlx5_ifc_exe_aso_ctrl exe_aso_ctrl;
3899 };
3900 
3901 struct mlx5_ifc_flow_context_bits {
3902 	struct mlx5_ifc_vlan_bits push_vlan;
3903 
3904 	u8         group_id[0x20];
3905 
3906 	u8         reserved_at_40[0x8];
3907 	u8         flow_tag[0x18];
3908 
3909 	u8         reserved_at_60[0x10];
3910 	u8         action[0x10];
3911 
3912 	u8         extended_destination[0x1];
3913 	u8         uplink_hairpin_en[0x1];
3914 	u8         flow_source[0x2];
3915 	u8         encrypt_decrypt_type[0x4];
3916 	u8         destination_list_size[0x18];
3917 
3918 	u8         reserved_at_a0[0x8];
3919 	u8         flow_counter_list_size[0x18];
3920 
3921 	u8         packet_reformat_id[0x20];
3922 
3923 	u8         modify_header_id[0x20];
3924 
3925 	struct mlx5_ifc_vlan_bits push_vlan_2;
3926 
3927 	u8         encrypt_decrypt_obj_id[0x20];
3928 	u8         reserved_at_140[0xc0];
3929 
3930 	struct mlx5_ifc_fte_match_param_bits match_value;
3931 
3932 	struct mlx5_ifc_execute_aso_bits execute_aso[4];
3933 
3934 	u8         reserved_at_1300[0x500];
3935 
3936 	union mlx5_ifc_dest_format_flow_counter_list_auto_bits destination[];
3937 };
3938 
3939 enum {
3940 	MLX5_XRC_SRQC_STATE_GOOD   = 0x0,
3941 	MLX5_XRC_SRQC_STATE_ERROR  = 0x1,
3942 };
3943 
3944 struct mlx5_ifc_xrc_srqc_bits {
3945 	u8         state[0x4];
3946 	u8         log_xrc_srq_size[0x4];
3947 	u8         reserved_at_8[0x18];
3948 
3949 	u8         wq_signature[0x1];
3950 	u8         cont_srq[0x1];
3951 	u8         reserved_at_22[0x1];
3952 	u8         rlky[0x1];
3953 	u8         basic_cyclic_rcv_wqe[0x1];
3954 	u8         log_rq_stride[0x3];
3955 	u8         xrcd[0x18];
3956 
3957 	u8         page_offset[0x6];
3958 	u8         reserved_at_46[0x1];
3959 	u8         dbr_umem_valid[0x1];
3960 	u8         cqn[0x18];
3961 
3962 	u8         reserved_at_60[0x20];
3963 
3964 	u8         user_index_equal_xrc_srqn[0x1];
3965 	u8         reserved_at_81[0x1];
3966 	u8         log_page_size[0x6];
3967 	u8         user_index[0x18];
3968 
3969 	u8         reserved_at_a0[0x20];
3970 
3971 	u8         reserved_at_c0[0x8];
3972 	u8         pd[0x18];
3973 
3974 	u8         lwm[0x10];
3975 	u8         wqe_cnt[0x10];
3976 
3977 	u8         reserved_at_100[0x40];
3978 
3979 	u8         db_record_addr_h[0x20];
3980 
3981 	u8         db_record_addr_l[0x1e];
3982 	u8         reserved_at_17e[0x2];
3983 
3984 	u8         reserved_at_180[0x80];
3985 };
3986 
3987 struct mlx5_ifc_vnic_diagnostic_statistics_bits {
3988 	u8         counter_error_queues[0x20];
3989 
3990 	u8         total_error_queues[0x20];
3991 
3992 	u8         send_queue_priority_update_flow[0x20];
3993 
3994 	u8         reserved_at_60[0x20];
3995 
3996 	u8         nic_receive_steering_discard[0x40];
3997 
3998 	u8         receive_discard_vport_down[0x40];
3999 
4000 	u8         transmit_discard_vport_down[0x40];
4001 
4002 	u8         async_eq_overrun[0x20];
4003 
4004 	u8         comp_eq_overrun[0x20];
4005 
4006 	u8         reserved_at_180[0x20];
4007 
4008 	u8         invalid_command[0x20];
4009 
4010 	u8         quota_exceeded_command[0x20];
4011 
4012 	u8         internal_rq_out_of_buffer[0x20];
4013 
4014 	u8         cq_overrun[0x20];
4015 
4016 	u8         eth_wqe_too_small[0x20];
4017 
4018 	u8         reserved_at_220[0xc0];
4019 
4020 	u8         generated_pkt_steering_fail[0x40];
4021 
4022 	u8         handled_pkt_steering_fail[0x40];
4023 
4024 	u8         bar_uar_access[0x20];
4025 
4026 	u8         odp_local_triggered_page_fault[0x20];
4027 
4028 	u8         odp_remote_triggered_page_fault[0x20];
4029 
4030 	u8         reserved_at_3c0[0xc20];
4031 };
4032 
4033 struct mlx5_ifc_traffic_counter_bits {
4034 	u8         packets[0x40];
4035 
4036 	u8         octets[0x40];
4037 };
4038 
4039 struct mlx5_ifc_tisc_bits {
4040 	u8         strict_lag_tx_port_affinity[0x1];
4041 	u8         tls_en[0x1];
4042 	u8         reserved_at_2[0x2];
4043 	u8         lag_tx_port_affinity[0x04];
4044 
4045 	u8         reserved_at_8[0x4];
4046 	u8         prio[0x4];
4047 	u8         reserved_at_10[0x10];
4048 
4049 	u8         reserved_at_20[0x100];
4050 
4051 	u8         reserved_at_120[0x8];
4052 	u8         transport_domain[0x18];
4053 
4054 	u8         reserved_at_140[0x8];
4055 	u8         underlay_qpn[0x18];
4056 
4057 	u8         reserved_at_160[0x8];
4058 	u8         pd[0x18];
4059 
4060 	u8         reserved_at_180[0x380];
4061 };
4062 
4063 enum {
4064 	MLX5_TIRC_DISP_TYPE_DIRECT    = 0x0,
4065 	MLX5_TIRC_DISP_TYPE_INDIRECT  = 0x1,
4066 };
4067 
4068 enum {
4069 	MLX5_TIRC_PACKET_MERGE_MASK_IPV4_LRO  = BIT(0),
4070 	MLX5_TIRC_PACKET_MERGE_MASK_IPV6_LRO  = BIT(1),
4071 };
4072 
4073 enum {
4074 	MLX5_RX_HASH_FN_NONE           = 0x0,
4075 	MLX5_RX_HASH_FN_INVERTED_XOR8  = 0x1,
4076 	MLX5_RX_HASH_FN_TOEPLITZ       = 0x2,
4077 };
4078 
4079 enum {
4080 	MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST    = 0x1,
4081 	MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST  = 0x2,
4082 };
4083 
4084 struct mlx5_ifc_tirc_bits {
4085 	u8         reserved_at_0[0x20];
4086 
4087 	u8         disp_type[0x4];
4088 	u8         tls_en[0x1];
4089 	u8         reserved_at_25[0x1b];
4090 
4091 	u8         reserved_at_40[0x40];
4092 
4093 	u8         reserved_at_80[0x4];
4094 	u8         lro_timeout_period_usecs[0x10];
4095 	u8         packet_merge_mask[0x4];
4096 	u8         lro_max_ip_payload_size[0x8];
4097 
4098 	u8         reserved_at_a0[0x40];
4099 
4100 	u8         reserved_at_e0[0x8];
4101 	u8         inline_rqn[0x18];
4102 
4103 	u8         rx_hash_symmetric[0x1];
4104 	u8         reserved_at_101[0x1];
4105 	u8         tunneled_offload_en[0x1];
4106 	u8         reserved_at_103[0x5];
4107 	u8         indirect_table[0x18];
4108 
4109 	u8         rx_hash_fn[0x4];
4110 	u8         reserved_at_124[0x2];
4111 	u8         self_lb_block[0x2];
4112 	u8         transport_domain[0x18];
4113 
4114 	u8         rx_hash_toeplitz_key[10][0x20];
4115 
4116 	struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
4117 
4118 	struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
4119 
4120 	u8         reserved_at_2c0[0x4c0];
4121 };
4122 
4123 enum {
4124 	MLX5_SRQC_STATE_GOOD   = 0x0,
4125 	MLX5_SRQC_STATE_ERROR  = 0x1,
4126 };
4127 
4128 struct mlx5_ifc_srqc_bits {
4129 	u8         state[0x4];
4130 	u8         log_srq_size[0x4];
4131 	u8         reserved_at_8[0x18];
4132 
4133 	u8         wq_signature[0x1];
4134 	u8         cont_srq[0x1];
4135 	u8         reserved_at_22[0x1];
4136 	u8         rlky[0x1];
4137 	u8         reserved_at_24[0x1];
4138 	u8         log_rq_stride[0x3];
4139 	u8         xrcd[0x18];
4140 
4141 	u8         page_offset[0x6];
4142 	u8         reserved_at_46[0x2];
4143 	u8         cqn[0x18];
4144 
4145 	u8         reserved_at_60[0x20];
4146 
4147 	u8         reserved_at_80[0x2];
4148 	u8         log_page_size[0x6];
4149 	u8         reserved_at_88[0x18];
4150 
4151 	u8         reserved_at_a0[0x20];
4152 
4153 	u8         reserved_at_c0[0x8];
4154 	u8         pd[0x18];
4155 
4156 	u8         lwm[0x10];
4157 	u8         wqe_cnt[0x10];
4158 
4159 	u8         reserved_at_100[0x40];
4160 
4161 	u8         dbr_addr[0x40];
4162 
4163 	u8         reserved_at_180[0x80];
4164 };
4165 
4166 enum {
4167 	MLX5_SQC_STATE_RST  = 0x0,
4168 	MLX5_SQC_STATE_RDY  = 0x1,
4169 	MLX5_SQC_STATE_ERR  = 0x3,
4170 };
4171 
4172 struct mlx5_ifc_sqc_bits {
4173 	u8         rlky[0x1];
4174 	u8         cd_master[0x1];
4175 	u8         fre[0x1];
4176 	u8         flush_in_error_en[0x1];
4177 	u8         allow_multi_pkt_send_wqe[0x1];
4178 	u8	   min_wqe_inline_mode[0x3];
4179 	u8         state[0x4];
4180 	u8         reg_umr[0x1];
4181 	u8         allow_swp[0x1];
4182 	u8         hairpin[0x1];
4183 	u8         non_wire[0x1];
4184 	u8         reserved_at_10[0xa];
4185 	u8	   ts_format[0x2];
4186 	u8	   reserved_at_1c[0x4];
4187 
4188 	u8         reserved_at_20[0x8];
4189 	u8         user_index[0x18];
4190 
4191 	u8         reserved_at_40[0x8];
4192 	u8         cqn[0x18];
4193 
4194 	u8         reserved_at_60[0x8];
4195 	u8         hairpin_peer_rq[0x18];
4196 
4197 	u8         reserved_at_80[0x10];
4198 	u8         hairpin_peer_vhca[0x10];
4199 
4200 	u8         reserved_at_a0[0x20];
4201 
4202 	u8         reserved_at_c0[0x8];
4203 	u8         ts_cqe_to_dest_cqn[0x18];
4204 
4205 	u8         reserved_at_e0[0x10];
4206 	u8         packet_pacing_rate_limit_index[0x10];
4207 	u8         tis_lst_sz[0x10];
4208 	u8         qos_queue_group_id[0x10];
4209 
4210 	u8         reserved_at_120[0x40];
4211 
4212 	u8         reserved_at_160[0x8];
4213 	u8         tis_num_0[0x18];
4214 
4215 	struct mlx5_ifc_wq_bits wq;
4216 };
4217 
4218 enum {
4219 	SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0,
4220 	SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1,
4221 	SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2,
4222 	SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3,
4223 	SCHEDULING_CONTEXT_ELEMENT_TYPE_QUEUE_GROUP = 0x4,
4224 	SCHEDULING_CONTEXT_ELEMENT_TYPE_RATE_LIMIT = 0x5,
4225 };
4226 
4227 enum {
4228 	ELEMENT_TYPE_CAP_MASK_TSAR		= 1 << 0,
4229 	ELEMENT_TYPE_CAP_MASK_VPORT		= 1 << 1,
4230 	ELEMENT_TYPE_CAP_MASK_VPORT_TC		= 1 << 2,
4231 	ELEMENT_TYPE_CAP_MASK_PARA_VPORT_TC	= 1 << 3,
4232 	ELEMENT_TYPE_CAP_MASK_QUEUE_GROUP	= 1 << 4,
4233 	ELEMENT_TYPE_CAP_MASK_RATE_LIMIT	= 1 << 5,
4234 };
4235 
4236 enum {
4237 	TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0,
4238 	TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1,
4239 	TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2,
4240 	TSAR_ELEMENT_TSAR_TYPE_TC_ARB = 0x3,
4241 };
4242 
4243 enum {
4244 	TSAR_TYPE_CAP_MASK_DWRR		= 1 << 0,
4245 	TSAR_TYPE_CAP_MASK_ROUND_ROBIN	= 1 << 1,
4246 	TSAR_TYPE_CAP_MASK_ETS		= 1 << 2,
4247 	TSAR_TYPE_CAP_MASK_TC_ARB       = 1 << 3,
4248 };
4249 
4250 struct mlx5_ifc_tsar_element_bits {
4251 	u8         traffic_class[0x4];
4252 	u8         reserved_at_4[0x4];
4253 	u8         tsar_type[0x8];
4254 	u8         reserved_at_10[0x10];
4255 };
4256 
4257 struct mlx5_ifc_vport_element_bits {
4258 	u8         reserved_at_0[0x4];
4259 	u8         eswitch_owner_vhca_id_valid[0x1];
4260 	u8         eswitch_owner_vhca_id[0xb];
4261 	u8         vport_number[0x10];
4262 };
4263 
4264 struct mlx5_ifc_vport_tc_element_bits {
4265 	u8         traffic_class[0x4];
4266 	u8         eswitch_owner_vhca_id_valid[0x1];
4267 	u8         eswitch_owner_vhca_id[0xb];
4268 	u8         vport_number[0x10];
4269 };
4270 
4271 union mlx5_ifc_element_attributes_bits {
4272 	struct mlx5_ifc_tsar_element_bits tsar;
4273 	struct mlx5_ifc_vport_element_bits vport;
4274 	struct mlx5_ifc_vport_tc_element_bits vport_tc;
4275 	u8 reserved_at_0[0x20];
4276 };
4277 
4278 struct mlx5_ifc_scheduling_context_bits {
4279 	u8         element_type[0x8];
4280 	u8         reserved_at_8[0x18];
4281 
4282 	union mlx5_ifc_element_attributes_bits element_attributes;
4283 
4284 	u8         parent_element_id[0x20];
4285 
4286 	u8         reserved_at_60[0x40];
4287 
4288 	u8         bw_share[0x20];
4289 
4290 	u8         max_average_bw[0x20];
4291 
4292 	u8         max_bw_obj_id[0x20];
4293 
4294 	u8         reserved_at_100[0x100];
4295 };
4296 
4297 struct mlx5_ifc_rqtc_bits {
4298 	u8    reserved_at_0[0xa0];
4299 
4300 	u8    reserved_at_a0[0x5];
4301 	u8    list_q_type[0x3];
4302 	u8    reserved_at_a8[0x8];
4303 	u8    rqt_max_size[0x10];
4304 
4305 	u8    rq_vhca_id_format[0x1];
4306 	u8    reserved_at_c1[0xf];
4307 	u8    rqt_actual_size[0x10];
4308 
4309 	u8    reserved_at_e0[0x6a0];
4310 
4311 	union {
4312 		DECLARE_FLEX_ARRAY(struct mlx5_ifc_rq_num_bits, rq_num);
4313 		DECLARE_FLEX_ARRAY(struct mlx5_ifc_rq_vhca_bits, rq_vhca);
4314 	};
4315 };
4316 
4317 enum {
4318 	MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE  = 0x0,
4319 	MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP     = 0x1,
4320 };
4321 
4322 enum {
4323 	MLX5_RQC_STATE_RST  = 0x0,
4324 	MLX5_RQC_STATE_RDY  = 0x1,
4325 	MLX5_RQC_STATE_ERR  = 0x3,
4326 };
4327 
4328 enum {
4329 	MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_BYTE    = 0x0,
4330 	MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_STRIDE  = 0x1,
4331 	MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_PAGE    = 0x2,
4332 };
4333 
4334 enum {
4335 	MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_NO_MATCH    = 0x0,
4336 	MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_EXTENDED    = 0x1,
4337 	MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_FIVE_TUPLE  = 0x2,
4338 };
4339 
4340 struct mlx5_ifc_rqc_bits {
4341 	u8         rlky[0x1];
4342 	u8	   delay_drop_en[0x1];
4343 	u8         scatter_fcs[0x1];
4344 	u8         vsd[0x1];
4345 	u8         mem_rq_type[0x4];
4346 	u8         state[0x4];
4347 	u8         reserved_at_c[0x1];
4348 	u8         flush_in_error_en[0x1];
4349 	u8         hairpin[0x1];
4350 	u8         reserved_at_f[0xb];
4351 	u8	   ts_format[0x2];
4352 	u8	   reserved_at_1c[0x4];
4353 
4354 	u8         reserved_at_20[0x8];
4355 	u8         user_index[0x18];
4356 
4357 	u8         reserved_at_40[0x8];
4358 	u8         cqn[0x18];
4359 
4360 	u8         counter_set_id[0x8];
4361 	u8         reserved_at_68[0x18];
4362 
4363 	u8         reserved_at_80[0x8];
4364 	u8         rmpn[0x18];
4365 
4366 	u8         reserved_at_a0[0x8];
4367 	u8         hairpin_peer_sq[0x18];
4368 
4369 	u8         reserved_at_c0[0x10];
4370 	u8         hairpin_peer_vhca[0x10];
4371 
4372 	u8         reserved_at_e0[0x46];
4373 	u8         shampo_no_match_alignment_granularity[0x2];
4374 	u8         reserved_at_128[0x6];
4375 	u8         shampo_match_criteria_type[0x2];
4376 	u8         reservation_timeout[0x10];
4377 
4378 	u8         reserved_at_140[0x40];
4379 
4380 	struct mlx5_ifc_wq_bits wq;
4381 };
4382 
4383 enum {
4384 	MLX5_RMPC_STATE_RDY  = 0x1,
4385 	MLX5_RMPC_STATE_ERR  = 0x3,
4386 };
4387 
4388 struct mlx5_ifc_rmpc_bits {
4389 	u8         reserved_at_0[0x8];
4390 	u8         state[0x4];
4391 	u8         reserved_at_c[0x14];
4392 
4393 	u8         basic_cyclic_rcv_wqe[0x1];
4394 	u8         reserved_at_21[0x1f];
4395 
4396 	u8         reserved_at_40[0x140];
4397 
4398 	struct mlx5_ifc_wq_bits wq;
4399 };
4400 
4401 enum {
4402 	VHCA_ID_TYPE_HW = 0,
4403 	VHCA_ID_TYPE_SW = 1,
4404 };
4405 
4406 struct mlx5_ifc_nic_vport_context_bits {
4407 	u8         reserved_at_0[0x5];
4408 	u8         min_wqe_inline_mode[0x3];
4409 	u8         reserved_at_8[0x15];
4410 	u8         disable_mc_local_lb[0x1];
4411 	u8         disable_uc_local_lb[0x1];
4412 	u8         roce_en[0x1];
4413 
4414 	u8         arm_change_event[0x1];
4415 	u8         reserved_at_21[0x1a];
4416 	u8         event_on_mtu[0x1];
4417 	u8         event_on_promisc_change[0x1];
4418 	u8         event_on_vlan_change[0x1];
4419 	u8         event_on_mc_address_change[0x1];
4420 	u8         event_on_uc_address_change[0x1];
4421 
4422 	u8         vhca_id_type[0x1];
4423 	u8         reserved_at_41[0xb];
4424 	u8	   affiliation_criteria[0x4];
4425 	u8	   affiliated_vhca_id[0x10];
4426 
4427 	u8	   reserved_at_60[0xa0];
4428 
4429 	u8	   reserved_at_100[0x1];
4430 	u8         sd_group[0x3];
4431 	u8	   reserved_at_104[0x1c];
4432 
4433 	u8	   reserved_at_120[0x10];
4434 	u8         mtu[0x10];
4435 
4436 	u8         system_image_guid[0x40];
4437 	u8         port_guid[0x40];
4438 	u8         node_guid[0x40];
4439 
4440 	u8         reserved_at_200[0x140];
4441 	u8         qkey_violation_counter[0x10];
4442 	u8         reserved_at_350[0x430];
4443 
4444 	u8         promisc_uc[0x1];
4445 	u8         promisc_mc[0x1];
4446 	u8         promisc_all[0x1];
4447 	u8         reserved_at_783[0x2];
4448 	u8         allowed_list_type[0x3];
4449 	u8         reserved_at_788[0xc];
4450 	u8         allowed_list_size[0xc];
4451 
4452 	struct mlx5_ifc_mac_address_layout_bits permanent_address;
4453 
4454 	u8         reserved_at_7e0[0x20];
4455 
4456 	u8         current_uc_mac_address[][0x40];
4457 };
4458 
4459 enum {
4460 	MLX5_MKC_ACCESS_MODE_PA    = 0x0,
4461 	MLX5_MKC_ACCESS_MODE_MTT   = 0x1,
4462 	MLX5_MKC_ACCESS_MODE_KLMS  = 0x2,
4463 	MLX5_MKC_ACCESS_MODE_KSM   = 0x3,
4464 	MLX5_MKC_ACCESS_MODE_SW_ICM = 0x4,
4465 	MLX5_MKC_ACCESS_MODE_MEMIC = 0x5,
4466 	MLX5_MKC_ACCESS_MODE_CROSSING = 0x6,
4467 };
4468 
4469 enum {
4470 	MLX5_MKC_PCIE_TPH_NO_STEERING_TAG_INDEX = 0,
4471 };
4472 
4473 struct mlx5_ifc_mkc_bits {
4474 	u8         reserved_at_0[0x1];
4475 	u8         free[0x1];
4476 	u8         reserved_at_2[0x1];
4477 	u8         access_mode_4_2[0x3];
4478 	u8         reserved_at_6[0x7];
4479 	u8         relaxed_ordering_write[0x1];
4480 	u8         reserved_at_e[0x1];
4481 	u8         small_fence_on_rdma_read_response[0x1];
4482 	u8         umr_en[0x1];
4483 	u8         a[0x1];
4484 	u8         rw[0x1];
4485 	u8         rr[0x1];
4486 	u8         lw[0x1];
4487 	u8         lr[0x1];
4488 	u8         access_mode_1_0[0x2];
4489 	u8         reserved_at_18[0x2];
4490 	u8         ma_translation_mode[0x2];
4491 	u8         reserved_at_1c[0x4];
4492 
4493 	u8         qpn[0x18];
4494 	u8         mkey_7_0[0x8];
4495 
4496 	u8         reserved_at_40[0x20];
4497 
4498 	u8         length64[0x1];
4499 	u8         bsf_en[0x1];
4500 	u8         sync_umr[0x1];
4501 	u8         reserved_at_63[0x2];
4502 	u8         expected_sigerr_count[0x1];
4503 	u8         reserved_at_66[0x1];
4504 	u8         en_rinval[0x1];
4505 	u8         pd[0x18];
4506 
4507 	u8         start_addr[0x40];
4508 
4509 	u8         len[0x40];
4510 
4511 	u8         bsf_octword_size[0x20];
4512 
4513 	u8         reserved_at_120[0x60];
4514 
4515 	u8         crossing_target_vhca_id[0x10];
4516 	u8         reserved_at_190[0x10];
4517 
4518 	u8         translations_octword_size[0x20];
4519 
4520 	u8         reserved_at_1c0[0x19];
4521 	u8         relaxed_ordering_read[0x1];
4522 	u8         log_page_size[0x6];
4523 
4524 	u8         reserved_at_1e0[0x5];
4525 	u8         pcie_tph_en[0x1];
4526 	u8         pcie_tph_ph[0x2];
4527 	u8         pcie_tph_steering_tag_index[0x8];
4528 	u8         reserved_at_1f0[0x10];
4529 };
4530 
4531 struct mlx5_ifc_pkey_bits {
4532 	u8         reserved_at_0[0x10];
4533 	u8         pkey[0x10];
4534 };
4535 
4536 struct mlx5_ifc_array128_auto_bits {
4537 	u8         array128_auto[16][0x8];
4538 };
4539 
4540 struct mlx5_ifc_hca_vport_context_bits {
4541 	u8         field_select[0x20];
4542 
4543 	u8         reserved_at_20[0xe0];
4544 
4545 	u8         sm_virt_aware[0x1];
4546 	u8         has_smi[0x1];
4547 	u8         has_raw[0x1];
4548 	u8         grh_required[0x1];
4549 	u8         reserved_at_104[0x4];
4550 	u8         num_port_plane[0x8];
4551 	u8         port_physical_state[0x4];
4552 	u8         vport_state_policy[0x4];
4553 	u8         port_state[0x4];
4554 	u8         vport_state[0x4];
4555 
4556 	u8         reserved_at_120[0x20];
4557 
4558 	u8         system_image_guid[0x40];
4559 
4560 	u8         port_guid[0x40];
4561 
4562 	u8         node_guid[0x40];
4563 
4564 	u8         cap_mask1[0x20];
4565 
4566 	u8         cap_mask1_field_select[0x20];
4567 
4568 	u8         cap_mask2[0x20];
4569 
4570 	u8         cap_mask2_field_select[0x20];
4571 
4572 	u8         reserved_at_280[0x80];
4573 
4574 	u8         lid[0x10];
4575 	u8         reserved_at_310[0x4];
4576 	u8         init_type_reply[0x4];
4577 	u8         lmc[0x3];
4578 	u8         subnet_timeout[0x5];
4579 
4580 	u8         sm_lid[0x10];
4581 	u8         sm_sl[0x4];
4582 	u8         reserved_at_334[0xc];
4583 
4584 	u8         qkey_violation_counter[0x10];
4585 	u8         pkey_violation_counter[0x10];
4586 
4587 	u8         reserved_at_360[0xca0];
4588 };
4589 
4590 struct mlx5_ifc_esw_vport_context_bits {
4591 	u8         fdb_to_vport_reg_c[0x1];
4592 	u8         reserved_at_1[0x2];
4593 	u8         vport_svlan_strip[0x1];
4594 	u8         vport_cvlan_strip[0x1];
4595 	u8         vport_svlan_insert[0x1];
4596 	u8         vport_cvlan_insert[0x2];
4597 	u8         fdb_to_vport_reg_c_id[0x8];
4598 	u8         reserved_at_10[0x10];
4599 
4600 	u8         reserved_at_20[0x20];
4601 
4602 	u8         svlan_cfi[0x1];
4603 	u8         svlan_pcp[0x3];
4604 	u8         svlan_id[0xc];
4605 	u8         cvlan_cfi[0x1];
4606 	u8         cvlan_pcp[0x3];
4607 	u8         cvlan_id[0xc];
4608 
4609 	u8         reserved_at_60[0x720];
4610 
4611 	u8         sw_steering_vport_icm_address_rx[0x40];
4612 
4613 	u8         sw_steering_vport_icm_address_tx[0x40];
4614 };
4615 
4616 enum {
4617 	MLX5_EQC_STATUS_OK                = 0x0,
4618 	MLX5_EQC_STATUS_EQ_WRITE_FAILURE  = 0xa,
4619 };
4620 
4621 enum {
4622 	MLX5_EQC_ST_ARMED  = 0x9,
4623 	MLX5_EQC_ST_FIRED  = 0xa,
4624 };
4625 
4626 struct mlx5_ifc_eqc_bits {
4627 	u8         status[0x4];
4628 	u8         reserved_at_4[0x9];
4629 	u8         ec[0x1];
4630 	u8         oi[0x1];
4631 	u8         reserved_at_f[0x5];
4632 	u8         st[0x4];
4633 	u8         reserved_at_18[0x8];
4634 
4635 	u8         reserved_at_20[0x20];
4636 
4637 	u8         reserved_at_40[0x14];
4638 	u8         page_offset[0x6];
4639 	u8         reserved_at_5a[0x6];
4640 
4641 	u8         reserved_at_60[0x3];
4642 	u8         log_eq_size[0x5];
4643 	u8         uar_page[0x18];
4644 
4645 	u8         reserved_at_80[0x20];
4646 
4647 	u8         reserved_at_a0[0x14];
4648 	u8         intr[0xc];
4649 
4650 	u8         reserved_at_c0[0x3];
4651 	u8         log_page_size[0x5];
4652 	u8         reserved_at_c8[0x18];
4653 
4654 	u8         reserved_at_e0[0x60];
4655 
4656 	u8         reserved_at_140[0x8];
4657 	u8         consumer_counter[0x18];
4658 
4659 	u8         reserved_at_160[0x8];
4660 	u8         producer_counter[0x18];
4661 
4662 	u8         reserved_at_180[0x80];
4663 };
4664 
4665 enum {
4666 	MLX5_DCTC_STATE_ACTIVE    = 0x0,
4667 	MLX5_DCTC_STATE_DRAINING  = 0x1,
4668 	MLX5_DCTC_STATE_DRAINED   = 0x2,
4669 };
4670 
4671 enum {
4672 	MLX5_DCTC_CS_RES_DISABLE    = 0x0,
4673 	MLX5_DCTC_CS_RES_NA         = 0x1,
4674 	MLX5_DCTC_CS_RES_UP_TO_64B  = 0x2,
4675 };
4676 
4677 enum {
4678 	MLX5_DCTC_MTU_256_BYTES  = 0x1,
4679 	MLX5_DCTC_MTU_512_BYTES  = 0x2,
4680 	MLX5_DCTC_MTU_1K_BYTES   = 0x3,
4681 	MLX5_DCTC_MTU_2K_BYTES   = 0x4,
4682 	MLX5_DCTC_MTU_4K_BYTES   = 0x5,
4683 };
4684 
4685 struct mlx5_ifc_dctc_bits {
4686 	u8         reserved_at_0[0x4];
4687 	u8         state[0x4];
4688 	u8         reserved_at_8[0x18];
4689 
4690 	u8         reserved_at_20[0x7];
4691 	u8         dp_ordering_force[0x1];
4692 	u8         user_index[0x18];
4693 
4694 	u8         reserved_at_40[0x8];
4695 	u8         cqn[0x18];
4696 
4697 	u8         counter_set_id[0x8];
4698 	u8         atomic_mode[0x4];
4699 	u8         rre[0x1];
4700 	u8         rwe[0x1];
4701 	u8         rae[0x1];
4702 	u8         atomic_like_write_en[0x1];
4703 	u8         latency_sensitive[0x1];
4704 	u8         rlky[0x1];
4705 	u8         free_ar[0x1];
4706 	u8         reserved_at_73[0x1];
4707 	u8         dp_ordering_1[0x1];
4708 	u8         reserved_at_75[0xb];
4709 
4710 	u8         reserved_at_80[0x8];
4711 	u8         cs_res[0x8];
4712 	u8         reserved_at_90[0x3];
4713 	u8         min_rnr_nak[0x5];
4714 	u8         reserved_at_98[0x8];
4715 
4716 	u8         reserved_at_a0[0x8];
4717 	u8         srqn_xrqn[0x18];
4718 
4719 	u8         reserved_at_c0[0x8];
4720 	u8         pd[0x18];
4721 
4722 	u8         tclass[0x8];
4723 	u8         reserved_at_e8[0x4];
4724 	u8         flow_label[0x14];
4725 
4726 	u8         dc_access_key[0x40];
4727 
4728 	u8         reserved_at_140[0x5];
4729 	u8         mtu[0x3];
4730 	u8         port[0x8];
4731 	u8         pkey_index[0x10];
4732 
4733 	u8         reserved_at_160[0x8];
4734 	u8         my_addr_index[0x8];
4735 	u8         reserved_at_170[0x8];
4736 	u8         hop_limit[0x8];
4737 
4738 	u8         dc_access_key_violation_count[0x20];
4739 
4740 	u8         reserved_at_1a0[0x14];
4741 	u8         dei_cfi[0x1];
4742 	u8         eth_prio[0x3];
4743 	u8         ecn[0x2];
4744 	u8         dscp[0x6];
4745 
4746 	u8         reserved_at_1c0[0x20];
4747 	u8         ece[0x20];
4748 };
4749 
4750 enum {
4751 	MLX5_CQC_STATUS_OK             = 0x0,
4752 	MLX5_CQC_STATUS_CQ_OVERFLOW    = 0x9,
4753 	MLX5_CQC_STATUS_CQ_WRITE_FAIL  = 0xa,
4754 };
4755 
4756 enum {
4757 	MLX5_CQC_CQE_SZ_64_BYTES   = 0x0,
4758 	MLX5_CQC_CQE_SZ_128_BYTES  = 0x1,
4759 };
4760 
4761 enum {
4762 	MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED  = 0x6,
4763 	MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED            = 0x9,
4764 	MLX5_CQC_ST_FIRED                                 = 0xa,
4765 };
4766 
4767 enum mlx5_cq_period_mode {
4768 	MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0,
4769 	MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1,
4770 	MLX5_CQ_PERIOD_NUM_MODES,
4771 };
4772 
4773 struct mlx5_ifc_cqc_bits {
4774 	u8         status[0x4];
4775 	u8         reserved_at_4[0x2];
4776 	u8         dbr_umem_valid[0x1];
4777 	u8         apu_cq[0x1];
4778 	u8         cqe_sz[0x3];
4779 	u8         cc[0x1];
4780 	u8         reserved_at_c[0x1];
4781 	u8         scqe_break_moderation_en[0x1];
4782 	u8         oi[0x1];
4783 	u8         cq_period_mode[0x2];
4784 	u8         cqe_comp_en[0x1];
4785 	u8         mini_cqe_res_format[0x2];
4786 	u8         st[0x4];
4787 	u8         reserved_at_18[0x6];
4788 	u8         cqe_compression_layout[0x2];
4789 
4790 	u8         reserved_at_20[0x20];
4791 
4792 	u8         reserved_at_40[0x14];
4793 	u8         page_offset[0x6];
4794 	u8         reserved_at_5a[0x6];
4795 
4796 	u8         reserved_at_60[0x3];
4797 	u8         log_cq_size[0x5];
4798 	u8         uar_page[0x18];
4799 
4800 	u8         reserved_at_80[0x4];
4801 	u8         cq_period[0xc];
4802 	u8         cq_max_count[0x10];
4803 
4804 	u8         c_eqn_or_apu_element[0x20];
4805 
4806 	u8         reserved_at_c0[0x3];
4807 	u8         log_page_size[0x5];
4808 	u8         reserved_at_c8[0x18];
4809 
4810 	u8         reserved_at_e0[0x20];
4811 
4812 	u8         reserved_at_100[0x8];
4813 	u8         last_notified_index[0x18];
4814 
4815 	u8         reserved_at_120[0x8];
4816 	u8         last_solicit_index[0x18];
4817 
4818 	u8         reserved_at_140[0x8];
4819 	u8         consumer_counter[0x18];
4820 
4821 	u8         reserved_at_160[0x8];
4822 	u8         producer_counter[0x18];
4823 
4824 	u8         reserved_at_180[0x40];
4825 
4826 	u8         dbr_addr[0x40];
4827 };
4828 
4829 union mlx5_ifc_cong_control_roce_ecn_auto_bits {
4830 	struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
4831 	struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
4832 	struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
4833 	struct mlx5_ifc_cong_control_r_roce_general_bits cong_control_r_roce_general;
4834 	u8         reserved_at_0[0x800];
4835 };
4836 
4837 struct mlx5_ifc_query_adapter_param_block_bits {
4838 	u8         reserved_at_0[0xc0];
4839 
4840 	u8         reserved_at_c0[0x8];
4841 	u8         ieee_vendor_id[0x18];
4842 
4843 	u8         reserved_at_e0[0x10];
4844 	u8         vsd_vendor_id[0x10];
4845 
4846 	u8         vsd[208][0x8];
4847 
4848 	u8         vsd_contd_psid[16][0x8];
4849 };
4850 
4851 enum {
4852 	MLX5_XRQC_STATE_GOOD   = 0x0,
4853 	MLX5_XRQC_STATE_ERROR  = 0x1,
4854 };
4855 
4856 enum {
4857 	MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0,
4858 	MLX5_XRQC_TOPOLOGY_TAG_MATCHING        = 0x1,
4859 };
4860 
4861 enum {
4862 	MLX5_XRQC_OFFLOAD_RNDV = 0x1,
4863 };
4864 
4865 struct mlx5_ifc_tag_matching_topology_context_bits {
4866 	u8         log_matching_list_sz[0x4];
4867 	u8         reserved_at_4[0xc];
4868 	u8         append_next_index[0x10];
4869 
4870 	u8         sw_phase_cnt[0x10];
4871 	u8         hw_phase_cnt[0x10];
4872 
4873 	u8         reserved_at_40[0x40];
4874 };
4875 
4876 struct mlx5_ifc_xrqc_bits {
4877 	u8         state[0x4];
4878 	u8         rlkey[0x1];
4879 	u8         reserved_at_5[0xf];
4880 	u8         topology[0x4];
4881 	u8         reserved_at_18[0x4];
4882 	u8         offload[0x4];
4883 
4884 	u8         reserved_at_20[0x8];
4885 	u8         user_index[0x18];
4886 
4887 	u8         reserved_at_40[0x8];
4888 	u8         cqn[0x18];
4889 
4890 	u8         reserved_at_60[0xa0];
4891 
4892 	struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context;
4893 
4894 	u8         reserved_at_180[0x280];
4895 
4896 	struct mlx5_ifc_wq_bits wq;
4897 };
4898 
4899 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits {
4900 	struct mlx5_ifc_modify_field_select_bits modify_field_select;
4901 	struct mlx5_ifc_resize_field_select_bits resize_field_select;
4902 	u8         reserved_at_0[0x20];
4903 };
4904 
4905 union mlx5_ifc_field_select_802_1_r_roce_auto_bits {
4906 	struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp;
4907 	struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp;
4908 	struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np;
4909 	u8         reserved_at_0[0x20];
4910 };
4911 
4912 struct mlx5_ifc_rs_histogram_cntrs_bits {
4913 	u8         hist[16][0x40];
4914 	u8         reserved_at_400[0x2c0];
4915 };
4916 
4917 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
4918 	struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
4919 	struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
4920 	struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
4921 	struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
4922 	struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
4923 	struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
4924 	struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout;
4925 	struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout;
4926 	struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
4927 	struct mlx5_ifc_ib_ext_port_cntrs_grp_data_layout_bits ib_ext_port_cntrs_grp_data_layout;
4928 	struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
4929 	struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs;
4930 	struct mlx5_ifc_phys_layer_recovery_cntrs_bits phys_layer_recovery_cntrs;
4931 	struct mlx5_ifc_rs_histogram_cntrs_bits rs_histogram_cntrs;
4932 	u8         reserved_at_0[0x7c0];
4933 };
4934 
4935 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits {
4936 	struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout;
4937 	u8         reserved_at_0[0x7c0];
4938 };
4939 
4940 union mlx5_ifc_event_auto_bits {
4941 	struct mlx5_ifc_comp_event_bits comp_event;
4942 	struct mlx5_ifc_dct_events_bits dct_events;
4943 	struct mlx5_ifc_qp_events_bits qp_events;
4944 	struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event;
4945 	struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event;
4946 	struct mlx5_ifc_cq_error_bits cq_error;
4947 	struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged;
4948 	struct mlx5_ifc_port_state_change_event_bits port_state_change_event;
4949 	struct mlx5_ifc_gpio_event_bits gpio_event;
4950 	struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event;
4951 	struct mlx5_ifc_stall_vl_event_bits stall_vl_event;
4952 	struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event;
4953 	u8         reserved_at_0[0xe0];
4954 };
4955 
4956 struct mlx5_ifc_health_buffer_bits {
4957 	u8         reserved_at_0[0x100];
4958 
4959 	u8         assert_existptr[0x20];
4960 
4961 	u8         assert_callra[0x20];
4962 
4963 	u8         reserved_at_140[0x20];
4964 
4965 	u8         time[0x20];
4966 
4967 	u8         fw_version[0x20];
4968 
4969 	u8         hw_id[0x20];
4970 
4971 	u8         rfr[0x1];
4972 	u8         reserved_at_1c1[0x3];
4973 	u8         valid[0x1];
4974 	u8         severity[0x3];
4975 	u8         reserved_at_1c8[0x18];
4976 
4977 	u8         irisc_index[0x8];
4978 	u8         synd[0x8];
4979 	u8         ext_synd[0x10];
4980 };
4981 
4982 struct mlx5_ifc_register_loopback_control_bits {
4983 	u8         no_lb[0x1];
4984 	u8         reserved_at_1[0x7];
4985 	u8         port[0x8];
4986 	u8         reserved_at_10[0x10];
4987 
4988 	u8         reserved_at_20[0x60];
4989 };
4990 
4991 enum {
4992 	MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0,
4993 	MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1,
4994 };
4995 
4996 struct mlx5_ifc_teardown_hca_out_bits {
4997 	u8         status[0x8];
4998 	u8         reserved_at_8[0x18];
4999 
5000 	u8         syndrome[0x20];
5001 
5002 	u8         reserved_at_40[0x3f];
5003 
5004 	u8         state[0x1];
5005 };
5006 
5007 enum {
5008 	MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE  = 0x0,
5009 	MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE     = 0x1,
5010 	MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN = 0x2,
5011 };
5012 
5013 struct mlx5_ifc_teardown_hca_in_bits {
5014 	u8         opcode[0x10];
5015 	u8         reserved_at_10[0x10];
5016 
5017 	u8         reserved_at_20[0x10];
5018 	u8         op_mod[0x10];
5019 
5020 	u8         reserved_at_40[0x10];
5021 	u8         profile[0x10];
5022 
5023 	u8         reserved_at_60[0x20];
5024 };
5025 
5026 struct mlx5_ifc_sqerr2rts_qp_out_bits {
5027 	u8         status[0x8];
5028 	u8         reserved_at_8[0x18];
5029 
5030 	u8         syndrome[0x20];
5031 
5032 	u8         reserved_at_40[0x40];
5033 };
5034 
5035 struct mlx5_ifc_sqerr2rts_qp_in_bits {
5036 	u8         opcode[0x10];
5037 	u8         uid[0x10];
5038 
5039 	u8         reserved_at_20[0x10];
5040 	u8         op_mod[0x10];
5041 
5042 	u8         reserved_at_40[0x8];
5043 	u8         qpn[0x18];
5044 
5045 	u8         reserved_at_60[0x20];
5046 
5047 	u8         opt_param_mask[0x20];
5048 
5049 	u8         reserved_at_a0[0x20];
5050 
5051 	struct mlx5_ifc_qpc_bits qpc;
5052 
5053 	u8         reserved_at_800[0x80];
5054 };
5055 
5056 struct mlx5_ifc_sqd2rts_qp_out_bits {
5057 	u8         status[0x8];
5058 	u8         reserved_at_8[0x18];
5059 
5060 	u8         syndrome[0x20];
5061 
5062 	u8         reserved_at_40[0x40];
5063 };
5064 
5065 struct mlx5_ifc_sqd2rts_qp_in_bits {
5066 	u8         opcode[0x10];
5067 	u8         uid[0x10];
5068 
5069 	u8         reserved_at_20[0x10];
5070 	u8         op_mod[0x10];
5071 
5072 	u8         reserved_at_40[0x8];
5073 	u8         qpn[0x18];
5074 
5075 	u8         reserved_at_60[0x20];
5076 
5077 	u8         opt_param_mask[0x20];
5078 
5079 	u8         reserved_at_a0[0x20];
5080 
5081 	struct mlx5_ifc_qpc_bits qpc;
5082 
5083 	u8         reserved_at_800[0x80];
5084 };
5085 
5086 struct mlx5_ifc_set_roce_address_out_bits {
5087 	u8         status[0x8];
5088 	u8         reserved_at_8[0x18];
5089 
5090 	u8         syndrome[0x20];
5091 
5092 	u8         reserved_at_40[0x40];
5093 };
5094 
5095 struct mlx5_ifc_set_roce_address_in_bits {
5096 	u8         opcode[0x10];
5097 	u8         reserved_at_10[0x10];
5098 
5099 	u8         reserved_at_20[0x10];
5100 	u8         op_mod[0x10];
5101 
5102 	u8         roce_address_index[0x10];
5103 	u8         reserved_at_50[0xc];
5104 	u8	   vhca_port_num[0x4];
5105 
5106 	u8         reserved_at_60[0x20];
5107 
5108 	struct mlx5_ifc_roce_addr_layout_bits roce_address;
5109 };
5110 
5111 struct mlx5_ifc_set_mad_demux_out_bits {
5112 	u8         status[0x8];
5113 	u8         reserved_at_8[0x18];
5114 
5115 	u8         syndrome[0x20];
5116 
5117 	u8         reserved_at_40[0x40];
5118 };
5119 
5120 enum {
5121 	MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL   = 0x0,
5122 	MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE  = 0x2,
5123 };
5124 
5125 struct mlx5_ifc_set_mad_demux_in_bits {
5126 	u8         opcode[0x10];
5127 	u8         reserved_at_10[0x10];
5128 
5129 	u8         reserved_at_20[0x10];
5130 	u8         op_mod[0x10];
5131 
5132 	u8         reserved_at_40[0x20];
5133 
5134 	u8         reserved_at_60[0x6];
5135 	u8         demux_mode[0x2];
5136 	u8         reserved_at_68[0x18];
5137 };
5138 
5139 struct mlx5_ifc_set_l2_table_entry_out_bits {
5140 	u8         status[0x8];
5141 	u8         reserved_at_8[0x18];
5142 
5143 	u8         syndrome[0x20];
5144 
5145 	u8         reserved_at_40[0x40];
5146 };
5147 
5148 struct mlx5_ifc_set_l2_table_entry_in_bits {
5149 	u8         opcode[0x10];
5150 	u8         reserved_at_10[0x10];
5151 
5152 	u8         reserved_at_20[0x10];
5153 	u8         op_mod[0x10];
5154 
5155 	u8         reserved_at_40[0x60];
5156 
5157 	u8         reserved_at_a0[0x8];
5158 	u8         table_index[0x18];
5159 
5160 	u8         reserved_at_c0[0x20];
5161 
5162 	u8         reserved_at_e0[0x10];
5163 	u8         silent_mode_valid[0x1];
5164 	u8         silent_mode[0x1];
5165 	u8         reserved_at_f2[0x1];
5166 	u8         vlan_valid[0x1];
5167 	u8         vlan[0xc];
5168 
5169 	struct mlx5_ifc_mac_address_layout_bits mac_address;
5170 
5171 	u8         reserved_at_140[0xc0];
5172 };
5173 
5174 struct mlx5_ifc_set_issi_out_bits {
5175 	u8         status[0x8];
5176 	u8         reserved_at_8[0x18];
5177 
5178 	u8         syndrome[0x20];
5179 
5180 	u8         reserved_at_40[0x40];
5181 };
5182 
5183 struct mlx5_ifc_set_issi_in_bits {
5184 	u8         opcode[0x10];
5185 	u8         reserved_at_10[0x10];
5186 
5187 	u8         reserved_at_20[0x10];
5188 	u8         op_mod[0x10];
5189 
5190 	u8         reserved_at_40[0x10];
5191 	u8         current_issi[0x10];
5192 
5193 	u8         reserved_at_60[0x20];
5194 };
5195 
5196 struct mlx5_ifc_set_hca_cap_out_bits {
5197 	u8         status[0x8];
5198 	u8         reserved_at_8[0x18];
5199 
5200 	u8         syndrome[0x20];
5201 
5202 	u8         reserved_at_40[0x40];
5203 };
5204 
5205 struct mlx5_ifc_set_hca_cap_in_bits {
5206 	u8         opcode[0x10];
5207 	u8         reserved_at_10[0x10];
5208 
5209 	u8         reserved_at_20[0x10];
5210 	u8         op_mod[0x10];
5211 
5212 	u8         other_function[0x1];
5213 	u8         ec_vf_function[0x1];
5214 	u8         reserved_at_42[0x1];
5215 	u8         function_id_type[0x1];
5216 	u8         reserved_at_44[0xc];
5217 	u8         function_id[0x10];
5218 
5219 	u8         reserved_at_60[0x20];
5220 
5221 	union mlx5_ifc_hca_cap_union_bits capability;
5222 };
5223 
5224 enum {
5225 	MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION    = 0x0,
5226 	MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG  = 0x1,
5227 	MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST    = 0x2,
5228 	MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS    = 0x3,
5229 	MLX5_SET_FTE_MODIFY_ENABLE_MASK_IPSEC_OBJ_ID    = 0x4
5230 };
5231 
5232 struct mlx5_ifc_set_fte_out_bits {
5233 	u8         status[0x8];
5234 	u8         reserved_at_8[0x18];
5235 
5236 	u8         syndrome[0x20];
5237 
5238 	u8         reserved_at_40[0x40];
5239 };
5240 
5241 struct mlx5_ifc_set_fte_in_bits {
5242 	u8         opcode[0x10];
5243 	u8         reserved_at_10[0x10];
5244 
5245 	u8         reserved_at_20[0x10];
5246 	u8         op_mod[0x10];
5247 
5248 	u8         other_vport[0x1];
5249 	u8         reserved_at_41[0xf];
5250 	u8         vport_number[0x10];
5251 
5252 	u8         reserved_at_60[0x20];
5253 
5254 	u8         table_type[0x8];
5255 	u8         reserved_at_88[0x18];
5256 
5257 	u8         reserved_at_a0[0x8];
5258 	u8         table_id[0x18];
5259 
5260 	u8         ignore_flow_level[0x1];
5261 	u8         reserved_at_c1[0x17];
5262 	u8         modify_enable_mask[0x8];
5263 
5264 	u8         reserved_at_e0[0x20];
5265 
5266 	u8         flow_index[0x20];
5267 
5268 	u8         reserved_at_120[0xe0];
5269 
5270 	struct mlx5_ifc_flow_context_bits flow_context;
5271 };
5272 
5273 struct mlx5_ifc_dest_format_bits {
5274 	u8         destination_type[0x8];
5275 	u8         destination_id[0x18];
5276 
5277 	u8         destination_eswitch_owner_vhca_id_valid[0x1];
5278 	u8         packet_reformat[0x1];
5279 	u8         reserved_at_22[0xe];
5280 	u8         destination_eswitch_owner_vhca_id[0x10];
5281 };
5282 
5283 struct mlx5_ifc_rts2rts_qp_out_bits {
5284 	u8         status[0x8];
5285 	u8         reserved_at_8[0x18];
5286 
5287 	u8         syndrome[0x20];
5288 
5289 	u8         reserved_at_40[0x20];
5290 	u8         ece[0x20];
5291 };
5292 
5293 struct mlx5_ifc_rts2rts_qp_in_bits {
5294 	u8         opcode[0x10];
5295 	u8         uid[0x10];
5296 
5297 	u8         reserved_at_20[0x10];
5298 	u8         op_mod[0x10];
5299 
5300 	u8         reserved_at_40[0x8];
5301 	u8         qpn[0x18];
5302 
5303 	u8         reserved_at_60[0x20];
5304 
5305 	u8         opt_param_mask[0x20];
5306 
5307 	u8         ece[0x20];
5308 
5309 	struct mlx5_ifc_qpc_bits qpc;
5310 
5311 	u8         reserved_at_800[0x80];
5312 };
5313 
5314 struct mlx5_ifc_rtr2rts_qp_out_bits {
5315 	u8         status[0x8];
5316 	u8         reserved_at_8[0x18];
5317 
5318 	u8         syndrome[0x20];
5319 
5320 	u8         reserved_at_40[0x20];
5321 	u8         ece[0x20];
5322 };
5323 
5324 struct mlx5_ifc_rtr2rts_qp_in_bits {
5325 	u8         opcode[0x10];
5326 	u8         uid[0x10];
5327 
5328 	u8         reserved_at_20[0x10];
5329 	u8         op_mod[0x10];
5330 
5331 	u8         reserved_at_40[0x8];
5332 	u8         qpn[0x18];
5333 
5334 	u8         reserved_at_60[0x20];
5335 
5336 	u8         opt_param_mask[0x20];
5337 
5338 	u8         ece[0x20];
5339 
5340 	struct mlx5_ifc_qpc_bits qpc;
5341 
5342 	u8         reserved_at_800[0x80];
5343 };
5344 
5345 struct mlx5_ifc_rst2init_qp_out_bits {
5346 	u8         status[0x8];
5347 	u8         reserved_at_8[0x18];
5348 
5349 	u8         syndrome[0x20];
5350 
5351 	u8         reserved_at_40[0x20];
5352 	u8         ece[0x20];
5353 };
5354 
5355 struct mlx5_ifc_rst2init_qp_in_bits {
5356 	u8         opcode[0x10];
5357 	u8         uid[0x10];
5358 
5359 	u8         reserved_at_20[0x10];
5360 	u8         op_mod[0x10];
5361 
5362 	u8         reserved_at_40[0x8];
5363 	u8         qpn[0x18];
5364 
5365 	u8         reserved_at_60[0x20];
5366 
5367 	u8         opt_param_mask[0x20];
5368 
5369 	u8         ece[0x20];
5370 
5371 	struct mlx5_ifc_qpc_bits qpc;
5372 
5373 	u8         reserved_at_800[0x80];
5374 };
5375 
5376 struct mlx5_ifc_query_xrq_out_bits {
5377 	u8         status[0x8];
5378 	u8         reserved_at_8[0x18];
5379 
5380 	u8         syndrome[0x20];
5381 
5382 	u8         reserved_at_40[0x40];
5383 
5384 	struct mlx5_ifc_xrqc_bits xrq_context;
5385 };
5386 
5387 struct mlx5_ifc_query_xrq_in_bits {
5388 	u8         opcode[0x10];
5389 	u8         reserved_at_10[0x10];
5390 
5391 	u8         reserved_at_20[0x10];
5392 	u8         op_mod[0x10];
5393 
5394 	u8         reserved_at_40[0x8];
5395 	u8         xrqn[0x18];
5396 
5397 	u8         reserved_at_60[0x20];
5398 };
5399 
5400 struct mlx5_ifc_query_xrc_srq_out_bits {
5401 	u8         status[0x8];
5402 	u8         reserved_at_8[0x18];
5403 
5404 	u8         syndrome[0x20];
5405 
5406 	u8         reserved_at_40[0x40];
5407 
5408 	struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
5409 
5410 	u8         reserved_at_280[0x600];
5411 
5412 	u8         pas[][0x40];
5413 };
5414 
5415 struct mlx5_ifc_query_xrc_srq_in_bits {
5416 	u8         opcode[0x10];
5417 	u8         reserved_at_10[0x10];
5418 
5419 	u8         reserved_at_20[0x10];
5420 	u8         op_mod[0x10];
5421 
5422 	u8         reserved_at_40[0x8];
5423 	u8         xrc_srqn[0x18];
5424 
5425 	u8         reserved_at_60[0x20];
5426 };
5427 
5428 enum {
5429 	MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN  = 0x0,
5430 	MLX5_QUERY_VPORT_STATE_OUT_STATE_UP    = 0x1,
5431 };
5432 
5433 struct mlx5_ifc_query_vport_state_out_bits {
5434 	u8         status[0x8];
5435 	u8         reserved_at_8[0x18];
5436 
5437 	u8         syndrome[0x20];
5438 
5439 	u8         reserved_at_40[0x20];
5440 
5441 	u8         reserved_at_60[0x18];
5442 	u8         admin_state[0x4];
5443 	u8         state[0x4];
5444 };
5445 
5446 struct mlx5_ifc_array1024_auto_bits {
5447 	u8         array1024_auto[32][0x20];
5448 };
5449 
5450 struct mlx5_ifc_query_vuid_in_bits {
5451 	u8         opcode[0x10];
5452 	u8         uid[0x10];
5453 
5454 	u8         reserved_at_20[0x40];
5455 
5456 	u8         query_vfs_vuid[0x1];
5457 	u8         data_direct[0x1];
5458 	u8         reserved_at_62[0xe];
5459 	u8         vhca_id[0x10];
5460 };
5461 
5462 struct mlx5_ifc_query_vuid_out_bits {
5463 	u8        status[0x8];
5464 	u8        reserved_at_8[0x18];
5465 
5466 	u8        syndrome[0x20];
5467 
5468 	u8        reserved_at_40[0x1a0];
5469 
5470 	u8        reserved_at_1e0[0x10];
5471 	u8        num_of_entries[0x10];
5472 
5473 	struct mlx5_ifc_array1024_auto_bits vuid[];
5474 };
5475 
5476 enum {
5477 	MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT  = 0x0,
5478 	MLX5_VPORT_STATE_OP_MOD_ESW_VPORT   = 0x1,
5479 	MLX5_VPORT_STATE_OP_MOD_UPLINK      = 0x2,
5480 };
5481 
5482 struct mlx5_ifc_arm_monitor_counter_in_bits {
5483 	u8         opcode[0x10];
5484 	u8         uid[0x10];
5485 
5486 	u8         reserved_at_20[0x10];
5487 	u8         op_mod[0x10];
5488 
5489 	u8         reserved_at_40[0x20];
5490 
5491 	u8         reserved_at_60[0x20];
5492 };
5493 
5494 struct mlx5_ifc_arm_monitor_counter_out_bits {
5495 	u8         status[0x8];
5496 	u8         reserved_at_8[0x18];
5497 
5498 	u8         syndrome[0x20];
5499 
5500 	u8         reserved_at_40[0x40];
5501 };
5502 
5503 enum {
5504 	MLX5_QUERY_MONITOR_CNT_TYPE_PPCNT     = 0x0,
5505 	MLX5_QUERY_MONITOR_CNT_TYPE_Q_COUNTER = 0x1,
5506 };
5507 
5508 enum mlx5_monitor_counter_ppcnt {
5509 	MLX5_QUERY_MONITOR_PPCNT_IN_RANGE_LENGTH_ERRORS      = 0x0,
5510 	MLX5_QUERY_MONITOR_PPCNT_OUT_OF_RANGE_LENGTH_FIELD   = 0x1,
5511 	MLX5_QUERY_MONITOR_PPCNT_FRAME_TOO_LONG_ERRORS       = 0x2,
5512 	MLX5_QUERY_MONITOR_PPCNT_FRAME_CHECK_SEQUENCE_ERRORS = 0x3,
5513 	MLX5_QUERY_MONITOR_PPCNT_ALIGNMENT_ERRORS            = 0x4,
5514 	MLX5_QUERY_MONITOR_PPCNT_IF_OUT_DISCARDS             = 0x5,
5515 };
5516 
5517 enum {
5518 	MLX5_QUERY_MONITOR_Q_COUNTER_RX_OUT_OF_BUFFER     = 0x4,
5519 };
5520 
5521 struct mlx5_ifc_monitor_counter_output_bits {
5522 	u8         reserved_at_0[0x4];
5523 	u8         type[0x4];
5524 	u8         reserved_at_8[0x8];
5525 	u8         counter[0x10];
5526 
5527 	u8         counter_group_id[0x20];
5528 };
5529 
5530 #define MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 (6)
5531 #define MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1    (1)
5532 #define MLX5_CMD_SET_MONITOR_NUM_COUNTER (MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 +\
5533 					  MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1)
5534 
5535 struct mlx5_ifc_set_monitor_counter_in_bits {
5536 	u8         opcode[0x10];
5537 	u8         uid[0x10];
5538 
5539 	u8         reserved_at_20[0x10];
5540 	u8         op_mod[0x10];
5541 
5542 	u8         reserved_at_40[0x10];
5543 	u8         num_of_counters[0x10];
5544 
5545 	u8         reserved_at_60[0x20];
5546 
5547 	struct mlx5_ifc_monitor_counter_output_bits monitor_counter[MLX5_CMD_SET_MONITOR_NUM_COUNTER];
5548 };
5549 
5550 struct mlx5_ifc_set_monitor_counter_out_bits {
5551 	u8         status[0x8];
5552 	u8         reserved_at_8[0x18];
5553 
5554 	u8         syndrome[0x20];
5555 
5556 	u8         reserved_at_40[0x40];
5557 };
5558 
5559 struct mlx5_ifc_query_vport_state_in_bits {
5560 	u8         opcode[0x10];
5561 	u8         reserved_at_10[0x10];
5562 
5563 	u8         reserved_at_20[0x10];
5564 	u8         op_mod[0x10];
5565 
5566 	u8         other_vport[0x1];
5567 	u8         reserved_at_41[0xf];
5568 	u8         vport_number[0x10];
5569 
5570 	u8         reserved_at_60[0x20];
5571 };
5572 
5573 struct mlx5_ifc_query_vnic_env_out_bits {
5574 	u8         status[0x8];
5575 	u8         reserved_at_8[0x18];
5576 
5577 	u8         syndrome[0x20];
5578 
5579 	u8         reserved_at_40[0x40];
5580 
5581 	struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env;
5582 };
5583 
5584 enum {
5585 	MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS  = 0x0,
5586 };
5587 
5588 struct mlx5_ifc_query_vnic_env_in_bits {
5589 	u8         opcode[0x10];
5590 	u8         reserved_at_10[0x10];
5591 
5592 	u8         reserved_at_20[0x10];
5593 	u8         op_mod[0x10];
5594 
5595 	u8         other_vport[0x1];
5596 	u8         reserved_at_41[0xf];
5597 	u8         vport_number[0x10];
5598 
5599 	u8         reserved_at_60[0x20];
5600 };
5601 
5602 struct mlx5_ifc_query_vport_counter_out_bits {
5603 	u8         status[0x8];
5604 	u8         reserved_at_8[0x18];
5605 
5606 	u8         syndrome[0x20];
5607 
5608 	u8         reserved_at_40[0x40];
5609 
5610 	struct mlx5_ifc_traffic_counter_bits received_errors;
5611 
5612 	struct mlx5_ifc_traffic_counter_bits transmit_errors;
5613 
5614 	struct mlx5_ifc_traffic_counter_bits received_ib_unicast;
5615 
5616 	struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast;
5617 
5618 	struct mlx5_ifc_traffic_counter_bits received_ib_multicast;
5619 
5620 	struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast;
5621 
5622 	struct mlx5_ifc_traffic_counter_bits received_eth_broadcast;
5623 
5624 	struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast;
5625 
5626 	struct mlx5_ifc_traffic_counter_bits received_eth_unicast;
5627 
5628 	struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast;
5629 
5630 	struct mlx5_ifc_traffic_counter_bits received_eth_multicast;
5631 
5632 	struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast;
5633 
5634 	struct mlx5_ifc_traffic_counter_bits local_loopback;
5635 
5636 	u8         reserved_at_700[0x980];
5637 };
5638 
5639 enum {
5640 	MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS  = 0x0,
5641 };
5642 
5643 struct mlx5_ifc_query_vport_counter_in_bits {
5644 	u8         opcode[0x10];
5645 	u8         reserved_at_10[0x10];
5646 
5647 	u8         reserved_at_20[0x10];
5648 	u8         op_mod[0x10];
5649 
5650 	u8         other_vport[0x1];
5651 	u8         reserved_at_41[0xb];
5652 	u8	   port_num[0x4];
5653 	u8         vport_number[0x10];
5654 
5655 	u8         reserved_at_60[0x60];
5656 
5657 	u8         clear[0x1];
5658 	u8         reserved_at_c1[0x1f];
5659 
5660 	u8         reserved_at_e0[0x20];
5661 };
5662 
5663 struct mlx5_ifc_query_tis_out_bits {
5664 	u8         status[0x8];
5665 	u8         reserved_at_8[0x18];
5666 
5667 	u8         syndrome[0x20];
5668 
5669 	u8         reserved_at_40[0x40];
5670 
5671 	struct mlx5_ifc_tisc_bits tis_context;
5672 };
5673 
5674 struct mlx5_ifc_query_tis_in_bits {
5675 	u8         opcode[0x10];
5676 	u8         reserved_at_10[0x10];
5677 
5678 	u8         reserved_at_20[0x10];
5679 	u8         op_mod[0x10];
5680 
5681 	u8         reserved_at_40[0x8];
5682 	u8         tisn[0x18];
5683 
5684 	u8         reserved_at_60[0x20];
5685 };
5686 
5687 struct mlx5_ifc_query_tir_out_bits {
5688 	u8         status[0x8];
5689 	u8         reserved_at_8[0x18];
5690 
5691 	u8         syndrome[0x20];
5692 
5693 	u8         reserved_at_40[0xc0];
5694 
5695 	struct mlx5_ifc_tirc_bits tir_context;
5696 };
5697 
5698 struct mlx5_ifc_query_tir_in_bits {
5699 	u8         opcode[0x10];
5700 	u8         reserved_at_10[0x10];
5701 
5702 	u8         reserved_at_20[0x10];
5703 	u8         op_mod[0x10];
5704 
5705 	u8         reserved_at_40[0x8];
5706 	u8         tirn[0x18];
5707 
5708 	u8         reserved_at_60[0x20];
5709 };
5710 
5711 struct mlx5_ifc_query_srq_out_bits {
5712 	u8         status[0x8];
5713 	u8         reserved_at_8[0x18];
5714 
5715 	u8         syndrome[0x20];
5716 
5717 	u8         reserved_at_40[0x40];
5718 
5719 	struct mlx5_ifc_srqc_bits srq_context_entry;
5720 
5721 	u8         reserved_at_280[0x600];
5722 
5723 	u8         pas[][0x40];
5724 };
5725 
5726 struct mlx5_ifc_query_srq_in_bits {
5727 	u8         opcode[0x10];
5728 	u8         reserved_at_10[0x10];
5729 
5730 	u8         reserved_at_20[0x10];
5731 	u8         op_mod[0x10];
5732 
5733 	u8         reserved_at_40[0x8];
5734 	u8         srqn[0x18];
5735 
5736 	u8         reserved_at_60[0x20];
5737 };
5738 
5739 struct mlx5_ifc_query_sq_out_bits {
5740 	u8         status[0x8];
5741 	u8         reserved_at_8[0x18];
5742 
5743 	u8         syndrome[0x20];
5744 
5745 	u8         reserved_at_40[0xc0];
5746 
5747 	struct mlx5_ifc_sqc_bits sq_context;
5748 };
5749 
5750 struct mlx5_ifc_query_sq_in_bits {
5751 	u8         opcode[0x10];
5752 	u8         reserved_at_10[0x10];
5753 
5754 	u8         reserved_at_20[0x10];
5755 	u8         op_mod[0x10];
5756 
5757 	u8         reserved_at_40[0x8];
5758 	u8         sqn[0x18];
5759 
5760 	u8         reserved_at_60[0x20];
5761 };
5762 
5763 struct mlx5_ifc_query_special_contexts_out_bits {
5764 	u8         status[0x8];
5765 	u8         reserved_at_8[0x18];
5766 
5767 	u8         syndrome[0x20];
5768 
5769 	u8         dump_fill_mkey[0x20];
5770 
5771 	u8         resd_lkey[0x20];
5772 
5773 	u8         null_mkey[0x20];
5774 
5775 	u8	   terminate_scatter_list_mkey[0x20];
5776 
5777 	u8	   repeated_mkey[0x20];
5778 
5779 	u8         reserved_at_a0[0x20];
5780 };
5781 
5782 struct mlx5_ifc_query_special_contexts_in_bits {
5783 	u8         opcode[0x10];
5784 	u8         reserved_at_10[0x10];
5785 
5786 	u8         reserved_at_20[0x10];
5787 	u8         op_mod[0x10];
5788 
5789 	u8         reserved_at_40[0x40];
5790 };
5791 
5792 struct mlx5_ifc_query_scheduling_element_out_bits {
5793 	u8         opcode[0x10];
5794 	u8         reserved_at_10[0x10];
5795 
5796 	u8         reserved_at_20[0x10];
5797 	u8         op_mod[0x10];
5798 
5799 	u8         reserved_at_40[0xc0];
5800 
5801 	struct mlx5_ifc_scheduling_context_bits scheduling_context;
5802 
5803 	u8         reserved_at_300[0x100];
5804 };
5805 
5806 enum {
5807 	SCHEDULING_HIERARCHY_E_SWITCH = 0x2,
5808 	SCHEDULING_HIERARCHY_NIC = 0x3,
5809 };
5810 
5811 struct mlx5_ifc_query_scheduling_element_in_bits {
5812 	u8         opcode[0x10];
5813 	u8         reserved_at_10[0x10];
5814 
5815 	u8         reserved_at_20[0x10];
5816 	u8         op_mod[0x10];
5817 
5818 	u8         scheduling_hierarchy[0x8];
5819 	u8         reserved_at_48[0x18];
5820 
5821 	u8         scheduling_element_id[0x20];
5822 
5823 	u8         reserved_at_80[0x180];
5824 };
5825 
5826 struct mlx5_ifc_query_rqt_out_bits {
5827 	u8         status[0x8];
5828 	u8         reserved_at_8[0x18];
5829 
5830 	u8         syndrome[0x20];
5831 
5832 	u8         reserved_at_40[0xc0];
5833 
5834 	struct mlx5_ifc_rqtc_bits rqt_context;
5835 };
5836 
5837 struct mlx5_ifc_query_rqt_in_bits {
5838 	u8         opcode[0x10];
5839 	u8         reserved_at_10[0x10];
5840 
5841 	u8         reserved_at_20[0x10];
5842 	u8         op_mod[0x10];
5843 
5844 	u8         reserved_at_40[0x8];
5845 	u8         rqtn[0x18];
5846 
5847 	u8         reserved_at_60[0x20];
5848 };
5849 
5850 struct mlx5_ifc_query_rq_out_bits {
5851 	u8         status[0x8];
5852 	u8         reserved_at_8[0x18];
5853 
5854 	u8         syndrome[0x20];
5855 
5856 	u8         reserved_at_40[0xc0];
5857 
5858 	struct mlx5_ifc_rqc_bits rq_context;
5859 };
5860 
5861 struct mlx5_ifc_query_rq_in_bits {
5862 	u8         opcode[0x10];
5863 	u8         reserved_at_10[0x10];
5864 
5865 	u8         reserved_at_20[0x10];
5866 	u8         op_mod[0x10];
5867 
5868 	u8         reserved_at_40[0x8];
5869 	u8         rqn[0x18];
5870 
5871 	u8         reserved_at_60[0x20];
5872 };
5873 
5874 struct mlx5_ifc_query_roce_address_out_bits {
5875 	u8         status[0x8];
5876 	u8         reserved_at_8[0x18];
5877 
5878 	u8         syndrome[0x20];
5879 
5880 	u8         reserved_at_40[0x40];
5881 
5882 	struct mlx5_ifc_roce_addr_layout_bits roce_address;
5883 };
5884 
5885 struct mlx5_ifc_query_roce_address_in_bits {
5886 	u8         opcode[0x10];
5887 	u8         reserved_at_10[0x10];
5888 
5889 	u8         reserved_at_20[0x10];
5890 	u8         op_mod[0x10];
5891 
5892 	u8         roce_address_index[0x10];
5893 	u8         reserved_at_50[0xc];
5894 	u8	   vhca_port_num[0x4];
5895 
5896 	u8         reserved_at_60[0x20];
5897 };
5898 
5899 struct mlx5_ifc_query_rmp_out_bits {
5900 	u8         status[0x8];
5901 	u8         reserved_at_8[0x18];
5902 
5903 	u8         syndrome[0x20];
5904 
5905 	u8         reserved_at_40[0xc0];
5906 
5907 	struct mlx5_ifc_rmpc_bits rmp_context;
5908 };
5909 
5910 struct mlx5_ifc_query_rmp_in_bits {
5911 	u8         opcode[0x10];
5912 	u8         reserved_at_10[0x10];
5913 
5914 	u8         reserved_at_20[0x10];
5915 	u8         op_mod[0x10];
5916 
5917 	u8         reserved_at_40[0x8];
5918 	u8         rmpn[0x18];
5919 
5920 	u8         reserved_at_60[0x20];
5921 };
5922 
5923 struct mlx5_ifc_cqe_error_syndrome_bits {
5924 	u8         hw_error_syndrome[0x8];
5925 	u8         hw_syndrome_type[0x4];
5926 	u8         reserved_at_c[0x4];
5927 	u8         vendor_error_syndrome[0x8];
5928 	u8         syndrome[0x8];
5929 };
5930 
5931 struct mlx5_ifc_qp_context_extension_bits {
5932 	u8         reserved_at_0[0x60];
5933 
5934 	struct mlx5_ifc_cqe_error_syndrome_bits error_syndrome;
5935 
5936 	u8         reserved_at_80[0x580];
5937 };
5938 
5939 struct mlx5_ifc_qpc_extension_and_pas_list_in_bits {
5940 	struct mlx5_ifc_qp_context_extension_bits qpc_data_extension;
5941 
5942 	u8         pas[0][0x40];
5943 };
5944 
5945 struct mlx5_ifc_qp_pas_list_in_bits {
5946 	struct mlx5_ifc_cmd_pas_bits pas[0];
5947 };
5948 
5949 union mlx5_ifc_qp_pas_or_qpc_ext_and_pas_bits {
5950 	struct mlx5_ifc_qp_pas_list_in_bits qp_pas_list;
5951 	struct mlx5_ifc_qpc_extension_and_pas_list_in_bits qpc_ext_and_pas_list;
5952 };
5953 
5954 struct mlx5_ifc_query_qp_out_bits {
5955 	u8         status[0x8];
5956 	u8         reserved_at_8[0x18];
5957 
5958 	u8         syndrome[0x20];
5959 
5960 	u8         reserved_at_40[0x40];
5961 
5962 	u8         opt_param_mask[0x20];
5963 
5964 	u8         ece[0x20];
5965 
5966 	struct mlx5_ifc_qpc_bits qpc;
5967 
5968 	u8         reserved_at_800[0x80];
5969 
5970 	union mlx5_ifc_qp_pas_or_qpc_ext_and_pas_bits qp_pas_or_qpc_ext_and_pas;
5971 };
5972 
5973 struct mlx5_ifc_query_qp_in_bits {
5974 	u8         opcode[0x10];
5975 	u8         reserved_at_10[0x10];
5976 
5977 	u8         reserved_at_20[0x10];
5978 	u8         op_mod[0x10];
5979 
5980 	u8         qpc_ext[0x1];
5981 	u8         reserved_at_41[0x7];
5982 	u8         qpn[0x18];
5983 
5984 	u8         reserved_at_60[0x20];
5985 };
5986 
5987 struct mlx5_ifc_query_q_counter_out_bits {
5988 	u8         status[0x8];
5989 	u8         reserved_at_8[0x18];
5990 
5991 	u8         syndrome[0x20];
5992 
5993 	u8         reserved_at_40[0x40];
5994 
5995 	u8         rx_write_requests[0x20];
5996 
5997 	u8         reserved_at_a0[0x20];
5998 
5999 	u8         rx_read_requests[0x20];
6000 
6001 	u8         reserved_at_e0[0x20];
6002 
6003 	u8         rx_atomic_requests[0x20];
6004 
6005 	u8         reserved_at_120[0x20];
6006 
6007 	u8         rx_dct_connect[0x20];
6008 
6009 	u8         reserved_at_160[0x20];
6010 
6011 	u8         out_of_buffer[0x20];
6012 
6013 	u8         reserved_at_1a0[0x20];
6014 
6015 	u8         out_of_sequence[0x20];
6016 
6017 	u8         reserved_at_1e0[0x20];
6018 
6019 	u8         duplicate_request[0x20];
6020 
6021 	u8         reserved_at_220[0x20];
6022 
6023 	u8         rnr_nak_retry_err[0x20];
6024 
6025 	u8         reserved_at_260[0x20];
6026 
6027 	u8         packet_seq_err[0x20];
6028 
6029 	u8         reserved_at_2a0[0x20];
6030 
6031 	u8         implied_nak_seq_err[0x20];
6032 
6033 	u8         reserved_at_2e0[0x20];
6034 
6035 	u8         local_ack_timeout_err[0x20];
6036 
6037 	u8         reserved_at_320[0x60];
6038 
6039 	u8         req_rnr_retries_exceeded[0x20];
6040 
6041 	u8         reserved_at_3a0[0x20];
6042 
6043 	u8         resp_local_length_error[0x20];
6044 
6045 	u8         req_local_length_error[0x20];
6046 
6047 	u8         resp_local_qp_error[0x20];
6048 
6049 	u8         local_operation_error[0x20];
6050 
6051 	u8         resp_local_protection[0x20];
6052 
6053 	u8         req_local_protection[0x20];
6054 
6055 	u8         resp_cqe_error[0x20];
6056 
6057 	u8         req_cqe_error[0x20];
6058 
6059 	u8         req_mw_binding[0x20];
6060 
6061 	u8         req_bad_response[0x20];
6062 
6063 	u8         req_remote_invalid_request[0x20];
6064 
6065 	u8         resp_remote_invalid_request[0x20];
6066 
6067 	u8         req_remote_access_errors[0x20];
6068 
6069 	u8	   resp_remote_access_errors[0x20];
6070 
6071 	u8         req_remote_operation_errors[0x20];
6072 
6073 	u8         req_transport_retries_exceeded[0x20];
6074 
6075 	u8         cq_overflow[0x20];
6076 
6077 	u8         resp_cqe_flush_error[0x20];
6078 
6079 	u8         req_cqe_flush_error[0x20];
6080 
6081 	u8         reserved_at_620[0x20];
6082 
6083 	u8         roce_adp_retrans[0x20];
6084 
6085 	u8         roce_adp_retrans_to[0x20];
6086 
6087 	u8         roce_slow_restart[0x20];
6088 
6089 	u8         roce_slow_restart_cnps[0x20];
6090 
6091 	u8         roce_slow_restart_trans[0x20];
6092 
6093 	u8         reserved_at_6e0[0x120];
6094 };
6095 
6096 struct mlx5_ifc_query_q_counter_in_bits {
6097 	u8         opcode[0x10];
6098 	u8         reserved_at_10[0x10];
6099 
6100 	u8         reserved_at_20[0x10];
6101 	u8         op_mod[0x10];
6102 
6103 	u8         other_vport[0x1];
6104 	u8         reserved_at_41[0xf];
6105 	u8         vport_number[0x10];
6106 
6107 	u8         reserved_at_60[0x60];
6108 
6109 	u8         clear[0x1];
6110 	u8         aggregate[0x1];
6111 	u8         reserved_at_c2[0x1e];
6112 
6113 	u8         reserved_at_e0[0x18];
6114 	u8         counter_set_id[0x8];
6115 };
6116 
6117 struct mlx5_ifc_query_pages_out_bits {
6118 	u8         status[0x8];
6119 	u8         reserved_at_8[0x18];
6120 
6121 	u8         syndrome[0x20];
6122 
6123 	u8         embedded_cpu_function[0x1];
6124 	u8         reserved_at_41[0xf];
6125 	u8         function_id[0x10];
6126 
6127 	u8         num_pages[0x20];
6128 };
6129 
6130 enum {
6131 	MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES     = 0x1,
6132 	MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES     = 0x2,
6133 	MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES  = 0x3,
6134 };
6135 
6136 struct mlx5_ifc_query_pages_in_bits {
6137 	u8         opcode[0x10];
6138 	u8         reserved_at_10[0x10];
6139 
6140 	u8         reserved_at_20[0x10];
6141 	u8         op_mod[0x10];
6142 
6143 	u8         embedded_cpu_function[0x1];
6144 	u8         reserved_at_41[0xf];
6145 	u8         function_id[0x10];
6146 
6147 	u8         reserved_at_60[0x20];
6148 };
6149 
6150 struct mlx5_ifc_query_nic_vport_context_out_bits {
6151 	u8         status[0x8];
6152 	u8         reserved_at_8[0x18];
6153 
6154 	u8         syndrome[0x20];
6155 
6156 	u8         reserved_at_40[0x40];
6157 
6158 	struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
6159 };
6160 
6161 struct mlx5_ifc_query_nic_vport_context_in_bits {
6162 	u8         opcode[0x10];
6163 	u8         reserved_at_10[0x10];
6164 
6165 	u8         reserved_at_20[0x10];
6166 	u8         op_mod[0x10];
6167 
6168 	u8         other_vport[0x1];
6169 	u8         reserved_at_41[0xf];
6170 	u8         vport_number[0x10];
6171 
6172 	u8         reserved_at_60[0x5];
6173 	u8         allowed_list_type[0x3];
6174 	u8         reserved_at_68[0x18];
6175 };
6176 
6177 struct mlx5_ifc_query_mkey_out_bits {
6178 	u8         status[0x8];
6179 	u8         reserved_at_8[0x18];
6180 
6181 	u8         syndrome[0x20];
6182 
6183 	u8         reserved_at_40[0x40];
6184 
6185 	struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
6186 
6187 	u8         reserved_at_280[0x600];
6188 
6189 	u8         bsf0_klm0_pas_mtt0_1[16][0x8];
6190 
6191 	u8         bsf1_klm1_pas_mtt2_3[16][0x8];
6192 };
6193 
6194 struct mlx5_ifc_query_mkey_in_bits {
6195 	u8         opcode[0x10];
6196 	u8         reserved_at_10[0x10];
6197 
6198 	u8         reserved_at_20[0x10];
6199 	u8         op_mod[0x10];
6200 
6201 	u8         reserved_at_40[0x8];
6202 	u8         mkey_index[0x18];
6203 
6204 	u8         pg_access[0x1];
6205 	u8         reserved_at_61[0x1f];
6206 };
6207 
6208 struct mlx5_ifc_query_mad_demux_out_bits {
6209 	u8         status[0x8];
6210 	u8         reserved_at_8[0x18];
6211 
6212 	u8         syndrome[0x20];
6213 
6214 	u8         reserved_at_40[0x40];
6215 
6216 	u8         mad_dumux_parameters_block[0x20];
6217 };
6218 
6219 struct mlx5_ifc_query_mad_demux_in_bits {
6220 	u8         opcode[0x10];
6221 	u8         reserved_at_10[0x10];
6222 
6223 	u8         reserved_at_20[0x10];
6224 	u8         op_mod[0x10];
6225 
6226 	u8         reserved_at_40[0x40];
6227 };
6228 
6229 struct mlx5_ifc_query_l2_table_entry_out_bits {
6230 	u8         status[0x8];
6231 	u8         reserved_at_8[0x18];
6232 
6233 	u8         syndrome[0x20];
6234 
6235 	u8         reserved_at_40[0xa0];
6236 
6237 	u8         reserved_at_e0[0x13];
6238 	u8         vlan_valid[0x1];
6239 	u8         vlan[0xc];
6240 
6241 	struct mlx5_ifc_mac_address_layout_bits mac_address;
6242 
6243 	u8         reserved_at_140[0xc0];
6244 };
6245 
6246 struct mlx5_ifc_query_l2_table_entry_in_bits {
6247 	u8         opcode[0x10];
6248 	u8         reserved_at_10[0x10];
6249 
6250 	u8         reserved_at_20[0x10];
6251 	u8         op_mod[0x10];
6252 
6253 	u8         reserved_at_40[0x60];
6254 
6255 	u8         reserved_at_a0[0x8];
6256 	u8         table_index[0x18];
6257 
6258 	u8         reserved_at_c0[0x140];
6259 };
6260 
6261 struct mlx5_ifc_query_issi_out_bits {
6262 	u8         status[0x8];
6263 	u8         reserved_at_8[0x18];
6264 
6265 	u8         syndrome[0x20];
6266 
6267 	u8         reserved_at_40[0x10];
6268 	u8         current_issi[0x10];
6269 
6270 	u8         reserved_at_60[0xa0];
6271 
6272 	u8         reserved_at_100[76][0x8];
6273 	u8         supported_issi_dw0[0x20];
6274 };
6275 
6276 struct mlx5_ifc_query_issi_in_bits {
6277 	u8         opcode[0x10];
6278 	u8         reserved_at_10[0x10];
6279 
6280 	u8         reserved_at_20[0x10];
6281 	u8         op_mod[0x10];
6282 
6283 	u8         reserved_at_40[0x40];
6284 };
6285 
6286 struct mlx5_ifc_set_driver_version_out_bits {
6287 	u8         status[0x8];
6288 	u8         reserved_0[0x18];
6289 
6290 	u8         syndrome[0x20];
6291 	u8         reserved_1[0x40];
6292 };
6293 
6294 struct mlx5_ifc_set_driver_version_in_bits {
6295 	u8         opcode[0x10];
6296 	u8         reserved_0[0x10];
6297 
6298 	u8         reserved_1[0x10];
6299 	u8         op_mod[0x10];
6300 
6301 	u8         reserved_2[0x40];
6302 	u8         driver_version[64][0x8];
6303 };
6304 
6305 struct mlx5_ifc_query_hca_vport_pkey_out_bits {
6306 	u8         status[0x8];
6307 	u8         reserved_at_8[0x18];
6308 
6309 	u8         syndrome[0x20];
6310 
6311 	u8         reserved_at_40[0x40];
6312 
6313 	struct mlx5_ifc_pkey_bits pkey[];
6314 };
6315 
6316 struct mlx5_ifc_query_hca_vport_pkey_in_bits {
6317 	u8         opcode[0x10];
6318 	u8         reserved_at_10[0x10];
6319 
6320 	u8         reserved_at_20[0x10];
6321 	u8         op_mod[0x10];
6322 
6323 	u8         other_vport[0x1];
6324 	u8         reserved_at_41[0xb];
6325 	u8         port_num[0x4];
6326 	u8         vport_number[0x10];
6327 
6328 	u8         reserved_at_60[0x10];
6329 	u8         pkey_index[0x10];
6330 };
6331 
6332 enum {
6333 	MLX5_HCA_VPORT_SEL_PORT_GUID	= 1 << 0,
6334 	MLX5_HCA_VPORT_SEL_NODE_GUID	= 1 << 1,
6335 	MLX5_HCA_VPORT_SEL_STATE_POLICY	= 1 << 2,
6336 };
6337 
6338 struct mlx5_ifc_query_hca_vport_gid_out_bits {
6339 	u8         status[0x8];
6340 	u8         reserved_at_8[0x18];
6341 
6342 	u8         syndrome[0x20];
6343 
6344 	u8         reserved_at_40[0x20];
6345 
6346 	u8         gids_num[0x10];
6347 	u8         reserved_at_70[0x10];
6348 
6349 	struct mlx5_ifc_array128_auto_bits gid[];
6350 };
6351 
6352 struct mlx5_ifc_query_hca_vport_gid_in_bits {
6353 	u8         opcode[0x10];
6354 	u8         reserved_at_10[0x10];
6355 
6356 	u8         reserved_at_20[0x10];
6357 	u8         op_mod[0x10];
6358 
6359 	u8         other_vport[0x1];
6360 	u8         reserved_at_41[0xb];
6361 	u8         port_num[0x4];
6362 	u8         vport_number[0x10];
6363 
6364 	u8         reserved_at_60[0x10];
6365 	u8         gid_index[0x10];
6366 };
6367 
6368 struct mlx5_ifc_query_hca_vport_context_out_bits {
6369 	u8         status[0x8];
6370 	u8         reserved_at_8[0x18];
6371 
6372 	u8         syndrome[0x20];
6373 
6374 	u8         reserved_at_40[0x40];
6375 
6376 	struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
6377 };
6378 
6379 struct mlx5_ifc_query_hca_vport_context_in_bits {
6380 	u8         opcode[0x10];
6381 	u8         reserved_at_10[0x10];
6382 
6383 	u8         reserved_at_20[0x10];
6384 	u8         op_mod[0x10];
6385 
6386 	u8         other_vport[0x1];
6387 	u8         reserved_at_41[0xb];
6388 	u8         port_num[0x4];
6389 	u8         vport_number[0x10];
6390 
6391 	u8         reserved_at_60[0x20];
6392 };
6393 
6394 struct mlx5_ifc_query_hca_cap_out_bits {
6395 	u8         status[0x8];
6396 	u8         reserved_at_8[0x18];
6397 
6398 	u8         syndrome[0x20];
6399 
6400 	u8         reserved_at_40[0x40];
6401 
6402 	union mlx5_ifc_hca_cap_union_bits capability;
6403 };
6404 
6405 struct mlx5_ifc_query_hca_cap_in_bits {
6406 	u8         opcode[0x10];
6407 	u8         reserved_at_10[0x10];
6408 
6409 	u8         reserved_at_20[0x10];
6410 	u8         op_mod[0x10];
6411 
6412 	u8         other_function[0x1];
6413 	u8         ec_vf_function[0x1];
6414 	u8         reserved_at_42[0x1];
6415 	u8         function_id_type[0x1];
6416 	u8         reserved_at_44[0xc];
6417 	u8         function_id[0x10];
6418 
6419 	u8         reserved_at_60[0x20];
6420 };
6421 
6422 struct mlx5_ifc_other_hca_cap_bits {
6423 	u8         roce[0x1];
6424 	u8         reserved_at_1[0x27f];
6425 };
6426 
6427 struct mlx5_ifc_query_other_hca_cap_out_bits {
6428 	u8         status[0x8];
6429 	u8         reserved_at_8[0x18];
6430 
6431 	u8         syndrome[0x20];
6432 
6433 	u8         reserved_at_40[0x40];
6434 
6435 	struct     mlx5_ifc_other_hca_cap_bits other_capability;
6436 };
6437 
6438 struct mlx5_ifc_query_other_hca_cap_in_bits {
6439 	u8         opcode[0x10];
6440 	u8         reserved_at_10[0x10];
6441 
6442 	u8         reserved_at_20[0x10];
6443 	u8         op_mod[0x10];
6444 
6445 	u8         reserved_at_40[0x10];
6446 	u8         function_id[0x10];
6447 
6448 	u8         reserved_at_60[0x20];
6449 };
6450 
6451 struct mlx5_ifc_modify_other_hca_cap_out_bits {
6452 	u8         status[0x8];
6453 	u8         reserved_at_8[0x18];
6454 
6455 	u8         syndrome[0x20];
6456 
6457 	u8         reserved_at_40[0x40];
6458 };
6459 
6460 struct mlx5_ifc_modify_other_hca_cap_in_bits {
6461 	u8         opcode[0x10];
6462 	u8         reserved_at_10[0x10];
6463 
6464 	u8         reserved_at_20[0x10];
6465 	u8         op_mod[0x10];
6466 
6467 	u8         reserved_at_40[0x10];
6468 	u8         function_id[0x10];
6469 	u8         field_select[0x20];
6470 
6471 	struct     mlx5_ifc_other_hca_cap_bits other_capability;
6472 };
6473 
6474 struct mlx5_ifc_sw_owner_icm_root_params_bits {
6475 	u8         sw_owner_icm_root_1[0x40];
6476 
6477 	u8         sw_owner_icm_root_0[0x40];
6478 };
6479 
6480 struct mlx5_ifc_rtc_params_bits {
6481 	u8         rtc_id_0[0x20];
6482 
6483 	u8         rtc_id_1[0x20];
6484 
6485 	u8         reserved_at_40[0x40];
6486 };
6487 
6488 struct mlx5_ifc_flow_table_context_bits {
6489 	u8         reformat_en[0x1];
6490 	u8         decap_en[0x1];
6491 	u8         sw_owner[0x1];
6492 	u8         termination_table[0x1];
6493 	u8         table_miss_action[0x4];
6494 	u8         level[0x8];
6495 	u8         rtc_valid[0x1];
6496 	u8         reserved_at_11[0x7];
6497 	u8         log_size[0x8];
6498 
6499 	u8         reserved_at_20[0x8];
6500 	u8         table_miss_id[0x18];
6501 
6502 	u8         reserved_at_40[0x8];
6503 	u8         lag_master_next_table_id[0x18];
6504 
6505 	u8         reserved_at_60[0x60];
6506 
6507 	union {
6508 		struct mlx5_ifc_sw_owner_icm_root_params_bits sws;
6509 		struct mlx5_ifc_rtc_params_bits hws;
6510 	};
6511 };
6512 
6513 struct mlx5_ifc_query_flow_table_out_bits {
6514 	u8         status[0x8];
6515 	u8         reserved_at_8[0x18];
6516 
6517 	u8         syndrome[0x20];
6518 
6519 	u8         reserved_at_40[0x80];
6520 
6521 	struct mlx5_ifc_flow_table_context_bits flow_table_context;
6522 };
6523 
6524 struct mlx5_ifc_query_flow_table_in_bits {
6525 	u8         opcode[0x10];
6526 	u8         reserved_at_10[0x10];
6527 
6528 	u8         reserved_at_20[0x10];
6529 	u8         op_mod[0x10];
6530 
6531 	u8         reserved_at_40[0x40];
6532 
6533 	u8         table_type[0x8];
6534 	u8         reserved_at_88[0x18];
6535 
6536 	u8         reserved_at_a0[0x8];
6537 	u8         table_id[0x18];
6538 
6539 	u8         reserved_at_c0[0x140];
6540 };
6541 
6542 struct mlx5_ifc_query_fte_out_bits {
6543 	u8         status[0x8];
6544 	u8         reserved_at_8[0x18];
6545 
6546 	u8         syndrome[0x20];
6547 
6548 	u8         reserved_at_40[0x1c0];
6549 
6550 	struct mlx5_ifc_flow_context_bits flow_context;
6551 };
6552 
6553 struct mlx5_ifc_query_fte_in_bits {
6554 	u8         opcode[0x10];
6555 	u8         reserved_at_10[0x10];
6556 
6557 	u8         reserved_at_20[0x10];
6558 	u8         op_mod[0x10];
6559 
6560 	u8         reserved_at_40[0x40];
6561 
6562 	u8         table_type[0x8];
6563 	u8         reserved_at_88[0x18];
6564 
6565 	u8         reserved_at_a0[0x8];
6566 	u8         table_id[0x18];
6567 
6568 	u8         reserved_at_c0[0x40];
6569 
6570 	u8         flow_index[0x20];
6571 
6572 	u8         reserved_at_120[0xe0];
6573 };
6574 
6575 struct mlx5_ifc_match_definer_format_0_bits {
6576 	u8         reserved_at_0[0x100];
6577 
6578 	u8         metadata_reg_c_0[0x20];
6579 
6580 	u8         metadata_reg_c_1[0x20];
6581 
6582 	u8         outer_dmac_47_16[0x20];
6583 
6584 	u8         outer_dmac_15_0[0x10];
6585 	u8         outer_ethertype[0x10];
6586 
6587 	u8         reserved_at_180[0x1];
6588 	u8         sx_sniffer[0x1];
6589 	u8         functional_lb[0x1];
6590 	u8         outer_ip_frag[0x1];
6591 	u8         outer_qp_type[0x2];
6592 	u8         outer_encap_type[0x2];
6593 	u8         port_number[0x2];
6594 	u8         outer_l3_type[0x2];
6595 	u8         outer_l4_type[0x2];
6596 	u8         outer_first_vlan_type[0x2];
6597 	u8         outer_first_vlan_prio[0x3];
6598 	u8         outer_first_vlan_cfi[0x1];
6599 	u8         outer_first_vlan_vid[0xc];
6600 
6601 	u8         outer_l4_type_ext[0x4];
6602 	u8         reserved_at_1a4[0x2];
6603 	u8         outer_ipsec_layer[0x2];
6604 	u8         outer_l2_type[0x2];
6605 	u8         force_lb[0x1];
6606 	u8         outer_l2_ok[0x1];
6607 	u8         outer_l3_ok[0x1];
6608 	u8         outer_l4_ok[0x1];
6609 	u8         outer_second_vlan_type[0x2];
6610 	u8         outer_second_vlan_prio[0x3];
6611 	u8         outer_second_vlan_cfi[0x1];
6612 	u8         outer_second_vlan_vid[0xc];
6613 
6614 	u8         outer_smac_47_16[0x20];
6615 
6616 	u8         outer_smac_15_0[0x10];
6617 	u8         inner_ipv4_checksum_ok[0x1];
6618 	u8         inner_l4_checksum_ok[0x1];
6619 	u8         outer_ipv4_checksum_ok[0x1];
6620 	u8         outer_l4_checksum_ok[0x1];
6621 	u8         inner_l3_ok[0x1];
6622 	u8         inner_l4_ok[0x1];
6623 	u8         outer_l3_ok_duplicate[0x1];
6624 	u8         outer_l4_ok_duplicate[0x1];
6625 	u8         outer_tcp_cwr[0x1];
6626 	u8         outer_tcp_ece[0x1];
6627 	u8         outer_tcp_urg[0x1];
6628 	u8         outer_tcp_ack[0x1];
6629 	u8         outer_tcp_psh[0x1];
6630 	u8         outer_tcp_rst[0x1];
6631 	u8         outer_tcp_syn[0x1];
6632 	u8         outer_tcp_fin[0x1];
6633 };
6634 
6635 struct mlx5_ifc_match_definer_format_22_bits {
6636 	u8         reserved_at_0[0x100];
6637 
6638 	u8         outer_ip_src_addr[0x20];
6639 
6640 	u8         outer_ip_dest_addr[0x20];
6641 
6642 	u8         outer_l4_sport[0x10];
6643 	u8         outer_l4_dport[0x10];
6644 
6645 	u8         reserved_at_160[0x1];
6646 	u8         sx_sniffer[0x1];
6647 	u8         functional_lb[0x1];
6648 	u8         outer_ip_frag[0x1];
6649 	u8         outer_qp_type[0x2];
6650 	u8         outer_encap_type[0x2];
6651 	u8         port_number[0x2];
6652 	u8         outer_l3_type[0x2];
6653 	u8         outer_l4_type[0x2];
6654 	u8         outer_first_vlan_type[0x2];
6655 	u8         outer_first_vlan_prio[0x3];
6656 	u8         outer_first_vlan_cfi[0x1];
6657 	u8         outer_first_vlan_vid[0xc];
6658 
6659 	u8         metadata_reg_c_0[0x20];
6660 
6661 	u8         outer_dmac_47_16[0x20];
6662 
6663 	u8         outer_smac_47_16[0x20];
6664 
6665 	u8         outer_smac_15_0[0x10];
6666 	u8         outer_dmac_15_0[0x10];
6667 };
6668 
6669 struct mlx5_ifc_match_definer_format_23_bits {
6670 	u8         reserved_at_0[0x100];
6671 
6672 	u8         inner_ip_src_addr[0x20];
6673 
6674 	u8         inner_ip_dest_addr[0x20];
6675 
6676 	u8         inner_l4_sport[0x10];
6677 	u8         inner_l4_dport[0x10];
6678 
6679 	u8         reserved_at_160[0x1];
6680 	u8         sx_sniffer[0x1];
6681 	u8         functional_lb[0x1];
6682 	u8         inner_ip_frag[0x1];
6683 	u8         inner_qp_type[0x2];
6684 	u8         inner_encap_type[0x2];
6685 	u8         port_number[0x2];
6686 	u8         inner_l3_type[0x2];
6687 	u8         inner_l4_type[0x2];
6688 	u8         inner_first_vlan_type[0x2];
6689 	u8         inner_first_vlan_prio[0x3];
6690 	u8         inner_first_vlan_cfi[0x1];
6691 	u8         inner_first_vlan_vid[0xc];
6692 
6693 	u8         tunnel_header_0[0x20];
6694 
6695 	u8         inner_dmac_47_16[0x20];
6696 
6697 	u8         inner_smac_47_16[0x20];
6698 
6699 	u8         inner_smac_15_0[0x10];
6700 	u8         inner_dmac_15_0[0x10];
6701 };
6702 
6703 struct mlx5_ifc_match_definer_format_29_bits {
6704 	u8         reserved_at_0[0xc0];
6705 
6706 	u8         outer_ip_dest_addr[0x80];
6707 
6708 	u8         outer_ip_src_addr[0x80];
6709 
6710 	u8         outer_l4_sport[0x10];
6711 	u8         outer_l4_dport[0x10];
6712 
6713 	u8         reserved_at_1e0[0x20];
6714 };
6715 
6716 struct mlx5_ifc_match_definer_format_30_bits {
6717 	u8         reserved_at_0[0xa0];
6718 
6719 	u8         outer_ip_dest_addr[0x80];
6720 
6721 	u8         outer_ip_src_addr[0x80];
6722 
6723 	u8         outer_dmac_47_16[0x20];
6724 
6725 	u8         outer_smac_47_16[0x20];
6726 
6727 	u8         outer_smac_15_0[0x10];
6728 	u8         outer_dmac_15_0[0x10];
6729 };
6730 
6731 struct mlx5_ifc_match_definer_format_31_bits {
6732 	u8         reserved_at_0[0xc0];
6733 
6734 	u8         inner_ip_dest_addr[0x80];
6735 
6736 	u8         inner_ip_src_addr[0x80];
6737 
6738 	u8         inner_l4_sport[0x10];
6739 	u8         inner_l4_dport[0x10];
6740 
6741 	u8         reserved_at_1e0[0x20];
6742 };
6743 
6744 struct mlx5_ifc_match_definer_format_32_bits {
6745 	u8         reserved_at_0[0xa0];
6746 
6747 	u8         inner_ip_dest_addr[0x80];
6748 
6749 	u8         inner_ip_src_addr[0x80];
6750 
6751 	u8         inner_dmac_47_16[0x20];
6752 
6753 	u8         inner_smac_47_16[0x20];
6754 
6755 	u8         inner_smac_15_0[0x10];
6756 	u8         inner_dmac_15_0[0x10];
6757 };
6758 
6759 enum {
6760 	MLX5_IFC_DEFINER_FORMAT_ID_SELECT = 61,
6761 };
6762 
6763 #define MLX5_IFC_DEFINER_FORMAT_OFFSET_UNUSED 0x0
6764 #define MLX5_IFC_DEFINER_FORMAT_OFFSET_OUTER_ETH_PKT_LEN 0x48
6765 #define MLX5_IFC_DEFINER_DW_SELECTORS_NUM 9
6766 #define MLX5_IFC_DEFINER_BYTE_SELECTORS_NUM 8
6767 
6768 struct mlx5_ifc_match_definer_match_mask_bits {
6769 	u8         reserved_at_1c0[5][0x20];
6770 	u8         match_dw_8[0x20];
6771 	u8         match_dw_7[0x20];
6772 	u8         match_dw_6[0x20];
6773 	u8         match_dw_5[0x20];
6774 	u8         match_dw_4[0x20];
6775 	u8         match_dw_3[0x20];
6776 	u8         match_dw_2[0x20];
6777 	u8         match_dw_1[0x20];
6778 	u8         match_dw_0[0x20];
6779 
6780 	u8         match_byte_7[0x8];
6781 	u8         match_byte_6[0x8];
6782 	u8         match_byte_5[0x8];
6783 	u8         match_byte_4[0x8];
6784 
6785 	u8         match_byte_3[0x8];
6786 	u8         match_byte_2[0x8];
6787 	u8         match_byte_1[0x8];
6788 	u8         match_byte_0[0x8];
6789 };
6790 
6791 struct mlx5_ifc_match_definer_bits {
6792 	u8         modify_field_select[0x40];
6793 
6794 	u8         reserved_at_40[0x40];
6795 
6796 	u8         reserved_at_80[0x10];
6797 	u8         format_id[0x10];
6798 
6799 	u8         reserved_at_a0[0x60];
6800 
6801 	u8         format_select_dw3[0x8];
6802 	u8         format_select_dw2[0x8];
6803 	u8         format_select_dw1[0x8];
6804 	u8         format_select_dw0[0x8];
6805 
6806 	u8         format_select_dw7[0x8];
6807 	u8         format_select_dw6[0x8];
6808 	u8         format_select_dw5[0x8];
6809 	u8         format_select_dw4[0x8];
6810 
6811 	u8         reserved_at_100[0x18];
6812 	u8         format_select_dw8[0x8];
6813 
6814 	u8         reserved_at_120[0x20];
6815 
6816 	u8         format_select_byte3[0x8];
6817 	u8         format_select_byte2[0x8];
6818 	u8         format_select_byte1[0x8];
6819 	u8         format_select_byte0[0x8];
6820 
6821 	u8         format_select_byte7[0x8];
6822 	u8         format_select_byte6[0x8];
6823 	u8         format_select_byte5[0x8];
6824 	u8         format_select_byte4[0x8];
6825 
6826 	u8         reserved_at_180[0x40];
6827 
6828 	union {
6829 		struct {
6830 			u8         match_mask[16][0x20];
6831 		};
6832 		struct mlx5_ifc_match_definer_match_mask_bits match_mask_format;
6833 	};
6834 };
6835 
6836 struct mlx5_ifc_general_obj_create_param_bits {
6837 	u8         alias_object[0x1];
6838 	u8         reserved_at_1[0x2];
6839 	u8         log_obj_range[0x5];
6840 	u8         reserved_at_8[0x18];
6841 };
6842 
6843 struct mlx5_ifc_general_obj_query_param_bits {
6844 	u8         alias_object[0x1];
6845 	u8         obj_offset[0x1f];
6846 };
6847 
6848 struct mlx5_ifc_general_obj_in_cmd_hdr_bits {
6849 	u8         opcode[0x10];
6850 	u8         uid[0x10];
6851 
6852 	u8         vhca_tunnel_id[0x10];
6853 	u8         obj_type[0x10];
6854 
6855 	u8         obj_id[0x20];
6856 
6857 	union {
6858 		struct mlx5_ifc_general_obj_create_param_bits create;
6859 		struct mlx5_ifc_general_obj_query_param_bits query;
6860 	} op_param;
6861 };
6862 
6863 struct mlx5_ifc_general_obj_out_cmd_hdr_bits {
6864 	u8         status[0x8];
6865 	u8         reserved_at_8[0x18];
6866 
6867 	u8         syndrome[0x20];
6868 
6869 	u8         obj_id[0x20];
6870 
6871 	u8         reserved_at_60[0x20];
6872 };
6873 
6874 struct mlx5_ifc_allow_other_vhca_access_in_bits {
6875 	u8 opcode[0x10];
6876 	u8 uid[0x10];
6877 	u8 reserved_at_20[0x10];
6878 	u8 op_mod[0x10];
6879 	u8 reserved_at_40[0x50];
6880 	u8 object_type_to_be_accessed[0x10];
6881 	u8 object_id_to_be_accessed[0x20];
6882 	u8 reserved_at_c0[0x40];
6883 	union {
6884 		u8 access_key_raw[0x100];
6885 		u8 access_key[8][0x20];
6886 	};
6887 };
6888 
6889 struct mlx5_ifc_allow_other_vhca_access_out_bits {
6890 	u8 status[0x8];
6891 	u8 reserved_at_8[0x18];
6892 	u8 syndrome[0x20];
6893 	u8 reserved_at_40[0x40];
6894 };
6895 
6896 struct mlx5_ifc_modify_header_arg_bits {
6897 	u8         reserved_at_0[0x80];
6898 
6899 	u8         reserved_at_80[0x8];
6900 	u8         access_pd[0x18];
6901 };
6902 
6903 struct mlx5_ifc_create_modify_header_arg_in_bits {
6904 	struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
6905 	struct mlx5_ifc_modify_header_arg_bits arg;
6906 };
6907 
6908 struct mlx5_ifc_create_match_definer_in_bits {
6909 	struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
6910 
6911 	struct mlx5_ifc_match_definer_bits obj_context;
6912 };
6913 
6914 struct mlx5_ifc_create_match_definer_out_bits {
6915 	struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr;
6916 };
6917 
6918 struct mlx5_ifc_alias_context_bits {
6919 	u8 vhca_id_to_be_accessed[0x10];
6920 	u8 reserved_at_10[0xd];
6921 	u8 status[0x3];
6922 	u8 object_id_to_be_accessed[0x20];
6923 	u8 reserved_at_40[0x40];
6924 	union {
6925 		u8 access_key_raw[0x100];
6926 		u8 access_key[8][0x20];
6927 	};
6928 	u8 metadata[0x80];
6929 };
6930 
6931 struct mlx5_ifc_create_alias_obj_in_bits {
6932 	struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
6933 	struct mlx5_ifc_alias_context_bits alias_ctx;
6934 };
6935 
6936 enum {
6937 	MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS    = 0x0,
6938 	MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS  = 0x1,
6939 	MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS    = 0x2,
6940 	MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3,
6941 	MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_3 = 0x4,
6942 	MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_4 = 0x5,
6943 	MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_5 = 0x6,
6944 };
6945 
6946 struct mlx5_ifc_query_flow_group_out_bits {
6947 	u8         status[0x8];
6948 	u8         reserved_at_8[0x18];
6949 
6950 	u8         syndrome[0x20];
6951 
6952 	u8         reserved_at_40[0xa0];
6953 
6954 	u8         start_flow_index[0x20];
6955 
6956 	u8         reserved_at_100[0x20];
6957 
6958 	u8         end_flow_index[0x20];
6959 
6960 	u8         reserved_at_140[0xa0];
6961 
6962 	u8         reserved_at_1e0[0x18];
6963 	u8         match_criteria_enable[0x8];
6964 
6965 	struct mlx5_ifc_fte_match_param_bits match_criteria;
6966 
6967 	u8         reserved_at_1200[0xe00];
6968 };
6969 
6970 struct mlx5_ifc_query_flow_group_in_bits {
6971 	u8         opcode[0x10];
6972 	u8         reserved_at_10[0x10];
6973 
6974 	u8         reserved_at_20[0x10];
6975 	u8         op_mod[0x10];
6976 
6977 	u8         reserved_at_40[0x40];
6978 
6979 	u8         table_type[0x8];
6980 	u8         reserved_at_88[0x18];
6981 
6982 	u8         reserved_at_a0[0x8];
6983 	u8         table_id[0x18];
6984 
6985 	u8         group_id[0x20];
6986 
6987 	u8         reserved_at_e0[0x120];
6988 };
6989 
6990 struct mlx5_ifc_query_flow_counter_out_bits {
6991 	u8         status[0x8];
6992 	u8         reserved_at_8[0x18];
6993 
6994 	u8         syndrome[0x20];
6995 
6996 	u8         reserved_at_40[0x40];
6997 
6998 	struct mlx5_ifc_traffic_counter_bits flow_statistics[];
6999 };
7000 
7001 struct mlx5_ifc_query_flow_counter_in_bits {
7002 	u8         opcode[0x10];
7003 	u8         reserved_at_10[0x10];
7004 
7005 	u8         reserved_at_20[0x10];
7006 	u8         op_mod[0x10];
7007 
7008 	u8         reserved_at_40[0x80];
7009 
7010 	u8         clear[0x1];
7011 	u8         reserved_at_c1[0xf];
7012 	u8         num_of_counters[0x10];
7013 
7014 	u8         flow_counter_id[0x20];
7015 };
7016 
7017 struct mlx5_ifc_query_esw_vport_context_out_bits {
7018 	u8         status[0x8];
7019 	u8         reserved_at_8[0x18];
7020 
7021 	u8         syndrome[0x20];
7022 
7023 	u8         reserved_at_40[0x40];
7024 
7025 	struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
7026 };
7027 
7028 struct mlx5_ifc_query_esw_vport_context_in_bits {
7029 	u8         opcode[0x10];
7030 	u8         reserved_at_10[0x10];
7031 
7032 	u8         reserved_at_20[0x10];
7033 	u8         op_mod[0x10];
7034 
7035 	u8         other_vport[0x1];
7036 	u8         reserved_at_41[0xf];
7037 	u8         vport_number[0x10];
7038 
7039 	u8         reserved_at_60[0x20];
7040 };
7041 
7042 struct mlx5_ifc_destroy_esw_vport_out_bits {
7043 	u8         status[0x8];
7044 	u8         reserved_at_8[0x18];
7045 
7046 	u8         syndrome[0x20];
7047 
7048 	u8         reserved_at_40[0x20];
7049 };
7050 
7051 struct mlx5_ifc_destroy_esw_vport_in_bits {
7052 	u8         opcode[0x10];
7053 	u8         uid[0x10];
7054 
7055 	u8         reserved_at_20[0x10];
7056 	u8         op_mod[0x10];
7057 
7058 	u8         reserved_at_40[0x10];
7059 	u8         vport_num[0x10];
7060 
7061 	u8         reserved_at_60[0x20];
7062 };
7063 
7064 struct mlx5_ifc_modify_esw_vport_context_out_bits {
7065 	u8         status[0x8];
7066 	u8         reserved_at_8[0x18];
7067 
7068 	u8         syndrome[0x20];
7069 
7070 	u8         reserved_at_40[0x40];
7071 };
7072 
7073 struct mlx5_ifc_esw_vport_context_fields_select_bits {
7074 	u8         reserved_at_0[0x1b];
7075 	u8         fdb_to_vport_reg_c_id[0x1];
7076 	u8         vport_cvlan_insert[0x1];
7077 	u8         vport_svlan_insert[0x1];
7078 	u8         vport_cvlan_strip[0x1];
7079 	u8         vport_svlan_strip[0x1];
7080 };
7081 
7082 struct mlx5_ifc_modify_esw_vport_context_in_bits {
7083 	u8         opcode[0x10];
7084 	u8         reserved_at_10[0x10];
7085 
7086 	u8         reserved_at_20[0x10];
7087 	u8         op_mod[0x10];
7088 
7089 	u8         other_vport[0x1];
7090 	u8         reserved_at_41[0xf];
7091 	u8         vport_number[0x10];
7092 
7093 	struct mlx5_ifc_esw_vport_context_fields_select_bits field_select;
7094 
7095 	struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
7096 };
7097 
7098 struct mlx5_ifc_query_eq_out_bits {
7099 	u8         status[0x8];
7100 	u8         reserved_at_8[0x18];
7101 
7102 	u8         syndrome[0x20];
7103 
7104 	u8         reserved_at_40[0x40];
7105 
7106 	struct mlx5_ifc_eqc_bits eq_context_entry;
7107 
7108 	u8         reserved_at_280[0x40];
7109 
7110 	u8         event_bitmask[0x40];
7111 
7112 	u8         reserved_at_300[0x580];
7113 
7114 	u8         pas[][0x40];
7115 };
7116 
7117 struct mlx5_ifc_query_eq_in_bits {
7118 	u8         opcode[0x10];
7119 	u8         reserved_at_10[0x10];
7120 
7121 	u8         reserved_at_20[0x10];
7122 	u8         op_mod[0x10];
7123 
7124 	u8         reserved_at_40[0x18];
7125 	u8         eq_number[0x8];
7126 
7127 	u8         reserved_at_60[0x20];
7128 };
7129 
7130 struct mlx5_ifc_packet_reformat_context_in_bits {
7131 	u8         reformat_type[0x8];
7132 	u8         reserved_at_8[0x4];
7133 	u8         reformat_param_0[0x4];
7134 	u8         reserved_at_10[0x6];
7135 	u8         reformat_data_size[0xa];
7136 
7137 	u8         reformat_param_1[0x8];
7138 	u8         reserved_at_28[0x8];
7139 	u8         reformat_data[2][0x8];
7140 
7141 	u8         more_reformat_data[][0x8];
7142 };
7143 
7144 struct mlx5_ifc_query_packet_reformat_context_out_bits {
7145 	u8         status[0x8];
7146 	u8         reserved_at_8[0x18];
7147 
7148 	u8         syndrome[0x20];
7149 
7150 	u8         reserved_at_40[0xa0];
7151 
7152 	struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context[];
7153 };
7154 
7155 struct mlx5_ifc_query_packet_reformat_context_in_bits {
7156 	u8         opcode[0x10];
7157 	u8         reserved_at_10[0x10];
7158 
7159 	u8         reserved_at_20[0x10];
7160 	u8         op_mod[0x10];
7161 
7162 	u8         packet_reformat_id[0x20];
7163 
7164 	u8         reserved_at_60[0xa0];
7165 };
7166 
7167 struct mlx5_ifc_alloc_packet_reformat_context_out_bits {
7168 	u8         status[0x8];
7169 	u8         reserved_at_8[0x18];
7170 
7171 	u8         syndrome[0x20];
7172 
7173 	u8         packet_reformat_id[0x20];
7174 
7175 	u8         reserved_at_60[0x20];
7176 };
7177 
7178 enum {
7179 	MLX5_REFORMAT_CONTEXT_ANCHOR_MAC_START = 0x1,
7180 	MLX5_REFORMAT_CONTEXT_ANCHOR_VLAN_START = 0x2,
7181 	MLX5_REFORMAT_CONTEXT_ANCHOR_IP_START = 0x7,
7182 	MLX5_REFORMAT_CONTEXT_ANCHOR_TCP_UDP_START = 0x9,
7183 };
7184 
7185 enum mlx5_reformat_ctx_type {
7186 	MLX5_REFORMAT_TYPE_L2_TO_VXLAN = 0x0,
7187 	MLX5_REFORMAT_TYPE_L2_TO_NVGRE = 0x1,
7188 	MLX5_REFORMAT_TYPE_L2_TO_L2_TUNNEL = 0x2,
7189 	MLX5_REFORMAT_TYPE_L3_TUNNEL_TO_L2 = 0x3,
7190 	MLX5_REFORMAT_TYPE_L2_TO_L3_TUNNEL = 0x4,
7191 	MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_IPV4 = 0x5,
7192 	MLX5_REFORMAT_TYPE_L2_TO_L3_ESP_TUNNEL = 0x6,
7193 	MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_UDPV4 = 0x7,
7194 	MLX5_REFORMAT_TYPE_DEL_ESP_TRANSPORT = 0x8,
7195 	MLX5_REFORMAT_TYPE_L3_ESP_TUNNEL_TO_L2 = 0x9,
7196 	MLX5_REFORMAT_TYPE_DEL_ESP_TRANSPORT_OVER_UDP = 0xa,
7197 	MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_IPV6 = 0xb,
7198 	MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_UDPV6 = 0xc,
7199 	MLX5_REFORMAT_TYPE_ADD_PSP_TUNNEL = 0xd,
7200 	MLX5_REFORMAT_TYPE_DEL_PSP_TUNNEL = 0xe,
7201 	MLX5_REFORMAT_TYPE_INSERT_HDR = 0xf,
7202 	MLX5_REFORMAT_TYPE_REMOVE_HDR = 0x10,
7203 	MLX5_REFORMAT_TYPE_ADD_MACSEC = 0x11,
7204 	MLX5_REFORMAT_TYPE_DEL_MACSEC = 0x12,
7205 };
7206 
7207 struct mlx5_ifc_alloc_packet_reformat_context_in_bits {
7208 	u8         opcode[0x10];
7209 	u8         reserved_at_10[0x10];
7210 
7211 	u8         reserved_at_20[0x10];
7212 	u8         op_mod[0x10];
7213 
7214 	u8         reserved_at_40[0xa0];
7215 
7216 	struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context;
7217 };
7218 
7219 struct mlx5_ifc_dealloc_packet_reformat_context_out_bits {
7220 	u8         status[0x8];
7221 	u8         reserved_at_8[0x18];
7222 
7223 	u8         syndrome[0x20];
7224 
7225 	u8         reserved_at_40[0x40];
7226 };
7227 
7228 struct mlx5_ifc_dealloc_packet_reformat_context_in_bits {
7229 	u8         opcode[0x10];
7230 	u8         reserved_at_10[0x10];
7231 
7232 	u8         reserved_20[0x10];
7233 	u8         op_mod[0x10];
7234 
7235 	u8         packet_reformat_id[0x20];
7236 
7237 	u8         reserved_60[0x20];
7238 };
7239 
7240 struct mlx5_ifc_set_action_in_bits {
7241 	u8         action_type[0x4];
7242 	u8         field[0xc];
7243 	u8         reserved_at_10[0x3];
7244 	u8         offset[0x5];
7245 	u8         reserved_at_18[0x3];
7246 	u8         length[0x5];
7247 
7248 	u8         data[0x20];
7249 };
7250 
7251 struct mlx5_ifc_add_action_in_bits {
7252 	u8         action_type[0x4];
7253 	u8         field[0xc];
7254 	u8         reserved_at_10[0x10];
7255 
7256 	u8         data[0x20];
7257 };
7258 
7259 struct mlx5_ifc_copy_action_in_bits {
7260 	u8         action_type[0x4];
7261 	u8         src_field[0xc];
7262 	u8         reserved_at_10[0x3];
7263 	u8         src_offset[0x5];
7264 	u8         reserved_at_18[0x3];
7265 	u8         length[0x5];
7266 
7267 	u8         reserved_at_20[0x4];
7268 	u8         dst_field[0xc];
7269 	u8         reserved_at_30[0x3];
7270 	u8         dst_offset[0x5];
7271 	u8         reserved_at_38[0x8];
7272 };
7273 
7274 union mlx5_ifc_set_add_copy_action_in_auto_bits {
7275 	struct mlx5_ifc_set_action_in_bits  set_action_in;
7276 	struct mlx5_ifc_add_action_in_bits  add_action_in;
7277 	struct mlx5_ifc_copy_action_in_bits copy_action_in;
7278 	u8         reserved_at_0[0x40];
7279 };
7280 
7281 enum {
7282 	MLX5_ACTION_TYPE_SET   = 0x1,
7283 	MLX5_ACTION_TYPE_ADD   = 0x2,
7284 	MLX5_ACTION_TYPE_COPY  = 0x3,
7285 };
7286 
7287 enum {
7288 	MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16    = 0x1,
7289 	MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0     = 0x2,
7290 	MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE     = 0x3,
7291 	MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16    = 0x4,
7292 	MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0     = 0x5,
7293 	MLX5_ACTION_IN_FIELD_OUT_IP_DSCP       = 0x6,
7294 	MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS     = 0x7,
7295 	MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT     = 0x8,
7296 	MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT     = 0x9,
7297 	MLX5_ACTION_IN_FIELD_OUT_IP_TTL        = 0xa,
7298 	MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT     = 0xb,
7299 	MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT     = 0xc,
7300 	MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96  = 0xd,
7301 	MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64   = 0xe,
7302 	MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32   = 0xf,
7303 	MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0    = 0x10,
7304 	MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96  = 0x11,
7305 	MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64   = 0x12,
7306 	MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32   = 0x13,
7307 	MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0    = 0x14,
7308 	MLX5_ACTION_IN_FIELD_OUT_SIPV4         = 0x15,
7309 	MLX5_ACTION_IN_FIELD_OUT_DIPV4         = 0x16,
7310 	MLX5_ACTION_IN_FIELD_OUT_FIRST_VID     = 0x17,
7311 	MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47,
7312 	MLX5_ACTION_IN_FIELD_METADATA_REG_A    = 0x49,
7313 	MLX5_ACTION_IN_FIELD_METADATA_REG_B    = 0x50,
7314 	MLX5_ACTION_IN_FIELD_METADATA_REG_C_0  = 0x51,
7315 	MLX5_ACTION_IN_FIELD_METADATA_REG_C_1  = 0x52,
7316 	MLX5_ACTION_IN_FIELD_METADATA_REG_C_2  = 0x53,
7317 	MLX5_ACTION_IN_FIELD_METADATA_REG_C_3  = 0x54,
7318 	MLX5_ACTION_IN_FIELD_METADATA_REG_C_4  = 0x55,
7319 	MLX5_ACTION_IN_FIELD_METADATA_REG_C_5  = 0x56,
7320 	MLX5_ACTION_IN_FIELD_METADATA_REG_C_6  = 0x57,
7321 	MLX5_ACTION_IN_FIELD_METADATA_REG_C_7  = 0x58,
7322 	MLX5_ACTION_IN_FIELD_OUT_TCP_SEQ_NUM   = 0x59,
7323 	MLX5_ACTION_IN_FIELD_OUT_TCP_ACK_NUM   = 0x5B,
7324 	MLX5_ACTION_IN_FIELD_IPSEC_SYNDROME    = 0x5D,
7325 	MLX5_ACTION_IN_FIELD_OUT_EMD_47_32     = 0x6F,
7326 	MLX5_ACTION_IN_FIELD_OUT_EMD_31_0      = 0x70,
7327 	MLX5_ACTION_IN_FIELD_PSP_SYNDROME      = 0x71,
7328 };
7329 
7330 struct mlx5_ifc_alloc_modify_header_context_out_bits {
7331 	u8         status[0x8];
7332 	u8         reserved_at_8[0x18];
7333 
7334 	u8         syndrome[0x20];
7335 
7336 	u8         modify_header_id[0x20];
7337 
7338 	u8         reserved_at_60[0x20];
7339 };
7340 
7341 struct mlx5_ifc_alloc_modify_header_context_in_bits {
7342 	u8         opcode[0x10];
7343 	u8         reserved_at_10[0x10];
7344 
7345 	u8         reserved_at_20[0x10];
7346 	u8         op_mod[0x10];
7347 
7348 	u8         reserved_at_40[0x20];
7349 
7350 	u8         table_type[0x8];
7351 	u8         reserved_at_68[0x10];
7352 	u8         num_of_actions[0x8];
7353 
7354 	union mlx5_ifc_set_add_copy_action_in_auto_bits actions[];
7355 };
7356 
7357 struct mlx5_ifc_dealloc_modify_header_context_out_bits {
7358 	u8         status[0x8];
7359 	u8         reserved_at_8[0x18];
7360 
7361 	u8         syndrome[0x20];
7362 
7363 	u8         reserved_at_40[0x40];
7364 };
7365 
7366 struct mlx5_ifc_dealloc_modify_header_context_in_bits {
7367 	u8         opcode[0x10];
7368 	u8         reserved_at_10[0x10];
7369 
7370 	u8         reserved_at_20[0x10];
7371 	u8         op_mod[0x10];
7372 
7373 	u8         modify_header_id[0x20];
7374 
7375 	u8         reserved_at_60[0x20];
7376 };
7377 
7378 struct mlx5_ifc_query_modify_header_context_in_bits {
7379 	u8         opcode[0x10];
7380 	u8         uid[0x10];
7381 
7382 	u8         reserved_at_20[0x10];
7383 	u8         op_mod[0x10];
7384 
7385 	u8         modify_header_id[0x20];
7386 
7387 	u8         reserved_at_60[0xa0];
7388 };
7389 
7390 struct mlx5_ifc_query_dct_out_bits {
7391 	u8         status[0x8];
7392 	u8         reserved_at_8[0x18];
7393 
7394 	u8         syndrome[0x20];
7395 
7396 	u8         reserved_at_40[0x40];
7397 
7398 	struct mlx5_ifc_dctc_bits dct_context_entry;
7399 
7400 	u8         reserved_at_280[0x180];
7401 };
7402 
7403 struct mlx5_ifc_query_dct_in_bits {
7404 	u8         opcode[0x10];
7405 	u8         reserved_at_10[0x10];
7406 
7407 	u8         reserved_at_20[0x10];
7408 	u8         op_mod[0x10];
7409 
7410 	u8         reserved_at_40[0x8];
7411 	u8         dctn[0x18];
7412 
7413 	u8         reserved_at_60[0x20];
7414 };
7415 
7416 struct mlx5_ifc_query_cq_out_bits {
7417 	u8         status[0x8];
7418 	u8         reserved_at_8[0x18];
7419 
7420 	u8         syndrome[0x20];
7421 
7422 	u8         reserved_at_40[0x40];
7423 
7424 	struct mlx5_ifc_cqc_bits cq_context;
7425 
7426 	u8         reserved_at_280[0x600];
7427 
7428 	u8         pas[][0x40];
7429 };
7430 
7431 struct mlx5_ifc_query_cq_in_bits {
7432 	u8         opcode[0x10];
7433 	u8         reserved_at_10[0x10];
7434 
7435 	u8         reserved_at_20[0x10];
7436 	u8         op_mod[0x10];
7437 
7438 	u8         reserved_at_40[0x8];
7439 	u8         cqn[0x18];
7440 
7441 	u8         reserved_at_60[0x20];
7442 };
7443 
7444 struct mlx5_ifc_query_cong_status_out_bits {
7445 	u8         status[0x8];
7446 	u8         reserved_at_8[0x18];
7447 
7448 	u8         syndrome[0x20];
7449 
7450 	u8         reserved_at_40[0x20];
7451 
7452 	u8         enable[0x1];
7453 	u8         tag_enable[0x1];
7454 	u8         reserved_at_62[0x1e];
7455 };
7456 
7457 struct mlx5_ifc_query_cong_status_in_bits {
7458 	u8         opcode[0x10];
7459 	u8         reserved_at_10[0x10];
7460 
7461 	u8         reserved_at_20[0x10];
7462 	u8         op_mod[0x10];
7463 
7464 	u8         reserved_at_40[0x18];
7465 	u8         priority[0x4];
7466 	u8         cong_protocol[0x4];
7467 
7468 	u8         reserved_at_60[0x20];
7469 };
7470 
7471 struct mlx5_ifc_query_cong_statistics_out_bits {
7472 	u8         status[0x8];
7473 	u8         reserved_at_8[0x18];
7474 
7475 	u8         syndrome[0x20];
7476 
7477 	u8         reserved_at_40[0x40];
7478 
7479 	u8         rp_cur_flows[0x20];
7480 
7481 	u8         sum_flows[0x20];
7482 
7483 	u8         rp_cnp_ignored_high[0x20];
7484 
7485 	u8         rp_cnp_ignored_low[0x20];
7486 
7487 	u8         rp_cnp_handled_high[0x20];
7488 
7489 	u8         rp_cnp_handled_low[0x20];
7490 
7491 	u8         reserved_at_140[0x100];
7492 
7493 	u8         time_stamp_high[0x20];
7494 
7495 	u8         time_stamp_low[0x20];
7496 
7497 	u8         accumulators_period[0x20];
7498 
7499 	u8         np_ecn_marked_roce_packets_high[0x20];
7500 
7501 	u8         np_ecn_marked_roce_packets_low[0x20];
7502 
7503 	u8         np_cnp_sent_high[0x20];
7504 
7505 	u8         np_cnp_sent_low[0x20];
7506 
7507 	u8         reserved_at_320[0x560];
7508 };
7509 
7510 struct mlx5_ifc_query_cong_statistics_in_bits {
7511 	u8         opcode[0x10];
7512 	u8         reserved_at_10[0x10];
7513 
7514 	u8         reserved_at_20[0x10];
7515 	u8         op_mod[0x10];
7516 
7517 	u8         clear[0x1];
7518 	u8         reserved_at_41[0x1f];
7519 
7520 	u8         reserved_at_60[0x20];
7521 };
7522 
7523 struct mlx5_ifc_query_cong_params_out_bits {
7524 	u8         status[0x8];
7525 	u8         reserved_at_8[0x18];
7526 
7527 	u8         syndrome[0x20];
7528 
7529 	u8         reserved_at_40[0x40];
7530 
7531 	union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
7532 };
7533 
7534 struct mlx5_ifc_query_cong_params_in_bits {
7535 	u8         opcode[0x10];
7536 	u8         reserved_at_10[0x10];
7537 
7538 	u8         reserved_at_20[0x10];
7539 	u8         op_mod[0x10];
7540 
7541 	u8         reserved_at_40[0x1c];
7542 	u8         cong_protocol[0x4];
7543 
7544 	u8         reserved_at_60[0x20];
7545 };
7546 
7547 struct mlx5_ifc_query_adapter_out_bits {
7548 	u8         status[0x8];
7549 	u8         reserved_at_8[0x18];
7550 
7551 	u8         syndrome[0x20];
7552 
7553 	u8         reserved_at_40[0x40];
7554 
7555 	struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct;
7556 };
7557 
7558 struct mlx5_ifc_query_adapter_in_bits {
7559 	u8         opcode[0x10];
7560 	u8         reserved_at_10[0x10];
7561 
7562 	u8         reserved_at_20[0x10];
7563 	u8         op_mod[0x10];
7564 
7565 	u8         reserved_at_40[0x40];
7566 };
7567 
7568 struct mlx5_ifc_function_vhca_rid_info_reg_bits {
7569 	u8         host_number[0x8];
7570 	u8         host_pci_device_function[0x8];
7571 	u8         host_pci_bus[0x8];
7572 	u8         reserved_at_18[0x3];
7573 	u8         pci_bus_assigned[0x1];
7574 	u8         function_type[0x4];
7575 
7576 	u8         parent_pci_device_function[0x8];
7577 	u8         parent_pci_bus[0x8];
7578 	u8         vhca_id[0x10];
7579 
7580 	u8         reserved_at_40[0x10];
7581 	u8         function_id[0x10];
7582 
7583 	u8         reserved_at_60[0x20];
7584 };
7585 
7586 struct mlx5_ifc_delegated_function_vhca_rid_info_bits {
7587 	struct mlx5_ifc_function_vhca_rid_info_reg_bits function_vhca_rid_info;
7588 
7589 	u8         reserved_at_80[0x18];
7590 	u8         manage_profile[0x8];
7591 
7592 	u8         reserved_at_a0[0x60];
7593 };
7594 
7595 struct mlx5_ifc_query_delegated_vhca_out_bits {
7596 	u8         status[0x8];
7597 	u8         reserved_at_8[0x18];
7598 
7599 	u8         syndrome[0x20];
7600 
7601 	u8         reserved_at_40[0x20];
7602 
7603 	u8         reserved_at_60[0x10];
7604 	u8         functions_count[0x10];
7605 
7606 	u8         reserved_at_80[0x80];
7607 
7608 	struct mlx5_ifc_delegated_function_vhca_rid_info_bits
7609 			delegated_function_vhca_rid_info[];
7610 };
7611 
7612 struct mlx5_ifc_query_delegated_vhca_in_bits {
7613 	u8         opcode[0x10];
7614 	u8         uid[0x10];
7615 
7616 	u8         reserved_at_20[0x10];
7617 	u8         op_mod[0x10];
7618 
7619 	u8         reserved_at_40[0x40];
7620 };
7621 
7622 struct mlx5_ifc_create_esw_vport_out_bits {
7623 	u8         status[0x8];
7624 	u8         reserved_at_8[0x18];
7625 
7626 	u8         syndrome[0x20];
7627 
7628 	u8         reserved_at_40[0x20];
7629 
7630 	u8         reserved_at_60[0x10];
7631 	u8         vport_num[0x10];
7632 };
7633 
7634 struct mlx5_ifc_create_esw_vport_in_bits {
7635 	u8         opcode[0x10];
7636 	u8         reserved_at_10[0x10];
7637 
7638 	u8         reserved_at_20[0x10];
7639 	u8         op_mod[0x10];
7640 
7641 	u8         reserved_at_40[0x10];
7642 	u8         managed_vhca_id[0x10];
7643 
7644 	u8         reserved_at_60[0x20];
7645 };
7646 
7647 struct mlx5_ifc_qp_2rst_out_bits {
7648 	u8         status[0x8];
7649 	u8         reserved_at_8[0x18];
7650 
7651 	u8         syndrome[0x20];
7652 
7653 	u8         reserved_at_40[0x40];
7654 };
7655 
7656 struct mlx5_ifc_qp_2rst_in_bits {
7657 	u8         opcode[0x10];
7658 	u8         uid[0x10];
7659 
7660 	u8         reserved_at_20[0x10];
7661 	u8         op_mod[0x10];
7662 
7663 	u8         reserved_at_40[0x8];
7664 	u8         qpn[0x18];
7665 
7666 	u8         reserved_at_60[0x20];
7667 };
7668 
7669 struct mlx5_ifc_qp_2err_out_bits {
7670 	u8         status[0x8];
7671 	u8         reserved_at_8[0x18];
7672 
7673 	u8         syndrome[0x20];
7674 
7675 	u8         reserved_at_40[0x40];
7676 };
7677 
7678 struct mlx5_ifc_qp_2err_in_bits {
7679 	u8         opcode[0x10];
7680 	u8         uid[0x10];
7681 
7682 	u8         reserved_at_20[0x10];
7683 	u8         op_mod[0x10];
7684 
7685 	u8         reserved_at_40[0x8];
7686 	u8         qpn[0x18];
7687 
7688 	u8         reserved_at_60[0x20];
7689 };
7690 
7691 struct mlx5_ifc_trans_page_fault_info_bits {
7692 	u8         error[0x1];
7693 	u8         reserved_at_1[0x4];
7694 	u8         page_fault_type[0x3];
7695 	u8         wq_number[0x18];
7696 
7697 	u8         reserved_at_20[0x8];
7698 	u8         fault_token[0x18];
7699 };
7700 
7701 struct mlx5_ifc_mem_page_fault_info_bits {
7702 	u8          error[0x1];
7703 	u8          reserved_at_1[0xf];
7704 	u8          fault_token_47_32[0x10];
7705 
7706 	u8          fault_token_31_0[0x20];
7707 };
7708 
7709 union mlx5_ifc_page_fault_resume_in_page_fault_info_auto_bits {
7710 	struct mlx5_ifc_trans_page_fault_info_bits trans_page_fault_info;
7711 	struct mlx5_ifc_mem_page_fault_info_bits mem_page_fault_info;
7712 	u8          reserved_at_0[0x40];
7713 };
7714 
7715 struct mlx5_ifc_page_fault_resume_out_bits {
7716 	u8         status[0x8];
7717 	u8         reserved_at_8[0x18];
7718 
7719 	u8         syndrome[0x20];
7720 
7721 	u8         reserved_at_40[0x40];
7722 };
7723 
7724 struct mlx5_ifc_page_fault_resume_in_bits {
7725 	u8         opcode[0x10];
7726 	u8         reserved_at_10[0x10];
7727 
7728 	u8         reserved_at_20[0x10];
7729 	u8         op_mod[0x10];
7730 
7731 	union mlx5_ifc_page_fault_resume_in_page_fault_info_auto_bits
7732 		page_fault_info;
7733 };
7734 
7735 struct mlx5_ifc_nop_out_bits {
7736 	u8         status[0x8];
7737 	u8         reserved_at_8[0x18];
7738 
7739 	u8         syndrome[0x20];
7740 
7741 	u8         reserved_at_40[0x40];
7742 };
7743 
7744 struct mlx5_ifc_nop_in_bits {
7745 	u8         opcode[0x10];
7746 	u8         reserved_at_10[0x10];
7747 
7748 	u8         reserved_at_20[0x10];
7749 	u8         op_mod[0x10];
7750 
7751 	u8         reserved_at_40[0x40];
7752 };
7753 
7754 struct mlx5_ifc_modify_vport_state_out_bits {
7755 	u8         status[0x8];
7756 	u8         reserved_at_8[0x18];
7757 
7758 	u8         syndrome[0x20];
7759 
7760 	u8         reserved_at_40[0x40];
7761 };
7762 
7763 struct mlx5_ifc_modify_vport_state_in_bits {
7764 	u8         opcode[0x10];
7765 	u8         reserved_at_10[0x10];
7766 
7767 	u8         reserved_at_20[0x10];
7768 	u8         op_mod[0x10];
7769 
7770 	u8         other_vport[0x1];
7771 	u8         reserved_at_41[0xf];
7772 	u8         vport_number[0x10];
7773 
7774 	u8         reserved_at_60[0x10];
7775 	u8         ingress_connect[0x1];
7776 	u8         egress_connect[0x1];
7777 	u8         ingress_connect_valid[0x1];
7778 	u8         egress_connect_valid[0x1];
7779 	u8         reserved_at_74[0x4];
7780 	u8         admin_state[0x4];
7781 	u8         reserved_at_7c[0x4];
7782 };
7783 
7784 struct mlx5_ifc_modify_tis_out_bits {
7785 	u8         status[0x8];
7786 	u8         reserved_at_8[0x18];
7787 
7788 	u8         syndrome[0x20];
7789 
7790 	u8         reserved_at_40[0x40];
7791 };
7792 
7793 struct mlx5_ifc_modify_tis_bitmask_bits {
7794 	u8         reserved_at_0[0x20];
7795 
7796 	u8         reserved_at_20[0x1d];
7797 	u8         lag_tx_port_affinity[0x1];
7798 	u8         strict_lag_tx_port_affinity[0x1];
7799 	u8         prio[0x1];
7800 };
7801 
7802 struct mlx5_ifc_modify_tis_in_bits {
7803 	u8         opcode[0x10];
7804 	u8         uid[0x10];
7805 
7806 	u8         reserved_at_20[0x10];
7807 	u8         op_mod[0x10];
7808 
7809 	u8         reserved_at_40[0x8];
7810 	u8         tisn[0x18];
7811 
7812 	u8         reserved_at_60[0x20];
7813 
7814 	struct mlx5_ifc_modify_tis_bitmask_bits bitmask;
7815 
7816 	u8         reserved_at_c0[0x40];
7817 
7818 	struct mlx5_ifc_tisc_bits ctx;
7819 };
7820 
7821 struct mlx5_ifc_modify_tir_bitmask_bits {
7822 	u8	   reserved_at_0[0x20];
7823 
7824 	u8         reserved_at_20[0x1b];
7825 	u8         self_lb_en[0x1];
7826 	u8         reserved_at_3c[0x1];
7827 	u8         hash[0x1];
7828 	u8         reserved_at_3e[0x1];
7829 	u8         packet_merge[0x1];
7830 };
7831 
7832 struct mlx5_ifc_modify_tir_out_bits {
7833 	u8         status[0x8];
7834 	u8         reserved_at_8[0x18];
7835 
7836 	u8         syndrome[0x20];
7837 
7838 	u8         reserved_at_40[0x40];
7839 };
7840 
7841 struct mlx5_ifc_modify_tir_in_bits {
7842 	u8         opcode[0x10];
7843 	u8         uid[0x10];
7844 
7845 	u8         reserved_at_20[0x10];
7846 	u8         op_mod[0x10];
7847 
7848 	u8         reserved_at_40[0x8];
7849 	u8         tirn[0x18];
7850 
7851 	u8         reserved_at_60[0x20];
7852 
7853 	struct mlx5_ifc_modify_tir_bitmask_bits bitmask;
7854 
7855 	u8         reserved_at_c0[0x40];
7856 
7857 	struct mlx5_ifc_tirc_bits ctx;
7858 };
7859 
7860 struct mlx5_ifc_modify_sq_out_bits {
7861 	u8         status[0x8];
7862 	u8         reserved_at_8[0x18];
7863 
7864 	u8         syndrome[0x20];
7865 
7866 	u8         reserved_at_40[0x40];
7867 };
7868 
7869 struct mlx5_ifc_modify_sq_in_bits {
7870 	u8         opcode[0x10];
7871 	u8         uid[0x10];
7872 
7873 	u8         reserved_at_20[0x10];
7874 	u8         op_mod[0x10];
7875 
7876 	u8         sq_state[0x4];
7877 	u8         reserved_at_44[0x4];
7878 	u8         sqn[0x18];
7879 
7880 	u8         reserved_at_60[0x20];
7881 
7882 	u8         modify_bitmask[0x40];
7883 
7884 	u8         reserved_at_c0[0x40];
7885 
7886 	struct mlx5_ifc_sqc_bits ctx;
7887 };
7888 
7889 struct mlx5_ifc_modify_scheduling_element_out_bits {
7890 	u8         status[0x8];
7891 	u8         reserved_at_8[0x18];
7892 
7893 	u8         syndrome[0x20];
7894 
7895 	u8         reserved_at_40[0x1c0];
7896 };
7897 
7898 enum {
7899 	MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1,
7900 	MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2,
7901 };
7902 
7903 struct mlx5_ifc_modify_scheduling_element_in_bits {
7904 	u8         opcode[0x10];
7905 	u8         reserved_at_10[0x10];
7906 
7907 	u8         reserved_at_20[0x10];
7908 	u8         op_mod[0x10];
7909 
7910 	u8         scheduling_hierarchy[0x8];
7911 	u8         reserved_at_48[0x18];
7912 
7913 	u8         scheduling_element_id[0x20];
7914 
7915 	u8         reserved_at_80[0x20];
7916 
7917 	u8         modify_bitmask[0x20];
7918 
7919 	u8         reserved_at_c0[0x40];
7920 
7921 	struct mlx5_ifc_scheduling_context_bits scheduling_context;
7922 
7923 	u8         reserved_at_300[0x100];
7924 };
7925 
7926 struct mlx5_ifc_modify_rqt_out_bits {
7927 	u8         status[0x8];
7928 	u8         reserved_at_8[0x18];
7929 
7930 	u8         syndrome[0x20];
7931 
7932 	u8         reserved_at_40[0x40];
7933 };
7934 
7935 struct mlx5_ifc_rqt_bitmask_bits {
7936 	u8	   reserved_at_0[0x20];
7937 
7938 	u8         reserved_at_20[0x1f];
7939 	u8         rqn_list[0x1];
7940 };
7941 
7942 struct mlx5_ifc_modify_rqt_in_bits {
7943 	u8         opcode[0x10];
7944 	u8         uid[0x10];
7945 
7946 	u8         reserved_at_20[0x10];
7947 	u8         op_mod[0x10];
7948 
7949 	u8         reserved_at_40[0x8];
7950 	u8         rqtn[0x18];
7951 
7952 	u8         reserved_at_60[0x20];
7953 
7954 	struct mlx5_ifc_rqt_bitmask_bits bitmask;
7955 
7956 	u8         reserved_at_c0[0x40];
7957 
7958 	struct mlx5_ifc_rqtc_bits ctx;
7959 };
7960 
7961 struct mlx5_ifc_modify_rq_out_bits {
7962 	u8         status[0x8];
7963 	u8         reserved_at_8[0x18];
7964 
7965 	u8         syndrome[0x20];
7966 
7967 	u8         reserved_at_40[0x40];
7968 };
7969 
7970 enum {
7971 	MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1,
7972 	MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2,
7973 	MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3,
7974 };
7975 
7976 struct mlx5_ifc_modify_rq_in_bits {
7977 	u8         opcode[0x10];
7978 	u8         uid[0x10];
7979 
7980 	u8         reserved_at_20[0x10];
7981 	u8         op_mod[0x10];
7982 
7983 	u8         rq_state[0x4];
7984 	u8         reserved_at_44[0x4];
7985 	u8         rqn[0x18];
7986 
7987 	u8         reserved_at_60[0x20];
7988 
7989 	u8         modify_bitmask[0x40];
7990 
7991 	u8         reserved_at_c0[0x40];
7992 
7993 	struct mlx5_ifc_rqc_bits ctx;
7994 };
7995 
7996 struct mlx5_ifc_modify_rmp_out_bits {
7997 	u8         status[0x8];
7998 	u8         reserved_at_8[0x18];
7999 
8000 	u8         syndrome[0x20];
8001 
8002 	u8         reserved_at_40[0x40];
8003 };
8004 
8005 struct mlx5_ifc_rmp_bitmask_bits {
8006 	u8	   reserved_at_0[0x20];
8007 
8008 	u8         reserved_at_20[0x1f];
8009 	u8         lwm[0x1];
8010 };
8011 
8012 struct mlx5_ifc_modify_rmp_in_bits {
8013 	u8         opcode[0x10];
8014 	u8         uid[0x10];
8015 
8016 	u8         reserved_at_20[0x10];
8017 	u8         op_mod[0x10];
8018 
8019 	u8         rmp_state[0x4];
8020 	u8         reserved_at_44[0x4];
8021 	u8         rmpn[0x18];
8022 
8023 	u8         reserved_at_60[0x20];
8024 
8025 	struct mlx5_ifc_rmp_bitmask_bits bitmask;
8026 
8027 	u8         reserved_at_c0[0x40];
8028 
8029 	struct mlx5_ifc_rmpc_bits ctx;
8030 };
8031 
8032 struct mlx5_ifc_modify_nic_vport_context_out_bits {
8033 	u8         status[0x8];
8034 	u8         reserved_at_8[0x18];
8035 
8036 	u8         syndrome[0x20];
8037 
8038 	u8         reserved_at_40[0x40];
8039 };
8040 
8041 struct mlx5_ifc_modify_nic_vport_field_select_bits {
8042 	u8         reserved_at_0[0x12];
8043 	u8	   affiliation[0x1];
8044 	u8	   reserved_at_13[0x1];
8045 	u8         disable_uc_local_lb[0x1];
8046 	u8         disable_mc_local_lb[0x1];
8047 	u8         node_guid[0x1];
8048 	u8         port_guid[0x1];
8049 	u8         min_inline[0x1];
8050 	u8         mtu[0x1];
8051 	u8         change_event[0x1];
8052 	u8         promisc[0x1];
8053 	u8         permanent_address[0x1];
8054 	u8         addresses_list[0x1];
8055 	u8         roce_en[0x1];
8056 	u8         reserved_at_1f[0x1];
8057 };
8058 
8059 struct mlx5_ifc_modify_nic_vport_context_in_bits {
8060 	u8         opcode[0x10];
8061 	u8         reserved_at_10[0x10];
8062 
8063 	u8         reserved_at_20[0x10];
8064 	u8         op_mod[0x10];
8065 
8066 	u8         other_vport[0x1];
8067 	u8         reserved_at_41[0xf];
8068 	u8         vport_number[0x10];
8069 
8070 	struct mlx5_ifc_modify_nic_vport_field_select_bits field_select;
8071 
8072 	u8         reserved_at_80[0x780];
8073 
8074 	struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
8075 };
8076 
8077 struct mlx5_ifc_modify_hca_vport_context_out_bits {
8078 	u8         status[0x8];
8079 	u8         reserved_at_8[0x18];
8080 
8081 	u8         syndrome[0x20];
8082 
8083 	u8         reserved_at_40[0x40];
8084 };
8085 
8086 struct mlx5_ifc_modify_hca_vport_context_in_bits {
8087 	u8         opcode[0x10];
8088 	u8         reserved_at_10[0x10];
8089 
8090 	u8         reserved_at_20[0x10];
8091 	u8         op_mod[0x10];
8092 
8093 	u8         other_vport[0x1];
8094 	u8         reserved_at_41[0xb];
8095 	u8         port_num[0x4];
8096 	u8         vport_number[0x10];
8097 
8098 	u8         reserved_at_60[0x20];
8099 
8100 	struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
8101 };
8102 
8103 struct mlx5_ifc_modify_cq_out_bits {
8104 	u8         status[0x8];
8105 	u8         reserved_at_8[0x18];
8106 
8107 	u8         syndrome[0x20];
8108 
8109 	u8         reserved_at_40[0x40];
8110 };
8111 
8112 enum {
8113 	MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ  = 0x0,
8114 	MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ  = 0x1,
8115 };
8116 
8117 struct mlx5_ifc_modify_cq_in_bits {
8118 	u8         opcode[0x10];
8119 	u8         uid[0x10];
8120 
8121 	u8         reserved_at_20[0x10];
8122 	u8         op_mod[0x10];
8123 
8124 	u8         reserved_at_40[0x8];
8125 	u8         cqn[0x18];
8126 
8127 	union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select;
8128 
8129 	struct mlx5_ifc_cqc_bits cq_context;
8130 
8131 	u8         reserved_at_280[0x60];
8132 
8133 	u8         cq_umem_valid[0x1];
8134 	u8         reserved_at_2e1[0x1f];
8135 
8136 	u8         reserved_at_300[0x580];
8137 
8138 	u8         pas[][0x40];
8139 };
8140 
8141 struct mlx5_ifc_modify_cong_status_out_bits {
8142 	u8         status[0x8];
8143 	u8         reserved_at_8[0x18];
8144 
8145 	u8         syndrome[0x20];
8146 
8147 	u8         reserved_at_40[0x40];
8148 };
8149 
8150 struct mlx5_ifc_modify_cong_status_in_bits {
8151 	u8         opcode[0x10];
8152 	u8         reserved_at_10[0x10];
8153 
8154 	u8         reserved_at_20[0x10];
8155 	u8         op_mod[0x10];
8156 
8157 	u8         reserved_at_40[0x18];
8158 	u8         priority[0x4];
8159 	u8         cong_protocol[0x4];
8160 
8161 	u8         enable[0x1];
8162 	u8         tag_enable[0x1];
8163 	u8         reserved_at_62[0x1e];
8164 };
8165 
8166 struct mlx5_ifc_modify_cong_params_out_bits {
8167 	u8         status[0x8];
8168 	u8         reserved_at_8[0x18];
8169 
8170 	u8         syndrome[0x20];
8171 
8172 	u8         reserved_at_40[0x40];
8173 };
8174 
8175 struct mlx5_ifc_modify_cong_params_in_bits {
8176 	u8         opcode[0x10];
8177 	u8         reserved_at_10[0x10];
8178 
8179 	u8         reserved_at_20[0x10];
8180 	u8         op_mod[0x10];
8181 
8182 	u8         reserved_at_40[0x1c];
8183 	u8         cong_protocol[0x4];
8184 
8185 	union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select;
8186 
8187 	u8         reserved_at_80[0x80];
8188 
8189 	union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
8190 };
8191 
8192 struct mlx5_ifc_manage_pages_out_bits {
8193 	u8         status[0x8];
8194 	u8         reserved_at_8[0x18];
8195 
8196 	u8         syndrome[0x20];
8197 
8198 	u8         output_num_entries[0x20];
8199 
8200 	u8         reserved_at_60[0x20];
8201 
8202 	u8         pas[][0x40];
8203 };
8204 
8205 enum {
8206 	MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL     = 0x0,
8207 	MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS  = 0x1,
8208 	MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES    = 0x2,
8209 };
8210 
8211 struct mlx5_ifc_manage_pages_in_bits {
8212 	u8         opcode[0x10];
8213 	u8         reserved_at_10[0x10];
8214 
8215 	u8         reserved_at_20[0x10];
8216 	u8         op_mod[0x10];
8217 
8218 	u8         embedded_cpu_function[0x1];
8219 	u8         reserved_at_41[0xf];
8220 	u8         function_id[0x10];
8221 
8222 	u8         input_num_entries[0x20];
8223 
8224 	u8         pas[][0x40];
8225 };
8226 
8227 struct mlx5_ifc_mad_ifc_out_bits {
8228 	u8         status[0x8];
8229 	u8         reserved_at_8[0x18];
8230 
8231 	u8         syndrome[0x20];
8232 
8233 	u8         reserved_at_40[0x40];
8234 
8235 	u8         response_mad_packet[256][0x8];
8236 };
8237 
8238 struct mlx5_ifc_mad_ifc_in_bits {
8239 	u8         opcode[0x10];
8240 	u8         reserved_at_10[0x10];
8241 
8242 	u8         reserved_at_20[0x10];
8243 	u8         op_mod[0x10];
8244 
8245 	u8         remote_lid[0x10];
8246 	u8         plane_index[0x8];
8247 	u8         port[0x8];
8248 
8249 	u8         reserved_at_60[0x20];
8250 
8251 	u8         mad[256][0x8];
8252 };
8253 
8254 struct mlx5_ifc_init_hca_out_bits {
8255 	u8         status[0x8];
8256 	u8         reserved_at_8[0x18];
8257 
8258 	u8         syndrome[0x20];
8259 
8260 	u8         reserved_at_40[0x40];
8261 };
8262 
8263 struct mlx5_ifc_init_hca_in_bits {
8264 	u8         opcode[0x10];
8265 	u8         reserved_at_10[0x10];
8266 
8267 	u8         reserved_at_20[0x10];
8268 	u8         op_mod[0x10];
8269 
8270 	u8         reserved_at_40[0x20];
8271 
8272 	u8         reserved_at_60[0x2];
8273 	u8         sw_vhca_id[0xe];
8274 	u8         reserved_at_70[0x10];
8275 
8276 	u8	   sw_owner_id[4][0x20];
8277 };
8278 
8279 struct mlx5_ifc_init2rtr_qp_out_bits {
8280 	u8         status[0x8];
8281 	u8         reserved_at_8[0x18];
8282 
8283 	u8         syndrome[0x20];
8284 
8285 	u8         reserved_at_40[0x20];
8286 	u8         ece[0x20];
8287 };
8288 
8289 struct mlx5_ifc_init2rtr_qp_in_bits {
8290 	u8         opcode[0x10];
8291 	u8         uid[0x10];
8292 
8293 	u8         reserved_at_20[0x10];
8294 	u8         op_mod[0x10];
8295 
8296 	u8         reserved_at_40[0x8];
8297 	u8         qpn[0x18];
8298 
8299 	u8         reserved_at_60[0x20];
8300 
8301 	u8         opt_param_mask[0x20];
8302 
8303 	u8         ece[0x20];
8304 
8305 	struct mlx5_ifc_qpc_bits qpc;
8306 
8307 	u8         reserved_at_800[0x80];
8308 };
8309 
8310 struct mlx5_ifc_init2init_qp_out_bits {
8311 	u8         status[0x8];
8312 	u8         reserved_at_8[0x18];
8313 
8314 	u8         syndrome[0x20];
8315 
8316 	u8         reserved_at_40[0x20];
8317 	u8         ece[0x20];
8318 };
8319 
8320 struct mlx5_ifc_init2init_qp_in_bits {
8321 	u8         opcode[0x10];
8322 	u8         uid[0x10];
8323 
8324 	u8         reserved_at_20[0x10];
8325 	u8         op_mod[0x10];
8326 
8327 	u8         reserved_at_40[0x8];
8328 	u8         qpn[0x18];
8329 
8330 	u8         reserved_at_60[0x20];
8331 
8332 	u8         opt_param_mask[0x20];
8333 
8334 	u8         ece[0x20];
8335 
8336 	struct mlx5_ifc_qpc_bits qpc;
8337 
8338 	u8         reserved_at_800[0x80];
8339 };
8340 
8341 struct mlx5_ifc_get_dropped_packet_log_out_bits {
8342 	u8         status[0x8];
8343 	u8         reserved_at_8[0x18];
8344 
8345 	u8         syndrome[0x20];
8346 
8347 	u8         reserved_at_40[0x40];
8348 
8349 	u8         packet_headers_log[128][0x8];
8350 
8351 	u8         packet_syndrome[64][0x8];
8352 };
8353 
8354 struct mlx5_ifc_get_dropped_packet_log_in_bits {
8355 	u8         opcode[0x10];
8356 	u8         reserved_at_10[0x10];
8357 
8358 	u8         reserved_at_20[0x10];
8359 	u8         op_mod[0x10];
8360 
8361 	u8         reserved_at_40[0x40];
8362 };
8363 
8364 struct mlx5_ifc_gen_eqe_in_bits {
8365 	u8         opcode[0x10];
8366 	u8         reserved_at_10[0x10];
8367 
8368 	u8         reserved_at_20[0x10];
8369 	u8         op_mod[0x10];
8370 
8371 	u8         reserved_at_40[0x18];
8372 	u8         eq_number[0x8];
8373 
8374 	u8         reserved_at_60[0x20];
8375 
8376 	u8         eqe[64][0x8];
8377 };
8378 
8379 struct mlx5_ifc_gen_eq_out_bits {
8380 	u8         status[0x8];
8381 	u8         reserved_at_8[0x18];
8382 
8383 	u8         syndrome[0x20];
8384 
8385 	u8         reserved_at_40[0x40];
8386 };
8387 
8388 struct mlx5_ifc_enable_hca_out_bits {
8389 	u8         status[0x8];
8390 	u8         reserved_at_8[0x18];
8391 
8392 	u8         syndrome[0x20];
8393 
8394 	u8         reserved_at_40[0x20];
8395 };
8396 
8397 struct mlx5_ifc_enable_hca_in_bits {
8398 	u8         opcode[0x10];
8399 	u8         reserved_at_10[0x10];
8400 
8401 	u8         reserved_at_20[0x10];
8402 	u8         op_mod[0x10];
8403 
8404 	u8         embedded_cpu_function[0x1];
8405 	u8         reserved_at_41[0xf];
8406 	u8         function_id[0x10];
8407 
8408 	u8         reserved_at_60[0x20];
8409 };
8410 
8411 struct mlx5_ifc_drain_dct_out_bits {
8412 	u8         status[0x8];
8413 	u8         reserved_at_8[0x18];
8414 
8415 	u8         syndrome[0x20];
8416 
8417 	u8         reserved_at_40[0x40];
8418 };
8419 
8420 struct mlx5_ifc_drain_dct_in_bits {
8421 	u8         opcode[0x10];
8422 	u8         uid[0x10];
8423 
8424 	u8         reserved_at_20[0x10];
8425 	u8         op_mod[0x10];
8426 
8427 	u8         reserved_at_40[0x8];
8428 	u8         dctn[0x18];
8429 
8430 	u8         reserved_at_60[0x20];
8431 };
8432 
8433 struct mlx5_ifc_disable_hca_out_bits {
8434 	u8         status[0x8];
8435 	u8         reserved_at_8[0x18];
8436 
8437 	u8         syndrome[0x20];
8438 
8439 	u8         reserved_at_40[0x20];
8440 };
8441 
8442 struct mlx5_ifc_disable_hca_in_bits {
8443 	u8         opcode[0x10];
8444 	u8         reserved_at_10[0x10];
8445 
8446 	u8         reserved_at_20[0x10];
8447 	u8         op_mod[0x10];
8448 
8449 	u8         embedded_cpu_function[0x1];
8450 	u8         reserved_at_41[0xf];
8451 	u8         function_id[0x10];
8452 
8453 	u8         reserved_at_60[0x20];
8454 };
8455 
8456 struct mlx5_ifc_detach_from_mcg_out_bits {
8457 	u8         status[0x8];
8458 	u8         reserved_at_8[0x18];
8459 
8460 	u8         syndrome[0x20];
8461 
8462 	u8         reserved_at_40[0x40];
8463 };
8464 
8465 struct mlx5_ifc_detach_from_mcg_in_bits {
8466 	u8         opcode[0x10];
8467 	u8         uid[0x10];
8468 
8469 	u8         reserved_at_20[0x10];
8470 	u8         op_mod[0x10];
8471 
8472 	u8         reserved_at_40[0x8];
8473 	u8         qpn[0x18];
8474 
8475 	u8         reserved_at_60[0x20];
8476 
8477 	u8         multicast_gid[16][0x8];
8478 };
8479 
8480 struct mlx5_ifc_destroy_xrq_out_bits {
8481 	u8         status[0x8];
8482 	u8         reserved_at_8[0x18];
8483 
8484 	u8         syndrome[0x20];
8485 
8486 	u8         reserved_at_40[0x40];
8487 };
8488 
8489 struct mlx5_ifc_destroy_xrq_in_bits {
8490 	u8         opcode[0x10];
8491 	u8         uid[0x10];
8492 
8493 	u8         reserved_at_20[0x10];
8494 	u8         op_mod[0x10];
8495 
8496 	u8         reserved_at_40[0x8];
8497 	u8         xrqn[0x18];
8498 
8499 	u8         reserved_at_60[0x20];
8500 };
8501 
8502 struct mlx5_ifc_destroy_xrc_srq_out_bits {
8503 	u8         status[0x8];
8504 	u8         reserved_at_8[0x18];
8505 
8506 	u8         syndrome[0x20];
8507 
8508 	u8         reserved_at_40[0x40];
8509 };
8510 
8511 struct mlx5_ifc_destroy_xrc_srq_in_bits {
8512 	u8         opcode[0x10];
8513 	u8         uid[0x10];
8514 
8515 	u8         reserved_at_20[0x10];
8516 	u8         op_mod[0x10];
8517 
8518 	u8         reserved_at_40[0x8];
8519 	u8         xrc_srqn[0x18];
8520 
8521 	u8         reserved_at_60[0x20];
8522 };
8523 
8524 struct mlx5_ifc_destroy_tis_out_bits {
8525 	u8         status[0x8];
8526 	u8         reserved_at_8[0x18];
8527 
8528 	u8         syndrome[0x20];
8529 
8530 	u8         reserved_at_40[0x40];
8531 };
8532 
8533 struct mlx5_ifc_destroy_tis_in_bits {
8534 	u8         opcode[0x10];
8535 	u8         uid[0x10];
8536 
8537 	u8         reserved_at_20[0x10];
8538 	u8         op_mod[0x10];
8539 
8540 	u8         reserved_at_40[0x8];
8541 	u8         tisn[0x18];
8542 
8543 	u8         reserved_at_60[0x20];
8544 };
8545 
8546 struct mlx5_ifc_destroy_tir_out_bits {
8547 	u8         status[0x8];
8548 	u8         reserved_at_8[0x18];
8549 
8550 	u8         syndrome[0x20];
8551 
8552 	u8         reserved_at_40[0x40];
8553 };
8554 
8555 struct mlx5_ifc_destroy_tir_in_bits {
8556 	u8         opcode[0x10];
8557 	u8         uid[0x10];
8558 
8559 	u8         reserved_at_20[0x10];
8560 	u8         op_mod[0x10];
8561 
8562 	u8         reserved_at_40[0x8];
8563 	u8         tirn[0x18];
8564 
8565 	u8         reserved_at_60[0x20];
8566 };
8567 
8568 struct mlx5_ifc_destroy_srq_out_bits {
8569 	u8         status[0x8];
8570 	u8         reserved_at_8[0x18];
8571 
8572 	u8         syndrome[0x20];
8573 
8574 	u8         reserved_at_40[0x40];
8575 };
8576 
8577 struct mlx5_ifc_destroy_srq_in_bits {
8578 	u8         opcode[0x10];
8579 	u8         uid[0x10];
8580 
8581 	u8         reserved_at_20[0x10];
8582 	u8         op_mod[0x10];
8583 
8584 	u8         reserved_at_40[0x8];
8585 	u8         srqn[0x18];
8586 
8587 	u8         reserved_at_60[0x20];
8588 };
8589 
8590 struct mlx5_ifc_destroy_sq_out_bits {
8591 	u8         status[0x8];
8592 	u8         reserved_at_8[0x18];
8593 
8594 	u8         syndrome[0x20];
8595 
8596 	u8         reserved_at_40[0x40];
8597 };
8598 
8599 struct mlx5_ifc_destroy_sq_in_bits {
8600 	u8         opcode[0x10];
8601 	u8         uid[0x10];
8602 
8603 	u8         reserved_at_20[0x10];
8604 	u8         op_mod[0x10];
8605 
8606 	u8         reserved_at_40[0x8];
8607 	u8         sqn[0x18];
8608 
8609 	u8         reserved_at_60[0x20];
8610 };
8611 
8612 struct mlx5_ifc_destroy_scheduling_element_out_bits {
8613 	u8         status[0x8];
8614 	u8         reserved_at_8[0x18];
8615 
8616 	u8         syndrome[0x20];
8617 
8618 	u8         reserved_at_40[0x1c0];
8619 };
8620 
8621 struct mlx5_ifc_destroy_scheduling_element_in_bits {
8622 	u8         opcode[0x10];
8623 	u8         reserved_at_10[0x10];
8624 
8625 	u8         reserved_at_20[0x10];
8626 	u8         op_mod[0x10];
8627 
8628 	u8         scheduling_hierarchy[0x8];
8629 	u8         reserved_at_48[0x18];
8630 
8631 	u8         scheduling_element_id[0x20];
8632 
8633 	u8         reserved_at_80[0x180];
8634 };
8635 
8636 struct mlx5_ifc_destroy_rqt_out_bits {
8637 	u8         status[0x8];
8638 	u8         reserved_at_8[0x18];
8639 
8640 	u8         syndrome[0x20];
8641 
8642 	u8         reserved_at_40[0x40];
8643 };
8644 
8645 struct mlx5_ifc_destroy_rqt_in_bits {
8646 	u8         opcode[0x10];
8647 	u8         uid[0x10];
8648 
8649 	u8         reserved_at_20[0x10];
8650 	u8         op_mod[0x10];
8651 
8652 	u8         reserved_at_40[0x8];
8653 	u8         rqtn[0x18];
8654 
8655 	u8         reserved_at_60[0x20];
8656 };
8657 
8658 struct mlx5_ifc_destroy_rq_out_bits {
8659 	u8         status[0x8];
8660 	u8         reserved_at_8[0x18];
8661 
8662 	u8         syndrome[0x20];
8663 
8664 	u8         reserved_at_40[0x40];
8665 };
8666 
8667 struct mlx5_ifc_destroy_rq_in_bits {
8668 	u8         opcode[0x10];
8669 	u8         uid[0x10];
8670 
8671 	u8         reserved_at_20[0x10];
8672 	u8         op_mod[0x10];
8673 
8674 	u8         reserved_at_40[0x8];
8675 	u8         rqn[0x18];
8676 
8677 	u8         reserved_at_60[0x20];
8678 };
8679 
8680 struct mlx5_ifc_set_delay_drop_params_in_bits {
8681 	u8         opcode[0x10];
8682 	u8         reserved_at_10[0x10];
8683 
8684 	u8         reserved_at_20[0x10];
8685 	u8         op_mod[0x10];
8686 
8687 	u8         reserved_at_40[0x20];
8688 
8689 	u8         reserved_at_60[0x10];
8690 	u8         delay_drop_timeout[0x10];
8691 };
8692 
8693 struct mlx5_ifc_set_delay_drop_params_out_bits {
8694 	u8         status[0x8];
8695 	u8         reserved_at_8[0x18];
8696 
8697 	u8         syndrome[0x20];
8698 
8699 	u8         reserved_at_40[0x40];
8700 };
8701 
8702 struct mlx5_ifc_destroy_rmp_out_bits {
8703 	u8         status[0x8];
8704 	u8         reserved_at_8[0x18];
8705 
8706 	u8         syndrome[0x20];
8707 
8708 	u8         reserved_at_40[0x40];
8709 };
8710 
8711 struct mlx5_ifc_destroy_rmp_in_bits {
8712 	u8         opcode[0x10];
8713 	u8         uid[0x10];
8714 
8715 	u8         reserved_at_20[0x10];
8716 	u8         op_mod[0x10];
8717 
8718 	u8         reserved_at_40[0x8];
8719 	u8         rmpn[0x18];
8720 
8721 	u8         reserved_at_60[0x20];
8722 };
8723 
8724 struct mlx5_ifc_destroy_qp_out_bits {
8725 	u8         status[0x8];
8726 	u8         reserved_at_8[0x18];
8727 
8728 	u8         syndrome[0x20];
8729 
8730 	u8         reserved_at_40[0x40];
8731 };
8732 
8733 struct mlx5_ifc_destroy_qp_in_bits {
8734 	u8         opcode[0x10];
8735 	u8         uid[0x10];
8736 
8737 	u8         reserved_at_20[0x10];
8738 	u8         op_mod[0x10];
8739 
8740 	u8         reserved_at_40[0x8];
8741 	u8         qpn[0x18];
8742 
8743 	u8         reserved_at_60[0x20];
8744 };
8745 
8746 struct mlx5_ifc_destroy_psv_out_bits {
8747 	u8         status[0x8];
8748 	u8         reserved_at_8[0x18];
8749 
8750 	u8         syndrome[0x20];
8751 
8752 	u8         reserved_at_40[0x40];
8753 };
8754 
8755 struct mlx5_ifc_destroy_psv_in_bits {
8756 	u8         opcode[0x10];
8757 	u8         reserved_at_10[0x10];
8758 
8759 	u8         reserved_at_20[0x10];
8760 	u8         op_mod[0x10];
8761 
8762 	u8         reserved_at_40[0x8];
8763 	u8         psvn[0x18];
8764 
8765 	u8         reserved_at_60[0x20];
8766 };
8767 
8768 struct mlx5_ifc_destroy_mkey_out_bits {
8769 	u8         status[0x8];
8770 	u8         reserved_at_8[0x18];
8771 
8772 	u8         syndrome[0x20];
8773 
8774 	u8         reserved_at_40[0x40];
8775 };
8776 
8777 struct mlx5_ifc_destroy_mkey_in_bits {
8778 	u8         opcode[0x10];
8779 	u8         uid[0x10];
8780 
8781 	u8         reserved_at_20[0x10];
8782 	u8         op_mod[0x10];
8783 
8784 	u8         reserved_at_40[0x8];
8785 	u8         mkey_index[0x18];
8786 
8787 	u8         reserved_at_60[0x20];
8788 };
8789 
8790 struct mlx5_ifc_destroy_flow_table_out_bits {
8791 	u8         status[0x8];
8792 	u8         reserved_at_8[0x18];
8793 
8794 	u8         syndrome[0x20];
8795 
8796 	u8         reserved_at_40[0x40];
8797 };
8798 
8799 struct mlx5_ifc_destroy_flow_table_in_bits {
8800 	u8         opcode[0x10];
8801 	u8         reserved_at_10[0x10];
8802 
8803 	u8         reserved_at_20[0x10];
8804 	u8         op_mod[0x10];
8805 
8806 	u8         other_vport[0x1];
8807 	u8         reserved_at_41[0xf];
8808 	u8         vport_number[0x10];
8809 
8810 	u8         reserved_at_60[0x20];
8811 
8812 	u8         table_type[0x8];
8813 	u8         reserved_at_88[0x18];
8814 
8815 	u8         reserved_at_a0[0x8];
8816 	u8         table_id[0x18];
8817 
8818 	u8         reserved_at_c0[0x140];
8819 };
8820 
8821 struct mlx5_ifc_destroy_flow_group_out_bits {
8822 	u8         status[0x8];
8823 	u8         reserved_at_8[0x18];
8824 
8825 	u8         syndrome[0x20];
8826 
8827 	u8         reserved_at_40[0x40];
8828 };
8829 
8830 struct mlx5_ifc_destroy_flow_group_in_bits {
8831 	u8         opcode[0x10];
8832 	u8         reserved_at_10[0x10];
8833 
8834 	u8         reserved_at_20[0x10];
8835 	u8         op_mod[0x10];
8836 
8837 	u8         other_vport[0x1];
8838 	u8         reserved_at_41[0xf];
8839 	u8         vport_number[0x10];
8840 
8841 	u8         reserved_at_60[0x20];
8842 
8843 	u8         table_type[0x8];
8844 	u8         reserved_at_88[0x18];
8845 
8846 	u8         reserved_at_a0[0x8];
8847 	u8         table_id[0x18];
8848 
8849 	u8         group_id[0x20];
8850 
8851 	u8         reserved_at_e0[0x120];
8852 };
8853 
8854 struct mlx5_ifc_destroy_eq_out_bits {
8855 	u8         status[0x8];
8856 	u8         reserved_at_8[0x18];
8857 
8858 	u8         syndrome[0x20];
8859 
8860 	u8         reserved_at_40[0x40];
8861 };
8862 
8863 struct mlx5_ifc_destroy_eq_in_bits {
8864 	u8         opcode[0x10];
8865 	u8         reserved_at_10[0x10];
8866 
8867 	u8         reserved_at_20[0x10];
8868 	u8         op_mod[0x10];
8869 
8870 	u8         reserved_at_40[0x18];
8871 	u8         eq_number[0x8];
8872 
8873 	u8         reserved_at_60[0x20];
8874 };
8875 
8876 struct mlx5_ifc_destroy_dct_out_bits {
8877 	u8         status[0x8];
8878 	u8         reserved_at_8[0x18];
8879 
8880 	u8         syndrome[0x20];
8881 
8882 	u8         reserved_at_40[0x40];
8883 };
8884 
8885 struct mlx5_ifc_destroy_dct_in_bits {
8886 	u8         opcode[0x10];
8887 	u8         uid[0x10];
8888 
8889 	u8         reserved_at_20[0x10];
8890 	u8         op_mod[0x10];
8891 
8892 	u8         reserved_at_40[0x8];
8893 	u8         dctn[0x18];
8894 
8895 	u8         reserved_at_60[0x20];
8896 };
8897 
8898 struct mlx5_ifc_destroy_cq_out_bits {
8899 	u8         status[0x8];
8900 	u8         reserved_at_8[0x18];
8901 
8902 	u8         syndrome[0x20];
8903 
8904 	u8         reserved_at_40[0x40];
8905 };
8906 
8907 struct mlx5_ifc_destroy_cq_in_bits {
8908 	u8         opcode[0x10];
8909 	u8         uid[0x10];
8910 
8911 	u8         reserved_at_20[0x10];
8912 	u8         op_mod[0x10];
8913 
8914 	u8         reserved_at_40[0x8];
8915 	u8         cqn[0x18];
8916 
8917 	u8         reserved_at_60[0x20];
8918 };
8919 
8920 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits {
8921 	u8         status[0x8];
8922 	u8         reserved_at_8[0x18];
8923 
8924 	u8         syndrome[0x20];
8925 
8926 	u8         reserved_at_40[0x40];
8927 };
8928 
8929 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits {
8930 	u8         opcode[0x10];
8931 	u8         reserved_at_10[0x10];
8932 
8933 	u8         reserved_at_20[0x10];
8934 	u8         op_mod[0x10];
8935 
8936 	u8         reserved_at_40[0x20];
8937 
8938 	u8         reserved_at_60[0x10];
8939 	u8         vxlan_udp_port[0x10];
8940 };
8941 
8942 struct mlx5_ifc_delete_l2_table_entry_out_bits {
8943 	u8         status[0x8];
8944 	u8         reserved_at_8[0x18];
8945 
8946 	u8         syndrome[0x20];
8947 
8948 	u8         reserved_at_40[0x40];
8949 };
8950 
8951 struct mlx5_ifc_delete_l2_table_entry_in_bits {
8952 	u8         opcode[0x10];
8953 	u8         reserved_at_10[0x10];
8954 
8955 	u8         reserved_at_20[0x10];
8956 	u8         op_mod[0x10];
8957 
8958 	u8         reserved_at_40[0x60];
8959 
8960 	u8         reserved_at_a0[0x8];
8961 	u8         table_index[0x18];
8962 
8963 	u8         reserved_at_c0[0x140];
8964 };
8965 
8966 struct mlx5_ifc_delete_fte_out_bits {
8967 	u8         status[0x8];
8968 	u8         reserved_at_8[0x18];
8969 
8970 	u8         syndrome[0x20];
8971 
8972 	u8         reserved_at_40[0x40];
8973 };
8974 
8975 struct mlx5_ifc_delete_fte_in_bits {
8976 	u8         opcode[0x10];
8977 	u8         reserved_at_10[0x10];
8978 
8979 	u8         reserved_at_20[0x10];
8980 	u8         op_mod[0x10];
8981 
8982 	u8         other_vport[0x1];
8983 	u8         reserved_at_41[0xf];
8984 	u8         vport_number[0x10];
8985 
8986 	u8         reserved_at_60[0x20];
8987 
8988 	u8         table_type[0x8];
8989 	u8         reserved_at_88[0x18];
8990 
8991 	u8         reserved_at_a0[0x8];
8992 	u8         table_id[0x18];
8993 
8994 	u8         reserved_at_c0[0x40];
8995 
8996 	u8         flow_index[0x20];
8997 
8998 	u8         reserved_at_120[0xe0];
8999 };
9000 
9001 struct mlx5_ifc_dealloc_xrcd_out_bits {
9002 	u8         status[0x8];
9003 	u8         reserved_at_8[0x18];
9004 
9005 	u8         syndrome[0x20];
9006 
9007 	u8         reserved_at_40[0x40];
9008 };
9009 
9010 struct mlx5_ifc_dealloc_xrcd_in_bits {
9011 	u8         opcode[0x10];
9012 	u8         uid[0x10];
9013 
9014 	u8         reserved_at_20[0x10];
9015 	u8         op_mod[0x10];
9016 
9017 	u8         reserved_at_40[0x8];
9018 	u8         xrcd[0x18];
9019 
9020 	u8         reserved_at_60[0x20];
9021 };
9022 
9023 struct mlx5_ifc_dealloc_uar_out_bits {
9024 	u8         status[0x8];
9025 	u8         reserved_at_8[0x18];
9026 
9027 	u8         syndrome[0x20];
9028 
9029 	u8         reserved_at_40[0x40];
9030 };
9031 
9032 struct mlx5_ifc_dealloc_uar_in_bits {
9033 	u8         opcode[0x10];
9034 	u8         uid[0x10];
9035 
9036 	u8         reserved_at_20[0x10];
9037 	u8         op_mod[0x10];
9038 
9039 	u8         reserved_at_40[0x8];
9040 	u8         uar[0x18];
9041 
9042 	u8         reserved_at_60[0x20];
9043 };
9044 
9045 struct mlx5_ifc_dealloc_transport_domain_out_bits {
9046 	u8         status[0x8];
9047 	u8         reserved_at_8[0x18];
9048 
9049 	u8         syndrome[0x20];
9050 
9051 	u8         reserved_at_40[0x40];
9052 };
9053 
9054 struct mlx5_ifc_dealloc_transport_domain_in_bits {
9055 	u8         opcode[0x10];
9056 	u8         uid[0x10];
9057 
9058 	u8         reserved_at_20[0x10];
9059 	u8         op_mod[0x10];
9060 
9061 	u8         reserved_at_40[0x8];
9062 	u8         transport_domain[0x18];
9063 
9064 	u8         reserved_at_60[0x20];
9065 };
9066 
9067 struct mlx5_ifc_dealloc_q_counter_out_bits {
9068 	u8         status[0x8];
9069 	u8         reserved_at_8[0x18];
9070 
9071 	u8         syndrome[0x20];
9072 
9073 	u8         reserved_at_40[0x40];
9074 };
9075 
9076 struct mlx5_ifc_dealloc_q_counter_in_bits {
9077 	u8         opcode[0x10];
9078 	u8         reserved_at_10[0x10];
9079 
9080 	u8         reserved_at_20[0x10];
9081 	u8         op_mod[0x10];
9082 
9083 	u8         reserved_at_40[0x18];
9084 	u8         counter_set_id[0x8];
9085 
9086 	u8         reserved_at_60[0x20];
9087 };
9088 
9089 struct mlx5_ifc_dealloc_pd_out_bits {
9090 	u8         status[0x8];
9091 	u8         reserved_at_8[0x18];
9092 
9093 	u8         syndrome[0x20];
9094 
9095 	u8         reserved_at_40[0x40];
9096 };
9097 
9098 struct mlx5_ifc_dealloc_pd_in_bits {
9099 	u8         opcode[0x10];
9100 	u8         uid[0x10];
9101 
9102 	u8         reserved_at_20[0x10];
9103 	u8         op_mod[0x10];
9104 
9105 	u8         reserved_at_40[0x8];
9106 	u8         pd[0x18];
9107 
9108 	u8         reserved_at_60[0x20];
9109 };
9110 
9111 struct mlx5_ifc_dealloc_flow_counter_out_bits {
9112 	u8         status[0x8];
9113 	u8         reserved_at_8[0x18];
9114 
9115 	u8         syndrome[0x20];
9116 
9117 	u8         reserved_at_40[0x40];
9118 };
9119 
9120 struct mlx5_ifc_dealloc_flow_counter_in_bits {
9121 	u8         opcode[0x10];
9122 	u8         reserved_at_10[0x10];
9123 
9124 	u8         reserved_at_20[0x10];
9125 	u8         op_mod[0x10];
9126 
9127 	u8         flow_counter_id[0x20];
9128 
9129 	u8         reserved_at_60[0x20];
9130 };
9131 
9132 struct mlx5_ifc_create_xrq_out_bits {
9133 	u8         status[0x8];
9134 	u8         reserved_at_8[0x18];
9135 
9136 	u8         syndrome[0x20];
9137 
9138 	u8         reserved_at_40[0x8];
9139 	u8         xrqn[0x18];
9140 
9141 	u8         reserved_at_60[0x20];
9142 };
9143 
9144 struct mlx5_ifc_create_xrq_in_bits {
9145 	u8         opcode[0x10];
9146 	u8         uid[0x10];
9147 
9148 	u8         reserved_at_20[0x10];
9149 	u8         op_mod[0x10];
9150 
9151 	u8         reserved_at_40[0x40];
9152 
9153 	struct mlx5_ifc_xrqc_bits xrq_context;
9154 };
9155 
9156 struct mlx5_ifc_create_xrc_srq_out_bits {
9157 	u8         status[0x8];
9158 	u8         reserved_at_8[0x18];
9159 
9160 	u8         syndrome[0x20];
9161 
9162 	u8         reserved_at_40[0x8];
9163 	u8         xrc_srqn[0x18];
9164 
9165 	u8         reserved_at_60[0x20];
9166 };
9167 
9168 struct mlx5_ifc_create_xrc_srq_in_bits {
9169 	u8         opcode[0x10];
9170 	u8         uid[0x10];
9171 
9172 	u8         reserved_at_20[0x10];
9173 	u8         op_mod[0x10];
9174 
9175 	u8         reserved_at_40[0x40];
9176 
9177 	struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
9178 
9179 	u8         reserved_at_280[0x60];
9180 
9181 	u8         xrc_srq_umem_valid[0x1];
9182 	u8         reserved_at_2e1[0x1f];
9183 
9184 	u8         reserved_at_300[0x580];
9185 
9186 	u8         pas[][0x40];
9187 };
9188 
9189 struct mlx5_ifc_create_tis_out_bits {
9190 	u8         status[0x8];
9191 	u8         reserved_at_8[0x18];
9192 
9193 	u8         syndrome[0x20];
9194 
9195 	u8         reserved_at_40[0x8];
9196 	u8         tisn[0x18];
9197 
9198 	u8         reserved_at_60[0x20];
9199 };
9200 
9201 struct mlx5_ifc_create_tis_in_bits {
9202 	u8         opcode[0x10];
9203 	u8         uid[0x10];
9204 
9205 	u8         reserved_at_20[0x10];
9206 	u8         op_mod[0x10];
9207 
9208 	u8         reserved_at_40[0xc0];
9209 
9210 	struct mlx5_ifc_tisc_bits ctx;
9211 };
9212 
9213 struct mlx5_ifc_create_tir_out_bits {
9214 	u8         status[0x8];
9215 	u8         icm_address_63_40[0x18];
9216 
9217 	u8         syndrome[0x20];
9218 
9219 	u8         icm_address_39_32[0x8];
9220 	u8         tirn[0x18];
9221 
9222 	u8         icm_address_31_0[0x20];
9223 };
9224 
9225 struct mlx5_ifc_create_tir_in_bits {
9226 	u8         opcode[0x10];
9227 	u8         uid[0x10];
9228 
9229 	u8         reserved_at_20[0x10];
9230 	u8         op_mod[0x10];
9231 
9232 	u8         reserved_at_40[0xc0];
9233 
9234 	struct mlx5_ifc_tirc_bits ctx;
9235 };
9236 
9237 struct mlx5_ifc_create_srq_out_bits {
9238 	u8         status[0x8];
9239 	u8         reserved_at_8[0x18];
9240 
9241 	u8         syndrome[0x20];
9242 
9243 	u8         reserved_at_40[0x8];
9244 	u8         srqn[0x18];
9245 
9246 	u8         reserved_at_60[0x20];
9247 };
9248 
9249 struct mlx5_ifc_create_srq_in_bits {
9250 	u8         opcode[0x10];
9251 	u8         uid[0x10];
9252 
9253 	u8         reserved_at_20[0x10];
9254 	u8         op_mod[0x10];
9255 
9256 	u8         reserved_at_40[0x40];
9257 
9258 	struct mlx5_ifc_srqc_bits srq_context_entry;
9259 
9260 	u8         reserved_at_280[0x600];
9261 
9262 	u8         pas[][0x40];
9263 };
9264 
9265 struct mlx5_ifc_create_sq_out_bits {
9266 	u8         status[0x8];
9267 	u8         reserved_at_8[0x18];
9268 
9269 	u8         syndrome[0x20];
9270 
9271 	u8         reserved_at_40[0x8];
9272 	u8         sqn[0x18];
9273 
9274 	u8         reserved_at_60[0x20];
9275 };
9276 
9277 struct mlx5_ifc_create_sq_in_bits {
9278 	u8         opcode[0x10];
9279 	u8         uid[0x10];
9280 
9281 	u8         reserved_at_20[0x10];
9282 	u8         op_mod[0x10];
9283 
9284 	u8         reserved_at_40[0xc0];
9285 
9286 	struct mlx5_ifc_sqc_bits ctx;
9287 };
9288 
9289 struct mlx5_ifc_create_scheduling_element_out_bits {
9290 	u8         status[0x8];
9291 	u8         reserved_at_8[0x18];
9292 
9293 	u8         syndrome[0x20];
9294 
9295 	u8         reserved_at_40[0x40];
9296 
9297 	u8         scheduling_element_id[0x20];
9298 
9299 	u8         reserved_at_a0[0x160];
9300 };
9301 
9302 struct mlx5_ifc_create_scheduling_element_in_bits {
9303 	u8         opcode[0x10];
9304 	u8         reserved_at_10[0x10];
9305 
9306 	u8         reserved_at_20[0x10];
9307 	u8         op_mod[0x10];
9308 
9309 	u8         scheduling_hierarchy[0x8];
9310 	u8         reserved_at_48[0x18];
9311 
9312 	u8         reserved_at_60[0xa0];
9313 
9314 	struct mlx5_ifc_scheduling_context_bits scheduling_context;
9315 
9316 	u8         reserved_at_300[0x100];
9317 };
9318 
9319 struct mlx5_ifc_create_rqt_out_bits {
9320 	u8         status[0x8];
9321 	u8         reserved_at_8[0x18];
9322 
9323 	u8         syndrome[0x20];
9324 
9325 	u8         reserved_at_40[0x8];
9326 	u8         rqtn[0x18];
9327 
9328 	u8         reserved_at_60[0x20];
9329 };
9330 
9331 struct mlx5_ifc_create_rqt_in_bits {
9332 	u8         opcode[0x10];
9333 	u8         uid[0x10];
9334 
9335 	u8         reserved_at_20[0x10];
9336 	u8         op_mod[0x10];
9337 
9338 	u8         reserved_at_40[0xc0];
9339 
9340 	struct mlx5_ifc_rqtc_bits rqt_context;
9341 };
9342 
9343 struct mlx5_ifc_create_rq_out_bits {
9344 	u8         status[0x8];
9345 	u8         reserved_at_8[0x18];
9346 
9347 	u8         syndrome[0x20];
9348 
9349 	u8         reserved_at_40[0x8];
9350 	u8         rqn[0x18];
9351 
9352 	u8         reserved_at_60[0x20];
9353 };
9354 
9355 struct mlx5_ifc_create_rq_in_bits {
9356 	u8         opcode[0x10];
9357 	u8         uid[0x10];
9358 
9359 	u8         reserved_at_20[0x10];
9360 	u8         op_mod[0x10];
9361 
9362 	u8         reserved_at_40[0xc0];
9363 
9364 	struct mlx5_ifc_rqc_bits ctx;
9365 };
9366 
9367 struct mlx5_ifc_create_rmp_out_bits {
9368 	u8         status[0x8];
9369 	u8         reserved_at_8[0x18];
9370 
9371 	u8         syndrome[0x20];
9372 
9373 	u8         reserved_at_40[0x8];
9374 	u8         rmpn[0x18];
9375 
9376 	u8         reserved_at_60[0x20];
9377 };
9378 
9379 struct mlx5_ifc_create_rmp_in_bits {
9380 	u8         opcode[0x10];
9381 	u8         uid[0x10];
9382 
9383 	u8         reserved_at_20[0x10];
9384 	u8         op_mod[0x10];
9385 
9386 	u8         reserved_at_40[0xc0];
9387 
9388 	struct mlx5_ifc_rmpc_bits ctx;
9389 };
9390 
9391 struct mlx5_ifc_create_qp_out_bits {
9392 	u8         status[0x8];
9393 	u8         reserved_at_8[0x18];
9394 
9395 	u8         syndrome[0x20];
9396 
9397 	u8         reserved_at_40[0x8];
9398 	u8         qpn[0x18];
9399 
9400 	u8         ece[0x20];
9401 };
9402 
9403 struct mlx5_ifc_create_qp_in_bits {
9404 	u8         opcode[0x10];
9405 	u8         uid[0x10];
9406 
9407 	u8         reserved_at_20[0x10];
9408 	u8         op_mod[0x10];
9409 
9410 	u8         qpc_ext[0x1];
9411 	u8         reserved_at_41[0x7];
9412 	u8         input_qpn[0x18];
9413 
9414 	u8         reserved_at_60[0x20];
9415 	u8         opt_param_mask[0x20];
9416 
9417 	u8         ece[0x20];
9418 
9419 	struct mlx5_ifc_qpc_bits qpc;
9420 
9421 	u8         wq_umem_offset[0x40];
9422 
9423 	u8         wq_umem_id[0x20];
9424 
9425 	u8         wq_umem_valid[0x1];
9426 	u8         reserved_at_861[0x1f];
9427 
9428 	u8         pas[][0x40];
9429 };
9430 
9431 struct mlx5_ifc_create_psv_out_bits {
9432 	u8         status[0x8];
9433 	u8         reserved_at_8[0x18];
9434 
9435 	u8         syndrome[0x20];
9436 
9437 	u8         reserved_at_40[0x40];
9438 
9439 	u8         reserved_at_80[0x8];
9440 	u8         psv0_index[0x18];
9441 
9442 	u8         reserved_at_a0[0x8];
9443 	u8         psv1_index[0x18];
9444 
9445 	u8         reserved_at_c0[0x8];
9446 	u8         psv2_index[0x18];
9447 
9448 	u8         reserved_at_e0[0x8];
9449 	u8         psv3_index[0x18];
9450 };
9451 
9452 struct mlx5_ifc_create_psv_in_bits {
9453 	u8         opcode[0x10];
9454 	u8         reserved_at_10[0x10];
9455 
9456 	u8         reserved_at_20[0x10];
9457 	u8         op_mod[0x10];
9458 
9459 	u8         num_psv[0x4];
9460 	u8         reserved_at_44[0x4];
9461 	u8         pd[0x18];
9462 
9463 	u8         reserved_at_60[0x20];
9464 };
9465 
9466 struct mlx5_ifc_create_mkey_out_bits {
9467 	u8         status[0x8];
9468 	u8         reserved_at_8[0x18];
9469 
9470 	u8         syndrome[0x20];
9471 
9472 	u8         reserved_at_40[0x8];
9473 	u8         mkey_index[0x18];
9474 
9475 	u8         reserved_at_60[0x20];
9476 };
9477 
9478 struct mlx5_ifc_create_mkey_in_bits {
9479 	u8         opcode[0x10];
9480 	u8         uid[0x10];
9481 
9482 	u8         reserved_at_20[0x10];
9483 	u8         op_mod[0x10];
9484 
9485 	u8         reserved_at_40[0x20];
9486 
9487 	u8         pg_access[0x1];
9488 	u8         mkey_umem_valid[0x1];
9489 	u8         data_direct[0x1];
9490 	u8         reserved_at_63[0x1d];
9491 
9492 	struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
9493 
9494 	u8         reserved_at_280[0x80];
9495 
9496 	u8         translations_octword_actual_size[0x20];
9497 
9498 	u8         reserved_at_320[0x560];
9499 
9500 	u8         klm_pas_mtt[][0x20];
9501 };
9502 
9503 enum {
9504 	MLX5_FLOW_TABLE_TYPE_NIC_RX		= 0x0,
9505 	MLX5_FLOW_TABLE_TYPE_NIC_TX		= 0x1,
9506 	MLX5_FLOW_TABLE_TYPE_ESW_EGRESS_ACL	= 0x2,
9507 	MLX5_FLOW_TABLE_TYPE_ESW_INGRESS_ACL	= 0x3,
9508 	MLX5_FLOW_TABLE_TYPE_FDB		= 0X4,
9509 	MLX5_FLOW_TABLE_TYPE_SNIFFER_RX		= 0X5,
9510 	MLX5_FLOW_TABLE_TYPE_SNIFFER_TX		= 0X6,
9511 };
9512 
9513 struct mlx5_ifc_create_flow_table_out_bits {
9514 	u8         status[0x8];
9515 	u8         icm_address_63_40[0x18];
9516 
9517 	u8         syndrome[0x20];
9518 
9519 	u8         icm_address_39_32[0x8];
9520 	u8         table_id[0x18];
9521 
9522 	u8         icm_address_31_0[0x20];
9523 };
9524 
9525 struct mlx5_ifc_create_flow_table_in_bits {
9526 	u8         opcode[0x10];
9527 	u8         uid[0x10];
9528 
9529 	u8         reserved_at_20[0x10];
9530 	u8         op_mod[0x10];
9531 
9532 	u8         other_vport[0x1];
9533 	u8         reserved_at_41[0xf];
9534 	u8         vport_number[0x10];
9535 
9536 	u8         reserved_at_60[0x20];
9537 
9538 	u8         table_type[0x8];
9539 	u8         reserved_at_88[0x18];
9540 
9541 	u8         reserved_at_a0[0x20];
9542 
9543 	struct mlx5_ifc_flow_table_context_bits flow_table_context;
9544 };
9545 
9546 struct mlx5_ifc_create_flow_group_out_bits {
9547 	u8         status[0x8];
9548 	u8         reserved_at_8[0x18];
9549 
9550 	u8         syndrome[0x20];
9551 
9552 	u8         reserved_at_40[0x8];
9553 	u8         group_id[0x18];
9554 
9555 	u8         reserved_at_60[0x20];
9556 };
9557 
9558 enum {
9559 	MLX5_CREATE_FLOW_GROUP_IN_GROUP_TYPE_TCAM_SUBTABLE  = 0x0,
9560 	MLX5_CREATE_FLOW_GROUP_IN_GROUP_TYPE_HASH_SPLIT     = 0x1,
9561 };
9562 
9563 enum {
9564 	MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS     = 0x0,
9565 	MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS   = 0x1,
9566 	MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS     = 0x2,
9567 	MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3,
9568 };
9569 
9570 struct mlx5_ifc_create_flow_group_in_bits {
9571 	u8         opcode[0x10];
9572 	u8         reserved_at_10[0x10];
9573 
9574 	u8         reserved_at_20[0x10];
9575 	u8         op_mod[0x10];
9576 
9577 	u8         other_vport[0x1];
9578 	u8         reserved_at_41[0xf];
9579 	u8         vport_number[0x10];
9580 
9581 	u8         reserved_at_60[0x20];
9582 
9583 	u8         table_type[0x8];
9584 	u8         reserved_at_88[0x4];
9585 	u8         group_type[0x4];
9586 	u8         reserved_at_90[0x10];
9587 
9588 	u8         reserved_at_a0[0x8];
9589 	u8         table_id[0x18];
9590 
9591 	u8         source_eswitch_owner_vhca_id_valid[0x1];
9592 
9593 	u8         reserved_at_c1[0x1f];
9594 
9595 	u8         start_flow_index[0x20];
9596 
9597 	u8         reserved_at_100[0x20];
9598 
9599 	u8         end_flow_index[0x20];
9600 
9601 	u8         reserved_at_140[0x10];
9602 	u8         match_definer_id[0x10];
9603 
9604 	u8         reserved_at_160[0x80];
9605 
9606 	u8         reserved_at_1e0[0x18];
9607 	u8         match_criteria_enable[0x8];
9608 
9609 	struct mlx5_ifc_fte_match_param_bits match_criteria;
9610 
9611 	u8         reserved_at_1200[0xe00];
9612 };
9613 
9614 struct mlx5_ifc_create_eq_out_bits {
9615 	u8         status[0x8];
9616 	u8         reserved_at_8[0x18];
9617 
9618 	u8         syndrome[0x20];
9619 
9620 	u8         reserved_at_40[0x18];
9621 	u8         eq_number[0x8];
9622 
9623 	u8         reserved_at_60[0x20];
9624 };
9625 
9626 struct mlx5_ifc_create_eq_in_bits {
9627 	u8         opcode[0x10];
9628 	u8         uid[0x10];
9629 
9630 	u8         reserved_at_20[0x10];
9631 	u8         op_mod[0x10];
9632 
9633 	u8         reserved_at_40[0x40];
9634 
9635 	struct mlx5_ifc_eqc_bits eq_context_entry;
9636 
9637 	u8         reserved_at_280[0x40];
9638 
9639 	u8         event_bitmask[4][0x40];
9640 
9641 	u8         reserved_at_3c0[0x4c0];
9642 
9643 	u8         pas[][0x40];
9644 };
9645 
9646 struct mlx5_ifc_create_dct_out_bits {
9647 	u8         status[0x8];
9648 	u8         reserved_at_8[0x18];
9649 
9650 	u8         syndrome[0x20];
9651 
9652 	u8         reserved_at_40[0x8];
9653 	u8         dctn[0x18];
9654 
9655 	u8         ece[0x20];
9656 };
9657 
9658 struct mlx5_ifc_create_dct_in_bits {
9659 	u8         opcode[0x10];
9660 	u8         uid[0x10];
9661 
9662 	u8         reserved_at_20[0x10];
9663 	u8         op_mod[0x10];
9664 
9665 	u8         reserved_at_40[0x40];
9666 
9667 	struct mlx5_ifc_dctc_bits dct_context_entry;
9668 
9669 	u8         reserved_at_280[0x180];
9670 };
9671 
9672 struct mlx5_ifc_create_cq_out_bits {
9673 	u8         status[0x8];
9674 	u8         reserved_at_8[0x18];
9675 
9676 	u8         syndrome[0x20];
9677 
9678 	u8         reserved_at_40[0x8];
9679 	u8         cqn[0x18];
9680 
9681 	u8         reserved_at_60[0x20];
9682 };
9683 
9684 struct mlx5_ifc_create_cq_in_bits {
9685 	u8         opcode[0x10];
9686 	u8         uid[0x10];
9687 
9688 	u8         reserved_at_20[0x10];
9689 	u8         op_mod[0x10];
9690 
9691 	u8         reserved_at_40[0x40];
9692 
9693 	struct mlx5_ifc_cqc_bits cq_context;
9694 
9695 	u8         reserved_at_280[0x60];
9696 
9697 	u8         cq_umem_valid[0x1];
9698 	u8         reserved_at_2e1[0x59f];
9699 
9700 	u8         pas[][0x40];
9701 };
9702 
9703 struct mlx5_ifc_config_int_moderation_out_bits {
9704 	u8         status[0x8];
9705 	u8         reserved_at_8[0x18];
9706 
9707 	u8         syndrome[0x20];
9708 
9709 	u8         reserved_at_40[0x4];
9710 	u8         min_delay[0xc];
9711 	u8         int_vector[0x10];
9712 
9713 	u8         reserved_at_60[0x20];
9714 };
9715 
9716 enum {
9717 	MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE  = 0x0,
9718 	MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ   = 0x1,
9719 };
9720 
9721 struct mlx5_ifc_config_int_moderation_in_bits {
9722 	u8         opcode[0x10];
9723 	u8         reserved_at_10[0x10];
9724 
9725 	u8         reserved_at_20[0x10];
9726 	u8         op_mod[0x10];
9727 
9728 	u8         reserved_at_40[0x4];
9729 	u8         min_delay[0xc];
9730 	u8         int_vector[0x10];
9731 
9732 	u8         reserved_at_60[0x20];
9733 };
9734 
9735 struct mlx5_ifc_attach_to_mcg_out_bits {
9736 	u8         status[0x8];
9737 	u8         reserved_at_8[0x18];
9738 
9739 	u8         syndrome[0x20];
9740 
9741 	u8         reserved_at_40[0x40];
9742 };
9743 
9744 struct mlx5_ifc_attach_to_mcg_in_bits {
9745 	u8         opcode[0x10];
9746 	u8         uid[0x10];
9747 
9748 	u8         reserved_at_20[0x10];
9749 	u8         op_mod[0x10];
9750 
9751 	u8         reserved_at_40[0x8];
9752 	u8         qpn[0x18];
9753 
9754 	u8         reserved_at_60[0x20];
9755 
9756 	u8         multicast_gid[16][0x8];
9757 };
9758 
9759 struct mlx5_ifc_arm_xrq_out_bits {
9760 	u8         status[0x8];
9761 	u8         reserved_at_8[0x18];
9762 
9763 	u8         syndrome[0x20];
9764 
9765 	u8         reserved_at_40[0x40];
9766 };
9767 
9768 struct mlx5_ifc_arm_xrq_in_bits {
9769 	u8         opcode[0x10];
9770 	u8         reserved_at_10[0x10];
9771 
9772 	u8         reserved_at_20[0x10];
9773 	u8         op_mod[0x10];
9774 
9775 	u8         reserved_at_40[0x8];
9776 	u8         xrqn[0x18];
9777 
9778 	u8         reserved_at_60[0x10];
9779 	u8         lwm[0x10];
9780 };
9781 
9782 struct mlx5_ifc_arm_xrc_srq_out_bits {
9783 	u8         status[0x8];
9784 	u8         reserved_at_8[0x18];
9785 
9786 	u8         syndrome[0x20];
9787 
9788 	u8         reserved_at_40[0x40];
9789 };
9790 
9791 enum {
9792 	MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ  = 0x1,
9793 };
9794 
9795 struct mlx5_ifc_arm_xrc_srq_in_bits {
9796 	u8         opcode[0x10];
9797 	u8         uid[0x10];
9798 
9799 	u8         reserved_at_20[0x10];
9800 	u8         op_mod[0x10];
9801 
9802 	u8         reserved_at_40[0x8];
9803 	u8         xrc_srqn[0x18];
9804 
9805 	u8         reserved_at_60[0x10];
9806 	u8         lwm[0x10];
9807 };
9808 
9809 struct mlx5_ifc_arm_rq_out_bits {
9810 	u8         status[0x8];
9811 	u8         reserved_at_8[0x18];
9812 
9813 	u8         syndrome[0x20];
9814 
9815 	u8         reserved_at_40[0x40];
9816 };
9817 
9818 enum {
9819 	MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1,
9820 	MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2,
9821 };
9822 
9823 struct mlx5_ifc_arm_rq_in_bits {
9824 	u8         opcode[0x10];
9825 	u8         uid[0x10];
9826 
9827 	u8         reserved_at_20[0x10];
9828 	u8         op_mod[0x10];
9829 
9830 	u8         reserved_at_40[0x8];
9831 	u8         srq_number[0x18];
9832 
9833 	u8         reserved_at_60[0x10];
9834 	u8         lwm[0x10];
9835 };
9836 
9837 struct mlx5_ifc_arm_dct_out_bits {
9838 	u8         status[0x8];
9839 	u8         reserved_at_8[0x18];
9840 
9841 	u8         syndrome[0x20];
9842 
9843 	u8         reserved_at_40[0x40];
9844 };
9845 
9846 struct mlx5_ifc_arm_dct_in_bits {
9847 	u8         opcode[0x10];
9848 	u8         reserved_at_10[0x10];
9849 
9850 	u8         reserved_at_20[0x10];
9851 	u8         op_mod[0x10];
9852 
9853 	u8         reserved_at_40[0x8];
9854 	u8         dct_number[0x18];
9855 
9856 	u8         reserved_at_60[0x20];
9857 };
9858 
9859 struct mlx5_ifc_alloc_xrcd_out_bits {
9860 	u8         status[0x8];
9861 	u8         reserved_at_8[0x18];
9862 
9863 	u8         syndrome[0x20];
9864 
9865 	u8         reserved_at_40[0x8];
9866 	u8         xrcd[0x18];
9867 
9868 	u8         reserved_at_60[0x20];
9869 };
9870 
9871 struct mlx5_ifc_alloc_xrcd_in_bits {
9872 	u8         opcode[0x10];
9873 	u8         uid[0x10];
9874 
9875 	u8         reserved_at_20[0x10];
9876 	u8         op_mod[0x10];
9877 
9878 	u8         reserved_at_40[0x40];
9879 };
9880 
9881 struct mlx5_ifc_alloc_uar_out_bits {
9882 	u8         status[0x8];
9883 	u8         reserved_at_8[0x18];
9884 
9885 	u8         syndrome[0x20];
9886 
9887 	u8         reserved_at_40[0x8];
9888 	u8         uar[0x18];
9889 
9890 	u8         reserved_at_60[0x20];
9891 };
9892 
9893 struct mlx5_ifc_alloc_uar_in_bits {
9894 	u8         opcode[0x10];
9895 	u8         uid[0x10];
9896 
9897 	u8         reserved_at_20[0x10];
9898 	u8         op_mod[0x10];
9899 
9900 	u8         reserved_at_40[0x40];
9901 };
9902 
9903 struct mlx5_ifc_alloc_transport_domain_out_bits {
9904 	u8         status[0x8];
9905 	u8         reserved_at_8[0x18];
9906 
9907 	u8         syndrome[0x20];
9908 
9909 	u8         reserved_at_40[0x8];
9910 	u8         transport_domain[0x18];
9911 
9912 	u8         reserved_at_60[0x20];
9913 };
9914 
9915 struct mlx5_ifc_alloc_transport_domain_in_bits {
9916 	u8         opcode[0x10];
9917 	u8         uid[0x10];
9918 
9919 	u8         reserved_at_20[0x10];
9920 	u8         op_mod[0x10];
9921 
9922 	u8         reserved_at_40[0x40];
9923 };
9924 
9925 struct mlx5_ifc_alloc_q_counter_out_bits {
9926 	u8         status[0x8];
9927 	u8         reserved_at_8[0x18];
9928 
9929 	u8         syndrome[0x20];
9930 
9931 	u8         reserved_at_40[0x18];
9932 	u8         counter_set_id[0x8];
9933 
9934 	u8         reserved_at_60[0x20];
9935 };
9936 
9937 struct mlx5_ifc_alloc_q_counter_in_bits {
9938 	u8         opcode[0x10];
9939 	u8         uid[0x10];
9940 
9941 	u8         reserved_at_20[0x10];
9942 	u8         op_mod[0x10];
9943 
9944 	u8         reserved_at_40[0x40];
9945 };
9946 
9947 struct mlx5_ifc_alloc_pd_out_bits {
9948 	u8         status[0x8];
9949 	u8         reserved_at_8[0x18];
9950 
9951 	u8         syndrome[0x20];
9952 
9953 	u8         reserved_at_40[0x8];
9954 	u8         pd[0x18];
9955 
9956 	u8         reserved_at_60[0x20];
9957 };
9958 
9959 struct mlx5_ifc_alloc_pd_in_bits {
9960 	u8         opcode[0x10];
9961 	u8         uid[0x10];
9962 
9963 	u8         reserved_at_20[0x10];
9964 	u8         op_mod[0x10];
9965 
9966 	u8         reserved_at_40[0x40];
9967 };
9968 
9969 struct mlx5_ifc_alloc_flow_counter_out_bits {
9970 	u8         status[0x8];
9971 	u8         reserved_at_8[0x18];
9972 
9973 	u8         syndrome[0x20];
9974 
9975 	u8         flow_counter_id[0x20];
9976 
9977 	u8         reserved_at_60[0x20];
9978 };
9979 
9980 struct mlx5_ifc_alloc_flow_counter_in_bits {
9981 	u8         opcode[0x10];
9982 	u8         reserved_at_10[0x10];
9983 
9984 	u8         reserved_at_20[0x10];
9985 	u8         op_mod[0x10];
9986 
9987 	u8         reserved_at_40[0x33];
9988 	u8         flow_counter_bulk_log_size[0x5];
9989 	u8         flow_counter_bulk[0x8];
9990 };
9991 
9992 struct mlx5_ifc_add_vxlan_udp_dport_out_bits {
9993 	u8         status[0x8];
9994 	u8         reserved_at_8[0x18];
9995 
9996 	u8         syndrome[0x20];
9997 
9998 	u8         reserved_at_40[0x40];
9999 };
10000 
10001 struct mlx5_ifc_add_vxlan_udp_dport_in_bits {
10002 	u8         opcode[0x10];
10003 	u8         reserved_at_10[0x10];
10004 
10005 	u8         reserved_at_20[0x10];
10006 	u8         op_mod[0x10];
10007 
10008 	u8         reserved_at_40[0x20];
10009 
10010 	u8         reserved_at_60[0x10];
10011 	u8         vxlan_udp_port[0x10];
10012 };
10013 
10014 struct mlx5_ifc_set_pp_rate_limit_out_bits {
10015 	u8         status[0x8];
10016 	u8         reserved_at_8[0x18];
10017 
10018 	u8         syndrome[0x20];
10019 
10020 	u8         reserved_at_40[0x40];
10021 };
10022 
10023 struct mlx5_ifc_set_pp_rate_limit_context_bits {
10024 	u8         rate_limit[0x20];
10025 
10026 	u8	   burst_upper_bound[0x20];
10027 
10028 	u8         reserved_at_40[0x10];
10029 	u8	   typical_packet_size[0x10];
10030 
10031 	u8         reserved_at_60[0x120];
10032 };
10033 
10034 struct mlx5_ifc_set_pp_rate_limit_in_bits {
10035 	u8         opcode[0x10];
10036 	u8         uid[0x10];
10037 
10038 	u8         reserved_at_20[0x10];
10039 	u8         op_mod[0x10];
10040 
10041 	u8         reserved_at_40[0x10];
10042 	u8         rate_limit_index[0x10];
10043 
10044 	u8         reserved_at_60[0x20];
10045 
10046 	struct mlx5_ifc_set_pp_rate_limit_context_bits ctx;
10047 };
10048 
10049 struct mlx5_ifc_access_register_out_bits {
10050 	u8         status[0x8];
10051 	u8         reserved_at_8[0x18];
10052 
10053 	u8         syndrome[0x20];
10054 
10055 	u8         reserved_at_40[0x40];
10056 
10057 	u8         register_data[][0x20];
10058 };
10059 
10060 enum {
10061 	MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE  = 0x0,
10062 	MLX5_ACCESS_REGISTER_IN_OP_MOD_READ   = 0x1,
10063 };
10064 
10065 struct mlx5_ifc_access_register_in_bits {
10066 	u8         opcode[0x10];
10067 	u8         reserved_at_10[0x10];
10068 
10069 	u8         reserved_at_20[0x10];
10070 	u8         op_mod[0x10];
10071 
10072 	u8         reserved_at_40[0x10];
10073 	u8         register_id[0x10];
10074 
10075 	u8         argument[0x20];
10076 
10077 	u8         register_data[][0x20];
10078 };
10079 
10080 struct mlx5_ifc_sltp_reg_bits {
10081 	u8         status[0x4];
10082 	u8         version[0x4];
10083 	u8         local_port[0x8];
10084 	u8         pnat[0x2];
10085 	u8         reserved_at_12[0x2];
10086 	u8         lane[0x4];
10087 	u8         reserved_at_18[0x8];
10088 
10089 	u8         reserved_at_20[0x20];
10090 
10091 	u8         reserved_at_40[0x7];
10092 	u8         polarity[0x1];
10093 	u8         ob_tap0[0x8];
10094 	u8         ob_tap1[0x8];
10095 	u8         ob_tap2[0x8];
10096 
10097 	u8         reserved_at_60[0xc];
10098 	u8         ob_preemp_mode[0x4];
10099 	u8         ob_reg[0x8];
10100 	u8         ob_bias[0x8];
10101 
10102 	u8         reserved_at_80[0x20];
10103 };
10104 
10105 struct mlx5_ifc_slrg_reg_bits {
10106 	u8         status[0x4];
10107 	u8         version[0x4];
10108 	u8         local_port[0x8];
10109 	u8         pnat[0x2];
10110 	u8         reserved_at_12[0x2];
10111 	u8         lane[0x4];
10112 	u8         reserved_at_18[0x8];
10113 
10114 	u8         time_to_link_up[0x10];
10115 	u8         reserved_at_30[0xc];
10116 	u8         grade_lane_speed[0x4];
10117 
10118 	u8         grade_version[0x8];
10119 	u8         grade[0x18];
10120 
10121 	u8         reserved_at_60[0x4];
10122 	u8         height_grade_type[0x4];
10123 	u8         height_grade[0x18];
10124 
10125 	u8         height_dz[0x10];
10126 	u8         height_dv[0x10];
10127 
10128 	u8         reserved_at_a0[0x10];
10129 	u8         height_sigma[0x10];
10130 
10131 	u8         reserved_at_c0[0x20];
10132 
10133 	u8         reserved_at_e0[0x4];
10134 	u8         phase_grade_type[0x4];
10135 	u8         phase_grade[0x18];
10136 
10137 	u8         reserved_at_100[0x8];
10138 	u8         phase_eo_pos[0x8];
10139 	u8         reserved_at_110[0x8];
10140 	u8         phase_eo_neg[0x8];
10141 
10142 	u8         ffe_set_tested[0x10];
10143 	u8         test_errors_per_lane[0x10];
10144 };
10145 
10146 struct mlx5_ifc_pvlc_reg_bits {
10147 	u8         reserved_at_0[0x8];
10148 	u8         local_port[0x8];
10149 	u8         reserved_at_10[0x10];
10150 
10151 	u8         reserved_at_20[0x1c];
10152 	u8         vl_hw_cap[0x4];
10153 
10154 	u8         reserved_at_40[0x1c];
10155 	u8         vl_admin[0x4];
10156 
10157 	u8         reserved_at_60[0x1c];
10158 	u8         vl_operational[0x4];
10159 };
10160 
10161 struct mlx5_ifc_pude_reg_bits {
10162 	u8         swid[0x8];
10163 	u8         local_port[0x8];
10164 	u8         reserved_at_10[0x4];
10165 	u8         admin_status[0x4];
10166 	u8         reserved_at_18[0x4];
10167 	u8         oper_status[0x4];
10168 
10169 	u8         reserved_at_20[0x60];
10170 };
10171 
10172 enum {
10173 	MLX5_PTYS_CONNECTOR_TYPE_PORT_DA = 0x7,
10174 };
10175 
10176 struct mlx5_ifc_ptys_reg_bits {
10177 	u8         reserved_at_0[0x1];
10178 	u8         an_disable_admin[0x1];
10179 	u8         an_disable_cap[0x1];
10180 	u8         reserved_at_3[0x5];
10181 	u8         local_port[0x8];
10182 	u8         reserved_at_10[0x8];
10183 	u8         plane_ind[0x4];
10184 	u8         reserved_at_1c[0x1];
10185 	u8         proto_mask[0x3];
10186 
10187 	u8         an_status[0x4];
10188 	u8         reserved_at_24[0xc];
10189 	u8         data_rate_oper[0x10];
10190 
10191 	u8         ext_eth_proto_capability[0x20];
10192 
10193 	u8         eth_proto_capability[0x20];
10194 
10195 	u8         ib_link_width_capability[0x10];
10196 	u8         ib_proto_capability[0x10];
10197 
10198 	u8         ext_eth_proto_admin[0x20];
10199 
10200 	u8         eth_proto_admin[0x20];
10201 
10202 	u8         ib_link_width_admin[0x10];
10203 	u8         ib_proto_admin[0x10];
10204 
10205 	u8         ext_eth_proto_oper[0x20];
10206 
10207 	u8         eth_proto_oper[0x20];
10208 
10209 	u8         ib_link_width_oper[0x10];
10210 	u8         ib_proto_oper[0x10];
10211 
10212 	u8         reserved_at_160[0x8];
10213 	u8         lane_rate_oper[0x14];
10214 	u8         connector_type[0x4];
10215 
10216 	u8         eth_proto_lp_advertise[0x20];
10217 
10218 	u8         reserved_at_1a0[0x60];
10219 };
10220 
10221 struct mlx5_ifc_mlcr_reg_bits {
10222 	u8         reserved_at_0[0x8];
10223 	u8         local_port[0x8];
10224 	u8         reserved_at_10[0x20];
10225 
10226 	u8         beacon_duration[0x10];
10227 	u8         reserved_at_40[0x10];
10228 
10229 	u8         beacon_remain[0x10];
10230 };
10231 
10232 struct mlx5_ifc_ptas_reg_bits {
10233 	u8         reserved_at_0[0x20];
10234 
10235 	u8         algorithm_options[0x10];
10236 	u8         reserved_at_30[0x4];
10237 	u8         repetitions_mode[0x4];
10238 	u8         num_of_repetitions[0x8];
10239 
10240 	u8         grade_version[0x8];
10241 	u8         height_grade_type[0x4];
10242 	u8         phase_grade_type[0x4];
10243 	u8         height_grade_weight[0x8];
10244 	u8         phase_grade_weight[0x8];
10245 
10246 	u8         gisim_measure_bits[0x10];
10247 	u8         adaptive_tap_measure_bits[0x10];
10248 
10249 	u8         ber_bath_high_error_threshold[0x10];
10250 	u8         ber_bath_mid_error_threshold[0x10];
10251 
10252 	u8         ber_bath_low_error_threshold[0x10];
10253 	u8         one_ratio_high_threshold[0x10];
10254 
10255 	u8         one_ratio_high_mid_threshold[0x10];
10256 	u8         one_ratio_low_mid_threshold[0x10];
10257 
10258 	u8         one_ratio_low_threshold[0x10];
10259 	u8         ndeo_error_threshold[0x10];
10260 
10261 	u8         mixer_offset_step_size[0x10];
10262 	u8         reserved_at_110[0x8];
10263 	u8         mix90_phase_for_voltage_bath[0x8];
10264 
10265 	u8         mixer_offset_start[0x10];
10266 	u8         mixer_offset_end[0x10];
10267 
10268 	u8         reserved_at_140[0x15];
10269 	u8         ber_test_time[0xb];
10270 };
10271 
10272 struct mlx5_ifc_pspa_reg_bits {
10273 	u8         swid[0x8];
10274 	u8         local_port[0x8];
10275 	u8         sub_port[0x8];
10276 	u8         reserved_at_18[0x8];
10277 
10278 	u8         reserved_at_20[0x20];
10279 };
10280 
10281 struct mlx5_ifc_pqdr_reg_bits {
10282 	u8         reserved_at_0[0x8];
10283 	u8         local_port[0x8];
10284 	u8         reserved_at_10[0x5];
10285 	u8         prio[0x3];
10286 	u8         reserved_at_18[0x6];
10287 	u8         mode[0x2];
10288 
10289 	u8         reserved_at_20[0x20];
10290 
10291 	u8         reserved_at_40[0x10];
10292 	u8         min_threshold[0x10];
10293 
10294 	u8         reserved_at_60[0x10];
10295 	u8         max_threshold[0x10];
10296 
10297 	u8         reserved_at_80[0x10];
10298 	u8         mark_probability_denominator[0x10];
10299 
10300 	u8         reserved_at_a0[0x60];
10301 };
10302 
10303 struct mlx5_ifc_ppsc_reg_bits {
10304 	u8         reserved_at_0[0x8];
10305 	u8         local_port[0x8];
10306 	u8         reserved_at_10[0x10];
10307 
10308 	u8         reserved_at_20[0x60];
10309 
10310 	u8         reserved_at_80[0x1c];
10311 	u8         wrps_admin[0x4];
10312 
10313 	u8         reserved_at_a0[0x1c];
10314 	u8         wrps_status[0x4];
10315 
10316 	u8         reserved_at_c0[0x8];
10317 	u8         up_threshold[0x8];
10318 	u8         reserved_at_d0[0x8];
10319 	u8         down_threshold[0x8];
10320 
10321 	u8         reserved_at_e0[0x20];
10322 
10323 	u8         reserved_at_100[0x1c];
10324 	u8         srps_admin[0x4];
10325 
10326 	u8         reserved_at_120[0x1c];
10327 	u8         srps_status[0x4];
10328 
10329 	u8         reserved_at_140[0x40];
10330 };
10331 
10332 struct mlx5_ifc_pplr_reg_bits {
10333 	u8         reserved_at_0[0x8];
10334 	u8         local_port[0x8];
10335 	u8         reserved_at_10[0x10];
10336 
10337 	u8         reserved_at_20[0x8];
10338 	u8         lb_cap[0x8];
10339 	u8         reserved_at_30[0x8];
10340 	u8         lb_en[0x8];
10341 };
10342 
10343 struct mlx5_ifc_pplm_reg_bits {
10344 	u8         reserved_at_0[0x8];
10345 	u8	   local_port[0x8];
10346 	u8	   reserved_at_10[0x10];
10347 
10348 	u8	   reserved_at_20[0x20];
10349 
10350 	u8	   port_profile_mode[0x8];
10351 	u8	   static_port_profile[0x8];
10352 	u8	   active_port_profile[0x8];
10353 	u8	   reserved_at_58[0x8];
10354 
10355 	u8	   retransmission_active[0x8];
10356 	u8	   fec_mode_active[0x18];
10357 
10358 	u8	   rs_fec_correction_bypass_cap[0x4];
10359 	u8	   reserved_at_84[0x8];
10360 	u8	   fec_override_cap_56g[0x4];
10361 	u8	   fec_override_cap_100g[0x4];
10362 	u8	   fec_override_cap_50g[0x4];
10363 	u8	   fec_override_cap_25g[0x4];
10364 	u8	   fec_override_cap_10g_40g[0x4];
10365 
10366 	u8	   rs_fec_correction_bypass_admin[0x4];
10367 	u8	   reserved_at_a4[0x8];
10368 	u8	   fec_override_admin_56g[0x4];
10369 	u8	   fec_override_admin_100g[0x4];
10370 	u8	   fec_override_admin_50g[0x4];
10371 	u8	   fec_override_admin_25g[0x4];
10372 	u8	   fec_override_admin_10g_40g[0x4];
10373 
10374 	u8         fec_override_cap_400g_8x[0x10];
10375 	u8         fec_override_cap_200g_4x[0x10];
10376 
10377 	u8         fec_override_cap_100g_2x[0x10];
10378 	u8         fec_override_cap_50g_1x[0x10];
10379 
10380 	u8         fec_override_admin_400g_8x[0x10];
10381 	u8         fec_override_admin_200g_4x[0x10];
10382 
10383 	u8         fec_override_admin_100g_2x[0x10];
10384 	u8         fec_override_admin_50g_1x[0x10];
10385 
10386 	u8         fec_override_cap_800g_8x[0x10];
10387 	u8         fec_override_cap_400g_4x[0x10];
10388 
10389 	u8         fec_override_cap_200g_2x[0x10];
10390 	u8         fec_override_cap_100g_1x[0x10];
10391 
10392 	u8         reserved_at_180[0xa0];
10393 
10394 	u8         fec_override_admin_800g_8x[0x10];
10395 	u8         fec_override_admin_400g_4x[0x10];
10396 
10397 	u8         fec_override_admin_200g_2x[0x10];
10398 	u8         fec_override_admin_100g_1x[0x10];
10399 
10400 	u8         reserved_at_260[0x60];
10401 
10402 	u8         fec_override_cap_1600g_8x[0x10];
10403 	u8         fec_override_cap_800g_4x[0x10];
10404 
10405 	u8         fec_override_cap_400g_2x[0x10];
10406 	u8         fec_override_cap_200g_1x[0x10];
10407 
10408 	u8         fec_override_admin_1600g_8x[0x10];
10409 	u8         fec_override_admin_800g_4x[0x10];
10410 
10411 	u8         fec_override_admin_400g_2x[0x10];
10412 	u8         fec_override_admin_200g_1x[0x10];
10413 
10414 	u8         reserved_at_340[0x80];
10415 };
10416 
10417 struct mlx5_ifc_ppcnt_reg_bits {
10418 	u8         swid[0x8];
10419 	u8         local_port[0x8];
10420 	u8         pnat[0x2];
10421 	u8         reserved_at_12[0x8];
10422 	u8         grp[0x6];
10423 
10424 	u8         clr[0x1];
10425 	u8         reserved_at_21[0x13];
10426 	u8         plane_ind[0x4];
10427 	u8         reserved_at_38[0x3];
10428 	u8         prio_tc[0x5];
10429 
10430 	union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set;
10431 };
10432 
10433 struct mlx5_ifc_mpein_reg_bits {
10434 	u8         reserved_at_0[0x2];
10435 	u8         depth[0x6];
10436 	u8         pcie_index[0x8];
10437 	u8         node[0x8];
10438 	u8         reserved_at_18[0x8];
10439 
10440 	u8         capability_mask[0x20];
10441 
10442 	u8         reserved_at_40[0x8];
10443 	u8         link_width_enabled[0x8];
10444 	u8         link_speed_enabled[0x10];
10445 
10446 	u8         lane0_physical_position[0x8];
10447 	u8         link_width_active[0x8];
10448 	u8         link_speed_active[0x10];
10449 
10450 	u8         num_of_pfs[0x10];
10451 	u8         num_of_vfs[0x10];
10452 
10453 	u8         bdf0[0x10];
10454 	u8         reserved_at_b0[0x10];
10455 
10456 	u8         max_read_request_size[0x4];
10457 	u8         max_payload_size[0x4];
10458 	u8         reserved_at_c8[0x5];
10459 	u8         pwr_status[0x3];
10460 	u8         port_type[0x4];
10461 	u8         reserved_at_d4[0xb];
10462 	u8         lane_reversal[0x1];
10463 
10464 	u8         reserved_at_e0[0x14];
10465 	u8         pci_power[0xc];
10466 
10467 	u8         reserved_at_100[0x20];
10468 
10469 	u8         device_status[0x10];
10470 	u8         port_state[0x8];
10471 	u8         reserved_at_138[0x8];
10472 
10473 	u8         reserved_at_140[0x10];
10474 	u8         receiver_detect_result[0x10];
10475 
10476 	u8         reserved_at_160[0x20];
10477 };
10478 
10479 struct mlx5_ifc_mpcnt_reg_bits {
10480 	u8         reserved_at_0[0x8];
10481 	u8         pcie_index[0x8];
10482 	u8         reserved_at_10[0xa];
10483 	u8         grp[0x6];
10484 
10485 	u8         clr[0x1];
10486 	u8         reserved_at_21[0x1f];
10487 
10488 	union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set;
10489 };
10490 
10491 struct mlx5_ifc_ppad_reg_bits {
10492 	u8         reserved_at_0[0x3];
10493 	u8         single_mac[0x1];
10494 	u8         reserved_at_4[0x4];
10495 	u8         local_port[0x8];
10496 	u8         mac_47_32[0x10];
10497 
10498 	u8         mac_31_0[0x20];
10499 
10500 	u8         reserved_at_40[0x40];
10501 };
10502 
10503 struct mlx5_ifc_pmtu_reg_bits {
10504 	u8         reserved_at_0[0x8];
10505 	u8         local_port[0x8];
10506 	u8         reserved_at_10[0x10];
10507 
10508 	u8         max_mtu[0x10];
10509 	u8         reserved_at_30[0x10];
10510 
10511 	u8         admin_mtu[0x10];
10512 	u8         reserved_at_50[0x10];
10513 
10514 	u8         oper_mtu[0x10];
10515 	u8         reserved_at_70[0x10];
10516 };
10517 
10518 struct mlx5_ifc_pmpr_reg_bits {
10519 	u8         reserved_at_0[0x8];
10520 	u8         module[0x8];
10521 	u8         reserved_at_10[0x10];
10522 
10523 	u8         reserved_at_20[0x18];
10524 	u8         attenuation_5g[0x8];
10525 
10526 	u8         reserved_at_40[0x18];
10527 	u8         attenuation_7g[0x8];
10528 
10529 	u8         reserved_at_60[0x18];
10530 	u8         attenuation_12g[0x8];
10531 };
10532 
10533 struct mlx5_ifc_pmpe_reg_bits {
10534 	u8         reserved_at_0[0x8];
10535 	u8         module[0x8];
10536 	u8         reserved_at_10[0xc];
10537 	u8         module_status[0x4];
10538 
10539 	u8         reserved_at_20[0x60];
10540 };
10541 
10542 struct mlx5_ifc_pmpc_reg_bits {
10543 	u8         module_state_updated[32][0x8];
10544 };
10545 
10546 struct mlx5_ifc_pmlpn_reg_bits {
10547 	u8         reserved_at_0[0x4];
10548 	u8         mlpn_status[0x4];
10549 	u8         local_port[0x8];
10550 	u8         reserved_at_10[0x10];
10551 
10552 	u8         e[0x1];
10553 	u8         reserved_at_21[0x1f];
10554 };
10555 
10556 struct mlx5_ifc_pmlp_reg_bits {
10557 	u8         rxtx[0x1];
10558 	u8         reserved_at_1[0x7];
10559 	u8         local_port[0x8];
10560 	u8         reserved_at_10[0x8];
10561 	u8         width[0x8];
10562 
10563 	u8         lane0_module_mapping[0x20];
10564 
10565 	u8         lane1_module_mapping[0x20];
10566 
10567 	u8         lane2_module_mapping[0x20];
10568 
10569 	u8         lane3_module_mapping[0x20];
10570 
10571 	u8         reserved_at_a0[0x160];
10572 };
10573 
10574 struct mlx5_ifc_pmaos_reg_bits {
10575 	u8         reserved_at_0[0x8];
10576 	u8         module[0x8];
10577 	u8         reserved_at_10[0x4];
10578 	u8         admin_status[0x4];
10579 	u8         reserved_at_18[0x4];
10580 	u8         oper_status[0x4];
10581 
10582 	u8         ase[0x1];
10583 	u8         ee[0x1];
10584 	u8         reserved_at_22[0x1c];
10585 	u8         e[0x2];
10586 
10587 	u8         reserved_at_40[0x40];
10588 };
10589 
10590 struct mlx5_ifc_plpc_reg_bits {
10591 	u8         reserved_at_0[0x4];
10592 	u8         profile_id[0xc];
10593 	u8         reserved_at_10[0x4];
10594 	u8         proto_mask[0x4];
10595 	u8         reserved_at_18[0x8];
10596 
10597 	u8         reserved_at_20[0x10];
10598 	u8         lane_speed[0x10];
10599 
10600 	u8         reserved_at_40[0x17];
10601 	u8         lpbf[0x1];
10602 	u8         fec_mode_policy[0x8];
10603 
10604 	u8         retransmission_capability[0x8];
10605 	u8         fec_mode_capability[0x18];
10606 
10607 	u8         retransmission_support_admin[0x8];
10608 	u8         fec_mode_support_admin[0x18];
10609 
10610 	u8         retransmission_request_admin[0x8];
10611 	u8         fec_mode_request_admin[0x18];
10612 
10613 	u8         reserved_at_c0[0x80];
10614 };
10615 
10616 struct mlx5_ifc_plib_reg_bits {
10617 	u8         reserved_at_0[0x8];
10618 	u8         local_port[0x8];
10619 	u8         reserved_at_10[0x8];
10620 	u8         ib_port[0x8];
10621 
10622 	u8         reserved_at_20[0x60];
10623 };
10624 
10625 struct mlx5_ifc_plbf_reg_bits {
10626 	u8         reserved_at_0[0x8];
10627 	u8         local_port[0x8];
10628 	u8         reserved_at_10[0xd];
10629 	u8         lbf_mode[0x3];
10630 
10631 	u8         reserved_at_20[0x20];
10632 };
10633 
10634 struct mlx5_ifc_pipg_reg_bits {
10635 	u8         reserved_at_0[0x8];
10636 	u8         local_port[0x8];
10637 	u8         reserved_at_10[0x10];
10638 
10639 	u8         dic[0x1];
10640 	u8         reserved_at_21[0x19];
10641 	u8         ipg[0x4];
10642 	u8         reserved_at_3e[0x2];
10643 };
10644 
10645 struct mlx5_ifc_pifr_reg_bits {
10646 	u8         reserved_at_0[0x8];
10647 	u8         local_port[0x8];
10648 	u8         reserved_at_10[0x10];
10649 
10650 	u8         reserved_at_20[0xe0];
10651 
10652 	u8         port_filter[8][0x20];
10653 
10654 	u8         port_filter_update_en[8][0x20];
10655 };
10656 
10657 enum {
10658 	MLX5_BUF_OWNERSHIP_UNKNOWN	= 0x0,
10659 	MLX5_BUF_OWNERSHIP_FW_OWNED	= 0x1,
10660 	MLX5_BUF_OWNERSHIP_SW_OWNED	= 0x2,
10661 };
10662 
10663 struct mlx5_ifc_pfcc_reg_bits {
10664 	u8         reserved_at_0[0x4];
10665 	u8	   buf_ownership[0x2];
10666 	u8	   reserved_at_6[0x2];
10667 	u8         local_port[0x8];
10668 	u8         reserved_at_10[0xa];
10669 	u8	   cable_length_mask[0x1];
10670 	u8         ppan_mask_n[0x1];
10671 	u8         minor_stall_mask[0x1];
10672 	u8         critical_stall_mask[0x1];
10673 	u8         reserved_at_1e[0x2];
10674 
10675 	u8         ppan[0x4];
10676 	u8         reserved_at_24[0x4];
10677 	u8         prio_mask_tx[0x8];
10678 	u8         reserved_at_30[0x8];
10679 	u8         prio_mask_rx[0x8];
10680 
10681 	u8         pptx[0x1];
10682 	u8         aptx[0x1];
10683 	u8         pptx_mask_n[0x1];
10684 	u8         reserved_at_43[0x5];
10685 	u8         pfctx[0x8];
10686 	u8         reserved_at_50[0x10];
10687 
10688 	u8         pprx[0x1];
10689 	u8         aprx[0x1];
10690 	u8         pprx_mask_n[0x1];
10691 	u8         reserved_at_63[0x5];
10692 	u8         pfcrx[0x8];
10693 	u8         reserved_at_70[0x10];
10694 
10695 	u8         device_stall_minor_watermark[0x10];
10696 	u8         device_stall_critical_watermark[0x10];
10697 
10698 	u8	   reserved_at_a0[0x18];
10699 	u8	   cable_length[0x8];
10700 
10701 	u8         reserved_at_c0[0x40];
10702 };
10703 
10704 struct mlx5_ifc_pelc_reg_bits {
10705 	u8         op[0x4];
10706 	u8         reserved_at_4[0x4];
10707 	u8         local_port[0x8];
10708 	u8         reserved_at_10[0x10];
10709 
10710 	u8         op_admin[0x8];
10711 	u8         op_capability[0x8];
10712 	u8         op_request[0x8];
10713 	u8         op_active[0x8];
10714 
10715 	u8         admin[0x40];
10716 
10717 	u8         capability[0x40];
10718 
10719 	u8         request[0x40];
10720 
10721 	u8         active[0x40];
10722 
10723 	u8         reserved_at_140[0x80];
10724 };
10725 
10726 struct mlx5_ifc_peir_reg_bits {
10727 	u8         reserved_at_0[0x8];
10728 	u8         local_port[0x8];
10729 	u8         reserved_at_10[0x10];
10730 
10731 	u8         reserved_at_20[0xc];
10732 	u8         error_count[0x4];
10733 	u8         reserved_at_30[0x10];
10734 
10735 	u8         reserved_at_40[0xc];
10736 	u8         lane[0x4];
10737 	u8         reserved_at_50[0x8];
10738 	u8         error_type[0x8];
10739 };
10740 
10741 struct mlx5_ifc_mpegc_reg_bits {
10742 	u8         reserved_at_0[0x30];
10743 	u8         field_select[0x10];
10744 
10745 	u8         tx_overflow_sense[0x1];
10746 	u8         mark_cqe[0x1];
10747 	u8         mark_cnp[0x1];
10748 	u8         reserved_at_43[0x1b];
10749 	u8         tx_lossy_overflow_oper[0x2];
10750 
10751 	u8         reserved_at_60[0x100];
10752 };
10753 
10754 struct mlx5_ifc_mpir_reg_bits {
10755 	u8         sdm[0x1];
10756 	u8         reserved_at_1[0x1b];
10757 	u8         host_buses[0x4];
10758 
10759 	u8         reserved_at_20[0x20];
10760 
10761 	u8         local_port[0x8];
10762 	u8         reserved_at_28[0x18];
10763 
10764 	u8         reserved_at_60[0x20];
10765 };
10766 
10767 enum {
10768 	MLX5_MTUTC_FREQ_ADJ_UNITS_PPB          = 0x0,
10769 	MLX5_MTUTC_FREQ_ADJ_UNITS_SCALED_PPM   = 0x1,
10770 };
10771 
10772 enum {
10773 	MLX5_MTUTC_OPERATION_SET_TIME_IMMEDIATE   = 0x1,
10774 	MLX5_MTUTC_OPERATION_ADJUST_TIME          = 0x2,
10775 	MLX5_MTUTC_OPERATION_ADJUST_FREQ_UTC      = 0x3,
10776 };
10777 
10778 struct mlx5_ifc_mtutc_reg_bits {
10779 	u8         reserved_at_0[0x5];
10780 	u8         freq_adj_units[0x3];
10781 	u8         reserved_at_8[0x3];
10782 	u8         log_max_freq_adjustment[0x5];
10783 
10784 	u8         reserved_at_10[0xc];
10785 	u8         operation[0x4];
10786 
10787 	u8         freq_adjustment[0x20];
10788 
10789 	u8         reserved_at_40[0x40];
10790 
10791 	u8         utc_sec[0x20];
10792 
10793 	u8         reserved_at_a0[0x2];
10794 	u8         utc_nsec[0x1e];
10795 
10796 	u8         time_adjustment[0x20];
10797 };
10798 
10799 struct mlx5_ifc_pcam_enhanced_features_bits {
10800 	u8         reserved_at_0[0x10];
10801 	u8         ppcnt_recovery_counters[0x1];
10802 	u8         reserved_at_11[0x7];
10803 	u8	   cable_length[0x1];
10804 	u8	   reserved_at_19[0x4];
10805 	u8         fec_200G_per_lane_in_pplm[0x1];
10806 	u8         reserved_at_1e[0x2a];
10807 	u8         fec_100G_per_lane_in_pplm[0x1];
10808 	u8         reserved_at_49[0xa];
10809 	u8	   buffer_ownership[0x1];
10810 	u8	   resereved_at_54[0x14];
10811 	u8         fec_50G_per_lane_in_pplm[0x1];
10812 	u8         reserved_at_69[0x4];
10813 	u8         rx_icrc_encapsulated_counter[0x1];
10814 	u8	   reserved_at_6e[0x4];
10815 	u8         ptys_extended_ethernet[0x1];
10816 	u8	   reserved_at_73[0x3];
10817 	u8         pfcc_mask[0x1];
10818 	u8         reserved_at_77[0x3];
10819 	u8         per_lane_error_counters[0x1];
10820 	u8         rx_buffer_fullness_counters[0x1];
10821 	u8         ptys_connector_type[0x1];
10822 	u8         reserved_at_7d[0x1];
10823 	u8         ppcnt_discard_group[0x1];
10824 	u8         ppcnt_statistical_group[0x1];
10825 };
10826 
10827 struct mlx5_ifc_pcam_regs_5000_to_507f_bits {
10828 	u8         port_access_reg_cap_mask_127_to_96[0x20];
10829 	u8         port_access_reg_cap_mask_95_to_64[0x20];
10830 
10831 	u8         port_access_reg_cap_mask_63_to_36[0x1c];
10832 	u8         pplm[0x1];
10833 	u8         port_access_reg_cap_mask_34_to_32[0x3];
10834 
10835 	u8         port_access_reg_cap_mask_31_to_13[0x13];
10836 	u8         pbmc[0x1];
10837 	u8         pptb[0x1];
10838 	u8         port_access_reg_cap_mask_10_to_09[0x2];
10839 	u8         ppcnt[0x1];
10840 	u8         port_access_reg_cap_mask_07_to_00[0x8];
10841 };
10842 
10843 struct mlx5_ifc_pcam_reg_bits {
10844 	u8         reserved_at_0[0x8];
10845 	u8         feature_group[0x8];
10846 	u8         reserved_at_10[0x8];
10847 	u8         access_reg_group[0x8];
10848 
10849 	u8         reserved_at_20[0x20];
10850 
10851 	union {
10852 		struct mlx5_ifc_pcam_regs_5000_to_507f_bits regs_5000_to_507f;
10853 		u8         reserved_at_0[0x80];
10854 	} port_access_reg_cap_mask;
10855 
10856 	u8         reserved_at_c0[0x80];
10857 
10858 	union {
10859 		struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features;
10860 		u8         reserved_at_0[0x80];
10861 	} feature_cap_mask;
10862 
10863 	u8         reserved_at_1c0[0xc0];
10864 };
10865 
10866 struct mlx5_ifc_mcam_enhanced_features_bits {
10867 	u8         reserved_at_0[0x50];
10868 	u8         mtutc_freq_adj_units[0x1];
10869 	u8         mtutc_time_adjustment_extended_range[0x1];
10870 	u8         reserved_at_52[0xb];
10871 	u8         mcia_32dwords[0x1];
10872 	u8         out_pulse_duration_ns[0x1];
10873 	u8         npps_period[0x1];
10874 	u8         reserved_at_60[0xa];
10875 	u8         reset_state[0x1];
10876 	u8         ptpcyc2realtime_modify[0x1];
10877 	u8         reserved_at_6c[0x2];
10878 	u8         pci_status_and_power[0x1];
10879 	u8         reserved_at_6f[0x5];
10880 	u8         mark_tx_action_cnp[0x1];
10881 	u8         mark_tx_action_cqe[0x1];
10882 	u8         dynamic_tx_overflow[0x1];
10883 	u8         reserved_at_77[0x4];
10884 	u8         pcie_outbound_stalled[0x1];
10885 	u8         tx_overflow_buffer_pkt[0x1];
10886 	u8         mtpps_enh_out_per_adj[0x1];
10887 	u8         mtpps_fs[0x1];
10888 	u8         pcie_performance_group[0x1];
10889 };
10890 
10891 struct mlx5_ifc_mcam_access_reg_bits {
10892 	u8         reserved_at_0[0x1c];
10893 	u8         mcda[0x1];
10894 	u8         mcc[0x1];
10895 	u8         mcqi[0x1];
10896 	u8         mcqs[0x1];
10897 
10898 	u8         regs_95_to_90[0x6];
10899 	u8         mpir[0x1];
10900 	u8         regs_88_to_87[0x2];
10901 	u8         mpegc[0x1];
10902 	u8         mtutc[0x1];
10903 	u8         regs_84_to_68[0x11];
10904 	u8         tracer_registers[0x4];
10905 
10906 	u8         regs_63_to_46[0x12];
10907 	u8         mrtc[0x1];
10908 	u8         regs_44_to_41[0x4];
10909 	u8         mfrl[0x1];
10910 	u8         regs_39_to_32[0x8];
10911 
10912 	u8         regs_31_to_11[0x15];
10913 	u8         mtmp[0x1];
10914 	u8         regs_9_to_0[0xa];
10915 };
10916 
10917 struct mlx5_ifc_mcam_access_reg_bits1 {
10918 	u8         regs_127_to_96[0x20];
10919 
10920 	u8         regs_95_to_64[0x20];
10921 
10922 	u8         regs_63_to_32[0x20];
10923 
10924 	u8         regs_31_to_0[0x20];
10925 };
10926 
10927 struct mlx5_ifc_mcam_access_reg_bits2 {
10928 	u8         regs_127_to_99[0x1d];
10929 	u8         mirc[0x1];
10930 	u8         regs_97_to_96[0x2];
10931 
10932 	u8         regs_95_to_87[0x09];
10933 	u8         synce_registers[0x2];
10934 	u8         regs_84_to_64[0x15];
10935 
10936 	u8         regs_63_to_32[0x20];
10937 
10938 	u8         regs_31_to_0[0x20];
10939 };
10940 
10941 struct mlx5_ifc_mcam_access_reg_bits3 {
10942 	u8         regs_127_to_96[0x20];
10943 
10944 	u8         regs_95_to_64[0x20];
10945 
10946 	u8         regs_63_to_32[0x20];
10947 
10948 	u8         regs_31_to_3[0x1d];
10949 	u8         mrtcq[0x1];
10950 	u8         mtctr[0x1];
10951 	u8         mtptm[0x1];
10952 };
10953 
10954 struct mlx5_ifc_mcam_reg_bits {
10955 	u8         reserved_at_0[0x8];
10956 	u8         feature_group[0x8];
10957 	u8         reserved_at_10[0x8];
10958 	u8         access_reg_group[0x8];
10959 
10960 	u8         reserved_at_20[0x20];
10961 
10962 	union {
10963 		struct mlx5_ifc_mcam_access_reg_bits access_regs;
10964 		struct mlx5_ifc_mcam_access_reg_bits1 access_regs1;
10965 		struct mlx5_ifc_mcam_access_reg_bits2 access_regs2;
10966 		struct mlx5_ifc_mcam_access_reg_bits3 access_regs3;
10967 		u8         reserved_at_0[0x80];
10968 	} mng_access_reg_cap_mask;
10969 
10970 	u8         reserved_at_c0[0x80];
10971 
10972 	union {
10973 		struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features;
10974 		u8         reserved_at_0[0x80];
10975 	} mng_feature_cap_mask;
10976 
10977 	u8         reserved_at_1c0[0x80];
10978 };
10979 
10980 struct mlx5_ifc_qcam_access_reg_cap_mask {
10981 	u8         qcam_access_reg_cap_mask_127_to_20[0x6C];
10982 	u8         qpdpm[0x1];
10983 	u8         qcam_access_reg_cap_mask_18_to_4[0x0F];
10984 	u8         qdpm[0x1];
10985 	u8         qpts[0x1];
10986 	u8         qcap[0x1];
10987 	u8         qcam_access_reg_cap_mask_0[0x1];
10988 };
10989 
10990 struct mlx5_ifc_qcam_qos_feature_cap_mask {
10991 	u8         qcam_qos_feature_cap_mask_127_to_1[0x7F];
10992 	u8         qpts_trust_both[0x1];
10993 };
10994 
10995 struct mlx5_ifc_qcam_reg_bits {
10996 	u8         reserved_at_0[0x8];
10997 	u8         feature_group[0x8];
10998 	u8         reserved_at_10[0x8];
10999 	u8         access_reg_group[0x8];
11000 	u8         reserved_at_20[0x20];
11001 
11002 	union {
11003 		struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap;
11004 		u8  reserved_at_0[0x80];
11005 	} qos_access_reg_cap_mask;
11006 
11007 	u8         reserved_at_c0[0x80];
11008 
11009 	union {
11010 		struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap;
11011 		u8  reserved_at_0[0x80];
11012 	} qos_feature_cap_mask;
11013 
11014 	u8         reserved_at_1c0[0x80];
11015 };
11016 
11017 struct mlx5_ifc_core_dump_reg_bits {
11018 	u8         reserved_at_0[0x18];
11019 	u8         core_dump_type[0x8];
11020 
11021 	u8         reserved_at_20[0x30];
11022 	u8         vhca_id[0x10];
11023 
11024 	u8         reserved_at_60[0x8];
11025 	u8         qpn[0x18];
11026 	u8         reserved_at_80[0x180];
11027 };
11028 
11029 struct mlx5_ifc_pcap_reg_bits {
11030 	u8         reserved_at_0[0x8];
11031 	u8         local_port[0x8];
11032 	u8         reserved_at_10[0x10];
11033 
11034 	u8         port_capability_mask[4][0x20];
11035 };
11036 
11037 struct mlx5_ifc_paos_reg_bits {
11038 	u8         swid[0x8];
11039 	u8         local_port[0x8];
11040 	u8         reserved_at_10[0x4];
11041 	u8         admin_status[0x4];
11042 	u8         reserved_at_18[0x4];
11043 	u8         oper_status[0x4];
11044 
11045 	u8         ase[0x1];
11046 	u8         ee[0x1];
11047 	u8         reserved_at_22[0x1c];
11048 	u8         e[0x2];
11049 
11050 	u8         reserved_at_40[0x40];
11051 };
11052 
11053 struct mlx5_ifc_pamp_reg_bits {
11054 	u8         reserved_at_0[0x8];
11055 	u8         opamp_group[0x8];
11056 	u8         reserved_at_10[0xc];
11057 	u8         opamp_group_type[0x4];
11058 
11059 	u8         start_index[0x10];
11060 	u8         reserved_at_30[0x4];
11061 	u8         num_of_indices[0xc];
11062 
11063 	u8         index_data[18][0x10];
11064 };
11065 
11066 struct mlx5_ifc_pcmr_reg_bits {
11067 	u8         reserved_at_0[0x8];
11068 	u8         local_port[0x8];
11069 	u8         reserved_at_10[0x10];
11070 
11071 	u8         entropy_force_cap[0x1];
11072 	u8         entropy_calc_cap[0x1];
11073 	u8         entropy_gre_calc_cap[0x1];
11074 	u8         reserved_at_23[0xf];
11075 	u8         rx_ts_over_crc_cap[0x1];
11076 	u8         reserved_at_33[0xb];
11077 	u8         fcs_cap[0x1];
11078 	u8         reserved_at_3f[0x1];
11079 
11080 	u8         entropy_force[0x1];
11081 	u8         entropy_calc[0x1];
11082 	u8         entropy_gre_calc[0x1];
11083 	u8         reserved_at_43[0xf];
11084 	u8         rx_ts_over_crc[0x1];
11085 	u8         reserved_at_53[0xb];
11086 	u8         fcs_chk[0x1];
11087 	u8         reserved_at_5f[0x1];
11088 };
11089 
11090 struct mlx5_ifc_lane_2_module_mapping_bits {
11091 	u8         reserved_at_0[0x4];
11092 	u8         rx_lane[0x4];
11093 	u8         reserved_at_8[0x4];
11094 	u8         tx_lane[0x4];
11095 	u8         reserved_at_10[0x8];
11096 	u8         module[0x8];
11097 };
11098 
11099 struct mlx5_ifc_bufferx_reg_bits {
11100 	u8         reserved_at_0[0x6];
11101 	u8         lossy[0x1];
11102 	u8         epsb[0x1];
11103 	u8         reserved_at_8[0x8];
11104 	u8         size[0x10];
11105 
11106 	u8         xoff_threshold[0x10];
11107 	u8         xon_threshold[0x10];
11108 };
11109 
11110 struct mlx5_ifc_set_node_in_bits {
11111 	u8         node_description[64][0x8];
11112 };
11113 
11114 struct mlx5_ifc_register_power_settings_bits {
11115 	u8         reserved_at_0[0x18];
11116 	u8         power_settings_level[0x8];
11117 
11118 	u8         reserved_at_20[0x60];
11119 };
11120 
11121 struct mlx5_ifc_register_host_endianness_bits {
11122 	u8         he[0x1];
11123 	u8         reserved_at_1[0x1f];
11124 
11125 	u8         reserved_at_20[0x60];
11126 };
11127 
11128 struct mlx5_ifc_umr_pointer_desc_argument_bits {
11129 	u8         reserved_at_0[0x20];
11130 
11131 	u8         mkey[0x20];
11132 
11133 	u8         addressh_63_32[0x20];
11134 
11135 	u8         addressl_31_0[0x20];
11136 };
11137 
11138 struct mlx5_ifc_ud_adrs_vector_bits {
11139 	u8         dc_key[0x40];
11140 
11141 	u8         ext[0x1];
11142 	u8         reserved_at_41[0x7];
11143 	u8         destination_qp_dct[0x18];
11144 
11145 	u8         static_rate[0x4];
11146 	u8         sl_eth_prio[0x4];
11147 	u8         fl[0x1];
11148 	u8         mlid[0x7];
11149 	u8         rlid_udp_sport[0x10];
11150 
11151 	u8         reserved_at_80[0x20];
11152 
11153 	u8         rmac_47_16[0x20];
11154 
11155 	u8         rmac_15_0[0x10];
11156 	u8         tclass[0x8];
11157 	u8         hop_limit[0x8];
11158 
11159 	u8         reserved_at_e0[0x1];
11160 	u8         grh[0x1];
11161 	u8         reserved_at_e2[0x2];
11162 	u8         src_addr_index[0x8];
11163 	u8         flow_label[0x14];
11164 
11165 	u8         rgid_rip[16][0x8];
11166 };
11167 
11168 struct mlx5_ifc_pages_req_event_bits {
11169 	u8         reserved_at_0[0x10];
11170 	u8         function_id[0x10];
11171 
11172 	u8         num_pages[0x20];
11173 
11174 	u8         reserved_at_40[0xa0];
11175 };
11176 
11177 struct mlx5_ifc_eqe_bits {
11178 	u8         reserved_at_0[0x8];
11179 	u8         event_type[0x8];
11180 	u8         reserved_at_10[0x8];
11181 	u8         event_sub_type[0x8];
11182 
11183 	u8         reserved_at_20[0xe0];
11184 
11185 	union mlx5_ifc_event_auto_bits event_data;
11186 
11187 	u8         reserved_at_1e0[0x10];
11188 	u8         signature[0x8];
11189 	u8         reserved_at_1f8[0x7];
11190 	u8         owner[0x1];
11191 };
11192 
11193 enum {
11194 	MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT  = 0x7,
11195 };
11196 
11197 struct mlx5_ifc_cmd_queue_entry_bits {
11198 	u8         type[0x8];
11199 	u8         reserved_at_8[0x18];
11200 
11201 	u8         input_length[0x20];
11202 
11203 	u8         input_mailbox_pointer_63_32[0x20];
11204 
11205 	u8         input_mailbox_pointer_31_9[0x17];
11206 	u8         reserved_at_77[0x9];
11207 
11208 	u8         command_input_inline_data[16][0x8];
11209 
11210 	u8         command_output_inline_data[16][0x8];
11211 
11212 	u8         output_mailbox_pointer_63_32[0x20];
11213 
11214 	u8         output_mailbox_pointer_31_9[0x17];
11215 	u8         reserved_at_1b7[0x9];
11216 
11217 	u8         output_length[0x20];
11218 
11219 	u8         token[0x8];
11220 	u8         signature[0x8];
11221 	u8         reserved_at_1f0[0x8];
11222 	u8         status[0x7];
11223 	u8         ownership[0x1];
11224 };
11225 
11226 struct mlx5_ifc_cmd_out_bits {
11227 	u8         status[0x8];
11228 	u8         reserved_at_8[0x18];
11229 
11230 	u8         syndrome[0x20];
11231 
11232 	u8         command_output[0x20];
11233 };
11234 
11235 struct mlx5_ifc_cmd_in_bits {
11236 	u8         opcode[0x10];
11237 	u8         reserved_at_10[0x10];
11238 
11239 	u8         reserved_at_20[0x10];
11240 	u8         op_mod[0x10];
11241 
11242 	u8         command[][0x20];
11243 };
11244 
11245 struct mlx5_ifc_cmd_if_box_bits {
11246 	u8         mailbox_data[512][0x8];
11247 
11248 	u8         reserved_at_1000[0x180];
11249 
11250 	u8         next_pointer_63_32[0x20];
11251 
11252 	u8         next_pointer_31_10[0x16];
11253 	u8         reserved_at_11b6[0xa];
11254 
11255 	u8         block_number[0x20];
11256 
11257 	u8         reserved_at_11e0[0x8];
11258 	u8         token[0x8];
11259 	u8         ctrl_signature[0x8];
11260 	u8         signature[0x8];
11261 };
11262 
11263 struct mlx5_ifc_mtt_bits {
11264 	u8         ptag_63_32[0x20];
11265 
11266 	u8         ptag_31_8[0x18];
11267 	u8         reserved_at_38[0x6];
11268 	u8         wr_en[0x1];
11269 	u8         rd_en[0x1];
11270 };
11271 
11272 struct mlx5_ifc_query_wol_rol_out_bits {
11273 	u8         status[0x8];
11274 	u8         reserved_at_8[0x18];
11275 
11276 	u8         syndrome[0x20];
11277 
11278 	u8         reserved_at_40[0x10];
11279 	u8         rol_mode[0x8];
11280 	u8         wol_mode[0x8];
11281 
11282 	u8         reserved_at_60[0x20];
11283 };
11284 
11285 struct mlx5_ifc_query_wol_rol_in_bits {
11286 	u8         opcode[0x10];
11287 	u8         reserved_at_10[0x10];
11288 
11289 	u8         reserved_at_20[0x10];
11290 	u8         op_mod[0x10];
11291 
11292 	u8         reserved_at_40[0x40];
11293 };
11294 
11295 struct mlx5_ifc_set_wol_rol_out_bits {
11296 	u8         status[0x8];
11297 	u8         reserved_at_8[0x18];
11298 
11299 	u8         syndrome[0x20];
11300 
11301 	u8         reserved_at_40[0x40];
11302 };
11303 
11304 struct mlx5_ifc_set_wol_rol_in_bits {
11305 	u8         opcode[0x10];
11306 	u8         reserved_at_10[0x10];
11307 
11308 	u8         reserved_at_20[0x10];
11309 	u8         op_mod[0x10];
11310 
11311 	u8         rol_mode_valid[0x1];
11312 	u8         wol_mode_valid[0x1];
11313 	u8         reserved_at_42[0xe];
11314 	u8         rol_mode[0x8];
11315 	u8         wol_mode[0x8];
11316 
11317 	u8         reserved_at_60[0x20];
11318 };
11319 
11320 enum {
11321 	MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER  = 0x0,
11322 	MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED     = 0x1,
11323 	MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC  = 0x2,
11324 	MLX5_INITIAL_SEG_NIC_INTERFACE_SW_RESET     = 0x7,
11325 };
11326 
11327 enum {
11328 	MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER  = 0x0,
11329 	MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED     = 0x1,
11330 	MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC  = 0x2,
11331 };
11332 
11333 enum {
11334 	MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR              = 0x1,
11335 	MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC                   = 0x7,
11336 	MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR                 = 0x8,
11337 	MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR                   = 0x9,
11338 	MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR            = 0xa,
11339 	MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR                 = 0xb,
11340 	MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN  = 0xc,
11341 	MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR                    = 0xd,
11342 	MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV                       = 0xe,
11343 	MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR                    = 0xf,
11344 	MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR                = 0x10,
11345 	MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PCI_POISONED_ERR         = 0x12,
11346 	MLX5_INITIAL_SEG_HEALTH_SYNDROME_TRUST_LOCKDOWN_ERR           = 0x13,
11347 };
11348 
11349 struct mlx5_ifc_initial_seg_bits {
11350 	u8         fw_rev_minor[0x10];
11351 	u8         fw_rev_major[0x10];
11352 
11353 	u8         cmd_interface_rev[0x10];
11354 	u8         fw_rev_subminor[0x10];
11355 
11356 	u8         reserved_at_40[0x40];
11357 
11358 	u8         cmdq_phy_addr_63_32[0x20];
11359 
11360 	u8         cmdq_phy_addr_31_12[0x14];
11361 	u8         reserved_at_b4[0x2];
11362 	u8         nic_interface[0x2];
11363 	u8         log_cmdq_size[0x4];
11364 	u8         log_cmdq_stride[0x4];
11365 
11366 	u8         command_doorbell_vector[0x20];
11367 
11368 	u8         reserved_at_e0[0xf00];
11369 
11370 	u8         initializing[0x1];
11371 	u8         reserved_at_fe1[0x4];
11372 	u8         nic_interface_supported[0x3];
11373 	u8         embedded_cpu[0x1];
11374 	u8         reserved_at_fe9[0x17];
11375 
11376 	struct mlx5_ifc_health_buffer_bits health_buffer;
11377 
11378 	u8         no_dram_nic_offset[0x20];
11379 
11380 	u8         reserved_at_1220[0x6e40];
11381 
11382 	u8         reserved_at_8060[0x1f];
11383 	u8         clear_int[0x1];
11384 
11385 	u8         health_syndrome[0x8];
11386 	u8         health_counter[0x18];
11387 
11388 	u8         reserved_at_80a0[0x17fc0];
11389 };
11390 
11391 struct mlx5_ifc_mtpps_reg_bits {
11392 	u8         reserved_at_0[0xc];
11393 	u8         cap_number_of_pps_pins[0x4];
11394 	u8         reserved_at_10[0x4];
11395 	u8         cap_max_num_of_pps_in_pins[0x4];
11396 	u8         reserved_at_18[0x4];
11397 	u8         cap_max_num_of_pps_out_pins[0x4];
11398 
11399 	u8         reserved_at_20[0x13];
11400 	u8         cap_log_min_npps_period[0x5];
11401 	u8         reserved_at_38[0x3];
11402 	u8         cap_log_min_out_pulse_duration_ns[0x5];
11403 
11404 	u8         reserved_at_40[0x4];
11405 	u8         cap_pin_3_mode[0x4];
11406 	u8         reserved_at_48[0x4];
11407 	u8         cap_pin_2_mode[0x4];
11408 	u8         reserved_at_50[0x4];
11409 	u8         cap_pin_1_mode[0x4];
11410 	u8         reserved_at_58[0x4];
11411 	u8         cap_pin_0_mode[0x4];
11412 
11413 	u8         reserved_at_60[0x4];
11414 	u8         cap_pin_7_mode[0x4];
11415 	u8         reserved_at_68[0x4];
11416 	u8         cap_pin_6_mode[0x4];
11417 	u8         reserved_at_70[0x4];
11418 	u8         cap_pin_5_mode[0x4];
11419 	u8         reserved_at_78[0x4];
11420 	u8         cap_pin_4_mode[0x4];
11421 
11422 	u8         field_select[0x20];
11423 	u8         reserved_at_a0[0x20];
11424 
11425 	u8         npps_period[0x40];
11426 
11427 	u8         enable[0x1];
11428 	u8         reserved_at_101[0xb];
11429 	u8         pattern[0x4];
11430 	u8         reserved_at_110[0x4];
11431 	u8         pin_mode[0x4];
11432 	u8         pin[0x8];
11433 
11434 	u8         reserved_at_120[0x2];
11435 	u8         out_pulse_duration_ns[0x1e];
11436 
11437 	u8         time_stamp[0x40];
11438 
11439 	u8         out_pulse_duration[0x10];
11440 	u8         out_periodic_adjustment[0x10];
11441 	u8         enhanced_out_periodic_adjustment[0x20];
11442 
11443 	u8         reserved_at_1c0[0x20];
11444 };
11445 
11446 struct mlx5_ifc_mtppse_reg_bits {
11447 	u8         reserved_at_0[0x18];
11448 	u8         pin[0x8];
11449 	u8         event_arm[0x1];
11450 	u8         reserved_at_21[0x1b];
11451 	u8         event_generation_mode[0x4];
11452 	u8         reserved_at_40[0x40];
11453 };
11454 
11455 struct mlx5_ifc_mcqs_reg_bits {
11456 	u8         last_index_flag[0x1];
11457 	u8         reserved_at_1[0x7];
11458 	u8         fw_device[0x8];
11459 	u8         component_index[0x10];
11460 
11461 	u8         reserved_at_20[0x10];
11462 	u8         identifier[0x10];
11463 
11464 	u8         reserved_at_40[0x17];
11465 	u8         component_status[0x5];
11466 	u8         component_update_state[0x4];
11467 
11468 	u8         last_update_state_changer_type[0x4];
11469 	u8         last_update_state_changer_host_id[0x4];
11470 	u8         reserved_at_68[0x18];
11471 };
11472 
11473 struct mlx5_ifc_mcqi_cap_bits {
11474 	u8         supported_info_bitmask[0x20];
11475 
11476 	u8         component_size[0x20];
11477 
11478 	u8         max_component_size[0x20];
11479 
11480 	u8         log_mcda_word_size[0x4];
11481 	u8         reserved_at_64[0xc];
11482 	u8         mcda_max_write_size[0x10];
11483 
11484 	u8         rd_en[0x1];
11485 	u8         reserved_at_81[0x1];
11486 	u8         match_chip_id[0x1];
11487 	u8         match_psid[0x1];
11488 	u8         check_user_timestamp[0x1];
11489 	u8         match_base_guid_mac[0x1];
11490 	u8         reserved_at_86[0x1a];
11491 };
11492 
11493 struct mlx5_ifc_mcqi_version_bits {
11494 	u8         reserved_at_0[0x2];
11495 	u8         build_time_valid[0x1];
11496 	u8         user_defined_time_valid[0x1];
11497 	u8         reserved_at_4[0x14];
11498 	u8         version_string_length[0x8];
11499 
11500 	u8         version[0x20];
11501 
11502 	u8         build_time[0x40];
11503 
11504 	u8         user_defined_time[0x40];
11505 
11506 	u8         build_tool_version[0x20];
11507 
11508 	u8         reserved_at_e0[0x20];
11509 
11510 	u8         version_string[92][0x8];
11511 };
11512 
11513 struct mlx5_ifc_mcqi_activation_method_bits {
11514 	u8         pending_server_ac_power_cycle[0x1];
11515 	u8         pending_server_dc_power_cycle[0x1];
11516 	u8         pending_server_reboot[0x1];
11517 	u8         pending_fw_reset[0x1];
11518 	u8         auto_activate[0x1];
11519 	u8         all_hosts_sync[0x1];
11520 	u8         device_hw_reset[0x1];
11521 	u8         reserved_at_7[0x19];
11522 };
11523 
11524 union mlx5_ifc_mcqi_reg_data_bits {
11525 	struct mlx5_ifc_mcqi_cap_bits               mcqi_caps;
11526 	struct mlx5_ifc_mcqi_version_bits           mcqi_version;
11527 	struct mlx5_ifc_mcqi_activation_method_bits mcqi_activation_mathod;
11528 };
11529 
11530 struct mlx5_ifc_mcqi_reg_bits {
11531 	u8         read_pending_component[0x1];
11532 	u8         reserved_at_1[0xf];
11533 	u8         component_index[0x10];
11534 
11535 	u8         reserved_at_20[0x20];
11536 
11537 	u8         reserved_at_40[0x1b];
11538 	u8         info_type[0x5];
11539 
11540 	u8         info_size[0x20];
11541 
11542 	u8         offset[0x20];
11543 
11544 	u8         reserved_at_a0[0x10];
11545 	u8         data_size[0x10];
11546 
11547 	union mlx5_ifc_mcqi_reg_data_bits data[];
11548 };
11549 
11550 struct mlx5_ifc_mcc_reg_bits {
11551 	u8         reserved_at_0[0x4];
11552 	u8         time_elapsed_since_last_cmd[0xc];
11553 	u8         reserved_at_10[0x8];
11554 	u8         instruction[0x8];
11555 
11556 	u8         reserved_at_20[0x10];
11557 	u8         component_index[0x10];
11558 
11559 	u8         reserved_at_40[0x8];
11560 	u8         update_handle[0x18];
11561 
11562 	u8         handle_owner_type[0x4];
11563 	u8         handle_owner_host_id[0x4];
11564 	u8         reserved_at_68[0x1];
11565 	u8         control_progress[0x7];
11566 	u8         error_code[0x8];
11567 	u8         reserved_at_78[0x4];
11568 	u8         control_state[0x4];
11569 
11570 	u8         component_size[0x20];
11571 
11572 	u8         reserved_at_a0[0x60];
11573 };
11574 
11575 struct mlx5_ifc_mcda_reg_bits {
11576 	u8         reserved_at_0[0x8];
11577 	u8         update_handle[0x18];
11578 
11579 	u8         offset[0x20];
11580 
11581 	u8         reserved_at_40[0x10];
11582 	u8         size[0x10];
11583 
11584 	u8         reserved_at_60[0x20];
11585 
11586 	u8         data[][0x20];
11587 };
11588 
11589 enum {
11590 	MLX5_MFRL_REG_PCI_RESET_METHOD_LINK_TOGGLE = 0,
11591 	MLX5_MFRL_REG_PCI_RESET_METHOD_HOT_RESET = 1,
11592 };
11593 
11594 enum {
11595 	MLX5_MFRL_REG_RESET_STATE_IDLE = 0,
11596 	MLX5_MFRL_REG_RESET_STATE_IN_NEGOTIATION = 1,
11597 	MLX5_MFRL_REG_RESET_STATE_RESET_IN_PROGRESS = 2,
11598 	MLX5_MFRL_REG_RESET_STATE_NEG_TIMEOUT = 3,
11599 	MLX5_MFRL_REG_RESET_STATE_NACK = 4,
11600 	MLX5_MFRL_REG_RESET_STATE_UNLOAD_TIMEOUT = 5,
11601 };
11602 
11603 enum {
11604 	MLX5_MFRL_REG_RESET_TYPE_FULL_CHIP = BIT(0),
11605 	MLX5_MFRL_REG_RESET_TYPE_NET_PORT_ALIVE = BIT(1),
11606 };
11607 
11608 enum {
11609 	MLX5_MFRL_REG_RESET_LEVEL0 = BIT(0),
11610 	MLX5_MFRL_REG_RESET_LEVEL3 = BIT(3),
11611 	MLX5_MFRL_REG_RESET_LEVEL6 = BIT(6),
11612 };
11613 
11614 struct mlx5_ifc_mfrl_reg_bits {
11615 	u8         reserved_at_0[0x20];
11616 
11617 	u8         reserved_at_20[0x2];
11618 	u8         pci_sync_for_fw_update_start[0x1];
11619 	u8         pci_sync_for_fw_update_resp[0x2];
11620 	u8         rst_type_sel[0x3];
11621 	u8         pci_reset_req_method[0x3];
11622 	u8         reserved_at_2b[0x1];
11623 	u8         reset_state[0x4];
11624 	u8         reset_type[0x8];
11625 	u8         reset_level[0x8];
11626 };
11627 
11628 struct mlx5_ifc_mirc_reg_bits {
11629 	u8         reserved_at_0[0x18];
11630 	u8         status_code[0x8];
11631 
11632 	u8         reserved_at_20[0x20];
11633 };
11634 
11635 struct mlx5_ifc_pddr_monitor_opcode_bits {
11636 	u8         reserved_at_0[0x10];
11637 	u8         monitor_opcode[0x10];
11638 };
11639 
11640 union mlx5_ifc_pddr_troubleshooting_page_status_opcode_auto_bits {
11641 	struct mlx5_ifc_pddr_monitor_opcode_bits pddr_monitor_opcode;
11642 	u8         reserved_at_0[0x20];
11643 };
11644 
11645 enum {
11646 	/* Monitor opcodes */
11647 	MLX5_PDDR_REG_TRBLSH_GROUP_OPCODE_MONITOR = 0x0,
11648 };
11649 
11650 struct mlx5_ifc_pddr_troubleshooting_page_bits {
11651 	u8         reserved_at_0[0x10];
11652 	u8         group_opcode[0x10];
11653 
11654 	union mlx5_ifc_pddr_troubleshooting_page_status_opcode_auto_bits status_opcode;
11655 
11656 	u8         reserved_at_40[0x20];
11657 
11658 	u8         status_message[59][0x20];
11659 };
11660 
11661 union mlx5_ifc_pddr_reg_page_data_auto_bits {
11662 	struct mlx5_ifc_pddr_troubleshooting_page_bits pddr_troubleshooting_page;
11663 	u8         reserved_at_0[0x7c0];
11664 };
11665 
11666 enum {
11667 	MLX5_PDDR_REG_PAGE_SELECT_TROUBLESHOOTING_INFO_PAGE      = 0x1,
11668 };
11669 
11670 struct mlx5_ifc_pddr_reg_bits {
11671 	u8         reserved_at_0[0x8];
11672 	u8         local_port[0x8];
11673 	u8         pnat[0x2];
11674 	u8         reserved_at_12[0xe];
11675 
11676 	u8         reserved_at_20[0x18];
11677 	u8         page_select[0x8];
11678 
11679 	union mlx5_ifc_pddr_reg_page_data_auto_bits page_data;
11680 };
11681 
11682 struct mlx5_ifc_mrtc_reg_bits {
11683 	u8         time_synced[0x1];
11684 	u8         reserved_at_1[0x1f];
11685 
11686 	u8         reserved_at_20[0x20];
11687 
11688 	u8         time_h[0x20];
11689 
11690 	u8         time_l[0x20];
11691 };
11692 
11693 struct mlx5_ifc_mtcap_reg_bits {
11694 	u8         reserved_at_0[0x19];
11695 	u8         sensor_count[0x7];
11696 
11697 	u8         reserved_at_20[0x20];
11698 
11699 	u8         sensor_map[0x40];
11700 };
11701 
11702 struct mlx5_ifc_mtmp_reg_bits {
11703 	u8         reserved_at_0[0x14];
11704 	u8         sensor_index[0xc];
11705 
11706 	u8         reserved_at_20[0x10];
11707 	u8         temperature[0x10];
11708 
11709 	u8         mte[0x1];
11710 	u8         mtr[0x1];
11711 	u8         reserved_at_42[0xe];
11712 	u8         max_temperature[0x10];
11713 
11714 	u8         tee[0x2];
11715 	u8         reserved_at_62[0xe];
11716 	u8         temp_threshold_hi[0x10];
11717 
11718 	u8         reserved_at_80[0x10];
11719 	u8         temp_threshold_lo[0x10];
11720 
11721 	u8         reserved_at_a0[0x20];
11722 
11723 	u8         sensor_name_hi[0x20];
11724 	u8         sensor_name_lo[0x20];
11725 };
11726 
11727 struct mlx5_ifc_mtptm_reg_bits {
11728 	u8         reserved_at_0[0x10];
11729 	u8         psta[0x1];
11730 	u8         reserved_at_11[0xf];
11731 
11732 	u8         reserved_at_20[0x60];
11733 };
11734 
11735 enum {
11736 	MLX5_MTCTR_REQUEST_NOP = 0x0,
11737 	MLX5_MTCTR_REQUEST_PTM_ROOT_CLOCK = 0x1,
11738 	MLX5_MTCTR_REQUEST_FREE_RUNNING_COUNTER = 0x2,
11739 	MLX5_MTCTR_REQUEST_REAL_TIME_CLOCK = 0x3,
11740 };
11741 
11742 struct mlx5_ifc_mtctr_reg_bits {
11743 	u8         first_clock_timestamp_request[0x8];
11744 	u8         second_clock_timestamp_request[0x8];
11745 	u8         reserved_at_10[0x10];
11746 
11747 	u8         first_clock_valid[0x1];
11748 	u8         second_clock_valid[0x1];
11749 	u8         reserved_at_22[0x1e];
11750 
11751 	u8         first_clock_timestamp[0x40];
11752 	u8         second_clock_timestamp[0x40];
11753 };
11754 
11755 struct mlx5_ifc_bin_range_layout_bits {
11756 	u8         reserved_at_0[0xa];
11757 	u8         high_val[0x6];
11758 	u8         reserved_at_10[0xa];
11759 	u8         low_val[0x6];
11760 };
11761 
11762 struct mlx5_ifc_pphcr_reg_bits {
11763 	u8         active_hist_type[0x4];
11764 	u8         reserved_at_4[0x4];
11765 	u8         local_port[0x8];
11766 	u8         reserved_at_10[0x10];
11767 
11768 	u8         reserved_at_20[0x8];
11769 	u8         num_of_bins[0x8];
11770 	u8         reserved_at_30[0x10];
11771 
11772 	u8         reserved_at_40[0x40];
11773 
11774 	struct mlx5_ifc_bin_range_layout_bits bin_range[16];
11775 };
11776 
11777 union mlx5_ifc_ports_control_registers_document_bits {
11778 	struct mlx5_ifc_bufferx_reg_bits bufferx_reg;
11779 	struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
11780 	struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
11781 	struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
11782 	struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
11783 	struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
11784 	struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
11785 	struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout;
11786 	struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout;
11787 	struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping;
11788 	struct mlx5_ifc_pamp_reg_bits pamp_reg;
11789 	struct mlx5_ifc_paos_reg_bits paos_reg;
11790 	struct mlx5_ifc_pcap_reg_bits pcap_reg;
11791 	struct mlx5_ifc_pddr_monitor_opcode_bits pddr_monitor_opcode;
11792 	struct mlx5_ifc_pddr_reg_bits pddr_reg;
11793 	struct mlx5_ifc_pddr_troubleshooting_page_bits pddr_troubleshooting_page;
11794 	struct mlx5_ifc_peir_reg_bits peir_reg;
11795 	struct mlx5_ifc_pelc_reg_bits pelc_reg;
11796 	struct mlx5_ifc_pfcc_reg_bits pfcc_reg;
11797 	struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
11798 	struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
11799 	struct mlx5_ifc_pifr_reg_bits pifr_reg;
11800 	struct mlx5_ifc_pipg_reg_bits pipg_reg;
11801 	struct mlx5_ifc_plbf_reg_bits plbf_reg;
11802 	struct mlx5_ifc_plib_reg_bits plib_reg;
11803 	struct mlx5_ifc_plpc_reg_bits plpc_reg;
11804 	struct mlx5_ifc_pmaos_reg_bits pmaos_reg;
11805 	struct mlx5_ifc_pmlp_reg_bits pmlp_reg;
11806 	struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg;
11807 	struct mlx5_ifc_pmpc_reg_bits pmpc_reg;
11808 	struct mlx5_ifc_pmpe_reg_bits pmpe_reg;
11809 	struct mlx5_ifc_pmpr_reg_bits pmpr_reg;
11810 	struct mlx5_ifc_pmtu_reg_bits pmtu_reg;
11811 	struct mlx5_ifc_ppad_reg_bits ppad_reg;
11812 	struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg;
11813 	struct mlx5_ifc_mpein_reg_bits mpein_reg;
11814 	struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg;
11815 	struct mlx5_ifc_pplm_reg_bits pplm_reg;
11816 	struct mlx5_ifc_pplr_reg_bits pplr_reg;
11817 	struct mlx5_ifc_ppsc_reg_bits ppsc_reg;
11818 	struct mlx5_ifc_pqdr_reg_bits pqdr_reg;
11819 	struct mlx5_ifc_pspa_reg_bits pspa_reg;
11820 	struct mlx5_ifc_ptas_reg_bits ptas_reg;
11821 	struct mlx5_ifc_ptys_reg_bits ptys_reg;
11822 	struct mlx5_ifc_mlcr_reg_bits mlcr_reg;
11823 	struct mlx5_ifc_pude_reg_bits pude_reg;
11824 	struct mlx5_ifc_pvlc_reg_bits pvlc_reg;
11825 	struct mlx5_ifc_slrg_reg_bits slrg_reg;
11826 	struct mlx5_ifc_sltp_reg_bits sltp_reg;
11827 	struct mlx5_ifc_mtpps_reg_bits mtpps_reg;
11828 	struct mlx5_ifc_mtppse_reg_bits mtppse_reg;
11829 	struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg;
11830 	struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits;
11831 	struct mlx5_ifc_fpga_cap_bits fpga_cap_bits;
11832 	struct mlx5_ifc_mcqi_reg_bits mcqi_reg;
11833 	struct mlx5_ifc_mcc_reg_bits mcc_reg;
11834 	struct mlx5_ifc_mcda_reg_bits mcda_reg;
11835 	struct mlx5_ifc_mirc_reg_bits mirc_reg;
11836 	struct mlx5_ifc_mfrl_reg_bits mfrl_reg;
11837 	struct mlx5_ifc_mtutc_reg_bits mtutc_reg;
11838 	struct mlx5_ifc_mrtc_reg_bits mrtc_reg;
11839 	struct mlx5_ifc_mtcap_reg_bits mtcap_reg;
11840 	struct mlx5_ifc_mtmp_reg_bits mtmp_reg;
11841 	struct mlx5_ifc_mtptm_reg_bits mtptm_reg;
11842 	struct mlx5_ifc_mtctr_reg_bits mtctr_reg;
11843 	struct mlx5_ifc_pphcr_reg_bits pphcr_reg;
11844 	u8         reserved_at_0[0x60e0];
11845 };
11846 
11847 union mlx5_ifc_debug_enhancements_document_bits {
11848 	struct mlx5_ifc_health_buffer_bits health_buffer;
11849 	u8         reserved_at_0[0x200];
11850 };
11851 
11852 union mlx5_ifc_uplink_pci_interface_document_bits {
11853 	struct mlx5_ifc_initial_seg_bits initial_seg;
11854 	u8         reserved_at_0[0x20060];
11855 };
11856 
11857 struct mlx5_ifc_set_flow_table_root_out_bits {
11858 	u8         status[0x8];
11859 	u8         reserved_at_8[0x18];
11860 
11861 	u8         syndrome[0x20];
11862 
11863 	u8         reserved_at_40[0x40];
11864 };
11865 
11866 struct mlx5_ifc_set_flow_table_root_in_bits {
11867 	u8         opcode[0x10];
11868 	u8         reserved_at_10[0x10];
11869 
11870 	u8         reserved_at_20[0x10];
11871 	u8         op_mod[0x10];
11872 
11873 	u8         other_vport[0x1];
11874 	u8         reserved_at_41[0xf];
11875 	u8         vport_number[0x10];
11876 
11877 	u8         reserved_at_60[0x20];
11878 
11879 	u8         table_type[0x8];
11880 	u8         reserved_at_88[0x7];
11881 	u8         table_of_other_vport[0x1];
11882 	u8         table_vport_number[0x10];
11883 
11884 	u8         reserved_at_a0[0x8];
11885 	u8         table_id[0x18];
11886 
11887 	u8         reserved_at_c0[0x8];
11888 	u8         underlay_qpn[0x18];
11889 	u8         table_eswitch_owner_vhca_id_valid[0x1];
11890 	u8         reserved_at_e1[0xf];
11891 	u8         table_eswitch_owner_vhca_id[0x10];
11892 	u8         reserved_at_100[0x100];
11893 };
11894 
11895 enum {
11896 	MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID     = (1UL << 0),
11897 	MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15),
11898 };
11899 
11900 struct mlx5_ifc_modify_flow_table_out_bits {
11901 	u8         status[0x8];
11902 	u8         reserved_at_8[0x18];
11903 
11904 	u8         syndrome[0x20];
11905 
11906 	u8         reserved_at_40[0x40];
11907 };
11908 
11909 struct mlx5_ifc_modify_flow_table_in_bits {
11910 	u8         opcode[0x10];
11911 	u8         reserved_at_10[0x10];
11912 
11913 	u8         reserved_at_20[0x10];
11914 	u8         op_mod[0x10];
11915 
11916 	u8         other_vport[0x1];
11917 	u8         reserved_at_41[0xf];
11918 	u8         vport_number[0x10];
11919 
11920 	u8         reserved_at_60[0x10];
11921 	u8         modify_field_select[0x10];
11922 
11923 	u8         table_type[0x8];
11924 	u8         reserved_at_88[0x18];
11925 
11926 	u8         reserved_at_a0[0x8];
11927 	u8         table_id[0x18];
11928 
11929 	struct mlx5_ifc_flow_table_context_bits flow_table_context;
11930 };
11931 
11932 struct mlx5_ifc_ets_tcn_config_reg_bits {
11933 	u8         g[0x1];
11934 	u8         b[0x1];
11935 	u8         r[0x1];
11936 	u8         reserved_at_3[0x9];
11937 	u8         group[0x4];
11938 	u8         reserved_at_10[0x9];
11939 	u8         bw_allocation[0x7];
11940 
11941 	u8         reserved_at_20[0xc];
11942 	u8         max_bw_units[0x4];
11943 	u8         reserved_at_30[0x8];
11944 	u8         max_bw_value[0x8];
11945 };
11946 
11947 struct mlx5_ifc_ets_global_config_reg_bits {
11948 	u8         reserved_at_0[0x2];
11949 	u8         r[0x1];
11950 	u8         reserved_at_3[0x1d];
11951 
11952 	u8         reserved_at_20[0xc];
11953 	u8         max_bw_units[0x4];
11954 	u8         reserved_at_30[0x8];
11955 	u8         max_bw_value[0x8];
11956 };
11957 
11958 struct mlx5_ifc_qetc_reg_bits {
11959 	u8                                         reserved_at_0[0x8];
11960 	u8                                         port_number[0x8];
11961 	u8                                         reserved_at_10[0x30];
11962 
11963 	struct mlx5_ifc_ets_tcn_config_reg_bits    tc_configuration[0x8];
11964 	struct mlx5_ifc_ets_global_config_reg_bits global_configuration;
11965 };
11966 
11967 struct mlx5_ifc_qpdpm_dscp_reg_bits {
11968 	u8         e[0x1];
11969 	u8         reserved_at_01[0x0b];
11970 	u8         prio[0x04];
11971 };
11972 
11973 struct mlx5_ifc_qpdpm_reg_bits {
11974 	u8                                     reserved_at_0[0x8];
11975 	u8                                     local_port[0x8];
11976 	u8                                     reserved_at_10[0x10];
11977 	struct mlx5_ifc_qpdpm_dscp_reg_bits    dscp[64];
11978 };
11979 
11980 struct mlx5_ifc_qpts_reg_bits {
11981 	u8         reserved_at_0[0x8];
11982 	u8         local_port[0x8];
11983 	u8         reserved_at_10[0x2d];
11984 	u8         trust_state[0x3];
11985 };
11986 
11987 struct mlx5_ifc_pptb_reg_bits {
11988 	u8         reserved_at_0[0x2];
11989 	u8         mm[0x2];
11990 	u8         reserved_at_4[0x4];
11991 	u8         local_port[0x8];
11992 	u8         reserved_at_10[0x6];
11993 	u8         cm[0x1];
11994 	u8         um[0x1];
11995 	u8         pm[0x8];
11996 
11997 	u8         prio_x_buff[0x20];
11998 
11999 	u8         pm_msb[0x8];
12000 	u8         reserved_at_48[0x10];
12001 	u8         ctrl_buff[0x4];
12002 	u8         untagged_buff[0x4];
12003 };
12004 
12005 struct mlx5_ifc_sbcam_reg_bits {
12006 	u8         reserved_at_0[0x8];
12007 	u8         feature_group[0x8];
12008 	u8         reserved_at_10[0x8];
12009 	u8         access_reg_group[0x8];
12010 
12011 	u8         reserved_at_20[0x20];
12012 
12013 	u8         sb_access_reg_cap_mask[4][0x20];
12014 
12015 	u8         reserved_at_c0[0x80];
12016 
12017 	u8         sb_feature_cap_mask[4][0x20];
12018 
12019 	u8         reserved_at_1c0[0x40];
12020 
12021 	u8         cap_total_buffer_size[0x20];
12022 
12023 	u8         cap_cell_size[0x10];
12024 	u8         cap_max_pg_buffers[0x8];
12025 	u8         cap_num_pool_supported[0x8];
12026 
12027 	u8         reserved_at_240[0x8];
12028 	u8         cap_sbsr_stat_size[0x8];
12029 	u8         cap_max_tclass_data[0x8];
12030 	u8         cap_max_cpu_ingress_tclass_sb[0x8];
12031 };
12032 
12033 struct mlx5_ifc_pbmc_reg_bits {
12034 	u8         reserved_at_0[0x8];
12035 	u8         local_port[0x8];
12036 	u8         reserved_at_10[0x10];
12037 
12038 	u8         xoff_timer_value[0x10];
12039 	u8         xoff_refresh[0x10];
12040 
12041 	u8         reserved_at_40[0x9];
12042 	u8         fullness_threshold[0x7];
12043 	u8         port_buffer_size[0x10];
12044 
12045 	struct mlx5_ifc_bufferx_reg_bits buffer[10];
12046 
12047 	u8         reserved_at_2e0[0x80];
12048 };
12049 
12050 struct mlx5_ifc_sbpr_reg_bits {
12051 	u8         desc[0x1];
12052 	u8         snap[0x1];
12053 	u8         reserved_at_2[0x4];
12054 	u8         dir[0x2];
12055 	u8         reserved_at_8[0x14];
12056 	u8         pool[0x4];
12057 
12058 	u8         infi_size[0x1];
12059 	u8         reserved_at_21[0x7];
12060 	u8         size[0x18];
12061 
12062 	u8         reserved_at_40[0x1c];
12063 	u8         mode[0x4];
12064 
12065 	u8         reserved_at_60[0x8];
12066 	u8         buff_occupancy[0x18];
12067 
12068 	u8         clr[0x1];
12069 	u8         reserved_at_81[0x7];
12070 	u8         max_buff_occupancy[0x18];
12071 
12072 	u8         reserved_at_a0[0x8];
12073 	u8         ext_buff_occupancy[0x18];
12074 };
12075 
12076 struct mlx5_ifc_sbcm_reg_bits {
12077 	u8         desc[0x1];
12078 	u8         snap[0x1];
12079 	u8         reserved_at_2[0x6];
12080 	u8         local_port[0x8];
12081 	u8         pnat[0x2];
12082 	u8         pg_buff[0x6];
12083 	u8         reserved_at_18[0x6];
12084 	u8         dir[0x2];
12085 
12086 	u8         reserved_at_20[0x1f];
12087 	u8         exc[0x1];
12088 
12089 	u8         reserved_at_40[0x40];
12090 
12091 	u8         reserved_at_80[0x8];
12092 	u8         buff_occupancy[0x18];
12093 
12094 	u8         clr[0x1];
12095 	u8         reserved_at_a1[0x7];
12096 	u8         max_buff_occupancy[0x18];
12097 
12098 	u8         reserved_at_c0[0x8];
12099 	u8         min_buff[0x18];
12100 
12101 	u8         infi_max[0x1];
12102 	u8         reserved_at_e1[0x7];
12103 	u8         max_buff[0x18];
12104 
12105 	u8         reserved_at_100[0x20];
12106 
12107 	u8         reserved_at_120[0x1c];
12108 	u8         pool[0x4];
12109 };
12110 
12111 struct mlx5_ifc_qtct_reg_bits {
12112 	u8         reserved_at_0[0x8];
12113 	u8         port_number[0x8];
12114 	u8         reserved_at_10[0xd];
12115 	u8         prio[0x3];
12116 
12117 	u8         reserved_at_20[0x1d];
12118 	u8         tclass[0x3];
12119 };
12120 
12121 struct mlx5_ifc_mcia_reg_bits {
12122 	u8         l[0x1];
12123 	u8         reserved_at_1[0x7];
12124 	u8         module[0x8];
12125 	u8         reserved_at_10[0x8];
12126 	u8         status[0x8];
12127 
12128 	u8         i2c_device_address[0x8];
12129 	u8         page_number[0x8];
12130 	u8         device_address[0x10];
12131 
12132 	u8         reserved_at_40[0x10];
12133 	u8         size[0x10];
12134 
12135 	u8         reserved_at_60[0x20];
12136 
12137 	u8         dword_0[0x20];
12138 	u8         dword_1[0x20];
12139 	u8         dword_2[0x20];
12140 	u8         dword_3[0x20];
12141 	u8         dword_4[0x20];
12142 	u8         dword_5[0x20];
12143 	u8         dword_6[0x20];
12144 	u8         dword_7[0x20];
12145 	u8         dword_8[0x20];
12146 	u8         dword_9[0x20];
12147 	u8         dword_10[0x20];
12148 	u8         dword_11[0x20];
12149 };
12150 
12151 struct mlx5_ifc_dcbx_param_bits {
12152 	u8         dcbx_cee_cap[0x1];
12153 	u8         dcbx_ieee_cap[0x1];
12154 	u8         dcbx_standby_cap[0x1];
12155 	u8         reserved_at_3[0x5];
12156 	u8         port_number[0x8];
12157 	u8         reserved_at_10[0xa];
12158 	u8         max_application_table_size[6];
12159 	u8         reserved_at_20[0x15];
12160 	u8         version_oper[0x3];
12161 	u8         reserved_at_38[5];
12162 	u8         version_admin[0x3];
12163 	u8         willing_admin[0x1];
12164 	u8         reserved_at_41[0x3];
12165 	u8         pfc_cap_oper[0x4];
12166 	u8         reserved_at_48[0x4];
12167 	u8         pfc_cap_admin[0x4];
12168 	u8         reserved_at_50[0x4];
12169 	u8         num_of_tc_oper[0x4];
12170 	u8         reserved_at_58[0x4];
12171 	u8         num_of_tc_admin[0x4];
12172 	u8         remote_willing[0x1];
12173 	u8         reserved_at_61[3];
12174 	u8         remote_pfc_cap[4];
12175 	u8         reserved_at_68[0x14];
12176 	u8         remote_num_of_tc[0x4];
12177 	u8         reserved_at_80[0x18];
12178 	u8         error[0x8];
12179 	u8         reserved_at_a0[0x160];
12180 };
12181 
12182 enum {
12183 	MLX5_LAG_PORT_SELECT_MODE_QUEUE_AFFINITY = 0,
12184 	MLX5_LAG_PORT_SELECT_MODE_PORT_SELECT_FT = 1,
12185 	MLX5_LAG_PORT_SELECT_MODE_PORT_SELECT_MPESW = 2,
12186 };
12187 
12188 struct mlx5_ifc_lagc_bits {
12189 	u8         fdb_selection_mode[0x1];
12190 	u8         reserved_at_1[0x14];
12191 	u8         port_select_mode[0x3];
12192 	u8         reserved_at_18[0x5];
12193 	u8         lag_state[0x3];
12194 
12195 	u8         reserved_at_20[0xc];
12196 	u8         active_port[0x4];
12197 	u8         reserved_at_30[0x4];
12198 	u8         tx_remap_affinity_2[0x4];
12199 	u8         reserved_at_38[0x4];
12200 	u8         tx_remap_affinity_1[0x4];
12201 };
12202 
12203 struct mlx5_ifc_create_lag_out_bits {
12204 	u8         status[0x8];
12205 	u8         reserved_at_8[0x18];
12206 
12207 	u8         syndrome[0x20];
12208 
12209 	u8         reserved_at_40[0x40];
12210 };
12211 
12212 struct mlx5_ifc_create_lag_in_bits {
12213 	u8         opcode[0x10];
12214 	u8         reserved_at_10[0x10];
12215 
12216 	u8         reserved_at_20[0x10];
12217 	u8         op_mod[0x10];
12218 
12219 	struct mlx5_ifc_lagc_bits ctx;
12220 };
12221 
12222 struct mlx5_ifc_modify_lag_out_bits {
12223 	u8         status[0x8];
12224 	u8         reserved_at_8[0x18];
12225 
12226 	u8         syndrome[0x20];
12227 
12228 	u8         reserved_at_40[0x40];
12229 };
12230 
12231 struct mlx5_ifc_modify_lag_in_bits {
12232 	u8         opcode[0x10];
12233 	u8         reserved_at_10[0x10];
12234 
12235 	u8         reserved_at_20[0x10];
12236 	u8         op_mod[0x10];
12237 
12238 	u8         reserved_at_40[0x20];
12239 	u8         field_select[0x20];
12240 
12241 	struct mlx5_ifc_lagc_bits ctx;
12242 };
12243 
12244 struct mlx5_ifc_query_lag_out_bits {
12245 	u8         status[0x8];
12246 	u8         reserved_at_8[0x18];
12247 
12248 	u8         syndrome[0x20];
12249 
12250 	struct mlx5_ifc_lagc_bits ctx;
12251 };
12252 
12253 struct mlx5_ifc_query_lag_in_bits {
12254 	u8         opcode[0x10];
12255 	u8         reserved_at_10[0x10];
12256 
12257 	u8         reserved_at_20[0x10];
12258 	u8         op_mod[0x10];
12259 
12260 	u8         reserved_at_40[0x40];
12261 };
12262 
12263 struct mlx5_ifc_destroy_lag_out_bits {
12264 	u8         status[0x8];
12265 	u8         reserved_at_8[0x18];
12266 
12267 	u8         syndrome[0x20];
12268 
12269 	u8         reserved_at_40[0x40];
12270 };
12271 
12272 struct mlx5_ifc_destroy_lag_in_bits {
12273 	u8         opcode[0x10];
12274 	u8         reserved_at_10[0x10];
12275 
12276 	u8         reserved_at_20[0x10];
12277 	u8         op_mod[0x10];
12278 
12279 	u8         reserved_at_40[0x40];
12280 };
12281 
12282 struct mlx5_ifc_create_vport_lag_out_bits {
12283 	u8         status[0x8];
12284 	u8         reserved_at_8[0x18];
12285 
12286 	u8         syndrome[0x20];
12287 
12288 	u8         reserved_at_40[0x40];
12289 };
12290 
12291 struct mlx5_ifc_create_vport_lag_in_bits {
12292 	u8         opcode[0x10];
12293 	u8         reserved_at_10[0x10];
12294 
12295 	u8         reserved_at_20[0x10];
12296 	u8         op_mod[0x10];
12297 
12298 	u8         reserved_at_40[0x40];
12299 };
12300 
12301 struct mlx5_ifc_destroy_vport_lag_out_bits {
12302 	u8         status[0x8];
12303 	u8         reserved_at_8[0x18];
12304 
12305 	u8         syndrome[0x20];
12306 
12307 	u8         reserved_at_40[0x40];
12308 };
12309 
12310 struct mlx5_ifc_destroy_vport_lag_in_bits {
12311 	u8         opcode[0x10];
12312 	u8         reserved_at_10[0x10];
12313 
12314 	u8         reserved_at_20[0x10];
12315 	u8         op_mod[0x10];
12316 
12317 	u8         reserved_at_40[0x40];
12318 };
12319 
12320 enum {
12321 	MLX5_MODIFY_MEMIC_OP_MOD_ALLOC,
12322 	MLX5_MODIFY_MEMIC_OP_MOD_DEALLOC,
12323 };
12324 
12325 struct mlx5_ifc_modify_memic_in_bits {
12326 	u8         opcode[0x10];
12327 	u8         uid[0x10];
12328 
12329 	u8         reserved_at_20[0x10];
12330 	u8         op_mod[0x10];
12331 
12332 	u8         reserved_at_40[0x20];
12333 
12334 	u8         reserved_at_60[0x18];
12335 	u8         memic_operation_type[0x8];
12336 
12337 	u8         memic_start_addr[0x40];
12338 
12339 	u8         reserved_at_c0[0x140];
12340 };
12341 
12342 struct mlx5_ifc_modify_memic_out_bits {
12343 	u8         status[0x8];
12344 	u8         reserved_at_8[0x18];
12345 
12346 	u8         syndrome[0x20];
12347 
12348 	u8         reserved_at_40[0x40];
12349 
12350 	u8         memic_operation_addr[0x40];
12351 
12352 	u8         reserved_at_c0[0x140];
12353 };
12354 
12355 struct mlx5_ifc_alloc_memic_in_bits {
12356 	u8         opcode[0x10];
12357 	u8         reserved_at_10[0x10];
12358 
12359 	u8         reserved_at_20[0x10];
12360 	u8         op_mod[0x10];
12361 
12362 	u8         reserved_at_30[0x20];
12363 
12364 	u8	   reserved_at_40[0x18];
12365 	u8	   log_memic_addr_alignment[0x8];
12366 
12367 	u8         range_start_addr[0x40];
12368 
12369 	u8         range_size[0x20];
12370 
12371 	u8         memic_size[0x20];
12372 };
12373 
12374 struct mlx5_ifc_alloc_memic_out_bits {
12375 	u8         status[0x8];
12376 	u8         reserved_at_8[0x18];
12377 
12378 	u8         syndrome[0x20];
12379 
12380 	u8         memic_start_addr[0x40];
12381 };
12382 
12383 struct mlx5_ifc_dealloc_memic_in_bits {
12384 	u8         opcode[0x10];
12385 	u8         reserved_at_10[0x10];
12386 
12387 	u8         reserved_at_20[0x10];
12388 	u8         op_mod[0x10];
12389 
12390 	u8         reserved_at_40[0x40];
12391 
12392 	u8         memic_start_addr[0x40];
12393 
12394 	u8         memic_size[0x20];
12395 
12396 	u8         reserved_at_e0[0x20];
12397 };
12398 
12399 struct mlx5_ifc_dealloc_memic_out_bits {
12400 	u8         status[0x8];
12401 	u8         reserved_at_8[0x18];
12402 
12403 	u8         syndrome[0x20];
12404 
12405 	u8         reserved_at_40[0x40];
12406 };
12407 
12408 struct mlx5_ifc_umem_bits {
12409 	u8         reserved_at_0[0x80];
12410 
12411 	u8         ats[0x1];
12412 	u8         reserved_at_81[0x1a];
12413 	u8         log_page_size[0x5];
12414 
12415 	u8         page_offset[0x20];
12416 
12417 	u8         num_of_mtt[0x40];
12418 
12419 	struct mlx5_ifc_mtt_bits  mtt[];
12420 };
12421 
12422 struct mlx5_ifc_uctx_bits {
12423 	u8         cap[0x20];
12424 
12425 	u8         reserved_at_20[0x160];
12426 };
12427 
12428 struct mlx5_ifc_sw_icm_bits {
12429 	u8         modify_field_select[0x40];
12430 
12431 	u8	   reserved_at_40[0x18];
12432 	u8         log_sw_icm_size[0x8];
12433 
12434 	u8         reserved_at_60[0x20];
12435 
12436 	u8         sw_icm_start_addr[0x40];
12437 
12438 	u8         reserved_at_c0[0x140];
12439 };
12440 
12441 struct mlx5_ifc_geneve_tlv_option_bits {
12442 	u8         modify_field_select[0x40];
12443 
12444 	u8         reserved_at_40[0x18];
12445 	u8         geneve_option_fte_index[0x8];
12446 
12447 	u8         option_class[0x10];
12448 	u8         option_type[0x8];
12449 	u8         reserved_at_78[0x3];
12450 	u8         option_data_length[0x5];
12451 
12452 	u8         reserved_at_80[0x180];
12453 };
12454 
12455 struct mlx5_ifc_create_umem_in_bits {
12456 	u8         opcode[0x10];
12457 	u8         uid[0x10];
12458 
12459 	u8         reserved_at_20[0x10];
12460 	u8         op_mod[0x10];
12461 
12462 	u8         reserved_at_40[0x40];
12463 
12464 	struct mlx5_ifc_umem_bits  umem;
12465 };
12466 
12467 struct mlx5_ifc_create_umem_out_bits {
12468 	u8         status[0x8];
12469 	u8         reserved_at_8[0x18];
12470 
12471 	u8         syndrome[0x20];
12472 
12473 	u8         reserved_at_40[0x8];
12474 	u8         umem_id[0x18];
12475 
12476 	u8         reserved_at_60[0x20];
12477 };
12478 
12479 struct mlx5_ifc_destroy_umem_in_bits {
12480 	u8        opcode[0x10];
12481 	u8        uid[0x10];
12482 
12483 	u8        reserved_at_20[0x10];
12484 	u8        op_mod[0x10];
12485 
12486 	u8        reserved_at_40[0x8];
12487 	u8        umem_id[0x18];
12488 
12489 	u8        reserved_at_60[0x20];
12490 };
12491 
12492 struct mlx5_ifc_destroy_umem_out_bits {
12493 	u8        status[0x8];
12494 	u8        reserved_at_8[0x18];
12495 
12496 	u8        syndrome[0x20];
12497 
12498 	u8        reserved_at_40[0x40];
12499 };
12500 
12501 struct mlx5_ifc_create_uctx_in_bits {
12502 	u8         opcode[0x10];
12503 	u8         reserved_at_10[0x10];
12504 
12505 	u8         reserved_at_20[0x10];
12506 	u8         op_mod[0x10];
12507 
12508 	u8         reserved_at_40[0x40];
12509 
12510 	struct mlx5_ifc_uctx_bits  uctx;
12511 };
12512 
12513 struct mlx5_ifc_create_uctx_out_bits {
12514 	u8         status[0x8];
12515 	u8         reserved_at_8[0x18];
12516 
12517 	u8         syndrome[0x20];
12518 
12519 	u8         reserved_at_40[0x10];
12520 	u8         uid[0x10];
12521 
12522 	u8         reserved_at_60[0x20];
12523 };
12524 
12525 struct mlx5_ifc_destroy_uctx_in_bits {
12526 	u8         opcode[0x10];
12527 	u8         reserved_at_10[0x10];
12528 
12529 	u8         reserved_at_20[0x10];
12530 	u8         op_mod[0x10];
12531 
12532 	u8         reserved_at_40[0x10];
12533 	u8         uid[0x10];
12534 
12535 	u8         reserved_at_60[0x20];
12536 };
12537 
12538 struct mlx5_ifc_destroy_uctx_out_bits {
12539 	u8         status[0x8];
12540 	u8         reserved_at_8[0x18];
12541 
12542 	u8         syndrome[0x20];
12543 
12544 	u8          reserved_at_40[0x40];
12545 };
12546 
12547 struct mlx5_ifc_create_sw_icm_in_bits {
12548 	struct mlx5_ifc_general_obj_in_cmd_hdr_bits   hdr;
12549 	struct mlx5_ifc_sw_icm_bits		      sw_icm;
12550 };
12551 
12552 struct mlx5_ifc_create_geneve_tlv_option_in_bits {
12553 	struct mlx5_ifc_general_obj_in_cmd_hdr_bits   hdr;
12554 	struct mlx5_ifc_geneve_tlv_option_bits        geneve_tlv_opt;
12555 };
12556 
12557 struct mlx5_ifc_mtrc_string_db_param_bits {
12558 	u8         string_db_base_address[0x20];
12559 
12560 	u8         reserved_at_20[0x8];
12561 	u8         string_db_size[0x18];
12562 };
12563 
12564 struct mlx5_ifc_mtrc_cap_bits {
12565 	u8         trace_owner[0x1];
12566 	u8         trace_to_memory[0x1];
12567 	u8         reserved_at_2[0x4];
12568 	u8         trc_ver[0x2];
12569 	u8         reserved_at_8[0x14];
12570 	u8         num_string_db[0x4];
12571 
12572 	u8         first_string_trace[0x8];
12573 	u8         num_string_trace[0x8];
12574 	u8         reserved_at_30[0x28];
12575 
12576 	u8         log_max_trace_buffer_size[0x8];
12577 
12578 	u8         reserved_at_60[0x20];
12579 
12580 	struct mlx5_ifc_mtrc_string_db_param_bits string_db_param[8];
12581 
12582 	u8         reserved_at_280[0x180];
12583 };
12584 
12585 struct mlx5_ifc_mtrc_conf_bits {
12586 	u8         reserved_at_0[0x1c];
12587 	u8         trace_mode[0x4];
12588 	u8         reserved_at_20[0x18];
12589 	u8         log_trace_buffer_size[0x8];
12590 	u8         trace_mkey[0x20];
12591 	u8         reserved_at_60[0x3a0];
12592 };
12593 
12594 struct mlx5_ifc_mtrc_stdb_bits {
12595 	u8         string_db_index[0x4];
12596 	u8         reserved_at_4[0x4];
12597 	u8         read_size[0x18];
12598 	u8         start_offset[0x20];
12599 	u8         string_db_data[];
12600 };
12601 
12602 struct mlx5_ifc_mtrc_ctrl_bits {
12603 	u8         trace_status[0x2];
12604 	u8         reserved_at_2[0x2];
12605 	u8         arm_event[0x1];
12606 	u8         reserved_at_5[0xb];
12607 	u8         modify_field_select[0x10];
12608 	u8         reserved_at_20[0x2b];
12609 	u8         current_timestamp52_32[0x15];
12610 	u8         current_timestamp31_0[0x20];
12611 	u8         reserved_at_80[0x180];
12612 };
12613 
12614 struct mlx5_ifc_host_params_context_bits {
12615 	u8         host_number[0x8];
12616 	u8         reserved_at_8[0x5];
12617 	u8         host_pf_not_exist[0x1];
12618 	u8         reserved_at_14[0x1];
12619 	u8         host_pf_disabled[0x1];
12620 	u8         host_num_of_vfs[0x10];
12621 
12622 	u8         host_total_vfs[0x10];
12623 	u8         host_pci_bus[0x10];
12624 
12625 	u8         reserved_at_40[0x10];
12626 	u8         host_pci_device[0x10];
12627 
12628 	u8         reserved_at_60[0x10];
12629 	u8         host_pci_function[0x10];
12630 
12631 	u8         reserved_at_80[0x180];
12632 };
12633 
12634 struct mlx5_ifc_query_esw_functions_in_bits {
12635 	u8         opcode[0x10];
12636 	u8         reserved_at_10[0x10];
12637 
12638 	u8         reserved_at_20[0x10];
12639 	u8         op_mod[0x10];
12640 
12641 	u8         reserved_at_40[0x40];
12642 };
12643 
12644 struct mlx5_ifc_query_esw_functions_out_bits {
12645 	u8         status[0x8];
12646 	u8         reserved_at_8[0x18];
12647 
12648 	u8         syndrome[0x20];
12649 
12650 	u8         reserved_at_40[0x40];
12651 
12652 	struct mlx5_ifc_host_params_context_bits host_params_context;
12653 
12654 	u8         reserved_at_280[0x180];
12655 	u8         host_sf_enable[][0x40];
12656 };
12657 
12658 struct mlx5_ifc_sf_partition_bits {
12659 	u8         reserved_at_0[0x10];
12660 	u8         log_num_sf[0x8];
12661 	u8         log_sf_bar_size[0x8];
12662 };
12663 
12664 struct mlx5_ifc_query_sf_partitions_out_bits {
12665 	u8         status[0x8];
12666 	u8         reserved_at_8[0x18];
12667 
12668 	u8         syndrome[0x20];
12669 
12670 	u8         reserved_at_40[0x18];
12671 	u8         num_sf_partitions[0x8];
12672 
12673 	u8         reserved_at_60[0x20];
12674 
12675 	struct mlx5_ifc_sf_partition_bits sf_partition[];
12676 };
12677 
12678 struct mlx5_ifc_query_sf_partitions_in_bits {
12679 	u8         opcode[0x10];
12680 	u8         reserved_at_10[0x10];
12681 
12682 	u8         reserved_at_20[0x10];
12683 	u8         op_mod[0x10];
12684 
12685 	u8         reserved_at_40[0x40];
12686 };
12687 
12688 struct mlx5_ifc_dealloc_sf_out_bits {
12689 	u8         status[0x8];
12690 	u8         reserved_at_8[0x18];
12691 
12692 	u8         syndrome[0x20];
12693 
12694 	u8         reserved_at_40[0x40];
12695 };
12696 
12697 struct mlx5_ifc_dealloc_sf_in_bits {
12698 	u8         opcode[0x10];
12699 	u8         reserved_at_10[0x10];
12700 
12701 	u8         reserved_at_20[0x10];
12702 	u8         op_mod[0x10];
12703 
12704 	u8         reserved_at_40[0x10];
12705 	u8         function_id[0x10];
12706 
12707 	u8         reserved_at_60[0x20];
12708 };
12709 
12710 struct mlx5_ifc_alloc_sf_out_bits {
12711 	u8         status[0x8];
12712 	u8         reserved_at_8[0x18];
12713 
12714 	u8         syndrome[0x20];
12715 
12716 	u8         reserved_at_40[0x40];
12717 };
12718 
12719 struct mlx5_ifc_alloc_sf_in_bits {
12720 	u8         opcode[0x10];
12721 	u8         reserved_at_10[0x10];
12722 
12723 	u8         reserved_at_20[0x10];
12724 	u8         op_mod[0x10];
12725 
12726 	u8         reserved_at_40[0x10];
12727 	u8         function_id[0x10];
12728 
12729 	u8         reserved_at_60[0x20];
12730 };
12731 
12732 struct mlx5_ifc_affiliated_event_header_bits {
12733 	u8         reserved_at_0[0x10];
12734 	u8         obj_type[0x10];
12735 
12736 	u8         obj_id[0x20];
12737 };
12738 
12739 enum {
12740 	MLX5_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = 0xc,
12741 	MLX5_GENERAL_OBJECT_TYPES_IPSEC = 0x13,
12742 	MLX5_GENERAL_OBJECT_TYPES_SAMPLER = 0x20,
12743 	MLX5_GENERAL_OBJECT_TYPES_FLOW_METER_ASO = 0x24,
12744 	MLX5_GENERAL_OBJECT_TYPES_MACSEC = 0x27,
12745 	MLX5_GENERAL_OBJECT_TYPES_INT_KEK = 0x47,
12746 	MLX5_GENERAL_OBJECT_TYPES_RDMA_CTRL = 0x53,
12747 	MLX5_GENERAL_OBJECT_TYPES_PCIE_CONG_EVENT = 0x58,
12748 	MLX5_GENERAL_OBJECT_TYPES_FLOW_TABLE_ALIAS = 0xff15,
12749 };
12750 
12751 enum {
12752 	MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY =
12753 		BIT_ULL(MLX5_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY),
12754 	MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_IPSEC =
12755 		BIT_ULL(MLX5_GENERAL_OBJECT_TYPES_IPSEC),
12756 	MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_SAMPLER =
12757 		BIT_ULL(MLX5_GENERAL_OBJECT_TYPES_SAMPLER),
12758 	MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_FLOW_METER_ASO =
12759 		BIT_ULL(MLX5_GENERAL_OBJECT_TYPES_FLOW_METER_ASO),
12760 };
12761 
12762 enum {
12763 	MLX5_HCA_CAP_2_GENERAL_OBJECT_TYPES_RDMA_CTRL =
12764 		BIT_ULL(MLX5_GENERAL_OBJECT_TYPES_RDMA_CTRL - 0x40),
12765 	MLX5_HCA_CAP_2_GENERAL_OBJECT_TYPES_PCIE_CONG_EVENT =
12766 		BIT_ULL(MLX5_GENERAL_OBJECT_TYPES_PCIE_CONG_EVENT - 0x40),
12767 };
12768 
12769 enum {
12770 	MLX5_IPSEC_OBJECT_ICV_LEN_16B,
12771 };
12772 
12773 enum {
12774 	MLX5_IPSEC_ASO_REG_C_0_1 = 0x0,
12775 	MLX5_IPSEC_ASO_REG_C_2_3 = 0x1,
12776 	MLX5_IPSEC_ASO_REG_C_4_5 = 0x2,
12777 	MLX5_IPSEC_ASO_REG_C_6_7 = 0x3,
12778 };
12779 
12780 enum {
12781 	MLX5_IPSEC_ASO_MODE              = 0x0,
12782 	MLX5_IPSEC_ASO_REPLAY_PROTECTION = 0x1,
12783 	MLX5_IPSEC_ASO_INC_SN            = 0x2,
12784 };
12785 
12786 enum {
12787 	MLX5_IPSEC_ASO_REPLAY_WIN_32BIT  = 0x0,
12788 	MLX5_IPSEC_ASO_REPLAY_WIN_64BIT  = 0x1,
12789 	MLX5_IPSEC_ASO_REPLAY_WIN_128BIT = 0x2,
12790 	MLX5_IPSEC_ASO_REPLAY_WIN_256BIT = 0x3,
12791 };
12792 
12793 struct mlx5_ifc_ipsec_aso_bits {
12794 	u8         valid[0x1];
12795 	u8         reserved_at_201[0x1];
12796 	u8         mode[0x2];
12797 	u8         window_sz[0x2];
12798 	u8         soft_lft_arm[0x1];
12799 	u8         hard_lft_arm[0x1];
12800 	u8         remove_flow_enable[0x1];
12801 	u8         esn_event_arm[0x1];
12802 	u8         reserved_at_20a[0x16];
12803 
12804 	u8         remove_flow_pkt_cnt[0x20];
12805 
12806 	u8         remove_flow_soft_lft[0x20];
12807 
12808 	u8         reserved_at_260[0x80];
12809 
12810 	u8         mode_parameter[0x20];
12811 
12812 	u8         replay_protection_window[0x100];
12813 };
12814 
12815 struct mlx5_ifc_ipsec_obj_bits {
12816 	u8         modify_field_select[0x40];
12817 	u8         full_offload[0x1];
12818 	u8         reserved_at_41[0x1];
12819 	u8         esn_en[0x1];
12820 	u8         esn_overlap[0x1];
12821 	u8         reserved_at_44[0x2];
12822 	u8         icv_length[0x2];
12823 	u8         reserved_at_48[0x4];
12824 	u8         aso_return_reg[0x4];
12825 	u8         reserved_at_50[0x10];
12826 
12827 	u8         esn_msb[0x20];
12828 
12829 	u8         reserved_at_80[0x8];
12830 	u8         dekn[0x18];
12831 
12832 	u8         salt[0x20];
12833 
12834 	u8         implicit_iv[0x40];
12835 
12836 	u8         reserved_at_100[0x8];
12837 	u8         ipsec_aso_access_pd[0x18];
12838 	u8         reserved_at_120[0xe0];
12839 
12840 	struct mlx5_ifc_ipsec_aso_bits ipsec_aso;
12841 };
12842 
12843 struct mlx5_ifc_create_ipsec_obj_in_bits {
12844 	struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
12845 	struct mlx5_ifc_ipsec_obj_bits ipsec_object;
12846 };
12847 
12848 enum {
12849 	MLX5_MODIFY_IPSEC_BITMASK_ESN_OVERLAP = BIT(0),
12850 	MLX5_MODIFY_IPSEC_BITMASK_ESN_MSB = BIT(1),
12851 };
12852 
12853 struct mlx5_ifc_query_ipsec_obj_out_bits {
12854 	struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr;
12855 	struct mlx5_ifc_ipsec_obj_bits ipsec_object;
12856 };
12857 
12858 struct mlx5_ifc_modify_ipsec_obj_in_bits {
12859 	struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
12860 	struct mlx5_ifc_ipsec_obj_bits ipsec_object;
12861 };
12862 
12863 enum {
12864 	MLX5_MACSEC_ASO_REPLAY_PROTECTION = 0x1,
12865 };
12866 
12867 enum {
12868 	MLX5_MACSEC_ASO_REPLAY_WIN_32BIT  = 0x0,
12869 	MLX5_MACSEC_ASO_REPLAY_WIN_64BIT  = 0x1,
12870 	MLX5_MACSEC_ASO_REPLAY_WIN_128BIT = 0x2,
12871 	MLX5_MACSEC_ASO_REPLAY_WIN_256BIT = 0x3,
12872 };
12873 
12874 #define MLX5_MACSEC_ASO_INC_SN  0x2
12875 #define MLX5_MACSEC_ASO_REG_C_4_5 0x2
12876 
12877 struct mlx5_ifc_macsec_aso_bits {
12878 	u8    valid[0x1];
12879 	u8    reserved_at_1[0x1];
12880 	u8    mode[0x2];
12881 	u8    window_size[0x2];
12882 	u8    soft_lifetime_arm[0x1];
12883 	u8    hard_lifetime_arm[0x1];
12884 	u8    remove_flow_enable[0x1];
12885 	u8    epn_event_arm[0x1];
12886 	u8    reserved_at_a[0x16];
12887 
12888 	u8    remove_flow_packet_count[0x20];
12889 
12890 	u8    remove_flow_soft_lifetime[0x20];
12891 
12892 	u8    reserved_at_60[0x80];
12893 
12894 	u8    mode_parameter[0x20];
12895 
12896 	u8    replay_protection_window[8][0x20];
12897 };
12898 
12899 struct mlx5_ifc_macsec_offload_obj_bits {
12900 	u8    modify_field_select[0x40];
12901 
12902 	u8    confidentiality_en[0x1];
12903 	u8    reserved_at_41[0x1];
12904 	u8    epn_en[0x1];
12905 	u8    epn_overlap[0x1];
12906 	u8    reserved_at_44[0x2];
12907 	u8    confidentiality_offset[0x2];
12908 	u8    reserved_at_48[0x4];
12909 	u8    aso_return_reg[0x4];
12910 	u8    reserved_at_50[0x10];
12911 
12912 	u8    epn_msb[0x20];
12913 
12914 	u8    reserved_at_80[0x8];
12915 	u8    dekn[0x18];
12916 
12917 	u8    reserved_at_a0[0x20];
12918 
12919 	u8    sci[0x40];
12920 
12921 	u8    reserved_at_100[0x8];
12922 	u8    macsec_aso_access_pd[0x18];
12923 
12924 	u8    reserved_at_120[0x60];
12925 
12926 	u8    salt[3][0x20];
12927 
12928 	u8    reserved_at_1e0[0x20];
12929 
12930 	struct mlx5_ifc_macsec_aso_bits macsec_aso;
12931 };
12932 
12933 struct mlx5_ifc_create_macsec_obj_in_bits {
12934 	struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
12935 	struct mlx5_ifc_macsec_offload_obj_bits macsec_object;
12936 };
12937 
12938 struct mlx5_ifc_modify_macsec_obj_in_bits {
12939 	struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
12940 	struct mlx5_ifc_macsec_offload_obj_bits macsec_object;
12941 };
12942 
12943 enum {
12944 	MLX5_MODIFY_MACSEC_BITMASK_EPN_OVERLAP = BIT(0),
12945 	MLX5_MODIFY_MACSEC_BITMASK_EPN_MSB = BIT(1),
12946 };
12947 
12948 struct mlx5_ifc_query_macsec_obj_out_bits {
12949 	struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr;
12950 	struct mlx5_ifc_macsec_offload_obj_bits macsec_object;
12951 };
12952 
12953 struct mlx5_ifc_wrapped_dek_bits {
12954 	u8         gcm_iv[0x60];
12955 
12956 	u8         reserved_at_60[0x20];
12957 
12958 	u8         const0[0x1];
12959 	u8         key_size[0x1];
12960 	u8         reserved_at_82[0x2];
12961 	u8         key2_invalid[0x1];
12962 	u8         reserved_at_85[0x3];
12963 	u8         pd[0x18];
12964 
12965 	u8         key_purpose[0x5];
12966 	u8         reserved_at_a5[0x13];
12967 	u8         kek_id[0x8];
12968 
12969 	u8         reserved_at_c0[0x40];
12970 
12971 	u8         key1[0x8][0x20];
12972 
12973 	u8         key2[0x8][0x20];
12974 
12975 	u8         reserved_at_300[0x40];
12976 
12977 	u8         const1[0x1];
12978 	u8         reserved_at_341[0x1f];
12979 
12980 	u8         reserved_at_360[0x20];
12981 
12982 	u8         auth_tag[0x80];
12983 };
12984 
12985 struct mlx5_ifc_encryption_key_obj_bits {
12986 	u8         modify_field_select[0x40];
12987 
12988 	u8         state[0x8];
12989 	u8         sw_wrapped[0x1];
12990 	u8         reserved_at_49[0xb];
12991 	u8         key_size[0x4];
12992 	u8         reserved_at_58[0x4];
12993 	u8         key_purpose[0x4];
12994 
12995 	u8         reserved_at_60[0x8];
12996 	u8         pd[0x18];
12997 
12998 	u8         reserved_at_80[0x100];
12999 
13000 	u8         opaque[0x40];
13001 
13002 	u8         reserved_at_1c0[0x40];
13003 
13004 	u8         key[8][0x80];
13005 
13006 	u8         sw_wrapped_dek[8][0x80];
13007 
13008 	u8         reserved_at_a00[0x600];
13009 };
13010 
13011 struct mlx5_ifc_create_encryption_key_in_bits {
13012 	struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
13013 	struct mlx5_ifc_encryption_key_obj_bits encryption_key_object;
13014 };
13015 
13016 struct mlx5_ifc_modify_encryption_key_in_bits {
13017 	struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
13018 	struct mlx5_ifc_encryption_key_obj_bits encryption_key_object;
13019 };
13020 
13021 enum {
13022 	MLX5_FLOW_METER_MODE_BYTES_IP_LENGTH		= 0x0,
13023 	MLX5_FLOW_METER_MODE_BYTES_CALC_WITH_L2		= 0x1,
13024 	MLX5_FLOW_METER_MODE_BYTES_CALC_WITH_L2_IPG	= 0x2,
13025 	MLX5_FLOW_METER_MODE_NUM_PACKETS		= 0x3,
13026 };
13027 
13028 struct mlx5_ifc_flow_meter_parameters_bits {
13029 	u8         valid[0x1];
13030 	u8         bucket_overflow[0x1];
13031 	u8         start_color[0x2];
13032 	u8         both_buckets_on_green[0x1];
13033 	u8         reserved_at_5[0x1];
13034 	u8         meter_mode[0x2];
13035 	u8         reserved_at_8[0x18];
13036 
13037 	u8         reserved_at_20[0x20];
13038 
13039 	u8         reserved_at_40[0x3];
13040 	u8         cbs_exponent[0x5];
13041 	u8         cbs_mantissa[0x8];
13042 	u8         reserved_at_50[0x3];
13043 	u8         cir_exponent[0x5];
13044 	u8         cir_mantissa[0x8];
13045 
13046 	u8         reserved_at_60[0x20];
13047 
13048 	u8         reserved_at_80[0x3];
13049 	u8         ebs_exponent[0x5];
13050 	u8         ebs_mantissa[0x8];
13051 	u8         reserved_at_90[0x3];
13052 	u8         eir_exponent[0x5];
13053 	u8         eir_mantissa[0x8];
13054 
13055 	u8         reserved_at_a0[0x60];
13056 };
13057 
13058 struct mlx5_ifc_flow_meter_aso_obj_bits {
13059 	u8         modify_field_select[0x40];
13060 
13061 	u8         reserved_at_40[0x40];
13062 
13063 	u8         reserved_at_80[0x8];
13064 	u8         meter_aso_access_pd[0x18];
13065 
13066 	u8         reserved_at_a0[0x160];
13067 
13068 	struct mlx5_ifc_flow_meter_parameters_bits flow_meter_parameters[2];
13069 };
13070 
13071 struct mlx5_ifc_create_flow_meter_aso_obj_in_bits {
13072 	struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
13073 	struct mlx5_ifc_flow_meter_aso_obj_bits flow_meter_aso_obj;
13074 };
13075 
13076 struct mlx5_ifc_int_kek_obj_bits {
13077 	u8         modify_field_select[0x40];
13078 
13079 	u8         state[0x8];
13080 	u8         auto_gen[0x1];
13081 	u8         reserved_at_49[0xb];
13082 	u8         key_size[0x4];
13083 	u8         reserved_at_58[0x8];
13084 
13085 	u8         reserved_at_60[0x8];
13086 	u8         pd[0x18];
13087 
13088 	u8         reserved_at_80[0x180];
13089 	u8         key[8][0x80];
13090 
13091 	u8         reserved_at_600[0x200];
13092 };
13093 
13094 struct mlx5_ifc_create_int_kek_obj_in_bits {
13095 	struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
13096 	struct mlx5_ifc_int_kek_obj_bits int_kek_object;
13097 };
13098 
13099 struct mlx5_ifc_create_int_kek_obj_out_bits {
13100 	struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr;
13101 	struct mlx5_ifc_int_kek_obj_bits int_kek_object;
13102 };
13103 
13104 struct mlx5_ifc_sampler_obj_bits {
13105 	u8         modify_field_select[0x40];
13106 
13107 	u8         table_type[0x8];
13108 	u8         level[0x8];
13109 	u8         reserved_at_50[0xf];
13110 	u8         ignore_flow_level[0x1];
13111 
13112 	u8         sample_ratio[0x20];
13113 
13114 	u8         reserved_at_80[0x8];
13115 	u8         sample_table_id[0x18];
13116 
13117 	u8         reserved_at_a0[0x8];
13118 	u8         default_table_id[0x18];
13119 
13120 	u8         sw_steering_icm_address_rx[0x40];
13121 	u8         sw_steering_icm_address_tx[0x40];
13122 
13123 	u8         reserved_at_140[0xa0];
13124 };
13125 
13126 struct mlx5_ifc_create_sampler_obj_in_bits {
13127 	struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
13128 	struct mlx5_ifc_sampler_obj_bits sampler_object;
13129 };
13130 
13131 struct mlx5_ifc_query_sampler_obj_out_bits {
13132 	struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr;
13133 	struct mlx5_ifc_sampler_obj_bits sampler_object;
13134 };
13135 
13136 enum {
13137 	MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_128 = 0x0,
13138 	MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_256 = 0x1,
13139 };
13140 
13141 enum {
13142 	MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_PURPOSE_TLS = 0x1,
13143 	MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_PURPOSE_IPSEC = 0x2,
13144 	MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_PURPOSE_MACSEC = 0x4,
13145 	MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_PURPOSE_PSP = 0x6,
13146 };
13147 
13148 struct mlx5_ifc_tls_static_params_bits {
13149 	u8         const_2[0x2];
13150 	u8         tls_version[0x4];
13151 	u8         const_1[0x2];
13152 	u8         reserved_at_8[0x14];
13153 	u8         encryption_standard[0x4];
13154 
13155 	u8         reserved_at_20[0x20];
13156 
13157 	u8         initial_record_number[0x40];
13158 
13159 	u8         resync_tcp_sn[0x20];
13160 
13161 	u8         gcm_iv[0x20];
13162 
13163 	u8         implicit_iv[0x40];
13164 
13165 	u8         reserved_at_100[0x8];
13166 	u8         dek_index[0x18];
13167 
13168 	u8         reserved_at_120[0xe0];
13169 };
13170 
13171 struct mlx5_ifc_tls_progress_params_bits {
13172 	u8         next_record_tcp_sn[0x20];
13173 
13174 	u8         hw_resync_tcp_sn[0x20];
13175 
13176 	u8         record_tracker_state[0x2];
13177 	u8         auth_state[0x2];
13178 	u8         reserved_at_44[0x4];
13179 	u8         hw_offset_record_number[0x18];
13180 };
13181 
13182 enum {
13183 	MLX5_MTT_PERM_READ	= 1 << 0,
13184 	MLX5_MTT_PERM_WRITE	= 1 << 1,
13185 	MLX5_MTT_PERM_RW	= MLX5_MTT_PERM_READ | MLX5_MTT_PERM_WRITE,
13186 };
13187 
13188 enum {
13189 	MLX5_SUSPEND_VHCA_IN_OP_MOD_SUSPEND_INITIATOR  = 0x0,
13190 	MLX5_SUSPEND_VHCA_IN_OP_MOD_SUSPEND_RESPONDER  = 0x1,
13191 };
13192 
13193 struct mlx5_ifc_suspend_vhca_in_bits {
13194 	u8         opcode[0x10];
13195 	u8         uid[0x10];
13196 
13197 	u8         reserved_at_20[0x10];
13198 	u8         op_mod[0x10];
13199 
13200 	u8         reserved_at_40[0x10];
13201 	u8         vhca_id[0x10];
13202 
13203 	u8         reserved_at_60[0x20];
13204 };
13205 
13206 struct mlx5_ifc_suspend_vhca_out_bits {
13207 	u8         status[0x8];
13208 	u8         reserved_at_8[0x18];
13209 
13210 	u8         syndrome[0x20];
13211 
13212 	u8         reserved_at_40[0x40];
13213 };
13214 
13215 enum {
13216 	MLX5_RESUME_VHCA_IN_OP_MOD_RESUME_RESPONDER  = 0x0,
13217 	MLX5_RESUME_VHCA_IN_OP_MOD_RESUME_INITIATOR  = 0x1,
13218 };
13219 
13220 struct mlx5_ifc_resume_vhca_in_bits {
13221 	u8         opcode[0x10];
13222 	u8         uid[0x10];
13223 
13224 	u8         reserved_at_20[0x10];
13225 	u8         op_mod[0x10];
13226 
13227 	u8         reserved_at_40[0x10];
13228 	u8         vhca_id[0x10];
13229 
13230 	u8         reserved_at_60[0x20];
13231 };
13232 
13233 struct mlx5_ifc_resume_vhca_out_bits {
13234 	u8         status[0x8];
13235 	u8         reserved_at_8[0x18];
13236 
13237 	u8         syndrome[0x20];
13238 
13239 	u8         reserved_at_40[0x40];
13240 };
13241 
13242 struct mlx5_ifc_query_vhca_migration_state_in_bits {
13243 	u8         opcode[0x10];
13244 	u8         uid[0x10];
13245 
13246 	u8         reserved_at_20[0x10];
13247 	u8         op_mod[0x10];
13248 
13249 	u8         incremental[0x1];
13250 	u8         chunk[0x1];
13251 	u8         reserved_at_42[0xe];
13252 	u8         vhca_id[0x10];
13253 
13254 	u8         reserved_at_60[0x20];
13255 };
13256 
13257 struct mlx5_ifc_query_vhca_migration_state_out_bits {
13258 	u8         status[0x8];
13259 	u8         reserved_at_8[0x18];
13260 
13261 	u8         syndrome[0x20];
13262 
13263 	u8         reserved_at_40[0x40];
13264 
13265 	u8         required_umem_size[0x20];
13266 
13267 	u8         reserved_at_a0[0x20];
13268 
13269 	u8         remaining_total_size[0x40];
13270 
13271 	u8         reserved_at_100[0x100];
13272 };
13273 
13274 struct mlx5_ifc_save_vhca_state_in_bits {
13275 	u8         opcode[0x10];
13276 	u8         uid[0x10];
13277 
13278 	u8         reserved_at_20[0x10];
13279 	u8         op_mod[0x10];
13280 
13281 	u8         incremental[0x1];
13282 	u8         set_track[0x1];
13283 	u8         reserved_at_42[0xe];
13284 	u8         vhca_id[0x10];
13285 
13286 	u8         reserved_at_60[0x20];
13287 
13288 	u8         va[0x40];
13289 
13290 	u8         mkey[0x20];
13291 
13292 	u8         size[0x20];
13293 };
13294 
13295 struct mlx5_ifc_save_vhca_state_out_bits {
13296 	u8         status[0x8];
13297 	u8         reserved_at_8[0x18];
13298 
13299 	u8         syndrome[0x20];
13300 
13301 	u8         actual_image_size[0x20];
13302 
13303 	u8         next_required_umem_size[0x20];
13304 };
13305 
13306 struct mlx5_ifc_load_vhca_state_in_bits {
13307 	u8         opcode[0x10];
13308 	u8         uid[0x10];
13309 
13310 	u8         reserved_at_20[0x10];
13311 	u8         op_mod[0x10];
13312 
13313 	u8         reserved_at_40[0x10];
13314 	u8         vhca_id[0x10];
13315 
13316 	u8         reserved_at_60[0x20];
13317 
13318 	u8         va[0x40];
13319 
13320 	u8         mkey[0x20];
13321 
13322 	u8         size[0x20];
13323 };
13324 
13325 struct mlx5_ifc_load_vhca_state_out_bits {
13326 	u8         status[0x8];
13327 	u8         reserved_at_8[0x18];
13328 
13329 	u8         syndrome[0x20];
13330 
13331 	u8         reserved_at_40[0x40];
13332 };
13333 
13334 struct mlx5_ifc_adv_rdma_cap_bits {
13335 	u8         rdma_transport_manager[0x1];
13336 	u8         rdma_transport_manager_other_eswitch[0x1];
13337 	u8         reserved_at_2[0x1e];
13338 
13339 	u8         rcx_type[0x8];
13340 	u8         reserved_at_28[0x2];
13341 	u8         ps_entry_log_max_value[0x6];
13342 	u8         reserved_at_30[0x6];
13343 	u8         qp_max_ps_num_entry[0xa];
13344 
13345 	u8         mp_max_num_queues[0x8];
13346 	u8         ps_user_context_max_log_size[0x8];
13347 	u8         message_based_qp_and_striding_wq[0x8];
13348 	u8         reserved_at_58[0x8];
13349 
13350 	u8         max_receive_send_message_size_stride[0x10];
13351 	u8         reserved_at_70[0x10];
13352 
13353 	u8         max_receive_send_message_size_byte[0x20];
13354 
13355 	u8         reserved_at_a0[0x160];
13356 
13357 	struct mlx5_ifc_flow_table_prop_layout_bits rdma_transport_rx_flow_table_properties;
13358 
13359 	struct mlx5_ifc_flow_table_prop_layout_bits rdma_transport_tx_flow_table_properties;
13360 
13361 	struct mlx5_ifc_flow_table_fields_supported_2_bits rdma_transport_rx_ft_field_support_2;
13362 
13363 	struct mlx5_ifc_flow_table_fields_supported_2_bits rdma_transport_tx_ft_field_support_2;
13364 
13365 	struct mlx5_ifc_flow_table_fields_supported_2_bits rdma_transport_rx_ft_field_bitmask_support_2;
13366 
13367 	struct mlx5_ifc_flow_table_fields_supported_2_bits rdma_transport_tx_ft_field_bitmask_support_2;
13368 
13369 	u8         reserved_at_800[0x3800];
13370 };
13371 
13372 struct mlx5_ifc_adv_virtualization_cap_bits {
13373 	u8         reserved_at_0[0x3];
13374 	u8         pg_track_log_max_num[0x5];
13375 	u8         pg_track_max_num_range[0x8];
13376 	u8         pg_track_log_min_addr_space[0x8];
13377 	u8         pg_track_log_max_addr_space[0x8];
13378 
13379 	u8         reserved_at_20[0x3];
13380 	u8         pg_track_log_min_msg_size[0x5];
13381 	u8         reserved_at_28[0x3];
13382 	u8         pg_track_log_max_msg_size[0x5];
13383 	u8         reserved_at_30[0x3];
13384 	u8         pg_track_log_min_page_size[0x5];
13385 	u8         reserved_at_38[0x3];
13386 	u8         pg_track_log_max_page_size[0x5];
13387 
13388 	u8         reserved_at_40[0x7c0];
13389 };
13390 
13391 struct mlx5_ifc_page_track_report_entry_bits {
13392 	u8         dirty_address_high[0x20];
13393 
13394 	u8         dirty_address_low[0x20];
13395 };
13396 
13397 enum {
13398 	MLX5_PAGE_TRACK_STATE_TRACKING,
13399 	MLX5_PAGE_TRACK_STATE_REPORTING,
13400 	MLX5_PAGE_TRACK_STATE_ERROR,
13401 };
13402 
13403 struct mlx5_ifc_page_track_range_bits {
13404 	u8         start_address[0x40];
13405 
13406 	u8         length[0x40];
13407 };
13408 
13409 struct mlx5_ifc_page_track_bits {
13410 	u8         modify_field_select[0x40];
13411 
13412 	u8         reserved_at_40[0x10];
13413 	u8         vhca_id[0x10];
13414 
13415 	u8         reserved_at_60[0x20];
13416 
13417 	u8         state[0x4];
13418 	u8         track_type[0x4];
13419 	u8         log_addr_space_size[0x8];
13420 	u8         reserved_at_90[0x3];
13421 	u8         log_page_size[0x5];
13422 	u8         reserved_at_98[0x3];
13423 	u8         log_msg_size[0x5];
13424 
13425 	u8         reserved_at_a0[0x8];
13426 	u8         reporting_qpn[0x18];
13427 
13428 	u8         reserved_at_c0[0x18];
13429 	u8         num_ranges[0x8];
13430 
13431 	u8         reserved_at_e0[0x20];
13432 
13433 	u8         range_start_address[0x40];
13434 
13435 	u8         length[0x40];
13436 
13437 	struct     mlx5_ifc_page_track_range_bits track_range[0];
13438 };
13439 
13440 struct mlx5_ifc_create_page_track_obj_in_bits {
13441 	struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
13442 	struct mlx5_ifc_page_track_bits obj_context;
13443 };
13444 
13445 struct mlx5_ifc_modify_page_track_obj_in_bits {
13446 	struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
13447 	struct mlx5_ifc_page_track_bits obj_context;
13448 };
13449 
13450 struct mlx5_ifc_query_page_track_obj_out_bits {
13451 	struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr;
13452 	struct mlx5_ifc_page_track_bits obj_context;
13453 };
13454 
13455 struct mlx5_ifc_msecq_reg_bits {
13456 	u8         reserved_at_0[0x20];
13457 
13458 	u8         reserved_at_20[0x12];
13459 	u8         network_option[0x2];
13460 	u8         local_ssm_code[0x4];
13461 	u8         local_enhanced_ssm_code[0x8];
13462 
13463 	u8         local_clock_identity[0x40];
13464 
13465 	u8         reserved_at_80[0x180];
13466 };
13467 
13468 enum {
13469 	MLX5_MSEES_FIELD_SELECT_ENABLE			= BIT(0),
13470 	MLX5_MSEES_FIELD_SELECT_ADMIN_STATUS		= BIT(1),
13471 	MLX5_MSEES_FIELD_SELECT_ADMIN_FREQ_MEASURE	= BIT(2),
13472 };
13473 
13474 enum mlx5_msees_admin_status {
13475 	MLX5_MSEES_ADMIN_STATUS_FREE_RUNNING		= 0x0,
13476 	MLX5_MSEES_ADMIN_STATUS_TRACK			= 0x1,
13477 };
13478 
13479 enum mlx5_msees_oper_status {
13480 	MLX5_MSEES_OPER_STATUS_FREE_RUNNING		= 0x0,
13481 	MLX5_MSEES_OPER_STATUS_SELF_TRACK		= 0x1,
13482 	MLX5_MSEES_OPER_STATUS_OTHER_TRACK		= 0x2,
13483 	MLX5_MSEES_OPER_STATUS_HOLDOVER			= 0x3,
13484 	MLX5_MSEES_OPER_STATUS_FAIL_HOLDOVER		= 0x4,
13485 	MLX5_MSEES_OPER_STATUS_FAIL_FREE_RUNNING	= 0x5,
13486 };
13487 
13488 enum mlx5_msees_failure_reason {
13489 	MLX5_MSEES_FAILURE_REASON_UNDEFINED_ERROR		= 0x0,
13490 	MLX5_MSEES_FAILURE_REASON_PORT_DOWN			= 0x1,
13491 	MLX5_MSEES_FAILURE_REASON_TOO_HIGH_FREQUENCY_DIFF	= 0x2,
13492 	MLX5_MSEES_FAILURE_REASON_NET_SYNCHRONIZER_DEVICE_ERROR	= 0x3,
13493 	MLX5_MSEES_FAILURE_REASON_LACK_OF_RESOURCES		= 0x4,
13494 };
13495 
13496 struct mlx5_ifc_msees_reg_bits {
13497 	u8         reserved_at_0[0x8];
13498 	u8         local_port[0x8];
13499 	u8         pnat[0x2];
13500 	u8         lp_msb[0x2];
13501 	u8         reserved_at_14[0xc];
13502 
13503 	u8         field_select[0x20];
13504 
13505 	u8         admin_status[0x4];
13506 	u8         oper_status[0x4];
13507 	u8         ho_acq[0x1];
13508 	u8         reserved_at_49[0xc];
13509 	u8         admin_freq_measure[0x1];
13510 	u8         oper_freq_measure[0x1];
13511 	u8         failure_reason[0x9];
13512 
13513 	u8         frequency_diff[0x20];
13514 
13515 	u8         reserved_at_80[0x180];
13516 };
13517 
13518 struct mlx5_ifc_mrtcq_reg_bits {
13519 	u8         reserved_at_0[0x40];
13520 
13521 	u8         rt_clock_identity[0x40];
13522 
13523 	u8         reserved_at_80[0x180];
13524 };
13525 
13526 struct mlx5_ifc_pcie_cong_event_obj_bits {
13527 	u8         modify_select_field[0x40];
13528 
13529 	u8         inbound_event_en[0x1];
13530 	u8         outbound_event_en[0x1];
13531 	u8         reserved_at_42[0x1e];
13532 
13533 	u8         reserved_at_60[0x1];
13534 	u8         inbound_cong_state[0x3];
13535 	u8         reserved_at_64[0x1];
13536 	u8         outbound_cong_state[0x3];
13537 	u8         reserved_at_68[0x18];
13538 
13539 	u8         inbound_cong_low_threshold[0x10];
13540 	u8         inbound_cong_high_threshold[0x10];
13541 
13542 	u8         outbound_cong_low_threshold[0x10];
13543 	u8         outbound_cong_high_threshold[0x10];
13544 
13545 	u8         reserved_at_e0[0x340];
13546 };
13547 
13548 struct mlx5_ifc_pcie_cong_event_cmd_in_bits {
13549 	struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
13550 	struct mlx5_ifc_pcie_cong_event_obj_bits cong_obj;
13551 };
13552 
13553 struct mlx5_ifc_pcie_cong_event_cmd_out_bits {
13554 	struct mlx5_ifc_general_obj_out_cmd_hdr_bits hdr;
13555 	struct mlx5_ifc_pcie_cong_event_obj_bits cong_obj;
13556 };
13557 
13558 enum mlx5e_pcie_cong_event_mod_field {
13559 	MLX5_PCIE_CONG_EVENT_MOD_EVENT_EN = BIT(0),
13560 	MLX5_PCIE_CONG_EVENT_MOD_THRESH   = BIT(2),
13561 };
13562 
13563 struct mlx5_ifc_psp_rotate_key_in_bits {
13564 	u8         opcode[0x10];
13565 	u8         uid[0x10];
13566 
13567 	u8         reserved_at_20[0x10];
13568 	u8         op_mod[0x10];
13569 
13570 	u8         reserved_at_40[0x40];
13571 };
13572 
13573 struct mlx5_ifc_psp_rotate_key_out_bits {
13574 	u8         status[0x8];
13575 	u8         reserved_at_8[0x18];
13576 
13577 	u8         syndrome[0x20];
13578 
13579 	u8         reserved_at_40[0x40];
13580 };
13581 
13582 enum mlx5_psp_gen_spi_in_key_size {
13583 	MLX5_PSP_GEN_SPI_IN_KEY_SIZE_128 = 0x0,
13584 	MLX5_PSP_GEN_SPI_IN_KEY_SIZE_256 = 0x1,
13585 };
13586 
13587 struct mlx5_ifc_key_spi_bits {
13588 	u8         spi[0x20];
13589 
13590 	u8         reserved_at_20[0x60];
13591 
13592 	u8         key[8][0x20];
13593 };
13594 
13595 struct mlx5_ifc_psp_gen_spi_in_bits {
13596 	u8         opcode[0x10];
13597 	u8         uid[0x10];
13598 
13599 	u8         reserved_at_20[0x10];
13600 	u8         op_mod[0x10];
13601 
13602 	u8         reserved_at_40[0x20];
13603 
13604 	u8         key_size[0x2];
13605 	u8         reserved_at_62[0xe];
13606 	u8         num_of_spi[0x10];
13607 };
13608 
13609 struct mlx5_ifc_psp_gen_spi_out_bits {
13610 	u8         status[0x8];
13611 	u8         reserved_at_8[0x18];
13612 
13613 	u8         syndrome[0x20];
13614 
13615 	u8         reserved_at_40[0x10];
13616 	u8         num_of_spi[0x10];
13617 
13618 	u8         reserved_at_60[0x20];
13619 
13620 	struct mlx5_ifc_key_spi_bits key_spi[];
13621 };
13622 
13623 #endif /* MLX5_IFC_H */
13624