1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 #ifndef MLX5_IFC_H 33 #define MLX5_IFC_H 34 35 #include "mlx5_ifc_fpga.h" 36 37 enum { 38 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0, 39 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1, 40 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2, 41 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3, 42 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13, 43 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14, 44 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c, 45 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d, 46 MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4, 47 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5, 48 MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED = 0x7, 49 MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT = 0xc, 50 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10, 51 MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR = 0x11, 52 MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR = 0x12, 53 MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR = 0x8, 54 MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE = 0x9, 55 MLX5_EVENT_TYPE_CODING_GPIO_EVENT = 0x15, 56 MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19, 57 MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a, 58 MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT = 0x1b, 59 MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT = 0x1f, 60 MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa, 61 MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb, 62 MLX5_EVENT_TYPE_CODING_FPGA_ERROR = 0x20, 63 MLX5_EVENT_TYPE_CODING_FPGA_QP_ERROR = 0x21 64 }; 65 66 enum { 67 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0, 68 MLX5_SET_HCA_CAP_OP_MOD_ODP = 0x2, 69 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3, 70 MLX5_SET_HCA_CAP_OP_MOD_ROCE = 0x4, 71 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE2 = 0x20, 72 MLX5_SET_HCA_CAP_OP_MODE_PORT_SELECTION = 0x25, 73 }; 74 75 enum { 76 MLX5_SHARED_RESOURCE_UID = 0xffff, 77 }; 78 79 enum { 80 MLX5_OBJ_TYPE_SW_ICM = 0x0008, 81 }; 82 83 enum { 84 MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM = (1ULL << MLX5_OBJ_TYPE_SW_ICM), 85 MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT = (1ULL << 11), 86 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q = (1ULL << 13), 87 MLX5_GENERAL_OBJ_TYPES_CAP_MACSEC_OFFLOAD = (1ULL << 39), 88 }; 89 90 enum { 91 MLX5_OBJ_TYPE_GENEVE_TLV_OPT = 0x000b, 92 MLX5_OBJ_TYPE_VIRTIO_NET_Q = 0x000d, 93 MLX5_OBJ_TYPE_VIRTIO_Q_COUNTERS = 0x001c, 94 MLX5_OBJ_TYPE_MATCH_DEFINER = 0x0018, 95 MLX5_OBJ_TYPE_PAGE_TRACK = 0x46, 96 MLX5_OBJ_TYPE_MKEY = 0xff01, 97 MLX5_OBJ_TYPE_QP = 0xff02, 98 MLX5_OBJ_TYPE_PSV = 0xff03, 99 MLX5_OBJ_TYPE_RMP = 0xff04, 100 MLX5_OBJ_TYPE_XRC_SRQ = 0xff05, 101 MLX5_OBJ_TYPE_RQ = 0xff06, 102 MLX5_OBJ_TYPE_SQ = 0xff07, 103 MLX5_OBJ_TYPE_TIR = 0xff08, 104 MLX5_OBJ_TYPE_TIS = 0xff09, 105 MLX5_OBJ_TYPE_DCT = 0xff0a, 106 MLX5_OBJ_TYPE_XRQ = 0xff0b, 107 MLX5_OBJ_TYPE_RQT = 0xff0e, 108 MLX5_OBJ_TYPE_FLOW_COUNTER = 0xff0f, 109 MLX5_OBJ_TYPE_CQ = 0xff10, 110 }; 111 112 enum { 113 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100, 114 MLX5_CMD_OP_QUERY_ADAPTER = 0x101, 115 MLX5_CMD_OP_INIT_HCA = 0x102, 116 MLX5_CMD_OP_TEARDOWN_HCA = 0x103, 117 MLX5_CMD_OP_ENABLE_HCA = 0x104, 118 MLX5_CMD_OP_DISABLE_HCA = 0x105, 119 MLX5_CMD_OP_QUERY_PAGES = 0x107, 120 MLX5_CMD_OP_MANAGE_PAGES = 0x108, 121 MLX5_CMD_OP_SET_HCA_CAP = 0x109, 122 MLX5_CMD_OP_QUERY_ISSI = 0x10a, 123 MLX5_CMD_OP_SET_ISSI = 0x10b, 124 MLX5_CMD_OP_SET_DRIVER_VERSION = 0x10d, 125 MLX5_CMD_OP_QUERY_SF_PARTITION = 0x111, 126 MLX5_CMD_OP_ALLOC_SF = 0x113, 127 MLX5_CMD_OP_DEALLOC_SF = 0x114, 128 MLX5_CMD_OP_SUSPEND_VHCA = 0x115, 129 MLX5_CMD_OP_RESUME_VHCA = 0x116, 130 MLX5_CMD_OP_QUERY_VHCA_MIGRATION_STATE = 0x117, 131 MLX5_CMD_OP_SAVE_VHCA_STATE = 0x118, 132 MLX5_CMD_OP_LOAD_VHCA_STATE = 0x119, 133 MLX5_CMD_OP_CREATE_MKEY = 0x200, 134 MLX5_CMD_OP_QUERY_MKEY = 0x201, 135 MLX5_CMD_OP_DESTROY_MKEY = 0x202, 136 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203, 137 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204, 138 MLX5_CMD_OP_ALLOC_MEMIC = 0x205, 139 MLX5_CMD_OP_DEALLOC_MEMIC = 0x206, 140 MLX5_CMD_OP_MODIFY_MEMIC = 0x207, 141 MLX5_CMD_OP_CREATE_EQ = 0x301, 142 MLX5_CMD_OP_DESTROY_EQ = 0x302, 143 MLX5_CMD_OP_QUERY_EQ = 0x303, 144 MLX5_CMD_OP_GEN_EQE = 0x304, 145 MLX5_CMD_OP_CREATE_CQ = 0x400, 146 MLX5_CMD_OP_DESTROY_CQ = 0x401, 147 MLX5_CMD_OP_QUERY_CQ = 0x402, 148 MLX5_CMD_OP_MODIFY_CQ = 0x403, 149 MLX5_CMD_OP_CREATE_QP = 0x500, 150 MLX5_CMD_OP_DESTROY_QP = 0x501, 151 MLX5_CMD_OP_RST2INIT_QP = 0x502, 152 MLX5_CMD_OP_INIT2RTR_QP = 0x503, 153 MLX5_CMD_OP_RTR2RTS_QP = 0x504, 154 MLX5_CMD_OP_RTS2RTS_QP = 0x505, 155 MLX5_CMD_OP_SQERR2RTS_QP = 0x506, 156 MLX5_CMD_OP_2ERR_QP = 0x507, 157 MLX5_CMD_OP_2RST_QP = 0x50a, 158 MLX5_CMD_OP_QUERY_QP = 0x50b, 159 MLX5_CMD_OP_SQD_RTS_QP = 0x50c, 160 MLX5_CMD_OP_INIT2INIT_QP = 0x50e, 161 MLX5_CMD_OP_CREATE_PSV = 0x600, 162 MLX5_CMD_OP_DESTROY_PSV = 0x601, 163 MLX5_CMD_OP_CREATE_SRQ = 0x700, 164 MLX5_CMD_OP_DESTROY_SRQ = 0x701, 165 MLX5_CMD_OP_QUERY_SRQ = 0x702, 166 MLX5_CMD_OP_ARM_RQ = 0x703, 167 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705, 168 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706, 169 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707, 170 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708, 171 MLX5_CMD_OP_CREATE_DCT = 0x710, 172 MLX5_CMD_OP_DESTROY_DCT = 0x711, 173 MLX5_CMD_OP_DRAIN_DCT = 0x712, 174 MLX5_CMD_OP_QUERY_DCT = 0x713, 175 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714, 176 MLX5_CMD_OP_CREATE_XRQ = 0x717, 177 MLX5_CMD_OP_DESTROY_XRQ = 0x718, 178 MLX5_CMD_OP_QUERY_XRQ = 0x719, 179 MLX5_CMD_OP_ARM_XRQ = 0x71a, 180 MLX5_CMD_OP_QUERY_XRQ_DC_PARAMS_ENTRY = 0x725, 181 MLX5_CMD_OP_SET_XRQ_DC_PARAMS_ENTRY = 0x726, 182 MLX5_CMD_OP_QUERY_XRQ_ERROR_PARAMS = 0x727, 183 MLX5_CMD_OP_RELEASE_XRQ_ERROR = 0x729, 184 MLX5_CMD_OP_MODIFY_XRQ = 0x72a, 185 MLX5_CMD_OP_QUERY_ESW_FUNCTIONS = 0x740, 186 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750, 187 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751, 188 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752, 189 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753, 190 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754, 191 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755, 192 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760, 193 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761, 194 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762, 195 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763, 196 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764, 197 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765, 198 MLX5_CMD_OP_QUERY_VNIC_ENV = 0x76f, 199 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770, 200 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771, 201 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772, 202 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773, 203 MLX5_CMD_OP_SET_MONITOR_COUNTER = 0x774, 204 MLX5_CMD_OP_ARM_MONITOR_COUNTER = 0x775, 205 MLX5_CMD_OP_SET_PP_RATE_LIMIT = 0x780, 206 MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781, 207 MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT = 0x782, 208 MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT = 0x783, 209 MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT = 0x784, 210 MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT = 0x785, 211 MLX5_CMD_OP_CREATE_QOS_PARA_VPORT = 0x786, 212 MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT = 0x787, 213 MLX5_CMD_OP_ALLOC_PD = 0x800, 214 MLX5_CMD_OP_DEALLOC_PD = 0x801, 215 MLX5_CMD_OP_ALLOC_UAR = 0x802, 216 MLX5_CMD_OP_DEALLOC_UAR = 0x803, 217 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804, 218 MLX5_CMD_OP_ACCESS_REG = 0x805, 219 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806, 220 MLX5_CMD_OP_DETACH_FROM_MCG = 0x807, 221 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a, 222 MLX5_CMD_OP_MAD_IFC = 0x50d, 223 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b, 224 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c, 225 MLX5_CMD_OP_NOP = 0x80d, 226 MLX5_CMD_OP_ALLOC_XRCD = 0x80e, 227 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f, 228 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816, 229 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817, 230 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822, 231 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823, 232 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824, 233 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825, 234 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826, 235 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827, 236 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828, 237 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829, 238 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a, 239 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b, 240 MLX5_CMD_OP_SET_WOL_ROL = 0x830, 241 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831, 242 MLX5_CMD_OP_CREATE_LAG = 0x840, 243 MLX5_CMD_OP_MODIFY_LAG = 0x841, 244 MLX5_CMD_OP_QUERY_LAG = 0x842, 245 MLX5_CMD_OP_DESTROY_LAG = 0x843, 246 MLX5_CMD_OP_CREATE_VPORT_LAG = 0x844, 247 MLX5_CMD_OP_DESTROY_VPORT_LAG = 0x845, 248 MLX5_CMD_OP_CREATE_TIR = 0x900, 249 MLX5_CMD_OP_MODIFY_TIR = 0x901, 250 MLX5_CMD_OP_DESTROY_TIR = 0x902, 251 MLX5_CMD_OP_QUERY_TIR = 0x903, 252 MLX5_CMD_OP_CREATE_SQ = 0x904, 253 MLX5_CMD_OP_MODIFY_SQ = 0x905, 254 MLX5_CMD_OP_DESTROY_SQ = 0x906, 255 MLX5_CMD_OP_QUERY_SQ = 0x907, 256 MLX5_CMD_OP_CREATE_RQ = 0x908, 257 MLX5_CMD_OP_MODIFY_RQ = 0x909, 258 MLX5_CMD_OP_SET_DELAY_DROP_PARAMS = 0x910, 259 MLX5_CMD_OP_DESTROY_RQ = 0x90a, 260 MLX5_CMD_OP_QUERY_RQ = 0x90b, 261 MLX5_CMD_OP_CREATE_RMP = 0x90c, 262 MLX5_CMD_OP_MODIFY_RMP = 0x90d, 263 MLX5_CMD_OP_DESTROY_RMP = 0x90e, 264 MLX5_CMD_OP_QUERY_RMP = 0x90f, 265 MLX5_CMD_OP_CREATE_TIS = 0x912, 266 MLX5_CMD_OP_MODIFY_TIS = 0x913, 267 MLX5_CMD_OP_DESTROY_TIS = 0x914, 268 MLX5_CMD_OP_QUERY_TIS = 0x915, 269 MLX5_CMD_OP_CREATE_RQT = 0x916, 270 MLX5_CMD_OP_MODIFY_RQT = 0x917, 271 MLX5_CMD_OP_DESTROY_RQT = 0x918, 272 MLX5_CMD_OP_QUERY_RQT = 0x919, 273 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f, 274 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930, 275 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931, 276 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932, 277 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933, 278 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934, 279 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935, 280 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936, 281 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937, 282 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938, 283 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939, 284 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a, 285 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b, 286 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c, 287 MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT = 0x93d, 288 MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT = 0x93e, 289 MLX5_CMD_OP_QUERY_PACKET_REFORMAT_CONTEXT = 0x93f, 290 MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT = 0x940, 291 MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941, 292 MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT = 0x942, 293 MLX5_CMD_OP_FPGA_CREATE_QP = 0x960, 294 MLX5_CMD_OP_FPGA_MODIFY_QP = 0x961, 295 MLX5_CMD_OP_FPGA_QUERY_QP = 0x962, 296 MLX5_CMD_OP_FPGA_DESTROY_QP = 0x963, 297 MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS = 0x964, 298 MLX5_CMD_OP_CREATE_GENERAL_OBJECT = 0xa00, 299 MLX5_CMD_OP_MODIFY_GENERAL_OBJECT = 0xa01, 300 MLX5_CMD_OP_QUERY_GENERAL_OBJECT = 0xa02, 301 MLX5_CMD_OP_DESTROY_GENERAL_OBJECT = 0xa03, 302 MLX5_CMD_OP_CREATE_UCTX = 0xa04, 303 MLX5_CMD_OP_DESTROY_UCTX = 0xa06, 304 MLX5_CMD_OP_CREATE_UMEM = 0xa08, 305 MLX5_CMD_OP_DESTROY_UMEM = 0xa0a, 306 MLX5_CMD_OP_SYNC_STEERING = 0xb00, 307 MLX5_CMD_OP_QUERY_VHCA_STATE = 0xb0d, 308 MLX5_CMD_OP_MODIFY_VHCA_STATE = 0xb0e, 309 MLX5_CMD_OP_SYNC_CRYPTO = 0xb12, 310 MLX5_CMD_OP_MAX 311 }; 312 313 /* Valid range for general commands that don't work over an object */ 314 enum { 315 MLX5_CMD_OP_GENERAL_START = 0xb00, 316 MLX5_CMD_OP_GENERAL_END = 0xd00, 317 }; 318 319 enum { 320 MLX5_FT_NIC_RX_2_NIC_RX_RDMA = BIT(0), 321 MLX5_FT_NIC_TX_RDMA_2_NIC_TX = BIT(1), 322 }; 323 324 struct mlx5_ifc_flow_table_fields_supported_bits { 325 u8 outer_dmac[0x1]; 326 u8 outer_smac[0x1]; 327 u8 outer_ether_type[0x1]; 328 u8 outer_ip_version[0x1]; 329 u8 outer_first_prio[0x1]; 330 u8 outer_first_cfi[0x1]; 331 u8 outer_first_vid[0x1]; 332 u8 outer_ipv4_ttl[0x1]; 333 u8 outer_second_prio[0x1]; 334 u8 outer_second_cfi[0x1]; 335 u8 outer_second_vid[0x1]; 336 u8 reserved_at_b[0x1]; 337 u8 outer_sip[0x1]; 338 u8 outer_dip[0x1]; 339 u8 outer_frag[0x1]; 340 u8 outer_ip_protocol[0x1]; 341 u8 outer_ip_ecn[0x1]; 342 u8 outer_ip_dscp[0x1]; 343 u8 outer_udp_sport[0x1]; 344 u8 outer_udp_dport[0x1]; 345 u8 outer_tcp_sport[0x1]; 346 u8 outer_tcp_dport[0x1]; 347 u8 outer_tcp_flags[0x1]; 348 u8 outer_gre_protocol[0x1]; 349 u8 outer_gre_key[0x1]; 350 u8 outer_vxlan_vni[0x1]; 351 u8 outer_geneve_vni[0x1]; 352 u8 outer_geneve_oam[0x1]; 353 u8 outer_geneve_protocol_type[0x1]; 354 u8 outer_geneve_opt_len[0x1]; 355 u8 source_vhca_port[0x1]; 356 u8 source_eswitch_port[0x1]; 357 358 u8 inner_dmac[0x1]; 359 u8 inner_smac[0x1]; 360 u8 inner_ether_type[0x1]; 361 u8 inner_ip_version[0x1]; 362 u8 inner_first_prio[0x1]; 363 u8 inner_first_cfi[0x1]; 364 u8 inner_first_vid[0x1]; 365 u8 reserved_at_27[0x1]; 366 u8 inner_second_prio[0x1]; 367 u8 inner_second_cfi[0x1]; 368 u8 inner_second_vid[0x1]; 369 u8 reserved_at_2b[0x1]; 370 u8 inner_sip[0x1]; 371 u8 inner_dip[0x1]; 372 u8 inner_frag[0x1]; 373 u8 inner_ip_protocol[0x1]; 374 u8 inner_ip_ecn[0x1]; 375 u8 inner_ip_dscp[0x1]; 376 u8 inner_udp_sport[0x1]; 377 u8 inner_udp_dport[0x1]; 378 u8 inner_tcp_sport[0x1]; 379 u8 inner_tcp_dport[0x1]; 380 u8 inner_tcp_flags[0x1]; 381 u8 reserved_at_37[0x9]; 382 383 u8 geneve_tlv_option_0_data[0x1]; 384 u8 geneve_tlv_option_0_exist[0x1]; 385 u8 reserved_at_42[0x3]; 386 u8 outer_first_mpls_over_udp[0x4]; 387 u8 outer_first_mpls_over_gre[0x4]; 388 u8 inner_first_mpls[0x4]; 389 u8 outer_first_mpls[0x4]; 390 u8 reserved_at_55[0x2]; 391 u8 outer_esp_spi[0x1]; 392 u8 reserved_at_58[0x2]; 393 u8 bth_dst_qp[0x1]; 394 u8 reserved_at_5b[0x5]; 395 396 u8 reserved_at_60[0x18]; 397 u8 metadata_reg_c_7[0x1]; 398 u8 metadata_reg_c_6[0x1]; 399 u8 metadata_reg_c_5[0x1]; 400 u8 metadata_reg_c_4[0x1]; 401 u8 metadata_reg_c_3[0x1]; 402 u8 metadata_reg_c_2[0x1]; 403 u8 metadata_reg_c_1[0x1]; 404 u8 metadata_reg_c_0[0x1]; 405 }; 406 407 struct mlx5_ifc_flow_table_fields_supported_2_bits { 408 u8 reserved_at_0[0xe]; 409 u8 bth_opcode[0x1]; 410 u8 reserved_at_f[0x11]; 411 412 u8 reserved_at_20[0x60]; 413 }; 414 415 struct mlx5_ifc_flow_table_prop_layout_bits { 416 u8 ft_support[0x1]; 417 u8 reserved_at_1[0x1]; 418 u8 flow_counter[0x1]; 419 u8 flow_modify_en[0x1]; 420 u8 modify_root[0x1]; 421 u8 identified_miss_table_mode[0x1]; 422 u8 flow_table_modify[0x1]; 423 u8 reformat[0x1]; 424 u8 decap[0x1]; 425 u8 reserved_at_9[0x1]; 426 u8 pop_vlan[0x1]; 427 u8 push_vlan[0x1]; 428 u8 reserved_at_c[0x1]; 429 u8 pop_vlan_2[0x1]; 430 u8 push_vlan_2[0x1]; 431 u8 reformat_and_vlan_action[0x1]; 432 u8 reserved_at_10[0x1]; 433 u8 sw_owner[0x1]; 434 u8 reformat_l3_tunnel_to_l2[0x1]; 435 u8 reformat_l2_to_l3_tunnel[0x1]; 436 u8 reformat_and_modify_action[0x1]; 437 u8 ignore_flow_level[0x1]; 438 u8 reserved_at_16[0x1]; 439 u8 table_miss_action_domain[0x1]; 440 u8 termination_table[0x1]; 441 u8 reformat_and_fwd_to_table[0x1]; 442 u8 reserved_at_1a[0x2]; 443 u8 ipsec_encrypt[0x1]; 444 u8 ipsec_decrypt[0x1]; 445 u8 sw_owner_v2[0x1]; 446 u8 reserved_at_1f[0x1]; 447 448 u8 termination_table_raw_traffic[0x1]; 449 u8 reserved_at_21[0x1]; 450 u8 log_max_ft_size[0x6]; 451 u8 log_max_modify_header_context[0x8]; 452 u8 max_modify_header_actions[0x8]; 453 u8 max_ft_level[0x8]; 454 455 u8 reformat_add_esp_trasport[0x1]; 456 u8 reserved_at_41[0x2]; 457 u8 reformat_del_esp_trasport[0x1]; 458 u8 reserved_at_44[0x2]; 459 u8 execute_aso[0x1]; 460 u8 reserved_at_47[0x19]; 461 462 u8 reserved_at_60[0x2]; 463 u8 reformat_insert[0x1]; 464 u8 reformat_remove[0x1]; 465 u8 macsec_encrypt[0x1]; 466 u8 macsec_decrypt[0x1]; 467 u8 reserved_at_66[0x2]; 468 u8 reformat_add_macsec[0x1]; 469 u8 reformat_remove_macsec[0x1]; 470 u8 reserved_at_6a[0xe]; 471 u8 log_max_ft_num[0x8]; 472 473 u8 reserved_at_80[0x10]; 474 u8 log_max_flow_counter[0x8]; 475 u8 log_max_destination[0x8]; 476 477 u8 reserved_at_a0[0x18]; 478 u8 log_max_flow[0x8]; 479 480 u8 reserved_at_c0[0x40]; 481 482 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support; 483 484 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support; 485 }; 486 487 struct mlx5_ifc_odp_per_transport_service_cap_bits { 488 u8 send[0x1]; 489 u8 receive[0x1]; 490 u8 write[0x1]; 491 u8 read[0x1]; 492 u8 atomic[0x1]; 493 u8 srq_receive[0x1]; 494 u8 reserved_at_6[0x1a]; 495 }; 496 497 struct mlx5_ifc_ipv4_layout_bits { 498 u8 reserved_at_0[0x60]; 499 500 u8 ipv4[0x20]; 501 }; 502 503 struct mlx5_ifc_ipv6_layout_bits { 504 u8 ipv6[16][0x8]; 505 }; 506 507 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits { 508 struct mlx5_ifc_ipv6_layout_bits ipv6_layout; 509 struct mlx5_ifc_ipv4_layout_bits ipv4_layout; 510 u8 reserved_at_0[0x80]; 511 }; 512 513 struct mlx5_ifc_fte_match_set_lyr_2_4_bits { 514 u8 smac_47_16[0x20]; 515 516 u8 smac_15_0[0x10]; 517 u8 ethertype[0x10]; 518 519 u8 dmac_47_16[0x20]; 520 521 u8 dmac_15_0[0x10]; 522 u8 first_prio[0x3]; 523 u8 first_cfi[0x1]; 524 u8 first_vid[0xc]; 525 526 u8 ip_protocol[0x8]; 527 u8 ip_dscp[0x6]; 528 u8 ip_ecn[0x2]; 529 u8 cvlan_tag[0x1]; 530 u8 svlan_tag[0x1]; 531 u8 frag[0x1]; 532 u8 ip_version[0x4]; 533 u8 tcp_flags[0x9]; 534 535 u8 tcp_sport[0x10]; 536 u8 tcp_dport[0x10]; 537 538 u8 reserved_at_c0[0x10]; 539 u8 ipv4_ihl[0x4]; 540 u8 reserved_at_c4[0x4]; 541 542 u8 ttl_hoplimit[0x8]; 543 544 u8 udp_sport[0x10]; 545 u8 udp_dport[0x10]; 546 547 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6; 548 549 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6; 550 }; 551 552 struct mlx5_ifc_nvgre_key_bits { 553 u8 hi[0x18]; 554 u8 lo[0x8]; 555 }; 556 557 union mlx5_ifc_gre_key_bits { 558 struct mlx5_ifc_nvgre_key_bits nvgre; 559 u8 key[0x20]; 560 }; 561 562 struct mlx5_ifc_fte_match_set_misc_bits { 563 u8 gre_c_present[0x1]; 564 u8 reserved_at_1[0x1]; 565 u8 gre_k_present[0x1]; 566 u8 gre_s_present[0x1]; 567 u8 source_vhca_port[0x4]; 568 u8 source_sqn[0x18]; 569 570 u8 source_eswitch_owner_vhca_id[0x10]; 571 u8 source_port[0x10]; 572 573 u8 outer_second_prio[0x3]; 574 u8 outer_second_cfi[0x1]; 575 u8 outer_second_vid[0xc]; 576 u8 inner_second_prio[0x3]; 577 u8 inner_second_cfi[0x1]; 578 u8 inner_second_vid[0xc]; 579 580 u8 outer_second_cvlan_tag[0x1]; 581 u8 inner_second_cvlan_tag[0x1]; 582 u8 outer_second_svlan_tag[0x1]; 583 u8 inner_second_svlan_tag[0x1]; 584 u8 reserved_at_64[0xc]; 585 u8 gre_protocol[0x10]; 586 587 union mlx5_ifc_gre_key_bits gre_key; 588 589 u8 vxlan_vni[0x18]; 590 u8 bth_opcode[0x8]; 591 592 u8 geneve_vni[0x18]; 593 u8 reserved_at_d8[0x6]; 594 u8 geneve_tlv_option_0_exist[0x1]; 595 u8 geneve_oam[0x1]; 596 597 u8 reserved_at_e0[0xc]; 598 u8 outer_ipv6_flow_label[0x14]; 599 600 u8 reserved_at_100[0xc]; 601 u8 inner_ipv6_flow_label[0x14]; 602 603 u8 reserved_at_120[0xa]; 604 u8 geneve_opt_len[0x6]; 605 u8 geneve_protocol_type[0x10]; 606 607 u8 reserved_at_140[0x8]; 608 u8 bth_dst_qp[0x18]; 609 u8 reserved_at_160[0x20]; 610 u8 outer_esp_spi[0x20]; 611 u8 reserved_at_1a0[0x60]; 612 }; 613 614 struct mlx5_ifc_fte_match_mpls_bits { 615 u8 mpls_label[0x14]; 616 u8 mpls_exp[0x3]; 617 u8 mpls_s_bos[0x1]; 618 u8 mpls_ttl[0x8]; 619 }; 620 621 struct mlx5_ifc_fte_match_set_misc2_bits { 622 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls; 623 624 struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls; 625 626 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre; 627 628 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp; 629 630 u8 metadata_reg_c_7[0x20]; 631 632 u8 metadata_reg_c_6[0x20]; 633 634 u8 metadata_reg_c_5[0x20]; 635 636 u8 metadata_reg_c_4[0x20]; 637 638 u8 metadata_reg_c_3[0x20]; 639 640 u8 metadata_reg_c_2[0x20]; 641 642 u8 metadata_reg_c_1[0x20]; 643 644 u8 metadata_reg_c_0[0x20]; 645 646 u8 metadata_reg_a[0x20]; 647 648 u8 reserved_at_1a0[0x8]; 649 650 u8 macsec_syndrome[0x8]; 651 u8 ipsec_syndrome[0x8]; 652 u8 reserved_at_1b8[0x8]; 653 654 u8 reserved_at_1c0[0x40]; 655 }; 656 657 struct mlx5_ifc_fte_match_set_misc3_bits { 658 u8 inner_tcp_seq_num[0x20]; 659 660 u8 outer_tcp_seq_num[0x20]; 661 662 u8 inner_tcp_ack_num[0x20]; 663 664 u8 outer_tcp_ack_num[0x20]; 665 666 u8 reserved_at_80[0x8]; 667 u8 outer_vxlan_gpe_vni[0x18]; 668 669 u8 outer_vxlan_gpe_next_protocol[0x8]; 670 u8 outer_vxlan_gpe_flags[0x8]; 671 u8 reserved_at_b0[0x10]; 672 673 u8 icmp_header_data[0x20]; 674 675 u8 icmpv6_header_data[0x20]; 676 677 u8 icmp_type[0x8]; 678 u8 icmp_code[0x8]; 679 u8 icmpv6_type[0x8]; 680 u8 icmpv6_code[0x8]; 681 682 u8 geneve_tlv_option_0_data[0x20]; 683 684 u8 gtpu_teid[0x20]; 685 686 u8 gtpu_msg_type[0x8]; 687 u8 gtpu_msg_flags[0x8]; 688 u8 reserved_at_170[0x10]; 689 690 u8 gtpu_dw_2[0x20]; 691 692 u8 gtpu_first_ext_dw_0[0x20]; 693 694 u8 gtpu_dw_0[0x20]; 695 696 u8 reserved_at_1e0[0x20]; 697 }; 698 699 struct mlx5_ifc_fte_match_set_misc4_bits { 700 u8 prog_sample_field_value_0[0x20]; 701 702 u8 prog_sample_field_id_0[0x20]; 703 704 u8 prog_sample_field_value_1[0x20]; 705 706 u8 prog_sample_field_id_1[0x20]; 707 708 u8 prog_sample_field_value_2[0x20]; 709 710 u8 prog_sample_field_id_2[0x20]; 711 712 u8 prog_sample_field_value_3[0x20]; 713 714 u8 prog_sample_field_id_3[0x20]; 715 716 u8 reserved_at_100[0x100]; 717 }; 718 719 struct mlx5_ifc_fte_match_set_misc5_bits { 720 u8 macsec_tag_0[0x20]; 721 722 u8 macsec_tag_1[0x20]; 723 724 u8 macsec_tag_2[0x20]; 725 726 u8 macsec_tag_3[0x20]; 727 728 u8 tunnel_header_0[0x20]; 729 730 u8 tunnel_header_1[0x20]; 731 732 u8 tunnel_header_2[0x20]; 733 734 u8 tunnel_header_3[0x20]; 735 736 u8 reserved_at_100[0x100]; 737 }; 738 739 struct mlx5_ifc_cmd_pas_bits { 740 u8 pa_h[0x20]; 741 742 u8 pa_l[0x14]; 743 u8 reserved_at_34[0xc]; 744 }; 745 746 struct mlx5_ifc_uint64_bits { 747 u8 hi[0x20]; 748 749 u8 lo[0x20]; 750 }; 751 752 enum { 753 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0, 754 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7, 755 MLX5_ADS_STAT_RATE_10GBPS = 0x8, 756 MLX5_ADS_STAT_RATE_30GBPS = 0x9, 757 MLX5_ADS_STAT_RATE_5GBPS = 0xa, 758 MLX5_ADS_STAT_RATE_20GBPS = 0xb, 759 MLX5_ADS_STAT_RATE_40GBPS = 0xc, 760 MLX5_ADS_STAT_RATE_60GBPS = 0xd, 761 MLX5_ADS_STAT_RATE_80GBPS = 0xe, 762 MLX5_ADS_STAT_RATE_120GBPS = 0xf, 763 }; 764 765 struct mlx5_ifc_ads_bits { 766 u8 fl[0x1]; 767 u8 free_ar[0x1]; 768 u8 reserved_at_2[0xe]; 769 u8 pkey_index[0x10]; 770 771 u8 reserved_at_20[0x8]; 772 u8 grh[0x1]; 773 u8 mlid[0x7]; 774 u8 rlid[0x10]; 775 776 u8 ack_timeout[0x5]; 777 u8 reserved_at_45[0x3]; 778 u8 src_addr_index[0x8]; 779 u8 reserved_at_50[0x4]; 780 u8 stat_rate[0x4]; 781 u8 hop_limit[0x8]; 782 783 u8 reserved_at_60[0x4]; 784 u8 tclass[0x8]; 785 u8 flow_label[0x14]; 786 787 u8 rgid_rip[16][0x8]; 788 789 u8 reserved_at_100[0x4]; 790 u8 f_dscp[0x1]; 791 u8 f_ecn[0x1]; 792 u8 reserved_at_106[0x1]; 793 u8 f_eth_prio[0x1]; 794 u8 ecn[0x2]; 795 u8 dscp[0x6]; 796 u8 udp_sport[0x10]; 797 798 u8 dei_cfi[0x1]; 799 u8 eth_prio[0x3]; 800 u8 sl[0x4]; 801 u8 vhca_port_num[0x8]; 802 u8 rmac_47_32[0x10]; 803 804 u8 rmac_31_0[0x20]; 805 }; 806 807 struct mlx5_ifc_flow_table_nic_cap_bits { 808 u8 nic_rx_multi_path_tirs[0x1]; 809 u8 nic_rx_multi_path_tirs_fts[0x1]; 810 u8 allow_sniffer_and_nic_rx_shared_tir[0x1]; 811 u8 reserved_at_3[0x4]; 812 u8 sw_owner_reformat_supported[0x1]; 813 u8 reserved_at_8[0x18]; 814 815 u8 encap_general_header[0x1]; 816 u8 reserved_at_21[0xa]; 817 u8 log_max_packet_reformat_context[0x5]; 818 u8 reserved_at_30[0x6]; 819 u8 max_encap_header_size[0xa]; 820 u8 reserved_at_40[0x1c0]; 821 822 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive; 823 824 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_rdma; 825 826 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer; 827 828 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit; 829 830 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_rdma; 831 832 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer; 833 834 u8 reserved_at_e00[0x700]; 835 836 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_receive_rdma; 837 838 u8 reserved_at_1580[0x280]; 839 840 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_transmit_rdma; 841 842 u8 reserved_at_1880[0x780]; 843 844 u8 sw_steering_nic_rx_action_drop_icm_address[0x40]; 845 846 u8 sw_steering_nic_tx_action_drop_icm_address[0x40]; 847 848 u8 sw_steering_nic_tx_action_allow_icm_address[0x40]; 849 850 u8 reserved_at_20c0[0x5f40]; 851 }; 852 853 struct mlx5_ifc_port_selection_cap_bits { 854 u8 reserved_at_0[0x10]; 855 u8 port_select_flow_table[0x1]; 856 u8 reserved_at_11[0x1]; 857 u8 port_select_flow_table_bypass[0x1]; 858 u8 reserved_at_13[0xd]; 859 860 u8 reserved_at_20[0x1e0]; 861 862 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_port_selection; 863 864 u8 reserved_at_400[0x7c00]; 865 }; 866 867 enum { 868 MLX5_FDB_TO_VPORT_REG_C_0 = 0x01, 869 MLX5_FDB_TO_VPORT_REG_C_1 = 0x02, 870 MLX5_FDB_TO_VPORT_REG_C_2 = 0x04, 871 MLX5_FDB_TO_VPORT_REG_C_3 = 0x08, 872 MLX5_FDB_TO_VPORT_REG_C_4 = 0x10, 873 MLX5_FDB_TO_VPORT_REG_C_5 = 0x20, 874 MLX5_FDB_TO_VPORT_REG_C_6 = 0x40, 875 MLX5_FDB_TO_VPORT_REG_C_7 = 0x80, 876 }; 877 878 struct mlx5_ifc_flow_table_eswitch_cap_bits { 879 u8 fdb_to_vport_reg_c_id[0x8]; 880 u8 reserved_at_8[0xd]; 881 u8 fdb_modify_header_fwd_to_table[0x1]; 882 u8 fdb_ipv4_ttl_modify[0x1]; 883 u8 flow_source[0x1]; 884 u8 reserved_at_18[0x2]; 885 u8 multi_fdb_encap[0x1]; 886 u8 egress_acl_forward_to_vport[0x1]; 887 u8 fdb_multi_path_to_table[0x1]; 888 u8 reserved_at_1d[0x3]; 889 890 u8 reserved_at_20[0x1e0]; 891 892 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb; 893 894 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress; 895 896 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress; 897 898 u8 reserved_at_800[0x1000]; 899 900 u8 sw_steering_fdb_action_drop_icm_address_rx[0x40]; 901 902 u8 sw_steering_fdb_action_drop_icm_address_tx[0x40]; 903 904 u8 sw_steering_uplink_icm_address_rx[0x40]; 905 906 u8 sw_steering_uplink_icm_address_tx[0x40]; 907 908 u8 reserved_at_1900[0x6700]; 909 }; 910 911 enum { 912 MLX5_COUNTER_SOURCE_ESWITCH = 0x0, 913 MLX5_COUNTER_FLOW_ESWITCH = 0x1, 914 }; 915 916 struct mlx5_ifc_e_switch_cap_bits { 917 u8 vport_svlan_strip[0x1]; 918 u8 vport_cvlan_strip[0x1]; 919 u8 vport_svlan_insert[0x1]; 920 u8 vport_cvlan_insert_if_not_exist[0x1]; 921 u8 vport_cvlan_insert_overwrite[0x1]; 922 u8 reserved_at_5[0x1]; 923 u8 vport_cvlan_insert_always[0x1]; 924 u8 esw_shared_ingress_acl[0x1]; 925 u8 esw_uplink_ingress_acl[0x1]; 926 u8 root_ft_on_other_esw[0x1]; 927 u8 reserved_at_a[0xf]; 928 u8 esw_functions_changed[0x1]; 929 u8 reserved_at_1a[0x1]; 930 u8 ecpf_vport_exists[0x1]; 931 u8 counter_eswitch_affinity[0x1]; 932 u8 merged_eswitch[0x1]; 933 u8 nic_vport_node_guid_modify[0x1]; 934 u8 nic_vport_port_guid_modify[0x1]; 935 936 u8 vxlan_encap_decap[0x1]; 937 u8 nvgre_encap_decap[0x1]; 938 u8 reserved_at_22[0x1]; 939 u8 log_max_fdb_encap_uplink[0x5]; 940 u8 reserved_at_21[0x3]; 941 u8 log_max_packet_reformat_context[0x5]; 942 u8 reserved_2b[0x6]; 943 u8 max_encap_header_size[0xa]; 944 945 u8 reserved_at_40[0xb]; 946 u8 log_max_esw_sf[0x5]; 947 u8 esw_sf_base_id[0x10]; 948 949 u8 reserved_at_60[0x7a0]; 950 951 }; 952 953 struct mlx5_ifc_qos_cap_bits { 954 u8 packet_pacing[0x1]; 955 u8 esw_scheduling[0x1]; 956 u8 esw_bw_share[0x1]; 957 u8 esw_rate_limit[0x1]; 958 u8 reserved_at_4[0x1]; 959 u8 packet_pacing_burst_bound[0x1]; 960 u8 packet_pacing_typical_size[0x1]; 961 u8 reserved_at_7[0x1]; 962 u8 nic_sq_scheduling[0x1]; 963 u8 nic_bw_share[0x1]; 964 u8 nic_rate_limit[0x1]; 965 u8 packet_pacing_uid[0x1]; 966 u8 log_esw_max_sched_depth[0x4]; 967 u8 reserved_at_10[0x10]; 968 969 u8 reserved_at_20[0xb]; 970 u8 log_max_qos_nic_queue_group[0x5]; 971 u8 reserved_at_30[0x10]; 972 973 u8 packet_pacing_max_rate[0x20]; 974 975 u8 packet_pacing_min_rate[0x20]; 976 977 u8 reserved_at_80[0x10]; 978 u8 packet_pacing_rate_table_size[0x10]; 979 980 u8 esw_element_type[0x10]; 981 u8 esw_tsar_type[0x10]; 982 983 u8 reserved_at_c0[0x10]; 984 u8 max_qos_para_vport[0x10]; 985 986 u8 max_tsar_bw_share[0x20]; 987 988 u8 reserved_at_100[0x20]; 989 990 u8 reserved_at_120[0x3]; 991 u8 log_meter_aso_granularity[0x5]; 992 u8 reserved_at_128[0x3]; 993 u8 log_meter_aso_max_alloc[0x5]; 994 u8 reserved_at_130[0x3]; 995 u8 log_max_num_meter_aso[0x5]; 996 u8 reserved_at_138[0x8]; 997 998 u8 reserved_at_140[0x6c0]; 999 }; 1000 1001 struct mlx5_ifc_debug_cap_bits { 1002 u8 core_dump_general[0x1]; 1003 u8 core_dump_qp[0x1]; 1004 u8 reserved_at_2[0x7]; 1005 u8 resource_dump[0x1]; 1006 u8 reserved_at_a[0x16]; 1007 1008 u8 reserved_at_20[0x2]; 1009 u8 stall_detect[0x1]; 1010 u8 reserved_at_23[0x1d]; 1011 1012 u8 reserved_at_40[0x7c0]; 1013 }; 1014 1015 struct mlx5_ifc_per_protocol_networking_offload_caps_bits { 1016 u8 csum_cap[0x1]; 1017 u8 vlan_cap[0x1]; 1018 u8 lro_cap[0x1]; 1019 u8 lro_psh_flag[0x1]; 1020 u8 lro_time_stamp[0x1]; 1021 u8 reserved_at_5[0x2]; 1022 u8 wqe_vlan_insert[0x1]; 1023 u8 self_lb_en_modifiable[0x1]; 1024 u8 reserved_at_9[0x2]; 1025 u8 max_lso_cap[0x5]; 1026 u8 multi_pkt_send_wqe[0x2]; 1027 u8 wqe_inline_mode[0x2]; 1028 u8 rss_ind_tbl_cap[0x4]; 1029 u8 reg_umr_sq[0x1]; 1030 u8 scatter_fcs[0x1]; 1031 u8 enhanced_multi_pkt_send_wqe[0x1]; 1032 u8 tunnel_lso_const_out_ip_id[0x1]; 1033 u8 tunnel_lro_gre[0x1]; 1034 u8 tunnel_lro_vxlan[0x1]; 1035 u8 tunnel_stateless_gre[0x1]; 1036 u8 tunnel_stateless_vxlan[0x1]; 1037 1038 u8 swp[0x1]; 1039 u8 swp_csum[0x1]; 1040 u8 swp_lso[0x1]; 1041 u8 cqe_checksum_full[0x1]; 1042 u8 tunnel_stateless_geneve_tx[0x1]; 1043 u8 tunnel_stateless_mpls_over_udp[0x1]; 1044 u8 tunnel_stateless_mpls_over_gre[0x1]; 1045 u8 tunnel_stateless_vxlan_gpe[0x1]; 1046 u8 tunnel_stateless_ipv4_over_vxlan[0x1]; 1047 u8 tunnel_stateless_ip_over_ip[0x1]; 1048 u8 insert_trailer[0x1]; 1049 u8 reserved_at_2b[0x1]; 1050 u8 tunnel_stateless_ip_over_ip_rx[0x1]; 1051 u8 tunnel_stateless_ip_over_ip_tx[0x1]; 1052 u8 reserved_at_2e[0x2]; 1053 u8 max_vxlan_udp_ports[0x8]; 1054 u8 reserved_at_38[0x6]; 1055 u8 max_geneve_opt_len[0x1]; 1056 u8 tunnel_stateless_geneve_rx[0x1]; 1057 1058 u8 reserved_at_40[0x10]; 1059 u8 lro_min_mss_size[0x10]; 1060 1061 u8 reserved_at_60[0x120]; 1062 1063 u8 lro_timer_supported_periods[4][0x20]; 1064 1065 u8 reserved_at_200[0x600]; 1066 }; 1067 1068 enum { 1069 MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING = 0x0, 1070 MLX5_TIMESTAMP_FORMAT_CAP_REAL_TIME = 0x1, 1071 MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING_AND_REAL_TIME = 0x2, 1072 }; 1073 1074 struct mlx5_ifc_roce_cap_bits { 1075 u8 roce_apm[0x1]; 1076 u8 reserved_at_1[0x3]; 1077 u8 sw_r_roce_src_udp_port[0x1]; 1078 u8 fl_rc_qp_when_roce_disabled[0x1]; 1079 u8 fl_rc_qp_when_roce_enabled[0x1]; 1080 u8 reserved_at_7[0x17]; 1081 u8 qp_ts_format[0x2]; 1082 1083 u8 reserved_at_20[0x60]; 1084 1085 u8 reserved_at_80[0xc]; 1086 u8 l3_type[0x4]; 1087 u8 reserved_at_90[0x8]; 1088 u8 roce_version[0x8]; 1089 1090 u8 reserved_at_a0[0x10]; 1091 u8 r_roce_dest_udp_port[0x10]; 1092 1093 u8 r_roce_max_src_udp_port[0x10]; 1094 u8 r_roce_min_src_udp_port[0x10]; 1095 1096 u8 reserved_at_e0[0x10]; 1097 u8 roce_address_table_size[0x10]; 1098 1099 u8 reserved_at_100[0x700]; 1100 }; 1101 1102 struct mlx5_ifc_sync_steering_in_bits { 1103 u8 opcode[0x10]; 1104 u8 uid[0x10]; 1105 1106 u8 reserved_at_20[0x10]; 1107 u8 op_mod[0x10]; 1108 1109 u8 reserved_at_40[0xc0]; 1110 }; 1111 1112 struct mlx5_ifc_sync_steering_out_bits { 1113 u8 status[0x8]; 1114 u8 reserved_at_8[0x18]; 1115 1116 u8 syndrome[0x20]; 1117 1118 u8 reserved_at_40[0x40]; 1119 }; 1120 1121 struct mlx5_ifc_sync_crypto_in_bits { 1122 u8 opcode[0x10]; 1123 u8 uid[0x10]; 1124 1125 u8 reserved_at_20[0x10]; 1126 u8 op_mod[0x10]; 1127 1128 u8 reserved_at_40[0x20]; 1129 1130 u8 reserved_at_60[0x10]; 1131 u8 crypto_type[0x10]; 1132 1133 u8 reserved_at_80[0x80]; 1134 }; 1135 1136 struct mlx5_ifc_sync_crypto_out_bits { 1137 u8 status[0x8]; 1138 u8 reserved_at_8[0x18]; 1139 1140 u8 syndrome[0x20]; 1141 1142 u8 reserved_at_40[0x40]; 1143 }; 1144 1145 struct mlx5_ifc_device_mem_cap_bits { 1146 u8 memic[0x1]; 1147 u8 reserved_at_1[0x1f]; 1148 1149 u8 reserved_at_20[0xb]; 1150 u8 log_min_memic_alloc_size[0x5]; 1151 u8 reserved_at_30[0x8]; 1152 u8 log_max_memic_addr_alignment[0x8]; 1153 1154 u8 memic_bar_start_addr[0x40]; 1155 1156 u8 memic_bar_size[0x20]; 1157 1158 u8 max_memic_size[0x20]; 1159 1160 u8 steering_sw_icm_start_address[0x40]; 1161 1162 u8 reserved_at_100[0x8]; 1163 u8 log_header_modify_sw_icm_size[0x8]; 1164 u8 reserved_at_110[0x2]; 1165 u8 log_sw_icm_alloc_granularity[0x6]; 1166 u8 log_steering_sw_icm_size[0x8]; 1167 1168 u8 reserved_at_120[0x18]; 1169 u8 log_header_modify_pattern_sw_icm_size[0x8]; 1170 1171 u8 header_modify_sw_icm_start_address[0x40]; 1172 1173 u8 reserved_at_180[0x40]; 1174 1175 u8 header_modify_pattern_sw_icm_start_address[0x40]; 1176 1177 u8 memic_operations[0x20]; 1178 1179 u8 reserved_at_220[0x5e0]; 1180 }; 1181 1182 struct mlx5_ifc_device_event_cap_bits { 1183 u8 user_affiliated_events[4][0x40]; 1184 1185 u8 user_unaffiliated_events[4][0x40]; 1186 }; 1187 1188 struct mlx5_ifc_virtio_emulation_cap_bits { 1189 u8 desc_tunnel_offload_type[0x1]; 1190 u8 eth_frame_offload_type[0x1]; 1191 u8 virtio_version_1_0[0x1]; 1192 u8 device_features_bits_mask[0xd]; 1193 u8 event_mode[0x8]; 1194 u8 virtio_queue_type[0x8]; 1195 1196 u8 max_tunnel_desc[0x10]; 1197 u8 reserved_at_30[0x3]; 1198 u8 log_doorbell_stride[0x5]; 1199 u8 reserved_at_38[0x3]; 1200 u8 log_doorbell_bar_size[0x5]; 1201 1202 u8 doorbell_bar_offset[0x40]; 1203 1204 u8 max_emulated_devices[0x8]; 1205 u8 max_num_virtio_queues[0x18]; 1206 1207 u8 reserved_at_a0[0x60]; 1208 1209 u8 umem_1_buffer_param_a[0x20]; 1210 1211 u8 umem_1_buffer_param_b[0x20]; 1212 1213 u8 umem_2_buffer_param_a[0x20]; 1214 1215 u8 umem_2_buffer_param_b[0x20]; 1216 1217 u8 umem_3_buffer_param_a[0x20]; 1218 1219 u8 umem_3_buffer_param_b[0x20]; 1220 1221 u8 reserved_at_1c0[0x640]; 1222 }; 1223 1224 enum { 1225 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0, 1226 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2, 1227 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4, 1228 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8, 1229 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10, 1230 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20, 1231 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40, 1232 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80, 1233 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100, 1234 }; 1235 1236 enum { 1237 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1, 1238 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2, 1239 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4, 1240 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8, 1241 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10, 1242 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20, 1243 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40, 1244 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80, 1245 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100, 1246 }; 1247 1248 struct mlx5_ifc_atomic_caps_bits { 1249 u8 reserved_at_0[0x40]; 1250 1251 u8 atomic_req_8B_endianness_mode[0x2]; 1252 u8 reserved_at_42[0x4]; 1253 u8 supported_atomic_req_8B_endianness_mode_1[0x1]; 1254 1255 u8 reserved_at_47[0x19]; 1256 1257 u8 reserved_at_60[0x20]; 1258 1259 u8 reserved_at_80[0x10]; 1260 u8 atomic_operations[0x10]; 1261 1262 u8 reserved_at_a0[0x10]; 1263 u8 atomic_size_qp[0x10]; 1264 1265 u8 reserved_at_c0[0x10]; 1266 u8 atomic_size_dc[0x10]; 1267 1268 u8 reserved_at_e0[0x720]; 1269 }; 1270 1271 struct mlx5_ifc_odp_cap_bits { 1272 u8 reserved_at_0[0x40]; 1273 1274 u8 sig[0x1]; 1275 u8 reserved_at_41[0x1f]; 1276 1277 u8 reserved_at_60[0x20]; 1278 1279 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps; 1280 1281 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps; 1282 1283 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps; 1284 1285 struct mlx5_ifc_odp_per_transport_service_cap_bits xrc_odp_caps; 1286 1287 struct mlx5_ifc_odp_per_transport_service_cap_bits dc_odp_caps; 1288 1289 u8 reserved_at_120[0x6E0]; 1290 }; 1291 1292 struct mlx5_ifc_calc_op { 1293 u8 reserved_at_0[0x10]; 1294 u8 reserved_at_10[0x9]; 1295 u8 op_swap_endianness[0x1]; 1296 u8 op_min[0x1]; 1297 u8 op_xor[0x1]; 1298 u8 op_or[0x1]; 1299 u8 op_and[0x1]; 1300 u8 op_max[0x1]; 1301 u8 op_add[0x1]; 1302 }; 1303 1304 struct mlx5_ifc_vector_calc_cap_bits { 1305 u8 calc_matrix[0x1]; 1306 u8 reserved_at_1[0x1f]; 1307 u8 reserved_at_20[0x8]; 1308 u8 max_vec_count[0x8]; 1309 u8 reserved_at_30[0xd]; 1310 u8 max_chunk_size[0x3]; 1311 struct mlx5_ifc_calc_op calc0; 1312 struct mlx5_ifc_calc_op calc1; 1313 struct mlx5_ifc_calc_op calc2; 1314 struct mlx5_ifc_calc_op calc3; 1315 1316 u8 reserved_at_c0[0x720]; 1317 }; 1318 1319 struct mlx5_ifc_tls_cap_bits { 1320 u8 tls_1_2_aes_gcm_128[0x1]; 1321 u8 tls_1_3_aes_gcm_128[0x1]; 1322 u8 tls_1_2_aes_gcm_256[0x1]; 1323 u8 tls_1_3_aes_gcm_256[0x1]; 1324 u8 reserved_at_4[0x1c]; 1325 1326 u8 reserved_at_20[0x7e0]; 1327 }; 1328 1329 struct mlx5_ifc_ipsec_cap_bits { 1330 u8 ipsec_full_offload[0x1]; 1331 u8 ipsec_crypto_offload[0x1]; 1332 u8 ipsec_esn[0x1]; 1333 u8 ipsec_crypto_esp_aes_gcm_256_encrypt[0x1]; 1334 u8 ipsec_crypto_esp_aes_gcm_128_encrypt[0x1]; 1335 u8 ipsec_crypto_esp_aes_gcm_256_decrypt[0x1]; 1336 u8 ipsec_crypto_esp_aes_gcm_128_decrypt[0x1]; 1337 u8 reserved_at_7[0x4]; 1338 u8 log_max_ipsec_offload[0x5]; 1339 u8 reserved_at_10[0x10]; 1340 1341 u8 min_log_ipsec_full_replay_window[0x8]; 1342 u8 max_log_ipsec_full_replay_window[0x8]; 1343 u8 reserved_at_30[0x7d0]; 1344 }; 1345 1346 struct mlx5_ifc_macsec_cap_bits { 1347 u8 macsec_epn[0x1]; 1348 u8 reserved_at_1[0x2]; 1349 u8 macsec_crypto_esp_aes_gcm_256_encrypt[0x1]; 1350 u8 macsec_crypto_esp_aes_gcm_128_encrypt[0x1]; 1351 u8 macsec_crypto_esp_aes_gcm_256_decrypt[0x1]; 1352 u8 macsec_crypto_esp_aes_gcm_128_decrypt[0x1]; 1353 u8 reserved_at_7[0x4]; 1354 u8 log_max_macsec_offload[0x5]; 1355 u8 reserved_at_10[0x10]; 1356 1357 u8 min_log_macsec_full_replay_window[0x8]; 1358 u8 max_log_macsec_full_replay_window[0x8]; 1359 u8 reserved_at_30[0x10]; 1360 1361 u8 reserved_at_40[0x7c0]; 1362 }; 1363 1364 enum { 1365 MLX5_WQ_TYPE_LINKED_LIST = 0x0, 1366 MLX5_WQ_TYPE_CYCLIC = 0x1, 1367 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2, 1368 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3, 1369 }; 1370 1371 enum { 1372 MLX5_WQ_END_PAD_MODE_NONE = 0x0, 1373 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1, 1374 }; 1375 1376 enum { 1377 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0, 1378 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1, 1379 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2, 1380 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3, 1381 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4, 1382 }; 1383 1384 enum { 1385 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0, 1386 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1, 1387 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2, 1388 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3, 1389 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4, 1390 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5, 1391 }; 1392 1393 enum { 1394 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0, 1395 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1, 1396 }; 1397 1398 enum { 1399 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0, 1400 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1, 1401 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3, 1402 }; 1403 1404 enum { 1405 MLX5_CAP_PORT_TYPE_IB = 0x0, 1406 MLX5_CAP_PORT_TYPE_ETH = 0x1, 1407 }; 1408 1409 enum { 1410 MLX5_CAP_UMR_FENCE_STRONG = 0x0, 1411 MLX5_CAP_UMR_FENCE_SMALL = 0x1, 1412 MLX5_CAP_UMR_FENCE_NONE = 0x2, 1413 }; 1414 1415 enum { 1416 MLX5_FLEX_PARSER_GENEVE_ENABLED = 1 << 3, 1417 MLX5_FLEX_PARSER_MPLS_OVER_GRE_ENABLED = 1 << 4, 1418 MLX5_FLEX_PARSER_MPLS_OVER_UDP_ENABLED = 1 << 5, 1419 MLX5_FLEX_PARSER_VXLAN_GPE_ENABLED = 1 << 7, 1420 MLX5_FLEX_PARSER_ICMP_V4_ENABLED = 1 << 8, 1421 MLX5_FLEX_PARSER_ICMP_V6_ENABLED = 1 << 9, 1422 MLX5_FLEX_PARSER_GENEVE_TLV_OPTION_0_ENABLED = 1 << 10, 1423 MLX5_FLEX_PARSER_GTPU_ENABLED = 1 << 11, 1424 MLX5_FLEX_PARSER_GTPU_DW_2_ENABLED = 1 << 16, 1425 MLX5_FLEX_PARSER_GTPU_FIRST_EXT_DW_0_ENABLED = 1 << 17, 1426 MLX5_FLEX_PARSER_GTPU_DW_0_ENABLED = 1 << 18, 1427 MLX5_FLEX_PARSER_GTPU_TEID_ENABLED = 1 << 19, 1428 }; 1429 1430 enum { 1431 MLX5_UCTX_CAP_RAW_TX = 1UL << 0, 1432 MLX5_UCTX_CAP_INTERNAL_DEV_RES = 1UL << 1, 1433 }; 1434 1435 #define MLX5_FC_BULK_SIZE_FACTOR 128 1436 1437 enum mlx5_fc_bulk_alloc_bitmask { 1438 MLX5_FC_BULK_128 = (1 << 0), 1439 MLX5_FC_BULK_256 = (1 << 1), 1440 MLX5_FC_BULK_512 = (1 << 2), 1441 MLX5_FC_BULK_1024 = (1 << 3), 1442 MLX5_FC_BULK_2048 = (1 << 4), 1443 MLX5_FC_BULK_4096 = (1 << 5), 1444 MLX5_FC_BULK_8192 = (1 << 6), 1445 MLX5_FC_BULK_16384 = (1 << 7), 1446 }; 1447 1448 #define MLX5_FC_BULK_NUM_FCS(fc_enum) (MLX5_FC_BULK_SIZE_FACTOR * (fc_enum)) 1449 1450 #define MLX5_FT_MAX_MULTIPATH_LEVEL 63 1451 1452 enum { 1453 MLX5_STEERING_FORMAT_CONNECTX_5 = 0, 1454 MLX5_STEERING_FORMAT_CONNECTX_6DX = 1, 1455 MLX5_STEERING_FORMAT_CONNECTX_7 = 2, 1456 }; 1457 1458 struct mlx5_ifc_cmd_hca_cap_bits { 1459 u8 reserved_at_0[0x10]; 1460 u8 shared_object_to_user_object_allowed[0x1]; 1461 u8 reserved_at_13[0xe]; 1462 u8 vhca_resource_manager[0x1]; 1463 1464 u8 hca_cap_2[0x1]; 1465 u8 create_lag_when_not_master_up[0x1]; 1466 u8 dtor[0x1]; 1467 u8 event_on_vhca_state_teardown_request[0x1]; 1468 u8 event_on_vhca_state_in_use[0x1]; 1469 u8 event_on_vhca_state_active[0x1]; 1470 u8 event_on_vhca_state_allocated[0x1]; 1471 u8 event_on_vhca_state_invalid[0x1]; 1472 u8 reserved_at_28[0x8]; 1473 u8 vhca_id[0x10]; 1474 1475 u8 reserved_at_40[0x40]; 1476 1477 u8 log_max_srq_sz[0x8]; 1478 u8 log_max_qp_sz[0x8]; 1479 u8 event_cap[0x1]; 1480 u8 reserved_at_91[0x2]; 1481 u8 isolate_vl_tc_new[0x1]; 1482 u8 reserved_at_94[0x4]; 1483 u8 prio_tag_required[0x1]; 1484 u8 reserved_at_99[0x2]; 1485 u8 log_max_qp[0x5]; 1486 1487 u8 reserved_at_a0[0x3]; 1488 u8 ece_support[0x1]; 1489 u8 reserved_at_a4[0x5]; 1490 u8 reg_c_preserve[0x1]; 1491 u8 reserved_at_aa[0x1]; 1492 u8 log_max_srq[0x5]; 1493 u8 reserved_at_b0[0x1]; 1494 u8 uplink_follow[0x1]; 1495 u8 ts_cqe_to_dest_cqn[0x1]; 1496 u8 reserved_at_b3[0x7]; 1497 u8 shampo[0x1]; 1498 u8 reserved_at_bb[0x5]; 1499 1500 u8 max_sgl_for_optimized_performance[0x8]; 1501 u8 log_max_cq_sz[0x8]; 1502 u8 relaxed_ordering_write_umr[0x1]; 1503 u8 relaxed_ordering_read_umr[0x1]; 1504 u8 reserved_at_d2[0x7]; 1505 u8 virtio_net_device_emualtion_manager[0x1]; 1506 u8 virtio_blk_device_emualtion_manager[0x1]; 1507 u8 log_max_cq[0x5]; 1508 1509 u8 log_max_eq_sz[0x8]; 1510 u8 relaxed_ordering_write[0x1]; 1511 u8 relaxed_ordering_read[0x1]; 1512 u8 log_max_mkey[0x6]; 1513 u8 reserved_at_f0[0x6]; 1514 u8 terminate_scatter_list_mkey[0x1]; 1515 u8 repeated_mkey[0x1]; 1516 u8 dump_fill_mkey[0x1]; 1517 u8 reserved_at_f9[0x2]; 1518 u8 fast_teardown[0x1]; 1519 u8 log_max_eq[0x4]; 1520 1521 u8 max_indirection[0x8]; 1522 u8 fixed_buffer_size[0x1]; 1523 u8 log_max_mrw_sz[0x7]; 1524 u8 force_teardown[0x1]; 1525 u8 reserved_at_111[0x1]; 1526 u8 log_max_bsf_list_size[0x6]; 1527 u8 umr_extended_translation_offset[0x1]; 1528 u8 null_mkey[0x1]; 1529 u8 log_max_klm_list_size[0x6]; 1530 1531 u8 reserved_at_120[0x2]; 1532 u8 qpc_extension[0x1]; 1533 u8 reserved_at_123[0x7]; 1534 u8 log_max_ra_req_dc[0x6]; 1535 u8 reserved_at_130[0x2]; 1536 u8 eth_wqe_too_small[0x1]; 1537 u8 reserved_at_133[0x6]; 1538 u8 vnic_env_cq_overrun[0x1]; 1539 u8 log_max_ra_res_dc[0x6]; 1540 1541 u8 reserved_at_140[0x5]; 1542 u8 release_all_pages[0x1]; 1543 u8 must_not_use[0x1]; 1544 u8 reserved_at_147[0x2]; 1545 u8 roce_accl[0x1]; 1546 u8 log_max_ra_req_qp[0x6]; 1547 u8 reserved_at_150[0xa]; 1548 u8 log_max_ra_res_qp[0x6]; 1549 1550 u8 end_pad[0x1]; 1551 u8 cc_query_allowed[0x1]; 1552 u8 cc_modify_allowed[0x1]; 1553 u8 start_pad[0x1]; 1554 u8 cache_line_128byte[0x1]; 1555 u8 reserved_at_165[0x4]; 1556 u8 rts2rts_qp_counters_set_id[0x1]; 1557 u8 reserved_at_16a[0x2]; 1558 u8 vnic_env_int_rq_oob[0x1]; 1559 u8 sbcam_reg[0x1]; 1560 u8 reserved_at_16e[0x1]; 1561 u8 qcam_reg[0x1]; 1562 u8 gid_table_size[0x10]; 1563 1564 u8 out_of_seq_cnt[0x1]; 1565 u8 vport_counters[0x1]; 1566 u8 retransmission_q_counters[0x1]; 1567 u8 debug[0x1]; 1568 u8 modify_rq_counter_set_id[0x1]; 1569 u8 rq_delay_drop[0x1]; 1570 u8 max_qp_cnt[0xa]; 1571 u8 pkey_table_size[0x10]; 1572 1573 u8 vport_group_manager[0x1]; 1574 u8 vhca_group_manager[0x1]; 1575 u8 ib_virt[0x1]; 1576 u8 eth_virt[0x1]; 1577 u8 vnic_env_queue_counters[0x1]; 1578 u8 ets[0x1]; 1579 u8 nic_flow_table[0x1]; 1580 u8 eswitch_manager[0x1]; 1581 u8 device_memory[0x1]; 1582 u8 mcam_reg[0x1]; 1583 u8 pcam_reg[0x1]; 1584 u8 local_ca_ack_delay[0x5]; 1585 u8 port_module_event[0x1]; 1586 u8 enhanced_error_q_counters[0x1]; 1587 u8 ports_check[0x1]; 1588 u8 reserved_at_1b3[0x1]; 1589 u8 disable_link_up[0x1]; 1590 u8 beacon_led[0x1]; 1591 u8 port_type[0x2]; 1592 u8 num_ports[0x8]; 1593 1594 u8 reserved_at_1c0[0x1]; 1595 u8 pps[0x1]; 1596 u8 pps_modify[0x1]; 1597 u8 log_max_msg[0x5]; 1598 u8 reserved_at_1c8[0x4]; 1599 u8 max_tc[0x4]; 1600 u8 temp_warn_event[0x1]; 1601 u8 dcbx[0x1]; 1602 u8 general_notification_event[0x1]; 1603 u8 reserved_at_1d3[0x2]; 1604 u8 fpga[0x1]; 1605 u8 rol_s[0x1]; 1606 u8 rol_g[0x1]; 1607 u8 reserved_at_1d8[0x1]; 1608 u8 wol_s[0x1]; 1609 u8 wol_g[0x1]; 1610 u8 wol_a[0x1]; 1611 u8 wol_b[0x1]; 1612 u8 wol_m[0x1]; 1613 u8 wol_u[0x1]; 1614 u8 wol_p[0x1]; 1615 1616 u8 stat_rate_support[0x10]; 1617 u8 reserved_at_1f0[0x1]; 1618 u8 pci_sync_for_fw_update_event[0x1]; 1619 u8 reserved_at_1f2[0x6]; 1620 u8 init2_lag_tx_port_affinity[0x1]; 1621 u8 reserved_at_1fa[0x3]; 1622 u8 cqe_version[0x4]; 1623 1624 u8 compact_address_vector[0x1]; 1625 u8 striding_rq[0x1]; 1626 u8 reserved_at_202[0x1]; 1627 u8 ipoib_enhanced_offloads[0x1]; 1628 u8 ipoib_basic_offloads[0x1]; 1629 u8 reserved_at_205[0x1]; 1630 u8 repeated_block_disabled[0x1]; 1631 u8 umr_modify_entity_size_disabled[0x1]; 1632 u8 umr_modify_atomic_disabled[0x1]; 1633 u8 umr_indirect_mkey_disabled[0x1]; 1634 u8 umr_fence[0x2]; 1635 u8 dc_req_scat_data_cqe[0x1]; 1636 u8 reserved_at_20d[0x2]; 1637 u8 drain_sigerr[0x1]; 1638 u8 cmdif_checksum[0x2]; 1639 u8 sigerr_cqe[0x1]; 1640 u8 reserved_at_213[0x1]; 1641 u8 wq_signature[0x1]; 1642 u8 sctr_data_cqe[0x1]; 1643 u8 reserved_at_216[0x1]; 1644 u8 sho[0x1]; 1645 u8 tph[0x1]; 1646 u8 rf[0x1]; 1647 u8 dct[0x1]; 1648 u8 qos[0x1]; 1649 u8 eth_net_offloads[0x1]; 1650 u8 roce[0x1]; 1651 u8 atomic[0x1]; 1652 u8 reserved_at_21f[0x1]; 1653 1654 u8 cq_oi[0x1]; 1655 u8 cq_resize[0x1]; 1656 u8 cq_moderation[0x1]; 1657 u8 reserved_at_223[0x3]; 1658 u8 cq_eq_remap[0x1]; 1659 u8 pg[0x1]; 1660 u8 block_lb_mc[0x1]; 1661 u8 reserved_at_229[0x1]; 1662 u8 scqe_break_moderation[0x1]; 1663 u8 cq_period_start_from_cqe[0x1]; 1664 u8 cd[0x1]; 1665 u8 reserved_at_22d[0x1]; 1666 u8 apm[0x1]; 1667 u8 vector_calc[0x1]; 1668 u8 umr_ptr_rlky[0x1]; 1669 u8 imaicl[0x1]; 1670 u8 qp_packet_based[0x1]; 1671 u8 reserved_at_233[0x3]; 1672 u8 qkv[0x1]; 1673 u8 pkv[0x1]; 1674 u8 set_deth_sqpn[0x1]; 1675 u8 reserved_at_239[0x3]; 1676 u8 xrc[0x1]; 1677 u8 ud[0x1]; 1678 u8 uc[0x1]; 1679 u8 rc[0x1]; 1680 1681 u8 uar_4k[0x1]; 1682 u8 reserved_at_241[0x9]; 1683 u8 uar_sz[0x6]; 1684 u8 port_selection_cap[0x1]; 1685 u8 reserved_at_248[0x1]; 1686 u8 umem_uid_0[0x1]; 1687 u8 reserved_at_250[0x5]; 1688 u8 log_pg_sz[0x8]; 1689 1690 u8 bf[0x1]; 1691 u8 driver_version[0x1]; 1692 u8 pad_tx_eth_packet[0x1]; 1693 u8 reserved_at_263[0x3]; 1694 u8 mkey_by_name[0x1]; 1695 u8 reserved_at_267[0x4]; 1696 1697 u8 log_bf_reg_size[0x5]; 1698 1699 u8 reserved_at_270[0x3]; 1700 u8 qp_error_syndrome[0x1]; 1701 u8 reserved_at_274[0x2]; 1702 u8 lag_dct[0x2]; 1703 u8 lag_tx_port_affinity[0x1]; 1704 u8 lag_native_fdb_selection[0x1]; 1705 u8 reserved_at_27a[0x1]; 1706 u8 lag_master[0x1]; 1707 u8 num_lag_ports[0x4]; 1708 1709 u8 reserved_at_280[0x10]; 1710 u8 max_wqe_sz_sq[0x10]; 1711 1712 u8 reserved_at_2a0[0x10]; 1713 u8 max_wqe_sz_rq[0x10]; 1714 1715 u8 max_flow_counter_31_16[0x10]; 1716 u8 max_wqe_sz_sq_dc[0x10]; 1717 1718 u8 reserved_at_2e0[0x7]; 1719 u8 max_qp_mcg[0x19]; 1720 1721 u8 reserved_at_300[0x10]; 1722 u8 flow_counter_bulk_alloc[0x8]; 1723 u8 log_max_mcg[0x8]; 1724 1725 u8 reserved_at_320[0x3]; 1726 u8 log_max_transport_domain[0x5]; 1727 u8 reserved_at_328[0x3]; 1728 u8 log_max_pd[0x5]; 1729 u8 reserved_at_330[0xb]; 1730 u8 log_max_xrcd[0x5]; 1731 1732 u8 nic_receive_steering_discard[0x1]; 1733 u8 receive_discard_vport_down[0x1]; 1734 u8 transmit_discard_vport_down[0x1]; 1735 u8 eq_overrun_count[0x1]; 1736 u8 reserved_at_344[0x1]; 1737 u8 invalid_command_count[0x1]; 1738 u8 quota_exceeded_count[0x1]; 1739 u8 reserved_at_347[0x1]; 1740 u8 log_max_flow_counter_bulk[0x8]; 1741 u8 max_flow_counter_15_0[0x10]; 1742 1743 1744 u8 reserved_at_360[0x3]; 1745 u8 log_max_rq[0x5]; 1746 u8 reserved_at_368[0x3]; 1747 u8 log_max_sq[0x5]; 1748 u8 reserved_at_370[0x3]; 1749 u8 log_max_tir[0x5]; 1750 u8 reserved_at_378[0x3]; 1751 u8 log_max_tis[0x5]; 1752 1753 u8 basic_cyclic_rcv_wqe[0x1]; 1754 u8 reserved_at_381[0x2]; 1755 u8 log_max_rmp[0x5]; 1756 u8 reserved_at_388[0x3]; 1757 u8 log_max_rqt[0x5]; 1758 u8 reserved_at_390[0x3]; 1759 u8 log_max_rqt_size[0x5]; 1760 u8 reserved_at_398[0x3]; 1761 u8 log_max_tis_per_sq[0x5]; 1762 1763 u8 ext_stride_num_range[0x1]; 1764 u8 roce_rw_supported[0x1]; 1765 u8 log_max_current_uc_list_wr_supported[0x1]; 1766 u8 log_max_stride_sz_rq[0x5]; 1767 u8 reserved_at_3a8[0x3]; 1768 u8 log_min_stride_sz_rq[0x5]; 1769 u8 reserved_at_3b0[0x3]; 1770 u8 log_max_stride_sz_sq[0x5]; 1771 u8 reserved_at_3b8[0x3]; 1772 u8 log_min_stride_sz_sq[0x5]; 1773 1774 u8 hairpin[0x1]; 1775 u8 reserved_at_3c1[0x2]; 1776 u8 log_max_hairpin_queues[0x5]; 1777 u8 reserved_at_3c8[0x3]; 1778 u8 log_max_hairpin_wq_data_sz[0x5]; 1779 u8 reserved_at_3d0[0x3]; 1780 u8 log_max_hairpin_num_packets[0x5]; 1781 u8 reserved_at_3d8[0x3]; 1782 u8 log_max_wq_sz[0x5]; 1783 1784 u8 nic_vport_change_event[0x1]; 1785 u8 disable_local_lb_uc[0x1]; 1786 u8 disable_local_lb_mc[0x1]; 1787 u8 log_min_hairpin_wq_data_sz[0x5]; 1788 u8 reserved_at_3e8[0x2]; 1789 u8 vhca_state[0x1]; 1790 u8 log_max_vlan_list[0x5]; 1791 u8 reserved_at_3f0[0x3]; 1792 u8 log_max_current_mc_list[0x5]; 1793 u8 reserved_at_3f8[0x3]; 1794 u8 log_max_current_uc_list[0x5]; 1795 1796 u8 general_obj_types[0x40]; 1797 1798 u8 sq_ts_format[0x2]; 1799 u8 rq_ts_format[0x2]; 1800 u8 steering_format_version[0x4]; 1801 u8 create_qp_start_hint[0x18]; 1802 1803 u8 reserved_at_460[0x1]; 1804 u8 ats[0x1]; 1805 u8 reserved_at_462[0x1]; 1806 u8 log_max_uctx[0x5]; 1807 u8 reserved_at_468[0x1]; 1808 u8 crypto[0x1]; 1809 u8 ipsec_offload[0x1]; 1810 u8 log_max_umem[0x5]; 1811 u8 max_num_eqs[0x10]; 1812 1813 u8 reserved_at_480[0x1]; 1814 u8 tls_tx[0x1]; 1815 u8 tls_rx[0x1]; 1816 u8 log_max_l2_table[0x5]; 1817 u8 reserved_at_488[0x8]; 1818 u8 log_uar_page_sz[0x10]; 1819 1820 u8 reserved_at_4a0[0x20]; 1821 u8 device_frequency_mhz[0x20]; 1822 u8 device_frequency_khz[0x20]; 1823 1824 u8 reserved_at_500[0x20]; 1825 u8 num_of_uars_per_page[0x20]; 1826 1827 u8 flex_parser_protocols[0x20]; 1828 1829 u8 max_geneve_tlv_options[0x8]; 1830 u8 reserved_at_568[0x3]; 1831 u8 max_geneve_tlv_option_data_len[0x5]; 1832 u8 reserved_at_570[0x9]; 1833 u8 adv_virtualization[0x1]; 1834 u8 reserved_at_57a[0x6]; 1835 1836 u8 reserved_at_580[0xb]; 1837 u8 log_max_dci_stream_channels[0x5]; 1838 u8 reserved_at_590[0x3]; 1839 u8 log_max_dci_errored_streams[0x5]; 1840 u8 reserved_at_598[0x8]; 1841 1842 u8 reserved_at_5a0[0x10]; 1843 u8 enhanced_cqe_compression[0x1]; 1844 u8 reserved_at_5b1[0x2]; 1845 u8 log_max_dek[0x5]; 1846 u8 reserved_at_5b8[0x4]; 1847 u8 mini_cqe_resp_stride_index[0x1]; 1848 u8 cqe_128_always[0x1]; 1849 u8 cqe_compression_128[0x1]; 1850 u8 cqe_compression[0x1]; 1851 1852 u8 cqe_compression_timeout[0x10]; 1853 u8 cqe_compression_max_num[0x10]; 1854 1855 u8 reserved_at_5e0[0x8]; 1856 u8 flex_parser_id_gtpu_dw_0[0x4]; 1857 u8 reserved_at_5ec[0x4]; 1858 u8 tag_matching[0x1]; 1859 u8 rndv_offload_rc[0x1]; 1860 u8 rndv_offload_dc[0x1]; 1861 u8 log_tag_matching_list_sz[0x5]; 1862 u8 reserved_at_5f8[0x3]; 1863 u8 log_max_xrq[0x5]; 1864 1865 u8 affiliate_nic_vport_criteria[0x8]; 1866 u8 native_port_num[0x8]; 1867 u8 num_vhca_ports[0x8]; 1868 u8 flex_parser_id_gtpu_teid[0x4]; 1869 u8 reserved_at_61c[0x2]; 1870 u8 sw_owner_id[0x1]; 1871 u8 reserved_at_61f[0x1]; 1872 1873 u8 max_num_of_monitor_counters[0x10]; 1874 u8 num_ppcnt_monitor_counters[0x10]; 1875 1876 u8 max_num_sf[0x10]; 1877 u8 num_q_monitor_counters[0x10]; 1878 1879 u8 reserved_at_660[0x20]; 1880 1881 u8 sf[0x1]; 1882 u8 sf_set_partition[0x1]; 1883 u8 reserved_at_682[0x1]; 1884 u8 log_max_sf[0x5]; 1885 u8 apu[0x1]; 1886 u8 reserved_at_689[0x4]; 1887 u8 migration[0x1]; 1888 u8 reserved_at_68e[0x2]; 1889 u8 log_min_sf_size[0x8]; 1890 u8 max_num_sf_partitions[0x8]; 1891 1892 u8 uctx_cap[0x20]; 1893 1894 u8 reserved_at_6c0[0x4]; 1895 u8 flex_parser_id_geneve_tlv_option_0[0x4]; 1896 u8 flex_parser_id_icmp_dw1[0x4]; 1897 u8 flex_parser_id_icmp_dw0[0x4]; 1898 u8 flex_parser_id_icmpv6_dw1[0x4]; 1899 u8 flex_parser_id_icmpv6_dw0[0x4]; 1900 u8 flex_parser_id_outer_first_mpls_over_gre[0x4]; 1901 u8 flex_parser_id_outer_first_mpls_over_udp_label[0x4]; 1902 1903 u8 max_num_match_definer[0x10]; 1904 u8 sf_base_id[0x10]; 1905 1906 u8 flex_parser_id_gtpu_dw_2[0x4]; 1907 u8 flex_parser_id_gtpu_first_ext_dw_0[0x4]; 1908 u8 num_total_dynamic_vf_msix[0x18]; 1909 u8 reserved_at_720[0x14]; 1910 u8 dynamic_msix_table_size[0xc]; 1911 u8 reserved_at_740[0xc]; 1912 u8 min_dynamic_vf_msix_table_size[0x4]; 1913 u8 reserved_at_750[0x4]; 1914 u8 max_dynamic_vf_msix_table_size[0xc]; 1915 1916 u8 reserved_at_760[0x20]; 1917 u8 vhca_tunnel_commands[0x40]; 1918 u8 match_definer_format_supported[0x40]; 1919 }; 1920 1921 struct mlx5_ifc_cmd_hca_cap_2_bits { 1922 u8 reserved_at_0[0x80]; 1923 1924 u8 migratable[0x1]; 1925 u8 reserved_at_81[0x1f]; 1926 1927 u8 max_reformat_insert_size[0x8]; 1928 u8 max_reformat_insert_offset[0x8]; 1929 u8 max_reformat_remove_size[0x8]; 1930 u8 max_reformat_remove_offset[0x8]; 1931 1932 u8 reserved_at_c0[0x8]; 1933 u8 migration_multi_load[0x1]; 1934 u8 migration_tracking_state[0x1]; 1935 u8 reserved_at_ca[0x16]; 1936 1937 u8 reserved_at_e0[0xc0]; 1938 1939 u8 flow_table_type_2_type[0x8]; 1940 u8 reserved_at_1a8[0x3]; 1941 u8 log_min_mkey_entity_size[0x5]; 1942 u8 reserved_at_1b0[0x10]; 1943 1944 u8 reserved_at_1c0[0x60]; 1945 1946 u8 reserved_at_220[0x1]; 1947 u8 sw_vhca_id_valid[0x1]; 1948 u8 sw_vhca_id[0xe]; 1949 u8 reserved_at_230[0x10]; 1950 1951 u8 reserved_at_240[0xb]; 1952 u8 ts_cqe_metadata_size2wqe_counter[0x5]; 1953 u8 reserved_at_250[0x10]; 1954 1955 u8 reserved_at_260[0x5a0]; 1956 }; 1957 1958 enum mlx5_ifc_flow_destination_type { 1959 MLX5_IFC_FLOW_DESTINATION_TYPE_VPORT = 0x0, 1960 MLX5_IFC_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1, 1961 MLX5_IFC_FLOW_DESTINATION_TYPE_TIR = 0x2, 1962 MLX5_IFC_FLOW_DESTINATION_TYPE_FLOW_SAMPLER = 0x6, 1963 MLX5_IFC_FLOW_DESTINATION_TYPE_UPLINK = 0x8, 1964 MLX5_IFC_FLOW_DESTINATION_TYPE_TABLE_TYPE = 0xA, 1965 }; 1966 1967 enum mlx5_flow_table_miss_action { 1968 MLX5_FLOW_TABLE_MISS_ACTION_DEF, 1969 MLX5_FLOW_TABLE_MISS_ACTION_FWD, 1970 MLX5_FLOW_TABLE_MISS_ACTION_SWITCH_DOMAIN, 1971 }; 1972 1973 struct mlx5_ifc_dest_format_struct_bits { 1974 u8 destination_type[0x8]; 1975 u8 destination_id[0x18]; 1976 1977 u8 destination_eswitch_owner_vhca_id_valid[0x1]; 1978 u8 packet_reformat[0x1]; 1979 u8 reserved_at_22[0x6]; 1980 u8 destination_table_type[0x8]; 1981 u8 destination_eswitch_owner_vhca_id[0x10]; 1982 }; 1983 1984 struct mlx5_ifc_flow_counter_list_bits { 1985 u8 flow_counter_id[0x20]; 1986 1987 u8 reserved_at_20[0x20]; 1988 }; 1989 1990 struct mlx5_ifc_extended_dest_format_bits { 1991 struct mlx5_ifc_dest_format_struct_bits destination_entry; 1992 1993 u8 packet_reformat_id[0x20]; 1994 1995 u8 reserved_at_60[0x20]; 1996 }; 1997 1998 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits { 1999 struct mlx5_ifc_extended_dest_format_bits extended_dest_format; 2000 struct mlx5_ifc_flow_counter_list_bits flow_counter_list; 2001 }; 2002 2003 struct mlx5_ifc_fte_match_param_bits { 2004 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers; 2005 2006 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters; 2007 2008 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers; 2009 2010 struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2; 2011 2012 struct mlx5_ifc_fte_match_set_misc3_bits misc_parameters_3; 2013 2014 struct mlx5_ifc_fte_match_set_misc4_bits misc_parameters_4; 2015 2016 struct mlx5_ifc_fte_match_set_misc5_bits misc_parameters_5; 2017 2018 u8 reserved_at_e00[0x200]; 2019 }; 2020 2021 enum { 2022 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0, 2023 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1, 2024 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2, 2025 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3, 2026 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4, 2027 }; 2028 2029 struct mlx5_ifc_rx_hash_field_select_bits { 2030 u8 l3_prot_type[0x1]; 2031 u8 l4_prot_type[0x1]; 2032 u8 selected_fields[0x1e]; 2033 }; 2034 2035 enum { 2036 MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0, 2037 MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1, 2038 }; 2039 2040 enum { 2041 MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0, 2042 MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1, 2043 }; 2044 2045 struct mlx5_ifc_wq_bits { 2046 u8 wq_type[0x4]; 2047 u8 wq_signature[0x1]; 2048 u8 end_padding_mode[0x2]; 2049 u8 cd_slave[0x1]; 2050 u8 reserved_at_8[0x18]; 2051 2052 u8 hds_skip_first_sge[0x1]; 2053 u8 log2_hds_buf_size[0x3]; 2054 u8 reserved_at_24[0x7]; 2055 u8 page_offset[0x5]; 2056 u8 lwm[0x10]; 2057 2058 u8 reserved_at_40[0x8]; 2059 u8 pd[0x18]; 2060 2061 u8 reserved_at_60[0x8]; 2062 u8 uar_page[0x18]; 2063 2064 u8 dbr_addr[0x40]; 2065 2066 u8 hw_counter[0x20]; 2067 2068 u8 sw_counter[0x20]; 2069 2070 u8 reserved_at_100[0xc]; 2071 u8 log_wq_stride[0x4]; 2072 u8 reserved_at_110[0x3]; 2073 u8 log_wq_pg_sz[0x5]; 2074 u8 reserved_at_118[0x3]; 2075 u8 log_wq_sz[0x5]; 2076 2077 u8 dbr_umem_valid[0x1]; 2078 u8 wq_umem_valid[0x1]; 2079 u8 reserved_at_122[0x1]; 2080 u8 log_hairpin_num_packets[0x5]; 2081 u8 reserved_at_128[0x3]; 2082 u8 log_hairpin_data_sz[0x5]; 2083 2084 u8 reserved_at_130[0x4]; 2085 u8 log_wqe_num_of_strides[0x4]; 2086 u8 two_byte_shift_en[0x1]; 2087 u8 reserved_at_139[0x4]; 2088 u8 log_wqe_stride_size[0x3]; 2089 2090 u8 reserved_at_140[0x80]; 2091 2092 u8 headers_mkey[0x20]; 2093 2094 u8 shampo_enable[0x1]; 2095 u8 reserved_at_1e1[0x4]; 2096 u8 log_reservation_size[0x3]; 2097 u8 reserved_at_1e8[0x5]; 2098 u8 log_max_num_of_packets_per_reservation[0x3]; 2099 u8 reserved_at_1f0[0x6]; 2100 u8 log_headers_entry_size[0x2]; 2101 u8 reserved_at_1f8[0x4]; 2102 u8 log_headers_buffer_entry_num[0x4]; 2103 2104 u8 reserved_at_200[0x400]; 2105 2106 struct mlx5_ifc_cmd_pas_bits pas[]; 2107 }; 2108 2109 struct mlx5_ifc_rq_num_bits { 2110 u8 reserved_at_0[0x8]; 2111 u8 rq_num[0x18]; 2112 }; 2113 2114 struct mlx5_ifc_mac_address_layout_bits { 2115 u8 reserved_at_0[0x10]; 2116 u8 mac_addr_47_32[0x10]; 2117 2118 u8 mac_addr_31_0[0x20]; 2119 }; 2120 2121 struct mlx5_ifc_vlan_layout_bits { 2122 u8 reserved_at_0[0x14]; 2123 u8 vlan[0x0c]; 2124 2125 u8 reserved_at_20[0x20]; 2126 }; 2127 2128 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits { 2129 u8 reserved_at_0[0xa0]; 2130 2131 u8 min_time_between_cnps[0x20]; 2132 2133 u8 reserved_at_c0[0x12]; 2134 u8 cnp_dscp[0x6]; 2135 u8 reserved_at_d8[0x4]; 2136 u8 cnp_prio_mode[0x1]; 2137 u8 cnp_802p_prio[0x3]; 2138 2139 u8 reserved_at_e0[0x720]; 2140 }; 2141 2142 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits { 2143 u8 reserved_at_0[0x60]; 2144 2145 u8 reserved_at_60[0x4]; 2146 u8 clamp_tgt_rate[0x1]; 2147 u8 reserved_at_65[0x3]; 2148 u8 clamp_tgt_rate_after_time_inc[0x1]; 2149 u8 reserved_at_69[0x17]; 2150 2151 u8 reserved_at_80[0x20]; 2152 2153 u8 rpg_time_reset[0x20]; 2154 2155 u8 rpg_byte_reset[0x20]; 2156 2157 u8 rpg_threshold[0x20]; 2158 2159 u8 rpg_max_rate[0x20]; 2160 2161 u8 rpg_ai_rate[0x20]; 2162 2163 u8 rpg_hai_rate[0x20]; 2164 2165 u8 rpg_gd[0x20]; 2166 2167 u8 rpg_min_dec_fac[0x20]; 2168 2169 u8 rpg_min_rate[0x20]; 2170 2171 u8 reserved_at_1c0[0xe0]; 2172 2173 u8 rate_to_set_on_first_cnp[0x20]; 2174 2175 u8 dce_tcp_g[0x20]; 2176 2177 u8 dce_tcp_rtt[0x20]; 2178 2179 u8 rate_reduce_monitor_period[0x20]; 2180 2181 u8 reserved_at_320[0x20]; 2182 2183 u8 initial_alpha_value[0x20]; 2184 2185 u8 reserved_at_360[0x4a0]; 2186 }; 2187 2188 struct mlx5_ifc_cong_control_r_roce_general_bits { 2189 u8 reserved_at_0[0x80]; 2190 2191 u8 reserved_at_80[0x10]; 2192 u8 rtt_resp_dscp_valid[0x1]; 2193 u8 reserved_at_91[0x9]; 2194 u8 rtt_resp_dscp[0x6]; 2195 2196 u8 reserved_at_a0[0x760]; 2197 }; 2198 2199 struct mlx5_ifc_cong_control_802_1qau_rp_bits { 2200 u8 reserved_at_0[0x80]; 2201 2202 u8 rppp_max_rps[0x20]; 2203 2204 u8 rpg_time_reset[0x20]; 2205 2206 u8 rpg_byte_reset[0x20]; 2207 2208 u8 rpg_threshold[0x20]; 2209 2210 u8 rpg_max_rate[0x20]; 2211 2212 u8 rpg_ai_rate[0x20]; 2213 2214 u8 rpg_hai_rate[0x20]; 2215 2216 u8 rpg_gd[0x20]; 2217 2218 u8 rpg_min_dec_fac[0x20]; 2219 2220 u8 rpg_min_rate[0x20]; 2221 2222 u8 reserved_at_1c0[0x640]; 2223 }; 2224 2225 enum { 2226 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1, 2227 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2, 2228 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4, 2229 }; 2230 2231 struct mlx5_ifc_resize_field_select_bits { 2232 u8 resize_field_select[0x20]; 2233 }; 2234 2235 struct mlx5_ifc_resource_dump_bits { 2236 u8 more_dump[0x1]; 2237 u8 inline_dump[0x1]; 2238 u8 reserved_at_2[0xa]; 2239 u8 seq_num[0x4]; 2240 u8 segment_type[0x10]; 2241 2242 u8 reserved_at_20[0x10]; 2243 u8 vhca_id[0x10]; 2244 2245 u8 index1[0x20]; 2246 2247 u8 index2[0x20]; 2248 2249 u8 num_of_obj1[0x10]; 2250 u8 num_of_obj2[0x10]; 2251 2252 u8 reserved_at_a0[0x20]; 2253 2254 u8 device_opaque[0x40]; 2255 2256 u8 mkey[0x20]; 2257 2258 u8 size[0x20]; 2259 2260 u8 address[0x40]; 2261 2262 u8 inline_data[52][0x20]; 2263 }; 2264 2265 struct mlx5_ifc_resource_dump_menu_record_bits { 2266 u8 reserved_at_0[0x4]; 2267 u8 num_of_obj2_supports_active[0x1]; 2268 u8 num_of_obj2_supports_all[0x1]; 2269 u8 must_have_num_of_obj2[0x1]; 2270 u8 support_num_of_obj2[0x1]; 2271 u8 num_of_obj1_supports_active[0x1]; 2272 u8 num_of_obj1_supports_all[0x1]; 2273 u8 must_have_num_of_obj1[0x1]; 2274 u8 support_num_of_obj1[0x1]; 2275 u8 must_have_index2[0x1]; 2276 u8 support_index2[0x1]; 2277 u8 must_have_index1[0x1]; 2278 u8 support_index1[0x1]; 2279 u8 segment_type[0x10]; 2280 2281 u8 segment_name[4][0x20]; 2282 2283 u8 index1_name[4][0x20]; 2284 2285 u8 index2_name[4][0x20]; 2286 }; 2287 2288 struct mlx5_ifc_resource_dump_segment_header_bits { 2289 u8 length_dw[0x10]; 2290 u8 segment_type[0x10]; 2291 }; 2292 2293 struct mlx5_ifc_resource_dump_command_segment_bits { 2294 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2295 2296 u8 segment_called[0x10]; 2297 u8 vhca_id[0x10]; 2298 2299 u8 index1[0x20]; 2300 2301 u8 index2[0x20]; 2302 2303 u8 num_of_obj1[0x10]; 2304 u8 num_of_obj2[0x10]; 2305 }; 2306 2307 struct mlx5_ifc_resource_dump_error_segment_bits { 2308 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2309 2310 u8 reserved_at_20[0x10]; 2311 u8 syndrome_id[0x10]; 2312 2313 u8 reserved_at_40[0x40]; 2314 2315 u8 error[8][0x20]; 2316 }; 2317 2318 struct mlx5_ifc_resource_dump_info_segment_bits { 2319 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2320 2321 u8 reserved_at_20[0x18]; 2322 u8 dump_version[0x8]; 2323 2324 u8 hw_version[0x20]; 2325 2326 u8 fw_version[0x20]; 2327 }; 2328 2329 struct mlx5_ifc_resource_dump_menu_segment_bits { 2330 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2331 2332 u8 reserved_at_20[0x10]; 2333 u8 num_of_records[0x10]; 2334 2335 struct mlx5_ifc_resource_dump_menu_record_bits record[]; 2336 }; 2337 2338 struct mlx5_ifc_resource_dump_resource_segment_bits { 2339 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2340 2341 u8 reserved_at_20[0x20]; 2342 2343 u8 index1[0x20]; 2344 2345 u8 index2[0x20]; 2346 2347 u8 payload[][0x20]; 2348 }; 2349 2350 struct mlx5_ifc_resource_dump_terminate_segment_bits { 2351 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2352 }; 2353 2354 struct mlx5_ifc_menu_resource_dump_response_bits { 2355 struct mlx5_ifc_resource_dump_info_segment_bits info; 2356 struct mlx5_ifc_resource_dump_command_segment_bits cmd; 2357 struct mlx5_ifc_resource_dump_menu_segment_bits menu; 2358 struct mlx5_ifc_resource_dump_terminate_segment_bits terminate; 2359 }; 2360 2361 enum { 2362 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1, 2363 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2, 2364 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4, 2365 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8, 2366 }; 2367 2368 struct mlx5_ifc_modify_field_select_bits { 2369 u8 modify_field_select[0x20]; 2370 }; 2371 2372 struct mlx5_ifc_field_select_r_roce_np_bits { 2373 u8 field_select_r_roce_np[0x20]; 2374 }; 2375 2376 struct mlx5_ifc_field_select_r_roce_rp_bits { 2377 u8 field_select_r_roce_rp[0x20]; 2378 }; 2379 2380 enum { 2381 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4, 2382 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8, 2383 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10, 2384 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20, 2385 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40, 2386 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80, 2387 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100, 2388 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200, 2389 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400, 2390 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800, 2391 }; 2392 2393 struct mlx5_ifc_field_select_802_1qau_rp_bits { 2394 u8 field_select_8021qaurp[0x20]; 2395 }; 2396 2397 struct mlx5_ifc_phys_layer_cntrs_bits { 2398 u8 time_since_last_clear_high[0x20]; 2399 2400 u8 time_since_last_clear_low[0x20]; 2401 2402 u8 symbol_errors_high[0x20]; 2403 2404 u8 symbol_errors_low[0x20]; 2405 2406 u8 sync_headers_errors_high[0x20]; 2407 2408 u8 sync_headers_errors_low[0x20]; 2409 2410 u8 edpl_bip_errors_lane0_high[0x20]; 2411 2412 u8 edpl_bip_errors_lane0_low[0x20]; 2413 2414 u8 edpl_bip_errors_lane1_high[0x20]; 2415 2416 u8 edpl_bip_errors_lane1_low[0x20]; 2417 2418 u8 edpl_bip_errors_lane2_high[0x20]; 2419 2420 u8 edpl_bip_errors_lane2_low[0x20]; 2421 2422 u8 edpl_bip_errors_lane3_high[0x20]; 2423 2424 u8 edpl_bip_errors_lane3_low[0x20]; 2425 2426 u8 fc_fec_corrected_blocks_lane0_high[0x20]; 2427 2428 u8 fc_fec_corrected_blocks_lane0_low[0x20]; 2429 2430 u8 fc_fec_corrected_blocks_lane1_high[0x20]; 2431 2432 u8 fc_fec_corrected_blocks_lane1_low[0x20]; 2433 2434 u8 fc_fec_corrected_blocks_lane2_high[0x20]; 2435 2436 u8 fc_fec_corrected_blocks_lane2_low[0x20]; 2437 2438 u8 fc_fec_corrected_blocks_lane3_high[0x20]; 2439 2440 u8 fc_fec_corrected_blocks_lane3_low[0x20]; 2441 2442 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20]; 2443 2444 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20]; 2445 2446 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20]; 2447 2448 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20]; 2449 2450 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20]; 2451 2452 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20]; 2453 2454 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20]; 2455 2456 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20]; 2457 2458 u8 rs_fec_corrected_blocks_high[0x20]; 2459 2460 u8 rs_fec_corrected_blocks_low[0x20]; 2461 2462 u8 rs_fec_uncorrectable_blocks_high[0x20]; 2463 2464 u8 rs_fec_uncorrectable_blocks_low[0x20]; 2465 2466 u8 rs_fec_no_errors_blocks_high[0x20]; 2467 2468 u8 rs_fec_no_errors_blocks_low[0x20]; 2469 2470 u8 rs_fec_single_error_blocks_high[0x20]; 2471 2472 u8 rs_fec_single_error_blocks_low[0x20]; 2473 2474 u8 rs_fec_corrected_symbols_total_high[0x20]; 2475 2476 u8 rs_fec_corrected_symbols_total_low[0x20]; 2477 2478 u8 rs_fec_corrected_symbols_lane0_high[0x20]; 2479 2480 u8 rs_fec_corrected_symbols_lane0_low[0x20]; 2481 2482 u8 rs_fec_corrected_symbols_lane1_high[0x20]; 2483 2484 u8 rs_fec_corrected_symbols_lane1_low[0x20]; 2485 2486 u8 rs_fec_corrected_symbols_lane2_high[0x20]; 2487 2488 u8 rs_fec_corrected_symbols_lane2_low[0x20]; 2489 2490 u8 rs_fec_corrected_symbols_lane3_high[0x20]; 2491 2492 u8 rs_fec_corrected_symbols_lane3_low[0x20]; 2493 2494 u8 link_down_events[0x20]; 2495 2496 u8 successful_recovery_events[0x20]; 2497 2498 u8 reserved_at_640[0x180]; 2499 }; 2500 2501 struct mlx5_ifc_phys_layer_statistical_cntrs_bits { 2502 u8 time_since_last_clear_high[0x20]; 2503 2504 u8 time_since_last_clear_low[0x20]; 2505 2506 u8 phy_received_bits_high[0x20]; 2507 2508 u8 phy_received_bits_low[0x20]; 2509 2510 u8 phy_symbol_errors_high[0x20]; 2511 2512 u8 phy_symbol_errors_low[0x20]; 2513 2514 u8 phy_corrected_bits_high[0x20]; 2515 2516 u8 phy_corrected_bits_low[0x20]; 2517 2518 u8 phy_corrected_bits_lane0_high[0x20]; 2519 2520 u8 phy_corrected_bits_lane0_low[0x20]; 2521 2522 u8 phy_corrected_bits_lane1_high[0x20]; 2523 2524 u8 phy_corrected_bits_lane1_low[0x20]; 2525 2526 u8 phy_corrected_bits_lane2_high[0x20]; 2527 2528 u8 phy_corrected_bits_lane2_low[0x20]; 2529 2530 u8 phy_corrected_bits_lane3_high[0x20]; 2531 2532 u8 phy_corrected_bits_lane3_low[0x20]; 2533 2534 u8 reserved_at_200[0x5c0]; 2535 }; 2536 2537 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits { 2538 u8 symbol_error_counter[0x10]; 2539 2540 u8 link_error_recovery_counter[0x8]; 2541 2542 u8 link_downed_counter[0x8]; 2543 2544 u8 port_rcv_errors[0x10]; 2545 2546 u8 port_rcv_remote_physical_errors[0x10]; 2547 2548 u8 port_rcv_switch_relay_errors[0x10]; 2549 2550 u8 port_xmit_discards[0x10]; 2551 2552 u8 port_xmit_constraint_errors[0x8]; 2553 2554 u8 port_rcv_constraint_errors[0x8]; 2555 2556 u8 reserved_at_70[0x8]; 2557 2558 u8 link_overrun_errors[0x8]; 2559 2560 u8 reserved_at_80[0x10]; 2561 2562 u8 vl_15_dropped[0x10]; 2563 2564 u8 reserved_at_a0[0x80]; 2565 2566 u8 port_xmit_wait[0x20]; 2567 }; 2568 2569 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits { 2570 u8 transmit_queue_high[0x20]; 2571 2572 u8 transmit_queue_low[0x20]; 2573 2574 u8 no_buffer_discard_uc_high[0x20]; 2575 2576 u8 no_buffer_discard_uc_low[0x20]; 2577 2578 u8 reserved_at_80[0x740]; 2579 }; 2580 2581 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits { 2582 u8 wred_discard_high[0x20]; 2583 2584 u8 wred_discard_low[0x20]; 2585 2586 u8 ecn_marked_tc_high[0x20]; 2587 2588 u8 ecn_marked_tc_low[0x20]; 2589 2590 u8 reserved_at_80[0x740]; 2591 }; 2592 2593 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits { 2594 u8 rx_octets_high[0x20]; 2595 2596 u8 rx_octets_low[0x20]; 2597 2598 u8 reserved_at_40[0xc0]; 2599 2600 u8 rx_frames_high[0x20]; 2601 2602 u8 rx_frames_low[0x20]; 2603 2604 u8 tx_octets_high[0x20]; 2605 2606 u8 tx_octets_low[0x20]; 2607 2608 u8 reserved_at_180[0xc0]; 2609 2610 u8 tx_frames_high[0x20]; 2611 2612 u8 tx_frames_low[0x20]; 2613 2614 u8 rx_pause_high[0x20]; 2615 2616 u8 rx_pause_low[0x20]; 2617 2618 u8 rx_pause_duration_high[0x20]; 2619 2620 u8 rx_pause_duration_low[0x20]; 2621 2622 u8 tx_pause_high[0x20]; 2623 2624 u8 tx_pause_low[0x20]; 2625 2626 u8 tx_pause_duration_high[0x20]; 2627 2628 u8 tx_pause_duration_low[0x20]; 2629 2630 u8 rx_pause_transition_high[0x20]; 2631 2632 u8 rx_pause_transition_low[0x20]; 2633 2634 u8 rx_discards_high[0x20]; 2635 2636 u8 rx_discards_low[0x20]; 2637 2638 u8 device_stall_minor_watermark_cnt_high[0x20]; 2639 2640 u8 device_stall_minor_watermark_cnt_low[0x20]; 2641 2642 u8 device_stall_critical_watermark_cnt_high[0x20]; 2643 2644 u8 device_stall_critical_watermark_cnt_low[0x20]; 2645 2646 u8 reserved_at_480[0x340]; 2647 }; 2648 2649 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits { 2650 u8 port_transmit_wait_high[0x20]; 2651 2652 u8 port_transmit_wait_low[0x20]; 2653 2654 u8 reserved_at_40[0x100]; 2655 2656 u8 rx_buffer_almost_full_high[0x20]; 2657 2658 u8 rx_buffer_almost_full_low[0x20]; 2659 2660 u8 rx_buffer_full_high[0x20]; 2661 2662 u8 rx_buffer_full_low[0x20]; 2663 2664 u8 rx_icrc_encapsulated_high[0x20]; 2665 2666 u8 rx_icrc_encapsulated_low[0x20]; 2667 2668 u8 reserved_at_200[0x5c0]; 2669 }; 2670 2671 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits { 2672 u8 dot3stats_alignment_errors_high[0x20]; 2673 2674 u8 dot3stats_alignment_errors_low[0x20]; 2675 2676 u8 dot3stats_fcs_errors_high[0x20]; 2677 2678 u8 dot3stats_fcs_errors_low[0x20]; 2679 2680 u8 dot3stats_single_collision_frames_high[0x20]; 2681 2682 u8 dot3stats_single_collision_frames_low[0x20]; 2683 2684 u8 dot3stats_multiple_collision_frames_high[0x20]; 2685 2686 u8 dot3stats_multiple_collision_frames_low[0x20]; 2687 2688 u8 dot3stats_sqe_test_errors_high[0x20]; 2689 2690 u8 dot3stats_sqe_test_errors_low[0x20]; 2691 2692 u8 dot3stats_deferred_transmissions_high[0x20]; 2693 2694 u8 dot3stats_deferred_transmissions_low[0x20]; 2695 2696 u8 dot3stats_late_collisions_high[0x20]; 2697 2698 u8 dot3stats_late_collisions_low[0x20]; 2699 2700 u8 dot3stats_excessive_collisions_high[0x20]; 2701 2702 u8 dot3stats_excessive_collisions_low[0x20]; 2703 2704 u8 dot3stats_internal_mac_transmit_errors_high[0x20]; 2705 2706 u8 dot3stats_internal_mac_transmit_errors_low[0x20]; 2707 2708 u8 dot3stats_carrier_sense_errors_high[0x20]; 2709 2710 u8 dot3stats_carrier_sense_errors_low[0x20]; 2711 2712 u8 dot3stats_frame_too_longs_high[0x20]; 2713 2714 u8 dot3stats_frame_too_longs_low[0x20]; 2715 2716 u8 dot3stats_internal_mac_receive_errors_high[0x20]; 2717 2718 u8 dot3stats_internal_mac_receive_errors_low[0x20]; 2719 2720 u8 dot3stats_symbol_errors_high[0x20]; 2721 2722 u8 dot3stats_symbol_errors_low[0x20]; 2723 2724 u8 dot3control_in_unknown_opcodes_high[0x20]; 2725 2726 u8 dot3control_in_unknown_opcodes_low[0x20]; 2727 2728 u8 dot3in_pause_frames_high[0x20]; 2729 2730 u8 dot3in_pause_frames_low[0x20]; 2731 2732 u8 dot3out_pause_frames_high[0x20]; 2733 2734 u8 dot3out_pause_frames_low[0x20]; 2735 2736 u8 reserved_at_400[0x3c0]; 2737 }; 2738 2739 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits { 2740 u8 ether_stats_drop_events_high[0x20]; 2741 2742 u8 ether_stats_drop_events_low[0x20]; 2743 2744 u8 ether_stats_octets_high[0x20]; 2745 2746 u8 ether_stats_octets_low[0x20]; 2747 2748 u8 ether_stats_pkts_high[0x20]; 2749 2750 u8 ether_stats_pkts_low[0x20]; 2751 2752 u8 ether_stats_broadcast_pkts_high[0x20]; 2753 2754 u8 ether_stats_broadcast_pkts_low[0x20]; 2755 2756 u8 ether_stats_multicast_pkts_high[0x20]; 2757 2758 u8 ether_stats_multicast_pkts_low[0x20]; 2759 2760 u8 ether_stats_crc_align_errors_high[0x20]; 2761 2762 u8 ether_stats_crc_align_errors_low[0x20]; 2763 2764 u8 ether_stats_undersize_pkts_high[0x20]; 2765 2766 u8 ether_stats_undersize_pkts_low[0x20]; 2767 2768 u8 ether_stats_oversize_pkts_high[0x20]; 2769 2770 u8 ether_stats_oversize_pkts_low[0x20]; 2771 2772 u8 ether_stats_fragments_high[0x20]; 2773 2774 u8 ether_stats_fragments_low[0x20]; 2775 2776 u8 ether_stats_jabbers_high[0x20]; 2777 2778 u8 ether_stats_jabbers_low[0x20]; 2779 2780 u8 ether_stats_collisions_high[0x20]; 2781 2782 u8 ether_stats_collisions_low[0x20]; 2783 2784 u8 ether_stats_pkts64octets_high[0x20]; 2785 2786 u8 ether_stats_pkts64octets_low[0x20]; 2787 2788 u8 ether_stats_pkts65to127octets_high[0x20]; 2789 2790 u8 ether_stats_pkts65to127octets_low[0x20]; 2791 2792 u8 ether_stats_pkts128to255octets_high[0x20]; 2793 2794 u8 ether_stats_pkts128to255octets_low[0x20]; 2795 2796 u8 ether_stats_pkts256to511octets_high[0x20]; 2797 2798 u8 ether_stats_pkts256to511octets_low[0x20]; 2799 2800 u8 ether_stats_pkts512to1023octets_high[0x20]; 2801 2802 u8 ether_stats_pkts512to1023octets_low[0x20]; 2803 2804 u8 ether_stats_pkts1024to1518octets_high[0x20]; 2805 2806 u8 ether_stats_pkts1024to1518octets_low[0x20]; 2807 2808 u8 ether_stats_pkts1519to2047octets_high[0x20]; 2809 2810 u8 ether_stats_pkts1519to2047octets_low[0x20]; 2811 2812 u8 ether_stats_pkts2048to4095octets_high[0x20]; 2813 2814 u8 ether_stats_pkts2048to4095octets_low[0x20]; 2815 2816 u8 ether_stats_pkts4096to8191octets_high[0x20]; 2817 2818 u8 ether_stats_pkts4096to8191octets_low[0x20]; 2819 2820 u8 ether_stats_pkts8192to10239octets_high[0x20]; 2821 2822 u8 ether_stats_pkts8192to10239octets_low[0x20]; 2823 2824 u8 reserved_at_540[0x280]; 2825 }; 2826 2827 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits { 2828 u8 if_in_octets_high[0x20]; 2829 2830 u8 if_in_octets_low[0x20]; 2831 2832 u8 if_in_ucast_pkts_high[0x20]; 2833 2834 u8 if_in_ucast_pkts_low[0x20]; 2835 2836 u8 if_in_discards_high[0x20]; 2837 2838 u8 if_in_discards_low[0x20]; 2839 2840 u8 if_in_errors_high[0x20]; 2841 2842 u8 if_in_errors_low[0x20]; 2843 2844 u8 if_in_unknown_protos_high[0x20]; 2845 2846 u8 if_in_unknown_protos_low[0x20]; 2847 2848 u8 if_out_octets_high[0x20]; 2849 2850 u8 if_out_octets_low[0x20]; 2851 2852 u8 if_out_ucast_pkts_high[0x20]; 2853 2854 u8 if_out_ucast_pkts_low[0x20]; 2855 2856 u8 if_out_discards_high[0x20]; 2857 2858 u8 if_out_discards_low[0x20]; 2859 2860 u8 if_out_errors_high[0x20]; 2861 2862 u8 if_out_errors_low[0x20]; 2863 2864 u8 if_in_multicast_pkts_high[0x20]; 2865 2866 u8 if_in_multicast_pkts_low[0x20]; 2867 2868 u8 if_in_broadcast_pkts_high[0x20]; 2869 2870 u8 if_in_broadcast_pkts_low[0x20]; 2871 2872 u8 if_out_multicast_pkts_high[0x20]; 2873 2874 u8 if_out_multicast_pkts_low[0x20]; 2875 2876 u8 if_out_broadcast_pkts_high[0x20]; 2877 2878 u8 if_out_broadcast_pkts_low[0x20]; 2879 2880 u8 reserved_at_340[0x480]; 2881 }; 2882 2883 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits { 2884 u8 a_frames_transmitted_ok_high[0x20]; 2885 2886 u8 a_frames_transmitted_ok_low[0x20]; 2887 2888 u8 a_frames_received_ok_high[0x20]; 2889 2890 u8 a_frames_received_ok_low[0x20]; 2891 2892 u8 a_frame_check_sequence_errors_high[0x20]; 2893 2894 u8 a_frame_check_sequence_errors_low[0x20]; 2895 2896 u8 a_alignment_errors_high[0x20]; 2897 2898 u8 a_alignment_errors_low[0x20]; 2899 2900 u8 a_octets_transmitted_ok_high[0x20]; 2901 2902 u8 a_octets_transmitted_ok_low[0x20]; 2903 2904 u8 a_octets_received_ok_high[0x20]; 2905 2906 u8 a_octets_received_ok_low[0x20]; 2907 2908 u8 a_multicast_frames_xmitted_ok_high[0x20]; 2909 2910 u8 a_multicast_frames_xmitted_ok_low[0x20]; 2911 2912 u8 a_broadcast_frames_xmitted_ok_high[0x20]; 2913 2914 u8 a_broadcast_frames_xmitted_ok_low[0x20]; 2915 2916 u8 a_multicast_frames_received_ok_high[0x20]; 2917 2918 u8 a_multicast_frames_received_ok_low[0x20]; 2919 2920 u8 a_broadcast_frames_received_ok_high[0x20]; 2921 2922 u8 a_broadcast_frames_received_ok_low[0x20]; 2923 2924 u8 a_in_range_length_errors_high[0x20]; 2925 2926 u8 a_in_range_length_errors_low[0x20]; 2927 2928 u8 a_out_of_range_length_field_high[0x20]; 2929 2930 u8 a_out_of_range_length_field_low[0x20]; 2931 2932 u8 a_frame_too_long_errors_high[0x20]; 2933 2934 u8 a_frame_too_long_errors_low[0x20]; 2935 2936 u8 a_symbol_error_during_carrier_high[0x20]; 2937 2938 u8 a_symbol_error_during_carrier_low[0x20]; 2939 2940 u8 a_mac_control_frames_transmitted_high[0x20]; 2941 2942 u8 a_mac_control_frames_transmitted_low[0x20]; 2943 2944 u8 a_mac_control_frames_received_high[0x20]; 2945 2946 u8 a_mac_control_frames_received_low[0x20]; 2947 2948 u8 a_unsupported_opcodes_received_high[0x20]; 2949 2950 u8 a_unsupported_opcodes_received_low[0x20]; 2951 2952 u8 a_pause_mac_ctrl_frames_received_high[0x20]; 2953 2954 u8 a_pause_mac_ctrl_frames_received_low[0x20]; 2955 2956 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20]; 2957 2958 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20]; 2959 2960 u8 reserved_at_4c0[0x300]; 2961 }; 2962 2963 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits { 2964 u8 life_time_counter_high[0x20]; 2965 2966 u8 life_time_counter_low[0x20]; 2967 2968 u8 rx_errors[0x20]; 2969 2970 u8 tx_errors[0x20]; 2971 2972 u8 l0_to_recovery_eieos[0x20]; 2973 2974 u8 l0_to_recovery_ts[0x20]; 2975 2976 u8 l0_to_recovery_framing[0x20]; 2977 2978 u8 l0_to_recovery_retrain[0x20]; 2979 2980 u8 crc_error_dllp[0x20]; 2981 2982 u8 crc_error_tlp[0x20]; 2983 2984 u8 tx_overflow_buffer_pkt_high[0x20]; 2985 2986 u8 tx_overflow_buffer_pkt_low[0x20]; 2987 2988 u8 outbound_stalled_reads[0x20]; 2989 2990 u8 outbound_stalled_writes[0x20]; 2991 2992 u8 outbound_stalled_reads_events[0x20]; 2993 2994 u8 outbound_stalled_writes_events[0x20]; 2995 2996 u8 reserved_at_200[0x5c0]; 2997 }; 2998 2999 struct mlx5_ifc_cmd_inter_comp_event_bits { 3000 u8 command_completion_vector[0x20]; 3001 3002 u8 reserved_at_20[0xc0]; 3003 }; 3004 3005 struct mlx5_ifc_stall_vl_event_bits { 3006 u8 reserved_at_0[0x18]; 3007 u8 port_num[0x1]; 3008 u8 reserved_at_19[0x3]; 3009 u8 vl[0x4]; 3010 3011 u8 reserved_at_20[0xa0]; 3012 }; 3013 3014 struct mlx5_ifc_db_bf_congestion_event_bits { 3015 u8 event_subtype[0x8]; 3016 u8 reserved_at_8[0x8]; 3017 u8 congestion_level[0x8]; 3018 u8 reserved_at_18[0x8]; 3019 3020 u8 reserved_at_20[0xa0]; 3021 }; 3022 3023 struct mlx5_ifc_gpio_event_bits { 3024 u8 reserved_at_0[0x60]; 3025 3026 u8 gpio_event_hi[0x20]; 3027 3028 u8 gpio_event_lo[0x20]; 3029 3030 u8 reserved_at_a0[0x40]; 3031 }; 3032 3033 struct mlx5_ifc_port_state_change_event_bits { 3034 u8 reserved_at_0[0x40]; 3035 3036 u8 port_num[0x4]; 3037 u8 reserved_at_44[0x1c]; 3038 3039 u8 reserved_at_60[0x80]; 3040 }; 3041 3042 struct mlx5_ifc_dropped_packet_logged_bits { 3043 u8 reserved_at_0[0xe0]; 3044 }; 3045 3046 struct mlx5_ifc_default_timeout_bits { 3047 u8 to_multiplier[0x3]; 3048 u8 reserved_at_3[0x9]; 3049 u8 to_value[0x14]; 3050 }; 3051 3052 struct mlx5_ifc_dtor_reg_bits { 3053 u8 reserved_at_0[0x20]; 3054 3055 struct mlx5_ifc_default_timeout_bits pcie_toggle_to; 3056 3057 u8 reserved_at_40[0x60]; 3058 3059 struct mlx5_ifc_default_timeout_bits health_poll_to; 3060 3061 struct mlx5_ifc_default_timeout_bits full_crdump_to; 3062 3063 struct mlx5_ifc_default_timeout_bits fw_reset_to; 3064 3065 struct mlx5_ifc_default_timeout_bits flush_on_err_to; 3066 3067 struct mlx5_ifc_default_timeout_bits pci_sync_update_to; 3068 3069 struct mlx5_ifc_default_timeout_bits tear_down_to; 3070 3071 struct mlx5_ifc_default_timeout_bits fsm_reactivate_to; 3072 3073 struct mlx5_ifc_default_timeout_bits reclaim_pages_to; 3074 3075 struct mlx5_ifc_default_timeout_bits reclaim_vfs_pages_to; 3076 3077 u8 reserved_at_1c0[0x40]; 3078 }; 3079 3080 enum { 3081 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1, 3082 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2, 3083 }; 3084 3085 struct mlx5_ifc_cq_error_bits { 3086 u8 reserved_at_0[0x8]; 3087 u8 cqn[0x18]; 3088 3089 u8 reserved_at_20[0x20]; 3090 3091 u8 reserved_at_40[0x18]; 3092 u8 syndrome[0x8]; 3093 3094 u8 reserved_at_60[0x80]; 3095 }; 3096 3097 struct mlx5_ifc_rdma_page_fault_event_bits { 3098 u8 bytes_committed[0x20]; 3099 3100 u8 r_key[0x20]; 3101 3102 u8 reserved_at_40[0x10]; 3103 u8 packet_len[0x10]; 3104 3105 u8 rdma_op_len[0x20]; 3106 3107 u8 rdma_va[0x40]; 3108 3109 u8 reserved_at_c0[0x5]; 3110 u8 rdma[0x1]; 3111 u8 write[0x1]; 3112 u8 requestor[0x1]; 3113 u8 qp_number[0x18]; 3114 }; 3115 3116 struct mlx5_ifc_wqe_associated_page_fault_event_bits { 3117 u8 bytes_committed[0x20]; 3118 3119 u8 reserved_at_20[0x10]; 3120 u8 wqe_index[0x10]; 3121 3122 u8 reserved_at_40[0x10]; 3123 u8 len[0x10]; 3124 3125 u8 reserved_at_60[0x60]; 3126 3127 u8 reserved_at_c0[0x5]; 3128 u8 rdma[0x1]; 3129 u8 write_read[0x1]; 3130 u8 requestor[0x1]; 3131 u8 qpn[0x18]; 3132 }; 3133 3134 struct mlx5_ifc_qp_events_bits { 3135 u8 reserved_at_0[0xa0]; 3136 3137 u8 type[0x8]; 3138 u8 reserved_at_a8[0x18]; 3139 3140 u8 reserved_at_c0[0x8]; 3141 u8 qpn_rqn_sqn[0x18]; 3142 }; 3143 3144 struct mlx5_ifc_dct_events_bits { 3145 u8 reserved_at_0[0xc0]; 3146 3147 u8 reserved_at_c0[0x8]; 3148 u8 dct_number[0x18]; 3149 }; 3150 3151 struct mlx5_ifc_comp_event_bits { 3152 u8 reserved_at_0[0xc0]; 3153 3154 u8 reserved_at_c0[0x8]; 3155 u8 cq_number[0x18]; 3156 }; 3157 3158 enum { 3159 MLX5_QPC_STATE_RST = 0x0, 3160 MLX5_QPC_STATE_INIT = 0x1, 3161 MLX5_QPC_STATE_RTR = 0x2, 3162 MLX5_QPC_STATE_RTS = 0x3, 3163 MLX5_QPC_STATE_SQER = 0x4, 3164 MLX5_QPC_STATE_ERR = 0x6, 3165 MLX5_QPC_STATE_SQD = 0x7, 3166 MLX5_QPC_STATE_SUSPENDED = 0x9, 3167 }; 3168 3169 enum { 3170 MLX5_QPC_ST_RC = 0x0, 3171 MLX5_QPC_ST_UC = 0x1, 3172 MLX5_QPC_ST_UD = 0x2, 3173 MLX5_QPC_ST_XRC = 0x3, 3174 MLX5_QPC_ST_DCI = 0x5, 3175 MLX5_QPC_ST_QP0 = 0x7, 3176 MLX5_QPC_ST_QP1 = 0x8, 3177 MLX5_QPC_ST_RAW_DATAGRAM = 0x9, 3178 MLX5_QPC_ST_REG_UMR = 0xc, 3179 }; 3180 3181 enum { 3182 MLX5_QPC_PM_STATE_ARMED = 0x0, 3183 MLX5_QPC_PM_STATE_REARM = 0x1, 3184 MLX5_QPC_PM_STATE_RESERVED = 0x2, 3185 MLX5_QPC_PM_STATE_MIGRATED = 0x3, 3186 }; 3187 3188 enum { 3189 MLX5_QPC_OFFLOAD_TYPE_RNDV = 0x1, 3190 }; 3191 3192 enum { 3193 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0, 3194 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1, 3195 }; 3196 3197 enum { 3198 MLX5_QPC_MTU_256_BYTES = 0x1, 3199 MLX5_QPC_MTU_512_BYTES = 0x2, 3200 MLX5_QPC_MTU_1K_BYTES = 0x3, 3201 MLX5_QPC_MTU_2K_BYTES = 0x4, 3202 MLX5_QPC_MTU_4K_BYTES = 0x5, 3203 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7, 3204 }; 3205 3206 enum { 3207 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1, 3208 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2, 3209 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3, 3210 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4, 3211 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5, 3212 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6, 3213 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7, 3214 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8, 3215 }; 3216 3217 enum { 3218 MLX5_QPC_CS_REQ_DISABLE = 0x0, 3219 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11, 3220 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22, 3221 }; 3222 3223 enum { 3224 MLX5_QPC_CS_RES_DISABLE = 0x0, 3225 MLX5_QPC_CS_RES_UP_TO_32B = 0x1, 3226 MLX5_QPC_CS_RES_UP_TO_64B = 0x2, 3227 }; 3228 3229 enum { 3230 MLX5_TIMESTAMP_FORMAT_FREE_RUNNING = 0x0, 3231 MLX5_TIMESTAMP_FORMAT_DEFAULT = 0x1, 3232 MLX5_TIMESTAMP_FORMAT_REAL_TIME = 0x2, 3233 }; 3234 3235 struct mlx5_ifc_qpc_bits { 3236 u8 state[0x4]; 3237 u8 lag_tx_port_affinity[0x4]; 3238 u8 st[0x8]; 3239 u8 reserved_at_10[0x2]; 3240 u8 isolate_vl_tc[0x1]; 3241 u8 pm_state[0x2]; 3242 u8 reserved_at_15[0x1]; 3243 u8 req_e2e_credit_mode[0x2]; 3244 u8 offload_type[0x4]; 3245 u8 end_padding_mode[0x2]; 3246 u8 reserved_at_1e[0x2]; 3247 3248 u8 wq_signature[0x1]; 3249 u8 block_lb_mc[0x1]; 3250 u8 atomic_like_write_en[0x1]; 3251 u8 latency_sensitive[0x1]; 3252 u8 reserved_at_24[0x1]; 3253 u8 drain_sigerr[0x1]; 3254 u8 reserved_at_26[0x2]; 3255 u8 pd[0x18]; 3256 3257 u8 mtu[0x3]; 3258 u8 log_msg_max[0x5]; 3259 u8 reserved_at_48[0x1]; 3260 u8 log_rq_size[0x4]; 3261 u8 log_rq_stride[0x3]; 3262 u8 no_sq[0x1]; 3263 u8 log_sq_size[0x4]; 3264 u8 reserved_at_55[0x3]; 3265 u8 ts_format[0x2]; 3266 u8 reserved_at_5a[0x1]; 3267 u8 rlky[0x1]; 3268 u8 ulp_stateless_offload_mode[0x4]; 3269 3270 u8 counter_set_id[0x8]; 3271 u8 uar_page[0x18]; 3272 3273 u8 reserved_at_80[0x8]; 3274 u8 user_index[0x18]; 3275 3276 u8 reserved_at_a0[0x3]; 3277 u8 log_page_size[0x5]; 3278 u8 remote_qpn[0x18]; 3279 3280 struct mlx5_ifc_ads_bits primary_address_path; 3281 3282 struct mlx5_ifc_ads_bits secondary_address_path; 3283 3284 u8 log_ack_req_freq[0x4]; 3285 u8 reserved_at_384[0x4]; 3286 u8 log_sra_max[0x3]; 3287 u8 reserved_at_38b[0x2]; 3288 u8 retry_count[0x3]; 3289 u8 rnr_retry[0x3]; 3290 u8 reserved_at_393[0x1]; 3291 u8 fre[0x1]; 3292 u8 cur_rnr_retry[0x3]; 3293 u8 cur_retry_count[0x3]; 3294 u8 reserved_at_39b[0x5]; 3295 3296 u8 reserved_at_3a0[0x20]; 3297 3298 u8 reserved_at_3c0[0x8]; 3299 u8 next_send_psn[0x18]; 3300 3301 u8 reserved_at_3e0[0x3]; 3302 u8 log_num_dci_stream_channels[0x5]; 3303 u8 cqn_snd[0x18]; 3304 3305 u8 reserved_at_400[0x3]; 3306 u8 log_num_dci_errored_streams[0x5]; 3307 u8 deth_sqpn[0x18]; 3308 3309 u8 reserved_at_420[0x20]; 3310 3311 u8 reserved_at_440[0x8]; 3312 u8 last_acked_psn[0x18]; 3313 3314 u8 reserved_at_460[0x8]; 3315 u8 ssn[0x18]; 3316 3317 u8 reserved_at_480[0x8]; 3318 u8 log_rra_max[0x3]; 3319 u8 reserved_at_48b[0x1]; 3320 u8 atomic_mode[0x4]; 3321 u8 rre[0x1]; 3322 u8 rwe[0x1]; 3323 u8 rae[0x1]; 3324 u8 reserved_at_493[0x1]; 3325 u8 page_offset[0x6]; 3326 u8 reserved_at_49a[0x3]; 3327 u8 cd_slave_receive[0x1]; 3328 u8 cd_slave_send[0x1]; 3329 u8 cd_master[0x1]; 3330 3331 u8 reserved_at_4a0[0x3]; 3332 u8 min_rnr_nak[0x5]; 3333 u8 next_rcv_psn[0x18]; 3334 3335 u8 reserved_at_4c0[0x8]; 3336 u8 xrcd[0x18]; 3337 3338 u8 reserved_at_4e0[0x8]; 3339 u8 cqn_rcv[0x18]; 3340 3341 u8 dbr_addr[0x40]; 3342 3343 u8 q_key[0x20]; 3344 3345 u8 reserved_at_560[0x5]; 3346 u8 rq_type[0x3]; 3347 u8 srqn_rmpn_xrqn[0x18]; 3348 3349 u8 reserved_at_580[0x8]; 3350 u8 rmsn[0x18]; 3351 3352 u8 hw_sq_wqebb_counter[0x10]; 3353 u8 sw_sq_wqebb_counter[0x10]; 3354 3355 u8 hw_rq_counter[0x20]; 3356 3357 u8 sw_rq_counter[0x20]; 3358 3359 u8 reserved_at_600[0x20]; 3360 3361 u8 reserved_at_620[0xf]; 3362 u8 cgs[0x1]; 3363 u8 cs_req[0x8]; 3364 u8 cs_res[0x8]; 3365 3366 u8 dc_access_key[0x40]; 3367 3368 u8 reserved_at_680[0x3]; 3369 u8 dbr_umem_valid[0x1]; 3370 3371 u8 reserved_at_684[0xbc]; 3372 }; 3373 3374 struct mlx5_ifc_roce_addr_layout_bits { 3375 u8 source_l3_address[16][0x8]; 3376 3377 u8 reserved_at_80[0x3]; 3378 u8 vlan_valid[0x1]; 3379 u8 vlan_id[0xc]; 3380 u8 source_mac_47_32[0x10]; 3381 3382 u8 source_mac_31_0[0x20]; 3383 3384 u8 reserved_at_c0[0x14]; 3385 u8 roce_l3_type[0x4]; 3386 u8 roce_version[0x8]; 3387 3388 u8 reserved_at_e0[0x20]; 3389 }; 3390 3391 struct mlx5_ifc_shampo_cap_bits { 3392 u8 reserved_at_0[0x3]; 3393 u8 shampo_log_max_reservation_size[0x5]; 3394 u8 reserved_at_8[0x3]; 3395 u8 shampo_log_min_reservation_size[0x5]; 3396 u8 shampo_min_mss_size[0x10]; 3397 3398 u8 reserved_at_20[0x3]; 3399 u8 shampo_max_log_headers_entry_size[0x5]; 3400 u8 reserved_at_28[0x18]; 3401 3402 u8 reserved_at_40[0x7c0]; 3403 }; 3404 3405 struct mlx5_ifc_crypto_cap_bits { 3406 u8 reserved_at_0[0x3]; 3407 u8 synchronize_dek[0x1]; 3408 u8 int_kek_manual[0x1]; 3409 u8 int_kek_auto[0x1]; 3410 u8 reserved_at_6[0x1a]; 3411 3412 u8 reserved_at_20[0x3]; 3413 u8 log_dek_max_alloc[0x5]; 3414 u8 reserved_at_28[0x3]; 3415 u8 log_max_num_deks[0x5]; 3416 u8 reserved_at_30[0x10]; 3417 3418 u8 reserved_at_40[0x20]; 3419 3420 u8 reserved_at_60[0x3]; 3421 u8 log_dek_granularity[0x5]; 3422 u8 reserved_at_68[0x3]; 3423 u8 log_max_num_int_kek[0x5]; 3424 u8 sw_wrapped_dek[0x10]; 3425 3426 u8 reserved_at_80[0x780]; 3427 }; 3428 3429 union mlx5_ifc_hca_cap_union_bits { 3430 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap; 3431 struct mlx5_ifc_cmd_hca_cap_2_bits cmd_hca_cap_2; 3432 struct mlx5_ifc_odp_cap_bits odp_cap; 3433 struct mlx5_ifc_atomic_caps_bits atomic_caps; 3434 struct mlx5_ifc_roce_cap_bits roce_cap; 3435 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps; 3436 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap; 3437 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap; 3438 struct mlx5_ifc_e_switch_cap_bits e_switch_cap; 3439 struct mlx5_ifc_port_selection_cap_bits port_selection_cap; 3440 struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap; 3441 struct mlx5_ifc_qos_cap_bits qos_cap; 3442 struct mlx5_ifc_debug_cap_bits debug_cap; 3443 struct mlx5_ifc_fpga_cap_bits fpga_cap; 3444 struct mlx5_ifc_tls_cap_bits tls_cap; 3445 struct mlx5_ifc_device_mem_cap_bits device_mem_cap; 3446 struct mlx5_ifc_virtio_emulation_cap_bits virtio_emulation_cap; 3447 struct mlx5_ifc_shampo_cap_bits shampo_cap; 3448 struct mlx5_ifc_macsec_cap_bits macsec_cap; 3449 struct mlx5_ifc_crypto_cap_bits crypto_cap; 3450 u8 reserved_at_0[0x8000]; 3451 }; 3452 3453 enum { 3454 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1, 3455 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2, 3456 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4, 3457 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8, 3458 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT = 0x10, 3459 MLX5_FLOW_CONTEXT_ACTION_DECAP = 0x20, 3460 MLX5_FLOW_CONTEXT_ACTION_MOD_HDR = 0x40, 3461 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP = 0x80, 3462 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100, 3463 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2 = 0x400, 3464 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2 = 0x800, 3465 MLX5_FLOW_CONTEXT_ACTION_CRYPTO_DECRYPT = 0x1000, 3466 MLX5_FLOW_CONTEXT_ACTION_CRYPTO_ENCRYPT = 0x2000, 3467 MLX5_FLOW_CONTEXT_ACTION_EXECUTE_ASO = 0x4000, 3468 }; 3469 3470 enum { 3471 MLX5_FLOW_CONTEXT_FLOW_SOURCE_ANY_VPORT = 0x0, 3472 MLX5_FLOW_CONTEXT_FLOW_SOURCE_UPLINK = 0x1, 3473 MLX5_FLOW_CONTEXT_FLOW_SOURCE_LOCAL_VPORT = 0x2, 3474 }; 3475 3476 enum { 3477 MLX5_FLOW_CONTEXT_ENCRYPT_DECRYPT_TYPE_IPSEC = 0x0, 3478 MLX5_FLOW_CONTEXT_ENCRYPT_DECRYPT_TYPE_MACSEC = 0x1, 3479 }; 3480 3481 struct mlx5_ifc_vlan_bits { 3482 u8 ethtype[0x10]; 3483 u8 prio[0x3]; 3484 u8 cfi[0x1]; 3485 u8 vid[0xc]; 3486 }; 3487 3488 enum { 3489 MLX5_FLOW_METER_COLOR_RED = 0x0, 3490 MLX5_FLOW_METER_COLOR_YELLOW = 0x1, 3491 MLX5_FLOW_METER_COLOR_GREEN = 0x2, 3492 MLX5_FLOW_METER_COLOR_UNDEFINED = 0x3, 3493 }; 3494 3495 enum { 3496 MLX5_EXE_ASO_FLOW_METER = 0x2, 3497 }; 3498 3499 struct mlx5_ifc_exe_aso_ctrl_flow_meter_bits { 3500 u8 return_reg_id[0x4]; 3501 u8 aso_type[0x4]; 3502 u8 reserved_at_8[0x14]; 3503 u8 action[0x1]; 3504 u8 init_color[0x2]; 3505 u8 meter_id[0x1]; 3506 }; 3507 3508 union mlx5_ifc_exe_aso_ctrl { 3509 struct mlx5_ifc_exe_aso_ctrl_flow_meter_bits exe_aso_ctrl_flow_meter; 3510 }; 3511 3512 struct mlx5_ifc_execute_aso_bits { 3513 u8 valid[0x1]; 3514 u8 reserved_at_1[0x7]; 3515 u8 aso_object_id[0x18]; 3516 3517 union mlx5_ifc_exe_aso_ctrl exe_aso_ctrl; 3518 }; 3519 3520 struct mlx5_ifc_flow_context_bits { 3521 struct mlx5_ifc_vlan_bits push_vlan; 3522 3523 u8 group_id[0x20]; 3524 3525 u8 reserved_at_40[0x8]; 3526 u8 flow_tag[0x18]; 3527 3528 u8 reserved_at_60[0x10]; 3529 u8 action[0x10]; 3530 3531 u8 extended_destination[0x1]; 3532 u8 reserved_at_81[0x1]; 3533 u8 flow_source[0x2]; 3534 u8 encrypt_decrypt_type[0x4]; 3535 u8 destination_list_size[0x18]; 3536 3537 u8 reserved_at_a0[0x8]; 3538 u8 flow_counter_list_size[0x18]; 3539 3540 u8 packet_reformat_id[0x20]; 3541 3542 u8 modify_header_id[0x20]; 3543 3544 struct mlx5_ifc_vlan_bits push_vlan_2; 3545 3546 u8 encrypt_decrypt_obj_id[0x20]; 3547 u8 reserved_at_140[0xc0]; 3548 3549 struct mlx5_ifc_fte_match_param_bits match_value; 3550 3551 struct mlx5_ifc_execute_aso_bits execute_aso[4]; 3552 3553 u8 reserved_at_1300[0x500]; 3554 3555 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[]; 3556 }; 3557 3558 enum { 3559 MLX5_XRC_SRQC_STATE_GOOD = 0x0, 3560 MLX5_XRC_SRQC_STATE_ERROR = 0x1, 3561 }; 3562 3563 struct mlx5_ifc_xrc_srqc_bits { 3564 u8 state[0x4]; 3565 u8 log_xrc_srq_size[0x4]; 3566 u8 reserved_at_8[0x18]; 3567 3568 u8 wq_signature[0x1]; 3569 u8 cont_srq[0x1]; 3570 u8 reserved_at_22[0x1]; 3571 u8 rlky[0x1]; 3572 u8 basic_cyclic_rcv_wqe[0x1]; 3573 u8 log_rq_stride[0x3]; 3574 u8 xrcd[0x18]; 3575 3576 u8 page_offset[0x6]; 3577 u8 reserved_at_46[0x1]; 3578 u8 dbr_umem_valid[0x1]; 3579 u8 cqn[0x18]; 3580 3581 u8 reserved_at_60[0x20]; 3582 3583 u8 user_index_equal_xrc_srqn[0x1]; 3584 u8 reserved_at_81[0x1]; 3585 u8 log_page_size[0x6]; 3586 u8 user_index[0x18]; 3587 3588 u8 reserved_at_a0[0x20]; 3589 3590 u8 reserved_at_c0[0x8]; 3591 u8 pd[0x18]; 3592 3593 u8 lwm[0x10]; 3594 u8 wqe_cnt[0x10]; 3595 3596 u8 reserved_at_100[0x40]; 3597 3598 u8 db_record_addr_h[0x20]; 3599 3600 u8 db_record_addr_l[0x1e]; 3601 u8 reserved_at_17e[0x2]; 3602 3603 u8 reserved_at_180[0x80]; 3604 }; 3605 3606 struct mlx5_ifc_vnic_diagnostic_statistics_bits { 3607 u8 counter_error_queues[0x20]; 3608 3609 u8 total_error_queues[0x20]; 3610 3611 u8 send_queue_priority_update_flow[0x20]; 3612 3613 u8 reserved_at_60[0x20]; 3614 3615 u8 nic_receive_steering_discard[0x40]; 3616 3617 u8 receive_discard_vport_down[0x40]; 3618 3619 u8 transmit_discard_vport_down[0x40]; 3620 3621 u8 async_eq_overrun[0x20]; 3622 3623 u8 comp_eq_overrun[0x20]; 3624 3625 u8 reserved_at_180[0x20]; 3626 3627 u8 invalid_command[0x20]; 3628 3629 u8 quota_exceeded_command[0x20]; 3630 3631 u8 internal_rq_out_of_buffer[0x20]; 3632 3633 u8 cq_overrun[0x20]; 3634 3635 u8 eth_wqe_too_small[0x20]; 3636 3637 u8 reserved_at_220[0xdc0]; 3638 }; 3639 3640 struct mlx5_ifc_traffic_counter_bits { 3641 u8 packets[0x40]; 3642 3643 u8 octets[0x40]; 3644 }; 3645 3646 struct mlx5_ifc_tisc_bits { 3647 u8 strict_lag_tx_port_affinity[0x1]; 3648 u8 tls_en[0x1]; 3649 u8 reserved_at_2[0x2]; 3650 u8 lag_tx_port_affinity[0x04]; 3651 3652 u8 reserved_at_8[0x4]; 3653 u8 prio[0x4]; 3654 u8 reserved_at_10[0x10]; 3655 3656 u8 reserved_at_20[0x100]; 3657 3658 u8 reserved_at_120[0x8]; 3659 u8 transport_domain[0x18]; 3660 3661 u8 reserved_at_140[0x8]; 3662 u8 underlay_qpn[0x18]; 3663 3664 u8 reserved_at_160[0x8]; 3665 u8 pd[0x18]; 3666 3667 u8 reserved_at_180[0x380]; 3668 }; 3669 3670 enum { 3671 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0, 3672 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1, 3673 }; 3674 3675 enum { 3676 MLX5_TIRC_PACKET_MERGE_MASK_IPV4_LRO = BIT(0), 3677 MLX5_TIRC_PACKET_MERGE_MASK_IPV6_LRO = BIT(1), 3678 }; 3679 3680 enum { 3681 MLX5_RX_HASH_FN_NONE = 0x0, 3682 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1, 3683 MLX5_RX_HASH_FN_TOEPLITZ = 0x2, 3684 }; 3685 3686 enum { 3687 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST = 0x1, 3688 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST = 0x2, 3689 }; 3690 3691 struct mlx5_ifc_tirc_bits { 3692 u8 reserved_at_0[0x20]; 3693 3694 u8 disp_type[0x4]; 3695 u8 tls_en[0x1]; 3696 u8 reserved_at_25[0x1b]; 3697 3698 u8 reserved_at_40[0x40]; 3699 3700 u8 reserved_at_80[0x4]; 3701 u8 lro_timeout_period_usecs[0x10]; 3702 u8 packet_merge_mask[0x4]; 3703 u8 lro_max_ip_payload_size[0x8]; 3704 3705 u8 reserved_at_a0[0x40]; 3706 3707 u8 reserved_at_e0[0x8]; 3708 u8 inline_rqn[0x18]; 3709 3710 u8 rx_hash_symmetric[0x1]; 3711 u8 reserved_at_101[0x1]; 3712 u8 tunneled_offload_en[0x1]; 3713 u8 reserved_at_103[0x5]; 3714 u8 indirect_table[0x18]; 3715 3716 u8 rx_hash_fn[0x4]; 3717 u8 reserved_at_124[0x2]; 3718 u8 self_lb_block[0x2]; 3719 u8 transport_domain[0x18]; 3720 3721 u8 rx_hash_toeplitz_key[10][0x20]; 3722 3723 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer; 3724 3725 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner; 3726 3727 u8 reserved_at_2c0[0x4c0]; 3728 }; 3729 3730 enum { 3731 MLX5_SRQC_STATE_GOOD = 0x0, 3732 MLX5_SRQC_STATE_ERROR = 0x1, 3733 }; 3734 3735 struct mlx5_ifc_srqc_bits { 3736 u8 state[0x4]; 3737 u8 log_srq_size[0x4]; 3738 u8 reserved_at_8[0x18]; 3739 3740 u8 wq_signature[0x1]; 3741 u8 cont_srq[0x1]; 3742 u8 reserved_at_22[0x1]; 3743 u8 rlky[0x1]; 3744 u8 reserved_at_24[0x1]; 3745 u8 log_rq_stride[0x3]; 3746 u8 xrcd[0x18]; 3747 3748 u8 page_offset[0x6]; 3749 u8 reserved_at_46[0x2]; 3750 u8 cqn[0x18]; 3751 3752 u8 reserved_at_60[0x20]; 3753 3754 u8 reserved_at_80[0x2]; 3755 u8 log_page_size[0x6]; 3756 u8 reserved_at_88[0x18]; 3757 3758 u8 reserved_at_a0[0x20]; 3759 3760 u8 reserved_at_c0[0x8]; 3761 u8 pd[0x18]; 3762 3763 u8 lwm[0x10]; 3764 u8 wqe_cnt[0x10]; 3765 3766 u8 reserved_at_100[0x40]; 3767 3768 u8 dbr_addr[0x40]; 3769 3770 u8 reserved_at_180[0x80]; 3771 }; 3772 3773 enum { 3774 MLX5_SQC_STATE_RST = 0x0, 3775 MLX5_SQC_STATE_RDY = 0x1, 3776 MLX5_SQC_STATE_ERR = 0x3, 3777 }; 3778 3779 struct mlx5_ifc_sqc_bits { 3780 u8 rlky[0x1]; 3781 u8 cd_master[0x1]; 3782 u8 fre[0x1]; 3783 u8 flush_in_error_en[0x1]; 3784 u8 allow_multi_pkt_send_wqe[0x1]; 3785 u8 min_wqe_inline_mode[0x3]; 3786 u8 state[0x4]; 3787 u8 reg_umr[0x1]; 3788 u8 allow_swp[0x1]; 3789 u8 hairpin[0x1]; 3790 u8 reserved_at_f[0xb]; 3791 u8 ts_format[0x2]; 3792 u8 reserved_at_1c[0x4]; 3793 3794 u8 reserved_at_20[0x8]; 3795 u8 user_index[0x18]; 3796 3797 u8 reserved_at_40[0x8]; 3798 u8 cqn[0x18]; 3799 3800 u8 reserved_at_60[0x8]; 3801 u8 hairpin_peer_rq[0x18]; 3802 3803 u8 reserved_at_80[0x10]; 3804 u8 hairpin_peer_vhca[0x10]; 3805 3806 u8 reserved_at_a0[0x20]; 3807 3808 u8 reserved_at_c0[0x8]; 3809 u8 ts_cqe_to_dest_cqn[0x18]; 3810 3811 u8 reserved_at_e0[0x10]; 3812 u8 packet_pacing_rate_limit_index[0x10]; 3813 u8 tis_lst_sz[0x10]; 3814 u8 qos_queue_group_id[0x10]; 3815 3816 u8 reserved_at_120[0x40]; 3817 3818 u8 reserved_at_160[0x8]; 3819 u8 tis_num_0[0x18]; 3820 3821 struct mlx5_ifc_wq_bits wq; 3822 }; 3823 3824 enum { 3825 SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0, 3826 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1, 3827 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2, 3828 SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3, 3829 SCHEDULING_CONTEXT_ELEMENT_TYPE_QUEUE_GROUP = 0x4, 3830 }; 3831 3832 enum { 3833 ELEMENT_TYPE_CAP_MASK_TASR = 1 << 0, 3834 ELEMENT_TYPE_CAP_MASK_VPORT = 1 << 1, 3835 ELEMENT_TYPE_CAP_MASK_VPORT_TC = 1 << 2, 3836 ELEMENT_TYPE_CAP_MASK_PARA_VPORT_TC = 1 << 3, 3837 }; 3838 3839 struct mlx5_ifc_scheduling_context_bits { 3840 u8 element_type[0x8]; 3841 u8 reserved_at_8[0x18]; 3842 3843 u8 element_attributes[0x20]; 3844 3845 u8 parent_element_id[0x20]; 3846 3847 u8 reserved_at_60[0x40]; 3848 3849 u8 bw_share[0x20]; 3850 3851 u8 max_average_bw[0x20]; 3852 3853 u8 reserved_at_e0[0x120]; 3854 }; 3855 3856 struct mlx5_ifc_rqtc_bits { 3857 u8 reserved_at_0[0xa0]; 3858 3859 u8 reserved_at_a0[0x5]; 3860 u8 list_q_type[0x3]; 3861 u8 reserved_at_a8[0x8]; 3862 u8 rqt_max_size[0x10]; 3863 3864 u8 rq_vhca_id_format[0x1]; 3865 u8 reserved_at_c1[0xf]; 3866 u8 rqt_actual_size[0x10]; 3867 3868 u8 reserved_at_e0[0x6a0]; 3869 3870 struct mlx5_ifc_rq_num_bits rq_num[]; 3871 }; 3872 3873 enum { 3874 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0, 3875 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1, 3876 }; 3877 3878 enum { 3879 MLX5_RQC_STATE_RST = 0x0, 3880 MLX5_RQC_STATE_RDY = 0x1, 3881 MLX5_RQC_STATE_ERR = 0x3, 3882 }; 3883 3884 enum { 3885 MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_BYTE = 0x0, 3886 MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_STRIDE = 0x1, 3887 MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_PAGE = 0x2, 3888 }; 3889 3890 enum { 3891 MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_NO_MATCH = 0x0, 3892 MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_EXTENDED = 0x1, 3893 MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_FIVE_TUPLE = 0x2, 3894 }; 3895 3896 struct mlx5_ifc_rqc_bits { 3897 u8 rlky[0x1]; 3898 u8 delay_drop_en[0x1]; 3899 u8 scatter_fcs[0x1]; 3900 u8 vsd[0x1]; 3901 u8 mem_rq_type[0x4]; 3902 u8 state[0x4]; 3903 u8 reserved_at_c[0x1]; 3904 u8 flush_in_error_en[0x1]; 3905 u8 hairpin[0x1]; 3906 u8 reserved_at_f[0xb]; 3907 u8 ts_format[0x2]; 3908 u8 reserved_at_1c[0x4]; 3909 3910 u8 reserved_at_20[0x8]; 3911 u8 user_index[0x18]; 3912 3913 u8 reserved_at_40[0x8]; 3914 u8 cqn[0x18]; 3915 3916 u8 counter_set_id[0x8]; 3917 u8 reserved_at_68[0x18]; 3918 3919 u8 reserved_at_80[0x8]; 3920 u8 rmpn[0x18]; 3921 3922 u8 reserved_at_a0[0x8]; 3923 u8 hairpin_peer_sq[0x18]; 3924 3925 u8 reserved_at_c0[0x10]; 3926 u8 hairpin_peer_vhca[0x10]; 3927 3928 u8 reserved_at_e0[0x46]; 3929 u8 shampo_no_match_alignment_granularity[0x2]; 3930 u8 reserved_at_128[0x6]; 3931 u8 shampo_match_criteria_type[0x2]; 3932 u8 reservation_timeout[0x10]; 3933 3934 u8 reserved_at_140[0x40]; 3935 3936 struct mlx5_ifc_wq_bits wq; 3937 }; 3938 3939 enum { 3940 MLX5_RMPC_STATE_RDY = 0x1, 3941 MLX5_RMPC_STATE_ERR = 0x3, 3942 }; 3943 3944 struct mlx5_ifc_rmpc_bits { 3945 u8 reserved_at_0[0x8]; 3946 u8 state[0x4]; 3947 u8 reserved_at_c[0x14]; 3948 3949 u8 basic_cyclic_rcv_wqe[0x1]; 3950 u8 reserved_at_21[0x1f]; 3951 3952 u8 reserved_at_40[0x140]; 3953 3954 struct mlx5_ifc_wq_bits wq; 3955 }; 3956 3957 enum { 3958 VHCA_ID_TYPE_HW = 0, 3959 VHCA_ID_TYPE_SW = 1, 3960 }; 3961 3962 struct mlx5_ifc_nic_vport_context_bits { 3963 u8 reserved_at_0[0x5]; 3964 u8 min_wqe_inline_mode[0x3]; 3965 u8 reserved_at_8[0x15]; 3966 u8 disable_mc_local_lb[0x1]; 3967 u8 disable_uc_local_lb[0x1]; 3968 u8 roce_en[0x1]; 3969 3970 u8 arm_change_event[0x1]; 3971 u8 reserved_at_21[0x1a]; 3972 u8 event_on_mtu[0x1]; 3973 u8 event_on_promisc_change[0x1]; 3974 u8 event_on_vlan_change[0x1]; 3975 u8 event_on_mc_address_change[0x1]; 3976 u8 event_on_uc_address_change[0x1]; 3977 3978 u8 vhca_id_type[0x1]; 3979 u8 reserved_at_41[0xb]; 3980 u8 affiliation_criteria[0x4]; 3981 u8 affiliated_vhca_id[0x10]; 3982 3983 u8 reserved_at_60[0xd0]; 3984 3985 u8 mtu[0x10]; 3986 3987 u8 system_image_guid[0x40]; 3988 u8 port_guid[0x40]; 3989 u8 node_guid[0x40]; 3990 3991 u8 reserved_at_200[0x140]; 3992 u8 qkey_violation_counter[0x10]; 3993 u8 reserved_at_350[0x430]; 3994 3995 u8 promisc_uc[0x1]; 3996 u8 promisc_mc[0x1]; 3997 u8 promisc_all[0x1]; 3998 u8 reserved_at_783[0x2]; 3999 u8 allowed_list_type[0x3]; 4000 u8 reserved_at_788[0xc]; 4001 u8 allowed_list_size[0xc]; 4002 4003 struct mlx5_ifc_mac_address_layout_bits permanent_address; 4004 4005 u8 reserved_at_7e0[0x20]; 4006 4007 u8 current_uc_mac_address[][0x40]; 4008 }; 4009 4010 enum { 4011 MLX5_MKC_ACCESS_MODE_PA = 0x0, 4012 MLX5_MKC_ACCESS_MODE_MTT = 0x1, 4013 MLX5_MKC_ACCESS_MODE_KLMS = 0x2, 4014 MLX5_MKC_ACCESS_MODE_KSM = 0x3, 4015 MLX5_MKC_ACCESS_MODE_SW_ICM = 0x4, 4016 MLX5_MKC_ACCESS_MODE_MEMIC = 0x5, 4017 }; 4018 4019 struct mlx5_ifc_mkc_bits { 4020 u8 reserved_at_0[0x1]; 4021 u8 free[0x1]; 4022 u8 reserved_at_2[0x1]; 4023 u8 access_mode_4_2[0x3]; 4024 u8 reserved_at_6[0x7]; 4025 u8 relaxed_ordering_write[0x1]; 4026 u8 reserved_at_e[0x1]; 4027 u8 small_fence_on_rdma_read_response[0x1]; 4028 u8 umr_en[0x1]; 4029 u8 a[0x1]; 4030 u8 rw[0x1]; 4031 u8 rr[0x1]; 4032 u8 lw[0x1]; 4033 u8 lr[0x1]; 4034 u8 access_mode_1_0[0x2]; 4035 u8 reserved_at_18[0x2]; 4036 u8 ma_translation_mode[0x2]; 4037 u8 reserved_at_1c[0x4]; 4038 4039 u8 qpn[0x18]; 4040 u8 mkey_7_0[0x8]; 4041 4042 u8 reserved_at_40[0x20]; 4043 4044 u8 length64[0x1]; 4045 u8 bsf_en[0x1]; 4046 u8 sync_umr[0x1]; 4047 u8 reserved_at_63[0x2]; 4048 u8 expected_sigerr_count[0x1]; 4049 u8 reserved_at_66[0x1]; 4050 u8 en_rinval[0x1]; 4051 u8 pd[0x18]; 4052 4053 u8 start_addr[0x40]; 4054 4055 u8 len[0x40]; 4056 4057 u8 bsf_octword_size[0x20]; 4058 4059 u8 reserved_at_120[0x80]; 4060 4061 u8 translations_octword_size[0x20]; 4062 4063 u8 reserved_at_1c0[0x19]; 4064 u8 relaxed_ordering_read[0x1]; 4065 u8 reserved_at_1d9[0x1]; 4066 u8 log_page_size[0x5]; 4067 4068 u8 reserved_at_1e0[0x20]; 4069 }; 4070 4071 struct mlx5_ifc_pkey_bits { 4072 u8 reserved_at_0[0x10]; 4073 u8 pkey[0x10]; 4074 }; 4075 4076 struct mlx5_ifc_array128_auto_bits { 4077 u8 array128_auto[16][0x8]; 4078 }; 4079 4080 struct mlx5_ifc_hca_vport_context_bits { 4081 u8 field_select[0x20]; 4082 4083 u8 reserved_at_20[0xe0]; 4084 4085 u8 sm_virt_aware[0x1]; 4086 u8 has_smi[0x1]; 4087 u8 has_raw[0x1]; 4088 u8 grh_required[0x1]; 4089 u8 reserved_at_104[0xc]; 4090 u8 port_physical_state[0x4]; 4091 u8 vport_state_policy[0x4]; 4092 u8 port_state[0x4]; 4093 u8 vport_state[0x4]; 4094 4095 u8 reserved_at_120[0x20]; 4096 4097 u8 system_image_guid[0x40]; 4098 4099 u8 port_guid[0x40]; 4100 4101 u8 node_guid[0x40]; 4102 4103 u8 cap_mask1[0x20]; 4104 4105 u8 cap_mask1_field_select[0x20]; 4106 4107 u8 cap_mask2[0x20]; 4108 4109 u8 cap_mask2_field_select[0x20]; 4110 4111 u8 reserved_at_280[0x80]; 4112 4113 u8 lid[0x10]; 4114 u8 reserved_at_310[0x4]; 4115 u8 init_type_reply[0x4]; 4116 u8 lmc[0x3]; 4117 u8 subnet_timeout[0x5]; 4118 4119 u8 sm_lid[0x10]; 4120 u8 sm_sl[0x4]; 4121 u8 reserved_at_334[0xc]; 4122 4123 u8 qkey_violation_counter[0x10]; 4124 u8 pkey_violation_counter[0x10]; 4125 4126 u8 reserved_at_360[0xca0]; 4127 }; 4128 4129 struct mlx5_ifc_esw_vport_context_bits { 4130 u8 fdb_to_vport_reg_c[0x1]; 4131 u8 reserved_at_1[0x2]; 4132 u8 vport_svlan_strip[0x1]; 4133 u8 vport_cvlan_strip[0x1]; 4134 u8 vport_svlan_insert[0x1]; 4135 u8 vport_cvlan_insert[0x2]; 4136 u8 fdb_to_vport_reg_c_id[0x8]; 4137 u8 reserved_at_10[0x10]; 4138 4139 u8 reserved_at_20[0x20]; 4140 4141 u8 svlan_cfi[0x1]; 4142 u8 svlan_pcp[0x3]; 4143 u8 svlan_id[0xc]; 4144 u8 cvlan_cfi[0x1]; 4145 u8 cvlan_pcp[0x3]; 4146 u8 cvlan_id[0xc]; 4147 4148 u8 reserved_at_60[0x720]; 4149 4150 u8 sw_steering_vport_icm_address_rx[0x40]; 4151 4152 u8 sw_steering_vport_icm_address_tx[0x40]; 4153 }; 4154 4155 enum { 4156 MLX5_EQC_STATUS_OK = 0x0, 4157 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa, 4158 }; 4159 4160 enum { 4161 MLX5_EQC_ST_ARMED = 0x9, 4162 MLX5_EQC_ST_FIRED = 0xa, 4163 }; 4164 4165 struct mlx5_ifc_eqc_bits { 4166 u8 status[0x4]; 4167 u8 reserved_at_4[0x9]; 4168 u8 ec[0x1]; 4169 u8 oi[0x1]; 4170 u8 reserved_at_f[0x5]; 4171 u8 st[0x4]; 4172 u8 reserved_at_18[0x8]; 4173 4174 u8 reserved_at_20[0x20]; 4175 4176 u8 reserved_at_40[0x14]; 4177 u8 page_offset[0x6]; 4178 u8 reserved_at_5a[0x6]; 4179 4180 u8 reserved_at_60[0x3]; 4181 u8 log_eq_size[0x5]; 4182 u8 uar_page[0x18]; 4183 4184 u8 reserved_at_80[0x20]; 4185 4186 u8 reserved_at_a0[0x14]; 4187 u8 intr[0xc]; 4188 4189 u8 reserved_at_c0[0x3]; 4190 u8 log_page_size[0x5]; 4191 u8 reserved_at_c8[0x18]; 4192 4193 u8 reserved_at_e0[0x60]; 4194 4195 u8 reserved_at_140[0x8]; 4196 u8 consumer_counter[0x18]; 4197 4198 u8 reserved_at_160[0x8]; 4199 u8 producer_counter[0x18]; 4200 4201 u8 reserved_at_180[0x80]; 4202 }; 4203 4204 enum { 4205 MLX5_DCTC_STATE_ACTIVE = 0x0, 4206 MLX5_DCTC_STATE_DRAINING = 0x1, 4207 MLX5_DCTC_STATE_DRAINED = 0x2, 4208 }; 4209 4210 enum { 4211 MLX5_DCTC_CS_RES_DISABLE = 0x0, 4212 MLX5_DCTC_CS_RES_NA = 0x1, 4213 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2, 4214 }; 4215 4216 enum { 4217 MLX5_DCTC_MTU_256_BYTES = 0x1, 4218 MLX5_DCTC_MTU_512_BYTES = 0x2, 4219 MLX5_DCTC_MTU_1K_BYTES = 0x3, 4220 MLX5_DCTC_MTU_2K_BYTES = 0x4, 4221 MLX5_DCTC_MTU_4K_BYTES = 0x5, 4222 }; 4223 4224 struct mlx5_ifc_dctc_bits { 4225 u8 reserved_at_0[0x4]; 4226 u8 state[0x4]; 4227 u8 reserved_at_8[0x18]; 4228 4229 u8 reserved_at_20[0x8]; 4230 u8 user_index[0x18]; 4231 4232 u8 reserved_at_40[0x8]; 4233 u8 cqn[0x18]; 4234 4235 u8 counter_set_id[0x8]; 4236 u8 atomic_mode[0x4]; 4237 u8 rre[0x1]; 4238 u8 rwe[0x1]; 4239 u8 rae[0x1]; 4240 u8 atomic_like_write_en[0x1]; 4241 u8 latency_sensitive[0x1]; 4242 u8 rlky[0x1]; 4243 u8 free_ar[0x1]; 4244 u8 reserved_at_73[0xd]; 4245 4246 u8 reserved_at_80[0x8]; 4247 u8 cs_res[0x8]; 4248 u8 reserved_at_90[0x3]; 4249 u8 min_rnr_nak[0x5]; 4250 u8 reserved_at_98[0x8]; 4251 4252 u8 reserved_at_a0[0x8]; 4253 u8 srqn_xrqn[0x18]; 4254 4255 u8 reserved_at_c0[0x8]; 4256 u8 pd[0x18]; 4257 4258 u8 tclass[0x8]; 4259 u8 reserved_at_e8[0x4]; 4260 u8 flow_label[0x14]; 4261 4262 u8 dc_access_key[0x40]; 4263 4264 u8 reserved_at_140[0x5]; 4265 u8 mtu[0x3]; 4266 u8 port[0x8]; 4267 u8 pkey_index[0x10]; 4268 4269 u8 reserved_at_160[0x8]; 4270 u8 my_addr_index[0x8]; 4271 u8 reserved_at_170[0x8]; 4272 u8 hop_limit[0x8]; 4273 4274 u8 dc_access_key_violation_count[0x20]; 4275 4276 u8 reserved_at_1a0[0x14]; 4277 u8 dei_cfi[0x1]; 4278 u8 eth_prio[0x3]; 4279 u8 ecn[0x2]; 4280 u8 dscp[0x6]; 4281 4282 u8 reserved_at_1c0[0x20]; 4283 u8 ece[0x20]; 4284 }; 4285 4286 enum { 4287 MLX5_CQC_STATUS_OK = 0x0, 4288 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9, 4289 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa, 4290 }; 4291 4292 enum { 4293 MLX5_CQC_CQE_SZ_64_BYTES = 0x0, 4294 MLX5_CQC_CQE_SZ_128_BYTES = 0x1, 4295 }; 4296 4297 enum { 4298 MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED = 0x6, 4299 MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED = 0x9, 4300 MLX5_CQC_ST_FIRED = 0xa, 4301 }; 4302 4303 enum { 4304 MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0, 4305 MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1, 4306 MLX5_CQ_PERIOD_NUM_MODES 4307 }; 4308 4309 struct mlx5_ifc_cqc_bits { 4310 u8 status[0x4]; 4311 u8 reserved_at_4[0x2]; 4312 u8 dbr_umem_valid[0x1]; 4313 u8 apu_cq[0x1]; 4314 u8 cqe_sz[0x3]; 4315 u8 cc[0x1]; 4316 u8 reserved_at_c[0x1]; 4317 u8 scqe_break_moderation_en[0x1]; 4318 u8 oi[0x1]; 4319 u8 cq_period_mode[0x2]; 4320 u8 cqe_comp_en[0x1]; 4321 u8 mini_cqe_res_format[0x2]; 4322 u8 st[0x4]; 4323 u8 reserved_at_18[0x6]; 4324 u8 cqe_compression_layout[0x2]; 4325 4326 u8 reserved_at_20[0x20]; 4327 4328 u8 reserved_at_40[0x14]; 4329 u8 page_offset[0x6]; 4330 u8 reserved_at_5a[0x6]; 4331 4332 u8 reserved_at_60[0x3]; 4333 u8 log_cq_size[0x5]; 4334 u8 uar_page[0x18]; 4335 4336 u8 reserved_at_80[0x4]; 4337 u8 cq_period[0xc]; 4338 u8 cq_max_count[0x10]; 4339 4340 u8 c_eqn_or_apu_element[0x20]; 4341 4342 u8 reserved_at_c0[0x3]; 4343 u8 log_page_size[0x5]; 4344 u8 reserved_at_c8[0x18]; 4345 4346 u8 reserved_at_e0[0x20]; 4347 4348 u8 reserved_at_100[0x8]; 4349 u8 last_notified_index[0x18]; 4350 4351 u8 reserved_at_120[0x8]; 4352 u8 last_solicit_index[0x18]; 4353 4354 u8 reserved_at_140[0x8]; 4355 u8 consumer_counter[0x18]; 4356 4357 u8 reserved_at_160[0x8]; 4358 u8 producer_counter[0x18]; 4359 4360 u8 reserved_at_180[0x40]; 4361 4362 u8 dbr_addr[0x40]; 4363 }; 4364 4365 union mlx5_ifc_cong_control_roce_ecn_auto_bits { 4366 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp; 4367 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp; 4368 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np; 4369 struct mlx5_ifc_cong_control_r_roce_general_bits cong_control_r_roce_general; 4370 u8 reserved_at_0[0x800]; 4371 }; 4372 4373 struct mlx5_ifc_query_adapter_param_block_bits { 4374 u8 reserved_at_0[0xc0]; 4375 4376 u8 reserved_at_c0[0x8]; 4377 u8 ieee_vendor_id[0x18]; 4378 4379 u8 reserved_at_e0[0x10]; 4380 u8 vsd_vendor_id[0x10]; 4381 4382 u8 vsd[208][0x8]; 4383 4384 u8 vsd_contd_psid[16][0x8]; 4385 }; 4386 4387 enum { 4388 MLX5_XRQC_STATE_GOOD = 0x0, 4389 MLX5_XRQC_STATE_ERROR = 0x1, 4390 }; 4391 4392 enum { 4393 MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0, 4394 MLX5_XRQC_TOPOLOGY_TAG_MATCHING = 0x1, 4395 }; 4396 4397 enum { 4398 MLX5_XRQC_OFFLOAD_RNDV = 0x1, 4399 }; 4400 4401 struct mlx5_ifc_tag_matching_topology_context_bits { 4402 u8 log_matching_list_sz[0x4]; 4403 u8 reserved_at_4[0xc]; 4404 u8 append_next_index[0x10]; 4405 4406 u8 sw_phase_cnt[0x10]; 4407 u8 hw_phase_cnt[0x10]; 4408 4409 u8 reserved_at_40[0x40]; 4410 }; 4411 4412 struct mlx5_ifc_xrqc_bits { 4413 u8 state[0x4]; 4414 u8 rlkey[0x1]; 4415 u8 reserved_at_5[0xf]; 4416 u8 topology[0x4]; 4417 u8 reserved_at_18[0x4]; 4418 u8 offload[0x4]; 4419 4420 u8 reserved_at_20[0x8]; 4421 u8 user_index[0x18]; 4422 4423 u8 reserved_at_40[0x8]; 4424 u8 cqn[0x18]; 4425 4426 u8 reserved_at_60[0xa0]; 4427 4428 struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context; 4429 4430 u8 reserved_at_180[0x280]; 4431 4432 struct mlx5_ifc_wq_bits wq; 4433 }; 4434 4435 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits { 4436 struct mlx5_ifc_modify_field_select_bits modify_field_select; 4437 struct mlx5_ifc_resize_field_select_bits resize_field_select; 4438 u8 reserved_at_0[0x20]; 4439 }; 4440 4441 union mlx5_ifc_field_select_802_1_r_roce_auto_bits { 4442 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp; 4443 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp; 4444 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np; 4445 u8 reserved_at_0[0x20]; 4446 }; 4447 4448 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits { 4449 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 4450 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 4451 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 4452 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 4453 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 4454 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 4455 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout; 4456 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout; 4457 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 4458 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 4459 struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs; 4460 u8 reserved_at_0[0x7c0]; 4461 }; 4462 4463 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits { 4464 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout; 4465 u8 reserved_at_0[0x7c0]; 4466 }; 4467 4468 union mlx5_ifc_event_auto_bits { 4469 struct mlx5_ifc_comp_event_bits comp_event; 4470 struct mlx5_ifc_dct_events_bits dct_events; 4471 struct mlx5_ifc_qp_events_bits qp_events; 4472 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event; 4473 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event; 4474 struct mlx5_ifc_cq_error_bits cq_error; 4475 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged; 4476 struct mlx5_ifc_port_state_change_event_bits port_state_change_event; 4477 struct mlx5_ifc_gpio_event_bits gpio_event; 4478 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event; 4479 struct mlx5_ifc_stall_vl_event_bits stall_vl_event; 4480 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event; 4481 u8 reserved_at_0[0xe0]; 4482 }; 4483 4484 struct mlx5_ifc_health_buffer_bits { 4485 u8 reserved_at_0[0x100]; 4486 4487 u8 assert_existptr[0x20]; 4488 4489 u8 assert_callra[0x20]; 4490 4491 u8 reserved_at_140[0x20]; 4492 4493 u8 time[0x20]; 4494 4495 u8 fw_version[0x20]; 4496 4497 u8 hw_id[0x20]; 4498 4499 u8 rfr[0x1]; 4500 u8 reserved_at_1c1[0x3]; 4501 u8 valid[0x1]; 4502 u8 severity[0x3]; 4503 u8 reserved_at_1c8[0x18]; 4504 4505 u8 irisc_index[0x8]; 4506 u8 synd[0x8]; 4507 u8 ext_synd[0x10]; 4508 }; 4509 4510 struct mlx5_ifc_register_loopback_control_bits { 4511 u8 no_lb[0x1]; 4512 u8 reserved_at_1[0x7]; 4513 u8 port[0x8]; 4514 u8 reserved_at_10[0x10]; 4515 4516 u8 reserved_at_20[0x60]; 4517 }; 4518 4519 struct mlx5_ifc_vport_tc_element_bits { 4520 u8 traffic_class[0x4]; 4521 u8 reserved_at_4[0xc]; 4522 u8 vport_number[0x10]; 4523 }; 4524 4525 struct mlx5_ifc_vport_element_bits { 4526 u8 reserved_at_0[0x10]; 4527 u8 vport_number[0x10]; 4528 }; 4529 4530 enum { 4531 TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0, 4532 TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1, 4533 TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2, 4534 }; 4535 4536 struct mlx5_ifc_tsar_element_bits { 4537 u8 reserved_at_0[0x8]; 4538 u8 tsar_type[0x8]; 4539 u8 reserved_at_10[0x10]; 4540 }; 4541 4542 enum { 4543 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0, 4544 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1, 4545 }; 4546 4547 struct mlx5_ifc_teardown_hca_out_bits { 4548 u8 status[0x8]; 4549 u8 reserved_at_8[0x18]; 4550 4551 u8 syndrome[0x20]; 4552 4553 u8 reserved_at_40[0x3f]; 4554 4555 u8 state[0x1]; 4556 }; 4557 4558 enum { 4559 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0, 4560 MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE = 0x1, 4561 MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN = 0x2, 4562 }; 4563 4564 struct mlx5_ifc_teardown_hca_in_bits { 4565 u8 opcode[0x10]; 4566 u8 reserved_at_10[0x10]; 4567 4568 u8 reserved_at_20[0x10]; 4569 u8 op_mod[0x10]; 4570 4571 u8 reserved_at_40[0x10]; 4572 u8 profile[0x10]; 4573 4574 u8 reserved_at_60[0x20]; 4575 }; 4576 4577 struct mlx5_ifc_sqerr2rts_qp_out_bits { 4578 u8 status[0x8]; 4579 u8 reserved_at_8[0x18]; 4580 4581 u8 syndrome[0x20]; 4582 4583 u8 reserved_at_40[0x40]; 4584 }; 4585 4586 struct mlx5_ifc_sqerr2rts_qp_in_bits { 4587 u8 opcode[0x10]; 4588 u8 uid[0x10]; 4589 4590 u8 reserved_at_20[0x10]; 4591 u8 op_mod[0x10]; 4592 4593 u8 reserved_at_40[0x8]; 4594 u8 qpn[0x18]; 4595 4596 u8 reserved_at_60[0x20]; 4597 4598 u8 opt_param_mask[0x20]; 4599 4600 u8 reserved_at_a0[0x20]; 4601 4602 struct mlx5_ifc_qpc_bits qpc; 4603 4604 u8 reserved_at_800[0x80]; 4605 }; 4606 4607 struct mlx5_ifc_sqd2rts_qp_out_bits { 4608 u8 status[0x8]; 4609 u8 reserved_at_8[0x18]; 4610 4611 u8 syndrome[0x20]; 4612 4613 u8 reserved_at_40[0x40]; 4614 }; 4615 4616 struct mlx5_ifc_sqd2rts_qp_in_bits { 4617 u8 opcode[0x10]; 4618 u8 uid[0x10]; 4619 4620 u8 reserved_at_20[0x10]; 4621 u8 op_mod[0x10]; 4622 4623 u8 reserved_at_40[0x8]; 4624 u8 qpn[0x18]; 4625 4626 u8 reserved_at_60[0x20]; 4627 4628 u8 opt_param_mask[0x20]; 4629 4630 u8 reserved_at_a0[0x20]; 4631 4632 struct mlx5_ifc_qpc_bits qpc; 4633 4634 u8 reserved_at_800[0x80]; 4635 }; 4636 4637 struct mlx5_ifc_set_roce_address_out_bits { 4638 u8 status[0x8]; 4639 u8 reserved_at_8[0x18]; 4640 4641 u8 syndrome[0x20]; 4642 4643 u8 reserved_at_40[0x40]; 4644 }; 4645 4646 struct mlx5_ifc_set_roce_address_in_bits { 4647 u8 opcode[0x10]; 4648 u8 reserved_at_10[0x10]; 4649 4650 u8 reserved_at_20[0x10]; 4651 u8 op_mod[0x10]; 4652 4653 u8 roce_address_index[0x10]; 4654 u8 reserved_at_50[0xc]; 4655 u8 vhca_port_num[0x4]; 4656 4657 u8 reserved_at_60[0x20]; 4658 4659 struct mlx5_ifc_roce_addr_layout_bits roce_address; 4660 }; 4661 4662 struct mlx5_ifc_set_mad_demux_out_bits { 4663 u8 status[0x8]; 4664 u8 reserved_at_8[0x18]; 4665 4666 u8 syndrome[0x20]; 4667 4668 u8 reserved_at_40[0x40]; 4669 }; 4670 4671 enum { 4672 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0, 4673 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2, 4674 }; 4675 4676 struct mlx5_ifc_set_mad_demux_in_bits { 4677 u8 opcode[0x10]; 4678 u8 reserved_at_10[0x10]; 4679 4680 u8 reserved_at_20[0x10]; 4681 u8 op_mod[0x10]; 4682 4683 u8 reserved_at_40[0x20]; 4684 4685 u8 reserved_at_60[0x6]; 4686 u8 demux_mode[0x2]; 4687 u8 reserved_at_68[0x18]; 4688 }; 4689 4690 struct mlx5_ifc_set_l2_table_entry_out_bits { 4691 u8 status[0x8]; 4692 u8 reserved_at_8[0x18]; 4693 4694 u8 syndrome[0x20]; 4695 4696 u8 reserved_at_40[0x40]; 4697 }; 4698 4699 struct mlx5_ifc_set_l2_table_entry_in_bits { 4700 u8 opcode[0x10]; 4701 u8 reserved_at_10[0x10]; 4702 4703 u8 reserved_at_20[0x10]; 4704 u8 op_mod[0x10]; 4705 4706 u8 reserved_at_40[0x60]; 4707 4708 u8 reserved_at_a0[0x8]; 4709 u8 table_index[0x18]; 4710 4711 u8 reserved_at_c0[0x20]; 4712 4713 u8 reserved_at_e0[0x13]; 4714 u8 vlan_valid[0x1]; 4715 u8 vlan[0xc]; 4716 4717 struct mlx5_ifc_mac_address_layout_bits mac_address; 4718 4719 u8 reserved_at_140[0xc0]; 4720 }; 4721 4722 struct mlx5_ifc_set_issi_out_bits { 4723 u8 status[0x8]; 4724 u8 reserved_at_8[0x18]; 4725 4726 u8 syndrome[0x20]; 4727 4728 u8 reserved_at_40[0x40]; 4729 }; 4730 4731 struct mlx5_ifc_set_issi_in_bits { 4732 u8 opcode[0x10]; 4733 u8 reserved_at_10[0x10]; 4734 4735 u8 reserved_at_20[0x10]; 4736 u8 op_mod[0x10]; 4737 4738 u8 reserved_at_40[0x10]; 4739 u8 current_issi[0x10]; 4740 4741 u8 reserved_at_60[0x20]; 4742 }; 4743 4744 struct mlx5_ifc_set_hca_cap_out_bits { 4745 u8 status[0x8]; 4746 u8 reserved_at_8[0x18]; 4747 4748 u8 syndrome[0x20]; 4749 4750 u8 reserved_at_40[0x40]; 4751 }; 4752 4753 struct mlx5_ifc_set_hca_cap_in_bits { 4754 u8 opcode[0x10]; 4755 u8 reserved_at_10[0x10]; 4756 4757 u8 reserved_at_20[0x10]; 4758 u8 op_mod[0x10]; 4759 4760 u8 other_function[0x1]; 4761 u8 reserved_at_41[0xf]; 4762 u8 function_id[0x10]; 4763 4764 u8 reserved_at_60[0x20]; 4765 4766 union mlx5_ifc_hca_cap_union_bits capability; 4767 }; 4768 4769 enum { 4770 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0, 4771 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1, 4772 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2, 4773 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3, 4774 MLX5_SET_FTE_MODIFY_ENABLE_MASK_IPSEC_OBJ_ID = 0x4 4775 }; 4776 4777 struct mlx5_ifc_set_fte_out_bits { 4778 u8 status[0x8]; 4779 u8 reserved_at_8[0x18]; 4780 4781 u8 syndrome[0x20]; 4782 4783 u8 reserved_at_40[0x40]; 4784 }; 4785 4786 struct mlx5_ifc_set_fte_in_bits { 4787 u8 opcode[0x10]; 4788 u8 reserved_at_10[0x10]; 4789 4790 u8 reserved_at_20[0x10]; 4791 u8 op_mod[0x10]; 4792 4793 u8 other_vport[0x1]; 4794 u8 reserved_at_41[0xf]; 4795 u8 vport_number[0x10]; 4796 4797 u8 reserved_at_60[0x20]; 4798 4799 u8 table_type[0x8]; 4800 u8 reserved_at_88[0x18]; 4801 4802 u8 reserved_at_a0[0x8]; 4803 u8 table_id[0x18]; 4804 4805 u8 ignore_flow_level[0x1]; 4806 u8 reserved_at_c1[0x17]; 4807 u8 modify_enable_mask[0x8]; 4808 4809 u8 reserved_at_e0[0x20]; 4810 4811 u8 flow_index[0x20]; 4812 4813 u8 reserved_at_120[0xe0]; 4814 4815 struct mlx5_ifc_flow_context_bits flow_context; 4816 }; 4817 4818 struct mlx5_ifc_rts2rts_qp_out_bits { 4819 u8 status[0x8]; 4820 u8 reserved_at_8[0x18]; 4821 4822 u8 syndrome[0x20]; 4823 4824 u8 reserved_at_40[0x20]; 4825 u8 ece[0x20]; 4826 }; 4827 4828 struct mlx5_ifc_rts2rts_qp_in_bits { 4829 u8 opcode[0x10]; 4830 u8 uid[0x10]; 4831 4832 u8 reserved_at_20[0x10]; 4833 u8 op_mod[0x10]; 4834 4835 u8 reserved_at_40[0x8]; 4836 u8 qpn[0x18]; 4837 4838 u8 reserved_at_60[0x20]; 4839 4840 u8 opt_param_mask[0x20]; 4841 4842 u8 ece[0x20]; 4843 4844 struct mlx5_ifc_qpc_bits qpc; 4845 4846 u8 reserved_at_800[0x80]; 4847 }; 4848 4849 struct mlx5_ifc_rtr2rts_qp_out_bits { 4850 u8 status[0x8]; 4851 u8 reserved_at_8[0x18]; 4852 4853 u8 syndrome[0x20]; 4854 4855 u8 reserved_at_40[0x20]; 4856 u8 ece[0x20]; 4857 }; 4858 4859 struct mlx5_ifc_rtr2rts_qp_in_bits { 4860 u8 opcode[0x10]; 4861 u8 uid[0x10]; 4862 4863 u8 reserved_at_20[0x10]; 4864 u8 op_mod[0x10]; 4865 4866 u8 reserved_at_40[0x8]; 4867 u8 qpn[0x18]; 4868 4869 u8 reserved_at_60[0x20]; 4870 4871 u8 opt_param_mask[0x20]; 4872 4873 u8 ece[0x20]; 4874 4875 struct mlx5_ifc_qpc_bits qpc; 4876 4877 u8 reserved_at_800[0x80]; 4878 }; 4879 4880 struct mlx5_ifc_rst2init_qp_out_bits { 4881 u8 status[0x8]; 4882 u8 reserved_at_8[0x18]; 4883 4884 u8 syndrome[0x20]; 4885 4886 u8 reserved_at_40[0x20]; 4887 u8 ece[0x20]; 4888 }; 4889 4890 struct mlx5_ifc_rst2init_qp_in_bits { 4891 u8 opcode[0x10]; 4892 u8 uid[0x10]; 4893 4894 u8 reserved_at_20[0x10]; 4895 u8 op_mod[0x10]; 4896 4897 u8 reserved_at_40[0x8]; 4898 u8 qpn[0x18]; 4899 4900 u8 reserved_at_60[0x20]; 4901 4902 u8 opt_param_mask[0x20]; 4903 4904 u8 ece[0x20]; 4905 4906 struct mlx5_ifc_qpc_bits qpc; 4907 4908 u8 reserved_at_800[0x80]; 4909 }; 4910 4911 struct mlx5_ifc_query_xrq_out_bits { 4912 u8 status[0x8]; 4913 u8 reserved_at_8[0x18]; 4914 4915 u8 syndrome[0x20]; 4916 4917 u8 reserved_at_40[0x40]; 4918 4919 struct mlx5_ifc_xrqc_bits xrq_context; 4920 }; 4921 4922 struct mlx5_ifc_query_xrq_in_bits { 4923 u8 opcode[0x10]; 4924 u8 reserved_at_10[0x10]; 4925 4926 u8 reserved_at_20[0x10]; 4927 u8 op_mod[0x10]; 4928 4929 u8 reserved_at_40[0x8]; 4930 u8 xrqn[0x18]; 4931 4932 u8 reserved_at_60[0x20]; 4933 }; 4934 4935 struct mlx5_ifc_query_xrc_srq_out_bits { 4936 u8 status[0x8]; 4937 u8 reserved_at_8[0x18]; 4938 4939 u8 syndrome[0x20]; 4940 4941 u8 reserved_at_40[0x40]; 4942 4943 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 4944 4945 u8 reserved_at_280[0x600]; 4946 4947 u8 pas[][0x40]; 4948 }; 4949 4950 struct mlx5_ifc_query_xrc_srq_in_bits { 4951 u8 opcode[0x10]; 4952 u8 reserved_at_10[0x10]; 4953 4954 u8 reserved_at_20[0x10]; 4955 u8 op_mod[0x10]; 4956 4957 u8 reserved_at_40[0x8]; 4958 u8 xrc_srqn[0x18]; 4959 4960 u8 reserved_at_60[0x20]; 4961 }; 4962 4963 enum { 4964 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0, 4965 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1, 4966 }; 4967 4968 struct mlx5_ifc_query_vport_state_out_bits { 4969 u8 status[0x8]; 4970 u8 reserved_at_8[0x18]; 4971 4972 u8 syndrome[0x20]; 4973 4974 u8 reserved_at_40[0x20]; 4975 4976 u8 reserved_at_60[0x18]; 4977 u8 admin_state[0x4]; 4978 u8 state[0x4]; 4979 }; 4980 4981 enum { 4982 MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT = 0x0, 4983 MLX5_VPORT_STATE_OP_MOD_ESW_VPORT = 0x1, 4984 MLX5_VPORT_STATE_OP_MOD_UPLINK = 0x2, 4985 }; 4986 4987 struct mlx5_ifc_arm_monitor_counter_in_bits { 4988 u8 opcode[0x10]; 4989 u8 uid[0x10]; 4990 4991 u8 reserved_at_20[0x10]; 4992 u8 op_mod[0x10]; 4993 4994 u8 reserved_at_40[0x20]; 4995 4996 u8 reserved_at_60[0x20]; 4997 }; 4998 4999 struct mlx5_ifc_arm_monitor_counter_out_bits { 5000 u8 status[0x8]; 5001 u8 reserved_at_8[0x18]; 5002 5003 u8 syndrome[0x20]; 5004 5005 u8 reserved_at_40[0x40]; 5006 }; 5007 5008 enum { 5009 MLX5_QUERY_MONITOR_CNT_TYPE_PPCNT = 0x0, 5010 MLX5_QUERY_MONITOR_CNT_TYPE_Q_COUNTER = 0x1, 5011 }; 5012 5013 enum mlx5_monitor_counter_ppcnt { 5014 MLX5_QUERY_MONITOR_PPCNT_IN_RANGE_LENGTH_ERRORS = 0x0, 5015 MLX5_QUERY_MONITOR_PPCNT_OUT_OF_RANGE_LENGTH_FIELD = 0x1, 5016 MLX5_QUERY_MONITOR_PPCNT_FRAME_TOO_LONG_ERRORS = 0x2, 5017 MLX5_QUERY_MONITOR_PPCNT_FRAME_CHECK_SEQUENCE_ERRORS = 0x3, 5018 MLX5_QUERY_MONITOR_PPCNT_ALIGNMENT_ERRORS = 0x4, 5019 MLX5_QUERY_MONITOR_PPCNT_IF_OUT_DISCARDS = 0x5, 5020 }; 5021 5022 enum { 5023 MLX5_QUERY_MONITOR_Q_COUNTER_RX_OUT_OF_BUFFER = 0x4, 5024 }; 5025 5026 struct mlx5_ifc_monitor_counter_output_bits { 5027 u8 reserved_at_0[0x4]; 5028 u8 type[0x4]; 5029 u8 reserved_at_8[0x8]; 5030 u8 counter[0x10]; 5031 5032 u8 counter_group_id[0x20]; 5033 }; 5034 5035 #define MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 (6) 5036 #define MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1 (1) 5037 #define MLX5_CMD_SET_MONITOR_NUM_COUNTER (MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 +\ 5038 MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1) 5039 5040 struct mlx5_ifc_set_monitor_counter_in_bits { 5041 u8 opcode[0x10]; 5042 u8 uid[0x10]; 5043 5044 u8 reserved_at_20[0x10]; 5045 u8 op_mod[0x10]; 5046 5047 u8 reserved_at_40[0x10]; 5048 u8 num_of_counters[0x10]; 5049 5050 u8 reserved_at_60[0x20]; 5051 5052 struct mlx5_ifc_monitor_counter_output_bits monitor_counter[MLX5_CMD_SET_MONITOR_NUM_COUNTER]; 5053 }; 5054 5055 struct mlx5_ifc_set_monitor_counter_out_bits { 5056 u8 status[0x8]; 5057 u8 reserved_at_8[0x18]; 5058 5059 u8 syndrome[0x20]; 5060 5061 u8 reserved_at_40[0x40]; 5062 }; 5063 5064 struct mlx5_ifc_query_vport_state_in_bits { 5065 u8 opcode[0x10]; 5066 u8 reserved_at_10[0x10]; 5067 5068 u8 reserved_at_20[0x10]; 5069 u8 op_mod[0x10]; 5070 5071 u8 other_vport[0x1]; 5072 u8 reserved_at_41[0xf]; 5073 u8 vport_number[0x10]; 5074 5075 u8 reserved_at_60[0x20]; 5076 }; 5077 5078 struct mlx5_ifc_query_vnic_env_out_bits { 5079 u8 status[0x8]; 5080 u8 reserved_at_8[0x18]; 5081 5082 u8 syndrome[0x20]; 5083 5084 u8 reserved_at_40[0x40]; 5085 5086 struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env; 5087 }; 5088 5089 enum { 5090 MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS = 0x0, 5091 }; 5092 5093 struct mlx5_ifc_query_vnic_env_in_bits { 5094 u8 opcode[0x10]; 5095 u8 reserved_at_10[0x10]; 5096 5097 u8 reserved_at_20[0x10]; 5098 u8 op_mod[0x10]; 5099 5100 u8 other_vport[0x1]; 5101 u8 reserved_at_41[0xf]; 5102 u8 vport_number[0x10]; 5103 5104 u8 reserved_at_60[0x20]; 5105 }; 5106 5107 struct mlx5_ifc_query_vport_counter_out_bits { 5108 u8 status[0x8]; 5109 u8 reserved_at_8[0x18]; 5110 5111 u8 syndrome[0x20]; 5112 5113 u8 reserved_at_40[0x40]; 5114 5115 struct mlx5_ifc_traffic_counter_bits received_errors; 5116 5117 struct mlx5_ifc_traffic_counter_bits transmit_errors; 5118 5119 struct mlx5_ifc_traffic_counter_bits received_ib_unicast; 5120 5121 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast; 5122 5123 struct mlx5_ifc_traffic_counter_bits received_ib_multicast; 5124 5125 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast; 5126 5127 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast; 5128 5129 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast; 5130 5131 struct mlx5_ifc_traffic_counter_bits received_eth_unicast; 5132 5133 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast; 5134 5135 struct mlx5_ifc_traffic_counter_bits received_eth_multicast; 5136 5137 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast; 5138 5139 u8 reserved_at_680[0xa00]; 5140 }; 5141 5142 enum { 5143 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0, 5144 }; 5145 5146 struct mlx5_ifc_query_vport_counter_in_bits { 5147 u8 opcode[0x10]; 5148 u8 reserved_at_10[0x10]; 5149 5150 u8 reserved_at_20[0x10]; 5151 u8 op_mod[0x10]; 5152 5153 u8 other_vport[0x1]; 5154 u8 reserved_at_41[0xb]; 5155 u8 port_num[0x4]; 5156 u8 vport_number[0x10]; 5157 5158 u8 reserved_at_60[0x60]; 5159 5160 u8 clear[0x1]; 5161 u8 reserved_at_c1[0x1f]; 5162 5163 u8 reserved_at_e0[0x20]; 5164 }; 5165 5166 struct mlx5_ifc_query_tis_out_bits { 5167 u8 status[0x8]; 5168 u8 reserved_at_8[0x18]; 5169 5170 u8 syndrome[0x20]; 5171 5172 u8 reserved_at_40[0x40]; 5173 5174 struct mlx5_ifc_tisc_bits tis_context; 5175 }; 5176 5177 struct mlx5_ifc_query_tis_in_bits { 5178 u8 opcode[0x10]; 5179 u8 reserved_at_10[0x10]; 5180 5181 u8 reserved_at_20[0x10]; 5182 u8 op_mod[0x10]; 5183 5184 u8 reserved_at_40[0x8]; 5185 u8 tisn[0x18]; 5186 5187 u8 reserved_at_60[0x20]; 5188 }; 5189 5190 struct mlx5_ifc_query_tir_out_bits { 5191 u8 status[0x8]; 5192 u8 reserved_at_8[0x18]; 5193 5194 u8 syndrome[0x20]; 5195 5196 u8 reserved_at_40[0xc0]; 5197 5198 struct mlx5_ifc_tirc_bits tir_context; 5199 }; 5200 5201 struct mlx5_ifc_query_tir_in_bits { 5202 u8 opcode[0x10]; 5203 u8 reserved_at_10[0x10]; 5204 5205 u8 reserved_at_20[0x10]; 5206 u8 op_mod[0x10]; 5207 5208 u8 reserved_at_40[0x8]; 5209 u8 tirn[0x18]; 5210 5211 u8 reserved_at_60[0x20]; 5212 }; 5213 5214 struct mlx5_ifc_query_srq_out_bits { 5215 u8 status[0x8]; 5216 u8 reserved_at_8[0x18]; 5217 5218 u8 syndrome[0x20]; 5219 5220 u8 reserved_at_40[0x40]; 5221 5222 struct mlx5_ifc_srqc_bits srq_context_entry; 5223 5224 u8 reserved_at_280[0x600]; 5225 5226 u8 pas[][0x40]; 5227 }; 5228 5229 struct mlx5_ifc_query_srq_in_bits { 5230 u8 opcode[0x10]; 5231 u8 reserved_at_10[0x10]; 5232 5233 u8 reserved_at_20[0x10]; 5234 u8 op_mod[0x10]; 5235 5236 u8 reserved_at_40[0x8]; 5237 u8 srqn[0x18]; 5238 5239 u8 reserved_at_60[0x20]; 5240 }; 5241 5242 struct mlx5_ifc_query_sq_out_bits { 5243 u8 status[0x8]; 5244 u8 reserved_at_8[0x18]; 5245 5246 u8 syndrome[0x20]; 5247 5248 u8 reserved_at_40[0xc0]; 5249 5250 struct mlx5_ifc_sqc_bits sq_context; 5251 }; 5252 5253 struct mlx5_ifc_query_sq_in_bits { 5254 u8 opcode[0x10]; 5255 u8 reserved_at_10[0x10]; 5256 5257 u8 reserved_at_20[0x10]; 5258 u8 op_mod[0x10]; 5259 5260 u8 reserved_at_40[0x8]; 5261 u8 sqn[0x18]; 5262 5263 u8 reserved_at_60[0x20]; 5264 }; 5265 5266 struct mlx5_ifc_query_special_contexts_out_bits { 5267 u8 status[0x8]; 5268 u8 reserved_at_8[0x18]; 5269 5270 u8 syndrome[0x20]; 5271 5272 u8 dump_fill_mkey[0x20]; 5273 5274 u8 resd_lkey[0x20]; 5275 5276 u8 null_mkey[0x20]; 5277 5278 u8 terminate_scatter_list_mkey[0x20]; 5279 5280 u8 repeated_mkey[0x20]; 5281 5282 u8 reserved_at_a0[0x20]; 5283 }; 5284 5285 struct mlx5_ifc_query_special_contexts_in_bits { 5286 u8 opcode[0x10]; 5287 u8 reserved_at_10[0x10]; 5288 5289 u8 reserved_at_20[0x10]; 5290 u8 op_mod[0x10]; 5291 5292 u8 reserved_at_40[0x40]; 5293 }; 5294 5295 struct mlx5_ifc_query_scheduling_element_out_bits { 5296 u8 opcode[0x10]; 5297 u8 reserved_at_10[0x10]; 5298 5299 u8 reserved_at_20[0x10]; 5300 u8 op_mod[0x10]; 5301 5302 u8 reserved_at_40[0xc0]; 5303 5304 struct mlx5_ifc_scheduling_context_bits scheduling_context; 5305 5306 u8 reserved_at_300[0x100]; 5307 }; 5308 5309 enum { 5310 SCHEDULING_HIERARCHY_E_SWITCH = 0x2, 5311 SCHEDULING_HIERARCHY_NIC = 0x3, 5312 }; 5313 5314 struct mlx5_ifc_query_scheduling_element_in_bits { 5315 u8 opcode[0x10]; 5316 u8 reserved_at_10[0x10]; 5317 5318 u8 reserved_at_20[0x10]; 5319 u8 op_mod[0x10]; 5320 5321 u8 scheduling_hierarchy[0x8]; 5322 u8 reserved_at_48[0x18]; 5323 5324 u8 scheduling_element_id[0x20]; 5325 5326 u8 reserved_at_80[0x180]; 5327 }; 5328 5329 struct mlx5_ifc_query_rqt_out_bits { 5330 u8 status[0x8]; 5331 u8 reserved_at_8[0x18]; 5332 5333 u8 syndrome[0x20]; 5334 5335 u8 reserved_at_40[0xc0]; 5336 5337 struct mlx5_ifc_rqtc_bits rqt_context; 5338 }; 5339 5340 struct mlx5_ifc_query_rqt_in_bits { 5341 u8 opcode[0x10]; 5342 u8 reserved_at_10[0x10]; 5343 5344 u8 reserved_at_20[0x10]; 5345 u8 op_mod[0x10]; 5346 5347 u8 reserved_at_40[0x8]; 5348 u8 rqtn[0x18]; 5349 5350 u8 reserved_at_60[0x20]; 5351 }; 5352 5353 struct mlx5_ifc_query_rq_out_bits { 5354 u8 status[0x8]; 5355 u8 reserved_at_8[0x18]; 5356 5357 u8 syndrome[0x20]; 5358 5359 u8 reserved_at_40[0xc0]; 5360 5361 struct mlx5_ifc_rqc_bits rq_context; 5362 }; 5363 5364 struct mlx5_ifc_query_rq_in_bits { 5365 u8 opcode[0x10]; 5366 u8 reserved_at_10[0x10]; 5367 5368 u8 reserved_at_20[0x10]; 5369 u8 op_mod[0x10]; 5370 5371 u8 reserved_at_40[0x8]; 5372 u8 rqn[0x18]; 5373 5374 u8 reserved_at_60[0x20]; 5375 }; 5376 5377 struct mlx5_ifc_query_roce_address_out_bits { 5378 u8 status[0x8]; 5379 u8 reserved_at_8[0x18]; 5380 5381 u8 syndrome[0x20]; 5382 5383 u8 reserved_at_40[0x40]; 5384 5385 struct mlx5_ifc_roce_addr_layout_bits roce_address; 5386 }; 5387 5388 struct mlx5_ifc_query_roce_address_in_bits { 5389 u8 opcode[0x10]; 5390 u8 reserved_at_10[0x10]; 5391 5392 u8 reserved_at_20[0x10]; 5393 u8 op_mod[0x10]; 5394 5395 u8 roce_address_index[0x10]; 5396 u8 reserved_at_50[0xc]; 5397 u8 vhca_port_num[0x4]; 5398 5399 u8 reserved_at_60[0x20]; 5400 }; 5401 5402 struct mlx5_ifc_query_rmp_out_bits { 5403 u8 status[0x8]; 5404 u8 reserved_at_8[0x18]; 5405 5406 u8 syndrome[0x20]; 5407 5408 u8 reserved_at_40[0xc0]; 5409 5410 struct mlx5_ifc_rmpc_bits rmp_context; 5411 }; 5412 5413 struct mlx5_ifc_query_rmp_in_bits { 5414 u8 opcode[0x10]; 5415 u8 reserved_at_10[0x10]; 5416 5417 u8 reserved_at_20[0x10]; 5418 u8 op_mod[0x10]; 5419 5420 u8 reserved_at_40[0x8]; 5421 u8 rmpn[0x18]; 5422 5423 u8 reserved_at_60[0x20]; 5424 }; 5425 5426 struct mlx5_ifc_cqe_error_syndrome_bits { 5427 u8 hw_error_syndrome[0x8]; 5428 u8 hw_syndrome_type[0x4]; 5429 u8 reserved_at_c[0x4]; 5430 u8 vendor_error_syndrome[0x8]; 5431 u8 syndrome[0x8]; 5432 }; 5433 5434 struct mlx5_ifc_qp_context_extension_bits { 5435 u8 reserved_at_0[0x60]; 5436 5437 struct mlx5_ifc_cqe_error_syndrome_bits error_syndrome; 5438 5439 u8 reserved_at_80[0x580]; 5440 }; 5441 5442 struct mlx5_ifc_qpc_extension_and_pas_list_in_bits { 5443 struct mlx5_ifc_qp_context_extension_bits qpc_data_extension; 5444 5445 u8 pas[0][0x40]; 5446 }; 5447 5448 struct mlx5_ifc_qp_pas_list_in_bits { 5449 struct mlx5_ifc_cmd_pas_bits pas[0]; 5450 }; 5451 5452 union mlx5_ifc_qp_pas_or_qpc_ext_and_pas_bits { 5453 struct mlx5_ifc_qp_pas_list_in_bits qp_pas_list; 5454 struct mlx5_ifc_qpc_extension_and_pas_list_in_bits qpc_ext_and_pas_list; 5455 }; 5456 5457 struct mlx5_ifc_query_qp_out_bits { 5458 u8 status[0x8]; 5459 u8 reserved_at_8[0x18]; 5460 5461 u8 syndrome[0x20]; 5462 5463 u8 reserved_at_40[0x40]; 5464 5465 u8 opt_param_mask[0x20]; 5466 5467 u8 ece[0x20]; 5468 5469 struct mlx5_ifc_qpc_bits qpc; 5470 5471 u8 reserved_at_800[0x80]; 5472 5473 union mlx5_ifc_qp_pas_or_qpc_ext_and_pas_bits qp_pas_or_qpc_ext_and_pas; 5474 }; 5475 5476 struct mlx5_ifc_query_qp_in_bits { 5477 u8 opcode[0x10]; 5478 u8 reserved_at_10[0x10]; 5479 5480 u8 reserved_at_20[0x10]; 5481 u8 op_mod[0x10]; 5482 5483 u8 qpc_ext[0x1]; 5484 u8 reserved_at_41[0x7]; 5485 u8 qpn[0x18]; 5486 5487 u8 reserved_at_60[0x20]; 5488 }; 5489 5490 struct mlx5_ifc_query_q_counter_out_bits { 5491 u8 status[0x8]; 5492 u8 reserved_at_8[0x18]; 5493 5494 u8 syndrome[0x20]; 5495 5496 u8 reserved_at_40[0x40]; 5497 5498 u8 rx_write_requests[0x20]; 5499 5500 u8 reserved_at_a0[0x20]; 5501 5502 u8 rx_read_requests[0x20]; 5503 5504 u8 reserved_at_e0[0x20]; 5505 5506 u8 rx_atomic_requests[0x20]; 5507 5508 u8 reserved_at_120[0x20]; 5509 5510 u8 rx_dct_connect[0x20]; 5511 5512 u8 reserved_at_160[0x20]; 5513 5514 u8 out_of_buffer[0x20]; 5515 5516 u8 reserved_at_1a0[0x20]; 5517 5518 u8 out_of_sequence[0x20]; 5519 5520 u8 reserved_at_1e0[0x20]; 5521 5522 u8 duplicate_request[0x20]; 5523 5524 u8 reserved_at_220[0x20]; 5525 5526 u8 rnr_nak_retry_err[0x20]; 5527 5528 u8 reserved_at_260[0x20]; 5529 5530 u8 packet_seq_err[0x20]; 5531 5532 u8 reserved_at_2a0[0x20]; 5533 5534 u8 implied_nak_seq_err[0x20]; 5535 5536 u8 reserved_at_2e0[0x20]; 5537 5538 u8 local_ack_timeout_err[0x20]; 5539 5540 u8 reserved_at_320[0xa0]; 5541 5542 u8 resp_local_length_error[0x20]; 5543 5544 u8 req_local_length_error[0x20]; 5545 5546 u8 resp_local_qp_error[0x20]; 5547 5548 u8 local_operation_error[0x20]; 5549 5550 u8 resp_local_protection[0x20]; 5551 5552 u8 req_local_protection[0x20]; 5553 5554 u8 resp_cqe_error[0x20]; 5555 5556 u8 req_cqe_error[0x20]; 5557 5558 u8 req_mw_binding[0x20]; 5559 5560 u8 req_bad_response[0x20]; 5561 5562 u8 req_remote_invalid_request[0x20]; 5563 5564 u8 resp_remote_invalid_request[0x20]; 5565 5566 u8 req_remote_access_errors[0x20]; 5567 5568 u8 resp_remote_access_errors[0x20]; 5569 5570 u8 req_remote_operation_errors[0x20]; 5571 5572 u8 req_transport_retries_exceeded[0x20]; 5573 5574 u8 cq_overflow[0x20]; 5575 5576 u8 resp_cqe_flush_error[0x20]; 5577 5578 u8 req_cqe_flush_error[0x20]; 5579 5580 u8 reserved_at_620[0x20]; 5581 5582 u8 roce_adp_retrans[0x20]; 5583 5584 u8 roce_adp_retrans_to[0x20]; 5585 5586 u8 roce_slow_restart[0x20]; 5587 5588 u8 roce_slow_restart_cnps[0x20]; 5589 5590 u8 roce_slow_restart_trans[0x20]; 5591 5592 u8 reserved_at_6e0[0x120]; 5593 }; 5594 5595 struct mlx5_ifc_query_q_counter_in_bits { 5596 u8 opcode[0x10]; 5597 u8 reserved_at_10[0x10]; 5598 5599 u8 reserved_at_20[0x10]; 5600 u8 op_mod[0x10]; 5601 5602 u8 reserved_at_40[0x80]; 5603 5604 u8 clear[0x1]; 5605 u8 reserved_at_c1[0x1f]; 5606 5607 u8 reserved_at_e0[0x18]; 5608 u8 counter_set_id[0x8]; 5609 }; 5610 5611 struct mlx5_ifc_query_pages_out_bits { 5612 u8 status[0x8]; 5613 u8 reserved_at_8[0x18]; 5614 5615 u8 syndrome[0x20]; 5616 5617 u8 embedded_cpu_function[0x1]; 5618 u8 reserved_at_41[0xf]; 5619 u8 function_id[0x10]; 5620 5621 u8 num_pages[0x20]; 5622 }; 5623 5624 enum { 5625 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1, 5626 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2, 5627 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3, 5628 }; 5629 5630 struct mlx5_ifc_query_pages_in_bits { 5631 u8 opcode[0x10]; 5632 u8 reserved_at_10[0x10]; 5633 5634 u8 reserved_at_20[0x10]; 5635 u8 op_mod[0x10]; 5636 5637 u8 embedded_cpu_function[0x1]; 5638 u8 reserved_at_41[0xf]; 5639 u8 function_id[0x10]; 5640 5641 u8 reserved_at_60[0x20]; 5642 }; 5643 5644 struct mlx5_ifc_query_nic_vport_context_out_bits { 5645 u8 status[0x8]; 5646 u8 reserved_at_8[0x18]; 5647 5648 u8 syndrome[0x20]; 5649 5650 u8 reserved_at_40[0x40]; 5651 5652 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 5653 }; 5654 5655 struct mlx5_ifc_query_nic_vport_context_in_bits { 5656 u8 opcode[0x10]; 5657 u8 reserved_at_10[0x10]; 5658 5659 u8 reserved_at_20[0x10]; 5660 u8 op_mod[0x10]; 5661 5662 u8 other_vport[0x1]; 5663 u8 reserved_at_41[0xf]; 5664 u8 vport_number[0x10]; 5665 5666 u8 reserved_at_60[0x5]; 5667 u8 allowed_list_type[0x3]; 5668 u8 reserved_at_68[0x18]; 5669 }; 5670 5671 struct mlx5_ifc_query_mkey_out_bits { 5672 u8 status[0x8]; 5673 u8 reserved_at_8[0x18]; 5674 5675 u8 syndrome[0x20]; 5676 5677 u8 reserved_at_40[0x40]; 5678 5679 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 5680 5681 u8 reserved_at_280[0x600]; 5682 5683 u8 bsf0_klm0_pas_mtt0_1[16][0x8]; 5684 5685 u8 bsf1_klm1_pas_mtt2_3[16][0x8]; 5686 }; 5687 5688 struct mlx5_ifc_query_mkey_in_bits { 5689 u8 opcode[0x10]; 5690 u8 reserved_at_10[0x10]; 5691 5692 u8 reserved_at_20[0x10]; 5693 u8 op_mod[0x10]; 5694 5695 u8 reserved_at_40[0x8]; 5696 u8 mkey_index[0x18]; 5697 5698 u8 pg_access[0x1]; 5699 u8 reserved_at_61[0x1f]; 5700 }; 5701 5702 struct mlx5_ifc_query_mad_demux_out_bits { 5703 u8 status[0x8]; 5704 u8 reserved_at_8[0x18]; 5705 5706 u8 syndrome[0x20]; 5707 5708 u8 reserved_at_40[0x40]; 5709 5710 u8 mad_dumux_parameters_block[0x20]; 5711 }; 5712 5713 struct mlx5_ifc_query_mad_demux_in_bits { 5714 u8 opcode[0x10]; 5715 u8 reserved_at_10[0x10]; 5716 5717 u8 reserved_at_20[0x10]; 5718 u8 op_mod[0x10]; 5719 5720 u8 reserved_at_40[0x40]; 5721 }; 5722 5723 struct mlx5_ifc_query_l2_table_entry_out_bits { 5724 u8 status[0x8]; 5725 u8 reserved_at_8[0x18]; 5726 5727 u8 syndrome[0x20]; 5728 5729 u8 reserved_at_40[0xa0]; 5730 5731 u8 reserved_at_e0[0x13]; 5732 u8 vlan_valid[0x1]; 5733 u8 vlan[0xc]; 5734 5735 struct mlx5_ifc_mac_address_layout_bits mac_address; 5736 5737 u8 reserved_at_140[0xc0]; 5738 }; 5739 5740 struct mlx5_ifc_query_l2_table_entry_in_bits { 5741 u8 opcode[0x10]; 5742 u8 reserved_at_10[0x10]; 5743 5744 u8 reserved_at_20[0x10]; 5745 u8 op_mod[0x10]; 5746 5747 u8 reserved_at_40[0x60]; 5748 5749 u8 reserved_at_a0[0x8]; 5750 u8 table_index[0x18]; 5751 5752 u8 reserved_at_c0[0x140]; 5753 }; 5754 5755 struct mlx5_ifc_query_issi_out_bits { 5756 u8 status[0x8]; 5757 u8 reserved_at_8[0x18]; 5758 5759 u8 syndrome[0x20]; 5760 5761 u8 reserved_at_40[0x10]; 5762 u8 current_issi[0x10]; 5763 5764 u8 reserved_at_60[0xa0]; 5765 5766 u8 reserved_at_100[76][0x8]; 5767 u8 supported_issi_dw0[0x20]; 5768 }; 5769 5770 struct mlx5_ifc_query_issi_in_bits { 5771 u8 opcode[0x10]; 5772 u8 reserved_at_10[0x10]; 5773 5774 u8 reserved_at_20[0x10]; 5775 u8 op_mod[0x10]; 5776 5777 u8 reserved_at_40[0x40]; 5778 }; 5779 5780 struct mlx5_ifc_set_driver_version_out_bits { 5781 u8 status[0x8]; 5782 u8 reserved_0[0x18]; 5783 5784 u8 syndrome[0x20]; 5785 u8 reserved_1[0x40]; 5786 }; 5787 5788 struct mlx5_ifc_set_driver_version_in_bits { 5789 u8 opcode[0x10]; 5790 u8 reserved_0[0x10]; 5791 5792 u8 reserved_1[0x10]; 5793 u8 op_mod[0x10]; 5794 5795 u8 reserved_2[0x40]; 5796 u8 driver_version[64][0x8]; 5797 }; 5798 5799 struct mlx5_ifc_query_hca_vport_pkey_out_bits { 5800 u8 status[0x8]; 5801 u8 reserved_at_8[0x18]; 5802 5803 u8 syndrome[0x20]; 5804 5805 u8 reserved_at_40[0x40]; 5806 5807 struct mlx5_ifc_pkey_bits pkey[]; 5808 }; 5809 5810 struct mlx5_ifc_query_hca_vport_pkey_in_bits { 5811 u8 opcode[0x10]; 5812 u8 reserved_at_10[0x10]; 5813 5814 u8 reserved_at_20[0x10]; 5815 u8 op_mod[0x10]; 5816 5817 u8 other_vport[0x1]; 5818 u8 reserved_at_41[0xb]; 5819 u8 port_num[0x4]; 5820 u8 vport_number[0x10]; 5821 5822 u8 reserved_at_60[0x10]; 5823 u8 pkey_index[0x10]; 5824 }; 5825 5826 enum { 5827 MLX5_HCA_VPORT_SEL_PORT_GUID = 1 << 0, 5828 MLX5_HCA_VPORT_SEL_NODE_GUID = 1 << 1, 5829 MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2, 5830 }; 5831 5832 struct mlx5_ifc_query_hca_vport_gid_out_bits { 5833 u8 status[0x8]; 5834 u8 reserved_at_8[0x18]; 5835 5836 u8 syndrome[0x20]; 5837 5838 u8 reserved_at_40[0x20]; 5839 5840 u8 gids_num[0x10]; 5841 u8 reserved_at_70[0x10]; 5842 5843 struct mlx5_ifc_array128_auto_bits gid[]; 5844 }; 5845 5846 struct mlx5_ifc_query_hca_vport_gid_in_bits { 5847 u8 opcode[0x10]; 5848 u8 reserved_at_10[0x10]; 5849 5850 u8 reserved_at_20[0x10]; 5851 u8 op_mod[0x10]; 5852 5853 u8 other_vport[0x1]; 5854 u8 reserved_at_41[0xb]; 5855 u8 port_num[0x4]; 5856 u8 vport_number[0x10]; 5857 5858 u8 reserved_at_60[0x10]; 5859 u8 gid_index[0x10]; 5860 }; 5861 5862 struct mlx5_ifc_query_hca_vport_context_out_bits { 5863 u8 status[0x8]; 5864 u8 reserved_at_8[0x18]; 5865 5866 u8 syndrome[0x20]; 5867 5868 u8 reserved_at_40[0x40]; 5869 5870 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 5871 }; 5872 5873 struct mlx5_ifc_query_hca_vport_context_in_bits { 5874 u8 opcode[0x10]; 5875 u8 reserved_at_10[0x10]; 5876 5877 u8 reserved_at_20[0x10]; 5878 u8 op_mod[0x10]; 5879 5880 u8 other_vport[0x1]; 5881 u8 reserved_at_41[0xb]; 5882 u8 port_num[0x4]; 5883 u8 vport_number[0x10]; 5884 5885 u8 reserved_at_60[0x20]; 5886 }; 5887 5888 struct mlx5_ifc_query_hca_cap_out_bits { 5889 u8 status[0x8]; 5890 u8 reserved_at_8[0x18]; 5891 5892 u8 syndrome[0x20]; 5893 5894 u8 reserved_at_40[0x40]; 5895 5896 union mlx5_ifc_hca_cap_union_bits capability; 5897 }; 5898 5899 struct mlx5_ifc_query_hca_cap_in_bits { 5900 u8 opcode[0x10]; 5901 u8 reserved_at_10[0x10]; 5902 5903 u8 reserved_at_20[0x10]; 5904 u8 op_mod[0x10]; 5905 5906 u8 other_function[0x1]; 5907 u8 reserved_at_41[0xf]; 5908 u8 function_id[0x10]; 5909 5910 u8 reserved_at_60[0x20]; 5911 }; 5912 5913 struct mlx5_ifc_other_hca_cap_bits { 5914 u8 roce[0x1]; 5915 u8 reserved_at_1[0x27f]; 5916 }; 5917 5918 struct mlx5_ifc_query_other_hca_cap_out_bits { 5919 u8 status[0x8]; 5920 u8 reserved_at_8[0x18]; 5921 5922 u8 syndrome[0x20]; 5923 5924 u8 reserved_at_40[0x40]; 5925 5926 struct mlx5_ifc_other_hca_cap_bits other_capability; 5927 }; 5928 5929 struct mlx5_ifc_query_other_hca_cap_in_bits { 5930 u8 opcode[0x10]; 5931 u8 reserved_at_10[0x10]; 5932 5933 u8 reserved_at_20[0x10]; 5934 u8 op_mod[0x10]; 5935 5936 u8 reserved_at_40[0x10]; 5937 u8 function_id[0x10]; 5938 5939 u8 reserved_at_60[0x20]; 5940 }; 5941 5942 struct mlx5_ifc_modify_other_hca_cap_out_bits { 5943 u8 status[0x8]; 5944 u8 reserved_at_8[0x18]; 5945 5946 u8 syndrome[0x20]; 5947 5948 u8 reserved_at_40[0x40]; 5949 }; 5950 5951 struct mlx5_ifc_modify_other_hca_cap_in_bits { 5952 u8 opcode[0x10]; 5953 u8 reserved_at_10[0x10]; 5954 5955 u8 reserved_at_20[0x10]; 5956 u8 op_mod[0x10]; 5957 5958 u8 reserved_at_40[0x10]; 5959 u8 function_id[0x10]; 5960 u8 field_select[0x20]; 5961 5962 struct mlx5_ifc_other_hca_cap_bits other_capability; 5963 }; 5964 5965 struct mlx5_ifc_flow_table_context_bits { 5966 u8 reformat_en[0x1]; 5967 u8 decap_en[0x1]; 5968 u8 sw_owner[0x1]; 5969 u8 termination_table[0x1]; 5970 u8 table_miss_action[0x4]; 5971 u8 level[0x8]; 5972 u8 reserved_at_10[0x8]; 5973 u8 log_size[0x8]; 5974 5975 u8 reserved_at_20[0x8]; 5976 u8 table_miss_id[0x18]; 5977 5978 u8 reserved_at_40[0x8]; 5979 u8 lag_master_next_table_id[0x18]; 5980 5981 u8 reserved_at_60[0x60]; 5982 5983 u8 sw_owner_icm_root_1[0x40]; 5984 5985 u8 sw_owner_icm_root_0[0x40]; 5986 5987 }; 5988 5989 struct mlx5_ifc_query_flow_table_out_bits { 5990 u8 status[0x8]; 5991 u8 reserved_at_8[0x18]; 5992 5993 u8 syndrome[0x20]; 5994 5995 u8 reserved_at_40[0x80]; 5996 5997 struct mlx5_ifc_flow_table_context_bits flow_table_context; 5998 }; 5999 6000 struct mlx5_ifc_query_flow_table_in_bits { 6001 u8 opcode[0x10]; 6002 u8 reserved_at_10[0x10]; 6003 6004 u8 reserved_at_20[0x10]; 6005 u8 op_mod[0x10]; 6006 6007 u8 reserved_at_40[0x40]; 6008 6009 u8 table_type[0x8]; 6010 u8 reserved_at_88[0x18]; 6011 6012 u8 reserved_at_a0[0x8]; 6013 u8 table_id[0x18]; 6014 6015 u8 reserved_at_c0[0x140]; 6016 }; 6017 6018 struct mlx5_ifc_query_fte_out_bits { 6019 u8 status[0x8]; 6020 u8 reserved_at_8[0x18]; 6021 6022 u8 syndrome[0x20]; 6023 6024 u8 reserved_at_40[0x1c0]; 6025 6026 struct mlx5_ifc_flow_context_bits flow_context; 6027 }; 6028 6029 struct mlx5_ifc_query_fte_in_bits { 6030 u8 opcode[0x10]; 6031 u8 reserved_at_10[0x10]; 6032 6033 u8 reserved_at_20[0x10]; 6034 u8 op_mod[0x10]; 6035 6036 u8 reserved_at_40[0x40]; 6037 6038 u8 table_type[0x8]; 6039 u8 reserved_at_88[0x18]; 6040 6041 u8 reserved_at_a0[0x8]; 6042 u8 table_id[0x18]; 6043 6044 u8 reserved_at_c0[0x40]; 6045 6046 u8 flow_index[0x20]; 6047 6048 u8 reserved_at_120[0xe0]; 6049 }; 6050 6051 struct mlx5_ifc_match_definer_format_0_bits { 6052 u8 reserved_at_0[0x100]; 6053 6054 u8 metadata_reg_c_0[0x20]; 6055 6056 u8 metadata_reg_c_1[0x20]; 6057 6058 u8 outer_dmac_47_16[0x20]; 6059 6060 u8 outer_dmac_15_0[0x10]; 6061 u8 outer_ethertype[0x10]; 6062 6063 u8 reserved_at_180[0x1]; 6064 u8 sx_sniffer[0x1]; 6065 u8 functional_lb[0x1]; 6066 u8 outer_ip_frag[0x1]; 6067 u8 outer_qp_type[0x2]; 6068 u8 outer_encap_type[0x2]; 6069 u8 port_number[0x2]; 6070 u8 outer_l3_type[0x2]; 6071 u8 outer_l4_type[0x2]; 6072 u8 outer_first_vlan_type[0x2]; 6073 u8 outer_first_vlan_prio[0x3]; 6074 u8 outer_first_vlan_cfi[0x1]; 6075 u8 outer_first_vlan_vid[0xc]; 6076 6077 u8 outer_l4_type_ext[0x4]; 6078 u8 reserved_at_1a4[0x2]; 6079 u8 outer_ipsec_layer[0x2]; 6080 u8 outer_l2_type[0x2]; 6081 u8 force_lb[0x1]; 6082 u8 outer_l2_ok[0x1]; 6083 u8 outer_l3_ok[0x1]; 6084 u8 outer_l4_ok[0x1]; 6085 u8 outer_second_vlan_type[0x2]; 6086 u8 outer_second_vlan_prio[0x3]; 6087 u8 outer_second_vlan_cfi[0x1]; 6088 u8 outer_second_vlan_vid[0xc]; 6089 6090 u8 outer_smac_47_16[0x20]; 6091 6092 u8 outer_smac_15_0[0x10]; 6093 u8 inner_ipv4_checksum_ok[0x1]; 6094 u8 inner_l4_checksum_ok[0x1]; 6095 u8 outer_ipv4_checksum_ok[0x1]; 6096 u8 outer_l4_checksum_ok[0x1]; 6097 u8 inner_l3_ok[0x1]; 6098 u8 inner_l4_ok[0x1]; 6099 u8 outer_l3_ok_duplicate[0x1]; 6100 u8 outer_l4_ok_duplicate[0x1]; 6101 u8 outer_tcp_cwr[0x1]; 6102 u8 outer_tcp_ece[0x1]; 6103 u8 outer_tcp_urg[0x1]; 6104 u8 outer_tcp_ack[0x1]; 6105 u8 outer_tcp_psh[0x1]; 6106 u8 outer_tcp_rst[0x1]; 6107 u8 outer_tcp_syn[0x1]; 6108 u8 outer_tcp_fin[0x1]; 6109 }; 6110 6111 struct mlx5_ifc_match_definer_format_22_bits { 6112 u8 reserved_at_0[0x100]; 6113 6114 u8 outer_ip_src_addr[0x20]; 6115 6116 u8 outer_ip_dest_addr[0x20]; 6117 6118 u8 outer_l4_sport[0x10]; 6119 u8 outer_l4_dport[0x10]; 6120 6121 u8 reserved_at_160[0x1]; 6122 u8 sx_sniffer[0x1]; 6123 u8 functional_lb[0x1]; 6124 u8 outer_ip_frag[0x1]; 6125 u8 outer_qp_type[0x2]; 6126 u8 outer_encap_type[0x2]; 6127 u8 port_number[0x2]; 6128 u8 outer_l3_type[0x2]; 6129 u8 outer_l4_type[0x2]; 6130 u8 outer_first_vlan_type[0x2]; 6131 u8 outer_first_vlan_prio[0x3]; 6132 u8 outer_first_vlan_cfi[0x1]; 6133 u8 outer_first_vlan_vid[0xc]; 6134 6135 u8 metadata_reg_c_0[0x20]; 6136 6137 u8 outer_dmac_47_16[0x20]; 6138 6139 u8 outer_smac_47_16[0x20]; 6140 6141 u8 outer_smac_15_0[0x10]; 6142 u8 outer_dmac_15_0[0x10]; 6143 }; 6144 6145 struct mlx5_ifc_match_definer_format_23_bits { 6146 u8 reserved_at_0[0x100]; 6147 6148 u8 inner_ip_src_addr[0x20]; 6149 6150 u8 inner_ip_dest_addr[0x20]; 6151 6152 u8 inner_l4_sport[0x10]; 6153 u8 inner_l4_dport[0x10]; 6154 6155 u8 reserved_at_160[0x1]; 6156 u8 sx_sniffer[0x1]; 6157 u8 functional_lb[0x1]; 6158 u8 inner_ip_frag[0x1]; 6159 u8 inner_qp_type[0x2]; 6160 u8 inner_encap_type[0x2]; 6161 u8 port_number[0x2]; 6162 u8 inner_l3_type[0x2]; 6163 u8 inner_l4_type[0x2]; 6164 u8 inner_first_vlan_type[0x2]; 6165 u8 inner_first_vlan_prio[0x3]; 6166 u8 inner_first_vlan_cfi[0x1]; 6167 u8 inner_first_vlan_vid[0xc]; 6168 6169 u8 tunnel_header_0[0x20]; 6170 6171 u8 inner_dmac_47_16[0x20]; 6172 6173 u8 inner_smac_47_16[0x20]; 6174 6175 u8 inner_smac_15_0[0x10]; 6176 u8 inner_dmac_15_0[0x10]; 6177 }; 6178 6179 struct mlx5_ifc_match_definer_format_29_bits { 6180 u8 reserved_at_0[0xc0]; 6181 6182 u8 outer_ip_dest_addr[0x80]; 6183 6184 u8 outer_ip_src_addr[0x80]; 6185 6186 u8 outer_l4_sport[0x10]; 6187 u8 outer_l4_dport[0x10]; 6188 6189 u8 reserved_at_1e0[0x20]; 6190 }; 6191 6192 struct mlx5_ifc_match_definer_format_30_bits { 6193 u8 reserved_at_0[0xa0]; 6194 6195 u8 outer_ip_dest_addr[0x80]; 6196 6197 u8 outer_ip_src_addr[0x80]; 6198 6199 u8 outer_dmac_47_16[0x20]; 6200 6201 u8 outer_smac_47_16[0x20]; 6202 6203 u8 outer_smac_15_0[0x10]; 6204 u8 outer_dmac_15_0[0x10]; 6205 }; 6206 6207 struct mlx5_ifc_match_definer_format_31_bits { 6208 u8 reserved_at_0[0xc0]; 6209 6210 u8 inner_ip_dest_addr[0x80]; 6211 6212 u8 inner_ip_src_addr[0x80]; 6213 6214 u8 inner_l4_sport[0x10]; 6215 u8 inner_l4_dport[0x10]; 6216 6217 u8 reserved_at_1e0[0x20]; 6218 }; 6219 6220 struct mlx5_ifc_match_definer_format_32_bits { 6221 u8 reserved_at_0[0xa0]; 6222 6223 u8 inner_ip_dest_addr[0x80]; 6224 6225 u8 inner_ip_src_addr[0x80]; 6226 6227 u8 inner_dmac_47_16[0x20]; 6228 6229 u8 inner_smac_47_16[0x20]; 6230 6231 u8 inner_smac_15_0[0x10]; 6232 u8 inner_dmac_15_0[0x10]; 6233 }; 6234 6235 enum { 6236 MLX5_IFC_DEFINER_FORMAT_ID_SELECT = 61, 6237 }; 6238 6239 #define MLX5_IFC_DEFINER_FORMAT_OFFSET_UNUSED 0x0 6240 #define MLX5_IFC_DEFINER_FORMAT_OFFSET_OUTER_ETH_PKT_LEN 0x48 6241 #define MLX5_IFC_DEFINER_DW_SELECTORS_NUM 9 6242 #define MLX5_IFC_DEFINER_BYTE_SELECTORS_NUM 8 6243 6244 struct mlx5_ifc_match_definer_match_mask_bits { 6245 u8 reserved_at_1c0[5][0x20]; 6246 u8 match_dw_8[0x20]; 6247 u8 match_dw_7[0x20]; 6248 u8 match_dw_6[0x20]; 6249 u8 match_dw_5[0x20]; 6250 u8 match_dw_4[0x20]; 6251 u8 match_dw_3[0x20]; 6252 u8 match_dw_2[0x20]; 6253 u8 match_dw_1[0x20]; 6254 u8 match_dw_0[0x20]; 6255 6256 u8 match_byte_7[0x8]; 6257 u8 match_byte_6[0x8]; 6258 u8 match_byte_5[0x8]; 6259 u8 match_byte_4[0x8]; 6260 6261 u8 match_byte_3[0x8]; 6262 u8 match_byte_2[0x8]; 6263 u8 match_byte_1[0x8]; 6264 u8 match_byte_0[0x8]; 6265 }; 6266 6267 struct mlx5_ifc_match_definer_bits { 6268 u8 modify_field_select[0x40]; 6269 6270 u8 reserved_at_40[0x40]; 6271 6272 u8 reserved_at_80[0x10]; 6273 u8 format_id[0x10]; 6274 6275 u8 reserved_at_a0[0x60]; 6276 6277 u8 format_select_dw3[0x8]; 6278 u8 format_select_dw2[0x8]; 6279 u8 format_select_dw1[0x8]; 6280 u8 format_select_dw0[0x8]; 6281 6282 u8 format_select_dw7[0x8]; 6283 u8 format_select_dw6[0x8]; 6284 u8 format_select_dw5[0x8]; 6285 u8 format_select_dw4[0x8]; 6286 6287 u8 reserved_at_100[0x18]; 6288 u8 format_select_dw8[0x8]; 6289 6290 u8 reserved_at_120[0x20]; 6291 6292 u8 format_select_byte3[0x8]; 6293 u8 format_select_byte2[0x8]; 6294 u8 format_select_byte1[0x8]; 6295 u8 format_select_byte0[0x8]; 6296 6297 u8 format_select_byte7[0x8]; 6298 u8 format_select_byte6[0x8]; 6299 u8 format_select_byte5[0x8]; 6300 u8 format_select_byte4[0x8]; 6301 6302 u8 reserved_at_180[0x40]; 6303 6304 union { 6305 struct { 6306 u8 match_mask[16][0x20]; 6307 }; 6308 struct mlx5_ifc_match_definer_match_mask_bits match_mask_format; 6309 }; 6310 }; 6311 6312 struct mlx5_ifc_general_obj_create_param_bits { 6313 u8 alias_object[0x1]; 6314 u8 reserved_at_1[0x2]; 6315 u8 log_obj_range[0x5]; 6316 u8 reserved_at_8[0x18]; 6317 }; 6318 6319 struct mlx5_ifc_general_obj_query_param_bits { 6320 u8 alias_object[0x1]; 6321 u8 obj_offset[0x1f]; 6322 }; 6323 6324 struct mlx5_ifc_general_obj_in_cmd_hdr_bits { 6325 u8 opcode[0x10]; 6326 u8 uid[0x10]; 6327 6328 u8 vhca_tunnel_id[0x10]; 6329 u8 obj_type[0x10]; 6330 6331 u8 obj_id[0x20]; 6332 6333 union { 6334 struct mlx5_ifc_general_obj_create_param_bits create; 6335 struct mlx5_ifc_general_obj_query_param_bits query; 6336 } op_param; 6337 }; 6338 6339 struct mlx5_ifc_general_obj_out_cmd_hdr_bits { 6340 u8 status[0x8]; 6341 u8 reserved_at_8[0x18]; 6342 6343 u8 syndrome[0x20]; 6344 6345 u8 obj_id[0x20]; 6346 6347 u8 reserved_at_60[0x20]; 6348 }; 6349 6350 struct mlx5_ifc_create_match_definer_in_bits { 6351 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 6352 6353 struct mlx5_ifc_match_definer_bits obj_context; 6354 }; 6355 6356 struct mlx5_ifc_create_match_definer_out_bits { 6357 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 6358 }; 6359 6360 enum { 6361 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 6362 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 6363 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 6364 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3, 6365 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_3 = 0x4, 6366 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_4 = 0x5, 6367 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_5 = 0x6, 6368 }; 6369 6370 struct mlx5_ifc_query_flow_group_out_bits { 6371 u8 status[0x8]; 6372 u8 reserved_at_8[0x18]; 6373 6374 u8 syndrome[0x20]; 6375 6376 u8 reserved_at_40[0xa0]; 6377 6378 u8 start_flow_index[0x20]; 6379 6380 u8 reserved_at_100[0x20]; 6381 6382 u8 end_flow_index[0x20]; 6383 6384 u8 reserved_at_140[0xa0]; 6385 6386 u8 reserved_at_1e0[0x18]; 6387 u8 match_criteria_enable[0x8]; 6388 6389 struct mlx5_ifc_fte_match_param_bits match_criteria; 6390 6391 u8 reserved_at_1200[0xe00]; 6392 }; 6393 6394 struct mlx5_ifc_query_flow_group_in_bits { 6395 u8 opcode[0x10]; 6396 u8 reserved_at_10[0x10]; 6397 6398 u8 reserved_at_20[0x10]; 6399 u8 op_mod[0x10]; 6400 6401 u8 reserved_at_40[0x40]; 6402 6403 u8 table_type[0x8]; 6404 u8 reserved_at_88[0x18]; 6405 6406 u8 reserved_at_a0[0x8]; 6407 u8 table_id[0x18]; 6408 6409 u8 group_id[0x20]; 6410 6411 u8 reserved_at_e0[0x120]; 6412 }; 6413 6414 struct mlx5_ifc_query_flow_counter_out_bits { 6415 u8 status[0x8]; 6416 u8 reserved_at_8[0x18]; 6417 6418 u8 syndrome[0x20]; 6419 6420 u8 reserved_at_40[0x40]; 6421 6422 struct mlx5_ifc_traffic_counter_bits flow_statistics[]; 6423 }; 6424 6425 struct mlx5_ifc_query_flow_counter_in_bits { 6426 u8 opcode[0x10]; 6427 u8 reserved_at_10[0x10]; 6428 6429 u8 reserved_at_20[0x10]; 6430 u8 op_mod[0x10]; 6431 6432 u8 reserved_at_40[0x80]; 6433 6434 u8 clear[0x1]; 6435 u8 reserved_at_c1[0xf]; 6436 u8 num_of_counters[0x10]; 6437 6438 u8 flow_counter_id[0x20]; 6439 }; 6440 6441 struct mlx5_ifc_query_esw_vport_context_out_bits { 6442 u8 status[0x8]; 6443 u8 reserved_at_8[0x18]; 6444 6445 u8 syndrome[0x20]; 6446 6447 u8 reserved_at_40[0x40]; 6448 6449 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 6450 }; 6451 6452 struct mlx5_ifc_query_esw_vport_context_in_bits { 6453 u8 opcode[0x10]; 6454 u8 reserved_at_10[0x10]; 6455 6456 u8 reserved_at_20[0x10]; 6457 u8 op_mod[0x10]; 6458 6459 u8 other_vport[0x1]; 6460 u8 reserved_at_41[0xf]; 6461 u8 vport_number[0x10]; 6462 6463 u8 reserved_at_60[0x20]; 6464 }; 6465 6466 struct mlx5_ifc_modify_esw_vport_context_out_bits { 6467 u8 status[0x8]; 6468 u8 reserved_at_8[0x18]; 6469 6470 u8 syndrome[0x20]; 6471 6472 u8 reserved_at_40[0x40]; 6473 }; 6474 6475 struct mlx5_ifc_esw_vport_context_fields_select_bits { 6476 u8 reserved_at_0[0x1b]; 6477 u8 fdb_to_vport_reg_c_id[0x1]; 6478 u8 vport_cvlan_insert[0x1]; 6479 u8 vport_svlan_insert[0x1]; 6480 u8 vport_cvlan_strip[0x1]; 6481 u8 vport_svlan_strip[0x1]; 6482 }; 6483 6484 struct mlx5_ifc_modify_esw_vport_context_in_bits { 6485 u8 opcode[0x10]; 6486 u8 reserved_at_10[0x10]; 6487 6488 u8 reserved_at_20[0x10]; 6489 u8 op_mod[0x10]; 6490 6491 u8 other_vport[0x1]; 6492 u8 reserved_at_41[0xf]; 6493 u8 vport_number[0x10]; 6494 6495 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select; 6496 6497 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 6498 }; 6499 6500 struct mlx5_ifc_query_eq_out_bits { 6501 u8 status[0x8]; 6502 u8 reserved_at_8[0x18]; 6503 6504 u8 syndrome[0x20]; 6505 6506 u8 reserved_at_40[0x40]; 6507 6508 struct mlx5_ifc_eqc_bits eq_context_entry; 6509 6510 u8 reserved_at_280[0x40]; 6511 6512 u8 event_bitmask[0x40]; 6513 6514 u8 reserved_at_300[0x580]; 6515 6516 u8 pas[][0x40]; 6517 }; 6518 6519 struct mlx5_ifc_query_eq_in_bits { 6520 u8 opcode[0x10]; 6521 u8 reserved_at_10[0x10]; 6522 6523 u8 reserved_at_20[0x10]; 6524 u8 op_mod[0x10]; 6525 6526 u8 reserved_at_40[0x18]; 6527 u8 eq_number[0x8]; 6528 6529 u8 reserved_at_60[0x20]; 6530 }; 6531 6532 struct mlx5_ifc_packet_reformat_context_in_bits { 6533 u8 reformat_type[0x8]; 6534 u8 reserved_at_8[0x4]; 6535 u8 reformat_param_0[0x4]; 6536 u8 reserved_at_10[0x6]; 6537 u8 reformat_data_size[0xa]; 6538 6539 u8 reformat_param_1[0x8]; 6540 u8 reserved_at_28[0x8]; 6541 u8 reformat_data[2][0x8]; 6542 6543 u8 more_reformat_data[][0x8]; 6544 }; 6545 6546 struct mlx5_ifc_query_packet_reformat_context_out_bits { 6547 u8 status[0x8]; 6548 u8 reserved_at_8[0x18]; 6549 6550 u8 syndrome[0x20]; 6551 6552 u8 reserved_at_40[0xa0]; 6553 6554 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context[]; 6555 }; 6556 6557 struct mlx5_ifc_query_packet_reformat_context_in_bits { 6558 u8 opcode[0x10]; 6559 u8 reserved_at_10[0x10]; 6560 6561 u8 reserved_at_20[0x10]; 6562 u8 op_mod[0x10]; 6563 6564 u8 packet_reformat_id[0x20]; 6565 6566 u8 reserved_at_60[0xa0]; 6567 }; 6568 6569 struct mlx5_ifc_alloc_packet_reformat_context_out_bits { 6570 u8 status[0x8]; 6571 u8 reserved_at_8[0x18]; 6572 6573 u8 syndrome[0x20]; 6574 6575 u8 packet_reformat_id[0x20]; 6576 6577 u8 reserved_at_60[0x20]; 6578 }; 6579 6580 enum { 6581 MLX5_REFORMAT_CONTEXT_ANCHOR_MAC_START = 0x1, 6582 MLX5_REFORMAT_CONTEXT_ANCHOR_IP_START = 0x7, 6583 MLX5_REFORMAT_CONTEXT_ANCHOR_TCP_UDP_START = 0x9, 6584 }; 6585 6586 enum mlx5_reformat_ctx_type { 6587 MLX5_REFORMAT_TYPE_L2_TO_VXLAN = 0x0, 6588 MLX5_REFORMAT_TYPE_L2_TO_NVGRE = 0x1, 6589 MLX5_REFORMAT_TYPE_L2_TO_L2_TUNNEL = 0x2, 6590 MLX5_REFORMAT_TYPE_L3_TUNNEL_TO_L2 = 0x3, 6591 MLX5_REFORMAT_TYPE_L2_TO_L3_TUNNEL = 0x4, 6592 MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_IPV4 = 0x5, 6593 MLX5_REFORMAT_TYPE_DEL_ESP_TRANSPORT = 0x8, 6594 MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_IPV6 = 0xb, 6595 MLX5_REFORMAT_TYPE_INSERT_HDR = 0xf, 6596 MLX5_REFORMAT_TYPE_REMOVE_HDR = 0x10, 6597 MLX5_REFORMAT_TYPE_ADD_MACSEC = 0x11, 6598 MLX5_REFORMAT_TYPE_DEL_MACSEC = 0x12, 6599 }; 6600 6601 struct mlx5_ifc_alloc_packet_reformat_context_in_bits { 6602 u8 opcode[0x10]; 6603 u8 reserved_at_10[0x10]; 6604 6605 u8 reserved_at_20[0x10]; 6606 u8 op_mod[0x10]; 6607 6608 u8 reserved_at_40[0xa0]; 6609 6610 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context; 6611 }; 6612 6613 struct mlx5_ifc_dealloc_packet_reformat_context_out_bits { 6614 u8 status[0x8]; 6615 u8 reserved_at_8[0x18]; 6616 6617 u8 syndrome[0x20]; 6618 6619 u8 reserved_at_40[0x40]; 6620 }; 6621 6622 struct mlx5_ifc_dealloc_packet_reformat_context_in_bits { 6623 u8 opcode[0x10]; 6624 u8 reserved_at_10[0x10]; 6625 6626 u8 reserved_20[0x10]; 6627 u8 op_mod[0x10]; 6628 6629 u8 packet_reformat_id[0x20]; 6630 6631 u8 reserved_60[0x20]; 6632 }; 6633 6634 struct mlx5_ifc_set_action_in_bits { 6635 u8 action_type[0x4]; 6636 u8 field[0xc]; 6637 u8 reserved_at_10[0x3]; 6638 u8 offset[0x5]; 6639 u8 reserved_at_18[0x3]; 6640 u8 length[0x5]; 6641 6642 u8 data[0x20]; 6643 }; 6644 6645 struct mlx5_ifc_add_action_in_bits { 6646 u8 action_type[0x4]; 6647 u8 field[0xc]; 6648 u8 reserved_at_10[0x10]; 6649 6650 u8 data[0x20]; 6651 }; 6652 6653 struct mlx5_ifc_copy_action_in_bits { 6654 u8 action_type[0x4]; 6655 u8 src_field[0xc]; 6656 u8 reserved_at_10[0x3]; 6657 u8 src_offset[0x5]; 6658 u8 reserved_at_18[0x3]; 6659 u8 length[0x5]; 6660 6661 u8 reserved_at_20[0x4]; 6662 u8 dst_field[0xc]; 6663 u8 reserved_at_30[0x3]; 6664 u8 dst_offset[0x5]; 6665 u8 reserved_at_38[0x8]; 6666 }; 6667 6668 union mlx5_ifc_set_add_copy_action_in_auto_bits { 6669 struct mlx5_ifc_set_action_in_bits set_action_in; 6670 struct mlx5_ifc_add_action_in_bits add_action_in; 6671 struct mlx5_ifc_copy_action_in_bits copy_action_in; 6672 u8 reserved_at_0[0x40]; 6673 }; 6674 6675 enum { 6676 MLX5_ACTION_TYPE_SET = 0x1, 6677 MLX5_ACTION_TYPE_ADD = 0x2, 6678 MLX5_ACTION_TYPE_COPY = 0x3, 6679 }; 6680 6681 enum { 6682 MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16 = 0x1, 6683 MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0 = 0x2, 6684 MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE = 0x3, 6685 MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16 = 0x4, 6686 MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0 = 0x5, 6687 MLX5_ACTION_IN_FIELD_OUT_IP_DSCP = 0x6, 6688 MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS = 0x7, 6689 MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT = 0x8, 6690 MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT = 0x9, 6691 MLX5_ACTION_IN_FIELD_OUT_IP_TTL = 0xa, 6692 MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT = 0xb, 6693 MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT = 0xc, 6694 MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96 = 0xd, 6695 MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64 = 0xe, 6696 MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32 = 0xf, 6697 MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0 = 0x10, 6698 MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96 = 0x11, 6699 MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64 = 0x12, 6700 MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32 = 0x13, 6701 MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0 = 0x14, 6702 MLX5_ACTION_IN_FIELD_OUT_SIPV4 = 0x15, 6703 MLX5_ACTION_IN_FIELD_OUT_DIPV4 = 0x16, 6704 MLX5_ACTION_IN_FIELD_OUT_FIRST_VID = 0x17, 6705 MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47, 6706 MLX5_ACTION_IN_FIELD_METADATA_REG_A = 0x49, 6707 MLX5_ACTION_IN_FIELD_METADATA_REG_B = 0x50, 6708 MLX5_ACTION_IN_FIELD_METADATA_REG_C_0 = 0x51, 6709 MLX5_ACTION_IN_FIELD_METADATA_REG_C_1 = 0x52, 6710 MLX5_ACTION_IN_FIELD_METADATA_REG_C_2 = 0x53, 6711 MLX5_ACTION_IN_FIELD_METADATA_REG_C_3 = 0x54, 6712 MLX5_ACTION_IN_FIELD_METADATA_REG_C_4 = 0x55, 6713 MLX5_ACTION_IN_FIELD_METADATA_REG_C_5 = 0x56, 6714 MLX5_ACTION_IN_FIELD_METADATA_REG_C_6 = 0x57, 6715 MLX5_ACTION_IN_FIELD_METADATA_REG_C_7 = 0x58, 6716 MLX5_ACTION_IN_FIELD_OUT_TCP_SEQ_NUM = 0x59, 6717 MLX5_ACTION_IN_FIELD_OUT_TCP_ACK_NUM = 0x5B, 6718 MLX5_ACTION_IN_FIELD_IPSEC_SYNDROME = 0x5D, 6719 MLX5_ACTION_IN_FIELD_OUT_EMD_47_32 = 0x6F, 6720 MLX5_ACTION_IN_FIELD_OUT_EMD_31_0 = 0x70, 6721 }; 6722 6723 struct mlx5_ifc_alloc_modify_header_context_out_bits { 6724 u8 status[0x8]; 6725 u8 reserved_at_8[0x18]; 6726 6727 u8 syndrome[0x20]; 6728 6729 u8 modify_header_id[0x20]; 6730 6731 u8 reserved_at_60[0x20]; 6732 }; 6733 6734 struct mlx5_ifc_alloc_modify_header_context_in_bits { 6735 u8 opcode[0x10]; 6736 u8 reserved_at_10[0x10]; 6737 6738 u8 reserved_at_20[0x10]; 6739 u8 op_mod[0x10]; 6740 6741 u8 reserved_at_40[0x20]; 6742 6743 u8 table_type[0x8]; 6744 u8 reserved_at_68[0x10]; 6745 u8 num_of_actions[0x8]; 6746 6747 union mlx5_ifc_set_add_copy_action_in_auto_bits actions[]; 6748 }; 6749 6750 struct mlx5_ifc_dealloc_modify_header_context_out_bits { 6751 u8 status[0x8]; 6752 u8 reserved_at_8[0x18]; 6753 6754 u8 syndrome[0x20]; 6755 6756 u8 reserved_at_40[0x40]; 6757 }; 6758 6759 struct mlx5_ifc_dealloc_modify_header_context_in_bits { 6760 u8 opcode[0x10]; 6761 u8 reserved_at_10[0x10]; 6762 6763 u8 reserved_at_20[0x10]; 6764 u8 op_mod[0x10]; 6765 6766 u8 modify_header_id[0x20]; 6767 6768 u8 reserved_at_60[0x20]; 6769 }; 6770 6771 struct mlx5_ifc_query_modify_header_context_in_bits { 6772 u8 opcode[0x10]; 6773 u8 uid[0x10]; 6774 6775 u8 reserved_at_20[0x10]; 6776 u8 op_mod[0x10]; 6777 6778 u8 modify_header_id[0x20]; 6779 6780 u8 reserved_at_60[0xa0]; 6781 }; 6782 6783 struct mlx5_ifc_query_dct_out_bits { 6784 u8 status[0x8]; 6785 u8 reserved_at_8[0x18]; 6786 6787 u8 syndrome[0x20]; 6788 6789 u8 reserved_at_40[0x40]; 6790 6791 struct mlx5_ifc_dctc_bits dct_context_entry; 6792 6793 u8 reserved_at_280[0x180]; 6794 }; 6795 6796 struct mlx5_ifc_query_dct_in_bits { 6797 u8 opcode[0x10]; 6798 u8 reserved_at_10[0x10]; 6799 6800 u8 reserved_at_20[0x10]; 6801 u8 op_mod[0x10]; 6802 6803 u8 reserved_at_40[0x8]; 6804 u8 dctn[0x18]; 6805 6806 u8 reserved_at_60[0x20]; 6807 }; 6808 6809 struct mlx5_ifc_query_cq_out_bits { 6810 u8 status[0x8]; 6811 u8 reserved_at_8[0x18]; 6812 6813 u8 syndrome[0x20]; 6814 6815 u8 reserved_at_40[0x40]; 6816 6817 struct mlx5_ifc_cqc_bits cq_context; 6818 6819 u8 reserved_at_280[0x600]; 6820 6821 u8 pas[][0x40]; 6822 }; 6823 6824 struct mlx5_ifc_query_cq_in_bits { 6825 u8 opcode[0x10]; 6826 u8 reserved_at_10[0x10]; 6827 6828 u8 reserved_at_20[0x10]; 6829 u8 op_mod[0x10]; 6830 6831 u8 reserved_at_40[0x8]; 6832 u8 cqn[0x18]; 6833 6834 u8 reserved_at_60[0x20]; 6835 }; 6836 6837 struct mlx5_ifc_query_cong_status_out_bits { 6838 u8 status[0x8]; 6839 u8 reserved_at_8[0x18]; 6840 6841 u8 syndrome[0x20]; 6842 6843 u8 reserved_at_40[0x20]; 6844 6845 u8 enable[0x1]; 6846 u8 tag_enable[0x1]; 6847 u8 reserved_at_62[0x1e]; 6848 }; 6849 6850 struct mlx5_ifc_query_cong_status_in_bits { 6851 u8 opcode[0x10]; 6852 u8 reserved_at_10[0x10]; 6853 6854 u8 reserved_at_20[0x10]; 6855 u8 op_mod[0x10]; 6856 6857 u8 reserved_at_40[0x18]; 6858 u8 priority[0x4]; 6859 u8 cong_protocol[0x4]; 6860 6861 u8 reserved_at_60[0x20]; 6862 }; 6863 6864 struct mlx5_ifc_query_cong_statistics_out_bits { 6865 u8 status[0x8]; 6866 u8 reserved_at_8[0x18]; 6867 6868 u8 syndrome[0x20]; 6869 6870 u8 reserved_at_40[0x40]; 6871 6872 u8 rp_cur_flows[0x20]; 6873 6874 u8 sum_flows[0x20]; 6875 6876 u8 rp_cnp_ignored_high[0x20]; 6877 6878 u8 rp_cnp_ignored_low[0x20]; 6879 6880 u8 rp_cnp_handled_high[0x20]; 6881 6882 u8 rp_cnp_handled_low[0x20]; 6883 6884 u8 reserved_at_140[0x100]; 6885 6886 u8 time_stamp_high[0x20]; 6887 6888 u8 time_stamp_low[0x20]; 6889 6890 u8 accumulators_period[0x20]; 6891 6892 u8 np_ecn_marked_roce_packets_high[0x20]; 6893 6894 u8 np_ecn_marked_roce_packets_low[0x20]; 6895 6896 u8 np_cnp_sent_high[0x20]; 6897 6898 u8 np_cnp_sent_low[0x20]; 6899 6900 u8 reserved_at_320[0x560]; 6901 }; 6902 6903 struct mlx5_ifc_query_cong_statistics_in_bits { 6904 u8 opcode[0x10]; 6905 u8 reserved_at_10[0x10]; 6906 6907 u8 reserved_at_20[0x10]; 6908 u8 op_mod[0x10]; 6909 6910 u8 clear[0x1]; 6911 u8 reserved_at_41[0x1f]; 6912 6913 u8 reserved_at_60[0x20]; 6914 }; 6915 6916 struct mlx5_ifc_query_cong_params_out_bits { 6917 u8 status[0x8]; 6918 u8 reserved_at_8[0x18]; 6919 6920 u8 syndrome[0x20]; 6921 6922 u8 reserved_at_40[0x40]; 6923 6924 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 6925 }; 6926 6927 struct mlx5_ifc_query_cong_params_in_bits { 6928 u8 opcode[0x10]; 6929 u8 reserved_at_10[0x10]; 6930 6931 u8 reserved_at_20[0x10]; 6932 u8 op_mod[0x10]; 6933 6934 u8 reserved_at_40[0x1c]; 6935 u8 cong_protocol[0x4]; 6936 6937 u8 reserved_at_60[0x20]; 6938 }; 6939 6940 struct mlx5_ifc_query_adapter_out_bits { 6941 u8 status[0x8]; 6942 u8 reserved_at_8[0x18]; 6943 6944 u8 syndrome[0x20]; 6945 6946 u8 reserved_at_40[0x40]; 6947 6948 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct; 6949 }; 6950 6951 struct mlx5_ifc_query_adapter_in_bits { 6952 u8 opcode[0x10]; 6953 u8 reserved_at_10[0x10]; 6954 6955 u8 reserved_at_20[0x10]; 6956 u8 op_mod[0x10]; 6957 6958 u8 reserved_at_40[0x40]; 6959 }; 6960 6961 struct mlx5_ifc_qp_2rst_out_bits { 6962 u8 status[0x8]; 6963 u8 reserved_at_8[0x18]; 6964 6965 u8 syndrome[0x20]; 6966 6967 u8 reserved_at_40[0x40]; 6968 }; 6969 6970 struct mlx5_ifc_qp_2rst_in_bits { 6971 u8 opcode[0x10]; 6972 u8 uid[0x10]; 6973 6974 u8 reserved_at_20[0x10]; 6975 u8 op_mod[0x10]; 6976 6977 u8 reserved_at_40[0x8]; 6978 u8 qpn[0x18]; 6979 6980 u8 reserved_at_60[0x20]; 6981 }; 6982 6983 struct mlx5_ifc_qp_2err_out_bits { 6984 u8 status[0x8]; 6985 u8 reserved_at_8[0x18]; 6986 6987 u8 syndrome[0x20]; 6988 6989 u8 reserved_at_40[0x40]; 6990 }; 6991 6992 struct mlx5_ifc_qp_2err_in_bits { 6993 u8 opcode[0x10]; 6994 u8 uid[0x10]; 6995 6996 u8 reserved_at_20[0x10]; 6997 u8 op_mod[0x10]; 6998 6999 u8 reserved_at_40[0x8]; 7000 u8 qpn[0x18]; 7001 7002 u8 reserved_at_60[0x20]; 7003 }; 7004 7005 struct mlx5_ifc_page_fault_resume_out_bits { 7006 u8 status[0x8]; 7007 u8 reserved_at_8[0x18]; 7008 7009 u8 syndrome[0x20]; 7010 7011 u8 reserved_at_40[0x40]; 7012 }; 7013 7014 struct mlx5_ifc_page_fault_resume_in_bits { 7015 u8 opcode[0x10]; 7016 u8 reserved_at_10[0x10]; 7017 7018 u8 reserved_at_20[0x10]; 7019 u8 op_mod[0x10]; 7020 7021 u8 error[0x1]; 7022 u8 reserved_at_41[0x4]; 7023 u8 page_fault_type[0x3]; 7024 u8 wq_number[0x18]; 7025 7026 u8 reserved_at_60[0x8]; 7027 u8 token[0x18]; 7028 }; 7029 7030 struct mlx5_ifc_nop_out_bits { 7031 u8 status[0x8]; 7032 u8 reserved_at_8[0x18]; 7033 7034 u8 syndrome[0x20]; 7035 7036 u8 reserved_at_40[0x40]; 7037 }; 7038 7039 struct mlx5_ifc_nop_in_bits { 7040 u8 opcode[0x10]; 7041 u8 reserved_at_10[0x10]; 7042 7043 u8 reserved_at_20[0x10]; 7044 u8 op_mod[0x10]; 7045 7046 u8 reserved_at_40[0x40]; 7047 }; 7048 7049 struct mlx5_ifc_modify_vport_state_out_bits { 7050 u8 status[0x8]; 7051 u8 reserved_at_8[0x18]; 7052 7053 u8 syndrome[0x20]; 7054 7055 u8 reserved_at_40[0x40]; 7056 }; 7057 7058 struct mlx5_ifc_modify_vport_state_in_bits { 7059 u8 opcode[0x10]; 7060 u8 reserved_at_10[0x10]; 7061 7062 u8 reserved_at_20[0x10]; 7063 u8 op_mod[0x10]; 7064 7065 u8 other_vport[0x1]; 7066 u8 reserved_at_41[0xf]; 7067 u8 vport_number[0x10]; 7068 7069 u8 reserved_at_60[0x18]; 7070 u8 admin_state[0x4]; 7071 u8 reserved_at_7c[0x4]; 7072 }; 7073 7074 struct mlx5_ifc_modify_tis_out_bits { 7075 u8 status[0x8]; 7076 u8 reserved_at_8[0x18]; 7077 7078 u8 syndrome[0x20]; 7079 7080 u8 reserved_at_40[0x40]; 7081 }; 7082 7083 struct mlx5_ifc_modify_tis_bitmask_bits { 7084 u8 reserved_at_0[0x20]; 7085 7086 u8 reserved_at_20[0x1d]; 7087 u8 lag_tx_port_affinity[0x1]; 7088 u8 strict_lag_tx_port_affinity[0x1]; 7089 u8 prio[0x1]; 7090 }; 7091 7092 struct mlx5_ifc_modify_tis_in_bits { 7093 u8 opcode[0x10]; 7094 u8 uid[0x10]; 7095 7096 u8 reserved_at_20[0x10]; 7097 u8 op_mod[0x10]; 7098 7099 u8 reserved_at_40[0x8]; 7100 u8 tisn[0x18]; 7101 7102 u8 reserved_at_60[0x20]; 7103 7104 struct mlx5_ifc_modify_tis_bitmask_bits bitmask; 7105 7106 u8 reserved_at_c0[0x40]; 7107 7108 struct mlx5_ifc_tisc_bits ctx; 7109 }; 7110 7111 struct mlx5_ifc_modify_tir_bitmask_bits { 7112 u8 reserved_at_0[0x20]; 7113 7114 u8 reserved_at_20[0x1b]; 7115 u8 self_lb_en[0x1]; 7116 u8 reserved_at_3c[0x1]; 7117 u8 hash[0x1]; 7118 u8 reserved_at_3e[0x1]; 7119 u8 packet_merge[0x1]; 7120 }; 7121 7122 struct mlx5_ifc_modify_tir_out_bits { 7123 u8 status[0x8]; 7124 u8 reserved_at_8[0x18]; 7125 7126 u8 syndrome[0x20]; 7127 7128 u8 reserved_at_40[0x40]; 7129 }; 7130 7131 struct mlx5_ifc_modify_tir_in_bits { 7132 u8 opcode[0x10]; 7133 u8 uid[0x10]; 7134 7135 u8 reserved_at_20[0x10]; 7136 u8 op_mod[0x10]; 7137 7138 u8 reserved_at_40[0x8]; 7139 u8 tirn[0x18]; 7140 7141 u8 reserved_at_60[0x20]; 7142 7143 struct mlx5_ifc_modify_tir_bitmask_bits bitmask; 7144 7145 u8 reserved_at_c0[0x40]; 7146 7147 struct mlx5_ifc_tirc_bits ctx; 7148 }; 7149 7150 struct mlx5_ifc_modify_sq_out_bits { 7151 u8 status[0x8]; 7152 u8 reserved_at_8[0x18]; 7153 7154 u8 syndrome[0x20]; 7155 7156 u8 reserved_at_40[0x40]; 7157 }; 7158 7159 struct mlx5_ifc_modify_sq_in_bits { 7160 u8 opcode[0x10]; 7161 u8 uid[0x10]; 7162 7163 u8 reserved_at_20[0x10]; 7164 u8 op_mod[0x10]; 7165 7166 u8 sq_state[0x4]; 7167 u8 reserved_at_44[0x4]; 7168 u8 sqn[0x18]; 7169 7170 u8 reserved_at_60[0x20]; 7171 7172 u8 modify_bitmask[0x40]; 7173 7174 u8 reserved_at_c0[0x40]; 7175 7176 struct mlx5_ifc_sqc_bits ctx; 7177 }; 7178 7179 struct mlx5_ifc_modify_scheduling_element_out_bits { 7180 u8 status[0x8]; 7181 u8 reserved_at_8[0x18]; 7182 7183 u8 syndrome[0x20]; 7184 7185 u8 reserved_at_40[0x1c0]; 7186 }; 7187 7188 enum { 7189 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1, 7190 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2, 7191 }; 7192 7193 struct mlx5_ifc_modify_scheduling_element_in_bits { 7194 u8 opcode[0x10]; 7195 u8 reserved_at_10[0x10]; 7196 7197 u8 reserved_at_20[0x10]; 7198 u8 op_mod[0x10]; 7199 7200 u8 scheduling_hierarchy[0x8]; 7201 u8 reserved_at_48[0x18]; 7202 7203 u8 scheduling_element_id[0x20]; 7204 7205 u8 reserved_at_80[0x20]; 7206 7207 u8 modify_bitmask[0x20]; 7208 7209 u8 reserved_at_c0[0x40]; 7210 7211 struct mlx5_ifc_scheduling_context_bits scheduling_context; 7212 7213 u8 reserved_at_300[0x100]; 7214 }; 7215 7216 struct mlx5_ifc_modify_rqt_out_bits { 7217 u8 status[0x8]; 7218 u8 reserved_at_8[0x18]; 7219 7220 u8 syndrome[0x20]; 7221 7222 u8 reserved_at_40[0x40]; 7223 }; 7224 7225 struct mlx5_ifc_rqt_bitmask_bits { 7226 u8 reserved_at_0[0x20]; 7227 7228 u8 reserved_at_20[0x1f]; 7229 u8 rqn_list[0x1]; 7230 }; 7231 7232 struct mlx5_ifc_modify_rqt_in_bits { 7233 u8 opcode[0x10]; 7234 u8 uid[0x10]; 7235 7236 u8 reserved_at_20[0x10]; 7237 u8 op_mod[0x10]; 7238 7239 u8 reserved_at_40[0x8]; 7240 u8 rqtn[0x18]; 7241 7242 u8 reserved_at_60[0x20]; 7243 7244 struct mlx5_ifc_rqt_bitmask_bits bitmask; 7245 7246 u8 reserved_at_c0[0x40]; 7247 7248 struct mlx5_ifc_rqtc_bits ctx; 7249 }; 7250 7251 struct mlx5_ifc_modify_rq_out_bits { 7252 u8 status[0x8]; 7253 u8 reserved_at_8[0x18]; 7254 7255 u8 syndrome[0x20]; 7256 7257 u8 reserved_at_40[0x40]; 7258 }; 7259 7260 enum { 7261 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1, 7262 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2, 7263 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3, 7264 }; 7265 7266 struct mlx5_ifc_modify_rq_in_bits { 7267 u8 opcode[0x10]; 7268 u8 uid[0x10]; 7269 7270 u8 reserved_at_20[0x10]; 7271 u8 op_mod[0x10]; 7272 7273 u8 rq_state[0x4]; 7274 u8 reserved_at_44[0x4]; 7275 u8 rqn[0x18]; 7276 7277 u8 reserved_at_60[0x20]; 7278 7279 u8 modify_bitmask[0x40]; 7280 7281 u8 reserved_at_c0[0x40]; 7282 7283 struct mlx5_ifc_rqc_bits ctx; 7284 }; 7285 7286 struct mlx5_ifc_modify_rmp_out_bits { 7287 u8 status[0x8]; 7288 u8 reserved_at_8[0x18]; 7289 7290 u8 syndrome[0x20]; 7291 7292 u8 reserved_at_40[0x40]; 7293 }; 7294 7295 struct mlx5_ifc_rmp_bitmask_bits { 7296 u8 reserved_at_0[0x20]; 7297 7298 u8 reserved_at_20[0x1f]; 7299 u8 lwm[0x1]; 7300 }; 7301 7302 struct mlx5_ifc_modify_rmp_in_bits { 7303 u8 opcode[0x10]; 7304 u8 uid[0x10]; 7305 7306 u8 reserved_at_20[0x10]; 7307 u8 op_mod[0x10]; 7308 7309 u8 rmp_state[0x4]; 7310 u8 reserved_at_44[0x4]; 7311 u8 rmpn[0x18]; 7312 7313 u8 reserved_at_60[0x20]; 7314 7315 struct mlx5_ifc_rmp_bitmask_bits bitmask; 7316 7317 u8 reserved_at_c0[0x40]; 7318 7319 struct mlx5_ifc_rmpc_bits ctx; 7320 }; 7321 7322 struct mlx5_ifc_modify_nic_vport_context_out_bits { 7323 u8 status[0x8]; 7324 u8 reserved_at_8[0x18]; 7325 7326 u8 syndrome[0x20]; 7327 7328 u8 reserved_at_40[0x40]; 7329 }; 7330 7331 struct mlx5_ifc_modify_nic_vport_field_select_bits { 7332 u8 reserved_at_0[0x12]; 7333 u8 affiliation[0x1]; 7334 u8 reserved_at_13[0x1]; 7335 u8 disable_uc_local_lb[0x1]; 7336 u8 disable_mc_local_lb[0x1]; 7337 u8 node_guid[0x1]; 7338 u8 port_guid[0x1]; 7339 u8 min_inline[0x1]; 7340 u8 mtu[0x1]; 7341 u8 change_event[0x1]; 7342 u8 promisc[0x1]; 7343 u8 permanent_address[0x1]; 7344 u8 addresses_list[0x1]; 7345 u8 roce_en[0x1]; 7346 u8 reserved_at_1f[0x1]; 7347 }; 7348 7349 struct mlx5_ifc_modify_nic_vport_context_in_bits { 7350 u8 opcode[0x10]; 7351 u8 reserved_at_10[0x10]; 7352 7353 u8 reserved_at_20[0x10]; 7354 u8 op_mod[0x10]; 7355 7356 u8 other_vport[0x1]; 7357 u8 reserved_at_41[0xf]; 7358 u8 vport_number[0x10]; 7359 7360 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select; 7361 7362 u8 reserved_at_80[0x780]; 7363 7364 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 7365 }; 7366 7367 struct mlx5_ifc_modify_hca_vport_context_out_bits { 7368 u8 status[0x8]; 7369 u8 reserved_at_8[0x18]; 7370 7371 u8 syndrome[0x20]; 7372 7373 u8 reserved_at_40[0x40]; 7374 }; 7375 7376 struct mlx5_ifc_modify_hca_vport_context_in_bits { 7377 u8 opcode[0x10]; 7378 u8 reserved_at_10[0x10]; 7379 7380 u8 reserved_at_20[0x10]; 7381 u8 op_mod[0x10]; 7382 7383 u8 other_vport[0x1]; 7384 u8 reserved_at_41[0xb]; 7385 u8 port_num[0x4]; 7386 u8 vport_number[0x10]; 7387 7388 u8 reserved_at_60[0x20]; 7389 7390 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 7391 }; 7392 7393 struct mlx5_ifc_modify_cq_out_bits { 7394 u8 status[0x8]; 7395 u8 reserved_at_8[0x18]; 7396 7397 u8 syndrome[0x20]; 7398 7399 u8 reserved_at_40[0x40]; 7400 }; 7401 7402 enum { 7403 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0, 7404 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1, 7405 }; 7406 7407 struct mlx5_ifc_modify_cq_in_bits { 7408 u8 opcode[0x10]; 7409 u8 uid[0x10]; 7410 7411 u8 reserved_at_20[0x10]; 7412 u8 op_mod[0x10]; 7413 7414 u8 reserved_at_40[0x8]; 7415 u8 cqn[0x18]; 7416 7417 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select; 7418 7419 struct mlx5_ifc_cqc_bits cq_context; 7420 7421 u8 reserved_at_280[0x60]; 7422 7423 u8 cq_umem_valid[0x1]; 7424 u8 reserved_at_2e1[0x1f]; 7425 7426 u8 reserved_at_300[0x580]; 7427 7428 u8 pas[][0x40]; 7429 }; 7430 7431 struct mlx5_ifc_modify_cong_status_out_bits { 7432 u8 status[0x8]; 7433 u8 reserved_at_8[0x18]; 7434 7435 u8 syndrome[0x20]; 7436 7437 u8 reserved_at_40[0x40]; 7438 }; 7439 7440 struct mlx5_ifc_modify_cong_status_in_bits { 7441 u8 opcode[0x10]; 7442 u8 reserved_at_10[0x10]; 7443 7444 u8 reserved_at_20[0x10]; 7445 u8 op_mod[0x10]; 7446 7447 u8 reserved_at_40[0x18]; 7448 u8 priority[0x4]; 7449 u8 cong_protocol[0x4]; 7450 7451 u8 enable[0x1]; 7452 u8 tag_enable[0x1]; 7453 u8 reserved_at_62[0x1e]; 7454 }; 7455 7456 struct mlx5_ifc_modify_cong_params_out_bits { 7457 u8 status[0x8]; 7458 u8 reserved_at_8[0x18]; 7459 7460 u8 syndrome[0x20]; 7461 7462 u8 reserved_at_40[0x40]; 7463 }; 7464 7465 struct mlx5_ifc_modify_cong_params_in_bits { 7466 u8 opcode[0x10]; 7467 u8 reserved_at_10[0x10]; 7468 7469 u8 reserved_at_20[0x10]; 7470 u8 op_mod[0x10]; 7471 7472 u8 reserved_at_40[0x1c]; 7473 u8 cong_protocol[0x4]; 7474 7475 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select; 7476 7477 u8 reserved_at_80[0x80]; 7478 7479 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 7480 }; 7481 7482 struct mlx5_ifc_manage_pages_out_bits { 7483 u8 status[0x8]; 7484 u8 reserved_at_8[0x18]; 7485 7486 u8 syndrome[0x20]; 7487 7488 u8 output_num_entries[0x20]; 7489 7490 u8 reserved_at_60[0x20]; 7491 7492 u8 pas[][0x40]; 7493 }; 7494 7495 enum { 7496 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL = 0x0, 7497 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS = 0x1, 7498 MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES = 0x2, 7499 }; 7500 7501 struct mlx5_ifc_manage_pages_in_bits { 7502 u8 opcode[0x10]; 7503 u8 reserved_at_10[0x10]; 7504 7505 u8 reserved_at_20[0x10]; 7506 u8 op_mod[0x10]; 7507 7508 u8 embedded_cpu_function[0x1]; 7509 u8 reserved_at_41[0xf]; 7510 u8 function_id[0x10]; 7511 7512 u8 input_num_entries[0x20]; 7513 7514 u8 pas[][0x40]; 7515 }; 7516 7517 struct mlx5_ifc_mad_ifc_out_bits { 7518 u8 status[0x8]; 7519 u8 reserved_at_8[0x18]; 7520 7521 u8 syndrome[0x20]; 7522 7523 u8 reserved_at_40[0x40]; 7524 7525 u8 response_mad_packet[256][0x8]; 7526 }; 7527 7528 struct mlx5_ifc_mad_ifc_in_bits { 7529 u8 opcode[0x10]; 7530 u8 reserved_at_10[0x10]; 7531 7532 u8 reserved_at_20[0x10]; 7533 u8 op_mod[0x10]; 7534 7535 u8 remote_lid[0x10]; 7536 u8 reserved_at_50[0x8]; 7537 u8 port[0x8]; 7538 7539 u8 reserved_at_60[0x20]; 7540 7541 u8 mad[256][0x8]; 7542 }; 7543 7544 struct mlx5_ifc_init_hca_out_bits { 7545 u8 status[0x8]; 7546 u8 reserved_at_8[0x18]; 7547 7548 u8 syndrome[0x20]; 7549 7550 u8 reserved_at_40[0x40]; 7551 }; 7552 7553 struct mlx5_ifc_init_hca_in_bits { 7554 u8 opcode[0x10]; 7555 u8 reserved_at_10[0x10]; 7556 7557 u8 reserved_at_20[0x10]; 7558 u8 op_mod[0x10]; 7559 7560 u8 reserved_at_40[0x20]; 7561 7562 u8 reserved_at_60[0x2]; 7563 u8 sw_vhca_id[0xe]; 7564 u8 reserved_at_70[0x10]; 7565 7566 u8 sw_owner_id[4][0x20]; 7567 }; 7568 7569 struct mlx5_ifc_init2rtr_qp_out_bits { 7570 u8 status[0x8]; 7571 u8 reserved_at_8[0x18]; 7572 7573 u8 syndrome[0x20]; 7574 7575 u8 reserved_at_40[0x20]; 7576 u8 ece[0x20]; 7577 }; 7578 7579 struct mlx5_ifc_init2rtr_qp_in_bits { 7580 u8 opcode[0x10]; 7581 u8 uid[0x10]; 7582 7583 u8 reserved_at_20[0x10]; 7584 u8 op_mod[0x10]; 7585 7586 u8 reserved_at_40[0x8]; 7587 u8 qpn[0x18]; 7588 7589 u8 reserved_at_60[0x20]; 7590 7591 u8 opt_param_mask[0x20]; 7592 7593 u8 ece[0x20]; 7594 7595 struct mlx5_ifc_qpc_bits qpc; 7596 7597 u8 reserved_at_800[0x80]; 7598 }; 7599 7600 struct mlx5_ifc_init2init_qp_out_bits { 7601 u8 status[0x8]; 7602 u8 reserved_at_8[0x18]; 7603 7604 u8 syndrome[0x20]; 7605 7606 u8 reserved_at_40[0x20]; 7607 u8 ece[0x20]; 7608 }; 7609 7610 struct mlx5_ifc_init2init_qp_in_bits { 7611 u8 opcode[0x10]; 7612 u8 uid[0x10]; 7613 7614 u8 reserved_at_20[0x10]; 7615 u8 op_mod[0x10]; 7616 7617 u8 reserved_at_40[0x8]; 7618 u8 qpn[0x18]; 7619 7620 u8 reserved_at_60[0x20]; 7621 7622 u8 opt_param_mask[0x20]; 7623 7624 u8 ece[0x20]; 7625 7626 struct mlx5_ifc_qpc_bits qpc; 7627 7628 u8 reserved_at_800[0x80]; 7629 }; 7630 7631 struct mlx5_ifc_get_dropped_packet_log_out_bits { 7632 u8 status[0x8]; 7633 u8 reserved_at_8[0x18]; 7634 7635 u8 syndrome[0x20]; 7636 7637 u8 reserved_at_40[0x40]; 7638 7639 u8 packet_headers_log[128][0x8]; 7640 7641 u8 packet_syndrome[64][0x8]; 7642 }; 7643 7644 struct mlx5_ifc_get_dropped_packet_log_in_bits { 7645 u8 opcode[0x10]; 7646 u8 reserved_at_10[0x10]; 7647 7648 u8 reserved_at_20[0x10]; 7649 u8 op_mod[0x10]; 7650 7651 u8 reserved_at_40[0x40]; 7652 }; 7653 7654 struct mlx5_ifc_gen_eqe_in_bits { 7655 u8 opcode[0x10]; 7656 u8 reserved_at_10[0x10]; 7657 7658 u8 reserved_at_20[0x10]; 7659 u8 op_mod[0x10]; 7660 7661 u8 reserved_at_40[0x18]; 7662 u8 eq_number[0x8]; 7663 7664 u8 reserved_at_60[0x20]; 7665 7666 u8 eqe[64][0x8]; 7667 }; 7668 7669 struct mlx5_ifc_gen_eq_out_bits { 7670 u8 status[0x8]; 7671 u8 reserved_at_8[0x18]; 7672 7673 u8 syndrome[0x20]; 7674 7675 u8 reserved_at_40[0x40]; 7676 }; 7677 7678 struct mlx5_ifc_enable_hca_out_bits { 7679 u8 status[0x8]; 7680 u8 reserved_at_8[0x18]; 7681 7682 u8 syndrome[0x20]; 7683 7684 u8 reserved_at_40[0x20]; 7685 }; 7686 7687 struct mlx5_ifc_enable_hca_in_bits { 7688 u8 opcode[0x10]; 7689 u8 reserved_at_10[0x10]; 7690 7691 u8 reserved_at_20[0x10]; 7692 u8 op_mod[0x10]; 7693 7694 u8 embedded_cpu_function[0x1]; 7695 u8 reserved_at_41[0xf]; 7696 u8 function_id[0x10]; 7697 7698 u8 reserved_at_60[0x20]; 7699 }; 7700 7701 struct mlx5_ifc_drain_dct_out_bits { 7702 u8 status[0x8]; 7703 u8 reserved_at_8[0x18]; 7704 7705 u8 syndrome[0x20]; 7706 7707 u8 reserved_at_40[0x40]; 7708 }; 7709 7710 struct mlx5_ifc_drain_dct_in_bits { 7711 u8 opcode[0x10]; 7712 u8 uid[0x10]; 7713 7714 u8 reserved_at_20[0x10]; 7715 u8 op_mod[0x10]; 7716 7717 u8 reserved_at_40[0x8]; 7718 u8 dctn[0x18]; 7719 7720 u8 reserved_at_60[0x20]; 7721 }; 7722 7723 struct mlx5_ifc_disable_hca_out_bits { 7724 u8 status[0x8]; 7725 u8 reserved_at_8[0x18]; 7726 7727 u8 syndrome[0x20]; 7728 7729 u8 reserved_at_40[0x20]; 7730 }; 7731 7732 struct mlx5_ifc_disable_hca_in_bits { 7733 u8 opcode[0x10]; 7734 u8 reserved_at_10[0x10]; 7735 7736 u8 reserved_at_20[0x10]; 7737 u8 op_mod[0x10]; 7738 7739 u8 embedded_cpu_function[0x1]; 7740 u8 reserved_at_41[0xf]; 7741 u8 function_id[0x10]; 7742 7743 u8 reserved_at_60[0x20]; 7744 }; 7745 7746 struct mlx5_ifc_detach_from_mcg_out_bits { 7747 u8 status[0x8]; 7748 u8 reserved_at_8[0x18]; 7749 7750 u8 syndrome[0x20]; 7751 7752 u8 reserved_at_40[0x40]; 7753 }; 7754 7755 struct mlx5_ifc_detach_from_mcg_in_bits { 7756 u8 opcode[0x10]; 7757 u8 uid[0x10]; 7758 7759 u8 reserved_at_20[0x10]; 7760 u8 op_mod[0x10]; 7761 7762 u8 reserved_at_40[0x8]; 7763 u8 qpn[0x18]; 7764 7765 u8 reserved_at_60[0x20]; 7766 7767 u8 multicast_gid[16][0x8]; 7768 }; 7769 7770 struct mlx5_ifc_destroy_xrq_out_bits { 7771 u8 status[0x8]; 7772 u8 reserved_at_8[0x18]; 7773 7774 u8 syndrome[0x20]; 7775 7776 u8 reserved_at_40[0x40]; 7777 }; 7778 7779 struct mlx5_ifc_destroy_xrq_in_bits { 7780 u8 opcode[0x10]; 7781 u8 uid[0x10]; 7782 7783 u8 reserved_at_20[0x10]; 7784 u8 op_mod[0x10]; 7785 7786 u8 reserved_at_40[0x8]; 7787 u8 xrqn[0x18]; 7788 7789 u8 reserved_at_60[0x20]; 7790 }; 7791 7792 struct mlx5_ifc_destroy_xrc_srq_out_bits { 7793 u8 status[0x8]; 7794 u8 reserved_at_8[0x18]; 7795 7796 u8 syndrome[0x20]; 7797 7798 u8 reserved_at_40[0x40]; 7799 }; 7800 7801 struct mlx5_ifc_destroy_xrc_srq_in_bits { 7802 u8 opcode[0x10]; 7803 u8 uid[0x10]; 7804 7805 u8 reserved_at_20[0x10]; 7806 u8 op_mod[0x10]; 7807 7808 u8 reserved_at_40[0x8]; 7809 u8 xrc_srqn[0x18]; 7810 7811 u8 reserved_at_60[0x20]; 7812 }; 7813 7814 struct mlx5_ifc_destroy_tis_out_bits { 7815 u8 status[0x8]; 7816 u8 reserved_at_8[0x18]; 7817 7818 u8 syndrome[0x20]; 7819 7820 u8 reserved_at_40[0x40]; 7821 }; 7822 7823 struct mlx5_ifc_destroy_tis_in_bits { 7824 u8 opcode[0x10]; 7825 u8 uid[0x10]; 7826 7827 u8 reserved_at_20[0x10]; 7828 u8 op_mod[0x10]; 7829 7830 u8 reserved_at_40[0x8]; 7831 u8 tisn[0x18]; 7832 7833 u8 reserved_at_60[0x20]; 7834 }; 7835 7836 struct mlx5_ifc_destroy_tir_out_bits { 7837 u8 status[0x8]; 7838 u8 reserved_at_8[0x18]; 7839 7840 u8 syndrome[0x20]; 7841 7842 u8 reserved_at_40[0x40]; 7843 }; 7844 7845 struct mlx5_ifc_destroy_tir_in_bits { 7846 u8 opcode[0x10]; 7847 u8 uid[0x10]; 7848 7849 u8 reserved_at_20[0x10]; 7850 u8 op_mod[0x10]; 7851 7852 u8 reserved_at_40[0x8]; 7853 u8 tirn[0x18]; 7854 7855 u8 reserved_at_60[0x20]; 7856 }; 7857 7858 struct mlx5_ifc_destroy_srq_out_bits { 7859 u8 status[0x8]; 7860 u8 reserved_at_8[0x18]; 7861 7862 u8 syndrome[0x20]; 7863 7864 u8 reserved_at_40[0x40]; 7865 }; 7866 7867 struct mlx5_ifc_destroy_srq_in_bits { 7868 u8 opcode[0x10]; 7869 u8 uid[0x10]; 7870 7871 u8 reserved_at_20[0x10]; 7872 u8 op_mod[0x10]; 7873 7874 u8 reserved_at_40[0x8]; 7875 u8 srqn[0x18]; 7876 7877 u8 reserved_at_60[0x20]; 7878 }; 7879 7880 struct mlx5_ifc_destroy_sq_out_bits { 7881 u8 status[0x8]; 7882 u8 reserved_at_8[0x18]; 7883 7884 u8 syndrome[0x20]; 7885 7886 u8 reserved_at_40[0x40]; 7887 }; 7888 7889 struct mlx5_ifc_destroy_sq_in_bits { 7890 u8 opcode[0x10]; 7891 u8 uid[0x10]; 7892 7893 u8 reserved_at_20[0x10]; 7894 u8 op_mod[0x10]; 7895 7896 u8 reserved_at_40[0x8]; 7897 u8 sqn[0x18]; 7898 7899 u8 reserved_at_60[0x20]; 7900 }; 7901 7902 struct mlx5_ifc_destroy_scheduling_element_out_bits { 7903 u8 status[0x8]; 7904 u8 reserved_at_8[0x18]; 7905 7906 u8 syndrome[0x20]; 7907 7908 u8 reserved_at_40[0x1c0]; 7909 }; 7910 7911 struct mlx5_ifc_destroy_scheduling_element_in_bits { 7912 u8 opcode[0x10]; 7913 u8 reserved_at_10[0x10]; 7914 7915 u8 reserved_at_20[0x10]; 7916 u8 op_mod[0x10]; 7917 7918 u8 scheduling_hierarchy[0x8]; 7919 u8 reserved_at_48[0x18]; 7920 7921 u8 scheduling_element_id[0x20]; 7922 7923 u8 reserved_at_80[0x180]; 7924 }; 7925 7926 struct mlx5_ifc_destroy_rqt_out_bits { 7927 u8 status[0x8]; 7928 u8 reserved_at_8[0x18]; 7929 7930 u8 syndrome[0x20]; 7931 7932 u8 reserved_at_40[0x40]; 7933 }; 7934 7935 struct mlx5_ifc_destroy_rqt_in_bits { 7936 u8 opcode[0x10]; 7937 u8 uid[0x10]; 7938 7939 u8 reserved_at_20[0x10]; 7940 u8 op_mod[0x10]; 7941 7942 u8 reserved_at_40[0x8]; 7943 u8 rqtn[0x18]; 7944 7945 u8 reserved_at_60[0x20]; 7946 }; 7947 7948 struct mlx5_ifc_destroy_rq_out_bits { 7949 u8 status[0x8]; 7950 u8 reserved_at_8[0x18]; 7951 7952 u8 syndrome[0x20]; 7953 7954 u8 reserved_at_40[0x40]; 7955 }; 7956 7957 struct mlx5_ifc_destroy_rq_in_bits { 7958 u8 opcode[0x10]; 7959 u8 uid[0x10]; 7960 7961 u8 reserved_at_20[0x10]; 7962 u8 op_mod[0x10]; 7963 7964 u8 reserved_at_40[0x8]; 7965 u8 rqn[0x18]; 7966 7967 u8 reserved_at_60[0x20]; 7968 }; 7969 7970 struct mlx5_ifc_set_delay_drop_params_in_bits { 7971 u8 opcode[0x10]; 7972 u8 reserved_at_10[0x10]; 7973 7974 u8 reserved_at_20[0x10]; 7975 u8 op_mod[0x10]; 7976 7977 u8 reserved_at_40[0x20]; 7978 7979 u8 reserved_at_60[0x10]; 7980 u8 delay_drop_timeout[0x10]; 7981 }; 7982 7983 struct mlx5_ifc_set_delay_drop_params_out_bits { 7984 u8 status[0x8]; 7985 u8 reserved_at_8[0x18]; 7986 7987 u8 syndrome[0x20]; 7988 7989 u8 reserved_at_40[0x40]; 7990 }; 7991 7992 struct mlx5_ifc_destroy_rmp_out_bits { 7993 u8 status[0x8]; 7994 u8 reserved_at_8[0x18]; 7995 7996 u8 syndrome[0x20]; 7997 7998 u8 reserved_at_40[0x40]; 7999 }; 8000 8001 struct mlx5_ifc_destroy_rmp_in_bits { 8002 u8 opcode[0x10]; 8003 u8 uid[0x10]; 8004 8005 u8 reserved_at_20[0x10]; 8006 u8 op_mod[0x10]; 8007 8008 u8 reserved_at_40[0x8]; 8009 u8 rmpn[0x18]; 8010 8011 u8 reserved_at_60[0x20]; 8012 }; 8013 8014 struct mlx5_ifc_destroy_qp_out_bits { 8015 u8 status[0x8]; 8016 u8 reserved_at_8[0x18]; 8017 8018 u8 syndrome[0x20]; 8019 8020 u8 reserved_at_40[0x40]; 8021 }; 8022 8023 struct mlx5_ifc_destroy_qp_in_bits { 8024 u8 opcode[0x10]; 8025 u8 uid[0x10]; 8026 8027 u8 reserved_at_20[0x10]; 8028 u8 op_mod[0x10]; 8029 8030 u8 reserved_at_40[0x8]; 8031 u8 qpn[0x18]; 8032 8033 u8 reserved_at_60[0x20]; 8034 }; 8035 8036 struct mlx5_ifc_destroy_psv_out_bits { 8037 u8 status[0x8]; 8038 u8 reserved_at_8[0x18]; 8039 8040 u8 syndrome[0x20]; 8041 8042 u8 reserved_at_40[0x40]; 8043 }; 8044 8045 struct mlx5_ifc_destroy_psv_in_bits { 8046 u8 opcode[0x10]; 8047 u8 reserved_at_10[0x10]; 8048 8049 u8 reserved_at_20[0x10]; 8050 u8 op_mod[0x10]; 8051 8052 u8 reserved_at_40[0x8]; 8053 u8 psvn[0x18]; 8054 8055 u8 reserved_at_60[0x20]; 8056 }; 8057 8058 struct mlx5_ifc_destroy_mkey_out_bits { 8059 u8 status[0x8]; 8060 u8 reserved_at_8[0x18]; 8061 8062 u8 syndrome[0x20]; 8063 8064 u8 reserved_at_40[0x40]; 8065 }; 8066 8067 struct mlx5_ifc_destroy_mkey_in_bits { 8068 u8 opcode[0x10]; 8069 u8 uid[0x10]; 8070 8071 u8 reserved_at_20[0x10]; 8072 u8 op_mod[0x10]; 8073 8074 u8 reserved_at_40[0x8]; 8075 u8 mkey_index[0x18]; 8076 8077 u8 reserved_at_60[0x20]; 8078 }; 8079 8080 struct mlx5_ifc_destroy_flow_table_out_bits { 8081 u8 status[0x8]; 8082 u8 reserved_at_8[0x18]; 8083 8084 u8 syndrome[0x20]; 8085 8086 u8 reserved_at_40[0x40]; 8087 }; 8088 8089 struct mlx5_ifc_destroy_flow_table_in_bits { 8090 u8 opcode[0x10]; 8091 u8 reserved_at_10[0x10]; 8092 8093 u8 reserved_at_20[0x10]; 8094 u8 op_mod[0x10]; 8095 8096 u8 other_vport[0x1]; 8097 u8 reserved_at_41[0xf]; 8098 u8 vport_number[0x10]; 8099 8100 u8 reserved_at_60[0x20]; 8101 8102 u8 table_type[0x8]; 8103 u8 reserved_at_88[0x18]; 8104 8105 u8 reserved_at_a0[0x8]; 8106 u8 table_id[0x18]; 8107 8108 u8 reserved_at_c0[0x140]; 8109 }; 8110 8111 struct mlx5_ifc_destroy_flow_group_out_bits { 8112 u8 status[0x8]; 8113 u8 reserved_at_8[0x18]; 8114 8115 u8 syndrome[0x20]; 8116 8117 u8 reserved_at_40[0x40]; 8118 }; 8119 8120 struct mlx5_ifc_destroy_flow_group_in_bits { 8121 u8 opcode[0x10]; 8122 u8 reserved_at_10[0x10]; 8123 8124 u8 reserved_at_20[0x10]; 8125 u8 op_mod[0x10]; 8126 8127 u8 other_vport[0x1]; 8128 u8 reserved_at_41[0xf]; 8129 u8 vport_number[0x10]; 8130 8131 u8 reserved_at_60[0x20]; 8132 8133 u8 table_type[0x8]; 8134 u8 reserved_at_88[0x18]; 8135 8136 u8 reserved_at_a0[0x8]; 8137 u8 table_id[0x18]; 8138 8139 u8 group_id[0x20]; 8140 8141 u8 reserved_at_e0[0x120]; 8142 }; 8143 8144 struct mlx5_ifc_destroy_eq_out_bits { 8145 u8 status[0x8]; 8146 u8 reserved_at_8[0x18]; 8147 8148 u8 syndrome[0x20]; 8149 8150 u8 reserved_at_40[0x40]; 8151 }; 8152 8153 struct mlx5_ifc_destroy_eq_in_bits { 8154 u8 opcode[0x10]; 8155 u8 reserved_at_10[0x10]; 8156 8157 u8 reserved_at_20[0x10]; 8158 u8 op_mod[0x10]; 8159 8160 u8 reserved_at_40[0x18]; 8161 u8 eq_number[0x8]; 8162 8163 u8 reserved_at_60[0x20]; 8164 }; 8165 8166 struct mlx5_ifc_destroy_dct_out_bits { 8167 u8 status[0x8]; 8168 u8 reserved_at_8[0x18]; 8169 8170 u8 syndrome[0x20]; 8171 8172 u8 reserved_at_40[0x40]; 8173 }; 8174 8175 struct mlx5_ifc_destroy_dct_in_bits { 8176 u8 opcode[0x10]; 8177 u8 uid[0x10]; 8178 8179 u8 reserved_at_20[0x10]; 8180 u8 op_mod[0x10]; 8181 8182 u8 reserved_at_40[0x8]; 8183 u8 dctn[0x18]; 8184 8185 u8 reserved_at_60[0x20]; 8186 }; 8187 8188 struct mlx5_ifc_destroy_cq_out_bits { 8189 u8 status[0x8]; 8190 u8 reserved_at_8[0x18]; 8191 8192 u8 syndrome[0x20]; 8193 8194 u8 reserved_at_40[0x40]; 8195 }; 8196 8197 struct mlx5_ifc_destroy_cq_in_bits { 8198 u8 opcode[0x10]; 8199 u8 uid[0x10]; 8200 8201 u8 reserved_at_20[0x10]; 8202 u8 op_mod[0x10]; 8203 8204 u8 reserved_at_40[0x8]; 8205 u8 cqn[0x18]; 8206 8207 u8 reserved_at_60[0x20]; 8208 }; 8209 8210 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits { 8211 u8 status[0x8]; 8212 u8 reserved_at_8[0x18]; 8213 8214 u8 syndrome[0x20]; 8215 8216 u8 reserved_at_40[0x40]; 8217 }; 8218 8219 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits { 8220 u8 opcode[0x10]; 8221 u8 reserved_at_10[0x10]; 8222 8223 u8 reserved_at_20[0x10]; 8224 u8 op_mod[0x10]; 8225 8226 u8 reserved_at_40[0x20]; 8227 8228 u8 reserved_at_60[0x10]; 8229 u8 vxlan_udp_port[0x10]; 8230 }; 8231 8232 struct mlx5_ifc_delete_l2_table_entry_out_bits { 8233 u8 status[0x8]; 8234 u8 reserved_at_8[0x18]; 8235 8236 u8 syndrome[0x20]; 8237 8238 u8 reserved_at_40[0x40]; 8239 }; 8240 8241 struct mlx5_ifc_delete_l2_table_entry_in_bits { 8242 u8 opcode[0x10]; 8243 u8 reserved_at_10[0x10]; 8244 8245 u8 reserved_at_20[0x10]; 8246 u8 op_mod[0x10]; 8247 8248 u8 reserved_at_40[0x60]; 8249 8250 u8 reserved_at_a0[0x8]; 8251 u8 table_index[0x18]; 8252 8253 u8 reserved_at_c0[0x140]; 8254 }; 8255 8256 struct mlx5_ifc_delete_fte_out_bits { 8257 u8 status[0x8]; 8258 u8 reserved_at_8[0x18]; 8259 8260 u8 syndrome[0x20]; 8261 8262 u8 reserved_at_40[0x40]; 8263 }; 8264 8265 struct mlx5_ifc_delete_fte_in_bits { 8266 u8 opcode[0x10]; 8267 u8 reserved_at_10[0x10]; 8268 8269 u8 reserved_at_20[0x10]; 8270 u8 op_mod[0x10]; 8271 8272 u8 other_vport[0x1]; 8273 u8 reserved_at_41[0xf]; 8274 u8 vport_number[0x10]; 8275 8276 u8 reserved_at_60[0x20]; 8277 8278 u8 table_type[0x8]; 8279 u8 reserved_at_88[0x18]; 8280 8281 u8 reserved_at_a0[0x8]; 8282 u8 table_id[0x18]; 8283 8284 u8 reserved_at_c0[0x40]; 8285 8286 u8 flow_index[0x20]; 8287 8288 u8 reserved_at_120[0xe0]; 8289 }; 8290 8291 struct mlx5_ifc_dealloc_xrcd_out_bits { 8292 u8 status[0x8]; 8293 u8 reserved_at_8[0x18]; 8294 8295 u8 syndrome[0x20]; 8296 8297 u8 reserved_at_40[0x40]; 8298 }; 8299 8300 struct mlx5_ifc_dealloc_xrcd_in_bits { 8301 u8 opcode[0x10]; 8302 u8 uid[0x10]; 8303 8304 u8 reserved_at_20[0x10]; 8305 u8 op_mod[0x10]; 8306 8307 u8 reserved_at_40[0x8]; 8308 u8 xrcd[0x18]; 8309 8310 u8 reserved_at_60[0x20]; 8311 }; 8312 8313 struct mlx5_ifc_dealloc_uar_out_bits { 8314 u8 status[0x8]; 8315 u8 reserved_at_8[0x18]; 8316 8317 u8 syndrome[0x20]; 8318 8319 u8 reserved_at_40[0x40]; 8320 }; 8321 8322 struct mlx5_ifc_dealloc_uar_in_bits { 8323 u8 opcode[0x10]; 8324 u8 uid[0x10]; 8325 8326 u8 reserved_at_20[0x10]; 8327 u8 op_mod[0x10]; 8328 8329 u8 reserved_at_40[0x8]; 8330 u8 uar[0x18]; 8331 8332 u8 reserved_at_60[0x20]; 8333 }; 8334 8335 struct mlx5_ifc_dealloc_transport_domain_out_bits { 8336 u8 status[0x8]; 8337 u8 reserved_at_8[0x18]; 8338 8339 u8 syndrome[0x20]; 8340 8341 u8 reserved_at_40[0x40]; 8342 }; 8343 8344 struct mlx5_ifc_dealloc_transport_domain_in_bits { 8345 u8 opcode[0x10]; 8346 u8 uid[0x10]; 8347 8348 u8 reserved_at_20[0x10]; 8349 u8 op_mod[0x10]; 8350 8351 u8 reserved_at_40[0x8]; 8352 u8 transport_domain[0x18]; 8353 8354 u8 reserved_at_60[0x20]; 8355 }; 8356 8357 struct mlx5_ifc_dealloc_q_counter_out_bits { 8358 u8 status[0x8]; 8359 u8 reserved_at_8[0x18]; 8360 8361 u8 syndrome[0x20]; 8362 8363 u8 reserved_at_40[0x40]; 8364 }; 8365 8366 struct mlx5_ifc_dealloc_q_counter_in_bits { 8367 u8 opcode[0x10]; 8368 u8 reserved_at_10[0x10]; 8369 8370 u8 reserved_at_20[0x10]; 8371 u8 op_mod[0x10]; 8372 8373 u8 reserved_at_40[0x18]; 8374 u8 counter_set_id[0x8]; 8375 8376 u8 reserved_at_60[0x20]; 8377 }; 8378 8379 struct mlx5_ifc_dealloc_pd_out_bits { 8380 u8 status[0x8]; 8381 u8 reserved_at_8[0x18]; 8382 8383 u8 syndrome[0x20]; 8384 8385 u8 reserved_at_40[0x40]; 8386 }; 8387 8388 struct mlx5_ifc_dealloc_pd_in_bits { 8389 u8 opcode[0x10]; 8390 u8 uid[0x10]; 8391 8392 u8 reserved_at_20[0x10]; 8393 u8 op_mod[0x10]; 8394 8395 u8 reserved_at_40[0x8]; 8396 u8 pd[0x18]; 8397 8398 u8 reserved_at_60[0x20]; 8399 }; 8400 8401 struct mlx5_ifc_dealloc_flow_counter_out_bits { 8402 u8 status[0x8]; 8403 u8 reserved_at_8[0x18]; 8404 8405 u8 syndrome[0x20]; 8406 8407 u8 reserved_at_40[0x40]; 8408 }; 8409 8410 struct mlx5_ifc_dealloc_flow_counter_in_bits { 8411 u8 opcode[0x10]; 8412 u8 reserved_at_10[0x10]; 8413 8414 u8 reserved_at_20[0x10]; 8415 u8 op_mod[0x10]; 8416 8417 u8 flow_counter_id[0x20]; 8418 8419 u8 reserved_at_60[0x20]; 8420 }; 8421 8422 struct mlx5_ifc_create_xrq_out_bits { 8423 u8 status[0x8]; 8424 u8 reserved_at_8[0x18]; 8425 8426 u8 syndrome[0x20]; 8427 8428 u8 reserved_at_40[0x8]; 8429 u8 xrqn[0x18]; 8430 8431 u8 reserved_at_60[0x20]; 8432 }; 8433 8434 struct mlx5_ifc_create_xrq_in_bits { 8435 u8 opcode[0x10]; 8436 u8 uid[0x10]; 8437 8438 u8 reserved_at_20[0x10]; 8439 u8 op_mod[0x10]; 8440 8441 u8 reserved_at_40[0x40]; 8442 8443 struct mlx5_ifc_xrqc_bits xrq_context; 8444 }; 8445 8446 struct mlx5_ifc_create_xrc_srq_out_bits { 8447 u8 status[0x8]; 8448 u8 reserved_at_8[0x18]; 8449 8450 u8 syndrome[0x20]; 8451 8452 u8 reserved_at_40[0x8]; 8453 u8 xrc_srqn[0x18]; 8454 8455 u8 reserved_at_60[0x20]; 8456 }; 8457 8458 struct mlx5_ifc_create_xrc_srq_in_bits { 8459 u8 opcode[0x10]; 8460 u8 uid[0x10]; 8461 8462 u8 reserved_at_20[0x10]; 8463 u8 op_mod[0x10]; 8464 8465 u8 reserved_at_40[0x40]; 8466 8467 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 8468 8469 u8 reserved_at_280[0x60]; 8470 8471 u8 xrc_srq_umem_valid[0x1]; 8472 u8 reserved_at_2e1[0x1f]; 8473 8474 u8 reserved_at_300[0x580]; 8475 8476 u8 pas[][0x40]; 8477 }; 8478 8479 struct mlx5_ifc_create_tis_out_bits { 8480 u8 status[0x8]; 8481 u8 reserved_at_8[0x18]; 8482 8483 u8 syndrome[0x20]; 8484 8485 u8 reserved_at_40[0x8]; 8486 u8 tisn[0x18]; 8487 8488 u8 reserved_at_60[0x20]; 8489 }; 8490 8491 struct mlx5_ifc_create_tis_in_bits { 8492 u8 opcode[0x10]; 8493 u8 uid[0x10]; 8494 8495 u8 reserved_at_20[0x10]; 8496 u8 op_mod[0x10]; 8497 8498 u8 reserved_at_40[0xc0]; 8499 8500 struct mlx5_ifc_tisc_bits ctx; 8501 }; 8502 8503 struct mlx5_ifc_create_tir_out_bits { 8504 u8 status[0x8]; 8505 u8 icm_address_63_40[0x18]; 8506 8507 u8 syndrome[0x20]; 8508 8509 u8 icm_address_39_32[0x8]; 8510 u8 tirn[0x18]; 8511 8512 u8 icm_address_31_0[0x20]; 8513 }; 8514 8515 struct mlx5_ifc_create_tir_in_bits { 8516 u8 opcode[0x10]; 8517 u8 uid[0x10]; 8518 8519 u8 reserved_at_20[0x10]; 8520 u8 op_mod[0x10]; 8521 8522 u8 reserved_at_40[0xc0]; 8523 8524 struct mlx5_ifc_tirc_bits ctx; 8525 }; 8526 8527 struct mlx5_ifc_create_srq_out_bits { 8528 u8 status[0x8]; 8529 u8 reserved_at_8[0x18]; 8530 8531 u8 syndrome[0x20]; 8532 8533 u8 reserved_at_40[0x8]; 8534 u8 srqn[0x18]; 8535 8536 u8 reserved_at_60[0x20]; 8537 }; 8538 8539 struct mlx5_ifc_create_srq_in_bits { 8540 u8 opcode[0x10]; 8541 u8 uid[0x10]; 8542 8543 u8 reserved_at_20[0x10]; 8544 u8 op_mod[0x10]; 8545 8546 u8 reserved_at_40[0x40]; 8547 8548 struct mlx5_ifc_srqc_bits srq_context_entry; 8549 8550 u8 reserved_at_280[0x600]; 8551 8552 u8 pas[][0x40]; 8553 }; 8554 8555 struct mlx5_ifc_create_sq_out_bits { 8556 u8 status[0x8]; 8557 u8 reserved_at_8[0x18]; 8558 8559 u8 syndrome[0x20]; 8560 8561 u8 reserved_at_40[0x8]; 8562 u8 sqn[0x18]; 8563 8564 u8 reserved_at_60[0x20]; 8565 }; 8566 8567 struct mlx5_ifc_create_sq_in_bits { 8568 u8 opcode[0x10]; 8569 u8 uid[0x10]; 8570 8571 u8 reserved_at_20[0x10]; 8572 u8 op_mod[0x10]; 8573 8574 u8 reserved_at_40[0xc0]; 8575 8576 struct mlx5_ifc_sqc_bits ctx; 8577 }; 8578 8579 struct mlx5_ifc_create_scheduling_element_out_bits { 8580 u8 status[0x8]; 8581 u8 reserved_at_8[0x18]; 8582 8583 u8 syndrome[0x20]; 8584 8585 u8 reserved_at_40[0x40]; 8586 8587 u8 scheduling_element_id[0x20]; 8588 8589 u8 reserved_at_a0[0x160]; 8590 }; 8591 8592 struct mlx5_ifc_create_scheduling_element_in_bits { 8593 u8 opcode[0x10]; 8594 u8 reserved_at_10[0x10]; 8595 8596 u8 reserved_at_20[0x10]; 8597 u8 op_mod[0x10]; 8598 8599 u8 scheduling_hierarchy[0x8]; 8600 u8 reserved_at_48[0x18]; 8601 8602 u8 reserved_at_60[0xa0]; 8603 8604 struct mlx5_ifc_scheduling_context_bits scheduling_context; 8605 8606 u8 reserved_at_300[0x100]; 8607 }; 8608 8609 struct mlx5_ifc_create_rqt_out_bits { 8610 u8 status[0x8]; 8611 u8 reserved_at_8[0x18]; 8612 8613 u8 syndrome[0x20]; 8614 8615 u8 reserved_at_40[0x8]; 8616 u8 rqtn[0x18]; 8617 8618 u8 reserved_at_60[0x20]; 8619 }; 8620 8621 struct mlx5_ifc_create_rqt_in_bits { 8622 u8 opcode[0x10]; 8623 u8 uid[0x10]; 8624 8625 u8 reserved_at_20[0x10]; 8626 u8 op_mod[0x10]; 8627 8628 u8 reserved_at_40[0xc0]; 8629 8630 struct mlx5_ifc_rqtc_bits rqt_context; 8631 }; 8632 8633 struct mlx5_ifc_create_rq_out_bits { 8634 u8 status[0x8]; 8635 u8 reserved_at_8[0x18]; 8636 8637 u8 syndrome[0x20]; 8638 8639 u8 reserved_at_40[0x8]; 8640 u8 rqn[0x18]; 8641 8642 u8 reserved_at_60[0x20]; 8643 }; 8644 8645 struct mlx5_ifc_create_rq_in_bits { 8646 u8 opcode[0x10]; 8647 u8 uid[0x10]; 8648 8649 u8 reserved_at_20[0x10]; 8650 u8 op_mod[0x10]; 8651 8652 u8 reserved_at_40[0xc0]; 8653 8654 struct mlx5_ifc_rqc_bits ctx; 8655 }; 8656 8657 struct mlx5_ifc_create_rmp_out_bits { 8658 u8 status[0x8]; 8659 u8 reserved_at_8[0x18]; 8660 8661 u8 syndrome[0x20]; 8662 8663 u8 reserved_at_40[0x8]; 8664 u8 rmpn[0x18]; 8665 8666 u8 reserved_at_60[0x20]; 8667 }; 8668 8669 struct mlx5_ifc_create_rmp_in_bits { 8670 u8 opcode[0x10]; 8671 u8 uid[0x10]; 8672 8673 u8 reserved_at_20[0x10]; 8674 u8 op_mod[0x10]; 8675 8676 u8 reserved_at_40[0xc0]; 8677 8678 struct mlx5_ifc_rmpc_bits ctx; 8679 }; 8680 8681 struct mlx5_ifc_create_qp_out_bits { 8682 u8 status[0x8]; 8683 u8 reserved_at_8[0x18]; 8684 8685 u8 syndrome[0x20]; 8686 8687 u8 reserved_at_40[0x8]; 8688 u8 qpn[0x18]; 8689 8690 u8 ece[0x20]; 8691 }; 8692 8693 struct mlx5_ifc_create_qp_in_bits { 8694 u8 opcode[0x10]; 8695 u8 uid[0x10]; 8696 8697 u8 reserved_at_20[0x10]; 8698 u8 op_mod[0x10]; 8699 8700 u8 qpc_ext[0x1]; 8701 u8 reserved_at_41[0x7]; 8702 u8 input_qpn[0x18]; 8703 8704 u8 reserved_at_60[0x20]; 8705 u8 opt_param_mask[0x20]; 8706 8707 u8 ece[0x20]; 8708 8709 struct mlx5_ifc_qpc_bits qpc; 8710 8711 u8 reserved_at_800[0x60]; 8712 8713 u8 wq_umem_valid[0x1]; 8714 u8 reserved_at_861[0x1f]; 8715 8716 u8 pas[][0x40]; 8717 }; 8718 8719 struct mlx5_ifc_create_psv_out_bits { 8720 u8 status[0x8]; 8721 u8 reserved_at_8[0x18]; 8722 8723 u8 syndrome[0x20]; 8724 8725 u8 reserved_at_40[0x40]; 8726 8727 u8 reserved_at_80[0x8]; 8728 u8 psv0_index[0x18]; 8729 8730 u8 reserved_at_a0[0x8]; 8731 u8 psv1_index[0x18]; 8732 8733 u8 reserved_at_c0[0x8]; 8734 u8 psv2_index[0x18]; 8735 8736 u8 reserved_at_e0[0x8]; 8737 u8 psv3_index[0x18]; 8738 }; 8739 8740 struct mlx5_ifc_create_psv_in_bits { 8741 u8 opcode[0x10]; 8742 u8 reserved_at_10[0x10]; 8743 8744 u8 reserved_at_20[0x10]; 8745 u8 op_mod[0x10]; 8746 8747 u8 num_psv[0x4]; 8748 u8 reserved_at_44[0x4]; 8749 u8 pd[0x18]; 8750 8751 u8 reserved_at_60[0x20]; 8752 }; 8753 8754 struct mlx5_ifc_create_mkey_out_bits { 8755 u8 status[0x8]; 8756 u8 reserved_at_8[0x18]; 8757 8758 u8 syndrome[0x20]; 8759 8760 u8 reserved_at_40[0x8]; 8761 u8 mkey_index[0x18]; 8762 8763 u8 reserved_at_60[0x20]; 8764 }; 8765 8766 struct mlx5_ifc_create_mkey_in_bits { 8767 u8 opcode[0x10]; 8768 u8 uid[0x10]; 8769 8770 u8 reserved_at_20[0x10]; 8771 u8 op_mod[0x10]; 8772 8773 u8 reserved_at_40[0x20]; 8774 8775 u8 pg_access[0x1]; 8776 u8 mkey_umem_valid[0x1]; 8777 u8 reserved_at_62[0x1e]; 8778 8779 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 8780 8781 u8 reserved_at_280[0x80]; 8782 8783 u8 translations_octword_actual_size[0x20]; 8784 8785 u8 reserved_at_320[0x560]; 8786 8787 u8 klm_pas_mtt[][0x20]; 8788 }; 8789 8790 enum { 8791 MLX5_FLOW_TABLE_TYPE_NIC_RX = 0x0, 8792 MLX5_FLOW_TABLE_TYPE_NIC_TX = 0x1, 8793 MLX5_FLOW_TABLE_TYPE_ESW_EGRESS_ACL = 0x2, 8794 MLX5_FLOW_TABLE_TYPE_ESW_INGRESS_ACL = 0x3, 8795 MLX5_FLOW_TABLE_TYPE_FDB = 0X4, 8796 MLX5_FLOW_TABLE_TYPE_SNIFFER_RX = 0X5, 8797 MLX5_FLOW_TABLE_TYPE_SNIFFER_TX = 0X6, 8798 }; 8799 8800 struct mlx5_ifc_create_flow_table_out_bits { 8801 u8 status[0x8]; 8802 u8 icm_address_63_40[0x18]; 8803 8804 u8 syndrome[0x20]; 8805 8806 u8 icm_address_39_32[0x8]; 8807 u8 table_id[0x18]; 8808 8809 u8 icm_address_31_0[0x20]; 8810 }; 8811 8812 struct mlx5_ifc_create_flow_table_in_bits { 8813 u8 opcode[0x10]; 8814 u8 uid[0x10]; 8815 8816 u8 reserved_at_20[0x10]; 8817 u8 op_mod[0x10]; 8818 8819 u8 other_vport[0x1]; 8820 u8 reserved_at_41[0xf]; 8821 u8 vport_number[0x10]; 8822 8823 u8 reserved_at_60[0x20]; 8824 8825 u8 table_type[0x8]; 8826 u8 reserved_at_88[0x18]; 8827 8828 u8 reserved_at_a0[0x20]; 8829 8830 struct mlx5_ifc_flow_table_context_bits flow_table_context; 8831 }; 8832 8833 struct mlx5_ifc_create_flow_group_out_bits { 8834 u8 status[0x8]; 8835 u8 reserved_at_8[0x18]; 8836 8837 u8 syndrome[0x20]; 8838 8839 u8 reserved_at_40[0x8]; 8840 u8 group_id[0x18]; 8841 8842 u8 reserved_at_60[0x20]; 8843 }; 8844 8845 enum { 8846 MLX5_CREATE_FLOW_GROUP_IN_GROUP_TYPE_TCAM_SUBTABLE = 0x0, 8847 MLX5_CREATE_FLOW_GROUP_IN_GROUP_TYPE_HASH_SPLIT = 0x1, 8848 }; 8849 8850 enum { 8851 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 8852 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 8853 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 8854 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3, 8855 }; 8856 8857 struct mlx5_ifc_create_flow_group_in_bits { 8858 u8 opcode[0x10]; 8859 u8 reserved_at_10[0x10]; 8860 8861 u8 reserved_at_20[0x10]; 8862 u8 op_mod[0x10]; 8863 8864 u8 other_vport[0x1]; 8865 u8 reserved_at_41[0xf]; 8866 u8 vport_number[0x10]; 8867 8868 u8 reserved_at_60[0x20]; 8869 8870 u8 table_type[0x8]; 8871 u8 reserved_at_88[0x4]; 8872 u8 group_type[0x4]; 8873 u8 reserved_at_90[0x10]; 8874 8875 u8 reserved_at_a0[0x8]; 8876 u8 table_id[0x18]; 8877 8878 u8 source_eswitch_owner_vhca_id_valid[0x1]; 8879 8880 u8 reserved_at_c1[0x1f]; 8881 8882 u8 start_flow_index[0x20]; 8883 8884 u8 reserved_at_100[0x20]; 8885 8886 u8 end_flow_index[0x20]; 8887 8888 u8 reserved_at_140[0x10]; 8889 u8 match_definer_id[0x10]; 8890 8891 u8 reserved_at_160[0x80]; 8892 8893 u8 reserved_at_1e0[0x18]; 8894 u8 match_criteria_enable[0x8]; 8895 8896 struct mlx5_ifc_fte_match_param_bits match_criteria; 8897 8898 u8 reserved_at_1200[0xe00]; 8899 }; 8900 8901 struct mlx5_ifc_create_eq_out_bits { 8902 u8 status[0x8]; 8903 u8 reserved_at_8[0x18]; 8904 8905 u8 syndrome[0x20]; 8906 8907 u8 reserved_at_40[0x18]; 8908 u8 eq_number[0x8]; 8909 8910 u8 reserved_at_60[0x20]; 8911 }; 8912 8913 struct mlx5_ifc_create_eq_in_bits { 8914 u8 opcode[0x10]; 8915 u8 uid[0x10]; 8916 8917 u8 reserved_at_20[0x10]; 8918 u8 op_mod[0x10]; 8919 8920 u8 reserved_at_40[0x40]; 8921 8922 struct mlx5_ifc_eqc_bits eq_context_entry; 8923 8924 u8 reserved_at_280[0x40]; 8925 8926 u8 event_bitmask[4][0x40]; 8927 8928 u8 reserved_at_3c0[0x4c0]; 8929 8930 u8 pas[][0x40]; 8931 }; 8932 8933 struct mlx5_ifc_create_dct_out_bits { 8934 u8 status[0x8]; 8935 u8 reserved_at_8[0x18]; 8936 8937 u8 syndrome[0x20]; 8938 8939 u8 reserved_at_40[0x8]; 8940 u8 dctn[0x18]; 8941 8942 u8 ece[0x20]; 8943 }; 8944 8945 struct mlx5_ifc_create_dct_in_bits { 8946 u8 opcode[0x10]; 8947 u8 uid[0x10]; 8948 8949 u8 reserved_at_20[0x10]; 8950 u8 op_mod[0x10]; 8951 8952 u8 reserved_at_40[0x40]; 8953 8954 struct mlx5_ifc_dctc_bits dct_context_entry; 8955 8956 u8 reserved_at_280[0x180]; 8957 }; 8958 8959 struct mlx5_ifc_create_cq_out_bits { 8960 u8 status[0x8]; 8961 u8 reserved_at_8[0x18]; 8962 8963 u8 syndrome[0x20]; 8964 8965 u8 reserved_at_40[0x8]; 8966 u8 cqn[0x18]; 8967 8968 u8 reserved_at_60[0x20]; 8969 }; 8970 8971 struct mlx5_ifc_create_cq_in_bits { 8972 u8 opcode[0x10]; 8973 u8 uid[0x10]; 8974 8975 u8 reserved_at_20[0x10]; 8976 u8 op_mod[0x10]; 8977 8978 u8 reserved_at_40[0x40]; 8979 8980 struct mlx5_ifc_cqc_bits cq_context; 8981 8982 u8 reserved_at_280[0x60]; 8983 8984 u8 cq_umem_valid[0x1]; 8985 u8 reserved_at_2e1[0x59f]; 8986 8987 u8 pas[][0x40]; 8988 }; 8989 8990 struct mlx5_ifc_config_int_moderation_out_bits { 8991 u8 status[0x8]; 8992 u8 reserved_at_8[0x18]; 8993 8994 u8 syndrome[0x20]; 8995 8996 u8 reserved_at_40[0x4]; 8997 u8 min_delay[0xc]; 8998 u8 int_vector[0x10]; 8999 9000 u8 reserved_at_60[0x20]; 9001 }; 9002 9003 enum { 9004 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0, 9005 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1, 9006 }; 9007 9008 struct mlx5_ifc_config_int_moderation_in_bits { 9009 u8 opcode[0x10]; 9010 u8 reserved_at_10[0x10]; 9011 9012 u8 reserved_at_20[0x10]; 9013 u8 op_mod[0x10]; 9014 9015 u8 reserved_at_40[0x4]; 9016 u8 min_delay[0xc]; 9017 u8 int_vector[0x10]; 9018 9019 u8 reserved_at_60[0x20]; 9020 }; 9021 9022 struct mlx5_ifc_attach_to_mcg_out_bits { 9023 u8 status[0x8]; 9024 u8 reserved_at_8[0x18]; 9025 9026 u8 syndrome[0x20]; 9027 9028 u8 reserved_at_40[0x40]; 9029 }; 9030 9031 struct mlx5_ifc_attach_to_mcg_in_bits { 9032 u8 opcode[0x10]; 9033 u8 uid[0x10]; 9034 9035 u8 reserved_at_20[0x10]; 9036 u8 op_mod[0x10]; 9037 9038 u8 reserved_at_40[0x8]; 9039 u8 qpn[0x18]; 9040 9041 u8 reserved_at_60[0x20]; 9042 9043 u8 multicast_gid[16][0x8]; 9044 }; 9045 9046 struct mlx5_ifc_arm_xrq_out_bits { 9047 u8 status[0x8]; 9048 u8 reserved_at_8[0x18]; 9049 9050 u8 syndrome[0x20]; 9051 9052 u8 reserved_at_40[0x40]; 9053 }; 9054 9055 struct mlx5_ifc_arm_xrq_in_bits { 9056 u8 opcode[0x10]; 9057 u8 reserved_at_10[0x10]; 9058 9059 u8 reserved_at_20[0x10]; 9060 u8 op_mod[0x10]; 9061 9062 u8 reserved_at_40[0x8]; 9063 u8 xrqn[0x18]; 9064 9065 u8 reserved_at_60[0x10]; 9066 u8 lwm[0x10]; 9067 }; 9068 9069 struct mlx5_ifc_arm_xrc_srq_out_bits { 9070 u8 status[0x8]; 9071 u8 reserved_at_8[0x18]; 9072 9073 u8 syndrome[0x20]; 9074 9075 u8 reserved_at_40[0x40]; 9076 }; 9077 9078 enum { 9079 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1, 9080 }; 9081 9082 struct mlx5_ifc_arm_xrc_srq_in_bits { 9083 u8 opcode[0x10]; 9084 u8 uid[0x10]; 9085 9086 u8 reserved_at_20[0x10]; 9087 u8 op_mod[0x10]; 9088 9089 u8 reserved_at_40[0x8]; 9090 u8 xrc_srqn[0x18]; 9091 9092 u8 reserved_at_60[0x10]; 9093 u8 lwm[0x10]; 9094 }; 9095 9096 struct mlx5_ifc_arm_rq_out_bits { 9097 u8 status[0x8]; 9098 u8 reserved_at_8[0x18]; 9099 9100 u8 syndrome[0x20]; 9101 9102 u8 reserved_at_40[0x40]; 9103 }; 9104 9105 enum { 9106 MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1, 9107 MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2, 9108 }; 9109 9110 struct mlx5_ifc_arm_rq_in_bits { 9111 u8 opcode[0x10]; 9112 u8 uid[0x10]; 9113 9114 u8 reserved_at_20[0x10]; 9115 u8 op_mod[0x10]; 9116 9117 u8 reserved_at_40[0x8]; 9118 u8 srq_number[0x18]; 9119 9120 u8 reserved_at_60[0x10]; 9121 u8 lwm[0x10]; 9122 }; 9123 9124 struct mlx5_ifc_arm_dct_out_bits { 9125 u8 status[0x8]; 9126 u8 reserved_at_8[0x18]; 9127 9128 u8 syndrome[0x20]; 9129 9130 u8 reserved_at_40[0x40]; 9131 }; 9132 9133 struct mlx5_ifc_arm_dct_in_bits { 9134 u8 opcode[0x10]; 9135 u8 reserved_at_10[0x10]; 9136 9137 u8 reserved_at_20[0x10]; 9138 u8 op_mod[0x10]; 9139 9140 u8 reserved_at_40[0x8]; 9141 u8 dct_number[0x18]; 9142 9143 u8 reserved_at_60[0x20]; 9144 }; 9145 9146 struct mlx5_ifc_alloc_xrcd_out_bits { 9147 u8 status[0x8]; 9148 u8 reserved_at_8[0x18]; 9149 9150 u8 syndrome[0x20]; 9151 9152 u8 reserved_at_40[0x8]; 9153 u8 xrcd[0x18]; 9154 9155 u8 reserved_at_60[0x20]; 9156 }; 9157 9158 struct mlx5_ifc_alloc_xrcd_in_bits { 9159 u8 opcode[0x10]; 9160 u8 uid[0x10]; 9161 9162 u8 reserved_at_20[0x10]; 9163 u8 op_mod[0x10]; 9164 9165 u8 reserved_at_40[0x40]; 9166 }; 9167 9168 struct mlx5_ifc_alloc_uar_out_bits { 9169 u8 status[0x8]; 9170 u8 reserved_at_8[0x18]; 9171 9172 u8 syndrome[0x20]; 9173 9174 u8 reserved_at_40[0x8]; 9175 u8 uar[0x18]; 9176 9177 u8 reserved_at_60[0x20]; 9178 }; 9179 9180 struct mlx5_ifc_alloc_uar_in_bits { 9181 u8 opcode[0x10]; 9182 u8 uid[0x10]; 9183 9184 u8 reserved_at_20[0x10]; 9185 u8 op_mod[0x10]; 9186 9187 u8 reserved_at_40[0x40]; 9188 }; 9189 9190 struct mlx5_ifc_alloc_transport_domain_out_bits { 9191 u8 status[0x8]; 9192 u8 reserved_at_8[0x18]; 9193 9194 u8 syndrome[0x20]; 9195 9196 u8 reserved_at_40[0x8]; 9197 u8 transport_domain[0x18]; 9198 9199 u8 reserved_at_60[0x20]; 9200 }; 9201 9202 struct mlx5_ifc_alloc_transport_domain_in_bits { 9203 u8 opcode[0x10]; 9204 u8 uid[0x10]; 9205 9206 u8 reserved_at_20[0x10]; 9207 u8 op_mod[0x10]; 9208 9209 u8 reserved_at_40[0x40]; 9210 }; 9211 9212 struct mlx5_ifc_alloc_q_counter_out_bits { 9213 u8 status[0x8]; 9214 u8 reserved_at_8[0x18]; 9215 9216 u8 syndrome[0x20]; 9217 9218 u8 reserved_at_40[0x18]; 9219 u8 counter_set_id[0x8]; 9220 9221 u8 reserved_at_60[0x20]; 9222 }; 9223 9224 struct mlx5_ifc_alloc_q_counter_in_bits { 9225 u8 opcode[0x10]; 9226 u8 uid[0x10]; 9227 9228 u8 reserved_at_20[0x10]; 9229 u8 op_mod[0x10]; 9230 9231 u8 reserved_at_40[0x40]; 9232 }; 9233 9234 struct mlx5_ifc_alloc_pd_out_bits { 9235 u8 status[0x8]; 9236 u8 reserved_at_8[0x18]; 9237 9238 u8 syndrome[0x20]; 9239 9240 u8 reserved_at_40[0x8]; 9241 u8 pd[0x18]; 9242 9243 u8 reserved_at_60[0x20]; 9244 }; 9245 9246 struct mlx5_ifc_alloc_pd_in_bits { 9247 u8 opcode[0x10]; 9248 u8 uid[0x10]; 9249 9250 u8 reserved_at_20[0x10]; 9251 u8 op_mod[0x10]; 9252 9253 u8 reserved_at_40[0x40]; 9254 }; 9255 9256 struct mlx5_ifc_alloc_flow_counter_out_bits { 9257 u8 status[0x8]; 9258 u8 reserved_at_8[0x18]; 9259 9260 u8 syndrome[0x20]; 9261 9262 u8 flow_counter_id[0x20]; 9263 9264 u8 reserved_at_60[0x20]; 9265 }; 9266 9267 struct mlx5_ifc_alloc_flow_counter_in_bits { 9268 u8 opcode[0x10]; 9269 u8 reserved_at_10[0x10]; 9270 9271 u8 reserved_at_20[0x10]; 9272 u8 op_mod[0x10]; 9273 9274 u8 reserved_at_40[0x38]; 9275 u8 flow_counter_bulk[0x8]; 9276 }; 9277 9278 struct mlx5_ifc_add_vxlan_udp_dport_out_bits { 9279 u8 status[0x8]; 9280 u8 reserved_at_8[0x18]; 9281 9282 u8 syndrome[0x20]; 9283 9284 u8 reserved_at_40[0x40]; 9285 }; 9286 9287 struct mlx5_ifc_add_vxlan_udp_dport_in_bits { 9288 u8 opcode[0x10]; 9289 u8 reserved_at_10[0x10]; 9290 9291 u8 reserved_at_20[0x10]; 9292 u8 op_mod[0x10]; 9293 9294 u8 reserved_at_40[0x20]; 9295 9296 u8 reserved_at_60[0x10]; 9297 u8 vxlan_udp_port[0x10]; 9298 }; 9299 9300 struct mlx5_ifc_set_pp_rate_limit_out_bits { 9301 u8 status[0x8]; 9302 u8 reserved_at_8[0x18]; 9303 9304 u8 syndrome[0x20]; 9305 9306 u8 reserved_at_40[0x40]; 9307 }; 9308 9309 struct mlx5_ifc_set_pp_rate_limit_context_bits { 9310 u8 rate_limit[0x20]; 9311 9312 u8 burst_upper_bound[0x20]; 9313 9314 u8 reserved_at_40[0x10]; 9315 u8 typical_packet_size[0x10]; 9316 9317 u8 reserved_at_60[0x120]; 9318 }; 9319 9320 struct mlx5_ifc_set_pp_rate_limit_in_bits { 9321 u8 opcode[0x10]; 9322 u8 uid[0x10]; 9323 9324 u8 reserved_at_20[0x10]; 9325 u8 op_mod[0x10]; 9326 9327 u8 reserved_at_40[0x10]; 9328 u8 rate_limit_index[0x10]; 9329 9330 u8 reserved_at_60[0x20]; 9331 9332 struct mlx5_ifc_set_pp_rate_limit_context_bits ctx; 9333 }; 9334 9335 struct mlx5_ifc_access_register_out_bits { 9336 u8 status[0x8]; 9337 u8 reserved_at_8[0x18]; 9338 9339 u8 syndrome[0x20]; 9340 9341 u8 reserved_at_40[0x40]; 9342 9343 u8 register_data[][0x20]; 9344 }; 9345 9346 enum { 9347 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0, 9348 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1, 9349 }; 9350 9351 struct mlx5_ifc_access_register_in_bits { 9352 u8 opcode[0x10]; 9353 u8 reserved_at_10[0x10]; 9354 9355 u8 reserved_at_20[0x10]; 9356 u8 op_mod[0x10]; 9357 9358 u8 reserved_at_40[0x10]; 9359 u8 register_id[0x10]; 9360 9361 u8 argument[0x20]; 9362 9363 u8 register_data[][0x20]; 9364 }; 9365 9366 struct mlx5_ifc_sltp_reg_bits { 9367 u8 status[0x4]; 9368 u8 version[0x4]; 9369 u8 local_port[0x8]; 9370 u8 pnat[0x2]; 9371 u8 reserved_at_12[0x2]; 9372 u8 lane[0x4]; 9373 u8 reserved_at_18[0x8]; 9374 9375 u8 reserved_at_20[0x20]; 9376 9377 u8 reserved_at_40[0x7]; 9378 u8 polarity[0x1]; 9379 u8 ob_tap0[0x8]; 9380 u8 ob_tap1[0x8]; 9381 u8 ob_tap2[0x8]; 9382 9383 u8 reserved_at_60[0xc]; 9384 u8 ob_preemp_mode[0x4]; 9385 u8 ob_reg[0x8]; 9386 u8 ob_bias[0x8]; 9387 9388 u8 reserved_at_80[0x20]; 9389 }; 9390 9391 struct mlx5_ifc_slrg_reg_bits { 9392 u8 status[0x4]; 9393 u8 version[0x4]; 9394 u8 local_port[0x8]; 9395 u8 pnat[0x2]; 9396 u8 reserved_at_12[0x2]; 9397 u8 lane[0x4]; 9398 u8 reserved_at_18[0x8]; 9399 9400 u8 time_to_link_up[0x10]; 9401 u8 reserved_at_30[0xc]; 9402 u8 grade_lane_speed[0x4]; 9403 9404 u8 grade_version[0x8]; 9405 u8 grade[0x18]; 9406 9407 u8 reserved_at_60[0x4]; 9408 u8 height_grade_type[0x4]; 9409 u8 height_grade[0x18]; 9410 9411 u8 height_dz[0x10]; 9412 u8 height_dv[0x10]; 9413 9414 u8 reserved_at_a0[0x10]; 9415 u8 height_sigma[0x10]; 9416 9417 u8 reserved_at_c0[0x20]; 9418 9419 u8 reserved_at_e0[0x4]; 9420 u8 phase_grade_type[0x4]; 9421 u8 phase_grade[0x18]; 9422 9423 u8 reserved_at_100[0x8]; 9424 u8 phase_eo_pos[0x8]; 9425 u8 reserved_at_110[0x8]; 9426 u8 phase_eo_neg[0x8]; 9427 9428 u8 ffe_set_tested[0x10]; 9429 u8 test_errors_per_lane[0x10]; 9430 }; 9431 9432 struct mlx5_ifc_pvlc_reg_bits { 9433 u8 reserved_at_0[0x8]; 9434 u8 local_port[0x8]; 9435 u8 reserved_at_10[0x10]; 9436 9437 u8 reserved_at_20[0x1c]; 9438 u8 vl_hw_cap[0x4]; 9439 9440 u8 reserved_at_40[0x1c]; 9441 u8 vl_admin[0x4]; 9442 9443 u8 reserved_at_60[0x1c]; 9444 u8 vl_operational[0x4]; 9445 }; 9446 9447 struct mlx5_ifc_pude_reg_bits { 9448 u8 swid[0x8]; 9449 u8 local_port[0x8]; 9450 u8 reserved_at_10[0x4]; 9451 u8 admin_status[0x4]; 9452 u8 reserved_at_18[0x4]; 9453 u8 oper_status[0x4]; 9454 9455 u8 reserved_at_20[0x60]; 9456 }; 9457 9458 struct mlx5_ifc_ptys_reg_bits { 9459 u8 reserved_at_0[0x1]; 9460 u8 an_disable_admin[0x1]; 9461 u8 an_disable_cap[0x1]; 9462 u8 reserved_at_3[0x5]; 9463 u8 local_port[0x8]; 9464 u8 reserved_at_10[0xd]; 9465 u8 proto_mask[0x3]; 9466 9467 u8 an_status[0x4]; 9468 u8 reserved_at_24[0xc]; 9469 u8 data_rate_oper[0x10]; 9470 9471 u8 ext_eth_proto_capability[0x20]; 9472 9473 u8 eth_proto_capability[0x20]; 9474 9475 u8 ib_link_width_capability[0x10]; 9476 u8 ib_proto_capability[0x10]; 9477 9478 u8 ext_eth_proto_admin[0x20]; 9479 9480 u8 eth_proto_admin[0x20]; 9481 9482 u8 ib_link_width_admin[0x10]; 9483 u8 ib_proto_admin[0x10]; 9484 9485 u8 ext_eth_proto_oper[0x20]; 9486 9487 u8 eth_proto_oper[0x20]; 9488 9489 u8 ib_link_width_oper[0x10]; 9490 u8 ib_proto_oper[0x10]; 9491 9492 u8 reserved_at_160[0x1c]; 9493 u8 connector_type[0x4]; 9494 9495 u8 eth_proto_lp_advertise[0x20]; 9496 9497 u8 reserved_at_1a0[0x60]; 9498 }; 9499 9500 struct mlx5_ifc_mlcr_reg_bits { 9501 u8 reserved_at_0[0x8]; 9502 u8 local_port[0x8]; 9503 u8 reserved_at_10[0x20]; 9504 9505 u8 beacon_duration[0x10]; 9506 u8 reserved_at_40[0x10]; 9507 9508 u8 beacon_remain[0x10]; 9509 }; 9510 9511 struct mlx5_ifc_ptas_reg_bits { 9512 u8 reserved_at_0[0x20]; 9513 9514 u8 algorithm_options[0x10]; 9515 u8 reserved_at_30[0x4]; 9516 u8 repetitions_mode[0x4]; 9517 u8 num_of_repetitions[0x8]; 9518 9519 u8 grade_version[0x8]; 9520 u8 height_grade_type[0x4]; 9521 u8 phase_grade_type[0x4]; 9522 u8 height_grade_weight[0x8]; 9523 u8 phase_grade_weight[0x8]; 9524 9525 u8 gisim_measure_bits[0x10]; 9526 u8 adaptive_tap_measure_bits[0x10]; 9527 9528 u8 ber_bath_high_error_threshold[0x10]; 9529 u8 ber_bath_mid_error_threshold[0x10]; 9530 9531 u8 ber_bath_low_error_threshold[0x10]; 9532 u8 one_ratio_high_threshold[0x10]; 9533 9534 u8 one_ratio_high_mid_threshold[0x10]; 9535 u8 one_ratio_low_mid_threshold[0x10]; 9536 9537 u8 one_ratio_low_threshold[0x10]; 9538 u8 ndeo_error_threshold[0x10]; 9539 9540 u8 mixer_offset_step_size[0x10]; 9541 u8 reserved_at_110[0x8]; 9542 u8 mix90_phase_for_voltage_bath[0x8]; 9543 9544 u8 mixer_offset_start[0x10]; 9545 u8 mixer_offset_end[0x10]; 9546 9547 u8 reserved_at_140[0x15]; 9548 u8 ber_test_time[0xb]; 9549 }; 9550 9551 struct mlx5_ifc_pspa_reg_bits { 9552 u8 swid[0x8]; 9553 u8 local_port[0x8]; 9554 u8 sub_port[0x8]; 9555 u8 reserved_at_18[0x8]; 9556 9557 u8 reserved_at_20[0x20]; 9558 }; 9559 9560 struct mlx5_ifc_pqdr_reg_bits { 9561 u8 reserved_at_0[0x8]; 9562 u8 local_port[0x8]; 9563 u8 reserved_at_10[0x5]; 9564 u8 prio[0x3]; 9565 u8 reserved_at_18[0x6]; 9566 u8 mode[0x2]; 9567 9568 u8 reserved_at_20[0x20]; 9569 9570 u8 reserved_at_40[0x10]; 9571 u8 min_threshold[0x10]; 9572 9573 u8 reserved_at_60[0x10]; 9574 u8 max_threshold[0x10]; 9575 9576 u8 reserved_at_80[0x10]; 9577 u8 mark_probability_denominator[0x10]; 9578 9579 u8 reserved_at_a0[0x60]; 9580 }; 9581 9582 struct mlx5_ifc_ppsc_reg_bits { 9583 u8 reserved_at_0[0x8]; 9584 u8 local_port[0x8]; 9585 u8 reserved_at_10[0x10]; 9586 9587 u8 reserved_at_20[0x60]; 9588 9589 u8 reserved_at_80[0x1c]; 9590 u8 wrps_admin[0x4]; 9591 9592 u8 reserved_at_a0[0x1c]; 9593 u8 wrps_status[0x4]; 9594 9595 u8 reserved_at_c0[0x8]; 9596 u8 up_threshold[0x8]; 9597 u8 reserved_at_d0[0x8]; 9598 u8 down_threshold[0x8]; 9599 9600 u8 reserved_at_e0[0x20]; 9601 9602 u8 reserved_at_100[0x1c]; 9603 u8 srps_admin[0x4]; 9604 9605 u8 reserved_at_120[0x1c]; 9606 u8 srps_status[0x4]; 9607 9608 u8 reserved_at_140[0x40]; 9609 }; 9610 9611 struct mlx5_ifc_pplr_reg_bits { 9612 u8 reserved_at_0[0x8]; 9613 u8 local_port[0x8]; 9614 u8 reserved_at_10[0x10]; 9615 9616 u8 reserved_at_20[0x8]; 9617 u8 lb_cap[0x8]; 9618 u8 reserved_at_30[0x8]; 9619 u8 lb_en[0x8]; 9620 }; 9621 9622 struct mlx5_ifc_pplm_reg_bits { 9623 u8 reserved_at_0[0x8]; 9624 u8 local_port[0x8]; 9625 u8 reserved_at_10[0x10]; 9626 9627 u8 reserved_at_20[0x20]; 9628 9629 u8 port_profile_mode[0x8]; 9630 u8 static_port_profile[0x8]; 9631 u8 active_port_profile[0x8]; 9632 u8 reserved_at_58[0x8]; 9633 9634 u8 retransmission_active[0x8]; 9635 u8 fec_mode_active[0x18]; 9636 9637 u8 rs_fec_correction_bypass_cap[0x4]; 9638 u8 reserved_at_84[0x8]; 9639 u8 fec_override_cap_56g[0x4]; 9640 u8 fec_override_cap_100g[0x4]; 9641 u8 fec_override_cap_50g[0x4]; 9642 u8 fec_override_cap_25g[0x4]; 9643 u8 fec_override_cap_10g_40g[0x4]; 9644 9645 u8 rs_fec_correction_bypass_admin[0x4]; 9646 u8 reserved_at_a4[0x8]; 9647 u8 fec_override_admin_56g[0x4]; 9648 u8 fec_override_admin_100g[0x4]; 9649 u8 fec_override_admin_50g[0x4]; 9650 u8 fec_override_admin_25g[0x4]; 9651 u8 fec_override_admin_10g_40g[0x4]; 9652 9653 u8 fec_override_cap_400g_8x[0x10]; 9654 u8 fec_override_cap_200g_4x[0x10]; 9655 9656 u8 fec_override_cap_100g_2x[0x10]; 9657 u8 fec_override_cap_50g_1x[0x10]; 9658 9659 u8 fec_override_admin_400g_8x[0x10]; 9660 u8 fec_override_admin_200g_4x[0x10]; 9661 9662 u8 fec_override_admin_100g_2x[0x10]; 9663 u8 fec_override_admin_50g_1x[0x10]; 9664 9665 u8 reserved_at_140[0x140]; 9666 }; 9667 9668 struct mlx5_ifc_ppcnt_reg_bits { 9669 u8 swid[0x8]; 9670 u8 local_port[0x8]; 9671 u8 pnat[0x2]; 9672 u8 reserved_at_12[0x8]; 9673 u8 grp[0x6]; 9674 9675 u8 clr[0x1]; 9676 u8 reserved_at_21[0x1c]; 9677 u8 prio_tc[0x3]; 9678 9679 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set; 9680 }; 9681 9682 struct mlx5_ifc_mpein_reg_bits { 9683 u8 reserved_at_0[0x2]; 9684 u8 depth[0x6]; 9685 u8 pcie_index[0x8]; 9686 u8 node[0x8]; 9687 u8 reserved_at_18[0x8]; 9688 9689 u8 capability_mask[0x20]; 9690 9691 u8 reserved_at_40[0x8]; 9692 u8 link_width_enabled[0x8]; 9693 u8 link_speed_enabled[0x10]; 9694 9695 u8 lane0_physical_position[0x8]; 9696 u8 link_width_active[0x8]; 9697 u8 link_speed_active[0x10]; 9698 9699 u8 num_of_pfs[0x10]; 9700 u8 num_of_vfs[0x10]; 9701 9702 u8 bdf0[0x10]; 9703 u8 reserved_at_b0[0x10]; 9704 9705 u8 max_read_request_size[0x4]; 9706 u8 max_payload_size[0x4]; 9707 u8 reserved_at_c8[0x5]; 9708 u8 pwr_status[0x3]; 9709 u8 port_type[0x4]; 9710 u8 reserved_at_d4[0xb]; 9711 u8 lane_reversal[0x1]; 9712 9713 u8 reserved_at_e0[0x14]; 9714 u8 pci_power[0xc]; 9715 9716 u8 reserved_at_100[0x20]; 9717 9718 u8 device_status[0x10]; 9719 u8 port_state[0x8]; 9720 u8 reserved_at_138[0x8]; 9721 9722 u8 reserved_at_140[0x10]; 9723 u8 receiver_detect_result[0x10]; 9724 9725 u8 reserved_at_160[0x20]; 9726 }; 9727 9728 struct mlx5_ifc_mpcnt_reg_bits { 9729 u8 reserved_at_0[0x8]; 9730 u8 pcie_index[0x8]; 9731 u8 reserved_at_10[0xa]; 9732 u8 grp[0x6]; 9733 9734 u8 clr[0x1]; 9735 u8 reserved_at_21[0x1f]; 9736 9737 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set; 9738 }; 9739 9740 struct mlx5_ifc_ppad_reg_bits { 9741 u8 reserved_at_0[0x3]; 9742 u8 single_mac[0x1]; 9743 u8 reserved_at_4[0x4]; 9744 u8 local_port[0x8]; 9745 u8 mac_47_32[0x10]; 9746 9747 u8 mac_31_0[0x20]; 9748 9749 u8 reserved_at_40[0x40]; 9750 }; 9751 9752 struct mlx5_ifc_pmtu_reg_bits { 9753 u8 reserved_at_0[0x8]; 9754 u8 local_port[0x8]; 9755 u8 reserved_at_10[0x10]; 9756 9757 u8 max_mtu[0x10]; 9758 u8 reserved_at_30[0x10]; 9759 9760 u8 admin_mtu[0x10]; 9761 u8 reserved_at_50[0x10]; 9762 9763 u8 oper_mtu[0x10]; 9764 u8 reserved_at_70[0x10]; 9765 }; 9766 9767 struct mlx5_ifc_pmpr_reg_bits { 9768 u8 reserved_at_0[0x8]; 9769 u8 module[0x8]; 9770 u8 reserved_at_10[0x10]; 9771 9772 u8 reserved_at_20[0x18]; 9773 u8 attenuation_5g[0x8]; 9774 9775 u8 reserved_at_40[0x18]; 9776 u8 attenuation_7g[0x8]; 9777 9778 u8 reserved_at_60[0x18]; 9779 u8 attenuation_12g[0x8]; 9780 }; 9781 9782 struct mlx5_ifc_pmpe_reg_bits { 9783 u8 reserved_at_0[0x8]; 9784 u8 module[0x8]; 9785 u8 reserved_at_10[0xc]; 9786 u8 module_status[0x4]; 9787 9788 u8 reserved_at_20[0x60]; 9789 }; 9790 9791 struct mlx5_ifc_pmpc_reg_bits { 9792 u8 module_state_updated[32][0x8]; 9793 }; 9794 9795 struct mlx5_ifc_pmlpn_reg_bits { 9796 u8 reserved_at_0[0x4]; 9797 u8 mlpn_status[0x4]; 9798 u8 local_port[0x8]; 9799 u8 reserved_at_10[0x10]; 9800 9801 u8 e[0x1]; 9802 u8 reserved_at_21[0x1f]; 9803 }; 9804 9805 struct mlx5_ifc_pmlp_reg_bits { 9806 u8 rxtx[0x1]; 9807 u8 reserved_at_1[0x7]; 9808 u8 local_port[0x8]; 9809 u8 reserved_at_10[0x8]; 9810 u8 width[0x8]; 9811 9812 u8 lane0_module_mapping[0x20]; 9813 9814 u8 lane1_module_mapping[0x20]; 9815 9816 u8 lane2_module_mapping[0x20]; 9817 9818 u8 lane3_module_mapping[0x20]; 9819 9820 u8 reserved_at_a0[0x160]; 9821 }; 9822 9823 struct mlx5_ifc_pmaos_reg_bits { 9824 u8 reserved_at_0[0x8]; 9825 u8 module[0x8]; 9826 u8 reserved_at_10[0x4]; 9827 u8 admin_status[0x4]; 9828 u8 reserved_at_18[0x4]; 9829 u8 oper_status[0x4]; 9830 9831 u8 ase[0x1]; 9832 u8 ee[0x1]; 9833 u8 reserved_at_22[0x1c]; 9834 u8 e[0x2]; 9835 9836 u8 reserved_at_40[0x40]; 9837 }; 9838 9839 struct mlx5_ifc_plpc_reg_bits { 9840 u8 reserved_at_0[0x4]; 9841 u8 profile_id[0xc]; 9842 u8 reserved_at_10[0x4]; 9843 u8 proto_mask[0x4]; 9844 u8 reserved_at_18[0x8]; 9845 9846 u8 reserved_at_20[0x10]; 9847 u8 lane_speed[0x10]; 9848 9849 u8 reserved_at_40[0x17]; 9850 u8 lpbf[0x1]; 9851 u8 fec_mode_policy[0x8]; 9852 9853 u8 retransmission_capability[0x8]; 9854 u8 fec_mode_capability[0x18]; 9855 9856 u8 retransmission_support_admin[0x8]; 9857 u8 fec_mode_support_admin[0x18]; 9858 9859 u8 retransmission_request_admin[0x8]; 9860 u8 fec_mode_request_admin[0x18]; 9861 9862 u8 reserved_at_c0[0x80]; 9863 }; 9864 9865 struct mlx5_ifc_plib_reg_bits { 9866 u8 reserved_at_0[0x8]; 9867 u8 local_port[0x8]; 9868 u8 reserved_at_10[0x8]; 9869 u8 ib_port[0x8]; 9870 9871 u8 reserved_at_20[0x60]; 9872 }; 9873 9874 struct mlx5_ifc_plbf_reg_bits { 9875 u8 reserved_at_0[0x8]; 9876 u8 local_port[0x8]; 9877 u8 reserved_at_10[0xd]; 9878 u8 lbf_mode[0x3]; 9879 9880 u8 reserved_at_20[0x20]; 9881 }; 9882 9883 struct mlx5_ifc_pipg_reg_bits { 9884 u8 reserved_at_0[0x8]; 9885 u8 local_port[0x8]; 9886 u8 reserved_at_10[0x10]; 9887 9888 u8 dic[0x1]; 9889 u8 reserved_at_21[0x19]; 9890 u8 ipg[0x4]; 9891 u8 reserved_at_3e[0x2]; 9892 }; 9893 9894 struct mlx5_ifc_pifr_reg_bits { 9895 u8 reserved_at_0[0x8]; 9896 u8 local_port[0x8]; 9897 u8 reserved_at_10[0x10]; 9898 9899 u8 reserved_at_20[0xe0]; 9900 9901 u8 port_filter[8][0x20]; 9902 9903 u8 port_filter_update_en[8][0x20]; 9904 }; 9905 9906 struct mlx5_ifc_pfcc_reg_bits { 9907 u8 reserved_at_0[0x8]; 9908 u8 local_port[0x8]; 9909 u8 reserved_at_10[0xb]; 9910 u8 ppan_mask_n[0x1]; 9911 u8 minor_stall_mask[0x1]; 9912 u8 critical_stall_mask[0x1]; 9913 u8 reserved_at_1e[0x2]; 9914 9915 u8 ppan[0x4]; 9916 u8 reserved_at_24[0x4]; 9917 u8 prio_mask_tx[0x8]; 9918 u8 reserved_at_30[0x8]; 9919 u8 prio_mask_rx[0x8]; 9920 9921 u8 pptx[0x1]; 9922 u8 aptx[0x1]; 9923 u8 pptx_mask_n[0x1]; 9924 u8 reserved_at_43[0x5]; 9925 u8 pfctx[0x8]; 9926 u8 reserved_at_50[0x10]; 9927 9928 u8 pprx[0x1]; 9929 u8 aprx[0x1]; 9930 u8 pprx_mask_n[0x1]; 9931 u8 reserved_at_63[0x5]; 9932 u8 pfcrx[0x8]; 9933 u8 reserved_at_70[0x10]; 9934 9935 u8 device_stall_minor_watermark[0x10]; 9936 u8 device_stall_critical_watermark[0x10]; 9937 9938 u8 reserved_at_a0[0x60]; 9939 }; 9940 9941 struct mlx5_ifc_pelc_reg_bits { 9942 u8 op[0x4]; 9943 u8 reserved_at_4[0x4]; 9944 u8 local_port[0x8]; 9945 u8 reserved_at_10[0x10]; 9946 9947 u8 op_admin[0x8]; 9948 u8 op_capability[0x8]; 9949 u8 op_request[0x8]; 9950 u8 op_active[0x8]; 9951 9952 u8 admin[0x40]; 9953 9954 u8 capability[0x40]; 9955 9956 u8 request[0x40]; 9957 9958 u8 active[0x40]; 9959 9960 u8 reserved_at_140[0x80]; 9961 }; 9962 9963 struct mlx5_ifc_peir_reg_bits { 9964 u8 reserved_at_0[0x8]; 9965 u8 local_port[0x8]; 9966 u8 reserved_at_10[0x10]; 9967 9968 u8 reserved_at_20[0xc]; 9969 u8 error_count[0x4]; 9970 u8 reserved_at_30[0x10]; 9971 9972 u8 reserved_at_40[0xc]; 9973 u8 lane[0x4]; 9974 u8 reserved_at_50[0x8]; 9975 u8 error_type[0x8]; 9976 }; 9977 9978 struct mlx5_ifc_mpegc_reg_bits { 9979 u8 reserved_at_0[0x30]; 9980 u8 field_select[0x10]; 9981 9982 u8 tx_overflow_sense[0x1]; 9983 u8 mark_cqe[0x1]; 9984 u8 mark_cnp[0x1]; 9985 u8 reserved_at_43[0x1b]; 9986 u8 tx_lossy_overflow_oper[0x2]; 9987 9988 u8 reserved_at_60[0x100]; 9989 }; 9990 9991 enum { 9992 MLX5_MTUTC_FREQ_ADJ_UNITS_PPB = 0x0, 9993 MLX5_MTUTC_FREQ_ADJ_UNITS_SCALED_PPM = 0x1, 9994 }; 9995 9996 enum { 9997 MLX5_MTUTC_OPERATION_SET_TIME_IMMEDIATE = 0x1, 9998 MLX5_MTUTC_OPERATION_ADJUST_TIME = 0x2, 9999 MLX5_MTUTC_OPERATION_ADJUST_FREQ_UTC = 0x3, 10000 }; 10001 10002 struct mlx5_ifc_mtutc_reg_bits { 10003 u8 reserved_at_0[0x5]; 10004 u8 freq_adj_units[0x3]; 10005 u8 reserved_at_8[0x14]; 10006 u8 operation[0x4]; 10007 10008 u8 freq_adjustment[0x20]; 10009 10010 u8 reserved_at_40[0x40]; 10011 10012 u8 utc_sec[0x20]; 10013 10014 u8 reserved_at_a0[0x2]; 10015 u8 utc_nsec[0x1e]; 10016 10017 u8 time_adjustment[0x20]; 10018 }; 10019 10020 struct mlx5_ifc_pcam_enhanced_features_bits { 10021 u8 reserved_at_0[0x68]; 10022 u8 fec_50G_per_lane_in_pplm[0x1]; 10023 u8 reserved_at_69[0x4]; 10024 u8 rx_icrc_encapsulated_counter[0x1]; 10025 u8 reserved_at_6e[0x4]; 10026 u8 ptys_extended_ethernet[0x1]; 10027 u8 reserved_at_73[0x3]; 10028 u8 pfcc_mask[0x1]; 10029 u8 reserved_at_77[0x3]; 10030 u8 per_lane_error_counters[0x1]; 10031 u8 rx_buffer_fullness_counters[0x1]; 10032 u8 ptys_connector_type[0x1]; 10033 u8 reserved_at_7d[0x1]; 10034 u8 ppcnt_discard_group[0x1]; 10035 u8 ppcnt_statistical_group[0x1]; 10036 }; 10037 10038 struct mlx5_ifc_pcam_regs_5000_to_507f_bits { 10039 u8 port_access_reg_cap_mask_127_to_96[0x20]; 10040 u8 port_access_reg_cap_mask_95_to_64[0x20]; 10041 10042 u8 port_access_reg_cap_mask_63_to_36[0x1c]; 10043 u8 pplm[0x1]; 10044 u8 port_access_reg_cap_mask_34_to_32[0x3]; 10045 10046 u8 port_access_reg_cap_mask_31_to_13[0x13]; 10047 u8 pbmc[0x1]; 10048 u8 pptb[0x1]; 10049 u8 port_access_reg_cap_mask_10_to_09[0x2]; 10050 u8 ppcnt[0x1]; 10051 u8 port_access_reg_cap_mask_07_to_00[0x8]; 10052 }; 10053 10054 struct mlx5_ifc_pcam_reg_bits { 10055 u8 reserved_at_0[0x8]; 10056 u8 feature_group[0x8]; 10057 u8 reserved_at_10[0x8]; 10058 u8 access_reg_group[0x8]; 10059 10060 u8 reserved_at_20[0x20]; 10061 10062 union { 10063 struct mlx5_ifc_pcam_regs_5000_to_507f_bits regs_5000_to_507f; 10064 u8 reserved_at_0[0x80]; 10065 } port_access_reg_cap_mask; 10066 10067 u8 reserved_at_c0[0x80]; 10068 10069 union { 10070 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features; 10071 u8 reserved_at_0[0x80]; 10072 } feature_cap_mask; 10073 10074 u8 reserved_at_1c0[0xc0]; 10075 }; 10076 10077 struct mlx5_ifc_mcam_enhanced_features_bits { 10078 u8 reserved_at_0[0x50]; 10079 u8 mtutc_freq_adj_units[0x1]; 10080 u8 mtutc_time_adjustment_extended_range[0x1]; 10081 u8 reserved_at_52[0xb]; 10082 u8 mcia_32dwords[0x1]; 10083 u8 out_pulse_duration_ns[0x1]; 10084 u8 npps_period[0x1]; 10085 u8 reserved_at_60[0xa]; 10086 u8 reset_state[0x1]; 10087 u8 ptpcyc2realtime_modify[0x1]; 10088 u8 reserved_at_6c[0x2]; 10089 u8 pci_status_and_power[0x1]; 10090 u8 reserved_at_6f[0x5]; 10091 u8 mark_tx_action_cnp[0x1]; 10092 u8 mark_tx_action_cqe[0x1]; 10093 u8 dynamic_tx_overflow[0x1]; 10094 u8 reserved_at_77[0x4]; 10095 u8 pcie_outbound_stalled[0x1]; 10096 u8 tx_overflow_buffer_pkt[0x1]; 10097 u8 mtpps_enh_out_per_adj[0x1]; 10098 u8 mtpps_fs[0x1]; 10099 u8 pcie_performance_group[0x1]; 10100 }; 10101 10102 struct mlx5_ifc_mcam_access_reg_bits { 10103 u8 reserved_at_0[0x1c]; 10104 u8 mcda[0x1]; 10105 u8 mcc[0x1]; 10106 u8 mcqi[0x1]; 10107 u8 mcqs[0x1]; 10108 10109 u8 regs_95_to_87[0x9]; 10110 u8 mpegc[0x1]; 10111 u8 mtutc[0x1]; 10112 u8 regs_84_to_68[0x11]; 10113 u8 tracer_registers[0x4]; 10114 10115 u8 regs_63_to_46[0x12]; 10116 u8 mrtc[0x1]; 10117 u8 regs_44_to_32[0xd]; 10118 10119 u8 regs_31_to_0[0x20]; 10120 }; 10121 10122 struct mlx5_ifc_mcam_access_reg_bits1 { 10123 u8 regs_127_to_96[0x20]; 10124 10125 u8 regs_95_to_64[0x20]; 10126 10127 u8 regs_63_to_32[0x20]; 10128 10129 u8 regs_31_to_0[0x20]; 10130 }; 10131 10132 struct mlx5_ifc_mcam_access_reg_bits2 { 10133 u8 regs_127_to_99[0x1d]; 10134 u8 mirc[0x1]; 10135 u8 regs_97_to_96[0x2]; 10136 10137 u8 regs_95_to_64[0x20]; 10138 10139 u8 regs_63_to_32[0x20]; 10140 10141 u8 regs_31_to_0[0x20]; 10142 }; 10143 10144 struct mlx5_ifc_mcam_reg_bits { 10145 u8 reserved_at_0[0x8]; 10146 u8 feature_group[0x8]; 10147 u8 reserved_at_10[0x8]; 10148 u8 access_reg_group[0x8]; 10149 10150 u8 reserved_at_20[0x20]; 10151 10152 union { 10153 struct mlx5_ifc_mcam_access_reg_bits access_regs; 10154 struct mlx5_ifc_mcam_access_reg_bits1 access_regs1; 10155 struct mlx5_ifc_mcam_access_reg_bits2 access_regs2; 10156 u8 reserved_at_0[0x80]; 10157 } mng_access_reg_cap_mask; 10158 10159 u8 reserved_at_c0[0x80]; 10160 10161 union { 10162 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features; 10163 u8 reserved_at_0[0x80]; 10164 } mng_feature_cap_mask; 10165 10166 u8 reserved_at_1c0[0x80]; 10167 }; 10168 10169 struct mlx5_ifc_qcam_access_reg_cap_mask { 10170 u8 qcam_access_reg_cap_mask_127_to_20[0x6C]; 10171 u8 qpdpm[0x1]; 10172 u8 qcam_access_reg_cap_mask_18_to_4[0x0F]; 10173 u8 qdpm[0x1]; 10174 u8 qpts[0x1]; 10175 u8 qcap[0x1]; 10176 u8 qcam_access_reg_cap_mask_0[0x1]; 10177 }; 10178 10179 struct mlx5_ifc_qcam_qos_feature_cap_mask { 10180 u8 qcam_qos_feature_cap_mask_127_to_1[0x7F]; 10181 u8 qpts_trust_both[0x1]; 10182 }; 10183 10184 struct mlx5_ifc_qcam_reg_bits { 10185 u8 reserved_at_0[0x8]; 10186 u8 feature_group[0x8]; 10187 u8 reserved_at_10[0x8]; 10188 u8 access_reg_group[0x8]; 10189 u8 reserved_at_20[0x20]; 10190 10191 union { 10192 struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap; 10193 u8 reserved_at_0[0x80]; 10194 } qos_access_reg_cap_mask; 10195 10196 u8 reserved_at_c0[0x80]; 10197 10198 union { 10199 struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap; 10200 u8 reserved_at_0[0x80]; 10201 } qos_feature_cap_mask; 10202 10203 u8 reserved_at_1c0[0x80]; 10204 }; 10205 10206 struct mlx5_ifc_core_dump_reg_bits { 10207 u8 reserved_at_0[0x18]; 10208 u8 core_dump_type[0x8]; 10209 10210 u8 reserved_at_20[0x30]; 10211 u8 vhca_id[0x10]; 10212 10213 u8 reserved_at_60[0x8]; 10214 u8 qpn[0x18]; 10215 u8 reserved_at_80[0x180]; 10216 }; 10217 10218 struct mlx5_ifc_pcap_reg_bits { 10219 u8 reserved_at_0[0x8]; 10220 u8 local_port[0x8]; 10221 u8 reserved_at_10[0x10]; 10222 10223 u8 port_capability_mask[4][0x20]; 10224 }; 10225 10226 struct mlx5_ifc_paos_reg_bits { 10227 u8 swid[0x8]; 10228 u8 local_port[0x8]; 10229 u8 reserved_at_10[0x4]; 10230 u8 admin_status[0x4]; 10231 u8 reserved_at_18[0x4]; 10232 u8 oper_status[0x4]; 10233 10234 u8 ase[0x1]; 10235 u8 ee[0x1]; 10236 u8 reserved_at_22[0x1c]; 10237 u8 e[0x2]; 10238 10239 u8 reserved_at_40[0x40]; 10240 }; 10241 10242 struct mlx5_ifc_pamp_reg_bits { 10243 u8 reserved_at_0[0x8]; 10244 u8 opamp_group[0x8]; 10245 u8 reserved_at_10[0xc]; 10246 u8 opamp_group_type[0x4]; 10247 10248 u8 start_index[0x10]; 10249 u8 reserved_at_30[0x4]; 10250 u8 num_of_indices[0xc]; 10251 10252 u8 index_data[18][0x10]; 10253 }; 10254 10255 struct mlx5_ifc_pcmr_reg_bits { 10256 u8 reserved_at_0[0x8]; 10257 u8 local_port[0x8]; 10258 u8 reserved_at_10[0x10]; 10259 10260 u8 entropy_force_cap[0x1]; 10261 u8 entropy_calc_cap[0x1]; 10262 u8 entropy_gre_calc_cap[0x1]; 10263 u8 reserved_at_23[0xf]; 10264 u8 rx_ts_over_crc_cap[0x1]; 10265 u8 reserved_at_33[0xb]; 10266 u8 fcs_cap[0x1]; 10267 u8 reserved_at_3f[0x1]; 10268 10269 u8 entropy_force[0x1]; 10270 u8 entropy_calc[0x1]; 10271 u8 entropy_gre_calc[0x1]; 10272 u8 reserved_at_43[0xf]; 10273 u8 rx_ts_over_crc[0x1]; 10274 u8 reserved_at_53[0xb]; 10275 u8 fcs_chk[0x1]; 10276 u8 reserved_at_5f[0x1]; 10277 }; 10278 10279 struct mlx5_ifc_lane_2_module_mapping_bits { 10280 u8 reserved_at_0[0x4]; 10281 u8 rx_lane[0x4]; 10282 u8 reserved_at_8[0x4]; 10283 u8 tx_lane[0x4]; 10284 u8 reserved_at_10[0x8]; 10285 u8 module[0x8]; 10286 }; 10287 10288 struct mlx5_ifc_bufferx_reg_bits { 10289 u8 reserved_at_0[0x6]; 10290 u8 lossy[0x1]; 10291 u8 epsb[0x1]; 10292 u8 reserved_at_8[0x8]; 10293 u8 size[0x10]; 10294 10295 u8 xoff_threshold[0x10]; 10296 u8 xon_threshold[0x10]; 10297 }; 10298 10299 struct mlx5_ifc_set_node_in_bits { 10300 u8 node_description[64][0x8]; 10301 }; 10302 10303 struct mlx5_ifc_register_power_settings_bits { 10304 u8 reserved_at_0[0x18]; 10305 u8 power_settings_level[0x8]; 10306 10307 u8 reserved_at_20[0x60]; 10308 }; 10309 10310 struct mlx5_ifc_register_host_endianness_bits { 10311 u8 he[0x1]; 10312 u8 reserved_at_1[0x1f]; 10313 10314 u8 reserved_at_20[0x60]; 10315 }; 10316 10317 struct mlx5_ifc_umr_pointer_desc_argument_bits { 10318 u8 reserved_at_0[0x20]; 10319 10320 u8 mkey[0x20]; 10321 10322 u8 addressh_63_32[0x20]; 10323 10324 u8 addressl_31_0[0x20]; 10325 }; 10326 10327 struct mlx5_ifc_ud_adrs_vector_bits { 10328 u8 dc_key[0x40]; 10329 10330 u8 ext[0x1]; 10331 u8 reserved_at_41[0x7]; 10332 u8 destination_qp_dct[0x18]; 10333 10334 u8 static_rate[0x4]; 10335 u8 sl_eth_prio[0x4]; 10336 u8 fl[0x1]; 10337 u8 mlid[0x7]; 10338 u8 rlid_udp_sport[0x10]; 10339 10340 u8 reserved_at_80[0x20]; 10341 10342 u8 rmac_47_16[0x20]; 10343 10344 u8 rmac_15_0[0x10]; 10345 u8 tclass[0x8]; 10346 u8 hop_limit[0x8]; 10347 10348 u8 reserved_at_e0[0x1]; 10349 u8 grh[0x1]; 10350 u8 reserved_at_e2[0x2]; 10351 u8 src_addr_index[0x8]; 10352 u8 flow_label[0x14]; 10353 10354 u8 rgid_rip[16][0x8]; 10355 }; 10356 10357 struct mlx5_ifc_pages_req_event_bits { 10358 u8 reserved_at_0[0x10]; 10359 u8 function_id[0x10]; 10360 10361 u8 num_pages[0x20]; 10362 10363 u8 reserved_at_40[0xa0]; 10364 }; 10365 10366 struct mlx5_ifc_eqe_bits { 10367 u8 reserved_at_0[0x8]; 10368 u8 event_type[0x8]; 10369 u8 reserved_at_10[0x8]; 10370 u8 event_sub_type[0x8]; 10371 10372 u8 reserved_at_20[0xe0]; 10373 10374 union mlx5_ifc_event_auto_bits event_data; 10375 10376 u8 reserved_at_1e0[0x10]; 10377 u8 signature[0x8]; 10378 u8 reserved_at_1f8[0x7]; 10379 u8 owner[0x1]; 10380 }; 10381 10382 enum { 10383 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7, 10384 }; 10385 10386 struct mlx5_ifc_cmd_queue_entry_bits { 10387 u8 type[0x8]; 10388 u8 reserved_at_8[0x18]; 10389 10390 u8 input_length[0x20]; 10391 10392 u8 input_mailbox_pointer_63_32[0x20]; 10393 10394 u8 input_mailbox_pointer_31_9[0x17]; 10395 u8 reserved_at_77[0x9]; 10396 10397 u8 command_input_inline_data[16][0x8]; 10398 10399 u8 command_output_inline_data[16][0x8]; 10400 10401 u8 output_mailbox_pointer_63_32[0x20]; 10402 10403 u8 output_mailbox_pointer_31_9[0x17]; 10404 u8 reserved_at_1b7[0x9]; 10405 10406 u8 output_length[0x20]; 10407 10408 u8 token[0x8]; 10409 u8 signature[0x8]; 10410 u8 reserved_at_1f0[0x8]; 10411 u8 status[0x7]; 10412 u8 ownership[0x1]; 10413 }; 10414 10415 struct mlx5_ifc_cmd_out_bits { 10416 u8 status[0x8]; 10417 u8 reserved_at_8[0x18]; 10418 10419 u8 syndrome[0x20]; 10420 10421 u8 command_output[0x20]; 10422 }; 10423 10424 struct mlx5_ifc_cmd_in_bits { 10425 u8 opcode[0x10]; 10426 u8 reserved_at_10[0x10]; 10427 10428 u8 reserved_at_20[0x10]; 10429 u8 op_mod[0x10]; 10430 10431 u8 command[][0x20]; 10432 }; 10433 10434 struct mlx5_ifc_cmd_if_box_bits { 10435 u8 mailbox_data[512][0x8]; 10436 10437 u8 reserved_at_1000[0x180]; 10438 10439 u8 next_pointer_63_32[0x20]; 10440 10441 u8 next_pointer_31_10[0x16]; 10442 u8 reserved_at_11b6[0xa]; 10443 10444 u8 block_number[0x20]; 10445 10446 u8 reserved_at_11e0[0x8]; 10447 u8 token[0x8]; 10448 u8 ctrl_signature[0x8]; 10449 u8 signature[0x8]; 10450 }; 10451 10452 struct mlx5_ifc_mtt_bits { 10453 u8 ptag_63_32[0x20]; 10454 10455 u8 ptag_31_8[0x18]; 10456 u8 reserved_at_38[0x6]; 10457 u8 wr_en[0x1]; 10458 u8 rd_en[0x1]; 10459 }; 10460 10461 struct mlx5_ifc_query_wol_rol_out_bits { 10462 u8 status[0x8]; 10463 u8 reserved_at_8[0x18]; 10464 10465 u8 syndrome[0x20]; 10466 10467 u8 reserved_at_40[0x10]; 10468 u8 rol_mode[0x8]; 10469 u8 wol_mode[0x8]; 10470 10471 u8 reserved_at_60[0x20]; 10472 }; 10473 10474 struct mlx5_ifc_query_wol_rol_in_bits { 10475 u8 opcode[0x10]; 10476 u8 reserved_at_10[0x10]; 10477 10478 u8 reserved_at_20[0x10]; 10479 u8 op_mod[0x10]; 10480 10481 u8 reserved_at_40[0x40]; 10482 }; 10483 10484 struct mlx5_ifc_set_wol_rol_out_bits { 10485 u8 status[0x8]; 10486 u8 reserved_at_8[0x18]; 10487 10488 u8 syndrome[0x20]; 10489 10490 u8 reserved_at_40[0x40]; 10491 }; 10492 10493 struct mlx5_ifc_set_wol_rol_in_bits { 10494 u8 opcode[0x10]; 10495 u8 reserved_at_10[0x10]; 10496 10497 u8 reserved_at_20[0x10]; 10498 u8 op_mod[0x10]; 10499 10500 u8 rol_mode_valid[0x1]; 10501 u8 wol_mode_valid[0x1]; 10502 u8 reserved_at_42[0xe]; 10503 u8 rol_mode[0x8]; 10504 u8 wol_mode[0x8]; 10505 10506 u8 reserved_at_60[0x20]; 10507 }; 10508 10509 enum { 10510 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0, 10511 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1, 10512 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2, 10513 }; 10514 10515 enum { 10516 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0, 10517 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1, 10518 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2, 10519 }; 10520 10521 enum { 10522 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR = 0x1, 10523 MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC = 0x7, 10524 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR = 0x8, 10525 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR = 0x9, 10526 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR = 0xa, 10527 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR = 0xb, 10528 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN = 0xc, 10529 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR = 0xd, 10530 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV = 0xe, 10531 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR = 0xf, 10532 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR = 0x10, 10533 }; 10534 10535 struct mlx5_ifc_initial_seg_bits { 10536 u8 fw_rev_minor[0x10]; 10537 u8 fw_rev_major[0x10]; 10538 10539 u8 cmd_interface_rev[0x10]; 10540 u8 fw_rev_subminor[0x10]; 10541 10542 u8 reserved_at_40[0x40]; 10543 10544 u8 cmdq_phy_addr_63_32[0x20]; 10545 10546 u8 cmdq_phy_addr_31_12[0x14]; 10547 u8 reserved_at_b4[0x2]; 10548 u8 nic_interface[0x2]; 10549 u8 log_cmdq_size[0x4]; 10550 u8 log_cmdq_stride[0x4]; 10551 10552 u8 command_doorbell_vector[0x20]; 10553 10554 u8 reserved_at_e0[0xf00]; 10555 10556 u8 initializing[0x1]; 10557 u8 reserved_at_fe1[0x4]; 10558 u8 nic_interface_supported[0x3]; 10559 u8 embedded_cpu[0x1]; 10560 u8 reserved_at_fe9[0x17]; 10561 10562 struct mlx5_ifc_health_buffer_bits health_buffer; 10563 10564 u8 no_dram_nic_offset[0x20]; 10565 10566 u8 reserved_at_1220[0x6e40]; 10567 10568 u8 reserved_at_8060[0x1f]; 10569 u8 clear_int[0x1]; 10570 10571 u8 health_syndrome[0x8]; 10572 u8 health_counter[0x18]; 10573 10574 u8 reserved_at_80a0[0x17fc0]; 10575 }; 10576 10577 struct mlx5_ifc_mtpps_reg_bits { 10578 u8 reserved_at_0[0xc]; 10579 u8 cap_number_of_pps_pins[0x4]; 10580 u8 reserved_at_10[0x4]; 10581 u8 cap_max_num_of_pps_in_pins[0x4]; 10582 u8 reserved_at_18[0x4]; 10583 u8 cap_max_num_of_pps_out_pins[0x4]; 10584 10585 u8 reserved_at_20[0x13]; 10586 u8 cap_log_min_npps_period[0x5]; 10587 u8 reserved_at_38[0x3]; 10588 u8 cap_log_min_out_pulse_duration_ns[0x5]; 10589 10590 u8 reserved_at_40[0x4]; 10591 u8 cap_pin_3_mode[0x4]; 10592 u8 reserved_at_48[0x4]; 10593 u8 cap_pin_2_mode[0x4]; 10594 u8 reserved_at_50[0x4]; 10595 u8 cap_pin_1_mode[0x4]; 10596 u8 reserved_at_58[0x4]; 10597 u8 cap_pin_0_mode[0x4]; 10598 10599 u8 reserved_at_60[0x4]; 10600 u8 cap_pin_7_mode[0x4]; 10601 u8 reserved_at_68[0x4]; 10602 u8 cap_pin_6_mode[0x4]; 10603 u8 reserved_at_70[0x4]; 10604 u8 cap_pin_5_mode[0x4]; 10605 u8 reserved_at_78[0x4]; 10606 u8 cap_pin_4_mode[0x4]; 10607 10608 u8 field_select[0x20]; 10609 u8 reserved_at_a0[0x20]; 10610 10611 u8 npps_period[0x40]; 10612 10613 u8 enable[0x1]; 10614 u8 reserved_at_101[0xb]; 10615 u8 pattern[0x4]; 10616 u8 reserved_at_110[0x4]; 10617 u8 pin_mode[0x4]; 10618 u8 pin[0x8]; 10619 10620 u8 reserved_at_120[0x2]; 10621 u8 out_pulse_duration_ns[0x1e]; 10622 10623 u8 time_stamp[0x40]; 10624 10625 u8 out_pulse_duration[0x10]; 10626 u8 out_periodic_adjustment[0x10]; 10627 u8 enhanced_out_periodic_adjustment[0x20]; 10628 10629 u8 reserved_at_1c0[0x20]; 10630 }; 10631 10632 struct mlx5_ifc_mtppse_reg_bits { 10633 u8 reserved_at_0[0x18]; 10634 u8 pin[0x8]; 10635 u8 event_arm[0x1]; 10636 u8 reserved_at_21[0x1b]; 10637 u8 event_generation_mode[0x4]; 10638 u8 reserved_at_40[0x40]; 10639 }; 10640 10641 struct mlx5_ifc_mcqs_reg_bits { 10642 u8 last_index_flag[0x1]; 10643 u8 reserved_at_1[0x7]; 10644 u8 fw_device[0x8]; 10645 u8 component_index[0x10]; 10646 10647 u8 reserved_at_20[0x10]; 10648 u8 identifier[0x10]; 10649 10650 u8 reserved_at_40[0x17]; 10651 u8 component_status[0x5]; 10652 u8 component_update_state[0x4]; 10653 10654 u8 last_update_state_changer_type[0x4]; 10655 u8 last_update_state_changer_host_id[0x4]; 10656 u8 reserved_at_68[0x18]; 10657 }; 10658 10659 struct mlx5_ifc_mcqi_cap_bits { 10660 u8 supported_info_bitmask[0x20]; 10661 10662 u8 component_size[0x20]; 10663 10664 u8 max_component_size[0x20]; 10665 10666 u8 log_mcda_word_size[0x4]; 10667 u8 reserved_at_64[0xc]; 10668 u8 mcda_max_write_size[0x10]; 10669 10670 u8 rd_en[0x1]; 10671 u8 reserved_at_81[0x1]; 10672 u8 match_chip_id[0x1]; 10673 u8 match_psid[0x1]; 10674 u8 check_user_timestamp[0x1]; 10675 u8 match_base_guid_mac[0x1]; 10676 u8 reserved_at_86[0x1a]; 10677 }; 10678 10679 struct mlx5_ifc_mcqi_version_bits { 10680 u8 reserved_at_0[0x2]; 10681 u8 build_time_valid[0x1]; 10682 u8 user_defined_time_valid[0x1]; 10683 u8 reserved_at_4[0x14]; 10684 u8 version_string_length[0x8]; 10685 10686 u8 version[0x20]; 10687 10688 u8 build_time[0x40]; 10689 10690 u8 user_defined_time[0x40]; 10691 10692 u8 build_tool_version[0x20]; 10693 10694 u8 reserved_at_e0[0x20]; 10695 10696 u8 version_string[92][0x8]; 10697 }; 10698 10699 struct mlx5_ifc_mcqi_activation_method_bits { 10700 u8 pending_server_ac_power_cycle[0x1]; 10701 u8 pending_server_dc_power_cycle[0x1]; 10702 u8 pending_server_reboot[0x1]; 10703 u8 pending_fw_reset[0x1]; 10704 u8 auto_activate[0x1]; 10705 u8 all_hosts_sync[0x1]; 10706 u8 device_hw_reset[0x1]; 10707 u8 reserved_at_7[0x19]; 10708 }; 10709 10710 union mlx5_ifc_mcqi_reg_data_bits { 10711 struct mlx5_ifc_mcqi_cap_bits mcqi_caps; 10712 struct mlx5_ifc_mcqi_version_bits mcqi_version; 10713 struct mlx5_ifc_mcqi_activation_method_bits mcqi_activation_mathod; 10714 }; 10715 10716 struct mlx5_ifc_mcqi_reg_bits { 10717 u8 read_pending_component[0x1]; 10718 u8 reserved_at_1[0xf]; 10719 u8 component_index[0x10]; 10720 10721 u8 reserved_at_20[0x20]; 10722 10723 u8 reserved_at_40[0x1b]; 10724 u8 info_type[0x5]; 10725 10726 u8 info_size[0x20]; 10727 10728 u8 offset[0x20]; 10729 10730 u8 reserved_at_a0[0x10]; 10731 u8 data_size[0x10]; 10732 10733 union mlx5_ifc_mcqi_reg_data_bits data[]; 10734 }; 10735 10736 struct mlx5_ifc_mcc_reg_bits { 10737 u8 reserved_at_0[0x4]; 10738 u8 time_elapsed_since_last_cmd[0xc]; 10739 u8 reserved_at_10[0x8]; 10740 u8 instruction[0x8]; 10741 10742 u8 reserved_at_20[0x10]; 10743 u8 component_index[0x10]; 10744 10745 u8 reserved_at_40[0x8]; 10746 u8 update_handle[0x18]; 10747 10748 u8 handle_owner_type[0x4]; 10749 u8 handle_owner_host_id[0x4]; 10750 u8 reserved_at_68[0x1]; 10751 u8 control_progress[0x7]; 10752 u8 error_code[0x8]; 10753 u8 reserved_at_78[0x4]; 10754 u8 control_state[0x4]; 10755 10756 u8 component_size[0x20]; 10757 10758 u8 reserved_at_a0[0x60]; 10759 }; 10760 10761 struct mlx5_ifc_mcda_reg_bits { 10762 u8 reserved_at_0[0x8]; 10763 u8 update_handle[0x18]; 10764 10765 u8 offset[0x20]; 10766 10767 u8 reserved_at_40[0x10]; 10768 u8 size[0x10]; 10769 10770 u8 reserved_at_60[0x20]; 10771 10772 u8 data[][0x20]; 10773 }; 10774 10775 enum { 10776 MLX5_MFRL_REG_RESET_STATE_IDLE = 0, 10777 MLX5_MFRL_REG_RESET_STATE_IN_NEGOTIATION = 1, 10778 MLX5_MFRL_REG_RESET_STATE_RESET_IN_PROGRESS = 2, 10779 MLX5_MFRL_REG_RESET_STATE_TIMEOUT = 3, 10780 MLX5_MFRL_REG_RESET_STATE_NACK = 4, 10781 }; 10782 10783 enum { 10784 MLX5_MFRL_REG_RESET_TYPE_FULL_CHIP = BIT(0), 10785 MLX5_MFRL_REG_RESET_TYPE_NET_PORT_ALIVE = BIT(1), 10786 }; 10787 10788 enum { 10789 MLX5_MFRL_REG_RESET_LEVEL0 = BIT(0), 10790 MLX5_MFRL_REG_RESET_LEVEL3 = BIT(3), 10791 MLX5_MFRL_REG_RESET_LEVEL6 = BIT(6), 10792 }; 10793 10794 struct mlx5_ifc_mfrl_reg_bits { 10795 u8 reserved_at_0[0x20]; 10796 10797 u8 reserved_at_20[0x2]; 10798 u8 pci_sync_for_fw_update_start[0x1]; 10799 u8 pci_sync_for_fw_update_resp[0x2]; 10800 u8 rst_type_sel[0x3]; 10801 u8 reserved_at_28[0x4]; 10802 u8 reset_state[0x4]; 10803 u8 reset_type[0x8]; 10804 u8 reset_level[0x8]; 10805 }; 10806 10807 struct mlx5_ifc_mirc_reg_bits { 10808 u8 reserved_at_0[0x18]; 10809 u8 status_code[0x8]; 10810 10811 u8 reserved_at_20[0x20]; 10812 }; 10813 10814 struct mlx5_ifc_pddr_monitor_opcode_bits { 10815 u8 reserved_at_0[0x10]; 10816 u8 monitor_opcode[0x10]; 10817 }; 10818 10819 union mlx5_ifc_pddr_troubleshooting_page_status_opcode_auto_bits { 10820 struct mlx5_ifc_pddr_monitor_opcode_bits pddr_monitor_opcode; 10821 u8 reserved_at_0[0x20]; 10822 }; 10823 10824 enum { 10825 /* Monitor opcodes */ 10826 MLX5_PDDR_REG_TRBLSH_GROUP_OPCODE_MONITOR = 0x0, 10827 }; 10828 10829 struct mlx5_ifc_pddr_troubleshooting_page_bits { 10830 u8 reserved_at_0[0x10]; 10831 u8 group_opcode[0x10]; 10832 10833 union mlx5_ifc_pddr_troubleshooting_page_status_opcode_auto_bits status_opcode; 10834 10835 u8 reserved_at_40[0x20]; 10836 10837 u8 status_message[59][0x20]; 10838 }; 10839 10840 union mlx5_ifc_pddr_reg_page_data_auto_bits { 10841 struct mlx5_ifc_pddr_troubleshooting_page_bits pddr_troubleshooting_page; 10842 u8 reserved_at_0[0x7c0]; 10843 }; 10844 10845 enum { 10846 MLX5_PDDR_REG_PAGE_SELECT_TROUBLESHOOTING_INFO_PAGE = 0x1, 10847 }; 10848 10849 struct mlx5_ifc_pddr_reg_bits { 10850 u8 reserved_at_0[0x8]; 10851 u8 local_port[0x8]; 10852 u8 pnat[0x2]; 10853 u8 reserved_at_12[0xe]; 10854 10855 u8 reserved_at_20[0x18]; 10856 u8 page_select[0x8]; 10857 10858 union mlx5_ifc_pddr_reg_page_data_auto_bits page_data; 10859 }; 10860 10861 struct mlx5_ifc_mrtc_reg_bits { 10862 u8 time_synced[0x1]; 10863 u8 reserved_at_1[0x1f]; 10864 10865 u8 reserved_at_20[0x20]; 10866 10867 u8 time_h[0x20]; 10868 10869 u8 time_l[0x20]; 10870 }; 10871 10872 union mlx5_ifc_ports_control_registers_document_bits { 10873 struct mlx5_ifc_bufferx_reg_bits bufferx_reg; 10874 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 10875 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 10876 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 10877 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 10878 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 10879 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 10880 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout; 10881 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout; 10882 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping; 10883 struct mlx5_ifc_pamp_reg_bits pamp_reg; 10884 struct mlx5_ifc_paos_reg_bits paos_reg; 10885 struct mlx5_ifc_pcap_reg_bits pcap_reg; 10886 struct mlx5_ifc_pddr_monitor_opcode_bits pddr_monitor_opcode; 10887 struct mlx5_ifc_pddr_reg_bits pddr_reg; 10888 struct mlx5_ifc_pddr_troubleshooting_page_bits pddr_troubleshooting_page; 10889 struct mlx5_ifc_peir_reg_bits peir_reg; 10890 struct mlx5_ifc_pelc_reg_bits pelc_reg; 10891 struct mlx5_ifc_pfcc_reg_bits pfcc_reg; 10892 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 10893 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 10894 struct mlx5_ifc_pifr_reg_bits pifr_reg; 10895 struct mlx5_ifc_pipg_reg_bits pipg_reg; 10896 struct mlx5_ifc_plbf_reg_bits plbf_reg; 10897 struct mlx5_ifc_plib_reg_bits plib_reg; 10898 struct mlx5_ifc_plpc_reg_bits plpc_reg; 10899 struct mlx5_ifc_pmaos_reg_bits pmaos_reg; 10900 struct mlx5_ifc_pmlp_reg_bits pmlp_reg; 10901 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg; 10902 struct mlx5_ifc_pmpc_reg_bits pmpc_reg; 10903 struct mlx5_ifc_pmpe_reg_bits pmpe_reg; 10904 struct mlx5_ifc_pmpr_reg_bits pmpr_reg; 10905 struct mlx5_ifc_pmtu_reg_bits pmtu_reg; 10906 struct mlx5_ifc_ppad_reg_bits ppad_reg; 10907 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg; 10908 struct mlx5_ifc_mpein_reg_bits mpein_reg; 10909 struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg; 10910 struct mlx5_ifc_pplm_reg_bits pplm_reg; 10911 struct mlx5_ifc_pplr_reg_bits pplr_reg; 10912 struct mlx5_ifc_ppsc_reg_bits ppsc_reg; 10913 struct mlx5_ifc_pqdr_reg_bits pqdr_reg; 10914 struct mlx5_ifc_pspa_reg_bits pspa_reg; 10915 struct mlx5_ifc_ptas_reg_bits ptas_reg; 10916 struct mlx5_ifc_ptys_reg_bits ptys_reg; 10917 struct mlx5_ifc_mlcr_reg_bits mlcr_reg; 10918 struct mlx5_ifc_pude_reg_bits pude_reg; 10919 struct mlx5_ifc_pvlc_reg_bits pvlc_reg; 10920 struct mlx5_ifc_slrg_reg_bits slrg_reg; 10921 struct mlx5_ifc_sltp_reg_bits sltp_reg; 10922 struct mlx5_ifc_mtpps_reg_bits mtpps_reg; 10923 struct mlx5_ifc_mtppse_reg_bits mtppse_reg; 10924 struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg; 10925 struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits; 10926 struct mlx5_ifc_fpga_cap_bits fpga_cap_bits; 10927 struct mlx5_ifc_mcqi_reg_bits mcqi_reg; 10928 struct mlx5_ifc_mcc_reg_bits mcc_reg; 10929 struct mlx5_ifc_mcda_reg_bits mcda_reg; 10930 struct mlx5_ifc_mirc_reg_bits mirc_reg; 10931 struct mlx5_ifc_mfrl_reg_bits mfrl_reg; 10932 struct mlx5_ifc_mtutc_reg_bits mtutc_reg; 10933 struct mlx5_ifc_mrtc_reg_bits mrtc_reg; 10934 u8 reserved_at_0[0x60e0]; 10935 }; 10936 10937 union mlx5_ifc_debug_enhancements_document_bits { 10938 struct mlx5_ifc_health_buffer_bits health_buffer; 10939 u8 reserved_at_0[0x200]; 10940 }; 10941 10942 union mlx5_ifc_uplink_pci_interface_document_bits { 10943 struct mlx5_ifc_initial_seg_bits initial_seg; 10944 u8 reserved_at_0[0x20060]; 10945 }; 10946 10947 struct mlx5_ifc_set_flow_table_root_out_bits { 10948 u8 status[0x8]; 10949 u8 reserved_at_8[0x18]; 10950 10951 u8 syndrome[0x20]; 10952 10953 u8 reserved_at_40[0x40]; 10954 }; 10955 10956 struct mlx5_ifc_set_flow_table_root_in_bits { 10957 u8 opcode[0x10]; 10958 u8 reserved_at_10[0x10]; 10959 10960 u8 reserved_at_20[0x10]; 10961 u8 op_mod[0x10]; 10962 10963 u8 other_vport[0x1]; 10964 u8 reserved_at_41[0xf]; 10965 u8 vport_number[0x10]; 10966 10967 u8 reserved_at_60[0x20]; 10968 10969 u8 table_type[0x8]; 10970 u8 reserved_at_88[0x7]; 10971 u8 table_of_other_vport[0x1]; 10972 u8 table_vport_number[0x10]; 10973 10974 u8 reserved_at_a0[0x8]; 10975 u8 table_id[0x18]; 10976 10977 u8 reserved_at_c0[0x8]; 10978 u8 underlay_qpn[0x18]; 10979 u8 table_eswitch_owner_vhca_id_valid[0x1]; 10980 u8 reserved_at_e1[0xf]; 10981 u8 table_eswitch_owner_vhca_id[0x10]; 10982 u8 reserved_at_100[0x100]; 10983 }; 10984 10985 enum { 10986 MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = (1UL << 0), 10987 MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15), 10988 }; 10989 10990 struct mlx5_ifc_modify_flow_table_out_bits { 10991 u8 status[0x8]; 10992 u8 reserved_at_8[0x18]; 10993 10994 u8 syndrome[0x20]; 10995 10996 u8 reserved_at_40[0x40]; 10997 }; 10998 10999 struct mlx5_ifc_modify_flow_table_in_bits { 11000 u8 opcode[0x10]; 11001 u8 reserved_at_10[0x10]; 11002 11003 u8 reserved_at_20[0x10]; 11004 u8 op_mod[0x10]; 11005 11006 u8 other_vport[0x1]; 11007 u8 reserved_at_41[0xf]; 11008 u8 vport_number[0x10]; 11009 11010 u8 reserved_at_60[0x10]; 11011 u8 modify_field_select[0x10]; 11012 11013 u8 table_type[0x8]; 11014 u8 reserved_at_88[0x18]; 11015 11016 u8 reserved_at_a0[0x8]; 11017 u8 table_id[0x18]; 11018 11019 struct mlx5_ifc_flow_table_context_bits flow_table_context; 11020 }; 11021 11022 struct mlx5_ifc_ets_tcn_config_reg_bits { 11023 u8 g[0x1]; 11024 u8 b[0x1]; 11025 u8 r[0x1]; 11026 u8 reserved_at_3[0x9]; 11027 u8 group[0x4]; 11028 u8 reserved_at_10[0x9]; 11029 u8 bw_allocation[0x7]; 11030 11031 u8 reserved_at_20[0xc]; 11032 u8 max_bw_units[0x4]; 11033 u8 reserved_at_30[0x8]; 11034 u8 max_bw_value[0x8]; 11035 }; 11036 11037 struct mlx5_ifc_ets_global_config_reg_bits { 11038 u8 reserved_at_0[0x2]; 11039 u8 r[0x1]; 11040 u8 reserved_at_3[0x1d]; 11041 11042 u8 reserved_at_20[0xc]; 11043 u8 max_bw_units[0x4]; 11044 u8 reserved_at_30[0x8]; 11045 u8 max_bw_value[0x8]; 11046 }; 11047 11048 struct mlx5_ifc_qetc_reg_bits { 11049 u8 reserved_at_0[0x8]; 11050 u8 port_number[0x8]; 11051 u8 reserved_at_10[0x30]; 11052 11053 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8]; 11054 struct mlx5_ifc_ets_global_config_reg_bits global_configuration; 11055 }; 11056 11057 struct mlx5_ifc_qpdpm_dscp_reg_bits { 11058 u8 e[0x1]; 11059 u8 reserved_at_01[0x0b]; 11060 u8 prio[0x04]; 11061 }; 11062 11063 struct mlx5_ifc_qpdpm_reg_bits { 11064 u8 reserved_at_0[0x8]; 11065 u8 local_port[0x8]; 11066 u8 reserved_at_10[0x10]; 11067 struct mlx5_ifc_qpdpm_dscp_reg_bits dscp[64]; 11068 }; 11069 11070 struct mlx5_ifc_qpts_reg_bits { 11071 u8 reserved_at_0[0x8]; 11072 u8 local_port[0x8]; 11073 u8 reserved_at_10[0x2d]; 11074 u8 trust_state[0x3]; 11075 }; 11076 11077 struct mlx5_ifc_pptb_reg_bits { 11078 u8 reserved_at_0[0x2]; 11079 u8 mm[0x2]; 11080 u8 reserved_at_4[0x4]; 11081 u8 local_port[0x8]; 11082 u8 reserved_at_10[0x6]; 11083 u8 cm[0x1]; 11084 u8 um[0x1]; 11085 u8 pm[0x8]; 11086 11087 u8 prio_x_buff[0x20]; 11088 11089 u8 pm_msb[0x8]; 11090 u8 reserved_at_48[0x10]; 11091 u8 ctrl_buff[0x4]; 11092 u8 untagged_buff[0x4]; 11093 }; 11094 11095 struct mlx5_ifc_sbcam_reg_bits { 11096 u8 reserved_at_0[0x8]; 11097 u8 feature_group[0x8]; 11098 u8 reserved_at_10[0x8]; 11099 u8 access_reg_group[0x8]; 11100 11101 u8 reserved_at_20[0x20]; 11102 11103 u8 sb_access_reg_cap_mask[4][0x20]; 11104 11105 u8 reserved_at_c0[0x80]; 11106 11107 u8 sb_feature_cap_mask[4][0x20]; 11108 11109 u8 reserved_at_1c0[0x40]; 11110 11111 u8 cap_total_buffer_size[0x20]; 11112 11113 u8 cap_cell_size[0x10]; 11114 u8 cap_max_pg_buffers[0x8]; 11115 u8 cap_num_pool_supported[0x8]; 11116 11117 u8 reserved_at_240[0x8]; 11118 u8 cap_sbsr_stat_size[0x8]; 11119 u8 cap_max_tclass_data[0x8]; 11120 u8 cap_max_cpu_ingress_tclass_sb[0x8]; 11121 }; 11122 11123 struct mlx5_ifc_pbmc_reg_bits { 11124 u8 reserved_at_0[0x8]; 11125 u8 local_port[0x8]; 11126 u8 reserved_at_10[0x10]; 11127 11128 u8 xoff_timer_value[0x10]; 11129 u8 xoff_refresh[0x10]; 11130 11131 u8 reserved_at_40[0x9]; 11132 u8 fullness_threshold[0x7]; 11133 u8 port_buffer_size[0x10]; 11134 11135 struct mlx5_ifc_bufferx_reg_bits buffer[10]; 11136 11137 u8 reserved_at_2e0[0x80]; 11138 }; 11139 11140 struct mlx5_ifc_sbpr_reg_bits { 11141 u8 desc[0x1]; 11142 u8 snap[0x1]; 11143 u8 reserved_at_2[0x4]; 11144 u8 dir[0x2]; 11145 u8 reserved_at_8[0x14]; 11146 u8 pool[0x4]; 11147 11148 u8 infi_size[0x1]; 11149 u8 reserved_at_21[0x7]; 11150 u8 size[0x18]; 11151 11152 u8 reserved_at_40[0x1c]; 11153 u8 mode[0x4]; 11154 11155 u8 reserved_at_60[0x8]; 11156 u8 buff_occupancy[0x18]; 11157 11158 u8 clr[0x1]; 11159 u8 reserved_at_81[0x7]; 11160 u8 max_buff_occupancy[0x18]; 11161 11162 u8 reserved_at_a0[0x8]; 11163 u8 ext_buff_occupancy[0x18]; 11164 }; 11165 11166 struct mlx5_ifc_sbcm_reg_bits { 11167 u8 desc[0x1]; 11168 u8 snap[0x1]; 11169 u8 reserved_at_2[0x6]; 11170 u8 local_port[0x8]; 11171 u8 pnat[0x2]; 11172 u8 pg_buff[0x6]; 11173 u8 reserved_at_18[0x6]; 11174 u8 dir[0x2]; 11175 11176 u8 reserved_at_20[0x1f]; 11177 u8 exc[0x1]; 11178 11179 u8 reserved_at_40[0x40]; 11180 11181 u8 reserved_at_80[0x8]; 11182 u8 buff_occupancy[0x18]; 11183 11184 u8 clr[0x1]; 11185 u8 reserved_at_a1[0x7]; 11186 u8 max_buff_occupancy[0x18]; 11187 11188 u8 reserved_at_c0[0x8]; 11189 u8 min_buff[0x18]; 11190 11191 u8 infi_max[0x1]; 11192 u8 reserved_at_e1[0x7]; 11193 u8 max_buff[0x18]; 11194 11195 u8 reserved_at_100[0x20]; 11196 11197 u8 reserved_at_120[0x1c]; 11198 u8 pool[0x4]; 11199 }; 11200 11201 struct mlx5_ifc_qtct_reg_bits { 11202 u8 reserved_at_0[0x8]; 11203 u8 port_number[0x8]; 11204 u8 reserved_at_10[0xd]; 11205 u8 prio[0x3]; 11206 11207 u8 reserved_at_20[0x1d]; 11208 u8 tclass[0x3]; 11209 }; 11210 11211 struct mlx5_ifc_mcia_reg_bits { 11212 u8 l[0x1]; 11213 u8 reserved_at_1[0x7]; 11214 u8 module[0x8]; 11215 u8 reserved_at_10[0x8]; 11216 u8 status[0x8]; 11217 11218 u8 i2c_device_address[0x8]; 11219 u8 page_number[0x8]; 11220 u8 device_address[0x10]; 11221 11222 u8 reserved_at_40[0x10]; 11223 u8 size[0x10]; 11224 11225 u8 reserved_at_60[0x20]; 11226 11227 u8 dword_0[0x20]; 11228 u8 dword_1[0x20]; 11229 u8 dword_2[0x20]; 11230 u8 dword_3[0x20]; 11231 u8 dword_4[0x20]; 11232 u8 dword_5[0x20]; 11233 u8 dword_6[0x20]; 11234 u8 dword_7[0x20]; 11235 u8 dword_8[0x20]; 11236 u8 dword_9[0x20]; 11237 u8 dword_10[0x20]; 11238 u8 dword_11[0x20]; 11239 }; 11240 11241 struct mlx5_ifc_dcbx_param_bits { 11242 u8 dcbx_cee_cap[0x1]; 11243 u8 dcbx_ieee_cap[0x1]; 11244 u8 dcbx_standby_cap[0x1]; 11245 u8 reserved_at_3[0x5]; 11246 u8 port_number[0x8]; 11247 u8 reserved_at_10[0xa]; 11248 u8 max_application_table_size[6]; 11249 u8 reserved_at_20[0x15]; 11250 u8 version_oper[0x3]; 11251 u8 reserved_at_38[5]; 11252 u8 version_admin[0x3]; 11253 u8 willing_admin[0x1]; 11254 u8 reserved_at_41[0x3]; 11255 u8 pfc_cap_oper[0x4]; 11256 u8 reserved_at_48[0x4]; 11257 u8 pfc_cap_admin[0x4]; 11258 u8 reserved_at_50[0x4]; 11259 u8 num_of_tc_oper[0x4]; 11260 u8 reserved_at_58[0x4]; 11261 u8 num_of_tc_admin[0x4]; 11262 u8 remote_willing[0x1]; 11263 u8 reserved_at_61[3]; 11264 u8 remote_pfc_cap[4]; 11265 u8 reserved_at_68[0x14]; 11266 u8 remote_num_of_tc[0x4]; 11267 u8 reserved_at_80[0x18]; 11268 u8 error[0x8]; 11269 u8 reserved_at_a0[0x160]; 11270 }; 11271 11272 enum { 11273 MLX5_LAG_PORT_SELECT_MODE_QUEUE_AFFINITY = 0, 11274 MLX5_LAG_PORT_SELECT_MODE_PORT_SELECT_FT = 1, 11275 MLX5_LAG_PORT_SELECT_MODE_PORT_SELECT_MPESW = 2, 11276 }; 11277 11278 struct mlx5_ifc_lagc_bits { 11279 u8 fdb_selection_mode[0x1]; 11280 u8 reserved_at_1[0x14]; 11281 u8 port_select_mode[0x3]; 11282 u8 reserved_at_18[0x5]; 11283 u8 lag_state[0x3]; 11284 11285 u8 reserved_at_20[0xc]; 11286 u8 active_port[0x4]; 11287 u8 reserved_at_30[0x4]; 11288 u8 tx_remap_affinity_2[0x4]; 11289 u8 reserved_at_38[0x4]; 11290 u8 tx_remap_affinity_1[0x4]; 11291 }; 11292 11293 struct mlx5_ifc_create_lag_out_bits { 11294 u8 status[0x8]; 11295 u8 reserved_at_8[0x18]; 11296 11297 u8 syndrome[0x20]; 11298 11299 u8 reserved_at_40[0x40]; 11300 }; 11301 11302 struct mlx5_ifc_create_lag_in_bits { 11303 u8 opcode[0x10]; 11304 u8 reserved_at_10[0x10]; 11305 11306 u8 reserved_at_20[0x10]; 11307 u8 op_mod[0x10]; 11308 11309 struct mlx5_ifc_lagc_bits ctx; 11310 }; 11311 11312 struct mlx5_ifc_modify_lag_out_bits { 11313 u8 status[0x8]; 11314 u8 reserved_at_8[0x18]; 11315 11316 u8 syndrome[0x20]; 11317 11318 u8 reserved_at_40[0x40]; 11319 }; 11320 11321 struct mlx5_ifc_modify_lag_in_bits { 11322 u8 opcode[0x10]; 11323 u8 reserved_at_10[0x10]; 11324 11325 u8 reserved_at_20[0x10]; 11326 u8 op_mod[0x10]; 11327 11328 u8 reserved_at_40[0x20]; 11329 u8 field_select[0x20]; 11330 11331 struct mlx5_ifc_lagc_bits ctx; 11332 }; 11333 11334 struct mlx5_ifc_query_lag_out_bits { 11335 u8 status[0x8]; 11336 u8 reserved_at_8[0x18]; 11337 11338 u8 syndrome[0x20]; 11339 11340 struct mlx5_ifc_lagc_bits ctx; 11341 }; 11342 11343 struct mlx5_ifc_query_lag_in_bits { 11344 u8 opcode[0x10]; 11345 u8 reserved_at_10[0x10]; 11346 11347 u8 reserved_at_20[0x10]; 11348 u8 op_mod[0x10]; 11349 11350 u8 reserved_at_40[0x40]; 11351 }; 11352 11353 struct mlx5_ifc_destroy_lag_out_bits { 11354 u8 status[0x8]; 11355 u8 reserved_at_8[0x18]; 11356 11357 u8 syndrome[0x20]; 11358 11359 u8 reserved_at_40[0x40]; 11360 }; 11361 11362 struct mlx5_ifc_destroy_lag_in_bits { 11363 u8 opcode[0x10]; 11364 u8 reserved_at_10[0x10]; 11365 11366 u8 reserved_at_20[0x10]; 11367 u8 op_mod[0x10]; 11368 11369 u8 reserved_at_40[0x40]; 11370 }; 11371 11372 struct mlx5_ifc_create_vport_lag_out_bits { 11373 u8 status[0x8]; 11374 u8 reserved_at_8[0x18]; 11375 11376 u8 syndrome[0x20]; 11377 11378 u8 reserved_at_40[0x40]; 11379 }; 11380 11381 struct mlx5_ifc_create_vport_lag_in_bits { 11382 u8 opcode[0x10]; 11383 u8 reserved_at_10[0x10]; 11384 11385 u8 reserved_at_20[0x10]; 11386 u8 op_mod[0x10]; 11387 11388 u8 reserved_at_40[0x40]; 11389 }; 11390 11391 struct mlx5_ifc_destroy_vport_lag_out_bits { 11392 u8 status[0x8]; 11393 u8 reserved_at_8[0x18]; 11394 11395 u8 syndrome[0x20]; 11396 11397 u8 reserved_at_40[0x40]; 11398 }; 11399 11400 struct mlx5_ifc_destroy_vport_lag_in_bits { 11401 u8 opcode[0x10]; 11402 u8 reserved_at_10[0x10]; 11403 11404 u8 reserved_at_20[0x10]; 11405 u8 op_mod[0x10]; 11406 11407 u8 reserved_at_40[0x40]; 11408 }; 11409 11410 enum { 11411 MLX5_MODIFY_MEMIC_OP_MOD_ALLOC, 11412 MLX5_MODIFY_MEMIC_OP_MOD_DEALLOC, 11413 }; 11414 11415 struct mlx5_ifc_modify_memic_in_bits { 11416 u8 opcode[0x10]; 11417 u8 uid[0x10]; 11418 11419 u8 reserved_at_20[0x10]; 11420 u8 op_mod[0x10]; 11421 11422 u8 reserved_at_40[0x20]; 11423 11424 u8 reserved_at_60[0x18]; 11425 u8 memic_operation_type[0x8]; 11426 11427 u8 memic_start_addr[0x40]; 11428 11429 u8 reserved_at_c0[0x140]; 11430 }; 11431 11432 struct mlx5_ifc_modify_memic_out_bits { 11433 u8 status[0x8]; 11434 u8 reserved_at_8[0x18]; 11435 11436 u8 syndrome[0x20]; 11437 11438 u8 reserved_at_40[0x40]; 11439 11440 u8 memic_operation_addr[0x40]; 11441 11442 u8 reserved_at_c0[0x140]; 11443 }; 11444 11445 struct mlx5_ifc_alloc_memic_in_bits { 11446 u8 opcode[0x10]; 11447 u8 reserved_at_10[0x10]; 11448 11449 u8 reserved_at_20[0x10]; 11450 u8 op_mod[0x10]; 11451 11452 u8 reserved_at_30[0x20]; 11453 11454 u8 reserved_at_40[0x18]; 11455 u8 log_memic_addr_alignment[0x8]; 11456 11457 u8 range_start_addr[0x40]; 11458 11459 u8 range_size[0x20]; 11460 11461 u8 memic_size[0x20]; 11462 }; 11463 11464 struct mlx5_ifc_alloc_memic_out_bits { 11465 u8 status[0x8]; 11466 u8 reserved_at_8[0x18]; 11467 11468 u8 syndrome[0x20]; 11469 11470 u8 memic_start_addr[0x40]; 11471 }; 11472 11473 struct mlx5_ifc_dealloc_memic_in_bits { 11474 u8 opcode[0x10]; 11475 u8 reserved_at_10[0x10]; 11476 11477 u8 reserved_at_20[0x10]; 11478 u8 op_mod[0x10]; 11479 11480 u8 reserved_at_40[0x40]; 11481 11482 u8 memic_start_addr[0x40]; 11483 11484 u8 memic_size[0x20]; 11485 11486 u8 reserved_at_e0[0x20]; 11487 }; 11488 11489 struct mlx5_ifc_dealloc_memic_out_bits { 11490 u8 status[0x8]; 11491 u8 reserved_at_8[0x18]; 11492 11493 u8 syndrome[0x20]; 11494 11495 u8 reserved_at_40[0x40]; 11496 }; 11497 11498 struct mlx5_ifc_umem_bits { 11499 u8 reserved_at_0[0x80]; 11500 11501 u8 ats[0x1]; 11502 u8 reserved_at_81[0x1a]; 11503 u8 log_page_size[0x5]; 11504 11505 u8 page_offset[0x20]; 11506 11507 u8 num_of_mtt[0x40]; 11508 11509 struct mlx5_ifc_mtt_bits mtt[]; 11510 }; 11511 11512 struct mlx5_ifc_uctx_bits { 11513 u8 cap[0x20]; 11514 11515 u8 reserved_at_20[0x160]; 11516 }; 11517 11518 struct mlx5_ifc_sw_icm_bits { 11519 u8 modify_field_select[0x40]; 11520 11521 u8 reserved_at_40[0x18]; 11522 u8 log_sw_icm_size[0x8]; 11523 11524 u8 reserved_at_60[0x20]; 11525 11526 u8 sw_icm_start_addr[0x40]; 11527 11528 u8 reserved_at_c0[0x140]; 11529 }; 11530 11531 struct mlx5_ifc_geneve_tlv_option_bits { 11532 u8 modify_field_select[0x40]; 11533 11534 u8 reserved_at_40[0x18]; 11535 u8 geneve_option_fte_index[0x8]; 11536 11537 u8 option_class[0x10]; 11538 u8 option_type[0x8]; 11539 u8 reserved_at_78[0x3]; 11540 u8 option_data_length[0x5]; 11541 11542 u8 reserved_at_80[0x180]; 11543 }; 11544 11545 struct mlx5_ifc_create_umem_in_bits { 11546 u8 opcode[0x10]; 11547 u8 uid[0x10]; 11548 11549 u8 reserved_at_20[0x10]; 11550 u8 op_mod[0x10]; 11551 11552 u8 reserved_at_40[0x40]; 11553 11554 struct mlx5_ifc_umem_bits umem; 11555 }; 11556 11557 struct mlx5_ifc_create_umem_out_bits { 11558 u8 status[0x8]; 11559 u8 reserved_at_8[0x18]; 11560 11561 u8 syndrome[0x20]; 11562 11563 u8 reserved_at_40[0x8]; 11564 u8 umem_id[0x18]; 11565 11566 u8 reserved_at_60[0x20]; 11567 }; 11568 11569 struct mlx5_ifc_destroy_umem_in_bits { 11570 u8 opcode[0x10]; 11571 u8 uid[0x10]; 11572 11573 u8 reserved_at_20[0x10]; 11574 u8 op_mod[0x10]; 11575 11576 u8 reserved_at_40[0x8]; 11577 u8 umem_id[0x18]; 11578 11579 u8 reserved_at_60[0x20]; 11580 }; 11581 11582 struct mlx5_ifc_destroy_umem_out_bits { 11583 u8 status[0x8]; 11584 u8 reserved_at_8[0x18]; 11585 11586 u8 syndrome[0x20]; 11587 11588 u8 reserved_at_40[0x40]; 11589 }; 11590 11591 struct mlx5_ifc_create_uctx_in_bits { 11592 u8 opcode[0x10]; 11593 u8 reserved_at_10[0x10]; 11594 11595 u8 reserved_at_20[0x10]; 11596 u8 op_mod[0x10]; 11597 11598 u8 reserved_at_40[0x40]; 11599 11600 struct mlx5_ifc_uctx_bits uctx; 11601 }; 11602 11603 struct mlx5_ifc_create_uctx_out_bits { 11604 u8 status[0x8]; 11605 u8 reserved_at_8[0x18]; 11606 11607 u8 syndrome[0x20]; 11608 11609 u8 reserved_at_40[0x10]; 11610 u8 uid[0x10]; 11611 11612 u8 reserved_at_60[0x20]; 11613 }; 11614 11615 struct mlx5_ifc_destroy_uctx_in_bits { 11616 u8 opcode[0x10]; 11617 u8 reserved_at_10[0x10]; 11618 11619 u8 reserved_at_20[0x10]; 11620 u8 op_mod[0x10]; 11621 11622 u8 reserved_at_40[0x10]; 11623 u8 uid[0x10]; 11624 11625 u8 reserved_at_60[0x20]; 11626 }; 11627 11628 struct mlx5_ifc_destroy_uctx_out_bits { 11629 u8 status[0x8]; 11630 u8 reserved_at_8[0x18]; 11631 11632 u8 syndrome[0x20]; 11633 11634 u8 reserved_at_40[0x40]; 11635 }; 11636 11637 struct mlx5_ifc_create_sw_icm_in_bits { 11638 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 11639 struct mlx5_ifc_sw_icm_bits sw_icm; 11640 }; 11641 11642 struct mlx5_ifc_create_geneve_tlv_option_in_bits { 11643 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 11644 struct mlx5_ifc_geneve_tlv_option_bits geneve_tlv_opt; 11645 }; 11646 11647 struct mlx5_ifc_mtrc_string_db_param_bits { 11648 u8 string_db_base_address[0x20]; 11649 11650 u8 reserved_at_20[0x8]; 11651 u8 string_db_size[0x18]; 11652 }; 11653 11654 struct mlx5_ifc_mtrc_cap_bits { 11655 u8 trace_owner[0x1]; 11656 u8 trace_to_memory[0x1]; 11657 u8 reserved_at_2[0x4]; 11658 u8 trc_ver[0x2]; 11659 u8 reserved_at_8[0x14]; 11660 u8 num_string_db[0x4]; 11661 11662 u8 first_string_trace[0x8]; 11663 u8 num_string_trace[0x8]; 11664 u8 reserved_at_30[0x28]; 11665 11666 u8 log_max_trace_buffer_size[0x8]; 11667 11668 u8 reserved_at_60[0x20]; 11669 11670 struct mlx5_ifc_mtrc_string_db_param_bits string_db_param[8]; 11671 11672 u8 reserved_at_280[0x180]; 11673 }; 11674 11675 struct mlx5_ifc_mtrc_conf_bits { 11676 u8 reserved_at_0[0x1c]; 11677 u8 trace_mode[0x4]; 11678 u8 reserved_at_20[0x18]; 11679 u8 log_trace_buffer_size[0x8]; 11680 u8 trace_mkey[0x20]; 11681 u8 reserved_at_60[0x3a0]; 11682 }; 11683 11684 struct mlx5_ifc_mtrc_stdb_bits { 11685 u8 string_db_index[0x4]; 11686 u8 reserved_at_4[0x4]; 11687 u8 read_size[0x18]; 11688 u8 start_offset[0x20]; 11689 u8 string_db_data[]; 11690 }; 11691 11692 struct mlx5_ifc_mtrc_ctrl_bits { 11693 u8 trace_status[0x2]; 11694 u8 reserved_at_2[0x2]; 11695 u8 arm_event[0x1]; 11696 u8 reserved_at_5[0xb]; 11697 u8 modify_field_select[0x10]; 11698 u8 reserved_at_20[0x2b]; 11699 u8 current_timestamp52_32[0x15]; 11700 u8 current_timestamp31_0[0x20]; 11701 u8 reserved_at_80[0x180]; 11702 }; 11703 11704 struct mlx5_ifc_host_params_context_bits { 11705 u8 host_number[0x8]; 11706 u8 reserved_at_8[0x7]; 11707 u8 host_pf_disabled[0x1]; 11708 u8 host_num_of_vfs[0x10]; 11709 11710 u8 host_total_vfs[0x10]; 11711 u8 host_pci_bus[0x10]; 11712 11713 u8 reserved_at_40[0x10]; 11714 u8 host_pci_device[0x10]; 11715 11716 u8 reserved_at_60[0x10]; 11717 u8 host_pci_function[0x10]; 11718 11719 u8 reserved_at_80[0x180]; 11720 }; 11721 11722 struct mlx5_ifc_query_esw_functions_in_bits { 11723 u8 opcode[0x10]; 11724 u8 reserved_at_10[0x10]; 11725 11726 u8 reserved_at_20[0x10]; 11727 u8 op_mod[0x10]; 11728 11729 u8 reserved_at_40[0x40]; 11730 }; 11731 11732 struct mlx5_ifc_query_esw_functions_out_bits { 11733 u8 status[0x8]; 11734 u8 reserved_at_8[0x18]; 11735 11736 u8 syndrome[0x20]; 11737 11738 u8 reserved_at_40[0x40]; 11739 11740 struct mlx5_ifc_host_params_context_bits host_params_context; 11741 11742 u8 reserved_at_280[0x180]; 11743 u8 host_sf_enable[][0x40]; 11744 }; 11745 11746 struct mlx5_ifc_sf_partition_bits { 11747 u8 reserved_at_0[0x10]; 11748 u8 log_num_sf[0x8]; 11749 u8 log_sf_bar_size[0x8]; 11750 }; 11751 11752 struct mlx5_ifc_query_sf_partitions_out_bits { 11753 u8 status[0x8]; 11754 u8 reserved_at_8[0x18]; 11755 11756 u8 syndrome[0x20]; 11757 11758 u8 reserved_at_40[0x18]; 11759 u8 num_sf_partitions[0x8]; 11760 11761 u8 reserved_at_60[0x20]; 11762 11763 struct mlx5_ifc_sf_partition_bits sf_partition[]; 11764 }; 11765 11766 struct mlx5_ifc_query_sf_partitions_in_bits { 11767 u8 opcode[0x10]; 11768 u8 reserved_at_10[0x10]; 11769 11770 u8 reserved_at_20[0x10]; 11771 u8 op_mod[0x10]; 11772 11773 u8 reserved_at_40[0x40]; 11774 }; 11775 11776 struct mlx5_ifc_dealloc_sf_out_bits { 11777 u8 status[0x8]; 11778 u8 reserved_at_8[0x18]; 11779 11780 u8 syndrome[0x20]; 11781 11782 u8 reserved_at_40[0x40]; 11783 }; 11784 11785 struct mlx5_ifc_dealloc_sf_in_bits { 11786 u8 opcode[0x10]; 11787 u8 reserved_at_10[0x10]; 11788 11789 u8 reserved_at_20[0x10]; 11790 u8 op_mod[0x10]; 11791 11792 u8 reserved_at_40[0x10]; 11793 u8 function_id[0x10]; 11794 11795 u8 reserved_at_60[0x20]; 11796 }; 11797 11798 struct mlx5_ifc_alloc_sf_out_bits { 11799 u8 status[0x8]; 11800 u8 reserved_at_8[0x18]; 11801 11802 u8 syndrome[0x20]; 11803 11804 u8 reserved_at_40[0x40]; 11805 }; 11806 11807 struct mlx5_ifc_alloc_sf_in_bits { 11808 u8 opcode[0x10]; 11809 u8 reserved_at_10[0x10]; 11810 11811 u8 reserved_at_20[0x10]; 11812 u8 op_mod[0x10]; 11813 11814 u8 reserved_at_40[0x10]; 11815 u8 function_id[0x10]; 11816 11817 u8 reserved_at_60[0x20]; 11818 }; 11819 11820 struct mlx5_ifc_affiliated_event_header_bits { 11821 u8 reserved_at_0[0x10]; 11822 u8 obj_type[0x10]; 11823 11824 u8 obj_id[0x20]; 11825 }; 11826 11827 enum { 11828 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = BIT_ULL(0xc), 11829 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_IPSEC = BIT_ULL(0x13), 11830 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_SAMPLER = BIT_ULL(0x20), 11831 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_FLOW_METER_ASO = BIT_ULL(0x24), 11832 }; 11833 11834 enum { 11835 MLX5_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = 0xc, 11836 MLX5_GENERAL_OBJECT_TYPES_IPSEC = 0x13, 11837 MLX5_GENERAL_OBJECT_TYPES_SAMPLER = 0x20, 11838 MLX5_GENERAL_OBJECT_TYPES_FLOW_METER_ASO = 0x24, 11839 MLX5_GENERAL_OBJECT_TYPES_MACSEC = 0x27, 11840 MLX5_GENERAL_OBJECT_TYPES_INT_KEK = 0x47, 11841 }; 11842 11843 enum { 11844 MLX5_IPSEC_OBJECT_ICV_LEN_16B, 11845 }; 11846 11847 enum { 11848 MLX5_IPSEC_ASO_REG_C_0_1 = 0x0, 11849 MLX5_IPSEC_ASO_REG_C_2_3 = 0x1, 11850 MLX5_IPSEC_ASO_REG_C_4_5 = 0x2, 11851 MLX5_IPSEC_ASO_REG_C_6_7 = 0x3, 11852 }; 11853 11854 enum { 11855 MLX5_IPSEC_ASO_MODE = 0x0, 11856 MLX5_IPSEC_ASO_REPLAY_PROTECTION = 0x1, 11857 MLX5_IPSEC_ASO_INC_SN = 0x2, 11858 }; 11859 11860 struct mlx5_ifc_ipsec_aso_bits { 11861 u8 valid[0x1]; 11862 u8 reserved_at_201[0x1]; 11863 u8 mode[0x2]; 11864 u8 window_sz[0x2]; 11865 u8 soft_lft_arm[0x1]; 11866 u8 hard_lft_arm[0x1]; 11867 u8 remove_flow_enable[0x1]; 11868 u8 esn_event_arm[0x1]; 11869 u8 reserved_at_20a[0x16]; 11870 11871 u8 remove_flow_pkt_cnt[0x20]; 11872 11873 u8 remove_flow_soft_lft[0x20]; 11874 11875 u8 reserved_at_260[0x80]; 11876 11877 u8 mode_parameter[0x20]; 11878 11879 u8 replay_protection_window[0x100]; 11880 }; 11881 11882 struct mlx5_ifc_ipsec_obj_bits { 11883 u8 modify_field_select[0x40]; 11884 u8 full_offload[0x1]; 11885 u8 reserved_at_41[0x1]; 11886 u8 esn_en[0x1]; 11887 u8 esn_overlap[0x1]; 11888 u8 reserved_at_44[0x2]; 11889 u8 icv_length[0x2]; 11890 u8 reserved_at_48[0x4]; 11891 u8 aso_return_reg[0x4]; 11892 u8 reserved_at_50[0x10]; 11893 11894 u8 esn_msb[0x20]; 11895 11896 u8 reserved_at_80[0x8]; 11897 u8 dekn[0x18]; 11898 11899 u8 salt[0x20]; 11900 11901 u8 implicit_iv[0x40]; 11902 11903 u8 reserved_at_100[0x8]; 11904 u8 ipsec_aso_access_pd[0x18]; 11905 u8 reserved_at_120[0xe0]; 11906 11907 struct mlx5_ifc_ipsec_aso_bits ipsec_aso; 11908 }; 11909 11910 struct mlx5_ifc_create_ipsec_obj_in_bits { 11911 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 11912 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 11913 }; 11914 11915 enum { 11916 MLX5_MODIFY_IPSEC_BITMASK_ESN_OVERLAP = BIT(0), 11917 MLX5_MODIFY_IPSEC_BITMASK_ESN_MSB = BIT(1), 11918 }; 11919 11920 struct mlx5_ifc_query_ipsec_obj_out_bits { 11921 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 11922 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 11923 }; 11924 11925 struct mlx5_ifc_modify_ipsec_obj_in_bits { 11926 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 11927 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 11928 }; 11929 11930 enum { 11931 MLX5_MACSEC_ASO_REPLAY_PROTECTION = 0x1, 11932 }; 11933 11934 enum { 11935 MLX5_MACSEC_ASO_REPLAY_WIN_32BIT = 0x0, 11936 MLX5_MACSEC_ASO_REPLAY_WIN_64BIT = 0x1, 11937 MLX5_MACSEC_ASO_REPLAY_WIN_128BIT = 0x2, 11938 MLX5_MACSEC_ASO_REPLAY_WIN_256BIT = 0x3, 11939 }; 11940 11941 #define MLX5_MACSEC_ASO_INC_SN 0x2 11942 #define MLX5_MACSEC_ASO_REG_C_4_5 0x2 11943 11944 struct mlx5_ifc_macsec_aso_bits { 11945 u8 valid[0x1]; 11946 u8 reserved_at_1[0x1]; 11947 u8 mode[0x2]; 11948 u8 window_size[0x2]; 11949 u8 soft_lifetime_arm[0x1]; 11950 u8 hard_lifetime_arm[0x1]; 11951 u8 remove_flow_enable[0x1]; 11952 u8 epn_event_arm[0x1]; 11953 u8 reserved_at_a[0x16]; 11954 11955 u8 remove_flow_packet_count[0x20]; 11956 11957 u8 remove_flow_soft_lifetime[0x20]; 11958 11959 u8 reserved_at_60[0x80]; 11960 11961 u8 mode_parameter[0x20]; 11962 11963 u8 replay_protection_window[8][0x20]; 11964 }; 11965 11966 struct mlx5_ifc_macsec_offload_obj_bits { 11967 u8 modify_field_select[0x40]; 11968 11969 u8 confidentiality_en[0x1]; 11970 u8 reserved_at_41[0x1]; 11971 u8 epn_en[0x1]; 11972 u8 epn_overlap[0x1]; 11973 u8 reserved_at_44[0x2]; 11974 u8 confidentiality_offset[0x2]; 11975 u8 reserved_at_48[0x4]; 11976 u8 aso_return_reg[0x4]; 11977 u8 reserved_at_50[0x10]; 11978 11979 u8 epn_msb[0x20]; 11980 11981 u8 reserved_at_80[0x8]; 11982 u8 dekn[0x18]; 11983 11984 u8 reserved_at_a0[0x20]; 11985 11986 u8 sci[0x40]; 11987 11988 u8 reserved_at_100[0x8]; 11989 u8 macsec_aso_access_pd[0x18]; 11990 11991 u8 reserved_at_120[0x60]; 11992 11993 u8 salt[3][0x20]; 11994 11995 u8 reserved_at_1e0[0x20]; 11996 11997 struct mlx5_ifc_macsec_aso_bits macsec_aso; 11998 }; 11999 12000 struct mlx5_ifc_create_macsec_obj_in_bits { 12001 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12002 struct mlx5_ifc_macsec_offload_obj_bits macsec_object; 12003 }; 12004 12005 struct mlx5_ifc_modify_macsec_obj_in_bits { 12006 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12007 struct mlx5_ifc_macsec_offload_obj_bits macsec_object; 12008 }; 12009 12010 enum { 12011 MLX5_MODIFY_MACSEC_BITMASK_EPN_OVERLAP = BIT(0), 12012 MLX5_MODIFY_MACSEC_BITMASK_EPN_MSB = BIT(1), 12013 }; 12014 12015 struct mlx5_ifc_query_macsec_obj_out_bits { 12016 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 12017 struct mlx5_ifc_macsec_offload_obj_bits macsec_object; 12018 }; 12019 12020 struct mlx5_ifc_wrapped_dek_bits { 12021 u8 gcm_iv[0x60]; 12022 12023 u8 reserved_at_60[0x20]; 12024 12025 u8 const0[0x1]; 12026 u8 key_size[0x1]; 12027 u8 reserved_at_82[0x2]; 12028 u8 key2_invalid[0x1]; 12029 u8 reserved_at_85[0x3]; 12030 u8 pd[0x18]; 12031 12032 u8 key_purpose[0x5]; 12033 u8 reserved_at_a5[0x13]; 12034 u8 kek_id[0x8]; 12035 12036 u8 reserved_at_c0[0x40]; 12037 12038 u8 key1[0x8][0x20]; 12039 12040 u8 key2[0x8][0x20]; 12041 12042 u8 reserved_at_300[0x40]; 12043 12044 u8 const1[0x1]; 12045 u8 reserved_at_341[0x1f]; 12046 12047 u8 reserved_at_360[0x20]; 12048 12049 u8 auth_tag[0x80]; 12050 }; 12051 12052 struct mlx5_ifc_encryption_key_obj_bits { 12053 u8 modify_field_select[0x40]; 12054 12055 u8 state[0x8]; 12056 u8 sw_wrapped[0x1]; 12057 u8 reserved_at_49[0xb]; 12058 u8 key_size[0x4]; 12059 u8 reserved_at_58[0x4]; 12060 u8 key_purpose[0x4]; 12061 12062 u8 reserved_at_60[0x8]; 12063 u8 pd[0x18]; 12064 12065 u8 reserved_at_80[0x100]; 12066 12067 u8 opaque[0x40]; 12068 12069 u8 reserved_at_1c0[0x40]; 12070 12071 u8 key[8][0x80]; 12072 12073 u8 sw_wrapped_dek[8][0x80]; 12074 12075 u8 reserved_at_a00[0x600]; 12076 }; 12077 12078 struct mlx5_ifc_create_encryption_key_in_bits { 12079 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12080 struct mlx5_ifc_encryption_key_obj_bits encryption_key_object; 12081 }; 12082 12083 struct mlx5_ifc_modify_encryption_key_in_bits { 12084 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12085 struct mlx5_ifc_encryption_key_obj_bits encryption_key_object; 12086 }; 12087 12088 enum { 12089 MLX5_FLOW_METER_MODE_BYTES_IP_LENGTH = 0x0, 12090 MLX5_FLOW_METER_MODE_BYTES_CALC_WITH_L2 = 0x1, 12091 MLX5_FLOW_METER_MODE_BYTES_CALC_WITH_L2_IPG = 0x2, 12092 MLX5_FLOW_METER_MODE_NUM_PACKETS = 0x3, 12093 }; 12094 12095 struct mlx5_ifc_flow_meter_parameters_bits { 12096 u8 valid[0x1]; 12097 u8 bucket_overflow[0x1]; 12098 u8 start_color[0x2]; 12099 u8 both_buckets_on_green[0x1]; 12100 u8 reserved_at_5[0x1]; 12101 u8 meter_mode[0x2]; 12102 u8 reserved_at_8[0x18]; 12103 12104 u8 reserved_at_20[0x20]; 12105 12106 u8 reserved_at_40[0x3]; 12107 u8 cbs_exponent[0x5]; 12108 u8 cbs_mantissa[0x8]; 12109 u8 reserved_at_50[0x3]; 12110 u8 cir_exponent[0x5]; 12111 u8 cir_mantissa[0x8]; 12112 12113 u8 reserved_at_60[0x20]; 12114 12115 u8 reserved_at_80[0x3]; 12116 u8 ebs_exponent[0x5]; 12117 u8 ebs_mantissa[0x8]; 12118 u8 reserved_at_90[0x3]; 12119 u8 eir_exponent[0x5]; 12120 u8 eir_mantissa[0x8]; 12121 12122 u8 reserved_at_a0[0x60]; 12123 }; 12124 12125 struct mlx5_ifc_flow_meter_aso_obj_bits { 12126 u8 modify_field_select[0x40]; 12127 12128 u8 reserved_at_40[0x40]; 12129 12130 u8 reserved_at_80[0x8]; 12131 u8 meter_aso_access_pd[0x18]; 12132 12133 u8 reserved_at_a0[0x160]; 12134 12135 struct mlx5_ifc_flow_meter_parameters_bits flow_meter_parameters[2]; 12136 }; 12137 12138 struct mlx5_ifc_create_flow_meter_aso_obj_in_bits { 12139 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 12140 struct mlx5_ifc_flow_meter_aso_obj_bits flow_meter_aso_obj; 12141 }; 12142 12143 struct mlx5_ifc_int_kek_obj_bits { 12144 u8 modify_field_select[0x40]; 12145 12146 u8 state[0x8]; 12147 u8 auto_gen[0x1]; 12148 u8 reserved_at_49[0xb]; 12149 u8 key_size[0x4]; 12150 u8 reserved_at_58[0x8]; 12151 12152 u8 reserved_at_60[0x8]; 12153 u8 pd[0x18]; 12154 12155 u8 reserved_at_80[0x180]; 12156 u8 key[8][0x80]; 12157 12158 u8 reserved_at_600[0x200]; 12159 }; 12160 12161 struct mlx5_ifc_create_int_kek_obj_in_bits { 12162 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12163 struct mlx5_ifc_int_kek_obj_bits int_kek_object; 12164 }; 12165 12166 struct mlx5_ifc_create_int_kek_obj_out_bits { 12167 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 12168 struct mlx5_ifc_int_kek_obj_bits int_kek_object; 12169 }; 12170 12171 struct mlx5_ifc_sampler_obj_bits { 12172 u8 modify_field_select[0x40]; 12173 12174 u8 table_type[0x8]; 12175 u8 level[0x8]; 12176 u8 reserved_at_50[0xf]; 12177 u8 ignore_flow_level[0x1]; 12178 12179 u8 sample_ratio[0x20]; 12180 12181 u8 reserved_at_80[0x8]; 12182 u8 sample_table_id[0x18]; 12183 12184 u8 reserved_at_a0[0x8]; 12185 u8 default_table_id[0x18]; 12186 12187 u8 sw_steering_icm_address_rx[0x40]; 12188 u8 sw_steering_icm_address_tx[0x40]; 12189 12190 u8 reserved_at_140[0xa0]; 12191 }; 12192 12193 struct mlx5_ifc_create_sampler_obj_in_bits { 12194 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12195 struct mlx5_ifc_sampler_obj_bits sampler_object; 12196 }; 12197 12198 struct mlx5_ifc_query_sampler_obj_out_bits { 12199 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 12200 struct mlx5_ifc_sampler_obj_bits sampler_object; 12201 }; 12202 12203 enum { 12204 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_128 = 0x0, 12205 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_256 = 0x1, 12206 }; 12207 12208 enum { 12209 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_PURPOSE_TLS = 0x1, 12210 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_PURPOSE_IPSEC = 0x2, 12211 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_PURPOSE_MACSEC = 0x4, 12212 }; 12213 12214 struct mlx5_ifc_tls_static_params_bits { 12215 u8 const_2[0x2]; 12216 u8 tls_version[0x4]; 12217 u8 const_1[0x2]; 12218 u8 reserved_at_8[0x14]; 12219 u8 encryption_standard[0x4]; 12220 12221 u8 reserved_at_20[0x20]; 12222 12223 u8 initial_record_number[0x40]; 12224 12225 u8 resync_tcp_sn[0x20]; 12226 12227 u8 gcm_iv[0x20]; 12228 12229 u8 implicit_iv[0x40]; 12230 12231 u8 reserved_at_100[0x8]; 12232 u8 dek_index[0x18]; 12233 12234 u8 reserved_at_120[0xe0]; 12235 }; 12236 12237 struct mlx5_ifc_tls_progress_params_bits { 12238 u8 next_record_tcp_sn[0x20]; 12239 12240 u8 hw_resync_tcp_sn[0x20]; 12241 12242 u8 record_tracker_state[0x2]; 12243 u8 auth_state[0x2]; 12244 u8 reserved_at_44[0x4]; 12245 u8 hw_offset_record_number[0x18]; 12246 }; 12247 12248 enum { 12249 MLX5_MTT_PERM_READ = 1 << 0, 12250 MLX5_MTT_PERM_WRITE = 1 << 1, 12251 MLX5_MTT_PERM_RW = MLX5_MTT_PERM_READ | MLX5_MTT_PERM_WRITE, 12252 }; 12253 12254 enum { 12255 MLX5_SUSPEND_VHCA_IN_OP_MOD_SUSPEND_INITIATOR = 0x0, 12256 MLX5_SUSPEND_VHCA_IN_OP_MOD_SUSPEND_RESPONDER = 0x1, 12257 }; 12258 12259 struct mlx5_ifc_suspend_vhca_in_bits { 12260 u8 opcode[0x10]; 12261 u8 uid[0x10]; 12262 12263 u8 reserved_at_20[0x10]; 12264 u8 op_mod[0x10]; 12265 12266 u8 reserved_at_40[0x10]; 12267 u8 vhca_id[0x10]; 12268 12269 u8 reserved_at_60[0x20]; 12270 }; 12271 12272 struct mlx5_ifc_suspend_vhca_out_bits { 12273 u8 status[0x8]; 12274 u8 reserved_at_8[0x18]; 12275 12276 u8 syndrome[0x20]; 12277 12278 u8 reserved_at_40[0x40]; 12279 }; 12280 12281 enum { 12282 MLX5_RESUME_VHCA_IN_OP_MOD_RESUME_RESPONDER = 0x0, 12283 MLX5_RESUME_VHCA_IN_OP_MOD_RESUME_INITIATOR = 0x1, 12284 }; 12285 12286 struct mlx5_ifc_resume_vhca_in_bits { 12287 u8 opcode[0x10]; 12288 u8 uid[0x10]; 12289 12290 u8 reserved_at_20[0x10]; 12291 u8 op_mod[0x10]; 12292 12293 u8 reserved_at_40[0x10]; 12294 u8 vhca_id[0x10]; 12295 12296 u8 reserved_at_60[0x20]; 12297 }; 12298 12299 struct mlx5_ifc_resume_vhca_out_bits { 12300 u8 status[0x8]; 12301 u8 reserved_at_8[0x18]; 12302 12303 u8 syndrome[0x20]; 12304 12305 u8 reserved_at_40[0x40]; 12306 }; 12307 12308 struct mlx5_ifc_query_vhca_migration_state_in_bits { 12309 u8 opcode[0x10]; 12310 u8 uid[0x10]; 12311 12312 u8 reserved_at_20[0x10]; 12313 u8 op_mod[0x10]; 12314 12315 u8 incremental[0x1]; 12316 u8 reserved_at_41[0xf]; 12317 u8 vhca_id[0x10]; 12318 12319 u8 reserved_at_60[0x20]; 12320 }; 12321 12322 struct mlx5_ifc_query_vhca_migration_state_out_bits { 12323 u8 status[0x8]; 12324 u8 reserved_at_8[0x18]; 12325 12326 u8 syndrome[0x20]; 12327 12328 u8 reserved_at_40[0x40]; 12329 12330 u8 required_umem_size[0x20]; 12331 12332 u8 reserved_at_a0[0x160]; 12333 }; 12334 12335 struct mlx5_ifc_save_vhca_state_in_bits { 12336 u8 opcode[0x10]; 12337 u8 uid[0x10]; 12338 12339 u8 reserved_at_20[0x10]; 12340 u8 op_mod[0x10]; 12341 12342 u8 incremental[0x1]; 12343 u8 set_track[0x1]; 12344 u8 reserved_at_42[0xe]; 12345 u8 vhca_id[0x10]; 12346 12347 u8 reserved_at_60[0x20]; 12348 12349 u8 va[0x40]; 12350 12351 u8 mkey[0x20]; 12352 12353 u8 size[0x20]; 12354 }; 12355 12356 struct mlx5_ifc_save_vhca_state_out_bits { 12357 u8 status[0x8]; 12358 u8 reserved_at_8[0x18]; 12359 12360 u8 syndrome[0x20]; 12361 12362 u8 actual_image_size[0x20]; 12363 12364 u8 reserved_at_60[0x20]; 12365 }; 12366 12367 struct mlx5_ifc_load_vhca_state_in_bits { 12368 u8 opcode[0x10]; 12369 u8 uid[0x10]; 12370 12371 u8 reserved_at_20[0x10]; 12372 u8 op_mod[0x10]; 12373 12374 u8 reserved_at_40[0x10]; 12375 u8 vhca_id[0x10]; 12376 12377 u8 reserved_at_60[0x20]; 12378 12379 u8 va[0x40]; 12380 12381 u8 mkey[0x20]; 12382 12383 u8 size[0x20]; 12384 }; 12385 12386 struct mlx5_ifc_load_vhca_state_out_bits { 12387 u8 status[0x8]; 12388 u8 reserved_at_8[0x18]; 12389 12390 u8 syndrome[0x20]; 12391 12392 u8 reserved_at_40[0x40]; 12393 }; 12394 12395 struct mlx5_ifc_adv_virtualization_cap_bits { 12396 u8 reserved_at_0[0x3]; 12397 u8 pg_track_log_max_num[0x5]; 12398 u8 pg_track_max_num_range[0x8]; 12399 u8 pg_track_log_min_addr_space[0x8]; 12400 u8 pg_track_log_max_addr_space[0x8]; 12401 12402 u8 reserved_at_20[0x3]; 12403 u8 pg_track_log_min_msg_size[0x5]; 12404 u8 reserved_at_28[0x3]; 12405 u8 pg_track_log_max_msg_size[0x5]; 12406 u8 reserved_at_30[0x3]; 12407 u8 pg_track_log_min_page_size[0x5]; 12408 u8 reserved_at_38[0x3]; 12409 u8 pg_track_log_max_page_size[0x5]; 12410 12411 u8 reserved_at_40[0x7c0]; 12412 }; 12413 12414 struct mlx5_ifc_page_track_report_entry_bits { 12415 u8 dirty_address_high[0x20]; 12416 12417 u8 dirty_address_low[0x20]; 12418 }; 12419 12420 enum { 12421 MLX5_PAGE_TRACK_STATE_TRACKING, 12422 MLX5_PAGE_TRACK_STATE_REPORTING, 12423 MLX5_PAGE_TRACK_STATE_ERROR, 12424 }; 12425 12426 struct mlx5_ifc_page_track_range_bits { 12427 u8 start_address[0x40]; 12428 12429 u8 length[0x40]; 12430 }; 12431 12432 struct mlx5_ifc_page_track_bits { 12433 u8 modify_field_select[0x40]; 12434 12435 u8 reserved_at_40[0x10]; 12436 u8 vhca_id[0x10]; 12437 12438 u8 reserved_at_60[0x20]; 12439 12440 u8 state[0x4]; 12441 u8 track_type[0x4]; 12442 u8 log_addr_space_size[0x8]; 12443 u8 reserved_at_90[0x3]; 12444 u8 log_page_size[0x5]; 12445 u8 reserved_at_98[0x3]; 12446 u8 log_msg_size[0x5]; 12447 12448 u8 reserved_at_a0[0x8]; 12449 u8 reporting_qpn[0x18]; 12450 12451 u8 reserved_at_c0[0x18]; 12452 u8 num_ranges[0x8]; 12453 12454 u8 reserved_at_e0[0x20]; 12455 12456 u8 range_start_address[0x40]; 12457 12458 u8 length[0x40]; 12459 12460 struct mlx5_ifc_page_track_range_bits track_range[0]; 12461 }; 12462 12463 struct mlx5_ifc_create_page_track_obj_in_bits { 12464 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12465 struct mlx5_ifc_page_track_bits obj_context; 12466 }; 12467 12468 struct mlx5_ifc_modify_page_track_obj_in_bits { 12469 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12470 struct mlx5_ifc_page_track_bits obj_context; 12471 }; 12472 12473 #endif /* MLX5_IFC_H */ 12474