1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 #ifndef MLX5_IFC_H 33 #define MLX5_IFC_H 34 35 #include "mlx5_ifc_fpga.h" 36 37 enum { 38 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0, 39 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1, 40 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2, 41 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3, 42 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13, 43 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14, 44 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c, 45 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d, 46 MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4, 47 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5, 48 MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED = 0x7, 49 MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT = 0xc, 50 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10, 51 MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR = 0x11, 52 MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR = 0x12, 53 MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR = 0x8, 54 MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE = 0x9, 55 MLX5_EVENT_TYPE_CODING_GPIO_EVENT = 0x15, 56 MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19, 57 MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a, 58 MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT = 0x1b, 59 MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT = 0x1f, 60 MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa, 61 MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb, 62 MLX5_EVENT_TYPE_CODING_FPGA_ERROR = 0x20, 63 MLX5_EVENT_TYPE_CODING_FPGA_QP_ERROR = 0x21 64 }; 65 66 enum { 67 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0, 68 MLX5_SET_HCA_CAP_OP_MOD_ODP = 0x2, 69 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3, 70 MLX5_SET_HCA_CAP_OP_MOD_ROCE = 0x4, 71 }; 72 73 enum { 74 MLX5_SHARED_RESOURCE_UID = 0xffff, 75 }; 76 77 enum { 78 MLX5_OBJ_TYPE_SW_ICM = 0x0008, 79 }; 80 81 enum { 82 MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM = (1ULL << MLX5_OBJ_TYPE_SW_ICM), 83 MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT = (1ULL << 11), 84 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q = (1ULL << 13), 85 }; 86 87 enum { 88 MLX5_OBJ_TYPE_GENEVE_TLV_OPT = 0x000b, 89 MLX5_OBJ_TYPE_VIRTIO_NET_Q = 0x000d, 90 MLX5_OBJ_TYPE_MATCH_DEFINER = 0x0018, 91 MLX5_OBJ_TYPE_MKEY = 0xff01, 92 MLX5_OBJ_TYPE_QP = 0xff02, 93 MLX5_OBJ_TYPE_PSV = 0xff03, 94 MLX5_OBJ_TYPE_RMP = 0xff04, 95 MLX5_OBJ_TYPE_XRC_SRQ = 0xff05, 96 MLX5_OBJ_TYPE_RQ = 0xff06, 97 MLX5_OBJ_TYPE_SQ = 0xff07, 98 MLX5_OBJ_TYPE_TIR = 0xff08, 99 MLX5_OBJ_TYPE_TIS = 0xff09, 100 MLX5_OBJ_TYPE_DCT = 0xff0a, 101 MLX5_OBJ_TYPE_XRQ = 0xff0b, 102 MLX5_OBJ_TYPE_RQT = 0xff0e, 103 MLX5_OBJ_TYPE_FLOW_COUNTER = 0xff0f, 104 MLX5_OBJ_TYPE_CQ = 0xff10, 105 }; 106 107 enum { 108 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100, 109 MLX5_CMD_OP_QUERY_ADAPTER = 0x101, 110 MLX5_CMD_OP_INIT_HCA = 0x102, 111 MLX5_CMD_OP_TEARDOWN_HCA = 0x103, 112 MLX5_CMD_OP_ENABLE_HCA = 0x104, 113 MLX5_CMD_OP_DISABLE_HCA = 0x105, 114 MLX5_CMD_OP_QUERY_PAGES = 0x107, 115 MLX5_CMD_OP_MANAGE_PAGES = 0x108, 116 MLX5_CMD_OP_SET_HCA_CAP = 0x109, 117 MLX5_CMD_OP_QUERY_ISSI = 0x10a, 118 MLX5_CMD_OP_SET_ISSI = 0x10b, 119 MLX5_CMD_OP_SET_DRIVER_VERSION = 0x10d, 120 MLX5_CMD_OP_QUERY_SF_PARTITION = 0x111, 121 MLX5_CMD_OP_ALLOC_SF = 0x113, 122 MLX5_CMD_OP_DEALLOC_SF = 0x114, 123 MLX5_CMD_OP_CREATE_MKEY = 0x200, 124 MLX5_CMD_OP_QUERY_MKEY = 0x201, 125 MLX5_CMD_OP_DESTROY_MKEY = 0x202, 126 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203, 127 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204, 128 MLX5_CMD_OP_ALLOC_MEMIC = 0x205, 129 MLX5_CMD_OP_DEALLOC_MEMIC = 0x206, 130 MLX5_CMD_OP_MODIFY_MEMIC = 0x207, 131 MLX5_CMD_OP_CREATE_EQ = 0x301, 132 MLX5_CMD_OP_DESTROY_EQ = 0x302, 133 MLX5_CMD_OP_QUERY_EQ = 0x303, 134 MLX5_CMD_OP_GEN_EQE = 0x304, 135 MLX5_CMD_OP_CREATE_CQ = 0x400, 136 MLX5_CMD_OP_DESTROY_CQ = 0x401, 137 MLX5_CMD_OP_QUERY_CQ = 0x402, 138 MLX5_CMD_OP_MODIFY_CQ = 0x403, 139 MLX5_CMD_OP_CREATE_QP = 0x500, 140 MLX5_CMD_OP_DESTROY_QP = 0x501, 141 MLX5_CMD_OP_RST2INIT_QP = 0x502, 142 MLX5_CMD_OP_INIT2RTR_QP = 0x503, 143 MLX5_CMD_OP_RTR2RTS_QP = 0x504, 144 MLX5_CMD_OP_RTS2RTS_QP = 0x505, 145 MLX5_CMD_OP_SQERR2RTS_QP = 0x506, 146 MLX5_CMD_OP_2ERR_QP = 0x507, 147 MLX5_CMD_OP_2RST_QP = 0x50a, 148 MLX5_CMD_OP_QUERY_QP = 0x50b, 149 MLX5_CMD_OP_SQD_RTS_QP = 0x50c, 150 MLX5_CMD_OP_INIT2INIT_QP = 0x50e, 151 MLX5_CMD_OP_CREATE_PSV = 0x600, 152 MLX5_CMD_OP_DESTROY_PSV = 0x601, 153 MLX5_CMD_OP_CREATE_SRQ = 0x700, 154 MLX5_CMD_OP_DESTROY_SRQ = 0x701, 155 MLX5_CMD_OP_QUERY_SRQ = 0x702, 156 MLX5_CMD_OP_ARM_RQ = 0x703, 157 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705, 158 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706, 159 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707, 160 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708, 161 MLX5_CMD_OP_CREATE_DCT = 0x710, 162 MLX5_CMD_OP_DESTROY_DCT = 0x711, 163 MLX5_CMD_OP_DRAIN_DCT = 0x712, 164 MLX5_CMD_OP_QUERY_DCT = 0x713, 165 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714, 166 MLX5_CMD_OP_CREATE_XRQ = 0x717, 167 MLX5_CMD_OP_DESTROY_XRQ = 0x718, 168 MLX5_CMD_OP_QUERY_XRQ = 0x719, 169 MLX5_CMD_OP_ARM_XRQ = 0x71a, 170 MLX5_CMD_OP_QUERY_XRQ_DC_PARAMS_ENTRY = 0x725, 171 MLX5_CMD_OP_SET_XRQ_DC_PARAMS_ENTRY = 0x726, 172 MLX5_CMD_OP_QUERY_XRQ_ERROR_PARAMS = 0x727, 173 MLX5_CMD_OP_RELEASE_XRQ_ERROR = 0x729, 174 MLX5_CMD_OP_MODIFY_XRQ = 0x72a, 175 MLX5_CMD_OP_QUERY_ESW_FUNCTIONS = 0x740, 176 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750, 177 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751, 178 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752, 179 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753, 180 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754, 181 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755, 182 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760, 183 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761, 184 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762, 185 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763, 186 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764, 187 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765, 188 MLX5_CMD_OP_QUERY_VNIC_ENV = 0x76f, 189 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770, 190 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771, 191 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772, 192 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773, 193 MLX5_CMD_OP_SET_MONITOR_COUNTER = 0x774, 194 MLX5_CMD_OP_ARM_MONITOR_COUNTER = 0x775, 195 MLX5_CMD_OP_SET_PP_RATE_LIMIT = 0x780, 196 MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781, 197 MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT = 0x782, 198 MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT = 0x783, 199 MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT = 0x784, 200 MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT = 0x785, 201 MLX5_CMD_OP_CREATE_QOS_PARA_VPORT = 0x786, 202 MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT = 0x787, 203 MLX5_CMD_OP_ALLOC_PD = 0x800, 204 MLX5_CMD_OP_DEALLOC_PD = 0x801, 205 MLX5_CMD_OP_ALLOC_UAR = 0x802, 206 MLX5_CMD_OP_DEALLOC_UAR = 0x803, 207 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804, 208 MLX5_CMD_OP_ACCESS_REG = 0x805, 209 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806, 210 MLX5_CMD_OP_DETACH_FROM_MCG = 0x807, 211 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a, 212 MLX5_CMD_OP_MAD_IFC = 0x50d, 213 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b, 214 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c, 215 MLX5_CMD_OP_NOP = 0x80d, 216 MLX5_CMD_OP_ALLOC_XRCD = 0x80e, 217 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f, 218 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816, 219 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817, 220 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822, 221 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823, 222 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824, 223 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825, 224 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826, 225 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827, 226 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828, 227 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829, 228 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a, 229 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b, 230 MLX5_CMD_OP_SET_WOL_ROL = 0x830, 231 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831, 232 MLX5_CMD_OP_CREATE_LAG = 0x840, 233 MLX5_CMD_OP_MODIFY_LAG = 0x841, 234 MLX5_CMD_OP_QUERY_LAG = 0x842, 235 MLX5_CMD_OP_DESTROY_LAG = 0x843, 236 MLX5_CMD_OP_CREATE_VPORT_LAG = 0x844, 237 MLX5_CMD_OP_DESTROY_VPORT_LAG = 0x845, 238 MLX5_CMD_OP_CREATE_TIR = 0x900, 239 MLX5_CMD_OP_MODIFY_TIR = 0x901, 240 MLX5_CMD_OP_DESTROY_TIR = 0x902, 241 MLX5_CMD_OP_QUERY_TIR = 0x903, 242 MLX5_CMD_OP_CREATE_SQ = 0x904, 243 MLX5_CMD_OP_MODIFY_SQ = 0x905, 244 MLX5_CMD_OP_DESTROY_SQ = 0x906, 245 MLX5_CMD_OP_QUERY_SQ = 0x907, 246 MLX5_CMD_OP_CREATE_RQ = 0x908, 247 MLX5_CMD_OP_MODIFY_RQ = 0x909, 248 MLX5_CMD_OP_SET_DELAY_DROP_PARAMS = 0x910, 249 MLX5_CMD_OP_DESTROY_RQ = 0x90a, 250 MLX5_CMD_OP_QUERY_RQ = 0x90b, 251 MLX5_CMD_OP_CREATE_RMP = 0x90c, 252 MLX5_CMD_OP_MODIFY_RMP = 0x90d, 253 MLX5_CMD_OP_DESTROY_RMP = 0x90e, 254 MLX5_CMD_OP_QUERY_RMP = 0x90f, 255 MLX5_CMD_OP_CREATE_TIS = 0x912, 256 MLX5_CMD_OP_MODIFY_TIS = 0x913, 257 MLX5_CMD_OP_DESTROY_TIS = 0x914, 258 MLX5_CMD_OP_QUERY_TIS = 0x915, 259 MLX5_CMD_OP_CREATE_RQT = 0x916, 260 MLX5_CMD_OP_MODIFY_RQT = 0x917, 261 MLX5_CMD_OP_DESTROY_RQT = 0x918, 262 MLX5_CMD_OP_QUERY_RQT = 0x919, 263 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f, 264 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930, 265 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931, 266 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932, 267 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933, 268 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934, 269 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935, 270 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936, 271 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937, 272 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938, 273 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939, 274 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a, 275 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b, 276 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c, 277 MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT = 0x93d, 278 MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT = 0x93e, 279 MLX5_CMD_OP_QUERY_PACKET_REFORMAT_CONTEXT = 0x93f, 280 MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT = 0x940, 281 MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941, 282 MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT = 0x942, 283 MLX5_CMD_OP_FPGA_CREATE_QP = 0x960, 284 MLX5_CMD_OP_FPGA_MODIFY_QP = 0x961, 285 MLX5_CMD_OP_FPGA_QUERY_QP = 0x962, 286 MLX5_CMD_OP_FPGA_DESTROY_QP = 0x963, 287 MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS = 0x964, 288 MLX5_CMD_OP_CREATE_GENERAL_OBJECT = 0xa00, 289 MLX5_CMD_OP_MODIFY_GENERAL_OBJECT = 0xa01, 290 MLX5_CMD_OP_QUERY_GENERAL_OBJECT = 0xa02, 291 MLX5_CMD_OP_DESTROY_GENERAL_OBJECT = 0xa03, 292 MLX5_CMD_OP_CREATE_UCTX = 0xa04, 293 MLX5_CMD_OP_DESTROY_UCTX = 0xa06, 294 MLX5_CMD_OP_CREATE_UMEM = 0xa08, 295 MLX5_CMD_OP_DESTROY_UMEM = 0xa0a, 296 MLX5_CMD_OP_SYNC_STEERING = 0xb00, 297 MLX5_CMD_OP_QUERY_VHCA_STATE = 0xb0d, 298 MLX5_CMD_OP_MODIFY_VHCA_STATE = 0xb0e, 299 MLX5_CMD_OP_MAX 300 }; 301 302 /* Valid range for general commands that don't work over an object */ 303 enum { 304 MLX5_CMD_OP_GENERAL_START = 0xb00, 305 MLX5_CMD_OP_GENERAL_END = 0xd00, 306 }; 307 308 struct mlx5_ifc_flow_table_fields_supported_bits { 309 u8 outer_dmac[0x1]; 310 u8 outer_smac[0x1]; 311 u8 outer_ether_type[0x1]; 312 u8 outer_ip_version[0x1]; 313 u8 outer_first_prio[0x1]; 314 u8 outer_first_cfi[0x1]; 315 u8 outer_first_vid[0x1]; 316 u8 outer_ipv4_ttl[0x1]; 317 u8 outer_second_prio[0x1]; 318 u8 outer_second_cfi[0x1]; 319 u8 outer_second_vid[0x1]; 320 u8 reserved_at_b[0x1]; 321 u8 outer_sip[0x1]; 322 u8 outer_dip[0x1]; 323 u8 outer_frag[0x1]; 324 u8 outer_ip_protocol[0x1]; 325 u8 outer_ip_ecn[0x1]; 326 u8 outer_ip_dscp[0x1]; 327 u8 outer_udp_sport[0x1]; 328 u8 outer_udp_dport[0x1]; 329 u8 outer_tcp_sport[0x1]; 330 u8 outer_tcp_dport[0x1]; 331 u8 outer_tcp_flags[0x1]; 332 u8 outer_gre_protocol[0x1]; 333 u8 outer_gre_key[0x1]; 334 u8 outer_vxlan_vni[0x1]; 335 u8 outer_geneve_vni[0x1]; 336 u8 outer_geneve_oam[0x1]; 337 u8 outer_geneve_protocol_type[0x1]; 338 u8 outer_geneve_opt_len[0x1]; 339 u8 source_vhca_port[0x1]; 340 u8 source_eswitch_port[0x1]; 341 342 u8 inner_dmac[0x1]; 343 u8 inner_smac[0x1]; 344 u8 inner_ether_type[0x1]; 345 u8 inner_ip_version[0x1]; 346 u8 inner_first_prio[0x1]; 347 u8 inner_first_cfi[0x1]; 348 u8 inner_first_vid[0x1]; 349 u8 reserved_at_27[0x1]; 350 u8 inner_second_prio[0x1]; 351 u8 inner_second_cfi[0x1]; 352 u8 inner_second_vid[0x1]; 353 u8 reserved_at_2b[0x1]; 354 u8 inner_sip[0x1]; 355 u8 inner_dip[0x1]; 356 u8 inner_frag[0x1]; 357 u8 inner_ip_protocol[0x1]; 358 u8 inner_ip_ecn[0x1]; 359 u8 inner_ip_dscp[0x1]; 360 u8 inner_udp_sport[0x1]; 361 u8 inner_udp_dport[0x1]; 362 u8 inner_tcp_sport[0x1]; 363 u8 inner_tcp_dport[0x1]; 364 u8 inner_tcp_flags[0x1]; 365 u8 reserved_at_37[0x9]; 366 367 u8 geneve_tlv_option_0_data[0x1]; 368 u8 geneve_tlv_option_0_exist[0x1]; 369 u8 reserved_at_42[0x3]; 370 u8 outer_first_mpls_over_udp[0x4]; 371 u8 outer_first_mpls_over_gre[0x4]; 372 u8 inner_first_mpls[0x4]; 373 u8 outer_first_mpls[0x4]; 374 u8 reserved_at_55[0x2]; 375 u8 outer_esp_spi[0x1]; 376 u8 reserved_at_58[0x2]; 377 u8 bth_dst_qp[0x1]; 378 u8 reserved_at_5b[0x5]; 379 380 u8 reserved_at_60[0x18]; 381 u8 metadata_reg_c_7[0x1]; 382 u8 metadata_reg_c_6[0x1]; 383 u8 metadata_reg_c_5[0x1]; 384 u8 metadata_reg_c_4[0x1]; 385 u8 metadata_reg_c_3[0x1]; 386 u8 metadata_reg_c_2[0x1]; 387 u8 metadata_reg_c_1[0x1]; 388 u8 metadata_reg_c_0[0x1]; 389 }; 390 391 struct mlx5_ifc_flow_table_fields_supported_2_bits { 392 u8 reserved_at_0[0xe]; 393 u8 bth_opcode[0x1]; 394 u8 reserved_at_f[0x11]; 395 396 u8 reserved_at_20[0x60]; 397 }; 398 399 struct mlx5_ifc_flow_table_prop_layout_bits { 400 u8 ft_support[0x1]; 401 u8 reserved_at_1[0x1]; 402 u8 flow_counter[0x1]; 403 u8 flow_modify_en[0x1]; 404 u8 modify_root[0x1]; 405 u8 identified_miss_table_mode[0x1]; 406 u8 flow_table_modify[0x1]; 407 u8 reformat[0x1]; 408 u8 decap[0x1]; 409 u8 reserved_at_9[0x1]; 410 u8 pop_vlan[0x1]; 411 u8 push_vlan[0x1]; 412 u8 reserved_at_c[0x1]; 413 u8 pop_vlan_2[0x1]; 414 u8 push_vlan_2[0x1]; 415 u8 reformat_and_vlan_action[0x1]; 416 u8 reserved_at_10[0x1]; 417 u8 sw_owner[0x1]; 418 u8 reformat_l3_tunnel_to_l2[0x1]; 419 u8 reformat_l2_to_l3_tunnel[0x1]; 420 u8 reformat_and_modify_action[0x1]; 421 u8 ignore_flow_level[0x1]; 422 u8 reserved_at_16[0x1]; 423 u8 table_miss_action_domain[0x1]; 424 u8 termination_table[0x1]; 425 u8 reformat_and_fwd_to_table[0x1]; 426 u8 reserved_at_1a[0x2]; 427 u8 ipsec_encrypt[0x1]; 428 u8 ipsec_decrypt[0x1]; 429 u8 sw_owner_v2[0x1]; 430 u8 reserved_at_1f[0x1]; 431 432 u8 termination_table_raw_traffic[0x1]; 433 u8 reserved_at_21[0x1]; 434 u8 log_max_ft_size[0x6]; 435 u8 log_max_modify_header_context[0x8]; 436 u8 max_modify_header_actions[0x8]; 437 u8 max_ft_level[0x8]; 438 439 u8 reserved_at_40[0x20]; 440 441 u8 reserved_at_60[0x2]; 442 u8 reformat_insert[0x1]; 443 u8 reformat_remove[0x1]; 444 u8 reserver_at_64[0x14]; 445 u8 log_max_ft_num[0x8]; 446 447 u8 reserved_at_80[0x10]; 448 u8 log_max_flow_counter[0x8]; 449 u8 log_max_destination[0x8]; 450 451 u8 reserved_at_a0[0x18]; 452 u8 log_max_flow[0x8]; 453 454 u8 reserved_at_c0[0x40]; 455 456 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support; 457 458 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support; 459 }; 460 461 struct mlx5_ifc_odp_per_transport_service_cap_bits { 462 u8 send[0x1]; 463 u8 receive[0x1]; 464 u8 write[0x1]; 465 u8 read[0x1]; 466 u8 atomic[0x1]; 467 u8 srq_receive[0x1]; 468 u8 reserved_at_6[0x1a]; 469 }; 470 471 struct mlx5_ifc_fte_match_set_lyr_2_4_bits { 472 u8 smac_47_16[0x20]; 473 474 u8 smac_15_0[0x10]; 475 u8 ethertype[0x10]; 476 477 u8 dmac_47_16[0x20]; 478 479 u8 dmac_15_0[0x10]; 480 u8 first_prio[0x3]; 481 u8 first_cfi[0x1]; 482 u8 first_vid[0xc]; 483 484 u8 ip_protocol[0x8]; 485 u8 ip_dscp[0x6]; 486 u8 ip_ecn[0x2]; 487 u8 cvlan_tag[0x1]; 488 u8 svlan_tag[0x1]; 489 u8 frag[0x1]; 490 u8 ip_version[0x4]; 491 u8 tcp_flags[0x9]; 492 493 u8 tcp_sport[0x10]; 494 u8 tcp_dport[0x10]; 495 496 u8 reserved_at_c0[0x18]; 497 u8 ttl_hoplimit[0x8]; 498 499 u8 udp_sport[0x10]; 500 u8 udp_dport[0x10]; 501 502 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6; 503 504 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6; 505 }; 506 507 struct mlx5_ifc_nvgre_key_bits { 508 u8 hi[0x18]; 509 u8 lo[0x8]; 510 }; 511 512 union mlx5_ifc_gre_key_bits { 513 struct mlx5_ifc_nvgre_key_bits nvgre; 514 u8 key[0x20]; 515 }; 516 517 struct mlx5_ifc_fte_match_set_misc_bits { 518 u8 gre_c_present[0x1]; 519 u8 reserved_at_1[0x1]; 520 u8 gre_k_present[0x1]; 521 u8 gre_s_present[0x1]; 522 u8 source_vhca_port[0x4]; 523 u8 source_sqn[0x18]; 524 525 u8 source_eswitch_owner_vhca_id[0x10]; 526 u8 source_port[0x10]; 527 528 u8 outer_second_prio[0x3]; 529 u8 outer_second_cfi[0x1]; 530 u8 outer_second_vid[0xc]; 531 u8 inner_second_prio[0x3]; 532 u8 inner_second_cfi[0x1]; 533 u8 inner_second_vid[0xc]; 534 535 u8 outer_second_cvlan_tag[0x1]; 536 u8 inner_second_cvlan_tag[0x1]; 537 u8 outer_second_svlan_tag[0x1]; 538 u8 inner_second_svlan_tag[0x1]; 539 u8 reserved_at_64[0xc]; 540 u8 gre_protocol[0x10]; 541 542 union mlx5_ifc_gre_key_bits gre_key; 543 544 u8 vxlan_vni[0x18]; 545 u8 bth_opcode[0x8]; 546 547 u8 geneve_vni[0x18]; 548 u8 reserved_at_d8[0x6]; 549 u8 geneve_tlv_option_0_exist[0x1]; 550 u8 geneve_oam[0x1]; 551 552 u8 reserved_at_e0[0xc]; 553 u8 outer_ipv6_flow_label[0x14]; 554 555 u8 reserved_at_100[0xc]; 556 u8 inner_ipv6_flow_label[0x14]; 557 558 u8 reserved_at_120[0xa]; 559 u8 geneve_opt_len[0x6]; 560 u8 geneve_protocol_type[0x10]; 561 562 u8 reserved_at_140[0x8]; 563 u8 bth_dst_qp[0x18]; 564 u8 reserved_at_160[0x20]; 565 u8 outer_esp_spi[0x20]; 566 u8 reserved_at_1a0[0x60]; 567 }; 568 569 struct mlx5_ifc_fte_match_mpls_bits { 570 u8 mpls_label[0x14]; 571 u8 mpls_exp[0x3]; 572 u8 mpls_s_bos[0x1]; 573 u8 mpls_ttl[0x8]; 574 }; 575 576 struct mlx5_ifc_fte_match_set_misc2_bits { 577 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls; 578 579 struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls; 580 581 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre; 582 583 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp; 584 585 u8 metadata_reg_c_7[0x20]; 586 587 u8 metadata_reg_c_6[0x20]; 588 589 u8 metadata_reg_c_5[0x20]; 590 591 u8 metadata_reg_c_4[0x20]; 592 593 u8 metadata_reg_c_3[0x20]; 594 595 u8 metadata_reg_c_2[0x20]; 596 597 u8 metadata_reg_c_1[0x20]; 598 599 u8 metadata_reg_c_0[0x20]; 600 601 u8 metadata_reg_a[0x20]; 602 603 u8 reserved_at_1a0[0x60]; 604 }; 605 606 struct mlx5_ifc_fte_match_set_misc3_bits { 607 u8 inner_tcp_seq_num[0x20]; 608 609 u8 outer_tcp_seq_num[0x20]; 610 611 u8 inner_tcp_ack_num[0x20]; 612 613 u8 outer_tcp_ack_num[0x20]; 614 615 u8 reserved_at_80[0x8]; 616 u8 outer_vxlan_gpe_vni[0x18]; 617 618 u8 outer_vxlan_gpe_next_protocol[0x8]; 619 u8 outer_vxlan_gpe_flags[0x8]; 620 u8 reserved_at_b0[0x10]; 621 622 u8 icmp_header_data[0x20]; 623 624 u8 icmpv6_header_data[0x20]; 625 626 u8 icmp_type[0x8]; 627 u8 icmp_code[0x8]; 628 u8 icmpv6_type[0x8]; 629 u8 icmpv6_code[0x8]; 630 631 u8 geneve_tlv_option_0_data[0x20]; 632 633 u8 gtpu_teid[0x20]; 634 635 u8 gtpu_msg_type[0x8]; 636 u8 gtpu_msg_flags[0x8]; 637 u8 reserved_at_170[0x10]; 638 639 u8 gtpu_dw_2[0x20]; 640 641 u8 gtpu_first_ext_dw_0[0x20]; 642 643 u8 gtpu_dw_0[0x20]; 644 645 u8 reserved_at_1e0[0x20]; 646 }; 647 648 struct mlx5_ifc_fte_match_set_misc4_bits { 649 u8 prog_sample_field_value_0[0x20]; 650 651 u8 prog_sample_field_id_0[0x20]; 652 653 u8 prog_sample_field_value_1[0x20]; 654 655 u8 prog_sample_field_id_1[0x20]; 656 657 u8 prog_sample_field_value_2[0x20]; 658 659 u8 prog_sample_field_id_2[0x20]; 660 661 u8 prog_sample_field_value_3[0x20]; 662 663 u8 prog_sample_field_id_3[0x20]; 664 665 u8 reserved_at_100[0x100]; 666 }; 667 668 struct mlx5_ifc_fte_match_set_misc5_bits { 669 u8 macsec_tag_0[0x20]; 670 671 u8 macsec_tag_1[0x20]; 672 673 u8 macsec_tag_2[0x20]; 674 675 u8 macsec_tag_3[0x20]; 676 677 u8 tunnel_header_0[0x20]; 678 679 u8 tunnel_header_1[0x20]; 680 681 u8 tunnel_header_2[0x20]; 682 683 u8 tunnel_header_3[0x20]; 684 685 u8 reserved_at_100[0x100]; 686 }; 687 688 struct mlx5_ifc_cmd_pas_bits { 689 u8 pa_h[0x20]; 690 691 u8 pa_l[0x14]; 692 u8 reserved_at_34[0xc]; 693 }; 694 695 struct mlx5_ifc_uint64_bits { 696 u8 hi[0x20]; 697 698 u8 lo[0x20]; 699 }; 700 701 enum { 702 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0, 703 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7, 704 MLX5_ADS_STAT_RATE_10GBPS = 0x8, 705 MLX5_ADS_STAT_RATE_30GBPS = 0x9, 706 MLX5_ADS_STAT_RATE_5GBPS = 0xa, 707 MLX5_ADS_STAT_RATE_20GBPS = 0xb, 708 MLX5_ADS_STAT_RATE_40GBPS = 0xc, 709 MLX5_ADS_STAT_RATE_60GBPS = 0xd, 710 MLX5_ADS_STAT_RATE_80GBPS = 0xe, 711 MLX5_ADS_STAT_RATE_120GBPS = 0xf, 712 }; 713 714 struct mlx5_ifc_ads_bits { 715 u8 fl[0x1]; 716 u8 free_ar[0x1]; 717 u8 reserved_at_2[0xe]; 718 u8 pkey_index[0x10]; 719 720 u8 reserved_at_20[0x8]; 721 u8 grh[0x1]; 722 u8 mlid[0x7]; 723 u8 rlid[0x10]; 724 725 u8 ack_timeout[0x5]; 726 u8 reserved_at_45[0x3]; 727 u8 src_addr_index[0x8]; 728 u8 reserved_at_50[0x4]; 729 u8 stat_rate[0x4]; 730 u8 hop_limit[0x8]; 731 732 u8 reserved_at_60[0x4]; 733 u8 tclass[0x8]; 734 u8 flow_label[0x14]; 735 736 u8 rgid_rip[16][0x8]; 737 738 u8 reserved_at_100[0x4]; 739 u8 f_dscp[0x1]; 740 u8 f_ecn[0x1]; 741 u8 reserved_at_106[0x1]; 742 u8 f_eth_prio[0x1]; 743 u8 ecn[0x2]; 744 u8 dscp[0x6]; 745 u8 udp_sport[0x10]; 746 747 u8 dei_cfi[0x1]; 748 u8 eth_prio[0x3]; 749 u8 sl[0x4]; 750 u8 vhca_port_num[0x8]; 751 u8 rmac_47_32[0x10]; 752 753 u8 rmac_31_0[0x20]; 754 }; 755 756 struct mlx5_ifc_flow_table_nic_cap_bits { 757 u8 nic_rx_multi_path_tirs[0x1]; 758 u8 nic_rx_multi_path_tirs_fts[0x1]; 759 u8 allow_sniffer_and_nic_rx_shared_tir[0x1]; 760 u8 reserved_at_3[0x4]; 761 u8 sw_owner_reformat_supported[0x1]; 762 u8 reserved_at_8[0x18]; 763 764 u8 encap_general_header[0x1]; 765 u8 reserved_at_21[0xa]; 766 u8 log_max_packet_reformat_context[0x5]; 767 u8 reserved_at_30[0x6]; 768 u8 max_encap_header_size[0xa]; 769 u8 reserved_at_40[0x1c0]; 770 771 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive; 772 773 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_rdma; 774 775 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer; 776 777 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit; 778 779 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_rdma; 780 781 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer; 782 783 u8 reserved_at_e00[0x700]; 784 785 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_receive_rdma; 786 787 u8 reserved_at_1580[0x280]; 788 789 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_transmit_rdma; 790 791 u8 reserved_at_1880[0x780]; 792 793 u8 sw_steering_nic_rx_action_drop_icm_address[0x40]; 794 795 u8 sw_steering_nic_tx_action_drop_icm_address[0x40]; 796 797 u8 sw_steering_nic_tx_action_allow_icm_address[0x40]; 798 799 u8 reserved_at_20c0[0x5f40]; 800 }; 801 802 struct mlx5_ifc_port_selection_cap_bits { 803 u8 reserved_at_0[0x10]; 804 u8 port_select_flow_table[0x1]; 805 u8 reserved_at_11[0xf]; 806 807 u8 reserved_at_20[0x1e0]; 808 809 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_port_selection; 810 811 u8 reserved_at_400[0x7c00]; 812 }; 813 814 enum { 815 MLX5_FDB_TO_VPORT_REG_C_0 = 0x01, 816 MLX5_FDB_TO_VPORT_REG_C_1 = 0x02, 817 MLX5_FDB_TO_VPORT_REG_C_2 = 0x04, 818 MLX5_FDB_TO_VPORT_REG_C_3 = 0x08, 819 MLX5_FDB_TO_VPORT_REG_C_4 = 0x10, 820 MLX5_FDB_TO_VPORT_REG_C_5 = 0x20, 821 MLX5_FDB_TO_VPORT_REG_C_6 = 0x40, 822 MLX5_FDB_TO_VPORT_REG_C_7 = 0x80, 823 }; 824 825 struct mlx5_ifc_flow_table_eswitch_cap_bits { 826 u8 fdb_to_vport_reg_c_id[0x8]; 827 u8 reserved_at_8[0xd]; 828 u8 fdb_modify_header_fwd_to_table[0x1]; 829 u8 fdb_ipv4_ttl_modify[0x1]; 830 u8 flow_source[0x1]; 831 u8 reserved_at_18[0x2]; 832 u8 multi_fdb_encap[0x1]; 833 u8 egress_acl_forward_to_vport[0x1]; 834 u8 fdb_multi_path_to_table[0x1]; 835 u8 reserved_at_1d[0x3]; 836 837 u8 reserved_at_20[0x1e0]; 838 839 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb; 840 841 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress; 842 843 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress; 844 845 u8 reserved_at_800[0x1000]; 846 847 u8 sw_steering_fdb_action_drop_icm_address_rx[0x40]; 848 849 u8 sw_steering_fdb_action_drop_icm_address_tx[0x40]; 850 851 u8 sw_steering_uplink_icm_address_rx[0x40]; 852 853 u8 sw_steering_uplink_icm_address_tx[0x40]; 854 855 u8 reserved_at_1900[0x6700]; 856 }; 857 858 enum { 859 MLX5_COUNTER_SOURCE_ESWITCH = 0x0, 860 MLX5_COUNTER_FLOW_ESWITCH = 0x1, 861 }; 862 863 struct mlx5_ifc_e_switch_cap_bits { 864 u8 vport_svlan_strip[0x1]; 865 u8 vport_cvlan_strip[0x1]; 866 u8 vport_svlan_insert[0x1]; 867 u8 vport_cvlan_insert_if_not_exist[0x1]; 868 u8 vport_cvlan_insert_overwrite[0x1]; 869 u8 reserved_at_5[0x2]; 870 u8 esw_shared_ingress_acl[0x1]; 871 u8 esw_uplink_ingress_acl[0x1]; 872 u8 root_ft_on_other_esw[0x1]; 873 u8 reserved_at_a[0xf]; 874 u8 esw_functions_changed[0x1]; 875 u8 reserved_at_1a[0x1]; 876 u8 ecpf_vport_exists[0x1]; 877 u8 counter_eswitch_affinity[0x1]; 878 u8 merged_eswitch[0x1]; 879 u8 nic_vport_node_guid_modify[0x1]; 880 u8 nic_vport_port_guid_modify[0x1]; 881 882 u8 vxlan_encap_decap[0x1]; 883 u8 nvgre_encap_decap[0x1]; 884 u8 reserved_at_22[0x1]; 885 u8 log_max_fdb_encap_uplink[0x5]; 886 u8 reserved_at_21[0x3]; 887 u8 log_max_packet_reformat_context[0x5]; 888 u8 reserved_2b[0x6]; 889 u8 max_encap_header_size[0xa]; 890 891 u8 reserved_at_40[0xb]; 892 u8 log_max_esw_sf[0x5]; 893 u8 esw_sf_base_id[0x10]; 894 895 u8 reserved_at_60[0x7a0]; 896 897 }; 898 899 struct mlx5_ifc_qos_cap_bits { 900 u8 packet_pacing[0x1]; 901 u8 esw_scheduling[0x1]; 902 u8 esw_bw_share[0x1]; 903 u8 esw_rate_limit[0x1]; 904 u8 reserved_at_4[0x1]; 905 u8 packet_pacing_burst_bound[0x1]; 906 u8 packet_pacing_typical_size[0x1]; 907 u8 reserved_at_7[0x1]; 908 u8 nic_sq_scheduling[0x1]; 909 u8 nic_bw_share[0x1]; 910 u8 nic_rate_limit[0x1]; 911 u8 packet_pacing_uid[0x1]; 912 u8 log_esw_max_sched_depth[0x4]; 913 u8 reserved_at_10[0x10]; 914 915 u8 reserved_at_20[0xb]; 916 u8 log_max_qos_nic_queue_group[0x5]; 917 u8 reserved_at_30[0x10]; 918 919 u8 packet_pacing_max_rate[0x20]; 920 921 u8 packet_pacing_min_rate[0x20]; 922 923 u8 reserved_at_80[0x10]; 924 u8 packet_pacing_rate_table_size[0x10]; 925 926 u8 esw_element_type[0x10]; 927 u8 esw_tsar_type[0x10]; 928 929 u8 reserved_at_c0[0x10]; 930 u8 max_qos_para_vport[0x10]; 931 932 u8 max_tsar_bw_share[0x20]; 933 934 u8 reserved_at_100[0x700]; 935 }; 936 937 struct mlx5_ifc_debug_cap_bits { 938 u8 core_dump_general[0x1]; 939 u8 core_dump_qp[0x1]; 940 u8 reserved_at_2[0x7]; 941 u8 resource_dump[0x1]; 942 u8 reserved_at_a[0x16]; 943 944 u8 reserved_at_20[0x2]; 945 u8 stall_detect[0x1]; 946 u8 reserved_at_23[0x1d]; 947 948 u8 reserved_at_40[0x7c0]; 949 }; 950 951 struct mlx5_ifc_per_protocol_networking_offload_caps_bits { 952 u8 csum_cap[0x1]; 953 u8 vlan_cap[0x1]; 954 u8 lro_cap[0x1]; 955 u8 lro_psh_flag[0x1]; 956 u8 lro_time_stamp[0x1]; 957 u8 reserved_at_5[0x2]; 958 u8 wqe_vlan_insert[0x1]; 959 u8 self_lb_en_modifiable[0x1]; 960 u8 reserved_at_9[0x2]; 961 u8 max_lso_cap[0x5]; 962 u8 multi_pkt_send_wqe[0x2]; 963 u8 wqe_inline_mode[0x2]; 964 u8 rss_ind_tbl_cap[0x4]; 965 u8 reg_umr_sq[0x1]; 966 u8 scatter_fcs[0x1]; 967 u8 enhanced_multi_pkt_send_wqe[0x1]; 968 u8 tunnel_lso_const_out_ip_id[0x1]; 969 u8 tunnel_lro_gre[0x1]; 970 u8 tunnel_lro_vxlan[0x1]; 971 u8 tunnel_stateless_gre[0x1]; 972 u8 tunnel_stateless_vxlan[0x1]; 973 974 u8 swp[0x1]; 975 u8 swp_csum[0x1]; 976 u8 swp_lso[0x1]; 977 u8 cqe_checksum_full[0x1]; 978 u8 tunnel_stateless_geneve_tx[0x1]; 979 u8 tunnel_stateless_mpls_over_udp[0x1]; 980 u8 tunnel_stateless_mpls_over_gre[0x1]; 981 u8 tunnel_stateless_vxlan_gpe[0x1]; 982 u8 tunnel_stateless_ipv4_over_vxlan[0x1]; 983 u8 tunnel_stateless_ip_over_ip[0x1]; 984 u8 insert_trailer[0x1]; 985 u8 reserved_at_2b[0x1]; 986 u8 tunnel_stateless_ip_over_ip_rx[0x1]; 987 u8 tunnel_stateless_ip_over_ip_tx[0x1]; 988 u8 reserved_at_2e[0x2]; 989 u8 max_vxlan_udp_ports[0x8]; 990 u8 reserved_at_38[0x6]; 991 u8 max_geneve_opt_len[0x1]; 992 u8 tunnel_stateless_geneve_rx[0x1]; 993 994 u8 reserved_at_40[0x10]; 995 u8 lro_min_mss_size[0x10]; 996 997 u8 reserved_at_60[0x120]; 998 999 u8 lro_timer_supported_periods[4][0x20]; 1000 1001 u8 reserved_at_200[0x600]; 1002 }; 1003 1004 enum { 1005 MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING = 0x0, 1006 MLX5_TIMESTAMP_FORMAT_CAP_REAL_TIME = 0x1, 1007 MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING_AND_REAL_TIME = 0x2, 1008 }; 1009 1010 struct mlx5_ifc_roce_cap_bits { 1011 u8 roce_apm[0x1]; 1012 u8 reserved_at_1[0x3]; 1013 u8 sw_r_roce_src_udp_port[0x1]; 1014 u8 fl_rc_qp_when_roce_disabled[0x1]; 1015 u8 fl_rc_qp_when_roce_enabled[0x1]; 1016 u8 reserved_at_7[0x17]; 1017 u8 qp_ts_format[0x2]; 1018 1019 u8 reserved_at_20[0x60]; 1020 1021 u8 reserved_at_80[0xc]; 1022 u8 l3_type[0x4]; 1023 u8 reserved_at_90[0x8]; 1024 u8 roce_version[0x8]; 1025 1026 u8 reserved_at_a0[0x10]; 1027 u8 r_roce_dest_udp_port[0x10]; 1028 1029 u8 r_roce_max_src_udp_port[0x10]; 1030 u8 r_roce_min_src_udp_port[0x10]; 1031 1032 u8 reserved_at_e0[0x10]; 1033 u8 roce_address_table_size[0x10]; 1034 1035 u8 reserved_at_100[0x700]; 1036 }; 1037 1038 struct mlx5_ifc_sync_steering_in_bits { 1039 u8 opcode[0x10]; 1040 u8 uid[0x10]; 1041 1042 u8 reserved_at_20[0x10]; 1043 u8 op_mod[0x10]; 1044 1045 u8 reserved_at_40[0xc0]; 1046 }; 1047 1048 struct mlx5_ifc_sync_steering_out_bits { 1049 u8 status[0x8]; 1050 u8 reserved_at_8[0x18]; 1051 1052 u8 syndrome[0x20]; 1053 1054 u8 reserved_at_40[0x40]; 1055 }; 1056 1057 struct mlx5_ifc_device_mem_cap_bits { 1058 u8 memic[0x1]; 1059 u8 reserved_at_1[0x1f]; 1060 1061 u8 reserved_at_20[0xb]; 1062 u8 log_min_memic_alloc_size[0x5]; 1063 u8 reserved_at_30[0x8]; 1064 u8 log_max_memic_addr_alignment[0x8]; 1065 1066 u8 memic_bar_start_addr[0x40]; 1067 1068 u8 memic_bar_size[0x20]; 1069 1070 u8 max_memic_size[0x20]; 1071 1072 u8 steering_sw_icm_start_address[0x40]; 1073 1074 u8 reserved_at_100[0x8]; 1075 u8 log_header_modify_sw_icm_size[0x8]; 1076 u8 reserved_at_110[0x2]; 1077 u8 log_sw_icm_alloc_granularity[0x6]; 1078 u8 log_steering_sw_icm_size[0x8]; 1079 1080 u8 reserved_at_120[0x20]; 1081 1082 u8 header_modify_sw_icm_start_address[0x40]; 1083 1084 u8 reserved_at_180[0x80]; 1085 1086 u8 memic_operations[0x20]; 1087 1088 u8 reserved_at_220[0x5e0]; 1089 }; 1090 1091 struct mlx5_ifc_device_event_cap_bits { 1092 u8 user_affiliated_events[4][0x40]; 1093 1094 u8 user_unaffiliated_events[4][0x40]; 1095 }; 1096 1097 struct mlx5_ifc_virtio_emulation_cap_bits { 1098 u8 desc_tunnel_offload_type[0x1]; 1099 u8 eth_frame_offload_type[0x1]; 1100 u8 virtio_version_1_0[0x1]; 1101 u8 device_features_bits_mask[0xd]; 1102 u8 event_mode[0x8]; 1103 u8 virtio_queue_type[0x8]; 1104 1105 u8 max_tunnel_desc[0x10]; 1106 u8 reserved_at_30[0x3]; 1107 u8 log_doorbell_stride[0x5]; 1108 u8 reserved_at_38[0x3]; 1109 u8 log_doorbell_bar_size[0x5]; 1110 1111 u8 doorbell_bar_offset[0x40]; 1112 1113 u8 max_emulated_devices[0x8]; 1114 u8 max_num_virtio_queues[0x18]; 1115 1116 u8 reserved_at_a0[0x60]; 1117 1118 u8 umem_1_buffer_param_a[0x20]; 1119 1120 u8 umem_1_buffer_param_b[0x20]; 1121 1122 u8 umem_2_buffer_param_a[0x20]; 1123 1124 u8 umem_2_buffer_param_b[0x20]; 1125 1126 u8 umem_3_buffer_param_a[0x20]; 1127 1128 u8 umem_3_buffer_param_b[0x20]; 1129 1130 u8 reserved_at_1c0[0x640]; 1131 }; 1132 1133 enum { 1134 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0, 1135 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2, 1136 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4, 1137 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8, 1138 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10, 1139 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20, 1140 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40, 1141 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80, 1142 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100, 1143 }; 1144 1145 enum { 1146 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1, 1147 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2, 1148 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4, 1149 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8, 1150 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10, 1151 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20, 1152 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40, 1153 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80, 1154 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100, 1155 }; 1156 1157 struct mlx5_ifc_atomic_caps_bits { 1158 u8 reserved_at_0[0x40]; 1159 1160 u8 atomic_req_8B_endianness_mode[0x2]; 1161 u8 reserved_at_42[0x4]; 1162 u8 supported_atomic_req_8B_endianness_mode_1[0x1]; 1163 1164 u8 reserved_at_47[0x19]; 1165 1166 u8 reserved_at_60[0x20]; 1167 1168 u8 reserved_at_80[0x10]; 1169 u8 atomic_operations[0x10]; 1170 1171 u8 reserved_at_a0[0x10]; 1172 u8 atomic_size_qp[0x10]; 1173 1174 u8 reserved_at_c0[0x10]; 1175 u8 atomic_size_dc[0x10]; 1176 1177 u8 reserved_at_e0[0x720]; 1178 }; 1179 1180 struct mlx5_ifc_odp_cap_bits { 1181 u8 reserved_at_0[0x40]; 1182 1183 u8 sig[0x1]; 1184 u8 reserved_at_41[0x1f]; 1185 1186 u8 reserved_at_60[0x20]; 1187 1188 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps; 1189 1190 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps; 1191 1192 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps; 1193 1194 struct mlx5_ifc_odp_per_transport_service_cap_bits xrc_odp_caps; 1195 1196 struct mlx5_ifc_odp_per_transport_service_cap_bits dc_odp_caps; 1197 1198 u8 reserved_at_120[0x6E0]; 1199 }; 1200 1201 struct mlx5_ifc_calc_op { 1202 u8 reserved_at_0[0x10]; 1203 u8 reserved_at_10[0x9]; 1204 u8 op_swap_endianness[0x1]; 1205 u8 op_min[0x1]; 1206 u8 op_xor[0x1]; 1207 u8 op_or[0x1]; 1208 u8 op_and[0x1]; 1209 u8 op_max[0x1]; 1210 u8 op_add[0x1]; 1211 }; 1212 1213 struct mlx5_ifc_vector_calc_cap_bits { 1214 u8 calc_matrix[0x1]; 1215 u8 reserved_at_1[0x1f]; 1216 u8 reserved_at_20[0x8]; 1217 u8 max_vec_count[0x8]; 1218 u8 reserved_at_30[0xd]; 1219 u8 max_chunk_size[0x3]; 1220 struct mlx5_ifc_calc_op calc0; 1221 struct mlx5_ifc_calc_op calc1; 1222 struct mlx5_ifc_calc_op calc2; 1223 struct mlx5_ifc_calc_op calc3; 1224 1225 u8 reserved_at_c0[0x720]; 1226 }; 1227 1228 struct mlx5_ifc_tls_cap_bits { 1229 u8 tls_1_2_aes_gcm_128[0x1]; 1230 u8 tls_1_3_aes_gcm_128[0x1]; 1231 u8 tls_1_2_aes_gcm_256[0x1]; 1232 u8 tls_1_3_aes_gcm_256[0x1]; 1233 u8 reserved_at_4[0x1c]; 1234 1235 u8 reserved_at_20[0x7e0]; 1236 }; 1237 1238 struct mlx5_ifc_ipsec_cap_bits { 1239 u8 ipsec_full_offload[0x1]; 1240 u8 ipsec_crypto_offload[0x1]; 1241 u8 ipsec_esn[0x1]; 1242 u8 ipsec_crypto_esp_aes_gcm_256_encrypt[0x1]; 1243 u8 ipsec_crypto_esp_aes_gcm_128_encrypt[0x1]; 1244 u8 ipsec_crypto_esp_aes_gcm_256_decrypt[0x1]; 1245 u8 ipsec_crypto_esp_aes_gcm_128_decrypt[0x1]; 1246 u8 reserved_at_7[0x4]; 1247 u8 log_max_ipsec_offload[0x5]; 1248 u8 reserved_at_10[0x10]; 1249 1250 u8 min_log_ipsec_full_replay_window[0x8]; 1251 u8 max_log_ipsec_full_replay_window[0x8]; 1252 u8 reserved_at_30[0x7d0]; 1253 }; 1254 1255 enum { 1256 MLX5_WQ_TYPE_LINKED_LIST = 0x0, 1257 MLX5_WQ_TYPE_CYCLIC = 0x1, 1258 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2, 1259 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3, 1260 }; 1261 1262 enum { 1263 MLX5_WQ_END_PAD_MODE_NONE = 0x0, 1264 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1, 1265 }; 1266 1267 enum { 1268 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0, 1269 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1, 1270 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2, 1271 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3, 1272 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4, 1273 }; 1274 1275 enum { 1276 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0, 1277 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1, 1278 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2, 1279 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3, 1280 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4, 1281 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5, 1282 }; 1283 1284 enum { 1285 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0, 1286 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1, 1287 }; 1288 1289 enum { 1290 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0, 1291 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1, 1292 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3, 1293 }; 1294 1295 enum { 1296 MLX5_CAP_PORT_TYPE_IB = 0x0, 1297 MLX5_CAP_PORT_TYPE_ETH = 0x1, 1298 }; 1299 1300 enum { 1301 MLX5_CAP_UMR_FENCE_STRONG = 0x0, 1302 MLX5_CAP_UMR_FENCE_SMALL = 0x1, 1303 MLX5_CAP_UMR_FENCE_NONE = 0x2, 1304 }; 1305 1306 enum { 1307 MLX5_FLEX_PARSER_GENEVE_ENABLED = 1 << 3, 1308 MLX5_FLEX_PARSER_MPLS_OVER_GRE_ENABLED = 1 << 4, 1309 MLX5_FLEX_PARSER_MPLS_OVER_UDP_ENABLED = 1 << 5, 1310 MLX5_FLEX_PARSER_VXLAN_GPE_ENABLED = 1 << 7, 1311 MLX5_FLEX_PARSER_ICMP_V4_ENABLED = 1 << 8, 1312 MLX5_FLEX_PARSER_ICMP_V6_ENABLED = 1 << 9, 1313 MLX5_FLEX_PARSER_GENEVE_TLV_OPTION_0_ENABLED = 1 << 10, 1314 MLX5_FLEX_PARSER_GTPU_ENABLED = 1 << 11, 1315 MLX5_FLEX_PARSER_GTPU_DW_2_ENABLED = 1 << 16, 1316 MLX5_FLEX_PARSER_GTPU_FIRST_EXT_DW_0_ENABLED = 1 << 17, 1317 MLX5_FLEX_PARSER_GTPU_DW_0_ENABLED = 1 << 18, 1318 MLX5_FLEX_PARSER_GTPU_TEID_ENABLED = 1 << 19, 1319 }; 1320 1321 enum { 1322 MLX5_UCTX_CAP_RAW_TX = 1UL << 0, 1323 MLX5_UCTX_CAP_INTERNAL_DEV_RES = 1UL << 1, 1324 }; 1325 1326 #define MLX5_FC_BULK_SIZE_FACTOR 128 1327 1328 enum mlx5_fc_bulk_alloc_bitmask { 1329 MLX5_FC_BULK_128 = (1 << 0), 1330 MLX5_FC_BULK_256 = (1 << 1), 1331 MLX5_FC_BULK_512 = (1 << 2), 1332 MLX5_FC_BULK_1024 = (1 << 3), 1333 MLX5_FC_BULK_2048 = (1 << 4), 1334 MLX5_FC_BULK_4096 = (1 << 5), 1335 MLX5_FC_BULK_8192 = (1 << 6), 1336 MLX5_FC_BULK_16384 = (1 << 7), 1337 }; 1338 1339 #define MLX5_FC_BULK_NUM_FCS(fc_enum) (MLX5_FC_BULK_SIZE_FACTOR * (fc_enum)) 1340 1341 #define MLX5_FT_MAX_MULTIPATH_LEVEL 63 1342 1343 enum { 1344 MLX5_STEERING_FORMAT_CONNECTX_5 = 0, 1345 MLX5_STEERING_FORMAT_CONNECTX_6DX = 1, 1346 }; 1347 1348 struct mlx5_ifc_cmd_hca_cap_bits { 1349 u8 reserved_at_0[0x1f]; 1350 u8 vhca_resource_manager[0x1]; 1351 1352 u8 hca_cap_2[0x1]; 1353 u8 reserved_at_21[0x1]; 1354 u8 dtor[0x1]; 1355 u8 event_on_vhca_state_teardown_request[0x1]; 1356 u8 event_on_vhca_state_in_use[0x1]; 1357 u8 event_on_vhca_state_active[0x1]; 1358 u8 event_on_vhca_state_allocated[0x1]; 1359 u8 event_on_vhca_state_invalid[0x1]; 1360 u8 reserved_at_28[0x8]; 1361 u8 vhca_id[0x10]; 1362 1363 u8 reserved_at_40[0x40]; 1364 1365 u8 log_max_srq_sz[0x8]; 1366 u8 log_max_qp_sz[0x8]; 1367 u8 event_cap[0x1]; 1368 u8 reserved_at_91[0x2]; 1369 u8 isolate_vl_tc_new[0x1]; 1370 u8 reserved_at_94[0x4]; 1371 u8 prio_tag_required[0x1]; 1372 u8 reserved_at_99[0x2]; 1373 u8 log_max_qp[0x5]; 1374 1375 u8 reserved_at_a0[0x3]; 1376 u8 ece_support[0x1]; 1377 u8 reserved_at_a4[0x5]; 1378 u8 reg_c_preserve[0x1]; 1379 u8 reserved_at_aa[0x1]; 1380 u8 log_max_srq[0x5]; 1381 u8 reserved_at_b0[0x1]; 1382 u8 uplink_follow[0x1]; 1383 u8 ts_cqe_to_dest_cqn[0x1]; 1384 u8 reserved_at_b3[0x7]; 1385 u8 shampo[0x1]; 1386 u8 reserved_at_bb[0x5]; 1387 1388 u8 max_sgl_for_optimized_performance[0x8]; 1389 u8 log_max_cq_sz[0x8]; 1390 u8 relaxed_ordering_write_umr[0x1]; 1391 u8 relaxed_ordering_read_umr[0x1]; 1392 u8 reserved_at_d2[0x7]; 1393 u8 virtio_net_device_emualtion_manager[0x1]; 1394 u8 virtio_blk_device_emualtion_manager[0x1]; 1395 u8 log_max_cq[0x5]; 1396 1397 u8 log_max_eq_sz[0x8]; 1398 u8 relaxed_ordering_write[0x1]; 1399 u8 relaxed_ordering_read[0x1]; 1400 u8 log_max_mkey[0x6]; 1401 u8 reserved_at_f0[0x8]; 1402 u8 dump_fill_mkey[0x1]; 1403 u8 reserved_at_f9[0x2]; 1404 u8 fast_teardown[0x1]; 1405 u8 log_max_eq[0x4]; 1406 1407 u8 max_indirection[0x8]; 1408 u8 fixed_buffer_size[0x1]; 1409 u8 log_max_mrw_sz[0x7]; 1410 u8 force_teardown[0x1]; 1411 u8 reserved_at_111[0x1]; 1412 u8 log_max_bsf_list_size[0x6]; 1413 u8 umr_extended_translation_offset[0x1]; 1414 u8 null_mkey[0x1]; 1415 u8 log_max_klm_list_size[0x6]; 1416 1417 u8 reserved_at_120[0xa]; 1418 u8 log_max_ra_req_dc[0x6]; 1419 u8 reserved_at_130[0xa]; 1420 u8 log_max_ra_res_dc[0x6]; 1421 1422 u8 reserved_at_140[0x6]; 1423 u8 release_all_pages[0x1]; 1424 u8 reserved_at_147[0x2]; 1425 u8 roce_accl[0x1]; 1426 u8 log_max_ra_req_qp[0x6]; 1427 u8 reserved_at_150[0xa]; 1428 u8 log_max_ra_res_qp[0x6]; 1429 1430 u8 end_pad[0x1]; 1431 u8 cc_query_allowed[0x1]; 1432 u8 cc_modify_allowed[0x1]; 1433 u8 start_pad[0x1]; 1434 u8 cache_line_128byte[0x1]; 1435 u8 reserved_at_165[0x4]; 1436 u8 rts2rts_qp_counters_set_id[0x1]; 1437 u8 reserved_at_16a[0x2]; 1438 u8 vnic_env_int_rq_oob[0x1]; 1439 u8 sbcam_reg[0x1]; 1440 u8 reserved_at_16e[0x1]; 1441 u8 qcam_reg[0x1]; 1442 u8 gid_table_size[0x10]; 1443 1444 u8 out_of_seq_cnt[0x1]; 1445 u8 vport_counters[0x1]; 1446 u8 retransmission_q_counters[0x1]; 1447 u8 debug[0x1]; 1448 u8 modify_rq_counter_set_id[0x1]; 1449 u8 rq_delay_drop[0x1]; 1450 u8 max_qp_cnt[0xa]; 1451 u8 pkey_table_size[0x10]; 1452 1453 u8 vport_group_manager[0x1]; 1454 u8 vhca_group_manager[0x1]; 1455 u8 ib_virt[0x1]; 1456 u8 eth_virt[0x1]; 1457 u8 vnic_env_queue_counters[0x1]; 1458 u8 ets[0x1]; 1459 u8 nic_flow_table[0x1]; 1460 u8 eswitch_manager[0x1]; 1461 u8 device_memory[0x1]; 1462 u8 mcam_reg[0x1]; 1463 u8 pcam_reg[0x1]; 1464 u8 local_ca_ack_delay[0x5]; 1465 u8 port_module_event[0x1]; 1466 u8 enhanced_error_q_counters[0x1]; 1467 u8 ports_check[0x1]; 1468 u8 reserved_at_1b3[0x1]; 1469 u8 disable_link_up[0x1]; 1470 u8 beacon_led[0x1]; 1471 u8 port_type[0x2]; 1472 u8 num_ports[0x8]; 1473 1474 u8 reserved_at_1c0[0x1]; 1475 u8 pps[0x1]; 1476 u8 pps_modify[0x1]; 1477 u8 log_max_msg[0x5]; 1478 u8 reserved_at_1c8[0x4]; 1479 u8 max_tc[0x4]; 1480 u8 temp_warn_event[0x1]; 1481 u8 dcbx[0x1]; 1482 u8 general_notification_event[0x1]; 1483 u8 reserved_at_1d3[0x2]; 1484 u8 fpga[0x1]; 1485 u8 rol_s[0x1]; 1486 u8 rol_g[0x1]; 1487 u8 reserved_at_1d8[0x1]; 1488 u8 wol_s[0x1]; 1489 u8 wol_g[0x1]; 1490 u8 wol_a[0x1]; 1491 u8 wol_b[0x1]; 1492 u8 wol_m[0x1]; 1493 u8 wol_u[0x1]; 1494 u8 wol_p[0x1]; 1495 1496 u8 stat_rate_support[0x10]; 1497 u8 reserved_at_1f0[0x1]; 1498 u8 pci_sync_for_fw_update_event[0x1]; 1499 u8 reserved_at_1f2[0x6]; 1500 u8 init2_lag_tx_port_affinity[0x1]; 1501 u8 reserved_at_1fa[0x3]; 1502 u8 cqe_version[0x4]; 1503 1504 u8 compact_address_vector[0x1]; 1505 u8 striding_rq[0x1]; 1506 u8 reserved_at_202[0x1]; 1507 u8 ipoib_enhanced_offloads[0x1]; 1508 u8 ipoib_basic_offloads[0x1]; 1509 u8 reserved_at_205[0x1]; 1510 u8 repeated_block_disabled[0x1]; 1511 u8 umr_modify_entity_size_disabled[0x1]; 1512 u8 umr_modify_atomic_disabled[0x1]; 1513 u8 umr_indirect_mkey_disabled[0x1]; 1514 u8 umr_fence[0x2]; 1515 u8 dc_req_scat_data_cqe[0x1]; 1516 u8 reserved_at_20d[0x2]; 1517 u8 drain_sigerr[0x1]; 1518 u8 cmdif_checksum[0x2]; 1519 u8 sigerr_cqe[0x1]; 1520 u8 reserved_at_213[0x1]; 1521 u8 wq_signature[0x1]; 1522 u8 sctr_data_cqe[0x1]; 1523 u8 reserved_at_216[0x1]; 1524 u8 sho[0x1]; 1525 u8 tph[0x1]; 1526 u8 rf[0x1]; 1527 u8 dct[0x1]; 1528 u8 qos[0x1]; 1529 u8 eth_net_offloads[0x1]; 1530 u8 roce[0x1]; 1531 u8 atomic[0x1]; 1532 u8 reserved_at_21f[0x1]; 1533 1534 u8 cq_oi[0x1]; 1535 u8 cq_resize[0x1]; 1536 u8 cq_moderation[0x1]; 1537 u8 reserved_at_223[0x3]; 1538 u8 cq_eq_remap[0x1]; 1539 u8 pg[0x1]; 1540 u8 block_lb_mc[0x1]; 1541 u8 reserved_at_229[0x1]; 1542 u8 scqe_break_moderation[0x1]; 1543 u8 cq_period_start_from_cqe[0x1]; 1544 u8 cd[0x1]; 1545 u8 reserved_at_22d[0x1]; 1546 u8 apm[0x1]; 1547 u8 vector_calc[0x1]; 1548 u8 umr_ptr_rlky[0x1]; 1549 u8 imaicl[0x1]; 1550 u8 qp_packet_based[0x1]; 1551 u8 reserved_at_233[0x3]; 1552 u8 qkv[0x1]; 1553 u8 pkv[0x1]; 1554 u8 set_deth_sqpn[0x1]; 1555 u8 reserved_at_239[0x3]; 1556 u8 xrc[0x1]; 1557 u8 ud[0x1]; 1558 u8 uc[0x1]; 1559 u8 rc[0x1]; 1560 1561 u8 uar_4k[0x1]; 1562 u8 reserved_at_241[0x9]; 1563 u8 uar_sz[0x6]; 1564 u8 port_selection_cap[0x1]; 1565 u8 reserved_at_248[0x1]; 1566 u8 umem_uid_0[0x1]; 1567 u8 reserved_at_250[0x5]; 1568 u8 log_pg_sz[0x8]; 1569 1570 u8 bf[0x1]; 1571 u8 driver_version[0x1]; 1572 u8 pad_tx_eth_packet[0x1]; 1573 u8 reserved_at_263[0x3]; 1574 u8 mkey_by_name[0x1]; 1575 u8 reserved_at_267[0x4]; 1576 1577 u8 log_bf_reg_size[0x5]; 1578 1579 u8 reserved_at_270[0x6]; 1580 u8 lag_dct[0x2]; 1581 u8 lag_tx_port_affinity[0x1]; 1582 u8 lag_native_fdb_selection[0x1]; 1583 u8 reserved_at_27a[0x1]; 1584 u8 lag_master[0x1]; 1585 u8 num_lag_ports[0x4]; 1586 1587 u8 reserved_at_280[0x10]; 1588 u8 max_wqe_sz_sq[0x10]; 1589 1590 u8 reserved_at_2a0[0x10]; 1591 u8 max_wqe_sz_rq[0x10]; 1592 1593 u8 max_flow_counter_31_16[0x10]; 1594 u8 max_wqe_sz_sq_dc[0x10]; 1595 1596 u8 reserved_at_2e0[0x7]; 1597 u8 max_qp_mcg[0x19]; 1598 1599 u8 reserved_at_300[0x10]; 1600 u8 flow_counter_bulk_alloc[0x8]; 1601 u8 log_max_mcg[0x8]; 1602 1603 u8 reserved_at_320[0x3]; 1604 u8 log_max_transport_domain[0x5]; 1605 u8 reserved_at_328[0x3]; 1606 u8 log_max_pd[0x5]; 1607 u8 reserved_at_330[0xb]; 1608 u8 log_max_xrcd[0x5]; 1609 1610 u8 nic_receive_steering_discard[0x1]; 1611 u8 receive_discard_vport_down[0x1]; 1612 u8 transmit_discard_vport_down[0x1]; 1613 u8 reserved_at_343[0x5]; 1614 u8 log_max_flow_counter_bulk[0x8]; 1615 u8 max_flow_counter_15_0[0x10]; 1616 1617 1618 u8 reserved_at_360[0x3]; 1619 u8 log_max_rq[0x5]; 1620 u8 reserved_at_368[0x3]; 1621 u8 log_max_sq[0x5]; 1622 u8 reserved_at_370[0x3]; 1623 u8 log_max_tir[0x5]; 1624 u8 reserved_at_378[0x3]; 1625 u8 log_max_tis[0x5]; 1626 1627 u8 basic_cyclic_rcv_wqe[0x1]; 1628 u8 reserved_at_381[0x2]; 1629 u8 log_max_rmp[0x5]; 1630 u8 reserved_at_388[0x3]; 1631 u8 log_max_rqt[0x5]; 1632 u8 reserved_at_390[0x3]; 1633 u8 log_max_rqt_size[0x5]; 1634 u8 reserved_at_398[0x3]; 1635 u8 log_max_tis_per_sq[0x5]; 1636 1637 u8 ext_stride_num_range[0x1]; 1638 u8 roce_rw_supported[0x1]; 1639 u8 log_max_current_uc_list_wr_supported[0x1]; 1640 u8 log_max_stride_sz_rq[0x5]; 1641 u8 reserved_at_3a8[0x3]; 1642 u8 log_min_stride_sz_rq[0x5]; 1643 u8 reserved_at_3b0[0x3]; 1644 u8 log_max_stride_sz_sq[0x5]; 1645 u8 reserved_at_3b8[0x3]; 1646 u8 log_min_stride_sz_sq[0x5]; 1647 1648 u8 hairpin[0x1]; 1649 u8 reserved_at_3c1[0x2]; 1650 u8 log_max_hairpin_queues[0x5]; 1651 u8 reserved_at_3c8[0x3]; 1652 u8 log_max_hairpin_wq_data_sz[0x5]; 1653 u8 reserved_at_3d0[0x3]; 1654 u8 log_max_hairpin_num_packets[0x5]; 1655 u8 reserved_at_3d8[0x3]; 1656 u8 log_max_wq_sz[0x5]; 1657 1658 u8 nic_vport_change_event[0x1]; 1659 u8 disable_local_lb_uc[0x1]; 1660 u8 disable_local_lb_mc[0x1]; 1661 u8 log_min_hairpin_wq_data_sz[0x5]; 1662 u8 reserved_at_3e8[0x2]; 1663 u8 vhca_state[0x1]; 1664 u8 log_max_vlan_list[0x5]; 1665 u8 reserved_at_3f0[0x3]; 1666 u8 log_max_current_mc_list[0x5]; 1667 u8 reserved_at_3f8[0x3]; 1668 u8 log_max_current_uc_list[0x5]; 1669 1670 u8 general_obj_types[0x40]; 1671 1672 u8 sq_ts_format[0x2]; 1673 u8 rq_ts_format[0x2]; 1674 u8 steering_format_version[0x4]; 1675 u8 create_qp_start_hint[0x18]; 1676 1677 u8 reserved_at_460[0x3]; 1678 u8 log_max_uctx[0x5]; 1679 u8 reserved_at_468[0x2]; 1680 u8 ipsec_offload[0x1]; 1681 u8 log_max_umem[0x5]; 1682 u8 max_num_eqs[0x10]; 1683 1684 u8 reserved_at_480[0x1]; 1685 u8 tls_tx[0x1]; 1686 u8 tls_rx[0x1]; 1687 u8 log_max_l2_table[0x5]; 1688 u8 reserved_at_488[0x8]; 1689 u8 log_uar_page_sz[0x10]; 1690 1691 u8 reserved_at_4a0[0x20]; 1692 u8 device_frequency_mhz[0x20]; 1693 u8 device_frequency_khz[0x20]; 1694 1695 u8 reserved_at_500[0x20]; 1696 u8 num_of_uars_per_page[0x20]; 1697 1698 u8 flex_parser_protocols[0x20]; 1699 1700 u8 max_geneve_tlv_options[0x8]; 1701 u8 reserved_at_568[0x3]; 1702 u8 max_geneve_tlv_option_data_len[0x5]; 1703 u8 reserved_at_570[0x10]; 1704 1705 u8 reserved_at_580[0xb]; 1706 u8 log_max_dci_stream_channels[0x5]; 1707 u8 reserved_at_590[0x3]; 1708 u8 log_max_dci_errored_streams[0x5]; 1709 u8 reserved_at_598[0x8]; 1710 1711 u8 reserved_at_5a0[0x13]; 1712 u8 log_max_dek[0x5]; 1713 u8 reserved_at_5b8[0x4]; 1714 u8 mini_cqe_resp_stride_index[0x1]; 1715 u8 cqe_128_always[0x1]; 1716 u8 cqe_compression_128[0x1]; 1717 u8 cqe_compression[0x1]; 1718 1719 u8 cqe_compression_timeout[0x10]; 1720 u8 cqe_compression_max_num[0x10]; 1721 1722 u8 reserved_at_5e0[0x8]; 1723 u8 flex_parser_id_gtpu_dw_0[0x4]; 1724 u8 reserved_at_5ec[0x4]; 1725 u8 tag_matching[0x1]; 1726 u8 rndv_offload_rc[0x1]; 1727 u8 rndv_offload_dc[0x1]; 1728 u8 log_tag_matching_list_sz[0x5]; 1729 u8 reserved_at_5f8[0x3]; 1730 u8 log_max_xrq[0x5]; 1731 1732 u8 affiliate_nic_vport_criteria[0x8]; 1733 u8 native_port_num[0x8]; 1734 u8 num_vhca_ports[0x8]; 1735 u8 flex_parser_id_gtpu_teid[0x4]; 1736 u8 reserved_at_61c[0x2]; 1737 u8 sw_owner_id[0x1]; 1738 u8 reserved_at_61f[0x1]; 1739 1740 u8 max_num_of_monitor_counters[0x10]; 1741 u8 num_ppcnt_monitor_counters[0x10]; 1742 1743 u8 max_num_sf[0x10]; 1744 u8 num_q_monitor_counters[0x10]; 1745 1746 u8 reserved_at_660[0x20]; 1747 1748 u8 sf[0x1]; 1749 u8 sf_set_partition[0x1]; 1750 u8 reserved_at_682[0x1]; 1751 u8 log_max_sf[0x5]; 1752 u8 apu[0x1]; 1753 u8 reserved_at_689[0x7]; 1754 u8 log_min_sf_size[0x8]; 1755 u8 max_num_sf_partitions[0x8]; 1756 1757 u8 uctx_cap[0x20]; 1758 1759 u8 reserved_at_6c0[0x4]; 1760 u8 flex_parser_id_geneve_tlv_option_0[0x4]; 1761 u8 flex_parser_id_icmp_dw1[0x4]; 1762 u8 flex_parser_id_icmp_dw0[0x4]; 1763 u8 flex_parser_id_icmpv6_dw1[0x4]; 1764 u8 flex_parser_id_icmpv6_dw0[0x4]; 1765 u8 flex_parser_id_outer_first_mpls_over_gre[0x4]; 1766 u8 flex_parser_id_outer_first_mpls_over_udp_label[0x4]; 1767 1768 u8 max_num_match_definer[0x10]; 1769 u8 sf_base_id[0x10]; 1770 1771 u8 flex_parser_id_gtpu_dw_2[0x4]; 1772 u8 flex_parser_id_gtpu_first_ext_dw_0[0x4]; 1773 u8 num_total_dynamic_vf_msix[0x18]; 1774 u8 reserved_at_720[0x14]; 1775 u8 dynamic_msix_table_size[0xc]; 1776 u8 reserved_at_740[0xc]; 1777 u8 min_dynamic_vf_msix_table_size[0x4]; 1778 u8 reserved_at_750[0x4]; 1779 u8 max_dynamic_vf_msix_table_size[0xc]; 1780 1781 u8 reserved_at_760[0x20]; 1782 u8 vhca_tunnel_commands[0x40]; 1783 u8 match_definer_format_supported[0x40]; 1784 }; 1785 1786 struct mlx5_ifc_cmd_hca_cap_2_bits { 1787 u8 reserved_at_0[0xa0]; 1788 1789 u8 max_reformat_insert_size[0x8]; 1790 u8 max_reformat_insert_offset[0x8]; 1791 u8 max_reformat_remove_size[0x8]; 1792 u8 max_reformat_remove_offset[0x8]; 1793 1794 u8 reserved_at_c0[0x740]; 1795 }; 1796 1797 enum mlx5_flow_destination_type { 1798 MLX5_FLOW_DESTINATION_TYPE_VPORT = 0x0, 1799 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1, 1800 MLX5_FLOW_DESTINATION_TYPE_TIR = 0x2, 1801 MLX5_FLOW_DESTINATION_TYPE_FLOW_SAMPLER = 0x6, 1802 MLX5_FLOW_DESTINATION_TYPE_UPLINK = 0x8, 1803 1804 MLX5_FLOW_DESTINATION_TYPE_PORT = 0x99, 1805 MLX5_FLOW_DESTINATION_TYPE_COUNTER = 0x100, 1806 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE_NUM = 0x101, 1807 }; 1808 1809 enum mlx5_flow_table_miss_action { 1810 MLX5_FLOW_TABLE_MISS_ACTION_DEF, 1811 MLX5_FLOW_TABLE_MISS_ACTION_FWD, 1812 MLX5_FLOW_TABLE_MISS_ACTION_SWITCH_DOMAIN, 1813 }; 1814 1815 struct mlx5_ifc_dest_format_struct_bits { 1816 u8 destination_type[0x8]; 1817 u8 destination_id[0x18]; 1818 1819 u8 destination_eswitch_owner_vhca_id_valid[0x1]; 1820 u8 packet_reformat[0x1]; 1821 u8 reserved_at_22[0xe]; 1822 u8 destination_eswitch_owner_vhca_id[0x10]; 1823 }; 1824 1825 struct mlx5_ifc_flow_counter_list_bits { 1826 u8 flow_counter_id[0x20]; 1827 1828 u8 reserved_at_20[0x20]; 1829 }; 1830 1831 struct mlx5_ifc_extended_dest_format_bits { 1832 struct mlx5_ifc_dest_format_struct_bits destination_entry; 1833 1834 u8 packet_reformat_id[0x20]; 1835 1836 u8 reserved_at_60[0x20]; 1837 }; 1838 1839 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits { 1840 struct mlx5_ifc_extended_dest_format_bits extended_dest_format; 1841 struct mlx5_ifc_flow_counter_list_bits flow_counter_list; 1842 }; 1843 1844 struct mlx5_ifc_fte_match_param_bits { 1845 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers; 1846 1847 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters; 1848 1849 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers; 1850 1851 struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2; 1852 1853 struct mlx5_ifc_fte_match_set_misc3_bits misc_parameters_3; 1854 1855 struct mlx5_ifc_fte_match_set_misc4_bits misc_parameters_4; 1856 1857 struct mlx5_ifc_fte_match_set_misc5_bits misc_parameters_5; 1858 1859 u8 reserved_at_e00[0x200]; 1860 }; 1861 1862 enum { 1863 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0, 1864 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1, 1865 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2, 1866 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3, 1867 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4, 1868 }; 1869 1870 struct mlx5_ifc_rx_hash_field_select_bits { 1871 u8 l3_prot_type[0x1]; 1872 u8 l4_prot_type[0x1]; 1873 u8 selected_fields[0x1e]; 1874 }; 1875 1876 enum { 1877 MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0, 1878 MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1, 1879 }; 1880 1881 enum { 1882 MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0, 1883 MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1, 1884 }; 1885 1886 struct mlx5_ifc_wq_bits { 1887 u8 wq_type[0x4]; 1888 u8 wq_signature[0x1]; 1889 u8 end_padding_mode[0x2]; 1890 u8 cd_slave[0x1]; 1891 u8 reserved_at_8[0x18]; 1892 1893 u8 hds_skip_first_sge[0x1]; 1894 u8 log2_hds_buf_size[0x3]; 1895 u8 reserved_at_24[0x7]; 1896 u8 page_offset[0x5]; 1897 u8 lwm[0x10]; 1898 1899 u8 reserved_at_40[0x8]; 1900 u8 pd[0x18]; 1901 1902 u8 reserved_at_60[0x8]; 1903 u8 uar_page[0x18]; 1904 1905 u8 dbr_addr[0x40]; 1906 1907 u8 hw_counter[0x20]; 1908 1909 u8 sw_counter[0x20]; 1910 1911 u8 reserved_at_100[0xc]; 1912 u8 log_wq_stride[0x4]; 1913 u8 reserved_at_110[0x3]; 1914 u8 log_wq_pg_sz[0x5]; 1915 u8 reserved_at_118[0x3]; 1916 u8 log_wq_sz[0x5]; 1917 1918 u8 dbr_umem_valid[0x1]; 1919 u8 wq_umem_valid[0x1]; 1920 u8 reserved_at_122[0x1]; 1921 u8 log_hairpin_num_packets[0x5]; 1922 u8 reserved_at_128[0x3]; 1923 u8 log_hairpin_data_sz[0x5]; 1924 1925 u8 reserved_at_130[0x4]; 1926 u8 log_wqe_num_of_strides[0x4]; 1927 u8 two_byte_shift_en[0x1]; 1928 u8 reserved_at_139[0x4]; 1929 u8 log_wqe_stride_size[0x3]; 1930 1931 u8 reserved_at_140[0x80]; 1932 1933 u8 headers_mkey[0x20]; 1934 1935 u8 shampo_enable[0x1]; 1936 u8 reserved_at_1e1[0x4]; 1937 u8 log_reservation_size[0x3]; 1938 u8 reserved_at_1e8[0x5]; 1939 u8 log_max_num_of_packets_per_reservation[0x3]; 1940 u8 reserved_at_1f0[0x6]; 1941 u8 log_headers_entry_size[0x2]; 1942 u8 reserved_at_1f8[0x4]; 1943 u8 log_headers_buffer_entry_num[0x4]; 1944 1945 u8 reserved_at_200[0x400]; 1946 1947 struct mlx5_ifc_cmd_pas_bits pas[]; 1948 }; 1949 1950 struct mlx5_ifc_rq_num_bits { 1951 u8 reserved_at_0[0x8]; 1952 u8 rq_num[0x18]; 1953 }; 1954 1955 struct mlx5_ifc_mac_address_layout_bits { 1956 u8 reserved_at_0[0x10]; 1957 u8 mac_addr_47_32[0x10]; 1958 1959 u8 mac_addr_31_0[0x20]; 1960 }; 1961 1962 struct mlx5_ifc_vlan_layout_bits { 1963 u8 reserved_at_0[0x14]; 1964 u8 vlan[0x0c]; 1965 1966 u8 reserved_at_20[0x20]; 1967 }; 1968 1969 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits { 1970 u8 reserved_at_0[0xa0]; 1971 1972 u8 min_time_between_cnps[0x20]; 1973 1974 u8 reserved_at_c0[0x12]; 1975 u8 cnp_dscp[0x6]; 1976 u8 reserved_at_d8[0x4]; 1977 u8 cnp_prio_mode[0x1]; 1978 u8 cnp_802p_prio[0x3]; 1979 1980 u8 reserved_at_e0[0x720]; 1981 }; 1982 1983 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits { 1984 u8 reserved_at_0[0x60]; 1985 1986 u8 reserved_at_60[0x4]; 1987 u8 clamp_tgt_rate[0x1]; 1988 u8 reserved_at_65[0x3]; 1989 u8 clamp_tgt_rate_after_time_inc[0x1]; 1990 u8 reserved_at_69[0x17]; 1991 1992 u8 reserved_at_80[0x20]; 1993 1994 u8 rpg_time_reset[0x20]; 1995 1996 u8 rpg_byte_reset[0x20]; 1997 1998 u8 rpg_threshold[0x20]; 1999 2000 u8 rpg_max_rate[0x20]; 2001 2002 u8 rpg_ai_rate[0x20]; 2003 2004 u8 rpg_hai_rate[0x20]; 2005 2006 u8 rpg_gd[0x20]; 2007 2008 u8 rpg_min_dec_fac[0x20]; 2009 2010 u8 rpg_min_rate[0x20]; 2011 2012 u8 reserved_at_1c0[0xe0]; 2013 2014 u8 rate_to_set_on_first_cnp[0x20]; 2015 2016 u8 dce_tcp_g[0x20]; 2017 2018 u8 dce_tcp_rtt[0x20]; 2019 2020 u8 rate_reduce_monitor_period[0x20]; 2021 2022 u8 reserved_at_320[0x20]; 2023 2024 u8 initial_alpha_value[0x20]; 2025 2026 u8 reserved_at_360[0x4a0]; 2027 }; 2028 2029 struct mlx5_ifc_cong_control_802_1qau_rp_bits { 2030 u8 reserved_at_0[0x80]; 2031 2032 u8 rppp_max_rps[0x20]; 2033 2034 u8 rpg_time_reset[0x20]; 2035 2036 u8 rpg_byte_reset[0x20]; 2037 2038 u8 rpg_threshold[0x20]; 2039 2040 u8 rpg_max_rate[0x20]; 2041 2042 u8 rpg_ai_rate[0x20]; 2043 2044 u8 rpg_hai_rate[0x20]; 2045 2046 u8 rpg_gd[0x20]; 2047 2048 u8 rpg_min_dec_fac[0x20]; 2049 2050 u8 rpg_min_rate[0x20]; 2051 2052 u8 reserved_at_1c0[0x640]; 2053 }; 2054 2055 enum { 2056 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1, 2057 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2, 2058 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4, 2059 }; 2060 2061 struct mlx5_ifc_resize_field_select_bits { 2062 u8 resize_field_select[0x20]; 2063 }; 2064 2065 struct mlx5_ifc_resource_dump_bits { 2066 u8 more_dump[0x1]; 2067 u8 inline_dump[0x1]; 2068 u8 reserved_at_2[0xa]; 2069 u8 seq_num[0x4]; 2070 u8 segment_type[0x10]; 2071 2072 u8 reserved_at_20[0x10]; 2073 u8 vhca_id[0x10]; 2074 2075 u8 index1[0x20]; 2076 2077 u8 index2[0x20]; 2078 2079 u8 num_of_obj1[0x10]; 2080 u8 num_of_obj2[0x10]; 2081 2082 u8 reserved_at_a0[0x20]; 2083 2084 u8 device_opaque[0x40]; 2085 2086 u8 mkey[0x20]; 2087 2088 u8 size[0x20]; 2089 2090 u8 address[0x40]; 2091 2092 u8 inline_data[52][0x20]; 2093 }; 2094 2095 struct mlx5_ifc_resource_dump_menu_record_bits { 2096 u8 reserved_at_0[0x4]; 2097 u8 num_of_obj2_supports_active[0x1]; 2098 u8 num_of_obj2_supports_all[0x1]; 2099 u8 must_have_num_of_obj2[0x1]; 2100 u8 support_num_of_obj2[0x1]; 2101 u8 num_of_obj1_supports_active[0x1]; 2102 u8 num_of_obj1_supports_all[0x1]; 2103 u8 must_have_num_of_obj1[0x1]; 2104 u8 support_num_of_obj1[0x1]; 2105 u8 must_have_index2[0x1]; 2106 u8 support_index2[0x1]; 2107 u8 must_have_index1[0x1]; 2108 u8 support_index1[0x1]; 2109 u8 segment_type[0x10]; 2110 2111 u8 segment_name[4][0x20]; 2112 2113 u8 index1_name[4][0x20]; 2114 2115 u8 index2_name[4][0x20]; 2116 }; 2117 2118 struct mlx5_ifc_resource_dump_segment_header_bits { 2119 u8 length_dw[0x10]; 2120 u8 segment_type[0x10]; 2121 }; 2122 2123 struct mlx5_ifc_resource_dump_command_segment_bits { 2124 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2125 2126 u8 segment_called[0x10]; 2127 u8 vhca_id[0x10]; 2128 2129 u8 index1[0x20]; 2130 2131 u8 index2[0x20]; 2132 2133 u8 num_of_obj1[0x10]; 2134 u8 num_of_obj2[0x10]; 2135 }; 2136 2137 struct mlx5_ifc_resource_dump_error_segment_bits { 2138 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2139 2140 u8 reserved_at_20[0x10]; 2141 u8 syndrome_id[0x10]; 2142 2143 u8 reserved_at_40[0x40]; 2144 2145 u8 error[8][0x20]; 2146 }; 2147 2148 struct mlx5_ifc_resource_dump_info_segment_bits { 2149 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2150 2151 u8 reserved_at_20[0x18]; 2152 u8 dump_version[0x8]; 2153 2154 u8 hw_version[0x20]; 2155 2156 u8 fw_version[0x20]; 2157 }; 2158 2159 struct mlx5_ifc_resource_dump_menu_segment_bits { 2160 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2161 2162 u8 reserved_at_20[0x10]; 2163 u8 num_of_records[0x10]; 2164 2165 struct mlx5_ifc_resource_dump_menu_record_bits record[]; 2166 }; 2167 2168 struct mlx5_ifc_resource_dump_resource_segment_bits { 2169 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2170 2171 u8 reserved_at_20[0x20]; 2172 2173 u8 index1[0x20]; 2174 2175 u8 index2[0x20]; 2176 2177 u8 payload[][0x20]; 2178 }; 2179 2180 struct mlx5_ifc_resource_dump_terminate_segment_bits { 2181 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2182 }; 2183 2184 struct mlx5_ifc_menu_resource_dump_response_bits { 2185 struct mlx5_ifc_resource_dump_info_segment_bits info; 2186 struct mlx5_ifc_resource_dump_command_segment_bits cmd; 2187 struct mlx5_ifc_resource_dump_menu_segment_bits menu; 2188 struct mlx5_ifc_resource_dump_terminate_segment_bits terminate; 2189 }; 2190 2191 enum { 2192 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1, 2193 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2, 2194 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4, 2195 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8, 2196 }; 2197 2198 struct mlx5_ifc_modify_field_select_bits { 2199 u8 modify_field_select[0x20]; 2200 }; 2201 2202 struct mlx5_ifc_field_select_r_roce_np_bits { 2203 u8 field_select_r_roce_np[0x20]; 2204 }; 2205 2206 struct mlx5_ifc_field_select_r_roce_rp_bits { 2207 u8 field_select_r_roce_rp[0x20]; 2208 }; 2209 2210 enum { 2211 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4, 2212 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8, 2213 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10, 2214 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20, 2215 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40, 2216 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80, 2217 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100, 2218 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200, 2219 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400, 2220 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800, 2221 }; 2222 2223 struct mlx5_ifc_field_select_802_1qau_rp_bits { 2224 u8 field_select_8021qaurp[0x20]; 2225 }; 2226 2227 struct mlx5_ifc_phys_layer_cntrs_bits { 2228 u8 time_since_last_clear_high[0x20]; 2229 2230 u8 time_since_last_clear_low[0x20]; 2231 2232 u8 symbol_errors_high[0x20]; 2233 2234 u8 symbol_errors_low[0x20]; 2235 2236 u8 sync_headers_errors_high[0x20]; 2237 2238 u8 sync_headers_errors_low[0x20]; 2239 2240 u8 edpl_bip_errors_lane0_high[0x20]; 2241 2242 u8 edpl_bip_errors_lane0_low[0x20]; 2243 2244 u8 edpl_bip_errors_lane1_high[0x20]; 2245 2246 u8 edpl_bip_errors_lane1_low[0x20]; 2247 2248 u8 edpl_bip_errors_lane2_high[0x20]; 2249 2250 u8 edpl_bip_errors_lane2_low[0x20]; 2251 2252 u8 edpl_bip_errors_lane3_high[0x20]; 2253 2254 u8 edpl_bip_errors_lane3_low[0x20]; 2255 2256 u8 fc_fec_corrected_blocks_lane0_high[0x20]; 2257 2258 u8 fc_fec_corrected_blocks_lane0_low[0x20]; 2259 2260 u8 fc_fec_corrected_blocks_lane1_high[0x20]; 2261 2262 u8 fc_fec_corrected_blocks_lane1_low[0x20]; 2263 2264 u8 fc_fec_corrected_blocks_lane2_high[0x20]; 2265 2266 u8 fc_fec_corrected_blocks_lane2_low[0x20]; 2267 2268 u8 fc_fec_corrected_blocks_lane3_high[0x20]; 2269 2270 u8 fc_fec_corrected_blocks_lane3_low[0x20]; 2271 2272 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20]; 2273 2274 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20]; 2275 2276 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20]; 2277 2278 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20]; 2279 2280 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20]; 2281 2282 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20]; 2283 2284 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20]; 2285 2286 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20]; 2287 2288 u8 rs_fec_corrected_blocks_high[0x20]; 2289 2290 u8 rs_fec_corrected_blocks_low[0x20]; 2291 2292 u8 rs_fec_uncorrectable_blocks_high[0x20]; 2293 2294 u8 rs_fec_uncorrectable_blocks_low[0x20]; 2295 2296 u8 rs_fec_no_errors_blocks_high[0x20]; 2297 2298 u8 rs_fec_no_errors_blocks_low[0x20]; 2299 2300 u8 rs_fec_single_error_blocks_high[0x20]; 2301 2302 u8 rs_fec_single_error_blocks_low[0x20]; 2303 2304 u8 rs_fec_corrected_symbols_total_high[0x20]; 2305 2306 u8 rs_fec_corrected_symbols_total_low[0x20]; 2307 2308 u8 rs_fec_corrected_symbols_lane0_high[0x20]; 2309 2310 u8 rs_fec_corrected_symbols_lane0_low[0x20]; 2311 2312 u8 rs_fec_corrected_symbols_lane1_high[0x20]; 2313 2314 u8 rs_fec_corrected_symbols_lane1_low[0x20]; 2315 2316 u8 rs_fec_corrected_symbols_lane2_high[0x20]; 2317 2318 u8 rs_fec_corrected_symbols_lane2_low[0x20]; 2319 2320 u8 rs_fec_corrected_symbols_lane3_high[0x20]; 2321 2322 u8 rs_fec_corrected_symbols_lane3_low[0x20]; 2323 2324 u8 link_down_events[0x20]; 2325 2326 u8 successful_recovery_events[0x20]; 2327 2328 u8 reserved_at_640[0x180]; 2329 }; 2330 2331 struct mlx5_ifc_phys_layer_statistical_cntrs_bits { 2332 u8 time_since_last_clear_high[0x20]; 2333 2334 u8 time_since_last_clear_low[0x20]; 2335 2336 u8 phy_received_bits_high[0x20]; 2337 2338 u8 phy_received_bits_low[0x20]; 2339 2340 u8 phy_symbol_errors_high[0x20]; 2341 2342 u8 phy_symbol_errors_low[0x20]; 2343 2344 u8 phy_corrected_bits_high[0x20]; 2345 2346 u8 phy_corrected_bits_low[0x20]; 2347 2348 u8 phy_corrected_bits_lane0_high[0x20]; 2349 2350 u8 phy_corrected_bits_lane0_low[0x20]; 2351 2352 u8 phy_corrected_bits_lane1_high[0x20]; 2353 2354 u8 phy_corrected_bits_lane1_low[0x20]; 2355 2356 u8 phy_corrected_bits_lane2_high[0x20]; 2357 2358 u8 phy_corrected_bits_lane2_low[0x20]; 2359 2360 u8 phy_corrected_bits_lane3_high[0x20]; 2361 2362 u8 phy_corrected_bits_lane3_low[0x20]; 2363 2364 u8 reserved_at_200[0x5c0]; 2365 }; 2366 2367 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits { 2368 u8 symbol_error_counter[0x10]; 2369 2370 u8 link_error_recovery_counter[0x8]; 2371 2372 u8 link_downed_counter[0x8]; 2373 2374 u8 port_rcv_errors[0x10]; 2375 2376 u8 port_rcv_remote_physical_errors[0x10]; 2377 2378 u8 port_rcv_switch_relay_errors[0x10]; 2379 2380 u8 port_xmit_discards[0x10]; 2381 2382 u8 port_xmit_constraint_errors[0x8]; 2383 2384 u8 port_rcv_constraint_errors[0x8]; 2385 2386 u8 reserved_at_70[0x8]; 2387 2388 u8 link_overrun_errors[0x8]; 2389 2390 u8 reserved_at_80[0x10]; 2391 2392 u8 vl_15_dropped[0x10]; 2393 2394 u8 reserved_at_a0[0x80]; 2395 2396 u8 port_xmit_wait[0x20]; 2397 }; 2398 2399 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits { 2400 u8 transmit_queue_high[0x20]; 2401 2402 u8 transmit_queue_low[0x20]; 2403 2404 u8 no_buffer_discard_uc_high[0x20]; 2405 2406 u8 no_buffer_discard_uc_low[0x20]; 2407 2408 u8 reserved_at_80[0x740]; 2409 }; 2410 2411 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits { 2412 u8 wred_discard_high[0x20]; 2413 2414 u8 wred_discard_low[0x20]; 2415 2416 u8 ecn_marked_tc_high[0x20]; 2417 2418 u8 ecn_marked_tc_low[0x20]; 2419 2420 u8 reserved_at_80[0x740]; 2421 }; 2422 2423 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits { 2424 u8 rx_octets_high[0x20]; 2425 2426 u8 rx_octets_low[0x20]; 2427 2428 u8 reserved_at_40[0xc0]; 2429 2430 u8 rx_frames_high[0x20]; 2431 2432 u8 rx_frames_low[0x20]; 2433 2434 u8 tx_octets_high[0x20]; 2435 2436 u8 tx_octets_low[0x20]; 2437 2438 u8 reserved_at_180[0xc0]; 2439 2440 u8 tx_frames_high[0x20]; 2441 2442 u8 tx_frames_low[0x20]; 2443 2444 u8 rx_pause_high[0x20]; 2445 2446 u8 rx_pause_low[0x20]; 2447 2448 u8 rx_pause_duration_high[0x20]; 2449 2450 u8 rx_pause_duration_low[0x20]; 2451 2452 u8 tx_pause_high[0x20]; 2453 2454 u8 tx_pause_low[0x20]; 2455 2456 u8 tx_pause_duration_high[0x20]; 2457 2458 u8 tx_pause_duration_low[0x20]; 2459 2460 u8 rx_pause_transition_high[0x20]; 2461 2462 u8 rx_pause_transition_low[0x20]; 2463 2464 u8 rx_discards_high[0x20]; 2465 2466 u8 rx_discards_low[0x20]; 2467 2468 u8 device_stall_minor_watermark_cnt_high[0x20]; 2469 2470 u8 device_stall_minor_watermark_cnt_low[0x20]; 2471 2472 u8 device_stall_critical_watermark_cnt_high[0x20]; 2473 2474 u8 device_stall_critical_watermark_cnt_low[0x20]; 2475 2476 u8 reserved_at_480[0x340]; 2477 }; 2478 2479 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits { 2480 u8 port_transmit_wait_high[0x20]; 2481 2482 u8 port_transmit_wait_low[0x20]; 2483 2484 u8 reserved_at_40[0x100]; 2485 2486 u8 rx_buffer_almost_full_high[0x20]; 2487 2488 u8 rx_buffer_almost_full_low[0x20]; 2489 2490 u8 rx_buffer_full_high[0x20]; 2491 2492 u8 rx_buffer_full_low[0x20]; 2493 2494 u8 rx_icrc_encapsulated_high[0x20]; 2495 2496 u8 rx_icrc_encapsulated_low[0x20]; 2497 2498 u8 reserved_at_200[0x5c0]; 2499 }; 2500 2501 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits { 2502 u8 dot3stats_alignment_errors_high[0x20]; 2503 2504 u8 dot3stats_alignment_errors_low[0x20]; 2505 2506 u8 dot3stats_fcs_errors_high[0x20]; 2507 2508 u8 dot3stats_fcs_errors_low[0x20]; 2509 2510 u8 dot3stats_single_collision_frames_high[0x20]; 2511 2512 u8 dot3stats_single_collision_frames_low[0x20]; 2513 2514 u8 dot3stats_multiple_collision_frames_high[0x20]; 2515 2516 u8 dot3stats_multiple_collision_frames_low[0x20]; 2517 2518 u8 dot3stats_sqe_test_errors_high[0x20]; 2519 2520 u8 dot3stats_sqe_test_errors_low[0x20]; 2521 2522 u8 dot3stats_deferred_transmissions_high[0x20]; 2523 2524 u8 dot3stats_deferred_transmissions_low[0x20]; 2525 2526 u8 dot3stats_late_collisions_high[0x20]; 2527 2528 u8 dot3stats_late_collisions_low[0x20]; 2529 2530 u8 dot3stats_excessive_collisions_high[0x20]; 2531 2532 u8 dot3stats_excessive_collisions_low[0x20]; 2533 2534 u8 dot3stats_internal_mac_transmit_errors_high[0x20]; 2535 2536 u8 dot3stats_internal_mac_transmit_errors_low[0x20]; 2537 2538 u8 dot3stats_carrier_sense_errors_high[0x20]; 2539 2540 u8 dot3stats_carrier_sense_errors_low[0x20]; 2541 2542 u8 dot3stats_frame_too_longs_high[0x20]; 2543 2544 u8 dot3stats_frame_too_longs_low[0x20]; 2545 2546 u8 dot3stats_internal_mac_receive_errors_high[0x20]; 2547 2548 u8 dot3stats_internal_mac_receive_errors_low[0x20]; 2549 2550 u8 dot3stats_symbol_errors_high[0x20]; 2551 2552 u8 dot3stats_symbol_errors_low[0x20]; 2553 2554 u8 dot3control_in_unknown_opcodes_high[0x20]; 2555 2556 u8 dot3control_in_unknown_opcodes_low[0x20]; 2557 2558 u8 dot3in_pause_frames_high[0x20]; 2559 2560 u8 dot3in_pause_frames_low[0x20]; 2561 2562 u8 dot3out_pause_frames_high[0x20]; 2563 2564 u8 dot3out_pause_frames_low[0x20]; 2565 2566 u8 reserved_at_400[0x3c0]; 2567 }; 2568 2569 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits { 2570 u8 ether_stats_drop_events_high[0x20]; 2571 2572 u8 ether_stats_drop_events_low[0x20]; 2573 2574 u8 ether_stats_octets_high[0x20]; 2575 2576 u8 ether_stats_octets_low[0x20]; 2577 2578 u8 ether_stats_pkts_high[0x20]; 2579 2580 u8 ether_stats_pkts_low[0x20]; 2581 2582 u8 ether_stats_broadcast_pkts_high[0x20]; 2583 2584 u8 ether_stats_broadcast_pkts_low[0x20]; 2585 2586 u8 ether_stats_multicast_pkts_high[0x20]; 2587 2588 u8 ether_stats_multicast_pkts_low[0x20]; 2589 2590 u8 ether_stats_crc_align_errors_high[0x20]; 2591 2592 u8 ether_stats_crc_align_errors_low[0x20]; 2593 2594 u8 ether_stats_undersize_pkts_high[0x20]; 2595 2596 u8 ether_stats_undersize_pkts_low[0x20]; 2597 2598 u8 ether_stats_oversize_pkts_high[0x20]; 2599 2600 u8 ether_stats_oversize_pkts_low[0x20]; 2601 2602 u8 ether_stats_fragments_high[0x20]; 2603 2604 u8 ether_stats_fragments_low[0x20]; 2605 2606 u8 ether_stats_jabbers_high[0x20]; 2607 2608 u8 ether_stats_jabbers_low[0x20]; 2609 2610 u8 ether_stats_collisions_high[0x20]; 2611 2612 u8 ether_stats_collisions_low[0x20]; 2613 2614 u8 ether_stats_pkts64octets_high[0x20]; 2615 2616 u8 ether_stats_pkts64octets_low[0x20]; 2617 2618 u8 ether_stats_pkts65to127octets_high[0x20]; 2619 2620 u8 ether_stats_pkts65to127octets_low[0x20]; 2621 2622 u8 ether_stats_pkts128to255octets_high[0x20]; 2623 2624 u8 ether_stats_pkts128to255octets_low[0x20]; 2625 2626 u8 ether_stats_pkts256to511octets_high[0x20]; 2627 2628 u8 ether_stats_pkts256to511octets_low[0x20]; 2629 2630 u8 ether_stats_pkts512to1023octets_high[0x20]; 2631 2632 u8 ether_stats_pkts512to1023octets_low[0x20]; 2633 2634 u8 ether_stats_pkts1024to1518octets_high[0x20]; 2635 2636 u8 ether_stats_pkts1024to1518octets_low[0x20]; 2637 2638 u8 ether_stats_pkts1519to2047octets_high[0x20]; 2639 2640 u8 ether_stats_pkts1519to2047octets_low[0x20]; 2641 2642 u8 ether_stats_pkts2048to4095octets_high[0x20]; 2643 2644 u8 ether_stats_pkts2048to4095octets_low[0x20]; 2645 2646 u8 ether_stats_pkts4096to8191octets_high[0x20]; 2647 2648 u8 ether_stats_pkts4096to8191octets_low[0x20]; 2649 2650 u8 ether_stats_pkts8192to10239octets_high[0x20]; 2651 2652 u8 ether_stats_pkts8192to10239octets_low[0x20]; 2653 2654 u8 reserved_at_540[0x280]; 2655 }; 2656 2657 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits { 2658 u8 if_in_octets_high[0x20]; 2659 2660 u8 if_in_octets_low[0x20]; 2661 2662 u8 if_in_ucast_pkts_high[0x20]; 2663 2664 u8 if_in_ucast_pkts_low[0x20]; 2665 2666 u8 if_in_discards_high[0x20]; 2667 2668 u8 if_in_discards_low[0x20]; 2669 2670 u8 if_in_errors_high[0x20]; 2671 2672 u8 if_in_errors_low[0x20]; 2673 2674 u8 if_in_unknown_protos_high[0x20]; 2675 2676 u8 if_in_unknown_protos_low[0x20]; 2677 2678 u8 if_out_octets_high[0x20]; 2679 2680 u8 if_out_octets_low[0x20]; 2681 2682 u8 if_out_ucast_pkts_high[0x20]; 2683 2684 u8 if_out_ucast_pkts_low[0x20]; 2685 2686 u8 if_out_discards_high[0x20]; 2687 2688 u8 if_out_discards_low[0x20]; 2689 2690 u8 if_out_errors_high[0x20]; 2691 2692 u8 if_out_errors_low[0x20]; 2693 2694 u8 if_in_multicast_pkts_high[0x20]; 2695 2696 u8 if_in_multicast_pkts_low[0x20]; 2697 2698 u8 if_in_broadcast_pkts_high[0x20]; 2699 2700 u8 if_in_broadcast_pkts_low[0x20]; 2701 2702 u8 if_out_multicast_pkts_high[0x20]; 2703 2704 u8 if_out_multicast_pkts_low[0x20]; 2705 2706 u8 if_out_broadcast_pkts_high[0x20]; 2707 2708 u8 if_out_broadcast_pkts_low[0x20]; 2709 2710 u8 reserved_at_340[0x480]; 2711 }; 2712 2713 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits { 2714 u8 a_frames_transmitted_ok_high[0x20]; 2715 2716 u8 a_frames_transmitted_ok_low[0x20]; 2717 2718 u8 a_frames_received_ok_high[0x20]; 2719 2720 u8 a_frames_received_ok_low[0x20]; 2721 2722 u8 a_frame_check_sequence_errors_high[0x20]; 2723 2724 u8 a_frame_check_sequence_errors_low[0x20]; 2725 2726 u8 a_alignment_errors_high[0x20]; 2727 2728 u8 a_alignment_errors_low[0x20]; 2729 2730 u8 a_octets_transmitted_ok_high[0x20]; 2731 2732 u8 a_octets_transmitted_ok_low[0x20]; 2733 2734 u8 a_octets_received_ok_high[0x20]; 2735 2736 u8 a_octets_received_ok_low[0x20]; 2737 2738 u8 a_multicast_frames_xmitted_ok_high[0x20]; 2739 2740 u8 a_multicast_frames_xmitted_ok_low[0x20]; 2741 2742 u8 a_broadcast_frames_xmitted_ok_high[0x20]; 2743 2744 u8 a_broadcast_frames_xmitted_ok_low[0x20]; 2745 2746 u8 a_multicast_frames_received_ok_high[0x20]; 2747 2748 u8 a_multicast_frames_received_ok_low[0x20]; 2749 2750 u8 a_broadcast_frames_received_ok_high[0x20]; 2751 2752 u8 a_broadcast_frames_received_ok_low[0x20]; 2753 2754 u8 a_in_range_length_errors_high[0x20]; 2755 2756 u8 a_in_range_length_errors_low[0x20]; 2757 2758 u8 a_out_of_range_length_field_high[0x20]; 2759 2760 u8 a_out_of_range_length_field_low[0x20]; 2761 2762 u8 a_frame_too_long_errors_high[0x20]; 2763 2764 u8 a_frame_too_long_errors_low[0x20]; 2765 2766 u8 a_symbol_error_during_carrier_high[0x20]; 2767 2768 u8 a_symbol_error_during_carrier_low[0x20]; 2769 2770 u8 a_mac_control_frames_transmitted_high[0x20]; 2771 2772 u8 a_mac_control_frames_transmitted_low[0x20]; 2773 2774 u8 a_mac_control_frames_received_high[0x20]; 2775 2776 u8 a_mac_control_frames_received_low[0x20]; 2777 2778 u8 a_unsupported_opcodes_received_high[0x20]; 2779 2780 u8 a_unsupported_opcodes_received_low[0x20]; 2781 2782 u8 a_pause_mac_ctrl_frames_received_high[0x20]; 2783 2784 u8 a_pause_mac_ctrl_frames_received_low[0x20]; 2785 2786 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20]; 2787 2788 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20]; 2789 2790 u8 reserved_at_4c0[0x300]; 2791 }; 2792 2793 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits { 2794 u8 life_time_counter_high[0x20]; 2795 2796 u8 life_time_counter_low[0x20]; 2797 2798 u8 rx_errors[0x20]; 2799 2800 u8 tx_errors[0x20]; 2801 2802 u8 l0_to_recovery_eieos[0x20]; 2803 2804 u8 l0_to_recovery_ts[0x20]; 2805 2806 u8 l0_to_recovery_framing[0x20]; 2807 2808 u8 l0_to_recovery_retrain[0x20]; 2809 2810 u8 crc_error_dllp[0x20]; 2811 2812 u8 crc_error_tlp[0x20]; 2813 2814 u8 tx_overflow_buffer_pkt_high[0x20]; 2815 2816 u8 tx_overflow_buffer_pkt_low[0x20]; 2817 2818 u8 outbound_stalled_reads[0x20]; 2819 2820 u8 outbound_stalled_writes[0x20]; 2821 2822 u8 outbound_stalled_reads_events[0x20]; 2823 2824 u8 outbound_stalled_writes_events[0x20]; 2825 2826 u8 reserved_at_200[0x5c0]; 2827 }; 2828 2829 struct mlx5_ifc_cmd_inter_comp_event_bits { 2830 u8 command_completion_vector[0x20]; 2831 2832 u8 reserved_at_20[0xc0]; 2833 }; 2834 2835 struct mlx5_ifc_stall_vl_event_bits { 2836 u8 reserved_at_0[0x18]; 2837 u8 port_num[0x1]; 2838 u8 reserved_at_19[0x3]; 2839 u8 vl[0x4]; 2840 2841 u8 reserved_at_20[0xa0]; 2842 }; 2843 2844 struct mlx5_ifc_db_bf_congestion_event_bits { 2845 u8 event_subtype[0x8]; 2846 u8 reserved_at_8[0x8]; 2847 u8 congestion_level[0x8]; 2848 u8 reserved_at_18[0x8]; 2849 2850 u8 reserved_at_20[0xa0]; 2851 }; 2852 2853 struct mlx5_ifc_gpio_event_bits { 2854 u8 reserved_at_0[0x60]; 2855 2856 u8 gpio_event_hi[0x20]; 2857 2858 u8 gpio_event_lo[0x20]; 2859 2860 u8 reserved_at_a0[0x40]; 2861 }; 2862 2863 struct mlx5_ifc_port_state_change_event_bits { 2864 u8 reserved_at_0[0x40]; 2865 2866 u8 port_num[0x4]; 2867 u8 reserved_at_44[0x1c]; 2868 2869 u8 reserved_at_60[0x80]; 2870 }; 2871 2872 struct mlx5_ifc_dropped_packet_logged_bits { 2873 u8 reserved_at_0[0xe0]; 2874 }; 2875 2876 struct mlx5_ifc_default_timeout_bits { 2877 u8 to_multiplier[0x3]; 2878 u8 reserved_at_3[0x9]; 2879 u8 to_value[0x14]; 2880 }; 2881 2882 struct mlx5_ifc_dtor_reg_bits { 2883 u8 reserved_at_0[0x20]; 2884 2885 struct mlx5_ifc_default_timeout_bits pcie_toggle_to; 2886 2887 u8 reserved_at_40[0x60]; 2888 2889 struct mlx5_ifc_default_timeout_bits health_poll_to; 2890 2891 struct mlx5_ifc_default_timeout_bits full_crdump_to; 2892 2893 struct mlx5_ifc_default_timeout_bits fw_reset_to; 2894 2895 struct mlx5_ifc_default_timeout_bits flush_on_err_to; 2896 2897 struct mlx5_ifc_default_timeout_bits pci_sync_update_to; 2898 2899 struct mlx5_ifc_default_timeout_bits tear_down_to; 2900 2901 struct mlx5_ifc_default_timeout_bits fsm_reactivate_to; 2902 2903 struct mlx5_ifc_default_timeout_bits reclaim_pages_to; 2904 2905 struct mlx5_ifc_default_timeout_bits reclaim_vfs_pages_to; 2906 2907 u8 reserved_at_1c0[0x40]; 2908 }; 2909 2910 enum { 2911 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1, 2912 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2, 2913 }; 2914 2915 struct mlx5_ifc_cq_error_bits { 2916 u8 reserved_at_0[0x8]; 2917 u8 cqn[0x18]; 2918 2919 u8 reserved_at_20[0x20]; 2920 2921 u8 reserved_at_40[0x18]; 2922 u8 syndrome[0x8]; 2923 2924 u8 reserved_at_60[0x80]; 2925 }; 2926 2927 struct mlx5_ifc_rdma_page_fault_event_bits { 2928 u8 bytes_committed[0x20]; 2929 2930 u8 r_key[0x20]; 2931 2932 u8 reserved_at_40[0x10]; 2933 u8 packet_len[0x10]; 2934 2935 u8 rdma_op_len[0x20]; 2936 2937 u8 rdma_va[0x40]; 2938 2939 u8 reserved_at_c0[0x5]; 2940 u8 rdma[0x1]; 2941 u8 write[0x1]; 2942 u8 requestor[0x1]; 2943 u8 qp_number[0x18]; 2944 }; 2945 2946 struct mlx5_ifc_wqe_associated_page_fault_event_bits { 2947 u8 bytes_committed[0x20]; 2948 2949 u8 reserved_at_20[0x10]; 2950 u8 wqe_index[0x10]; 2951 2952 u8 reserved_at_40[0x10]; 2953 u8 len[0x10]; 2954 2955 u8 reserved_at_60[0x60]; 2956 2957 u8 reserved_at_c0[0x5]; 2958 u8 rdma[0x1]; 2959 u8 write_read[0x1]; 2960 u8 requestor[0x1]; 2961 u8 qpn[0x18]; 2962 }; 2963 2964 struct mlx5_ifc_qp_events_bits { 2965 u8 reserved_at_0[0xa0]; 2966 2967 u8 type[0x8]; 2968 u8 reserved_at_a8[0x18]; 2969 2970 u8 reserved_at_c0[0x8]; 2971 u8 qpn_rqn_sqn[0x18]; 2972 }; 2973 2974 struct mlx5_ifc_dct_events_bits { 2975 u8 reserved_at_0[0xc0]; 2976 2977 u8 reserved_at_c0[0x8]; 2978 u8 dct_number[0x18]; 2979 }; 2980 2981 struct mlx5_ifc_comp_event_bits { 2982 u8 reserved_at_0[0xc0]; 2983 2984 u8 reserved_at_c0[0x8]; 2985 u8 cq_number[0x18]; 2986 }; 2987 2988 enum { 2989 MLX5_QPC_STATE_RST = 0x0, 2990 MLX5_QPC_STATE_INIT = 0x1, 2991 MLX5_QPC_STATE_RTR = 0x2, 2992 MLX5_QPC_STATE_RTS = 0x3, 2993 MLX5_QPC_STATE_SQER = 0x4, 2994 MLX5_QPC_STATE_ERR = 0x6, 2995 MLX5_QPC_STATE_SQD = 0x7, 2996 MLX5_QPC_STATE_SUSPENDED = 0x9, 2997 }; 2998 2999 enum { 3000 MLX5_QPC_ST_RC = 0x0, 3001 MLX5_QPC_ST_UC = 0x1, 3002 MLX5_QPC_ST_UD = 0x2, 3003 MLX5_QPC_ST_XRC = 0x3, 3004 MLX5_QPC_ST_DCI = 0x5, 3005 MLX5_QPC_ST_QP0 = 0x7, 3006 MLX5_QPC_ST_QP1 = 0x8, 3007 MLX5_QPC_ST_RAW_DATAGRAM = 0x9, 3008 MLX5_QPC_ST_REG_UMR = 0xc, 3009 }; 3010 3011 enum { 3012 MLX5_QPC_PM_STATE_ARMED = 0x0, 3013 MLX5_QPC_PM_STATE_REARM = 0x1, 3014 MLX5_QPC_PM_STATE_RESERVED = 0x2, 3015 MLX5_QPC_PM_STATE_MIGRATED = 0x3, 3016 }; 3017 3018 enum { 3019 MLX5_QPC_OFFLOAD_TYPE_RNDV = 0x1, 3020 }; 3021 3022 enum { 3023 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0, 3024 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1, 3025 }; 3026 3027 enum { 3028 MLX5_QPC_MTU_256_BYTES = 0x1, 3029 MLX5_QPC_MTU_512_BYTES = 0x2, 3030 MLX5_QPC_MTU_1K_BYTES = 0x3, 3031 MLX5_QPC_MTU_2K_BYTES = 0x4, 3032 MLX5_QPC_MTU_4K_BYTES = 0x5, 3033 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7, 3034 }; 3035 3036 enum { 3037 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1, 3038 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2, 3039 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3, 3040 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4, 3041 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5, 3042 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6, 3043 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7, 3044 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8, 3045 }; 3046 3047 enum { 3048 MLX5_QPC_CS_REQ_DISABLE = 0x0, 3049 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11, 3050 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22, 3051 }; 3052 3053 enum { 3054 MLX5_QPC_CS_RES_DISABLE = 0x0, 3055 MLX5_QPC_CS_RES_UP_TO_32B = 0x1, 3056 MLX5_QPC_CS_RES_UP_TO_64B = 0x2, 3057 }; 3058 3059 enum { 3060 MLX5_TIMESTAMP_FORMAT_FREE_RUNNING = 0x0, 3061 MLX5_TIMESTAMP_FORMAT_DEFAULT = 0x1, 3062 MLX5_TIMESTAMP_FORMAT_REAL_TIME = 0x2, 3063 }; 3064 3065 struct mlx5_ifc_qpc_bits { 3066 u8 state[0x4]; 3067 u8 lag_tx_port_affinity[0x4]; 3068 u8 st[0x8]; 3069 u8 reserved_at_10[0x2]; 3070 u8 isolate_vl_tc[0x1]; 3071 u8 pm_state[0x2]; 3072 u8 reserved_at_15[0x1]; 3073 u8 req_e2e_credit_mode[0x2]; 3074 u8 offload_type[0x4]; 3075 u8 end_padding_mode[0x2]; 3076 u8 reserved_at_1e[0x2]; 3077 3078 u8 wq_signature[0x1]; 3079 u8 block_lb_mc[0x1]; 3080 u8 atomic_like_write_en[0x1]; 3081 u8 latency_sensitive[0x1]; 3082 u8 reserved_at_24[0x1]; 3083 u8 drain_sigerr[0x1]; 3084 u8 reserved_at_26[0x2]; 3085 u8 pd[0x18]; 3086 3087 u8 mtu[0x3]; 3088 u8 log_msg_max[0x5]; 3089 u8 reserved_at_48[0x1]; 3090 u8 log_rq_size[0x4]; 3091 u8 log_rq_stride[0x3]; 3092 u8 no_sq[0x1]; 3093 u8 log_sq_size[0x4]; 3094 u8 reserved_at_55[0x3]; 3095 u8 ts_format[0x2]; 3096 u8 reserved_at_5a[0x1]; 3097 u8 rlky[0x1]; 3098 u8 ulp_stateless_offload_mode[0x4]; 3099 3100 u8 counter_set_id[0x8]; 3101 u8 uar_page[0x18]; 3102 3103 u8 reserved_at_80[0x8]; 3104 u8 user_index[0x18]; 3105 3106 u8 reserved_at_a0[0x3]; 3107 u8 log_page_size[0x5]; 3108 u8 remote_qpn[0x18]; 3109 3110 struct mlx5_ifc_ads_bits primary_address_path; 3111 3112 struct mlx5_ifc_ads_bits secondary_address_path; 3113 3114 u8 log_ack_req_freq[0x4]; 3115 u8 reserved_at_384[0x4]; 3116 u8 log_sra_max[0x3]; 3117 u8 reserved_at_38b[0x2]; 3118 u8 retry_count[0x3]; 3119 u8 rnr_retry[0x3]; 3120 u8 reserved_at_393[0x1]; 3121 u8 fre[0x1]; 3122 u8 cur_rnr_retry[0x3]; 3123 u8 cur_retry_count[0x3]; 3124 u8 reserved_at_39b[0x5]; 3125 3126 u8 reserved_at_3a0[0x20]; 3127 3128 u8 reserved_at_3c0[0x8]; 3129 u8 next_send_psn[0x18]; 3130 3131 u8 reserved_at_3e0[0x3]; 3132 u8 log_num_dci_stream_channels[0x5]; 3133 u8 cqn_snd[0x18]; 3134 3135 u8 reserved_at_400[0x3]; 3136 u8 log_num_dci_errored_streams[0x5]; 3137 u8 deth_sqpn[0x18]; 3138 3139 u8 reserved_at_420[0x20]; 3140 3141 u8 reserved_at_440[0x8]; 3142 u8 last_acked_psn[0x18]; 3143 3144 u8 reserved_at_460[0x8]; 3145 u8 ssn[0x18]; 3146 3147 u8 reserved_at_480[0x8]; 3148 u8 log_rra_max[0x3]; 3149 u8 reserved_at_48b[0x1]; 3150 u8 atomic_mode[0x4]; 3151 u8 rre[0x1]; 3152 u8 rwe[0x1]; 3153 u8 rae[0x1]; 3154 u8 reserved_at_493[0x1]; 3155 u8 page_offset[0x6]; 3156 u8 reserved_at_49a[0x3]; 3157 u8 cd_slave_receive[0x1]; 3158 u8 cd_slave_send[0x1]; 3159 u8 cd_master[0x1]; 3160 3161 u8 reserved_at_4a0[0x3]; 3162 u8 min_rnr_nak[0x5]; 3163 u8 next_rcv_psn[0x18]; 3164 3165 u8 reserved_at_4c0[0x8]; 3166 u8 xrcd[0x18]; 3167 3168 u8 reserved_at_4e0[0x8]; 3169 u8 cqn_rcv[0x18]; 3170 3171 u8 dbr_addr[0x40]; 3172 3173 u8 q_key[0x20]; 3174 3175 u8 reserved_at_560[0x5]; 3176 u8 rq_type[0x3]; 3177 u8 srqn_rmpn_xrqn[0x18]; 3178 3179 u8 reserved_at_580[0x8]; 3180 u8 rmsn[0x18]; 3181 3182 u8 hw_sq_wqebb_counter[0x10]; 3183 u8 sw_sq_wqebb_counter[0x10]; 3184 3185 u8 hw_rq_counter[0x20]; 3186 3187 u8 sw_rq_counter[0x20]; 3188 3189 u8 reserved_at_600[0x20]; 3190 3191 u8 reserved_at_620[0xf]; 3192 u8 cgs[0x1]; 3193 u8 cs_req[0x8]; 3194 u8 cs_res[0x8]; 3195 3196 u8 dc_access_key[0x40]; 3197 3198 u8 reserved_at_680[0x3]; 3199 u8 dbr_umem_valid[0x1]; 3200 3201 u8 reserved_at_684[0xbc]; 3202 }; 3203 3204 struct mlx5_ifc_roce_addr_layout_bits { 3205 u8 source_l3_address[16][0x8]; 3206 3207 u8 reserved_at_80[0x3]; 3208 u8 vlan_valid[0x1]; 3209 u8 vlan_id[0xc]; 3210 u8 source_mac_47_32[0x10]; 3211 3212 u8 source_mac_31_0[0x20]; 3213 3214 u8 reserved_at_c0[0x14]; 3215 u8 roce_l3_type[0x4]; 3216 u8 roce_version[0x8]; 3217 3218 u8 reserved_at_e0[0x20]; 3219 }; 3220 3221 struct mlx5_ifc_shampo_cap_bits { 3222 u8 reserved_at_0[0x3]; 3223 u8 shampo_log_max_reservation_size[0x5]; 3224 u8 reserved_at_8[0x3]; 3225 u8 shampo_log_min_reservation_size[0x5]; 3226 u8 shampo_min_mss_size[0x10]; 3227 3228 u8 reserved_at_20[0x3]; 3229 u8 shampo_max_log_headers_entry_size[0x5]; 3230 u8 reserved_at_28[0x18]; 3231 3232 u8 reserved_at_40[0x7c0]; 3233 }; 3234 3235 union mlx5_ifc_hca_cap_union_bits { 3236 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap; 3237 struct mlx5_ifc_cmd_hca_cap_2_bits cmd_hca_cap_2; 3238 struct mlx5_ifc_odp_cap_bits odp_cap; 3239 struct mlx5_ifc_atomic_caps_bits atomic_caps; 3240 struct mlx5_ifc_roce_cap_bits roce_cap; 3241 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps; 3242 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap; 3243 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap; 3244 struct mlx5_ifc_e_switch_cap_bits e_switch_cap; 3245 struct mlx5_ifc_port_selection_cap_bits port_selection_cap; 3246 struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap; 3247 struct mlx5_ifc_qos_cap_bits qos_cap; 3248 struct mlx5_ifc_debug_cap_bits debug_cap; 3249 struct mlx5_ifc_fpga_cap_bits fpga_cap; 3250 struct mlx5_ifc_tls_cap_bits tls_cap; 3251 struct mlx5_ifc_device_mem_cap_bits device_mem_cap; 3252 struct mlx5_ifc_virtio_emulation_cap_bits virtio_emulation_cap; 3253 struct mlx5_ifc_shampo_cap_bits shampo_cap; 3254 u8 reserved_at_0[0x8000]; 3255 }; 3256 3257 enum { 3258 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1, 3259 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2, 3260 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4, 3261 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8, 3262 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT = 0x10, 3263 MLX5_FLOW_CONTEXT_ACTION_DECAP = 0x20, 3264 MLX5_FLOW_CONTEXT_ACTION_MOD_HDR = 0x40, 3265 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP = 0x80, 3266 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100, 3267 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2 = 0x400, 3268 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2 = 0x800, 3269 MLX5_FLOW_CONTEXT_ACTION_IPSEC_DECRYPT = 0x1000, 3270 MLX5_FLOW_CONTEXT_ACTION_IPSEC_ENCRYPT = 0x2000, 3271 }; 3272 3273 enum { 3274 MLX5_FLOW_CONTEXT_FLOW_SOURCE_ANY_VPORT = 0x0, 3275 MLX5_FLOW_CONTEXT_FLOW_SOURCE_UPLINK = 0x1, 3276 MLX5_FLOW_CONTEXT_FLOW_SOURCE_LOCAL_VPORT = 0x2, 3277 }; 3278 3279 struct mlx5_ifc_vlan_bits { 3280 u8 ethtype[0x10]; 3281 u8 prio[0x3]; 3282 u8 cfi[0x1]; 3283 u8 vid[0xc]; 3284 }; 3285 3286 struct mlx5_ifc_flow_context_bits { 3287 struct mlx5_ifc_vlan_bits push_vlan; 3288 3289 u8 group_id[0x20]; 3290 3291 u8 reserved_at_40[0x8]; 3292 u8 flow_tag[0x18]; 3293 3294 u8 reserved_at_60[0x10]; 3295 u8 action[0x10]; 3296 3297 u8 extended_destination[0x1]; 3298 u8 reserved_at_81[0x1]; 3299 u8 flow_source[0x2]; 3300 u8 reserved_at_84[0x4]; 3301 u8 destination_list_size[0x18]; 3302 3303 u8 reserved_at_a0[0x8]; 3304 u8 flow_counter_list_size[0x18]; 3305 3306 u8 packet_reformat_id[0x20]; 3307 3308 u8 modify_header_id[0x20]; 3309 3310 struct mlx5_ifc_vlan_bits push_vlan_2; 3311 3312 u8 ipsec_obj_id[0x20]; 3313 u8 reserved_at_140[0xc0]; 3314 3315 struct mlx5_ifc_fte_match_param_bits match_value; 3316 3317 u8 reserved_at_1200[0x600]; 3318 3319 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[]; 3320 }; 3321 3322 enum { 3323 MLX5_XRC_SRQC_STATE_GOOD = 0x0, 3324 MLX5_XRC_SRQC_STATE_ERROR = 0x1, 3325 }; 3326 3327 struct mlx5_ifc_xrc_srqc_bits { 3328 u8 state[0x4]; 3329 u8 log_xrc_srq_size[0x4]; 3330 u8 reserved_at_8[0x18]; 3331 3332 u8 wq_signature[0x1]; 3333 u8 cont_srq[0x1]; 3334 u8 reserved_at_22[0x1]; 3335 u8 rlky[0x1]; 3336 u8 basic_cyclic_rcv_wqe[0x1]; 3337 u8 log_rq_stride[0x3]; 3338 u8 xrcd[0x18]; 3339 3340 u8 page_offset[0x6]; 3341 u8 reserved_at_46[0x1]; 3342 u8 dbr_umem_valid[0x1]; 3343 u8 cqn[0x18]; 3344 3345 u8 reserved_at_60[0x20]; 3346 3347 u8 user_index_equal_xrc_srqn[0x1]; 3348 u8 reserved_at_81[0x1]; 3349 u8 log_page_size[0x6]; 3350 u8 user_index[0x18]; 3351 3352 u8 reserved_at_a0[0x20]; 3353 3354 u8 reserved_at_c0[0x8]; 3355 u8 pd[0x18]; 3356 3357 u8 lwm[0x10]; 3358 u8 wqe_cnt[0x10]; 3359 3360 u8 reserved_at_100[0x40]; 3361 3362 u8 db_record_addr_h[0x20]; 3363 3364 u8 db_record_addr_l[0x1e]; 3365 u8 reserved_at_17e[0x2]; 3366 3367 u8 reserved_at_180[0x80]; 3368 }; 3369 3370 struct mlx5_ifc_vnic_diagnostic_statistics_bits { 3371 u8 counter_error_queues[0x20]; 3372 3373 u8 total_error_queues[0x20]; 3374 3375 u8 send_queue_priority_update_flow[0x20]; 3376 3377 u8 reserved_at_60[0x20]; 3378 3379 u8 nic_receive_steering_discard[0x40]; 3380 3381 u8 receive_discard_vport_down[0x40]; 3382 3383 u8 transmit_discard_vport_down[0x40]; 3384 3385 u8 reserved_at_140[0xa0]; 3386 3387 u8 internal_rq_out_of_buffer[0x20]; 3388 3389 u8 reserved_at_200[0xe00]; 3390 }; 3391 3392 struct mlx5_ifc_traffic_counter_bits { 3393 u8 packets[0x40]; 3394 3395 u8 octets[0x40]; 3396 }; 3397 3398 struct mlx5_ifc_tisc_bits { 3399 u8 strict_lag_tx_port_affinity[0x1]; 3400 u8 tls_en[0x1]; 3401 u8 reserved_at_2[0x2]; 3402 u8 lag_tx_port_affinity[0x04]; 3403 3404 u8 reserved_at_8[0x4]; 3405 u8 prio[0x4]; 3406 u8 reserved_at_10[0x10]; 3407 3408 u8 reserved_at_20[0x100]; 3409 3410 u8 reserved_at_120[0x8]; 3411 u8 transport_domain[0x18]; 3412 3413 u8 reserved_at_140[0x8]; 3414 u8 underlay_qpn[0x18]; 3415 3416 u8 reserved_at_160[0x8]; 3417 u8 pd[0x18]; 3418 3419 u8 reserved_at_180[0x380]; 3420 }; 3421 3422 enum { 3423 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0, 3424 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1, 3425 }; 3426 3427 enum { 3428 MLX5_TIRC_PACKET_MERGE_MASK_IPV4_LRO = BIT(0), 3429 MLX5_TIRC_PACKET_MERGE_MASK_IPV6_LRO = BIT(1), 3430 MLX5_TIRC_PACKET_MERGE_MASK_SHAMPO = BIT(2), 3431 }; 3432 3433 enum { 3434 MLX5_RX_HASH_FN_NONE = 0x0, 3435 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1, 3436 MLX5_RX_HASH_FN_TOEPLITZ = 0x2, 3437 }; 3438 3439 enum { 3440 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST = 0x1, 3441 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST = 0x2, 3442 }; 3443 3444 struct mlx5_ifc_tirc_bits { 3445 u8 reserved_at_0[0x20]; 3446 3447 u8 disp_type[0x4]; 3448 u8 tls_en[0x1]; 3449 u8 reserved_at_25[0x1b]; 3450 3451 u8 reserved_at_40[0x40]; 3452 3453 u8 reserved_at_80[0x4]; 3454 u8 lro_timeout_period_usecs[0x10]; 3455 u8 packet_merge_mask[0x4]; 3456 u8 lro_max_ip_payload_size[0x8]; 3457 3458 u8 reserved_at_a0[0x40]; 3459 3460 u8 reserved_at_e0[0x8]; 3461 u8 inline_rqn[0x18]; 3462 3463 u8 rx_hash_symmetric[0x1]; 3464 u8 reserved_at_101[0x1]; 3465 u8 tunneled_offload_en[0x1]; 3466 u8 reserved_at_103[0x5]; 3467 u8 indirect_table[0x18]; 3468 3469 u8 rx_hash_fn[0x4]; 3470 u8 reserved_at_124[0x2]; 3471 u8 self_lb_block[0x2]; 3472 u8 transport_domain[0x18]; 3473 3474 u8 rx_hash_toeplitz_key[10][0x20]; 3475 3476 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer; 3477 3478 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner; 3479 3480 u8 reserved_at_2c0[0x4c0]; 3481 }; 3482 3483 enum { 3484 MLX5_SRQC_STATE_GOOD = 0x0, 3485 MLX5_SRQC_STATE_ERROR = 0x1, 3486 }; 3487 3488 struct mlx5_ifc_srqc_bits { 3489 u8 state[0x4]; 3490 u8 log_srq_size[0x4]; 3491 u8 reserved_at_8[0x18]; 3492 3493 u8 wq_signature[0x1]; 3494 u8 cont_srq[0x1]; 3495 u8 reserved_at_22[0x1]; 3496 u8 rlky[0x1]; 3497 u8 reserved_at_24[0x1]; 3498 u8 log_rq_stride[0x3]; 3499 u8 xrcd[0x18]; 3500 3501 u8 page_offset[0x6]; 3502 u8 reserved_at_46[0x2]; 3503 u8 cqn[0x18]; 3504 3505 u8 reserved_at_60[0x20]; 3506 3507 u8 reserved_at_80[0x2]; 3508 u8 log_page_size[0x6]; 3509 u8 reserved_at_88[0x18]; 3510 3511 u8 reserved_at_a0[0x20]; 3512 3513 u8 reserved_at_c0[0x8]; 3514 u8 pd[0x18]; 3515 3516 u8 lwm[0x10]; 3517 u8 wqe_cnt[0x10]; 3518 3519 u8 reserved_at_100[0x40]; 3520 3521 u8 dbr_addr[0x40]; 3522 3523 u8 reserved_at_180[0x80]; 3524 }; 3525 3526 enum { 3527 MLX5_SQC_STATE_RST = 0x0, 3528 MLX5_SQC_STATE_RDY = 0x1, 3529 MLX5_SQC_STATE_ERR = 0x3, 3530 }; 3531 3532 struct mlx5_ifc_sqc_bits { 3533 u8 rlky[0x1]; 3534 u8 cd_master[0x1]; 3535 u8 fre[0x1]; 3536 u8 flush_in_error_en[0x1]; 3537 u8 allow_multi_pkt_send_wqe[0x1]; 3538 u8 min_wqe_inline_mode[0x3]; 3539 u8 state[0x4]; 3540 u8 reg_umr[0x1]; 3541 u8 allow_swp[0x1]; 3542 u8 hairpin[0x1]; 3543 u8 reserved_at_f[0xb]; 3544 u8 ts_format[0x2]; 3545 u8 reserved_at_1c[0x4]; 3546 3547 u8 reserved_at_20[0x8]; 3548 u8 user_index[0x18]; 3549 3550 u8 reserved_at_40[0x8]; 3551 u8 cqn[0x18]; 3552 3553 u8 reserved_at_60[0x8]; 3554 u8 hairpin_peer_rq[0x18]; 3555 3556 u8 reserved_at_80[0x10]; 3557 u8 hairpin_peer_vhca[0x10]; 3558 3559 u8 reserved_at_a0[0x20]; 3560 3561 u8 reserved_at_c0[0x8]; 3562 u8 ts_cqe_to_dest_cqn[0x18]; 3563 3564 u8 reserved_at_e0[0x10]; 3565 u8 packet_pacing_rate_limit_index[0x10]; 3566 u8 tis_lst_sz[0x10]; 3567 u8 qos_queue_group_id[0x10]; 3568 3569 u8 reserved_at_120[0x40]; 3570 3571 u8 reserved_at_160[0x8]; 3572 u8 tis_num_0[0x18]; 3573 3574 struct mlx5_ifc_wq_bits wq; 3575 }; 3576 3577 enum { 3578 SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0, 3579 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1, 3580 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2, 3581 SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3, 3582 SCHEDULING_CONTEXT_ELEMENT_TYPE_QUEUE_GROUP = 0x4, 3583 }; 3584 3585 enum { 3586 ELEMENT_TYPE_CAP_MASK_TASR = 1 << 0, 3587 ELEMENT_TYPE_CAP_MASK_VPORT = 1 << 1, 3588 ELEMENT_TYPE_CAP_MASK_VPORT_TC = 1 << 2, 3589 ELEMENT_TYPE_CAP_MASK_PARA_VPORT_TC = 1 << 3, 3590 }; 3591 3592 struct mlx5_ifc_scheduling_context_bits { 3593 u8 element_type[0x8]; 3594 u8 reserved_at_8[0x18]; 3595 3596 u8 element_attributes[0x20]; 3597 3598 u8 parent_element_id[0x20]; 3599 3600 u8 reserved_at_60[0x40]; 3601 3602 u8 bw_share[0x20]; 3603 3604 u8 max_average_bw[0x20]; 3605 3606 u8 reserved_at_e0[0x120]; 3607 }; 3608 3609 struct mlx5_ifc_rqtc_bits { 3610 u8 reserved_at_0[0xa0]; 3611 3612 u8 reserved_at_a0[0x5]; 3613 u8 list_q_type[0x3]; 3614 u8 reserved_at_a8[0x8]; 3615 u8 rqt_max_size[0x10]; 3616 3617 u8 rq_vhca_id_format[0x1]; 3618 u8 reserved_at_c1[0xf]; 3619 u8 rqt_actual_size[0x10]; 3620 3621 u8 reserved_at_e0[0x6a0]; 3622 3623 struct mlx5_ifc_rq_num_bits rq_num[]; 3624 }; 3625 3626 enum { 3627 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0, 3628 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1, 3629 }; 3630 3631 enum { 3632 MLX5_RQC_STATE_RST = 0x0, 3633 MLX5_RQC_STATE_RDY = 0x1, 3634 MLX5_RQC_STATE_ERR = 0x3, 3635 }; 3636 3637 enum { 3638 MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_BYTE = 0x0, 3639 MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_STRIDE = 0x1, 3640 MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_PAGE = 0x2, 3641 }; 3642 3643 enum { 3644 MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_NO_MATCH = 0x0, 3645 MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_EXTENDED = 0x1, 3646 MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_FIVE_TUPLE = 0x2, 3647 }; 3648 3649 struct mlx5_ifc_rqc_bits { 3650 u8 rlky[0x1]; 3651 u8 delay_drop_en[0x1]; 3652 u8 scatter_fcs[0x1]; 3653 u8 vsd[0x1]; 3654 u8 mem_rq_type[0x4]; 3655 u8 state[0x4]; 3656 u8 reserved_at_c[0x1]; 3657 u8 flush_in_error_en[0x1]; 3658 u8 hairpin[0x1]; 3659 u8 reserved_at_f[0xb]; 3660 u8 ts_format[0x2]; 3661 u8 reserved_at_1c[0x4]; 3662 3663 u8 reserved_at_20[0x8]; 3664 u8 user_index[0x18]; 3665 3666 u8 reserved_at_40[0x8]; 3667 u8 cqn[0x18]; 3668 3669 u8 counter_set_id[0x8]; 3670 u8 reserved_at_68[0x18]; 3671 3672 u8 reserved_at_80[0x8]; 3673 u8 rmpn[0x18]; 3674 3675 u8 reserved_at_a0[0x8]; 3676 u8 hairpin_peer_sq[0x18]; 3677 3678 u8 reserved_at_c0[0x10]; 3679 u8 hairpin_peer_vhca[0x10]; 3680 3681 u8 reserved_at_e0[0x46]; 3682 u8 shampo_no_match_alignment_granularity[0x2]; 3683 u8 reserved_at_128[0x6]; 3684 u8 shampo_match_criteria_type[0x2]; 3685 u8 reservation_timeout[0x10]; 3686 3687 u8 reserved_at_140[0x40]; 3688 3689 struct mlx5_ifc_wq_bits wq; 3690 }; 3691 3692 enum { 3693 MLX5_RMPC_STATE_RDY = 0x1, 3694 MLX5_RMPC_STATE_ERR = 0x3, 3695 }; 3696 3697 struct mlx5_ifc_rmpc_bits { 3698 u8 reserved_at_0[0x8]; 3699 u8 state[0x4]; 3700 u8 reserved_at_c[0x14]; 3701 3702 u8 basic_cyclic_rcv_wqe[0x1]; 3703 u8 reserved_at_21[0x1f]; 3704 3705 u8 reserved_at_40[0x140]; 3706 3707 struct mlx5_ifc_wq_bits wq; 3708 }; 3709 3710 struct mlx5_ifc_nic_vport_context_bits { 3711 u8 reserved_at_0[0x5]; 3712 u8 min_wqe_inline_mode[0x3]; 3713 u8 reserved_at_8[0x15]; 3714 u8 disable_mc_local_lb[0x1]; 3715 u8 disable_uc_local_lb[0x1]; 3716 u8 roce_en[0x1]; 3717 3718 u8 arm_change_event[0x1]; 3719 u8 reserved_at_21[0x1a]; 3720 u8 event_on_mtu[0x1]; 3721 u8 event_on_promisc_change[0x1]; 3722 u8 event_on_vlan_change[0x1]; 3723 u8 event_on_mc_address_change[0x1]; 3724 u8 event_on_uc_address_change[0x1]; 3725 3726 u8 reserved_at_40[0xc]; 3727 3728 u8 affiliation_criteria[0x4]; 3729 u8 affiliated_vhca_id[0x10]; 3730 3731 u8 reserved_at_60[0xd0]; 3732 3733 u8 mtu[0x10]; 3734 3735 u8 system_image_guid[0x40]; 3736 u8 port_guid[0x40]; 3737 u8 node_guid[0x40]; 3738 3739 u8 reserved_at_200[0x140]; 3740 u8 qkey_violation_counter[0x10]; 3741 u8 reserved_at_350[0x430]; 3742 3743 u8 promisc_uc[0x1]; 3744 u8 promisc_mc[0x1]; 3745 u8 promisc_all[0x1]; 3746 u8 reserved_at_783[0x2]; 3747 u8 allowed_list_type[0x3]; 3748 u8 reserved_at_788[0xc]; 3749 u8 allowed_list_size[0xc]; 3750 3751 struct mlx5_ifc_mac_address_layout_bits permanent_address; 3752 3753 u8 reserved_at_7e0[0x20]; 3754 3755 u8 current_uc_mac_address[][0x40]; 3756 }; 3757 3758 enum { 3759 MLX5_MKC_ACCESS_MODE_PA = 0x0, 3760 MLX5_MKC_ACCESS_MODE_MTT = 0x1, 3761 MLX5_MKC_ACCESS_MODE_KLMS = 0x2, 3762 MLX5_MKC_ACCESS_MODE_KSM = 0x3, 3763 MLX5_MKC_ACCESS_MODE_SW_ICM = 0x4, 3764 MLX5_MKC_ACCESS_MODE_MEMIC = 0x5, 3765 }; 3766 3767 struct mlx5_ifc_mkc_bits { 3768 u8 reserved_at_0[0x1]; 3769 u8 free[0x1]; 3770 u8 reserved_at_2[0x1]; 3771 u8 access_mode_4_2[0x3]; 3772 u8 reserved_at_6[0x7]; 3773 u8 relaxed_ordering_write[0x1]; 3774 u8 reserved_at_e[0x1]; 3775 u8 small_fence_on_rdma_read_response[0x1]; 3776 u8 umr_en[0x1]; 3777 u8 a[0x1]; 3778 u8 rw[0x1]; 3779 u8 rr[0x1]; 3780 u8 lw[0x1]; 3781 u8 lr[0x1]; 3782 u8 access_mode_1_0[0x2]; 3783 u8 reserved_at_18[0x8]; 3784 3785 u8 qpn[0x18]; 3786 u8 mkey_7_0[0x8]; 3787 3788 u8 reserved_at_40[0x20]; 3789 3790 u8 length64[0x1]; 3791 u8 bsf_en[0x1]; 3792 u8 sync_umr[0x1]; 3793 u8 reserved_at_63[0x2]; 3794 u8 expected_sigerr_count[0x1]; 3795 u8 reserved_at_66[0x1]; 3796 u8 en_rinval[0x1]; 3797 u8 pd[0x18]; 3798 3799 u8 start_addr[0x40]; 3800 3801 u8 len[0x40]; 3802 3803 u8 bsf_octword_size[0x20]; 3804 3805 u8 reserved_at_120[0x80]; 3806 3807 u8 translations_octword_size[0x20]; 3808 3809 u8 reserved_at_1c0[0x19]; 3810 u8 relaxed_ordering_read[0x1]; 3811 u8 reserved_at_1d9[0x1]; 3812 u8 log_page_size[0x5]; 3813 3814 u8 reserved_at_1e0[0x20]; 3815 }; 3816 3817 struct mlx5_ifc_pkey_bits { 3818 u8 reserved_at_0[0x10]; 3819 u8 pkey[0x10]; 3820 }; 3821 3822 struct mlx5_ifc_array128_auto_bits { 3823 u8 array128_auto[16][0x8]; 3824 }; 3825 3826 struct mlx5_ifc_hca_vport_context_bits { 3827 u8 field_select[0x20]; 3828 3829 u8 reserved_at_20[0xe0]; 3830 3831 u8 sm_virt_aware[0x1]; 3832 u8 has_smi[0x1]; 3833 u8 has_raw[0x1]; 3834 u8 grh_required[0x1]; 3835 u8 reserved_at_104[0xc]; 3836 u8 port_physical_state[0x4]; 3837 u8 vport_state_policy[0x4]; 3838 u8 port_state[0x4]; 3839 u8 vport_state[0x4]; 3840 3841 u8 reserved_at_120[0x20]; 3842 3843 u8 system_image_guid[0x40]; 3844 3845 u8 port_guid[0x40]; 3846 3847 u8 node_guid[0x40]; 3848 3849 u8 cap_mask1[0x20]; 3850 3851 u8 cap_mask1_field_select[0x20]; 3852 3853 u8 cap_mask2[0x20]; 3854 3855 u8 cap_mask2_field_select[0x20]; 3856 3857 u8 reserved_at_280[0x80]; 3858 3859 u8 lid[0x10]; 3860 u8 reserved_at_310[0x4]; 3861 u8 init_type_reply[0x4]; 3862 u8 lmc[0x3]; 3863 u8 subnet_timeout[0x5]; 3864 3865 u8 sm_lid[0x10]; 3866 u8 sm_sl[0x4]; 3867 u8 reserved_at_334[0xc]; 3868 3869 u8 qkey_violation_counter[0x10]; 3870 u8 pkey_violation_counter[0x10]; 3871 3872 u8 reserved_at_360[0xca0]; 3873 }; 3874 3875 struct mlx5_ifc_esw_vport_context_bits { 3876 u8 fdb_to_vport_reg_c[0x1]; 3877 u8 reserved_at_1[0x2]; 3878 u8 vport_svlan_strip[0x1]; 3879 u8 vport_cvlan_strip[0x1]; 3880 u8 vport_svlan_insert[0x1]; 3881 u8 vport_cvlan_insert[0x2]; 3882 u8 fdb_to_vport_reg_c_id[0x8]; 3883 u8 reserved_at_10[0x10]; 3884 3885 u8 reserved_at_20[0x20]; 3886 3887 u8 svlan_cfi[0x1]; 3888 u8 svlan_pcp[0x3]; 3889 u8 svlan_id[0xc]; 3890 u8 cvlan_cfi[0x1]; 3891 u8 cvlan_pcp[0x3]; 3892 u8 cvlan_id[0xc]; 3893 3894 u8 reserved_at_60[0x720]; 3895 3896 u8 sw_steering_vport_icm_address_rx[0x40]; 3897 3898 u8 sw_steering_vport_icm_address_tx[0x40]; 3899 }; 3900 3901 enum { 3902 MLX5_EQC_STATUS_OK = 0x0, 3903 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa, 3904 }; 3905 3906 enum { 3907 MLX5_EQC_ST_ARMED = 0x9, 3908 MLX5_EQC_ST_FIRED = 0xa, 3909 }; 3910 3911 struct mlx5_ifc_eqc_bits { 3912 u8 status[0x4]; 3913 u8 reserved_at_4[0x9]; 3914 u8 ec[0x1]; 3915 u8 oi[0x1]; 3916 u8 reserved_at_f[0x5]; 3917 u8 st[0x4]; 3918 u8 reserved_at_18[0x8]; 3919 3920 u8 reserved_at_20[0x20]; 3921 3922 u8 reserved_at_40[0x14]; 3923 u8 page_offset[0x6]; 3924 u8 reserved_at_5a[0x6]; 3925 3926 u8 reserved_at_60[0x3]; 3927 u8 log_eq_size[0x5]; 3928 u8 uar_page[0x18]; 3929 3930 u8 reserved_at_80[0x20]; 3931 3932 u8 reserved_at_a0[0x14]; 3933 u8 intr[0xc]; 3934 3935 u8 reserved_at_c0[0x3]; 3936 u8 log_page_size[0x5]; 3937 u8 reserved_at_c8[0x18]; 3938 3939 u8 reserved_at_e0[0x60]; 3940 3941 u8 reserved_at_140[0x8]; 3942 u8 consumer_counter[0x18]; 3943 3944 u8 reserved_at_160[0x8]; 3945 u8 producer_counter[0x18]; 3946 3947 u8 reserved_at_180[0x80]; 3948 }; 3949 3950 enum { 3951 MLX5_DCTC_STATE_ACTIVE = 0x0, 3952 MLX5_DCTC_STATE_DRAINING = 0x1, 3953 MLX5_DCTC_STATE_DRAINED = 0x2, 3954 }; 3955 3956 enum { 3957 MLX5_DCTC_CS_RES_DISABLE = 0x0, 3958 MLX5_DCTC_CS_RES_NA = 0x1, 3959 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2, 3960 }; 3961 3962 enum { 3963 MLX5_DCTC_MTU_256_BYTES = 0x1, 3964 MLX5_DCTC_MTU_512_BYTES = 0x2, 3965 MLX5_DCTC_MTU_1K_BYTES = 0x3, 3966 MLX5_DCTC_MTU_2K_BYTES = 0x4, 3967 MLX5_DCTC_MTU_4K_BYTES = 0x5, 3968 }; 3969 3970 struct mlx5_ifc_dctc_bits { 3971 u8 reserved_at_0[0x4]; 3972 u8 state[0x4]; 3973 u8 reserved_at_8[0x18]; 3974 3975 u8 reserved_at_20[0x8]; 3976 u8 user_index[0x18]; 3977 3978 u8 reserved_at_40[0x8]; 3979 u8 cqn[0x18]; 3980 3981 u8 counter_set_id[0x8]; 3982 u8 atomic_mode[0x4]; 3983 u8 rre[0x1]; 3984 u8 rwe[0x1]; 3985 u8 rae[0x1]; 3986 u8 atomic_like_write_en[0x1]; 3987 u8 latency_sensitive[0x1]; 3988 u8 rlky[0x1]; 3989 u8 free_ar[0x1]; 3990 u8 reserved_at_73[0xd]; 3991 3992 u8 reserved_at_80[0x8]; 3993 u8 cs_res[0x8]; 3994 u8 reserved_at_90[0x3]; 3995 u8 min_rnr_nak[0x5]; 3996 u8 reserved_at_98[0x8]; 3997 3998 u8 reserved_at_a0[0x8]; 3999 u8 srqn_xrqn[0x18]; 4000 4001 u8 reserved_at_c0[0x8]; 4002 u8 pd[0x18]; 4003 4004 u8 tclass[0x8]; 4005 u8 reserved_at_e8[0x4]; 4006 u8 flow_label[0x14]; 4007 4008 u8 dc_access_key[0x40]; 4009 4010 u8 reserved_at_140[0x5]; 4011 u8 mtu[0x3]; 4012 u8 port[0x8]; 4013 u8 pkey_index[0x10]; 4014 4015 u8 reserved_at_160[0x8]; 4016 u8 my_addr_index[0x8]; 4017 u8 reserved_at_170[0x8]; 4018 u8 hop_limit[0x8]; 4019 4020 u8 dc_access_key_violation_count[0x20]; 4021 4022 u8 reserved_at_1a0[0x14]; 4023 u8 dei_cfi[0x1]; 4024 u8 eth_prio[0x3]; 4025 u8 ecn[0x2]; 4026 u8 dscp[0x6]; 4027 4028 u8 reserved_at_1c0[0x20]; 4029 u8 ece[0x20]; 4030 }; 4031 4032 enum { 4033 MLX5_CQC_STATUS_OK = 0x0, 4034 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9, 4035 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa, 4036 }; 4037 4038 enum { 4039 MLX5_CQC_CQE_SZ_64_BYTES = 0x0, 4040 MLX5_CQC_CQE_SZ_128_BYTES = 0x1, 4041 }; 4042 4043 enum { 4044 MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED = 0x6, 4045 MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED = 0x9, 4046 MLX5_CQC_ST_FIRED = 0xa, 4047 }; 4048 4049 enum { 4050 MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0, 4051 MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1, 4052 MLX5_CQ_PERIOD_NUM_MODES 4053 }; 4054 4055 struct mlx5_ifc_cqc_bits { 4056 u8 status[0x4]; 4057 u8 reserved_at_4[0x2]; 4058 u8 dbr_umem_valid[0x1]; 4059 u8 apu_cq[0x1]; 4060 u8 cqe_sz[0x3]; 4061 u8 cc[0x1]; 4062 u8 reserved_at_c[0x1]; 4063 u8 scqe_break_moderation_en[0x1]; 4064 u8 oi[0x1]; 4065 u8 cq_period_mode[0x2]; 4066 u8 cqe_comp_en[0x1]; 4067 u8 mini_cqe_res_format[0x2]; 4068 u8 st[0x4]; 4069 u8 reserved_at_18[0x8]; 4070 4071 u8 reserved_at_20[0x20]; 4072 4073 u8 reserved_at_40[0x14]; 4074 u8 page_offset[0x6]; 4075 u8 reserved_at_5a[0x6]; 4076 4077 u8 reserved_at_60[0x3]; 4078 u8 log_cq_size[0x5]; 4079 u8 uar_page[0x18]; 4080 4081 u8 reserved_at_80[0x4]; 4082 u8 cq_period[0xc]; 4083 u8 cq_max_count[0x10]; 4084 4085 u8 c_eqn_or_apu_element[0x20]; 4086 4087 u8 reserved_at_c0[0x3]; 4088 u8 log_page_size[0x5]; 4089 u8 reserved_at_c8[0x18]; 4090 4091 u8 reserved_at_e0[0x20]; 4092 4093 u8 reserved_at_100[0x8]; 4094 u8 last_notified_index[0x18]; 4095 4096 u8 reserved_at_120[0x8]; 4097 u8 last_solicit_index[0x18]; 4098 4099 u8 reserved_at_140[0x8]; 4100 u8 consumer_counter[0x18]; 4101 4102 u8 reserved_at_160[0x8]; 4103 u8 producer_counter[0x18]; 4104 4105 u8 reserved_at_180[0x40]; 4106 4107 u8 dbr_addr[0x40]; 4108 }; 4109 4110 union mlx5_ifc_cong_control_roce_ecn_auto_bits { 4111 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp; 4112 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp; 4113 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np; 4114 u8 reserved_at_0[0x800]; 4115 }; 4116 4117 struct mlx5_ifc_query_adapter_param_block_bits { 4118 u8 reserved_at_0[0xc0]; 4119 4120 u8 reserved_at_c0[0x8]; 4121 u8 ieee_vendor_id[0x18]; 4122 4123 u8 reserved_at_e0[0x10]; 4124 u8 vsd_vendor_id[0x10]; 4125 4126 u8 vsd[208][0x8]; 4127 4128 u8 vsd_contd_psid[16][0x8]; 4129 }; 4130 4131 enum { 4132 MLX5_XRQC_STATE_GOOD = 0x0, 4133 MLX5_XRQC_STATE_ERROR = 0x1, 4134 }; 4135 4136 enum { 4137 MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0, 4138 MLX5_XRQC_TOPOLOGY_TAG_MATCHING = 0x1, 4139 }; 4140 4141 enum { 4142 MLX5_XRQC_OFFLOAD_RNDV = 0x1, 4143 }; 4144 4145 struct mlx5_ifc_tag_matching_topology_context_bits { 4146 u8 log_matching_list_sz[0x4]; 4147 u8 reserved_at_4[0xc]; 4148 u8 append_next_index[0x10]; 4149 4150 u8 sw_phase_cnt[0x10]; 4151 u8 hw_phase_cnt[0x10]; 4152 4153 u8 reserved_at_40[0x40]; 4154 }; 4155 4156 struct mlx5_ifc_xrqc_bits { 4157 u8 state[0x4]; 4158 u8 rlkey[0x1]; 4159 u8 reserved_at_5[0xf]; 4160 u8 topology[0x4]; 4161 u8 reserved_at_18[0x4]; 4162 u8 offload[0x4]; 4163 4164 u8 reserved_at_20[0x8]; 4165 u8 user_index[0x18]; 4166 4167 u8 reserved_at_40[0x8]; 4168 u8 cqn[0x18]; 4169 4170 u8 reserved_at_60[0xa0]; 4171 4172 struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context; 4173 4174 u8 reserved_at_180[0x280]; 4175 4176 struct mlx5_ifc_wq_bits wq; 4177 }; 4178 4179 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits { 4180 struct mlx5_ifc_modify_field_select_bits modify_field_select; 4181 struct mlx5_ifc_resize_field_select_bits resize_field_select; 4182 u8 reserved_at_0[0x20]; 4183 }; 4184 4185 union mlx5_ifc_field_select_802_1_r_roce_auto_bits { 4186 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp; 4187 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp; 4188 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np; 4189 u8 reserved_at_0[0x20]; 4190 }; 4191 4192 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits { 4193 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 4194 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 4195 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 4196 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 4197 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 4198 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 4199 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout; 4200 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout; 4201 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 4202 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 4203 struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs; 4204 u8 reserved_at_0[0x7c0]; 4205 }; 4206 4207 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits { 4208 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout; 4209 u8 reserved_at_0[0x7c0]; 4210 }; 4211 4212 union mlx5_ifc_event_auto_bits { 4213 struct mlx5_ifc_comp_event_bits comp_event; 4214 struct mlx5_ifc_dct_events_bits dct_events; 4215 struct mlx5_ifc_qp_events_bits qp_events; 4216 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event; 4217 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event; 4218 struct mlx5_ifc_cq_error_bits cq_error; 4219 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged; 4220 struct mlx5_ifc_port_state_change_event_bits port_state_change_event; 4221 struct mlx5_ifc_gpio_event_bits gpio_event; 4222 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event; 4223 struct mlx5_ifc_stall_vl_event_bits stall_vl_event; 4224 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event; 4225 u8 reserved_at_0[0xe0]; 4226 }; 4227 4228 struct mlx5_ifc_health_buffer_bits { 4229 u8 reserved_at_0[0x100]; 4230 4231 u8 assert_existptr[0x20]; 4232 4233 u8 assert_callra[0x20]; 4234 4235 u8 reserved_at_140[0x20]; 4236 4237 u8 time[0x20]; 4238 4239 u8 fw_version[0x20]; 4240 4241 u8 hw_id[0x20]; 4242 4243 u8 rfr[0x1]; 4244 u8 reserved_at_1c1[0x3]; 4245 u8 valid[0x1]; 4246 u8 severity[0x3]; 4247 u8 reserved_at_1c8[0x18]; 4248 4249 u8 irisc_index[0x8]; 4250 u8 synd[0x8]; 4251 u8 ext_synd[0x10]; 4252 }; 4253 4254 struct mlx5_ifc_register_loopback_control_bits { 4255 u8 no_lb[0x1]; 4256 u8 reserved_at_1[0x7]; 4257 u8 port[0x8]; 4258 u8 reserved_at_10[0x10]; 4259 4260 u8 reserved_at_20[0x60]; 4261 }; 4262 4263 struct mlx5_ifc_vport_tc_element_bits { 4264 u8 traffic_class[0x4]; 4265 u8 reserved_at_4[0xc]; 4266 u8 vport_number[0x10]; 4267 }; 4268 4269 struct mlx5_ifc_vport_element_bits { 4270 u8 reserved_at_0[0x10]; 4271 u8 vport_number[0x10]; 4272 }; 4273 4274 enum { 4275 TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0, 4276 TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1, 4277 TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2, 4278 }; 4279 4280 struct mlx5_ifc_tsar_element_bits { 4281 u8 reserved_at_0[0x8]; 4282 u8 tsar_type[0x8]; 4283 u8 reserved_at_10[0x10]; 4284 }; 4285 4286 enum { 4287 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0, 4288 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1, 4289 }; 4290 4291 struct mlx5_ifc_teardown_hca_out_bits { 4292 u8 status[0x8]; 4293 u8 reserved_at_8[0x18]; 4294 4295 u8 syndrome[0x20]; 4296 4297 u8 reserved_at_40[0x3f]; 4298 4299 u8 state[0x1]; 4300 }; 4301 4302 enum { 4303 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0, 4304 MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE = 0x1, 4305 MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN = 0x2, 4306 }; 4307 4308 struct mlx5_ifc_teardown_hca_in_bits { 4309 u8 opcode[0x10]; 4310 u8 reserved_at_10[0x10]; 4311 4312 u8 reserved_at_20[0x10]; 4313 u8 op_mod[0x10]; 4314 4315 u8 reserved_at_40[0x10]; 4316 u8 profile[0x10]; 4317 4318 u8 reserved_at_60[0x20]; 4319 }; 4320 4321 struct mlx5_ifc_sqerr2rts_qp_out_bits { 4322 u8 status[0x8]; 4323 u8 reserved_at_8[0x18]; 4324 4325 u8 syndrome[0x20]; 4326 4327 u8 reserved_at_40[0x40]; 4328 }; 4329 4330 struct mlx5_ifc_sqerr2rts_qp_in_bits { 4331 u8 opcode[0x10]; 4332 u8 uid[0x10]; 4333 4334 u8 reserved_at_20[0x10]; 4335 u8 op_mod[0x10]; 4336 4337 u8 reserved_at_40[0x8]; 4338 u8 qpn[0x18]; 4339 4340 u8 reserved_at_60[0x20]; 4341 4342 u8 opt_param_mask[0x20]; 4343 4344 u8 reserved_at_a0[0x20]; 4345 4346 struct mlx5_ifc_qpc_bits qpc; 4347 4348 u8 reserved_at_800[0x80]; 4349 }; 4350 4351 struct mlx5_ifc_sqd2rts_qp_out_bits { 4352 u8 status[0x8]; 4353 u8 reserved_at_8[0x18]; 4354 4355 u8 syndrome[0x20]; 4356 4357 u8 reserved_at_40[0x40]; 4358 }; 4359 4360 struct mlx5_ifc_sqd2rts_qp_in_bits { 4361 u8 opcode[0x10]; 4362 u8 uid[0x10]; 4363 4364 u8 reserved_at_20[0x10]; 4365 u8 op_mod[0x10]; 4366 4367 u8 reserved_at_40[0x8]; 4368 u8 qpn[0x18]; 4369 4370 u8 reserved_at_60[0x20]; 4371 4372 u8 opt_param_mask[0x20]; 4373 4374 u8 reserved_at_a0[0x20]; 4375 4376 struct mlx5_ifc_qpc_bits qpc; 4377 4378 u8 reserved_at_800[0x80]; 4379 }; 4380 4381 struct mlx5_ifc_set_roce_address_out_bits { 4382 u8 status[0x8]; 4383 u8 reserved_at_8[0x18]; 4384 4385 u8 syndrome[0x20]; 4386 4387 u8 reserved_at_40[0x40]; 4388 }; 4389 4390 struct mlx5_ifc_set_roce_address_in_bits { 4391 u8 opcode[0x10]; 4392 u8 reserved_at_10[0x10]; 4393 4394 u8 reserved_at_20[0x10]; 4395 u8 op_mod[0x10]; 4396 4397 u8 roce_address_index[0x10]; 4398 u8 reserved_at_50[0xc]; 4399 u8 vhca_port_num[0x4]; 4400 4401 u8 reserved_at_60[0x20]; 4402 4403 struct mlx5_ifc_roce_addr_layout_bits roce_address; 4404 }; 4405 4406 struct mlx5_ifc_set_mad_demux_out_bits { 4407 u8 status[0x8]; 4408 u8 reserved_at_8[0x18]; 4409 4410 u8 syndrome[0x20]; 4411 4412 u8 reserved_at_40[0x40]; 4413 }; 4414 4415 enum { 4416 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0, 4417 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2, 4418 }; 4419 4420 struct mlx5_ifc_set_mad_demux_in_bits { 4421 u8 opcode[0x10]; 4422 u8 reserved_at_10[0x10]; 4423 4424 u8 reserved_at_20[0x10]; 4425 u8 op_mod[0x10]; 4426 4427 u8 reserved_at_40[0x20]; 4428 4429 u8 reserved_at_60[0x6]; 4430 u8 demux_mode[0x2]; 4431 u8 reserved_at_68[0x18]; 4432 }; 4433 4434 struct mlx5_ifc_set_l2_table_entry_out_bits { 4435 u8 status[0x8]; 4436 u8 reserved_at_8[0x18]; 4437 4438 u8 syndrome[0x20]; 4439 4440 u8 reserved_at_40[0x40]; 4441 }; 4442 4443 struct mlx5_ifc_set_l2_table_entry_in_bits { 4444 u8 opcode[0x10]; 4445 u8 reserved_at_10[0x10]; 4446 4447 u8 reserved_at_20[0x10]; 4448 u8 op_mod[0x10]; 4449 4450 u8 reserved_at_40[0x60]; 4451 4452 u8 reserved_at_a0[0x8]; 4453 u8 table_index[0x18]; 4454 4455 u8 reserved_at_c0[0x20]; 4456 4457 u8 reserved_at_e0[0x13]; 4458 u8 vlan_valid[0x1]; 4459 u8 vlan[0xc]; 4460 4461 struct mlx5_ifc_mac_address_layout_bits mac_address; 4462 4463 u8 reserved_at_140[0xc0]; 4464 }; 4465 4466 struct mlx5_ifc_set_issi_out_bits { 4467 u8 status[0x8]; 4468 u8 reserved_at_8[0x18]; 4469 4470 u8 syndrome[0x20]; 4471 4472 u8 reserved_at_40[0x40]; 4473 }; 4474 4475 struct mlx5_ifc_set_issi_in_bits { 4476 u8 opcode[0x10]; 4477 u8 reserved_at_10[0x10]; 4478 4479 u8 reserved_at_20[0x10]; 4480 u8 op_mod[0x10]; 4481 4482 u8 reserved_at_40[0x10]; 4483 u8 current_issi[0x10]; 4484 4485 u8 reserved_at_60[0x20]; 4486 }; 4487 4488 struct mlx5_ifc_set_hca_cap_out_bits { 4489 u8 status[0x8]; 4490 u8 reserved_at_8[0x18]; 4491 4492 u8 syndrome[0x20]; 4493 4494 u8 reserved_at_40[0x40]; 4495 }; 4496 4497 struct mlx5_ifc_set_hca_cap_in_bits { 4498 u8 opcode[0x10]; 4499 u8 reserved_at_10[0x10]; 4500 4501 u8 reserved_at_20[0x10]; 4502 u8 op_mod[0x10]; 4503 4504 u8 other_function[0x1]; 4505 u8 reserved_at_41[0xf]; 4506 u8 function_id[0x10]; 4507 4508 u8 reserved_at_60[0x20]; 4509 4510 union mlx5_ifc_hca_cap_union_bits capability; 4511 }; 4512 4513 enum { 4514 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0, 4515 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1, 4516 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2, 4517 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3, 4518 MLX5_SET_FTE_MODIFY_ENABLE_MASK_IPSEC_OBJ_ID = 0x4 4519 }; 4520 4521 struct mlx5_ifc_set_fte_out_bits { 4522 u8 status[0x8]; 4523 u8 reserved_at_8[0x18]; 4524 4525 u8 syndrome[0x20]; 4526 4527 u8 reserved_at_40[0x40]; 4528 }; 4529 4530 struct mlx5_ifc_set_fte_in_bits { 4531 u8 opcode[0x10]; 4532 u8 reserved_at_10[0x10]; 4533 4534 u8 reserved_at_20[0x10]; 4535 u8 op_mod[0x10]; 4536 4537 u8 other_vport[0x1]; 4538 u8 reserved_at_41[0xf]; 4539 u8 vport_number[0x10]; 4540 4541 u8 reserved_at_60[0x20]; 4542 4543 u8 table_type[0x8]; 4544 u8 reserved_at_88[0x18]; 4545 4546 u8 reserved_at_a0[0x8]; 4547 u8 table_id[0x18]; 4548 4549 u8 ignore_flow_level[0x1]; 4550 u8 reserved_at_c1[0x17]; 4551 u8 modify_enable_mask[0x8]; 4552 4553 u8 reserved_at_e0[0x20]; 4554 4555 u8 flow_index[0x20]; 4556 4557 u8 reserved_at_120[0xe0]; 4558 4559 struct mlx5_ifc_flow_context_bits flow_context; 4560 }; 4561 4562 struct mlx5_ifc_rts2rts_qp_out_bits { 4563 u8 status[0x8]; 4564 u8 reserved_at_8[0x18]; 4565 4566 u8 syndrome[0x20]; 4567 4568 u8 reserved_at_40[0x20]; 4569 u8 ece[0x20]; 4570 }; 4571 4572 struct mlx5_ifc_rts2rts_qp_in_bits { 4573 u8 opcode[0x10]; 4574 u8 uid[0x10]; 4575 4576 u8 reserved_at_20[0x10]; 4577 u8 op_mod[0x10]; 4578 4579 u8 reserved_at_40[0x8]; 4580 u8 qpn[0x18]; 4581 4582 u8 reserved_at_60[0x20]; 4583 4584 u8 opt_param_mask[0x20]; 4585 4586 u8 ece[0x20]; 4587 4588 struct mlx5_ifc_qpc_bits qpc; 4589 4590 u8 reserved_at_800[0x80]; 4591 }; 4592 4593 struct mlx5_ifc_rtr2rts_qp_out_bits { 4594 u8 status[0x8]; 4595 u8 reserved_at_8[0x18]; 4596 4597 u8 syndrome[0x20]; 4598 4599 u8 reserved_at_40[0x20]; 4600 u8 ece[0x20]; 4601 }; 4602 4603 struct mlx5_ifc_rtr2rts_qp_in_bits { 4604 u8 opcode[0x10]; 4605 u8 uid[0x10]; 4606 4607 u8 reserved_at_20[0x10]; 4608 u8 op_mod[0x10]; 4609 4610 u8 reserved_at_40[0x8]; 4611 u8 qpn[0x18]; 4612 4613 u8 reserved_at_60[0x20]; 4614 4615 u8 opt_param_mask[0x20]; 4616 4617 u8 ece[0x20]; 4618 4619 struct mlx5_ifc_qpc_bits qpc; 4620 4621 u8 reserved_at_800[0x80]; 4622 }; 4623 4624 struct mlx5_ifc_rst2init_qp_out_bits { 4625 u8 status[0x8]; 4626 u8 reserved_at_8[0x18]; 4627 4628 u8 syndrome[0x20]; 4629 4630 u8 reserved_at_40[0x20]; 4631 u8 ece[0x20]; 4632 }; 4633 4634 struct mlx5_ifc_rst2init_qp_in_bits { 4635 u8 opcode[0x10]; 4636 u8 uid[0x10]; 4637 4638 u8 reserved_at_20[0x10]; 4639 u8 op_mod[0x10]; 4640 4641 u8 reserved_at_40[0x8]; 4642 u8 qpn[0x18]; 4643 4644 u8 reserved_at_60[0x20]; 4645 4646 u8 opt_param_mask[0x20]; 4647 4648 u8 ece[0x20]; 4649 4650 struct mlx5_ifc_qpc_bits qpc; 4651 4652 u8 reserved_at_800[0x80]; 4653 }; 4654 4655 struct mlx5_ifc_query_xrq_out_bits { 4656 u8 status[0x8]; 4657 u8 reserved_at_8[0x18]; 4658 4659 u8 syndrome[0x20]; 4660 4661 u8 reserved_at_40[0x40]; 4662 4663 struct mlx5_ifc_xrqc_bits xrq_context; 4664 }; 4665 4666 struct mlx5_ifc_query_xrq_in_bits { 4667 u8 opcode[0x10]; 4668 u8 reserved_at_10[0x10]; 4669 4670 u8 reserved_at_20[0x10]; 4671 u8 op_mod[0x10]; 4672 4673 u8 reserved_at_40[0x8]; 4674 u8 xrqn[0x18]; 4675 4676 u8 reserved_at_60[0x20]; 4677 }; 4678 4679 struct mlx5_ifc_query_xrc_srq_out_bits { 4680 u8 status[0x8]; 4681 u8 reserved_at_8[0x18]; 4682 4683 u8 syndrome[0x20]; 4684 4685 u8 reserved_at_40[0x40]; 4686 4687 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 4688 4689 u8 reserved_at_280[0x600]; 4690 4691 u8 pas[][0x40]; 4692 }; 4693 4694 struct mlx5_ifc_query_xrc_srq_in_bits { 4695 u8 opcode[0x10]; 4696 u8 reserved_at_10[0x10]; 4697 4698 u8 reserved_at_20[0x10]; 4699 u8 op_mod[0x10]; 4700 4701 u8 reserved_at_40[0x8]; 4702 u8 xrc_srqn[0x18]; 4703 4704 u8 reserved_at_60[0x20]; 4705 }; 4706 4707 enum { 4708 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0, 4709 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1, 4710 }; 4711 4712 struct mlx5_ifc_query_vport_state_out_bits { 4713 u8 status[0x8]; 4714 u8 reserved_at_8[0x18]; 4715 4716 u8 syndrome[0x20]; 4717 4718 u8 reserved_at_40[0x20]; 4719 4720 u8 reserved_at_60[0x18]; 4721 u8 admin_state[0x4]; 4722 u8 state[0x4]; 4723 }; 4724 4725 enum { 4726 MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT = 0x0, 4727 MLX5_VPORT_STATE_OP_MOD_ESW_VPORT = 0x1, 4728 MLX5_VPORT_STATE_OP_MOD_UPLINK = 0x2, 4729 }; 4730 4731 struct mlx5_ifc_arm_monitor_counter_in_bits { 4732 u8 opcode[0x10]; 4733 u8 uid[0x10]; 4734 4735 u8 reserved_at_20[0x10]; 4736 u8 op_mod[0x10]; 4737 4738 u8 reserved_at_40[0x20]; 4739 4740 u8 reserved_at_60[0x20]; 4741 }; 4742 4743 struct mlx5_ifc_arm_monitor_counter_out_bits { 4744 u8 status[0x8]; 4745 u8 reserved_at_8[0x18]; 4746 4747 u8 syndrome[0x20]; 4748 4749 u8 reserved_at_40[0x40]; 4750 }; 4751 4752 enum { 4753 MLX5_QUERY_MONITOR_CNT_TYPE_PPCNT = 0x0, 4754 MLX5_QUERY_MONITOR_CNT_TYPE_Q_COUNTER = 0x1, 4755 }; 4756 4757 enum mlx5_monitor_counter_ppcnt { 4758 MLX5_QUERY_MONITOR_PPCNT_IN_RANGE_LENGTH_ERRORS = 0x0, 4759 MLX5_QUERY_MONITOR_PPCNT_OUT_OF_RANGE_LENGTH_FIELD = 0x1, 4760 MLX5_QUERY_MONITOR_PPCNT_FRAME_TOO_LONG_ERRORS = 0x2, 4761 MLX5_QUERY_MONITOR_PPCNT_FRAME_CHECK_SEQUENCE_ERRORS = 0x3, 4762 MLX5_QUERY_MONITOR_PPCNT_ALIGNMENT_ERRORS = 0x4, 4763 MLX5_QUERY_MONITOR_PPCNT_IF_OUT_DISCARDS = 0x5, 4764 }; 4765 4766 enum { 4767 MLX5_QUERY_MONITOR_Q_COUNTER_RX_OUT_OF_BUFFER = 0x4, 4768 }; 4769 4770 struct mlx5_ifc_monitor_counter_output_bits { 4771 u8 reserved_at_0[0x4]; 4772 u8 type[0x4]; 4773 u8 reserved_at_8[0x8]; 4774 u8 counter[0x10]; 4775 4776 u8 counter_group_id[0x20]; 4777 }; 4778 4779 #define MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 (6) 4780 #define MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1 (1) 4781 #define MLX5_CMD_SET_MONITOR_NUM_COUNTER (MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 +\ 4782 MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1) 4783 4784 struct mlx5_ifc_set_monitor_counter_in_bits { 4785 u8 opcode[0x10]; 4786 u8 uid[0x10]; 4787 4788 u8 reserved_at_20[0x10]; 4789 u8 op_mod[0x10]; 4790 4791 u8 reserved_at_40[0x10]; 4792 u8 num_of_counters[0x10]; 4793 4794 u8 reserved_at_60[0x20]; 4795 4796 struct mlx5_ifc_monitor_counter_output_bits monitor_counter[MLX5_CMD_SET_MONITOR_NUM_COUNTER]; 4797 }; 4798 4799 struct mlx5_ifc_set_monitor_counter_out_bits { 4800 u8 status[0x8]; 4801 u8 reserved_at_8[0x18]; 4802 4803 u8 syndrome[0x20]; 4804 4805 u8 reserved_at_40[0x40]; 4806 }; 4807 4808 struct mlx5_ifc_query_vport_state_in_bits { 4809 u8 opcode[0x10]; 4810 u8 reserved_at_10[0x10]; 4811 4812 u8 reserved_at_20[0x10]; 4813 u8 op_mod[0x10]; 4814 4815 u8 other_vport[0x1]; 4816 u8 reserved_at_41[0xf]; 4817 u8 vport_number[0x10]; 4818 4819 u8 reserved_at_60[0x20]; 4820 }; 4821 4822 struct mlx5_ifc_query_vnic_env_out_bits { 4823 u8 status[0x8]; 4824 u8 reserved_at_8[0x18]; 4825 4826 u8 syndrome[0x20]; 4827 4828 u8 reserved_at_40[0x40]; 4829 4830 struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env; 4831 }; 4832 4833 enum { 4834 MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS = 0x0, 4835 }; 4836 4837 struct mlx5_ifc_query_vnic_env_in_bits { 4838 u8 opcode[0x10]; 4839 u8 reserved_at_10[0x10]; 4840 4841 u8 reserved_at_20[0x10]; 4842 u8 op_mod[0x10]; 4843 4844 u8 other_vport[0x1]; 4845 u8 reserved_at_41[0xf]; 4846 u8 vport_number[0x10]; 4847 4848 u8 reserved_at_60[0x20]; 4849 }; 4850 4851 struct mlx5_ifc_query_vport_counter_out_bits { 4852 u8 status[0x8]; 4853 u8 reserved_at_8[0x18]; 4854 4855 u8 syndrome[0x20]; 4856 4857 u8 reserved_at_40[0x40]; 4858 4859 struct mlx5_ifc_traffic_counter_bits received_errors; 4860 4861 struct mlx5_ifc_traffic_counter_bits transmit_errors; 4862 4863 struct mlx5_ifc_traffic_counter_bits received_ib_unicast; 4864 4865 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast; 4866 4867 struct mlx5_ifc_traffic_counter_bits received_ib_multicast; 4868 4869 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast; 4870 4871 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast; 4872 4873 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast; 4874 4875 struct mlx5_ifc_traffic_counter_bits received_eth_unicast; 4876 4877 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast; 4878 4879 struct mlx5_ifc_traffic_counter_bits received_eth_multicast; 4880 4881 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast; 4882 4883 u8 reserved_at_680[0xa00]; 4884 }; 4885 4886 enum { 4887 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0, 4888 }; 4889 4890 struct mlx5_ifc_query_vport_counter_in_bits { 4891 u8 opcode[0x10]; 4892 u8 reserved_at_10[0x10]; 4893 4894 u8 reserved_at_20[0x10]; 4895 u8 op_mod[0x10]; 4896 4897 u8 other_vport[0x1]; 4898 u8 reserved_at_41[0xb]; 4899 u8 port_num[0x4]; 4900 u8 vport_number[0x10]; 4901 4902 u8 reserved_at_60[0x60]; 4903 4904 u8 clear[0x1]; 4905 u8 reserved_at_c1[0x1f]; 4906 4907 u8 reserved_at_e0[0x20]; 4908 }; 4909 4910 struct mlx5_ifc_query_tis_out_bits { 4911 u8 status[0x8]; 4912 u8 reserved_at_8[0x18]; 4913 4914 u8 syndrome[0x20]; 4915 4916 u8 reserved_at_40[0x40]; 4917 4918 struct mlx5_ifc_tisc_bits tis_context; 4919 }; 4920 4921 struct mlx5_ifc_query_tis_in_bits { 4922 u8 opcode[0x10]; 4923 u8 reserved_at_10[0x10]; 4924 4925 u8 reserved_at_20[0x10]; 4926 u8 op_mod[0x10]; 4927 4928 u8 reserved_at_40[0x8]; 4929 u8 tisn[0x18]; 4930 4931 u8 reserved_at_60[0x20]; 4932 }; 4933 4934 struct mlx5_ifc_query_tir_out_bits { 4935 u8 status[0x8]; 4936 u8 reserved_at_8[0x18]; 4937 4938 u8 syndrome[0x20]; 4939 4940 u8 reserved_at_40[0xc0]; 4941 4942 struct mlx5_ifc_tirc_bits tir_context; 4943 }; 4944 4945 struct mlx5_ifc_query_tir_in_bits { 4946 u8 opcode[0x10]; 4947 u8 reserved_at_10[0x10]; 4948 4949 u8 reserved_at_20[0x10]; 4950 u8 op_mod[0x10]; 4951 4952 u8 reserved_at_40[0x8]; 4953 u8 tirn[0x18]; 4954 4955 u8 reserved_at_60[0x20]; 4956 }; 4957 4958 struct mlx5_ifc_query_srq_out_bits { 4959 u8 status[0x8]; 4960 u8 reserved_at_8[0x18]; 4961 4962 u8 syndrome[0x20]; 4963 4964 u8 reserved_at_40[0x40]; 4965 4966 struct mlx5_ifc_srqc_bits srq_context_entry; 4967 4968 u8 reserved_at_280[0x600]; 4969 4970 u8 pas[][0x40]; 4971 }; 4972 4973 struct mlx5_ifc_query_srq_in_bits { 4974 u8 opcode[0x10]; 4975 u8 reserved_at_10[0x10]; 4976 4977 u8 reserved_at_20[0x10]; 4978 u8 op_mod[0x10]; 4979 4980 u8 reserved_at_40[0x8]; 4981 u8 srqn[0x18]; 4982 4983 u8 reserved_at_60[0x20]; 4984 }; 4985 4986 struct mlx5_ifc_query_sq_out_bits { 4987 u8 status[0x8]; 4988 u8 reserved_at_8[0x18]; 4989 4990 u8 syndrome[0x20]; 4991 4992 u8 reserved_at_40[0xc0]; 4993 4994 struct mlx5_ifc_sqc_bits sq_context; 4995 }; 4996 4997 struct mlx5_ifc_query_sq_in_bits { 4998 u8 opcode[0x10]; 4999 u8 reserved_at_10[0x10]; 5000 5001 u8 reserved_at_20[0x10]; 5002 u8 op_mod[0x10]; 5003 5004 u8 reserved_at_40[0x8]; 5005 u8 sqn[0x18]; 5006 5007 u8 reserved_at_60[0x20]; 5008 }; 5009 5010 struct mlx5_ifc_query_special_contexts_out_bits { 5011 u8 status[0x8]; 5012 u8 reserved_at_8[0x18]; 5013 5014 u8 syndrome[0x20]; 5015 5016 u8 dump_fill_mkey[0x20]; 5017 5018 u8 resd_lkey[0x20]; 5019 5020 u8 null_mkey[0x20]; 5021 5022 u8 reserved_at_a0[0x60]; 5023 }; 5024 5025 struct mlx5_ifc_query_special_contexts_in_bits { 5026 u8 opcode[0x10]; 5027 u8 reserved_at_10[0x10]; 5028 5029 u8 reserved_at_20[0x10]; 5030 u8 op_mod[0x10]; 5031 5032 u8 reserved_at_40[0x40]; 5033 }; 5034 5035 struct mlx5_ifc_query_scheduling_element_out_bits { 5036 u8 opcode[0x10]; 5037 u8 reserved_at_10[0x10]; 5038 5039 u8 reserved_at_20[0x10]; 5040 u8 op_mod[0x10]; 5041 5042 u8 reserved_at_40[0xc0]; 5043 5044 struct mlx5_ifc_scheduling_context_bits scheduling_context; 5045 5046 u8 reserved_at_300[0x100]; 5047 }; 5048 5049 enum { 5050 SCHEDULING_HIERARCHY_E_SWITCH = 0x2, 5051 SCHEDULING_HIERARCHY_NIC = 0x3, 5052 }; 5053 5054 struct mlx5_ifc_query_scheduling_element_in_bits { 5055 u8 opcode[0x10]; 5056 u8 reserved_at_10[0x10]; 5057 5058 u8 reserved_at_20[0x10]; 5059 u8 op_mod[0x10]; 5060 5061 u8 scheduling_hierarchy[0x8]; 5062 u8 reserved_at_48[0x18]; 5063 5064 u8 scheduling_element_id[0x20]; 5065 5066 u8 reserved_at_80[0x180]; 5067 }; 5068 5069 struct mlx5_ifc_query_rqt_out_bits { 5070 u8 status[0x8]; 5071 u8 reserved_at_8[0x18]; 5072 5073 u8 syndrome[0x20]; 5074 5075 u8 reserved_at_40[0xc0]; 5076 5077 struct mlx5_ifc_rqtc_bits rqt_context; 5078 }; 5079 5080 struct mlx5_ifc_query_rqt_in_bits { 5081 u8 opcode[0x10]; 5082 u8 reserved_at_10[0x10]; 5083 5084 u8 reserved_at_20[0x10]; 5085 u8 op_mod[0x10]; 5086 5087 u8 reserved_at_40[0x8]; 5088 u8 rqtn[0x18]; 5089 5090 u8 reserved_at_60[0x20]; 5091 }; 5092 5093 struct mlx5_ifc_query_rq_out_bits { 5094 u8 status[0x8]; 5095 u8 reserved_at_8[0x18]; 5096 5097 u8 syndrome[0x20]; 5098 5099 u8 reserved_at_40[0xc0]; 5100 5101 struct mlx5_ifc_rqc_bits rq_context; 5102 }; 5103 5104 struct mlx5_ifc_query_rq_in_bits { 5105 u8 opcode[0x10]; 5106 u8 reserved_at_10[0x10]; 5107 5108 u8 reserved_at_20[0x10]; 5109 u8 op_mod[0x10]; 5110 5111 u8 reserved_at_40[0x8]; 5112 u8 rqn[0x18]; 5113 5114 u8 reserved_at_60[0x20]; 5115 }; 5116 5117 struct mlx5_ifc_query_roce_address_out_bits { 5118 u8 status[0x8]; 5119 u8 reserved_at_8[0x18]; 5120 5121 u8 syndrome[0x20]; 5122 5123 u8 reserved_at_40[0x40]; 5124 5125 struct mlx5_ifc_roce_addr_layout_bits roce_address; 5126 }; 5127 5128 struct mlx5_ifc_query_roce_address_in_bits { 5129 u8 opcode[0x10]; 5130 u8 reserved_at_10[0x10]; 5131 5132 u8 reserved_at_20[0x10]; 5133 u8 op_mod[0x10]; 5134 5135 u8 roce_address_index[0x10]; 5136 u8 reserved_at_50[0xc]; 5137 u8 vhca_port_num[0x4]; 5138 5139 u8 reserved_at_60[0x20]; 5140 }; 5141 5142 struct mlx5_ifc_query_rmp_out_bits { 5143 u8 status[0x8]; 5144 u8 reserved_at_8[0x18]; 5145 5146 u8 syndrome[0x20]; 5147 5148 u8 reserved_at_40[0xc0]; 5149 5150 struct mlx5_ifc_rmpc_bits rmp_context; 5151 }; 5152 5153 struct mlx5_ifc_query_rmp_in_bits { 5154 u8 opcode[0x10]; 5155 u8 reserved_at_10[0x10]; 5156 5157 u8 reserved_at_20[0x10]; 5158 u8 op_mod[0x10]; 5159 5160 u8 reserved_at_40[0x8]; 5161 u8 rmpn[0x18]; 5162 5163 u8 reserved_at_60[0x20]; 5164 }; 5165 5166 struct mlx5_ifc_query_qp_out_bits { 5167 u8 status[0x8]; 5168 u8 reserved_at_8[0x18]; 5169 5170 u8 syndrome[0x20]; 5171 5172 u8 reserved_at_40[0x20]; 5173 u8 ece[0x20]; 5174 5175 u8 opt_param_mask[0x20]; 5176 5177 u8 reserved_at_a0[0x20]; 5178 5179 struct mlx5_ifc_qpc_bits qpc; 5180 5181 u8 reserved_at_800[0x80]; 5182 5183 u8 pas[][0x40]; 5184 }; 5185 5186 struct mlx5_ifc_query_qp_in_bits { 5187 u8 opcode[0x10]; 5188 u8 reserved_at_10[0x10]; 5189 5190 u8 reserved_at_20[0x10]; 5191 u8 op_mod[0x10]; 5192 5193 u8 reserved_at_40[0x8]; 5194 u8 qpn[0x18]; 5195 5196 u8 reserved_at_60[0x20]; 5197 }; 5198 5199 struct mlx5_ifc_query_q_counter_out_bits { 5200 u8 status[0x8]; 5201 u8 reserved_at_8[0x18]; 5202 5203 u8 syndrome[0x20]; 5204 5205 u8 reserved_at_40[0x40]; 5206 5207 u8 rx_write_requests[0x20]; 5208 5209 u8 reserved_at_a0[0x20]; 5210 5211 u8 rx_read_requests[0x20]; 5212 5213 u8 reserved_at_e0[0x20]; 5214 5215 u8 rx_atomic_requests[0x20]; 5216 5217 u8 reserved_at_120[0x20]; 5218 5219 u8 rx_dct_connect[0x20]; 5220 5221 u8 reserved_at_160[0x20]; 5222 5223 u8 out_of_buffer[0x20]; 5224 5225 u8 reserved_at_1a0[0x20]; 5226 5227 u8 out_of_sequence[0x20]; 5228 5229 u8 reserved_at_1e0[0x20]; 5230 5231 u8 duplicate_request[0x20]; 5232 5233 u8 reserved_at_220[0x20]; 5234 5235 u8 rnr_nak_retry_err[0x20]; 5236 5237 u8 reserved_at_260[0x20]; 5238 5239 u8 packet_seq_err[0x20]; 5240 5241 u8 reserved_at_2a0[0x20]; 5242 5243 u8 implied_nak_seq_err[0x20]; 5244 5245 u8 reserved_at_2e0[0x20]; 5246 5247 u8 local_ack_timeout_err[0x20]; 5248 5249 u8 reserved_at_320[0xa0]; 5250 5251 u8 resp_local_length_error[0x20]; 5252 5253 u8 req_local_length_error[0x20]; 5254 5255 u8 resp_local_qp_error[0x20]; 5256 5257 u8 local_operation_error[0x20]; 5258 5259 u8 resp_local_protection[0x20]; 5260 5261 u8 req_local_protection[0x20]; 5262 5263 u8 resp_cqe_error[0x20]; 5264 5265 u8 req_cqe_error[0x20]; 5266 5267 u8 req_mw_binding[0x20]; 5268 5269 u8 req_bad_response[0x20]; 5270 5271 u8 req_remote_invalid_request[0x20]; 5272 5273 u8 resp_remote_invalid_request[0x20]; 5274 5275 u8 req_remote_access_errors[0x20]; 5276 5277 u8 resp_remote_access_errors[0x20]; 5278 5279 u8 req_remote_operation_errors[0x20]; 5280 5281 u8 req_transport_retries_exceeded[0x20]; 5282 5283 u8 cq_overflow[0x20]; 5284 5285 u8 resp_cqe_flush_error[0x20]; 5286 5287 u8 req_cqe_flush_error[0x20]; 5288 5289 u8 reserved_at_620[0x20]; 5290 5291 u8 roce_adp_retrans[0x20]; 5292 5293 u8 roce_adp_retrans_to[0x20]; 5294 5295 u8 roce_slow_restart[0x20]; 5296 5297 u8 roce_slow_restart_cnps[0x20]; 5298 5299 u8 roce_slow_restart_trans[0x20]; 5300 5301 u8 reserved_at_6e0[0x120]; 5302 }; 5303 5304 struct mlx5_ifc_query_q_counter_in_bits { 5305 u8 opcode[0x10]; 5306 u8 reserved_at_10[0x10]; 5307 5308 u8 reserved_at_20[0x10]; 5309 u8 op_mod[0x10]; 5310 5311 u8 reserved_at_40[0x80]; 5312 5313 u8 clear[0x1]; 5314 u8 reserved_at_c1[0x1f]; 5315 5316 u8 reserved_at_e0[0x18]; 5317 u8 counter_set_id[0x8]; 5318 }; 5319 5320 struct mlx5_ifc_query_pages_out_bits { 5321 u8 status[0x8]; 5322 u8 reserved_at_8[0x18]; 5323 5324 u8 syndrome[0x20]; 5325 5326 u8 embedded_cpu_function[0x1]; 5327 u8 reserved_at_41[0xf]; 5328 u8 function_id[0x10]; 5329 5330 u8 num_pages[0x20]; 5331 }; 5332 5333 enum { 5334 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1, 5335 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2, 5336 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3, 5337 }; 5338 5339 struct mlx5_ifc_query_pages_in_bits { 5340 u8 opcode[0x10]; 5341 u8 reserved_at_10[0x10]; 5342 5343 u8 reserved_at_20[0x10]; 5344 u8 op_mod[0x10]; 5345 5346 u8 embedded_cpu_function[0x1]; 5347 u8 reserved_at_41[0xf]; 5348 u8 function_id[0x10]; 5349 5350 u8 reserved_at_60[0x20]; 5351 }; 5352 5353 struct mlx5_ifc_query_nic_vport_context_out_bits { 5354 u8 status[0x8]; 5355 u8 reserved_at_8[0x18]; 5356 5357 u8 syndrome[0x20]; 5358 5359 u8 reserved_at_40[0x40]; 5360 5361 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 5362 }; 5363 5364 struct mlx5_ifc_query_nic_vport_context_in_bits { 5365 u8 opcode[0x10]; 5366 u8 reserved_at_10[0x10]; 5367 5368 u8 reserved_at_20[0x10]; 5369 u8 op_mod[0x10]; 5370 5371 u8 other_vport[0x1]; 5372 u8 reserved_at_41[0xf]; 5373 u8 vport_number[0x10]; 5374 5375 u8 reserved_at_60[0x5]; 5376 u8 allowed_list_type[0x3]; 5377 u8 reserved_at_68[0x18]; 5378 }; 5379 5380 struct mlx5_ifc_query_mkey_out_bits { 5381 u8 status[0x8]; 5382 u8 reserved_at_8[0x18]; 5383 5384 u8 syndrome[0x20]; 5385 5386 u8 reserved_at_40[0x40]; 5387 5388 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 5389 5390 u8 reserved_at_280[0x600]; 5391 5392 u8 bsf0_klm0_pas_mtt0_1[16][0x8]; 5393 5394 u8 bsf1_klm1_pas_mtt2_3[16][0x8]; 5395 }; 5396 5397 struct mlx5_ifc_query_mkey_in_bits { 5398 u8 opcode[0x10]; 5399 u8 reserved_at_10[0x10]; 5400 5401 u8 reserved_at_20[0x10]; 5402 u8 op_mod[0x10]; 5403 5404 u8 reserved_at_40[0x8]; 5405 u8 mkey_index[0x18]; 5406 5407 u8 pg_access[0x1]; 5408 u8 reserved_at_61[0x1f]; 5409 }; 5410 5411 struct mlx5_ifc_query_mad_demux_out_bits { 5412 u8 status[0x8]; 5413 u8 reserved_at_8[0x18]; 5414 5415 u8 syndrome[0x20]; 5416 5417 u8 reserved_at_40[0x40]; 5418 5419 u8 mad_dumux_parameters_block[0x20]; 5420 }; 5421 5422 struct mlx5_ifc_query_mad_demux_in_bits { 5423 u8 opcode[0x10]; 5424 u8 reserved_at_10[0x10]; 5425 5426 u8 reserved_at_20[0x10]; 5427 u8 op_mod[0x10]; 5428 5429 u8 reserved_at_40[0x40]; 5430 }; 5431 5432 struct mlx5_ifc_query_l2_table_entry_out_bits { 5433 u8 status[0x8]; 5434 u8 reserved_at_8[0x18]; 5435 5436 u8 syndrome[0x20]; 5437 5438 u8 reserved_at_40[0xa0]; 5439 5440 u8 reserved_at_e0[0x13]; 5441 u8 vlan_valid[0x1]; 5442 u8 vlan[0xc]; 5443 5444 struct mlx5_ifc_mac_address_layout_bits mac_address; 5445 5446 u8 reserved_at_140[0xc0]; 5447 }; 5448 5449 struct mlx5_ifc_query_l2_table_entry_in_bits { 5450 u8 opcode[0x10]; 5451 u8 reserved_at_10[0x10]; 5452 5453 u8 reserved_at_20[0x10]; 5454 u8 op_mod[0x10]; 5455 5456 u8 reserved_at_40[0x60]; 5457 5458 u8 reserved_at_a0[0x8]; 5459 u8 table_index[0x18]; 5460 5461 u8 reserved_at_c0[0x140]; 5462 }; 5463 5464 struct mlx5_ifc_query_issi_out_bits { 5465 u8 status[0x8]; 5466 u8 reserved_at_8[0x18]; 5467 5468 u8 syndrome[0x20]; 5469 5470 u8 reserved_at_40[0x10]; 5471 u8 current_issi[0x10]; 5472 5473 u8 reserved_at_60[0xa0]; 5474 5475 u8 reserved_at_100[76][0x8]; 5476 u8 supported_issi_dw0[0x20]; 5477 }; 5478 5479 struct mlx5_ifc_query_issi_in_bits { 5480 u8 opcode[0x10]; 5481 u8 reserved_at_10[0x10]; 5482 5483 u8 reserved_at_20[0x10]; 5484 u8 op_mod[0x10]; 5485 5486 u8 reserved_at_40[0x40]; 5487 }; 5488 5489 struct mlx5_ifc_set_driver_version_out_bits { 5490 u8 status[0x8]; 5491 u8 reserved_0[0x18]; 5492 5493 u8 syndrome[0x20]; 5494 u8 reserved_1[0x40]; 5495 }; 5496 5497 struct mlx5_ifc_set_driver_version_in_bits { 5498 u8 opcode[0x10]; 5499 u8 reserved_0[0x10]; 5500 5501 u8 reserved_1[0x10]; 5502 u8 op_mod[0x10]; 5503 5504 u8 reserved_2[0x40]; 5505 u8 driver_version[64][0x8]; 5506 }; 5507 5508 struct mlx5_ifc_query_hca_vport_pkey_out_bits { 5509 u8 status[0x8]; 5510 u8 reserved_at_8[0x18]; 5511 5512 u8 syndrome[0x20]; 5513 5514 u8 reserved_at_40[0x40]; 5515 5516 struct mlx5_ifc_pkey_bits pkey[]; 5517 }; 5518 5519 struct mlx5_ifc_query_hca_vport_pkey_in_bits { 5520 u8 opcode[0x10]; 5521 u8 reserved_at_10[0x10]; 5522 5523 u8 reserved_at_20[0x10]; 5524 u8 op_mod[0x10]; 5525 5526 u8 other_vport[0x1]; 5527 u8 reserved_at_41[0xb]; 5528 u8 port_num[0x4]; 5529 u8 vport_number[0x10]; 5530 5531 u8 reserved_at_60[0x10]; 5532 u8 pkey_index[0x10]; 5533 }; 5534 5535 enum { 5536 MLX5_HCA_VPORT_SEL_PORT_GUID = 1 << 0, 5537 MLX5_HCA_VPORT_SEL_NODE_GUID = 1 << 1, 5538 MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2, 5539 }; 5540 5541 struct mlx5_ifc_query_hca_vport_gid_out_bits { 5542 u8 status[0x8]; 5543 u8 reserved_at_8[0x18]; 5544 5545 u8 syndrome[0x20]; 5546 5547 u8 reserved_at_40[0x20]; 5548 5549 u8 gids_num[0x10]; 5550 u8 reserved_at_70[0x10]; 5551 5552 struct mlx5_ifc_array128_auto_bits gid[]; 5553 }; 5554 5555 struct mlx5_ifc_query_hca_vport_gid_in_bits { 5556 u8 opcode[0x10]; 5557 u8 reserved_at_10[0x10]; 5558 5559 u8 reserved_at_20[0x10]; 5560 u8 op_mod[0x10]; 5561 5562 u8 other_vport[0x1]; 5563 u8 reserved_at_41[0xb]; 5564 u8 port_num[0x4]; 5565 u8 vport_number[0x10]; 5566 5567 u8 reserved_at_60[0x10]; 5568 u8 gid_index[0x10]; 5569 }; 5570 5571 struct mlx5_ifc_query_hca_vport_context_out_bits { 5572 u8 status[0x8]; 5573 u8 reserved_at_8[0x18]; 5574 5575 u8 syndrome[0x20]; 5576 5577 u8 reserved_at_40[0x40]; 5578 5579 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 5580 }; 5581 5582 struct mlx5_ifc_query_hca_vport_context_in_bits { 5583 u8 opcode[0x10]; 5584 u8 reserved_at_10[0x10]; 5585 5586 u8 reserved_at_20[0x10]; 5587 u8 op_mod[0x10]; 5588 5589 u8 other_vport[0x1]; 5590 u8 reserved_at_41[0xb]; 5591 u8 port_num[0x4]; 5592 u8 vport_number[0x10]; 5593 5594 u8 reserved_at_60[0x20]; 5595 }; 5596 5597 struct mlx5_ifc_query_hca_cap_out_bits { 5598 u8 status[0x8]; 5599 u8 reserved_at_8[0x18]; 5600 5601 u8 syndrome[0x20]; 5602 5603 u8 reserved_at_40[0x40]; 5604 5605 union mlx5_ifc_hca_cap_union_bits capability; 5606 }; 5607 5608 struct mlx5_ifc_query_hca_cap_in_bits { 5609 u8 opcode[0x10]; 5610 u8 reserved_at_10[0x10]; 5611 5612 u8 reserved_at_20[0x10]; 5613 u8 op_mod[0x10]; 5614 5615 u8 other_function[0x1]; 5616 u8 reserved_at_41[0xf]; 5617 u8 function_id[0x10]; 5618 5619 u8 reserved_at_60[0x20]; 5620 }; 5621 5622 struct mlx5_ifc_other_hca_cap_bits { 5623 u8 roce[0x1]; 5624 u8 reserved_at_1[0x27f]; 5625 }; 5626 5627 struct mlx5_ifc_query_other_hca_cap_out_bits { 5628 u8 status[0x8]; 5629 u8 reserved_at_8[0x18]; 5630 5631 u8 syndrome[0x20]; 5632 5633 u8 reserved_at_40[0x40]; 5634 5635 struct mlx5_ifc_other_hca_cap_bits other_capability; 5636 }; 5637 5638 struct mlx5_ifc_query_other_hca_cap_in_bits { 5639 u8 opcode[0x10]; 5640 u8 reserved_at_10[0x10]; 5641 5642 u8 reserved_at_20[0x10]; 5643 u8 op_mod[0x10]; 5644 5645 u8 reserved_at_40[0x10]; 5646 u8 function_id[0x10]; 5647 5648 u8 reserved_at_60[0x20]; 5649 }; 5650 5651 struct mlx5_ifc_modify_other_hca_cap_out_bits { 5652 u8 status[0x8]; 5653 u8 reserved_at_8[0x18]; 5654 5655 u8 syndrome[0x20]; 5656 5657 u8 reserved_at_40[0x40]; 5658 }; 5659 5660 struct mlx5_ifc_modify_other_hca_cap_in_bits { 5661 u8 opcode[0x10]; 5662 u8 reserved_at_10[0x10]; 5663 5664 u8 reserved_at_20[0x10]; 5665 u8 op_mod[0x10]; 5666 5667 u8 reserved_at_40[0x10]; 5668 u8 function_id[0x10]; 5669 u8 field_select[0x20]; 5670 5671 struct mlx5_ifc_other_hca_cap_bits other_capability; 5672 }; 5673 5674 struct mlx5_ifc_flow_table_context_bits { 5675 u8 reformat_en[0x1]; 5676 u8 decap_en[0x1]; 5677 u8 sw_owner[0x1]; 5678 u8 termination_table[0x1]; 5679 u8 table_miss_action[0x4]; 5680 u8 level[0x8]; 5681 u8 reserved_at_10[0x8]; 5682 u8 log_size[0x8]; 5683 5684 u8 reserved_at_20[0x8]; 5685 u8 table_miss_id[0x18]; 5686 5687 u8 reserved_at_40[0x8]; 5688 u8 lag_master_next_table_id[0x18]; 5689 5690 u8 reserved_at_60[0x60]; 5691 5692 u8 sw_owner_icm_root_1[0x40]; 5693 5694 u8 sw_owner_icm_root_0[0x40]; 5695 5696 }; 5697 5698 struct mlx5_ifc_query_flow_table_out_bits { 5699 u8 status[0x8]; 5700 u8 reserved_at_8[0x18]; 5701 5702 u8 syndrome[0x20]; 5703 5704 u8 reserved_at_40[0x80]; 5705 5706 struct mlx5_ifc_flow_table_context_bits flow_table_context; 5707 }; 5708 5709 struct mlx5_ifc_query_flow_table_in_bits { 5710 u8 opcode[0x10]; 5711 u8 reserved_at_10[0x10]; 5712 5713 u8 reserved_at_20[0x10]; 5714 u8 op_mod[0x10]; 5715 5716 u8 reserved_at_40[0x40]; 5717 5718 u8 table_type[0x8]; 5719 u8 reserved_at_88[0x18]; 5720 5721 u8 reserved_at_a0[0x8]; 5722 u8 table_id[0x18]; 5723 5724 u8 reserved_at_c0[0x140]; 5725 }; 5726 5727 struct mlx5_ifc_query_fte_out_bits { 5728 u8 status[0x8]; 5729 u8 reserved_at_8[0x18]; 5730 5731 u8 syndrome[0x20]; 5732 5733 u8 reserved_at_40[0x1c0]; 5734 5735 struct mlx5_ifc_flow_context_bits flow_context; 5736 }; 5737 5738 struct mlx5_ifc_query_fte_in_bits { 5739 u8 opcode[0x10]; 5740 u8 reserved_at_10[0x10]; 5741 5742 u8 reserved_at_20[0x10]; 5743 u8 op_mod[0x10]; 5744 5745 u8 reserved_at_40[0x40]; 5746 5747 u8 table_type[0x8]; 5748 u8 reserved_at_88[0x18]; 5749 5750 u8 reserved_at_a0[0x8]; 5751 u8 table_id[0x18]; 5752 5753 u8 reserved_at_c0[0x40]; 5754 5755 u8 flow_index[0x20]; 5756 5757 u8 reserved_at_120[0xe0]; 5758 }; 5759 5760 struct mlx5_ifc_match_definer_format_0_bits { 5761 u8 reserved_at_0[0x100]; 5762 5763 u8 metadata_reg_c_0[0x20]; 5764 5765 u8 metadata_reg_c_1[0x20]; 5766 5767 u8 outer_dmac_47_16[0x20]; 5768 5769 u8 outer_dmac_15_0[0x10]; 5770 u8 outer_ethertype[0x10]; 5771 5772 u8 reserved_at_180[0x1]; 5773 u8 sx_sniffer[0x1]; 5774 u8 functional_lb[0x1]; 5775 u8 outer_ip_frag[0x1]; 5776 u8 outer_qp_type[0x2]; 5777 u8 outer_encap_type[0x2]; 5778 u8 port_number[0x2]; 5779 u8 outer_l3_type[0x2]; 5780 u8 outer_l4_type[0x2]; 5781 u8 outer_first_vlan_type[0x2]; 5782 u8 outer_first_vlan_prio[0x3]; 5783 u8 outer_first_vlan_cfi[0x1]; 5784 u8 outer_first_vlan_vid[0xc]; 5785 5786 u8 outer_l4_type_ext[0x4]; 5787 u8 reserved_at_1a4[0x2]; 5788 u8 outer_ipsec_layer[0x2]; 5789 u8 outer_l2_type[0x2]; 5790 u8 force_lb[0x1]; 5791 u8 outer_l2_ok[0x1]; 5792 u8 outer_l3_ok[0x1]; 5793 u8 outer_l4_ok[0x1]; 5794 u8 outer_second_vlan_type[0x2]; 5795 u8 outer_second_vlan_prio[0x3]; 5796 u8 outer_second_vlan_cfi[0x1]; 5797 u8 outer_second_vlan_vid[0xc]; 5798 5799 u8 outer_smac_47_16[0x20]; 5800 5801 u8 outer_smac_15_0[0x10]; 5802 u8 inner_ipv4_checksum_ok[0x1]; 5803 u8 inner_l4_checksum_ok[0x1]; 5804 u8 outer_ipv4_checksum_ok[0x1]; 5805 u8 outer_l4_checksum_ok[0x1]; 5806 u8 inner_l3_ok[0x1]; 5807 u8 inner_l4_ok[0x1]; 5808 u8 outer_l3_ok_duplicate[0x1]; 5809 u8 outer_l4_ok_duplicate[0x1]; 5810 u8 outer_tcp_cwr[0x1]; 5811 u8 outer_tcp_ece[0x1]; 5812 u8 outer_tcp_urg[0x1]; 5813 u8 outer_tcp_ack[0x1]; 5814 u8 outer_tcp_psh[0x1]; 5815 u8 outer_tcp_rst[0x1]; 5816 u8 outer_tcp_syn[0x1]; 5817 u8 outer_tcp_fin[0x1]; 5818 }; 5819 5820 struct mlx5_ifc_match_definer_format_22_bits { 5821 u8 reserved_at_0[0x100]; 5822 5823 u8 outer_ip_src_addr[0x20]; 5824 5825 u8 outer_ip_dest_addr[0x20]; 5826 5827 u8 outer_l4_sport[0x10]; 5828 u8 outer_l4_dport[0x10]; 5829 5830 u8 reserved_at_160[0x1]; 5831 u8 sx_sniffer[0x1]; 5832 u8 functional_lb[0x1]; 5833 u8 outer_ip_frag[0x1]; 5834 u8 outer_qp_type[0x2]; 5835 u8 outer_encap_type[0x2]; 5836 u8 port_number[0x2]; 5837 u8 outer_l3_type[0x2]; 5838 u8 outer_l4_type[0x2]; 5839 u8 outer_first_vlan_type[0x2]; 5840 u8 outer_first_vlan_prio[0x3]; 5841 u8 outer_first_vlan_cfi[0x1]; 5842 u8 outer_first_vlan_vid[0xc]; 5843 5844 u8 metadata_reg_c_0[0x20]; 5845 5846 u8 outer_dmac_47_16[0x20]; 5847 5848 u8 outer_smac_47_16[0x20]; 5849 5850 u8 outer_smac_15_0[0x10]; 5851 u8 outer_dmac_15_0[0x10]; 5852 }; 5853 5854 struct mlx5_ifc_match_definer_format_23_bits { 5855 u8 reserved_at_0[0x100]; 5856 5857 u8 inner_ip_src_addr[0x20]; 5858 5859 u8 inner_ip_dest_addr[0x20]; 5860 5861 u8 inner_l4_sport[0x10]; 5862 u8 inner_l4_dport[0x10]; 5863 5864 u8 reserved_at_160[0x1]; 5865 u8 sx_sniffer[0x1]; 5866 u8 functional_lb[0x1]; 5867 u8 inner_ip_frag[0x1]; 5868 u8 inner_qp_type[0x2]; 5869 u8 inner_encap_type[0x2]; 5870 u8 port_number[0x2]; 5871 u8 inner_l3_type[0x2]; 5872 u8 inner_l4_type[0x2]; 5873 u8 inner_first_vlan_type[0x2]; 5874 u8 inner_first_vlan_prio[0x3]; 5875 u8 inner_first_vlan_cfi[0x1]; 5876 u8 inner_first_vlan_vid[0xc]; 5877 5878 u8 tunnel_header_0[0x20]; 5879 5880 u8 inner_dmac_47_16[0x20]; 5881 5882 u8 inner_smac_47_16[0x20]; 5883 5884 u8 inner_smac_15_0[0x10]; 5885 u8 inner_dmac_15_0[0x10]; 5886 }; 5887 5888 struct mlx5_ifc_match_definer_format_29_bits { 5889 u8 reserved_at_0[0xc0]; 5890 5891 u8 outer_ip_dest_addr[0x80]; 5892 5893 u8 outer_ip_src_addr[0x80]; 5894 5895 u8 outer_l4_sport[0x10]; 5896 u8 outer_l4_dport[0x10]; 5897 5898 u8 reserved_at_1e0[0x20]; 5899 }; 5900 5901 struct mlx5_ifc_match_definer_format_30_bits { 5902 u8 reserved_at_0[0xa0]; 5903 5904 u8 outer_ip_dest_addr[0x80]; 5905 5906 u8 outer_ip_src_addr[0x80]; 5907 5908 u8 outer_dmac_47_16[0x20]; 5909 5910 u8 outer_smac_47_16[0x20]; 5911 5912 u8 outer_smac_15_0[0x10]; 5913 u8 outer_dmac_15_0[0x10]; 5914 }; 5915 5916 struct mlx5_ifc_match_definer_format_31_bits { 5917 u8 reserved_at_0[0xc0]; 5918 5919 u8 inner_ip_dest_addr[0x80]; 5920 5921 u8 inner_ip_src_addr[0x80]; 5922 5923 u8 inner_l4_sport[0x10]; 5924 u8 inner_l4_dport[0x10]; 5925 5926 u8 reserved_at_1e0[0x20]; 5927 }; 5928 5929 struct mlx5_ifc_match_definer_format_32_bits { 5930 u8 reserved_at_0[0xa0]; 5931 5932 u8 inner_ip_dest_addr[0x80]; 5933 5934 u8 inner_ip_src_addr[0x80]; 5935 5936 u8 inner_dmac_47_16[0x20]; 5937 5938 u8 inner_smac_47_16[0x20]; 5939 5940 u8 inner_smac_15_0[0x10]; 5941 u8 inner_dmac_15_0[0x10]; 5942 }; 5943 5944 struct mlx5_ifc_match_definer_bits { 5945 u8 modify_field_select[0x40]; 5946 5947 u8 reserved_at_40[0x40]; 5948 5949 u8 reserved_at_80[0x10]; 5950 u8 format_id[0x10]; 5951 5952 u8 reserved_at_a0[0x160]; 5953 5954 u8 match_mask[16][0x20]; 5955 }; 5956 5957 struct mlx5_ifc_general_obj_in_cmd_hdr_bits { 5958 u8 opcode[0x10]; 5959 u8 uid[0x10]; 5960 5961 u8 vhca_tunnel_id[0x10]; 5962 u8 obj_type[0x10]; 5963 5964 u8 obj_id[0x20]; 5965 5966 u8 reserved_at_60[0x20]; 5967 }; 5968 5969 struct mlx5_ifc_general_obj_out_cmd_hdr_bits { 5970 u8 status[0x8]; 5971 u8 reserved_at_8[0x18]; 5972 5973 u8 syndrome[0x20]; 5974 5975 u8 obj_id[0x20]; 5976 5977 u8 reserved_at_60[0x20]; 5978 }; 5979 5980 struct mlx5_ifc_create_match_definer_in_bits { 5981 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 5982 5983 struct mlx5_ifc_match_definer_bits obj_context; 5984 }; 5985 5986 struct mlx5_ifc_create_match_definer_out_bits { 5987 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 5988 }; 5989 5990 enum { 5991 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 5992 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 5993 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 5994 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3, 5995 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_3 = 0x4, 5996 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_4 = 0x5, 5997 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_5 = 0x6, 5998 }; 5999 6000 struct mlx5_ifc_query_flow_group_out_bits { 6001 u8 status[0x8]; 6002 u8 reserved_at_8[0x18]; 6003 6004 u8 syndrome[0x20]; 6005 6006 u8 reserved_at_40[0xa0]; 6007 6008 u8 start_flow_index[0x20]; 6009 6010 u8 reserved_at_100[0x20]; 6011 6012 u8 end_flow_index[0x20]; 6013 6014 u8 reserved_at_140[0xa0]; 6015 6016 u8 reserved_at_1e0[0x18]; 6017 u8 match_criteria_enable[0x8]; 6018 6019 struct mlx5_ifc_fte_match_param_bits match_criteria; 6020 6021 u8 reserved_at_1200[0xe00]; 6022 }; 6023 6024 struct mlx5_ifc_query_flow_group_in_bits { 6025 u8 opcode[0x10]; 6026 u8 reserved_at_10[0x10]; 6027 6028 u8 reserved_at_20[0x10]; 6029 u8 op_mod[0x10]; 6030 6031 u8 reserved_at_40[0x40]; 6032 6033 u8 table_type[0x8]; 6034 u8 reserved_at_88[0x18]; 6035 6036 u8 reserved_at_a0[0x8]; 6037 u8 table_id[0x18]; 6038 6039 u8 group_id[0x20]; 6040 6041 u8 reserved_at_e0[0x120]; 6042 }; 6043 6044 struct mlx5_ifc_query_flow_counter_out_bits { 6045 u8 status[0x8]; 6046 u8 reserved_at_8[0x18]; 6047 6048 u8 syndrome[0x20]; 6049 6050 u8 reserved_at_40[0x40]; 6051 6052 struct mlx5_ifc_traffic_counter_bits flow_statistics[]; 6053 }; 6054 6055 struct mlx5_ifc_query_flow_counter_in_bits { 6056 u8 opcode[0x10]; 6057 u8 reserved_at_10[0x10]; 6058 6059 u8 reserved_at_20[0x10]; 6060 u8 op_mod[0x10]; 6061 6062 u8 reserved_at_40[0x80]; 6063 6064 u8 clear[0x1]; 6065 u8 reserved_at_c1[0xf]; 6066 u8 num_of_counters[0x10]; 6067 6068 u8 flow_counter_id[0x20]; 6069 }; 6070 6071 struct mlx5_ifc_query_esw_vport_context_out_bits { 6072 u8 status[0x8]; 6073 u8 reserved_at_8[0x18]; 6074 6075 u8 syndrome[0x20]; 6076 6077 u8 reserved_at_40[0x40]; 6078 6079 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 6080 }; 6081 6082 struct mlx5_ifc_query_esw_vport_context_in_bits { 6083 u8 opcode[0x10]; 6084 u8 reserved_at_10[0x10]; 6085 6086 u8 reserved_at_20[0x10]; 6087 u8 op_mod[0x10]; 6088 6089 u8 other_vport[0x1]; 6090 u8 reserved_at_41[0xf]; 6091 u8 vport_number[0x10]; 6092 6093 u8 reserved_at_60[0x20]; 6094 }; 6095 6096 struct mlx5_ifc_modify_esw_vport_context_out_bits { 6097 u8 status[0x8]; 6098 u8 reserved_at_8[0x18]; 6099 6100 u8 syndrome[0x20]; 6101 6102 u8 reserved_at_40[0x40]; 6103 }; 6104 6105 struct mlx5_ifc_esw_vport_context_fields_select_bits { 6106 u8 reserved_at_0[0x1b]; 6107 u8 fdb_to_vport_reg_c_id[0x1]; 6108 u8 vport_cvlan_insert[0x1]; 6109 u8 vport_svlan_insert[0x1]; 6110 u8 vport_cvlan_strip[0x1]; 6111 u8 vport_svlan_strip[0x1]; 6112 }; 6113 6114 struct mlx5_ifc_modify_esw_vport_context_in_bits { 6115 u8 opcode[0x10]; 6116 u8 reserved_at_10[0x10]; 6117 6118 u8 reserved_at_20[0x10]; 6119 u8 op_mod[0x10]; 6120 6121 u8 other_vport[0x1]; 6122 u8 reserved_at_41[0xf]; 6123 u8 vport_number[0x10]; 6124 6125 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select; 6126 6127 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 6128 }; 6129 6130 struct mlx5_ifc_query_eq_out_bits { 6131 u8 status[0x8]; 6132 u8 reserved_at_8[0x18]; 6133 6134 u8 syndrome[0x20]; 6135 6136 u8 reserved_at_40[0x40]; 6137 6138 struct mlx5_ifc_eqc_bits eq_context_entry; 6139 6140 u8 reserved_at_280[0x40]; 6141 6142 u8 event_bitmask[0x40]; 6143 6144 u8 reserved_at_300[0x580]; 6145 6146 u8 pas[][0x40]; 6147 }; 6148 6149 struct mlx5_ifc_query_eq_in_bits { 6150 u8 opcode[0x10]; 6151 u8 reserved_at_10[0x10]; 6152 6153 u8 reserved_at_20[0x10]; 6154 u8 op_mod[0x10]; 6155 6156 u8 reserved_at_40[0x18]; 6157 u8 eq_number[0x8]; 6158 6159 u8 reserved_at_60[0x20]; 6160 }; 6161 6162 struct mlx5_ifc_packet_reformat_context_in_bits { 6163 u8 reformat_type[0x8]; 6164 u8 reserved_at_8[0x4]; 6165 u8 reformat_param_0[0x4]; 6166 u8 reserved_at_10[0x6]; 6167 u8 reformat_data_size[0xa]; 6168 6169 u8 reformat_param_1[0x8]; 6170 u8 reserved_at_28[0x8]; 6171 u8 reformat_data[2][0x8]; 6172 6173 u8 more_reformat_data[][0x8]; 6174 }; 6175 6176 struct mlx5_ifc_query_packet_reformat_context_out_bits { 6177 u8 status[0x8]; 6178 u8 reserved_at_8[0x18]; 6179 6180 u8 syndrome[0x20]; 6181 6182 u8 reserved_at_40[0xa0]; 6183 6184 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context[]; 6185 }; 6186 6187 struct mlx5_ifc_query_packet_reformat_context_in_bits { 6188 u8 opcode[0x10]; 6189 u8 reserved_at_10[0x10]; 6190 6191 u8 reserved_at_20[0x10]; 6192 u8 op_mod[0x10]; 6193 6194 u8 packet_reformat_id[0x20]; 6195 6196 u8 reserved_at_60[0xa0]; 6197 }; 6198 6199 struct mlx5_ifc_alloc_packet_reformat_context_out_bits { 6200 u8 status[0x8]; 6201 u8 reserved_at_8[0x18]; 6202 6203 u8 syndrome[0x20]; 6204 6205 u8 packet_reformat_id[0x20]; 6206 6207 u8 reserved_at_60[0x20]; 6208 }; 6209 6210 enum { 6211 MLX5_REFORMAT_CONTEXT_ANCHOR_MAC_START = 0x1, 6212 MLX5_REFORMAT_CONTEXT_ANCHOR_IP_START = 0x7, 6213 MLX5_REFORMAT_CONTEXT_ANCHOR_TCP_UDP_START = 0x9, 6214 }; 6215 6216 enum mlx5_reformat_ctx_type { 6217 MLX5_REFORMAT_TYPE_L2_TO_VXLAN = 0x0, 6218 MLX5_REFORMAT_TYPE_L2_TO_NVGRE = 0x1, 6219 MLX5_REFORMAT_TYPE_L2_TO_L2_TUNNEL = 0x2, 6220 MLX5_REFORMAT_TYPE_L3_TUNNEL_TO_L2 = 0x3, 6221 MLX5_REFORMAT_TYPE_L2_TO_L3_TUNNEL = 0x4, 6222 MLX5_REFORMAT_TYPE_INSERT_HDR = 0xf, 6223 MLX5_REFORMAT_TYPE_REMOVE_HDR = 0x10, 6224 }; 6225 6226 struct mlx5_ifc_alloc_packet_reformat_context_in_bits { 6227 u8 opcode[0x10]; 6228 u8 reserved_at_10[0x10]; 6229 6230 u8 reserved_at_20[0x10]; 6231 u8 op_mod[0x10]; 6232 6233 u8 reserved_at_40[0xa0]; 6234 6235 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context; 6236 }; 6237 6238 struct mlx5_ifc_dealloc_packet_reformat_context_out_bits { 6239 u8 status[0x8]; 6240 u8 reserved_at_8[0x18]; 6241 6242 u8 syndrome[0x20]; 6243 6244 u8 reserved_at_40[0x40]; 6245 }; 6246 6247 struct mlx5_ifc_dealloc_packet_reformat_context_in_bits { 6248 u8 opcode[0x10]; 6249 u8 reserved_at_10[0x10]; 6250 6251 u8 reserved_20[0x10]; 6252 u8 op_mod[0x10]; 6253 6254 u8 packet_reformat_id[0x20]; 6255 6256 u8 reserved_60[0x20]; 6257 }; 6258 6259 struct mlx5_ifc_set_action_in_bits { 6260 u8 action_type[0x4]; 6261 u8 field[0xc]; 6262 u8 reserved_at_10[0x3]; 6263 u8 offset[0x5]; 6264 u8 reserved_at_18[0x3]; 6265 u8 length[0x5]; 6266 6267 u8 data[0x20]; 6268 }; 6269 6270 struct mlx5_ifc_add_action_in_bits { 6271 u8 action_type[0x4]; 6272 u8 field[0xc]; 6273 u8 reserved_at_10[0x10]; 6274 6275 u8 data[0x20]; 6276 }; 6277 6278 struct mlx5_ifc_copy_action_in_bits { 6279 u8 action_type[0x4]; 6280 u8 src_field[0xc]; 6281 u8 reserved_at_10[0x3]; 6282 u8 src_offset[0x5]; 6283 u8 reserved_at_18[0x3]; 6284 u8 length[0x5]; 6285 6286 u8 reserved_at_20[0x4]; 6287 u8 dst_field[0xc]; 6288 u8 reserved_at_30[0x3]; 6289 u8 dst_offset[0x5]; 6290 u8 reserved_at_38[0x8]; 6291 }; 6292 6293 union mlx5_ifc_set_add_copy_action_in_auto_bits { 6294 struct mlx5_ifc_set_action_in_bits set_action_in; 6295 struct mlx5_ifc_add_action_in_bits add_action_in; 6296 struct mlx5_ifc_copy_action_in_bits copy_action_in; 6297 u8 reserved_at_0[0x40]; 6298 }; 6299 6300 enum { 6301 MLX5_ACTION_TYPE_SET = 0x1, 6302 MLX5_ACTION_TYPE_ADD = 0x2, 6303 MLX5_ACTION_TYPE_COPY = 0x3, 6304 }; 6305 6306 enum { 6307 MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16 = 0x1, 6308 MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0 = 0x2, 6309 MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE = 0x3, 6310 MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16 = 0x4, 6311 MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0 = 0x5, 6312 MLX5_ACTION_IN_FIELD_OUT_IP_DSCP = 0x6, 6313 MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS = 0x7, 6314 MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT = 0x8, 6315 MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT = 0x9, 6316 MLX5_ACTION_IN_FIELD_OUT_IP_TTL = 0xa, 6317 MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT = 0xb, 6318 MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT = 0xc, 6319 MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96 = 0xd, 6320 MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64 = 0xe, 6321 MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32 = 0xf, 6322 MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0 = 0x10, 6323 MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96 = 0x11, 6324 MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64 = 0x12, 6325 MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32 = 0x13, 6326 MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0 = 0x14, 6327 MLX5_ACTION_IN_FIELD_OUT_SIPV4 = 0x15, 6328 MLX5_ACTION_IN_FIELD_OUT_DIPV4 = 0x16, 6329 MLX5_ACTION_IN_FIELD_OUT_FIRST_VID = 0x17, 6330 MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47, 6331 MLX5_ACTION_IN_FIELD_METADATA_REG_A = 0x49, 6332 MLX5_ACTION_IN_FIELD_METADATA_REG_B = 0x50, 6333 MLX5_ACTION_IN_FIELD_METADATA_REG_C_0 = 0x51, 6334 MLX5_ACTION_IN_FIELD_METADATA_REG_C_1 = 0x52, 6335 MLX5_ACTION_IN_FIELD_METADATA_REG_C_2 = 0x53, 6336 MLX5_ACTION_IN_FIELD_METADATA_REG_C_3 = 0x54, 6337 MLX5_ACTION_IN_FIELD_METADATA_REG_C_4 = 0x55, 6338 MLX5_ACTION_IN_FIELD_METADATA_REG_C_5 = 0x56, 6339 MLX5_ACTION_IN_FIELD_METADATA_REG_C_6 = 0x57, 6340 MLX5_ACTION_IN_FIELD_METADATA_REG_C_7 = 0x58, 6341 MLX5_ACTION_IN_FIELD_OUT_TCP_SEQ_NUM = 0x59, 6342 MLX5_ACTION_IN_FIELD_OUT_TCP_ACK_NUM = 0x5B, 6343 MLX5_ACTION_IN_FIELD_IPSEC_SYNDROME = 0x5D, 6344 MLX5_ACTION_IN_FIELD_OUT_EMD_47_32 = 0x6F, 6345 MLX5_ACTION_IN_FIELD_OUT_EMD_31_0 = 0x70, 6346 }; 6347 6348 struct mlx5_ifc_alloc_modify_header_context_out_bits { 6349 u8 status[0x8]; 6350 u8 reserved_at_8[0x18]; 6351 6352 u8 syndrome[0x20]; 6353 6354 u8 modify_header_id[0x20]; 6355 6356 u8 reserved_at_60[0x20]; 6357 }; 6358 6359 struct mlx5_ifc_alloc_modify_header_context_in_bits { 6360 u8 opcode[0x10]; 6361 u8 reserved_at_10[0x10]; 6362 6363 u8 reserved_at_20[0x10]; 6364 u8 op_mod[0x10]; 6365 6366 u8 reserved_at_40[0x20]; 6367 6368 u8 table_type[0x8]; 6369 u8 reserved_at_68[0x10]; 6370 u8 num_of_actions[0x8]; 6371 6372 union mlx5_ifc_set_add_copy_action_in_auto_bits actions[]; 6373 }; 6374 6375 struct mlx5_ifc_dealloc_modify_header_context_out_bits { 6376 u8 status[0x8]; 6377 u8 reserved_at_8[0x18]; 6378 6379 u8 syndrome[0x20]; 6380 6381 u8 reserved_at_40[0x40]; 6382 }; 6383 6384 struct mlx5_ifc_dealloc_modify_header_context_in_bits { 6385 u8 opcode[0x10]; 6386 u8 reserved_at_10[0x10]; 6387 6388 u8 reserved_at_20[0x10]; 6389 u8 op_mod[0x10]; 6390 6391 u8 modify_header_id[0x20]; 6392 6393 u8 reserved_at_60[0x20]; 6394 }; 6395 6396 struct mlx5_ifc_query_modify_header_context_in_bits { 6397 u8 opcode[0x10]; 6398 u8 uid[0x10]; 6399 6400 u8 reserved_at_20[0x10]; 6401 u8 op_mod[0x10]; 6402 6403 u8 modify_header_id[0x20]; 6404 6405 u8 reserved_at_60[0xa0]; 6406 }; 6407 6408 struct mlx5_ifc_query_dct_out_bits { 6409 u8 status[0x8]; 6410 u8 reserved_at_8[0x18]; 6411 6412 u8 syndrome[0x20]; 6413 6414 u8 reserved_at_40[0x40]; 6415 6416 struct mlx5_ifc_dctc_bits dct_context_entry; 6417 6418 u8 reserved_at_280[0x180]; 6419 }; 6420 6421 struct mlx5_ifc_query_dct_in_bits { 6422 u8 opcode[0x10]; 6423 u8 reserved_at_10[0x10]; 6424 6425 u8 reserved_at_20[0x10]; 6426 u8 op_mod[0x10]; 6427 6428 u8 reserved_at_40[0x8]; 6429 u8 dctn[0x18]; 6430 6431 u8 reserved_at_60[0x20]; 6432 }; 6433 6434 struct mlx5_ifc_query_cq_out_bits { 6435 u8 status[0x8]; 6436 u8 reserved_at_8[0x18]; 6437 6438 u8 syndrome[0x20]; 6439 6440 u8 reserved_at_40[0x40]; 6441 6442 struct mlx5_ifc_cqc_bits cq_context; 6443 6444 u8 reserved_at_280[0x600]; 6445 6446 u8 pas[][0x40]; 6447 }; 6448 6449 struct mlx5_ifc_query_cq_in_bits { 6450 u8 opcode[0x10]; 6451 u8 reserved_at_10[0x10]; 6452 6453 u8 reserved_at_20[0x10]; 6454 u8 op_mod[0x10]; 6455 6456 u8 reserved_at_40[0x8]; 6457 u8 cqn[0x18]; 6458 6459 u8 reserved_at_60[0x20]; 6460 }; 6461 6462 struct mlx5_ifc_query_cong_status_out_bits { 6463 u8 status[0x8]; 6464 u8 reserved_at_8[0x18]; 6465 6466 u8 syndrome[0x20]; 6467 6468 u8 reserved_at_40[0x20]; 6469 6470 u8 enable[0x1]; 6471 u8 tag_enable[0x1]; 6472 u8 reserved_at_62[0x1e]; 6473 }; 6474 6475 struct mlx5_ifc_query_cong_status_in_bits { 6476 u8 opcode[0x10]; 6477 u8 reserved_at_10[0x10]; 6478 6479 u8 reserved_at_20[0x10]; 6480 u8 op_mod[0x10]; 6481 6482 u8 reserved_at_40[0x18]; 6483 u8 priority[0x4]; 6484 u8 cong_protocol[0x4]; 6485 6486 u8 reserved_at_60[0x20]; 6487 }; 6488 6489 struct mlx5_ifc_query_cong_statistics_out_bits { 6490 u8 status[0x8]; 6491 u8 reserved_at_8[0x18]; 6492 6493 u8 syndrome[0x20]; 6494 6495 u8 reserved_at_40[0x40]; 6496 6497 u8 rp_cur_flows[0x20]; 6498 6499 u8 sum_flows[0x20]; 6500 6501 u8 rp_cnp_ignored_high[0x20]; 6502 6503 u8 rp_cnp_ignored_low[0x20]; 6504 6505 u8 rp_cnp_handled_high[0x20]; 6506 6507 u8 rp_cnp_handled_low[0x20]; 6508 6509 u8 reserved_at_140[0x100]; 6510 6511 u8 time_stamp_high[0x20]; 6512 6513 u8 time_stamp_low[0x20]; 6514 6515 u8 accumulators_period[0x20]; 6516 6517 u8 np_ecn_marked_roce_packets_high[0x20]; 6518 6519 u8 np_ecn_marked_roce_packets_low[0x20]; 6520 6521 u8 np_cnp_sent_high[0x20]; 6522 6523 u8 np_cnp_sent_low[0x20]; 6524 6525 u8 reserved_at_320[0x560]; 6526 }; 6527 6528 struct mlx5_ifc_query_cong_statistics_in_bits { 6529 u8 opcode[0x10]; 6530 u8 reserved_at_10[0x10]; 6531 6532 u8 reserved_at_20[0x10]; 6533 u8 op_mod[0x10]; 6534 6535 u8 clear[0x1]; 6536 u8 reserved_at_41[0x1f]; 6537 6538 u8 reserved_at_60[0x20]; 6539 }; 6540 6541 struct mlx5_ifc_query_cong_params_out_bits { 6542 u8 status[0x8]; 6543 u8 reserved_at_8[0x18]; 6544 6545 u8 syndrome[0x20]; 6546 6547 u8 reserved_at_40[0x40]; 6548 6549 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 6550 }; 6551 6552 struct mlx5_ifc_query_cong_params_in_bits { 6553 u8 opcode[0x10]; 6554 u8 reserved_at_10[0x10]; 6555 6556 u8 reserved_at_20[0x10]; 6557 u8 op_mod[0x10]; 6558 6559 u8 reserved_at_40[0x1c]; 6560 u8 cong_protocol[0x4]; 6561 6562 u8 reserved_at_60[0x20]; 6563 }; 6564 6565 struct mlx5_ifc_query_adapter_out_bits { 6566 u8 status[0x8]; 6567 u8 reserved_at_8[0x18]; 6568 6569 u8 syndrome[0x20]; 6570 6571 u8 reserved_at_40[0x40]; 6572 6573 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct; 6574 }; 6575 6576 struct mlx5_ifc_query_adapter_in_bits { 6577 u8 opcode[0x10]; 6578 u8 reserved_at_10[0x10]; 6579 6580 u8 reserved_at_20[0x10]; 6581 u8 op_mod[0x10]; 6582 6583 u8 reserved_at_40[0x40]; 6584 }; 6585 6586 struct mlx5_ifc_qp_2rst_out_bits { 6587 u8 status[0x8]; 6588 u8 reserved_at_8[0x18]; 6589 6590 u8 syndrome[0x20]; 6591 6592 u8 reserved_at_40[0x40]; 6593 }; 6594 6595 struct mlx5_ifc_qp_2rst_in_bits { 6596 u8 opcode[0x10]; 6597 u8 uid[0x10]; 6598 6599 u8 reserved_at_20[0x10]; 6600 u8 op_mod[0x10]; 6601 6602 u8 reserved_at_40[0x8]; 6603 u8 qpn[0x18]; 6604 6605 u8 reserved_at_60[0x20]; 6606 }; 6607 6608 struct mlx5_ifc_qp_2err_out_bits { 6609 u8 status[0x8]; 6610 u8 reserved_at_8[0x18]; 6611 6612 u8 syndrome[0x20]; 6613 6614 u8 reserved_at_40[0x40]; 6615 }; 6616 6617 struct mlx5_ifc_qp_2err_in_bits { 6618 u8 opcode[0x10]; 6619 u8 uid[0x10]; 6620 6621 u8 reserved_at_20[0x10]; 6622 u8 op_mod[0x10]; 6623 6624 u8 reserved_at_40[0x8]; 6625 u8 qpn[0x18]; 6626 6627 u8 reserved_at_60[0x20]; 6628 }; 6629 6630 struct mlx5_ifc_page_fault_resume_out_bits { 6631 u8 status[0x8]; 6632 u8 reserved_at_8[0x18]; 6633 6634 u8 syndrome[0x20]; 6635 6636 u8 reserved_at_40[0x40]; 6637 }; 6638 6639 struct mlx5_ifc_page_fault_resume_in_bits { 6640 u8 opcode[0x10]; 6641 u8 reserved_at_10[0x10]; 6642 6643 u8 reserved_at_20[0x10]; 6644 u8 op_mod[0x10]; 6645 6646 u8 error[0x1]; 6647 u8 reserved_at_41[0x4]; 6648 u8 page_fault_type[0x3]; 6649 u8 wq_number[0x18]; 6650 6651 u8 reserved_at_60[0x8]; 6652 u8 token[0x18]; 6653 }; 6654 6655 struct mlx5_ifc_nop_out_bits { 6656 u8 status[0x8]; 6657 u8 reserved_at_8[0x18]; 6658 6659 u8 syndrome[0x20]; 6660 6661 u8 reserved_at_40[0x40]; 6662 }; 6663 6664 struct mlx5_ifc_nop_in_bits { 6665 u8 opcode[0x10]; 6666 u8 reserved_at_10[0x10]; 6667 6668 u8 reserved_at_20[0x10]; 6669 u8 op_mod[0x10]; 6670 6671 u8 reserved_at_40[0x40]; 6672 }; 6673 6674 struct mlx5_ifc_modify_vport_state_out_bits { 6675 u8 status[0x8]; 6676 u8 reserved_at_8[0x18]; 6677 6678 u8 syndrome[0x20]; 6679 6680 u8 reserved_at_40[0x40]; 6681 }; 6682 6683 struct mlx5_ifc_modify_vport_state_in_bits { 6684 u8 opcode[0x10]; 6685 u8 reserved_at_10[0x10]; 6686 6687 u8 reserved_at_20[0x10]; 6688 u8 op_mod[0x10]; 6689 6690 u8 other_vport[0x1]; 6691 u8 reserved_at_41[0xf]; 6692 u8 vport_number[0x10]; 6693 6694 u8 reserved_at_60[0x18]; 6695 u8 admin_state[0x4]; 6696 u8 reserved_at_7c[0x4]; 6697 }; 6698 6699 struct mlx5_ifc_modify_tis_out_bits { 6700 u8 status[0x8]; 6701 u8 reserved_at_8[0x18]; 6702 6703 u8 syndrome[0x20]; 6704 6705 u8 reserved_at_40[0x40]; 6706 }; 6707 6708 struct mlx5_ifc_modify_tis_bitmask_bits { 6709 u8 reserved_at_0[0x20]; 6710 6711 u8 reserved_at_20[0x1d]; 6712 u8 lag_tx_port_affinity[0x1]; 6713 u8 strict_lag_tx_port_affinity[0x1]; 6714 u8 prio[0x1]; 6715 }; 6716 6717 struct mlx5_ifc_modify_tis_in_bits { 6718 u8 opcode[0x10]; 6719 u8 uid[0x10]; 6720 6721 u8 reserved_at_20[0x10]; 6722 u8 op_mod[0x10]; 6723 6724 u8 reserved_at_40[0x8]; 6725 u8 tisn[0x18]; 6726 6727 u8 reserved_at_60[0x20]; 6728 6729 struct mlx5_ifc_modify_tis_bitmask_bits bitmask; 6730 6731 u8 reserved_at_c0[0x40]; 6732 6733 struct mlx5_ifc_tisc_bits ctx; 6734 }; 6735 6736 struct mlx5_ifc_modify_tir_bitmask_bits { 6737 u8 reserved_at_0[0x20]; 6738 6739 u8 reserved_at_20[0x1b]; 6740 u8 self_lb_en[0x1]; 6741 u8 reserved_at_3c[0x1]; 6742 u8 hash[0x1]; 6743 u8 reserved_at_3e[0x1]; 6744 u8 packet_merge[0x1]; 6745 }; 6746 6747 struct mlx5_ifc_modify_tir_out_bits { 6748 u8 status[0x8]; 6749 u8 reserved_at_8[0x18]; 6750 6751 u8 syndrome[0x20]; 6752 6753 u8 reserved_at_40[0x40]; 6754 }; 6755 6756 struct mlx5_ifc_modify_tir_in_bits { 6757 u8 opcode[0x10]; 6758 u8 uid[0x10]; 6759 6760 u8 reserved_at_20[0x10]; 6761 u8 op_mod[0x10]; 6762 6763 u8 reserved_at_40[0x8]; 6764 u8 tirn[0x18]; 6765 6766 u8 reserved_at_60[0x20]; 6767 6768 struct mlx5_ifc_modify_tir_bitmask_bits bitmask; 6769 6770 u8 reserved_at_c0[0x40]; 6771 6772 struct mlx5_ifc_tirc_bits ctx; 6773 }; 6774 6775 struct mlx5_ifc_modify_sq_out_bits { 6776 u8 status[0x8]; 6777 u8 reserved_at_8[0x18]; 6778 6779 u8 syndrome[0x20]; 6780 6781 u8 reserved_at_40[0x40]; 6782 }; 6783 6784 struct mlx5_ifc_modify_sq_in_bits { 6785 u8 opcode[0x10]; 6786 u8 uid[0x10]; 6787 6788 u8 reserved_at_20[0x10]; 6789 u8 op_mod[0x10]; 6790 6791 u8 sq_state[0x4]; 6792 u8 reserved_at_44[0x4]; 6793 u8 sqn[0x18]; 6794 6795 u8 reserved_at_60[0x20]; 6796 6797 u8 modify_bitmask[0x40]; 6798 6799 u8 reserved_at_c0[0x40]; 6800 6801 struct mlx5_ifc_sqc_bits ctx; 6802 }; 6803 6804 struct mlx5_ifc_modify_scheduling_element_out_bits { 6805 u8 status[0x8]; 6806 u8 reserved_at_8[0x18]; 6807 6808 u8 syndrome[0x20]; 6809 6810 u8 reserved_at_40[0x1c0]; 6811 }; 6812 6813 enum { 6814 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1, 6815 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2, 6816 }; 6817 6818 struct mlx5_ifc_modify_scheduling_element_in_bits { 6819 u8 opcode[0x10]; 6820 u8 reserved_at_10[0x10]; 6821 6822 u8 reserved_at_20[0x10]; 6823 u8 op_mod[0x10]; 6824 6825 u8 scheduling_hierarchy[0x8]; 6826 u8 reserved_at_48[0x18]; 6827 6828 u8 scheduling_element_id[0x20]; 6829 6830 u8 reserved_at_80[0x20]; 6831 6832 u8 modify_bitmask[0x20]; 6833 6834 u8 reserved_at_c0[0x40]; 6835 6836 struct mlx5_ifc_scheduling_context_bits scheduling_context; 6837 6838 u8 reserved_at_300[0x100]; 6839 }; 6840 6841 struct mlx5_ifc_modify_rqt_out_bits { 6842 u8 status[0x8]; 6843 u8 reserved_at_8[0x18]; 6844 6845 u8 syndrome[0x20]; 6846 6847 u8 reserved_at_40[0x40]; 6848 }; 6849 6850 struct mlx5_ifc_rqt_bitmask_bits { 6851 u8 reserved_at_0[0x20]; 6852 6853 u8 reserved_at_20[0x1f]; 6854 u8 rqn_list[0x1]; 6855 }; 6856 6857 struct mlx5_ifc_modify_rqt_in_bits { 6858 u8 opcode[0x10]; 6859 u8 uid[0x10]; 6860 6861 u8 reserved_at_20[0x10]; 6862 u8 op_mod[0x10]; 6863 6864 u8 reserved_at_40[0x8]; 6865 u8 rqtn[0x18]; 6866 6867 u8 reserved_at_60[0x20]; 6868 6869 struct mlx5_ifc_rqt_bitmask_bits bitmask; 6870 6871 u8 reserved_at_c0[0x40]; 6872 6873 struct mlx5_ifc_rqtc_bits ctx; 6874 }; 6875 6876 struct mlx5_ifc_modify_rq_out_bits { 6877 u8 status[0x8]; 6878 u8 reserved_at_8[0x18]; 6879 6880 u8 syndrome[0x20]; 6881 6882 u8 reserved_at_40[0x40]; 6883 }; 6884 6885 enum { 6886 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1, 6887 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2, 6888 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3, 6889 }; 6890 6891 struct mlx5_ifc_modify_rq_in_bits { 6892 u8 opcode[0x10]; 6893 u8 uid[0x10]; 6894 6895 u8 reserved_at_20[0x10]; 6896 u8 op_mod[0x10]; 6897 6898 u8 rq_state[0x4]; 6899 u8 reserved_at_44[0x4]; 6900 u8 rqn[0x18]; 6901 6902 u8 reserved_at_60[0x20]; 6903 6904 u8 modify_bitmask[0x40]; 6905 6906 u8 reserved_at_c0[0x40]; 6907 6908 struct mlx5_ifc_rqc_bits ctx; 6909 }; 6910 6911 struct mlx5_ifc_modify_rmp_out_bits { 6912 u8 status[0x8]; 6913 u8 reserved_at_8[0x18]; 6914 6915 u8 syndrome[0x20]; 6916 6917 u8 reserved_at_40[0x40]; 6918 }; 6919 6920 struct mlx5_ifc_rmp_bitmask_bits { 6921 u8 reserved_at_0[0x20]; 6922 6923 u8 reserved_at_20[0x1f]; 6924 u8 lwm[0x1]; 6925 }; 6926 6927 struct mlx5_ifc_modify_rmp_in_bits { 6928 u8 opcode[0x10]; 6929 u8 uid[0x10]; 6930 6931 u8 reserved_at_20[0x10]; 6932 u8 op_mod[0x10]; 6933 6934 u8 rmp_state[0x4]; 6935 u8 reserved_at_44[0x4]; 6936 u8 rmpn[0x18]; 6937 6938 u8 reserved_at_60[0x20]; 6939 6940 struct mlx5_ifc_rmp_bitmask_bits bitmask; 6941 6942 u8 reserved_at_c0[0x40]; 6943 6944 struct mlx5_ifc_rmpc_bits ctx; 6945 }; 6946 6947 struct mlx5_ifc_modify_nic_vport_context_out_bits { 6948 u8 status[0x8]; 6949 u8 reserved_at_8[0x18]; 6950 6951 u8 syndrome[0x20]; 6952 6953 u8 reserved_at_40[0x40]; 6954 }; 6955 6956 struct mlx5_ifc_modify_nic_vport_field_select_bits { 6957 u8 reserved_at_0[0x12]; 6958 u8 affiliation[0x1]; 6959 u8 reserved_at_13[0x1]; 6960 u8 disable_uc_local_lb[0x1]; 6961 u8 disable_mc_local_lb[0x1]; 6962 u8 node_guid[0x1]; 6963 u8 port_guid[0x1]; 6964 u8 min_inline[0x1]; 6965 u8 mtu[0x1]; 6966 u8 change_event[0x1]; 6967 u8 promisc[0x1]; 6968 u8 permanent_address[0x1]; 6969 u8 addresses_list[0x1]; 6970 u8 roce_en[0x1]; 6971 u8 reserved_at_1f[0x1]; 6972 }; 6973 6974 struct mlx5_ifc_modify_nic_vport_context_in_bits { 6975 u8 opcode[0x10]; 6976 u8 reserved_at_10[0x10]; 6977 6978 u8 reserved_at_20[0x10]; 6979 u8 op_mod[0x10]; 6980 6981 u8 other_vport[0x1]; 6982 u8 reserved_at_41[0xf]; 6983 u8 vport_number[0x10]; 6984 6985 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select; 6986 6987 u8 reserved_at_80[0x780]; 6988 6989 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 6990 }; 6991 6992 struct mlx5_ifc_modify_hca_vport_context_out_bits { 6993 u8 status[0x8]; 6994 u8 reserved_at_8[0x18]; 6995 6996 u8 syndrome[0x20]; 6997 6998 u8 reserved_at_40[0x40]; 6999 }; 7000 7001 struct mlx5_ifc_modify_hca_vport_context_in_bits { 7002 u8 opcode[0x10]; 7003 u8 reserved_at_10[0x10]; 7004 7005 u8 reserved_at_20[0x10]; 7006 u8 op_mod[0x10]; 7007 7008 u8 other_vport[0x1]; 7009 u8 reserved_at_41[0xb]; 7010 u8 port_num[0x4]; 7011 u8 vport_number[0x10]; 7012 7013 u8 reserved_at_60[0x20]; 7014 7015 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 7016 }; 7017 7018 struct mlx5_ifc_modify_cq_out_bits { 7019 u8 status[0x8]; 7020 u8 reserved_at_8[0x18]; 7021 7022 u8 syndrome[0x20]; 7023 7024 u8 reserved_at_40[0x40]; 7025 }; 7026 7027 enum { 7028 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0, 7029 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1, 7030 }; 7031 7032 struct mlx5_ifc_modify_cq_in_bits { 7033 u8 opcode[0x10]; 7034 u8 uid[0x10]; 7035 7036 u8 reserved_at_20[0x10]; 7037 u8 op_mod[0x10]; 7038 7039 u8 reserved_at_40[0x8]; 7040 u8 cqn[0x18]; 7041 7042 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select; 7043 7044 struct mlx5_ifc_cqc_bits cq_context; 7045 7046 u8 reserved_at_280[0x60]; 7047 7048 u8 cq_umem_valid[0x1]; 7049 u8 reserved_at_2e1[0x1f]; 7050 7051 u8 reserved_at_300[0x580]; 7052 7053 u8 pas[][0x40]; 7054 }; 7055 7056 struct mlx5_ifc_modify_cong_status_out_bits { 7057 u8 status[0x8]; 7058 u8 reserved_at_8[0x18]; 7059 7060 u8 syndrome[0x20]; 7061 7062 u8 reserved_at_40[0x40]; 7063 }; 7064 7065 struct mlx5_ifc_modify_cong_status_in_bits { 7066 u8 opcode[0x10]; 7067 u8 reserved_at_10[0x10]; 7068 7069 u8 reserved_at_20[0x10]; 7070 u8 op_mod[0x10]; 7071 7072 u8 reserved_at_40[0x18]; 7073 u8 priority[0x4]; 7074 u8 cong_protocol[0x4]; 7075 7076 u8 enable[0x1]; 7077 u8 tag_enable[0x1]; 7078 u8 reserved_at_62[0x1e]; 7079 }; 7080 7081 struct mlx5_ifc_modify_cong_params_out_bits { 7082 u8 status[0x8]; 7083 u8 reserved_at_8[0x18]; 7084 7085 u8 syndrome[0x20]; 7086 7087 u8 reserved_at_40[0x40]; 7088 }; 7089 7090 struct mlx5_ifc_modify_cong_params_in_bits { 7091 u8 opcode[0x10]; 7092 u8 reserved_at_10[0x10]; 7093 7094 u8 reserved_at_20[0x10]; 7095 u8 op_mod[0x10]; 7096 7097 u8 reserved_at_40[0x1c]; 7098 u8 cong_protocol[0x4]; 7099 7100 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select; 7101 7102 u8 reserved_at_80[0x80]; 7103 7104 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 7105 }; 7106 7107 struct mlx5_ifc_manage_pages_out_bits { 7108 u8 status[0x8]; 7109 u8 reserved_at_8[0x18]; 7110 7111 u8 syndrome[0x20]; 7112 7113 u8 output_num_entries[0x20]; 7114 7115 u8 reserved_at_60[0x20]; 7116 7117 u8 pas[][0x40]; 7118 }; 7119 7120 enum { 7121 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL = 0x0, 7122 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS = 0x1, 7123 MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES = 0x2, 7124 }; 7125 7126 struct mlx5_ifc_manage_pages_in_bits { 7127 u8 opcode[0x10]; 7128 u8 reserved_at_10[0x10]; 7129 7130 u8 reserved_at_20[0x10]; 7131 u8 op_mod[0x10]; 7132 7133 u8 embedded_cpu_function[0x1]; 7134 u8 reserved_at_41[0xf]; 7135 u8 function_id[0x10]; 7136 7137 u8 input_num_entries[0x20]; 7138 7139 u8 pas[][0x40]; 7140 }; 7141 7142 struct mlx5_ifc_mad_ifc_out_bits { 7143 u8 status[0x8]; 7144 u8 reserved_at_8[0x18]; 7145 7146 u8 syndrome[0x20]; 7147 7148 u8 reserved_at_40[0x40]; 7149 7150 u8 response_mad_packet[256][0x8]; 7151 }; 7152 7153 struct mlx5_ifc_mad_ifc_in_bits { 7154 u8 opcode[0x10]; 7155 u8 reserved_at_10[0x10]; 7156 7157 u8 reserved_at_20[0x10]; 7158 u8 op_mod[0x10]; 7159 7160 u8 remote_lid[0x10]; 7161 u8 reserved_at_50[0x8]; 7162 u8 port[0x8]; 7163 7164 u8 reserved_at_60[0x20]; 7165 7166 u8 mad[256][0x8]; 7167 }; 7168 7169 struct mlx5_ifc_init_hca_out_bits { 7170 u8 status[0x8]; 7171 u8 reserved_at_8[0x18]; 7172 7173 u8 syndrome[0x20]; 7174 7175 u8 reserved_at_40[0x40]; 7176 }; 7177 7178 struct mlx5_ifc_init_hca_in_bits { 7179 u8 opcode[0x10]; 7180 u8 reserved_at_10[0x10]; 7181 7182 u8 reserved_at_20[0x10]; 7183 u8 op_mod[0x10]; 7184 7185 u8 reserved_at_40[0x40]; 7186 u8 sw_owner_id[4][0x20]; 7187 }; 7188 7189 struct mlx5_ifc_init2rtr_qp_out_bits { 7190 u8 status[0x8]; 7191 u8 reserved_at_8[0x18]; 7192 7193 u8 syndrome[0x20]; 7194 7195 u8 reserved_at_40[0x20]; 7196 u8 ece[0x20]; 7197 }; 7198 7199 struct mlx5_ifc_init2rtr_qp_in_bits { 7200 u8 opcode[0x10]; 7201 u8 uid[0x10]; 7202 7203 u8 reserved_at_20[0x10]; 7204 u8 op_mod[0x10]; 7205 7206 u8 reserved_at_40[0x8]; 7207 u8 qpn[0x18]; 7208 7209 u8 reserved_at_60[0x20]; 7210 7211 u8 opt_param_mask[0x20]; 7212 7213 u8 ece[0x20]; 7214 7215 struct mlx5_ifc_qpc_bits qpc; 7216 7217 u8 reserved_at_800[0x80]; 7218 }; 7219 7220 struct mlx5_ifc_init2init_qp_out_bits { 7221 u8 status[0x8]; 7222 u8 reserved_at_8[0x18]; 7223 7224 u8 syndrome[0x20]; 7225 7226 u8 reserved_at_40[0x20]; 7227 u8 ece[0x20]; 7228 }; 7229 7230 struct mlx5_ifc_init2init_qp_in_bits { 7231 u8 opcode[0x10]; 7232 u8 uid[0x10]; 7233 7234 u8 reserved_at_20[0x10]; 7235 u8 op_mod[0x10]; 7236 7237 u8 reserved_at_40[0x8]; 7238 u8 qpn[0x18]; 7239 7240 u8 reserved_at_60[0x20]; 7241 7242 u8 opt_param_mask[0x20]; 7243 7244 u8 ece[0x20]; 7245 7246 struct mlx5_ifc_qpc_bits qpc; 7247 7248 u8 reserved_at_800[0x80]; 7249 }; 7250 7251 struct mlx5_ifc_get_dropped_packet_log_out_bits { 7252 u8 status[0x8]; 7253 u8 reserved_at_8[0x18]; 7254 7255 u8 syndrome[0x20]; 7256 7257 u8 reserved_at_40[0x40]; 7258 7259 u8 packet_headers_log[128][0x8]; 7260 7261 u8 packet_syndrome[64][0x8]; 7262 }; 7263 7264 struct mlx5_ifc_get_dropped_packet_log_in_bits { 7265 u8 opcode[0x10]; 7266 u8 reserved_at_10[0x10]; 7267 7268 u8 reserved_at_20[0x10]; 7269 u8 op_mod[0x10]; 7270 7271 u8 reserved_at_40[0x40]; 7272 }; 7273 7274 struct mlx5_ifc_gen_eqe_in_bits { 7275 u8 opcode[0x10]; 7276 u8 reserved_at_10[0x10]; 7277 7278 u8 reserved_at_20[0x10]; 7279 u8 op_mod[0x10]; 7280 7281 u8 reserved_at_40[0x18]; 7282 u8 eq_number[0x8]; 7283 7284 u8 reserved_at_60[0x20]; 7285 7286 u8 eqe[64][0x8]; 7287 }; 7288 7289 struct mlx5_ifc_gen_eq_out_bits { 7290 u8 status[0x8]; 7291 u8 reserved_at_8[0x18]; 7292 7293 u8 syndrome[0x20]; 7294 7295 u8 reserved_at_40[0x40]; 7296 }; 7297 7298 struct mlx5_ifc_enable_hca_out_bits { 7299 u8 status[0x8]; 7300 u8 reserved_at_8[0x18]; 7301 7302 u8 syndrome[0x20]; 7303 7304 u8 reserved_at_40[0x20]; 7305 }; 7306 7307 struct mlx5_ifc_enable_hca_in_bits { 7308 u8 opcode[0x10]; 7309 u8 reserved_at_10[0x10]; 7310 7311 u8 reserved_at_20[0x10]; 7312 u8 op_mod[0x10]; 7313 7314 u8 embedded_cpu_function[0x1]; 7315 u8 reserved_at_41[0xf]; 7316 u8 function_id[0x10]; 7317 7318 u8 reserved_at_60[0x20]; 7319 }; 7320 7321 struct mlx5_ifc_drain_dct_out_bits { 7322 u8 status[0x8]; 7323 u8 reserved_at_8[0x18]; 7324 7325 u8 syndrome[0x20]; 7326 7327 u8 reserved_at_40[0x40]; 7328 }; 7329 7330 struct mlx5_ifc_drain_dct_in_bits { 7331 u8 opcode[0x10]; 7332 u8 uid[0x10]; 7333 7334 u8 reserved_at_20[0x10]; 7335 u8 op_mod[0x10]; 7336 7337 u8 reserved_at_40[0x8]; 7338 u8 dctn[0x18]; 7339 7340 u8 reserved_at_60[0x20]; 7341 }; 7342 7343 struct mlx5_ifc_disable_hca_out_bits { 7344 u8 status[0x8]; 7345 u8 reserved_at_8[0x18]; 7346 7347 u8 syndrome[0x20]; 7348 7349 u8 reserved_at_40[0x20]; 7350 }; 7351 7352 struct mlx5_ifc_disable_hca_in_bits { 7353 u8 opcode[0x10]; 7354 u8 reserved_at_10[0x10]; 7355 7356 u8 reserved_at_20[0x10]; 7357 u8 op_mod[0x10]; 7358 7359 u8 embedded_cpu_function[0x1]; 7360 u8 reserved_at_41[0xf]; 7361 u8 function_id[0x10]; 7362 7363 u8 reserved_at_60[0x20]; 7364 }; 7365 7366 struct mlx5_ifc_detach_from_mcg_out_bits { 7367 u8 status[0x8]; 7368 u8 reserved_at_8[0x18]; 7369 7370 u8 syndrome[0x20]; 7371 7372 u8 reserved_at_40[0x40]; 7373 }; 7374 7375 struct mlx5_ifc_detach_from_mcg_in_bits { 7376 u8 opcode[0x10]; 7377 u8 uid[0x10]; 7378 7379 u8 reserved_at_20[0x10]; 7380 u8 op_mod[0x10]; 7381 7382 u8 reserved_at_40[0x8]; 7383 u8 qpn[0x18]; 7384 7385 u8 reserved_at_60[0x20]; 7386 7387 u8 multicast_gid[16][0x8]; 7388 }; 7389 7390 struct mlx5_ifc_destroy_xrq_out_bits { 7391 u8 status[0x8]; 7392 u8 reserved_at_8[0x18]; 7393 7394 u8 syndrome[0x20]; 7395 7396 u8 reserved_at_40[0x40]; 7397 }; 7398 7399 struct mlx5_ifc_destroy_xrq_in_bits { 7400 u8 opcode[0x10]; 7401 u8 uid[0x10]; 7402 7403 u8 reserved_at_20[0x10]; 7404 u8 op_mod[0x10]; 7405 7406 u8 reserved_at_40[0x8]; 7407 u8 xrqn[0x18]; 7408 7409 u8 reserved_at_60[0x20]; 7410 }; 7411 7412 struct mlx5_ifc_destroy_xrc_srq_out_bits { 7413 u8 status[0x8]; 7414 u8 reserved_at_8[0x18]; 7415 7416 u8 syndrome[0x20]; 7417 7418 u8 reserved_at_40[0x40]; 7419 }; 7420 7421 struct mlx5_ifc_destroy_xrc_srq_in_bits { 7422 u8 opcode[0x10]; 7423 u8 uid[0x10]; 7424 7425 u8 reserved_at_20[0x10]; 7426 u8 op_mod[0x10]; 7427 7428 u8 reserved_at_40[0x8]; 7429 u8 xrc_srqn[0x18]; 7430 7431 u8 reserved_at_60[0x20]; 7432 }; 7433 7434 struct mlx5_ifc_destroy_tis_out_bits { 7435 u8 status[0x8]; 7436 u8 reserved_at_8[0x18]; 7437 7438 u8 syndrome[0x20]; 7439 7440 u8 reserved_at_40[0x40]; 7441 }; 7442 7443 struct mlx5_ifc_destroy_tis_in_bits { 7444 u8 opcode[0x10]; 7445 u8 uid[0x10]; 7446 7447 u8 reserved_at_20[0x10]; 7448 u8 op_mod[0x10]; 7449 7450 u8 reserved_at_40[0x8]; 7451 u8 tisn[0x18]; 7452 7453 u8 reserved_at_60[0x20]; 7454 }; 7455 7456 struct mlx5_ifc_destroy_tir_out_bits { 7457 u8 status[0x8]; 7458 u8 reserved_at_8[0x18]; 7459 7460 u8 syndrome[0x20]; 7461 7462 u8 reserved_at_40[0x40]; 7463 }; 7464 7465 struct mlx5_ifc_destroy_tir_in_bits { 7466 u8 opcode[0x10]; 7467 u8 uid[0x10]; 7468 7469 u8 reserved_at_20[0x10]; 7470 u8 op_mod[0x10]; 7471 7472 u8 reserved_at_40[0x8]; 7473 u8 tirn[0x18]; 7474 7475 u8 reserved_at_60[0x20]; 7476 }; 7477 7478 struct mlx5_ifc_destroy_srq_out_bits { 7479 u8 status[0x8]; 7480 u8 reserved_at_8[0x18]; 7481 7482 u8 syndrome[0x20]; 7483 7484 u8 reserved_at_40[0x40]; 7485 }; 7486 7487 struct mlx5_ifc_destroy_srq_in_bits { 7488 u8 opcode[0x10]; 7489 u8 uid[0x10]; 7490 7491 u8 reserved_at_20[0x10]; 7492 u8 op_mod[0x10]; 7493 7494 u8 reserved_at_40[0x8]; 7495 u8 srqn[0x18]; 7496 7497 u8 reserved_at_60[0x20]; 7498 }; 7499 7500 struct mlx5_ifc_destroy_sq_out_bits { 7501 u8 status[0x8]; 7502 u8 reserved_at_8[0x18]; 7503 7504 u8 syndrome[0x20]; 7505 7506 u8 reserved_at_40[0x40]; 7507 }; 7508 7509 struct mlx5_ifc_destroy_sq_in_bits { 7510 u8 opcode[0x10]; 7511 u8 uid[0x10]; 7512 7513 u8 reserved_at_20[0x10]; 7514 u8 op_mod[0x10]; 7515 7516 u8 reserved_at_40[0x8]; 7517 u8 sqn[0x18]; 7518 7519 u8 reserved_at_60[0x20]; 7520 }; 7521 7522 struct mlx5_ifc_destroy_scheduling_element_out_bits { 7523 u8 status[0x8]; 7524 u8 reserved_at_8[0x18]; 7525 7526 u8 syndrome[0x20]; 7527 7528 u8 reserved_at_40[0x1c0]; 7529 }; 7530 7531 struct mlx5_ifc_destroy_scheduling_element_in_bits { 7532 u8 opcode[0x10]; 7533 u8 reserved_at_10[0x10]; 7534 7535 u8 reserved_at_20[0x10]; 7536 u8 op_mod[0x10]; 7537 7538 u8 scheduling_hierarchy[0x8]; 7539 u8 reserved_at_48[0x18]; 7540 7541 u8 scheduling_element_id[0x20]; 7542 7543 u8 reserved_at_80[0x180]; 7544 }; 7545 7546 struct mlx5_ifc_destroy_rqt_out_bits { 7547 u8 status[0x8]; 7548 u8 reserved_at_8[0x18]; 7549 7550 u8 syndrome[0x20]; 7551 7552 u8 reserved_at_40[0x40]; 7553 }; 7554 7555 struct mlx5_ifc_destroy_rqt_in_bits { 7556 u8 opcode[0x10]; 7557 u8 uid[0x10]; 7558 7559 u8 reserved_at_20[0x10]; 7560 u8 op_mod[0x10]; 7561 7562 u8 reserved_at_40[0x8]; 7563 u8 rqtn[0x18]; 7564 7565 u8 reserved_at_60[0x20]; 7566 }; 7567 7568 struct mlx5_ifc_destroy_rq_out_bits { 7569 u8 status[0x8]; 7570 u8 reserved_at_8[0x18]; 7571 7572 u8 syndrome[0x20]; 7573 7574 u8 reserved_at_40[0x40]; 7575 }; 7576 7577 struct mlx5_ifc_destroy_rq_in_bits { 7578 u8 opcode[0x10]; 7579 u8 uid[0x10]; 7580 7581 u8 reserved_at_20[0x10]; 7582 u8 op_mod[0x10]; 7583 7584 u8 reserved_at_40[0x8]; 7585 u8 rqn[0x18]; 7586 7587 u8 reserved_at_60[0x20]; 7588 }; 7589 7590 struct mlx5_ifc_set_delay_drop_params_in_bits { 7591 u8 opcode[0x10]; 7592 u8 reserved_at_10[0x10]; 7593 7594 u8 reserved_at_20[0x10]; 7595 u8 op_mod[0x10]; 7596 7597 u8 reserved_at_40[0x20]; 7598 7599 u8 reserved_at_60[0x10]; 7600 u8 delay_drop_timeout[0x10]; 7601 }; 7602 7603 struct mlx5_ifc_set_delay_drop_params_out_bits { 7604 u8 status[0x8]; 7605 u8 reserved_at_8[0x18]; 7606 7607 u8 syndrome[0x20]; 7608 7609 u8 reserved_at_40[0x40]; 7610 }; 7611 7612 struct mlx5_ifc_destroy_rmp_out_bits { 7613 u8 status[0x8]; 7614 u8 reserved_at_8[0x18]; 7615 7616 u8 syndrome[0x20]; 7617 7618 u8 reserved_at_40[0x40]; 7619 }; 7620 7621 struct mlx5_ifc_destroy_rmp_in_bits { 7622 u8 opcode[0x10]; 7623 u8 uid[0x10]; 7624 7625 u8 reserved_at_20[0x10]; 7626 u8 op_mod[0x10]; 7627 7628 u8 reserved_at_40[0x8]; 7629 u8 rmpn[0x18]; 7630 7631 u8 reserved_at_60[0x20]; 7632 }; 7633 7634 struct mlx5_ifc_destroy_qp_out_bits { 7635 u8 status[0x8]; 7636 u8 reserved_at_8[0x18]; 7637 7638 u8 syndrome[0x20]; 7639 7640 u8 reserved_at_40[0x40]; 7641 }; 7642 7643 struct mlx5_ifc_destroy_qp_in_bits { 7644 u8 opcode[0x10]; 7645 u8 uid[0x10]; 7646 7647 u8 reserved_at_20[0x10]; 7648 u8 op_mod[0x10]; 7649 7650 u8 reserved_at_40[0x8]; 7651 u8 qpn[0x18]; 7652 7653 u8 reserved_at_60[0x20]; 7654 }; 7655 7656 struct mlx5_ifc_destroy_psv_out_bits { 7657 u8 status[0x8]; 7658 u8 reserved_at_8[0x18]; 7659 7660 u8 syndrome[0x20]; 7661 7662 u8 reserved_at_40[0x40]; 7663 }; 7664 7665 struct mlx5_ifc_destroy_psv_in_bits { 7666 u8 opcode[0x10]; 7667 u8 reserved_at_10[0x10]; 7668 7669 u8 reserved_at_20[0x10]; 7670 u8 op_mod[0x10]; 7671 7672 u8 reserved_at_40[0x8]; 7673 u8 psvn[0x18]; 7674 7675 u8 reserved_at_60[0x20]; 7676 }; 7677 7678 struct mlx5_ifc_destroy_mkey_out_bits { 7679 u8 status[0x8]; 7680 u8 reserved_at_8[0x18]; 7681 7682 u8 syndrome[0x20]; 7683 7684 u8 reserved_at_40[0x40]; 7685 }; 7686 7687 struct mlx5_ifc_destroy_mkey_in_bits { 7688 u8 opcode[0x10]; 7689 u8 uid[0x10]; 7690 7691 u8 reserved_at_20[0x10]; 7692 u8 op_mod[0x10]; 7693 7694 u8 reserved_at_40[0x8]; 7695 u8 mkey_index[0x18]; 7696 7697 u8 reserved_at_60[0x20]; 7698 }; 7699 7700 struct mlx5_ifc_destroy_flow_table_out_bits { 7701 u8 status[0x8]; 7702 u8 reserved_at_8[0x18]; 7703 7704 u8 syndrome[0x20]; 7705 7706 u8 reserved_at_40[0x40]; 7707 }; 7708 7709 struct mlx5_ifc_destroy_flow_table_in_bits { 7710 u8 opcode[0x10]; 7711 u8 reserved_at_10[0x10]; 7712 7713 u8 reserved_at_20[0x10]; 7714 u8 op_mod[0x10]; 7715 7716 u8 other_vport[0x1]; 7717 u8 reserved_at_41[0xf]; 7718 u8 vport_number[0x10]; 7719 7720 u8 reserved_at_60[0x20]; 7721 7722 u8 table_type[0x8]; 7723 u8 reserved_at_88[0x18]; 7724 7725 u8 reserved_at_a0[0x8]; 7726 u8 table_id[0x18]; 7727 7728 u8 reserved_at_c0[0x140]; 7729 }; 7730 7731 struct mlx5_ifc_destroy_flow_group_out_bits { 7732 u8 status[0x8]; 7733 u8 reserved_at_8[0x18]; 7734 7735 u8 syndrome[0x20]; 7736 7737 u8 reserved_at_40[0x40]; 7738 }; 7739 7740 struct mlx5_ifc_destroy_flow_group_in_bits { 7741 u8 opcode[0x10]; 7742 u8 reserved_at_10[0x10]; 7743 7744 u8 reserved_at_20[0x10]; 7745 u8 op_mod[0x10]; 7746 7747 u8 other_vport[0x1]; 7748 u8 reserved_at_41[0xf]; 7749 u8 vport_number[0x10]; 7750 7751 u8 reserved_at_60[0x20]; 7752 7753 u8 table_type[0x8]; 7754 u8 reserved_at_88[0x18]; 7755 7756 u8 reserved_at_a0[0x8]; 7757 u8 table_id[0x18]; 7758 7759 u8 group_id[0x20]; 7760 7761 u8 reserved_at_e0[0x120]; 7762 }; 7763 7764 struct mlx5_ifc_destroy_eq_out_bits { 7765 u8 status[0x8]; 7766 u8 reserved_at_8[0x18]; 7767 7768 u8 syndrome[0x20]; 7769 7770 u8 reserved_at_40[0x40]; 7771 }; 7772 7773 struct mlx5_ifc_destroy_eq_in_bits { 7774 u8 opcode[0x10]; 7775 u8 reserved_at_10[0x10]; 7776 7777 u8 reserved_at_20[0x10]; 7778 u8 op_mod[0x10]; 7779 7780 u8 reserved_at_40[0x18]; 7781 u8 eq_number[0x8]; 7782 7783 u8 reserved_at_60[0x20]; 7784 }; 7785 7786 struct mlx5_ifc_destroy_dct_out_bits { 7787 u8 status[0x8]; 7788 u8 reserved_at_8[0x18]; 7789 7790 u8 syndrome[0x20]; 7791 7792 u8 reserved_at_40[0x40]; 7793 }; 7794 7795 struct mlx5_ifc_destroy_dct_in_bits { 7796 u8 opcode[0x10]; 7797 u8 uid[0x10]; 7798 7799 u8 reserved_at_20[0x10]; 7800 u8 op_mod[0x10]; 7801 7802 u8 reserved_at_40[0x8]; 7803 u8 dctn[0x18]; 7804 7805 u8 reserved_at_60[0x20]; 7806 }; 7807 7808 struct mlx5_ifc_destroy_cq_out_bits { 7809 u8 status[0x8]; 7810 u8 reserved_at_8[0x18]; 7811 7812 u8 syndrome[0x20]; 7813 7814 u8 reserved_at_40[0x40]; 7815 }; 7816 7817 struct mlx5_ifc_destroy_cq_in_bits { 7818 u8 opcode[0x10]; 7819 u8 uid[0x10]; 7820 7821 u8 reserved_at_20[0x10]; 7822 u8 op_mod[0x10]; 7823 7824 u8 reserved_at_40[0x8]; 7825 u8 cqn[0x18]; 7826 7827 u8 reserved_at_60[0x20]; 7828 }; 7829 7830 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits { 7831 u8 status[0x8]; 7832 u8 reserved_at_8[0x18]; 7833 7834 u8 syndrome[0x20]; 7835 7836 u8 reserved_at_40[0x40]; 7837 }; 7838 7839 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits { 7840 u8 opcode[0x10]; 7841 u8 reserved_at_10[0x10]; 7842 7843 u8 reserved_at_20[0x10]; 7844 u8 op_mod[0x10]; 7845 7846 u8 reserved_at_40[0x20]; 7847 7848 u8 reserved_at_60[0x10]; 7849 u8 vxlan_udp_port[0x10]; 7850 }; 7851 7852 struct mlx5_ifc_delete_l2_table_entry_out_bits { 7853 u8 status[0x8]; 7854 u8 reserved_at_8[0x18]; 7855 7856 u8 syndrome[0x20]; 7857 7858 u8 reserved_at_40[0x40]; 7859 }; 7860 7861 struct mlx5_ifc_delete_l2_table_entry_in_bits { 7862 u8 opcode[0x10]; 7863 u8 reserved_at_10[0x10]; 7864 7865 u8 reserved_at_20[0x10]; 7866 u8 op_mod[0x10]; 7867 7868 u8 reserved_at_40[0x60]; 7869 7870 u8 reserved_at_a0[0x8]; 7871 u8 table_index[0x18]; 7872 7873 u8 reserved_at_c0[0x140]; 7874 }; 7875 7876 struct mlx5_ifc_delete_fte_out_bits { 7877 u8 status[0x8]; 7878 u8 reserved_at_8[0x18]; 7879 7880 u8 syndrome[0x20]; 7881 7882 u8 reserved_at_40[0x40]; 7883 }; 7884 7885 struct mlx5_ifc_delete_fte_in_bits { 7886 u8 opcode[0x10]; 7887 u8 reserved_at_10[0x10]; 7888 7889 u8 reserved_at_20[0x10]; 7890 u8 op_mod[0x10]; 7891 7892 u8 other_vport[0x1]; 7893 u8 reserved_at_41[0xf]; 7894 u8 vport_number[0x10]; 7895 7896 u8 reserved_at_60[0x20]; 7897 7898 u8 table_type[0x8]; 7899 u8 reserved_at_88[0x18]; 7900 7901 u8 reserved_at_a0[0x8]; 7902 u8 table_id[0x18]; 7903 7904 u8 reserved_at_c0[0x40]; 7905 7906 u8 flow_index[0x20]; 7907 7908 u8 reserved_at_120[0xe0]; 7909 }; 7910 7911 struct mlx5_ifc_dealloc_xrcd_out_bits { 7912 u8 status[0x8]; 7913 u8 reserved_at_8[0x18]; 7914 7915 u8 syndrome[0x20]; 7916 7917 u8 reserved_at_40[0x40]; 7918 }; 7919 7920 struct mlx5_ifc_dealloc_xrcd_in_bits { 7921 u8 opcode[0x10]; 7922 u8 uid[0x10]; 7923 7924 u8 reserved_at_20[0x10]; 7925 u8 op_mod[0x10]; 7926 7927 u8 reserved_at_40[0x8]; 7928 u8 xrcd[0x18]; 7929 7930 u8 reserved_at_60[0x20]; 7931 }; 7932 7933 struct mlx5_ifc_dealloc_uar_out_bits { 7934 u8 status[0x8]; 7935 u8 reserved_at_8[0x18]; 7936 7937 u8 syndrome[0x20]; 7938 7939 u8 reserved_at_40[0x40]; 7940 }; 7941 7942 struct mlx5_ifc_dealloc_uar_in_bits { 7943 u8 opcode[0x10]; 7944 u8 uid[0x10]; 7945 7946 u8 reserved_at_20[0x10]; 7947 u8 op_mod[0x10]; 7948 7949 u8 reserved_at_40[0x8]; 7950 u8 uar[0x18]; 7951 7952 u8 reserved_at_60[0x20]; 7953 }; 7954 7955 struct mlx5_ifc_dealloc_transport_domain_out_bits { 7956 u8 status[0x8]; 7957 u8 reserved_at_8[0x18]; 7958 7959 u8 syndrome[0x20]; 7960 7961 u8 reserved_at_40[0x40]; 7962 }; 7963 7964 struct mlx5_ifc_dealloc_transport_domain_in_bits { 7965 u8 opcode[0x10]; 7966 u8 uid[0x10]; 7967 7968 u8 reserved_at_20[0x10]; 7969 u8 op_mod[0x10]; 7970 7971 u8 reserved_at_40[0x8]; 7972 u8 transport_domain[0x18]; 7973 7974 u8 reserved_at_60[0x20]; 7975 }; 7976 7977 struct mlx5_ifc_dealloc_q_counter_out_bits { 7978 u8 status[0x8]; 7979 u8 reserved_at_8[0x18]; 7980 7981 u8 syndrome[0x20]; 7982 7983 u8 reserved_at_40[0x40]; 7984 }; 7985 7986 struct mlx5_ifc_dealloc_q_counter_in_bits { 7987 u8 opcode[0x10]; 7988 u8 reserved_at_10[0x10]; 7989 7990 u8 reserved_at_20[0x10]; 7991 u8 op_mod[0x10]; 7992 7993 u8 reserved_at_40[0x18]; 7994 u8 counter_set_id[0x8]; 7995 7996 u8 reserved_at_60[0x20]; 7997 }; 7998 7999 struct mlx5_ifc_dealloc_pd_out_bits { 8000 u8 status[0x8]; 8001 u8 reserved_at_8[0x18]; 8002 8003 u8 syndrome[0x20]; 8004 8005 u8 reserved_at_40[0x40]; 8006 }; 8007 8008 struct mlx5_ifc_dealloc_pd_in_bits { 8009 u8 opcode[0x10]; 8010 u8 uid[0x10]; 8011 8012 u8 reserved_at_20[0x10]; 8013 u8 op_mod[0x10]; 8014 8015 u8 reserved_at_40[0x8]; 8016 u8 pd[0x18]; 8017 8018 u8 reserved_at_60[0x20]; 8019 }; 8020 8021 struct mlx5_ifc_dealloc_flow_counter_out_bits { 8022 u8 status[0x8]; 8023 u8 reserved_at_8[0x18]; 8024 8025 u8 syndrome[0x20]; 8026 8027 u8 reserved_at_40[0x40]; 8028 }; 8029 8030 struct mlx5_ifc_dealloc_flow_counter_in_bits { 8031 u8 opcode[0x10]; 8032 u8 reserved_at_10[0x10]; 8033 8034 u8 reserved_at_20[0x10]; 8035 u8 op_mod[0x10]; 8036 8037 u8 flow_counter_id[0x20]; 8038 8039 u8 reserved_at_60[0x20]; 8040 }; 8041 8042 struct mlx5_ifc_create_xrq_out_bits { 8043 u8 status[0x8]; 8044 u8 reserved_at_8[0x18]; 8045 8046 u8 syndrome[0x20]; 8047 8048 u8 reserved_at_40[0x8]; 8049 u8 xrqn[0x18]; 8050 8051 u8 reserved_at_60[0x20]; 8052 }; 8053 8054 struct mlx5_ifc_create_xrq_in_bits { 8055 u8 opcode[0x10]; 8056 u8 uid[0x10]; 8057 8058 u8 reserved_at_20[0x10]; 8059 u8 op_mod[0x10]; 8060 8061 u8 reserved_at_40[0x40]; 8062 8063 struct mlx5_ifc_xrqc_bits xrq_context; 8064 }; 8065 8066 struct mlx5_ifc_create_xrc_srq_out_bits { 8067 u8 status[0x8]; 8068 u8 reserved_at_8[0x18]; 8069 8070 u8 syndrome[0x20]; 8071 8072 u8 reserved_at_40[0x8]; 8073 u8 xrc_srqn[0x18]; 8074 8075 u8 reserved_at_60[0x20]; 8076 }; 8077 8078 struct mlx5_ifc_create_xrc_srq_in_bits { 8079 u8 opcode[0x10]; 8080 u8 uid[0x10]; 8081 8082 u8 reserved_at_20[0x10]; 8083 u8 op_mod[0x10]; 8084 8085 u8 reserved_at_40[0x40]; 8086 8087 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 8088 8089 u8 reserved_at_280[0x60]; 8090 8091 u8 xrc_srq_umem_valid[0x1]; 8092 u8 reserved_at_2e1[0x1f]; 8093 8094 u8 reserved_at_300[0x580]; 8095 8096 u8 pas[][0x40]; 8097 }; 8098 8099 struct mlx5_ifc_create_tis_out_bits { 8100 u8 status[0x8]; 8101 u8 reserved_at_8[0x18]; 8102 8103 u8 syndrome[0x20]; 8104 8105 u8 reserved_at_40[0x8]; 8106 u8 tisn[0x18]; 8107 8108 u8 reserved_at_60[0x20]; 8109 }; 8110 8111 struct mlx5_ifc_create_tis_in_bits { 8112 u8 opcode[0x10]; 8113 u8 uid[0x10]; 8114 8115 u8 reserved_at_20[0x10]; 8116 u8 op_mod[0x10]; 8117 8118 u8 reserved_at_40[0xc0]; 8119 8120 struct mlx5_ifc_tisc_bits ctx; 8121 }; 8122 8123 struct mlx5_ifc_create_tir_out_bits { 8124 u8 status[0x8]; 8125 u8 icm_address_63_40[0x18]; 8126 8127 u8 syndrome[0x20]; 8128 8129 u8 icm_address_39_32[0x8]; 8130 u8 tirn[0x18]; 8131 8132 u8 icm_address_31_0[0x20]; 8133 }; 8134 8135 struct mlx5_ifc_create_tir_in_bits { 8136 u8 opcode[0x10]; 8137 u8 uid[0x10]; 8138 8139 u8 reserved_at_20[0x10]; 8140 u8 op_mod[0x10]; 8141 8142 u8 reserved_at_40[0xc0]; 8143 8144 struct mlx5_ifc_tirc_bits ctx; 8145 }; 8146 8147 struct mlx5_ifc_create_srq_out_bits { 8148 u8 status[0x8]; 8149 u8 reserved_at_8[0x18]; 8150 8151 u8 syndrome[0x20]; 8152 8153 u8 reserved_at_40[0x8]; 8154 u8 srqn[0x18]; 8155 8156 u8 reserved_at_60[0x20]; 8157 }; 8158 8159 struct mlx5_ifc_create_srq_in_bits { 8160 u8 opcode[0x10]; 8161 u8 uid[0x10]; 8162 8163 u8 reserved_at_20[0x10]; 8164 u8 op_mod[0x10]; 8165 8166 u8 reserved_at_40[0x40]; 8167 8168 struct mlx5_ifc_srqc_bits srq_context_entry; 8169 8170 u8 reserved_at_280[0x600]; 8171 8172 u8 pas[][0x40]; 8173 }; 8174 8175 struct mlx5_ifc_create_sq_out_bits { 8176 u8 status[0x8]; 8177 u8 reserved_at_8[0x18]; 8178 8179 u8 syndrome[0x20]; 8180 8181 u8 reserved_at_40[0x8]; 8182 u8 sqn[0x18]; 8183 8184 u8 reserved_at_60[0x20]; 8185 }; 8186 8187 struct mlx5_ifc_create_sq_in_bits { 8188 u8 opcode[0x10]; 8189 u8 uid[0x10]; 8190 8191 u8 reserved_at_20[0x10]; 8192 u8 op_mod[0x10]; 8193 8194 u8 reserved_at_40[0xc0]; 8195 8196 struct mlx5_ifc_sqc_bits ctx; 8197 }; 8198 8199 struct mlx5_ifc_create_scheduling_element_out_bits { 8200 u8 status[0x8]; 8201 u8 reserved_at_8[0x18]; 8202 8203 u8 syndrome[0x20]; 8204 8205 u8 reserved_at_40[0x40]; 8206 8207 u8 scheduling_element_id[0x20]; 8208 8209 u8 reserved_at_a0[0x160]; 8210 }; 8211 8212 struct mlx5_ifc_create_scheduling_element_in_bits { 8213 u8 opcode[0x10]; 8214 u8 reserved_at_10[0x10]; 8215 8216 u8 reserved_at_20[0x10]; 8217 u8 op_mod[0x10]; 8218 8219 u8 scheduling_hierarchy[0x8]; 8220 u8 reserved_at_48[0x18]; 8221 8222 u8 reserved_at_60[0xa0]; 8223 8224 struct mlx5_ifc_scheduling_context_bits scheduling_context; 8225 8226 u8 reserved_at_300[0x100]; 8227 }; 8228 8229 struct mlx5_ifc_create_rqt_out_bits { 8230 u8 status[0x8]; 8231 u8 reserved_at_8[0x18]; 8232 8233 u8 syndrome[0x20]; 8234 8235 u8 reserved_at_40[0x8]; 8236 u8 rqtn[0x18]; 8237 8238 u8 reserved_at_60[0x20]; 8239 }; 8240 8241 struct mlx5_ifc_create_rqt_in_bits { 8242 u8 opcode[0x10]; 8243 u8 uid[0x10]; 8244 8245 u8 reserved_at_20[0x10]; 8246 u8 op_mod[0x10]; 8247 8248 u8 reserved_at_40[0xc0]; 8249 8250 struct mlx5_ifc_rqtc_bits rqt_context; 8251 }; 8252 8253 struct mlx5_ifc_create_rq_out_bits { 8254 u8 status[0x8]; 8255 u8 reserved_at_8[0x18]; 8256 8257 u8 syndrome[0x20]; 8258 8259 u8 reserved_at_40[0x8]; 8260 u8 rqn[0x18]; 8261 8262 u8 reserved_at_60[0x20]; 8263 }; 8264 8265 struct mlx5_ifc_create_rq_in_bits { 8266 u8 opcode[0x10]; 8267 u8 uid[0x10]; 8268 8269 u8 reserved_at_20[0x10]; 8270 u8 op_mod[0x10]; 8271 8272 u8 reserved_at_40[0xc0]; 8273 8274 struct mlx5_ifc_rqc_bits ctx; 8275 }; 8276 8277 struct mlx5_ifc_create_rmp_out_bits { 8278 u8 status[0x8]; 8279 u8 reserved_at_8[0x18]; 8280 8281 u8 syndrome[0x20]; 8282 8283 u8 reserved_at_40[0x8]; 8284 u8 rmpn[0x18]; 8285 8286 u8 reserved_at_60[0x20]; 8287 }; 8288 8289 struct mlx5_ifc_create_rmp_in_bits { 8290 u8 opcode[0x10]; 8291 u8 uid[0x10]; 8292 8293 u8 reserved_at_20[0x10]; 8294 u8 op_mod[0x10]; 8295 8296 u8 reserved_at_40[0xc0]; 8297 8298 struct mlx5_ifc_rmpc_bits ctx; 8299 }; 8300 8301 struct mlx5_ifc_create_qp_out_bits { 8302 u8 status[0x8]; 8303 u8 reserved_at_8[0x18]; 8304 8305 u8 syndrome[0x20]; 8306 8307 u8 reserved_at_40[0x8]; 8308 u8 qpn[0x18]; 8309 8310 u8 ece[0x20]; 8311 }; 8312 8313 struct mlx5_ifc_create_qp_in_bits { 8314 u8 opcode[0x10]; 8315 u8 uid[0x10]; 8316 8317 u8 reserved_at_20[0x10]; 8318 u8 op_mod[0x10]; 8319 8320 u8 reserved_at_40[0x8]; 8321 u8 input_qpn[0x18]; 8322 8323 u8 reserved_at_60[0x20]; 8324 u8 opt_param_mask[0x20]; 8325 8326 u8 ece[0x20]; 8327 8328 struct mlx5_ifc_qpc_bits qpc; 8329 8330 u8 reserved_at_800[0x60]; 8331 8332 u8 wq_umem_valid[0x1]; 8333 u8 reserved_at_861[0x1f]; 8334 8335 u8 pas[][0x40]; 8336 }; 8337 8338 struct mlx5_ifc_create_psv_out_bits { 8339 u8 status[0x8]; 8340 u8 reserved_at_8[0x18]; 8341 8342 u8 syndrome[0x20]; 8343 8344 u8 reserved_at_40[0x40]; 8345 8346 u8 reserved_at_80[0x8]; 8347 u8 psv0_index[0x18]; 8348 8349 u8 reserved_at_a0[0x8]; 8350 u8 psv1_index[0x18]; 8351 8352 u8 reserved_at_c0[0x8]; 8353 u8 psv2_index[0x18]; 8354 8355 u8 reserved_at_e0[0x8]; 8356 u8 psv3_index[0x18]; 8357 }; 8358 8359 struct mlx5_ifc_create_psv_in_bits { 8360 u8 opcode[0x10]; 8361 u8 reserved_at_10[0x10]; 8362 8363 u8 reserved_at_20[0x10]; 8364 u8 op_mod[0x10]; 8365 8366 u8 num_psv[0x4]; 8367 u8 reserved_at_44[0x4]; 8368 u8 pd[0x18]; 8369 8370 u8 reserved_at_60[0x20]; 8371 }; 8372 8373 struct mlx5_ifc_create_mkey_out_bits { 8374 u8 status[0x8]; 8375 u8 reserved_at_8[0x18]; 8376 8377 u8 syndrome[0x20]; 8378 8379 u8 reserved_at_40[0x8]; 8380 u8 mkey_index[0x18]; 8381 8382 u8 reserved_at_60[0x20]; 8383 }; 8384 8385 struct mlx5_ifc_create_mkey_in_bits { 8386 u8 opcode[0x10]; 8387 u8 uid[0x10]; 8388 8389 u8 reserved_at_20[0x10]; 8390 u8 op_mod[0x10]; 8391 8392 u8 reserved_at_40[0x20]; 8393 8394 u8 pg_access[0x1]; 8395 u8 mkey_umem_valid[0x1]; 8396 u8 reserved_at_62[0x1e]; 8397 8398 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 8399 8400 u8 reserved_at_280[0x80]; 8401 8402 u8 translations_octword_actual_size[0x20]; 8403 8404 u8 reserved_at_320[0x560]; 8405 8406 u8 klm_pas_mtt[][0x20]; 8407 }; 8408 8409 enum { 8410 MLX5_FLOW_TABLE_TYPE_NIC_RX = 0x0, 8411 MLX5_FLOW_TABLE_TYPE_NIC_TX = 0x1, 8412 MLX5_FLOW_TABLE_TYPE_ESW_EGRESS_ACL = 0x2, 8413 MLX5_FLOW_TABLE_TYPE_ESW_INGRESS_ACL = 0x3, 8414 MLX5_FLOW_TABLE_TYPE_FDB = 0X4, 8415 MLX5_FLOW_TABLE_TYPE_SNIFFER_RX = 0X5, 8416 MLX5_FLOW_TABLE_TYPE_SNIFFER_TX = 0X6, 8417 }; 8418 8419 struct mlx5_ifc_create_flow_table_out_bits { 8420 u8 status[0x8]; 8421 u8 icm_address_63_40[0x18]; 8422 8423 u8 syndrome[0x20]; 8424 8425 u8 icm_address_39_32[0x8]; 8426 u8 table_id[0x18]; 8427 8428 u8 icm_address_31_0[0x20]; 8429 }; 8430 8431 struct mlx5_ifc_create_flow_table_in_bits { 8432 u8 opcode[0x10]; 8433 u8 reserved_at_10[0x10]; 8434 8435 u8 reserved_at_20[0x10]; 8436 u8 op_mod[0x10]; 8437 8438 u8 other_vport[0x1]; 8439 u8 reserved_at_41[0xf]; 8440 u8 vport_number[0x10]; 8441 8442 u8 reserved_at_60[0x20]; 8443 8444 u8 table_type[0x8]; 8445 u8 reserved_at_88[0x18]; 8446 8447 u8 reserved_at_a0[0x20]; 8448 8449 struct mlx5_ifc_flow_table_context_bits flow_table_context; 8450 }; 8451 8452 struct mlx5_ifc_create_flow_group_out_bits { 8453 u8 status[0x8]; 8454 u8 reserved_at_8[0x18]; 8455 8456 u8 syndrome[0x20]; 8457 8458 u8 reserved_at_40[0x8]; 8459 u8 group_id[0x18]; 8460 8461 u8 reserved_at_60[0x20]; 8462 }; 8463 8464 enum { 8465 MLX5_CREATE_FLOW_GROUP_IN_GROUP_TYPE_TCAM_SUBTABLE = 0x0, 8466 MLX5_CREATE_FLOW_GROUP_IN_GROUP_TYPE_HASH_SPLIT = 0x1, 8467 }; 8468 8469 enum { 8470 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 8471 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 8472 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 8473 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3, 8474 }; 8475 8476 struct mlx5_ifc_create_flow_group_in_bits { 8477 u8 opcode[0x10]; 8478 u8 reserved_at_10[0x10]; 8479 8480 u8 reserved_at_20[0x10]; 8481 u8 op_mod[0x10]; 8482 8483 u8 other_vport[0x1]; 8484 u8 reserved_at_41[0xf]; 8485 u8 vport_number[0x10]; 8486 8487 u8 reserved_at_60[0x20]; 8488 8489 u8 table_type[0x8]; 8490 u8 reserved_at_88[0x4]; 8491 u8 group_type[0x4]; 8492 u8 reserved_at_90[0x10]; 8493 8494 u8 reserved_at_a0[0x8]; 8495 u8 table_id[0x18]; 8496 8497 u8 source_eswitch_owner_vhca_id_valid[0x1]; 8498 8499 u8 reserved_at_c1[0x1f]; 8500 8501 u8 start_flow_index[0x20]; 8502 8503 u8 reserved_at_100[0x20]; 8504 8505 u8 end_flow_index[0x20]; 8506 8507 u8 reserved_at_140[0x10]; 8508 u8 match_definer_id[0x10]; 8509 8510 u8 reserved_at_160[0x80]; 8511 8512 u8 reserved_at_1e0[0x18]; 8513 u8 match_criteria_enable[0x8]; 8514 8515 struct mlx5_ifc_fte_match_param_bits match_criteria; 8516 8517 u8 reserved_at_1200[0xe00]; 8518 }; 8519 8520 struct mlx5_ifc_create_eq_out_bits { 8521 u8 status[0x8]; 8522 u8 reserved_at_8[0x18]; 8523 8524 u8 syndrome[0x20]; 8525 8526 u8 reserved_at_40[0x18]; 8527 u8 eq_number[0x8]; 8528 8529 u8 reserved_at_60[0x20]; 8530 }; 8531 8532 struct mlx5_ifc_create_eq_in_bits { 8533 u8 opcode[0x10]; 8534 u8 uid[0x10]; 8535 8536 u8 reserved_at_20[0x10]; 8537 u8 op_mod[0x10]; 8538 8539 u8 reserved_at_40[0x40]; 8540 8541 struct mlx5_ifc_eqc_bits eq_context_entry; 8542 8543 u8 reserved_at_280[0x40]; 8544 8545 u8 event_bitmask[4][0x40]; 8546 8547 u8 reserved_at_3c0[0x4c0]; 8548 8549 u8 pas[][0x40]; 8550 }; 8551 8552 struct mlx5_ifc_create_dct_out_bits { 8553 u8 status[0x8]; 8554 u8 reserved_at_8[0x18]; 8555 8556 u8 syndrome[0x20]; 8557 8558 u8 reserved_at_40[0x8]; 8559 u8 dctn[0x18]; 8560 8561 u8 ece[0x20]; 8562 }; 8563 8564 struct mlx5_ifc_create_dct_in_bits { 8565 u8 opcode[0x10]; 8566 u8 uid[0x10]; 8567 8568 u8 reserved_at_20[0x10]; 8569 u8 op_mod[0x10]; 8570 8571 u8 reserved_at_40[0x40]; 8572 8573 struct mlx5_ifc_dctc_bits dct_context_entry; 8574 8575 u8 reserved_at_280[0x180]; 8576 }; 8577 8578 struct mlx5_ifc_create_cq_out_bits { 8579 u8 status[0x8]; 8580 u8 reserved_at_8[0x18]; 8581 8582 u8 syndrome[0x20]; 8583 8584 u8 reserved_at_40[0x8]; 8585 u8 cqn[0x18]; 8586 8587 u8 reserved_at_60[0x20]; 8588 }; 8589 8590 struct mlx5_ifc_create_cq_in_bits { 8591 u8 opcode[0x10]; 8592 u8 uid[0x10]; 8593 8594 u8 reserved_at_20[0x10]; 8595 u8 op_mod[0x10]; 8596 8597 u8 reserved_at_40[0x40]; 8598 8599 struct mlx5_ifc_cqc_bits cq_context; 8600 8601 u8 reserved_at_280[0x60]; 8602 8603 u8 cq_umem_valid[0x1]; 8604 u8 reserved_at_2e1[0x59f]; 8605 8606 u8 pas[][0x40]; 8607 }; 8608 8609 struct mlx5_ifc_config_int_moderation_out_bits { 8610 u8 status[0x8]; 8611 u8 reserved_at_8[0x18]; 8612 8613 u8 syndrome[0x20]; 8614 8615 u8 reserved_at_40[0x4]; 8616 u8 min_delay[0xc]; 8617 u8 int_vector[0x10]; 8618 8619 u8 reserved_at_60[0x20]; 8620 }; 8621 8622 enum { 8623 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0, 8624 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1, 8625 }; 8626 8627 struct mlx5_ifc_config_int_moderation_in_bits { 8628 u8 opcode[0x10]; 8629 u8 reserved_at_10[0x10]; 8630 8631 u8 reserved_at_20[0x10]; 8632 u8 op_mod[0x10]; 8633 8634 u8 reserved_at_40[0x4]; 8635 u8 min_delay[0xc]; 8636 u8 int_vector[0x10]; 8637 8638 u8 reserved_at_60[0x20]; 8639 }; 8640 8641 struct mlx5_ifc_attach_to_mcg_out_bits { 8642 u8 status[0x8]; 8643 u8 reserved_at_8[0x18]; 8644 8645 u8 syndrome[0x20]; 8646 8647 u8 reserved_at_40[0x40]; 8648 }; 8649 8650 struct mlx5_ifc_attach_to_mcg_in_bits { 8651 u8 opcode[0x10]; 8652 u8 uid[0x10]; 8653 8654 u8 reserved_at_20[0x10]; 8655 u8 op_mod[0x10]; 8656 8657 u8 reserved_at_40[0x8]; 8658 u8 qpn[0x18]; 8659 8660 u8 reserved_at_60[0x20]; 8661 8662 u8 multicast_gid[16][0x8]; 8663 }; 8664 8665 struct mlx5_ifc_arm_xrq_out_bits { 8666 u8 status[0x8]; 8667 u8 reserved_at_8[0x18]; 8668 8669 u8 syndrome[0x20]; 8670 8671 u8 reserved_at_40[0x40]; 8672 }; 8673 8674 struct mlx5_ifc_arm_xrq_in_bits { 8675 u8 opcode[0x10]; 8676 u8 reserved_at_10[0x10]; 8677 8678 u8 reserved_at_20[0x10]; 8679 u8 op_mod[0x10]; 8680 8681 u8 reserved_at_40[0x8]; 8682 u8 xrqn[0x18]; 8683 8684 u8 reserved_at_60[0x10]; 8685 u8 lwm[0x10]; 8686 }; 8687 8688 struct mlx5_ifc_arm_xrc_srq_out_bits { 8689 u8 status[0x8]; 8690 u8 reserved_at_8[0x18]; 8691 8692 u8 syndrome[0x20]; 8693 8694 u8 reserved_at_40[0x40]; 8695 }; 8696 8697 enum { 8698 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1, 8699 }; 8700 8701 struct mlx5_ifc_arm_xrc_srq_in_bits { 8702 u8 opcode[0x10]; 8703 u8 uid[0x10]; 8704 8705 u8 reserved_at_20[0x10]; 8706 u8 op_mod[0x10]; 8707 8708 u8 reserved_at_40[0x8]; 8709 u8 xrc_srqn[0x18]; 8710 8711 u8 reserved_at_60[0x10]; 8712 u8 lwm[0x10]; 8713 }; 8714 8715 struct mlx5_ifc_arm_rq_out_bits { 8716 u8 status[0x8]; 8717 u8 reserved_at_8[0x18]; 8718 8719 u8 syndrome[0x20]; 8720 8721 u8 reserved_at_40[0x40]; 8722 }; 8723 8724 enum { 8725 MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1, 8726 MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2, 8727 }; 8728 8729 struct mlx5_ifc_arm_rq_in_bits { 8730 u8 opcode[0x10]; 8731 u8 uid[0x10]; 8732 8733 u8 reserved_at_20[0x10]; 8734 u8 op_mod[0x10]; 8735 8736 u8 reserved_at_40[0x8]; 8737 u8 srq_number[0x18]; 8738 8739 u8 reserved_at_60[0x10]; 8740 u8 lwm[0x10]; 8741 }; 8742 8743 struct mlx5_ifc_arm_dct_out_bits { 8744 u8 status[0x8]; 8745 u8 reserved_at_8[0x18]; 8746 8747 u8 syndrome[0x20]; 8748 8749 u8 reserved_at_40[0x40]; 8750 }; 8751 8752 struct mlx5_ifc_arm_dct_in_bits { 8753 u8 opcode[0x10]; 8754 u8 reserved_at_10[0x10]; 8755 8756 u8 reserved_at_20[0x10]; 8757 u8 op_mod[0x10]; 8758 8759 u8 reserved_at_40[0x8]; 8760 u8 dct_number[0x18]; 8761 8762 u8 reserved_at_60[0x20]; 8763 }; 8764 8765 struct mlx5_ifc_alloc_xrcd_out_bits { 8766 u8 status[0x8]; 8767 u8 reserved_at_8[0x18]; 8768 8769 u8 syndrome[0x20]; 8770 8771 u8 reserved_at_40[0x8]; 8772 u8 xrcd[0x18]; 8773 8774 u8 reserved_at_60[0x20]; 8775 }; 8776 8777 struct mlx5_ifc_alloc_xrcd_in_bits { 8778 u8 opcode[0x10]; 8779 u8 uid[0x10]; 8780 8781 u8 reserved_at_20[0x10]; 8782 u8 op_mod[0x10]; 8783 8784 u8 reserved_at_40[0x40]; 8785 }; 8786 8787 struct mlx5_ifc_alloc_uar_out_bits { 8788 u8 status[0x8]; 8789 u8 reserved_at_8[0x18]; 8790 8791 u8 syndrome[0x20]; 8792 8793 u8 reserved_at_40[0x8]; 8794 u8 uar[0x18]; 8795 8796 u8 reserved_at_60[0x20]; 8797 }; 8798 8799 struct mlx5_ifc_alloc_uar_in_bits { 8800 u8 opcode[0x10]; 8801 u8 uid[0x10]; 8802 8803 u8 reserved_at_20[0x10]; 8804 u8 op_mod[0x10]; 8805 8806 u8 reserved_at_40[0x40]; 8807 }; 8808 8809 struct mlx5_ifc_alloc_transport_domain_out_bits { 8810 u8 status[0x8]; 8811 u8 reserved_at_8[0x18]; 8812 8813 u8 syndrome[0x20]; 8814 8815 u8 reserved_at_40[0x8]; 8816 u8 transport_domain[0x18]; 8817 8818 u8 reserved_at_60[0x20]; 8819 }; 8820 8821 struct mlx5_ifc_alloc_transport_domain_in_bits { 8822 u8 opcode[0x10]; 8823 u8 uid[0x10]; 8824 8825 u8 reserved_at_20[0x10]; 8826 u8 op_mod[0x10]; 8827 8828 u8 reserved_at_40[0x40]; 8829 }; 8830 8831 struct mlx5_ifc_alloc_q_counter_out_bits { 8832 u8 status[0x8]; 8833 u8 reserved_at_8[0x18]; 8834 8835 u8 syndrome[0x20]; 8836 8837 u8 reserved_at_40[0x18]; 8838 u8 counter_set_id[0x8]; 8839 8840 u8 reserved_at_60[0x20]; 8841 }; 8842 8843 struct mlx5_ifc_alloc_q_counter_in_bits { 8844 u8 opcode[0x10]; 8845 u8 uid[0x10]; 8846 8847 u8 reserved_at_20[0x10]; 8848 u8 op_mod[0x10]; 8849 8850 u8 reserved_at_40[0x40]; 8851 }; 8852 8853 struct mlx5_ifc_alloc_pd_out_bits { 8854 u8 status[0x8]; 8855 u8 reserved_at_8[0x18]; 8856 8857 u8 syndrome[0x20]; 8858 8859 u8 reserved_at_40[0x8]; 8860 u8 pd[0x18]; 8861 8862 u8 reserved_at_60[0x20]; 8863 }; 8864 8865 struct mlx5_ifc_alloc_pd_in_bits { 8866 u8 opcode[0x10]; 8867 u8 uid[0x10]; 8868 8869 u8 reserved_at_20[0x10]; 8870 u8 op_mod[0x10]; 8871 8872 u8 reserved_at_40[0x40]; 8873 }; 8874 8875 struct mlx5_ifc_alloc_flow_counter_out_bits { 8876 u8 status[0x8]; 8877 u8 reserved_at_8[0x18]; 8878 8879 u8 syndrome[0x20]; 8880 8881 u8 flow_counter_id[0x20]; 8882 8883 u8 reserved_at_60[0x20]; 8884 }; 8885 8886 struct mlx5_ifc_alloc_flow_counter_in_bits { 8887 u8 opcode[0x10]; 8888 u8 reserved_at_10[0x10]; 8889 8890 u8 reserved_at_20[0x10]; 8891 u8 op_mod[0x10]; 8892 8893 u8 reserved_at_40[0x38]; 8894 u8 flow_counter_bulk[0x8]; 8895 }; 8896 8897 struct mlx5_ifc_add_vxlan_udp_dport_out_bits { 8898 u8 status[0x8]; 8899 u8 reserved_at_8[0x18]; 8900 8901 u8 syndrome[0x20]; 8902 8903 u8 reserved_at_40[0x40]; 8904 }; 8905 8906 struct mlx5_ifc_add_vxlan_udp_dport_in_bits { 8907 u8 opcode[0x10]; 8908 u8 reserved_at_10[0x10]; 8909 8910 u8 reserved_at_20[0x10]; 8911 u8 op_mod[0x10]; 8912 8913 u8 reserved_at_40[0x20]; 8914 8915 u8 reserved_at_60[0x10]; 8916 u8 vxlan_udp_port[0x10]; 8917 }; 8918 8919 struct mlx5_ifc_set_pp_rate_limit_out_bits { 8920 u8 status[0x8]; 8921 u8 reserved_at_8[0x18]; 8922 8923 u8 syndrome[0x20]; 8924 8925 u8 reserved_at_40[0x40]; 8926 }; 8927 8928 struct mlx5_ifc_set_pp_rate_limit_context_bits { 8929 u8 rate_limit[0x20]; 8930 8931 u8 burst_upper_bound[0x20]; 8932 8933 u8 reserved_at_40[0x10]; 8934 u8 typical_packet_size[0x10]; 8935 8936 u8 reserved_at_60[0x120]; 8937 }; 8938 8939 struct mlx5_ifc_set_pp_rate_limit_in_bits { 8940 u8 opcode[0x10]; 8941 u8 uid[0x10]; 8942 8943 u8 reserved_at_20[0x10]; 8944 u8 op_mod[0x10]; 8945 8946 u8 reserved_at_40[0x10]; 8947 u8 rate_limit_index[0x10]; 8948 8949 u8 reserved_at_60[0x20]; 8950 8951 struct mlx5_ifc_set_pp_rate_limit_context_bits ctx; 8952 }; 8953 8954 struct mlx5_ifc_access_register_out_bits { 8955 u8 status[0x8]; 8956 u8 reserved_at_8[0x18]; 8957 8958 u8 syndrome[0x20]; 8959 8960 u8 reserved_at_40[0x40]; 8961 8962 u8 register_data[][0x20]; 8963 }; 8964 8965 enum { 8966 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0, 8967 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1, 8968 }; 8969 8970 struct mlx5_ifc_access_register_in_bits { 8971 u8 opcode[0x10]; 8972 u8 reserved_at_10[0x10]; 8973 8974 u8 reserved_at_20[0x10]; 8975 u8 op_mod[0x10]; 8976 8977 u8 reserved_at_40[0x10]; 8978 u8 register_id[0x10]; 8979 8980 u8 argument[0x20]; 8981 8982 u8 register_data[][0x20]; 8983 }; 8984 8985 struct mlx5_ifc_sltp_reg_bits { 8986 u8 status[0x4]; 8987 u8 version[0x4]; 8988 u8 local_port[0x8]; 8989 u8 pnat[0x2]; 8990 u8 reserved_at_12[0x2]; 8991 u8 lane[0x4]; 8992 u8 reserved_at_18[0x8]; 8993 8994 u8 reserved_at_20[0x20]; 8995 8996 u8 reserved_at_40[0x7]; 8997 u8 polarity[0x1]; 8998 u8 ob_tap0[0x8]; 8999 u8 ob_tap1[0x8]; 9000 u8 ob_tap2[0x8]; 9001 9002 u8 reserved_at_60[0xc]; 9003 u8 ob_preemp_mode[0x4]; 9004 u8 ob_reg[0x8]; 9005 u8 ob_bias[0x8]; 9006 9007 u8 reserved_at_80[0x20]; 9008 }; 9009 9010 struct mlx5_ifc_slrg_reg_bits { 9011 u8 status[0x4]; 9012 u8 version[0x4]; 9013 u8 local_port[0x8]; 9014 u8 pnat[0x2]; 9015 u8 reserved_at_12[0x2]; 9016 u8 lane[0x4]; 9017 u8 reserved_at_18[0x8]; 9018 9019 u8 time_to_link_up[0x10]; 9020 u8 reserved_at_30[0xc]; 9021 u8 grade_lane_speed[0x4]; 9022 9023 u8 grade_version[0x8]; 9024 u8 grade[0x18]; 9025 9026 u8 reserved_at_60[0x4]; 9027 u8 height_grade_type[0x4]; 9028 u8 height_grade[0x18]; 9029 9030 u8 height_dz[0x10]; 9031 u8 height_dv[0x10]; 9032 9033 u8 reserved_at_a0[0x10]; 9034 u8 height_sigma[0x10]; 9035 9036 u8 reserved_at_c0[0x20]; 9037 9038 u8 reserved_at_e0[0x4]; 9039 u8 phase_grade_type[0x4]; 9040 u8 phase_grade[0x18]; 9041 9042 u8 reserved_at_100[0x8]; 9043 u8 phase_eo_pos[0x8]; 9044 u8 reserved_at_110[0x8]; 9045 u8 phase_eo_neg[0x8]; 9046 9047 u8 ffe_set_tested[0x10]; 9048 u8 test_errors_per_lane[0x10]; 9049 }; 9050 9051 struct mlx5_ifc_pvlc_reg_bits { 9052 u8 reserved_at_0[0x8]; 9053 u8 local_port[0x8]; 9054 u8 reserved_at_10[0x10]; 9055 9056 u8 reserved_at_20[0x1c]; 9057 u8 vl_hw_cap[0x4]; 9058 9059 u8 reserved_at_40[0x1c]; 9060 u8 vl_admin[0x4]; 9061 9062 u8 reserved_at_60[0x1c]; 9063 u8 vl_operational[0x4]; 9064 }; 9065 9066 struct mlx5_ifc_pude_reg_bits { 9067 u8 swid[0x8]; 9068 u8 local_port[0x8]; 9069 u8 reserved_at_10[0x4]; 9070 u8 admin_status[0x4]; 9071 u8 reserved_at_18[0x4]; 9072 u8 oper_status[0x4]; 9073 9074 u8 reserved_at_20[0x60]; 9075 }; 9076 9077 struct mlx5_ifc_ptys_reg_bits { 9078 u8 reserved_at_0[0x1]; 9079 u8 an_disable_admin[0x1]; 9080 u8 an_disable_cap[0x1]; 9081 u8 reserved_at_3[0x5]; 9082 u8 local_port[0x8]; 9083 u8 reserved_at_10[0xd]; 9084 u8 proto_mask[0x3]; 9085 9086 u8 an_status[0x4]; 9087 u8 reserved_at_24[0xc]; 9088 u8 data_rate_oper[0x10]; 9089 9090 u8 ext_eth_proto_capability[0x20]; 9091 9092 u8 eth_proto_capability[0x20]; 9093 9094 u8 ib_link_width_capability[0x10]; 9095 u8 ib_proto_capability[0x10]; 9096 9097 u8 ext_eth_proto_admin[0x20]; 9098 9099 u8 eth_proto_admin[0x20]; 9100 9101 u8 ib_link_width_admin[0x10]; 9102 u8 ib_proto_admin[0x10]; 9103 9104 u8 ext_eth_proto_oper[0x20]; 9105 9106 u8 eth_proto_oper[0x20]; 9107 9108 u8 ib_link_width_oper[0x10]; 9109 u8 ib_proto_oper[0x10]; 9110 9111 u8 reserved_at_160[0x1c]; 9112 u8 connector_type[0x4]; 9113 9114 u8 eth_proto_lp_advertise[0x20]; 9115 9116 u8 reserved_at_1a0[0x60]; 9117 }; 9118 9119 struct mlx5_ifc_mlcr_reg_bits { 9120 u8 reserved_at_0[0x8]; 9121 u8 local_port[0x8]; 9122 u8 reserved_at_10[0x20]; 9123 9124 u8 beacon_duration[0x10]; 9125 u8 reserved_at_40[0x10]; 9126 9127 u8 beacon_remain[0x10]; 9128 }; 9129 9130 struct mlx5_ifc_ptas_reg_bits { 9131 u8 reserved_at_0[0x20]; 9132 9133 u8 algorithm_options[0x10]; 9134 u8 reserved_at_30[0x4]; 9135 u8 repetitions_mode[0x4]; 9136 u8 num_of_repetitions[0x8]; 9137 9138 u8 grade_version[0x8]; 9139 u8 height_grade_type[0x4]; 9140 u8 phase_grade_type[0x4]; 9141 u8 height_grade_weight[0x8]; 9142 u8 phase_grade_weight[0x8]; 9143 9144 u8 gisim_measure_bits[0x10]; 9145 u8 adaptive_tap_measure_bits[0x10]; 9146 9147 u8 ber_bath_high_error_threshold[0x10]; 9148 u8 ber_bath_mid_error_threshold[0x10]; 9149 9150 u8 ber_bath_low_error_threshold[0x10]; 9151 u8 one_ratio_high_threshold[0x10]; 9152 9153 u8 one_ratio_high_mid_threshold[0x10]; 9154 u8 one_ratio_low_mid_threshold[0x10]; 9155 9156 u8 one_ratio_low_threshold[0x10]; 9157 u8 ndeo_error_threshold[0x10]; 9158 9159 u8 mixer_offset_step_size[0x10]; 9160 u8 reserved_at_110[0x8]; 9161 u8 mix90_phase_for_voltage_bath[0x8]; 9162 9163 u8 mixer_offset_start[0x10]; 9164 u8 mixer_offset_end[0x10]; 9165 9166 u8 reserved_at_140[0x15]; 9167 u8 ber_test_time[0xb]; 9168 }; 9169 9170 struct mlx5_ifc_pspa_reg_bits { 9171 u8 swid[0x8]; 9172 u8 local_port[0x8]; 9173 u8 sub_port[0x8]; 9174 u8 reserved_at_18[0x8]; 9175 9176 u8 reserved_at_20[0x20]; 9177 }; 9178 9179 struct mlx5_ifc_pqdr_reg_bits { 9180 u8 reserved_at_0[0x8]; 9181 u8 local_port[0x8]; 9182 u8 reserved_at_10[0x5]; 9183 u8 prio[0x3]; 9184 u8 reserved_at_18[0x6]; 9185 u8 mode[0x2]; 9186 9187 u8 reserved_at_20[0x20]; 9188 9189 u8 reserved_at_40[0x10]; 9190 u8 min_threshold[0x10]; 9191 9192 u8 reserved_at_60[0x10]; 9193 u8 max_threshold[0x10]; 9194 9195 u8 reserved_at_80[0x10]; 9196 u8 mark_probability_denominator[0x10]; 9197 9198 u8 reserved_at_a0[0x60]; 9199 }; 9200 9201 struct mlx5_ifc_ppsc_reg_bits { 9202 u8 reserved_at_0[0x8]; 9203 u8 local_port[0x8]; 9204 u8 reserved_at_10[0x10]; 9205 9206 u8 reserved_at_20[0x60]; 9207 9208 u8 reserved_at_80[0x1c]; 9209 u8 wrps_admin[0x4]; 9210 9211 u8 reserved_at_a0[0x1c]; 9212 u8 wrps_status[0x4]; 9213 9214 u8 reserved_at_c0[0x8]; 9215 u8 up_threshold[0x8]; 9216 u8 reserved_at_d0[0x8]; 9217 u8 down_threshold[0x8]; 9218 9219 u8 reserved_at_e0[0x20]; 9220 9221 u8 reserved_at_100[0x1c]; 9222 u8 srps_admin[0x4]; 9223 9224 u8 reserved_at_120[0x1c]; 9225 u8 srps_status[0x4]; 9226 9227 u8 reserved_at_140[0x40]; 9228 }; 9229 9230 struct mlx5_ifc_pplr_reg_bits { 9231 u8 reserved_at_0[0x8]; 9232 u8 local_port[0x8]; 9233 u8 reserved_at_10[0x10]; 9234 9235 u8 reserved_at_20[0x8]; 9236 u8 lb_cap[0x8]; 9237 u8 reserved_at_30[0x8]; 9238 u8 lb_en[0x8]; 9239 }; 9240 9241 struct mlx5_ifc_pplm_reg_bits { 9242 u8 reserved_at_0[0x8]; 9243 u8 local_port[0x8]; 9244 u8 reserved_at_10[0x10]; 9245 9246 u8 reserved_at_20[0x20]; 9247 9248 u8 port_profile_mode[0x8]; 9249 u8 static_port_profile[0x8]; 9250 u8 active_port_profile[0x8]; 9251 u8 reserved_at_58[0x8]; 9252 9253 u8 retransmission_active[0x8]; 9254 u8 fec_mode_active[0x18]; 9255 9256 u8 rs_fec_correction_bypass_cap[0x4]; 9257 u8 reserved_at_84[0x8]; 9258 u8 fec_override_cap_56g[0x4]; 9259 u8 fec_override_cap_100g[0x4]; 9260 u8 fec_override_cap_50g[0x4]; 9261 u8 fec_override_cap_25g[0x4]; 9262 u8 fec_override_cap_10g_40g[0x4]; 9263 9264 u8 rs_fec_correction_bypass_admin[0x4]; 9265 u8 reserved_at_a4[0x8]; 9266 u8 fec_override_admin_56g[0x4]; 9267 u8 fec_override_admin_100g[0x4]; 9268 u8 fec_override_admin_50g[0x4]; 9269 u8 fec_override_admin_25g[0x4]; 9270 u8 fec_override_admin_10g_40g[0x4]; 9271 9272 u8 fec_override_cap_400g_8x[0x10]; 9273 u8 fec_override_cap_200g_4x[0x10]; 9274 9275 u8 fec_override_cap_100g_2x[0x10]; 9276 u8 fec_override_cap_50g_1x[0x10]; 9277 9278 u8 fec_override_admin_400g_8x[0x10]; 9279 u8 fec_override_admin_200g_4x[0x10]; 9280 9281 u8 fec_override_admin_100g_2x[0x10]; 9282 u8 fec_override_admin_50g_1x[0x10]; 9283 9284 u8 reserved_at_140[0x140]; 9285 }; 9286 9287 struct mlx5_ifc_ppcnt_reg_bits { 9288 u8 swid[0x8]; 9289 u8 local_port[0x8]; 9290 u8 pnat[0x2]; 9291 u8 reserved_at_12[0x8]; 9292 u8 grp[0x6]; 9293 9294 u8 clr[0x1]; 9295 u8 reserved_at_21[0x1c]; 9296 u8 prio_tc[0x3]; 9297 9298 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set; 9299 }; 9300 9301 struct mlx5_ifc_mpein_reg_bits { 9302 u8 reserved_at_0[0x2]; 9303 u8 depth[0x6]; 9304 u8 pcie_index[0x8]; 9305 u8 node[0x8]; 9306 u8 reserved_at_18[0x8]; 9307 9308 u8 capability_mask[0x20]; 9309 9310 u8 reserved_at_40[0x8]; 9311 u8 link_width_enabled[0x8]; 9312 u8 link_speed_enabled[0x10]; 9313 9314 u8 lane0_physical_position[0x8]; 9315 u8 link_width_active[0x8]; 9316 u8 link_speed_active[0x10]; 9317 9318 u8 num_of_pfs[0x10]; 9319 u8 num_of_vfs[0x10]; 9320 9321 u8 bdf0[0x10]; 9322 u8 reserved_at_b0[0x10]; 9323 9324 u8 max_read_request_size[0x4]; 9325 u8 max_payload_size[0x4]; 9326 u8 reserved_at_c8[0x5]; 9327 u8 pwr_status[0x3]; 9328 u8 port_type[0x4]; 9329 u8 reserved_at_d4[0xb]; 9330 u8 lane_reversal[0x1]; 9331 9332 u8 reserved_at_e0[0x14]; 9333 u8 pci_power[0xc]; 9334 9335 u8 reserved_at_100[0x20]; 9336 9337 u8 device_status[0x10]; 9338 u8 port_state[0x8]; 9339 u8 reserved_at_138[0x8]; 9340 9341 u8 reserved_at_140[0x10]; 9342 u8 receiver_detect_result[0x10]; 9343 9344 u8 reserved_at_160[0x20]; 9345 }; 9346 9347 struct mlx5_ifc_mpcnt_reg_bits { 9348 u8 reserved_at_0[0x8]; 9349 u8 pcie_index[0x8]; 9350 u8 reserved_at_10[0xa]; 9351 u8 grp[0x6]; 9352 9353 u8 clr[0x1]; 9354 u8 reserved_at_21[0x1f]; 9355 9356 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set; 9357 }; 9358 9359 struct mlx5_ifc_ppad_reg_bits { 9360 u8 reserved_at_0[0x3]; 9361 u8 single_mac[0x1]; 9362 u8 reserved_at_4[0x4]; 9363 u8 local_port[0x8]; 9364 u8 mac_47_32[0x10]; 9365 9366 u8 mac_31_0[0x20]; 9367 9368 u8 reserved_at_40[0x40]; 9369 }; 9370 9371 struct mlx5_ifc_pmtu_reg_bits { 9372 u8 reserved_at_0[0x8]; 9373 u8 local_port[0x8]; 9374 u8 reserved_at_10[0x10]; 9375 9376 u8 max_mtu[0x10]; 9377 u8 reserved_at_30[0x10]; 9378 9379 u8 admin_mtu[0x10]; 9380 u8 reserved_at_50[0x10]; 9381 9382 u8 oper_mtu[0x10]; 9383 u8 reserved_at_70[0x10]; 9384 }; 9385 9386 struct mlx5_ifc_pmpr_reg_bits { 9387 u8 reserved_at_0[0x8]; 9388 u8 module[0x8]; 9389 u8 reserved_at_10[0x10]; 9390 9391 u8 reserved_at_20[0x18]; 9392 u8 attenuation_5g[0x8]; 9393 9394 u8 reserved_at_40[0x18]; 9395 u8 attenuation_7g[0x8]; 9396 9397 u8 reserved_at_60[0x18]; 9398 u8 attenuation_12g[0x8]; 9399 }; 9400 9401 struct mlx5_ifc_pmpe_reg_bits { 9402 u8 reserved_at_0[0x8]; 9403 u8 module[0x8]; 9404 u8 reserved_at_10[0xc]; 9405 u8 module_status[0x4]; 9406 9407 u8 reserved_at_20[0x60]; 9408 }; 9409 9410 struct mlx5_ifc_pmpc_reg_bits { 9411 u8 module_state_updated[32][0x8]; 9412 }; 9413 9414 struct mlx5_ifc_pmlpn_reg_bits { 9415 u8 reserved_at_0[0x4]; 9416 u8 mlpn_status[0x4]; 9417 u8 local_port[0x8]; 9418 u8 reserved_at_10[0x10]; 9419 9420 u8 e[0x1]; 9421 u8 reserved_at_21[0x1f]; 9422 }; 9423 9424 struct mlx5_ifc_pmlp_reg_bits { 9425 u8 rxtx[0x1]; 9426 u8 reserved_at_1[0x7]; 9427 u8 local_port[0x8]; 9428 u8 reserved_at_10[0x8]; 9429 u8 width[0x8]; 9430 9431 u8 lane0_module_mapping[0x20]; 9432 9433 u8 lane1_module_mapping[0x20]; 9434 9435 u8 lane2_module_mapping[0x20]; 9436 9437 u8 lane3_module_mapping[0x20]; 9438 9439 u8 reserved_at_a0[0x160]; 9440 }; 9441 9442 struct mlx5_ifc_pmaos_reg_bits { 9443 u8 reserved_at_0[0x8]; 9444 u8 module[0x8]; 9445 u8 reserved_at_10[0x4]; 9446 u8 admin_status[0x4]; 9447 u8 reserved_at_18[0x4]; 9448 u8 oper_status[0x4]; 9449 9450 u8 ase[0x1]; 9451 u8 ee[0x1]; 9452 u8 reserved_at_22[0x1c]; 9453 u8 e[0x2]; 9454 9455 u8 reserved_at_40[0x40]; 9456 }; 9457 9458 struct mlx5_ifc_plpc_reg_bits { 9459 u8 reserved_at_0[0x4]; 9460 u8 profile_id[0xc]; 9461 u8 reserved_at_10[0x4]; 9462 u8 proto_mask[0x4]; 9463 u8 reserved_at_18[0x8]; 9464 9465 u8 reserved_at_20[0x10]; 9466 u8 lane_speed[0x10]; 9467 9468 u8 reserved_at_40[0x17]; 9469 u8 lpbf[0x1]; 9470 u8 fec_mode_policy[0x8]; 9471 9472 u8 retransmission_capability[0x8]; 9473 u8 fec_mode_capability[0x18]; 9474 9475 u8 retransmission_support_admin[0x8]; 9476 u8 fec_mode_support_admin[0x18]; 9477 9478 u8 retransmission_request_admin[0x8]; 9479 u8 fec_mode_request_admin[0x18]; 9480 9481 u8 reserved_at_c0[0x80]; 9482 }; 9483 9484 struct mlx5_ifc_plib_reg_bits { 9485 u8 reserved_at_0[0x8]; 9486 u8 local_port[0x8]; 9487 u8 reserved_at_10[0x8]; 9488 u8 ib_port[0x8]; 9489 9490 u8 reserved_at_20[0x60]; 9491 }; 9492 9493 struct mlx5_ifc_plbf_reg_bits { 9494 u8 reserved_at_0[0x8]; 9495 u8 local_port[0x8]; 9496 u8 reserved_at_10[0xd]; 9497 u8 lbf_mode[0x3]; 9498 9499 u8 reserved_at_20[0x20]; 9500 }; 9501 9502 struct mlx5_ifc_pipg_reg_bits { 9503 u8 reserved_at_0[0x8]; 9504 u8 local_port[0x8]; 9505 u8 reserved_at_10[0x10]; 9506 9507 u8 dic[0x1]; 9508 u8 reserved_at_21[0x19]; 9509 u8 ipg[0x4]; 9510 u8 reserved_at_3e[0x2]; 9511 }; 9512 9513 struct mlx5_ifc_pifr_reg_bits { 9514 u8 reserved_at_0[0x8]; 9515 u8 local_port[0x8]; 9516 u8 reserved_at_10[0x10]; 9517 9518 u8 reserved_at_20[0xe0]; 9519 9520 u8 port_filter[8][0x20]; 9521 9522 u8 port_filter_update_en[8][0x20]; 9523 }; 9524 9525 struct mlx5_ifc_pfcc_reg_bits { 9526 u8 reserved_at_0[0x8]; 9527 u8 local_port[0x8]; 9528 u8 reserved_at_10[0xb]; 9529 u8 ppan_mask_n[0x1]; 9530 u8 minor_stall_mask[0x1]; 9531 u8 critical_stall_mask[0x1]; 9532 u8 reserved_at_1e[0x2]; 9533 9534 u8 ppan[0x4]; 9535 u8 reserved_at_24[0x4]; 9536 u8 prio_mask_tx[0x8]; 9537 u8 reserved_at_30[0x8]; 9538 u8 prio_mask_rx[0x8]; 9539 9540 u8 pptx[0x1]; 9541 u8 aptx[0x1]; 9542 u8 pptx_mask_n[0x1]; 9543 u8 reserved_at_43[0x5]; 9544 u8 pfctx[0x8]; 9545 u8 reserved_at_50[0x10]; 9546 9547 u8 pprx[0x1]; 9548 u8 aprx[0x1]; 9549 u8 pprx_mask_n[0x1]; 9550 u8 reserved_at_63[0x5]; 9551 u8 pfcrx[0x8]; 9552 u8 reserved_at_70[0x10]; 9553 9554 u8 device_stall_minor_watermark[0x10]; 9555 u8 device_stall_critical_watermark[0x10]; 9556 9557 u8 reserved_at_a0[0x60]; 9558 }; 9559 9560 struct mlx5_ifc_pelc_reg_bits { 9561 u8 op[0x4]; 9562 u8 reserved_at_4[0x4]; 9563 u8 local_port[0x8]; 9564 u8 reserved_at_10[0x10]; 9565 9566 u8 op_admin[0x8]; 9567 u8 op_capability[0x8]; 9568 u8 op_request[0x8]; 9569 u8 op_active[0x8]; 9570 9571 u8 admin[0x40]; 9572 9573 u8 capability[0x40]; 9574 9575 u8 request[0x40]; 9576 9577 u8 active[0x40]; 9578 9579 u8 reserved_at_140[0x80]; 9580 }; 9581 9582 struct mlx5_ifc_peir_reg_bits { 9583 u8 reserved_at_0[0x8]; 9584 u8 local_port[0x8]; 9585 u8 reserved_at_10[0x10]; 9586 9587 u8 reserved_at_20[0xc]; 9588 u8 error_count[0x4]; 9589 u8 reserved_at_30[0x10]; 9590 9591 u8 reserved_at_40[0xc]; 9592 u8 lane[0x4]; 9593 u8 reserved_at_50[0x8]; 9594 u8 error_type[0x8]; 9595 }; 9596 9597 struct mlx5_ifc_mpegc_reg_bits { 9598 u8 reserved_at_0[0x30]; 9599 u8 field_select[0x10]; 9600 9601 u8 tx_overflow_sense[0x1]; 9602 u8 mark_cqe[0x1]; 9603 u8 mark_cnp[0x1]; 9604 u8 reserved_at_43[0x1b]; 9605 u8 tx_lossy_overflow_oper[0x2]; 9606 9607 u8 reserved_at_60[0x100]; 9608 }; 9609 9610 enum { 9611 MLX5_MTUTC_OPERATION_SET_TIME_IMMEDIATE = 0x1, 9612 MLX5_MTUTC_OPERATION_ADJUST_TIME = 0x2, 9613 MLX5_MTUTC_OPERATION_ADJUST_FREQ_UTC = 0x3, 9614 }; 9615 9616 struct mlx5_ifc_mtutc_reg_bits { 9617 u8 reserved_at_0[0x1c]; 9618 u8 operation[0x4]; 9619 9620 u8 freq_adjustment[0x20]; 9621 9622 u8 reserved_at_40[0x40]; 9623 9624 u8 utc_sec[0x20]; 9625 9626 u8 reserved_at_a0[0x2]; 9627 u8 utc_nsec[0x1e]; 9628 9629 u8 time_adjustment[0x20]; 9630 }; 9631 9632 struct mlx5_ifc_pcam_enhanced_features_bits { 9633 u8 reserved_at_0[0x68]; 9634 u8 fec_50G_per_lane_in_pplm[0x1]; 9635 u8 reserved_at_69[0x4]; 9636 u8 rx_icrc_encapsulated_counter[0x1]; 9637 u8 reserved_at_6e[0x4]; 9638 u8 ptys_extended_ethernet[0x1]; 9639 u8 reserved_at_73[0x3]; 9640 u8 pfcc_mask[0x1]; 9641 u8 reserved_at_77[0x3]; 9642 u8 per_lane_error_counters[0x1]; 9643 u8 rx_buffer_fullness_counters[0x1]; 9644 u8 ptys_connector_type[0x1]; 9645 u8 reserved_at_7d[0x1]; 9646 u8 ppcnt_discard_group[0x1]; 9647 u8 ppcnt_statistical_group[0x1]; 9648 }; 9649 9650 struct mlx5_ifc_pcam_regs_5000_to_507f_bits { 9651 u8 port_access_reg_cap_mask_127_to_96[0x20]; 9652 u8 port_access_reg_cap_mask_95_to_64[0x20]; 9653 9654 u8 port_access_reg_cap_mask_63_to_36[0x1c]; 9655 u8 pplm[0x1]; 9656 u8 port_access_reg_cap_mask_34_to_32[0x3]; 9657 9658 u8 port_access_reg_cap_mask_31_to_13[0x13]; 9659 u8 pbmc[0x1]; 9660 u8 pptb[0x1]; 9661 u8 port_access_reg_cap_mask_10_to_09[0x2]; 9662 u8 ppcnt[0x1]; 9663 u8 port_access_reg_cap_mask_07_to_00[0x8]; 9664 }; 9665 9666 struct mlx5_ifc_pcam_reg_bits { 9667 u8 reserved_at_0[0x8]; 9668 u8 feature_group[0x8]; 9669 u8 reserved_at_10[0x8]; 9670 u8 access_reg_group[0x8]; 9671 9672 u8 reserved_at_20[0x20]; 9673 9674 union { 9675 struct mlx5_ifc_pcam_regs_5000_to_507f_bits regs_5000_to_507f; 9676 u8 reserved_at_0[0x80]; 9677 } port_access_reg_cap_mask; 9678 9679 u8 reserved_at_c0[0x80]; 9680 9681 union { 9682 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features; 9683 u8 reserved_at_0[0x80]; 9684 } feature_cap_mask; 9685 9686 u8 reserved_at_1c0[0xc0]; 9687 }; 9688 9689 struct mlx5_ifc_mcam_enhanced_features_bits { 9690 u8 reserved_at_0[0x6b]; 9691 u8 ptpcyc2realtime_modify[0x1]; 9692 u8 reserved_at_6c[0x2]; 9693 u8 pci_status_and_power[0x1]; 9694 u8 reserved_at_6f[0x5]; 9695 u8 mark_tx_action_cnp[0x1]; 9696 u8 mark_tx_action_cqe[0x1]; 9697 u8 dynamic_tx_overflow[0x1]; 9698 u8 reserved_at_77[0x4]; 9699 u8 pcie_outbound_stalled[0x1]; 9700 u8 tx_overflow_buffer_pkt[0x1]; 9701 u8 mtpps_enh_out_per_adj[0x1]; 9702 u8 mtpps_fs[0x1]; 9703 u8 pcie_performance_group[0x1]; 9704 }; 9705 9706 struct mlx5_ifc_mcam_access_reg_bits { 9707 u8 reserved_at_0[0x1c]; 9708 u8 mcda[0x1]; 9709 u8 mcc[0x1]; 9710 u8 mcqi[0x1]; 9711 u8 mcqs[0x1]; 9712 9713 u8 regs_95_to_87[0x9]; 9714 u8 mpegc[0x1]; 9715 u8 mtutc[0x1]; 9716 u8 regs_84_to_68[0x11]; 9717 u8 tracer_registers[0x4]; 9718 9719 u8 regs_63_to_46[0x12]; 9720 u8 mrtc[0x1]; 9721 u8 regs_44_to_32[0xd]; 9722 9723 u8 regs_31_to_0[0x20]; 9724 }; 9725 9726 struct mlx5_ifc_mcam_access_reg_bits1 { 9727 u8 regs_127_to_96[0x20]; 9728 9729 u8 regs_95_to_64[0x20]; 9730 9731 u8 regs_63_to_32[0x20]; 9732 9733 u8 regs_31_to_0[0x20]; 9734 }; 9735 9736 struct mlx5_ifc_mcam_access_reg_bits2 { 9737 u8 regs_127_to_99[0x1d]; 9738 u8 mirc[0x1]; 9739 u8 regs_97_to_96[0x2]; 9740 9741 u8 regs_95_to_64[0x20]; 9742 9743 u8 regs_63_to_32[0x20]; 9744 9745 u8 regs_31_to_0[0x20]; 9746 }; 9747 9748 struct mlx5_ifc_mcam_reg_bits { 9749 u8 reserved_at_0[0x8]; 9750 u8 feature_group[0x8]; 9751 u8 reserved_at_10[0x8]; 9752 u8 access_reg_group[0x8]; 9753 9754 u8 reserved_at_20[0x20]; 9755 9756 union { 9757 struct mlx5_ifc_mcam_access_reg_bits access_regs; 9758 struct mlx5_ifc_mcam_access_reg_bits1 access_regs1; 9759 struct mlx5_ifc_mcam_access_reg_bits2 access_regs2; 9760 u8 reserved_at_0[0x80]; 9761 } mng_access_reg_cap_mask; 9762 9763 u8 reserved_at_c0[0x80]; 9764 9765 union { 9766 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features; 9767 u8 reserved_at_0[0x80]; 9768 } mng_feature_cap_mask; 9769 9770 u8 reserved_at_1c0[0x80]; 9771 }; 9772 9773 struct mlx5_ifc_qcam_access_reg_cap_mask { 9774 u8 qcam_access_reg_cap_mask_127_to_20[0x6C]; 9775 u8 qpdpm[0x1]; 9776 u8 qcam_access_reg_cap_mask_18_to_4[0x0F]; 9777 u8 qdpm[0x1]; 9778 u8 qpts[0x1]; 9779 u8 qcap[0x1]; 9780 u8 qcam_access_reg_cap_mask_0[0x1]; 9781 }; 9782 9783 struct mlx5_ifc_qcam_qos_feature_cap_mask { 9784 u8 qcam_qos_feature_cap_mask_127_to_1[0x7F]; 9785 u8 qpts_trust_both[0x1]; 9786 }; 9787 9788 struct mlx5_ifc_qcam_reg_bits { 9789 u8 reserved_at_0[0x8]; 9790 u8 feature_group[0x8]; 9791 u8 reserved_at_10[0x8]; 9792 u8 access_reg_group[0x8]; 9793 u8 reserved_at_20[0x20]; 9794 9795 union { 9796 struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap; 9797 u8 reserved_at_0[0x80]; 9798 } qos_access_reg_cap_mask; 9799 9800 u8 reserved_at_c0[0x80]; 9801 9802 union { 9803 struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap; 9804 u8 reserved_at_0[0x80]; 9805 } qos_feature_cap_mask; 9806 9807 u8 reserved_at_1c0[0x80]; 9808 }; 9809 9810 struct mlx5_ifc_core_dump_reg_bits { 9811 u8 reserved_at_0[0x18]; 9812 u8 core_dump_type[0x8]; 9813 9814 u8 reserved_at_20[0x30]; 9815 u8 vhca_id[0x10]; 9816 9817 u8 reserved_at_60[0x8]; 9818 u8 qpn[0x18]; 9819 u8 reserved_at_80[0x180]; 9820 }; 9821 9822 struct mlx5_ifc_pcap_reg_bits { 9823 u8 reserved_at_0[0x8]; 9824 u8 local_port[0x8]; 9825 u8 reserved_at_10[0x10]; 9826 9827 u8 port_capability_mask[4][0x20]; 9828 }; 9829 9830 struct mlx5_ifc_paos_reg_bits { 9831 u8 swid[0x8]; 9832 u8 local_port[0x8]; 9833 u8 reserved_at_10[0x4]; 9834 u8 admin_status[0x4]; 9835 u8 reserved_at_18[0x4]; 9836 u8 oper_status[0x4]; 9837 9838 u8 ase[0x1]; 9839 u8 ee[0x1]; 9840 u8 reserved_at_22[0x1c]; 9841 u8 e[0x2]; 9842 9843 u8 reserved_at_40[0x40]; 9844 }; 9845 9846 struct mlx5_ifc_pamp_reg_bits { 9847 u8 reserved_at_0[0x8]; 9848 u8 opamp_group[0x8]; 9849 u8 reserved_at_10[0xc]; 9850 u8 opamp_group_type[0x4]; 9851 9852 u8 start_index[0x10]; 9853 u8 reserved_at_30[0x4]; 9854 u8 num_of_indices[0xc]; 9855 9856 u8 index_data[18][0x10]; 9857 }; 9858 9859 struct mlx5_ifc_pcmr_reg_bits { 9860 u8 reserved_at_0[0x8]; 9861 u8 local_port[0x8]; 9862 u8 reserved_at_10[0x10]; 9863 9864 u8 entropy_force_cap[0x1]; 9865 u8 entropy_calc_cap[0x1]; 9866 u8 entropy_gre_calc_cap[0x1]; 9867 u8 reserved_at_23[0xf]; 9868 u8 rx_ts_over_crc_cap[0x1]; 9869 u8 reserved_at_33[0xb]; 9870 u8 fcs_cap[0x1]; 9871 u8 reserved_at_3f[0x1]; 9872 9873 u8 entropy_force[0x1]; 9874 u8 entropy_calc[0x1]; 9875 u8 entropy_gre_calc[0x1]; 9876 u8 reserved_at_43[0xf]; 9877 u8 rx_ts_over_crc[0x1]; 9878 u8 reserved_at_53[0xb]; 9879 u8 fcs_chk[0x1]; 9880 u8 reserved_at_5f[0x1]; 9881 }; 9882 9883 struct mlx5_ifc_lane_2_module_mapping_bits { 9884 u8 reserved_at_0[0x6]; 9885 u8 rx_lane[0x2]; 9886 u8 reserved_at_8[0x6]; 9887 u8 tx_lane[0x2]; 9888 u8 reserved_at_10[0x8]; 9889 u8 module[0x8]; 9890 }; 9891 9892 struct mlx5_ifc_bufferx_reg_bits { 9893 u8 reserved_at_0[0x6]; 9894 u8 lossy[0x1]; 9895 u8 epsb[0x1]; 9896 u8 reserved_at_8[0xc]; 9897 u8 size[0xc]; 9898 9899 u8 xoff_threshold[0x10]; 9900 u8 xon_threshold[0x10]; 9901 }; 9902 9903 struct mlx5_ifc_set_node_in_bits { 9904 u8 node_description[64][0x8]; 9905 }; 9906 9907 struct mlx5_ifc_register_power_settings_bits { 9908 u8 reserved_at_0[0x18]; 9909 u8 power_settings_level[0x8]; 9910 9911 u8 reserved_at_20[0x60]; 9912 }; 9913 9914 struct mlx5_ifc_register_host_endianness_bits { 9915 u8 he[0x1]; 9916 u8 reserved_at_1[0x1f]; 9917 9918 u8 reserved_at_20[0x60]; 9919 }; 9920 9921 struct mlx5_ifc_umr_pointer_desc_argument_bits { 9922 u8 reserved_at_0[0x20]; 9923 9924 u8 mkey[0x20]; 9925 9926 u8 addressh_63_32[0x20]; 9927 9928 u8 addressl_31_0[0x20]; 9929 }; 9930 9931 struct mlx5_ifc_ud_adrs_vector_bits { 9932 u8 dc_key[0x40]; 9933 9934 u8 ext[0x1]; 9935 u8 reserved_at_41[0x7]; 9936 u8 destination_qp_dct[0x18]; 9937 9938 u8 static_rate[0x4]; 9939 u8 sl_eth_prio[0x4]; 9940 u8 fl[0x1]; 9941 u8 mlid[0x7]; 9942 u8 rlid_udp_sport[0x10]; 9943 9944 u8 reserved_at_80[0x20]; 9945 9946 u8 rmac_47_16[0x20]; 9947 9948 u8 rmac_15_0[0x10]; 9949 u8 tclass[0x8]; 9950 u8 hop_limit[0x8]; 9951 9952 u8 reserved_at_e0[0x1]; 9953 u8 grh[0x1]; 9954 u8 reserved_at_e2[0x2]; 9955 u8 src_addr_index[0x8]; 9956 u8 flow_label[0x14]; 9957 9958 u8 rgid_rip[16][0x8]; 9959 }; 9960 9961 struct mlx5_ifc_pages_req_event_bits { 9962 u8 reserved_at_0[0x10]; 9963 u8 function_id[0x10]; 9964 9965 u8 num_pages[0x20]; 9966 9967 u8 reserved_at_40[0xa0]; 9968 }; 9969 9970 struct mlx5_ifc_eqe_bits { 9971 u8 reserved_at_0[0x8]; 9972 u8 event_type[0x8]; 9973 u8 reserved_at_10[0x8]; 9974 u8 event_sub_type[0x8]; 9975 9976 u8 reserved_at_20[0xe0]; 9977 9978 union mlx5_ifc_event_auto_bits event_data; 9979 9980 u8 reserved_at_1e0[0x10]; 9981 u8 signature[0x8]; 9982 u8 reserved_at_1f8[0x7]; 9983 u8 owner[0x1]; 9984 }; 9985 9986 enum { 9987 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7, 9988 }; 9989 9990 struct mlx5_ifc_cmd_queue_entry_bits { 9991 u8 type[0x8]; 9992 u8 reserved_at_8[0x18]; 9993 9994 u8 input_length[0x20]; 9995 9996 u8 input_mailbox_pointer_63_32[0x20]; 9997 9998 u8 input_mailbox_pointer_31_9[0x17]; 9999 u8 reserved_at_77[0x9]; 10000 10001 u8 command_input_inline_data[16][0x8]; 10002 10003 u8 command_output_inline_data[16][0x8]; 10004 10005 u8 output_mailbox_pointer_63_32[0x20]; 10006 10007 u8 output_mailbox_pointer_31_9[0x17]; 10008 u8 reserved_at_1b7[0x9]; 10009 10010 u8 output_length[0x20]; 10011 10012 u8 token[0x8]; 10013 u8 signature[0x8]; 10014 u8 reserved_at_1f0[0x8]; 10015 u8 status[0x7]; 10016 u8 ownership[0x1]; 10017 }; 10018 10019 struct mlx5_ifc_cmd_out_bits { 10020 u8 status[0x8]; 10021 u8 reserved_at_8[0x18]; 10022 10023 u8 syndrome[0x20]; 10024 10025 u8 command_output[0x20]; 10026 }; 10027 10028 struct mlx5_ifc_cmd_in_bits { 10029 u8 opcode[0x10]; 10030 u8 reserved_at_10[0x10]; 10031 10032 u8 reserved_at_20[0x10]; 10033 u8 op_mod[0x10]; 10034 10035 u8 command[][0x20]; 10036 }; 10037 10038 struct mlx5_ifc_cmd_if_box_bits { 10039 u8 mailbox_data[512][0x8]; 10040 10041 u8 reserved_at_1000[0x180]; 10042 10043 u8 next_pointer_63_32[0x20]; 10044 10045 u8 next_pointer_31_10[0x16]; 10046 u8 reserved_at_11b6[0xa]; 10047 10048 u8 block_number[0x20]; 10049 10050 u8 reserved_at_11e0[0x8]; 10051 u8 token[0x8]; 10052 u8 ctrl_signature[0x8]; 10053 u8 signature[0x8]; 10054 }; 10055 10056 struct mlx5_ifc_mtt_bits { 10057 u8 ptag_63_32[0x20]; 10058 10059 u8 ptag_31_8[0x18]; 10060 u8 reserved_at_38[0x6]; 10061 u8 wr_en[0x1]; 10062 u8 rd_en[0x1]; 10063 }; 10064 10065 struct mlx5_ifc_query_wol_rol_out_bits { 10066 u8 status[0x8]; 10067 u8 reserved_at_8[0x18]; 10068 10069 u8 syndrome[0x20]; 10070 10071 u8 reserved_at_40[0x10]; 10072 u8 rol_mode[0x8]; 10073 u8 wol_mode[0x8]; 10074 10075 u8 reserved_at_60[0x20]; 10076 }; 10077 10078 struct mlx5_ifc_query_wol_rol_in_bits { 10079 u8 opcode[0x10]; 10080 u8 reserved_at_10[0x10]; 10081 10082 u8 reserved_at_20[0x10]; 10083 u8 op_mod[0x10]; 10084 10085 u8 reserved_at_40[0x40]; 10086 }; 10087 10088 struct mlx5_ifc_set_wol_rol_out_bits { 10089 u8 status[0x8]; 10090 u8 reserved_at_8[0x18]; 10091 10092 u8 syndrome[0x20]; 10093 10094 u8 reserved_at_40[0x40]; 10095 }; 10096 10097 struct mlx5_ifc_set_wol_rol_in_bits { 10098 u8 opcode[0x10]; 10099 u8 reserved_at_10[0x10]; 10100 10101 u8 reserved_at_20[0x10]; 10102 u8 op_mod[0x10]; 10103 10104 u8 rol_mode_valid[0x1]; 10105 u8 wol_mode_valid[0x1]; 10106 u8 reserved_at_42[0xe]; 10107 u8 rol_mode[0x8]; 10108 u8 wol_mode[0x8]; 10109 10110 u8 reserved_at_60[0x20]; 10111 }; 10112 10113 enum { 10114 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0, 10115 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1, 10116 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2, 10117 }; 10118 10119 enum { 10120 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0, 10121 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1, 10122 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2, 10123 }; 10124 10125 enum { 10126 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR = 0x1, 10127 MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC = 0x7, 10128 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR = 0x8, 10129 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR = 0x9, 10130 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR = 0xa, 10131 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR = 0xb, 10132 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN = 0xc, 10133 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR = 0xd, 10134 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV = 0xe, 10135 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR = 0xf, 10136 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR = 0x10, 10137 }; 10138 10139 struct mlx5_ifc_initial_seg_bits { 10140 u8 fw_rev_minor[0x10]; 10141 u8 fw_rev_major[0x10]; 10142 10143 u8 cmd_interface_rev[0x10]; 10144 u8 fw_rev_subminor[0x10]; 10145 10146 u8 reserved_at_40[0x40]; 10147 10148 u8 cmdq_phy_addr_63_32[0x20]; 10149 10150 u8 cmdq_phy_addr_31_12[0x14]; 10151 u8 reserved_at_b4[0x2]; 10152 u8 nic_interface[0x2]; 10153 u8 log_cmdq_size[0x4]; 10154 u8 log_cmdq_stride[0x4]; 10155 10156 u8 command_doorbell_vector[0x20]; 10157 10158 u8 reserved_at_e0[0xf00]; 10159 10160 u8 initializing[0x1]; 10161 u8 reserved_at_fe1[0x4]; 10162 u8 nic_interface_supported[0x3]; 10163 u8 embedded_cpu[0x1]; 10164 u8 reserved_at_fe9[0x17]; 10165 10166 struct mlx5_ifc_health_buffer_bits health_buffer; 10167 10168 u8 no_dram_nic_offset[0x20]; 10169 10170 u8 reserved_at_1220[0x6e40]; 10171 10172 u8 reserved_at_8060[0x1f]; 10173 u8 clear_int[0x1]; 10174 10175 u8 health_syndrome[0x8]; 10176 u8 health_counter[0x18]; 10177 10178 u8 reserved_at_80a0[0x17fc0]; 10179 }; 10180 10181 struct mlx5_ifc_mtpps_reg_bits { 10182 u8 reserved_at_0[0xc]; 10183 u8 cap_number_of_pps_pins[0x4]; 10184 u8 reserved_at_10[0x4]; 10185 u8 cap_max_num_of_pps_in_pins[0x4]; 10186 u8 reserved_at_18[0x4]; 10187 u8 cap_max_num_of_pps_out_pins[0x4]; 10188 10189 u8 reserved_at_20[0x24]; 10190 u8 cap_pin_3_mode[0x4]; 10191 u8 reserved_at_48[0x4]; 10192 u8 cap_pin_2_mode[0x4]; 10193 u8 reserved_at_50[0x4]; 10194 u8 cap_pin_1_mode[0x4]; 10195 u8 reserved_at_58[0x4]; 10196 u8 cap_pin_0_mode[0x4]; 10197 10198 u8 reserved_at_60[0x4]; 10199 u8 cap_pin_7_mode[0x4]; 10200 u8 reserved_at_68[0x4]; 10201 u8 cap_pin_6_mode[0x4]; 10202 u8 reserved_at_70[0x4]; 10203 u8 cap_pin_5_mode[0x4]; 10204 u8 reserved_at_78[0x4]; 10205 u8 cap_pin_4_mode[0x4]; 10206 10207 u8 field_select[0x20]; 10208 u8 reserved_at_a0[0x60]; 10209 10210 u8 enable[0x1]; 10211 u8 reserved_at_101[0xb]; 10212 u8 pattern[0x4]; 10213 u8 reserved_at_110[0x4]; 10214 u8 pin_mode[0x4]; 10215 u8 pin[0x8]; 10216 10217 u8 reserved_at_120[0x20]; 10218 10219 u8 time_stamp[0x40]; 10220 10221 u8 out_pulse_duration[0x10]; 10222 u8 out_periodic_adjustment[0x10]; 10223 u8 enhanced_out_periodic_adjustment[0x20]; 10224 10225 u8 reserved_at_1c0[0x20]; 10226 }; 10227 10228 struct mlx5_ifc_mtppse_reg_bits { 10229 u8 reserved_at_0[0x18]; 10230 u8 pin[0x8]; 10231 u8 event_arm[0x1]; 10232 u8 reserved_at_21[0x1b]; 10233 u8 event_generation_mode[0x4]; 10234 u8 reserved_at_40[0x40]; 10235 }; 10236 10237 struct mlx5_ifc_mcqs_reg_bits { 10238 u8 last_index_flag[0x1]; 10239 u8 reserved_at_1[0x7]; 10240 u8 fw_device[0x8]; 10241 u8 component_index[0x10]; 10242 10243 u8 reserved_at_20[0x10]; 10244 u8 identifier[0x10]; 10245 10246 u8 reserved_at_40[0x17]; 10247 u8 component_status[0x5]; 10248 u8 component_update_state[0x4]; 10249 10250 u8 last_update_state_changer_type[0x4]; 10251 u8 last_update_state_changer_host_id[0x4]; 10252 u8 reserved_at_68[0x18]; 10253 }; 10254 10255 struct mlx5_ifc_mcqi_cap_bits { 10256 u8 supported_info_bitmask[0x20]; 10257 10258 u8 component_size[0x20]; 10259 10260 u8 max_component_size[0x20]; 10261 10262 u8 log_mcda_word_size[0x4]; 10263 u8 reserved_at_64[0xc]; 10264 u8 mcda_max_write_size[0x10]; 10265 10266 u8 rd_en[0x1]; 10267 u8 reserved_at_81[0x1]; 10268 u8 match_chip_id[0x1]; 10269 u8 match_psid[0x1]; 10270 u8 check_user_timestamp[0x1]; 10271 u8 match_base_guid_mac[0x1]; 10272 u8 reserved_at_86[0x1a]; 10273 }; 10274 10275 struct mlx5_ifc_mcqi_version_bits { 10276 u8 reserved_at_0[0x2]; 10277 u8 build_time_valid[0x1]; 10278 u8 user_defined_time_valid[0x1]; 10279 u8 reserved_at_4[0x14]; 10280 u8 version_string_length[0x8]; 10281 10282 u8 version[0x20]; 10283 10284 u8 build_time[0x40]; 10285 10286 u8 user_defined_time[0x40]; 10287 10288 u8 build_tool_version[0x20]; 10289 10290 u8 reserved_at_e0[0x20]; 10291 10292 u8 version_string[92][0x8]; 10293 }; 10294 10295 struct mlx5_ifc_mcqi_activation_method_bits { 10296 u8 pending_server_ac_power_cycle[0x1]; 10297 u8 pending_server_dc_power_cycle[0x1]; 10298 u8 pending_server_reboot[0x1]; 10299 u8 pending_fw_reset[0x1]; 10300 u8 auto_activate[0x1]; 10301 u8 all_hosts_sync[0x1]; 10302 u8 device_hw_reset[0x1]; 10303 u8 reserved_at_7[0x19]; 10304 }; 10305 10306 union mlx5_ifc_mcqi_reg_data_bits { 10307 struct mlx5_ifc_mcqi_cap_bits mcqi_caps; 10308 struct mlx5_ifc_mcqi_version_bits mcqi_version; 10309 struct mlx5_ifc_mcqi_activation_method_bits mcqi_activation_mathod; 10310 }; 10311 10312 struct mlx5_ifc_mcqi_reg_bits { 10313 u8 read_pending_component[0x1]; 10314 u8 reserved_at_1[0xf]; 10315 u8 component_index[0x10]; 10316 10317 u8 reserved_at_20[0x20]; 10318 10319 u8 reserved_at_40[0x1b]; 10320 u8 info_type[0x5]; 10321 10322 u8 info_size[0x20]; 10323 10324 u8 offset[0x20]; 10325 10326 u8 reserved_at_a0[0x10]; 10327 u8 data_size[0x10]; 10328 10329 union mlx5_ifc_mcqi_reg_data_bits data[]; 10330 }; 10331 10332 struct mlx5_ifc_mcc_reg_bits { 10333 u8 reserved_at_0[0x4]; 10334 u8 time_elapsed_since_last_cmd[0xc]; 10335 u8 reserved_at_10[0x8]; 10336 u8 instruction[0x8]; 10337 10338 u8 reserved_at_20[0x10]; 10339 u8 component_index[0x10]; 10340 10341 u8 reserved_at_40[0x8]; 10342 u8 update_handle[0x18]; 10343 10344 u8 handle_owner_type[0x4]; 10345 u8 handle_owner_host_id[0x4]; 10346 u8 reserved_at_68[0x1]; 10347 u8 control_progress[0x7]; 10348 u8 error_code[0x8]; 10349 u8 reserved_at_78[0x4]; 10350 u8 control_state[0x4]; 10351 10352 u8 component_size[0x20]; 10353 10354 u8 reserved_at_a0[0x60]; 10355 }; 10356 10357 struct mlx5_ifc_mcda_reg_bits { 10358 u8 reserved_at_0[0x8]; 10359 u8 update_handle[0x18]; 10360 10361 u8 offset[0x20]; 10362 10363 u8 reserved_at_40[0x10]; 10364 u8 size[0x10]; 10365 10366 u8 reserved_at_60[0x20]; 10367 10368 u8 data[][0x20]; 10369 }; 10370 10371 enum { 10372 MLX5_MFRL_REG_RESET_TYPE_FULL_CHIP = BIT(0), 10373 MLX5_MFRL_REG_RESET_TYPE_NET_PORT_ALIVE = BIT(1), 10374 }; 10375 10376 enum { 10377 MLX5_MFRL_REG_RESET_LEVEL0 = BIT(0), 10378 MLX5_MFRL_REG_RESET_LEVEL3 = BIT(3), 10379 MLX5_MFRL_REG_RESET_LEVEL6 = BIT(6), 10380 }; 10381 10382 struct mlx5_ifc_mfrl_reg_bits { 10383 u8 reserved_at_0[0x20]; 10384 10385 u8 reserved_at_20[0x2]; 10386 u8 pci_sync_for_fw_update_start[0x1]; 10387 u8 pci_sync_for_fw_update_resp[0x2]; 10388 u8 rst_type_sel[0x3]; 10389 u8 reserved_at_28[0x8]; 10390 u8 reset_type[0x8]; 10391 u8 reset_level[0x8]; 10392 }; 10393 10394 struct mlx5_ifc_mirc_reg_bits { 10395 u8 reserved_at_0[0x18]; 10396 u8 status_code[0x8]; 10397 10398 u8 reserved_at_20[0x20]; 10399 }; 10400 10401 struct mlx5_ifc_pddr_monitor_opcode_bits { 10402 u8 reserved_at_0[0x10]; 10403 u8 monitor_opcode[0x10]; 10404 }; 10405 10406 union mlx5_ifc_pddr_troubleshooting_page_status_opcode_auto_bits { 10407 struct mlx5_ifc_pddr_monitor_opcode_bits pddr_monitor_opcode; 10408 u8 reserved_at_0[0x20]; 10409 }; 10410 10411 enum { 10412 /* Monitor opcodes */ 10413 MLX5_PDDR_REG_TRBLSH_GROUP_OPCODE_MONITOR = 0x0, 10414 }; 10415 10416 struct mlx5_ifc_pddr_troubleshooting_page_bits { 10417 u8 reserved_at_0[0x10]; 10418 u8 group_opcode[0x10]; 10419 10420 union mlx5_ifc_pddr_troubleshooting_page_status_opcode_auto_bits status_opcode; 10421 10422 u8 reserved_at_40[0x20]; 10423 10424 u8 status_message[59][0x20]; 10425 }; 10426 10427 union mlx5_ifc_pddr_reg_page_data_auto_bits { 10428 struct mlx5_ifc_pddr_troubleshooting_page_bits pddr_troubleshooting_page; 10429 u8 reserved_at_0[0x7c0]; 10430 }; 10431 10432 enum { 10433 MLX5_PDDR_REG_PAGE_SELECT_TROUBLESHOOTING_INFO_PAGE = 0x1, 10434 }; 10435 10436 struct mlx5_ifc_pddr_reg_bits { 10437 u8 reserved_at_0[0x8]; 10438 u8 local_port[0x8]; 10439 u8 pnat[0x2]; 10440 u8 reserved_at_12[0xe]; 10441 10442 u8 reserved_at_20[0x18]; 10443 u8 page_select[0x8]; 10444 10445 union mlx5_ifc_pddr_reg_page_data_auto_bits page_data; 10446 }; 10447 10448 struct mlx5_ifc_mrtc_reg_bits { 10449 u8 time_synced[0x1]; 10450 u8 reserved_at_1[0x1f]; 10451 10452 u8 reserved_at_20[0x20]; 10453 10454 u8 time_h[0x20]; 10455 10456 u8 time_l[0x20]; 10457 }; 10458 10459 union mlx5_ifc_ports_control_registers_document_bits { 10460 struct mlx5_ifc_bufferx_reg_bits bufferx_reg; 10461 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 10462 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 10463 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 10464 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 10465 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 10466 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 10467 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout; 10468 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout; 10469 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping; 10470 struct mlx5_ifc_pamp_reg_bits pamp_reg; 10471 struct mlx5_ifc_paos_reg_bits paos_reg; 10472 struct mlx5_ifc_pcap_reg_bits pcap_reg; 10473 struct mlx5_ifc_pddr_monitor_opcode_bits pddr_monitor_opcode; 10474 struct mlx5_ifc_pddr_reg_bits pddr_reg; 10475 struct mlx5_ifc_pddr_troubleshooting_page_bits pddr_troubleshooting_page; 10476 struct mlx5_ifc_peir_reg_bits peir_reg; 10477 struct mlx5_ifc_pelc_reg_bits pelc_reg; 10478 struct mlx5_ifc_pfcc_reg_bits pfcc_reg; 10479 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 10480 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 10481 struct mlx5_ifc_pifr_reg_bits pifr_reg; 10482 struct mlx5_ifc_pipg_reg_bits pipg_reg; 10483 struct mlx5_ifc_plbf_reg_bits plbf_reg; 10484 struct mlx5_ifc_plib_reg_bits plib_reg; 10485 struct mlx5_ifc_plpc_reg_bits plpc_reg; 10486 struct mlx5_ifc_pmaos_reg_bits pmaos_reg; 10487 struct mlx5_ifc_pmlp_reg_bits pmlp_reg; 10488 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg; 10489 struct mlx5_ifc_pmpc_reg_bits pmpc_reg; 10490 struct mlx5_ifc_pmpe_reg_bits pmpe_reg; 10491 struct mlx5_ifc_pmpr_reg_bits pmpr_reg; 10492 struct mlx5_ifc_pmtu_reg_bits pmtu_reg; 10493 struct mlx5_ifc_ppad_reg_bits ppad_reg; 10494 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg; 10495 struct mlx5_ifc_mpein_reg_bits mpein_reg; 10496 struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg; 10497 struct mlx5_ifc_pplm_reg_bits pplm_reg; 10498 struct mlx5_ifc_pplr_reg_bits pplr_reg; 10499 struct mlx5_ifc_ppsc_reg_bits ppsc_reg; 10500 struct mlx5_ifc_pqdr_reg_bits pqdr_reg; 10501 struct mlx5_ifc_pspa_reg_bits pspa_reg; 10502 struct mlx5_ifc_ptas_reg_bits ptas_reg; 10503 struct mlx5_ifc_ptys_reg_bits ptys_reg; 10504 struct mlx5_ifc_mlcr_reg_bits mlcr_reg; 10505 struct mlx5_ifc_pude_reg_bits pude_reg; 10506 struct mlx5_ifc_pvlc_reg_bits pvlc_reg; 10507 struct mlx5_ifc_slrg_reg_bits slrg_reg; 10508 struct mlx5_ifc_sltp_reg_bits sltp_reg; 10509 struct mlx5_ifc_mtpps_reg_bits mtpps_reg; 10510 struct mlx5_ifc_mtppse_reg_bits mtppse_reg; 10511 struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg; 10512 struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits; 10513 struct mlx5_ifc_fpga_cap_bits fpga_cap_bits; 10514 struct mlx5_ifc_mcqi_reg_bits mcqi_reg; 10515 struct mlx5_ifc_mcc_reg_bits mcc_reg; 10516 struct mlx5_ifc_mcda_reg_bits mcda_reg; 10517 struct mlx5_ifc_mirc_reg_bits mirc_reg; 10518 struct mlx5_ifc_mfrl_reg_bits mfrl_reg; 10519 struct mlx5_ifc_mtutc_reg_bits mtutc_reg; 10520 struct mlx5_ifc_mrtc_reg_bits mrtc_reg; 10521 u8 reserved_at_0[0x60e0]; 10522 }; 10523 10524 union mlx5_ifc_debug_enhancements_document_bits { 10525 struct mlx5_ifc_health_buffer_bits health_buffer; 10526 u8 reserved_at_0[0x200]; 10527 }; 10528 10529 union mlx5_ifc_uplink_pci_interface_document_bits { 10530 struct mlx5_ifc_initial_seg_bits initial_seg; 10531 u8 reserved_at_0[0x20060]; 10532 }; 10533 10534 struct mlx5_ifc_set_flow_table_root_out_bits { 10535 u8 status[0x8]; 10536 u8 reserved_at_8[0x18]; 10537 10538 u8 syndrome[0x20]; 10539 10540 u8 reserved_at_40[0x40]; 10541 }; 10542 10543 struct mlx5_ifc_set_flow_table_root_in_bits { 10544 u8 opcode[0x10]; 10545 u8 reserved_at_10[0x10]; 10546 10547 u8 reserved_at_20[0x10]; 10548 u8 op_mod[0x10]; 10549 10550 u8 other_vport[0x1]; 10551 u8 reserved_at_41[0xf]; 10552 u8 vport_number[0x10]; 10553 10554 u8 reserved_at_60[0x20]; 10555 10556 u8 table_type[0x8]; 10557 u8 reserved_at_88[0x7]; 10558 u8 table_of_other_vport[0x1]; 10559 u8 table_vport_number[0x10]; 10560 10561 u8 reserved_at_a0[0x8]; 10562 u8 table_id[0x18]; 10563 10564 u8 reserved_at_c0[0x8]; 10565 u8 underlay_qpn[0x18]; 10566 u8 table_eswitch_owner_vhca_id_valid[0x1]; 10567 u8 reserved_at_e1[0xf]; 10568 u8 table_eswitch_owner_vhca_id[0x10]; 10569 u8 reserved_at_100[0x100]; 10570 }; 10571 10572 enum { 10573 MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = (1UL << 0), 10574 MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15), 10575 }; 10576 10577 struct mlx5_ifc_modify_flow_table_out_bits { 10578 u8 status[0x8]; 10579 u8 reserved_at_8[0x18]; 10580 10581 u8 syndrome[0x20]; 10582 10583 u8 reserved_at_40[0x40]; 10584 }; 10585 10586 struct mlx5_ifc_modify_flow_table_in_bits { 10587 u8 opcode[0x10]; 10588 u8 reserved_at_10[0x10]; 10589 10590 u8 reserved_at_20[0x10]; 10591 u8 op_mod[0x10]; 10592 10593 u8 other_vport[0x1]; 10594 u8 reserved_at_41[0xf]; 10595 u8 vport_number[0x10]; 10596 10597 u8 reserved_at_60[0x10]; 10598 u8 modify_field_select[0x10]; 10599 10600 u8 table_type[0x8]; 10601 u8 reserved_at_88[0x18]; 10602 10603 u8 reserved_at_a0[0x8]; 10604 u8 table_id[0x18]; 10605 10606 struct mlx5_ifc_flow_table_context_bits flow_table_context; 10607 }; 10608 10609 struct mlx5_ifc_ets_tcn_config_reg_bits { 10610 u8 g[0x1]; 10611 u8 b[0x1]; 10612 u8 r[0x1]; 10613 u8 reserved_at_3[0x9]; 10614 u8 group[0x4]; 10615 u8 reserved_at_10[0x9]; 10616 u8 bw_allocation[0x7]; 10617 10618 u8 reserved_at_20[0xc]; 10619 u8 max_bw_units[0x4]; 10620 u8 reserved_at_30[0x8]; 10621 u8 max_bw_value[0x8]; 10622 }; 10623 10624 struct mlx5_ifc_ets_global_config_reg_bits { 10625 u8 reserved_at_0[0x2]; 10626 u8 r[0x1]; 10627 u8 reserved_at_3[0x1d]; 10628 10629 u8 reserved_at_20[0xc]; 10630 u8 max_bw_units[0x4]; 10631 u8 reserved_at_30[0x8]; 10632 u8 max_bw_value[0x8]; 10633 }; 10634 10635 struct mlx5_ifc_qetc_reg_bits { 10636 u8 reserved_at_0[0x8]; 10637 u8 port_number[0x8]; 10638 u8 reserved_at_10[0x30]; 10639 10640 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8]; 10641 struct mlx5_ifc_ets_global_config_reg_bits global_configuration; 10642 }; 10643 10644 struct mlx5_ifc_qpdpm_dscp_reg_bits { 10645 u8 e[0x1]; 10646 u8 reserved_at_01[0x0b]; 10647 u8 prio[0x04]; 10648 }; 10649 10650 struct mlx5_ifc_qpdpm_reg_bits { 10651 u8 reserved_at_0[0x8]; 10652 u8 local_port[0x8]; 10653 u8 reserved_at_10[0x10]; 10654 struct mlx5_ifc_qpdpm_dscp_reg_bits dscp[64]; 10655 }; 10656 10657 struct mlx5_ifc_qpts_reg_bits { 10658 u8 reserved_at_0[0x8]; 10659 u8 local_port[0x8]; 10660 u8 reserved_at_10[0x2d]; 10661 u8 trust_state[0x3]; 10662 }; 10663 10664 struct mlx5_ifc_pptb_reg_bits { 10665 u8 reserved_at_0[0x2]; 10666 u8 mm[0x2]; 10667 u8 reserved_at_4[0x4]; 10668 u8 local_port[0x8]; 10669 u8 reserved_at_10[0x6]; 10670 u8 cm[0x1]; 10671 u8 um[0x1]; 10672 u8 pm[0x8]; 10673 10674 u8 prio_x_buff[0x20]; 10675 10676 u8 pm_msb[0x8]; 10677 u8 reserved_at_48[0x10]; 10678 u8 ctrl_buff[0x4]; 10679 u8 untagged_buff[0x4]; 10680 }; 10681 10682 struct mlx5_ifc_sbcam_reg_bits { 10683 u8 reserved_at_0[0x8]; 10684 u8 feature_group[0x8]; 10685 u8 reserved_at_10[0x8]; 10686 u8 access_reg_group[0x8]; 10687 10688 u8 reserved_at_20[0x20]; 10689 10690 u8 sb_access_reg_cap_mask[4][0x20]; 10691 10692 u8 reserved_at_c0[0x80]; 10693 10694 u8 sb_feature_cap_mask[4][0x20]; 10695 10696 u8 reserved_at_1c0[0x40]; 10697 10698 u8 cap_total_buffer_size[0x20]; 10699 10700 u8 cap_cell_size[0x10]; 10701 u8 cap_max_pg_buffers[0x8]; 10702 u8 cap_num_pool_supported[0x8]; 10703 10704 u8 reserved_at_240[0x8]; 10705 u8 cap_sbsr_stat_size[0x8]; 10706 u8 cap_max_tclass_data[0x8]; 10707 u8 cap_max_cpu_ingress_tclass_sb[0x8]; 10708 }; 10709 10710 struct mlx5_ifc_pbmc_reg_bits { 10711 u8 reserved_at_0[0x8]; 10712 u8 local_port[0x8]; 10713 u8 reserved_at_10[0x10]; 10714 10715 u8 xoff_timer_value[0x10]; 10716 u8 xoff_refresh[0x10]; 10717 10718 u8 reserved_at_40[0x9]; 10719 u8 fullness_threshold[0x7]; 10720 u8 port_buffer_size[0x10]; 10721 10722 struct mlx5_ifc_bufferx_reg_bits buffer[10]; 10723 10724 u8 reserved_at_2e0[0x80]; 10725 }; 10726 10727 struct mlx5_ifc_qtct_reg_bits { 10728 u8 reserved_at_0[0x8]; 10729 u8 port_number[0x8]; 10730 u8 reserved_at_10[0xd]; 10731 u8 prio[0x3]; 10732 10733 u8 reserved_at_20[0x1d]; 10734 u8 tclass[0x3]; 10735 }; 10736 10737 struct mlx5_ifc_mcia_reg_bits { 10738 u8 l[0x1]; 10739 u8 reserved_at_1[0x7]; 10740 u8 module[0x8]; 10741 u8 reserved_at_10[0x8]; 10742 u8 status[0x8]; 10743 10744 u8 i2c_device_address[0x8]; 10745 u8 page_number[0x8]; 10746 u8 device_address[0x10]; 10747 10748 u8 reserved_at_40[0x10]; 10749 u8 size[0x10]; 10750 10751 u8 reserved_at_60[0x20]; 10752 10753 u8 dword_0[0x20]; 10754 u8 dword_1[0x20]; 10755 u8 dword_2[0x20]; 10756 u8 dword_3[0x20]; 10757 u8 dword_4[0x20]; 10758 u8 dword_5[0x20]; 10759 u8 dword_6[0x20]; 10760 u8 dword_7[0x20]; 10761 u8 dword_8[0x20]; 10762 u8 dword_9[0x20]; 10763 u8 dword_10[0x20]; 10764 u8 dword_11[0x20]; 10765 }; 10766 10767 struct mlx5_ifc_dcbx_param_bits { 10768 u8 dcbx_cee_cap[0x1]; 10769 u8 dcbx_ieee_cap[0x1]; 10770 u8 dcbx_standby_cap[0x1]; 10771 u8 reserved_at_3[0x5]; 10772 u8 port_number[0x8]; 10773 u8 reserved_at_10[0xa]; 10774 u8 max_application_table_size[6]; 10775 u8 reserved_at_20[0x15]; 10776 u8 version_oper[0x3]; 10777 u8 reserved_at_38[5]; 10778 u8 version_admin[0x3]; 10779 u8 willing_admin[0x1]; 10780 u8 reserved_at_41[0x3]; 10781 u8 pfc_cap_oper[0x4]; 10782 u8 reserved_at_48[0x4]; 10783 u8 pfc_cap_admin[0x4]; 10784 u8 reserved_at_50[0x4]; 10785 u8 num_of_tc_oper[0x4]; 10786 u8 reserved_at_58[0x4]; 10787 u8 num_of_tc_admin[0x4]; 10788 u8 remote_willing[0x1]; 10789 u8 reserved_at_61[3]; 10790 u8 remote_pfc_cap[4]; 10791 u8 reserved_at_68[0x14]; 10792 u8 remote_num_of_tc[0x4]; 10793 u8 reserved_at_80[0x18]; 10794 u8 error[0x8]; 10795 u8 reserved_at_a0[0x160]; 10796 }; 10797 10798 enum { 10799 MLX5_LAG_PORT_SELECT_MODE_QUEUE_AFFINITY = 0, 10800 MLX5_LAG_PORT_SELECT_MODE_PORT_SELECT_FT, 10801 }; 10802 10803 struct mlx5_ifc_lagc_bits { 10804 u8 fdb_selection_mode[0x1]; 10805 u8 reserved_at_1[0x14]; 10806 u8 port_select_mode[0x3]; 10807 u8 reserved_at_18[0x5]; 10808 u8 lag_state[0x3]; 10809 10810 u8 reserved_at_20[0x14]; 10811 u8 tx_remap_affinity_2[0x4]; 10812 u8 reserved_at_38[0x4]; 10813 u8 tx_remap_affinity_1[0x4]; 10814 }; 10815 10816 struct mlx5_ifc_create_lag_out_bits { 10817 u8 status[0x8]; 10818 u8 reserved_at_8[0x18]; 10819 10820 u8 syndrome[0x20]; 10821 10822 u8 reserved_at_40[0x40]; 10823 }; 10824 10825 struct mlx5_ifc_create_lag_in_bits { 10826 u8 opcode[0x10]; 10827 u8 reserved_at_10[0x10]; 10828 10829 u8 reserved_at_20[0x10]; 10830 u8 op_mod[0x10]; 10831 10832 struct mlx5_ifc_lagc_bits ctx; 10833 }; 10834 10835 struct mlx5_ifc_modify_lag_out_bits { 10836 u8 status[0x8]; 10837 u8 reserved_at_8[0x18]; 10838 10839 u8 syndrome[0x20]; 10840 10841 u8 reserved_at_40[0x40]; 10842 }; 10843 10844 struct mlx5_ifc_modify_lag_in_bits { 10845 u8 opcode[0x10]; 10846 u8 reserved_at_10[0x10]; 10847 10848 u8 reserved_at_20[0x10]; 10849 u8 op_mod[0x10]; 10850 10851 u8 reserved_at_40[0x20]; 10852 u8 field_select[0x20]; 10853 10854 struct mlx5_ifc_lagc_bits ctx; 10855 }; 10856 10857 struct mlx5_ifc_query_lag_out_bits { 10858 u8 status[0x8]; 10859 u8 reserved_at_8[0x18]; 10860 10861 u8 syndrome[0x20]; 10862 10863 struct mlx5_ifc_lagc_bits ctx; 10864 }; 10865 10866 struct mlx5_ifc_query_lag_in_bits { 10867 u8 opcode[0x10]; 10868 u8 reserved_at_10[0x10]; 10869 10870 u8 reserved_at_20[0x10]; 10871 u8 op_mod[0x10]; 10872 10873 u8 reserved_at_40[0x40]; 10874 }; 10875 10876 struct mlx5_ifc_destroy_lag_out_bits { 10877 u8 status[0x8]; 10878 u8 reserved_at_8[0x18]; 10879 10880 u8 syndrome[0x20]; 10881 10882 u8 reserved_at_40[0x40]; 10883 }; 10884 10885 struct mlx5_ifc_destroy_lag_in_bits { 10886 u8 opcode[0x10]; 10887 u8 reserved_at_10[0x10]; 10888 10889 u8 reserved_at_20[0x10]; 10890 u8 op_mod[0x10]; 10891 10892 u8 reserved_at_40[0x40]; 10893 }; 10894 10895 struct mlx5_ifc_create_vport_lag_out_bits { 10896 u8 status[0x8]; 10897 u8 reserved_at_8[0x18]; 10898 10899 u8 syndrome[0x20]; 10900 10901 u8 reserved_at_40[0x40]; 10902 }; 10903 10904 struct mlx5_ifc_create_vport_lag_in_bits { 10905 u8 opcode[0x10]; 10906 u8 reserved_at_10[0x10]; 10907 10908 u8 reserved_at_20[0x10]; 10909 u8 op_mod[0x10]; 10910 10911 u8 reserved_at_40[0x40]; 10912 }; 10913 10914 struct mlx5_ifc_destroy_vport_lag_out_bits { 10915 u8 status[0x8]; 10916 u8 reserved_at_8[0x18]; 10917 10918 u8 syndrome[0x20]; 10919 10920 u8 reserved_at_40[0x40]; 10921 }; 10922 10923 struct mlx5_ifc_destroy_vport_lag_in_bits { 10924 u8 opcode[0x10]; 10925 u8 reserved_at_10[0x10]; 10926 10927 u8 reserved_at_20[0x10]; 10928 u8 op_mod[0x10]; 10929 10930 u8 reserved_at_40[0x40]; 10931 }; 10932 10933 enum { 10934 MLX5_MODIFY_MEMIC_OP_MOD_ALLOC, 10935 MLX5_MODIFY_MEMIC_OP_MOD_DEALLOC, 10936 }; 10937 10938 struct mlx5_ifc_modify_memic_in_bits { 10939 u8 opcode[0x10]; 10940 u8 uid[0x10]; 10941 10942 u8 reserved_at_20[0x10]; 10943 u8 op_mod[0x10]; 10944 10945 u8 reserved_at_40[0x20]; 10946 10947 u8 reserved_at_60[0x18]; 10948 u8 memic_operation_type[0x8]; 10949 10950 u8 memic_start_addr[0x40]; 10951 10952 u8 reserved_at_c0[0x140]; 10953 }; 10954 10955 struct mlx5_ifc_modify_memic_out_bits { 10956 u8 status[0x8]; 10957 u8 reserved_at_8[0x18]; 10958 10959 u8 syndrome[0x20]; 10960 10961 u8 reserved_at_40[0x40]; 10962 10963 u8 memic_operation_addr[0x40]; 10964 10965 u8 reserved_at_c0[0x140]; 10966 }; 10967 10968 struct mlx5_ifc_alloc_memic_in_bits { 10969 u8 opcode[0x10]; 10970 u8 reserved_at_10[0x10]; 10971 10972 u8 reserved_at_20[0x10]; 10973 u8 op_mod[0x10]; 10974 10975 u8 reserved_at_30[0x20]; 10976 10977 u8 reserved_at_40[0x18]; 10978 u8 log_memic_addr_alignment[0x8]; 10979 10980 u8 range_start_addr[0x40]; 10981 10982 u8 range_size[0x20]; 10983 10984 u8 memic_size[0x20]; 10985 }; 10986 10987 struct mlx5_ifc_alloc_memic_out_bits { 10988 u8 status[0x8]; 10989 u8 reserved_at_8[0x18]; 10990 10991 u8 syndrome[0x20]; 10992 10993 u8 memic_start_addr[0x40]; 10994 }; 10995 10996 struct mlx5_ifc_dealloc_memic_in_bits { 10997 u8 opcode[0x10]; 10998 u8 reserved_at_10[0x10]; 10999 11000 u8 reserved_at_20[0x10]; 11001 u8 op_mod[0x10]; 11002 11003 u8 reserved_at_40[0x40]; 11004 11005 u8 memic_start_addr[0x40]; 11006 11007 u8 memic_size[0x20]; 11008 11009 u8 reserved_at_e0[0x20]; 11010 }; 11011 11012 struct mlx5_ifc_dealloc_memic_out_bits { 11013 u8 status[0x8]; 11014 u8 reserved_at_8[0x18]; 11015 11016 u8 syndrome[0x20]; 11017 11018 u8 reserved_at_40[0x40]; 11019 }; 11020 11021 struct mlx5_ifc_umem_bits { 11022 u8 reserved_at_0[0x80]; 11023 11024 u8 reserved_at_80[0x1b]; 11025 u8 log_page_size[0x5]; 11026 11027 u8 page_offset[0x20]; 11028 11029 u8 num_of_mtt[0x40]; 11030 11031 struct mlx5_ifc_mtt_bits mtt[]; 11032 }; 11033 11034 struct mlx5_ifc_uctx_bits { 11035 u8 cap[0x20]; 11036 11037 u8 reserved_at_20[0x160]; 11038 }; 11039 11040 struct mlx5_ifc_sw_icm_bits { 11041 u8 modify_field_select[0x40]; 11042 11043 u8 reserved_at_40[0x18]; 11044 u8 log_sw_icm_size[0x8]; 11045 11046 u8 reserved_at_60[0x20]; 11047 11048 u8 sw_icm_start_addr[0x40]; 11049 11050 u8 reserved_at_c0[0x140]; 11051 }; 11052 11053 struct mlx5_ifc_geneve_tlv_option_bits { 11054 u8 modify_field_select[0x40]; 11055 11056 u8 reserved_at_40[0x18]; 11057 u8 geneve_option_fte_index[0x8]; 11058 11059 u8 option_class[0x10]; 11060 u8 option_type[0x8]; 11061 u8 reserved_at_78[0x3]; 11062 u8 option_data_length[0x5]; 11063 11064 u8 reserved_at_80[0x180]; 11065 }; 11066 11067 struct mlx5_ifc_create_umem_in_bits { 11068 u8 opcode[0x10]; 11069 u8 uid[0x10]; 11070 11071 u8 reserved_at_20[0x10]; 11072 u8 op_mod[0x10]; 11073 11074 u8 reserved_at_40[0x40]; 11075 11076 struct mlx5_ifc_umem_bits umem; 11077 }; 11078 11079 struct mlx5_ifc_create_umem_out_bits { 11080 u8 status[0x8]; 11081 u8 reserved_at_8[0x18]; 11082 11083 u8 syndrome[0x20]; 11084 11085 u8 reserved_at_40[0x8]; 11086 u8 umem_id[0x18]; 11087 11088 u8 reserved_at_60[0x20]; 11089 }; 11090 11091 struct mlx5_ifc_destroy_umem_in_bits { 11092 u8 opcode[0x10]; 11093 u8 uid[0x10]; 11094 11095 u8 reserved_at_20[0x10]; 11096 u8 op_mod[0x10]; 11097 11098 u8 reserved_at_40[0x8]; 11099 u8 umem_id[0x18]; 11100 11101 u8 reserved_at_60[0x20]; 11102 }; 11103 11104 struct mlx5_ifc_destroy_umem_out_bits { 11105 u8 status[0x8]; 11106 u8 reserved_at_8[0x18]; 11107 11108 u8 syndrome[0x20]; 11109 11110 u8 reserved_at_40[0x40]; 11111 }; 11112 11113 struct mlx5_ifc_create_uctx_in_bits { 11114 u8 opcode[0x10]; 11115 u8 reserved_at_10[0x10]; 11116 11117 u8 reserved_at_20[0x10]; 11118 u8 op_mod[0x10]; 11119 11120 u8 reserved_at_40[0x40]; 11121 11122 struct mlx5_ifc_uctx_bits uctx; 11123 }; 11124 11125 struct mlx5_ifc_create_uctx_out_bits { 11126 u8 status[0x8]; 11127 u8 reserved_at_8[0x18]; 11128 11129 u8 syndrome[0x20]; 11130 11131 u8 reserved_at_40[0x10]; 11132 u8 uid[0x10]; 11133 11134 u8 reserved_at_60[0x20]; 11135 }; 11136 11137 struct mlx5_ifc_destroy_uctx_in_bits { 11138 u8 opcode[0x10]; 11139 u8 reserved_at_10[0x10]; 11140 11141 u8 reserved_at_20[0x10]; 11142 u8 op_mod[0x10]; 11143 11144 u8 reserved_at_40[0x10]; 11145 u8 uid[0x10]; 11146 11147 u8 reserved_at_60[0x20]; 11148 }; 11149 11150 struct mlx5_ifc_destroy_uctx_out_bits { 11151 u8 status[0x8]; 11152 u8 reserved_at_8[0x18]; 11153 11154 u8 syndrome[0x20]; 11155 11156 u8 reserved_at_40[0x40]; 11157 }; 11158 11159 struct mlx5_ifc_create_sw_icm_in_bits { 11160 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 11161 struct mlx5_ifc_sw_icm_bits sw_icm; 11162 }; 11163 11164 struct mlx5_ifc_create_geneve_tlv_option_in_bits { 11165 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 11166 struct mlx5_ifc_geneve_tlv_option_bits geneve_tlv_opt; 11167 }; 11168 11169 struct mlx5_ifc_mtrc_string_db_param_bits { 11170 u8 string_db_base_address[0x20]; 11171 11172 u8 reserved_at_20[0x8]; 11173 u8 string_db_size[0x18]; 11174 }; 11175 11176 struct mlx5_ifc_mtrc_cap_bits { 11177 u8 trace_owner[0x1]; 11178 u8 trace_to_memory[0x1]; 11179 u8 reserved_at_2[0x4]; 11180 u8 trc_ver[0x2]; 11181 u8 reserved_at_8[0x14]; 11182 u8 num_string_db[0x4]; 11183 11184 u8 first_string_trace[0x8]; 11185 u8 num_string_trace[0x8]; 11186 u8 reserved_at_30[0x28]; 11187 11188 u8 log_max_trace_buffer_size[0x8]; 11189 11190 u8 reserved_at_60[0x20]; 11191 11192 struct mlx5_ifc_mtrc_string_db_param_bits string_db_param[8]; 11193 11194 u8 reserved_at_280[0x180]; 11195 }; 11196 11197 struct mlx5_ifc_mtrc_conf_bits { 11198 u8 reserved_at_0[0x1c]; 11199 u8 trace_mode[0x4]; 11200 u8 reserved_at_20[0x18]; 11201 u8 log_trace_buffer_size[0x8]; 11202 u8 trace_mkey[0x20]; 11203 u8 reserved_at_60[0x3a0]; 11204 }; 11205 11206 struct mlx5_ifc_mtrc_stdb_bits { 11207 u8 string_db_index[0x4]; 11208 u8 reserved_at_4[0x4]; 11209 u8 read_size[0x18]; 11210 u8 start_offset[0x20]; 11211 u8 string_db_data[]; 11212 }; 11213 11214 struct mlx5_ifc_mtrc_ctrl_bits { 11215 u8 trace_status[0x2]; 11216 u8 reserved_at_2[0x2]; 11217 u8 arm_event[0x1]; 11218 u8 reserved_at_5[0xb]; 11219 u8 modify_field_select[0x10]; 11220 u8 reserved_at_20[0x2b]; 11221 u8 current_timestamp52_32[0x15]; 11222 u8 current_timestamp31_0[0x20]; 11223 u8 reserved_at_80[0x180]; 11224 }; 11225 11226 struct mlx5_ifc_host_params_context_bits { 11227 u8 host_number[0x8]; 11228 u8 reserved_at_8[0x7]; 11229 u8 host_pf_disabled[0x1]; 11230 u8 host_num_of_vfs[0x10]; 11231 11232 u8 host_total_vfs[0x10]; 11233 u8 host_pci_bus[0x10]; 11234 11235 u8 reserved_at_40[0x10]; 11236 u8 host_pci_device[0x10]; 11237 11238 u8 reserved_at_60[0x10]; 11239 u8 host_pci_function[0x10]; 11240 11241 u8 reserved_at_80[0x180]; 11242 }; 11243 11244 struct mlx5_ifc_query_esw_functions_in_bits { 11245 u8 opcode[0x10]; 11246 u8 reserved_at_10[0x10]; 11247 11248 u8 reserved_at_20[0x10]; 11249 u8 op_mod[0x10]; 11250 11251 u8 reserved_at_40[0x40]; 11252 }; 11253 11254 struct mlx5_ifc_query_esw_functions_out_bits { 11255 u8 status[0x8]; 11256 u8 reserved_at_8[0x18]; 11257 11258 u8 syndrome[0x20]; 11259 11260 u8 reserved_at_40[0x40]; 11261 11262 struct mlx5_ifc_host_params_context_bits host_params_context; 11263 11264 u8 reserved_at_280[0x180]; 11265 u8 host_sf_enable[][0x40]; 11266 }; 11267 11268 struct mlx5_ifc_sf_partition_bits { 11269 u8 reserved_at_0[0x10]; 11270 u8 log_num_sf[0x8]; 11271 u8 log_sf_bar_size[0x8]; 11272 }; 11273 11274 struct mlx5_ifc_query_sf_partitions_out_bits { 11275 u8 status[0x8]; 11276 u8 reserved_at_8[0x18]; 11277 11278 u8 syndrome[0x20]; 11279 11280 u8 reserved_at_40[0x18]; 11281 u8 num_sf_partitions[0x8]; 11282 11283 u8 reserved_at_60[0x20]; 11284 11285 struct mlx5_ifc_sf_partition_bits sf_partition[]; 11286 }; 11287 11288 struct mlx5_ifc_query_sf_partitions_in_bits { 11289 u8 opcode[0x10]; 11290 u8 reserved_at_10[0x10]; 11291 11292 u8 reserved_at_20[0x10]; 11293 u8 op_mod[0x10]; 11294 11295 u8 reserved_at_40[0x40]; 11296 }; 11297 11298 struct mlx5_ifc_dealloc_sf_out_bits { 11299 u8 status[0x8]; 11300 u8 reserved_at_8[0x18]; 11301 11302 u8 syndrome[0x20]; 11303 11304 u8 reserved_at_40[0x40]; 11305 }; 11306 11307 struct mlx5_ifc_dealloc_sf_in_bits { 11308 u8 opcode[0x10]; 11309 u8 reserved_at_10[0x10]; 11310 11311 u8 reserved_at_20[0x10]; 11312 u8 op_mod[0x10]; 11313 11314 u8 reserved_at_40[0x10]; 11315 u8 function_id[0x10]; 11316 11317 u8 reserved_at_60[0x20]; 11318 }; 11319 11320 struct mlx5_ifc_alloc_sf_out_bits { 11321 u8 status[0x8]; 11322 u8 reserved_at_8[0x18]; 11323 11324 u8 syndrome[0x20]; 11325 11326 u8 reserved_at_40[0x40]; 11327 }; 11328 11329 struct mlx5_ifc_alloc_sf_in_bits { 11330 u8 opcode[0x10]; 11331 u8 reserved_at_10[0x10]; 11332 11333 u8 reserved_at_20[0x10]; 11334 u8 op_mod[0x10]; 11335 11336 u8 reserved_at_40[0x10]; 11337 u8 function_id[0x10]; 11338 11339 u8 reserved_at_60[0x20]; 11340 }; 11341 11342 struct mlx5_ifc_affiliated_event_header_bits { 11343 u8 reserved_at_0[0x10]; 11344 u8 obj_type[0x10]; 11345 11346 u8 obj_id[0x20]; 11347 }; 11348 11349 enum { 11350 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = BIT_ULL(0xc), 11351 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_IPSEC = BIT_ULL(0x13), 11352 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_SAMPLER = BIT_ULL(0x20), 11353 }; 11354 11355 enum { 11356 MLX5_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = 0xc, 11357 MLX5_GENERAL_OBJECT_TYPES_IPSEC = 0x13, 11358 MLX5_GENERAL_OBJECT_TYPES_SAMPLER = 0x20, 11359 }; 11360 11361 enum { 11362 MLX5_IPSEC_OBJECT_ICV_LEN_16B, 11363 MLX5_IPSEC_OBJECT_ICV_LEN_12B, 11364 MLX5_IPSEC_OBJECT_ICV_LEN_8B, 11365 }; 11366 11367 struct mlx5_ifc_ipsec_obj_bits { 11368 u8 modify_field_select[0x40]; 11369 u8 full_offload[0x1]; 11370 u8 reserved_at_41[0x1]; 11371 u8 esn_en[0x1]; 11372 u8 esn_overlap[0x1]; 11373 u8 reserved_at_44[0x2]; 11374 u8 icv_length[0x2]; 11375 u8 reserved_at_48[0x4]; 11376 u8 aso_return_reg[0x4]; 11377 u8 reserved_at_50[0x10]; 11378 11379 u8 esn_msb[0x20]; 11380 11381 u8 reserved_at_80[0x8]; 11382 u8 dekn[0x18]; 11383 11384 u8 salt[0x20]; 11385 11386 u8 implicit_iv[0x40]; 11387 11388 u8 reserved_at_100[0x700]; 11389 }; 11390 11391 struct mlx5_ifc_create_ipsec_obj_in_bits { 11392 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 11393 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 11394 }; 11395 11396 enum { 11397 MLX5_MODIFY_IPSEC_BITMASK_ESN_OVERLAP = BIT(0), 11398 MLX5_MODIFY_IPSEC_BITMASK_ESN_MSB = BIT(1), 11399 }; 11400 11401 struct mlx5_ifc_query_ipsec_obj_out_bits { 11402 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 11403 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 11404 }; 11405 11406 struct mlx5_ifc_modify_ipsec_obj_in_bits { 11407 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 11408 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 11409 }; 11410 11411 struct mlx5_ifc_encryption_key_obj_bits { 11412 u8 modify_field_select[0x40]; 11413 11414 u8 reserved_at_40[0x14]; 11415 u8 key_size[0x4]; 11416 u8 reserved_at_58[0x4]; 11417 u8 key_type[0x4]; 11418 11419 u8 reserved_at_60[0x8]; 11420 u8 pd[0x18]; 11421 11422 u8 reserved_at_80[0x180]; 11423 u8 key[8][0x20]; 11424 11425 u8 reserved_at_300[0x500]; 11426 }; 11427 11428 struct mlx5_ifc_create_encryption_key_in_bits { 11429 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 11430 struct mlx5_ifc_encryption_key_obj_bits encryption_key_object; 11431 }; 11432 11433 struct mlx5_ifc_sampler_obj_bits { 11434 u8 modify_field_select[0x40]; 11435 11436 u8 table_type[0x8]; 11437 u8 level[0x8]; 11438 u8 reserved_at_50[0xf]; 11439 u8 ignore_flow_level[0x1]; 11440 11441 u8 sample_ratio[0x20]; 11442 11443 u8 reserved_at_80[0x8]; 11444 u8 sample_table_id[0x18]; 11445 11446 u8 reserved_at_a0[0x8]; 11447 u8 default_table_id[0x18]; 11448 11449 u8 sw_steering_icm_address_rx[0x40]; 11450 u8 sw_steering_icm_address_tx[0x40]; 11451 11452 u8 reserved_at_140[0xa0]; 11453 }; 11454 11455 struct mlx5_ifc_create_sampler_obj_in_bits { 11456 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 11457 struct mlx5_ifc_sampler_obj_bits sampler_object; 11458 }; 11459 11460 struct mlx5_ifc_query_sampler_obj_out_bits { 11461 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 11462 struct mlx5_ifc_sampler_obj_bits sampler_object; 11463 }; 11464 11465 enum { 11466 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_128 = 0x0, 11467 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_256 = 0x1, 11468 }; 11469 11470 enum { 11471 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_TYPE_TLS = 0x1, 11472 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_TYPE_IPSEC = 0x2, 11473 }; 11474 11475 struct mlx5_ifc_tls_static_params_bits { 11476 u8 const_2[0x2]; 11477 u8 tls_version[0x4]; 11478 u8 const_1[0x2]; 11479 u8 reserved_at_8[0x14]; 11480 u8 encryption_standard[0x4]; 11481 11482 u8 reserved_at_20[0x20]; 11483 11484 u8 initial_record_number[0x40]; 11485 11486 u8 resync_tcp_sn[0x20]; 11487 11488 u8 gcm_iv[0x20]; 11489 11490 u8 implicit_iv[0x40]; 11491 11492 u8 reserved_at_100[0x8]; 11493 u8 dek_index[0x18]; 11494 11495 u8 reserved_at_120[0xe0]; 11496 }; 11497 11498 struct mlx5_ifc_tls_progress_params_bits { 11499 u8 next_record_tcp_sn[0x20]; 11500 11501 u8 hw_resync_tcp_sn[0x20]; 11502 11503 u8 record_tracker_state[0x2]; 11504 u8 auth_state[0x2]; 11505 u8 reserved_at_44[0x4]; 11506 u8 hw_offset_record_number[0x18]; 11507 }; 11508 11509 enum { 11510 MLX5_MTT_PERM_READ = 1 << 0, 11511 MLX5_MTT_PERM_WRITE = 1 << 1, 11512 MLX5_MTT_PERM_RW = MLX5_MTT_PERM_READ | MLX5_MTT_PERM_WRITE, 11513 }; 11514 11515 #endif /* MLX5_IFC_H */ 11516