1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 #ifndef MLX5_IFC_H 33 #define MLX5_IFC_H 34 35 #include "mlx5_ifc_fpga.h" 36 37 enum { 38 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0, 39 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1, 40 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2, 41 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3, 42 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13, 43 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14, 44 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c, 45 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d, 46 MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4, 47 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5, 48 MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED = 0x7, 49 MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT = 0xc, 50 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10, 51 MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR = 0x11, 52 MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR = 0x12, 53 MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR = 0x8, 54 MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE = 0x9, 55 MLX5_EVENT_TYPE_CODING_GPIO_EVENT = 0x15, 56 MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19, 57 MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a, 58 MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT = 0x1b, 59 MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT = 0x1f, 60 MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa, 61 MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb, 62 MLX5_EVENT_TYPE_CODING_FPGA_ERROR = 0x20, 63 MLX5_EVENT_TYPE_CODING_FPGA_QP_ERROR = 0x21 64 }; 65 66 enum { 67 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0, 68 MLX5_SET_HCA_CAP_OP_MOD_ETHERNET_OFFLOADS = 0x1, 69 MLX5_SET_HCA_CAP_OP_MOD_ODP = 0x2, 70 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3, 71 MLX5_SET_HCA_CAP_OP_MOD_ROCE = 0x4, 72 MLX5_SET_HCA_CAP_OP_MOD_IPSEC = 0x15, 73 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE2 = 0x20, 74 MLX5_SET_HCA_CAP_OP_MOD_PORT_SELECTION = 0x25, 75 }; 76 77 enum { 78 MLX5_SHARED_RESOURCE_UID = 0xffff, 79 }; 80 81 enum { 82 MLX5_OBJ_TYPE_SW_ICM = 0x0008, 83 MLX5_OBJ_TYPE_HEADER_MODIFY_ARGUMENT = 0x23, 84 }; 85 86 enum { 87 MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM = (1ULL << MLX5_OBJ_TYPE_SW_ICM), 88 MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT = (1ULL << 11), 89 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q = (1ULL << 13), 90 MLX5_GENERAL_OBJ_TYPES_CAP_HEADER_MODIFY_ARGUMENT = 91 (1ULL << MLX5_OBJ_TYPE_HEADER_MODIFY_ARGUMENT), 92 MLX5_GENERAL_OBJ_TYPES_CAP_MACSEC_OFFLOAD = (1ULL << 39), 93 }; 94 95 enum { 96 MLX5_OBJ_TYPE_GENEVE_TLV_OPT = 0x000b, 97 MLX5_OBJ_TYPE_VIRTIO_NET_Q = 0x000d, 98 MLX5_OBJ_TYPE_VIRTIO_Q_COUNTERS = 0x001c, 99 MLX5_OBJ_TYPE_MATCH_DEFINER = 0x0018, 100 MLX5_OBJ_TYPE_PAGE_TRACK = 0x46, 101 MLX5_OBJ_TYPE_MKEY = 0xff01, 102 MLX5_OBJ_TYPE_QP = 0xff02, 103 MLX5_OBJ_TYPE_PSV = 0xff03, 104 MLX5_OBJ_TYPE_RMP = 0xff04, 105 MLX5_OBJ_TYPE_XRC_SRQ = 0xff05, 106 MLX5_OBJ_TYPE_RQ = 0xff06, 107 MLX5_OBJ_TYPE_SQ = 0xff07, 108 MLX5_OBJ_TYPE_TIR = 0xff08, 109 MLX5_OBJ_TYPE_TIS = 0xff09, 110 MLX5_OBJ_TYPE_DCT = 0xff0a, 111 MLX5_OBJ_TYPE_XRQ = 0xff0b, 112 MLX5_OBJ_TYPE_RQT = 0xff0e, 113 MLX5_OBJ_TYPE_FLOW_COUNTER = 0xff0f, 114 MLX5_OBJ_TYPE_CQ = 0xff10, 115 }; 116 117 enum { 118 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100, 119 MLX5_CMD_OP_QUERY_ADAPTER = 0x101, 120 MLX5_CMD_OP_INIT_HCA = 0x102, 121 MLX5_CMD_OP_TEARDOWN_HCA = 0x103, 122 MLX5_CMD_OP_ENABLE_HCA = 0x104, 123 MLX5_CMD_OP_DISABLE_HCA = 0x105, 124 MLX5_CMD_OP_QUERY_PAGES = 0x107, 125 MLX5_CMD_OP_MANAGE_PAGES = 0x108, 126 MLX5_CMD_OP_SET_HCA_CAP = 0x109, 127 MLX5_CMD_OP_QUERY_ISSI = 0x10a, 128 MLX5_CMD_OP_SET_ISSI = 0x10b, 129 MLX5_CMD_OP_SET_DRIVER_VERSION = 0x10d, 130 MLX5_CMD_OP_QUERY_SF_PARTITION = 0x111, 131 MLX5_CMD_OP_ALLOC_SF = 0x113, 132 MLX5_CMD_OP_DEALLOC_SF = 0x114, 133 MLX5_CMD_OP_SUSPEND_VHCA = 0x115, 134 MLX5_CMD_OP_RESUME_VHCA = 0x116, 135 MLX5_CMD_OP_QUERY_VHCA_MIGRATION_STATE = 0x117, 136 MLX5_CMD_OP_SAVE_VHCA_STATE = 0x118, 137 MLX5_CMD_OP_LOAD_VHCA_STATE = 0x119, 138 MLX5_CMD_OP_CREATE_MKEY = 0x200, 139 MLX5_CMD_OP_QUERY_MKEY = 0x201, 140 MLX5_CMD_OP_DESTROY_MKEY = 0x202, 141 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203, 142 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204, 143 MLX5_CMD_OP_ALLOC_MEMIC = 0x205, 144 MLX5_CMD_OP_DEALLOC_MEMIC = 0x206, 145 MLX5_CMD_OP_MODIFY_MEMIC = 0x207, 146 MLX5_CMD_OP_CREATE_EQ = 0x301, 147 MLX5_CMD_OP_DESTROY_EQ = 0x302, 148 MLX5_CMD_OP_QUERY_EQ = 0x303, 149 MLX5_CMD_OP_GEN_EQE = 0x304, 150 MLX5_CMD_OP_CREATE_CQ = 0x400, 151 MLX5_CMD_OP_DESTROY_CQ = 0x401, 152 MLX5_CMD_OP_QUERY_CQ = 0x402, 153 MLX5_CMD_OP_MODIFY_CQ = 0x403, 154 MLX5_CMD_OP_CREATE_QP = 0x500, 155 MLX5_CMD_OP_DESTROY_QP = 0x501, 156 MLX5_CMD_OP_RST2INIT_QP = 0x502, 157 MLX5_CMD_OP_INIT2RTR_QP = 0x503, 158 MLX5_CMD_OP_RTR2RTS_QP = 0x504, 159 MLX5_CMD_OP_RTS2RTS_QP = 0x505, 160 MLX5_CMD_OP_SQERR2RTS_QP = 0x506, 161 MLX5_CMD_OP_2ERR_QP = 0x507, 162 MLX5_CMD_OP_2RST_QP = 0x50a, 163 MLX5_CMD_OP_QUERY_QP = 0x50b, 164 MLX5_CMD_OP_SQD_RTS_QP = 0x50c, 165 MLX5_CMD_OP_INIT2INIT_QP = 0x50e, 166 MLX5_CMD_OP_CREATE_PSV = 0x600, 167 MLX5_CMD_OP_DESTROY_PSV = 0x601, 168 MLX5_CMD_OP_CREATE_SRQ = 0x700, 169 MLX5_CMD_OP_DESTROY_SRQ = 0x701, 170 MLX5_CMD_OP_QUERY_SRQ = 0x702, 171 MLX5_CMD_OP_ARM_RQ = 0x703, 172 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705, 173 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706, 174 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707, 175 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708, 176 MLX5_CMD_OP_CREATE_DCT = 0x710, 177 MLX5_CMD_OP_DESTROY_DCT = 0x711, 178 MLX5_CMD_OP_DRAIN_DCT = 0x712, 179 MLX5_CMD_OP_QUERY_DCT = 0x713, 180 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714, 181 MLX5_CMD_OP_CREATE_XRQ = 0x717, 182 MLX5_CMD_OP_DESTROY_XRQ = 0x718, 183 MLX5_CMD_OP_QUERY_XRQ = 0x719, 184 MLX5_CMD_OP_ARM_XRQ = 0x71a, 185 MLX5_CMD_OP_QUERY_XRQ_DC_PARAMS_ENTRY = 0x725, 186 MLX5_CMD_OP_SET_XRQ_DC_PARAMS_ENTRY = 0x726, 187 MLX5_CMD_OP_QUERY_XRQ_ERROR_PARAMS = 0x727, 188 MLX5_CMD_OP_RELEASE_XRQ_ERROR = 0x729, 189 MLX5_CMD_OP_MODIFY_XRQ = 0x72a, 190 MLX5_CMD_OP_QUERY_ESW_FUNCTIONS = 0x740, 191 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750, 192 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751, 193 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752, 194 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753, 195 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754, 196 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755, 197 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760, 198 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761, 199 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762, 200 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763, 201 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764, 202 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765, 203 MLX5_CMD_OP_QUERY_VNIC_ENV = 0x76f, 204 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770, 205 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771, 206 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772, 207 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773, 208 MLX5_CMD_OP_SET_MONITOR_COUNTER = 0x774, 209 MLX5_CMD_OP_ARM_MONITOR_COUNTER = 0x775, 210 MLX5_CMD_OP_SET_PP_RATE_LIMIT = 0x780, 211 MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781, 212 MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT = 0x782, 213 MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT = 0x783, 214 MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT = 0x784, 215 MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT = 0x785, 216 MLX5_CMD_OP_CREATE_QOS_PARA_VPORT = 0x786, 217 MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT = 0x787, 218 MLX5_CMD_OP_ALLOC_PD = 0x800, 219 MLX5_CMD_OP_DEALLOC_PD = 0x801, 220 MLX5_CMD_OP_ALLOC_UAR = 0x802, 221 MLX5_CMD_OP_DEALLOC_UAR = 0x803, 222 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804, 223 MLX5_CMD_OP_ACCESS_REG = 0x805, 224 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806, 225 MLX5_CMD_OP_DETACH_FROM_MCG = 0x807, 226 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a, 227 MLX5_CMD_OP_MAD_IFC = 0x50d, 228 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b, 229 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c, 230 MLX5_CMD_OP_NOP = 0x80d, 231 MLX5_CMD_OP_ALLOC_XRCD = 0x80e, 232 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f, 233 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816, 234 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817, 235 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822, 236 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823, 237 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824, 238 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825, 239 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826, 240 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827, 241 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828, 242 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829, 243 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a, 244 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b, 245 MLX5_CMD_OP_SET_WOL_ROL = 0x830, 246 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831, 247 MLX5_CMD_OP_CREATE_LAG = 0x840, 248 MLX5_CMD_OP_MODIFY_LAG = 0x841, 249 MLX5_CMD_OP_QUERY_LAG = 0x842, 250 MLX5_CMD_OP_DESTROY_LAG = 0x843, 251 MLX5_CMD_OP_CREATE_VPORT_LAG = 0x844, 252 MLX5_CMD_OP_DESTROY_VPORT_LAG = 0x845, 253 MLX5_CMD_OP_CREATE_TIR = 0x900, 254 MLX5_CMD_OP_MODIFY_TIR = 0x901, 255 MLX5_CMD_OP_DESTROY_TIR = 0x902, 256 MLX5_CMD_OP_QUERY_TIR = 0x903, 257 MLX5_CMD_OP_CREATE_SQ = 0x904, 258 MLX5_CMD_OP_MODIFY_SQ = 0x905, 259 MLX5_CMD_OP_DESTROY_SQ = 0x906, 260 MLX5_CMD_OP_QUERY_SQ = 0x907, 261 MLX5_CMD_OP_CREATE_RQ = 0x908, 262 MLX5_CMD_OP_MODIFY_RQ = 0x909, 263 MLX5_CMD_OP_SET_DELAY_DROP_PARAMS = 0x910, 264 MLX5_CMD_OP_DESTROY_RQ = 0x90a, 265 MLX5_CMD_OP_QUERY_RQ = 0x90b, 266 MLX5_CMD_OP_CREATE_RMP = 0x90c, 267 MLX5_CMD_OP_MODIFY_RMP = 0x90d, 268 MLX5_CMD_OP_DESTROY_RMP = 0x90e, 269 MLX5_CMD_OP_QUERY_RMP = 0x90f, 270 MLX5_CMD_OP_CREATE_TIS = 0x912, 271 MLX5_CMD_OP_MODIFY_TIS = 0x913, 272 MLX5_CMD_OP_DESTROY_TIS = 0x914, 273 MLX5_CMD_OP_QUERY_TIS = 0x915, 274 MLX5_CMD_OP_CREATE_RQT = 0x916, 275 MLX5_CMD_OP_MODIFY_RQT = 0x917, 276 MLX5_CMD_OP_DESTROY_RQT = 0x918, 277 MLX5_CMD_OP_QUERY_RQT = 0x919, 278 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f, 279 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930, 280 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931, 281 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932, 282 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933, 283 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934, 284 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935, 285 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936, 286 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937, 287 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938, 288 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939, 289 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a, 290 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b, 291 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c, 292 MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT = 0x93d, 293 MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT = 0x93e, 294 MLX5_CMD_OP_QUERY_PACKET_REFORMAT_CONTEXT = 0x93f, 295 MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT = 0x940, 296 MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941, 297 MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT = 0x942, 298 MLX5_CMD_OP_FPGA_CREATE_QP = 0x960, 299 MLX5_CMD_OP_FPGA_MODIFY_QP = 0x961, 300 MLX5_CMD_OP_FPGA_QUERY_QP = 0x962, 301 MLX5_CMD_OP_FPGA_DESTROY_QP = 0x963, 302 MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS = 0x964, 303 MLX5_CMD_OP_CREATE_GENERAL_OBJECT = 0xa00, 304 MLX5_CMD_OP_MODIFY_GENERAL_OBJECT = 0xa01, 305 MLX5_CMD_OP_QUERY_GENERAL_OBJECT = 0xa02, 306 MLX5_CMD_OP_DESTROY_GENERAL_OBJECT = 0xa03, 307 MLX5_CMD_OP_CREATE_UCTX = 0xa04, 308 MLX5_CMD_OP_DESTROY_UCTX = 0xa06, 309 MLX5_CMD_OP_CREATE_UMEM = 0xa08, 310 MLX5_CMD_OP_DESTROY_UMEM = 0xa0a, 311 MLX5_CMD_OP_SYNC_STEERING = 0xb00, 312 MLX5_CMD_OP_QUERY_VHCA_STATE = 0xb0d, 313 MLX5_CMD_OP_MODIFY_VHCA_STATE = 0xb0e, 314 MLX5_CMD_OP_SYNC_CRYPTO = 0xb12, 315 MLX5_CMD_OP_ALLOW_OTHER_VHCA_ACCESS = 0xb16, 316 MLX5_CMD_OP_MAX 317 }; 318 319 /* Valid range for general commands that don't work over an object */ 320 enum { 321 MLX5_CMD_OP_GENERAL_START = 0xb00, 322 MLX5_CMD_OP_GENERAL_END = 0xd00, 323 }; 324 325 enum { 326 MLX5_FT_NIC_RX_2_NIC_RX_RDMA = BIT(0), 327 MLX5_FT_NIC_TX_RDMA_2_NIC_TX = BIT(1), 328 }; 329 330 enum { 331 MLX5_CMD_OP_MOD_UPDATE_HEADER_MODIFY_ARGUMENT = 0x1, 332 }; 333 334 struct mlx5_ifc_flow_table_fields_supported_bits { 335 u8 outer_dmac[0x1]; 336 u8 outer_smac[0x1]; 337 u8 outer_ether_type[0x1]; 338 u8 outer_ip_version[0x1]; 339 u8 outer_first_prio[0x1]; 340 u8 outer_first_cfi[0x1]; 341 u8 outer_first_vid[0x1]; 342 u8 outer_ipv4_ttl[0x1]; 343 u8 outer_second_prio[0x1]; 344 u8 outer_second_cfi[0x1]; 345 u8 outer_second_vid[0x1]; 346 u8 reserved_at_b[0x1]; 347 u8 outer_sip[0x1]; 348 u8 outer_dip[0x1]; 349 u8 outer_frag[0x1]; 350 u8 outer_ip_protocol[0x1]; 351 u8 outer_ip_ecn[0x1]; 352 u8 outer_ip_dscp[0x1]; 353 u8 outer_udp_sport[0x1]; 354 u8 outer_udp_dport[0x1]; 355 u8 outer_tcp_sport[0x1]; 356 u8 outer_tcp_dport[0x1]; 357 u8 outer_tcp_flags[0x1]; 358 u8 outer_gre_protocol[0x1]; 359 u8 outer_gre_key[0x1]; 360 u8 outer_vxlan_vni[0x1]; 361 u8 outer_geneve_vni[0x1]; 362 u8 outer_geneve_oam[0x1]; 363 u8 outer_geneve_protocol_type[0x1]; 364 u8 outer_geneve_opt_len[0x1]; 365 u8 source_vhca_port[0x1]; 366 u8 source_eswitch_port[0x1]; 367 368 u8 inner_dmac[0x1]; 369 u8 inner_smac[0x1]; 370 u8 inner_ether_type[0x1]; 371 u8 inner_ip_version[0x1]; 372 u8 inner_first_prio[0x1]; 373 u8 inner_first_cfi[0x1]; 374 u8 inner_first_vid[0x1]; 375 u8 reserved_at_27[0x1]; 376 u8 inner_second_prio[0x1]; 377 u8 inner_second_cfi[0x1]; 378 u8 inner_second_vid[0x1]; 379 u8 reserved_at_2b[0x1]; 380 u8 inner_sip[0x1]; 381 u8 inner_dip[0x1]; 382 u8 inner_frag[0x1]; 383 u8 inner_ip_protocol[0x1]; 384 u8 inner_ip_ecn[0x1]; 385 u8 inner_ip_dscp[0x1]; 386 u8 inner_udp_sport[0x1]; 387 u8 inner_udp_dport[0x1]; 388 u8 inner_tcp_sport[0x1]; 389 u8 inner_tcp_dport[0x1]; 390 u8 inner_tcp_flags[0x1]; 391 u8 reserved_at_37[0x9]; 392 393 u8 geneve_tlv_option_0_data[0x1]; 394 u8 geneve_tlv_option_0_exist[0x1]; 395 u8 reserved_at_42[0x3]; 396 u8 outer_first_mpls_over_udp[0x4]; 397 u8 outer_first_mpls_over_gre[0x4]; 398 u8 inner_first_mpls[0x4]; 399 u8 outer_first_mpls[0x4]; 400 u8 reserved_at_55[0x2]; 401 u8 outer_esp_spi[0x1]; 402 u8 reserved_at_58[0x2]; 403 u8 bth_dst_qp[0x1]; 404 u8 reserved_at_5b[0x5]; 405 406 u8 reserved_at_60[0x18]; 407 u8 metadata_reg_c_7[0x1]; 408 u8 metadata_reg_c_6[0x1]; 409 u8 metadata_reg_c_5[0x1]; 410 u8 metadata_reg_c_4[0x1]; 411 u8 metadata_reg_c_3[0x1]; 412 u8 metadata_reg_c_2[0x1]; 413 u8 metadata_reg_c_1[0x1]; 414 u8 metadata_reg_c_0[0x1]; 415 }; 416 417 /* Table 2170 - Flow Table Fields Supported 2 Format */ 418 struct mlx5_ifc_flow_table_fields_supported_2_bits { 419 u8 reserved_at_0[0xe]; 420 u8 bth_opcode[0x1]; 421 u8 reserved_at_f[0x1]; 422 u8 tunnel_header_0_1[0x1]; 423 u8 reserved_at_11[0xf]; 424 425 u8 reserved_at_20[0x60]; 426 }; 427 428 struct mlx5_ifc_flow_table_prop_layout_bits { 429 u8 ft_support[0x1]; 430 u8 reserved_at_1[0x1]; 431 u8 flow_counter[0x1]; 432 u8 flow_modify_en[0x1]; 433 u8 modify_root[0x1]; 434 u8 identified_miss_table_mode[0x1]; 435 u8 flow_table_modify[0x1]; 436 u8 reformat[0x1]; 437 u8 decap[0x1]; 438 u8 reserved_at_9[0x1]; 439 u8 pop_vlan[0x1]; 440 u8 push_vlan[0x1]; 441 u8 reserved_at_c[0x1]; 442 u8 pop_vlan_2[0x1]; 443 u8 push_vlan_2[0x1]; 444 u8 reformat_and_vlan_action[0x1]; 445 u8 reserved_at_10[0x1]; 446 u8 sw_owner[0x1]; 447 u8 reformat_l3_tunnel_to_l2[0x1]; 448 u8 reformat_l2_to_l3_tunnel[0x1]; 449 u8 reformat_and_modify_action[0x1]; 450 u8 ignore_flow_level[0x1]; 451 u8 reserved_at_16[0x1]; 452 u8 table_miss_action_domain[0x1]; 453 u8 termination_table[0x1]; 454 u8 reformat_and_fwd_to_table[0x1]; 455 u8 reserved_at_1a[0x2]; 456 u8 ipsec_encrypt[0x1]; 457 u8 ipsec_decrypt[0x1]; 458 u8 sw_owner_v2[0x1]; 459 u8 reserved_at_1f[0x1]; 460 461 u8 termination_table_raw_traffic[0x1]; 462 u8 reserved_at_21[0x1]; 463 u8 log_max_ft_size[0x6]; 464 u8 log_max_modify_header_context[0x8]; 465 u8 max_modify_header_actions[0x8]; 466 u8 max_ft_level[0x8]; 467 468 u8 reformat_add_esp_trasport[0x1]; 469 u8 reformat_l2_to_l3_esp_tunnel[0x1]; 470 u8 reformat_add_esp_transport_over_udp[0x1]; 471 u8 reformat_del_esp_trasport[0x1]; 472 u8 reformat_l3_esp_tunnel_to_l2[0x1]; 473 u8 reformat_del_esp_transport_over_udp[0x1]; 474 u8 execute_aso[0x1]; 475 u8 reserved_at_47[0x19]; 476 477 u8 reserved_at_60[0x2]; 478 u8 reformat_insert[0x1]; 479 u8 reformat_remove[0x1]; 480 u8 macsec_encrypt[0x1]; 481 u8 macsec_decrypt[0x1]; 482 u8 reserved_at_66[0x2]; 483 u8 reformat_add_macsec[0x1]; 484 u8 reformat_remove_macsec[0x1]; 485 u8 reserved_at_6a[0xe]; 486 u8 log_max_ft_num[0x8]; 487 488 u8 reserved_at_80[0x10]; 489 u8 log_max_flow_counter[0x8]; 490 u8 log_max_destination[0x8]; 491 492 u8 reserved_at_a0[0x18]; 493 u8 log_max_flow[0x8]; 494 495 u8 reserved_at_c0[0x40]; 496 497 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support; 498 499 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support; 500 }; 501 502 struct mlx5_ifc_odp_per_transport_service_cap_bits { 503 u8 send[0x1]; 504 u8 receive[0x1]; 505 u8 write[0x1]; 506 u8 read[0x1]; 507 u8 atomic[0x1]; 508 u8 srq_receive[0x1]; 509 u8 reserved_at_6[0x1a]; 510 }; 511 512 struct mlx5_ifc_ipv4_layout_bits { 513 u8 reserved_at_0[0x60]; 514 515 u8 ipv4[0x20]; 516 }; 517 518 struct mlx5_ifc_ipv6_layout_bits { 519 u8 ipv6[16][0x8]; 520 }; 521 522 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits { 523 struct mlx5_ifc_ipv6_layout_bits ipv6_layout; 524 struct mlx5_ifc_ipv4_layout_bits ipv4_layout; 525 u8 reserved_at_0[0x80]; 526 }; 527 528 struct mlx5_ifc_fte_match_set_lyr_2_4_bits { 529 u8 smac_47_16[0x20]; 530 531 u8 smac_15_0[0x10]; 532 u8 ethertype[0x10]; 533 534 u8 dmac_47_16[0x20]; 535 536 u8 dmac_15_0[0x10]; 537 u8 first_prio[0x3]; 538 u8 first_cfi[0x1]; 539 u8 first_vid[0xc]; 540 541 u8 ip_protocol[0x8]; 542 u8 ip_dscp[0x6]; 543 u8 ip_ecn[0x2]; 544 u8 cvlan_tag[0x1]; 545 u8 svlan_tag[0x1]; 546 u8 frag[0x1]; 547 u8 ip_version[0x4]; 548 u8 tcp_flags[0x9]; 549 550 u8 tcp_sport[0x10]; 551 u8 tcp_dport[0x10]; 552 553 u8 reserved_at_c0[0x10]; 554 u8 ipv4_ihl[0x4]; 555 u8 reserved_at_c4[0x4]; 556 557 u8 ttl_hoplimit[0x8]; 558 559 u8 udp_sport[0x10]; 560 u8 udp_dport[0x10]; 561 562 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6; 563 564 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6; 565 }; 566 567 struct mlx5_ifc_nvgre_key_bits { 568 u8 hi[0x18]; 569 u8 lo[0x8]; 570 }; 571 572 union mlx5_ifc_gre_key_bits { 573 struct mlx5_ifc_nvgre_key_bits nvgre; 574 u8 key[0x20]; 575 }; 576 577 struct mlx5_ifc_fte_match_set_misc_bits { 578 u8 gre_c_present[0x1]; 579 u8 reserved_at_1[0x1]; 580 u8 gre_k_present[0x1]; 581 u8 gre_s_present[0x1]; 582 u8 source_vhca_port[0x4]; 583 u8 source_sqn[0x18]; 584 585 u8 source_eswitch_owner_vhca_id[0x10]; 586 u8 source_port[0x10]; 587 588 u8 outer_second_prio[0x3]; 589 u8 outer_second_cfi[0x1]; 590 u8 outer_second_vid[0xc]; 591 u8 inner_second_prio[0x3]; 592 u8 inner_second_cfi[0x1]; 593 u8 inner_second_vid[0xc]; 594 595 u8 outer_second_cvlan_tag[0x1]; 596 u8 inner_second_cvlan_tag[0x1]; 597 u8 outer_second_svlan_tag[0x1]; 598 u8 inner_second_svlan_tag[0x1]; 599 u8 reserved_at_64[0xc]; 600 u8 gre_protocol[0x10]; 601 602 union mlx5_ifc_gre_key_bits gre_key; 603 604 u8 vxlan_vni[0x18]; 605 u8 bth_opcode[0x8]; 606 607 u8 geneve_vni[0x18]; 608 u8 reserved_at_d8[0x6]; 609 u8 geneve_tlv_option_0_exist[0x1]; 610 u8 geneve_oam[0x1]; 611 612 u8 reserved_at_e0[0xc]; 613 u8 outer_ipv6_flow_label[0x14]; 614 615 u8 reserved_at_100[0xc]; 616 u8 inner_ipv6_flow_label[0x14]; 617 618 u8 reserved_at_120[0xa]; 619 u8 geneve_opt_len[0x6]; 620 u8 geneve_protocol_type[0x10]; 621 622 u8 reserved_at_140[0x8]; 623 u8 bth_dst_qp[0x18]; 624 u8 reserved_at_160[0x20]; 625 u8 outer_esp_spi[0x20]; 626 u8 reserved_at_1a0[0x60]; 627 }; 628 629 struct mlx5_ifc_fte_match_mpls_bits { 630 u8 mpls_label[0x14]; 631 u8 mpls_exp[0x3]; 632 u8 mpls_s_bos[0x1]; 633 u8 mpls_ttl[0x8]; 634 }; 635 636 struct mlx5_ifc_fte_match_set_misc2_bits { 637 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls; 638 639 struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls; 640 641 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre; 642 643 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp; 644 645 u8 metadata_reg_c_7[0x20]; 646 647 u8 metadata_reg_c_6[0x20]; 648 649 u8 metadata_reg_c_5[0x20]; 650 651 u8 metadata_reg_c_4[0x20]; 652 653 u8 metadata_reg_c_3[0x20]; 654 655 u8 metadata_reg_c_2[0x20]; 656 657 u8 metadata_reg_c_1[0x20]; 658 659 u8 metadata_reg_c_0[0x20]; 660 661 u8 metadata_reg_a[0x20]; 662 663 u8 reserved_at_1a0[0x8]; 664 665 u8 macsec_syndrome[0x8]; 666 u8 ipsec_syndrome[0x8]; 667 u8 reserved_at_1b8[0x8]; 668 669 u8 reserved_at_1c0[0x40]; 670 }; 671 672 struct mlx5_ifc_fte_match_set_misc3_bits { 673 u8 inner_tcp_seq_num[0x20]; 674 675 u8 outer_tcp_seq_num[0x20]; 676 677 u8 inner_tcp_ack_num[0x20]; 678 679 u8 outer_tcp_ack_num[0x20]; 680 681 u8 reserved_at_80[0x8]; 682 u8 outer_vxlan_gpe_vni[0x18]; 683 684 u8 outer_vxlan_gpe_next_protocol[0x8]; 685 u8 outer_vxlan_gpe_flags[0x8]; 686 u8 reserved_at_b0[0x10]; 687 688 u8 icmp_header_data[0x20]; 689 690 u8 icmpv6_header_data[0x20]; 691 692 u8 icmp_type[0x8]; 693 u8 icmp_code[0x8]; 694 u8 icmpv6_type[0x8]; 695 u8 icmpv6_code[0x8]; 696 697 u8 geneve_tlv_option_0_data[0x20]; 698 699 u8 gtpu_teid[0x20]; 700 701 u8 gtpu_msg_type[0x8]; 702 u8 gtpu_msg_flags[0x8]; 703 u8 reserved_at_170[0x10]; 704 705 u8 gtpu_dw_2[0x20]; 706 707 u8 gtpu_first_ext_dw_0[0x20]; 708 709 u8 gtpu_dw_0[0x20]; 710 711 u8 reserved_at_1e0[0x20]; 712 }; 713 714 struct mlx5_ifc_fte_match_set_misc4_bits { 715 u8 prog_sample_field_value_0[0x20]; 716 717 u8 prog_sample_field_id_0[0x20]; 718 719 u8 prog_sample_field_value_1[0x20]; 720 721 u8 prog_sample_field_id_1[0x20]; 722 723 u8 prog_sample_field_value_2[0x20]; 724 725 u8 prog_sample_field_id_2[0x20]; 726 727 u8 prog_sample_field_value_3[0x20]; 728 729 u8 prog_sample_field_id_3[0x20]; 730 731 u8 reserved_at_100[0x100]; 732 }; 733 734 struct mlx5_ifc_fte_match_set_misc5_bits { 735 u8 macsec_tag_0[0x20]; 736 737 u8 macsec_tag_1[0x20]; 738 739 u8 macsec_tag_2[0x20]; 740 741 u8 macsec_tag_3[0x20]; 742 743 u8 tunnel_header_0[0x20]; 744 745 u8 tunnel_header_1[0x20]; 746 747 u8 tunnel_header_2[0x20]; 748 749 u8 tunnel_header_3[0x20]; 750 751 u8 reserved_at_100[0x100]; 752 }; 753 754 struct mlx5_ifc_cmd_pas_bits { 755 u8 pa_h[0x20]; 756 757 u8 pa_l[0x14]; 758 u8 reserved_at_34[0xc]; 759 }; 760 761 struct mlx5_ifc_uint64_bits { 762 u8 hi[0x20]; 763 764 u8 lo[0x20]; 765 }; 766 767 enum { 768 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0, 769 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7, 770 MLX5_ADS_STAT_RATE_10GBPS = 0x8, 771 MLX5_ADS_STAT_RATE_30GBPS = 0x9, 772 MLX5_ADS_STAT_RATE_5GBPS = 0xa, 773 MLX5_ADS_STAT_RATE_20GBPS = 0xb, 774 MLX5_ADS_STAT_RATE_40GBPS = 0xc, 775 MLX5_ADS_STAT_RATE_60GBPS = 0xd, 776 MLX5_ADS_STAT_RATE_80GBPS = 0xe, 777 MLX5_ADS_STAT_RATE_120GBPS = 0xf, 778 }; 779 780 struct mlx5_ifc_ads_bits { 781 u8 fl[0x1]; 782 u8 free_ar[0x1]; 783 u8 reserved_at_2[0xe]; 784 u8 pkey_index[0x10]; 785 786 u8 reserved_at_20[0x8]; 787 u8 grh[0x1]; 788 u8 mlid[0x7]; 789 u8 rlid[0x10]; 790 791 u8 ack_timeout[0x5]; 792 u8 reserved_at_45[0x3]; 793 u8 src_addr_index[0x8]; 794 u8 reserved_at_50[0x4]; 795 u8 stat_rate[0x4]; 796 u8 hop_limit[0x8]; 797 798 u8 reserved_at_60[0x4]; 799 u8 tclass[0x8]; 800 u8 flow_label[0x14]; 801 802 u8 rgid_rip[16][0x8]; 803 804 u8 reserved_at_100[0x4]; 805 u8 f_dscp[0x1]; 806 u8 f_ecn[0x1]; 807 u8 reserved_at_106[0x1]; 808 u8 f_eth_prio[0x1]; 809 u8 ecn[0x2]; 810 u8 dscp[0x6]; 811 u8 udp_sport[0x10]; 812 813 u8 dei_cfi[0x1]; 814 u8 eth_prio[0x3]; 815 u8 sl[0x4]; 816 u8 vhca_port_num[0x8]; 817 u8 rmac_47_32[0x10]; 818 819 u8 rmac_31_0[0x20]; 820 }; 821 822 struct mlx5_ifc_flow_table_nic_cap_bits { 823 u8 nic_rx_multi_path_tirs[0x1]; 824 u8 nic_rx_multi_path_tirs_fts[0x1]; 825 u8 allow_sniffer_and_nic_rx_shared_tir[0x1]; 826 u8 reserved_at_3[0x4]; 827 u8 sw_owner_reformat_supported[0x1]; 828 u8 reserved_at_8[0x18]; 829 830 u8 encap_general_header[0x1]; 831 u8 reserved_at_21[0xa]; 832 u8 log_max_packet_reformat_context[0x5]; 833 u8 reserved_at_30[0x6]; 834 u8 max_encap_header_size[0xa]; 835 u8 reserved_at_40[0x1c0]; 836 837 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive; 838 839 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_rdma; 840 841 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer; 842 843 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit; 844 845 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_rdma; 846 847 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer; 848 849 u8 reserved_at_e00[0x700]; 850 851 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_receive_rdma; 852 853 u8 reserved_at_1580[0x280]; 854 855 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_transmit_rdma; 856 857 u8 reserved_at_1880[0x780]; 858 859 u8 sw_steering_nic_rx_action_drop_icm_address[0x40]; 860 861 u8 sw_steering_nic_tx_action_drop_icm_address[0x40]; 862 863 u8 sw_steering_nic_tx_action_allow_icm_address[0x40]; 864 865 u8 reserved_at_20c0[0x5f40]; 866 }; 867 868 struct mlx5_ifc_port_selection_cap_bits { 869 u8 reserved_at_0[0x10]; 870 u8 port_select_flow_table[0x1]; 871 u8 reserved_at_11[0x1]; 872 u8 port_select_flow_table_bypass[0x1]; 873 u8 reserved_at_13[0xd]; 874 875 u8 reserved_at_20[0x1e0]; 876 877 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_port_selection; 878 879 u8 reserved_at_400[0x7c00]; 880 }; 881 882 enum { 883 MLX5_FDB_TO_VPORT_REG_C_0 = 0x01, 884 MLX5_FDB_TO_VPORT_REG_C_1 = 0x02, 885 MLX5_FDB_TO_VPORT_REG_C_2 = 0x04, 886 MLX5_FDB_TO_VPORT_REG_C_3 = 0x08, 887 MLX5_FDB_TO_VPORT_REG_C_4 = 0x10, 888 MLX5_FDB_TO_VPORT_REG_C_5 = 0x20, 889 MLX5_FDB_TO_VPORT_REG_C_6 = 0x40, 890 MLX5_FDB_TO_VPORT_REG_C_7 = 0x80, 891 }; 892 893 struct mlx5_ifc_flow_table_eswitch_cap_bits { 894 u8 fdb_to_vport_reg_c_id[0x8]; 895 u8 reserved_at_8[0x5]; 896 u8 fdb_uplink_hairpin[0x1]; 897 u8 fdb_multi_path_any_table_limit_regc[0x1]; 898 u8 reserved_at_f[0x3]; 899 u8 fdb_multi_path_any_table[0x1]; 900 u8 reserved_at_13[0x2]; 901 u8 fdb_modify_header_fwd_to_table[0x1]; 902 u8 fdb_ipv4_ttl_modify[0x1]; 903 u8 flow_source[0x1]; 904 u8 reserved_at_18[0x2]; 905 u8 multi_fdb_encap[0x1]; 906 u8 egress_acl_forward_to_vport[0x1]; 907 u8 fdb_multi_path_to_table[0x1]; 908 u8 reserved_at_1d[0x3]; 909 910 u8 reserved_at_20[0x1e0]; 911 912 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb; 913 914 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress; 915 916 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress; 917 918 u8 reserved_at_800[0xC00]; 919 920 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_esw_fdb; 921 922 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_bitmask_support_2_esw_fdb; 923 924 u8 reserved_at_1500[0x300]; 925 926 u8 sw_steering_fdb_action_drop_icm_address_rx[0x40]; 927 928 u8 sw_steering_fdb_action_drop_icm_address_tx[0x40]; 929 930 u8 sw_steering_uplink_icm_address_rx[0x40]; 931 932 u8 sw_steering_uplink_icm_address_tx[0x40]; 933 934 u8 reserved_at_1900[0x6700]; 935 }; 936 937 enum { 938 MLX5_COUNTER_SOURCE_ESWITCH = 0x0, 939 MLX5_COUNTER_FLOW_ESWITCH = 0x1, 940 }; 941 942 struct mlx5_ifc_e_switch_cap_bits { 943 u8 vport_svlan_strip[0x1]; 944 u8 vport_cvlan_strip[0x1]; 945 u8 vport_svlan_insert[0x1]; 946 u8 vport_cvlan_insert_if_not_exist[0x1]; 947 u8 vport_cvlan_insert_overwrite[0x1]; 948 u8 reserved_at_5[0x1]; 949 u8 vport_cvlan_insert_always[0x1]; 950 u8 esw_shared_ingress_acl[0x1]; 951 u8 esw_uplink_ingress_acl[0x1]; 952 u8 root_ft_on_other_esw[0x1]; 953 u8 reserved_at_a[0xf]; 954 u8 esw_functions_changed[0x1]; 955 u8 reserved_at_1a[0x1]; 956 u8 ecpf_vport_exists[0x1]; 957 u8 counter_eswitch_affinity[0x1]; 958 u8 merged_eswitch[0x1]; 959 u8 nic_vport_node_guid_modify[0x1]; 960 u8 nic_vport_port_guid_modify[0x1]; 961 962 u8 vxlan_encap_decap[0x1]; 963 u8 nvgre_encap_decap[0x1]; 964 u8 reserved_at_22[0x1]; 965 u8 log_max_fdb_encap_uplink[0x5]; 966 u8 reserved_at_21[0x3]; 967 u8 log_max_packet_reformat_context[0x5]; 968 u8 reserved_2b[0x6]; 969 u8 max_encap_header_size[0xa]; 970 971 u8 reserved_at_40[0xb]; 972 u8 log_max_esw_sf[0x5]; 973 u8 esw_sf_base_id[0x10]; 974 975 u8 reserved_at_60[0x7a0]; 976 977 }; 978 979 struct mlx5_ifc_qos_cap_bits { 980 u8 packet_pacing[0x1]; 981 u8 esw_scheduling[0x1]; 982 u8 esw_bw_share[0x1]; 983 u8 esw_rate_limit[0x1]; 984 u8 reserved_at_4[0x1]; 985 u8 packet_pacing_burst_bound[0x1]; 986 u8 packet_pacing_typical_size[0x1]; 987 u8 reserved_at_7[0x1]; 988 u8 nic_sq_scheduling[0x1]; 989 u8 nic_bw_share[0x1]; 990 u8 nic_rate_limit[0x1]; 991 u8 packet_pacing_uid[0x1]; 992 u8 log_esw_max_sched_depth[0x4]; 993 u8 reserved_at_10[0x10]; 994 995 u8 reserved_at_20[0xb]; 996 u8 log_max_qos_nic_queue_group[0x5]; 997 u8 reserved_at_30[0x10]; 998 999 u8 packet_pacing_max_rate[0x20]; 1000 1001 u8 packet_pacing_min_rate[0x20]; 1002 1003 u8 reserved_at_80[0x10]; 1004 u8 packet_pacing_rate_table_size[0x10]; 1005 1006 u8 esw_element_type[0x10]; 1007 u8 esw_tsar_type[0x10]; 1008 1009 u8 reserved_at_c0[0x10]; 1010 u8 max_qos_para_vport[0x10]; 1011 1012 u8 max_tsar_bw_share[0x20]; 1013 1014 u8 reserved_at_100[0x20]; 1015 1016 u8 reserved_at_120[0x3]; 1017 u8 log_meter_aso_granularity[0x5]; 1018 u8 reserved_at_128[0x3]; 1019 u8 log_meter_aso_max_alloc[0x5]; 1020 u8 reserved_at_130[0x3]; 1021 u8 log_max_num_meter_aso[0x5]; 1022 u8 reserved_at_138[0x8]; 1023 1024 u8 reserved_at_140[0x6c0]; 1025 }; 1026 1027 struct mlx5_ifc_debug_cap_bits { 1028 u8 core_dump_general[0x1]; 1029 u8 core_dump_qp[0x1]; 1030 u8 reserved_at_2[0x7]; 1031 u8 resource_dump[0x1]; 1032 u8 reserved_at_a[0x16]; 1033 1034 u8 reserved_at_20[0x2]; 1035 u8 stall_detect[0x1]; 1036 u8 reserved_at_23[0x1d]; 1037 1038 u8 reserved_at_40[0x7c0]; 1039 }; 1040 1041 struct mlx5_ifc_per_protocol_networking_offload_caps_bits { 1042 u8 csum_cap[0x1]; 1043 u8 vlan_cap[0x1]; 1044 u8 lro_cap[0x1]; 1045 u8 lro_psh_flag[0x1]; 1046 u8 lro_time_stamp[0x1]; 1047 u8 reserved_at_5[0x2]; 1048 u8 wqe_vlan_insert[0x1]; 1049 u8 self_lb_en_modifiable[0x1]; 1050 u8 reserved_at_9[0x2]; 1051 u8 max_lso_cap[0x5]; 1052 u8 multi_pkt_send_wqe[0x2]; 1053 u8 wqe_inline_mode[0x2]; 1054 u8 rss_ind_tbl_cap[0x4]; 1055 u8 reg_umr_sq[0x1]; 1056 u8 scatter_fcs[0x1]; 1057 u8 enhanced_multi_pkt_send_wqe[0x1]; 1058 u8 tunnel_lso_const_out_ip_id[0x1]; 1059 u8 tunnel_lro_gre[0x1]; 1060 u8 tunnel_lro_vxlan[0x1]; 1061 u8 tunnel_stateless_gre[0x1]; 1062 u8 tunnel_stateless_vxlan[0x1]; 1063 1064 u8 swp[0x1]; 1065 u8 swp_csum[0x1]; 1066 u8 swp_lso[0x1]; 1067 u8 cqe_checksum_full[0x1]; 1068 u8 tunnel_stateless_geneve_tx[0x1]; 1069 u8 tunnel_stateless_mpls_over_udp[0x1]; 1070 u8 tunnel_stateless_mpls_over_gre[0x1]; 1071 u8 tunnel_stateless_vxlan_gpe[0x1]; 1072 u8 tunnel_stateless_ipv4_over_vxlan[0x1]; 1073 u8 tunnel_stateless_ip_over_ip[0x1]; 1074 u8 insert_trailer[0x1]; 1075 u8 reserved_at_2b[0x1]; 1076 u8 tunnel_stateless_ip_over_ip_rx[0x1]; 1077 u8 tunnel_stateless_ip_over_ip_tx[0x1]; 1078 u8 reserved_at_2e[0x2]; 1079 u8 max_vxlan_udp_ports[0x8]; 1080 u8 reserved_at_38[0x6]; 1081 u8 max_geneve_opt_len[0x1]; 1082 u8 tunnel_stateless_geneve_rx[0x1]; 1083 1084 u8 reserved_at_40[0x10]; 1085 u8 lro_min_mss_size[0x10]; 1086 1087 u8 reserved_at_60[0x120]; 1088 1089 u8 lro_timer_supported_periods[4][0x20]; 1090 1091 u8 reserved_at_200[0x600]; 1092 }; 1093 1094 enum { 1095 MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING = 0x0, 1096 MLX5_TIMESTAMP_FORMAT_CAP_REAL_TIME = 0x1, 1097 MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING_AND_REAL_TIME = 0x2, 1098 }; 1099 1100 struct mlx5_ifc_roce_cap_bits { 1101 u8 roce_apm[0x1]; 1102 u8 reserved_at_1[0x3]; 1103 u8 sw_r_roce_src_udp_port[0x1]; 1104 u8 fl_rc_qp_when_roce_disabled[0x1]; 1105 u8 fl_rc_qp_when_roce_enabled[0x1]; 1106 u8 reserved_at_7[0x1]; 1107 u8 qp_ooo_transmit_default[0x1]; 1108 u8 reserved_at_9[0x15]; 1109 u8 qp_ts_format[0x2]; 1110 1111 u8 reserved_at_20[0x60]; 1112 1113 u8 reserved_at_80[0xc]; 1114 u8 l3_type[0x4]; 1115 u8 reserved_at_90[0x8]; 1116 u8 roce_version[0x8]; 1117 1118 u8 reserved_at_a0[0x10]; 1119 u8 r_roce_dest_udp_port[0x10]; 1120 1121 u8 r_roce_max_src_udp_port[0x10]; 1122 u8 r_roce_min_src_udp_port[0x10]; 1123 1124 u8 reserved_at_e0[0x10]; 1125 u8 roce_address_table_size[0x10]; 1126 1127 u8 reserved_at_100[0x700]; 1128 }; 1129 1130 struct mlx5_ifc_sync_steering_in_bits { 1131 u8 opcode[0x10]; 1132 u8 uid[0x10]; 1133 1134 u8 reserved_at_20[0x10]; 1135 u8 op_mod[0x10]; 1136 1137 u8 reserved_at_40[0xc0]; 1138 }; 1139 1140 struct mlx5_ifc_sync_steering_out_bits { 1141 u8 status[0x8]; 1142 u8 reserved_at_8[0x18]; 1143 1144 u8 syndrome[0x20]; 1145 1146 u8 reserved_at_40[0x40]; 1147 }; 1148 1149 struct mlx5_ifc_sync_crypto_in_bits { 1150 u8 opcode[0x10]; 1151 u8 uid[0x10]; 1152 1153 u8 reserved_at_20[0x10]; 1154 u8 op_mod[0x10]; 1155 1156 u8 reserved_at_40[0x20]; 1157 1158 u8 reserved_at_60[0x10]; 1159 u8 crypto_type[0x10]; 1160 1161 u8 reserved_at_80[0x80]; 1162 }; 1163 1164 struct mlx5_ifc_sync_crypto_out_bits { 1165 u8 status[0x8]; 1166 u8 reserved_at_8[0x18]; 1167 1168 u8 syndrome[0x20]; 1169 1170 u8 reserved_at_40[0x40]; 1171 }; 1172 1173 struct mlx5_ifc_device_mem_cap_bits { 1174 u8 memic[0x1]; 1175 u8 reserved_at_1[0x1f]; 1176 1177 u8 reserved_at_20[0xb]; 1178 u8 log_min_memic_alloc_size[0x5]; 1179 u8 reserved_at_30[0x8]; 1180 u8 log_max_memic_addr_alignment[0x8]; 1181 1182 u8 memic_bar_start_addr[0x40]; 1183 1184 u8 memic_bar_size[0x20]; 1185 1186 u8 max_memic_size[0x20]; 1187 1188 u8 steering_sw_icm_start_address[0x40]; 1189 1190 u8 reserved_at_100[0x8]; 1191 u8 log_header_modify_sw_icm_size[0x8]; 1192 u8 reserved_at_110[0x2]; 1193 u8 log_sw_icm_alloc_granularity[0x6]; 1194 u8 log_steering_sw_icm_size[0x8]; 1195 1196 u8 reserved_at_120[0x18]; 1197 u8 log_header_modify_pattern_sw_icm_size[0x8]; 1198 1199 u8 header_modify_sw_icm_start_address[0x40]; 1200 1201 u8 reserved_at_180[0x40]; 1202 1203 u8 header_modify_pattern_sw_icm_start_address[0x40]; 1204 1205 u8 memic_operations[0x20]; 1206 1207 u8 reserved_at_220[0x5e0]; 1208 }; 1209 1210 struct mlx5_ifc_device_event_cap_bits { 1211 u8 user_affiliated_events[4][0x40]; 1212 1213 u8 user_unaffiliated_events[4][0x40]; 1214 }; 1215 1216 struct mlx5_ifc_virtio_emulation_cap_bits { 1217 u8 desc_tunnel_offload_type[0x1]; 1218 u8 eth_frame_offload_type[0x1]; 1219 u8 virtio_version_1_0[0x1]; 1220 u8 device_features_bits_mask[0xd]; 1221 u8 event_mode[0x8]; 1222 u8 virtio_queue_type[0x8]; 1223 1224 u8 max_tunnel_desc[0x10]; 1225 u8 reserved_at_30[0x3]; 1226 u8 log_doorbell_stride[0x5]; 1227 u8 reserved_at_38[0x3]; 1228 u8 log_doorbell_bar_size[0x5]; 1229 1230 u8 doorbell_bar_offset[0x40]; 1231 1232 u8 max_emulated_devices[0x8]; 1233 u8 max_num_virtio_queues[0x18]; 1234 1235 u8 reserved_at_a0[0x60]; 1236 1237 u8 umem_1_buffer_param_a[0x20]; 1238 1239 u8 umem_1_buffer_param_b[0x20]; 1240 1241 u8 umem_2_buffer_param_a[0x20]; 1242 1243 u8 umem_2_buffer_param_b[0x20]; 1244 1245 u8 umem_3_buffer_param_a[0x20]; 1246 1247 u8 umem_3_buffer_param_b[0x20]; 1248 1249 u8 reserved_at_1c0[0x640]; 1250 }; 1251 1252 enum { 1253 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0, 1254 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2, 1255 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4, 1256 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8, 1257 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10, 1258 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20, 1259 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40, 1260 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80, 1261 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100, 1262 }; 1263 1264 enum { 1265 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1, 1266 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2, 1267 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4, 1268 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8, 1269 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10, 1270 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20, 1271 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40, 1272 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80, 1273 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100, 1274 }; 1275 1276 struct mlx5_ifc_atomic_caps_bits { 1277 u8 reserved_at_0[0x40]; 1278 1279 u8 atomic_req_8B_endianness_mode[0x2]; 1280 u8 reserved_at_42[0x4]; 1281 u8 supported_atomic_req_8B_endianness_mode_1[0x1]; 1282 1283 u8 reserved_at_47[0x19]; 1284 1285 u8 reserved_at_60[0x20]; 1286 1287 u8 reserved_at_80[0x10]; 1288 u8 atomic_operations[0x10]; 1289 1290 u8 reserved_at_a0[0x10]; 1291 u8 atomic_size_qp[0x10]; 1292 1293 u8 reserved_at_c0[0x10]; 1294 u8 atomic_size_dc[0x10]; 1295 1296 u8 reserved_at_e0[0x720]; 1297 }; 1298 1299 struct mlx5_ifc_odp_cap_bits { 1300 u8 reserved_at_0[0x40]; 1301 1302 u8 sig[0x1]; 1303 u8 reserved_at_41[0x1f]; 1304 1305 u8 reserved_at_60[0x20]; 1306 1307 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps; 1308 1309 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps; 1310 1311 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps; 1312 1313 struct mlx5_ifc_odp_per_transport_service_cap_bits xrc_odp_caps; 1314 1315 struct mlx5_ifc_odp_per_transport_service_cap_bits dc_odp_caps; 1316 1317 u8 reserved_at_120[0x6E0]; 1318 }; 1319 1320 struct mlx5_ifc_tls_cap_bits { 1321 u8 tls_1_2_aes_gcm_128[0x1]; 1322 u8 tls_1_3_aes_gcm_128[0x1]; 1323 u8 tls_1_2_aes_gcm_256[0x1]; 1324 u8 tls_1_3_aes_gcm_256[0x1]; 1325 u8 reserved_at_4[0x1c]; 1326 1327 u8 reserved_at_20[0x7e0]; 1328 }; 1329 1330 struct mlx5_ifc_ipsec_cap_bits { 1331 u8 ipsec_full_offload[0x1]; 1332 u8 ipsec_crypto_offload[0x1]; 1333 u8 ipsec_esn[0x1]; 1334 u8 ipsec_crypto_esp_aes_gcm_256_encrypt[0x1]; 1335 u8 ipsec_crypto_esp_aes_gcm_128_encrypt[0x1]; 1336 u8 ipsec_crypto_esp_aes_gcm_256_decrypt[0x1]; 1337 u8 ipsec_crypto_esp_aes_gcm_128_decrypt[0x1]; 1338 u8 reserved_at_7[0x4]; 1339 u8 log_max_ipsec_offload[0x5]; 1340 u8 reserved_at_10[0x10]; 1341 1342 u8 min_log_ipsec_full_replay_window[0x8]; 1343 u8 max_log_ipsec_full_replay_window[0x8]; 1344 u8 reserved_at_30[0x7d0]; 1345 }; 1346 1347 struct mlx5_ifc_macsec_cap_bits { 1348 u8 macsec_epn[0x1]; 1349 u8 reserved_at_1[0x2]; 1350 u8 macsec_crypto_esp_aes_gcm_256_encrypt[0x1]; 1351 u8 macsec_crypto_esp_aes_gcm_128_encrypt[0x1]; 1352 u8 macsec_crypto_esp_aes_gcm_256_decrypt[0x1]; 1353 u8 macsec_crypto_esp_aes_gcm_128_decrypt[0x1]; 1354 u8 reserved_at_7[0x4]; 1355 u8 log_max_macsec_offload[0x5]; 1356 u8 reserved_at_10[0x10]; 1357 1358 u8 min_log_macsec_full_replay_window[0x8]; 1359 u8 max_log_macsec_full_replay_window[0x8]; 1360 u8 reserved_at_30[0x10]; 1361 1362 u8 reserved_at_40[0x7c0]; 1363 }; 1364 1365 enum { 1366 MLX5_WQ_TYPE_LINKED_LIST = 0x0, 1367 MLX5_WQ_TYPE_CYCLIC = 0x1, 1368 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2, 1369 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3, 1370 }; 1371 1372 enum { 1373 MLX5_WQ_END_PAD_MODE_NONE = 0x0, 1374 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1, 1375 }; 1376 1377 enum { 1378 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0, 1379 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1, 1380 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2, 1381 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3, 1382 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4, 1383 }; 1384 1385 enum { 1386 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0, 1387 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1, 1388 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2, 1389 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3, 1390 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4, 1391 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5, 1392 }; 1393 1394 enum { 1395 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0, 1396 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1, 1397 }; 1398 1399 enum { 1400 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0, 1401 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1, 1402 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3, 1403 }; 1404 1405 enum { 1406 MLX5_CAP_PORT_TYPE_IB = 0x0, 1407 MLX5_CAP_PORT_TYPE_ETH = 0x1, 1408 }; 1409 1410 enum { 1411 MLX5_CAP_UMR_FENCE_STRONG = 0x0, 1412 MLX5_CAP_UMR_FENCE_SMALL = 0x1, 1413 MLX5_CAP_UMR_FENCE_NONE = 0x2, 1414 }; 1415 1416 enum { 1417 MLX5_FLEX_PARSER_GENEVE_ENABLED = 1 << 3, 1418 MLX5_FLEX_PARSER_MPLS_OVER_GRE_ENABLED = 1 << 4, 1419 MLX5_FLEX_PARSER_MPLS_OVER_UDP_ENABLED = 1 << 5, 1420 MLX5_FLEX_PARSER_VXLAN_GPE_ENABLED = 1 << 7, 1421 MLX5_FLEX_PARSER_ICMP_V4_ENABLED = 1 << 8, 1422 MLX5_FLEX_PARSER_ICMP_V6_ENABLED = 1 << 9, 1423 MLX5_FLEX_PARSER_GENEVE_TLV_OPTION_0_ENABLED = 1 << 10, 1424 MLX5_FLEX_PARSER_GTPU_ENABLED = 1 << 11, 1425 MLX5_FLEX_PARSER_GTPU_DW_2_ENABLED = 1 << 16, 1426 MLX5_FLEX_PARSER_GTPU_FIRST_EXT_DW_0_ENABLED = 1 << 17, 1427 MLX5_FLEX_PARSER_GTPU_DW_0_ENABLED = 1 << 18, 1428 MLX5_FLEX_PARSER_GTPU_TEID_ENABLED = 1 << 19, 1429 }; 1430 1431 enum { 1432 MLX5_UCTX_CAP_RAW_TX = 1UL << 0, 1433 MLX5_UCTX_CAP_INTERNAL_DEV_RES = 1UL << 1, 1434 }; 1435 1436 #define MLX5_FC_BULK_SIZE_FACTOR 128 1437 1438 enum mlx5_fc_bulk_alloc_bitmask { 1439 MLX5_FC_BULK_128 = (1 << 0), 1440 MLX5_FC_BULK_256 = (1 << 1), 1441 MLX5_FC_BULK_512 = (1 << 2), 1442 MLX5_FC_BULK_1024 = (1 << 3), 1443 MLX5_FC_BULK_2048 = (1 << 4), 1444 MLX5_FC_BULK_4096 = (1 << 5), 1445 MLX5_FC_BULK_8192 = (1 << 6), 1446 MLX5_FC_BULK_16384 = (1 << 7), 1447 }; 1448 1449 #define MLX5_FC_BULK_NUM_FCS(fc_enum) (MLX5_FC_BULK_SIZE_FACTOR * (fc_enum)) 1450 1451 #define MLX5_FT_MAX_MULTIPATH_LEVEL 63 1452 1453 enum { 1454 MLX5_STEERING_FORMAT_CONNECTX_5 = 0, 1455 MLX5_STEERING_FORMAT_CONNECTX_6DX = 1, 1456 MLX5_STEERING_FORMAT_CONNECTX_7 = 2, 1457 }; 1458 1459 struct mlx5_ifc_cmd_hca_cap_bits { 1460 u8 reserved_at_0[0x10]; 1461 u8 shared_object_to_user_object_allowed[0x1]; 1462 u8 reserved_at_13[0xe]; 1463 u8 vhca_resource_manager[0x1]; 1464 1465 u8 hca_cap_2[0x1]; 1466 u8 create_lag_when_not_master_up[0x1]; 1467 u8 dtor[0x1]; 1468 u8 event_on_vhca_state_teardown_request[0x1]; 1469 u8 event_on_vhca_state_in_use[0x1]; 1470 u8 event_on_vhca_state_active[0x1]; 1471 u8 event_on_vhca_state_allocated[0x1]; 1472 u8 event_on_vhca_state_invalid[0x1]; 1473 u8 reserved_at_28[0x8]; 1474 u8 vhca_id[0x10]; 1475 1476 u8 reserved_at_40[0x40]; 1477 1478 u8 log_max_srq_sz[0x8]; 1479 u8 log_max_qp_sz[0x8]; 1480 u8 event_cap[0x1]; 1481 u8 reserved_at_91[0x2]; 1482 u8 isolate_vl_tc_new[0x1]; 1483 u8 reserved_at_94[0x4]; 1484 u8 prio_tag_required[0x1]; 1485 u8 reserved_at_99[0x2]; 1486 u8 log_max_qp[0x5]; 1487 1488 u8 reserved_at_a0[0x3]; 1489 u8 ece_support[0x1]; 1490 u8 reserved_at_a4[0x5]; 1491 u8 reg_c_preserve[0x1]; 1492 u8 reserved_at_aa[0x1]; 1493 u8 log_max_srq[0x5]; 1494 u8 reserved_at_b0[0x1]; 1495 u8 uplink_follow[0x1]; 1496 u8 ts_cqe_to_dest_cqn[0x1]; 1497 u8 reserved_at_b3[0x6]; 1498 u8 go_back_n[0x1]; 1499 u8 shampo[0x1]; 1500 u8 reserved_at_bb[0x5]; 1501 1502 u8 max_sgl_for_optimized_performance[0x8]; 1503 u8 log_max_cq_sz[0x8]; 1504 u8 relaxed_ordering_write_umr[0x1]; 1505 u8 relaxed_ordering_read_umr[0x1]; 1506 u8 reserved_at_d2[0x7]; 1507 u8 virtio_net_device_emualtion_manager[0x1]; 1508 u8 virtio_blk_device_emualtion_manager[0x1]; 1509 u8 log_max_cq[0x5]; 1510 1511 u8 log_max_eq_sz[0x8]; 1512 u8 relaxed_ordering_write[0x1]; 1513 u8 relaxed_ordering_read_pci_enabled[0x1]; 1514 u8 log_max_mkey[0x6]; 1515 u8 reserved_at_f0[0x6]; 1516 u8 terminate_scatter_list_mkey[0x1]; 1517 u8 repeated_mkey[0x1]; 1518 u8 dump_fill_mkey[0x1]; 1519 u8 reserved_at_f9[0x2]; 1520 u8 fast_teardown[0x1]; 1521 u8 log_max_eq[0x4]; 1522 1523 u8 max_indirection[0x8]; 1524 u8 fixed_buffer_size[0x1]; 1525 u8 log_max_mrw_sz[0x7]; 1526 u8 force_teardown[0x1]; 1527 u8 reserved_at_111[0x1]; 1528 u8 log_max_bsf_list_size[0x6]; 1529 u8 umr_extended_translation_offset[0x1]; 1530 u8 null_mkey[0x1]; 1531 u8 log_max_klm_list_size[0x6]; 1532 1533 u8 reserved_at_120[0x2]; 1534 u8 qpc_extension[0x1]; 1535 u8 reserved_at_123[0x7]; 1536 u8 log_max_ra_req_dc[0x6]; 1537 u8 reserved_at_130[0x2]; 1538 u8 eth_wqe_too_small[0x1]; 1539 u8 reserved_at_133[0x6]; 1540 u8 vnic_env_cq_overrun[0x1]; 1541 u8 log_max_ra_res_dc[0x6]; 1542 1543 u8 reserved_at_140[0x5]; 1544 u8 release_all_pages[0x1]; 1545 u8 must_not_use[0x1]; 1546 u8 reserved_at_147[0x2]; 1547 u8 roce_accl[0x1]; 1548 u8 log_max_ra_req_qp[0x6]; 1549 u8 reserved_at_150[0xa]; 1550 u8 log_max_ra_res_qp[0x6]; 1551 1552 u8 end_pad[0x1]; 1553 u8 cc_query_allowed[0x1]; 1554 u8 cc_modify_allowed[0x1]; 1555 u8 start_pad[0x1]; 1556 u8 cache_line_128byte[0x1]; 1557 u8 reserved_at_165[0x4]; 1558 u8 rts2rts_qp_counters_set_id[0x1]; 1559 u8 reserved_at_16a[0x2]; 1560 u8 vnic_env_int_rq_oob[0x1]; 1561 u8 sbcam_reg[0x1]; 1562 u8 reserved_at_16e[0x1]; 1563 u8 qcam_reg[0x1]; 1564 u8 gid_table_size[0x10]; 1565 1566 u8 out_of_seq_cnt[0x1]; 1567 u8 vport_counters[0x1]; 1568 u8 retransmission_q_counters[0x1]; 1569 u8 debug[0x1]; 1570 u8 modify_rq_counter_set_id[0x1]; 1571 u8 rq_delay_drop[0x1]; 1572 u8 max_qp_cnt[0xa]; 1573 u8 pkey_table_size[0x10]; 1574 1575 u8 vport_group_manager[0x1]; 1576 u8 vhca_group_manager[0x1]; 1577 u8 ib_virt[0x1]; 1578 u8 eth_virt[0x1]; 1579 u8 vnic_env_queue_counters[0x1]; 1580 u8 ets[0x1]; 1581 u8 nic_flow_table[0x1]; 1582 u8 eswitch_manager[0x1]; 1583 u8 device_memory[0x1]; 1584 u8 mcam_reg[0x1]; 1585 u8 pcam_reg[0x1]; 1586 u8 local_ca_ack_delay[0x5]; 1587 u8 port_module_event[0x1]; 1588 u8 enhanced_error_q_counters[0x1]; 1589 u8 ports_check[0x1]; 1590 u8 reserved_at_1b3[0x1]; 1591 u8 disable_link_up[0x1]; 1592 u8 beacon_led[0x1]; 1593 u8 port_type[0x2]; 1594 u8 num_ports[0x8]; 1595 1596 u8 reserved_at_1c0[0x1]; 1597 u8 pps[0x1]; 1598 u8 pps_modify[0x1]; 1599 u8 log_max_msg[0x5]; 1600 u8 reserved_at_1c8[0x4]; 1601 u8 max_tc[0x4]; 1602 u8 temp_warn_event[0x1]; 1603 u8 dcbx[0x1]; 1604 u8 general_notification_event[0x1]; 1605 u8 reserved_at_1d3[0x2]; 1606 u8 fpga[0x1]; 1607 u8 rol_s[0x1]; 1608 u8 rol_g[0x1]; 1609 u8 reserved_at_1d8[0x1]; 1610 u8 wol_s[0x1]; 1611 u8 wol_g[0x1]; 1612 u8 wol_a[0x1]; 1613 u8 wol_b[0x1]; 1614 u8 wol_m[0x1]; 1615 u8 wol_u[0x1]; 1616 u8 wol_p[0x1]; 1617 1618 u8 stat_rate_support[0x10]; 1619 u8 reserved_at_1f0[0x1]; 1620 u8 pci_sync_for_fw_update_event[0x1]; 1621 u8 reserved_at_1f2[0x6]; 1622 u8 init2_lag_tx_port_affinity[0x1]; 1623 u8 reserved_at_1fa[0x3]; 1624 u8 cqe_version[0x4]; 1625 1626 u8 compact_address_vector[0x1]; 1627 u8 striding_rq[0x1]; 1628 u8 reserved_at_202[0x1]; 1629 u8 ipoib_enhanced_offloads[0x1]; 1630 u8 ipoib_basic_offloads[0x1]; 1631 u8 reserved_at_205[0x1]; 1632 u8 repeated_block_disabled[0x1]; 1633 u8 umr_modify_entity_size_disabled[0x1]; 1634 u8 umr_modify_atomic_disabled[0x1]; 1635 u8 umr_indirect_mkey_disabled[0x1]; 1636 u8 umr_fence[0x2]; 1637 u8 dc_req_scat_data_cqe[0x1]; 1638 u8 reserved_at_20d[0x2]; 1639 u8 drain_sigerr[0x1]; 1640 u8 cmdif_checksum[0x2]; 1641 u8 sigerr_cqe[0x1]; 1642 u8 reserved_at_213[0x1]; 1643 u8 wq_signature[0x1]; 1644 u8 sctr_data_cqe[0x1]; 1645 u8 reserved_at_216[0x1]; 1646 u8 sho[0x1]; 1647 u8 tph[0x1]; 1648 u8 rf[0x1]; 1649 u8 dct[0x1]; 1650 u8 qos[0x1]; 1651 u8 eth_net_offloads[0x1]; 1652 u8 roce[0x1]; 1653 u8 atomic[0x1]; 1654 u8 reserved_at_21f[0x1]; 1655 1656 u8 cq_oi[0x1]; 1657 u8 cq_resize[0x1]; 1658 u8 cq_moderation[0x1]; 1659 u8 reserved_at_223[0x3]; 1660 u8 cq_eq_remap[0x1]; 1661 u8 pg[0x1]; 1662 u8 block_lb_mc[0x1]; 1663 u8 reserved_at_229[0x1]; 1664 u8 scqe_break_moderation[0x1]; 1665 u8 cq_period_start_from_cqe[0x1]; 1666 u8 cd[0x1]; 1667 u8 reserved_at_22d[0x1]; 1668 u8 apm[0x1]; 1669 u8 vector_calc[0x1]; 1670 u8 umr_ptr_rlky[0x1]; 1671 u8 imaicl[0x1]; 1672 u8 qp_packet_based[0x1]; 1673 u8 reserved_at_233[0x3]; 1674 u8 qkv[0x1]; 1675 u8 pkv[0x1]; 1676 u8 set_deth_sqpn[0x1]; 1677 u8 reserved_at_239[0x3]; 1678 u8 xrc[0x1]; 1679 u8 ud[0x1]; 1680 u8 uc[0x1]; 1681 u8 rc[0x1]; 1682 1683 u8 uar_4k[0x1]; 1684 u8 reserved_at_241[0x7]; 1685 u8 fl_rc_qp_when_roce_disabled[0x1]; 1686 u8 regexp_params[0x1]; 1687 u8 uar_sz[0x6]; 1688 u8 port_selection_cap[0x1]; 1689 u8 reserved_at_251[0x1]; 1690 u8 umem_uid_0[0x1]; 1691 u8 reserved_at_253[0x5]; 1692 u8 log_pg_sz[0x8]; 1693 1694 u8 bf[0x1]; 1695 u8 driver_version[0x1]; 1696 u8 pad_tx_eth_packet[0x1]; 1697 u8 reserved_at_263[0x3]; 1698 u8 mkey_by_name[0x1]; 1699 u8 reserved_at_267[0x4]; 1700 1701 u8 log_bf_reg_size[0x5]; 1702 1703 u8 reserved_at_270[0x3]; 1704 u8 qp_error_syndrome[0x1]; 1705 u8 reserved_at_274[0x2]; 1706 u8 lag_dct[0x2]; 1707 u8 lag_tx_port_affinity[0x1]; 1708 u8 lag_native_fdb_selection[0x1]; 1709 u8 reserved_at_27a[0x1]; 1710 u8 lag_master[0x1]; 1711 u8 num_lag_ports[0x4]; 1712 1713 u8 reserved_at_280[0x10]; 1714 u8 max_wqe_sz_sq[0x10]; 1715 1716 u8 reserved_at_2a0[0x10]; 1717 u8 max_wqe_sz_rq[0x10]; 1718 1719 u8 max_flow_counter_31_16[0x10]; 1720 u8 max_wqe_sz_sq_dc[0x10]; 1721 1722 u8 reserved_at_2e0[0x7]; 1723 u8 max_qp_mcg[0x19]; 1724 1725 u8 reserved_at_300[0x10]; 1726 u8 flow_counter_bulk_alloc[0x8]; 1727 u8 log_max_mcg[0x8]; 1728 1729 u8 reserved_at_320[0x3]; 1730 u8 log_max_transport_domain[0x5]; 1731 u8 reserved_at_328[0x2]; 1732 u8 relaxed_ordering_read[0x1]; 1733 u8 log_max_pd[0x5]; 1734 u8 reserved_at_330[0x6]; 1735 u8 pci_sync_for_fw_update_with_driver_unload[0x1]; 1736 u8 vnic_env_cnt_steering_fail[0x1]; 1737 u8 vport_counter_local_loopback[0x1]; 1738 u8 q_counter_aggregation[0x1]; 1739 u8 q_counter_other_vport[0x1]; 1740 u8 log_max_xrcd[0x5]; 1741 1742 u8 nic_receive_steering_discard[0x1]; 1743 u8 receive_discard_vport_down[0x1]; 1744 u8 transmit_discard_vport_down[0x1]; 1745 u8 eq_overrun_count[0x1]; 1746 u8 reserved_at_344[0x1]; 1747 u8 invalid_command_count[0x1]; 1748 u8 quota_exceeded_count[0x1]; 1749 u8 reserved_at_347[0x1]; 1750 u8 log_max_flow_counter_bulk[0x8]; 1751 u8 max_flow_counter_15_0[0x10]; 1752 1753 1754 u8 reserved_at_360[0x3]; 1755 u8 log_max_rq[0x5]; 1756 u8 reserved_at_368[0x3]; 1757 u8 log_max_sq[0x5]; 1758 u8 reserved_at_370[0x3]; 1759 u8 log_max_tir[0x5]; 1760 u8 reserved_at_378[0x3]; 1761 u8 log_max_tis[0x5]; 1762 1763 u8 basic_cyclic_rcv_wqe[0x1]; 1764 u8 reserved_at_381[0x2]; 1765 u8 log_max_rmp[0x5]; 1766 u8 reserved_at_388[0x3]; 1767 u8 log_max_rqt[0x5]; 1768 u8 reserved_at_390[0x3]; 1769 u8 log_max_rqt_size[0x5]; 1770 u8 reserved_at_398[0x3]; 1771 u8 log_max_tis_per_sq[0x5]; 1772 1773 u8 ext_stride_num_range[0x1]; 1774 u8 roce_rw_supported[0x1]; 1775 u8 log_max_current_uc_list_wr_supported[0x1]; 1776 u8 log_max_stride_sz_rq[0x5]; 1777 u8 reserved_at_3a8[0x3]; 1778 u8 log_min_stride_sz_rq[0x5]; 1779 u8 reserved_at_3b0[0x3]; 1780 u8 log_max_stride_sz_sq[0x5]; 1781 u8 reserved_at_3b8[0x3]; 1782 u8 log_min_stride_sz_sq[0x5]; 1783 1784 u8 hairpin[0x1]; 1785 u8 reserved_at_3c1[0x2]; 1786 u8 log_max_hairpin_queues[0x5]; 1787 u8 reserved_at_3c8[0x3]; 1788 u8 log_max_hairpin_wq_data_sz[0x5]; 1789 u8 reserved_at_3d0[0x3]; 1790 u8 log_max_hairpin_num_packets[0x5]; 1791 u8 reserved_at_3d8[0x3]; 1792 u8 log_max_wq_sz[0x5]; 1793 1794 u8 nic_vport_change_event[0x1]; 1795 u8 disable_local_lb_uc[0x1]; 1796 u8 disable_local_lb_mc[0x1]; 1797 u8 log_min_hairpin_wq_data_sz[0x5]; 1798 u8 reserved_at_3e8[0x2]; 1799 u8 vhca_state[0x1]; 1800 u8 log_max_vlan_list[0x5]; 1801 u8 reserved_at_3f0[0x3]; 1802 u8 log_max_current_mc_list[0x5]; 1803 u8 reserved_at_3f8[0x3]; 1804 u8 log_max_current_uc_list[0x5]; 1805 1806 u8 general_obj_types[0x40]; 1807 1808 u8 sq_ts_format[0x2]; 1809 u8 rq_ts_format[0x2]; 1810 u8 steering_format_version[0x4]; 1811 u8 create_qp_start_hint[0x18]; 1812 1813 u8 reserved_at_460[0x1]; 1814 u8 ats[0x1]; 1815 u8 reserved_at_462[0x1]; 1816 u8 log_max_uctx[0x5]; 1817 u8 reserved_at_468[0x1]; 1818 u8 crypto[0x1]; 1819 u8 ipsec_offload[0x1]; 1820 u8 log_max_umem[0x5]; 1821 u8 max_num_eqs[0x10]; 1822 1823 u8 reserved_at_480[0x1]; 1824 u8 tls_tx[0x1]; 1825 u8 tls_rx[0x1]; 1826 u8 log_max_l2_table[0x5]; 1827 u8 reserved_at_488[0x8]; 1828 u8 log_uar_page_sz[0x10]; 1829 1830 u8 reserved_at_4a0[0x20]; 1831 u8 device_frequency_mhz[0x20]; 1832 u8 device_frequency_khz[0x20]; 1833 1834 u8 reserved_at_500[0x20]; 1835 u8 num_of_uars_per_page[0x20]; 1836 1837 u8 flex_parser_protocols[0x20]; 1838 1839 u8 max_geneve_tlv_options[0x8]; 1840 u8 reserved_at_568[0x3]; 1841 u8 max_geneve_tlv_option_data_len[0x5]; 1842 u8 reserved_at_570[0x9]; 1843 u8 adv_virtualization[0x1]; 1844 u8 reserved_at_57a[0x6]; 1845 1846 u8 reserved_at_580[0xb]; 1847 u8 log_max_dci_stream_channels[0x5]; 1848 u8 reserved_at_590[0x3]; 1849 u8 log_max_dci_errored_streams[0x5]; 1850 u8 reserved_at_598[0x8]; 1851 1852 u8 reserved_at_5a0[0x10]; 1853 u8 enhanced_cqe_compression[0x1]; 1854 u8 reserved_at_5b1[0x2]; 1855 u8 log_max_dek[0x5]; 1856 u8 reserved_at_5b8[0x4]; 1857 u8 mini_cqe_resp_stride_index[0x1]; 1858 u8 cqe_128_always[0x1]; 1859 u8 cqe_compression_128[0x1]; 1860 u8 cqe_compression[0x1]; 1861 1862 u8 cqe_compression_timeout[0x10]; 1863 u8 cqe_compression_max_num[0x10]; 1864 1865 u8 reserved_at_5e0[0x8]; 1866 u8 flex_parser_id_gtpu_dw_0[0x4]; 1867 u8 reserved_at_5ec[0x4]; 1868 u8 tag_matching[0x1]; 1869 u8 rndv_offload_rc[0x1]; 1870 u8 rndv_offload_dc[0x1]; 1871 u8 log_tag_matching_list_sz[0x5]; 1872 u8 reserved_at_5f8[0x3]; 1873 u8 log_max_xrq[0x5]; 1874 1875 u8 affiliate_nic_vport_criteria[0x8]; 1876 u8 native_port_num[0x8]; 1877 u8 num_vhca_ports[0x8]; 1878 u8 flex_parser_id_gtpu_teid[0x4]; 1879 u8 reserved_at_61c[0x2]; 1880 u8 sw_owner_id[0x1]; 1881 u8 reserved_at_61f[0x1]; 1882 1883 u8 max_num_of_monitor_counters[0x10]; 1884 u8 num_ppcnt_monitor_counters[0x10]; 1885 1886 u8 max_num_sf[0x10]; 1887 u8 num_q_monitor_counters[0x10]; 1888 1889 u8 reserved_at_660[0x20]; 1890 1891 u8 sf[0x1]; 1892 u8 sf_set_partition[0x1]; 1893 u8 reserved_at_682[0x1]; 1894 u8 log_max_sf[0x5]; 1895 u8 apu[0x1]; 1896 u8 reserved_at_689[0x4]; 1897 u8 migration[0x1]; 1898 u8 reserved_at_68e[0x2]; 1899 u8 log_min_sf_size[0x8]; 1900 u8 max_num_sf_partitions[0x8]; 1901 1902 u8 uctx_cap[0x20]; 1903 1904 u8 reserved_at_6c0[0x4]; 1905 u8 flex_parser_id_geneve_tlv_option_0[0x4]; 1906 u8 flex_parser_id_icmp_dw1[0x4]; 1907 u8 flex_parser_id_icmp_dw0[0x4]; 1908 u8 flex_parser_id_icmpv6_dw1[0x4]; 1909 u8 flex_parser_id_icmpv6_dw0[0x4]; 1910 u8 flex_parser_id_outer_first_mpls_over_gre[0x4]; 1911 u8 flex_parser_id_outer_first_mpls_over_udp_label[0x4]; 1912 1913 u8 max_num_match_definer[0x10]; 1914 u8 sf_base_id[0x10]; 1915 1916 u8 flex_parser_id_gtpu_dw_2[0x4]; 1917 u8 flex_parser_id_gtpu_first_ext_dw_0[0x4]; 1918 u8 num_total_dynamic_vf_msix[0x18]; 1919 u8 reserved_at_720[0x14]; 1920 u8 dynamic_msix_table_size[0xc]; 1921 u8 reserved_at_740[0xc]; 1922 u8 min_dynamic_vf_msix_table_size[0x4]; 1923 u8 reserved_at_750[0x4]; 1924 u8 max_dynamic_vf_msix_table_size[0xc]; 1925 1926 u8 reserved_at_760[0x3]; 1927 u8 log_max_num_header_modify_argument[0x5]; 1928 u8 reserved_at_768[0x4]; 1929 u8 log_header_modify_argument_granularity[0x4]; 1930 u8 reserved_at_770[0x3]; 1931 u8 log_header_modify_argument_max_alloc[0x5]; 1932 u8 reserved_at_778[0x8]; 1933 1934 u8 vhca_tunnel_commands[0x40]; 1935 u8 match_definer_format_supported[0x40]; 1936 }; 1937 1938 enum { 1939 MLX5_CROSS_VHCA_OBJ_TO_OBJ_SUPPORTED_LOCAL_FLOW_TABLE_TO_REMOTE_FLOW_TABLE_MISS = 0x80000, 1940 }; 1941 1942 enum { 1943 MLX5_ALLOWED_OBJ_FOR_OTHER_VHCA_ACCESS_FLOW_TABLE = 0x200, 1944 }; 1945 1946 struct mlx5_ifc_cmd_hca_cap_2_bits { 1947 u8 reserved_at_0[0x80]; 1948 1949 u8 migratable[0x1]; 1950 u8 reserved_at_81[0x1f]; 1951 1952 u8 max_reformat_insert_size[0x8]; 1953 u8 max_reformat_insert_offset[0x8]; 1954 u8 max_reformat_remove_size[0x8]; 1955 u8 max_reformat_remove_offset[0x8]; 1956 1957 u8 reserved_at_c0[0x8]; 1958 u8 migration_multi_load[0x1]; 1959 u8 migration_tracking_state[0x1]; 1960 u8 reserved_at_ca[0x6]; 1961 u8 migration_in_chunks[0x1]; 1962 u8 reserved_at_d1[0xf]; 1963 1964 u8 cross_vhca_object_to_object_supported[0x20]; 1965 1966 u8 allowed_object_for_other_vhca_access[0x40]; 1967 1968 u8 reserved_at_140[0x60]; 1969 1970 u8 flow_table_type_2_type[0x8]; 1971 u8 reserved_at_1a8[0x3]; 1972 u8 log_min_mkey_entity_size[0x5]; 1973 u8 reserved_at_1b0[0x10]; 1974 1975 u8 reserved_at_1c0[0x60]; 1976 1977 u8 reserved_at_220[0x1]; 1978 u8 sw_vhca_id_valid[0x1]; 1979 u8 sw_vhca_id[0xe]; 1980 u8 reserved_at_230[0x10]; 1981 1982 u8 reserved_at_240[0xb]; 1983 u8 ts_cqe_metadata_size2wqe_counter[0x5]; 1984 u8 reserved_at_250[0x10]; 1985 1986 u8 reserved_at_260[0x120]; 1987 u8 reserved_at_380[0x10]; 1988 u8 ec_vf_vport_base[0x10]; 1989 u8 reserved_at_3a0[0x460]; 1990 }; 1991 1992 enum mlx5_ifc_flow_destination_type { 1993 MLX5_IFC_FLOW_DESTINATION_TYPE_VPORT = 0x0, 1994 MLX5_IFC_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1, 1995 MLX5_IFC_FLOW_DESTINATION_TYPE_TIR = 0x2, 1996 MLX5_IFC_FLOW_DESTINATION_TYPE_FLOW_SAMPLER = 0x6, 1997 MLX5_IFC_FLOW_DESTINATION_TYPE_UPLINK = 0x8, 1998 MLX5_IFC_FLOW_DESTINATION_TYPE_TABLE_TYPE = 0xA, 1999 }; 2000 2001 enum mlx5_flow_table_miss_action { 2002 MLX5_FLOW_TABLE_MISS_ACTION_DEF, 2003 MLX5_FLOW_TABLE_MISS_ACTION_FWD, 2004 MLX5_FLOW_TABLE_MISS_ACTION_SWITCH_DOMAIN, 2005 }; 2006 2007 struct mlx5_ifc_dest_format_struct_bits { 2008 u8 destination_type[0x8]; 2009 u8 destination_id[0x18]; 2010 2011 u8 destination_eswitch_owner_vhca_id_valid[0x1]; 2012 u8 packet_reformat[0x1]; 2013 u8 reserved_at_22[0x6]; 2014 u8 destination_table_type[0x8]; 2015 u8 destination_eswitch_owner_vhca_id[0x10]; 2016 }; 2017 2018 struct mlx5_ifc_flow_counter_list_bits { 2019 u8 flow_counter_id[0x20]; 2020 2021 u8 reserved_at_20[0x20]; 2022 }; 2023 2024 struct mlx5_ifc_extended_dest_format_bits { 2025 struct mlx5_ifc_dest_format_struct_bits destination_entry; 2026 2027 u8 packet_reformat_id[0x20]; 2028 2029 u8 reserved_at_60[0x20]; 2030 }; 2031 2032 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits { 2033 struct mlx5_ifc_extended_dest_format_bits extended_dest_format; 2034 struct mlx5_ifc_flow_counter_list_bits flow_counter_list; 2035 }; 2036 2037 struct mlx5_ifc_fte_match_param_bits { 2038 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers; 2039 2040 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters; 2041 2042 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers; 2043 2044 struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2; 2045 2046 struct mlx5_ifc_fte_match_set_misc3_bits misc_parameters_3; 2047 2048 struct mlx5_ifc_fte_match_set_misc4_bits misc_parameters_4; 2049 2050 struct mlx5_ifc_fte_match_set_misc5_bits misc_parameters_5; 2051 2052 u8 reserved_at_e00[0x200]; 2053 }; 2054 2055 enum { 2056 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0, 2057 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1, 2058 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2, 2059 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3, 2060 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4, 2061 }; 2062 2063 struct mlx5_ifc_rx_hash_field_select_bits { 2064 u8 l3_prot_type[0x1]; 2065 u8 l4_prot_type[0x1]; 2066 u8 selected_fields[0x1e]; 2067 }; 2068 2069 enum { 2070 MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0, 2071 MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1, 2072 }; 2073 2074 enum { 2075 MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0, 2076 MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1, 2077 }; 2078 2079 struct mlx5_ifc_wq_bits { 2080 u8 wq_type[0x4]; 2081 u8 wq_signature[0x1]; 2082 u8 end_padding_mode[0x2]; 2083 u8 cd_slave[0x1]; 2084 u8 reserved_at_8[0x18]; 2085 2086 u8 hds_skip_first_sge[0x1]; 2087 u8 log2_hds_buf_size[0x3]; 2088 u8 reserved_at_24[0x7]; 2089 u8 page_offset[0x5]; 2090 u8 lwm[0x10]; 2091 2092 u8 reserved_at_40[0x8]; 2093 u8 pd[0x18]; 2094 2095 u8 reserved_at_60[0x8]; 2096 u8 uar_page[0x18]; 2097 2098 u8 dbr_addr[0x40]; 2099 2100 u8 hw_counter[0x20]; 2101 2102 u8 sw_counter[0x20]; 2103 2104 u8 reserved_at_100[0xc]; 2105 u8 log_wq_stride[0x4]; 2106 u8 reserved_at_110[0x3]; 2107 u8 log_wq_pg_sz[0x5]; 2108 u8 reserved_at_118[0x3]; 2109 u8 log_wq_sz[0x5]; 2110 2111 u8 dbr_umem_valid[0x1]; 2112 u8 wq_umem_valid[0x1]; 2113 u8 reserved_at_122[0x1]; 2114 u8 log_hairpin_num_packets[0x5]; 2115 u8 reserved_at_128[0x3]; 2116 u8 log_hairpin_data_sz[0x5]; 2117 2118 u8 reserved_at_130[0x4]; 2119 u8 log_wqe_num_of_strides[0x4]; 2120 u8 two_byte_shift_en[0x1]; 2121 u8 reserved_at_139[0x4]; 2122 u8 log_wqe_stride_size[0x3]; 2123 2124 u8 reserved_at_140[0x80]; 2125 2126 u8 headers_mkey[0x20]; 2127 2128 u8 shampo_enable[0x1]; 2129 u8 reserved_at_1e1[0x4]; 2130 u8 log_reservation_size[0x3]; 2131 u8 reserved_at_1e8[0x5]; 2132 u8 log_max_num_of_packets_per_reservation[0x3]; 2133 u8 reserved_at_1f0[0x6]; 2134 u8 log_headers_entry_size[0x2]; 2135 u8 reserved_at_1f8[0x4]; 2136 u8 log_headers_buffer_entry_num[0x4]; 2137 2138 u8 reserved_at_200[0x400]; 2139 2140 struct mlx5_ifc_cmd_pas_bits pas[]; 2141 }; 2142 2143 struct mlx5_ifc_rq_num_bits { 2144 u8 reserved_at_0[0x8]; 2145 u8 rq_num[0x18]; 2146 }; 2147 2148 struct mlx5_ifc_mac_address_layout_bits { 2149 u8 reserved_at_0[0x10]; 2150 u8 mac_addr_47_32[0x10]; 2151 2152 u8 mac_addr_31_0[0x20]; 2153 }; 2154 2155 struct mlx5_ifc_vlan_layout_bits { 2156 u8 reserved_at_0[0x14]; 2157 u8 vlan[0x0c]; 2158 2159 u8 reserved_at_20[0x20]; 2160 }; 2161 2162 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits { 2163 u8 reserved_at_0[0xa0]; 2164 2165 u8 min_time_between_cnps[0x20]; 2166 2167 u8 reserved_at_c0[0x12]; 2168 u8 cnp_dscp[0x6]; 2169 u8 reserved_at_d8[0x4]; 2170 u8 cnp_prio_mode[0x1]; 2171 u8 cnp_802p_prio[0x3]; 2172 2173 u8 reserved_at_e0[0x720]; 2174 }; 2175 2176 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits { 2177 u8 reserved_at_0[0x60]; 2178 2179 u8 reserved_at_60[0x4]; 2180 u8 clamp_tgt_rate[0x1]; 2181 u8 reserved_at_65[0x3]; 2182 u8 clamp_tgt_rate_after_time_inc[0x1]; 2183 u8 reserved_at_69[0x17]; 2184 2185 u8 reserved_at_80[0x20]; 2186 2187 u8 rpg_time_reset[0x20]; 2188 2189 u8 rpg_byte_reset[0x20]; 2190 2191 u8 rpg_threshold[0x20]; 2192 2193 u8 rpg_max_rate[0x20]; 2194 2195 u8 rpg_ai_rate[0x20]; 2196 2197 u8 rpg_hai_rate[0x20]; 2198 2199 u8 rpg_gd[0x20]; 2200 2201 u8 rpg_min_dec_fac[0x20]; 2202 2203 u8 rpg_min_rate[0x20]; 2204 2205 u8 reserved_at_1c0[0xe0]; 2206 2207 u8 rate_to_set_on_first_cnp[0x20]; 2208 2209 u8 dce_tcp_g[0x20]; 2210 2211 u8 dce_tcp_rtt[0x20]; 2212 2213 u8 rate_reduce_monitor_period[0x20]; 2214 2215 u8 reserved_at_320[0x20]; 2216 2217 u8 initial_alpha_value[0x20]; 2218 2219 u8 reserved_at_360[0x4a0]; 2220 }; 2221 2222 struct mlx5_ifc_cong_control_r_roce_general_bits { 2223 u8 reserved_at_0[0x80]; 2224 2225 u8 reserved_at_80[0x10]; 2226 u8 rtt_resp_dscp_valid[0x1]; 2227 u8 reserved_at_91[0x9]; 2228 u8 rtt_resp_dscp[0x6]; 2229 2230 u8 reserved_at_a0[0x760]; 2231 }; 2232 2233 struct mlx5_ifc_cong_control_802_1qau_rp_bits { 2234 u8 reserved_at_0[0x80]; 2235 2236 u8 rppp_max_rps[0x20]; 2237 2238 u8 rpg_time_reset[0x20]; 2239 2240 u8 rpg_byte_reset[0x20]; 2241 2242 u8 rpg_threshold[0x20]; 2243 2244 u8 rpg_max_rate[0x20]; 2245 2246 u8 rpg_ai_rate[0x20]; 2247 2248 u8 rpg_hai_rate[0x20]; 2249 2250 u8 rpg_gd[0x20]; 2251 2252 u8 rpg_min_dec_fac[0x20]; 2253 2254 u8 rpg_min_rate[0x20]; 2255 2256 u8 reserved_at_1c0[0x640]; 2257 }; 2258 2259 enum { 2260 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1, 2261 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2, 2262 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4, 2263 }; 2264 2265 struct mlx5_ifc_resize_field_select_bits { 2266 u8 resize_field_select[0x20]; 2267 }; 2268 2269 struct mlx5_ifc_resource_dump_bits { 2270 u8 more_dump[0x1]; 2271 u8 inline_dump[0x1]; 2272 u8 reserved_at_2[0xa]; 2273 u8 seq_num[0x4]; 2274 u8 segment_type[0x10]; 2275 2276 u8 reserved_at_20[0x10]; 2277 u8 vhca_id[0x10]; 2278 2279 u8 index1[0x20]; 2280 2281 u8 index2[0x20]; 2282 2283 u8 num_of_obj1[0x10]; 2284 u8 num_of_obj2[0x10]; 2285 2286 u8 reserved_at_a0[0x20]; 2287 2288 u8 device_opaque[0x40]; 2289 2290 u8 mkey[0x20]; 2291 2292 u8 size[0x20]; 2293 2294 u8 address[0x40]; 2295 2296 u8 inline_data[52][0x20]; 2297 }; 2298 2299 struct mlx5_ifc_resource_dump_menu_record_bits { 2300 u8 reserved_at_0[0x4]; 2301 u8 num_of_obj2_supports_active[0x1]; 2302 u8 num_of_obj2_supports_all[0x1]; 2303 u8 must_have_num_of_obj2[0x1]; 2304 u8 support_num_of_obj2[0x1]; 2305 u8 num_of_obj1_supports_active[0x1]; 2306 u8 num_of_obj1_supports_all[0x1]; 2307 u8 must_have_num_of_obj1[0x1]; 2308 u8 support_num_of_obj1[0x1]; 2309 u8 must_have_index2[0x1]; 2310 u8 support_index2[0x1]; 2311 u8 must_have_index1[0x1]; 2312 u8 support_index1[0x1]; 2313 u8 segment_type[0x10]; 2314 2315 u8 segment_name[4][0x20]; 2316 2317 u8 index1_name[4][0x20]; 2318 2319 u8 index2_name[4][0x20]; 2320 }; 2321 2322 struct mlx5_ifc_resource_dump_segment_header_bits { 2323 u8 length_dw[0x10]; 2324 u8 segment_type[0x10]; 2325 }; 2326 2327 struct mlx5_ifc_resource_dump_command_segment_bits { 2328 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2329 2330 u8 segment_called[0x10]; 2331 u8 vhca_id[0x10]; 2332 2333 u8 index1[0x20]; 2334 2335 u8 index2[0x20]; 2336 2337 u8 num_of_obj1[0x10]; 2338 u8 num_of_obj2[0x10]; 2339 }; 2340 2341 struct mlx5_ifc_resource_dump_error_segment_bits { 2342 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2343 2344 u8 reserved_at_20[0x10]; 2345 u8 syndrome_id[0x10]; 2346 2347 u8 reserved_at_40[0x40]; 2348 2349 u8 error[8][0x20]; 2350 }; 2351 2352 struct mlx5_ifc_resource_dump_info_segment_bits { 2353 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2354 2355 u8 reserved_at_20[0x18]; 2356 u8 dump_version[0x8]; 2357 2358 u8 hw_version[0x20]; 2359 2360 u8 fw_version[0x20]; 2361 }; 2362 2363 struct mlx5_ifc_resource_dump_menu_segment_bits { 2364 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2365 2366 u8 reserved_at_20[0x10]; 2367 u8 num_of_records[0x10]; 2368 2369 struct mlx5_ifc_resource_dump_menu_record_bits record[]; 2370 }; 2371 2372 struct mlx5_ifc_resource_dump_resource_segment_bits { 2373 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2374 2375 u8 reserved_at_20[0x20]; 2376 2377 u8 index1[0x20]; 2378 2379 u8 index2[0x20]; 2380 2381 u8 payload[][0x20]; 2382 }; 2383 2384 struct mlx5_ifc_resource_dump_terminate_segment_bits { 2385 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2386 }; 2387 2388 struct mlx5_ifc_menu_resource_dump_response_bits { 2389 struct mlx5_ifc_resource_dump_info_segment_bits info; 2390 struct mlx5_ifc_resource_dump_command_segment_bits cmd; 2391 struct mlx5_ifc_resource_dump_menu_segment_bits menu; 2392 struct mlx5_ifc_resource_dump_terminate_segment_bits terminate; 2393 }; 2394 2395 enum { 2396 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1, 2397 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2, 2398 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4, 2399 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8, 2400 }; 2401 2402 struct mlx5_ifc_modify_field_select_bits { 2403 u8 modify_field_select[0x20]; 2404 }; 2405 2406 struct mlx5_ifc_field_select_r_roce_np_bits { 2407 u8 field_select_r_roce_np[0x20]; 2408 }; 2409 2410 struct mlx5_ifc_field_select_r_roce_rp_bits { 2411 u8 field_select_r_roce_rp[0x20]; 2412 }; 2413 2414 enum { 2415 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4, 2416 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8, 2417 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10, 2418 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20, 2419 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40, 2420 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80, 2421 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100, 2422 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200, 2423 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400, 2424 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800, 2425 }; 2426 2427 struct mlx5_ifc_field_select_802_1qau_rp_bits { 2428 u8 field_select_8021qaurp[0x20]; 2429 }; 2430 2431 struct mlx5_ifc_phys_layer_cntrs_bits { 2432 u8 time_since_last_clear_high[0x20]; 2433 2434 u8 time_since_last_clear_low[0x20]; 2435 2436 u8 symbol_errors_high[0x20]; 2437 2438 u8 symbol_errors_low[0x20]; 2439 2440 u8 sync_headers_errors_high[0x20]; 2441 2442 u8 sync_headers_errors_low[0x20]; 2443 2444 u8 edpl_bip_errors_lane0_high[0x20]; 2445 2446 u8 edpl_bip_errors_lane0_low[0x20]; 2447 2448 u8 edpl_bip_errors_lane1_high[0x20]; 2449 2450 u8 edpl_bip_errors_lane1_low[0x20]; 2451 2452 u8 edpl_bip_errors_lane2_high[0x20]; 2453 2454 u8 edpl_bip_errors_lane2_low[0x20]; 2455 2456 u8 edpl_bip_errors_lane3_high[0x20]; 2457 2458 u8 edpl_bip_errors_lane3_low[0x20]; 2459 2460 u8 fc_fec_corrected_blocks_lane0_high[0x20]; 2461 2462 u8 fc_fec_corrected_blocks_lane0_low[0x20]; 2463 2464 u8 fc_fec_corrected_blocks_lane1_high[0x20]; 2465 2466 u8 fc_fec_corrected_blocks_lane1_low[0x20]; 2467 2468 u8 fc_fec_corrected_blocks_lane2_high[0x20]; 2469 2470 u8 fc_fec_corrected_blocks_lane2_low[0x20]; 2471 2472 u8 fc_fec_corrected_blocks_lane3_high[0x20]; 2473 2474 u8 fc_fec_corrected_blocks_lane3_low[0x20]; 2475 2476 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20]; 2477 2478 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20]; 2479 2480 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20]; 2481 2482 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20]; 2483 2484 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20]; 2485 2486 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20]; 2487 2488 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20]; 2489 2490 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20]; 2491 2492 u8 rs_fec_corrected_blocks_high[0x20]; 2493 2494 u8 rs_fec_corrected_blocks_low[0x20]; 2495 2496 u8 rs_fec_uncorrectable_blocks_high[0x20]; 2497 2498 u8 rs_fec_uncorrectable_blocks_low[0x20]; 2499 2500 u8 rs_fec_no_errors_blocks_high[0x20]; 2501 2502 u8 rs_fec_no_errors_blocks_low[0x20]; 2503 2504 u8 rs_fec_single_error_blocks_high[0x20]; 2505 2506 u8 rs_fec_single_error_blocks_low[0x20]; 2507 2508 u8 rs_fec_corrected_symbols_total_high[0x20]; 2509 2510 u8 rs_fec_corrected_symbols_total_low[0x20]; 2511 2512 u8 rs_fec_corrected_symbols_lane0_high[0x20]; 2513 2514 u8 rs_fec_corrected_symbols_lane0_low[0x20]; 2515 2516 u8 rs_fec_corrected_symbols_lane1_high[0x20]; 2517 2518 u8 rs_fec_corrected_symbols_lane1_low[0x20]; 2519 2520 u8 rs_fec_corrected_symbols_lane2_high[0x20]; 2521 2522 u8 rs_fec_corrected_symbols_lane2_low[0x20]; 2523 2524 u8 rs_fec_corrected_symbols_lane3_high[0x20]; 2525 2526 u8 rs_fec_corrected_symbols_lane3_low[0x20]; 2527 2528 u8 link_down_events[0x20]; 2529 2530 u8 successful_recovery_events[0x20]; 2531 2532 u8 reserved_at_640[0x180]; 2533 }; 2534 2535 struct mlx5_ifc_phys_layer_statistical_cntrs_bits { 2536 u8 time_since_last_clear_high[0x20]; 2537 2538 u8 time_since_last_clear_low[0x20]; 2539 2540 u8 phy_received_bits_high[0x20]; 2541 2542 u8 phy_received_bits_low[0x20]; 2543 2544 u8 phy_symbol_errors_high[0x20]; 2545 2546 u8 phy_symbol_errors_low[0x20]; 2547 2548 u8 phy_corrected_bits_high[0x20]; 2549 2550 u8 phy_corrected_bits_low[0x20]; 2551 2552 u8 phy_corrected_bits_lane0_high[0x20]; 2553 2554 u8 phy_corrected_bits_lane0_low[0x20]; 2555 2556 u8 phy_corrected_bits_lane1_high[0x20]; 2557 2558 u8 phy_corrected_bits_lane1_low[0x20]; 2559 2560 u8 phy_corrected_bits_lane2_high[0x20]; 2561 2562 u8 phy_corrected_bits_lane2_low[0x20]; 2563 2564 u8 phy_corrected_bits_lane3_high[0x20]; 2565 2566 u8 phy_corrected_bits_lane3_low[0x20]; 2567 2568 u8 reserved_at_200[0x5c0]; 2569 }; 2570 2571 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits { 2572 u8 symbol_error_counter[0x10]; 2573 2574 u8 link_error_recovery_counter[0x8]; 2575 2576 u8 link_downed_counter[0x8]; 2577 2578 u8 port_rcv_errors[0x10]; 2579 2580 u8 port_rcv_remote_physical_errors[0x10]; 2581 2582 u8 port_rcv_switch_relay_errors[0x10]; 2583 2584 u8 port_xmit_discards[0x10]; 2585 2586 u8 port_xmit_constraint_errors[0x8]; 2587 2588 u8 port_rcv_constraint_errors[0x8]; 2589 2590 u8 reserved_at_70[0x8]; 2591 2592 u8 link_overrun_errors[0x8]; 2593 2594 u8 reserved_at_80[0x10]; 2595 2596 u8 vl_15_dropped[0x10]; 2597 2598 u8 reserved_at_a0[0x80]; 2599 2600 u8 port_xmit_wait[0x20]; 2601 }; 2602 2603 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits { 2604 u8 transmit_queue_high[0x20]; 2605 2606 u8 transmit_queue_low[0x20]; 2607 2608 u8 no_buffer_discard_uc_high[0x20]; 2609 2610 u8 no_buffer_discard_uc_low[0x20]; 2611 2612 u8 reserved_at_80[0x740]; 2613 }; 2614 2615 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits { 2616 u8 wred_discard_high[0x20]; 2617 2618 u8 wred_discard_low[0x20]; 2619 2620 u8 ecn_marked_tc_high[0x20]; 2621 2622 u8 ecn_marked_tc_low[0x20]; 2623 2624 u8 reserved_at_80[0x740]; 2625 }; 2626 2627 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits { 2628 u8 rx_octets_high[0x20]; 2629 2630 u8 rx_octets_low[0x20]; 2631 2632 u8 reserved_at_40[0xc0]; 2633 2634 u8 rx_frames_high[0x20]; 2635 2636 u8 rx_frames_low[0x20]; 2637 2638 u8 tx_octets_high[0x20]; 2639 2640 u8 tx_octets_low[0x20]; 2641 2642 u8 reserved_at_180[0xc0]; 2643 2644 u8 tx_frames_high[0x20]; 2645 2646 u8 tx_frames_low[0x20]; 2647 2648 u8 rx_pause_high[0x20]; 2649 2650 u8 rx_pause_low[0x20]; 2651 2652 u8 rx_pause_duration_high[0x20]; 2653 2654 u8 rx_pause_duration_low[0x20]; 2655 2656 u8 tx_pause_high[0x20]; 2657 2658 u8 tx_pause_low[0x20]; 2659 2660 u8 tx_pause_duration_high[0x20]; 2661 2662 u8 tx_pause_duration_low[0x20]; 2663 2664 u8 rx_pause_transition_high[0x20]; 2665 2666 u8 rx_pause_transition_low[0x20]; 2667 2668 u8 rx_discards_high[0x20]; 2669 2670 u8 rx_discards_low[0x20]; 2671 2672 u8 device_stall_minor_watermark_cnt_high[0x20]; 2673 2674 u8 device_stall_minor_watermark_cnt_low[0x20]; 2675 2676 u8 device_stall_critical_watermark_cnt_high[0x20]; 2677 2678 u8 device_stall_critical_watermark_cnt_low[0x20]; 2679 2680 u8 reserved_at_480[0x340]; 2681 }; 2682 2683 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits { 2684 u8 port_transmit_wait_high[0x20]; 2685 2686 u8 port_transmit_wait_low[0x20]; 2687 2688 u8 reserved_at_40[0x100]; 2689 2690 u8 rx_buffer_almost_full_high[0x20]; 2691 2692 u8 rx_buffer_almost_full_low[0x20]; 2693 2694 u8 rx_buffer_full_high[0x20]; 2695 2696 u8 rx_buffer_full_low[0x20]; 2697 2698 u8 rx_icrc_encapsulated_high[0x20]; 2699 2700 u8 rx_icrc_encapsulated_low[0x20]; 2701 2702 u8 reserved_at_200[0x5c0]; 2703 }; 2704 2705 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits { 2706 u8 dot3stats_alignment_errors_high[0x20]; 2707 2708 u8 dot3stats_alignment_errors_low[0x20]; 2709 2710 u8 dot3stats_fcs_errors_high[0x20]; 2711 2712 u8 dot3stats_fcs_errors_low[0x20]; 2713 2714 u8 dot3stats_single_collision_frames_high[0x20]; 2715 2716 u8 dot3stats_single_collision_frames_low[0x20]; 2717 2718 u8 dot3stats_multiple_collision_frames_high[0x20]; 2719 2720 u8 dot3stats_multiple_collision_frames_low[0x20]; 2721 2722 u8 dot3stats_sqe_test_errors_high[0x20]; 2723 2724 u8 dot3stats_sqe_test_errors_low[0x20]; 2725 2726 u8 dot3stats_deferred_transmissions_high[0x20]; 2727 2728 u8 dot3stats_deferred_transmissions_low[0x20]; 2729 2730 u8 dot3stats_late_collisions_high[0x20]; 2731 2732 u8 dot3stats_late_collisions_low[0x20]; 2733 2734 u8 dot3stats_excessive_collisions_high[0x20]; 2735 2736 u8 dot3stats_excessive_collisions_low[0x20]; 2737 2738 u8 dot3stats_internal_mac_transmit_errors_high[0x20]; 2739 2740 u8 dot3stats_internal_mac_transmit_errors_low[0x20]; 2741 2742 u8 dot3stats_carrier_sense_errors_high[0x20]; 2743 2744 u8 dot3stats_carrier_sense_errors_low[0x20]; 2745 2746 u8 dot3stats_frame_too_longs_high[0x20]; 2747 2748 u8 dot3stats_frame_too_longs_low[0x20]; 2749 2750 u8 dot3stats_internal_mac_receive_errors_high[0x20]; 2751 2752 u8 dot3stats_internal_mac_receive_errors_low[0x20]; 2753 2754 u8 dot3stats_symbol_errors_high[0x20]; 2755 2756 u8 dot3stats_symbol_errors_low[0x20]; 2757 2758 u8 dot3control_in_unknown_opcodes_high[0x20]; 2759 2760 u8 dot3control_in_unknown_opcodes_low[0x20]; 2761 2762 u8 dot3in_pause_frames_high[0x20]; 2763 2764 u8 dot3in_pause_frames_low[0x20]; 2765 2766 u8 dot3out_pause_frames_high[0x20]; 2767 2768 u8 dot3out_pause_frames_low[0x20]; 2769 2770 u8 reserved_at_400[0x3c0]; 2771 }; 2772 2773 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits { 2774 u8 ether_stats_drop_events_high[0x20]; 2775 2776 u8 ether_stats_drop_events_low[0x20]; 2777 2778 u8 ether_stats_octets_high[0x20]; 2779 2780 u8 ether_stats_octets_low[0x20]; 2781 2782 u8 ether_stats_pkts_high[0x20]; 2783 2784 u8 ether_stats_pkts_low[0x20]; 2785 2786 u8 ether_stats_broadcast_pkts_high[0x20]; 2787 2788 u8 ether_stats_broadcast_pkts_low[0x20]; 2789 2790 u8 ether_stats_multicast_pkts_high[0x20]; 2791 2792 u8 ether_stats_multicast_pkts_low[0x20]; 2793 2794 u8 ether_stats_crc_align_errors_high[0x20]; 2795 2796 u8 ether_stats_crc_align_errors_low[0x20]; 2797 2798 u8 ether_stats_undersize_pkts_high[0x20]; 2799 2800 u8 ether_stats_undersize_pkts_low[0x20]; 2801 2802 u8 ether_stats_oversize_pkts_high[0x20]; 2803 2804 u8 ether_stats_oversize_pkts_low[0x20]; 2805 2806 u8 ether_stats_fragments_high[0x20]; 2807 2808 u8 ether_stats_fragments_low[0x20]; 2809 2810 u8 ether_stats_jabbers_high[0x20]; 2811 2812 u8 ether_stats_jabbers_low[0x20]; 2813 2814 u8 ether_stats_collisions_high[0x20]; 2815 2816 u8 ether_stats_collisions_low[0x20]; 2817 2818 u8 ether_stats_pkts64octets_high[0x20]; 2819 2820 u8 ether_stats_pkts64octets_low[0x20]; 2821 2822 u8 ether_stats_pkts65to127octets_high[0x20]; 2823 2824 u8 ether_stats_pkts65to127octets_low[0x20]; 2825 2826 u8 ether_stats_pkts128to255octets_high[0x20]; 2827 2828 u8 ether_stats_pkts128to255octets_low[0x20]; 2829 2830 u8 ether_stats_pkts256to511octets_high[0x20]; 2831 2832 u8 ether_stats_pkts256to511octets_low[0x20]; 2833 2834 u8 ether_stats_pkts512to1023octets_high[0x20]; 2835 2836 u8 ether_stats_pkts512to1023octets_low[0x20]; 2837 2838 u8 ether_stats_pkts1024to1518octets_high[0x20]; 2839 2840 u8 ether_stats_pkts1024to1518octets_low[0x20]; 2841 2842 u8 ether_stats_pkts1519to2047octets_high[0x20]; 2843 2844 u8 ether_stats_pkts1519to2047octets_low[0x20]; 2845 2846 u8 ether_stats_pkts2048to4095octets_high[0x20]; 2847 2848 u8 ether_stats_pkts2048to4095octets_low[0x20]; 2849 2850 u8 ether_stats_pkts4096to8191octets_high[0x20]; 2851 2852 u8 ether_stats_pkts4096to8191octets_low[0x20]; 2853 2854 u8 ether_stats_pkts8192to10239octets_high[0x20]; 2855 2856 u8 ether_stats_pkts8192to10239octets_low[0x20]; 2857 2858 u8 reserved_at_540[0x280]; 2859 }; 2860 2861 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits { 2862 u8 if_in_octets_high[0x20]; 2863 2864 u8 if_in_octets_low[0x20]; 2865 2866 u8 if_in_ucast_pkts_high[0x20]; 2867 2868 u8 if_in_ucast_pkts_low[0x20]; 2869 2870 u8 if_in_discards_high[0x20]; 2871 2872 u8 if_in_discards_low[0x20]; 2873 2874 u8 if_in_errors_high[0x20]; 2875 2876 u8 if_in_errors_low[0x20]; 2877 2878 u8 if_in_unknown_protos_high[0x20]; 2879 2880 u8 if_in_unknown_protos_low[0x20]; 2881 2882 u8 if_out_octets_high[0x20]; 2883 2884 u8 if_out_octets_low[0x20]; 2885 2886 u8 if_out_ucast_pkts_high[0x20]; 2887 2888 u8 if_out_ucast_pkts_low[0x20]; 2889 2890 u8 if_out_discards_high[0x20]; 2891 2892 u8 if_out_discards_low[0x20]; 2893 2894 u8 if_out_errors_high[0x20]; 2895 2896 u8 if_out_errors_low[0x20]; 2897 2898 u8 if_in_multicast_pkts_high[0x20]; 2899 2900 u8 if_in_multicast_pkts_low[0x20]; 2901 2902 u8 if_in_broadcast_pkts_high[0x20]; 2903 2904 u8 if_in_broadcast_pkts_low[0x20]; 2905 2906 u8 if_out_multicast_pkts_high[0x20]; 2907 2908 u8 if_out_multicast_pkts_low[0x20]; 2909 2910 u8 if_out_broadcast_pkts_high[0x20]; 2911 2912 u8 if_out_broadcast_pkts_low[0x20]; 2913 2914 u8 reserved_at_340[0x480]; 2915 }; 2916 2917 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits { 2918 u8 a_frames_transmitted_ok_high[0x20]; 2919 2920 u8 a_frames_transmitted_ok_low[0x20]; 2921 2922 u8 a_frames_received_ok_high[0x20]; 2923 2924 u8 a_frames_received_ok_low[0x20]; 2925 2926 u8 a_frame_check_sequence_errors_high[0x20]; 2927 2928 u8 a_frame_check_sequence_errors_low[0x20]; 2929 2930 u8 a_alignment_errors_high[0x20]; 2931 2932 u8 a_alignment_errors_low[0x20]; 2933 2934 u8 a_octets_transmitted_ok_high[0x20]; 2935 2936 u8 a_octets_transmitted_ok_low[0x20]; 2937 2938 u8 a_octets_received_ok_high[0x20]; 2939 2940 u8 a_octets_received_ok_low[0x20]; 2941 2942 u8 a_multicast_frames_xmitted_ok_high[0x20]; 2943 2944 u8 a_multicast_frames_xmitted_ok_low[0x20]; 2945 2946 u8 a_broadcast_frames_xmitted_ok_high[0x20]; 2947 2948 u8 a_broadcast_frames_xmitted_ok_low[0x20]; 2949 2950 u8 a_multicast_frames_received_ok_high[0x20]; 2951 2952 u8 a_multicast_frames_received_ok_low[0x20]; 2953 2954 u8 a_broadcast_frames_received_ok_high[0x20]; 2955 2956 u8 a_broadcast_frames_received_ok_low[0x20]; 2957 2958 u8 a_in_range_length_errors_high[0x20]; 2959 2960 u8 a_in_range_length_errors_low[0x20]; 2961 2962 u8 a_out_of_range_length_field_high[0x20]; 2963 2964 u8 a_out_of_range_length_field_low[0x20]; 2965 2966 u8 a_frame_too_long_errors_high[0x20]; 2967 2968 u8 a_frame_too_long_errors_low[0x20]; 2969 2970 u8 a_symbol_error_during_carrier_high[0x20]; 2971 2972 u8 a_symbol_error_during_carrier_low[0x20]; 2973 2974 u8 a_mac_control_frames_transmitted_high[0x20]; 2975 2976 u8 a_mac_control_frames_transmitted_low[0x20]; 2977 2978 u8 a_mac_control_frames_received_high[0x20]; 2979 2980 u8 a_mac_control_frames_received_low[0x20]; 2981 2982 u8 a_unsupported_opcodes_received_high[0x20]; 2983 2984 u8 a_unsupported_opcodes_received_low[0x20]; 2985 2986 u8 a_pause_mac_ctrl_frames_received_high[0x20]; 2987 2988 u8 a_pause_mac_ctrl_frames_received_low[0x20]; 2989 2990 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20]; 2991 2992 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20]; 2993 2994 u8 reserved_at_4c0[0x300]; 2995 }; 2996 2997 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits { 2998 u8 life_time_counter_high[0x20]; 2999 3000 u8 life_time_counter_low[0x20]; 3001 3002 u8 rx_errors[0x20]; 3003 3004 u8 tx_errors[0x20]; 3005 3006 u8 l0_to_recovery_eieos[0x20]; 3007 3008 u8 l0_to_recovery_ts[0x20]; 3009 3010 u8 l0_to_recovery_framing[0x20]; 3011 3012 u8 l0_to_recovery_retrain[0x20]; 3013 3014 u8 crc_error_dllp[0x20]; 3015 3016 u8 crc_error_tlp[0x20]; 3017 3018 u8 tx_overflow_buffer_pkt_high[0x20]; 3019 3020 u8 tx_overflow_buffer_pkt_low[0x20]; 3021 3022 u8 outbound_stalled_reads[0x20]; 3023 3024 u8 outbound_stalled_writes[0x20]; 3025 3026 u8 outbound_stalled_reads_events[0x20]; 3027 3028 u8 outbound_stalled_writes_events[0x20]; 3029 3030 u8 reserved_at_200[0x5c0]; 3031 }; 3032 3033 struct mlx5_ifc_cmd_inter_comp_event_bits { 3034 u8 command_completion_vector[0x20]; 3035 3036 u8 reserved_at_20[0xc0]; 3037 }; 3038 3039 struct mlx5_ifc_stall_vl_event_bits { 3040 u8 reserved_at_0[0x18]; 3041 u8 port_num[0x1]; 3042 u8 reserved_at_19[0x3]; 3043 u8 vl[0x4]; 3044 3045 u8 reserved_at_20[0xa0]; 3046 }; 3047 3048 struct mlx5_ifc_db_bf_congestion_event_bits { 3049 u8 event_subtype[0x8]; 3050 u8 reserved_at_8[0x8]; 3051 u8 congestion_level[0x8]; 3052 u8 reserved_at_18[0x8]; 3053 3054 u8 reserved_at_20[0xa0]; 3055 }; 3056 3057 struct mlx5_ifc_gpio_event_bits { 3058 u8 reserved_at_0[0x60]; 3059 3060 u8 gpio_event_hi[0x20]; 3061 3062 u8 gpio_event_lo[0x20]; 3063 3064 u8 reserved_at_a0[0x40]; 3065 }; 3066 3067 struct mlx5_ifc_port_state_change_event_bits { 3068 u8 reserved_at_0[0x40]; 3069 3070 u8 port_num[0x4]; 3071 u8 reserved_at_44[0x1c]; 3072 3073 u8 reserved_at_60[0x80]; 3074 }; 3075 3076 struct mlx5_ifc_dropped_packet_logged_bits { 3077 u8 reserved_at_0[0xe0]; 3078 }; 3079 3080 struct mlx5_ifc_default_timeout_bits { 3081 u8 to_multiplier[0x3]; 3082 u8 reserved_at_3[0x9]; 3083 u8 to_value[0x14]; 3084 }; 3085 3086 struct mlx5_ifc_dtor_reg_bits { 3087 u8 reserved_at_0[0x20]; 3088 3089 struct mlx5_ifc_default_timeout_bits pcie_toggle_to; 3090 3091 u8 reserved_at_40[0x60]; 3092 3093 struct mlx5_ifc_default_timeout_bits health_poll_to; 3094 3095 struct mlx5_ifc_default_timeout_bits full_crdump_to; 3096 3097 struct mlx5_ifc_default_timeout_bits fw_reset_to; 3098 3099 struct mlx5_ifc_default_timeout_bits flush_on_err_to; 3100 3101 struct mlx5_ifc_default_timeout_bits pci_sync_update_to; 3102 3103 struct mlx5_ifc_default_timeout_bits tear_down_to; 3104 3105 struct mlx5_ifc_default_timeout_bits fsm_reactivate_to; 3106 3107 struct mlx5_ifc_default_timeout_bits reclaim_pages_to; 3108 3109 struct mlx5_ifc_default_timeout_bits reclaim_vfs_pages_to; 3110 3111 struct mlx5_ifc_default_timeout_bits reset_unload_to; 3112 3113 u8 reserved_at_1c0[0x20]; 3114 }; 3115 3116 enum { 3117 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1, 3118 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2, 3119 }; 3120 3121 struct mlx5_ifc_cq_error_bits { 3122 u8 reserved_at_0[0x8]; 3123 u8 cqn[0x18]; 3124 3125 u8 reserved_at_20[0x20]; 3126 3127 u8 reserved_at_40[0x18]; 3128 u8 syndrome[0x8]; 3129 3130 u8 reserved_at_60[0x80]; 3131 }; 3132 3133 struct mlx5_ifc_rdma_page_fault_event_bits { 3134 u8 bytes_committed[0x20]; 3135 3136 u8 r_key[0x20]; 3137 3138 u8 reserved_at_40[0x10]; 3139 u8 packet_len[0x10]; 3140 3141 u8 rdma_op_len[0x20]; 3142 3143 u8 rdma_va[0x40]; 3144 3145 u8 reserved_at_c0[0x5]; 3146 u8 rdma[0x1]; 3147 u8 write[0x1]; 3148 u8 requestor[0x1]; 3149 u8 qp_number[0x18]; 3150 }; 3151 3152 struct mlx5_ifc_wqe_associated_page_fault_event_bits { 3153 u8 bytes_committed[0x20]; 3154 3155 u8 reserved_at_20[0x10]; 3156 u8 wqe_index[0x10]; 3157 3158 u8 reserved_at_40[0x10]; 3159 u8 len[0x10]; 3160 3161 u8 reserved_at_60[0x60]; 3162 3163 u8 reserved_at_c0[0x5]; 3164 u8 rdma[0x1]; 3165 u8 write_read[0x1]; 3166 u8 requestor[0x1]; 3167 u8 qpn[0x18]; 3168 }; 3169 3170 struct mlx5_ifc_qp_events_bits { 3171 u8 reserved_at_0[0xa0]; 3172 3173 u8 type[0x8]; 3174 u8 reserved_at_a8[0x18]; 3175 3176 u8 reserved_at_c0[0x8]; 3177 u8 qpn_rqn_sqn[0x18]; 3178 }; 3179 3180 struct mlx5_ifc_dct_events_bits { 3181 u8 reserved_at_0[0xc0]; 3182 3183 u8 reserved_at_c0[0x8]; 3184 u8 dct_number[0x18]; 3185 }; 3186 3187 struct mlx5_ifc_comp_event_bits { 3188 u8 reserved_at_0[0xc0]; 3189 3190 u8 reserved_at_c0[0x8]; 3191 u8 cq_number[0x18]; 3192 }; 3193 3194 enum { 3195 MLX5_QPC_STATE_RST = 0x0, 3196 MLX5_QPC_STATE_INIT = 0x1, 3197 MLX5_QPC_STATE_RTR = 0x2, 3198 MLX5_QPC_STATE_RTS = 0x3, 3199 MLX5_QPC_STATE_SQER = 0x4, 3200 MLX5_QPC_STATE_ERR = 0x6, 3201 MLX5_QPC_STATE_SQD = 0x7, 3202 MLX5_QPC_STATE_SUSPENDED = 0x9, 3203 }; 3204 3205 enum { 3206 MLX5_QPC_ST_RC = 0x0, 3207 MLX5_QPC_ST_UC = 0x1, 3208 MLX5_QPC_ST_UD = 0x2, 3209 MLX5_QPC_ST_XRC = 0x3, 3210 MLX5_QPC_ST_DCI = 0x5, 3211 MLX5_QPC_ST_QP0 = 0x7, 3212 MLX5_QPC_ST_QP1 = 0x8, 3213 MLX5_QPC_ST_RAW_DATAGRAM = 0x9, 3214 MLX5_QPC_ST_REG_UMR = 0xc, 3215 }; 3216 3217 enum { 3218 MLX5_QPC_PM_STATE_ARMED = 0x0, 3219 MLX5_QPC_PM_STATE_REARM = 0x1, 3220 MLX5_QPC_PM_STATE_RESERVED = 0x2, 3221 MLX5_QPC_PM_STATE_MIGRATED = 0x3, 3222 }; 3223 3224 enum { 3225 MLX5_QPC_OFFLOAD_TYPE_RNDV = 0x1, 3226 }; 3227 3228 enum { 3229 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0, 3230 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1, 3231 }; 3232 3233 enum { 3234 MLX5_QPC_MTU_256_BYTES = 0x1, 3235 MLX5_QPC_MTU_512_BYTES = 0x2, 3236 MLX5_QPC_MTU_1K_BYTES = 0x3, 3237 MLX5_QPC_MTU_2K_BYTES = 0x4, 3238 MLX5_QPC_MTU_4K_BYTES = 0x5, 3239 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7, 3240 }; 3241 3242 enum { 3243 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1, 3244 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2, 3245 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3, 3246 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4, 3247 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5, 3248 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6, 3249 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7, 3250 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8, 3251 }; 3252 3253 enum { 3254 MLX5_QPC_CS_REQ_DISABLE = 0x0, 3255 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11, 3256 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22, 3257 }; 3258 3259 enum { 3260 MLX5_QPC_CS_RES_DISABLE = 0x0, 3261 MLX5_QPC_CS_RES_UP_TO_32B = 0x1, 3262 MLX5_QPC_CS_RES_UP_TO_64B = 0x2, 3263 }; 3264 3265 enum { 3266 MLX5_TIMESTAMP_FORMAT_FREE_RUNNING = 0x0, 3267 MLX5_TIMESTAMP_FORMAT_DEFAULT = 0x1, 3268 MLX5_TIMESTAMP_FORMAT_REAL_TIME = 0x2, 3269 }; 3270 3271 struct mlx5_ifc_qpc_bits { 3272 u8 state[0x4]; 3273 u8 lag_tx_port_affinity[0x4]; 3274 u8 st[0x8]; 3275 u8 reserved_at_10[0x2]; 3276 u8 isolate_vl_tc[0x1]; 3277 u8 pm_state[0x2]; 3278 u8 reserved_at_15[0x1]; 3279 u8 req_e2e_credit_mode[0x2]; 3280 u8 offload_type[0x4]; 3281 u8 end_padding_mode[0x2]; 3282 u8 reserved_at_1e[0x2]; 3283 3284 u8 wq_signature[0x1]; 3285 u8 block_lb_mc[0x1]; 3286 u8 atomic_like_write_en[0x1]; 3287 u8 latency_sensitive[0x1]; 3288 u8 reserved_at_24[0x1]; 3289 u8 drain_sigerr[0x1]; 3290 u8 reserved_at_26[0x2]; 3291 u8 pd[0x18]; 3292 3293 u8 mtu[0x3]; 3294 u8 log_msg_max[0x5]; 3295 u8 reserved_at_48[0x1]; 3296 u8 log_rq_size[0x4]; 3297 u8 log_rq_stride[0x3]; 3298 u8 no_sq[0x1]; 3299 u8 log_sq_size[0x4]; 3300 u8 reserved_at_55[0x1]; 3301 u8 retry_mode[0x2]; 3302 u8 ts_format[0x2]; 3303 u8 reserved_at_5a[0x1]; 3304 u8 rlky[0x1]; 3305 u8 ulp_stateless_offload_mode[0x4]; 3306 3307 u8 counter_set_id[0x8]; 3308 u8 uar_page[0x18]; 3309 3310 u8 reserved_at_80[0x8]; 3311 u8 user_index[0x18]; 3312 3313 u8 reserved_at_a0[0x3]; 3314 u8 log_page_size[0x5]; 3315 u8 remote_qpn[0x18]; 3316 3317 struct mlx5_ifc_ads_bits primary_address_path; 3318 3319 struct mlx5_ifc_ads_bits secondary_address_path; 3320 3321 u8 log_ack_req_freq[0x4]; 3322 u8 reserved_at_384[0x4]; 3323 u8 log_sra_max[0x3]; 3324 u8 reserved_at_38b[0x2]; 3325 u8 retry_count[0x3]; 3326 u8 rnr_retry[0x3]; 3327 u8 reserved_at_393[0x1]; 3328 u8 fre[0x1]; 3329 u8 cur_rnr_retry[0x3]; 3330 u8 cur_retry_count[0x3]; 3331 u8 reserved_at_39b[0x5]; 3332 3333 u8 reserved_at_3a0[0x20]; 3334 3335 u8 reserved_at_3c0[0x8]; 3336 u8 next_send_psn[0x18]; 3337 3338 u8 reserved_at_3e0[0x3]; 3339 u8 log_num_dci_stream_channels[0x5]; 3340 u8 cqn_snd[0x18]; 3341 3342 u8 reserved_at_400[0x3]; 3343 u8 log_num_dci_errored_streams[0x5]; 3344 u8 deth_sqpn[0x18]; 3345 3346 u8 reserved_at_420[0x20]; 3347 3348 u8 reserved_at_440[0x8]; 3349 u8 last_acked_psn[0x18]; 3350 3351 u8 reserved_at_460[0x8]; 3352 u8 ssn[0x18]; 3353 3354 u8 reserved_at_480[0x8]; 3355 u8 log_rra_max[0x3]; 3356 u8 reserved_at_48b[0x1]; 3357 u8 atomic_mode[0x4]; 3358 u8 rre[0x1]; 3359 u8 rwe[0x1]; 3360 u8 rae[0x1]; 3361 u8 reserved_at_493[0x1]; 3362 u8 page_offset[0x6]; 3363 u8 reserved_at_49a[0x3]; 3364 u8 cd_slave_receive[0x1]; 3365 u8 cd_slave_send[0x1]; 3366 u8 cd_master[0x1]; 3367 3368 u8 reserved_at_4a0[0x3]; 3369 u8 min_rnr_nak[0x5]; 3370 u8 next_rcv_psn[0x18]; 3371 3372 u8 reserved_at_4c0[0x8]; 3373 u8 xrcd[0x18]; 3374 3375 u8 reserved_at_4e0[0x8]; 3376 u8 cqn_rcv[0x18]; 3377 3378 u8 dbr_addr[0x40]; 3379 3380 u8 q_key[0x20]; 3381 3382 u8 reserved_at_560[0x5]; 3383 u8 rq_type[0x3]; 3384 u8 srqn_rmpn_xrqn[0x18]; 3385 3386 u8 reserved_at_580[0x8]; 3387 u8 rmsn[0x18]; 3388 3389 u8 hw_sq_wqebb_counter[0x10]; 3390 u8 sw_sq_wqebb_counter[0x10]; 3391 3392 u8 hw_rq_counter[0x20]; 3393 3394 u8 sw_rq_counter[0x20]; 3395 3396 u8 reserved_at_600[0x20]; 3397 3398 u8 reserved_at_620[0xf]; 3399 u8 cgs[0x1]; 3400 u8 cs_req[0x8]; 3401 u8 cs_res[0x8]; 3402 3403 u8 dc_access_key[0x40]; 3404 3405 u8 reserved_at_680[0x3]; 3406 u8 dbr_umem_valid[0x1]; 3407 3408 u8 reserved_at_684[0xbc]; 3409 }; 3410 3411 struct mlx5_ifc_roce_addr_layout_bits { 3412 u8 source_l3_address[16][0x8]; 3413 3414 u8 reserved_at_80[0x3]; 3415 u8 vlan_valid[0x1]; 3416 u8 vlan_id[0xc]; 3417 u8 source_mac_47_32[0x10]; 3418 3419 u8 source_mac_31_0[0x20]; 3420 3421 u8 reserved_at_c0[0x14]; 3422 u8 roce_l3_type[0x4]; 3423 u8 roce_version[0x8]; 3424 3425 u8 reserved_at_e0[0x20]; 3426 }; 3427 3428 struct mlx5_ifc_crypto_cap_bits { 3429 u8 reserved_at_0[0x3]; 3430 u8 synchronize_dek[0x1]; 3431 u8 int_kek_manual[0x1]; 3432 u8 int_kek_auto[0x1]; 3433 u8 reserved_at_6[0x1a]; 3434 3435 u8 reserved_at_20[0x3]; 3436 u8 log_dek_max_alloc[0x5]; 3437 u8 reserved_at_28[0x3]; 3438 u8 log_max_num_deks[0x5]; 3439 u8 reserved_at_30[0x10]; 3440 3441 u8 reserved_at_40[0x20]; 3442 3443 u8 reserved_at_60[0x3]; 3444 u8 log_dek_granularity[0x5]; 3445 u8 reserved_at_68[0x3]; 3446 u8 log_max_num_int_kek[0x5]; 3447 u8 sw_wrapped_dek[0x10]; 3448 3449 u8 reserved_at_80[0x780]; 3450 }; 3451 3452 union mlx5_ifc_hca_cap_union_bits { 3453 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap; 3454 struct mlx5_ifc_cmd_hca_cap_2_bits cmd_hca_cap_2; 3455 struct mlx5_ifc_odp_cap_bits odp_cap; 3456 struct mlx5_ifc_atomic_caps_bits atomic_caps; 3457 struct mlx5_ifc_roce_cap_bits roce_cap; 3458 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps; 3459 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap; 3460 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap; 3461 struct mlx5_ifc_e_switch_cap_bits e_switch_cap; 3462 struct mlx5_ifc_port_selection_cap_bits port_selection_cap; 3463 struct mlx5_ifc_qos_cap_bits qos_cap; 3464 struct mlx5_ifc_debug_cap_bits debug_cap; 3465 struct mlx5_ifc_fpga_cap_bits fpga_cap; 3466 struct mlx5_ifc_tls_cap_bits tls_cap; 3467 struct mlx5_ifc_device_mem_cap_bits device_mem_cap; 3468 struct mlx5_ifc_virtio_emulation_cap_bits virtio_emulation_cap; 3469 struct mlx5_ifc_macsec_cap_bits macsec_cap; 3470 struct mlx5_ifc_crypto_cap_bits crypto_cap; 3471 struct mlx5_ifc_ipsec_cap_bits ipsec_cap; 3472 u8 reserved_at_0[0x8000]; 3473 }; 3474 3475 enum { 3476 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1, 3477 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2, 3478 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4, 3479 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8, 3480 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT = 0x10, 3481 MLX5_FLOW_CONTEXT_ACTION_DECAP = 0x20, 3482 MLX5_FLOW_CONTEXT_ACTION_MOD_HDR = 0x40, 3483 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP = 0x80, 3484 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100, 3485 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2 = 0x400, 3486 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2 = 0x800, 3487 MLX5_FLOW_CONTEXT_ACTION_CRYPTO_DECRYPT = 0x1000, 3488 MLX5_FLOW_CONTEXT_ACTION_CRYPTO_ENCRYPT = 0x2000, 3489 MLX5_FLOW_CONTEXT_ACTION_EXECUTE_ASO = 0x4000, 3490 }; 3491 3492 enum { 3493 MLX5_FLOW_CONTEXT_FLOW_SOURCE_ANY_VPORT = 0x0, 3494 MLX5_FLOW_CONTEXT_FLOW_SOURCE_UPLINK = 0x1, 3495 MLX5_FLOW_CONTEXT_FLOW_SOURCE_LOCAL_VPORT = 0x2, 3496 }; 3497 3498 enum { 3499 MLX5_FLOW_CONTEXT_ENCRYPT_DECRYPT_TYPE_IPSEC = 0x0, 3500 MLX5_FLOW_CONTEXT_ENCRYPT_DECRYPT_TYPE_MACSEC = 0x1, 3501 }; 3502 3503 struct mlx5_ifc_vlan_bits { 3504 u8 ethtype[0x10]; 3505 u8 prio[0x3]; 3506 u8 cfi[0x1]; 3507 u8 vid[0xc]; 3508 }; 3509 3510 enum { 3511 MLX5_FLOW_METER_COLOR_RED = 0x0, 3512 MLX5_FLOW_METER_COLOR_YELLOW = 0x1, 3513 MLX5_FLOW_METER_COLOR_GREEN = 0x2, 3514 MLX5_FLOW_METER_COLOR_UNDEFINED = 0x3, 3515 }; 3516 3517 enum { 3518 MLX5_EXE_ASO_FLOW_METER = 0x2, 3519 }; 3520 3521 struct mlx5_ifc_exe_aso_ctrl_flow_meter_bits { 3522 u8 return_reg_id[0x4]; 3523 u8 aso_type[0x4]; 3524 u8 reserved_at_8[0x14]; 3525 u8 action[0x1]; 3526 u8 init_color[0x2]; 3527 u8 meter_id[0x1]; 3528 }; 3529 3530 union mlx5_ifc_exe_aso_ctrl { 3531 struct mlx5_ifc_exe_aso_ctrl_flow_meter_bits exe_aso_ctrl_flow_meter; 3532 }; 3533 3534 struct mlx5_ifc_execute_aso_bits { 3535 u8 valid[0x1]; 3536 u8 reserved_at_1[0x7]; 3537 u8 aso_object_id[0x18]; 3538 3539 union mlx5_ifc_exe_aso_ctrl exe_aso_ctrl; 3540 }; 3541 3542 struct mlx5_ifc_flow_context_bits { 3543 struct mlx5_ifc_vlan_bits push_vlan; 3544 3545 u8 group_id[0x20]; 3546 3547 u8 reserved_at_40[0x8]; 3548 u8 flow_tag[0x18]; 3549 3550 u8 reserved_at_60[0x10]; 3551 u8 action[0x10]; 3552 3553 u8 extended_destination[0x1]; 3554 u8 reserved_at_81[0x1]; 3555 u8 flow_source[0x2]; 3556 u8 encrypt_decrypt_type[0x4]; 3557 u8 destination_list_size[0x18]; 3558 3559 u8 reserved_at_a0[0x8]; 3560 u8 flow_counter_list_size[0x18]; 3561 3562 u8 packet_reformat_id[0x20]; 3563 3564 u8 modify_header_id[0x20]; 3565 3566 struct mlx5_ifc_vlan_bits push_vlan_2; 3567 3568 u8 encrypt_decrypt_obj_id[0x20]; 3569 u8 reserved_at_140[0xc0]; 3570 3571 struct mlx5_ifc_fte_match_param_bits match_value; 3572 3573 struct mlx5_ifc_execute_aso_bits execute_aso[4]; 3574 3575 u8 reserved_at_1300[0x500]; 3576 3577 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[]; 3578 }; 3579 3580 enum { 3581 MLX5_XRC_SRQC_STATE_GOOD = 0x0, 3582 MLX5_XRC_SRQC_STATE_ERROR = 0x1, 3583 }; 3584 3585 struct mlx5_ifc_xrc_srqc_bits { 3586 u8 state[0x4]; 3587 u8 log_xrc_srq_size[0x4]; 3588 u8 reserved_at_8[0x18]; 3589 3590 u8 wq_signature[0x1]; 3591 u8 cont_srq[0x1]; 3592 u8 reserved_at_22[0x1]; 3593 u8 rlky[0x1]; 3594 u8 basic_cyclic_rcv_wqe[0x1]; 3595 u8 log_rq_stride[0x3]; 3596 u8 xrcd[0x18]; 3597 3598 u8 page_offset[0x6]; 3599 u8 reserved_at_46[0x1]; 3600 u8 dbr_umem_valid[0x1]; 3601 u8 cqn[0x18]; 3602 3603 u8 reserved_at_60[0x20]; 3604 3605 u8 user_index_equal_xrc_srqn[0x1]; 3606 u8 reserved_at_81[0x1]; 3607 u8 log_page_size[0x6]; 3608 u8 user_index[0x18]; 3609 3610 u8 reserved_at_a0[0x20]; 3611 3612 u8 reserved_at_c0[0x8]; 3613 u8 pd[0x18]; 3614 3615 u8 lwm[0x10]; 3616 u8 wqe_cnt[0x10]; 3617 3618 u8 reserved_at_100[0x40]; 3619 3620 u8 db_record_addr_h[0x20]; 3621 3622 u8 db_record_addr_l[0x1e]; 3623 u8 reserved_at_17e[0x2]; 3624 3625 u8 reserved_at_180[0x80]; 3626 }; 3627 3628 struct mlx5_ifc_vnic_diagnostic_statistics_bits { 3629 u8 counter_error_queues[0x20]; 3630 3631 u8 total_error_queues[0x20]; 3632 3633 u8 send_queue_priority_update_flow[0x20]; 3634 3635 u8 reserved_at_60[0x20]; 3636 3637 u8 nic_receive_steering_discard[0x40]; 3638 3639 u8 receive_discard_vport_down[0x40]; 3640 3641 u8 transmit_discard_vport_down[0x40]; 3642 3643 u8 async_eq_overrun[0x20]; 3644 3645 u8 comp_eq_overrun[0x20]; 3646 3647 u8 reserved_at_180[0x20]; 3648 3649 u8 invalid_command[0x20]; 3650 3651 u8 quota_exceeded_command[0x20]; 3652 3653 u8 internal_rq_out_of_buffer[0x20]; 3654 3655 u8 cq_overrun[0x20]; 3656 3657 u8 eth_wqe_too_small[0x20]; 3658 3659 u8 reserved_at_220[0xc0]; 3660 3661 u8 generated_pkt_steering_fail[0x40]; 3662 3663 u8 handled_pkt_steering_fail[0x40]; 3664 3665 u8 reserved_at_360[0xc80]; 3666 }; 3667 3668 struct mlx5_ifc_traffic_counter_bits { 3669 u8 packets[0x40]; 3670 3671 u8 octets[0x40]; 3672 }; 3673 3674 struct mlx5_ifc_tisc_bits { 3675 u8 strict_lag_tx_port_affinity[0x1]; 3676 u8 tls_en[0x1]; 3677 u8 reserved_at_2[0x2]; 3678 u8 lag_tx_port_affinity[0x04]; 3679 3680 u8 reserved_at_8[0x4]; 3681 u8 prio[0x4]; 3682 u8 reserved_at_10[0x10]; 3683 3684 u8 reserved_at_20[0x100]; 3685 3686 u8 reserved_at_120[0x8]; 3687 u8 transport_domain[0x18]; 3688 3689 u8 reserved_at_140[0x8]; 3690 u8 underlay_qpn[0x18]; 3691 3692 u8 reserved_at_160[0x8]; 3693 u8 pd[0x18]; 3694 3695 u8 reserved_at_180[0x380]; 3696 }; 3697 3698 enum { 3699 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0, 3700 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1, 3701 }; 3702 3703 enum { 3704 MLX5_TIRC_PACKET_MERGE_MASK_IPV4_LRO = BIT(0), 3705 MLX5_TIRC_PACKET_MERGE_MASK_IPV6_LRO = BIT(1), 3706 }; 3707 3708 enum { 3709 MLX5_RX_HASH_FN_NONE = 0x0, 3710 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1, 3711 MLX5_RX_HASH_FN_TOEPLITZ = 0x2, 3712 }; 3713 3714 enum { 3715 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST = 0x1, 3716 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST = 0x2, 3717 }; 3718 3719 struct mlx5_ifc_tirc_bits { 3720 u8 reserved_at_0[0x20]; 3721 3722 u8 disp_type[0x4]; 3723 u8 tls_en[0x1]; 3724 u8 reserved_at_25[0x1b]; 3725 3726 u8 reserved_at_40[0x40]; 3727 3728 u8 reserved_at_80[0x4]; 3729 u8 lro_timeout_period_usecs[0x10]; 3730 u8 packet_merge_mask[0x4]; 3731 u8 lro_max_ip_payload_size[0x8]; 3732 3733 u8 reserved_at_a0[0x40]; 3734 3735 u8 reserved_at_e0[0x8]; 3736 u8 inline_rqn[0x18]; 3737 3738 u8 rx_hash_symmetric[0x1]; 3739 u8 reserved_at_101[0x1]; 3740 u8 tunneled_offload_en[0x1]; 3741 u8 reserved_at_103[0x5]; 3742 u8 indirect_table[0x18]; 3743 3744 u8 rx_hash_fn[0x4]; 3745 u8 reserved_at_124[0x2]; 3746 u8 self_lb_block[0x2]; 3747 u8 transport_domain[0x18]; 3748 3749 u8 rx_hash_toeplitz_key[10][0x20]; 3750 3751 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer; 3752 3753 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner; 3754 3755 u8 reserved_at_2c0[0x4c0]; 3756 }; 3757 3758 enum { 3759 MLX5_SRQC_STATE_GOOD = 0x0, 3760 MLX5_SRQC_STATE_ERROR = 0x1, 3761 }; 3762 3763 struct mlx5_ifc_srqc_bits { 3764 u8 state[0x4]; 3765 u8 log_srq_size[0x4]; 3766 u8 reserved_at_8[0x18]; 3767 3768 u8 wq_signature[0x1]; 3769 u8 cont_srq[0x1]; 3770 u8 reserved_at_22[0x1]; 3771 u8 rlky[0x1]; 3772 u8 reserved_at_24[0x1]; 3773 u8 log_rq_stride[0x3]; 3774 u8 xrcd[0x18]; 3775 3776 u8 page_offset[0x6]; 3777 u8 reserved_at_46[0x2]; 3778 u8 cqn[0x18]; 3779 3780 u8 reserved_at_60[0x20]; 3781 3782 u8 reserved_at_80[0x2]; 3783 u8 log_page_size[0x6]; 3784 u8 reserved_at_88[0x18]; 3785 3786 u8 reserved_at_a0[0x20]; 3787 3788 u8 reserved_at_c0[0x8]; 3789 u8 pd[0x18]; 3790 3791 u8 lwm[0x10]; 3792 u8 wqe_cnt[0x10]; 3793 3794 u8 reserved_at_100[0x40]; 3795 3796 u8 dbr_addr[0x40]; 3797 3798 u8 reserved_at_180[0x80]; 3799 }; 3800 3801 enum { 3802 MLX5_SQC_STATE_RST = 0x0, 3803 MLX5_SQC_STATE_RDY = 0x1, 3804 MLX5_SQC_STATE_ERR = 0x3, 3805 }; 3806 3807 struct mlx5_ifc_sqc_bits { 3808 u8 rlky[0x1]; 3809 u8 cd_master[0x1]; 3810 u8 fre[0x1]; 3811 u8 flush_in_error_en[0x1]; 3812 u8 allow_multi_pkt_send_wqe[0x1]; 3813 u8 min_wqe_inline_mode[0x3]; 3814 u8 state[0x4]; 3815 u8 reg_umr[0x1]; 3816 u8 allow_swp[0x1]; 3817 u8 hairpin[0x1]; 3818 u8 reserved_at_f[0xb]; 3819 u8 ts_format[0x2]; 3820 u8 reserved_at_1c[0x4]; 3821 3822 u8 reserved_at_20[0x8]; 3823 u8 user_index[0x18]; 3824 3825 u8 reserved_at_40[0x8]; 3826 u8 cqn[0x18]; 3827 3828 u8 reserved_at_60[0x8]; 3829 u8 hairpin_peer_rq[0x18]; 3830 3831 u8 reserved_at_80[0x10]; 3832 u8 hairpin_peer_vhca[0x10]; 3833 3834 u8 reserved_at_a0[0x20]; 3835 3836 u8 reserved_at_c0[0x8]; 3837 u8 ts_cqe_to_dest_cqn[0x18]; 3838 3839 u8 reserved_at_e0[0x10]; 3840 u8 packet_pacing_rate_limit_index[0x10]; 3841 u8 tis_lst_sz[0x10]; 3842 u8 qos_queue_group_id[0x10]; 3843 3844 u8 reserved_at_120[0x40]; 3845 3846 u8 reserved_at_160[0x8]; 3847 u8 tis_num_0[0x18]; 3848 3849 struct mlx5_ifc_wq_bits wq; 3850 }; 3851 3852 enum { 3853 SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0, 3854 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1, 3855 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2, 3856 SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3, 3857 SCHEDULING_CONTEXT_ELEMENT_TYPE_QUEUE_GROUP = 0x4, 3858 }; 3859 3860 enum { 3861 ELEMENT_TYPE_CAP_MASK_TASR = 1 << 0, 3862 ELEMENT_TYPE_CAP_MASK_VPORT = 1 << 1, 3863 ELEMENT_TYPE_CAP_MASK_VPORT_TC = 1 << 2, 3864 ELEMENT_TYPE_CAP_MASK_PARA_VPORT_TC = 1 << 3, 3865 }; 3866 3867 struct mlx5_ifc_scheduling_context_bits { 3868 u8 element_type[0x8]; 3869 u8 reserved_at_8[0x18]; 3870 3871 u8 element_attributes[0x20]; 3872 3873 u8 parent_element_id[0x20]; 3874 3875 u8 reserved_at_60[0x40]; 3876 3877 u8 bw_share[0x20]; 3878 3879 u8 max_average_bw[0x20]; 3880 3881 u8 reserved_at_e0[0x120]; 3882 }; 3883 3884 struct mlx5_ifc_rqtc_bits { 3885 u8 reserved_at_0[0xa0]; 3886 3887 u8 reserved_at_a0[0x5]; 3888 u8 list_q_type[0x3]; 3889 u8 reserved_at_a8[0x8]; 3890 u8 rqt_max_size[0x10]; 3891 3892 u8 rq_vhca_id_format[0x1]; 3893 u8 reserved_at_c1[0xf]; 3894 u8 rqt_actual_size[0x10]; 3895 3896 u8 reserved_at_e0[0x6a0]; 3897 3898 struct mlx5_ifc_rq_num_bits rq_num[]; 3899 }; 3900 3901 enum { 3902 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0, 3903 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1, 3904 }; 3905 3906 enum { 3907 MLX5_RQC_STATE_RST = 0x0, 3908 MLX5_RQC_STATE_RDY = 0x1, 3909 MLX5_RQC_STATE_ERR = 0x3, 3910 }; 3911 3912 enum { 3913 MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_BYTE = 0x0, 3914 MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_STRIDE = 0x1, 3915 MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_PAGE = 0x2, 3916 }; 3917 3918 enum { 3919 MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_NO_MATCH = 0x0, 3920 MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_EXTENDED = 0x1, 3921 MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_FIVE_TUPLE = 0x2, 3922 }; 3923 3924 struct mlx5_ifc_rqc_bits { 3925 u8 rlky[0x1]; 3926 u8 delay_drop_en[0x1]; 3927 u8 scatter_fcs[0x1]; 3928 u8 vsd[0x1]; 3929 u8 mem_rq_type[0x4]; 3930 u8 state[0x4]; 3931 u8 reserved_at_c[0x1]; 3932 u8 flush_in_error_en[0x1]; 3933 u8 hairpin[0x1]; 3934 u8 reserved_at_f[0xb]; 3935 u8 ts_format[0x2]; 3936 u8 reserved_at_1c[0x4]; 3937 3938 u8 reserved_at_20[0x8]; 3939 u8 user_index[0x18]; 3940 3941 u8 reserved_at_40[0x8]; 3942 u8 cqn[0x18]; 3943 3944 u8 counter_set_id[0x8]; 3945 u8 reserved_at_68[0x18]; 3946 3947 u8 reserved_at_80[0x8]; 3948 u8 rmpn[0x18]; 3949 3950 u8 reserved_at_a0[0x8]; 3951 u8 hairpin_peer_sq[0x18]; 3952 3953 u8 reserved_at_c0[0x10]; 3954 u8 hairpin_peer_vhca[0x10]; 3955 3956 u8 reserved_at_e0[0x46]; 3957 u8 shampo_no_match_alignment_granularity[0x2]; 3958 u8 reserved_at_128[0x6]; 3959 u8 shampo_match_criteria_type[0x2]; 3960 u8 reservation_timeout[0x10]; 3961 3962 u8 reserved_at_140[0x40]; 3963 3964 struct mlx5_ifc_wq_bits wq; 3965 }; 3966 3967 enum { 3968 MLX5_RMPC_STATE_RDY = 0x1, 3969 MLX5_RMPC_STATE_ERR = 0x3, 3970 }; 3971 3972 struct mlx5_ifc_rmpc_bits { 3973 u8 reserved_at_0[0x8]; 3974 u8 state[0x4]; 3975 u8 reserved_at_c[0x14]; 3976 3977 u8 basic_cyclic_rcv_wqe[0x1]; 3978 u8 reserved_at_21[0x1f]; 3979 3980 u8 reserved_at_40[0x140]; 3981 3982 struct mlx5_ifc_wq_bits wq; 3983 }; 3984 3985 enum { 3986 VHCA_ID_TYPE_HW = 0, 3987 VHCA_ID_TYPE_SW = 1, 3988 }; 3989 3990 struct mlx5_ifc_nic_vport_context_bits { 3991 u8 reserved_at_0[0x5]; 3992 u8 min_wqe_inline_mode[0x3]; 3993 u8 reserved_at_8[0x15]; 3994 u8 disable_mc_local_lb[0x1]; 3995 u8 disable_uc_local_lb[0x1]; 3996 u8 roce_en[0x1]; 3997 3998 u8 arm_change_event[0x1]; 3999 u8 reserved_at_21[0x1a]; 4000 u8 event_on_mtu[0x1]; 4001 u8 event_on_promisc_change[0x1]; 4002 u8 event_on_vlan_change[0x1]; 4003 u8 event_on_mc_address_change[0x1]; 4004 u8 event_on_uc_address_change[0x1]; 4005 4006 u8 vhca_id_type[0x1]; 4007 u8 reserved_at_41[0xb]; 4008 u8 affiliation_criteria[0x4]; 4009 u8 affiliated_vhca_id[0x10]; 4010 4011 u8 reserved_at_60[0xd0]; 4012 4013 u8 mtu[0x10]; 4014 4015 u8 system_image_guid[0x40]; 4016 u8 port_guid[0x40]; 4017 u8 node_guid[0x40]; 4018 4019 u8 reserved_at_200[0x140]; 4020 u8 qkey_violation_counter[0x10]; 4021 u8 reserved_at_350[0x430]; 4022 4023 u8 promisc_uc[0x1]; 4024 u8 promisc_mc[0x1]; 4025 u8 promisc_all[0x1]; 4026 u8 reserved_at_783[0x2]; 4027 u8 allowed_list_type[0x3]; 4028 u8 reserved_at_788[0xc]; 4029 u8 allowed_list_size[0xc]; 4030 4031 struct mlx5_ifc_mac_address_layout_bits permanent_address; 4032 4033 u8 reserved_at_7e0[0x20]; 4034 4035 u8 current_uc_mac_address[][0x40]; 4036 }; 4037 4038 enum { 4039 MLX5_MKC_ACCESS_MODE_PA = 0x0, 4040 MLX5_MKC_ACCESS_MODE_MTT = 0x1, 4041 MLX5_MKC_ACCESS_MODE_KLMS = 0x2, 4042 MLX5_MKC_ACCESS_MODE_KSM = 0x3, 4043 MLX5_MKC_ACCESS_MODE_SW_ICM = 0x4, 4044 MLX5_MKC_ACCESS_MODE_MEMIC = 0x5, 4045 }; 4046 4047 struct mlx5_ifc_mkc_bits { 4048 u8 reserved_at_0[0x1]; 4049 u8 free[0x1]; 4050 u8 reserved_at_2[0x1]; 4051 u8 access_mode_4_2[0x3]; 4052 u8 reserved_at_6[0x7]; 4053 u8 relaxed_ordering_write[0x1]; 4054 u8 reserved_at_e[0x1]; 4055 u8 small_fence_on_rdma_read_response[0x1]; 4056 u8 umr_en[0x1]; 4057 u8 a[0x1]; 4058 u8 rw[0x1]; 4059 u8 rr[0x1]; 4060 u8 lw[0x1]; 4061 u8 lr[0x1]; 4062 u8 access_mode_1_0[0x2]; 4063 u8 reserved_at_18[0x2]; 4064 u8 ma_translation_mode[0x2]; 4065 u8 reserved_at_1c[0x4]; 4066 4067 u8 qpn[0x18]; 4068 u8 mkey_7_0[0x8]; 4069 4070 u8 reserved_at_40[0x20]; 4071 4072 u8 length64[0x1]; 4073 u8 bsf_en[0x1]; 4074 u8 sync_umr[0x1]; 4075 u8 reserved_at_63[0x2]; 4076 u8 expected_sigerr_count[0x1]; 4077 u8 reserved_at_66[0x1]; 4078 u8 en_rinval[0x1]; 4079 u8 pd[0x18]; 4080 4081 u8 start_addr[0x40]; 4082 4083 u8 len[0x40]; 4084 4085 u8 bsf_octword_size[0x20]; 4086 4087 u8 reserved_at_120[0x80]; 4088 4089 u8 translations_octword_size[0x20]; 4090 4091 u8 reserved_at_1c0[0x19]; 4092 u8 relaxed_ordering_read[0x1]; 4093 u8 reserved_at_1d9[0x1]; 4094 u8 log_page_size[0x5]; 4095 4096 u8 reserved_at_1e0[0x20]; 4097 }; 4098 4099 struct mlx5_ifc_pkey_bits { 4100 u8 reserved_at_0[0x10]; 4101 u8 pkey[0x10]; 4102 }; 4103 4104 struct mlx5_ifc_array128_auto_bits { 4105 u8 array128_auto[16][0x8]; 4106 }; 4107 4108 struct mlx5_ifc_hca_vport_context_bits { 4109 u8 field_select[0x20]; 4110 4111 u8 reserved_at_20[0xe0]; 4112 4113 u8 sm_virt_aware[0x1]; 4114 u8 has_smi[0x1]; 4115 u8 has_raw[0x1]; 4116 u8 grh_required[0x1]; 4117 u8 reserved_at_104[0xc]; 4118 u8 port_physical_state[0x4]; 4119 u8 vport_state_policy[0x4]; 4120 u8 port_state[0x4]; 4121 u8 vport_state[0x4]; 4122 4123 u8 reserved_at_120[0x20]; 4124 4125 u8 system_image_guid[0x40]; 4126 4127 u8 port_guid[0x40]; 4128 4129 u8 node_guid[0x40]; 4130 4131 u8 cap_mask1[0x20]; 4132 4133 u8 cap_mask1_field_select[0x20]; 4134 4135 u8 cap_mask2[0x20]; 4136 4137 u8 cap_mask2_field_select[0x20]; 4138 4139 u8 reserved_at_280[0x80]; 4140 4141 u8 lid[0x10]; 4142 u8 reserved_at_310[0x4]; 4143 u8 init_type_reply[0x4]; 4144 u8 lmc[0x3]; 4145 u8 subnet_timeout[0x5]; 4146 4147 u8 sm_lid[0x10]; 4148 u8 sm_sl[0x4]; 4149 u8 reserved_at_334[0xc]; 4150 4151 u8 qkey_violation_counter[0x10]; 4152 u8 pkey_violation_counter[0x10]; 4153 4154 u8 reserved_at_360[0xca0]; 4155 }; 4156 4157 struct mlx5_ifc_esw_vport_context_bits { 4158 u8 fdb_to_vport_reg_c[0x1]; 4159 u8 reserved_at_1[0x2]; 4160 u8 vport_svlan_strip[0x1]; 4161 u8 vport_cvlan_strip[0x1]; 4162 u8 vport_svlan_insert[0x1]; 4163 u8 vport_cvlan_insert[0x2]; 4164 u8 fdb_to_vport_reg_c_id[0x8]; 4165 u8 reserved_at_10[0x10]; 4166 4167 u8 reserved_at_20[0x20]; 4168 4169 u8 svlan_cfi[0x1]; 4170 u8 svlan_pcp[0x3]; 4171 u8 svlan_id[0xc]; 4172 u8 cvlan_cfi[0x1]; 4173 u8 cvlan_pcp[0x3]; 4174 u8 cvlan_id[0xc]; 4175 4176 u8 reserved_at_60[0x720]; 4177 4178 u8 sw_steering_vport_icm_address_rx[0x40]; 4179 4180 u8 sw_steering_vport_icm_address_tx[0x40]; 4181 }; 4182 4183 enum { 4184 MLX5_EQC_STATUS_OK = 0x0, 4185 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa, 4186 }; 4187 4188 enum { 4189 MLX5_EQC_ST_ARMED = 0x9, 4190 MLX5_EQC_ST_FIRED = 0xa, 4191 }; 4192 4193 struct mlx5_ifc_eqc_bits { 4194 u8 status[0x4]; 4195 u8 reserved_at_4[0x9]; 4196 u8 ec[0x1]; 4197 u8 oi[0x1]; 4198 u8 reserved_at_f[0x5]; 4199 u8 st[0x4]; 4200 u8 reserved_at_18[0x8]; 4201 4202 u8 reserved_at_20[0x20]; 4203 4204 u8 reserved_at_40[0x14]; 4205 u8 page_offset[0x6]; 4206 u8 reserved_at_5a[0x6]; 4207 4208 u8 reserved_at_60[0x3]; 4209 u8 log_eq_size[0x5]; 4210 u8 uar_page[0x18]; 4211 4212 u8 reserved_at_80[0x20]; 4213 4214 u8 reserved_at_a0[0x14]; 4215 u8 intr[0xc]; 4216 4217 u8 reserved_at_c0[0x3]; 4218 u8 log_page_size[0x5]; 4219 u8 reserved_at_c8[0x18]; 4220 4221 u8 reserved_at_e0[0x60]; 4222 4223 u8 reserved_at_140[0x8]; 4224 u8 consumer_counter[0x18]; 4225 4226 u8 reserved_at_160[0x8]; 4227 u8 producer_counter[0x18]; 4228 4229 u8 reserved_at_180[0x80]; 4230 }; 4231 4232 enum { 4233 MLX5_DCTC_STATE_ACTIVE = 0x0, 4234 MLX5_DCTC_STATE_DRAINING = 0x1, 4235 MLX5_DCTC_STATE_DRAINED = 0x2, 4236 }; 4237 4238 enum { 4239 MLX5_DCTC_CS_RES_DISABLE = 0x0, 4240 MLX5_DCTC_CS_RES_NA = 0x1, 4241 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2, 4242 }; 4243 4244 enum { 4245 MLX5_DCTC_MTU_256_BYTES = 0x1, 4246 MLX5_DCTC_MTU_512_BYTES = 0x2, 4247 MLX5_DCTC_MTU_1K_BYTES = 0x3, 4248 MLX5_DCTC_MTU_2K_BYTES = 0x4, 4249 MLX5_DCTC_MTU_4K_BYTES = 0x5, 4250 }; 4251 4252 struct mlx5_ifc_dctc_bits { 4253 u8 reserved_at_0[0x4]; 4254 u8 state[0x4]; 4255 u8 reserved_at_8[0x18]; 4256 4257 u8 reserved_at_20[0x8]; 4258 u8 user_index[0x18]; 4259 4260 u8 reserved_at_40[0x8]; 4261 u8 cqn[0x18]; 4262 4263 u8 counter_set_id[0x8]; 4264 u8 atomic_mode[0x4]; 4265 u8 rre[0x1]; 4266 u8 rwe[0x1]; 4267 u8 rae[0x1]; 4268 u8 atomic_like_write_en[0x1]; 4269 u8 latency_sensitive[0x1]; 4270 u8 rlky[0x1]; 4271 u8 free_ar[0x1]; 4272 u8 reserved_at_73[0xd]; 4273 4274 u8 reserved_at_80[0x8]; 4275 u8 cs_res[0x8]; 4276 u8 reserved_at_90[0x3]; 4277 u8 min_rnr_nak[0x5]; 4278 u8 reserved_at_98[0x8]; 4279 4280 u8 reserved_at_a0[0x8]; 4281 u8 srqn_xrqn[0x18]; 4282 4283 u8 reserved_at_c0[0x8]; 4284 u8 pd[0x18]; 4285 4286 u8 tclass[0x8]; 4287 u8 reserved_at_e8[0x4]; 4288 u8 flow_label[0x14]; 4289 4290 u8 dc_access_key[0x40]; 4291 4292 u8 reserved_at_140[0x5]; 4293 u8 mtu[0x3]; 4294 u8 port[0x8]; 4295 u8 pkey_index[0x10]; 4296 4297 u8 reserved_at_160[0x8]; 4298 u8 my_addr_index[0x8]; 4299 u8 reserved_at_170[0x8]; 4300 u8 hop_limit[0x8]; 4301 4302 u8 dc_access_key_violation_count[0x20]; 4303 4304 u8 reserved_at_1a0[0x14]; 4305 u8 dei_cfi[0x1]; 4306 u8 eth_prio[0x3]; 4307 u8 ecn[0x2]; 4308 u8 dscp[0x6]; 4309 4310 u8 reserved_at_1c0[0x20]; 4311 u8 ece[0x20]; 4312 }; 4313 4314 enum { 4315 MLX5_CQC_STATUS_OK = 0x0, 4316 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9, 4317 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa, 4318 }; 4319 4320 enum { 4321 MLX5_CQC_CQE_SZ_64_BYTES = 0x0, 4322 MLX5_CQC_CQE_SZ_128_BYTES = 0x1, 4323 }; 4324 4325 enum { 4326 MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED = 0x6, 4327 MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED = 0x9, 4328 MLX5_CQC_ST_FIRED = 0xa, 4329 }; 4330 4331 enum { 4332 MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0, 4333 MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1, 4334 MLX5_CQ_PERIOD_NUM_MODES 4335 }; 4336 4337 struct mlx5_ifc_cqc_bits { 4338 u8 status[0x4]; 4339 u8 reserved_at_4[0x2]; 4340 u8 dbr_umem_valid[0x1]; 4341 u8 apu_cq[0x1]; 4342 u8 cqe_sz[0x3]; 4343 u8 cc[0x1]; 4344 u8 reserved_at_c[0x1]; 4345 u8 scqe_break_moderation_en[0x1]; 4346 u8 oi[0x1]; 4347 u8 cq_period_mode[0x2]; 4348 u8 cqe_comp_en[0x1]; 4349 u8 mini_cqe_res_format[0x2]; 4350 u8 st[0x4]; 4351 u8 reserved_at_18[0x6]; 4352 u8 cqe_compression_layout[0x2]; 4353 4354 u8 reserved_at_20[0x20]; 4355 4356 u8 reserved_at_40[0x14]; 4357 u8 page_offset[0x6]; 4358 u8 reserved_at_5a[0x6]; 4359 4360 u8 reserved_at_60[0x3]; 4361 u8 log_cq_size[0x5]; 4362 u8 uar_page[0x18]; 4363 4364 u8 reserved_at_80[0x4]; 4365 u8 cq_period[0xc]; 4366 u8 cq_max_count[0x10]; 4367 4368 u8 c_eqn_or_apu_element[0x20]; 4369 4370 u8 reserved_at_c0[0x3]; 4371 u8 log_page_size[0x5]; 4372 u8 reserved_at_c8[0x18]; 4373 4374 u8 reserved_at_e0[0x20]; 4375 4376 u8 reserved_at_100[0x8]; 4377 u8 last_notified_index[0x18]; 4378 4379 u8 reserved_at_120[0x8]; 4380 u8 last_solicit_index[0x18]; 4381 4382 u8 reserved_at_140[0x8]; 4383 u8 consumer_counter[0x18]; 4384 4385 u8 reserved_at_160[0x8]; 4386 u8 producer_counter[0x18]; 4387 4388 u8 reserved_at_180[0x40]; 4389 4390 u8 dbr_addr[0x40]; 4391 }; 4392 4393 union mlx5_ifc_cong_control_roce_ecn_auto_bits { 4394 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp; 4395 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp; 4396 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np; 4397 struct mlx5_ifc_cong_control_r_roce_general_bits cong_control_r_roce_general; 4398 u8 reserved_at_0[0x800]; 4399 }; 4400 4401 struct mlx5_ifc_query_adapter_param_block_bits { 4402 u8 reserved_at_0[0xc0]; 4403 4404 u8 reserved_at_c0[0x8]; 4405 u8 ieee_vendor_id[0x18]; 4406 4407 u8 reserved_at_e0[0x10]; 4408 u8 vsd_vendor_id[0x10]; 4409 4410 u8 vsd[208][0x8]; 4411 4412 u8 vsd_contd_psid[16][0x8]; 4413 }; 4414 4415 enum { 4416 MLX5_XRQC_STATE_GOOD = 0x0, 4417 MLX5_XRQC_STATE_ERROR = 0x1, 4418 }; 4419 4420 enum { 4421 MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0, 4422 MLX5_XRQC_TOPOLOGY_TAG_MATCHING = 0x1, 4423 }; 4424 4425 enum { 4426 MLX5_XRQC_OFFLOAD_RNDV = 0x1, 4427 }; 4428 4429 struct mlx5_ifc_tag_matching_topology_context_bits { 4430 u8 log_matching_list_sz[0x4]; 4431 u8 reserved_at_4[0xc]; 4432 u8 append_next_index[0x10]; 4433 4434 u8 sw_phase_cnt[0x10]; 4435 u8 hw_phase_cnt[0x10]; 4436 4437 u8 reserved_at_40[0x40]; 4438 }; 4439 4440 struct mlx5_ifc_xrqc_bits { 4441 u8 state[0x4]; 4442 u8 rlkey[0x1]; 4443 u8 reserved_at_5[0xf]; 4444 u8 topology[0x4]; 4445 u8 reserved_at_18[0x4]; 4446 u8 offload[0x4]; 4447 4448 u8 reserved_at_20[0x8]; 4449 u8 user_index[0x18]; 4450 4451 u8 reserved_at_40[0x8]; 4452 u8 cqn[0x18]; 4453 4454 u8 reserved_at_60[0xa0]; 4455 4456 struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context; 4457 4458 u8 reserved_at_180[0x280]; 4459 4460 struct mlx5_ifc_wq_bits wq; 4461 }; 4462 4463 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits { 4464 struct mlx5_ifc_modify_field_select_bits modify_field_select; 4465 struct mlx5_ifc_resize_field_select_bits resize_field_select; 4466 u8 reserved_at_0[0x20]; 4467 }; 4468 4469 union mlx5_ifc_field_select_802_1_r_roce_auto_bits { 4470 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp; 4471 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp; 4472 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np; 4473 u8 reserved_at_0[0x20]; 4474 }; 4475 4476 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits { 4477 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 4478 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 4479 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 4480 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 4481 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 4482 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 4483 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout; 4484 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout; 4485 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 4486 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 4487 struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs; 4488 u8 reserved_at_0[0x7c0]; 4489 }; 4490 4491 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits { 4492 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout; 4493 u8 reserved_at_0[0x7c0]; 4494 }; 4495 4496 union mlx5_ifc_event_auto_bits { 4497 struct mlx5_ifc_comp_event_bits comp_event; 4498 struct mlx5_ifc_dct_events_bits dct_events; 4499 struct mlx5_ifc_qp_events_bits qp_events; 4500 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event; 4501 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event; 4502 struct mlx5_ifc_cq_error_bits cq_error; 4503 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged; 4504 struct mlx5_ifc_port_state_change_event_bits port_state_change_event; 4505 struct mlx5_ifc_gpio_event_bits gpio_event; 4506 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event; 4507 struct mlx5_ifc_stall_vl_event_bits stall_vl_event; 4508 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event; 4509 u8 reserved_at_0[0xe0]; 4510 }; 4511 4512 struct mlx5_ifc_health_buffer_bits { 4513 u8 reserved_at_0[0x100]; 4514 4515 u8 assert_existptr[0x20]; 4516 4517 u8 assert_callra[0x20]; 4518 4519 u8 reserved_at_140[0x20]; 4520 4521 u8 time[0x20]; 4522 4523 u8 fw_version[0x20]; 4524 4525 u8 hw_id[0x20]; 4526 4527 u8 rfr[0x1]; 4528 u8 reserved_at_1c1[0x3]; 4529 u8 valid[0x1]; 4530 u8 severity[0x3]; 4531 u8 reserved_at_1c8[0x18]; 4532 4533 u8 irisc_index[0x8]; 4534 u8 synd[0x8]; 4535 u8 ext_synd[0x10]; 4536 }; 4537 4538 struct mlx5_ifc_register_loopback_control_bits { 4539 u8 no_lb[0x1]; 4540 u8 reserved_at_1[0x7]; 4541 u8 port[0x8]; 4542 u8 reserved_at_10[0x10]; 4543 4544 u8 reserved_at_20[0x60]; 4545 }; 4546 4547 struct mlx5_ifc_vport_tc_element_bits { 4548 u8 traffic_class[0x4]; 4549 u8 reserved_at_4[0xc]; 4550 u8 vport_number[0x10]; 4551 }; 4552 4553 struct mlx5_ifc_vport_element_bits { 4554 u8 reserved_at_0[0x10]; 4555 u8 vport_number[0x10]; 4556 }; 4557 4558 enum { 4559 TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0, 4560 TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1, 4561 TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2, 4562 }; 4563 4564 struct mlx5_ifc_tsar_element_bits { 4565 u8 reserved_at_0[0x8]; 4566 u8 tsar_type[0x8]; 4567 u8 reserved_at_10[0x10]; 4568 }; 4569 4570 enum { 4571 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0, 4572 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1, 4573 }; 4574 4575 struct mlx5_ifc_teardown_hca_out_bits { 4576 u8 status[0x8]; 4577 u8 reserved_at_8[0x18]; 4578 4579 u8 syndrome[0x20]; 4580 4581 u8 reserved_at_40[0x3f]; 4582 4583 u8 state[0x1]; 4584 }; 4585 4586 enum { 4587 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0, 4588 MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE = 0x1, 4589 MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN = 0x2, 4590 }; 4591 4592 struct mlx5_ifc_teardown_hca_in_bits { 4593 u8 opcode[0x10]; 4594 u8 reserved_at_10[0x10]; 4595 4596 u8 reserved_at_20[0x10]; 4597 u8 op_mod[0x10]; 4598 4599 u8 reserved_at_40[0x10]; 4600 u8 profile[0x10]; 4601 4602 u8 reserved_at_60[0x20]; 4603 }; 4604 4605 struct mlx5_ifc_sqerr2rts_qp_out_bits { 4606 u8 status[0x8]; 4607 u8 reserved_at_8[0x18]; 4608 4609 u8 syndrome[0x20]; 4610 4611 u8 reserved_at_40[0x40]; 4612 }; 4613 4614 struct mlx5_ifc_sqerr2rts_qp_in_bits { 4615 u8 opcode[0x10]; 4616 u8 uid[0x10]; 4617 4618 u8 reserved_at_20[0x10]; 4619 u8 op_mod[0x10]; 4620 4621 u8 reserved_at_40[0x8]; 4622 u8 qpn[0x18]; 4623 4624 u8 reserved_at_60[0x20]; 4625 4626 u8 opt_param_mask[0x20]; 4627 4628 u8 reserved_at_a0[0x20]; 4629 4630 struct mlx5_ifc_qpc_bits qpc; 4631 4632 u8 reserved_at_800[0x80]; 4633 }; 4634 4635 struct mlx5_ifc_sqd2rts_qp_out_bits { 4636 u8 status[0x8]; 4637 u8 reserved_at_8[0x18]; 4638 4639 u8 syndrome[0x20]; 4640 4641 u8 reserved_at_40[0x40]; 4642 }; 4643 4644 struct mlx5_ifc_sqd2rts_qp_in_bits { 4645 u8 opcode[0x10]; 4646 u8 uid[0x10]; 4647 4648 u8 reserved_at_20[0x10]; 4649 u8 op_mod[0x10]; 4650 4651 u8 reserved_at_40[0x8]; 4652 u8 qpn[0x18]; 4653 4654 u8 reserved_at_60[0x20]; 4655 4656 u8 opt_param_mask[0x20]; 4657 4658 u8 reserved_at_a0[0x20]; 4659 4660 struct mlx5_ifc_qpc_bits qpc; 4661 4662 u8 reserved_at_800[0x80]; 4663 }; 4664 4665 struct mlx5_ifc_set_roce_address_out_bits { 4666 u8 status[0x8]; 4667 u8 reserved_at_8[0x18]; 4668 4669 u8 syndrome[0x20]; 4670 4671 u8 reserved_at_40[0x40]; 4672 }; 4673 4674 struct mlx5_ifc_set_roce_address_in_bits { 4675 u8 opcode[0x10]; 4676 u8 reserved_at_10[0x10]; 4677 4678 u8 reserved_at_20[0x10]; 4679 u8 op_mod[0x10]; 4680 4681 u8 roce_address_index[0x10]; 4682 u8 reserved_at_50[0xc]; 4683 u8 vhca_port_num[0x4]; 4684 4685 u8 reserved_at_60[0x20]; 4686 4687 struct mlx5_ifc_roce_addr_layout_bits roce_address; 4688 }; 4689 4690 struct mlx5_ifc_set_mad_demux_out_bits { 4691 u8 status[0x8]; 4692 u8 reserved_at_8[0x18]; 4693 4694 u8 syndrome[0x20]; 4695 4696 u8 reserved_at_40[0x40]; 4697 }; 4698 4699 enum { 4700 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0, 4701 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2, 4702 }; 4703 4704 struct mlx5_ifc_set_mad_demux_in_bits { 4705 u8 opcode[0x10]; 4706 u8 reserved_at_10[0x10]; 4707 4708 u8 reserved_at_20[0x10]; 4709 u8 op_mod[0x10]; 4710 4711 u8 reserved_at_40[0x20]; 4712 4713 u8 reserved_at_60[0x6]; 4714 u8 demux_mode[0x2]; 4715 u8 reserved_at_68[0x18]; 4716 }; 4717 4718 struct mlx5_ifc_set_l2_table_entry_out_bits { 4719 u8 status[0x8]; 4720 u8 reserved_at_8[0x18]; 4721 4722 u8 syndrome[0x20]; 4723 4724 u8 reserved_at_40[0x40]; 4725 }; 4726 4727 struct mlx5_ifc_set_l2_table_entry_in_bits { 4728 u8 opcode[0x10]; 4729 u8 reserved_at_10[0x10]; 4730 4731 u8 reserved_at_20[0x10]; 4732 u8 op_mod[0x10]; 4733 4734 u8 reserved_at_40[0x60]; 4735 4736 u8 reserved_at_a0[0x8]; 4737 u8 table_index[0x18]; 4738 4739 u8 reserved_at_c0[0x20]; 4740 4741 u8 reserved_at_e0[0x13]; 4742 u8 vlan_valid[0x1]; 4743 u8 vlan[0xc]; 4744 4745 struct mlx5_ifc_mac_address_layout_bits mac_address; 4746 4747 u8 reserved_at_140[0xc0]; 4748 }; 4749 4750 struct mlx5_ifc_set_issi_out_bits { 4751 u8 status[0x8]; 4752 u8 reserved_at_8[0x18]; 4753 4754 u8 syndrome[0x20]; 4755 4756 u8 reserved_at_40[0x40]; 4757 }; 4758 4759 struct mlx5_ifc_set_issi_in_bits { 4760 u8 opcode[0x10]; 4761 u8 reserved_at_10[0x10]; 4762 4763 u8 reserved_at_20[0x10]; 4764 u8 op_mod[0x10]; 4765 4766 u8 reserved_at_40[0x10]; 4767 u8 current_issi[0x10]; 4768 4769 u8 reserved_at_60[0x20]; 4770 }; 4771 4772 struct mlx5_ifc_set_hca_cap_out_bits { 4773 u8 status[0x8]; 4774 u8 reserved_at_8[0x18]; 4775 4776 u8 syndrome[0x20]; 4777 4778 u8 reserved_at_40[0x40]; 4779 }; 4780 4781 struct mlx5_ifc_set_hca_cap_in_bits { 4782 u8 opcode[0x10]; 4783 u8 reserved_at_10[0x10]; 4784 4785 u8 reserved_at_20[0x10]; 4786 u8 op_mod[0x10]; 4787 4788 u8 other_function[0x1]; 4789 u8 ec_vf_function[0x1]; 4790 u8 reserved_at_42[0xe]; 4791 u8 function_id[0x10]; 4792 4793 u8 reserved_at_60[0x20]; 4794 4795 union mlx5_ifc_hca_cap_union_bits capability; 4796 }; 4797 4798 enum { 4799 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0, 4800 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1, 4801 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2, 4802 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3, 4803 MLX5_SET_FTE_MODIFY_ENABLE_MASK_IPSEC_OBJ_ID = 0x4 4804 }; 4805 4806 struct mlx5_ifc_set_fte_out_bits { 4807 u8 status[0x8]; 4808 u8 reserved_at_8[0x18]; 4809 4810 u8 syndrome[0x20]; 4811 4812 u8 reserved_at_40[0x40]; 4813 }; 4814 4815 struct mlx5_ifc_set_fte_in_bits { 4816 u8 opcode[0x10]; 4817 u8 reserved_at_10[0x10]; 4818 4819 u8 reserved_at_20[0x10]; 4820 u8 op_mod[0x10]; 4821 4822 u8 other_vport[0x1]; 4823 u8 reserved_at_41[0xf]; 4824 u8 vport_number[0x10]; 4825 4826 u8 reserved_at_60[0x20]; 4827 4828 u8 table_type[0x8]; 4829 u8 reserved_at_88[0x18]; 4830 4831 u8 reserved_at_a0[0x8]; 4832 u8 table_id[0x18]; 4833 4834 u8 ignore_flow_level[0x1]; 4835 u8 reserved_at_c1[0x17]; 4836 u8 modify_enable_mask[0x8]; 4837 4838 u8 reserved_at_e0[0x20]; 4839 4840 u8 flow_index[0x20]; 4841 4842 u8 reserved_at_120[0xe0]; 4843 4844 struct mlx5_ifc_flow_context_bits flow_context; 4845 }; 4846 4847 struct mlx5_ifc_rts2rts_qp_out_bits { 4848 u8 status[0x8]; 4849 u8 reserved_at_8[0x18]; 4850 4851 u8 syndrome[0x20]; 4852 4853 u8 reserved_at_40[0x20]; 4854 u8 ece[0x20]; 4855 }; 4856 4857 struct mlx5_ifc_rts2rts_qp_in_bits { 4858 u8 opcode[0x10]; 4859 u8 uid[0x10]; 4860 4861 u8 reserved_at_20[0x10]; 4862 u8 op_mod[0x10]; 4863 4864 u8 reserved_at_40[0x8]; 4865 u8 qpn[0x18]; 4866 4867 u8 reserved_at_60[0x20]; 4868 4869 u8 opt_param_mask[0x20]; 4870 4871 u8 ece[0x20]; 4872 4873 struct mlx5_ifc_qpc_bits qpc; 4874 4875 u8 reserved_at_800[0x80]; 4876 }; 4877 4878 struct mlx5_ifc_rtr2rts_qp_out_bits { 4879 u8 status[0x8]; 4880 u8 reserved_at_8[0x18]; 4881 4882 u8 syndrome[0x20]; 4883 4884 u8 reserved_at_40[0x20]; 4885 u8 ece[0x20]; 4886 }; 4887 4888 struct mlx5_ifc_rtr2rts_qp_in_bits { 4889 u8 opcode[0x10]; 4890 u8 uid[0x10]; 4891 4892 u8 reserved_at_20[0x10]; 4893 u8 op_mod[0x10]; 4894 4895 u8 reserved_at_40[0x8]; 4896 u8 qpn[0x18]; 4897 4898 u8 reserved_at_60[0x20]; 4899 4900 u8 opt_param_mask[0x20]; 4901 4902 u8 ece[0x20]; 4903 4904 struct mlx5_ifc_qpc_bits qpc; 4905 4906 u8 reserved_at_800[0x80]; 4907 }; 4908 4909 struct mlx5_ifc_rst2init_qp_out_bits { 4910 u8 status[0x8]; 4911 u8 reserved_at_8[0x18]; 4912 4913 u8 syndrome[0x20]; 4914 4915 u8 reserved_at_40[0x20]; 4916 u8 ece[0x20]; 4917 }; 4918 4919 struct mlx5_ifc_rst2init_qp_in_bits { 4920 u8 opcode[0x10]; 4921 u8 uid[0x10]; 4922 4923 u8 reserved_at_20[0x10]; 4924 u8 op_mod[0x10]; 4925 4926 u8 reserved_at_40[0x8]; 4927 u8 qpn[0x18]; 4928 4929 u8 reserved_at_60[0x20]; 4930 4931 u8 opt_param_mask[0x20]; 4932 4933 u8 ece[0x20]; 4934 4935 struct mlx5_ifc_qpc_bits qpc; 4936 4937 u8 reserved_at_800[0x80]; 4938 }; 4939 4940 struct mlx5_ifc_query_xrq_out_bits { 4941 u8 status[0x8]; 4942 u8 reserved_at_8[0x18]; 4943 4944 u8 syndrome[0x20]; 4945 4946 u8 reserved_at_40[0x40]; 4947 4948 struct mlx5_ifc_xrqc_bits xrq_context; 4949 }; 4950 4951 struct mlx5_ifc_query_xrq_in_bits { 4952 u8 opcode[0x10]; 4953 u8 reserved_at_10[0x10]; 4954 4955 u8 reserved_at_20[0x10]; 4956 u8 op_mod[0x10]; 4957 4958 u8 reserved_at_40[0x8]; 4959 u8 xrqn[0x18]; 4960 4961 u8 reserved_at_60[0x20]; 4962 }; 4963 4964 struct mlx5_ifc_query_xrc_srq_out_bits { 4965 u8 status[0x8]; 4966 u8 reserved_at_8[0x18]; 4967 4968 u8 syndrome[0x20]; 4969 4970 u8 reserved_at_40[0x40]; 4971 4972 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 4973 4974 u8 reserved_at_280[0x600]; 4975 4976 u8 pas[][0x40]; 4977 }; 4978 4979 struct mlx5_ifc_query_xrc_srq_in_bits { 4980 u8 opcode[0x10]; 4981 u8 reserved_at_10[0x10]; 4982 4983 u8 reserved_at_20[0x10]; 4984 u8 op_mod[0x10]; 4985 4986 u8 reserved_at_40[0x8]; 4987 u8 xrc_srqn[0x18]; 4988 4989 u8 reserved_at_60[0x20]; 4990 }; 4991 4992 enum { 4993 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0, 4994 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1, 4995 }; 4996 4997 struct mlx5_ifc_query_vport_state_out_bits { 4998 u8 status[0x8]; 4999 u8 reserved_at_8[0x18]; 5000 5001 u8 syndrome[0x20]; 5002 5003 u8 reserved_at_40[0x20]; 5004 5005 u8 reserved_at_60[0x18]; 5006 u8 admin_state[0x4]; 5007 u8 state[0x4]; 5008 }; 5009 5010 enum { 5011 MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT = 0x0, 5012 MLX5_VPORT_STATE_OP_MOD_ESW_VPORT = 0x1, 5013 MLX5_VPORT_STATE_OP_MOD_UPLINK = 0x2, 5014 }; 5015 5016 struct mlx5_ifc_arm_monitor_counter_in_bits { 5017 u8 opcode[0x10]; 5018 u8 uid[0x10]; 5019 5020 u8 reserved_at_20[0x10]; 5021 u8 op_mod[0x10]; 5022 5023 u8 reserved_at_40[0x20]; 5024 5025 u8 reserved_at_60[0x20]; 5026 }; 5027 5028 struct mlx5_ifc_arm_monitor_counter_out_bits { 5029 u8 status[0x8]; 5030 u8 reserved_at_8[0x18]; 5031 5032 u8 syndrome[0x20]; 5033 5034 u8 reserved_at_40[0x40]; 5035 }; 5036 5037 enum { 5038 MLX5_QUERY_MONITOR_CNT_TYPE_PPCNT = 0x0, 5039 MLX5_QUERY_MONITOR_CNT_TYPE_Q_COUNTER = 0x1, 5040 }; 5041 5042 enum mlx5_monitor_counter_ppcnt { 5043 MLX5_QUERY_MONITOR_PPCNT_IN_RANGE_LENGTH_ERRORS = 0x0, 5044 MLX5_QUERY_MONITOR_PPCNT_OUT_OF_RANGE_LENGTH_FIELD = 0x1, 5045 MLX5_QUERY_MONITOR_PPCNT_FRAME_TOO_LONG_ERRORS = 0x2, 5046 MLX5_QUERY_MONITOR_PPCNT_FRAME_CHECK_SEQUENCE_ERRORS = 0x3, 5047 MLX5_QUERY_MONITOR_PPCNT_ALIGNMENT_ERRORS = 0x4, 5048 MLX5_QUERY_MONITOR_PPCNT_IF_OUT_DISCARDS = 0x5, 5049 }; 5050 5051 enum { 5052 MLX5_QUERY_MONITOR_Q_COUNTER_RX_OUT_OF_BUFFER = 0x4, 5053 }; 5054 5055 struct mlx5_ifc_monitor_counter_output_bits { 5056 u8 reserved_at_0[0x4]; 5057 u8 type[0x4]; 5058 u8 reserved_at_8[0x8]; 5059 u8 counter[0x10]; 5060 5061 u8 counter_group_id[0x20]; 5062 }; 5063 5064 #define MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 (6) 5065 #define MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1 (1) 5066 #define MLX5_CMD_SET_MONITOR_NUM_COUNTER (MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 +\ 5067 MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1) 5068 5069 struct mlx5_ifc_set_monitor_counter_in_bits { 5070 u8 opcode[0x10]; 5071 u8 uid[0x10]; 5072 5073 u8 reserved_at_20[0x10]; 5074 u8 op_mod[0x10]; 5075 5076 u8 reserved_at_40[0x10]; 5077 u8 num_of_counters[0x10]; 5078 5079 u8 reserved_at_60[0x20]; 5080 5081 struct mlx5_ifc_monitor_counter_output_bits monitor_counter[MLX5_CMD_SET_MONITOR_NUM_COUNTER]; 5082 }; 5083 5084 struct mlx5_ifc_set_monitor_counter_out_bits { 5085 u8 status[0x8]; 5086 u8 reserved_at_8[0x18]; 5087 5088 u8 syndrome[0x20]; 5089 5090 u8 reserved_at_40[0x40]; 5091 }; 5092 5093 struct mlx5_ifc_query_vport_state_in_bits { 5094 u8 opcode[0x10]; 5095 u8 reserved_at_10[0x10]; 5096 5097 u8 reserved_at_20[0x10]; 5098 u8 op_mod[0x10]; 5099 5100 u8 other_vport[0x1]; 5101 u8 reserved_at_41[0xf]; 5102 u8 vport_number[0x10]; 5103 5104 u8 reserved_at_60[0x20]; 5105 }; 5106 5107 struct mlx5_ifc_query_vnic_env_out_bits { 5108 u8 status[0x8]; 5109 u8 reserved_at_8[0x18]; 5110 5111 u8 syndrome[0x20]; 5112 5113 u8 reserved_at_40[0x40]; 5114 5115 struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env; 5116 }; 5117 5118 enum { 5119 MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS = 0x0, 5120 }; 5121 5122 struct mlx5_ifc_query_vnic_env_in_bits { 5123 u8 opcode[0x10]; 5124 u8 reserved_at_10[0x10]; 5125 5126 u8 reserved_at_20[0x10]; 5127 u8 op_mod[0x10]; 5128 5129 u8 other_vport[0x1]; 5130 u8 reserved_at_41[0xf]; 5131 u8 vport_number[0x10]; 5132 5133 u8 reserved_at_60[0x20]; 5134 }; 5135 5136 struct mlx5_ifc_query_vport_counter_out_bits { 5137 u8 status[0x8]; 5138 u8 reserved_at_8[0x18]; 5139 5140 u8 syndrome[0x20]; 5141 5142 u8 reserved_at_40[0x40]; 5143 5144 struct mlx5_ifc_traffic_counter_bits received_errors; 5145 5146 struct mlx5_ifc_traffic_counter_bits transmit_errors; 5147 5148 struct mlx5_ifc_traffic_counter_bits received_ib_unicast; 5149 5150 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast; 5151 5152 struct mlx5_ifc_traffic_counter_bits received_ib_multicast; 5153 5154 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast; 5155 5156 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast; 5157 5158 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast; 5159 5160 struct mlx5_ifc_traffic_counter_bits received_eth_unicast; 5161 5162 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast; 5163 5164 struct mlx5_ifc_traffic_counter_bits received_eth_multicast; 5165 5166 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast; 5167 5168 struct mlx5_ifc_traffic_counter_bits local_loopback; 5169 5170 u8 reserved_at_700[0x980]; 5171 }; 5172 5173 enum { 5174 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0, 5175 }; 5176 5177 struct mlx5_ifc_query_vport_counter_in_bits { 5178 u8 opcode[0x10]; 5179 u8 reserved_at_10[0x10]; 5180 5181 u8 reserved_at_20[0x10]; 5182 u8 op_mod[0x10]; 5183 5184 u8 other_vport[0x1]; 5185 u8 reserved_at_41[0xb]; 5186 u8 port_num[0x4]; 5187 u8 vport_number[0x10]; 5188 5189 u8 reserved_at_60[0x60]; 5190 5191 u8 clear[0x1]; 5192 u8 reserved_at_c1[0x1f]; 5193 5194 u8 reserved_at_e0[0x20]; 5195 }; 5196 5197 struct mlx5_ifc_query_tis_out_bits { 5198 u8 status[0x8]; 5199 u8 reserved_at_8[0x18]; 5200 5201 u8 syndrome[0x20]; 5202 5203 u8 reserved_at_40[0x40]; 5204 5205 struct mlx5_ifc_tisc_bits tis_context; 5206 }; 5207 5208 struct mlx5_ifc_query_tis_in_bits { 5209 u8 opcode[0x10]; 5210 u8 reserved_at_10[0x10]; 5211 5212 u8 reserved_at_20[0x10]; 5213 u8 op_mod[0x10]; 5214 5215 u8 reserved_at_40[0x8]; 5216 u8 tisn[0x18]; 5217 5218 u8 reserved_at_60[0x20]; 5219 }; 5220 5221 struct mlx5_ifc_query_tir_out_bits { 5222 u8 status[0x8]; 5223 u8 reserved_at_8[0x18]; 5224 5225 u8 syndrome[0x20]; 5226 5227 u8 reserved_at_40[0xc0]; 5228 5229 struct mlx5_ifc_tirc_bits tir_context; 5230 }; 5231 5232 struct mlx5_ifc_query_tir_in_bits { 5233 u8 opcode[0x10]; 5234 u8 reserved_at_10[0x10]; 5235 5236 u8 reserved_at_20[0x10]; 5237 u8 op_mod[0x10]; 5238 5239 u8 reserved_at_40[0x8]; 5240 u8 tirn[0x18]; 5241 5242 u8 reserved_at_60[0x20]; 5243 }; 5244 5245 struct mlx5_ifc_query_srq_out_bits { 5246 u8 status[0x8]; 5247 u8 reserved_at_8[0x18]; 5248 5249 u8 syndrome[0x20]; 5250 5251 u8 reserved_at_40[0x40]; 5252 5253 struct mlx5_ifc_srqc_bits srq_context_entry; 5254 5255 u8 reserved_at_280[0x600]; 5256 5257 u8 pas[][0x40]; 5258 }; 5259 5260 struct mlx5_ifc_query_srq_in_bits { 5261 u8 opcode[0x10]; 5262 u8 reserved_at_10[0x10]; 5263 5264 u8 reserved_at_20[0x10]; 5265 u8 op_mod[0x10]; 5266 5267 u8 reserved_at_40[0x8]; 5268 u8 srqn[0x18]; 5269 5270 u8 reserved_at_60[0x20]; 5271 }; 5272 5273 struct mlx5_ifc_query_sq_out_bits { 5274 u8 status[0x8]; 5275 u8 reserved_at_8[0x18]; 5276 5277 u8 syndrome[0x20]; 5278 5279 u8 reserved_at_40[0xc0]; 5280 5281 struct mlx5_ifc_sqc_bits sq_context; 5282 }; 5283 5284 struct mlx5_ifc_query_sq_in_bits { 5285 u8 opcode[0x10]; 5286 u8 reserved_at_10[0x10]; 5287 5288 u8 reserved_at_20[0x10]; 5289 u8 op_mod[0x10]; 5290 5291 u8 reserved_at_40[0x8]; 5292 u8 sqn[0x18]; 5293 5294 u8 reserved_at_60[0x20]; 5295 }; 5296 5297 struct mlx5_ifc_query_special_contexts_out_bits { 5298 u8 status[0x8]; 5299 u8 reserved_at_8[0x18]; 5300 5301 u8 syndrome[0x20]; 5302 5303 u8 dump_fill_mkey[0x20]; 5304 5305 u8 resd_lkey[0x20]; 5306 5307 u8 null_mkey[0x20]; 5308 5309 u8 terminate_scatter_list_mkey[0x20]; 5310 5311 u8 repeated_mkey[0x20]; 5312 5313 u8 reserved_at_a0[0x20]; 5314 }; 5315 5316 struct mlx5_ifc_query_special_contexts_in_bits { 5317 u8 opcode[0x10]; 5318 u8 reserved_at_10[0x10]; 5319 5320 u8 reserved_at_20[0x10]; 5321 u8 op_mod[0x10]; 5322 5323 u8 reserved_at_40[0x40]; 5324 }; 5325 5326 struct mlx5_ifc_query_scheduling_element_out_bits { 5327 u8 opcode[0x10]; 5328 u8 reserved_at_10[0x10]; 5329 5330 u8 reserved_at_20[0x10]; 5331 u8 op_mod[0x10]; 5332 5333 u8 reserved_at_40[0xc0]; 5334 5335 struct mlx5_ifc_scheduling_context_bits scheduling_context; 5336 5337 u8 reserved_at_300[0x100]; 5338 }; 5339 5340 enum { 5341 SCHEDULING_HIERARCHY_E_SWITCH = 0x2, 5342 SCHEDULING_HIERARCHY_NIC = 0x3, 5343 }; 5344 5345 struct mlx5_ifc_query_scheduling_element_in_bits { 5346 u8 opcode[0x10]; 5347 u8 reserved_at_10[0x10]; 5348 5349 u8 reserved_at_20[0x10]; 5350 u8 op_mod[0x10]; 5351 5352 u8 scheduling_hierarchy[0x8]; 5353 u8 reserved_at_48[0x18]; 5354 5355 u8 scheduling_element_id[0x20]; 5356 5357 u8 reserved_at_80[0x180]; 5358 }; 5359 5360 struct mlx5_ifc_query_rqt_out_bits { 5361 u8 status[0x8]; 5362 u8 reserved_at_8[0x18]; 5363 5364 u8 syndrome[0x20]; 5365 5366 u8 reserved_at_40[0xc0]; 5367 5368 struct mlx5_ifc_rqtc_bits rqt_context; 5369 }; 5370 5371 struct mlx5_ifc_query_rqt_in_bits { 5372 u8 opcode[0x10]; 5373 u8 reserved_at_10[0x10]; 5374 5375 u8 reserved_at_20[0x10]; 5376 u8 op_mod[0x10]; 5377 5378 u8 reserved_at_40[0x8]; 5379 u8 rqtn[0x18]; 5380 5381 u8 reserved_at_60[0x20]; 5382 }; 5383 5384 struct mlx5_ifc_query_rq_out_bits { 5385 u8 status[0x8]; 5386 u8 reserved_at_8[0x18]; 5387 5388 u8 syndrome[0x20]; 5389 5390 u8 reserved_at_40[0xc0]; 5391 5392 struct mlx5_ifc_rqc_bits rq_context; 5393 }; 5394 5395 struct mlx5_ifc_query_rq_in_bits { 5396 u8 opcode[0x10]; 5397 u8 reserved_at_10[0x10]; 5398 5399 u8 reserved_at_20[0x10]; 5400 u8 op_mod[0x10]; 5401 5402 u8 reserved_at_40[0x8]; 5403 u8 rqn[0x18]; 5404 5405 u8 reserved_at_60[0x20]; 5406 }; 5407 5408 struct mlx5_ifc_query_roce_address_out_bits { 5409 u8 status[0x8]; 5410 u8 reserved_at_8[0x18]; 5411 5412 u8 syndrome[0x20]; 5413 5414 u8 reserved_at_40[0x40]; 5415 5416 struct mlx5_ifc_roce_addr_layout_bits roce_address; 5417 }; 5418 5419 struct mlx5_ifc_query_roce_address_in_bits { 5420 u8 opcode[0x10]; 5421 u8 reserved_at_10[0x10]; 5422 5423 u8 reserved_at_20[0x10]; 5424 u8 op_mod[0x10]; 5425 5426 u8 roce_address_index[0x10]; 5427 u8 reserved_at_50[0xc]; 5428 u8 vhca_port_num[0x4]; 5429 5430 u8 reserved_at_60[0x20]; 5431 }; 5432 5433 struct mlx5_ifc_query_rmp_out_bits { 5434 u8 status[0x8]; 5435 u8 reserved_at_8[0x18]; 5436 5437 u8 syndrome[0x20]; 5438 5439 u8 reserved_at_40[0xc0]; 5440 5441 struct mlx5_ifc_rmpc_bits rmp_context; 5442 }; 5443 5444 struct mlx5_ifc_query_rmp_in_bits { 5445 u8 opcode[0x10]; 5446 u8 reserved_at_10[0x10]; 5447 5448 u8 reserved_at_20[0x10]; 5449 u8 op_mod[0x10]; 5450 5451 u8 reserved_at_40[0x8]; 5452 u8 rmpn[0x18]; 5453 5454 u8 reserved_at_60[0x20]; 5455 }; 5456 5457 struct mlx5_ifc_cqe_error_syndrome_bits { 5458 u8 hw_error_syndrome[0x8]; 5459 u8 hw_syndrome_type[0x4]; 5460 u8 reserved_at_c[0x4]; 5461 u8 vendor_error_syndrome[0x8]; 5462 u8 syndrome[0x8]; 5463 }; 5464 5465 struct mlx5_ifc_qp_context_extension_bits { 5466 u8 reserved_at_0[0x60]; 5467 5468 struct mlx5_ifc_cqe_error_syndrome_bits error_syndrome; 5469 5470 u8 reserved_at_80[0x580]; 5471 }; 5472 5473 struct mlx5_ifc_qpc_extension_and_pas_list_in_bits { 5474 struct mlx5_ifc_qp_context_extension_bits qpc_data_extension; 5475 5476 u8 pas[0][0x40]; 5477 }; 5478 5479 struct mlx5_ifc_qp_pas_list_in_bits { 5480 struct mlx5_ifc_cmd_pas_bits pas[0]; 5481 }; 5482 5483 union mlx5_ifc_qp_pas_or_qpc_ext_and_pas_bits { 5484 struct mlx5_ifc_qp_pas_list_in_bits qp_pas_list; 5485 struct mlx5_ifc_qpc_extension_and_pas_list_in_bits qpc_ext_and_pas_list; 5486 }; 5487 5488 struct mlx5_ifc_query_qp_out_bits { 5489 u8 status[0x8]; 5490 u8 reserved_at_8[0x18]; 5491 5492 u8 syndrome[0x20]; 5493 5494 u8 reserved_at_40[0x40]; 5495 5496 u8 opt_param_mask[0x20]; 5497 5498 u8 ece[0x20]; 5499 5500 struct mlx5_ifc_qpc_bits qpc; 5501 5502 u8 reserved_at_800[0x80]; 5503 5504 union mlx5_ifc_qp_pas_or_qpc_ext_and_pas_bits qp_pas_or_qpc_ext_and_pas; 5505 }; 5506 5507 struct mlx5_ifc_query_qp_in_bits { 5508 u8 opcode[0x10]; 5509 u8 reserved_at_10[0x10]; 5510 5511 u8 reserved_at_20[0x10]; 5512 u8 op_mod[0x10]; 5513 5514 u8 qpc_ext[0x1]; 5515 u8 reserved_at_41[0x7]; 5516 u8 qpn[0x18]; 5517 5518 u8 reserved_at_60[0x20]; 5519 }; 5520 5521 struct mlx5_ifc_query_q_counter_out_bits { 5522 u8 status[0x8]; 5523 u8 reserved_at_8[0x18]; 5524 5525 u8 syndrome[0x20]; 5526 5527 u8 reserved_at_40[0x40]; 5528 5529 u8 rx_write_requests[0x20]; 5530 5531 u8 reserved_at_a0[0x20]; 5532 5533 u8 rx_read_requests[0x20]; 5534 5535 u8 reserved_at_e0[0x20]; 5536 5537 u8 rx_atomic_requests[0x20]; 5538 5539 u8 reserved_at_120[0x20]; 5540 5541 u8 rx_dct_connect[0x20]; 5542 5543 u8 reserved_at_160[0x20]; 5544 5545 u8 out_of_buffer[0x20]; 5546 5547 u8 reserved_at_1a0[0x20]; 5548 5549 u8 out_of_sequence[0x20]; 5550 5551 u8 reserved_at_1e0[0x20]; 5552 5553 u8 duplicate_request[0x20]; 5554 5555 u8 reserved_at_220[0x20]; 5556 5557 u8 rnr_nak_retry_err[0x20]; 5558 5559 u8 reserved_at_260[0x20]; 5560 5561 u8 packet_seq_err[0x20]; 5562 5563 u8 reserved_at_2a0[0x20]; 5564 5565 u8 implied_nak_seq_err[0x20]; 5566 5567 u8 reserved_at_2e0[0x20]; 5568 5569 u8 local_ack_timeout_err[0x20]; 5570 5571 u8 reserved_at_320[0xa0]; 5572 5573 u8 resp_local_length_error[0x20]; 5574 5575 u8 req_local_length_error[0x20]; 5576 5577 u8 resp_local_qp_error[0x20]; 5578 5579 u8 local_operation_error[0x20]; 5580 5581 u8 resp_local_protection[0x20]; 5582 5583 u8 req_local_protection[0x20]; 5584 5585 u8 resp_cqe_error[0x20]; 5586 5587 u8 req_cqe_error[0x20]; 5588 5589 u8 req_mw_binding[0x20]; 5590 5591 u8 req_bad_response[0x20]; 5592 5593 u8 req_remote_invalid_request[0x20]; 5594 5595 u8 resp_remote_invalid_request[0x20]; 5596 5597 u8 req_remote_access_errors[0x20]; 5598 5599 u8 resp_remote_access_errors[0x20]; 5600 5601 u8 req_remote_operation_errors[0x20]; 5602 5603 u8 req_transport_retries_exceeded[0x20]; 5604 5605 u8 cq_overflow[0x20]; 5606 5607 u8 resp_cqe_flush_error[0x20]; 5608 5609 u8 req_cqe_flush_error[0x20]; 5610 5611 u8 reserved_at_620[0x20]; 5612 5613 u8 roce_adp_retrans[0x20]; 5614 5615 u8 roce_adp_retrans_to[0x20]; 5616 5617 u8 roce_slow_restart[0x20]; 5618 5619 u8 roce_slow_restart_cnps[0x20]; 5620 5621 u8 roce_slow_restart_trans[0x20]; 5622 5623 u8 reserved_at_6e0[0x120]; 5624 }; 5625 5626 struct mlx5_ifc_query_q_counter_in_bits { 5627 u8 opcode[0x10]; 5628 u8 reserved_at_10[0x10]; 5629 5630 u8 reserved_at_20[0x10]; 5631 u8 op_mod[0x10]; 5632 5633 u8 other_vport[0x1]; 5634 u8 reserved_at_41[0xf]; 5635 u8 vport_number[0x10]; 5636 5637 u8 reserved_at_60[0x60]; 5638 5639 u8 clear[0x1]; 5640 u8 aggregate[0x1]; 5641 u8 reserved_at_c2[0x1e]; 5642 5643 u8 reserved_at_e0[0x18]; 5644 u8 counter_set_id[0x8]; 5645 }; 5646 5647 struct mlx5_ifc_query_pages_out_bits { 5648 u8 status[0x8]; 5649 u8 reserved_at_8[0x18]; 5650 5651 u8 syndrome[0x20]; 5652 5653 u8 embedded_cpu_function[0x1]; 5654 u8 reserved_at_41[0xf]; 5655 u8 function_id[0x10]; 5656 5657 u8 num_pages[0x20]; 5658 }; 5659 5660 enum { 5661 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1, 5662 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2, 5663 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3, 5664 }; 5665 5666 struct mlx5_ifc_query_pages_in_bits { 5667 u8 opcode[0x10]; 5668 u8 reserved_at_10[0x10]; 5669 5670 u8 reserved_at_20[0x10]; 5671 u8 op_mod[0x10]; 5672 5673 u8 embedded_cpu_function[0x1]; 5674 u8 reserved_at_41[0xf]; 5675 u8 function_id[0x10]; 5676 5677 u8 reserved_at_60[0x20]; 5678 }; 5679 5680 struct mlx5_ifc_query_nic_vport_context_out_bits { 5681 u8 status[0x8]; 5682 u8 reserved_at_8[0x18]; 5683 5684 u8 syndrome[0x20]; 5685 5686 u8 reserved_at_40[0x40]; 5687 5688 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 5689 }; 5690 5691 struct mlx5_ifc_query_nic_vport_context_in_bits { 5692 u8 opcode[0x10]; 5693 u8 reserved_at_10[0x10]; 5694 5695 u8 reserved_at_20[0x10]; 5696 u8 op_mod[0x10]; 5697 5698 u8 other_vport[0x1]; 5699 u8 reserved_at_41[0xf]; 5700 u8 vport_number[0x10]; 5701 5702 u8 reserved_at_60[0x5]; 5703 u8 allowed_list_type[0x3]; 5704 u8 reserved_at_68[0x18]; 5705 }; 5706 5707 struct mlx5_ifc_query_mkey_out_bits { 5708 u8 status[0x8]; 5709 u8 reserved_at_8[0x18]; 5710 5711 u8 syndrome[0x20]; 5712 5713 u8 reserved_at_40[0x40]; 5714 5715 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 5716 5717 u8 reserved_at_280[0x600]; 5718 5719 u8 bsf0_klm0_pas_mtt0_1[16][0x8]; 5720 5721 u8 bsf1_klm1_pas_mtt2_3[16][0x8]; 5722 }; 5723 5724 struct mlx5_ifc_query_mkey_in_bits { 5725 u8 opcode[0x10]; 5726 u8 reserved_at_10[0x10]; 5727 5728 u8 reserved_at_20[0x10]; 5729 u8 op_mod[0x10]; 5730 5731 u8 reserved_at_40[0x8]; 5732 u8 mkey_index[0x18]; 5733 5734 u8 pg_access[0x1]; 5735 u8 reserved_at_61[0x1f]; 5736 }; 5737 5738 struct mlx5_ifc_query_mad_demux_out_bits { 5739 u8 status[0x8]; 5740 u8 reserved_at_8[0x18]; 5741 5742 u8 syndrome[0x20]; 5743 5744 u8 reserved_at_40[0x40]; 5745 5746 u8 mad_dumux_parameters_block[0x20]; 5747 }; 5748 5749 struct mlx5_ifc_query_mad_demux_in_bits { 5750 u8 opcode[0x10]; 5751 u8 reserved_at_10[0x10]; 5752 5753 u8 reserved_at_20[0x10]; 5754 u8 op_mod[0x10]; 5755 5756 u8 reserved_at_40[0x40]; 5757 }; 5758 5759 struct mlx5_ifc_query_l2_table_entry_out_bits { 5760 u8 status[0x8]; 5761 u8 reserved_at_8[0x18]; 5762 5763 u8 syndrome[0x20]; 5764 5765 u8 reserved_at_40[0xa0]; 5766 5767 u8 reserved_at_e0[0x13]; 5768 u8 vlan_valid[0x1]; 5769 u8 vlan[0xc]; 5770 5771 struct mlx5_ifc_mac_address_layout_bits mac_address; 5772 5773 u8 reserved_at_140[0xc0]; 5774 }; 5775 5776 struct mlx5_ifc_query_l2_table_entry_in_bits { 5777 u8 opcode[0x10]; 5778 u8 reserved_at_10[0x10]; 5779 5780 u8 reserved_at_20[0x10]; 5781 u8 op_mod[0x10]; 5782 5783 u8 reserved_at_40[0x60]; 5784 5785 u8 reserved_at_a0[0x8]; 5786 u8 table_index[0x18]; 5787 5788 u8 reserved_at_c0[0x140]; 5789 }; 5790 5791 struct mlx5_ifc_query_issi_out_bits { 5792 u8 status[0x8]; 5793 u8 reserved_at_8[0x18]; 5794 5795 u8 syndrome[0x20]; 5796 5797 u8 reserved_at_40[0x10]; 5798 u8 current_issi[0x10]; 5799 5800 u8 reserved_at_60[0xa0]; 5801 5802 u8 reserved_at_100[76][0x8]; 5803 u8 supported_issi_dw0[0x20]; 5804 }; 5805 5806 struct mlx5_ifc_query_issi_in_bits { 5807 u8 opcode[0x10]; 5808 u8 reserved_at_10[0x10]; 5809 5810 u8 reserved_at_20[0x10]; 5811 u8 op_mod[0x10]; 5812 5813 u8 reserved_at_40[0x40]; 5814 }; 5815 5816 struct mlx5_ifc_set_driver_version_out_bits { 5817 u8 status[0x8]; 5818 u8 reserved_0[0x18]; 5819 5820 u8 syndrome[0x20]; 5821 u8 reserved_1[0x40]; 5822 }; 5823 5824 struct mlx5_ifc_set_driver_version_in_bits { 5825 u8 opcode[0x10]; 5826 u8 reserved_0[0x10]; 5827 5828 u8 reserved_1[0x10]; 5829 u8 op_mod[0x10]; 5830 5831 u8 reserved_2[0x40]; 5832 u8 driver_version[64][0x8]; 5833 }; 5834 5835 struct mlx5_ifc_query_hca_vport_pkey_out_bits { 5836 u8 status[0x8]; 5837 u8 reserved_at_8[0x18]; 5838 5839 u8 syndrome[0x20]; 5840 5841 u8 reserved_at_40[0x40]; 5842 5843 struct mlx5_ifc_pkey_bits pkey[]; 5844 }; 5845 5846 struct mlx5_ifc_query_hca_vport_pkey_in_bits { 5847 u8 opcode[0x10]; 5848 u8 reserved_at_10[0x10]; 5849 5850 u8 reserved_at_20[0x10]; 5851 u8 op_mod[0x10]; 5852 5853 u8 other_vport[0x1]; 5854 u8 reserved_at_41[0xb]; 5855 u8 port_num[0x4]; 5856 u8 vport_number[0x10]; 5857 5858 u8 reserved_at_60[0x10]; 5859 u8 pkey_index[0x10]; 5860 }; 5861 5862 enum { 5863 MLX5_HCA_VPORT_SEL_PORT_GUID = 1 << 0, 5864 MLX5_HCA_VPORT_SEL_NODE_GUID = 1 << 1, 5865 MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2, 5866 }; 5867 5868 struct mlx5_ifc_query_hca_vport_gid_out_bits { 5869 u8 status[0x8]; 5870 u8 reserved_at_8[0x18]; 5871 5872 u8 syndrome[0x20]; 5873 5874 u8 reserved_at_40[0x20]; 5875 5876 u8 gids_num[0x10]; 5877 u8 reserved_at_70[0x10]; 5878 5879 struct mlx5_ifc_array128_auto_bits gid[]; 5880 }; 5881 5882 struct mlx5_ifc_query_hca_vport_gid_in_bits { 5883 u8 opcode[0x10]; 5884 u8 reserved_at_10[0x10]; 5885 5886 u8 reserved_at_20[0x10]; 5887 u8 op_mod[0x10]; 5888 5889 u8 other_vport[0x1]; 5890 u8 reserved_at_41[0xb]; 5891 u8 port_num[0x4]; 5892 u8 vport_number[0x10]; 5893 5894 u8 reserved_at_60[0x10]; 5895 u8 gid_index[0x10]; 5896 }; 5897 5898 struct mlx5_ifc_query_hca_vport_context_out_bits { 5899 u8 status[0x8]; 5900 u8 reserved_at_8[0x18]; 5901 5902 u8 syndrome[0x20]; 5903 5904 u8 reserved_at_40[0x40]; 5905 5906 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 5907 }; 5908 5909 struct mlx5_ifc_query_hca_vport_context_in_bits { 5910 u8 opcode[0x10]; 5911 u8 reserved_at_10[0x10]; 5912 5913 u8 reserved_at_20[0x10]; 5914 u8 op_mod[0x10]; 5915 5916 u8 other_vport[0x1]; 5917 u8 reserved_at_41[0xb]; 5918 u8 port_num[0x4]; 5919 u8 vport_number[0x10]; 5920 5921 u8 reserved_at_60[0x20]; 5922 }; 5923 5924 struct mlx5_ifc_query_hca_cap_out_bits { 5925 u8 status[0x8]; 5926 u8 reserved_at_8[0x18]; 5927 5928 u8 syndrome[0x20]; 5929 5930 u8 reserved_at_40[0x40]; 5931 5932 union mlx5_ifc_hca_cap_union_bits capability; 5933 }; 5934 5935 struct mlx5_ifc_query_hca_cap_in_bits { 5936 u8 opcode[0x10]; 5937 u8 reserved_at_10[0x10]; 5938 5939 u8 reserved_at_20[0x10]; 5940 u8 op_mod[0x10]; 5941 5942 u8 other_function[0x1]; 5943 u8 ec_vf_function[0x1]; 5944 u8 reserved_at_42[0xe]; 5945 u8 function_id[0x10]; 5946 5947 u8 reserved_at_60[0x20]; 5948 }; 5949 5950 struct mlx5_ifc_other_hca_cap_bits { 5951 u8 roce[0x1]; 5952 u8 reserved_at_1[0x27f]; 5953 }; 5954 5955 struct mlx5_ifc_query_other_hca_cap_out_bits { 5956 u8 status[0x8]; 5957 u8 reserved_at_8[0x18]; 5958 5959 u8 syndrome[0x20]; 5960 5961 u8 reserved_at_40[0x40]; 5962 5963 struct mlx5_ifc_other_hca_cap_bits other_capability; 5964 }; 5965 5966 struct mlx5_ifc_query_other_hca_cap_in_bits { 5967 u8 opcode[0x10]; 5968 u8 reserved_at_10[0x10]; 5969 5970 u8 reserved_at_20[0x10]; 5971 u8 op_mod[0x10]; 5972 5973 u8 reserved_at_40[0x10]; 5974 u8 function_id[0x10]; 5975 5976 u8 reserved_at_60[0x20]; 5977 }; 5978 5979 struct mlx5_ifc_modify_other_hca_cap_out_bits { 5980 u8 status[0x8]; 5981 u8 reserved_at_8[0x18]; 5982 5983 u8 syndrome[0x20]; 5984 5985 u8 reserved_at_40[0x40]; 5986 }; 5987 5988 struct mlx5_ifc_modify_other_hca_cap_in_bits { 5989 u8 opcode[0x10]; 5990 u8 reserved_at_10[0x10]; 5991 5992 u8 reserved_at_20[0x10]; 5993 u8 op_mod[0x10]; 5994 5995 u8 reserved_at_40[0x10]; 5996 u8 function_id[0x10]; 5997 u8 field_select[0x20]; 5998 5999 struct mlx5_ifc_other_hca_cap_bits other_capability; 6000 }; 6001 6002 struct mlx5_ifc_flow_table_context_bits { 6003 u8 reformat_en[0x1]; 6004 u8 decap_en[0x1]; 6005 u8 sw_owner[0x1]; 6006 u8 termination_table[0x1]; 6007 u8 table_miss_action[0x4]; 6008 u8 level[0x8]; 6009 u8 reserved_at_10[0x8]; 6010 u8 log_size[0x8]; 6011 6012 u8 reserved_at_20[0x8]; 6013 u8 table_miss_id[0x18]; 6014 6015 u8 reserved_at_40[0x8]; 6016 u8 lag_master_next_table_id[0x18]; 6017 6018 u8 reserved_at_60[0x60]; 6019 6020 u8 sw_owner_icm_root_1[0x40]; 6021 6022 u8 sw_owner_icm_root_0[0x40]; 6023 6024 }; 6025 6026 struct mlx5_ifc_query_flow_table_out_bits { 6027 u8 status[0x8]; 6028 u8 reserved_at_8[0x18]; 6029 6030 u8 syndrome[0x20]; 6031 6032 u8 reserved_at_40[0x80]; 6033 6034 struct mlx5_ifc_flow_table_context_bits flow_table_context; 6035 }; 6036 6037 struct mlx5_ifc_query_flow_table_in_bits { 6038 u8 opcode[0x10]; 6039 u8 reserved_at_10[0x10]; 6040 6041 u8 reserved_at_20[0x10]; 6042 u8 op_mod[0x10]; 6043 6044 u8 reserved_at_40[0x40]; 6045 6046 u8 table_type[0x8]; 6047 u8 reserved_at_88[0x18]; 6048 6049 u8 reserved_at_a0[0x8]; 6050 u8 table_id[0x18]; 6051 6052 u8 reserved_at_c0[0x140]; 6053 }; 6054 6055 struct mlx5_ifc_query_fte_out_bits { 6056 u8 status[0x8]; 6057 u8 reserved_at_8[0x18]; 6058 6059 u8 syndrome[0x20]; 6060 6061 u8 reserved_at_40[0x1c0]; 6062 6063 struct mlx5_ifc_flow_context_bits flow_context; 6064 }; 6065 6066 struct mlx5_ifc_query_fte_in_bits { 6067 u8 opcode[0x10]; 6068 u8 reserved_at_10[0x10]; 6069 6070 u8 reserved_at_20[0x10]; 6071 u8 op_mod[0x10]; 6072 6073 u8 reserved_at_40[0x40]; 6074 6075 u8 table_type[0x8]; 6076 u8 reserved_at_88[0x18]; 6077 6078 u8 reserved_at_a0[0x8]; 6079 u8 table_id[0x18]; 6080 6081 u8 reserved_at_c0[0x40]; 6082 6083 u8 flow_index[0x20]; 6084 6085 u8 reserved_at_120[0xe0]; 6086 }; 6087 6088 struct mlx5_ifc_match_definer_format_0_bits { 6089 u8 reserved_at_0[0x100]; 6090 6091 u8 metadata_reg_c_0[0x20]; 6092 6093 u8 metadata_reg_c_1[0x20]; 6094 6095 u8 outer_dmac_47_16[0x20]; 6096 6097 u8 outer_dmac_15_0[0x10]; 6098 u8 outer_ethertype[0x10]; 6099 6100 u8 reserved_at_180[0x1]; 6101 u8 sx_sniffer[0x1]; 6102 u8 functional_lb[0x1]; 6103 u8 outer_ip_frag[0x1]; 6104 u8 outer_qp_type[0x2]; 6105 u8 outer_encap_type[0x2]; 6106 u8 port_number[0x2]; 6107 u8 outer_l3_type[0x2]; 6108 u8 outer_l4_type[0x2]; 6109 u8 outer_first_vlan_type[0x2]; 6110 u8 outer_first_vlan_prio[0x3]; 6111 u8 outer_first_vlan_cfi[0x1]; 6112 u8 outer_first_vlan_vid[0xc]; 6113 6114 u8 outer_l4_type_ext[0x4]; 6115 u8 reserved_at_1a4[0x2]; 6116 u8 outer_ipsec_layer[0x2]; 6117 u8 outer_l2_type[0x2]; 6118 u8 force_lb[0x1]; 6119 u8 outer_l2_ok[0x1]; 6120 u8 outer_l3_ok[0x1]; 6121 u8 outer_l4_ok[0x1]; 6122 u8 outer_second_vlan_type[0x2]; 6123 u8 outer_second_vlan_prio[0x3]; 6124 u8 outer_second_vlan_cfi[0x1]; 6125 u8 outer_second_vlan_vid[0xc]; 6126 6127 u8 outer_smac_47_16[0x20]; 6128 6129 u8 outer_smac_15_0[0x10]; 6130 u8 inner_ipv4_checksum_ok[0x1]; 6131 u8 inner_l4_checksum_ok[0x1]; 6132 u8 outer_ipv4_checksum_ok[0x1]; 6133 u8 outer_l4_checksum_ok[0x1]; 6134 u8 inner_l3_ok[0x1]; 6135 u8 inner_l4_ok[0x1]; 6136 u8 outer_l3_ok_duplicate[0x1]; 6137 u8 outer_l4_ok_duplicate[0x1]; 6138 u8 outer_tcp_cwr[0x1]; 6139 u8 outer_tcp_ece[0x1]; 6140 u8 outer_tcp_urg[0x1]; 6141 u8 outer_tcp_ack[0x1]; 6142 u8 outer_tcp_psh[0x1]; 6143 u8 outer_tcp_rst[0x1]; 6144 u8 outer_tcp_syn[0x1]; 6145 u8 outer_tcp_fin[0x1]; 6146 }; 6147 6148 struct mlx5_ifc_match_definer_format_22_bits { 6149 u8 reserved_at_0[0x100]; 6150 6151 u8 outer_ip_src_addr[0x20]; 6152 6153 u8 outer_ip_dest_addr[0x20]; 6154 6155 u8 outer_l4_sport[0x10]; 6156 u8 outer_l4_dport[0x10]; 6157 6158 u8 reserved_at_160[0x1]; 6159 u8 sx_sniffer[0x1]; 6160 u8 functional_lb[0x1]; 6161 u8 outer_ip_frag[0x1]; 6162 u8 outer_qp_type[0x2]; 6163 u8 outer_encap_type[0x2]; 6164 u8 port_number[0x2]; 6165 u8 outer_l3_type[0x2]; 6166 u8 outer_l4_type[0x2]; 6167 u8 outer_first_vlan_type[0x2]; 6168 u8 outer_first_vlan_prio[0x3]; 6169 u8 outer_first_vlan_cfi[0x1]; 6170 u8 outer_first_vlan_vid[0xc]; 6171 6172 u8 metadata_reg_c_0[0x20]; 6173 6174 u8 outer_dmac_47_16[0x20]; 6175 6176 u8 outer_smac_47_16[0x20]; 6177 6178 u8 outer_smac_15_0[0x10]; 6179 u8 outer_dmac_15_0[0x10]; 6180 }; 6181 6182 struct mlx5_ifc_match_definer_format_23_bits { 6183 u8 reserved_at_0[0x100]; 6184 6185 u8 inner_ip_src_addr[0x20]; 6186 6187 u8 inner_ip_dest_addr[0x20]; 6188 6189 u8 inner_l4_sport[0x10]; 6190 u8 inner_l4_dport[0x10]; 6191 6192 u8 reserved_at_160[0x1]; 6193 u8 sx_sniffer[0x1]; 6194 u8 functional_lb[0x1]; 6195 u8 inner_ip_frag[0x1]; 6196 u8 inner_qp_type[0x2]; 6197 u8 inner_encap_type[0x2]; 6198 u8 port_number[0x2]; 6199 u8 inner_l3_type[0x2]; 6200 u8 inner_l4_type[0x2]; 6201 u8 inner_first_vlan_type[0x2]; 6202 u8 inner_first_vlan_prio[0x3]; 6203 u8 inner_first_vlan_cfi[0x1]; 6204 u8 inner_first_vlan_vid[0xc]; 6205 6206 u8 tunnel_header_0[0x20]; 6207 6208 u8 inner_dmac_47_16[0x20]; 6209 6210 u8 inner_smac_47_16[0x20]; 6211 6212 u8 inner_smac_15_0[0x10]; 6213 u8 inner_dmac_15_0[0x10]; 6214 }; 6215 6216 struct mlx5_ifc_match_definer_format_29_bits { 6217 u8 reserved_at_0[0xc0]; 6218 6219 u8 outer_ip_dest_addr[0x80]; 6220 6221 u8 outer_ip_src_addr[0x80]; 6222 6223 u8 outer_l4_sport[0x10]; 6224 u8 outer_l4_dport[0x10]; 6225 6226 u8 reserved_at_1e0[0x20]; 6227 }; 6228 6229 struct mlx5_ifc_match_definer_format_30_bits { 6230 u8 reserved_at_0[0xa0]; 6231 6232 u8 outer_ip_dest_addr[0x80]; 6233 6234 u8 outer_ip_src_addr[0x80]; 6235 6236 u8 outer_dmac_47_16[0x20]; 6237 6238 u8 outer_smac_47_16[0x20]; 6239 6240 u8 outer_smac_15_0[0x10]; 6241 u8 outer_dmac_15_0[0x10]; 6242 }; 6243 6244 struct mlx5_ifc_match_definer_format_31_bits { 6245 u8 reserved_at_0[0xc0]; 6246 6247 u8 inner_ip_dest_addr[0x80]; 6248 6249 u8 inner_ip_src_addr[0x80]; 6250 6251 u8 inner_l4_sport[0x10]; 6252 u8 inner_l4_dport[0x10]; 6253 6254 u8 reserved_at_1e0[0x20]; 6255 }; 6256 6257 struct mlx5_ifc_match_definer_format_32_bits { 6258 u8 reserved_at_0[0xa0]; 6259 6260 u8 inner_ip_dest_addr[0x80]; 6261 6262 u8 inner_ip_src_addr[0x80]; 6263 6264 u8 inner_dmac_47_16[0x20]; 6265 6266 u8 inner_smac_47_16[0x20]; 6267 6268 u8 inner_smac_15_0[0x10]; 6269 u8 inner_dmac_15_0[0x10]; 6270 }; 6271 6272 enum { 6273 MLX5_IFC_DEFINER_FORMAT_ID_SELECT = 61, 6274 }; 6275 6276 #define MLX5_IFC_DEFINER_FORMAT_OFFSET_UNUSED 0x0 6277 #define MLX5_IFC_DEFINER_FORMAT_OFFSET_OUTER_ETH_PKT_LEN 0x48 6278 #define MLX5_IFC_DEFINER_DW_SELECTORS_NUM 9 6279 #define MLX5_IFC_DEFINER_BYTE_SELECTORS_NUM 8 6280 6281 struct mlx5_ifc_match_definer_match_mask_bits { 6282 u8 reserved_at_1c0[5][0x20]; 6283 u8 match_dw_8[0x20]; 6284 u8 match_dw_7[0x20]; 6285 u8 match_dw_6[0x20]; 6286 u8 match_dw_5[0x20]; 6287 u8 match_dw_4[0x20]; 6288 u8 match_dw_3[0x20]; 6289 u8 match_dw_2[0x20]; 6290 u8 match_dw_1[0x20]; 6291 u8 match_dw_0[0x20]; 6292 6293 u8 match_byte_7[0x8]; 6294 u8 match_byte_6[0x8]; 6295 u8 match_byte_5[0x8]; 6296 u8 match_byte_4[0x8]; 6297 6298 u8 match_byte_3[0x8]; 6299 u8 match_byte_2[0x8]; 6300 u8 match_byte_1[0x8]; 6301 u8 match_byte_0[0x8]; 6302 }; 6303 6304 struct mlx5_ifc_match_definer_bits { 6305 u8 modify_field_select[0x40]; 6306 6307 u8 reserved_at_40[0x40]; 6308 6309 u8 reserved_at_80[0x10]; 6310 u8 format_id[0x10]; 6311 6312 u8 reserved_at_a0[0x60]; 6313 6314 u8 format_select_dw3[0x8]; 6315 u8 format_select_dw2[0x8]; 6316 u8 format_select_dw1[0x8]; 6317 u8 format_select_dw0[0x8]; 6318 6319 u8 format_select_dw7[0x8]; 6320 u8 format_select_dw6[0x8]; 6321 u8 format_select_dw5[0x8]; 6322 u8 format_select_dw4[0x8]; 6323 6324 u8 reserved_at_100[0x18]; 6325 u8 format_select_dw8[0x8]; 6326 6327 u8 reserved_at_120[0x20]; 6328 6329 u8 format_select_byte3[0x8]; 6330 u8 format_select_byte2[0x8]; 6331 u8 format_select_byte1[0x8]; 6332 u8 format_select_byte0[0x8]; 6333 6334 u8 format_select_byte7[0x8]; 6335 u8 format_select_byte6[0x8]; 6336 u8 format_select_byte5[0x8]; 6337 u8 format_select_byte4[0x8]; 6338 6339 u8 reserved_at_180[0x40]; 6340 6341 union { 6342 struct { 6343 u8 match_mask[16][0x20]; 6344 }; 6345 struct mlx5_ifc_match_definer_match_mask_bits match_mask_format; 6346 }; 6347 }; 6348 6349 struct mlx5_ifc_general_obj_create_param_bits { 6350 u8 alias_object[0x1]; 6351 u8 reserved_at_1[0x2]; 6352 u8 log_obj_range[0x5]; 6353 u8 reserved_at_8[0x18]; 6354 }; 6355 6356 struct mlx5_ifc_general_obj_query_param_bits { 6357 u8 alias_object[0x1]; 6358 u8 obj_offset[0x1f]; 6359 }; 6360 6361 struct mlx5_ifc_general_obj_in_cmd_hdr_bits { 6362 u8 opcode[0x10]; 6363 u8 uid[0x10]; 6364 6365 u8 vhca_tunnel_id[0x10]; 6366 u8 obj_type[0x10]; 6367 6368 u8 obj_id[0x20]; 6369 6370 union { 6371 struct mlx5_ifc_general_obj_create_param_bits create; 6372 struct mlx5_ifc_general_obj_query_param_bits query; 6373 } op_param; 6374 }; 6375 6376 struct mlx5_ifc_general_obj_out_cmd_hdr_bits { 6377 u8 status[0x8]; 6378 u8 reserved_at_8[0x18]; 6379 6380 u8 syndrome[0x20]; 6381 6382 u8 obj_id[0x20]; 6383 6384 u8 reserved_at_60[0x20]; 6385 }; 6386 6387 struct mlx5_ifc_allow_other_vhca_access_in_bits { 6388 u8 opcode[0x10]; 6389 u8 uid[0x10]; 6390 u8 reserved_at_20[0x10]; 6391 u8 op_mod[0x10]; 6392 u8 reserved_at_40[0x50]; 6393 u8 object_type_to_be_accessed[0x10]; 6394 u8 object_id_to_be_accessed[0x20]; 6395 u8 reserved_at_c0[0x40]; 6396 union { 6397 u8 access_key_raw[0x100]; 6398 u8 access_key[8][0x20]; 6399 }; 6400 }; 6401 6402 struct mlx5_ifc_allow_other_vhca_access_out_bits { 6403 u8 status[0x8]; 6404 u8 reserved_at_8[0x18]; 6405 u8 syndrome[0x20]; 6406 u8 reserved_at_40[0x40]; 6407 }; 6408 6409 struct mlx5_ifc_modify_header_arg_bits { 6410 u8 reserved_at_0[0x80]; 6411 6412 u8 reserved_at_80[0x8]; 6413 u8 access_pd[0x18]; 6414 }; 6415 6416 struct mlx5_ifc_create_modify_header_arg_in_bits { 6417 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 6418 struct mlx5_ifc_modify_header_arg_bits arg; 6419 }; 6420 6421 struct mlx5_ifc_create_match_definer_in_bits { 6422 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 6423 6424 struct mlx5_ifc_match_definer_bits obj_context; 6425 }; 6426 6427 struct mlx5_ifc_create_match_definer_out_bits { 6428 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 6429 }; 6430 6431 struct mlx5_ifc_alias_context_bits { 6432 u8 vhca_id_to_be_accessed[0x10]; 6433 u8 reserved_at_10[0xd]; 6434 u8 status[0x3]; 6435 u8 object_id_to_be_accessed[0x20]; 6436 u8 reserved_at_40[0x40]; 6437 union { 6438 u8 access_key_raw[0x100]; 6439 u8 access_key[8][0x20]; 6440 }; 6441 u8 metadata[0x80]; 6442 }; 6443 6444 struct mlx5_ifc_create_alias_obj_in_bits { 6445 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 6446 struct mlx5_ifc_alias_context_bits alias_ctx; 6447 }; 6448 6449 enum { 6450 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 6451 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 6452 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 6453 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3, 6454 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_3 = 0x4, 6455 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_4 = 0x5, 6456 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_5 = 0x6, 6457 }; 6458 6459 struct mlx5_ifc_query_flow_group_out_bits { 6460 u8 status[0x8]; 6461 u8 reserved_at_8[0x18]; 6462 6463 u8 syndrome[0x20]; 6464 6465 u8 reserved_at_40[0xa0]; 6466 6467 u8 start_flow_index[0x20]; 6468 6469 u8 reserved_at_100[0x20]; 6470 6471 u8 end_flow_index[0x20]; 6472 6473 u8 reserved_at_140[0xa0]; 6474 6475 u8 reserved_at_1e0[0x18]; 6476 u8 match_criteria_enable[0x8]; 6477 6478 struct mlx5_ifc_fte_match_param_bits match_criteria; 6479 6480 u8 reserved_at_1200[0xe00]; 6481 }; 6482 6483 struct mlx5_ifc_query_flow_group_in_bits { 6484 u8 opcode[0x10]; 6485 u8 reserved_at_10[0x10]; 6486 6487 u8 reserved_at_20[0x10]; 6488 u8 op_mod[0x10]; 6489 6490 u8 reserved_at_40[0x40]; 6491 6492 u8 table_type[0x8]; 6493 u8 reserved_at_88[0x18]; 6494 6495 u8 reserved_at_a0[0x8]; 6496 u8 table_id[0x18]; 6497 6498 u8 group_id[0x20]; 6499 6500 u8 reserved_at_e0[0x120]; 6501 }; 6502 6503 struct mlx5_ifc_query_flow_counter_out_bits { 6504 u8 status[0x8]; 6505 u8 reserved_at_8[0x18]; 6506 6507 u8 syndrome[0x20]; 6508 6509 u8 reserved_at_40[0x40]; 6510 6511 struct mlx5_ifc_traffic_counter_bits flow_statistics[]; 6512 }; 6513 6514 struct mlx5_ifc_query_flow_counter_in_bits { 6515 u8 opcode[0x10]; 6516 u8 reserved_at_10[0x10]; 6517 6518 u8 reserved_at_20[0x10]; 6519 u8 op_mod[0x10]; 6520 6521 u8 reserved_at_40[0x80]; 6522 6523 u8 clear[0x1]; 6524 u8 reserved_at_c1[0xf]; 6525 u8 num_of_counters[0x10]; 6526 6527 u8 flow_counter_id[0x20]; 6528 }; 6529 6530 struct mlx5_ifc_query_esw_vport_context_out_bits { 6531 u8 status[0x8]; 6532 u8 reserved_at_8[0x18]; 6533 6534 u8 syndrome[0x20]; 6535 6536 u8 reserved_at_40[0x40]; 6537 6538 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 6539 }; 6540 6541 struct mlx5_ifc_query_esw_vport_context_in_bits { 6542 u8 opcode[0x10]; 6543 u8 reserved_at_10[0x10]; 6544 6545 u8 reserved_at_20[0x10]; 6546 u8 op_mod[0x10]; 6547 6548 u8 other_vport[0x1]; 6549 u8 reserved_at_41[0xf]; 6550 u8 vport_number[0x10]; 6551 6552 u8 reserved_at_60[0x20]; 6553 }; 6554 6555 struct mlx5_ifc_modify_esw_vport_context_out_bits { 6556 u8 status[0x8]; 6557 u8 reserved_at_8[0x18]; 6558 6559 u8 syndrome[0x20]; 6560 6561 u8 reserved_at_40[0x40]; 6562 }; 6563 6564 struct mlx5_ifc_esw_vport_context_fields_select_bits { 6565 u8 reserved_at_0[0x1b]; 6566 u8 fdb_to_vport_reg_c_id[0x1]; 6567 u8 vport_cvlan_insert[0x1]; 6568 u8 vport_svlan_insert[0x1]; 6569 u8 vport_cvlan_strip[0x1]; 6570 u8 vport_svlan_strip[0x1]; 6571 }; 6572 6573 struct mlx5_ifc_modify_esw_vport_context_in_bits { 6574 u8 opcode[0x10]; 6575 u8 reserved_at_10[0x10]; 6576 6577 u8 reserved_at_20[0x10]; 6578 u8 op_mod[0x10]; 6579 6580 u8 other_vport[0x1]; 6581 u8 reserved_at_41[0xf]; 6582 u8 vport_number[0x10]; 6583 6584 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select; 6585 6586 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 6587 }; 6588 6589 struct mlx5_ifc_query_eq_out_bits { 6590 u8 status[0x8]; 6591 u8 reserved_at_8[0x18]; 6592 6593 u8 syndrome[0x20]; 6594 6595 u8 reserved_at_40[0x40]; 6596 6597 struct mlx5_ifc_eqc_bits eq_context_entry; 6598 6599 u8 reserved_at_280[0x40]; 6600 6601 u8 event_bitmask[0x40]; 6602 6603 u8 reserved_at_300[0x580]; 6604 6605 u8 pas[][0x40]; 6606 }; 6607 6608 struct mlx5_ifc_query_eq_in_bits { 6609 u8 opcode[0x10]; 6610 u8 reserved_at_10[0x10]; 6611 6612 u8 reserved_at_20[0x10]; 6613 u8 op_mod[0x10]; 6614 6615 u8 reserved_at_40[0x18]; 6616 u8 eq_number[0x8]; 6617 6618 u8 reserved_at_60[0x20]; 6619 }; 6620 6621 struct mlx5_ifc_packet_reformat_context_in_bits { 6622 u8 reformat_type[0x8]; 6623 u8 reserved_at_8[0x4]; 6624 u8 reformat_param_0[0x4]; 6625 u8 reserved_at_10[0x6]; 6626 u8 reformat_data_size[0xa]; 6627 6628 u8 reformat_param_1[0x8]; 6629 u8 reserved_at_28[0x8]; 6630 u8 reformat_data[2][0x8]; 6631 6632 u8 more_reformat_data[][0x8]; 6633 }; 6634 6635 struct mlx5_ifc_query_packet_reformat_context_out_bits { 6636 u8 status[0x8]; 6637 u8 reserved_at_8[0x18]; 6638 6639 u8 syndrome[0x20]; 6640 6641 u8 reserved_at_40[0xa0]; 6642 6643 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context[]; 6644 }; 6645 6646 struct mlx5_ifc_query_packet_reformat_context_in_bits { 6647 u8 opcode[0x10]; 6648 u8 reserved_at_10[0x10]; 6649 6650 u8 reserved_at_20[0x10]; 6651 u8 op_mod[0x10]; 6652 6653 u8 packet_reformat_id[0x20]; 6654 6655 u8 reserved_at_60[0xa0]; 6656 }; 6657 6658 struct mlx5_ifc_alloc_packet_reformat_context_out_bits { 6659 u8 status[0x8]; 6660 u8 reserved_at_8[0x18]; 6661 6662 u8 syndrome[0x20]; 6663 6664 u8 packet_reformat_id[0x20]; 6665 6666 u8 reserved_at_60[0x20]; 6667 }; 6668 6669 enum { 6670 MLX5_REFORMAT_CONTEXT_ANCHOR_MAC_START = 0x1, 6671 MLX5_REFORMAT_CONTEXT_ANCHOR_IP_START = 0x7, 6672 MLX5_REFORMAT_CONTEXT_ANCHOR_TCP_UDP_START = 0x9, 6673 }; 6674 6675 enum mlx5_reformat_ctx_type { 6676 MLX5_REFORMAT_TYPE_L2_TO_VXLAN = 0x0, 6677 MLX5_REFORMAT_TYPE_L2_TO_NVGRE = 0x1, 6678 MLX5_REFORMAT_TYPE_L2_TO_L2_TUNNEL = 0x2, 6679 MLX5_REFORMAT_TYPE_L3_TUNNEL_TO_L2 = 0x3, 6680 MLX5_REFORMAT_TYPE_L2_TO_L3_TUNNEL = 0x4, 6681 MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_IPV4 = 0x5, 6682 MLX5_REFORMAT_TYPE_L2_TO_L3_ESP_TUNNEL = 0x6, 6683 MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_UDPV4 = 0x7, 6684 MLX5_REFORMAT_TYPE_DEL_ESP_TRANSPORT = 0x8, 6685 MLX5_REFORMAT_TYPE_L3_ESP_TUNNEL_TO_L2 = 0x9, 6686 MLX5_REFORMAT_TYPE_DEL_ESP_TRANSPORT_OVER_UDP = 0xa, 6687 MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_IPV6 = 0xb, 6688 MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_UDPV6 = 0xc, 6689 MLX5_REFORMAT_TYPE_INSERT_HDR = 0xf, 6690 MLX5_REFORMAT_TYPE_REMOVE_HDR = 0x10, 6691 MLX5_REFORMAT_TYPE_ADD_MACSEC = 0x11, 6692 MLX5_REFORMAT_TYPE_DEL_MACSEC = 0x12, 6693 }; 6694 6695 struct mlx5_ifc_alloc_packet_reformat_context_in_bits { 6696 u8 opcode[0x10]; 6697 u8 reserved_at_10[0x10]; 6698 6699 u8 reserved_at_20[0x10]; 6700 u8 op_mod[0x10]; 6701 6702 u8 reserved_at_40[0xa0]; 6703 6704 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context; 6705 }; 6706 6707 struct mlx5_ifc_dealloc_packet_reformat_context_out_bits { 6708 u8 status[0x8]; 6709 u8 reserved_at_8[0x18]; 6710 6711 u8 syndrome[0x20]; 6712 6713 u8 reserved_at_40[0x40]; 6714 }; 6715 6716 struct mlx5_ifc_dealloc_packet_reformat_context_in_bits { 6717 u8 opcode[0x10]; 6718 u8 reserved_at_10[0x10]; 6719 6720 u8 reserved_20[0x10]; 6721 u8 op_mod[0x10]; 6722 6723 u8 packet_reformat_id[0x20]; 6724 6725 u8 reserved_60[0x20]; 6726 }; 6727 6728 struct mlx5_ifc_set_action_in_bits { 6729 u8 action_type[0x4]; 6730 u8 field[0xc]; 6731 u8 reserved_at_10[0x3]; 6732 u8 offset[0x5]; 6733 u8 reserved_at_18[0x3]; 6734 u8 length[0x5]; 6735 6736 u8 data[0x20]; 6737 }; 6738 6739 struct mlx5_ifc_add_action_in_bits { 6740 u8 action_type[0x4]; 6741 u8 field[0xc]; 6742 u8 reserved_at_10[0x10]; 6743 6744 u8 data[0x20]; 6745 }; 6746 6747 struct mlx5_ifc_copy_action_in_bits { 6748 u8 action_type[0x4]; 6749 u8 src_field[0xc]; 6750 u8 reserved_at_10[0x3]; 6751 u8 src_offset[0x5]; 6752 u8 reserved_at_18[0x3]; 6753 u8 length[0x5]; 6754 6755 u8 reserved_at_20[0x4]; 6756 u8 dst_field[0xc]; 6757 u8 reserved_at_30[0x3]; 6758 u8 dst_offset[0x5]; 6759 u8 reserved_at_38[0x8]; 6760 }; 6761 6762 union mlx5_ifc_set_add_copy_action_in_auto_bits { 6763 struct mlx5_ifc_set_action_in_bits set_action_in; 6764 struct mlx5_ifc_add_action_in_bits add_action_in; 6765 struct mlx5_ifc_copy_action_in_bits copy_action_in; 6766 u8 reserved_at_0[0x40]; 6767 }; 6768 6769 enum { 6770 MLX5_ACTION_TYPE_SET = 0x1, 6771 MLX5_ACTION_TYPE_ADD = 0x2, 6772 MLX5_ACTION_TYPE_COPY = 0x3, 6773 }; 6774 6775 enum { 6776 MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16 = 0x1, 6777 MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0 = 0x2, 6778 MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE = 0x3, 6779 MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16 = 0x4, 6780 MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0 = 0x5, 6781 MLX5_ACTION_IN_FIELD_OUT_IP_DSCP = 0x6, 6782 MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS = 0x7, 6783 MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT = 0x8, 6784 MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT = 0x9, 6785 MLX5_ACTION_IN_FIELD_OUT_IP_TTL = 0xa, 6786 MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT = 0xb, 6787 MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT = 0xc, 6788 MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96 = 0xd, 6789 MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64 = 0xe, 6790 MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32 = 0xf, 6791 MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0 = 0x10, 6792 MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96 = 0x11, 6793 MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64 = 0x12, 6794 MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32 = 0x13, 6795 MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0 = 0x14, 6796 MLX5_ACTION_IN_FIELD_OUT_SIPV4 = 0x15, 6797 MLX5_ACTION_IN_FIELD_OUT_DIPV4 = 0x16, 6798 MLX5_ACTION_IN_FIELD_OUT_FIRST_VID = 0x17, 6799 MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47, 6800 MLX5_ACTION_IN_FIELD_METADATA_REG_A = 0x49, 6801 MLX5_ACTION_IN_FIELD_METADATA_REG_B = 0x50, 6802 MLX5_ACTION_IN_FIELD_METADATA_REG_C_0 = 0x51, 6803 MLX5_ACTION_IN_FIELD_METADATA_REG_C_1 = 0x52, 6804 MLX5_ACTION_IN_FIELD_METADATA_REG_C_2 = 0x53, 6805 MLX5_ACTION_IN_FIELD_METADATA_REG_C_3 = 0x54, 6806 MLX5_ACTION_IN_FIELD_METADATA_REG_C_4 = 0x55, 6807 MLX5_ACTION_IN_FIELD_METADATA_REG_C_5 = 0x56, 6808 MLX5_ACTION_IN_FIELD_METADATA_REG_C_6 = 0x57, 6809 MLX5_ACTION_IN_FIELD_METADATA_REG_C_7 = 0x58, 6810 MLX5_ACTION_IN_FIELD_OUT_TCP_SEQ_NUM = 0x59, 6811 MLX5_ACTION_IN_FIELD_OUT_TCP_ACK_NUM = 0x5B, 6812 MLX5_ACTION_IN_FIELD_IPSEC_SYNDROME = 0x5D, 6813 MLX5_ACTION_IN_FIELD_OUT_EMD_47_32 = 0x6F, 6814 MLX5_ACTION_IN_FIELD_OUT_EMD_31_0 = 0x70, 6815 }; 6816 6817 struct mlx5_ifc_alloc_modify_header_context_out_bits { 6818 u8 status[0x8]; 6819 u8 reserved_at_8[0x18]; 6820 6821 u8 syndrome[0x20]; 6822 6823 u8 modify_header_id[0x20]; 6824 6825 u8 reserved_at_60[0x20]; 6826 }; 6827 6828 struct mlx5_ifc_alloc_modify_header_context_in_bits { 6829 u8 opcode[0x10]; 6830 u8 reserved_at_10[0x10]; 6831 6832 u8 reserved_at_20[0x10]; 6833 u8 op_mod[0x10]; 6834 6835 u8 reserved_at_40[0x20]; 6836 6837 u8 table_type[0x8]; 6838 u8 reserved_at_68[0x10]; 6839 u8 num_of_actions[0x8]; 6840 6841 union mlx5_ifc_set_add_copy_action_in_auto_bits actions[]; 6842 }; 6843 6844 struct mlx5_ifc_dealloc_modify_header_context_out_bits { 6845 u8 status[0x8]; 6846 u8 reserved_at_8[0x18]; 6847 6848 u8 syndrome[0x20]; 6849 6850 u8 reserved_at_40[0x40]; 6851 }; 6852 6853 struct mlx5_ifc_dealloc_modify_header_context_in_bits { 6854 u8 opcode[0x10]; 6855 u8 reserved_at_10[0x10]; 6856 6857 u8 reserved_at_20[0x10]; 6858 u8 op_mod[0x10]; 6859 6860 u8 modify_header_id[0x20]; 6861 6862 u8 reserved_at_60[0x20]; 6863 }; 6864 6865 struct mlx5_ifc_query_modify_header_context_in_bits { 6866 u8 opcode[0x10]; 6867 u8 uid[0x10]; 6868 6869 u8 reserved_at_20[0x10]; 6870 u8 op_mod[0x10]; 6871 6872 u8 modify_header_id[0x20]; 6873 6874 u8 reserved_at_60[0xa0]; 6875 }; 6876 6877 struct mlx5_ifc_query_dct_out_bits { 6878 u8 status[0x8]; 6879 u8 reserved_at_8[0x18]; 6880 6881 u8 syndrome[0x20]; 6882 6883 u8 reserved_at_40[0x40]; 6884 6885 struct mlx5_ifc_dctc_bits dct_context_entry; 6886 6887 u8 reserved_at_280[0x180]; 6888 }; 6889 6890 struct mlx5_ifc_query_dct_in_bits { 6891 u8 opcode[0x10]; 6892 u8 reserved_at_10[0x10]; 6893 6894 u8 reserved_at_20[0x10]; 6895 u8 op_mod[0x10]; 6896 6897 u8 reserved_at_40[0x8]; 6898 u8 dctn[0x18]; 6899 6900 u8 reserved_at_60[0x20]; 6901 }; 6902 6903 struct mlx5_ifc_query_cq_out_bits { 6904 u8 status[0x8]; 6905 u8 reserved_at_8[0x18]; 6906 6907 u8 syndrome[0x20]; 6908 6909 u8 reserved_at_40[0x40]; 6910 6911 struct mlx5_ifc_cqc_bits cq_context; 6912 6913 u8 reserved_at_280[0x600]; 6914 6915 u8 pas[][0x40]; 6916 }; 6917 6918 struct mlx5_ifc_query_cq_in_bits { 6919 u8 opcode[0x10]; 6920 u8 reserved_at_10[0x10]; 6921 6922 u8 reserved_at_20[0x10]; 6923 u8 op_mod[0x10]; 6924 6925 u8 reserved_at_40[0x8]; 6926 u8 cqn[0x18]; 6927 6928 u8 reserved_at_60[0x20]; 6929 }; 6930 6931 struct mlx5_ifc_query_cong_status_out_bits { 6932 u8 status[0x8]; 6933 u8 reserved_at_8[0x18]; 6934 6935 u8 syndrome[0x20]; 6936 6937 u8 reserved_at_40[0x20]; 6938 6939 u8 enable[0x1]; 6940 u8 tag_enable[0x1]; 6941 u8 reserved_at_62[0x1e]; 6942 }; 6943 6944 struct mlx5_ifc_query_cong_status_in_bits { 6945 u8 opcode[0x10]; 6946 u8 reserved_at_10[0x10]; 6947 6948 u8 reserved_at_20[0x10]; 6949 u8 op_mod[0x10]; 6950 6951 u8 reserved_at_40[0x18]; 6952 u8 priority[0x4]; 6953 u8 cong_protocol[0x4]; 6954 6955 u8 reserved_at_60[0x20]; 6956 }; 6957 6958 struct mlx5_ifc_query_cong_statistics_out_bits { 6959 u8 status[0x8]; 6960 u8 reserved_at_8[0x18]; 6961 6962 u8 syndrome[0x20]; 6963 6964 u8 reserved_at_40[0x40]; 6965 6966 u8 rp_cur_flows[0x20]; 6967 6968 u8 sum_flows[0x20]; 6969 6970 u8 rp_cnp_ignored_high[0x20]; 6971 6972 u8 rp_cnp_ignored_low[0x20]; 6973 6974 u8 rp_cnp_handled_high[0x20]; 6975 6976 u8 rp_cnp_handled_low[0x20]; 6977 6978 u8 reserved_at_140[0x100]; 6979 6980 u8 time_stamp_high[0x20]; 6981 6982 u8 time_stamp_low[0x20]; 6983 6984 u8 accumulators_period[0x20]; 6985 6986 u8 np_ecn_marked_roce_packets_high[0x20]; 6987 6988 u8 np_ecn_marked_roce_packets_low[0x20]; 6989 6990 u8 np_cnp_sent_high[0x20]; 6991 6992 u8 np_cnp_sent_low[0x20]; 6993 6994 u8 reserved_at_320[0x560]; 6995 }; 6996 6997 struct mlx5_ifc_query_cong_statistics_in_bits { 6998 u8 opcode[0x10]; 6999 u8 reserved_at_10[0x10]; 7000 7001 u8 reserved_at_20[0x10]; 7002 u8 op_mod[0x10]; 7003 7004 u8 clear[0x1]; 7005 u8 reserved_at_41[0x1f]; 7006 7007 u8 reserved_at_60[0x20]; 7008 }; 7009 7010 struct mlx5_ifc_query_cong_params_out_bits { 7011 u8 status[0x8]; 7012 u8 reserved_at_8[0x18]; 7013 7014 u8 syndrome[0x20]; 7015 7016 u8 reserved_at_40[0x40]; 7017 7018 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 7019 }; 7020 7021 struct mlx5_ifc_query_cong_params_in_bits { 7022 u8 opcode[0x10]; 7023 u8 reserved_at_10[0x10]; 7024 7025 u8 reserved_at_20[0x10]; 7026 u8 op_mod[0x10]; 7027 7028 u8 reserved_at_40[0x1c]; 7029 u8 cong_protocol[0x4]; 7030 7031 u8 reserved_at_60[0x20]; 7032 }; 7033 7034 struct mlx5_ifc_query_adapter_out_bits { 7035 u8 status[0x8]; 7036 u8 reserved_at_8[0x18]; 7037 7038 u8 syndrome[0x20]; 7039 7040 u8 reserved_at_40[0x40]; 7041 7042 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct; 7043 }; 7044 7045 struct mlx5_ifc_query_adapter_in_bits { 7046 u8 opcode[0x10]; 7047 u8 reserved_at_10[0x10]; 7048 7049 u8 reserved_at_20[0x10]; 7050 u8 op_mod[0x10]; 7051 7052 u8 reserved_at_40[0x40]; 7053 }; 7054 7055 struct mlx5_ifc_qp_2rst_out_bits { 7056 u8 status[0x8]; 7057 u8 reserved_at_8[0x18]; 7058 7059 u8 syndrome[0x20]; 7060 7061 u8 reserved_at_40[0x40]; 7062 }; 7063 7064 struct mlx5_ifc_qp_2rst_in_bits { 7065 u8 opcode[0x10]; 7066 u8 uid[0x10]; 7067 7068 u8 reserved_at_20[0x10]; 7069 u8 op_mod[0x10]; 7070 7071 u8 reserved_at_40[0x8]; 7072 u8 qpn[0x18]; 7073 7074 u8 reserved_at_60[0x20]; 7075 }; 7076 7077 struct mlx5_ifc_qp_2err_out_bits { 7078 u8 status[0x8]; 7079 u8 reserved_at_8[0x18]; 7080 7081 u8 syndrome[0x20]; 7082 7083 u8 reserved_at_40[0x40]; 7084 }; 7085 7086 struct mlx5_ifc_qp_2err_in_bits { 7087 u8 opcode[0x10]; 7088 u8 uid[0x10]; 7089 7090 u8 reserved_at_20[0x10]; 7091 u8 op_mod[0x10]; 7092 7093 u8 reserved_at_40[0x8]; 7094 u8 qpn[0x18]; 7095 7096 u8 reserved_at_60[0x20]; 7097 }; 7098 7099 struct mlx5_ifc_page_fault_resume_out_bits { 7100 u8 status[0x8]; 7101 u8 reserved_at_8[0x18]; 7102 7103 u8 syndrome[0x20]; 7104 7105 u8 reserved_at_40[0x40]; 7106 }; 7107 7108 struct mlx5_ifc_page_fault_resume_in_bits { 7109 u8 opcode[0x10]; 7110 u8 reserved_at_10[0x10]; 7111 7112 u8 reserved_at_20[0x10]; 7113 u8 op_mod[0x10]; 7114 7115 u8 error[0x1]; 7116 u8 reserved_at_41[0x4]; 7117 u8 page_fault_type[0x3]; 7118 u8 wq_number[0x18]; 7119 7120 u8 reserved_at_60[0x8]; 7121 u8 token[0x18]; 7122 }; 7123 7124 struct mlx5_ifc_nop_out_bits { 7125 u8 status[0x8]; 7126 u8 reserved_at_8[0x18]; 7127 7128 u8 syndrome[0x20]; 7129 7130 u8 reserved_at_40[0x40]; 7131 }; 7132 7133 struct mlx5_ifc_nop_in_bits { 7134 u8 opcode[0x10]; 7135 u8 reserved_at_10[0x10]; 7136 7137 u8 reserved_at_20[0x10]; 7138 u8 op_mod[0x10]; 7139 7140 u8 reserved_at_40[0x40]; 7141 }; 7142 7143 struct mlx5_ifc_modify_vport_state_out_bits { 7144 u8 status[0x8]; 7145 u8 reserved_at_8[0x18]; 7146 7147 u8 syndrome[0x20]; 7148 7149 u8 reserved_at_40[0x40]; 7150 }; 7151 7152 struct mlx5_ifc_modify_vport_state_in_bits { 7153 u8 opcode[0x10]; 7154 u8 reserved_at_10[0x10]; 7155 7156 u8 reserved_at_20[0x10]; 7157 u8 op_mod[0x10]; 7158 7159 u8 other_vport[0x1]; 7160 u8 reserved_at_41[0xf]; 7161 u8 vport_number[0x10]; 7162 7163 u8 reserved_at_60[0x18]; 7164 u8 admin_state[0x4]; 7165 u8 reserved_at_7c[0x4]; 7166 }; 7167 7168 struct mlx5_ifc_modify_tis_out_bits { 7169 u8 status[0x8]; 7170 u8 reserved_at_8[0x18]; 7171 7172 u8 syndrome[0x20]; 7173 7174 u8 reserved_at_40[0x40]; 7175 }; 7176 7177 struct mlx5_ifc_modify_tis_bitmask_bits { 7178 u8 reserved_at_0[0x20]; 7179 7180 u8 reserved_at_20[0x1d]; 7181 u8 lag_tx_port_affinity[0x1]; 7182 u8 strict_lag_tx_port_affinity[0x1]; 7183 u8 prio[0x1]; 7184 }; 7185 7186 struct mlx5_ifc_modify_tis_in_bits { 7187 u8 opcode[0x10]; 7188 u8 uid[0x10]; 7189 7190 u8 reserved_at_20[0x10]; 7191 u8 op_mod[0x10]; 7192 7193 u8 reserved_at_40[0x8]; 7194 u8 tisn[0x18]; 7195 7196 u8 reserved_at_60[0x20]; 7197 7198 struct mlx5_ifc_modify_tis_bitmask_bits bitmask; 7199 7200 u8 reserved_at_c0[0x40]; 7201 7202 struct mlx5_ifc_tisc_bits ctx; 7203 }; 7204 7205 struct mlx5_ifc_modify_tir_bitmask_bits { 7206 u8 reserved_at_0[0x20]; 7207 7208 u8 reserved_at_20[0x1b]; 7209 u8 self_lb_en[0x1]; 7210 u8 reserved_at_3c[0x1]; 7211 u8 hash[0x1]; 7212 u8 reserved_at_3e[0x1]; 7213 u8 packet_merge[0x1]; 7214 }; 7215 7216 struct mlx5_ifc_modify_tir_out_bits { 7217 u8 status[0x8]; 7218 u8 reserved_at_8[0x18]; 7219 7220 u8 syndrome[0x20]; 7221 7222 u8 reserved_at_40[0x40]; 7223 }; 7224 7225 struct mlx5_ifc_modify_tir_in_bits { 7226 u8 opcode[0x10]; 7227 u8 uid[0x10]; 7228 7229 u8 reserved_at_20[0x10]; 7230 u8 op_mod[0x10]; 7231 7232 u8 reserved_at_40[0x8]; 7233 u8 tirn[0x18]; 7234 7235 u8 reserved_at_60[0x20]; 7236 7237 struct mlx5_ifc_modify_tir_bitmask_bits bitmask; 7238 7239 u8 reserved_at_c0[0x40]; 7240 7241 struct mlx5_ifc_tirc_bits ctx; 7242 }; 7243 7244 struct mlx5_ifc_modify_sq_out_bits { 7245 u8 status[0x8]; 7246 u8 reserved_at_8[0x18]; 7247 7248 u8 syndrome[0x20]; 7249 7250 u8 reserved_at_40[0x40]; 7251 }; 7252 7253 struct mlx5_ifc_modify_sq_in_bits { 7254 u8 opcode[0x10]; 7255 u8 uid[0x10]; 7256 7257 u8 reserved_at_20[0x10]; 7258 u8 op_mod[0x10]; 7259 7260 u8 sq_state[0x4]; 7261 u8 reserved_at_44[0x4]; 7262 u8 sqn[0x18]; 7263 7264 u8 reserved_at_60[0x20]; 7265 7266 u8 modify_bitmask[0x40]; 7267 7268 u8 reserved_at_c0[0x40]; 7269 7270 struct mlx5_ifc_sqc_bits ctx; 7271 }; 7272 7273 struct mlx5_ifc_modify_scheduling_element_out_bits { 7274 u8 status[0x8]; 7275 u8 reserved_at_8[0x18]; 7276 7277 u8 syndrome[0x20]; 7278 7279 u8 reserved_at_40[0x1c0]; 7280 }; 7281 7282 enum { 7283 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1, 7284 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2, 7285 }; 7286 7287 struct mlx5_ifc_modify_scheduling_element_in_bits { 7288 u8 opcode[0x10]; 7289 u8 reserved_at_10[0x10]; 7290 7291 u8 reserved_at_20[0x10]; 7292 u8 op_mod[0x10]; 7293 7294 u8 scheduling_hierarchy[0x8]; 7295 u8 reserved_at_48[0x18]; 7296 7297 u8 scheduling_element_id[0x20]; 7298 7299 u8 reserved_at_80[0x20]; 7300 7301 u8 modify_bitmask[0x20]; 7302 7303 u8 reserved_at_c0[0x40]; 7304 7305 struct mlx5_ifc_scheduling_context_bits scheduling_context; 7306 7307 u8 reserved_at_300[0x100]; 7308 }; 7309 7310 struct mlx5_ifc_modify_rqt_out_bits { 7311 u8 status[0x8]; 7312 u8 reserved_at_8[0x18]; 7313 7314 u8 syndrome[0x20]; 7315 7316 u8 reserved_at_40[0x40]; 7317 }; 7318 7319 struct mlx5_ifc_rqt_bitmask_bits { 7320 u8 reserved_at_0[0x20]; 7321 7322 u8 reserved_at_20[0x1f]; 7323 u8 rqn_list[0x1]; 7324 }; 7325 7326 struct mlx5_ifc_modify_rqt_in_bits { 7327 u8 opcode[0x10]; 7328 u8 uid[0x10]; 7329 7330 u8 reserved_at_20[0x10]; 7331 u8 op_mod[0x10]; 7332 7333 u8 reserved_at_40[0x8]; 7334 u8 rqtn[0x18]; 7335 7336 u8 reserved_at_60[0x20]; 7337 7338 struct mlx5_ifc_rqt_bitmask_bits bitmask; 7339 7340 u8 reserved_at_c0[0x40]; 7341 7342 struct mlx5_ifc_rqtc_bits ctx; 7343 }; 7344 7345 struct mlx5_ifc_modify_rq_out_bits { 7346 u8 status[0x8]; 7347 u8 reserved_at_8[0x18]; 7348 7349 u8 syndrome[0x20]; 7350 7351 u8 reserved_at_40[0x40]; 7352 }; 7353 7354 enum { 7355 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1, 7356 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2, 7357 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3, 7358 }; 7359 7360 struct mlx5_ifc_modify_rq_in_bits { 7361 u8 opcode[0x10]; 7362 u8 uid[0x10]; 7363 7364 u8 reserved_at_20[0x10]; 7365 u8 op_mod[0x10]; 7366 7367 u8 rq_state[0x4]; 7368 u8 reserved_at_44[0x4]; 7369 u8 rqn[0x18]; 7370 7371 u8 reserved_at_60[0x20]; 7372 7373 u8 modify_bitmask[0x40]; 7374 7375 u8 reserved_at_c0[0x40]; 7376 7377 struct mlx5_ifc_rqc_bits ctx; 7378 }; 7379 7380 struct mlx5_ifc_modify_rmp_out_bits { 7381 u8 status[0x8]; 7382 u8 reserved_at_8[0x18]; 7383 7384 u8 syndrome[0x20]; 7385 7386 u8 reserved_at_40[0x40]; 7387 }; 7388 7389 struct mlx5_ifc_rmp_bitmask_bits { 7390 u8 reserved_at_0[0x20]; 7391 7392 u8 reserved_at_20[0x1f]; 7393 u8 lwm[0x1]; 7394 }; 7395 7396 struct mlx5_ifc_modify_rmp_in_bits { 7397 u8 opcode[0x10]; 7398 u8 uid[0x10]; 7399 7400 u8 reserved_at_20[0x10]; 7401 u8 op_mod[0x10]; 7402 7403 u8 rmp_state[0x4]; 7404 u8 reserved_at_44[0x4]; 7405 u8 rmpn[0x18]; 7406 7407 u8 reserved_at_60[0x20]; 7408 7409 struct mlx5_ifc_rmp_bitmask_bits bitmask; 7410 7411 u8 reserved_at_c0[0x40]; 7412 7413 struct mlx5_ifc_rmpc_bits ctx; 7414 }; 7415 7416 struct mlx5_ifc_modify_nic_vport_context_out_bits { 7417 u8 status[0x8]; 7418 u8 reserved_at_8[0x18]; 7419 7420 u8 syndrome[0x20]; 7421 7422 u8 reserved_at_40[0x40]; 7423 }; 7424 7425 struct mlx5_ifc_modify_nic_vport_field_select_bits { 7426 u8 reserved_at_0[0x12]; 7427 u8 affiliation[0x1]; 7428 u8 reserved_at_13[0x1]; 7429 u8 disable_uc_local_lb[0x1]; 7430 u8 disable_mc_local_lb[0x1]; 7431 u8 node_guid[0x1]; 7432 u8 port_guid[0x1]; 7433 u8 min_inline[0x1]; 7434 u8 mtu[0x1]; 7435 u8 change_event[0x1]; 7436 u8 promisc[0x1]; 7437 u8 permanent_address[0x1]; 7438 u8 addresses_list[0x1]; 7439 u8 roce_en[0x1]; 7440 u8 reserved_at_1f[0x1]; 7441 }; 7442 7443 struct mlx5_ifc_modify_nic_vport_context_in_bits { 7444 u8 opcode[0x10]; 7445 u8 reserved_at_10[0x10]; 7446 7447 u8 reserved_at_20[0x10]; 7448 u8 op_mod[0x10]; 7449 7450 u8 other_vport[0x1]; 7451 u8 reserved_at_41[0xf]; 7452 u8 vport_number[0x10]; 7453 7454 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select; 7455 7456 u8 reserved_at_80[0x780]; 7457 7458 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 7459 }; 7460 7461 struct mlx5_ifc_modify_hca_vport_context_out_bits { 7462 u8 status[0x8]; 7463 u8 reserved_at_8[0x18]; 7464 7465 u8 syndrome[0x20]; 7466 7467 u8 reserved_at_40[0x40]; 7468 }; 7469 7470 struct mlx5_ifc_modify_hca_vport_context_in_bits { 7471 u8 opcode[0x10]; 7472 u8 reserved_at_10[0x10]; 7473 7474 u8 reserved_at_20[0x10]; 7475 u8 op_mod[0x10]; 7476 7477 u8 other_vport[0x1]; 7478 u8 reserved_at_41[0xb]; 7479 u8 port_num[0x4]; 7480 u8 vport_number[0x10]; 7481 7482 u8 reserved_at_60[0x20]; 7483 7484 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 7485 }; 7486 7487 struct mlx5_ifc_modify_cq_out_bits { 7488 u8 status[0x8]; 7489 u8 reserved_at_8[0x18]; 7490 7491 u8 syndrome[0x20]; 7492 7493 u8 reserved_at_40[0x40]; 7494 }; 7495 7496 enum { 7497 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0, 7498 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1, 7499 }; 7500 7501 struct mlx5_ifc_modify_cq_in_bits { 7502 u8 opcode[0x10]; 7503 u8 uid[0x10]; 7504 7505 u8 reserved_at_20[0x10]; 7506 u8 op_mod[0x10]; 7507 7508 u8 reserved_at_40[0x8]; 7509 u8 cqn[0x18]; 7510 7511 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select; 7512 7513 struct mlx5_ifc_cqc_bits cq_context; 7514 7515 u8 reserved_at_280[0x60]; 7516 7517 u8 cq_umem_valid[0x1]; 7518 u8 reserved_at_2e1[0x1f]; 7519 7520 u8 reserved_at_300[0x580]; 7521 7522 u8 pas[][0x40]; 7523 }; 7524 7525 struct mlx5_ifc_modify_cong_status_out_bits { 7526 u8 status[0x8]; 7527 u8 reserved_at_8[0x18]; 7528 7529 u8 syndrome[0x20]; 7530 7531 u8 reserved_at_40[0x40]; 7532 }; 7533 7534 struct mlx5_ifc_modify_cong_status_in_bits { 7535 u8 opcode[0x10]; 7536 u8 reserved_at_10[0x10]; 7537 7538 u8 reserved_at_20[0x10]; 7539 u8 op_mod[0x10]; 7540 7541 u8 reserved_at_40[0x18]; 7542 u8 priority[0x4]; 7543 u8 cong_protocol[0x4]; 7544 7545 u8 enable[0x1]; 7546 u8 tag_enable[0x1]; 7547 u8 reserved_at_62[0x1e]; 7548 }; 7549 7550 struct mlx5_ifc_modify_cong_params_out_bits { 7551 u8 status[0x8]; 7552 u8 reserved_at_8[0x18]; 7553 7554 u8 syndrome[0x20]; 7555 7556 u8 reserved_at_40[0x40]; 7557 }; 7558 7559 struct mlx5_ifc_modify_cong_params_in_bits { 7560 u8 opcode[0x10]; 7561 u8 reserved_at_10[0x10]; 7562 7563 u8 reserved_at_20[0x10]; 7564 u8 op_mod[0x10]; 7565 7566 u8 reserved_at_40[0x1c]; 7567 u8 cong_protocol[0x4]; 7568 7569 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select; 7570 7571 u8 reserved_at_80[0x80]; 7572 7573 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 7574 }; 7575 7576 struct mlx5_ifc_manage_pages_out_bits { 7577 u8 status[0x8]; 7578 u8 reserved_at_8[0x18]; 7579 7580 u8 syndrome[0x20]; 7581 7582 u8 output_num_entries[0x20]; 7583 7584 u8 reserved_at_60[0x20]; 7585 7586 u8 pas[][0x40]; 7587 }; 7588 7589 enum { 7590 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL = 0x0, 7591 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS = 0x1, 7592 MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES = 0x2, 7593 }; 7594 7595 struct mlx5_ifc_manage_pages_in_bits { 7596 u8 opcode[0x10]; 7597 u8 reserved_at_10[0x10]; 7598 7599 u8 reserved_at_20[0x10]; 7600 u8 op_mod[0x10]; 7601 7602 u8 embedded_cpu_function[0x1]; 7603 u8 reserved_at_41[0xf]; 7604 u8 function_id[0x10]; 7605 7606 u8 input_num_entries[0x20]; 7607 7608 u8 pas[][0x40]; 7609 }; 7610 7611 struct mlx5_ifc_mad_ifc_out_bits { 7612 u8 status[0x8]; 7613 u8 reserved_at_8[0x18]; 7614 7615 u8 syndrome[0x20]; 7616 7617 u8 reserved_at_40[0x40]; 7618 7619 u8 response_mad_packet[256][0x8]; 7620 }; 7621 7622 struct mlx5_ifc_mad_ifc_in_bits { 7623 u8 opcode[0x10]; 7624 u8 reserved_at_10[0x10]; 7625 7626 u8 reserved_at_20[0x10]; 7627 u8 op_mod[0x10]; 7628 7629 u8 remote_lid[0x10]; 7630 u8 reserved_at_50[0x8]; 7631 u8 port[0x8]; 7632 7633 u8 reserved_at_60[0x20]; 7634 7635 u8 mad[256][0x8]; 7636 }; 7637 7638 struct mlx5_ifc_init_hca_out_bits { 7639 u8 status[0x8]; 7640 u8 reserved_at_8[0x18]; 7641 7642 u8 syndrome[0x20]; 7643 7644 u8 reserved_at_40[0x40]; 7645 }; 7646 7647 struct mlx5_ifc_init_hca_in_bits { 7648 u8 opcode[0x10]; 7649 u8 reserved_at_10[0x10]; 7650 7651 u8 reserved_at_20[0x10]; 7652 u8 op_mod[0x10]; 7653 7654 u8 reserved_at_40[0x20]; 7655 7656 u8 reserved_at_60[0x2]; 7657 u8 sw_vhca_id[0xe]; 7658 u8 reserved_at_70[0x10]; 7659 7660 u8 sw_owner_id[4][0x20]; 7661 }; 7662 7663 struct mlx5_ifc_init2rtr_qp_out_bits { 7664 u8 status[0x8]; 7665 u8 reserved_at_8[0x18]; 7666 7667 u8 syndrome[0x20]; 7668 7669 u8 reserved_at_40[0x20]; 7670 u8 ece[0x20]; 7671 }; 7672 7673 struct mlx5_ifc_init2rtr_qp_in_bits { 7674 u8 opcode[0x10]; 7675 u8 uid[0x10]; 7676 7677 u8 reserved_at_20[0x10]; 7678 u8 op_mod[0x10]; 7679 7680 u8 reserved_at_40[0x8]; 7681 u8 qpn[0x18]; 7682 7683 u8 reserved_at_60[0x20]; 7684 7685 u8 opt_param_mask[0x20]; 7686 7687 u8 ece[0x20]; 7688 7689 struct mlx5_ifc_qpc_bits qpc; 7690 7691 u8 reserved_at_800[0x80]; 7692 }; 7693 7694 struct mlx5_ifc_init2init_qp_out_bits { 7695 u8 status[0x8]; 7696 u8 reserved_at_8[0x18]; 7697 7698 u8 syndrome[0x20]; 7699 7700 u8 reserved_at_40[0x20]; 7701 u8 ece[0x20]; 7702 }; 7703 7704 struct mlx5_ifc_init2init_qp_in_bits { 7705 u8 opcode[0x10]; 7706 u8 uid[0x10]; 7707 7708 u8 reserved_at_20[0x10]; 7709 u8 op_mod[0x10]; 7710 7711 u8 reserved_at_40[0x8]; 7712 u8 qpn[0x18]; 7713 7714 u8 reserved_at_60[0x20]; 7715 7716 u8 opt_param_mask[0x20]; 7717 7718 u8 ece[0x20]; 7719 7720 struct mlx5_ifc_qpc_bits qpc; 7721 7722 u8 reserved_at_800[0x80]; 7723 }; 7724 7725 struct mlx5_ifc_get_dropped_packet_log_out_bits { 7726 u8 status[0x8]; 7727 u8 reserved_at_8[0x18]; 7728 7729 u8 syndrome[0x20]; 7730 7731 u8 reserved_at_40[0x40]; 7732 7733 u8 packet_headers_log[128][0x8]; 7734 7735 u8 packet_syndrome[64][0x8]; 7736 }; 7737 7738 struct mlx5_ifc_get_dropped_packet_log_in_bits { 7739 u8 opcode[0x10]; 7740 u8 reserved_at_10[0x10]; 7741 7742 u8 reserved_at_20[0x10]; 7743 u8 op_mod[0x10]; 7744 7745 u8 reserved_at_40[0x40]; 7746 }; 7747 7748 struct mlx5_ifc_gen_eqe_in_bits { 7749 u8 opcode[0x10]; 7750 u8 reserved_at_10[0x10]; 7751 7752 u8 reserved_at_20[0x10]; 7753 u8 op_mod[0x10]; 7754 7755 u8 reserved_at_40[0x18]; 7756 u8 eq_number[0x8]; 7757 7758 u8 reserved_at_60[0x20]; 7759 7760 u8 eqe[64][0x8]; 7761 }; 7762 7763 struct mlx5_ifc_gen_eq_out_bits { 7764 u8 status[0x8]; 7765 u8 reserved_at_8[0x18]; 7766 7767 u8 syndrome[0x20]; 7768 7769 u8 reserved_at_40[0x40]; 7770 }; 7771 7772 struct mlx5_ifc_enable_hca_out_bits { 7773 u8 status[0x8]; 7774 u8 reserved_at_8[0x18]; 7775 7776 u8 syndrome[0x20]; 7777 7778 u8 reserved_at_40[0x20]; 7779 }; 7780 7781 struct mlx5_ifc_enable_hca_in_bits { 7782 u8 opcode[0x10]; 7783 u8 reserved_at_10[0x10]; 7784 7785 u8 reserved_at_20[0x10]; 7786 u8 op_mod[0x10]; 7787 7788 u8 embedded_cpu_function[0x1]; 7789 u8 reserved_at_41[0xf]; 7790 u8 function_id[0x10]; 7791 7792 u8 reserved_at_60[0x20]; 7793 }; 7794 7795 struct mlx5_ifc_drain_dct_out_bits { 7796 u8 status[0x8]; 7797 u8 reserved_at_8[0x18]; 7798 7799 u8 syndrome[0x20]; 7800 7801 u8 reserved_at_40[0x40]; 7802 }; 7803 7804 struct mlx5_ifc_drain_dct_in_bits { 7805 u8 opcode[0x10]; 7806 u8 uid[0x10]; 7807 7808 u8 reserved_at_20[0x10]; 7809 u8 op_mod[0x10]; 7810 7811 u8 reserved_at_40[0x8]; 7812 u8 dctn[0x18]; 7813 7814 u8 reserved_at_60[0x20]; 7815 }; 7816 7817 struct mlx5_ifc_disable_hca_out_bits { 7818 u8 status[0x8]; 7819 u8 reserved_at_8[0x18]; 7820 7821 u8 syndrome[0x20]; 7822 7823 u8 reserved_at_40[0x20]; 7824 }; 7825 7826 struct mlx5_ifc_disable_hca_in_bits { 7827 u8 opcode[0x10]; 7828 u8 reserved_at_10[0x10]; 7829 7830 u8 reserved_at_20[0x10]; 7831 u8 op_mod[0x10]; 7832 7833 u8 embedded_cpu_function[0x1]; 7834 u8 reserved_at_41[0xf]; 7835 u8 function_id[0x10]; 7836 7837 u8 reserved_at_60[0x20]; 7838 }; 7839 7840 struct mlx5_ifc_detach_from_mcg_out_bits { 7841 u8 status[0x8]; 7842 u8 reserved_at_8[0x18]; 7843 7844 u8 syndrome[0x20]; 7845 7846 u8 reserved_at_40[0x40]; 7847 }; 7848 7849 struct mlx5_ifc_detach_from_mcg_in_bits { 7850 u8 opcode[0x10]; 7851 u8 uid[0x10]; 7852 7853 u8 reserved_at_20[0x10]; 7854 u8 op_mod[0x10]; 7855 7856 u8 reserved_at_40[0x8]; 7857 u8 qpn[0x18]; 7858 7859 u8 reserved_at_60[0x20]; 7860 7861 u8 multicast_gid[16][0x8]; 7862 }; 7863 7864 struct mlx5_ifc_destroy_xrq_out_bits { 7865 u8 status[0x8]; 7866 u8 reserved_at_8[0x18]; 7867 7868 u8 syndrome[0x20]; 7869 7870 u8 reserved_at_40[0x40]; 7871 }; 7872 7873 struct mlx5_ifc_destroy_xrq_in_bits { 7874 u8 opcode[0x10]; 7875 u8 uid[0x10]; 7876 7877 u8 reserved_at_20[0x10]; 7878 u8 op_mod[0x10]; 7879 7880 u8 reserved_at_40[0x8]; 7881 u8 xrqn[0x18]; 7882 7883 u8 reserved_at_60[0x20]; 7884 }; 7885 7886 struct mlx5_ifc_destroy_xrc_srq_out_bits { 7887 u8 status[0x8]; 7888 u8 reserved_at_8[0x18]; 7889 7890 u8 syndrome[0x20]; 7891 7892 u8 reserved_at_40[0x40]; 7893 }; 7894 7895 struct mlx5_ifc_destroy_xrc_srq_in_bits { 7896 u8 opcode[0x10]; 7897 u8 uid[0x10]; 7898 7899 u8 reserved_at_20[0x10]; 7900 u8 op_mod[0x10]; 7901 7902 u8 reserved_at_40[0x8]; 7903 u8 xrc_srqn[0x18]; 7904 7905 u8 reserved_at_60[0x20]; 7906 }; 7907 7908 struct mlx5_ifc_destroy_tis_out_bits { 7909 u8 status[0x8]; 7910 u8 reserved_at_8[0x18]; 7911 7912 u8 syndrome[0x20]; 7913 7914 u8 reserved_at_40[0x40]; 7915 }; 7916 7917 struct mlx5_ifc_destroy_tis_in_bits { 7918 u8 opcode[0x10]; 7919 u8 uid[0x10]; 7920 7921 u8 reserved_at_20[0x10]; 7922 u8 op_mod[0x10]; 7923 7924 u8 reserved_at_40[0x8]; 7925 u8 tisn[0x18]; 7926 7927 u8 reserved_at_60[0x20]; 7928 }; 7929 7930 struct mlx5_ifc_destroy_tir_out_bits { 7931 u8 status[0x8]; 7932 u8 reserved_at_8[0x18]; 7933 7934 u8 syndrome[0x20]; 7935 7936 u8 reserved_at_40[0x40]; 7937 }; 7938 7939 struct mlx5_ifc_destroy_tir_in_bits { 7940 u8 opcode[0x10]; 7941 u8 uid[0x10]; 7942 7943 u8 reserved_at_20[0x10]; 7944 u8 op_mod[0x10]; 7945 7946 u8 reserved_at_40[0x8]; 7947 u8 tirn[0x18]; 7948 7949 u8 reserved_at_60[0x20]; 7950 }; 7951 7952 struct mlx5_ifc_destroy_srq_out_bits { 7953 u8 status[0x8]; 7954 u8 reserved_at_8[0x18]; 7955 7956 u8 syndrome[0x20]; 7957 7958 u8 reserved_at_40[0x40]; 7959 }; 7960 7961 struct mlx5_ifc_destroy_srq_in_bits { 7962 u8 opcode[0x10]; 7963 u8 uid[0x10]; 7964 7965 u8 reserved_at_20[0x10]; 7966 u8 op_mod[0x10]; 7967 7968 u8 reserved_at_40[0x8]; 7969 u8 srqn[0x18]; 7970 7971 u8 reserved_at_60[0x20]; 7972 }; 7973 7974 struct mlx5_ifc_destroy_sq_out_bits { 7975 u8 status[0x8]; 7976 u8 reserved_at_8[0x18]; 7977 7978 u8 syndrome[0x20]; 7979 7980 u8 reserved_at_40[0x40]; 7981 }; 7982 7983 struct mlx5_ifc_destroy_sq_in_bits { 7984 u8 opcode[0x10]; 7985 u8 uid[0x10]; 7986 7987 u8 reserved_at_20[0x10]; 7988 u8 op_mod[0x10]; 7989 7990 u8 reserved_at_40[0x8]; 7991 u8 sqn[0x18]; 7992 7993 u8 reserved_at_60[0x20]; 7994 }; 7995 7996 struct mlx5_ifc_destroy_scheduling_element_out_bits { 7997 u8 status[0x8]; 7998 u8 reserved_at_8[0x18]; 7999 8000 u8 syndrome[0x20]; 8001 8002 u8 reserved_at_40[0x1c0]; 8003 }; 8004 8005 struct mlx5_ifc_destroy_scheduling_element_in_bits { 8006 u8 opcode[0x10]; 8007 u8 reserved_at_10[0x10]; 8008 8009 u8 reserved_at_20[0x10]; 8010 u8 op_mod[0x10]; 8011 8012 u8 scheduling_hierarchy[0x8]; 8013 u8 reserved_at_48[0x18]; 8014 8015 u8 scheduling_element_id[0x20]; 8016 8017 u8 reserved_at_80[0x180]; 8018 }; 8019 8020 struct mlx5_ifc_destroy_rqt_out_bits { 8021 u8 status[0x8]; 8022 u8 reserved_at_8[0x18]; 8023 8024 u8 syndrome[0x20]; 8025 8026 u8 reserved_at_40[0x40]; 8027 }; 8028 8029 struct mlx5_ifc_destroy_rqt_in_bits { 8030 u8 opcode[0x10]; 8031 u8 uid[0x10]; 8032 8033 u8 reserved_at_20[0x10]; 8034 u8 op_mod[0x10]; 8035 8036 u8 reserved_at_40[0x8]; 8037 u8 rqtn[0x18]; 8038 8039 u8 reserved_at_60[0x20]; 8040 }; 8041 8042 struct mlx5_ifc_destroy_rq_out_bits { 8043 u8 status[0x8]; 8044 u8 reserved_at_8[0x18]; 8045 8046 u8 syndrome[0x20]; 8047 8048 u8 reserved_at_40[0x40]; 8049 }; 8050 8051 struct mlx5_ifc_destroy_rq_in_bits { 8052 u8 opcode[0x10]; 8053 u8 uid[0x10]; 8054 8055 u8 reserved_at_20[0x10]; 8056 u8 op_mod[0x10]; 8057 8058 u8 reserved_at_40[0x8]; 8059 u8 rqn[0x18]; 8060 8061 u8 reserved_at_60[0x20]; 8062 }; 8063 8064 struct mlx5_ifc_set_delay_drop_params_in_bits { 8065 u8 opcode[0x10]; 8066 u8 reserved_at_10[0x10]; 8067 8068 u8 reserved_at_20[0x10]; 8069 u8 op_mod[0x10]; 8070 8071 u8 reserved_at_40[0x20]; 8072 8073 u8 reserved_at_60[0x10]; 8074 u8 delay_drop_timeout[0x10]; 8075 }; 8076 8077 struct mlx5_ifc_set_delay_drop_params_out_bits { 8078 u8 status[0x8]; 8079 u8 reserved_at_8[0x18]; 8080 8081 u8 syndrome[0x20]; 8082 8083 u8 reserved_at_40[0x40]; 8084 }; 8085 8086 struct mlx5_ifc_destroy_rmp_out_bits { 8087 u8 status[0x8]; 8088 u8 reserved_at_8[0x18]; 8089 8090 u8 syndrome[0x20]; 8091 8092 u8 reserved_at_40[0x40]; 8093 }; 8094 8095 struct mlx5_ifc_destroy_rmp_in_bits { 8096 u8 opcode[0x10]; 8097 u8 uid[0x10]; 8098 8099 u8 reserved_at_20[0x10]; 8100 u8 op_mod[0x10]; 8101 8102 u8 reserved_at_40[0x8]; 8103 u8 rmpn[0x18]; 8104 8105 u8 reserved_at_60[0x20]; 8106 }; 8107 8108 struct mlx5_ifc_destroy_qp_out_bits { 8109 u8 status[0x8]; 8110 u8 reserved_at_8[0x18]; 8111 8112 u8 syndrome[0x20]; 8113 8114 u8 reserved_at_40[0x40]; 8115 }; 8116 8117 struct mlx5_ifc_destroy_qp_in_bits { 8118 u8 opcode[0x10]; 8119 u8 uid[0x10]; 8120 8121 u8 reserved_at_20[0x10]; 8122 u8 op_mod[0x10]; 8123 8124 u8 reserved_at_40[0x8]; 8125 u8 qpn[0x18]; 8126 8127 u8 reserved_at_60[0x20]; 8128 }; 8129 8130 struct mlx5_ifc_destroy_psv_out_bits { 8131 u8 status[0x8]; 8132 u8 reserved_at_8[0x18]; 8133 8134 u8 syndrome[0x20]; 8135 8136 u8 reserved_at_40[0x40]; 8137 }; 8138 8139 struct mlx5_ifc_destroy_psv_in_bits { 8140 u8 opcode[0x10]; 8141 u8 reserved_at_10[0x10]; 8142 8143 u8 reserved_at_20[0x10]; 8144 u8 op_mod[0x10]; 8145 8146 u8 reserved_at_40[0x8]; 8147 u8 psvn[0x18]; 8148 8149 u8 reserved_at_60[0x20]; 8150 }; 8151 8152 struct mlx5_ifc_destroy_mkey_out_bits { 8153 u8 status[0x8]; 8154 u8 reserved_at_8[0x18]; 8155 8156 u8 syndrome[0x20]; 8157 8158 u8 reserved_at_40[0x40]; 8159 }; 8160 8161 struct mlx5_ifc_destroy_mkey_in_bits { 8162 u8 opcode[0x10]; 8163 u8 uid[0x10]; 8164 8165 u8 reserved_at_20[0x10]; 8166 u8 op_mod[0x10]; 8167 8168 u8 reserved_at_40[0x8]; 8169 u8 mkey_index[0x18]; 8170 8171 u8 reserved_at_60[0x20]; 8172 }; 8173 8174 struct mlx5_ifc_destroy_flow_table_out_bits { 8175 u8 status[0x8]; 8176 u8 reserved_at_8[0x18]; 8177 8178 u8 syndrome[0x20]; 8179 8180 u8 reserved_at_40[0x40]; 8181 }; 8182 8183 struct mlx5_ifc_destroy_flow_table_in_bits { 8184 u8 opcode[0x10]; 8185 u8 reserved_at_10[0x10]; 8186 8187 u8 reserved_at_20[0x10]; 8188 u8 op_mod[0x10]; 8189 8190 u8 other_vport[0x1]; 8191 u8 reserved_at_41[0xf]; 8192 u8 vport_number[0x10]; 8193 8194 u8 reserved_at_60[0x20]; 8195 8196 u8 table_type[0x8]; 8197 u8 reserved_at_88[0x18]; 8198 8199 u8 reserved_at_a0[0x8]; 8200 u8 table_id[0x18]; 8201 8202 u8 reserved_at_c0[0x140]; 8203 }; 8204 8205 struct mlx5_ifc_destroy_flow_group_out_bits { 8206 u8 status[0x8]; 8207 u8 reserved_at_8[0x18]; 8208 8209 u8 syndrome[0x20]; 8210 8211 u8 reserved_at_40[0x40]; 8212 }; 8213 8214 struct mlx5_ifc_destroy_flow_group_in_bits { 8215 u8 opcode[0x10]; 8216 u8 reserved_at_10[0x10]; 8217 8218 u8 reserved_at_20[0x10]; 8219 u8 op_mod[0x10]; 8220 8221 u8 other_vport[0x1]; 8222 u8 reserved_at_41[0xf]; 8223 u8 vport_number[0x10]; 8224 8225 u8 reserved_at_60[0x20]; 8226 8227 u8 table_type[0x8]; 8228 u8 reserved_at_88[0x18]; 8229 8230 u8 reserved_at_a0[0x8]; 8231 u8 table_id[0x18]; 8232 8233 u8 group_id[0x20]; 8234 8235 u8 reserved_at_e0[0x120]; 8236 }; 8237 8238 struct mlx5_ifc_destroy_eq_out_bits { 8239 u8 status[0x8]; 8240 u8 reserved_at_8[0x18]; 8241 8242 u8 syndrome[0x20]; 8243 8244 u8 reserved_at_40[0x40]; 8245 }; 8246 8247 struct mlx5_ifc_destroy_eq_in_bits { 8248 u8 opcode[0x10]; 8249 u8 reserved_at_10[0x10]; 8250 8251 u8 reserved_at_20[0x10]; 8252 u8 op_mod[0x10]; 8253 8254 u8 reserved_at_40[0x18]; 8255 u8 eq_number[0x8]; 8256 8257 u8 reserved_at_60[0x20]; 8258 }; 8259 8260 struct mlx5_ifc_destroy_dct_out_bits { 8261 u8 status[0x8]; 8262 u8 reserved_at_8[0x18]; 8263 8264 u8 syndrome[0x20]; 8265 8266 u8 reserved_at_40[0x40]; 8267 }; 8268 8269 struct mlx5_ifc_destroy_dct_in_bits { 8270 u8 opcode[0x10]; 8271 u8 uid[0x10]; 8272 8273 u8 reserved_at_20[0x10]; 8274 u8 op_mod[0x10]; 8275 8276 u8 reserved_at_40[0x8]; 8277 u8 dctn[0x18]; 8278 8279 u8 reserved_at_60[0x20]; 8280 }; 8281 8282 struct mlx5_ifc_destroy_cq_out_bits { 8283 u8 status[0x8]; 8284 u8 reserved_at_8[0x18]; 8285 8286 u8 syndrome[0x20]; 8287 8288 u8 reserved_at_40[0x40]; 8289 }; 8290 8291 struct mlx5_ifc_destroy_cq_in_bits { 8292 u8 opcode[0x10]; 8293 u8 uid[0x10]; 8294 8295 u8 reserved_at_20[0x10]; 8296 u8 op_mod[0x10]; 8297 8298 u8 reserved_at_40[0x8]; 8299 u8 cqn[0x18]; 8300 8301 u8 reserved_at_60[0x20]; 8302 }; 8303 8304 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits { 8305 u8 status[0x8]; 8306 u8 reserved_at_8[0x18]; 8307 8308 u8 syndrome[0x20]; 8309 8310 u8 reserved_at_40[0x40]; 8311 }; 8312 8313 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits { 8314 u8 opcode[0x10]; 8315 u8 reserved_at_10[0x10]; 8316 8317 u8 reserved_at_20[0x10]; 8318 u8 op_mod[0x10]; 8319 8320 u8 reserved_at_40[0x20]; 8321 8322 u8 reserved_at_60[0x10]; 8323 u8 vxlan_udp_port[0x10]; 8324 }; 8325 8326 struct mlx5_ifc_delete_l2_table_entry_out_bits { 8327 u8 status[0x8]; 8328 u8 reserved_at_8[0x18]; 8329 8330 u8 syndrome[0x20]; 8331 8332 u8 reserved_at_40[0x40]; 8333 }; 8334 8335 struct mlx5_ifc_delete_l2_table_entry_in_bits { 8336 u8 opcode[0x10]; 8337 u8 reserved_at_10[0x10]; 8338 8339 u8 reserved_at_20[0x10]; 8340 u8 op_mod[0x10]; 8341 8342 u8 reserved_at_40[0x60]; 8343 8344 u8 reserved_at_a0[0x8]; 8345 u8 table_index[0x18]; 8346 8347 u8 reserved_at_c0[0x140]; 8348 }; 8349 8350 struct mlx5_ifc_delete_fte_out_bits { 8351 u8 status[0x8]; 8352 u8 reserved_at_8[0x18]; 8353 8354 u8 syndrome[0x20]; 8355 8356 u8 reserved_at_40[0x40]; 8357 }; 8358 8359 struct mlx5_ifc_delete_fte_in_bits { 8360 u8 opcode[0x10]; 8361 u8 reserved_at_10[0x10]; 8362 8363 u8 reserved_at_20[0x10]; 8364 u8 op_mod[0x10]; 8365 8366 u8 other_vport[0x1]; 8367 u8 reserved_at_41[0xf]; 8368 u8 vport_number[0x10]; 8369 8370 u8 reserved_at_60[0x20]; 8371 8372 u8 table_type[0x8]; 8373 u8 reserved_at_88[0x18]; 8374 8375 u8 reserved_at_a0[0x8]; 8376 u8 table_id[0x18]; 8377 8378 u8 reserved_at_c0[0x40]; 8379 8380 u8 flow_index[0x20]; 8381 8382 u8 reserved_at_120[0xe0]; 8383 }; 8384 8385 struct mlx5_ifc_dealloc_xrcd_out_bits { 8386 u8 status[0x8]; 8387 u8 reserved_at_8[0x18]; 8388 8389 u8 syndrome[0x20]; 8390 8391 u8 reserved_at_40[0x40]; 8392 }; 8393 8394 struct mlx5_ifc_dealloc_xrcd_in_bits { 8395 u8 opcode[0x10]; 8396 u8 uid[0x10]; 8397 8398 u8 reserved_at_20[0x10]; 8399 u8 op_mod[0x10]; 8400 8401 u8 reserved_at_40[0x8]; 8402 u8 xrcd[0x18]; 8403 8404 u8 reserved_at_60[0x20]; 8405 }; 8406 8407 struct mlx5_ifc_dealloc_uar_out_bits { 8408 u8 status[0x8]; 8409 u8 reserved_at_8[0x18]; 8410 8411 u8 syndrome[0x20]; 8412 8413 u8 reserved_at_40[0x40]; 8414 }; 8415 8416 struct mlx5_ifc_dealloc_uar_in_bits { 8417 u8 opcode[0x10]; 8418 u8 uid[0x10]; 8419 8420 u8 reserved_at_20[0x10]; 8421 u8 op_mod[0x10]; 8422 8423 u8 reserved_at_40[0x8]; 8424 u8 uar[0x18]; 8425 8426 u8 reserved_at_60[0x20]; 8427 }; 8428 8429 struct mlx5_ifc_dealloc_transport_domain_out_bits { 8430 u8 status[0x8]; 8431 u8 reserved_at_8[0x18]; 8432 8433 u8 syndrome[0x20]; 8434 8435 u8 reserved_at_40[0x40]; 8436 }; 8437 8438 struct mlx5_ifc_dealloc_transport_domain_in_bits { 8439 u8 opcode[0x10]; 8440 u8 uid[0x10]; 8441 8442 u8 reserved_at_20[0x10]; 8443 u8 op_mod[0x10]; 8444 8445 u8 reserved_at_40[0x8]; 8446 u8 transport_domain[0x18]; 8447 8448 u8 reserved_at_60[0x20]; 8449 }; 8450 8451 struct mlx5_ifc_dealloc_q_counter_out_bits { 8452 u8 status[0x8]; 8453 u8 reserved_at_8[0x18]; 8454 8455 u8 syndrome[0x20]; 8456 8457 u8 reserved_at_40[0x40]; 8458 }; 8459 8460 struct mlx5_ifc_dealloc_q_counter_in_bits { 8461 u8 opcode[0x10]; 8462 u8 reserved_at_10[0x10]; 8463 8464 u8 reserved_at_20[0x10]; 8465 u8 op_mod[0x10]; 8466 8467 u8 reserved_at_40[0x18]; 8468 u8 counter_set_id[0x8]; 8469 8470 u8 reserved_at_60[0x20]; 8471 }; 8472 8473 struct mlx5_ifc_dealloc_pd_out_bits { 8474 u8 status[0x8]; 8475 u8 reserved_at_8[0x18]; 8476 8477 u8 syndrome[0x20]; 8478 8479 u8 reserved_at_40[0x40]; 8480 }; 8481 8482 struct mlx5_ifc_dealloc_pd_in_bits { 8483 u8 opcode[0x10]; 8484 u8 uid[0x10]; 8485 8486 u8 reserved_at_20[0x10]; 8487 u8 op_mod[0x10]; 8488 8489 u8 reserved_at_40[0x8]; 8490 u8 pd[0x18]; 8491 8492 u8 reserved_at_60[0x20]; 8493 }; 8494 8495 struct mlx5_ifc_dealloc_flow_counter_out_bits { 8496 u8 status[0x8]; 8497 u8 reserved_at_8[0x18]; 8498 8499 u8 syndrome[0x20]; 8500 8501 u8 reserved_at_40[0x40]; 8502 }; 8503 8504 struct mlx5_ifc_dealloc_flow_counter_in_bits { 8505 u8 opcode[0x10]; 8506 u8 reserved_at_10[0x10]; 8507 8508 u8 reserved_at_20[0x10]; 8509 u8 op_mod[0x10]; 8510 8511 u8 flow_counter_id[0x20]; 8512 8513 u8 reserved_at_60[0x20]; 8514 }; 8515 8516 struct mlx5_ifc_create_xrq_out_bits { 8517 u8 status[0x8]; 8518 u8 reserved_at_8[0x18]; 8519 8520 u8 syndrome[0x20]; 8521 8522 u8 reserved_at_40[0x8]; 8523 u8 xrqn[0x18]; 8524 8525 u8 reserved_at_60[0x20]; 8526 }; 8527 8528 struct mlx5_ifc_create_xrq_in_bits { 8529 u8 opcode[0x10]; 8530 u8 uid[0x10]; 8531 8532 u8 reserved_at_20[0x10]; 8533 u8 op_mod[0x10]; 8534 8535 u8 reserved_at_40[0x40]; 8536 8537 struct mlx5_ifc_xrqc_bits xrq_context; 8538 }; 8539 8540 struct mlx5_ifc_create_xrc_srq_out_bits { 8541 u8 status[0x8]; 8542 u8 reserved_at_8[0x18]; 8543 8544 u8 syndrome[0x20]; 8545 8546 u8 reserved_at_40[0x8]; 8547 u8 xrc_srqn[0x18]; 8548 8549 u8 reserved_at_60[0x20]; 8550 }; 8551 8552 struct mlx5_ifc_create_xrc_srq_in_bits { 8553 u8 opcode[0x10]; 8554 u8 uid[0x10]; 8555 8556 u8 reserved_at_20[0x10]; 8557 u8 op_mod[0x10]; 8558 8559 u8 reserved_at_40[0x40]; 8560 8561 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 8562 8563 u8 reserved_at_280[0x60]; 8564 8565 u8 xrc_srq_umem_valid[0x1]; 8566 u8 reserved_at_2e1[0x1f]; 8567 8568 u8 reserved_at_300[0x580]; 8569 8570 u8 pas[][0x40]; 8571 }; 8572 8573 struct mlx5_ifc_create_tis_out_bits { 8574 u8 status[0x8]; 8575 u8 reserved_at_8[0x18]; 8576 8577 u8 syndrome[0x20]; 8578 8579 u8 reserved_at_40[0x8]; 8580 u8 tisn[0x18]; 8581 8582 u8 reserved_at_60[0x20]; 8583 }; 8584 8585 struct mlx5_ifc_create_tis_in_bits { 8586 u8 opcode[0x10]; 8587 u8 uid[0x10]; 8588 8589 u8 reserved_at_20[0x10]; 8590 u8 op_mod[0x10]; 8591 8592 u8 reserved_at_40[0xc0]; 8593 8594 struct mlx5_ifc_tisc_bits ctx; 8595 }; 8596 8597 struct mlx5_ifc_create_tir_out_bits { 8598 u8 status[0x8]; 8599 u8 icm_address_63_40[0x18]; 8600 8601 u8 syndrome[0x20]; 8602 8603 u8 icm_address_39_32[0x8]; 8604 u8 tirn[0x18]; 8605 8606 u8 icm_address_31_0[0x20]; 8607 }; 8608 8609 struct mlx5_ifc_create_tir_in_bits { 8610 u8 opcode[0x10]; 8611 u8 uid[0x10]; 8612 8613 u8 reserved_at_20[0x10]; 8614 u8 op_mod[0x10]; 8615 8616 u8 reserved_at_40[0xc0]; 8617 8618 struct mlx5_ifc_tirc_bits ctx; 8619 }; 8620 8621 struct mlx5_ifc_create_srq_out_bits { 8622 u8 status[0x8]; 8623 u8 reserved_at_8[0x18]; 8624 8625 u8 syndrome[0x20]; 8626 8627 u8 reserved_at_40[0x8]; 8628 u8 srqn[0x18]; 8629 8630 u8 reserved_at_60[0x20]; 8631 }; 8632 8633 struct mlx5_ifc_create_srq_in_bits { 8634 u8 opcode[0x10]; 8635 u8 uid[0x10]; 8636 8637 u8 reserved_at_20[0x10]; 8638 u8 op_mod[0x10]; 8639 8640 u8 reserved_at_40[0x40]; 8641 8642 struct mlx5_ifc_srqc_bits srq_context_entry; 8643 8644 u8 reserved_at_280[0x600]; 8645 8646 u8 pas[][0x40]; 8647 }; 8648 8649 struct mlx5_ifc_create_sq_out_bits { 8650 u8 status[0x8]; 8651 u8 reserved_at_8[0x18]; 8652 8653 u8 syndrome[0x20]; 8654 8655 u8 reserved_at_40[0x8]; 8656 u8 sqn[0x18]; 8657 8658 u8 reserved_at_60[0x20]; 8659 }; 8660 8661 struct mlx5_ifc_create_sq_in_bits { 8662 u8 opcode[0x10]; 8663 u8 uid[0x10]; 8664 8665 u8 reserved_at_20[0x10]; 8666 u8 op_mod[0x10]; 8667 8668 u8 reserved_at_40[0xc0]; 8669 8670 struct mlx5_ifc_sqc_bits ctx; 8671 }; 8672 8673 struct mlx5_ifc_create_scheduling_element_out_bits { 8674 u8 status[0x8]; 8675 u8 reserved_at_8[0x18]; 8676 8677 u8 syndrome[0x20]; 8678 8679 u8 reserved_at_40[0x40]; 8680 8681 u8 scheduling_element_id[0x20]; 8682 8683 u8 reserved_at_a0[0x160]; 8684 }; 8685 8686 struct mlx5_ifc_create_scheduling_element_in_bits { 8687 u8 opcode[0x10]; 8688 u8 reserved_at_10[0x10]; 8689 8690 u8 reserved_at_20[0x10]; 8691 u8 op_mod[0x10]; 8692 8693 u8 scheduling_hierarchy[0x8]; 8694 u8 reserved_at_48[0x18]; 8695 8696 u8 reserved_at_60[0xa0]; 8697 8698 struct mlx5_ifc_scheduling_context_bits scheduling_context; 8699 8700 u8 reserved_at_300[0x100]; 8701 }; 8702 8703 struct mlx5_ifc_create_rqt_out_bits { 8704 u8 status[0x8]; 8705 u8 reserved_at_8[0x18]; 8706 8707 u8 syndrome[0x20]; 8708 8709 u8 reserved_at_40[0x8]; 8710 u8 rqtn[0x18]; 8711 8712 u8 reserved_at_60[0x20]; 8713 }; 8714 8715 struct mlx5_ifc_create_rqt_in_bits { 8716 u8 opcode[0x10]; 8717 u8 uid[0x10]; 8718 8719 u8 reserved_at_20[0x10]; 8720 u8 op_mod[0x10]; 8721 8722 u8 reserved_at_40[0xc0]; 8723 8724 struct mlx5_ifc_rqtc_bits rqt_context; 8725 }; 8726 8727 struct mlx5_ifc_create_rq_out_bits { 8728 u8 status[0x8]; 8729 u8 reserved_at_8[0x18]; 8730 8731 u8 syndrome[0x20]; 8732 8733 u8 reserved_at_40[0x8]; 8734 u8 rqn[0x18]; 8735 8736 u8 reserved_at_60[0x20]; 8737 }; 8738 8739 struct mlx5_ifc_create_rq_in_bits { 8740 u8 opcode[0x10]; 8741 u8 uid[0x10]; 8742 8743 u8 reserved_at_20[0x10]; 8744 u8 op_mod[0x10]; 8745 8746 u8 reserved_at_40[0xc0]; 8747 8748 struct mlx5_ifc_rqc_bits ctx; 8749 }; 8750 8751 struct mlx5_ifc_create_rmp_out_bits { 8752 u8 status[0x8]; 8753 u8 reserved_at_8[0x18]; 8754 8755 u8 syndrome[0x20]; 8756 8757 u8 reserved_at_40[0x8]; 8758 u8 rmpn[0x18]; 8759 8760 u8 reserved_at_60[0x20]; 8761 }; 8762 8763 struct mlx5_ifc_create_rmp_in_bits { 8764 u8 opcode[0x10]; 8765 u8 uid[0x10]; 8766 8767 u8 reserved_at_20[0x10]; 8768 u8 op_mod[0x10]; 8769 8770 u8 reserved_at_40[0xc0]; 8771 8772 struct mlx5_ifc_rmpc_bits ctx; 8773 }; 8774 8775 struct mlx5_ifc_create_qp_out_bits { 8776 u8 status[0x8]; 8777 u8 reserved_at_8[0x18]; 8778 8779 u8 syndrome[0x20]; 8780 8781 u8 reserved_at_40[0x8]; 8782 u8 qpn[0x18]; 8783 8784 u8 ece[0x20]; 8785 }; 8786 8787 struct mlx5_ifc_create_qp_in_bits { 8788 u8 opcode[0x10]; 8789 u8 uid[0x10]; 8790 8791 u8 reserved_at_20[0x10]; 8792 u8 op_mod[0x10]; 8793 8794 u8 qpc_ext[0x1]; 8795 u8 reserved_at_41[0x7]; 8796 u8 input_qpn[0x18]; 8797 8798 u8 reserved_at_60[0x20]; 8799 u8 opt_param_mask[0x20]; 8800 8801 u8 ece[0x20]; 8802 8803 struct mlx5_ifc_qpc_bits qpc; 8804 8805 u8 reserved_at_800[0x60]; 8806 8807 u8 wq_umem_valid[0x1]; 8808 u8 reserved_at_861[0x1f]; 8809 8810 u8 pas[][0x40]; 8811 }; 8812 8813 struct mlx5_ifc_create_psv_out_bits { 8814 u8 status[0x8]; 8815 u8 reserved_at_8[0x18]; 8816 8817 u8 syndrome[0x20]; 8818 8819 u8 reserved_at_40[0x40]; 8820 8821 u8 reserved_at_80[0x8]; 8822 u8 psv0_index[0x18]; 8823 8824 u8 reserved_at_a0[0x8]; 8825 u8 psv1_index[0x18]; 8826 8827 u8 reserved_at_c0[0x8]; 8828 u8 psv2_index[0x18]; 8829 8830 u8 reserved_at_e0[0x8]; 8831 u8 psv3_index[0x18]; 8832 }; 8833 8834 struct mlx5_ifc_create_psv_in_bits { 8835 u8 opcode[0x10]; 8836 u8 reserved_at_10[0x10]; 8837 8838 u8 reserved_at_20[0x10]; 8839 u8 op_mod[0x10]; 8840 8841 u8 num_psv[0x4]; 8842 u8 reserved_at_44[0x4]; 8843 u8 pd[0x18]; 8844 8845 u8 reserved_at_60[0x20]; 8846 }; 8847 8848 struct mlx5_ifc_create_mkey_out_bits { 8849 u8 status[0x8]; 8850 u8 reserved_at_8[0x18]; 8851 8852 u8 syndrome[0x20]; 8853 8854 u8 reserved_at_40[0x8]; 8855 u8 mkey_index[0x18]; 8856 8857 u8 reserved_at_60[0x20]; 8858 }; 8859 8860 struct mlx5_ifc_create_mkey_in_bits { 8861 u8 opcode[0x10]; 8862 u8 uid[0x10]; 8863 8864 u8 reserved_at_20[0x10]; 8865 u8 op_mod[0x10]; 8866 8867 u8 reserved_at_40[0x20]; 8868 8869 u8 pg_access[0x1]; 8870 u8 mkey_umem_valid[0x1]; 8871 u8 reserved_at_62[0x1e]; 8872 8873 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 8874 8875 u8 reserved_at_280[0x80]; 8876 8877 u8 translations_octword_actual_size[0x20]; 8878 8879 u8 reserved_at_320[0x560]; 8880 8881 u8 klm_pas_mtt[][0x20]; 8882 }; 8883 8884 enum { 8885 MLX5_FLOW_TABLE_TYPE_NIC_RX = 0x0, 8886 MLX5_FLOW_TABLE_TYPE_NIC_TX = 0x1, 8887 MLX5_FLOW_TABLE_TYPE_ESW_EGRESS_ACL = 0x2, 8888 MLX5_FLOW_TABLE_TYPE_ESW_INGRESS_ACL = 0x3, 8889 MLX5_FLOW_TABLE_TYPE_FDB = 0X4, 8890 MLX5_FLOW_TABLE_TYPE_SNIFFER_RX = 0X5, 8891 MLX5_FLOW_TABLE_TYPE_SNIFFER_TX = 0X6, 8892 }; 8893 8894 struct mlx5_ifc_create_flow_table_out_bits { 8895 u8 status[0x8]; 8896 u8 icm_address_63_40[0x18]; 8897 8898 u8 syndrome[0x20]; 8899 8900 u8 icm_address_39_32[0x8]; 8901 u8 table_id[0x18]; 8902 8903 u8 icm_address_31_0[0x20]; 8904 }; 8905 8906 struct mlx5_ifc_create_flow_table_in_bits { 8907 u8 opcode[0x10]; 8908 u8 uid[0x10]; 8909 8910 u8 reserved_at_20[0x10]; 8911 u8 op_mod[0x10]; 8912 8913 u8 other_vport[0x1]; 8914 u8 reserved_at_41[0xf]; 8915 u8 vport_number[0x10]; 8916 8917 u8 reserved_at_60[0x20]; 8918 8919 u8 table_type[0x8]; 8920 u8 reserved_at_88[0x18]; 8921 8922 u8 reserved_at_a0[0x20]; 8923 8924 struct mlx5_ifc_flow_table_context_bits flow_table_context; 8925 }; 8926 8927 struct mlx5_ifc_create_flow_group_out_bits { 8928 u8 status[0x8]; 8929 u8 reserved_at_8[0x18]; 8930 8931 u8 syndrome[0x20]; 8932 8933 u8 reserved_at_40[0x8]; 8934 u8 group_id[0x18]; 8935 8936 u8 reserved_at_60[0x20]; 8937 }; 8938 8939 enum { 8940 MLX5_CREATE_FLOW_GROUP_IN_GROUP_TYPE_TCAM_SUBTABLE = 0x0, 8941 MLX5_CREATE_FLOW_GROUP_IN_GROUP_TYPE_HASH_SPLIT = 0x1, 8942 }; 8943 8944 enum { 8945 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 8946 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 8947 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 8948 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3, 8949 }; 8950 8951 struct mlx5_ifc_create_flow_group_in_bits { 8952 u8 opcode[0x10]; 8953 u8 reserved_at_10[0x10]; 8954 8955 u8 reserved_at_20[0x10]; 8956 u8 op_mod[0x10]; 8957 8958 u8 other_vport[0x1]; 8959 u8 reserved_at_41[0xf]; 8960 u8 vport_number[0x10]; 8961 8962 u8 reserved_at_60[0x20]; 8963 8964 u8 table_type[0x8]; 8965 u8 reserved_at_88[0x4]; 8966 u8 group_type[0x4]; 8967 u8 reserved_at_90[0x10]; 8968 8969 u8 reserved_at_a0[0x8]; 8970 u8 table_id[0x18]; 8971 8972 u8 source_eswitch_owner_vhca_id_valid[0x1]; 8973 8974 u8 reserved_at_c1[0x1f]; 8975 8976 u8 start_flow_index[0x20]; 8977 8978 u8 reserved_at_100[0x20]; 8979 8980 u8 end_flow_index[0x20]; 8981 8982 u8 reserved_at_140[0x10]; 8983 u8 match_definer_id[0x10]; 8984 8985 u8 reserved_at_160[0x80]; 8986 8987 u8 reserved_at_1e0[0x18]; 8988 u8 match_criteria_enable[0x8]; 8989 8990 struct mlx5_ifc_fte_match_param_bits match_criteria; 8991 8992 u8 reserved_at_1200[0xe00]; 8993 }; 8994 8995 struct mlx5_ifc_create_eq_out_bits { 8996 u8 status[0x8]; 8997 u8 reserved_at_8[0x18]; 8998 8999 u8 syndrome[0x20]; 9000 9001 u8 reserved_at_40[0x18]; 9002 u8 eq_number[0x8]; 9003 9004 u8 reserved_at_60[0x20]; 9005 }; 9006 9007 struct mlx5_ifc_create_eq_in_bits { 9008 u8 opcode[0x10]; 9009 u8 uid[0x10]; 9010 9011 u8 reserved_at_20[0x10]; 9012 u8 op_mod[0x10]; 9013 9014 u8 reserved_at_40[0x40]; 9015 9016 struct mlx5_ifc_eqc_bits eq_context_entry; 9017 9018 u8 reserved_at_280[0x40]; 9019 9020 u8 event_bitmask[4][0x40]; 9021 9022 u8 reserved_at_3c0[0x4c0]; 9023 9024 u8 pas[][0x40]; 9025 }; 9026 9027 struct mlx5_ifc_create_dct_out_bits { 9028 u8 status[0x8]; 9029 u8 reserved_at_8[0x18]; 9030 9031 u8 syndrome[0x20]; 9032 9033 u8 reserved_at_40[0x8]; 9034 u8 dctn[0x18]; 9035 9036 u8 ece[0x20]; 9037 }; 9038 9039 struct mlx5_ifc_create_dct_in_bits { 9040 u8 opcode[0x10]; 9041 u8 uid[0x10]; 9042 9043 u8 reserved_at_20[0x10]; 9044 u8 op_mod[0x10]; 9045 9046 u8 reserved_at_40[0x40]; 9047 9048 struct mlx5_ifc_dctc_bits dct_context_entry; 9049 9050 u8 reserved_at_280[0x180]; 9051 }; 9052 9053 struct mlx5_ifc_create_cq_out_bits { 9054 u8 status[0x8]; 9055 u8 reserved_at_8[0x18]; 9056 9057 u8 syndrome[0x20]; 9058 9059 u8 reserved_at_40[0x8]; 9060 u8 cqn[0x18]; 9061 9062 u8 reserved_at_60[0x20]; 9063 }; 9064 9065 struct mlx5_ifc_create_cq_in_bits { 9066 u8 opcode[0x10]; 9067 u8 uid[0x10]; 9068 9069 u8 reserved_at_20[0x10]; 9070 u8 op_mod[0x10]; 9071 9072 u8 reserved_at_40[0x40]; 9073 9074 struct mlx5_ifc_cqc_bits cq_context; 9075 9076 u8 reserved_at_280[0x60]; 9077 9078 u8 cq_umem_valid[0x1]; 9079 u8 reserved_at_2e1[0x59f]; 9080 9081 u8 pas[][0x40]; 9082 }; 9083 9084 struct mlx5_ifc_config_int_moderation_out_bits { 9085 u8 status[0x8]; 9086 u8 reserved_at_8[0x18]; 9087 9088 u8 syndrome[0x20]; 9089 9090 u8 reserved_at_40[0x4]; 9091 u8 min_delay[0xc]; 9092 u8 int_vector[0x10]; 9093 9094 u8 reserved_at_60[0x20]; 9095 }; 9096 9097 enum { 9098 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0, 9099 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1, 9100 }; 9101 9102 struct mlx5_ifc_config_int_moderation_in_bits { 9103 u8 opcode[0x10]; 9104 u8 reserved_at_10[0x10]; 9105 9106 u8 reserved_at_20[0x10]; 9107 u8 op_mod[0x10]; 9108 9109 u8 reserved_at_40[0x4]; 9110 u8 min_delay[0xc]; 9111 u8 int_vector[0x10]; 9112 9113 u8 reserved_at_60[0x20]; 9114 }; 9115 9116 struct mlx5_ifc_attach_to_mcg_out_bits { 9117 u8 status[0x8]; 9118 u8 reserved_at_8[0x18]; 9119 9120 u8 syndrome[0x20]; 9121 9122 u8 reserved_at_40[0x40]; 9123 }; 9124 9125 struct mlx5_ifc_attach_to_mcg_in_bits { 9126 u8 opcode[0x10]; 9127 u8 uid[0x10]; 9128 9129 u8 reserved_at_20[0x10]; 9130 u8 op_mod[0x10]; 9131 9132 u8 reserved_at_40[0x8]; 9133 u8 qpn[0x18]; 9134 9135 u8 reserved_at_60[0x20]; 9136 9137 u8 multicast_gid[16][0x8]; 9138 }; 9139 9140 struct mlx5_ifc_arm_xrq_out_bits { 9141 u8 status[0x8]; 9142 u8 reserved_at_8[0x18]; 9143 9144 u8 syndrome[0x20]; 9145 9146 u8 reserved_at_40[0x40]; 9147 }; 9148 9149 struct mlx5_ifc_arm_xrq_in_bits { 9150 u8 opcode[0x10]; 9151 u8 reserved_at_10[0x10]; 9152 9153 u8 reserved_at_20[0x10]; 9154 u8 op_mod[0x10]; 9155 9156 u8 reserved_at_40[0x8]; 9157 u8 xrqn[0x18]; 9158 9159 u8 reserved_at_60[0x10]; 9160 u8 lwm[0x10]; 9161 }; 9162 9163 struct mlx5_ifc_arm_xrc_srq_out_bits { 9164 u8 status[0x8]; 9165 u8 reserved_at_8[0x18]; 9166 9167 u8 syndrome[0x20]; 9168 9169 u8 reserved_at_40[0x40]; 9170 }; 9171 9172 enum { 9173 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1, 9174 }; 9175 9176 struct mlx5_ifc_arm_xrc_srq_in_bits { 9177 u8 opcode[0x10]; 9178 u8 uid[0x10]; 9179 9180 u8 reserved_at_20[0x10]; 9181 u8 op_mod[0x10]; 9182 9183 u8 reserved_at_40[0x8]; 9184 u8 xrc_srqn[0x18]; 9185 9186 u8 reserved_at_60[0x10]; 9187 u8 lwm[0x10]; 9188 }; 9189 9190 struct mlx5_ifc_arm_rq_out_bits { 9191 u8 status[0x8]; 9192 u8 reserved_at_8[0x18]; 9193 9194 u8 syndrome[0x20]; 9195 9196 u8 reserved_at_40[0x40]; 9197 }; 9198 9199 enum { 9200 MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1, 9201 MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2, 9202 }; 9203 9204 struct mlx5_ifc_arm_rq_in_bits { 9205 u8 opcode[0x10]; 9206 u8 uid[0x10]; 9207 9208 u8 reserved_at_20[0x10]; 9209 u8 op_mod[0x10]; 9210 9211 u8 reserved_at_40[0x8]; 9212 u8 srq_number[0x18]; 9213 9214 u8 reserved_at_60[0x10]; 9215 u8 lwm[0x10]; 9216 }; 9217 9218 struct mlx5_ifc_arm_dct_out_bits { 9219 u8 status[0x8]; 9220 u8 reserved_at_8[0x18]; 9221 9222 u8 syndrome[0x20]; 9223 9224 u8 reserved_at_40[0x40]; 9225 }; 9226 9227 struct mlx5_ifc_arm_dct_in_bits { 9228 u8 opcode[0x10]; 9229 u8 reserved_at_10[0x10]; 9230 9231 u8 reserved_at_20[0x10]; 9232 u8 op_mod[0x10]; 9233 9234 u8 reserved_at_40[0x8]; 9235 u8 dct_number[0x18]; 9236 9237 u8 reserved_at_60[0x20]; 9238 }; 9239 9240 struct mlx5_ifc_alloc_xrcd_out_bits { 9241 u8 status[0x8]; 9242 u8 reserved_at_8[0x18]; 9243 9244 u8 syndrome[0x20]; 9245 9246 u8 reserved_at_40[0x8]; 9247 u8 xrcd[0x18]; 9248 9249 u8 reserved_at_60[0x20]; 9250 }; 9251 9252 struct mlx5_ifc_alloc_xrcd_in_bits { 9253 u8 opcode[0x10]; 9254 u8 uid[0x10]; 9255 9256 u8 reserved_at_20[0x10]; 9257 u8 op_mod[0x10]; 9258 9259 u8 reserved_at_40[0x40]; 9260 }; 9261 9262 struct mlx5_ifc_alloc_uar_out_bits { 9263 u8 status[0x8]; 9264 u8 reserved_at_8[0x18]; 9265 9266 u8 syndrome[0x20]; 9267 9268 u8 reserved_at_40[0x8]; 9269 u8 uar[0x18]; 9270 9271 u8 reserved_at_60[0x20]; 9272 }; 9273 9274 struct mlx5_ifc_alloc_uar_in_bits { 9275 u8 opcode[0x10]; 9276 u8 uid[0x10]; 9277 9278 u8 reserved_at_20[0x10]; 9279 u8 op_mod[0x10]; 9280 9281 u8 reserved_at_40[0x40]; 9282 }; 9283 9284 struct mlx5_ifc_alloc_transport_domain_out_bits { 9285 u8 status[0x8]; 9286 u8 reserved_at_8[0x18]; 9287 9288 u8 syndrome[0x20]; 9289 9290 u8 reserved_at_40[0x8]; 9291 u8 transport_domain[0x18]; 9292 9293 u8 reserved_at_60[0x20]; 9294 }; 9295 9296 struct mlx5_ifc_alloc_transport_domain_in_bits { 9297 u8 opcode[0x10]; 9298 u8 uid[0x10]; 9299 9300 u8 reserved_at_20[0x10]; 9301 u8 op_mod[0x10]; 9302 9303 u8 reserved_at_40[0x40]; 9304 }; 9305 9306 struct mlx5_ifc_alloc_q_counter_out_bits { 9307 u8 status[0x8]; 9308 u8 reserved_at_8[0x18]; 9309 9310 u8 syndrome[0x20]; 9311 9312 u8 reserved_at_40[0x18]; 9313 u8 counter_set_id[0x8]; 9314 9315 u8 reserved_at_60[0x20]; 9316 }; 9317 9318 struct mlx5_ifc_alloc_q_counter_in_bits { 9319 u8 opcode[0x10]; 9320 u8 uid[0x10]; 9321 9322 u8 reserved_at_20[0x10]; 9323 u8 op_mod[0x10]; 9324 9325 u8 reserved_at_40[0x40]; 9326 }; 9327 9328 struct mlx5_ifc_alloc_pd_out_bits { 9329 u8 status[0x8]; 9330 u8 reserved_at_8[0x18]; 9331 9332 u8 syndrome[0x20]; 9333 9334 u8 reserved_at_40[0x8]; 9335 u8 pd[0x18]; 9336 9337 u8 reserved_at_60[0x20]; 9338 }; 9339 9340 struct mlx5_ifc_alloc_pd_in_bits { 9341 u8 opcode[0x10]; 9342 u8 uid[0x10]; 9343 9344 u8 reserved_at_20[0x10]; 9345 u8 op_mod[0x10]; 9346 9347 u8 reserved_at_40[0x40]; 9348 }; 9349 9350 struct mlx5_ifc_alloc_flow_counter_out_bits { 9351 u8 status[0x8]; 9352 u8 reserved_at_8[0x18]; 9353 9354 u8 syndrome[0x20]; 9355 9356 u8 flow_counter_id[0x20]; 9357 9358 u8 reserved_at_60[0x20]; 9359 }; 9360 9361 struct mlx5_ifc_alloc_flow_counter_in_bits { 9362 u8 opcode[0x10]; 9363 u8 reserved_at_10[0x10]; 9364 9365 u8 reserved_at_20[0x10]; 9366 u8 op_mod[0x10]; 9367 9368 u8 reserved_at_40[0x33]; 9369 u8 flow_counter_bulk_log_size[0x5]; 9370 u8 flow_counter_bulk[0x8]; 9371 }; 9372 9373 struct mlx5_ifc_add_vxlan_udp_dport_out_bits { 9374 u8 status[0x8]; 9375 u8 reserved_at_8[0x18]; 9376 9377 u8 syndrome[0x20]; 9378 9379 u8 reserved_at_40[0x40]; 9380 }; 9381 9382 struct mlx5_ifc_add_vxlan_udp_dport_in_bits { 9383 u8 opcode[0x10]; 9384 u8 reserved_at_10[0x10]; 9385 9386 u8 reserved_at_20[0x10]; 9387 u8 op_mod[0x10]; 9388 9389 u8 reserved_at_40[0x20]; 9390 9391 u8 reserved_at_60[0x10]; 9392 u8 vxlan_udp_port[0x10]; 9393 }; 9394 9395 struct mlx5_ifc_set_pp_rate_limit_out_bits { 9396 u8 status[0x8]; 9397 u8 reserved_at_8[0x18]; 9398 9399 u8 syndrome[0x20]; 9400 9401 u8 reserved_at_40[0x40]; 9402 }; 9403 9404 struct mlx5_ifc_set_pp_rate_limit_context_bits { 9405 u8 rate_limit[0x20]; 9406 9407 u8 burst_upper_bound[0x20]; 9408 9409 u8 reserved_at_40[0x10]; 9410 u8 typical_packet_size[0x10]; 9411 9412 u8 reserved_at_60[0x120]; 9413 }; 9414 9415 struct mlx5_ifc_set_pp_rate_limit_in_bits { 9416 u8 opcode[0x10]; 9417 u8 uid[0x10]; 9418 9419 u8 reserved_at_20[0x10]; 9420 u8 op_mod[0x10]; 9421 9422 u8 reserved_at_40[0x10]; 9423 u8 rate_limit_index[0x10]; 9424 9425 u8 reserved_at_60[0x20]; 9426 9427 struct mlx5_ifc_set_pp_rate_limit_context_bits ctx; 9428 }; 9429 9430 struct mlx5_ifc_access_register_out_bits { 9431 u8 status[0x8]; 9432 u8 reserved_at_8[0x18]; 9433 9434 u8 syndrome[0x20]; 9435 9436 u8 reserved_at_40[0x40]; 9437 9438 u8 register_data[][0x20]; 9439 }; 9440 9441 enum { 9442 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0, 9443 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1, 9444 }; 9445 9446 struct mlx5_ifc_access_register_in_bits { 9447 u8 opcode[0x10]; 9448 u8 reserved_at_10[0x10]; 9449 9450 u8 reserved_at_20[0x10]; 9451 u8 op_mod[0x10]; 9452 9453 u8 reserved_at_40[0x10]; 9454 u8 register_id[0x10]; 9455 9456 u8 argument[0x20]; 9457 9458 u8 register_data[][0x20]; 9459 }; 9460 9461 struct mlx5_ifc_sltp_reg_bits { 9462 u8 status[0x4]; 9463 u8 version[0x4]; 9464 u8 local_port[0x8]; 9465 u8 pnat[0x2]; 9466 u8 reserved_at_12[0x2]; 9467 u8 lane[0x4]; 9468 u8 reserved_at_18[0x8]; 9469 9470 u8 reserved_at_20[0x20]; 9471 9472 u8 reserved_at_40[0x7]; 9473 u8 polarity[0x1]; 9474 u8 ob_tap0[0x8]; 9475 u8 ob_tap1[0x8]; 9476 u8 ob_tap2[0x8]; 9477 9478 u8 reserved_at_60[0xc]; 9479 u8 ob_preemp_mode[0x4]; 9480 u8 ob_reg[0x8]; 9481 u8 ob_bias[0x8]; 9482 9483 u8 reserved_at_80[0x20]; 9484 }; 9485 9486 struct mlx5_ifc_slrg_reg_bits { 9487 u8 status[0x4]; 9488 u8 version[0x4]; 9489 u8 local_port[0x8]; 9490 u8 pnat[0x2]; 9491 u8 reserved_at_12[0x2]; 9492 u8 lane[0x4]; 9493 u8 reserved_at_18[0x8]; 9494 9495 u8 time_to_link_up[0x10]; 9496 u8 reserved_at_30[0xc]; 9497 u8 grade_lane_speed[0x4]; 9498 9499 u8 grade_version[0x8]; 9500 u8 grade[0x18]; 9501 9502 u8 reserved_at_60[0x4]; 9503 u8 height_grade_type[0x4]; 9504 u8 height_grade[0x18]; 9505 9506 u8 height_dz[0x10]; 9507 u8 height_dv[0x10]; 9508 9509 u8 reserved_at_a0[0x10]; 9510 u8 height_sigma[0x10]; 9511 9512 u8 reserved_at_c0[0x20]; 9513 9514 u8 reserved_at_e0[0x4]; 9515 u8 phase_grade_type[0x4]; 9516 u8 phase_grade[0x18]; 9517 9518 u8 reserved_at_100[0x8]; 9519 u8 phase_eo_pos[0x8]; 9520 u8 reserved_at_110[0x8]; 9521 u8 phase_eo_neg[0x8]; 9522 9523 u8 ffe_set_tested[0x10]; 9524 u8 test_errors_per_lane[0x10]; 9525 }; 9526 9527 struct mlx5_ifc_pvlc_reg_bits { 9528 u8 reserved_at_0[0x8]; 9529 u8 local_port[0x8]; 9530 u8 reserved_at_10[0x10]; 9531 9532 u8 reserved_at_20[0x1c]; 9533 u8 vl_hw_cap[0x4]; 9534 9535 u8 reserved_at_40[0x1c]; 9536 u8 vl_admin[0x4]; 9537 9538 u8 reserved_at_60[0x1c]; 9539 u8 vl_operational[0x4]; 9540 }; 9541 9542 struct mlx5_ifc_pude_reg_bits { 9543 u8 swid[0x8]; 9544 u8 local_port[0x8]; 9545 u8 reserved_at_10[0x4]; 9546 u8 admin_status[0x4]; 9547 u8 reserved_at_18[0x4]; 9548 u8 oper_status[0x4]; 9549 9550 u8 reserved_at_20[0x60]; 9551 }; 9552 9553 struct mlx5_ifc_ptys_reg_bits { 9554 u8 reserved_at_0[0x1]; 9555 u8 an_disable_admin[0x1]; 9556 u8 an_disable_cap[0x1]; 9557 u8 reserved_at_3[0x5]; 9558 u8 local_port[0x8]; 9559 u8 reserved_at_10[0xd]; 9560 u8 proto_mask[0x3]; 9561 9562 u8 an_status[0x4]; 9563 u8 reserved_at_24[0xc]; 9564 u8 data_rate_oper[0x10]; 9565 9566 u8 ext_eth_proto_capability[0x20]; 9567 9568 u8 eth_proto_capability[0x20]; 9569 9570 u8 ib_link_width_capability[0x10]; 9571 u8 ib_proto_capability[0x10]; 9572 9573 u8 ext_eth_proto_admin[0x20]; 9574 9575 u8 eth_proto_admin[0x20]; 9576 9577 u8 ib_link_width_admin[0x10]; 9578 u8 ib_proto_admin[0x10]; 9579 9580 u8 ext_eth_proto_oper[0x20]; 9581 9582 u8 eth_proto_oper[0x20]; 9583 9584 u8 ib_link_width_oper[0x10]; 9585 u8 ib_proto_oper[0x10]; 9586 9587 u8 reserved_at_160[0x1c]; 9588 u8 connector_type[0x4]; 9589 9590 u8 eth_proto_lp_advertise[0x20]; 9591 9592 u8 reserved_at_1a0[0x60]; 9593 }; 9594 9595 struct mlx5_ifc_mlcr_reg_bits { 9596 u8 reserved_at_0[0x8]; 9597 u8 local_port[0x8]; 9598 u8 reserved_at_10[0x20]; 9599 9600 u8 beacon_duration[0x10]; 9601 u8 reserved_at_40[0x10]; 9602 9603 u8 beacon_remain[0x10]; 9604 }; 9605 9606 struct mlx5_ifc_ptas_reg_bits { 9607 u8 reserved_at_0[0x20]; 9608 9609 u8 algorithm_options[0x10]; 9610 u8 reserved_at_30[0x4]; 9611 u8 repetitions_mode[0x4]; 9612 u8 num_of_repetitions[0x8]; 9613 9614 u8 grade_version[0x8]; 9615 u8 height_grade_type[0x4]; 9616 u8 phase_grade_type[0x4]; 9617 u8 height_grade_weight[0x8]; 9618 u8 phase_grade_weight[0x8]; 9619 9620 u8 gisim_measure_bits[0x10]; 9621 u8 adaptive_tap_measure_bits[0x10]; 9622 9623 u8 ber_bath_high_error_threshold[0x10]; 9624 u8 ber_bath_mid_error_threshold[0x10]; 9625 9626 u8 ber_bath_low_error_threshold[0x10]; 9627 u8 one_ratio_high_threshold[0x10]; 9628 9629 u8 one_ratio_high_mid_threshold[0x10]; 9630 u8 one_ratio_low_mid_threshold[0x10]; 9631 9632 u8 one_ratio_low_threshold[0x10]; 9633 u8 ndeo_error_threshold[0x10]; 9634 9635 u8 mixer_offset_step_size[0x10]; 9636 u8 reserved_at_110[0x8]; 9637 u8 mix90_phase_for_voltage_bath[0x8]; 9638 9639 u8 mixer_offset_start[0x10]; 9640 u8 mixer_offset_end[0x10]; 9641 9642 u8 reserved_at_140[0x15]; 9643 u8 ber_test_time[0xb]; 9644 }; 9645 9646 struct mlx5_ifc_pspa_reg_bits { 9647 u8 swid[0x8]; 9648 u8 local_port[0x8]; 9649 u8 sub_port[0x8]; 9650 u8 reserved_at_18[0x8]; 9651 9652 u8 reserved_at_20[0x20]; 9653 }; 9654 9655 struct mlx5_ifc_pqdr_reg_bits { 9656 u8 reserved_at_0[0x8]; 9657 u8 local_port[0x8]; 9658 u8 reserved_at_10[0x5]; 9659 u8 prio[0x3]; 9660 u8 reserved_at_18[0x6]; 9661 u8 mode[0x2]; 9662 9663 u8 reserved_at_20[0x20]; 9664 9665 u8 reserved_at_40[0x10]; 9666 u8 min_threshold[0x10]; 9667 9668 u8 reserved_at_60[0x10]; 9669 u8 max_threshold[0x10]; 9670 9671 u8 reserved_at_80[0x10]; 9672 u8 mark_probability_denominator[0x10]; 9673 9674 u8 reserved_at_a0[0x60]; 9675 }; 9676 9677 struct mlx5_ifc_ppsc_reg_bits { 9678 u8 reserved_at_0[0x8]; 9679 u8 local_port[0x8]; 9680 u8 reserved_at_10[0x10]; 9681 9682 u8 reserved_at_20[0x60]; 9683 9684 u8 reserved_at_80[0x1c]; 9685 u8 wrps_admin[0x4]; 9686 9687 u8 reserved_at_a0[0x1c]; 9688 u8 wrps_status[0x4]; 9689 9690 u8 reserved_at_c0[0x8]; 9691 u8 up_threshold[0x8]; 9692 u8 reserved_at_d0[0x8]; 9693 u8 down_threshold[0x8]; 9694 9695 u8 reserved_at_e0[0x20]; 9696 9697 u8 reserved_at_100[0x1c]; 9698 u8 srps_admin[0x4]; 9699 9700 u8 reserved_at_120[0x1c]; 9701 u8 srps_status[0x4]; 9702 9703 u8 reserved_at_140[0x40]; 9704 }; 9705 9706 struct mlx5_ifc_pplr_reg_bits { 9707 u8 reserved_at_0[0x8]; 9708 u8 local_port[0x8]; 9709 u8 reserved_at_10[0x10]; 9710 9711 u8 reserved_at_20[0x8]; 9712 u8 lb_cap[0x8]; 9713 u8 reserved_at_30[0x8]; 9714 u8 lb_en[0x8]; 9715 }; 9716 9717 struct mlx5_ifc_pplm_reg_bits { 9718 u8 reserved_at_0[0x8]; 9719 u8 local_port[0x8]; 9720 u8 reserved_at_10[0x10]; 9721 9722 u8 reserved_at_20[0x20]; 9723 9724 u8 port_profile_mode[0x8]; 9725 u8 static_port_profile[0x8]; 9726 u8 active_port_profile[0x8]; 9727 u8 reserved_at_58[0x8]; 9728 9729 u8 retransmission_active[0x8]; 9730 u8 fec_mode_active[0x18]; 9731 9732 u8 rs_fec_correction_bypass_cap[0x4]; 9733 u8 reserved_at_84[0x8]; 9734 u8 fec_override_cap_56g[0x4]; 9735 u8 fec_override_cap_100g[0x4]; 9736 u8 fec_override_cap_50g[0x4]; 9737 u8 fec_override_cap_25g[0x4]; 9738 u8 fec_override_cap_10g_40g[0x4]; 9739 9740 u8 rs_fec_correction_bypass_admin[0x4]; 9741 u8 reserved_at_a4[0x8]; 9742 u8 fec_override_admin_56g[0x4]; 9743 u8 fec_override_admin_100g[0x4]; 9744 u8 fec_override_admin_50g[0x4]; 9745 u8 fec_override_admin_25g[0x4]; 9746 u8 fec_override_admin_10g_40g[0x4]; 9747 9748 u8 fec_override_cap_400g_8x[0x10]; 9749 u8 fec_override_cap_200g_4x[0x10]; 9750 9751 u8 fec_override_cap_100g_2x[0x10]; 9752 u8 fec_override_cap_50g_1x[0x10]; 9753 9754 u8 fec_override_admin_400g_8x[0x10]; 9755 u8 fec_override_admin_200g_4x[0x10]; 9756 9757 u8 fec_override_admin_100g_2x[0x10]; 9758 u8 fec_override_admin_50g_1x[0x10]; 9759 9760 u8 reserved_at_140[0x140]; 9761 }; 9762 9763 struct mlx5_ifc_ppcnt_reg_bits { 9764 u8 swid[0x8]; 9765 u8 local_port[0x8]; 9766 u8 pnat[0x2]; 9767 u8 reserved_at_12[0x8]; 9768 u8 grp[0x6]; 9769 9770 u8 clr[0x1]; 9771 u8 reserved_at_21[0x1c]; 9772 u8 prio_tc[0x3]; 9773 9774 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set; 9775 }; 9776 9777 struct mlx5_ifc_mpein_reg_bits { 9778 u8 reserved_at_0[0x2]; 9779 u8 depth[0x6]; 9780 u8 pcie_index[0x8]; 9781 u8 node[0x8]; 9782 u8 reserved_at_18[0x8]; 9783 9784 u8 capability_mask[0x20]; 9785 9786 u8 reserved_at_40[0x8]; 9787 u8 link_width_enabled[0x8]; 9788 u8 link_speed_enabled[0x10]; 9789 9790 u8 lane0_physical_position[0x8]; 9791 u8 link_width_active[0x8]; 9792 u8 link_speed_active[0x10]; 9793 9794 u8 num_of_pfs[0x10]; 9795 u8 num_of_vfs[0x10]; 9796 9797 u8 bdf0[0x10]; 9798 u8 reserved_at_b0[0x10]; 9799 9800 u8 max_read_request_size[0x4]; 9801 u8 max_payload_size[0x4]; 9802 u8 reserved_at_c8[0x5]; 9803 u8 pwr_status[0x3]; 9804 u8 port_type[0x4]; 9805 u8 reserved_at_d4[0xb]; 9806 u8 lane_reversal[0x1]; 9807 9808 u8 reserved_at_e0[0x14]; 9809 u8 pci_power[0xc]; 9810 9811 u8 reserved_at_100[0x20]; 9812 9813 u8 device_status[0x10]; 9814 u8 port_state[0x8]; 9815 u8 reserved_at_138[0x8]; 9816 9817 u8 reserved_at_140[0x10]; 9818 u8 receiver_detect_result[0x10]; 9819 9820 u8 reserved_at_160[0x20]; 9821 }; 9822 9823 struct mlx5_ifc_mpcnt_reg_bits { 9824 u8 reserved_at_0[0x8]; 9825 u8 pcie_index[0x8]; 9826 u8 reserved_at_10[0xa]; 9827 u8 grp[0x6]; 9828 9829 u8 clr[0x1]; 9830 u8 reserved_at_21[0x1f]; 9831 9832 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set; 9833 }; 9834 9835 struct mlx5_ifc_ppad_reg_bits { 9836 u8 reserved_at_0[0x3]; 9837 u8 single_mac[0x1]; 9838 u8 reserved_at_4[0x4]; 9839 u8 local_port[0x8]; 9840 u8 mac_47_32[0x10]; 9841 9842 u8 mac_31_0[0x20]; 9843 9844 u8 reserved_at_40[0x40]; 9845 }; 9846 9847 struct mlx5_ifc_pmtu_reg_bits { 9848 u8 reserved_at_0[0x8]; 9849 u8 local_port[0x8]; 9850 u8 reserved_at_10[0x10]; 9851 9852 u8 max_mtu[0x10]; 9853 u8 reserved_at_30[0x10]; 9854 9855 u8 admin_mtu[0x10]; 9856 u8 reserved_at_50[0x10]; 9857 9858 u8 oper_mtu[0x10]; 9859 u8 reserved_at_70[0x10]; 9860 }; 9861 9862 struct mlx5_ifc_pmpr_reg_bits { 9863 u8 reserved_at_0[0x8]; 9864 u8 module[0x8]; 9865 u8 reserved_at_10[0x10]; 9866 9867 u8 reserved_at_20[0x18]; 9868 u8 attenuation_5g[0x8]; 9869 9870 u8 reserved_at_40[0x18]; 9871 u8 attenuation_7g[0x8]; 9872 9873 u8 reserved_at_60[0x18]; 9874 u8 attenuation_12g[0x8]; 9875 }; 9876 9877 struct mlx5_ifc_pmpe_reg_bits { 9878 u8 reserved_at_0[0x8]; 9879 u8 module[0x8]; 9880 u8 reserved_at_10[0xc]; 9881 u8 module_status[0x4]; 9882 9883 u8 reserved_at_20[0x60]; 9884 }; 9885 9886 struct mlx5_ifc_pmpc_reg_bits { 9887 u8 module_state_updated[32][0x8]; 9888 }; 9889 9890 struct mlx5_ifc_pmlpn_reg_bits { 9891 u8 reserved_at_0[0x4]; 9892 u8 mlpn_status[0x4]; 9893 u8 local_port[0x8]; 9894 u8 reserved_at_10[0x10]; 9895 9896 u8 e[0x1]; 9897 u8 reserved_at_21[0x1f]; 9898 }; 9899 9900 struct mlx5_ifc_pmlp_reg_bits { 9901 u8 rxtx[0x1]; 9902 u8 reserved_at_1[0x7]; 9903 u8 local_port[0x8]; 9904 u8 reserved_at_10[0x8]; 9905 u8 width[0x8]; 9906 9907 u8 lane0_module_mapping[0x20]; 9908 9909 u8 lane1_module_mapping[0x20]; 9910 9911 u8 lane2_module_mapping[0x20]; 9912 9913 u8 lane3_module_mapping[0x20]; 9914 9915 u8 reserved_at_a0[0x160]; 9916 }; 9917 9918 struct mlx5_ifc_pmaos_reg_bits { 9919 u8 reserved_at_0[0x8]; 9920 u8 module[0x8]; 9921 u8 reserved_at_10[0x4]; 9922 u8 admin_status[0x4]; 9923 u8 reserved_at_18[0x4]; 9924 u8 oper_status[0x4]; 9925 9926 u8 ase[0x1]; 9927 u8 ee[0x1]; 9928 u8 reserved_at_22[0x1c]; 9929 u8 e[0x2]; 9930 9931 u8 reserved_at_40[0x40]; 9932 }; 9933 9934 struct mlx5_ifc_plpc_reg_bits { 9935 u8 reserved_at_0[0x4]; 9936 u8 profile_id[0xc]; 9937 u8 reserved_at_10[0x4]; 9938 u8 proto_mask[0x4]; 9939 u8 reserved_at_18[0x8]; 9940 9941 u8 reserved_at_20[0x10]; 9942 u8 lane_speed[0x10]; 9943 9944 u8 reserved_at_40[0x17]; 9945 u8 lpbf[0x1]; 9946 u8 fec_mode_policy[0x8]; 9947 9948 u8 retransmission_capability[0x8]; 9949 u8 fec_mode_capability[0x18]; 9950 9951 u8 retransmission_support_admin[0x8]; 9952 u8 fec_mode_support_admin[0x18]; 9953 9954 u8 retransmission_request_admin[0x8]; 9955 u8 fec_mode_request_admin[0x18]; 9956 9957 u8 reserved_at_c0[0x80]; 9958 }; 9959 9960 struct mlx5_ifc_plib_reg_bits { 9961 u8 reserved_at_0[0x8]; 9962 u8 local_port[0x8]; 9963 u8 reserved_at_10[0x8]; 9964 u8 ib_port[0x8]; 9965 9966 u8 reserved_at_20[0x60]; 9967 }; 9968 9969 struct mlx5_ifc_plbf_reg_bits { 9970 u8 reserved_at_0[0x8]; 9971 u8 local_port[0x8]; 9972 u8 reserved_at_10[0xd]; 9973 u8 lbf_mode[0x3]; 9974 9975 u8 reserved_at_20[0x20]; 9976 }; 9977 9978 struct mlx5_ifc_pipg_reg_bits { 9979 u8 reserved_at_0[0x8]; 9980 u8 local_port[0x8]; 9981 u8 reserved_at_10[0x10]; 9982 9983 u8 dic[0x1]; 9984 u8 reserved_at_21[0x19]; 9985 u8 ipg[0x4]; 9986 u8 reserved_at_3e[0x2]; 9987 }; 9988 9989 struct mlx5_ifc_pifr_reg_bits { 9990 u8 reserved_at_0[0x8]; 9991 u8 local_port[0x8]; 9992 u8 reserved_at_10[0x10]; 9993 9994 u8 reserved_at_20[0xe0]; 9995 9996 u8 port_filter[8][0x20]; 9997 9998 u8 port_filter_update_en[8][0x20]; 9999 }; 10000 10001 struct mlx5_ifc_pfcc_reg_bits { 10002 u8 reserved_at_0[0x8]; 10003 u8 local_port[0x8]; 10004 u8 reserved_at_10[0xb]; 10005 u8 ppan_mask_n[0x1]; 10006 u8 minor_stall_mask[0x1]; 10007 u8 critical_stall_mask[0x1]; 10008 u8 reserved_at_1e[0x2]; 10009 10010 u8 ppan[0x4]; 10011 u8 reserved_at_24[0x4]; 10012 u8 prio_mask_tx[0x8]; 10013 u8 reserved_at_30[0x8]; 10014 u8 prio_mask_rx[0x8]; 10015 10016 u8 pptx[0x1]; 10017 u8 aptx[0x1]; 10018 u8 pptx_mask_n[0x1]; 10019 u8 reserved_at_43[0x5]; 10020 u8 pfctx[0x8]; 10021 u8 reserved_at_50[0x10]; 10022 10023 u8 pprx[0x1]; 10024 u8 aprx[0x1]; 10025 u8 pprx_mask_n[0x1]; 10026 u8 reserved_at_63[0x5]; 10027 u8 pfcrx[0x8]; 10028 u8 reserved_at_70[0x10]; 10029 10030 u8 device_stall_minor_watermark[0x10]; 10031 u8 device_stall_critical_watermark[0x10]; 10032 10033 u8 reserved_at_a0[0x60]; 10034 }; 10035 10036 struct mlx5_ifc_pelc_reg_bits { 10037 u8 op[0x4]; 10038 u8 reserved_at_4[0x4]; 10039 u8 local_port[0x8]; 10040 u8 reserved_at_10[0x10]; 10041 10042 u8 op_admin[0x8]; 10043 u8 op_capability[0x8]; 10044 u8 op_request[0x8]; 10045 u8 op_active[0x8]; 10046 10047 u8 admin[0x40]; 10048 10049 u8 capability[0x40]; 10050 10051 u8 request[0x40]; 10052 10053 u8 active[0x40]; 10054 10055 u8 reserved_at_140[0x80]; 10056 }; 10057 10058 struct mlx5_ifc_peir_reg_bits { 10059 u8 reserved_at_0[0x8]; 10060 u8 local_port[0x8]; 10061 u8 reserved_at_10[0x10]; 10062 10063 u8 reserved_at_20[0xc]; 10064 u8 error_count[0x4]; 10065 u8 reserved_at_30[0x10]; 10066 10067 u8 reserved_at_40[0xc]; 10068 u8 lane[0x4]; 10069 u8 reserved_at_50[0x8]; 10070 u8 error_type[0x8]; 10071 }; 10072 10073 struct mlx5_ifc_mpegc_reg_bits { 10074 u8 reserved_at_0[0x30]; 10075 u8 field_select[0x10]; 10076 10077 u8 tx_overflow_sense[0x1]; 10078 u8 mark_cqe[0x1]; 10079 u8 mark_cnp[0x1]; 10080 u8 reserved_at_43[0x1b]; 10081 u8 tx_lossy_overflow_oper[0x2]; 10082 10083 u8 reserved_at_60[0x100]; 10084 }; 10085 10086 enum { 10087 MLX5_MTUTC_FREQ_ADJ_UNITS_PPB = 0x0, 10088 MLX5_MTUTC_FREQ_ADJ_UNITS_SCALED_PPM = 0x1, 10089 }; 10090 10091 enum { 10092 MLX5_MTUTC_OPERATION_SET_TIME_IMMEDIATE = 0x1, 10093 MLX5_MTUTC_OPERATION_ADJUST_TIME = 0x2, 10094 MLX5_MTUTC_OPERATION_ADJUST_FREQ_UTC = 0x3, 10095 }; 10096 10097 struct mlx5_ifc_mtutc_reg_bits { 10098 u8 reserved_at_0[0x5]; 10099 u8 freq_adj_units[0x3]; 10100 u8 reserved_at_8[0x14]; 10101 u8 operation[0x4]; 10102 10103 u8 freq_adjustment[0x20]; 10104 10105 u8 reserved_at_40[0x40]; 10106 10107 u8 utc_sec[0x20]; 10108 10109 u8 reserved_at_a0[0x2]; 10110 u8 utc_nsec[0x1e]; 10111 10112 u8 time_adjustment[0x20]; 10113 }; 10114 10115 struct mlx5_ifc_pcam_enhanced_features_bits { 10116 u8 reserved_at_0[0x68]; 10117 u8 fec_50G_per_lane_in_pplm[0x1]; 10118 u8 reserved_at_69[0x4]; 10119 u8 rx_icrc_encapsulated_counter[0x1]; 10120 u8 reserved_at_6e[0x4]; 10121 u8 ptys_extended_ethernet[0x1]; 10122 u8 reserved_at_73[0x3]; 10123 u8 pfcc_mask[0x1]; 10124 u8 reserved_at_77[0x3]; 10125 u8 per_lane_error_counters[0x1]; 10126 u8 rx_buffer_fullness_counters[0x1]; 10127 u8 ptys_connector_type[0x1]; 10128 u8 reserved_at_7d[0x1]; 10129 u8 ppcnt_discard_group[0x1]; 10130 u8 ppcnt_statistical_group[0x1]; 10131 }; 10132 10133 struct mlx5_ifc_pcam_regs_5000_to_507f_bits { 10134 u8 port_access_reg_cap_mask_127_to_96[0x20]; 10135 u8 port_access_reg_cap_mask_95_to_64[0x20]; 10136 10137 u8 port_access_reg_cap_mask_63_to_36[0x1c]; 10138 u8 pplm[0x1]; 10139 u8 port_access_reg_cap_mask_34_to_32[0x3]; 10140 10141 u8 port_access_reg_cap_mask_31_to_13[0x13]; 10142 u8 pbmc[0x1]; 10143 u8 pptb[0x1]; 10144 u8 port_access_reg_cap_mask_10_to_09[0x2]; 10145 u8 ppcnt[0x1]; 10146 u8 port_access_reg_cap_mask_07_to_00[0x8]; 10147 }; 10148 10149 struct mlx5_ifc_pcam_reg_bits { 10150 u8 reserved_at_0[0x8]; 10151 u8 feature_group[0x8]; 10152 u8 reserved_at_10[0x8]; 10153 u8 access_reg_group[0x8]; 10154 10155 u8 reserved_at_20[0x20]; 10156 10157 union { 10158 struct mlx5_ifc_pcam_regs_5000_to_507f_bits regs_5000_to_507f; 10159 u8 reserved_at_0[0x80]; 10160 } port_access_reg_cap_mask; 10161 10162 u8 reserved_at_c0[0x80]; 10163 10164 union { 10165 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features; 10166 u8 reserved_at_0[0x80]; 10167 } feature_cap_mask; 10168 10169 u8 reserved_at_1c0[0xc0]; 10170 }; 10171 10172 struct mlx5_ifc_mcam_enhanced_features_bits { 10173 u8 reserved_at_0[0x50]; 10174 u8 mtutc_freq_adj_units[0x1]; 10175 u8 mtutc_time_adjustment_extended_range[0x1]; 10176 u8 reserved_at_52[0xb]; 10177 u8 mcia_32dwords[0x1]; 10178 u8 out_pulse_duration_ns[0x1]; 10179 u8 npps_period[0x1]; 10180 u8 reserved_at_60[0xa]; 10181 u8 reset_state[0x1]; 10182 u8 ptpcyc2realtime_modify[0x1]; 10183 u8 reserved_at_6c[0x2]; 10184 u8 pci_status_and_power[0x1]; 10185 u8 reserved_at_6f[0x5]; 10186 u8 mark_tx_action_cnp[0x1]; 10187 u8 mark_tx_action_cqe[0x1]; 10188 u8 dynamic_tx_overflow[0x1]; 10189 u8 reserved_at_77[0x4]; 10190 u8 pcie_outbound_stalled[0x1]; 10191 u8 tx_overflow_buffer_pkt[0x1]; 10192 u8 mtpps_enh_out_per_adj[0x1]; 10193 u8 mtpps_fs[0x1]; 10194 u8 pcie_performance_group[0x1]; 10195 }; 10196 10197 struct mlx5_ifc_mcam_access_reg_bits { 10198 u8 reserved_at_0[0x1c]; 10199 u8 mcda[0x1]; 10200 u8 mcc[0x1]; 10201 u8 mcqi[0x1]; 10202 u8 mcqs[0x1]; 10203 10204 u8 regs_95_to_87[0x9]; 10205 u8 mpegc[0x1]; 10206 u8 mtutc[0x1]; 10207 u8 regs_84_to_68[0x11]; 10208 u8 tracer_registers[0x4]; 10209 10210 u8 regs_63_to_46[0x12]; 10211 u8 mrtc[0x1]; 10212 u8 regs_44_to_32[0xd]; 10213 10214 u8 regs_31_to_10[0x16]; 10215 u8 mtmp[0x1]; 10216 u8 regs_8_to_0[0x9]; 10217 }; 10218 10219 struct mlx5_ifc_mcam_access_reg_bits1 { 10220 u8 regs_127_to_96[0x20]; 10221 10222 u8 regs_95_to_64[0x20]; 10223 10224 u8 regs_63_to_32[0x20]; 10225 10226 u8 regs_31_to_0[0x20]; 10227 }; 10228 10229 struct mlx5_ifc_mcam_access_reg_bits2 { 10230 u8 regs_127_to_99[0x1d]; 10231 u8 mirc[0x1]; 10232 u8 regs_97_to_96[0x2]; 10233 10234 u8 regs_95_to_87[0x09]; 10235 u8 synce_registers[0x2]; 10236 u8 regs_84_to_64[0x15]; 10237 10238 u8 regs_63_to_32[0x20]; 10239 10240 u8 regs_31_to_0[0x20]; 10241 }; 10242 10243 struct mlx5_ifc_mcam_reg_bits { 10244 u8 reserved_at_0[0x8]; 10245 u8 feature_group[0x8]; 10246 u8 reserved_at_10[0x8]; 10247 u8 access_reg_group[0x8]; 10248 10249 u8 reserved_at_20[0x20]; 10250 10251 union { 10252 struct mlx5_ifc_mcam_access_reg_bits access_regs; 10253 struct mlx5_ifc_mcam_access_reg_bits1 access_regs1; 10254 struct mlx5_ifc_mcam_access_reg_bits2 access_regs2; 10255 u8 reserved_at_0[0x80]; 10256 } mng_access_reg_cap_mask; 10257 10258 u8 reserved_at_c0[0x80]; 10259 10260 union { 10261 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features; 10262 u8 reserved_at_0[0x80]; 10263 } mng_feature_cap_mask; 10264 10265 u8 reserved_at_1c0[0x80]; 10266 }; 10267 10268 struct mlx5_ifc_qcam_access_reg_cap_mask { 10269 u8 qcam_access_reg_cap_mask_127_to_20[0x6C]; 10270 u8 qpdpm[0x1]; 10271 u8 qcam_access_reg_cap_mask_18_to_4[0x0F]; 10272 u8 qdpm[0x1]; 10273 u8 qpts[0x1]; 10274 u8 qcap[0x1]; 10275 u8 qcam_access_reg_cap_mask_0[0x1]; 10276 }; 10277 10278 struct mlx5_ifc_qcam_qos_feature_cap_mask { 10279 u8 qcam_qos_feature_cap_mask_127_to_1[0x7F]; 10280 u8 qpts_trust_both[0x1]; 10281 }; 10282 10283 struct mlx5_ifc_qcam_reg_bits { 10284 u8 reserved_at_0[0x8]; 10285 u8 feature_group[0x8]; 10286 u8 reserved_at_10[0x8]; 10287 u8 access_reg_group[0x8]; 10288 u8 reserved_at_20[0x20]; 10289 10290 union { 10291 struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap; 10292 u8 reserved_at_0[0x80]; 10293 } qos_access_reg_cap_mask; 10294 10295 u8 reserved_at_c0[0x80]; 10296 10297 union { 10298 struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap; 10299 u8 reserved_at_0[0x80]; 10300 } qos_feature_cap_mask; 10301 10302 u8 reserved_at_1c0[0x80]; 10303 }; 10304 10305 struct mlx5_ifc_core_dump_reg_bits { 10306 u8 reserved_at_0[0x18]; 10307 u8 core_dump_type[0x8]; 10308 10309 u8 reserved_at_20[0x30]; 10310 u8 vhca_id[0x10]; 10311 10312 u8 reserved_at_60[0x8]; 10313 u8 qpn[0x18]; 10314 u8 reserved_at_80[0x180]; 10315 }; 10316 10317 struct mlx5_ifc_pcap_reg_bits { 10318 u8 reserved_at_0[0x8]; 10319 u8 local_port[0x8]; 10320 u8 reserved_at_10[0x10]; 10321 10322 u8 port_capability_mask[4][0x20]; 10323 }; 10324 10325 struct mlx5_ifc_paos_reg_bits { 10326 u8 swid[0x8]; 10327 u8 local_port[0x8]; 10328 u8 reserved_at_10[0x4]; 10329 u8 admin_status[0x4]; 10330 u8 reserved_at_18[0x4]; 10331 u8 oper_status[0x4]; 10332 10333 u8 ase[0x1]; 10334 u8 ee[0x1]; 10335 u8 reserved_at_22[0x1c]; 10336 u8 e[0x2]; 10337 10338 u8 reserved_at_40[0x40]; 10339 }; 10340 10341 struct mlx5_ifc_pamp_reg_bits { 10342 u8 reserved_at_0[0x8]; 10343 u8 opamp_group[0x8]; 10344 u8 reserved_at_10[0xc]; 10345 u8 opamp_group_type[0x4]; 10346 10347 u8 start_index[0x10]; 10348 u8 reserved_at_30[0x4]; 10349 u8 num_of_indices[0xc]; 10350 10351 u8 index_data[18][0x10]; 10352 }; 10353 10354 struct mlx5_ifc_pcmr_reg_bits { 10355 u8 reserved_at_0[0x8]; 10356 u8 local_port[0x8]; 10357 u8 reserved_at_10[0x10]; 10358 10359 u8 entropy_force_cap[0x1]; 10360 u8 entropy_calc_cap[0x1]; 10361 u8 entropy_gre_calc_cap[0x1]; 10362 u8 reserved_at_23[0xf]; 10363 u8 rx_ts_over_crc_cap[0x1]; 10364 u8 reserved_at_33[0xb]; 10365 u8 fcs_cap[0x1]; 10366 u8 reserved_at_3f[0x1]; 10367 10368 u8 entropy_force[0x1]; 10369 u8 entropy_calc[0x1]; 10370 u8 entropy_gre_calc[0x1]; 10371 u8 reserved_at_43[0xf]; 10372 u8 rx_ts_over_crc[0x1]; 10373 u8 reserved_at_53[0xb]; 10374 u8 fcs_chk[0x1]; 10375 u8 reserved_at_5f[0x1]; 10376 }; 10377 10378 struct mlx5_ifc_lane_2_module_mapping_bits { 10379 u8 reserved_at_0[0x4]; 10380 u8 rx_lane[0x4]; 10381 u8 reserved_at_8[0x4]; 10382 u8 tx_lane[0x4]; 10383 u8 reserved_at_10[0x8]; 10384 u8 module[0x8]; 10385 }; 10386 10387 struct mlx5_ifc_bufferx_reg_bits { 10388 u8 reserved_at_0[0x6]; 10389 u8 lossy[0x1]; 10390 u8 epsb[0x1]; 10391 u8 reserved_at_8[0x8]; 10392 u8 size[0x10]; 10393 10394 u8 xoff_threshold[0x10]; 10395 u8 xon_threshold[0x10]; 10396 }; 10397 10398 struct mlx5_ifc_set_node_in_bits { 10399 u8 node_description[64][0x8]; 10400 }; 10401 10402 struct mlx5_ifc_register_power_settings_bits { 10403 u8 reserved_at_0[0x18]; 10404 u8 power_settings_level[0x8]; 10405 10406 u8 reserved_at_20[0x60]; 10407 }; 10408 10409 struct mlx5_ifc_register_host_endianness_bits { 10410 u8 he[0x1]; 10411 u8 reserved_at_1[0x1f]; 10412 10413 u8 reserved_at_20[0x60]; 10414 }; 10415 10416 struct mlx5_ifc_umr_pointer_desc_argument_bits { 10417 u8 reserved_at_0[0x20]; 10418 10419 u8 mkey[0x20]; 10420 10421 u8 addressh_63_32[0x20]; 10422 10423 u8 addressl_31_0[0x20]; 10424 }; 10425 10426 struct mlx5_ifc_ud_adrs_vector_bits { 10427 u8 dc_key[0x40]; 10428 10429 u8 ext[0x1]; 10430 u8 reserved_at_41[0x7]; 10431 u8 destination_qp_dct[0x18]; 10432 10433 u8 static_rate[0x4]; 10434 u8 sl_eth_prio[0x4]; 10435 u8 fl[0x1]; 10436 u8 mlid[0x7]; 10437 u8 rlid_udp_sport[0x10]; 10438 10439 u8 reserved_at_80[0x20]; 10440 10441 u8 rmac_47_16[0x20]; 10442 10443 u8 rmac_15_0[0x10]; 10444 u8 tclass[0x8]; 10445 u8 hop_limit[0x8]; 10446 10447 u8 reserved_at_e0[0x1]; 10448 u8 grh[0x1]; 10449 u8 reserved_at_e2[0x2]; 10450 u8 src_addr_index[0x8]; 10451 u8 flow_label[0x14]; 10452 10453 u8 rgid_rip[16][0x8]; 10454 }; 10455 10456 struct mlx5_ifc_pages_req_event_bits { 10457 u8 reserved_at_0[0x10]; 10458 u8 function_id[0x10]; 10459 10460 u8 num_pages[0x20]; 10461 10462 u8 reserved_at_40[0xa0]; 10463 }; 10464 10465 struct mlx5_ifc_eqe_bits { 10466 u8 reserved_at_0[0x8]; 10467 u8 event_type[0x8]; 10468 u8 reserved_at_10[0x8]; 10469 u8 event_sub_type[0x8]; 10470 10471 u8 reserved_at_20[0xe0]; 10472 10473 union mlx5_ifc_event_auto_bits event_data; 10474 10475 u8 reserved_at_1e0[0x10]; 10476 u8 signature[0x8]; 10477 u8 reserved_at_1f8[0x7]; 10478 u8 owner[0x1]; 10479 }; 10480 10481 enum { 10482 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7, 10483 }; 10484 10485 struct mlx5_ifc_cmd_queue_entry_bits { 10486 u8 type[0x8]; 10487 u8 reserved_at_8[0x18]; 10488 10489 u8 input_length[0x20]; 10490 10491 u8 input_mailbox_pointer_63_32[0x20]; 10492 10493 u8 input_mailbox_pointer_31_9[0x17]; 10494 u8 reserved_at_77[0x9]; 10495 10496 u8 command_input_inline_data[16][0x8]; 10497 10498 u8 command_output_inline_data[16][0x8]; 10499 10500 u8 output_mailbox_pointer_63_32[0x20]; 10501 10502 u8 output_mailbox_pointer_31_9[0x17]; 10503 u8 reserved_at_1b7[0x9]; 10504 10505 u8 output_length[0x20]; 10506 10507 u8 token[0x8]; 10508 u8 signature[0x8]; 10509 u8 reserved_at_1f0[0x8]; 10510 u8 status[0x7]; 10511 u8 ownership[0x1]; 10512 }; 10513 10514 struct mlx5_ifc_cmd_out_bits { 10515 u8 status[0x8]; 10516 u8 reserved_at_8[0x18]; 10517 10518 u8 syndrome[0x20]; 10519 10520 u8 command_output[0x20]; 10521 }; 10522 10523 struct mlx5_ifc_cmd_in_bits { 10524 u8 opcode[0x10]; 10525 u8 reserved_at_10[0x10]; 10526 10527 u8 reserved_at_20[0x10]; 10528 u8 op_mod[0x10]; 10529 10530 u8 command[][0x20]; 10531 }; 10532 10533 struct mlx5_ifc_cmd_if_box_bits { 10534 u8 mailbox_data[512][0x8]; 10535 10536 u8 reserved_at_1000[0x180]; 10537 10538 u8 next_pointer_63_32[0x20]; 10539 10540 u8 next_pointer_31_10[0x16]; 10541 u8 reserved_at_11b6[0xa]; 10542 10543 u8 block_number[0x20]; 10544 10545 u8 reserved_at_11e0[0x8]; 10546 u8 token[0x8]; 10547 u8 ctrl_signature[0x8]; 10548 u8 signature[0x8]; 10549 }; 10550 10551 struct mlx5_ifc_mtt_bits { 10552 u8 ptag_63_32[0x20]; 10553 10554 u8 ptag_31_8[0x18]; 10555 u8 reserved_at_38[0x6]; 10556 u8 wr_en[0x1]; 10557 u8 rd_en[0x1]; 10558 }; 10559 10560 struct mlx5_ifc_query_wol_rol_out_bits { 10561 u8 status[0x8]; 10562 u8 reserved_at_8[0x18]; 10563 10564 u8 syndrome[0x20]; 10565 10566 u8 reserved_at_40[0x10]; 10567 u8 rol_mode[0x8]; 10568 u8 wol_mode[0x8]; 10569 10570 u8 reserved_at_60[0x20]; 10571 }; 10572 10573 struct mlx5_ifc_query_wol_rol_in_bits { 10574 u8 opcode[0x10]; 10575 u8 reserved_at_10[0x10]; 10576 10577 u8 reserved_at_20[0x10]; 10578 u8 op_mod[0x10]; 10579 10580 u8 reserved_at_40[0x40]; 10581 }; 10582 10583 struct mlx5_ifc_set_wol_rol_out_bits { 10584 u8 status[0x8]; 10585 u8 reserved_at_8[0x18]; 10586 10587 u8 syndrome[0x20]; 10588 10589 u8 reserved_at_40[0x40]; 10590 }; 10591 10592 struct mlx5_ifc_set_wol_rol_in_bits { 10593 u8 opcode[0x10]; 10594 u8 reserved_at_10[0x10]; 10595 10596 u8 reserved_at_20[0x10]; 10597 u8 op_mod[0x10]; 10598 10599 u8 rol_mode_valid[0x1]; 10600 u8 wol_mode_valid[0x1]; 10601 u8 reserved_at_42[0xe]; 10602 u8 rol_mode[0x8]; 10603 u8 wol_mode[0x8]; 10604 10605 u8 reserved_at_60[0x20]; 10606 }; 10607 10608 enum { 10609 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0, 10610 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1, 10611 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2, 10612 }; 10613 10614 enum { 10615 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0, 10616 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1, 10617 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2, 10618 }; 10619 10620 enum { 10621 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR = 0x1, 10622 MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC = 0x7, 10623 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR = 0x8, 10624 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR = 0x9, 10625 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR = 0xa, 10626 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR = 0xb, 10627 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN = 0xc, 10628 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR = 0xd, 10629 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV = 0xe, 10630 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR = 0xf, 10631 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR = 0x10, 10632 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PCI_POISONED_ERR = 0x12, 10633 }; 10634 10635 struct mlx5_ifc_initial_seg_bits { 10636 u8 fw_rev_minor[0x10]; 10637 u8 fw_rev_major[0x10]; 10638 10639 u8 cmd_interface_rev[0x10]; 10640 u8 fw_rev_subminor[0x10]; 10641 10642 u8 reserved_at_40[0x40]; 10643 10644 u8 cmdq_phy_addr_63_32[0x20]; 10645 10646 u8 cmdq_phy_addr_31_12[0x14]; 10647 u8 reserved_at_b4[0x2]; 10648 u8 nic_interface[0x2]; 10649 u8 log_cmdq_size[0x4]; 10650 u8 log_cmdq_stride[0x4]; 10651 10652 u8 command_doorbell_vector[0x20]; 10653 10654 u8 reserved_at_e0[0xf00]; 10655 10656 u8 initializing[0x1]; 10657 u8 reserved_at_fe1[0x4]; 10658 u8 nic_interface_supported[0x3]; 10659 u8 embedded_cpu[0x1]; 10660 u8 reserved_at_fe9[0x17]; 10661 10662 struct mlx5_ifc_health_buffer_bits health_buffer; 10663 10664 u8 no_dram_nic_offset[0x20]; 10665 10666 u8 reserved_at_1220[0x6e40]; 10667 10668 u8 reserved_at_8060[0x1f]; 10669 u8 clear_int[0x1]; 10670 10671 u8 health_syndrome[0x8]; 10672 u8 health_counter[0x18]; 10673 10674 u8 reserved_at_80a0[0x17fc0]; 10675 }; 10676 10677 struct mlx5_ifc_mtpps_reg_bits { 10678 u8 reserved_at_0[0xc]; 10679 u8 cap_number_of_pps_pins[0x4]; 10680 u8 reserved_at_10[0x4]; 10681 u8 cap_max_num_of_pps_in_pins[0x4]; 10682 u8 reserved_at_18[0x4]; 10683 u8 cap_max_num_of_pps_out_pins[0x4]; 10684 10685 u8 reserved_at_20[0x13]; 10686 u8 cap_log_min_npps_period[0x5]; 10687 u8 reserved_at_38[0x3]; 10688 u8 cap_log_min_out_pulse_duration_ns[0x5]; 10689 10690 u8 reserved_at_40[0x4]; 10691 u8 cap_pin_3_mode[0x4]; 10692 u8 reserved_at_48[0x4]; 10693 u8 cap_pin_2_mode[0x4]; 10694 u8 reserved_at_50[0x4]; 10695 u8 cap_pin_1_mode[0x4]; 10696 u8 reserved_at_58[0x4]; 10697 u8 cap_pin_0_mode[0x4]; 10698 10699 u8 reserved_at_60[0x4]; 10700 u8 cap_pin_7_mode[0x4]; 10701 u8 reserved_at_68[0x4]; 10702 u8 cap_pin_6_mode[0x4]; 10703 u8 reserved_at_70[0x4]; 10704 u8 cap_pin_5_mode[0x4]; 10705 u8 reserved_at_78[0x4]; 10706 u8 cap_pin_4_mode[0x4]; 10707 10708 u8 field_select[0x20]; 10709 u8 reserved_at_a0[0x20]; 10710 10711 u8 npps_period[0x40]; 10712 10713 u8 enable[0x1]; 10714 u8 reserved_at_101[0xb]; 10715 u8 pattern[0x4]; 10716 u8 reserved_at_110[0x4]; 10717 u8 pin_mode[0x4]; 10718 u8 pin[0x8]; 10719 10720 u8 reserved_at_120[0x2]; 10721 u8 out_pulse_duration_ns[0x1e]; 10722 10723 u8 time_stamp[0x40]; 10724 10725 u8 out_pulse_duration[0x10]; 10726 u8 out_periodic_adjustment[0x10]; 10727 u8 enhanced_out_periodic_adjustment[0x20]; 10728 10729 u8 reserved_at_1c0[0x20]; 10730 }; 10731 10732 struct mlx5_ifc_mtppse_reg_bits { 10733 u8 reserved_at_0[0x18]; 10734 u8 pin[0x8]; 10735 u8 event_arm[0x1]; 10736 u8 reserved_at_21[0x1b]; 10737 u8 event_generation_mode[0x4]; 10738 u8 reserved_at_40[0x40]; 10739 }; 10740 10741 struct mlx5_ifc_mcqs_reg_bits { 10742 u8 last_index_flag[0x1]; 10743 u8 reserved_at_1[0x7]; 10744 u8 fw_device[0x8]; 10745 u8 component_index[0x10]; 10746 10747 u8 reserved_at_20[0x10]; 10748 u8 identifier[0x10]; 10749 10750 u8 reserved_at_40[0x17]; 10751 u8 component_status[0x5]; 10752 u8 component_update_state[0x4]; 10753 10754 u8 last_update_state_changer_type[0x4]; 10755 u8 last_update_state_changer_host_id[0x4]; 10756 u8 reserved_at_68[0x18]; 10757 }; 10758 10759 struct mlx5_ifc_mcqi_cap_bits { 10760 u8 supported_info_bitmask[0x20]; 10761 10762 u8 component_size[0x20]; 10763 10764 u8 max_component_size[0x20]; 10765 10766 u8 log_mcda_word_size[0x4]; 10767 u8 reserved_at_64[0xc]; 10768 u8 mcda_max_write_size[0x10]; 10769 10770 u8 rd_en[0x1]; 10771 u8 reserved_at_81[0x1]; 10772 u8 match_chip_id[0x1]; 10773 u8 match_psid[0x1]; 10774 u8 check_user_timestamp[0x1]; 10775 u8 match_base_guid_mac[0x1]; 10776 u8 reserved_at_86[0x1a]; 10777 }; 10778 10779 struct mlx5_ifc_mcqi_version_bits { 10780 u8 reserved_at_0[0x2]; 10781 u8 build_time_valid[0x1]; 10782 u8 user_defined_time_valid[0x1]; 10783 u8 reserved_at_4[0x14]; 10784 u8 version_string_length[0x8]; 10785 10786 u8 version[0x20]; 10787 10788 u8 build_time[0x40]; 10789 10790 u8 user_defined_time[0x40]; 10791 10792 u8 build_tool_version[0x20]; 10793 10794 u8 reserved_at_e0[0x20]; 10795 10796 u8 version_string[92][0x8]; 10797 }; 10798 10799 struct mlx5_ifc_mcqi_activation_method_bits { 10800 u8 pending_server_ac_power_cycle[0x1]; 10801 u8 pending_server_dc_power_cycle[0x1]; 10802 u8 pending_server_reboot[0x1]; 10803 u8 pending_fw_reset[0x1]; 10804 u8 auto_activate[0x1]; 10805 u8 all_hosts_sync[0x1]; 10806 u8 device_hw_reset[0x1]; 10807 u8 reserved_at_7[0x19]; 10808 }; 10809 10810 union mlx5_ifc_mcqi_reg_data_bits { 10811 struct mlx5_ifc_mcqi_cap_bits mcqi_caps; 10812 struct mlx5_ifc_mcqi_version_bits mcqi_version; 10813 struct mlx5_ifc_mcqi_activation_method_bits mcqi_activation_mathod; 10814 }; 10815 10816 struct mlx5_ifc_mcqi_reg_bits { 10817 u8 read_pending_component[0x1]; 10818 u8 reserved_at_1[0xf]; 10819 u8 component_index[0x10]; 10820 10821 u8 reserved_at_20[0x20]; 10822 10823 u8 reserved_at_40[0x1b]; 10824 u8 info_type[0x5]; 10825 10826 u8 info_size[0x20]; 10827 10828 u8 offset[0x20]; 10829 10830 u8 reserved_at_a0[0x10]; 10831 u8 data_size[0x10]; 10832 10833 union mlx5_ifc_mcqi_reg_data_bits data[]; 10834 }; 10835 10836 struct mlx5_ifc_mcc_reg_bits { 10837 u8 reserved_at_0[0x4]; 10838 u8 time_elapsed_since_last_cmd[0xc]; 10839 u8 reserved_at_10[0x8]; 10840 u8 instruction[0x8]; 10841 10842 u8 reserved_at_20[0x10]; 10843 u8 component_index[0x10]; 10844 10845 u8 reserved_at_40[0x8]; 10846 u8 update_handle[0x18]; 10847 10848 u8 handle_owner_type[0x4]; 10849 u8 handle_owner_host_id[0x4]; 10850 u8 reserved_at_68[0x1]; 10851 u8 control_progress[0x7]; 10852 u8 error_code[0x8]; 10853 u8 reserved_at_78[0x4]; 10854 u8 control_state[0x4]; 10855 10856 u8 component_size[0x20]; 10857 10858 u8 reserved_at_a0[0x60]; 10859 }; 10860 10861 struct mlx5_ifc_mcda_reg_bits { 10862 u8 reserved_at_0[0x8]; 10863 u8 update_handle[0x18]; 10864 10865 u8 offset[0x20]; 10866 10867 u8 reserved_at_40[0x10]; 10868 u8 size[0x10]; 10869 10870 u8 reserved_at_60[0x20]; 10871 10872 u8 data[][0x20]; 10873 }; 10874 10875 enum { 10876 MLX5_MFRL_REG_RESET_STATE_IDLE = 0, 10877 MLX5_MFRL_REG_RESET_STATE_IN_NEGOTIATION = 1, 10878 MLX5_MFRL_REG_RESET_STATE_RESET_IN_PROGRESS = 2, 10879 MLX5_MFRL_REG_RESET_STATE_NEG_TIMEOUT = 3, 10880 MLX5_MFRL_REG_RESET_STATE_NACK = 4, 10881 MLX5_MFRL_REG_RESET_STATE_UNLOAD_TIMEOUT = 5, 10882 }; 10883 10884 enum { 10885 MLX5_MFRL_REG_RESET_TYPE_FULL_CHIP = BIT(0), 10886 MLX5_MFRL_REG_RESET_TYPE_NET_PORT_ALIVE = BIT(1), 10887 }; 10888 10889 enum { 10890 MLX5_MFRL_REG_RESET_LEVEL0 = BIT(0), 10891 MLX5_MFRL_REG_RESET_LEVEL3 = BIT(3), 10892 MLX5_MFRL_REG_RESET_LEVEL6 = BIT(6), 10893 }; 10894 10895 struct mlx5_ifc_mfrl_reg_bits { 10896 u8 reserved_at_0[0x20]; 10897 10898 u8 reserved_at_20[0x2]; 10899 u8 pci_sync_for_fw_update_start[0x1]; 10900 u8 pci_sync_for_fw_update_resp[0x2]; 10901 u8 rst_type_sel[0x3]; 10902 u8 reserved_at_28[0x4]; 10903 u8 reset_state[0x4]; 10904 u8 reset_type[0x8]; 10905 u8 reset_level[0x8]; 10906 }; 10907 10908 struct mlx5_ifc_mirc_reg_bits { 10909 u8 reserved_at_0[0x18]; 10910 u8 status_code[0x8]; 10911 10912 u8 reserved_at_20[0x20]; 10913 }; 10914 10915 struct mlx5_ifc_pddr_monitor_opcode_bits { 10916 u8 reserved_at_0[0x10]; 10917 u8 monitor_opcode[0x10]; 10918 }; 10919 10920 union mlx5_ifc_pddr_troubleshooting_page_status_opcode_auto_bits { 10921 struct mlx5_ifc_pddr_monitor_opcode_bits pddr_monitor_opcode; 10922 u8 reserved_at_0[0x20]; 10923 }; 10924 10925 enum { 10926 /* Monitor opcodes */ 10927 MLX5_PDDR_REG_TRBLSH_GROUP_OPCODE_MONITOR = 0x0, 10928 }; 10929 10930 struct mlx5_ifc_pddr_troubleshooting_page_bits { 10931 u8 reserved_at_0[0x10]; 10932 u8 group_opcode[0x10]; 10933 10934 union mlx5_ifc_pddr_troubleshooting_page_status_opcode_auto_bits status_opcode; 10935 10936 u8 reserved_at_40[0x20]; 10937 10938 u8 status_message[59][0x20]; 10939 }; 10940 10941 union mlx5_ifc_pddr_reg_page_data_auto_bits { 10942 struct mlx5_ifc_pddr_troubleshooting_page_bits pddr_troubleshooting_page; 10943 u8 reserved_at_0[0x7c0]; 10944 }; 10945 10946 enum { 10947 MLX5_PDDR_REG_PAGE_SELECT_TROUBLESHOOTING_INFO_PAGE = 0x1, 10948 }; 10949 10950 struct mlx5_ifc_pddr_reg_bits { 10951 u8 reserved_at_0[0x8]; 10952 u8 local_port[0x8]; 10953 u8 pnat[0x2]; 10954 u8 reserved_at_12[0xe]; 10955 10956 u8 reserved_at_20[0x18]; 10957 u8 page_select[0x8]; 10958 10959 union mlx5_ifc_pddr_reg_page_data_auto_bits page_data; 10960 }; 10961 10962 struct mlx5_ifc_mrtc_reg_bits { 10963 u8 time_synced[0x1]; 10964 u8 reserved_at_1[0x1f]; 10965 10966 u8 reserved_at_20[0x20]; 10967 10968 u8 time_h[0x20]; 10969 10970 u8 time_l[0x20]; 10971 }; 10972 10973 struct mlx5_ifc_mtcap_reg_bits { 10974 u8 reserved_at_0[0x19]; 10975 u8 sensor_count[0x7]; 10976 10977 u8 reserved_at_20[0x20]; 10978 10979 u8 sensor_map[0x40]; 10980 }; 10981 10982 struct mlx5_ifc_mtmp_reg_bits { 10983 u8 reserved_at_0[0x14]; 10984 u8 sensor_index[0xc]; 10985 10986 u8 reserved_at_20[0x10]; 10987 u8 temperature[0x10]; 10988 10989 u8 mte[0x1]; 10990 u8 mtr[0x1]; 10991 u8 reserved_at_42[0xe]; 10992 u8 max_temperature[0x10]; 10993 10994 u8 tee[0x2]; 10995 u8 reserved_at_62[0xe]; 10996 u8 temp_threshold_hi[0x10]; 10997 10998 u8 reserved_at_80[0x10]; 10999 u8 temp_threshold_lo[0x10]; 11000 11001 u8 reserved_at_a0[0x20]; 11002 11003 u8 sensor_name_hi[0x20]; 11004 u8 sensor_name_lo[0x20]; 11005 }; 11006 11007 union mlx5_ifc_ports_control_registers_document_bits { 11008 struct mlx5_ifc_bufferx_reg_bits bufferx_reg; 11009 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 11010 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 11011 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 11012 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 11013 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 11014 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 11015 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout; 11016 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout; 11017 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping; 11018 struct mlx5_ifc_pamp_reg_bits pamp_reg; 11019 struct mlx5_ifc_paos_reg_bits paos_reg; 11020 struct mlx5_ifc_pcap_reg_bits pcap_reg; 11021 struct mlx5_ifc_pddr_monitor_opcode_bits pddr_monitor_opcode; 11022 struct mlx5_ifc_pddr_reg_bits pddr_reg; 11023 struct mlx5_ifc_pddr_troubleshooting_page_bits pddr_troubleshooting_page; 11024 struct mlx5_ifc_peir_reg_bits peir_reg; 11025 struct mlx5_ifc_pelc_reg_bits pelc_reg; 11026 struct mlx5_ifc_pfcc_reg_bits pfcc_reg; 11027 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 11028 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 11029 struct mlx5_ifc_pifr_reg_bits pifr_reg; 11030 struct mlx5_ifc_pipg_reg_bits pipg_reg; 11031 struct mlx5_ifc_plbf_reg_bits plbf_reg; 11032 struct mlx5_ifc_plib_reg_bits plib_reg; 11033 struct mlx5_ifc_plpc_reg_bits plpc_reg; 11034 struct mlx5_ifc_pmaos_reg_bits pmaos_reg; 11035 struct mlx5_ifc_pmlp_reg_bits pmlp_reg; 11036 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg; 11037 struct mlx5_ifc_pmpc_reg_bits pmpc_reg; 11038 struct mlx5_ifc_pmpe_reg_bits pmpe_reg; 11039 struct mlx5_ifc_pmpr_reg_bits pmpr_reg; 11040 struct mlx5_ifc_pmtu_reg_bits pmtu_reg; 11041 struct mlx5_ifc_ppad_reg_bits ppad_reg; 11042 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg; 11043 struct mlx5_ifc_mpein_reg_bits mpein_reg; 11044 struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg; 11045 struct mlx5_ifc_pplm_reg_bits pplm_reg; 11046 struct mlx5_ifc_pplr_reg_bits pplr_reg; 11047 struct mlx5_ifc_ppsc_reg_bits ppsc_reg; 11048 struct mlx5_ifc_pqdr_reg_bits pqdr_reg; 11049 struct mlx5_ifc_pspa_reg_bits pspa_reg; 11050 struct mlx5_ifc_ptas_reg_bits ptas_reg; 11051 struct mlx5_ifc_ptys_reg_bits ptys_reg; 11052 struct mlx5_ifc_mlcr_reg_bits mlcr_reg; 11053 struct mlx5_ifc_pude_reg_bits pude_reg; 11054 struct mlx5_ifc_pvlc_reg_bits pvlc_reg; 11055 struct mlx5_ifc_slrg_reg_bits slrg_reg; 11056 struct mlx5_ifc_sltp_reg_bits sltp_reg; 11057 struct mlx5_ifc_mtpps_reg_bits mtpps_reg; 11058 struct mlx5_ifc_mtppse_reg_bits mtppse_reg; 11059 struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg; 11060 struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits; 11061 struct mlx5_ifc_fpga_cap_bits fpga_cap_bits; 11062 struct mlx5_ifc_mcqi_reg_bits mcqi_reg; 11063 struct mlx5_ifc_mcc_reg_bits mcc_reg; 11064 struct mlx5_ifc_mcda_reg_bits mcda_reg; 11065 struct mlx5_ifc_mirc_reg_bits mirc_reg; 11066 struct mlx5_ifc_mfrl_reg_bits mfrl_reg; 11067 struct mlx5_ifc_mtutc_reg_bits mtutc_reg; 11068 struct mlx5_ifc_mrtc_reg_bits mrtc_reg; 11069 struct mlx5_ifc_mtcap_reg_bits mtcap_reg; 11070 struct mlx5_ifc_mtmp_reg_bits mtmp_reg; 11071 u8 reserved_at_0[0x60e0]; 11072 }; 11073 11074 union mlx5_ifc_debug_enhancements_document_bits { 11075 struct mlx5_ifc_health_buffer_bits health_buffer; 11076 u8 reserved_at_0[0x200]; 11077 }; 11078 11079 union mlx5_ifc_uplink_pci_interface_document_bits { 11080 struct mlx5_ifc_initial_seg_bits initial_seg; 11081 u8 reserved_at_0[0x20060]; 11082 }; 11083 11084 struct mlx5_ifc_set_flow_table_root_out_bits { 11085 u8 status[0x8]; 11086 u8 reserved_at_8[0x18]; 11087 11088 u8 syndrome[0x20]; 11089 11090 u8 reserved_at_40[0x40]; 11091 }; 11092 11093 struct mlx5_ifc_set_flow_table_root_in_bits { 11094 u8 opcode[0x10]; 11095 u8 reserved_at_10[0x10]; 11096 11097 u8 reserved_at_20[0x10]; 11098 u8 op_mod[0x10]; 11099 11100 u8 other_vport[0x1]; 11101 u8 reserved_at_41[0xf]; 11102 u8 vport_number[0x10]; 11103 11104 u8 reserved_at_60[0x20]; 11105 11106 u8 table_type[0x8]; 11107 u8 reserved_at_88[0x7]; 11108 u8 table_of_other_vport[0x1]; 11109 u8 table_vport_number[0x10]; 11110 11111 u8 reserved_at_a0[0x8]; 11112 u8 table_id[0x18]; 11113 11114 u8 reserved_at_c0[0x8]; 11115 u8 underlay_qpn[0x18]; 11116 u8 table_eswitch_owner_vhca_id_valid[0x1]; 11117 u8 reserved_at_e1[0xf]; 11118 u8 table_eswitch_owner_vhca_id[0x10]; 11119 u8 reserved_at_100[0x100]; 11120 }; 11121 11122 enum { 11123 MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = (1UL << 0), 11124 MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15), 11125 }; 11126 11127 struct mlx5_ifc_modify_flow_table_out_bits { 11128 u8 status[0x8]; 11129 u8 reserved_at_8[0x18]; 11130 11131 u8 syndrome[0x20]; 11132 11133 u8 reserved_at_40[0x40]; 11134 }; 11135 11136 struct mlx5_ifc_modify_flow_table_in_bits { 11137 u8 opcode[0x10]; 11138 u8 reserved_at_10[0x10]; 11139 11140 u8 reserved_at_20[0x10]; 11141 u8 op_mod[0x10]; 11142 11143 u8 other_vport[0x1]; 11144 u8 reserved_at_41[0xf]; 11145 u8 vport_number[0x10]; 11146 11147 u8 reserved_at_60[0x10]; 11148 u8 modify_field_select[0x10]; 11149 11150 u8 table_type[0x8]; 11151 u8 reserved_at_88[0x18]; 11152 11153 u8 reserved_at_a0[0x8]; 11154 u8 table_id[0x18]; 11155 11156 struct mlx5_ifc_flow_table_context_bits flow_table_context; 11157 }; 11158 11159 struct mlx5_ifc_ets_tcn_config_reg_bits { 11160 u8 g[0x1]; 11161 u8 b[0x1]; 11162 u8 r[0x1]; 11163 u8 reserved_at_3[0x9]; 11164 u8 group[0x4]; 11165 u8 reserved_at_10[0x9]; 11166 u8 bw_allocation[0x7]; 11167 11168 u8 reserved_at_20[0xc]; 11169 u8 max_bw_units[0x4]; 11170 u8 reserved_at_30[0x8]; 11171 u8 max_bw_value[0x8]; 11172 }; 11173 11174 struct mlx5_ifc_ets_global_config_reg_bits { 11175 u8 reserved_at_0[0x2]; 11176 u8 r[0x1]; 11177 u8 reserved_at_3[0x1d]; 11178 11179 u8 reserved_at_20[0xc]; 11180 u8 max_bw_units[0x4]; 11181 u8 reserved_at_30[0x8]; 11182 u8 max_bw_value[0x8]; 11183 }; 11184 11185 struct mlx5_ifc_qetc_reg_bits { 11186 u8 reserved_at_0[0x8]; 11187 u8 port_number[0x8]; 11188 u8 reserved_at_10[0x30]; 11189 11190 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8]; 11191 struct mlx5_ifc_ets_global_config_reg_bits global_configuration; 11192 }; 11193 11194 struct mlx5_ifc_qpdpm_dscp_reg_bits { 11195 u8 e[0x1]; 11196 u8 reserved_at_01[0x0b]; 11197 u8 prio[0x04]; 11198 }; 11199 11200 struct mlx5_ifc_qpdpm_reg_bits { 11201 u8 reserved_at_0[0x8]; 11202 u8 local_port[0x8]; 11203 u8 reserved_at_10[0x10]; 11204 struct mlx5_ifc_qpdpm_dscp_reg_bits dscp[64]; 11205 }; 11206 11207 struct mlx5_ifc_qpts_reg_bits { 11208 u8 reserved_at_0[0x8]; 11209 u8 local_port[0x8]; 11210 u8 reserved_at_10[0x2d]; 11211 u8 trust_state[0x3]; 11212 }; 11213 11214 struct mlx5_ifc_pptb_reg_bits { 11215 u8 reserved_at_0[0x2]; 11216 u8 mm[0x2]; 11217 u8 reserved_at_4[0x4]; 11218 u8 local_port[0x8]; 11219 u8 reserved_at_10[0x6]; 11220 u8 cm[0x1]; 11221 u8 um[0x1]; 11222 u8 pm[0x8]; 11223 11224 u8 prio_x_buff[0x20]; 11225 11226 u8 pm_msb[0x8]; 11227 u8 reserved_at_48[0x10]; 11228 u8 ctrl_buff[0x4]; 11229 u8 untagged_buff[0x4]; 11230 }; 11231 11232 struct mlx5_ifc_sbcam_reg_bits { 11233 u8 reserved_at_0[0x8]; 11234 u8 feature_group[0x8]; 11235 u8 reserved_at_10[0x8]; 11236 u8 access_reg_group[0x8]; 11237 11238 u8 reserved_at_20[0x20]; 11239 11240 u8 sb_access_reg_cap_mask[4][0x20]; 11241 11242 u8 reserved_at_c0[0x80]; 11243 11244 u8 sb_feature_cap_mask[4][0x20]; 11245 11246 u8 reserved_at_1c0[0x40]; 11247 11248 u8 cap_total_buffer_size[0x20]; 11249 11250 u8 cap_cell_size[0x10]; 11251 u8 cap_max_pg_buffers[0x8]; 11252 u8 cap_num_pool_supported[0x8]; 11253 11254 u8 reserved_at_240[0x8]; 11255 u8 cap_sbsr_stat_size[0x8]; 11256 u8 cap_max_tclass_data[0x8]; 11257 u8 cap_max_cpu_ingress_tclass_sb[0x8]; 11258 }; 11259 11260 struct mlx5_ifc_pbmc_reg_bits { 11261 u8 reserved_at_0[0x8]; 11262 u8 local_port[0x8]; 11263 u8 reserved_at_10[0x10]; 11264 11265 u8 xoff_timer_value[0x10]; 11266 u8 xoff_refresh[0x10]; 11267 11268 u8 reserved_at_40[0x9]; 11269 u8 fullness_threshold[0x7]; 11270 u8 port_buffer_size[0x10]; 11271 11272 struct mlx5_ifc_bufferx_reg_bits buffer[10]; 11273 11274 u8 reserved_at_2e0[0x80]; 11275 }; 11276 11277 struct mlx5_ifc_sbpr_reg_bits { 11278 u8 desc[0x1]; 11279 u8 snap[0x1]; 11280 u8 reserved_at_2[0x4]; 11281 u8 dir[0x2]; 11282 u8 reserved_at_8[0x14]; 11283 u8 pool[0x4]; 11284 11285 u8 infi_size[0x1]; 11286 u8 reserved_at_21[0x7]; 11287 u8 size[0x18]; 11288 11289 u8 reserved_at_40[0x1c]; 11290 u8 mode[0x4]; 11291 11292 u8 reserved_at_60[0x8]; 11293 u8 buff_occupancy[0x18]; 11294 11295 u8 clr[0x1]; 11296 u8 reserved_at_81[0x7]; 11297 u8 max_buff_occupancy[0x18]; 11298 11299 u8 reserved_at_a0[0x8]; 11300 u8 ext_buff_occupancy[0x18]; 11301 }; 11302 11303 struct mlx5_ifc_sbcm_reg_bits { 11304 u8 desc[0x1]; 11305 u8 snap[0x1]; 11306 u8 reserved_at_2[0x6]; 11307 u8 local_port[0x8]; 11308 u8 pnat[0x2]; 11309 u8 pg_buff[0x6]; 11310 u8 reserved_at_18[0x6]; 11311 u8 dir[0x2]; 11312 11313 u8 reserved_at_20[0x1f]; 11314 u8 exc[0x1]; 11315 11316 u8 reserved_at_40[0x40]; 11317 11318 u8 reserved_at_80[0x8]; 11319 u8 buff_occupancy[0x18]; 11320 11321 u8 clr[0x1]; 11322 u8 reserved_at_a1[0x7]; 11323 u8 max_buff_occupancy[0x18]; 11324 11325 u8 reserved_at_c0[0x8]; 11326 u8 min_buff[0x18]; 11327 11328 u8 infi_max[0x1]; 11329 u8 reserved_at_e1[0x7]; 11330 u8 max_buff[0x18]; 11331 11332 u8 reserved_at_100[0x20]; 11333 11334 u8 reserved_at_120[0x1c]; 11335 u8 pool[0x4]; 11336 }; 11337 11338 struct mlx5_ifc_qtct_reg_bits { 11339 u8 reserved_at_0[0x8]; 11340 u8 port_number[0x8]; 11341 u8 reserved_at_10[0xd]; 11342 u8 prio[0x3]; 11343 11344 u8 reserved_at_20[0x1d]; 11345 u8 tclass[0x3]; 11346 }; 11347 11348 struct mlx5_ifc_mcia_reg_bits { 11349 u8 l[0x1]; 11350 u8 reserved_at_1[0x7]; 11351 u8 module[0x8]; 11352 u8 reserved_at_10[0x8]; 11353 u8 status[0x8]; 11354 11355 u8 i2c_device_address[0x8]; 11356 u8 page_number[0x8]; 11357 u8 device_address[0x10]; 11358 11359 u8 reserved_at_40[0x10]; 11360 u8 size[0x10]; 11361 11362 u8 reserved_at_60[0x20]; 11363 11364 u8 dword_0[0x20]; 11365 u8 dword_1[0x20]; 11366 u8 dword_2[0x20]; 11367 u8 dword_3[0x20]; 11368 u8 dword_4[0x20]; 11369 u8 dword_5[0x20]; 11370 u8 dword_6[0x20]; 11371 u8 dword_7[0x20]; 11372 u8 dword_8[0x20]; 11373 u8 dword_9[0x20]; 11374 u8 dword_10[0x20]; 11375 u8 dword_11[0x20]; 11376 }; 11377 11378 struct mlx5_ifc_dcbx_param_bits { 11379 u8 dcbx_cee_cap[0x1]; 11380 u8 dcbx_ieee_cap[0x1]; 11381 u8 dcbx_standby_cap[0x1]; 11382 u8 reserved_at_3[0x5]; 11383 u8 port_number[0x8]; 11384 u8 reserved_at_10[0xa]; 11385 u8 max_application_table_size[6]; 11386 u8 reserved_at_20[0x15]; 11387 u8 version_oper[0x3]; 11388 u8 reserved_at_38[5]; 11389 u8 version_admin[0x3]; 11390 u8 willing_admin[0x1]; 11391 u8 reserved_at_41[0x3]; 11392 u8 pfc_cap_oper[0x4]; 11393 u8 reserved_at_48[0x4]; 11394 u8 pfc_cap_admin[0x4]; 11395 u8 reserved_at_50[0x4]; 11396 u8 num_of_tc_oper[0x4]; 11397 u8 reserved_at_58[0x4]; 11398 u8 num_of_tc_admin[0x4]; 11399 u8 remote_willing[0x1]; 11400 u8 reserved_at_61[3]; 11401 u8 remote_pfc_cap[4]; 11402 u8 reserved_at_68[0x14]; 11403 u8 remote_num_of_tc[0x4]; 11404 u8 reserved_at_80[0x18]; 11405 u8 error[0x8]; 11406 u8 reserved_at_a0[0x160]; 11407 }; 11408 11409 enum { 11410 MLX5_LAG_PORT_SELECT_MODE_QUEUE_AFFINITY = 0, 11411 MLX5_LAG_PORT_SELECT_MODE_PORT_SELECT_FT = 1, 11412 MLX5_LAG_PORT_SELECT_MODE_PORT_SELECT_MPESW = 2, 11413 }; 11414 11415 struct mlx5_ifc_lagc_bits { 11416 u8 fdb_selection_mode[0x1]; 11417 u8 reserved_at_1[0x14]; 11418 u8 port_select_mode[0x3]; 11419 u8 reserved_at_18[0x5]; 11420 u8 lag_state[0x3]; 11421 11422 u8 reserved_at_20[0xc]; 11423 u8 active_port[0x4]; 11424 u8 reserved_at_30[0x4]; 11425 u8 tx_remap_affinity_2[0x4]; 11426 u8 reserved_at_38[0x4]; 11427 u8 tx_remap_affinity_1[0x4]; 11428 }; 11429 11430 struct mlx5_ifc_create_lag_out_bits { 11431 u8 status[0x8]; 11432 u8 reserved_at_8[0x18]; 11433 11434 u8 syndrome[0x20]; 11435 11436 u8 reserved_at_40[0x40]; 11437 }; 11438 11439 struct mlx5_ifc_create_lag_in_bits { 11440 u8 opcode[0x10]; 11441 u8 reserved_at_10[0x10]; 11442 11443 u8 reserved_at_20[0x10]; 11444 u8 op_mod[0x10]; 11445 11446 struct mlx5_ifc_lagc_bits ctx; 11447 }; 11448 11449 struct mlx5_ifc_modify_lag_out_bits { 11450 u8 status[0x8]; 11451 u8 reserved_at_8[0x18]; 11452 11453 u8 syndrome[0x20]; 11454 11455 u8 reserved_at_40[0x40]; 11456 }; 11457 11458 struct mlx5_ifc_modify_lag_in_bits { 11459 u8 opcode[0x10]; 11460 u8 reserved_at_10[0x10]; 11461 11462 u8 reserved_at_20[0x10]; 11463 u8 op_mod[0x10]; 11464 11465 u8 reserved_at_40[0x20]; 11466 u8 field_select[0x20]; 11467 11468 struct mlx5_ifc_lagc_bits ctx; 11469 }; 11470 11471 struct mlx5_ifc_query_lag_out_bits { 11472 u8 status[0x8]; 11473 u8 reserved_at_8[0x18]; 11474 11475 u8 syndrome[0x20]; 11476 11477 struct mlx5_ifc_lagc_bits ctx; 11478 }; 11479 11480 struct mlx5_ifc_query_lag_in_bits { 11481 u8 opcode[0x10]; 11482 u8 reserved_at_10[0x10]; 11483 11484 u8 reserved_at_20[0x10]; 11485 u8 op_mod[0x10]; 11486 11487 u8 reserved_at_40[0x40]; 11488 }; 11489 11490 struct mlx5_ifc_destroy_lag_out_bits { 11491 u8 status[0x8]; 11492 u8 reserved_at_8[0x18]; 11493 11494 u8 syndrome[0x20]; 11495 11496 u8 reserved_at_40[0x40]; 11497 }; 11498 11499 struct mlx5_ifc_destroy_lag_in_bits { 11500 u8 opcode[0x10]; 11501 u8 reserved_at_10[0x10]; 11502 11503 u8 reserved_at_20[0x10]; 11504 u8 op_mod[0x10]; 11505 11506 u8 reserved_at_40[0x40]; 11507 }; 11508 11509 struct mlx5_ifc_create_vport_lag_out_bits { 11510 u8 status[0x8]; 11511 u8 reserved_at_8[0x18]; 11512 11513 u8 syndrome[0x20]; 11514 11515 u8 reserved_at_40[0x40]; 11516 }; 11517 11518 struct mlx5_ifc_create_vport_lag_in_bits { 11519 u8 opcode[0x10]; 11520 u8 reserved_at_10[0x10]; 11521 11522 u8 reserved_at_20[0x10]; 11523 u8 op_mod[0x10]; 11524 11525 u8 reserved_at_40[0x40]; 11526 }; 11527 11528 struct mlx5_ifc_destroy_vport_lag_out_bits { 11529 u8 status[0x8]; 11530 u8 reserved_at_8[0x18]; 11531 11532 u8 syndrome[0x20]; 11533 11534 u8 reserved_at_40[0x40]; 11535 }; 11536 11537 struct mlx5_ifc_destroy_vport_lag_in_bits { 11538 u8 opcode[0x10]; 11539 u8 reserved_at_10[0x10]; 11540 11541 u8 reserved_at_20[0x10]; 11542 u8 op_mod[0x10]; 11543 11544 u8 reserved_at_40[0x40]; 11545 }; 11546 11547 enum { 11548 MLX5_MODIFY_MEMIC_OP_MOD_ALLOC, 11549 MLX5_MODIFY_MEMIC_OP_MOD_DEALLOC, 11550 }; 11551 11552 struct mlx5_ifc_modify_memic_in_bits { 11553 u8 opcode[0x10]; 11554 u8 uid[0x10]; 11555 11556 u8 reserved_at_20[0x10]; 11557 u8 op_mod[0x10]; 11558 11559 u8 reserved_at_40[0x20]; 11560 11561 u8 reserved_at_60[0x18]; 11562 u8 memic_operation_type[0x8]; 11563 11564 u8 memic_start_addr[0x40]; 11565 11566 u8 reserved_at_c0[0x140]; 11567 }; 11568 11569 struct mlx5_ifc_modify_memic_out_bits { 11570 u8 status[0x8]; 11571 u8 reserved_at_8[0x18]; 11572 11573 u8 syndrome[0x20]; 11574 11575 u8 reserved_at_40[0x40]; 11576 11577 u8 memic_operation_addr[0x40]; 11578 11579 u8 reserved_at_c0[0x140]; 11580 }; 11581 11582 struct mlx5_ifc_alloc_memic_in_bits { 11583 u8 opcode[0x10]; 11584 u8 reserved_at_10[0x10]; 11585 11586 u8 reserved_at_20[0x10]; 11587 u8 op_mod[0x10]; 11588 11589 u8 reserved_at_30[0x20]; 11590 11591 u8 reserved_at_40[0x18]; 11592 u8 log_memic_addr_alignment[0x8]; 11593 11594 u8 range_start_addr[0x40]; 11595 11596 u8 range_size[0x20]; 11597 11598 u8 memic_size[0x20]; 11599 }; 11600 11601 struct mlx5_ifc_alloc_memic_out_bits { 11602 u8 status[0x8]; 11603 u8 reserved_at_8[0x18]; 11604 11605 u8 syndrome[0x20]; 11606 11607 u8 memic_start_addr[0x40]; 11608 }; 11609 11610 struct mlx5_ifc_dealloc_memic_in_bits { 11611 u8 opcode[0x10]; 11612 u8 reserved_at_10[0x10]; 11613 11614 u8 reserved_at_20[0x10]; 11615 u8 op_mod[0x10]; 11616 11617 u8 reserved_at_40[0x40]; 11618 11619 u8 memic_start_addr[0x40]; 11620 11621 u8 memic_size[0x20]; 11622 11623 u8 reserved_at_e0[0x20]; 11624 }; 11625 11626 struct mlx5_ifc_dealloc_memic_out_bits { 11627 u8 status[0x8]; 11628 u8 reserved_at_8[0x18]; 11629 11630 u8 syndrome[0x20]; 11631 11632 u8 reserved_at_40[0x40]; 11633 }; 11634 11635 struct mlx5_ifc_umem_bits { 11636 u8 reserved_at_0[0x80]; 11637 11638 u8 ats[0x1]; 11639 u8 reserved_at_81[0x1a]; 11640 u8 log_page_size[0x5]; 11641 11642 u8 page_offset[0x20]; 11643 11644 u8 num_of_mtt[0x40]; 11645 11646 struct mlx5_ifc_mtt_bits mtt[]; 11647 }; 11648 11649 struct mlx5_ifc_uctx_bits { 11650 u8 cap[0x20]; 11651 11652 u8 reserved_at_20[0x160]; 11653 }; 11654 11655 struct mlx5_ifc_sw_icm_bits { 11656 u8 modify_field_select[0x40]; 11657 11658 u8 reserved_at_40[0x18]; 11659 u8 log_sw_icm_size[0x8]; 11660 11661 u8 reserved_at_60[0x20]; 11662 11663 u8 sw_icm_start_addr[0x40]; 11664 11665 u8 reserved_at_c0[0x140]; 11666 }; 11667 11668 struct mlx5_ifc_geneve_tlv_option_bits { 11669 u8 modify_field_select[0x40]; 11670 11671 u8 reserved_at_40[0x18]; 11672 u8 geneve_option_fte_index[0x8]; 11673 11674 u8 option_class[0x10]; 11675 u8 option_type[0x8]; 11676 u8 reserved_at_78[0x3]; 11677 u8 option_data_length[0x5]; 11678 11679 u8 reserved_at_80[0x180]; 11680 }; 11681 11682 struct mlx5_ifc_create_umem_in_bits { 11683 u8 opcode[0x10]; 11684 u8 uid[0x10]; 11685 11686 u8 reserved_at_20[0x10]; 11687 u8 op_mod[0x10]; 11688 11689 u8 reserved_at_40[0x40]; 11690 11691 struct mlx5_ifc_umem_bits umem; 11692 }; 11693 11694 struct mlx5_ifc_create_umem_out_bits { 11695 u8 status[0x8]; 11696 u8 reserved_at_8[0x18]; 11697 11698 u8 syndrome[0x20]; 11699 11700 u8 reserved_at_40[0x8]; 11701 u8 umem_id[0x18]; 11702 11703 u8 reserved_at_60[0x20]; 11704 }; 11705 11706 struct mlx5_ifc_destroy_umem_in_bits { 11707 u8 opcode[0x10]; 11708 u8 uid[0x10]; 11709 11710 u8 reserved_at_20[0x10]; 11711 u8 op_mod[0x10]; 11712 11713 u8 reserved_at_40[0x8]; 11714 u8 umem_id[0x18]; 11715 11716 u8 reserved_at_60[0x20]; 11717 }; 11718 11719 struct mlx5_ifc_destroy_umem_out_bits { 11720 u8 status[0x8]; 11721 u8 reserved_at_8[0x18]; 11722 11723 u8 syndrome[0x20]; 11724 11725 u8 reserved_at_40[0x40]; 11726 }; 11727 11728 struct mlx5_ifc_create_uctx_in_bits { 11729 u8 opcode[0x10]; 11730 u8 reserved_at_10[0x10]; 11731 11732 u8 reserved_at_20[0x10]; 11733 u8 op_mod[0x10]; 11734 11735 u8 reserved_at_40[0x40]; 11736 11737 struct mlx5_ifc_uctx_bits uctx; 11738 }; 11739 11740 struct mlx5_ifc_create_uctx_out_bits { 11741 u8 status[0x8]; 11742 u8 reserved_at_8[0x18]; 11743 11744 u8 syndrome[0x20]; 11745 11746 u8 reserved_at_40[0x10]; 11747 u8 uid[0x10]; 11748 11749 u8 reserved_at_60[0x20]; 11750 }; 11751 11752 struct mlx5_ifc_destroy_uctx_in_bits { 11753 u8 opcode[0x10]; 11754 u8 reserved_at_10[0x10]; 11755 11756 u8 reserved_at_20[0x10]; 11757 u8 op_mod[0x10]; 11758 11759 u8 reserved_at_40[0x10]; 11760 u8 uid[0x10]; 11761 11762 u8 reserved_at_60[0x20]; 11763 }; 11764 11765 struct mlx5_ifc_destroy_uctx_out_bits { 11766 u8 status[0x8]; 11767 u8 reserved_at_8[0x18]; 11768 11769 u8 syndrome[0x20]; 11770 11771 u8 reserved_at_40[0x40]; 11772 }; 11773 11774 struct mlx5_ifc_create_sw_icm_in_bits { 11775 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 11776 struct mlx5_ifc_sw_icm_bits sw_icm; 11777 }; 11778 11779 struct mlx5_ifc_create_geneve_tlv_option_in_bits { 11780 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 11781 struct mlx5_ifc_geneve_tlv_option_bits geneve_tlv_opt; 11782 }; 11783 11784 struct mlx5_ifc_mtrc_string_db_param_bits { 11785 u8 string_db_base_address[0x20]; 11786 11787 u8 reserved_at_20[0x8]; 11788 u8 string_db_size[0x18]; 11789 }; 11790 11791 struct mlx5_ifc_mtrc_cap_bits { 11792 u8 trace_owner[0x1]; 11793 u8 trace_to_memory[0x1]; 11794 u8 reserved_at_2[0x4]; 11795 u8 trc_ver[0x2]; 11796 u8 reserved_at_8[0x14]; 11797 u8 num_string_db[0x4]; 11798 11799 u8 first_string_trace[0x8]; 11800 u8 num_string_trace[0x8]; 11801 u8 reserved_at_30[0x28]; 11802 11803 u8 log_max_trace_buffer_size[0x8]; 11804 11805 u8 reserved_at_60[0x20]; 11806 11807 struct mlx5_ifc_mtrc_string_db_param_bits string_db_param[8]; 11808 11809 u8 reserved_at_280[0x180]; 11810 }; 11811 11812 struct mlx5_ifc_mtrc_conf_bits { 11813 u8 reserved_at_0[0x1c]; 11814 u8 trace_mode[0x4]; 11815 u8 reserved_at_20[0x18]; 11816 u8 log_trace_buffer_size[0x8]; 11817 u8 trace_mkey[0x20]; 11818 u8 reserved_at_60[0x3a0]; 11819 }; 11820 11821 struct mlx5_ifc_mtrc_stdb_bits { 11822 u8 string_db_index[0x4]; 11823 u8 reserved_at_4[0x4]; 11824 u8 read_size[0x18]; 11825 u8 start_offset[0x20]; 11826 u8 string_db_data[]; 11827 }; 11828 11829 struct mlx5_ifc_mtrc_ctrl_bits { 11830 u8 trace_status[0x2]; 11831 u8 reserved_at_2[0x2]; 11832 u8 arm_event[0x1]; 11833 u8 reserved_at_5[0xb]; 11834 u8 modify_field_select[0x10]; 11835 u8 reserved_at_20[0x2b]; 11836 u8 current_timestamp52_32[0x15]; 11837 u8 current_timestamp31_0[0x20]; 11838 u8 reserved_at_80[0x180]; 11839 }; 11840 11841 struct mlx5_ifc_host_params_context_bits { 11842 u8 host_number[0x8]; 11843 u8 reserved_at_8[0x7]; 11844 u8 host_pf_disabled[0x1]; 11845 u8 host_num_of_vfs[0x10]; 11846 11847 u8 host_total_vfs[0x10]; 11848 u8 host_pci_bus[0x10]; 11849 11850 u8 reserved_at_40[0x10]; 11851 u8 host_pci_device[0x10]; 11852 11853 u8 reserved_at_60[0x10]; 11854 u8 host_pci_function[0x10]; 11855 11856 u8 reserved_at_80[0x180]; 11857 }; 11858 11859 struct mlx5_ifc_query_esw_functions_in_bits { 11860 u8 opcode[0x10]; 11861 u8 reserved_at_10[0x10]; 11862 11863 u8 reserved_at_20[0x10]; 11864 u8 op_mod[0x10]; 11865 11866 u8 reserved_at_40[0x40]; 11867 }; 11868 11869 struct mlx5_ifc_query_esw_functions_out_bits { 11870 u8 status[0x8]; 11871 u8 reserved_at_8[0x18]; 11872 11873 u8 syndrome[0x20]; 11874 11875 u8 reserved_at_40[0x40]; 11876 11877 struct mlx5_ifc_host_params_context_bits host_params_context; 11878 11879 u8 reserved_at_280[0x180]; 11880 u8 host_sf_enable[][0x40]; 11881 }; 11882 11883 struct mlx5_ifc_sf_partition_bits { 11884 u8 reserved_at_0[0x10]; 11885 u8 log_num_sf[0x8]; 11886 u8 log_sf_bar_size[0x8]; 11887 }; 11888 11889 struct mlx5_ifc_query_sf_partitions_out_bits { 11890 u8 status[0x8]; 11891 u8 reserved_at_8[0x18]; 11892 11893 u8 syndrome[0x20]; 11894 11895 u8 reserved_at_40[0x18]; 11896 u8 num_sf_partitions[0x8]; 11897 11898 u8 reserved_at_60[0x20]; 11899 11900 struct mlx5_ifc_sf_partition_bits sf_partition[]; 11901 }; 11902 11903 struct mlx5_ifc_query_sf_partitions_in_bits { 11904 u8 opcode[0x10]; 11905 u8 reserved_at_10[0x10]; 11906 11907 u8 reserved_at_20[0x10]; 11908 u8 op_mod[0x10]; 11909 11910 u8 reserved_at_40[0x40]; 11911 }; 11912 11913 struct mlx5_ifc_dealloc_sf_out_bits { 11914 u8 status[0x8]; 11915 u8 reserved_at_8[0x18]; 11916 11917 u8 syndrome[0x20]; 11918 11919 u8 reserved_at_40[0x40]; 11920 }; 11921 11922 struct mlx5_ifc_dealloc_sf_in_bits { 11923 u8 opcode[0x10]; 11924 u8 reserved_at_10[0x10]; 11925 11926 u8 reserved_at_20[0x10]; 11927 u8 op_mod[0x10]; 11928 11929 u8 reserved_at_40[0x10]; 11930 u8 function_id[0x10]; 11931 11932 u8 reserved_at_60[0x20]; 11933 }; 11934 11935 struct mlx5_ifc_alloc_sf_out_bits { 11936 u8 status[0x8]; 11937 u8 reserved_at_8[0x18]; 11938 11939 u8 syndrome[0x20]; 11940 11941 u8 reserved_at_40[0x40]; 11942 }; 11943 11944 struct mlx5_ifc_alloc_sf_in_bits { 11945 u8 opcode[0x10]; 11946 u8 reserved_at_10[0x10]; 11947 11948 u8 reserved_at_20[0x10]; 11949 u8 op_mod[0x10]; 11950 11951 u8 reserved_at_40[0x10]; 11952 u8 function_id[0x10]; 11953 11954 u8 reserved_at_60[0x20]; 11955 }; 11956 11957 struct mlx5_ifc_affiliated_event_header_bits { 11958 u8 reserved_at_0[0x10]; 11959 u8 obj_type[0x10]; 11960 11961 u8 obj_id[0x20]; 11962 }; 11963 11964 enum { 11965 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = BIT_ULL(0xc), 11966 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_IPSEC = BIT_ULL(0x13), 11967 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_SAMPLER = BIT_ULL(0x20), 11968 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_FLOW_METER_ASO = BIT_ULL(0x24), 11969 }; 11970 11971 enum { 11972 MLX5_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = 0xc, 11973 MLX5_GENERAL_OBJECT_TYPES_IPSEC = 0x13, 11974 MLX5_GENERAL_OBJECT_TYPES_SAMPLER = 0x20, 11975 MLX5_GENERAL_OBJECT_TYPES_FLOW_METER_ASO = 0x24, 11976 MLX5_GENERAL_OBJECT_TYPES_MACSEC = 0x27, 11977 MLX5_GENERAL_OBJECT_TYPES_INT_KEK = 0x47, 11978 MLX5_GENERAL_OBJECT_TYPES_FLOW_TABLE_ALIAS = 0xff15, 11979 }; 11980 11981 enum { 11982 MLX5_IPSEC_OBJECT_ICV_LEN_16B, 11983 }; 11984 11985 enum { 11986 MLX5_IPSEC_ASO_REG_C_0_1 = 0x0, 11987 MLX5_IPSEC_ASO_REG_C_2_3 = 0x1, 11988 MLX5_IPSEC_ASO_REG_C_4_5 = 0x2, 11989 MLX5_IPSEC_ASO_REG_C_6_7 = 0x3, 11990 }; 11991 11992 enum { 11993 MLX5_IPSEC_ASO_MODE = 0x0, 11994 MLX5_IPSEC_ASO_REPLAY_PROTECTION = 0x1, 11995 MLX5_IPSEC_ASO_INC_SN = 0x2, 11996 }; 11997 11998 struct mlx5_ifc_ipsec_aso_bits { 11999 u8 valid[0x1]; 12000 u8 reserved_at_201[0x1]; 12001 u8 mode[0x2]; 12002 u8 window_sz[0x2]; 12003 u8 soft_lft_arm[0x1]; 12004 u8 hard_lft_arm[0x1]; 12005 u8 remove_flow_enable[0x1]; 12006 u8 esn_event_arm[0x1]; 12007 u8 reserved_at_20a[0x16]; 12008 12009 u8 remove_flow_pkt_cnt[0x20]; 12010 12011 u8 remove_flow_soft_lft[0x20]; 12012 12013 u8 reserved_at_260[0x80]; 12014 12015 u8 mode_parameter[0x20]; 12016 12017 u8 replay_protection_window[0x100]; 12018 }; 12019 12020 struct mlx5_ifc_ipsec_obj_bits { 12021 u8 modify_field_select[0x40]; 12022 u8 full_offload[0x1]; 12023 u8 reserved_at_41[0x1]; 12024 u8 esn_en[0x1]; 12025 u8 esn_overlap[0x1]; 12026 u8 reserved_at_44[0x2]; 12027 u8 icv_length[0x2]; 12028 u8 reserved_at_48[0x4]; 12029 u8 aso_return_reg[0x4]; 12030 u8 reserved_at_50[0x10]; 12031 12032 u8 esn_msb[0x20]; 12033 12034 u8 reserved_at_80[0x8]; 12035 u8 dekn[0x18]; 12036 12037 u8 salt[0x20]; 12038 12039 u8 implicit_iv[0x40]; 12040 12041 u8 reserved_at_100[0x8]; 12042 u8 ipsec_aso_access_pd[0x18]; 12043 u8 reserved_at_120[0xe0]; 12044 12045 struct mlx5_ifc_ipsec_aso_bits ipsec_aso; 12046 }; 12047 12048 struct mlx5_ifc_create_ipsec_obj_in_bits { 12049 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12050 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 12051 }; 12052 12053 enum { 12054 MLX5_MODIFY_IPSEC_BITMASK_ESN_OVERLAP = BIT(0), 12055 MLX5_MODIFY_IPSEC_BITMASK_ESN_MSB = BIT(1), 12056 }; 12057 12058 struct mlx5_ifc_query_ipsec_obj_out_bits { 12059 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 12060 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 12061 }; 12062 12063 struct mlx5_ifc_modify_ipsec_obj_in_bits { 12064 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12065 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 12066 }; 12067 12068 enum { 12069 MLX5_MACSEC_ASO_REPLAY_PROTECTION = 0x1, 12070 }; 12071 12072 enum { 12073 MLX5_MACSEC_ASO_REPLAY_WIN_32BIT = 0x0, 12074 MLX5_MACSEC_ASO_REPLAY_WIN_64BIT = 0x1, 12075 MLX5_MACSEC_ASO_REPLAY_WIN_128BIT = 0x2, 12076 MLX5_MACSEC_ASO_REPLAY_WIN_256BIT = 0x3, 12077 }; 12078 12079 #define MLX5_MACSEC_ASO_INC_SN 0x2 12080 #define MLX5_MACSEC_ASO_REG_C_4_5 0x2 12081 12082 struct mlx5_ifc_macsec_aso_bits { 12083 u8 valid[0x1]; 12084 u8 reserved_at_1[0x1]; 12085 u8 mode[0x2]; 12086 u8 window_size[0x2]; 12087 u8 soft_lifetime_arm[0x1]; 12088 u8 hard_lifetime_arm[0x1]; 12089 u8 remove_flow_enable[0x1]; 12090 u8 epn_event_arm[0x1]; 12091 u8 reserved_at_a[0x16]; 12092 12093 u8 remove_flow_packet_count[0x20]; 12094 12095 u8 remove_flow_soft_lifetime[0x20]; 12096 12097 u8 reserved_at_60[0x80]; 12098 12099 u8 mode_parameter[0x20]; 12100 12101 u8 replay_protection_window[8][0x20]; 12102 }; 12103 12104 struct mlx5_ifc_macsec_offload_obj_bits { 12105 u8 modify_field_select[0x40]; 12106 12107 u8 confidentiality_en[0x1]; 12108 u8 reserved_at_41[0x1]; 12109 u8 epn_en[0x1]; 12110 u8 epn_overlap[0x1]; 12111 u8 reserved_at_44[0x2]; 12112 u8 confidentiality_offset[0x2]; 12113 u8 reserved_at_48[0x4]; 12114 u8 aso_return_reg[0x4]; 12115 u8 reserved_at_50[0x10]; 12116 12117 u8 epn_msb[0x20]; 12118 12119 u8 reserved_at_80[0x8]; 12120 u8 dekn[0x18]; 12121 12122 u8 reserved_at_a0[0x20]; 12123 12124 u8 sci[0x40]; 12125 12126 u8 reserved_at_100[0x8]; 12127 u8 macsec_aso_access_pd[0x18]; 12128 12129 u8 reserved_at_120[0x60]; 12130 12131 u8 salt[3][0x20]; 12132 12133 u8 reserved_at_1e0[0x20]; 12134 12135 struct mlx5_ifc_macsec_aso_bits macsec_aso; 12136 }; 12137 12138 struct mlx5_ifc_create_macsec_obj_in_bits { 12139 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12140 struct mlx5_ifc_macsec_offload_obj_bits macsec_object; 12141 }; 12142 12143 struct mlx5_ifc_modify_macsec_obj_in_bits { 12144 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12145 struct mlx5_ifc_macsec_offload_obj_bits macsec_object; 12146 }; 12147 12148 enum { 12149 MLX5_MODIFY_MACSEC_BITMASK_EPN_OVERLAP = BIT(0), 12150 MLX5_MODIFY_MACSEC_BITMASK_EPN_MSB = BIT(1), 12151 }; 12152 12153 struct mlx5_ifc_query_macsec_obj_out_bits { 12154 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 12155 struct mlx5_ifc_macsec_offload_obj_bits macsec_object; 12156 }; 12157 12158 struct mlx5_ifc_wrapped_dek_bits { 12159 u8 gcm_iv[0x60]; 12160 12161 u8 reserved_at_60[0x20]; 12162 12163 u8 const0[0x1]; 12164 u8 key_size[0x1]; 12165 u8 reserved_at_82[0x2]; 12166 u8 key2_invalid[0x1]; 12167 u8 reserved_at_85[0x3]; 12168 u8 pd[0x18]; 12169 12170 u8 key_purpose[0x5]; 12171 u8 reserved_at_a5[0x13]; 12172 u8 kek_id[0x8]; 12173 12174 u8 reserved_at_c0[0x40]; 12175 12176 u8 key1[0x8][0x20]; 12177 12178 u8 key2[0x8][0x20]; 12179 12180 u8 reserved_at_300[0x40]; 12181 12182 u8 const1[0x1]; 12183 u8 reserved_at_341[0x1f]; 12184 12185 u8 reserved_at_360[0x20]; 12186 12187 u8 auth_tag[0x80]; 12188 }; 12189 12190 struct mlx5_ifc_encryption_key_obj_bits { 12191 u8 modify_field_select[0x40]; 12192 12193 u8 state[0x8]; 12194 u8 sw_wrapped[0x1]; 12195 u8 reserved_at_49[0xb]; 12196 u8 key_size[0x4]; 12197 u8 reserved_at_58[0x4]; 12198 u8 key_purpose[0x4]; 12199 12200 u8 reserved_at_60[0x8]; 12201 u8 pd[0x18]; 12202 12203 u8 reserved_at_80[0x100]; 12204 12205 u8 opaque[0x40]; 12206 12207 u8 reserved_at_1c0[0x40]; 12208 12209 u8 key[8][0x80]; 12210 12211 u8 sw_wrapped_dek[8][0x80]; 12212 12213 u8 reserved_at_a00[0x600]; 12214 }; 12215 12216 struct mlx5_ifc_create_encryption_key_in_bits { 12217 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12218 struct mlx5_ifc_encryption_key_obj_bits encryption_key_object; 12219 }; 12220 12221 struct mlx5_ifc_modify_encryption_key_in_bits { 12222 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12223 struct mlx5_ifc_encryption_key_obj_bits encryption_key_object; 12224 }; 12225 12226 enum { 12227 MLX5_FLOW_METER_MODE_BYTES_IP_LENGTH = 0x0, 12228 MLX5_FLOW_METER_MODE_BYTES_CALC_WITH_L2 = 0x1, 12229 MLX5_FLOW_METER_MODE_BYTES_CALC_WITH_L2_IPG = 0x2, 12230 MLX5_FLOW_METER_MODE_NUM_PACKETS = 0x3, 12231 }; 12232 12233 struct mlx5_ifc_flow_meter_parameters_bits { 12234 u8 valid[0x1]; 12235 u8 bucket_overflow[0x1]; 12236 u8 start_color[0x2]; 12237 u8 both_buckets_on_green[0x1]; 12238 u8 reserved_at_5[0x1]; 12239 u8 meter_mode[0x2]; 12240 u8 reserved_at_8[0x18]; 12241 12242 u8 reserved_at_20[0x20]; 12243 12244 u8 reserved_at_40[0x3]; 12245 u8 cbs_exponent[0x5]; 12246 u8 cbs_mantissa[0x8]; 12247 u8 reserved_at_50[0x3]; 12248 u8 cir_exponent[0x5]; 12249 u8 cir_mantissa[0x8]; 12250 12251 u8 reserved_at_60[0x20]; 12252 12253 u8 reserved_at_80[0x3]; 12254 u8 ebs_exponent[0x5]; 12255 u8 ebs_mantissa[0x8]; 12256 u8 reserved_at_90[0x3]; 12257 u8 eir_exponent[0x5]; 12258 u8 eir_mantissa[0x8]; 12259 12260 u8 reserved_at_a0[0x60]; 12261 }; 12262 12263 struct mlx5_ifc_flow_meter_aso_obj_bits { 12264 u8 modify_field_select[0x40]; 12265 12266 u8 reserved_at_40[0x40]; 12267 12268 u8 reserved_at_80[0x8]; 12269 u8 meter_aso_access_pd[0x18]; 12270 12271 u8 reserved_at_a0[0x160]; 12272 12273 struct mlx5_ifc_flow_meter_parameters_bits flow_meter_parameters[2]; 12274 }; 12275 12276 struct mlx5_ifc_create_flow_meter_aso_obj_in_bits { 12277 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 12278 struct mlx5_ifc_flow_meter_aso_obj_bits flow_meter_aso_obj; 12279 }; 12280 12281 struct mlx5_ifc_int_kek_obj_bits { 12282 u8 modify_field_select[0x40]; 12283 12284 u8 state[0x8]; 12285 u8 auto_gen[0x1]; 12286 u8 reserved_at_49[0xb]; 12287 u8 key_size[0x4]; 12288 u8 reserved_at_58[0x8]; 12289 12290 u8 reserved_at_60[0x8]; 12291 u8 pd[0x18]; 12292 12293 u8 reserved_at_80[0x180]; 12294 u8 key[8][0x80]; 12295 12296 u8 reserved_at_600[0x200]; 12297 }; 12298 12299 struct mlx5_ifc_create_int_kek_obj_in_bits { 12300 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12301 struct mlx5_ifc_int_kek_obj_bits int_kek_object; 12302 }; 12303 12304 struct mlx5_ifc_create_int_kek_obj_out_bits { 12305 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 12306 struct mlx5_ifc_int_kek_obj_bits int_kek_object; 12307 }; 12308 12309 struct mlx5_ifc_sampler_obj_bits { 12310 u8 modify_field_select[0x40]; 12311 12312 u8 table_type[0x8]; 12313 u8 level[0x8]; 12314 u8 reserved_at_50[0xf]; 12315 u8 ignore_flow_level[0x1]; 12316 12317 u8 sample_ratio[0x20]; 12318 12319 u8 reserved_at_80[0x8]; 12320 u8 sample_table_id[0x18]; 12321 12322 u8 reserved_at_a0[0x8]; 12323 u8 default_table_id[0x18]; 12324 12325 u8 sw_steering_icm_address_rx[0x40]; 12326 u8 sw_steering_icm_address_tx[0x40]; 12327 12328 u8 reserved_at_140[0xa0]; 12329 }; 12330 12331 struct mlx5_ifc_create_sampler_obj_in_bits { 12332 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12333 struct mlx5_ifc_sampler_obj_bits sampler_object; 12334 }; 12335 12336 struct mlx5_ifc_query_sampler_obj_out_bits { 12337 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 12338 struct mlx5_ifc_sampler_obj_bits sampler_object; 12339 }; 12340 12341 enum { 12342 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_128 = 0x0, 12343 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_256 = 0x1, 12344 }; 12345 12346 enum { 12347 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_PURPOSE_TLS = 0x1, 12348 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_PURPOSE_IPSEC = 0x2, 12349 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_PURPOSE_MACSEC = 0x4, 12350 }; 12351 12352 struct mlx5_ifc_tls_static_params_bits { 12353 u8 const_2[0x2]; 12354 u8 tls_version[0x4]; 12355 u8 const_1[0x2]; 12356 u8 reserved_at_8[0x14]; 12357 u8 encryption_standard[0x4]; 12358 12359 u8 reserved_at_20[0x20]; 12360 12361 u8 initial_record_number[0x40]; 12362 12363 u8 resync_tcp_sn[0x20]; 12364 12365 u8 gcm_iv[0x20]; 12366 12367 u8 implicit_iv[0x40]; 12368 12369 u8 reserved_at_100[0x8]; 12370 u8 dek_index[0x18]; 12371 12372 u8 reserved_at_120[0xe0]; 12373 }; 12374 12375 struct mlx5_ifc_tls_progress_params_bits { 12376 u8 next_record_tcp_sn[0x20]; 12377 12378 u8 hw_resync_tcp_sn[0x20]; 12379 12380 u8 record_tracker_state[0x2]; 12381 u8 auth_state[0x2]; 12382 u8 reserved_at_44[0x4]; 12383 u8 hw_offset_record_number[0x18]; 12384 }; 12385 12386 enum { 12387 MLX5_MTT_PERM_READ = 1 << 0, 12388 MLX5_MTT_PERM_WRITE = 1 << 1, 12389 MLX5_MTT_PERM_RW = MLX5_MTT_PERM_READ | MLX5_MTT_PERM_WRITE, 12390 }; 12391 12392 enum { 12393 MLX5_SUSPEND_VHCA_IN_OP_MOD_SUSPEND_INITIATOR = 0x0, 12394 MLX5_SUSPEND_VHCA_IN_OP_MOD_SUSPEND_RESPONDER = 0x1, 12395 }; 12396 12397 struct mlx5_ifc_suspend_vhca_in_bits { 12398 u8 opcode[0x10]; 12399 u8 uid[0x10]; 12400 12401 u8 reserved_at_20[0x10]; 12402 u8 op_mod[0x10]; 12403 12404 u8 reserved_at_40[0x10]; 12405 u8 vhca_id[0x10]; 12406 12407 u8 reserved_at_60[0x20]; 12408 }; 12409 12410 struct mlx5_ifc_suspend_vhca_out_bits { 12411 u8 status[0x8]; 12412 u8 reserved_at_8[0x18]; 12413 12414 u8 syndrome[0x20]; 12415 12416 u8 reserved_at_40[0x40]; 12417 }; 12418 12419 enum { 12420 MLX5_RESUME_VHCA_IN_OP_MOD_RESUME_RESPONDER = 0x0, 12421 MLX5_RESUME_VHCA_IN_OP_MOD_RESUME_INITIATOR = 0x1, 12422 }; 12423 12424 struct mlx5_ifc_resume_vhca_in_bits { 12425 u8 opcode[0x10]; 12426 u8 uid[0x10]; 12427 12428 u8 reserved_at_20[0x10]; 12429 u8 op_mod[0x10]; 12430 12431 u8 reserved_at_40[0x10]; 12432 u8 vhca_id[0x10]; 12433 12434 u8 reserved_at_60[0x20]; 12435 }; 12436 12437 struct mlx5_ifc_resume_vhca_out_bits { 12438 u8 status[0x8]; 12439 u8 reserved_at_8[0x18]; 12440 12441 u8 syndrome[0x20]; 12442 12443 u8 reserved_at_40[0x40]; 12444 }; 12445 12446 struct mlx5_ifc_query_vhca_migration_state_in_bits { 12447 u8 opcode[0x10]; 12448 u8 uid[0x10]; 12449 12450 u8 reserved_at_20[0x10]; 12451 u8 op_mod[0x10]; 12452 12453 u8 incremental[0x1]; 12454 u8 chunk[0x1]; 12455 u8 reserved_at_42[0xe]; 12456 u8 vhca_id[0x10]; 12457 12458 u8 reserved_at_60[0x20]; 12459 }; 12460 12461 struct mlx5_ifc_query_vhca_migration_state_out_bits { 12462 u8 status[0x8]; 12463 u8 reserved_at_8[0x18]; 12464 12465 u8 syndrome[0x20]; 12466 12467 u8 reserved_at_40[0x40]; 12468 12469 u8 required_umem_size[0x20]; 12470 12471 u8 reserved_at_a0[0x20]; 12472 12473 u8 remaining_total_size[0x40]; 12474 12475 u8 reserved_at_100[0x100]; 12476 }; 12477 12478 struct mlx5_ifc_save_vhca_state_in_bits { 12479 u8 opcode[0x10]; 12480 u8 uid[0x10]; 12481 12482 u8 reserved_at_20[0x10]; 12483 u8 op_mod[0x10]; 12484 12485 u8 incremental[0x1]; 12486 u8 set_track[0x1]; 12487 u8 reserved_at_42[0xe]; 12488 u8 vhca_id[0x10]; 12489 12490 u8 reserved_at_60[0x20]; 12491 12492 u8 va[0x40]; 12493 12494 u8 mkey[0x20]; 12495 12496 u8 size[0x20]; 12497 }; 12498 12499 struct mlx5_ifc_save_vhca_state_out_bits { 12500 u8 status[0x8]; 12501 u8 reserved_at_8[0x18]; 12502 12503 u8 syndrome[0x20]; 12504 12505 u8 actual_image_size[0x20]; 12506 12507 u8 next_required_umem_size[0x20]; 12508 }; 12509 12510 struct mlx5_ifc_load_vhca_state_in_bits { 12511 u8 opcode[0x10]; 12512 u8 uid[0x10]; 12513 12514 u8 reserved_at_20[0x10]; 12515 u8 op_mod[0x10]; 12516 12517 u8 reserved_at_40[0x10]; 12518 u8 vhca_id[0x10]; 12519 12520 u8 reserved_at_60[0x20]; 12521 12522 u8 va[0x40]; 12523 12524 u8 mkey[0x20]; 12525 12526 u8 size[0x20]; 12527 }; 12528 12529 struct mlx5_ifc_load_vhca_state_out_bits { 12530 u8 status[0x8]; 12531 u8 reserved_at_8[0x18]; 12532 12533 u8 syndrome[0x20]; 12534 12535 u8 reserved_at_40[0x40]; 12536 }; 12537 12538 struct mlx5_ifc_adv_virtualization_cap_bits { 12539 u8 reserved_at_0[0x3]; 12540 u8 pg_track_log_max_num[0x5]; 12541 u8 pg_track_max_num_range[0x8]; 12542 u8 pg_track_log_min_addr_space[0x8]; 12543 u8 pg_track_log_max_addr_space[0x8]; 12544 12545 u8 reserved_at_20[0x3]; 12546 u8 pg_track_log_min_msg_size[0x5]; 12547 u8 reserved_at_28[0x3]; 12548 u8 pg_track_log_max_msg_size[0x5]; 12549 u8 reserved_at_30[0x3]; 12550 u8 pg_track_log_min_page_size[0x5]; 12551 u8 reserved_at_38[0x3]; 12552 u8 pg_track_log_max_page_size[0x5]; 12553 12554 u8 reserved_at_40[0x7c0]; 12555 }; 12556 12557 struct mlx5_ifc_page_track_report_entry_bits { 12558 u8 dirty_address_high[0x20]; 12559 12560 u8 dirty_address_low[0x20]; 12561 }; 12562 12563 enum { 12564 MLX5_PAGE_TRACK_STATE_TRACKING, 12565 MLX5_PAGE_TRACK_STATE_REPORTING, 12566 MLX5_PAGE_TRACK_STATE_ERROR, 12567 }; 12568 12569 struct mlx5_ifc_page_track_range_bits { 12570 u8 start_address[0x40]; 12571 12572 u8 length[0x40]; 12573 }; 12574 12575 struct mlx5_ifc_page_track_bits { 12576 u8 modify_field_select[0x40]; 12577 12578 u8 reserved_at_40[0x10]; 12579 u8 vhca_id[0x10]; 12580 12581 u8 reserved_at_60[0x20]; 12582 12583 u8 state[0x4]; 12584 u8 track_type[0x4]; 12585 u8 log_addr_space_size[0x8]; 12586 u8 reserved_at_90[0x3]; 12587 u8 log_page_size[0x5]; 12588 u8 reserved_at_98[0x3]; 12589 u8 log_msg_size[0x5]; 12590 12591 u8 reserved_at_a0[0x8]; 12592 u8 reporting_qpn[0x18]; 12593 12594 u8 reserved_at_c0[0x18]; 12595 u8 num_ranges[0x8]; 12596 12597 u8 reserved_at_e0[0x20]; 12598 12599 u8 range_start_address[0x40]; 12600 12601 u8 length[0x40]; 12602 12603 struct mlx5_ifc_page_track_range_bits track_range[0]; 12604 }; 12605 12606 struct mlx5_ifc_create_page_track_obj_in_bits { 12607 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12608 struct mlx5_ifc_page_track_bits obj_context; 12609 }; 12610 12611 struct mlx5_ifc_modify_page_track_obj_in_bits { 12612 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12613 struct mlx5_ifc_page_track_bits obj_context; 12614 }; 12615 12616 struct mlx5_ifc_msecq_reg_bits { 12617 u8 reserved_at_0[0x20]; 12618 12619 u8 reserved_at_20[0x12]; 12620 u8 network_option[0x2]; 12621 u8 local_ssm_code[0x4]; 12622 u8 local_enhanced_ssm_code[0x8]; 12623 12624 u8 local_clock_identity[0x40]; 12625 12626 u8 reserved_at_80[0x180]; 12627 }; 12628 12629 enum { 12630 MLX5_MSEES_FIELD_SELECT_ENABLE = BIT(0), 12631 MLX5_MSEES_FIELD_SELECT_ADMIN_STATUS = BIT(1), 12632 MLX5_MSEES_FIELD_SELECT_ADMIN_FREQ_MEASURE = BIT(2), 12633 }; 12634 12635 enum mlx5_msees_admin_status { 12636 MLX5_MSEES_ADMIN_STATUS_FREE_RUNNING = 0x0, 12637 MLX5_MSEES_ADMIN_STATUS_TRACK = 0x1, 12638 }; 12639 12640 enum mlx5_msees_oper_status { 12641 MLX5_MSEES_OPER_STATUS_FREE_RUNNING = 0x0, 12642 MLX5_MSEES_OPER_STATUS_SELF_TRACK = 0x1, 12643 MLX5_MSEES_OPER_STATUS_OTHER_TRACK = 0x2, 12644 MLX5_MSEES_OPER_STATUS_HOLDOVER = 0x3, 12645 MLX5_MSEES_OPER_STATUS_FAIL_HOLDOVER = 0x4, 12646 MLX5_MSEES_OPER_STATUS_FAIL_FREE_RUNNING = 0x5, 12647 }; 12648 12649 struct mlx5_ifc_msees_reg_bits { 12650 u8 reserved_at_0[0x8]; 12651 u8 local_port[0x8]; 12652 u8 pnat[0x2]; 12653 u8 lp_msb[0x2]; 12654 u8 reserved_at_14[0xc]; 12655 12656 u8 field_select[0x20]; 12657 12658 u8 admin_status[0x4]; 12659 u8 oper_status[0x4]; 12660 u8 ho_acq[0x1]; 12661 u8 reserved_at_49[0xc]; 12662 u8 admin_freq_measure[0x1]; 12663 u8 oper_freq_measure[0x1]; 12664 u8 failure_reason[0x9]; 12665 12666 u8 frequency_diff[0x20]; 12667 12668 u8 reserved_at_80[0x180]; 12669 }; 12670 12671 #endif /* MLX5_IFC_H */ 12672