1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 #ifndef MLX5_IFC_H 33 #define MLX5_IFC_H 34 35 #include "mlx5_ifc_fpga.h" 36 37 enum { 38 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0, 39 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1, 40 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2, 41 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3, 42 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13, 43 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14, 44 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c, 45 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d, 46 MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4, 47 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5, 48 MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED = 0x7, 49 MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT = 0xc, 50 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10, 51 MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR = 0x11, 52 MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR = 0x12, 53 MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR = 0x8, 54 MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE = 0x9, 55 MLX5_EVENT_TYPE_CODING_GPIO_EVENT = 0x15, 56 MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19, 57 MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a, 58 MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT = 0x1b, 59 MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT = 0x1f, 60 MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa, 61 MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb, 62 MLX5_EVENT_TYPE_CODING_FPGA_ERROR = 0x20, 63 MLX5_EVENT_TYPE_CODING_FPGA_QP_ERROR = 0x21 64 }; 65 66 enum { 67 MLX5_MODIFY_TIR_BITMASK_LRO = 0x0, 68 MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE = 0x1, 69 MLX5_MODIFY_TIR_BITMASK_HASH = 0x2, 70 MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN = 0x3 71 }; 72 73 enum { 74 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0, 75 MLX5_SET_HCA_CAP_OP_MOD_ODP = 0x2, 76 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3, 77 MLX5_SET_HCA_CAP_OP_MOD_ROCE = 0x4, 78 }; 79 80 enum { 81 MLX5_SHARED_RESOURCE_UID = 0xffff, 82 }; 83 84 enum { 85 MLX5_OBJ_TYPE_SW_ICM = 0x0008, 86 }; 87 88 enum { 89 MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM = (1ULL << MLX5_OBJ_TYPE_SW_ICM), 90 MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT = (1ULL << 11), 91 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q = (1ULL << 13), 92 }; 93 94 enum { 95 MLX5_OBJ_TYPE_GENEVE_TLV_OPT = 0x000b, 96 MLX5_OBJ_TYPE_VIRTIO_NET_Q = 0x000d, 97 MLX5_OBJ_TYPE_MKEY = 0xff01, 98 MLX5_OBJ_TYPE_QP = 0xff02, 99 MLX5_OBJ_TYPE_PSV = 0xff03, 100 MLX5_OBJ_TYPE_RMP = 0xff04, 101 MLX5_OBJ_TYPE_XRC_SRQ = 0xff05, 102 MLX5_OBJ_TYPE_RQ = 0xff06, 103 MLX5_OBJ_TYPE_SQ = 0xff07, 104 MLX5_OBJ_TYPE_TIR = 0xff08, 105 MLX5_OBJ_TYPE_TIS = 0xff09, 106 MLX5_OBJ_TYPE_DCT = 0xff0a, 107 MLX5_OBJ_TYPE_XRQ = 0xff0b, 108 MLX5_OBJ_TYPE_RQT = 0xff0e, 109 MLX5_OBJ_TYPE_FLOW_COUNTER = 0xff0f, 110 MLX5_OBJ_TYPE_CQ = 0xff10, 111 }; 112 113 enum { 114 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100, 115 MLX5_CMD_OP_QUERY_ADAPTER = 0x101, 116 MLX5_CMD_OP_INIT_HCA = 0x102, 117 MLX5_CMD_OP_TEARDOWN_HCA = 0x103, 118 MLX5_CMD_OP_ENABLE_HCA = 0x104, 119 MLX5_CMD_OP_DISABLE_HCA = 0x105, 120 MLX5_CMD_OP_QUERY_PAGES = 0x107, 121 MLX5_CMD_OP_MANAGE_PAGES = 0x108, 122 MLX5_CMD_OP_SET_HCA_CAP = 0x109, 123 MLX5_CMD_OP_QUERY_ISSI = 0x10a, 124 MLX5_CMD_OP_SET_ISSI = 0x10b, 125 MLX5_CMD_OP_SET_DRIVER_VERSION = 0x10d, 126 MLX5_CMD_OP_QUERY_SF_PARTITION = 0x111, 127 MLX5_CMD_OP_ALLOC_SF = 0x113, 128 MLX5_CMD_OP_DEALLOC_SF = 0x114, 129 MLX5_CMD_OP_CREATE_MKEY = 0x200, 130 MLX5_CMD_OP_QUERY_MKEY = 0x201, 131 MLX5_CMD_OP_DESTROY_MKEY = 0x202, 132 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203, 133 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204, 134 MLX5_CMD_OP_ALLOC_MEMIC = 0x205, 135 MLX5_CMD_OP_DEALLOC_MEMIC = 0x206, 136 MLX5_CMD_OP_CREATE_EQ = 0x301, 137 MLX5_CMD_OP_DESTROY_EQ = 0x302, 138 MLX5_CMD_OP_QUERY_EQ = 0x303, 139 MLX5_CMD_OP_GEN_EQE = 0x304, 140 MLX5_CMD_OP_CREATE_CQ = 0x400, 141 MLX5_CMD_OP_DESTROY_CQ = 0x401, 142 MLX5_CMD_OP_QUERY_CQ = 0x402, 143 MLX5_CMD_OP_MODIFY_CQ = 0x403, 144 MLX5_CMD_OP_CREATE_QP = 0x500, 145 MLX5_CMD_OP_DESTROY_QP = 0x501, 146 MLX5_CMD_OP_RST2INIT_QP = 0x502, 147 MLX5_CMD_OP_INIT2RTR_QP = 0x503, 148 MLX5_CMD_OP_RTR2RTS_QP = 0x504, 149 MLX5_CMD_OP_RTS2RTS_QP = 0x505, 150 MLX5_CMD_OP_SQERR2RTS_QP = 0x506, 151 MLX5_CMD_OP_2ERR_QP = 0x507, 152 MLX5_CMD_OP_2RST_QP = 0x50a, 153 MLX5_CMD_OP_QUERY_QP = 0x50b, 154 MLX5_CMD_OP_SQD_RTS_QP = 0x50c, 155 MLX5_CMD_OP_INIT2INIT_QP = 0x50e, 156 MLX5_CMD_OP_CREATE_PSV = 0x600, 157 MLX5_CMD_OP_DESTROY_PSV = 0x601, 158 MLX5_CMD_OP_CREATE_SRQ = 0x700, 159 MLX5_CMD_OP_DESTROY_SRQ = 0x701, 160 MLX5_CMD_OP_QUERY_SRQ = 0x702, 161 MLX5_CMD_OP_ARM_RQ = 0x703, 162 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705, 163 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706, 164 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707, 165 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708, 166 MLX5_CMD_OP_CREATE_DCT = 0x710, 167 MLX5_CMD_OP_DESTROY_DCT = 0x711, 168 MLX5_CMD_OP_DRAIN_DCT = 0x712, 169 MLX5_CMD_OP_QUERY_DCT = 0x713, 170 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714, 171 MLX5_CMD_OP_CREATE_XRQ = 0x717, 172 MLX5_CMD_OP_DESTROY_XRQ = 0x718, 173 MLX5_CMD_OP_QUERY_XRQ = 0x719, 174 MLX5_CMD_OP_ARM_XRQ = 0x71a, 175 MLX5_CMD_OP_QUERY_XRQ_DC_PARAMS_ENTRY = 0x725, 176 MLX5_CMD_OP_SET_XRQ_DC_PARAMS_ENTRY = 0x726, 177 MLX5_CMD_OP_QUERY_XRQ_ERROR_PARAMS = 0x727, 178 MLX5_CMD_OP_RELEASE_XRQ_ERROR = 0x729, 179 MLX5_CMD_OP_MODIFY_XRQ = 0x72a, 180 MLX5_CMD_OP_QUERY_ESW_FUNCTIONS = 0x740, 181 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750, 182 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751, 183 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752, 184 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753, 185 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754, 186 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755, 187 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760, 188 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761, 189 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762, 190 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763, 191 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764, 192 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765, 193 MLX5_CMD_OP_QUERY_VNIC_ENV = 0x76f, 194 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770, 195 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771, 196 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772, 197 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773, 198 MLX5_CMD_OP_SET_MONITOR_COUNTER = 0x774, 199 MLX5_CMD_OP_ARM_MONITOR_COUNTER = 0x775, 200 MLX5_CMD_OP_SET_PP_RATE_LIMIT = 0x780, 201 MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781, 202 MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT = 0x782, 203 MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT = 0x783, 204 MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT = 0x784, 205 MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT = 0x785, 206 MLX5_CMD_OP_CREATE_QOS_PARA_VPORT = 0x786, 207 MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT = 0x787, 208 MLX5_CMD_OP_ALLOC_PD = 0x800, 209 MLX5_CMD_OP_DEALLOC_PD = 0x801, 210 MLX5_CMD_OP_ALLOC_UAR = 0x802, 211 MLX5_CMD_OP_DEALLOC_UAR = 0x803, 212 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804, 213 MLX5_CMD_OP_ACCESS_REG = 0x805, 214 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806, 215 MLX5_CMD_OP_DETACH_FROM_MCG = 0x807, 216 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a, 217 MLX5_CMD_OP_MAD_IFC = 0x50d, 218 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b, 219 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c, 220 MLX5_CMD_OP_NOP = 0x80d, 221 MLX5_CMD_OP_ALLOC_XRCD = 0x80e, 222 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f, 223 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816, 224 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817, 225 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822, 226 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823, 227 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824, 228 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825, 229 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826, 230 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827, 231 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828, 232 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829, 233 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a, 234 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b, 235 MLX5_CMD_OP_SET_WOL_ROL = 0x830, 236 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831, 237 MLX5_CMD_OP_CREATE_LAG = 0x840, 238 MLX5_CMD_OP_MODIFY_LAG = 0x841, 239 MLX5_CMD_OP_QUERY_LAG = 0x842, 240 MLX5_CMD_OP_DESTROY_LAG = 0x843, 241 MLX5_CMD_OP_CREATE_VPORT_LAG = 0x844, 242 MLX5_CMD_OP_DESTROY_VPORT_LAG = 0x845, 243 MLX5_CMD_OP_CREATE_TIR = 0x900, 244 MLX5_CMD_OP_MODIFY_TIR = 0x901, 245 MLX5_CMD_OP_DESTROY_TIR = 0x902, 246 MLX5_CMD_OP_QUERY_TIR = 0x903, 247 MLX5_CMD_OP_CREATE_SQ = 0x904, 248 MLX5_CMD_OP_MODIFY_SQ = 0x905, 249 MLX5_CMD_OP_DESTROY_SQ = 0x906, 250 MLX5_CMD_OP_QUERY_SQ = 0x907, 251 MLX5_CMD_OP_CREATE_RQ = 0x908, 252 MLX5_CMD_OP_MODIFY_RQ = 0x909, 253 MLX5_CMD_OP_SET_DELAY_DROP_PARAMS = 0x910, 254 MLX5_CMD_OP_DESTROY_RQ = 0x90a, 255 MLX5_CMD_OP_QUERY_RQ = 0x90b, 256 MLX5_CMD_OP_CREATE_RMP = 0x90c, 257 MLX5_CMD_OP_MODIFY_RMP = 0x90d, 258 MLX5_CMD_OP_DESTROY_RMP = 0x90e, 259 MLX5_CMD_OP_QUERY_RMP = 0x90f, 260 MLX5_CMD_OP_CREATE_TIS = 0x912, 261 MLX5_CMD_OP_MODIFY_TIS = 0x913, 262 MLX5_CMD_OP_DESTROY_TIS = 0x914, 263 MLX5_CMD_OP_QUERY_TIS = 0x915, 264 MLX5_CMD_OP_CREATE_RQT = 0x916, 265 MLX5_CMD_OP_MODIFY_RQT = 0x917, 266 MLX5_CMD_OP_DESTROY_RQT = 0x918, 267 MLX5_CMD_OP_QUERY_RQT = 0x919, 268 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f, 269 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930, 270 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931, 271 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932, 272 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933, 273 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934, 274 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935, 275 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936, 276 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937, 277 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938, 278 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939, 279 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a, 280 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b, 281 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c, 282 MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT = 0x93d, 283 MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT = 0x93e, 284 MLX5_CMD_OP_QUERY_PACKET_REFORMAT_CONTEXT = 0x93f, 285 MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT = 0x940, 286 MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941, 287 MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT = 0x942, 288 MLX5_CMD_OP_FPGA_CREATE_QP = 0x960, 289 MLX5_CMD_OP_FPGA_MODIFY_QP = 0x961, 290 MLX5_CMD_OP_FPGA_QUERY_QP = 0x962, 291 MLX5_CMD_OP_FPGA_DESTROY_QP = 0x963, 292 MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS = 0x964, 293 MLX5_CMD_OP_CREATE_GENERAL_OBJECT = 0xa00, 294 MLX5_CMD_OP_MODIFY_GENERAL_OBJECT = 0xa01, 295 MLX5_CMD_OP_QUERY_GENERAL_OBJECT = 0xa02, 296 MLX5_CMD_OP_DESTROY_GENERAL_OBJECT = 0xa03, 297 MLX5_CMD_OP_CREATE_UCTX = 0xa04, 298 MLX5_CMD_OP_DESTROY_UCTX = 0xa06, 299 MLX5_CMD_OP_CREATE_UMEM = 0xa08, 300 MLX5_CMD_OP_DESTROY_UMEM = 0xa0a, 301 MLX5_CMD_OP_SYNC_STEERING = 0xb00, 302 MLX5_CMD_OP_QUERY_VHCA_STATE = 0xb0d, 303 MLX5_CMD_OP_MODIFY_VHCA_STATE = 0xb0e, 304 MLX5_CMD_OP_MAX 305 }; 306 307 /* Valid range for general commands that don't work over an object */ 308 enum { 309 MLX5_CMD_OP_GENERAL_START = 0xb00, 310 MLX5_CMD_OP_GENERAL_END = 0xd00, 311 }; 312 313 struct mlx5_ifc_flow_table_fields_supported_bits { 314 u8 outer_dmac[0x1]; 315 u8 outer_smac[0x1]; 316 u8 outer_ether_type[0x1]; 317 u8 outer_ip_version[0x1]; 318 u8 outer_first_prio[0x1]; 319 u8 outer_first_cfi[0x1]; 320 u8 outer_first_vid[0x1]; 321 u8 outer_ipv4_ttl[0x1]; 322 u8 outer_second_prio[0x1]; 323 u8 outer_second_cfi[0x1]; 324 u8 outer_second_vid[0x1]; 325 u8 reserved_at_b[0x1]; 326 u8 outer_sip[0x1]; 327 u8 outer_dip[0x1]; 328 u8 outer_frag[0x1]; 329 u8 outer_ip_protocol[0x1]; 330 u8 outer_ip_ecn[0x1]; 331 u8 outer_ip_dscp[0x1]; 332 u8 outer_udp_sport[0x1]; 333 u8 outer_udp_dport[0x1]; 334 u8 outer_tcp_sport[0x1]; 335 u8 outer_tcp_dport[0x1]; 336 u8 outer_tcp_flags[0x1]; 337 u8 outer_gre_protocol[0x1]; 338 u8 outer_gre_key[0x1]; 339 u8 outer_vxlan_vni[0x1]; 340 u8 outer_geneve_vni[0x1]; 341 u8 outer_geneve_oam[0x1]; 342 u8 outer_geneve_protocol_type[0x1]; 343 u8 outer_geneve_opt_len[0x1]; 344 u8 reserved_at_1e[0x1]; 345 u8 source_eswitch_port[0x1]; 346 347 u8 inner_dmac[0x1]; 348 u8 inner_smac[0x1]; 349 u8 inner_ether_type[0x1]; 350 u8 inner_ip_version[0x1]; 351 u8 inner_first_prio[0x1]; 352 u8 inner_first_cfi[0x1]; 353 u8 inner_first_vid[0x1]; 354 u8 reserved_at_27[0x1]; 355 u8 inner_second_prio[0x1]; 356 u8 inner_second_cfi[0x1]; 357 u8 inner_second_vid[0x1]; 358 u8 reserved_at_2b[0x1]; 359 u8 inner_sip[0x1]; 360 u8 inner_dip[0x1]; 361 u8 inner_frag[0x1]; 362 u8 inner_ip_protocol[0x1]; 363 u8 inner_ip_ecn[0x1]; 364 u8 inner_ip_dscp[0x1]; 365 u8 inner_udp_sport[0x1]; 366 u8 inner_udp_dport[0x1]; 367 u8 inner_tcp_sport[0x1]; 368 u8 inner_tcp_dport[0x1]; 369 u8 inner_tcp_flags[0x1]; 370 u8 reserved_at_37[0x9]; 371 372 u8 geneve_tlv_option_0_data[0x1]; 373 u8 reserved_at_41[0x4]; 374 u8 outer_first_mpls_over_udp[0x4]; 375 u8 outer_first_mpls_over_gre[0x4]; 376 u8 inner_first_mpls[0x4]; 377 u8 outer_first_mpls[0x4]; 378 u8 reserved_at_55[0x2]; 379 u8 outer_esp_spi[0x1]; 380 u8 reserved_at_58[0x2]; 381 u8 bth_dst_qp[0x1]; 382 u8 reserved_at_5b[0x5]; 383 384 u8 reserved_at_60[0x18]; 385 u8 metadata_reg_c_7[0x1]; 386 u8 metadata_reg_c_6[0x1]; 387 u8 metadata_reg_c_5[0x1]; 388 u8 metadata_reg_c_4[0x1]; 389 u8 metadata_reg_c_3[0x1]; 390 u8 metadata_reg_c_2[0x1]; 391 u8 metadata_reg_c_1[0x1]; 392 u8 metadata_reg_c_0[0x1]; 393 }; 394 395 struct mlx5_ifc_flow_table_prop_layout_bits { 396 u8 ft_support[0x1]; 397 u8 reserved_at_1[0x1]; 398 u8 flow_counter[0x1]; 399 u8 flow_modify_en[0x1]; 400 u8 modify_root[0x1]; 401 u8 identified_miss_table_mode[0x1]; 402 u8 flow_table_modify[0x1]; 403 u8 reformat[0x1]; 404 u8 decap[0x1]; 405 u8 reserved_at_9[0x1]; 406 u8 pop_vlan[0x1]; 407 u8 push_vlan[0x1]; 408 u8 reserved_at_c[0x1]; 409 u8 pop_vlan_2[0x1]; 410 u8 push_vlan_2[0x1]; 411 u8 reformat_and_vlan_action[0x1]; 412 u8 reserved_at_10[0x1]; 413 u8 sw_owner[0x1]; 414 u8 reformat_l3_tunnel_to_l2[0x1]; 415 u8 reformat_l2_to_l3_tunnel[0x1]; 416 u8 reformat_and_modify_action[0x1]; 417 u8 ignore_flow_level[0x1]; 418 u8 reserved_at_16[0x1]; 419 u8 table_miss_action_domain[0x1]; 420 u8 termination_table[0x1]; 421 u8 reformat_and_fwd_to_table[0x1]; 422 u8 reserved_at_1a[0x2]; 423 u8 ipsec_encrypt[0x1]; 424 u8 ipsec_decrypt[0x1]; 425 u8 sw_owner_v2[0x1]; 426 u8 reserved_at_1f[0x1]; 427 428 u8 termination_table_raw_traffic[0x1]; 429 u8 reserved_at_21[0x1]; 430 u8 log_max_ft_size[0x6]; 431 u8 log_max_modify_header_context[0x8]; 432 u8 max_modify_header_actions[0x8]; 433 u8 max_ft_level[0x8]; 434 435 u8 reserved_at_40[0x20]; 436 437 u8 reserved_at_60[0x18]; 438 u8 log_max_ft_num[0x8]; 439 440 u8 reserved_at_80[0x18]; 441 u8 log_max_destination[0x8]; 442 443 u8 log_max_flow_counter[0x8]; 444 u8 reserved_at_a8[0x10]; 445 u8 log_max_flow[0x8]; 446 447 u8 reserved_at_c0[0x40]; 448 449 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support; 450 451 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support; 452 }; 453 454 struct mlx5_ifc_odp_per_transport_service_cap_bits { 455 u8 send[0x1]; 456 u8 receive[0x1]; 457 u8 write[0x1]; 458 u8 read[0x1]; 459 u8 atomic[0x1]; 460 u8 srq_receive[0x1]; 461 u8 reserved_at_6[0x1a]; 462 }; 463 464 struct mlx5_ifc_fte_match_set_lyr_2_4_bits { 465 u8 smac_47_16[0x20]; 466 467 u8 smac_15_0[0x10]; 468 u8 ethertype[0x10]; 469 470 u8 dmac_47_16[0x20]; 471 472 u8 dmac_15_0[0x10]; 473 u8 first_prio[0x3]; 474 u8 first_cfi[0x1]; 475 u8 first_vid[0xc]; 476 477 u8 ip_protocol[0x8]; 478 u8 ip_dscp[0x6]; 479 u8 ip_ecn[0x2]; 480 u8 cvlan_tag[0x1]; 481 u8 svlan_tag[0x1]; 482 u8 frag[0x1]; 483 u8 ip_version[0x4]; 484 u8 tcp_flags[0x9]; 485 486 u8 tcp_sport[0x10]; 487 u8 tcp_dport[0x10]; 488 489 u8 reserved_at_c0[0x18]; 490 u8 ttl_hoplimit[0x8]; 491 492 u8 udp_sport[0x10]; 493 u8 udp_dport[0x10]; 494 495 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6; 496 497 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6; 498 }; 499 500 struct mlx5_ifc_nvgre_key_bits { 501 u8 hi[0x18]; 502 u8 lo[0x8]; 503 }; 504 505 union mlx5_ifc_gre_key_bits { 506 struct mlx5_ifc_nvgre_key_bits nvgre; 507 u8 key[0x20]; 508 }; 509 510 struct mlx5_ifc_fte_match_set_misc_bits { 511 u8 gre_c_present[0x1]; 512 u8 reserved_at_1[0x1]; 513 u8 gre_k_present[0x1]; 514 u8 gre_s_present[0x1]; 515 u8 source_vhca_port[0x4]; 516 u8 source_sqn[0x18]; 517 518 u8 source_eswitch_owner_vhca_id[0x10]; 519 u8 source_port[0x10]; 520 521 u8 outer_second_prio[0x3]; 522 u8 outer_second_cfi[0x1]; 523 u8 outer_second_vid[0xc]; 524 u8 inner_second_prio[0x3]; 525 u8 inner_second_cfi[0x1]; 526 u8 inner_second_vid[0xc]; 527 528 u8 outer_second_cvlan_tag[0x1]; 529 u8 inner_second_cvlan_tag[0x1]; 530 u8 outer_second_svlan_tag[0x1]; 531 u8 inner_second_svlan_tag[0x1]; 532 u8 reserved_at_64[0xc]; 533 u8 gre_protocol[0x10]; 534 535 union mlx5_ifc_gre_key_bits gre_key; 536 537 u8 vxlan_vni[0x18]; 538 u8 reserved_at_b8[0x8]; 539 540 u8 geneve_vni[0x18]; 541 u8 reserved_at_d8[0x7]; 542 u8 geneve_oam[0x1]; 543 544 u8 reserved_at_e0[0xc]; 545 u8 outer_ipv6_flow_label[0x14]; 546 547 u8 reserved_at_100[0xc]; 548 u8 inner_ipv6_flow_label[0x14]; 549 550 u8 reserved_at_120[0xa]; 551 u8 geneve_opt_len[0x6]; 552 u8 geneve_protocol_type[0x10]; 553 554 u8 reserved_at_140[0x8]; 555 u8 bth_dst_qp[0x18]; 556 u8 reserved_at_160[0x20]; 557 u8 outer_esp_spi[0x20]; 558 u8 reserved_at_1a0[0x60]; 559 }; 560 561 struct mlx5_ifc_fte_match_mpls_bits { 562 u8 mpls_label[0x14]; 563 u8 mpls_exp[0x3]; 564 u8 mpls_s_bos[0x1]; 565 u8 mpls_ttl[0x8]; 566 }; 567 568 struct mlx5_ifc_fte_match_set_misc2_bits { 569 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls; 570 571 struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls; 572 573 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre; 574 575 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp; 576 577 u8 metadata_reg_c_7[0x20]; 578 579 u8 metadata_reg_c_6[0x20]; 580 581 u8 metadata_reg_c_5[0x20]; 582 583 u8 metadata_reg_c_4[0x20]; 584 585 u8 metadata_reg_c_3[0x20]; 586 587 u8 metadata_reg_c_2[0x20]; 588 589 u8 metadata_reg_c_1[0x20]; 590 591 u8 metadata_reg_c_0[0x20]; 592 593 u8 metadata_reg_a[0x20]; 594 595 u8 reserved_at_1a0[0x60]; 596 }; 597 598 struct mlx5_ifc_fte_match_set_misc3_bits { 599 u8 inner_tcp_seq_num[0x20]; 600 601 u8 outer_tcp_seq_num[0x20]; 602 603 u8 inner_tcp_ack_num[0x20]; 604 605 u8 outer_tcp_ack_num[0x20]; 606 607 u8 reserved_at_80[0x8]; 608 u8 outer_vxlan_gpe_vni[0x18]; 609 610 u8 outer_vxlan_gpe_next_protocol[0x8]; 611 u8 outer_vxlan_gpe_flags[0x8]; 612 u8 reserved_at_b0[0x10]; 613 614 u8 icmp_header_data[0x20]; 615 616 u8 icmpv6_header_data[0x20]; 617 618 u8 icmp_type[0x8]; 619 u8 icmp_code[0x8]; 620 u8 icmpv6_type[0x8]; 621 u8 icmpv6_code[0x8]; 622 623 u8 geneve_tlv_option_0_data[0x20]; 624 625 u8 reserved_at_140[0xc0]; 626 }; 627 628 struct mlx5_ifc_fte_match_set_misc4_bits { 629 u8 prog_sample_field_value_0[0x20]; 630 631 u8 prog_sample_field_id_0[0x20]; 632 633 u8 prog_sample_field_value_1[0x20]; 634 635 u8 prog_sample_field_id_1[0x20]; 636 637 u8 prog_sample_field_value_2[0x20]; 638 639 u8 prog_sample_field_id_2[0x20]; 640 641 u8 prog_sample_field_value_3[0x20]; 642 643 u8 prog_sample_field_id_3[0x20]; 644 645 u8 reserved_at_100[0x100]; 646 }; 647 648 struct mlx5_ifc_cmd_pas_bits { 649 u8 pa_h[0x20]; 650 651 u8 pa_l[0x14]; 652 u8 reserved_at_34[0xc]; 653 }; 654 655 struct mlx5_ifc_uint64_bits { 656 u8 hi[0x20]; 657 658 u8 lo[0x20]; 659 }; 660 661 enum { 662 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0, 663 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7, 664 MLX5_ADS_STAT_RATE_10GBPS = 0x8, 665 MLX5_ADS_STAT_RATE_30GBPS = 0x9, 666 MLX5_ADS_STAT_RATE_5GBPS = 0xa, 667 MLX5_ADS_STAT_RATE_20GBPS = 0xb, 668 MLX5_ADS_STAT_RATE_40GBPS = 0xc, 669 MLX5_ADS_STAT_RATE_60GBPS = 0xd, 670 MLX5_ADS_STAT_RATE_80GBPS = 0xe, 671 MLX5_ADS_STAT_RATE_120GBPS = 0xf, 672 }; 673 674 struct mlx5_ifc_ads_bits { 675 u8 fl[0x1]; 676 u8 free_ar[0x1]; 677 u8 reserved_at_2[0xe]; 678 u8 pkey_index[0x10]; 679 680 u8 reserved_at_20[0x8]; 681 u8 grh[0x1]; 682 u8 mlid[0x7]; 683 u8 rlid[0x10]; 684 685 u8 ack_timeout[0x5]; 686 u8 reserved_at_45[0x3]; 687 u8 src_addr_index[0x8]; 688 u8 reserved_at_50[0x4]; 689 u8 stat_rate[0x4]; 690 u8 hop_limit[0x8]; 691 692 u8 reserved_at_60[0x4]; 693 u8 tclass[0x8]; 694 u8 flow_label[0x14]; 695 696 u8 rgid_rip[16][0x8]; 697 698 u8 reserved_at_100[0x4]; 699 u8 f_dscp[0x1]; 700 u8 f_ecn[0x1]; 701 u8 reserved_at_106[0x1]; 702 u8 f_eth_prio[0x1]; 703 u8 ecn[0x2]; 704 u8 dscp[0x6]; 705 u8 udp_sport[0x10]; 706 707 u8 dei_cfi[0x1]; 708 u8 eth_prio[0x3]; 709 u8 sl[0x4]; 710 u8 vhca_port_num[0x8]; 711 u8 rmac_47_32[0x10]; 712 713 u8 rmac_31_0[0x20]; 714 }; 715 716 struct mlx5_ifc_flow_table_nic_cap_bits { 717 u8 nic_rx_multi_path_tirs[0x1]; 718 u8 nic_rx_multi_path_tirs_fts[0x1]; 719 u8 allow_sniffer_and_nic_rx_shared_tir[0x1]; 720 u8 reserved_at_3[0x4]; 721 u8 sw_owner_reformat_supported[0x1]; 722 u8 reserved_at_8[0x18]; 723 724 u8 encap_general_header[0x1]; 725 u8 reserved_at_21[0xa]; 726 u8 log_max_packet_reformat_context[0x5]; 727 u8 reserved_at_30[0x6]; 728 u8 max_encap_header_size[0xa]; 729 u8 reserved_at_40[0x1c0]; 730 731 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive; 732 733 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_rdma; 734 735 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer; 736 737 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit; 738 739 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_rdma; 740 741 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer; 742 743 u8 reserved_at_e00[0x1200]; 744 745 u8 sw_steering_nic_rx_action_drop_icm_address[0x40]; 746 747 u8 sw_steering_nic_tx_action_drop_icm_address[0x40]; 748 749 u8 sw_steering_nic_tx_action_allow_icm_address[0x40]; 750 751 u8 reserved_at_20c0[0x5f40]; 752 }; 753 754 enum { 755 MLX5_FDB_TO_VPORT_REG_C_0 = 0x01, 756 MLX5_FDB_TO_VPORT_REG_C_1 = 0x02, 757 MLX5_FDB_TO_VPORT_REG_C_2 = 0x04, 758 MLX5_FDB_TO_VPORT_REG_C_3 = 0x08, 759 MLX5_FDB_TO_VPORT_REG_C_4 = 0x10, 760 MLX5_FDB_TO_VPORT_REG_C_5 = 0x20, 761 MLX5_FDB_TO_VPORT_REG_C_6 = 0x40, 762 MLX5_FDB_TO_VPORT_REG_C_7 = 0x80, 763 }; 764 765 struct mlx5_ifc_flow_table_eswitch_cap_bits { 766 u8 fdb_to_vport_reg_c_id[0x8]; 767 u8 reserved_at_8[0xd]; 768 u8 fdb_modify_header_fwd_to_table[0x1]; 769 u8 reserved_at_16[0x1]; 770 u8 flow_source[0x1]; 771 u8 reserved_at_18[0x2]; 772 u8 multi_fdb_encap[0x1]; 773 u8 egress_acl_forward_to_vport[0x1]; 774 u8 fdb_multi_path_to_table[0x1]; 775 u8 reserved_at_1d[0x3]; 776 777 u8 reserved_at_20[0x1e0]; 778 779 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb; 780 781 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress; 782 783 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress; 784 785 u8 reserved_at_800[0x1000]; 786 787 u8 sw_steering_fdb_action_drop_icm_address_rx[0x40]; 788 789 u8 sw_steering_fdb_action_drop_icm_address_tx[0x40]; 790 791 u8 sw_steering_uplink_icm_address_rx[0x40]; 792 793 u8 sw_steering_uplink_icm_address_tx[0x40]; 794 795 u8 reserved_at_1900[0x6700]; 796 }; 797 798 enum { 799 MLX5_COUNTER_SOURCE_ESWITCH = 0x0, 800 MLX5_COUNTER_FLOW_ESWITCH = 0x1, 801 }; 802 803 struct mlx5_ifc_e_switch_cap_bits { 804 u8 vport_svlan_strip[0x1]; 805 u8 vport_cvlan_strip[0x1]; 806 u8 vport_svlan_insert[0x1]; 807 u8 vport_cvlan_insert_if_not_exist[0x1]; 808 u8 vport_cvlan_insert_overwrite[0x1]; 809 u8 reserved_at_5[0x3]; 810 u8 esw_uplink_ingress_acl[0x1]; 811 u8 reserved_at_9[0x10]; 812 u8 esw_functions_changed[0x1]; 813 u8 reserved_at_1a[0x1]; 814 u8 ecpf_vport_exists[0x1]; 815 u8 counter_eswitch_affinity[0x1]; 816 u8 merged_eswitch[0x1]; 817 u8 nic_vport_node_guid_modify[0x1]; 818 u8 nic_vport_port_guid_modify[0x1]; 819 820 u8 vxlan_encap_decap[0x1]; 821 u8 nvgre_encap_decap[0x1]; 822 u8 reserved_at_22[0x1]; 823 u8 log_max_fdb_encap_uplink[0x5]; 824 u8 reserved_at_21[0x3]; 825 u8 log_max_packet_reformat_context[0x5]; 826 u8 reserved_2b[0x6]; 827 u8 max_encap_header_size[0xa]; 828 829 u8 reserved_at_40[0xb]; 830 u8 log_max_esw_sf[0x5]; 831 u8 esw_sf_base_id[0x10]; 832 833 u8 reserved_at_60[0x7a0]; 834 835 }; 836 837 struct mlx5_ifc_qos_cap_bits { 838 u8 packet_pacing[0x1]; 839 u8 esw_scheduling[0x1]; 840 u8 esw_bw_share[0x1]; 841 u8 esw_rate_limit[0x1]; 842 u8 reserved_at_4[0x1]; 843 u8 packet_pacing_burst_bound[0x1]; 844 u8 packet_pacing_typical_size[0x1]; 845 u8 reserved_at_7[0x4]; 846 u8 packet_pacing_uid[0x1]; 847 u8 reserved_at_c[0x14]; 848 849 u8 reserved_at_20[0x20]; 850 851 u8 packet_pacing_max_rate[0x20]; 852 853 u8 packet_pacing_min_rate[0x20]; 854 855 u8 reserved_at_80[0x10]; 856 u8 packet_pacing_rate_table_size[0x10]; 857 858 u8 esw_element_type[0x10]; 859 u8 esw_tsar_type[0x10]; 860 861 u8 reserved_at_c0[0x10]; 862 u8 max_qos_para_vport[0x10]; 863 864 u8 max_tsar_bw_share[0x20]; 865 866 u8 reserved_at_100[0x700]; 867 }; 868 869 struct mlx5_ifc_debug_cap_bits { 870 u8 core_dump_general[0x1]; 871 u8 core_dump_qp[0x1]; 872 u8 reserved_at_2[0x7]; 873 u8 resource_dump[0x1]; 874 u8 reserved_at_a[0x16]; 875 876 u8 reserved_at_20[0x2]; 877 u8 stall_detect[0x1]; 878 u8 reserved_at_23[0x1d]; 879 880 u8 reserved_at_40[0x7c0]; 881 }; 882 883 struct mlx5_ifc_per_protocol_networking_offload_caps_bits { 884 u8 csum_cap[0x1]; 885 u8 vlan_cap[0x1]; 886 u8 lro_cap[0x1]; 887 u8 lro_psh_flag[0x1]; 888 u8 lro_time_stamp[0x1]; 889 u8 reserved_at_5[0x2]; 890 u8 wqe_vlan_insert[0x1]; 891 u8 self_lb_en_modifiable[0x1]; 892 u8 reserved_at_9[0x2]; 893 u8 max_lso_cap[0x5]; 894 u8 multi_pkt_send_wqe[0x2]; 895 u8 wqe_inline_mode[0x2]; 896 u8 rss_ind_tbl_cap[0x4]; 897 u8 reg_umr_sq[0x1]; 898 u8 scatter_fcs[0x1]; 899 u8 enhanced_multi_pkt_send_wqe[0x1]; 900 u8 tunnel_lso_const_out_ip_id[0x1]; 901 u8 reserved_at_1c[0x2]; 902 u8 tunnel_stateless_gre[0x1]; 903 u8 tunnel_stateless_vxlan[0x1]; 904 905 u8 swp[0x1]; 906 u8 swp_csum[0x1]; 907 u8 swp_lso[0x1]; 908 u8 cqe_checksum_full[0x1]; 909 u8 tunnel_stateless_geneve_tx[0x1]; 910 u8 tunnel_stateless_mpls_over_udp[0x1]; 911 u8 tunnel_stateless_mpls_over_gre[0x1]; 912 u8 tunnel_stateless_vxlan_gpe[0x1]; 913 u8 tunnel_stateless_ipv4_over_vxlan[0x1]; 914 u8 tunnel_stateless_ip_over_ip[0x1]; 915 u8 insert_trailer[0x1]; 916 u8 reserved_at_2b[0x1]; 917 u8 tunnel_stateless_ip_over_ip_rx[0x1]; 918 u8 tunnel_stateless_ip_over_ip_tx[0x1]; 919 u8 reserved_at_2e[0x2]; 920 u8 max_vxlan_udp_ports[0x8]; 921 u8 reserved_at_38[0x6]; 922 u8 max_geneve_opt_len[0x1]; 923 u8 tunnel_stateless_geneve_rx[0x1]; 924 925 u8 reserved_at_40[0x10]; 926 u8 lro_min_mss_size[0x10]; 927 928 u8 reserved_at_60[0x120]; 929 930 u8 lro_timer_supported_periods[4][0x20]; 931 932 u8 reserved_at_200[0x600]; 933 }; 934 935 struct mlx5_ifc_roce_cap_bits { 936 u8 roce_apm[0x1]; 937 u8 reserved_at_1[0x3]; 938 u8 sw_r_roce_src_udp_port[0x1]; 939 u8 reserved_at_5[0x1b]; 940 941 u8 reserved_at_20[0x60]; 942 943 u8 reserved_at_80[0xc]; 944 u8 l3_type[0x4]; 945 u8 reserved_at_90[0x8]; 946 u8 roce_version[0x8]; 947 948 u8 reserved_at_a0[0x10]; 949 u8 r_roce_dest_udp_port[0x10]; 950 951 u8 r_roce_max_src_udp_port[0x10]; 952 u8 r_roce_min_src_udp_port[0x10]; 953 954 u8 reserved_at_e0[0x10]; 955 u8 roce_address_table_size[0x10]; 956 957 u8 reserved_at_100[0x700]; 958 }; 959 960 struct mlx5_ifc_sync_steering_in_bits { 961 u8 opcode[0x10]; 962 u8 uid[0x10]; 963 964 u8 reserved_at_20[0x10]; 965 u8 op_mod[0x10]; 966 967 u8 reserved_at_40[0xc0]; 968 }; 969 970 struct mlx5_ifc_sync_steering_out_bits { 971 u8 status[0x8]; 972 u8 reserved_at_8[0x18]; 973 974 u8 syndrome[0x20]; 975 976 u8 reserved_at_40[0x40]; 977 }; 978 979 struct mlx5_ifc_device_mem_cap_bits { 980 u8 memic[0x1]; 981 u8 reserved_at_1[0x1f]; 982 983 u8 reserved_at_20[0xb]; 984 u8 log_min_memic_alloc_size[0x5]; 985 u8 reserved_at_30[0x8]; 986 u8 log_max_memic_addr_alignment[0x8]; 987 988 u8 memic_bar_start_addr[0x40]; 989 990 u8 memic_bar_size[0x20]; 991 992 u8 max_memic_size[0x20]; 993 994 u8 steering_sw_icm_start_address[0x40]; 995 996 u8 reserved_at_100[0x8]; 997 u8 log_header_modify_sw_icm_size[0x8]; 998 u8 reserved_at_110[0x2]; 999 u8 log_sw_icm_alloc_granularity[0x6]; 1000 u8 log_steering_sw_icm_size[0x8]; 1001 1002 u8 reserved_at_120[0x20]; 1003 1004 u8 header_modify_sw_icm_start_address[0x40]; 1005 1006 u8 reserved_at_180[0x680]; 1007 }; 1008 1009 struct mlx5_ifc_device_event_cap_bits { 1010 u8 user_affiliated_events[4][0x40]; 1011 1012 u8 user_unaffiliated_events[4][0x40]; 1013 }; 1014 1015 struct mlx5_ifc_virtio_emulation_cap_bits { 1016 u8 desc_tunnel_offload_type[0x1]; 1017 u8 eth_frame_offload_type[0x1]; 1018 u8 virtio_version_1_0[0x1]; 1019 u8 device_features_bits_mask[0xd]; 1020 u8 event_mode[0x8]; 1021 u8 virtio_queue_type[0x8]; 1022 1023 u8 max_tunnel_desc[0x10]; 1024 u8 reserved_at_30[0x3]; 1025 u8 log_doorbell_stride[0x5]; 1026 u8 reserved_at_38[0x3]; 1027 u8 log_doorbell_bar_size[0x5]; 1028 1029 u8 doorbell_bar_offset[0x40]; 1030 1031 u8 max_emulated_devices[0x8]; 1032 u8 max_num_virtio_queues[0x18]; 1033 1034 u8 reserved_at_a0[0x60]; 1035 1036 u8 umem_1_buffer_param_a[0x20]; 1037 1038 u8 umem_1_buffer_param_b[0x20]; 1039 1040 u8 umem_2_buffer_param_a[0x20]; 1041 1042 u8 umem_2_buffer_param_b[0x20]; 1043 1044 u8 umem_3_buffer_param_a[0x20]; 1045 1046 u8 umem_3_buffer_param_b[0x20]; 1047 1048 u8 reserved_at_1c0[0x640]; 1049 }; 1050 1051 enum { 1052 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0, 1053 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2, 1054 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4, 1055 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8, 1056 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10, 1057 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20, 1058 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40, 1059 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80, 1060 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100, 1061 }; 1062 1063 enum { 1064 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1, 1065 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2, 1066 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4, 1067 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8, 1068 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10, 1069 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20, 1070 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40, 1071 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80, 1072 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100, 1073 }; 1074 1075 struct mlx5_ifc_atomic_caps_bits { 1076 u8 reserved_at_0[0x40]; 1077 1078 u8 atomic_req_8B_endianness_mode[0x2]; 1079 u8 reserved_at_42[0x4]; 1080 u8 supported_atomic_req_8B_endianness_mode_1[0x1]; 1081 1082 u8 reserved_at_47[0x19]; 1083 1084 u8 reserved_at_60[0x20]; 1085 1086 u8 reserved_at_80[0x10]; 1087 u8 atomic_operations[0x10]; 1088 1089 u8 reserved_at_a0[0x10]; 1090 u8 atomic_size_qp[0x10]; 1091 1092 u8 reserved_at_c0[0x10]; 1093 u8 atomic_size_dc[0x10]; 1094 1095 u8 reserved_at_e0[0x720]; 1096 }; 1097 1098 struct mlx5_ifc_odp_cap_bits { 1099 u8 reserved_at_0[0x40]; 1100 1101 u8 sig[0x1]; 1102 u8 reserved_at_41[0x1f]; 1103 1104 u8 reserved_at_60[0x20]; 1105 1106 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps; 1107 1108 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps; 1109 1110 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps; 1111 1112 struct mlx5_ifc_odp_per_transport_service_cap_bits xrc_odp_caps; 1113 1114 struct mlx5_ifc_odp_per_transport_service_cap_bits dc_odp_caps; 1115 1116 u8 reserved_at_120[0x6E0]; 1117 }; 1118 1119 struct mlx5_ifc_calc_op { 1120 u8 reserved_at_0[0x10]; 1121 u8 reserved_at_10[0x9]; 1122 u8 op_swap_endianness[0x1]; 1123 u8 op_min[0x1]; 1124 u8 op_xor[0x1]; 1125 u8 op_or[0x1]; 1126 u8 op_and[0x1]; 1127 u8 op_max[0x1]; 1128 u8 op_add[0x1]; 1129 }; 1130 1131 struct mlx5_ifc_vector_calc_cap_bits { 1132 u8 calc_matrix[0x1]; 1133 u8 reserved_at_1[0x1f]; 1134 u8 reserved_at_20[0x8]; 1135 u8 max_vec_count[0x8]; 1136 u8 reserved_at_30[0xd]; 1137 u8 max_chunk_size[0x3]; 1138 struct mlx5_ifc_calc_op calc0; 1139 struct mlx5_ifc_calc_op calc1; 1140 struct mlx5_ifc_calc_op calc2; 1141 struct mlx5_ifc_calc_op calc3; 1142 1143 u8 reserved_at_c0[0x720]; 1144 }; 1145 1146 struct mlx5_ifc_tls_cap_bits { 1147 u8 tls_1_2_aes_gcm_128[0x1]; 1148 u8 tls_1_3_aes_gcm_128[0x1]; 1149 u8 tls_1_2_aes_gcm_256[0x1]; 1150 u8 tls_1_3_aes_gcm_256[0x1]; 1151 u8 reserved_at_4[0x1c]; 1152 1153 u8 reserved_at_20[0x7e0]; 1154 }; 1155 1156 struct mlx5_ifc_ipsec_cap_bits { 1157 u8 ipsec_full_offload[0x1]; 1158 u8 ipsec_crypto_offload[0x1]; 1159 u8 ipsec_esn[0x1]; 1160 u8 ipsec_crypto_esp_aes_gcm_256_encrypt[0x1]; 1161 u8 ipsec_crypto_esp_aes_gcm_128_encrypt[0x1]; 1162 u8 ipsec_crypto_esp_aes_gcm_256_decrypt[0x1]; 1163 u8 ipsec_crypto_esp_aes_gcm_128_decrypt[0x1]; 1164 u8 reserved_at_7[0x4]; 1165 u8 log_max_ipsec_offload[0x5]; 1166 u8 reserved_at_10[0x10]; 1167 1168 u8 min_log_ipsec_full_replay_window[0x8]; 1169 u8 max_log_ipsec_full_replay_window[0x8]; 1170 u8 reserved_at_30[0x7d0]; 1171 }; 1172 1173 enum { 1174 MLX5_WQ_TYPE_LINKED_LIST = 0x0, 1175 MLX5_WQ_TYPE_CYCLIC = 0x1, 1176 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2, 1177 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3, 1178 }; 1179 1180 enum { 1181 MLX5_WQ_END_PAD_MODE_NONE = 0x0, 1182 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1, 1183 }; 1184 1185 enum { 1186 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0, 1187 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1, 1188 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2, 1189 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3, 1190 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4, 1191 }; 1192 1193 enum { 1194 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0, 1195 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1, 1196 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2, 1197 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3, 1198 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4, 1199 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5, 1200 }; 1201 1202 enum { 1203 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0, 1204 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1, 1205 }; 1206 1207 enum { 1208 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0, 1209 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1, 1210 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3, 1211 }; 1212 1213 enum { 1214 MLX5_CAP_PORT_TYPE_IB = 0x0, 1215 MLX5_CAP_PORT_TYPE_ETH = 0x1, 1216 }; 1217 1218 enum { 1219 MLX5_CAP_UMR_FENCE_STRONG = 0x0, 1220 MLX5_CAP_UMR_FENCE_SMALL = 0x1, 1221 MLX5_CAP_UMR_FENCE_NONE = 0x2, 1222 }; 1223 1224 enum { 1225 MLX5_FLEX_PARSER_GENEVE_ENABLED = 1 << 3, 1226 MLX5_FLEX_PARSER_VXLAN_GPE_ENABLED = 1 << 7, 1227 MLX5_FLEX_PARSER_ICMP_V4_ENABLED = 1 << 8, 1228 MLX5_FLEX_PARSER_ICMP_V6_ENABLED = 1 << 9, 1229 }; 1230 1231 enum { 1232 MLX5_UCTX_CAP_RAW_TX = 1UL << 0, 1233 MLX5_UCTX_CAP_INTERNAL_DEV_RES = 1UL << 1, 1234 }; 1235 1236 #define MLX5_FC_BULK_SIZE_FACTOR 128 1237 1238 enum mlx5_fc_bulk_alloc_bitmask { 1239 MLX5_FC_BULK_128 = (1 << 0), 1240 MLX5_FC_BULK_256 = (1 << 1), 1241 MLX5_FC_BULK_512 = (1 << 2), 1242 MLX5_FC_BULK_1024 = (1 << 3), 1243 MLX5_FC_BULK_2048 = (1 << 4), 1244 MLX5_FC_BULK_4096 = (1 << 5), 1245 MLX5_FC_BULK_8192 = (1 << 6), 1246 MLX5_FC_BULK_16384 = (1 << 7), 1247 }; 1248 1249 #define MLX5_FC_BULK_NUM_FCS(fc_enum) (MLX5_FC_BULK_SIZE_FACTOR * (fc_enum)) 1250 1251 enum { 1252 MLX5_STEERING_FORMAT_CONNECTX_5 = 0, 1253 MLX5_STEERING_FORMAT_CONNECTX_6DX = 1, 1254 }; 1255 1256 struct mlx5_ifc_cmd_hca_cap_bits { 1257 u8 reserved_at_0[0x1f]; 1258 u8 vhca_resource_manager[0x1]; 1259 1260 u8 reserved_at_20[0x3]; 1261 u8 event_on_vhca_state_teardown_request[0x1]; 1262 u8 event_on_vhca_state_in_use[0x1]; 1263 u8 event_on_vhca_state_active[0x1]; 1264 u8 event_on_vhca_state_allocated[0x1]; 1265 u8 event_on_vhca_state_invalid[0x1]; 1266 u8 reserved_at_28[0x8]; 1267 u8 vhca_id[0x10]; 1268 1269 u8 reserved_at_40[0x40]; 1270 1271 u8 log_max_srq_sz[0x8]; 1272 u8 log_max_qp_sz[0x8]; 1273 u8 event_cap[0x1]; 1274 u8 reserved_at_91[0x7]; 1275 u8 prio_tag_required[0x1]; 1276 u8 reserved_at_99[0x2]; 1277 u8 log_max_qp[0x5]; 1278 1279 u8 reserved_at_a0[0x3]; 1280 u8 ece_support[0x1]; 1281 u8 reserved_at_a4[0x7]; 1282 u8 log_max_srq[0x5]; 1283 u8 reserved_at_b0[0x2]; 1284 u8 ts_cqe_to_dest_cqn[0x1]; 1285 u8 reserved_at_b3[0xd]; 1286 1287 u8 max_sgl_for_optimized_performance[0x8]; 1288 u8 log_max_cq_sz[0x8]; 1289 u8 relaxed_ordering_write_umr[0x1]; 1290 u8 relaxed_ordering_read_umr[0x1]; 1291 u8 reserved_at_d2[0x7]; 1292 u8 virtio_net_device_emualtion_manager[0x1]; 1293 u8 virtio_blk_device_emualtion_manager[0x1]; 1294 u8 log_max_cq[0x5]; 1295 1296 u8 log_max_eq_sz[0x8]; 1297 u8 relaxed_ordering_write[0x1]; 1298 u8 relaxed_ordering_read[0x1]; 1299 u8 log_max_mkey[0x6]; 1300 u8 reserved_at_f0[0x8]; 1301 u8 dump_fill_mkey[0x1]; 1302 u8 reserved_at_f9[0x2]; 1303 u8 fast_teardown[0x1]; 1304 u8 log_max_eq[0x4]; 1305 1306 u8 max_indirection[0x8]; 1307 u8 fixed_buffer_size[0x1]; 1308 u8 log_max_mrw_sz[0x7]; 1309 u8 force_teardown[0x1]; 1310 u8 reserved_at_111[0x1]; 1311 u8 log_max_bsf_list_size[0x6]; 1312 u8 umr_extended_translation_offset[0x1]; 1313 u8 null_mkey[0x1]; 1314 u8 log_max_klm_list_size[0x6]; 1315 1316 u8 reserved_at_120[0xa]; 1317 u8 log_max_ra_req_dc[0x6]; 1318 u8 reserved_at_130[0xa]; 1319 u8 log_max_ra_res_dc[0x6]; 1320 1321 u8 reserved_at_140[0x6]; 1322 u8 release_all_pages[0x1]; 1323 u8 reserved_at_147[0x2]; 1324 u8 roce_accl[0x1]; 1325 u8 log_max_ra_req_qp[0x6]; 1326 u8 reserved_at_150[0xa]; 1327 u8 log_max_ra_res_qp[0x6]; 1328 1329 u8 end_pad[0x1]; 1330 u8 cc_query_allowed[0x1]; 1331 u8 cc_modify_allowed[0x1]; 1332 u8 start_pad[0x1]; 1333 u8 cache_line_128byte[0x1]; 1334 u8 reserved_at_165[0x4]; 1335 u8 rts2rts_qp_counters_set_id[0x1]; 1336 u8 reserved_at_16a[0x2]; 1337 u8 vnic_env_int_rq_oob[0x1]; 1338 u8 sbcam_reg[0x1]; 1339 u8 reserved_at_16e[0x1]; 1340 u8 qcam_reg[0x1]; 1341 u8 gid_table_size[0x10]; 1342 1343 u8 out_of_seq_cnt[0x1]; 1344 u8 vport_counters[0x1]; 1345 u8 retransmission_q_counters[0x1]; 1346 u8 debug[0x1]; 1347 u8 modify_rq_counter_set_id[0x1]; 1348 u8 rq_delay_drop[0x1]; 1349 u8 max_qp_cnt[0xa]; 1350 u8 pkey_table_size[0x10]; 1351 1352 u8 vport_group_manager[0x1]; 1353 u8 vhca_group_manager[0x1]; 1354 u8 ib_virt[0x1]; 1355 u8 eth_virt[0x1]; 1356 u8 vnic_env_queue_counters[0x1]; 1357 u8 ets[0x1]; 1358 u8 nic_flow_table[0x1]; 1359 u8 eswitch_manager[0x1]; 1360 u8 device_memory[0x1]; 1361 u8 mcam_reg[0x1]; 1362 u8 pcam_reg[0x1]; 1363 u8 local_ca_ack_delay[0x5]; 1364 u8 port_module_event[0x1]; 1365 u8 enhanced_error_q_counters[0x1]; 1366 u8 ports_check[0x1]; 1367 u8 reserved_at_1b3[0x1]; 1368 u8 disable_link_up[0x1]; 1369 u8 beacon_led[0x1]; 1370 u8 port_type[0x2]; 1371 u8 num_ports[0x8]; 1372 1373 u8 reserved_at_1c0[0x1]; 1374 u8 pps[0x1]; 1375 u8 pps_modify[0x1]; 1376 u8 log_max_msg[0x5]; 1377 u8 reserved_at_1c8[0x4]; 1378 u8 max_tc[0x4]; 1379 u8 temp_warn_event[0x1]; 1380 u8 dcbx[0x1]; 1381 u8 general_notification_event[0x1]; 1382 u8 reserved_at_1d3[0x2]; 1383 u8 fpga[0x1]; 1384 u8 rol_s[0x1]; 1385 u8 rol_g[0x1]; 1386 u8 reserved_at_1d8[0x1]; 1387 u8 wol_s[0x1]; 1388 u8 wol_g[0x1]; 1389 u8 wol_a[0x1]; 1390 u8 wol_b[0x1]; 1391 u8 wol_m[0x1]; 1392 u8 wol_u[0x1]; 1393 u8 wol_p[0x1]; 1394 1395 u8 stat_rate_support[0x10]; 1396 u8 reserved_at_1f0[0x1]; 1397 u8 pci_sync_for_fw_update_event[0x1]; 1398 u8 reserved_at_1f2[0x6]; 1399 u8 init2_lag_tx_port_affinity[0x1]; 1400 u8 reserved_at_1fa[0x3]; 1401 u8 cqe_version[0x4]; 1402 1403 u8 compact_address_vector[0x1]; 1404 u8 striding_rq[0x1]; 1405 u8 reserved_at_202[0x1]; 1406 u8 ipoib_enhanced_offloads[0x1]; 1407 u8 ipoib_basic_offloads[0x1]; 1408 u8 reserved_at_205[0x1]; 1409 u8 repeated_block_disabled[0x1]; 1410 u8 umr_modify_entity_size_disabled[0x1]; 1411 u8 umr_modify_atomic_disabled[0x1]; 1412 u8 umr_indirect_mkey_disabled[0x1]; 1413 u8 umr_fence[0x2]; 1414 u8 dc_req_scat_data_cqe[0x1]; 1415 u8 reserved_at_20d[0x2]; 1416 u8 drain_sigerr[0x1]; 1417 u8 cmdif_checksum[0x2]; 1418 u8 sigerr_cqe[0x1]; 1419 u8 reserved_at_213[0x1]; 1420 u8 wq_signature[0x1]; 1421 u8 sctr_data_cqe[0x1]; 1422 u8 reserved_at_216[0x1]; 1423 u8 sho[0x1]; 1424 u8 tph[0x1]; 1425 u8 rf[0x1]; 1426 u8 dct[0x1]; 1427 u8 qos[0x1]; 1428 u8 eth_net_offloads[0x1]; 1429 u8 roce[0x1]; 1430 u8 atomic[0x1]; 1431 u8 reserved_at_21f[0x1]; 1432 1433 u8 cq_oi[0x1]; 1434 u8 cq_resize[0x1]; 1435 u8 cq_moderation[0x1]; 1436 u8 reserved_at_223[0x3]; 1437 u8 cq_eq_remap[0x1]; 1438 u8 pg[0x1]; 1439 u8 block_lb_mc[0x1]; 1440 u8 reserved_at_229[0x1]; 1441 u8 scqe_break_moderation[0x1]; 1442 u8 cq_period_start_from_cqe[0x1]; 1443 u8 cd[0x1]; 1444 u8 reserved_at_22d[0x1]; 1445 u8 apm[0x1]; 1446 u8 vector_calc[0x1]; 1447 u8 umr_ptr_rlky[0x1]; 1448 u8 imaicl[0x1]; 1449 u8 qp_packet_based[0x1]; 1450 u8 reserved_at_233[0x3]; 1451 u8 qkv[0x1]; 1452 u8 pkv[0x1]; 1453 u8 set_deth_sqpn[0x1]; 1454 u8 reserved_at_239[0x3]; 1455 u8 xrc[0x1]; 1456 u8 ud[0x1]; 1457 u8 uc[0x1]; 1458 u8 rc[0x1]; 1459 1460 u8 uar_4k[0x1]; 1461 u8 reserved_at_241[0x9]; 1462 u8 uar_sz[0x6]; 1463 u8 reserved_at_250[0x8]; 1464 u8 log_pg_sz[0x8]; 1465 1466 u8 bf[0x1]; 1467 u8 driver_version[0x1]; 1468 u8 pad_tx_eth_packet[0x1]; 1469 u8 reserved_at_263[0x3]; 1470 u8 mkey_by_name[0x1]; 1471 u8 reserved_at_267[0x4]; 1472 1473 u8 log_bf_reg_size[0x5]; 1474 1475 u8 reserved_at_270[0x6]; 1476 u8 lag_dct[0x2]; 1477 u8 lag_tx_port_affinity[0x1]; 1478 u8 reserved_at_279[0x2]; 1479 u8 lag_master[0x1]; 1480 u8 num_lag_ports[0x4]; 1481 1482 u8 reserved_at_280[0x10]; 1483 u8 max_wqe_sz_sq[0x10]; 1484 1485 u8 reserved_at_2a0[0x10]; 1486 u8 max_wqe_sz_rq[0x10]; 1487 1488 u8 max_flow_counter_31_16[0x10]; 1489 u8 max_wqe_sz_sq_dc[0x10]; 1490 1491 u8 reserved_at_2e0[0x7]; 1492 u8 max_qp_mcg[0x19]; 1493 1494 u8 reserved_at_300[0x10]; 1495 u8 flow_counter_bulk_alloc[0x8]; 1496 u8 log_max_mcg[0x8]; 1497 1498 u8 reserved_at_320[0x3]; 1499 u8 log_max_transport_domain[0x5]; 1500 u8 reserved_at_328[0x3]; 1501 u8 log_max_pd[0x5]; 1502 u8 reserved_at_330[0xb]; 1503 u8 log_max_xrcd[0x5]; 1504 1505 u8 nic_receive_steering_discard[0x1]; 1506 u8 receive_discard_vport_down[0x1]; 1507 u8 transmit_discard_vport_down[0x1]; 1508 u8 reserved_at_343[0x5]; 1509 u8 log_max_flow_counter_bulk[0x8]; 1510 u8 max_flow_counter_15_0[0x10]; 1511 1512 1513 u8 reserved_at_360[0x3]; 1514 u8 log_max_rq[0x5]; 1515 u8 reserved_at_368[0x3]; 1516 u8 log_max_sq[0x5]; 1517 u8 reserved_at_370[0x3]; 1518 u8 log_max_tir[0x5]; 1519 u8 reserved_at_378[0x3]; 1520 u8 log_max_tis[0x5]; 1521 1522 u8 basic_cyclic_rcv_wqe[0x1]; 1523 u8 reserved_at_381[0x2]; 1524 u8 log_max_rmp[0x5]; 1525 u8 reserved_at_388[0x3]; 1526 u8 log_max_rqt[0x5]; 1527 u8 reserved_at_390[0x3]; 1528 u8 log_max_rqt_size[0x5]; 1529 u8 reserved_at_398[0x3]; 1530 u8 log_max_tis_per_sq[0x5]; 1531 1532 u8 ext_stride_num_range[0x1]; 1533 u8 reserved_at_3a1[0x2]; 1534 u8 log_max_stride_sz_rq[0x5]; 1535 u8 reserved_at_3a8[0x3]; 1536 u8 log_min_stride_sz_rq[0x5]; 1537 u8 reserved_at_3b0[0x3]; 1538 u8 log_max_stride_sz_sq[0x5]; 1539 u8 reserved_at_3b8[0x3]; 1540 u8 log_min_stride_sz_sq[0x5]; 1541 1542 u8 hairpin[0x1]; 1543 u8 reserved_at_3c1[0x2]; 1544 u8 log_max_hairpin_queues[0x5]; 1545 u8 reserved_at_3c8[0x3]; 1546 u8 log_max_hairpin_wq_data_sz[0x5]; 1547 u8 reserved_at_3d0[0x3]; 1548 u8 log_max_hairpin_num_packets[0x5]; 1549 u8 reserved_at_3d8[0x3]; 1550 u8 log_max_wq_sz[0x5]; 1551 1552 u8 nic_vport_change_event[0x1]; 1553 u8 disable_local_lb_uc[0x1]; 1554 u8 disable_local_lb_mc[0x1]; 1555 u8 log_min_hairpin_wq_data_sz[0x5]; 1556 u8 reserved_at_3e8[0x2]; 1557 u8 vhca_state[0x1]; 1558 u8 log_max_vlan_list[0x5]; 1559 u8 reserved_at_3f0[0x3]; 1560 u8 log_max_current_mc_list[0x5]; 1561 u8 reserved_at_3f8[0x3]; 1562 u8 log_max_current_uc_list[0x5]; 1563 1564 u8 general_obj_types[0x40]; 1565 1566 u8 reserved_at_440[0x4]; 1567 u8 steering_format_version[0x4]; 1568 u8 create_qp_start_hint[0x18]; 1569 1570 u8 reserved_at_460[0x3]; 1571 u8 log_max_uctx[0x5]; 1572 u8 reserved_at_468[0x2]; 1573 u8 ipsec_offload[0x1]; 1574 u8 log_max_umem[0x5]; 1575 u8 max_num_eqs[0x10]; 1576 1577 u8 reserved_at_480[0x1]; 1578 u8 tls_tx[0x1]; 1579 u8 tls_rx[0x1]; 1580 u8 log_max_l2_table[0x5]; 1581 u8 reserved_at_488[0x8]; 1582 u8 log_uar_page_sz[0x10]; 1583 1584 u8 reserved_at_4a0[0x20]; 1585 u8 device_frequency_mhz[0x20]; 1586 u8 device_frequency_khz[0x20]; 1587 1588 u8 reserved_at_500[0x20]; 1589 u8 num_of_uars_per_page[0x20]; 1590 1591 u8 flex_parser_protocols[0x20]; 1592 1593 u8 max_geneve_tlv_options[0x8]; 1594 u8 reserved_at_568[0x3]; 1595 u8 max_geneve_tlv_option_data_len[0x5]; 1596 u8 reserved_at_570[0x10]; 1597 1598 u8 reserved_at_580[0x33]; 1599 u8 log_max_dek[0x5]; 1600 u8 reserved_at_5b8[0x4]; 1601 u8 mini_cqe_resp_stride_index[0x1]; 1602 u8 cqe_128_always[0x1]; 1603 u8 cqe_compression_128[0x1]; 1604 u8 cqe_compression[0x1]; 1605 1606 u8 cqe_compression_timeout[0x10]; 1607 u8 cqe_compression_max_num[0x10]; 1608 1609 u8 reserved_at_5e0[0x10]; 1610 u8 tag_matching[0x1]; 1611 u8 rndv_offload_rc[0x1]; 1612 u8 rndv_offload_dc[0x1]; 1613 u8 log_tag_matching_list_sz[0x5]; 1614 u8 reserved_at_5f8[0x3]; 1615 u8 log_max_xrq[0x5]; 1616 1617 u8 affiliate_nic_vport_criteria[0x8]; 1618 u8 native_port_num[0x8]; 1619 u8 num_vhca_ports[0x8]; 1620 u8 reserved_at_618[0x6]; 1621 u8 sw_owner_id[0x1]; 1622 u8 reserved_at_61f[0x1]; 1623 1624 u8 max_num_of_monitor_counters[0x10]; 1625 u8 num_ppcnt_monitor_counters[0x10]; 1626 1627 u8 max_num_sf[0x10]; 1628 u8 num_q_monitor_counters[0x10]; 1629 1630 u8 reserved_at_660[0x20]; 1631 1632 u8 sf[0x1]; 1633 u8 sf_set_partition[0x1]; 1634 u8 reserved_at_682[0x1]; 1635 u8 log_max_sf[0x5]; 1636 u8 reserved_at_688[0x8]; 1637 u8 log_min_sf_size[0x8]; 1638 u8 max_num_sf_partitions[0x8]; 1639 1640 u8 uctx_cap[0x20]; 1641 1642 u8 reserved_at_6c0[0x4]; 1643 u8 flex_parser_id_geneve_tlv_option_0[0x4]; 1644 u8 flex_parser_id_icmp_dw1[0x4]; 1645 u8 flex_parser_id_icmp_dw0[0x4]; 1646 u8 flex_parser_id_icmpv6_dw1[0x4]; 1647 u8 flex_parser_id_icmpv6_dw0[0x4]; 1648 u8 flex_parser_id_outer_first_mpls_over_gre[0x4]; 1649 u8 flex_parser_id_outer_first_mpls_over_udp_label[0x4]; 1650 1651 u8 reserved_at_6e0[0x10]; 1652 u8 sf_base_id[0x10]; 1653 1654 u8 reserved_at_700[0x80]; 1655 u8 vhca_tunnel_commands[0x40]; 1656 u8 reserved_at_7c0[0x40]; 1657 }; 1658 1659 enum mlx5_flow_destination_type { 1660 MLX5_FLOW_DESTINATION_TYPE_VPORT = 0x0, 1661 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1, 1662 MLX5_FLOW_DESTINATION_TYPE_TIR = 0x2, 1663 MLX5_FLOW_DESTINATION_TYPE_FLOW_SAMPLER = 0x6, 1664 1665 MLX5_FLOW_DESTINATION_TYPE_PORT = 0x99, 1666 MLX5_FLOW_DESTINATION_TYPE_COUNTER = 0x100, 1667 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE_NUM = 0x101, 1668 }; 1669 1670 enum mlx5_flow_table_miss_action { 1671 MLX5_FLOW_TABLE_MISS_ACTION_DEF, 1672 MLX5_FLOW_TABLE_MISS_ACTION_FWD, 1673 MLX5_FLOW_TABLE_MISS_ACTION_SWITCH_DOMAIN, 1674 }; 1675 1676 struct mlx5_ifc_dest_format_struct_bits { 1677 u8 destination_type[0x8]; 1678 u8 destination_id[0x18]; 1679 1680 u8 destination_eswitch_owner_vhca_id_valid[0x1]; 1681 u8 packet_reformat[0x1]; 1682 u8 reserved_at_22[0xe]; 1683 u8 destination_eswitch_owner_vhca_id[0x10]; 1684 }; 1685 1686 struct mlx5_ifc_flow_counter_list_bits { 1687 u8 flow_counter_id[0x20]; 1688 1689 u8 reserved_at_20[0x20]; 1690 }; 1691 1692 struct mlx5_ifc_extended_dest_format_bits { 1693 struct mlx5_ifc_dest_format_struct_bits destination_entry; 1694 1695 u8 packet_reformat_id[0x20]; 1696 1697 u8 reserved_at_60[0x20]; 1698 }; 1699 1700 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits { 1701 struct mlx5_ifc_extended_dest_format_bits extended_dest_format; 1702 struct mlx5_ifc_flow_counter_list_bits flow_counter_list; 1703 }; 1704 1705 struct mlx5_ifc_fte_match_param_bits { 1706 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers; 1707 1708 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters; 1709 1710 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers; 1711 1712 struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2; 1713 1714 struct mlx5_ifc_fte_match_set_misc3_bits misc_parameters_3; 1715 1716 struct mlx5_ifc_fte_match_set_misc4_bits misc_parameters_4; 1717 1718 u8 reserved_at_c00[0x400]; 1719 }; 1720 1721 enum { 1722 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0, 1723 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1, 1724 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2, 1725 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3, 1726 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4, 1727 }; 1728 1729 struct mlx5_ifc_rx_hash_field_select_bits { 1730 u8 l3_prot_type[0x1]; 1731 u8 l4_prot_type[0x1]; 1732 u8 selected_fields[0x1e]; 1733 }; 1734 1735 enum { 1736 MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0, 1737 MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1, 1738 }; 1739 1740 enum { 1741 MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0, 1742 MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1, 1743 }; 1744 1745 struct mlx5_ifc_wq_bits { 1746 u8 wq_type[0x4]; 1747 u8 wq_signature[0x1]; 1748 u8 end_padding_mode[0x2]; 1749 u8 cd_slave[0x1]; 1750 u8 reserved_at_8[0x18]; 1751 1752 u8 hds_skip_first_sge[0x1]; 1753 u8 log2_hds_buf_size[0x3]; 1754 u8 reserved_at_24[0x7]; 1755 u8 page_offset[0x5]; 1756 u8 lwm[0x10]; 1757 1758 u8 reserved_at_40[0x8]; 1759 u8 pd[0x18]; 1760 1761 u8 reserved_at_60[0x8]; 1762 u8 uar_page[0x18]; 1763 1764 u8 dbr_addr[0x40]; 1765 1766 u8 hw_counter[0x20]; 1767 1768 u8 sw_counter[0x20]; 1769 1770 u8 reserved_at_100[0xc]; 1771 u8 log_wq_stride[0x4]; 1772 u8 reserved_at_110[0x3]; 1773 u8 log_wq_pg_sz[0x5]; 1774 u8 reserved_at_118[0x3]; 1775 u8 log_wq_sz[0x5]; 1776 1777 u8 dbr_umem_valid[0x1]; 1778 u8 wq_umem_valid[0x1]; 1779 u8 reserved_at_122[0x1]; 1780 u8 log_hairpin_num_packets[0x5]; 1781 u8 reserved_at_128[0x3]; 1782 u8 log_hairpin_data_sz[0x5]; 1783 1784 u8 reserved_at_130[0x4]; 1785 u8 log_wqe_num_of_strides[0x4]; 1786 u8 two_byte_shift_en[0x1]; 1787 u8 reserved_at_139[0x4]; 1788 u8 log_wqe_stride_size[0x3]; 1789 1790 u8 reserved_at_140[0x4c0]; 1791 1792 struct mlx5_ifc_cmd_pas_bits pas[]; 1793 }; 1794 1795 struct mlx5_ifc_rq_num_bits { 1796 u8 reserved_at_0[0x8]; 1797 u8 rq_num[0x18]; 1798 }; 1799 1800 struct mlx5_ifc_mac_address_layout_bits { 1801 u8 reserved_at_0[0x10]; 1802 u8 mac_addr_47_32[0x10]; 1803 1804 u8 mac_addr_31_0[0x20]; 1805 }; 1806 1807 struct mlx5_ifc_vlan_layout_bits { 1808 u8 reserved_at_0[0x14]; 1809 u8 vlan[0x0c]; 1810 1811 u8 reserved_at_20[0x20]; 1812 }; 1813 1814 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits { 1815 u8 reserved_at_0[0xa0]; 1816 1817 u8 min_time_between_cnps[0x20]; 1818 1819 u8 reserved_at_c0[0x12]; 1820 u8 cnp_dscp[0x6]; 1821 u8 reserved_at_d8[0x4]; 1822 u8 cnp_prio_mode[0x1]; 1823 u8 cnp_802p_prio[0x3]; 1824 1825 u8 reserved_at_e0[0x720]; 1826 }; 1827 1828 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits { 1829 u8 reserved_at_0[0x60]; 1830 1831 u8 reserved_at_60[0x4]; 1832 u8 clamp_tgt_rate[0x1]; 1833 u8 reserved_at_65[0x3]; 1834 u8 clamp_tgt_rate_after_time_inc[0x1]; 1835 u8 reserved_at_69[0x17]; 1836 1837 u8 reserved_at_80[0x20]; 1838 1839 u8 rpg_time_reset[0x20]; 1840 1841 u8 rpg_byte_reset[0x20]; 1842 1843 u8 rpg_threshold[0x20]; 1844 1845 u8 rpg_max_rate[0x20]; 1846 1847 u8 rpg_ai_rate[0x20]; 1848 1849 u8 rpg_hai_rate[0x20]; 1850 1851 u8 rpg_gd[0x20]; 1852 1853 u8 rpg_min_dec_fac[0x20]; 1854 1855 u8 rpg_min_rate[0x20]; 1856 1857 u8 reserved_at_1c0[0xe0]; 1858 1859 u8 rate_to_set_on_first_cnp[0x20]; 1860 1861 u8 dce_tcp_g[0x20]; 1862 1863 u8 dce_tcp_rtt[0x20]; 1864 1865 u8 rate_reduce_monitor_period[0x20]; 1866 1867 u8 reserved_at_320[0x20]; 1868 1869 u8 initial_alpha_value[0x20]; 1870 1871 u8 reserved_at_360[0x4a0]; 1872 }; 1873 1874 struct mlx5_ifc_cong_control_802_1qau_rp_bits { 1875 u8 reserved_at_0[0x80]; 1876 1877 u8 rppp_max_rps[0x20]; 1878 1879 u8 rpg_time_reset[0x20]; 1880 1881 u8 rpg_byte_reset[0x20]; 1882 1883 u8 rpg_threshold[0x20]; 1884 1885 u8 rpg_max_rate[0x20]; 1886 1887 u8 rpg_ai_rate[0x20]; 1888 1889 u8 rpg_hai_rate[0x20]; 1890 1891 u8 rpg_gd[0x20]; 1892 1893 u8 rpg_min_dec_fac[0x20]; 1894 1895 u8 rpg_min_rate[0x20]; 1896 1897 u8 reserved_at_1c0[0x640]; 1898 }; 1899 1900 enum { 1901 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1, 1902 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2, 1903 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4, 1904 }; 1905 1906 struct mlx5_ifc_resize_field_select_bits { 1907 u8 resize_field_select[0x20]; 1908 }; 1909 1910 struct mlx5_ifc_resource_dump_bits { 1911 u8 more_dump[0x1]; 1912 u8 inline_dump[0x1]; 1913 u8 reserved_at_2[0xa]; 1914 u8 seq_num[0x4]; 1915 u8 segment_type[0x10]; 1916 1917 u8 reserved_at_20[0x10]; 1918 u8 vhca_id[0x10]; 1919 1920 u8 index1[0x20]; 1921 1922 u8 index2[0x20]; 1923 1924 u8 num_of_obj1[0x10]; 1925 u8 num_of_obj2[0x10]; 1926 1927 u8 reserved_at_a0[0x20]; 1928 1929 u8 device_opaque[0x40]; 1930 1931 u8 mkey[0x20]; 1932 1933 u8 size[0x20]; 1934 1935 u8 address[0x40]; 1936 1937 u8 inline_data[52][0x20]; 1938 }; 1939 1940 struct mlx5_ifc_resource_dump_menu_record_bits { 1941 u8 reserved_at_0[0x4]; 1942 u8 num_of_obj2_supports_active[0x1]; 1943 u8 num_of_obj2_supports_all[0x1]; 1944 u8 must_have_num_of_obj2[0x1]; 1945 u8 support_num_of_obj2[0x1]; 1946 u8 num_of_obj1_supports_active[0x1]; 1947 u8 num_of_obj1_supports_all[0x1]; 1948 u8 must_have_num_of_obj1[0x1]; 1949 u8 support_num_of_obj1[0x1]; 1950 u8 must_have_index2[0x1]; 1951 u8 support_index2[0x1]; 1952 u8 must_have_index1[0x1]; 1953 u8 support_index1[0x1]; 1954 u8 segment_type[0x10]; 1955 1956 u8 segment_name[4][0x20]; 1957 1958 u8 index1_name[4][0x20]; 1959 1960 u8 index2_name[4][0x20]; 1961 }; 1962 1963 struct mlx5_ifc_resource_dump_segment_header_bits { 1964 u8 length_dw[0x10]; 1965 u8 segment_type[0x10]; 1966 }; 1967 1968 struct mlx5_ifc_resource_dump_command_segment_bits { 1969 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 1970 1971 u8 segment_called[0x10]; 1972 u8 vhca_id[0x10]; 1973 1974 u8 index1[0x20]; 1975 1976 u8 index2[0x20]; 1977 1978 u8 num_of_obj1[0x10]; 1979 u8 num_of_obj2[0x10]; 1980 }; 1981 1982 struct mlx5_ifc_resource_dump_error_segment_bits { 1983 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 1984 1985 u8 reserved_at_20[0x10]; 1986 u8 syndrome_id[0x10]; 1987 1988 u8 reserved_at_40[0x40]; 1989 1990 u8 error[8][0x20]; 1991 }; 1992 1993 struct mlx5_ifc_resource_dump_info_segment_bits { 1994 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 1995 1996 u8 reserved_at_20[0x18]; 1997 u8 dump_version[0x8]; 1998 1999 u8 hw_version[0x20]; 2000 2001 u8 fw_version[0x20]; 2002 }; 2003 2004 struct mlx5_ifc_resource_dump_menu_segment_bits { 2005 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2006 2007 u8 reserved_at_20[0x10]; 2008 u8 num_of_records[0x10]; 2009 2010 struct mlx5_ifc_resource_dump_menu_record_bits record[]; 2011 }; 2012 2013 struct mlx5_ifc_resource_dump_resource_segment_bits { 2014 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2015 2016 u8 reserved_at_20[0x20]; 2017 2018 u8 index1[0x20]; 2019 2020 u8 index2[0x20]; 2021 2022 u8 payload[][0x20]; 2023 }; 2024 2025 struct mlx5_ifc_resource_dump_terminate_segment_bits { 2026 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2027 }; 2028 2029 struct mlx5_ifc_menu_resource_dump_response_bits { 2030 struct mlx5_ifc_resource_dump_info_segment_bits info; 2031 struct mlx5_ifc_resource_dump_command_segment_bits cmd; 2032 struct mlx5_ifc_resource_dump_menu_segment_bits menu; 2033 struct mlx5_ifc_resource_dump_terminate_segment_bits terminate; 2034 }; 2035 2036 enum { 2037 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1, 2038 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2, 2039 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4, 2040 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8, 2041 }; 2042 2043 struct mlx5_ifc_modify_field_select_bits { 2044 u8 modify_field_select[0x20]; 2045 }; 2046 2047 struct mlx5_ifc_field_select_r_roce_np_bits { 2048 u8 field_select_r_roce_np[0x20]; 2049 }; 2050 2051 struct mlx5_ifc_field_select_r_roce_rp_bits { 2052 u8 field_select_r_roce_rp[0x20]; 2053 }; 2054 2055 enum { 2056 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4, 2057 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8, 2058 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10, 2059 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20, 2060 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40, 2061 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80, 2062 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100, 2063 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200, 2064 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400, 2065 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800, 2066 }; 2067 2068 struct mlx5_ifc_field_select_802_1qau_rp_bits { 2069 u8 field_select_8021qaurp[0x20]; 2070 }; 2071 2072 struct mlx5_ifc_phys_layer_cntrs_bits { 2073 u8 time_since_last_clear_high[0x20]; 2074 2075 u8 time_since_last_clear_low[0x20]; 2076 2077 u8 symbol_errors_high[0x20]; 2078 2079 u8 symbol_errors_low[0x20]; 2080 2081 u8 sync_headers_errors_high[0x20]; 2082 2083 u8 sync_headers_errors_low[0x20]; 2084 2085 u8 edpl_bip_errors_lane0_high[0x20]; 2086 2087 u8 edpl_bip_errors_lane0_low[0x20]; 2088 2089 u8 edpl_bip_errors_lane1_high[0x20]; 2090 2091 u8 edpl_bip_errors_lane1_low[0x20]; 2092 2093 u8 edpl_bip_errors_lane2_high[0x20]; 2094 2095 u8 edpl_bip_errors_lane2_low[0x20]; 2096 2097 u8 edpl_bip_errors_lane3_high[0x20]; 2098 2099 u8 edpl_bip_errors_lane3_low[0x20]; 2100 2101 u8 fc_fec_corrected_blocks_lane0_high[0x20]; 2102 2103 u8 fc_fec_corrected_blocks_lane0_low[0x20]; 2104 2105 u8 fc_fec_corrected_blocks_lane1_high[0x20]; 2106 2107 u8 fc_fec_corrected_blocks_lane1_low[0x20]; 2108 2109 u8 fc_fec_corrected_blocks_lane2_high[0x20]; 2110 2111 u8 fc_fec_corrected_blocks_lane2_low[0x20]; 2112 2113 u8 fc_fec_corrected_blocks_lane3_high[0x20]; 2114 2115 u8 fc_fec_corrected_blocks_lane3_low[0x20]; 2116 2117 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20]; 2118 2119 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20]; 2120 2121 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20]; 2122 2123 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20]; 2124 2125 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20]; 2126 2127 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20]; 2128 2129 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20]; 2130 2131 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20]; 2132 2133 u8 rs_fec_corrected_blocks_high[0x20]; 2134 2135 u8 rs_fec_corrected_blocks_low[0x20]; 2136 2137 u8 rs_fec_uncorrectable_blocks_high[0x20]; 2138 2139 u8 rs_fec_uncorrectable_blocks_low[0x20]; 2140 2141 u8 rs_fec_no_errors_blocks_high[0x20]; 2142 2143 u8 rs_fec_no_errors_blocks_low[0x20]; 2144 2145 u8 rs_fec_single_error_blocks_high[0x20]; 2146 2147 u8 rs_fec_single_error_blocks_low[0x20]; 2148 2149 u8 rs_fec_corrected_symbols_total_high[0x20]; 2150 2151 u8 rs_fec_corrected_symbols_total_low[0x20]; 2152 2153 u8 rs_fec_corrected_symbols_lane0_high[0x20]; 2154 2155 u8 rs_fec_corrected_symbols_lane0_low[0x20]; 2156 2157 u8 rs_fec_corrected_symbols_lane1_high[0x20]; 2158 2159 u8 rs_fec_corrected_symbols_lane1_low[0x20]; 2160 2161 u8 rs_fec_corrected_symbols_lane2_high[0x20]; 2162 2163 u8 rs_fec_corrected_symbols_lane2_low[0x20]; 2164 2165 u8 rs_fec_corrected_symbols_lane3_high[0x20]; 2166 2167 u8 rs_fec_corrected_symbols_lane3_low[0x20]; 2168 2169 u8 link_down_events[0x20]; 2170 2171 u8 successful_recovery_events[0x20]; 2172 2173 u8 reserved_at_640[0x180]; 2174 }; 2175 2176 struct mlx5_ifc_phys_layer_statistical_cntrs_bits { 2177 u8 time_since_last_clear_high[0x20]; 2178 2179 u8 time_since_last_clear_low[0x20]; 2180 2181 u8 phy_received_bits_high[0x20]; 2182 2183 u8 phy_received_bits_low[0x20]; 2184 2185 u8 phy_symbol_errors_high[0x20]; 2186 2187 u8 phy_symbol_errors_low[0x20]; 2188 2189 u8 phy_corrected_bits_high[0x20]; 2190 2191 u8 phy_corrected_bits_low[0x20]; 2192 2193 u8 phy_corrected_bits_lane0_high[0x20]; 2194 2195 u8 phy_corrected_bits_lane0_low[0x20]; 2196 2197 u8 phy_corrected_bits_lane1_high[0x20]; 2198 2199 u8 phy_corrected_bits_lane1_low[0x20]; 2200 2201 u8 phy_corrected_bits_lane2_high[0x20]; 2202 2203 u8 phy_corrected_bits_lane2_low[0x20]; 2204 2205 u8 phy_corrected_bits_lane3_high[0x20]; 2206 2207 u8 phy_corrected_bits_lane3_low[0x20]; 2208 2209 u8 reserved_at_200[0x5c0]; 2210 }; 2211 2212 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits { 2213 u8 symbol_error_counter[0x10]; 2214 2215 u8 link_error_recovery_counter[0x8]; 2216 2217 u8 link_downed_counter[0x8]; 2218 2219 u8 port_rcv_errors[0x10]; 2220 2221 u8 port_rcv_remote_physical_errors[0x10]; 2222 2223 u8 port_rcv_switch_relay_errors[0x10]; 2224 2225 u8 port_xmit_discards[0x10]; 2226 2227 u8 port_xmit_constraint_errors[0x8]; 2228 2229 u8 port_rcv_constraint_errors[0x8]; 2230 2231 u8 reserved_at_70[0x8]; 2232 2233 u8 link_overrun_errors[0x8]; 2234 2235 u8 reserved_at_80[0x10]; 2236 2237 u8 vl_15_dropped[0x10]; 2238 2239 u8 reserved_at_a0[0x80]; 2240 2241 u8 port_xmit_wait[0x20]; 2242 }; 2243 2244 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits { 2245 u8 transmit_queue_high[0x20]; 2246 2247 u8 transmit_queue_low[0x20]; 2248 2249 u8 no_buffer_discard_uc_high[0x20]; 2250 2251 u8 no_buffer_discard_uc_low[0x20]; 2252 2253 u8 reserved_at_80[0x740]; 2254 }; 2255 2256 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits { 2257 u8 wred_discard_high[0x20]; 2258 2259 u8 wred_discard_low[0x20]; 2260 2261 u8 ecn_marked_tc_high[0x20]; 2262 2263 u8 ecn_marked_tc_low[0x20]; 2264 2265 u8 reserved_at_80[0x740]; 2266 }; 2267 2268 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits { 2269 u8 rx_octets_high[0x20]; 2270 2271 u8 rx_octets_low[0x20]; 2272 2273 u8 reserved_at_40[0xc0]; 2274 2275 u8 rx_frames_high[0x20]; 2276 2277 u8 rx_frames_low[0x20]; 2278 2279 u8 tx_octets_high[0x20]; 2280 2281 u8 tx_octets_low[0x20]; 2282 2283 u8 reserved_at_180[0xc0]; 2284 2285 u8 tx_frames_high[0x20]; 2286 2287 u8 tx_frames_low[0x20]; 2288 2289 u8 rx_pause_high[0x20]; 2290 2291 u8 rx_pause_low[0x20]; 2292 2293 u8 rx_pause_duration_high[0x20]; 2294 2295 u8 rx_pause_duration_low[0x20]; 2296 2297 u8 tx_pause_high[0x20]; 2298 2299 u8 tx_pause_low[0x20]; 2300 2301 u8 tx_pause_duration_high[0x20]; 2302 2303 u8 tx_pause_duration_low[0x20]; 2304 2305 u8 rx_pause_transition_high[0x20]; 2306 2307 u8 rx_pause_transition_low[0x20]; 2308 2309 u8 rx_discards_high[0x20]; 2310 2311 u8 rx_discards_low[0x20]; 2312 2313 u8 device_stall_minor_watermark_cnt_high[0x20]; 2314 2315 u8 device_stall_minor_watermark_cnt_low[0x20]; 2316 2317 u8 device_stall_critical_watermark_cnt_high[0x20]; 2318 2319 u8 device_stall_critical_watermark_cnt_low[0x20]; 2320 2321 u8 reserved_at_480[0x340]; 2322 }; 2323 2324 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits { 2325 u8 port_transmit_wait_high[0x20]; 2326 2327 u8 port_transmit_wait_low[0x20]; 2328 2329 u8 reserved_at_40[0x100]; 2330 2331 u8 rx_buffer_almost_full_high[0x20]; 2332 2333 u8 rx_buffer_almost_full_low[0x20]; 2334 2335 u8 rx_buffer_full_high[0x20]; 2336 2337 u8 rx_buffer_full_low[0x20]; 2338 2339 u8 rx_icrc_encapsulated_high[0x20]; 2340 2341 u8 rx_icrc_encapsulated_low[0x20]; 2342 2343 u8 reserved_at_200[0x5c0]; 2344 }; 2345 2346 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits { 2347 u8 dot3stats_alignment_errors_high[0x20]; 2348 2349 u8 dot3stats_alignment_errors_low[0x20]; 2350 2351 u8 dot3stats_fcs_errors_high[0x20]; 2352 2353 u8 dot3stats_fcs_errors_low[0x20]; 2354 2355 u8 dot3stats_single_collision_frames_high[0x20]; 2356 2357 u8 dot3stats_single_collision_frames_low[0x20]; 2358 2359 u8 dot3stats_multiple_collision_frames_high[0x20]; 2360 2361 u8 dot3stats_multiple_collision_frames_low[0x20]; 2362 2363 u8 dot3stats_sqe_test_errors_high[0x20]; 2364 2365 u8 dot3stats_sqe_test_errors_low[0x20]; 2366 2367 u8 dot3stats_deferred_transmissions_high[0x20]; 2368 2369 u8 dot3stats_deferred_transmissions_low[0x20]; 2370 2371 u8 dot3stats_late_collisions_high[0x20]; 2372 2373 u8 dot3stats_late_collisions_low[0x20]; 2374 2375 u8 dot3stats_excessive_collisions_high[0x20]; 2376 2377 u8 dot3stats_excessive_collisions_low[0x20]; 2378 2379 u8 dot3stats_internal_mac_transmit_errors_high[0x20]; 2380 2381 u8 dot3stats_internal_mac_transmit_errors_low[0x20]; 2382 2383 u8 dot3stats_carrier_sense_errors_high[0x20]; 2384 2385 u8 dot3stats_carrier_sense_errors_low[0x20]; 2386 2387 u8 dot3stats_frame_too_longs_high[0x20]; 2388 2389 u8 dot3stats_frame_too_longs_low[0x20]; 2390 2391 u8 dot3stats_internal_mac_receive_errors_high[0x20]; 2392 2393 u8 dot3stats_internal_mac_receive_errors_low[0x20]; 2394 2395 u8 dot3stats_symbol_errors_high[0x20]; 2396 2397 u8 dot3stats_symbol_errors_low[0x20]; 2398 2399 u8 dot3control_in_unknown_opcodes_high[0x20]; 2400 2401 u8 dot3control_in_unknown_opcodes_low[0x20]; 2402 2403 u8 dot3in_pause_frames_high[0x20]; 2404 2405 u8 dot3in_pause_frames_low[0x20]; 2406 2407 u8 dot3out_pause_frames_high[0x20]; 2408 2409 u8 dot3out_pause_frames_low[0x20]; 2410 2411 u8 reserved_at_400[0x3c0]; 2412 }; 2413 2414 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits { 2415 u8 ether_stats_drop_events_high[0x20]; 2416 2417 u8 ether_stats_drop_events_low[0x20]; 2418 2419 u8 ether_stats_octets_high[0x20]; 2420 2421 u8 ether_stats_octets_low[0x20]; 2422 2423 u8 ether_stats_pkts_high[0x20]; 2424 2425 u8 ether_stats_pkts_low[0x20]; 2426 2427 u8 ether_stats_broadcast_pkts_high[0x20]; 2428 2429 u8 ether_stats_broadcast_pkts_low[0x20]; 2430 2431 u8 ether_stats_multicast_pkts_high[0x20]; 2432 2433 u8 ether_stats_multicast_pkts_low[0x20]; 2434 2435 u8 ether_stats_crc_align_errors_high[0x20]; 2436 2437 u8 ether_stats_crc_align_errors_low[0x20]; 2438 2439 u8 ether_stats_undersize_pkts_high[0x20]; 2440 2441 u8 ether_stats_undersize_pkts_low[0x20]; 2442 2443 u8 ether_stats_oversize_pkts_high[0x20]; 2444 2445 u8 ether_stats_oversize_pkts_low[0x20]; 2446 2447 u8 ether_stats_fragments_high[0x20]; 2448 2449 u8 ether_stats_fragments_low[0x20]; 2450 2451 u8 ether_stats_jabbers_high[0x20]; 2452 2453 u8 ether_stats_jabbers_low[0x20]; 2454 2455 u8 ether_stats_collisions_high[0x20]; 2456 2457 u8 ether_stats_collisions_low[0x20]; 2458 2459 u8 ether_stats_pkts64octets_high[0x20]; 2460 2461 u8 ether_stats_pkts64octets_low[0x20]; 2462 2463 u8 ether_stats_pkts65to127octets_high[0x20]; 2464 2465 u8 ether_stats_pkts65to127octets_low[0x20]; 2466 2467 u8 ether_stats_pkts128to255octets_high[0x20]; 2468 2469 u8 ether_stats_pkts128to255octets_low[0x20]; 2470 2471 u8 ether_stats_pkts256to511octets_high[0x20]; 2472 2473 u8 ether_stats_pkts256to511octets_low[0x20]; 2474 2475 u8 ether_stats_pkts512to1023octets_high[0x20]; 2476 2477 u8 ether_stats_pkts512to1023octets_low[0x20]; 2478 2479 u8 ether_stats_pkts1024to1518octets_high[0x20]; 2480 2481 u8 ether_stats_pkts1024to1518octets_low[0x20]; 2482 2483 u8 ether_stats_pkts1519to2047octets_high[0x20]; 2484 2485 u8 ether_stats_pkts1519to2047octets_low[0x20]; 2486 2487 u8 ether_stats_pkts2048to4095octets_high[0x20]; 2488 2489 u8 ether_stats_pkts2048to4095octets_low[0x20]; 2490 2491 u8 ether_stats_pkts4096to8191octets_high[0x20]; 2492 2493 u8 ether_stats_pkts4096to8191octets_low[0x20]; 2494 2495 u8 ether_stats_pkts8192to10239octets_high[0x20]; 2496 2497 u8 ether_stats_pkts8192to10239octets_low[0x20]; 2498 2499 u8 reserved_at_540[0x280]; 2500 }; 2501 2502 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits { 2503 u8 if_in_octets_high[0x20]; 2504 2505 u8 if_in_octets_low[0x20]; 2506 2507 u8 if_in_ucast_pkts_high[0x20]; 2508 2509 u8 if_in_ucast_pkts_low[0x20]; 2510 2511 u8 if_in_discards_high[0x20]; 2512 2513 u8 if_in_discards_low[0x20]; 2514 2515 u8 if_in_errors_high[0x20]; 2516 2517 u8 if_in_errors_low[0x20]; 2518 2519 u8 if_in_unknown_protos_high[0x20]; 2520 2521 u8 if_in_unknown_protos_low[0x20]; 2522 2523 u8 if_out_octets_high[0x20]; 2524 2525 u8 if_out_octets_low[0x20]; 2526 2527 u8 if_out_ucast_pkts_high[0x20]; 2528 2529 u8 if_out_ucast_pkts_low[0x20]; 2530 2531 u8 if_out_discards_high[0x20]; 2532 2533 u8 if_out_discards_low[0x20]; 2534 2535 u8 if_out_errors_high[0x20]; 2536 2537 u8 if_out_errors_low[0x20]; 2538 2539 u8 if_in_multicast_pkts_high[0x20]; 2540 2541 u8 if_in_multicast_pkts_low[0x20]; 2542 2543 u8 if_in_broadcast_pkts_high[0x20]; 2544 2545 u8 if_in_broadcast_pkts_low[0x20]; 2546 2547 u8 if_out_multicast_pkts_high[0x20]; 2548 2549 u8 if_out_multicast_pkts_low[0x20]; 2550 2551 u8 if_out_broadcast_pkts_high[0x20]; 2552 2553 u8 if_out_broadcast_pkts_low[0x20]; 2554 2555 u8 reserved_at_340[0x480]; 2556 }; 2557 2558 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits { 2559 u8 a_frames_transmitted_ok_high[0x20]; 2560 2561 u8 a_frames_transmitted_ok_low[0x20]; 2562 2563 u8 a_frames_received_ok_high[0x20]; 2564 2565 u8 a_frames_received_ok_low[0x20]; 2566 2567 u8 a_frame_check_sequence_errors_high[0x20]; 2568 2569 u8 a_frame_check_sequence_errors_low[0x20]; 2570 2571 u8 a_alignment_errors_high[0x20]; 2572 2573 u8 a_alignment_errors_low[0x20]; 2574 2575 u8 a_octets_transmitted_ok_high[0x20]; 2576 2577 u8 a_octets_transmitted_ok_low[0x20]; 2578 2579 u8 a_octets_received_ok_high[0x20]; 2580 2581 u8 a_octets_received_ok_low[0x20]; 2582 2583 u8 a_multicast_frames_xmitted_ok_high[0x20]; 2584 2585 u8 a_multicast_frames_xmitted_ok_low[0x20]; 2586 2587 u8 a_broadcast_frames_xmitted_ok_high[0x20]; 2588 2589 u8 a_broadcast_frames_xmitted_ok_low[0x20]; 2590 2591 u8 a_multicast_frames_received_ok_high[0x20]; 2592 2593 u8 a_multicast_frames_received_ok_low[0x20]; 2594 2595 u8 a_broadcast_frames_received_ok_high[0x20]; 2596 2597 u8 a_broadcast_frames_received_ok_low[0x20]; 2598 2599 u8 a_in_range_length_errors_high[0x20]; 2600 2601 u8 a_in_range_length_errors_low[0x20]; 2602 2603 u8 a_out_of_range_length_field_high[0x20]; 2604 2605 u8 a_out_of_range_length_field_low[0x20]; 2606 2607 u8 a_frame_too_long_errors_high[0x20]; 2608 2609 u8 a_frame_too_long_errors_low[0x20]; 2610 2611 u8 a_symbol_error_during_carrier_high[0x20]; 2612 2613 u8 a_symbol_error_during_carrier_low[0x20]; 2614 2615 u8 a_mac_control_frames_transmitted_high[0x20]; 2616 2617 u8 a_mac_control_frames_transmitted_low[0x20]; 2618 2619 u8 a_mac_control_frames_received_high[0x20]; 2620 2621 u8 a_mac_control_frames_received_low[0x20]; 2622 2623 u8 a_unsupported_opcodes_received_high[0x20]; 2624 2625 u8 a_unsupported_opcodes_received_low[0x20]; 2626 2627 u8 a_pause_mac_ctrl_frames_received_high[0x20]; 2628 2629 u8 a_pause_mac_ctrl_frames_received_low[0x20]; 2630 2631 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20]; 2632 2633 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20]; 2634 2635 u8 reserved_at_4c0[0x300]; 2636 }; 2637 2638 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits { 2639 u8 life_time_counter_high[0x20]; 2640 2641 u8 life_time_counter_low[0x20]; 2642 2643 u8 rx_errors[0x20]; 2644 2645 u8 tx_errors[0x20]; 2646 2647 u8 l0_to_recovery_eieos[0x20]; 2648 2649 u8 l0_to_recovery_ts[0x20]; 2650 2651 u8 l0_to_recovery_framing[0x20]; 2652 2653 u8 l0_to_recovery_retrain[0x20]; 2654 2655 u8 crc_error_dllp[0x20]; 2656 2657 u8 crc_error_tlp[0x20]; 2658 2659 u8 tx_overflow_buffer_pkt_high[0x20]; 2660 2661 u8 tx_overflow_buffer_pkt_low[0x20]; 2662 2663 u8 outbound_stalled_reads[0x20]; 2664 2665 u8 outbound_stalled_writes[0x20]; 2666 2667 u8 outbound_stalled_reads_events[0x20]; 2668 2669 u8 outbound_stalled_writes_events[0x20]; 2670 2671 u8 reserved_at_200[0x5c0]; 2672 }; 2673 2674 struct mlx5_ifc_cmd_inter_comp_event_bits { 2675 u8 command_completion_vector[0x20]; 2676 2677 u8 reserved_at_20[0xc0]; 2678 }; 2679 2680 struct mlx5_ifc_stall_vl_event_bits { 2681 u8 reserved_at_0[0x18]; 2682 u8 port_num[0x1]; 2683 u8 reserved_at_19[0x3]; 2684 u8 vl[0x4]; 2685 2686 u8 reserved_at_20[0xa0]; 2687 }; 2688 2689 struct mlx5_ifc_db_bf_congestion_event_bits { 2690 u8 event_subtype[0x8]; 2691 u8 reserved_at_8[0x8]; 2692 u8 congestion_level[0x8]; 2693 u8 reserved_at_18[0x8]; 2694 2695 u8 reserved_at_20[0xa0]; 2696 }; 2697 2698 struct mlx5_ifc_gpio_event_bits { 2699 u8 reserved_at_0[0x60]; 2700 2701 u8 gpio_event_hi[0x20]; 2702 2703 u8 gpio_event_lo[0x20]; 2704 2705 u8 reserved_at_a0[0x40]; 2706 }; 2707 2708 struct mlx5_ifc_port_state_change_event_bits { 2709 u8 reserved_at_0[0x40]; 2710 2711 u8 port_num[0x4]; 2712 u8 reserved_at_44[0x1c]; 2713 2714 u8 reserved_at_60[0x80]; 2715 }; 2716 2717 struct mlx5_ifc_dropped_packet_logged_bits { 2718 u8 reserved_at_0[0xe0]; 2719 }; 2720 2721 enum { 2722 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1, 2723 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2, 2724 }; 2725 2726 struct mlx5_ifc_cq_error_bits { 2727 u8 reserved_at_0[0x8]; 2728 u8 cqn[0x18]; 2729 2730 u8 reserved_at_20[0x20]; 2731 2732 u8 reserved_at_40[0x18]; 2733 u8 syndrome[0x8]; 2734 2735 u8 reserved_at_60[0x80]; 2736 }; 2737 2738 struct mlx5_ifc_rdma_page_fault_event_bits { 2739 u8 bytes_committed[0x20]; 2740 2741 u8 r_key[0x20]; 2742 2743 u8 reserved_at_40[0x10]; 2744 u8 packet_len[0x10]; 2745 2746 u8 rdma_op_len[0x20]; 2747 2748 u8 rdma_va[0x40]; 2749 2750 u8 reserved_at_c0[0x5]; 2751 u8 rdma[0x1]; 2752 u8 write[0x1]; 2753 u8 requestor[0x1]; 2754 u8 qp_number[0x18]; 2755 }; 2756 2757 struct mlx5_ifc_wqe_associated_page_fault_event_bits { 2758 u8 bytes_committed[0x20]; 2759 2760 u8 reserved_at_20[0x10]; 2761 u8 wqe_index[0x10]; 2762 2763 u8 reserved_at_40[0x10]; 2764 u8 len[0x10]; 2765 2766 u8 reserved_at_60[0x60]; 2767 2768 u8 reserved_at_c0[0x5]; 2769 u8 rdma[0x1]; 2770 u8 write_read[0x1]; 2771 u8 requestor[0x1]; 2772 u8 qpn[0x18]; 2773 }; 2774 2775 struct mlx5_ifc_qp_events_bits { 2776 u8 reserved_at_0[0xa0]; 2777 2778 u8 type[0x8]; 2779 u8 reserved_at_a8[0x18]; 2780 2781 u8 reserved_at_c0[0x8]; 2782 u8 qpn_rqn_sqn[0x18]; 2783 }; 2784 2785 struct mlx5_ifc_dct_events_bits { 2786 u8 reserved_at_0[0xc0]; 2787 2788 u8 reserved_at_c0[0x8]; 2789 u8 dct_number[0x18]; 2790 }; 2791 2792 struct mlx5_ifc_comp_event_bits { 2793 u8 reserved_at_0[0xc0]; 2794 2795 u8 reserved_at_c0[0x8]; 2796 u8 cq_number[0x18]; 2797 }; 2798 2799 enum { 2800 MLX5_QPC_STATE_RST = 0x0, 2801 MLX5_QPC_STATE_INIT = 0x1, 2802 MLX5_QPC_STATE_RTR = 0x2, 2803 MLX5_QPC_STATE_RTS = 0x3, 2804 MLX5_QPC_STATE_SQER = 0x4, 2805 MLX5_QPC_STATE_ERR = 0x6, 2806 MLX5_QPC_STATE_SQD = 0x7, 2807 MLX5_QPC_STATE_SUSPENDED = 0x9, 2808 }; 2809 2810 enum { 2811 MLX5_QPC_ST_RC = 0x0, 2812 MLX5_QPC_ST_UC = 0x1, 2813 MLX5_QPC_ST_UD = 0x2, 2814 MLX5_QPC_ST_XRC = 0x3, 2815 MLX5_QPC_ST_DCI = 0x5, 2816 MLX5_QPC_ST_QP0 = 0x7, 2817 MLX5_QPC_ST_QP1 = 0x8, 2818 MLX5_QPC_ST_RAW_DATAGRAM = 0x9, 2819 MLX5_QPC_ST_REG_UMR = 0xc, 2820 }; 2821 2822 enum { 2823 MLX5_QPC_PM_STATE_ARMED = 0x0, 2824 MLX5_QPC_PM_STATE_REARM = 0x1, 2825 MLX5_QPC_PM_STATE_RESERVED = 0x2, 2826 MLX5_QPC_PM_STATE_MIGRATED = 0x3, 2827 }; 2828 2829 enum { 2830 MLX5_QPC_OFFLOAD_TYPE_RNDV = 0x1, 2831 }; 2832 2833 enum { 2834 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0, 2835 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1, 2836 }; 2837 2838 enum { 2839 MLX5_QPC_MTU_256_BYTES = 0x1, 2840 MLX5_QPC_MTU_512_BYTES = 0x2, 2841 MLX5_QPC_MTU_1K_BYTES = 0x3, 2842 MLX5_QPC_MTU_2K_BYTES = 0x4, 2843 MLX5_QPC_MTU_4K_BYTES = 0x5, 2844 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7, 2845 }; 2846 2847 enum { 2848 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1, 2849 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2, 2850 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3, 2851 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4, 2852 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5, 2853 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6, 2854 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7, 2855 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8, 2856 }; 2857 2858 enum { 2859 MLX5_QPC_CS_REQ_DISABLE = 0x0, 2860 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11, 2861 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22, 2862 }; 2863 2864 enum { 2865 MLX5_QPC_CS_RES_DISABLE = 0x0, 2866 MLX5_QPC_CS_RES_UP_TO_32B = 0x1, 2867 MLX5_QPC_CS_RES_UP_TO_64B = 0x2, 2868 }; 2869 2870 struct mlx5_ifc_qpc_bits { 2871 u8 state[0x4]; 2872 u8 lag_tx_port_affinity[0x4]; 2873 u8 st[0x8]; 2874 u8 reserved_at_10[0x3]; 2875 u8 pm_state[0x2]; 2876 u8 reserved_at_15[0x1]; 2877 u8 req_e2e_credit_mode[0x2]; 2878 u8 offload_type[0x4]; 2879 u8 end_padding_mode[0x2]; 2880 u8 reserved_at_1e[0x2]; 2881 2882 u8 wq_signature[0x1]; 2883 u8 block_lb_mc[0x1]; 2884 u8 atomic_like_write_en[0x1]; 2885 u8 latency_sensitive[0x1]; 2886 u8 reserved_at_24[0x1]; 2887 u8 drain_sigerr[0x1]; 2888 u8 reserved_at_26[0x2]; 2889 u8 pd[0x18]; 2890 2891 u8 mtu[0x3]; 2892 u8 log_msg_max[0x5]; 2893 u8 reserved_at_48[0x1]; 2894 u8 log_rq_size[0x4]; 2895 u8 log_rq_stride[0x3]; 2896 u8 no_sq[0x1]; 2897 u8 log_sq_size[0x4]; 2898 u8 reserved_at_55[0x6]; 2899 u8 rlky[0x1]; 2900 u8 ulp_stateless_offload_mode[0x4]; 2901 2902 u8 counter_set_id[0x8]; 2903 u8 uar_page[0x18]; 2904 2905 u8 reserved_at_80[0x8]; 2906 u8 user_index[0x18]; 2907 2908 u8 reserved_at_a0[0x3]; 2909 u8 log_page_size[0x5]; 2910 u8 remote_qpn[0x18]; 2911 2912 struct mlx5_ifc_ads_bits primary_address_path; 2913 2914 struct mlx5_ifc_ads_bits secondary_address_path; 2915 2916 u8 log_ack_req_freq[0x4]; 2917 u8 reserved_at_384[0x4]; 2918 u8 log_sra_max[0x3]; 2919 u8 reserved_at_38b[0x2]; 2920 u8 retry_count[0x3]; 2921 u8 rnr_retry[0x3]; 2922 u8 reserved_at_393[0x1]; 2923 u8 fre[0x1]; 2924 u8 cur_rnr_retry[0x3]; 2925 u8 cur_retry_count[0x3]; 2926 u8 reserved_at_39b[0x5]; 2927 2928 u8 reserved_at_3a0[0x20]; 2929 2930 u8 reserved_at_3c0[0x8]; 2931 u8 next_send_psn[0x18]; 2932 2933 u8 reserved_at_3e0[0x8]; 2934 u8 cqn_snd[0x18]; 2935 2936 u8 reserved_at_400[0x8]; 2937 u8 deth_sqpn[0x18]; 2938 2939 u8 reserved_at_420[0x20]; 2940 2941 u8 reserved_at_440[0x8]; 2942 u8 last_acked_psn[0x18]; 2943 2944 u8 reserved_at_460[0x8]; 2945 u8 ssn[0x18]; 2946 2947 u8 reserved_at_480[0x8]; 2948 u8 log_rra_max[0x3]; 2949 u8 reserved_at_48b[0x1]; 2950 u8 atomic_mode[0x4]; 2951 u8 rre[0x1]; 2952 u8 rwe[0x1]; 2953 u8 rae[0x1]; 2954 u8 reserved_at_493[0x1]; 2955 u8 page_offset[0x6]; 2956 u8 reserved_at_49a[0x3]; 2957 u8 cd_slave_receive[0x1]; 2958 u8 cd_slave_send[0x1]; 2959 u8 cd_master[0x1]; 2960 2961 u8 reserved_at_4a0[0x3]; 2962 u8 min_rnr_nak[0x5]; 2963 u8 next_rcv_psn[0x18]; 2964 2965 u8 reserved_at_4c0[0x8]; 2966 u8 xrcd[0x18]; 2967 2968 u8 reserved_at_4e0[0x8]; 2969 u8 cqn_rcv[0x18]; 2970 2971 u8 dbr_addr[0x40]; 2972 2973 u8 q_key[0x20]; 2974 2975 u8 reserved_at_560[0x5]; 2976 u8 rq_type[0x3]; 2977 u8 srqn_rmpn_xrqn[0x18]; 2978 2979 u8 reserved_at_580[0x8]; 2980 u8 rmsn[0x18]; 2981 2982 u8 hw_sq_wqebb_counter[0x10]; 2983 u8 sw_sq_wqebb_counter[0x10]; 2984 2985 u8 hw_rq_counter[0x20]; 2986 2987 u8 sw_rq_counter[0x20]; 2988 2989 u8 reserved_at_600[0x20]; 2990 2991 u8 reserved_at_620[0xf]; 2992 u8 cgs[0x1]; 2993 u8 cs_req[0x8]; 2994 u8 cs_res[0x8]; 2995 2996 u8 dc_access_key[0x40]; 2997 2998 u8 reserved_at_680[0x3]; 2999 u8 dbr_umem_valid[0x1]; 3000 3001 u8 reserved_at_684[0xbc]; 3002 }; 3003 3004 struct mlx5_ifc_roce_addr_layout_bits { 3005 u8 source_l3_address[16][0x8]; 3006 3007 u8 reserved_at_80[0x3]; 3008 u8 vlan_valid[0x1]; 3009 u8 vlan_id[0xc]; 3010 u8 source_mac_47_32[0x10]; 3011 3012 u8 source_mac_31_0[0x20]; 3013 3014 u8 reserved_at_c0[0x14]; 3015 u8 roce_l3_type[0x4]; 3016 u8 roce_version[0x8]; 3017 3018 u8 reserved_at_e0[0x20]; 3019 }; 3020 3021 union mlx5_ifc_hca_cap_union_bits { 3022 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap; 3023 struct mlx5_ifc_odp_cap_bits odp_cap; 3024 struct mlx5_ifc_atomic_caps_bits atomic_caps; 3025 struct mlx5_ifc_roce_cap_bits roce_cap; 3026 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps; 3027 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap; 3028 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap; 3029 struct mlx5_ifc_e_switch_cap_bits e_switch_cap; 3030 struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap; 3031 struct mlx5_ifc_qos_cap_bits qos_cap; 3032 struct mlx5_ifc_debug_cap_bits debug_cap; 3033 struct mlx5_ifc_fpga_cap_bits fpga_cap; 3034 struct mlx5_ifc_tls_cap_bits tls_cap; 3035 struct mlx5_ifc_device_mem_cap_bits device_mem_cap; 3036 struct mlx5_ifc_virtio_emulation_cap_bits virtio_emulation_cap; 3037 u8 reserved_at_0[0x8000]; 3038 }; 3039 3040 enum { 3041 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1, 3042 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2, 3043 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4, 3044 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8, 3045 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT = 0x10, 3046 MLX5_FLOW_CONTEXT_ACTION_DECAP = 0x20, 3047 MLX5_FLOW_CONTEXT_ACTION_MOD_HDR = 0x40, 3048 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP = 0x80, 3049 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100, 3050 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2 = 0x400, 3051 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2 = 0x800, 3052 MLX5_FLOW_CONTEXT_ACTION_IPSEC_DECRYPT = 0x1000, 3053 MLX5_FLOW_CONTEXT_ACTION_IPSEC_ENCRYPT = 0x2000, 3054 }; 3055 3056 enum { 3057 MLX5_FLOW_CONTEXT_FLOW_SOURCE_ANY_VPORT = 0x0, 3058 MLX5_FLOW_CONTEXT_FLOW_SOURCE_UPLINK = 0x1, 3059 MLX5_FLOW_CONTEXT_FLOW_SOURCE_LOCAL_VPORT = 0x2, 3060 }; 3061 3062 struct mlx5_ifc_vlan_bits { 3063 u8 ethtype[0x10]; 3064 u8 prio[0x3]; 3065 u8 cfi[0x1]; 3066 u8 vid[0xc]; 3067 }; 3068 3069 struct mlx5_ifc_flow_context_bits { 3070 struct mlx5_ifc_vlan_bits push_vlan; 3071 3072 u8 group_id[0x20]; 3073 3074 u8 reserved_at_40[0x8]; 3075 u8 flow_tag[0x18]; 3076 3077 u8 reserved_at_60[0x10]; 3078 u8 action[0x10]; 3079 3080 u8 extended_destination[0x1]; 3081 u8 reserved_at_81[0x1]; 3082 u8 flow_source[0x2]; 3083 u8 reserved_at_84[0x4]; 3084 u8 destination_list_size[0x18]; 3085 3086 u8 reserved_at_a0[0x8]; 3087 u8 flow_counter_list_size[0x18]; 3088 3089 u8 packet_reformat_id[0x20]; 3090 3091 u8 modify_header_id[0x20]; 3092 3093 struct mlx5_ifc_vlan_bits push_vlan_2; 3094 3095 u8 ipsec_obj_id[0x20]; 3096 u8 reserved_at_140[0xc0]; 3097 3098 struct mlx5_ifc_fte_match_param_bits match_value; 3099 3100 u8 reserved_at_1200[0x600]; 3101 3102 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[]; 3103 }; 3104 3105 enum { 3106 MLX5_XRC_SRQC_STATE_GOOD = 0x0, 3107 MLX5_XRC_SRQC_STATE_ERROR = 0x1, 3108 }; 3109 3110 struct mlx5_ifc_xrc_srqc_bits { 3111 u8 state[0x4]; 3112 u8 log_xrc_srq_size[0x4]; 3113 u8 reserved_at_8[0x18]; 3114 3115 u8 wq_signature[0x1]; 3116 u8 cont_srq[0x1]; 3117 u8 reserved_at_22[0x1]; 3118 u8 rlky[0x1]; 3119 u8 basic_cyclic_rcv_wqe[0x1]; 3120 u8 log_rq_stride[0x3]; 3121 u8 xrcd[0x18]; 3122 3123 u8 page_offset[0x6]; 3124 u8 reserved_at_46[0x1]; 3125 u8 dbr_umem_valid[0x1]; 3126 u8 cqn[0x18]; 3127 3128 u8 reserved_at_60[0x20]; 3129 3130 u8 user_index_equal_xrc_srqn[0x1]; 3131 u8 reserved_at_81[0x1]; 3132 u8 log_page_size[0x6]; 3133 u8 user_index[0x18]; 3134 3135 u8 reserved_at_a0[0x20]; 3136 3137 u8 reserved_at_c0[0x8]; 3138 u8 pd[0x18]; 3139 3140 u8 lwm[0x10]; 3141 u8 wqe_cnt[0x10]; 3142 3143 u8 reserved_at_100[0x40]; 3144 3145 u8 db_record_addr_h[0x20]; 3146 3147 u8 db_record_addr_l[0x1e]; 3148 u8 reserved_at_17e[0x2]; 3149 3150 u8 reserved_at_180[0x80]; 3151 }; 3152 3153 struct mlx5_ifc_vnic_diagnostic_statistics_bits { 3154 u8 counter_error_queues[0x20]; 3155 3156 u8 total_error_queues[0x20]; 3157 3158 u8 send_queue_priority_update_flow[0x20]; 3159 3160 u8 reserved_at_60[0x20]; 3161 3162 u8 nic_receive_steering_discard[0x40]; 3163 3164 u8 receive_discard_vport_down[0x40]; 3165 3166 u8 transmit_discard_vport_down[0x40]; 3167 3168 u8 reserved_at_140[0xa0]; 3169 3170 u8 internal_rq_out_of_buffer[0x20]; 3171 3172 u8 reserved_at_200[0xe00]; 3173 }; 3174 3175 struct mlx5_ifc_traffic_counter_bits { 3176 u8 packets[0x40]; 3177 3178 u8 octets[0x40]; 3179 }; 3180 3181 struct mlx5_ifc_tisc_bits { 3182 u8 strict_lag_tx_port_affinity[0x1]; 3183 u8 tls_en[0x1]; 3184 u8 reserved_at_2[0x2]; 3185 u8 lag_tx_port_affinity[0x04]; 3186 3187 u8 reserved_at_8[0x4]; 3188 u8 prio[0x4]; 3189 u8 reserved_at_10[0x10]; 3190 3191 u8 reserved_at_20[0x100]; 3192 3193 u8 reserved_at_120[0x8]; 3194 u8 transport_domain[0x18]; 3195 3196 u8 reserved_at_140[0x8]; 3197 u8 underlay_qpn[0x18]; 3198 3199 u8 reserved_at_160[0x8]; 3200 u8 pd[0x18]; 3201 3202 u8 reserved_at_180[0x380]; 3203 }; 3204 3205 enum { 3206 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0, 3207 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1, 3208 }; 3209 3210 enum { 3211 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO = 0x1, 3212 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO = 0x2, 3213 }; 3214 3215 enum { 3216 MLX5_RX_HASH_FN_NONE = 0x0, 3217 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1, 3218 MLX5_RX_HASH_FN_TOEPLITZ = 0x2, 3219 }; 3220 3221 enum { 3222 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST = 0x1, 3223 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST = 0x2, 3224 }; 3225 3226 struct mlx5_ifc_tirc_bits { 3227 u8 reserved_at_0[0x20]; 3228 3229 u8 disp_type[0x4]; 3230 u8 tls_en[0x1]; 3231 u8 reserved_at_25[0x1b]; 3232 3233 u8 reserved_at_40[0x40]; 3234 3235 u8 reserved_at_80[0x4]; 3236 u8 lro_timeout_period_usecs[0x10]; 3237 u8 lro_enable_mask[0x4]; 3238 u8 lro_max_ip_payload_size[0x8]; 3239 3240 u8 reserved_at_a0[0x40]; 3241 3242 u8 reserved_at_e0[0x8]; 3243 u8 inline_rqn[0x18]; 3244 3245 u8 rx_hash_symmetric[0x1]; 3246 u8 reserved_at_101[0x1]; 3247 u8 tunneled_offload_en[0x1]; 3248 u8 reserved_at_103[0x5]; 3249 u8 indirect_table[0x18]; 3250 3251 u8 rx_hash_fn[0x4]; 3252 u8 reserved_at_124[0x2]; 3253 u8 self_lb_block[0x2]; 3254 u8 transport_domain[0x18]; 3255 3256 u8 rx_hash_toeplitz_key[10][0x20]; 3257 3258 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer; 3259 3260 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner; 3261 3262 u8 reserved_at_2c0[0x4c0]; 3263 }; 3264 3265 enum { 3266 MLX5_SRQC_STATE_GOOD = 0x0, 3267 MLX5_SRQC_STATE_ERROR = 0x1, 3268 }; 3269 3270 struct mlx5_ifc_srqc_bits { 3271 u8 state[0x4]; 3272 u8 log_srq_size[0x4]; 3273 u8 reserved_at_8[0x18]; 3274 3275 u8 wq_signature[0x1]; 3276 u8 cont_srq[0x1]; 3277 u8 reserved_at_22[0x1]; 3278 u8 rlky[0x1]; 3279 u8 reserved_at_24[0x1]; 3280 u8 log_rq_stride[0x3]; 3281 u8 xrcd[0x18]; 3282 3283 u8 page_offset[0x6]; 3284 u8 reserved_at_46[0x2]; 3285 u8 cqn[0x18]; 3286 3287 u8 reserved_at_60[0x20]; 3288 3289 u8 reserved_at_80[0x2]; 3290 u8 log_page_size[0x6]; 3291 u8 reserved_at_88[0x18]; 3292 3293 u8 reserved_at_a0[0x20]; 3294 3295 u8 reserved_at_c0[0x8]; 3296 u8 pd[0x18]; 3297 3298 u8 lwm[0x10]; 3299 u8 wqe_cnt[0x10]; 3300 3301 u8 reserved_at_100[0x40]; 3302 3303 u8 dbr_addr[0x40]; 3304 3305 u8 reserved_at_180[0x80]; 3306 }; 3307 3308 enum { 3309 MLX5_SQC_STATE_RST = 0x0, 3310 MLX5_SQC_STATE_RDY = 0x1, 3311 MLX5_SQC_STATE_ERR = 0x3, 3312 }; 3313 3314 struct mlx5_ifc_sqc_bits { 3315 u8 rlky[0x1]; 3316 u8 cd_master[0x1]; 3317 u8 fre[0x1]; 3318 u8 flush_in_error_en[0x1]; 3319 u8 allow_multi_pkt_send_wqe[0x1]; 3320 u8 min_wqe_inline_mode[0x3]; 3321 u8 state[0x4]; 3322 u8 reg_umr[0x1]; 3323 u8 allow_swp[0x1]; 3324 u8 hairpin[0x1]; 3325 u8 reserved_at_f[0x11]; 3326 3327 u8 reserved_at_20[0x8]; 3328 u8 user_index[0x18]; 3329 3330 u8 reserved_at_40[0x8]; 3331 u8 cqn[0x18]; 3332 3333 u8 reserved_at_60[0x8]; 3334 u8 hairpin_peer_rq[0x18]; 3335 3336 u8 reserved_at_80[0x10]; 3337 u8 hairpin_peer_vhca[0x10]; 3338 3339 u8 reserved_at_a0[0x20]; 3340 3341 u8 reserved_at_c0[0x8]; 3342 u8 ts_cqe_to_dest_cqn[0x18]; 3343 3344 u8 reserved_at_e0[0x10]; 3345 u8 packet_pacing_rate_limit_index[0x10]; 3346 u8 tis_lst_sz[0x10]; 3347 u8 reserved_at_110[0x10]; 3348 3349 u8 reserved_at_120[0x40]; 3350 3351 u8 reserved_at_160[0x8]; 3352 u8 tis_num_0[0x18]; 3353 3354 struct mlx5_ifc_wq_bits wq; 3355 }; 3356 3357 enum { 3358 SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0, 3359 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1, 3360 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2, 3361 SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3, 3362 }; 3363 3364 enum { 3365 ELEMENT_TYPE_CAP_MASK_TASR = 1 << 0, 3366 ELEMENT_TYPE_CAP_MASK_VPORT = 1 << 1, 3367 ELEMENT_TYPE_CAP_MASK_VPORT_TC = 1 << 2, 3368 ELEMENT_TYPE_CAP_MASK_PARA_VPORT_TC = 1 << 3, 3369 }; 3370 3371 struct mlx5_ifc_scheduling_context_bits { 3372 u8 element_type[0x8]; 3373 u8 reserved_at_8[0x18]; 3374 3375 u8 element_attributes[0x20]; 3376 3377 u8 parent_element_id[0x20]; 3378 3379 u8 reserved_at_60[0x40]; 3380 3381 u8 bw_share[0x20]; 3382 3383 u8 max_average_bw[0x20]; 3384 3385 u8 reserved_at_e0[0x120]; 3386 }; 3387 3388 struct mlx5_ifc_rqtc_bits { 3389 u8 reserved_at_0[0xa0]; 3390 3391 u8 reserved_at_a0[0x5]; 3392 u8 list_q_type[0x3]; 3393 u8 reserved_at_a8[0x8]; 3394 u8 rqt_max_size[0x10]; 3395 3396 u8 rq_vhca_id_format[0x1]; 3397 u8 reserved_at_c1[0xf]; 3398 u8 rqt_actual_size[0x10]; 3399 3400 u8 reserved_at_e0[0x6a0]; 3401 3402 struct mlx5_ifc_rq_num_bits rq_num[]; 3403 }; 3404 3405 enum { 3406 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0, 3407 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1, 3408 }; 3409 3410 enum { 3411 MLX5_RQC_STATE_RST = 0x0, 3412 MLX5_RQC_STATE_RDY = 0x1, 3413 MLX5_RQC_STATE_ERR = 0x3, 3414 }; 3415 3416 struct mlx5_ifc_rqc_bits { 3417 u8 rlky[0x1]; 3418 u8 delay_drop_en[0x1]; 3419 u8 scatter_fcs[0x1]; 3420 u8 vsd[0x1]; 3421 u8 mem_rq_type[0x4]; 3422 u8 state[0x4]; 3423 u8 reserved_at_c[0x1]; 3424 u8 flush_in_error_en[0x1]; 3425 u8 hairpin[0x1]; 3426 u8 reserved_at_f[0x11]; 3427 3428 u8 reserved_at_20[0x8]; 3429 u8 user_index[0x18]; 3430 3431 u8 reserved_at_40[0x8]; 3432 u8 cqn[0x18]; 3433 3434 u8 counter_set_id[0x8]; 3435 u8 reserved_at_68[0x18]; 3436 3437 u8 reserved_at_80[0x8]; 3438 u8 rmpn[0x18]; 3439 3440 u8 reserved_at_a0[0x8]; 3441 u8 hairpin_peer_sq[0x18]; 3442 3443 u8 reserved_at_c0[0x10]; 3444 u8 hairpin_peer_vhca[0x10]; 3445 3446 u8 reserved_at_e0[0xa0]; 3447 3448 struct mlx5_ifc_wq_bits wq; 3449 }; 3450 3451 enum { 3452 MLX5_RMPC_STATE_RDY = 0x1, 3453 MLX5_RMPC_STATE_ERR = 0x3, 3454 }; 3455 3456 struct mlx5_ifc_rmpc_bits { 3457 u8 reserved_at_0[0x8]; 3458 u8 state[0x4]; 3459 u8 reserved_at_c[0x14]; 3460 3461 u8 basic_cyclic_rcv_wqe[0x1]; 3462 u8 reserved_at_21[0x1f]; 3463 3464 u8 reserved_at_40[0x140]; 3465 3466 struct mlx5_ifc_wq_bits wq; 3467 }; 3468 3469 struct mlx5_ifc_nic_vport_context_bits { 3470 u8 reserved_at_0[0x5]; 3471 u8 min_wqe_inline_mode[0x3]; 3472 u8 reserved_at_8[0x15]; 3473 u8 disable_mc_local_lb[0x1]; 3474 u8 disable_uc_local_lb[0x1]; 3475 u8 roce_en[0x1]; 3476 3477 u8 arm_change_event[0x1]; 3478 u8 reserved_at_21[0x1a]; 3479 u8 event_on_mtu[0x1]; 3480 u8 event_on_promisc_change[0x1]; 3481 u8 event_on_vlan_change[0x1]; 3482 u8 event_on_mc_address_change[0x1]; 3483 u8 event_on_uc_address_change[0x1]; 3484 3485 u8 reserved_at_40[0xc]; 3486 3487 u8 affiliation_criteria[0x4]; 3488 u8 affiliated_vhca_id[0x10]; 3489 3490 u8 reserved_at_60[0xd0]; 3491 3492 u8 mtu[0x10]; 3493 3494 u8 system_image_guid[0x40]; 3495 u8 port_guid[0x40]; 3496 u8 node_guid[0x40]; 3497 3498 u8 reserved_at_200[0x140]; 3499 u8 qkey_violation_counter[0x10]; 3500 u8 reserved_at_350[0x430]; 3501 3502 u8 promisc_uc[0x1]; 3503 u8 promisc_mc[0x1]; 3504 u8 promisc_all[0x1]; 3505 u8 reserved_at_783[0x2]; 3506 u8 allowed_list_type[0x3]; 3507 u8 reserved_at_788[0xc]; 3508 u8 allowed_list_size[0xc]; 3509 3510 struct mlx5_ifc_mac_address_layout_bits permanent_address; 3511 3512 u8 reserved_at_7e0[0x20]; 3513 3514 u8 current_uc_mac_address[][0x40]; 3515 }; 3516 3517 enum { 3518 MLX5_MKC_ACCESS_MODE_PA = 0x0, 3519 MLX5_MKC_ACCESS_MODE_MTT = 0x1, 3520 MLX5_MKC_ACCESS_MODE_KLMS = 0x2, 3521 MLX5_MKC_ACCESS_MODE_KSM = 0x3, 3522 MLX5_MKC_ACCESS_MODE_SW_ICM = 0x4, 3523 MLX5_MKC_ACCESS_MODE_MEMIC = 0x5, 3524 }; 3525 3526 struct mlx5_ifc_mkc_bits { 3527 u8 reserved_at_0[0x1]; 3528 u8 free[0x1]; 3529 u8 reserved_at_2[0x1]; 3530 u8 access_mode_4_2[0x3]; 3531 u8 reserved_at_6[0x7]; 3532 u8 relaxed_ordering_write[0x1]; 3533 u8 reserved_at_e[0x1]; 3534 u8 small_fence_on_rdma_read_response[0x1]; 3535 u8 umr_en[0x1]; 3536 u8 a[0x1]; 3537 u8 rw[0x1]; 3538 u8 rr[0x1]; 3539 u8 lw[0x1]; 3540 u8 lr[0x1]; 3541 u8 access_mode_1_0[0x2]; 3542 u8 reserved_at_18[0x8]; 3543 3544 u8 qpn[0x18]; 3545 u8 mkey_7_0[0x8]; 3546 3547 u8 reserved_at_40[0x20]; 3548 3549 u8 length64[0x1]; 3550 u8 bsf_en[0x1]; 3551 u8 sync_umr[0x1]; 3552 u8 reserved_at_63[0x2]; 3553 u8 expected_sigerr_count[0x1]; 3554 u8 reserved_at_66[0x1]; 3555 u8 en_rinval[0x1]; 3556 u8 pd[0x18]; 3557 3558 u8 start_addr[0x40]; 3559 3560 u8 len[0x40]; 3561 3562 u8 bsf_octword_size[0x20]; 3563 3564 u8 reserved_at_120[0x80]; 3565 3566 u8 translations_octword_size[0x20]; 3567 3568 u8 reserved_at_1c0[0x19]; 3569 u8 relaxed_ordering_read[0x1]; 3570 u8 reserved_at_1d9[0x1]; 3571 u8 log_page_size[0x5]; 3572 3573 u8 reserved_at_1e0[0x20]; 3574 }; 3575 3576 struct mlx5_ifc_pkey_bits { 3577 u8 reserved_at_0[0x10]; 3578 u8 pkey[0x10]; 3579 }; 3580 3581 struct mlx5_ifc_array128_auto_bits { 3582 u8 array128_auto[16][0x8]; 3583 }; 3584 3585 struct mlx5_ifc_hca_vport_context_bits { 3586 u8 field_select[0x20]; 3587 3588 u8 reserved_at_20[0xe0]; 3589 3590 u8 sm_virt_aware[0x1]; 3591 u8 has_smi[0x1]; 3592 u8 has_raw[0x1]; 3593 u8 grh_required[0x1]; 3594 u8 reserved_at_104[0xc]; 3595 u8 port_physical_state[0x4]; 3596 u8 vport_state_policy[0x4]; 3597 u8 port_state[0x4]; 3598 u8 vport_state[0x4]; 3599 3600 u8 reserved_at_120[0x20]; 3601 3602 u8 system_image_guid[0x40]; 3603 3604 u8 port_guid[0x40]; 3605 3606 u8 node_guid[0x40]; 3607 3608 u8 cap_mask1[0x20]; 3609 3610 u8 cap_mask1_field_select[0x20]; 3611 3612 u8 cap_mask2[0x20]; 3613 3614 u8 cap_mask2_field_select[0x20]; 3615 3616 u8 reserved_at_280[0x80]; 3617 3618 u8 lid[0x10]; 3619 u8 reserved_at_310[0x4]; 3620 u8 init_type_reply[0x4]; 3621 u8 lmc[0x3]; 3622 u8 subnet_timeout[0x5]; 3623 3624 u8 sm_lid[0x10]; 3625 u8 sm_sl[0x4]; 3626 u8 reserved_at_334[0xc]; 3627 3628 u8 qkey_violation_counter[0x10]; 3629 u8 pkey_violation_counter[0x10]; 3630 3631 u8 reserved_at_360[0xca0]; 3632 }; 3633 3634 struct mlx5_ifc_esw_vport_context_bits { 3635 u8 fdb_to_vport_reg_c[0x1]; 3636 u8 reserved_at_1[0x2]; 3637 u8 vport_svlan_strip[0x1]; 3638 u8 vport_cvlan_strip[0x1]; 3639 u8 vport_svlan_insert[0x1]; 3640 u8 vport_cvlan_insert[0x2]; 3641 u8 fdb_to_vport_reg_c_id[0x8]; 3642 u8 reserved_at_10[0x10]; 3643 3644 u8 reserved_at_20[0x20]; 3645 3646 u8 svlan_cfi[0x1]; 3647 u8 svlan_pcp[0x3]; 3648 u8 svlan_id[0xc]; 3649 u8 cvlan_cfi[0x1]; 3650 u8 cvlan_pcp[0x3]; 3651 u8 cvlan_id[0xc]; 3652 3653 u8 reserved_at_60[0x720]; 3654 3655 u8 sw_steering_vport_icm_address_rx[0x40]; 3656 3657 u8 sw_steering_vport_icm_address_tx[0x40]; 3658 }; 3659 3660 enum { 3661 MLX5_EQC_STATUS_OK = 0x0, 3662 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa, 3663 }; 3664 3665 enum { 3666 MLX5_EQC_ST_ARMED = 0x9, 3667 MLX5_EQC_ST_FIRED = 0xa, 3668 }; 3669 3670 struct mlx5_ifc_eqc_bits { 3671 u8 status[0x4]; 3672 u8 reserved_at_4[0x9]; 3673 u8 ec[0x1]; 3674 u8 oi[0x1]; 3675 u8 reserved_at_f[0x5]; 3676 u8 st[0x4]; 3677 u8 reserved_at_18[0x8]; 3678 3679 u8 reserved_at_20[0x20]; 3680 3681 u8 reserved_at_40[0x14]; 3682 u8 page_offset[0x6]; 3683 u8 reserved_at_5a[0x6]; 3684 3685 u8 reserved_at_60[0x3]; 3686 u8 log_eq_size[0x5]; 3687 u8 uar_page[0x18]; 3688 3689 u8 reserved_at_80[0x20]; 3690 3691 u8 reserved_at_a0[0x18]; 3692 u8 intr[0x8]; 3693 3694 u8 reserved_at_c0[0x3]; 3695 u8 log_page_size[0x5]; 3696 u8 reserved_at_c8[0x18]; 3697 3698 u8 reserved_at_e0[0x60]; 3699 3700 u8 reserved_at_140[0x8]; 3701 u8 consumer_counter[0x18]; 3702 3703 u8 reserved_at_160[0x8]; 3704 u8 producer_counter[0x18]; 3705 3706 u8 reserved_at_180[0x80]; 3707 }; 3708 3709 enum { 3710 MLX5_DCTC_STATE_ACTIVE = 0x0, 3711 MLX5_DCTC_STATE_DRAINING = 0x1, 3712 MLX5_DCTC_STATE_DRAINED = 0x2, 3713 }; 3714 3715 enum { 3716 MLX5_DCTC_CS_RES_DISABLE = 0x0, 3717 MLX5_DCTC_CS_RES_NA = 0x1, 3718 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2, 3719 }; 3720 3721 enum { 3722 MLX5_DCTC_MTU_256_BYTES = 0x1, 3723 MLX5_DCTC_MTU_512_BYTES = 0x2, 3724 MLX5_DCTC_MTU_1K_BYTES = 0x3, 3725 MLX5_DCTC_MTU_2K_BYTES = 0x4, 3726 MLX5_DCTC_MTU_4K_BYTES = 0x5, 3727 }; 3728 3729 struct mlx5_ifc_dctc_bits { 3730 u8 reserved_at_0[0x4]; 3731 u8 state[0x4]; 3732 u8 reserved_at_8[0x18]; 3733 3734 u8 reserved_at_20[0x8]; 3735 u8 user_index[0x18]; 3736 3737 u8 reserved_at_40[0x8]; 3738 u8 cqn[0x18]; 3739 3740 u8 counter_set_id[0x8]; 3741 u8 atomic_mode[0x4]; 3742 u8 rre[0x1]; 3743 u8 rwe[0x1]; 3744 u8 rae[0x1]; 3745 u8 atomic_like_write_en[0x1]; 3746 u8 latency_sensitive[0x1]; 3747 u8 rlky[0x1]; 3748 u8 free_ar[0x1]; 3749 u8 reserved_at_73[0xd]; 3750 3751 u8 reserved_at_80[0x8]; 3752 u8 cs_res[0x8]; 3753 u8 reserved_at_90[0x3]; 3754 u8 min_rnr_nak[0x5]; 3755 u8 reserved_at_98[0x8]; 3756 3757 u8 reserved_at_a0[0x8]; 3758 u8 srqn_xrqn[0x18]; 3759 3760 u8 reserved_at_c0[0x8]; 3761 u8 pd[0x18]; 3762 3763 u8 tclass[0x8]; 3764 u8 reserved_at_e8[0x4]; 3765 u8 flow_label[0x14]; 3766 3767 u8 dc_access_key[0x40]; 3768 3769 u8 reserved_at_140[0x5]; 3770 u8 mtu[0x3]; 3771 u8 port[0x8]; 3772 u8 pkey_index[0x10]; 3773 3774 u8 reserved_at_160[0x8]; 3775 u8 my_addr_index[0x8]; 3776 u8 reserved_at_170[0x8]; 3777 u8 hop_limit[0x8]; 3778 3779 u8 dc_access_key_violation_count[0x20]; 3780 3781 u8 reserved_at_1a0[0x14]; 3782 u8 dei_cfi[0x1]; 3783 u8 eth_prio[0x3]; 3784 u8 ecn[0x2]; 3785 u8 dscp[0x6]; 3786 3787 u8 reserved_at_1c0[0x20]; 3788 u8 ece[0x20]; 3789 }; 3790 3791 enum { 3792 MLX5_CQC_STATUS_OK = 0x0, 3793 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9, 3794 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa, 3795 }; 3796 3797 enum { 3798 MLX5_CQC_CQE_SZ_64_BYTES = 0x0, 3799 MLX5_CQC_CQE_SZ_128_BYTES = 0x1, 3800 }; 3801 3802 enum { 3803 MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED = 0x6, 3804 MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED = 0x9, 3805 MLX5_CQC_ST_FIRED = 0xa, 3806 }; 3807 3808 enum { 3809 MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0, 3810 MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1, 3811 MLX5_CQ_PERIOD_NUM_MODES 3812 }; 3813 3814 struct mlx5_ifc_cqc_bits { 3815 u8 status[0x4]; 3816 u8 reserved_at_4[0x2]; 3817 u8 dbr_umem_valid[0x1]; 3818 u8 reserved_at_7[0x1]; 3819 u8 cqe_sz[0x3]; 3820 u8 cc[0x1]; 3821 u8 reserved_at_c[0x1]; 3822 u8 scqe_break_moderation_en[0x1]; 3823 u8 oi[0x1]; 3824 u8 cq_period_mode[0x2]; 3825 u8 cqe_comp_en[0x1]; 3826 u8 mini_cqe_res_format[0x2]; 3827 u8 st[0x4]; 3828 u8 reserved_at_18[0x8]; 3829 3830 u8 reserved_at_20[0x20]; 3831 3832 u8 reserved_at_40[0x14]; 3833 u8 page_offset[0x6]; 3834 u8 reserved_at_5a[0x6]; 3835 3836 u8 reserved_at_60[0x3]; 3837 u8 log_cq_size[0x5]; 3838 u8 uar_page[0x18]; 3839 3840 u8 reserved_at_80[0x4]; 3841 u8 cq_period[0xc]; 3842 u8 cq_max_count[0x10]; 3843 3844 u8 reserved_at_a0[0x18]; 3845 u8 c_eqn[0x8]; 3846 3847 u8 reserved_at_c0[0x3]; 3848 u8 log_page_size[0x5]; 3849 u8 reserved_at_c8[0x18]; 3850 3851 u8 reserved_at_e0[0x20]; 3852 3853 u8 reserved_at_100[0x8]; 3854 u8 last_notified_index[0x18]; 3855 3856 u8 reserved_at_120[0x8]; 3857 u8 last_solicit_index[0x18]; 3858 3859 u8 reserved_at_140[0x8]; 3860 u8 consumer_counter[0x18]; 3861 3862 u8 reserved_at_160[0x8]; 3863 u8 producer_counter[0x18]; 3864 3865 u8 reserved_at_180[0x40]; 3866 3867 u8 dbr_addr[0x40]; 3868 }; 3869 3870 union mlx5_ifc_cong_control_roce_ecn_auto_bits { 3871 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp; 3872 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp; 3873 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np; 3874 u8 reserved_at_0[0x800]; 3875 }; 3876 3877 struct mlx5_ifc_query_adapter_param_block_bits { 3878 u8 reserved_at_0[0xc0]; 3879 3880 u8 reserved_at_c0[0x8]; 3881 u8 ieee_vendor_id[0x18]; 3882 3883 u8 reserved_at_e0[0x10]; 3884 u8 vsd_vendor_id[0x10]; 3885 3886 u8 vsd[208][0x8]; 3887 3888 u8 vsd_contd_psid[16][0x8]; 3889 }; 3890 3891 enum { 3892 MLX5_XRQC_STATE_GOOD = 0x0, 3893 MLX5_XRQC_STATE_ERROR = 0x1, 3894 }; 3895 3896 enum { 3897 MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0, 3898 MLX5_XRQC_TOPOLOGY_TAG_MATCHING = 0x1, 3899 }; 3900 3901 enum { 3902 MLX5_XRQC_OFFLOAD_RNDV = 0x1, 3903 }; 3904 3905 struct mlx5_ifc_tag_matching_topology_context_bits { 3906 u8 log_matching_list_sz[0x4]; 3907 u8 reserved_at_4[0xc]; 3908 u8 append_next_index[0x10]; 3909 3910 u8 sw_phase_cnt[0x10]; 3911 u8 hw_phase_cnt[0x10]; 3912 3913 u8 reserved_at_40[0x40]; 3914 }; 3915 3916 struct mlx5_ifc_xrqc_bits { 3917 u8 state[0x4]; 3918 u8 rlkey[0x1]; 3919 u8 reserved_at_5[0xf]; 3920 u8 topology[0x4]; 3921 u8 reserved_at_18[0x4]; 3922 u8 offload[0x4]; 3923 3924 u8 reserved_at_20[0x8]; 3925 u8 user_index[0x18]; 3926 3927 u8 reserved_at_40[0x8]; 3928 u8 cqn[0x18]; 3929 3930 u8 reserved_at_60[0xa0]; 3931 3932 struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context; 3933 3934 u8 reserved_at_180[0x280]; 3935 3936 struct mlx5_ifc_wq_bits wq; 3937 }; 3938 3939 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits { 3940 struct mlx5_ifc_modify_field_select_bits modify_field_select; 3941 struct mlx5_ifc_resize_field_select_bits resize_field_select; 3942 u8 reserved_at_0[0x20]; 3943 }; 3944 3945 union mlx5_ifc_field_select_802_1_r_roce_auto_bits { 3946 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp; 3947 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp; 3948 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np; 3949 u8 reserved_at_0[0x20]; 3950 }; 3951 3952 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits { 3953 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 3954 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 3955 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 3956 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 3957 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 3958 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 3959 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout; 3960 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout; 3961 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 3962 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 3963 struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs; 3964 u8 reserved_at_0[0x7c0]; 3965 }; 3966 3967 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits { 3968 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout; 3969 u8 reserved_at_0[0x7c0]; 3970 }; 3971 3972 union mlx5_ifc_event_auto_bits { 3973 struct mlx5_ifc_comp_event_bits comp_event; 3974 struct mlx5_ifc_dct_events_bits dct_events; 3975 struct mlx5_ifc_qp_events_bits qp_events; 3976 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event; 3977 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event; 3978 struct mlx5_ifc_cq_error_bits cq_error; 3979 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged; 3980 struct mlx5_ifc_port_state_change_event_bits port_state_change_event; 3981 struct mlx5_ifc_gpio_event_bits gpio_event; 3982 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event; 3983 struct mlx5_ifc_stall_vl_event_bits stall_vl_event; 3984 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event; 3985 u8 reserved_at_0[0xe0]; 3986 }; 3987 3988 struct mlx5_ifc_health_buffer_bits { 3989 u8 reserved_at_0[0x100]; 3990 3991 u8 assert_existptr[0x20]; 3992 3993 u8 assert_callra[0x20]; 3994 3995 u8 reserved_at_140[0x40]; 3996 3997 u8 fw_version[0x20]; 3998 3999 u8 hw_id[0x20]; 4000 4001 u8 reserved_at_1c0[0x20]; 4002 4003 u8 irisc_index[0x8]; 4004 u8 synd[0x8]; 4005 u8 ext_synd[0x10]; 4006 }; 4007 4008 struct mlx5_ifc_register_loopback_control_bits { 4009 u8 no_lb[0x1]; 4010 u8 reserved_at_1[0x7]; 4011 u8 port[0x8]; 4012 u8 reserved_at_10[0x10]; 4013 4014 u8 reserved_at_20[0x60]; 4015 }; 4016 4017 struct mlx5_ifc_vport_tc_element_bits { 4018 u8 traffic_class[0x4]; 4019 u8 reserved_at_4[0xc]; 4020 u8 vport_number[0x10]; 4021 }; 4022 4023 struct mlx5_ifc_vport_element_bits { 4024 u8 reserved_at_0[0x10]; 4025 u8 vport_number[0x10]; 4026 }; 4027 4028 enum { 4029 TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0, 4030 TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1, 4031 TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2, 4032 }; 4033 4034 struct mlx5_ifc_tsar_element_bits { 4035 u8 reserved_at_0[0x8]; 4036 u8 tsar_type[0x8]; 4037 u8 reserved_at_10[0x10]; 4038 }; 4039 4040 enum { 4041 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0, 4042 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1, 4043 }; 4044 4045 struct mlx5_ifc_teardown_hca_out_bits { 4046 u8 status[0x8]; 4047 u8 reserved_at_8[0x18]; 4048 4049 u8 syndrome[0x20]; 4050 4051 u8 reserved_at_40[0x3f]; 4052 4053 u8 state[0x1]; 4054 }; 4055 4056 enum { 4057 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0, 4058 MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE = 0x1, 4059 MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN = 0x2, 4060 }; 4061 4062 struct mlx5_ifc_teardown_hca_in_bits { 4063 u8 opcode[0x10]; 4064 u8 reserved_at_10[0x10]; 4065 4066 u8 reserved_at_20[0x10]; 4067 u8 op_mod[0x10]; 4068 4069 u8 reserved_at_40[0x10]; 4070 u8 profile[0x10]; 4071 4072 u8 reserved_at_60[0x20]; 4073 }; 4074 4075 struct mlx5_ifc_sqerr2rts_qp_out_bits { 4076 u8 status[0x8]; 4077 u8 reserved_at_8[0x18]; 4078 4079 u8 syndrome[0x20]; 4080 4081 u8 reserved_at_40[0x40]; 4082 }; 4083 4084 struct mlx5_ifc_sqerr2rts_qp_in_bits { 4085 u8 opcode[0x10]; 4086 u8 uid[0x10]; 4087 4088 u8 reserved_at_20[0x10]; 4089 u8 op_mod[0x10]; 4090 4091 u8 reserved_at_40[0x8]; 4092 u8 qpn[0x18]; 4093 4094 u8 reserved_at_60[0x20]; 4095 4096 u8 opt_param_mask[0x20]; 4097 4098 u8 reserved_at_a0[0x20]; 4099 4100 struct mlx5_ifc_qpc_bits qpc; 4101 4102 u8 reserved_at_800[0x80]; 4103 }; 4104 4105 struct mlx5_ifc_sqd2rts_qp_out_bits { 4106 u8 status[0x8]; 4107 u8 reserved_at_8[0x18]; 4108 4109 u8 syndrome[0x20]; 4110 4111 u8 reserved_at_40[0x40]; 4112 }; 4113 4114 struct mlx5_ifc_sqd2rts_qp_in_bits { 4115 u8 opcode[0x10]; 4116 u8 uid[0x10]; 4117 4118 u8 reserved_at_20[0x10]; 4119 u8 op_mod[0x10]; 4120 4121 u8 reserved_at_40[0x8]; 4122 u8 qpn[0x18]; 4123 4124 u8 reserved_at_60[0x20]; 4125 4126 u8 opt_param_mask[0x20]; 4127 4128 u8 reserved_at_a0[0x20]; 4129 4130 struct mlx5_ifc_qpc_bits qpc; 4131 4132 u8 reserved_at_800[0x80]; 4133 }; 4134 4135 struct mlx5_ifc_set_roce_address_out_bits { 4136 u8 status[0x8]; 4137 u8 reserved_at_8[0x18]; 4138 4139 u8 syndrome[0x20]; 4140 4141 u8 reserved_at_40[0x40]; 4142 }; 4143 4144 struct mlx5_ifc_set_roce_address_in_bits { 4145 u8 opcode[0x10]; 4146 u8 reserved_at_10[0x10]; 4147 4148 u8 reserved_at_20[0x10]; 4149 u8 op_mod[0x10]; 4150 4151 u8 roce_address_index[0x10]; 4152 u8 reserved_at_50[0xc]; 4153 u8 vhca_port_num[0x4]; 4154 4155 u8 reserved_at_60[0x20]; 4156 4157 struct mlx5_ifc_roce_addr_layout_bits roce_address; 4158 }; 4159 4160 struct mlx5_ifc_set_mad_demux_out_bits { 4161 u8 status[0x8]; 4162 u8 reserved_at_8[0x18]; 4163 4164 u8 syndrome[0x20]; 4165 4166 u8 reserved_at_40[0x40]; 4167 }; 4168 4169 enum { 4170 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0, 4171 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2, 4172 }; 4173 4174 struct mlx5_ifc_set_mad_demux_in_bits { 4175 u8 opcode[0x10]; 4176 u8 reserved_at_10[0x10]; 4177 4178 u8 reserved_at_20[0x10]; 4179 u8 op_mod[0x10]; 4180 4181 u8 reserved_at_40[0x20]; 4182 4183 u8 reserved_at_60[0x6]; 4184 u8 demux_mode[0x2]; 4185 u8 reserved_at_68[0x18]; 4186 }; 4187 4188 struct mlx5_ifc_set_l2_table_entry_out_bits { 4189 u8 status[0x8]; 4190 u8 reserved_at_8[0x18]; 4191 4192 u8 syndrome[0x20]; 4193 4194 u8 reserved_at_40[0x40]; 4195 }; 4196 4197 struct mlx5_ifc_set_l2_table_entry_in_bits { 4198 u8 opcode[0x10]; 4199 u8 reserved_at_10[0x10]; 4200 4201 u8 reserved_at_20[0x10]; 4202 u8 op_mod[0x10]; 4203 4204 u8 reserved_at_40[0x60]; 4205 4206 u8 reserved_at_a0[0x8]; 4207 u8 table_index[0x18]; 4208 4209 u8 reserved_at_c0[0x20]; 4210 4211 u8 reserved_at_e0[0x13]; 4212 u8 vlan_valid[0x1]; 4213 u8 vlan[0xc]; 4214 4215 struct mlx5_ifc_mac_address_layout_bits mac_address; 4216 4217 u8 reserved_at_140[0xc0]; 4218 }; 4219 4220 struct mlx5_ifc_set_issi_out_bits { 4221 u8 status[0x8]; 4222 u8 reserved_at_8[0x18]; 4223 4224 u8 syndrome[0x20]; 4225 4226 u8 reserved_at_40[0x40]; 4227 }; 4228 4229 struct mlx5_ifc_set_issi_in_bits { 4230 u8 opcode[0x10]; 4231 u8 reserved_at_10[0x10]; 4232 4233 u8 reserved_at_20[0x10]; 4234 u8 op_mod[0x10]; 4235 4236 u8 reserved_at_40[0x10]; 4237 u8 current_issi[0x10]; 4238 4239 u8 reserved_at_60[0x20]; 4240 }; 4241 4242 struct mlx5_ifc_set_hca_cap_out_bits { 4243 u8 status[0x8]; 4244 u8 reserved_at_8[0x18]; 4245 4246 u8 syndrome[0x20]; 4247 4248 u8 reserved_at_40[0x40]; 4249 }; 4250 4251 struct mlx5_ifc_set_hca_cap_in_bits { 4252 u8 opcode[0x10]; 4253 u8 reserved_at_10[0x10]; 4254 4255 u8 reserved_at_20[0x10]; 4256 u8 op_mod[0x10]; 4257 4258 u8 other_function[0x1]; 4259 u8 reserved_at_41[0xf]; 4260 u8 function_id[0x10]; 4261 4262 u8 reserved_at_60[0x20]; 4263 4264 union mlx5_ifc_hca_cap_union_bits capability; 4265 }; 4266 4267 enum { 4268 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0, 4269 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1, 4270 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2, 4271 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3, 4272 MLX5_SET_FTE_MODIFY_ENABLE_MASK_IPSEC_OBJ_ID = 0x4 4273 }; 4274 4275 struct mlx5_ifc_set_fte_out_bits { 4276 u8 status[0x8]; 4277 u8 reserved_at_8[0x18]; 4278 4279 u8 syndrome[0x20]; 4280 4281 u8 reserved_at_40[0x40]; 4282 }; 4283 4284 struct mlx5_ifc_set_fte_in_bits { 4285 u8 opcode[0x10]; 4286 u8 reserved_at_10[0x10]; 4287 4288 u8 reserved_at_20[0x10]; 4289 u8 op_mod[0x10]; 4290 4291 u8 other_vport[0x1]; 4292 u8 reserved_at_41[0xf]; 4293 u8 vport_number[0x10]; 4294 4295 u8 reserved_at_60[0x20]; 4296 4297 u8 table_type[0x8]; 4298 u8 reserved_at_88[0x18]; 4299 4300 u8 reserved_at_a0[0x8]; 4301 u8 table_id[0x18]; 4302 4303 u8 ignore_flow_level[0x1]; 4304 u8 reserved_at_c1[0x17]; 4305 u8 modify_enable_mask[0x8]; 4306 4307 u8 reserved_at_e0[0x20]; 4308 4309 u8 flow_index[0x20]; 4310 4311 u8 reserved_at_120[0xe0]; 4312 4313 struct mlx5_ifc_flow_context_bits flow_context; 4314 }; 4315 4316 struct mlx5_ifc_rts2rts_qp_out_bits { 4317 u8 status[0x8]; 4318 u8 reserved_at_8[0x18]; 4319 4320 u8 syndrome[0x20]; 4321 4322 u8 reserved_at_40[0x20]; 4323 u8 ece[0x20]; 4324 }; 4325 4326 struct mlx5_ifc_rts2rts_qp_in_bits { 4327 u8 opcode[0x10]; 4328 u8 uid[0x10]; 4329 4330 u8 reserved_at_20[0x10]; 4331 u8 op_mod[0x10]; 4332 4333 u8 reserved_at_40[0x8]; 4334 u8 qpn[0x18]; 4335 4336 u8 reserved_at_60[0x20]; 4337 4338 u8 opt_param_mask[0x20]; 4339 4340 u8 ece[0x20]; 4341 4342 struct mlx5_ifc_qpc_bits qpc; 4343 4344 u8 reserved_at_800[0x80]; 4345 }; 4346 4347 struct mlx5_ifc_rtr2rts_qp_out_bits { 4348 u8 status[0x8]; 4349 u8 reserved_at_8[0x18]; 4350 4351 u8 syndrome[0x20]; 4352 4353 u8 reserved_at_40[0x20]; 4354 u8 ece[0x20]; 4355 }; 4356 4357 struct mlx5_ifc_rtr2rts_qp_in_bits { 4358 u8 opcode[0x10]; 4359 u8 uid[0x10]; 4360 4361 u8 reserved_at_20[0x10]; 4362 u8 op_mod[0x10]; 4363 4364 u8 reserved_at_40[0x8]; 4365 u8 qpn[0x18]; 4366 4367 u8 reserved_at_60[0x20]; 4368 4369 u8 opt_param_mask[0x20]; 4370 4371 u8 ece[0x20]; 4372 4373 struct mlx5_ifc_qpc_bits qpc; 4374 4375 u8 reserved_at_800[0x80]; 4376 }; 4377 4378 struct mlx5_ifc_rst2init_qp_out_bits { 4379 u8 status[0x8]; 4380 u8 reserved_at_8[0x18]; 4381 4382 u8 syndrome[0x20]; 4383 4384 u8 reserved_at_40[0x20]; 4385 u8 ece[0x20]; 4386 }; 4387 4388 struct mlx5_ifc_rst2init_qp_in_bits { 4389 u8 opcode[0x10]; 4390 u8 uid[0x10]; 4391 4392 u8 reserved_at_20[0x10]; 4393 u8 op_mod[0x10]; 4394 4395 u8 reserved_at_40[0x8]; 4396 u8 qpn[0x18]; 4397 4398 u8 reserved_at_60[0x20]; 4399 4400 u8 opt_param_mask[0x20]; 4401 4402 u8 ece[0x20]; 4403 4404 struct mlx5_ifc_qpc_bits qpc; 4405 4406 u8 reserved_at_800[0x80]; 4407 }; 4408 4409 struct mlx5_ifc_query_xrq_out_bits { 4410 u8 status[0x8]; 4411 u8 reserved_at_8[0x18]; 4412 4413 u8 syndrome[0x20]; 4414 4415 u8 reserved_at_40[0x40]; 4416 4417 struct mlx5_ifc_xrqc_bits xrq_context; 4418 }; 4419 4420 struct mlx5_ifc_query_xrq_in_bits { 4421 u8 opcode[0x10]; 4422 u8 reserved_at_10[0x10]; 4423 4424 u8 reserved_at_20[0x10]; 4425 u8 op_mod[0x10]; 4426 4427 u8 reserved_at_40[0x8]; 4428 u8 xrqn[0x18]; 4429 4430 u8 reserved_at_60[0x20]; 4431 }; 4432 4433 struct mlx5_ifc_query_xrc_srq_out_bits { 4434 u8 status[0x8]; 4435 u8 reserved_at_8[0x18]; 4436 4437 u8 syndrome[0x20]; 4438 4439 u8 reserved_at_40[0x40]; 4440 4441 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 4442 4443 u8 reserved_at_280[0x600]; 4444 4445 u8 pas[][0x40]; 4446 }; 4447 4448 struct mlx5_ifc_query_xrc_srq_in_bits { 4449 u8 opcode[0x10]; 4450 u8 reserved_at_10[0x10]; 4451 4452 u8 reserved_at_20[0x10]; 4453 u8 op_mod[0x10]; 4454 4455 u8 reserved_at_40[0x8]; 4456 u8 xrc_srqn[0x18]; 4457 4458 u8 reserved_at_60[0x20]; 4459 }; 4460 4461 enum { 4462 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0, 4463 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1, 4464 }; 4465 4466 struct mlx5_ifc_query_vport_state_out_bits { 4467 u8 status[0x8]; 4468 u8 reserved_at_8[0x18]; 4469 4470 u8 syndrome[0x20]; 4471 4472 u8 reserved_at_40[0x20]; 4473 4474 u8 reserved_at_60[0x18]; 4475 u8 admin_state[0x4]; 4476 u8 state[0x4]; 4477 }; 4478 4479 enum { 4480 MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT = 0x0, 4481 MLX5_VPORT_STATE_OP_MOD_ESW_VPORT = 0x1, 4482 MLX5_VPORT_STATE_OP_MOD_UPLINK = 0x2, 4483 }; 4484 4485 struct mlx5_ifc_arm_monitor_counter_in_bits { 4486 u8 opcode[0x10]; 4487 u8 uid[0x10]; 4488 4489 u8 reserved_at_20[0x10]; 4490 u8 op_mod[0x10]; 4491 4492 u8 reserved_at_40[0x20]; 4493 4494 u8 reserved_at_60[0x20]; 4495 }; 4496 4497 struct mlx5_ifc_arm_monitor_counter_out_bits { 4498 u8 status[0x8]; 4499 u8 reserved_at_8[0x18]; 4500 4501 u8 syndrome[0x20]; 4502 4503 u8 reserved_at_40[0x40]; 4504 }; 4505 4506 enum { 4507 MLX5_QUERY_MONITOR_CNT_TYPE_PPCNT = 0x0, 4508 MLX5_QUERY_MONITOR_CNT_TYPE_Q_COUNTER = 0x1, 4509 }; 4510 4511 enum mlx5_monitor_counter_ppcnt { 4512 MLX5_QUERY_MONITOR_PPCNT_IN_RANGE_LENGTH_ERRORS = 0x0, 4513 MLX5_QUERY_MONITOR_PPCNT_OUT_OF_RANGE_LENGTH_FIELD = 0x1, 4514 MLX5_QUERY_MONITOR_PPCNT_FRAME_TOO_LONG_ERRORS = 0x2, 4515 MLX5_QUERY_MONITOR_PPCNT_FRAME_CHECK_SEQUENCE_ERRORS = 0x3, 4516 MLX5_QUERY_MONITOR_PPCNT_ALIGNMENT_ERRORS = 0x4, 4517 MLX5_QUERY_MONITOR_PPCNT_IF_OUT_DISCARDS = 0x5, 4518 }; 4519 4520 enum { 4521 MLX5_QUERY_MONITOR_Q_COUNTER_RX_OUT_OF_BUFFER = 0x4, 4522 }; 4523 4524 struct mlx5_ifc_monitor_counter_output_bits { 4525 u8 reserved_at_0[0x4]; 4526 u8 type[0x4]; 4527 u8 reserved_at_8[0x8]; 4528 u8 counter[0x10]; 4529 4530 u8 counter_group_id[0x20]; 4531 }; 4532 4533 #define MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 (6) 4534 #define MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1 (1) 4535 #define MLX5_CMD_SET_MONITOR_NUM_COUNTER (MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 +\ 4536 MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1) 4537 4538 struct mlx5_ifc_set_monitor_counter_in_bits { 4539 u8 opcode[0x10]; 4540 u8 uid[0x10]; 4541 4542 u8 reserved_at_20[0x10]; 4543 u8 op_mod[0x10]; 4544 4545 u8 reserved_at_40[0x10]; 4546 u8 num_of_counters[0x10]; 4547 4548 u8 reserved_at_60[0x20]; 4549 4550 struct mlx5_ifc_monitor_counter_output_bits monitor_counter[MLX5_CMD_SET_MONITOR_NUM_COUNTER]; 4551 }; 4552 4553 struct mlx5_ifc_set_monitor_counter_out_bits { 4554 u8 status[0x8]; 4555 u8 reserved_at_8[0x18]; 4556 4557 u8 syndrome[0x20]; 4558 4559 u8 reserved_at_40[0x40]; 4560 }; 4561 4562 struct mlx5_ifc_query_vport_state_in_bits { 4563 u8 opcode[0x10]; 4564 u8 reserved_at_10[0x10]; 4565 4566 u8 reserved_at_20[0x10]; 4567 u8 op_mod[0x10]; 4568 4569 u8 other_vport[0x1]; 4570 u8 reserved_at_41[0xf]; 4571 u8 vport_number[0x10]; 4572 4573 u8 reserved_at_60[0x20]; 4574 }; 4575 4576 struct mlx5_ifc_query_vnic_env_out_bits { 4577 u8 status[0x8]; 4578 u8 reserved_at_8[0x18]; 4579 4580 u8 syndrome[0x20]; 4581 4582 u8 reserved_at_40[0x40]; 4583 4584 struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env; 4585 }; 4586 4587 enum { 4588 MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS = 0x0, 4589 }; 4590 4591 struct mlx5_ifc_query_vnic_env_in_bits { 4592 u8 opcode[0x10]; 4593 u8 reserved_at_10[0x10]; 4594 4595 u8 reserved_at_20[0x10]; 4596 u8 op_mod[0x10]; 4597 4598 u8 other_vport[0x1]; 4599 u8 reserved_at_41[0xf]; 4600 u8 vport_number[0x10]; 4601 4602 u8 reserved_at_60[0x20]; 4603 }; 4604 4605 struct mlx5_ifc_query_vport_counter_out_bits { 4606 u8 status[0x8]; 4607 u8 reserved_at_8[0x18]; 4608 4609 u8 syndrome[0x20]; 4610 4611 u8 reserved_at_40[0x40]; 4612 4613 struct mlx5_ifc_traffic_counter_bits received_errors; 4614 4615 struct mlx5_ifc_traffic_counter_bits transmit_errors; 4616 4617 struct mlx5_ifc_traffic_counter_bits received_ib_unicast; 4618 4619 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast; 4620 4621 struct mlx5_ifc_traffic_counter_bits received_ib_multicast; 4622 4623 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast; 4624 4625 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast; 4626 4627 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast; 4628 4629 struct mlx5_ifc_traffic_counter_bits received_eth_unicast; 4630 4631 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast; 4632 4633 struct mlx5_ifc_traffic_counter_bits received_eth_multicast; 4634 4635 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast; 4636 4637 u8 reserved_at_680[0xa00]; 4638 }; 4639 4640 enum { 4641 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0, 4642 }; 4643 4644 struct mlx5_ifc_query_vport_counter_in_bits { 4645 u8 opcode[0x10]; 4646 u8 reserved_at_10[0x10]; 4647 4648 u8 reserved_at_20[0x10]; 4649 u8 op_mod[0x10]; 4650 4651 u8 other_vport[0x1]; 4652 u8 reserved_at_41[0xb]; 4653 u8 port_num[0x4]; 4654 u8 vport_number[0x10]; 4655 4656 u8 reserved_at_60[0x60]; 4657 4658 u8 clear[0x1]; 4659 u8 reserved_at_c1[0x1f]; 4660 4661 u8 reserved_at_e0[0x20]; 4662 }; 4663 4664 struct mlx5_ifc_query_tis_out_bits { 4665 u8 status[0x8]; 4666 u8 reserved_at_8[0x18]; 4667 4668 u8 syndrome[0x20]; 4669 4670 u8 reserved_at_40[0x40]; 4671 4672 struct mlx5_ifc_tisc_bits tis_context; 4673 }; 4674 4675 struct mlx5_ifc_query_tis_in_bits { 4676 u8 opcode[0x10]; 4677 u8 reserved_at_10[0x10]; 4678 4679 u8 reserved_at_20[0x10]; 4680 u8 op_mod[0x10]; 4681 4682 u8 reserved_at_40[0x8]; 4683 u8 tisn[0x18]; 4684 4685 u8 reserved_at_60[0x20]; 4686 }; 4687 4688 struct mlx5_ifc_query_tir_out_bits { 4689 u8 status[0x8]; 4690 u8 reserved_at_8[0x18]; 4691 4692 u8 syndrome[0x20]; 4693 4694 u8 reserved_at_40[0xc0]; 4695 4696 struct mlx5_ifc_tirc_bits tir_context; 4697 }; 4698 4699 struct mlx5_ifc_query_tir_in_bits { 4700 u8 opcode[0x10]; 4701 u8 reserved_at_10[0x10]; 4702 4703 u8 reserved_at_20[0x10]; 4704 u8 op_mod[0x10]; 4705 4706 u8 reserved_at_40[0x8]; 4707 u8 tirn[0x18]; 4708 4709 u8 reserved_at_60[0x20]; 4710 }; 4711 4712 struct mlx5_ifc_query_srq_out_bits { 4713 u8 status[0x8]; 4714 u8 reserved_at_8[0x18]; 4715 4716 u8 syndrome[0x20]; 4717 4718 u8 reserved_at_40[0x40]; 4719 4720 struct mlx5_ifc_srqc_bits srq_context_entry; 4721 4722 u8 reserved_at_280[0x600]; 4723 4724 u8 pas[][0x40]; 4725 }; 4726 4727 struct mlx5_ifc_query_srq_in_bits { 4728 u8 opcode[0x10]; 4729 u8 reserved_at_10[0x10]; 4730 4731 u8 reserved_at_20[0x10]; 4732 u8 op_mod[0x10]; 4733 4734 u8 reserved_at_40[0x8]; 4735 u8 srqn[0x18]; 4736 4737 u8 reserved_at_60[0x20]; 4738 }; 4739 4740 struct mlx5_ifc_query_sq_out_bits { 4741 u8 status[0x8]; 4742 u8 reserved_at_8[0x18]; 4743 4744 u8 syndrome[0x20]; 4745 4746 u8 reserved_at_40[0xc0]; 4747 4748 struct mlx5_ifc_sqc_bits sq_context; 4749 }; 4750 4751 struct mlx5_ifc_query_sq_in_bits { 4752 u8 opcode[0x10]; 4753 u8 reserved_at_10[0x10]; 4754 4755 u8 reserved_at_20[0x10]; 4756 u8 op_mod[0x10]; 4757 4758 u8 reserved_at_40[0x8]; 4759 u8 sqn[0x18]; 4760 4761 u8 reserved_at_60[0x20]; 4762 }; 4763 4764 struct mlx5_ifc_query_special_contexts_out_bits { 4765 u8 status[0x8]; 4766 u8 reserved_at_8[0x18]; 4767 4768 u8 syndrome[0x20]; 4769 4770 u8 dump_fill_mkey[0x20]; 4771 4772 u8 resd_lkey[0x20]; 4773 4774 u8 null_mkey[0x20]; 4775 4776 u8 reserved_at_a0[0x60]; 4777 }; 4778 4779 struct mlx5_ifc_query_special_contexts_in_bits { 4780 u8 opcode[0x10]; 4781 u8 reserved_at_10[0x10]; 4782 4783 u8 reserved_at_20[0x10]; 4784 u8 op_mod[0x10]; 4785 4786 u8 reserved_at_40[0x40]; 4787 }; 4788 4789 struct mlx5_ifc_query_scheduling_element_out_bits { 4790 u8 opcode[0x10]; 4791 u8 reserved_at_10[0x10]; 4792 4793 u8 reserved_at_20[0x10]; 4794 u8 op_mod[0x10]; 4795 4796 u8 reserved_at_40[0xc0]; 4797 4798 struct mlx5_ifc_scheduling_context_bits scheduling_context; 4799 4800 u8 reserved_at_300[0x100]; 4801 }; 4802 4803 enum { 4804 SCHEDULING_HIERARCHY_E_SWITCH = 0x2, 4805 }; 4806 4807 struct mlx5_ifc_query_scheduling_element_in_bits { 4808 u8 opcode[0x10]; 4809 u8 reserved_at_10[0x10]; 4810 4811 u8 reserved_at_20[0x10]; 4812 u8 op_mod[0x10]; 4813 4814 u8 scheduling_hierarchy[0x8]; 4815 u8 reserved_at_48[0x18]; 4816 4817 u8 scheduling_element_id[0x20]; 4818 4819 u8 reserved_at_80[0x180]; 4820 }; 4821 4822 struct mlx5_ifc_query_rqt_out_bits { 4823 u8 status[0x8]; 4824 u8 reserved_at_8[0x18]; 4825 4826 u8 syndrome[0x20]; 4827 4828 u8 reserved_at_40[0xc0]; 4829 4830 struct mlx5_ifc_rqtc_bits rqt_context; 4831 }; 4832 4833 struct mlx5_ifc_query_rqt_in_bits { 4834 u8 opcode[0x10]; 4835 u8 reserved_at_10[0x10]; 4836 4837 u8 reserved_at_20[0x10]; 4838 u8 op_mod[0x10]; 4839 4840 u8 reserved_at_40[0x8]; 4841 u8 rqtn[0x18]; 4842 4843 u8 reserved_at_60[0x20]; 4844 }; 4845 4846 struct mlx5_ifc_query_rq_out_bits { 4847 u8 status[0x8]; 4848 u8 reserved_at_8[0x18]; 4849 4850 u8 syndrome[0x20]; 4851 4852 u8 reserved_at_40[0xc0]; 4853 4854 struct mlx5_ifc_rqc_bits rq_context; 4855 }; 4856 4857 struct mlx5_ifc_query_rq_in_bits { 4858 u8 opcode[0x10]; 4859 u8 reserved_at_10[0x10]; 4860 4861 u8 reserved_at_20[0x10]; 4862 u8 op_mod[0x10]; 4863 4864 u8 reserved_at_40[0x8]; 4865 u8 rqn[0x18]; 4866 4867 u8 reserved_at_60[0x20]; 4868 }; 4869 4870 struct mlx5_ifc_query_roce_address_out_bits { 4871 u8 status[0x8]; 4872 u8 reserved_at_8[0x18]; 4873 4874 u8 syndrome[0x20]; 4875 4876 u8 reserved_at_40[0x40]; 4877 4878 struct mlx5_ifc_roce_addr_layout_bits roce_address; 4879 }; 4880 4881 struct mlx5_ifc_query_roce_address_in_bits { 4882 u8 opcode[0x10]; 4883 u8 reserved_at_10[0x10]; 4884 4885 u8 reserved_at_20[0x10]; 4886 u8 op_mod[0x10]; 4887 4888 u8 roce_address_index[0x10]; 4889 u8 reserved_at_50[0xc]; 4890 u8 vhca_port_num[0x4]; 4891 4892 u8 reserved_at_60[0x20]; 4893 }; 4894 4895 struct mlx5_ifc_query_rmp_out_bits { 4896 u8 status[0x8]; 4897 u8 reserved_at_8[0x18]; 4898 4899 u8 syndrome[0x20]; 4900 4901 u8 reserved_at_40[0xc0]; 4902 4903 struct mlx5_ifc_rmpc_bits rmp_context; 4904 }; 4905 4906 struct mlx5_ifc_query_rmp_in_bits { 4907 u8 opcode[0x10]; 4908 u8 reserved_at_10[0x10]; 4909 4910 u8 reserved_at_20[0x10]; 4911 u8 op_mod[0x10]; 4912 4913 u8 reserved_at_40[0x8]; 4914 u8 rmpn[0x18]; 4915 4916 u8 reserved_at_60[0x20]; 4917 }; 4918 4919 struct mlx5_ifc_query_qp_out_bits { 4920 u8 status[0x8]; 4921 u8 reserved_at_8[0x18]; 4922 4923 u8 syndrome[0x20]; 4924 4925 u8 reserved_at_40[0x20]; 4926 u8 ece[0x20]; 4927 4928 u8 opt_param_mask[0x20]; 4929 4930 u8 reserved_at_a0[0x20]; 4931 4932 struct mlx5_ifc_qpc_bits qpc; 4933 4934 u8 reserved_at_800[0x80]; 4935 4936 u8 pas[][0x40]; 4937 }; 4938 4939 struct mlx5_ifc_query_qp_in_bits { 4940 u8 opcode[0x10]; 4941 u8 reserved_at_10[0x10]; 4942 4943 u8 reserved_at_20[0x10]; 4944 u8 op_mod[0x10]; 4945 4946 u8 reserved_at_40[0x8]; 4947 u8 qpn[0x18]; 4948 4949 u8 reserved_at_60[0x20]; 4950 }; 4951 4952 struct mlx5_ifc_query_q_counter_out_bits { 4953 u8 status[0x8]; 4954 u8 reserved_at_8[0x18]; 4955 4956 u8 syndrome[0x20]; 4957 4958 u8 reserved_at_40[0x40]; 4959 4960 u8 rx_write_requests[0x20]; 4961 4962 u8 reserved_at_a0[0x20]; 4963 4964 u8 rx_read_requests[0x20]; 4965 4966 u8 reserved_at_e0[0x20]; 4967 4968 u8 rx_atomic_requests[0x20]; 4969 4970 u8 reserved_at_120[0x20]; 4971 4972 u8 rx_dct_connect[0x20]; 4973 4974 u8 reserved_at_160[0x20]; 4975 4976 u8 out_of_buffer[0x20]; 4977 4978 u8 reserved_at_1a0[0x20]; 4979 4980 u8 out_of_sequence[0x20]; 4981 4982 u8 reserved_at_1e0[0x20]; 4983 4984 u8 duplicate_request[0x20]; 4985 4986 u8 reserved_at_220[0x20]; 4987 4988 u8 rnr_nak_retry_err[0x20]; 4989 4990 u8 reserved_at_260[0x20]; 4991 4992 u8 packet_seq_err[0x20]; 4993 4994 u8 reserved_at_2a0[0x20]; 4995 4996 u8 implied_nak_seq_err[0x20]; 4997 4998 u8 reserved_at_2e0[0x20]; 4999 5000 u8 local_ack_timeout_err[0x20]; 5001 5002 u8 reserved_at_320[0xa0]; 5003 5004 u8 resp_local_length_error[0x20]; 5005 5006 u8 req_local_length_error[0x20]; 5007 5008 u8 resp_local_qp_error[0x20]; 5009 5010 u8 local_operation_error[0x20]; 5011 5012 u8 resp_local_protection[0x20]; 5013 5014 u8 req_local_protection[0x20]; 5015 5016 u8 resp_cqe_error[0x20]; 5017 5018 u8 req_cqe_error[0x20]; 5019 5020 u8 req_mw_binding[0x20]; 5021 5022 u8 req_bad_response[0x20]; 5023 5024 u8 req_remote_invalid_request[0x20]; 5025 5026 u8 resp_remote_invalid_request[0x20]; 5027 5028 u8 req_remote_access_errors[0x20]; 5029 5030 u8 resp_remote_access_errors[0x20]; 5031 5032 u8 req_remote_operation_errors[0x20]; 5033 5034 u8 req_transport_retries_exceeded[0x20]; 5035 5036 u8 cq_overflow[0x20]; 5037 5038 u8 resp_cqe_flush_error[0x20]; 5039 5040 u8 req_cqe_flush_error[0x20]; 5041 5042 u8 reserved_at_620[0x20]; 5043 5044 u8 roce_adp_retrans[0x20]; 5045 5046 u8 roce_adp_retrans_to[0x20]; 5047 5048 u8 roce_slow_restart[0x20]; 5049 5050 u8 roce_slow_restart_cnps[0x20]; 5051 5052 u8 roce_slow_restart_trans[0x20]; 5053 5054 u8 reserved_at_6e0[0x120]; 5055 }; 5056 5057 struct mlx5_ifc_query_q_counter_in_bits { 5058 u8 opcode[0x10]; 5059 u8 reserved_at_10[0x10]; 5060 5061 u8 reserved_at_20[0x10]; 5062 u8 op_mod[0x10]; 5063 5064 u8 reserved_at_40[0x80]; 5065 5066 u8 clear[0x1]; 5067 u8 reserved_at_c1[0x1f]; 5068 5069 u8 reserved_at_e0[0x18]; 5070 u8 counter_set_id[0x8]; 5071 }; 5072 5073 struct mlx5_ifc_query_pages_out_bits { 5074 u8 status[0x8]; 5075 u8 reserved_at_8[0x18]; 5076 5077 u8 syndrome[0x20]; 5078 5079 u8 embedded_cpu_function[0x1]; 5080 u8 reserved_at_41[0xf]; 5081 u8 function_id[0x10]; 5082 5083 u8 num_pages[0x20]; 5084 }; 5085 5086 enum { 5087 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1, 5088 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2, 5089 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3, 5090 }; 5091 5092 struct mlx5_ifc_query_pages_in_bits { 5093 u8 opcode[0x10]; 5094 u8 reserved_at_10[0x10]; 5095 5096 u8 reserved_at_20[0x10]; 5097 u8 op_mod[0x10]; 5098 5099 u8 embedded_cpu_function[0x1]; 5100 u8 reserved_at_41[0xf]; 5101 u8 function_id[0x10]; 5102 5103 u8 reserved_at_60[0x20]; 5104 }; 5105 5106 struct mlx5_ifc_query_nic_vport_context_out_bits { 5107 u8 status[0x8]; 5108 u8 reserved_at_8[0x18]; 5109 5110 u8 syndrome[0x20]; 5111 5112 u8 reserved_at_40[0x40]; 5113 5114 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 5115 }; 5116 5117 struct mlx5_ifc_query_nic_vport_context_in_bits { 5118 u8 opcode[0x10]; 5119 u8 reserved_at_10[0x10]; 5120 5121 u8 reserved_at_20[0x10]; 5122 u8 op_mod[0x10]; 5123 5124 u8 other_vport[0x1]; 5125 u8 reserved_at_41[0xf]; 5126 u8 vport_number[0x10]; 5127 5128 u8 reserved_at_60[0x5]; 5129 u8 allowed_list_type[0x3]; 5130 u8 reserved_at_68[0x18]; 5131 }; 5132 5133 struct mlx5_ifc_query_mkey_out_bits { 5134 u8 status[0x8]; 5135 u8 reserved_at_8[0x18]; 5136 5137 u8 syndrome[0x20]; 5138 5139 u8 reserved_at_40[0x40]; 5140 5141 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 5142 5143 u8 reserved_at_280[0x600]; 5144 5145 u8 bsf0_klm0_pas_mtt0_1[16][0x8]; 5146 5147 u8 bsf1_klm1_pas_mtt2_3[16][0x8]; 5148 }; 5149 5150 struct mlx5_ifc_query_mkey_in_bits { 5151 u8 opcode[0x10]; 5152 u8 reserved_at_10[0x10]; 5153 5154 u8 reserved_at_20[0x10]; 5155 u8 op_mod[0x10]; 5156 5157 u8 reserved_at_40[0x8]; 5158 u8 mkey_index[0x18]; 5159 5160 u8 pg_access[0x1]; 5161 u8 reserved_at_61[0x1f]; 5162 }; 5163 5164 struct mlx5_ifc_query_mad_demux_out_bits { 5165 u8 status[0x8]; 5166 u8 reserved_at_8[0x18]; 5167 5168 u8 syndrome[0x20]; 5169 5170 u8 reserved_at_40[0x40]; 5171 5172 u8 mad_dumux_parameters_block[0x20]; 5173 }; 5174 5175 struct mlx5_ifc_query_mad_demux_in_bits { 5176 u8 opcode[0x10]; 5177 u8 reserved_at_10[0x10]; 5178 5179 u8 reserved_at_20[0x10]; 5180 u8 op_mod[0x10]; 5181 5182 u8 reserved_at_40[0x40]; 5183 }; 5184 5185 struct mlx5_ifc_query_l2_table_entry_out_bits { 5186 u8 status[0x8]; 5187 u8 reserved_at_8[0x18]; 5188 5189 u8 syndrome[0x20]; 5190 5191 u8 reserved_at_40[0xa0]; 5192 5193 u8 reserved_at_e0[0x13]; 5194 u8 vlan_valid[0x1]; 5195 u8 vlan[0xc]; 5196 5197 struct mlx5_ifc_mac_address_layout_bits mac_address; 5198 5199 u8 reserved_at_140[0xc0]; 5200 }; 5201 5202 struct mlx5_ifc_query_l2_table_entry_in_bits { 5203 u8 opcode[0x10]; 5204 u8 reserved_at_10[0x10]; 5205 5206 u8 reserved_at_20[0x10]; 5207 u8 op_mod[0x10]; 5208 5209 u8 reserved_at_40[0x60]; 5210 5211 u8 reserved_at_a0[0x8]; 5212 u8 table_index[0x18]; 5213 5214 u8 reserved_at_c0[0x140]; 5215 }; 5216 5217 struct mlx5_ifc_query_issi_out_bits { 5218 u8 status[0x8]; 5219 u8 reserved_at_8[0x18]; 5220 5221 u8 syndrome[0x20]; 5222 5223 u8 reserved_at_40[0x10]; 5224 u8 current_issi[0x10]; 5225 5226 u8 reserved_at_60[0xa0]; 5227 5228 u8 reserved_at_100[76][0x8]; 5229 u8 supported_issi_dw0[0x20]; 5230 }; 5231 5232 struct mlx5_ifc_query_issi_in_bits { 5233 u8 opcode[0x10]; 5234 u8 reserved_at_10[0x10]; 5235 5236 u8 reserved_at_20[0x10]; 5237 u8 op_mod[0x10]; 5238 5239 u8 reserved_at_40[0x40]; 5240 }; 5241 5242 struct mlx5_ifc_set_driver_version_out_bits { 5243 u8 status[0x8]; 5244 u8 reserved_0[0x18]; 5245 5246 u8 syndrome[0x20]; 5247 u8 reserved_1[0x40]; 5248 }; 5249 5250 struct mlx5_ifc_set_driver_version_in_bits { 5251 u8 opcode[0x10]; 5252 u8 reserved_0[0x10]; 5253 5254 u8 reserved_1[0x10]; 5255 u8 op_mod[0x10]; 5256 5257 u8 reserved_2[0x40]; 5258 u8 driver_version[64][0x8]; 5259 }; 5260 5261 struct mlx5_ifc_query_hca_vport_pkey_out_bits { 5262 u8 status[0x8]; 5263 u8 reserved_at_8[0x18]; 5264 5265 u8 syndrome[0x20]; 5266 5267 u8 reserved_at_40[0x40]; 5268 5269 struct mlx5_ifc_pkey_bits pkey[]; 5270 }; 5271 5272 struct mlx5_ifc_query_hca_vport_pkey_in_bits { 5273 u8 opcode[0x10]; 5274 u8 reserved_at_10[0x10]; 5275 5276 u8 reserved_at_20[0x10]; 5277 u8 op_mod[0x10]; 5278 5279 u8 other_vport[0x1]; 5280 u8 reserved_at_41[0xb]; 5281 u8 port_num[0x4]; 5282 u8 vport_number[0x10]; 5283 5284 u8 reserved_at_60[0x10]; 5285 u8 pkey_index[0x10]; 5286 }; 5287 5288 enum { 5289 MLX5_HCA_VPORT_SEL_PORT_GUID = 1 << 0, 5290 MLX5_HCA_VPORT_SEL_NODE_GUID = 1 << 1, 5291 MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2, 5292 }; 5293 5294 struct mlx5_ifc_query_hca_vport_gid_out_bits { 5295 u8 status[0x8]; 5296 u8 reserved_at_8[0x18]; 5297 5298 u8 syndrome[0x20]; 5299 5300 u8 reserved_at_40[0x20]; 5301 5302 u8 gids_num[0x10]; 5303 u8 reserved_at_70[0x10]; 5304 5305 struct mlx5_ifc_array128_auto_bits gid[]; 5306 }; 5307 5308 struct mlx5_ifc_query_hca_vport_gid_in_bits { 5309 u8 opcode[0x10]; 5310 u8 reserved_at_10[0x10]; 5311 5312 u8 reserved_at_20[0x10]; 5313 u8 op_mod[0x10]; 5314 5315 u8 other_vport[0x1]; 5316 u8 reserved_at_41[0xb]; 5317 u8 port_num[0x4]; 5318 u8 vport_number[0x10]; 5319 5320 u8 reserved_at_60[0x10]; 5321 u8 gid_index[0x10]; 5322 }; 5323 5324 struct mlx5_ifc_query_hca_vport_context_out_bits { 5325 u8 status[0x8]; 5326 u8 reserved_at_8[0x18]; 5327 5328 u8 syndrome[0x20]; 5329 5330 u8 reserved_at_40[0x40]; 5331 5332 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 5333 }; 5334 5335 struct mlx5_ifc_query_hca_vport_context_in_bits { 5336 u8 opcode[0x10]; 5337 u8 reserved_at_10[0x10]; 5338 5339 u8 reserved_at_20[0x10]; 5340 u8 op_mod[0x10]; 5341 5342 u8 other_vport[0x1]; 5343 u8 reserved_at_41[0xb]; 5344 u8 port_num[0x4]; 5345 u8 vport_number[0x10]; 5346 5347 u8 reserved_at_60[0x20]; 5348 }; 5349 5350 struct mlx5_ifc_query_hca_cap_out_bits { 5351 u8 status[0x8]; 5352 u8 reserved_at_8[0x18]; 5353 5354 u8 syndrome[0x20]; 5355 5356 u8 reserved_at_40[0x40]; 5357 5358 union mlx5_ifc_hca_cap_union_bits capability; 5359 }; 5360 5361 struct mlx5_ifc_query_hca_cap_in_bits { 5362 u8 opcode[0x10]; 5363 u8 reserved_at_10[0x10]; 5364 5365 u8 reserved_at_20[0x10]; 5366 u8 op_mod[0x10]; 5367 5368 u8 other_function[0x1]; 5369 u8 reserved_at_41[0xf]; 5370 u8 function_id[0x10]; 5371 5372 u8 reserved_at_60[0x20]; 5373 }; 5374 5375 struct mlx5_ifc_other_hca_cap_bits { 5376 u8 roce[0x1]; 5377 u8 reserved_at_1[0x27f]; 5378 }; 5379 5380 struct mlx5_ifc_query_other_hca_cap_out_bits { 5381 u8 status[0x8]; 5382 u8 reserved_at_8[0x18]; 5383 5384 u8 syndrome[0x20]; 5385 5386 u8 reserved_at_40[0x40]; 5387 5388 struct mlx5_ifc_other_hca_cap_bits other_capability; 5389 }; 5390 5391 struct mlx5_ifc_query_other_hca_cap_in_bits { 5392 u8 opcode[0x10]; 5393 u8 reserved_at_10[0x10]; 5394 5395 u8 reserved_at_20[0x10]; 5396 u8 op_mod[0x10]; 5397 5398 u8 reserved_at_40[0x10]; 5399 u8 function_id[0x10]; 5400 5401 u8 reserved_at_60[0x20]; 5402 }; 5403 5404 struct mlx5_ifc_modify_other_hca_cap_out_bits { 5405 u8 status[0x8]; 5406 u8 reserved_at_8[0x18]; 5407 5408 u8 syndrome[0x20]; 5409 5410 u8 reserved_at_40[0x40]; 5411 }; 5412 5413 struct mlx5_ifc_modify_other_hca_cap_in_bits { 5414 u8 opcode[0x10]; 5415 u8 reserved_at_10[0x10]; 5416 5417 u8 reserved_at_20[0x10]; 5418 u8 op_mod[0x10]; 5419 5420 u8 reserved_at_40[0x10]; 5421 u8 function_id[0x10]; 5422 u8 field_select[0x20]; 5423 5424 struct mlx5_ifc_other_hca_cap_bits other_capability; 5425 }; 5426 5427 struct mlx5_ifc_flow_table_context_bits { 5428 u8 reformat_en[0x1]; 5429 u8 decap_en[0x1]; 5430 u8 sw_owner[0x1]; 5431 u8 termination_table[0x1]; 5432 u8 table_miss_action[0x4]; 5433 u8 level[0x8]; 5434 u8 reserved_at_10[0x8]; 5435 u8 log_size[0x8]; 5436 5437 u8 reserved_at_20[0x8]; 5438 u8 table_miss_id[0x18]; 5439 5440 u8 reserved_at_40[0x8]; 5441 u8 lag_master_next_table_id[0x18]; 5442 5443 u8 reserved_at_60[0x60]; 5444 5445 u8 sw_owner_icm_root_1[0x40]; 5446 5447 u8 sw_owner_icm_root_0[0x40]; 5448 5449 }; 5450 5451 struct mlx5_ifc_query_flow_table_out_bits { 5452 u8 status[0x8]; 5453 u8 reserved_at_8[0x18]; 5454 5455 u8 syndrome[0x20]; 5456 5457 u8 reserved_at_40[0x80]; 5458 5459 struct mlx5_ifc_flow_table_context_bits flow_table_context; 5460 }; 5461 5462 struct mlx5_ifc_query_flow_table_in_bits { 5463 u8 opcode[0x10]; 5464 u8 reserved_at_10[0x10]; 5465 5466 u8 reserved_at_20[0x10]; 5467 u8 op_mod[0x10]; 5468 5469 u8 reserved_at_40[0x40]; 5470 5471 u8 table_type[0x8]; 5472 u8 reserved_at_88[0x18]; 5473 5474 u8 reserved_at_a0[0x8]; 5475 u8 table_id[0x18]; 5476 5477 u8 reserved_at_c0[0x140]; 5478 }; 5479 5480 struct mlx5_ifc_query_fte_out_bits { 5481 u8 status[0x8]; 5482 u8 reserved_at_8[0x18]; 5483 5484 u8 syndrome[0x20]; 5485 5486 u8 reserved_at_40[0x1c0]; 5487 5488 struct mlx5_ifc_flow_context_bits flow_context; 5489 }; 5490 5491 struct mlx5_ifc_query_fte_in_bits { 5492 u8 opcode[0x10]; 5493 u8 reserved_at_10[0x10]; 5494 5495 u8 reserved_at_20[0x10]; 5496 u8 op_mod[0x10]; 5497 5498 u8 reserved_at_40[0x40]; 5499 5500 u8 table_type[0x8]; 5501 u8 reserved_at_88[0x18]; 5502 5503 u8 reserved_at_a0[0x8]; 5504 u8 table_id[0x18]; 5505 5506 u8 reserved_at_c0[0x40]; 5507 5508 u8 flow_index[0x20]; 5509 5510 u8 reserved_at_120[0xe0]; 5511 }; 5512 5513 enum { 5514 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 5515 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 5516 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 5517 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3, 5518 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_3 = 0x4, 5519 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_4 = 0x5, 5520 }; 5521 5522 struct mlx5_ifc_query_flow_group_out_bits { 5523 u8 status[0x8]; 5524 u8 reserved_at_8[0x18]; 5525 5526 u8 syndrome[0x20]; 5527 5528 u8 reserved_at_40[0xa0]; 5529 5530 u8 start_flow_index[0x20]; 5531 5532 u8 reserved_at_100[0x20]; 5533 5534 u8 end_flow_index[0x20]; 5535 5536 u8 reserved_at_140[0xa0]; 5537 5538 u8 reserved_at_1e0[0x18]; 5539 u8 match_criteria_enable[0x8]; 5540 5541 struct mlx5_ifc_fte_match_param_bits match_criteria; 5542 5543 u8 reserved_at_1200[0xe00]; 5544 }; 5545 5546 struct mlx5_ifc_query_flow_group_in_bits { 5547 u8 opcode[0x10]; 5548 u8 reserved_at_10[0x10]; 5549 5550 u8 reserved_at_20[0x10]; 5551 u8 op_mod[0x10]; 5552 5553 u8 reserved_at_40[0x40]; 5554 5555 u8 table_type[0x8]; 5556 u8 reserved_at_88[0x18]; 5557 5558 u8 reserved_at_a0[0x8]; 5559 u8 table_id[0x18]; 5560 5561 u8 group_id[0x20]; 5562 5563 u8 reserved_at_e0[0x120]; 5564 }; 5565 5566 struct mlx5_ifc_query_flow_counter_out_bits { 5567 u8 status[0x8]; 5568 u8 reserved_at_8[0x18]; 5569 5570 u8 syndrome[0x20]; 5571 5572 u8 reserved_at_40[0x40]; 5573 5574 struct mlx5_ifc_traffic_counter_bits flow_statistics[]; 5575 }; 5576 5577 struct mlx5_ifc_query_flow_counter_in_bits { 5578 u8 opcode[0x10]; 5579 u8 reserved_at_10[0x10]; 5580 5581 u8 reserved_at_20[0x10]; 5582 u8 op_mod[0x10]; 5583 5584 u8 reserved_at_40[0x80]; 5585 5586 u8 clear[0x1]; 5587 u8 reserved_at_c1[0xf]; 5588 u8 num_of_counters[0x10]; 5589 5590 u8 flow_counter_id[0x20]; 5591 }; 5592 5593 struct mlx5_ifc_query_esw_vport_context_out_bits { 5594 u8 status[0x8]; 5595 u8 reserved_at_8[0x18]; 5596 5597 u8 syndrome[0x20]; 5598 5599 u8 reserved_at_40[0x40]; 5600 5601 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 5602 }; 5603 5604 struct mlx5_ifc_query_esw_vport_context_in_bits { 5605 u8 opcode[0x10]; 5606 u8 reserved_at_10[0x10]; 5607 5608 u8 reserved_at_20[0x10]; 5609 u8 op_mod[0x10]; 5610 5611 u8 other_vport[0x1]; 5612 u8 reserved_at_41[0xf]; 5613 u8 vport_number[0x10]; 5614 5615 u8 reserved_at_60[0x20]; 5616 }; 5617 5618 struct mlx5_ifc_modify_esw_vport_context_out_bits { 5619 u8 status[0x8]; 5620 u8 reserved_at_8[0x18]; 5621 5622 u8 syndrome[0x20]; 5623 5624 u8 reserved_at_40[0x40]; 5625 }; 5626 5627 struct mlx5_ifc_esw_vport_context_fields_select_bits { 5628 u8 reserved_at_0[0x1b]; 5629 u8 fdb_to_vport_reg_c_id[0x1]; 5630 u8 vport_cvlan_insert[0x1]; 5631 u8 vport_svlan_insert[0x1]; 5632 u8 vport_cvlan_strip[0x1]; 5633 u8 vport_svlan_strip[0x1]; 5634 }; 5635 5636 struct mlx5_ifc_modify_esw_vport_context_in_bits { 5637 u8 opcode[0x10]; 5638 u8 reserved_at_10[0x10]; 5639 5640 u8 reserved_at_20[0x10]; 5641 u8 op_mod[0x10]; 5642 5643 u8 other_vport[0x1]; 5644 u8 reserved_at_41[0xf]; 5645 u8 vport_number[0x10]; 5646 5647 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select; 5648 5649 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 5650 }; 5651 5652 struct mlx5_ifc_query_eq_out_bits { 5653 u8 status[0x8]; 5654 u8 reserved_at_8[0x18]; 5655 5656 u8 syndrome[0x20]; 5657 5658 u8 reserved_at_40[0x40]; 5659 5660 struct mlx5_ifc_eqc_bits eq_context_entry; 5661 5662 u8 reserved_at_280[0x40]; 5663 5664 u8 event_bitmask[0x40]; 5665 5666 u8 reserved_at_300[0x580]; 5667 5668 u8 pas[][0x40]; 5669 }; 5670 5671 struct mlx5_ifc_query_eq_in_bits { 5672 u8 opcode[0x10]; 5673 u8 reserved_at_10[0x10]; 5674 5675 u8 reserved_at_20[0x10]; 5676 u8 op_mod[0x10]; 5677 5678 u8 reserved_at_40[0x18]; 5679 u8 eq_number[0x8]; 5680 5681 u8 reserved_at_60[0x20]; 5682 }; 5683 5684 struct mlx5_ifc_packet_reformat_context_in_bits { 5685 u8 reserved_at_0[0x5]; 5686 u8 reformat_type[0x3]; 5687 u8 reserved_at_8[0xe]; 5688 u8 reformat_data_size[0xa]; 5689 5690 u8 reserved_at_20[0x10]; 5691 u8 reformat_data[2][0x8]; 5692 5693 u8 more_reformat_data[][0x8]; 5694 }; 5695 5696 struct mlx5_ifc_query_packet_reformat_context_out_bits { 5697 u8 status[0x8]; 5698 u8 reserved_at_8[0x18]; 5699 5700 u8 syndrome[0x20]; 5701 5702 u8 reserved_at_40[0xa0]; 5703 5704 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context[]; 5705 }; 5706 5707 struct mlx5_ifc_query_packet_reformat_context_in_bits { 5708 u8 opcode[0x10]; 5709 u8 reserved_at_10[0x10]; 5710 5711 u8 reserved_at_20[0x10]; 5712 u8 op_mod[0x10]; 5713 5714 u8 packet_reformat_id[0x20]; 5715 5716 u8 reserved_at_60[0xa0]; 5717 }; 5718 5719 struct mlx5_ifc_alloc_packet_reformat_context_out_bits { 5720 u8 status[0x8]; 5721 u8 reserved_at_8[0x18]; 5722 5723 u8 syndrome[0x20]; 5724 5725 u8 packet_reformat_id[0x20]; 5726 5727 u8 reserved_at_60[0x20]; 5728 }; 5729 5730 enum mlx5_reformat_ctx_type { 5731 MLX5_REFORMAT_TYPE_L2_TO_VXLAN = 0x0, 5732 MLX5_REFORMAT_TYPE_L2_TO_NVGRE = 0x1, 5733 MLX5_REFORMAT_TYPE_L2_TO_L2_TUNNEL = 0x2, 5734 MLX5_REFORMAT_TYPE_L3_TUNNEL_TO_L2 = 0x3, 5735 MLX5_REFORMAT_TYPE_L2_TO_L3_TUNNEL = 0x4, 5736 }; 5737 5738 struct mlx5_ifc_alloc_packet_reformat_context_in_bits { 5739 u8 opcode[0x10]; 5740 u8 reserved_at_10[0x10]; 5741 5742 u8 reserved_at_20[0x10]; 5743 u8 op_mod[0x10]; 5744 5745 u8 reserved_at_40[0xa0]; 5746 5747 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context; 5748 }; 5749 5750 struct mlx5_ifc_dealloc_packet_reformat_context_out_bits { 5751 u8 status[0x8]; 5752 u8 reserved_at_8[0x18]; 5753 5754 u8 syndrome[0x20]; 5755 5756 u8 reserved_at_40[0x40]; 5757 }; 5758 5759 struct mlx5_ifc_dealloc_packet_reformat_context_in_bits { 5760 u8 opcode[0x10]; 5761 u8 reserved_at_10[0x10]; 5762 5763 u8 reserved_20[0x10]; 5764 u8 op_mod[0x10]; 5765 5766 u8 packet_reformat_id[0x20]; 5767 5768 u8 reserved_60[0x20]; 5769 }; 5770 5771 struct mlx5_ifc_set_action_in_bits { 5772 u8 action_type[0x4]; 5773 u8 field[0xc]; 5774 u8 reserved_at_10[0x3]; 5775 u8 offset[0x5]; 5776 u8 reserved_at_18[0x3]; 5777 u8 length[0x5]; 5778 5779 u8 data[0x20]; 5780 }; 5781 5782 struct mlx5_ifc_add_action_in_bits { 5783 u8 action_type[0x4]; 5784 u8 field[0xc]; 5785 u8 reserved_at_10[0x10]; 5786 5787 u8 data[0x20]; 5788 }; 5789 5790 struct mlx5_ifc_copy_action_in_bits { 5791 u8 action_type[0x4]; 5792 u8 src_field[0xc]; 5793 u8 reserved_at_10[0x3]; 5794 u8 src_offset[0x5]; 5795 u8 reserved_at_18[0x3]; 5796 u8 length[0x5]; 5797 5798 u8 reserved_at_20[0x4]; 5799 u8 dst_field[0xc]; 5800 u8 reserved_at_30[0x3]; 5801 u8 dst_offset[0x5]; 5802 u8 reserved_at_38[0x8]; 5803 }; 5804 5805 union mlx5_ifc_set_add_copy_action_in_auto_bits { 5806 struct mlx5_ifc_set_action_in_bits set_action_in; 5807 struct mlx5_ifc_add_action_in_bits add_action_in; 5808 struct mlx5_ifc_copy_action_in_bits copy_action_in; 5809 u8 reserved_at_0[0x40]; 5810 }; 5811 5812 enum { 5813 MLX5_ACTION_TYPE_SET = 0x1, 5814 MLX5_ACTION_TYPE_ADD = 0x2, 5815 MLX5_ACTION_TYPE_COPY = 0x3, 5816 }; 5817 5818 enum { 5819 MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16 = 0x1, 5820 MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0 = 0x2, 5821 MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE = 0x3, 5822 MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16 = 0x4, 5823 MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0 = 0x5, 5824 MLX5_ACTION_IN_FIELD_OUT_IP_DSCP = 0x6, 5825 MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS = 0x7, 5826 MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT = 0x8, 5827 MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT = 0x9, 5828 MLX5_ACTION_IN_FIELD_OUT_IP_TTL = 0xa, 5829 MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT = 0xb, 5830 MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT = 0xc, 5831 MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96 = 0xd, 5832 MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64 = 0xe, 5833 MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32 = 0xf, 5834 MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0 = 0x10, 5835 MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96 = 0x11, 5836 MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64 = 0x12, 5837 MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32 = 0x13, 5838 MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0 = 0x14, 5839 MLX5_ACTION_IN_FIELD_OUT_SIPV4 = 0x15, 5840 MLX5_ACTION_IN_FIELD_OUT_DIPV4 = 0x16, 5841 MLX5_ACTION_IN_FIELD_OUT_FIRST_VID = 0x17, 5842 MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47, 5843 MLX5_ACTION_IN_FIELD_METADATA_REG_A = 0x49, 5844 MLX5_ACTION_IN_FIELD_METADATA_REG_B = 0x50, 5845 MLX5_ACTION_IN_FIELD_METADATA_REG_C_0 = 0x51, 5846 MLX5_ACTION_IN_FIELD_METADATA_REG_C_1 = 0x52, 5847 MLX5_ACTION_IN_FIELD_METADATA_REG_C_2 = 0x53, 5848 MLX5_ACTION_IN_FIELD_METADATA_REG_C_3 = 0x54, 5849 MLX5_ACTION_IN_FIELD_METADATA_REG_C_4 = 0x55, 5850 MLX5_ACTION_IN_FIELD_METADATA_REG_C_5 = 0x56, 5851 MLX5_ACTION_IN_FIELD_METADATA_REG_C_6 = 0x57, 5852 MLX5_ACTION_IN_FIELD_METADATA_REG_C_7 = 0x58, 5853 MLX5_ACTION_IN_FIELD_OUT_TCP_SEQ_NUM = 0x59, 5854 MLX5_ACTION_IN_FIELD_OUT_TCP_ACK_NUM = 0x5B, 5855 MLX5_ACTION_IN_FIELD_IPSEC_SYNDROME = 0x5D, 5856 }; 5857 5858 struct mlx5_ifc_alloc_modify_header_context_out_bits { 5859 u8 status[0x8]; 5860 u8 reserved_at_8[0x18]; 5861 5862 u8 syndrome[0x20]; 5863 5864 u8 modify_header_id[0x20]; 5865 5866 u8 reserved_at_60[0x20]; 5867 }; 5868 5869 struct mlx5_ifc_alloc_modify_header_context_in_bits { 5870 u8 opcode[0x10]; 5871 u8 reserved_at_10[0x10]; 5872 5873 u8 reserved_at_20[0x10]; 5874 u8 op_mod[0x10]; 5875 5876 u8 reserved_at_40[0x20]; 5877 5878 u8 table_type[0x8]; 5879 u8 reserved_at_68[0x10]; 5880 u8 num_of_actions[0x8]; 5881 5882 union mlx5_ifc_set_add_copy_action_in_auto_bits actions[]; 5883 }; 5884 5885 struct mlx5_ifc_dealloc_modify_header_context_out_bits { 5886 u8 status[0x8]; 5887 u8 reserved_at_8[0x18]; 5888 5889 u8 syndrome[0x20]; 5890 5891 u8 reserved_at_40[0x40]; 5892 }; 5893 5894 struct mlx5_ifc_dealloc_modify_header_context_in_bits { 5895 u8 opcode[0x10]; 5896 u8 reserved_at_10[0x10]; 5897 5898 u8 reserved_at_20[0x10]; 5899 u8 op_mod[0x10]; 5900 5901 u8 modify_header_id[0x20]; 5902 5903 u8 reserved_at_60[0x20]; 5904 }; 5905 5906 struct mlx5_ifc_query_dct_out_bits { 5907 u8 status[0x8]; 5908 u8 reserved_at_8[0x18]; 5909 5910 u8 syndrome[0x20]; 5911 5912 u8 reserved_at_40[0x40]; 5913 5914 struct mlx5_ifc_dctc_bits dct_context_entry; 5915 5916 u8 reserved_at_280[0x180]; 5917 }; 5918 5919 struct mlx5_ifc_query_dct_in_bits { 5920 u8 opcode[0x10]; 5921 u8 reserved_at_10[0x10]; 5922 5923 u8 reserved_at_20[0x10]; 5924 u8 op_mod[0x10]; 5925 5926 u8 reserved_at_40[0x8]; 5927 u8 dctn[0x18]; 5928 5929 u8 reserved_at_60[0x20]; 5930 }; 5931 5932 struct mlx5_ifc_query_cq_out_bits { 5933 u8 status[0x8]; 5934 u8 reserved_at_8[0x18]; 5935 5936 u8 syndrome[0x20]; 5937 5938 u8 reserved_at_40[0x40]; 5939 5940 struct mlx5_ifc_cqc_bits cq_context; 5941 5942 u8 reserved_at_280[0x600]; 5943 5944 u8 pas[][0x40]; 5945 }; 5946 5947 struct mlx5_ifc_query_cq_in_bits { 5948 u8 opcode[0x10]; 5949 u8 reserved_at_10[0x10]; 5950 5951 u8 reserved_at_20[0x10]; 5952 u8 op_mod[0x10]; 5953 5954 u8 reserved_at_40[0x8]; 5955 u8 cqn[0x18]; 5956 5957 u8 reserved_at_60[0x20]; 5958 }; 5959 5960 struct mlx5_ifc_query_cong_status_out_bits { 5961 u8 status[0x8]; 5962 u8 reserved_at_8[0x18]; 5963 5964 u8 syndrome[0x20]; 5965 5966 u8 reserved_at_40[0x20]; 5967 5968 u8 enable[0x1]; 5969 u8 tag_enable[0x1]; 5970 u8 reserved_at_62[0x1e]; 5971 }; 5972 5973 struct mlx5_ifc_query_cong_status_in_bits { 5974 u8 opcode[0x10]; 5975 u8 reserved_at_10[0x10]; 5976 5977 u8 reserved_at_20[0x10]; 5978 u8 op_mod[0x10]; 5979 5980 u8 reserved_at_40[0x18]; 5981 u8 priority[0x4]; 5982 u8 cong_protocol[0x4]; 5983 5984 u8 reserved_at_60[0x20]; 5985 }; 5986 5987 struct mlx5_ifc_query_cong_statistics_out_bits { 5988 u8 status[0x8]; 5989 u8 reserved_at_8[0x18]; 5990 5991 u8 syndrome[0x20]; 5992 5993 u8 reserved_at_40[0x40]; 5994 5995 u8 rp_cur_flows[0x20]; 5996 5997 u8 sum_flows[0x20]; 5998 5999 u8 rp_cnp_ignored_high[0x20]; 6000 6001 u8 rp_cnp_ignored_low[0x20]; 6002 6003 u8 rp_cnp_handled_high[0x20]; 6004 6005 u8 rp_cnp_handled_low[0x20]; 6006 6007 u8 reserved_at_140[0x100]; 6008 6009 u8 time_stamp_high[0x20]; 6010 6011 u8 time_stamp_low[0x20]; 6012 6013 u8 accumulators_period[0x20]; 6014 6015 u8 np_ecn_marked_roce_packets_high[0x20]; 6016 6017 u8 np_ecn_marked_roce_packets_low[0x20]; 6018 6019 u8 np_cnp_sent_high[0x20]; 6020 6021 u8 np_cnp_sent_low[0x20]; 6022 6023 u8 reserved_at_320[0x560]; 6024 }; 6025 6026 struct mlx5_ifc_query_cong_statistics_in_bits { 6027 u8 opcode[0x10]; 6028 u8 reserved_at_10[0x10]; 6029 6030 u8 reserved_at_20[0x10]; 6031 u8 op_mod[0x10]; 6032 6033 u8 clear[0x1]; 6034 u8 reserved_at_41[0x1f]; 6035 6036 u8 reserved_at_60[0x20]; 6037 }; 6038 6039 struct mlx5_ifc_query_cong_params_out_bits { 6040 u8 status[0x8]; 6041 u8 reserved_at_8[0x18]; 6042 6043 u8 syndrome[0x20]; 6044 6045 u8 reserved_at_40[0x40]; 6046 6047 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 6048 }; 6049 6050 struct mlx5_ifc_query_cong_params_in_bits { 6051 u8 opcode[0x10]; 6052 u8 reserved_at_10[0x10]; 6053 6054 u8 reserved_at_20[0x10]; 6055 u8 op_mod[0x10]; 6056 6057 u8 reserved_at_40[0x1c]; 6058 u8 cong_protocol[0x4]; 6059 6060 u8 reserved_at_60[0x20]; 6061 }; 6062 6063 struct mlx5_ifc_query_adapter_out_bits { 6064 u8 status[0x8]; 6065 u8 reserved_at_8[0x18]; 6066 6067 u8 syndrome[0x20]; 6068 6069 u8 reserved_at_40[0x40]; 6070 6071 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct; 6072 }; 6073 6074 struct mlx5_ifc_query_adapter_in_bits { 6075 u8 opcode[0x10]; 6076 u8 reserved_at_10[0x10]; 6077 6078 u8 reserved_at_20[0x10]; 6079 u8 op_mod[0x10]; 6080 6081 u8 reserved_at_40[0x40]; 6082 }; 6083 6084 struct mlx5_ifc_qp_2rst_out_bits { 6085 u8 status[0x8]; 6086 u8 reserved_at_8[0x18]; 6087 6088 u8 syndrome[0x20]; 6089 6090 u8 reserved_at_40[0x40]; 6091 }; 6092 6093 struct mlx5_ifc_qp_2rst_in_bits { 6094 u8 opcode[0x10]; 6095 u8 uid[0x10]; 6096 6097 u8 reserved_at_20[0x10]; 6098 u8 op_mod[0x10]; 6099 6100 u8 reserved_at_40[0x8]; 6101 u8 qpn[0x18]; 6102 6103 u8 reserved_at_60[0x20]; 6104 }; 6105 6106 struct mlx5_ifc_qp_2err_out_bits { 6107 u8 status[0x8]; 6108 u8 reserved_at_8[0x18]; 6109 6110 u8 syndrome[0x20]; 6111 6112 u8 reserved_at_40[0x40]; 6113 }; 6114 6115 struct mlx5_ifc_qp_2err_in_bits { 6116 u8 opcode[0x10]; 6117 u8 uid[0x10]; 6118 6119 u8 reserved_at_20[0x10]; 6120 u8 op_mod[0x10]; 6121 6122 u8 reserved_at_40[0x8]; 6123 u8 qpn[0x18]; 6124 6125 u8 reserved_at_60[0x20]; 6126 }; 6127 6128 struct mlx5_ifc_page_fault_resume_out_bits { 6129 u8 status[0x8]; 6130 u8 reserved_at_8[0x18]; 6131 6132 u8 syndrome[0x20]; 6133 6134 u8 reserved_at_40[0x40]; 6135 }; 6136 6137 struct mlx5_ifc_page_fault_resume_in_bits { 6138 u8 opcode[0x10]; 6139 u8 reserved_at_10[0x10]; 6140 6141 u8 reserved_at_20[0x10]; 6142 u8 op_mod[0x10]; 6143 6144 u8 error[0x1]; 6145 u8 reserved_at_41[0x4]; 6146 u8 page_fault_type[0x3]; 6147 u8 wq_number[0x18]; 6148 6149 u8 reserved_at_60[0x8]; 6150 u8 token[0x18]; 6151 }; 6152 6153 struct mlx5_ifc_nop_out_bits { 6154 u8 status[0x8]; 6155 u8 reserved_at_8[0x18]; 6156 6157 u8 syndrome[0x20]; 6158 6159 u8 reserved_at_40[0x40]; 6160 }; 6161 6162 struct mlx5_ifc_nop_in_bits { 6163 u8 opcode[0x10]; 6164 u8 reserved_at_10[0x10]; 6165 6166 u8 reserved_at_20[0x10]; 6167 u8 op_mod[0x10]; 6168 6169 u8 reserved_at_40[0x40]; 6170 }; 6171 6172 struct mlx5_ifc_modify_vport_state_out_bits { 6173 u8 status[0x8]; 6174 u8 reserved_at_8[0x18]; 6175 6176 u8 syndrome[0x20]; 6177 6178 u8 reserved_at_40[0x40]; 6179 }; 6180 6181 struct mlx5_ifc_modify_vport_state_in_bits { 6182 u8 opcode[0x10]; 6183 u8 reserved_at_10[0x10]; 6184 6185 u8 reserved_at_20[0x10]; 6186 u8 op_mod[0x10]; 6187 6188 u8 other_vport[0x1]; 6189 u8 reserved_at_41[0xf]; 6190 u8 vport_number[0x10]; 6191 6192 u8 reserved_at_60[0x18]; 6193 u8 admin_state[0x4]; 6194 u8 reserved_at_7c[0x4]; 6195 }; 6196 6197 struct mlx5_ifc_modify_tis_out_bits { 6198 u8 status[0x8]; 6199 u8 reserved_at_8[0x18]; 6200 6201 u8 syndrome[0x20]; 6202 6203 u8 reserved_at_40[0x40]; 6204 }; 6205 6206 struct mlx5_ifc_modify_tis_bitmask_bits { 6207 u8 reserved_at_0[0x20]; 6208 6209 u8 reserved_at_20[0x1d]; 6210 u8 lag_tx_port_affinity[0x1]; 6211 u8 strict_lag_tx_port_affinity[0x1]; 6212 u8 prio[0x1]; 6213 }; 6214 6215 struct mlx5_ifc_modify_tis_in_bits { 6216 u8 opcode[0x10]; 6217 u8 uid[0x10]; 6218 6219 u8 reserved_at_20[0x10]; 6220 u8 op_mod[0x10]; 6221 6222 u8 reserved_at_40[0x8]; 6223 u8 tisn[0x18]; 6224 6225 u8 reserved_at_60[0x20]; 6226 6227 struct mlx5_ifc_modify_tis_bitmask_bits bitmask; 6228 6229 u8 reserved_at_c0[0x40]; 6230 6231 struct mlx5_ifc_tisc_bits ctx; 6232 }; 6233 6234 struct mlx5_ifc_modify_tir_bitmask_bits { 6235 u8 reserved_at_0[0x20]; 6236 6237 u8 reserved_at_20[0x1b]; 6238 u8 self_lb_en[0x1]; 6239 u8 reserved_at_3c[0x1]; 6240 u8 hash[0x1]; 6241 u8 reserved_at_3e[0x1]; 6242 u8 lro[0x1]; 6243 }; 6244 6245 struct mlx5_ifc_modify_tir_out_bits { 6246 u8 status[0x8]; 6247 u8 reserved_at_8[0x18]; 6248 6249 u8 syndrome[0x20]; 6250 6251 u8 reserved_at_40[0x40]; 6252 }; 6253 6254 struct mlx5_ifc_modify_tir_in_bits { 6255 u8 opcode[0x10]; 6256 u8 uid[0x10]; 6257 6258 u8 reserved_at_20[0x10]; 6259 u8 op_mod[0x10]; 6260 6261 u8 reserved_at_40[0x8]; 6262 u8 tirn[0x18]; 6263 6264 u8 reserved_at_60[0x20]; 6265 6266 struct mlx5_ifc_modify_tir_bitmask_bits bitmask; 6267 6268 u8 reserved_at_c0[0x40]; 6269 6270 struct mlx5_ifc_tirc_bits ctx; 6271 }; 6272 6273 struct mlx5_ifc_modify_sq_out_bits { 6274 u8 status[0x8]; 6275 u8 reserved_at_8[0x18]; 6276 6277 u8 syndrome[0x20]; 6278 6279 u8 reserved_at_40[0x40]; 6280 }; 6281 6282 struct mlx5_ifc_modify_sq_in_bits { 6283 u8 opcode[0x10]; 6284 u8 uid[0x10]; 6285 6286 u8 reserved_at_20[0x10]; 6287 u8 op_mod[0x10]; 6288 6289 u8 sq_state[0x4]; 6290 u8 reserved_at_44[0x4]; 6291 u8 sqn[0x18]; 6292 6293 u8 reserved_at_60[0x20]; 6294 6295 u8 modify_bitmask[0x40]; 6296 6297 u8 reserved_at_c0[0x40]; 6298 6299 struct mlx5_ifc_sqc_bits ctx; 6300 }; 6301 6302 struct mlx5_ifc_modify_scheduling_element_out_bits { 6303 u8 status[0x8]; 6304 u8 reserved_at_8[0x18]; 6305 6306 u8 syndrome[0x20]; 6307 6308 u8 reserved_at_40[0x1c0]; 6309 }; 6310 6311 enum { 6312 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1, 6313 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2, 6314 }; 6315 6316 struct mlx5_ifc_modify_scheduling_element_in_bits { 6317 u8 opcode[0x10]; 6318 u8 reserved_at_10[0x10]; 6319 6320 u8 reserved_at_20[0x10]; 6321 u8 op_mod[0x10]; 6322 6323 u8 scheduling_hierarchy[0x8]; 6324 u8 reserved_at_48[0x18]; 6325 6326 u8 scheduling_element_id[0x20]; 6327 6328 u8 reserved_at_80[0x20]; 6329 6330 u8 modify_bitmask[0x20]; 6331 6332 u8 reserved_at_c0[0x40]; 6333 6334 struct mlx5_ifc_scheduling_context_bits scheduling_context; 6335 6336 u8 reserved_at_300[0x100]; 6337 }; 6338 6339 struct mlx5_ifc_modify_rqt_out_bits { 6340 u8 status[0x8]; 6341 u8 reserved_at_8[0x18]; 6342 6343 u8 syndrome[0x20]; 6344 6345 u8 reserved_at_40[0x40]; 6346 }; 6347 6348 struct mlx5_ifc_rqt_bitmask_bits { 6349 u8 reserved_at_0[0x20]; 6350 6351 u8 reserved_at_20[0x1f]; 6352 u8 rqn_list[0x1]; 6353 }; 6354 6355 struct mlx5_ifc_modify_rqt_in_bits { 6356 u8 opcode[0x10]; 6357 u8 uid[0x10]; 6358 6359 u8 reserved_at_20[0x10]; 6360 u8 op_mod[0x10]; 6361 6362 u8 reserved_at_40[0x8]; 6363 u8 rqtn[0x18]; 6364 6365 u8 reserved_at_60[0x20]; 6366 6367 struct mlx5_ifc_rqt_bitmask_bits bitmask; 6368 6369 u8 reserved_at_c0[0x40]; 6370 6371 struct mlx5_ifc_rqtc_bits ctx; 6372 }; 6373 6374 struct mlx5_ifc_modify_rq_out_bits { 6375 u8 status[0x8]; 6376 u8 reserved_at_8[0x18]; 6377 6378 u8 syndrome[0x20]; 6379 6380 u8 reserved_at_40[0x40]; 6381 }; 6382 6383 enum { 6384 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1, 6385 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2, 6386 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3, 6387 }; 6388 6389 struct mlx5_ifc_modify_rq_in_bits { 6390 u8 opcode[0x10]; 6391 u8 uid[0x10]; 6392 6393 u8 reserved_at_20[0x10]; 6394 u8 op_mod[0x10]; 6395 6396 u8 rq_state[0x4]; 6397 u8 reserved_at_44[0x4]; 6398 u8 rqn[0x18]; 6399 6400 u8 reserved_at_60[0x20]; 6401 6402 u8 modify_bitmask[0x40]; 6403 6404 u8 reserved_at_c0[0x40]; 6405 6406 struct mlx5_ifc_rqc_bits ctx; 6407 }; 6408 6409 struct mlx5_ifc_modify_rmp_out_bits { 6410 u8 status[0x8]; 6411 u8 reserved_at_8[0x18]; 6412 6413 u8 syndrome[0x20]; 6414 6415 u8 reserved_at_40[0x40]; 6416 }; 6417 6418 struct mlx5_ifc_rmp_bitmask_bits { 6419 u8 reserved_at_0[0x20]; 6420 6421 u8 reserved_at_20[0x1f]; 6422 u8 lwm[0x1]; 6423 }; 6424 6425 struct mlx5_ifc_modify_rmp_in_bits { 6426 u8 opcode[0x10]; 6427 u8 uid[0x10]; 6428 6429 u8 reserved_at_20[0x10]; 6430 u8 op_mod[0x10]; 6431 6432 u8 rmp_state[0x4]; 6433 u8 reserved_at_44[0x4]; 6434 u8 rmpn[0x18]; 6435 6436 u8 reserved_at_60[0x20]; 6437 6438 struct mlx5_ifc_rmp_bitmask_bits bitmask; 6439 6440 u8 reserved_at_c0[0x40]; 6441 6442 struct mlx5_ifc_rmpc_bits ctx; 6443 }; 6444 6445 struct mlx5_ifc_modify_nic_vport_context_out_bits { 6446 u8 status[0x8]; 6447 u8 reserved_at_8[0x18]; 6448 6449 u8 syndrome[0x20]; 6450 6451 u8 reserved_at_40[0x40]; 6452 }; 6453 6454 struct mlx5_ifc_modify_nic_vport_field_select_bits { 6455 u8 reserved_at_0[0x12]; 6456 u8 affiliation[0x1]; 6457 u8 reserved_at_13[0x1]; 6458 u8 disable_uc_local_lb[0x1]; 6459 u8 disable_mc_local_lb[0x1]; 6460 u8 node_guid[0x1]; 6461 u8 port_guid[0x1]; 6462 u8 min_inline[0x1]; 6463 u8 mtu[0x1]; 6464 u8 change_event[0x1]; 6465 u8 promisc[0x1]; 6466 u8 permanent_address[0x1]; 6467 u8 addresses_list[0x1]; 6468 u8 roce_en[0x1]; 6469 u8 reserved_at_1f[0x1]; 6470 }; 6471 6472 struct mlx5_ifc_modify_nic_vport_context_in_bits { 6473 u8 opcode[0x10]; 6474 u8 reserved_at_10[0x10]; 6475 6476 u8 reserved_at_20[0x10]; 6477 u8 op_mod[0x10]; 6478 6479 u8 other_vport[0x1]; 6480 u8 reserved_at_41[0xf]; 6481 u8 vport_number[0x10]; 6482 6483 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select; 6484 6485 u8 reserved_at_80[0x780]; 6486 6487 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 6488 }; 6489 6490 struct mlx5_ifc_modify_hca_vport_context_out_bits { 6491 u8 status[0x8]; 6492 u8 reserved_at_8[0x18]; 6493 6494 u8 syndrome[0x20]; 6495 6496 u8 reserved_at_40[0x40]; 6497 }; 6498 6499 struct mlx5_ifc_modify_hca_vport_context_in_bits { 6500 u8 opcode[0x10]; 6501 u8 reserved_at_10[0x10]; 6502 6503 u8 reserved_at_20[0x10]; 6504 u8 op_mod[0x10]; 6505 6506 u8 other_vport[0x1]; 6507 u8 reserved_at_41[0xb]; 6508 u8 port_num[0x4]; 6509 u8 vport_number[0x10]; 6510 6511 u8 reserved_at_60[0x20]; 6512 6513 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 6514 }; 6515 6516 struct mlx5_ifc_modify_cq_out_bits { 6517 u8 status[0x8]; 6518 u8 reserved_at_8[0x18]; 6519 6520 u8 syndrome[0x20]; 6521 6522 u8 reserved_at_40[0x40]; 6523 }; 6524 6525 enum { 6526 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0, 6527 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1, 6528 }; 6529 6530 struct mlx5_ifc_modify_cq_in_bits { 6531 u8 opcode[0x10]; 6532 u8 uid[0x10]; 6533 6534 u8 reserved_at_20[0x10]; 6535 u8 op_mod[0x10]; 6536 6537 u8 reserved_at_40[0x8]; 6538 u8 cqn[0x18]; 6539 6540 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select; 6541 6542 struct mlx5_ifc_cqc_bits cq_context; 6543 6544 u8 reserved_at_280[0x60]; 6545 6546 u8 cq_umem_valid[0x1]; 6547 u8 reserved_at_2e1[0x1f]; 6548 6549 u8 reserved_at_300[0x580]; 6550 6551 u8 pas[][0x40]; 6552 }; 6553 6554 struct mlx5_ifc_modify_cong_status_out_bits { 6555 u8 status[0x8]; 6556 u8 reserved_at_8[0x18]; 6557 6558 u8 syndrome[0x20]; 6559 6560 u8 reserved_at_40[0x40]; 6561 }; 6562 6563 struct mlx5_ifc_modify_cong_status_in_bits { 6564 u8 opcode[0x10]; 6565 u8 reserved_at_10[0x10]; 6566 6567 u8 reserved_at_20[0x10]; 6568 u8 op_mod[0x10]; 6569 6570 u8 reserved_at_40[0x18]; 6571 u8 priority[0x4]; 6572 u8 cong_protocol[0x4]; 6573 6574 u8 enable[0x1]; 6575 u8 tag_enable[0x1]; 6576 u8 reserved_at_62[0x1e]; 6577 }; 6578 6579 struct mlx5_ifc_modify_cong_params_out_bits { 6580 u8 status[0x8]; 6581 u8 reserved_at_8[0x18]; 6582 6583 u8 syndrome[0x20]; 6584 6585 u8 reserved_at_40[0x40]; 6586 }; 6587 6588 struct mlx5_ifc_modify_cong_params_in_bits { 6589 u8 opcode[0x10]; 6590 u8 reserved_at_10[0x10]; 6591 6592 u8 reserved_at_20[0x10]; 6593 u8 op_mod[0x10]; 6594 6595 u8 reserved_at_40[0x1c]; 6596 u8 cong_protocol[0x4]; 6597 6598 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select; 6599 6600 u8 reserved_at_80[0x80]; 6601 6602 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 6603 }; 6604 6605 struct mlx5_ifc_manage_pages_out_bits { 6606 u8 status[0x8]; 6607 u8 reserved_at_8[0x18]; 6608 6609 u8 syndrome[0x20]; 6610 6611 u8 output_num_entries[0x20]; 6612 6613 u8 reserved_at_60[0x20]; 6614 6615 u8 pas[][0x40]; 6616 }; 6617 6618 enum { 6619 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL = 0x0, 6620 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS = 0x1, 6621 MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES = 0x2, 6622 }; 6623 6624 struct mlx5_ifc_manage_pages_in_bits { 6625 u8 opcode[0x10]; 6626 u8 reserved_at_10[0x10]; 6627 6628 u8 reserved_at_20[0x10]; 6629 u8 op_mod[0x10]; 6630 6631 u8 embedded_cpu_function[0x1]; 6632 u8 reserved_at_41[0xf]; 6633 u8 function_id[0x10]; 6634 6635 u8 input_num_entries[0x20]; 6636 6637 u8 pas[][0x40]; 6638 }; 6639 6640 struct mlx5_ifc_mad_ifc_out_bits { 6641 u8 status[0x8]; 6642 u8 reserved_at_8[0x18]; 6643 6644 u8 syndrome[0x20]; 6645 6646 u8 reserved_at_40[0x40]; 6647 6648 u8 response_mad_packet[256][0x8]; 6649 }; 6650 6651 struct mlx5_ifc_mad_ifc_in_bits { 6652 u8 opcode[0x10]; 6653 u8 reserved_at_10[0x10]; 6654 6655 u8 reserved_at_20[0x10]; 6656 u8 op_mod[0x10]; 6657 6658 u8 remote_lid[0x10]; 6659 u8 reserved_at_50[0x8]; 6660 u8 port[0x8]; 6661 6662 u8 reserved_at_60[0x20]; 6663 6664 u8 mad[256][0x8]; 6665 }; 6666 6667 struct mlx5_ifc_init_hca_out_bits { 6668 u8 status[0x8]; 6669 u8 reserved_at_8[0x18]; 6670 6671 u8 syndrome[0x20]; 6672 6673 u8 reserved_at_40[0x40]; 6674 }; 6675 6676 struct mlx5_ifc_init_hca_in_bits { 6677 u8 opcode[0x10]; 6678 u8 reserved_at_10[0x10]; 6679 6680 u8 reserved_at_20[0x10]; 6681 u8 op_mod[0x10]; 6682 6683 u8 reserved_at_40[0x40]; 6684 u8 sw_owner_id[4][0x20]; 6685 }; 6686 6687 struct mlx5_ifc_init2rtr_qp_out_bits { 6688 u8 status[0x8]; 6689 u8 reserved_at_8[0x18]; 6690 6691 u8 syndrome[0x20]; 6692 6693 u8 reserved_at_40[0x20]; 6694 u8 ece[0x20]; 6695 }; 6696 6697 struct mlx5_ifc_init2rtr_qp_in_bits { 6698 u8 opcode[0x10]; 6699 u8 uid[0x10]; 6700 6701 u8 reserved_at_20[0x10]; 6702 u8 op_mod[0x10]; 6703 6704 u8 reserved_at_40[0x8]; 6705 u8 qpn[0x18]; 6706 6707 u8 reserved_at_60[0x20]; 6708 6709 u8 opt_param_mask[0x20]; 6710 6711 u8 ece[0x20]; 6712 6713 struct mlx5_ifc_qpc_bits qpc; 6714 6715 u8 reserved_at_800[0x80]; 6716 }; 6717 6718 struct mlx5_ifc_init2init_qp_out_bits { 6719 u8 status[0x8]; 6720 u8 reserved_at_8[0x18]; 6721 6722 u8 syndrome[0x20]; 6723 6724 u8 reserved_at_40[0x20]; 6725 u8 ece[0x20]; 6726 }; 6727 6728 struct mlx5_ifc_init2init_qp_in_bits { 6729 u8 opcode[0x10]; 6730 u8 uid[0x10]; 6731 6732 u8 reserved_at_20[0x10]; 6733 u8 op_mod[0x10]; 6734 6735 u8 reserved_at_40[0x8]; 6736 u8 qpn[0x18]; 6737 6738 u8 reserved_at_60[0x20]; 6739 6740 u8 opt_param_mask[0x20]; 6741 6742 u8 ece[0x20]; 6743 6744 struct mlx5_ifc_qpc_bits qpc; 6745 6746 u8 reserved_at_800[0x80]; 6747 }; 6748 6749 struct mlx5_ifc_get_dropped_packet_log_out_bits { 6750 u8 status[0x8]; 6751 u8 reserved_at_8[0x18]; 6752 6753 u8 syndrome[0x20]; 6754 6755 u8 reserved_at_40[0x40]; 6756 6757 u8 packet_headers_log[128][0x8]; 6758 6759 u8 packet_syndrome[64][0x8]; 6760 }; 6761 6762 struct mlx5_ifc_get_dropped_packet_log_in_bits { 6763 u8 opcode[0x10]; 6764 u8 reserved_at_10[0x10]; 6765 6766 u8 reserved_at_20[0x10]; 6767 u8 op_mod[0x10]; 6768 6769 u8 reserved_at_40[0x40]; 6770 }; 6771 6772 struct mlx5_ifc_gen_eqe_in_bits { 6773 u8 opcode[0x10]; 6774 u8 reserved_at_10[0x10]; 6775 6776 u8 reserved_at_20[0x10]; 6777 u8 op_mod[0x10]; 6778 6779 u8 reserved_at_40[0x18]; 6780 u8 eq_number[0x8]; 6781 6782 u8 reserved_at_60[0x20]; 6783 6784 u8 eqe[64][0x8]; 6785 }; 6786 6787 struct mlx5_ifc_gen_eq_out_bits { 6788 u8 status[0x8]; 6789 u8 reserved_at_8[0x18]; 6790 6791 u8 syndrome[0x20]; 6792 6793 u8 reserved_at_40[0x40]; 6794 }; 6795 6796 struct mlx5_ifc_enable_hca_out_bits { 6797 u8 status[0x8]; 6798 u8 reserved_at_8[0x18]; 6799 6800 u8 syndrome[0x20]; 6801 6802 u8 reserved_at_40[0x20]; 6803 }; 6804 6805 struct mlx5_ifc_enable_hca_in_bits { 6806 u8 opcode[0x10]; 6807 u8 reserved_at_10[0x10]; 6808 6809 u8 reserved_at_20[0x10]; 6810 u8 op_mod[0x10]; 6811 6812 u8 embedded_cpu_function[0x1]; 6813 u8 reserved_at_41[0xf]; 6814 u8 function_id[0x10]; 6815 6816 u8 reserved_at_60[0x20]; 6817 }; 6818 6819 struct mlx5_ifc_drain_dct_out_bits { 6820 u8 status[0x8]; 6821 u8 reserved_at_8[0x18]; 6822 6823 u8 syndrome[0x20]; 6824 6825 u8 reserved_at_40[0x40]; 6826 }; 6827 6828 struct mlx5_ifc_drain_dct_in_bits { 6829 u8 opcode[0x10]; 6830 u8 uid[0x10]; 6831 6832 u8 reserved_at_20[0x10]; 6833 u8 op_mod[0x10]; 6834 6835 u8 reserved_at_40[0x8]; 6836 u8 dctn[0x18]; 6837 6838 u8 reserved_at_60[0x20]; 6839 }; 6840 6841 struct mlx5_ifc_disable_hca_out_bits { 6842 u8 status[0x8]; 6843 u8 reserved_at_8[0x18]; 6844 6845 u8 syndrome[0x20]; 6846 6847 u8 reserved_at_40[0x20]; 6848 }; 6849 6850 struct mlx5_ifc_disable_hca_in_bits { 6851 u8 opcode[0x10]; 6852 u8 reserved_at_10[0x10]; 6853 6854 u8 reserved_at_20[0x10]; 6855 u8 op_mod[0x10]; 6856 6857 u8 embedded_cpu_function[0x1]; 6858 u8 reserved_at_41[0xf]; 6859 u8 function_id[0x10]; 6860 6861 u8 reserved_at_60[0x20]; 6862 }; 6863 6864 struct mlx5_ifc_detach_from_mcg_out_bits { 6865 u8 status[0x8]; 6866 u8 reserved_at_8[0x18]; 6867 6868 u8 syndrome[0x20]; 6869 6870 u8 reserved_at_40[0x40]; 6871 }; 6872 6873 struct mlx5_ifc_detach_from_mcg_in_bits { 6874 u8 opcode[0x10]; 6875 u8 uid[0x10]; 6876 6877 u8 reserved_at_20[0x10]; 6878 u8 op_mod[0x10]; 6879 6880 u8 reserved_at_40[0x8]; 6881 u8 qpn[0x18]; 6882 6883 u8 reserved_at_60[0x20]; 6884 6885 u8 multicast_gid[16][0x8]; 6886 }; 6887 6888 struct mlx5_ifc_destroy_xrq_out_bits { 6889 u8 status[0x8]; 6890 u8 reserved_at_8[0x18]; 6891 6892 u8 syndrome[0x20]; 6893 6894 u8 reserved_at_40[0x40]; 6895 }; 6896 6897 struct mlx5_ifc_destroy_xrq_in_bits { 6898 u8 opcode[0x10]; 6899 u8 uid[0x10]; 6900 6901 u8 reserved_at_20[0x10]; 6902 u8 op_mod[0x10]; 6903 6904 u8 reserved_at_40[0x8]; 6905 u8 xrqn[0x18]; 6906 6907 u8 reserved_at_60[0x20]; 6908 }; 6909 6910 struct mlx5_ifc_destroy_xrc_srq_out_bits { 6911 u8 status[0x8]; 6912 u8 reserved_at_8[0x18]; 6913 6914 u8 syndrome[0x20]; 6915 6916 u8 reserved_at_40[0x40]; 6917 }; 6918 6919 struct mlx5_ifc_destroy_xrc_srq_in_bits { 6920 u8 opcode[0x10]; 6921 u8 uid[0x10]; 6922 6923 u8 reserved_at_20[0x10]; 6924 u8 op_mod[0x10]; 6925 6926 u8 reserved_at_40[0x8]; 6927 u8 xrc_srqn[0x18]; 6928 6929 u8 reserved_at_60[0x20]; 6930 }; 6931 6932 struct mlx5_ifc_destroy_tis_out_bits { 6933 u8 status[0x8]; 6934 u8 reserved_at_8[0x18]; 6935 6936 u8 syndrome[0x20]; 6937 6938 u8 reserved_at_40[0x40]; 6939 }; 6940 6941 struct mlx5_ifc_destroy_tis_in_bits { 6942 u8 opcode[0x10]; 6943 u8 uid[0x10]; 6944 6945 u8 reserved_at_20[0x10]; 6946 u8 op_mod[0x10]; 6947 6948 u8 reserved_at_40[0x8]; 6949 u8 tisn[0x18]; 6950 6951 u8 reserved_at_60[0x20]; 6952 }; 6953 6954 struct mlx5_ifc_destroy_tir_out_bits { 6955 u8 status[0x8]; 6956 u8 reserved_at_8[0x18]; 6957 6958 u8 syndrome[0x20]; 6959 6960 u8 reserved_at_40[0x40]; 6961 }; 6962 6963 struct mlx5_ifc_destroy_tir_in_bits { 6964 u8 opcode[0x10]; 6965 u8 uid[0x10]; 6966 6967 u8 reserved_at_20[0x10]; 6968 u8 op_mod[0x10]; 6969 6970 u8 reserved_at_40[0x8]; 6971 u8 tirn[0x18]; 6972 6973 u8 reserved_at_60[0x20]; 6974 }; 6975 6976 struct mlx5_ifc_destroy_srq_out_bits { 6977 u8 status[0x8]; 6978 u8 reserved_at_8[0x18]; 6979 6980 u8 syndrome[0x20]; 6981 6982 u8 reserved_at_40[0x40]; 6983 }; 6984 6985 struct mlx5_ifc_destroy_srq_in_bits { 6986 u8 opcode[0x10]; 6987 u8 uid[0x10]; 6988 6989 u8 reserved_at_20[0x10]; 6990 u8 op_mod[0x10]; 6991 6992 u8 reserved_at_40[0x8]; 6993 u8 srqn[0x18]; 6994 6995 u8 reserved_at_60[0x20]; 6996 }; 6997 6998 struct mlx5_ifc_destroy_sq_out_bits { 6999 u8 status[0x8]; 7000 u8 reserved_at_8[0x18]; 7001 7002 u8 syndrome[0x20]; 7003 7004 u8 reserved_at_40[0x40]; 7005 }; 7006 7007 struct mlx5_ifc_destroy_sq_in_bits { 7008 u8 opcode[0x10]; 7009 u8 uid[0x10]; 7010 7011 u8 reserved_at_20[0x10]; 7012 u8 op_mod[0x10]; 7013 7014 u8 reserved_at_40[0x8]; 7015 u8 sqn[0x18]; 7016 7017 u8 reserved_at_60[0x20]; 7018 }; 7019 7020 struct mlx5_ifc_destroy_scheduling_element_out_bits { 7021 u8 status[0x8]; 7022 u8 reserved_at_8[0x18]; 7023 7024 u8 syndrome[0x20]; 7025 7026 u8 reserved_at_40[0x1c0]; 7027 }; 7028 7029 struct mlx5_ifc_destroy_scheduling_element_in_bits { 7030 u8 opcode[0x10]; 7031 u8 reserved_at_10[0x10]; 7032 7033 u8 reserved_at_20[0x10]; 7034 u8 op_mod[0x10]; 7035 7036 u8 scheduling_hierarchy[0x8]; 7037 u8 reserved_at_48[0x18]; 7038 7039 u8 scheduling_element_id[0x20]; 7040 7041 u8 reserved_at_80[0x180]; 7042 }; 7043 7044 struct mlx5_ifc_destroy_rqt_out_bits { 7045 u8 status[0x8]; 7046 u8 reserved_at_8[0x18]; 7047 7048 u8 syndrome[0x20]; 7049 7050 u8 reserved_at_40[0x40]; 7051 }; 7052 7053 struct mlx5_ifc_destroy_rqt_in_bits { 7054 u8 opcode[0x10]; 7055 u8 uid[0x10]; 7056 7057 u8 reserved_at_20[0x10]; 7058 u8 op_mod[0x10]; 7059 7060 u8 reserved_at_40[0x8]; 7061 u8 rqtn[0x18]; 7062 7063 u8 reserved_at_60[0x20]; 7064 }; 7065 7066 struct mlx5_ifc_destroy_rq_out_bits { 7067 u8 status[0x8]; 7068 u8 reserved_at_8[0x18]; 7069 7070 u8 syndrome[0x20]; 7071 7072 u8 reserved_at_40[0x40]; 7073 }; 7074 7075 struct mlx5_ifc_destroy_rq_in_bits { 7076 u8 opcode[0x10]; 7077 u8 uid[0x10]; 7078 7079 u8 reserved_at_20[0x10]; 7080 u8 op_mod[0x10]; 7081 7082 u8 reserved_at_40[0x8]; 7083 u8 rqn[0x18]; 7084 7085 u8 reserved_at_60[0x20]; 7086 }; 7087 7088 struct mlx5_ifc_set_delay_drop_params_in_bits { 7089 u8 opcode[0x10]; 7090 u8 reserved_at_10[0x10]; 7091 7092 u8 reserved_at_20[0x10]; 7093 u8 op_mod[0x10]; 7094 7095 u8 reserved_at_40[0x20]; 7096 7097 u8 reserved_at_60[0x10]; 7098 u8 delay_drop_timeout[0x10]; 7099 }; 7100 7101 struct mlx5_ifc_set_delay_drop_params_out_bits { 7102 u8 status[0x8]; 7103 u8 reserved_at_8[0x18]; 7104 7105 u8 syndrome[0x20]; 7106 7107 u8 reserved_at_40[0x40]; 7108 }; 7109 7110 struct mlx5_ifc_destroy_rmp_out_bits { 7111 u8 status[0x8]; 7112 u8 reserved_at_8[0x18]; 7113 7114 u8 syndrome[0x20]; 7115 7116 u8 reserved_at_40[0x40]; 7117 }; 7118 7119 struct mlx5_ifc_destroy_rmp_in_bits { 7120 u8 opcode[0x10]; 7121 u8 uid[0x10]; 7122 7123 u8 reserved_at_20[0x10]; 7124 u8 op_mod[0x10]; 7125 7126 u8 reserved_at_40[0x8]; 7127 u8 rmpn[0x18]; 7128 7129 u8 reserved_at_60[0x20]; 7130 }; 7131 7132 struct mlx5_ifc_destroy_qp_out_bits { 7133 u8 status[0x8]; 7134 u8 reserved_at_8[0x18]; 7135 7136 u8 syndrome[0x20]; 7137 7138 u8 reserved_at_40[0x40]; 7139 }; 7140 7141 struct mlx5_ifc_destroy_qp_in_bits { 7142 u8 opcode[0x10]; 7143 u8 uid[0x10]; 7144 7145 u8 reserved_at_20[0x10]; 7146 u8 op_mod[0x10]; 7147 7148 u8 reserved_at_40[0x8]; 7149 u8 qpn[0x18]; 7150 7151 u8 reserved_at_60[0x20]; 7152 }; 7153 7154 struct mlx5_ifc_destroy_psv_out_bits { 7155 u8 status[0x8]; 7156 u8 reserved_at_8[0x18]; 7157 7158 u8 syndrome[0x20]; 7159 7160 u8 reserved_at_40[0x40]; 7161 }; 7162 7163 struct mlx5_ifc_destroy_psv_in_bits { 7164 u8 opcode[0x10]; 7165 u8 reserved_at_10[0x10]; 7166 7167 u8 reserved_at_20[0x10]; 7168 u8 op_mod[0x10]; 7169 7170 u8 reserved_at_40[0x8]; 7171 u8 psvn[0x18]; 7172 7173 u8 reserved_at_60[0x20]; 7174 }; 7175 7176 struct mlx5_ifc_destroy_mkey_out_bits { 7177 u8 status[0x8]; 7178 u8 reserved_at_8[0x18]; 7179 7180 u8 syndrome[0x20]; 7181 7182 u8 reserved_at_40[0x40]; 7183 }; 7184 7185 struct mlx5_ifc_destroy_mkey_in_bits { 7186 u8 opcode[0x10]; 7187 u8 uid[0x10]; 7188 7189 u8 reserved_at_20[0x10]; 7190 u8 op_mod[0x10]; 7191 7192 u8 reserved_at_40[0x8]; 7193 u8 mkey_index[0x18]; 7194 7195 u8 reserved_at_60[0x20]; 7196 }; 7197 7198 struct mlx5_ifc_destroy_flow_table_out_bits { 7199 u8 status[0x8]; 7200 u8 reserved_at_8[0x18]; 7201 7202 u8 syndrome[0x20]; 7203 7204 u8 reserved_at_40[0x40]; 7205 }; 7206 7207 struct mlx5_ifc_destroy_flow_table_in_bits { 7208 u8 opcode[0x10]; 7209 u8 reserved_at_10[0x10]; 7210 7211 u8 reserved_at_20[0x10]; 7212 u8 op_mod[0x10]; 7213 7214 u8 other_vport[0x1]; 7215 u8 reserved_at_41[0xf]; 7216 u8 vport_number[0x10]; 7217 7218 u8 reserved_at_60[0x20]; 7219 7220 u8 table_type[0x8]; 7221 u8 reserved_at_88[0x18]; 7222 7223 u8 reserved_at_a0[0x8]; 7224 u8 table_id[0x18]; 7225 7226 u8 reserved_at_c0[0x140]; 7227 }; 7228 7229 struct mlx5_ifc_destroy_flow_group_out_bits { 7230 u8 status[0x8]; 7231 u8 reserved_at_8[0x18]; 7232 7233 u8 syndrome[0x20]; 7234 7235 u8 reserved_at_40[0x40]; 7236 }; 7237 7238 struct mlx5_ifc_destroy_flow_group_in_bits { 7239 u8 opcode[0x10]; 7240 u8 reserved_at_10[0x10]; 7241 7242 u8 reserved_at_20[0x10]; 7243 u8 op_mod[0x10]; 7244 7245 u8 other_vport[0x1]; 7246 u8 reserved_at_41[0xf]; 7247 u8 vport_number[0x10]; 7248 7249 u8 reserved_at_60[0x20]; 7250 7251 u8 table_type[0x8]; 7252 u8 reserved_at_88[0x18]; 7253 7254 u8 reserved_at_a0[0x8]; 7255 u8 table_id[0x18]; 7256 7257 u8 group_id[0x20]; 7258 7259 u8 reserved_at_e0[0x120]; 7260 }; 7261 7262 struct mlx5_ifc_destroy_eq_out_bits { 7263 u8 status[0x8]; 7264 u8 reserved_at_8[0x18]; 7265 7266 u8 syndrome[0x20]; 7267 7268 u8 reserved_at_40[0x40]; 7269 }; 7270 7271 struct mlx5_ifc_destroy_eq_in_bits { 7272 u8 opcode[0x10]; 7273 u8 reserved_at_10[0x10]; 7274 7275 u8 reserved_at_20[0x10]; 7276 u8 op_mod[0x10]; 7277 7278 u8 reserved_at_40[0x18]; 7279 u8 eq_number[0x8]; 7280 7281 u8 reserved_at_60[0x20]; 7282 }; 7283 7284 struct mlx5_ifc_destroy_dct_out_bits { 7285 u8 status[0x8]; 7286 u8 reserved_at_8[0x18]; 7287 7288 u8 syndrome[0x20]; 7289 7290 u8 reserved_at_40[0x40]; 7291 }; 7292 7293 struct mlx5_ifc_destroy_dct_in_bits { 7294 u8 opcode[0x10]; 7295 u8 uid[0x10]; 7296 7297 u8 reserved_at_20[0x10]; 7298 u8 op_mod[0x10]; 7299 7300 u8 reserved_at_40[0x8]; 7301 u8 dctn[0x18]; 7302 7303 u8 reserved_at_60[0x20]; 7304 }; 7305 7306 struct mlx5_ifc_destroy_cq_out_bits { 7307 u8 status[0x8]; 7308 u8 reserved_at_8[0x18]; 7309 7310 u8 syndrome[0x20]; 7311 7312 u8 reserved_at_40[0x40]; 7313 }; 7314 7315 struct mlx5_ifc_destroy_cq_in_bits { 7316 u8 opcode[0x10]; 7317 u8 uid[0x10]; 7318 7319 u8 reserved_at_20[0x10]; 7320 u8 op_mod[0x10]; 7321 7322 u8 reserved_at_40[0x8]; 7323 u8 cqn[0x18]; 7324 7325 u8 reserved_at_60[0x20]; 7326 }; 7327 7328 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits { 7329 u8 status[0x8]; 7330 u8 reserved_at_8[0x18]; 7331 7332 u8 syndrome[0x20]; 7333 7334 u8 reserved_at_40[0x40]; 7335 }; 7336 7337 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits { 7338 u8 opcode[0x10]; 7339 u8 reserved_at_10[0x10]; 7340 7341 u8 reserved_at_20[0x10]; 7342 u8 op_mod[0x10]; 7343 7344 u8 reserved_at_40[0x20]; 7345 7346 u8 reserved_at_60[0x10]; 7347 u8 vxlan_udp_port[0x10]; 7348 }; 7349 7350 struct mlx5_ifc_delete_l2_table_entry_out_bits { 7351 u8 status[0x8]; 7352 u8 reserved_at_8[0x18]; 7353 7354 u8 syndrome[0x20]; 7355 7356 u8 reserved_at_40[0x40]; 7357 }; 7358 7359 struct mlx5_ifc_delete_l2_table_entry_in_bits { 7360 u8 opcode[0x10]; 7361 u8 reserved_at_10[0x10]; 7362 7363 u8 reserved_at_20[0x10]; 7364 u8 op_mod[0x10]; 7365 7366 u8 reserved_at_40[0x60]; 7367 7368 u8 reserved_at_a0[0x8]; 7369 u8 table_index[0x18]; 7370 7371 u8 reserved_at_c0[0x140]; 7372 }; 7373 7374 struct mlx5_ifc_delete_fte_out_bits { 7375 u8 status[0x8]; 7376 u8 reserved_at_8[0x18]; 7377 7378 u8 syndrome[0x20]; 7379 7380 u8 reserved_at_40[0x40]; 7381 }; 7382 7383 struct mlx5_ifc_delete_fte_in_bits { 7384 u8 opcode[0x10]; 7385 u8 reserved_at_10[0x10]; 7386 7387 u8 reserved_at_20[0x10]; 7388 u8 op_mod[0x10]; 7389 7390 u8 other_vport[0x1]; 7391 u8 reserved_at_41[0xf]; 7392 u8 vport_number[0x10]; 7393 7394 u8 reserved_at_60[0x20]; 7395 7396 u8 table_type[0x8]; 7397 u8 reserved_at_88[0x18]; 7398 7399 u8 reserved_at_a0[0x8]; 7400 u8 table_id[0x18]; 7401 7402 u8 reserved_at_c0[0x40]; 7403 7404 u8 flow_index[0x20]; 7405 7406 u8 reserved_at_120[0xe0]; 7407 }; 7408 7409 struct mlx5_ifc_dealloc_xrcd_out_bits { 7410 u8 status[0x8]; 7411 u8 reserved_at_8[0x18]; 7412 7413 u8 syndrome[0x20]; 7414 7415 u8 reserved_at_40[0x40]; 7416 }; 7417 7418 struct mlx5_ifc_dealloc_xrcd_in_bits { 7419 u8 opcode[0x10]; 7420 u8 uid[0x10]; 7421 7422 u8 reserved_at_20[0x10]; 7423 u8 op_mod[0x10]; 7424 7425 u8 reserved_at_40[0x8]; 7426 u8 xrcd[0x18]; 7427 7428 u8 reserved_at_60[0x20]; 7429 }; 7430 7431 struct mlx5_ifc_dealloc_uar_out_bits { 7432 u8 status[0x8]; 7433 u8 reserved_at_8[0x18]; 7434 7435 u8 syndrome[0x20]; 7436 7437 u8 reserved_at_40[0x40]; 7438 }; 7439 7440 struct mlx5_ifc_dealloc_uar_in_bits { 7441 u8 opcode[0x10]; 7442 u8 reserved_at_10[0x10]; 7443 7444 u8 reserved_at_20[0x10]; 7445 u8 op_mod[0x10]; 7446 7447 u8 reserved_at_40[0x8]; 7448 u8 uar[0x18]; 7449 7450 u8 reserved_at_60[0x20]; 7451 }; 7452 7453 struct mlx5_ifc_dealloc_transport_domain_out_bits { 7454 u8 status[0x8]; 7455 u8 reserved_at_8[0x18]; 7456 7457 u8 syndrome[0x20]; 7458 7459 u8 reserved_at_40[0x40]; 7460 }; 7461 7462 struct mlx5_ifc_dealloc_transport_domain_in_bits { 7463 u8 opcode[0x10]; 7464 u8 uid[0x10]; 7465 7466 u8 reserved_at_20[0x10]; 7467 u8 op_mod[0x10]; 7468 7469 u8 reserved_at_40[0x8]; 7470 u8 transport_domain[0x18]; 7471 7472 u8 reserved_at_60[0x20]; 7473 }; 7474 7475 struct mlx5_ifc_dealloc_q_counter_out_bits { 7476 u8 status[0x8]; 7477 u8 reserved_at_8[0x18]; 7478 7479 u8 syndrome[0x20]; 7480 7481 u8 reserved_at_40[0x40]; 7482 }; 7483 7484 struct mlx5_ifc_dealloc_q_counter_in_bits { 7485 u8 opcode[0x10]; 7486 u8 reserved_at_10[0x10]; 7487 7488 u8 reserved_at_20[0x10]; 7489 u8 op_mod[0x10]; 7490 7491 u8 reserved_at_40[0x18]; 7492 u8 counter_set_id[0x8]; 7493 7494 u8 reserved_at_60[0x20]; 7495 }; 7496 7497 struct mlx5_ifc_dealloc_pd_out_bits { 7498 u8 status[0x8]; 7499 u8 reserved_at_8[0x18]; 7500 7501 u8 syndrome[0x20]; 7502 7503 u8 reserved_at_40[0x40]; 7504 }; 7505 7506 struct mlx5_ifc_dealloc_pd_in_bits { 7507 u8 opcode[0x10]; 7508 u8 uid[0x10]; 7509 7510 u8 reserved_at_20[0x10]; 7511 u8 op_mod[0x10]; 7512 7513 u8 reserved_at_40[0x8]; 7514 u8 pd[0x18]; 7515 7516 u8 reserved_at_60[0x20]; 7517 }; 7518 7519 struct mlx5_ifc_dealloc_flow_counter_out_bits { 7520 u8 status[0x8]; 7521 u8 reserved_at_8[0x18]; 7522 7523 u8 syndrome[0x20]; 7524 7525 u8 reserved_at_40[0x40]; 7526 }; 7527 7528 struct mlx5_ifc_dealloc_flow_counter_in_bits { 7529 u8 opcode[0x10]; 7530 u8 reserved_at_10[0x10]; 7531 7532 u8 reserved_at_20[0x10]; 7533 u8 op_mod[0x10]; 7534 7535 u8 flow_counter_id[0x20]; 7536 7537 u8 reserved_at_60[0x20]; 7538 }; 7539 7540 struct mlx5_ifc_create_xrq_out_bits { 7541 u8 status[0x8]; 7542 u8 reserved_at_8[0x18]; 7543 7544 u8 syndrome[0x20]; 7545 7546 u8 reserved_at_40[0x8]; 7547 u8 xrqn[0x18]; 7548 7549 u8 reserved_at_60[0x20]; 7550 }; 7551 7552 struct mlx5_ifc_create_xrq_in_bits { 7553 u8 opcode[0x10]; 7554 u8 uid[0x10]; 7555 7556 u8 reserved_at_20[0x10]; 7557 u8 op_mod[0x10]; 7558 7559 u8 reserved_at_40[0x40]; 7560 7561 struct mlx5_ifc_xrqc_bits xrq_context; 7562 }; 7563 7564 struct mlx5_ifc_create_xrc_srq_out_bits { 7565 u8 status[0x8]; 7566 u8 reserved_at_8[0x18]; 7567 7568 u8 syndrome[0x20]; 7569 7570 u8 reserved_at_40[0x8]; 7571 u8 xrc_srqn[0x18]; 7572 7573 u8 reserved_at_60[0x20]; 7574 }; 7575 7576 struct mlx5_ifc_create_xrc_srq_in_bits { 7577 u8 opcode[0x10]; 7578 u8 uid[0x10]; 7579 7580 u8 reserved_at_20[0x10]; 7581 u8 op_mod[0x10]; 7582 7583 u8 reserved_at_40[0x40]; 7584 7585 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 7586 7587 u8 reserved_at_280[0x60]; 7588 7589 u8 xrc_srq_umem_valid[0x1]; 7590 u8 reserved_at_2e1[0x1f]; 7591 7592 u8 reserved_at_300[0x580]; 7593 7594 u8 pas[][0x40]; 7595 }; 7596 7597 struct mlx5_ifc_create_tis_out_bits { 7598 u8 status[0x8]; 7599 u8 reserved_at_8[0x18]; 7600 7601 u8 syndrome[0x20]; 7602 7603 u8 reserved_at_40[0x8]; 7604 u8 tisn[0x18]; 7605 7606 u8 reserved_at_60[0x20]; 7607 }; 7608 7609 struct mlx5_ifc_create_tis_in_bits { 7610 u8 opcode[0x10]; 7611 u8 uid[0x10]; 7612 7613 u8 reserved_at_20[0x10]; 7614 u8 op_mod[0x10]; 7615 7616 u8 reserved_at_40[0xc0]; 7617 7618 struct mlx5_ifc_tisc_bits ctx; 7619 }; 7620 7621 struct mlx5_ifc_create_tir_out_bits { 7622 u8 status[0x8]; 7623 u8 icm_address_63_40[0x18]; 7624 7625 u8 syndrome[0x20]; 7626 7627 u8 icm_address_39_32[0x8]; 7628 u8 tirn[0x18]; 7629 7630 u8 icm_address_31_0[0x20]; 7631 }; 7632 7633 struct mlx5_ifc_create_tir_in_bits { 7634 u8 opcode[0x10]; 7635 u8 uid[0x10]; 7636 7637 u8 reserved_at_20[0x10]; 7638 u8 op_mod[0x10]; 7639 7640 u8 reserved_at_40[0xc0]; 7641 7642 struct mlx5_ifc_tirc_bits ctx; 7643 }; 7644 7645 struct mlx5_ifc_create_srq_out_bits { 7646 u8 status[0x8]; 7647 u8 reserved_at_8[0x18]; 7648 7649 u8 syndrome[0x20]; 7650 7651 u8 reserved_at_40[0x8]; 7652 u8 srqn[0x18]; 7653 7654 u8 reserved_at_60[0x20]; 7655 }; 7656 7657 struct mlx5_ifc_create_srq_in_bits { 7658 u8 opcode[0x10]; 7659 u8 uid[0x10]; 7660 7661 u8 reserved_at_20[0x10]; 7662 u8 op_mod[0x10]; 7663 7664 u8 reserved_at_40[0x40]; 7665 7666 struct mlx5_ifc_srqc_bits srq_context_entry; 7667 7668 u8 reserved_at_280[0x600]; 7669 7670 u8 pas[][0x40]; 7671 }; 7672 7673 struct mlx5_ifc_create_sq_out_bits { 7674 u8 status[0x8]; 7675 u8 reserved_at_8[0x18]; 7676 7677 u8 syndrome[0x20]; 7678 7679 u8 reserved_at_40[0x8]; 7680 u8 sqn[0x18]; 7681 7682 u8 reserved_at_60[0x20]; 7683 }; 7684 7685 struct mlx5_ifc_create_sq_in_bits { 7686 u8 opcode[0x10]; 7687 u8 uid[0x10]; 7688 7689 u8 reserved_at_20[0x10]; 7690 u8 op_mod[0x10]; 7691 7692 u8 reserved_at_40[0xc0]; 7693 7694 struct mlx5_ifc_sqc_bits ctx; 7695 }; 7696 7697 struct mlx5_ifc_create_scheduling_element_out_bits { 7698 u8 status[0x8]; 7699 u8 reserved_at_8[0x18]; 7700 7701 u8 syndrome[0x20]; 7702 7703 u8 reserved_at_40[0x40]; 7704 7705 u8 scheduling_element_id[0x20]; 7706 7707 u8 reserved_at_a0[0x160]; 7708 }; 7709 7710 struct mlx5_ifc_create_scheduling_element_in_bits { 7711 u8 opcode[0x10]; 7712 u8 reserved_at_10[0x10]; 7713 7714 u8 reserved_at_20[0x10]; 7715 u8 op_mod[0x10]; 7716 7717 u8 scheduling_hierarchy[0x8]; 7718 u8 reserved_at_48[0x18]; 7719 7720 u8 reserved_at_60[0xa0]; 7721 7722 struct mlx5_ifc_scheduling_context_bits scheduling_context; 7723 7724 u8 reserved_at_300[0x100]; 7725 }; 7726 7727 struct mlx5_ifc_create_rqt_out_bits { 7728 u8 status[0x8]; 7729 u8 reserved_at_8[0x18]; 7730 7731 u8 syndrome[0x20]; 7732 7733 u8 reserved_at_40[0x8]; 7734 u8 rqtn[0x18]; 7735 7736 u8 reserved_at_60[0x20]; 7737 }; 7738 7739 struct mlx5_ifc_create_rqt_in_bits { 7740 u8 opcode[0x10]; 7741 u8 uid[0x10]; 7742 7743 u8 reserved_at_20[0x10]; 7744 u8 op_mod[0x10]; 7745 7746 u8 reserved_at_40[0xc0]; 7747 7748 struct mlx5_ifc_rqtc_bits rqt_context; 7749 }; 7750 7751 struct mlx5_ifc_create_rq_out_bits { 7752 u8 status[0x8]; 7753 u8 reserved_at_8[0x18]; 7754 7755 u8 syndrome[0x20]; 7756 7757 u8 reserved_at_40[0x8]; 7758 u8 rqn[0x18]; 7759 7760 u8 reserved_at_60[0x20]; 7761 }; 7762 7763 struct mlx5_ifc_create_rq_in_bits { 7764 u8 opcode[0x10]; 7765 u8 uid[0x10]; 7766 7767 u8 reserved_at_20[0x10]; 7768 u8 op_mod[0x10]; 7769 7770 u8 reserved_at_40[0xc0]; 7771 7772 struct mlx5_ifc_rqc_bits ctx; 7773 }; 7774 7775 struct mlx5_ifc_create_rmp_out_bits { 7776 u8 status[0x8]; 7777 u8 reserved_at_8[0x18]; 7778 7779 u8 syndrome[0x20]; 7780 7781 u8 reserved_at_40[0x8]; 7782 u8 rmpn[0x18]; 7783 7784 u8 reserved_at_60[0x20]; 7785 }; 7786 7787 struct mlx5_ifc_create_rmp_in_bits { 7788 u8 opcode[0x10]; 7789 u8 uid[0x10]; 7790 7791 u8 reserved_at_20[0x10]; 7792 u8 op_mod[0x10]; 7793 7794 u8 reserved_at_40[0xc0]; 7795 7796 struct mlx5_ifc_rmpc_bits ctx; 7797 }; 7798 7799 struct mlx5_ifc_create_qp_out_bits { 7800 u8 status[0x8]; 7801 u8 reserved_at_8[0x18]; 7802 7803 u8 syndrome[0x20]; 7804 7805 u8 reserved_at_40[0x8]; 7806 u8 qpn[0x18]; 7807 7808 u8 ece[0x20]; 7809 }; 7810 7811 struct mlx5_ifc_create_qp_in_bits { 7812 u8 opcode[0x10]; 7813 u8 uid[0x10]; 7814 7815 u8 reserved_at_20[0x10]; 7816 u8 op_mod[0x10]; 7817 7818 u8 reserved_at_40[0x8]; 7819 u8 input_qpn[0x18]; 7820 7821 u8 reserved_at_60[0x20]; 7822 u8 opt_param_mask[0x20]; 7823 7824 u8 ece[0x20]; 7825 7826 struct mlx5_ifc_qpc_bits qpc; 7827 7828 u8 reserved_at_800[0x60]; 7829 7830 u8 wq_umem_valid[0x1]; 7831 u8 reserved_at_861[0x1f]; 7832 7833 u8 pas[][0x40]; 7834 }; 7835 7836 struct mlx5_ifc_create_psv_out_bits { 7837 u8 status[0x8]; 7838 u8 reserved_at_8[0x18]; 7839 7840 u8 syndrome[0x20]; 7841 7842 u8 reserved_at_40[0x40]; 7843 7844 u8 reserved_at_80[0x8]; 7845 u8 psv0_index[0x18]; 7846 7847 u8 reserved_at_a0[0x8]; 7848 u8 psv1_index[0x18]; 7849 7850 u8 reserved_at_c0[0x8]; 7851 u8 psv2_index[0x18]; 7852 7853 u8 reserved_at_e0[0x8]; 7854 u8 psv3_index[0x18]; 7855 }; 7856 7857 struct mlx5_ifc_create_psv_in_bits { 7858 u8 opcode[0x10]; 7859 u8 reserved_at_10[0x10]; 7860 7861 u8 reserved_at_20[0x10]; 7862 u8 op_mod[0x10]; 7863 7864 u8 num_psv[0x4]; 7865 u8 reserved_at_44[0x4]; 7866 u8 pd[0x18]; 7867 7868 u8 reserved_at_60[0x20]; 7869 }; 7870 7871 struct mlx5_ifc_create_mkey_out_bits { 7872 u8 status[0x8]; 7873 u8 reserved_at_8[0x18]; 7874 7875 u8 syndrome[0x20]; 7876 7877 u8 reserved_at_40[0x8]; 7878 u8 mkey_index[0x18]; 7879 7880 u8 reserved_at_60[0x20]; 7881 }; 7882 7883 struct mlx5_ifc_create_mkey_in_bits { 7884 u8 opcode[0x10]; 7885 u8 uid[0x10]; 7886 7887 u8 reserved_at_20[0x10]; 7888 u8 op_mod[0x10]; 7889 7890 u8 reserved_at_40[0x20]; 7891 7892 u8 pg_access[0x1]; 7893 u8 mkey_umem_valid[0x1]; 7894 u8 reserved_at_62[0x1e]; 7895 7896 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 7897 7898 u8 reserved_at_280[0x80]; 7899 7900 u8 translations_octword_actual_size[0x20]; 7901 7902 u8 reserved_at_320[0x560]; 7903 7904 u8 klm_pas_mtt[][0x20]; 7905 }; 7906 7907 enum { 7908 MLX5_FLOW_TABLE_TYPE_NIC_RX = 0x0, 7909 MLX5_FLOW_TABLE_TYPE_NIC_TX = 0x1, 7910 MLX5_FLOW_TABLE_TYPE_ESW_EGRESS_ACL = 0x2, 7911 MLX5_FLOW_TABLE_TYPE_ESW_INGRESS_ACL = 0x3, 7912 MLX5_FLOW_TABLE_TYPE_FDB = 0X4, 7913 MLX5_FLOW_TABLE_TYPE_SNIFFER_RX = 0X5, 7914 MLX5_FLOW_TABLE_TYPE_SNIFFER_TX = 0X6, 7915 }; 7916 7917 struct mlx5_ifc_create_flow_table_out_bits { 7918 u8 status[0x8]; 7919 u8 icm_address_63_40[0x18]; 7920 7921 u8 syndrome[0x20]; 7922 7923 u8 icm_address_39_32[0x8]; 7924 u8 table_id[0x18]; 7925 7926 u8 icm_address_31_0[0x20]; 7927 }; 7928 7929 struct mlx5_ifc_create_flow_table_in_bits { 7930 u8 opcode[0x10]; 7931 u8 reserved_at_10[0x10]; 7932 7933 u8 reserved_at_20[0x10]; 7934 u8 op_mod[0x10]; 7935 7936 u8 other_vport[0x1]; 7937 u8 reserved_at_41[0xf]; 7938 u8 vport_number[0x10]; 7939 7940 u8 reserved_at_60[0x20]; 7941 7942 u8 table_type[0x8]; 7943 u8 reserved_at_88[0x18]; 7944 7945 u8 reserved_at_a0[0x20]; 7946 7947 struct mlx5_ifc_flow_table_context_bits flow_table_context; 7948 }; 7949 7950 struct mlx5_ifc_create_flow_group_out_bits { 7951 u8 status[0x8]; 7952 u8 reserved_at_8[0x18]; 7953 7954 u8 syndrome[0x20]; 7955 7956 u8 reserved_at_40[0x8]; 7957 u8 group_id[0x18]; 7958 7959 u8 reserved_at_60[0x20]; 7960 }; 7961 7962 enum { 7963 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 7964 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 7965 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 7966 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3, 7967 }; 7968 7969 struct mlx5_ifc_create_flow_group_in_bits { 7970 u8 opcode[0x10]; 7971 u8 reserved_at_10[0x10]; 7972 7973 u8 reserved_at_20[0x10]; 7974 u8 op_mod[0x10]; 7975 7976 u8 other_vport[0x1]; 7977 u8 reserved_at_41[0xf]; 7978 u8 vport_number[0x10]; 7979 7980 u8 reserved_at_60[0x20]; 7981 7982 u8 table_type[0x8]; 7983 u8 reserved_at_88[0x18]; 7984 7985 u8 reserved_at_a0[0x8]; 7986 u8 table_id[0x18]; 7987 7988 u8 source_eswitch_owner_vhca_id_valid[0x1]; 7989 7990 u8 reserved_at_c1[0x1f]; 7991 7992 u8 start_flow_index[0x20]; 7993 7994 u8 reserved_at_100[0x20]; 7995 7996 u8 end_flow_index[0x20]; 7997 7998 u8 reserved_at_140[0xa0]; 7999 8000 u8 reserved_at_1e0[0x18]; 8001 u8 match_criteria_enable[0x8]; 8002 8003 struct mlx5_ifc_fte_match_param_bits match_criteria; 8004 8005 u8 reserved_at_1200[0xe00]; 8006 }; 8007 8008 struct mlx5_ifc_create_eq_out_bits { 8009 u8 status[0x8]; 8010 u8 reserved_at_8[0x18]; 8011 8012 u8 syndrome[0x20]; 8013 8014 u8 reserved_at_40[0x18]; 8015 u8 eq_number[0x8]; 8016 8017 u8 reserved_at_60[0x20]; 8018 }; 8019 8020 struct mlx5_ifc_create_eq_in_bits { 8021 u8 opcode[0x10]; 8022 u8 uid[0x10]; 8023 8024 u8 reserved_at_20[0x10]; 8025 u8 op_mod[0x10]; 8026 8027 u8 reserved_at_40[0x40]; 8028 8029 struct mlx5_ifc_eqc_bits eq_context_entry; 8030 8031 u8 reserved_at_280[0x40]; 8032 8033 u8 event_bitmask[4][0x40]; 8034 8035 u8 reserved_at_3c0[0x4c0]; 8036 8037 u8 pas[][0x40]; 8038 }; 8039 8040 struct mlx5_ifc_create_dct_out_bits { 8041 u8 status[0x8]; 8042 u8 reserved_at_8[0x18]; 8043 8044 u8 syndrome[0x20]; 8045 8046 u8 reserved_at_40[0x8]; 8047 u8 dctn[0x18]; 8048 8049 u8 ece[0x20]; 8050 }; 8051 8052 struct mlx5_ifc_create_dct_in_bits { 8053 u8 opcode[0x10]; 8054 u8 uid[0x10]; 8055 8056 u8 reserved_at_20[0x10]; 8057 u8 op_mod[0x10]; 8058 8059 u8 reserved_at_40[0x40]; 8060 8061 struct mlx5_ifc_dctc_bits dct_context_entry; 8062 8063 u8 reserved_at_280[0x180]; 8064 }; 8065 8066 struct mlx5_ifc_create_cq_out_bits { 8067 u8 status[0x8]; 8068 u8 reserved_at_8[0x18]; 8069 8070 u8 syndrome[0x20]; 8071 8072 u8 reserved_at_40[0x8]; 8073 u8 cqn[0x18]; 8074 8075 u8 reserved_at_60[0x20]; 8076 }; 8077 8078 struct mlx5_ifc_create_cq_in_bits { 8079 u8 opcode[0x10]; 8080 u8 uid[0x10]; 8081 8082 u8 reserved_at_20[0x10]; 8083 u8 op_mod[0x10]; 8084 8085 u8 reserved_at_40[0x40]; 8086 8087 struct mlx5_ifc_cqc_bits cq_context; 8088 8089 u8 reserved_at_280[0x60]; 8090 8091 u8 cq_umem_valid[0x1]; 8092 u8 reserved_at_2e1[0x59f]; 8093 8094 u8 pas[][0x40]; 8095 }; 8096 8097 struct mlx5_ifc_config_int_moderation_out_bits { 8098 u8 status[0x8]; 8099 u8 reserved_at_8[0x18]; 8100 8101 u8 syndrome[0x20]; 8102 8103 u8 reserved_at_40[0x4]; 8104 u8 min_delay[0xc]; 8105 u8 int_vector[0x10]; 8106 8107 u8 reserved_at_60[0x20]; 8108 }; 8109 8110 enum { 8111 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0, 8112 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1, 8113 }; 8114 8115 struct mlx5_ifc_config_int_moderation_in_bits { 8116 u8 opcode[0x10]; 8117 u8 reserved_at_10[0x10]; 8118 8119 u8 reserved_at_20[0x10]; 8120 u8 op_mod[0x10]; 8121 8122 u8 reserved_at_40[0x4]; 8123 u8 min_delay[0xc]; 8124 u8 int_vector[0x10]; 8125 8126 u8 reserved_at_60[0x20]; 8127 }; 8128 8129 struct mlx5_ifc_attach_to_mcg_out_bits { 8130 u8 status[0x8]; 8131 u8 reserved_at_8[0x18]; 8132 8133 u8 syndrome[0x20]; 8134 8135 u8 reserved_at_40[0x40]; 8136 }; 8137 8138 struct mlx5_ifc_attach_to_mcg_in_bits { 8139 u8 opcode[0x10]; 8140 u8 uid[0x10]; 8141 8142 u8 reserved_at_20[0x10]; 8143 u8 op_mod[0x10]; 8144 8145 u8 reserved_at_40[0x8]; 8146 u8 qpn[0x18]; 8147 8148 u8 reserved_at_60[0x20]; 8149 8150 u8 multicast_gid[16][0x8]; 8151 }; 8152 8153 struct mlx5_ifc_arm_xrq_out_bits { 8154 u8 status[0x8]; 8155 u8 reserved_at_8[0x18]; 8156 8157 u8 syndrome[0x20]; 8158 8159 u8 reserved_at_40[0x40]; 8160 }; 8161 8162 struct mlx5_ifc_arm_xrq_in_bits { 8163 u8 opcode[0x10]; 8164 u8 reserved_at_10[0x10]; 8165 8166 u8 reserved_at_20[0x10]; 8167 u8 op_mod[0x10]; 8168 8169 u8 reserved_at_40[0x8]; 8170 u8 xrqn[0x18]; 8171 8172 u8 reserved_at_60[0x10]; 8173 u8 lwm[0x10]; 8174 }; 8175 8176 struct mlx5_ifc_arm_xrc_srq_out_bits { 8177 u8 status[0x8]; 8178 u8 reserved_at_8[0x18]; 8179 8180 u8 syndrome[0x20]; 8181 8182 u8 reserved_at_40[0x40]; 8183 }; 8184 8185 enum { 8186 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1, 8187 }; 8188 8189 struct mlx5_ifc_arm_xrc_srq_in_bits { 8190 u8 opcode[0x10]; 8191 u8 uid[0x10]; 8192 8193 u8 reserved_at_20[0x10]; 8194 u8 op_mod[0x10]; 8195 8196 u8 reserved_at_40[0x8]; 8197 u8 xrc_srqn[0x18]; 8198 8199 u8 reserved_at_60[0x10]; 8200 u8 lwm[0x10]; 8201 }; 8202 8203 struct mlx5_ifc_arm_rq_out_bits { 8204 u8 status[0x8]; 8205 u8 reserved_at_8[0x18]; 8206 8207 u8 syndrome[0x20]; 8208 8209 u8 reserved_at_40[0x40]; 8210 }; 8211 8212 enum { 8213 MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1, 8214 MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2, 8215 }; 8216 8217 struct mlx5_ifc_arm_rq_in_bits { 8218 u8 opcode[0x10]; 8219 u8 uid[0x10]; 8220 8221 u8 reserved_at_20[0x10]; 8222 u8 op_mod[0x10]; 8223 8224 u8 reserved_at_40[0x8]; 8225 u8 srq_number[0x18]; 8226 8227 u8 reserved_at_60[0x10]; 8228 u8 lwm[0x10]; 8229 }; 8230 8231 struct mlx5_ifc_arm_dct_out_bits { 8232 u8 status[0x8]; 8233 u8 reserved_at_8[0x18]; 8234 8235 u8 syndrome[0x20]; 8236 8237 u8 reserved_at_40[0x40]; 8238 }; 8239 8240 struct mlx5_ifc_arm_dct_in_bits { 8241 u8 opcode[0x10]; 8242 u8 reserved_at_10[0x10]; 8243 8244 u8 reserved_at_20[0x10]; 8245 u8 op_mod[0x10]; 8246 8247 u8 reserved_at_40[0x8]; 8248 u8 dct_number[0x18]; 8249 8250 u8 reserved_at_60[0x20]; 8251 }; 8252 8253 struct mlx5_ifc_alloc_xrcd_out_bits { 8254 u8 status[0x8]; 8255 u8 reserved_at_8[0x18]; 8256 8257 u8 syndrome[0x20]; 8258 8259 u8 reserved_at_40[0x8]; 8260 u8 xrcd[0x18]; 8261 8262 u8 reserved_at_60[0x20]; 8263 }; 8264 8265 struct mlx5_ifc_alloc_xrcd_in_bits { 8266 u8 opcode[0x10]; 8267 u8 uid[0x10]; 8268 8269 u8 reserved_at_20[0x10]; 8270 u8 op_mod[0x10]; 8271 8272 u8 reserved_at_40[0x40]; 8273 }; 8274 8275 struct mlx5_ifc_alloc_uar_out_bits { 8276 u8 status[0x8]; 8277 u8 reserved_at_8[0x18]; 8278 8279 u8 syndrome[0x20]; 8280 8281 u8 reserved_at_40[0x8]; 8282 u8 uar[0x18]; 8283 8284 u8 reserved_at_60[0x20]; 8285 }; 8286 8287 struct mlx5_ifc_alloc_uar_in_bits { 8288 u8 opcode[0x10]; 8289 u8 reserved_at_10[0x10]; 8290 8291 u8 reserved_at_20[0x10]; 8292 u8 op_mod[0x10]; 8293 8294 u8 reserved_at_40[0x40]; 8295 }; 8296 8297 struct mlx5_ifc_alloc_transport_domain_out_bits { 8298 u8 status[0x8]; 8299 u8 reserved_at_8[0x18]; 8300 8301 u8 syndrome[0x20]; 8302 8303 u8 reserved_at_40[0x8]; 8304 u8 transport_domain[0x18]; 8305 8306 u8 reserved_at_60[0x20]; 8307 }; 8308 8309 struct mlx5_ifc_alloc_transport_domain_in_bits { 8310 u8 opcode[0x10]; 8311 u8 uid[0x10]; 8312 8313 u8 reserved_at_20[0x10]; 8314 u8 op_mod[0x10]; 8315 8316 u8 reserved_at_40[0x40]; 8317 }; 8318 8319 struct mlx5_ifc_alloc_q_counter_out_bits { 8320 u8 status[0x8]; 8321 u8 reserved_at_8[0x18]; 8322 8323 u8 syndrome[0x20]; 8324 8325 u8 reserved_at_40[0x18]; 8326 u8 counter_set_id[0x8]; 8327 8328 u8 reserved_at_60[0x20]; 8329 }; 8330 8331 struct mlx5_ifc_alloc_q_counter_in_bits { 8332 u8 opcode[0x10]; 8333 u8 uid[0x10]; 8334 8335 u8 reserved_at_20[0x10]; 8336 u8 op_mod[0x10]; 8337 8338 u8 reserved_at_40[0x40]; 8339 }; 8340 8341 struct mlx5_ifc_alloc_pd_out_bits { 8342 u8 status[0x8]; 8343 u8 reserved_at_8[0x18]; 8344 8345 u8 syndrome[0x20]; 8346 8347 u8 reserved_at_40[0x8]; 8348 u8 pd[0x18]; 8349 8350 u8 reserved_at_60[0x20]; 8351 }; 8352 8353 struct mlx5_ifc_alloc_pd_in_bits { 8354 u8 opcode[0x10]; 8355 u8 uid[0x10]; 8356 8357 u8 reserved_at_20[0x10]; 8358 u8 op_mod[0x10]; 8359 8360 u8 reserved_at_40[0x40]; 8361 }; 8362 8363 struct mlx5_ifc_alloc_flow_counter_out_bits { 8364 u8 status[0x8]; 8365 u8 reserved_at_8[0x18]; 8366 8367 u8 syndrome[0x20]; 8368 8369 u8 flow_counter_id[0x20]; 8370 8371 u8 reserved_at_60[0x20]; 8372 }; 8373 8374 struct mlx5_ifc_alloc_flow_counter_in_bits { 8375 u8 opcode[0x10]; 8376 u8 reserved_at_10[0x10]; 8377 8378 u8 reserved_at_20[0x10]; 8379 u8 op_mod[0x10]; 8380 8381 u8 reserved_at_40[0x38]; 8382 u8 flow_counter_bulk[0x8]; 8383 }; 8384 8385 struct mlx5_ifc_add_vxlan_udp_dport_out_bits { 8386 u8 status[0x8]; 8387 u8 reserved_at_8[0x18]; 8388 8389 u8 syndrome[0x20]; 8390 8391 u8 reserved_at_40[0x40]; 8392 }; 8393 8394 struct mlx5_ifc_add_vxlan_udp_dport_in_bits { 8395 u8 opcode[0x10]; 8396 u8 reserved_at_10[0x10]; 8397 8398 u8 reserved_at_20[0x10]; 8399 u8 op_mod[0x10]; 8400 8401 u8 reserved_at_40[0x20]; 8402 8403 u8 reserved_at_60[0x10]; 8404 u8 vxlan_udp_port[0x10]; 8405 }; 8406 8407 struct mlx5_ifc_set_pp_rate_limit_out_bits { 8408 u8 status[0x8]; 8409 u8 reserved_at_8[0x18]; 8410 8411 u8 syndrome[0x20]; 8412 8413 u8 reserved_at_40[0x40]; 8414 }; 8415 8416 struct mlx5_ifc_set_pp_rate_limit_context_bits { 8417 u8 rate_limit[0x20]; 8418 8419 u8 burst_upper_bound[0x20]; 8420 8421 u8 reserved_at_40[0x10]; 8422 u8 typical_packet_size[0x10]; 8423 8424 u8 reserved_at_60[0x120]; 8425 }; 8426 8427 struct mlx5_ifc_set_pp_rate_limit_in_bits { 8428 u8 opcode[0x10]; 8429 u8 uid[0x10]; 8430 8431 u8 reserved_at_20[0x10]; 8432 u8 op_mod[0x10]; 8433 8434 u8 reserved_at_40[0x10]; 8435 u8 rate_limit_index[0x10]; 8436 8437 u8 reserved_at_60[0x20]; 8438 8439 struct mlx5_ifc_set_pp_rate_limit_context_bits ctx; 8440 }; 8441 8442 struct mlx5_ifc_access_register_out_bits { 8443 u8 status[0x8]; 8444 u8 reserved_at_8[0x18]; 8445 8446 u8 syndrome[0x20]; 8447 8448 u8 reserved_at_40[0x40]; 8449 8450 u8 register_data[][0x20]; 8451 }; 8452 8453 enum { 8454 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0, 8455 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1, 8456 }; 8457 8458 struct mlx5_ifc_access_register_in_bits { 8459 u8 opcode[0x10]; 8460 u8 reserved_at_10[0x10]; 8461 8462 u8 reserved_at_20[0x10]; 8463 u8 op_mod[0x10]; 8464 8465 u8 reserved_at_40[0x10]; 8466 u8 register_id[0x10]; 8467 8468 u8 argument[0x20]; 8469 8470 u8 register_data[][0x20]; 8471 }; 8472 8473 struct mlx5_ifc_sltp_reg_bits { 8474 u8 status[0x4]; 8475 u8 version[0x4]; 8476 u8 local_port[0x8]; 8477 u8 pnat[0x2]; 8478 u8 reserved_at_12[0x2]; 8479 u8 lane[0x4]; 8480 u8 reserved_at_18[0x8]; 8481 8482 u8 reserved_at_20[0x20]; 8483 8484 u8 reserved_at_40[0x7]; 8485 u8 polarity[0x1]; 8486 u8 ob_tap0[0x8]; 8487 u8 ob_tap1[0x8]; 8488 u8 ob_tap2[0x8]; 8489 8490 u8 reserved_at_60[0xc]; 8491 u8 ob_preemp_mode[0x4]; 8492 u8 ob_reg[0x8]; 8493 u8 ob_bias[0x8]; 8494 8495 u8 reserved_at_80[0x20]; 8496 }; 8497 8498 struct mlx5_ifc_slrg_reg_bits { 8499 u8 status[0x4]; 8500 u8 version[0x4]; 8501 u8 local_port[0x8]; 8502 u8 pnat[0x2]; 8503 u8 reserved_at_12[0x2]; 8504 u8 lane[0x4]; 8505 u8 reserved_at_18[0x8]; 8506 8507 u8 time_to_link_up[0x10]; 8508 u8 reserved_at_30[0xc]; 8509 u8 grade_lane_speed[0x4]; 8510 8511 u8 grade_version[0x8]; 8512 u8 grade[0x18]; 8513 8514 u8 reserved_at_60[0x4]; 8515 u8 height_grade_type[0x4]; 8516 u8 height_grade[0x18]; 8517 8518 u8 height_dz[0x10]; 8519 u8 height_dv[0x10]; 8520 8521 u8 reserved_at_a0[0x10]; 8522 u8 height_sigma[0x10]; 8523 8524 u8 reserved_at_c0[0x20]; 8525 8526 u8 reserved_at_e0[0x4]; 8527 u8 phase_grade_type[0x4]; 8528 u8 phase_grade[0x18]; 8529 8530 u8 reserved_at_100[0x8]; 8531 u8 phase_eo_pos[0x8]; 8532 u8 reserved_at_110[0x8]; 8533 u8 phase_eo_neg[0x8]; 8534 8535 u8 ffe_set_tested[0x10]; 8536 u8 test_errors_per_lane[0x10]; 8537 }; 8538 8539 struct mlx5_ifc_pvlc_reg_bits { 8540 u8 reserved_at_0[0x8]; 8541 u8 local_port[0x8]; 8542 u8 reserved_at_10[0x10]; 8543 8544 u8 reserved_at_20[0x1c]; 8545 u8 vl_hw_cap[0x4]; 8546 8547 u8 reserved_at_40[0x1c]; 8548 u8 vl_admin[0x4]; 8549 8550 u8 reserved_at_60[0x1c]; 8551 u8 vl_operational[0x4]; 8552 }; 8553 8554 struct mlx5_ifc_pude_reg_bits { 8555 u8 swid[0x8]; 8556 u8 local_port[0x8]; 8557 u8 reserved_at_10[0x4]; 8558 u8 admin_status[0x4]; 8559 u8 reserved_at_18[0x4]; 8560 u8 oper_status[0x4]; 8561 8562 u8 reserved_at_20[0x60]; 8563 }; 8564 8565 struct mlx5_ifc_ptys_reg_bits { 8566 u8 reserved_at_0[0x1]; 8567 u8 an_disable_admin[0x1]; 8568 u8 an_disable_cap[0x1]; 8569 u8 reserved_at_3[0x5]; 8570 u8 local_port[0x8]; 8571 u8 reserved_at_10[0xd]; 8572 u8 proto_mask[0x3]; 8573 8574 u8 an_status[0x4]; 8575 u8 reserved_at_24[0xc]; 8576 u8 data_rate_oper[0x10]; 8577 8578 u8 ext_eth_proto_capability[0x20]; 8579 8580 u8 eth_proto_capability[0x20]; 8581 8582 u8 ib_link_width_capability[0x10]; 8583 u8 ib_proto_capability[0x10]; 8584 8585 u8 ext_eth_proto_admin[0x20]; 8586 8587 u8 eth_proto_admin[0x20]; 8588 8589 u8 ib_link_width_admin[0x10]; 8590 u8 ib_proto_admin[0x10]; 8591 8592 u8 ext_eth_proto_oper[0x20]; 8593 8594 u8 eth_proto_oper[0x20]; 8595 8596 u8 ib_link_width_oper[0x10]; 8597 u8 ib_proto_oper[0x10]; 8598 8599 u8 reserved_at_160[0x1c]; 8600 u8 connector_type[0x4]; 8601 8602 u8 eth_proto_lp_advertise[0x20]; 8603 8604 u8 reserved_at_1a0[0x60]; 8605 }; 8606 8607 struct mlx5_ifc_mlcr_reg_bits { 8608 u8 reserved_at_0[0x8]; 8609 u8 local_port[0x8]; 8610 u8 reserved_at_10[0x20]; 8611 8612 u8 beacon_duration[0x10]; 8613 u8 reserved_at_40[0x10]; 8614 8615 u8 beacon_remain[0x10]; 8616 }; 8617 8618 struct mlx5_ifc_ptas_reg_bits { 8619 u8 reserved_at_0[0x20]; 8620 8621 u8 algorithm_options[0x10]; 8622 u8 reserved_at_30[0x4]; 8623 u8 repetitions_mode[0x4]; 8624 u8 num_of_repetitions[0x8]; 8625 8626 u8 grade_version[0x8]; 8627 u8 height_grade_type[0x4]; 8628 u8 phase_grade_type[0x4]; 8629 u8 height_grade_weight[0x8]; 8630 u8 phase_grade_weight[0x8]; 8631 8632 u8 gisim_measure_bits[0x10]; 8633 u8 adaptive_tap_measure_bits[0x10]; 8634 8635 u8 ber_bath_high_error_threshold[0x10]; 8636 u8 ber_bath_mid_error_threshold[0x10]; 8637 8638 u8 ber_bath_low_error_threshold[0x10]; 8639 u8 one_ratio_high_threshold[0x10]; 8640 8641 u8 one_ratio_high_mid_threshold[0x10]; 8642 u8 one_ratio_low_mid_threshold[0x10]; 8643 8644 u8 one_ratio_low_threshold[0x10]; 8645 u8 ndeo_error_threshold[0x10]; 8646 8647 u8 mixer_offset_step_size[0x10]; 8648 u8 reserved_at_110[0x8]; 8649 u8 mix90_phase_for_voltage_bath[0x8]; 8650 8651 u8 mixer_offset_start[0x10]; 8652 u8 mixer_offset_end[0x10]; 8653 8654 u8 reserved_at_140[0x15]; 8655 u8 ber_test_time[0xb]; 8656 }; 8657 8658 struct mlx5_ifc_pspa_reg_bits { 8659 u8 swid[0x8]; 8660 u8 local_port[0x8]; 8661 u8 sub_port[0x8]; 8662 u8 reserved_at_18[0x8]; 8663 8664 u8 reserved_at_20[0x20]; 8665 }; 8666 8667 struct mlx5_ifc_pqdr_reg_bits { 8668 u8 reserved_at_0[0x8]; 8669 u8 local_port[0x8]; 8670 u8 reserved_at_10[0x5]; 8671 u8 prio[0x3]; 8672 u8 reserved_at_18[0x6]; 8673 u8 mode[0x2]; 8674 8675 u8 reserved_at_20[0x20]; 8676 8677 u8 reserved_at_40[0x10]; 8678 u8 min_threshold[0x10]; 8679 8680 u8 reserved_at_60[0x10]; 8681 u8 max_threshold[0x10]; 8682 8683 u8 reserved_at_80[0x10]; 8684 u8 mark_probability_denominator[0x10]; 8685 8686 u8 reserved_at_a0[0x60]; 8687 }; 8688 8689 struct mlx5_ifc_ppsc_reg_bits { 8690 u8 reserved_at_0[0x8]; 8691 u8 local_port[0x8]; 8692 u8 reserved_at_10[0x10]; 8693 8694 u8 reserved_at_20[0x60]; 8695 8696 u8 reserved_at_80[0x1c]; 8697 u8 wrps_admin[0x4]; 8698 8699 u8 reserved_at_a0[0x1c]; 8700 u8 wrps_status[0x4]; 8701 8702 u8 reserved_at_c0[0x8]; 8703 u8 up_threshold[0x8]; 8704 u8 reserved_at_d0[0x8]; 8705 u8 down_threshold[0x8]; 8706 8707 u8 reserved_at_e0[0x20]; 8708 8709 u8 reserved_at_100[0x1c]; 8710 u8 srps_admin[0x4]; 8711 8712 u8 reserved_at_120[0x1c]; 8713 u8 srps_status[0x4]; 8714 8715 u8 reserved_at_140[0x40]; 8716 }; 8717 8718 struct mlx5_ifc_pplr_reg_bits { 8719 u8 reserved_at_0[0x8]; 8720 u8 local_port[0x8]; 8721 u8 reserved_at_10[0x10]; 8722 8723 u8 reserved_at_20[0x8]; 8724 u8 lb_cap[0x8]; 8725 u8 reserved_at_30[0x8]; 8726 u8 lb_en[0x8]; 8727 }; 8728 8729 struct mlx5_ifc_pplm_reg_bits { 8730 u8 reserved_at_0[0x8]; 8731 u8 local_port[0x8]; 8732 u8 reserved_at_10[0x10]; 8733 8734 u8 reserved_at_20[0x20]; 8735 8736 u8 port_profile_mode[0x8]; 8737 u8 static_port_profile[0x8]; 8738 u8 active_port_profile[0x8]; 8739 u8 reserved_at_58[0x8]; 8740 8741 u8 retransmission_active[0x8]; 8742 u8 fec_mode_active[0x18]; 8743 8744 u8 rs_fec_correction_bypass_cap[0x4]; 8745 u8 reserved_at_84[0x8]; 8746 u8 fec_override_cap_56g[0x4]; 8747 u8 fec_override_cap_100g[0x4]; 8748 u8 fec_override_cap_50g[0x4]; 8749 u8 fec_override_cap_25g[0x4]; 8750 u8 fec_override_cap_10g_40g[0x4]; 8751 8752 u8 rs_fec_correction_bypass_admin[0x4]; 8753 u8 reserved_at_a4[0x8]; 8754 u8 fec_override_admin_56g[0x4]; 8755 u8 fec_override_admin_100g[0x4]; 8756 u8 fec_override_admin_50g[0x4]; 8757 u8 fec_override_admin_25g[0x4]; 8758 u8 fec_override_admin_10g_40g[0x4]; 8759 8760 u8 fec_override_cap_400g_8x[0x10]; 8761 u8 fec_override_cap_200g_4x[0x10]; 8762 8763 u8 fec_override_cap_100g_2x[0x10]; 8764 u8 fec_override_cap_50g_1x[0x10]; 8765 8766 u8 fec_override_admin_400g_8x[0x10]; 8767 u8 fec_override_admin_200g_4x[0x10]; 8768 8769 u8 fec_override_admin_100g_2x[0x10]; 8770 u8 fec_override_admin_50g_1x[0x10]; 8771 }; 8772 8773 struct mlx5_ifc_ppcnt_reg_bits { 8774 u8 swid[0x8]; 8775 u8 local_port[0x8]; 8776 u8 pnat[0x2]; 8777 u8 reserved_at_12[0x8]; 8778 u8 grp[0x6]; 8779 8780 u8 clr[0x1]; 8781 u8 reserved_at_21[0x1c]; 8782 u8 prio_tc[0x3]; 8783 8784 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set; 8785 }; 8786 8787 struct mlx5_ifc_mpein_reg_bits { 8788 u8 reserved_at_0[0x2]; 8789 u8 depth[0x6]; 8790 u8 pcie_index[0x8]; 8791 u8 node[0x8]; 8792 u8 reserved_at_18[0x8]; 8793 8794 u8 capability_mask[0x20]; 8795 8796 u8 reserved_at_40[0x8]; 8797 u8 link_width_enabled[0x8]; 8798 u8 link_speed_enabled[0x10]; 8799 8800 u8 lane0_physical_position[0x8]; 8801 u8 link_width_active[0x8]; 8802 u8 link_speed_active[0x10]; 8803 8804 u8 num_of_pfs[0x10]; 8805 u8 num_of_vfs[0x10]; 8806 8807 u8 bdf0[0x10]; 8808 u8 reserved_at_b0[0x10]; 8809 8810 u8 max_read_request_size[0x4]; 8811 u8 max_payload_size[0x4]; 8812 u8 reserved_at_c8[0x5]; 8813 u8 pwr_status[0x3]; 8814 u8 port_type[0x4]; 8815 u8 reserved_at_d4[0xb]; 8816 u8 lane_reversal[0x1]; 8817 8818 u8 reserved_at_e0[0x14]; 8819 u8 pci_power[0xc]; 8820 8821 u8 reserved_at_100[0x20]; 8822 8823 u8 device_status[0x10]; 8824 u8 port_state[0x8]; 8825 u8 reserved_at_138[0x8]; 8826 8827 u8 reserved_at_140[0x10]; 8828 u8 receiver_detect_result[0x10]; 8829 8830 u8 reserved_at_160[0x20]; 8831 }; 8832 8833 struct mlx5_ifc_mpcnt_reg_bits { 8834 u8 reserved_at_0[0x8]; 8835 u8 pcie_index[0x8]; 8836 u8 reserved_at_10[0xa]; 8837 u8 grp[0x6]; 8838 8839 u8 clr[0x1]; 8840 u8 reserved_at_21[0x1f]; 8841 8842 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set; 8843 }; 8844 8845 struct mlx5_ifc_ppad_reg_bits { 8846 u8 reserved_at_0[0x3]; 8847 u8 single_mac[0x1]; 8848 u8 reserved_at_4[0x4]; 8849 u8 local_port[0x8]; 8850 u8 mac_47_32[0x10]; 8851 8852 u8 mac_31_0[0x20]; 8853 8854 u8 reserved_at_40[0x40]; 8855 }; 8856 8857 struct mlx5_ifc_pmtu_reg_bits { 8858 u8 reserved_at_0[0x8]; 8859 u8 local_port[0x8]; 8860 u8 reserved_at_10[0x10]; 8861 8862 u8 max_mtu[0x10]; 8863 u8 reserved_at_30[0x10]; 8864 8865 u8 admin_mtu[0x10]; 8866 u8 reserved_at_50[0x10]; 8867 8868 u8 oper_mtu[0x10]; 8869 u8 reserved_at_70[0x10]; 8870 }; 8871 8872 struct mlx5_ifc_pmpr_reg_bits { 8873 u8 reserved_at_0[0x8]; 8874 u8 module[0x8]; 8875 u8 reserved_at_10[0x10]; 8876 8877 u8 reserved_at_20[0x18]; 8878 u8 attenuation_5g[0x8]; 8879 8880 u8 reserved_at_40[0x18]; 8881 u8 attenuation_7g[0x8]; 8882 8883 u8 reserved_at_60[0x18]; 8884 u8 attenuation_12g[0x8]; 8885 }; 8886 8887 struct mlx5_ifc_pmpe_reg_bits { 8888 u8 reserved_at_0[0x8]; 8889 u8 module[0x8]; 8890 u8 reserved_at_10[0xc]; 8891 u8 module_status[0x4]; 8892 8893 u8 reserved_at_20[0x60]; 8894 }; 8895 8896 struct mlx5_ifc_pmpc_reg_bits { 8897 u8 module_state_updated[32][0x8]; 8898 }; 8899 8900 struct mlx5_ifc_pmlpn_reg_bits { 8901 u8 reserved_at_0[0x4]; 8902 u8 mlpn_status[0x4]; 8903 u8 local_port[0x8]; 8904 u8 reserved_at_10[0x10]; 8905 8906 u8 e[0x1]; 8907 u8 reserved_at_21[0x1f]; 8908 }; 8909 8910 struct mlx5_ifc_pmlp_reg_bits { 8911 u8 rxtx[0x1]; 8912 u8 reserved_at_1[0x7]; 8913 u8 local_port[0x8]; 8914 u8 reserved_at_10[0x8]; 8915 u8 width[0x8]; 8916 8917 u8 lane0_module_mapping[0x20]; 8918 8919 u8 lane1_module_mapping[0x20]; 8920 8921 u8 lane2_module_mapping[0x20]; 8922 8923 u8 lane3_module_mapping[0x20]; 8924 8925 u8 reserved_at_a0[0x160]; 8926 }; 8927 8928 struct mlx5_ifc_pmaos_reg_bits { 8929 u8 reserved_at_0[0x8]; 8930 u8 module[0x8]; 8931 u8 reserved_at_10[0x4]; 8932 u8 admin_status[0x4]; 8933 u8 reserved_at_18[0x4]; 8934 u8 oper_status[0x4]; 8935 8936 u8 ase[0x1]; 8937 u8 ee[0x1]; 8938 u8 reserved_at_22[0x1c]; 8939 u8 e[0x2]; 8940 8941 u8 reserved_at_40[0x40]; 8942 }; 8943 8944 struct mlx5_ifc_plpc_reg_bits { 8945 u8 reserved_at_0[0x4]; 8946 u8 profile_id[0xc]; 8947 u8 reserved_at_10[0x4]; 8948 u8 proto_mask[0x4]; 8949 u8 reserved_at_18[0x8]; 8950 8951 u8 reserved_at_20[0x10]; 8952 u8 lane_speed[0x10]; 8953 8954 u8 reserved_at_40[0x17]; 8955 u8 lpbf[0x1]; 8956 u8 fec_mode_policy[0x8]; 8957 8958 u8 retransmission_capability[0x8]; 8959 u8 fec_mode_capability[0x18]; 8960 8961 u8 retransmission_support_admin[0x8]; 8962 u8 fec_mode_support_admin[0x18]; 8963 8964 u8 retransmission_request_admin[0x8]; 8965 u8 fec_mode_request_admin[0x18]; 8966 8967 u8 reserved_at_c0[0x80]; 8968 }; 8969 8970 struct mlx5_ifc_plib_reg_bits { 8971 u8 reserved_at_0[0x8]; 8972 u8 local_port[0x8]; 8973 u8 reserved_at_10[0x8]; 8974 u8 ib_port[0x8]; 8975 8976 u8 reserved_at_20[0x60]; 8977 }; 8978 8979 struct mlx5_ifc_plbf_reg_bits { 8980 u8 reserved_at_0[0x8]; 8981 u8 local_port[0x8]; 8982 u8 reserved_at_10[0xd]; 8983 u8 lbf_mode[0x3]; 8984 8985 u8 reserved_at_20[0x20]; 8986 }; 8987 8988 struct mlx5_ifc_pipg_reg_bits { 8989 u8 reserved_at_0[0x8]; 8990 u8 local_port[0x8]; 8991 u8 reserved_at_10[0x10]; 8992 8993 u8 dic[0x1]; 8994 u8 reserved_at_21[0x19]; 8995 u8 ipg[0x4]; 8996 u8 reserved_at_3e[0x2]; 8997 }; 8998 8999 struct mlx5_ifc_pifr_reg_bits { 9000 u8 reserved_at_0[0x8]; 9001 u8 local_port[0x8]; 9002 u8 reserved_at_10[0x10]; 9003 9004 u8 reserved_at_20[0xe0]; 9005 9006 u8 port_filter[8][0x20]; 9007 9008 u8 port_filter_update_en[8][0x20]; 9009 }; 9010 9011 struct mlx5_ifc_pfcc_reg_bits { 9012 u8 reserved_at_0[0x8]; 9013 u8 local_port[0x8]; 9014 u8 reserved_at_10[0xb]; 9015 u8 ppan_mask_n[0x1]; 9016 u8 minor_stall_mask[0x1]; 9017 u8 critical_stall_mask[0x1]; 9018 u8 reserved_at_1e[0x2]; 9019 9020 u8 ppan[0x4]; 9021 u8 reserved_at_24[0x4]; 9022 u8 prio_mask_tx[0x8]; 9023 u8 reserved_at_30[0x8]; 9024 u8 prio_mask_rx[0x8]; 9025 9026 u8 pptx[0x1]; 9027 u8 aptx[0x1]; 9028 u8 pptx_mask_n[0x1]; 9029 u8 reserved_at_43[0x5]; 9030 u8 pfctx[0x8]; 9031 u8 reserved_at_50[0x10]; 9032 9033 u8 pprx[0x1]; 9034 u8 aprx[0x1]; 9035 u8 pprx_mask_n[0x1]; 9036 u8 reserved_at_63[0x5]; 9037 u8 pfcrx[0x8]; 9038 u8 reserved_at_70[0x10]; 9039 9040 u8 device_stall_minor_watermark[0x10]; 9041 u8 device_stall_critical_watermark[0x10]; 9042 9043 u8 reserved_at_a0[0x60]; 9044 }; 9045 9046 struct mlx5_ifc_pelc_reg_bits { 9047 u8 op[0x4]; 9048 u8 reserved_at_4[0x4]; 9049 u8 local_port[0x8]; 9050 u8 reserved_at_10[0x10]; 9051 9052 u8 op_admin[0x8]; 9053 u8 op_capability[0x8]; 9054 u8 op_request[0x8]; 9055 u8 op_active[0x8]; 9056 9057 u8 admin[0x40]; 9058 9059 u8 capability[0x40]; 9060 9061 u8 request[0x40]; 9062 9063 u8 active[0x40]; 9064 9065 u8 reserved_at_140[0x80]; 9066 }; 9067 9068 struct mlx5_ifc_peir_reg_bits { 9069 u8 reserved_at_0[0x8]; 9070 u8 local_port[0x8]; 9071 u8 reserved_at_10[0x10]; 9072 9073 u8 reserved_at_20[0xc]; 9074 u8 error_count[0x4]; 9075 u8 reserved_at_30[0x10]; 9076 9077 u8 reserved_at_40[0xc]; 9078 u8 lane[0x4]; 9079 u8 reserved_at_50[0x8]; 9080 u8 error_type[0x8]; 9081 }; 9082 9083 struct mlx5_ifc_mpegc_reg_bits { 9084 u8 reserved_at_0[0x30]; 9085 u8 field_select[0x10]; 9086 9087 u8 tx_overflow_sense[0x1]; 9088 u8 mark_cqe[0x1]; 9089 u8 mark_cnp[0x1]; 9090 u8 reserved_at_43[0x1b]; 9091 u8 tx_lossy_overflow_oper[0x2]; 9092 9093 u8 reserved_at_60[0x100]; 9094 }; 9095 9096 struct mlx5_ifc_pcam_enhanced_features_bits { 9097 u8 reserved_at_0[0x68]; 9098 u8 fec_50G_per_lane_in_pplm[0x1]; 9099 u8 reserved_at_69[0x4]; 9100 u8 rx_icrc_encapsulated_counter[0x1]; 9101 u8 reserved_at_6e[0x4]; 9102 u8 ptys_extended_ethernet[0x1]; 9103 u8 reserved_at_73[0x3]; 9104 u8 pfcc_mask[0x1]; 9105 u8 reserved_at_77[0x3]; 9106 u8 per_lane_error_counters[0x1]; 9107 u8 rx_buffer_fullness_counters[0x1]; 9108 u8 ptys_connector_type[0x1]; 9109 u8 reserved_at_7d[0x1]; 9110 u8 ppcnt_discard_group[0x1]; 9111 u8 ppcnt_statistical_group[0x1]; 9112 }; 9113 9114 struct mlx5_ifc_pcam_regs_5000_to_507f_bits { 9115 u8 port_access_reg_cap_mask_127_to_96[0x20]; 9116 u8 port_access_reg_cap_mask_95_to_64[0x20]; 9117 9118 u8 port_access_reg_cap_mask_63_to_36[0x1c]; 9119 u8 pplm[0x1]; 9120 u8 port_access_reg_cap_mask_34_to_32[0x3]; 9121 9122 u8 port_access_reg_cap_mask_31_to_13[0x13]; 9123 u8 pbmc[0x1]; 9124 u8 pptb[0x1]; 9125 u8 port_access_reg_cap_mask_10_to_09[0x2]; 9126 u8 ppcnt[0x1]; 9127 u8 port_access_reg_cap_mask_07_to_00[0x8]; 9128 }; 9129 9130 struct mlx5_ifc_pcam_reg_bits { 9131 u8 reserved_at_0[0x8]; 9132 u8 feature_group[0x8]; 9133 u8 reserved_at_10[0x8]; 9134 u8 access_reg_group[0x8]; 9135 9136 u8 reserved_at_20[0x20]; 9137 9138 union { 9139 struct mlx5_ifc_pcam_regs_5000_to_507f_bits regs_5000_to_507f; 9140 u8 reserved_at_0[0x80]; 9141 } port_access_reg_cap_mask; 9142 9143 u8 reserved_at_c0[0x80]; 9144 9145 union { 9146 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features; 9147 u8 reserved_at_0[0x80]; 9148 } feature_cap_mask; 9149 9150 u8 reserved_at_1c0[0xc0]; 9151 }; 9152 9153 struct mlx5_ifc_mcam_enhanced_features_bits { 9154 u8 reserved_at_0[0x6e]; 9155 u8 pci_status_and_power[0x1]; 9156 u8 reserved_at_6f[0x5]; 9157 u8 mark_tx_action_cnp[0x1]; 9158 u8 mark_tx_action_cqe[0x1]; 9159 u8 dynamic_tx_overflow[0x1]; 9160 u8 reserved_at_77[0x4]; 9161 u8 pcie_outbound_stalled[0x1]; 9162 u8 tx_overflow_buffer_pkt[0x1]; 9163 u8 mtpps_enh_out_per_adj[0x1]; 9164 u8 mtpps_fs[0x1]; 9165 u8 pcie_performance_group[0x1]; 9166 }; 9167 9168 struct mlx5_ifc_mcam_access_reg_bits { 9169 u8 reserved_at_0[0x1c]; 9170 u8 mcda[0x1]; 9171 u8 mcc[0x1]; 9172 u8 mcqi[0x1]; 9173 u8 mcqs[0x1]; 9174 9175 u8 regs_95_to_87[0x9]; 9176 u8 mpegc[0x1]; 9177 u8 regs_85_to_68[0x12]; 9178 u8 tracer_registers[0x4]; 9179 9180 u8 regs_63_to_32[0x20]; 9181 u8 regs_31_to_0[0x20]; 9182 }; 9183 9184 struct mlx5_ifc_mcam_access_reg_bits1 { 9185 u8 regs_127_to_96[0x20]; 9186 9187 u8 regs_95_to_64[0x20]; 9188 9189 u8 regs_63_to_32[0x20]; 9190 9191 u8 regs_31_to_0[0x20]; 9192 }; 9193 9194 struct mlx5_ifc_mcam_access_reg_bits2 { 9195 u8 regs_127_to_99[0x1d]; 9196 u8 mirc[0x1]; 9197 u8 regs_97_to_96[0x2]; 9198 9199 u8 regs_95_to_64[0x20]; 9200 9201 u8 regs_63_to_32[0x20]; 9202 9203 u8 regs_31_to_0[0x20]; 9204 }; 9205 9206 struct mlx5_ifc_mcam_reg_bits { 9207 u8 reserved_at_0[0x8]; 9208 u8 feature_group[0x8]; 9209 u8 reserved_at_10[0x8]; 9210 u8 access_reg_group[0x8]; 9211 9212 u8 reserved_at_20[0x20]; 9213 9214 union { 9215 struct mlx5_ifc_mcam_access_reg_bits access_regs; 9216 struct mlx5_ifc_mcam_access_reg_bits1 access_regs1; 9217 struct mlx5_ifc_mcam_access_reg_bits2 access_regs2; 9218 u8 reserved_at_0[0x80]; 9219 } mng_access_reg_cap_mask; 9220 9221 u8 reserved_at_c0[0x80]; 9222 9223 union { 9224 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features; 9225 u8 reserved_at_0[0x80]; 9226 } mng_feature_cap_mask; 9227 9228 u8 reserved_at_1c0[0x80]; 9229 }; 9230 9231 struct mlx5_ifc_qcam_access_reg_cap_mask { 9232 u8 qcam_access_reg_cap_mask_127_to_20[0x6C]; 9233 u8 qpdpm[0x1]; 9234 u8 qcam_access_reg_cap_mask_18_to_4[0x0F]; 9235 u8 qdpm[0x1]; 9236 u8 qpts[0x1]; 9237 u8 qcap[0x1]; 9238 u8 qcam_access_reg_cap_mask_0[0x1]; 9239 }; 9240 9241 struct mlx5_ifc_qcam_qos_feature_cap_mask { 9242 u8 qcam_qos_feature_cap_mask_127_to_1[0x7F]; 9243 u8 qpts_trust_both[0x1]; 9244 }; 9245 9246 struct mlx5_ifc_qcam_reg_bits { 9247 u8 reserved_at_0[0x8]; 9248 u8 feature_group[0x8]; 9249 u8 reserved_at_10[0x8]; 9250 u8 access_reg_group[0x8]; 9251 u8 reserved_at_20[0x20]; 9252 9253 union { 9254 struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap; 9255 u8 reserved_at_0[0x80]; 9256 } qos_access_reg_cap_mask; 9257 9258 u8 reserved_at_c0[0x80]; 9259 9260 union { 9261 struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap; 9262 u8 reserved_at_0[0x80]; 9263 } qos_feature_cap_mask; 9264 9265 u8 reserved_at_1c0[0x80]; 9266 }; 9267 9268 struct mlx5_ifc_core_dump_reg_bits { 9269 u8 reserved_at_0[0x18]; 9270 u8 core_dump_type[0x8]; 9271 9272 u8 reserved_at_20[0x30]; 9273 u8 vhca_id[0x10]; 9274 9275 u8 reserved_at_60[0x8]; 9276 u8 qpn[0x18]; 9277 u8 reserved_at_80[0x180]; 9278 }; 9279 9280 struct mlx5_ifc_pcap_reg_bits { 9281 u8 reserved_at_0[0x8]; 9282 u8 local_port[0x8]; 9283 u8 reserved_at_10[0x10]; 9284 9285 u8 port_capability_mask[4][0x20]; 9286 }; 9287 9288 struct mlx5_ifc_paos_reg_bits { 9289 u8 swid[0x8]; 9290 u8 local_port[0x8]; 9291 u8 reserved_at_10[0x4]; 9292 u8 admin_status[0x4]; 9293 u8 reserved_at_18[0x4]; 9294 u8 oper_status[0x4]; 9295 9296 u8 ase[0x1]; 9297 u8 ee[0x1]; 9298 u8 reserved_at_22[0x1c]; 9299 u8 e[0x2]; 9300 9301 u8 reserved_at_40[0x40]; 9302 }; 9303 9304 struct mlx5_ifc_pamp_reg_bits { 9305 u8 reserved_at_0[0x8]; 9306 u8 opamp_group[0x8]; 9307 u8 reserved_at_10[0xc]; 9308 u8 opamp_group_type[0x4]; 9309 9310 u8 start_index[0x10]; 9311 u8 reserved_at_30[0x4]; 9312 u8 num_of_indices[0xc]; 9313 9314 u8 index_data[18][0x10]; 9315 }; 9316 9317 struct mlx5_ifc_pcmr_reg_bits { 9318 u8 reserved_at_0[0x8]; 9319 u8 local_port[0x8]; 9320 u8 reserved_at_10[0x10]; 9321 u8 entropy_force_cap[0x1]; 9322 u8 entropy_calc_cap[0x1]; 9323 u8 entropy_gre_calc_cap[0x1]; 9324 u8 reserved_at_23[0x1b]; 9325 u8 fcs_cap[0x1]; 9326 u8 reserved_at_3f[0x1]; 9327 u8 entropy_force[0x1]; 9328 u8 entropy_calc[0x1]; 9329 u8 entropy_gre_calc[0x1]; 9330 u8 reserved_at_43[0x1b]; 9331 u8 fcs_chk[0x1]; 9332 u8 reserved_at_5f[0x1]; 9333 }; 9334 9335 struct mlx5_ifc_lane_2_module_mapping_bits { 9336 u8 reserved_at_0[0x6]; 9337 u8 rx_lane[0x2]; 9338 u8 reserved_at_8[0x6]; 9339 u8 tx_lane[0x2]; 9340 u8 reserved_at_10[0x8]; 9341 u8 module[0x8]; 9342 }; 9343 9344 struct mlx5_ifc_bufferx_reg_bits { 9345 u8 reserved_at_0[0x6]; 9346 u8 lossy[0x1]; 9347 u8 epsb[0x1]; 9348 u8 reserved_at_8[0xc]; 9349 u8 size[0xc]; 9350 9351 u8 xoff_threshold[0x10]; 9352 u8 xon_threshold[0x10]; 9353 }; 9354 9355 struct mlx5_ifc_set_node_in_bits { 9356 u8 node_description[64][0x8]; 9357 }; 9358 9359 struct mlx5_ifc_register_power_settings_bits { 9360 u8 reserved_at_0[0x18]; 9361 u8 power_settings_level[0x8]; 9362 9363 u8 reserved_at_20[0x60]; 9364 }; 9365 9366 struct mlx5_ifc_register_host_endianness_bits { 9367 u8 he[0x1]; 9368 u8 reserved_at_1[0x1f]; 9369 9370 u8 reserved_at_20[0x60]; 9371 }; 9372 9373 struct mlx5_ifc_umr_pointer_desc_argument_bits { 9374 u8 reserved_at_0[0x20]; 9375 9376 u8 mkey[0x20]; 9377 9378 u8 addressh_63_32[0x20]; 9379 9380 u8 addressl_31_0[0x20]; 9381 }; 9382 9383 struct mlx5_ifc_ud_adrs_vector_bits { 9384 u8 dc_key[0x40]; 9385 9386 u8 ext[0x1]; 9387 u8 reserved_at_41[0x7]; 9388 u8 destination_qp_dct[0x18]; 9389 9390 u8 static_rate[0x4]; 9391 u8 sl_eth_prio[0x4]; 9392 u8 fl[0x1]; 9393 u8 mlid[0x7]; 9394 u8 rlid_udp_sport[0x10]; 9395 9396 u8 reserved_at_80[0x20]; 9397 9398 u8 rmac_47_16[0x20]; 9399 9400 u8 rmac_15_0[0x10]; 9401 u8 tclass[0x8]; 9402 u8 hop_limit[0x8]; 9403 9404 u8 reserved_at_e0[0x1]; 9405 u8 grh[0x1]; 9406 u8 reserved_at_e2[0x2]; 9407 u8 src_addr_index[0x8]; 9408 u8 flow_label[0x14]; 9409 9410 u8 rgid_rip[16][0x8]; 9411 }; 9412 9413 struct mlx5_ifc_pages_req_event_bits { 9414 u8 reserved_at_0[0x10]; 9415 u8 function_id[0x10]; 9416 9417 u8 num_pages[0x20]; 9418 9419 u8 reserved_at_40[0xa0]; 9420 }; 9421 9422 struct mlx5_ifc_eqe_bits { 9423 u8 reserved_at_0[0x8]; 9424 u8 event_type[0x8]; 9425 u8 reserved_at_10[0x8]; 9426 u8 event_sub_type[0x8]; 9427 9428 u8 reserved_at_20[0xe0]; 9429 9430 union mlx5_ifc_event_auto_bits event_data; 9431 9432 u8 reserved_at_1e0[0x10]; 9433 u8 signature[0x8]; 9434 u8 reserved_at_1f8[0x7]; 9435 u8 owner[0x1]; 9436 }; 9437 9438 enum { 9439 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7, 9440 }; 9441 9442 struct mlx5_ifc_cmd_queue_entry_bits { 9443 u8 type[0x8]; 9444 u8 reserved_at_8[0x18]; 9445 9446 u8 input_length[0x20]; 9447 9448 u8 input_mailbox_pointer_63_32[0x20]; 9449 9450 u8 input_mailbox_pointer_31_9[0x17]; 9451 u8 reserved_at_77[0x9]; 9452 9453 u8 command_input_inline_data[16][0x8]; 9454 9455 u8 command_output_inline_data[16][0x8]; 9456 9457 u8 output_mailbox_pointer_63_32[0x20]; 9458 9459 u8 output_mailbox_pointer_31_9[0x17]; 9460 u8 reserved_at_1b7[0x9]; 9461 9462 u8 output_length[0x20]; 9463 9464 u8 token[0x8]; 9465 u8 signature[0x8]; 9466 u8 reserved_at_1f0[0x8]; 9467 u8 status[0x7]; 9468 u8 ownership[0x1]; 9469 }; 9470 9471 struct mlx5_ifc_cmd_out_bits { 9472 u8 status[0x8]; 9473 u8 reserved_at_8[0x18]; 9474 9475 u8 syndrome[0x20]; 9476 9477 u8 command_output[0x20]; 9478 }; 9479 9480 struct mlx5_ifc_cmd_in_bits { 9481 u8 opcode[0x10]; 9482 u8 reserved_at_10[0x10]; 9483 9484 u8 reserved_at_20[0x10]; 9485 u8 op_mod[0x10]; 9486 9487 u8 command[][0x20]; 9488 }; 9489 9490 struct mlx5_ifc_cmd_if_box_bits { 9491 u8 mailbox_data[512][0x8]; 9492 9493 u8 reserved_at_1000[0x180]; 9494 9495 u8 next_pointer_63_32[0x20]; 9496 9497 u8 next_pointer_31_10[0x16]; 9498 u8 reserved_at_11b6[0xa]; 9499 9500 u8 block_number[0x20]; 9501 9502 u8 reserved_at_11e0[0x8]; 9503 u8 token[0x8]; 9504 u8 ctrl_signature[0x8]; 9505 u8 signature[0x8]; 9506 }; 9507 9508 struct mlx5_ifc_mtt_bits { 9509 u8 ptag_63_32[0x20]; 9510 9511 u8 ptag_31_8[0x18]; 9512 u8 reserved_at_38[0x6]; 9513 u8 wr_en[0x1]; 9514 u8 rd_en[0x1]; 9515 }; 9516 9517 struct mlx5_ifc_query_wol_rol_out_bits { 9518 u8 status[0x8]; 9519 u8 reserved_at_8[0x18]; 9520 9521 u8 syndrome[0x20]; 9522 9523 u8 reserved_at_40[0x10]; 9524 u8 rol_mode[0x8]; 9525 u8 wol_mode[0x8]; 9526 9527 u8 reserved_at_60[0x20]; 9528 }; 9529 9530 struct mlx5_ifc_query_wol_rol_in_bits { 9531 u8 opcode[0x10]; 9532 u8 reserved_at_10[0x10]; 9533 9534 u8 reserved_at_20[0x10]; 9535 u8 op_mod[0x10]; 9536 9537 u8 reserved_at_40[0x40]; 9538 }; 9539 9540 struct mlx5_ifc_set_wol_rol_out_bits { 9541 u8 status[0x8]; 9542 u8 reserved_at_8[0x18]; 9543 9544 u8 syndrome[0x20]; 9545 9546 u8 reserved_at_40[0x40]; 9547 }; 9548 9549 struct mlx5_ifc_set_wol_rol_in_bits { 9550 u8 opcode[0x10]; 9551 u8 reserved_at_10[0x10]; 9552 9553 u8 reserved_at_20[0x10]; 9554 u8 op_mod[0x10]; 9555 9556 u8 rol_mode_valid[0x1]; 9557 u8 wol_mode_valid[0x1]; 9558 u8 reserved_at_42[0xe]; 9559 u8 rol_mode[0x8]; 9560 u8 wol_mode[0x8]; 9561 9562 u8 reserved_at_60[0x20]; 9563 }; 9564 9565 enum { 9566 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0, 9567 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1, 9568 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2, 9569 }; 9570 9571 enum { 9572 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0, 9573 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1, 9574 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2, 9575 }; 9576 9577 enum { 9578 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR = 0x1, 9579 MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC = 0x7, 9580 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR = 0x8, 9581 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR = 0x9, 9582 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR = 0xa, 9583 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR = 0xb, 9584 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN = 0xc, 9585 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR = 0xd, 9586 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV = 0xe, 9587 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR = 0xf, 9588 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR = 0x10, 9589 }; 9590 9591 struct mlx5_ifc_initial_seg_bits { 9592 u8 fw_rev_minor[0x10]; 9593 u8 fw_rev_major[0x10]; 9594 9595 u8 cmd_interface_rev[0x10]; 9596 u8 fw_rev_subminor[0x10]; 9597 9598 u8 reserved_at_40[0x40]; 9599 9600 u8 cmdq_phy_addr_63_32[0x20]; 9601 9602 u8 cmdq_phy_addr_31_12[0x14]; 9603 u8 reserved_at_b4[0x2]; 9604 u8 nic_interface[0x2]; 9605 u8 log_cmdq_size[0x4]; 9606 u8 log_cmdq_stride[0x4]; 9607 9608 u8 command_doorbell_vector[0x20]; 9609 9610 u8 reserved_at_e0[0xf00]; 9611 9612 u8 initializing[0x1]; 9613 u8 reserved_at_fe1[0x4]; 9614 u8 nic_interface_supported[0x3]; 9615 u8 embedded_cpu[0x1]; 9616 u8 reserved_at_fe9[0x17]; 9617 9618 struct mlx5_ifc_health_buffer_bits health_buffer; 9619 9620 u8 no_dram_nic_offset[0x20]; 9621 9622 u8 reserved_at_1220[0x6e40]; 9623 9624 u8 reserved_at_8060[0x1f]; 9625 u8 clear_int[0x1]; 9626 9627 u8 health_syndrome[0x8]; 9628 u8 health_counter[0x18]; 9629 9630 u8 reserved_at_80a0[0x17fc0]; 9631 }; 9632 9633 struct mlx5_ifc_mtpps_reg_bits { 9634 u8 reserved_at_0[0xc]; 9635 u8 cap_number_of_pps_pins[0x4]; 9636 u8 reserved_at_10[0x4]; 9637 u8 cap_max_num_of_pps_in_pins[0x4]; 9638 u8 reserved_at_18[0x4]; 9639 u8 cap_max_num_of_pps_out_pins[0x4]; 9640 9641 u8 reserved_at_20[0x24]; 9642 u8 cap_pin_3_mode[0x4]; 9643 u8 reserved_at_48[0x4]; 9644 u8 cap_pin_2_mode[0x4]; 9645 u8 reserved_at_50[0x4]; 9646 u8 cap_pin_1_mode[0x4]; 9647 u8 reserved_at_58[0x4]; 9648 u8 cap_pin_0_mode[0x4]; 9649 9650 u8 reserved_at_60[0x4]; 9651 u8 cap_pin_7_mode[0x4]; 9652 u8 reserved_at_68[0x4]; 9653 u8 cap_pin_6_mode[0x4]; 9654 u8 reserved_at_70[0x4]; 9655 u8 cap_pin_5_mode[0x4]; 9656 u8 reserved_at_78[0x4]; 9657 u8 cap_pin_4_mode[0x4]; 9658 9659 u8 field_select[0x20]; 9660 u8 reserved_at_a0[0x60]; 9661 9662 u8 enable[0x1]; 9663 u8 reserved_at_101[0xb]; 9664 u8 pattern[0x4]; 9665 u8 reserved_at_110[0x4]; 9666 u8 pin_mode[0x4]; 9667 u8 pin[0x8]; 9668 9669 u8 reserved_at_120[0x20]; 9670 9671 u8 time_stamp[0x40]; 9672 9673 u8 out_pulse_duration[0x10]; 9674 u8 out_periodic_adjustment[0x10]; 9675 u8 enhanced_out_periodic_adjustment[0x20]; 9676 9677 u8 reserved_at_1c0[0x20]; 9678 }; 9679 9680 struct mlx5_ifc_mtppse_reg_bits { 9681 u8 reserved_at_0[0x18]; 9682 u8 pin[0x8]; 9683 u8 event_arm[0x1]; 9684 u8 reserved_at_21[0x1b]; 9685 u8 event_generation_mode[0x4]; 9686 u8 reserved_at_40[0x40]; 9687 }; 9688 9689 struct mlx5_ifc_mcqs_reg_bits { 9690 u8 last_index_flag[0x1]; 9691 u8 reserved_at_1[0x7]; 9692 u8 fw_device[0x8]; 9693 u8 component_index[0x10]; 9694 9695 u8 reserved_at_20[0x10]; 9696 u8 identifier[0x10]; 9697 9698 u8 reserved_at_40[0x17]; 9699 u8 component_status[0x5]; 9700 u8 component_update_state[0x4]; 9701 9702 u8 last_update_state_changer_type[0x4]; 9703 u8 last_update_state_changer_host_id[0x4]; 9704 u8 reserved_at_68[0x18]; 9705 }; 9706 9707 struct mlx5_ifc_mcqi_cap_bits { 9708 u8 supported_info_bitmask[0x20]; 9709 9710 u8 component_size[0x20]; 9711 9712 u8 max_component_size[0x20]; 9713 9714 u8 log_mcda_word_size[0x4]; 9715 u8 reserved_at_64[0xc]; 9716 u8 mcda_max_write_size[0x10]; 9717 9718 u8 rd_en[0x1]; 9719 u8 reserved_at_81[0x1]; 9720 u8 match_chip_id[0x1]; 9721 u8 match_psid[0x1]; 9722 u8 check_user_timestamp[0x1]; 9723 u8 match_base_guid_mac[0x1]; 9724 u8 reserved_at_86[0x1a]; 9725 }; 9726 9727 struct mlx5_ifc_mcqi_version_bits { 9728 u8 reserved_at_0[0x2]; 9729 u8 build_time_valid[0x1]; 9730 u8 user_defined_time_valid[0x1]; 9731 u8 reserved_at_4[0x14]; 9732 u8 version_string_length[0x8]; 9733 9734 u8 version[0x20]; 9735 9736 u8 build_time[0x40]; 9737 9738 u8 user_defined_time[0x40]; 9739 9740 u8 build_tool_version[0x20]; 9741 9742 u8 reserved_at_e0[0x20]; 9743 9744 u8 version_string[92][0x8]; 9745 }; 9746 9747 struct mlx5_ifc_mcqi_activation_method_bits { 9748 u8 pending_server_ac_power_cycle[0x1]; 9749 u8 pending_server_dc_power_cycle[0x1]; 9750 u8 pending_server_reboot[0x1]; 9751 u8 pending_fw_reset[0x1]; 9752 u8 auto_activate[0x1]; 9753 u8 all_hosts_sync[0x1]; 9754 u8 device_hw_reset[0x1]; 9755 u8 reserved_at_7[0x19]; 9756 }; 9757 9758 union mlx5_ifc_mcqi_reg_data_bits { 9759 struct mlx5_ifc_mcqi_cap_bits mcqi_caps; 9760 struct mlx5_ifc_mcqi_version_bits mcqi_version; 9761 struct mlx5_ifc_mcqi_activation_method_bits mcqi_activation_mathod; 9762 }; 9763 9764 struct mlx5_ifc_mcqi_reg_bits { 9765 u8 read_pending_component[0x1]; 9766 u8 reserved_at_1[0xf]; 9767 u8 component_index[0x10]; 9768 9769 u8 reserved_at_20[0x20]; 9770 9771 u8 reserved_at_40[0x1b]; 9772 u8 info_type[0x5]; 9773 9774 u8 info_size[0x20]; 9775 9776 u8 offset[0x20]; 9777 9778 u8 reserved_at_a0[0x10]; 9779 u8 data_size[0x10]; 9780 9781 union mlx5_ifc_mcqi_reg_data_bits data[]; 9782 }; 9783 9784 struct mlx5_ifc_mcc_reg_bits { 9785 u8 reserved_at_0[0x4]; 9786 u8 time_elapsed_since_last_cmd[0xc]; 9787 u8 reserved_at_10[0x8]; 9788 u8 instruction[0x8]; 9789 9790 u8 reserved_at_20[0x10]; 9791 u8 component_index[0x10]; 9792 9793 u8 reserved_at_40[0x8]; 9794 u8 update_handle[0x18]; 9795 9796 u8 handle_owner_type[0x4]; 9797 u8 handle_owner_host_id[0x4]; 9798 u8 reserved_at_68[0x1]; 9799 u8 control_progress[0x7]; 9800 u8 error_code[0x8]; 9801 u8 reserved_at_78[0x4]; 9802 u8 control_state[0x4]; 9803 9804 u8 component_size[0x20]; 9805 9806 u8 reserved_at_a0[0x60]; 9807 }; 9808 9809 struct mlx5_ifc_mcda_reg_bits { 9810 u8 reserved_at_0[0x8]; 9811 u8 update_handle[0x18]; 9812 9813 u8 offset[0x20]; 9814 9815 u8 reserved_at_40[0x10]; 9816 u8 size[0x10]; 9817 9818 u8 reserved_at_60[0x20]; 9819 9820 u8 data[][0x20]; 9821 }; 9822 9823 enum { 9824 MLX5_MFRL_REG_RESET_TYPE_FULL_CHIP = BIT(0), 9825 MLX5_MFRL_REG_RESET_TYPE_NET_PORT_ALIVE = BIT(1), 9826 }; 9827 9828 enum { 9829 MLX5_MFRL_REG_RESET_LEVEL0 = BIT(0), 9830 MLX5_MFRL_REG_RESET_LEVEL3 = BIT(3), 9831 MLX5_MFRL_REG_RESET_LEVEL6 = BIT(6), 9832 }; 9833 9834 struct mlx5_ifc_mfrl_reg_bits { 9835 u8 reserved_at_0[0x20]; 9836 9837 u8 reserved_at_20[0x2]; 9838 u8 pci_sync_for_fw_update_start[0x1]; 9839 u8 pci_sync_for_fw_update_resp[0x2]; 9840 u8 rst_type_sel[0x3]; 9841 u8 reserved_at_28[0x8]; 9842 u8 reset_type[0x8]; 9843 u8 reset_level[0x8]; 9844 }; 9845 9846 struct mlx5_ifc_mirc_reg_bits { 9847 u8 reserved_at_0[0x18]; 9848 u8 status_code[0x8]; 9849 9850 u8 reserved_at_20[0x20]; 9851 }; 9852 9853 union mlx5_ifc_ports_control_registers_document_bits { 9854 struct mlx5_ifc_bufferx_reg_bits bufferx_reg; 9855 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 9856 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 9857 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 9858 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 9859 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 9860 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 9861 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout; 9862 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout; 9863 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping; 9864 struct mlx5_ifc_pamp_reg_bits pamp_reg; 9865 struct mlx5_ifc_paos_reg_bits paos_reg; 9866 struct mlx5_ifc_pcap_reg_bits pcap_reg; 9867 struct mlx5_ifc_peir_reg_bits peir_reg; 9868 struct mlx5_ifc_pelc_reg_bits pelc_reg; 9869 struct mlx5_ifc_pfcc_reg_bits pfcc_reg; 9870 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 9871 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 9872 struct mlx5_ifc_pifr_reg_bits pifr_reg; 9873 struct mlx5_ifc_pipg_reg_bits pipg_reg; 9874 struct mlx5_ifc_plbf_reg_bits plbf_reg; 9875 struct mlx5_ifc_plib_reg_bits plib_reg; 9876 struct mlx5_ifc_plpc_reg_bits plpc_reg; 9877 struct mlx5_ifc_pmaos_reg_bits pmaos_reg; 9878 struct mlx5_ifc_pmlp_reg_bits pmlp_reg; 9879 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg; 9880 struct mlx5_ifc_pmpc_reg_bits pmpc_reg; 9881 struct mlx5_ifc_pmpe_reg_bits pmpe_reg; 9882 struct mlx5_ifc_pmpr_reg_bits pmpr_reg; 9883 struct mlx5_ifc_pmtu_reg_bits pmtu_reg; 9884 struct mlx5_ifc_ppad_reg_bits ppad_reg; 9885 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg; 9886 struct mlx5_ifc_mpein_reg_bits mpein_reg; 9887 struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg; 9888 struct mlx5_ifc_pplm_reg_bits pplm_reg; 9889 struct mlx5_ifc_pplr_reg_bits pplr_reg; 9890 struct mlx5_ifc_ppsc_reg_bits ppsc_reg; 9891 struct mlx5_ifc_pqdr_reg_bits pqdr_reg; 9892 struct mlx5_ifc_pspa_reg_bits pspa_reg; 9893 struct mlx5_ifc_ptas_reg_bits ptas_reg; 9894 struct mlx5_ifc_ptys_reg_bits ptys_reg; 9895 struct mlx5_ifc_mlcr_reg_bits mlcr_reg; 9896 struct mlx5_ifc_pude_reg_bits pude_reg; 9897 struct mlx5_ifc_pvlc_reg_bits pvlc_reg; 9898 struct mlx5_ifc_slrg_reg_bits slrg_reg; 9899 struct mlx5_ifc_sltp_reg_bits sltp_reg; 9900 struct mlx5_ifc_mtpps_reg_bits mtpps_reg; 9901 struct mlx5_ifc_mtppse_reg_bits mtppse_reg; 9902 struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg; 9903 struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits; 9904 struct mlx5_ifc_fpga_cap_bits fpga_cap_bits; 9905 struct mlx5_ifc_mcqi_reg_bits mcqi_reg; 9906 struct mlx5_ifc_mcc_reg_bits mcc_reg; 9907 struct mlx5_ifc_mcda_reg_bits mcda_reg; 9908 struct mlx5_ifc_mirc_reg_bits mirc_reg; 9909 struct mlx5_ifc_mfrl_reg_bits mfrl_reg; 9910 u8 reserved_at_0[0x60e0]; 9911 }; 9912 9913 union mlx5_ifc_debug_enhancements_document_bits { 9914 struct mlx5_ifc_health_buffer_bits health_buffer; 9915 u8 reserved_at_0[0x200]; 9916 }; 9917 9918 union mlx5_ifc_uplink_pci_interface_document_bits { 9919 struct mlx5_ifc_initial_seg_bits initial_seg; 9920 u8 reserved_at_0[0x20060]; 9921 }; 9922 9923 struct mlx5_ifc_set_flow_table_root_out_bits { 9924 u8 status[0x8]; 9925 u8 reserved_at_8[0x18]; 9926 9927 u8 syndrome[0x20]; 9928 9929 u8 reserved_at_40[0x40]; 9930 }; 9931 9932 struct mlx5_ifc_set_flow_table_root_in_bits { 9933 u8 opcode[0x10]; 9934 u8 reserved_at_10[0x10]; 9935 9936 u8 reserved_at_20[0x10]; 9937 u8 op_mod[0x10]; 9938 9939 u8 other_vport[0x1]; 9940 u8 reserved_at_41[0xf]; 9941 u8 vport_number[0x10]; 9942 9943 u8 reserved_at_60[0x20]; 9944 9945 u8 table_type[0x8]; 9946 u8 reserved_at_88[0x18]; 9947 9948 u8 reserved_at_a0[0x8]; 9949 u8 table_id[0x18]; 9950 9951 u8 reserved_at_c0[0x8]; 9952 u8 underlay_qpn[0x18]; 9953 u8 reserved_at_e0[0x120]; 9954 }; 9955 9956 enum { 9957 MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = (1UL << 0), 9958 MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15), 9959 }; 9960 9961 struct mlx5_ifc_modify_flow_table_out_bits { 9962 u8 status[0x8]; 9963 u8 reserved_at_8[0x18]; 9964 9965 u8 syndrome[0x20]; 9966 9967 u8 reserved_at_40[0x40]; 9968 }; 9969 9970 struct mlx5_ifc_modify_flow_table_in_bits { 9971 u8 opcode[0x10]; 9972 u8 reserved_at_10[0x10]; 9973 9974 u8 reserved_at_20[0x10]; 9975 u8 op_mod[0x10]; 9976 9977 u8 other_vport[0x1]; 9978 u8 reserved_at_41[0xf]; 9979 u8 vport_number[0x10]; 9980 9981 u8 reserved_at_60[0x10]; 9982 u8 modify_field_select[0x10]; 9983 9984 u8 table_type[0x8]; 9985 u8 reserved_at_88[0x18]; 9986 9987 u8 reserved_at_a0[0x8]; 9988 u8 table_id[0x18]; 9989 9990 struct mlx5_ifc_flow_table_context_bits flow_table_context; 9991 }; 9992 9993 struct mlx5_ifc_ets_tcn_config_reg_bits { 9994 u8 g[0x1]; 9995 u8 b[0x1]; 9996 u8 r[0x1]; 9997 u8 reserved_at_3[0x9]; 9998 u8 group[0x4]; 9999 u8 reserved_at_10[0x9]; 10000 u8 bw_allocation[0x7]; 10001 10002 u8 reserved_at_20[0xc]; 10003 u8 max_bw_units[0x4]; 10004 u8 reserved_at_30[0x8]; 10005 u8 max_bw_value[0x8]; 10006 }; 10007 10008 struct mlx5_ifc_ets_global_config_reg_bits { 10009 u8 reserved_at_0[0x2]; 10010 u8 r[0x1]; 10011 u8 reserved_at_3[0x1d]; 10012 10013 u8 reserved_at_20[0xc]; 10014 u8 max_bw_units[0x4]; 10015 u8 reserved_at_30[0x8]; 10016 u8 max_bw_value[0x8]; 10017 }; 10018 10019 struct mlx5_ifc_qetc_reg_bits { 10020 u8 reserved_at_0[0x8]; 10021 u8 port_number[0x8]; 10022 u8 reserved_at_10[0x30]; 10023 10024 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8]; 10025 struct mlx5_ifc_ets_global_config_reg_bits global_configuration; 10026 }; 10027 10028 struct mlx5_ifc_qpdpm_dscp_reg_bits { 10029 u8 e[0x1]; 10030 u8 reserved_at_01[0x0b]; 10031 u8 prio[0x04]; 10032 }; 10033 10034 struct mlx5_ifc_qpdpm_reg_bits { 10035 u8 reserved_at_0[0x8]; 10036 u8 local_port[0x8]; 10037 u8 reserved_at_10[0x10]; 10038 struct mlx5_ifc_qpdpm_dscp_reg_bits dscp[64]; 10039 }; 10040 10041 struct mlx5_ifc_qpts_reg_bits { 10042 u8 reserved_at_0[0x8]; 10043 u8 local_port[0x8]; 10044 u8 reserved_at_10[0x2d]; 10045 u8 trust_state[0x3]; 10046 }; 10047 10048 struct mlx5_ifc_pptb_reg_bits { 10049 u8 reserved_at_0[0x2]; 10050 u8 mm[0x2]; 10051 u8 reserved_at_4[0x4]; 10052 u8 local_port[0x8]; 10053 u8 reserved_at_10[0x6]; 10054 u8 cm[0x1]; 10055 u8 um[0x1]; 10056 u8 pm[0x8]; 10057 10058 u8 prio_x_buff[0x20]; 10059 10060 u8 pm_msb[0x8]; 10061 u8 reserved_at_48[0x10]; 10062 u8 ctrl_buff[0x4]; 10063 u8 untagged_buff[0x4]; 10064 }; 10065 10066 struct mlx5_ifc_sbcam_reg_bits { 10067 u8 reserved_at_0[0x8]; 10068 u8 feature_group[0x8]; 10069 u8 reserved_at_10[0x8]; 10070 u8 access_reg_group[0x8]; 10071 10072 u8 reserved_at_20[0x20]; 10073 10074 u8 sb_access_reg_cap_mask[4][0x20]; 10075 10076 u8 reserved_at_c0[0x80]; 10077 10078 u8 sb_feature_cap_mask[4][0x20]; 10079 10080 u8 reserved_at_1c0[0x40]; 10081 10082 u8 cap_total_buffer_size[0x20]; 10083 10084 u8 cap_cell_size[0x10]; 10085 u8 cap_max_pg_buffers[0x8]; 10086 u8 cap_num_pool_supported[0x8]; 10087 10088 u8 reserved_at_240[0x8]; 10089 u8 cap_sbsr_stat_size[0x8]; 10090 u8 cap_max_tclass_data[0x8]; 10091 u8 cap_max_cpu_ingress_tclass_sb[0x8]; 10092 }; 10093 10094 struct mlx5_ifc_pbmc_reg_bits { 10095 u8 reserved_at_0[0x8]; 10096 u8 local_port[0x8]; 10097 u8 reserved_at_10[0x10]; 10098 10099 u8 xoff_timer_value[0x10]; 10100 u8 xoff_refresh[0x10]; 10101 10102 u8 reserved_at_40[0x9]; 10103 u8 fullness_threshold[0x7]; 10104 u8 port_buffer_size[0x10]; 10105 10106 struct mlx5_ifc_bufferx_reg_bits buffer[10]; 10107 10108 u8 reserved_at_2e0[0x40]; 10109 }; 10110 10111 struct mlx5_ifc_qtct_reg_bits { 10112 u8 reserved_at_0[0x8]; 10113 u8 port_number[0x8]; 10114 u8 reserved_at_10[0xd]; 10115 u8 prio[0x3]; 10116 10117 u8 reserved_at_20[0x1d]; 10118 u8 tclass[0x3]; 10119 }; 10120 10121 struct mlx5_ifc_mcia_reg_bits { 10122 u8 l[0x1]; 10123 u8 reserved_at_1[0x7]; 10124 u8 module[0x8]; 10125 u8 reserved_at_10[0x8]; 10126 u8 status[0x8]; 10127 10128 u8 i2c_device_address[0x8]; 10129 u8 page_number[0x8]; 10130 u8 device_address[0x10]; 10131 10132 u8 reserved_at_40[0x10]; 10133 u8 size[0x10]; 10134 10135 u8 reserved_at_60[0x20]; 10136 10137 u8 dword_0[0x20]; 10138 u8 dword_1[0x20]; 10139 u8 dword_2[0x20]; 10140 u8 dword_3[0x20]; 10141 u8 dword_4[0x20]; 10142 u8 dword_5[0x20]; 10143 u8 dword_6[0x20]; 10144 u8 dword_7[0x20]; 10145 u8 dword_8[0x20]; 10146 u8 dword_9[0x20]; 10147 u8 dword_10[0x20]; 10148 u8 dword_11[0x20]; 10149 }; 10150 10151 struct mlx5_ifc_dcbx_param_bits { 10152 u8 dcbx_cee_cap[0x1]; 10153 u8 dcbx_ieee_cap[0x1]; 10154 u8 dcbx_standby_cap[0x1]; 10155 u8 reserved_at_3[0x5]; 10156 u8 port_number[0x8]; 10157 u8 reserved_at_10[0xa]; 10158 u8 max_application_table_size[6]; 10159 u8 reserved_at_20[0x15]; 10160 u8 version_oper[0x3]; 10161 u8 reserved_at_38[5]; 10162 u8 version_admin[0x3]; 10163 u8 willing_admin[0x1]; 10164 u8 reserved_at_41[0x3]; 10165 u8 pfc_cap_oper[0x4]; 10166 u8 reserved_at_48[0x4]; 10167 u8 pfc_cap_admin[0x4]; 10168 u8 reserved_at_50[0x4]; 10169 u8 num_of_tc_oper[0x4]; 10170 u8 reserved_at_58[0x4]; 10171 u8 num_of_tc_admin[0x4]; 10172 u8 remote_willing[0x1]; 10173 u8 reserved_at_61[3]; 10174 u8 remote_pfc_cap[4]; 10175 u8 reserved_at_68[0x14]; 10176 u8 remote_num_of_tc[0x4]; 10177 u8 reserved_at_80[0x18]; 10178 u8 error[0x8]; 10179 u8 reserved_at_a0[0x160]; 10180 }; 10181 10182 struct mlx5_ifc_lagc_bits { 10183 u8 reserved_at_0[0x1d]; 10184 u8 lag_state[0x3]; 10185 10186 u8 reserved_at_20[0x14]; 10187 u8 tx_remap_affinity_2[0x4]; 10188 u8 reserved_at_38[0x4]; 10189 u8 tx_remap_affinity_1[0x4]; 10190 }; 10191 10192 struct mlx5_ifc_create_lag_out_bits { 10193 u8 status[0x8]; 10194 u8 reserved_at_8[0x18]; 10195 10196 u8 syndrome[0x20]; 10197 10198 u8 reserved_at_40[0x40]; 10199 }; 10200 10201 struct mlx5_ifc_create_lag_in_bits { 10202 u8 opcode[0x10]; 10203 u8 reserved_at_10[0x10]; 10204 10205 u8 reserved_at_20[0x10]; 10206 u8 op_mod[0x10]; 10207 10208 struct mlx5_ifc_lagc_bits ctx; 10209 }; 10210 10211 struct mlx5_ifc_modify_lag_out_bits { 10212 u8 status[0x8]; 10213 u8 reserved_at_8[0x18]; 10214 10215 u8 syndrome[0x20]; 10216 10217 u8 reserved_at_40[0x40]; 10218 }; 10219 10220 struct mlx5_ifc_modify_lag_in_bits { 10221 u8 opcode[0x10]; 10222 u8 reserved_at_10[0x10]; 10223 10224 u8 reserved_at_20[0x10]; 10225 u8 op_mod[0x10]; 10226 10227 u8 reserved_at_40[0x20]; 10228 u8 field_select[0x20]; 10229 10230 struct mlx5_ifc_lagc_bits ctx; 10231 }; 10232 10233 struct mlx5_ifc_query_lag_out_bits { 10234 u8 status[0x8]; 10235 u8 reserved_at_8[0x18]; 10236 10237 u8 syndrome[0x20]; 10238 10239 struct mlx5_ifc_lagc_bits ctx; 10240 }; 10241 10242 struct mlx5_ifc_query_lag_in_bits { 10243 u8 opcode[0x10]; 10244 u8 reserved_at_10[0x10]; 10245 10246 u8 reserved_at_20[0x10]; 10247 u8 op_mod[0x10]; 10248 10249 u8 reserved_at_40[0x40]; 10250 }; 10251 10252 struct mlx5_ifc_destroy_lag_out_bits { 10253 u8 status[0x8]; 10254 u8 reserved_at_8[0x18]; 10255 10256 u8 syndrome[0x20]; 10257 10258 u8 reserved_at_40[0x40]; 10259 }; 10260 10261 struct mlx5_ifc_destroy_lag_in_bits { 10262 u8 opcode[0x10]; 10263 u8 reserved_at_10[0x10]; 10264 10265 u8 reserved_at_20[0x10]; 10266 u8 op_mod[0x10]; 10267 10268 u8 reserved_at_40[0x40]; 10269 }; 10270 10271 struct mlx5_ifc_create_vport_lag_out_bits { 10272 u8 status[0x8]; 10273 u8 reserved_at_8[0x18]; 10274 10275 u8 syndrome[0x20]; 10276 10277 u8 reserved_at_40[0x40]; 10278 }; 10279 10280 struct mlx5_ifc_create_vport_lag_in_bits { 10281 u8 opcode[0x10]; 10282 u8 reserved_at_10[0x10]; 10283 10284 u8 reserved_at_20[0x10]; 10285 u8 op_mod[0x10]; 10286 10287 u8 reserved_at_40[0x40]; 10288 }; 10289 10290 struct mlx5_ifc_destroy_vport_lag_out_bits { 10291 u8 status[0x8]; 10292 u8 reserved_at_8[0x18]; 10293 10294 u8 syndrome[0x20]; 10295 10296 u8 reserved_at_40[0x40]; 10297 }; 10298 10299 struct mlx5_ifc_destroy_vport_lag_in_bits { 10300 u8 opcode[0x10]; 10301 u8 reserved_at_10[0x10]; 10302 10303 u8 reserved_at_20[0x10]; 10304 u8 op_mod[0x10]; 10305 10306 u8 reserved_at_40[0x40]; 10307 }; 10308 10309 struct mlx5_ifc_alloc_memic_in_bits { 10310 u8 opcode[0x10]; 10311 u8 reserved_at_10[0x10]; 10312 10313 u8 reserved_at_20[0x10]; 10314 u8 op_mod[0x10]; 10315 10316 u8 reserved_at_30[0x20]; 10317 10318 u8 reserved_at_40[0x18]; 10319 u8 log_memic_addr_alignment[0x8]; 10320 10321 u8 range_start_addr[0x40]; 10322 10323 u8 range_size[0x20]; 10324 10325 u8 memic_size[0x20]; 10326 }; 10327 10328 struct mlx5_ifc_alloc_memic_out_bits { 10329 u8 status[0x8]; 10330 u8 reserved_at_8[0x18]; 10331 10332 u8 syndrome[0x20]; 10333 10334 u8 memic_start_addr[0x40]; 10335 }; 10336 10337 struct mlx5_ifc_dealloc_memic_in_bits { 10338 u8 opcode[0x10]; 10339 u8 reserved_at_10[0x10]; 10340 10341 u8 reserved_at_20[0x10]; 10342 u8 op_mod[0x10]; 10343 10344 u8 reserved_at_40[0x40]; 10345 10346 u8 memic_start_addr[0x40]; 10347 10348 u8 memic_size[0x20]; 10349 10350 u8 reserved_at_e0[0x20]; 10351 }; 10352 10353 struct mlx5_ifc_dealloc_memic_out_bits { 10354 u8 status[0x8]; 10355 u8 reserved_at_8[0x18]; 10356 10357 u8 syndrome[0x20]; 10358 10359 u8 reserved_at_40[0x40]; 10360 }; 10361 10362 struct mlx5_ifc_general_obj_in_cmd_hdr_bits { 10363 u8 opcode[0x10]; 10364 u8 uid[0x10]; 10365 10366 u8 vhca_tunnel_id[0x10]; 10367 u8 obj_type[0x10]; 10368 10369 u8 obj_id[0x20]; 10370 10371 u8 reserved_at_60[0x20]; 10372 }; 10373 10374 struct mlx5_ifc_general_obj_out_cmd_hdr_bits { 10375 u8 status[0x8]; 10376 u8 reserved_at_8[0x18]; 10377 10378 u8 syndrome[0x20]; 10379 10380 u8 obj_id[0x20]; 10381 10382 u8 reserved_at_60[0x20]; 10383 }; 10384 10385 struct mlx5_ifc_umem_bits { 10386 u8 reserved_at_0[0x80]; 10387 10388 u8 reserved_at_80[0x1b]; 10389 u8 log_page_size[0x5]; 10390 10391 u8 page_offset[0x20]; 10392 10393 u8 num_of_mtt[0x40]; 10394 10395 struct mlx5_ifc_mtt_bits mtt[]; 10396 }; 10397 10398 struct mlx5_ifc_uctx_bits { 10399 u8 cap[0x20]; 10400 10401 u8 reserved_at_20[0x160]; 10402 }; 10403 10404 struct mlx5_ifc_sw_icm_bits { 10405 u8 modify_field_select[0x40]; 10406 10407 u8 reserved_at_40[0x18]; 10408 u8 log_sw_icm_size[0x8]; 10409 10410 u8 reserved_at_60[0x20]; 10411 10412 u8 sw_icm_start_addr[0x40]; 10413 10414 u8 reserved_at_c0[0x140]; 10415 }; 10416 10417 struct mlx5_ifc_geneve_tlv_option_bits { 10418 u8 modify_field_select[0x40]; 10419 10420 u8 reserved_at_40[0x18]; 10421 u8 geneve_option_fte_index[0x8]; 10422 10423 u8 option_class[0x10]; 10424 u8 option_type[0x8]; 10425 u8 reserved_at_78[0x3]; 10426 u8 option_data_length[0x5]; 10427 10428 u8 reserved_at_80[0x180]; 10429 }; 10430 10431 struct mlx5_ifc_create_umem_in_bits { 10432 u8 opcode[0x10]; 10433 u8 uid[0x10]; 10434 10435 u8 reserved_at_20[0x10]; 10436 u8 op_mod[0x10]; 10437 10438 u8 reserved_at_40[0x40]; 10439 10440 struct mlx5_ifc_umem_bits umem; 10441 }; 10442 10443 struct mlx5_ifc_create_umem_out_bits { 10444 u8 status[0x8]; 10445 u8 reserved_at_8[0x18]; 10446 10447 u8 syndrome[0x20]; 10448 10449 u8 reserved_at_40[0x8]; 10450 u8 umem_id[0x18]; 10451 10452 u8 reserved_at_60[0x20]; 10453 }; 10454 10455 struct mlx5_ifc_destroy_umem_in_bits { 10456 u8 opcode[0x10]; 10457 u8 uid[0x10]; 10458 10459 u8 reserved_at_20[0x10]; 10460 u8 op_mod[0x10]; 10461 10462 u8 reserved_at_40[0x8]; 10463 u8 umem_id[0x18]; 10464 10465 u8 reserved_at_60[0x20]; 10466 }; 10467 10468 struct mlx5_ifc_destroy_umem_out_bits { 10469 u8 status[0x8]; 10470 u8 reserved_at_8[0x18]; 10471 10472 u8 syndrome[0x20]; 10473 10474 u8 reserved_at_40[0x40]; 10475 }; 10476 10477 struct mlx5_ifc_create_uctx_in_bits { 10478 u8 opcode[0x10]; 10479 u8 reserved_at_10[0x10]; 10480 10481 u8 reserved_at_20[0x10]; 10482 u8 op_mod[0x10]; 10483 10484 u8 reserved_at_40[0x40]; 10485 10486 struct mlx5_ifc_uctx_bits uctx; 10487 }; 10488 10489 struct mlx5_ifc_create_uctx_out_bits { 10490 u8 status[0x8]; 10491 u8 reserved_at_8[0x18]; 10492 10493 u8 syndrome[0x20]; 10494 10495 u8 reserved_at_40[0x10]; 10496 u8 uid[0x10]; 10497 10498 u8 reserved_at_60[0x20]; 10499 }; 10500 10501 struct mlx5_ifc_destroy_uctx_in_bits { 10502 u8 opcode[0x10]; 10503 u8 reserved_at_10[0x10]; 10504 10505 u8 reserved_at_20[0x10]; 10506 u8 op_mod[0x10]; 10507 10508 u8 reserved_at_40[0x10]; 10509 u8 uid[0x10]; 10510 10511 u8 reserved_at_60[0x20]; 10512 }; 10513 10514 struct mlx5_ifc_destroy_uctx_out_bits { 10515 u8 status[0x8]; 10516 u8 reserved_at_8[0x18]; 10517 10518 u8 syndrome[0x20]; 10519 10520 u8 reserved_at_40[0x40]; 10521 }; 10522 10523 struct mlx5_ifc_create_sw_icm_in_bits { 10524 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 10525 struct mlx5_ifc_sw_icm_bits sw_icm; 10526 }; 10527 10528 struct mlx5_ifc_create_geneve_tlv_option_in_bits { 10529 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 10530 struct mlx5_ifc_geneve_tlv_option_bits geneve_tlv_opt; 10531 }; 10532 10533 struct mlx5_ifc_mtrc_string_db_param_bits { 10534 u8 string_db_base_address[0x20]; 10535 10536 u8 reserved_at_20[0x8]; 10537 u8 string_db_size[0x18]; 10538 }; 10539 10540 struct mlx5_ifc_mtrc_cap_bits { 10541 u8 trace_owner[0x1]; 10542 u8 trace_to_memory[0x1]; 10543 u8 reserved_at_2[0x4]; 10544 u8 trc_ver[0x2]; 10545 u8 reserved_at_8[0x14]; 10546 u8 num_string_db[0x4]; 10547 10548 u8 first_string_trace[0x8]; 10549 u8 num_string_trace[0x8]; 10550 u8 reserved_at_30[0x28]; 10551 10552 u8 log_max_trace_buffer_size[0x8]; 10553 10554 u8 reserved_at_60[0x20]; 10555 10556 struct mlx5_ifc_mtrc_string_db_param_bits string_db_param[8]; 10557 10558 u8 reserved_at_280[0x180]; 10559 }; 10560 10561 struct mlx5_ifc_mtrc_conf_bits { 10562 u8 reserved_at_0[0x1c]; 10563 u8 trace_mode[0x4]; 10564 u8 reserved_at_20[0x18]; 10565 u8 log_trace_buffer_size[0x8]; 10566 u8 trace_mkey[0x20]; 10567 u8 reserved_at_60[0x3a0]; 10568 }; 10569 10570 struct mlx5_ifc_mtrc_stdb_bits { 10571 u8 string_db_index[0x4]; 10572 u8 reserved_at_4[0x4]; 10573 u8 read_size[0x18]; 10574 u8 start_offset[0x20]; 10575 u8 string_db_data[]; 10576 }; 10577 10578 struct mlx5_ifc_mtrc_ctrl_bits { 10579 u8 trace_status[0x2]; 10580 u8 reserved_at_2[0x2]; 10581 u8 arm_event[0x1]; 10582 u8 reserved_at_5[0xb]; 10583 u8 modify_field_select[0x10]; 10584 u8 reserved_at_20[0x2b]; 10585 u8 current_timestamp52_32[0x15]; 10586 u8 current_timestamp31_0[0x20]; 10587 u8 reserved_at_80[0x180]; 10588 }; 10589 10590 struct mlx5_ifc_host_params_context_bits { 10591 u8 host_number[0x8]; 10592 u8 reserved_at_8[0x7]; 10593 u8 host_pf_disabled[0x1]; 10594 u8 host_num_of_vfs[0x10]; 10595 10596 u8 host_total_vfs[0x10]; 10597 u8 host_pci_bus[0x10]; 10598 10599 u8 reserved_at_40[0x10]; 10600 u8 host_pci_device[0x10]; 10601 10602 u8 reserved_at_60[0x10]; 10603 u8 host_pci_function[0x10]; 10604 10605 u8 reserved_at_80[0x180]; 10606 }; 10607 10608 struct mlx5_ifc_query_esw_functions_in_bits { 10609 u8 opcode[0x10]; 10610 u8 reserved_at_10[0x10]; 10611 10612 u8 reserved_at_20[0x10]; 10613 u8 op_mod[0x10]; 10614 10615 u8 reserved_at_40[0x40]; 10616 }; 10617 10618 struct mlx5_ifc_query_esw_functions_out_bits { 10619 u8 status[0x8]; 10620 u8 reserved_at_8[0x18]; 10621 10622 u8 syndrome[0x20]; 10623 10624 u8 reserved_at_40[0x40]; 10625 10626 struct mlx5_ifc_host_params_context_bits host_params_context; 10627 10628 u8 reserved_at_280[0x180]; 10629 u8 host_sf_enable[][0x40]; 10630 }; 10631 10632 struct mlx5_ifc_sf_partition_bits { 10633 u8 reserved_at_0[0x10]; 10634 u8 log_num_sf[0x8]; 10635 u8 log_sf_bar_size[0x8]; 10636 }; 10637 10638 struct mlx5_ifc_query_sf_partitions_out_bits { 10639 u8 status[0x8]; 10640 u8 reserved_at_8[0x18]; 10641 10642 u8 syndrome[0x20]; 10643 10644 u8 reserved_at_40[0x18]; 10645 u8 num_sf_partitions[0x8]; 10646 10647 u8 reserved_at_60[0x20]; 10648 10649 struct mlx5_ifc_sf_partition_bits sf_partition[]; 10650 }; 10651 10652 struct mlx5_ifc_query_sf_partitions_in_bits { 10653 u8 opcode[0x10]; 10654 u8 reserved_at_10[0x10]; 10655 10656 u8 reserved_at_20[0x10]; 10657 u8 op_mod[0x10]; 10658 10659 u8 reserved_at_40[0x40]; 10660 }; 10661 10662 struct mlx5_ifc_dealloc_sf_out_bits { 10663 u8 status[0x8]; 10664 u8 reserved_at_8[0x18]; 10665 10666 u8 syndrome[0x20]; 10667 10668 u8 reserved_at_40[0x40]; 10669 }; 10670 10671 struct mlx5_ifc_dealloc_sf_in_bits { 10672 u8 opcode[0x10]; 10673 u8 reserved_at_10[0x10]; 10674 10675 u8 reserved_at_20[0x10]; 10676 u8 op_mod[0x10]; 10677 10678 u8 reserved_at_40[0x10]; 10679 u8 function_id[0x10]; 10680 10681 u8 reserved_at_60[0x20]; 10682 }; 10683 10684 struct mlx5_ifc_alloc_sf_out_bits { 10685 u8 status[0x8]; 10686 u8 reserved_at_8[0x18]; 10687 10688 u8 syndrome[0x20]; 10689 10690 u8 reserved_at_40[0x40]; 10691 }; 10692 10693 struct mlx5_ifc_alloc_sf_in_bits { 10694 u8 opcode[0x10]; 10695 u8 reserved_at_10[0x10]; 10696 10697 u8 reserved_at_20[0x10]; 10698 u8 op_mod[0x10]; 10699 10700 u8 reserved_at_40[0x10]; 10701 u8 function_id[0x10]; 10702 10703 u8 reserved_at_60[0x20]; 10704 }; 10705 10706 struct mlx5_ifc_affiliated_event_header_bits { 10707 u8 reserved_at_0[0x10]; 10708 u8 obj_type[0x10]; 10709 10710 u8 obj_id[0x20]; 10711 }; 10712 10713 enum { 10714 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = BIT_ULL(0xc), 10715 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_IPSEC = BIT_ULL(0x13), 10716 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_SAMPLER = BIT_ULL(0x20), 10717 }; 10718 10719 enum { 10720 MLX5_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = 0xc, 10721 MLX5_GENERAL_OBJECT_TYPES_IPSEC = 0x13, 10722 MLX5_GENERAL_OBJECT_TYPES_SAMPLER = 0x20, 10723 }; 10724 10725 enum { 10726 MLX5_IPSEC_OBJECT_ICV_LEN_16B, 10727 MLX5_IPSEC_OBJECT_ICV_LEN_12B, 10728 MLX5_IPSEC_OBJECT_ICV_LEN_8B, 10729 }; 10730 10731 struct mlx5_ifc_ipsec_obj_bits { 10732 u8 modify_field_select[0x40]; 10733 u8 full_offload[0x1]; 10734 u8 reserved_at_41[0x1]; 10735 u8 esn_en[0x1]; 10736 u8 esn_overlap[0x1]; 10737 u8 reserved_at_44[0x2]; 10738 u8 icv_length[0x2]; 10739 u8 reserved_at_48[0x4]; 10740 u8 aso_return_reg[0x4]; 10741 u8 reserved_at_50[0x10]; 10742 10743 u8 esn_msb[0x20]; 10744 10745 u8 reserved_at_80[0x8]; 10746 u8 dekn[0x18]; 10747 10748 u8 salt[0x20]; 10749 10750 u8 implicit_iv[0x40]; 10751 10752 u8 reserved_at_100[0x700]; 10753 }; 10754 10755 struct mlx5_ifc_create_ipsec_obj_in_bits { 10756 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 10757 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 10758 }; 10759 10760 enum { 10761 MLX5_MODIFY_IPSEC_BITMASK_ESN_OVERLAP = BIT(0), 10762 MLX5_MODIFY_IPSEC_BITMASK_ESN_MSB = BIT(1), 10763 }; 10764 10765 struct mlx5_ifc_query_ipsec_obj_out_bits { 10766 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 10767 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 10768 }; 10769 10770 struct mlx5_ifc_modify_ipsec_obj_in_bits { 10771 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 10772 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 10773 }; 10774 10775 struct mlx5_ifc_encryption_key_obj_bits { 10776 u8 modify_field_select[0x40]; 10777 10778 u8 reserved_at_40[0x14]; 10779 u8 key_size[0x4]; 10780 u8 reserved_at_58[0x4]; 10781 u8 key_type[0x4]; 10782 10783 u8 reserved_at_60[0x8]; 10784 u8 pd[0x18]; 10785 10786 u8 reserved_at_80[0x180]; 10787 u8 key[8][0x20]; 10788 10789 u8 reserved_at_300[0x500]; 10790 }; 10791 10792 struct mlx5_ifc_create_encryption_key_in_bits { 10793 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 10794 struct mlx5_ifc_encryption_key_obj_bits encryption_key_object; 10795 }; 10796 10797 struct mlx5_ifc_sampler_obj_bits { 10798 u8 modify_field_select[0x40]; 10799 10800 u8 table_type[0x8]; 10801 u8 level[0x8]; 10802 u8 reserved_at_50[0xf]; 10803 u8 ignore_flow_level[0x1]; 10804 10805 u8 sample_ratio[0x20]; 10806 10807 u8 reserved_at_80[0x8]; 10808 u8 sample_table_id[0x18]; 10809 10810 u8 reserved_at_a0[0x8]; 10811 u8 default_table_id[0x18]; 10812 10813 u8 sw_steering_icm_address_rx[0x40]; 10814 u8 sw_steering_icm_address_tx[0x40]; 10815 10816 u8 reserved_at_140[0xa0]; 10817 }; 10818 10819 struct mlx5_ifc_create_sampler_obj_in_bits { 10820 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 10821 struct mlx5_ifc_sampler_obj_bits sampler_object; 10822 }; 10823 10824 enum { 10825 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_128 = 0x0, 10826 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_256 = 0x1, 10827 }; 10828 10829 enum { 10830 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_TYPE_TLS = 0x1, 10831 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_TYPE_IPSEC = 0x2, 10832 }; 10833 10834 struct mlx5_ifc_tls_static_params_bits { 10835 u8 const_2[0x2]; 10836 u8 tls_version[0x4]; 10837 u8 const_1[0x2]; 10838 u8 reserved_at_8[0x14]; 10839 u8 encryption_standard[0x4]; 10840 10841 u8 reserved_at_20[0x20]; 10842 10843 u8 initial_record_number[0x40]; 10844 10845 u8 resync_tcp_sn[0x20]; 10846 10847 u8 gcm_iv[0x20]; 10848 10849 u8 implicit_iv[0x40]; 10850 10851 u8 reserved_at_100[0x8]; 10852 u8 dek_index[0x18]; 10853 10854 u8 reserved_at_120[0xe0]; 10855 }; 10856 10857 struct mlx5_ifc_tls_progress_params_bits { 10858 u8 next_record_tcp_sn[0x20]; 10859 10860 u8 hw_resync_tcp_sn[0x20]; 10861 10862 u8 record_tracker_state[0x2]; 10863 u8 auth_state[0x2]; 10864 u8 reserved_at_44[0x4]; 10865 u8 hw_offset_record_number[0x18]; 10866 }; 10867 10868 enum { 10869 MLX5_MTT_PERM_READ = 1 << 0, 10870 MLX5_MTT_PERM_WRITE = 1 << 1, 10871 MLX5_MTT_PERM_RW = MLX5_MTT_PERM_READ | MLX5_MTT_PERM_WRITE, 10872 }; 10873 10874 #endif /* MLX5_IFC_H */ 10875