1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 #ifndef MLX5_IFC_H 33 #define MLX5_IFC_H 34 35 #include "mlx5_ifc_fpga.h" 36 37 enum { 38 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0, 39 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1, 40 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2, 41 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3, 42 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13, 43 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14, 44 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c, 45 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d, 46 MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4, 47 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5, 48 MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED = 0x7, 49 MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT = 0xc, 50 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10, 51 MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR = 0x11, 52 MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR = 0x12, 53 MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR = 0x8, 54 MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE = 0x9, 55 MLX5_EVENT_TYPE_CODING_GPIO_EVENT = 0x15, 56 MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19, 57 MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a, 58 MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT = 0x1b, 59 MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT = 0x1f, 60 MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa, 61 MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb, 62 MLX5_EVENT_TYPE_CODING_FPGA_ERROR = 0x20, 63 MLX5_EVENT_TYPE_CODING_FPGA_QP_ERROR = 0x21 64 }; 65 66 enum { 67 MLX5_MODIFY_TIR_BITMASK_LRO = 0x0, 68 MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE = 0x1, 69 MLX5_MODIFY_TIR_BITMASK_HASH = 0x2, 70 MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN = 0x3 71 }; 72 73 enum { 74 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0, 75 MLX5_SET_HCA_CAP_OP_MOD_ODP = 0x2, 76 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3, 77 }; 78 79 enum { 80 MLX5_SHARED_RESOURCE_UID = 0xffff, 81 }; 82 83 enum { 84 MLX5_OBJ_TYPE_SW_ICM = 0x0008, 85 }; 86 87 enum { 88 MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM = (1ULL << MLX5_OBJ_TYPE_SW_ICM), 89 MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT = (1ULL << 11), 90 }; 91 92 enum { 93 MLX5_OBJ_TYPE_GENEVE_TLV_OPT = 0x000b, 94 }; 95 96 enum { 97 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100, 98 MLX5_CMD_OP_QUERY_ADAPTER = 0x101, 99 MLX5_CMD_OP_INIT_HCA = 0x102, 100 MLX5_CMD_OP_TEARDOWN_HCA = 0x103, 101 MLX5_CMD_OP_ENABLE_HCA = 0x104, 102 MLX5_CMD_OP_DISABLE_HCA = 0x105, 103 MLX5_CMD_OP_QUERY_PAGES = 0x107, 104 MLX5_CMD_OP_MANAGE_PAGES = 0x108, 105 MLX5_CMD_OP_SET_HCA_CAP = 0x109, 106 MLX5_CMD_OP_QUERY_ISSI = 0x10a, 107 MLX5_CMD_OP_SET_ISSI = 0x10b, 108 MLX5_CMD_OP_SET_DRIVER_VERSION = 0x10d, 109 MLX5_CMD_OP_CREATE_MKEY = 0x200, 110 MLX5_CMD_OP_QUERY_MKEY = 0x201, 111 MLX5_CMD_OP_DESTROY_MKEY = 0x202, 112 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203, 113 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204, 114 MLX5_CMD_OP_ALLOC_MEMIC = 0x205, 115 MLX5_CMD_OP_DEALLOC_MEMIC = 0x206, 116 MLX5_CMD_OP_CREATE_EQ = 0x301, 117 MLX5_CMD_OP_DESTROY_EQ = 0x302, 118 MLX5_CMD_OP_QUERY_EQ = 0x303, 119 MLX5_CMD_OP_GEN_EQE = 0x304, 120 MLX5_CMD_OP_CREATE_CQ = 0x400, 121 MLX5_CMD_OP_DESTROY_CQ = 0x401, 122 MLX5_CMD_OP_QUERY_CQ = 0x402, 123 MLX5_CMD_OP_MODIFY_CQ = 0x403, 124 MLX5_CMD_OP_CREATE_QP = 0x500, 125 MLX5_CMD_OP_DESTROY_QP = 0x501, 126 MLX5_CMD_OP_RST2INIT_QP = 0x502, 127 MLX5_CMD_OP_INIT2RTR_QP = 0x503, 128 MLX5_CMD_OP_RTR2RTS_QP = 0x504, 129 MLX5_CMD_OP_RTS2RTS_QP = 0x505, 130 MLX5_CMD_OP_SQERR2RTS_QP = 0x506, 131 MLX5_CMD_OP_2ERR_QP = 0x507, 132 MLX5_CMD_OP_2RST_QP = 0x50a, 133 MLX5_CMD_OP_QUERY_QP = 0x50b, 134 MLX5_CMD_OP_SQD_RTS_QP = 0x50c, 135 MLX5_CMD_OP_INIT2INIT_QP = 0x50e, 136 MLX5_CMD_OP_CREATE_PSV = 0x600, 137 MLX5_CMD_OP_DESTROY_PSV = 0x601, 138 MLX5_CMD_OP_CREATE_SRQ = 0x700, 139 MLX5_CMD_OP_DESTROY_SRQ = 0x701, 140 MLX5_CMD_OP_QUERY_SRQ = 0x702, 141 MLX5_CMD_OP_ARM_RQ = 0x703, 142 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705, 143 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706, 144 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707, 145 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708, 146 MLX5_CMD_OP_CREATE_DCT = 0x710, 147 MLX5_CMD_OP_DESTROY_DCT = 0x711, 148 MLX5_CMD_OP_DRAIN_DCT = 0x712, 149 MLX5_CMD_OP_QUERY_DCT = 0x713, 150 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714, 151 MLX5_CMD_OP_CREATE_XRQ = 0x717, 152 MLX5_CMD_OP_DESTROY_XRQ = 0x718, 153 MLX5_CMD_OP_QUERY_XRQ = 0x719, 154 MLX5_CMD_OP_ARM_XRQ = 0x71a, 155 MLX5_CMD_OP_QUERY_XRQ_DC_PARAMS_ENTRY = 0x725, 156 MLX5_CMD_OP_SET_XRQ_DC_PARAMS_ENTRY = 0x726, 157 MLX5_CMD_OP_QUERY_XRQ_ERROR_PARAMS = 0x727, 158 MLX5_CMD_OP_QUERY_ESW_FUNCTIONS = 0x740, 159 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750, 160 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751, 161 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752, 162 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753, 163 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754, 164 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755, 165 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760, 166 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761, 167 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762, 168 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763, 169 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764, 170 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765, 171 MLX5_CMD_OP_QUERY_VNIC_ENV = 0x76f, 172 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770, 173 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771, 174 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772, 175 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773, 176 MLX5_CMD_OP_SET_MONITOR_COUNTER = 0x774, 177 MLX5_CMD_OP_ARM_MONITOR_COUNTER = 0x775, 178 MLX5_CMD_OP_SET_PP_RATE_LIMIT = 0x780, 179 MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781, 180 MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT = 0x782, 181 MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT = 0x783, 182 MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT = 0x784, 183 MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT = 0x785, 184 MLX5_CMD_OP_CREATE_QOS_PARA_VPORT = 0x786, 185 MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT = 0x787, 186 MLX5_CMD_OP_ALLOC_PD = 0x800, 187 MLX5_CMD_OP_DEALLOC_PD = 0x801, 188 MLX5_CMD_OP_ALLOC_UAR = 0x802, 189 MLX5_CMD_OP_DEALLOC_UAR = 0x803, 190 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804, 191 MLX5_CMD_OP_ACCESS_REG = 0x805, 192 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806, 193 MLX5_CMD_OP_DETACH_FROM_MCG = 0x807, 194 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a, 195 MLX5_CMD_OP_MAD_IFC = 0x50d, 196 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b, 197 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c, 198 MLX5_CMD_OP_NOP = 0x80d, 199 MLX5_CMD_OP_ALLOC_XRCD = 0x80e, 200 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f, 201 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816, 202 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817, 203 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822, 204 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823, 205 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824, 206 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825, 207 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826, 208 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827, 209 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828, 210 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829, 211 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a, 212 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b, 213 MLX5_CMD_OP_SET_WOL_ROL = 0x830, 214 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831, 215 MLX5_CMD_OP_CREATE_LAG = 0x840, 216 MLX5_CMD_OP_MODIFY_LAG = 0x841, 217 MLX5_CMD_OP_QUERY_LAG = 0x842, 218 MLX5_CMD_OP_DESTROY_LAG = 0x843, 219 MLX5_CMD_OP_CREATE_VPORT_LAG = 0x844, 220 MLX5_CMD_OP_DESTROY_VPORT_LAG = 0x845, 221 MLX5_CMD_OP_CREATE_TIR = 0x900, 222 MLX5_CMD_OP_MODIFY_TIR = 0x901, 223 MLX5_CMD_OP_DESTROY_TIR = 0x902, 224 MLX5_CMD_OP_QUERY_TIR = 0x903, 225 MLX5_CMD_OP_CREATE_SQ = 0x904, 226 MLX5_CMD_OP_MODIFY_SQ = 0x905, 227 MLX5_CMD_OP_DESTROY_SQ = 0x906, 228 MLX5_CMD_OP_QUERY_SQ = 0x907, 229 MLX5_CMD_OP_CREATE_RQ = 0x908, 230 MLX5_CMD_OP_MODIFY_RQ = 0x909, 231 MLX5_CMD_OP_SET_DELAY_DROP_PARAMS = 0x910, 232 MLX5_CMD_OP_DESTROY_RQ = 0x90a, 233 MLX5_CMD_OP_QUERY_RQ = 0x90b, 234 MLX5_CMD_OP_CREATE_RMP = 0x90c, 235 MLX5_CMD_OP_MODIFY_RMP = 0x90d, 236 MLX5_CMD_OP_DESTROY_RMP = 0x90e, 237 MLX5_CMD_OP_QUERY_RMP = 0x90f, 238 MLX5_CMD_OP_CREATE_TIS = 0x912, 239 MLX5_CMD_OP_MODIFY_TIS = 0x913, 240 MLX5_CMD_OP_DESTROY_TIS = 0x914, 241 MLX5_CMD_OP_QUERY_TIS = 0x915, 242 MLX5_CMD_OP_CREATE_RQT = 0x916, 243 MLX5_CMD_OP_MODIFY_RQT = 0x917, 244 MLX5_CMD_OP_DESTROY_RQT = 0x918, 245 MLX5_CMD_OP_QUERY_RQT = 0x919, 246 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f, 247 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930, 248 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931, 249 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932, 250 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933, 251 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934, 252 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935, 253 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936, 254 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937, 255 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938, 256 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939, 257 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a, 258 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b, 259 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c, 260 MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT = 0x93d, 261 MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT = 0x93e, 262 MLX5_CMD_OP_QUERY_PACKET_REFORMAT_CONTEXT = 0x93f, 263 MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT = 0x940, 264 MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941, 265 MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT = 0x942, 266 MLX5_CMD_OP_FPGA_CREATE_QP = 0x960, 267 MLX5_CMD_OP_FPGA_MODIFY_QP = 0x961, 268 MLX5_CMD_OP_FPGA_QUERY_QP = 0x962, 269 MLX5_CMD_OP_FPGA_DESTROY_QP = 0x963, 270 MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS = 0x964, 271 MLX5_CMD_OP_CREATE_GENERAL_OBJECT = 0xa00, 272 MLX5_CMD_OP_MODIFY_GENERAL_OBJECT = 0xa01, 273 MLX5_CMD_OP_QUERY_GENERAL_OBJECT = 0xa02, 274 MLX5_CMD_OP_DESTROY_GENERAL_OBJECT = 0xa03, 275 MLX5_CMD_OP_CREATE_UCTX = 0xa04, 276 MLX5_CMD_OP_DESTROY_UCTX = 0xa06, 277 MLX5_CMD_OP_CREATE_UMEM = 0xa08, 278 MLX5_CMD_OP_DESTROY_UMEM = 0xa0a, 279 MLX5_CMD_OP_MAX 280 }; 281 282 /* Valid range for general commands that don't work over an object */ 283 enum { 284 MLX5_CMD_OP_GENERAL_START = 0xb00, 285 MLX5_CMD_OP_GENERAL_END = 0xd00, 286 }; 287 288 struct mlx5_ifc_flow_table_fields_supported_bits { 289 u8 outer_dmac[0x1]; 290 u8 outer_smac[0x1]; 291 u8 outer_ether_type[0x1]; 292 u8 outer_ip_version[0x1]; 293 u8 outer_first_prio[0x1]; 294 u8 outer_first_cfi[0x1]; 295 u8 outer_first_vid[0x1]; 296 u8 outer_ipv4_ttl[0x1]; 297 u8 outer_second_prio[0x1]; 298 u8 outer_second_cfi[0x1]; 299 u8 outer_second_vid[0x1]; 300 u8 reserved_at_b[0x1]; 301 u8 outer_sip[0x1]; 302 u8 outer_dip[0x1]; 303 u8 outer_frag[0x1]; 304 u8 outer_ip_protocol[0x1]; 305 u8 outer_ip_ecn[0x1]; 306 u8 outer_ip_dscp[0x1]; 307 u8 outer_udp_sport[0x1]; 308 u8 outer_udp_dport[0x1]; 309 u8 outer_tcp_sport[0x1]; 310 u8 outer_tcp_dport[0x1]; 311 u8 outer_tcp_flags[0x1]; 312 u8 outer_gre_protocol[0x1]; 313 u8 outer_gre_key[0x1]; 314 u8 outer_vxlan_vni[0x1]; 315 u8 outer_geneve_vni[0x1]; 316 u8 outer_geneve_oam[0x1]; 317 u8 outer_geneve_protocol_type[0x1]; 318 u8 outer_geneve_opt_len[0x1]; 319 u8 reserved_at_1e[0x1]; 320 u8 source_eswitch_port[0x1]; 321 322 u8 inner_dmac[0x1]; 323 u8 inner_smac[0x1]; 324 u8 inner_ether_type[0x1]; 325 u8 inner_ip_version[0x1]; 326 u8 inner_first_prio[0x1]; 327 u8 inner_first_cfi[0x1]; 328 u8 inner_first_vid[0x1]; 329 u8 reserved_at_27[0x1]; 330 u8 inner_second_prio[0x1]; 331 u8 inner_second_cfi[0x1]; 332 u8 inner_second_vid[0x1]; 333 u8 reserved_at_2b[0x1]; 334 u8 inner_sip[0x1]; 335 u8 inner_dip[0x1]; 336 u8 inner_frag[0x1]; 337 u8 inner_ip_protocol[0x1]; 338 u8 inner_ip_ecn[0x1]; 339 u8 inner_ip_dscp[0x1]; 340 u8 inner_udp_sport[0x1]; 341 u8 inner_udp_dport[0x1]; 342 u8 inner_tcp_sport[0x1]; 343 u8 inner_tcp_dport[0x1]; 344 u8 inner_tcp_flags[0x1]; 345 u8 reserved_at_37[0x9]; 346 347 u8 geneve_tlv_option_0_data[0x1]; 348 u8 reserved_at_41[0x4]; 349 u8 outer_first_mpls_over_udp[0x4]; 350 u8 outer_first_mpls_over_gre[0x4]; 351 u8 inner_first_mpls[0x4]; 352 u8 outer_first_mpls[0x4]; 353 u8 reserved_at_55[0x2]; 354 u8 outer_esp_spi[0x1]; 355 u8 reserved_at_58[0x2]; 356 u8 bth_dst_qp[0x1]; 357 358 u8 reserved_at_5b[0x25]; 359 }; 360 361 struct mlx5_ifc_flow_table_prop_layout_bits { 362 u8 ft_support[0x1]; 363 u8 reserved_at_1[0x1]; 364 u8 flow_counter[0x1]; 365 u8 flow_modify_en[0x1]; 366 u8 modify_root[0x1]; 367 u8 identified_miss_table_mode[0x1]; 368 u8 flow_table_modify[0x1]; 369 u8 reformat[0x1]; 370 u8 decap[0x1]; 371 u8 reserved_at_9[0x1]; 372 u8 pop_vlan[0x1]; 373 u8 push_vlan[0x1]; 374 u8 reserved_at_c[0x1]; 375 u8 pop_vlan_2[0x1]; 376 u8 push_vlan_2[0x1]; 377 u8 reformat_and_vlan_action[0x1]; 378 u8 reserved_at_10[0x1]; 379 u8 sw_owner[0x1]; 380 u8 reformat_l3_tunnel_to_l2[0x1]; 381 u8 reformat_l2_to_l3_tunnel[0x1]; 382 u8 reformat_and_modify_action[0x1]; 383 u8 reserved_at_15[0x2]; 384 u8 table_miss_action_domain[0x1]; 385 u8 termination_table[0x1]; 386 u8 reserved_at_19[0x7]; 387 u8 reserved_at_20[0x2]; 388 u8 log_max_ft_size[0x6]; 389 u8 log_max_modify_header_context[0x8]; 390 u8 max_modify_header_actions[0x8]; 391 u8 max_ft_level[0x8]; 392 393 u8 reserved_at_40[0x20]; 394 395 u8 reserved_at_60[0x18]; 396 u8 log_max_ft_num[0x8]; 397 398 u8 reserved_at_80[0x18]; 399 u8 log_max_destination[0x8]; 400 401 u8 log_max_flow_counter[0x8]; 402 u8 reserved_at_a8[0x10]; 403 u8 log_max_flow[0x8]; 404 405 u8 reserved_at_c0[0x40]; 406 407 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support; 408 409 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support; 410 }; 411 412 struct mlx5_ifc_odp_per_transport_service_cap_bits { 413 u8 send[0x1]; 414 u8 receive[0x1]; 415 u8 write[0x1]; 416 u8 read[0x1]; 417 u8 atomic[0x1]; 418 u8 srq_receive[0x1]; 419 u8 reserved_at_6[0x1a]; 420 }; 421 422 struct mlx5_ifc_fte_match_set_lyr_2_4_bits { 423 u8 smac_47_16[0x20]; 424 425 u8 smac_15_0[0x10]; 426 u8 ethertype[0x10]; 427 428 u8 dmac_47_16[0x20]; 429 430 u8 dmac_15_0[0x10]; 431 u8 first_prio[0x3]; 432 u8 first_cfi[0x1]; 433 u8 first_vid[0xc]; 434 435 u8 ip_protocol[0x8]; 436 u8 ip_dscp[0x6]; 437 u8 ip_ecn[0x2]; 438 u8 cvlan_tag[0x1]; 439 u8 svlan_tag[0x1]; 440 u8 frag[0x1]; 441 u8 ip_version[0x4]; 442 u8 tcp_flags[0x9]; 443 444 u8 tcp_sport[0x10]; 445 u8 tcp_dport[0x10]; 446 447 u8 reserved_at_c0[0x18]; 448 u8 ttl_hoplimit[0x8]; 449 450 u8 udp_sport[0x10]; 451 u8 udp_dport[0x10]; 452 453 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6; 454 455 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6; 456 }; 457 458 struct mlx5_ifc_nvgre_key_bits { 459 u8 hi[0x18]; 460 u8 lo[0x8]; 461 }; 462 463 union mlx5_ifc_gre_key_bits { 464 struct mlx5_ifc_nvgre_key_bits nvgre; 465 u8 key[0x20]; 466 }; 467 468 struct mlx5_ifc_fte_match_set_misc_bits { 469 u8 reserved_at_0[0x8]; 470 u8 source_sqn[0x18]; 471 472 u8 source_eswitch_owner_vhca_id[0x10]; 473 u8 source_port[0x10]; 474 475 u8 outer_second_prio[0x3]; 476 u8 outer_second_cfi[0x1]; 477 u8 outer_second_vid[0xc]; 478 u8 inner_second_prio[0x3]; 479 u8 inner_second_cfi[0x1]; 480 u8 inner_second_vid[0xc]; 481 482 u8 outer_second_cvlan_tag[0x1]; 483 u8 inner_second_cvlan_tag[0x1]; 484 u8 outer_second_svlan_tag[0x1]; 485 u8 inner_second_svlan_tag[0x1]; 486 u8 reserved_at_64[0xc]; 487 u8 gre_protocol[0x10]; 488 489 union mlx5_ifc_gre_key_bits gre_key; 490 491 u8 vxlan_vni[0x18]; 492 u8 reserved_at_b8[0x8]; 493 494 u8 geneve_vni[0x18]; 495 u8 reserved_at_d8[0x7]; 496 u8 geneve_oam[0x1]; 497 498 u8 reserved_at_e0[0xc]; 499 u8 outer_ipv6_flow_label[0x14]; 500 501 u8 reserved_at_100[0xc]; 502 u8 inner_ipv6_flow_label[0x14]; 503 504 u8 reserved_at_120[0xa]; 505 u8 geneve_opt_len[0x6]; 506 u8 geneve_protocol_type[0x10]; 507 508 u8 reserved_at_140[0x8]; 509 u8 bth_dst_qp[0x18]; 510 u8 reserved_at_160[0x20]; 511 u8 outer_esp_spi[0x20]; 512 u8 reserved_at_1a0[0x60]; 513 }; 514 515 struct mlx5_ifc_fte_match_mpls_bits { 516 u8 mpls_label[0x14]; 517 u8 mpls_exp[0x3]; 518 u8 mpls_s_bos[0x1]; 519 u8 mpls_ttl[0x8]; 520 }; 521 522 struct mlx5_ifc_fte_match_set_misc2_bits { 523 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls; 524 525 struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls; 526 527 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre; 528 529 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp; 530 531 u8 metadata_reg_c_7[0x20]; 532 533 u8 metadata_reg_c_6[0x20]; 534 535 u8 metadata_reg_c_5[0x20]; 536 537 u8 metadata_reg_c_4[0x20]; 538 539 u8 metadata_reg_c_3[0x20]; 540 541 u8 metadata_reg_c_2[0x20]; 542 543 u8 metadata_reg_c_1[0x20]; 544 545 u8 metadata_reg_c_0[0x20]; 546 547 u8 metadata_reg_a[0x20]; 548 549 u8 reserved_at_1a0[0x60]; 550 }; 551 552 struct mlx5_ifc_fte_match_set_misc3_bits { 553 u8 reserved_at_0[0x120]; 554 u8 geneve_tlv_option_0_data[0x20]; 555 u8 reserved_at_140[0xc0]; 556 }; 557 558 struct mlx5_ifc_cmd_pas_bits { 559 u8 pa_h[0x20]; 560 561 u8 pa_l[0x14]; 562 u8 reserved_at_34[0xc]; 563 }; 564 565 struct mlx5_ifc_uint64_bits { 566 u8 hi[0x20]; 567 568 u8 lo[0x20]; 569 }; 570 571 enum { 572 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0, 573 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7, 574 MLX5_ADS_STAT_RATE_10GBPS = 0x8, 575 MLX5_ADS_STAT_RATE_30GBPS = 0x9, 576 MLX5_ADS_STAT_RATE_5GBPS = 0xa, 577 MLX5_ADS_STAT_RATE_20GBPS = 0xb, 578 MLX5_ADS_STAT_RATE_40GBPS = 0xc, 579 MLX5_ADS_STAT_RATE_60GBPS = 0xd, 580 MLX5_ADS_STAT_RATE_80GBPS = 0xe, 581 MLX5_ADS_STAT_RATE_120GBPS = 0xf, 582 }; 583 584 struct mlx5_ifc_ads_bits { 585 u8 fl[0x1]; 586 u8 free_ar[0x1]; 587 u8 reserved_at_2[0xe]; 588 u8 pkey_index[0x10]; 589 590 u8 reserved_at_20[0x8]; 591 u8 grh[0x1]; 592 u8 mlid[0x7]; 593 u8 rlid[0x10]; 594 595 u8 ack_timeout[0x5]; 596 u8 reserved_at_45[0x3]; 597 u8 src_addr_index[0x8]; 598 u8 reserved_at_50[0x4]; 599 u8 stat_rate[0x4]; 600 u8 hop_limit[0x8]; 601 602 u8 reserved_at_60[0x4]; 603 u8 tclass[0x8]; 604 u8 flow_label[0x14]; 605 606 u8 rgid_rip[16][0x8]; 607 608 u8 reserved_at_100[0x4]; 609 u8 f_dscp[0x1]; 610 u8 f_ecn[0x1]; 611 u8 reserved_at_106[0x1]; 612 u8 f_eth_prio[0x1]; 613 u8 ecn[0x2]; 614 u8 dscp[0x6]; 615 u8 udp_sport[0x10]; 616 617 u8 dei_cfi[0x1]; 618 u8 eth_prio[0x3]; 619 u8 sl[0x4]; 620 u8 vhca_port_num[0x8]; 621 u8 rmac_47_32[0x10]; 622 623 u8 rmac_31_0[0x20]; 624 }; 625 626 struct mlx5_ifc_flow_table_nic_cap_bits { 627 u8 nic_rx_multi_path_tirs[0x1]; 628 u8 nic_rx_multi_path_tirs_fts[0x1]; 629 u8 allow_sniffer_and_nic_rx_shared_tir[0x1]; 630 u8 reserved_at_3[0x1d]; 631 u8 encap_general_header[0x1]; 632 u8 reserved_at_21[0xa]; 633 u8 log_max_packet_reformat_context[0x5]; 634 u8 reserved_at_30[0x6]; 635 u8 max_encap_header_size[0xa]; 636 u8 reserved_at_40[0x1c0]; 637 638 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive; 639 640 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_rdma; 641 642 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer; 643 644 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit; 645 646 u8 reserved_at_a00[0x200]; 647 648 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer; 649 650 u8 reserved_at_e00[0x7200]; 651 }; 652 653 enum { 654 MLX5_FDB_TO_VPORT_REG_C_0 = 0x01, 655 MLX5_FDB_TO_VPORT_REG_C_1 = 0x02, 656 MLX5_FDB_TO_VPORT_REG_C_2 = 0x04, 657 MLX5_FDB_TO_VPORT_REG_C_3 = 0x08, 658 MLX5_FDB_TO_VPORT_REG_C_4 = 0x10, 659 MLX5_FDB_TO_VPORT_REG_C_5 = 0x20, 660 MLX5_FDB_TO_VPORT_REG_C_6 = 0x40, 661 MLX5_FDB_TO_VPORT_REG_C_7 = 0x80, 662 }; 663 664 struct mlx5_ifc_flow_table_eswitch_cap_bits { 665 u8 fdb_to_vport_reg_c_id[0x8]; 666 u8 reserved_at_8[0xf]; 667 u8 flow_source[0x1]; 668 u8 reserved_at_18[0x2]; 669 u8 multi_fdb_encap[0x1]; 670 u8 reserved_at_1b[0x1]; 671 u8 fdb_multi_path_to_table[0x1]; 672 u8 reserved_at_1d[0x3]; 673 674 u8 reserved_at_20[0x1e0]; 675 676 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb; 677 678 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress; 679 680 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress; 681 682 u8 reserved_at_800[0x7800]; 683 }; 684 685 enum { 686 MLX5_COUNTER_SOURCE_ESWITCH = 0x0, 687 MLX5_COUNTER_FLOW_ESWITCH = 0x1, 688 }; 689 690 struct mlx5_ifc_e_switch_cap_bits { 691 u8 vport_svlan_strip[0x1]; 692 u8 vport_cvlan_strip[0x1]; 693 u8 vport_svlan_insert[0x1]; 694 u8 vport_cvlan_insert_if_not_exist[0x1]; 695 u8 vport_cvlan_insert_overwrite[0x1]; 696 u8 reserved_at_5[0x3]; 697 u8 esw_uplink_ingress_acl[0x1]; 698 u8 reserved_at_9[0x10]; 699 u8 esw_functions_changed[0x1]; 700 u8 reserved_at_1a[0x1]; 701 u8 ecpf_vport_exists[0x1]; 702 u8 counter_eswitch_affinity[0x1]; 703 u8 merged_eswitch[0x1]; 704 u8 nic_vport_node_guid_modify[0x1]; 705 u8 nic_vport_port_guid_modify[0x1]; 706 707 u8 vxlan_encap_decap[0x1]; 708 u8 nvgre_encap_decap[0x1]; 709 u8 reserved_at_22[0x1]; 710 u8 log_max_fdb_encap_uplink[0x5]; 711 u8 reserved_at_21[0x3]; 712 u8 log_max_packet_reformat_context[0x5]; 713 u8 reserved_2b[0x6]; 714 u8 max_encap_header_size[0xa]; 715 716 u8 reserved_40[0x7c0]; 717 718 }; 719 720 struct mlx5_ifc_qos_cap_bits { 721 u8 packet_pacing[0x1]; 722 u8 esw_scheduling[0x1]; 723 u8 esw_bw_share[0x1]; 724 u8 esw_rate_limit[0x1]; 725 u8 reserved_at_4[0x1]; 726 u8 packet_pacing_burst_bound[0x1]; 727 u8 packet_pacing_typical_size[0x1]; 728 u8 reserved_at_7[0x19]; 729 730 u8 reserved_at_20[0x20]; 731 732 u8 packet_pacing_max_rate[0x20]; 733 734 u8 packet_pacing_min_rate[0x20]; 735 736 u8 reserved_at_80[0x10]; 737 u8 packet_pacing_rate_table_size[0x10]; 738 739 u8 esw_element_type[0x10]; 740 u8 esw_tsar_type[0x10]; 741 742 u8 reserved_at_c0[0x10]; 743 u8 max_qos_para_vport[0x10]; 744 745 u8 max_tsar_bw_share[0x20]; 746 747 u8 reserved_at_100[0x700]; 748 }; 749 750 struct mlx5_ifc_debug_cap_bits { 751 u8 core_dump_general[0x1]; 752 u8 core_dump_qp[0x1]; 753 u8 reserved_at_2[0x1e]; 754 755 u8 reserved_at_20[0x2]; 756 u8 stall_detect[0x1]; 757 u8 reserved_at_23[0x1d]; 758 759 u8 reserved_at_40[0x7c0]; 760 }; 761 762 struct mlx5_ifc_per_protocol_networking_offload_caps_bits { 763 u8 csum_cap[0x1]; 764 u8 vlan_cap[0x1]; 765 u8 lro_cap[0x1]; 766 u8 lro_psh_flag[0x1]; 767 u8 lro_time_stamp[0x1]; 768 u8 reserved_at_5[0x2]; 769 u8 wqe_vlan_insert[0x1]; 770 u8 self_lb_en_modifiable[0x1]; 771 u8 reserved_at_9[0x2]; 772 u8 max_lso_cap[0x5]; 773 u8 multi_pkt_send_wqe[0x2]; 774 u8 wqe_inline_mode[0x2]; 775 u8 rss_ind_tbl_cap[0x4]; 776 u8 reg_umr_sq[0x1]; 777 u8 scatter_fcs[0x1]; 778 u8 enhanced_multi_pkt_send_wqe[0x1]; 779 u8 tunnel_lso_const_out_ip_id[0x1]; 780 u8 reserved_at_1c[0x2]; 781 u8 tunnel_stateless_gre[0x1]; 782 u8 tunnel_stateless_vxlan[0x1]; 783 784 u8 swp[0x1]; 785 u8 swp_csum[0x1]; 786 u8 swp_lso[0x1]; 787 u8 reserved_at_23[0xd]; 788 u8 max_vxlan_udp_ports[0x8]; 789 u8 reserved_at_38[0x6]; 790 u8 max_geneve_opt_len[0x1]; 791 u8 tunnel_stateless_geneve_rx[0x1]; 792 793 u8 reserved_at_40[0x10]; 794 u8 lro_min_mss_size[0x10]; 795 796 u8 reserved_at_60[0x120]; 797 798 u8 lro_timer_supported_periods[4][0x20]; 799 800 u8 reserved_at_200[0x600]; 801 }; 802 803 struct mlx5_ifc_roce_cap_bits { 804 u8 roce_apm[0x1]; 805 u8 reserved_at_1[0x1f]; 806 807 u8 reserved_at_20[0x60]; 808 809 u8 reserved_at_80[0xc]; 810 u8 l3_type[0x4]; 811 u8 reserved_at_90[0x8]; 812 u8 roce_version[0x8]; 813 814 u8 reserved_at_a0[0x10]; 815 u8 r_roce_dest_udp_port[0x10]; 816 817 u8 r_roce_max_src_udp_port[0x10]; 818 u8 r_roce_min_src_udp_port[0x10]; 819 820 u8 reserved_at_e0[0x10]; 821 u8 roce_address_table_size[0x10]; 822 823 u8 reserved_at_100[0x700]; 824 }; 825 826 struct mlx5_ifc_device_mem_cap_bits { 827 u8 memic[0x1]; 828 u8 reserved_at_1[0x1f]; 829 830 u8 reserved_at_20[0xb]; 831 u8 log_min_memic_alloc_size[0x5]; 832 u8 reserved_at_30[0x8]; 833 u8 log_max_memic_addr_alignment[0x8]; 834 835 u8 memic_bar_start_addr[0x40]; 836 837 u8 memic_bar_size[0x20]; 838 839 u8 max_memic_size[0x20]; 840 841 u8 steering_sw_icm_start_address[0x40]; 842 843 u8 reserved_at_100[0x8]; 844 u8 log_header_modify_sw_icm_size[0x8]; 845 u8 reserved_at_110[0x2]; 846 u8 log_sw_icm_alloc_granularity[0x6]; 847 u8 log_steering_sw_icm_size[0x8]; 848 849 u8 reserved_at_120[0x20]; 850 851 u8 header_modify_sw_icm_start_address[0x40]; 852 853 u8 reserved_at_180[0x680]; 854 }; 855 856 enum { 857 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0, 858 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2, 859 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4, 860 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8, 861 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10, 862 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20, 863 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40, 864 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80, 865 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100, 866 }; 867 868 enum { 869 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1, 870 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2, 871 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4, 872 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8, 873 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10, 874 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20, 875 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40, 876 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80, 877 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100, 878 }; 879 880 struct mlx5_ifc_atomic_caps_bits { 881 u8 reserved_at_0[0x40]; 882 883 u8 atomic_req_8B_endianness_mode[0x2]; 884 u8 reserved_at_42[0x4]; 885 u8 supported_atomic_req_8B_endianness_mode_1[0x1]; 886 887 u8 reserved_at_47[0x19]; 888 889 u8 reserved_at_60[0x20]; 890 891 u8 reserved_at_80[0x10]; 892 u8 atomic_operations[0x10]; 893 894 u8 reserved_at_a0[0x10]; 895 u8 atomic_size_qp[0x10]; 896 897 u8 reserved_at_c0[0x10]; 898 u8 atomic_size_dc[0x10]; 899 900 u8 reserved_at_e0[0x720]; 901 }; 902 903 struct mlx5_ifc_odp_cap_bits { 904 u8 reserved_at_0[0x40]; 905 906 u8 sig[0x1]; 907 u8 reserved_at_41[0x1f]; 908 909 u8 reserved_at_60[0x20]; 910 911 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps; 912 913 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps; 914 915 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps; 916 917 struct mlx5_ifc_odp_per_transport_service_cap_bits xrc_odp_caps; 918 919 u8 reserved_at_100[0x700]; 920 }; 921 922 struct mlx5_ifc_calc_op { 923 u8 reserved_at_0[0x10]; 924 u8 reserved_at_10[0x9]; 925 u8 op_swap_endianness[0x1]; 926 u8 op_min[0x1]; 927 u8 op_xor[0x1]; 928 u8 op_or[0x1]; 929 u8 op_and[0x1]; 930 u8 op_max[0x1]; 931 u8 op_add[0x1]; 932 }; 933 934 struct mlx5_ifc_vector_calc_cap_bits { 935 u8 calc_matrix[0x1]; 936 u8 reserved_at_1[0x1f]; 937 u8 reserved_at_20[0x8]; 938 u8 max_vec_count[0x8]; 939 u8 reserved_at_30[0xd]; 940 u8 max_chunk_size[0x3]; 941 struct mlx5_ifc_calc_op calc0; 942 struct mlx5_ifc_calc_op calc1; 943 struct mlx5_ifc_calc_op calc2; 944 struct mlx5_ifc_calc_op calc3; 945 946 u8 reserved_at_c0[0x720]; 947 }; 948 949 enum { 950 MLX5_WQ_TYPE_LINKED_LIST = 0x0, 951 MLX5_WQ_TYPE_CYCLIC = 0x1, 952 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2, 953 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3, 954 }; 955 956 enum { 957 MLX5_WQ_END_PAD_MODE_NONE = 0x0, 958 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1, 959 }; 960 961 enum { 962 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0, 963 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1, 964 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2, 965 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3, 966 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4, 967 }; 968 969 enum { 970 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0, 971 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1, 972 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2, 973 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3, 974 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4, 975 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5, 976 }; 977 978 enum { 979 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0, 980 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1, 981 }; 982 983 enum { 984 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0, 985 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1, 986 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3, 987 }; 988 989 enum { 990 MLX5_CAP_PORT_TYPE_IB = 0x0, 991 MLX5_CAP_PORT_TYPE_ETH = 0x1, 992 }; 993 994 enum { 995 MLX5_CAP_UMR_FENCE_STRONG = 0x0, 996 MLX5_CAP_UMR_FENCE_SMALL = 0x1, 997 MLX5_CAP_UMR_FENCE_NONE = 0x2, 998 }; 999 1000 enum { 1001 MLX5_UCTX_CAP_RAW_TX = 1UL << 0, 1002 MLX5_UCTX_CAP_INTERNAL_DEV_RES = 1UL << 1, 1003 }; 1004 1005 struct mlx5_ifc_cmd_hca_cap_bits { 1006 u8 reserved_at_0[0x30]; 1007 u8 vhca_id[0x10]; 1008 1009 u8 reserved_at_40[0x40]; 1010 1011 u8 log_max_srq_sz[0x8]; 1012 u8 log_max_qp_sz[0x8]; 1013 u8 reserved_at_90[0x8]; 1014 u8 prio_tag_required[0x1]; 1015 u8 reserved_at_99[0x2]; 1016 u8 log_max_qp[0x5]; 1017 1018 u8 reserved_at_a0[0xb]; 1019 u8 log_max_srq[0x5]; 1020 u8 reserved_at_b0[0x10]; 1021 1022 u8 reserved_at_c0[0x8]; 1023 u8 log_max_cq_sz[0x8]; 1024 u8 reserved_at_d0[0xb]; 1025 u8 log_max_cq[0x5]; 1026 1027 u8 log_max_eq_sz[0x8]; 1028 u8 reserved_at_e8[0x2]; 1029 u8 log_max_mkey[0x6]; 1030 u8 reserved_at_f0[0x8]; 1031 u8 dump_fill_mkey[0x1]; 1032 u8 reserved_at_f9[0x2]; 1033 u8 fast_teardown[0x1]; 1034 u8 log_max_eq[0x4]; 1035 1036 u8 max_indirection[0x8]; 1037 u8 fixed_buffer_size[0x1]; 1038 u8 log_max_mrw_sz[0x7]; 1039 u8 force_teardown[0x1]; 1040 u8 reserved_at_111[0x1]; 1041 u8 log_max_bsf_list_size[0x6]; 1042 u8 umr_extended_translation_offset[0x1]; 1043 u8 null_mkey[0x1]; 1044 u8 log_max_klm_list_size[0x6]; 1045 1046 u8 reserved_at_120[0xa]; 1047 u8 log_max_ra_req_dc[0x6]; 1048 u8 reserved_at_130[0xa]; 1049 u8 log_max_ra_res_dc[0x6]; 1050 1051 u8 reserved_at_140[0xa]; 1052 u8 log_max_ra_req_qp[0x6]; 1053 u8 reserved_at_150[0xa]; 1054 u8 log_max_ra_res_qp[0x6]; 1055 1056 u8 end_pad[0x1]; 1057 u8 cc_query_allowed[0x1]; 1058 u8 cc_modify_allowed[0x1]; 1059 u8 start_pad[0x1]; 1060 u8 cache_line_128byte[0x1]; 1061 u8 reserved_at_165[0xa]; 1062 u8 qcam_reg[0x1]; 1063 u8 gid_table_size[0x10]; 1064 1065 u8 out_of_seq_cnt[0x1]; 1066 u8 vport_counters[0x1]; 1067 u8 retransmission_q_counters[0x1]; 1068 u8 debug[0x1]; 1069 u8 modify_rq_counter_set_id[0x1]; 1070 u8 rq_delay_drop[0x1]; 1071 u8 max_qp_cnt[0xa]; 1072 u8 pkey_table_size[0x10]; 1073 1074 u8 vport_group_manager[0x1]; 1075 u8 vhca_group_manager[0x1]; 1076 u8 ib_virt[0x1]; 1077 u8 eth_virt[0x1]; 1078 u8 vnic_env_queue_counters[0x1]; 1079 u8 ets[0x1]; 1080 u8 nic_flow_table[0x1]; 1081 u8 eswitch_manager[0x1]; 1082 u8 device_memory[0x1]; 1083 u8 mcam_reg[0x1]; 1084 u8 pcam_reg[0x1]; 1085 u8 local_ca_ack_delay[0x5]; 1086 u8 port_module_event[0x1]; 1087 u8 enhanced_error_q_counters[0x1]; 1088 u8 ports_check[0x1]; 1089 u8 reserved_at_1b3[0x1]; 1090 u8 disable_link_up[0x1]; 1091 u8 beacon_led[0x1]; 1092 u8 port_type[0x2]; 1093 u8 num_ports[0x8]; 1094 1095 u8 reserved_at_1c0[0x1]; 1096 u8 pps[0x1]; 1097 u8 pps_modify[0x1]; 1098 u8 log_max_msg[0x5]; 1099 u8 reserved_at_1c8[0x4]; 1100 u8 max_tc[0x4]; 1101 u8 temp_warn_event[0x1]; 1102 u8 dcbx[0x1]; 1103 u8 general_notification_event[0x1]; 1104 u8 reserved_at_1d3[0x2]; 1105 u8 fpga[0x1]; 1106 u8 rol_s[0x1]; 1107 u8 rol_g[0x1]; 1108 u8 reserved_at_1d8[0x1]; 1109 u8 wol_s[0x1]; 1110 u8 wol_g[0x1]; 1111 u8 wol_a[0x1]; 1112 u8 wol_b[0x1]; 1113 u8 wol_m[0x1]; 1114 u8 wol_u[0x1]; 1115 u8 wol_p[0x1]; 1116 1117 u8 stat_rate_support[0x10]; 1118 u8 reserved_at_1f0[0xc]; 1119 u8 cqe_version[0x4]; 1120 1121 u8 compact_address_vector[0x1]; 1122 u8 striding_rq[0x1]; 1123 u8 reserved_at_202[0x1]; 1124 u8 ipoib_enhanced_offloads[0x1]; 1125 u8 ipoib_basic_offloads[0x1]; 1126 u8 reserved_at_205[0x1]; 1127 u8 repeated_block_disabled[0x1]; 1128 u8 umr_modify_entity_size_disabled[0x1]; 1129 u8 umr_modify_atomic_disabled[0x1]; 1130 u8 umr_indirect_mkey_disabled[0x1]; 1131 u8 umr_fence[0x2]; 1132 u8 dc_req_scat_data_cqe[0x1]; 1133 u8 reserved_at_20d[0x2]; 1134 u8 drain_sigerr[0x1]; 1135 u8 cmdif_checksum[0x2]; 1136 u8 sigerr_cqe[0x1]; 1137 u8 reserved_at_213[0x1]; 1138 u8 wq_signature[0x1]; 1139 u8 sctr_data_cqe[0x1]; 1140 u8 reserved_at_216[0x1]; 1141 u8 sho[0x1]; 1142 u8 tph[0x1]; 1143 u8 rf[0x1]; 1144 u8 dct[0x1]; 1145 u8 qos[0x1]; 1146 u8 eth_net_offloads[0x1]; 1147 u8 roce[0x1]; 1148 u8 atomic[0x1]; 1149 u8 reserved_at_21f[0x1]; 1150 1151 u8 cq_oi[0x1]; 1152 u8 cq_resize[0x1]; 1153 u8 cq_moderation[0x1]; 1154 u8 reserved_at_223[0x3]; 1155 u8 cq_eq_remap[0x1]; 1156 u8 pg[0x1]; 1157 u8 block_lb_mc[0x1]; 1158 u8 reserved_at_229[0x1]; 1159 u8 scqe_break_moderation[0x1]; 1160 u8 cq_period_start_from_cqe[0x1]; 1161 u8 cd[0x1]; 1162 u8 reserved_at_22d[0x1]; 1163 u8 apm[0x1]; 1164 u8 vector_calc[0x1]; 1165 u8 umr_ptr_rlky[0x1]; 1166 u8 imaicl[0x1]; 1167 u8 qp_packet_based[0x1]; 1168 u8 reserved_at_233[0x3]; 1169 u8 qkv[0x1]; 1170 u8 pkv[0x1]; 1171 u8 set_deth_sqpn[0x1]; 1172 u8 reserved_at_239[0x3]; 1173 u8 xrc[0x1]; 1174 u8 ud[0x1]; 1175 u8 uc[0x1]; 1176 u8 rc[0x1]; 1177 1178 u8 uar_4k[0x1]; 1179 u8 reserved_at_241[0x9]; 1180 u8 uar_sz[0x6]; 1181 u8 reserved_at_250[0x8]; 1182 u8 log_pg_sz[0x8]; 1183 1184 u8 bf[0x1]; 1185 u8 driver_version[0x1]; 1186 u8 pad_tx_eth_packet[0x1]; 1187 u8 reserved_at_263[0x8]; 1188 u8 log_bf_reg_size[0x5]; 1189 1190 u8 reserved_at_270[0xb]; 1191 u8 lag_master[0x1]; 1192 u8 num_lag_ports[0x4]; 1193 1194 u8 reserved_at_280[0x10]; 1195 u8 max_wqe_sz_sq[0x10]; 1196 1197 u8 reserved_at_2a0[0x10]; 1198 u8 max_wqe_sz_rq[0x10]; 1199 1200 u8 max_flow_counter_31_16[0x10]; 1201 u8 max_wqe_sz_sq_dc[0x10]; 1202 1203 u8 reserved_at_2e0[0x7]; 1204 u8 max_qp_mcg[0x19]; 1205 1206 u8 reserved_at_300[0x18]; 1207 u8 log_max_mcg[0x8]; 1208 1209 u8 reserved_at_320[0x3]; 1210 u8 log_max_transport_domain[0x5]; 1211 u8 reserved_at_328[0x3]; 1212 u8 log_max_pd[0x5]; 1213 u8 reserved_at_330[0xb]; 1214 u8 log_max_xrcd[0x5]; 1215 1216 u8 nic_receive_steering_discard[0x1]; 1217 u8 receive_discard_vport_down[0x1]; 1218 u8 transmit_discard_vport_down[0x1]; 1219 u8 reserved_at_343[0x5]; 1220 u8 log_max_flow_counter_bulk[0x8]; 1221 u8 max_flow_counter_15_0[0x10]; 1222 1223 1224 u8 reserved_at_360[0x3]; 1225 u8 log_max_rq[0x5]; 1226 u8 reserved_at_368[0x3]; 1227 u8 log_max_sq[0x5]; 1228 u8 reserved_at_370[0x3]; 1229 u8 log_max_tir[0x5]; 1230 u8 reserved_at_378[0x3]; 1231 u8 log_max_tis[0x5]; 1232 1233 u8 basic_cyclic_rcv_wqe[0x1]; 1234 u8 reserved_at_381[0x2]; 1235 u8 log_max_rmp[0x5]; 1236 u8 reserved_at_388[0x3]; 1237 u8 log_max_rqt[0x5]; 1238 u8 reserved_at_390[0x3]; 1239 u8 log_max_rqt_size[0x5]; 1240 u8 reserved_at_398[0x3]; 1241 u8 log_max_tis_per_sq[0x5]; 1242 1243 u8 ext_stride_num_range[0x1]; 1244 u8 reserved_at_3a1[0x2]; 1245 u8 log_max_stride_sz_rq[0x5]; 1246 u8 reserved_at_3a8[0x3]; 1247 u8 log_min_stride_sz_rq[0x5]; 1248 u8 reserved_at_3b0[0x3]; 1249 u8 log_max_stride_sz_sq[0x5]; 1250 u8 reserved_at_3b8[0x3]; 1251 u8 log_min_stride_sz_sq[0x5]; 1252 1253 u8 hairpin[0x1]; 1254 u8 reserved_at_3c1[0x2]; 1255 u8 log_max_hairpin_queues[0x5]; 1256 u8 reserved_at_3c8[0x3]; 1257 u8 log_max_hairpin_wq_data_sz[0x5]; 1258 u8 reserved_at_3d0[0x3]; 1259 u8 log_max_hairpin_num_packets[0x5]; 1260 u8 reserved_at_3d8[0x3]; 1261 u8 log_max_wq_sz[0x5]; 1262 1263 u8 nic_vport_change_event[0x1]; 1264 u8 disable_local_lb_uc[0x1]; 1265 u8 disable_local_lb_mc[0x1]; 1266 u8 log_min_hairpin_wq_data_sz[0x5]; 1267 u8 reserved_at_3e8[0x3]; 1268 u8 log_max_vlan_list[0x5]; 1269 u8 reserved_at_3f0[0x3]; 1270 u8 log_max_current_mc_list[0x5]; 1271 u8 reserved_at_3f8[0x3]; 1272 u8 log_max_current_uc_list[0x5]; 1273 1274 u8 general_obj_types[0x40]; 1275 1276 u8 reserved_at_440[0x20]; 1277 1278 u8 reserved_at_460[0x3]; 1279 u8 log_max_uctx[0x5]; 1280 u8 reserved_at_468[0x3]; 1281 u8 log_max_umem[0x5]; 1282 u8 max_num_eqs[0x10]; 1283 1284 u8 reserved_at_480[0x3]; 1285 u8 log_max_l2_table[0x5]; 1286 u8 reserved_at_488[0x8]; 1287 u8 log_uar_page_sz[0x10]; 1288 1289 u8 reserved_at_4a0[0x20]; 1290 u8 device_frequency_mhz[0x20]; 1291 u8 device_frequency_khz[0x20]; 1292 1293 u8 reserved_at_500[0x20]; 1294 u8 num_of_uars_per_page[0x20]; 1295 1296 u8 flex_parser_protocols[0x20]; 1297 1298 u8 max_geneve_tlv_options[0x8]; 1299 u8 reserved_at_568[0x3]; 1300 u8 max_geneve_tlv_option_data_len[0x5]; 1301 u8 reserved_at_570[0x10]; 1302 1303 u8 reserved_at_580[0x3c]; 1304 u8 mini_cqe_resp_stride_index[0x1]; 1305 u8 cqe_128_always[0x1]; 1306 u8 cqe_compression_128[0x1]; 1307 u8 cqe_compression[0x1]; 1308 1309 u8 cqe_compression_timeout[0x10]; 1310 u8 cqe_compression_max_num[0x10]; 1311 1312 u8 reserved_at_5e0[0x10]; 1313 u8 tag_matching[0x1]; 1314 u8 rndv_offload_rc[0x1]; 1315 u8 rndv_offload_dc[0x1]; 1316 u8 log_tag_matching_list_sz[0x5]; 1317 u8 reserved_at_5f8[0x3]; 1318 u8 log_max_xrq[0x5]; 1319 1320 u8 affiliate_nic_vport_criteria[0x8]; 1321 u8 native_port_num[0x8]; 1322 u8 num_vhca_ports[0x8]; 1323 u8 reserved_at_618[0x6]; 1324 u8 sw_owner_id[0x1]; 1325 u8 reserved_at_61f[0x1]; 1326 1327 u8 max_num_of_monitor_counters[0x10]; 1328 u8 num_ppcnt_monitor_counters[0x10]; 1329 1330 u8 reserved_at_640[0x10]; 1331 u8 num_q_monitor_counters[0x10]; 1332 1333 u8 reserved_at_660[0x40]; 1334 1335 u8 uctx_cap[0x20]; 1336 1337 u8 reserved_at_6c0[0x4]; 1338 u8 flex_parser_id_geneve_tlv_option_0[0x4]; 1339 u8 reserved_at_6c8[0x138]; 1340 }; 1341 1342 enum mlx5_flow_destination_type { 1343 MLX5_FLOW_DESTINATION_TYPE_VPORT = 0x0, 1344 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1, 1345 MLX5_FLOW_DESTINATION_TYPE_TIR = 0x2, 1346 1347 MLX5_FLOW_DESTINATION_TYPE_PORT = 0x99, 1348 MLX5_FLOW_DESTINATION_TYPE_COUNTER = 0x100, 1349 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE_NUM = 0x101, 1350 }; 1351 1352 enum mlx5_flow_table_miss_action { 1353 MLX5_FLOW_TABLE_MISS_ACTION_DEF, 1354 MLX5_FLOW_TABLE_MISS_ACTION_FWD, 1355 MLX5_FLOW_TABLE_MISS_ACTION_SWITCH_DOMAIN, 1356 }; 1357 1358 struct mlx5_ifc_dest_format_struct_bits { 1359 u8 destination_type[0x8]; 1360 u8 destination_id[0x18]; 1361 1362 u8 destination_eswitch_owner_vhca_id_valid[0x1]; 1363 u8 packet_reformat[0x1]; 1364 u8 reserved_at_22[0xe]; 1365 u8 destination_eswitch_owner_vhca_id[0x10]; 1366 }; 1367 1368 struct mlx5_ifc_flow_counter_list_bits { 1369 u8 flow_counter_id[0x20]; 1370 1371 u8 reserved_at_20[0x20]; 1372 }; 1373 1374 struct mlx5_ifc_extended_dest_format_bits { 1375 struct mlx5_ifc_dest_format_struct_bits destination_entry; 1376 1377 u8 packet_reformat_id[0x20]; 1378 1379 u8 reserved_at_60[0x20]; 1380 }; 1381 1382 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits { 1383 struct mlx5_ifc_dest_format_struct_bits dest_format_struct; 1384 struct mlx5_ifc_flow_counter_list_bits flow_counter_list; 1385 u8 reserved_at_0[0x40]; 1386 }; 1387 1388 struct mlx5_ifc_fte_match_param_bits { 1389 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers; 1390 1391 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters; 1392 1393 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers; 1394 1395 struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2; 1396 1397 struct mlx5_ifc_fte_match_set_misc3_bits misc_parameters_3; 1398 1399 u8 reserved_at_a00[0x600]; 1400 }; 1401 1402 enum { 1403 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0, 1404 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1, 1405 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2, 1406 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3, 1407 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4, 1408 }; 1409 1410 struct mlx5_ifc_rx_hash_field_select_bits { 1411 u8 l3_prot_type[0x1]; 1412 u8 l4_prot_type[0x1]; 1413 u8 selected_fields[0x1e]; 1414 }; 1415 1416 enum { 1417 MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0, 1418 MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1, 1419 }; 1420 1421 enum { 1422 MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0, 1423 MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1, 1424 }; 1425 1426 struct mlx5_ifc_wq_bits { 1427 u8 wq_type[0x4]; 1428 u8 wq_signature[0x1]; 1429 u8 end_padding_mode[0x2]; 1430 u8 cd_slave[0x1]; 1431 u8 reserved_at_8[0x18]; 1432 1433 u8 hds_skip_first_sge[0x1]; 1434 u8 log2_hds_buf_size[0x3]; 1435 u8 reserved_at_24[0x7]; 1436 u8 page_offset[0x5]; 1437 u8 lwm[0x10]; 1438 1439 u8 reserved_at_40[0x8]; 1440 u8 pd[0x18]; 1441 1442 u8 reserved_at_60[0x8]; 1443 u8 uar_page[0x18]; 1444 1445 u8 dbr_addr[0x40]; 1446 1447 u8 hw_counter[0x20]; 1448 1449 u8 sw_counter[0x20]; 1450 1451 u8 reserved_at_100[0xc]; 1452 u8 log_wq_stride[0x4]; 1453 u8 reserved_at_110[0x3]; 1454 u8 log_wq_pg_sz[0x5]; 1455 u8 reserved_at_118[0x3]; 1456 u8 log_wq_sz[0x5]; 1457 1458 u8 dbr_umem_valid[0x1]; 1459 u8 wq_umem_valid[0x1]; 1460 u8 reserved_at_122[0x1]; 1461 u8 log_hairpin_num_packets[0x5]; 1462 u8 reserved_at_128[0x3]; 1463 u8 log_hairpin_data_sz[0x5]; 1464 1465 u8 reserved_at_130[0x4]; 1466 u8 log_wqe_num_of_strides[0x4]; 1467 u8 two_byte_shift_en[0x1]; 1468 u8 reserved_at_139[0x4]; 1469 u8 log_wqe_stride_size[0x3]; 1470 1471 u8 reserved_at_140[0x4c0]; 1472 1473 struct mlx5_ifc_cmd_pas_bits pas[0]; 1474 }; 1475 1476 struct mlx5_ifc_rq_num_bits { 1477 u8 reserved_at_0[0x8]; 1478 u8 rq_num[0x18]; 1479 }; 1480 1481 struct mlx5_ifc_mac_address_layout_bits { 1482 u8 reserved_at_0[0x10]; 1483 u8 mac_addr_47_32[0x10]; 1484 1485 u8 mac_addr_31_0[0x20]; 1486 }; 1487 1488 struct mlx5_ifc_vlan_layout_bits { 1489 u8 reserved_at_0[0x14]; 1490 u8 vlan[0x0c]; 1491 1492 u8 reserved_at_20[0x20]; 1493 }; 1494 1495 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits { 1496 u8 reserved_at_0[0xa0]; 1497 1498 u8 min_time_between_cnps[0x20]; 1499 1500 u8 reserved_at_c0[0x12]; 1501 u8 cnp_dscp[0x6]; 1502 u8 reserved_at_d8[0x4]; 1503 u8 cnp_prio_mode[0x1]; 1504 u8 cnp_802p_prio[0x3]; 1505 1506 u8 reserved_at_e0[0x720]; 1507 }; 1508 1509 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits { 1510 u8 reserved_at_0[0x60]; 1511 1512 u8 reserved_at_60[0x4]; 1513 u8 clamp_tgt_rate[0x1]; 1514 u8 reserved_at_65[0x3]; 1515 u8 clamp_tgt_rate_after_time_inc[0x1]; 1516 u8 reserved_at_69[0x17]; 1517 1518 u8 reserved_at_80[0x20]; 1519 1520 u8 rpg_time_reset[0x20]; 1521 1522 u8 rpg_byte_reset[0x20]; 1523 1524 u8 rpg_threshold[0x20]; 1525 1526 u8 rpg_max_rate[0x20]; 1527 1528 u8 rpg_ai_rate[0x20]; 1529 1530 u8 rpg_hai_rate[0x20]; 1531 1532 u8 rpg_gd[0x20]; 1533 1534 u8 rpg_min_dec_fac[0x20]; 1535 1536 u8 rpg_min_rate[0x20]; 1537 1538 u8 reserved_at_1c0[0xe0]; 1539 1540 u8 rate_to_set_on_first_cnp[0x20]; 1541 1542 u8 dce_tcp_g[0x20]; 1543 1544 u8 dce_tcp_rtt[0x20]; 1545 1546 u8 rate_reduce_monitor_period[0x20]; 1547 1548 u8 reserved_at_320[0x20]; 1549 1550 u8 initial_alpha_value[0x20]; 1551 1552 u8 reserved_at_360[0x4a0]; 1553 }; 1554 1555 struct mlx5_ifc_cong_control_802_1qau_rp_bits { 1556 u8 reserved_at_0[0x80]; 1557 1558 u8 rppp_max_rps[0x20]; 1559 1560 u8 rpg_time_reset[0x20]; 1561 1562 u8 rpg_byte_reset[0x20]; 1563 1564 u8 rpg_threshold[0x20]; 1565 1566 u8 rpg_max_rate[0x20]; 1567 1568 u8 rpg_ai_rate[0x20]; 1569 1570 u8 rpg_hai_rate[0x20]; 1571 1572 u8 rpg_gd[0x20]; 1573 1574 u8 rpg_min_dec_fac[0x20]; 1575 1576 u8 rpg_min_rate[0x20]; 1577 1578 u8 reserved_at_1c0[0x640]; 1579 }; 1580 1581 enum { 1582 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1, 1583 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2, 1584 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4, 1585 }; 1586 1587 struct mlx5_ifc_resize_field_select_bits { 1588 u8 resize_field_select[0x20]; 1589 }; 1590 1591 enum { 1592 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1, 1593 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2, 1594 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4, 1595 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8, 1596 }; 1597 1598 struct mlx5_ifc_modify_field_select_bits { 1599 u8 modify_field_select[0x20]; 1600 }; 1601 1602 struct mlx5_ifc_field_select_r_roce_np_bits { 1603 u8 field_select_r_roce_np[0x20]; 1604 }; 1605 1606 struct mlx5_ifc_field_select_r_roce_rp_bits { 1607 u8 field_select_r_roce_rp[0x20]; 1608 }; 1609 1610 enum { 1611 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4, 1612 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8, 1613 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10, 1614 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20, 1615 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40, 1616 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80, 1617 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100, 1618 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200, 1619 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400, 1620 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800, 1621 }; 1622 1623 struct mlx5_ifc_field_select_802_1qau_rp_bits { 1624 u8 field_select_8021qaurp[0x20]; 1625 }; 1626 1627 struct mlx5_ifc_phys_layer_cntrs_bits { 1628 u8 time_since_last_clear_high[0x20]; 1629 1630 u8 time_since_last_clear_low[0x20]; 1631 1632 u8 symbol_errors_high[0x20]; 1633 1634 u8 symbol_errors_low[0x20]; 1635 1636 u8 sync_headers_errors_high[0x20]; 1637 1638 u8 sync_headers_errors_low[0x20]; 1639 1640 u8 edpl_bip_errors_lane0_high[0x20]; 1641 1642 u8 edpl_bip_errors_lane0_low[0x20]; 1643 1644 u8 edpl_bip_errors_lane1_high[0x20]; 1645 1646 u8 edpl_bip_errors_lane1_low[0x20]; 1647 1648 u8 edpl_bip_errors_lane2_high[0x20]; 1649 1650 u8 edpl_bip_errors_lane2_low[0x20]; 1651 1652 u8 edpl_bip_errors_lane3_high[0x20]; 1653 1654 u8 edpl_bip_errors_lane3_low[0x20]; 1655 1656 u8 fc_fec_corrected_blocks_lane0_high[0x20]; 1657 1658 u8 fc_fec_corrected_blocks_lane0_low[0x20]; 1659 1660 u8 fc_fec_corrected_blocks_lane1_high[0x20]; 1661 1662 u8 fc_fec_corrected_blocks_lane1_low[0x20]; 1663 1664 u8 fc_fec_corrected_blocks_lane2_high[0x20]; 1665 1666 u8 fc_fec_corrected_blocks_lane2_low[0x20]; 1667 1668 u8 fc_fec_corrected_blocks_lane3_high[0x20]; 1669 1670 u8 fc_fec_corrected_blocks_lane3_low[0x20]; 1671 1672 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20]; 1673 1674 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20]; 1675 1676 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20]; 1677 1678 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20]; 1679 1680 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20]; 1681 1682 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20]; 1683 1684 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20]; 1685 1686 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20]; 1687 1688 u8 rs_fec_corrected_blocks_high[0x20]; 1689 1690 u8 rs_fec_corrected_blocks_low[0x20]; 1691 1692 u8 rs_fec_uncorrectable_blocks_high[0x20]; 1693 1694 u8 rs_fec_uncorrectable_blocks_low[0x20]; 1695 1696 u8 rs_fec_no_errors_blocks_high[0x20]; 1697 1698 u8 rs_fec_no_errors_blocks_low[0x20]; 1699 1700 u8 rs_fec_single_error_blocks_high[0x20]; 1701 1702 u8 rs_fec_single_error_blocks_low[0x20]; 1703 1704 u8 rs_fec_corrected_symbols_total_high[0x20]; 1705 1706 u8 rs_fec_corrected_symbols_total_low[0x20]; 1707 1708 u8 rs_fec_corrected_symbols_lane0_high[0x20]; 1709 1710 u8 rs_fec_corrected_symbols_lane0_low[0x20]; 1711 1712 u8 rs_fec_corrected_symbols_lane1_high[0x20]; 1713 1714 u8 rs_fec_corrected_symbols_lane1_low[0x20]; 1715 1716 u8 rs_fec_corrected_symbols_lane2_high[0x20]; 1717 1718 u8 rs_fec_corrected_symbols_lane2_low[0x20]; 1719 1720 u8 rs_fec_corrected_symbols_lane3_high[0x20]; 1721 1722 u8 rs_fec_corrected_symbols_lane3_low[0x20]; 1723 1724 u8 link_down_events[0x20]; 1725 1726 u8 successful_recovery_events[0x20]; 1727 1728 u8 reserved_at_640[0x180]; 1729 }; 1730 1731 struct mlx5_ifc_phys_layer_statistical_cntrs_bits { 1732 u8 time_since_last_clear_high[0x20]; 1733 1734 u8 time_since_last_clear_low[0x20]; 1735 1736 u8 phy_received_bits_high[0x20]; 1737 1738 u8 phy_received_bits_low[0x20]; 1739 1740 u8 phy_symbol_errors_high[0x20]; 1741 1742 u8 phy_symbol_errors_low[0x20]; 1743 1744 u8 phy_corrected_bits_high[0x20]; 1745 1746 u8 phy_corrected_bits_low[0x20]; 1747 1748 u8 phy_corrected_bits_lane0_high[0x20]; 1749 1750 u8 phy_corrected_bits_lane0_low[0x20]; 1751 1752 u8 phy_corrected_bits_lane1_high[0x20]; 1753 1754 u8 phy_corrected_bits_lane1_low[0x20]; 1755 1756 u8 phy_corrected_bits_lane2_high[0x20]; 1757 1758 u8 phy_corrected_bits_lane2_low[0x20]; 1759 1760 u8 phy_corrected_bits_lane3_high[0x20]; 1761 1762 u8 phy_corrected_bits_lane3_low[0x20]; 1763 1764 u8 reserved_at_200[0x5c0]; 1765 }; 1766 1767 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits { 1768 u8 symbol_error_counter[0x10]; 1769 1770 u8 link_error_recovery_counter[0x8]; 1771 1772 u8 link_downed_counter[0x8]; 1773 1774 u8 port_rcv_errors[0x10]; 1775 1776 u8 port_rcv_remote_physical_errors[0x10]; 1777 1778 u8 port_rcv_switch_relay_errors[0x10]; 1779 1780 u8 port_xmit_discards[0x10]; 1781 1782 u8 port_xmit_constraint_errors[0x8]; 1783 1784 u8 port_rcv_constraint_errors[0x8]; 1785 1786 u8 reserved_at_70[0x8]; 1787 1788 u8 link_overrun_errors[0x8]; 1789 1790 u8 reserved_at_80[0x10]; 1791 1792 u8 vl_15_dropped[0x10]; 1793 1794 u8 reserved_at_a0[0x80]; 1795 1796 u8 port_xmit_wait[0x20]; 1797 }; 1798 1799 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits { 1800 u8 transmit_queue_high[0x20]; 1801 1802 u8 transmit_queue_low[0x20]; 1803 1804 u8 reserved_at_40[0x780]; 1805 }; 1806 1807 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits { 1808 u8 rx_octets_high[0x20]; 1809 1810 u8 rx_octets_low[0x20]; 1811 1812 u8 reserved_at_40[0xc0]; 1813 1814 u8 rx_frames_high[0x20]; 1815 1816 u8 rx_frames_low[0x20]; 1817 1818 u8 tx_octets_high[0x20]; 1819 1820 u8 tx_octets_low[0x20]; 1821 1822 u8 reserved_at_180[0xc0]; 1823 1824 u8 tx_frames_high[0x20]; 1825 1826 u8 tx_frames_low[0x20]; 1827 1828 u8 rx_pause_high[0x20]; 1829 1830 u8 rx_pause_low[0x20]; 1831 1832 u8 rx_pause_duration_high[0x20]; 1833 1834 u8 rx_pause_duration_low[0x20]; 1835 1836 u8 tx_pause_high[0x20]; 1837 1838 u8 tx_pause_low[0x20]; 1839 1840 u8 tx_pause_duration_high[0x20]; 1841 1842 u8 tx_pause_duration_low[0x20]; 1843 1844 u8 rx_pause_transition_high[0x20]; 1845 1846 u8 rx_pause_transition_low[0x20]; 1847 1848 u8 reserved_at_3c0[0x40]; 1849 1850 u8 device_stall_minor_watermark_cnt_high[0x20]; 1851 1852 u8 device_stall_minor_watermark_cnt_low[0x20]; 1853 1854 u8 device_stall_critical_watermark_cnt_high[0x20]; 1855 1856 u8 device_stall_critical_watermark_cnt_low[0x20]; 1857 1858 u8 reserved_at_480[0x340]; 1859 }; 1860 1861 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits { 1862 u8 port_transmit_wait_high[0x20]; 1863 1864 u8 port_transmit_wait_low[0x20]; 1865 1866 u8 reserved_at_40[0x100]; 1867 1868 u8 rx_buffer_almost_full_high[0x20]; 1869 1870 u8 rx_buffer_almost_full_low[0x20]; 1871 1872 u8 rx_buffer_full_high[0x20]; 1873 1874 u8 rx_buffer_full_low[0x20]; 1875 1876 u8 rx_icrc_encapsulated_high[0x20]; 1877 1878 u8 rx_icrc_encapsulated_low[0x20]; 1879 1880 u8 reserved_at_200[0x5c0]; 1881 }; 1882 1883 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits { 1884 u8 dot3stats_alignment_errors_high[0x20]; 1885 1886 u8 dot3stats_alignment_errors_low[0x20]; 1887 1888 u8 dot3stats_fcs_errors_high[0x20]; 1889 1890 u8 dot3stats_fcs_errors_low[0x20]; 1891 1892 u8 dot3stats_single_collision_frames_high[0x20]; 1893 1894 u8 dot3stats_single_collision_frames_low[0x20]; 1895 1896 u8 dot3stats_multiple_collision_frames_high[0x20]; 1897 1898 u8 dot3stats_multiple_collision_frames_low[0x20]; 1899 1900 u8 dot3stats_sqe_test_errors_high[0x20]; 1901 1902 u8 dot3stats_sqe_test_errors_low[0x20]; 1903 1904 u8 dot3stats_deferred_transmissions_high[0x20]; 1905 1906 u8 dot3stats_deferred_transmissions_low[0x20]; 1907 1908 u8 dot3stats_late_collisions_high[0x20]; 1909 1910 u8 dot3stats_late_collisions_low[0x20]; 1911 1912 u8 dot3stats_excessive_collisions_high[0x20]; 1913 1914 u8 dot3stats_excessive_collisions_low[0x20]; 1915 1916 u8 dot3stats_internal_mac_transmit_errors_high[0x20]; 1917 1918 u8 dot3stats_internal_mac_transmit_errors_low[0x20]; 1919 1920 u8 dot3stats_carrier_sense_errors_high[0x20]; 1921 1922 u8 dot3stats_carrier_sense_errors_low[0x20]; 1923 1924 u8 dot3stats_frame_too_longs_high[0x20]; 1925 1926 u8 dot3stats_frame_too_longs_low[0x20]; 1927 1928 u8 dot3stats_internal_mac_receive_errors_high[0x20]; 1929 1930 u8 dot3stats_internal_mac_receive_errors_low[0x20]; 1931 1932 u8 dot3stats_symbol_errors_high[0x20]; 1933 1934 u8 dot3stats_symbol_errors_low[0x20]; 1935 1936 u8 dot3control_in_unknown_opcodes_high[0x20]; 1937 1938 u8 dot3control_in_unknown_opcodes_low[0x20]; 1939 1940 u8 dot3in_pause_frames_high[0x20]; 1941 1942 u8 dot3in_pause_frames_low[0x20]; 1943 1944 u8 dot3out_pause_frames_high[0x20]; 1945 1946 u8 dot3out_pause_frames_low[0x20]; 1947 1948 u8 reserved_at_400[0x3c0]; 1949 }; 1950 1951 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits { 1952 u8 ether_stats_drop_events_high[0x20]; 1953 1954 u8 ether_stats_drop_events_low[0x20]; 1955 1956 u8 ether_stats_octets_high[0x20]; 1957 1958 u8 ether_stats_octets_low[0x20]; 1959 1960 u8 ether_stats_pkts_high[0x20]; 1961 1962 u8 ether_stats_pkts_low[0x20]; 1963 1964 u8 ether_stats_broadcast_pkts_high[0x20]; 1965 1966 u8 ether_stats_broadcast_pkts_low[0x20]; 1967 1968 u8 ether_stats_multicast_pkts_high[0x20]; 1969 1970 u8 ether_stats_multicast_pkts_low[0x20]; 1971 1972 u8 ether_stats_crc_align_errors_high[0x20]; 1973 1974 u8 ether_stats_crc_align_errors_low[0x20]; 1975 1976 u8 ether_stats_undersize_pkts_high[0x20]; 1977 1978 u8 ether_stats_undersize_pkts_low[0x20]; 1979 1980 u8 ether_stats_oversize_pkts_high[0x20]; 1981 1982 u8 ether_stats_oversize_pkts_low[0x20]; 1983 1984 u8 ether_stats_fragments_high[0x20]; 1985 1986 u8 ether_stats_fragments_low[0x20]; 1987 1988 u8 ether_stats_jabbers_high[0x20]; 1989 1990 u8 ether_stats_jabbers_low[0x20]; 1991 1992 u8 ether_stats_collisions_high[0x20]; 1993 1994 u8 ether_stats_collisions_low[0x20]; 1995 1996 u8 ether_stats_pkts64octets_high[0x20]; 1997 1998 u8 ether_stats_pkts64octets_low[0x20]; 1999 2000 u8 ether_stats_pkts65to127octets_high[0x20]; 2001 2002 u8 ether_stats_pkts65to127octets_low[0x20]; 2003 2004 u8 ether_stats_pkts128to255octets_high[0x20]; 2005 2006 u8 ether_stats_pkts128to255octets_low[0x20]; 2007 2008 u8 ether_stats_pkts256to511octets_high[0x20]; 2009 2010 u8 ether_stats_pkts256to511octets_low[0x20]; 2011 2012 u8 ether_stats_pkts512to1023octets_high[0x20]; 2013 2014 u8 ether_stats_pkts512to1023octets_low[0x20]; 2015 2016 u8 ether_stats_pkts1024to1518octets_high[0x20]; 2017 2018 u8 ether_stats_pkts1024to1518octets_low[0x20]; 2019 2020 u8 ether_stats_pkts1519to2047octets_high[0x20]; 2021 2022 u8 ether_stats_pkts1519to2047octets_low[0x20]; 2023 2024 u8 ether_stats_pkts2048to4095octets_high[0x20]; 2025 2026 u8 ether_stats_pkts2048to4095octets_low[0x20]; 2027 2028 u8 ether_stats_pkts4096to8191octets_high[0x20]; 2029 2030 u8 ether_stats_pkts4096to8191octets_low[0x20]; 2031 2032 u8 ether_stats_pkts8192to10239octets_high[0x20]; 2033 2034 u8 ether_stats_pkts8192to10239octets_low[0x20]; 2035 2036 u8 reserved_at_540[0x280]; 2037 }; 2038 2039 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits { 2040 u8 if_in_octets_high[0x20]; 2041 2042 u8 if_in_octets_low[0x20]; 2043 2044 u8 if_in_ucast_pkts_high[0x20]; 2045 2046 u8 if_in_ucast_pkts_low[0x20]; 2047 2048 u8 if_in_discards_high[0x20]; 2049 2050 u8 if_in_discards_low[0x20]; 2051 2052 u8 if_in_errors_high[0x20]; 2053 2054 u8 if_in_errors_low[0x20]; 2055 2056 u8 if_in_unknown_protos_high[0x20]; 2057 2058 u8 if_in_unknown_protos_low[0x20]; 2059 2060 u8 if_out_octets_high[0x20]; 2061 2062 u8 if_out_octets_low[0x20]; 2063 2064 u8 if_out_ucast_pkts_high[0x20]; 2065 2066 u8 if_out_ucast_pkts_low[0x20]; 2067 2068 u8 if_out_discards_high[0x20]; 2069 2070 u8 if_out_discards_low[0x20]; 2071 2072 u8 if_out_errors_high[0x20]; 2073 2074 u8 if_out_errors_low[0x20]; 2075 2076 u8 if_in_multicast_pkts_high[0x20]; 2077 2078 u8 if_in_multicast_pkts_low[0x20]; 2079 2080 u8 if_in_broadcast_pkts_high[0x20]; 2081 2082 u8 if_in_broadcast_pkts_low[0x20]; 2083 2084 u8 if_out_multicast_pkts_high[0x20]; 2085 2086 u8 if_out_multicast_pkts_low[0x20]; 2087 2088 u8 if_out_broadcast_pkts_high[0x20]; 2089 2090 u8 if_out_broadcast_pkts_low[0x20]; 2091 2092 u8 reserved_at_340[0x480]; 2093 }; 2094 2095 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits { 2096 u8 a_frames_transmitted_ok_high[0x20]; 2097 2098 u8 a_frames_transmitted_ok_low[0x20]; 2099 2100 u8 a_frames_received_ok_high[0x20]; 2101 2102 u8 a_frames_received_ok_low[0x20]; 2103 2104 u8 a_frame_check_sequence_errors_high[0x20]; 2105 2106 u8 a_frame_check_sequence_errors_low[0x20]; 2107 2108 u8 a_alignment_errors_high[0x20]; 2109 2110 u8 a_alignment_errors_low[0x20]; 2111 2112 u8 a_octets_transmitted_ok_high[0x20]; 2113 2114 u8 a_octets_transmitted_ok_low[0x20]; 2115 2116 u8 a_octets_received_ok_high[0x20]; 2117 2118 u8 a_octets_received_ok_low[0x20]; 2119 2120 u8 a_multicast_frames_xmitted_ok_high[0x20]; 2121 2122 u8 a_multicast_frames_xmitted_ok_low[0x20]; 2123 2124 u8 a_broadcast_frames_xmitted_ok_high[0x20]; 2125 2126 u8 a_broadcast_frames_xmitted_ok_low[0x20]; 2127 2128 u8 a_multicast_frames_received_ok_high[0x20]; 2129 2130 u8 a_multicast_frames_received_ok_low[0x20]; 2131 2132 u8 a_broadcast_frames_received_ok_high[0x20]; 2133 2134 u8 a_broadcast_frames_received_ok_low[0x20]; 2135 2136 u8 a_in_range_length_errors_high[0x20]; 2137 2138 u8 a_in_range_length_errors_low[0x20]; 2139 2140 u8 a_out_of_range_length_field_high[0x20]; 2141 2142 u8 a_out_of_range_length_field_low[0x20]; 2143 2144 u8 a_frame_too_long_errors_high[0x20]; 2145 2146 u8 a_frame_too_long_errors_low[0x20]; 2147 2148 u8 a_symbol_error_during_carrier_high[0x20]; 2149 2150 u8 a_symbol_error_during_carrier_low[0x20]; 2151 2152 u8 a_mac_control_frames_transmitted_high[0x20]; 2153 2154 u8 a_mac_control_frames_transmitted_low[0x20]; 2155 2156 u8 a_mac_control_frames_received_high[0x20]; 2157 2158 u8 a_mac_control_frames_received_low[0x20]; 2159 2160 u8 a_unsupported_opcodes_received_high[0x20]; 2161 2162 u8 a_unsupported_opcodes_received_low[0x20]; 2163 2164 u8 a_pause_mac_ctrl_frames_received_high[0x20]; 2165 2166 u8 a_pause_mac_ctrl_frames_received_low[0x20]; 2167 2168 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20]; 2169 2170 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20]; 2171 2172 u8 reserved_at_4c0[0x300]; 2173 }; 2174 2175 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits { 2176 u8 life_time_counter_high[0x20]; 2177 2178 u8 life_time_counter_low[0x20]; 2179 2180 u8 rx_errors[0x20]; 2181 2182 u8 tx_errors[0x20]; 2183 2184 u8 l0_to_recovery_eieos[0x20]; 2185 2186 u8 l0_to_recovery_ts[0x20]; 2187 2188 u8 l0_to_recovery_framing[0x20]; 2189 2190 u8 l0_to_recovery_retrain[0x20]; 2191 2192 u8 crc_error_dllp[0x20]; 2193 2194 u8 crc_error_tlp[0x20]; 2195 2196 u8 tx_overflow_buffer_pkt_high[0x20]; 2197 2198 u8 tx_overflow_buffer_pkt_low[0x20]; 2199 2200 u8 outbound_stalled_reads[0x20]; 2201 2202 u8 outbound_stalled_writes[0x20]; 2203 2204 u8 outbound_stalled_reads_events[0x20]; 2205 2206 u8 outbound_stalled_writes_events[0x20]; 2207 2208 u8 reserved_at_200[0x5c0]; 2209 }; 2210 2211 struct mlx5_ifc_cmd_inter_comp_event_bits { 2212 u8 command_completion_vector[0x20]; 2213 2214 u8 reserved_at_20[0xc0]; 2215 }; 2216 2217 struct mlx5_ifc_stall_vl_event_bits { 2218 u8 reserved_at_0[0x18]; 2219 u8 port_num[0x1]; 2220 u8 reserved_at_19[0x3]; 2221 u8 vl[0x4]; 2222 2223 u8 reserved_at_20[0xa0]; 2224 }; 2225 2226 struct mlx5_ifc_db_bf_congestion_event_bits { 2227 u8 event_subtype[0x8]; 2228 u8 reserved_at_8[0x8]; 2229 u8 congestion_level[0x8]; 2230 u8 reserved_at_18[0x8]; 2231 2232 u8 reserved_at_20[0xa0]; 2233 }; 2234 2235 struct mlx5_ifc_gpio_event_bits { 2236 u8 reserved_at_0[0x60]; 2237 2238 u8 gpio_event_hi[0x20]; 2239 2240 u8 gpio_event_lo[0x20]; 2241 2242 u8 reserved_at_a0[0x40]; 2243 }; 2244 2245 struct mlx5_ifc_port_state_change_event_bits { 2246 u8 reserved_at_0[0x40]; 2247 2248 u8 port_num[0x4]; 2249 u8 reserved_at_44[0x1c]; 2250 2251 u8 reserved_at_60[0x80]; 2252 }; 2253 2254 struct mlx5_ifc_dropped_packet_logged_bits { 2255 u8 reserved_at_0[0xe0]; 2256 }; 2257 2258 enum { 2259 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1, 2260 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2, 2261 }; 2262 2263 struct mlx5_ifc_cq_error_bits { 2264 u8 reserved_at_0[0x8]; 2265 u8 cqn[0x18]; 2266 2267 u8 reserved_at_20[0x20]; 2268 2269 u8 reserved_at_40[0x18]; 2270 u8 syndrome[0x8]; 2271 2272 u8 reserved_at_60[0x80]; 2273 }; 2274 2275 struct mlx5_ifc_rdma_page_fault_event_bits { 2276 u8 bytes_committed[0x20]; 2277 2278 u8 r_key[0x20]; 2279 2280 u8 reserved_at_40[0x10]; 2281 u8 packet_len[0x10]; 2282 2283 u8 rdma_op_len[0x20]; 2284 2285 u8 rdma_va[0x40]; 2286 2287 u8 reserved_at_c0[0x5]; 2288 u8 rdma[0x1]; 2289 u8 write[0x1]; 2290 u8 requestor[0x1]; 2291 u8 qp_number[0x18]; 2292 }; 2293 2294 struct mlx5_ifc_wqe_associated_page_fault_event_bits { 2295 u8 bytes_committed[0x20]; 2296 2297 u8 reserved_at_20[0x10]; 2298 u8 wqe_index[0x10]; 2299 2300 u8 reserved_at_40[0x10]; 2301 u8 len[0x10]; 2302 2303 u8 reserved_at_60[0x60]; 2304 2305 u8 reserved_at_c0[0x5]; 2306 u8 rdma[0x1]; 2307 u8 write_read[0x1]; 2308 u8 requestor[0x1]; 2309 u8 qpn[0x18]; 2310 }; 2311 2312 struct mlx5_ifc_qp_events_bits { 2313 u8 reserved_at_0[0xa0]; 2314 2315 u8 type[0x8]; 2316 u8 reserved_at_a8[0x18]; 2317 2318 u8 reserved_at_c0[0x8]; 2319 u8 qpn_rqn_sqn[0x18]; 2320 }; 2321 2322 struct mlx5_ifc_dct_events_bits { 2323 u8 reserved_at_0[0xc0]; 2324 2325 u8 reserved_at_c0[0x8]; 2326 u8 dct_number[0x18]; 2327 }; 2328 2329 struct mlx5_ifc_comp_event_bits { 2330 u8 reserved_at_0[0xc0]; 2331 2332 u8 reserved_at_c0[0x8]; 2333 u8 cq_number[0x18]; 2334 }; 2335 2336 enum { 2337 MLX5_QPC_STATE_RST = 0x0, 2338 MLX5_QPC_STATE_INIT = 0x1, 2339 MLX5_QPC_STATE_RTR = 0x2, 2340 MLX5_QPC_STATE_RTS = 0x3, 2341 MLX5_QPC_STATE_SQER = 0x4, 2342 MLX5_QPC_STATE_ERR = 0x6, 2343 MLX5_QPC_STATE_SQD = 0x7, 2344 MLX5_QPC_STATE_SUSPENDED = 0x9, 2345 }; 2346 2347 enum { 2348 MLX5_QPC_ST_RC = 0x0, 2349 MLX5_QPC_ST_UC = 0x1, 2350 MLX5_QPC_ST_UD = 0x2, 2351 MLX5_QPC_ST_XRC = 0x3, 2352 MLX5_QPC_ST_DCI = 0x5, 2353 MLX5_QPC_ST_QP0 = 0x7, 2354 MLX5_QPC_ST_QP1 = 0x8, 2355 MLX5_QPC_ST_RAW_DATAGRAM = 0x9, 2356 MLX5_QPC_ST_REG_UMR = 0xc, 2357 }; 2358 2359 enum { 2360 MLX5_QPC_PM_STATE_ARMED = 0x0, 2361 MLX5_QPC_PM_STATE_REARM = 0x1, 2362 MLX5_QPC_PM_STATE_RESERVED = 0x2, 2363 MLX5_QPC_PM_STATE_MIGRATED = 0x3, 2364 }; 2365 2366 enum { 2367 MLX5_QPC_OFFLOAD_TYPE_RNDV = 0x1, 2368 }; 2369 2370 enum { 2371 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0, 2372 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1, 2373 }; 2374 2375 enum { 2376 MLX5_QPC_MTU_256_BYTES = 0x1, 2377 MLX5_QPC_MTU_512_BYTES = 0x2, 2378 MLX5_QPC_MTU_1K_BYTES = 0x3, 2379 MLX5_QPC_MTU_2K_BYTES = 0x4, 2380 MLX5_QPC_MTU_4K_BYTES = 0x5, 2381 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7, 2382 }; 2383 2384 enum { 2385 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1, 2386 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2, 2387 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3, 2388 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4, 2389 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5, 2390 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6, 2391 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7, 2392 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8, 2393 }; 2394 2395 enum { 2396 MLX5_QPC_CS_REQ_DISABLE = 0x0, 2397 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11, 2398 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22, 2399 }; 2400 2401 enum { 2402 MLX5_QPC_CS_RES_DISABLE = 0x0, 2403 MLX5_QPC_CS_RES_UP_TO_32B = 0x1, 2404 MLX5_QPC_CS_RES_UP_TO_64B = 0x2, 2405 }; 2406 2407 struct mlx5_ifc_qpc_bits { 2408 u8 state[0x4]; 2409 u8 lag_tx_port_affinity[0x4]; 2410 u8 st[0x8]; 2411 u8 reserved_at_10[0x3]; 2412 u8 pm_state[0x2]; 2413 u8 reserved_at_15[0x1]; 2414 u8 req_e2e_credit_mode[0x2]; 2415 u8 offload_type[0x4]; 2416 u8 end_padding_mode[0x2]; 2417 u8 reserved_at_1e[0x2]; 2418 2419 u8 wq_signature[0x1]; 2420 u8 block_lb_mc[0x1]; 2421 u8 atomic_like_write_en[0x1]; 2422 u8 latency_sensitive[0x1]; 2423 u8 reserved_at_24[0x1]; 2424 u8 drain_sigerr[0x1]; 2425 u8 reserved_at_26[0x2]; 2426 u8 pd[0x18]; 2427 2428 u8 mtu[0x3]; 2429 u8 log_msg_max[0x5]; 2430 u8 reserved_at_48[0x1]; 2431 u8 log_rq_size[0x4]; 2432 u8 log_rq_stride[0x3]; 2433 u8 no_sq[0x1]; 2434 u8 log_sq_size[0x4]; 2435 u8 reserved_at_55[0x6]; 2436 u8 rlky[0x1]; 2437 u8 ulp_stateless_offload_mode[0x4]; 2438 2439 u8 counter_set_id[0x8]; 2440 u8 uar_page[0x18]; 2441 2442 u8 reserved_at_80[0x8]; 2443 u8 user_index[0x18]; 2444 2445 u8 reserved_at_a0[0x3]; 2446 u8 log_page_size[0x5]; 2447 u8 remote_qpn[0x18]; 2448 2449 struct mlx5_ifc_ads_bits primary_address_path; 2450 2451 struct mlx5_ifc_ads_bits secondary_address_path; 2452 2453 u8 log_ack_req_freq[0x4]; 2454 u8 reserved_at_384[0x4]; 2455 u8 log_sra_max[0x3]; 2456 u8 reserved_at_38b[0x2]; 2457 u8 retry_count[0x3]; 2458 u8 rnr_retry[0x3]; 2459 u8 reserved_at_393[0x1]; 2460 u8 fre[0x1]; 2461 u8 cur_rnr_retry[0x3]; 2462 u8 cur_retry_count[0x3]; 2463 u8 reserved_at_39b[0x5]; 2464 2465 u8 reserved_at_3a0[0x20]; 2466 2467 u8 reserved_at_3c0[0x8]; 2468 u8 next_send_psn[0x18]; 2469 2470 u8 reserved_at_3e0[0x8]; 2471 u8 cqn_snd[0x18]; 2472 2473 u8 reserved_at_400[0x8]; 2474 u8 deth_sqpn[0x18]; 2475 2476 u8 reserved_at_420[0x20]; 2477 2478 u8 reserved_at_440[0x8]; 2479 u8 last_acked_psn[0x18]; 2480 2481 u8 reserved_at_460[0x8]; 2482 u8 ssn[0x18]; 2483 2484 u8 reserved_at_480[0x8]; 2485 u8 log_rra_max[0x3]; 2486 u8 reserved_at_48b[0x1]; 2487 u8 atomic_mode[0x4]; 2488 u8 rre[0x1]; 2489 u8 rwe[0x1]; 2490 u8 rae[0x1]; 2491 u8 reserved_at_493[0x1]; 2492 u8 page_offset[0x6]; 2493 u8 reserved_at_49a[0x3]; 2494 u8 cd_slave_receive[0x1]; 2495 u8 cd_slave_send[0x1]; 2496 u8 cd_master[0x1]; 2497 2498 u8 reserved_at_4a0[0x3]; 2499 u8 min_rnr_nak[0x5]; 2500 u8 next_rcv_psn[0x18]; 2501 2502 u8 reserved_at_4c0[0x8]; 2503 u8 xrcd[0x18]; 2504 2505 u8 reserved_at_4e0[0x8]; 2506 u8 cqn_rcv[0x18]; 2507 2508 u8 dbr_addr[0x40]; 2509 2510 u8 q_key[0x20]; 2511 2512 u8 reserved_at_560[0x5]; 2513 u8 rq_type[0x3]; 2514 u8 srqn_rmpn_xrqn[0x18]; 2515 2516 u8 reserved_at_580[0x8]; 2517 u8 rmsn[0x18]; 2518 2519 u8 hw_sq_wqebb_counter[0x10]; 2520 u8 sw_sq_wqebb_counter[0x10]; 2521 2522 u8 hw_rq_counter[0x20]; 2523 2524 u8 sw_rq_counter[0x20]; 2525 2526 u8 reserved_at_600[0x20]; 2527 2528 u8 reserved_at_620[0xf]; 2529 u8 cgs[0x1]; 2530 u8 cs_req[0x8]; 2531 u8 cs_res[0x8]; 2532 2533 u8 dc_access_key[0x40]; 2534 2535 u8 reserved_at_680[0x3]; 2536 u8 dbr_umem_valid[0x1]; 2537 2538 u8 reserved_at_684[0xbc]; 2539 }; 2540 2541 struct mlx5_ifc_roce_addr_layout_bits { 2542 u8 source_l3_address[16][0x8]; 2543 2544 u8 reserved_at_80[0x3]; 2545 u8 vlan_valid[0x1]; 2546 u8 vlan_id[0xc]; 2547 u8 source_mac_47_32[0x10]; 2548 2549 u8 source_mac_31_0[0x20]; 2550 2551 u8 reserved_at_c0[0x14]; 2552 u8 roce_l3_type[0x4]; 2553 u8 roce_version[0x8]; 2554 2555 u8 reserved_at_e0[0x20]; 2556 }; 2557 2558 union mlx5_ifc_hca_cap_union_bits { 2559 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap; 2560 struct mlx5_ifc_odp_cap_bits odp_cap; 2561 struct mlx5_ifc_atomic_caps_bits atomic_caps; 2562 struct mlx5_ifc_roce_cap_bits roce_cap; 2563 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps; 2564 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap; 2565 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap; 2566 struct mlx5_ifc_e_switch_cap_bits e_switch_cap; 2567 struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap; 2568 struct mlx5_ifc_qos_cap_bits qos_cap; 2569 struct mlx5_ifc_debug_cap_bits debug_cap; 2570 struct mlx5_ifc_fpga_cap_bits fpga_cap; 2571 u8 reserved_at_0[0x8000]; 2572 }; 2573 2574 enum { 2575 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1, 2576 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2, 2577 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4, 2578 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8, 2579 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT = 0x10, 2580 MLX5_FLOW_CONTEXT_ACTION_DECAP = 0x20, 2581 MLX5_FLOW_CONTEXT_ACTION_MOD_HDR = 0x40, 2582 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP = 0x80, 2583 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100, 2584 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2 = 0x400, 2585 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2 = 0x800, 2586 }; 2587 2588 enum { 2589 MLX5_FLOW_CONTEXT_FLOW_SOURCE_ANY_VPORT = 0x0, 2590 MLX5_FLOW_CONTEXT_FLOW_SOURCE_UPLINK = 0x1, 2591 MLX5_FLOW_CONTEXT_FLOW_SOURCE_LOCAL_VPORT = 0x2, 2592 }; 2593 2594 struct mlx5_ifc_vlan_bits { 2595 u8 ethtype[0x10]; 2596 u8 prio[0x3]; 2597 u8 cfi[0x1]; 2598 u8 vid[0xc]; 2599 }; 2600 2601 struct mlx5_ifc_flow_context_bits { 2602 struct mlx5_ifc_vlan_bits push_vlan; 2603 2604 u8 group_id[0x20]; 2605 2606 u8 reserved_at_40[0x8]; 2607 u8 flow_tag[0x18]; 2608 2609 u8 reserved_at_60[0x10]; 2610 u8 action[0x10]; 2611 2612 u8 extended_destination[0x1]; 2613 u8 reserved_at_81[0x1]; 2614 u8 flow_source[0x2]; 2615 u8 reserved_at_84[0x4]; 2616 u8 destination_list_size[0x18]; 2617 2618 u8 reserved_at_a0[0x8]; 2619 u8 flow_counter_list_size[0x18]; 2620 2621 u8 packet_reformat_id[0x20]; 2622 2623 u8 modify_header_id[0x20]; 2624 2625 struct mlx5_ifc_vlan_bits push_vlan_2; 2626 2627 u8 reserved_at_120[0xe0]; 2628 2629 struct mlx5_ifc_fte_match_param_bits match_value; 2630 2631 u8 reserved_at_1200[0x600]; 2632 2633 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[0]; 2634 }; 2635 2636 enum { 2637 MLX5_XRC_SRQC_STATE_GOOD = 0x0, 2638 MLX5_XRC_SRQC_STATE_ERROR = 0x1, 2639 }; 2640 2641 struct mlx5_ifc_xrc_srqc_bits { 2642 u8 state[0x4]; 2643 u8 log_xrc_srq_size[0x4]; 2644 u8 reserved_at_8[0x18]; 2645 2646 u8 wq_signature[0x1]; 2647 u8 cont_srq[0x1]; 2648 u8 reserved_at_22[0x1]; 2649 u8 rlky[0x1]; 2650 u8 basic_cyclic_rcv_wqe[0x1]; 2651 u8 log_rq_stride[0x3]; 2652 u8 xrcd[0x18]; 2653 2654 u8 page_offset[0x6]; 2655 u8 reserved_at_46[0x1]; 2656 u8 dbr_umem_valid[0x1]; 2657 u8 cqn[0x18]; 2658 2659 u8 reserved_at_60[0x20]; 2660 2661 u8 user_index_equal_xrc_srqn[0x1]; 2662 u8 reserved_at_81[0x1]; 2663 u8 log_page_size[0x6]; 2664 u8 user_index[0x18]; 2665 2666 u8 reserved_at_a0[0x20]; 2667 2668 u8 reserved_at_c0[0x8]; 2669 u8 pd[0x18]; 2670 2671 u8 lwm[0x10]; 2672 u8 wqe_cnt[0x10]; 2673 2674 u8 reserved_at_100[0x40]; 2675 2676 u8 db_record_addr_h[0x20]; 2677 2678 u8 db_record_addr_l[0x1e]; 2679 u8 reserved_at_17e[0x2]; 2680 2681 u8 reserved_at_180[0x80]; 2682 }; 2683 2684 struct mlx5_ifc_vnic_diagnostic_statistics_bits { 2685 u8 counter_error_queues[0x20]; 2686 2687 u8 total_error_queues[0x20]; 2688 2689 u8 send_queue_priority_update_flow[0x20]; 2690 2691 u8 reserved_at_60[0x20]; 2692 2693 u8 nic_receive_steering_discard[0x40]; 2694 2695 u8 receive_discard_vport_down[0x40]; 2696 2697 u8 transmit_discard_vport_down[0x40]; 2698 2699 u8 reserved_at_140[0xec0]; 2700 }; 2701 2702 struct mlx5_ifc_traffic_counter_bits { 2703 u8 packets[0x40]; 2704 2705 u8 octets[0x40]; 2706 }; 2707 2708 struct mlx5_ifc_tisc_bits { 2709 u8 strict_lag_tx_port_affinity[0x1]; 2710 u8 reserved_at_1[0x3]; 2711 u8 lag_tx_port_affinity[0x04]; 2712 2713 u8 reserved_at_8[0x4]; 2714 u8 prio[0x4]; 2715 u8 reserved_at_10[0x10]; 2716 2717 u8 reserved_at_20[0x100]; 2718 2719 u8 reserved_at_120[0x8]; 2720 u8 transport_domain[0x18]; 2721 2722 u8 reserved_at_140[0x8]; 2723 u8 underlay_qpn[0x18]; 2724 u8 reserved_at_160[0x3a0]; 2725 }; 2726 2727 enum { 2728 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0, 2729 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1, 2730 }; 2731 2732 enum { 2733 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO = 0x1, 2734 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO = 0x2, 2735 }; 2736 2737 enum { 2738 MLX5_RX_HASH_FN_NONE = 0x0, 2739 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1, 2740 MLX5_RX_HASH_FN_TOEPLITZ = 0x2, 2741 }; 2742 2743 enum { 2744 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST = 0x1, 2745 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST = 0x2, 2746 }; 2747 2748 struct mlx5_ifc_tirc_bits { 2749 u8 reserved_at_0[0x20]; 2750 2751 u8 disp_type[0x4]; 2752 u8 reserved_at_24[0x1c]; 2753 2754 u8 reserved_at_40[0x40]; 2755 2756 u8 reserved_at_80[0x4]; 2757 u8 lro_timeout_period_usecs[0x10]; 2758 u8 lro_enable_mask[0x4]; 2759 u8 lro_max_ip_payload_size[0x8]; 2760 2761 u8 reserved_at_a0[0x40]; 2762 2763 u8 reserved_at_e0[0x8]; 2764 u8 inline_rqn[0x18]; 2765 2766 u8 rx_hash_symmetric[0x1]; 2767 u8 reserved_at_101[0x1]; 2768 u8 tunneled_offload_en[0x1]; 2769 u8 reserved_at_103[0x5]; 2770 u8 indirect_table[0x18]; 2771 2772 u8 rx_hash_fn[0x4]; 2773 u8 reserved_at_124[0x2]; 2774 u8 self_lb_block[0x2]; 2775 u8 transport_domain[0x18]; 2776 2777 u8 rx_hash_toeplitz_key[10][0x20]; 2778 2779 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer; 2780 2781 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner; 2782 2783 u8 reserved_at_2c0[0x4c0]; 2784 }; 2785 2786 enum { 2787 MLX5_SRQC_STATE_GOOD = 0x0, 2788 MLX5_SRQC_STATE_ERROR = 0x1, 2789 }; 2790 2791 struct mlx5_ifc_srqc_bits { 2792 u8 state[0x4]; 2793 u8 log_srq_size[0x4]; 2794 u8 reserved_at_8[0x18]; 2795 2796 u8 wq_signature[0x1]; 2797 u8 cont_srq[0x1]; 2798 u8 reserved_at_22[0x1]; 2799 u8 rlky[0x1]; 2800 u8 reserved_at_24[0x1]; 2801 u8 log_rq_stride[0x3]; 2802 u8 xrcd[0x18]; 2803 2804 u8 page_offset[0x6]; 2805 u8 reserved_at_46[0x2]; 2806 u8 cqn[0x18]; 2807 2808 u8 reserved_at_60[0x20]; 2809 2810 u8 reserved_at_80[0x2]; 2811 u8 log_page_size[0x6]; 2812 u8 reserved_at_88[0x18]; 2813 2814 u8 reserved_at_a0[0x20]; 2815 2816 u8 reserved_at_c0[0x8]; 2817 u8 pd[0x18]; 2818 2819 u8 lwm[0x10]; 2820 u8 wqe_cnt[0x10]; 2821 2822 u8 reserved_at_100[0x40]; 2823 2824 u8 dbr_addr[0x40]; 2825 2826 u8 reserved_at_180[0x80]; 2827 }; 2828 2829 enum { 2830 MLX5_SQC_STATE_RST = 0x0, 2831 MLX5_SQC_STATE_RDY = 0x1, 2832 MLX5_SQC_STATE_ERR = 0x3, 2833 }; 2834 2835 struct mlx5_ifc_sqc_bits { 2836 u8 rlky[0x1]; 2837 u8 cd_master[0x1]; 2838 u8 fre[0x1]; 2839 u8 flush_in_error_en[0x1]; 2840 u8 allow_multi_pkt_send_wqe[0x1]; 2841 u8 min_wqe_inline_mode[0x3]; 2842 u8 state[0x4]; 2843 u8 reg_umr[0x1]; 2844 u8 allow_swp[0x1]; 2845 u8 hairpin[0x1]; 2846 u8 reserved_at_f[0x11]; 2847 2848 u8 reserved_at_20[0x8]; 2849 u8 user_index[0x18]; 2850 2851 u8 reserved_at_40[0x8]; 2852 u8 cqn[0x18]; 2853 2854 u8 reserved_at_60[0x8]; 2855 u8 hairpin_peer_rq[0x18]; 2856 2857 u8 reserved_at_80[0x10]; 2858 u8 hairpin_peer_vhca[0x10]; 2859 2860 u8 reserved_at_a0[0x50]; 2861 2862 u8 packet_pacing_rate_limit_index[0x10]; 2863 u8 tis_lst_sz[0x10]; 2864 u8 reserved_at_110[0x10]; 2865 2866 u8 reserved_at_120[0x40]; 2867 2868 u8 reserved_at_160[0x8]; 2869 u8 tis_num_0[0x18]; 2870 2871 struct mlx5_ifc_wq_bits wq; 2872 }; 2873 2874 enum { 2875 SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0, 2876 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1, 2877 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2, 2878 SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3, 2879 }; 2880 2881 struct mlx5_ifc_scheduling_context_bits { 2882 u8 element_type[0x8]; 2883 u8 reserved_at_8[0x18]; 2884 2885 u8 element_attributes[0x20]; 2886 2887 u8 parent_element_id[0x20]; 2888 2889 u8 reserved_at_60[0x40]; 2890 2891 u8 bw_share[0x20]; 2892 2893 u8 max_average_bw[0x20]; 2894 2895 u8 reserved_at_e0[0x120]; 2896 }; 2897 2898 struct mlx5_ifc_rqtc_bits { 2899 u8 reserved_at_0[0xa0]; 2900 2901 u8 reserved_at_a0[0x10]; 2902 u8 rqt_max_size[0x10]; 2903 2904 u8 reserved_at_c0[0x10]; 2905 u8 rqt_actual_size[0x10]; 2906 2907 u8 reserved_at_e0[0x6a0]; 2908 2909 struct mlx5_ifc_rq_num_bits rq_num[0]; 2910 }; 2911 2912 enum { 2913 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0, 2914 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1, 2915 }; 2916 2917 enum { 2918 MLX5_RQC_STATE_RST = 0x0, 2919 MLX5_RQC_STATE_RDY = 0x1, 2920 MLX5_RQC_STATE_ERR = 0x3, 2921 }; 2922 2923 struct mlx5_ifc_rqc_bits { 2924 u8 rlky[0x1]; 2925 u8 delay_drop_en[0x1]; 2926 u8 scatter_fcs[0x1]; 2927 u8 vsd[0x1]; 2928 u8 mem_rq_type[0x4]; 2929 u8 state[0x4]; 2930 u8 reserved_at_c[0x1]; 2931 u8 flush_in_error_en[0x1]; 2932 u8 hairpin[0x1]; 2933 u8 reserved_at_f[0x11]; 2934 2935 u8 reserved_at_20[0x8]; 2936 u8 user_index[0x18]; 2937 2938 u8 reserved_at_40[0x8]; 2939 u8 cqn[0x18]; 2940 2941 u8 counter_set_id[0x8]; 2942 u8 reserved_at_68[0x18]; 2943 2944 u8 reserved_at_80[0x8]; 2945 u8 rmpn[0x18]; 2946 2947 u8 reserved_at_a0[0x8]; 2948 u8 hairpin_peer_sq[0x18]; 2949 2950 u8 reserved_at_c0[0x10]; 2951 u8 hairpin_peer_vhca[0x10]; 2952 2953 u8 reserved_at_e0[0xa0]; 2954 2955 struct mlx5_ifc_wq_bits wq; 2956 }; 2957 2958 enum { 2959 MLX5_RMPC_STATE_RDY = 0x1, 2960 MLX5_RMPC_STATE_ERR = 0x3, 2961 }; 2962 2963 struct mlx5_ifc_rmpc_bits { 2964 u8 reserved_at_0[0x8]; 2965 u8 state[0x4]; 2966 u8 reserved_at_c[0x14]; 2967 2968 u8 basic_cyclic_rcv_wqe[0x1]; 2969 u8 reserved_at_21[0x1f]; 2970 2971 u8 reserved_at_40[0x140]; 2972 2973 struct mlx5_ifc_wq_bits wq; 2974 }; 2975 2976 struct mlx5_ifc_nic_vport_context_bits { 2977 u8 reserved_at_0[0x5]; 2978 u8 min_wqe_inline_mode[0x3]; 2979 u8 reserved_at_8[0x15]; 2980 u8 disable_mc_local_lb[0x1]; 2981 u8 disable_uc_local_lb[0x1]; 2982 u8 roce_en[0x1]; 2983 2984 u8 arm_change_event[0x1]; 2985 u8 reserved_at_21[0x1a]; 2986 u8 event_on_mtu[0x1]; 2987 u8 event_on_promisc_change[0x1]; 2988 u8 event_on_vlan_change[0x1]; 2989 u8 event_on_mc_address_change[0x1]; 2990 u8 event_on_uc_address_change[0x1]; 2991 2992 u8 reserved_at_40[0xc]; 2993 2994 u8 affiliation_criteria[0x4]; 2995 u8 affiliated_vhca_id[0x10]; 2996 2997 u8 reserved_at_60[0xd0]; 2998 2999 u8 mtu[0x10]; 3000 3001 u8 system_image_guid[0x40]; 3002 u8 port_guid[0x40]; 3003 u8 node_guid[0x40]; 3004 3005 u8 reserved_at_200[0x140]; 3006 u8 qkey_violation_counter[0x10]; 3007 u8 reserved_at_350[0x430]; 3008 3009 u8 promisc_uc[0x1]; 3010 u8 promisc_mc[0x1]; 3011 u8 promisc_all[0x1]; 3012 u8 reserved_at_783[0x2]; 3013 u8 allowed_list_type[0x3]; 3014 u8 reserved_at_788[0xc]; 3015 u8 allowed_list_size[0xc]; 3016 3017 struct mlx5_ifc_mac_address_layout_bits permanent_address; 3018 3019 u8 reserved_at_7e0[0x20]; 3020 3021 u8 current_uc_mac_address[0][0x40]; 3022 }; 3023 3024 enum { 3025 MLX5_MKC_ACCESS_MODE_PA = 0x0, 3026 MLX5_MKC_ACCESS_MODE_MTT = 0x1, 3027 MLX5_MKC_ACCESS_MODE_KLMS = 0x2, 3028 MLX5_MKC_ACCESS_MODE_KSM = 0x3, 3029 MLX5_MKC_ACCESS_MODE_SW_ICM = 0x4, 3030 MLX5_MKC_ACCESS_MODE_MEMIC = 0x5, 3031 }; 3032 3033 struct mlx5_ifc_mkc_bits { 3034 u8 reserved_at_0[0x1]; 3035 u8 free[0x1]; 3036 u8 reserved_at_2[0x1]; 3037 u8 access_mode_4_2[0x3]; 3038 u8 reserved_at_6[0x7]; 3039 u8 relaxed_ordering_write[0x1]; 3040 u8 reserved_at_e[0x1]; 3041 u8 small_fence_on_rdma_read_response[0x1]; 3042 u8 umr_en[0x1]; 3043 u8 a[0x1]; 3044 u8 rw[0x1]; 3045 u8 rr[0x1]; 3046 u8 lw[0x1]; 3047 u8 lr[0x1]; 3048 u8 access_mode_1_0[0x2]; 3049 u8 reserved_at_18[0x8]; 3050 3051 u8 qpn[0x18]; 3052 u8 mkey_7_0[0x8]; 3053 3054 u8 reserved_at_40[0x20]; 3055 3056 u8 length64[0x1]; 3057 u8 bsf_en[0x1]; 3058 u8 sync_umr[0x1]; 3059 u8 reserved_at_63[0x2]; 3060 u8 expected_sigerr_count[0x1]; 3061 u8 reserved_at_66[0x1]; 3062 u8 en_rinval[0x1]; 3063 u8 pd[0x18]; 3064 3065 u8 start_addr[0x40]; 3066 3067 u8 len[0x40]; 3068 3069 u8 bsf_octword_size[0x20]; 3070 3071 u8 reserved_at_120[0x80]; 3072 3073 u8 translations_octword_size[0x20]; 3074 3075 u8 reserved_at_1c0[0x1b]; 3076 u8 log_page_size[0x5]; 3077 3078 u8 reserved_at_1e0[0x20]; 3079 }; 3080 3081 struct mlx5_ifc_pkey_bits { 3082 u8 reserved_at_0[0x10]; 3083 u8 pkey[0x10]; 3084 }; 3085 3086 struct mlx5_ifc_array128_auto_bits { 3087 u8 array128_auto[16][0x8]; 3088 }; 3089 3090 struct mlx5_ifc_hca_vport_context_bits { 3091 u8 field_select[0x20]; 3092 3093 u8 reserved_at_20[0xe0]; 3094 3095 u8 sm_virt_aware[0x1]; 3096 u8 has_smi[0x1]; 3097 u8 has_raw[0x1]; 3098 u8 grh_required[0x1]; 3099 u8 reserved_at_104[0xc]; 3100 u8 port_physical_state[0x4]; 3101 u8 vport_state_policy[0x4]; 3102 u8 port_state[0x4]; 3103 u8 vport_state[0x4]; 3104 3105 u8 reserved_at_120[0x20]; 3106 3107 u8 system_image_guid[0x40]; 3108 3109 u8 port_guid[0x40]; 3110 3111 u8 node_guid[0x40]; 3112 3113 u8 cap_mask1[0x20]; 3114 3115 u8 cap_mask1_field_select[0x20]; 3116 3117 u8 cap_mask2[0x20]; 3118 3119 u8 cap_mask2_field_select[0x20]; 3120 3121 u8 reserved_at_280[0x80]; 3122 3123 u8 lid[0x10]; 3124 u8 reserved_at_310[0x4]; 3125 u8 init_type_reply[0x4]; 3126 u8 lmc[0x3]; 3127 u8 subnet_timeout[0x5]; 3128 3129 u8 sm_lid[0x10]; 3130 u8 sm_sl[0x4]; 3131 u8 reserved_at_334[0xc]; 3132 3133 u8 qkey_violation_counter[0x10]; 3134 u8 pkey_violation_counter[0x10]; 3135 3136 u8 reserved_at_360[0xca0]; 3137 }; 3138 3139 struct mlx5_ifc_esw_vport_context_bits { 3140 u8 fdb_to_vport_reg_c[0x1]; 3141 u8 reserved_at_1[0x2]; 3142 u8 vport_svlan_strip[0x1]; 3143 u8 vport_cvlan_strip[0x1]; 3144 u8 vport_svlan_insert[0x1]; 3145 u8 vport_cvlan_insert[0x2]; 3146 u8 fdb_to_vport_reg_c_id[0x8]; 3147 u8 reserved_at_10[0x10]; 3148 3149 u8 reserved_at_20[0x20]; 3150 3151 u8 svlan_cfi[0x1]; 3152 u8 svlan_pcp[0x3]; 3153 u8 svlan_id[0xc]; 3154 u8 cvlan_cfi[0x1]; 3155 u8 cvlan_pcp[0x3]; 3156 u8 cvlan_id[0xc]; 3157 3158 u8 reserved_at_60[0x7a0]; 3159 }; 3160 3161 enum { 3162 MLX5_EQC_STATUS_OK = 0x0, 3163 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa, 3164 }; 3165 3166 enum { 3167 MLX5_EQC_ST_ARMED = 0x9, 3168 MLX5_EQC_ST_FIRED = 0xa, 3169 }; 3170 3171 struct mlx5_ifc_eqc_bits { 3172 u8 status[0x4]; 3173 u8 reserved_at_4[0x9]; 3174 u8 ec[0x1]; 3175 u8 oi[0x1]; 3176 u8 reserved_at_f[0x5]; 3177 u8 st[0x4]; 3178 u8 reserved_at_18[0x8]; 3179 3180 u8 reserved_at_20[0x20]; 3181 3182 u8 reserved_at_40[0x14]; 3183 u8 page_offset[0x6]; 3184 u8 reserved_at_5a[0x6]; 3185 3186 u8 reserved_at_60[0x3]; 3187 u8 log_eq_size[0x5]; 3188 u8 uar_page[0x18]; 3189 3190 u8 reserved_at_80[0x20]; 3191 3192 u8 reserved_at_a0[0x18]; 3193 u8 intr[0x8]; 3194 3195 u8 reserved_at_c0[0x3]; 3196 u8 log_page_size[0x5]; 3197 u8 reserved_at_c8[0x18]; 3198 3199 u8 reserved_at_e0[0x60]; 3200 3201 u8 reserved_at_140[0x8]; 3202 u8 consumer_counter[0x18]; 3203 3204 u8 reserved_at_160[0x8]; 3205 u8 producer_counter[0x18]; 3206 3207 u8 reserved_at_180[0x80]; 3208 }; 3209 3210 enum { 3211 MLX5_DCTC_STATE_ACTIVE = 0x0, 3212 MLX5_DCTC_STATE_DRAINING = 0x1, 3213 MLX5_DCTC_STATE_DRAINED = 0x2, 3214 }; 3215 3216 enum { 3217 MLX5_DCTC_CS_RES_DISABLE = 0x0, 3218 MLX5_DCTC_CS_RES_NA = 0x1, 3219 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2, 3220 }; 3221 3222 enum { 3223 MLX5_DCTC_MTU_256_BYTES = 0x1, 3224 MLX5_DCTC_MTU_512_BYTES = 0x2, 3225 MLX5_DCTC_MTU_1K_BYTES = 0x3, 3226 MLX5_DCTC_MTU_2K_BYTES = 0x4, 3227 MLX5_DCTC_MTU_4K_BYTES = 0x5, 3228 }; 3229 3230 struct mlx5_ifc_dctc_bits { 3231 u8 reserved_at_0[0x4]; 3232 u8 state[0x4]; 3233 u8 reserved_at_8[0x18]; 3234 3235 u8 reserved_at_20[0x8]; 3236 u8 user_index[0x18]; 3237 3238 u8 reserved_at_40[0x8]; 3239 u8 cqn[0x18]; 3240 3241 u8 counter_set_id[0x8]; 3242 u8 atomic_mode[0x4]; 3243 u8 rre[0x1]; 3244 u8 rwe[0x1]; 3245 u8 rae[0x1]; 3246 u8 atomic_like_write_en[0x1]; 3247 u8 latency_sensitive[0x1]; 3248 u8 rlky[0x1]; 3249 u8 free_ar[0x1]; 3250 u8 reserved_at_73[0xd]; 3251 3252 u8 reserved_at_80[0x8]; 3253 u8 cs_res[0x8]; 3254 u8 reserved_at_90[0x3]; 3255 u8 min_rnr_nak[0x5]; 3256 u8 reserved_at_98[0x8]; 3257 3258 u8 reserved_at_a0[0x8]; 3259 u8 srqn_xrqn[0x18]; 3260 3261 u8 reserved_at_c0[0x8]; 3262 u8 pd[0x18]; 3263 3264 u8 tclass[0x8]; 3265 u8 reserved_at_e8[0x4]; 3266 u8 flow_label[0x14]; 3267 3268 u8 dc_access_key[0x40]; 3269 3270 u8 reserved_at_140[0x5]; 3271 u8 mtu[0x3]; 3272 u8 port[0x8]; 3273 u8 pkey_index[0x10]; 3274 3275 u8 reserved_at_160[0x8]; 3276 u8 my_addr_index[0x8]; 3277 u8 reserved_at_170[0x8]; 3278 u8 hop_limit[0x8]; 3279 3280 u8 dc_access_key_violation_count[0x20]; 3281 3282 u8 reserved_at_1a0[0x14]; 3283 u8 dei_cfi[0x1]; 3284 u8 eth_prio[0x3]; 3285 u8 ecn[0x2]; 3286 u8 dscp[0x6]; 3287 3288 u8 reserved_at_1c0[0x40]; 3289 }; 3290 3291 enum { 3292 MLX5_CQC_STATUS_OK = 0x0, 3293 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9, 3294 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa, 3295 }; 3296 3297 enum { 3298 MLX5_CQC_CQE_SZ_64_BYTES = 0x0, 3299 MLX5_CQC_CQE_SZ_128_BYTES = 0x1, 3300 }; 3301 3302 enum { 3303 MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED = 0x6, 3304 MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED = 0x9, 3305 MLX5_CQC_ST_FIRED = 0xa, 3306 }; 3307 3308 enum { 3309 MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0, 3310 MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1, 3311 MLX5_CQ_PERIOD_NUM_MODES 3312 }; 3313 3314 struct mlx5_ifc_cqc_bits { 3315 u8 status[0x4]; 3316 u8 reserved_at_4[0x2]; 3317 u8 dbr_umem_valid[0x1]; 3318 u8 reserved_at_7[0x1]; 3319 u8 cqe_sz[0x3]; 3320 u8 cc[0x1]; 3321 u8 reserved_at_c[0x1]; 3322 u8 scqe_break_moderation_en[0x1]; 3323 u8 oi[0x1]; 3324 u8 cq_period_mode[0x2]; 3325 u8 cqe_comp_en[0x1]; 3326 u8 mini_cqe_res_format[0x2]; 3327 u8 st[0x4]; 3328 u8 reserved_at_18[0x8]; 3329 3330 u8 reserved_at_20[0x20]; 3331 3332 u8 reserved_at_40[0x14]; 3333 u8 page_offset[0x6]; 3334 u8 reserved_at_5a[0x6]; 3335 3336 u8 reserved_at_60[0x3]; 3337 u8 log_cq_size[0x5]; 3338 u8 uar_page[0x18]; 3339 3340 u8 reserved_at_80[0x4]; 3341 u8 cq_period[0xc]; 3342 u8 cq_max_count[0x10]; 3343 3344 u8 reserved_at_a0[0x18]; 3345 u8 c_eqn[0x8]; 3346 3347 u8 reserved_at_c0[0x3]; 3348 u8 log_page_size[0x5]; 3349 u8 reserved_at_c8[0x18]; 3350 3351 u8 reserved_at_e0[0x20]; 3352 3353 u8 reserved_at_100[0x8]; 3354 u8 last_notified_index[0x18]; 3355 3356 u8 reserved_at_120[0x8]; 3357 u8 last_solicit_index[0x18]; 3358 3359 u8 reserved_at_140[0x8]; 3360 u8 consumer_counter[0x18]; 3361 3362 u8 reserved_at_160[0x8]; 3363 u8 producer_counter[0x18]; 3364 3365 u8 reserved_at_180[0x40]; 3366 3367 u8 dbr_addr[0x40]; 3368 }; 3369 3370 union mlx5_ifc_cong_control_roce_ecn_auto_bits { 3371 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp; 3372 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp; 3373 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np; 3374 u8 reserved_at_0[0x800]; 3375 }; 3376 3377 struct mlx5_ifc_query_adapter_param_block_bits { 3378 u8 reserved_at_0[0xc0]; 3379 3380 u8 reserved_at_c0[0x8]; 3381 u8 ieee_vendor_id[0x18]; 3382 3383 u8 reserved_at_e0[0x10]; 3384 u8 vsd_vendor_id[0x10]; 3385 3386 u8 vsd[208][0x8]; 3387 3388 u8 vsd_contd_psid[16][0x8]; 3389 }; 3390 3391 enum { 3392 MLX5_XRQC_STATE_GOOD = 0x0, 3393 MLX5_XRQC_STATE_ERROR = 0x1, 3394 }; 3395 3396 enum { 3397 MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0, 3398 MLX5_XRQC_TOPOLOGY_TAG_MATCHING = 0x1, 3399 }; 3400 3401 enum { 3402 MLX5_XRQC_OFFLOAD_RNDV = 0x1, 3403 }; 3404 3405 struct mlx5_ifc_tag_matching_topology_context_bits { 3406 u8 log_matching_list_sz[0x4]; 3407 u8 reserved_at_4[0xc]; 3408 u8 append_next_index[0x10]; 3409 3410 u8 sw_phase_cnt[0x10]; 3411 u8 hw_phase_cnt[0x10]; 3412 3413 u8 reserved_at_40[0x40]; 3414 }; 3415 3416 struct mlx5_ifc_xrqc_bits { 3417 u8 state[0x4]; 3418 u8 rlkey[0x1]; 3419 u8 reserved_at_5[0xf]; 3420 u8 topology[0x4]; 3421 u8 reserved_at_18[0x4]; 3422 u8 offload[0x4]; 3423 3424 u8 reserved_at_20[0x8]; 3425 u8 user_index[0x18]; 3426 3427 u8 reserved_at_40[0x8]; 3428 u8 cqn[0x18]; 3429 3430 u8 reserved_at_60[0xa0]; 3431 3432 struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context; 3433 3434 u8 reserved_at_180[0x280]; 3435 3436 struct mlx5_ifc_wq_bits wq; 3437 }; 3438 3439 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits { 3440 struct mlx5_ifc_modify_field_select_bits modify_field_select; 3441 struct mlx5_ifc_resize_field_select_bits resize_field_select; 3442 u8 reserved_at_0[0x20]; 3443 }; 3444 3445 union mlx5_ifc_field_select_802_1_r_roce_auto_bits { 3446 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp; 3447 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp; 3448 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np; 3449 u8 reserved_at_0[0x20]; 3450 }; 3451 3452 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits { 3453 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 3454 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 3455 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 3456 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 3457 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 3458 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 3459 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout; 3460 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 3461 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 3462 struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs; 3463 u8 reserved_at_0[0x7c0]; 3464 }; 3465 3466 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits { 3467 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout; 3468 u8 reserved_at_0[0x7c0]; 3469 }; 3470 3471 union mlx5_ifc_event_auto_bits { 3472 struct mlx5_ifc_comp_event_bits comp_event; 3473 struct mlx5_ifc_dct_events_bits dct_events; 3474 struct mlx5_ifc_qp_events_bits qp_events; 3475 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event; 3476 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event; 3477 struct mlx5_ifc_cq_error_bits cq_error; 3478 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged; 3479 struct mlx5_ifc_port_state_change_event_bits port_state_change_event; 3480 struct mlx5_ifc_gpio_event_bits gpio_event; 3481 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event; 3482 struct mlx5_ifc_stall_vl_event_bits stall_vl_event; 3483 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event; 3484 u8 reserved_at_0[0xe0]; 3485 }; 3486 3487 struct mlx5_ifc_health_buffer_bits { 3488 u8 reserved_at_0[0x100]; 3489 3490 u8 assert_existptr[0x20]; 3491 3492 u8 assert_callra[0x20]; 3493 3494 u8 reserved_at_140[0x40]; 3495 3496 u8 fw_version[0x20]; 3497 3498 u8 hw_id[0x20]; 3499 3500 u8 reserved_at_1c0[0x20]; 3501 3502 u8 irisc_index[0x8]; 3503 u8 synd[0x8]; 3504 u8 ext_synd[0x10]; 3505 }; 3506 3507 struct mlx5_ifc_register_loopback_control_bits { 3508 u8 no_lb[0x1]; 3509 u8 reserved_at_1[0x7]; 3510 u8 port[0x8]; 3511 u8 reserved_at_10[0x10]; 3512 3513 u8 reserved_at_20[0x60]; 3514 }; 3515 3516 struct mlx5_ifc_vport_tc_element_bits { 3517 u8 traffic_class[0x4]; 3518 u8 reserved_at_4[0xc]; 3519 u8 vport_number[0x10]; 3520 }; 3521 3522 struct mlx5_ifc_vport_element_bits { 3523 u8 reserved_at_0[0x10]; 3524 u8 vport_number[0x10]; 3525 }; 3526 3527 enum { 3528 TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0, 3529 TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1, 3530 TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2, 3531 }; 3532 3533 struct mlx5_ifc_tsar_element_bits { 3534 u8 reserved_at_0[0x8]; 3535 u8 tsar_type[0x8]; 3536 u8 reserved_at_10[0x10]; 3537 }; 3538 3539 enum { 3540 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0, 3541 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1, 3542 }; 3543 3544 struct mlx5_ifc_teardown_hca_out_bits { 3545 u8 status[0x8]; 3546 u8 reserved_at_8[0x18]; 3547 3548 u8 syndrome[0x20]; 3549 3550 u8 reserved_at_40[0x3f]; 3551 3552 u8 state[0x1]; 3553 }; 3554 3555 enum { 3556 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0, 3557 MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE = 0x1, 3558 MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN = 0x2, 3559 }; 3560 3561 struct mlx5_ifc_teardown_hca_in_bits { 3562 u8 opcode[0x10]; 3563 u8 reserved_at_10[0x10]; 3564 3565 u8 reserved_at_20[0x10]; 3566 u8 op_mod[0x10]; 3567 3568 u8 reserved_at_40[0x10]; 3569 u8 profile[0x10]; 3570 3571 u8 reserved_at_60[0x20]; 3572 }; 3573 3574 struct mlx5_ifc_sqerr2rts_qp_out_bits { 3575 u8 status[0x8]; 3576 u8 reserved_at_8[0x18]; 3577 3578 u8 syndrome[0x20]; 3579 3580 u8 reserved_at_40[0x40]; 3581 }; 3582 3583 struct mlx5_ifc_sqerr2rts_qp_in_bits { 3584 u8 opcode[0x10]; 3585 u8 uid[0x10]; 3586 3587 u8 reserved_at_20[0x10]; 3588 u8 op_mod[0x10]; 3589 3590 u8 reserved_at_40[0x8]; 3591 u8 qpn[0x18]; 3592 3593 u8 reserved_at_60[0x20]; 3594 3595 u8 opt_param_mask[0x20]; 3596 3597 u8 reserved_at_a0[0x20]; 3598 3599 struct mlx5_ifc_qpc_bits qpc; 3600 3601 u8 reserved_at_800[0x80]; 3602 }; 3603 3604 struct mlx5_ifc_sqd2rts_qp_out_bits { 3605 u8 status[0x8]; 3606 u8 reserved_at_8[0x18]; 3607 3608 u8 syndrome[0x20]; 3609 3610 u8 reserved_at_40[0x40]; 3611 }; 3612 3613 struct mlx5_ifc_sqd2rts_qp_in_bits { 3614 u8 opcode[0x10]; 3615 u8 uid[0x10]; 3616 3617 u8 reserved_at_20[0x10]; 3618 u8 op_mod[0x10]; 3619 3620 u8 reserved_at_40[0x8]; 3621 u8 qpn[0x18]; 3622 3623 u8 reserved_at_60[0x20]; 3624 3625 u8 opt_param_mask[0x20]; 3626 3627 u8 reserved_at_a0[0x20]; 3628 3629 struct mlx5_ifc_qpc_bits qpc; 3630 3631 u8 reserved_at_800[0x80]; 3632 }; 3633 3634 struct mlx5_ifc_set_roce_address_out_bits { 3635 u8 status[0x8]; 3636 u8 reserved_at_8[0x18]; 3637 3638 u8 syndrome[0x20]; 3639 3640 u8 reserved_at_40[0x40]; 3641 }; 3642 3643 struct mlx5_ifc_set_roce_address_in_bits { 3644 u8 opcode[0x10]; 3645 u8 reserved_at_10[0x10]; 3646 3647 u8 reserved_at_20[0x10]; 3648 u8 op_mod[0x10]; 3649 3650 u8 roce_address_index[0x10]; 3651 u8 reserved_at_50[0xc]; 3652 u8 vhca_port_num[0x4]; 3653 3654 u8 reserved_at_60[0x20]; 3655 3656 struct mlx5_ifc_roce_addr_layout_bits roce_address; 3657 }; 3658 3659 struct mlx5_ifc_set_mad_demux_out_bits { 3660 u8 status[0x8]; 3661 u8 reserved_at_8[0x18]; 3662 3663 u8 syndrome[0x20]; 3664 3665 u8 reserved_at_40[0x40]; 3666 }; 3667 3668 enum { 3669 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0, 3670 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2, 3671 }; 3672 3673 struct mlx5_ifc_set_mad_demux_in_bits { 3674 u8 opcode[0x10]; 3675 u8 reserved_at_10[0x10]; 3676 3677 u8 reserved_at_20[0x10]; 3678 u8 op_mod[0x10]; 3679 3680 u8 reserved_at_40[0x20]; 3681 3682 u8 reserved_at_60[0x6]; 3683 u8 demux_mode[0x2]; 3684 u8 reserved_at_68[0x18]; 3685 }; 3686 3687 struct mlx5_ifc_set_l2_table_entry_out_bits { 3688 u8 status[0x8]; 3689 u8 reserved_at_8[0x18]; 3690 3691 u8 syndrome[0x20]; 3692 3693 u8 reserved_at_40[0x40]; 3694 }; 3695 3696 struct mlx5_ifc_set_l2_table_entry_in_bits { 3697 u8 opcode[0x10]; 3698 u8 reserved_at_10[0x10]; 3699 3700 u8 reserved_at_20[0x10]; 3701 u8 op_mod[0x10]; 3702 3703 u8 reserved_at_40[0x60]; 3704 3705 u8 reserved_at_a0[0x8]; 3706 u8 table_index[0x18]; 3707 3708 u8 reserved_at_c0[0x20]; 3709 3710 u8 reserved_at_e0[0x13]; 3711 u8 vlan_valid[0x1]; 3712 u8 vlan[0xc]; 3713 3714 struct mlx5_ifc_mac_address_layout_bits mac_address; 3715 3716 u8 reserved_at_140[0xc0]; 3717 }; 3718 3719 struct mlx5_ifc_set_issi_out_bits { 3720 u8 status[0x8]; 3721 u8 reserved_at_8[0x18]; 3722 3723 u8 syndrome[0x20]; 3724 3725 u8 reserved_at_40[0x40]; 3726 }; 3727 3728 struct mlx5_ifc_set_issi_in_bits { 3729 u8 opcode[0x10]; 3730 u8 reserved_at_10[0x10]; 3731 3732 u8 reserved_at_20[0x10]; 3733 u8 op_mod[0x10]; 3734 3735 u8 reserved_at_40[0x10]; 3736 u8 current_issi[0x10]; 3737 3738 u8 reserved_at_60[0x20]; 3739 }; 3740 3741 struct mlx5_ifc_set_hca_cap_out_bits { 3742 u8 status[0x8]; 3743 u8 reserved_at_8[0x18]; 3744 3745 u8 syndrome[0x20]; 3746 3747 u8 reserved_at_40[0x40]; 3748 }; 3749 3750 struct mlx5_ifc_set_hca_cap_in_bits { 3751 u8 opcode[0x10]; 3752 u8 reserved_at_10[0x10]; 3753 3754 u8 reserved_at_20[0x10]; 3755 u8 op_mod[0x10]; 3756 3757 u8 reserved_at_40[0x40]; 3758 3759 union mlx5_ifc_hca_cap_union_bits capability; 3760 }; 3761 3762 enum { 3763 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0, 3764 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1, 3765 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2, 3766 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3 3767 }; 3768 3769 struct mlx5_ifc_set_fte_out_bits { 3770 u8 status[0x8]; 3771 u8 reserved_at_8[0x18]; 3772 3773 u8 syndrome[0x20]; 3774 3775 u8 reserved_at_40[0x40]; 3776 }; 3777 3778 struct mlx5_ifc_set_fte_in_bits { 3779 u8 opcode[0x10]; 3780 u8 reserved_at_10[0x10]; 3781 3782 u8 reserved_at_20[0x10]; 3783 u8 op_mod[0x10]; 3784 3785 u8 other_vport[0x1]; 3786 u8 reserved_at_41[0xf]; 3787 u8 vport_number[0x10]; 3788 3789 u8 reserved_at_60[0x20]; 3790 3791 u8 table_type[0x8]; 3792 u8 reserved_at_88[0x18]; 3793 3794 u8 reserved_at_a0[0x8]; 3795 u8 table_id[0x18]; 3796 3797 u8 reserved_at_c0[0x18]; 3798 u8 modify_enable_mask[0x8]; 3799 3800 u8 reserved_at_e0[0x20]; 3801 3802 u8 flow_index[0x20]; 3803 3804 u8 reserved_at_120[0xe0]; 3805 3806 struct mlx5_ifc_flow_context_bits flow_context; 3807 }; 3808 3809 struct mlx5_ifc_rts2rts_qp_out_bits { 3810 u8 status[0x8]; 3811 u8 reserved_at_8[0x18]; 3812 3813 u8 syndrome[0x20]; 3814 3815 u8 reserved_at_40[0x40]; 3816 }; 3817 3818 struct mlx5_ifc_rts2rts_qp_in_bits { 3819 u8 opcode[0x10]; 3820 u8 uid[0x10]; 3821 3822 u8 reserved_at_20[0x10]; 3823 u8 op_mod[0x10]; 3824 3825 u8 reserved_at_40[0x8]; 3826 u8 qpn[0x18]; 3827 3828 u8 reserved_at_60[0x20]; 3829 3830 u8 opt_param_mask[0x20]; 3831 3832 u8 reserved_at_a0[0x20]; 3833 3834 struct mlx5_ifc_qpc_bits qpc; 3835 3836 u8 reserved_at_800[0x80]; 3837 }; 3838 3839 struct mlx5_ifc_rtr2rts_qp_out_bits { 3840 u8 status[0x8]; 3841 u8 reserved_at_8[0x18]; 3842 3843 u8 syndrome[0x20]; 3844 3845 u8 reserved_at_40[0x40]; 3846 }; 3847 3848 struct mlx5_ifc_rtr2rts_qp_in_bits { 3849 u8 opcode[0x10]; 3850 u8 uid[0x10]; 3851 3852 u8 reserved_at_20[0x10]; 3853 u8 op_mod[0x10]; 3854 3855 u8 reserved_at_40[0x8]; 3856 u8 qpn[0x18]; 3857 3858 u8 reserved_at_60[0x20]; 3859 3860 u8 opt_param_mask[0x20]; 3861 3862 u8 reserved_at_a0[0x20]; 3863 3864 struct mlx5_ifc_qpc_bits qpc; 3865 3866 u8 reserved_at_800[0x80]; 3867 }; 3868 3869 struct mlx5_ifc_rst2init_qp_out_bits { 3870 u8 status[0x8]; 3871 u8 reserved_at_8[0x18]; 3872 3873 u8 syndrome[0x20]; 3874 3875 u8 reserved_at_40[0x40]; 3876 }; 3877 3878 struct mlx5_ifc_rst2init_qp_in_bits { 3879 u8 opcode[0x10]; 3880 u8 uid[0x10]; 3881 3882 u8 reserved_at_20[0x10]; 3883 u8 op_mod[0x10]; 3884 3885 u8 reserved_at_40[0x8]; 3886 u8 qpn[0x18]; 3887 3888 u8 reserved_at_60[0x20]; 3889 3890 u8 opt_param_mask[0x20]; 3891 3892 u8 reserved_at_a0[0x20]; 3893 3894 struct mlx5_ifc_qpc_bits qpc; 3895 3896 u8 reserved_at_800[0x80]; 3897 }; 3898 3899 struct mlx5_ifc_query_xrq_out_bits { 3900 u8 status[0x8]; 3901 u8 reserved_at_8[0x18]; 3902 3903 u8 syndrome[0x20]; 3904 3905 u8 reserved_at_40[0x40]; 3906 3907 struct mlx5_ifc_xrqc_bits xrq_context; 3908 }; 3909 3910 struct mlx5_ifc_query_xrq_in_bits { 3911 u8 opcode[0x10]; 3912 u8 reserved_at_10[0x10]; 3913 3914 u8 reserved_at_20[0x10]; 3915 u8 op_mod[0x10]; 3916 3917 u8 reserved_at_40[0x8]; 3918 u8 xrqn[0x18]; 3919 3920 u8 reserved_at_60[0x20]; 3921 }; 3922 3923 struct mlx5_ifc_query_xrc_srq_out_bits { 3924 u8 status[0x8]; 3925 u8 reserved_at_8[0x18]; 3926 3927 u8 syndrome[0x20]; 3928 3929 u8 reserved_at_40[0x40]; 3930 3931 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 3932 3933 u8 reserved_at_280[0x600]; 3934 3935 u8 pas[0][0x40]; 3936 }; 3937 3938 struct mlx5_ifc_query_xrc_srq_in_bits { 3939 u8 opcode[0x10]; 3940 u8 reserved_at_10[0x10]; 3941 3942 u8 reserved_at_20[0x10]; 3943 u8 op_mod[0x10]; 3944 3945 u8 reserved_at_40[0x8]; 3946 u8 xrc_srqn[0x18]; 3947 3948 u8 reserved_at_60[0x20]; 3949 }; 3950 3951 enum { 3952 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0, 3953 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1, 3954 }; 3955 3956 struct mlx5_ifc_query_vport_state_out_bits { 3957 u8 status[0x8]; 3958 u8 reserved_at_8[0x18]; 3959 3960 u8 syndrome[0x20]; 3961 3962 u8 reserved_at_40[0x20]; 3963 3964 u8 reserved_at_60[0x18]; 3965 u8 admin_state[0x4]; 3966 u8 state[0x4]; 3967 }; 3968 3969 enum { 3970 MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT = 0x0, 3971 MLX5_VPORT_STATE_OP_MOD_ESW_VPORT = 0x1, 3972 }; 3973 3974 struct mlx5_ifc_arm_monitor_counter_in_bits { 3975 u8 opcode[0x10]; 3976 u8 uid[0x10]; 3977 3978 u8 reserved_at_20[0x10]; 3979 u8 op_mod[0x10]; 3980 3981 u8 reserved_at_40[0x20]; 3982 3983 u8 reserved_at_60[0x20]; 3984 }; 3985 3986 struct mlx5_ifc_arm_monitor_counter_out_bits { 3987 u8 status[0x8]; 3988 u8 reserved_at_8[0x18]; 3989 3990 u8 syndrome[0x20]; 3991 3992 u8 reserved_at_40[0x40]; 3993 }; 3994 3995 enum { 3996 MLX5_QUERY_MONITOR_CNT_TYPE_PPCNT = 0x0, 3997 MLX5_QUERY_MONITOR_CNT_TYPE_Q_COUNTER = 0x1, 3998 }; 3999 4000 enum mlx5_monitor_counter_ppcnt { 4001 MLX5_QUERY_MONITOR_PPCNT_IN_RANGE_LENGTH_ERRORS = 0x0, 4002 MLX5_QUERY_MONITOR_PPCNT_OUT_OF_RANGE_LENGTH_FIELD = 0x1, 4003 MLX5_QUERY_MONITOR_PPCNT_FRAME_TOO_LONG_ERRORS = 0x2, 4004 MLX5_QUERY_MONITOR_PPCNT_FRAME_CHECK_SEQUENCE_ERRORS = 0x3, 4005 MLX5_QUERY_MONITOR_PPCNT_ALIGNMENT_ERRORS = 0x4, 4006 MLX5_QUERY_MONITOR_PPCNT_IF_OUT_DISCARDS = 0x5, 4007 }; 4008 4009 enum { 4010 MLX5_QUERY_MONITOR_Q_COUNTER_RX_OUT_OF_BUFFER = 0x4, 4011 }; 4012 4013 struct mlx5_ifc_monitor_counter_output_bits { 4014 u8 reserved_at_0[0x4]; 4015 u8 type[0x4]; 4016 u8 reserved_at_8[0x8]; 4017 u8 counter[0x10]; 4018 4019 u8 counter_group_id[0x20]; 4020 }; 4021 4022 #define MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 (6) 4023 #define MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1 (1) 4024 #define MLX5_CMD_SET_MONITOR_NUM_COUNTER (MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 +\ 4025 MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1) 4026 4027 struct mlx5_ifc_set_monitor_counter_in_bits { 4028 u8 opcode[0x10]; 4029 u8 uid[0x10]; 4030 4031 u8 reserved_at_20[0x10]; 4032 u8 op_mod[0x10]; 4033 4034 u8 reserved_at_40[0x10]; 4035 u8 num_of_counters[0x10]; 4036 4037 u8 reserved_at_60[0x20]; 4038 4039 struct mlx5_ifc_monitor_counter_output_bits monitor_counter[MLX5_CMD_SET_MONITOR_NUM_COUNTER]; 4040 }; 4041 4042 struct mlx5_ifc_set_monitor_counter_out_bits { 4043 u8 status[0x8]; 4044 u8 reserved_at_8[0x18]; 4045 4046 u8 syndrome[0x20]; 4047 4048 u8 reserved_at_40[0x40]; 4049 }; 4050 4051 struct mlx5_ifc_query_vport_state_in_bits { 4052 u8 opcode[0x10]; 4053 u8 reserved_at_10[0x10]; 4054 4055 u8 reserved_at_20[0x10]; 4056 u8 op_mod[0x10]; 4057 4058 u8 other_vport[0x1]; 4059 u8 reserved_at_41[0xf]; 4060 u8 vport_number[0x10]; 4061 4062 u8 reserved_at_60[0x20]; 4063 }; 4064 4065 struct mlx5_ifc_query_vnic_env_out_bits { 4066 u8 status[0x8]; 4067 u8 reserved_at_8[0x18]; 4068 4069 u8 syndrome[0x20]; 4070 4071 u8 reserved_at_40[0x40]; 4072 4073 struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env; 4074 }; 4075 4076 enum { 4077 MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS = 0x0, 4078 }; 4079 4080 struct mlx5_ifc_query_vnic_env_in_bits { 4081 u8 opcode[0x10]; 4082 u8 reserved_at_10[0x10]; 4083 4084 u8 reserved_at_20[0x10]; 4085 u8 op_mod[0x10]; 4086 4087 u8 other_vport[0x1]; 4088 u8 reserved_at_41[0xf]; 4089 u8 vport_number[0x10]; 4090 4091 u8 reserved_at_60[0x20]; 4092 }; 4093 4094 struct mlx5_ifc_query_vport_counter_out_bits { 4095 u8 status[0x8]; 4096 u8 reserved_at_8[0x18]; 4097 4098 u8 syndrome[0x20]; 4099 4100 u8 reserved_at_40[0x40]; 4101 4102 struct mlx5_ifc_traffic_counter_bits received_errors; 4103 4104 struct mlx5_ifc_traffic_counter_bits transmit_errors; 4105 4106 struct mlx5_ifc_traffic_counter_bits received_ib_unicast; 4107 4108 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast; 4109 4110 struct mlx5_ifc_traffic_counter_bits received_ib_multicast; 4111 4112 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast; 4113 4114 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast; 4115 4116 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast; 4117 4118 struct mlx5_ifc_traffic_counter_bits received_eth_unicast; 4119 4120 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast; 4121 4122 struct mlx5_ifc_traffic_counter_bits received_eth_multicast; 4123 4124 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast; 4125 4126 u8 reserved_at_680[0xa00]; 4127 }; 4128 4129 enum { 4130 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0, 4131 }; 4132 4133 struct mlx5_ifc_query_vport_counter_in_bits { 4134 u8 opcode[0x10]; 4135 u8 reserved_at_10[0x10]; 4136 4137 u8 reserved_at_20[0x10]; 4138 u8 op_mod[0x10]; 4139 4140 u8 other_vport[0x1]; 4141 u8 reserved_at_41[0xb]; 4142 u8 port_num[0x4]; 4143 u8 vport_number[0x10]; 4144 4145 u8 reserved_at_60[0x60]; 4146 4147 u8 clear[0x1]; 4148 u8 reserved_at_c1[0x1f]; 4149 4150 u8 reserved_at_e0[0x20]; 4151 }; 4152 4153 struct mlx5_ifc_query_tis_out_bits { 4154 u8 status[0x8]; 4155 u8 reserved_at_8[0x18]; 4156 4157 u8 syndrome[0x20]; 4158 4159 u8 reserved_at_40[0x40]; 4160 4161 struct mlx5_ifc_tisc_bits tis_context; 4162 }; 4163 4164 struct mlx5_ifc_query_tis_in_bits { 4165 u8 opcode[0x10]; 4166 u8 reserved_at_10[0x10]; 4167 4168 u8 reserved_at_20[0x10]; 4169 u8 op_mod[0x10]; 4170 4171 u8 reserved_at_40[0x8]; 4172 u8 tisn[0x18]; 4173 4174 u8 reserved_at_60[0x20]; 4175 }; 4176 4177 struct mlx5_ifc_query_tir_out_bits { 4178 u8 status[0x8]; 4179 u8 reserved_at_8[0x18]; 4180 4181 u8 syndrome[0x20]; 4182 4183 u8 reserved_at_40[0xc0]; 4184 4185 struct mlx5_ifc_tirc_bits tir_context; 4186 }; 4187 4188 struct mlx5_ifc_query_tir_in_bits { 4189 u8 opcode[0x10]; 4190 u8 reserved_at_10[0x10]; 4191 4192 u8 reserved_at_20[0x10]; 4193 u8 op_mod[0x10]; 4194 4195 u8 reserved_at_40[0x8]; 4196 u8 tirn[0x18]; 4197 4198 u8 reserved_at_60[0x20]; 4199 }; 4200 4201 struct mlx5_ifc_query_srq_out_bits { 4202 u8 status[0x8]; 4203 u8 reserved_at_8[0x18]; 4204 4205 u8 syndrome[0x20]; 4206 4207 u8 reserved_at_40[0x40]; 4208 4209 struct mlx5_ifc_srqc_bits srq_context_entry; 4210 4211 u8 reserved_at_280[0x600]; 4212 4213 u8 pas[0][0x40]; 4214 }; 4215 4216 struct mlx5_ifc_query_srq_in_bits { 4217 u8 opcode[0x10]; 4218 u8 reserved_at_10[0x10]; 4219 4220 u8 reserved_at_20[0x10]; 4221 u8 op_mod[0x10]; 4222 4223 u8 reserved_at_40[0x8]; 4224 u8 srqn[0x18]; 4225 4226 u8 reserved_at_60[0x20]; 4227 }; 4228 4229 struct mlx5_ifc_query_sq_out_bits { 4230 u8 status[0x8]; 4231 u8 reserved_at_8[0x18]; 4232 4233 u8 syndrome[0x20]; 4234 4235 u8 reserved_at_40[0xc0]; 4236 4237 struct mlx5_ifc_sqc_bits sq_context; 4238 }; 4239 4240 struct mlx5_ifc_query_sq_in_bits { 4241 u8 opcode[0x10]; 4242 u8 reserved_at_10[0x10]; 4243 4244 u8 reserved_at_20[0x10]; 4245 u8 op_mod[0x10]; 4246 4247 u8 reserved_at_40[0x8]; 4248 u8 sqn[0x18]; 4249 4250 u8 reserved_at_60[0x20]; 4251 }; 4252 4253 struct mlx5_ifc_query_special_contexts_out_bits { 4254 u8 status[0x8]; 4255 u8 reserved_at_8[0x18]; 4256 4257 u8 syndrome[0x20]; 4258 4259 u8 dump_fill_mkey[0x20]; 4260 4261 u8 resd_lkey[0x20]; 4262 4263 u8 null_mkey[0x20]; 4264 4265 u8 reserved_at_a0[0x60]; 4266 }; 4267 4268 struct mlx5_ifc_query_special_contexts_in_bits { 4269 u8 opcode[0x10]; 4270 u8 reserved_at_10[0x10]; 4271 4272 u8 reserved_at_20[0x10]; 4273 u8 op_mod[0x10]; 4274 4275 u8 reserved_at_40[0x40]; 4276 }; 4277 4278 struct mlx5_ifc_query_scheduling_element_out_bits { 4279 u8 opcode[0x10]; 4280 u8 reserved_at_10[0x10]; 4281 4282 u8 reserved_at_20[0x10]; 4283 u8 op_mod[0x10]; 4284 4285 u8 reserved_at_40[0xc0]; 4286 4287 struct mlx5_ifc_scheduling_context_bits scheduling_context; 4288 4289 u8 reserved_at_300[0x100]; 4290 }; 4291 4292 enum { 4293 SCHEDULING_HIERARCHY_E_SWITCH = 0x2, 4294 }; 4295 4296 struct mlx5_ifc_query_scheduling_element_in_bits { 4297 u8 opcode[0x10]; 4298 u8 reserved_at_10[0x10]; 4299 4300 u8 reserved_at_20[0x10]; 4301 u8 op_mod[0x10]; 4302 4303 u8 scheduling_hierarchy[0x8]; 4304 u8 reserved_at_48[0x18]; 4305 4306 u8 scheduling_element_id[0x20]; 4307 4308 u8 reserved_at_80[0x180]; 4309 }; 4310 4311 struct mlx5_ifc_query_rqt_out_bits { 4312 u8 status[0x8]; 4313 u8 reserved_at_8[0x18]; 4314 4315 u8 syndrome[0x20]; 4316 4317 u8 reserved_at_40[0xc0]; 4318 4319 struct mlx5_ifc_rqtc_bits rqt_context; 4320 }; 4321 4322 struct mlx5_ifc_query_rqt_in_bits { 4323 u8 opcode[0x10]; 4324 u8 reserved_at_10[0x10]; 4325 4326 u8 reserved_at_20[0x10]; 4327 u8 op_mod[0x10]; 4328 4329 u8 reserved_at_40[0x8]; 4330 u8 rqtn[0x18]; 4331 4332 u8 reserved_at_60[0x20]; 4333 }; 4334 4335 struct mlx5_ifc_query_rq_out_bits { 4336 u8 status[0x8]; 4337 u8 reserved_at_8[0x18]; 4338 4339 u8 syndrome[0x20]; 4340 4341 u8 reserved_at_40[0xc0]; 4342 4343 struct mlx5_ifc_rqc_bits rq_context; 4344 }; 4345 4346 struct mlx5_ifc_query_rq_in_bits { 4347 u8 opcode[0x10]; 4348 u8 reserved_at_10[0x10]; 4349 4350 u8 reserved_at_20[0x10]; 4351 u8 op_mod[0x10]; 4352 4353 u8 reserved_at_40[0x8]; 4354 u8 rqn[0x18]; 4355 4356 u8 reserved_at_60[0x20]; 4357 }; 4358 4359 struct mlx5_ifc_query_roce_address_out_bits { 4360 u8 status[0x8]; 4361 u8 reserved_at_8[0x18]; 4362 4363 u8 syndrome[0x20]; 4364 4365 u8 reserved_at_40[0x40]; 4366 4367 struct mlx5_ifc_roce_addr_layout_bits roce_address; 4368 }; 4369 4370 struct mlx5_ifc_query_roce_address_in_bits { 4371 u8 opcode[0x10]; 4372 u8 reserved_at_10[0x10]; 4373 4374 u8 reserved_at_20[0x10]; 4375 u8 op_mod[0x10]; 4376 4377 u8 roce_address_index[0x10]; 4378 u8 reserved_at_50[0xc]; 4379 u8 vhca_port_num[0x4]; 4380 4381 u8 reserved_at_60[0x20]; 4382 }; 4383 4384 struct mlx5_ifc_query_rmp_out_bits { 4385 u8 status[0x8]; 4386 u8 reserved_at_8[0x18]; 4387 4388 u8 syndrome[0x20]; 4389 4390 u8 reserved_at_40[0xc0]; 4391 4392 struct mlx5_ifc_rmpc_bits rmp_context; 4393 }; 4394 4395 struct mlx5_ifc_query_rmp_in_bits { 4396 u8 opcode[0x10]; 4397 u8 reserved_at_10[0x10]; 4398 4399 u8 reserved_at_20[0x10]; 4400 u8 op_mod[0x10]; 4401 4402 u8 reserved_at_40[0x8]; 4403 u8 rmpn[0x18]; 4404 4405 u8 reserved_at_60[0x20]; 4406 }; 4407 4408 struct mlx5_ifc_query_qp_out_bits { 4409 u8 status[0x8]; 4410 u8 reserved_at_8[0x18]; 4411 4412 u8 syndrome[0x20]; 4413 4414 u8 reserved_at_40[0x40]; 4415 4416 u8 opt_param_mask[0x20]; 4417 4418 u8 reserved_at_a0[0x20]; 4419 4420 struct mlx5_ifc_qpc_bits qpc; 4421 4422 u8 reserved_at_800[0x80]; 4423 4424 u8 pas[0][0x40]; 4425 }; 4426 4427 struct mlx5_ifc_query_qp_in_bits { 4428 u8 opcode[0x10]; 4429 u8 reserved_at_10[0x10]; 4430 4431 u8 reserved_at_20[0x10]; 4432 u8 op_mod[0x10]; 4433 4434 u8 reserved_at_40[0x8]; 4435 u8 qpn[0x18]; 4436 4437 u8 reserved_at_60[0x20]; 4438 }; 4439 4440 struct mlx5_ifc_query_q_counter_out_bits { 4441 u8 status[0x8]; 4442 u8 reserved_at_8[0x18]; 4443 4444 u8 syndrome[0x20]; 4445 4446 u8 reserved_at_40[0x40]; 4447 4448 u8 rx_write_requests[0x20]; 4449 4450 u8 reserved_at_a0[0x20]; 4451 4452 u8 rx_read_requests[0x20]; 4453 4454 u8 reserved_at_e0[0x20]; 4455 4456 u8 rx_atomic_requests[0x20]; 4457 4458 u8 reserved_at_120[0x20]; 4459 4460 u8 rx_dct_connect[0x20]; 4461 4462 u8 reserved_at_160[0x20]; 4463 4464 u8 out_of_buffer[0x20]; 4465 4466 u8 reserved_at_1a0[0x20]; 4467 4468 u8 out_of_sequence[0x20]; 4469 4470 u8 reserved_at_1e0[0x20]; 4471 4472 u8 duplicate_request[0x20]; 4473 4474 u8 reserved_at_220[0x20]; 4475 4476 u8 rnr_nak_retry_err[0x20]; 4477 4478 u8 reserved_at_260[0x20]; 4479 4480 u8 packet_seq_err[0x20]; 4481 4482 u8 reserved_at_2a0[0x20]; 4483 4484 u8 implied_nak_seq_err[0x20]; 4485 4486 u8 reserved_at_2e0[0x20]; 4487 4488 u8 local_ack_timeout_err[0x20]; 4489 4490 u8 reserved_at_320[0xa0]; 4491 4492 u8 resp_local_length_error[0x20]; 4493 4494 u8 req_local_length_error[0x20]; 4495 4496 u8 resp_local_qp_error[0x20]; 4497 4498 u8 local_operation_error[0x20]; 4499 4500 u8 resp_local_protection[0x20]; 4501 4502 u8 req_local_protection[0x20]; 4503 4504 u8 resp_cqe_error[0x20]; 4505 4506 u8 req_cqe_error[0x20]; 4507 4508 u8 req_mw_binding[0x20]; 4509 4510 u8 req_bad_response[0x20]; 4511 4512 u8 req_remote_invalid_request[0x20]; 4513 4514 u8 resp_remote_invalid_request[0x20]; 4515 4516 u8 req_remote_access_errors[0x20]; 4517 4518 u8 resp_remote_access_errors[0x20]; 4519 4520 u8 req_remote_operation_errors[0x20]; 4521 4522 u8 req_transport_retries_exceeded[0x20]; 4523 4524 u8 cq_overflow[0x20]; 4525 4526 u8 resp_cqe_flush_error[0x20]; 4527 4528 u8 req_cqe_flush_error[0x20]; 4529 4530 u8 reserved_at_620[0x1e0]; 4531 }; 4532 4533 struct mlx5_ifc_query_q_counter_in_bits { 4534 u8 opcode[0x10]; 4535 u8 reserved_at_10[0x10]; 4536 4537 u8 reserved_at_20[0x10]; 4538 u8 op_mod[0x10]; 4539 4540 u8 reserved_at_40[0x80]; 4541 4542 u8 clear[0x1]; 4543 u8 reserved_at_c1[0x1f]; 4544 4545 u8 reserved_at_e0[0x18]; 4546 u8 counter_set_id[0x8]; 4547 }; 4548 4549 struct mlx5_ifc_query_pages_out_bits { 4550 u8 status[0x8]; 4551 u8 reserved_at_8[0x18]; 4552 4553 u8 syndrome[0x20]; 4554 4555 u8 embedded_cpu_function[0x1]; 4556 u8 reserved_at_41[0xf]; 4557 u8 function_id[0x10]; 4558 4559 u8 num_pages[0x20]; 4560 }; 4561 4562 enum { 4563 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1, 4564 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2, 4565 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3, 4566 }; 4567 4568 struct mlx5_ifc_query_pages_in_bits { 4569 u8 opcode[0x10]; 4570 u8 reserved_at_10[0x10]; 4571 4572 u8 reserved_at_20[0x10]; 4573 u8 op_mod[0x10]; 4574 4575 u8 embedded_cpu_function[0x1]; 4576 u8 reserved_at_41[0xf]; 4577 u8 function_id[0x10]; 4578 4579 u8 reserved_at_60[0x20]; 4580 }; 4581 4582 struct mlx5_ifc_query_nic_vport_context_out_bits { 4583 u8 status[0x8]; 4584 u8 reserved_at_8[0x18]; 4585 4586 u8 syndrome[0x20]; 4587 4588 u8 reserved_at_40[0x40]; 4589 4590 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 4591 }; 4592 4593 struct mlx5_ifc_query_nic_vport_context_in_bits { 4594 u8 opcode[0x10]; 4595 u8 reserved_at_10[0x10]; 4596 4597 u8 reserved_at_20[0x10]; 4598 u8 op_mod[0x10]; 4599 4600 u8 other_vport[0x1]; 4601 u8 reserved_at_41[0xf]; 4602 u8 vport_number[0x10]; 4603 4604 u8 reserved_at_60[0x5]; 4605 u8 allowed_list_type[0x3]; 4606 u8 reserved_at_68[0x18]; 4607 }; 4608 4609 struct mlx5_ifc_query_mkey_out_bits { 4610 u8 status[0x8]; 4611 u8 reserved_at_8[0x18]; 4612 4613 u8 syndrome[0x20]; 4614 4615 u8 reserved_at_40[0x40]; 4616 4617 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 4618 4619 u8 reserved_at_280[0x600]; 4620 4621 u8 bsf0_klm0_pas_mtt0_1[16][0x8]; 4622 4623 u8 bsf1_klm1_pas_mtt2_3[16][0x8]; 4624 }; 4625 4626 struct mlx5_ifc_query_mkey_in_bits { 4627 u8 opcode[0x10]; 4628 u8 reserved_at_10[0x10]; 4629 4630 u8 reserved_at_20[0x10]; 4631 u8 op_mod[0x10]; 4632 4633 u8 reserved_at_40[0x8]; 4634 u8 mkey_index[0x18]; 4635 4636 u8 pg_access[0x1]; 4637 u8 reserved_at_61[0x1f]; 4638 }; 4639 4640 struct mlx5_ifc_query_mad_demux_out_bits { 4641 u8 status[0x8]; 4642 u8 reserved_at_8[0x18]; 4643 4644 u8 syndrome[0x20]; 4645 4646 u8 reserved_at_40[0x40]; 4647 4648 u8 mad_dumux_parameters_block[0x20]; 4649 }; 4650 4651 struct mlx5_ifc_query_mad_demux_in_bits { 4652 u8 opcode[0x10]; 4653 u8 reserved_at_10[0x10]; 4654 4655 u8 reserved_at_20[0x10]; 4656 u8 op_mod[0x10]; 4657 4658 u8 reserved_at_40[0x40]; 4659 }; 4660 4661 struct mlx5_ifc_query_l2_table_entry_out_bits { 4662 u8 status[0x8]; 4663 u8 reserved_at_8[0x18]; 4664 4665 u8 syndrome[0x20]; 4666 4667 u8 reserved_at_40[0xa0]; 4668 4669 u8 reserved_at_e0[0x13]; 4670 u8 vlan_valid[0x1]; 4671 u8 vlan[0xc]; 4672 4673 struct mlx5_ifc_mac_address_layout_bits mac_address; 4674 4675 u8 reserved_at_140[0xc0]; 4676 }; 4677 4678 struct mlx5_ifc_query_l2_table_entry_in_bits { 4679 u8 opcode[0x10]; 4680 u8 reserved_at_10[0x10]; 4681 4682 u8 reserved_at_20[0x10]; 4683 u8 op_mod[0x10]; 4684 4685 u8 reserved_at_40[0x60]; 4686 4687 u8 reserved_at_a0[0x8]; 4688 u8 table_index[0x18]; 4689 4690 u8 reserved_at_c0[0x140]; 4691 }; 4692 4693 struct mlx5_ifc_query_issi_out_bits { 4694 u8 status[0x8]; 4695 u8 reserved_at_8[0x18]; 4696 4697 u8 syndrome[0x20]; 4698 4699 u8 reserved_at_40[0x10]; 4700 u8 current_issi[0x10]; 4701 4702 u8 reserved_at_60[0xa0]; 4703 4704 u8 reserved_at_100[76][0x8]; 4705 u8 supported_issi_dw0[0x20]; 4706 }; 4707 4708 struct mlx5_ifc_query_issi_in_bits { 4709 u8 opcode[0x10]; 4710 u8 reserved_at_10[0x10]; 4711 4712 u8 reserved_at_20[0x10]; 4713 u8 op_mod[0x10]; 4714 4715 u8 reserved_at_40[0x40]; 4716 }; 4717 4718 struct mlx5_ifc_set_driver_version_out_bits { 4719 u8 status[0x8]; 4720 u8 reserved_0[0x18]; 4721 4722 u8 syndrome[0x20]; 4723 u8 reserved_1[0x40]; 4724 }; 4725 4726 struct mlx5_ifc_set_driver_version_in_bits { 4727 u8 opcode[0x10]; 4728 u8 reserved_0[0x10]; 4729 4730 u8 reserved_1[0x10]; 4731 u8 op_mod[0x10]; 4732 4733 u8 reserved_2[0x40]; 4734 u8 driver_version[64][0x8]; 4735 }; 4736 4737 struct mlx5_ifc_query_hca_vport_pkey_out_bits { 4738 u8 status[0x8]; 4739 u8 reserved_at_8[0x18]; 4740 4741 u8 syndrome[0x20]; 4742 4743 u8 reserved_at_40[0x40]; 4744 4745 struct mlx5_ifc_pkey_bits pkey[0]; 4746 }; 4747 4748 struct mlx5_ifc_query_hca_vport_pkey_in_bits { 4749 u8 opcode[0x10]; 4750 u8 reserved_at_10[0x10]; 4751 4752 u8 reserved_at_20[0x10]; 4753 u8 op_mod[0x10]; 4754 4755 u8 other_vport[0x1]; 4756 u8 reserved_at_41[0xb]; 4757 u8 port_num[0x4]; 4758 u8 vport_number[0x10]; 4759 4760 u8 reserved_at_60[0x10]; 4761 u8 pkey_index[0x10]; 4762 }; 4763 4764 enum { 4765 MLX5_HCA_VPORT_SEL_PORT_GUID = 1 << 0, 4766 MLX5_HCA_VPORT_SEL_NODE_GUID = 1 << 1, 4767 MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2, 4768 }; 4769 4770 struct mlx5_ifc_query_hca_vport_gid_out_bits { 4771 u8 status[0x8]; 4772 u8 reserved_at_8[0x18]; 4773 4774 u8 syndrome[0x20]; 4775 4776 u8 reserved_at_40[0x20]; 4777 4778 u8 gids_num[0x10]; 4779 u8 reserved_at_70[0x10]; 4780 4781 struct mlx5_ifc_array128_auto_bits gid[0]; 4782 }; 4783 4784 struct mlx5_ifc_query_hca_vport_gid_in_bits { 4785 u8 opcode[0x10]; 4786 u8 reserved_at_10[0x10]; 4787 4788 u8 reserved_at_20[0x10]; 4789 u8 op_mod[0x10]; 4790 4791 u8 other_vport[0x1]; 4792 u8 reserved_at_41[0xb]; 4793 u8 port_num[0x4]; 4794 u8 vport_number[0x10]; 4795 4796 u8 reserved_at_60[0x10]; 4797 u8 gid_index[0x10]; 4798 }; 4799 4800 struct mlx5_ifc_query_hca_vport_context_out_bits { 4801 u8 status[0x8]; 4802 u8 reserved_at_8[0x18]; 4803 4804 u8 syndrome[0x20]; 4805 4806 u8 reserved_at_40[0x40]; 4807 4808 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 4809 }; 4810 4811 struct mlx5_ifc_query_hca_vport_context_in_bits { 4812 u8 opcode[0x10]; 4813 u8 reserved_at_10[0x10]; 4814 4815 u8 reserved_at_20[0x10]; 4816 u8 op_mod[0x10]; 4817 4818 u8 other_vport[0x1]; 4819 u8 reserved_at_41[0xb]; 4820 u8 port_num[0x4]; 4821 u8 vport_number[0x10]; 4822 4823 u8 reserved_at_60[0x20]; 4824 }; 4825 4826 struct mlx5_ifc_query_hca_cap_out_bits { 4827 u8 status[0x8]; 4828 u8 reserved_at_8[0x18]; 4829 4830 u8 syndrome[0x20]; 4831 4832 u8 reserved_at_40[0x40]; 4833 4834 union mlx5_ifc_hca_cap_union_bits capability; 4835 }; 4836 4837 struct mlx5_ifc_query_hca_cap_in_bits { 4838 u8 opcode[0x10]; 4839 u8 reserved_at_10[0x10]; 4840 4841 u8 reserved_at_20[0x10]; 4842 u8 op_mod[0x10]; 4843 4844 u8 reserved_at_40[0x40]; 4845 }; 4846 4847 struct mlx5_ifc_query_flow_table_out_bits { 4848 u8 status[0x8]; 4849 u8 reserved_at_8[0x18]; 4850 4851 u8 syndrome[0x20]; 4852 4853 u8 reserved_at_40[0x80]; 4854 4855 u8 reserved_at_c0[0x8]; 4856 u8 level[0x8]; 4857 u8 reserved_at_d0[0x8]; 4858 u8 log_size[0x8]; 4859 4860 u8 reserved_at_e0[0x120]; 4861 }; 4862 4863 struct mlx5_ifc_query_flow_table_in_bits { 4864 u8 opcode[0x10]; 4865 u8 reserved_at_10[0x10]; 4866 4867 u8 reserved_at_20[0x10]; 4868 u8 op_mod[0x10]; 4869 4870 u8 reserved_at_40[0x40]; 4871 4872 u8 table_type[0x8]; 4873 u8 reserved_at_88[0x18]; 4874 4875 u8 reserved_at_a0[0x8]; 4876 u8 table_id[0x18]; 4877 4878 u8 reserved_at_c0[0x140]; 4879 }; 4880 4881 struct mlx5_ifc_query_fte_out_bits { 4882 u8 status[0x8]; 4883 u8 reserved_at_8[0x18]; 4884 4885 u8 syndrome[0x20]; 4886 4887 u8 reserved_at_40[0x1c0]; 4888 4889 struct mlx5_ifc_flow_context_bits flow_context; 4890 }; 4891 4892 struct mlx5_ifc_query_fte_in_bits { 4893 u8 opcode[0x10]; 4894 u8 reserved_at_10[0x10]; 4895 4896 u8 reserved_at_20[0x10]; 4897 u8 op_mod[0x10]; 4898 4899 u8 reserved_at_40[0x40]; 4900 4901 u8 table_type[0x8]; 4902 u8 reserved_at_88[0x18]; 4903 4904 u8 reserved_at_a0[0x8]; 4905 u8 table_id[0x18]; 4906 4907 u8 reserved_at_c0[0x40]; 4908 4909 u8 flow_index[0x20]; 4910 4911 u8 reserved_at_120[0xe0]; 4912 }; 4913 4914 enum { 4915 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 4916 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 4917 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 4918 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3, 4919 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_3 = 0x4, 4920 }; 4921 4922 struct mlx5_ifc_query_flow_group_out_bits { 4923 u8 status[0x8]; 4924 u8 reserved_at_8[0x18]; 4925 4926 u8 syndrome[0x20]; 4927 4928 u8 reserved_at_40[0xa0]; 4929 4930 u8 start_flow_index[0x20]; 4931 4932 u8 reserved_at_100[0x20]; 4933 4934 u8 end_flow_index[0x20]; 4935 4936 u8 reserved_at_140[0xa0]; 4937 4938 u8 reserved_at_1e0[0x18]; 4939 u8 match_criteria_enable[0x8]; 4940 4941 struct mlx5_ifc_fte_match_param_bits match_criteria; 4942 4943 u8 reserved_at_1200[0xe00]; 4944 }; 4945 4946 struct mlx5_ifc_query_flow_group_in_bits { 4947 u8 opcode[0x10]; 4948 u8 reserved_at_10[0x10]; 4949 4950 u8 reserved_at_20[0x10]; 4951 u8 op_mod[0x10]; 4952 4953 u8 reserved_at_40[0x40]; 4954 4955 u8 table_type[0x8]; 4956 u8 reserved_at_88[0x18]; 4957 4958 u8 reserved_at_a0[0x8]; 4959 u8 table_id[0x18]; 4960 4961 u8 group_id[0x20]; 4962 4963 u8 reserved_at_e0[0x120]; 4964 }; 4965 4966 struct mlx5_ifc_query_flow_counter_out_bits { 4967 u8 status[0x8]; 4968 u8 reserved_at_8[0x18]; 4969 4970 u8 syndrome[0x20]; 4971 4972 u8 reserved_at_40[0x40]; 4973 4974 struct mlx5_ifc_traffic_counter_bits flow_statistics[0]; 4975 }; 4976 4977 struct mlx5_ifc_query_flow_counter_in_bits { 4978 u8 opcode[0x10]; 4979 u8 reserved_at_10[0x10]; 4980 4981 u8 reserved_at_20[0x10]; 4982 u8 op_mod[0x10]; 4983 4984 u8 reserved_at_40[0x80]; 4985 4986 u8 clear[0x1]; 4987 u8 reserved_at_c1[0xf]; 4988 u8 num_of_counters[0x10]; 4989 4990 u8 flow_counter_id[0x20]; 4991 }; 4992 4993 struct mlx5_ifc_query_esw_vport_context_out_bits { 4994 u8 status[0x8]; 4995 u8 reserved_at_8[0x18]; 4996 4997 u8 syndrome[0x20]; 4998 4999 u8 reserved_at_40[0x40]; 5000 5001 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 5002 }; 5003 5004 struct mlx5_ifc_query_esw_vport_context_in_bits { 5005 u8 opcode[0x10]; 5006 u8 reserved_at_10[0x10]; 5007 5008 u8 reserved_at_20[0x10]; 5009 u8 op_mod[0x10]; 5010 5011 u8 other_vport[0x1]; 5012 u8 reserved_at_41[0xf]; 5013 u8 vport_number[0x10]; 5014 5015 u8 reserved_at_60[0x20]; 5016 }; 5017 5018 struct mlx5_ifc_modify_esw_vport_context_out_bits { 5019 u8 status[0x8]; 5020 u8 reserved_at_8[0x18]; 5021 5022 u8 syndrome[0x20]; 5023 5024 u8 reserved_at_40[0x40]; 5025 }; 5026 5027 struct mlx5_ifc_esw_vport_context_fields_select_bits { 5028 u8 reserved_at_0[0x1b]; 5029 u8 fdb_to_vport_reg_c_id[0x1]; 5030 u8 vport_cvlan_insert[0x1]; 5031 u8 vport_svlan_insert[0x1]; 5032 u8 vport_cvlan_strip[0x1]; 5033 u8 vport_svlan_strip[0x1]; 5034 }; 5035 5036 struct mlx5_ifc_modify_esw_vport_context_in_bits { 5037 u8 opcode[0x10]; 5038 u8 reserved_at_10[0x10]; 5039 5040 u8 reserved_at_20[0x10]; 5041 u8 op_mod[0x10]; 5042 5043 u8 other_vport[0x1]; 5044 u8 reserved_at_41[0xf]; 5045 u8 vport_number[0x10]; 5046 5047 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select; 5048 5049 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 5050 }; 5051 5052 struct mlx5_ifc_query_eq_out_bits { 5053 u8 status[0x8]; 5054 u8 reserved_at_8[0x18]; 5055 5056 u8 syndrome[0x20]; 5057 5058 u8 reserved_at_40[0x40]; 5059 5060 struct mlx5_ifc_eqc_bits eq_context_entry; 5061 5062 u8 reserved_at_280[0x40]; 5063 5064 u8 event_bitmask[0x40]; 5065 5066 u8 reserved_at_300[0x580]; 5067 5068 u8 pas[0][0x40]; 5069 }; 5070 5071 struct mlx5_ifc_query_eq_in_bits { 5072 u8 opcode[0x10]; 5073 u8 reserved_at_10[0x10]; 5074 5075 u8 reserved_at_20[0x10]; 5076 u8 op_mod[0x10]; 5077 5078 u8 reserved_at_40[0x18]; 5079 u8 eq_number[0x8]; 5080 5081 u8 reserved_at_60[0x20]; 5082 }; 5083 5084 struct mlx5_ifc_packet_reformat_context_in_bits { 5085 u8 reserved_at_0[0x5]; 5086 u8 reformat_type[0x3]; 5087 u8 reserved_at_8[0xe]; 5088 u8 reformat_data_size[0xa]; 5089 5090 u8 reserved_at_20[0x10]; 5091 u8 reformat_data[2][0x8]; 5092 5093 u8 more_reformat_data[0][0x8]; 5094 }; 5095 5096 struct mlx5_ifc_query_packet_reformat_context_out_bits { 5097 u8 status[0x8]; 5098 u8 reserved_at_8[0x18]; 5099 5100 u8 syndrome[0x20]; 5101 5102 u8 reserved_at_40[0xa0]; 5103 5104 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context[0]; 5105 }; 5106 5107 struct mlx5_ifc_query_packet_reformat_context_in_bits { 5108 u8 opcode[0x10]; 5109 u8 reserved_at_10[0x10]; 5110 5111 u8 reserved_at_20[0x10]; 5112 u8 op_mod[0x10]; 5113 5114 u8 packet_reformat_id[0x20]; 5115 5116 u8 reserved_at_60[0xa0]; 5117 }; 5118 5119 struct mlx5_ifc_alloc_packet_reformat_context_out_bits { 5120 u8 status[0x8]; 5121 u8 reserved_at_8[0x18]; 5122 5123 u8 syndrome[0x20]; 5124 5125 u8 packet_reformat_id[0x20]; 5126 5127 u8 reserved_at_60[0x20]; 5128 }; 5129 5130 enum { 5131 MLX5_REFORMAT_TYPE_L2_TO_VXLAN = 0x0, 5132 MLX5_REFORMAT_TYPE_L2_TO_NVGRE = 0x1, 5133 MLX5_REFORMAT_TYPE_L2_TO_L2_TUNNEL = 0x2, 5134 MLX5_REFORMAT_TYPE_L3_TUNNEL_TO_L2 = 0x3, 5135 MLX5_REFORMAT_TYPE_L2_TO_L3_TUNNEL = 0x4, 5136 }; 5137 5138 struct mlx5_ifc_alloc_packet_reformat_context_in_bits { 5139 u8 opcode[0x10]; 5140 u8 reserved_at_10[0x10]; 5141 5142 u8 reserved_at_20[0x10]; 5143 u8 op_mod[0x10]; 5144 5145 u8 reserved_at_40[0xa0]; 5146 5147 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context; 5148 }; 5149 5150 struct mlx5_ifc_dealloc_packet_reformat_context_out_bits { 5151 u8 status[0x8]; 5152 u8 reserved_at_8[0x18]; 5153 5154 u8 syndrome[0x20]; 5155 5156 u8 reserved_at_40[0x40]; 5157 }; 5158 5159 struct mlx5_ifc_dealloc_packet_reformat_context_in_bits { 5160 u8 opcode[0x10]; 5161 u8 reserved_at_10[0x10]; 5162 5163 u8 reserved_20[0x10]; 5164 u8 op_mod[0x10]; 5165 5166 u8 packet_reformat_id[0x20]; 5167 5168 u8 reserved_60[0x20]; 5169 }; 5170 5171 struct mlx5_ifc_set_action_in_bits { 5172 u8 action_type[0x4]; 5173 u8 field[0xc]; 5174 u8 reserved_at_10[0x3]; 5175 u8 offset[0x5]; 5176 u8 reserved_at_18[0x3]; 5177 u8 length[0x5]; 5178 5179 u8 data[0x20]; 5180 }; 5181 5182 struct mlx5_ifc_add_action_in_bits { 5183 u8 action_type[0x4]; 5184 u8 field[0xc]; 5185 u8 reserved_at_10[0x10]; 5186 5187 u8 data[0x20]; 5188 }; 5189 5190 union mlx5_ifc_set_action_in_add_action_in_auto_bits { 5191 struct mlx5_ifc_set_action_in_bits set_action_in; 5192 struct mlx5_ifc_add_action_in_bits add_action_in; 5193 u8 reserved_at_0[0x40]; 5194 }; 5195 5196 enum { 5197 MLX5_ACTION_TYPE_SET = 0x1, 5198 MLX5_ACTION_TYPE_ADD = 0x2, 5199 }; 5200 5201 enum { 5202 MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16 = 0x1, 5203 MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0 = 0x2, 5204 MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE = 0x3, 5205 MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16 = 0x4, 5206 MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0 = 0x5, 5207 MLX5_ACTION_IN_FIELD_OUT_IP_DSCP = 0x6, 5208 MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS = 0x7, 5209 MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT = 0x8, 5210 MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT = 0x9, 5211 MLX5_ACTION_IN_FIELD_OUT_IP_TTL = 0xa, 5212 MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT = 0xb, 5213 MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT = 0xc, 5214 MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96 = 0xd, 5215 MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64 = 0xe, 5216 MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32 = 0xf, 5217 MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0 = 0x10, 5218 MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96 = 0x11, 5219 MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64 = 0x12, 5220 MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32 = 0x13, 5221 MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0 = 0x14, 5222 MLX5_ACTION_IN_FIELD_OUT_SIPV4 = 0x15, 5223 MLX5_ACTION_IN_FIELD_OUT_DIPV4 = 0x16, 5224 MLX5_ACTION_IN_FIELD_OUT_FIRST_VID = 0x17, 5225 MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47, 5226 MLX5_ACTION_IN_FIELD_METADATA_REG_C_0 = 0x51, 5227 }; 5228 5229 struct mlx5_ifc_alloc_modify_header_context_out_bits { 5230 u8 status[0x8]; 5231 u8 reserved_at_8[0x18]; 5232 5233 u8 syndrome[0x20]; 5234 5235 u8 modify_header_id[0x20]; 5236 5237 u8 reserved_at_60[0x20]; 5238 }; 5239 5240 struct mlx5_ifc_alloc_modify_header_context_in_bits { 5241 u8 opcode[0x10]; 5242 u8 reserved_at_10[0x10]; 5243 5244 u8 reserved_at_20[0x10]; 5245 u8 op_mod[0x10]; 5246 5247 u8 reserved_at_40[0x20]; 5248 5249 u8 table_type[0x8]; 5250 u8 reserved_at_68[0x10]; 5251 u8 num_of_actions[0x8]; 5252 5253 union mlx5_ifc_set_action_in_add_action_in_auto_bits actions[0]; 5254 }; 5255 5256 struct mlx5_ifc_dealloc_modify_header_context_out_bits { 5257 u8 status[0x8]; 5258 u8 reserved_at_8[0x18]; 5259 5260 u8 syndrome[0x20]; 5261 5262 u8 reserved_at_40[0x40]; 5263 }; 5264 5265 struct mlx5_ifc_dealloc_modify_header_context_in_bits { 5266 u8 opcode[0x10]; 5267 u8 reserved_at_10[0x10]; 5268 5269 u8 reserved_at_20[0x10]; 5270 u8 op_mod[0x10]; 5271 5272 u8 modify_header_id[0x20]; 5273 5274 u8 reserved_at_60[0x20]; 5275 }; 5276 5277 struct mlx5_ifc_query_dct_out_bits { 5278 u8 status[0x8]; 5279 u8 reserved_at_8[0x18]; 5280 5281 u8 syndrome[0x20]; 5282 5283 u8 reserved_at_40[0x40]; 5284 5285 struct mlx5_ifc_dctc_bits dct_context_entry; 5286 5287 u8 reserved_at_280[0x180]; 5288 }; 5289 5290 struct mlx5_ifc_query_dct_in_bits { 5291 u8 opcode[0x10]; 5292 u8 reserved_at_10[0x10]; 5293 5294 u8 reserved_at_20[0x10]; 5295 u8 op_mod[0x10]; 5296 5297 u8 reserved_at_40[0x8]; 5298 u8 dctn[0x18]; 5299 5300 u8 reserved_at_60[0x20]; 5301 }; 5302 5303 struct mlx5_ifc_query_cq_out_bits { 5304 u8 status[0x8]; 5305 u8 reserved_at_8[0x18]; 5306 5307 u8 syndrome[0x20]; 5308 5309 u8 reserved_at_40[0x40]; 5310 5311 struct mlx5_ifc_cqc_bits cq_context; 5312 5313 u8 reserved_at_280[0x600]; 5314 5315 u8 pas[0][0x40]; 5316 }; 5317 5318 struct mlx5_ifc_query_cq_in_bits { 5319 u8 opcode[0x10]; 5320 u8 reserved_at_10[0x10]; 5321 5322 u8 reserved_at_20[0x10]; 5323 u8 op_mod[0x10]; 5324 5325 u8 reserved_at_40[0x8]; 5326 u8 cqn[0x18]; 5327 5328 u8 reserved_at_60[0x20]; 5329 }; 5330 5331 struct mlx5_ifc_query_cong_status_out_bits { 5332 u8 status[0x8]; 5333 u8 reserved_at_8[0x18]; 5334 5335 u8 syndrome[0x20]; 5336 5337 u8 reserved_at_40[0x20]; 5338 5339 u8 enable[0x1]; 5340 u8 tag_enable[0x1]; 5341 u8 reserved_at_62[0x1e]; 5342 }; 5343 5344 struct mlx5_ifc_query_cong_status_in_bits { 5345 u8 opcode[0x10]; 5346 u8 reserved_at_10[0x10]; 5347 5348 u8 reserved_at_20[0x10]; 5349 u8 op_mod[0x10]; 5350 5351 u8 reserved_at_40[0x18]; 5352 u8 priority[0x4]; 5353 u8 cong_protocol[0x4]; 5354 5355 u8 reserved_at_60[0x20]; 5356 }; 5357 5358 struct mlx5_ifc_query_cong_statistics_out_bits { 5359 u8 status[0x8]; 5360 u8 reserved_at_8[0x18]; 5361 5362 u8 syndrome[0x20]; 5363 5364 u8 reserved_at_40[0x40]; 5365 5366 u8 rp_cur_flows[0x20]; 5367 5368 u8 sum_flows[0x20]; 5369 5370 u8 rp_cnp_ignored_high[0x20]; 5371 5372 u8 rp_cnp_ignored_low[0x20]; 5373 5374 u8 rp_cnp_handled_high[0x20]; 5375 5376 u8 rp_cnp_handled_low[0x20]; 5377 5378 u8 reserved_at_140[0x100]; 5379 5380 u8 time_stamp_high[0x20]; 5381 5382 u8 time_stamp_low[0x20]; 5383 5384 u8 accumulators_period[0x20]; 5385 5386 u8 np_ecn_marked_roce_packets_high[0x20]; 5387 5388 u8 np_ecn_marked_roce_packets_low[0x20]; 5389 5390 u8 np_cnp_sent_high[0x20]; 5391 5392 u8 np_cnp_sent_low[0x20]; 5393 5394 u8 reserved_at_320[0x560]; 5395 }; 5396 5397 struct mlx5_ifc_query_cong_statistics_in_bits { 5398 u8 opcode[0x10]; 5399 u8 reserved_at_10[0x10]; 5400 5401 u8 reserved_at_20[0x10]; 5402 u8 op_mod[0x10]; 5403 5404 u8 clear[0x1]; 5405 u8 reserved_at_41[0x1f]; 5406 5407 u8 reserved_at_60[0x20]; 5408 }; 5409 5410 struct mlx5_ifc_query_cong_params_out_bits { 5411 u8 status[0x8]; 5412 u8 reserved_at_8[0x18]; 5413 5414 u8 syndrome[0x20]; 5415 5416 u8 reserved_at_40[0x40]; 5417 5418 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 5419 }; 5420 5421 struct mlx5_ifc_query_cong_params_in_bits { 5422 u8 opcode[0x10]; 5423 u8 reserved_at_10[0x10]; 5424 5425 u8 reserved_at_20[0x10]; 5426 u8 op_mod[0x10]; 5427 5428 u8 reserved_at_40[0x1c]; 5429 u8 cong_protocol[0x4]; 5430 5431 u8 reserved_at_60[0x20]; 5432 }; 5433 5434 struct mlx5_ifc_query_adapter_out_bits { 5435 u8 status[0x8]; 5436 u8 reserved_at_8[0x18]; 5437 5438 u8 syndrome[0x20]; 5439 5440 u8 reserved_at_40[0x40]; 5441 5442 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct; 5443 }; 5444 5445 struct mlx5_ifc_query_adapter_in_bits { 5446 u8 opcode[0x10]; 5447 u8 reserved_at_10[0x10]; 5448 5449 u8 reserved_at_20[0x10]; 5450 u8 op_mod[0x10]; 5451 5452 u8 reserved_at_40[0x40]; 5453 }; 5454 5455 struct mlx5_ifc_qp_2rst_out_bits { 5456 u8 status[0x8]; 5457 u8 reserved_at_8[0x18]; 5458 5459 u8 syndrome[0x20]; 5460 5461 u8 reserved_at_40[0x40]; 5462 }; 5463 5464 struct mlx5_ifc_qp_2rst_in_bits { 5465 u8 opcode[0x10]; 5466 u8 uid[0x10]; 5467 5468 u8 reserved_at_20[0x10]; 5469 u8 op_mod[0x10]; 5470 5471 u8 reserved_at_40[0x8]; 5472 u8 qpn[0x18]; 5473 5474 u8 reserved_at_60[0x20]; 5475 }; 5476 5477 struct mlx5_ifc_qp_2err_out_bits { 5478 u8 status[0x8]; 5479 u8 reserved_at_8[0x18]; 5480 5481 u8 syndrome[0x20]; 5482 5483 u8 reserved_at_40[0x40]; 5484 }; 5485 5486 struct mlx5_ifc_qp_2err_in_bits { 5487 u8 opcode[0x10]; 5488 u8 uid[0x10]; 5489 5490 u8 reserved_at_20[0x10]; 5491 u8 op_mod[0x10]; 5492 5493 u8 reserved_at_40[0x8]; 5494 u8 qpn[0x18]; 5495 5496 u8 reserved_at_60[0x20]; 5497 }; 5498 5499 struct mlx5_ifc_page_fault_resume_out_bits { 5500 u8 status[0x8]; 5501 u8 reserved_at_8[0x18]; 5502 5503 u8 syndrome[0x20]; 5504 5505 u8 reserved_at_40[0x40]; 5506 }; 5507 5508 struct mlx5_ifc_page_fault_resume_in_bits { 5509 u8 opcode[0x10]; 5510 u8 reserved_at_10[0x10]; 5511 5512 u8 reserved_at_20[0x10]; 5513 u8 op_mod[0x10]; 5514 5515 u8 error[0x1]; 5516 u8 reserved_at_41[0x4]; 5517 u8 page_fault_type[0x3]; 5518 u8 wq_number[0x18]; 5519 5520 u8 reserved_at_60[0x8]; 5521 u8 token[0x18]; 5522 }; 5523 5524 struct mlx5_ifc_nop_out_bits { 5525 u8 status[0x8]; 5526 u8 reserved_at_8[0x18]; 5527 5528 u8 syndrome[0x20]; 5529 5530 u8 reserved_at_40[0x40]; 5531 }; 5532 5533 struct mlx5_ifc_nop_in_bits { 5534 u8 opcode[0x10]; 5535 u8 reserved_at_10[0x10]; 5536 5537 u8 reserved_at_20[0x10]; 5538 u8 op_mod[0x10]; 5539 5540 u8 reserved_at_40[0x40]; 5541 }; 5542 5543 struct mlx5_ifc_modify_vport_state_out_bits { 5544 u8 status[0x8]; 5545 u8 reserved_at_8[0x18]; 5546 5547 u8 syndrome[0x20]; 5548 5549 u8 reserved_at_40[0x40]; 5550 }; 5551 5552 struct mlx5_ifc_modify_vport_state_in_bits { 5553 u8 opcode[0x10]; 5554 u8 reserved_at_10[0x10]; 5555 5556 u8 reserved_at_20[0x10]; 5557 u8 op_mod[0x10]; 5558 5559 u8 other_vport[0x1]; 5560 u8 reserved_at_41[0xf]; 5561 u8 vport_number[0x10]; 5562 5563 u8 reserved_at_60[0x18]; 5564 u8 admin_state[0x4]; 5565 u8 reserved_at_7c[0x4]; 5566 }; 5567 5568 struct mlx5_ifc_modify_tis_out_bits { 5569 u8 status[0x8]; 5570 u8 reserved_at_8[0x18]; 5571 5572 u8 syndrome[0x20]; 5573 5574 u8 reserved_at_40[0x40]; 5575 }; 5576 5577 struct mlx5_ifc_modify_tis_bitmask_bits { 5578 u8 reserved_at_0[0x20]; 5579 5580 u8 reserved_at_20[0x1d]; 5581 u8 lag_tx_port_affinity[0x1]; 5582 u8 strict_lag_tx_port_affinity[0x1]; 5583 u8 prio[0x1]; 5584 }; 5585 5586 struct mlx5_ifc_modify_tis_in_bits { 5587 u8 opcode[0x10]; 5588 u8 uid[0x10]; 5589 5590 u8 reserved_at_20[0x10]; 5591 u8 op_mod[0x10]; 5592 5593 u8 reserved_at_40[0x8]; 5594 u8 tisn[0x18]; 5595 5596 u8 reserved_at_60[0x20]; 5597 5598 struct mlx5_ifc_modify_tis_bitmask_bits bitmask; 5599 5600 u8 reserved_at_c0[0x40]; 5601 5602 struct mlx5_ifc_tisc_bits ctx; 5603 }; 5604 5605 struct mlx5_ifc_modify_tir_bitmask_bits { 5606 u8 reserved_at_0[0x20]; 5607 5608 u8 reserved_at_20[0x1b]; 5609 u8 self_lb_en[0x1]; 5610 u8 reserved_at_3c[0x1]; 5611 u8 hash[0x1]; 5612 u8 reserved_at_3e[0x1]; 5613 u8 lro[0x1]; 5614 }; 5615 5616 struct mlx5_ifc_modify_tir_out_bits { 5617 u8 status[0x8]; 5618 u8 reserved_at_8[0x18]; 5619 5620 u8 syndrome[0x20]; 5621 5622 u8 reserved_at_40[0x40]; 5623 }; 5624 5625 struct mlx5_ifc_modify_tir_in_bits { 5626 u8 opcode[0x10]; 5627 u8 uid[0x10]; 5628 5629 u8 reserved_at_20[0x10]; 5630 u8 op_mod[0x10]; 5631 5632 u8 reserved_at_40[0x8]; 5633 u8 tirn[0x18]; 5634 5635 u8 reserved_at_60[0x20]; 5636 5637 struct mlx5_ifc_modify_tir_bitmask_bits bitmask; 5638 5639 u8 reserved_at_c0[0x40]; 5640 5641 struct mlx5_ifc_tirc_bits ctx; 5642 }; 5643 5644 struct mlx5_ifc_modify_sq_out_bits { 5645 u8 status[0x8]; 5646 u8 reserved_at_8[0x18]; 5647 5648 u8 syndrome[0x20]; 5649 5650 u8 reserved_at_40[0x40]; 5651 }; 5652 5653 struct mlx5_ifc_modify_sq_in_bits { 5654 u8 opcode[0x10]; 5655 u8 uid[0x10]; 5656 5657 u8 reserved_at_20[0x10]; 5658 u8 op_mod[0x10]; 5659 5660 u8 sq_state[0x4]; 5661 u8 reserved_at_44[0x4]; 5662 u8 sqn[0x18]; 5663 5664 u8 reserved_at_60[0x20]; 5665 5666 u8 modify_bitmask[0x40]; 5667 5668 u8 reserved_at_c0[0x40]; 5669 5670 struct mlx5_ifc_sqc_bits ctx; 5671 }; 5672 5673 struct mlx5_ifc_modify_scheduling_element_out_bits { 5674 u8 status[0x8]; 5675 u8 reserved_at_8[0x18]; 5676 5677 u8 syndrome[0x20]; 5678 5679 u8 reserved_at_40[0x1c0]; 5680 }; 5681 5682 enum { 5683 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1, 5684 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2, 5685 }; 5686 5687 struct mlx5_ifc_modify_scheduling_element_in_bits { 5688 u8 opcode[0x10]; 5689 u8 reserved_at_10[0x10]; 5690 5691 u8 reserved_at_20[0x10]; 5692 u8 op_mod[0x10]; 5693 5694 u8 scheduling_hierarchy[0x8]; 5695 u8 reserved_at_48[0x18]; 5696 5697 u8 scheduling_element_id[0x20]; 5698 5699 u8 reserved_at_80[0x20]; 5700 5701 u8 modify_bitmask[0x20]; 5702 5703 u8 reserved_at_c0[0x40]; 5704 5705 struct mlx5_ifc_scheduling_context_bits scheduling_context; 5706 5707 u8 reserved_at_300[0x100]; 5708 }; 5709 5710 struct mlx5_ifc_modify_rqt_out_bits { 5711 u8 status[0x8]; 5712 u8 reserved_at_8[0x18]; 5713 5714 u8 syndrome[0x20]; 5715 5716 u8 reserved_at_40[0x40]; 5717 }; 5718 5719 struct mlx5_ifc_rqt_bitmask_bits { 5720 u8 reserved_at_0[0x20]; 5721 5722 u8 reserved_at_20[0x1f]; 5723 u8 rqn_list[0x1]; 5724 }; 5725 5726 struct mlx5_ifc_modify_rqt_in_bits { 5727 u8 opcode[0x10]; 5728 u8 uid[0x10]; 5729 5730 u8 reserved_at_20[0x10]; 5731 u8 op_mod[0x10]; 5732 5733 u8 reserved_at_40[0x8]; 5734 u8 rqtn[0x18]; 5735 5736 u8 reserved_at_60[0x20]; 5737 5738 struct mlx5_ifc_rqt_bitmask_bits bitmask; 5739 5740 u8 reserved_at_c0[0x40]; 5741 5742 struct mlx5_ifc_rqtc_bits ctx; 5743 }; 5744 5745 struct mlx5_ifc_modify_rq_out_bits { 5746 u8 status[0x8]; 5747 u8 reserved_at_8[0x18]; 5748 5749 u8 syndrome[0x20]; 5750 5751 u8 reserved_at_40[0x40]; 5752 }; 5753 5754 enum { 5755 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1, 5756 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2, 5757 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3, 5758 }; 5759 5760 struct mlx5_ifc_modify_rq_in_bits { 5761 u8 opcode[0x10]; 5762 u8 uid[0x10]; 5763 5764 u8 reserved_at_20[0x10]; 5765 u8 op_mod[0x10]; 5766 5767 u8 rq_state[0x4]; 5768 u8 reserved_at_44[0x4]; 5769 u8 rqn[0x18]; 5770 5771 u8 reserved_at_60[0x20]; 5772 5773 u8 modify_bitmask[0x40]; 5774 5775 u8 reserved_at_c0[0x40]; 5776 5777 struct mlx5_ifc_rqc_bits ctx; 5778 }; 5779 5780 struct mlx5_ifc_modify_rmp_out_bits { 5781 u8 status[0x8]; 5782 u8 reserved_at_8[0x18]; 5783 5784 u8 syndrome[0x20]; 5785 5786 u8 reserved_at_40[0x40]; 5787 }; 5788 5789 struct mlx5_ifc_rmp_bitmask_bits { 5790 u8 reserved_at_0[0x20]; 5791 5792 u8 reserved_at_20[0x1f]; 5793 u8 lwm[0x1]; 5794 }; 5795 5796 struct mlx5_ifc_modify_rmp_in_bits { 5797 u8 opcode[0x10]; 5798 u8 uid[0x10]; 5799 5800 u8 reserved_at_20[0x10]; 5801 u8 op_mod[0x10]; 5802 5803 u8 rmp_state[0x4]; 5804 u8 reserved_at_44[0x4]; 5805 u8 rmpn[0x18]; 5806 5807 u8 reserved_at_60[0x20]; 5808 5809 struct mlx5_ifc_rmp_bitmask_bits bitmask; 5810 5811 u8 reserved_at_c0[0x40]; 5812 5813 struct mlx5_ifc_rmpc_bits ctx; 5814 }; 5815 5816 struct mlx5_ifc_modify_nic_vport_context_out_bits { 5817 u8 status[0x8]; 5818 u8 reserved_at_8[0x18]; 5819 5820 u8 syndrome[0x20]; 5821 5822 u8 reserved_at_40[0x40]; 5823 }; 5824 5825 struct mlx5_ifc_modify_nic_vport_field_select_bits { 5826 u8 reserved_at_0[0x12]; 5827 u8 affiliation[0x1]; 5828 u8 reserved_at_13[0x1]; 5829 u8 disable_uc_local_lb[0x1]; 5830 u8 disable_mc_local_lb[0x1]; 5831 u8 node_guid[0x1]; 5832 u8 port_guid[0x1]; 5833 u8 min_inline[0x1]; 5834 u8 mtu[0x1]; 5835 u8 change_event[0x1]; 5836 u8 promisc[0x1]; 5837 u8 permanent_address[0x1]; 5838 u8 addresses_list[0x1]; 5839 u8 roce_en[0x1]; 5840 u8 reserved_at_1f[0x1]; 5841 }; 5842 5843 struct mlx5_ifc_modify_nic_vport_context_in_bits { 5844 u8 opcode[0x10]; 5845 u8 reserved_at_10[0x10]; 5846 5847 u8 reserved_at_20[0x10]; 5848 u8 op_mod[0x10]; 5849 5850 u8 other_vport[0x1]; 5851 u8 reserved_at_41[0xf]; 5852 u8 vport_number[0x10]; 5853 5854 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select; 5855 5856 u8 reserved_at_80[0x780]; 5857 5858 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 5859 }; 5860 5861 struct mlx5_ifc_modify_hca_vport_context_out_bits { 5862 u8 status[0x8]; 5863 u8 reserved_at_8[0x18]; 5864 5865 u8 syndrome[0x20]; 5866 5867 u8 reserved_at_40[0x40]; 5868 }; 5869 5870 struct mlx5_ifc_modify_hca_vport_context_in_bits { 5871 u8 opcode[0x10]; 5872 u8 reserved_at_10[0x10]; 5873 5874 u8 reserved_at_20[0x10]; 5875 u8 op_mod[0x10]; 5876 5877 u8 other_vport[0x1]; 5878 u8 reserved_at_41[0xb]; 5879 u8 port_num[0x4]; 5880 u8 vport_number[0x10]; 5881 5882 u8 reserved_at_60[0x20]; 5883 5884 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 5885 }; 5886 5887 struct mlx5_ifc_modify_cq_out_bits { 5888 u8 status[0x8]; 5889 u8 reserved_at_8[0x18]; 5890 5891 u8 syndrome[0x20]; 5892 5893 u8 reserved_at_40[0x40]; 5894 }; 5895 5896 enum { 5897 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0, 5898 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1, 5899 }; 5900 5901 struct mlx5_ifc_modify_cq_in_bits { 5902 u8 opcode[0x10]; 5903 u8 uid[0x10]; 5904 5905 u8 reserved_at_20[0x10]; 5906 u8 op_mod[0x10]; 5907 5908 u8 reserved_at_40[0x8]; 5909 u8 cqn[0x18]; 5910 5911 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select; 5912 5913 struct mlx5_ifc_cqc_bits cq_context; 5914 5915 u8 reserved_at_280[0x40]; 5916 5917 u8 cq_umem_valid[0x1]; 5918 u8 reserved_at_2c1[0x5bf]; 5919 5920 u8 pas[0][0x40]; 5921 }; 5922 5923 struct mlx5_ifc_modify_cong_status_out_bits { 5924 u8 status[0x8]; 5925 u8 reserved_at_8[0x18]; 5926 5927 u8 syndrome[0x20]; 5928 5929 u8 reserved_at_40[0x40]; 5930 }; 5931 5932 struct mlx5_ifc_modify_cong_status_in_bits { 5933 u8 opcode[0x10]; 5934 u8 reserved_at_10[0x10]; 5935 5936 u8 reserved_at_20[0x10]; 5937 u8 op_mod[0x10]; 5938 5939 u8 reserved_at_40[0x18]; 5940 u8 priority[0x4]; 5941 u8 cong_protocol[0x4]; 5942 5943 u8 enable[0x1]; 5944 u8 tag_enable[0x1]; 5945 u8 reserved_at_62[0x1e]; 5946 }; 5947 5948 struct mlx5_ifc_modify_cong_params_out_bits { 5949 u8 status[0x8]; 5950 u8 reserved_at_8[0x18]; 5951 5952 u8 syndrome[0x20]; 5953 5954 u8 reserved_at_40[0x40]; 5955 }; 5956 5957 struct mlx5_ifc_modify_cong_params_in_bits { 5958 u8 opcode[0x10]; 5959 u8 reserved_at_10[0x10]; 5960 5961 u8 reserved_at_20[0x10]; 5962 u8 op_mod[0x10]; 5963 5964 u8 reserved_at_40[0x1c]; 5965 u8 cong_protocol[0x4]; 5966 5967 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select; 5968 5969 u8 reserved_at_80[0x80]; 5970 5971 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 5972 }; 5973 5974 struct mlx5_ifc_manage_pages_out_bits { 5975 u8 status[0x8]; 5976 u8 reserved_at_8[0x18]; 5977 5978 u8 syndrome[0x20]; 5979 5980 u8 output_num_entries[0x20]; 5981 5982 u8 reserved_at_60[0x20]; 5983 5984 u8 pas[0][0x40]; 5985 }; 5986 5987 enum { 5988 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL = 0x0, 5989 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS = 0x1, 5990 MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES = 0x2, 5991 }; 5992 5993 struct mlx5_ifc_manage_pages_in_bits { 5994 u8 opcode[0x10]; 5995 u8 reserved_at_10[0x10]; 5996 5997 u8 reserved_at_20[0x10]; 5998 u8 op_mod[0x10]; 5999 6000 u8 embedded_cpu_function[0x1]; 6001 u8 reserved_at_41[0xf]; 6002 u8 function_id[0x10]; 6003 6004 u8 input_num_entries[0x20]; 6005 6006 u8 pas[0][0x40]; 6007 }; 6008 6009 struct mlx5_ifc_mad_ifc_out_bits { 6010 u8 status[0x8]; 6011 u8 reserved_at_8[0x18]; 6012 6013 u8 syndrome[0x20]; 6014 6015 u8 reserved_at_40[0x40]; 6016 6017 u8 response_mad_packet[256][0x8]; 6018 }; 6019 6020 struct mlx5_ifc_mad_ifc_in_bits { 6021 u8 opcode[0x10]; 6022 u8 reserved_at_10[0x10]; 6023 6024 u8 reserved_at_20[0x10]; 6025 u8 op_mod[0x10]; 6026 6027 u8 remote_lid[0x10]; 6028 u8 reserved_at_50[0x8]; 6029 u8 port[0x8]; 6030 6031 u8 reserved_at_60[0x20]; 6032 6033 u8 mad[256][0x8]; 6034 }; 6035 6036 struct mlx5_ifc_init_hca_out_bits { 6037 u8 status[0x8]; 6038 u8 reserved_at_8[0x18]; 6039 6040 u8 syndrome[0x20]; 6041 6042 u8 reserved_at_40[0x40]; 6043 }; 6044 6045 struct mlx5_ifc_init_hca_in_bits { 6046 u8 opcode[0x10]; 6047 u8 reserved_at_10[0x10]; 6048 6049 u8 reserved_at_20[0x10]; 6050 u8 op_mod[0x10]; 6051 6052 u8 reserved_at_40[0x40]; 6053 u8 sw_owner_id[4][0x20]; 6054 }; 6055 6056 struct mlx5_ifc_init2rtr_qp_out_bits { 6057 u8 status[0x8]; 6058 u8 reserved_at_8[0x18]; 6059 6060 u8 syndrome[0x20]; 6061 6062 u8 reserved_at_40[0x40]; 6063 }; 6064 6065 struct mlx5_ifc_init2rtr_qp_in_bits { 6066 u8 opcode[0x10]; 6067 u8 uid[0x10]; 6068 6069 u8 reserved_at_20[0x10]; 6070 u8 op_mod[0x10]; 6071 6072 u8 reserved_at_40[0x8]; 6073 u8 qpn[0x18]; 6074 6075 u8 reserved_at_60[0x20]; 6076 6077 u8 opt_param_mask[0x20]; 6078 6079 u8 reserved_at_a0[0x20]; 6080 6081 struct mlx5_ifc_qpc_bits qpc; 6082 6083 u8 reserved_at_800[0x80]; 6084 }; 6085 6086 struct mlx5_ifc_init2init_qp_out_bits { 6087 u8 status[0x8]; 6088 u8 reserved_at_8[0x18]; 6089 6090 u8 syndrome[0x20]; 6091 6092 u8 reserved_at_40[0x40]; 6093 }; 6094 6095 struct mlx5_ifc_init2init_qp_in_bits { 6096 u8 opcode[0x10]; 6097 u8 uid[0x10]; 6098 6099 u8 reserved_at_20[0x10]; 6100 u8 op_mod[0x10]; 6101 6102 u8 reserved_at_40[0x8]; 6103 u8 qpn[0x18]; 6104 6105 u8 reserved_at_60[0x20]; 6106 6107 u8 opt_param_mask[0x20]; 6108 6109 u8 reserved_at_a0[0x20]; 6110 6111 struct mlx5_ifc_qpc_bits qpc; 6112 6113 u8 reserved_at_800[0x80]; 6114 }; 6115 6116 struct mlx5_ifc_get_dropped_packet_log_out_bits { 6117 u8 status[0x8]; 6118 u8 reserved_at_8[0x18]; 6119 6120 u8 syndrome[0x20]; 6121 6122 u8 reserved_at_40[0x40]; 6123 6124 u8 packet_headers_log[128][0x8]; 6125 6126 u8 packet_syndrome[64][0x8]; 6127 }; 6128 6129 struct mlx5_ifc_get_dropped_packet_log_in_bits { 6130 u8 opcode[0x10]; 6131 u8 reserved_at_10[0x10]; 6132 6133 u8 reserved_at_20[0x10]; 6134 u8 op_mod[0x10]; 6135 6136 u8 reserved_at_40[0x40]; 6137 }; 6138 6139 struct mlx5_ifc_gen_eqe_in_bits { 6140 u8 opcode[0x10]; 6141 u8 reserved_at_10[0x10]; 6142 6143 u8 reserved_at_20[0x10]; 6144 u8 op_mod[0x10]; 6145 6146 u8 reserved_at_40[0x18]; 6147 u8 eq_number[0x8]; 6148 6149 u8 reserved_at_60[0x20]; 6150 6151 u8 eqe[64][0x8]; 6152 }; 6153 6154 struct mlx5_ifc_gen_eq_out_bits { 6155 u8 status[0x8]; 6156 u8 reserved_at_8[0x18]; 6157 6158 u8 syndrome[0x20]; 6159 6160 u8 reserved_at_40[0x40]; 6161 }; 6162 6163 struct mlx5_ifc_enable_hca_out_bits { 6164 u8 status[0x8]; 6165 u8 reserved_at_8[0x18]; 6166 6167 u8 syndrome[0x20]; 6168 6169 u8 reserved_at_40[0x20]; 6170 }; 6171 6172 struct mlx5_ifc_enable_hca_in_bits { 6173 u8 opcode[0x10]; 6174 u8 reserved_at_10[0x10]; 6175 6176 u8 reserved_at_20[0x10]; 6177 u8 op_mod[0x10]; 6178 6179 u8 embedded_cpu_function[0x1]; 6180 u8 reserved_at_41[0xf]; 6181 u8 function_id[0x10]; 6182 6183 u8 reserved_at_60[0x20]; 6184 }; 6185 6186 struct mlx5_ifc_drain_dct_out_bits { 6187 u8 status[0x8]; 6188 u8 reserved_at_8[0x18]; 6189 6190 u8 syndrome[0x20]; 6191 6192 u8 reserved_at_40[0x40]; 6193 }; 6194 6195 struct mlx5_ifc_drain_dct_in_bits { 6196 u8 opcode[0x10]; 6197 u8 uid[0x10]; 6198 6199 u8 reserved_at_20[0x10]; 6200 u8 op_mod[0x10]; 6201 6202 u8 reserved_at_40[0x8]; 6203 u8 dctn[0x18]; 6204 6205 u8 reserved_at_60[0x20]; 6206 }; 6207 6208 struct mlx5_ifc_disable_hca_out_bits { 6209 u8 status[0x8]; 6210 u8 reserved_at_8[0x18]; 6211 6212 u8 syndrome[0x20]; 6213 6214 u8 reserved_at_40[0x20]; 6215 }; 6216 6217 struct mlx5_ifc_disable_hca_in_bits { 6218 u8 opcode[0x10]; 6219 u8 reserved_at_10[0x10]; 6220 6221 u8 reserved_at_20[0x10]; 6222 u8 op_mod[0x10]; 6223 6224 u8 embedded_cpu_function[0x1]; 6225 u8 reserved_at_41[0xf]; 6226 u8 function_id[0x10]; 6227 6228 u8 reserved_at_60[0x20]; 6229 }; 6230 6231 struct mlx5_ifc_detach_from_mcg_out_bits { 6232 u8 status[0x8]; 6233 u8 reserved_at_8[0x18]; 6234 6235 u8 syndrome[0x20]; 6236 6237 u8 reserved_at_40[0x40]; 6238 }; 6239 6240 struct mlx5_ifc_detach_from_mcg_in_bits { 6241 u8 opcode[0x10]; 6242 u8 uid[0x10]; 6243 6244 u8 reserved_at_20[0x10]; 6245 u8 op_mod[0x10]; 6246 6247 u8 reserved_at_40[0x8]; 6248 u8 qpn[0x18]; 6249 6250 u8 reserved_at_60[0x20]; 6251 6252 u8 multicast_gid[16][0x8]; 6253 }; 6254 6255 struct mlx5_ifc_destroy_xrq_out_bits { 6256 u8 status[0x8]; 6257 u8 reserved_at_8[0x18]; 6258 6259 u8 syndrome[0x20]; 6260 6261 u8 reserved_at_40[0x40]; 6262 }; 6263 6264 struct mlx5_ifc_destroy_xrq_in_bits { 6265 u8 opcode[0x10]; 6266 u8 uid[0x10]; 6267 6268 u8 reserved_at_20[0x10]; 6269 u8 op_mod[0x10]; 6270 6271 u8 reserved_at_40[0x8]; 6272 u8 xrqn[0x18]; 6273 6274 u8 reserved_at_60[0x20]; 6275 }; 6276 6277 struct mlx5_ifc_destroy_xrc_srq_out_bits { 6278 u8 status[0x8]; 6279 u8 reserved_at_8[0x18]; 6280 6281 u8 syndrome[0x20]; 6282 6283 u8 reserved_at_40[0x40]; 6284 }; 6285 6286 struct mlx5_ifc_destroy_xrc_srq_in_bits { 6287 u8 opcode[0x10]; 6288 u8 uid[0x10]; 6289 6290 u8 reserved_at_20[0x10]; 6291 u8 op_mod[0x10]; 6292 6293 u8 reserved_at_40[0x8]; 6294 u8 xrc_srqn[0x18]; 6295 6296 u8 reserved_at_60[0x20]; 6297 }; 6298 6299 struct mlx5_ifc_destroy_tis_out_bits { 6300 u8 status[0x8]; 6301 u8 reserved_at_8[0x18]; 6302 6303 u8 syndrome[0x20]; 6304 6305 u8 reserved_at_40[0x40]; 6306 }; 6307 6308 struct mlx5_ifc_destroy_tis_in_bits { 6309 u8 opcode[0x10]; 6310 u8 uid[0x10]; 6311 6312 u8 reserved_at_20[0x10]; 6313 u8 op_mod[0x10]; 6314 6315 u8 reserved_at_40[0x8]; 6316 u8 tisn[0x18]; 6317 6318 u8 reserved_at_60[0x20]; 6319 }; 6320 6321 struct mlx5_ifc_destroy_tir_out_bits { 6322 u8 status[0x8]; 6323 u8 reserved_at_8[0x18]; 6324 6325 u8 syndrome[0x20]; 6326 6327 u8 reserved_at_40[0x40]; 6328 }; 6329 6330 struct mlx5_ifc_destroy_tir_in_bits { 6331 u8 opcode[0x10]; 6332 u8 uid[0x10]; 6333 6334 u8 reserved_at_20[0x10]; 6335 u8 op_mod[0x10]; 6336 6337 u8 reserved_at_40[0x8]; 6338 u8 tirn[0x18]; 6339 6340 u8 reserved_at_60[0x20]; 6341 }; 6342 6343 struct mlx5_ifc_destroy_srq_out_bits { 6344 u8 status[0x8]; 6345 u8 reserved_at_8[0x18]; 6346 6347 u8 syndrome[0x20]; 6348 6349 u8 reserved_at_40[0x40]; 6350 }; 6351 6352 struct mlx5_ifc_destroy_srq_in_bits { 6353 u8 opcode[0x10]; 6354 u8 uid[0x10]; 6355 6356 u8 reserved_at_20[0x10]; 6357 u8 op_mod[0x10]; 6358 6359 u8 reserved_at_40[0x8]; 6360 u8 srqn[0x18]; 6361 6362 u8 reserved_at_60[0x20]; 6363 }; 6364 6365 struct mlx5_ifc_destroy_sq_out_bits { 6366 u8 status[0x8]; 6367 u8 reserved_at_8[0x18]; 6368 6369 u8 syndrome[0x20]; 6370 6371 u8 reserved_at_40[0x40]; 6372 }; 6373 6374 struct mlx5_ifc_destroy_sq_in_bits { 6375 u8 opcode[0x10]; 6376 u8 uid[0x10]; 6377 6378 u8 reserved_at_20[0x10]; 6379 u8 op_mod[0x10]; 6380 6381 u8 reserved_at_40[0x8]; 6382 u8 sqn[0x18]; 6383 6384 u8 reserved_at_60[0x20]; 6385 }; 6386 6387 struct mlx5_ifc_destroy_scheduling_element_out_bits { 6388 u8 status[0x8]; 6389 u8 reserved_at_8[0x18]; 6390 6391 u8 syndrome[0x20]; 6392 6393 u8 reserved_at_40[0x1c0]; 6394 }; 6395 6396 struct mlx5_ifc_destroy_scheduling_element_in_bits { 6397 u8 opcode[0x10]; 6398 u8 reserved_at_10[0x10]; 6399 6400 u8 reserved_at_20[0x10]; 6401 u8 op_mod[0x10]; 6402 6403 u8 scheduling_hierarchy[0x8]; 6404 u8 reserved_at_48[0x18]; 6405 6406 u8 scheduling_element_id[0x20]; 6407 6408 u8 reserved_at_80[0x180]; 6409 }; 6410 6411 struct mlx5_ifc_destroy_rqt_out_bits { 6412 u8 status[0x8]; 6413 u8 reserved_at_8[0x18]; 6414 6415 u8 syndrome[0x20]; 6416 6417 u8 reserved_at_40[0x40]; 6418 }; 6419 6420 struct mlx5_ifc_destroy_rqt_in_bits { 6421 u8 opcode[0x10]; 6422 u8 uid[0x10]; 6423 6424 u8 reserved_at_20[0x10]; 6425 u8 op_mod[0x10]; 6426 6427 u8 reserved_at_40[0x8]; 6428 u8 rqtn[0x18]; 6429 6430 u8 reserved_at_60[0x20]; 6431 }; 6432 6433 struct mlx5_ifc_destroy_rq_out_bits { 6434 u8 status[0x8]; 6435 u8 reserved_at_8[0x18]; 6436 6437 u8 syndrome[0x20]; 6438 6439 u8 reserved_at_40[0x40]; 6440 }; 6441 6442 struct mlx5_ifc_destroy_rq_in_bits { 6443 u8 opcode[0x10]; 6444 u8 uid[0x10]; 6445 6446 u8 reserved_at_20[0x10]; 6447 u8 op_mod[0x10]; 6448 6449 u8 reserved_at_40[0x8]; 6450 u8 rqn[0x18]; 6451 6452 u8 reserved_at_60[0x20]; 6453 }; 6454 6455 struct mlx5_ifc_set_delay_drop_params_in_bits { 6456 u8 opcode[0x10]; 6457 u8 reserved_at_10[0x10]; 6458 6459 u8 reserved_at_20[0x10]; 6460 u8 op_mod[0x10]; 6461 6462 u8 reserved_at_40[0x20]; 6463 6464 u8 reserved_at_60[0x10]; 6465 u8 delay_drop_timeout[0x10]; 6466 }; 6467 6468 struct mlx5_ifc_set_delay_drop_params_out_bits { 6469 u8 status[0x8]; 6470 u8 reserved_at_8[0x18]; 6471 6472 u8 syndrome[0x20]; 6473 6474 u8 reserved_at_40[0x40]; 6475 }; 6476 6477 struct mlx5_ifc_destroy_rmp_out_bits { 6478 u8 status[0x8]; 6479 u8 reserved_at_8[0x18]; 6480 6481 u8 syndrome[0x20]; 6482 6483 u8 reserved_at_40[0x40]; 6484 }; 6485 6486 struct mlx5_ifc_destroy_rmp_in_bits { 6487 u8 opcode[0x10]; 6488 u8 uid[0x10]; 6489 6490 u8 reserved_at_20[0x10]; 6491 u8 op_mod[0x10]; 6492 6493 u8 reserved_at_40[0x8]; 6494 u8 rmpn[0x18]; 6495 6496 u8 reserved_at_60[0x20]; 6497 }; 6498 6499 struct mlx5_ifc_destroy_qp_out_bits { 6500 u8 status[0x8]; 6501 u8 reserved_at_8[0x18]; 6502 6503 u8 syndrome[0x20]; 6504 6505 u8 reserved_at_40[0x40]; 6506 }; 6507 6508 struct mlx5_ifc_destroy_qp_in_bits { 6509 u8 opcode[0x10]; 6510 u8 uid[0x10]; 6511 6512 u8 reserved_at_20[0x10]; 6513 u8 op_mod[0x10]; 6514 6515 u8 reserved_at_40[0x8]; 6516 u8 qpn[0x18]; 6517 6518 u8 reserved_at_60[0x20]; 6519 }; 6520 6521 struct mlx5_ifc_destroy_psv_out_bits { 6522 u8 status[0x8]; 6523 u8 reserved_at_8[0x18]; 6524 6525 u8 syndrome[0x20]; 6526 6527 u8 reserved_at_40[0x40]; 6528 }; 6529 6530 struct mlx5_ifc_destroy_psv_in_bits { 6531 u8 opcode[0x10]; 6532 u8 reserved_at_10[0x10]; 6533 6534 u8 reserved_at_20[0x10]; 6535 u8 op_mod[0x10]; 6536 6537 u8 reserved_at_40[0x8]; 6538 u8 psvn[0x18]; 6539 6540 u8 reserved_at_60[0x20]; 6541 }; 6542 6543 struct mlx5_ifc_destroy_mkey_out_bits { 6544 u8 status[0x8]; 6545 u8 reserved_at_8[0x18]; 6546 6547 u8 syndrome[0x20]; 6548 6549 u8 reserved_at_40[0x40]; 6550 }; 6551 6552 struct mlx5_ifc_destroy_mkey_in_bits { 6553 u8 opcode[0x10]; 6554 u8 reserved_at_10[0x10]; 6555 6556 u8 reserved_at_20[0x10]; 6557 u8 op_mod[0x10]; 6558 6559 u8 reserved_at_40[0x8]; 6560 u8 mkey_index[0x18]; 6561 6562 u8 reserved_at_60[0x20]; 6563 }; 6564 6565 struct mlx5_ifc_destroy_flow_table_out_bits { 6566 u8 status[0x8]; 6567 u8 reserved_at_8[0x18]; 6568 6569 u8 syndrome[0x20]; 6570 6571 u8 reserved_at_40[0x40]; 6572 }; 6573 6574 struct mlx5_ifc_destroy_flow_table_in_bits { 6575 u8 opcode[0x10]; 6576 u8 reserved_at_10[0x10]; 6577 6578 u8 reserved_at_20[0x10]; 6579 u8 op_mod[0x10]; 6580 6581 u8 other_vport[0x1]; 6582 u8 reserved_at_41[0xf]; 6583 u8 vport_number[0x10]; 6584 6585 u8 reserved_at_60[0x20]; 6586 6587 u8 table_type[0x8]; 6588 u8 reserved_at_88[0x18]; 6589 6590 u8 reserved_at_a0[0x8]; 6591 u8 table_id[0x18]; 6592 6593 u8 reserved_at_c0[0x140]; 6594 }; 6595 6596 struct mlx5_ifc_destroy_flow_group_out_bits { 6597 u8 status[0x8]; 6598 u8 reserved_at_8[0x18]; 6599 6600 u8 syndrome[0x20]; 6601 6602 u8 reserved_at_40[0x40]; 6603 }; 6604 6605 struct mlx5_ifc_destroy_flow_group_in_bits { 6606 u8 opcode[0x10]; 6607 u8 reserved_at_10[0x10]; 6608 6609 u8 reserved_at_20[0x10]; 6610 u8 op_mod[0x10]; 6611 6612 u8 other_vport[0x1]; 6613 u8 reserved_at_41[0xf]; 6614 u8 vport_number[0x10]; 6615 6616 u8 reserved_at_60[0x20]; 6617 6618 u8 table_type[0x8]; 6619 u8 reserved_at_88[0x18]; 6620 6621 u8 reserved_at_a0[0x8]; 6622 u8 table_id[0x18]; 6623 6624 u8 group_id[0x20]; 6625 6626 u8 reserved_at_e0[0x120]; 6627 }; 6628 6629 struct mlx5_ifc_destroy_eq_out_bits { 6630 u8 status[0x8]; 6631 u8 reserved_at_8[0x18]; 6632 6633 u8 syndrome[0x20]; 6634 6635 u8 reserved_at_40[0x40]; 6636 }; 6637 6638 struct mlx5_ifc_destroy_eq_in_bits { 6639 u8 opcode[0x10]; 6640 u8 reserved_at_10[0x10]; 6641 6642 u8 reserved_at_20[0x10]; 6643 u8 op_mod[0x10]; 6644 6645 u8 reserved_at_40[0x18]; 6646 u8 eq_number[0x8]; 6647 6648 u8 reserved_at_60[0x20]; 6649 }; 6650 6651 struct mlx5_ifc_destroy_dct_out_bits { 6652 u8 status[0x8]; 6653 u8 reserved_at_8[0x18]; 6654 6655 u8 syndrome[0x20]; 6656 6657 u8 reserved_at_40[0x40]; 6658 }; 6659 6660 struct mlx5_ifc_destroy_dct_in_bits { 6661 u8 opcode[0x10]; 6662 u8 uid[0x10]; 6663 6664 u8 reserved_at_20[0x10]; 6665 u8 op_mod[0x10]; 6666 6667 u8 reserved_at_40[0x8]; 6668 u8 dctn[0x18]; 6669 6670 u8 reserved_at_60[0x20]; 6671 }; 6672 6673 struct mlx5_ifc_destroy_cq_out_bits { 6674 u8 status[0x8]; 6675 u8 reserved_at_8[0x18]; 6676 6677 u8 syndrome[0x20]; 6678 6679 u8 reserved_at_40[0x40]; 6680 }; 6681 6682 struct mlx5_ifc_destroy_cq_in_bits { 6683 u8 opcode[0x10]; 6684 u8 uid[0x10]; 6685 6686 u8 reserved_at_20[0x10]; 6687 u8 op_mod[0x10]; 6688 6689 u8 reserved_at_40[0x8]; 6690 u8 cqn[0x18]; 6691 6692 u8 reserved_at_60[0x20]; 6693 }; 6694 6695 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits { 6696 u8 status[0x8]; 6697 u8 reserved_at_8[0x18]; 6698 6699 u8 syndrome[0x20]; 6700 6701 u8 reserved_at_40[0x40]; 6702 }; 6703 6704 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits { 6705 u8 opcode[0x10]; 6706 u8 reserved_at_10[0x10]; 6707 6708 u8 reserved_at_20[0x10]; 6709 u8 op_mod[0x10]; 6710 6711 u8 reserved_at_40[0x20]; 6712 6713 u8 reserved_at_60[0x10]; 6714 u8 vxlan_udp_port[0x10]; 6715 }; 6716 6717 struct mlx5_ifc_delete_l2_table_entry_out_bits { 6718 u8 status[0x8]; 6719 u8 reserved_at_8[0x18]; 6720 6721 u8 syndrome[0x20]; 6722 6723 u8 reserved_at_40[0x40]; 6724 }; 6725 6726 struct mlx5_ifc_delete_l2_table_entry_in_bits { 6727 u8 opcode[0x10]; 6728 u8 reserved_at_10[0x10]; 6729 6730 u8 reserved_at_20[0x10]; 6731 u8 op_mod[0x10]; 6732 6733 u8 reserved_at_40[0x60]; 6734 6735 u8 reserved_at_a0[0x8]; 6736 u8 table_index[0x18]; 6737 6738 u8 reserved_at_c0[0x140]; 6739 }; 6740 6741 struct mlx5_ifc_delete_fte_out_bits { 6742 u8 status[0x8]; 6743 u8 reserved_at_8[0x18]; 6744 6745 u8 syndrome[0x20]; 6746 6747 u8 reserved_at_40[0x40]; 6748 }; 6749 6750 struct mlx5_ifc_delete_fte_in_bits { 6751 u8 opcode[0x10]; 6752 u8 reserved_at_10[0x10]; 6753 6754 u8 reserved_at_20[0x10]; 6755 u8 op_mod[0x10]; 6756 6757 u8 other_vport[0x1]; 6758 u8 reserved_at_41[0xf]; 6759 u8 vport_number[0x10]; 6760 6761 u8 reserved_at_60[0x20]; 6762 6763 u8 table_type[0x8]; 6764 u8 reserved_at_88[0x18]; 6765 6766 u8 reserved_at_a0[0x8]; 6767 u8 table_id[0x18]; 6768 6769 u8 reserved_at_c0[0x40]; 6770 6771 u8 flow_index[0x20]; 6772 6773 u8 reserved_at_120[0xe0]; 6774 }; 6775 6776 struct mlx5_ifc_dealloc_xrcd_out_bits { 6777 u8 status[0x8]; 6778 u8 reserved_at_8[0x18]; 6779 6780 u8 syndrome[0x20]; 6781 6782 u8 reserved_at_40[0x40]; 6783 }; 6784 6785 struct mlx5_ifc_dealloc_xrcd_in_bits { 6786 u8 opcode[0x10]; 6787 u8 uid[0x10]; 6788 6789 u8 reserved_at_20[0x10]; 6790 u8 op_mod[0x10]; 6791 6792 u8 reserved_at_40[0x8]; 6793 u8 xrcd[0x18]; 6794 6795 u8 reserved_at_60[0x20]; 6796 }; 6797 6798 struct mlx5_ifc_dealloc_uar_out_bits { 6799 u8 status[0x8]; 6800 u8 reserved_at_8[0x18]; 6801 6802 u8 syndrome[0x20]; 6803 6804 u8 reserved_at_40[0x40]; 6805 }; 6806 6807 struct mlx5_ifc_dealloc_uar_in_bits { 6808 u8 opcode[0x10]; 6809 u8 reserved_at_10[0x10]; 6810 6811 u8 reserved_at_20[0x10]; 6812 u8 op_mod[0x10]; 6813 6814 u8 reserved_at_40[0x8]; 6815 u8 uar[0x18]; 6816 6817 u8 reserved_at_60[0x20]; 6818 }; 6819 6820 struct mlx5_ifc_dealloc_transport_domain_out_bits { 6821 u8 status[0x8]; 6822 u8 reserved_at_8[0x18]; 6823 6824 u8 syndrome[0x20]; 6825 6826 u8 reserved_at_40[0x40]; 6827 }; 6828 6829 struct mlx5_ifc_dealloc_transport_domain_in_bits { 6830 u8 opcode[0x10]; 6831 u8 uid[0x10]; 6832 6833 u8 reserved_at_20[0x10]; 6834 u8 op_mod[0x10]; 6835 6836 u8 reserved_at_40[0x8]; 6837 u8 transport_domain[0x18]; 6838 6839 u8 reserved_at_60[0x20]; 6840 }; 6841 6842 struct mlx5_ifc_dealloc_q_counter_out_bits { 6843 u8 status[0x8]; 6844 u8 reserved_at_8[0x18]; 6845 6846 u8 syndrome[0x20]; 6847 6848 u8 reserved_at_40[0x40]; 6849 }; 6850 6851 struct mlx5_ifc_dealloc_q_counter_in_bits { 6852 u8 opcode[0x10]; 6853 u8 reserved_at_10[0x10]; 6854 6855 u8 reserved_at_20[0x10]; 6856 u8 op_mod[0x10]; 6857 6858 u8 reserved_at_40[0x18]; 6859 u8 counter_set_id[0x8]; 6860 6861 u8 reserved_at_60[0x20]; 6862 }; 6863 6864 struct mlx5_ifc_dealloc_pd_out_bits { 6865 u8 status[0x8]; 6866 u8 reserved_at_8[0x18]; 6867 6868 u8 syndrome[0x20]; 6869 6870 u8 reserved_at_40[0x40]; 6871 }; 6872 6873 struct mlx5_ifc_dealloc_pd_in_bits { 6874 u8 opcode[0x10]; 6875 u8 uid[0x10]; 6876 6877 u8 reserved_at_20[0x10]; 6878 u8 op_mod[0x10]; 6879 6880 u8 reserved_at_40[0x8]; 6881 u8 pd[0x18]; 6882 6883 u8 reserved_at_60[0x20]; 6884 }; 6885 6886 struct mlx5_ifc_dealloc_flow_counter_out_bits { 6887 u8 status[0x8]; 6888 u8 reserved_at_8[0x18]; 6889 6890 u8 syndrome[0x20]; 6891 6892 u8 reserved_at_40[0x40]; 6893 }; 6894 6895 struct mlx5_ifc_dealloc_flow_counter_in_bits { 6896 u8 opcode[0x10]; 6897 u8 reserved_at_10[0x10]; 6898 6899 u8 reserved_at_20[0x10]; 6900 u8 op_mod[0x10]; 6901 6902 u8 flow_counter_id[0x20]; 6903 6904 u8 reserved_at_60[0x20]; 6905 }; 6906 6907 struct mlx5_ifc_create_xrq_out_bits { 6908 u8 status[0x8]; 6909 u8 reserved_at_8[0x18]; 6910 6911 u8 syndrome[0x20]; 6912 6913 u8 reserved_at_40[0x8]; 6914 u8 xrqn[0x18]; 6915 6916 u8 reserved_at_60[0x20]; 6917 }; 6918 6919 struct mlx5_ifc_create_xrq_in_bits { 6920 u8 opcode[0x10]; 6921 u8 uid[0x10]; 6922 6923 u8 reserved_at_20[0x10]; 6924 u8 op_mod[0x10]; 6925 6926 u8 reserved_at_40[0x40]; 6927 6928 struct mlx5_ifc_xrqc_bits xrq_context; 6929 }; 6930 6931 struct mlx5_ifc_create_xrc_srq_out_bits { 6932 u8 status[0x8]; 6933 u8 reserved_at_8[0x18]; 6934 6935 u8 syndrome[0x20]; 6936 6937 u8 reserved_at_40[0x8]; 6938 u8 xrc_srqn[0x18]; 6939 6940 u8 reserved_at_60[0x20]; 6941 }; 6942 6943 struct mlx5_ifc_create_xrc_srq_in_bits { 6944 u8 opcode[0x10]; 6945 u8 uid[0x10]; 6946 6947 u8 reserved_at_20[0x10]; 6948 u8 op_mod[0x10]; 6949 6950 u8 reserved_at_40[0x40]; 6951 6952 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 6953 6954 u8 reserved_at_280[0x60]; 6955 6956 u8 xrc_srq_umem_valid[0x1]; 6957 u8 reserved_at_2e1[0x1f]; 6958 6959 u8 reserved_at_300[0x580]; 6960 6961 u8 pas[0][0x40]; 6962 }; 6963 6964 struct mlx5_ifc_create_tis_out_bits { 6965 u8 status[0x8]; 6966 u8 reserved_at_8[0x18]; 6967 6968 u8 syndrome[0x20]; 6969 6970 u8 reserved_at_40[0x8]; 6971 u8 tisn[0x18]; 6972 6973 u8 reserved_at_60[0x20]; 6974 }; 6975 6976 struct mlx5_ifc_create_tis_in_bits { 6977 u8 opcode[0x10]; 6978 u8 uid[0x10]; 6979 6980 u8 reserved_at_20[0x10]; 6981 u8 op_mod[0x10]; 6982 6983 u8 reserved_at_40[0xc0]; 6984 6985 struct mlx5_ifc_tisc_bits ctx; 6986 }; 6987 6988 struct mlx5_ifc_create_tir_out_bits { 6989 u8 status[0x8]; 6990 u8 icm_address_63_40[0x18]; 6991 6992 u8 syndrome[0x20]; 6993 6994 u8 icm_address_39_32[0x8]; 6995 u8 tirn[0x18]; 6996 6997 u8 icm_address_31_0[0x20]; 6998 }; 6999 7000 struct mlx5_ifc_create_tir_in_bits { 7001 u8 opcode[0x10]; 7002 u8 uid[0x10]; 7003 7004 u8 reserved_at_20[0x10]; 7005 u8 op_mod[0x10]; 7006 7007 u8 reserved_at_40[0xc0]; 7008 7009 struct mlx5_ifc_tirc_bits ctx; 7010 }; 7011 7012 struct mlx5_ifc_create_srq_out_bits { 7013 u8 status[0x8]; 7014 u8 reserved_at_8[0x18]; 7015 7016 u8 syndrome[0x20]; 7017 7018 u8 reserved_at_40[0x8]; 7019 u8 srqn[0x18]; 7020 7021 u8 reserved_at_60[0x20]; 7022 }; 7023 7024 struct mlx5_ifc_create_srq_in_bits { 7025 u8 opcode[0x10]; 7026 u8 uid[0x10]; 7027 7028 u8 reserved_at_20[0x10]; 7029 u8 op_mod[0x10]; 7030 7031 u8 reserved_at_40[0x40]; 7032 7033 struct mlx5_ifc_srqc_bits srq_context_entry; 7034 7035 u8 reserved_at_280[0x600]; 7036 7037 u8 pas[0][0x40]; 7038 }; 7039 7040 struct mlx5_ifc_create_sq_out_bits { 7041 u8 status[0x8]; 7042 u8 reserved_at_8[0x18]; 7043 7044 u8 syndrome[0x20]; 7045 7046 u8 reserved_at_40[0x8]; 7047 u8 sqn[0x18]; 7048 7049 u8 reserved_at_60[0x20]; 7050 }; 7051 7052 struct mlx5_ifc_create_sq_in_bits { 7053 u8 opcode[0x10]; 7054 u8 uid[0x10]; 7055 7056 u8 reserved_at_20[0x10]; 7057 u8 op_mod[0x10]; 7058 7059 u8 reserved_at_40[0xc0]; 7060 7061 struct mlx5_ifc_sqc_bits ctx; 7062 }; 7063 7064 struct mlx5_ifc_create_scheduling_element_out_bits { 7065 u8 status[0x8]; 7066 u8 reserved_at_8[0x18]; 7067 7068 u8 syndrome[0x20]; 7069 7070 u8 reserved_at_40[0x40]; 7071 7072 u8 scheduling_element_id[0x20]; 7073 7074 u8 reserved_at_a0[0x160]; 7075 }; 7076 7077 struct mlx5_ifc_create_scheduling_element_in_bits { 7078 u8 opcode[0x10]; 7079 u8 reserved_at_10[0x10]; 7080 7081 u8 reserved_at_20[0x10]; 7082 u8 op_mod[0x10]; 7083 7084 u8 scheduling_hierarchy[0x8]; 7085 u8 reserved_at_48[0x18]; 7086 7087 u8 reserved_at_60[0xa0]; 7088 7089 struct mlx5_ifc_scheduling_context_bits scheduling_context; 7090 7091 u8 reserved_at_300[0x100]; 7092 }; 7093 7094 struct mlx5_ifc_create_rqt_out_bits { 7095 u8 status[0x8]; 7096 u8 reserved_at_8[0x18]; 7097 7098 u8 syndrome[0x20]; 7099 7100 u8 reserved_at_40[0x8]; 7101 u8 rqtn[0x18]; 7102 7103 u8 reserved_at_60[0x20]; 7104 }; 7105 7106 struct mlx5_ifc_create_rqt_in_bits { 7107 u8 opcode[0x10]; 7108 u8 uid[0x10]; 7109 7110 u8 reserved_at_20[0x10]; 7111 u8 op_mod[0x10]; 7112 7113 u8 reserved_at_40[0xc0]; 7114 7115 struct mlx5_ifc_rqtc_bits rqt_context; 7116 }; 7117 7118 struct mlx5_ifc_create_rq_out_bits { 7119 u8 status[0x8]; 7120 u8 reserved_at_8[0x18]; 7121 7122 u8 syndrome[0x20]; 7123 7124 u8 reserved_at_40[0x8]; 7125 u8 rqn[0x18]; 7126 7127 u8 reserved_at_60[0x20]; 7128 }; 7129 7130 struct mlx5_ifc_create_rq_in_bits { 7131 u8 opcode[0x10]; 7132 u8 uid[0x10]; 7133 7134 u8 reserved_at_20[0x10]; 7135 u8 op_mod[0x10]; 7136 7137 u8 reserved_at_40[0xc0]; 7138 7139 struct mlx5_ifc_rqc_bits ctx; 7140 }; 7141 7142 struct mlx5_ifc_create_rmp_out_bits { 7143 u8 status[0x8]; 7144 u8 reserved_at_8[0x18]; 7145 7146 u8 syndrome[0x20]; 7147 7148 u8 reserved_at_40[0x8]; 7149 u8 rmpn[0x18]; 7150 7151 u8 reserved_at_60[0x20]; 7152 }; 7153 7154 struct mlx5_ifc_create_rmp_in_bits { 7155 u8 opcode[0x10]; 7156 u8 uid[0x10]; 7157 7158 u8 reserved_at_20[0x10]; 7159 u8 op_mod[0x10]; 7160 7161 u8 reserved_at_40[0xc0]; 7162 7163 struct mlx5_ifc_rmpc_bits ctx; 7164 }; 7165 7166 struct mlx5_ifc_create_qp_out_bits { 7167 u8 status[0x8]; 7168 u8 reserved_at_8[0x18]; 7169 7170 u8 syndrome[0x20]; 7171 7172 u8 reserved_at_40[0x8]; 7173 u8 qpn[0x18]; 7174 7175 u8 reserved_at_60[0x20]; 7176 }; 7177 7178 struct mlx5_ifc_create_qp_in_bits { 7179 u8 opcode[0x10]; 7180 u8 uid[0x10]; 7181 7182 u8 reserved_at_20[0x10]; 7183 u8 op_mod[0x10]; 7184 7185 u8 reserved_at_40[0x40]; 7186 7187 u8 opt_param_mask[0x20]; 7188 7189 u8 reserved_at_a0[0x20]; 7190 7191 struct mlx5_ifc_qpc_bits qpc; 7192 7193 u8 reserved_at_800[0x60]; 7194 7195 u8 wq_umem_valid[0x1]; 7196 u8 reserved_at_861[0x1f]; 7197 7198 u8 pas[0][0x40]; 7199 }; 7200 7201 struct mlx5_ifc_create_psv_out_bits { 7202 u8 status[0x8]; 7203 u8 reserved_at_8[0x18]; 7204 7205 u8 syndrome[0x20]; 7206 7207 u8 reserved_at_40[0x40]; 7208 7209 u8 reserved_at_80[0x8]; 7210 u8 psv0_index[0x18]; 7211 7212 u8 reserved_at_a0[0x8]; 7213 u8 psv1_index[0x18]; 7214 7215 u8 reserved_at_c0[0x8]; 7216 u8 psv2_index[0x18]; 7217 7218 u8 reserved_at_e0[0x8]; 7219 u8 psv3_index[0x18]; 7220 }; 7221 7222 struct mlx5_ifc_create_psv_in_bits { 7223 u8 opcode[0x10]; 7224 u8 reserved_at_10[0x10]; 7225 7226 u8 reserved_at_20[0x10]; 7227 u8 op_mod[0x10]; 7228 7229 u8 num_psv[0x4]; 7230 u8 reserved_at_44[0x4]; 7231 u8 pd[0x18]; 7232 7233 u8 reserved_at_60[0x20]; 7234 }; 7235 7236 struct mlx5_ifc_create_mkey_out_bits { 7237 u8 status[0x8]; 7238 u8 reserved_at_8[0x18]; 7239 7240 u8 syndrome[0x20]; 7241 7242 u8 reserved_at_40[0x8]; 7243 u8 mkey_index[0x18]; 7244 7245 u8 reserved_at_60[0x20]; 7246 }; 7247 7248 struct mlx5_ifc_create_mkey_in_bits { 7249 u8 opcode[0x10]; 7250 u8 reserved_at_10[0x10]; 7251 7252 u8 reserved_at_20[0x10]; 7253 u8 op_mod[0x10]; 7254 7255 u8 reserved_at_40[0x20]; 7256 7257 u8 pg_access[0x1]; 7258 u8 mkey_umem_valid[0x1]; 7259 u8 reserved_at_62[0x1e]; 7260 7261 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 7262 7263 u8 reserved_at_280[0x80]; 7264 7265 u8 translations_octword_actual_size[0x20]; 7266 7267 u8 reserved_at_320[0x560]; 7268 7269 u8 klm_pas_mtt[0][0x20]; 7270 }; 7271 7272 struct mlx5_ifc_create_flow_table_out_bits { 7273 u8 status[0x8]; 7274 u8 reserved_at_8[0x18]; 7275 7276 u8 syndrome[0x20]; 7277 7278 u8 reserved_at_40[0x8]; 7279 u8 table_id[0x18]; 7280 7281 u8 reserved_at_60[0x20]; 7282 }; 7283 7284 struct mlx5_ifc_flow_table_context_bits { 7285 u8 reformat_en[0x1]; 7286 u8 decap_en[0x1]; 7287 u8 reserved_at_2[0x1]; 7288 u8 termination_table[0x1]; 7289 u8 table_miss_action[0x4]; 7290 u8 level[0x8]; 7291 u8 reserved_at_10[0x8]; 7292 u8 log_size[0x8]; 7293 7294 u8 reserved_at_20[0x8]; 7295 u8 table_miss_id[0x18]; 7296 7297 u8 reserved_at_40[0x8]; 7298 u8 lag_master_next_table_id[0x18]; 7299 7300 u8 reserved_at_60[0xe0]; 7301 }; 7302 7303 struct mlx5_ifc_create_flow_table_in_bits { 7304 u8 opcode[0x10]; 7305 u8 reserved_at_10[0x10]; 7306 7307 u8 reserved_at_20[0x10]; 7308 u8 op_mod[0x10]; 7309 7310 u8 other_vport[0x1]; 7311 u8 reserved_at_41[0xf]; 7312 u8 vport_number[0x10]; 7313 7314 u8 reserved_at_60[0x20]; 7315 7316 u8 table_type[0x8]; 7317 u8 reserved_at_88[0x18]; 7318 7319 u8 reserved_at_a0[0x20]; 7320 7321 struct mlx5_ifc_flow_table_context_bits flow_table_context; 7322 }; 7323 7324 struct mlx5_ifc_create_flow_group_out_bits { 7325 u8 status[0x8]; 7326 u8 reserved_at_8[0x18]; 7327 7328 u8 syndrome[0x20]; 7329 7330 u8 reserved_at_40[0x8]; 7331 u8 group_id[0x18]; 7332 7333 u8 reserved_at_60[0x20]; 7334 }; 7335 7336 enum { 7337 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 7338 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 7339 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 7340 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3, 7341 }; 7342 7343 struct mlx5_ifc_create_flow_group_in_bits { 7344 u8 opcode[0x10]; 7345 u8 reserved_at_10[0x10]; 7346 7347 u8 reserved_at_20[0x10]; 7348 u8 op_mod[0x10]; 7349 7350 u8 other_vport[0x1]; 7351 u8 reserved_at_41[0xf]; 7352 u8 vport_number[0x10]; 7353 7354 u8 reserved_at_60[0x20]; 7355 7356 u8 table_type[0x8]; 7357 u8 reserved_at_88[0x18]; 7358 7359 u8 reserved_at_a0[0x8]; 7360 u8 table_id[0x18]; 7361 7362 u8 source_eswitch_owner_vhca_id_valid[0x1]; 7363 7364 u8 reserved_at_c1[0x1f]; 7365 7366 u8 start_flow_index[0x20]; 7367 7368 u8 reserved_at_100[0x20]; 7369 7370 u8 end_flow_index[0x20]; 7371 7372 u8 reserved_at_140[0xa0]; 7373 7374 u8 reserved_at_1e0[0x18]; 7375 u8 match_criteria_enable[0x8]; 7376 7377 struct mlx5_ifc_fte_match_param_bits match_criteria; 7378 7379 u8 reserved_at_1200[0xe00]; 7380 }; 7381 7382 struct mlx5_ifc_create_eq_out_bits { 7383 u8 status[0x8]; 7384 u8 reserved_at_8[0x18]; 7385 7386 u8 syndrome[0x20]; 7387 7388 u8 reserved_at_40[0x18]; 7389 u8 eq_number[0x8]; 7390 7391 u8 reserved_at_60[0x20]; 7392 }; 7393 7394 struct mlx5_ifc_create_eq_in_bits { 7395 u8 opcode[0x10]; 7396 u8 uid[0x10]; 7397 7398 u8 reserved_at_20[0x10]; 7399 u8 op_mod[0x10]; 7400 7401 u8 reserved_at_40[0x40]; 7402 7403 struct mlx5_ifc_eqc_bits eq_context_entry; 7404 7405 u8 reserved_at_280[0x40]; 7406 7407 u8 event_bitmask[0x40]; 7408 7409 u8 reserved_at_300[0x580]; 7410 7411 u8 pas[0][0x40]; 7412 }; 7413 7414 struct mlx5_ifc_create_dct_out_bits { 7415 u8 status[0x8]; 7416 u8 reserved_at_8[0x18]; 7417 7418 u8 syndrome[0x20]; 7419 7420 u8 reserved_at_40[0x8]; 7421 u8 dctn[0x18]; 7422 7423 u8 reserved_at_60[0x20]; 7424 }; 7425 7426 struct mlx5_ifc_create_dct_in_bits { 7427 u8 opcode[0x10]; 7428 u8 uid[0x10]; 7429 7430 u8 reserved_at_20[0x10]; 7431 u8 op_mod[0x10]; 7432 7433 u8 reserved_at_40[0x40]; 7434 7435 struct mlx5_ifc_dctc_bits dct_context_entry; 7436 7437 u8 reserved_at_280[0x180]; 7438 }; 7439 7440 struct mlx5_ifc_create_cq_out_bits { 7441 u8 status[0x8]; 7442 u8 reserved_at_8[0x18]; 7443 7444 u8 syndrome[0x20]; 7445 7446 u8 reserved_at_40[0x8]; 7447 u8 cqn[0x18]; 7448 7449 u8 reserved_at_60[0x20]; 7450 }; 7451 7452 struct mlx5_ifc_create_cq_in_bits { 7453 u8 opcode[0x10]; 7454 u8 uid[0x10]; 7455 7456 u8 reserved_at_20[0x10]; 7457 u8 op_mod[0x10]; 7458 7459 u8 reserved_at_40[0x40]; 7460 7461 struct mlx5_ifc_cqc_bits cq_context; 7462 7463 u8 reserved_at_280[0x60]; 7464 7465 u8 cq_umem_valid[0x1]; 7466 u8 reserved_at_2e1[0x59f]; 7467 7468 u8 pas[0][0x40]; 7469 }; 7470 7471 struct mlx5_ifc_config_int_moderation_out_bits { 7472 u8 status[0x8]; 7473 u8 reserved_at_8[0x18]; 7474 7475 u8 syndrome[0x20]; 7476 7477 u8 reserved_at_40[0x4]; 7478 u8 min_delay[0xc]; 7479 u8 int_vector[0x10]; 7480 7481 u8 reserved_at_60[0x20]; 7482 }; 7483 7484 enum { 7485 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0, 7486 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1, 7487 }; 7488 7489 struct mlx5_ifc_config_int_moderation_in_bits { 7490 u8 opcode[0x10]; 7491 u8 reserved_at_10[0x10]; 7492 7493 u8 reserved_at_20[0x10]; 7494 u8 op_mod[0x10]; 7495 7496 u8 reserved_at_40[0x4]; 7497 u8 min_delay[0xc]; 7498 u8 int_vector[0x10]; 7499 7500 u8 reserved_at_60[0x20]; 7501 }; 7502 7503 struct mlx5_ifc_attach_to_mcg_out_bits { 7504 u8 status[0x8]; 7505 u8 reserved_at_8[0x18]; 7506 7507 u8 syndrome[0x20]; 7508 7509 u8 reserved_at_40[0x40]; 7510 }; 7511 7512 struct mlx5_ifc_attach_to_mcg_in_bits { 7513 u8 opcode[0x10]; 7514 u8 uid[0x10]; 7515 7516 u8 reserved_at_20[0x10]; 7517 u8 op_mod[0x10]; 7518 7519 u8 reserved_at_40[0x8]; 7520 u8 qpn[0x18]; 7521 7522 u8 reserved_at_60[0x20]; 7523 7524 u8 multicast_gid[16][0x8]; 7525 }; 7526 7527 struct mlx5_ifc_arm_xrq_out_bits { 7528 u8 status[0x8]; 7529 u8 reserved_at_8[0x18]; 7530 7531 u8 syndrome[0x20]; 7532 7533 u8 reserved_at_40[0x40]; 7534 }; 7535 7536 struct mlx5_ifc_arm_xrq_in_bits { 7537 u8 opcode[0x10]; 7538 u8 reserved_at_10[0x10]; 7539 7540 u8 reserved_at_20[0x10]; 7541 u8 op_mod[0x10]; 7542 7543 u8 reserved_at_40[0x8]; 7544 u8 xrqn[0x18]; 7545 7546 u8 reserved_at_60[0x10]; 7547 u8 lwm[0x10]; 7548 }; 7549 7550 struct mlx5_ifc_arm_xrc_srq_out_bits { 7551 u8 status[0x8]; 7552 u8 reserved_at_8[0x18]; 7553 7554 u8 syndrome[0x20]; 7555 7556 u8 reserved_at_40[0x40]; 7557 }; 7558 7559 enum { 7560 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1, 7561 }; 7562 7563 struct mlx5_ifc_arm_xrc_srq_in_bits { 7564 u8 opcode[0x10]; 7565 u8 uid[0x10]; 7566 7567 u8 reserved_at_20[0x10]; 7568 u8 op_mod[0x10]; 7569 7570 u8 reserved_at_40[0x8]; 7571 u8 xrc_srqn[0x18]; 7572 7573 u8 reserved_at_60[0x10]; 7574 u8 lwm[0x10]; 7575 }; 7576 7577 struct mlx5_ifc_arm_rq_out_bits { 7578 u8 status[0x8]; 7579 u8 reserved_at_8[0x18]; 7580 7581 u8 syndrome[0x20]; 7582 7583 u8 reserved_at_40[0x40]; 7584 }; 7585 7586 enum { 7587 MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1, 7588 MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2, 7589 }; 7590 7591 struct mlx5_ifc_arm_rq_in_bits { 7592 u8 opcode[0x10]; 7593 u8 uid[0x10]; 7594 7595 u8 reserved_at_20[0x10]; 7596 u8 op_mod[0x10]; 7597 7598 u8 reserved_at_40[0x8]; 7599 u8 srq_number[0x18]; 7600 7601 u8 reserved_at_60[0x10]; 7602 u8 lwm[0x10]; 7603 }; 7604 7605 struct mlx5_ifc_arm_dct_out_bits { 7606 u8 status[0x8]; 7607 u8 reserved_at_8[0x18]; 7608 7609 u8 syndrome[0x20]; 7610 7611 u8 reserved_at_40[0x40]; 7612 }; 7613 7614 struct mlx5_ifc_arm_dct_in_bits { 7615 u8 opcode[0x10]; 7616 u8 reserved_at_10[0x10]; 7617 7618 u8 reserved_at_20[0x10]; 7619 u8 op_mod[0x10]; 7620 7621 u8 reserved_at_40[0x8]; 7622 u8 dct_number[0x18]; 7623 7624 u8 reserved_at_60[0x20]; 7625 }; 7626 7627 struct mlx5_ifc_alloc_xrcd_out_bits { 7628 u8 status[0x8]; 7629 u8 reserved_at_8[0x18]; 7630 7631 u8 syndrome[0x20]; 7632 7633 u8 reserved_at_40[0x8]; 7634 u8 xrcd[0x18]; 7635 7636 u8 reserved_at_60[0x20]; 7637 }; 7638 7639 struct mlx5_ifc_alloc_xrcd_in_bits { 7640 u8 opcode[0x10]; 7641 u8 uid[0x10]; 7642 7643 u8 reserved_at_20[0x10]; 7644 u8 op_mod[0x10]; 7645 7646 u8 reserved_at_40[0x40]; 7647 }; 7648 7649 struct mlx5_ifc_alloc_uar_out_bits { 7650 u8 status[0x8]; 7651 u8 reserved_at_8[0x18]; 7652 7653 u8 syndrome[0x20]; 7654 7655 u8 reserved_at_40[0x8]; 7656 u8 uar[0x18]; 7657 7658 u8 reserved_at_60[0x20]; 7659 }; 7660 7661 struct mlx5_ifc_alloc_uar_in_bits { 7662 u8 opcode[0x10]; 7663 u8 reserved_at_10[0x10]; 7664 7665 u8 reserved_at_20[0x10]; 7666 u8 op_mod[0x10]; 7667 7668 u8 reserved_at_40[0x40]; 7669 }; 7670 7671 struct mlx5_ifc_alloc_transport_domain_out_bits { 7672 u8 status[0x8]; 7673 u8 reserved_at_8[0x18]; 7674 7675 u8 syndrome[0x20]; 7676 7677 u8 reserved_at_40[0x8]; 7678 u8 transport_domain[0x18]; 7679 7680 u8 reserved_at_60[0x20]; 7681 }; 7682 7683 struct mlx5_ifc_alloc_transport_domain_in_bits { 7684 u8 opcode[0x10]; 7685 u8 uid[0x10]; 7686 7687 u8 reserved_at_20[0x10]; 7688 u8 op_mod[0x10]; 7689 7690 u8 reserved_at_40[0x40]; 7691 }; 7692 7693 struct mlx5_ifc_alloc_q_counter_out_bits { 7694 u8 status[0x8]; 7695 u8 reserved_at_8[0x18]; 7696 7697 u8 syndrome[0x20]; 7698 7699 u8 reserved_at_40[0x18]; 7700 u8 counter_set_id[0x8]; 7701 7702 u8 reserved_at_60[0x20]; 7703 }; 7704 7705 struct mlx5_ifc_alloc_q_counter_in_bits { 7706 u8 opcode[0x10]; 7707 u8 uid[0x10]; 7708 7709 u8 reserved_at_20[0x10]; 7710 u8 op_mod[0x10]; 7711 7712 u8 reserved_at_40[0x40]; 7713 }; 7714 7715 struct mlx5_ifc_alloc_pd_out_bits { 7716 u8 status[0x8]; 7717 u8 reserved_at_8[0x18]; 7718 7719 u8 syndrome[0x20]; 7720 7721 u8 reserved_at_40[0x8]; 7722 u8 pd[0x18]; 7723 7724 u8 reserved_at_60[0x20]; 7725 }; 7726 7727 struct mlx5_ifc_alloc_pd_in_bits { 7728 u8 opcode[0x10]; 7729 u8 uid[0x10]; 7730 7731 u8 reserved_at_20[0x10]; 7732 u8 op_mod[0x10]; 7733 7734 u8 reserved_at_40[0x40]; 7735 }; 7736 7737 struct mlx5_ifc_alloc_flow_counter_out_bits { 7738 u8 status[0x8]; 7739 u8 reserved_at_8[0x18]; 7740 7741 u8 syndrome[0x20]; 7742 7743 u8 flow_counter_id[0x20]; 7744 7745 u8 reserved_at_60[0x20]; 7746 }; 7747 7748 struct mlx5_ifc_alloc_flow_counter_in_bits { 7749 u8 opcode[0x10]; 7750 u8 reserved_at_10[0x10]; 7751 7752 u8 reserved_at_20[0x10]; 7753 u8 op_mod[0x10]; 7754 7755 u8 reserved_at_40[0x40]; 7756 }; 7757 7758 struct mlx5_ifc_add_vxlan_udp_dport_out_bits { 7759 u8 status[0x8]; 7760 u8 reserved_at_8[0x18]; 7761 7762 u8 syndrome[0x20]; 7763 7764 u8 reserved_at_40[0x40]; 7765 }; 7766 7767 struct mlx5_ifc_add_vxlan_udp_dport_in_bits { 7768 u8 opcode[0x10]; 7769 u8 reserved_at_10[0x10]; 7770 7771 u8 reserved_at_20[0x10]; 7772 u8 op_mod[0x10]; 7773 7774 u8 reserved_at_40[0x20]; 7775 7776 u8 reserved_at_60[0x10]; 7777 u8 vxlan_udp_port[0x10]; 7778 }; 7779 7780 struct mlx5_ifc_set_pp_rate_limit_out_bits { 7781 u8 status[0x8]; 7782 u8 reserved_at_8[0x18]; 7783 7784 u8 syndrome[0x20]; 7785 7786 u8 reserved_at_40[0x40]; 7787 }; 7788 7789 struct mlx5_ifc_set_pp_rate_limit_in_bits { 7790 u8 opcode[0x10]; 7791 u8 reserved_at_10[0x10]; 7792 7793 u8 reserved_at_20[0x10]; 7794 u8 op_mod[0x10]; 7795 7796 u8 reserved_at_40[0x10]; 7797 u8 rate_limit_index[0x10]; 7798 7799 u8 reserved_at_60[0x20]; 7800 7801 u8 rate_limit[0x20]; 7802 7803 u8 burst_upper_bound[0x20]; 7804 7805 u8 reserved_at_c0[0x10]; 7806 u8 typical_packet_size[0x10]; 7807 7808 u8 reserved_at_e0[0x120]; 7809 }; 7810 7811 struct mlx5_ifc_access_register_out_bits { 7812 u8 status[0x8]; 7813 u8 reserved_at_8[0x18]; 7814 7815 u8 syndrome[0x20]; 7816 7817 u8 reserved_at_40[0x40]; 7818 7819 u8 register_data[0][0x20]; 7820 }; 7821 7822 enum { 7823 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0, 7824 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1, 7825 }; 7826 7827 struct mlx5_ifc_access_register_in_bits { 7828 u8 opcode[0x10]; 7829 u8 reserved_at_10[0x10]; 7830 7831 u8 reserved_at_20[0x10]; 7832 u8 op_mod[0x10]; 7833 7834 u8 reserved_at_40[0x10]; 7835 u8 register_id[0x10]; 7836 7837 u8 argument[0x20]; 7838 7839 u8 register_data[0][0x20]; 7840 }; 7841 7842 struct mlx5_ifc_sltp_reg_bits { 7843 u8 status[0x4]; 7844 u8 version[0x4]; 7845 u8 local_port[0x8]; 7846 u8 pnat[0x2]; 7847 u8 reserved_at_12[0x2]; 7848 u8 lane[0x4]; 7849 u8 reserved_at_18[0x8]; 7850 7851 u8 reserved_at_20[0x20]; 7852 7853 u8 reserved_at_40[0x7]; 7854 u8 polarity[0x1]; 7855 u8 ob_tap0[0x8]; 7856 u8 ob_tap1[0x8]; 7857 u8 ob_tap2[0x8]; 7858 7859 u8 reserved_at_60[0xc]; 7860 u8 ob_preemp_mode[0x4]; 7861 u8 ob_reg[0x8]; 7862 u8 ob_bias[0x8]; 7863 7864 u8 reserved_at_80[0x20]; 7865 }; 7866 7867 struct mlx5_ifc_slrg_reg_bits { 7868 u8 status[0x4]; 7869 u8 version[0x4]; 7870 u8 local_port[0x8]; 7871 u8 pnat[0x2]; 7872 u8 reserved_at_12[0x2]; 7873 u8 lane[0x4]; 7874 u8 reserved_at_18[0x8]; 7875 7876 u8 time_to_link_up[0x10]; 7877 u8 reserved_at_30[0xc]; 7878 u8 grade_lane_speed[0x4]; 7879 7880 u8 grade_version[0x8]; 7881 u8 grade[0x18]; 7882 7883 u8 reserved_at_60[0x4]; 7884 u8 height_grade_type[0x4]; 7885 u8 height_grade[0x18]; 7886 7887 u8 height_dz[0x10]; 7888 u8 height_dv[0x10]; 7889 7890 u8 reserved_at_a0[0x10]; 7891 u8 height_sigma[0x10]; 7892 7893 u8 reserved_at_c0[0x20]; 7894 7895 u8 reserved_at_e0[0x4]; 7896 u8 phase_grade_type[0x4]; 7897 u8 phase_grade[0x18]; 7898 7899 u8 reserved_at_100[0x8]; 7900 u8 phase_eo_pos[0x8]; 7901 u8 reserved_at_110[0x8]; 7902 u8 phase_eo_neg[0x8]; 7903 7904 u8 ffe_set_tested[0x10]; 7905 u8 test_errors_per_lane[0x10]; 7906 }; 7907 7908 struct mlx5_ifc_pvlc_reg_bits { 7909 u8 reserved_at_0[0x8]; 7910 u8 local_port[0x8]; 7911 u8 reserved_at_10[0x10]; 7912 7913 u8 reserved_at_20[0x1c]; 7914 u8 vl_hw_cap[0x4]; 7915 7916 u8 reserved_at_40[0x1c]; 7917 u8 vl_admin[0x4]; 7918 7919 u8 reserved_at_60[0x1c]; 7920 u8 vl_operational[0x4]; 7921 }; 7922 7923 struct mlx5_ifc_pude_reg_bits { 7924 u8 swid[0x8]; 7925 u8 local_port[0x8]; 7926 u8 reserved_at_10[0x4]; 7927 u8 admin_status[0x4]; 7928 u8 reserved_at_18[0x4]; 7929 u8 oper_status[0x4]; 7930 7931 u8 reserved_at_20[0x60]; 7932 }; 7933 7934 struct mlx5_ifc_ptys_reg_bits { 7935 u8 reserved_at_0[0x1]; 7936 u8 an_disable_admin[0x1]; 7937 u8 an_disable_cap[0x1]; 7938 u8 reserved_at_3[0x5]; 7939 u8 local_port[0x8]; 7940 u8 reserved_at_10[0xd]; 7941 u8 proto_mask[0x3]; 7942 7943 u8 an_status[0x4]; 7944 u8 reserved_at_24[0x1c]; 7945 7946 u8 ext_eth_proto_capability[0x20]; 7947 7948 u8 eth_proto_capability[0x20]; 7949 7950 u8 ib_link_width_capability[0x10]; 7951 u8 ib_proto_capability[0x10]; 7952 7953 u8 ext_eth_proto_admin[0x20]; 7954 7955 u8 eth_proto_admin[0x20]; 7956 7957 u8 ib_link_width_admin[0x10]; 7958 u8 ib_proto_admin[0x10]; 7959 7960 u8 ext_eth_proto_oper[0x20]; 7961 7962 u8 eth_proto_oper[0x20]; 7963 7964 u8 ib_link_width_oper[0x10]; 7965 u8 ib_proto_oper[0x10]; 7966 7967 u8 reserved_at_160[0x1c]; 7968 u8 connector_type[0x4]; 7969 7970 u8 eth_proto_lp_advertise[0x20]; 7971 7972 u8 reserved_at_1a0[0x60]; 7973 }; 7974 7975 struct mlx5_ifc_mlcr_reg_bits { 7976 u8 reserved_at_0[0x8]; 7977 u8 local_port[0x8]; 7978 u8 reserved_at_10[0x20]; 7979 7980 u8 beacon_duration[0x10]; 7981 u8 reserved_at_40[0x10]; 7982 7983 u8 beacon_remain[0x10]; 7984 }; 7985 7986 struct mlx5_ifc_ptas_reg_bits { 7987 u8 reserved_at_0[0x20]; 7988 7989 u8 algorithm_options[0x10]; 7990 u8 reserved_at_30[0x4]; 7991 u8 repetitions_mode[0x4]; 7992 u8 num_of_repetitions[0x8]; 7993 7994 u8 grade_version[0x8]; 7995 u8 height_grade_type[0x4]; 7996 u8 phase_grade_type[0x4]; 7997 u8 height_grade_weight[0x8]; 7998 u8 phase_grade_weight[0x8]; 7999 8000 u8 gisim_measure_bits[0x10]; 8001 u8 adaptive_tap_measure_bits[0x10]; 8002 8003 u8 ber_bath_high_error_threshold[0x10]; 8004 u8 ber_bath_mid_error_threshold[0x10]; 8005 8006 u8 ber_bath_low_error_threshold[0x10]; 8007 u8 one_ratio_high_threshold[0x10]; 8008 8009 u8 one_ratio_high_mid_threshold[0x10]; 8010 u8 one_ratio_low_mid_threshold[0x10]; 8011 8012 u8 one_ratio_low_threshold[0x10]; 8013 u8 ndeo_error_threshold[0x10]; 8014 8015 u8 mixer_offset_step_size[0x10]; 8016 u8 reserved_at_110[0x8]; 8017 u8 mix90_phase_for_voltage_bath[0x8]; 8018 8019 u8 mixer_offset_start[0x10]; 8020 u8 mixer_offset_end[0x10]; 8021 8022 u8 reserved_at_140[0x15]; 8023 u8 ber_test_time[0xb]; 8024 }; 8025 8026 struct mlx5_ifc_pspa_reg_bits { 8027 u8 swid[0x8]; 8028 u8 local_port[0x8]; 8029 u8 sub_port[0x8]; 8030 u8 reserved_at_18[0x8]; 8031 8032 u8 reserved_at_20[0x20]; 8033 }; 8034 8035 struct mlx5_ifc_pqdr_reg_bits { 8036 u8 reserved_at_0[0x8]; 8037 u8 local_port[0x8]; 8038 u8 reserved_at_10[0x5]; 8039 u8 prio[0x3]; 8040 u8 reserved_at_18[0x6]; 8041 u8 mode[0x2]; 8042 8043 u8 reserved_at_20[0x20]; 8044 8045 u8 reserved_at_40[0x10]; 8046 u8 min_threshold[0x10]; 8047 8048 u8 reserved_at_60[0x10]; 8049 u8 max_threshold[0x10]; 8050 8051 u8 reserved_at_80[0x10]; 8052 u8 mark_probability_denominator[0x10]; 8053 8054 u8 reserved_at_a0[0x60]; 8055 }; 8056 8057 struct mlx5_ifc_ppsc_reg_bits { 8058 u8 reserved_at_0[0x8]; 8059 u8 local_port[0x8]; 8060 u8 reserved_at_10[0x10]; 8061 8062 u8 reserved_at_20[0x60]; 8063 8064 u8 reserved_at_80[0x1c]; 8065 u8 wrps_admin[0x4]; 8066 8067 u8 reserved_at_a0[0x1c]; 8068 u8 wrps_status[0x4]; 8069 8070 u8 reserved_at_c0[0x8]; 8071 u8 up_threshold[0x8]; 8072 u8 reserved_at_d0[0x8]; 8073 u8 down_threshold[0x8]; 8074 8075 u8 reserved_at_e0[0x20]; 8076 8077 u8 reserved_at_100[0x1c]; 8078 u8 srps_admin[0x4]; 8079 8080 u8 reserved_at_120[0x1c]; 8081 u8 srps_status[0x4]; 8082 8083 u8 reserved_at_140[0x40]; 8084 }; 8085 8086 struct mlx5_ifc_pplr_reg_bits { 8087 u8 reserved_at_0[0x8]; 8088 u8 local_port[0x8]; 8089 u8 reserved_at_10[0x10]; 8090 8091 u8 reserved_at_20[0x8]; 8092 u8 lb_cap[0x8]; 8093 u8 reserved_at_30[0x8]; 8094 u8 lb_en[0x8]; 8095 }; 8096 8097 struct mlx5_ifc_pplm_reg_bits { 8098 u8 reserved_at_0[0x8]; 8099 u8 local_port[0x8]; 8100 u8 reserved_at_10[0x10]; 8101 8102 u8 reserved_at_20[0x20]; 8103 8104 u8 port_profile_mode[0x8]; 8105 u8 static_port_profile[0x8]; 8106 u8 active_port_profile[0x8]; 8107 u8 reserved_at_58[0x8]; 8108 8109 u8 retransmission_active[0x8]; 8110 u8 fec_mode_active[0x18]; 8111 8112 u8 rs_fec_correction_bypass_cap[0x4]; 8113 u8 reserved_at_84[0x8]; 8114 u8 fec_override_cap_56g[0x4]; 8115 u8 fec_override_cap_100g[0x4]; 8116 u8 fec_override_cap_50g[0x4]; 8117 u8 fec_override_cap_25g[0x4]; 8118 u8 fec_override_cap_10g_40g[0x4]; 8119 8120 u8 rs_fec_correction_bypass_admin[0x4]; 8121 u8 reserved_at_a4[0x8]; 8122 u8 fec_override_admin_56g[0x4]; 8123 u8 fec_override_admin_100g[0x4]; 8124 u8 fec_override_admin_50g[0x4]; 8125 u8 fec_override_admin_25g[0x4]; 8126 u8 fec_override_admin_10g_40g[0x4]; 8127 }; 8128 8129 struct mlx5_ifc_ppcnt_reg_bits { 8130 u8 swid[0x8]; 8131 u8 local_port[0x8]; 8132 u8 pnat[0x2]; 8133 u8 reserved_at_12[0x8]; 8134 u8 grp[0x6]; 8135 8136 u8 clr[0x1]; 8137 u8 reserved_at_21[0x1c]; 8138 u8 prio_tc[0x3]; 8139 8140 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set; 8141 }; 8142 8143 struct mlx5_ifc_mpein_reg_bits { 8144 u8 reserved_at_0[0x2]; 8145 u8 depth[0x6]; 8146 u8 pcie_index[0x8]; 8147 u8 node[0x8]; 8148 u8 reserved_at_18[0x8]; 8149 8150 u8 capability_mask[0x20]; 8151 8152 u8 reserved_at_40[0x8]; 8153 u8 link_width_enabled[0x8]; 8154 u8 link_speed_enabled[0x10]; 8155 8156 u8 lane0_physical_position[0x8]; 8157 u8 link_width_active[0x8]; 8158 u8 link_speed_active[0x10]; 8159 8160 u8 num_of_pfs[0x10]; 8161 u8 num_of_vfs[0x10]; 8162 8163 u8 bdf0[0x10]; 8164 u8 reserved_at_b0[0x10]; 8165 8166 u8 max_read_request_size[0x4]; 8167 u8 max_payload_size[0x4]; 8168 u8 reserved_at_c8[0x5]; 8169 u8 pwr_status[0x3]; 8170 u8 port_type[0x4]; 8171 u8 reserved_at_d4[0xb]; 8172 u8 lane_reversal[0x1]; 8173 8174 u8 reserved_at_e0[0x14]; 8175 u8 pci_power[0xc]; 8176 8177 u8 reserved_at_100[0x20]; 8178 8179 u8 device_status[0x10]; 8180 u8 port_state[0x8]; 8181 u8 reserved_at_138[0x8]; 8182 8183 u8 reserved_at_140[0x10]; 8184 u8 receiver_detect_result[0x10]; 8185 8186 u8 reserved_at_160[0x20]; 8187 }; 8188 8189 struct mlx5_ifc_mpcnt_reg_bits { 8190 u8 reserved_at_0[0x8]; 8191 u8 pcie_index[0x8]; 8192 u8 reserved_at_10[0xa]; 8193 u8 grp[0x6]; 8194 8195 u8 clr[0x1]; 8196 u8 reserved_at_21[0x1f]; 8197 8198 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set; 8199 }; 8200 8201 struct mlx5_ifc_ppad_reg_bits { 8202 u8 reserved_at_0[0x3]; 8203 u8 single_mac[0x1]; 8204 u8 reserved_at_4[0x4]; 8205 u8 local_port[0x8]; 8206 u8 mac_47_32[0x10]; 8207 8208 u8 mac_31_0[0x20]; 8209 8210 u8 reserved_at_40[0x40]; 8211 }; 8212 8213 struct mlx5_ifc_pmtu_reg_bits { 8214 u8 reserved_at_0[0x8]; 8215 u8 local_port[0x8]; 8216 u8 reserved_at_10[0x10]; 8217 8218 u8 max_mtu[0x10]; 8219 u8 reserved_at_30[0x10]; 8220 8221 u8 admin_mtu[0x10]; 8222 u8 reserved_at_50[0x10]; 8223 8224 u8 oper_mtu[0x10]; 8225 u8 reserved_at_70[0x10]; 8226 }; 8227 8228 struct mlx5_ifc_pmpr_reg_bits { 8229 u8 reserved_at_0[0x8]; 8230 u8 module[0x8]; 8231 u8 reserved_at_10[0x10]; 8232 8233 u8 reserved_at_20[0x18]; 8234 u8 attenuation_5g[0x8]; 8235 8236 u8 reserved_at_40[0x18]; 8237 u8 attenuation_7g[0x8]; 8238 8239 u8 reserved_at_60[0x18]; 8240 u8 attenuation_12g[0x8]; 8241 }; 8242 8243 struct mlx5_ifc_pmpe_reg_bits { 8244 u8 reserved_at_0[0x8]; 8245 u8 module[0x8]; 8246 u8 reserved_at_10[0xc]; 8247 u8 module_status[0x4]; 8248 8249 u8 reserved_at_20[0x60]; 8250 }; 8251 8252 struct mlx5_ifc_pmpc_reg_bits { 8253 u8 module_state_updated[32][0x8]; 8254 }; 8255 8256 struct mlx5_ifc_pmlpn_reg_bits { 8257 u8 reserved_at_0[0x4]; 8258 u8 mlpn_status[0x4]; 8259 u8 local_port[0x8]; 8260 u8 reserved_at_10[0x10]; 8261 8262 u8 e[0x1]; 8263 u8 reserved_at_21[0x1f]; 8264 }; 8265 8266 struct mlx5_ifc_pmlp_reg_bits { 8267 u8 rxtx[0x1]; 8268 u8 reserved_at_1[0x7]; 8269 u8 local_port[0x8]; 8270 u8 reserved_at_10[0x8]; 8271 u8 width[0x8]; 8272 8273 u8 lane0_module_mapping[0x20]; 8274 8275 u8 lane1_module_mapping[0x20]; 8276 8277 u8 lane2_module_mapping[0x20]; 8278 8279 u8 lane3_module_mapping[0x20]; 8280 8281 u8 reserved_at_a0[0x160]; 8282 }; 8283 8284 struct mlx5_ifc_pmaos_reg_bits { 8285 u8 reserved_at_0[0x8]; 8286 u8 module[0x8]; 8287 u8 reserved_at_10[0x4]; 8288 u8 admin_status[0x4]; 8289 u8 reserved_at_18[0x4]; 8290 u8 oper_status[0x4]; 8291 8292 u8 ase[0x1]; 8293 u8 ee[0x1]; 8294 u8 reserved_at_22[0x1c]; 8295 u8 e[0x2]; 8296 8297 u8 reserved_at_40[0x40]; 8298 }; 8299 8300 struct mlx5_ifc_plpc_reg_bits { 8301 u8 reserved_at_0[0x4]; 8302 u8 profile_id[0xc]; 8303 u8 reserved_at_10[0x4]; 8304 u8 proto_mask[0x4]; 8305 u8 reserved_at_18[0x8]; 8306 8307 u8 reserved_at_20[0x10]; 8308 u8 lane_speed[0x10]; 8309 8310 u8 reserved_at_40[0x17]; 8311 u8 lpbf[0x1]; 8312 u8 fec_mode_policy[0x8]; 8313 8314 u8 retransmission_capability[0x8]; 8315 u8 fec_mode_capability[0x18]; 8316 8317 u8 retransmission_support_admin[0x8]; 8318 u8 fec_mode_support_admin[0x18]; 8319 8320 u8 retransmission_request_admin[0x8]; 8321 u8 fec_mode_request_admin[0x18]; 8322 8323 u8 reserved_at_c0[0x80]; 8324 }; 8325 8326 struct mlx5_ifc_plib_reg_bits { 8327 u8 reserved_at_0[0x8]; 8328 u8 local_port[0x8]; 8329 u8 reserved_at_10[0x8]; 8330 u8 ib_port[0x8]; 8331 8332 u8 reserved_at_20[0x60]; 8333 }; 8334 8335 struct mlx5_ifc_plbf_reg_bits { 8336 u8 reserved_at_0[0x8]; 8337 u8 local_port[0x8]; 8338 u8 reserved_at_10[0xd]; 8339 u8 lbf_mode[0x3]; 8340 8341 u8 reserved_at_20[0x20]; 8342 }; 8343 8344 struct mlx5_ifc_pipg_reg_bits { 8345 u8 reserved_at_0[0x8]; 8346 u8 local_port[0x8]; 8347 u8 reserved_at_10[0x10]; 8348 8349 u8 dic[0x1]; 8350 u8 reserved_at_21[0x19]; 8351 u8 ipg[0x4]; 8352 u8 reserved_at_3e[0x2]; 8353 }; 8354 8355 struct mlx5_ifc_pifr_reg_bits { 8356 u8 reserved_at_0[0x8]; 8357 u8 local_port[0x8]; 8358 u8 reserved_at_10[0x10]; 8359 8360 u8 reserved_at_20[0xe0]; 8361 8362 u8 port_filter[8][0x20]; 8363 8364 u8 port_filter_update_en[8][0x20]; 8365 }; 8366 8367 struct mlx5_ifc_pfcc_reg_bits { 8368 u8 reserved_at_0[0x8]; 8369 u8 local_port[0x8]; 8370 u8 reserved_at_10[0xb]; 8371 u8 ppan_mask_n[0x1]; 8372 u8 minor_stall_mask[0x1]; 8373 u8 critical_stall_mask[0x1]; 8374 u8 reserved_at_1e[0x2]; 8375 8376 u8 ppan[0x4]; 8377 u8 reserved_at_24[0x4]; 8378 u8 prio_mask_tx[0x8]; 8379 u8 reserved_at_30[0x8]; 8380 u8 prio_mask_rx[0x8]; 8381 8382 u8 pptx[0x1]; 8383 u8 aptx[0x1]; 8384 u8 pptx_mask_n[0x1]; 8385 u8 reserved_at_43[0x5]; 8386 u8 pfctx[0x8]; 8387 u8 reserved_at_50[0x10]; 8388 8389 u8 pprx[0x1]; 8390 u8 aprx[0x1]; 8391 u8 pprx_mask_n[0x1]; 8392 u8 reserved_at_63[0x5]; 8393 u8 pfcrx[0x8]; 8394 u8 reserved_at_70[0x10]; 8395 8396 u8 device_stall_minor_watermark[0x10]; 8397 u8 device_stall_critical_watermark[0x10]; 8398 8399 u8 reserved_at_a0[0x60]; 8400 }; 8401 8402 struct mlx5_ifc_pelc_reg_bits { 8403 u8 op[0x4]; 8404 u8 reserved_at_4[0x4]; 8405 u8 local_port[0x8]; 8406 u8 reserved_at_10[0x10]; 8407 8408 u8 op_admin[0x8]; 8409 u8 op_capability[0x8]; 8410 u8 op_request[0x8]; 8411 u8 op_active[0x8]; 8412 8413 u8 admin[0x40]; 8414 8415 u8 capability[0x40]; 8416 8417 u8 request[0x40]; 8418 8419 u8 active[0x40]; 8420 8421 u8 reserved_at_140[0x80]; 8422 }; 8423 8424 struct mlx5_ifc_peir_reg_bits { 8425 u8 reserved_at_0[0x8]; 8426 u8 local_port[0x8]; 8427 u8 reserved_at_10[0x10]; 8428 8429 u8 reserved_at_20[0xc]; 8430 u8 error_count[0x4]; 8431 u8 reserved_at_30[0x10]; 8432 8433 u8 reserved_at_40[0xc]; 8434 u8 lane[0x4]; 8435 u8 reserved_at_50[0x8]; 8436 u8 error_type[0x8]; 8437 }; 8438 8439 struct mlx5_ifc_mpegc_reg_bits { 8440 u8 reserved_at_0[0x30]; 8441 u8 field_select[0x10]; 8442 8443 u8 tx_overflow_sense[0x1]; 8444 u8 mark_cqe[0x1]; 8445 u8 mark_cnp[0x1]; 8446 u8 reserved_at_43[0x1b]; 8447 u8 tx_lossy_overflow_oper[0x2]; 8448 8449 u8 reserved_at_60[0x100]; 8450 }; 8451 8452 struct mlx5_ifc_pcam_enhanced_features_bits { 8453 u8 reserved_at_0[0x6d]; 8454 u8 rx_icrc_encapsulated_counter[0x1]; 8455 u8 reserved_at_6e[0x4]; 8456 u8 ptys_extended_ethernet[0x1]; 8457 u8 reserved_at_73[0x3]; 8458 u8 pfcc_mask[0x1]; 8459 u8 reserved_at_77[0x3]; 8460 u8 per_lane_error_counters[0x1]; 8461 u8 rx_buffer_fullness_counters[0x1]; 8462 u8 ptys_connector_type[0x1]; 8463 u8 reserved_at_7d[0x1]; 8464 u8 ppcnt_discard_group[0x1]; 8465 u8 ppcnt_statistical_group[0x1]; 8466 }; 8467 8468 struct mlx5_ifc_pcam_regs_5000_to_507f_bits { 8469 u8 port_access_reg_cap_mask_127_to_96[0x20]; 8470 u8 port_access_reg_cap_mask_95_to_64[0x20]; 8471 8472 u8 port_access_reg_cap_mask_63_to_36[0x1c]; 8473 u8 pplm[0x1]; 8474 u8 port_access_reg_cap_mask_34_to_32[0x3]; 8475 8476 u8 port_access_reg_cap_mask_31_to_13[0x13]; 8477 u8 pbmc[0x1]; 8478 u8 pptb[0x1]; 8479 u8 port_access_reg_cap_mask_10_to_09[0x2]; 8480 u8 ppcnt[0x1]; 8481 u8 port_access_reg_cap_mask_07_to_00[0x8]; 8482 }; 8483 8484 struct mlx5_ifc_pcam_reg_bits { 8485 u8 reserved_at_0[0x8]; 8486 u8 feature_group[0x8]; 8487 u8 reserved_at_10[0x8]; 8488 u8 access_reg_group[0x8]; 8489 8490 u8 reserved_at_20[0x20]; 8491 8492 union { 8493 struct mlx5_ifc_pcam_regs_5000_to_507f_bits regs_5000_to_507f; 8494 u8 reserved_at_0[0x80]; 8495 } port_access_reg_cap_mask; 8496 8497 u8 reserved_at_c0[0x80]; 8498 8499 union { 8500 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features; 8501 u8 reserved_at_0[0x80]; 8502 } feature_cap_mask; 8503 8504 u8 reserved_at_1c0[0xc0]; 8505 }; 8506 8507 struct mlx5_ifc_mcam_enhanced_features_bits { 8508 u8 reserved_at_0[0x6e]; 8509 u8 pci_status_and_power[0x1]; 8510 u8 reserved_at_6f[0x5]; 8511 u8 mark_tx_action_cnp[0x1]; 8512 u8 mark_tx_action_cqe[0x1]; 8513 u8 dynamic_tx_overflow[0x1]; 8514 u8 reserved_at_77[0x4]; 8515 u8 pcie_outbound_stalled[0x1]; 8516 u8 tx_overflow_buffer_pkt[0x1]; 8517 u8 mtpps_enh_out_per_adj[0x1]; 8518 u8 mtpps_fs[0x1]; 8519 u8 pcie_performance_group[0x1]; 8520 }; 8521 8522 struct mlx5_ifc_mcam_access_reg_bits { 8523 u8 reserved_at_0[0x1c]; 8524 u8 mcda[0x1]; 8525 u8 mcc[0x1]; 8526 u8 mcqi[0x1]; 8527 u8 reserved_at_1f[0x1]; 8528 8529 u8 regs_95_to_87[0x9]; 8530 u8 mpegc[0x1]; 8531 u8 regs_85_to_68[0x12]; 8532 u8 tracer_registers[0x4]; 8533 8534 u8 regs_63_to_32[0x20]; 8535 u8 regs_31_to_0[0x20]; 8536 }; 8537 8538 struct mlx5_ifc_mcam_reg_bits { 8539 u8 reserved_at_0[0x8]; 8540 u8 feature_group[0x8]; 8541 u8 reserved_at_10[0x8]; 8542 u8 access_reg_group[0x8]; 8543 8544 u8 reserved_at_20[0x20]; 8545 8546 union { 8547 struct mlx5_ifc_mcam_access_reg_bits access_regs; 8548 u8 reserved_at_0[0x80]; 8549 } mng_access_reg_cap_mask; 8550 8551 u8 reserved_at_c0[0x80]; 8552 8553 union { 8554 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features; 8555 u8 reserved_at_0[0x80]; 8556 } mng_feature_cap_mask; 8557 8558 u8 reserved_at_1c0[0x80]; 8559 }; 8560 8561 struct mlx5_ifc_qcam_access_reg_cap_mask { 8562 u8 qcam_access_reg_cap_mask_127_to_20[0x6C]; 8563 u8 qpdpm[0x1]; 8564 u8 qcam_access_reg_cap_mask_18_to_4[0x0F]; 8565 u8 qdpm[0x1]; 8566 u8 qpts[0x1]; 8567 u8 qcap[0x1]; 8568 u8 qcam_access_reg_cap_mask_0[0x1]; 8569 }; 8570 8571 struct mlx5_ifc_qcam_qos_feature_cap_mask { 8572 u8 qcam_qos_feature_cap_mask_127_to_1[0x7F]; 8573 u8 qpts_trust_both[0x1]; 8574 }; 8575 8576 struct mlx5_ifc_qcam_reg_bits { 8577 u8 reserved_at_0[0x8]; 8578 u8 feature_group[0x8]; 8579 u8 reserved_at_10[0x8]; 8580 u8 access_reg_group[0x8]; 8581 u8 reserved_at_20[0x20]; 8582 8583 union { 8584 struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap; 8585 u8 reserved_at_0[0x80]; 8586 } qos_access_reg_cap_mask; 8587 8588 u8 reserved_at_c0[0x80]; 8589 8590 union { 8591 struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap; 8592 u8 reserved_at_0[0x80]; 8593 } qos_feature_cap_mask; 8594 8595 u8 reserved_at_1c0[0x80]; 8596 }; 8597 8598 struct mlx5_ifc_core_dump_reg_bits { 8599 u8 reserved_at_0[0x18]; 8600 u8 core_dump_type[0x8]; 8601 8602 u8 reserved_at_20[0x30]; 8603 u8 vhca_id[0x10]; 8604 8605 u8 reserved_at_60[0x8]; 8606 u8 qpn[0x18]; 8607 u8 reserved_at_80[0x180]; 8608 }; 8609 8610 struct mlx5_ifc_pcap_reg_bits { 8611 u8 reserved_at_0[0x8]; 8612 u8 local_port[0x8]; 8613 u8 reserved_at_10[0x10]; 8614 8615 u8 port_capability_mask[4][0x20]; 8616 }; 8617 8618 struct mlx5_ifc_paos_reg_bits { 8619 u8 swid[0x8]; 8620 u8 local_port[0x8]; 8621 u8 reserved_at_10[0x4]; 8622 u8 admin_status[0x4]; 8623 u8 reserved_at_18[0x4]; 8624 u8 oper_status[0x4]; 8625 8626 u8 ase[0x1]; 8627 u8 ee[0x1]; 8628 u8 reserved_at_22[0x1c]; 8629 u8 e[0x2]; 8630 8631 u8 reserved_at_40[0x40]; 8632 }; 8633 8634 struct mlx5_ifc_pamp_reg_bits { 8635 u8 reserved_at_0[0x8]; 8636 u8 opamp_group[0x8]; 8637 u8 reserved_at_10[0xc]; 8638 u8 opamp_group_type[0x4]; 8639 8640 u8 start_index[0x10]; 8641 u8 reserved_at_30[0x4]; 8642 u8 num_of_indices[0xc]; 8643 8644 u8 index_data[18][0x10]; 8645 }; 8646 8647 struct mlx5_ifc_pcmr_reg_bits { 8648 u8 reserved_at_0[0x8]; 8649 u8 local_port[0x8]; 8650 u8 reserved_at_10[0x10]; 8651 u8 entropy_force_cap[0x1]; 8652 u8 entropy_calc_cap[0x1]; 8653 u8 entropy_gre_calc_cap[0x1]; 8654 u8 reserved_at_23[0x1b]; 8655 u8 fcs_cap[0x1]; 8656 u8 reserved_at_3f[0x1]; 8657 u8 entropy_force[0x1]; 8658 u8 entropy_calc[0x1]; 8659 u8 entropy_gre_calc[0x1]; 8660 u8 reserved_at_43[0x1b]; 8661 u8 fcs_chk[0x1]; 8662 u8 reserved_at_5f[0x1]; 8663 }; 8664 8665 struct mlx5_ifc_lane_2_module_mapping_bits { 8666 u8 reserved_at_0[0x6]; 8667 u8 rx_lane[0x2]; 8668 u8 reserved_at_8[0x6]; 8669 u8 tx_lane[0x2]; 8670 u8 reserved_at_10[0x8]; 8671 u8 module[0x8]; 8672 }; 8673 8674 struct mlx5_ifc_bufferx_reg_bits { 8675 u8 reserved_at_0[0x6]; 8676 u8 lossy[0x1]; 8677 u8 epsb[0x1]; 8678 u8 reserved_at_8[0xc]; 8679 u8 size[0xc]; 8680 8681 u8 xoff_threshold[0x10]; 8682 u8 xon_threshold[0x10]; 8683 }; 8684 8685 struct mlx5_ifc_set_node_in_bits { 8686 u8 node_description[64][0x8]; 8687 }; 8688 8689 struct mlx5_ifc_register_power_settings_bits { 8690 u8 reserved_at_0[0x18]; 8691 u8 power_settings_level[0x8]; 8692 8693 u8 reserved_at_20[0x60]; 8694 }; 8695 8696 struct mlx5_ifc_register_host_endianness_bits { 8697 u8 he[0x1]; 8698 u8 reserved_at_1[0x1f]; 8699 8700 u8 reserved_at_20[0x60]; 8701 }; 8702 8703 struct mlx5_ifc_umr_pointer_desc_argument_bits { 8704 u8 reserved_at_0[0x20]; 8705 8706 u8 mkey[0x20]; 8707 8708 u8 addressh_63_32[0x20]; 8709 8710 u8 addressl_31_0[0x20]; 8711 }; 8712 8713 struct mlx5_ifc_ud_adrs_vector_bits { 8714 u8 dc_key[0x40]; 8715 8716 u8 ext[0x1]; 8717 u8 reserved_at_41[0x7]; 8718 u8 destination_qp_dct[0x18]; 8719 8720 u8 static_rate[0x4]; 8721 u8 sl_eth_prio[0x4]; 8722 u8 fl[0x1]; 8723 u8 mlid[0x7]; 8724 u8 rlid_udp_sport[0x10]; 8725 8726 u8 reserved_at_80[0x20]; 8727 8728 u8 rmac_47_16[0x20]; 8729 8730 u8 rmac_15_0[0x10]; 8731 u8 tclass[0x8]; 8732 u8 hop_limit[0x8]; 8733 8734 u8 reserved_at_e0[0x1]; 8735 u8 grh[0x1]; 8736 u8 reserved_at_e2[0x2]; 8737 u8 src_addr_index[0x8]; 8738 u8 flow_label[0x14]; 8739 8740 u8 rgid_rip[16][0x8]; 8741 }; 8742 8743 struct mlx5_ifc_pages_req_event_bits { 8744 u8 reserved_at_0[0x10]; 8745 u8 function_id[0x10]; 8746 8747 u8 num_pages[0x20]; 8748 8749 u8 reserved_at_40[0xa0]; 8750 }; 8751 8752 struct mlx5_ifc_eqe_bits { 8753 u8 reserved_at_0[0x8]; 8754 u8 event_type[0x8]; 8755 u8 reserved_at_10[0x8]; 8756 u8 event_sub_type[0x8]; 8757 8758 u8 reserved_at_20[0xe0]; 8759 8760 union mlx5_ifc_event_auto_bits event_data; 8761 8762 u8 reserved_at_1e0[0x10]; 8763 u8 signature[0x8]; 8764 u8 reserved_at_1f8[0x7]; 8765 u8 owner[0x1]; 8766 }; 8767 8768 enum { 8769 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7, 8770 }; 8771 8772 struct mlx5_ifc_cmd_queue_entry_bits { 8773 u8 type[0x8]; 8774 u8 reserved_at_8[0x18]; 8775 8776 u8 input_length[0x20]; 8777 8778 u8 input_mailbox_pointer_63_32[0x20]; 8779 8780 u8 input_mailbox_pointer_31_9[0x17]; 8781 u8 reserved_at_77[0x9]; 8782 8783 u8 command_input_inline_data[16][0x8]; 8784 8785 u8 command_output_inline_data[16][0x8]; 8786 8787 u8 output_mailbox_pointer_63_32[0x20]; 8788 8789 u8 output_mailbox_pointer_31_9[0x17]; 8790 u8 reserved_at_1b7[0x9]; 8791 8792 u8 output_length[0x20]; 8793 8794 u8 token[0x8]; 8795 u8 signature[0x8]; 8796 u8 reserved_at_1f0[0x8]; 8797 u8 status[0x7]; 8798 u8 ownership[0x1]; 8799 }; 8800 8801 struct mlx5_ifc_cmd_out_bits { 8802 u8 status[0x8]; 8803 u8 reserved_at_8[0x18]; 8804 8805 u8 syndrome[0x20]; 8806 8807 u8 command_output[0x20]; 8808 }; 8809 8810 struct mlx5_ifc_cmd_in_bits { 8811 u8 opcode[0x10]; 8812 u8 reserved_at_10[0x10]; 8813 8814 u8 reserved_at_20[0x10]; 8815 u8 op_mod[0x10]; 8816 8817 u8 command[0][0x20]; 8818 }; 8819 8820 struct mlx5_ifc_cmd_if_box_bits { 8821 u8 mailbox_data[512][0x8]; 8822 8823 u8 reserved_at_1000[0x180]; 8824 8825 u8 next_pointer_63_32[0x20]; 8826 8827 u8 next_pointer_31_10[0x16]; 8828 u8 reserved_at_11b6[0xa]; 8829 8830 u8 block_number[0x20]; 8831 8832 u8 reserved_at_11e0[0x8]; 8833 u8 token[0x8]; 8834 u8 ctrl_signature[0x8]; 8835 u8 signature[0x8]; 8836 }; 8837 8838 struct mlx5_ifc_mtt_bits { 8839 u8 ptag_63_32[0x20]; 8840 8841 u8 ptag_31_8[0x18]; 8842 u8 reserved_at_38[0x6]; 8843 u8 wr_en[0x1]; 8844 u8 rd_en[0x1]; 8845 }; 8846 8847 struct mlx5_ifc_query_wol_rol_out_bits { 8848 u8 status[0x8]; 8849 u8 reserved_at_8[0x18]; 8850 8851 u8 syndrome[0x20]; 8852 8853 u8 reserved_at_40[0x10]; 8854 u8 rol_mode[0x8]; 8855 u8 wol_mode[0x8]; 8856 8857 u8 reserved_at_60[0x20]; 8858 }; 8859 8860 struct mlx5_ifc_query_wol_rol_in_bits { 8861 u8 opcode[0x10]; 8862 u8 reserved_at_10[0x10]; 8863 8864 u8 reserved_at_20[0x10]; 8865 u8 op_mod[0x10]; 8866 8867 u8 reserved_at_40[0x40]; 8868 }; 8869 8870 struct mlx5_ifc_set_wol_rol_out_bits { 8871 u8 status[0x8]; 8872 u8 reserved_at_8[0x18]; 8873 8874 u8 syndrome[0x20]; 8875 8876 u8 reserved_at_40[0x40]; 8877 }; 8878 8879 struct mlx5_ifc_set_wol_rol_in_bits { 8880 u8 opcode[0x10]; 8881 u8 reserved_at_10[0x10]; 8882 8883 u8 reserved_at_20[0x10]; 8884 u8 op_mod[0x10]; 8885 8886 u8 rol_mode_valid[0x1]; 8887 u8 wol_mode_valid[0x1]; 8888 u8 reserved_at_42[0xe]; 8889 u8 rol_mode[0x8]; 8890 u8 wol_mode[0x8]; 8891 8892 u8 reserved_at_60[0x20]; 8893 }; 8894 8895 enum { 8896 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0, 8897 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1, 8898 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2, 8899 }; 8900 8901 enum { 8902 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0, 8903 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1, 8904 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2, 8905 }; 8906 8907 enum { 8908 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR = 0x1, 8909 MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC = 0x7, 8910 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR = 0x8, 8911 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR = 0x9, 8912 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR = 0xa, 8913 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR = 0xb, 8914 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN = 0xc, 8915 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR = 0xd, 8916 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV = 0xe, 8917 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR = 0xf, 8918 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR = 0x10, 8919 }; 8920 8921 struct mlx5_ifc_initial_seg_bits { 8922 u8 fw_rev_minor[0x10]; 8923 u8 fw_rev_major[0x10]; 8924 8925 u8 cmd_interface_rev[0x10]; 8926 u8 fw_rev_subminor[0x10]; 8927 8928 u8 reserved_at_40[0x40]; 8929 8930 u8 cmdq_phy_addr_63_32[0x20]; 8931 8932 u8 cmdq_phy_addr_31_12[0x14]; 8933 u8 reserved_at_b4[0x2]; 8934 u8 nic_interface[0x2]; 8935 u8 log_cmdq_size[0x4]; 8936 u8 log_cmdq_stride[0x4]; 8937 8938 u8 command_doorbell_vector[0x20]; 8939 8940 u8 reserved_at_e0[0xf00]; 8941 8942 u8 initializing[0x1]; 8943 u8 reserved_at_fe1[0x4]; 8944 u8 nic_interface_supported[0x3]; 8945 u8 embedded_cpu[0x1]; 8946 u8 reserved_at_fe9[0x17]; 8947 8948 struct mlx5_ifc_health_buffer_bits health_buffer; 8949 8950 u8 no_dram_nic_offset[0x20]; 8951 8952 u8 reserved_at_1220[0x6e40]; 8953 8954 u8 reserved_at_8060[0x1f]; 8955 u8 clear_int[0x1]; 8956 8957 u8 health_syndrome[0x8]; 8958 u8 health_counter[0x18]; 8959 8960 u8 reserved_at_80a0[0x17fc0]; 8961 }; 8962 8963 struct mlx5_ifc_mtpps_reg_bits { 8964 u8 reserved_at_0[0xc]; 8965 u8 cap_number_of_pps_pins[0x4]; 8966 u8 reserved_at_10[0x4]; 8967 u8 cap_max_num_of_pps_in_pins[0x4]; 8968 u8 reserved_at_18[0x4]; 8969 u8 cap_max_num_of_pps_out_pins[0x4]; 8970 8971 u8 reserved_at_20[0x24]; 8972 u8 cap_pin_3_mode[0x4]; 8973 u8 reserved_at_48[0x4]; 8974 u8 cap_pin_2_mode[0x4]; 8975 u8 reserved_at_50[0x4]; 8976 u8 cap_pin_1_mode[0x4]; 8977 u8 reserved_at_58[0x4]; 8978 u8 cap_pin_0_mode[0x4]; 8979 8980 u8 reserved_at_60[0x4]; 8981 u8 cap_pin_7_mode[0x4]; 8982 u8 reserved_at_68[0x4]; 8983 u8 cap_pin_6_mode[0x4]; 8984 u8 reserved_at_70[0x4]; 8985 u8 cap_pin_5_mode[0x4]; 8986 u8 reserved_at_78[0x4]; 8987 u8 cap_pin_4_mode[0x4]; 8988 8989 u8 field_select[0x20]; 8990 u8 reserved_at_a0[0x60]; 8991 8992 u8 enable[0x1]; 8993 u8 reserved_at_101[0xb]; 8994 u8 pattern[0x4]; 8995 u8 reserved_at_110[0x4]; 8996 u8 pin_mode[0x4]; 8997 u8 pin[0x8]; 8998 8999 u8 reserved_at_120[0x20]; 9000 9001 u8 time_stamp[0x40]; 9002 9003 u8 out_pulse_duration[0x10]; 9004 u8 out_periodic_adjustment[0x10]; 9005 u8 enhanced_out_periodic_adjustment[0x20]; 9006 9007 u8 reserved_at_1c0[0x20]; 9008 }; 9009 9010 struct mlx5_ifc_mtppse_reg_bits { 9011 u8 reserved_at_0[0x18]; 9012 u8 pin[0x8]; 9013 u8 event_arm[0x1]; 9014 u8 reserved_at_21[0x1b]; 9015 u8 event_generation_mode[0x4]; 9016 u8 reserved_at_40[0x40]; 9017 }; 9018 9019 struct mlx5_ifc_mcqi_cap_bits { 9020 u8 supported_info_bitmask[0x20]; 9021 9022 u8 component_size[0x20]; 9023 9024 u8 max_component_size[0x20]; 9025 9026 u8 log_mcda_word_size[0x4]; 9027 u8 reserved_at_64[0xc]; 9028 u8 mcda_max_write_size[0x10]; 9029 9030 u8 rd_en[0x1]; 9031 u8 reserved_at_81[0x1]; 9032 u8 match_chip_id[0x1]; 9033 u8 match_psid[0x1]; 9034 u8 check_user_timestamp[0x1]; 9035 u8 match_base_guid_mac[0x1]; 9036 u8 reserved_at_86[0x1a]; 9037 }; 9038 9039 struct mlx5_ifc_mcqi_reg_bits { 9040 u8 read_pending_component[0x1]; 9041 u8 reserved_at_1[0xf]; 9042 u8 component_index[0x10]; 9043 9044 u8 reserved_at_20[0x20]; 9045 9046 u8 reserved_at_40[0x1b]; 9047 u8 info_type[0x5]; 9048 9049 u8 info_size[0x20]; 9050 9051 u8 offset[0x20]; 9052 9053 u8 reserved_at_a0[0x10]; 9054 u8 data_size[0x10]; 9055 9056 u8 data[0][0x20]; 9057 }; 9058 9059 struct mlx5_ifc_mcc_reg_bits { 9060 u8 reserved_at_0[0x4]; 9061 u8 time_elapsed_since_last_cmd[0xc]; 9062 u8 reserved_at_10[0x8]; 9063 u8 instruction[0x8]; 9064 9065 u8 reserved_at_20[0x10]; 9066 u8 component_index[0x10]; 9067 9068 u8 reserved_at_40[0x8]; 9069 u8 update_handle[0x18]; 9070 9071 u8 handle_owner_type[0x4]; 9072 u8 handle_owner_host_id[0x4]; 9073 u8 reserved_at_68[0x1]; 9074 u8 control_progress[0x7]; 9075 u8 error_code[0x8]; 9076 u8 reserved_at_78[0x4]; 9077 u8 control_state[0x4]; 9078 9079 u8 component_size[0x20]; 9080 9081 u8 reserved_at_a0[0x60]; 9082 }; 9083 9084 struct mlx5_ifc_mcda_reg_bits { 9085 u8 reserved_at_0[0x8]; 9086 u8 update_handle[0x18]; 9087 9088 u8 offset[0x20]; 9089 9090 u8 reserved_at_40[0x10]; 9091 u8 size[0x10]; 9092 9093 u8 reserved_at_60[0x20]; 9094 9095 u8 data[0][0x20]; 9096 }; 9097 9098 union mlx5_ifc_ports_control_registers_document_bits { 9099 struct mlx5_ifc_bufferx_reg_bits bufferx_reg; 9100 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 9101 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 9102 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 9103 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 9104 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 9105 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 9106 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout; 9107 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping; 9108 struct mlx5_ifc_pamp_reg_bits pamp_reg; 9109 struct mlx5_ifc_paos_reg_bits paos_reg; 9110 struct mlx5_ifc_pcap_reg_bits pcap_reg; 9111 struct mlx5_ifc_peir_reg_bits peir_reg; 9112 struct mlx5_ifc_pelc_reg_bits pelc_reg; 9113 struct mlx5_ifc_pfcc_reg_bits pfcc_reg; 9114 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 9115 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 9116 struct mlx5_ifc_pifr_reg_bits pifr_reg; 9117 struct mlx5_ifc_pipg_reg_bits pipg_reg; 9118 struct mlx5_ifc_plbf_reg_bits plbf_reg; 9119 struct mlx5_ifc_plib_reg_bits plib_reg; 9120 struct mlx5_ifc_plpc_reg_bits plpc_reg; 9121 struct mlx5_ifc_pmaos_reg_bits pmaos_reg; 9122 struct mlx5_ifc_pmlp_reg_bits pmlp_reg; 9123 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg; 9124 struct mlx5_ifc_pmpc_reg_bits pmpc_reg; 9125 struct mlx5_ifc_pmpe_reg_bits pmpe_reg; 9126 struct mlx5_ifc_pmpr_reg_bits pmpr_reg; 9127 struct mlx5_ifc_pmtu_reg_bits pmtu_reg; 9128 struct mlx5_ifc_ppad_reg_bits ppad_reg; 9129 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg; 9130 struct mlx5_ifc_mpein_reg_bits mpein_reg; 9131 struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg; 9132 struct mlx5_ifc_pplm_reg_bits pplm_reg; 9133 struct mlx5_ifc_pplr_reg_bits pplr_reg; 9134 struct mlx5_ifc_ppsc_reg_bits ppsc_reg; 9135 struct mlx5_ifc_pqdr_reg_bits pqdr_reg; 9136 struct mlx5_ifc_pspa_reg_bits pspa_reg; 9137 struct mlx5_ifc_ptas_reg_bits ptas_reg; 9138 struct mlx5_ifc_ptys_reg_bits ptys_reg; 9139 struct mlx5_ifc_mlcr_reg_bits mlcr_reg; 9140 struct mlx5_ifc_pude_reg_bits pude_reg; 9141 struct mlx5_ifc_pvlc_reg_bits pvlc_reg; 9142 struct mlx5_ifc_slrg_reg_bits slrg_reg; 9143 struct mlx5_ifc_sltp_reg_bits sltp_reg; 9144 struct mlx5_ifc_mtpps_reg_bits mtpps_reg; 9145 struct mlx5_ifc_mtppse_reg_bits mtppse_reg; 9146 struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg; 9147 struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits; 9148 struct mlx5_ifc_fpga_cap_bits fpga_cap_bits; 9149 struct mlx5_ifc_mcqi_reg_bits mcqi_reg; 9150 struct mlx5_ifc_mcc_reg_bits mcc_reg; 9151 struct mlx5_ifc_mcda_reg_bits mcda_reg; 9152 u8 reserved_at_0[0x60e0]; 9153 }; 9154 9155 union mlx5_ifc_debug_enhancements_document_bits { 9156 struct mlx5_ifc_health_buffer_bits health_buffer; 9157 u8 reserved_at_0[0x200]; 9158 }; 9159 9160 union mlx5_ifc_uplink_pci_interface_document_bits { 9161 struct mlx5_ifc_initial_seg_bits initial_seg; 9162 u8 reserved_at_0[0x20060]; 9163 }; 9164 9165 struct mlx5_ifc_set_flow_table_root_out_bits { 9166 u8 status[0x8]; 9167 u8 reserved_at_8[0x18]; 9168 9169 u8 syndrome[0x20]; 9170 9171 u8 reserved_at_40[0x40]; 9172 }; 9173 9174 struct mlx5_ifc_set_flow_table_root_in_bits { 9175 u8 opcode[0x10]; 9176 u8 reserved_at_10[0x10]; 9177 9178 u8 reserved_at_20[0x10]; 9179 u8 op_mod[0x10]; 9180 9181 u8 other_vport[0x1]; 9182 u8 reserved_at_41[0xf]; 9183 u8 vport_number[0x10]; 9184 9185 u8 reserved_at_60[0x20]; 9186 9187 u8 table_type[0x8]; 9188 u8 reserved_at_88[0x18]; 9189 9190 u8 reserved_at_a0[0x8]; 9191 u8 table_id[0x18]; 9192 9193 u8 reserved_at_c0[0x8]; 9194 u8 underlay_qpn[0x18]; 9195 u8 reserved_at_e0[0x120]; 9196 }; 9197 9198 enum { 9199 MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = (1UL << 0), 9200 MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15), 9201 }; 9202 9203 struct mlx5_ifc_modify_flow_table_out_bits { 9204 u8 status[0x8]; 9205 u8 reserved_at_8[0x18]; 9206 9207 u8 syndrome[0x20]; 9208 9209 u8 reserved_at_40[0x40]; 9210 }; 9211 9212 struct mlx5_ifc_modify_flow_table_in_bits { 9213 u8 opcode[0x10]; 9214 u8 reserved_at_10[0x10]; 9215 9216 u8 reserved_at_20[0x10]; 9217 u8 op_mod[0x10]; 9218 9219 u8 other_vport[0x1]; 9220 u8 reserved_at_41[0xf]; 9221 u8 vport_number[0x10]; 9222 9223 u8 reserved_at_60[0x10]; 9224 u8 modify_field_select[0x10]; 9225 9226 u8 table_type[0x8]; 9227 u8 reserved_at_88[0x18]; 9228 9229 u8 reserved_at_a0[0x8]; 9230 u8 table_id[0x18]; 9231 9232 struct mlx5_ifc_flow_table_context_bits flow_table_context; 9233 }; 9234 9235 struct mlx5_ifc_ets_tcn_config_reg_bits { 9236 u8 g[0x1]; 9237 u8 b[0x1]; 9238 u8 r[0x1]; 9239 u8 reserved_at_3[0x9]; 9240 u8 group[0x4]; 9241 u8 reserved_at_10[0x9]; 9242 u8 bw_allocation[0x7]; 9243 9244 u8 reserved_at_20[0xc]; 9245 u8 max_bw_units[0x4]; 9246 u8 reserved_at_30[0x8]; 9247 u8 max_bw_value[0x8]; 9248 }; 9249 9250 struct mlx5_ifc_ets_global_config_reg_bits { 9251 u8 reserved_at_0[0x2]; 9252 u8 r[0x1]; 9253 u8 reserved_at_3[0x1d]; 9254 9255 u8 reserved_at_20[0xc]; 9256 u8 max_bw_units[0x4]; 9257 u8 reserved_at_30[0x8]; 9258 u8 max_bw_value[0x8]; 9259 }; 9260 9261 struct mlx5_ifc_qetc_reg_bits { 9262 u8 reserved_at_0[0x8]; 9263 u8 port_number[0x8]; 9264 u8 reserved_at_10[0x30]; 9265 9266 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8]; 9267 struct mlx5_ifc_ets_global_config_reg_bits global_configuration; 9268 }; 9269 9270 struct mlx5_ifc_qpdpm_dscp_reg_bits { 9271 u8 e[0x1]; 9272 u8 reserved_at_01[0x0b]; 9273 u8 prio[0x04]; 9274 }; 9275 9276 struct mlx5_ifc_qpdpm_reg_bits { 9277 u8 reserved_at_0[0x8]; 9278 u8 local_port[0x8]; 9279 u8 reserved_at_10[0x10]; 9280 struct mlx5_ifc_qpdpm_dscp_reg_bits dscp[64]; 9281 }; 9282 9283 struct mlx5_ifc_qpts_reg_bits { 9284 u8 reserved_at_0[0x8]; 9285 u8 local_port[0x8]; 9286 u8 reserved_at_10[0x2d]; 9287 u8 trust_state[0x3]; 9288 }; 9289 9290 struct mlx5_ifc_pptb_reg_bits { 9291 u8 reserved_at_0[0x2]; 9292 u8 mm[0x2]; 9293 u8 reserved_at_4[0x4]; 9294 u8 local_port[0x8]; 9295 u8 reserved_at_10[0x6]; 9296 u8 cm[0x1]; 9297 u8 um[0x1]; 9298 u8 pm[0x8]; 9299 9300 u8 prio_x_buff[0x20]; 9301 9302 u8 pm_msb[0x8]; 9303 u8 reserved_at_48[0x10]; 9304 u8 ctrl_buff[0x4]; 9305 u8 untagged_buff[0x4]; 9306 }; 9307 9308 struct mlx5_ifc_pbmc_reg_bits { 9309 u8 reserved_at_0[0x8]; 9310 u8 local_port[0x8]; 9311 u8 reserved_at_10[0x10]; 9312 9313 u8 xoff_timer_value[0x10]; 9314 u8 xoff_refresh[0x10]; 9315 9316 u8 reserved_at_40[0x9]; 9317 u8 fullness_threshold[0x7]; 9318 u8 port_buffer_size[0x10]; 9319 9320 struct mlx5_ifc_bufferx_reg_bits buffer[10]; 9321 9322 u8 reserved_at_2e0[0x40]; 9323 }; 9324 9325 struct mlx5_ifc_qtct_reg_bits { 9326 u8 reserved_at_0[0x8]; 9327 u8 port_number[0x8]; 9328 u8 reserved_at_10[0xd]; 9329 u8 prio[0x3]; 9330 9331 u8 reserved_at_20[0x1d]; 9332 u8 tclass[0x3]; 9333 }; 9334 9335 struct mlx5_ifc_mcia_reg_bits { 9336 u8 l[0x1]; 9337 u8 reserved_at_1[0x7]; 9338 u8 module[0x8]; 9339 u8 reserved_at_10[0x8]; 9340 u8 status[0x8]; 9341 9342 u8 i2c_device_address[0x8]; 9343 u8 page_number[0x8]; 9344 u8 device_address[0x10]; 9345 9346 u8 reserved_at_40[0x10]; 9347 u8 size[0x10]; 9348 9349 u8 reserved_at_60[0x20]; 9350 9351 u8 dword_0[0x20]; 9352 u8 dword_1[0x20]; 9353 u8 dword_2[0x20]; 9354 u8 dword_3[0x20]; 9355 u8 dword_4[0x20]; 9356 u8 dword_5[0x20]; 9357 u8 dword_6[0x20]; 9358 u8 dword_7[0x20]; 9359 u8 dword_8[0x20]; 9360 u8 dword_9[0x20]; 9361 u8 dword_10[0x20]; 9362 u8 dword_11[0x20]; 9363 }; 9364 9365 struct mlx5_ifc_dcbx_param_bits { 9366 u8 dcbx_cee_cap[0x1]; 9367 u8 dcbx_ieee_cap[0x1]; 9368 u8 dcbx_standby_cap[0x1]; 9369 u8 reserved_at_3[0x5]; 9370 u8 port_number[0x8]; 9371 u8 reserved_at_10[0xa]; 9372 u8 max_application_table_size[6]; 9373 u8 reserved_at_20[0x15]; 9374 u8 version_oper[0x3]; 9375 u8 reserved_at_38[5]; 9376 u8 version_admin[0x3]; 9377 u8 willing_admin[0x1]; 9378 u8 reserved_at_41[0x3]; 9379 u8 pfc_cap_oper[0x4]; 9380 u8 reserved_at_48[0x4]; 9381 u8 pfc_cap_admin[0x4]; 9382 u8 reserved_at_50[0x4]; 9383 u8 num_of_tc_oper[0x4]; 9384 u8 reserved_at_58[0x4]; 9385 u8 num_of_tc_admin[0x4]; 9386 u8 remote_willing[0x1]; 9387 u8 reserved_at_61[3]; 9388 u8 remote_pfc_cap[4]; 9389 u8 reserved_at_68[0x14]; 9390 u8 remote_num_of_tc[0x4]; 9391 u8 reserved_at_80[0x18]; 9392 u8 error[0x8]; 9393 u8 reserved_at_a0[0x160]; 9394 }; 9395 9396 struct mlx5_ifc_lagc_bits { 9397 u8 reserved_at_0[0x1d]; 9398 u8 lag_state[0x3]; 9399 9400 u8 reserved_at_20[0x14]; 9401 u8 tx_remap_affinity_2[0x4]; 9402 u8 reserved_at_38[0x4]; 9403 u8 tx_remap_affinity_1[0x4]; 9404 }; 9405 9406 struct mlx5_ifc_create_lag_out_bits { 9407 u8 status[0x8]; 9408 u8 reserved_at_8[0x18]; 9409 9410 u8 syndrome[0x20]; 9411 9412 u8 reserved_at_40[0x40]; 9413 }; 9414 9415 struct mlx5_ifc_create_lag_in_bits { 9416 u8 opcode[0x10]; 9417 u8 reserved_at_10[0x10]; 9418 9419 u8 reserved_at_20[0x10]; 9420 u8 op_mod[0x10]; 9421 9422 struct mlx5_ifc_lagc_bits ctx; 9423 }; 9424 9425 struct mlx5_ifc_modify_lag_out_bits { 9426 u8 status[0x8]; 9427 u8 reserved_at_8[0x18]; 9428 9429 u8 syndrome[0x20]; 9430 9431 u8 reserved_at_40[0x40]; 9432 }; 9433 9434 struct mlx5_ifc_modify_lag_in_bits { 9435 u8 opcode[0x10]; 9436 u8 reserved_at_10[0x10]; 9437 9438 u8 reserved_at_20[0x10]; 9439 u8 op_mod[0x10]; 9440 9441 u8 reserved_at_40[0x20]; 9442 u8 field_select[0x20]; 9443 9444 struct mlx5_ifc_lagc_bits ctx; 9445 }; 9446 9447 struct mlx5_ifc_query_lag_out_bits { 9448 u8 status[0x8]; 9449 u8 reserved_at_8[0x18]; 9450 9451 u8 syndrome[0x20]; 9452 9453 u8 reserved_at_40[0x40]; 9454 9455 struct mlx5_ifc_lagc_bits ctx; 9456 }; 9457 9458 struct mlx5_ifc_query_lag_in_bits { 9459 u8 opcode[0x10]; 9460 u8 reserved_at_10[0x10]; 9461 9462 u8 reserved_at_20[0x10]; 9463 u8 op_mod[0x10]; 9464 9465 u8 reserved_at_40[0x40]; 9466 }; 9467 9468 struct mlx5_ifc_destroy_lag_out_bits { 9469 u8 status[0x8]; 9470 u8 reserved_at_8[0x18]; 9471 9472 u8 syndrome[0x20]; 9473 9474 u8 reserved_at_40[0x40]; 9475 }; 9476 9477 struct mlx5_ifc_destroy_lag_in_bits { 9478 u8 opcode[0x10]; 9479 u8 reserved_at_10[0x10]; 9480 9481 u8 reserved_at_20[0x10]; 9482 u8 op_mod[0x10]; 9483 9484 u8 reserved_at_40[0x40]; 9485 }; 9486 9487 struct mlx5_ifc_create_vport_lag_out_bits { 9488 u8 status[0x8]; 9489 u8 reserved_at_8[0x18]; 9490 9491 u8 syndrome[0x20]; 9492 9493 u8 reserved_at_40[0x40]; 9494 }; 9495 9496 struct mlx5_ifc_create_vport_lag_in_bits { 9497 u8 opcode[0x10]; 9498 u8 reserved_at_10[0x10]; 9499 9500 u8 reserved_at_20[0x10]; 9501 u8 op_mod[0x10]; 9502 9503 u8 reserved_at_40[0x40]; 9504 }; 9505 9506 struct mlx5_ifc_destroy_vport_lag_out_bits { 9507 u8 status[0x8]; 9508 u8 reserved_at_8[0x18]; 9509 9510 u8 syndrome[0x20]; 9511 9512 u8 reserved_at_40[0x40]; 9513 }; 9514 9515 struct mlx5_ifc_destroy_vport_lag_in_bits { 9516 u8 opcode[0x10]; 9517 u8 reserved_at_10[0x10]; 9518 9519 u8 reserved_at_20[0x10]; 9520 u8 op_mod[0x10]; 9521 9522 u8 reserved_at_40[0x40]; 9523 }; 9524 9525 struct mlx5_ifc_alloc_memic_in_bits { 9526 u8 opcode[0x10]; 9527 u8 reserved_at_10[0x10]; 9528 9529 u8 reserved_at_20[0x10]; 9530 u8 op_mod[0x10]; 9531 9532 u8 reserved_at_30[0x20]; 9533 9534 u8 reserved_at_40[0x18]; 9535 u8 log_memic_addr_alignment[0x8]; 9536 9537 u8 range_start_addr[0x40]; 9538 9539 u8 range_size[0x20]; 9540 9541 u8 memic_size[0x20]; 9542 }; 9543 9544 struct mlx5_ifc_alloc_memic_out_bits { 9545 u8 status[0x8]; 9546 u8 reserved_at_8[0x18]; 9547 9548 u8 syndrome[0x20]; 9549 9550 u8 memic_start_addr[0x40]; 9551 }; 9552 9553 struct mlx5_ifc_dealloc_memic_in_bits { 9554 u8 opcode[0x10]; 9555 u8 reserved_at_10[0x10]; 9556 9557 u8 reserved_at_20[0x10]; 9558 u8 op_mod[0x10]; 9559 9560 u8 reserved_at_40[0x40]; 9561 9562 u8 memic_start_addr[0x40]; 9563 9564 u8 memic_size[0x20]; 9565 9566 u8 reserved_at_e0[0x20]; 9567 }; 9568 9569 struct mlx5_ifc_dealloc_memic_out_bits { 9570 u8 status[0x8]; 9571 u8 reserved_at_8[0x18]; 9572 9573 u8 syndrome[0x20]; 9574 9575 u8 reserved_at_40[0x40]; 9576 }; 9577 9578 struct mlx5_ifc_general_obj_in_cmd_hdr_bits { 9579 u8 opcode[0x10]; 9580 u8 uid[0x10]; 9581 9582 u8 reserved_at_20[0x10]; 9583 u8 obj_type[0x10]; 9584 9585 u8 obj_id[0x20]; 9586 9587 u8 reserved_at_60[0x20]; 9588 }; 9589 9590 struct mlx5_ifc_general_obj_out_cmd_hdr_bits { 9591 u8 status[0x8]; 9592 u8 reserved_at_8[0x18]; 9593 9594 u8 syndrome[0x20]; 9595 9596 u8 obj_id[0x20]; 9597 9598 u8 reserved_at_60[0x20]; 9599 }; 9600 9601 struct mlx5_ifc_umem_bits { 9602 u8 reserved_at_0[0x80]; 9603 9604 u8 reserved_at_80[0x1b]; 9605 u8 log_page_size[0x5]; 9606 9607 u8 page_offset[0x20]; 9608 9609 u8 num_of_mtt[0x40]; 9610 9611 struct mlx5_ifc_mtt_bits mtt[0]; 9612 }; 9613 9614 struct mlx5_ifc_uctx_bits { 9615 u8 cap[0x20]; 9616 9617 u8 reserved_at_20[0x160]; 9618 }; 9619 9620 struct mlx5_ifc_sw_icm_bits { 9621 u8 modify_field_select[0x40]; 9622 9623 u8 reserved_at_40[0x18]; 9624 u8 log_sw_icm_size[0x8]; 9625 9626 u8 reserved_at_60[0x20]; 9627 9628 u8 sw_icm_start_addr[0x40]; 9629 9630 u8 reserved_at_c0[0x140]; 9631 }; 9632 9633 struct mlx5_ifc_geneve_tlv_option_bits { 9634 u8 modify_field_select[0x40]; 9635 9636 u8 reserved_at_40[0x18]; 9637 u8 geneve_option_fte_index[0x8]; 9638 9639 u8 option_class[0x10]; 9640 u8 option_type[0x8]; 9641 u8 reserved_at_78[0x3]; 9642 u8 option_data_length[0x5]; 9643 9644 u8 reserved_at_80[0x180]; 9645 }; 9646 9647 struct mlx5_ifc_create_umem_in_bits { 9648 u8 opcode[0x10]; 9649 u8 uid[0x10]; 9650 9651 u8 reserved_at_20[0x10]; 9652 u8 op_mod[0x10]; 9653 9654 u8 reserved_at_40[0x40]; 9655 9656 struct mlx5_ifc_umem_bits umem; 9657 }; 9658 9659 struct mlx5_ifc_create_uctx_in_bits { 9660 u8 opcode[0x10]; 9661 u8 reserved_at_10[0x10]; 9662 9663 u8 reserved_at_20[0x10]; 9664 u8 op_mod[0x10]; 9665 9666 u8 reserved_at_40[0x40]; 9667 9668 struct mlx5_ifc_uctx_bits uctx; 9669 }; 9670 9671 struct mlx5_ifc_destroy_uctx_in_bits { 9672 u8 opcode[0x10]; 9673 u8 reserved_at_10[0x10]; 9674 9675 u8 reserved_at_20[0x10]; 9676 u8 op_mod[0x10]; 9677 9678 u8 reserved_at_40[0x10]; 9679 u8 uid[0x10]; 9680 9681 u8 reserved_at_60[0x20]; 9682 }; 9683 9684 struct mlx5_ifc_create_sw_icm_in_bits { 9685 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 9686 struct mlx5_ifc_sw_icm_bits sw_icm; 9687 }; 9688 9689 struct mlx5_ifc_create_geneve_tlv_option_in_bits { 9690 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 9691 struct mlx5_ifc_geneve_tlv_option_bits geneve_tlv_opt; 9692 }; 9693 9694 struct mlx5_ifc_mtrc_string_db_param_bits { 9695 u8 string_db_base_address[0x20]; 9696 9697 u8 reserved_at_20[0x8]; 9698 u8 string_db_size[0x18]; 9699 }; 9700 9701 struct mlx5_ifc_mtrc_cap_bits { 9702 u8 trace_owner[0x1]; 9703 u8 trace_to_memory[0x1]; 9704 u8 reserved_at_2[0x4]; 9705 u8 trc_ver[0x2]; 9706 u8 reserved_at_8[0x14]; 9707 u8 num_string_db[0x4]; 9708 9709 u8 first_string_trace[0x8]; 9710 u8 num_string_trace[0x8]; 9711 u8 reserved_at_30[0x28]; 9712 9713 u8 log_max_trace_buffer_size[0x8]; 9714 9715 u8 reserved_at_60[0x20]; 9716 9717 struct mlx5_ifc_mtrc_string_db_param_bits string_db_param[8]; 9718 9719 u8 reserved_at_280[0x180]; 9720 }; 9721 9722 struct mlx5_ifc_mtrc_conf_bits { 9723 u8 reserved_at_0[0x1c]; 9724 u8 trace_mode[0x4]; 9725 u8 reserved_at_20[0x18]; 9726 u8 log_trace_buffer_size[0x8]; 9727 u8 trace_mkey[0x20]; 9728 u8 reserved_at_60[0x3a0]; 9729 }; 9730 9731 struct mlx5_ifc_mtrc_stdb_bits { 9732 u8 string_db_index[0x4]; 9733 u8 reserved_at_4[0x4]; 9734 u8 read_size[0x18]; 9735 u8 start_offset[0x20]; 9736 u8 string_db_data[0]; 9737 }; 9738 9739 struct mlx5_ifc_mtrc_ctrl_bits { 9740 u8 trace_status[0x2]; 9741 u8 reserved_at_2[0x2]; 9742 u8 arm_event[0x1]; 9743 u8 reserved_at_5[0xb]; 9744 u8 modify_field_select[0x10]; 9745 u8 reserved_at_20[0x2b]; 9746 u8 current_timestamp52_32[0x15]; 9747 u8 current_timestamp31_0[0x20]; 9748 u8 reserved_at_80[0x180]; 9749 }; 9750 9751 struct mlx5_ifc_host_params_context_bits { 9752 u8 host_number[0x8]; 9753 u8 reserved_at_8[0x8]; 9754 u8 host_num_of_vfs[0x10]; 9755 9756 u8 host_total_vfs[0x10]; 9757 u8 host_pci_bus[0x10]; 9758 9759 u8 reserved_at_40[0x10]; 9760 u8 host_pci_device[0x10]; 9761 9762 u8 reserved_at_60[0x10]; 9763 u8 host_pci_function[0x10]; 9764 9765 u8 reserved_at_80[0x180]; 9766 }; 9767 9768 struct mlx5_ifc_query_esw_functions_in_bits { 9769 u8 opcode[0x10]; 9770 u8 reserved_at_10[0x10]; 9771 9772 u8 reserved_at_20[0x10]; 9773 u8 op_mod[0x10]; 9774 9775 u8 reserved_at_40[0x40]; 9776 }; 9777 9778 struct mlx5_ifc_query_esw_functions_out_bits { 9779 u8 status[0x8]; 9780 u8 reserved_at_8[0x18]; 9781 9782 u8 syndrome[0x20]; 9783 9784 u8 reserved_at_40[0x40]; 9785 9786 struct mlx5_ifc_host_params_context_bits host_params_context; 9787 9788 u8 reserved_at_280[0x180]; 9789 }; 9790 9791 #endif /* MLX5_IFC_H */ 9792