1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 #ifndef MLX5_IFC_H 33 #define MLX5_IFC_H 34 35 #include "mlx5_ifc_fpga.h" 36 37 enum { 38 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0, 39 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1, 40 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2, 41 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3, 42 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13, 43 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14, 44 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c, 45 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d, 46 MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4, 47 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5, 48 MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED = 0x7, 49 MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT = 0xc, 50 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10, 51 MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR = 0x11, 52 MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR = 0x12, 53 MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR = 0x8, 54 MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE = 0x9, 55 MLX5_EVENT_TYPE_CODING_GPIO_EVENT = 0x15, 56 MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19, 57 MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a, 58 MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT = 0x1b, 59 MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT = 0x1f, 60 MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa, 61 MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb, 62 MLX5_EVENT_TYPE_CODING_FPGA_ERROR = 0x20, 63 MLX5_EVENT_TYPE_CODING_FPGA_QP_ERROR = 0x21 64 }; 65 66 enum { 67 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0, 68 MLX5_SET_HCA_CAP_OP_MOD_ODP = 0x2, 69 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3, 70 MLX5_SET_HCA_CAP_OP_MOD_ROCE = 0x4, 71 MLX5_SET_HCA_CAP_OP_MODE_PORT_SELECTION = 0x25, 72 }; 73 74 enum { 75 MLX5_SHARED_RESOURCE_UID = 0xffff, 76 }; 77 78 enum { 79 MLX5_OBJ_TYPE_SW_ICM = 0x0008, 80 }; 81 82 enum { 83 MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM = (1ULL << MLX5_OBJ_TYPE_SW_ICM), 84 MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT = (1ULL << 11), 85 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q = (1ULL << 13), 86 MLX5_GENERAL_OBJ_TYPES_CAP_MACSEC_OFFLOAD = (1ULL << 39), 87 }; 88 89 enum { 90 MLX5_OBJ_TYPE_GENEVE_TLV_OPT = 0x000b, 91 MLX5_OBJ_TYPE_VIRTIO_NET_Q = 0x000d, 92 MLX5_OBJ_TYPE_VIRTIO_Q_COUNTERS = 0x001c, 93 MLX5_OBJ_TYPE_MATCH_DEFINER = 0x0018, 94 MLX5_OBJ_TYPE_PAGE_TRACK = 0x46, 95 MLX5_OBJ_TYPE_MKEY = 0xff01, 96 MLX5_OBJ_TYPE_QP = 0xff02, 97 MLX5_OBJ_TYPE_PSV = 0xff03, 98 MLX5_OBJ_TYPE_RMP = 0xff04, 99 MLX5_OBJ_TYPE_XRC_SRQ = 0xff05, 100 MLX5_OBJ_TYPE_RQ = 0xff06, 101 MLX5_OBJ_TYPE_SQ = 0xff07, 102 MLX5_OBJ_TYPE_TIR = 0xff08, 103 MLX5_OBJ_TYPE_TIS = 0xff09, 104 MLX5_OBJ_TYPE_DCT = 0xff0a, 105 MLX5_OBJ_TYPE_XRQ = 0xff0b, 106 MLX5_OBJ_TYPE_RQT = 0xff0e, 107 MLX5_OBJ_TYPE_FLOW_COUNTER = 0xff0f, 108 MLX5_OBJ_TYPE_CQ = 0xff10, 109 }; 110 111 enum { 112 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100, 113 MLX5_CMD_OP_QUERY_ADAPTER = 0x101, 114 MLX5_CMD_OP_INIT_HCA = 0x102, 115 MLX5_CMD_OP_TEARDOWN_HCA = 0x103, 116 MLX5_CMD_OP_ENABLE_HCA = 0x104, 117 MLX5_CMD_OP_DISABLE_HCA = 0x105, 118 MLX5_CMD_OP_QUERY_PAGES = 0x107, 119 MLX5_CMD_OP_MANAGE_PAGES = 0x108, 120 MLX5_CMD_OP_SET_HCA_CAP = 0x109, 121 MLX5_CMD_OP_QUERY_ISSI = 0x10a, 122 MLX5_CMD_OP_SET_ISSI = 0x10b, 123 MLX5_CMD_OP_SET_DRIVER_VERSION = 0x10d, 124 MLX5_CMD_OP_QUERY_SF_PARTITION = 0x111, 125 MLX5_CMD_OP_ALLOC_SF = 0x113, 126 MLX5_CMD_OP_DEALLOC_SF = 0x114, 127 MLX5_CMD_OP_SUSPEND_VHCA = 0x115, 128 MLX5_CMD_OP_RESUME_VHCA = 0x116, 129 MLX5_CMD_OP_QUERY_VHCA_MIGRATION_STATE = 0x117, 130 MLX5_CMD_OP_SAVE_VHCA_STATE = 0x118, 131 MLX5_CMD_OP_LOAD_VHCA_STATE = 0x119, 132 MLX5_CMD_OP_CREATE_MKEY = 0x200, 133 MLX5_CMD_OP_QUERY_MKEY = 0x201, 134 MLX5_CMD_OP_DESTROY_MKEY = 0x202, 135 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203, 136 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204, 137 MLX5_CMD_OP_ALLOC_MEMIC = 0x205, 138 MLX5_CMD_OP_DEALLOC_MEMIC = 0x206, 139 MLX5_CMD_OP_MODIFY_MEMIC = 0x207, 140 MLX5_CMD_OP_CREATE_EQ = 0x301, 141 MLX5_CMD_OP_DESTROY_EQ = 0x302, 142 MLX5_CMD_OP_QUERY_EQ = 0x303, 143 MLX5_CMD_OP_GEN_EQE = 0x304, 144 MLX5_CMD_OP_CREATE_CQ = 0x400, 145 MLX5_CMD_OP_DESTROY_CQ = 0x401, 146 MLX5_CMD_OP_QUERY_CQ = 0x402, 147 MLX5_CMD_OP_MODIFY_CQ = 0x403, 148 MLX5_CMD_OP_CREATE_QP = 0x500, 149 MLX5_CMD_OP_DESTROY_QP = 0x501, 150 MLX5_CMD_OP_RST2INIT_QP = 0x502, 151 MLX5_CMD_OP_INIT2RTR_QP = 0x503, 152 MLX5_CMD_OP_RTR2RTS_QP = 0x504, 153 MLX5_CMD_OP_RTS2RTS_QP = 0x505, 154 MLX5_CMD_OP_SQERR2RTS_QP = 0x506, 155 MLX5_CMD_OP_2ERR_QP = 0x507, 156 MLX5_CMD_OP_2RST_QP = 0x50a, 157 MLX5_CMD_OP_QUERY_QP = 0x50b, 158 MLX5_CMD_OP_SQD_RTS_QP = 0x50c, 159 MLX5_CMD_OP_INIT2INIT_QP = 0x50e, 160 MLX5_CMD_OP_CREATE_PSV = 0x600, 161 MLX5_CMD_OP_DESTROY_PSV = 0x601, 162 MLX5_CMD_OP_CREATE_SRQ = 0x700, 163 MLX5_CMD_OP_DESTROY_SRQ = 0x701, 164 MLX5_CMD_OP_QUERY_SRQ = 0x702, 165 MLX5_CMD_OP_ARM_RQ = 0x703, 166 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705, 167 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706, 168 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707, 169 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708, 170 MLX5_CMD_OP_CREATE_DCT = 0x710, 171 MLX5_CMD_OP_DESTROY_DCT = 0x711, 172 MLX5_CMD_OP_DRAIN_DCT = 0x712, 173 MLX5_CMD_OP_QUERY_DCT = 0x713, 174 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714, 175 MLX5_CMD_OP_CREATE_XRQ = 0x717, 176 MLX5_CMD_OP_DESTROY_XRQ = 0x718, 177 MLX5_CMD_OP_QUERY_XRQ = 0x719, 178 MLX5_CMD_OP_ARM_XRQ = 0x71a, 179 MLX5_CMD_OP_QUERY_XRQ_DC_PARAMS_ENTRY = 0x725, 180 MLX5_CMD_OP_SET_XRQ_DC_PARAMS_ENTRY = 0x726, 181 MLX5_CMD_OP_QUERY_XRQ_ERROR_PARAMS = 0x727, 182 MLX5_CMD_OP_RELEASE_XRQ_ERROR = 0x729, 183 MLX5_CMD_OP_MODIFY_XRQ = 0x72a, 184 MLX5_CMD_OP_QUERY_ESW_FUNCTIONS = 0x740, 185 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750, 186 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751, 187 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752, 188 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753, 189 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754, 190 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755, 191 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760, 192 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761, 193 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762, 194 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763, 195 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764, 196 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765, 197 MLX5_CMD_OP_QUERY_VNIC_ENV = 0x76f, 198 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770, 199 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771, 200 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772, 201 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773, 202 MLX5_CMD_OP_SET_MONITOR_COUNTER = 0x774, 203 MLX5_CMD_OP_ARM_MONITOR_COUNTER = 0x775, 204 MLX5_CMD_OP_SET_PP_RATE_LIMIT = 0x780, 205 MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781, 206 MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT = 0x782, 207 MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT = 0x783, 208 MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT = 0x784, 209 MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT = 0x785, 210 MLX5_CMD_OP_CREATE_QOS_PARA_VPORT = 0x786, 211 MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT = 0x787, 212 MLX5_CMD_OP_ALLOC_PD = 0x800, 213 MLX5_CMD_OP_DEALLOC_PD = 0x801, 214 MLX5_CMD_OP_ALLOC_UAR = 0x802, 215 MLX5_CMD_OP_DEALLOC_UAR = 0x803, 216 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804, 217 MLX5_CMD_OP_ACCESS_REG = 0x805, 218 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806, 219 MLX5_CMD_OP_DETACH_FROM_MCG = 0x807, 220 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a, 221 MLX5_CMD_OP_MAD_IFC = 0x50d, 222 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b, 223 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c, 224 MLX5_CMD_OP_NOP = 0x80d, 225 MLX5_CMD_OP_ALLOC_XRCD = 0x80e, 226 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f, 227 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816, 228 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817, 229 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822, 230 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823, 231 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824, 232 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825, 233 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826, 234 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827, 235 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828, 236 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829, 237 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a, 238 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b, 239 MLX5_CMD_OP_SET_WOL_ROL = 0x830, 240 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831, 241 MLX5_CMD_OP_CREATE_LAG = 0x840, 242 MLX5_CMD_OP_MODIFY_LAG = 0x841, 243 MLX5_CMD_OP_QUERY_LAG = 0x842, 244 MLX5_CMD_OP_DESTROY_LAG = 0x843, 245 MLX5_CMD_OP_CREATE_VPORT_LAG = 0x844, 246 MLX5_CMD_OP_DESTROY_VPORT_LAG = 0x845, 247 MLX5_CMD_OP_CREATE_TIR = 0x900, 248 MLX5_CMD_OP_MODIFY_TIR = 0x901, 249 MLX5_CMD_OP_DESTROY_TIR = 0x902, 250 MLX5_CMD_OP_QUERY_TIR = 0x903, 251 MLX5_CMD_OP_CREATE_SQ = 0x904, 252 MLX5_CMD_OP_MODIFY_SQ = 0x905, 253 MLX5_CMD_OP_DESTROY_SQ = 0x906, 254 MLX5_CMD_OP_QUERY_SQ = 0x907, 255 MLX5_CMD_OP_CREATE_RQ = 0x908, 256 MLX5_CMD_OP_MODIFY_RQ = 0x909, 257 MLX5_CMD_OP_SET_DELAY_DROP_PARAMS = 0x910, 258 MLX5_CMD_OP_DESTROY_RQ = 0x90a, 259 MLX5_CMD_OP_QUERY_RQ = 0x90b, 260 MLX5_CMD_OP_CREATE_RMP = 0x90c, 261 MLX5_CMD_OP_MODIFY_RMP = 0x90d, 262 MLX5_CMD_OP_DESTROY_RMP = 0x90e, 263 MLX5_CMD_OP_QUERY_RMP = 0x90f, 264 MLX5_CMD_OP_CREATE_TIS = 0x912, 265 MLX5_CMD_OP_MODIFY_TIS = 0x913, 266 MLX5_CMD_OP_DESTROY_TIS = 0x914, 267 MLX5_CMD_OP_QUERY_TIS = 0x915, 268 MLX5_CMD_OP_CREATE_RQT = 0x916, 269 MLX5_CMD_OP_MODIFY_RQT = 0x917, 270 MLX5_CMD_OP_DESTROY_RQT = 0x918, 271 MLX5_CMD_OP_QUERY_RQT = 0x919, 272 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f, 273 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930, 274 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931, 275 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932, 276 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933, 277 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934, 278 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935, 279 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936, 280 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937, 281 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938, 282 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939, 283 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a, 284 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b, 285 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c, 286 MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT = 0x93d, 287 MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT = 0x93e, 288 MLX5_CMD_OP_QUERY_PACKET_REFORMAT_CONTEXT = 0x93f, 289 MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT = 0x940, 290 MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941, 291 MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT = 0x942, 292 MLX5_CMD_OP_FPGA_CREATE_QP = 0x960, 293 MLX5_CMD_OP_FPGA_MODIFY_QP = 0x961, 294 MLX5_CMD_OP_FPGA_QUERY_QP = 0x962, 295 MLX5_CMD_OP_FPGA_DESTROY_QP = 0x963, 296 MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS = 0x964, 297 MLX5_CMD_OP_CREATE_GENERAL_OBJECT = 0xa00, 298 MLX5_CMD_OP_MODIFY_GENERAL_OBJECT = 0xa01, 299 MLX5_CMD_OP_QUERY_GENERAL_OBJECT = 0xa02, 300 MLX5_CMD_OP_DESTROY_GENERAL_OBJECT = 0xa03, 301 MLX5_CMD_OP_CREATE_UCTX = 0xa04, 302 MLX5_CMD_OP_DESTROY_UCTX = 0xa06, 303 MLX5_CMD_OP_CREATE_UMEM = 0xa08, 304 MLX5_CMD_OP_DESTROY_UMEM = 0xa0a, 305 MLX5_CMD_OP_SYNC_STEERING = 0xb00, 306 MLX5_CMD_OP_QUERY_VHCA_STATE = 0xb0d, 307 MLX5_CMD_OP_MODIFY_VHCA_STATE = 0xb0e, 308 MLX5_CMD_OP_MAX 309 }; 310 311 /* Valid range for general commands that don't work over an object */ 312 enum { 313 MLX5_CMD_OP_GENERAL_START = 0xb00, 314 MLX5_CMD_OP_GENERAL_END = 0xd00, 315 }; 316 317 struct mlx5_ifc_flow_table_fields_supported_bits { 318 u8 outer_dmac[0x1]; 319 u8 outer_smac[0x1]; 320 u8 outer_ether_type[0x1]; 321 u8 outer_ip_version[0x1]; 322 u8 outer_first_prio[0x1]; 323 u8 outer_first_cfi[0x1]; 324 u8 outer_first_vid[0x1]; 325 u8 outer_ipv4_ttl[0x1]; 326 u8 outer_second_prio[0x1]; 327 u8 outer_second_cfi[0x1]; 328 u8 outer_second_vid[0x1]; 329 u8 reserved_at_b[0x1]; 330 u8 outer_sip[0x1]; 331 u8 outer_dip[0x1]; 332 u8 outer_frag[0x1]; 333 u8 outer_ip_protocol[0x1]; 334 u8 outer_ip_ecn[0x1]; 335 u8 outer_ip_dscp[0x1]; 336 u8 outer_udp_sport[0x1]; 337 u8 outer_udp_dport[0x1]; 338 u8 outer_tcp_sport[0x1]; 339 u8 outer_tcp_dport[0x1]; 340 u8 outer_tcp_flags[0x1]; 341 u8 outer_gre_protocol[0x1]; 342 u8 outer_gre_key[0x1]; 343 u8 outer_vxlan_vni[0x1]; 344 u8 outer_geneve_vni[0x1]; 345 u8 outer_geneve_oam[0x1]; 346 u8 outer_geneve_protocol_type[0x1]; 347 u8 outer_geneve_opt_len[0x1]; 348 u8 source_vhca_port[0x1]; 349 u8 source_eswitch_port[0x1]; 350 351 u8 inner_dmac[0x1]; 352 u8 inner_smac[0x1]; 353 u8 inner_ether_type[0x1]; 354 u8 inner_ip_version[0x1]; 355 u8 inner_first_prio[0x1]; 356 u8 inner_first_cfi[0x1]; 357 u8 inner_first_vid[0x1]; 358 u8 reserved_at_27[0x1]; 359 u8 inner_second_prio[0x1]; 360 u8 inner_second_cfi[0x1]; 361 u8 inner_second_vid[0x1]; 362 u8 reserved_at_2b[0x1]; 363 u8 inner_sip[0x1]; 364 u8 inner_dip[0x1]; 365 u8 inner_frag[0x1]; 366 u8 inner_ip_protocol[0x1]; 367 u8 inner_ip_ecn[0x1]; 368 u8 inner_ip_dscp[0x1]; 369 u8 inner_udp_sport[0x1]; 370 u8 inner_udp_dport[0x1]; 371 u8 inner_tcp_sport[0x1]; 372 u8 inner_tcp_dport[0x1]; 373 u8 inner_tcp_flags[0x1]; 374 u8 reserved_at_37[0x9]; 375 376 u8 geneve_tlv_option_0_data[0x1]; 377 u8 geneve_tlv_option_0_exist[0x1]; 378 u8 reserved_at_42[0x3]; 379 u8 outer_first_mpls_over_udp[0x4]; 380 u8 outer_first_mpls_over_gre[0x4]; 381 u8 inner_first_mpls[0x4]; 382 u8 outer_first_mpls[0x4]; 383 u8 reserved_at_55[0x2]; 384 u8 outer_esp_spi[0x1]; 385 u8 reserved_at_58[0x2]; 386 u8 bth_dst_qp[0x1]; 387 u8 reserved_at_5b[0x5]; 388 389 u8 reserved_at_60[0x18]; 390 u8 metadata_reg_c_7[0x1]; 391 u8 metadata_reg_c_6[0x1]; 392 u8 metadata_reg_c_5[0x1]; 393 u8 metadata_reg_c_4[0x1]; 394 u8 metadata_reg_c_3[0x1]; 395 u8 metadata_reg_c_2[0x1]; 396 u8 metadata_reg_c_1[0x1]; 397 u8 metadata_reg_c_0[0x1]; 398 }; 399 400 struct mlx5_ifc_flow_table_fields_supported_2_bits { 401 u8 reserved_at_0[0xe]; 402 u8 bth_opcode[0x1]; 403 u8 reserved_at_f[0x11]; 404 405 u8 reserved_at_20[0x60]; 406 }; 407 408 struct mlx5_ifc_flow_table_prop_layout_bits { 409 u8 ft_support[0x1]; 410 u8 reserved_at_1[0x1]; 411 u8 flow_counter[0x1]; 412 u8 flow_modify_en[0x1]; 413 u8 modify_root[0x1]; 414 u8 identified_miss_table_mode[0x1]; 415 u8 flow_table_modify[0x1]; 416 u8 reformat[0x1]; 417 u8 decap[0x1]; 418 u8 reserved_at_9[0x1]; 419 u8 pop_vlan[0x1]; 420 u8 push_vlan[0x1]; 421 u8 reserved_at_c[0x1]; 422 u8 pop_vlan_2[0x1]; 423 u8 push_vlan_2[0x1]; 424 u8 reformat_and_vlan_action[0x1]; 425 u8 reserved_at_10[0x1]; 426 u8 sw_owner[0x1]; 427 u8 reformat_l3_tunnel_to_l2[0x1]; 428 u8 reformat_l2_to_l3_tunnel[0x1]; 429 u8 reformat_and_modify_action[0x1]; 430 u8 ignore_flow_level[0x1]; 431 u8 reserved_at_16[0x1]; 432 u8 table_miss_action_domain[0x1]; 433 u8 termination_table[0x1]; 434 u8 reformat_and_fwd_to_table[0x1]; 435 u8 reserved_at_1a[0x2]; 436 u8 ipsec_encrypt[0x1]; 437 u8 ipsec_decrypt[0x1]; 438 u8 sw_owner_v2[0x1]; 439 u8 reserved_at_1f[0x1]; 440 441 u8 termination_table_raw_traffic[0x1]; 442 u8 reserved_at_21[0x1]; 443 u8 log_max_ft_size[0x6]; 444 u8 log_max_modify_header_context[0x8]; 445 u8 max_modify_header_actions[0x8]; 446 u8 max_ft_level[0x8]; 447 448 u8 reserved_at_40[0x6]; 449 u8 execute_aso[0x1]; 450 u8 reserved_at_47[0x19]; 451 452 u8 reserved_at_60[0x2]; 453 u8 reformat_insert[0x1]; 454 u8 reformat_remove[0x1]; 455 u8 macsec_encrypt[0x1]; 456 u8 macsec_decrypt[0x1]; 457 u8 reserved_at_66[0x2]; 458 u8 reformat_add_macsec[0x1]; 459 u8 reformat_remove_macsec[0x1]; 460 u8 reserved_at_6a[0xe]; 461 u8 log_max_ft_num[0x8]; 462 463 u8 reserved_at_80[0x10]; 464 u8 log_max_flow_counter[0x8]; 465 u8 log_max_destination[0x8]; 466 467 u8 reserved_at_a0[0x18]; 468 u8 log_max_flow[0x8]; 469 470 u8 reserved_at_c0[0x40]; 471 472 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support; 473 474 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support; 475 }; 476 477 struct mlx5_ifc_odp_per_transport_service_cap_bits { 478 u8 send[0x1]; 479 u8 receive[0x1]; 480 u8 write[0x1]; 481 u8 read[0x1]; 482 u8 atomic[0x1]; 483 u8 srq_receive[0x1]; 484 u8 reserved_at_6[0x1a]; 485 }; 486 487 struct mlx5_ifc_ipv4_layout_bits { 488 u8 reserved_at_0[0x60]; 489 490 u8 ipv4[0x20]; 491 }; 492 493 struct mlx5_ifc_ipv6_layout_bits { 494 u8 ipv6[16][0x8]; 495 }; 496 497 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits { 498 struct mlx5_ifc_ipv6_layout_bits ipv6_layout; 499 struct mlx5_ifc_ipv4_layout_bits ipv4_layout; 500 u8 reserved_at_0[0x80]; 501 }; 502 503 struct mlx5_ifc_fte_match_set_lyr_2_4_bits { 504 u8 smac_47_16[0x20]; 505 506 u8 smac_15_0[0x10]; 507 u8 ethertype[0x10]; 508 509 u8 dmac_47_16[0x20]; 510 511 u8 dmac_15_0[0x10]; 512 u8 first_prio[0x3]; 513 u8 first_cfi[0x1]; 514 u8 first_vid[0xc]; 515 516 u8 ip_protocol[0x8]; 517 u8 ip_dscp[0x6]; 518 u8 ip_ecn[0x2]; 519 u8 cvlan_tag[0x1]; 520 u8 svlan_tag[0x1]; 521 u8 frag[0x1]; 522 u8 ip_version[0x4]; 523 u8 tcp_flags[0x9]; 524 525 u8 tcp_sport[0x10]; 526 u8 tcp_dport[0x10]; 527 528 u8 reserved_at_c0[0x10]; 529 u8 ipv4_ihl[0x4]; 530 u8 reserved_at_c4[0x4]; 531 532 u8 ttl_hoplimit[0x8]; 533 534 u8 udp_sport[0x10]; 535 u8 udp_dport[0x10]; 536 537 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6; 538 539 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6; 540 }; 541 542 struct mlx5_ifc_nvgre_key_bits { 543 u8 hi[0x18]; 544 u8 lo[0x8]; 545 }; 546 547 union mlx5_ifc_gre_key_bits { 548 struct mlx5_ifc_nvgre_key_bits nvgre; 549 u8 key[0x20]; 550 }; 551 552 struct mlx5_ifc_fte_match_set_misc_bits { 553 u8 gre_c_present[0x1]; 554 u8 reserved_at_1[0x1]; 555 u8 gre_k_present[0x1]; 556 u8 gre_s_present[0x1]; 557 u8 source_vhca_port[0x4]; 558 u8 source_sqn[0x18]; 559 560 u8 source_eswitch_owner_vhca_id[0x10]; 561 u8 source_port[0x10]; 562 563 u8 outer_second_prio[0x3]; 564 u8 outer_second_cfi[0x1]; 565 u8 outer_second_vid[0xc]; 566 u8 inner_second_prio[0x3]; 567 u8 inner_second_cfi[0x1]; 568 u8 inner_second_vid[0xc]; 569 570 u8 outer_second_cvlan_tag[0x1]; 571 u8 inner_second_cvlan_tag[0x1]; 572 u8 outer_second_svlan_tag[0x1]; 573 u8 inner_second_svlan_tag[0x1]; 574 u8 reserved_at_64[0xc]; 575 u8 gre_protocol[0x10]; 576 577 union mlx5_ifc_gre_key_bits gre_key; 578 579 u8 vxlan_vni[0x18]; 580 u8 bth_opcode[0x8]; 581 582 u8 geneve_vni[0x18]; 583 u8 reserved_at_d8[0x6]; 584 u8 geneve_tlv_option_0_exist[0x1]; 585 u8 geneve_oam[0x1]; 586 587 u8 reserved_at_e0[0xc]; 588 u8 outer_ipv6_flow_label[0x14]; 589 590 u8 reserved_at_100[0xc]; 591 u8 inner_ipv6_flow_label[0x14]; 592 593 u8 reserved_at_120[0xa]; 594 u8 geneve_opt_len[0x6]; 595 u8 geneve_protocol_type[0x10]; 596 597 u8 reserved_at_140[0x8]; 598 u8 bth_dst_qp[0x18]; 599 u8 reserved_at_160[0x20]; 600 u8 outer_esp_spi[0x20]; 601 u8 reserved_at_1a0[0x60]; 602 }; 603 604 struct mlx5_ifc_fte_match_mpls_bits { 605 u8 mpls_label[0x14]; 606 u8 mpls_exp[0x3]; 607 u8 mpls_s_bos[0x1]; 608 u8 mpls_ttl[0x8]; 609 }; 610 611 struct mlx5_ifc_fte_match_set_misc2_bits { 612 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls; 613 614 struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls; 615 616 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre; 617 618 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp; 619 620 u8 metadata_reg_c_7[0x20]; 621 622 u8 metadata_reg_c_6[0x20]; 623 624 u8 metadata_reg_c_5[0x20]; 625 626 u8 metadata_reg_c_4[0x20]; 627 628 u8 metadata_reg_c_3[0x20]; 629 630 u8 metadata_reg_c_2[0x20]; 631 632 u8 metadata_reg_c_1[0x20]; 633 634 u8 metadata_reg_c_0[0x20]; 635 636 u8 metadata_reg_a[0x20]; 637 638 u8 reserved_at_1a0[0x8]; 639 640 u8 macsec_syndrome[0x8]; 641 642 u8 reserved_at_1b0[0x50]; 643 }; 644 645 struct mlx5_ifc_fte_match_set_misc3_bits { 646 u8 inner_tcp_seq_num[0x20]; 647 648 u8 outer_tcp_seq_num[0x20]; 649 650 u8 inner_tcp_ack_num[0x20]; 651 652 u8 outer_tcp_ack_num[0x20]; 653 654 u8 reserved_at_80[0x8]; 655 u8 outer_vxlan_gpe_vni[0x18]; 656 657 u8 outer_vxlan_gpe_next_protocol[0x8]; 658 u8 outer_vxlan_gpe_flags[0x8]; 659 u8 reserved_at_b0[0x10]; 660 661 u8 icmp_header_data[0x20]; 662 663 u8 icmpv6_header_data[0x20]; 664 665 u8 icmp_type[0x8]; 666 u8 icmp_code[0x8]; 667 u8 icmpv6_type[0x8]; 668 u8 icmpv6_code[0x8]; 669 670 u8 geneve_tlv_option_0_data[0x20]; 671 672 u8 gtpu_teid[0x20]; 673 674 u8 gtpu_msg_type[0x8]; 675 u8 gtpu_msg_flags[0x8]; 676 u8 reserved_at_170[0x10]; 677 678 u8 gtpu_dw_2[0x20]; 679 680 u8 gtpu_first_ext_dw_0[0x20]; 681 682 u8 gtpu_dw_0[0x20]; 683 684 u8 reserved_at_1e0[0x20]; 685 }; 686 687 struct mlx5_ifc_fte_match_set_misc4_bits { 688 u8 prog_sample_field_value_0[0x20]; 689 690 u8 prog_sample_field_id_0[0x20]; 691 692 u8 prog_sample_field_value_1[0x20]; 693 694 u8 prog_sample_field_id_1[0x20]; 695 696 u8 prog_sample_field_value_2[0x20]; 697 698 u8 prog_sample_field_id_2[0x20]; 699 700 u8 prog_sample_field_value_3[0x20]; 701 702 u8 prog_sample_field_id_3[0x20]; 703 704 u8 reserved_at_100[0x100]; 705 }; 706 707 struct mlx5_ifc_fte_match_set_misc5_bits { 708 u8 macsec_tag_0[0x20]; 709 710 u8 macsec_tag_1[0x20]; 711 712 u8 macsec_tag_2[0x20]; 713 714 u8 macsec_tag_3[0x20]; 715 716 u8 tunnel_header_0[0x20]; 717 718 u8 tunnel_header_1[0x20]; 719 720 u8 tunnel_header_2[0x20]; 721 722 u8 tunnel_header_3[0x20]; 723 724 u8 reserved_at_100[0x100]; 725 }; 726 727 struct mlx5_ifc_cmd_pas_bits { 728 u8 pa_h[0x20]; 729 730 u8 pa_l[0x14]; 731 u8 reserved_at_34[0xc]; 732 }; 733 734 struct mlx5_ifc_uint64_bits { 735 u8 hi[0x20]; 736 737 u8 lo[0x20]; 738 }; 739 740 enum { 741 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0, 742 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7, 743 MLX5_ADS_STAT_RATE_10GBPS = 0x8, 744 MLX5_ADS_STAT_RATE_30GBPS = 0x9, 745 MLX5_ADS_STAT_RATE_5GBPS = 0xa, 746 MLX5_ADS_STAT_RATE_20GBPS = 0xb, 747 MLX5_ADS_STAT_RATE_40GBPS = 0xc, 748 MLX5_ADS_STAT_RATE_60GBPS = 0xd, 749 MLX5_ADS_STAT_RATE_80GBPS = 0xe, 750 MLX5_ADS_STAT_RATE_120GBPS = 0xf, 751 }; 752 753 struct mlx5_ifc_ads_bits { 754 u8 fl[0x1]; 755 u8 free_ar[0x1]; 756 u8 reserved_at_2[0xe]; 757 u8 pkey_index[0x10]; 758 759 u8 reserved_at_20[0x8]; 760 u8 grh[0x1]; 761 u8 mlid[0x7]; 762 u8 rlid[0x10]; 763 764 u8 ack_timeout[0x5]; 765 u8 reserved_at_45[0x3]; 766 u8 src_addr_index[0x8]; 767 u8 reserved_at_50[0x4]; 768 u8 stat_rate[0x4]; 769 u8 hop_limit[0x8]; 770 771 u8 reserved_at_60[0x4]; 772 u8 tclass[0x8]; 773 u8 flow_label[0x14]; 774 775 u8 rgid_rip[16][0x8]; 776 777 u8 reserved_at_100[0x4]; 778 u8 f_dscp[0x1]; 779 u8 f_ecn[0x1]; 780 u8 reserved_at_106[0x1]; 781 u8 f_eth_prio[0x1]; 782 u8 ecn[0x2]; 783 u8 dscp[0x6]; 784 u8 udp_sport[0x10]; 785 786 u8 dei_cfi[0x1]; 787 u8 eth_prio[0x3]; 788 u8 sl[0x4]; 789 u8 vhca_port_num[0x8]; 790 u8 rmac_47_32[0x10]; 791 792 u8 rmac_31_0[0x20]; 793 }; 794 795 struct mlx5_ifc_flow_table_nic_cap_bits { 796 u8 nic_rx_multi_path_tirs[0x1]; 797 u8 nic_rx_multi_path_tirs_fts[0x1]; 798 u8 allow_sniffer_and_nic_rx_shared_tir[0x1]; 799 u8 reserved_at_3[0x4]; 800 u8 sw_owner_reformat_supported[0x1]; 801 u8 reserved_at_8[0x18]; 802 803 u8 encap_general_header[0x1]; 804 u8 reserved_at_21[0xa]; 805 u8 log_max_packet_reformat_context[0x5]; 806 u8 reserved_at_30[0x6]; 807 u8 max_encap_header_size[0xa]; 808 u8 reserved_at_40[0x1c0]; 809 810 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive; 811 812 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_rdma; 813 814 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer; 815 816 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit; 817 818 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_rdma; 819 820 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer; 821 822 u8 reserved_at_e00[0x700]; 823 824 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_receive_rdma; 825 826 u8 reserved_at_1580[0x280]; 827 828 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_transmit_rdma; 829 830 u8 reserved_at_1880[0x780]; 831 832 u8 sw_steering_nic_rx_action_drop_icm_address[0x40]; 833 834 u8 sw_steering_nic_tx_action_drop_icm_address[0x40]; 835 836 u8 sw_steering_nic_tx_action_allow_icm_address[0x40]; 837 838 u8 reserved_at_20c0[0x5f40]; 839 }; 840 841 struct mlx5_ifc_port_selection_cap_bits { 842 u8 reserved_at_0[0x10]; 843 u8 port_select_flow_table[0x1]; 844 u8 reserved_at_11[0x1]; 845 u8 port_select_flow_table_bypass[0x1]; 846 u8 reserved_at_13[0xd]; 847 848 u8 reserved_at_20[0x1e0]; 849 850 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_port_selection; 851 852 u8 reserved_at_400[0x7c00]; 853 }; 854 855 enum { 856 MLX5_FDB_TO_VPORT_REG_C_0 = 0x01, 857 MLX5_FDB_TO_VPORT_REG_C_1 = 0x02, 858 MLX5_FDB_TO_VPORT_REG_C_2 = 0x04, 859 MLX5_FDB_TO_VPORT_REG_C_3 = 0x08, 860 MLX5_FDB_TO_VPORT_REG_C_4 = 0x10, 861 MLX5_FDB_TO_VPORT_REG_C_5 = 0x20, 862 MLX5_FDB_TO_VPORT_REG_C_6 = 0x40, 863 MLX5_FDB_TO_VPORT_REG_C_7 = 0x80, 864 }; 865 866 struct mlx5_ifc_flow_table_eswitch_cap_bits { 867 u8 fdb_to_vport_reg_c_id[0x8]; 868 u8 reserved_at_8[0xd]; 869 u8 fdb_modify_header_fwd_to_table[0x1]; 870 u8 fdb_ipv4_ttl_modify[0x1]; 871 u8 flow_source[0x1]; 872 u8 reserved_at_18[0x2]; 873 u8 multi_fdb_encap[0x1]; 874 u8 egress_acl_forward_to_vport[0x1]; 875 u8 fdb_multi_path_to_table[0x1]; 876 u8 reserved_at_1d[0x3]; 877 878 u8 reserved_at_20[0x1e0]; 879 880 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb; 881 882 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress; 883 884 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress; 885 886 u8 reserved_at_800[0x1000]; 887 888 u8 sw_steering_fdb_action_drop_icm_address_rx[0x40]; 889 890 u8 sw_steering_fdb_action_drop_icm_address_tx[0x40]; 891 892 u8 sw_steering_uplink_icm_address_rx[0x40]; 893 894 u8 sw_steering_uplink_icm_address_tx[0x40]; 895 896 u8 reserved_at_1900[0x6700]; 897 }; 898 899 enum { 900 MLX5_COUNTER_SOURCE_ESWITCH = 0x0, 901 MLX5_COUNTER_FLOW_ESWITCH = 0x1, 902 }; 903 904 struct mlx5_ifc_e_switch_cap_bits { 905 u8 vport_svlan_strip[0x1]; 906 u8 vport_cvlan_strip[0x1]; 907 u8 vport_svlan_insert[0x1]; 908 u8 vport_cvlan_insert_if_not_exist[0x1]; 909 u8 vport_cvlan_insert_overwrite[0x1]; 910 u8 reserved_at_5[0x2]; 911 u8 esw_shared_ingress_acl[0x1]; 912 u8 esw_uplink_ingress_acl[0x1]; 913 u8 root_ft_on_other_esw[0x1]; 914 u8 reserved_at_a[0xf]; 915 u8 esw_functions_changed[0x1]; 916 u8 reserved_at_1a[0x1]; 917 u8 ecpf_vport_exists[0x1]; 918 u8 counter_eswitch_affinity[0x1]; 919 u8 merged_eswitch[0x1]; 920 u8 nic_vport_node_guid_modify[0x1]; 921 u8 nic_vport_port_guid_modify[0x1]; 922 923 u8 vxlan_encap_decap[0x1]; 924 u8 nvgre_encap_decap[0x1]; 925 u8 reserved_at_22[0x1]; 926 u8 log_max_fdb_encap_uplink[0x5]; 927 u8 reserved_at_21[0x3]; 928 u8 log_max_packet_reformat_context[0x5]; 929 u8 reserved_2b[0x6]; 930 u8 max_encap_header_size[0xa]; 931 932 u8 reserved_at_40[0xb]; 933 u8 log_max_esw_sf[0x5]; 934 u8 esw_sf_base_id[0x10]; 935 936 u8 reserved_at_60[0x7a0]; 937 938 }; 939 940 struct mlx5_ifc_qos_cap_bits { 941 u8 packet_pacing[0x1]; 942 u8 esw_scheduling[0x1]; 943 u8 esw_bw_share[0x1]; 944 u8 esw_rate_limit[0x1]; 945 u8 reserved_at_4[0x1]; 946 u8 packet_pacing_burst_bound[0x1]; 947 u8 packet_pacing_typical_size[0x1]; 948 u8 reserved_at_7[0x1]; 949 u8 nic_sq_scheduling[0x1]; 950 u8 nic_bw_share[0x1]; 951 u8 nic_rate_limit[0x1]; 952 u8 packet_pacing_uid[0x1]; 953 u8 log_esw_max_sched_depth[0x4]; 954 u8 reserved_at_10[0x10]; 955 956 u8 reserved_at_20[0xb]; 957 u8 log_max_qos_nic_queue_group[0x5]; 958 u8 reserved_at_30[0x10]; 959 960 u8 packet_pacing_max_rate[0x20]; 961 962 u8 packet_pacing_min_rate[0x20]; 963 964 u8 reserved_at_80[0x10]; 965 u8 packet_pacing_rate_table_size[0x10]; 966 967 u8 esw_element_type[0x10]; 968 u8 esw_tsar_type[0x10]; 969 970 u8 reserved_at_c0[0x10]; 971 u8 max_qos_para_vport[0x10]; 972 973 u8 max_tsar_bw_share[0x20]; 974 975 u8 reserved_at_100[0x20]; 976 977 u8 reserved_at_120[0x3]; 978 u8 log_meter_aso_granularity[0x5]; 979 u8 reserved_at_128[0x3]; 980 u8 log_meter_aso_max_alloc[0x5]; 981 u8 reserved_at_130[0x3]; 982 u8 log_max_num_meter_aso[0x5]; 983 u8 reserved_at_138[0x8]; 984 985 u8 reserved_at_140[0x6c0]; 986 }; 987 988 struct mlx5_ifc_debug_cap_bits { 989 u8 core_dump_general[0x1]; 990 u8 core_dump_qp[0x1]; 991 u8 reserved_at_2[0x7]; 992 u8 resource_dump[0x1]; 993 u8 reserved_at_a[0x16]; 994 995 u8 reserved_at_20[0x2]; 996 u8 stall_detect[0x1]; 997 u8 reserved_at_23[0x1d]; 998 999 u8 reserved_at_40[0x7c0]; 1000 }; 1001 1002 struct mlx5_ifc_per_protocol_networking_offload_caps_bits { 1003 u8 csum_cap[0x1]; 1004 u8 vlan_cap[0x1]; 1005 u8 lro_cap[0x1]; 1006 u8 lro_psh_flag[0x1]; 1007 u8 lro_time_stamp[0x1]; 1008 u8 reserved_at_5[0x2]; 1009 u8 wqe_vlan_insert[0x1]; 1010 u8 self_lb_en_modifiable[0x1]; 1011 u8 reserved_at_9[0x2]; 1012 u8 max_lso_cap[0x5]; 1013 u8 multi_pkt_send_wqe[0x2]; 1014 u8 wqe_inline_mode[0x2]; 1015 u8 rss_ind_tbl_cap[0x4]; 1016 u8 reg_umr_sq[0x1]; 1017 u8 scatter_fcs[0x1]; 1018 u8 enhanced_multi_pkt_send_wqe[0x1]; 1019 u8 tunnel_lso_const_out_ip_id[0x1]; 1020 u8 tunnel_lro_gre[0x1]; 1021 u8 tunnel_lro_vxlan[0x1]; 1022 u8 tunnel_stateless_gre[0x1]; 1023 u8 tunnel_stateless_vxlan[0x1]; 1024 1025 u8 swp[0x1]; 1026 u8 swp_csum[0x1]; 1027 u8 swp_lso[0x1]; 1028 u8 cqe_checksum_full[0x1]; 1029 u8 tunnel_stateless_geneve_tx[0x1]; 1030 u8 tunnel_stateless_mpls_over_udp[0x1]; 1031 u8 tunnel_stateless_mpls_over_gre[0x1]; 1032 u8 tunnel_stateless_vxlan_gpe[0x1]; 1033 u8 tunnel_stateless_ipv4_over_vxlan[0x1]; 1034 u8 tunnel_stateless_ip_over_ip[0x1]; 1035 u8 insert_trailer[0x1]; 1036 u8 reserved_at_2b[0x1]; 1037 u8 tunnel_stateless_ip_over_ip_rx[0x1]; 1038 u8 tunnel_stateless_ip_over_ip_tx[0x1]; 1039 u8 reserved_at_2e[0x2]; 1040 u8 max_vxlan_udp_ports[0x8]; 1041 u8 reserved_at_38[0x6]; 1042 u8 max_geneve_opt_len[0x1]; 1043 u8 tunnel_stateless_geneve_rx[0x1]; 1044 1045 u8 reserved_at_40[0x10]; 1046 u8 lro_min_mss_size[0x10]; 1047 1048 u8 reserved_at_60[0x120]; 1049 1050 u8 lro_timer_supported_periods[4][0x20]; 1051 1052 u8 reserved_at_200[0x600]; 1053 }; 1054 1055 enum { 1056 MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING = 0x0, 1057 MLX5_TIMESTAMP_FORMAT_CAP_REAL_TIME = 0x1, 1058 MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING_AND_REAL_TIME = 0x2, 1059 }; 1060 1061 struct mlx5_ifc_roce_cap_bits { 1062 u8 roce_apm[0x1]; 1063 u8 reserved_at_1[0x3]; 1064 u8 sw_r_roce_src_udp_port[0x1]; 1065 u8 fl_rc_qp_when_roce_disabled[0x1]; 1066 u8 fl_rc_qp_when_roce_enabled[0x1]; 1067 u8 reserved_at_7[0x17]; 1068 u8 qp_ts_format[0x2]; 1069 1070 u8 reserved_at_20[0x60]; 1071 1072 u8 reserved_at_80[0xc]; 1073 u8 l3_type[0x4]; 1074 u8 reserved_at_90[0x8]; 1075 u8 roce_version[0x8]; 1076 1077 u8 reserved_at_a0[0x10]; 1078 u8 r_roce_dest_udp_port[0x10]; 1079 1080 u8 r_roce_max_src_udp_port[0x10]; 1081 u8 r_roce_min_src_udp_port[0x10]; 1082 1083 u8 reserved_at_e0[0x10]; 1084 u8 roce_address_table_size[0x10]; 1085 1086 u8 reserved_at_100[0x700]; 1087 }; 1088 1089 struct mlx5_ifc_sync_steering_in_bits { 1090 u8 opcode[0x10]; 1091 u8 uid[0x10]; 1092 1093 u8 reserved_at_20[0x10]; 1094 u8 op_mod[0x10]; 1095 1096 u8 reserved_at_40[0xc0]; 1097 }; 1098 1099 struct mlx5_ifc_sync_steering_out_bits { 1100 u8 status[0x8]; 1101 u8 reserved_at_8[0x18]; 1102 1103 u8 syndrome[0x20]; 1104 1105 u8 reserved_at_40[0x40]; 1106 }; 1107 1108 struct mlx5_ifc_device_mem_cap_bits { 1109 u8 memic[0x1]; 1110 u8 reserved_at_1[0x1f]; 1111 1112 u8 reserved_at_20[0xb]; 1113 u8 log_min_memic_alloc_size[0x5]; 1114 u8 reserved_at_30[0x8]; 1115 u8 log_max_memic_addr_alignment[0x8]; 1116 1117 u8 memic_bar_start_addr[0x40]; 1118 1119 u8 memic_bar_size[0x20]; 1120 1121 u8 max_memic_size[0x20]; 1122 1123 u8 steering_sw_icm_start_address[0x40]; 1124 1125 u8 reserved_at_100[0x8]; 1126 u8 log_header_modify_sw_icm_size[0x8]; 1127 u8 reserved_at_110[0x2]; 1128 u8 log_sw_icm_alloc_granularity[0x6]; 1129 u8 log_steering_sw_icm_size[0x8]; 1130 1131 u8 reserved_at_120[0x18]; 1132 u8 log_header_modify_pattern_sw_icm_size[0x8]; 1133 1134 u8 header_modify_sw_icm_start_address[0x40]; 1135 1136 u8 reserved_at_180[0x40]; 1137 1138 u8 header_modify_pattern_sw_icm_start_address[0x40]; 1139 1140 u8 memic_operations[0x20]; 1141 1142 u8 reserved_at_220[0x5e0]; 1143 }; 1144 1145 struct mlx5_ifc_device_event_cap_bits { 1146 u8 user_affiliated_events[4][0x40]; 1147 1148 u8 user_unaffiliated_events[4][0x40]; 1149 }; 1150 1151 struct mlx5_ifc_virtio_emulation_cap_bits { 1152 u8 desc_tunnel_offload_type[0x1]; 1153 u8 eth_frame_offload_type[0x1]; 1154 u8 virtio_version_1_0[0x1]; 1155 u8 device_features_bits_mask[0xd]; 1156 u8 event_mode[0x8]; 1157 u8 virtio_queue_type[0x8]; 1158 1159 u8 max_tunnel_desc[0x10]; 1160 u8 reserved_at_30[0x3]; 1161 u8 log_doorbell_stride[0x5]; 1162 u8 reserved_at_38[0x3]; 1163 u8 log_doorbell_bar_size[0x5]; 1164 1165 u8 doorbell_bar_offset[0x40]; 1166 1167 u8 max_emulated_devices[0x8]; 1168 u8 max_num_virtio_queues[0x18]; 1169 1170 u8 reserved_at_a0[0x60]; 1171 1172 u8 umem_1_buffer_param_a[0x20]; 1173 1174 u8 umem_1_buffer_param_b[0x20]; 1175 1176 u8 umem_2_buffer_param_a[0x20]; 1177 1178 u8 umem_2_buffer_param_b[0x20]; 1179 1180 u8 umem_3_buffer_param_a[0x20]; 1181 1182 u8 umem_3_buffer_param_b[0x20]; 1183 1184 u8 reserved_at_1c0[0x640]; 1185 }; 1186 1187 enum { 1188 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0, 1189 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2, 1190 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4, 1191 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8, 1192 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10, 1193 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20, 1194 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40, 1195 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80, 1196 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100, 1197 }; 1198 1199 enum { 1200 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1, 1201 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2, 1202 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4, 1203 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8, 1204 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10, 1205 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20, 1206 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40, 1207 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80, 1208 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100, 1209 }; 1210 1211 struct mlx5_ifc_atomic_caps_bits { 1212 u8 reserved_at_0[0x40]; 1213 1214 u8 atomic_req_8B_endianness_mode[0x2]; 1215 u8 reserved_at_42[0x4]; 1216 u8 supported_atomic_req_8B_endianness_mode_1[0x1]; 1217 1218 u8 reserved_at_47[0x19]; 1219 1220 u8 reserved_at_60[0x20]; 1221 1222 u8 reserved_at_80[0x10]; 1223 u8 atomic_operations[0x10]; 1224 1225 u8 reserved_at_a0[0x10]; 1226 u8 atomic_size_qp[0x10]; 1227 1228 u8 reserved_at_c0[0x10]; 1229 u8 atomic_size_dc[0x10]; 1230 1231 u8 reserved_at_e0[0x720]; 1232 }; 1233 1234 struct mlx5_ifc_odp_cap_bits { 1235 u8 reserved_at_0[0x40]; 1236 1237 u8 sig[0x1]; 1238 u8 reserved_at_41[0x1f]; 1239 1240 u8 reserved_at_60[0x20]; 1241 1242 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps; 1243 1244 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps; 1245 1246 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps; 1247 1248 struct mlx5_ifc_odp_per_transport_service_cap_bits xrc_odp_caps; 1249 1250 struct mlx5_ifc_odp_per_transport_service_cap_bits dc_odp_caps; 1251 1252 u8 reserved_at_120[0x6E0]; 1253 }; 1254 1255 struct mlx5_ifc_calc_op { 1256 u8 reserved_at_0[0x10]; 1257 u8 reserved_at_10[0x9]; 1258 u8 op_swap_endianness[0x1]; 1259 u8 op_min[0x1]; 1260 u8 op_xor[0x1]; 1261 u8 op_or[0x1]; 1262 u8 op_and[0x1]; 1263 u8 op_max[0x1]; 1264 u8 op_add[0x1]; 1265 }; 1266 1267 struct mlx5_ifc_vector_calc_cap_bits { 1268 u8 calc_matrix[0x1]; 1269 u8 reserved_at_1[0x1f]; 1270 u8 reserved_at_20[0x8]; 1271 u8 max_vec_count[0x8]; 1272 u8 reserved_at_30[0xd]; 1273 u8 max_chunk_size[0x3]; 1274 struct mlx5_ifc_calc_op calc0; 1275 struct mlx5_ifc_calc_op calc1; 1276 struct mlx5_ifc_calc_op calc2; 1277 struct mlx5_ifc_calc_op calc3; 1278 1279 u8 reserved_at_c0[0x720]; 1280 }; 1281 1282 struct mlx5_ifc_tls_cap_bits { 1283 u8 tls_1_2_aes_gcm_128[0x1]; 1284 u8 tls_1_3_aes_gcm_128[0x1]; 1285 u8 tls_1_2_aes_gcm_256[0x1]; 1286 u8 tls_1_3_aes_gcm_256[0x1]; 1287 u8 reserved_at_4[0x1c]; 1288 1289 u8 reserved_at_20[0x7e0]; 1290 }; 1291 1292 struct mlx5_ifc_ipsec_cap_bits { 1293 u8 ipsec_full_offload[0x1]; 1294 u8 ipsec_crypto_offload[0x1]; 1295 u8 ipsec_esn[0x1]; 1296 u8 ipsec_crypto_esp_aes_gcm_256_encrypt[0x1]; 1297 u8 ipsec_crypto_esp_aes_gcm_128_encrypt[0x1]; 1298 u8 ipsec_crypto_esp_aes_gcm_256_decrypt[0x1]; 1299 u8 ipsec_crypto_esp_aes_gcm_128_decrypt[0x1]; 1300 u8 reserved_at_7[0x4]; 1301 u8 log_max_ipsec_offload[0x5]; 1302 u8 reserved_at_10[0x10]; 1303 1304 u8 min_log_ipsec_full_replay_window[0x8]; 1305 u8 max_log_ipsec_full_replay_window[0x8]; 1306 u8 reserved_at_30[0x7d0]; 1307 }; 1308 1309 struct mlx5_ifc_macsec_cap_bits { 1310 u8 macsec_epn[0x1]; 1311 u8 reserved_at_1[0x2]; 1312 u8 macsec_crypto_esp_aes_gcm_256_encrypt[0x1]; 1313 u8 macsec_crypto_esp_aes_gcm_128_encrypt[0x1]; 1314 u8 macsec_crypto_esp_aes_gcm_256_decrypt[0x1]; 1315 u8 macsec_crypto_esp_aes_gcm_128_decrypt[0x1]; 1316 u8 reserved_at_7[0x4]; 1317 u8 log_max_macsec_offload[0x5]; 1318 u8 reserved_at_10[0x10]; 1319 1320 u8 min_log_macsec_full_replay_window[0x8]; 1321 u8 max_log_macsec_full_replay_window[0x8]; 1322 u8 reserved_at_30[0x10]; 1323 1324 u8 reserved_at_40[0x7c0]; 1325 }; 1326 1327 enum { 1328 MLX5_WQ_TYPE_LINKED_LIST = 0x0, 1329 MLX5_WQ_TYPE_CYCLIC = 0x1, 1330 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2, 1331 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3, 1332 }; 1333 1334 enum { 1335 MLX5_WQ_END_PAD_MODE_NONE = 0x0, 1336 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1, 1337 }; 1338 1339 enum { 1340 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0, 1341 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1, 1342 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2, 1343 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3, 1344 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4, 1345 }; 1346 1347 enum { 1348 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0, 1349 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1, 1350 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2, 1351 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3, 1352 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4, 1353 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5, 1354 }; 1355 1356 enum { 1357 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0, 1358 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1, 1359 }; 1360 1361 enum { 1362 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0, 1363 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1, 1364 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3, 1365 }; 1366 1367 enum { 1368 MLX5_CAP_PORT_TYPE_IB = 0x0, 1369 MLX5_CAP_PORT_TYPE_ETH = 0x1, 1370 }; 1371 1372 enum { 1373 MLX5_CAP_UMR_FENCE_STRONG = 0x0, 1374 MLX5_CAP_UMR_FENCE_SMALL = 0x1, 1375 MLX5_CAP_UMR_FENCE_NONE = 0x2, 1376 }; 1377 1378 enum { 1379 MLX5_FLEX_PARSER_GENEVE_ENABLED = 1 << 3, 1380 MLX5_FLEX_PARSER_MPLS_OVER_GRE_ENABLED = 1 << 4, 1381 MLX5_FLEX_PARSER_MPLS_OVER_UDP_ENABLED = 1 << 5, 1382 MLX5_FLEX_PARSER_VXLAN_GPE_ENABLED = 1 << 7, 1383 MLX5_FLEX_PARSER_ICMP_V4_ENABLED = 1 << 8, 1384 MLX5_FLEX_PARSER_ICMP_V6_ENABLED = 1 << 9, 1385 MLX5_FLEX_PARSER_GENEVE_TLV_OPTION_0_ENABLED = 1 << 10, 1386 MLX5_FLEX_PARSER_GTPU_ENABLED = 1 << 11, 1387 MLX5_FLEX_PARSER_GTPU_DW_2_ENABLED = 1 << 16, 1388 MLX5_FLEX_PARSER_GTPU_FIRST_EXT_DW_0_ENABLED = 1 << 17, 1389 MLX5_FLEX_PARSER_GTPU_DW_0_ENABLED = 1 << 18, 1390 MLX5_FLEX_PARSER_GTPU_TEID_ENABLED = 1 << 19, 1391 }; 1392 1393 enum { 1394 MLX5_UCTX_CAP_RAW_TX = 1UL << 0, 1395 MLX5_UCTX_CAP_INTERNAL_DEV_RES = 1UL << 1, 1396 }; 1397 1398 #define MLX5_FC_BULK_SIZE_FACTOR 128 1399 1400 enum mlx5_fc_bulk_alloc_bitmask { 1401 MLX5_FC_BULK_128 = (1 << 0), 1402 MLX5_FC_BULK_256 = (1 << 1), 1403 MLX5_FC_BULK_512 = (1 << 2), 1404 MLX5_FC_BULK_1024 = (1 << 3), 1405 MLX5_FC_BULK_2048 = (1 << 4), 1406 MLX5_FC_BULK_4096 = (1 << 5), 1407 MLX5_FC_BULK_8192 = (1 << 6), 1408 MLX5_FC_BULK_16384 = (1 << 7), 1409 }; 1410 1411 #define MLX5_FC_BULK_NUM_FCS(fc_enum) (MLX5_FC_BULK_SIZE_FACTOR * (fc_enum)) 1412 1413 #define MLX5_FT_MAX_MULTIPATH_LEVEL 63 1414 1415 enum { 1416 MLX5_STEERING_FORMAT_CONNECTX_5 = 0, 1417 MLX5_STEERING_FORMAT_CONNECTX_6DX = 1, 1418 MLX5_STEERING_FORMAT_CONNECTX_7 = 2, 1419 }; 1420 1421 struct mlx5_ifc_cmd_hca_cap_bits { 1422 u8 reserved_at_0[0x10]; 1423 u8 shared_object_to_user_object_allowed[0x1]; 1424 u8 reserved_at_13[0xe]; 1425 u8 vhca_resource_manager[0x1]; 1426 1427 u8 hca_cap_2[0x1]; 1428 u8 create_lag_when_not_master_up[0x1]; 1429 u8 dtor[0x1]; 1430 u8 event_on_vhca_state_teardown_request[0x1]; 1431 u8 event_on_vhca_state_in_use[0x1]; 1432 u8 event_on_vhca_state_active[0x1]; 1433 u8 event_on_vhca_state_allocated[0x1]; 1434 u8 event_on_vhca_state_invalid[0x1]; 1435 u8 reserved_at_28[0x8]; 1436 u8 vhca_id[0x10]; 1437 1438 u8 reserved_at_40[0x40]; 1439 1440 u8 log_max_srq_sz[0x8]; 1441 u8 log_max_qp_sz[0x8]; 1442 u8 event_cap[0x1]; 1443 u8 reserved_at_91[0x2]; 1444 u8 isolate_vl_tc_new[0x1]; 1445 u8 reserved_at_94[0x4]; 1446 u8 prio_tag_required[0x1]; 1447 u8 reserved_at_99[0x2]; 1448 u8 log_max_qp[0x5]; 1449 1450 u8 reserved_at_a0[0x3]; 1451 u8 ece_support[0x1]; 1452 u8 reserved_at_a4[0x5]; 1453 u8 reg_c_preserve[0x1]; 1454 u8 reserved_at_aa[0x1]; 1455 u8 log_max_srq[0x5]; 1456 u8 reserved_at_b0[0x1]; 1457 u8 uplink_follow[0x1]; 1458 u8 ts_cqe_to_dest_cqn[0x1]; 1459 u8 reserved_at_b3[0x7]; 1460 u8 shampo[0x1]; 1461 u8 reserved_at_bb[0x5]; 1462 1463 u8 max_sgl_for_optimized_performance[0x8]; 1464 u8 log_max_cq_sz[0x8]; 1465 u8 relaxed_ordering_write_umr[0x1]; 1466 u8 relaxed_ordering_read_umr[0x1]; 1467 u8 reserved_at_d2[0x7]; 1468 u8 virtio_net_device_emualtion_manager[0x1]; 1469 u8 virtio_blk_device_emualtion_manager[0x1]; 1470 u8 log_max_cq[0x5]; 1471 1472 u8 log_max_eq_sz[0x8]; 1473 u8 relaxed_ordering_write[0x1]; 1474 u8 relaxed_ordering_read[0x1]; 1475 u8 log_max_mkey[0x6]; 1476 u8 reserved_at_f0[0x8]; 1477 u8 dump_fill_mkey[0x1]; 1478 u8 reserved_at_f9[0x2]; 1479 u8 fast_teardown[0x1]; 1480 u8 log_max_eq[0x4]; 1481 1482 u8 max_indirection[0x8]; 1483 u8 fixed_buffer_size[0x1]; 1484 u8 log_max_mrw_sz[0x7]; 1485 u8 force_teardown[0x1]; 1486 u8 reserved_at_111[0x1]; 1487 u8 log_max_bsf_list_size[0x6]; 1488 u8 umr_extended_translation_offset[0x1]; 1489 u8 null_mkey[0x1]; 1490 u8 log_max_klm_list_size[0x6]; 1491 1492 u8 reserved_at_120[0xa]; 1493 u8 log_max_ra_req_dc[0x6]; 1494 u8 reserved_at_130[0x2]; 1495 u8 eth_wqe_too_small[0x1]; 1496 u8 reserved_at_133[0x6]; 1497 u8 vnic_env_cq_overrun[0x1]; 1498 u8 log_max_ra_res_dc[0x6]; 1499 1500 u8 reserved_at_140[0x5]; 1501 u8 release_all_pages[0x1]; 1502 u8 must_not_use[0x1]; 1503 u8 reserved_at_147[0x2]; 1504 u8 roce_accl[0x1]; 1505 u8 log_max_ra_req_qp[0x6]; 1506 u8 reserved_at_150[0xa]; 1507 u8 log_max_ra_res_qp[0x6]; 1508 1509 u8 end_pad[0x1]; 1510 u8 cc_query_allowed[0x1]; 1511 u8 cc_modify_allowed[0x1]; 1512 u8 start_pad[0x1]; 1513 u8 cache_line_128byte[0x1]; 1514 u8 reserved_at_165[0x4]; 1515 u8 rts2rts_qp_counters_set_id[0x1]; 1516 u8 reserved_at_16a[0x2]; 1517 u8 vnic_env_int_rq_oob[0x1]; 1518 u8 sbcam_reg[0x1]; 1519 u8 reserved_at_16e[0x1]; 1520 u8 qcam_reg[0x1]; 1521 u8 gid_table_size[0x10]; 1522 1523 u8 out_of_seq_cnt[0x1]; 1524 u8 vport_counters[0x1]; 1525 u8 retransmission_q_counters[0x1]; 1526 u8 debug[0x1]; 1527 u8 modify_rq_counter_set_id[0x1]; 1528 u8 rq_delay_drop[0x1]; 1529 u8 max_qp_cnt[0xa]; 1530 u8 pkey_table_size[0x10]; 1531 1532 u8 vport_group_manager[0x1]; 1533 u8 vhca_group_manager[0x1]; 1534 u8 ib_virt[0x1]; 1535 u8 eth_virt[0x1]; 1536 u8 vnic_env_queue_counters[0x1]; 1537 u8 ets[0x1]; 1538 u8 nic_flow_table[0x1]; 1539 u8 eswitch_manager[0x1]; 1540 u8 device_memory[0x1]; 1541 u8 mcam_reg[0x1]; 1542 u8 pcam_reg[0x1]; 1543 u8 local_ca_ack_delay[0x5]; 1544 u8 port_module_event[0x1]; 1545 u8 enhanced_error_q_counters[0x1]; 1546 u8 ports_check[0x1]; 1547 u8 reserved_at_1b3[0x1]; 1548 u8 disable_link_up[0x1]; 1549 u8 beacon_led[0x1]; 1550 u8 port_type[0x2]; 1551 u8 num_ports[0x8]; 1552 1553 u8 reserved_at_1c0[0x1]; 1554 u8 pps[0x1]; 1555 u8 pps_modify[0x1]; 1556 u8 log_max_msg[0x5]; 1557 u8 reserved_at_1c8[0x4]; 1558 u8 max_tc[0x4]; 1559 u8 temp_warn_event[0x1]; 1560 u8 dcbx[0x1]; 1561 u8 general_notification_event[0x1]; 1562 u8 reserved_at_1d3[0x2]; 1563 u8 fpga[0x1]; 1564 u8 rol_s[0x1]; 1565 u8 rol_g[0x1]; 1566 u8 reserved_at_1d8[0x1]; 1567 u8 wol_s[0x1]; 1568 u8 wol_g[0x1]; 1569 u8 wol_a[0x1]; 1570 u8 wol_b[0x1]; 1571 u8 wol_m[0x1]; 1572 u8 wol_u[0x1]; 1573 u8 wol_p[0x1]; 1574 1575 u8 stat_rate_support[0x10]; 1576 u8 reserved_at_1f0[0x1]; 1577 u8 pci_sync_for_fw_update_event[0x1]; 1578 u8 reserved_at_1f2[0x6]; 1579 u8 init2_lag_tx_port_affinity[0x1]; 1580 u8 reserved_at_1fa[0x3]; 1581 u8 cqe_version[0x4]; 1582 1583 u8 compact_address_vector[0x1]; 1584 u8 striding_rq[0x1]; 1585 u8 reserved_at_202[0x1]; 1586 u8 ipoib_enhanced_offloads[0x1]; 1587 u8 ipoib_basic_offloads[0x1]; 1588 u8 reserved_at_205[0x1]; 1589 u8 repeated_block_disabled[0x1]; 1590 u8 umr_modify_entity_size_disabled[0x1]; 1591 u8 umr_modify_atomic_disabled[0x1]; 1592 u8 umr_indirect_mkey_disabled[0x1]; 1593 u8 umr_fence[0x2]; 1594 u8 dc_req_scat_data_cqe[0x1]; 1595 u8 reserved_at_20d[0x2]; 1596 u8 drain_sigerr[0x1]; 1597 u8 cmdif_checksum[0x2]; 1598 u8 sigerr_cqe[0x1]; 1599 u8 reserved_at_213[0x1]; 1600 u8 wq_signature[0x1]; 1601 u8 sctr_data_cqe[0x1]; 1602 u8 reserved_at_216[0x1]; 1603 u8 sho[0x1]; 1604 u8 tph[0x1]; 1605 u8 rf[0x1]; 1606 u8 dct[0x1]; 1607 u8 qos[0x1]; 1608 u8 eth_net_offloads[0x1]; 1609 u8 roce[0x1]; 1610 u8 atomic[0x1]; 1611 u8 reserved_at_21f[0x1]; 1612 1613 u8 cq_oi[0x1]; 1614 u8 cq_resize[0x1]; 1615 u8 cq_moderation[0x1]; 1616 u8 reserved_at_223[0x3]; 1617 u8 cq_eq_remap[0x1]; 1618 u8 pg[0x1]; 1619 u8 block_lb_mc[0x1]; 1620 u8 reserved_at_229[0x1]; 1621 u8 scqe_break_moderation[0x1]; 1622 u8 cq_period_start_from_cqe[0x1]; 1623 u8 cd[0x1]; 1624 u8 reserved_at_22d[0x1]; 1625 u8 apm[0x1]; 1626 u8 vector_calc[0x1]; 1627 u8 umr_ptr_rlky[0x1]; 1628 u8 imaicl[0x1]; 1629 u8 qp_packet_based[0x1]; 1630 u8 reserved_at_233[0x3]; 1631 u8 qkv[0x1]; 1632 u8 pkv[0x1]; 1633 u8 set_deth_sqpn[0x1]; 1634 u8 reserved_at_239[0x3]; 1635 u8 xrc[0x1]; 1636 u8 ud[0x1]; 1637 u8 uc[0x1]; 1638 u8 rc[0x1]; 1639 1640 u8 uar_4k[0x1]; 1641 u8 reserved_at_241[0x9]; 1642 u8 uar_sz[0x6]; 1643 u8 port_selection_cap[0x1]; 1644 u8 reserved_at_248[0x1]; 1645 u8 umem_uid_0[0x1]; 1646 u8 reserved_at_250[0x5]; 1647 u8 log_pg_sz[0x8]; 1648 1649 u8 bf[0x1]; 1650 u8 driver_version[0x1]; 1651 u8 pad_tx_eth_packet[0x1]; 1652 u8 reserved_at_263[0x3]; 1653 u8 mkey_by_name[0x1]; 1654 u8 reserved_at_267[0x4]; 1655 1656 u8 log_bf_reg_size[0x5]; 1657 1658 u8 reserved_at_270[0x6]; 1659 u8 lag_dct[0x2]; 1660 u8 lag_tx_port_affinity[0x1]; 1661 u8 lag_native_fdb_selection[0x1]; 1662 u8 reserved_at_27a[0x1]; 1663 u8 lag_master[0x1]; 1664 u8 num_lag_ports[0x4]; 1665 1666 u8 reserved_at_280[0x10]; 1667 u8 max_wqe_sz_sq[0x10]; 1668 1669 u8 reserved_at_2a0[0x10]; 1670 u8 max_wqe_sz_rq[0x10]; 1671 1672 u8 max_flow_counter_31_16[0x10]; 1673 u8 max_wqe_sz_sq_dc[0x10]; 1674 1675 u8 reserved_at_2e0[0x7]; 1676 u8 max_qp_mcg[0x19]; 1677 1678 u8 reserved_at_300[0x10]; 1679 u8 flow_counter_bulk_alloc[0x8]; 1680 u8 log_max_mcg[0x8]; 1681 1682 u8 reserved_at_320[0x3]; 1683 u8 log_max_transport_domain[0x5]; 1684 u8 reserved_at_328[0x3]; 1685 u8 log_max_pd[0x5]; 1686 u8 reserved_at_330[0xb]; 1687 u8 log_max_xrcd[0x5]; 1688 1689 u8 nic_receive_steering_discard[0x1]; 1690 u8 receive_discard_vport_down[0x1]; 1691 u8 transmit_discard_vport_down[0x1]; 1692 u8 eq_overrun_count[0x1]; 1693 u8 reserved_at_344[0x1]; 1694 u8 invalid_command_count[0x1]; 1695 u8 quota_exceeded_count[0x1]; 1696 u8 reserved_at_347[0x1]; 1697 u8 log_max_flow_counter_bulk[0x8]; 1698 u8 max_flow_counter_15_0[0x10]; 1699 1700 1701 u8 reserved_at_360[0x3]; 1702 u8 log_max_rq[0x5]; 1703 u8 reserved_at_368[0x3]; 1704 u8 log_max_sq[0x5]; 1705 u8 reserved_at_370[0x3]; 1706 u8 log_max_tir[0x5]; 1707 u8 reserved_at_378[0x3]; 1708 u8 log_max_tis[0x5]; 1709 1710 u8 basic_cyclic_rcv_wqe[0x1]; 1711 u8 reserved_at_381[0x2]; 1712 u8 log_max_rmp[0x5]; 1713 u8 reserved_at_388[0x3]; 1714 u8 log_max_rqt[0x5]; 1715 u8 reserved_at_390[0x3]; 1716 u8 log_max_rqt_size[0x5]; 1717 u8 reserved_at_398[0x3]; 1718 u8 log_max_tis_per_sq[0x5]; 1719 1720 u8 ext_stride_num_range[0x1]; 1721 u8 roce_rw_supported[0x1]; 1722 u8 log_max_current_uc_list_wr_supported[0x1]; 1723 u8 log_max_stride_sz_rq[0x5]; 1724 u8 reserved_at_3a8[0x3]; 1725 u8 log_min_stride_sz_rq[0x5]; 1726 u8 reserved_at_3b0[0x3]; 1727 u8 log_max_stride_sz_sq[0x5]; 1728 u8 reserved_at_3b8[0x3]; 1729 u8 log_min_stride_sz_sq[0x5]; 1730 1731 u8 hairpin[0x1]; 1732 u8 reserved_at_3c1[0x2]; 1733 u8 log_max_hairpin_queues[0x5]; 1734 u8 reserved_at_3c8[0x3]; 1735 u8 log_max_hairpin_wq_data_sz[0x5]; 1736 u8 reserved_at_3d0[0x3]; 1737 u8 log_max_hairpin_num_packets[0x5]; 1738 u8 reserved_at_3d8[0x3]; 1739 u8 log_max_wq_sz[0x5]; 1740 1741 u8 nic_vport_change_event[0x1]; 1742 u8 disable_local_lb_uc[0x1]; 1743 u8 disable_local_lb_mc[0x1]; 1744 u8 log_min_hairpin_wq_data_sz[0x5]; 1745 u8 reserved_at_3e8[0x2]; 1746 u8 vhca_state[0x1]; 1747 u8 log_max_vlan_list[0x5]; 1748 u8 reserved_at_3f0[0x3]; 1749 u8 log_max_current_mc_list[0x5]; 1750 u8 reserved_at_3f8[0x3]; 1751 u8 log_max_current_uc_list[0x5]; 1752 1753 u8 general_obj_types[0x40]; 1754 1755 u8 sq_ts_format[0x2]; 1756 u8 rq_ts_format[0x2]; 1757 u8 steering_format_version[0x4]; 1758 u8 create_qp_start_hint[0x18]; 1759 1760 u8 reserved_at_460[0x3]; 1761 u8 log_max_uctx[0x5]; 1762 u8 reserved_at_468[0x2]; 1763 u8 ipsec_offload[0x1]; 1764 u8 log_max_umem[0x5]; 1765 u8 max_num_eqs[0x10]; 1766 1767 u8 reserved_at_480[0x1]; 1768 u8 tls_tx[0x1]; 1769 u8 tls_rx[0x1]; 1770 u8 log_max_l2_table[0x5]; 1771 u8 reserved_at_488[0x8]; 1772 u8 log_uar_page_sz[0x10]; 1773 1774 u8 reserved_at_4a0[0x20]; 1775 u8 device_frequency_mhz[0x20]; 1776 u8 device_frequency_khz[0x20]; 1777 1778 u8 reserved_at_500[0x20]; 1779 u8 num_of_uars_per_page[0x20]; 1780 1781 u8 flex_parser_protocols[0x20]; 1782 1783 u8 max_geneve_tlv_options[0x8]; 1784 u8 reserved_at_568[0x3]; 1785 u8 max_geneve_tlv_option_data_len[0x5]; 1786 u8 reserved_at_570[0x9]; 1787 u8 adv_virtualization[0x1]; 1788 u8 reserved_at_57a[0x6]; 1789 1790 u8 reserved_at_580[0xb]; 1791 u8 log_max_dci_stream_channels[0x5]; 1792 u8 reserved_at_590[0x3]; 1793 u8 log_max_dci_errored_streams[0x5]; 1794 u8 reserved_at_598[0x8]; 1795 1796 u8 reserved_at_5a0[0x10]; 1797 u8 enhanced_cqe_compression[0x1]; 1798 u8 reserved_at_5b1[0x2]; 1799 u8 log_max_dek[0x5]; 1800 u8 reserved_at_5b8[0x4]; 1801 u8 mini_cqe_resp_stride_index[0x1]; 1802 u8 cqe_128_always[0x1]; 1803 u8 cqe_compression_128[0x1]; 1804 u8 cqe_compression[0x1]; 1805 1806 u8 cqe_compression_timeout[0x10]; 1807 u8 cqe_compression_max_num[0x10]; 1808 1809 u8 reserved_at_5e0[0x8]; 1810 u8 flex_parser_id_gtpu_dw_0[0x4]; 1811 u8 reserved_at_5ec[0x4]; 1812 u8 tag_matching[0x1]; 1813 u8 rndv_offload_rc[0x1]; 1814 u8 rndv_offload_dc[0x1]; 1815 u8 log_tag_matching_list_sz[0x5]; 1816 u8 reserved_at_5f8[0x3]; 1817 u8 log_max_xrq[0x5]; 1818 1819 u8 affiliate_nic_vport_criteria[0x8]; 1820 u8 native_port_num[0x8]; 1821 u8 num_vhca_ports[0x8]; 1822 u8 flex_parser_id_gtpu_teid[0x4]; 1823 u8 reserved_at_61c[0x2]; 1824 u8 sw_owner_id[0x1]; 1825 u8 reserved_at_61f[0x1]; 1826 1827 u8 max_num_of_monitor_counters[0x10]; 1828 u8 num_ppcnt_monitor_counters[0x10]; 1829 1830 u8 max_num_sf[0x10]; 1831 u8 num_q_monitor_counters[0x10]; 1832 1833 u8 reserved_at_660[0x20]; 1834 1835 u8 sf[0x1]; 1836 u8 sf_set_partition[0x1]; 1837 u8 reserved_at_682[0x1]; 1838 u8 log_max_sf[0x5]; 1839 u8 apu[0x1]; 1840 u8 reserved_at_689[0x4]; 1841 u8 migration[0x1]; 1842 u8 reserved_at_68e[0x2]; 1843 u8 log_min_sf_size[0x8]; 1844 u8 max_num_sf_partitions[0x8]; 1845 1846 u8 uctx_cap[0x20]; 1847 1848 u8 reserved_at_6c0[0x4]; 1849 u8 flex_parser_id_geneve_tlv_option_0[0x4]; 1850 u8 flex_parser_id_icmp_dw1[0x4]; 1851 u8 flex_parser_id_icmp_dw0[0x4]; 1852 u8 flex_parser_id_icmpv6_dw1[0x4]; 1853 u8 flex_parser_id_icmpv6_dw0[0x4]; 1854 u8 flex_parser_id_outer_first_mpls_over_gre[0x4]; 1855 u8 flex_parser_id_outer_first_mpls_over_udp_label[0x4]; 1856 1857 u8 max_num_match_definer[0x10]; 1858 u8 sf_base_id[0x10]; 1859 1860 u8 flex_parser_id_gtpu_dw_2[0x4]; 1861 u8 flex_parser_id_gtpu_first_ext_dw_0[0x4]; 1862 u8 num_total_dynamic_vf_msix[0x18]; 1863 u8 reserved_at_720[0x14]; 1864 u8 dynamic_msix_table_size[0xc]; 1865 u8 reserved_at_740[0xc]; 1866 u8 min_dynamic_vf_msix_table_size[0x4]; 1867 u8 reserved_at_750[0x4]; 1868 u8 max_dynamic_vf_msix_table_size[0xc]; 1869 1870 u8 reserved_at_760[0x20]; 1871 u8 vhca_tunnel_commands[0x40]; 1872 u8 match_definer_format_supported[0x40]; 1873 }; 1874 1875 struct mlx5_ifc_cmd_hca_cap_2_bits { 1876 u8 reserved_at_0[0xa0]; 1877 1878 u8 max_reformat_insert_size[0x8]; 1879 u8 max_reformat_insert_offset[0x8]; 1880 u8 max_reformat_remove_size[0x8]; 1881 u8 max_reformat_remove_offset[0x8]; 1882 1883 u8 reserved_at_c0[0xe0]; 1884 1885 u8 reserved_at_1a0[0xb]; 1886 u8 log_min_mkey_entity_size[0x5]; 1887 u8 reserved_at_1b0[0x10]; 1888 1889 u8 reserved_at_1c0[0x60]; 1890 1891 u8 reserved_at_220[0x1]; 1892 u8 sw_vhca_id_valid[0x1]; 1893 u8 sw_vhca_id[0xe]; 1894 u8 reserved_at_230[0x10]; 1895 1896 u8 reserved_at_240[0xb]; 1897 u8 ts_cqe_metadata_size2wqe_counter[0x5]; 1898 u8 reserved_at_250[0x10]; 1899 1900 u8 reserved_at_260[0x5a0]; 1901 }; 1902 1903 enum mlx5_ifc_flow_destination_type { 1904 MLX5_IFC_FLOW_DESTINATION_TYPE_VPORT = 0x0, 1905 MLX5_IFC_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1, 1906 MLX5_IFC_FLOW_DESTINATION_TYPE_TIR = 0x2, 1907 MLX5_IFC_FLOW_DESTINATION_TYPE_FLOW_SAMPLER = 0x6, 1908 MLX5_IFC_FLOW_DESTINATION_TYPE_UPLINK = 0x8, 1909 }; 1910 1911 enum mlx5_flow_table_miss_action { 1912 MLX5_FLOW_TABLE_MISS_ACTION_DEF, 1913 MLX5_FLOW_TABLE_MISS_ACTION_FWD, 1914 MLX5_FLOW_TABLE_MISS_ACTION_SWITCH_DOMAIN, 1915 }; 1916 1917 struct mlx5_ifc_dest_format_struct_bits { 1918 u8 destination_type[0x8]; 1919 u8 destination_id[0x18]; 1920 1921 u8 destination_eswitch_owner_vhca_id_valid[0x1]; 1922 u8 packet_reformat[0x1]; 1923 u8 reserved_at_22[0xe]; 1924 u8 destination_eswitch_owner_vhca_id[0x10]; 1925 }; 1926 1927 struct mlx5_ifc_flow_counter_list_bits { 1928 u8 flow_counter_id[0x20]; 1929 1930 u8 reserved_at_20[0x20]; 1931 }; 1932 1933 struct mlx5_ifc_extended_dest_format_bits { 1934 struct mlx5_ifc_dest_format_struct_bits destination_entry; 1935 1936 u8 packet_reformat_id[0x20]; 1937 1938 u8 reserved_at_60[0x20]; 1939 }; 1940 1941 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits { 1942 struct mlx5_ifc_extended_dest_format_bits extended_dest_format; 1943 struct mlx5_ifc_flow_counter_list_bits flow_counter_list; 1944 }; 1945 1946 struct mlx5_ifc_fte_match_param_bits { 1947 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers; 1948 1949 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters; 1950 1951 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers; 1952 1953 struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2; 1954 1955 struct mlx5_ifc_fte_match_set_misc3_bits misc_parameters_3; 1956 1957 struct mlx5_ifc_fte_match_set_misc4_bits misc_parameters_4; 1958 1959 struct mlx5_ifc_fte_match_set_misc5_bits misc_parameters_5; 1960 1961 u8 reserved_at_e00[0x200]; 1962 }; 1963 1964 enum { 1965 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0, 1966 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1, 1967 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2, 1968 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3, 1969 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4, 1970 }; 1971 1972 struct mlx5_ifc_rx_hash_field_select_bits { 1973 u8 l3_prot_type[0x1]; 1974 u8 l4_prot_type[0x1]; 1975 u8 selected_fields[0x1e]; 1976 }; 1977 1978 enum { 1979 MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0, 1980 MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1, 1981 }; 1982 1983 enum { 1984 MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0, 1985 MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1, 1986 }; 1987 1988 struct mlx5_ifc_wq_bits { 1989 u8 wq_type[0x4]; 1990 u8 wq_signature[0x1]; 1991 u8 end_padding_mode[0x2]; 1992 u8 cd_slave[0x1]; 1993 u8 reserved_at_8[0x18]; 1994 1995 u8 hds_skip_first_sge[0x1]; 1996 u8 log2_hds_buf_size[0x3]; 1997 u8 reserved_at_24[0x7]; 1998 u8 page_offset[0x5]; 1999 u8 lwm[0x10]; 2000 2001 u8 reserved_at_40[0x8]; 2002 u8 pd[0x18]; 2003 2004 u8 reserved_at_60[0x8]; 2005 u8 uar_page[0x18]; 2006 2007 u8 dbr_addr[0x40]; 2008 2009 u8 hw_counter[0x20]; 2010 2011 u8 sw_counter[0x20]; 2012 2013 u8 reserved_at_100[0xc]; 2014 u8 log_wq_stride[0x4]; 2015 u8 reserved_at_110[0x3]; 2016 u8 log_wq_pg_sz[0x5]; 2017 u8 reserved_at_118[0x3]; 2018 u8 log_wq_sz[0x5]; 2019 2020 u8 dbr_umem_valid[0x1]; 2021 u8 wq_umem_valid[0x1]; 2022 u8 reserved_at_122[0x1]; 2023 u8 log_hairpin_num_packets[0x5]; 2024 u8 reserved_at_128[0x3]; 2025 u8 log_hairpin_data_sz[0x5]; 2026 2027 u8 reserved_at_130[0x4]; 2028 u8 log_wqe_num_of_strides[0x4]; 2029 u8 two_byte_shift_en[0x1]; 2030 u8 reserved_at_139[0x4]; 2031 u8 log_wqe_stride_size[0x3]; 2032 2033 u8 reserved_at_140[0x80]; 2034 2035 u8 headers_mkey[0x20]; 2036 2037 u8 shampo_enable[0x1]; 2038 u8 reserved_at_1e1[0x4]; 2039 u8 log_reservation_size[0x3]; 2040 u8 reserved_at_1e8[0x5]; 2041 u8 log_max_num_of_packets_per_reservation[0x3]; 2042 u8 reserved_at_1f0[0x6]; 2043 u8 log_headers_entry_size[0x2]; 2044 u8 reserved_at_1f8[0x4]; 2045 u8 log_headers_buffer_entry_num[0x4]; 2046 2047 u8 reserved_at_200[0x400]; 2048 2049 struct mlx5_ifc_cmd_pas_bits pas[]; 2050 }; 2051 2052 struct mlx5_ifc_rq_num_bits { 2053 u8 reserved_at_0[0x8]; 2054 u8 rq_num[0x18]; 2055 }; 2056 2057 struct mlx5_ifc_mac_address_layout_bits { 2058 u8 reserved_at_0[0x10]; 2059 u8 mac_addr_47_32[0x10]; 2060 2061 u8 mac_addr_31_0[0x20]; 2062 }; 2063 2064 struct mlx5_ifc_vlan_layout_bits { 2065 u8 reserved_at_0[0x14]; 2066 u8 vlan[0x0c]; 2067 2068 u8 reserved_at_20[0x20]; 2069 }; 2070 2071 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits { 2072 u8 reserved_at_0[0xa0]; 2073 2074 u8 min_time_between_cnps[0x20]; 2075 2076 u8 reserved_at_c0[0x12]; 2077 u8 cnp_dscp[0x6]; 2078 u8 reserved_at_d8[0x4]; 2079 u8 cnp_prio_mode[0x1]; 2080 u8 cnp_802p_prio[0x3]; 2081 2082 u8 reserved_at_e0[0x720]; 2083 }; 2084 2085 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits { 2086 u8 reserved_at_0[0x60]; 2087 2088 u8 reserved_at_60[0x4]; 2089 u8 clamp_tgt_rate[0x1]; 2090 u8 reserved_at_65[0x3]; 2091 u8 clamp_tgt_rate_after_time_inc[0x1]; 2092 u8 reserved_at_69[0x17]; 2093 2094 u8 reserved_at_80[0x20]; 2095 2096 u8 rpg_time_reset[0x20]; 2097 2098 u8 rpg_byte_reset[0x20]; 2099 2100 u8 rpg_threshold[0x20]; 2101 2102 u8 rpg_max_rate[0x20]; 2103 2104 u8 rpg_ai_rate[0x20]; 2105 2106 u8 rpg_hai_rate[0x20]; 2107 2108 u8 rpg_gd[0x20]; 2109 2110 u8 rpg_min_dec_fac[0x20]; 2111 2112 u8 rpg_min_rate[0x20]; 2113 2114 u8 reserved_at_1c0[0xe0]; 2115 2116 u8 rate_to_set_on_first_cnp[0x20]; 2117 2118 u8 dce_tcp_g[0x20]; 2119 2120 u8 dce_tcp_rtt[0x20]; 2121 2122 u8 rate_reduce_monitor_period[0x20]; 2123 2124 u8 reserved_at_320[0x20]; 2125 2126 u8 initial_alpha_value[0x20]; 2127 2128 u8 reserved_at_360[0x4a0]; 2129 }; 2130 2131 struct mlx5_ifc_cong_control_802_1qau_rp_bits { 2132 u8 reserved_at_0[0x80]; 2133 2134 u8 rppp_max_rps[0x20]; 2135 2136 u8 rpg_time_reset[0x20]; 2137 2138 u8 rpg_byte_reset[0x20]; 2139 2140 u8 rpg_threshold[0x20]; 2141 2142 u8 rpg_max_rate[0x20]; 2143 2144 u8 rpg_ai_rate[0x20]; 2145 2146 u8 rpg_hai_rate[0x20]; 2147 2148 u8 rpg_gd[0x20]; 2149 2150 u8 rpg_min_dec_fac[0x20]; 2151 2152 u8 rpg_min_rate[0x20]; 2153 2154 u8 reserved_at_1c0[0x640]; 2155 }; 2156 2157 enum { 2158 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1, 2159 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2, 2160 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4, 2161 }; 2162 2163 struct mlx5_ifc_resize_field_select_bits { 2164 u8 resize_field_select[0x20]; 2165 }; 2166 2167 struct mlx5_ifc_resource_dump_bits { 2168 u8 more_dump[0x1]; 2169 u8 inline_dump[0x1]; 2170 u8 reserved_at_2[0xa]; 2171 u8 seq_num[0x4]; 2172 u8 segment_type[0x10]; 2173 2174 u8 reserved_at_20[0x10]; 2175 u8 vhca_id[0x10]; 2176 2177 u8 index1[0x20]; 2178 2179 u8 index2[0x20]; 2180 2181 u8 num_of_obj1[0x10]; 2182 u8 num_of_obj2[0x10]; 2183 2184 u8 reserved_at_a0[0x20]; 2185 2186 u8 device_opaque[0x40]; 2187 2188 u8 mkey[0x20]; 2189 2190 u8 size[0x20]; 2191 2192 u8 address[0x40]; 2193 2194 u8 inline_data[52][0x20]; 2195 }; 2196 2197 struct mlx5_ifc_resource_dump_menu_record_bits { 2198 u8 reserved_at_0[0x4]; 2199 u8 num_of_obj2_supports_active[0x1]; 2200 u8 num_of_obj2_supports_all[0x1]; 2201 u8 must_have_num_of_obj2[0x1]; 2202 u8 support_num_of_obj2[0x1]; 2203 u8 num_of_obj1_supports_active[0x1]; 2204 u8 num_of_obj1_supports_all[0x1]; 2205 u8 must_have_num_of_obj1[0x1]; 2206 u8 support_num_of_obj1[0x1]; 2207 u8 must_have_index2[0x1]; 2208 u8 support_index2[0x1]; 2209 u8 must_have_index1[0x1]; 2210 u8 support_index1[0x1]; 2211 u8 segment_type[0x10]; 2212 2213 u8 segment_name[4][0x20]; 2214 2215 u8 index1_name[4][0x20]; 2216 2217 u8 index2_name[4][0x20]; 2218 }; 2219 2220 struct mlx5_ifc_resource_dump_segment_header_bits { 2221 u8 length_dw[0x10]; 2222 u8 segment_type[0x10]; 2223 }; 2224 2225 struct mlx5_ifc_resource_dump_command_segment_bits { 2226 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2227 2228 u8 segment_called[0x10]; 2229 u8 vhca_id[0x10]; 2230 2231 u8 index1[0x20]; 2232 2233 u8 index2[0x20]; 2234 2235 u8 num_of_obj1[0x10]; 2236 u8 num_of_obj2[0x10]; 2237 }; 2238 2239 struct mlx5_ifc_resource_dump_error_segment_bits { 2240 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2241 2242 u8 reserved_at_20[0x10]; 2243 u8 syndrome_id[0x10]; 2244 2245 u8 reserved_at_40[0x40]; 2246 2247 u8 error[8][0x20]; 2248 }; 2249 2250 struct mlx5_ifc_resource_dump_info_segment_bits { 2251 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2252 2253 u8 reserved_at_20[0x18]; 2254 u8 dump_version[0x8]; 2255 2256 u8 hw_version[0x20]; 2257 2258 u8 fw_version[0x20]; 2259 }; 2260 2261 struct mlx5_ifc_resource_dump_menu_segment_bits { 2262 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2263 2264 u8 reserved_at_20[0x10]; 2265 u8 num_of_records[0x10]; 2266 2267 struct mlx5_ifc_resource_dump_menu_record_bits record[]; 2268 }; 2269 2270 struct mlx5_ifc_resource_dump_resource_segment_bits { 2271 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2272 2273 u8 reserved_at_20[0x20]; 2274 2275 u8 index1[0x20]; 2276 2277 u8 index2[0x20]; 2278 2279 u8 payload[][0x20]; 2280 }; 2281 2282 struct mlx5_ifc_resource_dump_terminate_segment_bits { 2283 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2284 }; 2285 2286 struct mlx5_ifc_menu_resource_dump_response_bits { 2287 struct mlx5_ifc_resource_dump_info_segment_bits info; 2288 struct mlx5_ifc_resource_dump_command_segment_bits cmd; 2289 struct mlx5_ifc_resource_dump_menu_segment_bits menu; 2290 struct mlx5_ifc_resource_dump_terminate_segment_bits terminate; 2291 }; 2292 2293 enum { 2294 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1, 2295 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2, 2296 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4, 2297 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8, 2298 }; 2299 2300 struct mlx5_ifc_modify_field_select_bits { 2301 u8 modify_field_select[0x20]; 2302 }; 2303 2304 struct mlx5_ifc_field_select_r_roce_np_bits { 2305 u8 field_select_r_roce_np[0x20]; 2306 }; 2307 2308 struct mlx5_ifc_field_select_r_roce_rp_bits { 2309 u8 field_select_r_roce_rp[0x20]; 2310 }; 2311 2312 enum { 2313 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4, 2314 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8, 2315 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10, 2316 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20, 2317 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40, 2318 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80, 2319 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100, 2320 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200, 2321 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400, 2322 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800, 2323 }; 2324 2325 struct mlx5_ifc_field_select_802_1qau_rp_bits { 2326 u8 field_select_8021qaurp[0x20]; 2327 }; 2328 2329 struct mlx5_ifc_phys_layer_cntrs_bits { 2330 u8 time_since_last_clear_high[0x20]; 2331 2332 u8 time_since_last_clear_low[0x20]; 2333 2334 u8 symbol_errors_high[0x20]; 2335 2336 u8 symbol_errors_low[0x20]; 2337 2338 u8 sync_headers_errors_high[0x20]; 2339 2340 u8 sync_headers_errors_low[0x20]; 2341 2342 u8 edpl_bip_errors_lane0_high[0x20]; 2343 2344 u8 edpl_bip_errors_lane0_low[0x20]; 2345 2346 u8 edpl_bip_errors_lane1_high[0x20]; 2347 2348 u8 edpl_bip_errors_lane1_low[0x20]; 2349 2350 u8 edpl_bip_errors_lane2_high[0x20]; 2351 2352 u8 edpl_bip_errors_lane2_low[0x20]; 2353 2354 u8 edpl_bip_errors_lane3_high[0x20]; 2355 2356 u8 edpl_bip_errors_lane3_low[0x20]; 2357 2358 u8 fc_fec_corrected_blocks_lane0_high[0x20]; 2359 2360 u8 fc_fec_corrected_blocks_lane0_low[0x20]; 2361 2362 u8 fc_fec_corrected_blocks_lane1_high[0x20]; 2363 2364 u8 fc_fec_corrected_blocks_lane1_low[0x20]; 2365 2366 u8 fc_fec_corrected_blocks_lane2_high[0x20]; 2367 2368 u8 fc_fec_corrected_blocks_lane2_low[0x20]; 2369 2370 u8 fc_fec_corrected_blocks_lane3_high[0x20]; 2371 2372 u8 fc_fec_corrected_blocks_lane3_low[0x20]; 2373 2374 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20]; 2375 2376 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20]; 2377 2378 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20]; 2379 2380 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20]; 2381 2382 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20]; 2383 2384 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20]; 2385 2386 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20]; 2387 2388 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20]; 2389 2390 u8 rs_fec_corrected_blocks_high[0x20]; 2391 2392 u8 rs_fec_corrected_blocks_low[0x20]; 2393 2394 u8 rs_fec_uncorrectable_blocks_high[0x20]; 2395 2396 u8 rs_fec_uncorrectable_blocks_low[0x20]; 2397 2398 u8 rs_fec_no_errors_blocks_high[0x20]; 2399 2400 u8 rs_fec_no_errors_blocks_low[0x20]; 2401 2402 u8 rs_fec_single_error_blocks_high[0x20]; 2403 2404 u8 rs_fec_single_error_blocks_low[0x20]; 2405 2406 u8 rs_fec_corrected_symbols_total_high[0x20]; 2407 2408 u8 rs_fec_corrected_symbols_total_low[0x20]; 2409 2410 u8 rs_fec_corrected_symbols_lane0_high[0x20]; 2411 2412 u8 rs_fec_corrected_symbols_lane0_low[0x20]; 2413 2414 u8 rs_fec_corrected_symbols_lane1_high[0x20]; 2415 2416 u8 rs_fec_corrected_symbols_lane1_low[0x20]; 2417 2418 u8 rs_fec_corrected_symbols_lane2_high[0x20]; 2419 2420 u8 rs_fec_corrected_symbols_lane2_low[0x20]; 2421 2422 u8 rs_fec_corrected_symbols_lane3_high[0x20]; 2423 2424 u8 rs_fec_corrected_symbols_lane3_low[0x20]; 2425 2426 u8 link_down_events[0x20]; 2427 2428 u8 successful_recovery_events[0x20]; 2429 2430 u8 reserved_at_640[0x180]; 2431 }; 2432 2433 struct mlx5_ifc_phys_layer_statistical_cntrs_bits { 2434 u8 time_since_last_clear_high[0x20]; 2435 2436 u8 time_since_last_clear_low[0x20]; 2437 2438 u8 phy_received_bits_high[0x20]; 2439 2440 u8 phy_received_bits_low[0x20]; 2441 2442 u8 phy_symbol_errors_high[0x20]; 2443 2444 u8 phy_symbol_errors_low[0x20]; 2445 2446 u8 phy_corrected_bits_high[0x20]; 2447 2448 u8 phy_corrected_bits_low[0x20]; 2449 2450 u8 phy_corrected_bits_lane0_high[0x20]; 2451 2452 u8 phy_corrected_bits_lane0_low[0x20]; 2453 2454 u8 phy_corrected_bits_lane1_high[0x20]; 2455 2456 u8 phy_corrected_bits_lane1_low[0x20]; 2457 2458 u8 phy_corrected_bits_lane2_high[0x20]; 2459 2460 u8 phy_corrected_bits_lane2_low[0x20]; 2461 2462 u8 phy_corrected_bits_lane3_high[0x20]; 2463 2464 u8 phy_corrected_bits_lane3_low[0x20]; 2465 2466 u8 reserved_at_200[0x5c0]; 2467 }; 2468 2469 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits { 2470 u8 symbol_error_counter[0x10]; 2471 2472 u8 link_error_recovery_counter[0x8]; 2473 2474 u8 link_downed_counter[0x8]; 2475 2476 u8 port_rcv_errors[0x10]; 2477 2478 u8 port_rcv_remote_physical_errors[0x10]; 2479 2480 u8 port_rcv_switch_relay_errors[0x10]; 2481 2482 u8 port_xmit_discards[0x10]; 2483 2484 u8 port_xmit_constraint_errors[0x8]; 2485 2486 u8 port_rcv_constraint_errors[0x8]; 2487 2488 u8 reserved_at_70[0x8]; 2489 2490 u8 link_overrun_errors[0x8]; 2491 2492 u8 reserved_at_80[0x10]; 2493 2494 u8 vl_15_dropped[0x10]; 2495 2496 u8 reserved_at_a0[0x80]; 2497 2498 u8 port_xmit_wait[0x20]; 2499 }; 2500 2501 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits { 2502 u8 transmit_queue_high[0x20]; 2503 2504 u8 transmit_queue_low[0x20]; 2505 2506 u8 no_buffer_discard_uc_high[0x20]; 2507 2508 u8 no_buffer_discard_uc_low[0x20]; 2509 2510 u8 reserved_at_80[0x740]; 2511 }; 2512 2513 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits { 2514 u8 wred_discard_high[0x20]; 2515 2516 u8 wred_discard_low[0x20]; 2517 2518 u8 ecn_marked_tc_high[0x20]; 2519 2520 u8 ecn_marked_tc_low[0x20]; 2521 2522 u8 reserved_at_80[0x740]; 2523 }; 2524 2525 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits { 2526 u8 rx_octets_high[0x20]; 2527 2528 u8 rx_octets_low[0x20]; 2529 2530 u8 reserved_at_40[0xc0]; 2531 2532 u8 rx_frames_high[0x20]; 2533 2534 u8 rx_frames_low[0x20]; 2535 2536 u8 tx_octets_high[0x20]; 2537 2538 u8 tx_octets_low[0x20]; 2539 2540 u8 reserved_at_180[0xc0]; 2541 2542 u8 tx_frames_high[0x20]; 2543 2544 u8 tx_frames_low[0x20]; 2545 2546 u8 rx_pause_high[0x20]; 2547 2548 u8 rx_pause_low[0x20]; 2549 2550 u8 rx_pause_duration_high[0x20]; 2551 2552 u8 rx_pause_duration_low[0x20]; 2553 2554 u8 tx_pause_high[0x20]; 2555 2556 u8 tx_pause_low[0x20]; 2557 2558 u8 tx_pause_duration_high[0x20]; 2559 2560 u8 tx_pause_duration_low[0x20]; 2561 2562 u8 rx_pause_transition_high[0x20]; 2563 2564 u8 rx_pause_transition_low[0x20]; 2565 2566 u8 rx_discards_high[0x20]; 2567 2568 u8 rx_discards_low[0x20]; 2569 2570 u8 device_stall_minor_watermark_cnt_high[0x20]; 2571 2572 u8 device_stall_minor_watermark_cnt_low[0x20]; 2573 2574 u8 device_stall_critical_watermark_cnt_high[0x20]; 2575 2576 u8 device_stall_critical_watermark_cnt_low[0x20]; 2577 2578 u8 reserved_at_480[0x340]; 2579 }; 2580 2581 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits { 2582 u8 port_transmit_wait_high[0x20]; 2583 2584 u8 port_transmit_wait_low[0x20]; 2585 2586 u8 reserved_at_40[0x100]; 2587 2588 u8 rx_buffer_almost_full_high[0x20]; 2589 2590 u8 rx_buffer_almost_full_low[0x20]; 2591 2592 u8 rx_buffer_full_high[0x20]; 2593 2594 u8 rx_buffer_full_low[0x20]; 2595 2596 u8 rx_icrc_encapsulated_high[0x20]; 2597 2598 u8 rx_icrc_encapsulated_low[0x20]; 2599 2600 u8 reserved_at_200[0x5c0]; 2601 }; 2602 2603 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits { 2604 u8 dot3stats_alignment_errors_high[0x20]; 2605 2606 u8 dot3stats_alignment_errors_low[0x20]; 2607 2608 u8 dot3stats_fcs_errors_high[0x20]; 2609 2610 u8 dot3stats_fcs_errors_low[0x20]; 2611 2612 u8 dot3stats_single_collision_frames_high[0x20]; 2613 2614 u8 dot3stats_single_collision_frames_low[0x20]; 2615 2616 u8 dot3stats_multiple_collision_frames_high[0x20]; 2617 2618 u8 dot3stats_multiple_collision_frames_low[0x20]; 2619 2620 u8 dot3stats_sqe_test_errors_high[0x20]; 2621 2622 u8 dot3stats_sqe_test_errors_low[0x20]; 2623 2624 u8 dot3stats_deferred_transmissions_high[0x20]; 2625 2626 u8 dot3stats_deferred_transmissions_low[0x20]; 2627 2628 u8 dot3stats_late_collisions_high[0x20]; 2629 2630 u8 dot3stats_late_collisions_low[0x20]; 2631 2632 u8 dot3stats_excessive_collisions_high[0x20]; 2633 2634 u8 dot3stats_excessive_collisions_low[0x20]; 2635 2636 u8 dot3stats_internal_mac_transmit_errors_high[0x20]; 2637 2638 u8 dot3stats_internal_mac_transmit_errors_low[0x20]; 2639 2640 u8 dot3stats_carrier_sense_errors_high[0x20]; 2641 2642 u8 dot3stats_carrier_sense_errors_low[0x20]; 2643 2644 u8 dot3stats_frame_too_longs_high[0x20]; 2645 2646 u8 dot3stats_frame_too_longs_low[0x20]; 2647 2648 u8 dot3stats_internal_mac_receive_errors_high[0x20]; 2649 2650 u8 dot3stats_internal_mac_receive_errors_low[0x20]; 2651 2652 u8 dot3stats_symbol_errors_high[0x20]; 2653 2654 u8 dot3stats_symbol_errors_low[0x20]; 2655 2656 u8 dot3control_in_unknown_opcodes_high[0x20]; 2657 2658 u8 dot3control_in_unknown_opcodes_low[0x20]; 2659 2660 u8 dot3in_pause_frames_high[0x20]; 2661 2662 u8 dot3in_pause_frames_low[0x20]; 2663 2664 u8 dot3out_pause_frames_high[0x20]; 2665 2666 u8 dot3out_pause_frames_low[0x20]; 2667 2668 u8 reserved_at_400[0x3c0]; 2669 }; 2670 2671 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits { 2672 u8 ether_stats_drop_events_high[0x20]; 2673 2674 u8 ether_stats_drop_events_low[0x20]; 2675 2676 u8 ether_stats_octets_high[0x20]; 2677 2678 u8 ether_stats_octets_low[0x20]; 2679 2680 u8 ether_stats_pkts_high[0x20]; 2681 2682 u8 ether_stats_pkts_low[0x20]; 2683 2684 u8 ether_stats_broadcast_pkts_high[0x20]; 2685 2686 u8 ether_stats_broadcast_pkts_low[0x20]; 2687 2688 u8 ether_stats_multicast_pkts_high[0x20]; 2689 2690 u8 ether_stats_multicast_pkts_low[0x20]; 2691 2692 u8 ether_stats_crc_align_errors_high[0x20]; 2693 2694 u8 ether_stats_crc_align_errors_low[0x20]; 2695 2696 u8 ether_stats_undersize_pkts_high[0x20]; 2697 2698 u8 ether_stats_undersize_pkts_low[0x20]; 2699 2700 u8 ether_stats_oversize_pkts_high[0x20]; 2701 2702 u8 ether_stats_oversize_pkts_low[0x20]; 2703 2704 u8 ether_stats_fragments_high[0x20]; 2705 2706 u8 ether_stats_fragments_low[0x20]; 2707 2708 u8 ether_stats_jabbers_high[0x20]; 2709 2710 u8 ether_stats_jabbers_low[0x20]; 2711 2712 u8 ether_stats_collisions_high[0x20]; 2713 2714 u8 ether_stats_collisions_low[0x20]; 2715 2716 u8 ether_stats_pkts64octets_high[0x20]; 2717 2718 u8 ether_stats_pkts64octets_low[0x20]; 2719 2720 u8 ether_stats_pkts65to127octets_high[0x20]; 2721 2722 u8 ether_stats_pkts65to127octets_low[0x20]; 2723 2724 u8 ether_stats_pkts128to255octets_high[0x20]; 2725 2726 u8 ether_stats_pkts128to255octets_low[0x20]; 2727 2728 u8 ether_stats_pkts256to511octets_high[0x20]; 2729 2730 u8 ether_stats_pkts256to511octets_low[0x20]; 2731 2732 u8 ether_stats_pkts512to1023octets_high[0x20]; 2733 2734 u8 ether_stats_pkts512to1023octets_low[0x20]; 2735 2736 u8 ether_stats_pkts1024to1518octets_high[0x20]; 2737 2738 u8 ether_stats_pkts1024to1518octets_low[0x20]; 2739 2740 u8 ether_stats_pkts1519to2047octets_high[0x20]; 2741 2742 u8 ether_stats_pkts1519to2047octets_low[0x20]; 2743 2744 u8 ether_stats_pkts2048to4095octets_high[0x20]; 2745 2746 u8 ether_stats_pkts2048to4095octets_low[0x20]; 2747 2748 u8 ether_stats_pkts4096to8191octets_high[0x20]; 2749 2750 u8 ether_stats_pkts4096to8191octets_low[0x20]; 2751 2752 u8 ether_stats_pkts8192to10239octets_high[0x20]; 2753 2754 u8 ether_stats_pkts8192to10239octets_low[0x20]; 2755 2756 u8 reserved_at_540[0x280]; 2757 }; 2758 2759 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits { 2760 u8 if_in_octets_high[0x20]; 2761 2762 u8 if_in_octets_low[0x20]; 2763 2764 u8 if_in_ucast_pkts_high[0x20]; 2765 2766 u8 if_in_ucast_pkts_low[0x20]; 2767 2768 u8 if_in_discards_high[0x20]; 2769 2770 u8 if_in_discards_low[0x20]; 2771 2772 u8 if_in_errors_high[0x20]; 2773 2774 u8 if_in_errors_low[0x20]; 2775 2776 u8 if_in_unknown_protos_high[0x20]; 2777 2778 u8 if_in_unknown_protos_low[0x20]; 2779 2780 u8 if_out_octets_high[0x20]; 2781 2782 u8 if_out_octets_low[0x20]; 2783 2784 u8 if_out_ucast_pkts_high[0x20]; 2785 2786 u8 if_out_ucast_pkts_low[0x20]; 2787 2788 u8 if_out_discards_high[0x20]; 2789 2790 u8 if_out_discards_low[0x20]; 2791 2792 u8 if_out_errors_high[0x20]; 2793 2794 u8 if_out_errors_low[0x20]; 2795 2796 u8 if_in_multicast_pkts_high[0x20]; 2797 2798 u8 if_in_multicast_pkts_low[0x20]; 2799 2800 u8 if_in_broadcast_pkts_high[0x20]; 2801 2802 u8 if_in_broadcast_pkts_low[0x20]; 2803 2804 u8 if_out_multicast_pkts_high[0x20]; 2805 2806 u8 if_out_multicast_pkts_low[0x20]; 2807 2808 u8 if_out_broadcast_pkts_high[0x20]; 2809 2810 u8 if_out_broadcast_pkts_low[0x20]; 2811 2812 u8 reserved_at_340[0x480]; 2813 }; 2814 2815 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits { 2816 u8 a_frames_transmitted_ok_high[0x20]; 2817 2818 u8 a_frames_transmitted_ok_low[0x20]; 2819 2820 u8 a_frames_received_ok_high[0x20]; 2821 2822 u8 a_frames_received_ok_low[0x20]; 2823 2824 u8 a_frame_check_sequence_errors_high[0x20]; 2825 2826 u8 a_frame_check_sequence_errors_low[0x20]; 2827 2828 u8 a_alignment_errors_high[0x20]; 2829 2830 u8 a_alignment_errors_low[0x20]; 2831 2832 u8 a_octets_transmitted_ok_high[0x20]; 2833 2834 u8 a_octets_transmitted_ok_low[0x20]; 2835 2836 u8 a_octets_received_ok_high[0x20]; 2837 2838 u8 a_octets_received_ok_low[0x20]; 2839 2840 u8 a_multicast_frames_xmitted_ok_high[0x20]; 2841 2842 u8 a_multicast_frames_xmitted_ok_low[0x20]; 2843 2844 u8 a_broadcast_frames_xmitted_ok_high[0x20]; 2845 2846 u8 a_broadcast_frames_xmitted_ok_low[0x20]; 2847 2848 u8 a_multicast_frames_received_ok_high[0x20]; 2849 2850 u8 a_multicast_frames_received_ok_low[0x20]; 2851 2852 u8 a_broadcast_frames_received_ok_high[0x20]; 2853 2854 u8 a_broadcast_frames_received_ok_low[0x20]; 2855 2856 u8 a_in_range_length_errors_high[0x20]; 2857 2858 u8 a_in_range_length_errors_low[0x20]; 2859 2860 u8 a_out_of_range_length_field_high[0x20]; 2861 2862 u8 a_out_of_range_length_field_low[0x20]; 2863 2864 u8 a_frame_too_long_errors_high[0x20]; 2865 2866 u8 a_frame_too_long_errors_low[0x20]; 2867 2868 u8 a_symbol_error_during_carrier_high[0x20]; 2869 2870 u8 a_symbol_error_during_carrier_low[0x20]; 2871 2872 u8 a_mac_control_frames_transmitted_high[0x20]; 2873 2874 u8 a_mac_control_frames_transmitted_low[0x20]; 2875 2876 u8 a_mac_control_frames_received_high[0x20]; 2877 2878 u8 a_mac_control_frames_received_low[0x20]; 2879 2880 u8 a_unsupported_opcodes_received_high[0x20]; 2881 2882 u8 a_unsupported_opcodes_received_low[0x20]; 2883 2884 u8 a_pause_mac_ctrl_frames_received_high[0x20]; 2885 2886 u8 a_pause_mac_ctrl_frames_received_low[0x20]; 2887 2888 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20]; 2889 2890 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20]; 2891 2892 u8 reserved_at_4c0[0x300]; 2893 }; 2894 2895 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits { 2896 u8 life_time_counter_high[0x20]; 2897 2898 u8 life_time_counter_low[0x20]; 2899 2900 u8 rx_errors[0x20]; 2901 2902 u8 tx_errors[0x20]; 2903 2904 u8 l0_to_recovery_eieos[0x20]; 2905 2906 u8 l0_to_recovery_ts[0x20]; 2907 2908 u8 l0_to_recovery_framing[0x20]; 2909 2910 u8 l0_to_recovery_retrain[0x20]; 2911 2912 u8 crc_error_dllp[0x20]; 2913 2914 u8 crc_error_tlp[0x20]; 2915 2916 u8 tx_overflow_buffer_pkt_high[0x20]; 2917 2918 u8 tx_overflow_buffer_pkt_low[0x20]; 2919 2920 u8 outbound_stalled_reads[0x20]; 2921 2922 u8 outbound_stalled_writes[0x20]; 2923 2924 u8 outbound_stalled_reads_events[0x20]; 2925 2926 u8 outbound_stalled_writes_events[0x20]; 2927 2928 u8 reserved_at_200[0x5c0]; 2929 }; 2930 2931 struct mlx5_ifc_cmd_inter_comp_event_bits { 2932 u8 command_completion_vector[0x20]; 2933 2934 u8 reserved_at_20[0xc0]; 2935 }; 2936 2937 struct mlx5_ifc_stall_vl_event_bits { 2938 u8 reserved_at_0[0x18]; 2939 u8 port_num[0x1]; 2940 u8 reserved_at_19[0x3]; 2941 u8 vl[0x4]; 2942 2943 u8 reserved_at_20[0xa0]; 2944 }; 2945 2946 struct mlx5_ifc_db_bf_congestion_event_bits { 2947 u8 event_subtype[0x8]; 2948 u8 reserved_at_8[0x8]; 2949 u8 congestion_level[0x8]; 2950 u8 reserved_at_18[0x8]; 2951 2952 u8 reserved_at_20[0xa0]; 2953 }; 2954 2955 struct mlx5_ifc_gpio_event_bits { 2956 u8 reserved_at_0[0x60]; 2957 2958 u8 gpio_event_hi[0x20]; 2959 2960 u8 gpio_event_lo[0x20]; 2961 2962 u8 reserved_at_a0[0x40]; 2963 }; 2964 2965 struct mlx5_ifc_port_state_change_event_bits { 2966 u8 reserved_at_0[0x40]; 2967 2968 u8 port_num[0x4]; 2969 u8 reserved_at_44[0x1c]; 2970 2971 u8 reserved_at_60[0x80]; 2972 }; 2973 2974 struct mlx5_ifc_dropped_packet_logged_bits { 2975 u8 reserved_at_0[0xe0]; 2976 }; 2977 2978 struct mlx5_ifc_default_timeout_bits { 2979 u8 to_multiplier[0x3]; 2980 u8 reserved_at_3[0x9]; 2981 u8 to_value[0x14]; 2982 }; 2983 2984 struct mlx5_ifc_dtor_reg_bits { 2985 u8 reserved_at_0[0x20]; 2986 2987 struct mlx5_ifc_default_timeout_bits pcie_toggle_to; 2988 2989 u8 reserved_at_40[0x60]; 2990 2991 struct mlx5_ifc_default_timeout_bits health_poll_to; 2992 2993 struct mlx5_ifc_default_timeout_bits full_crdump_to; 2994 2995 struct mlx5_ifc_default_timeout_bits fw_reset_to; 2996 2997 struct mlx5_ifc_default_timeout_bits flush_on_err_to; 2998 2999 struct mlx5_ifc_default_timeout_bits pci_sync_update_to; 3000 3001 struct mlx5_ifc_default_timeout_bits tear_down_to; 3002 3003 struct mlx5_ifc_default_timeout_bits fsm_reactivate_to; 3004 3005 struct mlx5_ifc_default_timeout_bits reclaim_pages_to; 3006 3007 struct mlx5_ifc_default_timeout_bits reclaim_vfs_pages_to; 3008 3009 u8 reserved_at_1c0[0x40]; 3010 }; 3011 3012 enum { 3013 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1, 3014 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2, 3015 }; 3016 3017 struct mlx5_ifc_cq_error_bits { 3018 u8 reserved_at_0[0x8]; 3019 u8 cqn[0x18]; 3020 3021 u8 reserved_at_20[0x20]; 3022 3023 u8 reserved_at_40[0x18]; 3024 u8 syndrome[0x8]; 3025 3026 u8 reserved_at_60[0x80]; 3027 }; 3028 3029 struct mlx5_ifc_rdma_page_fault_event_bits { 3030 u8 bytes_committed[0x20]; 3031 3032 u8 r_key[0x20]; 3033 3034 u8 reserved_at_40[0x10]; 3035 u8 packet_len[0x10]; 3036 3037 u8 rdma_op_len[0x20]; 3038 3039 u8 rdma_va[0x40]; 3040 3041 u8 reserved_at_c0[0x5]; 3042 u8 rdma[0x1]; 3043 u8 write[0x1]; 3044 u8 requestor[0x1]; 3045 u8 qp_number[0x18]; 3046 }; 3047 3048 struct mlx5_ifc_wqe_associated_page_fault_event_bits { 3049 u8 bytes_committed[0x20]; 3050 3051 u8 reserved_at_20[0x10]; 3052 u8 wqe_index[0x10]; 3053 3054 u8 reserved_at_40[0x10]; 3055 u8 len[0x10]; 3056 3057 u8 reserved_at_60[0x60]; 3058 3059 u8 reserved_at_c0[0x5]; 3060 u8 rdma[0x1]; 3061 u8 write_read[0x1]; 3062 u8 requestor[0x1]; 3063 u8 qpn[0x18]; 3064 }; 3065 3066 struct mlx5_ifc_qp_events_bits { 3067 u8 reserved_at_0[0xa0]; 3068 3069 u8 type[0x8]; 3070 u8 reserved_at_a8[0x18]; 3071 3072 u8 reserved_at_c0[0x8]; 3073 u8 qpn_rqn_sqn[0x18]; 3074 }; 3075 3076 struct mlx5_ifc_dct_events_bits { 3077 u8 reserved_at_0[0xc0]; 3078 3079 u8 reserved_at_c0[0x8]; 3080 u8 dct_number[0x18]; 3081 }; 3082 3083 struct mlx5_ifc_comp_event_bits { 3084 u8 reserved_at_0[0xc0]; 3085 3086 u8 reserved_at_c0[0x8]; 3087 u8 cq_number[0x18]; 3088 }; 3089 3090 enum { 3091 MLX5_QPC_STATE_RST = 0x0, 3092 MLX5_QPC_STATE_INIT = 0x1, 3093 MLX5_QPC_STATE_RTR = 0x2, 3094 MLX5_QPC_STATE_RTS = 0x3, 3095 MLX5_QPC_STATE_SQER = 0x4, 3096 MLX5_QPC_STATE_ERR = 0x6, 3097 MLX5_QPC_STATE_SQD = 0x7, 3098 MLX5_QPC_STATE_SUSPENDED = 0x9, 3099 }; 3100 3101 enum { 3102 MLX5_QPC_ST_RC = 0x0, 3103 MLX5_QPC_ST_UC = 0x1, 3104 MLX5_QPC_ST_UD = 0x2, 3105 MLX5_QPC_ST_XRC = 0x3, 3106 MLX5_QPC_ST_DCI = 0x5, 3107 MLX5_QPC_ST_QP0 = 0x7, 3108 MLX5_QPC_ST_QP1 = 0x8, 3109 MLX5_QPC_ST_RAW_DATAGRAM = 0x9, 3110 MLX5_QPC_ST_REG_UMR = 0xc, 3111 }; 3112 3113 enum { 3114 MLX5_QPC_PM_STATE_ARMED = 0x0, 3115 MLX5_QPC_PM_STATE_REARM = 0x1, 3116 MLX5_QPC_PM_STATE_RESERVED = 0x2, 3117 MLX5_QPC_PM_STATE_MIGRATED = 0x3, 3118 }; 3119 3120 enum { 3121 MLX5_QPC_OFFLOAD_TYPE_RNDV = 0x1, 3122 }; 3123 3124 enum { 3125 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0, 3126 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1, 3127 }; 3128 3129 enum { 3130 MLX5_QPC_MTU_256_BYTES = 0x1, 3131 MLX5_QPC_MTU_512_BYTES = 0x2, 3132 MLX5_QPC_MTU_1K_BYTES = 0x3, 3133 MLX5_QPC_MTU_2K_BYTES = 0x4, 3134 MLX5_QPC_MTU_4K_BYTES = 0x5, 3135 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7, 3136 }; 3137 3138 enum { 3139 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1, 3140 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2, 3141 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3, 3142 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4, 3143 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5, 3144 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6, 3145 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7, 3146 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8, 3147 }; 3148 3149 enum { 3150 MLX5_QPC_CS_REQ_DISABLE = 0x0, 3151 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11, 3152 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22, 3153 }; 3154 3155 enum { 3156 MLX5_QPC_CS_RES_DISABLE = 0x0, 3157 MLX5_QPC_CS_RES_UP_TO_32B = 0x1, 3158 MLX5_QPC_CS_RES_UP_TO_64B = 0x2, 3159 }; 3160 3161 enum { 3162 MLX5_TIMESTAMP_FORMAT_FREE_RUNNING = 0x0, 3163 MLX5_TIMESTAMP_FORMAT_DEFAULT = 0x1, 3164 MLX5_TIMESTAMP_FORMAT_REAL_TIME = 0x2, 3165 }; 3166 3167 struct mlx5_ifc_qpc_bits { 3168 u8 state[0x4]; 3169 u8 lag_tx_port_affinity[0x4]; 3170 u8 st[0x8]; 3171 u8 reserved_at_10[0x2]; 3172 u8 isolate_vl_tc[0x1]; 3173 u8 pm_state[0x2]; 3174 u8 reserved_at_15[0x1]; 3175 u8 req_e2e_credit_mode[0x2]; 3176 u8 offload_type[0x4]; 3177 u8 end_padding_mode[0x2]; 3178 u8 reserved_at_1e[0x2]; 3179 3180 u8 wq_signature[0x1]; 3181 u8 block_lb_mc[0x1]; 3182 u8 atomic_like_write_en[0x1]; 3183 u8 latency_sensitive[0x1]; 3184 u8 reserved_at_24[0x1]; 3185 u8 drain_sigerr[0x1]; 3186 u8 reserved_at_26[0x2]; 3187 u8 pd[0x18]; 3188 3189 u8 mtu[0x3]; 3190 u8 log_msg_max[0x5]; 3191 u8 reserved_at_48[0x1]; 3192 u8 log_rq_size[0x4]; 3193 u8 log_rq_stride[0x3]; 3194 u8 no_sq[0x1]; 3195 u8 log_sq_size[0x4]; 3196 u8 reserved_at_55[0x3]; 3197 u8 ts_format[0x2]; 3198 u8 reserved_at_5a[0x1]; 3199 u8 rlky[0x1]; 3200 u8 ulp_stateless_offload_mode[0x4]; 3201 3202 u8 counter_set_id[0x8]; 3203 u8 uar_page[0x18]; 3204 3205 u8 reserved_at_80[0x8]; 3206 u8 user_index[0x18]; 3207 3208 u8 reserved_at_a0[0x3]; 3209 u8 log_page_size[0x5]; 3210 u8 remote_qpn[0x18]; 3211 3212 struct mlx5_ifc_ads_bits primary_address_path; 3213 3214 struct mlx5_ifc_ads_bits secondary_address_path; 3215 3216 u8 log_ack_req_freq[0x4]; 3217 u8 reserved_at_384[0x4]; 3218 u8 log_sra_max[0x3]; 3219 u8 reserved_at_38b[0x2]; 3220 u8 retry_count[0x3]; 3221 u8 rnr_retry[0x3]; 3222 u8 reserved_at_393[0x1]; 3223 u8 fre[0x1]; 3224 u8 cur_rnr_retry[0x3]; 3225 u8 cur_retry_count[0x3]; 3226 u8 reserved_at_39b[0x5]; 3227 3228 u8 reserved_at_3a0[0x20]; 3229 3230 u8 reserved_at_3c0[0x8]; 3231 u8 next_send_psn[0x18]; 3232 3233 u8 reserved_at_3e0[0x3]; 3234 u8 log_num_dci_stream_channels[0x5]; 3235 u8 cqn_snd[0x18]; 3236 3237 u8 reserved_at_400[0x3]; 3238 u8 log_num_dci_errored_streams[0x5]; 3239 u8 deth_sqpn[0x18]; 3240 3241 u8 reserved_at_420[0x20]; 3242 3243 u8 reserved_at_440[0x8]; 3244 u8 last_acked_psn[0x18]; 3245 3246 u8 reserved_at_460[0x8]; 3247 u8 ssn[0x18]; 3248 3249 u8 reserved_at_480[0x8]; 3250 u8 log_rra_max[0x3]; 3251 u8 reserved_at_48b[0x1]; 3252 u8 atomic_mode[0x4]; 3253 u8 rre[0x1]; 3254 u8 rwe[0x1]; 3255 u8 rae[0x1]; 3256 u8 reserved_at_493[0x1]; 3257 u8 page_offset[0x6]; 3258 u8 reserved_at_49a[0x3]; 3259 u8 cd_slave_receive[0x1]; 3260 u8 cd_slave_send[0x1]; 3261 u8 cd_master[0x1]; 3262 3263 u8 reserved_at_4a0[0x3]; 3264 u8 min_rnr_nak[0x5]; 3265 u8 next_rcv_psn[0x18]; 3266 3267 u8 reserved_at_4c0[0x8]; 3268 u8 xrcd[0x18]; 3269 3270 u8 reserved_at_4e0[0x8]; 3271 u8 cqn_rcv[0x18]; 3272 3273 u8 dbr_addr[0x40]; 3274 3275 u8 q_key[0x20]; 3276 3277 u8 reserved_at_560[0x5]; 3278 u8 rq_type[0x3]; 3279 u8 srqn_rmpn_xrqn[0x18]; 3280 3281 u8 reserved_at_580[0x8]; 3282 u8 rmsn[0x18]; 3283 3284 u8 hw_sq_wqebb_counter[0x10]; 3285 u8 sw_sq_wqebb_counter[0x10]; 3286 3287 u8 hw_rq_counter[0x20]; 3288 3289 u8 sw_rq_counter[0x20]; 3290 3291 u8 reserved_at_600[0x20]; 3292 3293 u8 reserved_at_620[0xf]; 3294 u8 cgs[0x1]; 3295 u8 cs_req[0x8]; 3296 u8 cs_res[0x8]; 3297 3298 u8 dc_access_key[0x40]; 3299 3300 u8 reserved_at_680[0x3]; 3301 u8 dbr_umem_valid[0x1]; 3302 3303 u8 reserved_at_684[0xbc]; 3304 }; 3305 3306 struct mlx5_ifc_roce_addr_layout_bits { 3307 u8 source_l3_address[16][0x8]; 3308 3309 u8 reserved_at_80[0x3]; 3310 u8 vlan_valid[0x1]; 3311 u8 vlan_id[0xc]; 3312 u8 source_mac_47_32[0x10]; 3313 3314 u8 source_mac_31_0[0x20]; 3315 3316 u8 reserved_at_c0[0x14]; 3317 u8 roce_l3_type[0x4]; 3318 u8 roce_version[0x8]; 3319 3320 u8 reserved_at_e0[0x20]; 3321 }; 3322 3323 struct mlx5_ifc_shampo_cap_bits { 3324 u8 reserved_at_0[0x3]; 3325 u8 shampo_log_max_reservation_size[0x5]; 3326 u8 reserved_at_8[0x3]; 3327 u8 shampo_log_min_reservation_size[0x5]; 3328 u8 shampo_min_mss_size[0x10]; 3329 3330 u8 reserved_at_20[0x3]; 3331 u8 shampo_max_log_headers_entry_size[0x5]; 3332 u8 reserved_at_28[0x18]; 3333 3334 u8 reserved_at_40[0x7c0]; 3335 }; 3336 3337 union mlx5_ifc_hca_cap_union_bits { 3338 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap; 3339 struct mlx5_ifc_cmd_hca_cap_2_bits cmd_hca_cap_2; 3340 struct mlx5_ifc_odp_cap_bits odp_cap; 3341 struct mlx5_ifc_atomic_caps_bits atomic_caps; 3342 struct mlx5_ifc_roce_cap_bits roce_cap; 3343 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps; 3344 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap; 3345 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap; 3346 struct mlx5_ifc_e_switch_cap_bits e_switch_cap; 3347 struct mlx5_ifc_port_selection_cap_bits port_selection_cap; 3348 struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap; 3349 struct mlx5_ifc_qos_cap_bits qos_cap; 3350 struct mlx5_ifc_debug_cap_bits debug_cap; 3351 struct mlx5_ifc_fpga_cap_bits fpga_cap; 3352 struct mlx5_ifc_tls_cap_bits tls_cap; 3353 struct mlx5_ifc_device_mem_cap_bits device_mem_cap; 3354 struct mlx5_ifc_virtio_emulation_cap_bits virtio_emulation_cap; 3355 struct mlx5_ifc_shampo_cap_bits shampo_cap; 3356 struct mlx5_ifc_macsec_cap_bits macsec_cap; 3357 u8 reserved_at_0[0x8000]; 3358 }; 3359 3360 enum { 3361 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1, 3362 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2, 3363 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4, 3364 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8, 3365 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT = 0x10, 3366 MLX5_FLOW_CONTEXT_ACTION_DECAP = 0x20, 3367 MLX5_FLOW_CONTEXT_ACTION_MOD_HDR = 0x40, 3368 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP = 0x80, 3369 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100, 3370 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2 = 0x400, 3371 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2 = 0x800, 3372 MLX5_FLOW_CONTEXT_ACTION_CRYPTO_DECRYPT = 0x1000, 3373 MLX5_FLOW_CONTEXT_ACTION_CRYPTO_ENCRYPT = 0x2000, 3374 MLX5_FLOW_CONTEXT_ACTION_EXECUTE_ASO = 0x4000, 3375 }; 3376 3377 enum { 3378 MLX5_FLOW_CONTEXT_FLOW_SOURCE_ANY_VPORT = 0x0, 3379 MLX5_FLOW_CONTEXT_FLOW_SOURCE_UPLINK = 0x1, 3380 MLX5_FLOW_CONTEXT_FLOW_SOURCE_LOCAL_VPORT = 0x2, 3381 }; 3382 3383 enum { 3384 MLX5_FLOW_CONTEXT_ENCRYPT_DECRYPT_TYPE_IPSEC = 0x0, 3385 MLX5_FLOW_CONTEXT_ENCRYPT_DECRYPT_TYPE_MACSEC = 0x1, 3386 }; 3387 3388 struct mlx5_ifc_vlan_bits { 3389 u8 ethtype[0x10]; 3390 u8 prio[0x3]; 3391 u8 cfi[0x1]; 3392 u8 vid[0xc]; 3393 }; 3394 3395 enum { 3396 MLX5_FLOW_METER_COLOR_RED = 0x0, 3397 MLX5_FLOW_METER_COLOR_YELLOW = 0x1, 3398 MLX5_FLOW_METER_COLOR_GREEN = 0x2, 3399 MLX5_FLOW_METER_COLOR_UNDEFINED = 0x3, 3400 }; 3401 3402 enum { 3403 MLX5_EXE_ASO_FLOW_METER = 0x2, 3404 }; 3405 3406 struct mlx5_ifc_exe_aso_ctrl_flow_meter_bits { 3407 u8 return_reg_id[0x4]; 3408 u8 aso_type[0x4]; 3409 u8 reserved_at_8[0x14]; 3410 u8 action[0x1]; 3411 u8 init_color[0x2]; 3412 u8 meter_id[0x1]; 3413 }; 3414 3415 union mlx5_ifc_exe_aso_ctrl { 3416 struct mlx5_ifc_exe_aso_ctrl_flow_meter_bits exe_aso_ctrl_flow_meter; 3417 }; 3418 3419 struct mlx5_ifc_execute_aso_bits { 3420 u8 valid[0x1]; 3421 u8 reserved_at_1[0x7]; 3422 u8 aso_object_id[0x18]; 3423 3424 union mlx5_ifc_exe_aso_ctrl exe_aso_ctrl; 3425 }; 3426 3427 struct mlx5_ifc_flow_context_bits { 3428 struct mlx5_ifc_vlan_bits push_vlan; 3429 3430 u8 group_id[0x20]; 3431 3432 u8 reserved_at_40[0x8]; 3433 u8 flow_tag[0x18]; 3434 3435 u8 reserved_at_60[0x10]; 3436 u8 action[0x10]; 3437 3438 u8 extended_destination[0x1]; 3439 u8 reserved_at_81[0x1]; 3440 u8 flow_source[0x2]; 3441 u8 encrypt_decrypt_type[0x4]; 3442 u8 destination_list_size[0x18]; 3443 3444 u8 reserved_at_a0[0x8]; 3445 u8 flow_counter_list_size[0x18]; 3446 3447 u8 packet_reformat_id[0x20]; 3448 3449 u8 modify_header_id[0x20]; 3450 3451 struct mlx5_ifc_vlan_bits push_vlan_2; 3452 3453 u8 encrypt_decrypt_obj_id[0x20]; 3454 u8 reserved_at_140[0xc0]; 3455 3456 struct mlx5_ifc_fte_match_param_bits match_value; 3457 3458 struct mlx5_ifc_execute_aso_bits execute_aso[4]; 3459 3460 u8 reserved_at_1300[0x500]; 3461 3462 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[]; 3463 }; 3464 3465 enum { 3466 MLX5_XRC_SRQC_STATE_GOOD = 0x0, 3467 MLX5_XRC_SRQC_STATE_ERROR = 0x1, 3468 }; 3469 3470 struct mlx5_ifc_xrc_srqc_bits { 3471 u8 state[0x4]; 3472 u8 log_xrc_srq_size[0x4]; 3473 u8 reserved_at_8[0x18]; 3474 3475 u8 wq_signature[0x1]; 3476 u8 cont_srq[0x1]; 3477 u8 reserved_at_22[0x1]; 3478 u8 rlky[0x1]; 3479 u8 basic_cyclic_rcv_wqe[0x1]; 3480 u8 log_rq_stride[0x3]; 3481 u8 xrcd[0x18]; 3482 3483 u8 page_offset[0x6]; 3484 u8 reserved_at_46[0x1]; 3485 u8 dbr_umem_valid[0x1]; 3486 u8 cqn[0x18]; 3487 3488 u8 reserved_at_60[0x20]; 3489 3490 u8 user_index_equal_xrc_srqn[0x1]; 3491 u8 reserved_at_81[0x1]; 3492 u8 log_page_size[0x6]; 3493 u8 user_index[0x18]; 3494 3495 u8 reserved_at_a0[0x20]; 3496 3497 u8 reserved_at_c0[0x8]; 3498 u8 pd[0x18]; 3499 3500 u8 lwm[0x10]; 3501 u8 wqe_cnt[0x10]; 3502 3503 u8 reserved_at_100[0x40]; 3504 3505 u8 db_record_addr_h[0x20]; 3506 3507 u8 db_record_addr_l[0x1e]; 3508 u8 reserved_at_17e[0x2]; 3509 3510 u8 reserved_at_180[0x80]; 3511 }; 3512 3513 struct mlx5_ifc_vnic_diagnostic_statistics_bits { 3514 u8 counter_error_queues[0x20]; 3515 3516 u8 total_error_queues[0x20]; 3517 3518 u8 send_queue_priority_update_flow[0x20]; 3519 3520 u8 reserved_at_60[0x20]; 3521 3522 u8 nic_receive_steering_discard[0x40]; 3523 3524 u8 receive_discard_vport_down[0x40]; 3525 3526 u8 transmit_discard_vport_down[0x40]; 3527 3528 u8 async_eq_overrun[0x20]; 3529 3530 u8 comp_eq_overrun[0x20]; 3531 3532 u8 reserved_at_180[0x20]; 3533 3534 u8 invalid_command[0x20]; 3535 3536 u8 quota_exceeded_command[0x20]; 3537 3538 u8 internal_rq_out_of_buffer[0x20]; 3539 3540 u8 cq_overrun[0x20]; 3541 3542 u8 eth_wqe_too_small[0x20]; 3543 3544 u8 reserved_at_220[0xdc0]; 3545 }; 3546 3547 struct mlx5_ifc_traffic_counter_bits { 3548 u8 packets[0x40]; 3549 3550 u8 octets[0x40]; 3551 }; 3552 3553 struct mlx5_ifc_tisc_bits { 3554 u8 strict_lag_tx_port_affinity[0x1]; 3555 u8 tls_en[0x1]; 3556 u8 reserved_at_2[0x2]; 3557 u8 lag_tx_port_affinity[0x04]; 3558 3559 u8 reserved_at_8[0x4]; 3560 u8 prio[0x4]; 3561 u8 reserved_at_10[0x10]; 3562 3563 u8 reserved_at_20[0x100]; 3564 3565 u8 reserved_at_120[0x8]; 3566 u8 transport_domain[0x18]; 3567 3568 u8 reserved_at_140[0x8]; 3569 u8 underlay_qpn[0x18]; 3570 3571 u8 reserved_at_160[0x8]; 3572 u8 pd[0x18]; 3573 3574 u8 reserved_at_180[0x380]; 3575 }; 3576 3577 enum { 3578 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0, 3579 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1, 3580 }; 3581 3582 enum { 3583 MLX5_TIRC_PACKET_MERGE_MASK_IPV4_LRO = BIT(0), 3584 MLX5_TIRC_PACKET_MERGE_MASK_IPV6_LRO = BIT(1), 3585 }; 3586 3587 enum { 3588 MLX5_RX_HASH_FN_NONE = 0x0, 3589 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1, 3590 MLX5_RX_HASH_FN_TOEPLITZ = 0x2, 3591 }; 3592 3593 enum { 3594 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST = 0x1, 3595 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST = 0x2, 3596 }; 3597 3598 struct mlx5_ifc_tirc_bits { 3599 u8 reserved_at_0[0x20]; 3600 3601 u8 disp_type[0x4]; 3602 u8 tls_en[0x1]; 3603 u8 reserved_at_25[0x1b]; 3604 3605 u8 reserved_at_40[0x40]; 3606 3607 u8 reserved_at_80[0x4]; 3608 u8 lro_timeout_period_usecs[0x10]; 3609 u8 packet_merge_mask[0x4]; 3610 u8 lro_max_ip_payload_size[0x8]; 3611 3612 u8 reserved_at_a0[0x40]; 3613 3614 u8 reserved_at_e0[0x8]; 3615 u8 inline_rqn[0x18]; 3616 3617 u8 rx_hash_symmetric[0x1]; 3618 u8 reserved_at_101[0x1]; 3619 u8 tunneled_offload_en[0x1]; 3620 u8 reserved_at_103[0x5]; 3621 u8 indirect_table[0x18]; 3622 3623 u8 rx_hash_fn[0x4]; 3624 u8 reserved_at_124[0x2]; 3625 u8 self_lb_block[0x2]; 3626 u8 transport_domain[0x18]; 3627 3628 u8 rx_hash_toeplitz_key[10][0x20]; 3629 3630 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer; 3631 3632 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner; 3633 3634 u8 reserved_at_2c0[0x4c0]; 3635 }; 3636 3637 enum { 3638 MLX5_SRQC_STATE_GOOD = 0x0, 3639 MLX5_SRQC_STATE_ERROR = 0x1, 3640 }; 3641 3642 struct mlx5_ifc_srqc_bits { 3643 u8 state[0x4]; 3644 u8 log_srq_size[0x4]; 3645 u8 reserved_at_8[0x18]; 3646 3647 u8 wq_signature[0x1]; 3648 u8 cont_srq[0x1]; 3649 u8 reserved_at_22[0x1]; 3650 u8 rlky[0x1]; 3651 u8 reserved_at_24[0x1]; 3652 u8 log_rq_stride[0x3]; 3653 u8 xrcd[0x18]; 3654 3655 u8 page_offset[0x6]; 3656 u8 reserved_at_46[0x2]; 3657 u8 cqn[0x18]; 3658 3659 u8 reserved_at_60[0x20]; 3660 3661 u8 reserved_at_80[0x2]; 3662 u8 log_page_size[0x6]; 3663 u8 reserved_at_88[0x18]; 3664 3665 u8 reserved_at_a0[0x20]; 3666 3667 u8 reserved_at_c0[0x8]; 3668 u8 pd[0x18]; 3669 3670 u8 lwm[0x10]; 3671 u8 wqe_cnt[0x10]; 3672 3673 u8 reserved_at_100[0x40]; 3674 3675 u8 dbr_addr[0x40]; 3676 3677 u8 reserved_at_180[0x80]; 3678 }; 3679 3680 enum { 3681 MLX5_SQC_STATE_RST = 0x0, 3682 MLX5_SQC_STATE_RDY = 0x1, 3683 MLX5_SQC_STATE_ERR = 0x3, 3684 }; 3685 3686 struct mlx5_ifc_sqc_bits { 3687 u8 rlky[0x1]; 3688 u8 cd_master[0x1]; 3689 u8 fre[0x1]; 3690 u8 flush_in_error_en[0x1]; 3691 u8 allow_multi_pkt_send_wqe[0x1]; 3692 u8 min_wqe_inline_mode[0x3]; 3693 u8 state[0x4]; 3694 u8 reg_umr[0x1]; 3695 u8 allow_swp[0x1]; 3696 u8 hairpin[0x1]; 3697 u8 reserved_at_f[0xb]; 3698 u8 ts_format[0x2]; 3699 u8 reserved_at_1c[0x4]; 3700 3701 u8 reserved_at_20[0x8]; 3702 u8 user_index[0x18]; 3703 3704 u8 reserved_at_40[0x8]; 3705 u8 cqn[0x18]; 3706 3707 u8 reserved_at_60[0x8]; 3708 u8 hairpin_peer_rq[0x18]; 3709 3710 u8 reserved_at_80[0x10]; 3711 u8 hairpin_peer_vhca[0x10]; 3712 3713 u8 reserved_at_a0[0x20]; 3714 3715 u8 reserved_at_c0[0x8]; 3716 u8 ts_cqe_to_dest_cqn[0x18]; 3717 3718 u8 reserved_at_e0[0x10]; 3719 u8 packet_pacing_rate_limit_index[0x10]; 3720 u8 tis_lst_sz[0x10]; 3721 u8 qos_queue_group_id[0x10]; 3722 3723 u8 reserved_at_120[0x40]; 3724 3725 u8 reserved_at_160[0x8]; 3726 u8 tis_num_0[0x18]; 3727 3728 struct mlx5_ifc_wq_bits wq; 3729 }; 3730 3731 enum { 3732 SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0, 3733 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1, 3734 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2, 3735 SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3, 3736 SCHEDULING_CONTEXT_ELEMENT_TYPE_QUEUE_GROUP = 0x4, 3737 }; 3738 3739 enum { 3740 ELEMENT_TYPE_CAP_MASK_TASR = 1 << 0, 3741 ELEMENT_TYPE_CAP_MASK_VPORT = 1 << 1, 3742 ELEMENT_TYPE_CAP_MASK_VPORT_TC = 1 << 2, 3743 ELEMENT_TYPE_CAP_MASK_PARA_VPORT_TC = 1 << 3, 3744 }; 3745 3746 struct mlx5_ifc_scheduling_context_bits { 3747 u8 element_type[0x8]; 3748 u8 reserved_at_8[0x18]; 3749 3750 u8 element_attributes[0x20]; 3751 3752 u8 parent_element_id[0x20]; 3753 3754 u8 reserved_at_60[0x40]; 3755 3756 u8 bw_share[0x20]; 3757 3758 u8 max_average_bw[0x20]; 3759 3760 u8 reserved_at_e0[0x120]; 3761 }; 3762 3763 struct mlx5_ifc_rqtc_bits { 3764 u8 reserved_at_0[0xa0]; 3765 3766 u8 reserved_at_a0[0x5]; 3767 u8 list_q_type[0x3]; 3768 u8 reserved_at_a8[0x8]; 3769 u8 rqt_max_size[0x10]; 3770 3771 u8 rq_vhca_id_format[0x1]; 3772 u8 reserved_at_c1[0xf]; 3773 u8 rqt_actual_size[0x10]; 3774 3775 u8 reserved_at_e0[0x6a0]; 3776 3777 struct mlx5_ifc_rq_num_bits rq_num[]; 3778 }; 3779 3780 enum { 3781 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0, 3782 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1, 3783 }; 3784 3785 enum { 3786 MLX5_RQC_STATE_RST = 0x0, 3787 MLX5_RQC_STATE_RDY = 0x1, 3788 MLX5_RQC_STATE_ERR = 0x3, 3789 }; 3790 3791 enum { 3792 MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_BYTE = 0x0, 3793 MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_STRIDE = 0x1, 3794 MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_PAGE = 0x2, 3795 }; 3796 3797 enum { 3798 MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_NO_MATCH = 0x0, 3799 MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_EXTENDED = 0x1, 3800 MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_FIVE_TUPLE = 0x2, 3801 }; 3802 3803 struct mlx5_ifc_rqc_bits { 3804 u8 rlky[0x1]; 3805 u8 delay_drop_en[0x1]; 3806 u8 scatter_fcs[0x1]; 3807 u8 vsd[0x1]; 3808 u8 mem_rq_type[0x4]; 3809 u8 state[0x4]; 3810 u8 reserved_at_c[0x1]; 3811 u8 flush_in_error_en[0x1]; 3812 u8 hairpin[0x1]; 3813 u8 reserved_at_f[0xb]; 3814 u8 ts_format[0x2]; 3815 u8 reserved_at_1c[0x4]; 3816 3817 u8 reserved_at_20[0x8]; 3818 u8 user_index[0x18]; 3819 3820 u8 reserved_at_40[0x8]; 3821 u8 cqn[0x18]; 3822 3823 u8 counter_set_id[0x8]; 3824 u8 reserved_at_68[0x18]; 3825 3826 u8 reserved_at_80[0x8]; 3827 u8 rmpn[0x18]; 3828 3829 u8 reserved_at_a0[0x8]; 3830 u8 hairpin_peer_sq[0x18]; 3831 3832 u8 reserved_at_c0[0x10]; 3833 u8 hairpin_peer_vhca[0x10]; 3834 3835 u8 reserved_at_e0[0x46]; 3836 u8 shampo_no_match_alignment_granularity[0x2]; 3837 u8 reserved_at_128[0x6]; 3838 u8 shampo_match_criteria_type[0x2]; 3839 u8 reservation_timeout[0x10]; 3840 3841 u8 reserved_at_140[0x40]; 3842 3843 struct mlx5_ifc_wq_bits wq; 3844 }; 3845 3846 enum { 3847 MLX5_RMPC_STATE_RDY = 0x1, 3848 MLX5_RMPC_STATE_ERR = 0x3, 3849 }; 3850 3851 struct mlx5_ifc_rmpc_bits { 3852 u8 reserved_at_0[0x8]; 3853 u8 state[0x4]; 3854 u8 reserved_at_c[0x14]; 3855 3856 u8 basic_cyclic_rcv_wqe[0x1]; 3857 u8 reserved_at_21[0x1f]; 3858 3859 u8 reserved_at_40[0x140]; 3860 3861 struct mlx5_ifc_wq_bits wq; 3862 }; 3863 3864 enum { 3865 VHCA_ID_TYPE_HW = 0, 3866 VHCA_ID_TYPE_SW = 1, 3867 }; 3868 3869 struct mlx5_ifc_nic_vport_context_bits { 3870 u8 reserved_at_0[0x5]; 3871 u8 min_wqe_inline_mode[0x3]; 3872 u8 reserved_at_8[0x15]; 3873 u8 disable_mc_local_lb[0x1]; 3874 u8 disable_uc_local_lb[0x1]; 3875 u8 roce_en[0x1]; 3876 3877 u8 arm_change_event[0x1]; 3878 u8 reserved_at_21[0x1a]; 3879 u8 event_on_mtu[0x1]; 3880 u8 event_on_promisc_change[0x1]; 3881 u8 event_on_vlan_change[0x1]; 3882 u8 event_on_mc_address_change[0x1]; 3883 u8 event_on_uc_address_change[0x1]; 3884 3885 u8 vhca_id_type[0x1]; 3886 u8 reserved_at_41[0xb]; 3887 u8 affiliation_criteria[0x4]; 3888 u8 affiliated_vhca_id[0x10]; 3889 3890 u8 reserved_at_60[0xd0]; 3891 3892 u8 mtu[0x10]; 3893 3894 u8 system_image_guid[0x40]; 3895 u8 port_guid[0x40]; 3896 u8 node_guid[0x40]; 3897 3898 u8 reserved_at_200[0x140]; 3899 u8 qkey_violation_counter[0x10]; 3900 u8 reserved_at_350[0x430]; 3901 3902 u8 promisc_uc[0x1]; 3903 u8 promisc_mc[0x1]; 3904 u8 promisc_all[0x1]; 3905 u8 reserved_at_783[0x2]; 3906 u8 allowed_list_type[0x3]; 3907 u8 reserved_at_788[0xc]; 3908 u8 allowed_list_size[0xc]; 3909 3910 struct mlx5_ifc_mac_address_layout_bits permanent_address; 3911 3912 u8 reserved_at_7e0[0x20]; 3913 3914 u8 current_uc_mac_address[][0x40]; 3915 }; 3916 3917 enum { 3918 MLX5_MKC_ACCESS_MODE_PA = 0x0, 3919 MLX5_MKC_ACCESS_MODE_MTT = 0x1, 3920 MLX5_MKC_ACCESS_MODE_KLMS = 0x2, 3921 MLX5_MKC_ACCESS_MODE_KSM = 0x3, 3922 MLX5_MKC_ACCESS_MODE_SW_ICM = 0x4, 3923 MLX5_MKC_ACCESS_MODE_MEMIC = 0x5, 3924 }; 3925 3926 struct mlx5_ifc_mkc_bits { 3927 u8 reserved_at_0[0x1]; 3928 u8 free[0x1]; 3929 u8 reserved_at_2[0x1]; 3930 u8 access_mode_4_2[0x3]; 3931 u8 reserved_at_6[0x7]; 3932 u8 relaxed_ordering_write[0x1]; 3933 u8 reserved_at_e[0x1]; 3934 u8 small_fence_on_rdma_read_response[0x1]; 3935 u8 umr_en[0x1]; 3936 u8 a[0x1]; 3937 u8 rw[0x1]; 3938 u8 rr[0x1]; 3939 u8 lw[0x1]; 3940 u8 lr[0x1]; 3941 u8 access_mode_1_0[0x2]; 3942 u8 reserved_at_18[0x8]; 3943 3944 u8 qpn[0x18]; 3945 u8 mkey_7_0[0x8]; 3946 3947 u8 reserved_at_40[0x20]; 3948 3949 u8 length64[0x1]; 3950 u8 bsf_en[0x1]; 3951 u8 sync_umr[0x1]; 3952 u8 reserved_at_63[0x2]; 3953 u8 expected_sigerr_count[0x1]; 3954 u8 reserved_at_66[0x1]; 3955 u8 en_rinval[0x1]; 3956 u8 pd[0x18]; 3957 3958 u8 start_addr[0x40]; 3959 3960 u8 len[0x40]; 3961 3962 u8 bsf_octword_size[0x20]; 3963 3964 u8 reserved_at_120[0x80]; 3965 3966 u8 translations_octword_size[0x20]; 3967 3968 u8 reserved_at_1c0[0x19]; 3969 u8 relaxed_ordering_read[0x1]; 3970 u8 reserved_at_1d9[0x1]; 3971 u8 log_page_size[0x5]; 3972 3973 u8 reserved_at_1e0[0x20]; 3974 }; 3975 3976 struct mlx5_ifc_pkey_bits { 3977 u8 reserved_at_0[0x10]; 3978 u8 pkey[0x10]; 3979 }; 3980 3981 struct mlx5_ifc_array128_auto_bits { 3982 u8 array128_auto[16][0x8]; 3983 }; 3984 3985 struct mlx5_ifc_hca_vport_context_bits { 3986 u8 field_select[0x20]; 3987 3988 u8 reserved_at_20[0xe0]; 3989 3990 u8 sm_virt_aware[0x1]; 3991 u8 has_smi[0x1]; 3992 u8 has_raw[0x1]; 3993 u8 grh_required[0x1]; 3994 u8 reserved_at_104[0xc]; 3995 u8 port_physical_state[0x4]; 3996 u8 vport_state_policy[0x4]; 3997 u8 port_state[0x4]; 3998 u8 vport_state[0x4]; 3999 4000 u8 reserved_at_120[0x20]; 4001 4002 u8 system_image_guid[0x40]; 4003 4004 u8 port_guid[0x40]; 4005 4006 u8 node_guid[0x40]; 4007 4008 u8 cap_mask1[0x20]; 4009 4010 u8 cap_mask1_field_select[0x20]; 4011 4012 u8 cap_mask2[0x20]; 4013 4014 u8 cap_mask2_field_select[0x20]; 4015 4016 u8 reserved_at_280[0x80]; 4017 4018 u8 lid[0x10]; 4019 u8 reserved_at_310[0x4]; 4020 u8 init_type_reply[0x4]; 4021 u8 lmc[0x3]; 4022 u8 subnet_timeout[0x5]; 4023 4024 u8 sm_lid[0x10]; 4025 u8 sm_sl[0x4]; 4026 u8 reserved_at_334[0xc]; 4027 4028 u8 qkey_violation_counter[0x10]; 4029 u8 pkey_violation_counter[0x10]; 4030 4031 u8 reserved_at_360[0xca0]; 4032 }; 4033 4034 struct mlx5_ifc_esw_vport_context_bits { 4035 u8 fdb_to_vport_reg_c[0x1]; 4036 u8 reserved_at_1[0x2]; 4037 u8 vport_svlan_strip[0x1]; 4038 u8 vport_cvlan_strip[0x1]; 4039 u8 vport_svlan_insert[0x1]; 4040 u8 vport_cvlan_insert[0x2]; 4041 u8 fdb_to_vport_reg_c_id[0x8]; 4042 u8 reserved_at_10[0x10]; 4043 4044 u8 reserved_at_20[0x20]; 4045 4046 u8 svlan_cfi[0x1]; 4047 u8 svlan_pcp[0x3]; 4048 u8 svlan_id[0xc]; 4049 u8 cvlan_cfi[0x1]; 4050 u8 cvlan_pcp[0x3]; 4051 u8 cvlan_id[0xc]; 4052 4053 u8 reserved_at_60[0x720]; 4054 4055 u8 sw_steering_vport_icm_address_rx[0x40]; 4056 4057 u8 sw_steering_vport_icm_address_tx[0x40]; 4058 }; 4059 4060 enum { 4061 MLX5_EQC_STATUS_OK = 0x0, 4062 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa, 4063 }; 4064 4065 enum { 4066 MLX5_EQC_ST_ARMED = 0x9, 4067 MLX5_EQC_ST_FIRED = 0xa, 4068 }; 4069 4070 struct mlx5_ifc_eqc_bits { 4071 u8 status[0x4]; 4072 u8 reserved_at_4[0x9]; 4073 u8 ec[0x1]; 4074 u8 oi[0x1]; 4075 u8 reserved_at_f[0x5]; 4076 u8 st[0x4]; 4077 u8 reserved_at_18[0x8]; 4078 4079 u8 reserved_at_20[0x20]; 4080 4081 u8 reserved_at_40[0x14]; 4082 u8 page_offset[0x6]; 4083 u8 reserved_at_5a[0x6]; 4084 4085 u8 reserved_at_60[0x3]; 4086 u8 log_eq_size[0x5]; 4087 u8 uar_page[0x18]; 4088 4089 u8 reserved_at_80[0x20]; 4090 4091 u8 reserved_at_a0[0x14]; 4092 u8 intr[0xc]; 4093 4094 u8 reserved_at_c0[0x3]; 4095 u8 log_page_size[0x5]; 4096 u8 reserved_at_c8[0x18]; 4097 4098 u8 reserved_at_e0[0x60]; 4099 4100 u8 reserved_at_140[0x8]; 4101 u8 consumer_counter[0x18]; 4102 4103 u8 reserved_at_160[0x8]; 4104 u8 producer_counter[0x18]; 4105 4106 u8 reserved_at_180[0x80]; 4107 }; 4108 4109 enum { 4110 MLX5_DCTC_STATE_ACTIVE = 0x0, 4111 MLX5_DCTC_STATE_DRAINING = 0x1, 4112 MLX5_DCTC_STATE_DRAINED = 0x2, 4113 }; 4114 4115 enum { 4116 MLX5_DCTC_CS_RES_DISABLE = 0x0, 4117 MLX5_DCTC_CS_RES_NA = 0x1, 4118 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2, 4119 }; 4120 4121 enum { 4122 MLX5_DCTC_MTU_256_BYTES = 0x1, 4123 MLX5_DCTC_MTU_512_BYTES = 0x2, 4124 MLX5_DCTC_MTU_1K_BYTES = 0x3, 4125 MLX5_DCTC_MTU_2K_BYTES = 0x4, 4126 MLX5_DCTC_MTU_4K_BYTES = 0x5, 4127 }; 4128 4129 struct mlx5_ifc_dctc_bits { 4130 u8 reserved_at_0[0x4]; 4131 u8 state[0x4]; 4132 u8 reserved_at_8[0x18]; 4133 4134 u8 reserved_at_20[0x8]; 4135 u8 user_index[0x18]; 4136 4137 u8 reserved_at_40[0x8]; 4138 u8 cqn[0x18]; 4139 4140 u8 counter_set_id[0x8]; 4141 u8 atomic_mode[0x4]; 4142 u8 rre[0x1]; 4143 u8 rwe[0x1]; 4144 u8 rae[0x1]; 4145 u8 atomic_like_write_en[0x1]; 4146 u8 latency_sensitive[0x1]; 4147 u8 rlky[0x1]; 4148 u8 free_ar[0x1]; 4149 u8 reserved_at_73[0xd]; 4150 4151 u8 reserved_at_80[0x8]; 4152 u8 cs_res[0x8]; 4153 u8 reserved_at_90[0x3]; 4154 u8 min_rnr_nak[0x5]; 4155 u8 reserved_at_98[0x8]; 4156 4157 u8 reserved_at_a0[0x8]; 4158 u8 srqn_xrqn[0x18]; 4159 4160 u8 reserved_at_c0[0x8]; 4161 u8 pd[0x18]; 4162 4163 u8 tclass[0x8]; 4164 u8 reserved_at_e8[0x4]; 4165 u8 flow_label[0x14]; 4166 4167 u8 dc_access_key[0x40]; 4168 4169 u8 reserved_at_140[0x5]; 4170 u8 mtu[0x3]; 4171 u8 port[0x8]; 4172 u8 pkey_index[0x10]; 4173 4174 u8 reserved_at_160[0x8]; 4175 u8 my_addr_index[0x8]; 4176 u8 reserved_at_170[0x8]; 4177 u8 hop_limit[0x8]; 4178 4179 u8 dc_access_key_violation_count[0x20]; 4180 4181 u8 reserved_at_1a0[0x14]; 4182 u8 dei_cfi[0x1]; 4183 u8 eth_prio[0x3]; 4184 u8 ecn[0x2]; 4185 u8 dscp[0x6]; 4186 4187 u8 reserved_at_1c0[0x20]; 4188 u8 ece[0x20]; 4189 }; 4190 4191 enum { 4192 MLX5_CQC_STATUS_OK = 0x0, 4193 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9, 4194 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa, 4195 }; 4196 4197 enum { 4198 MLX5_CQC_CQE_SZ_64_BYTES = 0x0, 4199 MLX5_CQC_CQE_SZ_128_BYTES = 0x1, 4200 }; 4201 4202 enum { 4203 MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED = 0x6, 4204 MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED = 0x9, 4205 MLX5_CQC_ST_FIRED = 0xa, 4206 }; 4207 4208 enum { 4209 MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0, 4210 MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1, 4211 MLX5_CQ_PERIOD_NUM_MODES 4212 }; 4213 4214 struct mlx5_ifc_cqc_bits { 4215 u8 status[0x4]; 4216 u8 reserved_at_4[0x2]; 4217 u8 dbr_umem_valid[0x1]; 4218 u8 apu_cq[0x1]; 4219 u8 cqe_sz[0x3]; 4220 u8 cc[0x1]; 4221 u8 reserved_at_c[0x1]; 4222 u8 scqe_break_moderation_en[0x1]; 4223 u8 oi[0x1]; 4224 u8 cq_period_mode[0x2]; 4225 u8 cqe_comp_en[0x1]; 4226 u8 mini_cqe_res_format[0x2]; 4227 u8 st[0x4]; 4228 u8 reserved_at_18[0x6]; 4229 u8 cqe_compression_layout[0x2]; 4230 4231 u8 reserved_at_20[0x20]; 4232 4233 u8 reserved_at_40[0x14]; 4234 u8 page_offset[0x6]; 4235 u8 reserved_at_5a[0x6]; 4236 4237 u8 reserved_at_60[0x3]; 4238 u8 log_cq_size[0x5]; 4239 u8 uar_page[0x18]; 4240 4241 u8 reserved_at_80[0x4]; 4242 u8 cq_period[0xc]; 4243 u8 cq_max_count[0x10]; 4244 4245 u8 c_eqn_or_apu_element[0x20]; 4246 4247 u8 reserved_at_c0[0x3]; 4248 u8 log_page_size[0x5]; 4249 u8 reserved_at_c8[0x18]; 4250 4251 u8 reserved_at_e0[0x20]; 4252 4253 u8 reserved_at_100[0x8]; 4254 u8 last_notified_index[0x18]; 4255 4256 u8 reserved_at_120[0x8]; 4257 u8 last_solicit_index[0x18]; 4258 4259 u8 reserved_at_140[0x8]; 4260 u8 consumer_counter[0x18]; 4261 4262 u8 reserved_at_160[0x8]; 4263 u8 producer_counter[0x18]; 4264 4265 u8 reserved_at_180[0x40]; 4266 4267 u8 dbr_addr[0x40]; 4268 }; 4269 4270 union mlx5_ifc_cong_control_roce_ecn_auto_bits { 4271 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp; 4272 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp; 4273 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np; 4274 u8 reserved_at_0[0x800]; 4275 }; 4276 4277 struct mlx5_ifc_query_adapter_param_block_bits { 4278 u8 reserved_at_0[0xc0]; 4279 4280 u8 reserved_at_c0[0x8]; 4281 u8 ieee_vendor_id[0x18]; 4282 4283 u8 reserved_at_e0[0x10]; 4284 u8 vsd_vendor_id[0x10]; 4285 4286 u8 vsd[208][0x8]; 4287 4288 u8 vsd_contd_psid[16][0x8]; 4289 }; 4290 4291 enum { 4292 MLX5_XRQC_STATE_GOOD = 0x0, 4293 MLX5_XRQC_STATE_ERROR = 0x1, 4294 }; 4295 4296 enum { 4297 MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0, 4298 MLX5_XRQC_TOPOLOGY_TAG_MATCHING = 0x1, 4299 }; 4300 4301 enum { 4302 MLX5_XRQC_OFFLOAD_RNDV = 0x1, 4303 }; 4304 4305 struct mlx5_ifc_tag_matching_topology_context_bits { 4306 u8 log_matching_list_sz[0x4]; 4307 u8 reserved_at_4[0xc]; 4308 u8 append_next_index[0x10]; 4309 4310 u8 sw_phase_cnt[0x10]; 4311 u8 hw_phase_cnt[0x10]; 4312 4313 u8 reserved_at_40[0x40]; 4314 }; 4315 4316 struct mlx5_ifc_xrqc_bits { 4317 u8 state[0x4]; 4318 u8 rlkey[0x1]; 4319 u8 reserved_at_5[0xf]; 4320 u8 topology[0x4]; 4321 u8 reserved_at_18[0x4]; 4322 u8 offload[0x4]; 4323 4324 u8 reserved_at_20[0x8]; 4325 u8 user_index[0x18]; 4326 4327 u8 reserved_at_40[0x8]; 4328 u8 cqn[0x18]; 4329 4330 u8 reserved_at_60[0xa0]; 4331 4332 struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context; 4333 4334 u8 reserved_at_180[0x280]; 4335 4336 struct mlx5_ifc_wq_bits wq; 4337 }; 4338 4339 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits { 4340 struct mlx5_ifc_modify_field_select_bits modify_field_select; 4341 struct mlx5_ifc_resize_field_select_bits resize_field_select; 4342 u8 reserved_at_0[0x20]; 4343 }; 4344 4345 union mlx5_ifc_field_select_802_1_r_roce_auto_bits { 4346 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp; 4347 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp; 4348 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np; 4349 u8 reserved_at_0[0x20]; 4350 }; 4351 4352 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits { 4353 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 4354 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 4355 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 4356 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 4357 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 4358 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 4359 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout; 4360 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout; 4361 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 4362 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 4363 struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs; 4364 u8 reserved_at_0[0x7c0]; 4365 }; 4366 4367 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits { 4368 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout; 4369 u8 reserved_at_0[0x7c0]; 4370 }; 4371 4372 union mlx5_ifc_event_auto_bits { 4373 struct mlx5_ifc_comp_event_bits comp_event; 4374 struct mlx5_ifc_dct_events_bits dct_events; 4375 struct mlx5_ifc_qp_events_bits qp_events; 4376 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event; 4377 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event; 4378 struct mlx5_ifc_cq_error_bits cq_error; 4379 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged; 4380 struct mlx5_ifc_port_state_change_event_bits port_state_change_event; 4381 struct mlx5_ifc_gpio_event_bits gpio_event; 4382 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event; 4383 struct mlx5_ifc_stall_vl_event_bits stall_vl_event; 4384 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event; 4385 u8 reserved_at_0[0xe0]; 4386 }; 4387 4388 struct mlx5_ifc_health_buffer_bits { 4389 u8 reserved_at_0[0x100]; 4390 4391 u8 assert_existptr[0x20]; 4392 4393 u8 assert_callra[0x20]; 4394 4395 u8 reserved_at_140[0x20]; 4396 4397 u8 time[0x20]; 4398 4399 u8 fw_version[0x20]; 4400 4401 u8 hw_id[0x20]; 4402 4403 u8 rfr[0x1]; 4404 u8 reserved_at_1c1[0x3]; 4405 u8 valid[0x1]; 4406 u8 severity[0x3]; 4407 u8 reserved_at_1c8[0x18]; 4408 4409 u8 irisc_index[0x8]; 4410 u8 synd[0x8]; 4411 u8 ext_synd[0x10]; 4412 }; 4413 4414 struct mlx5_ifc_register_loopback_control_bits { 4415 u8 no_lb[0x1]; 4416 u8 reserved_at_1[0x7]; 4417 u8 port[0x8]; 4418 u8 reserved_at_10[0x10]; 4419 4420 u8 reserved_at_20[0x60]; 4421 }; 4422 4423 struct mlx5_ifc_vport_tc_element_bits { 4424 u8 traffic_class[0x4]; 4425 u8 reserved_at_4[0xc]; 4426 u8 vport_number[0x10]; 4427 }; 4428 4429 struct mlx5_ifc_vport_element_bits { 4430 u8 reserved_at_0[0x10]; 4431 u8 vport_number[0x10]; 4432 }; 4433 4434 enum { 4435 TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0, 4436 TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1, 4437 TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2, 4438 }; 4439 4440 struct mlx5_ifc_tsar_element_bits { 4441 u8 reserved_at_0[0x8]; 4442 u8 tsar_type[0x8]; 4443 u8 reserved_at_10[0x10]; 4444 }; 4445 4446 enum { 4447 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0, 4448 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1, 4449 }; 4450 4451 struct mlx5_ifc_teardown_hca_out_bits { 4452 u8 status[0x8]; 4453 u8 reserved_at_8[0x18]; 4454 4455 u8 syndrome[0x20]; 4456 4457 u8 reserved_at_40[0x3f]; 4458 4459 u8 state[0x1]; 4460 }; 4461 4462 enum { 4463 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0, 4464 MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE = 0x1, 4465 MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN = 0x2, 4466 }; 4467 4468 struct mlx5_ifc_teardown_hca_in_bits { 4469 u8 opcode[0x10]; 4470 u8 reserved_at_10[0x10]; 4471 4472 u8 reserved_at_20[0x10]; 4473 u8 op_mod[0x10]; 4474 4475 u8 reserved_at_40[0x10]; 4476 u8 profile[0x10]; 4477 4478 u8 reserved_at_60[0x20]; 4479 }; 4480 4481 struct mlx5_ifc_sqerr2rts_qp_out_bits { 4482 u8 status[0x8]; 4483 u8 reserved_at_8[0x18]; 4484 4485 u8 syndrome[0x20]; 4486 4487 u8 reserved_at_40[0x40]; 4488 }; 4489 4490 struct mlx5_ifc_sqerr2rts_qp_in_bits { 4491 u8 opcode[0x10]; 4492 u8 uid[0x10]; 4493 4494 u8 reserved_at_20[0x10]; 4495 u8 op_mod[0x10]; 4496 4497 u8 reserved_at_40[0x8]; 4498 u8 qpn[0x18]; 4499 4500 u8 reserved_at_60[0x20]; 4501 4502 u8 opt_param_mask[0x20]; 4503 4504 u8 reserved_at_a0[0x20]; 4505 4506 struct mlx5_ifc_qpc_bits qpc; 4507 4508 u8 reserved_at_800[0x80]; 4509 }; 4510 4511 struct mlx5_ifc_sqd2rts_qp_out_bits { 4512 u8 status[0x8]; 4513 u8 reserved_at_8[0x18]; 4514 4515 u8 syndrome[0x20]; 4516 4517 u8 reserved_at_40[0x40]; 4518 }; 4519 4520 struct mlx5_ifc_sqd2rts_qp_in_bits { 4521 u8 opcode[0x10]; 4522 u8 uid[0x10]; 4523 4524 u8 reserved_at_20[0x10]; 4525 u8 op_mod[0x10]; 4526 4527 u8 reserved_at_40[0x8]; 4528 u8 qpn[0x18]; 4529 4530 u8 reserved_at_60[0x20]; 4531 4532 u8 opt_param_mask[0x20]; 4533 4534 u8 reserved_at_a0[0x20]; 4535 4536 struct mlx5_ifc_qpc_bits qpc; 4537 4538 u8 reserved_at_800[0x80]; 4539 }; 4540 4541 struct mlx5_ifc_set_roce_address_out_bits { 4542 u8 status[0x8]; 4543 u8 reserved_at_8[0x18]; 4544 4545 u8 syndrome[0x20]; 4546 4547 u8 reserved_at_40[0x40]; 4548 }; 4549 4550 struct mlx5_ifc_set_roce_address_in_bits { 4551 u8 opcode[0x10]; 4552 u8 reserved_at_10[0x10]; 4553 4554 u8 reserved_at_20[0x10]; 4555 u8 op_mod[0x10]; 4556 4557 u8 roce_address_index[0x10]; 4558 u8 reserved_at_50[0xc]; 4559 u8 vhca_port_num[0x4]; 4560 4561 u8 reserved_at_60[0x20]; 4562 4563 struct mlx5_ifc_roce_addr_layout_bits roce_address; 4564 }; 4565 4566 struct mlx5_ifc_set_mad_demux_out_bits { 4567 u8 status[0x8]; 4568 u8 reserved_at_8[0x18]; 4569 4570 u8 syndrome[0x20]; 4571 4572 u8 reserved_at_40[0x40]; 4573 }; 4574 4575 enum { 4576 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0, 4577 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2, 4578 }; 4579 4580 struct mlx5_ifc_set_mad_demux_in_bits { 4581 u8 opcode[0x10]; 4582 u8 reserved_at_10[0x10]; 4583 4584 u8 reserved_at_20[0x10]; 4585 u8 op_mod[0x10]; 4586 4587 u8 reserved_at_40[0x20]; 4588 4589 u8 reserved_at_60[0x6]; 4590 u8 demux_mode[0x2]; 4591 u8 reserved_at_68[0x18]; 4592 }; 4593 4594 struct mlx5_ifc_set_l2_table_entry_out_bits { 4595 u8 status[0x8]; 4596 u8 reserved_at_8[0x18]; 4597 4598 u8 syndrome[0x20]; 4599 4600 u8 reserved_at_40[0x40]; 4601 }; 4602 4603 struct mlx5_ifc_set_l2_table_entry_in_bits { 4604 u8 opcode[0x10]; 4605 u8 reserved_at_10[0x10]; 4606 4607 u8 reserved_at_20[0x10]; 4608 u8 op_mod[0x10]; 4609 4610 u8 reserved_at_40[0x60]; 4611 4612 u8 reserved_at_a0[0x8]; 4613 u8 table_index[0x18]; 4614 4615 u8 reserved_at_c0[0x20]; 4616 4617 u8 reserved_at_e0[0x13]; 4618 u8 vlan_valid[0x1]; 4619 u8 vlan[0xc]; 4620 4621 struct mlx5_ifc_mac_address_layout_bits mac_address; 4622 4623 u8 reserved_at_140[0xc0]; 4624 }; 4625 4626 struct mlx5_ifc_set_issi_out_bits { 4627 u8 status[0x8]; 4628 u8 reserved_at_8[0x18]; 4629 4630 u8 syndrome[0x20]; 4631 4632 u8 reserved_at_40[0x40]; 4633 }; 4634 4635 struct mlx5_ifc_set_issi_in_bits { 4636 u8 opcode[0x10]; 4637 u8 reserved_at_10[0x10]; 4638 4639 u8 reserved_at_20[0x10]; 4640 u8 op_mod[0x10]; 4641 4642 u8 reserved_at_40[0x10]; 4643 u8 current_issi[0x10]; 4644 4645 u8 reserved_at_60[0x20]; 4646 }; 4647 4648 struct mlx5_ifc_set_hca_cap_out_bits { 4649 u8 status[0x8]; 4650 u8 reserved_at_8[0x18]; 4651 4652 u8 syndrome[0x20]; 4653 4654 u8 reserved_at_40[0x40]; 4655 }; 4656 4657 struct mlx5_ifc_set_hca_cap_in_bits { 4658 u8 opcode[0x10]; 4659 u8 reserved_at_10[0x10]; 4660 4661 u8 reserved_at_20[0x10]; 4662 u8 op_mod[0x10]; 4663 4664 u8 other_function[0x1]; 4665 u8 reserved_at_41[0xf]; 4666 u8 function_id[0x10]; 4667 4668 u8 reserved_at_60[0x20]; 4669 4670 union mlx5_ifc_hca_cap_union_bits capability; 4671 }; 4672 4673 enum { 4674 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0, 4675 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1, 4676 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2, 4677 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3, 4678 MLX5_SET_FTE_MODIFY_ENABLE_MASK_IPSEC_OBJ_ID = 0x4 4679 }; 4680 4681 struct mlx5_ifc_set_fte_out_bits { 4682 u8 status[0x8]; 4683 u8 reserved_at_8[0x18]; 4684 4685 u8 syndrome[0x20]; 4686 4687 u8 reserved_at_40[0x40]; 4688 }; 4689 4690 struct mlx5_ifc_set_fte_in_bits { 4691 u8 opcode[0x10]; 4692 u8 reserved_at_10[0x10]; 4693 4694 u8 reserved_at_20[0x10]; 4695 u8 op_mod[0x10]; 4696 4697 u8 other_vport[0x1]; 4698 u8 reserved_at_41[0xf]; 4699 u8 vport_number[0x10]; 4700 4701 u8 reserved_at_60[0x20]; 4702 4703 u8 table_type[0x8]; 4704 u8 reserved_at_88[0x18]; 4705 4706 u8 reserved_at_a0[0x8]; 4707 u8 table_id[0x18]; 4708 4709 u8 ignore_flow_level[0x1]; 4710 u8 reserved_at_c1[0x17]; 4711 u8 modify_enable_mask[0x8]; 4712 4713 u8 reserved_at_e0[0x20]; 4714 4715 u8 flow_index[0x20]; 4716 4717 u8 reserved_at_120[0xe0]; 4718 4719 struct mlx5_ifc_flow_context_bits flow_context; 4720 }; 4721 4722 struct mlx5_ifc_rts2rts_qp_out_bits { 4723 u8 status[0x8]; 4724 u8 reserved_at_8[0x18]; 4725 4726 u8 syndrome[0x20]; 4727 4728 u8 reserved_at_40[0x20]; 4729 u8 ece[0x20]; 4730 }; 4731 4732 struct mlx5_ifc_rts2rts_qp_in_bits { 4733 u8 opcode[0x10]; 4734 u8 uid[0x10]; 4735 4736 u8 reserved_at_20[0x10]; 4737 u8 op_mod[0x10]; 4738 4739 u8 reserved_at_40[0x8]; 4740 u8 qpn[0x18]; 4741 4742 u8 reserved_at_60[0x20]; 4743 4744 u8 opt_param_mask[0x20]; 4745 4746 u8 ece[0x20]; 4747 4748 struct mlx5_ifc_qpc_bits qpc; 4749 4750 u8 reserved_at_800[0x80]; 4751 }; 4752 4753 struct mlx5_ifc_rtr2rts_qp_out_bits { 4754 u8 status[0x8]; 4755 u8 reserved_at_8[0x18]; 4756 4757 u8 syndrome[0x20]; 4758 4759 u8 reserved_at_40[0x20]; 4760 u8 ece[0x20]; 4761 }; 4762 4763 struct mlx5_ifc_rtr2rts_qp_in_bits { 4764 u8 opcode[0x10]; 4765 u8 uid[0x10]; 4766 4767 u8 reserved_at_20[0x10]; 4768 u8 op_mod[0x10]; 4769 4770 u8 reserved_at_40[0x8]; 4771 u8 qpn[0x18]; 4772 4773 u8 reserved_at_60[0x20]; 4774 4775 u8 opt_param_mask[0x20]; 4776 4777 u8 ece[0x20]; 4778 4779 struct mlx5_ifc_qpc_bits qpc; 4780 4781 u8 reserved_at_800[0x80]; 4782 }; 4783 4784 struct mlx5_ifc_rst2init_qp_out_bits { 4785 u8 status[0x8]; 4786 u8 reserved_at_8[0x18]; 4787 4788 u8 syndrome[0x20]; 4789 4790 u8 reserved_at_40[0x20]; 4791 u8 ece[0x20]; 4792 }; 4793 4794 struct mlx5_ifc_rst2init_qp_in_bits { 4795 u8 opcode[0x10]; 4796 u8 uid[0x10]; 4797 4798 u8 reserved_at_20[0x10]; 4799 u8 op_mod[0x10]; 4800 4801 u8 reserved_at_40[0x8]; 4802 u8 qpn[0x18]; 4803 4804 u8 reserved_at_60[0x20]; 4805 4806 u8 opt_param_mask[0x20]; 4807 4808 u8 ece[0x20]; 4809 4810 struct mlx5_ifc_qpc_bits qpc; 4811 4812 u8 reserved_at_800[0x80]; 4813 }; 4814 4815 struct mlx5_ifc_query_xrq_out_bits { 4816 u8 status[0x8]; 4817 u8 reserved_at_8[0x18]; 4818 4819 u8 syndrome[0x20]; 4820 4821 u8 reserved_at_40[0x40]; 4822 4823 struct mlx5_ifc_xrqc_bits xrq_context; 4824 }; 4825 4826 struct mlx5_ifc_query_xrq_in_bits { 4827 u8 opcode[0x10]; 4828 u8 reserved_at_10[0x10]; 4829 4830 u8 reserved_at_20[0x10]; 4831 u8 op_mod[0x10]; 4832 4833 u8 reserved_at_40[0x8]; 4834 u8 xrqn[0x18]; 4835 4836 u8 reserved_at_60[0x20]; 4837 }; 4838 4839 struct mlx5_ifc_query_xrc_srq_out_bits { 4840 u8 status[0x8]; 4841 u8 reserved_at_8[0x18]; 4842 4843 u8 syndrome[0x20]; 4844 4845 u8 reserved_at_40[0x40]; 4846 4847 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 4848 4849 u8 reserved_at_280[0x600]; 4850 4851 u8 pas[][0x40]; 4852 }; 4853 4854 struct mlx5_ifc_query_xrc_srq_in_bits { 4855 u8 opcode[0x10]; 4856 u8 reserved_at_10[0x10]; 4857 4858 u8 reserved_at_20[0x10]; 4859 u8 op_mod[0x10]; 4860 4861 u8 reserved_at_40[0x8]; 4862 u8 xrc_srqn[0x18]; 4863 4864 u8 reserved_at_60[0x20]; 4865 }; 4866 4867 enum { 4868 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0, 4869 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1, 4870 }; 4871 4872 struct mlx5_ifc_query_vport_state_out_bits { 4873 u8 status[0x8]; 4874 u8 reserved_at_8[0x18]; 4875 4876 u8 syndrome[0x20]; 4877 4878 u8 reserved_at_40[0x20]; 4879 4880 u8 reserved_at_60[0x18]; 4881 u8 admin_state[0x4]; 4882 u8 state[0x4]; 4883 }; 4884 4885 enum { 4886 MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT = 0x0, 4887 MLX5_VPORT_STATE_OP_MOD_ESW_VPORT = 0x1, 4888 MLX5_VPORT_STATE_OP_MOD_UPLINK = 0x2, 4889 }; 4890 4891 struct mlx5_ifc_arm_monitor_counter_in_bits { 4892 u8 opcode[0x10]; 4893 u8 uid[0x10]; 4894 4895 u8 reserved_at_20[0x10]; 4896 u8 op_mod[0x10]; 4897 4898 u8 reserved_at_40[0x20]; 4899 4900 u8 reserved_at_60[0x20]; 4901 }; 4902 4903 struct mlx5_ifc_arm_monitor_counter_out_bits { 4904 u8 status[0x8]; 4905 u8 reserved_at_8[0x18]; 4906 4907 u8 syndrome[0x20]; 4908 4909 u8 reserved_at_40[0x40]; 4910 }; 4911 4912 enum { 4913 MLX5_QUERY_MONITOR_CNT_TYPE_PPCNT = 0x0, 4914 MLX5_QUERY_MONITOR_CNT_TYPE_Q_COUNTER = 0x1, 4915 }; 4916 4917 enum mlx5_monitor_counter_ppcnt { 4918 MLX5_QUERY_MONITOR_PPCNT_IN_RANGE_LENGTH_ERRORS = 0x0, 4919 MLX5_QUERY_MONITOR_PPCNT_OUT_OF_RANGE_LENGTH_FIELD = 0x1, 4920 MLX5_QUERY_MONITOR_PPCNT_FRAME_TOO_LONG_ERRORS = 0x2, 4921 MLX5_QUERY_MONITOR_PPCNT_FRAME_CHECK_SEQUENCE_ERRORS = 0x3, 4922 MLX5_QUERY_MONITOR_PPCNT_ALIGNMENT_ERRORS = 0x4, 4923 MLX5_QUERY_MONITOR_PPCNT_IF_OUT_DISCARDS = 0x5, 4924 }; 4925 4926 enum { 4927 MLX5_QUERY_MONITOR_Q_COUNTER_RX_OUT_OF_BUFFER = 0x4, 4928 }; 4929 4930 struct mlx5_ifc_monitor_counter_output_bits { 4931 u8 reserved_at_0[0x4]; 4932 u8 type[0x4]; 4933 u8 reserved_at_8[0x8]; 4934 u8 counter[0x10]; 4935 4936 u8 counter_group_id[0x20]; 4937 }; 4938 4939 #define MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 (6) 4940 #define MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1 (1) 4941 #define MLX5_CMD_SET_MONITOR_NUM_COUNTER (MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 +\ 4942 MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1) 4943 4944 struct mlx5_ifc_set_monitor_counter_in_bits { 4945 u8 opcode[0x10]; 4946 u8 uid[0x10]; 4947 4948 u8 reserved_at_20[0x10]; 4949 u8 op_mod[0x10]; 4950 4951 u8 reserved_at_40[0x10]; 4952 u8 num_of_counters[0x10]; 4953 4954 u8 reserved_at_60[0x20]; 4955 4956 struct mlx5_ifc_monitor_counter_output_bits monitor_counter[MLX5_CMD_SET_MONITOR_NUM_COUNTER]; 4957 }; 4958 4959 struct mlx5_ifc_set_monitor_counter_out_bits { 4960 u8 status[0x8]; 4961 u8 reserved_at_8[0x18]; 4962 4963 u8 syndrome[0x20]; 4964 4965 u8 reserved_at_40[0x40]; 4966 }; 4967 4968 struct mlx5_ifc_query_vport_state_in_bits { 4969 u8 opcode[0x10]; 4970 u8 reserved_at_10[0x10]; 4971 4972 u8 reserved_at_20[0x10]; 4973 u8 op_mod[0x10]; 4974 4975 u8 other_vport[0x1]; 4976 u8 reserved_at_41[0xf]; 4977 u8 vport_number[0x10]; 4978 4979 u8 reserved_at_60[0x20]; 4980 }; 4981 4982 struct mlx5_ifc_query_vnic_env_out_bits { 4983 u8 status[0x8]; 4984 u8 reserved_at_8[0x18]; 4985 4986 u8 syndrome[0x20]; 4987 4988 u8 reserved_at_40[0x40]; 4989 4990 struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env; 4991 }; 4992 4993 enum { 4994 MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS = 0x0, 4995 }; 4996 4997 struct mlx5_ifc_query_vnic_env_in_bits { 4998 u8 opcode[0x10]; 4999 u8 reserved_at_10[0x10]; 5000 5001 u8 reserved_at_20[0x10]; 5002 u8 op_mod[0x10]; 5003 5004 u8 other_vport[0x1]; 5005 u8 reserved_at_41[0xf]; 5006 u8 vport_number[0x10]; 5007 5008 u8 reserved_at_60[0x20]; 5009 }; 5010 5011 struct mlx5_ifc_query_vport_counter_out_bits { 5012 u8 status[0x8]; 5013 u8 reserved_at_8[0x18]; 5014 5015 u8 syndrome[0x20]; 5016 5017 u8 reserved_at_40[0x40]; 5018 5019 struct mlx5_ifc_traffic_counter_bits received_errors; 5020 5021 struct mlx5_ifc_traffic_counter_bits transmit_errors; 5022 5023 struct mlx5_ifc_traffic_counter_bits received_ib_unicast; 5024 5025 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast; 5026 5027 struct mlx5_ifc_traffic_counter_bits received_ib_multicast; 5028 5029 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast; 5030 5031 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast; 5032 5033 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast; 5034 5035 struct mlx5_ifc_traffic_counter_bits received_eth_unicast; 5036 5037 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast; 5038 5039 struct mlx5_ifc_traffic_counter_bits received_eth_multicast; 5040 5041 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast; 5042 5043 u8 reserved_at_680[0xa00]; 5044 }; 5045 5046 enum { 5047 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0, 5048 }; 5049 5050 struct mlx5_ifc_query_vport_counter_in_bits { 5051 u8 opcode[0x10]; 5052 u8 reserved_at_10[0x10]; 5053 5054 u8 reserved_at_20[0x10]; 5055 u8 op_mod[0x10]; 5056 5057 u8 other_vport[0x1]; 5058 u8 reserved_at_41[0xb]; 5059 u8 port_num[0x4]; 5060 u8 vport_number[0x10]; 5061 5062 u8 reserved_at_60[0x60]; 5063 5064 u8 clear[0x1]; 5065 u8 reserved_at_c1[0x1f]; 5066 5067 u8 reserved_at_e0[0x20]; 5068 }; 5069 5070 struct mlx5_ifc_query_tis_out_bits { 5071 u8 status[0x8]; 5072 u8 reserved_at_8[0x18]; 5073 5074 u8 syndrome[0x20]; 5075 5076 u8 reserved_at_40[0x40]; 5077 5078 struct mlx5_ifc_tisc_bits tis_context; 5079 }; 5080 5081 struct mlx5_ifc_query_tis_in_bits { 5082 u8 opcode[0x10]; 5083 u8 reserved_at_10[0x10]; 5084 5085 u8 reserved_at_20[0x10]; 5086 u8 op_mod[0x10]; 5087 5088 u8 reserved_at_40[0x8]; 5089 u8 tisn[0x18]; 5090 5091 u8 reserved_at_60[0x20]; 5092 }; 5093 5094 struct mlx5_ifc_query_tir_out_bits { 5095 u8 status[0x8]; 5096 u8 reserved_at_8[0x18]; 5097 5098 u8 syndrome[0x20]; 5099 5100 u8 reserved_at_40[0xc0]; 5101 5102 struct mlx5_ifc_tirc_bits tir_context; 5103 }; 5104 5105 struct mlx5_ifc_query_tir_in_bits { 5106 u8 opcode[0x10]; 5107 u8 reserved_at_10[0x10]; 5108 5109 u8 reserved_at_20[0x10]; 5110 u8 op_mod[0x10]; 5111 5112 u8 reserved_at_40[0x8]; 5113 u8 tirn[0x18]; 5114 5115 u8 reserved_at_60[0x20]; 5116 }; 5117 5118 struct mlx5_ifc_query_srq_out_bits { 5119 u8 status[0x8]; 5120 u8 reserved_at_8[0x18]; 5121 5122 u8 syndrome[0x20]; 5123 5124 u8 reserved_at_40[0x40]; 5125 5126 struct mlx5_ifc_srqc_bits srq_context_entry; 5127 5128 u8 reserved_at_280[0x600]; 5129 5130 u8 pas[][0x40]; 5131 }; 5132 5133 struct mlx5_ifc_query_srq_in_bits { 5134 u8 opcode[0x10]; 5135 u8 reserved_at_10[0x10]; 5136 5137 u8 reserved_at_20[0x10]; 5138 u8 op_mod[0x10]; 5139 5140 u8 reserved_at_40[0x8]; 5141 u8 srqn[0x18]; 5142 5143 u8 reserved_at_60[0x20]; 5144 }; 5145 5146 struct mlx5_ifc_query_sq_out_bits { 5147 u8 status[0x8]; 5148 u8 reserved_at_8[0x18]; 5149 5150 u8 syndrome[0x20]; 5151 5152 u8 reserved_at_40[0xc0]; 5153 5154 struct mlx5_ifc_sqc_bits sq_context; 5155 }; 5156 5157 struct mlx5_ifc_query_sq_in_bits { 5158 u8 opcode[0x10]; 5159 u8 reserved_at_10[0x10]; 5160 5161 u8 reserved_at_20[0x10]; 5162 u8 op_mod[0x10]; 5163 5164 u8 reserved_at_40[0x8]; 5165 u8 sqn[0x18]; 5166 5167 u8 reserved_at_60[0x20]; 5168 }; 5169 5170 struct mlx5_ifc_query_special_contexts_out_bits { 5171 u8 status[0x8]; 5172 u8 reserved_at_8[0x18]; 5173 5174 u8 syndrome[0x20]; 5175 5176 u8 dump_fill_mkey[0x20]; 5177 5178 u8 resd_lkey[0x20]; 5179 5180 u8 null_mkey[0x20]; 5181 5182 u8 reserved_at_a0[0x60]; 5183 }; 5184 5185 struct mlx5_ifc_query_special_contexts_in_bits { 5186 u8 opcode[0x10]; 5187 u8 reserved_at_10[0x10]; 5188 5189 u8 reserved_at_20[0x10]; 5190 u8 op_mod[0x10]; 5191 5192 u8 reserved_at_40[0x40]; 5193 }; 5194 5195 struct mlx5_ifc_query_scheduling_element_out_bits { 5196 u8 opcode[0x10]; 5197 u8 reserved_at_10[0x10]; 5198 5199 u8 reserved_at_20[0x10]; 5200 u8 op_mod[0x10]; 5201 5202 u8 reserved_at_40[0xc0]; 5203 5204 struct mlx5_ifc_scheduling_context_bits scheduling_context; 5205 5206 u8 reserved_at_300[0x100]; 5207 }; 5208 5209 enum { 5210 SCHEDULING_HIERARCHY_E_SWITCH = 0x2, 5211 SCHEDULING_HIERARCHY_NIC = 0x3, 5212 }; 5213 5214 struct mlx5_ifc_query_scheduling_element_in_bits { 5215 u8 opcode[0x10]; 5216 u8 reserved_at_10[0x10]; 5217 5218 u8 reserved_at_20[0x10]; 5219 u8 op_mod[0x10]; 5220 5221 u8 scheduling_hierarchy[0x8]; 5222 u8 reserved_at_48[0x18]; 5223 5224 u8 scheduling_element_id[0x20]; 5225 5226 u8 reserved_at_80[0x180]; 5227 }; 5228 5229 struct mlx5_ifc_query_rqt_out_bits { 5230 u8 status[0x8]; 5231 u8 reserved_at_8[0x18]; 5232 5233 u8 syndrome[0x20]; 5234 5235 u8 reserved_at_40[0xc0]; 5236 5237 struct mlx5_ifc_rqtc_bits rqt_context; 5238 }; 5239 5240 struct mlx5_ifc_query_rqt_in_bits { 5241 u8 opcode[0x10]; 5242 u8 reserved_at_10[0x10]; 5243 5244 u8 reserved_at_20[0x10]; 5245 u8 op_mod[0x10]; 5246 5247 u8 reserved_at_40[0x8]; 5248 u8 rqtn[0x18]; 5249 5250 u8 reserved_at_60[0x20]; 5251 }; 5252 5253 struct mlx5_ifc_query_rq_out_bits { 5254 u8 status[0x8]; 5255 u8 reserved_at_8[0x18]; 5256 5257 u8 syndrome[0x20]; 5258 5259 u8 reserved_at_40[0xc0]; 5260 5261 struct mlx5_ifc_rqc_bits rq_context; 5262 }; 5263 5264 struct mlx5_ifc_query_rq_in_bits { 5265 u8 opcode[0x10]; 5266 u8 reserved_at_10[0x10]; 5267 5268 u8 reserved_at_20[0x10]; 5269 u8 op_mod[0x10]; 5270 5271 u8 reserved_at_40[0x8]; 5272 u8 rqn[0x18]; 5273 5274 u8 reserved_at_60[0x20]; 5275 }; 5276 5277 struct mlx5_ifc_query_roce_address_out_bits { 5278 u8 status[0x8]; 5279 u8 reserved_at_8[0x18]; 5280 5281 u8 syndrome[0x20]; 5282 5283 u8 reserved_at_40[0x40]; 5284 5285 struct mlx5_ifc_roce_addr_layout_bits roce_address; 5286 }; 5287 5288 struct mlx5_ifc_query_roce_address_in_bits { 5289 u8 opcode[0x10]; 5290 u8 reserved_at_10[0x10]; 5291 5292 u8 reserved_at_20[0x10]; 5293 u8 op_mod[0x10]; 5294 5295 u8 roce_address_index[0x10]; 5296 u8 reserved_at_50[0xc]; 5297 u8 vhca_port_num[0x4]; 5298 5299 u8 reserved_at_60[0x20]; 5300 }; 5301 5302 struct mlx5_ifc_query_rmp_out_bits { 5303 u8 status[0x8]; 5304 u8 reserved_at_8[0x18]; 5305 5306 u8 syndrome[0x20]; 5307 5308 u8 reserved_at_40[0xc0]; 5309 5310 struct mlx5_ifc_rmpc_bits rmp_context; 5311 }; 5312 5313 struct mlx5_ifc_query_rmp_in_bits { 5314 u8 opcode[0x10]; 5315 u8 reserved_at_10[0x10]; 5316 5317 u8 reserved_at_20[0x10]; 5318 u8 op_mod[0x10]; 5319 5320 u8 reserved_at_40[0x8]; 5321 u8 rmpn[0x18]; 5322 5323 u8 reserved_at_60[0x20]; 5324 }; 5325 5326 struct mlx5_ifc_query_qp_out_bits { 5327 u8 status[0x8]; 5328 u8 reserved_at_8[0x18]; 5329 5330 u8 syndrome[0x20]; 5331 5332 u8 reserved_at_40[0x40]; 5333 5334 u8 opt_param_mask[0x20]; 5335 5336 u8 ece[0x20]; 5337 5338 struct mlx5_ifc_qpc_bits qpc; 5339 5340 u8 reserved_at_800[0x80]; 5341 5342 u8 pas[][0x40]; 5343 }; 5344 5345 struct mlx5_ifc_query_qp_in_bits { 5346 u8 opcode[0x10]; 5347 u8 reserved_at_10[0x10]; 5348 5349 u8 reserved_at_20[0x10]; 5350 u8 op_mod[0x10]; 5351 5352 u8 reserved_at_40[0x8]; 5353 u8 qpn[0x18]; 5354 5355 u8 reserved_at_60[0x20]; 5356 }; 5357 5358 struct mlx5_ifc_query_q_counter_out_bits { 5359 u8 status[0x8]; 5360 u8 reserved_at_8[0x18]; 5361 5362 u8 syndrome[0x20]; 5363 5364 u8 reserved_at_40[0x40]; 5365 5366 u8 rx_write_requests[0x20]; 5367 5368 u8 reserved_at_a0[0x20]; 5369 5370 u8 rx_read_requests[0x20]; 5371 5372 u8 reserved_at_e0[0x20]; 5373 5374 u8 rx_atomic_requests[0x20]; 5375 5376 u8 reserved_at_120[0x20]; 5377 5378 u8 rx_dct_connect[0x20]; 5379 5380 u8 reserved_at_160[0x20]; 5381 5382 u8 out_of_buffer[0x20]; 5383 5384 u8 reserved_at_1a0[0x20]; 5385 5386 u8 out_of_sequence[0x20]; 5387 5388 u8 reserved_at_1e0[0x20]; 5389 5390 u8 duplicate_request[0x20]; 5391 5392 u8 reserved_at_220[0x20]; 5393 5394 u8 rnr_nak_retry_err[0x20]; 5395 5396 u8 reserved_at_260[0x20]; 5397 5398 u8 packet_seq_err[0x20]; 5399 5400 u8 reserved_at_2a0[0x20]; 5401 5402 u8 implied_nak_seq_err[0x20]; 5403 5404 u8 reserved_at_2e0[0x20]; 5405 5406 u8 local_ack_timeout_err[0x20]; 5407 5408 u8 reserved_at_320[0xa0]; 5409 5410 u8 resp_local_length_error[0x20]; 5411 5412 u8 req_local_length_error[0x20]; 5413 5414 u8 resp_local_qp_error[0x20]; 5415 5416 u8 local_operation_error[0x20]; 5417 5418 u8 resp_local_protection[0x20]; 5419 5420 u8 req_local_protection[0x20]; 5421 5422 u8 resp_cqe_error[0x20]; 5423 5424 u8 req_cqe_error[0x20]; 5425 5426 u8 req_mw_binding[0x20]; 5427 5428 u8 req_bad_response[0x20]; 5429 5430 u8 req_remote_invalid_request[0x20]; 5431 5432 u8 resp_remote_invalid_request[0x20]; 5433 5434 u8 req_remote_access_errors[0x20]; 5435 5436 u8 resp_remote_access_errors[0x20]; 5437 5438 u8 req_remote_operation_errors[0x20]; 5439 5440 u8 req_transport_retries_exceeded[0x20]; 5441 5442 u8 cq_overflow[0x20]; 5443 5444 u8 resp_cqe_flush_error[0x20]; 5445 5446 u8 req_cqe_flush_error[0x20]; 5447 5448 u8 reserved_at_620[0x20]; 5449 5450 u8 roce_adp_retrans[0x20]; 5451 5452 u8 roce_adp_retrans_to[0x20]; 5453 5454 u8 roce_slow_restart[0x20]; 5455 5456 u8 roce_slow_restart_cnps[0x20]; 5457 5458 u8 roce_slow_restart_trans[0x20]; 5459 5460 u8 reserved_at_6e0[0x120]; 5461 }; 5462 5463 struct mlx5_ifc_query_q_counter_in_bits { 5464 u8 opcode[0x10]; 5465 u8 reserved_at_10[0x10]; 5466 5467 u8 reserved_at_20[0x10]; 5468 u8 op_mod[0x10]; 5469 5470 u8 reserved_at_40[0x80]; 5471 5472 u8 clear[0x1]; 5473 u8 reserved_at_c1[0x1f]; 5474 5475 u8 reserved_at_e0[0x18]; 5476 u8 counter_set_id[0x8]; 5477 }; 5478 5479 struct mlx5_ifc_query_pages_out_bits { 5480 u8 status[0x8]; 5481 u8 reserved_at_8[0x18]; 5482 5483 u8 syndrome[0x20]; 5484 5485 u8 embedded_cpu_function[0x1]; 5486 u8 reserved_at_41[0xf]; 5487 u8 function_id[0x10]; 5488 5489 u8 num_pages[0x20]; 5490 }; 5491 5492 enum { 5493 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1, 5494 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2, 5495 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3, 5496 }; 5497 5498 struct mlx5_ifc_query_pages_in_bits { 5499 u8 opcode[0x10]; 5500 u8 reserved_at_10[0x10]; 5501 5502 u8 reserved_at_20[0x10]; 5503 u8 op_mod[0x10]; 5504 5505 u8 embedded_cpu_function[0x1]; 5506 u8 reserved_at_41[0xf]; 5507 u8 function_id[0x10]; 5508 5509 u8 reserved_at_60[0x20]; 5510 }; 5511 5512 struct mlx5_ifc_query_nic_vport_context_out_bits { 5513 u8 status[0x8]; 5514 u8 reserved_at_8[0x18]; 5515 5516 u8 syndrome[0x20]; 5517 5518 u8 reserved_at_40[0x40]; 5519 5520 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 5521 }; 5522 5523 struct mlx5_ifc_query_nic_vport_context_in_bits { 5524 u8 opcode[0x10]; 5525 u8 reserved_at_10[0x10]; 5526 5527 u8 reserved_at_20[0x10]; 5528 u8 op_mod[0x10]; 5529 5530 u8 other_vport[0x1]; 5531 u8 reserved_at_41[0xf]; 5532 u8 vport_number[0x10]; 5533 5534 u8 reserved_at_60[0x5]; 5535 u8 allowed_list_type[0x3]; 5536 u8 reserved_at_68[0x18]; 5537 }; 5538 5539 struct mlx5_ifc_query_mkey_out_bits { 5540 u8 status[0x8]; 5541 u8 reserved_at_8[0x18]; 5542 5543 u8 syndrome[0x20]; 5544 5545 u8 reserved_at_40[0x40]; 5546 5547 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 5548 5549 u8 reserved_at_280[0x600]; 5550 5551 u8 bsf0_klm0_pas_mtt0_1[16][0x8]; 5552 5553 u8 bsf1_klm1_pas_mtt2_3[16][0x8]; 5554 }; 5555 5556 struct mlx5_ifc_query_mkey_in_bits { 5557 u8 opcode[0x10]; 5558 u8 reserved_at_10[0x10]; 5559 5560 u8 reserved_at_20[0x10]; 5561 u8 op_mod[0x10]; 5562 5563 u8 reserved_at_40[0x8]; 5564 u8 mkey_index[0x18]; 5565 5566 u8 pg_access[0x1]; 5567 u8 reserved_at_61[0x1f]; 5568 }; 5569 5570 struct mlx5_ifc_query_mad_demux_out_bits { 5571 u8 status[0x8]; 5572 u8 reserved_at_8[0x18]; 5573 5574 u8 syndrome[0x20]; 5575 5576 u8 reserved_at_40[0x40]; 5577 5578 u8 mad_dumux_parameters_block[0x20]; 5579 }; 5580 5581 struct mlx5_ifc_query_mad_demux_in_bits { 5582 u8 opcode[0x10]; 5583 u8 reserved_at_10[0x10]; 5584 5585 u8 reserved_at_20[0x10]; 5586 u8 op_mod[0x10]; 5587 5588 u8 reserved_at_40[0x40]; 5589 }; 5590 5591 struct mlx5_ifc_query_l2_table_entry_out_bits { 5592 u8 status[0x8]; 5593 u8 reserved_at_8[0x18]; 5594 5595 u8 syndrome[0x20]; 5596 5597 u8 reserved_at_40[0xa0]; 5598 5599 u8 reserved_at_e0[0x13]; 5600 u8 vlan_valid[0x1]; 5601 u8 vlan[0xc]; 5602 5603 struct mlx5_ifc_mac_address_layout_bits mac_address; 5604 5605 u8 reserved_at_140[0xc0]; 5606 }; 5607 5608 struct mlx5_ifc_query_l2_table_entry_in_bits { 5609 u8 opcode[0x10]; 5610 u8 reserved_at_10[0x10]; 5611 5612 u8 reserved_at_20[0x10]; 5613 u8 op_mod[0x10]; 5614 5615 u8 reserved_at_40[0x60]; 5616 5617 u8 reserved_at_a0[0x8]; 5618 u8 table_index[0x18]; 5619 5620 u8 reserved_at_c0[0x140]; 5621 }; 5622 5623 struct mlx5_ifc_query_issi_out_bits { 5624 u8 status[0x8]; 5625 u8 reserved_at_8[0x18]; 5626 5627 u8 syndrome[0x20]; 5628 5629 u8 reserved_at_40[0x10]; 5630 u8 current_issi[0x10]; 5631 5632 u8 reserved_at_60[0xa0]; 5633 5634 u8 reserved_at_100[76][0x8]; 5635 u8 supported_issi_dw0[0x20]; 5636 }; 5637 5638 struct mlx5_ifc_query_issi_in_bits { 5639 u8 opcode[0x10]; 5640 u8 reserved_at_10[0x10]; 5641 5642 u8 reserved_at_20[0x10]; 5643 u8 op_mod[0x10]; 5644 5645 u8 reserved_at_40[0x40]; 5646 }; 5647 5648 struct mlx5_ifc_set_driver_version_out_bits { 5649 u8 status[0x8]; 5650 u8 reserved_0[0x18]; 5651 5652 u8 syndrome[0x20]; 5653 u8 reserved_1[0x40]; 5654 }; 5655 5656 struct mlx5_ifc_set_driver_version_in_bits { 5657 u8 opcode[0x10]; 5658 u8 reserved_0[0x10]; 5659 5660 u8 reserved_1[0x10]; 5661 u8 op_mod[0x10]; 5662 5663 u8 reserved_2[0x40]; 5664 u8 driver_version[64][0x8]; 5665 }; 5666 5667 struct mlx5_ifc_query_hca_vport_pkey_out_bits { 5668 u8 status[0x8]; 5669 u8 reserved_at_8[0x18]; 5670 5671 u8 syndrome[0x20]; 5672 5673 u8 reserved_at_40[0x40]; 5674 5675 struct mlx5_ifc_pkey_bits pkey[]; 5676 }; 5677 5678 struct mlx5_ifc_query_hca_vport_pkey_in_bits { 5679 u8 opcode[0x10]; 5680 u8 reserved_at_10[0x10]; 5681 5682 u8 reserved_at_20[0x10]; 5683 u8 op_mod[0x10]; 5684 5685 u8 other_vport[0x1]; 5686 u8 reserved_at_41[0xb]; 5687 u8 port_num[0x4]; 5688 u8 vport_number[0x10]; 5689 5690 u8 reserved_at_60[0x10]; 5691 u8 pkey_index[0x10]; 5692 }; 5693 5694 enum { 5695 MLX5_HCA_VPORT_SEL_PORT_GUID = 1 << 0, 5696 MLX5_HCA_VPORT_SEL_NODE_GUID = 1 << 1, 5697 MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2, 5698 }; 5699 5700 struct mlx5_ifc_query_hca_vport_gid_out_bits { 5701 u8 status[0x8]; 5702 u8 reserved_at_8[0x18]; 5703 5704 u8 syndrome[0x20]; 5705 5706 u8 reserved_at_40[0x20]; 5707 5708 u8 gids_num[0x10]; 5709 u8 reserved_at_70[0x10]; 5710 5711 struct mlx5_ifc_array128_auto_bits gid[]; 5712 }; 5713 5714 struct mlx5_ifc_query_hca_vport_gid_in_bits { 5715 u8 opcode[0x10]; 5716 u8 reserved_at_10[0x10]; 5717 5718 u8 reserved_at_20[0x10]; 5719 u8 op_mod[0x10]; 5720 5721 u8 other_vport[0x1]; 5722 u8 reserved_at_41[0xb]; 5723 u8 port_num[0x4]; 5724 u8 vport_number[0x10]; 5725 5726 u8 reserved_at_60[0x10]; 5727 u8 gid_index[0x10]; 5728 }; 5729 5730 struct mlx5_ifc_query_hca_vport_context_out_bits { 5731 u8 status[0x8]; 5732 u8 reserved_at_8[0x18]; 5733 5734 u8 syndrome[0x20]; 5735 5736 u8 reserved_at_40[0x40]; 5737 5738 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 5739 }; 5740 5741 struct mlx5_ifc_query_hca_vport_context_in_bits { 5742 u8 opcode[0x10]; 5743 u8 reserved_at_10[0x10]; 5744 5745 u8 reserved_at_20[0x10]; 5746 u8 op_mod[0x10]; 5747 5748 u8 other_vport[0x1]; 5749 u8 reserved_at_41[0xb]; 5750 u8 port_num[0x4]; 5751 u8 vport_number[0x10]; 5752 5753 u8 reserved_at_60[0x20]; 5754 }; 5755 5756 struct mlx5_ifc_query_hca_cap_out_bits { 5757 u8 status[0x8]; 5758 u8 reserved_at_8[0x18]; 5759 5760 u8 syndrome[0x20]; 5761 5762 u8 reserved_at_40[0x40]; 5763 5764 union mlx5_ifc_hca_cap_union_bits capability; 5765 }; 5766 5767 struct mlx5_ifc_query_hca_cap_in_bits { 5768 u8 opcode[0x10]; 5769 u8 reserved_at_10[0x10]; 5770 5771 u8 reserved_at_20[0x10]; 5772 u8 op_mod[0x10]; 5773 5774 u8 other_function[0x1]; 5775 u8 reserved_at_41[0xf]; 5776 u8 function_id[0x10]; 5777 5778 u8 reserved_at_60[0x20]; 5779 }; 5780 5781 struct mlx5_ifc_other_hca_cap_bits { 5782 u8 roce[0x1]; 5783 u8 reserved_at_1[0x27f]; 5784 }; 5785 5786 struct mlx5_ifc_query_other_hca_cap_out_bits { 5787 u8 status[0x8]; 5788 u8 reserved_at_8[0x18]; 5789 5790 u8 syndrome[0x20]; 5791 5792 u8 reserved_at_40[0x40]; 5793 5794 struct mlx5_ifc_other_hca_cap_bits other_capability; 5795 }; 5796 5797 struct mlx5_ifc_query_other_hca_cap_in_bits { 5798 u8 opcode[0x10]; 5799 u8 reserved_at_10[0x10]; 5800 5801 u8 reserved_at_20[0x10]; 5802 u8 op_mod[0x10]; 5803 5804 u8 reserved_at_40[0x10]; 5805 u8 function_id[0x10]; 5806 5807 u8 reserved_at_60[0x20]; 5808 }; 5809 5810 struct mlx5_ifc_modify_other_hca_cap_out_bits { 5811 u8 status[0x8]; 5812 u8 reserved_at_8[0x18]; 5813 5814 u8 syndrome[0x20]; 5815 5816 u8 reserved_at_40[0x40]; 5817 }; 5818 5819 struct mlx5_ifc_modify_other_hca_cap_in_bits { 5820 u8 opcode[0x10]; 5821 u8 reserved_at_10[0x10]; 5822 5823 u8 reserved_at_20[0x10]; 5824 u8 op_mod[0x10]; 5825 5826 u8 reserved_at_40[0x10]; 5827 u8 function_id[0x10]; 5828 u8 field_select[0x20]; 5829 5830 struct mlx5_ifc_other_hca_cap_bits other_capability; 5831 }; 5832 5833 struct mlx5_ifc_flow_table_context_bits { 5834 u8 reformat_en[0x1]; 5835 u8 decap_en[0x1]; 5836 u8 sw_owner[0x1]; 5837 u8 termination_table[0x1]; 5838 u8 table_miss_action[0x4]; 5839 u8 level[0x8]; 5840 u8 reserved_at_10[0x8]; 5841 u8 log_size[0x8]; 5842 5843 u8 reserved_at_20[0x8]; 5844 u8 table_miss_id[0x18]; 5845 5846 u8 reserved_at_40[0x8]; 5847 u8 lag_master_next_table_id[0x18]; 5848 5849 u8 reserved_at_60[0x60]; 5850 5851 u8 sw_owner_icm_root_1[0x40]; 5852 5853 u8 sw_owner_icm_root_0[0x40]; 5854 5855 }; 5856 5857 struct mlx5_ifc_query_flow_table_out_bits { 5858 u8 status[0x8]; 5859 u8 reserved_at_8[0x18]; 5860 5861 u8 syndrome[0x20]; 5862 5863 u8 reserved_at_40[0x80]; 5864 5865 struct mlx5_ifc_flow_table_context_bits flow_table_context; 5866 }; 5867 5868 struct mlx5_ifc_query_flow_table_in_bits { 5869 u8 opcode[0x10]; 5870 u8 reserved_at_10[0x10]; 5871 5872 u8 reserved_at_20[0x10]; 5873 u8 op_mod[0x10]; 5874 5875 u8 reserved_at_40[0x40]; 5876 5877 u8 table_type[0x8]; 5878 u8 reserved_at_88[0x18]; 5879 5880 u8 reserved_at_a0[0x8]; 5881 u8 table_id[0x18]; 5882 5883 u8 reserved_at_c0[0x140]; 5884 }; 5885 5886 struct mlx5_ifc_query_fte_out_bits { 5887 u8 status[0x8]; 5888 u8 reserved_at_8[0x18]; 5889 5890 u8 syndrome[0x20]; 5891 5892 u8 reserved_at_40[0x1c0]; 5893 5894 struct mlx5_ifc_flow_context_bits flow_context; 5895 }; 5896 5897 struct mlx5_ifc_query_fte_in_bits { 5898 u8 opcode[0x10]; 5899 u8 reserved_at_10[0x10]; 5900 5901 u8 reserved_at_20[0x10]; 5902 u8 op_mod[0x10]; 5903 5904 u8 reserved_at_40[0x40]; 5905 5906 u8 table_type[0x8]; 5907 u8 reserved_at_88[0x18]; 5908 5909 u8 reserved_at_a0[0x8]; 5910 u8 table_id[0x18]; 5911 5912 u8 reserved_at_c0[0x40]; 5913 5914 u8 flow_index[0x20]; 5915 5916 u8 reserved_at_120[0xe0]; 5917 }; 5918 5919 struct mlx5_ifc_match_definer_format_0_bits { 5920 u8 reserved_at_0[0x100]; 5921 5922 u8 metadata_reg_c_0[0x20]; 5923 5924 u8 metadata_reg_c_1[0x20]; 5925 5926 u8 outer_dmac_47_16[0x20]; 5927 5928 u8 outer_dmac_15_0[0x10]; 5929 u8 outer_ethertype[0x10]; 5930 5931 u8 reserved_at_180[0x1]; 5932 u8 sx_sniffer[0x1]; 5933 u8 functional_lb[0x1]; 5934 u8 outer_ip_frag[0x1]; 5935 u8 outer_qp_type[0x2]; 5936 u8 outer_encap_type[0x2]; 5937 u8 port_number[0x2]; 5938 u8 outer_l3_type[0x2]; 5939 u8 outer_l4_type[0x2]; 5940 u8 outer_first_vlan_type[0x2]; 5941 u8 outer_first_vlan_prio[0x3]; 5942 u8 outer_first_vlan_cfi[0x1]; 5943 u8 outer_first_vlan_vid[0xc]; 5944 5945 u8 outer_l4_type_ext[0x4]; 5946 u8 reserved_at_1a4[0x2]; 5947 u8 outer_ipsec_layer[0x2]; 5948 u8 outer_l2_type[0x2]; 5949 u8 force_lb[0x1]; 5950 u8 outer_l2_ok[0x1]; 5951 u8 outer_l3_ok[0x1]; 5952 u8 outer_l4_ok[0x1]; 5953 u8 outer_second_vlan_type[0x2]; 5954 u8 outer_second_vlan_prio[0x3]; 5955 u8 outer_second_vlan_cfi[0x1]; 5956 u8 outer_second_vlan_vid[0xc]; 5957 5958 u8 outer_smac_47_16[0x20]; 5959 5960 u8 outer_smac_15_0[0x10]; 5961 u8 inner_ipv4_checksum_ok[0x1]; 5962 u8 inner_l4_checksum_ok[0x1]; 5963 u8 outer_ipv4_checksum_ok[0x1]; 5964 u8 outer_l4_checksum_ok[0x1]; 5965 u8 inner_l3_ok[0x1]; 5966 u8 inner_l4_ok[0x1]; 5967 u8 outer_l3_ok_duplicate[0x1]; 5968 u8 outer_l4_ok_duplicate[0x1]; 5969 u8 outer_tcp_cwr[0x1]; 5970 u8 outer_tcp_ece[0x1]; 5971 u8 outer_tcp_urg[0x1]; 5972 u8 outer_tcp_ack[0x1]; 5973 u8 outer_tcp_psh[0x1]; 5974 u8 outer_tcp_rst[0x1]; 5975 u8 outer_tcp_syn[0x1]; 5976 u8 outer_tcp_fin[0x1]; 5977 }; 5978 5979 struct mlx5_ifc_match_definer_format_22_bits { 5980 u8 reserved_at_0[0x100]; 5981 5982 u8 outer_ip_src_addr[0x20]; 5983 5984 u8 outer_ip_dest_addr[0x20]; 5985 5986 u8 outer_l4_sport[0x10]; 5987 u8 outer_l4_dport[0x10]; 5988 5989 u8 reserved_at_160[0x1]; 5990 u8 sx_sniffer[0x1]; 5991 u8 functional_lb[0x1]; 5992 u8 outer_ip_frag[0x1]; 5993 u8 outer_qp_type[0x2]; 5994 u8 outer_encap_type[0x2]; 5995 u8 port_number[0x2]; 5996 u8 outer_l3_type[0x2]; 5997 u8 outer_l4_type[0x2]; 5998 u8 outer_first_vlan_type[0x2]; 5999 u8 outer_first_vlan_prio[0x3]; 6000 u8 outer_first_vlan_cfi[0x1]; 6001 u8 outer_first_vlan_vid[0xc]; 6002 6003 u8 metadata_reg_c_0[0x20]; 6004 6005 u8 outer_dmac_47_16[0x20]; 6006 6007 u8 outer_smac_47_16[0x20]; 6008 6009 u8 outer_smac_15_0[0x10]; 6010 u8 outer_dmac_15_0[0x10]; 6011 }; 6012 6013 struct mlx5_ifc_match_definer_format_23_bits { 6014 u8 reserved_at_0[0x100]; 6015 6016 u8 inner_ip_src_addr[0x20]; 6017 6018 u8 inner_ip_dest_addr[0x20]; 6019 6020 u8 inner_l4_sport[0x10]; 6021 u8 inner_l4_dport[0x10]; 6022 6023 u8 reserved_at_160[0x1]; 6024 u8 sx_sniffer[0x1]; 6025 u8 functional_lb[0x1]; 6026 u8 inner_ip_frag[0x1]; 6027 u8 inner_qp_type[0x2]; 6028 u8 inner_encap_type[0x2]; 6029 u8 port_number[0x2]; 6030 u8 inner_l3_type[0x2]; 6031 u8 inner_l4_type[0x2]; 6032 u8 inner_first_vlan_type[0x2]; 6033 u8 inner_first_vlan_prio[0x3]; 6034 u8 inner_first_vlan_cfi[0x1]; 6035 u8 inner_first_vlan_vid[0xc]; 6036 6037 u8 tunnel_header_0[0x20]; 6038 6039 u8 inner_dmac_47_16[0x20]; 6040 6041 u8 inner_smac_47_16[0x20]; 6042 6043 u8 inner_smac_15_0[0x10]; 6044 u8 inner_dmac_15_0[0x10]; 6045 }; 6046 6047 struct mlx5_ifc_match_definer_format_29_bits { 6048 u8 reserved_at_0[0xc0]; 6049 6050 u8 outer_ip_dest_addr[0x80]; 6051 6052 u8 outer_ip_src_addr[0x80]; 6053 6054 u8 outer_l4_sport[0x10]; 6055 u8 outer_l4_dport[0x10]; 6056 6057 u8 reserved_at_1e0[0x20]; 6058 }; 6059 6060 struct mlx5_ifc_match_definer_format_30_bits { 6061 u8 reserved_at_0[0xa0]; 6062 6063 u8 outer_ip_dest_addr[0x80]; 6064 6065 u8 outer_ip_src_addr[0x80]; 6066 6067 u8 outer_dmac_47_16[0x20]; 6068 6069 u8 outer_smac_47_16[0x20]; 6070 6071 u8 outer_smac_15_0[0x10]; 6072 u8 outer_dmac_15_0[0x10]; 6073 }; 6074 6075 struct mlx5_ifc_match_definer_format_31_bits { 6076 u8 reserved_at_0[0xc0]; 6077 6078 u8 inner_ip_dest_addr[0x80]; 6079 6080 u8 inner_ip_src_addr[0x80]; 6081 6082 u8 inner_l4_sport[0x10]; 6083 u8 inner_l4_dport[0x10]; 6084 6085 u8 reserved_at_1e0[0x20]; 6086 }; 6087 6088 struct mlx5_ifc_match_definer_format_32_bits { 6089 u8 reserved_at_0[0xa0]; 6090 6091 u8 inner_ip_dest_addr[0x80]; 6092 6093 u8 inner_ip_src_addr[0x80]; 6094 6095 u8 inner_dmac_47_16[0x20]; 6096 6097 u8 inner_smac_47_16[0x20]; 6098 6099 u8 inner_smac_15_0[0x10]; 6100 u8 inner_dmac_15_0[0x10]; 6101 }; 6102 6103 struct mlx5_ifc_match_definer_bits { 6104 u8 modify_field_select[0x40]; 6105 6106 u8 reserved_at_40[0x40]; 6107 6108 u8 reserved_at_80[0x10]; 6109 u8 format_id[0x10]; 6110 6111 u8 reserved_at_a0[0x160]; 6112 6113 u8 match_mask[16][0x20]; 6114 }; 6115 6116 struct mlx5_ifc_general_obj_in_cmd_hdr_bits { 6117 u8 opcode[0x10]; 6118 u8 uid[0x10]; 6119 6120 u8 vhca_tunnel_id[0x10]; 6121 u8 obj_type[0x10]; 6122 6123 u8 obj_id[0x20]; 6124 6125 u8 reserved_at_60[0x3]; 6126 u8 log_obj_range[0x5]; 6127 u8 reserved_at_68[0x18]; 6128 }; 6129 6130 struct mlx5_ifc_general_obj_out_cmd_hdr_bits { 6131 u8 status[0x8]; 6132 u8 reserved_at_8[0x18]; 6133 6134 u8 syndrome[0x20]; 6135 6136 u8 obj_id[0x20]; 6137 6138 u8 reserved_at_60[0x20]; 6139 }; 6140 6141 struct mlx5_ifc_create_match_definer_in_bits { 6142 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 6143 6144 struct mlx5_ifc_match_definer_bits obj_context; 6145 }; 6146 6147 struct mlx5_ifc_create_match_definer_out_bits { 6148 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 6149 }; 6150 6151 enum { 6152 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 6153 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 6154 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 6155 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3, 6156 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_3 = 0x4, 6157 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_4 = 0x5, 6158 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_5 = 0x6, 6159 }; 6160 6161 struct mlx5_ifc_query_flow_group_out_bits { 6162 u8 status[0x8]; 6163 u8 reserved_at_8[0x18]; 6164 6165 u8 syndrome[0x20]; 6166 6167 u8 reserved_at_40[0xa0]; 6168 6169 u8 start_flow_index[0x20]; 6170 6171 u8 reserved_at_100[0x20]; 6172 6173 u8 end_flow_index[0x20]; 6174 6175 u8 reserved_at_140[0xa0]; 6176 6177 u8 reserved_at_1e0[0x18]; 6178 u8 match_criteria_enable[0x8]; 6179 6180 struct mlx5_ifc_fte_match_param_bits match_criteria; 6181 6182 u8 reserved_at_1200[0xe00]; 6183 }; 6184 6185 struct mlx5_ifc_query_flow_group_in_bits { 6186 u8 opcode[0x10]; 6187 u8 reserved_at_10[0x10]; 6188 6189 u8 reserved_at_20[0x10]; 6190 u8 op_mod[0x10]; 6191 6192 u8 reserved_at_40[0x40]; 6193 6194 u8 table_type[0x8]; 6195 u8 reserved_at_88[0x18]; 6196 6197 u8 reserved_at_a0[0x8]; 6198 u8 table_id[0x18]; 6199 6200 u8 group_id[0x20]; 6201 6202 u8 reserved_at_e0[0x120]; 6203 }; 6204 6205 struct mlx5_ifc_query_flow_counter_out_bits { 6206 u8 status[0x8]; 6207 u8 reserved_at_8[0x18]; 6208 6209 u8 syndrome[0x20]; 6210 6211 u8 reserved_at_40[0x40]; 6212 6213 struct mlx5_ifc_traffic_counter_bits flow_statistics[]; 6214 }; 6215 6216 struct mlx5_ifc_query_flow_counter_in_bits { 6217 u8 opcode[0x10]; 6218 u8 reserved_at_10[0x10]; 6219 6220 u8 reserved_at_20[0x10]; 6221 u8 op_mod[0x10]; 6222 6223 u8 reserved_at_40[0x80]; 6224 6225 u8 clear[0x1]; 6226 u8 reserved_at_c1[0xf]; 6227 u8 num_of_counters[0x10]; 6228 6229 u8 flow_counter_id[0x20]; 6230 }; 6231 6232 struct mlx5_ifc_query_esw_vport_context_out_bits { 6233 u8 status[0x8]; 6234 u8 reserved_at_8[0x18]; 6235 6236 u8 syndrome[0x20]; 6237 6238 u8 reserved_at_40[0x40]; 6239 6240 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 6241 }; 6242 6243 struct mlx5_ifc_query_esw_vport_context_in_bits { 6244 u8 opcode[0x10]; 6245 u8 reserved_at_10[0x10]; 6246 6247 u8 reserved_at_20[0x10]; 6248 u8 op_mod[0x10]; 6249 6250 u8 other_vport[0x1]; 6251 u8 reserved_at_41[0xf]; 6252 u8 vport_number[0x10]; 6253 6254 u8 reserved_at_60[0x20]; 6255 }; 6256 6257 struct mlx5_ifc_modify_esw_vport_context_out_bits { 6258 u8 status[0x8]; 6259 u8 reserved_at_8[0x18]; 6260 6261 u8 syndrome[0x20]; 6262 6263 u8 reserved_at_40[0x40]; 6264 }; 6265 6266 struct mlx5_ifc_esw_vport_context_fields_select_bits { 6267 u8 reserved_at_0[0x1b]; 6268 u8 fdb_to_vport_reg_c_id[0x1]; 6269 u8 vport_cvlan_insert[0x1]; 6270 u8 vport_svlan_insert[0x1]; 6271 u8 vport_cvlan_strip[0x1]; 6272 u8 vport_svlan_strip[0x1]; 6273 }; 6274 6275 struct mlx5_ifc_modify_esw_vport_context_in_bits { 6276 u8 opcode[0x10]; 6277 u8 reserved_at_10[0x10]; 6278 6279 u8 reserved_at_20[0x10]; 6280 u8 op_mod[0x10]; 6281 6282 u8 other_vport[0x1]; 6283 u8 reserved_at_41[0xf]; 6284 u8 vport_number[0x10]; 6285 6286 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select; 6287 6288 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 6289 }; 6290 6291 struct mlx5_ifc_query_eq_out_bits { 6292 u8 status[0x8]; 6293 u8 reserved_at_8[0x18]; 6294 6295 u8 syndrome[0x20]; 6296 6297 u8 reserved_at_40[0x40]; 6298 6299 struct mlx5_ifc_eqc_bits eq_context_entry; 6300 6301 u8 reserved_at_280[0x40]; 6302 6303 u8 event_bitmask[0x40]; 6304 6305 u8 reserved_at_300[0x580]; 6306 6307 u8 pas[][0x40]; 6308 }; 6309 6310 struct mlx5_ifc_query_eq_in_bits { 6311 u8 opcode[0x10]; 6312 u8 reserved_at_10[0x10]; 6313 6314 u8 reserved_at_20[0x10]; 6315 u8 op_mod[0x10]; 6316 6317 u8 reserved_at_40[0x18]; 6318 u8 eq_number[0x8]; 6319 6320 u8 reserved_at_60[0x20]; 6321 }; 6322 6323 struct mlx5_ifc_packet_reformat_context_in_bits { 6324 u8 reformat_type[0x8]; 6325 u8 reserved_at_8[0x4]; 6326 u8 reformat_param_0[0x4]; 6327 u8 reserved_at_10[0x6]; 6328 u8 reformat_data_size[0xa]; 6329 6330 u8 reformat_param_1[0x8]; 6331 u8 reserved_at_28[0x8]; 6332 u8 reformat_data[2][0x8]; 6333 6334 u8 more_reformat_data[][0x8]; 6335 }; 6336 6337 struct mlx5_ifc_query_packet_reformat_context_out_bits { 6338 u8 status[0x8]; 6339 u8 reserved_at_8[0x18]; 6340 6341 u8 syndrome[0x20]; 6342 6343 u8 reserved_at_40[0xa0]; 6344 6345 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context[]; 6346 }; 6347 6348 struct mlx5_ifc_query_packet_reformat_context_in_bits { 6349 u8 opcode[0x10]; 6350 u8 reserved_at_10[0x10]; 6351 6352 u8 reserved_at_20[0x10]; 6353 u8 op_mod[0x10]; 6354 6355 u8 packet_reformat_id[0x20]; 6356 6357 u8 reserved_at_60[0xa0]; 6358 }; 6359 6360 struct mlx5_ifc_alloc_packet_reformat_context_out_bits { 6361 u8 status[0x8]; 6362 u8 reserved_at_8[0x18]; 6363 6364 u8 syndrome[0x20]; 6365 6366 u8 packet_reformat_id[0x20]; 6367 6368 u8 reserved_at_60[0x20]; 6369 }; 6370 6371 enum { 6372 MLX5_REFORMAT_CONTEXT_ANCHOR_MAC_START = 0x1, 6373 MLX5_REFORMAT_CONTEXT_ANCHOR_IP_START = 0x7, 6374 MLX5_REFORMAT_CONTEXT_ANCHOR_TCP_UDP_START = 0x9, 6375 }; 6376 6377 enum mlx5_reformat_ctx_type { 6378 MLX5_REFORMAT_TYPE_L2_TO_VXLAN = 0x0, 6379 MLX5_REFORMAT_TYPE_L2_TO_NVGRE = 0x1, 6380 MLX5_REFORMAT_TYPE_L2_TO_L2_TUNNEL = 0x2, 6381 MLX5_REFORMAT_TYPE_L3_TUNNEL_TO_L2 = 0x3, 6382 MLX5_REFORMAT_TYPE_L2_TO_L3_TUNNEL = 0x4, 6383 MLX5_REFORMAT_TYPE_INSERT_HDR = 0xf, 6384 MLX5_REFORMAT_TYPE_REMOVE_HDR = 0x10, 6385 MLX5_REFORMAT_TYPE_ADD_MACSEC = 0x11, 6386 MLX5_REFORMAT_TYPE_DEL_MACSEC = 0x12, 6387 }; 6388 6389 struct mlx5_ifc_alloc_packet_reformat_context_in_bits { 6390 u8 opcode[0x10]; 6391 u8 reserved_at_10[0x10]; 6392 6393 u8 reserved_at_20[0x10]; 6394 u8 op_mod[0x10]; 6395 6396 u8 reserved_at_40[0xa0]; 6397 6398 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context; 6399 }; 6400 6401 struct mlx5_ifc_dealloc_packet_reformat_context_out_bits { 6402 u8 status[0x8]; 6403 u8 reserved_at_8[0x18]; 6404 6405 u8 syndrome[0x20]; 6406 6407 u8 reserved_at_40[0x40]; 6408 }; 6409 6410 struct mlx5_ifc_dealloc_packet_reformat_context_in_bits { 6411 u8 opcode[0x10]; 6412 u8 reserved_at_10[0x10]; 6413 6414 u8 reserved_20[0x10]; 6415 u8 op_mod[0x10]; 6416 6417 u8 packet_reformat_id[0x20]; 6418 6419 u8 reserved_60[0x20]; 6420 }; 6421 6422 struct mlx5_ifc_set_action_in_bits { 6423 u8 action_type[0x4]; 6424 u8 field[0xc]; 6425 u8 reserved_at_10[0x3]; 6426 u8 offset[0x5]; 6427 u8 reserved_at_18[0x3]; 6428 u8 length[0x5]; 6429 6430 u8 data[0x20]; 6431 }; 6432 6433 struct mlx5_ifc_add_action_in_bits { 6434 u8 action_type[0x4]; 6435 u8 field[0xc]; 6436 u8 reserved_at_10[0x10]; 6437 6438 u8 data[0x20]; 6439 }; 6440 6441 struct mlx5_ifc_copy_action_in_bits { 6442 u8 action_type[0x4]; 6443 u8 src_field[0xc]; 6444 u8 reserved_at_10[0x3]; 6445 u8 src_offset[0x5]; 6446 u8 reserved_at_18[0x3]; 6447 u8 length[0x5]; 6448 6449 u8 reserved_at_20[0x4]; 6450 u8 dst_field[0xc]; 6451 u8 reserved_at_30[0x3]; 6452 u8 dst_offset[0x5]; 6453 u8 reserved_at_38[0x8]; 6454 }; 6455 6456 union mlx5_ifc_set_add_copy_action_in_auto_bits { 6457 struct mlx5_ifc_set_action_in_bits set_action_in; 6458 struct mlx5_ifc_add_action_in_bits add_action_in; 6459 struct mlx5_ifc_copy_action_in_bits copy_action_in; 6460 u8 reserved_at_0[0x40]; 6461 }; 6462 6463 enum { 6464 MLX5_ACTION_TYPE_SET = 0x1, 6465 MLX5_ACTION_TYPE_ADD = 0x2, 6466 MLX5_ACTION_TYPE_COPY = 0x3, 6467 }; 6468 6469 enum { 6470 MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16 = 0x1, 6471 MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0 = 0x2, 6472 MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE = 0x3, 6473 MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16 = 0x4, 6474 MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0 = 0x5, 6475 MLX5_ACTION_IN_FIELD_OUT_IP_DSCP = 0x6, 6476 MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS = 0x7, 6477 MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT = 0x8, 6478 MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT = 0x9, 6479 MLX5_ACTION_IN_FIELD_OUT_IP_TTL = 0xa, 6480 MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT = 0xb, 6481 MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT = 0xc, 6482 MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96 = 0xd, 6483 MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64 = 0xe, 6484 MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32 = 0xf, 6485 MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0 = 0x10, 6486 MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96 = 0x11, 6487 MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64 = 0x12, 6488 MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32 = 0x13, 6489 MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0 = 0x14, 6490 MLX5_ACTION_IN_FIELD_OUT_SIPV4 = 0x15, 6491 MLX5_ACTION_IN_FIELD_OUT_DIPV4 = 0x16, 6492 MLX5_ACTION_IN_FIELD_OUT_FIRST_VID = 0x17, 6493 MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47, 6494 MLX5_ACTION_IN_FIELD_METADATA_REG_A = 0x49, 6495 MLX5_ACTION_IN_FIELD_METADATA_REG_B = 0x50, 6496 MLX5_ACTION_IN_FIELD_METADATA_REG_C_0 = 0x51, 6497 MLX5_ACTION_IN_FIELD_METADATA_REG_C_1 = 0x52, 6498 MLX5_ACTION_IN_FIELD_METADATA_REG_C_2 = 0x53, 6499 MLX5_ACTION_IN_FIELD_METADATA_REG_C_3 = 0x54, 6500 MLX5_ACTION_IN_FIELD_METADATA_REG_C_4 = 0x55, 6501 MLX5_ACTION_IN_FIELD_METADATA_REG_C_5 = 0x56, 6502 MLX5_ACTION_IN_FIELD_METADATA_REG_C_6 = 0x57, 6503 MLX5_ACTION_IN_FIELD_METADATA_REG_C_7 = 0x58, 6504 MLX5_ACTION_IN_FIELD_OUT_TCP_SEQ_NUM = 0x59, 6505 MLX5_ACTION_IN_FIELD_OUT_TCP_ACK_NUM = 0x5B, 6506 MLX5_ACTION_IN_FIELD_IPSEC_SYNDROME = 0x5D, 6507 MLX5_ACTION_IN_FIELD_OUT_EMD_47_32 = 0x6F, 6508 MLX5_ACTION_IN_FIELD_OUT_EMD_31_0 = 0x70, 6509 }; 6510 6511 struct mlx5_ifc_alloc_modify_header_context_out_bits { 6512 u8 status[0x8]; 6513 u8 reserved_at_8[0x18]; 6514 6515 u8 syndrome[0x20]; 6516 6517 u8 modify_header_id[0x20]; 6518 6519 u8 reserved_at_60[0x20]; 6520 }; 6521 6522 struct mlx5_ifc_alloc_modify_header_context_in_bits { 6523 u8 opcode[0x10]; 6524 u8 reserved_at_10[0x10]; 6525 6526 u8 reserved_at_20[0x10]; 6527 u8 op_mod[0x10]; 6528 6529 u8 reserved_at_40[0x20]; 6530 6531 u8 table_type[0x8]; 6532 u8 reserved_at_68[0x10]; 6533 u8 num_of_actions[0x8]; 6534 6535 union mlx5_ifc_set_add_copy_action_in_auto_bits actions[]; 6536 }; 6537 6538 struct mlx5_ifc_dealloc_modify_header_context_out_bits { 6539 u8 status[0x8]; 6540 u8 reserved_at_8[0x18]; 6541 6542 u8 syndrome[0x20]; 6543 6544 u8 reserved_at_40[0x40]; 6545 }; 6546 6547 struct mlx5_ifc_dealloc_modify_header_context_in_bits { 6548 u8 opcode[0x10]; 6549 u8 reserved_at_10[0x10]; 6550 6551 u8 reserved_at_20[0x10]; 6552 u8 op_mod[0x10]; 6553 6554 u8 modify_header_id[0x20]; 6555 6556 u8 reserved_at_60[0x20]; 6557 }; 6558 6559 struct mlx5_ifc_query_modify_header_context_in_bits { 6560 u8 opcode[0x10]; 6561 u8 uid[0x10]; 6562 6563 u8 reserved_at_20[0x10]; 6564 u8 op_mod[0x10]; 6565 6566 u8 modify_header_id[0x20]; 6567 6568 u8 reserved_at_60[0xa0]; 6569 }; 6570 6571 struct mlx5_ifc_query_dct_out_bits { 6572 u8 status[0x8]; 6573 u8 reserved_at_8[0x18]; 6574 6575 u8 syndrome[0x20]; 6576 6577 u8 reserved_at_40[0x40]; 6578 6579 struct mlx5_ifc_dctc_bits dct_context_entry; 6580 6581 u8 reserved_at_280[0x180]; 6582 }; 6583 6584 struct mlx5_ifc_query_dct_in_bits { 6585 u8 opcode[0x10]; 6586 u8 reserved_at_10[0x10]; 6587 6588 u8 reserved_at_20[0x10]; 6589 u8 op_mod[0x10]; 6590 6591 u8 reserved_at_40[0x8]; 6592 u8 dctn[0x18]; 6593 6594 u8 reserved_at_60[0x20]; 6595 }; 6596 6597 struct mlx5_ifc_query_cq_out_bits { 6598 u8 status[0x8]; 6599 u8 reserved_at_8[0x18]; 6600 6601 u8 syndrome[0x20]; 6602 6603 u8 reserved_at_40[0x40]; 6604 6605 struct mlx5_ifc_cqc_bits cq_context; 6606 6607 u8 reserved_at_280[0x600]; 6608 6609 u8 pas[][0x40]; 6610 }; 6611 6612 struct mlx5_ifc_query_cq_in_bits { 6613 u8 opcode[0x10]; 6614 u8 reserved_at_10[0x10]; 6615 6616 u8 reserved_at_20[0x10]; 6617 u8 op_mod[0x10]; 6618 6619 u8 reserved_at_40[0x8]; 6620 u8 cqn[0x18]; 6621 6622 u8 reserved_at_60[0x20]; 6623 }; 6624 6625 struct mlx5_ifc_query_cong_status_out_bits { 6626 u8 status[0x8]; 6627 u8 reserved_at_8[0x18]; 6628 6629 u8 syndrome[0x20]; 6630 6631 u8 reserved_at_40[0x20]; 6632 6633 u8 enable[0x1]; 6634 u8 tag_enable[0x1]; 6635 u8 reserved_at_62[0x1e]; 6636 }; 6637 6638 struct mlx5_ifc_query_cong_status_in_bits { 6639 u8 opcode[0x10]; 6640 u8 reserved_at_10[0x10]; 6641 6642 u8 reserved_at_20[0x10]; 6643 u8 op_mod[0x10]; 6644 6645 u8 reserved_at_40[0x18]; 6646 u8 priority[0x4]; 6647 u8 cong_protocol[0x4]; 6648 6649 u8 reserved_at_60[0x20]; 6650 }; 6651 6652 struct mlx5_ifc_query_cong_statistics_out_bits { 6653 u8 status[0x8]; 6654 u8 reserved_at_8[0x18]; 6655 6656 u8 syndrome[0x20]; 6657 6658 u8 reserved_at_40[0x40]; 6659 6660 u8 rp_cur_flows[0x20]; 6661 6662 u8 sum_flows[0x20]; 6663 6664 u8 rp_cnp_ignored_high[0x20]; 6665 6666 u8 rp_cnp_ignored_low[0x20]; 6667 6668 u8 rp_cnp_handled_high[0x20]; 6669 6670 u8 rp_cnp_handled_low[0x20]; 6671 6672 u8 reserved_at_140[0x100]; 6673 6674 u8 time_stamp_high[0x20]; 6675 6676 u8 time_stamp_low[0x20]; 6677 6678 u8 accumulators_period[0x20]; 6679 6680 u8 np_ecn_marked_roce_packets_high[0x20]; 6681 6682 u8 np_ecn_marked_roce_packets_low[0x20]; 6683 6684 u8 np_cnp_sent_high[0x20]; 6685 6686 u8 np_cnp_sent_low[0x20]; 6687 6688 u8 reserved_at_320[0x560]; 6689 }; 6690 6691 struct mlx5_ifc_query_cong_statistics_in_bits { 6692 u8 opcode[0x10]; 6693 u8 reserved_at_10[0x10]; 6694 6695 u8 reserved_at_20[0x10]; 6696 u8 op_mod[0x10]; 6697 6698 u8 clear[0x1]; 6699 u8 reserved_at_41[0x1f]; 6700 6701 u8 reserved_at_60[0x20]; 6702 }; 6703 6704 struct mlx5_ifc_query_cong_params_out_bits { 6705 u8 status[0x8]; 6706 u8 reserved_at_8[0x18]; 6707 6708 u8 syndrome[0x20]; 6709 6710 u8 reserved_at_40[0x40]; 6711 6712 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 6713 }; 6714 6715 struct mlx5_ifc_query_cong_params_in_bits { 6716 u8 opcode[0x10]; 6717 u8 reserved_at_10[0x10]; 6718 6719 u8 reserved_at_20[0x10]; 6720 u8 op_mod[0x10]; 6721 6722 u8 reserved_at_40[0x1c]; 6723 u8 cong_protocol[0x4]; 6724 6725 u8 reserved_at_60[0x20]; 6726 }; 6727 6728 struct mlx5_ifc_query_adapter_out_bits { 6729 u8 status[0x8]; 6730 u8 reserved_at_8[0x18]; 6731 6732 u8 syndrome[0x20]; 6733 6734 u8 reserved_at_40[0x40]; 6735 6736 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct; 6737 }; 6738 6739 struct mlx5_ifc_query_adapter_in_bits { 6740 u8 opcode[0x10]; 6741 u8 reserved_at_10[0x10]; 6742 6743 u8 reserved_at_20[0x10]; 6744 u8 op_mod[0x10]; 6745 6746 u8 reserved_at_40[0x40]; 6747 }; 6748 6749 struct mlx5_ifc_qp_2rst_out_bits { 6750 u8 status[0x8]; 6751 u8 reserved_at_8[0x18]; 6752 6753 u8 syndrome[0x20]; 6754 6755 u8 reserved_at_40[0x40]; 6756 }; 6757 6758 struct mlx5_ifc_qp_2rst_in_bits { 6759 u8 opcode[0x10]; 6760 u8 uid[0x10]; 6761 6762 u8 reserved_at_20[0x10]; 6763 u8 op_mod[0x10]; 6764 6765 u8 reserved_at_40[0x8]; 6766 u8 qpn[0x18]; 6767 6768 u8 reserved_at_60[0x20]; 6769 }; 6770 6771 struct mlx5_ifc_qp_2err_out_bits { 6772 u8 status[0x8]; 6773 u8 reserved_at_8[0x18]; 6774 6775 u8 syndrome[0x20]; 6776 6777 u8 reserved_at_40[0x40]; 6778 }; 6779 6780 struct mlx5_ifc_qp_2err_in_bits { 6781 u8 opcode[0x10]; 6782 u8 uid[0x10]; 6783 6784 u8 reserved_at_20[0x10]; 6785 u8 op_mod[0x10]; 6786 6787 u8 reserved_at_40[0x8]; 6788 u8 qpn[0x18]; 6789 6790 u8 reserved_at_60[0x20]; 6791 }; 6792 6793 struct mlx5_ifc_page_fault_resume_out_bits { 6794 u8 status[0x8]; 6795 u8 reserved_at_8[0x18]; 6796 6797 u8 syndrome[0x20]; 6798 6799 u8 reserved_at_40[0x40]; 6800 }; 6801 6802 struct mlx5_ifc_page_fault_resume_in_bits { 6803 u8 opcode[0x10]; 6804 u8 reserved_at_10[0x10]; 6805 6806 u8 reserved_at_20[0x10]; 6807 u8 op_mod[0x10]; 6808 6809 u8 error[0x1]; 6810 u8 reserved_at_41[0x4]; 6811 u8 page_fault_type[0x3]; 6812 u8 wq_number[0x18]; 6813 6814 u8 reserved_at_60[0x8]; 6815 u8 token[0x18]; 6816 }; 6817 6818 struct mlx5_ifc_nop_out_bits { 6819 u8 status[0x8]; 6820 u8 reserved_at_8[0x18]; 6821 6822 u8 syndrome[0x20]; 6823 6824 u8 reserved_at_40[0x40]; 6825 }; 6826 6827 struct mlx5_ifc_nop_in_bits { 6828 u8 opcode[0x10]; 6829 u8 reserved_at_10[0x10]; 6830 6831 u8 reserved_at_20[0x10]; 6832 u8 op_mod[0x10]; 6833 6834 u8 reserved_at_40[0x40]; 6835 }; 6836 6837 struct mlx5_ifc_modify_vport_state_out_bits { 6838 u8 status[0x8]; 6839 u8 reserved_at_8[0x18]; 6840 6841 u8 syndrome[0x20]; 6842 6843 u8 reserved_at_40[0x40]; 6844 }; 6845 6846 struct mlx5_ifc_modify_vport_state_in_bits { 6847 u8 opcode[0x10]; 6848 u8 reserved_at_10[0x10]; 6849 6850 u8 reserved_at_20[0x10]; 6851 u8 op_mod[0x10]; 6852 6853 u8 other_vport[0x1]; 6854 u8 reserved_at_41[0xf]; 6855 u8 vport_number[0x10]; 6856 6857 u8 reserved_at_60[0x18]; 6858 u8 admin_state[0x4]; 6859 u8 reserved_at_7c[0x4]; 6860 }; 6861 6862 struct mlx5_ifc_modify_tis_out_bits { 6863 u8 status[0x8]; 6864 u8 reserved_at_8[0x18]; 6865 6866 u8 syndrome[0x20]; 6867 6868 u8 reserved_at_40[0x40]; 6869 }; 6870 6871 struct mlx5_ifc_modify_tis_bitmask_bits { 6872 u8 reserved_at_0[0x20]; 6873 6874 u8 reserved_at_20[0x1d]; 6875 u8 lag_tx_port_affinity[0x1]; 6876 u8 strict_lag_tx_port_affinity[0x1]; 6877 u8 prio[0x1]; 6878 }; 6879 6880 struct mlx5_ifc_modify_tis_in_bits { 6881 u8 opcode[0x10]; 6882 u8 uid[0x10]; 6883 6884 u8 reserved_at_20[0x10]; 6885 u8 op_mod[0x10]; 6886 6887 u8 reserved_at_40[0x8]; 6888 u8 tisn[0x18]; 6889 6890 u8 reserved_at_60[0x20]; 6891 6892 struct mlx5_ifc_modify_tis_bitmask_bits bitmask; 6893 6894 u8 reserved_at_c0[0x40]; 6895 6896 struct mlx5_ifc_tisc_bits ctx; 6897 }; 6898 6899 struct mlx5_ifc_modify_tir_bitmask_bits { 6900 u8 reserved_at_0[0x20]; 6901 6902 u8 reserved_at_20[0x1b]; 6903 u8 self_lb_en[0x1]; 6904 u8 reserved_at_3c[0x1]; 6905 u8 hash[0x1]; 6906 u8 reserved_at_3e[0x1]; 6907 u8 packet_merge[0x1]; 6908 }; 6909 6910 struct mlx5_ifc_modify_tir_out_bits { 6911 u8 status[0x8]; 6912 u8 reserved_at_8[0x18]; 6913 6914 u8 syndrome[0x20]; 6915 6916 u8 reserved_at_40[0x40]; 6917 }; 6918 6919 struct mlx5_ifc_modify_tir_in_bits { 6920 u8 opcode[0x10]; 6921 u8 uid[0x10]; 6922 6923 u8 reserved_at_20[0x10]; 6924 u8 op_mod[0x10]; 6925 6926 u8 reserved_at_40[0x8]; 6927 u8 tirn[0x18]; 6928 6929 u8 reserved_at_60[0x20]; 6930 6931 struct mlx5_ifc_modify_tir_bitmask_bits bitmask; 6932 6933 u8 reserved_at_c0[0x40]; 6934 6935 struct mlx5_ifc_tirc_bits ctx; 6936 }; 6937 6938 struct mlx5_ifc_modify_sq_out_bits { 6939 u8 status[0x8]; 6940 u8 reserved_at_8[0x18]; 6941 6942 u8 syndrome[0x20]; 6943 6944 u8 reserved_at_40[0x40]; 6945 }; 6946 6947 struct mlx5_ifc_modify_sq_in_bits { 6948 u8 opcode[0x10]; 6949 u8 uid[0x10]; 6950 6951 u8 reserved_at_20[0x10]; 6952 u8 op_mod[0x10]; 6953 6954 u8 sq_state[0x4]; 6955 u8 reserved_at_44[0x4]; 6956 u8 sqn[0x18]; 6957 6958 u8 reserved_at_60[0x20]; 6959 6960 u8 modify_bitmask[0x40]; 6961 6962 u8 reserved_at_c0[0x40]; 6963 6964 struct mlx5_ifc_sqc_bits ctx; 6965 }; 6966 6967 struct mlx5_ifc_modify_scheduling_element_out_bits { 6968 u8 status[0x8]; 6969 u8 reserved_at_8[0x18]; 6970 6971 u8 syndrome[0x20]; 6972 6973 u8 reserved_at_40[0x1c0]; 6974 }; 6975 6976 enum { 6977 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1, 6978 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2, 6979 }; 6980 6981 struct mlx5_ifc_modify_scheduling_element_in_bits { 6982 u8 opcode[0x10]; 6983 u8 reserved_at_10[0x10]; 6984 6985 u8 reserved_at_20[0x10]; 6986 u8 op_mod[0x10]; 6987 6988 u8 scheduling_hierarchy[0x8]; 6989 u8 reserved_at_48[0x18]; 6990 6991 u8 scheduling_element_id[0x20]; 6992 6993 u8 reserved_at_80[0x20]; 6994 6995 u8 modify_bitmask[0x20]; 6996 6997 u8 reserved_at_c0[0x40]; 6998 6999 struct mlx5_ifc_scheduling_context_bits scheduling_context; 7000 7001 u8 reserved_at_300[0x100]; 7002 }; 7003 7004 struct mlx5_ifc_modify_rqt_out_bits { 7005 u8 status[0x8]; 7006 u8 reserved_at_8[0x18]; 7007 7008 u8 syndrome[0x20]; 7009 7010 u8 reserved_at_40[0x40]; 7011 }; 7012 7013 struct mlx5_ifc_rqt_bitmask_bits { 7014 u8 reserved_at_0[0x20]; 7015 7016 u8 reserved_at_20[0x1f]; 7017 u8 rqn_list[0x1]; 7018 }; 7019 7020 struct mlx5_ifc_modify_rqt_in_bits { 7021 u8 opcode[0x10]; 7022 u8 uid[0x10]; 7023 7024 u8 reserved_at_20[0x10]; 7025 u8 op_mod[0x10]; 7026 7027 u8 reserved_at_40[0x8]; 7028 u8 rqtn[0x18]; 7029 7030 u8 reserved_at_60[0x20]; 7031 7032 struct mlx5_ifc_rqt_bitmask_bits bitmask; 7033 7034 u8 reserved_at_c0[0x40]; 7035 7036 struct mlx5_ifc_rqtc_bits ctx; 7037 }; 7038 7039 struct mlx5_ifc_modify_rq_out_bits { 7040 u8 status[0x8]; 7041 u8 reserved_at_8[0x18]; 7042 7043 u8 syndrome[0x20]; 7044 7045 u8 reserved_at_40[0x40]; 7046 }; 7047 7048 enum { 7049 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1, 7050 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2, 7051 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3, 7052 }; 7053 7054 struct mlx5_ifc_modify_rq_in_bits { 7055 u8 opcode[0x10]; 7056 u8 uid[0x10]; 7057 7058 u8 reserved_at_20[0x10]; 7059 u8 op_mod[0x10]; 7060 7061 u8 rq_state[0x4]; 7062 u8 reserved_at_44[0x4]; 7063 u8 rqn[0x18]; 7064 7065 u8 reserved_at_60[0x20]; 7066 7067 u8 modify_bitmask[0x40]; 7068 7069 u8 reserved_at_c0[0x40]; 7070 7071 struct mlx5_ifc_rqc_bits ctx; 7072 }; 7073 7074 struct mlx5_ifc_modify_rmp_out_bits { 7075 u8 status[0x8]; 7076 u8 reserved_at_8[0x18]; 7077 7078 u8 syndrome[0x20]; 7079 7080 u8 reserved_at_40[0x40]; 7081 }; 7082 7083 struct mlx5_ifc_rmp_bitmask_bits { 7084 u8 reserved_at_0[0x20]; 7085 7086 u8 reserved_at_20[0x1f]; 7087 u8 lwm[0x1]; 7088 }; 7089 7090 struct mlx5_ifc_modify_rmp_in_bits { 7091 u8 opcode[0x10]; 7092 u8 uid[0x10]; 7093 7094 u8 reserved_at_20[0x10]; 7095 u8 op_mod[0x10]; 7096 7097 u8 rmp_state[0x4]; 7098 u8 reserved_at_44[0x4]; 7099 u8 rmpn[0x18]; 7100 7101 u8 reserved_at_60[0x20]; 7102 7103 struct mlx5_ifc_rmp_bitmask_bits bitmask; 7104 7105 u8 reserved_at_c0[0x40]; 7106 7107 struct mlx5_ifc_rmpc_bits ctx; 7108 }; 7109 7110 struct mlx5_ifc_modify_nic_vport_context_out_bits { 7111 u8 status[0x8]; 7112 u8 reserved_at_8[0x18]; 7113 7114 u8 syndrome[0x20]; 7115 7116 u8 reserved_at_40[0x40]; 7117 }; 7118 7119 struct mlx5_ifc_modify_nic_vport_field_select_bits { 7120 u8 reserved_at_0[0x12]; 7121 u8 affiliation[0x1]; 7122 u8 reserved_at_13[0x1]; 7123 u8 disable_uc_local_lb[0x1]; 7124 u8 disable_mc_local_lb[0x1]; 7125 u8 node_guid[0x1]; 7126 u8 port_guid[0x1]; 7127 u8 min_inline[0x1]; 7128 u8 mtu[0x1]; 7129 u8 change_event[0x1]; 7130 u8 promisc[0x1]; 7131 u8 permanent_address[0x1]; 7132 u8 addresses_list[0x1]; 7133 u8 roce_en[0x1]; 7134 u8 reserved_at_1f[0x1]; 7135 }; 7136 7137 struct mlx5_ifc_modify_nic_vport_context_in_bits { 7138 u8 opcode[0x10]; 7139 u8 reserved_at_10[0x10]; 7140 7141 u8 reserved_at_20[0x10]; 7142 u8 op_mod[0x10]; 7143 7144 u8 other_vport[0x1]; 7145 u8 reserved_at_41[0xf]; 7146 u8 vport_number[0x10]; 7147 7148 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select; 7149 7150 u8 reserved_at_80[0x780]; 7151 7152 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 7153 }; 7154 7155 struct mlx5_ifc_modify_hca_vport_context_out_bits { 7156 u8 status[0x8]; 7157 u8 reserved_at_8[0x18]; 7158 7159 u8 syndrome[0x20]; 7160 7161 u8 reserved_at_40[0x40]; 7162 }; 7163 7164 struct mlx5_ifc_modify_hca_vport_context_in_bits { 7165 u8 opcode[0x10]; 7166 u8 reserved_at_10[0x10]; 7167 7168 u8 reserved_at_20[0x10]; 7169 u8 op_mod[0x10]; 7170 7171 u8 other_vport[0x1]; 7172 u8 reserved_at_41[0xb]; 7173 u8 port_num[0x4]; 7174 u8 vport_number[0x10]; 7175 7176 u8 reserved_at_60[0x20]; 7177 7178 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 7179 }; 7180 7181 struct mlx5_ifc_modify_cq_out_bits { 7182 u8 status[0x8]; 7183 u8 reserved_at_8[0x18]; 7184 7185 u8 syndrome[0x20]; 7186 7187 u8 reserved_at_40[0x40]; 7188 }; 7189 7190 enum { 7191 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0, 7192 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1, 7193 }; 7194 7195 struct mlx5_ifc_modify_cq_in_bits { 7196 u8 opcode[0x10]; 7197 u8 uid[0x10]; 7198 7199 u8 reserved_at_20[0x10]; 7200 u8 op_mod[0x10]; 7201 7202 u8 reserved_at_40[0x8]; 7203 u8 cqn[0x18]; 7204 7205 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select; 7206 7207 struct mlx5_ifc_cqc_bits cq_context; 7208 7209 u8 reserved_at_280[0x60]; 7210 7211 u8 cq_umem_valid[0x1]; 7212 u8 reserved_at_2e1[0x1f]; 7213 7214 u8 reserved_at_300[0x580]; 7215 7216 u8 pas[][0x40]; 7217 }; 7218 7219 struct mlx5_ifc_modify_cong_status_out_bits { 7220 u8 status[0x8]; 7221 u8 reserved_at_8[0x18]; 7222 7223 u8 syndrome[0x20]; 7224 7225 u8 reserved_at_40[0x40]; 7226 }; 7227 7228 struct mlx5_ifc_modify_cong_status_in_bits { 7229 u8 opcode[0x10]; 7230 u8 reserved_at_10[0x10]; 7231 7232 u8 reserved_at_20[0x10]; 7233 u8 op_mod[0x10]; 7234 7235 u8 reserved_at_40[0x18]; 7236 u8 priority[0x4]; 7237 u8 cong_protocol[0x4]; 7238 7239 u8 enable[0x1]; 7240 u8 tag_enable[0x1]; 7241 u8 reserved_at_62[0x1e]; 7242 }; 7243 7244 struct mlx5_ifc_modify_cong_params_out_bits { 7245 u8 status[0x8]; 7246 u8 reserved_at_8[0x18]; 7247 7248 u8 syndrome[0x20]; 7249 7250 u8 reserved_at_40[0x40]; 7251 }; 7252 7253 struct mlx5_ifc_modify_cong_params_in_bits { 7254 u8 opcode[0x10]; 7255 u8 reserved_at_10[0x10]; 7256 7257 u8 reserved_at_20[0x10]; 7258 u8 op_mod[0x10]; 7259 7260 u8 reserved_at_40[0x1c]; 7261 u8 cong_protocol[0x4]; 7262 7263 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select; 7264 7265 u8 reserved_at_80[0x80]; 7266 7267 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 7268 }; 7269 7270 struct mlx5_ifc_manage_pages_out_bits { 7271 u8 status[0x8]; 7272 u8 reserved_at_8[0x18]; 7273 7274 u8 syndrome[0x20]; 7275 7276 u8 output_num_entries[0x20]; 7277 7278 u8 reserved_at_60[0x20]; 7279 7280 u8 pas[][0x40]; 7281 }; 7282 7283 enum { 7284 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL = 0x0, 7285 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS = 0x1, 7286 MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES = 0x2, 7287 }; 7288 7289 struct mlx5_ifc_manage_pages_in_bits { 7290 u8 opcode[0x10]; 7291 u8 reserved_at_10[0x10]; 7292 7293 u8 reserved_at_20[0x10]; 7294 u8 op_mod[0x10]; 7295 7296 u8 embedded_cpu_function[0x1]; 7297 u8 reserved_at_41[0xf]; 7298 u8 function_id[0x10]; 7299 7300 u8 input_num_entries[0x20]; 7301 7302 u8 pas[][0x40]; 7303 }; 7304 7305 struct mlx5_ifc_mad_ifc_out_bits { 7306 u8 status[0x8]; 7307 u8 reserved_at_8[0x18]; 7308 7309 u8 syndrome[0x20]; 7310 7311 u8 reserved_at_40[0x40]; 7312 7313 u8 response_mad_packet[256][0x8]; 7314 }; 7315 7316 struct mlx5_ifc_mad_ifc_in_bits { 7317 u8 opcode[0x10]; 7318 u8 reserved_at_10[0x10]; 7319 7320 u8 reserved_at_20[0x10]; 7321 u8 op_mod[0x10]; 7322 7323 u8 remote_lid[0x10]; 7324 u8 reserved_at_50[0x8]; 7325 u8 port[0x8]; 7326 7327 u8 reserved_at_60[0x20]; 7328 7329 u8 mad[256][0x8]; 7330 }; 7331 7332 struct mlx5_ifc_init_hca_out_bits { 7333 u8 status[0x8]; 7334 u8 reserved_at_8[0x18]; 7335 7336 u8 syndrome[0x20]; 7337 7338 u8 reserved_at_40[0x40]; 7339 }; 7340 7341 struct mlx5_ifc_init_hca_in_bits { 7342 u8 opcode[0x10]; 7343 u8 reserved_at_10[0x10]; 7344 7345 u8 reserved_at_20[0x10]; 7346 u8 op_mod[0x10]; 7347 7348 u8 reserved_at_40[0x20]; 7349 7350 u8 reserved_at_60[0x2]; 7351 u8 sw_vhca_id[0xe]; 7352 u8 reserved_at_70[0x10]; 7353 7354 u8 sw_owner_id[4][0x20]; 7355 }; 7356 7357 struct mlx5_ifc_init2rtr_qp_out_bits { 7358 u8 status[0x8]; 7359 u8 reserved_at_8[0x18]; 7360 7361 u8 syndrome[0x20]; 7362 7363 u8 reserved_at_40[0x20]; 7364 u8 ece[0x20]; 7365 }; 7366 7367 struct mlx5_ifc_init2rtr_qp_in_bits { 7368 u8 opcode[0x10]; 7369 u8 uid[0x10]; 7370 7371 u8 reserved_at_20[0x10]; 7372 u8 op_mod[0x10]; 7373 7374 u8 reserved_at_40[0x8]; 7375 u8 qpn[0x18]; 7376 7377 u8 reserved_at_60[0x20]; 7378 7379 u8 opt_param_mask[0x20]; 7380 7381 u8 ece[0x20]; 7382 7383 struct mlx5_ifc_qpc_bits qpc; 7384 7385 u8 reserved_at_800[0x80]; 7386 }; 7387 7388 struct mlx5_ifc_init2init_qp_out_bits { 7389 u8 status[0x8]; 7390 u8 reserved_at_8[0x18]; 7391 7392 u8 syndrome[0x20]; 7393 7394 u8 reserved_at_40[0x20]; 7395 u8 ece[0x20]; 7396 }; 7397 7398 struct mlx5_ifc_init2init_qp_in_bits { 7399 u8 opcode[0x10]; 7400 u8 uid[0x10]; 7401 7402 u8 reserved_at_20[0x10]; 7403 u8 op_mod[0x10]; 7404 7405 u8 reserved_at_40[0x8]; 7406 u8 qpn[0x18]; 7407 7408 u8 reserved_at_60[0x20]; 7409 7410 u8 opt_param_mask[0x20]; 7411 7412 u8 ece[0x20]; 7413 7414 struct mlx5_ifc_qpc_bits qpc; 7415 7416 u8 reserved_at_800[0x80]; 7417 }; 7418 7419 struct mlx5_ifc_get_dropped_packet_log_out_bits { 7420 u8 status[0x8]; 7421 u8 reserved_at_8[0x18]; 7422 7423 u8 syndrome[0x20]; 7424 7425 u8 reserved_at_40[0x40]; 7426 7427 u8 packet_headers_log[128][0x8]; 7428 7429 u8 packet_syndrome[64][0x8]; 7430 }; 7431 7432 struct mlx5_ifc_get_dropped_packet_log_in_bits { 7433 u8 opcode[0x10]; 7434 u8 reserved_at_10[0x10]; 7435 7436 u8 reserved_at_20[0x10]; 7437 u8 op_mod[0x10]; 7438 7439 u8 reserved_at_40[0x40]; 7440 }; 7441 7442 struct mlx5_ifc_gen_eqe_in_bits { 7443 u8 opcode[0x10]; 7444 u8 reserved_at_10[0x10]; 7445 7446 u8 reserved_at_20[0x10]; 7447 u8 op_mod[0x10]; 7448 7449 u8 reserved_at_40[0x18]; 7450 u8 eq_number[0x8]; 7451 7452 u8 reserved_at_60[0x20]; 7453 7454 u8 eqe[64][0x8]; 7455 }; 7456 7457 struct mlx5_ifc_gen_eq_out_bits { 7458 u8 status[0x8]; 7459 u8 reserved_at_8[0x18]; 7460 7461 u8 syndrome[0x20]; 7462 7463 u8 reserved_at_40[0x40]; 7464 }; 7465 7466 struct mlx5_ifc_enable_hca_out_bits { 7467 u8 status[0x8]; 7468 u8 reserved_at_8[0x18]; 7469 7470 u8 syndrome[0x20]; 7471 7472 u8 reserved_at_40[0x20]; 7473 }; 7474 7475 struct mlx5_ifc_enable_hca_in_bits { 7476 u8 opcode[0x10]; 7477 u8 reserved_at_10[0x10]; 7478 7479 u8 reserved_at_20[0x10]; 7480 u8 op_mod[0x10]; 7481 7482 u8 embedded_cpu_function[0x1]; 7483 u8 reserved_at_41[0xf]; 7484 u8 function_id[0x10]; 7485 7486 u8 reserved_at_60[0x20]; 7487 }; 7488 7489 struct mlx5_ifc_drain_dct_out_bits { 7490 u8 status[0x8]; 7491 u8 reserved_at_8[0x18]; 7492 7493 u8 syndrome[0x20]; 7494 7495 u8 reserved_at_40[0x40]; 7496 }; 7497 7498 struct mlx5_ifc_drain_dct_in_bits { 7499 u8 opcode[0x10]; 7500 u8 uid[0x10]; 7501 7502 u8 reserved_at_20[0x10]; 7503 u8 op_mod[0x10]; 7504 7505 u8 reserved_at_40[0x8]; 7506 u8 dctn[0x18]; 7507 7508 u8 reserved_at_60[0x20]; 7509 }; 7510 7511 struct mlx5_ifc_disable_hca_out_bits { 7512 u8 status[0x8]; 7513 u8 reserved_at_8[0x18]; 7514 7515 u8 syndrome[0x20]; 7516 7517 u8 reserved_at_40[0x20]; 7518 }; 7519 7520 struct mlx5_ifc_disable_hca_in_bits { 7521 u8 opcode[0x10]; 7522 u8 reserved_at_10[0x10]; 7523 7524 u8 reserved_at_20[0x10]; 7525 u8 op_mod[0x10]; 7526 7527 u8 embedded_cpu_function[0x1]; 7528 u8 reserved_at_41[0xf]; 7529 u8 function_id[0x10]; 7530 7531 u8 reserved_at_60[0x20]; 7532 }; 7533 7534 struct mlx5_ifc_detach_from_mcg_out_bits { 7535 u8 status[0x8]; 7536 u8 reserved_at_8[0x18]; 7537 7538 u8 syndrome[0x20]; 7539 7540 u8 reserved_at_40[0x40]; 7541 }; 7542 7543 struct mlx5_ifc_detach_from_mcg_in_bits { 7544 u8 opcode[0x10]; 7545 u8 uid[0x10]; 7546 7547 u8 reserved_at_20[0x10]; 7548 u8 op_mod[0x10]; 7549 7550 u8 reserved_at_40[0x8]; 7551 u8 qpn[0x18]; 7552 7553 u8 reserved_at_60[0x20]; 7554 7555 u8 multicast_gid[16][0x8]; 7556 }; 7557 7558 struct mlx5_ifc_destroy_xrq_out_bits { 7559 u8 status[0x8]; 7560 u8 reserved_at_8[0x18]; 7561 7562 u8 syndrome[0x20]; 7563 7564 u8 reserved_at_40[0x40]; 7565 }; 7566 7567 struct mlx5_ifc_destroy_xrq_in_bits { 7568 u8 opcode[0x10]; 7569 u8 uid[0x10]; 7570 7571 u8 reserved_at_20[0x10]; 7572 u8 op_mod[0x10]; 7573 7574 u8 reserved_at_40[0x8]; 7575 u8 xrqn[0x18]; 7576 7577 u8 reserved_at_60[0x20]; 7578 }; 7579 7580 struct mlx5_ifc_destroy_xrc_srq_out_bits { 7581 u8 status[0x8]; 7582 u8 reserved_at_8[0x18]; 7583 7584 u8 syndrome[0x20]; 7585 7586 u8 reserved_at_40[0x40]; 7587 }; 7588 7589 struct mlx5_ifc_destroy_xrc_srq_in_bits { 7590 u8 opcode[0x10]; 7591 u8 uid[0x10]; 7592 7593 u8 reserved_at_20[0x10]; 7594 u8 op_mod[0x10]; 7595 7596 u8 reserved_at_40[0x8]; 7597 u8 xrc_srqn[0x18]; 7598 7599 u8 reserved_at_60[0x20]; 7600 }; 7601 7602 struct mlx5_ifc_destroy_tis_out_bits { 7603 u8 status[0x8]; 7604 u8 reserved_at_8[0x18]; 7605 7606 u8 syndrome[0x20]; 7607 7608 u8 reserved_at_40[0x40]; 7609 }; 7610 7611 struct mlx5_ifc_destroy_tis_in_bits { 7612 u8 opcode[0x10]; 7613 u8 uid[0x10]; 7614 7615 u8 reserved_at_20[0x10]; 7616 u8 op_mod[0x10]; 7617 7618 u8 reserved_at_40[0x8]; 7619 u8 tisn[0x18]; 7620 7621 u8 reserved_at_60[0x20]; 7622 }; 7623 7624 struct mlx5_ifc_destroy_tir_out_bits { 7625 u8 status[0x8]; 7626 u8 reserved_at_8[0x18]; 7627 7628 u8 syndrome[0x20]; 7629 7630 u8 reserved_at_40[0x40]; 7631 }; 7632 7633 struct mlx5_ifc_destroy_tir_in_bits { 7634 u8 opcode[0x10]; 7635 u8 uid[0x10]; 7636 7637 u8 reserved_at_20[0x10]; 7638 u8 op_mod[0x10]; 7639 7640 u8 reserved_at_40[0x8]; 7641 u8 tirn[0x18]; 7642 7643 u8 reserved_at_60[0x20]; 7644 }; 7645 7646 struct mlx5_ifc_destroy_srq_out_bits { 7647 u8 status[0x8]; 7648 u8 reserved_at_8[0x18]; 7649 7650 u8 syndrome[0x20]; 7651 7652 u8 reserved_at_40[0x40]; 7653 }; 7654 7655 struct mlx5_ifc_destroy_srq_in_bits { 7656 u8 opcode[0x10]; 7657 u8 uid[0x10]; 7658 7659 u8 reserved_at_20[0x10]; 7660 u8 op_mod[0x10]; 7661 7662 u8 reserved_at_40[0x8]; 7663 u8 srqn[0x18]; 7664 7665 u8 reserved_at_60[0x20]; 7666 }; 7667 7668 struct mlx5_ifc_destroy_sq_out_bits { 7669 u8 status[0x8]; 7670 u8 reserved_at_8[0x18]; 7671 7672 u8 syndrome[0x20]; 7673 7674 u8 reserved_at_40[0x40]; 7675 }; 7676 7677 struct mlx5_ifc_destroy_sq_in_bits { 7678 u8 opcode[0x10]; 7679 u8 uid[0x10]; 7680 7681 u8 reserved_at_20[0x10]; 7682 u8 op_mod[0x10]; 7683 7684 u8 reserved_at_40[0x8]; 7685 u8 sqn[0x18]; 7686 7687 u8 reserved_at_60[0x20]; 7688 }; 7689 7690 struct mlx5_ifc_destroy_scheduling_element_out_bits { 7691 u8 status[0x8]; 7692 u8 reserved_at_8[0x18]; 7693 7694 u8 syndrome[0x20]; 7695 7696 u8 reserved_at_40[0x1c0]; 7697 }; 7698 7699 struct mlx5_ifc_destroy_scheduling_element_in_bits { 7700 u8 opcode[0x10]; 7701 u8 reserved_at_10[0x10]; 7702 7703 u8 reserved_at_20[0x10]; 7704 u8 op_mod[0x10]; 7705 7706 u8 scheduling_hierarchy[0x8]; 7707 u8 reserved_at_48[0x18]; 7708 7709 u8 scheduling_element_id[0x20]; 7710 7711 u8 reserved_at_80[0x180]; 7712 }; 7713 7714 struct mlx5_ifc_destroy_rqt_out_bits { 7715 u8 status[0x8]; 7716 u8 reserved_at_8[0x18]; 7717 7718 u8 syndrome[0x20]; 7719 7720 u8 reserved_at_40[0x40]; 7721 }; 7722 7723 struct mlx5_ifc_destroy_rqt_in_bits { 7724 u8 opcode[0x10]; 7725 u8 uid[0x10]; 7726 7727 u8 reserved_at_20[0x10]; 7728 u8 op_mod[0x10]; 7729 7730 u8 reserved_at_40[0x8]; 7731 u8 rqtn[0x18]; 7732 7733 u8 reserved_at_60[0x20]; 7734 }; 7735 7736 struct mlx5_ifc_destroy_rq_out_bits { 7737 u8 status[0x8]; 7738 u8 reserved_at_8[0x18]; 7739 7740 u8 syndrome[0x20]; 7741 7742 u8 reserved_at_40[0x40]; 7743 }; 7744 7745 struct mlx5_ifc_destroy_rq_in_bits { 7746 u8 opcode[0x10]; 7747 u8 uid[0x10]; 7748 7749 u8 reserved_at_20[0x10]; 7750 u8 op_mod[0x10]; 7751 7752 u8 reserved_at_40[0x8]; 7753 u8 rqn[0x18]; 7754 7755 u8 reserved_at_60[0x20]; 7756 }; 7757 7758 struct mlx5_ifc_set_delay_drop_params_in_bits { 7759 u8 opcode[0x10]; 7760 u8 reserved_at_10[0x10]; 7761 7762 u8 reserved_at_20[0x10]; 7763 u8 op_mod[0x10]; 7764 7765 u8 reserved_at_40[0x20]; 7766 7767 u8 reserved_at_60[0x10]; 7768 u8 delay_drop_timeout[0x10]; 7769 }; 7770 7771 struct mlx5_ifc_set_delay_drop_params_out_bits { 7772 u8 status[0x8]; 7773 u8 reserved_at_8[0x18]; 7774 7775 u8 syndrome[0x20]; 7776 7777 u8 reserved_at_40[0x40]; 7778 }; 7779 7780 struct mlx5_ifc_destroy_rmp_out_bits { 7781 u8 status[0x8]; 7782 u8 reserved_at_8[0x18]; 7783 7784 u8 syndrome[0x20]; 7785 7786 u8 reserved_at_40[0x40]; 7787 }; 7788 7789 struct mlx5_ifc_destroy_rmp_in_bits { 7790 u8 opcode[0x10]; 7791 u8 uid[0x10]; 7792 7793 u8 reserved_at_20[0x10]; 7794 u8 op_mod[0x10]; 7795 7796 u8 reserved_at_40[0x8]; 7797 u8 rmpn[0x18]; 7798 7799 u8 reserved_at_60[0x20]; 7800 }; 7801 7802 struct mlx5_ifc_destroy_qp_out_bits { 7803 u8 status[0x8]; 7804 u8 reserved_at_8[0x18]; 7805 7806 u8 syndrome[0x20]; 7807 7808 u8 reserved_at_40[0x40]; 7809 }; 7810 7811 struct mlx5_ifc_destroy_qp_in_bits { 7812 u8 opcode[0x10]; 7813 u8 uid[0x10]; 7814 7815 u8 reserved_at_20[0x10]; 7816 u8 op_mod[0x10]; 7817 7818 u8 reserved_at_40[0x8]; 7819 u8 qpn[0x18]; 7820 7821 u8 reserved_at_60[0x20]; 7822 }; 7823 7824 struct mlx5_ifc_destroy_psv_out_bits { 7825 u8 status[0x8]; 7826 u8 reserved_at_8[0x18]; 7827 7828 u8 syndrome[0x20]; 7829 7830 u8 reserved_at_40[0x40]; 7831 }; 7832 7833 struct mlx5_ifc_destroy_psv_in_bits { 7834 u8 opcode[0x10]; 7835 u8 reserved_at_10[0x10]; 7836 7837 u8 reserved_at_20[0x10]; 7838 u8 op_mod[0x10]; 7839 7840 u8 reserved_at_40[0x8]; 7841 u8 psvn[0x18]; 7842 7843 u8 reserved_at_60[0x20]; 7844 }; 7845 7846 struct mlx5_ifc_destroy_mkey_out_bits { 7847 u8 status[0x8]; 7848 u8 reserved_at_8[0x18]; 7849 7850 u8 syndrome[0x20]; 7851 7852 u8 reserved_at_40[0x40]; 7853 }; 7854 7855 struct mlx5_ifc_destroy_mkey_in_bits { 7856 u8 opcode[0x10]; 7857 u8 uid[0x10]; 7858 7859 u8 reserved_at_20[0x10]; 7860 u8 op_mod[0x10]; 7861 7862 u8 reserved_at_40[0x8]; 7863 u8 mkey_index[0x18]; 7864 7865 u8 reserved_at_60[0x20]; 7866 }; 7867 7868 struct mlx5_ifc_destroy_flow_table_out_bits { 7869 u8 status[0x8]; 7870 u8 reserved_at_8[0x18]; 7871 7872 u8 syndrome[0x20]; 7873 7874 u8 reserved_at_40[0x40]; 7875 }; 7876 7877 struct mlx5_ifc_destroy_flow_table_in_bits { 7878 u8 opcode[0x10]; 7879 u8 reserved_at_10[0x10]; 7880 7881 u8 reserved_at_20[0x10]; 7882 u8 op_mod[0x10]; 7883 7884 u8 other_vport[0x1]; 7885 u8 reserved_at_41[0xf]; 7886 u8 vport_number[0x10]; 7887 7888 u8 reserved_at_60[0x20]; 7889 7890 u8 table_type[0x8]; 7891 u8 reserved_at_88[0x18]; 7892 7893 u8 reserved_at_a0[0x8]; 7894 u8 table_id[0x18]; 7895 7896 u8 reserved_at_c0[0x140]; 7897 }; 7898 7899 struct mlx5_ifc_destroy_flow_group_out_bits { 7900 u8 status[0x8]; 7901 u8 reserved_at_8[0x18]; 7902 7903 u8 syndrome[0x20]; 7904 7905 u8 reserved_at_40[0x40]; 7906 }; 7907 7908 struct mlx5_ifc_destroy_flow_group_in_bits { 7909 u8 opcode[0x10]; 7910 u8 reserved_at_10[0x10]; 7911 7912 u8 reserved_at_20[0x10]; 7913 u8 op_mod[0x10]; 7914 7915 u8 other_vport[0x1]; 7916 u8 reserved_at_41[0xf]; 7917 u8 vport_number[0x10]; 7918 7919 u8 reserved_at_60[0x20]; 7920 7921 u8 table_type[0x8]; 7922 u8 reserved_at_88[0x18]; 7923 7924 u8 reserved_at_a0[0x8]; 7925 u8 table_id[0x18]; 7926 7927 u8 group_id[0x20]; 7928 7929 u8 reserved_at_e0[0x120]; 7930 }; 7931 7932 struct mlx5_ifc_destroy_eq_out_bits { 7933 u8 status[0x8]; 7934 u8 reserved_at_8[0x18]; 7935 7936 u8 syndrome[0x20]; 7937 7938 u8 reserved_at_40[0x40]; 7939 }; 7940 7941 struct mlx5_ifc_destroy_eq_in_bits { 7942 u8 opcode[0x10]; 7943 u8 reserved_at_10[0x10]; 7944 7945 u8 reserved_at_20[0x10]; 7946 u8 op_mod[0x10]; 7947 7948 u8 reserved_at_40[0x18]; 7949 u8 eq_number[0x8]; 7950 7951 u8 reserved_at_60[0x20]; 7952 }; 7953 7954 struct mlx5_ifc_destroy_dct_out_bits { 7955 u8 status[0x8]; 7956 u8 reserved_at_8[0x18]; 7957 7958 u8 syndrome[0x20]; 7959 7960 u8 reserved_at_40[0x40]; 7961 }; 7962 7963 struct mlx5_ifc_destroy_dct_in_bits { 7964 u8 opcode[0x10]; 7965 u8 uid[0x10]; 7966 7967 u8 reserved_at_20[0x10]; 7968 u8 op_mod[0x10]; 7969 7970 u8 reserved_at_40[0x8]; 7971 u8 dctn[0x18]; 7972 7973 u8 reserved_at_60[0x20]; 7974 }; 7975 7976 struct mlx5_ifc_destroy_cq_out_bits { 7977 u8 status[0x8]; 7978 u8 reserved_at_8[0x18]; 7979 7980 u8 syndrome[0x20]; 7981 7982 u8 reserved_at_40[0x40]; 7983 }; 7984 7985 struct mlx5_ifc_destroy_cq_in_bits { 7986 u8 opcode[0x10]; 7987 u8 uid[0x10]; 7988 7989 u8 reserved_at_20[0x10]; 7990 u8 op_mod[0x10]; 7991 7992 u8 reserved_at_40[0x8]; 7993 u8 cqn[0x18]; 7994 7995 u8 reserved_at_60[0x20]; 7996 }; 7997 7998 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits { 7999 u8 status[0x8]; 8000 u8 reserved_at_8[0x18]; 8001 8002 u8 syndrome[0x20]; 8003 8004 u8 reserved_at_40[0x40]; 8005 }; 8006 8007 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits { 8008 u8 opcode[0x10]; 8009 u8 reserved_at_10[0x10]; 8010 8011 u8 reserved_at_20[0x10]; 8012 u8 op_mod[0x10]; 8013 8014 u8 reserved_at_40[0x20]; 8015 8016 u8 reserved_at_60[0x10]; 8017 u8 vxlan_udp_port[0x10]; 8018 }; 8019 8020 struct mlx5_ifc_delete_l2_table_entry_out_bits { 8021 u8 status[0x8]; 8022 u8 reserved_at_8[0x18]; 8023 8024 u8 syndrome[0x20]; 8025 8026 u8 reserved_at_40[0x40]; 8027 }; 8028 8029 struct mlx5_ifc_delete_l2_table_entry_in_bits { 8030 u8 opcode[0x10]; 8031 u8 reserved_at_10[0x10]; 8032 8033 u8 reserved_at_20[0x10]; 8034 u8 op_mod[0x10]; 8035 8036 u8 reserved_at_40[0x60]; 8037 8038 u8 reserved_at_a0[0x8]; 8039 u8 table_index[0x18]; 8040 8041 u8 reserved_at_c0[0x140]; 8042 }; 8043 8044 struct mlx5_ifc_delete_fte_out_bits { 8045 u8 status[0x8]; 8046 u8 reserved_at_8[0x18]; 8047 8048 u8 syndrome[0x20]; 8049 8050 u8 reserved_at_40[0x40]; 8051 }; 8052 8053 struct mlx5_ifc_delete_fte_in_bits { 8054 u8 opcode[0x10]; 8055 u8 reserved_at_10[0x10]; 8056 8057 u8 reserved_at_20[0x10]; 8058 u8 op_mod[0x10]; 8059 8060 u8 other_vport[0x1]; 8061 u8 reserved_at_41[0xf]; 8062 u8 vport_number[0x10]; 8063 8064 u8 reserved_at_60[0x20]; 8065 8066 u8 table_type[0x8]; 8067 u8 reserved_at_88[0x18]; 8068 8069 u8 reserved_at_a0[0x8]; 8070 u8 table_id[0x18]; 8071 8072 u8 reserved_at_c0[0x40]; 8073 8074 u8 flow_index[0x20]; 8075 8076 u8 reserved_at_120[0xe0]; 8077 }; 8078 8079 struct mlx5_ifc_dealloc_xrcd_out_bits { 8080 u8 status[0x8]; 8081 u8 reserved_at_8[0x18]; 8082 8083 u8 syndrome[0x20]; 8084 8085 u8 reserved_at_40[0x40]; 8086 }; 8087 8088 struct mlx5_ifc_dealloc_xrcd_in_bits { 8089 u8 opcode[0x10]; 8090 u8 uid[0x10]; 8091 8092 u8 reserved_at_20[0x10]; 8093 u8 op_mod[0x10]; 8094 8095 u8 reserved_at_40[0x8]; 8096 u8 xrcd[0x18]; 8097 8098 u8 reserved_at_60[0x20]; 8099 }; 8100 8101 struct mlx5_ifc_dealloc_uar_out_bits { 8102 u8 status[0x8]; 8103 u8 reserved_at_8[0x18]; 8104 8105 u8 syndrome[0x20]; 8106 8107 u8 reserved_at_40[0x40]; 8108 }; 8109 8110 struct mlx5_ifc_dealloc_uar_in_bits { 8111 u8 opcode[0x10]; 8112 u8 uid[0x10]; 8113 8114 u8 reserved_at_20[0x10]; 8115 u8 op_mod[0x10]; 8116 8117 u8 reserved_at_40[0x8]; 8118 u8 uar[0x18]; 8119 8120 u8 reserved_at_60[0x20]; 8121 }; 8122 8123 struct mlx5_ifc_dealloc_transport_domain_out_bits { 8124 u8 status[0x8]; 8125 u8 reserved_at_8[0x18]; 8126 8127 u8 syndrome[0x20]; 8128 8129 u8 reserved_at_40[0x40]; 8130 }; 8131 8132 struct mlx5_ifc_dealloc_transport_domain_in_bits { 8133 u8 opcode[0x10]; 8134 u8 uid[0x10]; 8135 8136 u8 reserved_at_20[0x10]; 8137 u8 op_mod[0x10]; 8138 8139 u8 reserved_at_40[0x8]; 8140 u8 transport_domain[0x18]; 8141 8142 u8 reserved_at_60[0x20]; 8143 }; 8144 8145 struct mlx5_ifc_dealloc_q_counter_out_bits { 8146 u8 status[0x8]; 8147 u8 reserved_at_8[0x18]; 8148 8149 u8 syndrome[0x20]; 8150 8151 u8 reserved_at_40[0x40]; 8152 }; 8153 8154 struct mlx5_ifc_dealloc_q_counter_in_bits { 8155 u8 opcode[0x10]; 8156 u8 reserved_at_10[0x10]; 8157 8158 u8 reserved_at_20[0x10]; 8159 u8 op_mod[0x10]; 8160 8161 u8 reserved_at_40[0x18]; 8162 u8 counter_set_id[0x8]; 8163 8164 u8 reserved_at_60[0x20]; 8165 }; 8166 8167 struct mlx5_ifc_dealloc_pd_out_bits { 8168 u8 status[0x8]; 8169 u8 reserved_at_8[0x18]; 8170 8171 u8 syndrome[0x20]; 8172 8173 u8 reserved_at_40[0x40]; 8174 }; 8175 8176 struct mlx5_ifc_dealloc_pd_in_bits { 8177 u8 opcode[0x10]; 8178 u8 uid[0x10]; 8179 8180 u8 reserved_at_20[0x10]; 8181 u8 op_mod[0x10]; 8182 8183 u8 reserved_at_40[0x8]; 8184 u8 pd[0x18]; 8185 8186 u8 reserved_at_60[0x20]; 8187 }; 8188 8189 struct mlx5_ifc_dealloc_flow_counter_out_bits { 8190 u8 status[0x8]; 8191 u8 reserved_at_8[0x18]; 8192 8193 u8 syndrome[0x20]; 8194 8195 u8 reserved_at_40[0x40]; 8196 }; 8197 8198 struct mlx5_ifc_dealloc_flow_counter_in_bits { 8199 u8 opcode[0x10]; 8200 u8 reserved_at_10[0x10]; 8201 8202 u8 reserved_at_20[0x10]; 8203 u8 op_mod[0x10]; 8204 8205 u8 flow_counter_id[0x20]; 8206 8207 u8 reserved_at_60[0x20]; 8208 }; 8209 8210 struct mlx5_ifc_create_xrq_out_bits { 8211 u8 status[0x8]; 8212 u8 reserved_at_8[0x18]; 8213 8214 u8 syndrome[0x20]; 8215 8216 u8 reserved_at_40[0x8]; 8217 u8 xrqn[0x18]; 8218 8219 u8 reserved_at_60[0x20]; 8220 }; 8221 8222 struct mlx5_ifc_create_xrq_in_bits { 8223 u8 opcode[0x10]; 8224 u8 uid[0x10]; 8225 8226 u8 reserved_at_20[0x10]; 8227 u8 op_mod[0x10]; 8228 8229 u8 reserved_at_40[0x40]; 8230 8231 struct mlx5_ifc_xrqc_bits xrq_context; 8232 }; 8233 8234 struct mlx5_ifc_create_xrc_srq_out_bits { 8235 u8 status[0x8]; 8236 u8 reserved_at_8[0x18]; 8237 8238 u8 syndrome[0x20]; 8239 8240 u8 reserved_at_40[0x8]; 8241 u8 xrc_srqn[0x18]; 8242 8243 u8 reserved_at_60[0x20]; 8244 }; 8245 8246 struct mlx5_ifc_create_xrc_srq_in_bits { 8247 u8 opcode[0x10]; 8248 u8 uid[0x10]; 8249 8250 u8 reserved_at_20[0x10]; 8251 u8 op_mod[0x10]; 8252 8253 u8 reserved_at_40[0x40]; 8254 8255 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 8256 8257 u8 reserved_at_280[0x60]; 8258 8259 u8 xrc_srq_umem_valid[0x1]; 8260 u8 reserved_at_2e1[0x1f]; 8261 8262 u8 reserved_at_300[0x580]; 8263 8264 u8 pas[][0x40]; 8265 }; 8266 8267 struct mlx5_ifc_create_tis_out_bits { 8268 u8 status[0x8]; 8269 u8 reserved_at_8[0x18]; 8270 8271 u8 syndrome[0x20]; 8272 8273 u8 reserved_at_40[0x8]; 8274 u8 tisn[0x18]; 8275 8276 u8 reserved_at_60[0x20]; 8277 }; 8278 8279 struct mlx5_ifc_create_tis_in_bits { 8280 u8 opcode[0x10]; 8281 u8 uid[0x10]; 8282 8283 u8 reserved_at_20[0x10]; 8284 u8 op_mod[0x10]; 8285 8286 u8 reserved_at_40[0xc0]; 8287 8288 struct mlx5_ifc_tisc_bits ctx; 8289 }; 8290 8291 struct mlx5_ifc_create_tir_out_bits { 8292 u8 status[0x8]; 8293 u8 icm_address_63_40[0x18]; 8294 8295 u8 syndrome[0x20]; 8296 8297 u8 icm_address_39_32[0x8]; 8298 u8 tirn[0x18]; 8299 8300 u8 icm_address_31_0[0x20]; 8301 }; 8302 8303 struct mlx5_ifc_create_tir_in_bits { 8304 u8 opcode[0x10]; 8305 u8 uid[0x10]; 8306 8307 u8 reserved_at_20[0x10]; 8308 u8 op_mod[0x10]; 8309 8310 u8 reserved_at_40[0xc0]; 8311 8312 struct mlx5_ifc_tirc_bits ctx; 8313 }; 8314 8315 struct mlx5_ifc_create_srq_out_bits { 8316 u8 status[0x8]; 8317 u8 reserved_at_8[0x18]; 8318 8319 u8 syndrome[0x20]; 8320 8321 u8 reserved_at_40[0x8]; 8322 u8 srqn[0x18]; 8323 8324 u8 reserved_at_60[0x20]; 8325 }; 8326 8327 struct mlx5_ifc_create_srq_in_bits { 8328 u8 opcode[0x10]; 8329 u8 uid[0x10]; 8330 8331 u8 reserved_at_20[0x10]; 8332 u8 op_mod[0x10]; 8333 8334 u8 reserved_at_40[0x40]; 8335 8336 struct mlx5_ifc_srqc_bits srq_context_entry; 8337 8338 u8 reserved_at_280[0x600]; 8339 8340 u8 pas[][0x40]; 8341 }; 8342 8343 struct mlx5_ifc_create_sq_out_bits { 8344 u8 status[0x8]; 8345 u8 reserved_at_8[0x18]; 8346 8347 u8 syndrome[0x20]; 8348 8349 u8 reserved_at_40[0x8]; 8350 u8 sqn[0x18]; 8351 8352 u8 reserved_at_60[0x20]; 8353 }; 8354 8355 struct mlx5_ifc_create_sq_in_bits { 8356 u8 opcode[0x10]; 8357 u8 uid[0x10]; 8358 8359 u8 reserved_at_20[0x10]; 8360 u8 op_mod[0x10]; 8361 8362 u8 reserved_at_40[0xc0]; 8363 8364 struct mlx5_ifc_sqc_bits ctx; 8365 }; 8366 8367 struct mlx5_ifc_create_scheduling_element_out_bits { 8368 u8 status[0x8]; 8369 u8 reserved_at_8[0x18]; 8370 8371 u8 syndrome[0x20]; 8372 8373 u8 reserved_at_40[0x40]; 8374 8375 u8 scheduling_element_id[0x20]; 8376 8377 u8 reserved_at_a0[0x160]; 8378 }; 8379 8380 struct mlx5_ifc_create_scheduling_element_in_bits { 8381 u8 opcode[0x10]; 8382 u8 reserved_at_10[0x10]; 8383 8384 u8 reserved_at_20[0x10]; 8385 u8 op_mod[0x10]; 8386 8387 u8 scheduling_hierarchy[0x8]; 8388 u8 reserved_at_48[0x18]; 8389 8390 u8 reserved_at_60[0xa0]; 8391 8392 struct mlx5_ifc_scheduling_context_bits scheduling_context; 8393 8394 u8 reserved_at_300[0x100]; 8395 }; 8396 8397 struct mlx5_ifc_create_rqt_out_bits { 8398 u8 status[0x8]; 8399 u8 reserved_at_8[0x18]; 8400 8401 u8 syndrome[0x20]; 8402 8403 u8 reserved_at_40[0x8]; 8404 u8 rqtn[0x18]; 8405 8406 u8 reserved_at_60[0x20]; 8407 }; 8408 8409 struct mlx5_ifc_create_rqt_in_bits { 8410 u8 opcode[0x10]; 8411 u8 uid[0x10]; 8412 8413 u8 reserved_at_20[0x10]; 8414 u8 op_mod[0x10]; 8415 8416 u8 reserved_at_40[0xc0]; 8417 8418 struct mlx5_ifc_rqtc_bits rqt_context; 8419 }; 8420 8421 struct mlx5_ifc_create_rq_out_bits { 8422 u8 status[0x8]; 8423 u8 reserved_at_8[0x18]; 8424 8425 u8 syndrome[0x20]; 8426 8427 u8 reserved_at_40[0x8]; 8428 u8 rqn[0x18]; 8429 8430 u8 reserved_at_60[0x20]; 8431 }; 8432 8433 struct mlx5_ifc_create_rq_in_bits { 8434 u8 opcode[0x10]; 8435 u8 uid[0x10]; 8436 8437 u8 reserved_at_20[0x10]; 8438 u8 op_mod[0x10]; 8439 8440 u8 reserved_at_40[0xc0]; 8441 8442 struct mlx5_ifc_rqc_bits ctx; 8443 }; 8444 8445 struct mlx5_ifc_create_rmp_out_bits { 8446 u8 status[0x8]; 8447 u8 reserved_at_8[0x18]; 8448 8449 u8 syndrome[0x20]; 8450 8451 u8 reserved_at_40[0x8]; 8452 u8 rmpn[0x18]; 8453 8454 u8 reserved_at_60[0x20]; 8455 }; 8456 8457 struct mlx5_ifc_create_rmp_in_bits { 8458 u8 opcode[0x10]; 8459 u8 uid[0x10]; 8460 8461 u8 reserved_at_20[0x10]; 8462 u8 op_mod[0x10]; 8463 8464 u8 reserved_at_40[0xc0]; 8465 8466 struct mlx5_ifc_rmpc_bits ctx; 8467 }; 8468 8469 struct mlx5_ifc_create_qp_out_bits { 8470 u8 status[0x8]; 8471 u8 reserved_at_8[0x18]; 8472 8473 u8 syndrome[0x20]; 8474 8475 u8 reserved_at_40[0x8]; 8476 u8 qpn[0x18]; 8477 8478 u8 ece[0x20]; 8479 }; 8480 8481 struct mlx5_ifc_create_qp_in_bits { 8482 u8 opcode[0x10]; 8483 u8 uid[0x10]; 8484 8485 u8 reserved_at_20[0x10]; 8486 u8 op_mod[0x10]; 8487 8488 u8 reserved_at_40[0x8]; 8489 u8 input_qpn[0x18]; 8490 8491 u8 reserved_at_60[0x20]; 8492 u8 opt_param_mask[0x20]; 8493 8494 u8 ece[0x20]; 8495 8496 struct mlx5_ifc_qpc_bits qpc; 8497 8498 u8 reserved_at_800[0x60]; 8499 8500 u8 wq_umem_valid[0x1]; 8501 u8 reserved_at_861[0x1f]; 8502 8503 u8 pas[][0x40]; 8504 }; 8505 8506 struct mlx5_ifc_create_psv_out_bits { 8507 u8 status[0x8]; 8508 u8 reserved_at_8[0x18]; 8509 8510 u8 syndrome[0x20]; 8511 8512 u8 reserved_at_40[0x40]; 8513 8514 u8 reserved_at_80[0x8]; 8515 u8 psv0_index[0x18]; 8516 8517 u8 reserved_at_a0[0x8]; 8518 u8 psv1_index[0x18]; 8519 8520 u8 reserved_at_c0[0x8]; 8521 u8 psv2_index[0x18]; 8522 8523 u8 reserved_at_e0[0x8]; 8524 u8 psv3_index[0x18]; 8525 }; 8526 8527 struct mlx5_ifc_create_psv_in_bits { 8528 u8 opcode[0x10]; 8529 u8 reserved_at_10[0x10]; 8530 8531 u8 reserved_at_20[0x10]; 8532 u8 op_mod[0x10]; 8533 8534 u8 num_psv[0x4]; 8535 u8 reserved_at_44[0x4]; 8536 u8 pd[0x18]; 8537 8538 u8 reserved_at_60[0x20]; 8539 }; 8540 8541 struct mlx5_ifc_create_mkey_out_bits { 8542 u8 status[0x8]; 8543 u8 reserved_at_8[0x18]; 8544 8545 u8 syndrome[0x20]; 8546 8547 u8 reserved_at_40[0x8]; 8548 u8 mkey_index[0x18]; 8549 8550 u8 reserved_at_60[0x20]; 8551 }; 8552 8553 struct mlx5_ifc_create_mkey_in_bits { 8554 u8 opcode[0x10]; 8555 u8 uid[0x10]; 8556 8557 u8 reserved_at_20[0x10]; 8558 u8 op_mod[0x10]; 8559 8560 u8 reserved_at_40[0x20]; 8561 8562 u8 pg_access[0x1]; 8563 u8 mkey_umem_valid[0x1]; 8564 u8 reserved_at_62[0x1e]; 8565 8566 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 8567 8568 u8 reserved_at_280[0x80]; 8569 8570 u8 translations_octword_actual_size[0x20]; 8571 8572 u8 reserved_at_320[0x560]; 8573 8574 u8 klm_pas_mtt[][0x20]; 8575 }; 8576 8577 enum { 8578 MLX5_FLOW_TABLE_TYPE_NIC_RX = 0x0, 8579 MLX5_FLOW_TABLE_TYPE_NIC_TX = 0x1, 8580 MLX5_FLOW_TABLE_TYPE_ESW_EGRESS_ACL = 0x2, 8581 MLX5_FLOW_TABLE_TYPE_ESW_INGRESS_ACL = 0x3, 8582 MLX5_FLOW_TABLE_TYPE_FDB = 0X4, 8583 MLX5_FLOW_TABLE_TYPE_SNIFFER_RX = 0X5, 8584 MLX5_FLOW_TABLE_TYPE_SNIFFER_TX = 0X6, 8585 }; 8586 8587 struct mlx5_ifc_create_flow_table_out_bits { 8588 u8 status[0x8]; 8589 u8 icm_address_63_40[0x18]; 8590 8591 u8 syndrome[0x20]; 8592 8593 u8 icm_address_39_32[0x8]; 8594 u8 table_id[0x18]; 8595 8596 u8 icm_address_31_0[0x20]; 8597 }; 8598 8599 struct mlx5_ifc_create_flow_table_in_bits { 8600 u8 opcode[0x10]; 8601 u8 uid[0x10]; 8602 8603 u8 reserved_at_20[0x10]; 8604 u8 op_mod[0x10]; 8605 8606 u8 other_vport[0x1]; 8607 u8 reserved_at_41[0xf]; 8608 u8 vport_number[0x10]; 8609 8610 u8 reserved_at_60[0x20]; 8611 8612 u8 table_type[0x8]; 8613 u8 reserved_at_88[0x18]; 8614 8615 u8 reserved_at_a0[0x20]; 8616 8617 struct mlx5_ifc_flow_table_context_bits flow_table_context; 8618 }; 8619 8620 struct mlx5_ifc_create_flow_group_out_bits { 8621 u8 status[0x8]; 8622 u8 reserved_at_8[0x18]; 8623 8624 u8 syndrome[0x20]; 8625 8626 u8 reserved_at_40[0x8]; 8627 u8 group_id[0x18]; 8628 8629 u8 reserved_at_60[0x20]; 8630 }; 8631 8632 enum { 8633 MLX5_CREATE_FLOW_GROUP_IN_GROUP_TYPE_TCAM_SUBTABLE = 0x0, 8634 MLX5_CREATE_FLOW_GROUP_IN_GROUP_TYPE_HASH_SPLIT = 0x1, 8635 }; 8636 8637 enum { 8638 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 8639 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 8640 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 8641 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3, 8642 }; 8643 8644 struct mlx5_ifc_create_flow_group_in_bits { 8645 u8 opcode[0x10]; 8646 u8 reserved_at_10[0x10]; 8647 8648 u8 reserved_at_20[0x10]; 8649 u8 op_mod[0x10]; 8650 8651 u8 other_vport[0x1]; 8652 u8 reserved_at_41[0xf]; 8653 u8 vport_number[0x10]; 8654 8655 u8 reserved_at_60[0x20]; 8656 8657 u8 table_type[0x8]; 8658 u8 reserved_at_88[0x4]; 8659 u8 group_type[0x4]; 8660 u8 reserved_at_90[0x10]; 8661 8662 u8 reserved_at_a0[0x8]; 8663 u8 table_id[0x18]; 8664 8665 u8 source_eswitch_owner_vhca_id_valid[0x1]; 8666 8667 u8 reserved_at_c1[0x1f]; 8668 8669 u8 start_flow_index[0x20]; 8670 8671 u8 reserved_at_100[0x20]; 8672 8673 u8 end_flow_index[0x20]; 8674 8675 u8 reserved_at_140[0x10]; 8676 u8 match_definer_id[0x10]; 8677 8678 u8 reserved_at_160[0x80]; 8679 8680 u8 reserved_at_1e0[0x18]; 8681 u8 match_criteria_enable[0x8]; 8682 8683 struct mlx5_ifc_fte_match_param_bits match_criteria; 8684 8685 u8 reserved_at_1200[0xe00]; 8686 }; 8687 8688 struct mlx5_ifc_create_eq_out_bits { 8689 u8 status[0x8]; 8690 u8 reserved_at_8[0x18]; 8691 8692 u8 syndrome[0x20]; 8693 8694 u8 reserved_at_40[0x18]; 8695 u8 eq_number[0x8]; 8696 8697 u8 reserved_at_60[0x20]; 8698 }; 8699 8700 struct mlx5_ifc_create_eq_in_bits { 8701 u8 opcode[0x10]; 8702 u8 uid[0x10]; 8703 8704 u8 reserved_at_20[0x10]; 8705 u8 op_mod[0x10]; 8706 8707 u8 reserved_at_40[0x40]; 8708 8709 struct mlx5_ifc_eqc_bits eq_context_entry; 8710 8711 u8 reserved_at_280[0x40]; 8712 8713 u8 event_bitmask[4][0x40]; 8714 8715 u8 reserved_at_3c0[0x4c0]; 8716 8717 u8 pas[][0x40]; 8718 }; 8719 8720 struct mlx5_ifc_create_dct_out_bits { 8721 u8 status[0x8]; 8722 u8 reserved_at_8[0x18]; 8723 8724 u8 syndrome[0x20]; 8725 8726 u8 reserved_at_40[0x8]; 8727 u8 dctn[0x18]; 8728 8729 u8 ece[0x20]; 8730 }; 8731 8732 struct mlx5_ifc_create_dct_in_bits { 8733 u8 opcode[0x10]; 8734 u8 uid[0x10]; 8735 8736 u8 reserved_at_20[0x10]; 8737 u8 op_mod[0x10]; 8738 8739 u8 reserved_at_40[0x40]; 8740 8741 struct mlx5_ifc_dctc_bits dct_context_entry; 8742 8743 u8 reserved_at_280[0x180]; 8744 }; 8745 8746 struct mlx5_ifc_create_cq_out_bits { 8747 u8 status[0x8]; 8748 u8 reserved_at_8[0x18]; 8749 8750 u8 syndrome[0x20]; 8751 8752 u8 reserved_at_40[0x8]; 8753 u8 cqn[0x18]; 8754 8755 u8 reserved_at_60[0x20]; 8756 }; 8757 8758 struct mlx5_ifc_create_cq_in_bits { 8759 u8 opcode[0x10]; 8760 u8 uid[0x10]; 8761 8762 u8 reserved_at_20[0x10]; 8763 u8 op_mod[0x10]; 8764 8765 u8 reserved_at_40[0x40]; 8766 8767 struct mlx5_ifc_cqc_bits cq_context; 8768 8769 u8 reserved_at_280[0x60]; 8770 8771 u8 cq_umem_valid[0x1]; 8772 u8 reserved_at_2e1[0x59f]; 8773 8774 u8 pas[][0x40]; 8775 }; 8776 8777 struct mlx5_ifc_config_int_moderation_out_bits { 8778 u8 status[0x8]; 8779 u8 reserved_at_8[0x18]; 8780 8781 u8 syndrome[0x20]; 8782 8783 u8 reserved_at_40[0x4]; 8784 u8 min_delay[0xc]; 8785 u8 int_vector[0x10]; 8786 8787 u8 reserved_at_60[0x20]; 8788 }; 8789 8790 enum { 8791 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0, 8792 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1, 8793 }; 8794 8795 struct mlx5_ifc_config_int_moderation_in_bits { 8796 u8 opcode[0x10]; 8797 u8 reserved_at_10[0x10]; 8798 8799 u8 reserved_at_20[0x10]; 8800 u8 op_mod[0x10]; 8801 8802 u8 reserved_at_40[0x4]; 8803 u8 min_delay[0xc]; 8804 u8 int_vector[0x10]; 8805 8806 u8 reserved_at_60[0x20]; 8807 }; 8808 8809 struct mlx5_ifc_attach_to_mcg_out_bits { 8810 u8 status[0x8]; 8811 u8 reserved_at_8[0x18]; 8812 8813 u8 syndrome[0x20]; 8814 8815 u8 reserved_at_40[0x40]; 8816 }; 8817 8818 struct mlx5_ifc_attach_to_mcg_in_bits { 8819 u8 opcode[0x10]; 8820 u8 uid[0x10]; 8821 8822 u8 reserved_at_20[0x10]; 8823 u8 op_mod[0x10]; 8824 8825 u8 reserved_at_40[0x8]; 8826 u8 qpn[0x18]; 8827 8828 u8 reserved_at_60[0x20]; 8829 8830 u8 multicast_gid[16][0x8]; 8831 }; 8832 8833 struct mlx5_ifc_arm_xrq_out_bits { 8834 u8 status[0x8]; 8835 u8 reserved_at_8[0x18]; 8836 8837 u8 syndrome[0x20]; 8838 8839 u8 reserved_at_40[0x40]; 8840 }; 8841 8842 struct mlx5_ifc_arm_xrq_in_bits { 8843 u8 opcode[0x10]; 8844 u8 reserved_at_10[0x10]; 8845 8846 u8 reserved_at_20[0x10]; 8847 u8 op_mod[0x10]; 8848 8849 u8 reserved_at_40[0x8]; 8850 u8 xrqn[0x18]; 8851 8852 u8 reserved_at_60[0x10]; 8853 u8 lwm[0x10]; 8854 }; 8855 8856 struct mlx5_ifc_arm_xrc_srq_out_bits { 8857 u8 status[0x8]; 8858 u8 reserved_at_8[0x18]; 8859 8860 u8 syndrome[0x20]; 8861 8862 u8 reserved_at_40[0x40]; 8863 }; 8864 8865 enum { 8866 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1, 8867 }; 8868 8869 struct mlx5_ifc_arm_xrc_srq_in_bits { 8870 u8 opcode[0x10]; 8871 u8 uid[0x10]; 8872 8873 u8 reserved_at_20[0x10]; 8874 u8 op_mod[0x10]; 8875 8876 u8 reserved_at_40[0x8]; 8877 u8 xrc_srqn[0x18]; 8878 8879 u8 reserved_at_60[0x10]; 8880 u8 lwm[0x10]; 8881 }; 8882 8883 struct mlx5_ifc_arm_rq_out_bits { 8884 u8 status[0x8]; 8885 u8 reserved_at_8[0x18]; 8886 8887 u8 syndrome[0x20]; 8888 8889 u8 reserved_at_40[0x40]; 8890 }; 8891 8892 enum { 8893 MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1, 8894 MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2, 8895 }; 8896 8897 struct mlx5_ifc_arm_rq_in_bits { 8898 u8 opcode[0x10]; 8899 u8 uid[0x10]; 8900 8901 u8 reserved_at_20[0x10]; 8902 u8 op_mod[0x10]; 8903 8904 u8 reserved_at_40[0x8]; 8905 u8 srq_number[0x18]; 8906 8907 u8 reserved_at_60[0x10]; 8908 u8 lwm[0x10]; 8909 }; 8910 8911 struct mlx5_ifc_arm_dct_out_bits { 8912 u8 status[0x8]; 8913 u8 reserved_at_8[0x18]; 8914 8915 u8 syndrome[0x20]; 8916 8917 u8 reserved_at_40[0x40]; 8918 }; 8919 8920 struct mlx5_ifc_arm_dct_in_bits { 8921 u8 opcode[0x10]; 8922 u8 reserved_at_10[0x10]; 8923 8924 u8 reserved_at_20[0x10]; 8925 u8 op_mod[0x10]; 8926 8927 u8 reserved_at_40[0x8]; 8928 u8 dct_number[0x18]; 8929 8930 u8 reserved_at_60[0x20]; 8931 }; 8932 8933 struct mlx5_ifc_alloc_xrcd_out_bits { 8934 u8 status[0x8]; 8935 u8 reserved_at_8[0x18]; 8936 8937 u8 syndrome[0x20]; 8938 8939 u8 reserved_at_40[0x8]; 8940 u8 xrcd[0x18]; 8941 8942 u8 reserved_at_60[0x20]; 8943 }; 8944 8945 struct mlx5_ifc_alloc_xrcd_in_bits { 8946 u8 opcode[0x10]; 8947 u8 uid[0x10]; 8948 8949 u8 reserved_at_20[0x10]; 8950 u8 op_mod[0x10]; 8951 8952 u8 reserved_at_40[0x40]; 8953 }; 8954 8955 struct mlx5_ifc_alloc_uar_out_bits { 8956 u8 status[0x8]; 8957 u8 reserved_at_8[0x18]; 8958 8959 u8 syndrome[0x20]; 8960 8961 u8 reserved_at_40[0x8]; 8962 u8 uar[0x18]; 8963 8964 u8 reserved_at_60[0x20]; 8965 }; 8966 8967 struct mlx5_ifc_alloc_uar_in_bits { 8968 u8 opcode[0x10]; 8969 u8 uid[0x10]; 8970 8971 u8 reserved_at_20[0x10]; 8972 u8 op_mod[0x10]; 8973 8974 u8 reserved_at_40[0x40]; 8975 }; 8976 8977 struct mlx5_ifc_alloc_transport_domain_out_bits { 8978 u8 status[0x8]; 8979 u8 reserved_at_8[0x18]; 8980 8981 u8 syndrome[0x20]; 8982 8983 u8 reserved_at_40[0x8]; 8984 u8 transport_domain[0x18]; 8985 8986 u8 reserved_at_60[0x20]; 8987 }; 8988 8989 struct mlx5_ifc_alloc_transport_domain_in_bits { 8990 u8 opcode[0x10]; 8991 u8 uid[0x10]; 8992 8993 u8 reserved_at_20[0x10]; 8994 u8 op_mod[0x10]; 8995 8996 u8 reserved_at_40[0x40]; 8997 }; 8998 8999 struct mlx5_ifc_alloc_q_counter_out_bits { 9000 u8 status[0x8]; 9001 u8 reserved_at_8[0x18]; 9002 9003 u8 syndrome[0x20]; 9004 9005 u8 reserved_at_40[0x18]; 9006 u8 counter_set_id[0x8]; 9007 9008 u8 reserved_at_60[0x20]; 9009 }; 9010 9011 struct mlx5_ifc_alloc_q_counter_in_bits { 9012 u8 opcode[0x10]; 9013 u8 uid[0x10]; 9014 9015 u8 reserved_at_20[0x10]; 9016 u8 op_mod[0x10]; 9017 9018 u8 reserved_at_40[0x40]; 9019 }; 9020 9021 struct mlx5_ifc_alloc_pd_out_bits { 9022 u8 status[0x8]; 9023 u8 reserved_at_8[0x18]; 9024 9025 u8 syndrome[0x20]; 9026 9027 u8 reserved_at_40[0x8]; 9028 u8 pd[0x18]; 9029 9030 u8 reserved_at_60[0x20]; 9031 }; 9032 9033 struct mlx5_ifc_alloc_pd_in_bits { 9034 u8 opcode[0x10]; 9035 u8 uid[0x10]; 9036 9037 u8 reserved_at_20[0x10]; 9038 u8 op_mod[0x10]; 9039 9040 u8 reserved_at_40[0x40]; 9041 }; 9042 9043 struct mlx5_ifc_alloc_flow_counter_out_bits { 9044 u8 status[0x8]; 9045 u8 reserved_at_8[0x18]; 9046 9047 u8 syndrome[0x20]; 9048 9049 u8 flow_counter_id[0x20]; 9050 9051 u8 reserved_at_60[0x20]; 9052 }; 9053 9054 struct mlx5_ifc_alloc_flow_counter_in_bits { 9055 u8 opcode[0x10]; 9056 u8 reserved_at_10[0x10]; 9057 9058 u8 reserved_at_20[0x10]; 9059 u8 op_mod[0x10]; 9060 9061 u8 reserved_at_40[0x38]; 9062 u8 flow_counter_bulk[0x8]; 9063 }; 9064 9065 struct mlx5_ifc_add_vxlan_udp_dport_out_bits { 9066 u8 status[0x8]; 9067 u8 reserved_at_8[0x18]; 9068 9069 u8 syndrome[0x20]; 9070 9071 u8 reserved_at_40[0x40]; 9072 }; 9073 9074 struct mlx5_ifc_add_vxlan_udp_dport_in_bits { 9075 u8 opcode[0x10]; 9076 u8 reserved_at_10[0x10]; 9077 9078 u8 reserved_at_20[0x10]; 9079 u8 op_mod[0x10]; 9080 9081 u8 reserved_at_40[0x20]; 9082 9083 u8 reserved_at_60[0x10]; 9084 u8 vxlan_udp_port[0x10]; 9085 }; 9086 9087 struct mlx5_ifc_set_pp_rate_limit_out_bits { 9088 u8 status[0x8]; 9089 u8 reserved_at_8[0x18]; 9090 9091 u8 syndrome[0x20]; 9092 9093 u8 reserved_at_40[0x40]; 9094 }; 9095 9096 struct mlx5_ifc_set_pp_rate_limit_context_bits { 9097 u8 rate_limit[0x20]; 9098 9099 u8 burst_upper_bound[0x20]; 9100 9101 u8 reserved_at_40[0x10]; 9102 u8 typical_packet_size[0x10]; 9103 9104 u8 reserved_at_60[0x120]; 9105 }; 9106 9107 struct mlx5_ifc_set_pp_rate_limit_in_bits { 9108 u8 opcode[0x10]; 9109 u8 uid[0x10]; 9110 9111 u8 reserved_at_20[0x10]; 9112 u8 op_mod[0x10]; 9113 9114 u8 reserved_at_40[0x10]; 9115 u8 rate_limit_index[0x10]; 9116 9117 u8 reserved_at_60[0x20]; 9118 9119 struct mlx5_ifc_set_pp_rate_limit_context_bits ctx; 9120 }; 9121 9122 struct mlx5_ifc_access_register_out_bits { 9123 u8 status[0x8]; 9124 u8 reserved_at_8[0x18]; 9125 9126 u8 syndrome[0x20]; 9127 9128 u8 reserved_at_40[0x40]; 9129 9130 u8 register_data[][0x20]; 9131 }; 9132 9133 enum { 9134 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0, 9135 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1, 9136 }; 9137 9138 struct mlx5_ifc_access_register_in_bits { 9139 u8 opcode[0x10]; 9140 u8 reserved_at_10[0x10]; 9141 9142 u8 reserved_at_20[0x10]; 9143 u8 op_mod[0x10]; 9144 9145 u8 reserved_at_40[0x10]; 9146 u8 register_id[0x10]; 9147 9148 u8 argument[0x20]; 9149 9150 u8 register_data[][0x20]; 9151 }; 9152 9153 struct mlx5_ifc_sltp_reg_bits { 9154 u8 status[0x4]; 9155 u8 version[0x4]; 9156 u8 local_port[0x8]; 9157 u8 pnat[0x2]; 9158 u8 reserved_at_12[0x2]; 9159 u8 lane[0x4]; 9160 u8 reserved_at_18[0x8]; 9161 9162 u8 reserved_at_20[0x20]; 9163 9164 u8 reserved_at_40[0x7]; 9165 u8 polarity[0x1]; 9166 u8 ob_tap0[0x8]; 9167 u8 ob_tap1[0x8]; 9168 u8 ob_tap2[0x8]; 9169 9170 u8 reserved_at_60[0xc]; 9171 u8 ob_preemp_mode[0x4]; 9172 u8 ob_reg[0x8]; 9173 u8 ob_bias[0x8]; 9174 9175 u8 reserved_at_80[0x20]; 9176 }; 9177 9178 struct mlx5_ifc_slrg_reg_bits { 9179 u8 status[0x4]; 9180 u8 version[0x4]; 9181 u8 local_port[0x8]; 9182 u8 pnat[0x2]; 9183 u8 reserved_at_12[0x2]; 9184 u8 lane[0x4]; 9185 u8 reserved_at_18[0x8]; 9186 9187 u8 time_to_link_up[0x10]; 9188 u8 reserved_at_30[0xc]; 9189 u8 grade_lane_speed[0x4]; 9190 9191 u8 grade_version[0x8]; 9192 u8 grade[0x18]; 9193 9194 u8 reserved_at_60[0x4]; 9195 u8 height_grade_type[0x4]; 9196 u8 height_grade[0x18]; 9197 9198 u8 height_dz[0x10]; 9199 u8 height_dv[0x10]; 9200 9201 u8 reserved_at_a0[0x10]; 9202 u8 height_sigma[0x10]; 9203 9204 u8 reserved_at_c0[0x20]; 9205 9206 u8 reserved_at_e0[0x4]; 9207 u8 phase_grade_type[0x4]; 9208 u8 phase_grade[0x18]; 9209 9210 u8 reserved_at_100[0x8]; 9211 u8 phase_eo_pos[0x8]; 9212 u8 reserved_at_110[0x8]; 9213 u8 phase_eo_neg[0x8]; 9214 9215 u8 ffe_set_tested[0x10]; 9216 u8 test_errors_per_lane[0x10]; 9217 }; 9218 9219 struct mlx5_ifc_pvlc_reg_bits { 9220 u8 reserved_at_0[0x8]; 9221 u8 local_port[0x8]; 9222 u8 reserved_at_10[0x10]; 9223 9224 u8 reserved_at_20[0x1c]; 9225 u8 vl_hw_cap[0x4]; 9226 9227 u8 reserved_at_40[0x1c]; 9228 u8 vl_admin[0x4]; 9229 9230 u8 reserved_at_60[0x1c]; 9231 u8 vl_operational[0x4]; 9232 }; 9233 9234 struct mlx5_ifc_pude_reg_bits { 9235 u8 swid[0x8]; 9236 u8 local_port[0x8]; 9237 u8 reserved_at_10[0x4]; 9238 u8 admin_status[0x4]; 9239 u8 reserved_at_18[0x4]; 9240 u8 oper_status[0x4]; 9241 9242 u8 reserved_at_20[0x60]; 9243 }; 9244 9245 struct mlx5_ifc_ptys_reg_bits { 9246 u8 reserved_at_0[0x1]; 9247 u8 an_disable_admin[0x1]; 9248 u8 an_disable_cap[0x1]; 9249 u8 reserved_at_3[0x5]; 9250 u8 local_port[0x8]; 9251 u8 reserved_at_10[0xd]; 9252 u8 proto_mask[0x3]; 9253 9254 u8 an_status[0x4]; 9255 u8 reserved_at_24[0xc]; 9256 u8 data_rate_oper[0x10]; 9257 9258 u8 ext_eth_proto_capability[0x20]; 9259 9260 u8 eth_proto_capability[0x20]; 9261 9262 u8 ib_link_width_capability[0x10]; 9263 u8 ib_proto_capability[0x10]; 9264 9265 u8 ext_eth_proto_admin[0x20]; 9266 9267 u8 eth_proto_admin[0x20]; 9268 9269 u8 ib_link_width_admin[0x10]; 9270 u8 ib_proto_admin[0x10]; 9271 9272 u8 ext_eth_proto_oper[0x20]; 9273 9274 u8 eth_proto_oper[0x20]; 9275 9276 u8 ib_link_width_oper[0x10]; 9277 u8 ib_proto_oper[0x10]; 9278 9279 u8 reserved_at_160[0x1c]; 9280 u8 connector_type[0x4]; 9281 9282 u8 eth_proto_lp_advertise[0x20]; 9283 9284 u8 reserved_at_1a0[0x60]; 9285 }; 9286 9287 struct mlx5_ifc_mlcr_reg_bits { 9288 u8 reserved_at_0[0x8]; 9289 u8 local_port[0x8]; 9290 u8 reserved_at_10[0x20]; 9291 9292 u8 beacon_duration[0x10]; 9293 u8 reserved_at_40[0x10]; 9294 9295 u8 beacon_remain[0x10]; 9296 }; 9297 9298 struct mlx5_ifc_ptas_reg_bits { 9299 u8 reserved_at_0[0x20]; 9300 9301 u8 algorithm_options[0x10]; 9302 u8 reserved_at_30[0x4]; 9303 u8 repetitions_mode[0x4]; 9304 u8 num_of_repetitions[0x8]; 9305 9306 u8 grade_version[0x8]; 9307 u8 height_grade_type[0x4]; 9308 u8 phase_grade_type[0x4]; 9309 u8 height_grade_weight[0x8]; 9310 u8 phase_grade_weight[0x8]; 9311 9312 u8 gisim_measure_bits[0x10]; 9313 u8 adaptive_tap_measure_bits[0x10]; 9314 9315 u8 ber_bath_high_error_threshold[0x10]; 9316 u8 ber_bath_mid_error_threshold[0x10]; 9317 9318 u8 ber_bath_low_error_threshold[0x10]; 9319 u8 one_ratio_high_threshold[0x10]; 9320 9321 u8 one_ratio_high_mid_threshold[0x10]; 9322 u8 one_ratio_low_mid_threshold[0x10]; 9323 9324 u8 one_ratio_low_threshold[0x10]; 9325 u8 ndeo_error_threshold[0x10]; 9326 9327 u8 mixer_offset_step_size[0x10]; 9328 u8 reserved_at_110[0x8]; 9329 u8 mix90_phase_for_voltage_bath[0x8]; 9330 9331 u8 mixer_offset_start[0x10]; 9332 u8 mixer_offset_end[0x10]; 9333 9334 u8 reserved_at_140[0x15]; 9335 u8 ber_test_time[0xb]; 9336 }; 9337 9338 struct mlx5_ifc_pspa_reg_bits { 9339 u8 swid[0x8]; 9340 u8 local_port[0x8]; 9341 u8 sub_port[0x8]; 9342 u8 reserved_at_18[0x8]; 9343 9344 u8 reserved_at_20[0x20]; 9345 }; 9346 9347 struct mlx5_ifc_pqdr_reg_bits { 9348 u8 reserved_at_0[0x8]; 9349 u8 local_port[0x8]; 9350 u8 reserved_at_10[0x5]; 9351 u8 prio[0x3]; 9352 u8 reserved_at_18[0x6]; 9353 u8 mode[0x2]; 9354 9355 u8 reserved_at_20[0x20]; 9356 9357 u8 reserved_at_40[0x10]; 9358 u8 min_threshold[0x10]; 9359 9360 u8 reserved_at_60[0x10]; 9361 u8 max_threshold[0x10]; 9362 9363 u8 reserved_at_80[0x10]; 9364 u8 mark_probability_denominator[0x10]; 9365 9366 u8 reserved_at_a0[0x60]; 9367 }; 9368 9369 struct mlx5_ifc_ppsc_reg_bits { 9370 u8 reserved_at_0[0x8]; 9371 u8 local_port[0x8]; 9372 u8 reserved_at_10[0x10]; 9373 9374 u8 reserved_at_20[0x60]; 9375 9376 u8 reserved_at_80[0x1c]; 9377 u8 wrps_admin[0x4]; 9378 9379 u8 reserved_at_a0[0x1c]; 9380 u8 wrps_status[0x4]; 9381 9382 u8 reserved_at_c0[0x8]; 9383 u8 up_threshold[0x8]; 9384 u8 reserved_at_d0[0x8]; 9385 u8 down_threshold[0x8]; 9386 9387 u8 reserved_at_e0[0x20]; 9388 9389 u8 reserved_at_100[0x1c]; 9390 u8 srps_admin[0x4]; 9391 9392 u8 reserved_at_120[0x1c]; 9393 u8 srps_status[0x4]; 9394 9395 u8 reserved_at_140[0x40]; 9396 }; 9397 9398 struct mlx5_ifc_pplr_reg_bits { 9399 u8 reserved_at_0[0x8]; 9400 u8 local_port[0x8]; 9401 u8 reserved_at_10[0x10]; 9402 9403 u8 reserved_at_20[0x8]; 9404 u8 lb_cap[0x8]; 9405 u8 reserved_at_30[0x8]; 9406 u8 lb_en[0x8]; 9407 }; 9408 9409 struct mlx5_ifc_pplm_reg_bits { 9410 u8 reserved_at_0[0x8]; 9411 u8 local_port[0x8]; 9412 u8 reserved_at_10[0x10]; 9413 9414 u8 reserved_at_20[0x20]; 9415 9416 u8 port_profile_mode[0x8]; 9417 u8 static_port_profile[0x8]; 9418 u8 active_port_profile[0x8]; 9419 u8 reserved_at_58[0x8]; 9420 9421 u8 retransmission_active[0x8]; 9422 u8 fec_mode_active[0x18]; 9423 9424 u8 rs_fec_correction_bypass_cap[0x4]; 9425 u8 reserved_at_84[0x8]; 9426 u8 fec_override_cap_56g[0x4]; 9427 u8 fec_override_cap_100g[0x4]; 9428 u8 fec_override_cap_50g[0x4]; 9429 u8 fec_override_cap_25g[0x4]; 9430 u8 fec_override_cap_10g_40g[0x4]; 9431 9432 u8 rs_fec_correction_bypass_admin[0x4]; 9433 u8 reserved_at_a4[0x8]; 9434 u8 fec_override_admin_56g[0x4]; 9435 u8 fec_override_admin_100g[0x4]; 9436 u8 fec_override_admin_50g[0x4]; 9437 u8 fec_override_admin_25g[0x4]; 9438 u8 fec_override_admin_10g_40g[0x4]; 9439 9440 u8 fec_override_cap_400g_8x[0x10]; 9441 u8 fec_override_cap_200g_4x[0x10]; 9442 9443 u8 fec_override_cap_100g_2x[0x10]; 9444 u8 fec_override_cap_50g_1x[0x10]; 9445 9446 u8 fec_override_admin_400g_8x[0x10]; 9447 u8 fec_override_admin_200g_4x[0x10]; 9448 9449 u8 fec_override_admin_100g_2x[0x10]; 9450 u8 fec_override_admin_50g_1x[0x10]; 9451 9452 u8 reserved_at_140[0x140]; 9453 }; 9454 9455 struct mlx5_ifc_ppcnt_reg_bits { 9456 u8 swid[0x8]; 9457 u8 local_port[0x8]; 9458 u8 pnat[0x2]; 9459 u8 reserved_at_12[0x8]; 9460 u8 grp[0x6]; 9461 9462 u8 clr[0x1]; 9463 u8 reserved_at_21[0x1c]; 9464 u8 prio_tc[0x3]; 9465 9466 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set; 9467 }; 9468 9469 struct mlx5_ifc_mpein_reg_bits { 9470 u8 reserved_at_0[0x2]; 9471 u8 depth[0x6]; 9472 u8 pcie_index[0x8]; 9473 u8 node[0x8]; 9474 u8 reserved_at_18[0x8]; 9475 9476 u8 capability_mask[0x20]; 9477 9478 u8 reserved_at_40[0x8]; 9479 u8 link_width_enabled[0x8]; 9480 u8 link_speed_enabled[0x10]; 9481 9482 u8 lane0_physical_position[0x8]; 9483 u8 link_width_active[0x8]; 9484 u8 link_speed_active[0x10]; 9485 9486 u8 num_of_pfs[0x10]; 9487 u8 num_of_vfs[0x10]; 9488 9489 u8 bdf0[0x10]; 9490 u8 reserved_at_b0[0x10]; 9491 9492 u8 max_read_request_size[0x4]; 9493 u8 max_payload_size[0x4]; 9494 u8 reserved_at_c8[0x5]; 9495 u8 pwr_status[0x3]; 9496 u8 port_type[0x4]; 9497 u8 reserved_at_d4[0xb]; 9498 u8 lane_reversal[0x1]; 9499 9500 u8 reserved_at_e0[0x14]; 9501 u8 pci_power[0xc]; 9502 9503 u8 reserved_at_100[0x20]; 9504 9505 u8 device_status[0x10]; 9506 u8 port_state[0x8]; 9507 u8 reserved_at_138[0x8]; 9508 9509 u8 reserved_at_140[0x10]; 9510 u8 receiver_detect_result[0x10]; 9511 9512 u8 reserved_at_160[0x20]; 9513 }; 9514 9515 struct mlx5_ifc_mpcnt_reg_bits { 9516 u8 reserved_at_0[0x8]; 9517 u8 pcie_index[0x8]; 9518 u8 reserved_at_10[0xa]; 9519 u8 grp[0x6]; 9520 9521 u8 clr[0x1]; 9522 u8 reserved_at_21[0x1f]; 9523 9524 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set; 9525 }; 9526 9527 struct mlx5_ifc_ppad_reg_bits { 9528 u8 reserved_at_0[0x3]; 9529 u8 single_mac[0x1]; 9530 u8 reserved_at_4[0x4]; 9531 u8 local_port[0x8]; 9532 u8 mac_47_32[0x10]; 9533 9534 u8 mac_31_0[0x20]; 9535 9536 u8 reserved_at_40[0x40]; 9537 }; 9538 9539 struct mlx5_ifc_pmtu_reg_bits { 9540 u8 reserved_at_0[0x8]; 9541 u8 local_port[0x8]; 9542 u8 reserved_at_10[0x10]; 9543 9544 u8 max_mtu[0x10]; 9545 u8 reserved_at_30[0x10]; 9546 9547 u8 admin_mtu[0x10]; 9548 u8 reserved_at_50[0x10]; 9549 9550 u8 oper_mtu[0x10]; 9551 u8 reserved_at_70[0x10]; 9552 }; 9553 9554 struct mlx5_ifc_pmpr_reg_bits { 9555 u8 reserved_at_0[0x8]; 9556 u8 module[0x8]; 9557 u8 reserved_at_10[0x10]; 9558 9559 u8 reserved_at_20[0x18]; 9560 u8 attenuation_5g[0x8]; 9561 9562 u8 reserved_at_40[0x18]; 9563 u8 attenuation_7g[0x8]; 9564 9565 u8 reserved_at_60[0x18]; 9566 u8 attenuation_12g[0x8]; 9567 }; 9568 9569 struct mlx5_ifc_pmpe_reg_bits { 9570 u8 reserved_at_0[0x8]; 9571 u8 module[0x8]; 9572 u8 reserved_at_10[0xc]; 9573 u8 module_status[0x4]; 9574 9575 u8 reserved_at_20[0x60]; 9576 }; 9577 9578 struct mlx5_ifc_pmpc_reg_bits { 9579 u8 module_state_updated[32][0x8]; 9580 }; 9581 9582 struct mlx5_ifc_pmlpn_reg_bits { 9583 u8 reserved_at_0[0x4]; 9584 u8 mlpn_status[0x4]; 9585 u8 local_port[0x8]; 9586 u8 reserved_at_10[0x10]; 9587 9588 u8 e[0x1]; 9589 u8 reserved_at_21[0x1f]; 9590 }; 9591 9592 struct mlx5_ifc_pmlp_reg_bits { 9593 u8 rxtx[0x1]; 9594 u8 reserved_at_1[0x7]; 9595 u8 local_port[0x8]; 9596 u8 reserved_at_10[0x8]; 9597 u8 width[0x8]; 9598 9599 u8 lane0_module_mapping[0x20]; 9600 9601 u8 lane1_module_mapping[0x20]; 9602 9603 u8 lane2_module_mapping[0x20]; 9604 9605 u8 lane3_module_mapping[0x20]; 9606 9607 u8 reserved_at_a0[0x160]; 9608 }; 9609 9610 struct mlx5_ifc_pmaos_reg_bits { 9611 u8 reserved_at_0[0x8]; 9612 u8 module[0x8]; 9613 u8 reserved_at_10[0x4]; 9614 u8 admin_status[0x4]; 9615 u8 reserved_at_18[0x4]; 9616 u8 oper_status[0x4]; 9617 9618 u8 ase[0x1]; 9619 u8 ee[0x1]; 9620 u8 reserved_at_22[0x1c]; 9621 u8 e[0x2]; 9622 9623 u8 reserved_at_40[0x40]; 9624 }; 9625 9626 struct mlx5_ifc_plpc_reg_bits { 9627 u8 reserved_at_0[0x4]; 9628 u8 profile_id[0xc]; 9629 u8 reserved_at_10[0x4]; 9630 u8 proto_mask[0x4]; 9631 u8 reserved_at_18[0x8]; 9632 9633 u8 reserved_at_20[0x10]; 9634 u8 lane_speed[0x10]; 9635 9636 u8 reserved_at_40[0x17]; 9637 u8 lpbf[0x1]; 9638 u8 fec_mode_policy[0x8]; 9639 9640 u8 retransmission_capability[0x8]; 9641 u8 fec_mode_capability[0x18]; 9642 9643 u8 retransmission_support_admin[0x8]; 9644 u8 fec_mode_support_admin[0x18]; 9645 9646 u8 retransmission_request_admin[0x8]; 9647 u8 fec_mode_request_admin[0x18]; 9648 9649 u8 reserved_at_c0[0x80]; 9650 }; 9651 9652 struct mlx5_ifc_plib_reg_bits { 9653 u8 reserved_at_0[0x8]; 9654 u8 local_port[0x8]; 9655 u8 reserved_at_10[0x8]; 9656 u8 ib_port[0x8]; 9657 9658 u8 reserved_at_20[0x60]; 9659 }; 9660 9661 struct mlx5_ifc_plbf_reg_bits { 9662 u8 reserved_at_0[0x8]; 9663 u8 local_port[0x8]; 9664 u8 reserved_at_10[0xd]; 9665 u8 lbf_mode[0x3]; 9666 9667 u8 reserved_at_20[0x20]; 9668 }; 9669 9670 struct mlx5_ifc_pipg_reg_bits { 9671 u8 reserved_at_0[0x8]; 9672 u8 local_port[0x8]; 9673 u8 reserved_at_10[0x10]; 9674 9675 u8 dic[0x1]; 9676 u8 reserved_at_21[0x19]; 9677 u8 ipg[0x4]; 9678 u8 reserved_at_3e[0x2]; 9679 }; 9680 9681 struct mlx5_ifc_pifr_reg_bits { 9682 u8 reserved_at_0[0x8]; 9683 u8 local_port[0x8]; 9684 u8 reserved_at_10[0x10]; 9685 9686 u8 reserved_at_20[0xe0]; 9687 9688 u8 port_filter[8][0x20]; 9689 9690 u8 port_filter_update_en[8][0x20]; 9691 }; 9692 9693 struct mlx5_ifc_pfcc_reg_bits { 9694 u8 reserved_at_0[0x8]; 9695 u8 local_port[0x8]; 9696 u8 reserved_at_10[0xb]; 9697 u8 ppan_mask_n[0x1]; 9698 u8 minor_stall_mask[0x1]; 9699 u8 critical_stall_mask[0x1]; 9700 u8 reserved_at_1e[0x2]; 9701 9702 u8 ppan[0x4]; 9703 u8 reserved_at_24[0x4]; 9704 u8 prio_mask_tx[0x8]; 9705 u8 reserved_at_30[0x8]; 9706 u8 prio_mask_rx[0x8]; 9707 9708 u8 pptx[0x1]; 9709 u8 aptx[0x1]; 9710 u8 pptx_mask_n[0x1]; 9711 u8 reserved_at_43[0x5]; 9712 u8 pfctx[0x8]; 9713 u8 reserved_at_50[0x10]; 9714 9715 u8 pprx[0x1]; 9716 u8 aprx[0x1]; 9717 u8 pprx_mask_n[0x1]; 9718 u8 reserved_at_63[0x5]; 9719 u8 pfcrx[0x8]; 9720 u8 reserved_at_70[0x10]; 9721 9722 u8 device_stall_minor_watermark[0x10]; 9723 u8 device_stall_critical_watermark[0x10]; 9724 9725 u8 reserved_at_a0[0x60]; 9726 }; 9727 9728 struct mlx5_ifc_pelc_reg_bits { 9729 u8 op[0x4]; 9730 u8 reserved_at_4[0x4]; 9731 u8 local_port[0x8]; 9732 u8 reserved_at_10[0x10]; 9733 9734 u8 op_admin[0x8]; 9735 u8 op_capability[0x8]; 9736 u8 op_request[0x8]; 9737 u8 op_active[0x8]; 9738 9739 u8 admin[0x40]; 9740 9741 u8 capability[0x40]; 9742 9743 u8 request[0x40]; 9744 9745 u8 active[0x40]; 9746 9747 u8 reserved_at_140[0x80]; 9748 }; 9749 9750 struct mlx5_ifc_peir_reg_bits { 9751 u8 reserved_at_0[0x8]; 9752 u8 local_port[0x8]; 9753 u8 reserved_at_10[0x10]; 9754 9755 u8 reserved_at_20[0xc]; 9756 u8 error_count[0x4]; 9757 u8 reserved_at_30[0x10]; 9758 9759 u8 reserved_at_40[0xc]; 9760 u8 lane[0x4]; 9761 u8 reserved_at_50[0x8]; 9762 u8 error_type[0x8]; 9763 }; 9764 9765 struct mlx5_ifc_mpegc_reg_bits { 9766 u8 reserved_at_0[0x30]; 9767 u8 field_select[0x10]; 9768 9769 u8 tx_overflow_sense[0x1]; 9770 u8 mark_cqe[0x1]; 9771 u8 mark_cnp[0x1]; 9772 u8 reserved_at_43[0x1b]; 9773 u8 tx_lossy_overflow_oper[0x2]; 9774 9775 u8 reserved_at_60[0x100]; 9776 }; 9777 9778 enum { 9779 MLX5_MTUTC_OPERATION_SET_TIME_IMMEDIATE = 0x1, 9780 MLX5_MTUTC_OPERATION_ADJUST_TIME = 0x2, 9781 MLX5_MTUTC_OPERATION_ADJUST_FREQ_UTC = 0x3, 9782 }; 9783 9784 struct mlx5_ifc_mtutc_reg_bits { 9785 u8 reserved_at_0[0x1c]; 9786 u8 operation[0x4]; 9787 9788 u8 freq_adjustment[0x20]; 9789 9790 u8 reserved_at_40[0x40]; 9791 9792 u8 utc_sec[0x20]; 9793 9794 u8 reserved_at_a0[0x2]; 9795 u8 utc_nsec[0x1e]; 9796 9797 u8 time_adjustment[0x20]; 9798 }; 9799 9800 struct mlx5_ifc_pcam_enhanced_features_bits { 9801 u8 reserved_at_0[0x68]; 9802 u8 fec_50G_per_lane_in_pplm[0x1]; 9803 u8 reserved_at_69[0x4]; 9804 u8 rx_icrc_encapsulated_counter[0x1]; 9805 u8 reserved_at_6e[0x4]; 9806 u8 ptys_extended_ethernet[0x1]; 9807 u8 reserved_at_73[0x3]; 9808 u8 pfcc_mask[0x1]; 9809 u8 reserved_at_77[0x3]; 9810 u8 per_lane_error_counters[0x1]; 9811 u8 rx_buffer_fullness_counters[0x1]; 9812 u8 ptys_connector_type[0x1]; 9813 u8 reserved_at_7d[0x1]; 9814 u8 ppcnt_discard_group[0x1]; 9815 u8 ppcnt_statistical_group[0x1]; 9816 }; 9817 9818 struct mlx5_ifc_pcam_regs_5000_to_507f_bits { 9819 u8 port_access_reg_cap_mask_127_to_96[0x20]; 9820 u8 port_access_reg_cap_mask_95_to_64[0x20]; 9821 9822 u8 port_access_reg_cap_mask_63_to_36[0x1c]; 9823 u8 pplm[0x1]; 9824 u8 port_access_reg_cap_mask_34_to_32[0x3]; 9825 9826 u8 port_access_reg_cap_mask_31_to_13[0x13]; 9827 u8 pbmc[0x1]; 9828 u8 pptb[0x1]; 9829 u8 port_access_reg_cap_mask_10_to_09[0x2]; 9830 u8 ppcnt[0x1]; 9831 u8 port_access_reg_cap_mask_07_to_00[0x8]; 9832 }; 9833 9834 struct mlx5_ifc_pcam_reg_bits { 9835 u8 reserved_at_0[0x8]; 9836 u8 feature_group[0x8]; 9837 u8 reserved_at_10[0x8]; 9838 u8 access_reg_group[0x8]; 9839 9840 u8 reserved_at_20[0x20]; 9841 9842 union { 9843 struct mlx5_ifc_pcam_regs_5000_to_507f_bits regs_5000_to_507f; 9844 u8 reserved_at_0[0x80]; 9845 } port_access_reg_cap_mask; 9846 9847 u8 reserved_at_c0[0x80]; 9848 9849 union { 9850 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features; 9851 u8 reserved_at_0[0x80]; 9852 } feature_cap_mask; 9853 9854 u8 reserved_at_1c0[0xc0]; 9855 }; 9856 9857 struct mlx5_ifc_mcam_enhanced_features_bits { 9858 u8 reserved_at_0[0x5d]; 9859 u8 mcia_32dwords[0x1]; 9860 u8 out_pulse_duration_ns[0x1]; 9861 u8 npps_period[0x1]; 9862 u8 reserved_at_60[0xa]; 9863 u8 reset_state[0x1]; 9864 u8 ptpcyc2realtime_modify[0x1]; 9865 u8 reserved_at_6c[0x2]; 9866 u8 pci_status_and_power[0x1]; 9867 u8 reserved_at_6f[0x5]; 9868 u8 mark_tx_action_cnp[0x1]; 9869 u8 mark_tx_action_cqe[0x1]; 9870 u8 dynamic_tx_overflow[0x1]; 9871 u8 reserved_at_77[0x4]; 9872 u8 pcie_outbound_stalled[0x1]; 9873 u8 tx_overflow_buffer_pkt[0x1]; 9874 u8 mtpps_enh_out_per_adj[0x1]; 9875 u8 mtpps_fs[0x1]; 9876 u8 pcie_performance_group[0x1]; 9877 }; 9878 9879 struct mlx5_ifc_mcam_access_reg_bits { 9880 u8 reserved_at_0[0x1c]; 9881 u8 mcda[0x1]; 9882 u8 mcc[0x1]; 9883 u8 mcqi[0x1]; 9884 u8 mcqs[0x1]; 9885 9886 u8 regs_95_to_87[0x9]; 9887 u8 mpegc[0x1]; 9888 u8 mtutc[0x1]; 9889 u8 regs_84_to_68[0x11]; 9890 u8 tracer_registers[0x4]; 9891 9892 u8 regs_63_to_46[0x12]; 9893 u8 mrtc[0x1]; 9894 u8 regs_44_to_32[0xd]; 9895 9896 u8 regs_31_to_0[0x20]; 9897 }; 9898 9899 struct mlx5_ifc_mcam_access_reg_bits1 { 9900 u8 regs_127_to_96[0x20]; 9901 9902 u8 regs_95_to_64[0x20]; 9903 9904 u8 regs_63_to_32[0x20]; 9905 9906 u8 regs_31_to_0[0x20]; 9907 }; 9908 9909 struct mlx5_ifc_mcam_access_reg_bits2 { 9910 u8 regs_127_to_99[0x1d]; 9911 u8 mirc[0x1]; 9912 u8 regs_97_to_96[0x2]; 9913 9914 u8 regs_95_to_64[0x20]; 9915 9916 u8 regs_63_to_32[0x20]; 9917 9918 u8 regs_31_to_0[0x20]; 9919 }; 9920 9921 struct mlx5_ifc_mcam_reg_bits { 9922 u8 reserved_at_0[0x8]; 9923 u8 feature_group[0x8]; 9924 u8 reserved_at_10[0x8]; 9925 u8 access_reg_group[0x8]; 9926 9927 u8 reserved_at_20[0x20]; 9928 9929 union { 9930 struct mlx5_ifc_mcam_access_reg_bits access_regs; 9931 struct mlx5_ifc_mcam_access_reg_bits1 access_regs1; 9932 struct mlx5_ifc_mcam_access_reg_bits2 access_regs2; 9933 u8 reserved_at_0[0x80]; 9934 } mng_access_reg_cap_mask; 9935 9936 u8 reserved_at_c0[0x80]; 9937 9938 union { 9939 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features; 9940 u8 reserved_at_0[0x80]; 9941 } mng_feature_cap_mask; 9942 9943 u8 reserved_at_1c0[0x80]; 9944 }; 9945 9946 struct mlx5_ifc_qcam_access_reg_cap_mask { 9947 u8 qcam_access_reg_cap_mask_127_to_20[0x6C]; 9948 u8 qpdpm[0x1]; 9949 u8 qcam_access_reg_cap_mask_18_to_4[0x0F]; 9950 u8 qdpm[0x1]; 9951 u8 qpts[0x1]; 9952 u8 qcap[0x1]; 9953 u8 qcam_access_reg_cap_mask_0[0x1]; 9954 }; 9955 9956 struct mlx5_ifc_qcam_qos_feature_cap_mask { 9957 u8 qcam_qos_feature_cap_mask_127_to_1[0x7F]; 9958 u8 qpts_trust_both[0x1]; 9959 }; 9960 9961 struct mlx5_ifc_qcam_reg_bits { 9962 u8 reserved_at_0[0x8]; 9963 u8 feature_group[0x8]; 9964 u8 reserved_at_10[0x8]; 9965 u8 access_reg_group[0x8]; 9966 u8 reserved_at_20[0x20]; 9967 9968 union { 9969 struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap; 9970 u8 reserved_at_0[0x80]; 9971 } qos_access_reg_cap_mask; 9972 9973 u8 reserved_at_c0[0x80]; 9974 9975 union { 9976 struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap; 9977 u8 reserved_at_0[0x80]; 9978 } qos_feature_cap_mask; 9979 9980 u8 reserved_at_1c0[0x80]; 9981 }; 9982 9983 struct mlx5_ifc_core_dump_reg_bits { 9984 u8 reserved_at_0[0x18]; 9985 u8 core_dump_type[0x8]; 9986 9987 u8 reserved_at_20[0x30]; 9988 u8 vhca_id[0x10]; 9989 9990 u8 reserved_at_60[0x8]; 9991 u8 qpn[0x18]; 9992 u8 reserved_at_80[0x180]; 9993 }; 9994 9995 struct mlx5_ifc_pcap_reg_bits { 9996 u8 reserved_at_0[0x8]; 9997 u8 local_port[0x8]; 9998 u8 reserved_at_10[0x10]; 9999 10000 u8 port_capability_mask[4][0x20]; 10001 }; 10002 10003 struct mlx5_ifc_paos_reg_bits { 10004 u8 swid[0x8]; 10005 u8 local_port[0x8]; 10006 u8 reserved_at_10[0x4]; 10007 u8 admin_status[0x4]; 10008 u8 reserved_at_18[0x4]; 10009 u8 oper_status[0x4]; 10010 10011 u8 ase[0x1]; 10012 u8 ee[0x1]; 10013 u8 reserved_at_22[0x1c]; 10014 u8 e[0x2]; 10015 10016 u8 reserved_at_40[0x40]; 10017 }; 10018 10019 struct mlx5_ifc_pamp_reg_bits { 10020 u8 reserved_at_0[0x8]; 10021 u8 opamp_group[0x8]; 10022 u8 reserved_at_10[0xc]; 10023 u8 opamp_group_type[0x4]; 10024 10025 u8 start_index[0x10]; 10026 u8 reserved_at_30[0x4]; 10027 u8 num_of_indices[0xc]; 10028 10029 u8 index_data[18][0x10]; 10030 }; 10031 10032 struct mlx5_ifc_pcmr_reg_bits { 10033 u8 reserved_at_0[0x8]; 10034 u8 local_port[0x8]; 10035 u8 reserved_at_10[0x10]; 10036 10037 u8 entropy_force_cap[0x1]; 10038 u8 entropy_calc_cap[0x1]; 10039 u8 entropy_gre_calc_cap[0x1]; 10040 u8 reserved_at_23[0xf]; 10041 u8 rx_ts_over_crc_cap[0x1]; 10042 u8 reserved_at_33[0xb]; 10043 u8 fcs_cap[0x1]; 10044 u8 reserved_at_3f[0x1]; 10045 10046 u8 entropy_force[0x1]; 10047 u8 entropy_calc[0x1]; 10048 u8 entropy_gre_calc[0x1]; 10049 u8 reserved_at_43[0xf]; 10050 u8 rx_ts_over_crc[0x1]; 10051 u8 reserved_at_53[0xb]; 10052 u8 fcs_chk[0x1]; 10053 u8 reserved_at_5f[0x1]; 10054 }; 10055 10056 struct mlx5_ifc_lane_2_module_mapping_bits { 10057 u8 reserved_at_0[0x4]; 10058 u8 rx_lane[0x4]; 10059 u8 reserved_at_8[0x4]; 10060 u8 tx_lane[0x4]; 10061 u8 reserved_at_10[0x8]; 10062 u8 module[0x8]; 10063 }; 10064 10065 struct mlx5_ifc_bufferx_reg_bits { 10066 u8 reserved_at_0[0x6]; 10067 u8 lossy[0x1]; 10068 u8 epsb[0x1]; 10069 u8 reserved_at_8[0x8]; 10070 u8 size[0x10]; 10071 10072 u8 xoff_threshold[0x10]; 10073 u8 xon_threshold[0x10]; 10074 }; 10075 10076 struct mlx5_ifc_set_node_in_bits { 10077 u8 node_description[64][0x8]; 10078 }; 10079 10080 struct mlx5_ifc_register_power_settings_bits { 10081 u8 reserved_at_0[0x18]; 10082 u8 power_settings_level[0x8]; 10083 10084 u8 reserved_at_20[0x60]; 10085 }; 10086 10087 struct mlx5_ifc_register_host_endianness_bits { 10088 u8 he[0x1]; 10089 u8 reserved_at_1[0x1f]; 10090 10091 u8 reserved_at_20[0x60]; 10092 }; 10093 10094 struct mlx5_ifc_umr_pointer_desc_argument_bits { 10095 u8 reserved_at_0[0x20]; 10096 10097 u8 mkey[0x20]; 10098 10099 u8 addressh_63_32[0x20]; 10100 10101 u8 addressl_31_0[0x20]; 10102 }; 10103 10104 struct mlx5_ifc_ud_adrs_vector_bits { 10105 u8 dc_key[0x40]; 10106 10107 u8 ext[0x1]; 10108 u8 reserved_at_41[0x7]; 10109 u8 destination_qp_dct[0x18]; 10110 10111 u8 static_rate[0x4]; 10112 u8 sl_eth_prio[0x4]; 10113 u8 fl[0x1]; 10114 u8 mlid[0x7]; 10115 u8 rlid_udp_sport[0x10]; 10116 10117 u8 reserved_at_80[0x20]; 10118 10119 u8 rmac_47_16[0x20]; 10120 10121 u8 rmac_15_0[0x10]; 10122 u8 tclass[0x8]; 10123 u8 hop_limit[0x8]; 10124 10125 u8 reserved_at_e0[0x1]; 10126 u8 grh[0x1]; 10127 u8 reserved_at_e2[0x2]; 10128 u8 src_addr_index[0x8]; 10129 u8 flow_label[0x14]; 10130 10131 u8 rgid_rip[16][0x8]; 10132 }; 10133 10134 struct mlx5_ifc_pages_req_event_bits { 10135 u8 reserved_at_0[0x10]; 10136 u8 function_id[0x10]; 10137 10138 u8 num_pages[0x20]; 10139 10140 u8 reserved_at_40[0xa0]; 10141 }; 10142 10143 struct mlx5_ifc_eqe_bits { 10144 u8 reserved_at_0[0x8]; 10145 u8 event_type[0x8]; 10146 u8 reserved_at_10[0x8]; 10147 u8 event_sub_type[0x8]; 10148 10149 u8 reserved_at_20[0xe0]; 10150 10151 union mlx5_ifc_event_auto_bits event_data; 10152 10153 u8 reserved_at_1e0[0x10]; 10154 u8 signature[0x8]; 10155 u8 reserved_at_1f8[0x7]; 10156 u8 owner[0x1]; 10157 }; 10158 10159 enum { 10160 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7, 10161 }; 10162 10163 struct mlx5_ifc_cmd_queue_entry_bits { 10164 u8 type[0x8]; 10165 u8 reserved_at_8[0x18]; 10166 10167 u8 input_length[0x20]; 10168 10169 u8 input_mailbox_pointer_63_32[0x20]; 10170 10171 u8 input_mailbox_pointer_31_9[0x17]; 10172 u8 reserved_at_77[0x9]; 10173 10174 u8 command_input_inline_data[16][0x8]; 10175 10176 u8 command_output_inline_data[16][0x8]; 10177 10178 u8 output_mailbox_pointer_63_32[0x20]; 10179 10180 u8 output_mailbox_pointer_31_9[0x17]; 10181 u8 reserved_at_1b7[0x9]; 10182 10183 u8 output_length[0x20]; 10184 10185 u8 token[0x8]; 10186 u8 signature[0x8]; 10187 u8 reserved_at_1f0[0x8]; 10188 u8 status[0x7]; 10189 u8 ownership[0x1]; 10190 }; 10191 10192 struct mlx5_ifc_cmd_out_bits { 10193 u8 status[0x8]; 10194 u8 reserved_at_8[0x18]; 10195 10196 u8 syndrome[0x20]; 10197 10198 u8 command_output[0x20]; 10199 }; 10200 10201 struct mlx5_ifc_cmd_in_bits { 10202 u8 opcode[0x10]; 10203 u8 reserved_at_10[0x10]; 10204 10205 u8 reserved_at_20[0x10]; 10206 u8 op_mod[0x10]; 10207 10208 u8 command[][0x20]; 10209 }; 10210 10211 struct mlx5_ifc_cmd_if_box_bits { 10212 u8 mailbox_data[512][0x8]; 10213 10214 u8 reserved_at_1000[0x180]; 10215 10216 u8 next_pointer_63_32[0x20]; 10217 10218 u8 next_pointer_31_10[0x16]; 10219 u8 reserved_at_11b6[0xa]; 10220 10221 u8 block_number[0x20]; 10222 10223 u8 reserved_at_11e0[0x8]; 10224 u8 token[0x8]; 10225 u8 ctrl_signature[0x8]; 10226 u8 signature[0x8]; 10227 }; 10228 10229 struct mlx5_ifc_mtt_bits { 10230 u8 ptag_63_32[0x20]; 10231 10232 u8 ptag_31_8[0x18]; 10233 u8 reserved_at_38[0x6]; 10234 u8 wr_en[0x1]; 10235 u8 rd_en[0x1]; 10236 }; 10237 10238 struct mlx5_ifc_query_wol_rol_out_bits { 10239 u8 status[0x8]; 10240 u8 reserved_at_8[0x18]; 10241 10242 u8 syndrome[0x20]; 10243 10244 u8 reserved_at_40[0x10]; 10245 u8 rol_mode[0x8]; 10246 u8 wol_mode[0x8]; 10247 10248 u8 reserved_at_60[0x20]; 10249 }; 10250 10251 struct mlx5_ifc_query_wol_rol_in_bits { 10252 u8 opcode[0x10]; 10253 u8 reserved_at_10[0x10]; 10254 10255 u8 reserved_at_20[0x10]; 10256 u8 op_mod[0x10]; 10257 10258 u8 reserved_at_40[0x40]; 10259 }; 10260 10261 struct mlx5_ifc_set_wol_rol_out_bits { 10262 u8 status[0x8]; 10263 u8 reserved_at_8[0x18]; 10264 10265 u8 syndrome[0x20]; 10266 10267 u8 reserved_at_40[0x40]; 10268 }; 10269 10270 struct mlx5_ifc_set_wol_rol_in_bits { 10271 u8 opcode[0x10]; 10272 u8 reserved_at_10[0x10]; 10273 10274 u8 reserved_at_20[0x10]; 10275 u8 op_mod[0x10]; 10276 10277 u8 rol_mode_valid[0x1]; 10278 u8 wol_mode_valid[0x1]; 10279 u8 reserved_at_42[0xe]; 10280 u8 rol_mode[0x8]; 10281 u8 wol_mode[0x8]; 10282 10283 u8 reserved_at_60[0x20]; 10284 }; 10285 10286 enum { 10287 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0, 10288 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1, 10289 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2, 10290 }; 10291 10292 enum { 10293 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0, 10294 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1, 10295 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2, 10296 }; 10297 10298 enum { 10299 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR = 0x1, 10300 MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC = 0x7, 10301 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR = 0x8, 10302 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR = 0x9, 10303 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR = 0xa, 10304 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR = 0xb, 10305 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN = 0xc, 10306 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR = 0xd, 10307 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV = 0xe, 10308 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR = 0xf, 10309 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR = 0x10, 10310 }; 10311 10312 struct mlx5_ifc_initial_seg_bits { 10313 u8 fw_rev_minor[0x10]; 10314 u8 fw_rev_major[0x10]; 10315 10316 u8 cmd_interface_rev[0x10]; 10317 u8 fw_rev_subminor[0x10]; 10318 10319 u8 reserved_at_40[0x40]; 10320 10321 u8 cmdq_phy_addr_63_32[0x20]; 10322 10323 u8 cmdq_phy_addr_31_12[0x14]; 10324 u8 reserved_at_b4[0x2]; 10325 u8 nic_interface[0x2]; 10326 u8 log_cmdq_size[0x4]; 10327 u8 log_cmdq_stride[0x4]; 10328 10329 u8 command_doorbell_vector[0x20]; 10330 10331 u8 reserved_at_e0[0xf00]; 10332 10333 u8 initializing[0x1]; 10334 u8 reserved_at_fe1[0x4]; 10335 u8 nic_interface_supported[0x3]; 10336 u8 embedded_cpu[0x1]; 10337 u8 reserved_at_fe9[0x17]; 10338 10339 struct mlx5_ifc_health_buffer_bits health_buffer; 10340 10341 u8 no_dram_nic_offset[0x20]; 10342 10343 u8 reserved_at_1220[0x6e40]; 10344 10345 u8 reserved_at_8060[0x1f]; 10346 u8 clear_int[0x1]; 10347 10348 u8 health_syndrome[0x8]; 10349 u8 health_counter[0x18]; 10350 10351 u8 reserved_at_80a0[0x17fc0]; 10352 }; 10353 10354 struct mlx5_ifc_mtpps_reg_bits { 10355 u8 reserved_at_0[0xc]; 10356 u8 cap_number_of_pps_pins[0x4]; 10357 u8 reserved_at_10[0x4]; 10358 u8 cap_max_num_of_pps_in_pins[0x4]; 10359 u8 reserved_at_18[0x4]; 10360 u8 cap_max_num_of_pps_out_pins[0x4]; 10361 10362 u8 reserved_at_20[0x13]; 10363 u8 cap_log_min_npps_period[0x5]; 10364 u8 reserved_at_38[0x3]; 10365 u8 cap_log_min_out_pulse_duration_ns[0x5]; 10366 10367 u8 reserved_at_40[0x4]; 10368 u8 cap_pin_3_mode[0x4]; 10369 u8 reserved_at_48[0x4]; 10370 u8 cap_pin_2_mode[0x4]; 10371 u8 reserved_at_50[0x4]; 10372 u8 cap_pin_1_mode[0x4]; 10373 u8 reserved_at_58[0x4]; 10374 u8 cap_pin_0_mode[0x4]; 10375 10376 u8 reserved_at_60[0x4]; 10377 u8 cap_pin_7_mode[0x4]; 10378 u8 reserved_at_68[0x4]; 10379 u8 cap_pin_6_mode[0x4]; 10380 u8 reserved_at_70[0x4]; 10381 u8 cap_pin_5_mode[0x4]; 10382 u8 reserved_at_78[0x4]; 10383 u8 cap_pin_4_mode[0x4]; 10384 10385 u8 field_select[0x20]; 10386 u8 reserved_at_a0[0x20]; 10387 10388 u8 npps_period[0x40]; 10389 10390 u8 enable[0x1]; 10391 u8 reserved_at_101[0xb]; 10392 u8 pattern[0x4]; 10393 u8 reserved_at_110[0x4]; 10394 u8 pin_mode[0x4]; 10395 u8 pin[0x8]; 10396 10397 u8 reserved_at_120[0x2]; 10398 u8 out_pulse_duration_ns[0x1e]; 10399 10400 u8 time_stamp[0x40]; 10401 10402 u8 out_pulse_duration[0x10]; 10403 u8 out_periodic_adjustment[0x10]; 10404 u8 enhanced_out_periodic_adjustment[0x20]; 10405 10406 u8 reserved_at_1c0[0x20]; 10407 }; 10408 10409 struct mlx5_ifc_mtppse_reg_bits { 10410 u8 reserved_at_0[0x18]; 10411 u8 pin[0x8]; 10412 u8 event_arm[0x1]; 10413 u8 reserved_at_21[0x1b]; 10414 u8 event_generation_mode[0x4]; 10415 u8 reserved_at_40[0x40]; 10416 }; 10417 10418 struct mlx5_ifc_mcqs_reg_bits { 10419 u8 last_index_flag[0x1]; 10420 u8 reserved_at_1[0x7]; 10421 u8 fw_device[0x8]; 10422 u8 component_index[0x10]; 10423 10424 u8 reserved_at_20[0x10]; 10425 u8 identifier[0x10]; 10426 10427 u8 reserved_at_40[0x17]; 10428 u8 component_status[0x5]; 10429 u8 component_update_state[0x4]; 10430 10431 u8 last_update_state_changer_type[0x4]; 10432 u8 last_update_state_changer_host_id[0x4]; 10433 u8 reserved_at_68[0x18]; 10434 }; 10435 10436 struct mlx5_ifc_mcqi_cap_bits { 10437 u8 supported_info_bitmask[0x20]; 10438 10439 u8 component_size[0x20]; 10440 10441 u8 max_component_size[0x20]; 10442 10443 u8 log_mcda_word_size[0x4]; 10444 u8 reserved_at_64[0xc]; 10445 u8 mcda_max_write_size[0x10]; 10446 10447 u8 rd_en[0x1]; 10448 u8 reserved_at_81[0x1]; 10449 u8 match_chip_id[0x1]; 10450 u8 match_psid[0x1]; 10451 u8 check_user_timestamp[0x1]; 10452 u8 match_base_guid_mac[0x1]; 10453 u8 reserved_at_86[0x1a]; 10454 }; 10455 10456 struct mlx5_ifc_mcqi_version_bits { 10457 u8 reserved_at_0[0x2]; 10458 u8 build_time_valid[0x1]; 10459 u8 user_defined_time_valid[0x1]; 10460 u8 reserved_at_4[0x14]; 10461 u8 version_string_length[0x8]; 10462 10463 u8 version[0x20]; 10464 10465 u8 build_time[0x40]; 10466 10467 u8 user_defined_time[0x40]; 10468 10469 u8 build_tool_version[0x20]; 10470 10471 u8 reserved_at_e0[0x20]; 10472 10473 u8 version_string[92][0x8]; 10474 }; 10475 10476 struct mlx5_ifc_mcqi_activation_method_bits { 10477 u8 pending_server_ac_power_cycle[0x1]; 10478 u8 pending_server_dc_power_cycle[0x1]; 10479 u8 pending_server_reboot[0x1]; 10480 u8 pending_fw_reset[0x1]; 10481 u8 auto_activate[0x1]; 10482 u8 all_hosts_sync[0x1]; 10483 u8 device_hw_reset[0x1]; 10484 u8 reserved_at_7[0x19]; 10485 }; 10486 10487 union mlx5_ifc_mcqi_reg_data_bits { 10488 struct mlx5_ifc_mcqi_cap_bits mcqi_caps; 10489 struct mlx5_ifc_mcqi_version_bits mcqi_version; 10490 struct mlx5_ifc_mcqi_activation_method_bits mcqi_activation_mathod; 10491 }; 10492 10493 struct mlx5_ifc_mcqi_reg_bits { 10494 u8 read_pending_component[0x1]; 10495 u8 reserved_at_1[0xf]; 10496 u8 component_index[0x10]; 10497 10498 u8 reserved_at_20[0x20]; 10499 10500 u8 reserved_at_40[0x1b]; 10501 u8 info_type[0x5]; 10502 10503 u8 info_size[0x20]; 10504 10505 u8 offset[0x20]; 10506 10507 u8 reserved_at_a0[0x10]; 10508 u8 data_size[0x10]; 10509 10510 union mlx5_ifc_mcqi_reg_data_bits data[]; 10511 }; 10512 10513 struct mlx5_ifc_mcc_reg_bits { 10514 u8 reserved_at_0[0x4]; 10515 u8 time_elapsed_since_last_cmd[0xc]; 10516 u8 reserved_at_10[0x8]; 10517 u8 instruction[0x8]; 10518 10519 u8 reserved_at_20[0x10]; 10520 u8 component_index[0x10]; 10521 10522 u8 reserved_at_40[0x8]; 10523 u8 update_handle[0x18]; 10524 10525 u8 handle_owner_type[0x4]; 10526 u8 handle_owner_host_id[0x4]; 10527 u8 reserved_at_68[0x1]; 10528 u8 control_progress[0x7]; 10529 u8 error_code[0x8]; 10530 u8 reserved_at_78[0x4]; 10531 u8 control_state[0x4]; 10532 10533 u8 component_size[0x20]; 10534 10535 u8 reserved_at_a0[0x60]; 10536 }; 10537 10538 struct mlx5_ifc_mcda_reg_bits { 10539 u8 reserved_at_0[0x8]; 10540 u8 update_handle[0x18]; 10541 10542 u8 offset[0x20]; 10543 10544 u8 reserved_at_40[0x10]; 10545 u8 size[0x10]; 10546 10547 u8 reserved_at_60[0x20]; 10548 10549 u8 data[][0x20]; 10550 }; 10551 10552 enum { 10553 MLX5_MFRL_REG_RESET_STATE_IDLE = 0, 10554 MLX5_MFRL_REG_RESET_STATE_IN_NEGOTIATION = 1, 10555 MLX5_MFRL_REG_RESET_STATE_RESET_IN_PROGRESS = 2, 10556 MLX5_MFRL_REG_RESET_STATE_TIMEOUT = 3, 10557 MLX5_MFRL_REG_RESET_STATE_NACK = 4, 10558 }; 10559 10560 enum { 10561 MLX5_MFRL_REG_RESET_TYPE_FULL_CHIP = BIT(0), 10562 MLX5_MFRL_REG_RESET_TYPE_NET_PORT_ALIVE = BIT(1), 10563 }; 10564 10565 enum { 10566 MLX5_MFRL_REG_RESET_LEVEL0 = BIT(0), 10567 MLX5_MFRL_REG_RESET_LEVEL3 = BIT(3), 10568 MLX5_MFRL_REG_RESET_LEVEL6 = BIT(6), 10569 }; 10570 10571 struct mlx5_ifc_mfrl_reg_bits { 10572 u8 reserved_at_0[0x20]; 10573 10574 u8 reserved_at_20[0x2]; 10575 u8 pci_sync_for_fw_update_start[0x1]; 10576 u8 pci_sync_for_fw_update_resp[0x2]; 10577 u8 rst_type_sel[0x3]; 10578 u8 reserved_at_28[0x4]; 10579 u8 reset_state[0x4]; 10580 u8 reset_type[0x8]; 10581 u8 reset_level[0x8]; 10582 }; 10583 10584 struct mlx5_ifc_mirc_reg_bits { 10585 u8 reserved_at_0[0x18]; 10586 u8 status_code[0x8]; 10587 10588 u8 reserved_at_20[0x20]; 10589 }; 10590 10591 struct mlx5_ifc_pddr_monitor_opcode_bits { 10592 u8 reserved_at_0[0x10]; 10593 u8 monitor_opcode[0x10]; 10594 }; 10595 10596 union mlx5_ifc_pddr_troubleshooting_page_status_opcode_auto_bits { 10597 struct mlx5_ifc_pddr_monitor_opcode_bits pddr_monitor_opcode; 10598 u8 reserved_at_0[0x20]; 10599 }; 10600 10601 enum { 10602 /* Monitor opcodes */ 10603 MLX5_PDDR_REG_TRBLSH_GROUP_OPCODE_MONITOR = 0x0, 10604 }; 10605 10606 struct mlx5_ifc_pddr_troubleshooting_page_bits { 10607 u8 reserved_at_0[0x10]; 10608 u8 group_opcode[0x10]; 10609 10610 union mlx5_ifc_pddr_troubleshooting_page_status_opcode_auto_bits status_opcode; 10611 10612 u8 reserved_at_40[0x20]; 10613 10614 u8 status_message[59][0x20]; 10615 }; 10616 10617 union mlx5_ifc_pddr_reg_page_data_auto_bits { 10618 struct mlx5_ifc_pddr_troubleshooting_page_bits pddr_troubleshooting_page; 10619 u8 reserved_at_0[0x7c0]; 10620 }; 10621 10622 enum { 10623 MLX5_PDDR_REG_PAGE_SELECT_TROUBLESHOOTING_INFO_PAGE = 0x1, 10624 }; 10625 10626 struct mlx5_ifc_pddr_reg_bits { 10627 u8 reserved_at_0[0x8]; 10628 u8 local_port[0x8]; 10629 u8 pnat[0x2]; 10630 u8 reserved_at_12[0xe]; 10631 10632 u8 reserved_at_20[0x18]; 10633 u8 page_select[0x8]; 10634 10635 union mlx5_ifc_pddr_reg_page_data_auto_bits page_data; 10636 }; 10637 10638 struct mlx5_ifc_mrtc_reg_bits { 10639 u8 time_synced[0x1]; 10640 u8 reserved_at_1[0x1f]; 10641 10642 u8 reserved_at_20[0x20]; 10643 10644 u8 time_h[0x20]; 10645 10646 u8 time_l[0x20]; 10647 }; 10648 10649 union mlx5_ifc_ports_control_registers_document_bits { 10650 struct mlx5_ifc_bufferx_reg_bits bufferx_reg; 10651 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 10652 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 10653 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 10654 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 10655 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 10656 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 10657 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout; 10658 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout; 10659 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping; 10660 struct mlx5_ifc_pamp_reg_bits pamp_reg; 10661 struct mlx5_ifc_paos_reg_bits paos_reg; 10662 struct mlx5_ifc_pcap_reg_bits pcap_reg; 10663 struct mlx5_ifc_pddr_monitor_opcode_bits pddr_monitor_opcode; 10664 struct mlx5_ifc_pddr_reg_bits pddr_reg; 10665 struct mlx5_ifc_pddr_troubleshooting_page_bits pddr_troubleshooting_page; 10666 struct mlx5_ifc_peir_reg_bits peir_reg; 10667 struct mlx5_ifc_pelc_reg_bits pelc_reg; 10668 struct mlx5_ifc_pfcc_reg_bits pfcc_reg; 10669 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 10670 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 10671 struct mlx5_ifc_pifr_reg_bits pifr_reg; 10672 struct mlx5_ifc_pipg_reg_bits pipg_reg; 10673 struct mlx5_ifc_plbf_reg_bits plbf_reg; 10674 struct mlx5_ifc_plib_reg_bits plib_reg; 10675 struct mlx5_ifc_plpc_reg_bits plpc_reg; 10676 struct mlx5_ifc_pmaos_reg_bits pmaos_reg; 10677 struct mlx5_ifc_pmlp_reg_bits pmlp_reg; 10678 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg; 10679 struct mlx5_ifc_pmpc_reg_bits pmpc_reg; 10680 struct mlx5_ifc_pmpe_reg_bits pmpe_reg; 10681 struct mlx5_ifc_pmpr_reg_bits pmpr_reg; 10682 struct mlx5_ifc_pmtu_reg_bits pmtu_reg; 10683 struct mlx5_ifc_ppad_reg_bits ppad_reg; 10684 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg; 10685 struct mlx5_ifc_mpein_reg_bits mpein_reg; 10686 struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg; 10687 struct mlx5_ifc_pplm_reg_bits pplm_reg; 10688 struct mlx5_ifc_pplr_reg_bits pplr_reg; 10689 struct mlx5_ifc_ppsc_reg_bits ppsc_reg; 10690 struct mlx5_ifc_pqdr_reg_bits pqdr_reg; 10691 struct mlx5_ifc_pspa_reg_bits pspa_reg; 10692 struct mlx5_ifc_ptas_reg_bits ptas_reg; 10693 struct mlx5_ifc_ptys_reg_bits ptys_reg; 10694 struct mlx5_ifc_mlcr_reg_bits mlcr_reg; 10695 struct mlx5_ifc_pude_reg_bits pude_reg; 10696 struct mlx5_ifc_pvlc_reg_bits pvlc_reg; 10697 struct mlx5_ifc_slrg_reg_bits slrg_reg; 10698 struct mlx5_ifc_sltp_reg_bits sltp_reg; 10699 struct mlx5_ifc_mtpps_reg_bits mtpps_reg; 10700 struct mlx5_ifc_mtppse_reg_bits mtppse_reg; 10701 struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg; 10702 struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits; 10703 struct mlx5_ifc_fpga_cap_bits fpga_cap_bits; 10704 struct mlx5_ifc_mcqi_reg_bits mcqi_reg; 10705 struct mlx5_ifc_mcc_reg_bits mcc_reg; 10706 struct mlx5_ifc_mcda_reg_bits mcda_reg; 10707 struct mlx5_ifc_mirc_reg_bits mirc_reg; 10708 struct mlx5_ifc_mfrl_reg_bits mfrl_reg; 10709 struct mlx5_ifc_mtutc_reg_bits mtutc_reg; 10710 struct mlx5_ifc_mrtc_reg_bits mrtc_reg; 10711 u8 reserved_at_0[0x60e0]; 10712 }; 10713 10714 union mlx5_ifc_debug_enhancements_document_bits { 10715 struct mlx5_ifc_health_buffer_bits health_buffer; 10716 u8 reserved_at_0[0x200]; 10717 }; 10718 10719 union mlx5_ifc_uplink_pci_interface_document_bits { 10720 struct mlx5_ifc_initial_seg_bits initial_seg; 10721 u8 reserved_at_0[0x20060]; 10722 }; 10723 10724 struct mlx5_ifc_set_flow_table_root_out_bits { 10725 u8 status[0x8]; 10726 u8 reserved_at_8[0x18]; 10727 10728 u8 syndrome[0x20]; 10729 10730 u8 reserved_at_40[0x40]; 10731 }; 10732 10733 struct mlx5_ifc_set_flow_table_root_in_bits { 10734 u8 opcode[0x10]; 10735 u8 reserved_at_10[0x10]; 10736 10737 u8 reserved_at_20[0x10]; 10738 u8 op_mod[0x10]; 10739 10740 u8 other_vport[0x1]; 10741 u8 reserved_at_41[0xf]; 10742 u8 vport_number[0x10]; 10743 10744 u8 reserved_at_60[0x20]; 10745 10746 u8 table_type[0x8]; 10747 u8 reserved_at_88[0x7]; 10748 u8 table_of_other_vport[0x1]; 10749 u8 table_vport_number[0x10]; 10750 10751 u8 reserved_at_a0[0x8]; 10752 u8 table_id[0x18]; 10753 10754 u8 reserved_at_c0[0x8]; 10755 u8 underlay_qpn[0x18]; 10756 u8 table_eswitch_owner_vhca_id_valid[0x1]; 10757 u8 reserved_at_e1[0xf]; 10758 u8 table_eswitch_owner_vhca_id[0x10]; 10759 u8 reserved_at_100[0x100]; 10760 }; 10761 10762 enum { 10763 MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = (1UL << 0), 10764 MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15), 10765 }; 10766 10767 struct mlx5_ifc_modify_flow_table_out_bits { 10768 u8 status[0x8]; 10769 u8 reserved_at_8[0x18]; 10770 10771 u8 syndrome[0x20]; 10772 10773 u8 reserved_at_40[0x40]; 10774 }; 10775 10776 struct mlx5_ifc_modify_flow_table_in_bits { 10777 u8 opcode[0x10]; 10778 u8 reserved_at_10[0x10]; 10779 10780 u8 reserved_at_20[0x10]; 10781 u8 op_mod[0x10]; 10782 10783 u8 other_vport[0x1]; 10784 u8 reserved_at_41[0xf]; 10785 u8 vport_number[0x10]; 10786 10787 u8 reserved_at_60[0x10]; 10788 u8 modify_field_select[0x10]; 10789 10790 u8 table_type[0x8]; 10791 u8 reserved_at_88[0x18]; 10792 10793 u8 reserved_at_a0[0x8]; 10794 u8 table_id[0x18]; 10795 10796 struct mlx5_ifc_flow_table_context_bits flow_table_context; 10797 }; 10798 10799 struct mlx5_ifc_ets_tcn_config_reg_bits { 10800 u8 g[0x1]; 10801 u8 b[0x1]; 10802 u8 r[0x1]; 10803 u8 reserved_at_3[0x9]; 10804 u8 group[0x4]; 10805 u8 reserved_at_10[0x9]; 10806 u8 bw_allocation[0x7]; 10807 10808 u8 reserved_at_20[0xc]; 10809 u8 max_bw_units[0x4]; 10810 u8 reserved_at_30[0x8]; 10811 u8 max_bw_value[0x8]; 10812 }; 10813 10814 struct mlx5_ifc_ets_global_config_reg_bits { 10815 u8 reserved_at_0[0x2]; 10816 u8 r[0x1]; 10817 u8 reserved_at_3[0x1d]; 10818 10819 u8 reserved_at_20[0xc]; 10820 u8 max_bw_units[0x4]; 10821 u8 reserved_at_30[0x8]; 10822 u8 max_bw_value[0x8]; 10823 }; 10824 10825 struct mlx5_ifc_qetc_reg_bits { 10826 u8 reserved_at_0[0x8]; 10827 u8 port_number[0x8]; 10828 u8 reserved_at_10[0x30]; 10829 10830 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8]; 10831 struct mlx5_ifc_ets_global_config_reg_bits global_configuration; 10832 }; 10833 10834 struct mlx5_ifc_qpdpm_dscp_reg_bits { 10835 u8 e[0x1]; 10836 u8 reserved_at_01[0x0b]; 10837 u8 prio[0x04]; 10838 }; 10839 10840 struct mlx5_ifc_qpdpm_reg_bits { 10841 u8 reserved_at_0[0x8]; 10842 u8 local_port[0x8]; 10843 u8 reserved_at_10[0x10]; 10844 struct mlx5_ifc_qpdpm_dscp_reg_bits dscp[64]; 10845 }; 10846 10847 struct mlx5_ifc_qpts_reg_bits { 10848 u8 reserved_at_0[0x8]; 10849 u8 local_port[0x8]; 10850 u8 reserved_at_10[0x2d]; 10851 u8 trust_state[0x3]; 10852 }; 10853 10854 struct mlx5_ifc_pptb_reg_bits { 10855 u8 reserved_at_0[0x2]; 10856 u8 mm[0x2]; 10857 u8 reserved_at_4[0x4]; 10858 u8 local_port[0x8]; 10859 u8 reserved_at_10[0x6]; 10860 u8 cm[0x1]; 10861 u8 um[0x1]; 10862 u8 pm[0x8]; 10863 10864 u8 prio_x_buff[0x20]; 10865 10866 u8 pm_msb[0x8]; 10867 u8 reserved_at_48[0x10]; 10868 u8 ctrl_buff[0x4]; 10869 u8 untagged_buff[0x4]; 10870 }; 10871 10872 struct mlx5_ifc_sbcam_reg_bits { 10873 u8 reserved_at_0[0x8]; 10874 u8 feature_group[0x8]; 10875 u8 reserved_at_10[0x8]; 10876 u8 access_reg_group[0x8]; 10877 10878 u8 reserved_at_20[0x20]; 10879 10880 u8 sb_access_reg_cap_mask[4][0x20]; 10881 10882 u8 reserved_at_c0[0x80]; 10883 10884 u8 sb_feature_cap_mask[4][0x20]; 10885 10886 u8 reserved_at_1c0[0x40]; 10887 10888 u8 cap_total_buffer_size[0x20]; 10889 10890 u8 cap_cell_size[0x10]; 10891 u8 cap_max_pg_buffers[0x8]; 10892 u8 cap_num_pool_supported[0x8]; 10893 10894 u8 reserved_at_240[0x8]; 10895 u8 cap_sbsr_stat_size[0x8]; 10896 u8 cap_max_tclass_data[0x8]; 10897 u8 cap_max_cpu_ingress_tclass_sb[0x8]; 10898 }; 10899 10900 struct mlx5_ifc_pbmc_reg_bits { 10901 u8 reserved_at_0[0x8]; 10902 u8 local_port[0x8]; 10903 u8 reserved_at_10[0x10]; 10904 10905 u8 xoff_timer_value[0x10]; 10906 u8 xoff_refresh[0x10]; 10907 10908 u8 reserved_at_40[0x9]; 10909 u8 fullness_threshold[0x7]; 10910 u8 port_buffer_size[0x10]; 10911 10912 struct mlx5_ifc_bufferx_reg_bits buffer[10]; 10913 10914 u8 reserved_at_2e0[0x80]; 10915 }; 10916 10917 struct mlx5_ifc_qtct_reg_bits { 10918 u8 reserved_at_0[0x8]; 10919 u8 port_number[0x8]; 10920 u8 reserved_at_10[0xd]; 10921 u8 prio[0x3]; 10922 10923 u8 reserved_at_20[0x1d]; 10924 u8 tclass[0x3]; 10925 }; 10926 10927 struct mlx5_ifc_mcia_reg_bits { 10928 u8 l[0x1]; 10929 u8 reserved_at_1[0x7]; 10930 u8 module[0x8]; 10931 u8 reserved_at_10[0x8]; 10932 u8 status[0x8]; 10933 10934 u8 i2c_device_address[0x8]; 10935 u8 page_number[0x8]; 10936 u8 device_address[0x10]; 10937 10938 u8 reserved_at_40[0x10]; 10939 u8 size[0x10]; 10940 10941 u8 reserved_at_60[0x20]; 10942 10943 u8 dword_0[0x20]; 10944 u8 dword_1[0x20]; 10945 u8 dword_2[0x20]; 10946 u8 dword_3[0x20]; 10947 u8 dword_4[0x20]; 10948 u8 dword_5[0x20]; 10949 u8 dword_6[0x20]; 10950 u8 dword_7[0x20]; 10951 u8 dword_8[0x20]; 10952 u8 dword_9[0x20]; 10953 u8 dword_10[0x20]; 10954 u8 dword_11[0x20]; 10955 }; 10956 10957 struct mlx5_ifc_dcbx_param_bits { 10958 u8 dcbx_cee_cap[0x1]; 10959 u8 dcbx_ieee_cap[0x1]; 10960 u8 dcbx_standby_cap[0x1]; 10961 u8 reserved_at_3[0x5]; 10962 u8 port_number[0x8]; 10963 u8 reserved_at_10[0xa]; 10964 u8 max_application_table_size[6]; 10965 u8 reserved_at_20[0x15]; 10966 u8 version_oper[0x3]; 10967 u8 reserved_at_38[5]; 10968 u8 version_admin[0x3]; 10969 u8 willing_admin[0x1]; 10970 u8 reserved_at_41[0x3]; 10971 u8 pfc_cap_oper[0x4]; 10972 u8 reserved_at_48[0x4]; 10973 u8 pfc_cap_admin[0x4]; 10974 u8 reserved_at_50[0x4]; 10975 u8 num_of_tc_oper[0x4]; 10976 u8 reserved_at_58[0x4]; 10977 u8 num_of_tc_admin[0x4]; 10978 u8 remote_willing[0x1]; 10979 u8 reserved_at_61[3]; 10980 u8 remote_pfc_cap[4]; 10981 u8 reserved_at_68[0x14]; 10982 u8 remote_num_of_tc[0x4]; 10983 u8 reserved_at_80[0x18]; 10984 u8 error[0x8]; 10985 u8 reserved_at_a0[0x160]; 10986 }; 10987 10988 enum { 10989 MLX5_LAG_PORT_SELECT_MODE_QUEUE_AFFINITY = 0, 10990 MLX5_LAG_PORT_SELECT_MODE_PORT_SELECT_FT = 1, 10991 MLX5_LAG_PORT_SELECT_MODE_PORT_SELECT_MPESW = 2, 10992 }; 10993 10994 struct mlx5_ifc_lagc_bits { 10995 u8 fdb_selection_mode[0x1]; 10996 u8 reserved_at_1[0x14]; 10997 u8 port_select_mode[0x3]; 10998 u8 reserved_at_18[0x5]; 10999 u8 lag_state[0x3]; 11000 11001 u8 reserved_at_20[0xc]; 11002 u8 active_port[0x4]; 11003 u8 reserved_at_30[0x4]; 11004 u8 tx_remap_affinity_2[0x4]; 11005 u8 reserved_at_38[0x4]; 11006 u8 tx_remap_affinity_1[0x4]; 11007 }; 11008 11009 struct mlx5_ifc_create_lag_out_bits { 11010 u8 status[0x8]; 11011 u8 reserved_at_8[0x18]; 11012 11013 u8 syndrome[0x20]; 11014 11015 u8 reserved_at_40[0x40]; 11016 }; 11017 11018 struct mlx5_ifc_create_lag_in_bits { 11019 u8 opcode[0x10]; 11020 u8 reserved_at_10[0x10]; 11021 11022 u8 reserved_at_20[0x10]; 11023 u8 op_mod[0x10]; 11024 11025 struct mlx5_ifc_lagc_bits ctx; 11026 }; 11027 11028 struct mlx5_ifc_modify_lag_out_bits { 11029 u8 status[0x8]; 11030 u8 reserved_at_8[0x18]; 11031 11032 u8 syndrome[0x20]; 11033 11034 u8 reserved_at_40[0x40]; 11035 }; 11036 11037 struct mlx5_ifc_modify_lag_in_bits { 11038 u8 opcode[0x10]; 11039 u8 reserved_at_10[0x10]; 11040 11041 u8 reserved_at_20[0x10]; 11042 u8 op_mod[0x10]; 11043 11044 u8 reserved_at_40[0x20]; 11045 u8 field_select[0x20]; 11046 11047 struct mlx5_ifc_lagc_bits ctx; 11048 }; 11049 11050 struct mlx5_ifc_query_lag_out_bits { 11051 u8 status[0x8]; 11052 u8 reserved_at_8[0x18]; 11053 11054 u8 syndrome[0x20]; 11055 11056 struct mlx5_ifc_lagc_bits ctx; 11057 }; 11058 11059 struct mlx5_ifc_query_lag_in_bits { 11060 u8 opcode[0x10]; 11061 u8 reserved_at_10[0x10]; 11062 11063 u8 reserved_at_20[0x10]; 11064 u8 op_mod[0x10]; 11065 11066 u8 reserved_at_40[0x40]; 11067 }; 11068 11069 struct mlx5_ifc_destroy_lag_out_bits { 11070 u8 status[0x8]; 11071 u8 reserved_at_8[0x18]; 11072 11073 u8 syndrome[0x20]; 11074 11075 u8 reserved_at_40[0x40]; 11076 }; 11077 11078 struct mlx5_ifc_destroy_lag_in_bits { 11079 u8 opcode[0x10]; 11080 u8 reserved_at_10[0x10]; 11081 11082 u8 reserved_at_20[0x10]; 11083 u8 op_mod[0x10]; 11084 11085 u8 reserved_at_40[0x40]; 11086 }; 11087 11088 struct mlx5_ifc_create_vport_lag_out_bits { 11089 u8 status[0x8]; 11090 u8 reserved_at_8[0x18]; 11091 11092 u8 syndrome[0x20]; 11093 11094 u8 reserved_at_40[0x40]; 11095 }; 11096 11097 struct mlx5_ifc_create_vport_lag_in_bits { 11098 u8 opcode[0x10]; 11099 u8 reserved_at_10[0x10]; 11100 11101 u8 reserved_at_20[0x10]; 11102 u8 op_mod[0x10]; 11103 11104 u8 reserved_at_40[0x40]; 11105 }; 11106 11107 struct mlx5_ifc_destroy_vport_lag_out_bits { 11108 u8 status[0x8]; 11109 u8 reserved_at_8[0x18]; 11110 11111 u8 syndrome[0x20]; 11112 11113 u8 reserved_at_40[0x40]; 11114 }; 11115 11116 struct mlx5_ifc_destroy_vport_lag_in_bits { 11117 u8 opcode[0x10]; 11118 u8 reserved_at_10[0x10]; 11119 11120 u8 reserved_at_20[0x10]; 11121 u8 op_mod[0x10]; 11122 11123 u8 reserved_at_40[0x40]; 11124 }; 11125 11126 enum { 11127 MLX5_MODIFY_MEMIC_OP_MOD_ALLOC, 11128 MLX5_MODIFY_MEMIC_OP_MOD_DEALLOC, 11129 }; 11130 11131 struct mlx5_ifc_modify_memic_in_bits { 11132 u8 opcode[0x10]; 11133 u8 uid[0x10]; 11134 11135 u8 reserved_at_20[0x10]; 11136 u8 op_mod[0x10]; 11137 11138 u8 reserved_at_40[0x20]; 11139 11140 u8 reserved_at_60[0x18]; 11141 u8 memic_operation_type[0x8]; 11142 11143 u8 memic_start_addr[0x40]; 11144 11145 u8 reserved_at_c0[0x140]; 11146 }; 11147 11148 struct mlx5_ifc_modify_memic_out_bits { 11149 u8 status[0x8]; 11150 u8 reserved_at_8[0x18]; 11151 11152 u8 syndrome[0x20]; 11153 11154 u8 reserved_at_40[0x40]; 11155 11156 u8 memic_operation_addr[0x40]; 11157 11158 u8 reserved_at_c0[0x140]; 11159 }; 11160 11161 struct mlx5_ifc_alloc_memic_in_bits { 11162 u8 opcode[0x10]; 11163 u8 reserved_at_10[0x10]; 11164 11165 u8 reserved_at_20[0x10]; 11166 u8 op_mod[0x10]; 11167 11168 u8 reserved_at_30[0x20]; 11169 11170 u8 reserved_at_40[0x18]; 11171 u8 log_memic_addr_alignment[0x8]; 11172 11173 u8 range_start_addr[0x40]; 11174 11175 u8 range_size[0x20]; 11176 11177 u8 memic_size[0x20]; 11178 }; 11179 11180 struct mlx5_ifc_alloc_memic_out_bits { 11181 u8 status[0x8]; 11182 u8 reserved_at_8[0x18]; 11183 11184 u8 syndrome[0x20]; 11185 11186 u8 memic_start_addr[0x40]; 11187 }; 11188 11189 struct mlx5_ifc_dealloc_memic_in_bits { 11190 u8 opcode[0x10]; 11191 u8 reserved_at_10[0x10]; 11192 11193 u8 reserved_at_20[0x10]; 11194 u8 op_mod[0x10]; 11195 11196 u8 reserved_at_40[0x40]; 11197 11198 u8 memic_start_addr[0x40]; 11199 11200 u8 memic_size[0x20]; 11201 11202 u8 reserved_at_e0[0x20]; 11203 }; 11204 11205 struct mlx5_ifc_dealloc_memic_out_bits { 11206 u8 status[0x8]; 11207 u8 reserved_at_8[0x18]; 11208 11209 u8 syndrome[0x20]; 11210 11211 u8 reserved_at_40[0x40]; 11212 }; 11213 11214 struct mlx5_ifc_umem_bits { 11215 u8 reserved_at_0[0x80]; 11216 11217 u8 reserved_at_80[0x1b]; 11218 u8 log_page_size[0x5]; 11219 11220 u8 page_offset[0x20]; 11221 11222 u8 num_of_mtt[0x40]; 11223 11224 struct mlx5_ifc_mtt_bits mtt[]; 11225 }; 11226 11227 struct mlx5_ifc_uctx_bits { 11228 u8 cap[0x20]; 11229 11230 u8 reserved_at_20[0x160]; 11231 }; 11232 11233 struct mlx5_ifc_sw_icm_bits { 11234 u8 modify_field_select[0x40]; 11235 11236 u8 reserved_at_40[0x18]; 11237 u8 log_sw_icm_size[0x8]; 11238 11239 u8 reserved_at_60[0x20]; 11240 11241 u8 sw_icm_start_addr[0x40]; 11242 11243 u8 reserved_at_c0[0x140]; 11244 }; 11245 11246 struct mlx5_ifc_geneve_tlv_option_bits { 11247 u8 modify_field_select[0x40]; 11248 11249 u8 reserved_at_40[0x18]; 11250 u8 geneve_option_fte_index[0x8]; 11251 11252 u8 option_class[0x10]; 11253 u8 option_type[0x8]; 11254 u8 reserved_at_78[0x3]; 11255 u8 option_data_length[0x5]; 11256 11257 u8 reserved_at_80[0x180]; 11258 }; 11259 11260 struct mlx5_ifc_create_umem_in_bits { 11261 u8 opcode[0x10]; 11262 u8 uid[0x10]; 11263 11264 u8 reserved_at_20[0x10]; 11265 u8 op_mod[0x10]; 11266 11267 u8 reserved_at_40[0x40]; 11268 11269 struct mlx5_ifc_umem_bits umem; 11270 }; 11271 11272 struct mlx5_ifc_create_umem_out_bits { 11273 u8 status[0x8]; 11274 u8 reserved_at_8[0x18]; 11275 11276 u8 syndrome[0x20]; 11277 11278 u8 reserved_at_40[0x8]; 11279 u8 umem_id[0x18]; 11280 11281 u8 reserved_at_60[0x20]; 11282 }; 11283 11284 struct mlx5_ifc_destroy_umem_in_bits { 11285 u8 opcode[0x10]; 11286 u8 uid[0x10]; 11287 11288 u8 reserved_at_20[0x10]; 11289 u8 op_mod[0x10]; 11290 11291 u8 reserved_at_40[0x8]; 11292 u8 umem_id[0x18]; 11293 11294 u8 reserved_at_60[0x20]; 11295 }; 11296 11297 struct mlx5_ifc_destroy_umem_out_bits { 11298 u8 status[0x8]; 11299 u8 reserved_at_8[0x18]; 11300 11301 u8 syndrome[0x20]; 11302 11303 u8 reserved_at_40[0x40]; 11304 }; 11305 11306 struct mlx5_ifc_create_uctx_in_bits { 11307 u8 opcode[0x10]; 11308 u8 reserved_at_10[0x10]; 11309 11310 u8 reserved_at_20[0x10]; 11311 u8 op_mod[0x10]; 11312 11313 u8 reserved_at_40[0x40]; 11314 11315 struct mlx5_ifc_uctx_bits uctx; 11316 }; 11317 11318 struct mlx5_ifc_create_uctx_out_bits { 11319 u8 status[0x8]; 11320 u8 reserved_at_8[0x18]; 11321 11322 u8 syndrome[0x20]; 11323 11324 u8 reserved_at_40[0x10]; 11325 u8 uid[0x10]; 11326 11327 u8 reserved_at_60[0x20]; 11328 }; 11329 11330 struct mlx5_ifc_destroy_uctx_in_bits { 11331 u8 opcode[0x10]; 11332 u8 reserved_at_10[0x10]; 11333 11334 u8 reserved_at_20[0x10]; 11335 u8 op_mod[0x10]; 11336 11337 u8 reserved_at_40[0x10]; 11338 u8 uid[0x10]; 11339 11340 u8 reserved_at_60[0x20]; 11341 }; 11342 11343 struct mlx5_ifc_destroy_uctx_out_bits { 11344 u8 status[0x8]; 11345 u8 reserved_at_8[0x18]; 11346 11347 u8 syndrome[0x20]; 11348 11349 u8 reserved_at_40[0x40]; 11350 }; 11351 11352 struct mlx5_ifc_create_sw_icm_in_bits { 11353 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 11354 struct mlx5_ifc_sw_icm_bits sw_icm; 11355 }; 11356 11357 struct mlx5_ifc_create_geneve_tlv_option_in_bits { 11358 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 11359 struct mlx5_ifc_geneve_tlv_option_bits geneve_tlv_opt; 11360 }; 11361 11362 struct mlx5_ifc_mtrc_string_db_param_bits { 11363 u8 string_db_base_address[0x20]; 11364 11365 u8 reserved_at_20[0x8]; 11366 u8 string_db_size[0x18]; 11367 }; 11368 11369 struct mlx5_ifc_mtrc_cap_bits { 11370 u8 trace_owner[0x1]; 11371 u8 trace_to_memory[0x1]; 11372 u8 reserved_at_2[0x4]; 11373 u8 trc_ver[0x2]; 11374 u8 reserved_at_8[0x14]; 11375 u8 num_string_db[0x4]; 11376 11377 u8 first_string_trace[0x8]; 11378 u8 num_string_trace[0x8]; 11379 u8 reserved_at_30[0x28]; 11380 11381 u8 log_max_trace_buffer_size[0x8]; 11382 11383 u8 reserved_at_60[0x20]; 11384 11385 struct mlx5_ifc_mtrc_string_db_param_bits string_db_param[8]; 11386 11387 u8 reserved_at_280[0x180]; 11388 }; 11389 11390 struct mlx5_ifc_mtrc_conf_bits { 11391 u8 reserved_at_0[0x1c]; 11392 u8 trace_mode[0x4]; 11393 u8 reserved_at_20[0x18]; 11394 u8 log_trace_buffer_size[0x8]; 11395 u8 trace_mkey[0x20]; 11396 u8 reserved_at_60[0x3a0]; 11397 }; 11398 11399 struct mlx5_ifc_mtrc_stdb_bits { 11400 u8 string_db_index[0x4]; 11401 u8 reserved_at_4[0x4]; 11402 u8 read_size[0x18]; 11403 u8 start_offset[0x20]; 11404 u8 string_db_data[]; 11405 }; 11406 11407 struct mlx5_ifc_mtrc_ctrl_bits { 11408 u8 trace_status[0x2]; 11409 u8 reserved_at_2[0x2]; 11410 u8 arm_event[0x1]; 11411 u8 reserved_at_5[0xb]; 11412 u8 modify_field_select[0x10]; 11413 u8 reserved_at_20[0x2b]; 11414 u8 current_timestamp52_32[0x15]; 11415 u8 current_timestamp31_0[0x20]; 11416 u8 reserved_at_80[0x180]; 11417 }; 11418 11419 struct mlx5_ifc_host_params_context_bits { 11420 u8 host_number[0x8]; 11421 u8 reserved_at_8[0x7]; 11422 u8 host_pf_disabled[0x1]; 11423 u8 host_num_of_vfs[0x10]; 11424 11425 u8 host_total_vfs[0x10]; 11426 u8 host_pci_bus[0x10]; 11427 11428 u8 reserved_at_40[0x10]; 11429 u8 host_pci_device[0x10]; 11430 11431 u8 reserved_at_60[0x10]; 11432 u8 host_pci_function[0x10]; 11433 11434 u8 reserved_at_80[0x180]; 11435 }; 11436 11437 struct mlx5_ifc_query_esw_functions_in_bits { 11438 u8 opcode[0x10]; 11439 u8 reserved_at_10[0x10]; 11440 11441 u8 reserved_at_20[0x10]; 11442 u8 op_mod[0x10]; 11443 11444 u8 reserved_at_40[0x40]; 11445 }; 11446 11447 struct mlx5_ifc_query_esw_functions_out_bits { 11448 u8 status[0x8]; 11449 u8 reserved_at_8[0x18]; 11450 11451 u8 syndrome[0x20]; 11452 11453 u8 reserved_at_40[0x40]; 11454 11455 struct mlx5_ifc_host_params_context_bits host_params_context; 11456 11457 u8 reserved_at_280[0x180]; 11458 u8 host_sf_enable[][0x40]; 11459 }; 11460 11461 struct mlx5_ifc_sf_partition_bits { 11462 u8 reserved_at_0[0x10]; 11463 u8 log_num_sf[0x8]; 11464 u8 log_sf_bar_size[0x8]; 11465 }; 11466 11467 struct mlx5_ifc_query_sf_partitions_out_bits { 11468 u8 status[0x8]; 11469 u8 reserved_at_8[0x18]; 11470 11471 u8 syndrome[0x20]; 11472 11473 u8 reserved_at_40[0x18]; 11474 u8 num_sf_partitions[0x8]; 11475 11476 u8 reserved_at_60[0x20]; 11477 11478 struct mlx5_ifc_sf_partition_bits sf_partition[]; 11479 }; 11480 11481 struct mlx5_ifc_query_sf_partitions_in_bits { 11482 u8 opcode[0x10]; 11483 u8 reserved_at_10[0x10]; 11484 11485 u8 reserved_at_20[0x10]; 11486 u8 op_mod[0x10]; 11487 11488 u8 reserved_at_40[0x40]; 11489 }; 11490 11491 struct mlx5_ifc_dealloc_sf_out_bits { 11492 u8 status[0x8]; 11493 u8 reserved_at_8[0x18]; 11494 11495 u8 syndrome[0x20]; 11496 11497 u8 reserved_at_40[0x40]; 11498 }; 11499 11500 struct mlx5_ifc_dealloc_sf_in_bits { 11501 u8 opcode[0x10]; 11502 u8 reserved_at_10[0x10]; 11503 11504 u8 reserved_at_20[0x10]; 11505 u8 op_mod[0x10]; 11506 11507 u8 reserved_at_40[0x10]; 11508 u8 function_id[0x10]; 11509 11510 u8 reserved_at_60[0x20]; 11511 }; 11512 11513 struct mlx5_ifc_alloc_sf_out_bits { 11514 u8 status[0x8]; 11515 u8 reserved_at_8[0x18]; 11516 11517 u8 syndrome[0x20]; 11518 11519 u8 reserved_at_40[0x40]; 11520 }; 11521 11522 struct mlx5_ifc_alloc_sf_in_bits { 11523 u8 opcode[0x10]; 11524 u8 reserved_at_10[0x10]; 11525 11526 u8 reserved_at_20[0x10]; 11527 u8 op_mod[0x10]; 11528 11529 u8 reserved_at_40[0x10]; 11530 u8 function_id[0x10]; 11531 11532 u8 reserved_at_60[0x20]; 11533 }; 11534 11535 struct mlx5_ifc_affiliated_event_header_bits { 11536 u8 reserved_at_0[0x10]; 11537 u8 obj_type[0x10]; 11538 11539 u8 obj_id[0x20]; 11540 }; 11541 11542 enum { 11543 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = BIT_ULL(0xc), 11544 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_IPSEC = BIT_ULL(0x13), 11545 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_SAMPLER = BIT_ULL(0x20), 11546 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_FLOW_METER_ASO = BIT_ULL(0x24), 11547 }; 11548 11549 enum { 11550 MLX5_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = 0xc, 11551 MLX5_GENERAL_OBJECT_TYPES_IPSEC = 0x13, 11552 MLX5_GENERAL_OBJECT_TYPES_SAMPLER = 0x20, 11553 MLX5_GENERAL_OBJECT_TYPES_FLOW_METER_ASO = 0x24, 11554 MLX5_GENERAL_OBJECT_TYPES_MACSEC = 0x27, 11555 }; 11556 11557 enum { 11558 MLX5_IPSEC_OBJECT_ICV_LEN_16B, 11559 }; 11560 11561 struct mlx5_ifc_ipsec_obj_bits { 11562 u8 modify_field_select[0x40]; 11563 u8 full_offload[0x1]; 11564 u8 reserved_at_41[0x1]; 11565 u8 esn_en[0x1]; 11566 u8 esn_overlap[0x1]; 11567 u8 reserved_at_44[0x2]; 11568 u8 icv_length[0x2]; 11569 u8 reserved_at_48[0x4]; 11570 u8 aso_return_reg[0x4]; 11571 u8 reserved_at_50[0x10]; 11572 11573 u8 esn_msb[0x20]; 11574 11575 u8 reserved_at_80[0x8]; 11576 u8 dekn[0x18]; 11577 11578 u8 salt[0x20]; 11579 11580 u8 implicit_iv[0x40]; 11581 11582 u8 reserved_at_100[0x700]; 11583 }; 11584 11585 struct mlx5_ifc_create_ipsec_obj_in_bits { 11586 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 11587 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 11588 }; 11589 11590 enum { 11591 MLX5_MODIFY_IPSEC_BITMASK_ESN_OVERLAP = BIT(0), 11592 MLX5_MODIFY_IPSEC_BITMASK_ESN_MSB = BIT(1), 11593 }; 11594 11595 struct mlx5_ifc_query_ipsec_obj_out_bits { 11596 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 11597 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 11598 }; 11599 11600 struct mlx5_ifc_modify_ipsec_obj_in_bits { 11601 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 11602 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 11603 }; 11604 11605 enum { 11606 MLX5_MACSEC_ASO_REPLAY_PROTECTION = 0x1, 11607 }; 11608 11609 enum { 11610 MLX5_MACSEC_ASO_REPLAY_WIN_32BIT = 0x0, 11611 MLX5_MACSEC_ASO_REPLAY_WIN_64BIT = 0x1, 11612 MLX5_MACSEC_ASO_REPLAY_WIN_128BIT = 0x2, 11613 MLX5_MACSEC_ASO_REPLAY_WIN_256BIT = 0x3, 11614 }; 11615 11616 #define MLX5_MACSEC_ASO_INC_SN 0x2 11617 #define MLX5_MACSEC_ASO_REG_C_4_5 0x2 11618 11619 struct mlx5_ifc_macsec_aso_bits { 11620 u8 valid[0x1]; 11621 u8 reserved_at_1[0x1]; 11622 u8 mode[0x2]; 11623 u8 window_size[0x2]; 11624 u8 soft_lifetime_arm[0x1]; 11625 u8 hard_lifetime_arm[0x1]; 11626 u8 remove_flow_enable[0x1]; 11627 u8 epn_event_arm[0x1]; 11628 u8 reserved_at_a[0x16]; 11629 11630 u8 remove_flow_packet_count[0x20]; 11631 11632 u8 remove_flow_soft_lifetime[0x20]; 11633 11634 u8 reserved_at_60[0x80]; 11635 11636 u8 mode_parameter[0x20]; 11637 11638 u8 replay_protection_window[8][0x20]; 11639 }; 11640 11641 struct mlx5_ifc_macsec_offload_obj_bits { 11642 u8 modify_field_select[0x40]; 11643 11644 u8 confidentiality_en[0x1]; 11645 u8 reserved_at_41[0x1]; 11646 u8 epn_en[0x1]; 11647 u8 epn_overlap[0x1]; 11648 u8 reserved_at_44[0x2]; 11649 u8 confidentiality_offset[0x2]; 11650 u8 reserved_at_48[0x4]; 11651 u8 aso_return_reg[0x4]; 11652 u8 reserved_at_50[0x10]; 11653 11654 u8 epn_msb[0x20]; 11655 11656 u8 reserved_at_80[0x8]; 11657 u8 dekn[0x18]; 11658 11659 u8 reserved_at_a0[0x20]; 11660 11661 u8 sci[0x40]; 11662 11663 u8 reserved_at_100[0x8]; 11664 u8 macsec_aso_access_pd[0x18]; 11665 11666 u8 reserved_at_120[0x60]; 11667 11668 u8 salt[3][0x20]; 11669 11670 u8 reserved_at_1e0[0x20]; 11671 11672 struct mlx5_ifc_macsec_aso_bits macsec_aso; 11673 }; 11674 11675 struct mlx5_ifc_create_macsec_obj_in_bits { 11676 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 11677 struct mlx5_ifc_macsec_offload_obj_bits macsec_object; 11678 }; 11679 11680 struct mlx5_ifc_modify_macsec_obj_in_bits { 11681 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 11682 struct mlx5_ifc_macsec_offload_obj_bits macsec_object; 11683 }; 11684 11685 enum { 11686 MLX5_MODIFY_MACSEC_BITMASK_EPN_OVERLAP = BIT(0), 11687 MLX5_MODIFY_MACSEC_BITMASK_EPN_MSB = BIT(1), 11688 }; 11689 11690 struct mlx5_ifc_query_macsec_obj_out_bits { 11691 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 11692 struct mlx5_ifc_macsec_offload_obj_bits macsec_object; 11693 }; 11694 11695 struct mlx5_ifc_encryption_key_obj_bits { 11696 u8 modify_field_select[0x40]; 11697 11698 u8 reserved_at_40[0x14]; 11699 u8 key_size[0x4]; 11700 u8 reserved_at_58[0x4]; 11701 u8 key_type[0x4]; 11702 11703 u8 reserved_at_60[0x8]; 11704 u8 pd[0x18]; 11705 11706 u8 reserved_at_80[0x180]; 11707 u8 key[8][0x20]; 11708 11709 u8 reserved_at_300[0x500]; 11710 }; 11711 11712 struct mlx5_ifc_create_encryption_key_in_bits { 11713 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 11714 struct mlx5_ifc_encryption_key_obj_bits encryption_key_object; 11715 }; 11716 11717 enum { 11718 MLX5_FLOW_METER_MODE_BYTES_IP_LENGTH = 0x0, 11719 MLX5_FLOW_METER_MODE_BYTES_CALC_WITH_L2 = 0x1, 11720 MLX5_FLOW_METER_MODE_BYTES_CALC_WITH_L2_IPG = 0x2, 11721 MLX5_FLOW_METER_MODE_NUM_PACKETS = 0x3, 11722 }; 11723 11724 struct mlx5_ifc_flow_meter_parameters_bits { 11725 u8 valid[0x1]; 11726 u8 bucket_overflow[0x1]; 11727 u8 start_color[0x2]; 11728 u8 both_buckets_on_green[0x1]; 11729 u8 reserved_at_5[0x1]; 11730 u8 meter_mode[0x2]; 11731 u8 reserved_at_8[0x18]; 11732 11733 u8 reserved_at_20[0x20]; 11734 11735 u8 reserved_at_40[0x3]; 11736 u8 cbs_exponent[0x5]; 11737 u8 cbs_mantissa[0x8]; 11738 u8 reserved_at_50[0x3]; 11739 u8 cir_exponent[0x5]; 11740 u8 cir_mantissa[0x8]; 11741 11742 u8 reserved_at_60[0x20]; 11743 11744 u8 reserved_at_80[0x3]; 11745 u8 ebs_exponent[0x5]; 11746 u8 ebs_mantissa[0x8]; 11747 u8 reserved_at_90[0x3]; 11748 u8 eir_exponent[0x5]; 11749 u8 eir_mantissa[0x8]; 11750 11751 u8 reserved_at_a0[0x60]; 11752 }; 11753 11754 struct mlx5_ifc_flow_meter_aso_obj_bits { 11755 u8 modify_field_select[0x40]; 11756 11757 u8 reserved_at_40[0x40]; 11758 11759 u8 reserved_at_80[0x8]; 11760 u8 meter_aso_access_pd[0x18]; 11761 11762 u8 reserved_at_a0[0x160]; 11763 11764 struct mlx5_ifc_flow_meter_parameters_bits flow_meter_parameters[2]; 11765 }; 11766 11767 struct mlx5_ifc_create_flow_meter_aso_obj_in_bits { 11768 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 11769 struct mlx5_ifc_flow_meter_aso_obj_bits flow_meter_aso_obj; 11770 }; 11771 11772 struct mlx5_ifc_sampler_obj_bits { 11773 u8 modify_field_select[0x40]; 11774 11775 u8 table_type[0x8]; 11776 u8 level[0x8]; 11777 u8 reserved_at_50[0xf]; 11778 u8 ignore_flow_level[0x1]; 11779 11780 u8 sample_ratio[0x20]; 11781 11782 u8 reserved_at_80[0x8]; 11783 u8 sample_table_id[0x18]; 11784 11785 u8 reserved_at_a0[0x8]; 11786 u8 default_table_id[0x18]; 11787 11788 u8 sw_steering_icm_address_rx[0x40]; 11789 u8 sw_steering_icm_address_tx[0x40]; 11790 11791 u8 reserved_at_140[0xa0]; 11792 }; 11793 11794 struct mlx5_ifc_create_sampler_obj_in_bits { 11795 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 11796 struct mlx5_ifc_sampler_obj_bits sampler_object; 11797 }; 11798 11799 struct mlx5_ifc_query_sampler_obj_out_bits { 11800 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 11801 struct mlx5_ifc_sampler_obj_bits sampler_object; 11802 }; 11803 11804 enum { 11805 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_128 = 0x0, 11806 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_256 = 0x1, 11807 }; 11808 11809 enum { 11810 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_TYPE_TLS = 0x1, 11811 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_TYPE_IPSEC = 0x2, 11812 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_TYPE_MACSEC = 0x4, 11813 }; 11814 11815 struct mlx5_ifc_tls_static_params_bits { 11816 u8 const_2[0x2]; 11817 u8 tls_version[0x4]; 11818 u8 const_1[0x2]; 11819 u8 reserved_at_8[0x14]; 11820 u8 encryption_standard[0x4]; 11821 11822 u8 reserved_at_20[0x20]; 11823 11824 u8 initial_record_number[0x40]; 11825 11826 u8 resync_tcp_sn[0x20]; 11827 11828 u8 gcm_iv[0x20]; 11829 11830 u8 implicit_iv[0x40]; 11831 11832 u8 reserved_at_100[0x8]; 11833 u8 dek_index[0x18]; 11834 11835 u8 reserved_at_120[0xe0]; 11836 }; 11837 11838 struct mlx5_ifc_tls_progress_params_bits { 11839 u8 next_record_tcp_sn[0x20]; 11840 11841 u8 hw_resync_tcp_sn[0x20]; 11842 11843 u8 record_tracker_state[0x2]; 11844 u8 auth_state[0x2]; 11845 u8 reserved_at_44[0x4]; 11846 u8 hw_offset_record_number[0x18]; 11847 }; 11848 11849 enum { 11850 MLX5_MTT_PERM_READ = 1 << 0, 11851 MLX5_MTT_PERM_WRITE = 1 << 1, 11852 MLX5_MTT_PERM_RW = MLX5_MTT_PERM_READ | MLX5_MTT_PERM_WRITE, 11853 }; 11854 11855 enum { 11856 MLX5_SUSPEND_VHCA_IN_OP_MOD_SUSPEND_INITIATOR = 0x0, 11857 MLX5_SUSPEND_VHCA_IN_OP_MOD_SUSPEND_RESPONDER = 0x1, 11858 }; 11859 11860 struct mlx5_ifc_suspend_vhca_in_bits { 11861 u8 opcode[0x10]; 11862 u8 uid[0x10]; 11863 11864 u8 reserved_at_20[0x10]; 11865 u8 op_mod[0x10]; 11866 11867 u8 reserved_at_40[0x10]; 11868 u8 vhca_id[0x10]; 11869 11870 u8 reserved_at_60[0x20]; 11871 }; 11872 11873 struct mlx5_ifc_suspend_vhca_out_bits { 11874 u8 status[0x8]; 11875 u8 reserved_at_8[0x18]; 11876 11877 u8 syndrome[0x20]; 11878 11879 u8 reserved_at_40[0x40]; 11880 }; 11881 11882 enum { 11883 MLX5_RESUME_VHCA_IN_OP_MOD_RESUME_RESPONDER = 0x0, 11884 MLX5_RESUME_VHCA_IN_OP_MOD_RESUME_INITIATOR = 0x1, 11885 }; 11886 11887 struct mlx5_ifc_resume_vhca_in_bits { 11888 u8 opcode[0x10]; 11889 u8 uid[0x10]; 11890 11891 u8 reserved_at_20[0x10]; 11892 u8 op_mod[0x10]; 11893 11894 u8 reserved_at_40[0x10]; 11895 u8 vhca_id[0x10]; 11896 11897 u8 reserved_at_60[0x20]; 11898 }; 11899 11900 struct mlx5_ifc_resume_vhca_out_bits { 11901 u8 status[0x8]; 11902 u8 reserved_at_8[0x18]; 11903 11904 u8 syndrome[0x20]; 11905 11906 u8 reserved_at_40[0x40]; 11907 }; 11908 11909 struct mlx5_ifc_query_vhca_migration_state_in_bits { 11910 u8 opcode[0x10]; 11911 u8 uid[0x10]; 11912 11913 u8 reserved_at_20[0x10]; 11914 u8 op_mod[0x10]; 11915 11916 u8 reserved_at_40[0x10]; 11917 u8 vhca_id[0x10]; 11918 11919 u8 reserved_at_60[0x20]; 11920 }; 11921 11922 struct mlx5_ifc_query_vhca_migration_state_out_bits { 11923 u8 status[0x8]; 11924 u8 reserved_at_8[0x18]; 11925 11926 u8 syndrome[0x20]; 11927 11928 u8 reserved_at_40[0x40]; 11929 11930 u8 required_umem_size[0x20]; 11931 11932 u8 reserved_at_a0[0x160]; 11933 }; 11934 11935 struct mlx5_ifc_save_vhca_state_in_bits { 11936 u8 opcode[0x10]; 11937 u8 uid[0x10]; 11938 11939 u8 reserved_at_20[0x10]; 11940 u8 op_mod[0x10]; 11941 11942 u8 reserved_at_40[0x10]; 11943 u8 vhca_id[0x10]; 11944 11945 u8 reserved_at_60[0x20]; 11946 11947 u8 va[0x40]; 11948 11949 u8 mkey[0x20]; 11950 11951 u8 size[0x20]; 11952 }; 11953 11954 struct mlx5_ifc_save_vhca_state_out_bits { 11955 u8 status[0x8]; 11956 u8 reserved_at_8[0x18]; 11957 11958 u8 syndrome[0x20]; 11959 11960 u8 actual_image_size[0x20]; 11961 11962 u8 reserved_at_60[0x20]; 11963 }; 11964 11965 struct mlx5_ifc_load_vhca_state_in_bits { 11966 u8 opcode[0x10]; 11967 u8 uid[0x10]; 11968 11969 u8 reserved_at_20[0x10]; 11970 u8 op_mod[0x10]; 11971 11972 u8 reserved_at_40[0x10]; 11973 u8 vhca_id[0x10]; 11974 11975 u8 reserved_at_60[0x20]; 11976 11977 u8 va[0x40]; 11978 11979 u8 mkey[0x20]; 11980 11981 u8 size[0x20]; 11982 }; 11983 11984 struct mlx5_ifc_load_vhca_state_out_bits { 11985 u8 status[0x8]; 11986 u8 reserved_at_8[0x18]; 11987 11988 u8 syndrome[0x20]; 11989 11990 u8 reserved_at_40[0x40]; 11991 }; 11992 11993 struct mlx5_ifc_adv_virtualization_cap_bits { 11994 u8 reserved_at_0[0x3]; 11995 u8 pg_track_log_max_num[0x5]; 11996 u8 pg_track_max_num_range[0x8]; 11997 u8 pg_track_log_min_addr_space[0x8]; 11998 u8 pg_track_log_max_addr_space[0x8]; 11999 12000 u8 reserved_at_20[0x3]; 12001 u8 pg_track_log_min_msg_size[0x5]; 12002 u8 reserved_at_28[0x3]; 12003 u8 pg_track_log_max_msg_size[0x5]; 12004 u8 reserved_at_30[0x3]; 12005 u8 pg_track_log_min_page_size[0x5]; 12006 u8 reserved_at_38[0x3]; 12007 u8 pg_track_log_max_page_size[0x5]; 12008 12009 u8 reserved_at_40[0x7c0]; 12010 }; 12011 12012 struct mlx5_ifc_page_track_report_entry_bits { 12013 u8 dirty_address_high[0x20]; 12014 12015 u8 dirty_address_low[0x20]; 12016 }; 12017 12018 enum { 12019 MLX5_PAGE_TRACK_STATE_TRACKING, 12020 MLX5_PAGE_TRACK_STATE_REPORTING, 12021 MLX5_PAGE_TRACK_STATE_ERROR, 12022 }; 12023 12024 struct mlx5_ifc_page_track_range_bits { 12025 u8 start_address[0x40]; 12026 12027 u8 length[0x40]; 12028 }; 12029 12030 struct mlx5_ifc_page_track_bits { 12031 u8 modify_field_select[0x40]; 12032 12033 u8 reserved_at_40[0x10]; 12034 u8 vhca_id[0x10]; 12035 12036 u8 reserved_at_60[0x20]; 12037 12038 u8 state[0x4]; 12039 u8 track_type[0x4]; 12040 u8 log_addr_space_size[0x8]; 12041 u8 reserved_at_90[0x3]; 12042 u8 log_page_size[0x5]; 12043 u8 reserved_at_98[0x3]; 12044 u8 log_msg_size[0x5]; 12045 12046 u8 reserved_at_a0[0x8]; 12047 u8 reporting_qpn[0x18]; 12048 12049 u8 reserved_at_c0[0x18]; 12050 u8 num_ranges[0x8]; 12051 12052 u8 reserved_at_e0[0x20]; 12053 12054 u8 range_start_address[0x40]; 12055 12056 u8 length[0x40]; 12057 12058 struct mlx5_ifc_page_track_range_bits track_range[0]; 12059 }; 12060 12061 struct mlx5_ifc_create_page_track_obj_in_bits { 12062 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12063 struct mlx5_ifc_page_track_bits obj_context; 12064 }; 12065 12066 struct mlx5_ifc_modify_page_track_obj_in_bits { 12067 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12068 struct mlx5_ifc_page_track_bits obj_context; 12069 }; 12070 12071 #endif /* MLX5_IFC_H */ 12072