1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 #ifndef MLX5_IFC_H 33 #define MLX5_IFC_H 34 35 #include "mlx5_ifc_fpga.h" 36 37 enum { 38 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0, 39 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1, 40 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2, 41 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3, 42 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13, 43 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14, 44 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c, 45 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d, 46 MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4, 47 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5, 48 MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED = 0x7, 49 MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT = 0xc, 50 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10, 51 MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR = 0x11, 52 MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR = 0x12, 53 MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR = 0x8, 54 MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE = 0x9, 55 MLX5_EVENT_TYPE_CODING_GPIO_EVENT = 0x15, 56 MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19, 57 MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a, 58 MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT = 0x1b, 59 MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT = 0x1f, 60 MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa, 61 MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb, 62 MLX5_EVENT_TYPE_CODING_FPGA_ERROR = 0x20, 63 MLX5_EVENT_TYPE_CODING_FPGA_QP_ERROR = 0x21 64 }; 65 66 enum { 67 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0, 68 MLX5_SET_HCA_CAP_OP_MOD_ODP = 0x2, 69 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3, 70 MLX5_SET_HCA_CAP_OP_MOD_ROCE = 0x4, 71 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE2 = 0x20, 72 MLX5_SET_HCA_CAP_OP_MODE_PORT_SELECTION = 0x25, 73 }; 74 75 enum { 76 MLX5_SHARED_RESOURCE_UID = 0xffff, 77 }; 78 79 enum { 80 MLX5_OBJ_TYPE_SW_ICM = 0x0008, 81 MLX5_OBJ_TYPE_HEADER_MODIFY_ARGUMENT = 0x23, 82 }; 83 84 enum { 85 MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM = (1ULL << MLX5_OBJ_TYPE_SW_ICM), 86 MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT = (1ULL << 11), 87 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q = (1ULL << 13), 88 MLX5_GENERAL_OBJ_TYPES_CAP_HEADER_MODIFY_ARGUMENT = 89 (1ULL << MLX5_OBJ_TYPE_HEADER_MODIFY_ARGUMENT), 90 MLX5_GENERAL_OBJ_TYPES_CAP_MACSEC_OFFLOAD = (1ULL << 39), 91 }; 92 93 enum { 94 MLX5_OBJ_TYPE_GENEVE_TLV_OPT = 0x000b, 95 MLX5_OBJ_TYPE_VIRTIO_NET_Q = 0x000d, 96 MLX5_OBJ_TYPE_VIRTIO_Q_COUNTERS = 0x001c, 97 MLX5_OBJ_TYPE_MATCH_DEFINER = 0x0018, 98 MLX5_OBJ_TYPE_PAGE_TRACK = 0x46, 99 MLX5_OBJ_TYPE_MKEY = 0xff01, 100 MLX5_OBJ_TYPE_QP = 0xff02, 101 MLX5_OBJ_TYPE_PSV = 0xff03, 102 MLX5_OBJ_TYPE_RMP = 0xff04, 103 MLX5_OBJ_TYPE_XRC_SRQ = 0xff05, 104 MLX5_OBJ_TYPE_RQ = 0xff06, 105 MLX5_OBJ_TYPE_SQ = 0xff07, 106 MLX5_OBJ_TYPE_TIR = 0xff08, 107 MLX5_OBJ_TYPE_TIS = 0xff09, 108 MLX5_OBJ_TYPE_DCT = 0xff0a, 109 MLX5_OBJ_TYPE_XRQ = 0xff0b, 110 MLX5_OBJ_TYPE_RQT = 0xff0e, 111 MLX5_OBJ_TYPE_FLOW_COUNTER = 0xff0f, 112 MLX5_OBJ_TYPE_CQ = 0xff10, 113 }; 114 115 enum { 116 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100, 117 MLX5_CMD_OP_QUERY_ADAPTER = 0x101, 118 MLX5_CMD_OP_INIT_HCA = 0x102, 119 MLX5_CMD_OP_TEARDOWN_HCA = 0x103, 120 MLX5_CMD_OP_ENABLE_HCA = 0x104, 121 MLX5_CMD_OP_DISABLE_HCA = 0x105, 122 MLX5_CMD_OP_QUERY_PAGES = 0x107, 123 MLX5_CMD_OP_MANAGE_PAGES = 0x108, 124 MLX5_CMD_OP_SET_HCA_CAP = 0x109, 125 MLX5_CMD_OP_QUERY_ISSI = 0x10a, 126 MLX5_CMD_OP_SET_ISSI = 0x10b, 127 MLX5_CMD_OP_SET_DRIVER_VERSION = 0x10d, 128 MLX5_CMD_OP_QUERY_SF_PARTITION = 0x111, 129 MLX5_CMD_OP_ALLOC_SF = 0x113, 130 MLX5_CMD_OP_DEALLOC_SF = 0x114, 131 MLX5_CMD_OP_SUSPEND_VHCA = 0x115, 132 MLX5_CMD_OP_RESUME_VHCA = 0x116, 133 MLX5_CMD_OP_QUERY_VHCA_MIGRATION_STATE = 0x117, 134 MLX5_CMD_OP_SAVE_VHCA_STATE = 0x118, 135 MLX5_CMD_OP_LOAD_VHCA_STATE = 0x119, 136 MLX5_CMD_OP_CREATE_MKEY = 0x200, 137 MLX5_CMD_OP_QUERY_MKEY = 0x201, 138 MLX5_CMD_OP_DESTROY_MKEY = 0x202, 139 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203, 140 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204, 141 MLX5_CMD_OP_ALLOC_MEMIC = 0x205, 142 MLX5_CMD_OP_DEALLOC_MEMIC = 0x206, 143 MLX5_CMD_OP_MODIFY_MEMIC = 0x207, 144 MLX5_CMD_OP_CREATE_EQ = 0x301, 145 MLX5_CMD_OP_DESTROY_EQ = 0x302, 146 MLX5_CMD_OP_QUERY_EQ = 0x303, 147 MLX5_CMD_OP_GEN_EQE = 0x304, 148 MLX5_CMD_OP_CREATE_CQ = 0x400, 149 MLX5_CMD_OP_DESTROY_CQ = 0x401, 150 MLX5_CMD_OP_QUERY_CQ = 0x402, 151 MLX5_CMD_OP_MODIFY_CQ = 0x403, 152 MLX5_CMD_OP_CREATE_QP = 0x500, 153 MLX5_CMD_OP_DESTROY_QP = 0x501, 154 MLX5_CMD_OP_RST2INIT_QP = 0x502, 155 MLX5_CMD_OP_INIT2RTR_QP = 0x503, 156 MLX5_CMD_OP_RTR2RTS_QP = 0x504, 157 MLX5_CMD_OP_RTS2RTS_QP = 0x505, 158 MLX5_CMD_OP_SQERR2RTS_QP = 0x506, 159 MLX5_CMD_OP_2ERR_QP = 0x507, 160 MLX5_CMD_OP_2RST_QP = 0x50a, 161 MLX5_CMD_OP_QUERY_QP = 0x50b, 162 MLX5_CMD_OP_SQD_RTS_QP = 0x50c, 163 MLX5_CMD_OP_INIT2INIT_QP = 0x50e, 164 MLX5_CMD_OP_CREATE_PSV = 0x600, 165 MLX5_CMD_OP_DESTROY_PSV = 0x601, 166 MLX5_CMD_OP_CREATE_SRQ = 0x700, 167 MLX5_CMD_OP_DESTROY_SRQ = 0x701, 168 MLX5_CMD_OP_QUERY_SRQ = 0x702, 169 MLX5_CMD_OP_ARM_RQ = 0x703, 170 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705, 171 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706, 172 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707, 173 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708, 174 MLX5_CMD_OP_CREATE_DCT = 0x710, 175 MLX5_CMD_OP_DESTROY_DCT = 0x711, 176 MLX5_CMD_OP_DRAIN_DCT = 0x712, 177 MLX5_CMD_OP_QUERY_DCT = 0x713, 178 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714, 179 MLX5_CMD_OP_CREATE_XRQ = 0x717, 180 MLX5_CMD_OP_DESTROY_XRQ = 0x718, 181 MLX5_CMD_OP_QUERY_XRQ = 0x719, 182 MLX5_CMD_OP_ARM_XRQ = 0x71a, 183 MLX5_CMD_OP_QUERY_XRQ_DC_PARAMS_ENTRY = 0x725, 184 MLX5_CMD_OP_SET_XRQ_DC_PARAMS_ENTRY = 0x726, 185 MLX5_CMD_OP_QUERY_XRQ_ERROR_PARAMS = 0x727, 186 MLX5_CMD_OP_RELEASE_XRQ_ERROR = 0x729, 187 MLX5_CMD_OP_MODIFY_XRQ = 0x72a, 188 MLX5_CMD_OP_QUERY_ESW_FUNCTIONS = 0x740, 189 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750, 190 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751, 191 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752, 192 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753, 193 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754, 194 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755, 195 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760, 196 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761, 197 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762, 198 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763, 199 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764, 200 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765, 201 MLX5_CMD_OP_QUERY_VNIC_ENV = 0x76f, 202 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770, 203 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771, 204 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772, 205 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773, 206 MLX5_CMD_OP_SET_MONITOR_COUNTER = 0x774, 207 MLX5_CMD_OP_ARM_MONITOR_COUNTER = 0x775, 208 MLX5_CMD_OP_SET_PP_RATE_LIMIT = 0x780, 209 MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781, 210 MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT = 0x782, 211 MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT = 0x783, 212 MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT = 0x784, 213 MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT = 0x785, 214 MLX5_CMD_OP_CREATE_QOS_PARA_VPORT = 0x786, 215 MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT = 0x787, 216 MLX5_CMD_OP_ALLOC_PD = 0x800, 217 MLX5_CMD_OP_DEALLOC_PD = 0x801, 218 MLX5_CMD_OP_ALLOC_UAR = 0x802, 219 MLX5_CMD_OP_DEALLOC_UAR = 0x803, 220 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804, 221 MLX5_CMD_OP_ACCESS_REG = 0x805, 222 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806, 223 MLX5_CMD_OP_DETACH_FROM_MCG = 0x807, 224 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a, 225 MLX5_CMD_OP_MAD_IFC = 0x50d, 226 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b, 227 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c, 228 MLX5_CMD_OP_NOP = 0x80d, 229 MLX5_CMD_OP_ALLOC_XRCD = 0x80e, 230 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f, 231 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816, 232 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817, 233 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822, 234 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823, 235 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824, 236 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825, 237 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826, 238 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827, 239 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828, 240 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829, 241 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a, 242 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b, 243 MLX5_CMD_OP_SET_WOL_ROL = 0x830, 244 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831, 245 MLX5_CMD_OP_CREATE_LAG = 0x840, 246 MLX5_CMD_OP_MODIFY_LAG = 0x841, 247 MLX5_CMD_OP_QUERY_LAG = 0x842, 248 MLX5_CMD_OP_DESTROY_LAG = 0x843, 249 MLX5_CMD_OP_CREATE_VPORT_LAG = 0x844, 250 MLX5_CMD_OP_DESTROY_VPORT_LAG = 0x845, 251 MLX5_CMD_OP_CREATE_TIR = 0x900, 252 MLX5_CMD_OP_MODIFY_TIR = 0x901, 253 MLX5_CMD_OP_DESTROY_TIR = 0x902, 254 MLX5_CMD_OP_QUERY_TIR = 0x903, 255 MLX5_CMD_OP_CREATE_SQ = 0x904, 256 MLX5_CMD_OP_MODIFY_SQ = 0x905, 257 MLX5_CMD_OP_DESTROY_SQ = 0x906, 258 MLX5_CMD_OP_QUERY_SQ = 0x907, 259 MLX5_CMD_OP_CREATE_RQ = 0x908, 260 MLX5_CMD_OP_MODIFY_RQ = 0x909, 261 MLX5_CMD_OP_SET_DELAY_DROP_PARAMS = 0x910, 262 MLX5_CMD_OP_DESTROY_RQ = 0x90a, 263 MLX5_CMD_OP_QUERY_RQ = 0x90b, 264 MLX5_CMD_OP_CREATE_RMP = 0x90c, 265 MLX5_CMD_OP_MODIFY_RMP = 0x90d, 266 MLX5_CMD_OP_DESTROY_RMP = 0x90e, 267 MLX5_CMD_OP_QUERY_RMP = 0x90f, 268 MLX5_CMD_OP_CREATE_TIS = 0x912, 269 MLX5_CMD_OP_MODIFY_TIS = 0x913, 270 MLX5_CMD_OP_DESTROY_TIS = 0x914, 271 MLX5_CMD_OP_QUERY_TIS = 0x915, 272 MLX5_CMD_OP_CREATE_RQT = 0x916, 273 MLX5_CMD_OP_MODIFY_RQT = 0x917, 274 MLX5_CMD_OP_DESTROY_RQT = 0x918, 275 MLX5_CMD_OP_QUERY_RQT = 0x919, 276 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f, 277 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930, 278 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931, 279 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932, 280 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933, 281 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934, 282 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935, 283 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936, 284 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937, 285 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938, 286 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939, 287 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a, 288 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b, 289 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c, 290 MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT = 0x93d, 291 MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT = 0x93e, 292 MLX5_CMD_OP_QUERY_PACKET_REFORMAT_CONTEXT = 0x93f, 293 MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT = 0x940, 294 MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941, 295 MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT = 0x942, 296 MLX5_CMD_OP_FPGA_CREATE_QP = 0x960, 297 MLX5_CMD_OP_FPGA_MODIFY_QP = 0x961, 298 MLX5_CMD_OP_FPGA_QUERY_QP = 0x962, 299 MLX5_CMD_OP_FPGA_DESTROY_QP = 0x963, 300 MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS = 0x964, 301 MLX5_CMD_OP_CREATE_GENERAL_OBJECT = 0xa00, 302 MLX5_CMD_OP_MODIFY_GENERAL_OBJECT = 0xa01, 303 MLX5_CMD_OP_QUERY_GENERAL_OBJECT = 0xa02, 304 MLX5_CMD_OP_DESTROY_GENERAL_OBJECT = 0xa03, 305 MLX5_CMD_OP_CREATE_UCTX = 0xa04, 306 MLX5_CMD_OP_DESTROY_UCTX = 0xa06, 307 MLX5_CMD_OP_CREATE_UMEM = 0xa08, 308 MLX5_CMD_OP_DESTROY_UMEM = 0xa0a, 309 MLX5_CMD_OP_SYNC_STEERING = 0xb00, 310 MLX5_CMD_OP_QUERY_VHCA_STATE = 0xb0d, 311 MLX5_CMD_OP_MODIFY_VHCA_STATE = 0xb0e, 312 MLX5_CMD_OP_SYNC_CRYPTO = 0xb12, 313 MLX5_CMD_OP_MAX 314 }; 315 316 /* Valid range for general commands that don't work over an object */ 317 enum { 318 MLX5_CMD_OP_GENERAL_START = 0xb00, 319 MLX5_CMD_OP_GENERAL_END = 0xd00, 320 }; 321 322 enum { 323 MLX5_FT_NIC_RX_2_NIC_RX_RDMA = BIT(0), 324 MLX5_FT_NIC_TX_RDMA_2_NIC_TX = BIT(1), 325 }; 326 327 enum { 328 MLX5_CMD_OP_MOD_UPDATE_HEADER_MODIFY_ARGUMENT = 0x1, 329 }; 330 331 struct mlx5_ifc_flow_table_fields_supported_bits { 332 u8 outer_dmac[0x1]; 333 u8 outer_smac[0x1]; 334 u8 outer_ether_type[0x1]; 335 u8 outer_ip_version[0x1]; 336 u8 outer_first_prio[0x1]; 337 u8 outer_first_cfi[0x1]; 338 u8 outer_first_vid[0x1]; 339 u8 outer_ipv4_ttl[0x1]; 340 u8 outer_second_prio[0x1]; 341 u8 outer_second_cfi[0x1]; 342 u8 outer_second_vid[0x1]; 343 u8 reserved_at_b[0x1]; 344 u8 outer_sip[0x1]; 345 u8 outer_dip[0x1]; 346 u8 outer_frag[0x1]; 347 u8 outer_ip_protocol[0x1]; 348 u8 outer_ip_ecn[0x1]; 349 u8 outer_ip_dscp[0x1]; 350 u8 outer_udp_sport[0x1]; 351 u8 outer_udp_dport[0x1]; 352 u8 outer_tcp_sport[0x1]; 353 u8 outer_tcp_dport[0x1]; 354 u8 outer_tcp_flags[0x1]; 355 u8 outer_gre_protocol[0x1]; 356 u8 outer_gre_key[0x1]; 357 u8 outer_vxlan_vni[0x1]; 358 u8 outer_geneve_vni[0x1]; 359 u8 outer_geneve_oam[0x1]; 360 u8 outer_geneve_protocol_type[0x1]; 361 u8 outer_geneve_opt_len[0x1]; 362 u8 source_vhca_port[0x1]; 363 u8 source_eswitch_port[0x1]; 364 365 u8 inner_dmac[0x1]; 366 u8 inner_smac[0x1]; 367 u8 inner_ether_type[0x1]; 368 u8 inner_ip_version[0x1]; 369 u8 inner_first_prio[0x1]; 370 u8 inner_first_cfi[0x1]; 371 u8 inner_first_vid[0x1]; 372 u8 reserved_at_27[0x1]; 373 u8 inner_second_prio[0x1]; 374 u8 inner_second_cfi[0x1]; 375 u8 inner_second_vid[0x1]; 376 u8 reserved_at_2b[0x1]; 377 u8 inner_sip[0x1]; 378 u8 inner_dip[0x1]; 379 u8 inner_frag[0x1]; 380 u8 inner_ip_protocol[0x1]; 381 u8 inner_ip_ecn[0x1]; 382 u8 inner_ip_dscp[0x1]; 383 u8 inner_udp_sport[0x1]; 384 u8 inner_udp_dport[0x1]; 385 u8 inner_tcp_sport[0x1]; 386 u8 inner_tcp_dport[0x1]; 387 u8 inner_tcp_flags[0x1]; 388 u8 reserved_at_37[0x9]; 389 390 u8 geneve_tlv_option_0_data[0x1]; 391 u8 geneve_tlv_option_0_exist[0x1]; 392 u8 reserved_at_42[0x3]; 393 u8 outer_first_mpls_over_udp[0x4]; 394 u8 outer_first_mpls_over_gre[0x4]; 395 u8 inner_first_mpls[0x4]; 396 u8 outer_first_mpls[0x4]; 397 u8 reserved_at_55[0x2]; 398 u8 outer_esp_spi[0x1]; 399 u8 reserved_at_58[0x2]; 400 u8 bth_dst_qp[0x1]; 401 u8 reserved_at_5b[0x5]; 402 403 u8 reserved_at_60[0x18]; 404 u8 metadata_reg_c_7[0x1]; 405 u8 metadata_reg_c_6[0x1]; 406 u8 metadata_reg_c_5[0x1]; 407 u8 metadata_reg_c_4[0x1]; 408 u8 metadata_reg_c_3[0x1]; 409 u8 metadata_reg_c_2[0x1]; 410 u8 metadata_reg_c_1[0x1]; 411 u8 metadata_reg_c_0[0x1]; 412 }; 413 414 /* Table 2170 - Flow Table Fields Supported 2 Format */ 415 struct mlx5_ifc_flow_table_fields_supported_2_bits { 416 u8 reserved_at_0[0xe]; 417 u8 bth_opcode[0x1]; 418 u8 reserved_at_f[0x1]; 419 u8 tunnel_header_0_1[0x1]; 420 u8 reserved_at_11[0xf]; 421 422 u8 reserved_at_20[0x60]; 423 }; 424 425 struct mlx5_ifc_flow_table_prop_layout_bits { 426 u8 ft_support[0x1]; 427 u8 reserved_at_1[0x1]; 428 u8 flow_counter[0x1]; 429 u8 flow_modify_en[0x1]; 430 u8 modify_root[0x1]; 431 u8 identified_miss_table_mode[0x1]; 432 u8 flow_table_modify[0x1]; 433 u8 reformat[0x1]; 434 u8 decap[0x1]; 435 u8 reserved_at_9[0x1]; 436 u8 pop_vlan[0x1]; 437 u8 push_vlan[0x1]; 438 u8 reserved_at_c[0x1]; 439 u8 pop_vlan_2[0x1]; 440 u8 push_vlan_2[0x1]; 441 u8 reformat_and_vlan_action[0x1]; 442 u8 reserved_at_10[0x1]; 443 u8 sw_owner[0x1]; 444 u8 reformat_l3_tunnel_to_l2[0x1]; 445 u8 reformat_l2_to_l3_tunnel[0x1]; 446 u8 reformat_and_modify_action[0x1]; 447 u8 ignore_flow_level[0x1]; 448 u8 reserved_at_16[0x1]; 449 u8 table_miss_action_domain[0x1]; 450 u8 termination_table[0x1]; 451 u8 reformat_and_fwd_to_table[0x1]; 452 u8 reserved_at_1a[0x2]; 453 u8 ipsec_encrypt[0x1]; 454 u8 ipsec_decrypt[0x1]; 455 u8 sw_owner_v2[0x1]; 456 u8 reserved_at_1f[0x1]; 457 458 u8 termination_table_raw_traffic[0x1]; 459 u8 reserved_at_21[0x1]; 460 u8 log_max_ft_size[0x6]; 461 u8 log_max_modify_header_context[0x8]; 462 u8 max_modify_header_actions[0x8]; 463 u8 max_ft_level[0x8]; 464 465 u8 reformat_add_esp_trasport[0x1]; 466 u8 reformat_l2_to_l3_esp_tunnel[0x1]; 467 u8 reserved_at_42[0x1]; 468 u8 reformat_del_esp_trasport[0x1]; 469 u8 reformat_l3_esp_tunnel_to_l2[0x1]; 470 u8 reserved_at_45[0x1]; 471 u8 execute_aso[0x1]; 472 u8 reserved_at_47[0x19]; 473 474 u8 reserved_at_60[0x2]; 475 u8 reformat_insert[0x1]; 476 u8 reformat_remove[0x1]; 477 u8 macsec_encrypt[0x1]; 478 u8 macsec_decrypt[0x1]; 479 u8 reserved_at_66[0x2]; 480 u8 reformat_add_macsec[0x1]; 481 u8 reformat_remove_macsec[0x1]; 482 u8 reserved_at_6a[0xe]; 483 u8 log_max_ft_num[0x8]; 484 485 u8 reserved_at_80[0x10]; 486 u8 log_max_flow_counter[0x8]; 487 u8 log_max_destination[0x8]; 488 489 u8 reserved_at_a0[0x18]; 490 u8 log_max_flow[0x8]; 491 492 u8 reserved_at_c0[0x40]; 493 494 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support; 495 496 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support; 497 }; 498 499 struct mlx5_ifc_odp_per_transport_service_cap_bits { 500 u8 send[0x1]; 501 u8 receive[0x1]; 502 u8 write[0x1]; 503 u8 read[0x1]; 504 u8 atomic[0x1]; 505 u8 srq_receive[0x1]; 506 u8 reserved_at_6[0x1a]; 507 }; 508 509 struct mlx5_ifc_ipv4_layout_bits { 510 u8 reserved_at_0[0x60]; 511 512 u8 ipv4[0x20]; 513 }; 514 515 struct mlx5_ifc_ipv6_layout_bits { 516 u8 ipv6[16][0x8]; 517 }; 518 519 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits { 520 struct mlx5_ifc_ipv6_layout_bits ipv6_layout; 521 struct mlx5_ifc_ipv4_layout_bits ipv4_layout; 522 u8 reserved_at_0[0x80]; 523 }; 524 525 struct mlx5_ifc_fte_match_set_lyr_2_4_bits { 526 u8 smac_47_16[0x20]; 527 528 u8 smac_15_0[0x10]; 529 u8 ethertype[0x10]; 530 531 u8 dmac_47_16[0x20]; 532 533 u8 dmac_15_0[0x10]; 534 u8 first_prio[0x3]; 535 u8 first_cfi[0x1]; 536 u8 first_vid[0xc]; 537 538 u8 ip_protocol[0x8]; 539 u8 ip_dscp[0x6]; 540 u8 ip_ecn[0x2]; 541 u8 cvlan_tag[0x1]; 542 u8 svlan_tag[0x1]; 543 u8 frag[0x1]; 544 u8 ip_version[0x4]; 545 u8 tcp_flags[0x9]; 546 547 u8 tcp_sport[0x10]; 548 u8 tcp_dport[0x10]; 549 550 u8 reserved_at_c0[0x10]; 551 u8 ipv4_ihl[0x4]; 552 u8 reserved_at_c4[0x4]; 553 554 u8 ttl_hoplimit[0x8]; 555 556 u8 udp_sport[0x10]; 557 u8 udp_dport[0x10]; 558 559 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6; 560 561 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6; 562 }; 563 564 struct mlx5_ifc_nvgre_key_bits { 565 u8 hi[0x18]; 566 u8 lo[0x8]; 567 }; 568 569 union mlx5_ifc_gre_key_bits { 570 struct mlx5_ifc_nvgre_key_bits nvgre; 571 u8 key[0x20]; 572 }; 573 574 struct mlx5_ifc_fte_match_set_misc_bits { 575 u8 gre_c_present[0x1]; 576 u8 reserved_at_1[0x1]; 577 u8 gre_k_present[0x1]; 578 u8 gre_s_present[0x1]; 579 u8 source_vhca_port[0x4]; 580 u8 source_sqn[0x18]; 581 582 u8 source_eswitch_owner_vhca_id[0x10]; 583 u8 source_port[0x10]; 584 585 u8 outer_second_prio[0x3]; 586 u8 outer_second_cfi[0x1]; 587 u8 outer_second_vid[0xc]; 588 u8 inner_second_prio[0x3]; 589 u8 inner_second_cfi[0x1]; 590 u8 inner_second_vid[0xc]; 591 592 u8 outer_second_cvlan_tag[0x1]; 593 u8 inner_second_cvlan_tag[0x1]; 594 u8 outer_second_svlan_tag[0x1]; 595 u8 inner_second_svlan_tag[0x1]; 596 u8 reserved_at_64[0xc]; 597 u8 gre_protocol[0x10]; 598 599 union mlx5_ifc_gre_key_bits gre_key; 600 601 u8 vxlan_vni[0x18]; 602 u8 bth_opcode[0x8]; 603 604 u8 geneve_vni[0x18]; 605 u8 reserved_at_d8[0x6]; 606 u8 geneve_tlv_option_0_exist[0x1]; 607 u8 geneve_oam[0x1]; 608 609 u8 reserved_at_e0[0xc]; 610 u8 outer_ipv6_flow_label[0x14]; 611 612 u8 reserved_at_100[0xc]; 613 u8 inner_ipv6_flow_label[0x14]; 614 615 u8 reserved_at_120[0xa]; 616 u8 geneve_opt_len[0x6]; 617 u8 geneve_protocol_type[0x10]; 618 619 u8 reserved_at_140[0x8]; 620 u8 bth_dst_qp[0x18]; 621 u8 reserved_at_160[0x20]; 622 u8 outer_esp_spi[0x20]; 623 u8 reserved_at_1a0[0x60]; 624 }; 625 626 struct mlx5_ifc_fte_match_mpls_bits { 627 u8 mpls_label[0x14]; 628 u8 mpls_exp[0x3]; 629 u8 mpls_s_bos[0x1]; 630 u8 mpls_ttl[0x8]; 631 }; 632 633 struct mlx5_ifc_fte_match_set_misc2_bits { 634 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls; 635 636 struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls; 637 638 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre; 639 640 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp; 641 642 u8 metadata_reg_c_7[0x20]; 643 644 u8 metadata_reg_c_6[0x20]; 645 646 u8 metadata_reg_c_5[0x20]; 647 648 u8 metadata_reg_c_4[0x20]; 649 650 u8 metadata_reg_c_3[0x20]; 651 652 u8 metadata_reg_c_2[0x20]; 653 654 u8 metadata_reg_c_1[0x20]; 655 656 u8 metadata_reg_c_0[0x20]; 657 658 u8 metadata_reg_a[0x20]; 659 660 u8 reserved_at_1a0[0x8]; 661 662 u8 macsec_syndrome[0x8]; 663 u8 ipsec_syndrome[0x8]; 664 u8 reserved_at_1b8[0x8]; 665 666 u8 reserved_at_1c0[0x40]; 667 }; 668 669 struct mlx5_ifc_fte_match_set_misc3_bits { 670 u8 inner_tcp_seq_num[0x20]; 671 672 u8 outer_tcp_seq_num[0x20]; 673 674 u8 inner_tcp_ack_num[0x20]; 675 676 u8 outer_tcp_ack_num[0x20]; 677 678 u8 reserved_at_80[0x8]; 679 u8 outer_vxlan_gpe_vni[0x18]; 680 681 u8 outer_vxlan_gpe_next_protocol[0x8]; 682 u8 outer_vxlan_gpe_flags[0x8]; 683 u8 reserved_at_b0[0x10]; 684 685 u8 icmp_header_data[0x20]; 686 687 u8 icmpv6_header_data[0x20]; 688 689 u8 icmp_type[0x8]; 690 u8 icmp_code[0x8]; 691 u8 icmpv6_type[0x8]; 692 u8 icmpv6_code[0x8]; 693 694 u8 geneve_tlv_option_0_data[0x20]; 695 696 u8 gtpu_teid[0x20]; 697 698 u8 gtpu_msg_type[0x8]; 699 u8 gtpu_msg_flags[0x8]; 700 u8 reserved_at_170[0x10]; 701 702 u8 gtpu_dw_2[0x20]; 703 704 u8 gtpu_first_ext_dw_0[0x20]; 705 706 u8 gtpu_dw_0[0x20]; 707 708 u8 reserved_at_1e0[0x20]; 709 }; 710 711 struct mlx5_ifc_fte_match_set_misc4_bits { 712 u8 prog_sample_field_value_0[0x20]; 713 714 u8 prog_sample_field_id_0[0x20]; 715 716 u8 prog_sample_field_value_1[0x20]; 717 718 u8 prog_sample_field_id_1[0x20]; 719 720 u8 prog_sample_field_value_2[0x20]; 721 722 u8 prog_sample_field_id_2[0x20]; 723 724 u8 prog_sample_field_value_3[0x20]; 725 726 u8 prog_sample_field_id_3[0x20]; 727 728 u8 reserved_at_100[0x100]; 729 }; 730 731 struct mlx5_ifc_fte_match_set_misc5_bits { 732 u8 macsec_tag_0[0x20]; 733 734 u8 macsec_tag_1[0x20]; 735 736 u8 macsec_tag_2[0x20]; 737 738 u8 macsec_tag_3[0x20]; 739 740 u8 tunnel_header_0[0x20]; 741 742 u8 tunnel_header_1[0x20]; 743 744 u8 tunnel_header_2[0x20]; 745 746 u8 tunnel_header_3[0x20]; 747 748 u8 reserved_at_100[0x100]; 749 }; 750 751 struct mlx5_ifc_cmd_pas_bits { 752 u8 pa_h[0x20]; 753 754 u8 pa_l[0x14]; 755 u8 reserved_at_34[0xc]; 756 }; 757 758 struct mlx5_ifc_uint64_bits { 759 u8 hi[0x20]; 760 761 u8 lo[0x20]; 762 }; 763 764 enum { 765 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0, 766 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7, 767 MLX5_ADS_STAT_RATE_10GBPS = 0x8, 768 MLX5_ADS_STAT_RATE_30GBPS = 0x9, 769 MLX5_ADS_STAT_RATE_5GBPS = 0xa, 770 MLX5_ADS_STAT_RATE_20GBPS = 0xb, 771 MLX5_ADS_STAT_RATE_40GBPS = 0xc, 772 MLX5_ADS_STAT_RATE_60GBPS = 0xd, 773 MLX5_ADS_STAT_RATE_80GBPS = 0xe, 774 MLX5_ADS_STAT_RATE_120GBPS = 0xf, 775 }; 776 777 struct mlx5_ifc_ads_bits { 778 u8 fl[0x1]; 779 u8 free_ar[0x1]; 780 u8 reserved_at_2[0xe]; 781 u8 pkey_index[0x10]; 782 783 u8 reserved_at_20[0x8]; 784 u8 grh[0x1]; 785 u8 mlid[0x7]; 786 u8 rlid[0x10]; 787 788 u8 ack_timeout[0x5]; 789 u8 reserved_at_45[0x3]; 790 u8 src_addr_index[0x8]; 791 u8 reserved_at_50[0x4]; 792 u8 stat_rate[0x4]; 793 u8 hop_limit[0x8]; 794 795 u8 reserved_at_60[0x4]; 796 u8 tclass[0x8]; 797 u8 flow_label[0x14]; 798 799 u8 rgid_rip[16][0x8]; 800 801 u8 reserved_at_100[0x4]; 802 u8 f_dscp[0x1]; 803 u8 f_ecn[0x1]; 804 u8 reserved_at_106[0x1]; 805 u8 f_eth_prio[0x1]; 806 u8 ecn[0x2]; 807 u8 dscp[0x6]; 808 u8 udp_sport[0x10]; 809 810 u8 dei_cfi[0x1]; 811 u8 eth_prio[0x3]; 812 u8 sl[0x4]; 813 u8 vhca_port_num[0x8]; 814 u8 rmac_47_32[0x10]; 815 816 u8 rmac_31_0[0x20]; 817 }; 818 819 struct mlx5_ifc_flow_table_nic_cap_bits { 820 u8 nic_rx_multi_path_tirs[0x1]; 821 u8 nic_rx_multi_path_tirs_fts[0x1]; 822 u8 allow_sniffer_and_nic_rx_shared_tir[0x1]; 823 u8 reserved_at_3[0x4]; 824 u8 sw_owner_reformat_supported[0x1]; 825 u8 reserved_at_8[0x18]; 826 827 u8 encap_general_header[0x1]; 828 u8 reserved_at_21[0xa]; 829 u8 log_max_packet_reformat_context[0x5]; 830 u8 reserved_at_30[0x6]; 831 u8 max_encap_header_size[0xa]; 832 u8 reserved_at_40[0x1c0]; 833 834 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive; 835 836 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_rdma; 837 838 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer; 839 840 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit; 841 842 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_rdma; 843 844 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer; 845 846 u8 reserved_at_e00[0x700]; 847 848 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_receive_rdma; 849 850 u8 reserved_at_1580[0x280]; 851 852 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_transmit_rdma; 853 854 u8 reserved_at_1880[0x780]; 855 856 u8 sw_steering_nic_rx_action_drop_icm_address[0x40]; 857 858 u8 sw_steering_nic_tx_action_drop_icm_address[0x40]; 859 860 u8 sw_steering_nic_tx_action_allow_icm_address[0x40]; 861 862 u8 reserved_at_20c0[0x5f40]; 863 }; 864 865 struct mlx5_ifc_port_selection_cap_bits { 866 u8 reserved_at_0[0x10]; 867 u8 port_select_flow_table[0x1]; 868 u8 reserved_at_11[0x1]; 869 u8 port_select_flow_table_bypass[0x1]; 870 u8 reserved_at_13[0xd]; 871 872 u8 reserved_at_20[0x1e0]; 873 874 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_port_selection; 875 876 u8 reserved_at_400[0x7c00]; 877 }; 878 879 enum { 880 MLX5_FDB_TO_VPORT_REG_C_0 = 0x01, 881 MLX5_FDB_TO_VPORT_REG_C_1 = 0x02, 882 MLX5_FDB_TO_VPORT_REG_C_2 = 0x04, 883 MLX5_FDB_TO_VPORT_REG_C_3 = 0x08, 884 MLX5_FDB_TO_VPORT_REG_C_4 = 0x10, 885 MLX5_FDB_TO_VPORT_REG_C_5 = 0x20, 886 MLX5_FDB_TO_VPORT_REG_C_6 = 0x40, 887 MLX5_FDB_TO_VPORT_REG_C_7 = 0x80, 888 }; 889 890 struct mlx5_ifc_flow_table_eswitch_cap_bits { 891 u8 fdb_to_vport_reg_c_id[0x8]; 892 u8 reserved_at_8[0x5]; 893 u8 fdb_uplink_hairpin[0x1]; 894 u8 fdb_multi_path_any_table_limit_regc[0x1]; 895 u8 reserved_at_f[0x3]; 896 u8 fdb_multi_path_any_table[0x1]; 897 u8 reserved_at_13[0x2]; 898 u8 fdb_modify_header_fwd_to_table[0x1]; 899 u8 fdb_ipv4_ttl_modify[0x1]; 900 u8 flow_source[0x1]; 901 u8 reserved_at_18[0x2]; 902 u8 multi_fdb_encap[0x1]; 903 u8 egress_acl_forward_to_vport[0x1]; 904 u8 fdb_multi_path_to_table[0x1]; 905 u8 reserved_at_1d[0x3]; 906 907 u8 reserved_at_20[0x1e0]; 908 909 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb; 910 911 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress; 912 913 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress; 914 915 u8 reserved_at_800[0xC00]; 916 917 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_esw_fdb; 918 919 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_bitmask_support_2_esw_fdb; 920 921 u8 reserved_at_1500[0x300]; 922 923 u8 sw_steering_fdb_action_drop_icm_address_rx[0x40]; 924 925 u8 sw_steering_fdb_action_drop_icm_address_tx[0x40]; 926 927 u8 sw_steering_uplink_icm_address_rx[0x40]; 928 929 u8 sw_steering_uplink_icm_address_tx[0x40]; 930 931 u8 reserved_at_1900[0x6700]; 932 }; 933 934 enum { 935 MLX5_COUNTER_SOURCE_ESWITCH = 0x0, 936 MLX5_COUNTER_FLOW_ESWITCH = 0x1, 937 }; 938 939 struct mlx5_ifc_e_switch_cap_bits { 940 u8 vport_svlan_strip[0x1]; 941 u8 vport_cvlan_strip[0x1]; 942 u8 vport_svlan_insert[0x1]; 943 u8 vport_cvlan_insert_if_not_exist[0x1]; 944 u8 vport_cvlan_insert_overwrite[0x1]; 945 u8 reserved_at_5[0x1]; 946 u8 vport_cvlan_insert_always[0x1]; 947 u8 esw_shared_ingress_acl[0x1]; 948 u8 esw_uplink_ingress_acl[0x1]; 949 u8 root_ft_on_other_esw[0x1]; 950 u8 reserved_at_a[0xf]; 951 u8 esw_functions_changed[0x1]; 952 u8 reserved_at_1a[0x1]; 953 u8 ecpf_vport_exists[0x1]; 954 u8 counter_eswitch_affinity[0x1]; 955 u8 merged_eswitch[0x1]; 956 u8 nic_vport_node_guid_modify[0x1]; 957 u8 nic_vport_port_guid_modify[0x1]; 958 959 u8 vxlan_encap_decap[0x1]; 960 u8 nvgre_encap_decap[0x1]; 961 u8 reserved_at_22[0x1]; 962 u8 log_max_fdb_encap_uplink[0x5]; 963 u8 reserved_at_21[0x3]; 964 u8 log_max_packet_reformat_context[0x5]; 965 u8 reserved_2b[0x6]; 966 u8 max_encap_header_size[0xa]; 967 968 u8 reserved_at_40[0xb]; 969 u8 log_max_esw_sf[0x5]; 970 u8 esw_sf_base_id[0x10]; 971 972 u8 reserved_at_60[0x7a0]; 973 974 }; 975 976 struct mlx5_ifc_qos_cap_bits { 977 u8 packet_pacing[0x1]; 978 u8 esw_scheduling[0x1]; 979 u8 esw_bw_share[0x1]; 980 u8 esw_rate_limit[0x1]; 981 u8 reserved_at_4[0x1]; 982 u8 packet_pacing_burst_bound[0x1]; 983 u8 packet_pacing_typical_size[0x1]; 984 u8 reserved_at_7[0x1]; 985 u8 nic_sq_scheduling[0x1]; 986 u8 nic_bw_share[0x1]; 987 u8 nic_rate_limit[0x1]; 988 u8 packet_pacing_uid[0x1]; 989 u8 log_esw_max_sched_depth[0x4]; 990 u8 reserved_at_10[0x10]; 991 992 u8 reserved_at_20[0xb]; 993 u8 log_max_qos_nic_queue_group[0x5]; 994 u8 reserved_at_30[0x10]; 995 996 u8 packet_pacing_max_rate[0x20]; 997 998 u8 packet_pacing_min_rate[0x20]; 999 1000 u8 reserved_at_80[0x10]; 1001 u8 packet_pacing_rate_table_size[0x10]; 1002 1003 u8 esw_element_type[0x10]; 1004 u8 esw_tsar_type[0x10]; 1005 1006 u8 reserved_at_c0[0x10]; 1007 u8 max_qos_para_vport[0x10]; 1008 1009 u8 max_tsar_bw_share[0x20]; 1010 1011 u8 reserved_at_100[0x20]; 1012 1013 u8 reserved_at_120[0x3]; 1014 u8 log_meter_aso_granularity[0x5]; 1015 u8 reserved_at_128[0x3]; 1016 u8 log_meter_aso_max_alloc[0x5]; 1017 u8 reserved_at_130[0x3]; 1018 u8 log_max_num_meter_aso[0x5]; 1019 u8 reserved_at_138[0x8]; 1020 1021 u8 reserved_at_140[0x6c0]; 1022 }; 1023 1024 struct mlx5_ifc_debug_cap_bits { 1025 u8 core_dump_general[0x1]; 1026 u8 core_dump_qp[0x1]; 1027 u8 reserved_at_2[0x7]; 1028 u8 resource_dump[0x1]; 1029 u8 reserved_at_a[0x16]; 1030 1031 u8 reserved_at_20[0x2]; 1032 u8 stall_detect[0x1]; 1033 u8 reserved_at_23[0x1d]; 1034 1035 u8 reserved_at_40[0x7c0]; 1036 }; 1037 1038 struct mlx5_ifc_per_protocol_networking_offload_caps_bits { 1039 u8 csum_cap[0x1]; 1040 u8 vlan_cap[0x1]; 1041 u8 lro_cap[0x1]; 1042 u8 lro_psh_flag[0x1]; 1043 u8 lro_time_stamp[0x1]; 1044 u8 reserved_at_5[0x2]; 1045 u8 wqe_vlan_insert[0x1]; 1046 u8 self_lb_en_modifiable[0x1]; 1047 u8 reserved_at_9[0x2]; 1048 u8 max_lso_cap[0x5]; 1049 u8 multi_pkt_send_wqe[0x2]; 1050 u8 wqe_inline_mode[0x2]; 1051 u8 rss_ind_tbl_cap[0x4]; 1052 u8 reg_umr_sq[0x1]; 1053 u8 scatter_fcs[0x1]; 1054 u8 enhanced_multi_pkt_send_wqe[0x1]; 1055 u8 tunnel_lso_const_out_ip_id[0x1]; 1056 u8 tunnel_lro_gre[0x1]; 1057 u8 tunnel_lro_vxlan[0x1]; 1058 u8 tunnel_stateless_gre[0x1]; 1059 u8 tunnel_stateless_vxlan[0x1]; 1060 1061 u8 swp[0x1]; 1062 u8 swp_csum[0x1]; 1063 u8 swp_lso[0x1]; 1064 u8 cqe_checksum_full[0x1]; 1065 u8 tunnel_stateless_geneve_tx[0x1]; 1066 u8 tunnel_stateless_mpls_over_udp[0x1]; 1067 u8 tunnel_stateless_mpls_over_gre[0x1]; 1068 u8 tunnel_stateless_vxlan_gpe[0x1]; 1069 u8 tunnel_stateless_ipv4_over_vxlan[0x1]; 1070 u8 tunnel_stateless_ip_over_ip[0x1]; 1071 u8 insert_trailer[0x1]; 1072 u8 reserved_at_2b[0x1]; 1073 u8 tunnel_stateless_ip_over_ip_rx[0x1]; 1074 u8 tunnel_stateless_ip_over_ip_tx[0x1]; 1075 u8 reserved_at_2e[0x2]; 1076 u8 max_vxlan_udp_ports[0x8]; 1077 u8 reserved_at_38[0x6]; 1078 u8 max_geneve_opt_len[0x1]; 1079 u8 tunnel_stateless_geneve_rx[0x1]; 1080 1081 u8 reserved_at_40[0x10]; 1082 u8 lro_min_mss_size[0x10]; 1083 1084 u8 reserved_at_60[0x120]; 1085 1086 u8 lro_timer_supported_periods[4][0x20]; 1087 1088 u8 reserved_at_200[0x600]; 1089 }; 1090 1091 enum { 1092 MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING = 0x0, 1093 MLX5_TIMESTAMP_FORMAT_CAP_REAL_TIME = 0x1, 1094 MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING_AND_REAL_TIME = 0x2, 1095 }; 1096 1097 struct mlx5_ifc_roce_cap_bits { 1098 u8 roce_apm[0x1]; 1099 u8 reserved_at_1[0x3]; 1100 u8 sw_r_roce_src_udp_port[0x1]; 1101 u8 fl_rc_qp_when_roce_disabled[0x1]; 1102 u8 fl_rc_qp_when_roce_enabled[0x1]; 1103 u8 reserved_at_7[0x17]; 1104 u8 qp_ts_format[0x2]; 1105 1106 u8 reserved_at_20[0x60]; 1107 1108 u8 reserved_at_80[0xc]; 1109 u8 l3_type[0x4]; 1110 u8 reserved_at_90[0x8]; 1111 u8 roce_version[0x8]; 1112 1113 u8 reserved_at_a0[0x10]; 1114 u8 r_roce_dest_udp_port[0x10]; 1115 1116 u8 r_roce_max_src_udp_port[0x10]; 1117 u8 r_roce_min_src_udp_port[0x10]; 1118 1119 u8 reserved_at_e0[0x10]; 1120 u8 roce_address_table_size[0x10]; 1121 1122 u8 reserved_at_100[0x700]; 1123 }; 1124 1125 struct mlx5_ifc_sync_steering_in_bits { 1126 u8 opcode[0x10]; 1127 u8 uid[0x10]; 1128 1129 u8 reserved_at_20[0x10]; 1130 u8 op_mod[0x10]; 1131 1132 u8 reserved_at_40[0xc0]; 1133 }; 1134 1135 struct mlx5_ifc_sync_steering_out_bits { 1136 u8 status[0x8]; 1137 u8 reserved_at_8[0x18]; 1138 1139 u8 syndrome[0x20]; 1140 1141 u8 reserved_at_40[0x40]; 1142 }; 1143 1144 struct mlx5_ifc_sync_crypto_in_bits { 1145 u8 opcode[0x10]; 1146 u8 uid[0x10]; 1147 1148 u8 reserved_at_20[0x10]; 1149 u8 op_mod[0x10]; 1150 1151 u8 reserved_at_40[0x20]; 1152 1153 u8 reserved_at_60[0x10]; 1154 u8 crypto_type[0x10]; 1155 1156 u8 reserved_at_80[0x80]; 1157 }; 1158 1159 struct mlx5_ifc_sync_crypto_out_bits { 1160 u8 status[0x8]; 1161 u8 reserved_at_8[0x18]; 1162 1163 u8 syndrome[0x20]; 1164 1165 u8 reserved_at_40[0x40]; 1166 }; 1167 1168 struct mlx5_ifc_device_mem_cap_bits { 1169 u8 memic[0x1]; 1170 u8 reserved_at_1[0x1f]; 1171 1172 u8 reserved_at_20[0xb]; 1173 u8 log_min_memic_alloc_size[0x5]; 1174 u8 reserved_at_30[0x8]; 1175 u8 log_max_memic_addr_alignment[0x8]; 1176 1177 u8 memic_bar_start_addr[0x40]; 1178 1179 u8 memic_bar_size[0x20]; 1180 1181 u8 max_memic_size[0x20]; 1182 1183 u8 steering_sw_icm_start_address[0x40]; 1184 1185 u8 reserved_at_100[0x8]; 1186 u8 log_header_modify_sw_icm_size[0x8]; 1187 u8 reserved_at_110[0x2]; 1188 u8 log_sw_icm_alloc_granularity[0x6]; 1189 u8 log_steering_sw_icm_size[0x8]; 1190 1191 u8 reserved_at_120[0x18]; 1192 u8 log_header_modify_pattern_sw_icm_size[0x8]; 1193 1194 u8 header_modify_sw_icm_start_address[0x40]; 1195 1196 u8 reserved_at_180[0x40]; 1197 1198 u8 header_modify_pattern_sw_icm_start_address[0x40]; 1199 1200 u8 memic_operations[0x20]; 1201 1202 u8 reserved_at_220[0x5e0]; 1203 }; 1204 1205 struct mlx5_ifc_device_event_cap_bits { 1206 u8 user_affiliated_events[4][0x40]; 1207 1208 u8 user_unaffiliated_events[4][0x40]; 1209 }; 1210 1211 struct mlx5_ifc_virtio_emulation_cap_bits { 1212 u8 desc_tunnel_offload_type[0x1]; 1213 u8 eth_frame_offload_type[0x1]; 1214 u8 virtio_version_1_0[0x1]; 1215 u8 device_features_bits_mask[0xd]; 1216 u8 event_mode[0x8]; 1217 u8 virtio_queue_type[0x8]; 1218 1219 u8 max_tunnel_desc[0x10]; 1220 u8 reserved_at_30[0x3]; 1221 u8 log_doorbell_stride[0x5]; 1222 u8 reserved_at_38[0x3]; 1223 u8 log_doorbell_bar_size[0x5]; 1224 1225 u8 doorbell_bar_offset[0x40]; 1226 1227 u8 max_emulated_devices[0x8]; 1228 u8 max_num_virtio_queues[0x18]; 1229 1230 u8 reserved_at_a0[0x60]; 1231 1232 u8 umem_1_buffer_param_a[0x20]; 1233 1234 u8 umem_1_buffer_param_b[0x20]; 1235 1236 u8 umem_2_buffer_param_a[0x20]; 1237 1238 u8 umem_2_buffer_param_b[0x20]; 1239 1240 u8 umem_3_buffer_param_a[0x20]; 1241 1242 u8 umem_3_buffer_param_b[0x20]; 1243 1244 u8 reserved_at_1c0[0x640]; 1245 }; 1246 1247 enum { 1248 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0, 1249 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2, 1250 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4, 1251 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8, 1252 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10, 1253 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20, 1254 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40, 1255 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80, 1256 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100, 1257 }; 1258 1259 enum { 1260 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1, 1261 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2, 1262 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4, 1263 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8, 1264 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10, 1265 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20, 1266 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40, 1267 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80, 1268 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100, 1269 }; 1270 1271 struct mlx5_ifc_atomic_caps_bits { 1272 u8 reserved_at_0[0x40]; 1273 1274 u8 atomic_req_8B_endianness_mode[0x2]; 1275 u8 reserved_at_42[0x4]; 1276 u8 supported_atomic_req_8B_endianness_mode_1[0x1]; 1277 1278 u8 reserved_at_47[0x19]; 1279 1280 u8 reserved_at_60[0x20]; 1281 1282 u8 reserved_at_80[0x10]; 1283 u8 atomic_operations[0x10]; 1284 1285 u8 reserved_at_a0[0x10]; 1286 u8 atomic_size_qp[0x10]; 1287 1288 u8 reserved_at_c0[0x10]; 1289 u8 atomic_size_dc[0x10]; 1290 1291 u8 reserved_at_e0[0x720]; 1292 }; 1293 1294 struct mlx5_ifc_odp_cap_bits { 1295 u8 reserved_at_0[0x40]; 1296 1297 u8 sig[0x1]; 1298 u8 reserved_at_41[0x1f]; 1299 1300 u8 reserved_at_60[0x20]; 1301 1302 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps; 1303 1304 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps; 1305 1306 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps; 1307 1308 struct mlx5_ifc_odp_per_transport_service_cap_bits xrc_odp_caps; 1309 1310 struct mlx5_ifc_odp_per_transport_service_cap_bits dc_odp_caps; 1311 1312 u8 reserved_at_120[0x6E0]; 1313 }; 1314 1315 struct mlx5_ifc_calc_op { 1316 u8 reserved_at_0[0x10]; 1317 u8 reserved_at_10[0x9]; 1318 u8 op_swap_endianness[0x1]; 1319 u8 op_min[0x1]; 1320 u8 op_xor[0x1]; 1321 u8 op_or[0x1]; 1322 u8 op_and[0x1]; 1323 u8 op_max[0x1]; 1324 u8 op_add[0x1]; 1325 }; 1326 1327 struct mlx5_ifc_vector_calc_cap_bits { 1328 u8 calc_matrix[0x1]; 1329 u8 reserved_at_1[0x1f]; 1330 u8 reserved_at_20[0x8]; 1331 u8 max_vec_count[0x8]; 1332 u8 reserved_at_30[0xd]; 1333 u8 max_chunk_size[0x3]; 1334 struct mlx5_ifc_calc_op calc0; 1335 struct mlx5_ifc_calc_op calc1; 1336 struct mlx5_ifc_calc_op calc2; 1337 struct mlx5_ifc_calc_op calc3; 1338 1339 u8 reserved_at_c0[0x720]; 1340 }; 1341 1342 struct mlx5_ifc_tls_cap_bits { 1343 u8 tls_1_2_aes_gcm_128[0x1]; 1344 u8 tls_1_3_aes_gcm_128[0x1]; 1345 u8 tls_1_2_aes_gcm_256[0x1]; 1346 u8 tls_1_3_aes_gcm_256[0x1]; 1347 u8 reserved_at_4[0x1c]; 1348 1349 u8 reserved_at_20[0x7e0]; 1350 }; 1351 1352 struct mlx5_ifc_ipsec_cap_bits { 1353 u8 ipsec_full_offload[0x1]; 1354 u8 ipsec_crypto_offload[0x1]; 1355 u8 ipsec_esn[0x1]; 1356 u8 ipsec_crypto_esp_aes_gcm_256_encrypt[0x1]; 1357 u8 ipsec_crypto_esp_aes_gcm_128_encrypt[0x1]; 1358 u8 ipsec_crypto_esp_aes_gcm_256_decrypt[0x1]; 1359 u8 ipsec_crypto_esp_aes_gcm_128_decrypt[0x1]; 1360 u8 reserved_at_7[0x4]; 1361 u8 log_max_ipsec_offload[0x5]; 1362 u8 reserved_at_10[0x10]; 1363 1364 u8 min_log_ipsec_full_replay_window[0x8]; 1365 u8 max_log_ipsec_full_replay_window[0x8]; 1366 u8 reserved_at_30[0x7d0]; 1367 }; 1368 1369 struct mlx5_ifc_macsec_cap_bits { 1370 u8 macsec_epn[0x1]; 1371 u8 reserved_at_1[0x2]; 1372 u8 macsec_crypto_esp_aes_gcm_256_encrypt[0x1]; 1373 u8 macsec_crypto_esp_aes_gcm_128_encrypt[0x1]; 1374 u8 macsec_crypto_esp_aes_gcm_256_decrypt[0x1]; 1375 u8 macsec_crypto_esp_aes_gcm_128_decrypt[0x1]; 1376 u8 reserved_at_7[0x4]; 1377 u8 log_max_macsec_offload[0x5]; 1378 u8 reserved_at_10[0x10]; 1379 1380 u8 min_log_macsec_full_replay_window[0x8]; 1381 u8 max_log_macsec_full_replay_window[0x8]; 1382 u8 reserved_at_30[0x10]; 1383 1384 u8 reserved_at_40[0x7c0]; 1385 }; 1386 1387 enum { 1388 MLX5_WQ_TYPE_LINKED_LIST = 0x0, 1389 MLX5_WQ_TYPE_CYCLIC = 0x1, 1390 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2, 1391 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3, 1392 }; 1393 1394 enum { 1395 MLX5_WQ_END_PAD_MODE_NONE = 0x0, 1396 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1, 1397 }; 1398 1399 enum { 1400 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0, 1401 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1, 1402 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2, 1403 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3, 1404 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4, 1405 }; 1406 1407 enum { 1408 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0, 1409 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1, 1410 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2, 1411 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3, 1412 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4, 1413 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5, 1414 }; 1415 1416 enum { 1417 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0, 1418 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1, 1419 }; 1420 1421 enum { 1422 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0, 1423 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1, 1424 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3, 1425 }; 1426 1427 enum { 1428 MLX5_CAP_PORT_TYPE_IB = 0x0, 1429 MLX5_CAP_PORT_TYPE_ETH = 0x1, 1430 }; 1431 1432 enum { 1433 MLX5_CAP_UMR_FENCE_STRONG = 0x0, 1434 MLX5_CAP_UMR_FENCE_SMALL = 0x1, 1435 MLX5_CAP_UMR_FENCE_NONE = 0x2, 1436 }; 1437 1438 enum { 1439 MLX5_FLEX_PARSER_GENEVE_ENABLED = 1 << 3, 1440 MLX5_FLEX_PARSER_MPLS_OVER_GRE_ENABLED = 1 << 4, 1441 MLX5_FLEX_PARSER_MPLS_OVER_UDP_ENABLED = 1 << 5, 1442 MLX5_FLEX_PARSER_VXLAN_GPE_ENABLED = 1 << 7, 1443 MLX5_FLEX_PARSER_ICMP_V4_ENABLED = 1 << 8, 1444 MLX5_FLEX_PARSER_ICMP_V6_ENABLED = 1 << 9, 1445 MLX5_FLEX_PARSER_GENEVE_TLV_OPTION_0_ENABLED = 1 << 10, 1446 MLX5_FLEX_PARSER_GTPU_ENABLED = 1 << 11, 1447 MLX5_FLEX_PARSER_GTPU_DW_2_ENABLED = 1 << 16, 1448 MLX5_FLEX_PARSER_GTPU_FIRST_EXT_DW_0_ENABLED = 1 << 17, 1449 MLX5_FLEX_PARSER_GTPU_DW_0_ENABLED = 1 << 18, 1450 MLX5_FLEX_PARSER_GTPU_TEID_ENABLED = 1 << 19, 1451 }; 1452 1453 enum { 1454 MLX5_UCTX_CAP_RAW_TX = 1UL << 0, 1455 MLX5_UCTX_CAP_INTERNAL_DEV_RES = 1UL << 1, 1456 }; 1457 1458 #define MLX5_FC_BULK_SIZE_FACTOR 128 1459 1460 enum mlx5_fc_bulk_alloc_bitmask { 1461 MLX5_FC_BULK_128 = (1 << 0), 1462 MLX5_FC_BULK_256 = (1 << 1), 1463 MLX5_FC_BULK_512 = (1 << 2), 1464 MLX5_FC_BULK_1024 = (1 << 3), 1465 MLX5_FC_BULK_2048 = (1 << 4), 1466 MLX5_FC_BULK_4096 = (1 << 5), 1467 MLX5_FC_BULK_8192 = (1 << 6), 1468 MLX5_FC_BULK_16384 = (1 << 7), 1469 }; 1470 1471 #define MLX5_FC_BULK_NUM_FCS(fc_enum) (MLX5_FC_BULK_SIZE_FACTOR * (fc_enum)) 1472 1473 #define MLX5_FT_MAX_MULTIPATH_LEVEL 63 1474 1475 enum { 1476 MLX5_STEERING_FORMAT_CONNECTX_5 = 0, 1477 MLX5_STEERING_FORMAT_CONNECTX_6DX = 1, 1478 MLX5_STEERING_FORMAT_CONNECTX_7 = 2, 1479 }; 1480 1481 struct mlx5_ifc_cmd_hca_cap_bits { 1482 u8 reserved_at_0[0x10]; 1483 u8 shared_object_to_user_object_allowed[0x1]; 1484 u8 reserved_at_13[0xe]; 1485 u8 vhca_resource_manager[0x1]; 1486 1487 u8 hca_cap_2[0x1]; 1488 u8 create_lag_when_not_master_up[0x1]; 1489 u8 dtor[0x1]; 1490 u8 event_on_vhca_state_teardown_request[0x1]; 1491 u8 event_on_vhca_state_in_use[0x1]; 1492 u8 event_on_vhca_state_active[0x1]; 1493 u8 event_on_vhca_state_allocated[0x1]; 1494 u8 event_on_vhca_state_invalid[0x1]; 1495 u8 reserved_at_28[0x8]; 1496 u8 vhca_id[0x10]; 1497 1498 u8 reserved_at_40[0x40]; 1499 1500 u8 log_max_srq_sz[0x8]; 1501 u8 log_max_qp_sz[0x8]; 1502 u8 event_cap[0x1]; 1503 u8 reserved_at_91[0x2]; 1504 u8 isolate_vl_tc_new[0x1]; 1505 u8 reserved_at_94[0x4]; 1506 u8 prio_tag_required[0x1]; 1507 u8 reserved_at_99[0x2]; 1508 u8 log_max_qp[0x5]; 1509 1510 u8 reserved_at_a0[0x3]; 1511 u8 ece_support[0x1]; 1512 u8 reserved_at_a4[0x5]; 1513 u8 reg_c_preserve[0x1]; 1514 u8 reserved_at_aa[0x1]; 1515 u8 log_max_srq[0x5]; 1516 u8 reserved_at_b0[0x1]; 1517 u8 uplink_follow[0x1]; 1518 u8 ts_cqe_to_dest_cqn[0x1]; 1519 u8 reserved_at_b3[0x7]; 1520 u8 shampo[0x1]; 1521 u8 reserved_at_bb[0x5]; 1522 1523 u8 max_sgl_for_optimized_performance[0x8]; 1524 u8 log_max_cq_sz[0x8]; 1525 u8 relaxed_ordering_write_umr[0x1]; 1526 u8 relaxed_ordering_read_umr[0x1]; 1527 u8 reserved_at_d2[0x7]; 1528 u8 virtio_net_device_emualtion_manager[0x1]; 1529 u8 virtio_blk_device_emualtion_manager[0x1]; 1530 u8 log_max_cq[0x5]; 1531 1532 u8 log_max_eq_sz[0x8]; 1533 u8 relaxed_ordering_write[0x1]; 1534 u8 relaxed_ordering_read[0x1]; 1535 u8 log_max_mkey[0x6]; 1536 u8 reserved_at_f0[0x6]; 1537 u8 terminate_scatter_list_mkey[0x1]; 1538 u8 repeated_mkey[0x1]; 1539 u8 dump_fill_mkey[0x1]; 1540 u8 reserved_at_f9[0x2]; 1541 u8 fast_teardown[0x1]; 1542 u8 log_max_eq[0x4]; 1543 1544 u8 max_indirection[0x8]; 1545 u8 fixed_buffer_size[0x1]; 1546 u8 log_max_mrw_sz[0x7]; 1547 u8 force_teardown[0x1]; 1548 u8 reserved_at_111[0x1]; 1549 u8 log_max_bsf_list_size[0x6]; 1550 u8 umr_extended_translation_offset[0x1]; 1551 u8 null_mkey[0x1]; 1552 u8 log_max_klm_list_size[0x6]; 1553 1554 u8 reserved_at_120[0x2]; 1555 u8 qpc_extension[0x1]; 1556 u8 reserved_at_123[0x7]; 1557 u8 log_max_ra_req_dc[0x6]; 1558 u8 reserved_at_130[0x2]; 1559 u8 eth_wqe_too_small[0x1]; 1560 u8 reserved_at_133[0x6]; 1561 u8 vnic_env_cq_overrun[0x1]; 1562 u8 log_max_ra_res_dc[0x6]; 1563 1564 u8 reserved_at_140[0x5]; 1565 u8 release_all_pages[0x1]; 1566 u8 must_not_use[0x1]; 1567 u8 reserved_at_147[0x2]; 1568 u8 roce_accl[0x1]; 1569 u8 log_max_ra_req_qp[0x6]; 1570 u8 reserved_at_150[0xa]; 1571 u8 log_max_ra_res_qp[0x6]; 1572 1573 u8 end_pad[0x1]; 1574 u8 cc_query_allowed[0x1]; 1575 u8 cc_modify_allowed[0x1]; 1576 u8 start_pad[0x1]; 1577 u8 cache_line_128byte[0x1]; 1578 u8 reserved_at_165[0x4]; 1579 u8 rts2rts_qp_counters_set_id[0x1]; 1580 u8 reserved_at_16a[0x2]; 1581 u8 vnic_env_int_rq_oob[0x1]; 1582 u8 sbcam_reg[0x1]; 1583 u8 reserved_at_16e[0x1]; 1584 u8 qcam_reg[0x1]; 1585 u8 gid_table_size[0x10]; 1586 1587 u8 out_of_seq_cnt[0x1]; 1588 u8 vport_counters[0x1]; 1589 u8 retransmission_q_counters[0x1]; 1590 u8 debug[0x1]; 1591 u8 modify_rq_counter_set_id[0x1]; 1592 u8 rq_delay_drop[0x1]; 1593 u8 max_qp_cnt[0xa]; 1594 u8 pkey_table_size[0x10]; 1595 1596 u8 vport_group_manager[0x1]; 1597 u8 vhca_group_manager[0x1]; 1598 u8 ib_virt[0x1]; 1599 u8 eth_virt[0x1]; 1600 u8 vnic_env_queue_counters[0x1]; 1601 u8 ets[0x1]; 1602 u8 nic_flow_table[0x1]; 1603 u8 eswitch_manager[0x1]; 1604 u8 device_memory[0x1]; 1605 u8 mcam_reg[0x1]; 1606 u8 pcam_reg[0x1]; 1607 u8 local_ca_ack_delay[0x5]; 1608 u8 port_module_event[0x1]; 1609 u8 enhanced_error_q_counters[0x1]; 1610 u8 ports_check[0x1]; 1611 u8 reserved_at_1b3[0x1]; 1612 u8 disable_link_up[0x1]; 1613 u8 beacon_led[0x1]; 1614 u8 port_type[0x2]; 1615 u8 num_ports[0x8]; 1616 1617 u8 reserved_at_1c0[0x1]; 1618 u8 pps[0x1]; 1619 u8 pps_modify[0x1]; 1620 u8 log_max_msg[0x5]; 1621 u8 reserved_at_1c8[0x4]; 1622 u8 max_tc[0x4]; 1623 u8 temp_warn_event[0x1]; 1624 u8 dcbx[0x1]; 1625 u8 general_notification_event[0x1]; 1626 u8 reserved_at_1d3[0x2]; 1627 u8 fpga[0x1]; 1628 u8 rol_s[0x1]; 1629 u8 rol_g[0x1]; 1630 u8 reserved_at_1d8[0x1]; 1631 u8 wol_s[0x1]; 1632 u8 wol_g[0x1]; 1633 u8 wol_a[0x1]; 1634 u8 wol_b[0x1]; 1635 u8 wol_m[0x1]; 1636 u8 wol_u[0x1]; 1637 u8 wol_p[0x1]; 1638 1639 u8 stat_rate_support[0x10]; 1640 u8 reserved_at_1f0[0x1]; 1641 u8 pci_sync_for_fw_update_event[0x1]; 1642 u8 reserved_at_1f2[0x6]; 1643 u8 init2_lag_tx_port_affinity[0x1]; 1644 u8 reserved_at_1fa[0x3]; 1645 u8 cqe_version[0x4]; 1646 1647 u8 compact_address_vector[0x1]; 1648 u8 striding_rq[0x1]; 1649 u8 reserved_at_202[0x1]; 1650 u8 ipoib_enhanced_offloads[0x1]; 1651 u8 ipoib_basic_offloads[0x1]; 1652 u8 reserved_at_205[0x1]; 1653 u8 repeated_block_disabled[0x1]; 1654 u8 umr_modify_entity_size_disabled[0x1]; 1655 u8 umr_modify_atomic_disabled[0x1]; 1656 u8 umr_indirect_mkey_disabled[0x1]; 1657 u8 umr_fence[0x2]; 1658 u8 dc_req_scat_data_cqe[0x1]; 1659 u8 reserved_at_20d[0x2]; 1660 u8 drain_sigerr[0x1]; 1661 u8 cmdif_checksum[0x2]; 1662 u8 sigerr_cqe[0x1]; 1663 u8 reserved_at_213[0x1]; 1664 u8 wq_signature[0x1]; 1665 u8 sctr_data_cqe[0x1]; 1666 u8 reserved_at_216[0x1]; 1667 u8 sho[0x1]; 1668 u8 tph[0x1]; 1669 u8 rf[0x1]; 1670 u8 dct[0x1]; 1671 u8 qos[0x1]; 1672 u8 eth_net_offloads[0x1]; 1673 u8 roce[0x1]; 1674 u8 atomic[0x1]; 1675 u8 reserved_at_21f[0x1]; 1676 1677 u8 cq_oi[0x1]; 1678 u8 cq_resize[0x1]; 1679 u8 cq_moderation[0x1]; 1680 u8 reserved_at_223[0x3]; 1681 u8 cq_eq_remap[0x1]; 1682 u8 pg[0x1]; 1683 u8 block_lb_mc[0x1]; 1684 u8 reserved_at_229[0x1]; 1685 u8 scqe_break_moderation[0x1]; 1686 u8 cq_period_start_from_cqe[0x1]; 1687 u8 cd[0x1]; 1688 u8 reserved_at_22d[0x1]; 1689 u8 apm[0x1]; 1690 u8 vector_calc[0x1]; 1691 u8 umr_ptr_rlky[0x1]; 1692 u8 imaicl[0x1]; 1693 u8 qp_packet_based[0x1]; 1694 u8 reserved_at_233[0x3]; 1695 u8 qkv[0x1]; 1696 u8 pkv[0x1]; 1697 u8 set_deth_sqpn[0x1]; 1698 u8 reserved_at_239[0x3]; 1699 u8 xrc[0x1]; 1700 u8 ud[0x1]; 1701 u8 uc[0x1]; 1702 u8 rc[0x1]; 1703 1704 u8 uar_4k[0x1]; 1705 u8 reserved_at_241[0x9]; 1706 u8 uar_sz[0x6]; 1707 u8 port_selection_cap[0x1]; 1708 u8 reserved_at_248[0x1]; 1709 u8 umem_uid_0[0x1]; 1710 u8 reserved_at_250[0x5]; 1711 u8 log_pg_sz[0x8]; 1712 1713 u8 bf[0x1]; 1714 u8 driver_version[0x1]; 1715 u8 pad_tx_eth_packet[0x1]; 1716 u8 reserved_at_263[0x3]; 1717 u8 mkey_by_name[0x1]; 1718 u8 reserved_at_267[0x4]; 1719 1720 u8 log_bf_reg_size[0x5]; 1721 1722 u8 reserved_at_270[0x3]; 1723 u8 qp_error_syndrome[0x1]; 1724 u8 reserved_at_274[0x2]; 1725 u8 lag_dct[0x2]; 1726 u8 lag_tx_port_affinity[0x1]; 1727 u8 lag_native_fdb_selection[0x1]; 1728 u8 reserved_at_27a[0x1]; 1729 u8 lag_master[0x1]; 1730 u8 num_lag_ports[0x4]; 1731 1732 u8 reserved_at_280[0x10]; 1733 u8 max_wqe_sz_sq[0x10]; 1734 1735 u8 reserved_at_2a0[0x10]; 1736 u8 max_wqe_sz_rq[0x10]; 1737 1738 u8 max_flow_counter_31_16[0x10]; 1739 u8 max_wqe_sz_sq_dc[0x10]; 1740 1741 u8 reserved_at_2e0[0x7]; 1742 u8 max_qp_mcg[0x19]; 1743 1744 u8 reserved_at_300[0x10]; 1745 u8 flow_counter_bulk_alloc[0x8]; 1746 u8 log_max_mcg[0x8]; 1747 1748 u8 reserved_at_320[0x3]; 1749 u8 log_max_transport_domain[0x5]; 1750 u8 reserved_at_328[0x3]; 1751 u8 log_max_pd[0x5]; 1752 u8 reserved_at_330[0xb]; 1753 u8 log_max_xrcd[0x5]; 1754 1755 u8 nic_receive_steering_discard[0x1]; 1756 u8 receive_discard_vport_down[0x1]; 1757 u8 transmit_discard_vport_down[0x1]; 1758 u8 eq_overrun_count[0x1]; 1759 u8 reserved_at_344[0x1]; 1760 u8 invalid_command_count[0x1]; 1761 u8 quota_exceeded_count[0x1]; 1762 u8 reserved_at_347[0x1]; 1763 u8 log_max_flow_counter_bulk[0x8]; 1764 u8 max_flow_counter_15_0[0x10]; 1765 1766 1767 u8 reserved_at_360[0x3]; 1768 u8 log_max_rq[0x5]; 1769 u8 reserved_at_368[0x3]; 1770 u8 log_max_sq[0x5]; 1771 u8 reserved_at_370[0x3]; 1772 u8 log_max_tir[0x5]; 1773 u8 reserved_at_378[0x3]; 1774 u8 log_max_tis[0x5]; 1775 1776 u8 basic_cyclic_rcv_wqe[0x1]; 1777 u8 reserved_at_381[0x2]; 1778 u8 log_max_rmp[0x5]; 1779 u8 reserved_at_388[0x3]; 1780 u8 log_max_rqt[0x5]; 1781 u8 reserved_at_390[0x3]; 1782 u8 log_max_rqt_size[0x5]; 1783 u8 reserved_at_398[0x3]; 1784 u8 log_max_tis_per_sq[0x5]; 1785 1786 u8 ext_stride_num_range[0x1]; 1787 u8 roce_rw_supported[0x1]; 1788 u8 log_max_current_uc_list_wr_supported[0x1]; 1789 u8 log_max_stride_sz_rq[0x5]; 1790 u8 reserved_at_3a8[0x3]; 1791 u8 log_min_stride_sz_rq[0x5]; 1792 u8 reserved_at_3b0[0x3]; 1793 u8 log_max_stride_sz_sq[0x5]; 1794 u8 reserved_at_3b8[0x3]; 1795 u8 log_min_stride_sz_sq[0x5]; 1796 1797 u8 hairpin[0x1]; 1798 u8 reserved_at_3c1[0x2]; 1799 u8 log_max_hairpin_queues[0x5]; 1800 u8 reserved_at_3c8[0x3]; 1801 u8 log_max_hairpin_wq_data_sz[0x5]; 1802 u8 reserved_at_3d0[0x3]; 1803 u8 log_max_hairpin_num_packets[0x5]; 1804 u8 reserved_at_3d8[0x3]; 1805 u8 log_max_wq_sz[0x5]; 1806 1807 u8 nic_vport_change_event[0x1]; 1808 u8 disable_local_lb_uc[0x1]; 1809 u8 disable_local_lb_mc[0x1]; 1810 u8 log_min_hairpin_wq_data_sz[0x5]; 1811 u8 reserved_at_3e8[0x2]; 1812 u8 vhca_state[0x1]; 1813 u8 log_max_vlan_list[0x5]; 1814 u8 reserved_at_3f0[0x3]; 1815 u8 log_max_current_mc_list[0x5]; 1816 u8 reserved_at_3f8[0x3]; 1817 u8 log_max_current_uc_list[0x5]; 1818 1819 u8 general_obj_types[0x40]; 1820 1821 u8 sq_ts_format[0x2]; 1822 u8 rq_ts_format[0x2]; 1823 u8 steering_format_version[0x4]; 1824 u8 create_qp_start_hint[0x18]; 1825 1826 u8 reserved_at_460[0x1]; 1827 u8 ats[0x1]; 1828 u8 reserved_at_462[0x1]; 1829 u8 log_max_uctx[0x5]; 1830 u8 reserved_at_468[0x1]; 1831 u8 crypto[0x1]; 1832 u8 ipsec_offload[0x1]; 1833 u8 log_max_umem[0x5]; 1834 u8 max_num_eqs[0x10]; 1835 1836 u8 reserved_at_480[0x1]; 1837 u8 tls_tx[0x1]; 1838 u8 tls_rx[0x1]; 1839 u8 log_max_l2_table[0x5]; 1840 u8 reserved_at_488[0x8]; 1841 u8 log_uar_page_sz[0x10]; 1842 1843 u8 reserved_at_4a0[0x20]; 1844 u8 device_frequency_mhz[0x20]; 1845 u8 device_frequency_khz[0x20]; 1846 1847 u8 reserved_at_500[0x20]; 1848 u8 num_of_uars_per_page[0x20]; 1849 1850 u8 flex_parser_protocols[0x20]; 1851 1852 u8 max_geneve_tlv_options[0x8]; 1853 u8 reserved_at_568[0x3]; 1854 u8 max_geneve_tlv_option_data_len[0x5]; 1855 u8 reserved_at_570[0x9]; 1856 u8 adv_virtualization[0x1]; 1857 u8 reserved_at_57a[0x6]; 1858 1859 u8 reserved_at_580[0xb]; 1860 u8 log_max_dci_stream_channels[0x5]; 1861 u8 reserved_at_590[0x3]; 1862 u8 log_max_dci_errored_streams[0x5]; 1863 u8 reserved_at_598[0x8]; 1864 1865 u8 reserved_at_5a0[0x10]; 1866 u8 enhanced_cqe_compression[0x1]; 1867 u8 reserved_at_5b1[0x2]; 1868 u8 log_max_dek[0x5]; 1869 u8 reserved_at_5b8[0x4]; 1870 u8 mini_cqe_resp_stride_index[0x1]; 1871 u8 cqe_128_always[0x1]; 1872 u8 cqe_compression_128[0x1]; 1873 u8 cqe_compression[0x1]; 1874 1875 u8 cqe_compression_timeout[0x10]; 1876 u8 cqe_compression_max_num[0x10]; 1877 1878 u8 reserved_at_5e0[0x8]; 1879 u8 flex_parser_id_gtpu_dw_0[0x4]; 1880 u8 reserved_at_5ec[0x4]; 1881 u8 tag_matching[0x1]; 1882 u8 rndv_offload_rc[0x1]; 1883 u8 rndv_offload_dc[0x1]; 1884 u8 log_tag_matching_list_sz[0x5]; 1885 u8 reserved_at_5f8[0x3]; 1886 u8 log_max_xrq[0x5]; 1887 1888 u8 affiliate_nic_vport_criteria[0x8]; 1889 u8 native_port_num[0x8]; 1890 u8 num_vhca_ports[0x8]; 1891 u8 flex_parser_id_gtpu_teid[0x4]; 1892 u8 reserved_at_61c[0x2]; 1893 u8 sw_owner_id[0x1]; 1894 u8 reserved_at_61f[0x1]; 1895 1896 u8 max_num_of_monitor_counters[0x10]; 1897 u8 num_ppcnt_monitor_counters[0x10]; 1898 1899 u8 max_num_sf[0x10]; 1900 u8 num_q_monitor_counters[0x10]; 1901 1902 u8 reserved_at_660[0x20]; 1903 1904 u8 sf[0x1]; 1905 u8 sf_set_partition[0x1]; 1906 u8 reserved_at_682[0x1]; 1907 u8 log_max_sf[0x5]; 1908 u8 apu[0x1]; 1909 u8 reserved_at_689[0x4]; 1910 u8 migration[0x1]; 1911 u8 reserved_at_68e[0x2]; 1912 u8 log_min_sf_size[0x8]; 1913 u8 max_num_sf_partitions[0x8]; 1914 1915 u8 uctx_cap[0x20]; 1916 1917 u8 reserved_at_6c0[0x4]; 1918 u8 flex_parser_id_geneve_tlv_option_0[0x4]; 1919 u8 flex_parser_id_icmp_dw1[0x4]; 1920 u8 flex_parser_id_icmp_dw0[0x4]; 1921 u8 flex_parser_id_icmpv6_dw1[0x4]; 1922 u8 flex_parser_id_icmpv6_dw0[0x4]; 1923 u8 flex_parser_id_outer_first_mpls_over_gre[0x4]; 1924 u8 flex_parser_id_outer_first_mpls_over_udp_label[0x4]; 1925 1926 u8 max_num_match_definer[0x10]; 1927 u8 sf_base_id[0x10]; 1928 1929 u8 flex_parser_id_gtpu_dw_2[0x4]; 1930 u8 flex_parser_id_gtpu_first_ext_dw_0[0x4]; 1931 u8 num_total_dynamic_vf_msix[0x18]; 1932 u8 reserved_at_720[0x14]; 1933 u8 dynamic_msix_table_size[0xc]; 1934 u8 reserved_at_740[0xc]; 1935 u8 min_dynamic_vf_msix_table_size[0x4]; 1936 u8 reserved_at_750[0x4]; 1937 u8 max_dynamic_vf_msix_table_size[0xc]; 1938 1939 u8 reserved_at_760[0x3]; 1940 u8 log_max_num_header_modify_argument[0x5]; 1941 u8 reserved_at_768[0x4]; 1942 u8 log_header_modify_argument_granularity[0x4]; 1943 u8 reserved_at_770[0x3]; 1944 u8 log_header_modify_argument_max_alloc[0x5]; 1945 u8 reserved_at_778[0x8]; 1946 1947 u8 vhca_tunnel_commands[0x40]; 1948 u8 match_definer_format_supported[0x40]; 1949 }; 1950 1951 struct mlx5_ifc_cmd_hca_cap_2_bits { 1952 u8 reserved_at_0[0x80]; 1953 1954 u8 migratable[0x1]; 1955 u8 reserved_at_81[0x1f]; 1956 1957 u8 max_reformat_insert_size[0x8]; 1958 u8 max_reformat_insert_offset[0x8]; 1959 u8 max_reformat_remove_size[0x8]; 1960 u8 max_reformat_remove_offset[0x8]; 1961 1962 u8 reserved_at_c0[0x8]; 1963 u8 migration_multi_load[0x1]; 1964 u8 migration_tracking_state[0x1]; 1965 u8 reserved_at_ca[0x16]; 1966 1967 u8 reserved_at_e0[0xc0]; 1968 1969 u8 flow_table_type_2_type[0x8]; 1970 u8 reserved_at_1a8[0x3]; 1971 u8 log_min_mkey_entity_size[0x5]; 1972 u8 reserved_at_1b0[0x10]; 1973 1974 u8 reserved_at_1c0[0x60]; 1975 1976 u8 reserved_at_220[0x1]; 1977 u8 sw_vhca_id_valid[0x1]; 1978 u8 sw_vhca_id[0xe]; 1979 u8 reserved_at_230[0x10]; 1980 1981 u8 reserved_at_240[0xb]; 1982 u8 ts_cqe_metadata_size2wqe_counter[0x5]; 1983 u8 reserved_at_250[0x10]; 1984 1985 u8 reserved_at_260[0x5a0]; 1986 }; 1987 1988 enum mlx5_ifc_flow_destination_type { 1989 MLX5_IFC_FLOW_DESTINATION_TYPE_VPORT = 0x0, 1990 MLX5_IFC_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1, 1991 MLX5_IFC_FLOW_DESTINATION_TYPE_TIR = 0x2, 1992 MLX5_IFC_FLOW_DESTINATION_TYPE_FLOW_SAMPLER = 0x6, 1993 MLX5_IFC_FLOW_DESTINATION_TYPE_UPLINK = 0x8, 1994 MLX5_IFC_FLOW_DESTINATION_TYPE_TABLE_TYPE = 0xA, 1995 }; 1996 1997 enum mlx5_flow_table_miss_action { 1998 MLX5_FLOW_TABLE_MISS_ACTION_DEF, 1999 MLX5_FLOW_TABLE_MISS_ACTION_FWD, 2000 MLX5_FLOW_TABLE_MISS_ACTION_SWITCH_DOMAIN, 2001 }; 2002 2003 struct mlx5_ifc_dest_format_struct_bits { 2004 u8 destination_type[0x8]; 2005 u8 destination_id[0x18]; 2006 2007 u8 destination_eswitch_owner_vhca_id_valid[0x1]; 2008 u8 packet_reformat[0x1]; 2009 u8 reserved_at_22[0x6]; 2010 u8 destination_table_type[0x8]; 2011 u8 destination_eswitch_owner_vhca_id[0x10]; 2012 }; 2013 2014 struct mlx5_ifc_flow_counter_list_bits { 2015 u8 flow_counter_id[0x20]; 2016 2017 u8 reserved_at_20[0x20]; 2018 }; 2019 2020 struct mlx5_ifc_extended_dest_format_bits { 2021 struct mlx5_ifc_dest_format_struct_bits destination_entry; 2022 2023 u8 packet_reformat_id[0x20]; 2024 2025 u8 reserved_at_60[0x20]; 2026 }; 2027 2028 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits { 2029 struct mlx5_ifc_extended_dest_format_bits extended_dest_format; 2030 struct mlx5_ifc_flow_counter_list_bits flow_counter_list; 2031 }; 2032 2033 struct mlx5_ifc_fte_match_param_bits { 2034 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers; 2035 2036 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters; 2037 2038 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers; 2039 2040 struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2; 2041 2042 struct mlx5_ifc_fte_match_set_misc3_bits misc_parameters_3; 2043 2044 struct mlx5_ifc_fte_match_set_misc4_bits misc_parameters_4; 2045 2046 struct mlx5_ifc_fte_match_set_misc5_bits misc_parameters_5; 2047 2048 u8 reserved_at_e00[0x200]; 2049 }; 2050 2051 enum { 2052 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0, 2053 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1, 2054 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2, 2055 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3, 2056 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4, 2057 }; 2058 2059 struct mlx5_ifc_rx_hash_field_select_bits { 2060 u8 l3_prot_type[0x1]; 2061 u8 l4_prot_type[0x1]; 2062 u8 selected_fields[0x1e]; 2063 }; 2064 2065 enum { 2066 MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0, 2067 MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1, 2068 }; 2069 2070 enum { 2071 MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0, 2072 MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1, 2073 }; 2074 2075 struct mlx5_ifc_wq_bits { 2076 u8 wq_type[0x4]; 2077 u8 wq_signature[0x1]; 2078 u8 end_padding_mode[0x2]; 2079 u8 cd_slave[0x1]; 2080 u8 reserved_at_8[0x18]; 2081 2082 u8 hds_skip_first_sge[0x1]; 2083 u8 log2_hds_buf_size[0x3]; 2084 u8 reserved_at_24[0x7]; 2085 u8 page_offset[0x5]; 2086 u8 lwm[0x10]; 2087 2088 u8 reserved_at_40[0x8]; 2089 u8 pd[0x18]; 2090 2091 u8 reserved_at_60[0x8]; 2092 u8 uar_page[0x18]; 2093 2094 u8 dbr_addr[0x40]; 2095 2096 u8 hw_counter[0x20]; 2097 2098 u8 sw_counter[0x20]; 2099 2100 u8 reserved_at_100[0xc]; 2101 u8 log_wq_stride[0x4]; 2102 u8 reserved_at_110[0x3]; 2103 u8 log_wq_pg_sz[0x5]; 2104 u8 reserved_at_118[0x3]; 2105 u8 log_wq_sz[0x5]; 2106 2107 u8 dbr_umem_valid[0x1]; 2108 u8 wq_umem_valid[0x1]; 2109 u8 reserved_at_122[0x1]; 2110 u8 log_hairpin_num_packets[0x5]; 2111 u8 reserved_at_128[0x3]; 2112 u8 log_hairpin_data_sz[0x5]; 2113 2114 u8 reserved_at_130[0x4]; 2115 u8 log_wqe_num_of_strides[0x4]; 2116 u8 two_byte_shift_en[0x1]; 2117 u8 reserved_at_139[0x4]; 2118 u8 log_wqe_stride_size[0x3]; 2119 2120 u8 reserved_at_140[0x80]; 2121 2122 u8 headers_mkey[0x20]; 2123 2124 u8 shampo_enable[0x1]; 2125 u8 reserved_at_1e1[0x4]; 2126 u8 log_reservation_size[0x3]; 2127 u8 reserved_at_1e8[0x5]; 2128 u8 log_max_num_of_packets_per_reservation[0x3]; 2129 u8 reserved_at_1f0[0x6]; 2130 u8 log_headers_entry_size[0x2]; 2131 u8 reserved_at_1f8[0x4]; 2132 u8 log_headers_buffer_entry_num[0x4]; 2133 2134 u8 reserved_at_200[0x400]; 2135 2136 struct mlx5_ifc_cmd_pas_bits pas[]; 2137 }; 2138 2139 struct mlx5_ifc_rq_num_bits { 2140 u8 reserved_at_0[0x8]; 2141 u8 rq_num[0x18]; 2142 }; 2143 2144 struct mlx5_ifc_mac_address_layout_bits { 2145 u8 reserved_at_0[0x10]; 2146 u8 mac_addr_47_32[0x10]; 2147 2148 u8 mac_addr_31_0[0x20]; 2149 }; 2150 2151 struct mlx5_ifc_vlan_layout_bits { 2152 u8 reserved_at_0[0x14]; 2153 u8 vlan[0x0c]; 2154 2155 u8 reserved_at_20[0x20]; 2156 }; 2157 2158 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits { 2159 u8 reserved_at_0[0xa0]; 2160 2161 u8 min_time_between_cnps[0x20]; 2162 2163 u8 reserved_at_c0[0x12]; 2164 u8 cnp_dscp[0x6]; 2165 u8 reserved_at_d8[0x4]; 2166 u8 cnp_prio_mode[0x1]; 2167 u8 cnp_802p_prio[0x3]; 2168 2169 u8 reserved_at_e0[0x720]; 2170 }; 2171 2172 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits { 2173 u8 reserved_at_0[0x60]; 2174 2175 u8 reserved_at_60[0x4]; 2176 u8 clamp_tgt_rate[0x1]; 2177 u8 reserved_at_65[0x3]; 2178 u8 clamp_tgt_rate_after_time_inc[0x1]; 2179 u8 reserved_at_69[0x17]; 2180 2181 u8 reserved_at_80[0x20]; 2182 2183 u8 rpg_time_reset[0x20]; 2184 2185 u8 rpg_byte_reset[0x20]; 2186 2187 u8 rpg_threshold[0x20]; 2188 2189 u8 rpg_max_rate[0x20]; 2190 2191 u8 rpg_ai_rate[0x20]; 2192 2193 u8 rpg_hai_rate[0x20]; 2194 2195 u8 rpg_gd[0x20]; 2196 2197 u8 rpg_min_dec_fac[0x20]; 2198 2199 u8 rpg_min_rate[0x20]; 2200 2201 u8 reserved_at_1c0[0xe0]; 2202 2203 u8 rate_to_set_on_first_cnp[0x20]; 2204 2205 u8 dce_tcp_g[0x20]; 2206 2207 u8 dce_tcp_rtt[0x20]; 2208 2209 u8 rate_reduce_monitor_period[0x20]; 2210 2211 u8 reserved_at_320[0x20]; 2212 2213 u8 initial_alpha_value[0x20]; 2214 2215 u8 reserved_at_360[0x4a0]; 2216 }; 2217 2218 struct mlx5_ifc_cong_control_r_roce_general_bits { 2219 u8 reserved_at_0[0x80]; 2220 2221 u8 reserved_at_80[0x10]; 2222 u8 rtt_resp_dscp_valid[0x1]; 2223 u8 reserved_at_91[0x9]; 2224 u8 rtt_resp_dscp[0x6]; 2225 2226 u8 reserved_at_a0[0x760]; 2227 }; 2228 2229 struct mlx5_ifc_cong_control_802_1qau_rp_bits { 2230 u8 reserved_at_0[0x80]; 2231 2232 u8 rppp_max_rps[0x20]; 2233 2234 u8 rpg_time_reset[0x20]; 2235 2236 u8 rpg_byte_reset[0x20]; 2237 2238 u8 rpg_threshold[0x20]; 2239 2240 u8 rpg_max_rate[0x20]; 2241 2242 u8 rpg_ai_rate[0x20]; 2243 2244 u8 rpg_hai_rate[0x20]; 2245 2246 u8 rpg_gd[0x20]; 2247 2248 u8 rpg_min_dec_fac[0x20]; 2249 2250 u8 rpg_min_rate[0x20]; 2251 2252 u8 reserved_at_1c0[0x640]; 2253 }; 2254 2255 enum { 2256 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1, 2257 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2, 2258 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4, 2259 }; 2260 2261 struct mlx5_ifc_resize_field_select_bits { 2262 u8 resize_field_select[0x20]; 2263 }; 2264 2265 struct mlx5_ifc_resource_dump_bits { 2266 u8 more_dump[0x1]; 2267 u8 inline_dump[0x1]; 2268 u8 reserved_at_2[0xa]; 2269 u8 seq_num[0x4]; 2270 u8 segment_type[0x10]; 2271 2272 u8 reserved_at_20[0x10]; 2273 u8 vhca_id[0x10]; 2274 2275 u8 index1[0x20]; 2276 2277 u8 index2[0x20]; 2278 2279 u8 num_of_obj1[0x10]; 2280 u8 num_of_obj2[0x10]; 2281 2282 u8 reserved_at_a0[0x20]; 2283 2284 u8 device_opaque[0x40]; 2285 2286 u8 mkey[0x20]; 2287 2288 u8 size[0x20]; 2289 2290 u8 address[0x40]; 2291 2292 u8 inline_data[52][0x20]; 2293 }; 2294 2295 struct mlx5_ifc_resource_dump_menu_record_bits { 2296 u8 reserved_at_0[0x4]; 2297 u8 num_of_obj2_supports_active[0x1]; 2298 u8 num_of_obj2_supports_all[0x1]; 2299 u8 must_have_num_of_obj2[0x1]; 2300 u8 support_num_of_obj2[0x1]; 2301 u8 num_of_obj1_supports_active[0x1]; 2302 u8 num_of_obj1_supports_all[0x1]; 2303 u8 must_have_num_of_obj1[0x1]; 2304 u8 support_num_of_obj1[0x1]; 2305 u8 must_have_index2[0x1]; 2306 u8 support_index2[0x1]; 2307 u8 must_have_index1[0x1]; 2308 u8 support_index1[0x1]; 2309 u8 segment_type[0x10]; 2310 2311 u8 segment_name[4][0x20]; 2312 2313 u8 index1_name[4][0x20]; 2314 2315 u8 index2_name[4][0x20]; 2316 }; 2317 2318 struct mlx5_ifc_resource_dump_segment_header_bits { 2319 u8 length_dw[0x10]; 2320 u8 segment_type[0x10]; 2321 }; 2322 2323 struct mlx5_ifc_resource_dump_command_segment_bits { 2324 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2325 2326 u8 segment_called[0x10]; 2327 u8 vhca_id[0x10]; 2328 2329 u8 index1[0x20]; 2330 2331 u8 index2[0x20]; 2332 2333 u8 num_of_obj1[0x10]; 2334 u8 num_of_obj2[0x10]; 2335 }; 2336 2337 struct mlx5_ifc_resource_dump_error_segment_bits { 2338 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2339 2340 u8 reserved_at_20[0x10]; 2341 u8 syndrome_id[0x10]; 2342 2343 u8 reserved_at_40[0x40]; 2344 2345 u8 error[8][0x20]; 2346 }; 2347 2348 struct mlx5_ifc_resource_dump_info_segment_bits { 2349 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2350 2351 u8 reserved_at_20[0x18]; 2352 u8 dump_version[0x8]; 2353 2354 u8 hw_version[0x20]; 2355 2356 u8 fw_version[0x20]; 2357 }; 2358 2359 struct mlx5_ifc_resource_dump_menu_segment_bits { 2360 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2361 2362 u8 reserved_at_20[0x10]; 2363 u8 num_of_records[0x10]; 2364 2365 struct mlx5_ifc_resource_dump_menu_record_bits record[]; 2366 }; 2367 2368 struct mlx5_ifc_resource_dump_resource_segment_bits { 2369 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2370 2371 u8 reserved_at_20[0x20]; 2372 2373 u8 index1[0x20]; 2374 2375 u8 index2[0x20]; 2376 2377 u8 payload[][0x20]; 2378 }; 2379 2380 struct mlx5_ifc_resource_dump_terminate_segment_bits { 2381 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2382 }; 2383 2384 struct mlx5_ifc_menu_resource_dump_response_bits { 2385 struct mlx5_ifc_resource_dump_info_segment_bits info; 2386 struct mlx5_ifc_resource_dump_command_segment_bits cmd; 2387 struct mlx5_ifc_resource_dump_menu_segment_bits menu; 2388 struct mlx5_ifc_resource_dump_terminate_segment_bits terminate; 2389 }; 2390 2391 enum { 2392 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1, 2393 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2, 2394 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4, 2395 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8, 2396 }; 2397 2398 struct mlx5_ifc_modify_field_select_bits { 2399 u8 modify_field_select[0x20]; 2400 }; 2401 2402 struct mlx5_ifc_field_select_r_roce_np_bits { 2403 u8 field_select_r_roce_np[0x20]; 2404 }; 2405 2406 struct mlx5_ifc_field_select_r_roce_rp_bits { 2407 u8 field_select_r_roce_rp[0x20]; 2408 }; 2409 2410 enum { 2411 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4, 2412 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8, 2413 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10, 2414 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20, 2415 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40, 2416 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80, 2417 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100, 2418 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200, 2419 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400, 2420 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800, 2421 }; 2422 2423 struct mlx5_ifc_field_select_802_1qau_rp_bits { 2424 u8 field_select_8021qaurp[0x20]; 2425 }; 2426 2427 struct mlx5_ifc_phys_layer_cntrs_bits { 2428 u8 time_since_last_clear_high[0x20]; 2429 2430 u8 time_since_last_clear_low[0x20]; 2431 2432 u8 symbol_errors_high[0x20]; 2433 2434 u8 symbol_errors_low[0x20]; 2435 2436 u8 sync_headers_errors_high[0x20]; 2437 2438 u8 sync_headers_errors_low[0x20]; 2439 2440 u8 edpl_bip_errors_lane0_high[0x20]; 2441 2442 u8 edpl_bip_errors_lane0_low[0x20]; 2443 2444 u8 edpl_bip_errors_lane1_high[0x20]; 2445 2446 u8 edpl_bip_errors_lane1_low[0x20]; 2447 2448 u8 edpl_bip_errors_lane2_high[0x20]; 2449 2450 u8 edpl_bip_errors_lane2_low[0x20]; 2451 2452 u8 edpl_bip_errors_lane3_high[0x20]; 2453 2454 u8 edpl_bip_errors_lane3_low[0x20]; 2455 2456 u8 fc_fec_corrected_blocks_lane0_high[0x20]; 2457 2458 u8 fc_fec_corrected_blocks_lane0_low[0x20]; 2459 2460 u8 fc_fec_corrected_blocks_lane1_high[0x20]; 2461 2462 u8 fc_fec_corrected_blocks_lane1_low[0x20]; 2463 2464 u8 fc_fec_corrected_blocks_lane2_high[0x20]; 2465 2466 u8 fc_fec_corrected_blocks_lane2_low[0x20]; 2467 2468 u8 fc_fec_corrected_blocks_lane3_high[0x20]; 2469 2470 u8 fc_fec_corrected_blocks_lane3_low[0x20]; 2471 2472 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20]; 2473 2474 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20]; 2475 2476 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20]; 2477 2478 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20]; 2479 2480 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20]; 2481 2482 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20]; 2483 2484 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20]; 2485 2486 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20]; 2487 2488 u8 rs_fec_corrected_blocks_high[0x20]; 2489 2490 u8 rs_fec_corrected_blocks_low[0x20]; 2491 2492 u8 rs_fec_uncorrectable_blocks_high[0x20]; 2493 2494 u8 rs_fec_uncorrectable_blocks_low[0x20]; 2495 2496 u8 rs_fec_no_errors_blocks_high[0x20]; 2497 2498 u8 rs_fec_no_errors_blocks_low[0x20]; 2499 2500 u8 rs_fec_single_error_blocks_high[0x20]; 2501 2502 u8 rs_fec_single_error_blocks_low[0x20]; 2503 2504 u8 rs_fec_corrected_symbols_total_high[0x20]; 2505 2506 u8 rs_fec_corrected_symbols_total_low[0x20]; 2507 2508 u8 rs_fec_corrected_symbols_lane0_high[0x20]; 2509 2510 u8 rs_fec_corrected_symbols_lane0_low[0x20]; 2511 2512 u8 rs_fec_corrected_symbols_lane1_high[0x20]; 2513 2514 u8 rs_fec_corrected_symbols_lane1_low[0x20]; 2515 2516 u8 rs_fec_corrected_symbols_lane2_high[0x20]; 2517 2518 u8 rs_fec_corrected_symbols_lane2_low[0x20]; 2519 2520 u8 rs_fec_corrected_symbols_lane3_high[0x20]; 2521 2522 u8 rs_fec_corrected_symbols_lane3_low[0x20]; 2523 2524 u8 link_down_events[0x20]; 2525 2526 u8 successful_recovery_events[0x20]; 2527 2528 u8 reserved_at_640[0x180]; 2529 }; 2530 2531 struct mlx5_ifc_phys_layer_statistical_cntrs_bits { 2532 u8 time_since_last_clear_high[0x20]; 2533 2534 u8 time_since_last_clear_low[0x20]; 2535 2536 u8 phy_received_bits_high[0x20]; 2537 2538 u8 phy_received_bits_low[0x20]; 2539 2540 u8 phy_symbol_errors_high[0x20]; 2541 2542 u8 phy_symbol_errors_low[0x20]; 2543 2544 u8 phy_corrected_bits_high[0x20]; 2545 2546 u8 phy_corrected_bits_low[0x20]; 2547 2548 u8 phy_corrected_bits_lane0_high[0x20]; 2549 2550 u8 phy_corrected_bits_lane0_low[0x20]; 2551 2552 u8 phy_corrected_bits_lane1_high[0x20]; 2553 2554 u8 phy_corrected_bits_lane1_low[0x20]; 2555 2556 u8 phy_corrected_bits_lane2_high[0x20]; 2557 2558 u8 phy_corrected_bits_lane2_low[0x20]; 2559 2560 u8 phy_corrected_bits_lane3_high[0x20]; 2561 2562 u8 phy_corrected_bits_lane3_low[0x20]; 2563 2564 u8 reserved_at_200[0x5c0]; 2565 }; 2566 2567 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits { 2568 u8 symbol_error_counter[0x10]; 2569 2570 u8 link_error_recovery_counter[0x8]; 2571 2572 u8 link_downed_counter[0x8]; 2573 2574 u8 port_rcv_errors[0x10]; 2575 2576 u8 port_rcv_remote_physical_errors[0x10]; 2577 2578 u8 port_rcv_switch_relay_errors[0x10]; 2579 2580 u8 port_xmit_discards[0x10]; 2581 2582 u8 port_xmit_constraint_errors[0x8]; 2583 2584 u8 port_rcv_constraint_errors[0x8]; 2585 2586 u8 reserved_at_70[0x8]; 2587 2588 u8 link_overrun_errors[0x8]; 2589 2590 u8 reserved_at_80[0x10]; 2591 2592 u8 vl_15_dropped[0x10]; 2593 2594 u8 reserved_at_a0[0x80]; 2595 2596 u8 port_xmit_wait[0x20]; 2597 }; 2598 2599 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits { 2600 u8 transmit_queue_high[0x20]; 2601 2602 u8 transmit_queue_low[0x20]; 2603 2604 u8 no_buffer_discard_uc_high[0x20]; 2605 2606 u8 no_buffer_discard_uc_low[0x20]; 2607 2608 u8 reserved_at_80[0x740]; 2609 }; 2610 2611 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits { 2612 u8 wred_discard_high[0x20]; 2613 2614 u8 wred_discard_low[0x20]; 2615 2616 u8 ecn_marked_tc_high[0x20]; 2617 2618 u8 ecn_marked_tc_low[0x20]; 2619 2620 u8 reserved_at_80[0x740]; 2621 }; 2622 2623 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits { 2624 u8 rx_octets_high[0x20]; 2625 2626 u8 rx_octets_low[0x20]; 2627 2628 u8 reserved_at_40[0xc0]; 2629 2630 u8 rx_frames_high[0x20]; 2631 2632 u8 rx_frames_low[0x20]; 2633 2634 u8 tx_octets_high[0x20]; 2635 2636 u8 tx_octets_low[0x20]; 2637 2638 u8 reserved_at_180[0xc0]; 2639 2640 u8 tx_frames_high[0x20]; 2641 2642 u8 tx_frames_low[0x20]; 2643 2644 u8 rx_pause_high[0x20]; 2645 2646 u8 rx_pause_low[0x20]; 2647 2648 u8 rx_pause_duration_high[0x20]; 2649 2650 u8 rx_pause_duration_low[0x20]; 2651 2652 u8 tx_pause_high[0x20]; 2653 2654 u8 tx_pause_low[0x20]; 2655 2656 u8 tx_pause_duration_high[0x20]; 2657 2658 u8 tx_pause_duration_low[0x20]; 2659 2660 u8 rx_pause_transition_high[0x20]; 2661 2662 u8 rx_pause_transition_low[0x20]; 2663 2664 u8 rx_discards_high[0x20]; 2665 2666 u8 rx_discards_low[0x20]; 2667 2668 u8 device_stall_minor_watermark_cnt_high[0x20]; 2669 2670 u8 device_stall_minor_watermark_cnt_low[0x20]; 2671 2672 u8 device_stall_critical_watermark_cnt_high[0x20]; 2673 2674 u8 device_stall_critical_watermark_cnt_low[0x20]; 2675 2676 u8 reserved_at_480[0x340]; 2677 }; 2678 2679 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits { 2680 u8 port_transmit_wait_high[0x20]; 2681 2682 u8 port_transmit_wait_low[0x20]; 2683 2684 u8 reserved_at_40[0x100]; 2685 2686 u8 rx_buffer_almost_full_high[0x20]; 2687 2688 u8 rx_buffer_almost_full_low[0x20]; 2689 2690 u8 rx_buffer_full_high[0x20]; 2691 2692 u8 rx_buffer_full_low[0x20]; 2693 2694 u8 rx_icrc_encapsulated_high[0x20]; 2695 2696 u8 rx_icrc_encapsulated_low[0x20]; 2697 2698 u8 reserved_at_200[0x5c0]; 2699 }; 2700 2701 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits { 2702 u8 dot3stats_alignment_errors_high[0x20]; 2703 2704 u8 dot3stats_alignment_errors_low[0x20]; 2705 2706 u8 dot3stats_fcs_errors_high[0x20]; 2707 2708 u8 dot3stats_fcs_errors_low[0x20]; 2709 2710 u8 dot3stats_single_collision_frames_high[0x20]; 2711 2712 u8 dot3stats_single_collision_frames_low[0x20]; 2713 2714 u8 dot3stats_multiple_collision_frames_high[0x20]; 2715 2716 u8 dot3stats_multiple_collision_frames_low[0x20]; 2717 2718 u8 dot3stats_sqe_test_errors_high[0x20]; 2719 2720 u8 dot3stats_sqe_test_errors_low[0x20]; 2721 2722 u8 dot3stats_deferred_transmissions_high[0x20]; 2723 2724 u8 dot3stats_deferred_transmissions_low[0x20]; 2725 2726 u8 dot3stats_late_collisions_high[0x20]; 2727 2728 u8 dot3stats_late_collisions_low[0x20]; 2729 2730 u8 dot3stats_excessive_collisions_high[0x20]; 2731 2732 u8 dot3stats_excessive_collisions_low[0x20]; 2733 2734 u8 dot3stats_internal_mac_transmit_errors_high[0x20]; 2735 2736 u8 dot3stats_internal_mac_transmit_errors_low[0x20]; 2737 2738 u8 dot3stats_carrier_sense_errors_high[0x20]; 2739 2740 u8 dot3stats_carrier_sense_errors_low[0x20]; 2741 2742 u8 dot3stats_frame_too_longs_high[0x20]; 2743 2744 u8 dot3stats_frame_too_longs_low[0x20]; 2745 2746 u8 dot3stats_internal_mac_receive_errors_high[0x20]; 2747 2748 u8 dot3stats_internal_mac_receive_errors_low[0x20]; 2749 2750 u8 dot3stats_symbol_errors_high[0x20]; 2751 2752 u8 dot3stats_symbol_errors_low[0x20]; 2753 2754 u8 dot3control_in_unknown_opcodes_high[0x20]; 2755 2756 u8 dot3control_in_unknown_opcodes_low[0x20]; 2757 2758 u8 dot3in_pause_frames_high[0x20]; 2759 2760 u8 dot3in_pause_frames_low[0x20]; 2761 2762 u8 dot3out_pause_frames_high[0x20]; 2763 2764 u8 dot3out_pause_frames_low[0x20]; 2765 2766 u8 reserved_at_400[0x3c0]; 2767 }; 2768 2769 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits { 2770 u8 ether_stats_drop_events_high[0x20]; 2771 2772 u8 ether_stats_drop_events_low[0x20]; 2773 2774 u8 ether_stats_octets_high[0x20]; 2775 2776 u8 ether_stats_octets_low[0x20]; 2777 2778 u8 ether_stats_pkts_high[0x20]; 2779 2780 u8 ether_stats_pkts_low[0x20]; 2781 2782 u8 ether_stats_broadcast_pkts_high[0x20]; 2783 2784 u8 ether_stats_broadcast_pkts_low[0x20]; 2785 2786 u8 ether_stats_multicast_pkts_high[0x20]; 2787 2788 u8 ether_stats_multicast_pkts_low[0x20]; 2789 2790 u8 ether_stats_crc_align_errors_high[0x20]; 2791 2792 u8 ether_stats_crc_align_errors_low[0x20]; 2793 2794 u8 ether_stats_undersize_pkts_high[0x20]; 2795 2796 u8 ether_stats_undersize_pkts_low[0x20]; 2797 2798 u8 ether_stats_oversize_pkts_high[0x20]; 2799 2800 u8 ether_stats_oversize_pkts_low[0x20]; 2801 2802 u8 ether_stats_fragments_high[0x20]; 2803 2804 u8 ether_stats_fragments_low[0x20]; 2805 2806 u8 ether_stats_jabbers_high[0x20]; 2807 2808 u8 ether_stats_jabbers_low[0x20]; 2809 2810 u8 ether_stats_collisions_high[0x20]; 2811 2812 u8 ether_stats_collisions_low[0x20]; 2813 2814 u8 ether_stats_pkts64octets_high[0x20]; 2815 2816 u8 ether_stats_pkts64octets_low[0x20]; 2817 2818 u8 ether_stats_pkts65to127octets_high[0x20]; 2819 2820 u8 ether_stats_pkts65to127octets_low[0x20]; 2821 2822 u8 ether_stats_pkts128to255octets_high[0x20]; 2823 2824 u8 ether_stats_pkts128to255octets_low[0x20]; 2825 2826 u8 ether_stats_pkts256to511octets_high[0x20]; 2827 2828 u8 ether_stats_pkts256to511octets_low[0x20]; 2829 2830 u8 ether_stats_pkts512to1023octets_high[0x20]; 2831 2832 u8 ether_stats_pkts512to1023octets_low[0x20]; 2833 2834 u8 ether_stats_pkts1024to1518octets_high[0x20]; 2835 2836 u8 ether_stats_pkts1024to1518octets_low[0x20]; 2837 2838 u8 ether_stats_pkts1519to2047octets_high[0x20]; 2839 2840 u8 ether_stats_pkts1519to2047octets_low[0x20]; 2841 2842 u8 ether_stats_pkts2048to4095octets_high[0x20]; 2843 2844 u8 ether_stats_pkts2048to4095octets_low[0x20]; 2845 2846 u8 ether_stats_pkts4096to8191octets_high[0x20]; 2847 2848 u8 ether_stats_pkts4096to8191octets_low[0x20]; 2849 2850 u8 ether_stats_pkts8192to10239octets_high[0x20]; 2851 2852 u8 ether_stats_pkts8192to10239octets_low[0x20]; 2853 2854 u8 reserved_at_540[0x280]; 2855 }; 2856 2857 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits { 2858 u8 if_in_octets_high[0x20]; 2859 2860 u8 if_in_octets_low[0x20]; 2861 2862 u8 if_in_ucast_pkts_high[0x20]; 2863 2864 u8 if_in_ucast_pkts_low[0x20]; 2865 2866 u8 if_in_discards_high[0x20]; 2867 2868 u8 if_in_discards_low[0x20]; 2869 2870 u8 if_in_errors_high[0x20]; 2871 2872 u8 if_in_errors_low[0x20]; 2873 2874 u8 if_in_unknown_protos_high[0x20]; 2875 2876 u8 if_in_unknown_protos_low[0x20]; 2877 2878 u8 if_out_octets_high[0x20]; 2879 2880 u8 if_out_octets_low[0x20]; 2881 2882 u8 if_out_ucast_pkts_high[0x20]; 2883 2884 u8 if_out_ucast_pkts_low[0x20]; 2885 2886 u8 if_out_discards_high[0x20]; 2887 2888 u8 if_out_discards_low[0x20]; 2889 2890 u8 if_out_errors_high[0x20]; 2891 2892 u8 if_out_errors_low[0x20]; 2893 2894 u8 if_in_multicast_pkts_high[0x20]; 2895 2896 u8 if_in_multicast_pkts_low[0x20]; 2897 2898 u8 if_in_broadcast_pkts_high[0x20]; 2899 2900 u8 if_in_broadcast_pkts_low[0x20]; 2901 2902 u8 if_out_multicast_pkts_high[0x20]; 2903 2904 u8 if_out_multicast_pkts_low[0x20]; 2905 2906 u8 if_out_broadcast_pkts_high[0x20]; 2907 2908 u8 if_out_broadcast_pkts_low[0x20]; 2909 2910 u8 reserved_at_340[0x480]; 2911 }; 2912 2913 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits { 2914 u8 a_frames_transmitted_ok_high[0x20]; 2915 2916 u8 a_frames_transmitted_ok_low[0x20]; 2917 2918 u8 a_frames_received_ok_high[0x20]; 2919 2920 u8 a_frames_received_ok_low[0x20]; 2921 2922 u8 a_frame_check_sequence_errors_high[0x20]; 2923 2924 u8 a_frame_check_sequence_errors_low[0x20]; 2925 2926 u8 a_alignment_errors_high[0x20]; 2927 2928 u8 a_alignment_errors_low[0x20]; 2929 2930 u8 a_octets_transmitted_ok_high[0x20]; 2931 2932 u8 a_octets_transmitted_ok_low[0x20]; 2933 2934 u8 a_octets_received_ok_high[0x20]; 2935 2936 u8 a_octets_received_ok_low[0x20]; 2937 2938 u8 a_multicast_frames_xmitted_ok_high[0x20]; 2939 2940 u8 a_multicast_frames_xmitted_ok_low[0x20]; 2941 2942 u8 a_broadcast_frames_xmitted_ok_high[0x20]; 2943 2944 u8 a_broadcast_frames_xmitted_ok_low[0x20]; 2945 2946 u8 a_multicast_frames_received_ok_high[0x20]; 2947 2948 u8 a_multicast_frames_received_ok_low[0x20]; 2949 2950 u8 a_broadcast_frames_received_ok_high[0x20]; 2951 2952 u8 a_broadcast_frames_received_ok_low[0x20]; 2953 2954 u8 a_in_range_length_errors_high[0x20]; 2955 2956 u8 a_in_range_length_errors_low[0x20]; 2957 2958 u8 a_out_of_range_length_field_high[0x20]; 2959 2960 u8 a_out_of_range_length_field_low[0x20]; 2961 2962 u8 a_frame_too_long_errors_high[0x20]; 2963 2964 u8 a_frame_too_long_errors_low[0x20]; 2965 2966 u8 a_symbol_error_during_carrier_high[0x20]; 2967 2968 u8 a_symbol_error_during_carrier_low[0x20]; 2969 2970 u8 a_mac_control_frames_transmitted_high[0x20]; 2971 2972 u8 a_mac_control_frames_transmitted_low[0x20]; 2973 2974 u8 a_mac_control_frames_received_high[0x20]; 2975 2976 u8 a_mac_control_frames_received_low[0x20]; 2977 2978 u8 a_unsupported_opcodes_received_high[0x20]; 2979 2980 u8 a_unsupported_opcodes_received_low[0x20]; 2981 2982 u8 a_pause_mac_ctrl_frames_received_high[0x20]; 2983 2984 u8 a_pause_mac_ctrl_frames_received_low[0x20]; 2985 2986 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20]; 2987 2988 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20]; 2989 2990 u8 reserved_at_4c0[0x300]; 2991 }; 2992 2993 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits { 2994 u8 life_time_counter_high[0x20]; 2995 2996 u8 life_time_counter_low[0x20]; 2997 2998 u8 rx_errors[0x20]; 2999 3000 u8 tx_errors[0x20]; 3001 3002 u8 l0_to_recovery_eieos[0x20]; 3003 3004 u8 l0_to_recovery_ts[0x20]; 3005 3006 u8 l0_to_recovery_framing[0x20]; 3007 3008 u8 l0_to_recovery_retrain[0x20]; 3009 3010 u8 crc_error_dllp[0x20]; 3011 3012 u8 crc_error_tlp[0x20]; 3013 3014 u8 tx_overflow_buffer_pkt_high[0x20]; 3015 3016 u8 tx_overflow_buffer_pkt_low[0x20]; 3017 3018 u8 outbound_stalled_reads[0x20]; 3019 3020 u8 outbound_stalled_writes[0x20]; 3021 3022 u8 outbound_stalled_reads_events[0x20]; 3023 3024 u8 outbound_stalled_writes_events[0x20]; 3025 3026 u8 reserved_at_200[0x5c0]; 3027 }; 3028 3029 struct mlx5_ifc_cmd_inter_comp_event_bits { 3030 u8 command_completion_vector[0x20]; 3031 3032 u8 reserved_at_20[0xc0]; 3033 }; 3034 3035 struct mlx5_ifc_stall_vl_event_bits { 3036 u8 reserved_at_0[0x18]; 3037 u8 port_num[0x1]; 3038 u8 reserved_at_19[0x3]; 3039 u8 vl[0x4]; 3040 3041 u8 reserved_at_20[0xa0]; 3042 }; 3043 3044 struct mlx5_ifc_db_bf_congestion_event_bits { 3045 u8 event_subtype[0x8]; 3046 u8 reserved_at_8[0x8]; 3047 u8 congestion_level[0x8]; 3048 u8 reserved_at_18[0x8]; 3049 3050 u8 reserved_at_20[0xa0]; 3051 }; 3052 3053 struct mlx5_ifc_gpio_event_bits { 3054 u8 reserved_at_0[0x60]; 3055 3056 u8 gpio_event_hi[0x20]; 3057 3058 u8 gpio_event_lo[0x20]; 3059 3060 u8 reserved_at_a0[0x40]; 3061 }; 3062 3063 struct mlx5_ifc_port_state_change_event_bits { 3064 u8 reserved_at_0[0x40]; 3065 3066 u8 port_num[0x4]; 3067 u8 reserved_at_44[0x1c]; 3068 3069 u8 reserved_at_60[0x80]; 3070 }; 3071 3072 struct mlx5_ifc_dropped_packet_logged_bits { 3073 u8 reserved_at_0[0xe0]; 3074 }; 3075 3076 struct mlx5_ifc_default_timeout_bits { 3077 u8 to_multiplier[0x3]; 3078 u8 reserved_at_3[0x9]; 3079 u8 to_value[0x14]; 3080 }; 3081 3082 struct mlx5_ifc_dtor_reg_bits { 3083 u8 reserved_at_0[0x20]; 3084 3085 struct mlx5_ifc_default_timeout_bits pcie_toggle_to; 3086 3087 u8 reserved_at_40[0x60]; 3088 3089 struct mlx5_ifc_default_timeout_bits health_poll_to; 3090 3091 struct mlx5_ifc_default_timeout_bits full_crdump_to; 3092 3093 struct mlx5_ifc_default_timeout_bits fw_reset_to; 3094 3095 struct mlx5_ifc_default_timeout_bits flush_on_err_to; 3096 3097 struct mlx5_ifc_default_timeout_bits pci_sync_update_to; 3098 3099 struct mlx5_ifc_default_timeout_bits tear_down_to; 3100 3101 struct mlx5_ifc_default_timeout_bits fsm_reactivate_to; 3102 3103 struct mlx5_ifc_default_timeout_bits reclaim_pages_to; 3104 3105 struct mlx5_ifc_default_timeout_bits reclaim_vfs_pages_to; 3106 3107 u8 reserved_at_1c0[0x40]; 3108 }; 3109 3110 enum { 3111 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1, 3112 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2, 3113 }; 3114 3115 struct mlx5_ifc_cq_error_bits { 3116 u8 reserved_at_0[0x8]; 3117 u8 cqn[0x18]; 3118 3119 u8 reserved_at_20[0x20]; 3120 3121 u8 reserved_at_40[0x18]; 3122 u8 syndrome[0x8]; 3123 3124 u8 reserved_at_60[0x80]; 3125 }; 3126 3127 struct mlx5_ifc_rdma_page_fault_event_bits { 3128 u8 bytes_committed[0x20]; 3129 3130 u8 r_key[0x20]; 3131 3132 u8 reserved_at_40[0x10]; 3133 u8 packet_len[0x10]; 3134 3135 u8 rdma_op_len[0x20]; 3136 3137 u8 rdma_va[0x40]; 3138 3139 u8 reserved_at_c0[0x5]; 3140 u8 rdma[0x1]; 3141 u8 write[0x1]; 3142 u8 requestor[0x1]; 3143 u8 qp_number[0x18]; 3144 }; 3145 3146 struct mlx5_ifc_wqe_associated_page_fault_event_bits { 3147 u8 bytes_committed[0x20]; 3148 3149 u8 reserved_at_20[0x10]; 3150 u8 wqe_index[0x10]; 3151 3152 u8 reserved_at_40[0x10]; 3153 u8 len[0x10]; 3154 3155 u8 reserved_at_60[0x60]; 3156 3157 u8 reserved_at_c0[0x5]; 3158 u8 rdma[0x1]; 3159 u8 write_read[0x1]; 3160 u8 requestor[0x1]; 3161 u8 qpn[0x18]; 3162 }; 3163 3164 struct mlx5_ifc_qp_events_bits { 3165 u8 reserved_at_0[0xa0]; 3166 3167 u8 type[0x8]; 3168 u8 reserved_at_a8[0x18]; 3169 3170 u8 reserved_at_c0[0x8]; 3171 u8 qpn_rqn_sqn[0x18]; 3172 }; 3173 3174 struct mlx5_ifc_dct_events_bits { 3175 u8 reserved_at_0[0xc0]; 3176 3177 u8 reserved_at_c0[0x8]; 3178 u8 dct_number[0x18]; 3179 }; 3180 3181 struct mlx5_ifc_comp_event_bits { 3182 u8 reserved_at_0[0xc0]; 3183 3184 u8 reserved_at_c0[0x8]; 3185 u8 cq_number[0x18]; 3186 }; 3187 3188 enum { 3189 MLX5_QPC_STATE_RST = 0x0, 3190 MLX5_QPC_STATE_INIT = 0x1, 3191 MLX5_QPC_STATE_RTR = 0x2, 3192 MLX5_QPC_STATE_RTS = 0x3, 3193 MLX5_QPC_STATE_SQER = 0x4, 3194 MLX5_QPC_STATE_ERR = 0x6, 3195 MLX5_QPC_STATE_SQD = 0x7, 3196 MLX5_QPC_STATE_SUSPENDED = 0x9, 3197 }; 3198 3199 enum { 3200 MLX5_QPC_ST_RC = 0x0, 3201 MLX5_QPC_ST_UC = 0x1, 3202 MLX5_QPC_ST_UD = 0x2, 3203 MLX5_QPC_ST_XRC = 0x3, 3204 MLX5_QPC_ST_DCI = 0x5, 3205 MLX5_QPC_ST_QP0 = 0x7, 3206 MLX5_QPC_ST_QP1 = 0x8, 3207 MLX5_QPC_ST_RAW_DATAGRAM = 0x9, 3208 MLX5_QPC_ST_REG_UMR = 0xc, 3209 }; 3210 3211 enum { 3212 MLX5_QPC_PM_STATE_ARMED = 0x0, 3213 MLX5_QPC_PM_STATE_REARM = 0x1, 3214 MLX5_QPC_PM_STATE_RESERVED = 0x2, 3215 MLX5_QPC_PM_STATE_MIGRATED = 0x3, 3216 }; 3217 3218 enum { 3219 MLX5_QPC_OFFLOAD_TYPE_RNDV = 0x1, 3220 }; 3221 3222 enum { 3223 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0, 3224 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1, 3225 }; 3226 3227 enum { 3228 MLX5_QPC_MTU_256_BYTES = 0x1, 3229 MLX5_QPC_MTU_512_BYTES = 0x2, 3230 MLX5_QPC_MTU_1K_BYTES = 0x3, 3231 MLX5_QPC_MTU_2K_BYTES = 0x4, 3232 MLX5_QPC_MTU_4K_BYTES = 0x5, 3233 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7, 3234 }; 3235 3236 enum { 3237 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1, 3238 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2, 3239 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3, 3240 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4, 3241 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5, 3242 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6, 3243 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7, 3244 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8, 3245 }; 3246 3247 enum { 3248 MLX5_QPC_CS_REQ_DISABLE = 0x0, 3249 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11, 3250 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22, 3251 }; 3252 3253 enum { 3254 MLX5_QPC_CS_RES_DISABLE = 0x0, 3255 MLX5_QPC_CS_RES_UP_TO_32B = 0x1, 3256 MLX5_QPC_CS_RES_UP_TO_64B = 0x2, 3257 }; 3258 3259 enum { 3260 MLX5_TIMESTAMP_FORMAT_FREE_RUNNING = 0x0, 3261 MLX5_TIMESTAMP_FORMAT_DEFAULT = 0x1, 3262 MLX5_TIMESTAMP_FORMAT_REAL_TIME = 0x2, 3263 }; 3264 3265 struct mlx5_ifc_qpc_bits { 3266 u8 state[0x4]; 3267 u8 lag_tx_port_affinity[0x4]; 3268 u8 st[0x8]; 3269 u8 reserved_at_10[0x2]; 3270 u8 isolate_vl_tc[0x1]; 3271 u8 pm_state[0x2]; 3272 u8 reserved_at_15[0x1]; 3273 u8 req_e2e_credit_mode[0x2]; 3274 u8 offload_type[0x4]; 3275 u8 end_padding_mode[0x2]; 3276 u8 reserved_at_1e[0x2]; 3277 3278 u8 wq_signature[0x1]; 3279 u8 block_lb_mc[0x1]; 3280 u8 atomic_like_write_en[0x1]; 3281 u8 latency_sensitive[0x1]; 3282 u8 reserved_at_24[0x1]; 3283 u8 drain_sigerr[0x1]; 3284 u8 reserved_at_26[0x2]; 3285 u8 pd[0x18]; 3286 3287 u8 mtu[0x3]; 3288 u8 log_msg_max[0x5]; 3289 u8 reserved_at_48[0x1]; 3290 u8 log_rq_size[0x4]; 3291 u8 log_rq_stride[0x3]; 3292 u8 no_sq[0x1]; 3293 u8 log_sq_size[0x4]; 3294 u8 reserved_at_55[0x3]; 3295 u8 ts_format[0x2]; 3296 u8 reserved_at_5a[0x1]; 3297 u8 rlky[0x1]; 3298 u8 ulp_stateless_offload_mode[0x4]; 3299 3300 u8 counter_set_id[0x8]; 3301 u8 uar_page[0x18]; 3302 3303 u8 reserved_at_80[0x8]; 3304 u8 user_index[0x18]; 3305 3306 u8 reserved_at_a0[0x3]; 3307 u8 log_page_size[0x5]; 3308 u8 remote_qpn[0x18]; 3309 3310 struct mlx5_ifc_ads_bits primary_address_path; 3311 3312 struct mlx5_ifc_ads_bits secondary_address_path; 3313 3314 u8 log_ack_req_freq[0x4]; 3315 u8 reserved_at_384[0x4]; 3316 u8 log_sra_max[0x3]; 3317 u8 reserved_at_38b[0x2]; 3318 u8 retry_count[0x3]; 3319 u8 rnr_retry[0x3]; 3320 u8 reserved_at_393[0x1]; 3321 u8 fre[0x1]; 3322 u8 cur_rnr_retry[0x3]; 3323 u8 cur_retry_count[0x3]; 3324 u8 reserved_at_39b[0x5]; 3325 3326 u8 reserved_at_3a0[0x20]; 3327 3328 u8 reserved_at_3c0[0x8]; 3329 u8 next_send_psn[0x18]; 3330 3331 u8 reserved_at_3e0[0x3]; 3332 u8 log_num_dci_stream_channels[0x5]; 3333 u8 cqn_snd[0x18]; 3334 3335 u8 reserved_at_400[0x3]; 3336 u8 log_num_dci_errored_streams[0x5]; 3337 u8 deth_sqpn[0x18]; 3338 3339 u8 reserved_at_420[0x20]; 3340 3341 u8 reserved_at_440[0x8]; 3342 u8 last_acked_psn[0x18]; 3343 3344 u8 reserved_at_460[0x8]; 3345 u8 ssn[0x18]; 3346 3347 u8 reserved_at_480[0x8]; 3348 u8 log_rra_max[0x3]; 3349 u8 reserved_at_48b[0x1]; 3350 u8 atomic_mode[0x4]; 3351 u8 rre[0x1]; 3352 u8 rwe[0x1]; 3353 u8 rae[0x1]; 3354 u8 reserved_at_493[0x1]; 3355 u8 page_offset[0x6]; 3356 u8 reserved_at_49a[0x3]; 3357 u8 cd_slave_receive[0x1]; 3358 u8 cd_slave_send[0x1]; 3359 u8 cd_master[0x1]; 3360 3361 u8 reserved_at_4a0[0x3]; 3362 u8 min_rnr_nak[0x5]; 3363 u8 next_rcv_psn[0x18]; 3364 3365 u8 reserved_at_4c0[0x8]; 3366 u8 xrcd[0x18]; 3367 3368 u8 reserved_at_4e0[0x8]; 3369 u8 cqn_rcv[0x18]; 3370 3371 u8 dbr_addr[0x40]; 3372 3373 u8 q_key[0x20]; 3374 3375 u8 reserved_at_560[0x5]; 3376 u8 rq_type[0x3]; 3377 u8 srqn_rmpn_xrqn[0x18]; 3378 3379 u8 reserved_at_580[0x8]; 3380 u8 rmsn[0x18]; 3381 3382 u8 hw_sq_wqebb_counter[0x10]; 3383 u8 sw_sq_wqebb_counter[0x10]; 3384 3385 u8 hw_rq_counter[0x20]; 3386 3387 u8 sw_rq_counter[0x20]; 3388 3389 u8 reserved_at_600[0x20]; 3390 3391 u8 reserved_at_620[0xf]; 3392 u8 cgs[0x1]; 3393 u8 cs_req[0x8]; 3394 u8 cs_res[0x8]; 3395 3396 u8 dc_access_key[0x40]; 3397 3398 u8 reserved_at_680[0x3]; 3399 u8 dbr_umem_valid[0x1]; 3400 3401 u8 reserved_at_684[0xbc]; 3402 }; 3403 3404 struct mlx5_ifc_roce_addr_layout_bits { 3405 u8 source_l3_address[16][0x8]; 3406 3407 u8 reserved_at_80[0x3]; 3408 u8 vlan_valid[0x1]; 3409 u8 vlan_id[0xc]; 3410 u8 source_mac_47_32[0x10]; 3411 3412 u8 source_mac_31_0[0x20]; 3413 3414 u8 reserved_at_c0[0x14]; 3415 u8 roce_l3_type[0x4]; 3416 u8 roce_version[0x8]; 3417 3418 u8 reserved_at_e0[0x20]; 3419 }; 3420 3421 struct mlx5_ifc_shampo_cap_bits { 3422 u8 reserved_at_0[0x3]; 3423 u8 shampo_log_max_reservation_size[0x5]; 3424 u8 reserved_at_8[0x3]; 3425 u8 shampo_log_min_reservation_size[0x5]; 3426 u8 shampo_min_mss_size[0x10]; 3427 3428 u8 reserved_at_20[0x3]; 3429 u8 shampo_max_log_headers_entry_size[0x5]; 3430 u8 reserved_at_28[0x18]; 3431 3432 u8 reserved_at_40[0x7c0]; 3433 }; 3434 3435 struct mlx5_ifc_crypto_cap_bits { 3436 u8 reserved_at_0[0x3]; 3437 u8 synchronize_dek[0x1]; 3438 u8 int_kek_manual[0x1]; 3439 u8 int_kek_auto[0x1]; 3440 u8 reserved_at_6[0x1a]; 3441 3442 u8 reserved_at_20[0x3]; 3443 u8 log_dek_max_alloc[0x5]; 3444 u8 reserved_at_28[0x3]; 3445 u8 log_max_num_deks[0x5]; 3446 u8 reserved_at_30[0x10]; 3447 3448 u8 reserved_at_40[0x20]; 3449 3450 u8 reserved_at_60[0x3]; 3451 u8 log_dek_granularity[0x5]; 3452 u8 reserved_at_68[0x3]; 3453 u8 log_max_num_int_kek[0x5]; 3454 u8 sw_wrapped_dek[0x10]; 3455 3456 u8 reserved_at_80[0x780]; 3457 }; 3458 3459 union mlx5_ifc_hca_cap_union_bits { 3460 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap; 3461 struct mlx5_ifc_cmd_hca_cap_2_bits cmd_hca_cap_2; 3462 struct mlx5_ifc_odp_cap_bits odp_cap; 3463 struct mlx5_ifc_atomic_caps_bits atomic_caps; 3464 struct mlx5_ifc_roce_cap_bits roce_cap; 3465 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps; 3466 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap; 3467 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap; 3468 struct mlx5_ifc_e_switch_cap_bits e_switch_cap; 3469 struct mlx5_ifc_port_selection_cap_bits port_selection_cap; 3470 struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap; 3471 struct mlx5_ifc_qos_cap_bits qos_cap; 3472 struct mlx5_ifc_debug_cap_bits debug_cap; 3473 struct mlx5_ifc_fpga_cap_bits fpga_cap; 3474 struct mlx5_ifc_tls_cap_bits tls_cap; 3475 struct mlx5_ifc_device_mem_cap_bits device_mem_cap; 3476 struct mlx5_ifc_virtio_emulation_cap_bits virtio_emulation_cap; 3477 struct mlx5_ifc_shampo_cap_bits shampo_cap; 3478 struct mlx5_ifc_macsec_cap_bits macsec_cap; 3479 struct mlx5_ifc_crypto_cap_bits crypto_cap; 3480 u8 reserved_at_0[0x8000]; 3481 }; 3482 3483 enum { 3484 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1, 3485 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2, 3486 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4, 3487 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8, 3488 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT = 0x10, 3489 MLX5_FLOW_CONTEXT_ACTION_DECAP = 0x20, 3490 MLX5_FLOW_CONTEXT_ACTION_MOD_HDR = 0x40, 3491 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP = 0x80, 3492 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100, 3493 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2 = 0x400, 3494 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2 = 0x800, 3495 MLX5_FLOW_CONTEXT_ACTION_CRYPTO_DECRYPT = 0x1000, 3496 MLX5_FLOW_CONTEXT_ACTION_CRYPTO_ENCRYPT = 0x2000, 3497 MLX5_FLOW_CONTEXT_ACTION_EXECUTE_ASO = 0x4000, 3498 }; 3499 3500 enum { 3501 MLX5_FLOW_CONTEXT_FLOW_SOURCE_ANY_VPORT = 0x0, 3502 MLX5_FLOW_CONTEXT_FLOW_SOURCE_UPLINK = 0x1, 3503 MLX5_FLOW_CONTEXT_FLOW_SOURCE_LOCAL_VPORT = 0x2, 3504 }; 3505 3506 enum { 3507 MLX5_FLOW_CONTEXT_ENCRYPT_DECRYPT_TYPE_IPSEC = 0x0, 3508 MLX5_FLOW_CONTEXT_ENCRYPT_DECRYPT_TYPE_MACSEC = 0x1, 3509 }; 3510 3511 struct mlx5_ifc_vlan_bits { 3512 u8 ethtype[0x10]; 3513 u8 prio[0x3]; 3514 u8 cfi[0x1]; 3515 u8 vid[0xc]; 3516 }; 3517 3518 enum { 3519 MLX5_FLOW_METER_COLOR_RED = 0x0, 3520 MLX5_FLOW_METER_COLOR_YELLOW = 0x1, 3521 MLX5_FLOW_METER_COLOR_GREEN = 0x2, 3522 MLX5_FLOW_METER_COLOR_UNDEFINED = 0x3, 3523 }; 3524 3525 enum { 3526 MLX5_EXE_ASO_FLOW_METER = 0x2, 3527 }; 3528 3529 struct mlx5_ifc_exe_aso_ctrl_flow_meter_bits { 3530 u8 return_reg_id[0x4]; 3531 u8 aso_type[0x4]; 3532 u8 reserved_at_8[0x14]; 3533 u8 action[0x1]; 3534 u8 init_color[0x2]; 3535 u8 meter_id[0x1]; 3536 }; 3537 3538 union mlx5_ifc_exe_aso_ctrl { 3539 struct mlx5_ifc_exe_aso_ctrl_flow_meter_bits exe_aso_ctrl_flow_meter; 3540 }; 3541 3542 struct mlx5_ifc_execute_aso_bits { 3543 u8 valid[0x1]; 3544 u8 reserved_at_1[0x7]; 3545 u8 aso_object_id[0x18]; 3546 3547 union mlx5_ifc_exe_aso_ctrl exe_aso_ctrl; 3548 }; 3549 3550 struct mlx5_ifc_flow_context_bits { 3551 struct mlx5_ifc_vlan_bits push_vlan; 3552 3553 u8 group_id[0x20]; 3554 3555 u8 reserved_at_40[0x8]; 3556 u8 flow_tag[0x18]; 3557 3558 u8 reserved_at_60[0x10]; 3559 u8 action[0x10]; 3560 3561 u8 extended_destination[0x1]; 3562 u8 reserved_at_81[0x1]; 3563 u8 flow_source[0x2]; 3564 u8 encrypt_decrypt_type[0x4]; 3565 u8 destination_list_size[0x18]; 3566 3567 u8 reserved_at_a0[0x8]; 3568 u8 flow_counter_list_size[0x18]; 3569 3570 u8 packet_reformat_id[0x20]; 3571 3572 u8 modify_header_id[0x20]; 3573 3574 struct mlx5_ifc_vlan_bits push_vlan_2; 3575 3576 u8 encrypt_decrypt_obj_id[0x20]; 3577 u8 reserved_at_140[0xc0]; 3578 3579 struct mlx5_ifc_fte_match_param_bits match_value; 3580 3581 struct mlx5_ifc_execute_aso_bits execute_aso[4]; 3582 3583 u8 reserved_at_1300[0x500]; 3584 3585 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[]; 3586 }; 3587 3588 enum { 3589 MLX5_XRC_SRQC_STATE_GOOD = 0x0, 3590 MLX5_XRC_SRQC_STATE_ERROR = 0x1, 3591 }; 3592 3593 struct mlx5_ifc_xrc_srqc_bits { 3594 u8 state[0x4]; 3595 u8 log_xrc_srq_size[0x4]; 3596 u8 reserved_at_8[0x18]; 3597 3598 u8 wq_signature[0x1]; 3599 u8 cont_srq[0x1]; 3600 u8 reserved_at_22[0x1]; 3601 u8 rlky[0x1]; 3602 u8 basic_cyclic_rcv_wqe[0x1]; 3603 u8 log_rq_stride[0x3]; 3604 u8 xrcd[0x18]; 3605 3606 u8 page_offset[0x6]; 3607 u8 reserved_at_46[0x1]; 3608 u8 dbr_umem_valid[0x1]; 3609 u8 cqn[0x18]; 3610 3611 u8 reserved_at_60[0x20]; 3612 3613 u8 user_index_equal_xrc_srqn[0x1]; 3614 u8 reserved_at_81[0x1]; 3615 u8 log_page_size[0x6]; 3616 u8 user_index[0x18]; 3617 3618 u8 reserved_at_a0[0x20]; 3619 3620 u8 reserved_at_c0[0x8]; 3621 u8 pd[0x18]; 3622 3623 u8 lwm[0x10]; 3624 u8 wqe_cnt[0x10]; 3625 3626 u8 reserved_at_100[0x40]; 3627 3628 u8 db_record_addr_h[0x20]; 3629 3630 u8 db_record_addr_l[0x1e]; 3631 u8 reserved_at_17e[0x2]; 3632 3633 u8 reserved_at_180[0x80]; 3634 }; 3635 3636 struct mlx5_ifc_vnic_diagnostic_statistics_bits { 3637 u8 counter_error_queues[0x20]; 3638 3639 u8 total_error_queues[0x20]; 3640 3641 u8 send_queue_priority_update_flow[0x20]; 3642 3643 u8 reserved_at_60[0x20]; 3644 3645 u8 nic_receive_steering_discard[0x40]; 3646 3647 u8 receive_discard_vport_down[0x40]; 3648 3649 u8 transmit_discard_vport_down[0x40]; 3650 3651 u8 async_eq_overrun[0x20]; 3652 3653 u8 comp_eq_overrun[0x20]; 3654 3655 u8 reserved_at_180[0x20]; 3656 3657 u8 invalid_command[0x20]; 3658 3659 u8 quota_exceeded_command[0x20]; 3660 3661 u8 internal_rq_out_of_buffer[0x20]; 3662 3663 u8 cq_overrun[0x20]; 3664 3665 u8 eth_wqe_too_small[0x20]; 3666 3667 u8 reserved_at_220[0xdc0]; 3668 }; 3669 3670 struct mlx5_ifc_traffic_counter_bits { 3671 u8 packets[0x40]; 3672 3673 u8 octets[0x40]; 3674 }; 3675 3676 struct mlx5_ifc_tisc_bits { 3677 u8 strict_lag_tx_port_affinity[0x1]; 3678 u8 tls_en[0x1]; 3679 u8 reserved_at_2[0x2]; 3680 u8 lag_tx_port_affinity[0x04]; 3681 3682 u8 reserved_at_8[0x4]; 3683 u8 prio[0x4]; 3684 u8 reserved_at_10[0x10]; 3685 3686 u8 reserved_at_20[0x100]; 3687 3688 u8 reserved_at_120[0x8]; 3689 u8 transport_domain[0x18]; 3690 3691 u8 reserved_at_140[0x8]; 3692 u8 underlay_qpn[0x18]; 3693 3694 u8 reserved_at_160[0x8]; 3695 u8 pd[0x18]; 3696 3697 u8 reserved_at_180[0x380]; 3698 }; 3699 3700 enum { 3701 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0, 3702 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1, 3703 }; 3704 3705 enum { 3706 MLX5_TIRC_PACKET_MERGE_MASK_IPV4_LRO = BIT(0), 3707 MLX5_TIRC_PACKET_MERGE_MASK_IPV6_LRO = BIT(1), 3708 }; 3709 3710 enum { 3711 MLX5_RX_HASH_FN_NONE = 0x0, 3712 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1, 3713 MLX5_RX_HASH_FN_TOEPLITZ = 0x2, 3714 }; 3715 3716 enum { 3717 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST = 0x1, 3718 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST = 0x2, 3719 }; 3720 3721 struct mlx5_ifc_tirc_bits { 3722 u8 reserved_at_0[0x20]; 3723 3724 u8 disp_type[0x4]; 3725 u8 tls_en[0x1]; 3726 u8 reserved_at_25[0x1b]; 3727 3728 u8 reserved_at_40[0x40]; 3729 3730 u8 reserved_at_80[0x4]; 3731 u8 lro_timeout_period_usecs[0x10]; 3732 u8 packet_merge_mask[0x4]; 3733 u8 lro_max_ip_payload_size[0x8]; 3734 3735 u8 reserved_at_a0[0x40]; 3736 3737 u8 reserved_at_e0[0x8]; 3738 u8 inline_rqn[0x18]; 3739 3740 u8 rx_hash_symmetric[0x1]; 3741 u8 reserved_at_101[0x1]; 3742 u8 tunneled_offload_en[0x1]; 3743 u8 reserved_at_103[0x5]; 3744 u8 indirect_table[0x18]; 3745 3746 u8 rx_hash_fn[0x4]; 3747 u8 reserved_at_124[0x2]; 3748 u8 self_lb_block[0x2]; 3749 u8 transport_domain[0x18]; 3750 3751 u8 rx_hash_toeplitz_key[10][0x20]; 3752 3753 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer; 3754 3755 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner; 3756 3757 u8 reserved_at_2c0[0x4c0]; 3758 }; 3759 3760 enum { 3761 MLX5_SRQC_STATE_GOOD = 0x0, 3762 MLX5_SRQC_STATE_ERROR = 0x1, 3763 }; 3764 3765 struct mlx5_ifc_srqc_bits { 3766 u8 state[0x4]; 3767 u8 log_srq_size[0x4]; 3768 u8 reserved_at_8[0x18]; 3769 3770 u8 wq_signature[0x1]; 3771 u8 cont_srq[0x1]; 3772 u8 reserved_at_22[0x1]; 3773 u8 rlky[0x1]; 3774 u8 reserved_at_24[0x1]; 3775 u8 log_rq_stride[0x3]; 3776 u8 xrcd[0x18]; 3777 3778 u8 page_offset[0x6]; 3779 u8 reserved_at_46[0x2]; 3780 u8 cqn[0x18]; 3781 3782 u8 reserved_at_60[0x20]; 3783 3784 u8 reserved_at_80[0x2]; 3785 u8 log_page_size[0x6]; 3786 u8 reserved_at_88[0x18]; 3787 3788 u8 reserved_at_a0[0x20]; 3789 3790 u8 reserved_at_c0[0x8]; 3791 u8 pd[0x18]; 3792 3793 u8 lwm[0x10]; 3794 u8 wqe_cnt[0x10]; 3795 3796 u8 reserved_at_100[0x40]; 3797 3798 u8 dbr_addr[0x40]; 3799 3800 u8 reserved_at_180[0x80]; 3801 }; 3802 3803 enum { 3804 MLX5_SQC_STATE_RST = 0x0, 3805 MLX5_SQC_STATE_RDY = 0x1, 3806 MLX5_SQC_STATE_ERR = 0x3, 3807 }; 3808 3809 struct mlx5_ifc_sqc_bits { 3810 u8 rlky[0x1]; 3811 u8 cd_master[0x1]; 3812 u8 fre[0x1]; 3813 u8 flush_in_error_en[0x1]; 3814 u8 allow_multi_pkt_send_wqe[0x1]; 3815 u8 min_wqe_inline_mode[0x3]; 3816 u8 state[0x4]; 3817 u8 reg_umr[0x1]; 3818 u8 allow_swp[0x1]; 3819 u8 hairpin[0x1]; 3820 u8 reserved_at_f[0xb]; 3821 u8 ts_format[0x2]; 3822 u8 reserved_at_1c[0x4]; 3823 3824 u8 reserved_at_20[0x8]; 3825 u8 user_index[0x18]; 3826 3827 u8 reserved_at_40[0x8]; 3828 u8 cqn[0x18]; 3829 3830 u8 reserved_at_60[0x8]; 3831 u8 hairpin_peer_rq[0x18]; 3832 3833 u8 reserved_at_80[0x10]; 3834 u8 hairpin_peer_vhca[0x10]; 3835 3836 u8 reserved_at_a0[0x20]; 3837 3838 u8 reserved_at_c0[0x8]; 3839 u8 ts_cqe_to_dest_cqn[0x18]; 3840 3841 u8 reserved_at_e0[0x10]; 3842 u8 packet_pacing_rate_limit_index[0x10]; 3843 u8 tis_lst_sz[0x10]; 3844 u8 qos_queue_group_id[0x10]; 3845 3846 u8 reserved_at_120[0x40]; 3847 3848 u8 reserved_at_160[0x8]; 3849 u8 tis_num_0[0x18]; 3850 3851 struct mlx5_ifc_wq_bits wq; 3852 }; 3853 3854 enum { 3855 SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0, 3856 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1, 3857 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2, 3858 SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3, 3859 SCHEDULING_CONTEXT_ELEMENT_TYPE_QUEUE_GROUP = 0x4, 3860 }; 3861 3862 enum { 3863 ELEMENT_TYPE_CAP_MASK_TASR = 1 << 0, 3864 ELEMENT_TYPE_CAP_MASK_VPORT = 1 << 1, 3865 ELEMENT_TYPE_CAP_MASK_VPORT_TC = 1 << 2, 3866 ELEMENT_TYPE_CAP_MASK_PARA_VPORT_TC = 1 << 3, 3867 }; 3868 3869 struct mlx5_ifc_scheduling_context_bits { 3870 u8 element_type[0x8]; 3871 u8 reserved_at_8[0x18]; 3872 3873 u8 element_attributes[0x20]; 3874 3875 u8 parent_element_id[0x20]; 3876 3877 u8 reserved_at_60[0x40]; 3878 3879 u8 bw_share[0x20]; 3880 3881 u8 max_average_bw[0x20]; 3882 3883 u8 reserved_at_e0[0x120]; 3884 }; 3885 3886 struct mlx5_ifc_rqtc_bits { 3887 u8 reserved_at_0[0xa0]; 3888 3889 u8 reserved_at_a0[0x5]; 3890 u8 list_q_type[0x3]; 3891 u8 reserved_at_a8[0x8]; 3892 u8 rqt_max_size[0x10]; 3893 3894 u8 rq_vhca_id_format[0x1]; 3895 u8 reserved_at_c1[0xf]; 3896 u8 rqt_actual_size[0x10]; 3897 3898 u8 reserved_at_e0[0x6a0]; 3899 3900 struct mlx5_ifc_rq_num_bits rq_num[]; 3901 }; 3902 3903 enum { 3904 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0, 3905 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1, 3906 }; 3907 3908 enum { 3909 MLX5_RQC_STATE_RST = 0x0, 3910 MLX5_RQC_STATE_RDY = 0x1, 3911 MLX5_RQC_STATE_ERR = 0x3, 3912 }; 3913 3914 enum { 3915 MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_BYTE = 0x0, 3916 MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_STRIDE = 0x1, 3917 MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_PAGE = 0x2, 3918 }; 3919 3920 enum { 3921 MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_NO_MATCH = 0x0, 3922 MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_EXTENDED = 0x1, 3923 MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_FIVE_TUPLE = 0x2, 3924 }; 3925 3926 struct mlx5_ifc_rqc_bits { 3927 u8 rlky[0x1]; 3928 u8 delay_drop_en[0x1]; 3929 u8 scatter_fcs[0x1]; 3930 u8 vsd[0x1]; 3931 u8 mem_rq_type[0x4]; 3932 u8 state[0x4]; 3933 u8 reserved_at_c[0x1]; 3934 u8 flush_in_error_en[0x1]; 3935 u8 hairpin[0x1]; 3936 u8 reserved_at_f[0xb]; 3937 u8 ts_format[0x2]; 3938 u8 reserved_at_1c[0x4]; 3939 3940 u8 reserved_at_20[0x8]; 3941 u8 user_index[0x18]; 3942 3943 u8 reserved_at_40[0x8]; 3944 u8 cqn[0x18]; 3945 3946 u8 counter_set_id[0x8]; 3947 u8 reserved_at_68[0x18]; 3948 3949 u8 reserved_at_80[0x8]; 3950 u8 rmpn[0x18]; 3951 3952 u8 reserved_at_a0[0x8]; 3953 u8 hairpin_peer_sq[0x18]; 3954 3955 u8 reserved_at_c0[0x10]; 3956 u8 hairpin_peer_vhca[0x10]; 3957 3958 u8 reserved_at_e0[0x46]; 3959 u8 shampo_no_match_alignment_granularity[0x2]; 3960 u8 reserved_at_128[0x6]; 3961 u8 shampo_match_criteria_type[0x2]; 3962 u8 reservation_timeout[0x10]; 3963 3964 u8 reserved_at_140[0x40]; 3965 3966 struct mlx5_ifc_wq_bits wq; 3967 }; 3968 3969 enum { 3970 MLX5_RMPC_STATE_RDY = 0x1, 3971 MLX5_RMPC_STATE_ERR = 0x3, 3972 }; 3973 3974 struct mlx5_ifc_rmpc_bits { 3975 u8 reserved_at_0[0x8]; 3976 u8 state[0x4]; 3977 u8 reserved_at_c[0x14]; 3978 3979 u8 basic_cyclic_rcv_wqe[0x1]; 3980 u8 reserved_at_21[0x1f]; 3981 3982 u8 reserved_at_40[0x140]; 3983 3984 struct mlx5_ifc_wq_bits wq; 3985 }; 3986 3987 enum { 3988 VHCA_ID_TYPE_HW = 0, 3989 VHCA_ID_TYPE_SW = 1, 3990 }; 3991 3992 struct mlx5_ifc_nic_vport_context_bits { 3993 u8 reserved_at_0[0x5]; 3994 u8 min_wqe_inline_mode[0x3]; 3995 u8 reserved_at_8[0x15]; 3996 u8 disable_mc_local_lb[0x1]; 3997 u8 disable_uc_local_lb[0x1]; 3998 u8 roce_en[0x1]; 3999 4000 u8 arm_change_event[0x1]; 4001 u8 reserved_at_21[0x1a]; 4002 u8 event_on_mtu[0x1]; 4003 u8 event_on_promisc_change[0x1]; 4004 u8 event_on_vlan_change[0x1]; 4005 u8 event_on_mc_address_change[0x1]; 4006 u8 event_on_uc_address_change[0x1]; 4007 4008 u8 vhca_id_type[0x1]; 4009 u8 reserved_at_41[0xb]; 4010 u8 affiliation_criteria[0x4]; 4011 u8 affiliated_vhca_id[0x10]; 4012 4013 u8 reserved_at_60[0xd0]; 4014 4015 u8 mtu[0x10]; 4016 4017 u8 system_image_guid[0x40]; 4018 u8 port_guid[0x40]; 4019 u8 node_guid[0x40]; 4020 4021 u8 reserved_at_200[0x140]; 4022 u8 qkey_violation_counter[0x10]; 4023 u8 reserved_at_350[0x430]; 4024 4025 u8 promisc_uc[0x1]; 4026 u8 promisc_mc[0x1]; 4027 u8 promisc_all[0x1]; 4028 u8 reserved_at_783[0x2]; 4029 u8 allowed_list_type[0x3]; 4030 u8 reserved_at_788[0xc]; 4031 u8 allowed_list_size[0xc]; 4032 4033 struct mlx5_ifc_mac_address_layout_bits permanent_address; 4034 4035 u8 reserved_at_7e0[0x20]; 4036 4037 u8 current_uc_mac_address[][0x40]; 4038 }; 4039 4040 enum { 4041 MLX5_MKC_ACCESS_MODE_PA = 0x0, 4042 MLX5_MKC_ACCESS_MODE_MTT = 0x1, 4043 MLX5_MKC_ACCESS_MODE_KLMS = 0x2, 4044 MLX5_MKC_ACCESS_MODE_KSM = 0x3, 4045 MLX5_MKC_ACCESS_MODE_SW_ICM = 0x4, 4046 MLX5_MKC_ACCESS_MODE_MEMIC = 0x5, 4047 }; 4048 4049 struct mlx5_ifc_mkc_bits { 4050 u8 reserved_at_0[0x1]; 4051 u8 free[0x1]; 4052 u8 reserved_at_2[0x1]; 4053 u8 access_mode_4_2[0x3]; 4054 u8 reserved_at_6[0x7]; 4055 u8 relaxed_ordering_write[0x1]; 4056 u8 reserved_at_e[0x1]; 4057 u8 small_fence_on_rdma_read_response[0x1]; 4058 u8 umr_en[0x1]; 4059 u8 a[0x1]; 4060 u8 rw[0x1]; 4061 u8 rr[0x1]; 4062 u8 lw[0x1]; 4063 u8 lr[0x1]; 4064 u8 access_mode_1_0[0x2]; 4065 u8 reserved_at_18[0x2]; 4066 u8 ma_translation_mode[0x2]; 4067 u8 reserved_at_1c[0x4]; 4068 4069 u8 qpn[0x18]; 4070 u8 mkey_7_0[0x8]; 4071 4072 u8 reserved_at_40[0x20]; 4073 4074 u8 length64[0x1]; 4075 u8 bsf_en[0x1]; 4076 u8 sync_umr[0x1]; 4077 u8 reserved_at_63[0x2]; 4078 u8 expected_sigerr_count[0x1]; 4079 u8 reserved_at_66[0x1]; 4080 u8 en_rinval[0x1]; 4081 u8 pd[0x18]; 4082 4083 u8 start_addr[0x40]; 4084 4085 u8 len[0x40]; 4086 4087 u8 bsf_octword_size[0x20]; 4088 4089 u8 reserved_at_120[0x80]; 4090 4091 u8 translations_octword_size[0x20]; 4092 4093 u8 reserved_at_1c0[0x19]; 4094 u8 relaxed_ordering_read[0x1]; 4095 u8 reserved_at_1d9[0x1]; 4096 u8 log_page_size[0x5]; 4097 4098 u8 reserved_at_1e0[0x20]; 4099 }; 4100 4101 struct mlx5_ifc_pkey_bits { 4102 u8 reserved_at_0[0x10]; 4103 u8 pkey[0x10]; 4104 }; 4105 4106 struct mlx5_ifc_array128_auto_bits { 4107 u8 array128_auto[16][0x8]; 4108 }; 4109 4110 struct mlx5_ifc_hca_vport_context_bits { 4111 u8 field_select[0x20]; 4112 4113 u8 reserved_at_20[0xe0]; 4114 4115 u8 sm_virt_aware[0x1]; 4116 u8 has_smi[0x1]; 4117 u8 has_raw[0x1]; 4118 u8 grh_required[0x1]; 4119 u8 reserved_at_104[0xc]; 4120 u8 port_physical_state[0x4]; 4121 u8 vport_state_policy[0x4]; 4122 u8 port_state[0x4]; 4123 u8 vport_state[0x4]; 4124 4125 u8 reserved_at_120[0x20]; 4126 4127 u8 system_image_guid[0x40]; 4128 4129 u8 port_guid[0x40]; 4130 4131 u8 node_guid[0x40]; 4132 4133 u8 cap_mask1[0x20]; 4134 4135 u8 cap_mask1_field_select[0x20]; 4136 4137 u8 cap_mask2[0x20]; 4138 4139 u8 cap_mask2_field_select[0x20]; 4140 4141 u8 reserved_at_280[0x80]; 4142 4143 u8 lid[0x10]; 4144 u8 reserved_at_310[0x4]; 4145 u8 init_type_reply[0x4]; 4146 u8 lmc[0x3]; 4147 u8 subnet_timeout[0x5]; 4148 4149 u8 sm_lid[0x10]; 4150 u8 sm_sl[0x4]; 4151 u8 reserved_at_334[0xc]; 4152 4153 u8 qkey_violation_counter[0x10]; 4154 u8 pkey_violation_counter[0x10]; 4155 4156 u8 reserved_at_360[0xca0]; 4157 }; 4158 4159 struct mlx5_ifc_esw_vport_context_bits { 4160 u8 fdb_to_vport_reg_c[0x1]; 4161 u8 reserved_at_1[0x2]; 4162 u8 vport_svlan_strip[0x1]; 4163 u8 vport_cvlan_strip[0x1]; 4164 u8 vport_svlan_insert[0x1]; 4165 u8 vport_cvlan_insert[0x2]; 4166 u8 fdb_to_vport_reg_c_id[0x8]; 4167 u8 reserved_at_10[0x10]; 4168 4169 u8 reserved_at_20[0x20]; 4170 4171 u8 svlan_cfi[0x1]; 4172 u8 svlan_pcp[0x3]; 4173 u8 svlan_id[0xc]; 4174 u8 cvlan_cfi[0x1]; 4175 u8 cvlan_pcp[0x3]; 4176 u8 cvlan_id[0xc]; 4177 4178 u8 reserved_at_60[0x720]; 4179 4180 u8 sw_steering_vport_icm_address_rx[0x40]; 4181 4182 u8 sw_steering_vport_icm_address_tx[0x40]; 4183 }; 4184 4185 enum { 4186 MLX5_EQC_STATUS_OK = 0x0, 4187 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa, 4188 }; 4189 4190 enum { 4191 MLX5_EQC_ST_ARMED = 0x9, 4192 MLX5_EQC_ST_FIRED = 0xa, 4193 }; 4194 4195 struct mlx5_ifc_eqc_bits { 4196 u8 status[0x4]; 4197 u8 reserved_at_4[0x9]; 4198 u8 ec[0x1]; 4199 u8 oi[0x1]; 4200 u8 reserved_at_f[0x5]; 4201 u8 st[0x4]; 4202 u8 reserved_at_18[0x8]; 4203 4204 u8 reserved_at_20[0x20]; 4205 4206 u8 reserved_at_40[0x14]; 4207 u8 page_offset[0x6]; 4208 u8 reserved_at_5a[0x6]; 4209 4210 u8 reserved_at_60[0x3]; 4211 u8 log_eq_size[0x5]; 4212 u8 uar_page[0x18]; 4213 4214 u8 reserved_at_80[0x20]; 4215 4216 u8 reserved_at_a0[0x14]; 4217 u8 intr[0xc]; 4218 4219 u8 reserved_at_c0[0x3]; 4220 u8 log_page_size[0x5]; 4221 u8 reserved_at_c8[0x18]; 4222 4223 u8 reserved_at_e0[0x60]; 4224 4225 u8 reserved_at_140[0x8]; 4226 u8 consumer_counter[0x18]; 4227 4228 u8 reserved_at_160[0x8]; 4229 u8 producer_counter[0x18]; 4230 4231 u8 reserved_at_180[0x80]; 4232 }; 4233 4234 enum { 4235 MLX5_DCTC_STATE_ACTIVE = 0x0, 4236 MLX5_DCTC_STATE_DRAINING = 0x1, 4237 MLX5_DCTC_STATE_DRAINED = 0x2, 4238 }; 4239 4240 enum { 4241 MLX5_DCTC_CS_RES_DISABLE = 0x0, 4242 MLX5_DCTC_CS_RES_NA = 0x1, 4243 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2, 4244 }; 4245 4246 enum { 4247 MLX5_DCTC_MTU_256_BYTES = 0x1, 4248 MLX5_DCTC_MTU_512_BYTES = 0x2, 4249 MLX5_DCTC_MTU_1K_BYTES = 0x3, 4250 MLX5_DCTC_MTU_2K_BYTES = 0x4, 4251 MLX5_DCTC_MTU_4K_BYTES = 0x5, 4252 }; 4253 4254 struct mlx5_ifc_dctc_bits { 4255 u8 reserved_at_0[0x4]; 4256 u8 state[0x4]; 4257 u8 reserved_at_8[0x18]; 4258 4259 u8 reserved_at_20[0x8]; 4260 u8 user_index[0x18]; 4261 4262 u8 reserved_at_40[0x8]; 4263 u8 cqn[0x18]; 4264 4265 u8 counter_set_id[0x8]; 4266 u8 atomic_mode[0x4]; 4267 u8 rre[0x1]; 4268 u8 rwe[0x1]; 4269 u8 rae[0x1]; 4270 u8 atomic_like_write_en[0x1]; 4271 u8 latency_sensitive[0x1]; 4272 u8 rlky[0x1]; 4273 u8 free_ar[0x1]; 4274 u8 reserved_at_73[0xd]; 4275 4276 u8 reserved_at_80[0x8]; 4277 u8 cs_res[0x8]; 4278 u8 reserved_at_90[0x3]; 4279 u8 min_rnr_nak[0x5]; 4280 u8 reserved_at_98[0x8]; 4281 4282 u8 reserved_at_a0[0x8]; 4283 u8 srqn_xrqn[0x18]; 4284 4285 u8 reserved_at_c0[0x8]; 4286 u8 pd[0x18]; 4287 4288 u8 tclass[0x8]; 4289 u8 reserved_at_e8[0x4]; 4290 u8 flow_label[0x14]; 4291 4292 u8 dc_access_key[0x40]; 4293 4294 u8 reserved_at_140[0x5]; 4295 u8 mtu[0x3]; 4296 u8 port[0x8]; 4297 u8 pkey_index[0x10]; 4298 4299 u8 reserved_at_160[0x8]; 4300 u8 my_addr_index[0x8]; 4301 u8 reserved_at_170[0x8]; 4302 u8 hop_limit[0x8]; 4303 4304 u8 dc_access_key_violation_count[0x20]; 4305 4306 u8 reserved_at_1a0[0x14]; 4307 u8 dei_cfi[0x1]; 4308 u8 eth_prio[0x3]; 4309 u8 ecn[0x2]; 4310 u8 dscp[0x6]; 4311 4312 u8 reserved_at_1c0[0x20]; 4313 u8 ece[0x20]; 4314 }; 4315 4316 enum { 4317 MLX5_CQC_STATUS_OK = 0x0, 4318 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9, 4319 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa, 4320 }; 4321 4322 enum { 4323 MLX5_CQC_CQE_SZ_64_BYTES = 0x0, 4324 MLX5_CQC_CQE_SZ_128_BYTES = 0x1, 4325 }; 4326 4327 enum { 4328 MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED = 0x6, 4329 MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED = 0x9, 4330 MLX5_CQC_ST_FIRED = 0xa, 4331 }; 4332 4333 enum { 4334 MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0, 4335 MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1, 4336 MLX5_CQ_PERIOD_NUM_MODES 4337 }; 4338 4339 struct mlx5_ifc_cqc_bits { 4340 u8 status[0x4]; 4341 u8 reserved_at_4[0x2]; 4342 u8 dbr_umem_valid[0x1]; 4343 u8 apu_cq[0x1]; 4344 u8 cqe_sz[0x3]; 4345 u8 cc[0x1]; 4346 u8 reserved_at_c[0x1]; 4347 u8 scqe_break_moderation_en[0x1]; 4348 u8 oi[0x1]; 4349 u8 cq_period_mode[0x2]; 4350 u8 cqe_comp_en[0x1]; 4351 u8 mini_cqe_res_format[0x2]; 4352 u8 st[0x4]; 4353 u8 reserved_at_18[0x6]; 4354 u8 cqe_compression_layout[0x2]; 4355 4356 u8 reserved_at_20[0x20]; 4357 4358 u8 reserved_at_40[0x14]; 4359 u8 page_offset[0x6]; 4360 u8 reserved_at_5a[0x6]; 4361 4362 u8 reserved_at_60[0x3]; 4363 u8 log_cq_size[0x5]; 4364 u8 uar_page[0x18]; 4365 4366 u8 reserved_at_80[0x4]; 4367 u8 cq_period[0xc]; 4368 u8 cq_max_count[0x10]; 4369 4370 u8 c_eqn_or_apu_element[0x20]; 4371 4372 u8 reserved_at_c0[0x3]; 4373 u8 log_page_size[0x5]; 4374 u8 reserved_at_c8[0x18]; 4375 4376 u8 reserved_at_e0[0x20]; 4377 4378 u8 reserved_at_100[0x8]; 4379 u8 last_notified_index[0x18]; 4380 4381 u8 reserved_at_120[0x8]; 4382 u8 last_solicit_index[0x18]; 4383 4384 u8 reserved_at_140[0x8]; 4385 u8 consumer_counter[0x18]; 4386 4387 u8 reserved_at_160[0x8]; 4388 u8 producer_counter[0x18]; 4389 4390 u8 reserved_at_180[0x40]; 4391 4392 u8 dbr_addr[0x40]; 4393 }; 4394 4395 union mlx5_ifc_cong_control_roce_ecn_auto_bits { 4396 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp; 4397 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp; 4398 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np; 4399 struct mlx5_ifc_cong_control_r_roce_general_bits cong_control_r_roce_general; 4400 u8 reserved_at_0[0x800]; 4401 }; 4402 4403 struct mlx5_ifc_query_adapter_param_block_bits { 4404 u8 reserved_at_0[0xc0]; 4405 4406 u8 reserved_at_c0[0x8]; 4407 u8 ieee_vendor_id[0x18]; 4408 4409 u8 reserved_at_e0[0x10]; 4410 u8 vsd_vendor_id[0x10]; 4411 4412 u8 vsd[208][0x8]; 4413 4414 u8 vsd_contd_psid[16][0x8]; 4415 }; 4416 4417 enum { 4418 MLX5_XRQC_STATE_GOOD = 0x0, 4419 MLX5_XRQC_STATE_ERROR = 0x1, 4420 }; 4421 4422 enum { 4423 MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0, 4424 MLX5_XRQC_TOPOLOGY_TAG_MATCHING = 0x1, 4425 }; 4426 4427 enum { 4428 MLX5_XRQC_OFFLOAD_RNDV = 0x1, 4429 }; 4430 4431 struct mlx5_ifc_tag_matching_topology_context_bits { 4432 u8 log_matching_list_sz[0x4]; 4433 u8 reserved_at_4[0xc]; 4434 u8 append_next_index[0x10]; 4435 4436 u8 sw_phase_cnt[0x10]; 4437 u8 hw_phase_cnt[0x10]; 4438 4439 u8 reserved_at_40[0x40]; 4440 }; 4441 4442 struct mlx5_ifc_xrqc_bits { 4443 u8 state[0x4]; 4444 u8 rlkey[0x1]; 4445 u8 reserved_at_5[0xf]; 4446 u8 topology[0x4]; 4447 u8 reserved_at_18[0x4]; 4448 u8 offload[0x4]; 4449 4450 u8 reserved_at_20[0x8]; 4451 u8 user_index[0x18]; 4452 4453 u8 reserved_at_40[0x8]; 4454 u8 cqn[0x18]; 4455 4456 u8 reserved_at_60[0xa0]; 4457 4458 struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context; 4459 4460 u8 reserved_at_180[0x280]; 4461 4462 struct mlx5_ifc_wq_bits wq; 4463 }; 4464 4465 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits { 4466 struct mlx5_ifc_modify_field_select_bits modify_field_select; 4467 struct mlx5_ifc_resize_field_select_bits resize_field_select; 4468 u8 reserved_at_0[0x20]; 4469 }; 4470 4471 union mlx5_ifc_field_select_802_1_r_roce_auto_bits { 4472 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp; 4473 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp; 4474 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np; 4475 u8 reserved_at_0[0x20]; 4476 }; 4477 4478 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits { 4479 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 4480 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 4481 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 4482 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 4483 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 4484 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 4485 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout; 4486 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout; 4487 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 4488 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 4489 struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs; 4490 u8 reserved_at_0[0x7c0]; 4491 }; 4492 4493 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits { 4494 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout; 4495 u8 reserved_at_0[0x7c0]; 4496 }; 4497 4498 union mlx5_ifc_event_auto_bits { 4499 struct mlx5_ifc_comp_event_bits comp_event; 4500 struct mlx5_ifc_dct_events_bits dct_events; 4501 struct mlx5_ifc_qp_events_bits qp_events; 4502 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event; 4503 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event; 4504 struct mlx5_ifc_cq_error_bits cq_error; 4505 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged; 4506 struct mlx5_ifc_port_state_change_event_bits port_state_change_event; 4507 struct mlx5_ifc_gpio_event_bits gpio_event; 4508 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event; 4509 struct mlx5_ifc_stall_vl_event_bits stall_vl_event; 4510 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event; 4511 u8 reserved_at_0[0xe0]; 4512 }; 4513 4514 struct mlx5_ifc_health_buffer_bits { 4515 u8 reserved_at_0[0x100]; 4516 4517 u8 assert_existptr[0x20]; 4518 4519 u8 assert_callra[0x20]; 4520 4521 u8 reserved_at_140[0x20]; 4522 4523 u8 time[0x20]; 4524 4525 u8 fw_version[0x20]; 4526 4527 u8 hw_id[0x20]; 4528 4529 u8 rfr[0x1]; 4530 u8 reserved_at_1c1[0x3]; 4531 u8 valid[0x1]; 4532 u8 severity[0x3]; 4533 u8 reserved_at_1c8[0x18]; 4534 4535 u8 irisc_index[0x8]; 4536 u8 synd[0x8]; 4537 u8 ext_synd[0x10]; 4538 }; 4539 4540 struct mlx5_ifc_register_loopback_control_bits { 4541 u8 no_lb[0x1]; 4542 u8 reserved_at_1[0x7]; 4543 u8 port[0x8]; 4544 u8 reserved_at_10[0x10]; 4545 4546 u8 reserved_at_20[0x60]; 4547 }; 4548 4549 struct mlx5_ifc_vport_tc_element_bits { 4550 u8 traffic_class[0x4]; 4551 u8 reserved_at_4[0xc]; 4552 u8 vport_number[0x10]; 4553 }; 4554 4555 struct mlx5_ifc_vport_element_bits { 4556 u8 reserved_at_0[0x10]; 4557 u8 vport_number[0x10]; 4558 }; 4559 4560 enum { 4561 TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0, 4562 TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1, 4563 TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2, 4564 }; 4565 4566 struct mlx5_ifc_tsar_element_bits { 4567 u8 reserved_at_0[0x8]; 4568 u8 tsar_type[0x8]; 4569 u8 reserved_at_10[0x10]; 4570 }; 4571 4572 enum { 4573 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0, 4574 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1, 4575 }; 4576 4577 struct mlx5_ifc_teardown_hca_out_bits { 4578 u8 status[0x8]; 4579 u8 reserved_at_8[0x18]; 4580 4581 u8 syndrome[0x20]; 4582 4583 u8 reserved_at_40[0x3f]; 4584 4585 u8 state[0x1]; 4586 }; 4587 4588 enum { 4589 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0, 4590 MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE = 0x1, 4591 MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN = 0x2, 4592 }; 4593 4594 struct mlx5_ifc_teardown_hca_in_bits { 4595 u8 opcode[0x10]; 4596 u8 reserved_at_10[0x10]; 4597 4598 u8 reserved_at_20[0x10]; 4599 u8 op_mod[0x10]; 4600 4601 u8 reserved_at_40[0x10]; 4602 u8 profile[0x10]; 4603 4604 u8 reserved_at_60[0x20]; 4605 }; 4606 4607 struct mlx5_ifc_sqerr2rts_qp_out_bits { 4608 u8 status[0x8]; 4609 u8 reserved_at_8[0x18]; 4610 4611 u8 syndrome[0x20]; 4612 4613 u8 reserved_at_40[0x40]; 4614 }; 4615 4616 struct mlx5_ifc_sqerr2rts_qp_in_bits { 4617 u8 opcode[0x10]; 4618 u8 uid[0x10]; 4619 4620 u8 reserved_at_20[0x10]; 4621 u8 op_mod[0x10]; 4622 4623 u8 reserved_at_40[0x8]; 4624 u8 qpn[0x18]; 4625 4626 u8 reserved_at_60[0x20]; 4627 4628 u8 opt_param_mask[0x20]; 4629 4630 u8 reserved_at_a0[0x20]; 4631 4632 struct mlx5_ifc_qpc_bits qpc; 4633 4634 u8 reserved_at_800[0x80]; 4635 }; 4636 4637 struct mlx5_ifc_sqd2rts_qp_out_bits { 4638 u8 status[0x8]; 4639 u8 reserved_at_8[0x18]; 4640 4641 u8 syndrome[0x20]; 4642 4643 u8 reserved_at_40[0x40]; 4644 }; 4645 4646 struct mlx5_ifc_sqd2rts_qp_in_bits { 4647 u8 opcode[0x10]; 4648 u8 uid[0x10]; 4649 4650 u8 reserved_at_20[0x10]; 4651 u8 op_mod[0x10]; 4652 4653 u8 reserved_at_40[0x8]; 4654 u8 qpn[0x18]; 4655 4656 u8 reserved_at_60[0x20]; 4657 4658 u8 opt_param_mask[0x20]; 4659 4660 u8 reserved_at_a0[0x20]; 4661 4662 struct mlx5_ifc_qpc_bits qpc; 4663 4664 u8 reserved_at_800[0x80]; 4665 }; 4666 4667 struct mlx5_ifc_set_roce_address_out_bits { 4668 u8 status[0x8]; 4669 u8 reserved_at_8[0x18]; 4670 4671 u8 syndrome[0x20]; 4672 4673 u8 reserved_at_40[0x40]; 4674 }; 4675 4676 struct mlx5_ifc_set_roce_address_in_bits { 4677 u8 opcode[0x10]; 4678 u8 reserved_at_10[0x10]; 4679 4680 u8 reserved_at_20[0x10]; 4681 u8 op_mod[0x10]; 4682 4683 u8 roce_address_index[0x10]; 4684 u8 reserved_at_50[0xc]; 4685 u8 vhca_port_num[0x4]; 4686 4687 u8 reserved_at_60[0x20]; 4688 4689 struct mlx5_ifc_roce_addr_layout_bits roce_address; 4690 }; 4691 4692 struct mlx5_ifc_set_mad_demux_out_bits { 4693 u8 status[0x8]; 4694 u8 reserved_at_8[0x18]; 4695 4696 u8 syndrome[0x20]; 4697 4698 u8 reserved_at_40[0x40]; 4699 }; 4700 4701 enum { 4702 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0, 4703 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2, 4704 }; 4705 4706 struct mlx5_ifc_set_mad_demux_in_bits { 4707 u8 opcode[0x10]; 4708 u8 reserved_at_10[0x10]; 4709 4710 u8 reserved_at_20[0x10]; 4711 u8 op_mod[0x10]; 4712 4713 u8 reserved_at_40[0x20]; 4714 4715 u8 reserved_at_60[0x6]; 4716 u8 demux_mode[0x2]; 4717 u8 reserved_at_68[0x18]; 4718 }; 4719 4720 struct mlx5_ifc_set_l2_table_entry_out_bits { 4721 u8 status[0x8]; 4722 u8 reserved_at_8[0x18]; 4723 4724 u8 syndrome[0x20]; 4725 4726 u8 reserved_at_40[0x40]; 4727 }; 4728 4729 struct mlx5_ifc_set_l2_table_entry_in_bits { 4730 u8 opcode[0x10]; 4731 u8 reserved_at_10[0x10]; 4732 4733 u8 reserved_at_20[0x10]; 4734 u8 op_mod[0x10]; 4735 4736 u8 reserved_at_40[0x60]; 4737 4738 u8 reserved_at_a0[0x8]; 4739 u8 table_index[0x18]; 4740 4741 u8 reserved_at_c0[0x20]; 4742 4743 u8 reserved_at_e0[0x13]; 4744 u8 vlan_valid[0x1]; 4745 u8 vlan[0xc]; 4746 4747 struct mlx5_ifc_mac_address_layout_bits mac_address; 4748 4749 u8 reserved_at_140[0xc0]; 4750 }; 4751 4752 struct mlx5_ifc_set_issi_out_bits { 4753 u8 status[0x8]; 4754 u8 reserved_at_8[0x18]; 4755 4756 u8 syndrome[0x20]; 4757 4758 u8 reserved_at_40[0x40]; 4759 }; 4760 4761 struct mlx5_ifc_set_issi_in_bits { 4762 u8 opcode[0x10]; 4763 u8 reserved_at_10[0x10]; 4764 4765 u8 reserved_at_20[0x10]; 4766 u8 op_mod[0x10]; 4767 4768 u8 reserved_at_40[0x10]; 4769 u8 current_issi[0x10]; 4770 4771 u8 reserved_at_60[0x20]; 4772 }; 4773 4774 struct mlx5_ifc_set_hca_cap_out_bits { 4775 u8 status[0x8]; 4776 u8 reserved_at_8[0x18]; 4777 4778 u8 syndrome[0x20]; 4779 4780 u8 reserved_at_40[0x40]; 4781 }; 4782 4783 struct mlx5_ifc_set_hca_cap_in_bits { 4784 u8 opcode[0x10]; 4785 u8 reserved_at_10[0x10]; 4786 4787 u8 reserved_at_20[0x10]; 4788 u8 op_mod[0x10]; 4789 4790 u8 other_function[0x1]; 4791 u8 reserved_at_41[0xf]; 4792 u8 function_id[0x10]; 4793 4794 u8 reserved_at_60[0x20]; 4795 4796 union mlx5_ifc_hca_cap_union_bits capability; 4797 }; 4798 4799 enum { 4800 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0, 4801 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1, 4802 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2, 4803 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3, 4804 MLX5_SET_FTE_MODIFY_ENABLE_MASK_IPSEC_OBJ_ID = 0x4 4805 }; 4806 4807 struct mlx5_ifc_set_fte_out_bits { 4808 u8 status[0x8]; 4809 u8 reserved_at_8[0x18]; 4810 4811 u8 syndrome[0x20]; 4812 4813 u8 reserved_at_40[0x40]; 4814 }; 4815 4816 struct mlx5_ifc_set_fte_in_bits { 4817 u8 opcode[0x10]; 4818 u8 reserved_at_10[0x10]; 4819 4820 u8 reserved_at_20[0x10]; 4821 u8 op_mod[0x10]; 4822 4823 u8 other_vport[0x1]; 4824 u8 reserved_at_41[0xf]; 4825 u8 vport_number[0x10]; 4826 4827 u8 reserved_at_60[0x20]; 4828 4829 u8 table_type[0x8]; 4830 u8 reserved_at_88[0x18]; 4831 4832 u8 reserved_at_a0[0x8]; 4833 u8 table_id[0x18]; 4834 4835 u8 ignore_flow_level[0x1]; 4836 u8 reserved_at_c1[0x17]; 4837 u8 modify_enable_mask[0x8]; 4838 4839 u8 reserved_at_e0[0x20]; 4840 4841 u8 flow_index[0x20]; 4842 4843 u8 reserved_at_120[0xe0]; 4844 4845 struct mlx5_ifc_flow_context_bits flow_context; 4846 }; 4847 4848 struct mlx5_ifc_rts2rts_qp_out_bits { 4849 u8 status[0x8]; 4850 u8 reserved_at_8[0x18]; 4851 4852 u8 syndrome[0x20]; 4853 4854 u8 reserved_at_40[0x20]; 4855 u8 ece[0x20]; 4856 }; 4857 4858 struct mlx5_ifc_rts2rts_qp_in_bits { 4859 u8 opcode[0x10]; 4860 u8 uid[0x10]; 4861 4862 u8 reserved_at_20[0x10]; 4863 u8 op_mod[0x10]; 4864 4865 u8 reserved_at_40[0x8]; 4866 u8 qpn[0x18]; 4867 4868 u8 reserved_at_60[0x20]; 4869 4870 u8 opt_param_mask[0x20]; 4871 4872 u8 ece[0x20]; 4873 4874 struct mlx5_ifc_qpc_bits qpc; 4875 4876 u8 reserved_at_800[0x80]; 4877 }; 4878 4879 struct mlx5_ifc_rtr2rts_qp_out_bits { 4880 u8 status[0x8]; 4881 u8 reserved_at_8[0x18]; 4882 4883 u8 syndrome[0x20]; 4884 4885 u8 reserved_at_40[0x20]; 4886 u8 ece[0x20]; 4887 }; 4888 4889 struct mlx5_ifc_rtr2rts_qp_in_bits { 4890 u8 opcode[0x10]; 4891 u8 uid[0x10]; 4892 4893 u8 reserved_at_20[0x10]; 4894 u8 op_mod[0x10]; 4895 4896 u8 reserved_at_40[0x8]; 4897 u8 qpn[0x18]; 4898 4899 u8 reserved_at_60[0x20]; 4900 4901 u8 opt_param_mask[0x20]; 4902 4903 u8 ece[0x20]; 4904 4905 struct mlx5_ifc_qpc_bits qpc; 4906 4907 u8 reserved_at_800[0x80]; 4908 }; 4909 4910 struct mlx5_ifc_rst2init_qp_out_bits { 4911 u8 status[0x8]; 4912 u8 reserved_at_8[0x18]; 4913 4914 u8 syndrome[0x20]; 4915 4916 u8 reserved_at_40[0x20]; 4917 u8 ece[0x20]; 4918 }; 4919 4920 struct mlx5_ifc_rst2init_qp_in_bits { 4921 u8 opcode[0x10]; 4922 u8 uid[0x10]; 4923 4924 u8 reserved_at_20[0x10]; 4925 u8 op_mod[0x10]; 4926 4927 u8 reserved_at_40[0x8]; 4928 u8 qpn[0x18]; 4929 4930 u8 reserved_at_60[0x20]; 4931 4932 u8 opt_param_mask[0x20]; 4933 4934 u8 ece[0x20]; 4935 4936 struct mlx5_ifc_qpc_bits qpc; 4937 4938 u8 reserved_at_800[0x80]; 4939 }; 4940 4941 struct mlx5_ifc_query_xrq_out_bits { 4942 u8 status[0x8]; 4943 u8 reserved_at_8[0x18]; 4944 4945 u8 syndrome[0x20]; 4946 4947 u8 reserved_at_40[0x40]; 4948 4949 struct mlx5_ifc_xrqc_bits xrq_context; 4950 }; 4951 4952 struct mlx5_ifc_query_xrq_in_bits { 4953 u8 opcode[0x10]; 4954 u8 reserved_at_10[0x10]; 4955 4956 u8 reserved_at_20[0x10]; 4957 u8 op_mod[0x10]; 4958 4959 u8 reserved_at_40[0x8]; 4960 u8 xrqn[0x18]; 4961 4962 u8 reserved_at_60[0x20]; 4963 }; 4964 4965 struct mlx5_ifc_query_xrc_srq_out_bits { 4966 u8 status[0x8]; 4967 u8 reserved_at_8[0x18]; 4968 4969 u8 syndrome[0x20]; 4970 4971 u8 reserved_at_40[0x40]; 4972 4973 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 4974 4975 u8 reserved_at_280[0x600]; 4976 4977 u8 pas[][0x40]; 4978 }; 4979 4980 struct mlx5_ifc_query_xrc_srq_in_bits { 4981 u8 opcode[0x10]; 4982 u8 reserved_at_10[0x10]; 4983 4984 u8 reserved_at_20[0x10]; 4985 u8 op_mod[0x10]; 4986 4987 u8 reserved_at_40[0x8]; 4988 u8 xrc_srqn[0x18]; 4989 4990 u8 reserved_at_60[0x20]; 4991 }; 4992 4993 enum { 4994 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0, 4995 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1, 4996 }; 4997 4998 struct mlx5_ifc_query_vport_state_out_bits { 4999 u8 status[0x8]; 5000 u8 reserved_at_8[0x18]; 5001 5002 u8 syndrome[0x20]; 5003 5004 u8 reserved_at_40[0x20]; 5005 5006 u8 reserved_at_60[0x18]; 5007 u8 admin_state[0x4]; 5008 u8 state[0x4]; 5009 }; 5010 5011 enum { 5012 MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT = 0x0, 5013 MLX5_VPORT_STATE_OP_MOD_ESW_VPORT = 0x1, 5014 MLX5_VPORT_STATE_OP_MOD_UPLINK = 0x2, 5015 }; 5016 5017 struct mlx5_ifc_arm_monitor_counter_in_bits { 5018 u8 opcode[0x10]; 5019 u8 uid[0x10]; 5020 5021 u8 reserved_at_20[0x10]; 5022 u8 op_mod[0x10]; 5023 5024 u8 reserved_at_40[0x20]; 5025 5026 u8 reserved_at_60[0x20]; 5027 }; 5028 5029 struct mlx5_ifc_arm_monitor_counter_out_bits { 5030 u8 status[0x8]; 5031 u8 reserved_at_8[0x18]; 5032 5033 u8 syndrome[0x20]; 5034 5035 u8 reserved_at_40[0x40]; 5036 }; 5037 5038 enum { 5039 MLX5_QUERY_MONITOR_CNT_TYPE_PPCNT = 0x0, 5040 MLX5_QUERY_MONITOR_CNT_TYPE_Q_COUNTER = 0x1, 5041 }; 5042 5043 enum mlx5_monitor_counter_ppcnt { 5044 MLX5_QUERY_MONITOR_PPCNT_IN_RANGE_LENGTH_ERRORS = 0x0, 5045 MLX5_QUERY_MONITOR_PPCNT_OUT_OF_RANGE_LENGTH_FIELD = 0x1, 5046 MLX5_QUERY_MONITOR_PPCNT_FRAME_TOO_LONG_ERRORS = 0x2, 5047 MLX5_QUERY_MONITOR_PPCNT_FRAME_CHECK_SEQUENCE_ERRORS = 0x3, 5048 MLX5_QUERY_MONITOR_PPCNT_ALIGNMENT_ERRORS = 0x4, 5049 MLX5_QUERY_MONITOR_PPCNT_IF_OUT_DISCARDS = 0x5, 5050 }; 5051 5052 enum { 5053 MLX5_QUERY_MONITOR_Q_COUNTER_RX_OUT_OF_BUFFER = 0x4, 5054 }; 5055 5056 struct mlx5_ifc_monitor_counter_output_bits { 5057 u8 reserved_at_0[0x4]; 5058 u8 type[0x4]; 5059 u8 reserved_at_8[0x8]; 5060 u8 counter[0x10]; 5061 5062 u8 counter_group_id[0x20]; 5063 }; 5064 5065 #define MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 (6) 5066 #define MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1 (1) 5067 #define MLX5_CMD_SET_MONITOR_NUM_COUNTER (MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 +\ 5068 MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1) 5069 5070 struct mlx5_ifc_set_monitor_counter_in_bits { 5071 u8 opcode[0x10]; 5072 u8 uid[0x10]; 5073 5074 u8 reserved_at_20[0x10]; 5075 u8 op_mod[0x10]; 5076 5077 u8 reserved_at_40[0x10]; 5078 u8 num_of_counters[0x10]; 5079 5080 u8 reserved_at_60[0x20]; 5081 5082 struct mlx5_ifc_monitor_counter_output_bits monitor_counter[MLX5_CMD_SET_MONITOR_NUM_COUNTER]; 5083 }; 5084 5085 struct mlx5_ifc_set_monitor_counter_out_bits { 5086 u8 status[0x8]; 5087 u8 reserved_at_8[0x18]; 5088 5089 u8 syndrome[0x20]; 5090 5091 u8 reserved_at_40[0x40]; 5092 }; 5093 5094 struct mlx5_ifc_query_vport_state_in_bits { 5095 u8 opcode[0x10]; 5096 u8 reserved_at_10[0x10]; 5097 5098 u8 reserved_at_20[0x10]; 5099 u8 op_mod[0x10]; 5100 5101 u8 other_vport[0x1]; 5102 u8 reserved_at_41[0xf]; 5103 u8 vport_number[0x10]; 5104 5105 u8 reserved_at_60[0x20]; 5106 }; 5107 5108 struct mlx5_ifc_query_vnic_env_out_bits { 5109 u8 status[0x8]; 5110 u8 reserved_at_8[0x18]; 5111 5112 u8 syndrome[0x20]; 5113 5114 u8 reserved_at_40[0x40]; 5115 5116 struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env; 5117 }; 5118 5119 enum { 5120 MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS = 0x0, 5121 }; 5122 5123 struct mlx5_ifc_query_vnic_env_in_bits { 5124 u8 opcode[0x10]; 5125 u8 reserved_at_10[0x10]; 5126 5127 u8 reserved_at_20[0x10]; 5128 u8 op_mod[0x10]; 5129 5130 u8 other_vport[0x1]; 5131 u8 reserved_at_41[0xf]; 5132 u8 vport_number[0x10]; 5133 5134 u8 reserved_at_60[0x20]; 5135 }; 5136 5137 struct mlx5_ifc_query_vport_counter_out_bits { 5138 u8 status[0x8]; 5139 u8 reserved_at_8[0x18]; 5140 5141 u8 syndrome[0x20]; 5142 5143 u8 reserved_at_40[0x40]; 5144 5145 struct mlx5_ifc_traffic_counter_bits received_errors; 5146 5147 struct mlx5_ifc_traffic_counter_bits transmit_errors; 5148 5149 struct mlx5_ifc_traffic_counter_bits received_ib_unicast; 5150 5151 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast; 5152 5153 struct mlx5_ifc_traffic_counter_bits received_ib_multicast; 5154 5155 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast; 5156 5157 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast; 5158 5159 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast; 5160 5161 struct mlx5_ifc_traffic_counter_bits received_eth_unicast; 5162 5163 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast; 5164 5165 struct mlx5_ifc_traffic_counter_bits received_eth_multicast; 5166 5167 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast; 5168 5169 u8 reserved_at_680[0xa00]; 5170 }; 5171 5172 enum { 5173 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0, 5174 }; 5175 5176 struct mlx5_ifc_query_vport_counter_in_bits { 5177 u8 opcode[0x10]; 5178 u8 reserved_at_10[0x10]; 5179 5180 u8 reserved_at_20[0x10]; 5181 u8 op_mod[0x10]; 5182 5183 u8 other_vport[0x1]; 5184 u8 reserved_at_41[0xb]; 5185 u8 port_num[0x4]; 5186 u8 vport_number[0x10]; 5187 5188 u8 reserved_at_60[0x60]; 5189 5190 u8 clear[0x1]; 5191 u8 reserved_at_c1[0x1f]; 5192 5193 u8 reserved_at_e0[0x20]; 5194 }; 5195 5196 struct mlx5_ifc_query_tis_out_bits { 5197 u8 status[0x8]; 5198 u8 reserved_at_8[0x18]; 5199 5200 u8 syndrome[0x20]; 5201 5202 u8 reserved_at_40[0x40]; 5203 5204 struct mlx5_ifc_tisc_bits tis_context; 5205 }; 5206 5207 struct mlx5_ifc_query_tis_in_bits { 5208 u8 opcode[0x10]; 5209 u8 reserved_at_10[0x10]; 5210 5211 u8 reserved_at_20[0x10]; 5212 u8 op_mod[0x10]; 5213 5214 u8 reserved_at_40[0x8]; 5215 u8 tisn[0x18]; 5216 5217 u8 reserved_at_60[0x20]; 5218 }; 5219 5220 struct mlx5_ifc_query_tir_out_bits { 5221 u8 status[0x8]; 5222 u8 reserved_at_8[0x18]; 5223 5224 u8 syndrome[0x20]; 5225 5226 u8 reserved_at_40[0xc0]; 5227 5228 struct mlx5_ifc_tirc_bits tir_context; 5229 }; 5230 5231 struct mlx5_ifc_query_tir_in_bits { 5232 u8 opcode[0x10]; 5233 u8 reserved_at_10[0x10]; 5234 5235 u8 reserved_at_20[0x10]; 5236 u8 op_mod[0x10]; 5237 5238 u8 reserved_at_40[0x8]; 5239 u8 tirn[0x18]; 5240 5241 u8 reserved_at_60[0x20]; 5242 }; 5243 5244 struct mlx5_ifc_query_srq_out_bits { 5245 u8 status[0x8]; 5246 u8 reserved_at_8[0x18]; 5247 5248 u8 syndrome[0x20]; 5249 5250 u8 reserved_at_40[0x40]; 5251 5252 struct mlx5_ifc_srqc_bits srq_context_entry; 5253 5254 u8 reserved_at_280[0x600]; 5255 5256 u8 pas[][0x40]; 5257 }; 5258 5259 struct mlx5_ifc_query_srq_in_bits { 5260 u8 opcode[0x10]; 5261 u8 reserved_at_10[0x10]; 5262 5263 u8 reserved_at_20[0x10]; 5264 u8 op_mod[0x10]; 5265 5266 u8 reserved_at_40[0x8]; 5267 u8 srqn[0x18]; 5268 5269 u8 reserved_at_60[0x20]; 5270 }; 5271 5272 struct mlx5_ifc_query_sq_out_bits { 5273 u8 status[0x8]; 5274 u8 reserved_at_8[0x18]; 5275 5276 u8 syndrome[0x20]; 5277 5278 u8 reserved_at_40[0xc0]; 5279 5280 struct mlx5_ifc_sqc_bits sq_context; 5281 }; 5282 5283 struct mlx5_ifc_query_sq_in_bits { 5284 u8 opcode[0x10]; 5285 u8 reserved_at_10[0x10]; 5286 5287 u8 reserved_at_20[0x10]; 5288 u8 op_mod[0x10]; 5289 5290 u8 reserved_at_40[0x8]; 5291 u8 sqn[0x18]; 5292 5293 u8 reserved_at_60[0x20]; 5294 }; 5295 5296 struct mlx5_ifc_query_special_contexts_out_bits { 5297 u8 status[0x8]; 5298 u8 reserved_at_8[0x18]; 5299 5300 u8 syndrome[0x20]; 5301 5302 u8 dump_fill_mkey[0x20]; 5303 5304 u8 resd_lkey[0x20]; 5305 5306 u8 null_mkey[0x20]; 5307 5308 u8 terminate_scatter_list_mkey[0x20]; 5309 5310 u8 repeated_mkey[0x20]; 5311 5312 u8 reserved_at_a0[0x20]; 5313 }; 5314 5315 struct mlx5_ifc_query_special_contexts_in_bits { 5316 u8 opcode[0x10]; 5317 u8 reserved_at_10[0x10]; 5318 5319 u8 reserved_at_20[0x10]; 5320 u8 op_mod[0x10]; 5321 5322 u8 reserved_at_40[0x40]; 5323 }; 5324 5325 struct mlx5_ifc_query_scheduling_element_out_bits { 5326 u8 opcode[0x10]; 5327 u8 reserved_at_10[0x10]; 5328 5329 u8 reserved_at_20[0x10]; 5330 u8 op_mod[0x10]; 5331 5332 u8 reserved_at_40[0xc0]; 5333 5334 struct mlx5_ifc_scheduling_context_bits scheduling_context; 5335 5336 u8 reserved_at_300[0x100]; 5337 }; 5338 5339 enum { 5340 SCHEDULING_HIERARCHY_E_SWITCH = 0x2, 5341 SCHEDULING_HIERARCHY_NIC = 0x3, 5342 }; 5343 5344 struct mlx5_ifc_query_scheduling_element_in_bits { 5345 u8 opcode[0x10]; 5346 u8 reserved_at_10[0x10]; 5347 5348 u8 reserved_at_20[0x10]; 5349 u8 op_mod[0x10]; 5350 5351 u8 scheduling_hierarchy[0x8]; 5352 u8 reserved_at_48[0x18]; 5353 5354 u8 scheduling_element_id[0x20]; 5355 5356 u8 reserved_at_80[0x180]; 5357 }; 5358 5359 struct mlx5_ifc_query_rqt_out_bits { 5360 u8 status[0x8]; 5361 u8 reserved_at_8[0x18]; 5362 5363 u8 syndrome[0x20]; 5364 5365 u8 reserved_at_40[0xc0]; 5366 5367 struct mlx5_ifc_rqtc_bits rqt_context; 5368 }; 5369 5370 struct mlx5_ifc_query_rqt_in_bits { 5371 u8 opcode[0x10]; 5372 u8 reserved_at_10[0x10]; 5373 5374 u8 reserved_at_20[0x10]; 5375 u8 op_mod[0x10]; 5376 5377 u8 reserved_at_40[0x8]; 5378 u8 rqtn[0x18]; 5379 5380 u8 reserved_at_60[0x20]; 5381 }; 5382 5383 struct mlx5_ifc_query_rq_out_bits { 5384 u8 status[0x8]; 5385 u8 reserved_at_8[0x18]; 5386 5387 u8 syndrome[0x20]; 5388 5389 u8 reserved_at_40[0xc0]; 5390 5391 struct mlx5_ifc_rqc_bits rq_context; 5392 }; 5393 5394 struct mlx5_ifc_query_rq_in_bits { 5395 u8 opcode[0x10]; 5396 u8 reserved_at_10[0x10]; 5397 5398 u8 reserved_at_20[0x10]; 5399 u8 op_mod[0x10]; 5400 5401 u8 reserved_at_40[0x8]; 5402 u8 rqn[0x18]; 5403 5404 u8 reserved_at_60[0x20]; 5405 }; 5406 5407 struct mlx5_ifc_query_roce_address_out_bits { 5408 u8 status[0x8]; 5409 u8 reserved_at_8[0x18]; 5410 5411 u8 syndrome[0x20]; 5412 5413 u8 reserved_at_40[0x40]; 5414 5415 struct mlx5_ifc_roce_addr_layout_bits roce_address; 5416 }; 5417 5418 struct mlx5_ifc_query_roce_address_in_bits { 5419 u8 opcode[0x10]; 5420 u8 reserved_at_10[0x10]; 5421 5422 u8 reserved_at_20[0x10]; 5423 u8 op_mod[0x10]; 5424 5425 u8 roce_address_index[0x10]; 5426 u8 reserved_at_50[0xc]; 5427 u8 vhca_port_num[0x4]; 5428 5429 u8 reserved_at_60[0x20]; 5430 }; 5431 5432 struct mlx5_ifc_query_rmp_out_bits { 5433 u8 status[0x8]; 5434 u8 reserved_at_8[0x18]; 5435 5436 u8 syndrome[0x20]; 5437 5438 u8 reserved_at_40[0xc0]; 5439 5440 struct mlx5_ifc_rmpc_bits rmp_context; 5441 }; 5442 5443 struct mlx5_ifc_query_rmp_in_bits { 5444 u8 opcode[0x10]; 5445 u8 reserved_at_10[0x10]; 5446 5447 u8 reserved_at_20[0x10]; 5448 u8 op_mod[0x10]; 5449 5450 u8 reserved_at_40[0x8]; 5451 u8 rmpn[0x18]; 5452 5453 u8 reserved_at_60[0x20]; 5454 }; 5455 5456 struct mlx5_ifc_cqe_error_syndrome_bits { 5457 u8 hw_error_syndrome[0x8]; 5458 u8 hw_syndrome_type[0x4]; 5459 u8 reserved_at_c[0x4]; 5460 u8 vendor_error_syndrome[0x8]; 5461 u8 syndrome[0x8]; 5462 }; 5463 5464 struct mlx5_ifc_qp_context_extension_bits { 5465 u8 reserved_at_0[0x60]; 5466 5467 struct mlx5_ifc_cqe_error_syndrome_bits error_syndrome; 5468 5469 u8 reserved_at_80[0x580]; 5470 }; 5471 5472 struct mlx5_ifc_qpc_extension_and_pas_list_in_bits { 5473 struct mlx5_ifc_qp_context_extension_bits qpc_data_extension; 5474 5475 u8 pas[0][0x40]; 5476 }; 5477 5478 struct mlx5_ifc_qp_pas_list_in_bits { 5479 struct mlx5_ifc_cmd_pas_bits pas[0]; 5480 }; 5481 5482 union mlx5_ifc_qp_pas_or_qpc_ext_and_pas_bits { 5483 struct mlx5_ifc_qp_pas_list_in_bits qp_pas_list; 5484 struct mlx5_ifc_qpc_extension_and_pas_list_in_bits qpc_ext_and_pas_list; 5485 }; 5486 5487 struct mlx5_ifc_query_qp_out_bits { 5488 u8 status[0x8]; 5489 u8 reserved_at_8[0x18]; 5490 5491 u8 syndrome[0x20]; 5492 5493 u8 reserved_at_40[0x40]; 5494 5495 u8 opt_param_mask[0x20]; 5496 5497 u8 ece[0x20]; 5498 5499 struct mlx5_ifc_qpc_bits qpc; 5500 5501 u8 reserved_at_800[0x80]; 5502 5503 union mlx5_ifc_qp_pas_or_qpc_ext_and_pas_bits qp_pas_or_qpc_ext_and_pas; 5504 }; 5505 5506 struct mlx5_ifc_query_qp_in_bits { 5507 u8 opcode[0x10]; 5508 u8 reserved_at_10[0x10]; 5509 5510 u8 reserved_at_20[0x10]; 5511 u8 op_mod[0x10]; 5512 5513 u8 qpc_ext[0x1]; 5514 u8 reserved_at_41[0x7]; 5515 u8 qpn[0x18]; 5516 5517 u8 reserved_at_60[0x20]; 5518 }; 5519 5520 struct mlx5_ifc_query_q_counter_out_bits { 5521 u8 status[0x8]; 5522 u8 reserved_at_8[0x18]; 5523 5524 u8 syndrome[0x20]; 5525 5526 u8 reserved_at_40[0x40]; 5527 5528 u8 rx_write_requests[0x20]; 5529 5530 u8 reserved_at_a0[0x20]; 5531 5532 u8 rx_read_requests[0x20]; 5533 5534 u8 reserved_at_e0[0x20]; 5535 5536 u8 rx_atomic_requests[0x20]; 5537 5538 u8 reserved_at_120[0x20]; 5539 5540 u8 rx_dct_connect[0x20]; 5541 5542 u8 reserved_at_160[0x20]; 5543 5544 u8 out_of_buffer[0x20]; 5545 5546 u8 reserved_at_1a0[0x20]; 5547 5548 u8 out_of_sequence[0x20]; 5549 5550 u8 reserved_at_1e0[0x20]; 5551 5552 u8 duplicate_request[0x20]; 5553 5554 u8 reserved_at_220[0x20]; 5555 5556 u8 rnr_nak_retry_err[0x20]; 5557 5558 u8 reserved_at_260[0x20]; 5559 5560 u8 packet_seq_err[0x20]; 5561 5562 u8 reserved_at_2a0[0x20]; 5563 5564 u8 implied_nak_seq_err[0x20]; 5565 5566 u8 reserved_at_2e0[0x20]; 5567 5568 u8 local_ack_timeout_err[0x20]; 5569 5570 u8 reserved_at_320[0xa0]; 5571 5572 u8 resp_local_length_error[0x20]; 5573 5574 u8 req_local_length_error[0x20]; 5575 5576 u8 resp_local_qp_error[0x20]; 5577 5578 u8 local_operation_error[0x20]; 5579 5580 u8 resp_local_protection[0x20]; 5581 5582 u8 req_local_protection[0x20]; 5583 5584 u8 resp_cqe_error[0x20]; 5585 5586 u8 req_cqe_error[0x20]; 5587 5588 u8 req_mw_binding[0x20]; 5589 5590 u8 req_bad_response[0x20]; 5591 5592 u8 req_remote_invalid_request[0x20]; 5593 5594 u8 resp_remote_invalid_request[0x20]; 5595 5596 u8 req_remote_access_errors[0x20]; 5597 5598 u8 resp_remote_access_errors[0x20]; 5599 5600 u8 req_remote_operation_errors[0x20]; 5601 5602 u8 req_transport_retries_exceeded[0x20]; 5603 5604 u8 cq_overflow[0x20]; 5605 5606 u8 resp_cqe_flush_error[0x20]; 5607 5608 u8 req_cqe_flush_error[0x20]; 5609 5610 u8 reserved_at_620[0x20]; 5611 5612 u8 roce_adp_retrans[0x20]; 5613 5614 u8 roce_adp_retrans_to[0x20]; 5615 5616 u8 roce_slow_restart[0x20]; 5617 5618 u8 roce_slow_restart_cnps[0x20]; 5619 5620 u8 roce_slow_restart_trans[0x20]; 5621 5622 u8 reserved_at_6e0[0x120]; 5623 }; 5624 5625 struct mlx5_ifc_query_q_counter_in_bits { 5626 u8 opcode[0x10]; 5627 u8 reserved_at_10[0x10]; 5628 5629 u8 reserved_at_20[0x10]; 5630 u8 op_mod[0x10]; 5631 5632 u8 reserved_at_40[0x80]; 5633 5634 u8 clear[0x1]; 5635 u8 reserved_at_c1[0x1f]; 5636 5637 u8 reserved_at_e0[0x18]; 5638 u8 counter_set_id[0x8]; 5639 }; 5640 5641 struct mlx5_ifc_query_pages_out_bits { 5642 u8 status[0x8]; 5643 u8 reserved_at_8[0x18]; 5644 5645 u8 syndrome[0x20]; 5646 5647 u8 embedded_cpu_function[0x1]; 5648 u8 reserved_at_41[0xf]; 5649 u8 function_id[0x10]; 5650 5651 u8 num_pages[0x20]; 5652 }; 5653 5654 enum { 5655 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1, 5656 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2, 5657 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3, 5658 }; 5659 5660 struct mlx5_ifc_query_pages_in_bits { 5661 u8 opcode[0x10]; 5662 u8 reserved_at_10[0x10]; 5663 5664 u8 reserved_at_20[0x10]; 5665 u8 op_mod[0x10]; 5666 5667 u8 embedded_cpu_function[0x1]; 5668 u8 reserved_at_41[0xf]; 5669 u8 function_id[0x10]; 5670 5671 u8 reserved_at_60[0x20]; 5672 }; 5673 5674 struct mlx5_ifc_query_nic_vport_context_out_bits { 5675 u8 status[0x8]; 5676 u8 reserved_at_8[0x18]; 5677 5678 u8 syndrome[0x20]; 5679 5680 u8 reserved_at_40[0x40]; 5681 5682 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 5683 }; 5684 5685 struct mlx5_ifc_query_nic_vport_context_in_bits { 5686 u8 opcode[0x10]; 5687 u8 reserved_at_10[0x10]; 5688 5689 u8 reserved_at_20[0x10]; 5690 u8 op_mod[0x10]; 5691 5692 u8 other_vport[0x1]; 5693 u8 reserved_at_41[0xf]; 5694 u8 vport_number[0x10]; 5695 5696 u8 reserved_at_60[0x5]; 5697 u8 allowed_list_type[0x3]; 5698 u8 reserved_at_68[0x18]; 5699 }; 5700 5701 struct mlx5_ifc_query_mkey_out_bits { 5702 u8 status[0x8]; 5703 u8 reserved_at_8[0x18]; 5704 5705 u8 syndrome[0x20]; 5706 5707 u8 reserved_at_40[0x40]; 5708 5709 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 5710 5711 u8 reserved_at_280[0x600]; 5712 5713 u8 bsf0_klm0_pas_mtt0_1[16][0x8]; 5714 5715 u8 bsf1_klm1_pas_mtt2_3[16][0x8]; 5716 }; 5717 5718 struct mlx5_ifc_query_mkey_in_bits { 5719 u8 opcode[0x10]; 5720 u8 reserved_at_10[0x10]; 5721 5722 u8 reserved_at_20[0x10]; 5723 u8 op_mod[0x10]; 5724 5725 u8 reserved_at_40[0x8]; 5726 u8 mkey_index[0x18]; 5727 5728 u8 pg_access[0x1]; 5729 u8 reserved_at_61[0x1f]; 5730 }; 5731 5732 struct mlx5_ifc_query_mad_demux_out_bits { 5733 u8 status[0x8]; 5734 u8 reserved_at_8[0x18]; 5735 5736 u8 syndrome[0x20]; 5737 5738 u8 reserved_at_40[0x40]; 5739 5740 u8 mad_dumux_parameters_block[0x20]; 5741 }; 5742 5743 struct mlx5_ifc_query_mad_demux_in_bits { 5744 u8 opcode[0x10]; 5745 u8 reserved_at_10[0x10]; 5746 5747 u8 reserved_at_20[0x10]; 5748 u8 op_mod[0x10]; 5749 5750 u8 reserved_at_40[0x40]; 5751 }; 5752 5753 struct mlx5_ifc_query_l2_table_entry_out_bits { 5754 u8 status[0x8]; 5755 u8 reserved_at_8[0x18]; 5756 5757 u8 syndrome[0x20]; 5758 5759 u8 reserved_at_40[0xa0]; 5760 5761 u8 reserved_at_e0[0x13]; 5762 u8 vlan_valid[0x1]; 5763 u8 vlan[0xc]; 5764 5765 struct mlx5_ifc_mac_address_layout_bits mac_address; 5766 5767 u8 reserved_at_140[0xc0]; 5768 }; 5769 5770 struct mlx5_ifc_query_l2_table_entry_in_bits { 5771 u8 opcode[0x10]; 5772 u8 reserved_at_10[0x10]; 5773 5774 u8 reserved_at_20[0x10]; 5775 u8 op_mod[0x10]; 5776 5777 u8 reserved_at_40[0x60]; 5778 5779 u8 reserved_at_a0[0x8]; 5780 u8 table_index[0x18]; 5781 5782 u8 reserved_at_c0[0x140]; 5783 }; 5784 5785 struct mlx5_ifc_query_issi_out_bits { 5786 u8 status[0x8]; 5787 u8 reserved_at_8[0x18]; 5788 5789 u8 syndrome[0x20]; 5790 5791 u8 reserved_at_40[0x10]; 5792 u8 current_issi[0x10]; 5793 5794 u8 reserved_at_60[0xa0]; 5795 5796 u8 reserved_at_100[76][0x8]; 5797 u8 supported_issi_dw0[0x20]; 5798 }; 5799 5800 struct mlx5_ifc_query_issi_in_bits { 5801 u8 opcode[0x10]; 5802 u8 reserved_at_10[0x10]; 5803 5804 u8 reserved_at_20[0x10]; 5805 u8 op_mod[0x10]; 5806 5807 u8 reserved_at_40[0x40]; 5808 }; 5809 5810 struct mlx5_ifc_set_driver_version_out_bits { 5811 u8 status[0x8]; 5812 u8 reserved_0[0x18]; 5813 5814 u8 syndrome[0x20]; 5815 u8 reserved_1[0x40]; 5816 }; 5817 5818 struct mlx5_ifc_set_driver_version_in_bits { 5819 u8 opcode[0x10]; 5820 u8 reserved_0[0x10]; 5821 5822 u8 reserved_1[0x10]; 5823 u8 op_mod[0x10]; 5824 5825 u8 reserved_2[0x40]; 5826 u8 driver_version[64][0x8]; 5827 }; 5828 5829 struct mlx5_ifc_query_hca_vport_pkey_out_bits { 5830 u8 status[0x8]; 5831 u8 reserved_at_8[0x18]; 5832 5833 u8 syndrome[0x20]; 5834 5835 u8 reserved_at_40[0x40]; 5836 5837 struct mlx5_ifc_pkey_bits pkey[]; 5838 }; 5839 5840 struct mlx5_ifc_query_hca_vport_pkey_in_bits { 5841 u8 opcode[0x10]; 5842 u8 reserved_at_10[0x10]; 5843 5844 u8 reserved_at_20[0x10]; 5845 u8 op_mod[0x10]; 5846 5847 u8 other_vport[0x1]; 5848 u8 reserved_at_41[0xb]; 5849 u8 port_num[0x4]; 5850 u8 vport_number[0x10]; 5851 5852 u8 reserved_at_60[0x10]; 5853 u8 pkey_index[0x10]; 5854 }; 5855 5856 enum { 5857 MLX5_HCA_VPORT_SEL_PORT_GUID = 1 << 0, 5858 MLX5_HCA_VPORT_SEL_NODE_GUID = 1 << 1, 5859 MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2, 5860 }; 5861 5862 struct mlx5_ifc_query_hca_vport_gid_out_bits { 5863 u8 status[0x8]; 5864 u8 reserved_at_8[0x18]; 5865 5866 u8 syndrome[0x20]; 5867 5868 u8 reserved_at_40[0x20]; 5869 5870 u8 gids_num[0x10]; 5871 u8 reserved_at_70[0x10]; 5872 5873 struct mlx5_ifc_array128_auto_bits gid[]; 5874 }; 5875 5876 struct mlx5_ifc_query_hca_vport_gid_in_bits { 5877 u8 opcode[0x10]; 5878 u8 reserved_at_10[0x10]; 5879 5880 u8 reserved_at_20[0x10]; 5881 u8 op_mod[0x10]; 5882 5883 u8 other_vport[0x1]; 5884 u8 reserved_at_41[0xb]; 5885 u8 port_num[0x4]; 5886 u8 vport_number[0x10]; 5887 5888 u8 reserved_at_60[0x10]; 5889 u8 gid_index[0x10]; 5890 }; 5891 5892 struct mlx5_ifc_query_hca_vport_context_out_bits { 5893 u8 status[0x8]; 5894 u8 reserved_at_8[0x18]; 5895 5896 u8 syndrome[0x20]; 5897 5898 u8 reserved_at_40[0x40]; 5899 5900 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 5901 }; 5902 5903 struct mlx5_ifc_query_hca_vport_context_in_bits { 5904 u8 opcode[0x10]; 5905 u8 reserved_at_10[0x10]; 5906 5907 u8 reserved_at_20[0x10]; 5908 u8 op_mod[0x10]; 5909 5910 u8 other_vport[0x1]; 5911 u8 reserved_at_41[0xb]; 5912 u8 port_num[0x4]; 5913 u8 vport_number[0x10]; 5914 5915 u8 reserved_at_60[0x20]; 5916 }; 5917 5918 struct mlx5_ifc_query_hca_cap_out_bits { 5919 u8 status[0x8]; 5920 u8 reserved_at_8[0x18]; 5921 5922 u8 syndrome[0x20]; 5923 5924 u8 reserved_at_40[0x40]; 5925 5926 union mlx5_ifc_hca_cap_union_bits capability; 5927 }; 5928 5929 struct mlx5_ifc_query_hca_cap_in_bits { 5930 u8 opcode[0x10]; 5931 u8 reserved_at_10[0x10]; 5932 5933 u8 reserved_at_20[0x10]; 5934 u8 op_mod[0x10]; 5935 5936 u8 other_function[0x1]; 5937 u8 reserved_at_41[0xf]; 5938 u8 function_id[0x10]; 5939 5940 u8 reserved_at_60[0x20]; 5941 }; 5942 5943 struct mlx5_ifc_other_hca_cap_bits { 5944 u8 roce[0x1]; 5945 u8 reserved_at_1[0x27f]; 5946 }; 5947 5948 struct mlx5_ifc_query_other_hca_cap_out_bits { 5949 u8 status[0x8]; 5950 u8 reserved_at_8[0x18]; 5951 5952 u8 syndrome[0x20]; 5953 5954 u8 reserved_at_40[0x40]; 5955 5956 struct mlx5_ifc_other_hca_cap_bits other_capability; 5957 }; 5958 5959 struct mlx5_ifc_query_other_hca_cap_in_bits { 5960 u8 opcode[0x10]; 5961 u8 reserved_at_10[0x10]; 5962 5963 u8 reserved_at_20[0x10]; 5964 u8 op_mod[0x10]; 5965 5966 u8 reserved_at_40[0x10]; 5967 u8 function_id[0x10]; 5968 5969 u8 reserved_at_60[0x20]; 5970 }; 5971 5972 struct mlx5_ifc_modify_other_hca_cap_out_bits { 5973 u8 status[0x8]; 5974 u8 reserved_at_8[0x18]; 5975 5976 u8 syndrome[0x20]; 5977 5978 u8 reserved_at_40[0x40]; 5979 }; 5980 5981 struct mlx5_ifc_modify_other_hca_cap_in_bits { 5982 u8 opcode[0x10]; 5983 u8 reserved_at_10[0x10]; 5984 5985 u8 reserved_at_20[0x10]; 5986 u8 op_mod[0x10]; 5987 5988 u8 reserved_at_40[0x10]; 5989 u8 function_id[0x10]; 5990 u8 field_select[0x20]; 5991 5992 struct mlx5_ifc_other_hca_cap_bits other_capability; 5993 }; 5994 5995 struct mlx5_ifc_flow_table_context_bits { 5996 u8 reformat_en[0x1]; 5997 u8 decap_en[0x1]; 5998 u8 sw_owner[0x1]; 5999 u8 termination_table[0x1]; 6000 u8 table_miss_action[0x4]; 6001 u8 level[0x8]; 6002 u8 reserved_at_10[0x8]; 6003 u8 log_size[0x8]; 6004 6005 u8 reserved_at_20[0x8]; 6006 u8 table_miss_id[0x18]; 6007 6008 u8 reserved_at_40[0x8]; 6009 u8 lag_master_next_table_id[0x18]; 6010 6011 u8 reserved_at_60[0x60]; 6012 6013 u8 sw_owner_icm_root_1[0x40]; 6014 6015 u8 sw_owner_icm_root_0[0x40]; 6016 6017 }; 6018 6019 struct mlx5_ifc_query_flow_table_out_bits { 6020 u8 status[0x8]; 6021 u8 reserved_at_8[0x18]; 6022 6023 u8 syndrome[0x20]; 6024 6025 u8 reserved_at_40[0x80]; 6026 6027 struct mlx5_ifc_flow_table_context_bits flow_table_context; 6028 }; 6029 6030 struct mlx5_ifc_query_flow_table_in_bits { 6031 u8 opcode[0x10]; 6032 u8 reserved_at_10[0x10]; 6033 6034 u8 reserved_at_20[0x10]; 6035 u8 op_mod[0x10]; 6036 6037 u8 reserved_at_40[0x40]; 6038 6039 u8 table_type[0x8]; 6040 u8 reserved_at_88[0x18]; 6041 6042 u8 reserved_at_a0[0x8]; 6043 u8 table_id[0x18]; 6044 6045 u8 reserved_at_c0[0x140]; 6046 }; 6047 6048 struct mlx5_ifc_query_fte_out_bits { 6049 u8 status[0x8]; 6050 u8 reserved_at_8[0x18]; 6051 6052 u8 syndrome[0x20]; 6053 6054 u8 reserved_at_40[0x1c0]; 6055 6056 struct mlx5_ifc_flow_context_bits flow_context; 6057 }; 6058 6059 struct mlx5_ifc_query_fte_in_bits { 6060 u8 opcode[0x10]; 6061 u8 reserved_at_10[0x10]; 6062 6063 u8 reserved_at_20[0x10]; 6064 u8 op_mod[0x10]; 6065 6066 u8 reserved_at_40[0x40]; 6067 6068 u8 table_type[0x8]; 6069 u8 reserved_at_88[0x18]; 6070 6071 u8 reserved_at_a0[0x8]; 6072 u8 table_id[0x18]; 6073 6074 u8 reserved_at_c0[0x40]; 6075 6076 u8 flow_index[0x20]; 6077 6078 u8 reserved_at_120[0xe0]; 6079 }; 6080 6081 struct mlx5_ifc_match_definer_format_0_bits { 6082 u8 reserved_at_0[0x100]; 6083 6084 u8 metadata_reg_c_0[0x20]; 6085 6086 u8 metadata_reg_c_1[0x20]; 6087 6088 u8 outer_dmac_47_16[0x20]; 6089 6090 u8 outer_dmac_15_0[0x10]; 6091 u8 outer_ethertype[0x10]; 6092 6093 u8 reserved_at_180[0x1]; 6094 u8 sx_sniffer[0x1]; 6095 u8 functional_lb[0x1]; 6096 u8 outer_ip_frag[0x1]; 6097 u8 outer_qp_type[0x2]; 6098 u8 outer_encap_type[0x2]; 6099 u8 port_number[0x2]; 6100 u8 outer_l3_type[0x2]; 6101 u8 outer_l4_type[0x2]; 6102 u8 outer_first_vlan_type[0x2]; 6103 u8 outer_first_vlan_prio[0x3]; 6104 u8 outer_first_vlan_cfi[0x1]; 6105 u8 outer_first_vlan_vid[0xc]; 6106 6107 u8 outer_l4_type_ext[0x4]; 6108 u8 reserved_at_1a4[0x2]; 6109 u8 outer_ipsec_layer[0x2]; 6110 u8 outer_l2_type[0x2]; 6111 u8 force_lb[0x1]; 6112 u8 outer_l2_ok[0x1]; 6113 u8 outer_l3_ok[0x1]; 6114 u8 outer_l4_ok[0x1]; 6115 u8 outer_second_vlan_type[0x2]; 6116 u8 outer_second_vlan_prio[0x3]; 6117 u8 outer_second_vlan_cfi[0x1]; 6118 u8 outer_second_vlan_vid[0xc]; 6119 6120 u8 outer_smac_47_16[0x20]; 6121 6122 u8 outer_smac_15_0[0x10]; 6123 u8 inner_ipv4_checksum_ok[0x1]; 6124 u8 inner_l4_checksum_ok[0x1]; 6125 u8 outer_ipv4_checksum_ok[0x1]; 6126 u8 outer_l4_checksum_ok[0x1]; 6127 u8 inner_l3_ok[0x1]; 6128 u8 inner_l4_ok[0x1]; 6129 u8 outer_l3_ok_duplicate[0x1]; 6130 u8 outer_l4_ok_duplicate[0x1]; 6131 u8 outer_tcp_cwr[0x1]; 6132 u8 outer_tcp_ece[0x1]; 6133 u8 outer_tcp_urg[0x1]; 6134 u8 outer_tcp_ack[0x1]; 6135 u8 outer_tcp_psh[0x1]; 6136 u8 outer_tcp_rst[0x1]; 6137 u8 outer_tcp_syn[0x1]; 6138 u8 outer_tcp_fin[0x1]; 6139 }; 6140 6141 struct mlx5_ifc_match_definer_format_22_bits { 6142 u8 reserved_at_0[0x100]; 6143 6144 u8 outer_ip_src_addr[0x20]; 6145 6146 u8 outer_ip_dest_addr[0x20]; 6147 6148 u8 outer_l4_sport[0x10]; 6149 u8 outer_l4_dport[0x10]; 6150 6151 u8 reserved_at_160[0x1]; 6152 u8 sx_sniffer[0x1]; 6153 u8 functional_lb[0x1]; 6154 u8 outer_ip_frag[0x1]; 6155 u8 outer_qp_type[0x2]; 6156 u8 outer_encap_type[0x2]; 6157 u8 port_number[0x2]; 6158 u8 outer_l3_type[0x2]; 6159 u8 outer_l4_type[0x2]; 6160 u8 outer_first_vlan_type[0x2]; 6161 u8 outer_first_vlan_prio[0x3]; 6162 u8 outer_first_vlan_cfi[0x1]; 6163 u8 outer_first_vlan_vid[0xc]; 6164 6165 u8 metadata_reg_c_0[0x20]; 6166 6167 u8 outer_dmac_47_16[0x20]; 6168 6169 u8 outer_smac_47_16[0x20]; 6170 6171 u8 outer_smac_15_0[0x10]; 6172 u8 outer_dmac_15_0[0x10]; 6173 }; 6174 6175 struct mlx5_ifc_match_definer_format_23_bits { 6176 u8 reserved_at_0[0x100]; 6177 6178 u8 inner_ip_src_addr[0x20]; 6179 6180 u8 inner_ip_dest_addr[0x20]; 6181 6182 u8 inner_l4_sport[0x10]; 6183 u8 inner_l4_dport[0x10]; 6184 6185 u8 reserved_at_160[0x1]; 6186 u8 sx_sniffer[0x1]; 6187 u8 functional_lb[0x1]; 6188 u8 inner_ip_frag[0x1]; 6189 u8 inner_qp_type[0x2]; 6190 u8 inner_encap_type[0x2]; 6191 u8 port_number[0x2]; 6192 u8 inner_l3_type[0x2]; 6193 u8 inner_l4_type[0x2]; 6194 u8 inner_first_vlan_type[0x2]; 6195 u8 inner_first_vlan_prio[0x3]; 6196 u8 inner_first_vlan_cfi[0x1]; 6197 u8 inner_first_vlan_vid[0xc]; 6198 6199 u8 tunnel_header_0[0x20]; 6200 6201 u8 inner_dmac_47_16[0x20]; 6202 6203 u8 inner_smac_47_16[0x20]; 6204 6205 u8 inner_smac_15_0[0x10]; 6206 u8 inner_dmac_15_0[0x10]; 6207 }; 6208 6209 struct mlx5_ifc_match_definer_format_29_bits { 6210 u8 reserved_at_0[0xc0]; 6211 6212 u8 outer_ip_dest_addr[0x80]; 6213 6214 u8 outer_ip_src_addr[0x80]; 6215 6216 u8 outer_l4_sport[0x10]; 6217 u8 outer_l4_dport[0x10]; 6218 6219 u8 reserved_at_1e0[0x20]; 6220 }; 6221 6222 struct mlx5_ifc_match_definer_format_30_bits { 6223 u8 reserved_at_0[0xa0]; 6224 6225 u8 outer_ip_dest_addr[0x80]; 6226 6227 u8 outer_ip_src_addr[0x80]; 6228 6229 u8 outer_dmac_47_16[0x20]; 6230 6231 u8 outer_smac_47_16[0x20]; 6232 6233 u8 outer_smac_15_0[0x10]; 6234 u8 outer_dmac_15_0[0x10]; 6235 }; 6236 6237 struct mlx5_ifc_match_definer_format_31_bits { 6238 u8 reserved_at_0[0xc0]; 6239 6240 u8 inner_ip_dest_addr[0x80]; 6241 6242 u8 inner_ip_src_addr[0x80]; 6243 6244 u8 inner_l4_sport[0x10]; 6245 u8 inner_l4_dport[0x10]; 6246 6247 u8 reserved_at_1e0[0x20]; 6248 }; 6249 6250 struct mlx5_ifc_match_definer_format_32_bits { 6251 u8 reserved_at_0[0xa0]; 6252 6253 u8 inner_ip_dest_addr[0x80]; 6254 6255 u8 inner_ip_src_addr[0x80]; 6256 6257 u8 inner_dmac_47_16[0x20]; 6258 6259 u8 inner_smac_47_16[0x20]; 6260 6261 u8 inner_smac_15_0[0x10]; 6262 u8 inner_dmac_15_0[0x10]; 6263 }; 6264 6265 enum { 6266 MLX5_IFC_DEFINER_FORMAT_ID_SELECT = 61, 6267 }; 6268 6269 #define MLX5_IFC_DEFINER_FORMAT_OFFSET_UNUSED 0x0 6270 #define MLX5_IFC_DEFINER_FORMAT_OFFSET_OUTER_ETH_PKT_LEN 0x48 6271 #define MLX5_IFC_DEFINER_DW_SELECTORS_NUM 9 6272 #define MLX5_IFC_DEFINER_BYTE_SELECTORS_NUM 8 6273 6274 struct mlx5_ifc_match_definer_match_mask_bits { 6275 u8 reserved_at_1c0[5][0x20]; 6276 u8 match_dw_8[0x20]; 6277 u8 match_dw_7[0x20]; 6278 u8 match_dw_6[0x20]; 6279 u8 match_dw_5[0x20]; 6280 u8 match_dw_4[0x20]; 6281 u8 match_dw_3[0x20]; 6282 u8 match_dw_2[0x20]; 6283 u8 match_dw_1[0x20]; 6284 u8 match_dw_0[0x20]; 6285 6286 u8 match_byte_7[0x8]; 6287 u8 match_byte_6[0x8]; 6288 u8 match_byte_5[0x8]; 6289 u8 match_byte_4[0x8]; 6290 6291 u8 match_byte_3[0x8]; 6292 u8 match_byte_2[0x8]; 6293 u8 match_byte_1[0x8]; 6294 u8 match_byte_0[0x8]; 6295 }; 6296 6297 struct mlx5_ifc_match_definer_bits { 6298 u8 modify_field_select[0x40]; 6299 6300 u8 reserved_at_40[0x40]; 6301 6302 u8 reserved_at_80[0x10]; 6303 u8 format_id[0x10]; 6304 6305 u8 reserved_at_a0[0x60]; 6306 6307 u8 format_select_dw3[0x8]; 6308 u8 format_select_dw2[0x8]; 6309 u8 format_select_dw1[0x8]; 6310 u8 format_select_dw0[0x8]; 6311 6312 u8 format_select_dw7[0x8]; 6313 u8 format_select_dw6[0x8]; 6314 u8 format_select_dw5[0x8]; 6315 u8 format_select_dw4[0x8]; 6316 6317 u8 reserved_at_100[0x18]; 6318 u8 format_select_dw8[0x8]; 6319 6320 u8 reserved_at_120[0x20]; 6321 6322 u8 format_select_byte3[0x8]; 6323 u8 format_select_byte2[0x8]; 6324 u8 format_select_byte1[0x8]; 6325 u8 format_select_byte0[0x8]; 6326 6327 u8 format_select_byte7[0x8]; 6328 u8 format_select_byte6[0x8]; 6329 u8 format_select_byte5[0x8]; 6330 u8 format_select_byte4[0x8]; 6331 6332 u8 reserved_at_180[0x40]; 6333 6334 union { 6335 struct { 6336 u8 match_mask[16][0x20]; 6337 }; 6338 struct mlx5_ifc_match_definer_match_mask_bits match_mask_format; 6339 }; 6340 }; 6341 6342 struct mlx5_ifc_general_obj_create_param_bits { 6343 u8 alias_object[0x1]; 6344 u8 reserved_at_1[0x2]; 6345 u8 log_obj_range[0x5]; 6346 u8 reserved_at_8[0x18]; 6347 }; 6348 6349 struct mlx5_ifc_general_obj_query_param_bits { 6350 u8 alias_object[0x1]; 6351 u8 obj_offset[0x1f]; 6352 }; 6353 6354 struct mlx5_ifc_general_obj_in_cmd_hdr_bits { 6355 u8 opcode[0x10]; 6356 u8 uid[0x10]; 6357 6358 u8 vhca_tunnel_id[0x10]; 6359 u8 obj_type[0x10]; 6360 6361 u8 obj_id[0x20]; 6362 6363 union { 6364 struct mlx5_ifc_general_obj_create_param_bits create; 6365 struct mlx5_ifc_general_obj_query_param_bits query; 6366 } op_param; 6367 }; 6368 6369 struct mlx5_ifc_general_obj_out_cmd_hdr_bits { 6370 u8 status[0x8]; 6371 u8 reserved_at_8[0x18]; 6372 6373 u8 syndrome[0x20]; 6374 6375 u8 obj_id[0x20]; 6376 6377 u8 reserved_at_60[0x20]; 6378 }; 6379 6380 struct mlx5_ifc_modify_header_arg_bits { 6381 u8 reserved_at_0[0x80]; 6382 6383 u8 reserved_at_80[0x8]; 6384 u8 access_pd[0x18]; 6385 }; 6386 6387 struct mlx5_ifc_create_modify_header_arg_in_bits { 6388 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 6389 struct mlx5_ifc_modify_header_arg_bits arg; 6390 }; 6391 6392 struct mlx5_ifc_create_match_definer_in_bits { 6393 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 6394 6395 struct mlx5_ifc_match_definer_bits obj_context; 6396 }; 6397 6398 struct mlx5_ifc_create_match_definer_out_bits { 6399 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 6400 }; 6401 6402 enum { 6403 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 6404 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 6405 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 6406 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3, 6407 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_3 = 0x4, 6408 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_4 = 0x5, 6409 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_5 = 0x6, 6410 }; 6411 6412 struct mlx5_ifc_query_flow_group_out_bits { 6413 u8 status[0x8]; 6414 u8 reserved_at_8[0x18]; 6415 6416 u8 syndrome[0x20]; 6417 6418 u8 reserved_at_40[0xa0]; 6419 6420 u8 start_flow_index[0x20]; 6421 6422 u8 reserved_at_100[0x20]; 6423 6424 u8 end_flow_index[0x20]; 6425 6426 u8 reserved_at_140[0xa0]; 6427 6428 u8 reserved_at_1e0[0x18]; 6429 u8 match_criteria_enable[0x8]; 6430 6431 struct mlx5_ifc_fte_match_param_bits match_criteria; 6432 6433 u8 reserved_at_1200[0xe00]; 6434 }; 6435 6436 struct mlx5_ifc_query_flow_group_in_bits { 6437 u8 opcode[0x10]; 6438 u8 reserved_at_10[0x10]; 6439 6440 u8 reserved_at_20[0x10]; 6441 u8 op_mod[0x10]; 6442 6443 u8 reserved_at_40[0x40]; 6444 6445 u8 table_type[0x8]; 6446 u8 reserved_at_88[0x18]; 6447 6448 u8 reserved_at_a0[0x8]; 6449 u8 table_id[0x18]; 6450 6451 u8 group_id[0x20]; 6452 6453 u8 reserved_at_e0[0x120]; 6454 }; 6455 6456 struct mlx5_ifc_query_flow_counter_out_bits { 6457 u8 status[0x8]; 6458 u8 reserved_at_8[0x18]; 6459 6460 u8 syndrome[0x20]; 6461 6462 u8 reserved_at_40[0x40]; 6463 6464 struct mlx5_ifc_traffic_counter_bits flow_statistics[]; 6465 }; 6466 6467 struct mlx5_ifc_query_flow_counter_in_bits { 6468 u8 opcode[0x10]; 6469 u8 reserved_at_10[0x10]; 6470 6471 u8 reserved_at_20[0x10]; 6472 u8 op_mod[0x10]; 6473 6474 u8 reserved_at_40[0x80]; 6475 6476 u8 clear[0x1]; 6477 u8 reserved_at_c1[0xf]; 6478 u8 num_of_counters[0x10]; 6479 6480 u8 flow_counter_id[0x20]; 6481 }; 6482 6483 struct mlx5_ifc_query_esw_vport_context_out_bits { 6484 u8 status[0x8]; 6485 u8 reserved_at_8[0x18]; 6486 6487 u8 syndrome[0x20]; 6488 6489 u8 reserved_at_40[0x40]; 6490 6491 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 6492 }; 6493 6494 struct mlx5_ifc_query_esw_vport_context_in_bits { 6495 u8 opcode[0x10]; 6496 u8 reserved_at_10[0x10]; 6497 6498 u8 reserved_at_20[0x10]; 6499 u8 op_mod[0x10]; 6500 6501 u8 other_vport[0x1]; 6502 u8 reserved_at_41[0xf]; 6503 u8 vport_number[0x10]; 6504 6505 u8 reserved_at_60[0x20]; 6506 }; 6507 6508 struct mlx5_ifc_modify_esw_vport_context_out_bits { 6509 u8 status[0x8]; 6510 u8 reserved_at_8[0x18]; 6511 6512 u8 syndrome[0x20]; 6513 6514 u8 reserved_at_40[0x40]; 6515 }; 6516 6517 struct mlx5_ifc_esw_vport_context_fields_select_bits { 6518 u8 reserved_at_0[0x1b]; 6519 u8 fdb_to_vport_reg_c_id[0x1]; 6520 u8 vport_cvlan_insert[0x1]; 6521 u8 vport_svlan_insert[0x1]; 6522 u8 vport_cvlan_strip[0x1]; 6523 u8 vport_svlan_strip[0x1]; 6524 }; 6525 6526 struct mlx5_ifc_modify_esw_vport_context_in_bits { 6527 u8 opcode[0x10]; 6528 u8 reserved_at_10[0x10]; 6529 6530 u8 reserved_at_20[0x10]; 6531 u8 op_mod[0x10]; 6532 6533 u8 other_vport[0x1]; 6534 u8 reserved_at_41[0xf]; 6535 u8 vport_number[0x10]; 6536 6537 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select; 6538 6539 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 6540 }; 6541 6542 struct mlx5_ifc_query_eq_out_bits { 6543 u8 status[0x8]; 6544 u8 reserved_at_8[0x18]; 6545 6546 u8 syndrome[0x20]; 6547 6548 u8 reserved_at_40[0x40]; 6549 6550 struct mlx5_ifc_eqc_bits eq_context_entry; 6551 6552 u8 reserved_at_280[0x40]; 6553 6554 u8 event_bitmask[0x40]; 6555 6556 u8 reserved_at_300[0x580]; 6557 6558 u8 pas[][0x40]; 6559 }; 6560 6561 struct mlx5_ifc_query_eq_in_bits { 6562 u8 opcode[0x10]; 6563 u8 reserved_at_10[0x10]; 6564 6565 u8 reserved_at_20[0x10]; 6566 u8 op_mod[0x10]; 6567 6568 u8 reserved_at_40[0x18]; 6569 u8 eq_number[0x8]; 6570 6571 u8 reserved_at_60[0x20]; 6572 }; 6573 6574 struct mlx5_ifc_packet_reformat_context_in_bits { 6575 u8 reformat_type[0x8]; 6576 u8 reserved_at_8[0x4]; 6577 u8 reformat_param_0[0x4]; 6578 u8 reserved_at_10[0x6]; 6579 u8 reformat_data_size[0xa]; 6580 6581 u8 reformat_param_1[0x8]; 6582 u8 reserved_at_28[0x8]; 6583 u8 reformat_data[2][0x8]; 6584 6585 u8 more_reformat_data[][0x8]; 6586 }; 6587 6588 struct mlx5_ifc_query_packet_reformat_context_out_bits { 6589 u8 status[0x8]; 6590 u8 reserved_at_8[0x18]; 6591 6592 u8 syndrome[0x20]; 6593 6594 u8 reserved_at_40[0xa0]; 6595 6596 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context[]; 6597 }; 6598 6599 struct mlx5_ifc_query_packet_reformat_context_in_bits { 6600 u8 opcode[0x10]; 6601 u8 reserved_at_10[0x10]; 6602 6603 u8 reserved_at_20[0x10]; 6604 u8 op_mod[0x10]; 6605 6606 u8 packet_reformat_id[0x20]; 6607 6608 u8 reserved_at_60[0xa0]; 6609 }; 6610 6611 struct mlx5_ifc_alloc_packet_reformat_context_out_bits { 6612 u8 status[0x8]; 6613 u8 reserved_at_8[0x18]; 6614 6615 u8 syndrome[0x20]; 6616 6617 u8 packet_reformat_id[0x20]; 6618 6619 u8 reserved_at_60[0x20]; 6620 }; 6621 6622 enum { 6623 MLX5_REFORMAT_CONTEXT_ANCHOR_MAC_START = 0x1, 6624 MLX5_REFORMAT_CONTEXT_ANCHOR_IP_START = 0x7, 6625 MLX5_REFORMAT_CONTEXT_ANCHOR_TCP_UDP_START = 0x9, 6626 }; 6627 6628 enum mlx5_reformat_ctx_type { 6629 MLX5_REFORMAT_TYPE_L2_TO_VXLAN = 0x0, 6630 MLX5_REFORMAT_TYPE_L2_TO_NVGRE = 0x1, 6631 MLX5_REFORMAT_TYPE_L2_TO_L2_TUNNEL = 0x2, 6632 MLX5_REFORMAT_TYPE_L3_TUNNEL_TO_L2 = 0x3, 6633 MLX5_REFORMAT_TYPE_L2_TO_L3_TUNNEL = 0x4, 6634 MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_IPV4 = 0x5, 6635 MLX5_REFORMAT_TYPE_L2_TO_L3_ESP_TUNNEL = 0x6, 6636 MLX5_REFORMAT_TYPE_DEL_ESP_TRANSPORT = 0x8, 6637 MLX5_REFORMAT_TYPE_L3_ESP_TUNNEL_TO_L2 = 0x9, 6638 MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_IPV6 = 0xb, 6639 MLX5_REFORMAT_TYPE_INSERT_HDR = 0xf, 6640 MLX5_REFORMAT_TYPE_REMOVE_HDR = 0x10, 6641 MLX5_REFORMAT_TYPE_ADD_MACSEC = 0x11, 6642 MLX5_REFORMAT_TYPE_DEL_MACSEC = 0x12, 6643 }; 6644 6645 struct mlx5_ifc_alloc_packet_reformat_context_in_bits { 6646 u8 opcode[0x10]; 6647 u8 reserved_at_10[0x10]; 6648 6649 u8 reserved_at_20[0x10]; 6650 u8 op_mod[0x10]; 6651 6652 u8 reserved_at_40[0xa0]; 6653 6654 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context; 6655 }; 6656 6657 struct mlx5_ifc_dealloc_packet_reformat_context_out_bits { 6658 u8 status[0x8]; 6659 u8 reserved_at_8[0x18]; 6660 6661 u8 syndrome[0x20]; 6662 6663 u8 reserved_at_40[0x40]; 6664 }; 6665 6666 struct mlx5_ifc_dealloc_packet_reformat_context_in_bits { 6667 u8 opcode[0x10]; 6668 u8 reserved_at_10[0x10]; 6669 6670 u8 reserved_20[0x10]; 6671 u8 op_mod[0x10]; 6672 6673 u8 packet_reformat_id[0x20]; 6674 6675 u8 reserved_60[0x20]; 6676 }; 6677 6678 struct mlx5_ifc_set_action_in_bits { 6679 u8 action_type[0x4]; 6680 u8 field[0xc]; 6681 u8 reserved_at_10[0x3]; 6682 u8 offset[0x5]; 6683 u8 reserved_at_18[0x3]; 6684 u8 length[0x5]; 6685 6686 u8 data[0x20]; 6687 }; 6688 6689 struct mlx5_ifc_add_action_in_bits { 6690 u8 action_type[0x4]; 6691 u8 field[0xc]; 6692 u8 reserved_at_10[0x10]; 6693 6694 u8 data[0x20]; 6695 }; 6696 6697 struct mlx5_ifc_copy_action_in_bits { 6698 u8 action_type[0x4]; 6699 u8 src_field[0xc]; 6700 u8 reserved_at_10[0x3]; 6701 u8 src_offset[0x5]; 6702 u8 reserved_at_18[0x3]; 6703 u8 length[0x5]; 6704 6705 u8 reserved_at_20[0x4]; 6706 u8 dst_field[0xc]; 6707 u8 reserved_at_30[0x3]; 6708 u8 dst_offset[0x5]; 6709 u8 reserved_at_38[0x8]; 6710 }; 6711 6712 union mlx5_ifc_set_add_copy_action_in_auto_bits { 6713 struct mlx5_ifc_set_action_in_bits set_action_in; 6714 struct mlx5_ifc_add_action_in_bits add_action_in; 6715 struct mlx5_ifc_copy_action_in_bits copy_action_in; 6716 u8 reserved_at_0[0x40]; 6717 }; 6718 6719 enum { 6720 MLX5_ACTION_TYPE_SET = 0x1, 6721 MLX5_ACTION_TYPE_ADD = 0x2, 6722 MLX5_ACTION_TYPE_COPY = 0x3, 6723 }; 6724 6725 enum { 6726 MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16 = 0x1, 6727 MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0 = 0x2, 6728 MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE = 0x3, 6729 MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16 = 0x4, 6730 MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0 = 0x5, 6731 MLX5_ACTION_IN_FIELD_OUT_IP_DSCP = 0x6, 6732 MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS = 0x7, 6733 MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT = 0x8, 6734 MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT = 0x9, 6735 MLX5_ACTION_IN_FIELD_OUT_IP_TTL = 0xa, 6736 MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT = 0xb, 6737 MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT = 0xc, 6738 MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96 = 0xd, 6739 MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64 = 0xe, 6740 MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32 = 0xf, 6741 MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0 = 0x10, 6742 MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96 = 0x11, 6743 MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64 = 0x12, 6744 MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32 = 0x13, 6745 MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0 = 0x14, 6746 MLX5_ACTION_IN_FIELD_OUT_SIPV4 = 0x15, 6747 MLX5_ACTION_IN_FIELD_OUT_DIPV4 = 0x16, 6748 MLX5_ACTION_IN_FIELD_OUT_FIRST_VID = 0x17, 6749 MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47, 6750 MLX5_ACTION_IN_FIELD_METADATA_REG_A = 0x49, 6751 MLX5_ACTION_IN_FIELD_METADATA_REG_B = 0x50, 6752 MLX5_ACTION_IN_FIELD_METADATA_REG_C_0 = 0x51, 6753 MLX5_ACTION_IN_FIELD_METADATA_REG_C_1 = 0x52, 6754 MLX5_ACTION_IN_FIELD_METADATA_REG_C_2 = 0x53, 6755 MLX5_ACTION_IN_FIELD_METADATA_REG_C_3 = 0x54, 6756 MLX5_ACTION_IN_FIELD_METADATA_REG_C_4 = 0x55, 6757 MLX5_ACTION_IN_FIELD_METADATA_REG_C_5 = 0x56, 6758 MLX5_ACTION_IN_FIELD_METADATA_REG_C_6 = 0x57, 6759 MLX5_ACTION_IN_FIELD_METADATA_REG_C_7 = 0x58, 6760 MLX5_ACTION_IN_FIELD_OUT_TCP_SEQ_NUM = 0x59, 6761 MLX5_ACTION_IN_FIELD_OUT_TCP_ACK_NUM = 0x5B, 6762 MLX5_ACTION_IN_FIELD_IPSEC_SYNDROME = 0x5D, 6763 MLX5_ACTION_IN_FIELD_OUT_EMD_47_32 = 0x6F, 6764 MLX5_ACTION_IN_FIELD_OUT_EMD_31_0 = 0x70, 6765 }; 6766 6767 struct mlx5_ifc_alloc_modify_header_context_out_bits { 6768 u8 status[0x8]; 6769 u8 reserved_at_8[0x18]; 6770 6771 u8 syndrome[0x20]; 6772 6773 u8 modify_header_id[0x20]; 6774 6775 u8 reserved_at_60[0x20]; 6776 }; 6777 6778 struct mlx5_ifc_alloc_modify_header_context_in_bits { 6779 u8 opcode[0x10]; 6780 u8 reserved_at_10[0x10]; 6781 6782 u8 reserved_at_20[0x10]; 6783 u8 op_mod[0x10]; 6784 6785 u8 reserved_at_40[0x20]; 6786 6787 u8 table_type[0x8]; 6788 u8 reserved_at_68[0x10]; 6789 u8 num_of_actions[0x8]; 6790 6791 union mlx5_ifc_set_add_copy_action_in_auto_bits actions[]; 6792 }; 6793 6794 struct mlx5_ifc_dealloc_modify_header_context_out_bits { 6795 u8 status[0x8]; 6796 u8 reserved_at_8[0x18]; 6797 6798 u8 syndrome[0x20]; 6799 6800 u8 reserved_at_40[0x40]; 6801 }; 6802 6803 struct mlx5_ifc_dealloc_modify_header_context_in_bits { 6804 u8 opcode[0x10]; 6805 u8 reserved_at_10[0x10]; 6806 6807 u8 reserved_at_20[0x10]; 6808 u8 op_mod[0x10]; 6809 6810 u8 modify_header_id[0x20]; 6811 6812 u8 reserved_at_60[0x20]; 6813 }; 6814 6815 struct mlx5_ifc_query_modify_header_context_in_bits { 6816 u8 opcode[0x10]; 6817 u8 uid[0x10]; 6818 6819 u8 reserved_at_20[0x10]; 6820 u8 op_mod[0x10]; 6821 6822 u8 modify_header_id[0x20]; 6823 6824 u8 reserved_at_60[0xa0]; 6825 }; 6826 6827 struct mlx5_ifc_query_dct_out_bits { 6828 u8 status[0x8]; 6829 u8 reserved_at_8[0x18]; 6830 6831 u8 syndrome[0x20]; 6832 6833 u8 reserved_at_40[0x40]; 6834 6835 struct mlx5_ifc_dctc_bits dct_context_entry; 6836 6837 u8 reserved_at_280[0x180]; 6838 }; 6839 6840 struct mlx5_ifc_query_dct_in_bits { 6841 u8 opcode[0x10]; 6842 u8 reserved_at_10[0x10]; 6843 6844 u8 reserved_at_20[0x10]; 6845 u8 op_mod[0x10]; 6846 6847 u8 reserved_at_40[0x8]; 6848 u8 dctn[0x18]; 6849 6850 u8 reserved_at_60[0x20]; 6851 }; 6852 6853 struct mlx5_ifc_query_cq_out_bits { 6854 u8 status[0x8]; 6855 u8 reserved_at_8[0x18]; 6856 6857 u8 syndrome[0x20]; 6858 6859 u8 reserved_at_40[0x40]; 6860 6861 struct mlx5_ifc_cqc_bits cq_context; 6862 6863 u8 reserved_at_280[0x600]; 6864 6865 u8 pas[][0x40]; 6866 }; 6867 6868 struct mlx5_ifc_query_cq_in_bits { 6869 u8 opcode[0x10]; 6870 u8 reserved_at_10[0x10]; 6871 6872 u8 reserved_at_20[0x10]; 6873 u8 op_mod[0x10]; 6874 6875 u8 reserved_at_40[0x8]; 6876 u8 cqn[0x18]; 6877 6878 u8 reserved_at_60[0x20]; 6879 }; 6880 6881 struct mlx5_ifc_query_cong_status_out_bits { 6882 u8 status[0x8]; 6883 u8 reserved_at_8[0x18]; 6884 6885 u8 syndrome[0x20]; 6886 6887 u8 reserved_at_40[0x20]; 6888 6889 u8 enable[0x1]; 6890 u8 tag_enable[0x1]; 6891 u8 reserved_at_62[0x1e]; 6892 }; 6893 6894 struct mlx5_ifc_query_cong_status_in_bits { 6895 u8 opcode[0x10]; 6896 u8 reserved_at_10[0x10]; 6897 6898 u8 reserved_at_20[0x10]; 6899 u8 op_mod[0x10]; 6900 6901 u8 reserved_at_40[0x18]; 6902 u8 priority[0x4]; 6903 u8 cong_protocol[0x4]; 6904 6905 u8 reserved_at_60[0x20]; 6906 }; 6907 6908 struct mlx5_ifc_query_cong_statistics_out_bits { 6909 u8 status[0x8]; 6910 u8 reserved_at_8[0x18]; 6911 6912 u8 syndrome[0x20]; 6913 6914 u8 reserved_at_40[0x40]; 6915 6916 u8 rp_cur_flows[0x20]; 6917 6918 u8 sum_flows[0x20]; 6919 6920 u8 rp_cnp_ignored_high[0x20]; 6921 6922 u8 rp_cnp_ignored_low[0x20]; 6923 6924 u8 rp_cnp_handled_high[0x20]; 6925 6926 u8 rp_cnp_handled_low[0x20]; 6927 6928 u8 reserved_at_140[0x100]; 6929 6930 u8 time_stamp_high[0x20]; 6931 6932 u8 time_stamp_low[0x20]; 6933 6934 u8 accumulators_period[0x20]; 6935 6936 u8 np_ecn_marked_roce_packets_high[0x20]; 6937 6938 u8 np_ecn_marked_roce_packets_low[0x20]; 6939 6940 u8 np_cnp_sent_high[0x20]; 6941 6942 u8 np_cnp_sent_low[0x20]; 6943 6944 u8 reserved_at_320[0x560]; 6945 }; 6946 6947 struct mlx5_ifc_query_cong_statistics_in_bits { 6948 u8 opcode[0x10]; 6949 u8 reserved_at_10[0x10]; 6950 6951 u8 reserved_at_20[0x10]; 6952 u8 op_mod[0x10]; 6953 6954 u8 clear[0x1]; 6955 u8 reserved_at_41[0x1f]; 6956 6957 u8 reserved_at_60[0x20]; 6958 }; 6959 6960 struct mlx5_ifc_query_cong_params_out_bits { 6961 u8 status[0x8]; 6962 u8 reserved_at_8[0x18]; 6963 6964 u8 syndrome[0x20]; 6965 6966 u8 reserved_at_40[0x40]; 6967 6968 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 6969 }; 6970 6971 struct mlx5_ifc_query_cong_params_in_bits { 6972 u8 opcode[0x10]; 6973 u8 reserved_at_10[0x10]; 6974 6975 u8 reserved_at_20[0x10]; 6976 u8 op_mod[0x10]; 6977 6978 u8 reserved_at_40[0x1c]; 6979 u8 cong_protocol[0x4]; 6980 6981 u8 reserved_at_60[0x20]; 6982 }; 6983 6984 struct mlx5_ifc_query_adapter_out_bits { 6985 u8 status[0x8]; 6986 u8 reserved_at_8[0x18]; 6987 6988 u8 syndrome[0x20]; 6989 6990 u8 reserved_at_40[0x40]; 6991 6992 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct; 6993 }; 6994 6995 struct mlx5_ifc_query_adapter_in_bits { 6996 u8 opcode[0x10]; 6997 u8 reserved_at_10[0x10]; 6998 6999 u8 reserved_at_20[0x10]; 7000 u8 op_mod[0x10]; 7001 7002 u8 reserved_at_40[0x40]; 7003 }; 7004 7005 struct mlx5_ifc_qp_2rst_out_bits { 7006 u8 status[0x8]; 7007 u8 reserved_at_8[0x18]; 7008 7009 u8 syndrome[0x20]; 7010 7011 u8 reserved_at_40[0x40]; 7012 }; 7013 7014 struct mlx5_ifc_qp_2rst_in_bits { 7015 u8 opcode[0x10]; 7016 u8 uid[0x10]; 7017 7018 u8 reserved_at_20[0x10]; 7019 u8 op_mod[0x10]; 7020 7021 u8 reserved_at_40[0x8]; 7022 u8 qpn[0x18]; 7023 7024 u8 reserved_at_60[0x20]; 7025 }; 7026 7027 struct mlx5_ifc_qp_2err_out_bits { 7028 u8 status[0x8]; 7029 u8 reserved_at_8[0x18]; 7030 7031 u8 syndrome[0x20]; 7032 7033 u8 reserved_at_40[0x40]; 7034 }; 7035 7036 struct mlx5_ifc_qp_2err_in_bits { 7037 u8 opcode[0x10]; 7038 u8 uid[0x10]; 7039 7040 u8 reserved_at_20[0x10]; 7041 u8 op_mod[0x10]; 7042 7043 u8 reserved_at_40[0x8]; 7044 u8 qpn[0x18]; 7045 7046 u8 reserved_at_60[0x20]; 7047 }; 7048 7049 struct mlx5_ifc_page_fault_resume_out_bits { 7050 u8 status[0x8]; 7051 u8 reserved_at_8[0x18]; 7052 7053 u8 syndrome[0x20]; 7054 7055 u8 reserved_at_40[0x40]; 7056 }; 7057 7058 struct mlx5_ifc_page_fault_resume_in_bits { 7059 u8 opcode[0x10]; 7060 u8 reserved_at_10[0x10]; 7061 7062 u8 reserved_at_20[0x10]; 7063 u8 op_mod[0x10]; 7064 7065 u8 error[0x1]; 7066 u8 reserved_at_41[0x4]; 7067 u8 page_fault_type[0x3]; 7068 u8 wq_number[0x18]; 7069 7070 u8 reserved_at_60[0x8]; 7071 u8 token[0x18]; 7072 }; 7073 7074 struct mlx5_ifc_nop_out_bits { 7075 u8 status[0x8]; 7076 u8 reserved_at_8[0x18]; 7077 7078 u8 syndrome[0x20]; 7079 7080 u8 reserved_at_40[0x40]; 7081 }; 7082 7083 struct mlx5_ifc_nop_in_bits { 7084 u8 opcode[0x10]; 7085 u8 reserved_at_10[0x10]; 7086 7087 u8 reserved_at_20[0x10]; 7088 u8 op_mod[0x10]; 7089 7090 u8 reserved_at_40[0x40]; 7091 }; 7092 7093 struct mlx5_ifc_modify_vport_state_out_bits { 7094 u8 status[0x8]; 7095 u8 reserved_at_8[0x18]; 7096 7097 u8 syndrome[0x20]; 7098 7099 u8 reserved_at_40[0x40]; 7100 }; 7101 7102 struct mlx5_ifc_modify_vport_state_in_bits { 7103 u8 opcode[0x10]; 7104 u8 reserved_at_10[0x10]; 7105 7106 u8 reserved_at_20[0x10]; 7107 u8 op_mod[0x10]; 7108 7109 u8 other_vport[0x1]; 7110 u8 reserved_at_41[0xf]; 7111 u8 vport_number[0x10]; 7112 7113 u8 reserved_at_60[0x18]; 7114 u8 admin_state[0x4]; 7115 u8 reserved_at_7c[0x4]; 7116 }; 7117 7118 struct mlx5_ifc_modify_tis_out_bits { 7119 u8 status[0x8]; 7120 u8 reserved_at_8[0x18]; 7121 7122 u8 syndrome[0x20]; 7123 7124 u8 reserved_at_40[0x40]; 7125 }; 7126 7127 struct mlx5_ifc_modify_tis_bitmask_bits { 7128 u8 reserved_at_0[0x20]; 7129 7130 u8 reserved_at_20[0x1d]; 7131 u8 lag_tx_port_affinity[0x1]; 7132 u8 strict_lag_tx_port_affinity[0x1]; 7133 u8 prio[0x1]; 7134 }; 7135 7136 struct mlx5_ifc_modify_tis_in_bits { 7137 u8 opcode[0x10]; 7138 u8 uid[0x10]; 7139 7140 u8 reserved_at_20[0x10]; 7141 u8 op_mod[0x10]; 7142 7143 u8 reserved_at_40[0x8]; 7144 u8 tisn[0x18]; 7145 7146 u8 reserved_at_60[0x20]; 7147 7148 struct mlx5_ifc_modify_tis_bitmask_bits bitmask; 7149 7150 u8 reserved_at_c0[0x40]; 7151 7152 struct mlx5_ifc_tisc_bits ctx; 7153 }; 7154 7155 struct mlx5_ifc_modify_tir_bitmask_bits { 7156 u8 reserved_at_0[0x20]; 7157 7158 u8 reserved_at_20[0x1b]; 7159 u8 self_lb_en[0x1]; 7160 u8 reserved_at_3c[0x1]; 7161 u8 hash[0x1]; 7162 u8 reserved_at_3e[0x1]; 7163 u8 packet_merge[0x1]; 7164 }; 7165 7166 struct mlx5_ifc_modify_tir_out_bits { 7167 u8 status[0x8]; 7168 u8 reserved_at_8[0x18]; 7169 7170 u8 syndrome[0x20]; 7171 7172 u8 reserved_at_40[0x40]; 7173 }; 7174 7175 struct mlx5_ifc_modify_tir_in_bits { 7176 u8 opcode[0x10]; 7177 u8 uid[0x10]; 7178 7179 u8 reserved_at_20[0x10]; 7180 u8 op_mod[0x10]; 7181 7182 u8 reserved_at_40[0x8]; 7183 u8 tirn[0x18]; 7184 7185 u8 reserved_at_60[0x20]; 7186 7187 struct mlx5_ifc_modify_tir_bitmask_bits bitmask; 7188 7189 u8 reserved_at_c0[0x40]; 7190 7191 struct mlx5_ifc_tirc_bits ctx; 7192 }; 7193 7194 struct mlx5_ifc_modify_sq_out_bits { 7195 u8 status[0x8]; 7196 u8 reserved_at_8[0x18]; 7197 7198 u8 syndrome[0x20]; 7199 7200 u8 reserved_at_40[0x40]; 7201 }; 7202 7203 struct mlx5_ifc_modify_sq_in_bits { 7204 u8 opcode[0x10]; 7205 u8 uid[0x10]; 7206 7207 u8 reserved_at_20[0x10]; 7208 u8 op_mod[0x10]; 7209 7210 u8 sq_state[0x4]; 7211 u8 reserved_at_44[0x4]; 7212 u8 sqn[0x18]; 7213 7214 u8 reserved_at_60[0x20]; 7215 7216 u8 modify_bitmask[0x40]; 7217 7218 u8 reserved_at_c0[0x40]; 7219 7220 struct mlx5_ifc_sqc_bits ctx; 7221 }; 7222 7223 struct mlx5_ifc_modify_scheduling_element_out_bits { 7224 u8 status[0x8]; 7225 u8 reserved_at_8[0x18]; 7226 7227 u8 syndrome[0x20]; 7228 7229 u8 reserved_at_40[0x1c0]; 7230 }; 7231 7232 enum { 7233 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1, 7234 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2, 7235 }; 7236 7237 struct mlx5_ifc_modify_scheduling_element_in_bits { 7238 u8 opcode[0x10]; 7239 u8 reserved_at_10[0x10]; 7240 7241 u8 reserved_at_20[0x10]; 7242 u8 op_mod[0x10]; 7243 7244 u8 scheduling_hierarchy[0x8]; 7245 u8 reserved_at_48[0x18]; 7246 7247 u8 scheduling_element_id[0x20]; 7248 7249 u8 reserved_at_80[0x20]; 7250 7251 u8 modify_bitmask[0x20]; 7252 7253 u8 reserved_at_c0[0x40]; 7254 7255 struct mlx5_ifc_scheduling_context_bits scheduling_context; 7256 7257 u8 reserved_at_300[0x100]; 7258 }; 7259 7260 struct mlx5_ifc_modify_rqt_out_bits { 7261 u8 status[0x8]; 7262 u8 reserved_at_8[0x18]; 7263 7264 u8 syndrome[0x20]; 7265 7266 u8 reserved_at_40[0x40]; 7267 }; 7268 7269 struct mlx5_ifc_rqt_bitmask_bits { 7270 u8 reserved_at_0[0x20]; 7271 7272 u8 reserved_at_20[0x1f]; 7273 u8 rqn_list[0x1]; 7274 }; 7275 7276 struct mlx5_ifc_modify_rqt_in_bits { 7277 u8 opcode[0x10]; 7278 u8 uid[0x10]; 7279 7280 u8 reserved_at_20[0x10]; 7281 u8 op_mod[0x10]; 7282 7283 u8 reserved_at_40[0x8]; 7284 u8 rqtn[0x18]; 7285 7286 u8 reserved_at_60[0x20]; 7287 7288 struct mlx5_ifc_rqt_bitmask_bits bitmask; 7289 7290 u8 reserved_at_c0[0x40]; 7291 7292 struct mlx5_ifc_rqtc_bits ctx; 7293 }; 7294 7295 struct mlx5_ifc_modify_rq_out_bits { 7296 u8 status[0x8]; 7297 u8 reserved_at_8[0x18]; 7298 7299 u8 syndrome[0x20]; 7300 7301 u8 reserved_at_40[0x40]; 7302 }; 7303 7304 enum { 7305 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1, 7306 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2, 7307 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3, 7308 }; 7309 7310 struct mlx5_ifc_modify_rq_in_bits { 7311 u8 opcode[0x10]; 7312 u8 uid[0x10]; 7313 7314 u8 reserved_at_20[0x10]; 7315 u8 op_mod[0x10]; 7316 7317 u8 rq_state[0x4]; 7318 u8 reserved_at_44[0x4]; 7319 u8 rqn[0x18]; 7320 7321 u8 reserved_at_60[0x20]; 7322 7323 u8 modify_bitmask[0x40]; 7324 7325 u8 reserved_at_c0[0x40]; 7326 7327 struct mlx5_ifc_rqc_bits ctx; 7328 }; 7329 7330 struct mlx5_ifc_modify_rmp_out_bits { 7331 u8 status[0x8]; 7332 u8 reserved_at_8[0x18]; 7333 7334 u8 syndrome[0x20]; 7335 7336 u8 reserved_at_40[0x40]; 7337 }; 7338 7339 struct mlx5_ifc_rmp_bitmask_bits { 7340 u8 reserved_at_0[0x20]; 7341 7342 u8 reserved_at_20[0x1f]; 7343 u8 lwm[0x1]; 7344 }; 7345 7346 struct mlx5_ifc_modify_rmp_in_bits { 7347 u8 opcode[0x10]; 7348 u8 uid[0x10]; 7349 7350 u8 reserved_at_20[0x10]; 7351 u8 op_mod[0x10]; 7352 7353 u8 rmp_state[0x4]; 7354 u8 reserved_at_44[0x4]; 7355 u8 rmpn[0x18]; 7356 7357 u8 reserved_at_60[0x20]; 7358 7359 struct mlx5_ifc_rmp_bitmask_bits bitmask; 7360 7361 u8 reserved_at_c0[0x40]; 7362 7363 struct mlx5_ifc_rmpc_bits ctx; 7364 }; 7365 7366 struct mlx5_ifc_modify_nic_vport_context_out_bits { 7367 u8 status[0x8]; 7368 u8 reserved_at_8[0x18]; 7369 7370 u8 syndrome[0x20]; 7371 7372 u8 reserved_at_40[0x40]; 7373 }; 7374 7375 struct mlx5_ifc_modify_nic_vport_field_select_bits { 7376 u8 reserved_at_0[0x12]; 7377 u8 affiliation[0x1]; 7378 u8 reserved_at_13[0x1]; 7379 u8 disable_uc_local_lb[0x1]; 7380 u8 disable_mc_local_lb[0x1]; 7381 u8 node_guid[0x1]; 7382 u8 port_guid[0x1]; 7383 u8 min_inline[0x1]; 7384 u8 mtu[0x1]; 7385 u8 change_event[0x1]; 7386 u8 promisc[0x1]; 7387 u8 permanent_address[0x1]; 7388 u8 addresses_list[0x1]; 7389 u8 roce_en[0x1]; 7390 u8 reserved_at_1f[0x1]; 7391 }; 7392 7393 struct mlx5_ifc_modify_nic_vport_context_in_bits { 7394 u8 opcode[0x10]; 7395 u8 reserved_at_10[0x10]; 7396 7397 u8 reserved_at_20[0x10]; 7398 u8 op_mod[0x10]; 7399 7400 u8 other_vport[0x1]; 7401 u8 reserved_at_41[0xf]; 7402 u8 vport_number[0x10]; 7403 7404 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select; 7405 7406 u8 reserved_at_80[0x780]; 7407 7408 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 7409 }; 7410 7411 struct mlx5_ifc_modify_hca_vport_context_out_bits { 7412 u8 status[0x8]; 7413 u8 reserved_at_8[0x18]; 7414 7415 u8 syndrome[0x20]; 7416 7417 u8 reserved_at_40[0x40]; 7418 }; 7419 7420 struct mlx5_ifc_modify_hca_vport_context_in_bits { 7421 u8 opcode[0x10]; 7422 u8 reserved_at_10[0x10]; 7423 7424 u8 reserved_at_20[0x10]; 7425 u8 op_mod[0x10]; 7426 7427 u8 other_vport[0x1]; 7428 u8 reserved_at_41[0xb]; 7429 u8 port_num[0x4]; 7430 u8 vport_number[0x10]; 7431 7432 u8 reserved_at_60[0x20]; 7433 7434 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 7435 }; 7436 7437 struct mlx5_ifc_modify_cq_out_bits { 7438 u8 status[0x8]; 7439 u8 reserved_at_8[0x18]; 7440 7441 u8 syndrome[0x20]; 7442 7443 u8 reserved_at_40[0x40]; 7444 }; 7445 7446 enum { 7447 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0, 7448 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1, 7449 }; 7450 7451 struct mlx5_ifc_modify_cq_in_bits { 7452 u8 opcode[0x10]; 7453 u8 uid[0x10]; 7454 7455 u8 reserved_at_20[0x10]; 7456 u8 op_mod[0x10]; 7457 7458 u8 reserved_at_40[0x8]; 7459 u8 cqn[0x18]; 7460 7461 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select; 7462 7463 struct mlx5_ifc_cqc_bits cq_context; 7464 7465 u8 reserved_at_280[0x60]; 7466 7467 u8 cq_umem_valid[0x1]; 7468 u8 reserved_at_2e1[0x1f]; 7469 7470 u8 reserved_at_300[0x580]; 7471 7472 u8 pas[][0x40]; 7473 }; 7474 7475 struct mlx5_ifc_modify_cong_status_out_bits { 7476 u8 status[0x8]; 7477 u8 reserved_at_8[0x18]; 7478 7479 u8 syndrome[0x20]; 7480 7481 u8 reserved_at_40[0x40]; 7482 }; 7483 7484 struct mlx5_ifc_modify_cong_status_in_bits { 7485 u8 opcode[0x10]; 7486 u8 reserved_at_10[0x10]; 7487 7488 u8 reserved_at_20[0x10]; 7489 u8 op_mod[0x10]; 7490 7491 u8 reserved_at_40[0x18]; 7492 u8 priority[0x4]; 7493 u8 cong_protocol[0x4]; 7494 7495 u8 enable[0x1]; 7496 u8 tag_enable[0x1]; 7497 u8 reserved_at_62[0x1e]; 7498 }; 7499 7500 struct mlx5_ifc_modify_cong_params_out_bits { 7501 u8 status[0x8]; 7502 u8 reserved_at_8[0x18]; 7503 7504 u8 syndrome[0x20]; 7505 7506 u8 reserved_at_40[0x40]; 7507 }; 7508 7509 struct mlx5_ifc_modify_cong_params_in_bits { 7510 u8 opcode[0x10]; 7511 u8 reserved_at_10[0x10]; 7512 7513 u8 reserved_at_20[0x10]; 7514 u8 op_mod[0x10]; 7515 7516 u8 reserved_at_40[0x1c]; 7517 u8 cong_protocol[0x4]; 7518 7519 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select; 7520 7521 u8 reserved_at_80[0x80]; 7522 7523 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 7524 }; 7525 7526 struct mlx5_ifc_manage_pages_out_bits { 7527 u8 status[0x8]; 7528 u8 reserved_at_8[0x18]; 7529 7530 u8 syndrome[0x20]; 7531 7532 u8 output_num_entries[0x20]; 7533 7534 u8 reserved_at_60[0x20]; 7535 7536 u8 pas[][0x40]; 7537 }; 7538 7539 enum { 7540 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL = 0x0, 7541 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS = 0x1, 7542 MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES = 0x2, 7543 }; 7544 7545 struct mlx5_ifc_manage_pages_in_bits { 7546 u8 opcode[0x10]; 7547 u8 reserved_at_10[0x10]; 7548 7549 u8 reserved_at_20[0x10]; 7550 u8 op_mod[0x10]; 7551 7552 u8 embedded_cpu_function[0x1]; 7553 u8 reserved_at_41[0xf]; 7554 u8 function_id[0x10]; 7555 7556 u8 input_num_entries[0x20]; 7557 7558 u8 pas[][0x40]; 7559 }; 7560 7561 struct mlx5_ifc_mad_ifc_out_bits { 7562 u8 status[0x8]; 7563 u8 reserved_at_8[0x18]; 7564 7565 u8 syndrome[0x20]; 7566 7567 u8 reserved_at_40[0x40]; 7568 7569 u8 response_mad_packet[256][0x8]; 7570 }; 7571 7572 struct mlx5_ifc_mad_ifc_in_bits { 7573 u8 opcode[0x10]; 7574 u8 reserved_at_10[0x10]; 7575 7576 u8 reserved_at_20[0x10]; 7577 u8 op_mod[0x10]; 7578 7579 u8 remote_lid[0x10]; 7580 u8 reserved_at_50[0x8]; 7581 u8 port[0x8]; 7582 7583 u8 reserved_at_60[0x20]; 7584 7585 u8 mad[256][0x8]; 7586 }; 7587 7588 struct mlx5_ifc_init_hca_out_bits { 7589 u8 status[0x8]; 7590 u8 reserved_at_8[0x18]; 7591 7592 u8 syndrome[0x20]; 7593 7594 u8 reserved_at_40[0x40]; 7595 }; 7596 7597 struct mlx5_ifc_init_hca_in_bits { 7598 u8 opcode[0x10]; 7599 u8 reserved_at_10[0x10]; 7600 7601 u8 reserved_at_20[0x10]; 7602 u8 op_mod[0x10]; 7603 7604 u8 reserved_at_40[0x20]; 7605 7606 u8 reserved_at_60[0x2]; 7607 u8 sw_vhca_id[0xe]; 7608 u8 reserved_at_70[0x10]; 7609 7610 u8 sw_owner_id[4][0x20]; 7611 }; 7612 7613 struct mlx5_ifc_init2rtr_qp_out_bits { 7614 u8 status[0x8]; 7615 u8 reserved_at_8[0x18]; 7616 7617 u8 syndrome[0x20]; 7618 7619 u8 reserved_at_40[0x20]; 7620 u8 ece[0x20]; 7621 }; 7622 7623 struct mlx5_ifc_init2rtr_qp_in_bits { 7624 u8 opcode[0x10]; 7625 u8 uid[0x10]; 7626 7627 u8 reserved_at_20[0x10]; 7628 u8 op_mod[0x10]; 7629 7630 u8 reserved_at_40[0x8]; 7631 u8 qpn[0x18]; 7632 7633 u8 reserved_at_60[0x20]; 7634 7635 u8 opt_param_mask[0x20]; 7636 7637 u8 ece[0x20]; 7638 7639 struct mlx5_ifc_qpc_bits qpc; 7640 7641 u8 reserved_at_800[0x80]; 7642 }; 7643 7644 struct mlx5_ifc_init2init_qp_out_bits { 7645 u8 status[0x8]; 7646 u8 reserved_at_8[0x18]; 7647 7648 u8 syndrome[0x20]; 7649 7650 u8 reserved_at_40[0x20]; 7651 u8 ece[0x20]; 7652 }; 7653 7654 struct mlx5_ifc_init2init_qp_in_bits { 7655 u8 opcode[0x10]; 7656 u8 uid[0x10]; 7657 7658 u8 reserved_at_20[0x10]; 7659 u8 op_mod[0x10]; 7660 7661 u8 reserved_at_40[0x8]; 7662 u8 qpn[0x18]; 7663 7664 u8 reserved_at_60[0x20]; 7665 7666 u8 opt_param_mask[0x20]; 7667 7668 u8 ece[0x20]; 7669 7670 struct mlx5_ifc_qpc_bits qpc; 7671 7672 u8 reserved_at_800[0x80]; 7673 }; 7674 7675 struct mlx5_ifc_get_dropped_packet_log_out_bits { 7676 u8 status[0x8]; 7677 u8 reserved_at_8[0x18]; 7678 7679 u8 syndrome[0x20]; 7680 7681 u8 reserved_at_40[0x40]; 7682 7683 u8 packet_headers_log[128][0x8]; 7684 7685 u8 packet_syndrome[64][0x8]; 7686 }; 7687 7688 struct mlx5_ifc_get_dropped_packet_log_in_bits { 7689 u8 opcode[0x10]; 7690 u8 reserved_at_10[0x10]; 7691 7692 u8 reserved_at_20[0x10]; 7693 u8 op_mod[0x10]; 7694 7695 u8 reserved_at_40[0x40]; 7696 }; 7697 7698 struct mlx5_ifc_gen_eqe_in_bits { 7699 u8 opcode[0x10]; 7700 u8 reserved_at_10[0x10]; 7701 7702 u8 reserved_at_20[0x10]; 7703 u8 op_mod[0x10]; 7704 7705 u8 reserved_at_40[0x18]; 7706 u8 eq_number[0x8]; 7707 7708 u8 reserved_at_60[0x20]; 7709 7710 u8 eqe[64][0x8]; 7711 }; 7712 7713 struct mlx5_ifc_gen_eq_out_bits { 7714 u8 status[0x8]; 7715 u8 reserved_at_8[0x18]; 7716 7717 u8 syndrome[0x20]; 7718 7719 u8 reserved_at_40[0x40]; 7720 }; 7721 7722 struct mlx5_ifc_enable_hca_out_bits { 7723 u8 status[0x8]; 7724 u8 reserved_at_8[0x18]; 7725 7726 u8 syndrome[0x20]; 7727 7728 u8 reserved_at_40[0x20]; 7729 }; 7730 7731 struct mlx5_ifc_enable_hca_in_bits { 7732 u8 opcode[0x10]; 7733 u8 reserved_at_10[0x10]; 7734 7735 u8 reserved_at_20[0x10]; 7736 u8 op_mod[0x10]; 7737 7738 u8 embedded_cpu_function[0x1]; 7739 u8 reserved_at_41[0xf]; 7740 u8 function_id[0x10]; 7741 7742 u8 reserved_at_60[0x20]; 7743 }; 7744 7745 struct mlx5_ifc_drain_dct_out_bits { 7746 u8 status[0x8]; 7747 u8 reserved_at_8[0x18]; 7748 7749 u8 syndrome[0x20]; 7750 7751 u8 reserved_at_40[0x40]; 7752 }; 7753 7754 struct mlx5_ifc_drain_dct_in_bits { 7755 u8 opcode[0x10]; 7756 u8 uid[0x10]; 7757 7758 u8 reserved_at_20[0x10]; 7759 u8 op_mod[0x10]; 7760 7761 u8 reserved_at_40[0x8]; 7762 u8 dctn[0x18]; 7763 7764 u8 reserved_at_60[0x20]; 7765 }; 7766 7767 struct mlx5_ifc_disable_hca_out_bits { 7768 u8 status[0x8]; 7769 u8 reserved_at_8[0x18]; 7770 7771 u8 syndrome[0x20]; 7772 7773 u8 reserved_at_40[0x20]; 7774 }; 7775 7776 struct mlx5_ifc_disable_hca_in_bits { 7777 u8 opcode[0x10]; 7778 u8 reserved_at_10[0x10]; 7779 7780 u8 reserved_at_20[0x10]; 7781 u8 op_mod[0x10]; 7782 7783 u8 embedded_cpu_function[0x1]; 7784 u8 reserved_at_41[0xf]; 7785 u8 function_id[0x10]; 7786 7787 u8 reserved_at_60[0x20]; 7788 }; 7789 7790 struct mlx5_ifc_detach_from_mcg_out_bits { 7791 u8 status[0x8]; 7792 u8 reserved_at_8[0x18]; 7793 7794 u8 syndrome[0x20]; 7795 7796 u8 reserved_at_40[0x40]; 7797 }; 7798 7799 struct mlx5_ifc_detach_from_mcg_in_bits { 7800 u8 opcode[0x10]; 7801 u8 uid[0x10]; 7802 7803 u8 reserved_at_20[0x10]; 7804 u8 op_mod[0x10]; 7805 7806 u8 reserved_at_40[0x8]; 7807 u8 qpn[0x18]; 7808 7809 u8 reserved_at_60[0x20]; 7810 7811 u8 multicast_gid[16][0x8]; 7812 }; 7813 7814 struct mlx5_ifc_destroy_xrq_out_bits { 7815 u8 status[0x8]; 7816 u8 reserved_at_8[0x18]; 7817 7818 u8 syndrome[0x20]; 7819 7820 u8 reserved_at_40[0x40]; 7821 }; 7822 7823 struct mlx5_ifc_destroy_xrq_in_bits { 7824 u8 opcode[0x10]; 7825 u8 uid[0x10]; 7826 7827 u8 reserved_at_20[0x10]; 7828 u8 op_mod[0x10]; 7829 7830 u8 reserved_at_40[0x8]; 7831 u8 xrqn[0x18]; 7832 7833 u8 reserved_at_60[0x20]; 7834 }; 7835 7836 struct mlx5_ifc_destroy_xrc_srq_out_bits { 7837 u8 status[0x8]; 7838 u8 reserved_at_8[0x18]; 7839 7840 u8 syndrome[0x20]; 7841 7842 u8 reserved_at_40[0x40]; 7843 }; 7844 7845 struct mlx5_ifc_destroy_xrc_srq_in_bits { 7846 u8 opcode[0x10]; 7847 u8 uid[0x10]; 7848 7849 u8 reserved_at_20[0x10]; 7850 u8 op_mod[0x10]; 7851 7852 u8 reserved_at_40[0x8]; 7853 u8 xrc_srqn[0x18]; 7854 7855 u8 reserved_at_60[0x20]; 7856 }; 7857 7858 struct mlx5_ifc_destroy_tis_out_bits { 7859 u8 status[0x8]; 7860 u8 reserved_at_8[0x18]; 7861 7862 u8 syndrome[0x20]; 7863 7864 u8 reserved_at_40[0x40]; 7865 }; 7866 7867 struct mlx5_ifc_destroy_tis_in_bits { 7868 u8 opcode[0x10]; 7869 u8 uid[0x10]; 7870 7871 u8 reserved_at_20[0x10]; 7872 u8 op_mod[0x10]; 7873 7874 u8 reserved_at_40[0x8]; 7875 u8 tisn[0x18]; 7876 7877 u8 reserved_at_60[0x20]; 7878 }; 7879 7880 struct mlx5_ifc_destroy_tir_out_bits { 7881 u8 status[0x8]; 7882 u8 reserved_at_8[0x18]; 7883 7884 u8 syndrome[0x20]; 7885 7886 u8 reserved_at_40[0x40]; 7887 }; 7888 7889 struct mlx5_ifc_destroy_tir_in_bits { 7890 u8 opcode[0x10]; 7891 u8 uid[0x10]; 7892 7893 u8 reserved_at_20[0x10]; 7894 u8 op_mod[0x10]; 7895 7896 u8 reserved_at_40[0x8]; 7897 u8 tirn[0x18]; 7898 7899 u8 reserved_at_60[0x20]; 7900 }; 7901 7902 struct mlx5_ifc_destroy_srq_out_bits { 7903 u8 status[0x8]; 7904 u8 reserved_at_8[0x18]; 7905 7906 u8 syndrome[0x20]; 7907 7908 u8 reserved_at_40[0x40]; 7909 }; 7910 7911 struct mlx5_ifc_destroy_srq_in_bits { 7912 u8 opcode[0x10]; 7913 u8 uid[0x10]; 7914 7915 u8 reserved_at_20[0x10]; 7916 u8 op_mod[0x10]; 7917 7918 u8 reserved_at_40[0x8]; 7919 u8 srqn[0x18]; 7920 7921 u8 reserved_at_60[0x20]; 7922 }; 7923 7924 struct mlx5_ifc_destroy_sq_out_bits { 7925 u8 status[0x8]; 7926 u8 reserved_at_8[0x18]; 7927 7928 u8 syndrome[0x20]; 7929 7930 u8 reserved_at_40[0x40]; 7931 }; 7932 7933 struct mlx5_ifc_destroy_sq_in_bits { 7934 u8 opcode[0x10]; 7935 u8 uid[0x10]; 7936 7937 u8 reserved_at_20[0x10]; 7938 u8 op_mod[0x10]; 7939 7940 u8 reserved_at_40[0x8]; 7941 u8 sqn[0x18]; 7942 7943 u8 reserved_at_60[0x20]; 7944 }; 7945 7946 struct mlx5_ifc_destroy_scheduling_element_out_bits { 7947 u8 status[0x8]; 7948 u8 reserved_at_8[0x18]; 7949 7950 u8 syndrome[0x20]; 7951 7952 u8 reserved_at_40[0x1c0]; 7953 }; 7954 7955 struct mlx5_ifc_destroy_scheduling_element_in_bits { 7956 u8 opcode[0x10]; 7957 u8 reserved_at_10[0x10]; 7958 7959 u8 reserved_at_20[0x10]; 7960 u8 op_mod[0x10]; 7961 7962 u8 scheduling_hierarchy[0x8]; 7963 u8 reserved_at_48[0x18]; 7964 7965 u8 scheduling_element_id[0x20]; 7966 7967 u8 reserved_at_80[0x180]; 7968 }; 7969 7970 struct mlx5_ifc_destroy_rqt_out_bits { 7971 u8 status[0x8]; 7972 u8 reserved_at_8[0x18]; 7973 7974 u8 syndrome[0x20]; 7975 7976 u8 reserved_at_40[0x40]; 7977 }; 7978 7979 struct mlx5_ifc_destroy_rqt_in_bits { 7980 u8 opcode[0x10]; 7981 u8 uid[0x10]; 7982 7983 u8 reserved_at_20[0x10]; 7984 u8 op_mod[0x10]; 7985 7986 u8 reserved_at_40[0x8]; 7987 u8 rqtn[0x18]; 7988 7989 u8 reserved_at_60[0x20]; 7990 }; 7991 7992 struct mlx5_ifc_destroy_rq_out_bits { 7993 u8 status[0x8]; 7994 u8 reserved_at_8[0x18]; 7995 7996 u8 syndrome[0x20]; 7997 7998 u8 reserved_at_40[0x40]; 7999 }; 8000 8001 struct mlx5_ifc_destroy_rq_in_bits { 8002 u8 opcode[0x10]; 8003 u8 uid[0x10]; 8004 8005 u8 reserved_at_20[0x10]; 8006 u8 op_mod[0x10]; 8007 8008 u8 reserved_at_40[0x8]; 8009 u8 rqn[0x18]; 8010 8011 u8 reserved_at_60[0x20]; 8012 }; 8013 8014 struct mlx5_ifc_set_delay_drop_params_in_bits { 8015 u8 opcode[0x10]; 8016 u8 reserved_at_10[0x10]; 8017 8018 u8 reserved_at_20[0x10]; 8019 u8 op_mod[0x10]; 8020 8021 u8 reserved_at_40[0x20]; 8022 8023 u8 reserved_at_60[0x10]; 8024 u8 delay_drop_timeout[0x10]; 8025 }; 8026 8027 struct mlx5_ifc_set_delay_drop_params_out_bits { 8028 u8 status[0x8]; 8029 u8 reserved_at_8[0x18]; 8030 8031 u8 syndrome[0x20]; 8032 8033 u8 reserved_at_40[0x40]; 8034 }; 8035 8036 struct mlx5_ifc_destroy_rmp_out_bits { 8037 u8 status[0x8]; 8038 u8 reserved_at_8[0x18]; 8039 8040 u8 syndrome[0x20]; 8041 8042 u8 reserved_at_40[0x40]; 8043 }; 8044 8045 struct mlx5_ifc_destroy_rmp_in_bits { 8046 u8 opcode[0x10]; 8047 u8 uid[0x10]; 8048 8049 u8 reserved_at_20[0x10]; 8050 u8 op_mod[0x10]; 8051 8052 u8 reserved_at_40[0x8]; 8053 u8 rmpn[0x18]; 8054 8055 u8 reserved_at_60[0x20]; 8056 }; 8057 8058 struct mlx5_ifc_destroy_qp_out_bits { 8059 u8 status[0x8]; 8060 u8 reserved_at_8[0x18]; 8061 8062 u8 syndrome[0x20]; 8063 8064 u8 reserved_at_40[0x40]; 8065 }; 8066 8067 struct mlx5_ifc_destroy_qp_in_bits { 8068 u8 opcode[0x10]; 8069 u8 uid[0x10]; 8070 8071 u8 reserved_at_20[0x10]; 8072 u8 op_mod[0x10]; 8073 8074 u8 reserved_at_40[0x8]; 8075 u8 qpn[0x18]; 8076 8077 u8 reserved_at_60[0x20]; 8078 }; 8079 8080 struct mlx5_ifc_destroy_psv_out_bits { 8081 u8 status[0x8]; 8082 u8 reserved_at_8[0x18]; 8083 8084 u8 syndrome[0x20]; 8085 8086 u8 reserved_at_40[0x40]; 8087 }; 8088 8089 struct mlx5_ifc_destroy_psv_in_bits { 8090 u8 opcode[0x10]; 8091 u8 reserved_at_10[0x10]; 8092 8093 u8 reserved_at_20[0x10]; 8094 u8 op_mod[0x10]; 8095 8096 u8 reserved_at_40[0x8]; 8097 u8 psvn[0x18]; 8098 8099 u8 reserved_at_60[0x20]; 8100 }; 8101 8102 struct mlx5_ifc_destroy_mkey_out_bits { 8103 u8 status[0x8]; 8104 u8 reserved_at_8[0x18]; 8105 8106 u8 syndrome[0x20]; 8107 8108 u8 reserved_at_40[0x40]; 8109 }; 8110 8111 struct mlx5_ifc_destroy_mkey_in_bits { 8112 u8 opcode[0x10]; 8113 u8 uid[0x10]; 8114 8115 u8 reserved_at_20[0x10]; 8116 u8 op_mod[0x10]; 8117 8118 u8 reserved_at_40[0x8]; 8119 u8 mkey_index[0x18]; 8120 8121 u8 reserved_at_60[0x20]; 8122 }; 8123 8124 struct mlx5_ifc_destroy_flow_table_out_bits { 8125 u8 status[0x8]; 8126 u8 reserved_at_8[0x18]; 8127 8128 u8 syndrome[0x20]; 8129 8130 u8 reserved_at_40[0x40]; 8131 }; 8132 8133 struct mlx5_ifc_destroy_flow_table_in_bits { 8134 u8 opcode[0x10]; 8135 u8 reserved_at_10[0x10]; 8136 8137 u8 reserved_at_20[0x10]; 8138 u8 op_mod[0x10]; 8139 8140 u8 other_vport[0x1]; 8141 u8 reserved_at_41[0xf]; 8142 u8 vport_number[0x10]; 8143 8144 u8 reserved_at_60[0x20]; 8145 8146 u8 table_type[0x8]; 8147 u8 reserved_at_88[0x18]; 8148 8149 u8 reserved_at_a0[0x8]; 8150 u8 table_id[0x18]; 8151 8152 u8 reserved_at_c0[0x140]; 8153 }; 8154 8155 struct mlx5_ifc_destroy_flow_group_out_bits { 8156 u8 status[0x8]; 8157 u8 reserved_at_8[0x18]; 8158 8159 u8 syndrome[0x20]; 8160 8161 u8 reserved_at_40[0x40]; 8162 }; 8163 8164 struct mlx5_ifc_destroy_flow_group_in_bits { 8165 u8 opcode[0x10]; 8166 u8 reserved_at_10[0x10]; 8167 8168 u8 reserved_at_20[0x10]; 8169 u8 op_mod[0x10]; 8170 8171 u8 other_vport[0x1]; 8172 u8 reserved_at_41[0xf]; 8173 u8 vport_number[0x10]; 8174 8175 u8 reserved_at_60[0x20]; 8176 8177 u8 table_type[0x8]; 8178 u8 reserved_at_88[0x18]; 8179 8180 u8 reserved_at_a0[0x8]; 8181 u8 table_id[0x18]; 8182 8183 u8 group_id[0x20]; 8184 8185 u8 reserved_at_e0[0x120]; 8186 }; 8187 8188 struct mlx5_ifc_destroy_eq_out_bits { 8189 u8 status[0x8]; 8190 u8 reserved_at_8[0x18]; 8191 8192 u8 syndrome[0x20]; 8193 8194 u8 reserved_at_40[0x40]; 8195 }; 8196 8197 struct mlx5_ifc_destroy_eq_in_bits { 8198 u8 opcode[0x10]; 8199 u8 reserved_at_10[0x10]; 8200 8201 u8 reserved_at_20[0x10]; 8202 u8 op_mod[0x10]; 8203 8204 u8 reserved_at_40[0x18]; 8205 u8 eq_number[0x8]; 8206 8207 u8 reserved_at_60[0x20]; 8208 }; 8209 8210 struct mlx5_ifc_destroy_dct_out_bits { 8211 u8 status[0x8]; 8212 u8 reserved_at_8[0x18]; 8213 8214 u8 syndrome[0x20]; 8215 8216 u8 reserved_at_40[0x40]; 8217 }; 8218 8219 struct mlx5_ifc_destroy_dct_in_bits { 8220 u8 opcode[0x10]; 8221 u8 uid[0x10]; 8222 8223 u8 reserved_at_20[0x10]; 8224 u8 op_mod[0x10]; 8225 8226 u8 reserved_at_40[0x8]; 8227 u8 dctn[0x18]; 8228 8229 u8 reserved_at_60[0x20]; 8230 }; 8231 8232 struct mlx5_ifc_destroy_cq_out_bits { 8233 u8 status[0x8]; 8234 u8 reserved_at_8[0x18]; 8235 8236 u8 syndrome[0x20]; 8237 8238 u8 reserved_at_40[0x40]; 8239 }; 8240 8241 struct mlx5_ifc_destroy_cq_in_bits { 8242 u8 opcode[0x10]; 8243 u8 uid[0x10]; 8244 8245 u8 reserved_at_20[0x10]; 8246 u8 op_mod[0x10]; 8247 8248 u8 reserved_at_40[0x8]; 8249 u8 cqn[0x18]; 8250 8251 u8 reserved_at_60[0x20]; 8252 }; 8253 8254 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits { 8255 u8 status[0x8]; 8256 u8 reserved_at_8[0x18]; 8257 8258 u8 syndrome[0x20]; 8259 8260 u8 reserved_at_40[0x40]; 8261 }; 8262 8263 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits { 8264 u8 opcode[0x10]; 8265 u8 reserved_at_10[0x10]; 8266 8267 u8 reserved_at_20[0x10]; 8268 u8 op_mod[0x10]; 8269 8270 u8 reserved_at_40[0x20]; 8271 8272 u8 reserved_at_60[0x10]; 8273 u8 vxlan_udp_port[0x10]; 8274 }; 8275 8276 struct mlx5_ifc_delete_l2_table_entry_out_bits { 8277 u8 status[0x8]; 8278 u8 reserved_at_8[0x18]; 8279 8280 u8 syndrome[0x20]; 8281 8282 u8 reserved_at_40[0x40]; 8283 }; 8284 8285 struct mlx5_ifc_delete_l2_table_entry_in_bits { 8286 u8 opcode[0x10]; 8287 u8 reserved_at_10[0x10]; 8288 8289 u8 reserved_at_20[0x10]; 8290 u8 op_mod[0x10]; 8291 8292 u8 reserved_at_40[0x60]; 8293 8294 u8 reserved_at_a0[0x8]; 8295 u8 table_index[0x18]; 8296 8297 u8 reserved_at_c0[0x140]; 8298 }; 8299 8300 struct mlx5_ifc_delete_fte_out_bits { 8301 u8 status[0x8]; 8302 u8 reserved_at_8[0x18]; 8303 8304 u8 syndrome[0x20]; 8305 8306 u8 reserved_at_40[0x40]; 8307 }; 8308 8309 struct mlx5_ifc_delete_fte_in_bits { 8310 u8 opcode[0x10]; 8311 u8 reserved_at_10[0x10]; 8312 8313 u8 reserved_at_20[0x10]; 8314 u8 op_mod[0x10]; 8315 8316 u8 other_vport[0x1]; 8317 u8 reserved_at_41[0xf]; 8318 u8 vport_number[0x10]; 8319 8320 u8 reserved_at_60[0x20]; 8321 8322 u8 table_type[0x8]; 8323 u8 reserved_at_88[0x18]; 8324 8325 u8 reserved_at_a0[0x8]; 8326 u8 table_id[0x18]; 8327 8328 u8 reserved_at_c0[0x40]; 8329 8330 u8 flow_index[0x20]; 8331 8332 u8 reserved_at_120[0xe0]; 8333 }; 8334 8335 struct mlx5_ifc_dealloc_xrcd_out_bits { 8336 u8 status[0x8]; 8337 u8 reserved_at_8[0x18]; 8338 8339 u8 syndrome[0x20]; 8340 8341 u8 reserved_at_40[0x40]; 8342 }; 8343 8344 struct mlx5_ifc_dealloc_xrcd_in_bits { 8345 u8 opcode[0x10]; 8346 u8 uid[0x10]; 8347 8348 u8 reserved_at_20[0x10]; 8349 u8 op_mod[0x10]; 8350 8351 u8 reserved_at_40[0x8]; 8352 u8 xrcd[0x18]; 8353 8354 u8 reserved_at_60[0x20]; 8355 }; 8356 8357 struct mlx5_ifc_dealloc_uar_out_bits { 8358 u8 status[0x8]; 8359 u8 reserved_at_8[0x18]; 8360 8361 u8 syndrome[0x20]; 8362 8363 u8 reserved_at_40[0x40]; 8364 }; 8365 8366 struct mlx5_ifc_dealloc_uar_in_bits { 8367 u8 opcode[0x10]; 8368 u8 uid[0x10]; 8369 8370 u8 reserved_at_20[0x10]; 8371 u8 op_mod[0x10]; 8372 8373 u8 reserved_at_40[0x8]; 8374 u8 uar[0x18]; 8375 8376 u8 reserved_at_60[0x20]; 8377 }; 8378 8379 struct mlx5_ifc_dealloc_transport_domain_out_bits { 8380 u8 status[0x8]; 8381 u8 reserved_at_8[0x18]; 8382 8383 u8 syndrome[0x20]; 8384 8385 u8 reserved_at_40[0x40]; 8386 }; 8387 8388 struct mlx5_ifc_dealloc_transport_domain_in_bits { 8389 u8 opcode[0x10]; 8390 u8 uid[0x10]; 8391 8392 u8 reserved_at_20[0x10]; 8393 u8 op_mod[0x10]; 8394 8395 u8 reserved_at_40[0x8]; 8396 u8 transport_domain[0x18]; 8397 8398 u8 reserved_at_60[0x20]; 8399 }; 8400 8401 struct mlx5_ifc_dealloc_q_counter_out_bits { 8402 u8 status[0x8]; 8403 u8 reserved_at_8[0x18]; 8404 8405 u8 syndrome[0x20]; 8406 8407 u8 reserved_at_40[0x40]; 8408 }; 8409 8410 struct mlx5_ifc_dealloc_q_counter_in_bits { 8411 u8 opcode[0x10]; 8412 u8 reserved_at_10[0x10]; 8413 8414 u8 reserved_at_20[0x10]; 8415 u8 op_mod[0x10]; 8416 8417 u8 reserved_at_40[0x18]; 8418 u8 counter_set_id[0x8]; 8419 8420 u8 reserved_at_60[0x20]; 8421 }; 8422 8423 struct mlx5_ifc_dealloc_pd_out_bits { 8424 u8 status[0x8]; 8425 u8 reserved_at_8[0x18]; 8426 8427 u8 syndrome[0x20]; 8428 8429 u8 reserved_at_40[0x40]; 8430 }; 8431 8432 struct mlx5_ifc_dealloc_pd_in_bits { 8433 u8 opcode[0x10]; 8434 u8 uid[0x10]; 8435 8436 u8 reserved_at_20[0x10]; 8437 u8 op_mod[0x10]; 8438 8439 u8 reserved_at_40[0x8]; 8440 u8 pd[0x18]; 8441 8442 u8 reserved_at_60[0x20]; 8443 }; 8444 8445 struct mlx5_ifc_dealloc_flow_counter_out_bits { 8446 u8 status[0x8]; 8447 u8 reserved_at_8[0x18]; 8448 8449 u8 syndrome[0x20]; 8450 8451 u8 reserved_at_40[0x40]; 8452 }; 8453 8454 struct mlx5_ifc_dealloc_flow_counter_in_bits { 8455 u8 opcode[0x10]; 8456 u8 reserved_at_10[0x10]; 8457 8458 u8 reserved_at_20[0x10]; 8459 u8 op_mod[0x10]; 8460 8461 u8 flow_counter_id[0x20]; 8462 8463 u8 reserved_at_60[0x20]; 8464 }; 8465 8466 struct mlx5_ifc_create_xrq_out_bits { 8467 u8 status[0x8]; 8468 u8 reserved_at_8[0x18]; 8469 8470 u8 syndrome[0x20]; 8471 8472 u8 reserved_at_40[0x8]; 8473 u8 xrqn[0x18]; 8474 8475 u8 reserved_at_60[0x20]; 8476 }; 8477 8478 struct mlx5_ifc_create_xrq_in_bits { 8479 u8 opcode[0x10]; 8480 u8 uid[0x10]; 8481 8482 u8 reserved_at_20[0x10]; 8483 u8 op_mod[0x10]; 8484 8485 u8 reserved_at_40[0x40]; 8486 8487 struct mlx5_ifc_xrqc_bits xrq_context; 8488 }; 8489 8490 struct mlx5_ifc_create_xrc_srq_out_bits { 8491 u8 status[0x8]; 8492 u8 reserved_at_8[0x18]; 8493 8494 u8 syndrome[0x20]; 8495 8496 u8 reserved_at_40[0x8]; 8497 u8 xrc_srqn[0x18]; 8498 8499 u8 reserved_at_60[0x20]; 8500 }; 8501 8502 struct mlx5_ifc_create_xrc_srq_in_bits { 8503 u8 opcode[0x10]; 8504 u8 uid[0x10]; 8505 8506 u8 reserved_at_20[0x10]; 8507 u8 op_mod[0x10]; 8508 8509 u8 reserved_at_40[0x40]; 8510 8511 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 8512 8513 u8 reserved_at_280[0x60]; 8514 8515 u8 xrc_srq_umem_valid[0x1]; 8516 u8 reserved_at_2e1[0x1f]; 8517 8518 u8 reserved_at_300[0x580]; 8519 8520 u8 pas[][0x40]; 8521 }; 8522 8523 struct mlx5_ifc_create_tis_out_bits { 8524 u8 status[0x8]; 8525 u8 reserved_at_8[0x18]; 8526 8527 u8 syndrome[0x20]; 8528 8529 u8 reserved_at_40[0x8]; 8530 u8 tisn[0x18]; 8531 8532 u8 reserved_at_60[0x20]; 8533 }; 8534 8535 struct mlx5_ifc_create_tis_in_bits { 8536 u8 opcode[0x10]; 8537 u8 uid[0x10]; 8538 8539 u8 reserved_at_20[0x10]; 8540 u8 op_mod[0x10]; 8541 8542 u8 reserved_at_40[0xc0]; 8543 8544 struct mlx5_ifc_tisc_bits ctx; 8545 }; 8546 8547 struct mlx5_ifc_create_tir_out_bits { 8548 u8 status[0x8]; 8549 u8 icm_address_63_40[0x18]; 8550 8551 u8 syndrome[0x20]; 8552 8553 u8 icm_address_39_32[0x8]; 8554 u8 tirn[0x18]; 8555 8556 u8 icm_address_31_0[0x20]; 8557 }; 8558 8559 struct mlx5_ifc_create_tir_in_bits { 8560 u8 opcode[0x10]; 8561 u8 uid[0x10]; 8562 8563 u8 reserved_at_20[0x10]; 8564 u8 op_mod[0x10]; 8565 8566 u8 reserved_at_40[0xc0]; 8567 8568 struct mlx5_ifc_tirc_bits ctx; 8569 }; 8570 8571 struct mlx5_ifc_create_srq_out_bits { 8572 u8 status[0x8]; 8573 u8 reserved_at_8[0x18]; 8574 8575 u8 syndrome[0x20]; 8576 8577 u8 reserved_at_40[0x8]; 8578 u8 srqn[0x18]; 8579 8580 u8 reserved_at_60[0x20]; 8581 }; 8582 8583 struct mlx5_ifc_create_srq_in_bits { 8584 u8 opcode[0x10]; 8585 u8 uid[0x10]; 8586 8587 u8 reserved_at_20[0x10]; 8588 u8 op_mod[0x10]; 8589 8590 u8 reserved_at_40[0x40]; 8591 8592 struct mlx5_ifc_srqc_bits srq_context_entry; 8593 8594 u8 reserved_at_280[0x600]; 8595 8596 u8 pas[][0x40]; 8597 }; 8598 8599 struct mlx5_ifc_create_sq_out_bits { 8600 u8 status[0x8]; 8601 u8 reserved_at_8[0x18]; 8602 8603 u8 syndrome[0x20]; 8604 8605 u8 reserved_at_40[0x8]; 8606 u8 sqn[0x18]; 8607 8608 u8 reserved_at_60[0x20]; 8609 }; 8610 8611 struct mlx5_ifc_create_sq_in_bits { 8612 u8 opcode[0x10]; 8613 u8 uid[0x10]; 8614 8615 u8 reserved_at_20[0x10]; 8616 u8 op_mod[0x10]; 8617 8618 u8 reserved_at_40[0xc0]; 8619 8620 struct mlx5_ifc_sqc_bits ctx; 8621 }; 8622 8623 struct mlx5_ifc_create_scheduling_element_out_bits { 8624 u8 status[0x8]; 8625 u8 reserved_at_8[0x18]; 8626 8627 u8 syndrome[0x20]; 8628 8629 u8 reserved_at_40[0x40]; 8630 8631 u8 scheduling_element_id[0x20]; 8632 8633 u8 reserved_at_a0[0x160]; 8634 }; 8635 8636 struct mlx5_ifc_create_scheduling_element_in_bits { 8637 u8 opcode[0x10]; 8638 u8 reserved_at_10[0x10]; 8639 8640 u8 reserved_at_20[0x10]; 8641 u8 op_mod[0x10]; 8642 8643 u8 scheduling_hierarchy[0x8]; 8644 u8 reserved_at_48[0x18]; 8645 8646 u8 reserved_at_60[0xa0]; 8647 8648 struct mlx5_ifc_scheduling_context_bits scheduling_context; 8649 8650 u8 reserved_at_300[0x100]; 8651 }; 8652 8653 struct mlx5_ifc_create_rqt_out_bits { 8654 u8 status[0x8]; 8655 u8 reserved_at_8[0x18]; 8656 8657 u8 syndrome[0x20]; 8658 8659 u8 reserved_at_40[0x8]; 8660 u8 rqtn[0x18]; 8661 8662 u8 reserved_at_60[0x20]; 8663 }; 8664 8665 struct mlx5_ifc_create_rqt_in_bits { 8666 u8 opcode[0x10]; 8667 u8 uid[0x10]; 8668 8669 u8 reserved_at_20[0x10]; 8670 u8 op_mod[0x10]; 8671 8672 u8 reserved_at_40[0xc0]; 8673 8674 struct mlx5_ifc_rqtc_bits rqt_context; 8675 }; 8676 8677 struct mlx5_ifc_create_rq_out_bits { 8678 u8 status[0x8]; 8679 u8 reserved_at_8[0x18]; 8680 8681 u8 syndrome[0x20]; 8682 8683 u8 reserved_at_40[0x8]; 8684 u8 rqn[0x18]; 8685 8686 u8 reserved_at_60[0x20]; 8687 }; 8688 8689 struct mlx5_ifc_create_rq_in_bits { 8690 u8 opcode[0x10]; 8691 u8 uid[0x10]; 8692 8693 u8 reserved_at_20[0x10]; 8694 u8 op_mod[0x10]; 8695 8696 u8 reserved_at_40[0xc0]; 8697 8698 struct mlx5_ifc_rqc_bits ctx; 8699 }; 8700 8701 struct mlx5_ifc_create_rmp_out_bits { 8702 u8 status[0x8]; 8703 u8 reserved_at_8[0x18]; 8704 8705 u8 syndrome[0x20]; 8706 8707 u8 reserved_at_40[0x8]; 8708 u8 rmpn[0x18]; 8709 8710 u8 reserved_at_60[0x20]; 8711 }; 8712 8713 struct mlx5_ifc_create_rmp_in_bits { 8714 u8 opcode[0x10]; 8715 u8 uid[0x10]; 8716 8717 u8 reserved_at_20[0x10]; 8718 u8 op_mod[0x10]; 8719 8720 u8 reserved_at_40[0xc0]; 8721 8722 struct mlx5_ifc_rmpc_bits ctx; 8723 }; 8724 8725 struct mlx5_ifc_create_qp_out_bits { 8726 u8 status[0x8]; 8727 u8 reserved_at_8[0x18]; 8728 8729 u8 syndrome[0x20]; 8730 8731 u8 reserved_at_40[0x8]; 8732 u8 qpn[0x18]; 8733 8734 u8 ece[0x20]; 8735 }; 8736 8737 struct mlx5_ifc_create_qp_in_bits { 8738 u8 opcode[0x10]; 8739 u8 uid[0x10]; 8740 8741 u8 reserved_at_20[0x10]; 8742 u8 op_mod[0x10]; 8743 8744 u8 qpc_ext[0x1]; 8745 u8 reserved_at_41[0x7]; 8746 u8 input_qpn[0x18]; 8747 8748 u8 reserved_at_60[0x20]; 8749 u8 opt_param_mask[0x20]; 8750 8751 u8 ece[0x20]; 8752 8753 struct mlx5_ifc_qpc_bits qpc; 8754 8755 u8 reserved_at_800[0x60]; 8756 8757 u8 wq_umem_valid[0x1]; 8758 u8 reserved_at_861[0x1f]; 8759 8760 u8 pas[][0x40]; 8761 }; 8762 8763 struct mlx5_ifc_create_psv_out_bits { 8764 u8 status[0x8]; 8765 u8 reserved_at_8[0x18]; 8766 8767 u8 syndrome[0x20]; 8768 8769 u8 reserved_at_40[0x40]; 8770 8771 u8 reserved_at_80[0x8]; 8772 u8 psv0_index[0x18]; 8773 8774 u8 reserved_at_a0[0x8]; 8775 u8 psv1_index[0x18]; 8776 8777 u8 reserved_at_c0[0x8]; 8778 u8 psv2_index[0x18]; 8779 8780 u8 reserved_at_e0[0x8]; 8781 u8 psv3_index[0x18]; 8782 }; 8783 8784 struct mlx5_ifc_create_psv_in_bits { 8785 u8 opcode[0x10]; 8786 u8 reserved_at_10[0x10]; 8787 8788 u8 reserved_at_20[0x10]; 8789 u8 op_mod[0x10]; 8790 8791 u8 num_psv[0x4]; 8792 u8 reserved_at_44[0x4]; 8793 u8 pd[0x18]; 8794 8795 u8 reserved_at_60[0x20]; 8796 }; 8797 8798 struct mlx5_ifc_create_mkey_out_bits { 8799 u8 status[0x8]; 8800 u8 reserved_at_8[0x18]; 8801 8802 u8 syndrome[0x20]; 8803 8804 u8 reserved_at_40[0x8]; 8805 u8 mkey_index[0x18]; 8806 8807 u8 reserved_at_60[0x20]; 8808 }; 8809 8810 struct mlx5_ifc_create_mkey_in_bits { 8811 u8 opcode[0x10]; 8812 u8 uid[0x10]; 8813 8814 u8 reserved_at_20[0x10]; 8815 u8 op_mod[0x10]; 8816 8817 u8 reserved_at_40[0x20]; 8818 8819 u8 pg_access[0x1]; 8820 u8 mkey_umem_valid[0x1]; 8821 u8 reserved_at_62[0x1e]; 8822 8823 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 8824 8825 u8 reserved_at_280[0x80]; 8826 8827 u8 translations_octword_actual_size[0x20]; 8828 8829 u8 reserved_at_320[0x560]; 8830 8831 u8 klm_pas_mtt[][0x20]; 8832 }; 8833 8834 enum { 8835 MLX5_FLOW_TABLE_TYPE_NIC_RX = 0x0, 8836 MLX5_FLOW_TABLE_TYPE_NIC_TX = 0x1, 8837 MLX5_FLOW_TABLE_TYPE_ESW_EGRESS_ACL = 0x2, 8838 MLX5_FLOW_TABLE_TYPE_ESW_INGRESS_ACL = 0x3, 8839 MLX5_FLOW_TABLE_TYPE_FDB = 0X4, 8840 MLX5_FLOW_TABLE_TYPE_SNIFFER_RX = 0X5, 8841 MLX5_FLOW_TABLE_TYPE_SNIFFER_TX = 0X6, 8842 }; 8843 8844 struct mlx5_ifc_create_flow_table_out_bits { 8845 u8 status[0x8]; 8846 u8 icm_address_63_40[0x18]; 8847 8848 u8 syndrome[0x20]; 8849 8850 u8 icm_address_39_32[0x8]; 8851 u8 table_id[0x18]; 8852 8853 u8 icm_address_31_0[0x20]; 8854 }; 8855 8856 struct mlx5_ifc_create_flow_table_in_bits { 8857 u8 opcode[0x10]; 8858 u8 uid[0x10]; 8859 8860 u8 reserved_at_20[0x10]; 8861 u8 op_mod[0x10]; 8862 8863 u8 other_vport[0x1]; 8864 u8 reserved_at_41[0xf]; 8865 u8 vport_number[0x10]; 8866 8867 u8 reserved_at_60[0x20]; 8868 8869 u8 table_type[0x8]; 8870 u8 reserved_at_88[0x18]; 8871 8872 u8 reserved_at_a0[0x20]; 8873 8874 struct mlx5_ifc_flow_table_context_bits flow_table_context; 8875 }; 8876 8877 struct mlx5_ifc_create_flow_group_out_bits { 8878 u8 status[0x8]; 8879 u8 reserved_at_8[0x18]; 8880 8881 u8 syndrome[0x20]; 8882 8883 u8 reserved_at_40[0x8]; 8884 u8 group_id[0x18]; 8885 8886 u8 reserved_at_60[0x20]; 8887 }; 8888 8889 enum { 8890 MLX5_CREATE_FLOW_GROUP_IN_GROUP_TYPE_TCAM_SUBTABLE = 0x0, 8891 MLX5_CREATE_FLOW_GROUP_IN_GROUP_TYPE_HASH_SPLIT = 0x1, 8892 }; 8893 8894 enum { 8895 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 8896 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 8897 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 8898 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3, 8899 }; 8900 8901 struct mlx5_ifc_create_flow_group_in_bits { 8902 u8 opcode[0x10]; 8903 u8 reserved_at_10[0x10]; 8904 8905 u8 reserved_at_20[0x10]; 8906 u8 op_mod[0x10]; 8907 8908 u8 other_vport[0x1]; 8909 u8 reserved_at_41[0xf]; 8910 u8 vport_number[0x10]; 8911 8912 u8 reserved_at_60[0x20]; 8913 8914 u8 table_type[0x8]; 8915 u8 reserved_at_88[0x4]; 8916 u8 group_type[0x4]; 8917 u8 reserved_at_90[0x10]; 8918 8919 u8 reserved_at_a0[0x8]; 8920 u8 table_id[0x18]; 8921 8922 u8 source_eswitch_owner_vhca_id_valid[0x1]; 8923 8924 u8 reserved_at_c1[0x1f]; 8925 8926 u8 start_flow_index[0x20]; 8927 8928 u8 reserved_at_100[0x20]; 8929 8930 u8 end_flow_index[0x20]; 8931 8932 u8 reserved_at_140[0x10]; 8933 u8 match_definer_id[0x10]; 8934 8935 u8 reserved_at_160[0x80]; 8936 8937 u8 reserved_at_1e0[0x18]; 8938 u8 match_criteria_enable[0x8]; 8939 8940 struct mlx5_ifc_fte_match_param_bits match_criteria; 8941 8942 u8 reserved_at_1200[0xe00]; 8943 }; 8944 8945 struct mlx5_ifc_create_eq_out_bits { 8946 u8 status[0x8]; 8947 u8 reserved_at_8[0x18]; 8948 8949 u8 syndrome[0x20]; 8950 8951 u8 reserved_at_40[0x18]; 8952 u8 eq_number[0x8]; 8953 8954 u8 reserved_at_60[0x20]; 8955 }; 8956 8957 struct mlx5_ifc_create_eq_in_bits { 8958 u8 opcode[0x10]; 8959 u8 uid[0x10]; 8960 8961 u8 reserved_at_20[0x10]; 8962 u8 op_mod[0x10]; 8963 8964 u8 reserved_at_40[0x40]; 8965 8966 struct mlx5_ifc_eqc_bits eq_context_entry; 8967 8968 u8 reserved_at_280[0x40]; 8969 8970 u8 event_bitmask[4][0x40]; 8971 8972 u8 reserved_at_3c0[0x4c0]; 8973 8974 u8 pas[][0x40]; 8975 }; 8976 8977 struct mlx5_ifc_create_dct_out_bits { 8978 u8 status[0x8]; 8979 u8 reserved_at_8[0x18]; 8980 8981 u8 syndrome[0x20]; 8982 8983 u8 reserved_at_40[0x8]; 8984 u8 dctn[0x18]; 8985 8986 u8 ece[0x20]; 8987 }; 8988 8989 struct mlx5_ifc_create_dct_in_bits { 8990 u8 opcode[0x10]; 8991 u8 uid[0x10]; 8992 8993 u8 reserved_at_20[0x10]; 8994 u8 op_mod[0x10]; 8995 8996 u8 reserved_at_40[0x40]; 8997 8998 struct mlx5_ifc_dctc_bits dct_context_entry; 8999 9000 u8 reserved_at_280[0x180]; 9001 }; 9002 9003 struct mlx5_ifc_create_cq_out_bits { 9004 u8 status[0x8]; 9005 u8 reserved_at_8[0x18]; 9006 9007 u8 syndrome[0x20]; 9008 9009 u8 reserved_at_40[0x8]; 9010 u8 cqn[0x18]; 9011 9012 u8 reserved_at_60[0x20]; 9013 }; 9014 9015 struct mlx5_ifc_create_cq_in_bits { 9016 u8 opcode[0x10]; 9017 u8 uid[0x10]; 9018 9019 u8 reserved_at_20[0x10]; 9020 u8 op_mod[0x10]; 9021 9022 u8 reserved_at_40[0x40]; 9023 9024 struct mlx5_ifc_cqc_bits cq_context; 9025 9026 u8 reserved_at_280[0x60]; 9027 9028 u8 cq_umem_valid[0x1]; 9029 u8 reserved_at_2e1[0x59f]; 9030 9031 u8 pas[][0x40]; 9032 }; 9033 9034 struct mlx5_ifc_config_int_moderation_out_bits { 9035 u8 status[0x8]; 9036 u8 reserved_at_8[0x18]; 9037 9038 u8 syndrome[0x20]; 9039 9040 u8 reserved_at_40[0x4]; 9041 u8 min_delay[0xc]; 9042 u8 int_vector[0x10]; 9043 9044 u8 reserved_at_60[0x20]; 9045 }; 9046 9047 enum { 9048 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0, 9049 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1, 9050 }; 9051 9052 struct mlx5_ifc_config_int_moderation_in_bits { 9053 u8 opcode[0x10]; 9054 u8 reserved_at_10[0x10]; 9055 9056 u8 reserved_at_20[0x10]; 9057 u8 op_mod[0x10]; 9058 9059 u8 reserved_at_40[0x4]; 9060 u8 min_delay[0xc]; 9061 u8 int_vector[0x10]; 9062 9063 u8 reserved_at_60[0x20]; 9064 }; 9065 9066 struct mlx5_ifc_attach_to_mcg_out_bits { 9067 u8 status[0x8]; 9068 u8 reserved_at_8[0x18]; 9069 9070 u8 syndrome[0x20]; 9071 9072 u8 reserved_at_40[0x40]; 9073 }; 9074 9075 struct mlx5_ifc_attach_to_mcg_in_bits { 9076 u8 opcode[0x10]; 9077 u8 uid[0x10]; 9078 9079 u8 reserved_at_20[0x10]; 9080 u8 op_mod[0x10]; 9081 9082 u8 reserved_at_40[0x8]; 9083 u8 qpn[0x18]; 9084 9085 u8 reserved_at_60[0x20]; 9086 9087 u8 multicast_gid[16][0x8]; 9088 }; 9089 9090 struct mlx5_ifc_arm_xrq_out_bits { 9091 u8 status[0x8]; 9092 u8 reserved_at_8[0x18]; 9093 9094 u8 syndrome[0x20]; 9095 9096 u8 reserved_at_40[0x40]; 9097 }; 9098 9099 struct mlx5_ifc_arm_xrq_in_bits { 9100 u8 opcode[0x10]; 9101 u8 reserved_at_10[0x10]; 9102 9103 u8 reserved_at_20[0x10]; 9104 u8 op_mod[0x10]; 9105 9106 u8 reserved_at_40[0x8]; 9107 u8 xrqn[0x18]; 9108 9109 u8 reserved_at_60[0x10]; 9110 u8 lwm[0x10]; 9111 }; 9112 9113 struct mlx5_ifc_arm_xrc_srq_out_bits { 9114 u8 status[0x8]; 9115 u8 reserved_at_8[0x18]; 9116 9117 u8 syndrome[0x20]; 9118 9119 u8 reserved_at_40[0x40]; 9120 }; 9121 9122 enum { 9123 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1, 9124 }; 9125 9126 struct mlx5_ifc_arm_xrc_srq_in_bits { 9127 u8 opcode[0x10]; 9128 u8 uid[0x10]; 9129 9130 u8 reserved_at_20[0x10]; 9131 u8 op_mod[0x10]; 9132 9133 u8 reserved_at_40[0x8]; 9134 u8 xrc_srqn[0x18]; 9135 9136 u8 reserved_at_60[0x10]; 9137 u8 lwm[0x10]; 9138 }; 9139 9140 struct mlx5_ifc_arm_rq_out_bits { 9141 u8 status[0x8]; 9142 u8 reserved_at_8[0x18]; 9143 9144 u8 syndrome[0x20]; 9145 9146 u8 reserved_at_40[0x40]; 9147 }; 9148 9149 enum { 9150 MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1, 9151 MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2, 9152 }; 9153 9154 struct mlx5_ifc_arm_rq_in_bits { 9155 u8 opcode[0x10]; 9156 u8 uid[0x10]; 9157 9158 u8 reserved_at_20[0x10]; 9159 u8 op_mod[0x10]; 9160 9161 u8 reserved_at_40[0x8]; 9162 u8 srq_number[0x18]; 9163 9164 u8 reserved_at_60[0x10]; 9165 u8 lwm[0x10]; 9166 }; 9167 9168 struct mlx5_ifc_arm_dct_out_bits { 9169 u8 status[0x8]; 9170 u8 reserved_at_8[0x18]; 9171 9172 u8 syndrome[0x20]; 9173 9174 u8 reserved_at_40[0x40]; 9175 }; 9176 9177 struct mlx5_ifc_arm_dct_in_bits { 9178 u8 opcode[0x10]; 9179 u8 reserved_at_10[0x10]; 9180 9181 u8 reserved_at_20[0x10]; 9182 u8 op_mod[0x10]; 9183 9184 u8 reserved_at_40[0x8]; 9185 u8 dct_number[0x18]; 9186 9187 u8 reserved_at_60[0x20]; 9188 }; 9189 9190 struct mlx5_ifc_alloc_xrcd_out_bits { 9191 u8 status[0x8]; 9192 u8 reserved_at_8[0x18]; 9193 9194 u8 syndrome[0x20]; 9195 9196 u8 reserved_at_40[0x8]; 9197 u8 xrcd[0x18]; 9198 9199 u8 reserved_at_60[0x20]; 9200 }; 9201 9202 struct mlx5_ifc_alloc_xrcd_in_bits { 9203 u8 opcode[0x10]; 9204 u8 uid[0x10]; 9205 9206 u8 reserved_at_20[0x10]; 9207 u8 op_mod[0x10]; 9208 9209 u8 reserved_at_40[0x40]; 9210 }; 9211 9212 struct mlx5_ifc_alloc_uar_out_bits { 9213 u8 status[0x8]; 9214 u8 reserved_at_8[0x18]; 9215 9216 u8 syndrome[0x20]; 9217 9218 u8 reserved_at_40[0x8]; 9219 u8 uar[0x18]; 9220 9221 u8 reserved_at_60[0x20]; 9222 }; 9223 9224 struct mlx5_ifc_alloc_uar_in_bits { 9225 u8 opcode[0x10]; 9226 u8 uid[0x10]; 9227 9228 u8 reserved_at_20[0x10]; 9229 u8 op_mod[0x10]; 9230 9231 u8 reserved_at_40[0x40]; 9232 }; 9233 9234 struct mlx5_ifc_alloc_transport_domain_out_bits { 9235 u8 status[0x8]; 9236 u8 reserved_at_8[0x18]; 9237 9238 u8 syndrome[0x20]; 9239 9240 u8 reserved_at_40[0x8]; 9241 u8 transport_domain[0x18]; 9242 9243 u8 reserved_at_60[0x20]; 9244 }; 9245 9246 struct mlx5_ifc_alloc_transport_domain_in_bits { 9247 u8 opcode[0x10]; 9248 u8 uid[0x10]; 9249 9250 u8 reserved_at_20[0x10]; 9251 u8 op_mod[0x10]; 9252 9253 u8 reserved_at_40[0x40]; 9254 }; 9255 9256 struct mlx5_ifc_alloc_q_counter_out_bits { 9257 u8 status[0x8]; 9258 u8 reserved_at_8[0x18]; 9259 9260 u8 syndrome[0x20]; 9261 9262 u8 reserved_at_40[0x18]; 9263 u8 counter_set_id[0x8]; 9264 9265 u8 reserved_at_60[0x20]; 9266 }; 9267 9268 struct mlx5_ifc_alloc_q_counter_in_bits { 9269 u8 opcode[0x10]; 9270 u8 uid[0x10]; 9271 9272 u8 reserved_at_20[0x10]; 9273 u8 op_mod[0x10]; 9274 9275 u8 reserved_at_40[0x40]; 9276 }; 9277 9278 struct mlx5_ifc_alloc_pd_out_bits { 9279 u8 status[0x8]; 9280 u8 reserved_at_8[0x18]; 9281 9282 u8 syndrome[0x20]; 9283 9284 u8 reserved_at_40[0x8]; 9285 u8 pd[0x18]; 9286 9287 u8 reserved_at_60[0x20]; 9288 }; 9289 9290 struct mlx5_ifc_alloc_pd_in_bits { 9291 u8 opcode[0x10]; 9292 u8 uid[0x10]; 9293 9294 u8 reserved_at_20[0x10]; 9295 u8 op_mod[0x10]; 9296 9297 u8 reserved_at_40[0x40]; 9298 }; 9299 9300 struct mlx5_ifc_alloc_flow_counter_out_bits { 9301 u8 status[0x8]; 9302 u8 reserved_at_8[0x18]; 9303 9304 u8 syndrome[0x20]; 9305 9306 u8 flow_counter_id[0x20]; 9307 9308 u8 reserved_at_60[0x20]; 9309 }; 9310 9311 struct mlx5_ifc_alloc_flow_counter_in_bits { 9312 u8 opcode[0x10]; 9313 u8 reserved_at_10[0x10]; 9314 9315 u8 reserved_at_20[0x10]; 9316 u8 op_mod[0x10]; 9317 9318 u8 reserved_at_40[0x38]; 9319 u8 flow_counter_bulk[0x8]; 9320 }; 9321 9322 struct mlx5_ifc_add_vxlan_udp_dport_out_bits { 9323 u8 status[0x8]; 9324 u8 reserved_at_8[0x18]; 9325 9326 u8 syndrome[0x20]; 9327 9328 u8 reserved_at_40[0x40]; 9329 }; 9330 9331 struct mlx5_ifc_add_vxlan_udp_dport_in_bits { 9332 u8 opcode[0x10]; 9333 u8 reserved_at_10[0x10]; 9334 9335 u8 reserved_at_20[0x10]; 9336 u8 op_mod[0x10]; 9337 9338 u8 reserved_at_40[0x20]; 9339 9340 u8 reserved_at_60[0x10]; 9341 u8 vxlan_udp_port[0x10]; 9342 }; 9343 9344 struct mlx5_ifc_set_pp_rate_limit_out_bits { 9345 u8 status[0x8]; 9346 u8 reserved_at_8[0x18]; 9347 9348 u8 syndrome[0x20]; 9349 9350 u8 reserved_at_40[0x40]; 9351 }; 9352 9353 struct mlx5_ifc_set_pp_rate_limit_context_bits { 9354 u8 rate_limit[0x20]; 9355 9356 u8 burst_upper_bound[0x20]; 9357 9358 u8 reserved_at_40[0x10]; 9359 u8 typical_packet_size[0x10]; 9360 9361 u8 reserved_at_60[0x120]; 9362 }; 9363 9364 struct mlx5_ifc_set_pp_rate_limit_in_bits { 9365 u8 opcode[0x10]; 9366 u8 uid[0x10]; 9367 9368 u8 reserved_at_20[0x10]; 9369 u8 op_mod[0x10]; 9370 9371 u8 reserved_at_40[0x10]; 9372 u8 rate_limit_index[0x10]; 9373 9374 u8 reserved_at_60[0x20]; 9375 9376 struct mlx5_ifc_set_pp_rate_limit_context_bits ctx; 9377 }; 9378 9379 struct mlx5_ifc_access_register_out_bits { 9380 u8 status[0x8]; 9381 u8 reserved_at_8[0x18]; 9382 9383 u8 syndrome[0x20]; 9384 9385 u8 reserved_at_40[0x40]; 9386 9387 u8 register_data[][0x20]; 9388 }; 9389 9390 enum { 9391 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0, 9392 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1, 9393 }; 9394 9395 struct mlx5_ifc_access_register_in_bits { 9396 u8 opcode[0x10]; 9397 u8 reserved_at_10[0x10]; 9398 9399 u8 reserved_at_20[0x10]; 9400 u8 op_mod[0x10]; 9401 9402 u8 reserved_at_40[0x10]; 9403 u8 register_id[0x10]; 9404 9405 u8 argument[0x20]; 9406 9407 u8 register_data[][0x20]; 9408 }; 9409 9410 struct mlx5_ifc_sltp_reg_bits { 9411 u8 status[0x4]; 9412 u8 version[0x4]; 9413 u8 local_port[0x8]; 9414 u8 pnat[0x2]; 9415 u8 reserved_at_12[0x2]; 9416 u8 lane[0x4]; 9417 u8 reserved_at_18[0x8]; 9418 9419 u8 reserved_at_20[0x20]; 9420 9421 u8 reserved_at_40[0x7]; 9422 u8 polarity[0x1]; 9423 u8 ob_tap0[0x8]; 9424 u8 ob_tap1[0x8]; 9425 u8 ob_tap2[0x8]; 9426 9427 u8 reserved_at_60[0xc]; 9428 u8 ob_preemp_mode[0x4]; 9429 u8 ob_reg[0x8]; 9430 u8 ob_bias[0x8]; 9431 9432 u8 reserved_at_80[0x20]; 9433 }; 9434 9435 struct mlx5_ifc_slrg_reg_bits { 9436 u8 status[0x4]; 9437 u8 version[0x4]; 9438 u8 local_port[0x8]; 9439 u8 pnat[0x2]; 9440 u8 reserved_at_12[0x2]; 9441 u8 lane[0x4]; 9442 u8 reserved_at_18[0x8]; 9443 9444 u8 time_to_link_up[0x10]; 9445 u8 reserved_at_30[0xc]; 9446 u8 grade_lane_speed[0x4]; 9447 9448 u8 grade_version[0x8]; 9449 u8 grade[0x18]; 9450 9451 u8 reserved_at_60[0x4]; 9452 u8 height_grade_type[0x4]; 9453 u8 height_grade[0x18]; 9454 9455 u8 height_dz[0x10]; 9456 u8 height_dv[0x10]; 9457 9458 u8 reserved_at_a0[0x10]; 9459 u8 height_sigma[0x10]; 9460 9461 u8 reserved_at_c0[0x20]; 9462 9463 u8 reserved_at_e0[0x4]; 9464 u8 phase_grade_type[0x4]; 9465 u8 phase_grade[0x18]; 9466 9467 u8 reserved_at_100[0x8]; 9468 u8 phase_eo_pos[0x8]; 9469 u8 reserved_at_110[0x8]; 9470 u8 phase_eo_neg[0x8]; 9471 9472 u8 ffe_set_tested[0x10]; 9473 u8 test_errors_per_lane[0x10]; 9474 }; 9475 9476 struct mlx5_ifc_pvlc_reg_bits { 9477 u8 reserved_at_0[0x8]; 9478 u8 local_port[0x8]; 9479 u8 reserved_at_10[0x10]; 9480 9481 u8 reserved_at_20[0x1c]; 9482 u8 vl_hw_cap[0x4]; 9483 9484 u8 reserved_at_40[0x1c]; 9485 u8 vl_admin[0x4]; 9486 9487 u8 reserved_at_60[0x1c]; 9488 u8 vl_operational[0x4]; 9489 }; 9490 9491 struct mlx5_ifc_pude_reg_bits { 9492 u8 swid[0x8]; 9493 u8 local_port[0x8]; 9494 u8 reserved_at_10[0x4]; 9495 u8 admin_status[0x4]; 9496 u8 reserved_at_18[0x4]; 9497 u8 oper_status[0x4]; 9498 9499 u8 reserved_at_20[0x60]; 9500 }; 9501 9502 struct mlx5_ifc_ptys_reg_bits { 9503 u8 reserved_at_0[0x1]; 9504 u8 an_disable_admin[0x1]; 9505 u8 an_disable_cap[0x1]; 9506 u8 reserved_at_3[0x5]; 9507 u8 local_port[0x8]; 9508 u8 reserved_at_10[0xd]; 9509 u8 proto_mask[0x3]; 9510 9511 u8 an_status[0x4]; 9512 u8 reserved_at_24[0xc]; 9513 u8 data_rate_oper[0x10]; 9514 9515 u8 ext_eth_proto_capability[0x20]; 9516 9517 u8 eth_proto_capability[0x20]; 9518 9519 u8 ib_link_width_capability[0x10]; 9520 u8 ib_proto_capability[0x10]; 9521 9522 u8 ext_eth_proto_admin[0x20]; 9523 9524 u8 eth_proto_admin[0x20]; 9525 9526 u8 ib_link_width_admin[0x10]; 9527 u8 ib_proto_admin[0x10]; 9528 9529 u8 ext_eth_proto_oper[0x20]; 9530 9531 u8 eth_proto_oper[0x20]; 9532 9533 u8 ib_link_width_oper[0x10]; 9534 u8 ib_proto_oper[0x10]; 9535 9536 u8 reserved_at_160[0x1c]; 9537 u8 connector_type[0x4]; 9538 9539 u8 eth_proto_lp_advertise[0x20]; 9540 9541 u8 reserved_at_1a0[0x60]; 9542 }; 9543 9544 struct mlx5_ifc_mlcr_reg_bits { 9545 u8 reserved_at_0[0x8]; 9546 u8 local_port[0x8]; 9547 u8 reserved_at_10[0x20]; 9548 9549 u8 beacon_duration[0x10]; 9550 u8 reserved_at_40[0x10]; 9551 9552 u8 beacon_remain[0x10]; 9553 }; 9554 9555 struct mlx5_ifc_ptas_reg_bits { 9556 u8 reserved_at_0[0x20]; 9557 9558 u8 algorithm_options[0x10]; 9559 u8 reserved_at_30[0x4]; 9560 u8 repetitions_mode[0x4]; 9561 u8 num_of_repetitions[0x8]; 9562 9563 u8 grade_version[0x8]; 9564 u8 height_grade_type[0x4]; 9565 u8 phase_grade_type[0x4]; 9566 u8 height_grade_weight[0x8]; 9567 u8 phase_grade_weight[0x8]; 9568 9569 u8 gisim_measure_bits[0x10]; 9570 u8 adaptive_tap_measure_bits[0x10]; 9571 9572 u8 ber_bath_high_error_threshold[0x10]; 9573 u8 ber_bath_mid_error_threshold[0x10]; 9574 9575 u8 ber_bath_low_error_threshold[0x10]; 9576 u8 one_ratio_high_threshold[0x10]; 9577 9578 u8 one_ratio_high_mid_threshold[0x10]; 9579 u8 one_ratio_low_mid_threshold[0x10]; 9580 9581 u8 one_ratio_low_threshold[0x10]; 9582 u8 ndeo_error_threshold[0x10]; 9583 9584 u8 mixer_offset_step_size[0x10]; 9585 u8 reserved_at_110[0x8]; 9586 u8 mix90_phase_for_voltage_bath[0x8]; 9587 9588 u8 mixer_offset_start[0x10]; 9589 u8 mixer_offset_end[0x10]; 9590 9591 u8 reserved_at_140[0x15]; 9592 u8 ber_test_time[0xb]; 9593 }; 9594 9595 struct mlx5_ifc_pspa_reg_bits { 9596 u8 swid[0x8]; 9597 u8 local_port[0x8]; 9598 u8 sub_port[0x8]; 9599 u8 reserved_at_18[0x8]; 9600 9601 u8 reserved_at_20[0x20]; 9602 }; 9603 9604 struct mlx5_ifc_pqdr_reg_bits { 9605 u8 reserved_at_0[0x8]; 9606 u8 local_port[0x8]; 9607 u8 reserved_at_10[0x5]; 9608 u8 prio[0x3]; 9609 u8 reserved_at_18[0x6]; 9610 u8 mode[0x2]; 9611 9612 u8 reserved_at_20[0x20]; 9613 9614 u8 reserved_at_40[0x10]; 9615 u8 min_threshold[0x10]; 9616 9617 u8 reserved_at_60[0x10]; 9618 u8 max_threshold[0x10]; 9619 9620 u8 reserved_at_80[0x10]; 9621 u8 mark_probability_denominator[0x10]; 9622 9623 u8 reserved_at_a0[0x60]; 9624 }; 9625 9626 struct mlx5_ifc_ppsc_reg_bits { 9627 u8 reserved_at_0[0x8]; 9628 u8 local_port[0x8]; 9629 u8 reserved_at_10[0x10]; 9630 9631 u8 reserved_at_20[0x60]; 9632 9633 u8 reserved_at_80[0x1c]; 9634 u8 wrps_admin[0x4]; 9635 9636 u8 reserved_at_a0[0x1c]; 9637 u8 wrps_status[0x4]; 9638 9639 u8 reserved_at_c0[0x8]; 9640 u8 up_threshold[0x8]; 9641 u8 reserved_at_d0[0x8]; 9642 u8 down_threshold[0x8]; 9643 9644 u8 reserved_at_e0[0x20]; 9645 9646 u8 reserved_at_100[0x1c]; 9647 u8 srps_admin[0x4]; 9648 9649 u8 reserved_at_120[0x1c]; 9650 u8 srps_status[0x4]; 9651 9652 u8 reserved_at_140[0x40]; 9653 }; 9654 9655 struct mlx5_ifc_pplr_reg_bits { 9656 u8 reserved_at_0[0x8]; 9657 u8 local_port[0x8]; 9658 u8 reserved_at_10[0x10]; 9659 9660 u8 reserved_at_20[0x8]; 9661 u8 lb_cap[0x8]; 9662 u8 reserved_at_30[0x8]; 9663 u8 lb_en[0x8]; 9664 }; 9665 9666 struct mlx5_ifc_pplm_reg_bits { 9667 u8 reserved_at_0[0x8]; 9668 u8 local_port[0x8]; 9669 u8 reserved_at_10[0x10]; 9670 9671 u8 reserved_at_20[0x20]; 9672 9673 u8 port_profile_mode[0x8]; 9674 u8 static_port_profile[0x8]; 9675 u8 active_port_profile[0x8]; 9676 u8 reserved_at_58[0x8]; 9677 9678 u8 retransmission_active[0x8]; 9679 u8 fec_mode_active[0x18]; 9680 9681 u8 rs_fec_correction_bypass_cap[0x4]; 9682 u8 reserved_at_84[0x8]; 9683 u8 fec_override_cap_56g[0x4]; 9684 u8 fec_override_cap_100g[0x4]; 9685 u8 fec_override_cap_50g[0x4]; 9686 u8 fec_override_cap_25g[0x4]; 9687 u8 fec_override_cap_10g_40g[0x4]; 9688 9689 u8 rs_fec_correction_bypass_admin[0x4]; 9690 u8 reserved_at_a4[0x8]; 9691 u8 fec_override_admin_56g[0x4]; 9692 u8 fec_override_admin_100g[0x4]; 9693 u8 fec_override_admin_50g[0x4]; 9694 u8 fec_override_admin_25g[0x4]; 9695 u8 fec_override_admin_10g_40g[0x4]; 9696 9697 u8 fec_override_cap_400g_8x[0x10]; 9698 u8 fec_override_cap_200g_4x[0x10]; 9699 9700 u8 fec_override_cap_100g_2x[0x10]; 9701 u8 fec_override_cap_50g_1x[0x10]; 9702 9703 u8 fec_override_admin_400g_8x[0x10]; 9704 u8 fec_override_admin_200g_4x[0x10]; 9705 9706 u8 fec_override_admin_100g_2x[0x10]; 9707 u8 fec_override_admin_50g_1x[0x10]; 9708 9709 u8 reserved_at_140[0x140]; 9710 }; 9711 9712 struct mlx5_ifc_ppcnt_reg_bits { 9713 u8 swid[0x8]; 9714 u8 local_port[0x8]; 9715 u8 pnat[0x2]; 9716 u8 reserved_at_12[0x8]; 9717 u8 grp[0x6]; 9718 9719 u8 clr[0x1]; 9720 u8 reserved_at_21[0x1c]; 9721 u8 prio_tc[0x3]; 9722 9723 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set; 9724 }; 9725 9726 struct mlx5_ifc_mpein_reg_bits { 9727 u8 reserved_at_0[0x2]; 9728 u8 depth[0x6]; 9729 u8 pcie_index[0x8]; 9730 u8 node[0x8]; 9731 u8 reserved_at_18[0x8]; 9732 9733 u8 capability_mask[0x20]; 9734 9735 u8 reserved_at_40[0x8]; 9736 u8 link_width_enabled[0x8]; 9737 u8 link_speed_enabled[0x10]; 9738 9739 u8 lane0_physical_position[0x8]; 9740 u8 link_width_active[0x8]; 9741 u8 link_speed_active[0x10]; 9742 9743 u8 num_of_pfs[0x10]; 9744 u8 num_of_vfs[0x10]; 9745 9746 u8 bdf0[0x10]; 9747 u8 reserved_at_b0[0x10]; 9748 9749 u8 max_read_request_size[0x4]; 9750 u8 max_payload_size[0x4]; 9751 u8 reserved_at_c8[0x5]; 9752 u8 pwr_status[0x3]; 9753 u8 port_type[0x4]; 9754 u8 reserved_at_d4[0xb]; 9755 u8 lane_reversal[0x1]; 9756 9757 u8 reserved_at_e0[0x14]; 9758 u8 pci_power[0xc]; 9759 9760 u8 reserved_at_100[0x20]; 9761 9762 u8 device_status[0x10]; 9763 u8 port_state[0x8]; 9764 u8 reserved_at_138[0x8]; 9765 9766 u8 reserved_at_140[0x10]; 9767 u8 receiver_detect_result[0x10]; 9768 9769 u8 reserved_at_160[0x20]; 9770 }; 9771 9772 struct mlx5_ifc_mpcnt_reg_bits { 9773 u8 reserved_at_0[0x8]; 9774 u8 pcie_index[0x8]; 9775 u8 reserved_at_10[0xa]; 9776 u8 grp[0x6]; 9777 9778 u8 clr[0x1]; 9779 u8 reserved_at_21[0x1f]; 9780 9781 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set; 9782 }; 9783 9784 struct mlx5_ifc_ppad_reg_bits { 9785 u8 reserved_at_0[0x3]; 9786 u8 single_mac[0x1]; 9787 u8 reserved_at_4[0x4]; 9788 u8 local_port[0x8]; 9789 u8 mac_47_32[0x10]; 9790 9791 u8 mac_31_0[0x20]; 9792 9793 u8 reserved_at_40[0x40]; 9794 }; 9795 9796 struct mlx5_ifc_pmtu_reg_bits { 9797 u8 reserved_at_0[0x8]; 9798 u8 local_port[0x8]; 9799 u8 reserved_at_10[0x10]; 9800 9801 u8 max_mtu[0x10]; 9802 u8 reserved_at_30[0x10]; 9803 9804 u8 admin_mtu[0x10]; 9805 u8 reserved_at_50[0x10]; 9806 9807 u8 oper_mtu[0x10]; 9808 u8 reserved_at_70[0x10]; 9809 }; 9810 9811 struct mlx5_ifc_pmpr_reg_bits { 9812 u8 reserved_at_0[0x8]; 9813 u8 module[0x8]; 9814 u8 reserved_at_10[0x10]; 9815 9816 u8 reserved_at_20[0x18]; 9817 u8 attenuation_5g[0x8]; 9818 9819 u8 reserved_at_40[0x18]; 9820 u8 attenuation_7g[0x8]; 9821 9822 u8 reserved_at_60[0x18]; 9823 u8 attenuation_12g[0x8]; 9824 }; 9825 9826 struct mlx5_ifc_pmpe_reg_bits { 9827 u8 reserved_at_0[0x8]; 9828 u8 module[0x8]; 9829 u8 reserved_at_10[0xc]; 9830 u8 module_status[0x4]; 9831 9832 u8 reserved_at_20[0x60]; 9833 }; 9834 9835 struct mlx5_ifc_pmpc_reg_bits { 9836 u8 module_state_updated[32][0x8]; 9837 }; 9838 9839 struct mlx5_ifc_pmlpn_reg_bits { 9840 u8 reserved_at_0[0x4]; 9841 u8 mlpn_status[0x4]; 9842 u8 local_port[0x8]; 9843 u8 reserved_at_10[0x10]; 9844 9845 u8 e[0x1]; 9846 u8 reserved_at_21[0x1f]; 9847 }; 9848 9849 struct mlx5_ifc_pmlp_reg_bits { 9850 u8 rxtx[0x1]; 9851 u8 reserved_at_1[0x7]; 9852 u8 local_port[0x8]; 9853 u8 reserved_at_10[0x8]; 9854 u8 width[0x8]; 9855 9856 u8 lane0_module_mapping[0x20]; 9857 9858 u8 lane1_module_mapping[0x20]; 9859 9860 u8 lane2_module_mapping[0x20]; 9861 9862 u8 lane3_module_mapping[0x20]; 9863 9864 u8 reserved_at_a0[0x160]; 9865 }; 9866 9867 struct mlx5_ifc_pmaos_reg_bits { 9868 u8 reserved_at_0[0x8]; 9869 u8 module[0x8]; 9870 u8 reserved_at_10[0x4]; 9871 u8 admin_status[0x4]; 9872 u8 reserved_at_18[0x4]; 9873 u8 oper_status[0x4]; 9874 9875 u8 ase[0x1]; 9876 u8 ee[0x1]; 9877 u8 reserved_at_22[0x1c]; 9878 u8 e[0x2]; 9879 9880 u8 reserved_at_40[0x40]; 9881 }; 9882 9883 struct mlx5_ifc_plpc_reg_bits { 9884 u8 reserved_at_0[0x4]; 9885 u8 profile_id[0xc]; 9886 u8 reserved_at_10[0x4]; 9887 u8 proto_mask[0x4]; 9888 u8 reserved_at_18[0x8]; 9889 9890 u8 reserved_at_20[0x10]; 9891 u8 lane_speed[0x10]; 9892 9893 u8 reserved_at_40[0x17]; 9894 u8 lpbf[0x1]; 9895 u8 fec_mode_policy[0x8]; 9896 9897 u8 retransmission_capability[0x8]; 9898 u8 fec_mode_capability[0x18]; 9899 9900 u8 retransmission_support_admin[0x8]; 9901 u8 fec_mode_support_admin[0x18]; 9902 9903 u8 retransmission_request_admin[0x8]; 9904 u8 fec_mode_request_admin[0x18]; 9905 9906 u8 reserved_at_c0[0x80]; 9907 }; 9908 9909 struct mlx5_ifc_plib_reg_bits { 9910 u8 reserved_at_0[0x8]; 9911 u8 local_port[0x8]; 9912 u8 reserved_at_10[0x8]; 9913 u8 ib_port[0x8]; 9914 9915 u8 reserved_at_20[0x60]; 9916 }; 9917 9918 struct mlx5_ifc_plbf_reg_bits { 9919 u8 reserved_at_0[0x8]; 9920 u8 local_port[0x8]; 9921 u8 reserved_at_10[0xd]; 9922 u8 lbf_mode[0x3]; 9923 9924 u8 reserved_at_20[0x20]; 9925 }; 9926 9927 struct mlx5_ifc_pipg_reg_bits { 9928 u8 reserved_at_0[0x8]; 9929 u8 local_port[0x8]; 9930 u8 reserved_at_10[0x10]; 9931 9932 u8 dic[0x1]; 9933 u8 reserved_at_21[0x19]; 9934 u8 ipg[0x4]; 9935 u8 reserved_at_3e[0x2]; 9936 }; 9937 9938 struct mlx5_ifc_pifr_reg_bits { 9939 u8 reserved_at_0[0x8]; 9940 u8 local_port[0x8]; 9941 u8 reserved_at_10[0x10]; 9942 9943 u8 reserved_at_20[0xe0]; 9944 9945 u8 port_filter[8][0x20]; 9946 9947 u8 port_filter_update_en[8][0x20]; 9948 }; 9949 9950 struct mlx5_ifc_pfcc_reg_bits { 9951 u8 reserved_at_0[0x8]; 9952 u8 local_port[0x8]; 9953 u8 reserved_at_10[0xb]; 9954 u8 ppan_mask_n[0x1]; 9955 u8 minor_stall_mask[0x1]; 9956 u8 critical_stall_mask[0x1]; 9957 u8 reserved_at_1e[0x2]; 9958 9959 u8 ppan[0x4]; 9960 u8 reserved_at_24[0x4]; 9961 u8 prio_mask_tx[0x8]; 9962 u8 reserved_at_30[0x8]; 9963 u8 prio_mask_rx[0x8]; 9964 9965 u8 pptx[0x1]; 9966 u8 aptx[0x1]; 9967 u8 pptx_mask_n[0x1]; 9968 u8 reserved_at_43[0x5]; 9969 u8 pfctx[0x8]; 9970 u8 reserved_at_50[0x10]; 9971 9972 u8 pprx[0x1]; 9973 u8 aprx[0x1]; 9974 u8 pprx_mask_n[0x1]; 9975 u8 reserved_at_63[0x5]; 9976 u8 pfcrx[0x8]; 9977 u8 reserved_at_70[0x10]; 9978 9979 u8 device_stall_minor_watermark[0x10]; 9980 u8 device_stall_critical_watermark[0x10]; 9981 9982 u8 reserved_at_a0[0x60]; 9983 }; 9984 9985 struct mlx5_ifc_pelc_reg_bits { 9986 u8 op[0x4]; 9987 u8 reserved_at_4[0x4]; 9988 u8 local_port[0x8]; 9989 u8 reserved_at_10[0x10]; 9990 9991 u8 op_admin[0x8]; 9992 u8 op_capability[0x8]; 9993 u8 op_request[0x8]; 9994 u8 op_active[0x8]; 9995 9996 u8 admin[0x40]; 9997 9998 u8 capability[0x40]; 9999 10000 u8 request[0x40]; 10001 10002 u8 active[0x40]; 10003 10004 u8 reserved_at_140[0x80]; 10005 }; 10006 10007 struct mlx5_ifc_peir_reg_bits { 10008 u8 reserved_at_0[0x8]; 10009 u8 local_port[0x8]; 10010 u8 reserved_at_10[0x10]; 10011 10012 u8 reserved_at_20[0xc]; 10013 u8 error_count[0x4]; 10014 u8 reserved_at_30[0x10]; 10015 10016 u8 reserved_at_40[0xc]; 10017 u8 lane[0x4]; 10018 u8 reserved_at_50[0x8]; 10019 u8 error_type[0x8]; 10020 }; 10021 10022 struct mlx5_ifc_mpegc_reg_bits { 10023 u8 reserved_at_0[0x30]; 10024 u8 field_select[0x10]; 10025 10026 u8 tx_overflow_sense[0x1]; 10027 u8 mark_cqe[0x1]; 10028 u8 mark_cnp[0x1]; 10029 u8 reserved_at_43[0x1b]; 10030 u8 tx_lossy_overflow_oper[0x2]; 10031 10032 u8 reserved_at_60[0x100]; 10033 }; 10034 10035 enum { 10036 MLX5_MTUTC_FREQ_ADJ_UNITS_PPB = 0x0, 10037 MLX5_MTUTC_FREQ_ADJ_UNITS_SCALED_PPM = 0x1, 10038 }; 10039 10040 enum { 10041 MLX5_MTUTC_OPERATION_SET_TIME_IMMEDIATE = 0x1, 10042 MLX5_MTUTC_OPERATION_ADJUST_TIME = 0x2, 10043 MLX5_MTUTC_OPERATION_ADJUST_FREQ_UTC = 0x3, 10044 }; 10045 10046 struct mlx5_ifc_mtutc_reg_bits { 10047 u8 reserved_at_0[0x5]; 10048 u8 freq_adj_units[0x3]; 10049 u8 reserved_at_8[0x14]; 10050 u8 operation[0x4]; 10051 10052 u8 freq_adjustment[0x20]; 10053 10054 u8 reserved_at_40[0x40]; 10055 10056 u8 utc_sec[0x20]; 10057 10058 u8 reserved_at_a0[0x2]; 10059 u8 utc_nsec[0x1e]; 10060 10061 u8 time_adjustment[0x20]; 10062 }; 10063 10064 struct mlx5_ifc_pcam_enhanced_features_bits { 10065 u8 reserved_at_0[0x68]; 10066 u8 fec_50G_per_lane_in_pplm[0x1]; 10067 u8 reserved_at_69[0x4]; 10068 u8 rx_icrc_encapsulated_counter[0x1]; 10069 u8 reserved_at_6e[0x4]; 10070 u8 ptys_extended_ethernet[0x1]; 10071 u8 reserved_at_73[0x3]; 10072 u8 pfcc_mask[0x1]; 10073 u8 reserved_at_77[0x3]; 10074 u8 per_lane_error_counters[0x1]; 10075 u8 rx_buffer_fullness_counters[0x1]; 10076 u8 ptys_connector_type[0x1]; 10077 u8 reserved_at_7d[0x1]; 10078 u8 ppcnt_discard_group[0x1]; 10079 u8 ppcnt_statistical_group[0x1]; 10080 }; 10081 10082 struct mlx5_ifc_pcam_regs_5000_to_507f_bits { 10083 u8 port_access_reg_cap_mask_127_to_96[0x20]; 10084 u8 port_access_reg_cap_mask_95_to_64[0x20]; 10085 10086 u8 port_access_reg_cap_mask_63_to_36[0x1c]; 10087 u8 pplm[0x1]; 10088 u8 port_access_reg_cap_mask_34_to_32[0x3]; 10089 10090 u8 port_access_reg_cap_mask_31_to_13[0x13]; 10091 u8 pbmc[0x1]; 10092 u8 pptb[0x1]; 10093 u8 port_access_reg_cap_mask_10_to_09[0x2]; 10094 u8 ppcnt[0x1]; 10095 u8 port_access_reg_cap_mask_07_to_00[0x8]; 10096 }; 10097 10098 struct mlx5_ifc_pcam_reg_bits { 10099 u8 reserved_at_0[0x8]; 10100 u8 feature_group[0x8]; 10101 u8 reserved_at_10[0x8]; 10102 u8 access_reg_group[0x8]; 10103 10104 u8 reserved_at_20[0x20]; 10105 10106 union { 10107 struct mlx5_ifc_pcam_regs_5000_to_507f_bits regs_5000_to_507f; 10108 u8 reserved_at_0[0x80]; 10109 } port_access_reg_cap_mask; 10110 10111 u8 reserved_at_c0[0x80]; 10112 10113 union { 10114 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features; 10115 u8 reserved_at_0[0x80]; 10116 } feature_cap_mask; 10117 10118 u8 reserved_at_1c0[0xc0]; 10119 }; 10120 10121 struct mlx5_ifc_mcam_enhanced_features_bits { 10122 u8 reserved_at_0[0x50]; 10123 u8 mtutc_freq_adj_units[0x1]; 10124 u8 mtutc_time_adjustment_extended_range[0x1]; 10125 u8 reserved_at_52[0xb]; 10126 u8 mcia_32dwords[0x1]; 10127 u8 out_pulse_duration_ns[0x1]; 10128 u8 npps_period[0x1]; 10129 u8 reserved_at_60[0xa]; 10130 u8 reset_state[0x1]; 10131 u8 ptpcyc2realtime_modify[0x1]; 10132 u8 reserved_at_6c[0x2]; 10133 u8 pci_status_and_power[0x1]; 10134 u8 reserved_at_6f[0x5]; 10135 u8 mark_tx_action_cnp[0x1]; 10136 u8 mark_tx_action_cqe[0x1]; 10137 u8 dynamic_tx_overflow[0x1]; 10138 u8 reserved_at_77[0x4]; 10139 u8 pcie_outbound_stalled[0x1]; 10140 u8 tx_overflow_buffer_pkt[0x1]; 10141 u8 mtpps_enh_out_per_adj[0x1]; 10142 u8 mtpps_fs[0x1]; 10143 u8 pcie_performance_group[0x1]; 10144 }; 10145 10146 struct mlx5_ifc_mcam_access_reg_bits { 10147 u8 reserved_at_0[0x1c]; 10148 u8 mcda[0x1]; 10149 u8 mcc[0x1]; 10150 u8 mcqi[0x1]; 10151 u8 mcqs[0x1]; 10152 10153 u8 regs_95_to_87[0x9]; 10154 u8 mpegc[0x1]; 10155 u8 mtutc[0x1]; 10156 u8 regs_84_to_68[0x11]; 10157 u8 tracer_registers[0x4]; 10158 10159 u8 regs_63_to_46[0x12]; 10160 u8 mrtc[0x1]; 10161 u8 regs_44_to_32[0xd]; 10162 10163 u8 regs_31_to_0[0x20]; 10164 }; 10165 10166 struct mlx5_ifc_mcam_access_reg_bits1 { 10167 u8 regs_127_to_96[0x20]; 10168 10169 u8 regs_95_to_64[0x20]; 10170 10171 u8 regs_63_to_32[0x20]; 10172 10173 u8 regs_31_to_0[0x20]; 10174 }; 10175 10176 struct mlx5_ifc_mcam_access_reg_bits2 { 10177 u8 regs_127_to_99[0x1d]; 10178 u8 mirc[0x1]; 10179 u8 regs_97_to_96[0x2]; 10180 10181 u8 regs_95_to_64[0x20]; 10182 10183 u8 regs_63_to_32[0x20]; 10184 10185 u8 regs_31_to_0[0x20]; 10186 }; 10187 10188 struct mlx5_ifc_mcam_reg_bits { 10189 u8 reserved_at_0[0x8]; 10190 u8 feature_group[0x8]; 10191 u8 reserved_at_10[0x8]; 10192 u8 access_reg_group[0x8]; 10193 10194 u8 reserved_at_20[0x20]; 10195 10196 union { 10197 struct mlx5_ifc_mcam_access_reg_bits access_regs; 10198 struct mlx5_ifc_mcam_access_reg_bits1 access_regs1; 10199 struct mlx5_ifc_mcam_access_reg_bits2 access_regs2; 10200 u8 reserved_at_0[0x80]; 10201 } mng_access_reg_cap_mask; 10202 10203 u8 reserved_at_c0[0x80]; 10204 10205 union { 10206 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features; 10207 u8 reserved_at_0[0x80]; 10208 } mng_feature_cap_mask; 10209 10210 u8 reserved_at_1c0[0x80]; 10211 }; 10212 10213 struct mlx5_ifc_qcam_access_reg_cap_mask { 10214 u8 qcam_access_reg_cap_mask_127_to_20[0x6C]; 10215 u8 qpdpm[0x1]; 10216 u8 qcam_access_reg_cap_mask_18_to_4[0x0F]; 10217 u8 qdpm[0x1]; 10218 u8 qpts[0x1]; 10219 u8 qcap[0x1]; 10220 u8 qcam_access_reg_cap_mask_0[0x1]; 10221 }; 10222 10223 struct mlx5_ifc_qcam_qos_feature_cap_mask { 10224 u8 qcam_qos_feature_cap_mask_127_to_1[0x7F]; 10225 u8 qpts_trust_both[0x1]; 10226 }; 10227 10228 struct mlx5_ifc_qcam_reg_bits { 10229 u8 reserved_at_0[0x8]; 10230 u8 feature_group[0x8]; 10231 u8 reserved_at_10[0x8]; 10232 u8 access_reg_group[0x8]; 10233 u8 reserved_at_20[0x20]; 10234 10235 union { 10236 struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap; 10237 u8 reserved_at_0[0x80]; 10238 } qos_access_reg_cap_mask; 10239 10240 u8 reserved_at_c0[0x80]; 10241 10242 union { 10243 struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap; 10244 u8 reserved_at_0[0x80]; 10245 } qos_feature_cap_mask; 10246 10247 u8 reserved_at_1c0[0x80]; 10248 }; 10249 10250 struct mlx5_ifc_core_dump_reg_bits { 10251 u8 reserved_at_0[0x18]; 10252 u8 core_dump_type[0x8]; 10253 10254 u8 reserved_at_20[0x30]; 10255 u8 vhca_id[0x10]; 10256 10257 u8 reserved_at_60[0x8]; 10258 u8 qpn[0x18]; 10259 u8 reserved_at_80[0x180]; 10260 }; 10261 10262 struct mlx5_ifc_pcap_reg_bits { 10263 u8 reserved_at_0[0x8]; 10264 u8 local_port[0x8]; 10265 u8 reserved_at_10[0x10]; 10266 10267 u8 port_capability_mask[4][0x20]; 10268 }; 10269 10270 struct mlx5_ifc_paos_reg_bits { 10271 u8 swid[0x8]; 10272 u8 local_port[0x8]; 10273 u8 reserved_at_10[0x4]; 10274 u8 admin_status[0x4]; 10275 u8 reserved_at_18[0x4]; 10276 u8 oper_status[0x4]; 10277 10278 u8 ase[0x1]; 10279 u8 ee[0x1]; 10280 u8 reserved_at_22[0x1c]; 10281 u8 e[0x2]; 10282 10283 u8 reserved_at_40[0x40]; 10284 }; 10285 10286 struct mlx5_ifc_pamp_reg_bits { 10287 u8 reserved_at_0[0x8]; 10288 u8 opamp_group[0x8]; 10289 u8 reserved_at_10[0xc]; 10290 u8 opamp_group_type[0x4]; 10291 10292 u8 start_index[0x10]; 10293 u8 reserved_at_30[0x4]; 10294 u8 num_of_indices[0xc]; 10295 10296 u8 index_data[18][0x10]; 10297 }; 10298 10299 struct mlx5_ifc_pcmr_reg_bits { 10300 u8 reserved_at_0[0x8]; 10301 u8 local_port[0x8]; 10302 u8 reserved_at_10[0x10]; 10303 10304 u8 entropy_force_cap[0x1]; 10305 u8 entropy_calc_cap[0x1]; 10306 u8 entropy_gre_calc_cap[0x1]; 10307 u8 reserved_at_23[0xf]; 10308 u8 rx_ts_over_crc_cap[0x1]; 10309 u8 reserved_at_33[0xb]; 10310 u8 fcs_cap[0x1]; 10311 u8 reserved_at_3f[0x1]; 10312 10313 u8 entropy_force[0x1]; 10314 u8 entropy_calc[0x1]; 10315 u8 entropy_gre_calc[0x1]; 10316 u8 reserved_at_43[0xf]; 10317 u8 rx_ts_over_crc[0x1]; 10318 u8 reserved_at_53[0xb]; 10319 u8 fcs_chk[0x1]; 10320 u8 reserved_at_5f[0x1]; 10321 }; 10322 10323 struct mlx5_ifc_lane_2_module_mapping_bits { 10324 u8 reserved_at_0[0x4]; 10325 u8 rx_lane[0x4]; 10326 u8 reserved_at_8[0x4]; 10327 u8 tx_lane[0x4]; 10328 u8 reserved_at_10[0x8]; 10329 u8 module[0x8]; 10330 }; 10331 10332 struct mlx5_ifc_bufferx_reg_bits { 10333 u8 reserved_at_0[0x6]; 10334 u8 lossy[0x1]; 10335 u8 epsb[0x1]; 10336 u8 reserved_at_8[0x8]; 10337 u8 size[0x10]; 10338 10339 u8 xoff_threshold[0x10]; 10340 u8 xon_threshold[0x10]; 10341 }; 10342 10343 struct mlx5_ifc_set_node_in_bits { 10344 u8 node_description[64][0x8]; 10345 }; 10346 10347 struct mlx5_ifc_register_power_settings_bits { 10348 u8 reserved_at_0[0x18]; 10349 u8 power_settings_level[0x8]; 10350 10351 u8 reserved_at_20[0x60]; 10352 }; 10353 10354 struct mlx5_ifc_register_host_endianness_bits { 10355 u8 he[0x1]; 10356 u8 reserved_at_1[0x1f]; 10357 10358 u8 reserved_at_20[0x60]; 10359 }; 10360 10361 struct mlx5_ifc_umr_pointer_desc_argument_bits { 10362 u8 reserved_at_0[0x20]; 10363 10364 u8 mkey[0x20]; 10365 10366 u8 addressh_63_32[0x20]; 10367 10368 u8 addressl_31_0[0x20]; 10369 }; 10370 10371 struct mlx5_ifc_ud_adrs_vector_bits { 10372 u8 dc_key[0x40]; 10373 10374 u8 ext[0x1]; 10375 u8 reserved_at_41[0x7]; 10376 u8 destination_qp_dct[0x18]; 10377 10378 u8 static_rate[0x4]; 10379 u8 sl_eth_prio[0x4]; 10380 u8 fl[0x1]; 10381 u8 mlid[0x7]; 10382 u8 rlid_udp_sport[0x10]; 10383 10384 u8 reserved_at_80[0x20]; 10385 10386 u8 rmac_47_16[0x20]; 10387 10388 u8 rmac_15_0[0x10]; 10389 u8 tclass[0x8]; 10390 u8 hop_limit[0x8]; 10391 10392 u8 reserved_at_e0[0x1]; 10393 u8 grh[0x1]; 10394 u8 reserved_at_e2[0x2]; 10395 u8 src_addr_index[0x8]; 10396 u8 flow_label[0x14]; 10397 10398 u8 rgid_rip[16][0x8]; 10399 }; 10400 10401 struct mlx5_ifc_pages_req_event_bits { 10402 u8 reserved_at_0[0x10]; 10403 u8 function_id[0x10]; 10404 10405 u8 num_pages[0x20]; 10406 10407 u8 reserved_at_40[0xa0]; 10408 }; 10409 10410 struct mlx5_ifc_eqe_bits { 10411 u8 reserved_at_0[0x8]; 10412 u8 event_type[0x8]; 10413 u8 reserved_at_10[0x8]; 10414 u8 event_sub_type[0x8]; 10415 10416 u8 reserved_at_20[0xe0]; 10417 10418 union mlx5_ifc_event_auto_bits event_data; 10419 10420 u8 reserved_at_1e0[0x10]; 10421 u8 signature[0x8]; 10422 u8 reserved_at_1f8[0x7]; 10423 u8 owner[0x1]; 10424 }; 10425 10426 enum { 10427 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7, 10428 }; 10429 10430 struct mlx5_ifc_cmd_queue_entry_bits { 10431 u8 type[0x8]; 10432 u8 reserved_at_8[0x18]; 10433 10434 u8 input_length[0x20]; 10435 10436 u8 input_mailbox_pointer_63_32[0x20]; 10437 10438 u8 input_mailbox_pointer_31_9[0x17]; 10439 u8 reserved_at_77[0x9]; 10440 10441 u8 command_input_inline_data[16][0x8]; 10442 10443 u8 command_output_inline_data[16][0x8]; 10444 10445 u8 output_mailbox_pointer_63_32[0x20]; 10446 10447 u8 output_mailbox_pointer_31_9[0x17]; 10448 u8 reserved_at_1b7[0x9]; 10449 10450 u8 output_length[0x20]; 10451 10452 u8 token[0x8]; 10453 u8 signature[0x8]; 10454 u8 reserved_at_1f0[0x8]; 10455 u8 status[0x7]; 10456 u8 ownership[0x1]; 10457 }; 10458 10459 struct mlx5_ifc_cmd_out_bits { 10460 u8 status[0x8]; 10461 u8 reserved_at_8[0x18]; 10462 10463 u8 syndrome[0x20]; 10464 10465 u8 command_output[0x20]; 10466 }; 10467 10468 struct mlx5_ifc_cmd_in_bits { 10469 u8 opcode[0x10]; 10470 u8 reserved_at_10[0x10]; 10471 10472 u8 reserved_at_20[0x10]; 10473 u8 op_mod[0x10]; 10474 10475 u8 command[][0x20]; 10476 }; 10477 10478 struct mlx5_ifc_cmd_if_box_bits { 10479 u8 mailbox_data[512][0x8]; 10480 10481 u8 reserved_at_1000[0x180]; 10482 10483 u8 next_pointer_63_32[0x20]; 10484 10485 u8 next_pointer_31_10[0x16]; 10486 u8 reserved_at_11b6[0xa]; 10487 10488 u8 block_number[0x20]; 10489 10490 u8 reserved_at_11e0[0x8]; 10491 u8 token[0x8]; 10492 u8 ctrl_signature[0x8]; 10493 u8 signature[0x8]; 10494 }; 10495 10496 struct mlx5_ifc_mtt_bits { 10497 u8 ptag_63_32[0x20]; 10498 10499 u8 ptag_31_8[0x18]; 10500 u8 reserved_at_38[0x6]; 10501 u8 wr_en[0x1]; 10502 u8 rd_en[0x1]; 10503 }; 10504 10505 struct mlx5_ifc_query_wol_rol_out_bits { 10506 u8 status[0x8]; 10507 u8 reserved_at_8[0x18]; 10508 10509 u8 syndrome[0x20]; 10510 10511 u8 reserved_at_40[0x10]; 10512 u8 rol_mode[0x8]; 10513 u8 wol_mode[0x8]; 10514 10515 u8 reserved_at_60[0x20]; 10516 }; 10517 10518 struct mlx5_ifc_query_wol_rol_in_bits { 10519 u8 opcode[0x10]; 10520 u8 reserved_at_10[0x10]; 10521 10522 u8 reserved_at_20[0x10]; 10523 u8 op_mod[0x10]; 10524 10525 u8 reserved_at_40[0x40]; 10526 }; 10527 10528 struct mlx5_ifc_set_wol_rol_out_bits { 10529 u8 status[0x8]; 10530 u8 reserved_at_8[0x18]; 10531 10532 u8 syndrome[0x20]; 10533 10534 u8 reserved_at_40[0x40]; 10535 }; 10536 10537 struct mlx5_ifc_set_wol_rol_in_bits { 10538 u8 opcode[0x10]; 10539 u8 reserved_at_10[0x10]; 10540 10541 u8 reserved_at_20[0x10]; 10542 u8 op_mod[0x10]; 10543 10544 u8 rol_mode_valid[0x1]; 10545 u8 wol_mode_valid[0x1]; 10546 u8 reserved_at_42[0xe]; 10547 u8 rol_mode[0x8]; 10548 u8 wol_mode[0x8]; 10549 10550 u8 reserved_at_60[0x20]; 10551 }; 10552 10553 enum { 10554 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0, 10555 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1, 10556 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2, 10557 }; 10558 10559 enum { 10560 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0, 10561 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1, 10562 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2, 10563 }; 10564 10565 enum { 10566 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR = 0x1, 10567 MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC = 0x7, 10568 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR = 0x8, 10569 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR = 0x9, 10570 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR = 0xa, 10571 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR = 0xb, 10572 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN = 0xc, 10573 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR = 0xd, 10574 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV = 0xe, 10575 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR = 0xf, 10576 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR = 0x10, 10577 }; 10578 10579 struct mlx5_ifc_initial_seg_bits { 10580 u8 fw_rev_minor[0x10]; 10581 u8 fw_rev_major[0x10]; 10582 10583 u8 cmd_interface_rev[0x10]; 10584 u8 fw_rev_subminor[0x10]; 10585 10586 u8 reserved_at_40[0x40]; 10587 10588 u8 cmdq_phy_addr_63_32[0x20]; 10589 10590 u8 cmdq_phy_addr_31_12[0x14]; 10591 u8 reserved_at_b4[0x2]; 10592 u8 nic_interface[0x2]; 10593 u8 log_cmdq_size[0x4]; 10594 u8 log_cmdq_stride[0x4]; 10595 10596 u8 command_doorbell_vector[0x20]; 10597 10598 u8 reserved_at_e0[0xf00]; 10599 10600 u8 initializing[0x1]; 10601 u8 reserved_at_fe1[0x4]; 10602 u8 nic_interface_supported[0x3]; 10603 u8 embedded_cpu[0x1]; 10604 u8 reserved_at_fe9[0x17]; 10605 10606 struct mlx5_ifc_health_buffer_bits health_buffer; 10607 10608 u8 no_dram_nic_offset[0x20]; 10609 10610 u8 reserved_at_1220[0x6e40]; 10611 10612 u8 reserved_at_8060[0x1f]; 10613 u8 clear_int[0x1]; 10614 10615 u8 health_syndrome[0x8]; 10616 u8 health_counter[0x18]; 10617 10618 u8 reserved_at_80a0[0x17fc0]; 10619 }; 10620 10621 struct mlx5_ifc_mtpps_reg_bits { 10622 u8 reserved_at_0[0xc]; 10623 u8 cap_number_of_pps_pins[0x4]; 10624 u8 reserved_at_10[0x4]; 10625 u8 cap_max_num_of_pps_in_pins[0x4]; 10626 u8 reserved_at_18[0x4]; 10627 u8 cap_max_num_of_pps_out_pins[0x4]; 10628 10629 u8 reserved_at_20[0x13]; 10630 u8 cap_log_min_npps_period[0x5]; 10631 u8 reserved_at_38[0x3]; 10632 u8 cap_log_min_out_pulse_duration_ns[0x5]; 10633 10634 u8 reserved_at_40[0x4]; 10635 u8 cap_pin_3_mode[0x4]; 10636 u8 reserved_at_48[0x4]; 10637 u8 cap_pin_2_mode[0x4]; 10638 u8 reserved_at_50[0x4]; 10639 u8 cap_pin_1_mode[0x4]; 10640 u8 reserved_at_58[0x4]; 10641 u8 cap_pin_0_mode[0x4]; 10642 10643 u8 reserved_at_60[0x4]; 10644 u8 cap_pin_7_mode[0x4]; 10645 u8 reserved_at_68[0x4]; 10646 u8 cap_pin_6_mode[0x4]; 10647 u8 reserved_at_70[0x4]; 10648 u8 cap_pin_5_mode[0x4]; 10649 u8 reserved_at_78[0x4]; 10650 u8 cap_pin_4_mode[0x4]; 10651 10652 u8 field_select[0x20]; 10653 u8 reserved_at_a0[0x20]; 10654 10655 u8 npps_period[0x40]; 10656 10657 u8 enable[0x1]; 10658 u8 reserved_at_101[0xb]; 10659 u8 pattern[0x4]; 10660 u8 reserved_at_110[0x4]; 10661 u8 pin_mode[0x4]; 10662 u8 pin[0x8]; 10663 10664 u8 reserved_at_120[0x2]; 10665 u8 out_pulse_duration_ns[0x1e]; 10666 10667 u8 time_stamp[0x40]; 10668 10669 u8 out_pulse_duration[0x10]; 10670 u8 out_periodic_adjustment[0x10]; 10671 u8 enhanced_out_periodic_adjustment[0x20]; 10672 10673 u8 reserved_at_1c0[0x20]; 10674 }; 10675 10676 struct mlx5_ifc_mtppse_reg_bits { 10677 u8 reserved_at_0[0x18]; 10678 u8 pin[0x8]; 10679 u8 event_arm[0x1]; 10680 u8 reserved_at_21[0x1b]; 10681 u8 event_generation_mode[0x4]; 10682 u8 reserved_at_40[0x40]; 10683 }; 10684 10685 struct mlx5_ifc_mcqs_reg_bits { 10686 u8 last_index_flag[0x1]; 10687 u8 reserved_at_1[0x7]; 10688 u8 fw_device[0x8]; 10689 u8 component_index[0x10]; 10690 10691 u8 reserved_at_20[0x10]; 10692 u8 identifier[0x10]; 10693 10694 u8 reserved_at_40[0x17]; 10695 u8 component_status[0x5]; 10696 u8 component_update_state[0x4]; 10697 10698 u8 last_update_state_changer_type[0x4]; 10699 u8 last_update_state_changer_host_id[0x4]; 10700 u8 reserved_at_68[0x18]; 10701 }; 10702 10703 struct mlx5_ifc_mcqi_cap_bits { 10704 u8 supported_info_bitmask[0x20]; 10705 10706 u8 component_size[0x20]; 10707 10708 u8 max_component_size[0x20]; 10709 10710 u8 log_mcda_word_size[0x4]; 10711 u8 reserved_at_64[0xc]; 10712 u8 mcda_max_write_size[0x10]; 10713 10714 u8 rd_en[0x1]; 10715 u8 reserved_at_81[0x1]; 10716 u8 match_chip_id[0x1]; 10717 u8 match_psid[0x1]; 10718 u8 check_user_timestamp[0x1]; 10719 u8 match_base_guid_mac[0x1]; 10720 u8 reserved_at_86[0x1a]; 10721 }; 10722 10723 struct mlx5_ifc_mcqi_version_bits { 10724 u8 reserved_at_0[0x2]; 10725 u8 build_time_valid[0x1]; 10726 u8 user_defined_time_valid[0x1]; 10727 u8 reserved_at_4[0x14]; 10728 u8 version_string_length[0x8]; 10729 10730 u8 version[0x20]; 10731 10732 u8 build_time[0x40]; 10733 10734 u8 user_defined_time[0x40]; 10735 10736 u8 build_tool_version[0x20]; 10737 10738 u8 reserved_at_e0[0x20]; 10739 10740 u8 version_string[92][0x8]; 10741 }; 10742 10743 struct mlx5_ifc_mcqi_activation_method_bits { 10744 u8 pending_server_ac_power_cycle[0x1]; 10745 u8 pending_server_dc_power_cycle[0x1]; 10746 u8 pending_server_reboot[0x1]; 10747 u8 pending_fw_reset[0x1]; 10748 u8 auto_activate[0x1]; 10749 u8 all_hosts_sync[0x1]; 10750 u8 device_hw_reset[0x1]; 10751 u8 reserved_at_7[0x19]; 10752 }; 10753 10754 union mlx5_ifc_mcqi_reg_data_bits { 10755 struct mlx5_ifc_mcqi_cap_bits mcqi_caps; 10756 struct mlx5_ifc_mcqi_version_bits mcqi_version; 10757 struct mlx5_ifc_mcqi_activation_method_bits mcqi_activation_mathod; 10758 }; 10759 10760 struct mlx5_ifc_mcqi_reg_bits { 10761 u8 read_pending_component[0x1]; 10762 u8 reserved_at_1[0xf]; 10763 u8 component_index[0x10]; 10764 10765 u8 reserved_at_20[0x20]; 10766 10767 u8 reserved_at_40[0x1b]; 10768 u8 info_type[0x5]; 10769 10770 u8 info_size[0x20]; 10771 10772 u8 offset[0x20]; 10773 10774 u8 reserved_at_a0[0x10]; 10775 u8 data_size[0x10]; 10776 10777 union mlx5_ifc_mcqi_reg_data_bits data[]; 10778 }; 10779 10780 struct mlx5_ifc_mcc_reg_bits { 10781 u8 reserved_at_0[0x4]; 10782 u8 time_elapsed_since_last_cmd[0xc]; 10783 u8 reserved_at_10[0x8]; 10784 u8 instruction[0x8]; 10785 10786 u8 reserved_at_20[0x10]; 10787 u8 component_index[0x10]; 10788 10789 u8 reserved_at_40[0x8]; 10790 u8 update_handle[0x18]; 10791 10792 u8 handle_owner_type[0x4]; 10793 u8 handle_owner_host_id[0x4]; 10794 u8 reserved_at_68[0x1]; 10795 u8 control_progress[0x7]; 10796 u8 error_code[0x8]; 10797 u8 reserved_at_78[0x4]; 10798 u8 control_state[0x4]; 10799 10800 u8 component_size[0x20]; 10801 10802 u8 reserved_at_a0[0x60]; 10803 }; 10804 10805 struct mlx5_ifc_mcda_reg_bits { 10806 u8 reserved_at_0[0x8]; 10807 u8 update_handle[0x18]; 10808 10809 u8 offset[0x20]; 10810 10811 u8 reserved_at_40[0x10]; 10812 u8 size[0x10]; 10813 10814 u8 reserved_at_60[0x20]; 10815 10816 u8 data[][0x20]; 10817 }; 10818 10819 enum { 10820 MLX5_MFRL_REG_RESET_STATE_IDLE = 0, 10821 MLX5_MFRL_REG_RESET_STATE_IN_NEGOTIATION = 1, 10822 MLX5_MFRL_REG_RESET_STATE_RESET_IN_PROGRESS = 2, 10823 MLX5_MFRL_REG_RESET_STATE_TIMEOUT = 3, 10824 MLX5_MFRL_REG_RESET_STATE_NACK = 4, 10825 }; 10826 10827 enum { 10828 MLX5_MFRL_REG_RESET_TYPE_FULL_CHIP = BIT(0), 10829 MLX5_MFRL_REG_RESET_TYPE_NET_PORT_ALIVE = BIT(1), 10830 }; 10831 10832 enum { 10833 MLX5_MFRL_REG_RESET_LEVEL0 = BIT(0), 10834 MLX5_MFRL_REG_RESET_LEVEL3 = BIT(3), 10835 MLX5_MFRL_REG_RESET_LEVEL6 = BIT(6), 10836 }; 10837 10838 struct mlx5_ifc_mfrl_reg_bits { 10839 u8 reserved_at_0[0x20]; 10840 10841 u8 reserved_at_20[0x2]; 10842 u8 pci_sync_for_fw_update_start[0x1]; 10843 u8 pci_sync_for_fw_update_resp[0x2]; 10844 u8 rst_type_sel[0x3]; 10845 u8 reserved_at_28[0x4]; 10846 u8 reset_state[0x4]; 10847 u8 reset_type[0x8]; 10848 u8 reset_level[0x8]; 10849 }; 10850 10851 struct mlx5_ifc_mirc_reg_bits { 10852 u8 reserved_at_0[0x18]; 10853 u8 status_code[0x8]; 10854 10855 u8 reserved_at_20[0x20]; 10856 }; 10857 10858 struct mlx5_ifc_pddr_monitor_opcode_bits { 10859 u8 reserved_at_0[0x10]; 10860 u8 monitor_opcode[0x10]; 10861 }; 10862 10863 union mlx5_ifc_pddr_troubleshooting_page_status_opcode_auto_bits { 10864 struct mlx5_ifc_pddr_monitor_opcode_bits pddr_monitor_opcode; 10865 u8 reserved_at_0[0x20]; 10866 }; 10867 10868 enum { 10869 /* Monitor opcodes */ 10870 MLX5_PDDR_REG_TRBLSH_GROUP_OPCODE_MONITOR = 0x0, 10871 }; 10872 10873 struct mlx5_ifc_pddr_troubleshooting_page_bits { 10874 u8 reserved_at_0[0x10]; 10875 u8 group_opcode[0x10]; 10876 10877 union mlx5_ifc_pddr_troubleshooting_page_status_opcode_auto_bits status_opcode; 10878 10879 u8 reserved_at_40[0x20]; 10880 10881 u8 status_message[59][0x20]; 10882 }; 10883 10884 union mlx5_ifc_pddr_reg_page_data_auto_bits { 10885 struct mlx5_ifc_pddr_troubleshooting_page_bits pddr_troubleshooting_page; 10886 u8 reserved_at_0[0x7c0]; 10887 }; 10888 10889 enum { 10890 MLX5_PDDR_REG_PAGE_SELECT_TROUBLESHOOTING_INFO_PAGE = 0x1, 10891 }; 10892 10893 struct mlx5_ifc_pddr_reg_bits { 10894 u8 reserved_at_0[0x8]; 10895 u8 local_port[0x8]; 10896 u8 pnat[0x2]; 10897 u8 reserved_at_12[0xe]; 10898 10899 u8 reserved_at_20[0x18]; 10900 u8 page_select[0x8]; 10901 10902 union mlx5_ifc_pddr_reg_page_data_auto_bits page_data; 10903 }; 10904 10905 struct mlx5_ifc_mrtc_reg_bits { 10906 u8 time_synced[0x1]; 10907 u8 reserved_at_1[0x1f]; 10908 10909 u8 reserved_at_20[0x20]; 10910 10911 u8 time_h[0x20]; 10912 10913 u8 time_l[0x20]; 10914 }; 10915 10916 struct mlx5_ifc_mtmp_reg_bits { 10917 u8 reserved_at_0[0x14]; 10918 u8 sensor_index[0xc]; 10919 10920 u8 reserved_at_20[0x10]; 10921 u8 temperature[0x10]; 10922 10923 u8 mte[0x1]; 10924 u8 mtr[0x1]; 10925 u8 reserved_at_42[0xe]; 10926 u8 max_temperature[0x10]; 10927 10928 u8 tee[0x2]; 10929 u8 reserved_at_62[0xe]; 10930 u8 temp_threshold_hi[0x10]; 10931 10932 u8 reserved_at_80[0x10]; 10933 u8 temp_threshold_lo[0x10]; 10934 10935 u8 reserved_at_a0[0x20]; 10936 10937 u8 sensor_name_hi[0x20]; 10938 u8 sensor_name_lo[0x20]; 10939 }; 10940 10941 union mlx5_ifc_ports_control_registers_document_bits { 10942 struct mlx5_ifc_bufferx_reg_bits bufferx_reg; 10943 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 10944 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 10945 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 10946 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 10947 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 10948 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 10949 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout; 10950 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout; 10951 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping; 10952 struct mlx5_ifc_pamp_reg_bits pamp_reg; 10953 struct mlx5_ifc_paos_reg_bits paos_reg; 10954 struct mlx5_ifc_pcap_reg_bits pcap_reg; 10955 struct mlx5_ifc_pddr_monitor_opcode_bits pddr_monitor_opcode; 10956 struct mlx5_ifc_pddr_reg_bits pddr_reg; 10957 struct mlx5_ifc_pddr_troubleshooting_page_bits pddr_troubleshooting_page; 10958 struct mlx5_ifc_peir_reg_bits peir_reg; 10959 struct mlx5_ifc_pelc_reg_bits pelc_reg; 10960 struct mlx5_ifc_pfcc_reg_bits pfcc_reg; 10961 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 10962 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 10963 struct mlx5_ifc_pifr_reg_bits pifr_reg; 10964 struct mlx5_ifc_pipg_reg_bits pipg_reg; 10965 struct mlx5_ifc_plbf_reg_bits plbf_reg; 10966 struct mlx5_ifc_plib_reg_bits plib_reg; 10967 struct mlx5_ifc_plpc_reg_bits plpc_reg; 10968 struct mlx5_ifc_pmaos_reg_bits pmaos_reg; 10969 struct mlx5_ifc_pmlp_reg_bits pmlp_reg; 10970 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg; 10971 struct mlx5_ifc_pmpc_reg_bits pmpc_reg; 10972 struct mlx5_ifc_pmpe_reg_bits pmpe_reg; 10973 struct mlx5_ifc_pmpr_reg_bits pmpr_reg; 10974 struct mlx5_ifc_pmtu_reg_bits pmtu_reg; 10975 struct mlx5_ifc_ppad_reg_bits ppad_reg; 10976 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg; 10977 struct mlx5_ifc_mpein_reg_bits mpein_reg; 10978 struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg; 10979 struct mlx5_ifc_pplm_reg_bits pplm_reg; 10980 struct mlx5_ifc_pplr_reg_bits pplr_reg; 10981 struct mlx5_ifc_ppsc_reg_bits ppsc_reg; 10982 struct mlx5_ifc_pqdr_reg_bits pqdr_reg; 10983 struct mlx5_ifc_pspa_reg_bits pspa_reg; 10984 struct mlx5_ifc_ptas_reg_bits ptas_reg; 10985 struct mlx5_ifc_ptys_reg_bits ptys_reg; 10986 struct mlx5_ifc_mlcr_reg_bits mlcr_reg; 10987 struct mlx5_ifc_pude_reg_bits pude_reg; 10988 struct mlx5_ifc_pvlc_reg_bits pvlc_reg; 10989 struct mlx5_ifc_slrg_reg_bits slrg_reg; 10990 struct mlx5_ifc_sltp_reg_bits sltp_reg; 10991 struct mlx5_ifc_mtpps_reg_bits mtpps_reg; 10992 struct mlx5_ifc_mtppse_reg_bits mtppse_reg; 10993 struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg; 10994 struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits; 10995 struct mlx5_ifc_fpga_cap_bits fpga_cap_bits; 10996 struct mlx5_ifc_mcqi_reg_bits mcqi_reg; 10997 struct mlx5_ifc_mcc_reg_bits mcc_reg; 10998 struct mlx5_ifc_mcda_reg_bits mcda_reg; 10999 struct mlx5_ifc_mirc_reg_bits mirc_reg; 11000 struct mlx5_ifc_mfrl_reg_bits mfrl_reg; 11001 struct mlx5_ifc_mtutc_reg_bits mtutc_reg; 11002 struct mlx5_ifc_mrtc_reg_bits mrtc_reg; 11003 struct mlx5_ifc_mtmp_reg_bits mtmp_reg; 11004 u8 reserved_at_0[0x60e0]; 11005 }; 11006 11007 union mlx5_ifc_debug_enhancements_document_bits { 11008 struct mlx5_ifc_health_buffer_bits health_buffer; 11009 u8 reserved_at_0[0x200]; 11010 }; 11011 11012 union mlx5_ifc_uplink_pci_interface_document_bits { 11013 struct mlx5_ifc_initial_seg_bits initial_seg; 11014 u8 reserved_at_0[0x20060]; 11015 }; 11016 11017 struct mlx5_ifc_set_flow_table_root_out_bits { 11018 u8 status[0x8]; 11019 u8 reserved_at_8[0x18]; 11020 11021 u8 syndrome[0x20]; 11022 11023 u8 reserved_at_40[0x40]; 11024 }; 11025 11026 struct mlx5_ifc_set_flow_table_root_in_bits { 11027 u8 opcode[0x10]; 11028 u8 reserved_at_10[0x10]; 11029 11030 u8 reserved_at_20[0x10]; 11031 u8 op_mod[0x10]; 11032 11033 u8 other_vport[0x1]; 11034 u8 reserved_at_41[0xf]; 11035 u8 vport_number[0x10]; 11036 11037 u8 reserved_at_60[0x20]; 11038 11039 u8 table_type[0x8]; 11040 u8 reserved_at_88[0x7]; 11041 u8 table_of_other_vport[0x1]; 11042 u8 table_vport_number[0x10]; 11043 11044 u8 reserved_at_a0[0x8]; 11045 u8 table_id[0x18]; 11046 11047 u8 reserved_at_c0[0x8]; 11048 u8 underlay_qpn[0x18]; 11049 u8 table_eswitch_owner_vhca_id_valid[0x1]; 11050 u8 reserved_at_e1[0xf]; 11051 u8 table_eswitch_owner_vhca_id[0x10]; 11052 u8 reserved_at_100[0x100]; 11053 }; 11054 11055 enum { 11056 MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = (1UL << 0), 11057 MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15), 11058 }; 11059 11060 struct mlx5_ifc_modify_flow_table_out_bits { 11061 u8 status[0x8]; 11062 u8 reserved_at_8[0x18]; 11063 11064 u8 syndrome[0x20]; 11065 11066 u8 reserved_at_40[0x40]; 11067 }; 11068 11069 struct mlx5_ifc_modify_flow_table_in_bits { 11070 u8 opcode[0x10]; 11071 u8 reserved_at_10[0x10]; 11072 11073 u8 reserved_at_20[0x10]; 11074 u8 op_mod[0x10]; 11075 11076 u8 other_vport[0x1]; 11077 u8 reserved_at_41[0xf]; 11078 u8 vport_number[0x10]; 11079 11080 u8 reserved_at_60[0x10]; 11081 u8 modify_field_select[0x10]; 11082 11083 u8 table_type[0x8]; 11084 u8 reserved_at_88[0x18]; 11085 11086 u8 reserved_at_a0[0x8]; 11087 u8 table_id[0x18]; 11088 11089 struct mlx5_ifc_flow_table_context_bits flow_table_context; 11090 }; 11091 11092 struct mlx5_ifc_ets_tcn_config_reg_bits { 11093 u8 g[0x1]; 11094 u8 b[0x1]; 11095 u8 r[0x1]; 11096 u8 reserved_at_3[0x9]; 11097 u8 group[0x4]; 11098 u8 reserved_at_10[0x9]; 11099 u8 bw_allocation[0x7]; 11100 11101 u8 reserved_at_20[0xc]; 11102 u8 max_bw_units[0x4]; 11103 u8 reserved_at_30[0x8]; 11104 u8 max_bw_value[0x8]; 11105 }; 11106 11107 struct mlx5_ifc_ets_global_config_reg_bits { 11108 u8 reserved_at_0[0x2]; 11109 u8 r[0x1]; 11110 u8 reserved_at_3[0x1d]; 11111 11112 u8 reserved_at_20[0xc]; 11113 u8 max_bw_units[0x4]; 11114 u8 reserved_at_30[0x8]; 11115 u8 max_bw_value[0x8]; 11116 }; 11117 11118 struct mlx5_ifc_qetc_reg_bits { 11119 u8 reserved_at_0[0x8]; 11120 u8 port_number[0x8]; 11121 u8 reserved_at_10[0x30]; 11122 11123 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8]; 11124 struct mlx5_ifc_ets_global_config_reg_bits global_configuration; 11125 }; 11126 11127 struct mlx5_ifc_qpdpm_dscp_reg_bits { 11128 u8 e[0x1]; 11129 u8 reserved_at_01[0x0b]; 11130 u8 prio[0x04]; 11131 }; 11132 11133 struct mlx5_ifc_qpdpm_reg_bits { 11134 u8 reserved_at_0[0x8]; 11135 u8 local_port[0x8]; 11136 u8 reserved_at_10[0x10]; 11137 struct mlx5_ifc_qpdpm_dscp_reg_bits dscp[64]; 11138 }; 11139 11140 struct mlx5_ifc_qpts_reg_bits { 11141 u8 reserved_at_0[0x8]; 11142 u8 local_port[0x8]; 11143 u8 reserved_at_10[0x2d]; 11144 u8 trust_state[0x3]; 11145 }; 11146 11147 struct mlx5_ifc_pptb_reg_bits { 11148 u8 reserved_at_0[0x2]; 11149 u8 mm[0x2]; 11150 u8 reserved_at_4[0x4]; 11151 u8 local_port[0x8]; 11152 u8 reserved_at_10[0x6]; 11153 u8 cm[0x1]; 11154 u8 um[0x1]; 11155 u8 pm[0x8]; 11156 11157 u8 prio_x_buff[0x20]; 11158 11159 u8 pm_msb[0x8]; 11160 u8 reserved_at_48[0x10]; 11161 u8 ctrl_buff[0x4]; 11162 u8 untagged_buff[0x4]; 11163 }; 11164 11165 struct mlx5_ifc_sbcam_reg_bits { 11166 u8 reserved_at_0[0x8]; 11167 u8 feature_group[0x8]; 11168 u8 reserved_at_10[0x8]; 11169 u8 access_reg_group[0x8]; 11170 11171 u8 reserved_at_20[0x20]; 11172 11173 u8 sb_access_reg_cap_mask[4][0x20]; 11174 11175 u8 reserved_at_c0[0x80]; 11176 11177 u8 sb_feature_cap_mask[4][0x20]; 11178 11179 u8 reserved_at_1c0[0x40]; 11180 11181 u8 cap_total_buffer_size[0x20]; 11182 11183 u8 cap_cell_size[0x10]; 11184 u8 cap_max_pg_buffers[0x8]; 11185 u8 cap_num_pool_supported[0x8]; 11186 11187 u8 reserved_at_240[0x8]; 11188 u8 cap_sbsr_stat_size[0x8]; 11189 u8 cap_max_tclass_data[0x8]; 11190 u8 cap_max_cpu_ingress_tclass_sb[0x8]; 11191 }; 11192 11193 struct mlx5_ifc_pbmc_reg_bits { 11194 u8 reserved_at_0[0x8]; 11195 u8 local_port[0x8]; 11196 u8 reserved_at_10[0x10]; 11197 11198 u8 xoff_timer_value[0x10]; 11199 u8 xoff_refresh[0x10]; 11200 11201 u8 reserved_at_40[0x9]; 11202 u8 fullness_threshold[0x7]; 11203 u8 port_buffer_size[0x10]; 11204 11205 struct mlx5_ifc_bufferx_reg_bits buffer[10]; 11206 11207 u8 reserved_at_2e0[0x80]; 11208 }; 11209 11210 struct mlx5_ifc_sbpr_reg_bits { 11211 u8 desc[0x1]; 11212 u8 snap[0x1]; 11213 u8 reserved_at_2[0x4]; 11214 u8 dir[0x2]; 11215 u8 reserved_at_8[0x14]; 11216 u8 pool[0x4]; 11217 11218 u8 infi_size[0x1]; 11219 u8 reserved_at_21[0x7]; 11220 u8 size[0x18]; 11221 11222 u8 reserved_at_40[0x1c]; 11223 u8 mode[0x4]; 11224 11225 u8 reserved_at_60[0x8]; 11226 u8 buff_occupancy[0x18]; 11227 11228 u8 clr[0x1]; 11229 u8 reserved_at_81[0x7]; 11230 u8 max_buff_occupancy[0x18]; 11231 11232 u8 reserved_at_a0[0x8]; 11233 u8 ext_buff_occupancy[0x18]; 11234 }; 11235 11236 struct mlx5_ifc_sbcm_reg_bits { 11237 u8 desc[0x1]; 11238 u8 snap[0x1]; 11239 u8 reserved_at_2[0x6]; 11240 u8 local_port[0x8]; 11241 u8 pnat[0x2]; 11242 u8 pg_buff[0x6]; 11243 u8 reserved_at_18[0x6]; 11244 u8 dir[0x2]; 11245 11246 u8 reserved_at_20[0x1f]; 11247 u8 exc[0x1]; 11248 11249 u8 reserved_at_40[0x40]; 11250 11251 u8 reserved_at_80[0x8]; 11252 u8 buff_occupancy[0x18]; 11253 11254 u8 clr[0x1]; 11255 u8 reserved_at_a1[0x7]; 11256 u8 max_buff_occupancy[0x18]; 11257 11258 u8 reserved_at_c0[0x8]; 11259 u8 min_buff[0x18]; 11260 11261 u8 infi_max[0x1]; 11262 u8 reserved_at_e1[0x7]; 11263 u8 max_buff[0x18]; 11264 11265 u8 reserved_at_100[0x20]; 11266 11267 u8 reserved_at_120[0x1c]; 11268 u8 pool[0x4]; 11269 }; 11270 11271 struct mlx5_ifc_qtct_reg_bits { 11272 u8 reserved_at_0[0x8]; 11273 u8 port_number[0x8]; 11274 u8 reserved_at_10[0xd]; 11275 u8 prio[0x3]; 11276 11277 u8 reserved_at_20[0x1d]; 11278 u8 tclass[0x3]; 11279 }; 11280 11281 struct mlx5_ifc_mcia_reg_bits { 11282 u8 l[0x1]; 11283 u8 reserved_at_1[0x7]; 11284 u8 module[0x8]; 11285 u8 reserved_at_10[0x8]; 11286 u8 status[0x8]; 11287 11288 u8 i2c_device_address[0x8]; 11289 u8 page_number[0x8]; 11290 u8 device_address[0x10]; 11291 11292 u8 reserved_at_40[0x10]; 11293 u8 size[0x10]; 11294 11295 u8 reserved_at_60[0x20]; 11296 11297 u8 dword_0[0x20]; 11298 u8 dword_1[0x20]; 11299 u8 dword_2[0x20]; 11300 u8 dword_3[0x20]; 11301 u8 dword_4[0x20]; 11302 u8 dword_5[0x20]; 11303 u8 dword_6[0x20]; 11304 u8 dword_7[0x20]; 11305 u8 dword_8[0x20]; 11306 u8 dword_9[0x20]; 11307 u8 dword_10[0x20]; 11308 u8 dword_11[0x20]; 11309 }; 11310 11311 struct mlx5_ifc_dcbx_param_bits { 11312 u8 dcbx_cee_cap[0x1]; 11313 u8 dcbx_ieee_cap[0x1]; 11314 u8 dcbx_standby_cap[0x1]; 11315 u8 reserved_at_3[0x5]; 11316 u8 port_number[0x8]; 11317 u8 reserved_at_10[0xa]; 11318 u8 max_application_table_size[6]; 11319 u8 reserved_at_20[0x15]; 11320 u8 version_oper[0x3]; 11321 u8 reserved_at_38[5]; 11322 u8 version_admin[0x3]; 11323 u8 willing_admin[0x1]; 11324 u8 reserved_at_41[0x3]; 11325 u8 pfc_cap_oper[0x4]; 11326 u8 reserved_at_48[0x4]; 11327 u8 pfc_cap_admin[0x4]; 11328 u8 reserved_at_50[0x4]; 11329 u8 num_of_tc_oper[0x4]; 11330 u8 reserved_at_58[0x4]; 11331 u8 num_of_tc_admin[0x4]; 11332 u8 remote_willing[0x1]; 11333 u8 reserved_at_61[3]; 11334 u8 remote_pfc_cap[4]; 11335 u8 reserved_at_68[0x14]; 11336 u8 remote_num_of_tc[0x4]; 11337 u8 reserved_at_80[0x18]; 11338 u8 error[0x8]; 11339 u8 reserved_at_a0[0x160]; 11340 }; 11341 11342 enum { 11343 MLX5_LAG_PORT_SELECT_MODE_QUEUE_AFFINITY = 0, 11344 MLX5_LAG_PORT_SELECT_MODE_PORT_SELECT_FT = 1, 11345 MLX5_LAG_PORT_SELECT_MODE_PORT_SELECT_MPESW = 2, 11346 }; 11347 11348 struct mlx5_ifc_lagc_bits { 11349 u8 fdb_selection_mode[0x1]; 11350 u8 reserved_at_1[0x14]; 11351 u8 port_select_mode[0x3]; 11352 u8 reserved_at_18[0x5]; 11353 u8 lag_state[0x3]; 11354 11355 u8 reserved_at_20[0xc]; 11356 u8 active_port[0x4]; 11357 u8 reserved_at_30[0x4]; 11358 u8 tx_remap_affinity_2[0x4]; 11359 u8 reserved_at_38[0x4]; 11360 u8 tx_remap_affinity_1[0x4]; 11361 }; 11362 11363 struct mlx5_ifc_create_lag_out_bits { 11364 u8 status[0x8]; 11365 u8 reserved_at_8[0x18]; 11366 11367 u8 syndrome[0x20]; 11368 11369 u8 reserved_at_40[0x40]; 11370 }; 11371 11372 struct mlx5_ifc_create_lag_in_bits { 11373 u8 opcode[0x10]; 11374 u8 reserved_at_10[0x10]; 11375 11376 u8 reserved_at_20[0x10]; 11377 u8 op_mod[0x10]; 11378 11379 struct mlx5_ifc_lagc_bits ctx; 11380 }; 11381 11382 struct mlx5_ifc_modify_lag_out_bits { 11383 u8 status[0x8]; 11384 u8 reserved_at_8[0x18]; 11385 11386 u8 syndrome[0x20]; 11387 11388 u8 reserved_at_40[0x40]; 11389 }; 11390 11391 struct mlx5_ifc_modify_lag_in_bits { 11392 u8 opcode[0x10]; 11393 u8 reserved_at_10[0x10]; 11394 11395 u8 reserved_at_20[0x10]; 11396 u8 op_mod[0x10]; 11397 11398 u8 reserved_at_40[0x20]; 11399 u8 field_select[0x20]; 11400 11401 struct mlx5_ifc_lagc_bits ctx; 11402 }; 11403 11404 struct mlx5_ifc_query_lag_out_bits { 11405 u8 status[0x8]; 11406 u8 reserved_at_8[0x18]; 11407 11408 u8 syndrome[0x20]; 11409 11410 struct mlx5_ifc_lagc_bits ctx; 11411 }; 11412 11413 struct mlx5_ifc_query_lag_in_bits { 11414 u8 opcode[0x10]; 11415 u8 reserved_at_10[0x10]; 11416 11417 u8 reserved_at_20[0x10]; 11418 u8 op_mod[0x10]; 11419 11420 u8 reserved_at_40[0x40]; 11421 }; 11422 11423 struct mlx5_ifc_destroy_lag_out_bits { 11424 u8 status[0x8]; 11425 u8 reserved_at_8[0x18]; 11426 11427 u8 syndrome[0x20]; 11428 11429 u8 reserved_at_40[0x40]; 11430 }; 11431 11432 struct mlx5_ifc_destroy_lag_in_bits { 11433 u8 opcode[0x10]; 11434 u8 reserved_at_10[0x10]; 11435 11436 u8 reserved_at_20[0x10]; 11437 u8 op_mod[0x10]; 11438 11439 u8 reserved_at_40[0x40]; 11440 }; 11441 11442 struct mlx5_ifc_create_vport_lag_out_bits { 11443 u8 status[0x8]; 11444 u8 reserved_at_8[0x18]; 11445 11446 u8 syndrome[0x20]; 11447 11448 u8 reserved_at_40[0x40]; 11449 }; 11450 11451 struct mlx5_ifc_create_vport_lag_in_bits { 11452 u8 opcode[0x10]; 11453 u8 reserved_at_10[0x10]; 11454 11455 u8 reserved_at_20[0x10]; 11456 u8 op_mod[0x10]; 11457 11458 u8 reserved_at_40[0x40]; 11459 }; 11460 11461 struct mlx5_ifc_destroy_vport_lag_out_bits { 11462 u8 status[0x8]; 11463 u8 reserved_at_8[0x18]; 11464 11465 u8 syndrome[0x20]; 11466 11467 u8 reserved_at_40[0x40]; 11468 }; 11469 11470 struct mlx5_ifc_destroy_vport_lag_in_bits { 11471 u8 opcode[0x10]; 11472 u8 reserved_at_10[0x10]; 11473 11474 u8 reserved_at_20[0x10]; 11475 u8 op_mod[0x10]; 11476 11477 u8 reserved_at_40[0x40]; 11478 }; 11479 11480 enum { 11481 MLX5_MODIFY_MEMIC_OP_MOD_ALLOC, 11482 MLX5_MODIFY_MEMIC_OP_MOD_DEALLOC, 11483 }; 11484 11485 struct mlx5_ifc_modify_memic_in_bits { 11486 u8 opcode[0x10]; 11487 u8 uid[0x10]; 11488 11489 u8 reserved_at_20[0x10]; 11490 u8 op_mod[0x10]; 11491 11492 u8 reserved_at_40[0x20]; 11493 11494 u8 reserved_at_60[0x18]; 11495 u8 memic_operation_type[0x8]; 11496 11497 u8 memic_start_addr[0x40]; 11498 11499 u8 reserved_at_c0[0x140]; 11500 }; 11501 11502 struct mlx5_ifc_modify_memic_out_bits { 11503 u8 status[0x8]; 11504 u8 reserved_at_8[0x18]; 11505 11506 u8 syndrome[0x20]; 11507 11508 u8 reserved_at_40[0x40]; 11509 11510 u8 memic_operation_addr[0x40]; 11511 11512 u8 reserved_at_c0[0x140]; 11513 }; 11514 11515 struct mlx5_ifc_alloc_memic_in_bits { 11516 u8 opcode[0x10]; 11517 u8 reserved_at_10[0x10]; 11518 11519 u8 reserved_at_20[0x10]; 11520 u8 op_mod[0x10]; 11521 11522 u8 reserved_at_30[0x20]; 11523 11524 u8 reserved_at_40[0x18]; 11525 u8 log_memic_addr_alignment[0x8]; 11526 11527 u8 range_start_addr[0x40]; 11528 11529 u8 range_size[0x20]; 11530 11531 u8 memic_size[0x20]; 11532 }; 11533 11534 struct mlx5_ifc_alloc_memic_out_bits { 11535 u8 status[0x8]; 11536 u8 reserved_at_8[0x18]; 11537 11538 u8 syndrome[0x20]; 11539 11540 u8 memic_start_addr[0x40]; 11541 }; 11542 11543 struct mlx5_ifc_dealloc_memic_in_bits { 11544 u8 opcode[0x10]; 11545 u8 reserved_at_10[0x10]; 11546 11547 u8 reserved_at_20[0x10]; 11548 u8 op_mod[0x10]; 11549 11550 u8 reserved_at_40[0x40]; 11551 11552 u8 memic_start_addr[0x40]; 11553 11554 u8 memic_size[0x20]; 11555 11556 u8 reserved_at_e0[0x20]; 11557 }; 11558 11559 struct mlx5_ifc_dealloc_memic_out_bits { 11560 u8 status[0x8]; 11561 u8 reserved_at_8[0x18]; 11562 11563 u8 syndrome[0x20]; 11564 11565 u8 reserved_at_40[0x40]; 11566 }; 11567 11568 struct mlx5_ifc_umem_bits { 11569 u8 reserved_at_0[0x80]; 11570 11571 u8 ats[0x1]; 11572 u8 reserved_at_81[0x1a]; 11573 u8 log_page_size[0x5]; 11574 11575 u8 page_offset[0x20]; 11576 11577 u8 num_of_mtt[0x40]; 11578 11579 struct mlx5_ifc_mtt_bits mtt[]; 11580 }; 11581 11582 struct mlx5_ifc_uctx_bits { 11583 u8 cap[0x20]; 11584 11585 u8 reserved_at_20[0x160]; 11586 }; 11587 11588 struct mlx5_ifc_sw_icm_bits { 11589 u8 modify_field_select[0x40]; 11590 11591 u8 reserved_at_40[0x18]; 11592 u8 log_sw_icm_size[0x8]; 11593 11594 u8 reserved_at_60[0x20]; 11595 11596 u8 sw_icm_start_addr[0x40]; 11597 11598 u8 reserved_at_c0[0x140]; 11599 }; 11600 11601 struct mlx5_ifc_geneve_tlv_option_bits { 11602 u8 modify_field_select[0x40]; 11603 11604 u8 reserved_at_40[0x18]; 11605 u8 geneve_option_fte_index[0x8]; 11606 11607 u8 option_class[0x10]; 11608 u8 option_type[0x8]; 11609 u8 reserved_at_78[0x3]; 11610 u8 option_data_length[0x5]; 11611 11612 u8 reserved_at_80[0x180]; 11613 }; 11614 11615 struct mlx5_ifc_create_umem_in_bits { 11616 u8 opcode[0x10]; 11617 u8 uid[0x10]; 11618 11619 u8 reserved_at_20[0x10]; 11620 u8 op_mod[0x10]; 11621 11622 u8 reserved_at_40[0x40]; 11623 11624 struct mlx5_ifc_umem_bits umem; 11625 }; 11626 11627 struct mlx5_ifc_create_umem_out_bits { 11628 u8 status[0x8]; 11629 u8 reserved_at_8[0x18]; 11630 11631 u8 syndrome[0x20]; 11632 11633 u8 reserved_at_40[0x8]; 11634 u8 umem_id[0x18]; 11635 11636 u8 reserved_at_60[0x20]; 11637 }; 11638 11639 struct mlx5_ifc_destroy_umem_in_bits { 11640 u8 opcode[0x10]; 11641 u8 uid[0x10]; 11642 11643 u8 reserved_at_20[0x10]; 11644 u8 op_mod[0x10]; 11645 11646 u8 reserved_at_40[0x8]; 11647 u8 umem_id[0x18]; 11648 11649 u8 reserved_at_60[0x20]; 11650 }; 11651 11652 struct mlx5_ifc_destroy_umem_out_bits { 11653 u8 status[0x8]; 11654 u8 reserved_at_8[0x18]; 11655 11656 u8 syndrome[0x20]; 11657 11658 u8 reserved_at_40[0x40]; 11659 }; 11660 11661 struct mlx5_ifc_create_uctx_in_bits { 11662 u8 opcode[0x10]; 11663 u8 reserved_at_10[0x10]; 11664 11665 u8 reserved_at_20[0x10]; 11666 u8 op_mod[0x10]; 11667 11668 u8 reserved_at_40[0x40]; 11669 11670 struct mlx5_ifc_uctx_bits uctx; 11671 }; 11672 11673 struct mlx5_ifc_create_uctx_out_bits { 11674 u8 status[0x8]; 11675 u8 reserved_at_8[0x18]; 11676 11677 u8 syndrome[0x20]; 11678 11679 u8 reserved_at_40[0x10]; 11680 u8 uid[0x10]; 11681 11682 u8 reserved_at_60[0x20]; 11683 }; 11684 11685 struct mlx5_ifc_destroy_uctx_in_bits { 11686 u8 opcode[0x10]; 11687 u8 reserved_at_10[0x10]; 11688 11689 u8 reserved_at_20[0x10]; 11690 u8 op_mod[0x10]; 11691 11692 u8 reserved_at_40[0x10]; 11693 u8 uid[0x10]; 11694 11695 u8 reserved_at_60[0x20]; 11696 }; 11697 11698 struct mlx5_ifc_destroy_uctx_out_bits { 11699 u8 status[0x8]; 11700 u8 reserved_at_8[0x18]; 11701 11702 u8 syndrome[0x20]; 11703 11704 u8 reserved_at_40[0x40]; 11705 }; 11706 11707 struct mlx5_ifc_create_sw_icm_in_bits { 11708 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 11709 struct mlx5_ifc_sw_icm_bits sw_icm; 11710 }; 11711 11712 struct mlx5_ifc_create_geneve_tlv_option_in_bits { 11713 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 11714 struct mlx5_ifc_geneve_tlv_option_bits geneve_tlv_opt; 11715 }; 11716 11717 struct mlx5_ifc_mtrc_string_db_param_bits { 11718 u8 string_db_base_address[0x20]; 11719 11720 u8 reserved_at_20[0x8]; 11721 u8 string_db_size[0x18]; 11722 }; 11723 11724 struct mlx5_ifc_mtrc_cap_bits { 11725 u8 trace_owner[0x1]; 11726 u8 trace_to_memory[0x1]; 11727 u8 reserved_at_2[0x4]; 11728 u8 trc_ver[0x2]; 11729 u8 reserved_at_8[0x14]; 11730 u8 num_string_db[0x4]; 11731 11732 u8 first_string_trace[0x8]; 11733 u8 num_string_trace[0x8]; 11734 u8 reserved_at_30[0x28]; 11735 11736 u8 log_max_trace_buffer_size[0x8]; 11737 11738 u8 reserved_at_60[0x20]; 11739 11740 struct mlx5_ifc_mtrc_string_db_param_bits string_db_param[8]; 11741 11742 u8 reserved_at_280[0x180]; 11743 }; 11744 11745 struct mlx5_ifc_mtrc_conf_bits { 11746 u8 reserved_at_0[0x1c]; 11747 u8 trace_mode[0x4]; 11748 u8 reserved_at_20[0x18]; 11749 u8 log_trace_buffer_size[0x8]; 11750 u8 trace_mkey[0x20]; 11751 u8 reserved_at_60[0x3a0]; 11752 }; 11753 11754 struct mlx5_ifc_mtrc_stdb_bits { 11755 u8 string_db_index[0x4]; 11756 u8 reserved_at_4[0x4]; 11757 u8 read_size[0x18]; 11758 u8 start_offset[0x20]; 11759 u8 string_db_data[]; 11760 }; 11761 11762 struct mlx5_ifc_mtrc_ctrl_bits { 11763 u8 trace_status[0x2]; 11764 u8 reserved_at_2[0x2]; 11765 u8 arm_event[0x1]; 11766 u8 reserved_at_5[0xb]; 11767 u8 modify_field_select[0x10]; 11768 u8 reserved_at_20[0x2b]; 11769 u8 current_timestamp52_32[0x15]; 11770 u8 current_timestamp31_0[0x20]; 11771 u8 reserved_at_80[0x180]; 11772 }; 11773 11774 struct mlx5_ifc_host_params_context_bits { 11775 u8 host_number[0x8]; 11776 u8 reserved_at_8[0x7]; 11777 u8 host_pf_disabled[0x1]; 11778 u8 host_num_of_vfs[0x10]; 11779 11780 u8 host_total_vfs[0x10]; 11781 u8 host_pci_bus[0x10]; 11782 11783 u8 reserved_at_40[0x10]; 11784 u8 host_pci_device[0x10]; 11785 11786 u8 reserved_at_60[0x10]; 11787 u8 host_pci_function[0x10]; 11788 11789 u8 reserved_at_80[0x180]; 11790 }; 11791 11792 struct mlx5_ifc_query_esw_functions_in_bits { 11793 u8 opcode[0x10]; 11794 u8 reserved_at_10[0x10]; 11795 11796 u8 reserved_at_20[0x10]; 11797 u8 op_mod[0x10]; 11798 11799 u8 reserved_at_40[0x40]; 11800 }; 11801 11802 struct mlx5_ifc_query_esw_functions_out_bits { 11803 u8 status[0x8]; 11804 u8 reserved_at_8[0x18]; 11805 11806 u8 syndrome[0x20]; 11807 11808 u8 reserved_at_40[0x40]; 11809 11810 struct mlx5_ifc_host_params_context_bits host_params_context; 11811 11812 u8 reserved_at_280[0x180]; 11813 u8 host_sf_enable[][0x40]; 11814 }; 11815 11816 struct mlx5_ifc_sf_partition_bits { 11817 u8 reserved_at_0[0x10]; 11818 u8 log_num_sf[0x8]; 11819 u8 log_sf_bar_size[0x8]; 11820 }; 11821 11822 struct mlx5_ifc_query_sf_partitions_out_bits { 11823 u8 status[0x8]; 11824 u8 reserved_at_8[0x18]; 11825 11826 u8 syndrome[0x20]; 11827 11828 u8 reserved_at_40[0x18]; 11829 u8 num_sf_partitions[0x8]; 11830 11831 u8 reserved_at_60[0x20]; 11832 11833 struct mlx5_ifc_sf_partition_bits sf_partition[]; 11834 }; 11835 11836 struct mlx5_ifc_query_sf_partitions_in_bits { 11837 u8 opcode[0x10]; 11838 u8 reserved_at_10[0x10]; 11839 11840 u8 reserved_at_20[0x10]; 11841 u8 op_mod[0x10]; 11842 11843 u8 reserved_at_40[0x40]; 11844 }; 11845 11846 struct mlx5_ifc_dealloc_sf_out_bits { 11847 u8 status[0x8]; 11848 u8 reserved_at_8[0x18]; 11849 11850 u8 syndrome[0x20]; 11851 11852 u8 reserved_at_40[0x40]; 11853 }; 11854 11855 struct mlx5_ifc_dealloc_sf_in_bits { 11856 u8 opcode[0x10]; 11857 u8 reserved_at_10[0x10]; 11858 11859 u8 reserved_at_20[0x10]; 11860 u8 op_mod[0x10]; 11861 11862 u8 reserved_at_40[0x10]; 11863 u8 function_id[0x10]; 11864 11865 u8 reserved_at_60[0x20]; 11866 }; 11867 11868 struct mlx5_ifc_alloc_sf_out_bits { 11869 u8 status[0x8]; 11870 u8 reserved_at_8[0x18]; 11871 11872 u8 syndrome[0x20]; 11873 11874 u8 reserved_at_40[0x40]; 11875 }; 11876 11877 struct mlx5_ifc_alloc_sf_in_bits { 11878 u8 opcode[0x10]; 11879 u8 reserved_at_10[0x10]; 11880 11881 u8 reserved_at_20[0x10]; 11882 u8 op_mod[0x10]; 11883 11884 u8 reserved_at_40[0x10]; 11885 u8 function_id[0x10]; 11886 11887 u8 reserved_at_60[0x20]; 11888 }; 11889 11890 struct mlx5_ifc_affiliated_event_header_bits { 11891 u8 reserved_at_0[0x10]; 11892 u8 obj_type[0x10]; 11893 11894 u8 obj_id[0x20]; 11895 }; 11896 11897 enum { 11898 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = BIT_ULL(0xc), 11899 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_IPSEC = BIT_ULL(0x13), 11900 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_SAMPLER = BIT_ULL(0x20), 11901 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_FLOW_METER_ASO = BIT_ULL(0x24), 11902 }; 11903 11904 enum { 11905 MLX5_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = 0xc, 11906 MLX5_GENERAL_OBJECT_TYPES_IPSEC = 0x13, 11907 MLX5_GENERAL_OBJECT_TYPES_SAMPLER = 0x20, 11908 MLX5_GENERAL_OBJECT_TYPES_FLOW_METER_ASO = 0x24, 11909 MLX5_GENERAL_OBJECT_TYPES_MACSEC = 0x27, 11910 MLX5_GENERAL_OBJECT_TYPES_INT_KEK = 0x47, 11911 }; 11912 11913 enum { 11914 MLX5_IPSEC_OBJECT_ICV_LEN_16B, 11915 }; 11916 11917 enum { 11918 MLX5_IPSEC_ASO_REG_C_0_1 = 0x0, 11919 MLX5_IPSEC_ASO_REG_C_2_3 = 0x1, 11920 MLX5_IPSEC_ASO_REG_C_4_5 = 0x2, 11921 MLX5_IPSEC_ASO_REG_C_6_7 = 0x3, 11922 }; 11923 11924 enum { 11925 MLX5_IPSEC_ASO_MODE = 0x0, 11926 MLX5_IPSEC_ASO_REPLAY_PROTECTION = 0x1, 11927 MLX5_IPSEC_ASO_INC_SN = 0x2, 11928 }; 11929 11930 struct mlx5_ifc_ipsec_aso_bits { 11931 u8 valid[0x1]; 11932 u8 reserved_at_201[0x1]; 11933 u8 mode[0x2]; 11934 u8 window_sz[0x2]; 11935 u8 soft_lft_arm[0x1]; 11936 u8 hard_lft_arm[0x1]; 11937 u8 remove_flow_enable[0x1]; 11938 u8 esn_event_arm[0x1]; 11939 u8 reserved_at_20a[0x16]; 11940 11941 u8 remove_flow_pkt_cnt[0x20]; 11942 11943 u8 remove_flow_soft_lft[0x20]; 11944 11945 u8 reserved_at_260[0x80]; 11946 11947 u8 mode_parameter[0x20]; 11948 11949 u8 replay_protection_window[0x100]; 11950 }; 11951 11952 struct mlx5_ifc_ipsec_obj_bits { 11953 u8 modify_field_select[0x40]; 11954 u8 full_offload[0x1]; 11955 u8 reserved_at_41[0x1]; 11956 u8 esn_en[0x1]; 11957 u8 esn_overlap[0x1]; 11958 u8 reserved_at_44[0x2]; 11959 u8 icv_length[0x2]; 11960 u8 reserved_at_48[0x4]; 11961 u8 aso_return_reg[0x4]; 11962 u8 reserved_at_50[0x10]; 11963 11964 u8 esn_msb[0x20]; 11965 11966 u8 reserved_at_80[0x8]; 11967 u8 dekn[0x18]; 11968 11969 u8 salt[0x20]; 11970 11971 u8 implicit_iv[0x40]; 11972 11973 u8 reserved_at_100[0x8]; 11974 u8 ipsec_aso_access_pd[0x18]; 11975 u8 reserved_at_120[0xe0]; 11976 11977 struct mlx5_ifc_ipsec_aso_bits ipsec_aso; 11978 }; 11979 11980 struct mlx5_ifc_create_ipsec_obj_in_bits { 11981 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 11982 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 11983 }; 11984 11985 enum { 11986 MLX5_MODIFY_IPSEC_BITMASK_ESN_OVERLAP = BIT(0), 11987 MLX5_MODIFY_IPSEC_BITMASK_ESN_MSB = BIT(1), 11988 }; 11989 11990 struct mlx5_ifc_query_ipsec_obj_out_bits { 11991 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 11992 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 11993 }; 11994 11995 struct mlx5_ifc_modify_ipsec_obj_in_bits { 11996 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 11997 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 11998 }; 11999 12000 enum { 12001 MLX5_MACSEC_ASO_REPLAY_PROTECTION = 0x1, 12002 }; 12003 12004 enum { 12005 MLX5_MACSEC_ASO_REPLAY_WIN_32BIT = 0x0, 12006 MLX5_MACSEC_ASO_REPLAY_WIN_64BIT = 0x1, 12007 MLX5_MACSEC_ASO_REPLAY_WIN_128BIT = 0x2, 12008 MLX5_MACSEC_ASO_REPLAY_WIN_256BIT = 0x3, 12009 }; 12010 12011 #define MLX5_MACSEC_ASO_INC_SN 0x2 12012 #define MLX5_MACSEC_ASO_REG_C_4_5 0x2 12013 12014 struct mlx5_ifc_macsec_aso_bits { 12015 u8 valid[0x1]; 12016 u8 reserved_at_1[0x1]; 12017 u8 mode[0x2]; 12018 u8 window_size[0x2]; 12019 u8 soft_lifetime_arm[0x1]; 12020 u8 hard_lifetime_arm[0x1]; 12021 u8 remove_flow_enable[0x1]; 12022 u8 epn_event_arm[0x1]; 12023 u8 reserved_at_a[0x16]; 12024 12025 u8 remove_flow_packet_count[0x20]; 12026 12027 u8 remove_flow_soft_lifetime[0x20]; 12028 12029 u8 reserved_at_60[0x80]; 12030 12031 u8 mode_parameter[0x20]; 12032 12033 u8 replay_protection_window[8][0x20]; 12034 }; 12035 12036 struct mlx5_ifc_macsec_offload_obj_bits { 12037 u8 modify_field_select[0x40]; 12038 12039 u8 confidentiality_en[0x1]; 12040 u8 reserved_at_41[0x1]; 12041 u8 epn_en[0x1]; 12042 u8 epn_overlap[0x1]; 12043 u8 reserved_at_44[0x2]; 12044 u8 confidentiality_offset[0x2]; 12045 u8 reserved_at_48[0x4]; 12046 u8 aso_return_reg[0x4]; 12047 u8 reserved_at_50[0x10]; 12048 12049 u8 epn_msb[0x20]; 12050 12051 u8 reserved_at_80[0x8]; 12052 u8 dekn[0x18]; 12053 12054 u8 reserved_at_a0[0x20]; 12055 12056 u8 sci[0x40]; 12057 12058 u8 reserved_at_100[0x8]; 12059 u8 macsec_aso_access_pd[0x18]; 12060 12061 u8 reserved_at_120[0x60]; 12062 12063 u8 salt[3][0x20]; 12064 12065 u8 reserved_at_1e0[0x20]; 12066 12067 struct mlx5_ifc_macsec_aso_bits macsec_aso; 12068 }; 12069 12070 struct mlx5_ifc_create_macsec_obj_in_bits { 12071 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12072 struct mlx5_ifc_macsec_offload_obj_bits macsec_object; 12073 }; 12074 12075 struct mlx5_ifc_modify_macsec_obj_in_bits { 12076 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12077 struct mlx5_ifc_macsec_offload_obj_bits macsec_object; 12078 }; 12079 12080 enum { 12081 MLX5_MODIFY_MACSEC_BITMASK_EPN_OVERLAP = BIT(0), 12082 MLX5_MODIFY_MACSEC_BITMASK_EPN_MSB = BIT(1), 12083 }; 12084 12085 struct mlx5_ifc_query_macsec_obj_out_bits { 12086 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 12087 struct mlx5_ifc_macsec_offload_obj_bits macsec_object; 12088 }; 12089 12090 struct mlx5_ifc_wrapped_dek_bits { 12091 u8 gcm_iv[0x60]; 12092 12093 u8 reserved_at_60[0x20]; 12094 12095 u8 const0[0x1]; 12096 u8 key_size[0x1]; 12097 u8 reserved_at_82[0x2]; 12098 u8 key2_invalid[0x1]; 12099 u8 reserved_at_85[0x3]; 12100 u8 pd[0x18]; 12101 12102 u8 key_purpose[0x5]; 12103 u8 reserved_at_a5[0x13]; 12104 u8 kek_id[0x8]; 12105 12106 u8 reserved_at_c0[0x40]; 12107 12108 u8 key1[0x8][0x20]; 12109 12110 u8 key2[0x8][0x20]; 12111 12112 u8 reserved_at_300[0x40]; 12113 12114 u8 const1[0x1]; 12115 u8 reserved_at_341[0x1f]; 12116 12117 u8 reserved_at_360[0x20]; 12118 12119 u8 auth_tag[0x80]; 12120 }; 12121 12122 struct mlx5_ifc_encryption_key_obj_bits { 12123 u8 modify_field_select[0x40]; 12124 12125 u8 state[0x8]; 12126 u8 sw_wrapped[0x1]; 12127 u8 reserved_at_49[0xb]; 12128 u8 key_size[0x4]; 12129 u8 reserved_at_58[0x4]; 12130 u8 key_purpose[0x4]; 12131 12132 u8 reserved_at_60[0x8]; 12133 u8 pd[0x18]; 12134 12135 u8 reserved_at_80[0x100]; 12136 12137 u8 opaque[0x40]; 12138 12139 u8 reserved_at_1c0[0x40]; 12140 12141 u8 key[8][0x80]; 12142 12143 u8 sw_wrapped_dek[8][0x80]; 12144 12145 u8 reserved_at_a00[0x600]; 12146 }; 12147 12148 struct mlx5_ifc_create_encryption_key_in_bits { 12149 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12150 struct mlx5_ifc_encryption_key_obj_bits encryption_key_object; 12151 }; 12152 12153 struct mlx5_ifc_modify_encryption_key_in_bits { 12154 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12155 struct mlx5_ifc_encryption_key_obj_bits encryption_key_object; 12156 }; 12157 12158 enum { 12159 MLX5_FLOW_METER_MODE_BYTES_IP_LENGTH = 0x0, 12160 MLX5_FLOW_METER_MODE_BYTES_CALC_WITH_L2 = 0x1, 12161 MLX5_FLOW_METER_MODE_BYTES_CALC_WITH_L2_IPG = 0x2, 12162 MLX5_FLOW_METER_MODE_NUM_PACKETS = 0x3, 12163 }; 12164 12165 struct mlx5_ifc_flow_meter_parameters_bits { 12166 u8 valid[0x1]; 12167 u8 bucket_overflow[0x1]; 12168 u8 start_color[0x2]; 12169 u8 both_buckets_on_green[0x1]; 12170 u8 reserved_at_5[0x1]; 12171 u8 meter_mode[0x2]; 12172 u8 reserved_at_8[0x18]; 12173 12174 u8 reserved_at_20[0x20]; 12175 12176 u8 reserved_at_40[0x3]; 12177 u8 cbs_exponent[0x5]; 12178 u8 cbs_mantissa[0x8]; 12179 u8 reserved_at_50[0x3]; 12180 u8 cir_exponent[0x5]; 12181 u8 cir_mantissa[0x8]; 12182 12183 u8 reserved_at_60[0x20]; 12184 12185 u8 reserved_at_80[0x3]; 12186 u8 ebs_exponent[0x5]; 12187 u8 ebs_mantissa[0x8]; 12188 u8 reserved_at_90[0x3]; 12189 u8 eir_exponent[0x5]; 12190 u8 eir_mantissa[0x8]; 12191 12192 u8 reserved_at_a0[0x60]; 12193 }; 12194 12195 struct mlx5_ifc_flow_meter_aso_obj_bits { 12196 u8 modify_field_select[0x40]; 12197 12198 u8 reserved_at_40[0x40]; 12199 12200 u8 reserved_at_80[0x8]; 12201 u8 meter_aso_access_pd[0x18]; 12202 12203 u8 reserved_at_a0[0x160]; 12204 12205 struct mlx5_ifc_flow_meter_parameters_bits flow_meter_parameters[2]; 12206 }; 12207 12208 struct mlx5_ifc_create_flow_meter_aso_obj_in_bits { 12209 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 12210 struct mlx5_ifc_flow_meter_aso_obj_bits flow_meter_aso_obj; 12211 }; 12212 12213 struct mlx5_ifc_int_kek_obj_bits { 12214 u8 modify_field_select[0x40]; 12215 12216 u8 state[0x8]; 12217 u8 auto_gen[0x1]; 12218 u8 reserved_at_49[0xb]; 12219 u8 key_size[0x4]; 12220 u8 reserved_at_58[0x8]; 12221 12222 u8 reserved_at_60[0x8]; 12223 u8 pd[0x18]; 12224 12225 u8 reserved_at_80[0x180]; 12226 u8 key[8][0x80]; 12227 12228 u8 reserved_at_600[0x200]; 12229 }; 12230 12231 struct mlx5_ifc_create_int_kek_obj_in_bits { 12232 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12233 struct mlx5_ifc_int_kek_obj_bits int_kek_object; 12234 }; 12235 12236 struct mlx5_ifc_create_int_kek_obj_out_bits { 12237 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 12238 struct mlx5_ifc_int_kek_obj_bits int_kek_object; 12239 }; 12240 12241 struct mlx5_ifc_sampler_obj_bits { 12242 u8 modify_field_select[0x40]; 12243 12244 u8 table_type[0x8]; 12245 u8 level[0x8]; 12246 u8 reserved_at_50[0xf]; 12247 u8 ignore_flow_level[0x1]; 12248 12249 u8 sample_ratio[0x20]; 12250 12251 u8 reserved_at_80[0x8]; 12252 u8 sample_table_id[0x18]; 12253 12254 u8 reserved_at_a0[0x8]; 12255 u8 default_table_id[0x18]; 12256 12257 u8 sw_steering_icm_address_rx[0x40]; 12258 u8 sw_steering_icm_address_tx[0x40]; 12259 12260 u8 reserved_at_140[0xa0]; 12261 }; 12262 12263 struct mlx5_ifc_create_sampler_obj_in_bits { 12264 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12265 struct mlx5_ifc_sampler_obj_bits sampler_object; 12266 }; 12267 12268 struct mlx5_ifc_query_sampler_obj_out_bits { 12269 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 12270 struct mlx5_ifc_sampler_obj_bits sampler_object; 12271 }; 12272 12273 enum { 12274 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_128 = 0x0, 12275 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_256 = 0x1, 12276 }; 12277 12278 enum { 12279 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_PURPOSE_TLS = 0x1, 12280 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_PURPOSE_IPSEC = 0x2, 12281 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_PURPOSE_MACSEC = 0x4, 12282 }; 12283 12284 struct mlx5_ifc_tls_static_params_bits { 12285 u8 const_2[0x2]; 12286 u8 tls_version[0x4]; 12287 u8 const_1[0x2]; 12288 u8 reserved_at_8[0x14]; 12289 u8 encryption_standard[0x4]; 12290 12291 u8 reserved_at_20[0x20]; 12292 12293 u8 initial_record_number[0x40]; 12294 12295 u8 resync_tcp_sn[0x20]; 12296 12297 u8 gcm_iv[0x20]; 12298 12299 u8 implicit_iv[0x40]; 12300 12301 u8 reserved_at_100[0x8]; 12302 u8 dek_index[0x18]; 12303 12304 u8 reserved_at_120[0xe0]; 12305 }; 12306 12307 struct mlx5_ifc_tls_progress_params_bits { 12308 u8 next_record_tcp_sn[0x20]; 12309 12310 u8 hw_resync_tcp_sn[0x20]; 12311 12312 u8 record_tracker_state[0x2]; 12313 u8 auth_state[0x2]; 12314 u8 reserved_at_44[0x4]; 12315 u8 hw_offset_record_number[0x18]; 12316 }; 12317 12318 enum { 12319 MLX5_MTT_PERM_READ = 1 << 0, 12320 MLX5_MTT_PERM_WRITE = 1 << 1, 12321 MLX5_MTT_PERM_RW = MLX5_MTT_PERM_READ | MLX5_MTT_PERM_WRITE, 12322 }; 12323 12324 enum { 12325 MLX5_SUSPEND_VHCA_IN_OP_MOD_SUSPEND_INITIATOR = 0x0, 12326 MLX5_SUSPEND_VHCA_IN_OP_MOD_SUSPEND_RESPONDER = 0x1, 12327 }; 12328 12329 struct mlx5_ifc_suspend_vhca_in_bits { 12330 u8 opcode[0x10]; 12331 u8 uid[0x10]; 12332 12333 u8 reserved_at_20[0x10]; 12334 u8 op_mod[0x10]; 12335 12336 u8 reserved_at_40[0x10]; 12337 u8 vhca_id[0x10]; 12338 12339 u8 reserved_at_60[0x20]; 12340 }; 12341 12342 struct mlx5_ifc_suspend_vhca_out_bits { 12343 u8 status[0x8]; 12344 u8 reserved_at_8[0x18]; 12345 12346 u8 syndrome[0x20]; 12347 12348 u8 reserved_at_40[0x40]; 12349 }; 12350 12351 enum { 12352 MLX5_RESUME_VHCA_IN_OP_MOD_RESUME_RESPONDER = 0x0, 12353 MLX5_RESUME_VHCA_IN_OP_MOD_RESUME_INITIATOR = 0x1, 12354 }; 12355 12356 struct mlx5_ifc_resume_vhca_in_bits { 12357 u8 opcode[0x10]; 12358 u8 uid[0x10]; 12359 12360 u8 reserved_at_20[0x10]; 12361 u8 op_mod[0x10]; 12362 12363 u8 reserved_at_40[0x10]; 12364 u8 vhca_id[0x10]; 12365 12366 u8 reserved_at_60[0x20]; 12367 }; 12368 12369 struct mlx5_ifc_resume_vhca_out_bits { 12370 u8 status[0x8]; 12371 u8 reserved_at_8[0x18]; 12372 12373 u8 syndrome[0x20]; 12374 12375 u8 reserved_at_40[0x40]; 12376 }; 12377 12378 struct mlx5_ifc_query_vhca_migration_state_in_bits { 12379 u8 opcode[0x10]; 12380 u8 uid[0x10]; 12381 12382 u8 reserved_at_20[0x10]; 12383 u8 op_mod[0x10]; 12384 12385 u8 incremental[0x1]; 12386 u8 reserved_at_41[0xf]; 12387 u8 vhca_id[0x10]; 12388 12389 u8 reserved_at_60[0x20]; 12390 }; 12391 12392 struct mlx5_ifc_query_vhca_migration_state_out_bits { 12393 u8 status[0x8]; 12394 u8 reserved_at_8[0x18]; 12395 12396 u8 syndrome[0x20]; 12397 12398 u8 reserved_at_40[0x40]; 12399 12400 u8 required_umem_size[0x20]; 12401 12402 u8 reserved_at_a0[0x160]; 12403 }; 12404 12405 struct mlx5_ifc_save_vhca_state_in_bits { 12406 u8 opcode[0x10]; 12407 u8 uid[0x10]; 12408 12409 u8 reserved_at_20[0x10]; 12410 u8 op_mod[0x10]; 12411 12412 u8 incremental[0x1]; 12413 u8 set_track[0x1]; 12414 u8 reserved_at_42[0xe]; 12415 u8 vhca_id[0x10]; 12416 12417 u8 reserved_at_60[0x20]; 12418 12419 u8 va[0x40]; 12420 12421 u8 mkey[0x20]; 12422 12423 u8 size[0x20]; 12424 }; 12425 12426 struct mlx5_ifc_save_vhca_state_out_bits { 12427 u8 status[0x8]; 12428 u8 reserved_at_8[0x18]; 12429 12430 u8 syndrome[0x20]; 12431 12432 u8 actual_image_size[0x20]; 12433 12434 u8 reserved_at_60[0x20]; 12435 }; 12436 12437 struct mlx5_ifc_load_vhca_state_in_bits { 12438 u8 opcode[0x10]; 12439 u8 uid[0x10]; 12440 12441 u8 reserved_at_20[0x10]; 12442 u8 op_mod[0x10]; 12443 12444 u8 reserved_at_40[0x10]; 12445 u8 vhca_id[0x10]; 12446 12447 u8 reserved_at_60[0x20]; 12448 12449 u8 va[0x40]; 12450 12451 u8 mkey[0x20]; 12452 12453 u8 size[0x20]; 12454 }; 12455 12456 struct mlx5_ifc_load_vhca_state_out_bits { 12457 u8 status[0x8]; 12458 u8 reserved_at_8[0x18]; 12459 12460 u8 syndrome[0x20]; 12461 12462 u8 reserved_at_40[0x40]; 12463 }; 12464 12465 struct mlx5_ifc_adv_virtualization_cap_bits { 12466 u8 reserved_at_0[0x3]; 12467 u8 pg_track_log_max_num[0x5]; 12468 u8 pg_track_max_num_range[0x8]; 12469 u8 pg_track_log_min_addr_space[0x8]; 12470 u8 pg_track_log_max_addr_space[0x8]; 12471 12472 u8 reserved_at_20[0x3]; 12473 u8 pg_track_log_min_msg_size[0x5]; 12474 u8 reserved_at_28[0x3]; 12475 u8 pg_track_log_max_msg_size[0x5]; 12476 u8 reserved_at_30[0x3]; 12477 u8 pg_track_log_min_page_size[0x5]; 12478 u8 reserved_at_38[0x3]; 12479 u8 pg_track_log_max_page_size[0x5]; 12480 12481 u8 reserved_at_40[0x7c0]; 12482 }; 12483 12484 struct mlx5_ifc_page_track_report_entry_bits { 12485 u8 dirty_address_high[0x20]; 12486 12487 u8 dirty_address_low[0x20]; 12488 }; 12489 12490 enum { 12491 MLX5_PAGE_TRACK_STATE_TRACKING, 12492 MLX5_PAGE_TRACK_STATE_REPORTING, 12493 MLX5_PAGE_TRACK_STATE_ERROR, 12494 }; 12495 12496 struct mlx5_ifc_page_track_range_bits { 12497 u8 start_address[0x40]; 12498 12499 u8 length[0x40]; 12500 }; 12501 12502 struct mlx5_ifc_page_track_bits { 12503 u8 modify_field_select[0x40]; 12504 12505 u8 reserved_at_40[0x10]; 12506 u8 vhca_id[0x10]; 12507 12508 u8 reserved_at_60[0x20]; 12509 12510 u8 state[0x4]; 12511 u8 track_type[0x4]; 12512 u8 log_addr_space_size[0x8]; 12513 u8 reserved_at_90[0x3]; 12514 u8 log_page_size[0x5]; 12515 u8 reserved_at_98[0x3]; 12516 u8 log_msg_size[0x5]; 12517 12518 u8 reserved_at_a0[0x8]; 12519 u8 reporting_qpn[0x18]; 12520 12521 u8 reserved_at_c0[0x18]; 12522 u8 num_ranges[0x8]; 12523 12524 u8 reserved_at_e0[0x20]; 12525 12526 u8 range_start_address[0x40]; 12527 12528 u8 length[0x40]; 12529 12530 struct mlx5_ifc_page_track_range_bits track_range[0]; 12531 }; 12532 12533 struct mlx5_ifc_create_page_track_obj_in_bits { 12534 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12535 struct mlx5_ifc_page_track_bits obj_context; 12536 }; 12537 12538 struct mlx5_ifc_modify_page_track_obj_in_bits { 12539 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12540 struct mlx5_ifc_page_track_bits obj_context; 12541 }; 12542 12543 #endif /* MLX5_IFC_H */ 12544