1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 #ifndef MLX5_IFC_H 33 #define MLX5_IFC_H 34 35 #include "mlx5_ifc_fpga.h" 36 37 enum { 38 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0, 39 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1, 40 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2, 41 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3, 42 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13, 43 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14, 44 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c, 45 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d, 46 MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4, 47 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5, 48 MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED = 0x7, 49 MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT = 0xc, 50 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10, 51 MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR = 0x11, 52 MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR = 0x12, 53 MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR = 0x8, 54 MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE = 0x9, 55 MLX5_EVENT_TYPE_CODING_GPIO_EVENT = 0x15, 56 MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19, 57 MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a, 58 MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT = 0x1b, 59 MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT = 0x1f, 60 MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa, 61 MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb, 62 MLX5_EVENT_TYPE_CODING_FPGA_ERROR = 0x20, 63 }; 64 65 enum { 66 MLX5_MODIFY_TIR_BITMASK_LRO = 0x0, 67 MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE = 0x1, 68 MLX5_MODIFY_TIR_BITMASK_HASH = 0x2, 69 MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN = 0x3 70 }; 71 72 enum { 73 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0, 74 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3, 75 }; 76 77 enum { 78 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100, 79 MLX5_CMD_OP_QUERY_ADAPTER = 0x101, 80 MLX5_CMD_OP_INIT_HCA = 0x102, 81 MLX5_CMD_OP_TEARDOWN_HCA = 0x103, 82 MLX5_CMD_OP_ENABLE_HCA = 0x104, 83 MLX5_CMD_OP_DISABLE_HCA = 0x105, 84 MLX5_CMD_OP_QUERY_PAGES = 0x107, 85 MLX5_CMD_OP_MANAGE_PAGES = 0x108, 86 MLX5_CMD_OP_SET_HCA_CAP = 0x109, 87 MLX5_CMD_OP_QUERY_ISSI = 0x10a, 88 MLX5_CMD_OP_SET_ISSI = 0x10b, 89 MLX5_CMD_OP_SET_DRIVER_VERSION = 0x10d, 90 MLX5_CMD_OP_CREATE_MKEY = 0x200, 91 MLX5_CMD_OP_QUERY_MKEY = 0x201, 92 MLX5_CMD_OP_DESTROY_MKEY = 0x202, 93 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203, 94 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204, 95 MLX5_CMD_OP_ALLOC_MEMIC = 0x205, 96 MLX5_CMD_OP_DEALLOC_MEMIC = 0x206, 97 MLX5_CMD_OP_CREATE_EQ = 0x301, 98 MLX5_CMD_OP_DESTROY_EQ = 0x302, 99 MLX5_CMD_OP_QUERY_EQ = 0x303, 100 MLX5_CMD_OP_GEN_EQE = 0x304, 101 MLX5_CMD_OP_CREATE_CQ = 0x400, 102 MLX5_CMD_OP_DESTROY_CQ = 0x401, 103 MLX5_CMD_OP_QUERY_CQ = 0x402, 104 MLX5_CMD_OP_MODIFY_CQ = 0x403, 105 MLX5_CMD_OP_CREATE_QP = 0x500, 106 MLX5_CMD_OP_DESTROY_QP = 0x501, 107 MLX5_CMD_OP_RST2INIT_QP = 0x502, 108 MLX5_CMD_OP_INIT2RTR_QP = 0x503, 109 MLX5_CMD_OP_RTR2RTS_QP = 0x504, 110 MLX5_CMD_OP_RTS2RTS_QP = 0x505, 111 MLX5_CMD_OP_SQERR2RTS_QP = 0x506, 112 MLX5_CMD_OP_2ERR_QP = 0x507, 113 MLX5_CMD_OP_2RST_QP = 0x50a, 114 MLX5_CMD_OP_QUERY_QP = 0x50b, 115 MLX5_CMD_OP_SQD_RTS_QP = 0x50c, 116 MLX5_CMD_OP_INIT2INIT_QP = 0x50e, 117 MLX5_CMD_OP_CREATE_PSV = 0x600, 118 MLX5_CMD_OP_DESTROY_PSV = 0x601, 119 MLX5_CMD_OP_CREATE_SRQ = 0x700, 120 MLX5_CMD_OP_DESTROY_SRQ = 0x701, 121 MLX5_CMD_OP_QUERY_SRQ = 0x702, 122 MLX5_CMD_OP_ARM_RQ = 0x703, 123 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705, 124 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706, 125 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707, 126 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708, 127 MLX5_CMD_OP_CREATE_DCT = 0x710, 128 MLX5_CMD_OP_DESTROY_DCT = 0x711, 129 MLX5_CMD_OP_DRAIN_DCT = 0x712, 130 MLX5_CMD_OP_QUERY_DCT = 0x713, 131 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714, 132 MLX5_CMD_OP_CREATE_XRQ = 0x717, 133 MLX5_CMD_OP_DESTROY_XRQ = 0x718, 134 MLX5_CMD_OP_QUERY_XRQ = 0x719, 135 MLX5_CMD_OP_ARM_XRQ = 0x71a, 136 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750, 137 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751, 138 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752, 139 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753, 140 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754, 141 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755, 142 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760, 143 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761, 144 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762, 145 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763, 146 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764, 147 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765, 148 MLX5_CMD_OP_QUERY_VNIC_ENV = 0x76f, 149 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770, 150 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771, 151 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772, 152 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773, 153 MLX5_CMD_OP_SET_PP_RATE_LIMIT = 0x780, 154 MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781, 155 MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT = 0x782, 156 MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT = 0x783, 157 MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT = 0x784, 158 MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT = 0x785, 159 MLX5_CMD_OP_CREATE_QOS_PARA_VPORT = 0x786, 160 MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT = 0x787, 161 MLX5_CMD_OP_ALLOC_PD = 0x800, 162 MLX5_CMD_OP_DEALLOC_PD = 0x801, 163 MLX5_CMD_OP_ALLOC_UAR = 0x802, 164 MLX5_CMD_OP_DEALLOC_UAR = 0x803, 165 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804, 166 MLX5_CMD_OP_ACCESS_REG = 0x805, 167 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806, 168 MLX5_CMD_OP_DETACH_FROM_MCG = 0x807, 169 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a, 170 MLX5_CMD_OP_MAD_IFC = 0x50d, 171 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b, 172 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c, 173 MLX5_CMD_OP_NOP = 0x80d, 174 MLX5_CMD_OP_ALLOC_XRCD = 0x80e, 175 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f, 176 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816, 177 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817, 178 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822, 179 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823, 180 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824, 181 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825, 182 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826, 183 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827, 184 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828, 185 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829, 186 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a, 187 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b, 188 MLX5_CMD_OP_SET_WOL_ROL = 0x830, 189 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831, 190 MLX5_CMD_OP_CREATE_LAG = 0x840, 191 MLX5_CMD_OP_MODIFY_LAG = 0x841, 192 MLX5_CMD_OP_QUERY_LAG = 0x842, 193 MLX5_CMD_OP_DESTROY_LAG = 0x843, 194 MLX5_CMD_OP_CREATE_VPORT_LAG = 0x844, 195 MLX5_CMD_OP_DESTROY_VPORT_LAG = 0x845, 196 MLX5_CMD_OP_CREATE_TIR = 0x900, 197 MLX5_CMD_OP_MODIFY_TIR = 0x901, 198 MLX5_CMD_OP_DESTROY_TIR = 0x902, 199 MLX5_CMD_OP_QUERY_TIR = 0x903, 200 MLX5_CMD_OP_CREATE_SQ = 0x904, 201 MLX5_CMD_OP_MODIFY_SQ = 0x905, 202 MLX5_CMD_OP_DESTROY_SQ = 0x906, 203 MLX5_CMD_OP_QUERY_SQ = 0x907, 204 MLX5_CMD_OP_CREATE_RQ = 0x908, 205 MLX5_CMD_OP_MODIFY_RQ = 0x909, 206 MLX5_CMD_OP_SET_DELAY_DROP_PARAMS = 0x910, 207 MLX5_CMD_OP_DESTROY_RQ = 0x90a, 208 MLX5_CMD_OP_QUERY_RQ = 0x90b, 209 MLX5_CMD_OP_CREATE_RMP = 0x90c, 210 MLX5_CMD_OP_MODIFY_RMP = 0x90d, 211 MLX5_CMD_OP_DESTROY_RMP = 0x90e, 212 MLX5_CMD_OP_QUERY_RMP = 0x90f, 213 MLX5_CMD_OP_CREATE_TIS = 0x912, 214 MLX5_CMD_OP_MODIFY_TIS = 0x913, 215 MLX5_CMD_OP_DESTROY_TIS = 0x914, 216 MLX5_CMD_OP_QUERY_TIS = 0x915, 217 MLX5_CMD_OP_CREATE_RQT = 0x916, 218 MLX5_CMD_OP_MODIFY_RQT = 0x917, 219 MLX5_CMD_OP_DESTROY_RQT = 0x918, 220 MLX5_CMD_OP_QUERY_RQT = 0x919, 221 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f, 222 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930, 223 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931, 224 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932, 225 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933, 226 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934, 227 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935, 228 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936, 229 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937, 230 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938, 231 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939, 232 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a, 233 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b, 234 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c, 235 MLX5_CMD_OP_ALLOC_ENCAP_HEADER = 0x93d, 236 MLX5_CMD_OP_DEALLOC_ENCAP_HEADER = 0x93e, 237 MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT = 0x940, 238 MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941, 239 MLX5_CMD_OP_FPGA_CREATE_QP = 0x960, 240 MLX5_CMD_OP_FPGA_MODIFY_QP = 0x961, 241 MLX5_CMD_OP_FPGA_QUERY_QP = 0x962, 242 MLX5_CMD_OP_FPGA_DESTROY_QP = 0x963, 243 MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS = 0x964, 244 MLX5_CMD_OP_MAX 245 }; 246 247 struct mlx5_ifc_flow_table_fields_supported_bits { 248 u8 outer_dmac[0x1]; 249 u8 outer_smac[0x1]; 250 u8 outer_ether_type[0x1]; 251 u8 outer_ip_version[0x1]; 252 u8 outer_first_prio[0x1]; 253 u8 outer_first_cfi[0x1]; 254 u8 outer_first_vid[0x1]; 255 u8 outer_ipv4_ttl[0x1]; 256 u8 outer_second_prio[0x1]; 257 u8 outer_second_cfi[0x1]; 258 u8 outer_second_vid[0x1]; 259 u8 reserved_at_b[0x1]; 260 u8 outer_sip[0x1]; 261 u8 outer_dip[0x1]; 262 u8 outer_frag[0x1]; 263 u8 outer_ip_protocol[0x1]; 264 u8 outer_ip_ecn[0x1]; 265 u8 outer_ip_dscp[0x1]; 266 u8 outer_udp_sport[0x1]; 267 u8 outer_udp_dport[0x1]; 268 u8 outer_tcp_sport[0x1]; 269 u8 outer_tcp_dport[0x1]; 270 u8 outer_tcp_flags[0x1]; 271 u8 outer_gre_protocol[0x1]; 272 u8 outer_gre_key[0x1]; 273 u8 outer_vxlan_vni[0x1]; 274 u8 reserved_at_1a[0x5]; 275 u8 source_eswitch_port[0x1]; 276 277 u8 inner_dmac[0x1]; 278 u8 inner_smac[0x1]; 279 u8 inner_ether_type[0x1]; 280 u8 inner_ip_version[0x1]; 281 u8 inner_first_prio[0x1]; 282 u8 inner_first_cfi[0x1]; 283 u8 inner_first_vid[0x1]; 284 u8 reserved_at_27[0x1]; 285 u8 inner_second_prio[0x1]; 286 u8 inner_second_cfi[0x1]; 287 u8 inner_second_vid[0x1]; 288 u8 reserved_at_2b[0x1]; 289 u8 inner_sip[0x1]; 290 u8 inner_dip[0x1]; 291 u8 inner_frag[0x1]; 292 u8 inner_ip_protocol[0x1]; 293 u8 inner_ip_ecn[0x1]; 294 u8 inner_ip_dscp[0x1]; 295 u8 inner_udp_sport[0x1]; 296 u8 inner_udp_dport[0x1]; 297 u8 inner_tcp_sport[0x1]; 298 u8 inner_tcp_dport[0x1]; 299 u8 inner_tcp_flags[0x1]; 300 u8 reserved_at_37[0x9]; 301 u8 reserved_at_40[0x17]; 302 u8 outer_esp_spi[0x1]; 303 u8 reserved_at_58[0x2]; 304 u8 bth_dst_qp[0x1]; 305 306 u8 reserved_at_5b[0x25]; 307 }; 308 309 struct mlx5_ifc_flow_table_prop_layout_bits { 310 u8 ft_support[0x1]; 311 u8 reserved_at_1[0x1]; 312 u8 flow_counter[0x1]; 313 u8 flow_modify_en[0x1]; 314 u8 modify_root[0x1]; 315 u8 identified_miss_table_mode[0x1]; 316 u8 flow_table_modify[0x1]; 317 u8 encap[0x1]; 318 u8 decap[0x1]; 319 u8 reserved_at_9[0x1]; 320 u8 pop_vlan[0x1]; 321 u8 push_vlan[0x1]; 322 u8 reserved_at_c[0x14]; 323 324 u8 reserved_at_20[0x2]; 325 u8 log_max_ft_size[0x6]; 326 u8 log_max_modify_header_context[0x8]; 327 u8 max_modify_header_actions[0x8]; 328 u8 max_ft_level[0x8]; 329 330 u8 reserved_at_40[0x20]; 331 332 u8 reserved_at_60[0x18]; 333 u8 log_max_ft_num[0x8]; 334 335 u8 reserved_at_80[0x18]; 336 u8 log_max_destination[0x8]; 337 338 u8 log_max_flow_counter[0x8]; 339 u8 reserved_at_a8[0x10]; 340 u8 log_max_flow[0x8]; 341 342 u8 reserved_at_c0[0x40]; 343 344 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support; 345 346 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support; 347 }; 348 349 struct mlx5_ifc_odp_per_transport_service_cap_bits { 350 u8 send[0x1]; 351 u8 receive[0x1]; 352 u8 write[0x1]; 353 u8 read[0x1]; 354 u8 atomic[0x1]; 355 u8 srq_receive[0x1]; 356 u8 reserved_at_6[0x1a]; 357 }; 358 359 struct mlx5_ifc_fte_match_set_lyr_2_4_bits { 360 u8 smac_47_16[0x20]; 361 362 u8 smac_15_0[0x10]; 363 u8 ethertype[0x10]; 364 365 u8 dmac_47_16[0x20]; 366 367 u8 dmac_15_0[0x10]; 368 u8 first_prio[0x3]; 369 u8 first_cfi[0x1]; 370 u8 first_vid[0xc]; 371 372 u8 ip_protocol[0x8]; 373 u8 ip_dscp[0x6]; 374 u8 ip_ecn[0x2]; 375 u8 cvlan_tag[0x1]; 376 u8 svlan_tag[0x1]; 377 u8 frag[0x1]; 378 u8 ip_version[0x4]; 379 u8 tcp_flags[0x9]; 380 381 u8 tcp_sport[0x10]; 382 u8 tcp_dport[0x10]; 383 384 u8 reserved_at_c0[0x18]; 385 u8 ttl_hoplimit[0x8]; 386 387 u8 udp_sport[0x10]; 388 u8 udp_dport[0x10]; 389 390 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6; 391 392 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6; 393 }; 394 395 struct mlx5_ifc_fte_match_set_misc_bits { 396 u8 reserved_at_0[0x8]; 397 u8 source_sqn[0x18]; 398 399 u8 reserved_at_20[0x10]; 400 u8 source_port[0x10]; 401 402 u8 outer_second_prio[0x3]; 403 u8 outer_second_cfi[0x1]; 404 u8 outer_second_vid[0xc]; 405 u8 inner_second_prio[0x3]; 406 u8 inner_second_cfi[0x1]; 407 u8 inner_second_vid[0xc]; 408 409 u8 outer_second_cvlan_tag[0x1]; 410 u8 inner_second_cvlan_tag[0x1]; 411 u8 outer_second_svlan_tag[0x1]; 412 u8 inner_second_svlan_tag[0x1]; 413 u8 reserved_at_64[0xc]; 414 u8 gre_protocol[0x10]; 415 416 u8 gre_key_h[0x18]; 417 u8 gre_key_l[0x8]; 418 419 u8 vxlan_vni[0x18]; 420 u8 reserved_at_b8[0x8]; 421 422 u8 reserved_at_c0[0x20]; 423 424 u8 reserved_at_e0[0xc]; 425 u8 outer_ipv6_flow_label[0x14]; 426 427 u8 reserved_at_100[0xc]; 428 u8 inner_ipv6_flow_label[0x14]; 429 430 u8 reserved_at_120[0x28]; 431 u8 bth_dst_qp[0x18]; 432 u8 reserved_at_160[0x20]; 433 u8 outer_esp_spi[0x20]; 434 u8 reserved_at_1a0[0x60]; 435 }; 436 437 struct mlx5_ifc_cmd_pas_bits { 438 u8 pa_h[0x20]; 439 440 u8 pa_l[0x14]; 441 u8 reserved_at_34[0xc]; 442 }; 443 444 struct mlx5_ifc_uint64_bits { 445 u8 hi[0x20]; 446 447 u8 lo[0x20]; 448 }; 449 450 enum { 451 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0, 452 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7, 453 MLX5_ADS_STAT_RATE_10GBPS = 0x8, 454 MLX5_ADS_STAT_RATE_30GBPS = 0x9, 455 MLX5_ADS_STAT_RATE_5GBPS = 0xa, 456 MLX5_ADS_STAT_RATE_20GBPS = 0xb, 457 MLX5_ADS_STAT_RATE_40GBPS = 0xc, 458 MLX5_ADS_STAT_RATE_60GBPS = 0xd, 459 MLX5_ADS_STAT_RATE_80GBPS = 0xe, 460 MLX5_ADS_STAT_RATE_120GBPS = 0xf, 461 }; 462 463 struct mlx5_ifc_ads_bits { 464 u8 fl[0x1]; 465 u8 free_ar[0x1]; 466 u8 reserved_at_2[0xe]; 467 u8 pkey_index[0x10]; 468 469 u8 reserved_at_20[0x8]; 470 u8 grh[0x1]; 471 u8 mlid[0x7]; 472 u8 rlid[0x10]; 473 474 u8 ack_timeout[0x5]; 475 u8 reserved_at_45[0x3]; 476 u8 src_addr_index[0x8]; 477 u8 reserved_at_50[0x4]; 478 u8 stat_rate[0x4]; 479 u8 hop_limit[0x8]; 480 481 u8 reserved_at_60[0x4]; 482 u8 tclass[0x8]; 483 u8 flow_label[0x14]; 484 485 u8 rgid_rip[16][0x8]; 486 487 u8 reserved_at_100[0x4]; 488 u8 f_dscp[0x1]; 489 u8 f_ecn[0x1]; 490 u8 reserved_at_106[0x1]; 491 u8 f_eth_prio[0x1]; 492 u8 ecn[0x2]; 493 u8 dscp[0x6]; 494 u8 udp_sport[0x10]; 495 496 u8 dei_cfi[0x1]; 497 u8 eth_prio[0x3]; 498 u8 sl[0x4]; 499 u8 vhca_port_num[0x8]; 500 u8 rmac_47_32[0x10]; 501 502 u8 rmac_31_0[0x20]; 503 }; 504 505 struct mlx5_ifc_flow_table_nic_cap_bits { 506 u8 nic_rx_multi_path_tirs[0x1]; 507 u8 nic_rx_multi_path_tirs_fts[0x1]; 508 u8 allow_sniffer_and_nic_rx_shared_tir[0x1]; 509 u8 reserved_at_3[0x1fd]; 510 511 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive; 512 513 u8 reserved_at_400[0x200]; 514 515 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer; 516 517 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit; 518 519 u8 reserved_at_a00[0x200]; 520 521 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer; 522 523 u8 reserved_at_e00[0x7200]; 524 }; 525 526 struct mlx5_ifc_flow_table_eswitch_cap_bits { 527 u8 reserved_at_0[0x200]; 528 529 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb; 530 531 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress; 532 533 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress; 534 535 u8 reserved_at_800[0x7800]; 536 }; 537 538 struct mlx5_ifc_e_switch_cap_bits { 539 u8 vport_svlan_strip[0x1]; 540 u8 vport_cvlan_strip[0x1]; 541 u8 vport_svlan_insert[0x1]; 542 u8 vport_cvlan_insert_if_not_exist[0x1]; 543 u8 vport_cvlan_insert_overwrite[0x1]; 544 u8 reserved_at_5[0x19]; 545 u8 nic_vport_node_guid_modify[0x1]; 546 u8 nic_vport_port_guid_modify[0x1]; 547 548 u8 vxlan_encap_decap[0x1]; 549 u8 nvgre_encap_decap[0x1]; 550 u8 reserved_at_22[0x9]; 551 u8 log_max_encap_headers[0x5]; 552 u8 reserved_2b[0x6]; 553 u8 max_encap_header_size[0xa]; 554 555 u8 reserved_40[0x7c0]; 556 557 }; 558 559 struct mlx5_ifc_qos_cap_bits { 560 u8 packet_pacing[0x1]; 561 u8 esw_scheduling[0x1]; 562 u8 esw_bw_share[0x1]; 563 u8 esw_rate_limit[0x1]; 564 u8 reserved_at_4[0x1]; 565 u8 packet_pacing_burst_bound[0x1]; 566 u8 packet_pacing_typical_size[0x1]; 567 u8 reserved_at_7[0x19]; 568 569 u8 reserved_at_20[0x20]; 570 571 u8 packet_pacing_max_rate[0x20]; 572 573 u8 packet_pacing_min_rate[0x20]; 574 575 u8 reserved_at_80[0x10]; 576 u8 packet_pacing_rate_table_size[0x10]; 577 578 u8 esw_element_type[0x10]; 579 u8 esw_tsar_type[0x10]; 580 581 u8 reserved_at_c0[0x10]; 582 u8 max_qos_para_vport[0x10]; 583 584 u8 max_tsar_bw_share[0x20]; 585 586 u8 reserved_at_100[0x700]; 587 }; 588 589 struct mlx5_ifc_debug_cap_bits { 590 u8 reserved_at_0[0x20]; 591 592 u8 reserved_at_20[0x2]; 593 u8 stall_detect[0x1]; 594 u8 reserved_at_23[0x1d]; 595 596 u8 reserved_at_40[0x7c0]; 597 }; 598 599 struct mlx5_ifc_per_protocol_networking_offload_caps_bits { 600 u8 csum_cap[0x1]; 601 u8 vlan_cap[0x1]; 602 u8 lro_cap[0x1]; 603 u8 lro_psh_flag[0x1]; 604 u8 lro_time_stamp[0x1]; 605 u8 reserved_at_5[0x2]; 606 u8 wqe_vlan_insert[0x1]; 607 u8 self_lb_en_modifiable[0x1]; 608 u8 reserved_at_9[0x2]; 609 u8 max_lso_cap[0x5]; 610 u8 multi_pkt_send_wqe[0x2]; 611 u8 wqe_inline_mode[0x2]; 612 u8 rss_ind_tbl_cap[0x4]; 613 u8 reg_umr_sq[0x1]; 614 u8 scatter_fcs[0x1]; 615 u8 enhanced_multi_pkt_send_wqe[0x1]; 616 u8 tunnel_lso_const_out_ip_id[0x1]; 617 u8 reserved_at_1c[0x2]; 618 u8 tunnel_stateless_gre[0x1]; 619 u8 tunnel_stateless_vxlan[0x1]; 620 621 u8 swp[0x1]; 622 u8 swp_csum[0x1]; 623 u8 swp_lso[0x1]; 624 u8 reserved_at_23[0x1b]; 625 u8 max_geneve_opt_len[0x1]; 626 u8 tunnel_stateless_geneve_rx[0x1]; 627 628 u8 reserved_at_40[0x10]; 629 u8 lro_min_mss_size[0x10]; 630 631 u8 reserved_at_60[0x120]; 632 633 u8 lro_timer_supported_periods[4][0x20]; 634 635 u8 reserved_at_200[0x600]; 636 }; 637 638 struct mlx5_ifc_roce_cap_bits { 639 u8 roce_apm[0x1]; 640 u8 reserved_at_1[0x1f]; 641 642 u8 reserved_at_20[0x60]; 643 644 u8 reserved_at_80[0xc]; 645 u8 l3_type[0x4]; 646 u8 reserved_at_90[0x8]; 647 u8 roce_version[0x8]; 648 649 u8 reserved_at_a0[0x10]; 650 u8 r_roce_dest_udp_port[0x10]; 651 652 u8 r_roce_max_src_udp_port[0x10]; 653 u8 r_roce_min_src_udp_port[0x10]; 654 655 u8 reserved_at_e0[0x10]; 656 u8 roce_address_table_size[0x10]; 657 658 u8 reserved_at_100[0x700]; 659 }; 660 661 struct mlx5_ifc_device_mem_cap_bits { 662 u8 memic[0x1]; 663 u8 reserved_at_1[0x1f]; 664 665 u8 reserved_at_20[0xb]; 666 u8 log_min_memic_alloc_size[0x5]; 667 u8 reserved_at_30[0x8]; 668 u8 log_max_memic_addr_alignment[0x8]; 669 670 u8 memic_bar_start_addr[0x40]; 671 672 u8 memic_bar_size[0x20]; 673 674 u8 max_memic_size[0x20]; 675 676 u8 reserved_at_c0[0x740]; 677 }; 678 679 enum { 680 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0, 681 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2, 682 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4, 683 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8, 684 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10, 685 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20, 686 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40, 687 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80, 688 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100, 689 }; 690 691 enum { 692 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1, 693 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2, 694 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4, 695 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8, 696 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10, 697 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20, 698 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40, 699 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80, 700 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100, 701 }; 702 703 struct mlx5_ifc_atomic_caps_bits { 704 u8 reserved_at_0[0x40]; 705 706 u8 atomic_req_8B_endianness_mode[0x2]; 707 u8 reserved_at_42[0x4]; 708 u8 supported_atomic_req_8B_endianness_mode_1[0x1]; 709 710 u8 reserved_at_47[0x19]; 711 712 u8 reserved_at_60[0x20]; 713 714 u8 reserved_at_80[0x10]; 715 u8 atomic_operations[0x10]; 716 717 u8 reserved_at_a0[0x10]; 718 u8 atomic_size_qp[0x10]; 719 720 u8 reserved_at_c0[0x10]; 721 u8 atomic_size_dc[0x10]; 722 723 u8 reserved_at_e0[0x720]; 724 }; 725 726 struct mlx5_ifc_odp_cap_bits { 727 u8 reserved_at_0[0x40]; 728 729 u8 sig[0x1]; 730 u8 reserved_at_41[0x1f]; 731 732 u8 reserved_at_60[0x20]; 733 734 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps; 735 736 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps; 737 738 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps; 739 740 u8 reserved_at_e0[0x720]; 741 }; 742 743 struct mlx5_ifc_calc_op { 744 u8 reserved_at_0[0x10]; 745 u8 reserved_at_10[0x9]; 746 u8 op_swap_endianness[0x1]; 747 u8 op_min[0x1]; 748 u8 op_xor[0x1]; 749 u8 op_or[0x1]; 750 u8 op_and[0x1]; 751 u8 op_max[0x1]; 752 u8 op_add[0x1]; 753 }; 754 755 struct mlx5_ifc_vector_calc_cap_bits { 756 u8 calc_matrix[0x1]; 757 u8 reserved_at_1[0x1f]; 758 u8 reserved_at_20[0x8]; 759 u8 max_vec_count[0x8]; 760 u8 reserved_at_30[0xd]; 761 u8 max_chunk_size[0x3]; 762 struct mlx5_ifc_calc_op calc0; 763 struct mlx5_ifc_calc_op calc1; 764 struct mlx5_ifc_calc_op calc2; 765 struct mlx5_ifc_calc_op calc3; 766 767 u8 reserved_at_e0[0x720]; 768 }; 769 770 enum { 771 MLX5_WQ_TYPE_LINKED_LIST = 0x0, 772 MLX5_WQ_TYPE_CYCLIC = 0x1, 773 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2, 774 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3, 775 }; 776 777 enum { 778 MLX5_WQ_END_PAD_MODE_NONE = 0x0, 779 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1, 780 }; 781 782 enum { 783 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0, 784 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1, 785 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2, 786 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3, 787 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4, 788 }; 789 790 enum { 791 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0, 792 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1, 793 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2, 794 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3, 795 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4, 796 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5, 797 }; 798 799 enum { 800 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0, 801 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1, 802 }; 803 804 enum { 805 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0, 806 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1, 807 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3, 808 }; 809 810 enum { 811 MLX5_CAP_PORT_TYPE_IB = 0x0, 812 MLX5_CAP_PORT_TYPE_ETH = 0x1, 813 }; 814 815 enum { 816 MLX5_CAP_UMR_FENCE_STRONG = 0x0, 817 MLX5_CAP_UMR_FENCE_SMALL = 0x1, 818 MLX5_CAP_UMR_FENCE_NONE = 0x2, 819 }; 820 821 struct mlx5_ifc_cmd_hca_cap_bits { 822 u8 reserved_at_0[0x30]; 823 u8 vhca_id[0x10]; 824 825 u8 reserved_at_40[0x40]; 826 827 u8 log_max_srq_sz[0x8]; 828 u8 log_max_qp_sz[0x8]; 829 u8 reserved_at_90[0xb]; 830 u8 log_max_qp[0x5]; 831 832 u8 reserved_at_a0[0xb]; 833 u8 log_max_srq[0x5]; 834 u8 reserved_at_b0[0x10]; 835 836 u8 reserved_at_c0[0x8]; 837 u8 log_max_cq_sz[0x8]; 838 u8 reserved_at_d0[0xb]; 839 u8 log_max_cq[0x5]; 840 841 u8 log_max_eq_sz[0x8]; 842 u8 reserved_at_e8[0x2]; 843 u8 log_max_mkey[0x6]; 844 u8 reserved_at_f0[0xc]; 845 u8 log_max_eq[0x4]; 846 847 u8 max_indirection[0x8]; 848 u8 fixed_buffer_size[0x1]; 849 u8 log_max_mrw_sz[0x7]; 850 u8 force_teardown[0x1]; 851 u8 reserved_at_111[0x1]; 852 u8 log_max_bsf_list_size[0x6]; 853 u8 umr_extended_translation_offset[0x1]; 854 u8 null_mkey[0x1]; 855 u8 log_max_klm_list_size[0x6]; 856 857 u8 reserved_at_120[0xa]; 858 u8 log_max_ra_req_dc[0x6]; 859 u8 reserved_at_130[0xa]; 860 u8 log_max_ra_res_dc[0x6]; 861 862 u8 reserved_at_140[0xa]; 863 u8 log_max_ra_req_qp[0x6]; 864 u8 reserved_at_150[0xa]; 865 u8 log_max_ra_res_qp[0x6]; 866 867 u8 end_pad[0x1]; 868 u8 cc_query_allowed[0x1]; 869 u8 cc_modify_allowed[0x1]; 870 u8 start_pad[0x1]; 871 u8 cache_line_128byte[0x1]; 872 u8 reserved_at_165[0xa]; 873 u8 qcam_reg[0x1]; 874 u8 gid_table_size[0x10]; 875 876 u8 out_of_seq_cnt[0x1]; 877 u8 vport_counters[0x1]; 878 u8 retransmission_q_counters[0x1]; 879 u8 debug[0x1]; 880 u8 modify_rq_counter_set_id[0x1]; 881 u8 rq_delay_drop[0x1]; 882 u8 max_qp_cnt[0xa]; 883 u8 pkey_table_size[0x10]; 884 885 u8 vport_group_manager[0x1]; 886 u8 vhca_group_manager[0x1]; 887 u8 ib_virt[0x1]; 888 u8 eth_virt[0x1]; 889 u8 vnic_env_queue_counters[0x1]; 890 u8 ets[0x1]; 891 u8 nic_flow_table[0x1]; 892 u8 eswitch_flow_table[0x1]; 893 u8 device_memory[0x1]; 894 u8 mcam_reg[0x1]; 895 u8 pcam_reg[0x1]; 896 u8 local_ca_ack_delay[0x5]; 897 u8 port_module_event[0x1]; 898 u8 enhanced_error_q_counters[0x1]; 899 u8 ports_check[0x1]; 900 u8 reserved_at_1b3[0x1]; 901 u8 disable_link_up[0x1]; 902 u8 beacon_led[0x1]; 903 u8 port_type[0x2]; 904 u8 num_ports[0x8]; 905 906 u8 reserved_at_1c0[0x1]; 907 u8 pps[0x1]; 908 u8 pps_modify[0x1]; 909 u8 log_max_msg[0x5]; 910 u8 reserved_at_1c8[0x4]; 911 u8 max_tc[0x4]; 912 u8 reserved_at_1d0[0x1]; 913 u8 dcbx[0x1]; 914 u8 general_notification_event[0x1]; 915 u8 reserved_at_1d3[0x2]; 916 u8 fpga[0x1]; 917 u8 rol_s[0x1]; 918 u8 rol_g[0x1]; 919 u8 reserved_at_1d8[0x1]; 920 u8 wol_s[0x1]; 921 u8 wol_g[0x1]; 922 u8 wol_a[0x1]; 923 u8 wol_b[0x1]; 924 u8 wol_m[0x1]; 925 u8 wol_u[0x1]; 926 u8 wol_p[0x1]; 927 928 u8 stat_rate_support[0x10]; 929 u8 reserved_at_1f0[0xc]; 930 u8 cqe_version[0x4]; 931 932 u8 compact_address_vector[0x1]; 933 u8 striding_rq[0x1]; 934 u8 reserved_at_202[0x1]; 935 u8 ipoib_enhanced_offloads[0x1]; 936 u8 ipoib_basic_offloads[0x1]; 937 u8 reserved_at_205[0x1]; 938 u8 repeated_block_disabled[0x1]; 939 u8 umr_modify_entity_size_disabled[0x1]; 940 u8 umr_modify_atomic_disabled[0x1]; 941 u8 umr_indirect_mkey_disabled[0x1]; 942 u8 umr_fence[0x2]; 943 u8 reserved_at_20c[0x3]; 944 u8 drain_sigerr[0x1]; 945 u8 cmdif_checksum[0x2]; 946 u8 sigerr_cqe[0x1]; 947 u8 reserved_at_213[0x1]; 948 u8 wq_signature[0x1]; 949 u8 sctr_data_cqe[0x1]; 950 u8 reserved_at_216[0x1]; 951 u8 sho[0x1]; 952 u8 tph[0x1]; 953 u8 rf[0x1]; 954 u8 dct[0x1]; 955 u8 qos[0x1]; 956 u8 eth_net_offloads[0x1]; 957 u8 roce[0x1]; 958 u8 atomic[0x1]; 959 u8 reserved_at_21f[0x1]; 960 961 u8 cq_oi[0x1]; 962 u8 cq_resize[0x1]; 963 u8 cq_moderation[0x1]; 964 u8 reserved_at_223[0x3]; 965 u8 cq_eq_remap[0x1]; 966 u8 pg[0x1]; 967 u8 block_lb_mc[0x1]; 968 u8 reserved_at_229[0x1]; 969 u8 scqe_break_moderation[0x1]; 970 u8 cq_period_start_from_cqe[0x1]; 971 u8 cd[0x1]; 972 u8 reserved_at_22d[0x1]; 973 u8 apm[0x1]; 974 u8 vector_calc[0x1]; 975 u8 umr_ptr_rlky[0x1]; 976 u8 imaicl[0x1]; 977 u8 reserved_at_232[0x4]; 978 u8 qkv[0x1]; 979 u8 pkv[0x1]; 980 u8 set_deth_sqpn[0x1]; 981 u8 reserved_at_239[0x3]; 982 u8 xrc[0x1]; 983 u8 ud[0x1]; 984 u8 uc[0x1]; 985 u8 rc[0x1]; 986 987 u8 uar_4k[0x1]; 988 u8 reserved_at_241[0x9]; 989 u8 uar_sz[0x6]; 990 u8 reserved_at_250[0x8]; 991 u8 log_pg_sz[0x8]; 992 993 u8 bf[0x1]; 994 u8 driver_version[0x1]; 995 u8 pad_tx_eth_packet[0x1]; 996 u8 reserved_at_263[0x8]; 997 u8 log_bf_reg_size[0x5]; 998 999 u8 reserved_at_270[0xb]; 1000 u8 lag_master[0x1]; 1001 u8 num_lag_ports[0x4]; 1002 1003 u8 reserved_at_280[0x10]; 1004 u8 max_wqe_sz_sq[0x10]; 1005 1006 u8 reserved_at_2a0[0x10]; 1007 u8 max_wqe_sz_rq[0x10]; 1008 1009 u8 max_flow_counter_31_16[0x10]; 1010 u8 max_wqe_sz_sq_dc[0x10]; 1011 1012 u8 reserved_at_2e0[0x7]; 1013 u8 max_qp_mcg[0x19]; 1014 1015 u8 reserved_at_300[0x18]; 1016 u8 log_max_mcg[0x8]; 1017 1018 u8 reserved_at_320[0x3]; 1019 u8 log_max_transport_domain[0x5]; 1020 u8 reserved_at_328[0x3]; 1021 u8 log_max_pd[0x5]; 1022 u8 reserved_at_330[0xb]; 1023 u8 log_max_xrcd[0x5]; 1024 1025 u8 nic_receive_steering_discard[0x1]; 1026 u8 receive_discard_vport_down[0x1]; 1027 u8 transmit_discard_vport_down[0x1]; 1028 u8 reserved_at_343[0x5]; 1029 u8 log_max_flow_counter_bulk[0x8]; 1030 u8 max_flow_counter_15_0[0x10]; 1031 1032 1033 u8 reserved_at_360[0x3]; 1034 u8 log_max_rq[0x5]; 1035 u8 reserved_at_368[0x3]; 1036 u8 log_max_sq[0x5]; 1037 u8 reserved_at_370[0x3]; 1038 u8 log_max_tir[0x5]; 1039 u8 reserved_at_378[0x3]; 1040 u8 log_max_tis[0x5]; 1041 1042 u8 basic_cyclic_rcv_wqe[0x1]; 1043 u8 reserved_at_381[0x2]; 1044 u8 log_max_rmp[0x5]; 1045 u8 reserved_at_388[0x3]; 1046 u8 log_max_rqt[0x5]; 1047 u8 reserved_at_390[0x3]; 1048 u8 log_max_rqt_size[0x5]; 1049 u8 reserved_at_398[0x3]; 1050 u8 log_max_tis_per_sq[0x5]; 1051 1052 u8 ext_stride_num_range[0x1]; 1053 u8 reserved_at_3a1[0x2]; 1054 u8 log_max_stride_sz_rq[0x5]; 1055 u8 reserved_at_3a8[0x3]; 1056 u8 log_min_stride_sz_rq[0x5]; 1057 u8 reserved_at_3b0[0x3]; 1058 u8 log_max_stride_sz_sq[0x5]; 1059 u8 reserved_at_3b8[0x3]; 1060 u8 log_min_stride_sz_sq[0x5]; 1061 1062 u8 hairpin[0x1]; 1063 u8 reserved_at_3c1[0x2]; 1064 u8 log_max_hairpin_queues[0x5]; 1065 u8 reserved_at_3c8[0x3]; 1066 u8 log_max_hairpin_wq_data_sz[0x5]; 1067 u8 reserved_at_3d0[0x3]; 1068 u8 log_max_hairpin_num_packets[0x5]; 1069 u8 reserved_at_3d8[0x3]; 1070 u8 log_max_wq_sz[0x5]; 1071 1072 u8 nic_vport_change_event[0x1]; 1073 u8 disable_local_lb_uc[0x1]; 1074 u8 disable_local_lb_mc[0x1]; 1075 u8 log_min_hairpin_wq_data_sz[0x5]; 1076 u8 reserved_at_3e8[0x3]; 1077 u8 log_max_vlan_list[0x5]; 1078 u8 reserved_at_3f0[0x3]; 1079 u8 log_max_current_mc_list[0x5]; 1080 u8 reserved_at_3f8[0x3]; 1081 u8 log_max_current_uc_list[0x5]; 1082 1083 u8 reserved_at_400[0x80]; 1084 1085 u8 reserved_at_480[0x3]; 1086 u8 log_max_l2_table[0x5]; 1087 u8 reserved_at_488[0x8]; 1088 u8 log_uar_page_sz[0x10]; 1089 1090 u8 reserved_at_4a0[0x20]; 1091 u8 device_frequency_mhz[0x20]; 1092 u8 device_frequency_khz[0x20]; 1093 1094 u8 reserved_at_500[0x20]; 1095 u8 num_of_uars_per_page[0x20]; 1096 u8 reserved_at_540[0x40]; 1097 1098 u8 reserved_at_580[0x3d]; 1099 u8 cqe_128_always[0x1]; 1100 u8 cqe_compression_128[0x1]; 1101 u8 cqe_compression[0x1]; 1102 1103 u8 cqe_compression_timeout[0x10]; 1104 u8 cqe_compression_max_num[0x10]; 1105 1106 u8 reserved_at_5e0[0x10]; 1107 u8 tag_matching[0x1]; 1108 u8 rndv_offload_rc[0x1]; 1109 u8 rndv_offload_dc[0x1]; 1110 u8 log_tag_matching_list_sz[0x5]; 1111 u8 reserved_at_5f8[0x3]; 1112 u8 log_max_xrq[0x5]; 1113 1114 u8 affiliate_nic_vport_criteria[0x8]; 1115 u8 native_port_num[0x8]; 1116 u8 num_vhca_ports[0x8]; 1117 u8 reserved_at_618[0x6]; 1118 u8 sw_owner_id[0x1]; 1119 u8 reserved_at_61f[0x1e1]; 1120 }; 1121 1122 enum mlx5_flow_destination_type { 1123 MLX5_FLOW_DESTINATION_TYPE_VPORT = 0x0, 1124 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1, 1125 MLX5_FLOW_DESTINATION_TYPE_TIR = 0x2, 1126 1127 MLX5_FLOW_DESTINATION_TYPE_PORT = 0x99, 1128 MLX5_FLOW_DESTINATION_TYPE_COUNTER = 0x100, 1129 }; 1130 1131 struct mlx5_ifc_dest_format_struct_bits { 1132 u8 destination_type[0x8]; 1133 u8 destination_id[0x18]; 1134 1135 u8 reserved_at_20[0x20]; 1136 }; 1137 1138 struct mlx5_ifc_flow_counter_list_bits { 1139 u8 flow_counter_id[0x20]; 1140 1141 u8 reserved_at_20[0x20]; 1142 }; 1143 1144 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits { 1145 struct mlx5_ifc_dest_format_struct_bits dest_format_struct; 1146 struct mlx5_ifc_flow_counter_list_bits flow_counter_list; 1147 u8 reserved_at_0[0x40]; 1148 }; 1149 1150 struct mlx5_ifc_fte_match_param_bits { 1151 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers; 1152 1153 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters; 1154 1155 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers; 1156 1157 u8 reserved_at_600[0xa00]; 1158 }; 1159 1160 enum { 1161 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0, 1162 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1, 1163 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2, 1164 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3, 1165 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4, 1166 }; 1167 1168 struct mlx5_ifc_rx_hash_field_select_bits { 1169 u8 l3_prot_type[0x1]; 1170 u8 l4_prot_type[0x1]; 1171 u8 selected_fields[0x1e]; 1172 }; 1173 1174 enum { 1175 MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0, 1176 MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1, 1177 }; 1178 1179 enum { 1180 MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0, 1181 MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1, 1182 }; 1183 1184 struct mlx5_ifc_wq_bits { 1185 u8 wq_type[0x4]; 1186 u8 wq_signature[0x1]; 1187 u8 end_padding_mode[0x2]; 1188 u8 cd_slave[0x1]; 1189 u8 reserved_at_8[0x18]; 1190 1191 u8 hds_skip_first_sge[0x1]; 1192 u8 log2_hds_buf_size[0x3]; 1193 u8 reserved_at_24[0x7]; 1194 u8 page_offset[0x5]; 1195 u8 lwm[0x10]; 1196 1197 u8 reserved_at_40[0x8]; 1198 u8 pd[0x18]; 1199 1200 u8 reserved_at_60[0x8]; 1201 u8 uar_page[0x18]; 1202 1203 u8 dbr_addr[0x40]; 1204 1205 u8 hw_counter[0x20]; 1206 1207 u8 sw_counter[0x20]; 1208 1209 u8 reserved_at_100[0xc]; 1210 u8 log_wq_stride[0x4]; 1211 u8 reserved_at_110[0x3]; 1212 u8 log_wq_pg_sz[0x5]; 1213 u8 reserved_at_118[0x3]; 1214 u8 log_wq_sz[0x5]; 1215 1216 u8 reserved_at_120[0x3]; 1217 u8 log_hairpin_num_packets[0x5]; 1218 u8 reserved_at_128[0x3]; 1219 u8 log_hairpin_data_sz[0x5]; 1220 1221 u8 reserved_at_130[0x4]; 1222 u8 log_wqe_num_of_strides[0x4]; 1223 u8 two_byte_shift_en[0x1]; 1224 u8 reserved_at_139[0x4]; 1225 u8 log_wqe_stride_size[0x3]; 1226 1227 u8 reserved_at_140[0x4c0]; 1228 1229 struct mlx5_ifc_cmd_pas_bits pas[0]; 1230 }; 1231 1232 struct mlx5_ifc_rq_num_bits { 1233 u8 reserved_at_0[0x8]; 1234 u8 rq_num[0x18]; 1235 }; 1236 1237 struct mlx5_ifc_mac_address_layout_bits { 1238 u8 reserved_at_0[0x10]; 1239 u8 mac_addr_47_32[0x10]; 1240 1241 u8 mac_addr_31_0[0x20]; 1242 }; 1243 1244 struct mlx5_ifc_vlan_layout_bits { 1245 u8 reserved_at_0[0x14]; 1246 u8 vlan[0x0c]; 1247 1248 u8 reserved_at_20[0x20]; 1249 }; 1250 1251 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits { 1252 u8 reserved_at_0[0xa0]; 1253 1254 u8 min_time_between_cnps[0x20]; 1255 1256 u8 reserved_at_c0[0x12]; 1257 u8 cnp_dscp[0x6]; 1258 u8 reserved_at_d8[0x4]; 1259 u8 cnp_prio_mode[0x1]; 1260 u8 cnp_802p_prio[0x3]; 1261 1262 u8 reserved_at_e0[0x720]; 1263 }; 1264 1265 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits { 1266 u8 reserved_at_0[0x60]; 1267 1268 u8 reserved_at_60[0x4]; 1269 u8 clamp_tgt_rate[0x1]; 1270 u8 reserved_at_65[0x3]; 1271 u8 clamp_tgt_rate_after_time_inc[0x1]; 1272 u8 reserved_at_69[0x17]; 1273 1274 u8 reserved_at_80[0x20]; 1275 1276 u8 rpg_time_reset[0x20]; 1277 1278 u8 rpg_byte_reset[0x20]; 1279 1280 u8 rpg_threshold[0x20]; 1281 1282 u8 rpg_max_rate[0x20]; 1283 1284 u8 rpg_ai_rate[0x20]; 1285 1286 u8 rpg_hai_rate[0x20]; 1287 1288 u8 rpg_gd[0x20]; 1289 1290 u8 rpg_min_dec_fac[0x20]; 1291 1292 u8 rpg_min_rate[0x20]; 1293 1294 u8 reserved_at_1c0[0xe0]; 1295 1296 u8 rate_to_set_on_first_cnp[0x20]; 1297 1298 u8 dce_tcp_g[0x20]; 1299 1300 u8 dce_tcp_rtt[0x20]; 1301 1302 u8 rate_reduce_monitor_period[0x20]; 1303 1304 u8 reserved_at_320[0x20]; 1305 1306 u8 initial_alpha_value[0x20]; 1307 1308 u8 reserved_at_360[0x4a0]; 1309 }; 1310 1311 struct mlx5_ifc_cong_control_802_1qau_rp_bits { 1312 u8 reserved_at_0[0x80]; 1313 1314 u8 rppp_max_rps[0x20]; 1315 1316 u8 rpg_time_reset[0x20]; 1317 1318 u8 rpg_byte_reset[0x20]; 1319 1320 u8 rpg_threshold[0x20]; 1321 1322 u8 rpg_max_rate[0x20]; 1323 1324 u8 rpg_ai_rate[0x20]; 1325 1326 u8 rpg_hai_rate[0x20]; 1327 1328 u8 rpg_gd[0x20]; 1329 1330 u8 rpg_min_dec_fac[0x20]; 1331 1332 u8 rpg_min_rate[0x20]; 1333 1334 u8 reserved_at_1c0[0x640]; 1335 }; 1336 1337 enum { 1338 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1, 1339 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2, 1340 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4, 1341 }; 1342 1343 struct mlx5_ifc_resize_field_select_bits { 1344 u8 resize_field_select[0x20]; 1345 }; 1346 1347 enum { 1348 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1, 1349 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2, 1350 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4, 1351 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8, 1352 }; 1353 1354 struct mlx5_ifc_modify_field_select_bits { 1355 u8 modify_field_select[0x20]; 1356 }; 1357 1358 struct mlx5_ifc_field_select_r_roce_np_bits { 1359 u8 field_select_r_roce_np[0x20]; 1360 }; 1361 1362 struct mlx5_ifc_field_select_r_roce_rp_bits { 1363 u8 field_select_r_roce_rp[0x20]; 1364 }; 1365 1366 enum { 1367 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4, 1368 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8, 1369 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10, 1370 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20, 1371 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40, 1372 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80, 1373 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100, 1374 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200, 1375 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400, 1376 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800, 1377 }; 1378 1379 struct mlx5_ifc_field_select_802_1qau_rp_bits { 1380 u8 field_select_8021qaurp[0x20]; 1381 }; 1382 1383 struct mlx5_ifc_phys_layer_cntrs_bits { 1384 u8 time_since_last_clear_high[0x20]; 1385 1386 u8 time_since_last_clear_low[0x20]; 1387 1388 u8 symbol_errors_high[0x20]; 1389 1390 u8 symbol_errors_low[0x20]; 1391 1392 u8 sync_headers_errors_high[0x20]; 1393 1394 u8 sync_headers_errors_low[0x20]; 1395 1396 u8 edpl_bip_errors_lane0_high[0x20]; 1397 1398 u8 edpl_bip_errors_lane0_low[0x20]; 1399 1400 u8 edpl_bip_errors_lane1_high[0x20]; 1401 1402 u8 edpl_bip_errors_lane1_low[0x20]; 1403 1404 u8 edpl_bip_errors_lane2_high[0x20]; 1405 1406 u8 edpl_bip_errors_lane2_low[0x20]; 1407 1408 u8 edpl_bip_errors_lane3_high[0x20]; 1409 1410 u8 edpl_bip_errors_lane3_low[0x20]; 1411 1412 u8 fc_fec_corrected_blocks_lane0_high[0x20]; 1413 1414 u8 fc_fec_corrected_blocks_lane0_low[0x20]; 1415 1416 u8 fc_fec_corrected_blocks_lane1_high[0x20]; 1417 1418 u8 fc_fec_corrected_blocks_lane1_low[0x20]; 1419 1420 u8 fc_fec_corrected_blocks_lane2_high[0x20]; 1421 1422 u8 fc_fec_corrected_blocks_lane2_low[0x20]; 1423 1424 u8 fc_fec_corrected_blocks_lane3_high[0x20]; 1425 1426 u8 fc_fec_corrected_blocks_lane3_low[0x20]; 1427 1428 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20]; 1429 1430 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20]; 1431 1432 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20]; 1433 1434 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20]; 1435 1436 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20]; 1437 1438 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20]; 1439 1440 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20]; 1441 1442 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20]; 1443 1444 u8 rs_fec_corrected_blocks_high[0x20]; 1445 1446 u8 rs_fec_corrected_blocks_low[0x20]; 1447 1448 u8 rs_fec_uncorrectable_blocks_high[0x20]; 1449 1450 u8 rs_fec_uncorrectable_blocks_low[0x20]; 1451 1452 u8 rs_fec_no_errors_blocks_high[0x20]; 1453 1454 u8 rs_fec_no_errors_blocks_low[0x20]; 1455 1456 u8 rs_fec_single_error_blocks_high[0x20]; 1457 1458 u8 rs_fec_single_error_blocks_low[0x20]; 1459 1460 u8 rs_fec_corrected_symbols_total_high[0x20]; 1461 1462 u8 rs_fec_corrected_symbols_total_low[0x20]; 1463 1464 u8 rs_fec_corrected_symbols_lane0_high[0x20]; 1465 1466 u8 rs_fec_corrected_symbols_lane0_low[0x20]; 1467 1468 u8 rs_fec_corrected_symbols_lane1_high[0x20]; 1469 1470 u8 rs_fec_corrected_symbols_lane1_low[0x20]; 1471 1472 u8 rs_fec_corrected_symbols_lane2_high[0x20]; 1473 1474 u8 rs_fec_corrected_symbols_lane2_low[0x20]; 1475 1476 u8 rs_fec_corrected_symbols_lane3_high[0x20]; 1477 1478 u8 rs_fec_corrected_symbols_lane3_low[0x20]; 1479 1480 u8 link_down_events[0x20]; 1481 1482 u8 successful_recovery_events[0x20]; 1483 1484 u8 reserved_at_640[0x180]; 1485 }; 1486 1487 struct mlx5_ifc_phys_layer_statistical_cntrs_bits { 1488 u8 time_since_last_clear_high[0x20]; 1489 1490 u8 time_since_last_clear_low[0x20]; 1491 1492 u8 phy_received_bits_high[0x20]; 1493 1494 u8 phy_received_bits_low[0x20]; 1495 1496 u8 phy_symbol_errors_high[0x20]; 1497 1498 u8 phy_symbol_errors_low[0x20]; 1499 1500 u8 phy_corrected_bits_high[0x20]; 1501 1502 u8 phy_corrected_bits_low[0x20]; 1503 1504 u8 phy_corrected_bits_lane0_high[0x20]; 1505 1506 u8 phy_corrected_bits_lane0_low[0x20]; 1507 1508 u8 phy_corrected_bits_lane1_high[0x20]; 1509 1510 u8 phy_corrected_bits_lane1_low[0x20]; 1511 1512 u8 phy_corrected_bits_lane2_high[0x20]; 1513 1514 u8 phy_corrected_bits_lane2_low[0x20]; 1515 1516 u8 phy_corrected_bits_lane3_high[0x20]; 1517 1518 u8 phy_corrected_bits_lane3_low[0x20]; 1519 1520 u8 reserved_at_200[0x5c0]; 1521 }; 1522 1523 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits { 1524 u8 symbol_error_counter[0x10]; 1525 1526 u8 link_error_recovery_counter[0x8]; 1527 1528 u8 link_downed_counter[0x8]; 1529 1530 u8 port_rcv_errors[0x10]; 1531 1532 u8 port_rcv_remote_physical_errors[0x10]; 1533 1534 u8 port_rcv_switch_relay_errors[0x10]; 1535 1536 u8 port_xmit_discards[0x10]; 1537 1538 u8 port_xmit_constraint_errors[0x8]; 1539 1540 u8 port_rcv_constraint_errors[0x8]; 1541 1542 u8 reserved_at_70[0x8]; 1543 1544 u8 link_overrun_errors[0x8]; 1545 1546 u8 reserved_at_80[0x10]; 1547 1548 u8 vl_15_dropped[0x10]; 1549 1550 u8 reserved_at_a0[0x80]; 1551 1552 u8 port_xmit_wait[0x20]; 1553 }; 1554 1555 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits { 1556 u8 transmit_queue_high[0x20]; 1557 1558 u8 transmit_queue_low[0x20]; 1559 1560 u8 reserved_at_40[0x780]; 1561 }; 1562 1563 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits { 1564 u8 rx_octets_high[0x20]; 1565 1566 u8 rx_octets_low[0x20]; 1567 1568 u8 reserved_at_40[0xc0]; 1569 1570 u8 rx_frames_high[0x20]; 1571 1572 u8 rx_frames_low[0x20]; 1573 1574 u8 tx_octets_high[0x20]; 1575 1576 u8 tx_octets_low[0x20]; 1577 1578 u8 reserved_at_180[0xc0]; 1579 1580 u8 tx_frames_high[0x20]; 1581 1582 u8 tx_frames_low[0x20]; 1583 1584 u8 rx_pause_high[0x20]; 1585 1586 u8 rx_pause_low[0x20]; 1587 1588 u8 rx_pause_duration_high[0x20]; 1589 1590 u8 rx_pause_duration_low[0x20]; 1591 1592 u8 tx_pause_high[0x20]; 1593 1594 u8 tx_pause_low[0x20]; 1595 1596 u8 tx_pause_duration_high[0x20]; 1597 1598 u8 tx_pause_duration_low[0x20]; 1599 1600 u8 rx_pause_transition_high[0x20]; 1601 1602 u8 rx_pause_transition_low[0x20]; 1603 1604 u8 reserved_at_3c0[0x40]; 1605 1606 u8 device_stall_minor_watermark_cnt_high[0x20]; 1607 1608 u8 device_stall_minor_watermark_cnt_low[0x20]; 1609 1610 u8 device_stall_critical_watermark_cnt_high[0x20]; 1611 1612 u8 device_stall_critical_watermark_cnt_low[0x20]; 1613 1614 u8 reserved_at_480[0x340]; 1615 }; 1616 1617 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits { 1618 u8 port_transmit_wait_high[0x20]; 1619 1620 u8 port_transmit_wait_low[0x20]; 1621 1622 u8 reserved_at_40[0x100]; 1623 1624 u8 rx_buffer_almost_full_high[0x20]; 1625 1626 u8 rx_buffer_almost_full_low[0x20]; 1627 1628 u8 rx_buffer_full_high[0x20]; 1629 1630 u8 rx_buffer_full_low[0x20]; 1631 1632 u8 reserved_at_1c0[0x600]; 1633 }; 1634 1635 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits { 1636 u8 dot3stats_alignment_errors_high[0x20]; 1637 1638 u8 dot3stats_alignment_errors_low[0x20]; 1639 1640 u8 dot3stats_fcs_errors_high[0x20]; 1641 1642 u8 dot3stats_fcs_errors_low[0x20]; 1643 1644 u8 dot3stats_single_collision_frames_high[0x20]; 1645 1646 u8 dot3stats_single_collision_frames_low[0x20]; 1647 1648 u8 dot3stats_multiple_collision_frames_high[0x20]; 1649 1650 u8 dot3stats_multiple_collision_frames_low[0x20]; 1651 1652 u8 dot3stats_sqe_test_errors_high[0x20]; 1653 1654 u8 dot3stats_sqe_test_errors_low[0x20]; 1655 1656 u8 dot3stats_deferred_transmissions_high[0x20]; 1657 1658 u8 dot3stats_deferred_transmissions_low[0x20]; 1659 1660 u8 dot3stats_late_collisions_high[0x20]; 1661 1662 u8 dot3stats_late_collisions_low[0x20]; 1663 1664 u8 dot3stats_excessive_collisions_high[0x20]; 1665 1666 u8 dot3stats_excessive_collisions_low[0x20]; 1667 1668 u8 dot3stats_internal_mac_transmit_errors_high[0x20]; 1669 1670 u8 dot3stats_internal_mac_transmit_errors_low[0x20]; 1671 1672 u8 dot3stats_carrier_sense_errors_high[0x20]; 1673 1674 u8 dot3stats_carrier_sense_errors_low[0x20]; 1675 1676 u8 dot3stats_frame_too_longs_high[0x20]; 1677 1678 u8 dot3stats_frame_too_longs_low[0x20]; 1679 1680 u8 dot3stats_internal_mac_receive_errors_high[0x20]; 1681 1682 u8 dot3stats_internal_mac_receive_errors_low[0x20]; 1683 1684 u8 dot3stats_symbol_errors_high[0x20]; 1685 1686 u8 dot3stats_symbol_errors_low[0x20]; 1687 1688 u8 dot3control_in_unknown_opcodes_high[0x20]; 1689 1690 u8 dot3control_in_unknown_opcodes_low[0x20]; 1691 1692 u8 dot3in_pause_frames_high[0x20]; 1693 1694 u8 dot3in_pause_frames_low[0x20]; 1695 1696 u8 dot3out_pause_frames_high[0x20]; 1697 1698 u8 dot3out_pause_frames_low[0x20]; 1699 1700 u8 reserved_at_400[0x3c0]; 1701 }; 1702 1703 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits { 1704 u8 ether_stats_drop_events_high[0x20]; 1705 1706 u8 ether_stats_drop_events_low[0x20]; 1707 1708 u8 ether_stats_octets_high[0x20]; 1709 1710 u8 ether_stats_octets_low[0x20]; 1711 1712 u8 ether_stats_pkts_high[0x20]; 1713 1714 u8 ether_stats_pkts_low[0x20]; 1715 1716 u8 ether_stats_broadcast_pkts_high[0x20]; 1717 1718 u8 ether_stats_broadcast_pkts_low[0x20]; 1719 1720 u8 ether_stats_multicast_pkts_high[0x20]; 1721 1722 u8 ether_stats_multicast_pkts_low[0x20]; 1723 1724 u8 ether_stats_crc_align_errors_high[0x20]; 1725 1726 u8 ether_stats_crc_align_errors_low[0x20]; 1727 1728 u8 ether_stats_undersize_pkts_high[0x20]; 1729 1730 u8 ether_stats_undersize_pkts_low[0x20]; 1731 1732 u8 ether_stats_oversize_pkts_high[0x20]; 1733 1734 u8 ether_stats_oversize_pkts_low[0x20]; 1735 1736 u8 ether_stats_fragments_high[0x20]; 1737 1738 u8 ether_stats_fragments_low[0x20]; 1739 1740 u8 ether_stats_jabbers_high[0x20]; 1741 1742 u8 ether_stats_jabbers_low[0x20]; 1743 1744 u8 ether_stats_collisions_high[0x20]; 1745 1746 u8 ether_stats_collisions_low[0x20]; 1747 1748 u8 ether_stats_pkts64octets_high[0x20]; 1749 1750 u8 ether_stats_pkts64octets_low[0x20]; 1751 1752 u8 ether_stats_pkts65to127octets_high[0x20]; 1753 1754 u8 ether_stats_pkts65to127octets_low[0x20]; 1755 1756 u8 ether_stats_pkts128to255octets_high[0x20]; 1757 1758 u8 ether_stats_pkts128to255octets_low[0x20]; 1759 1760 u8 ether_stats_pkts256to511octets_high[0x20]; 1761 1762 u8 ether_stats_pkts256to511octets_low[0x20]; 1763 1764 u8 ether_stats_pkts512to1023octets_high[0x20]; 1765 1766 u8 ether_stats_pkts512to1023octets_low[0x20]; 1767 1768 u8 ether_stats_pkts1024to1518octets_high[0x20]; 1769 1770 u8 ether_stats_pkts1024to1518octets_low[0x20]; 1771 1772 u8 ether_stats_pkts1519to2047octets_high[0x20]; 1773 1774 u8 ether_stats_pkts1519to2047octets_low[0x20]; 1775 1776 u8 ether_stats_pkts2048to4095octets_high[0x20]; 1777 1778 u8 ether_stats_pkts2048to4095octets_low[0x20]; 1779 1780 u8 ether_stats_pkts4096to8191octets_high[0x20]; 1781 1782 u8 ether_stats_pkts4096to8191octets_low[0x20]; 1783 1784 u8 ether_stats_pkts8192to10239octets_high[0x20]; 1785 1786 u8 ether_stats_pkts8192to10239octets_low[0x20]; 1787 1788 u8 reserved_at_540[0x280]; 1789 }; 1790 1791 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits { 1792 u8 if_in_octets_high[0x20]; 1793 1794 u8 if_in_octets_low[0x20]; 1795 1796 u8 if_in_ucast_pkts_high[0x20]; 1797 1798 u8 if_in_ucast_pkts_low[0x20]; 1799 1800 u8 if_in_discards_high[0x20]; 1801 1802 u8 if_in_discards_low[0x20]; 1803 1804 u8 if_in_errors_high[0x20]; 1805 1806 u8 if_in_errors_low[0x20]; 1807 1808 u8 if_in_unknown_protos_high[0x20]; 1809 1810 u8 if_in_unknown_protos_low[0x20]; 1811 1812 u8 if_out_octets_high[0x20]; 1813 1814 u8 if_out_octets_low[0x20]; 1815 1816 u8 if_out_ucast_pkts_high[0x20]; 1817 1818 u8 if_out_ucast_pkts_low[0x20]; 1819 1820 u8 if_out_discards_high[0x20]; 1821 1822 u8 if_out_discards_low[0x20]; 1823 1824 u8 if_out_errors_high[0x20]; 1825 1826 u8 if_out_errors_low[0x20]; 1827 1828 u8 if_in_multicast_pkts_high[0x20]; 1829 1830 u8 if_in_multicast_pkts_low[0x20]; 1831 1832 u8 if_in_broadcast_pkts_high[0x20]; 1833 1834 u8 if_in_broadcast_pkts_low[0x20]; 1835 1836 u8 if_out_multicast_pkts_high[0x20]; 1837 1838 u8 if_out_multicast_pkts_low[0x20]; 1839 1840 u8 if_out_broadcast_pkts_high[0x20]; 1841 1842 u8 if_out_broadcast_pkts_low[0x20]; 1843 1844 u8 reserved_at_340[0x480]; 1845 }; 1846 1847 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits { 1848 u8 a_frames_transmitted_ok_high[0x20]; 1849 1850 u8 a_frames_transmitted_ok_low[0x20]; 1851 1852 u8 a_frames_received_ok_high[0x20]; 1853 1854 u8 a_frames_received_ok_low[0x20]; 1855 1856 u8 a_frame_check_sequence_errors_high[0x20]; 1857 1858 u8 a_frame_check_sequence_errors_low[0x20]; 1859 1860 u8 a_alignment_errors_high[0x20]; 1861 1862 u8 a_alignment_errors_low[0x20]; 1863 1864 u8 a_octets_transmitted_ok_high[0x20]; 1865 1866 u8 a_octets_transmitted_ok_low[0x20]; 1867 1868 u8 a_octets_received_ok_high[0x20]; 1869 1870 u8 a_octets_received_ok_low[0x20]; 1871 1872 u8 a_multicast_frames_xmitted_ok_high[0x20]; 1873 1874 u8 a_multicast_frames_xmitted_ok_low[0x20]; 1875 1876 u8 a_broadcast_frames_xmitted_ok_high[0x20]; 1877 1878 u8 a_broadcast_frames_xmitted_ok_low[0x20]; 1879 1880 u8 a_multicast_frames_received_ok_high[0x20]; 1881 1882 u8 a_multicast_frames_received_ok_low[0x20]; 1883 1884 u8 a_broadcast_frames_received_ok_high[0x20]; 1885 1886 u8 a_broadcast_frames_received_ok_low[0x20]; 1887 1888 u8 a_in_range_length_errors_high[0x20]; 1889 1890 u8 a_in_range_length_errors_low[0x20]; 1891 1892 u8 a_out_of_range_length_field_high[0x20]; 1893 1894 u8 a_out_of_range_length_field_low[0x20]; 1895 1896 u8 a_frame_too_long_errors_high[0x20]; 1897 1898 u8 a_frame_too_long_errors_low[0x20]; 1899 1900 u8 a_symbol_error_during_carrier_high[0x20]; 1901 1902 u8 a_symbol_error_during_carrier_low[0x20]; 1903 1904 u8 a_mac_control_frames_transmitted_high[0x20]; 1905 1906 u8 a_mac_control_frames_transmitted_low[0x20]; 1907 1908 u8 a_mac_control_frames_received_high[0x20]; 1909 1910 u8 a_mac_control_frames_received_low[0x20]; 1911 1912 u8 a_unsupported_opcodes_received_high[0x20]; 1913 1914 u8 a_unsupported_opcodes_received_low[0x20]; 1915 1916 u8 a_pause_mac_ctrl_frames_received_high[0x20]; 1917 1918 u8 a_pause_mac_ctrl_frames_received_low[0x20]; 1919 1920 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20]; 1921 1922 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20]; 1923 1924 u8 reserved_at_4c0[0x300]; 1925 }; 1926 1927 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits { 1928 u8 life_time_counter_high[0x20]; 1929 1930 u8 life_time_counter_low[0x20]; 1931 1932 u8 rx_errors[0x20]; 1933 1934 u8 tx_errors[0x20]; 1935 1936 u8 l0_to_recovery_eieos[0x20]; 1937 1938 u8 l0_to_recovery_ts[0x20]; 1939 1940 u8 l0_to_recovery_framing[0x20]; 1941 1942 u8 l0_to_recovery_retrain[0x20]; 1943 1944 u8 crc_error_dllp[0x20]; 1945 1946 u8 crc_error_tlp[0x20]; 1947 1948 u8 tx_overflow_buffer_pkt_high[0x20]; 1949 1950 u8 tx_overflow_buffer_pkt_low[0x20]; 1951 1952 u8 outbound_stalled_reads[0x20]; 1953 1954 u8 outbound_stalled_writes[0x20]; 1955 1956 u8 outbound_stalled_reads_events[0x20]; 1957 1958 u8 outbound_stalled_writes_events[0x20]; 1959 1960 u8 reserved_at_200[0x5c0]; 1961 }; 1962 1963 struct mlx5_ifc_cmd_inter_comp_event_bits { 1964 u8 command_completion_vector[0x20]; 1965 1966 u8 reserved_at_20[0xc0]; 1967 }; 1968 1969 struct mlx5_ifc_stall_vl_event_bits { 1970 u8 reserved_at_0[0x18]; 1971 u8 port_num[0x1]; 1972 u8 reserved_at_19[0x3]; 1973 u8 vl[0x4]; 1974 1975 u8 reserved_at_20[0xa0]; 1976 }; 1977 1978 struct mlx5_ifc_db_bf_congestion_event_bits { 1979 u8 event_subtype[0x8]; 1980 u8 reserved_at_8[0x8]; 1981 u8 congestion_level[0x8]; 1982 u8 reserved_at_18[0x8]; 1983 1984 u8 reserved_at_20[0xa0]; 1985 }; 1986 1987 struct mlx5_ifc_gpio_event_bits { 1988 u8 reserved_at_0[0x60]; 1989 1990 u8 gpio_event_hi[0x20]; 1991 1992 u8 gpio_event_lo[0x20]; 1993 1994 u8 reserved_at_a0[0x40]; 1995 }; 1996 1997 struct mlx5_ifc_port_state_change_event_bits { 1998 u8 reserved_at_0[0x40]; 1999 2000 u8 port_num[0x4]; 2001 u8 reserved_at_44[0x1c]; 2002 2003 u8 reserved_at_60[0x80]; 2004 }; 2005 2006 struct mlx5_ifc_dropped_packet_logged_bits { 2007 u8 reserved_at_0[0xe0]; 2008 }; 2009 2010 enum { 2011 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1, 2012 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2, 2013 }; 2014 2015 struct mlx5_ifc_cq_error_bits { 2016 u8 reserved_at_0[0x8]; 2017 u8 cqn[0x18]; 2018 2019 u8 reserved_at_20[0x20]; 2020 2021 u8 reserved_at_40[0x18]; 2022 u8 syndrome[0x8]; 2023 2024 u8 reserved_at_60[0x80]; 2025 }; 2026 2027 struct mlx5_ifc_rdma_page_fault_event_bits { 2028 u8 bytes_committed[0x20]; 2029 2030 u8 r_key[0x20]; 2031 2032 u8 reserved_at_40[0x10]; 2033 u8 packet_len[0x10]; 2034 2035 u8 rdma_op_len[0x20]; 2036 2037 u8 rdma_va[0x40]; 2038 2039 u8 reserved_at_c0[0x5]; 2040 u8 rdma[0x1]; 2041 u8 write[0x1]; 2042 u8 requestor[0x1]; 2043 u8 qp_number[0x18]; 2044 }; 2045 2046 struct mlx5_ifc_wqe_associated_page_fault_event_bits { 2047 u8 bytes_committed[0x20]; 2048 2049 u8 reserved_at_20[0x10]; 2050 u8 wqe_index[0x10]; 2051 2052 u8 reserved_at_40[0x10]; 2053 u8 len[0x10]; 2054 2055 u8 reserved_at_60[0x60]; 2056 2057 u8 reserved_at_c0[0x5]; 2058 u8 rdma[0x1]; 2059 u8 write_read[0x1]; 2060 u8 requestor[0x1]; 2061 u8 qpn[0x18]; 2062 }; 2063 2064 struct mlx5_ifc_qp_events_bits { 2065 u8 reserved_at_0[0xa0]; 2066 2067 u8 type[0x8]; 2068 u8 reserved_at_a8[0x18]; 2069 2070 u8 reserved_at_c0[0x8]; 2071 u8 qpn_rqn_sqn[0x18]; 2072 }; 2073 2074 struct mlx5_ifc_dct_events_bits { 2075 u8 reserved_at_0[0xc0]; 2076 2077 u8 reserved_at_c0[0x8]; 2078 u8 dct_number[0x18]; 2079 }; 2080 2081 struct mlx5_ifc_comp_event_bits { 2082 u8 reserved_at_0[0xc0]; 2083 2084 u8 reserved_at_c0[0x8]; 2085 u8 cq_number[0x18]; 2086 }; 2087 2088 enum { 2089 MLX5_QPC_STATE_RST = 0x0, 2090 MLX5_QPC_STATE_INIT = 0x1, 2091 MLX5_QPC_STATE_RTR = 0x2, 2092 MLX5_QPC_STATE_RTS = 0x3, 2093 MLX5_QPC_STATE_SQER = 0x4, 2094 MLX5_QPC_STATE_ERR = 0x6, 2095 MLX5_QPC_STATE_SQD = 0x7, 2096 MLX5_QPC_STATE_SUSPENDED = 0x9, 2097 }; 2098 2099 enum { 2100 MLX5_QPC_ST_RC = 0x0, 2101 MLX5_QPC_ST_UC = 0x1, 2102 MLX5_QPC_ST_UD = 0x2, 2103 MLX5_QPC_ST_XRC = 0x3, 2104 MLX5_QPC_ST_DCI = 0x5, 2105 MLX5_QPC_ST_QP0 = 0x7, 2106 MLX5_QPC_ST_QP1 = 0x8, 2107 MLX5_QPC_ST_RAW_DATAGRAM = 0x9, 2108 MLX5_QPC_ST_REG_UMR = 0xc, 2109 }; 2110 2111 enum { 2112 MLX5_QPC_PM_STATE_ARMED = 0x0, 2113 MLX5_QPC_PM_STATE_REARM = 0x1, 2114 MLX5_QPC_PM_STATE_RESERVED = 0x2, 2115 MLX5_QPC_PM_STATE_MIGRATED = 0x3, 2116 }; 2117 2118 enum { 2119 MLX5_QPC_OFFLOAD_TYPE_RNDV = 0x1, 2120 }; 2121 2122 enum { 2123 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0, 2124 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1, 2125 }; 2126 2127 enum { 2128 MLX5_QPC_MTU_256_BYTES = 0x1, 2129 MLX5_QPC_MTU_512_BYTES = 0x2, 2130 MLX5_QPC_MTU_1K_BYTES = 0x3, 2131 MLX5_QPC_MTU_2K_BYTES = 0x4, 2132 MLX5_QPC_MTU_4K_BYTES = 0x5, 2133 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7, 2134 }; 2135 2136 enum { 2137 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1, 2138 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2, 2139 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3, 2140 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4, 2141 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5, 2142 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6, 2143 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7, 2144 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8, 2145 }; 2146 2147 enum { 2148 MLX5_QPC_CS_REQ_DISABLE = 0x0, 2149 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11, 2150 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22, 2151 }; 2152 2153 enum { 2154 MLX5_QPC_CS_RES_DISABLE = 0x0, 2155 MLX5_QPC_CS_RES_UP_TO_32B = 0x1, 2156 MLX5_QPC_CS_RES_UP_TO_64B = 0x2, 2157 }; 2158 2159 struct mlx5_ifc_qpc_bits { 2160 u8 state[0x4]; 2161 u8 lag_tx_port_affinity[0x4]; 2162 u8 st[0x8]; 2163 u8 reserved_at_10[0x3]; 2164 u8 pm_state[0x2]; 2165 u8 reserved_at_15[0x3]; 2166 u8 offload_type[0x4]; 2167 u8 end_padding_mode[0x2]; 2168 u8 reserved_at_1e[0x2]; 2169 2170 u8 wq_signature[0x1]; 2171 u8 block_lb_mc[0x1]; 2172 u8 atomic_like_write_en[0x1]; 2173 u8 latency_sensitive[0x1]; 2174 u8 reserved_at_24[0x1]; 2175 u8 drain_sigerr[0x1]; 2176 u8 reserved_at_26[0x2]; 2177 u8 pd[0x18]; 2178 2179 u8 mtu[0x3]; 2180 u8 log_msg_max[0x5]; 2181 u8 reserved_at_48[0x1]; 2182 u8 log_rq_size[0x4]; 2183 u8 log_rq_stride[0x3]; 2184 u8 no_sq[0x1]; 2185 u8 log_sq_size[0x4]; 2186 u8 reserved_at_55[0x6]; 2187 u8 rlky[0x1]; 2188 u8 ulp_stateless_offload_mode[0x4]; 2189 2190 u8 counter_set_id[0x8]; 2191 u8 uar_page[0x18]; 2192 2193 u8 reserved_at_80[0x8]; 2194 u8 user_index[0x18]; 2195 2196 u8 reserved_at_a0[0x3]; 2197 u8 log_page_size[0x5]; 2198 u8 remote_qpn[0x18]; 2199 2200 struct mlx5_ifc_ads_bits primary_address_path; 2201 2202 struct mlx5_ifc_ads_bits secondary_address_path; 2203 2204 u8 log_ack_req_freq[0x4]; 2205 u8 reserved_at_384[0x4]; 2206 u8 log_sra_max[0x3]; 2207 u8 reserved_at_38b[0x2]; 2208 u8 retry_count[0x3]; 2209 u8 rnr_retry[0x3]; 2210 u8 reserved_at_393[0x1]; 2211 u8 fre[0x1]; 2212 u8 cur_rnr_retry[0x3]; 2213 u8 cur_retry_count[0x3]; 2214 u8 reserved_at_39b[0x5]; 2215 2216 u8 reserved_at_3a0[0x20]; 2217 2218 u8 reserved_at_3c0[0x8]; 2219 u8 next_send_psn[0x18]; 2220 2221 u8 reserved_at_3e0[0x8]; 2222 u8 cqn_snd[0x18]; 2223 2224 u8 reserved_at_400[0x8]; 2225 u8 deth_sqpn[0x18]; 2226 2227 u8 reserved_at_420[0x20]; 2228 2229 u8 reserved_at_440[0x8]; 2230 u8 last_acked_psn[0x18]; 2231 2232 u8 reserved_at_460[0x8]; 2233 u8 ssn[0x18]; 2234 2235 u8 reserved_at_480[0x8]; 2236 u8 log_rra_max[0x3]; 2237 u8 reserved_at_48b[0x1]; 2238 u8 atomic_mode[0x4]; 2239 u8 rre[0x1]; 2240 u8 rwe[0x1]; 2241 u8 rae[0x1]; 2242 u8 reserved_at_493[0x1]; 2243 u8 page_offset[0x6]; 2244 u8 reserved_at_49a[0x3]; 2245 u8 cd_slave_receive[0x1]; 2246 u8 cd_slave_send[0x1]; 2247 u8 cd_master[0x1]; 2248 2249 u8 reserved_at_4a0[0x3]; 2250 u8 min_rnr_nak[0x5]; 2251 u8 next_rcv_psn[0x18]; 2252 2253 u8 reserved_at_4c0[0x8]; 2254 u8 xrcd[0x18]; 2255 2256 u8 reserved_at_4e0[0x8]; 2257 u8 cqn_rcv[0x18]; 2258 2259 u8 dbr_addr[0x40]; 2260 2261 u8 q_key[0x20]; 2262 2263 u8 reserved_at_560[0x5]; 2264 u8 rq_type[0x3]; 2265 u8 srqn_rmpn_xrqn[0x18]; 2266 2267 u8 reserved_at_580[0x8]; 2268 u8 rmsn[0x18]; 2269 2270 u8 hw_sq_wqebb_counter[0x10]; 2271 u8 sw_sq_wqebb_counter[0x10]; 2272 2273 u8 hw_rq_counter[0x20]; 2274 2275 u8 sw_rq_counter[0x20]; 2276 2277 u8 reserved_at_600[0x20]; 2278 2279 u8 reserved_at_620[0xf]; 2280 u8 cgs[0x1]; 2281 u8 cs_req[0x8]; 2282 u8 cs_res[0x8]; 2283 2284 u8 dc_access_key[0x40]; 2285 2286 u8 reserved_at_680[0xc0]; 2287 }; 2288 2289 struct mlx5_ifc_roce_addr_layout_bits { 2290 u8 source_l3_address[16][0x8]; 2291 2292 u8 reserved_at_80[0x3]; 2293 u8 vlan_valid[0x1]; 2294 u8 vlan_id[0xc]; 2295 u8 source_mac_47_32[0x10]; 2296 2297 u8 source_mac_31_0[0x20]; 2298 2299 u8 reserved_at_c0[0x14]; 2300 u8 roce_l3_type[0x4]; 2301 u8 roce_version[0x8]; 2302 2303 u8 reserved_at_e0[0x20]; 2304 }; 2305 2306 union mlx5_ifc_hca_cap_union_bits { 2307 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap; 2308 struct mlx5_ifc_odp_cap_bits odp_cap; 2309 struct mlx5_ifc_atomic_caps_bits atomic_caps; 2310 struct mlx5_ifc_roce_cap_bits roce_cap; 2311 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps; 2312 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap; 2313 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap; 2314 struct mlx5_ifc_e_switch_cap_bits e_switch_cap; 2315 struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap; 2316 struct mlx5_ifc_qos_cap_bits qos_cap; 2317 struct mlx5_ifc_fpga_cap_bits fpga_cap; 2318 u8 reserved_at_0[0x8000]; 2319 }; 2320 2321 enum { 2322 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1, 2323 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2, 2324 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4, 2325 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8, 2326 MLX5_FLOW_CONTEXT_ACTION_ENCAP = 0x10, 2327 MLX5_FLOW_CONTEXT_ACTION_DECAP = 0x20, 2328 MLX5_FLOW_CONTEXT_ACTION_MOD_HDR = 0x40, 2329 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP = 0x80, 2330 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100, 2331 }; 2332 2333 struct mlx5_ifc_vlan_bits { 2334 u8 ethtype[0x10]; 2335 u8 prio[0x3]; 2336 u8 cfi[0x1]; 2337 u8 vid[0xc]; 2338 }; 2339 2340 struct mlx5_ifc_flow_context_bits { 2341 struct mlx5_ifc_vlan_bits push_vlan; 2342 2343 u8 group_id[0x20]; 2344 2345 u8 reserved_at_40[0x8]; 2346 u8 flow_tag[0x18]; 2347 2348 u8 reserved_at_60[0x10]; 2349 u8 action[0x10]; 2350 2351 u8 reserved_at_80[0x8]; 2352 u8 destination_list_size[0x18]; 2353 2354 u8 reserved_at_a0[0x8]; 2355 u8 flow_counter_list_size[0x18]; 2356 2357 u8 encap_id[0x20]; 2358 2359 u8 modify_header_id[0x20]; 2360 2361 u8 reserved_at_100[0x100]; 2362 2363 struct mlx5_ifc_fte_match_param_bits match_value; 2364 2365 u8 reserved_at_1200[0x600]; 2366 2367 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[0]; 2368 }; 2369 2370 enum { 2371 MLX5_XRC_SRQC_STATE_GOOD = 0x0, 2372 MLX5_XRC_SRQC_STATE_ERROR = 0x1, 2373 }; 2374 2375 struct mlx5_ifc_xrc_srqc_bits { 2376 u8 state[0x4]; 2377 u8 log_xrc_srq_size[0x4]; 2378 u8 reserved_at_8[0x18]; 2379 2380 u8 wq_signature[0x1]; 2381 u8 cont_srq[0x1]; 2382 u8 reserved_at_22[0x1]; 2383 u8 rlky[0x1]; 2384 u8 basic_cyclic_rcv_wqe[0x1]; 2385 u8 log_rq_stride[0x3]; 2386 u8 xrcd[0x18]; 2387 2388 u8 page_offset[0x6]; 2389 u8 reserved_at_46[0x2]; 2390 u8 cqn[0x18]; 2391 2392 u8 reserved_at_60[0x20]; 2393 2394 u8 user_index_equal_xrc_srqn[0x1]; 2395 u8 reserved_at_81[0x1]; 2396 u8 log_page_size[0x6]; 2397 u8 user_index[0x18]; 2398 2399 u8 reserved_at_a0[0x20]; 2400 2401 u8 reserved_at_c0[0x8]; 2402 u8 pd[0x18]; 2403 2404 u8 lwm[0x10]; 2405 u8 wqe_cnt[0x10]; 2406 2407 u8 reserved_at_100[0x40]; 2408 2409 u8 db_record_addr_h[0x20]; 2410 2411 u8 db_record_addr_l[0x1e]; 2412 u8 reserved_at_17e[0x2]; 2413 2414 u8 reserved_at_180[0x80]; 2415 }; 2416 2417 struct mlx5_ifc_vnic_diagnostic_statistics_bits { 2418 u8 counter_error_queues[0x20]; 2419 2420 u8 total_error_queues[0x20]; 2421 2422 u8 send_queue_priority_update_flow[0x20]; 2423 2424 u8 reserved_at_60[0x20]; 2425 2426 u8 nic_receive_steering_discard[0x40]; 2427 2428 u8 receive_discard_vport_down[0x40]; 2429 2430 u8 transmit_discard_vport_down[0x40]; 2431 2432 u8 reserved_at_140[0xec0]; 2433 }; 2434 2435 struct mlx5_ifc_traffic_counter_bits { 2436 u8 packets[0x40]; 2437 2438 u8 octets[0x40]; 2439 }; 2440 2441 struct mlx5_ifc_tisc_bits { 2442 u8 strict_lag_tx_port_affinity[0x1]; 2443 u8 reserved_at_1[0x3]; 2444 u8 lag_tx_port_affinity[0x04]; 2445 2446 u8 reserved_at_8[0x4]; 2447 u8 prio[0x4]; 2448 u8 reserved_at_10[0x10]; 2449 2450 u8 reserved_at_20[0x100]; 2451 2452 u8 reserved_at_120[0x8]; 2453 u8 transport_domain[0x18]; 2454 2455 u8 reserved_at_140[0x8]; 2456 u8 underlay_qpn[0x18]; 2457 u8 reserved_at_160[0x3a0]; 2458 }; 2459 2460 enum { 2461 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0, 2462 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1, 2463 }; 2464 2465 enum { 2466 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO = 0x1, 2467 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO = 0x2, 2468 }; 2469 2470 enum { 2471 MLX5_RX_HASH_FN_NONE = 0x0, 2472 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1, 2473 MLX5_RX_HASH_FN_TOEPLITZ = 0x2, 2474 }; 2475 2476 enum { 2477 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST_ = 0x1, 2478 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST_ = 0x2, 2479 }; 2480 2481 struct mlx5_ifc_tirc_bits { 2482 u8 reserved_at_0[0x20]; 2483 2484 u8 disp_type[0x4]; 2485 u8 reserved_at_24[0x1c]; 2486 2487 u8 reserved_at_40[0x40]; 2488 2489 u8 reserved_at_80[0x4]; 2490 u8 lro_timeout_period_usecs[0x10]; 2491 u8 lro_enable_mask[0x4]; 2492 u8 lro_max_ip_payload_size[0x8]; 2493 2494 u8 reserved_at_a0[0x40]; 2495 2496 u8 reserved_at_e0[0x8]; 2497 u8 inline_rqn[0x18]; 2498 2499 u8 rx_hash_symmetric[0x1]; 2500 u8 reserved_at_101[0x1]; 2501 u8 tunneled_offload_en[0x1]; 2502 u8 reserved_at_103[0x5]; 2503 u8 indirect_table[0x18]; 2504 2505 u8 rx_hash_fn[0x4]; 2506 u8 reserved_at_124[0x2]; 2507 u8 self_lb_block[0x2]; 2508 u8 transport_domain[0x18]; 2509 2510 u8 rx_hash_toeplitz_key[10][0x20]; 2511 2512 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer; 2513 2514 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner; 2515 2516 u8 reserved_at_2c0[0x4c0]; 2517 }; 2518 2519 enum { 2520 MLX5_SRQC_STATE_GOOD = 0x0, 2521 MLX5_SRQC_STATE_ERROR = 0x1, 2522 }; 2523 2524 struct mlx5_ifc_srqc_bits { 2525 u8 state[0x4]; 2526 u8 log_srq_size[0x4]; 2527 u8 reserved_at_8[0x18]; 2528 2529 u8 wq_signature[0x1]; 2530 u8 cont_srq[0x1]; 2531 u8 reserved_at_22[0x1]; 2532 u8 rlky[0x1]; 2533 u8 reserved_at_24[0x1]; 2534 u8 log_rq_stride[0x3]; 2535 u8 xrcd[0x18]; 2536 2537 u8 page_offset[0x6]; 2538 u8 reserved_at_46[0x2]; 2539 u8 cqn[0x18]; 2540 2541 u8 reserved_at_60[0x20]; 2542 2543 u8 reserved_at_80[0x2]; 2544 u8 log_page_size[0x6]; 2545 u8 reserved_at_88[0x18]; 2546 2547 u8 reserved_at_a0[0x20]; 2548 2549 u8 reserved_at_c0[0x8]; 2550 u8 pd[0x18]; 2551 2552 u8 lwm[0x10]; 2553 u8 wqe_cnt[0x10]; 2554 2555 u8 reserved_at_100[0x40]; 2556 2557 u8 dbr_addr[0x40]; 2558 2559 u8 reserved_at_180[0x80]; 2560 }; 2561 2562 enum { 2563 MLX5_SQC_STATE_RST = 0x0, 2564 MLX5_SQC_STATE_RDY = 0x1, 2565 MLX5_SQC_STATE_ERR = 0x3, 2566 }; 2567 2568 struct mlx5_ifc_sqc_bits { 2569 u8 rlky[0x1]; 2570 u8 cd_master[0x1]; 2571 u8 fre[0x1]; 2572 u8 flush_in_error_en[0x1]; 2573 u8 allow_multi_pkt_send_wqe[0x1]; 2574 u8 min_wqe_inline_mode[0x3]; 2575 u8 state[0x4]; 2576 u8 reg_umr[0x1]; 2577 u8 allow_swp[0x1]; 2578 u8 hairpin[0x1]; 2579 u8 reserved_at_f[0x11]; 2580 2581 u8 reserved_at_20[0x8]; 2582 u8 user_index[0x18]; 2583 2584 u8 reserved_at_40[0x8]; 2585 u8 cqn[0x18]; 2586 2587 u8 reserved_at_60[0x8]; 2588 u8 hairpin_peer_rq[0x18]; 2589 2590 u8 reserved_at_80[0x10]; 2591 u8 hairpin_peer_vhca[0x10]; 2592 2593 u8 reserved_at_a0[0x50]; 2594 2595 u8 packet_pacing_rate_limit_index[0x10]; 2596 u8 tis_lst_sz[0x10]; 2597 u8 reserved_at_110[0x10]; 2598 2599 u8 reserved_at_120[0x40]; 2600 2601 u8 reserved_at_160[0x8]; 2602 u8 tis_num_0[0x18]; 2603 2604 struct mlx5_ifc_wq_bits wq; 2605 }; 2606 2607 enum { 2608 SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0, 2609 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1, 2610 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2, 2611 SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3, 2612 }; 2613 2614 struct mlx5_ifc_scheduling_context_bits { 2615 u8 element_type[0x8]; 2616 u8 reserved_at_8[0x18]; 2617 2618 u8 element_attributes[0x20]; 2619 2620 u8 parent_element_id[0x20]; 2621 2622 u8 reserved_at_60[0x40]; 2623 2624 u8 bw_share[0x20]; 2625 2626 u8 max_average_bw[0x20]; 2627 2628 u8 reserved_at_e0[0x120]; 2629 }; 2630 2631 struct mlx5_ifc_rqtc_bits { 2632 u8 reserved_at_0[0xa0]; 2633 2634 u8 reserved_at_a0[0x10]; 2635 u8 rqt_max_size[0x10]; 2636 2637 u8 reserved_at_c0[0x10]; 2638 u8 rqt_actual_size[0x10]; 2639 2640 u8 reserved_at_e0[0x6a0]; 2641 2642 struct mlx5_ifc_rq_num_bits rq_num[0]; 2643 }; 2644 2645 enum { 2646 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0, 2647 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1, 2648 }; 2649 2650 enum { 2651 MLX5_RQC_STATE_RST = 0x0, 2652 MLX5_RQC_STATE_RDY = 0x1, 2653 MLX5_RQC_STATE_ERR = 0x3, 2654 }; 2655 2656 struct mlx5_ifc_rqc_bits { 2657 u8 rlky[0x1]; 2658 u8 delay_drop_en[0x1]; 2659 u8 scatter_fcs[0x1]; 2660 u8 vsd[0x1]; 2661 u8 mem_rq_type[0x4]; 2662 u8 state[0x4]; 2663 u8 reserved_at_c[0x1]; 2664 u8 flush_in_error_en[0x1]; 2665 u8 hairpin[0x1]; 2666 u8 reserved_at_f[0x11]; 2667 2668 u8 reserved_at_20[0x8]; 2669 u8 user_index[0x18]; 2670 2671 u8 reserved_at_40[0x8]; 2672 u8 cqn[0x18]; 2673 2674 u8 counter_set_id[0x8]; 2675 u8 reserved_at_68[0x18]; 2676 2677 u8 reserved_at_80[0x8]; 2678 u8 rmpn[0x18]; 2679 2680 u8 reserved_at_a0[0x8]; 2681 u8 hairpin_peer_sq[0x18]; 2682 2683 u8 reserved_at_c0[0x10]; 2684 u8 hairpin_peer_vhca[0x10]; 2685 2686 u8 reserved_at_e0[0xa0]; 2687 2688 struct mlx5_ifc_wq_bits wq; 2689 }; 2690 2691 enum { 2692 MLX5_RMPC_STATE_RDY = 0x1, 2693 MLX5_RMPC_STATE_ERR = 0x3, 2694 }; 2695 2696 struct mlx5_ifc_rmpc_bits { 2697 u8 reserved_at_0[0x8]; 2698 u8 state[0x4]; 2699 u8 reserved_at_c[0x14]; 2700 2701 u8 basic_cyclic_rcv_wqe[0x1]; 2702 u8 reserved_at_21[0x1f]; 2703 2704 u8 reserved_at_40[0x140]; 2705 2706 struct mlx5_ifc_wq_bits wq; 2707 }; 2708 2709 struct mlx5_ifc_nic_vport_context_bits { 2710 u8 reserved_at_0[0x5]; 2711 u8 min_wqe_inline_mode[0x3]; 2712 u8 reserved_at_8[0x15]; 2713 u8 disable_mc_local_lb[0x1]; 2714 u8 disable_uc_local_lb[0x1]; 2715 u8 roce_en[0x1]; 2716 2717 u8 arm_change_event[0x1]; 2718 u8 reserved_at_21[0x1a]; 2719 u8 event_on_mtu[0x1]; 2720 u8 event_on_promisc_change[0x1]; 2721 u8 event_on_vlan_change[0x1]; 2722 u8 event_on_mc_address_change[0x1]; 2723 u8 event_on_uc_address_change[0x1]; 2724 2725 u8 reserved_at_40[0xc]; 2726 2727 u8 affiliation_criteria[0x4]; 2728 u8 affiliated_vhca_id[0x10]; 2729 2730 u8 reserved_at_60[0xd0]; 2731 2732 u8 mtu[0x10]; 2733 2734 u8 system_image_guid[0x40]; 2735 u8 port_guid[0x40]; 2736 u8 node_guid[0x40]; 2737 2738 u8 reserved_at_200[0x140]; 2739 u8 qkey_violation_counter[0x10]; 2740 u8 reserved_at_350[0x430]; 2741 2742 u8 promisc_uc[0x1]; 2743 u8 promisc_mc[0x1]; 2744 u8 promisc_all[0x1]; 2745 u8 reserved_at_783[0x2]; 2746 u8 allowed_list_type[0x3]; 2747 u8 reserved_at_788[0xc]; 2748 u8 allowed_list_size[0xc]; 2749 2750 struct mlx5_ifc_mac_address_layout_bits permanent_address; 2751 2752 u8 reserved_at_7e0[0x20]; 2753 2754 u8 current_uc_mac_address[0][0x40]; 2755 }; 2756 2757 enum { 2758 MLX5_MKC_ACCESS_MODE_PA = 0x0, 2759 MLX5_MKC_ACCESS_MODE_MTT = 0x1, 2760 MLX5_MKC_ACCESS_MODE_KLMS = 0x2, 2761 MLX5_MKC_ACCESS_MODE_KSM = 0x3, 2762 MLX5_MKC_ACCESS_MODE_MEMIC = 0x5, 2763 }; 2764 2765 struct mlx5_ifc_mkc_bits { 2766 u8 reserved_at_0[0x1]; 2767 u8 free[0x1]; 2768 u8 reserved_at_2[0x1]; 2769 u8 access_mode_4_2[0x3]; 2770 u8 reserved_at_6[0x7]; 2771 u8 relaxed_ordering_write[0x1]; 2772 u8 reserved_at_e[0x1]; 2773 u8 small_fence_on_rdma_read_response[0x1]; 2774 u8 umr_en[0x1]; 2775 u8 a[0x1]; 2776 u8 rw[0x1]; 2777 u8 rr[0x1]; 2778 u8 lw[0x1]; 2779 u8 lr[0x1]; 2780 u8 access_mode_1_0[0x2]; 2781 u8 reserved_at_18[0x8]; 2782 2783 u8 qpn[0x18]; 2784 u8 mkey_7_0[0x8]; 2785 2786 u8 reserved_at_40[0x20]; 2787 2788 u8 length64[0x1]; 2789 u8 bsf_en[0x1]; 2790 u8 sync_umr[0x1]; 2791 u8 reserved_at_63[0x2]; 2792 u8 expected_sigerr_count[0x1]; 2793 u8 reserved_at_66[0x1]; 2794 u8 en_rinval[0x1]; 2795 u8 pd[0x18]; 2796 2797 u8 start_addr[0x40]; 2798 2799 u8 len[0x40]; 2800 2801 u8 bsf_octword_size[0x20]; 2802 2803 u8 reserved_at_120[0x80]; 2804 2805 u8 translations_octword_size[0x20]; 2806 2807 u8 reserved_at_1c0[0x1b]; 2808 u8 log_page_size[0x5]; 2809 2810 u8 reserved_at_1e0[0x20]; 2811 }; 2812 2813 struct mlx5_ifc_pkey_bits { 2814 u8 reserved_at_0[0x10]; 2815 u8 pkey[0x10]; 2816 }; 2817 2818 struct mlx5_ifc_array128_auto_bits { 2819 u8 array128_auto[16][0x8]; 2820 }; 2821 2822 struct mlx5_ifc_hca_vport_context_bits { 2823 u8 field_select[0x20]; 2824 2825 u8 reserved_at_20[0xe0]; 2826 2827 u8 sm_virt_aware[0x1]; 2828 u8 has_smi[0x1]; 2829 u8 has_raw[0x1]; 2830 u8 grh_required[0x1]; 2831 u8 reserved_at_104[0xc]; 2832 u8 port_physical_state[0x4]; 2833 u8 vport_state_policy[0x4]; 2834 u8 port_state[0x4]; 2835 u8 vport_state[0x4]; 2836 2837 u8 reserved_at_120[0x20]; 2838 2839 u8 system_image_guid[0x40]; 2840 2841 u8 port_guid[0x40]; 2842 2843 u8 node_guid[0x40]; 2844 2845 u8 cap_mask1[0x20]; 2846 2847 u8 cap_mask1_field_select[0x20]; 2848 2849 u8 cap_mask2[0x20]; 2850 2851 u8 cap_mask2_field_select[0x20]; 2852 2853 u8 reserved_at_280[0x80]; 2854 2855 u8 lid[0x10]; 2856 u8 reserved_at_310[0x4]; 2857 u8 init_type_reply[0x4]; 2858 u8 lmc[0x3]; 2859 u8 subnet_timeout[0x5]; 2860 2861 u8 sm_lid[0x10]; 2862 u8 sm_sl[0x4]; 2863 u8 reserved_at_334[0xc]; 2864 2865 u8 qkey_violation_counter[0x10]; 2866 u8 pkey_violation_counter[0x10]; 2867 2868 u8 reserved_at_360[0xca0]; 2869 }; 2870 2871 struct mlx5_ifc_esw_vport_context_bits { 2872 u8 reserved_at_0[0x3]; 2873 u8 vport_svlan_strip[0x1]; 2874 u8 vport_cvlan_strip[0x1]; 2875 u8 vport_svlan_insert[0x1]; 2876 u8 vport_cvlan_insert[0x2]; 2877 u8 reserved_at_8[0x18]; 2878 2879 u8 reserved_at_20[0x20]; 2880 2881 u8 svlan_cfi[0x1]; 2882 u8 svlan_pcp[0x3]; 2883 u8 svlan_id[0xc]; 2884 u8 cvlan_cfi[0x1]; 2885 u8 cvlan_pcp[0x3]; 2886 u8 cvlan_id[0xc]; 2887 2888 u8 reserved_at_60[0x7a0]; 2889 }; 2890 2891 enum { 2892 MLX5_EQC_STATUS_OK = 0x0, 2893 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa, 2894 }; 2895 2896 enum { 2897 MLX5_EQC_ST_ARMED = 0x9, 2898 MLX5_EQC_ST_FIRED = 0xa, 2899 }; 2900 2901 struct mlx5_ifc_eqc_bits { 2902 u8 status[0x4]; 2903 u8 reserved_at_4[0x9]; 2904 u8 ec[0x1]; 2905 u8 oi[0x1]; 2906 u8 reserved_at_f[0x5]; 2907 u8 st[0x4]; 2908 u8 reserved_at_18[0x8]; 2909 2910 u8 reserved_at_20[0x20]; 2911 2912 u8 reserved_at_40[0x14]; 2913 u8 page_offset[0x6]; 2914 u8 reserved_at_5a[0x6]; 2915 2916 u8 reserved_at_60[0x3]; 2917 u8 log_eq_size[0x5]; 2918 u8 uar_page[0x18]; 2919 2920 u8 reserved_at_80[0x20]; 2921 2922 u8 reserved_at_a0[0x18]; 2923 u8 intr[0x8]; 2924 2925 u8 reserved_at_c0[0x3]; 2926 u8 log_page_size[0x5]; 2927 u8 reserved_at_c8[0x18]; 2928 2929 u8 reserved_at_e0[0x60]; 2930 2931 u8 reserved_at_140[0x8]; 2932 u8 consumer_counter[0x18]; 2933 2934 u8 reserved_at_160[0x8]; 2935 u8 producer_counter[0x18]; 2936 2937 u8 reserved_at_180[0x80]; 2938 }; 2939 2940 enum { 2941 MLX5_DCTC_STATE_ACTIVE = 0x0, 2942 MLX5_DCTC_STATE_DRAINING = 0x1, 2943 MLX5_DCTC_STATE_DRAINED = 0x2, 2944 }; 2945 2946 enum { 2947 MLX5_DCTC_CS_RES_DISABLE = 0x0, 2948 MLX5_DCTC_CS_RES_NA = 0x1, 2949 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2, 2950 }; 2951 2952 enum { 2953 MLX5_DCTC_MTU_256_BYTES = 0x1, 2954 MLX5_DCTC_MTU_512_BYTES = 0x2, 2955 MLX5_DCTC_MTU_1K_BYTES = 0x3, 2956 MLX5_DCTC_MTU_2K_BYTES = 0x4, 2957 MLX5_DCTC_MTU_4K_BYTES = 0x5, 2958 }; 2959 2960 struct mlx5_ifc_dctc_bits { 2961 u8 reserved_at_0[0x4]; 2962 u8 state[0x4]; 2963 u8 reserved_at_8[0x18]; 2964 2965 u8 reserved_at_20[0x8]; 2966 u8 user_index[0x18]; 2967 2968 u8 reserved_at_40[0x8]; 2969 u8 cqn[0x18]; 2970 2971 u8 counter_set_id[0x8]; 2972 u8 atomic_mode[0x4]; 2973 u8 rre[0x1]; 2974 u8 rwe[0x1]; 2975 u8 rae[0x1]; 2976 u8 atomic_like_write_en[0x1]; 2977 u8 latency_sensitive[0x1]; 2978 u8 rlky[0x1]; 2979 u8 free_ar[0x1]; 2980 u8 reserved_at_73[0xd]; 2981 2982 u8 reserved_at_80[0x8]; 2983 u8 cs_res[0x8]; 2984 u8 reserved_at_90[0x3]; 2985 u8 min_rnr_nak[0x5]; 2986 u8 reserved_at_98[0x8]; 2987 2988 u8 reserved_at_a0[0x8]; 2989 u8 srqn_xrqn[0x18]; 2990 2991 u8 reserved_at_c0[0x8]; 2992 u8 pd[0x18]; 2993 2994 u8 tclass[0x8]; 2995 u8 reserved_at_e8[0x4]; 2996 u8 flow_label[0x14]; 2997 2998 u8 dc_access_key[0x40]; 2999 3000 u8 reserved_at_140[0x5]; 3001 u8 mtu[0x3]; 3002 u8 port[0x8]; 3003 u8 pkey_index[0x10]; 3004 3005 u8 reserved_at_160[0x8]; 3006 u8 my_addr_index[0x8]; 3007 u8 reserved_at_170[0x8]; 3008 u8 hop_limit[0x8]; 3009 3010 u8 dc_access_key_violation_count[0x20]; 3011 3012 u8 reserved_at_1a0[0x14]; 3013 u8 dei_cfi[0x1]; 3014 u8 eth_prio[0x3]; 3015 u8 ecn[0x2]; 3016 u8 dscp[0x6]; 3017 3018 u8 reserved_at_1c0[0x40]; 3019 }; 3020 3021 enum { 3022 MLX5_CQC_STATUS_OK = 0x0, 3023 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9, 3024 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa, 3025 }; 3026 3027 enum { 3028 MLX5_CQC_CQE_SZ_64_BYTES = 0x0, 3029 MLX5_CQC_CQE_SZ_128_BYTES = 0x1, 3030 }; 3031 3032 enum { 3033 MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED = 0x6, 3034 MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED = 0x9, 3035 MLX5_CQC_ST_FIRED = 0xa, 3036 }; 3037 3038 enum { 3039 MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0, 3040 MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1, 3041 MLX5_CQ_PERIOD_NUM_MODES 3042 }; 3043 3044 struct mlx5_ifc_cqc_bits { 3045 u8 status[0x4]; 3046 u8 reserved_at_4[0x4]; 3047 u8 cqe_sz[0x3]; 3048 u8 cc[0x1]; 3049 u8 reserved_at_c[0x1]; 3050 u8 scqe_break_moderation_en[0x1]; 3051 u8 oi[0x1]; 3052 u8 cq_period_mode[0x2]; 3053 u8 cqe_comp_en[0x1]; 3054 u8 mini_cqe_res_format[0x2]; 3055 u8 st[0x4]; 3056 u8 reserved_at_18[0x8]; 3057 3058 u8 reserved_at_20[0x20]; 3059 3060 u8 reserved_at_40[0x14]; 3061 u8 page_offset[0x6]; 3062 u8 reserved_at_5a[0x6]; 3063 3064 u8 reserved_at_60[0x3]; 3065 u8 log_cq_size[0x5]; 3066 u8 uar_page[0x18]; 3067 3068 u8 reserved_at_80[0x4]; 3069 u8 cq_period[0xc]; 3070 u8 cq_max_count[0x10]; 3071 3072 u8 reserved_at_a0[0x18]; 3073 u8 c_eqn[0x8]; 3074 3075 u8 reserved_at_c0[0x3]; 3076 u8 log_page_size[0x5]; 3077 u8 reserved_at_c8[0x18]; 3078 3079 u8 reserved_at_e0[0x20]; 3080 3081 u8 reserved_at_100[0x8]; 3082 u8 last_notified_index[0x18]; 3083 3084 u8 reserved_at_120[0x8]; 3085 u8 last_solicit_index[0x18]; 3086 3087 u8 reserved_at_140[0x8]; 3088 u8 consumer_counter[0x18]; 3089 3090 u8 reserved_at_160[0x8]; 3091 u8 producer_counter[0x18]; 3092 3093 u8 reserved_at_180[0x40]; 3094 3095 u8 dbr_addr[0x40]; 3096 }; 3097 3098 union mlx5_ifc_cong_control_roce_ecn_auto_bits { 3099 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp; 3100 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp; 3101 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np; 3102 u8 reserved_at_0[0x800]; 3103 }; 3104 3105 struct mlx5_ifc_query_adapter_param_block_bits { 3106 u8 reserved_at_0[0xc0]; 3107 3108 u8 reserved_at_c0[0x8]; 3109 u8 ieee_vendor_id[0x18]; 3110 3111 u8 reserved_at_e0[0x10]; 3112 u8 vsd_vendor_id[0x10]; 3113 3114 u8 vsd[208][0x8]; 3115 3116 u8 vsd_contd_psid[16][0x8]; 3117 }; 3118 3119 enum { 3120 MLX5_XRQC_STATE_GOOD = 0x0, 3121 MLX5_XRQC_STATE_ERROR = 0x1, 3122 }; 3123 3124 enum { 3125 MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0, 3126 MLX5_XRQC_TOPOLOGY_TAG_MATCHING = 0x1, 3127 }; 3128 3129 enum { 3130 MLX5_XRQC_OFFLOAD_RNDV = 0x1, 3131 }; 3132 3133 struct mlx5_ifc_tag_matching_topology_context_bits { 3134 u8 log_matching_list_sz[0x4]; 3135 u8 reserved_at_4[0xc]; 3136 u8 append_next_index[0x10]; 3137 3138 u8 sw_phase_cnt[0x10]; 3139 u8 hw_phase_cnt[0x10]; 3140 3141 u8 reserved_at_40[0x40]; 3142 }; 3143 3144 struct mlx5_ifc_xrqc_bits { 3145 u8 state[0x4]; 3146 u8 rlkey[0x1]; 3147 u8 reserved_at_5[0xf]; 3148 u8 topology[0x4]; 3149 u8 reserved_at_18[0x4]; 3150 u8 offload[0x4]; 3151 3152 u8 reserved_at_20[0x8]; 3153 u8 user_index[0x18]; 3154 3155 u8 reserved_at_40[0x8]; 3156 u8 cqn[0x18]; 3157 3158 u8 reserved_at_60[0xa0]; 3159 3160 struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context; 3161 3162 u8 reserved_at_180[0x280]; 3163 3164 struct mlx5_ifc_wq_bits wq; 3165 }; 3166 3167 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits { 3168 struct mlx5_ifc_modify_field_select_bits modify_field_select; 3169 struct mlx5_ifc_resize_field_select_bits resize_field_select; 3170 u8 reserved_at_0[0x20]; 3171 }; 3172 3173 union mlx5_ifc_field_select_802_1_r_roce_auto_bits { 3174 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp; 3175 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp; 3176 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np; 3177 u8 reserved_at_0[0x20]; 3178 }; 3179 3180 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits { 3181 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 3182 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 3183 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 3184 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 3185 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 3186 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 3187 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout; 3188 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 3189 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 3190 struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs; 3191 u8 reserved_at_0[0x7c0]; 3192 }; 3193 3194 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits { 3195 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout; 3196 u8 reserved_at_0[0x7c0]; 3197 }; 3198 3199 union mlx5_ifc_event_auto_bits { 3200 struct mlx5_ifc_comp_event_bits comp_event; 3201 struct mlx5_ifc_dct_events_bits dct_events; 3202 struct mlx5_ifc_qp_events_bits qp_events; 3203 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event; 3204 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event; 3205 struct mlx5_ifc_cq_error_bits cq_error; 3206 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged; 3207 struct mlx5_ifc_port_state_change_event_bits port_state_change_event; 3208 struct mlx5_ifc_gpio_event_bits gpio_event; 3209 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event; 3210 struct mlx5_ifc_stall_vl_event_bits stall_vl_event; 3211 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event; 3212 u8 reserved_at_0[0xe0]; 3213 }; 3214 3215 struct mlx5_ifc_health_buffer_bits { 3216 u8 reserved_at_0[0x100]; 3217 3218 u8 assert_existptr[0x20]; 3219 3220 u8 assert_callra[0x20]; 3221 3222 u8 reserved_at_140[0x40]; 3223 3224 u8 fw_version[0x20]; 3225 3226 u8 hw_id[0x20]; 3227 3228 u8 reserved_at_1c0[0x20]; 3229 3230 u8 irisc_index[0x8]; 3231 u8 synd[0x8]; 3232 u8 ext_synd[0x10]; 3233 }; 3234 3235 struct mlx5_ifc_register_loopback_control_bits { 3236 u8 no_lb[0x1]; 3237 u8 reserved_at_1[0x7]; 3238 u8 port[0x8]; 3239 u8 reserved_at_10[0x10]; 3240 3241 u8 reserved_at_20[0x60]; 3242 }; 3243 3244 struct mlx5_ifc_vport_tc_element_bits { 3245 u8 traffic_class[0x4]; 3246 u8 reserved_at_4[0xc]; 3247 u8 vport_number[0x10]; 3248 }; 3249 3250 struct mlx5_ifc_vport_element_bits { 3251 u8 reserved_at_0[0x10]; 3252 u8 vport_number[0x10]; 3253 }; 3254 3255 enum { 3256 TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0, 3257 TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1, 3258 TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2, 3259 }; 3260 3261 struct mlx5_ifc_tsar_element_bits { 3262 u8 reserved_at_0[0x8]; 3263 u8 tsar_type[0x8]; 3264 u8 reserved_at_10[0x10]; 3265 }; 3266 3267 enum { 3268 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0, 3269 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1, 3270 }; 3271 3272 struct mlx5_ifc_teardown_hca_out_bits { 3273 u8 status[0x8]; 3274 u8 reserved_at_8[0x18]; 3275 3276 u8 syndrome[0x20]; 3277 3278 u8 reserved_at_40[0x3f]; 3279 3280 u8 force_state[0x1]; 3281 }; 3282 3283 enum { 3284 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0, 3285 MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE = 0x1, 3286 }; 3287 3288 struct mlx5_ifc_teardown_hca_in_bits { 3289 u8 opcode[0x10]; 3290 u8 reserved_at_10[0x10]; 3291 3292 u8 reserved_at_20[0x10]; 3293 u8 op_mod[0x10]; 3294 3295 u8 reserved_at_40[0x10]; 3296 u8 profile[0x10]; 3297 3298 u8 reserved_at_60[0x20]; 3299 }; 3300 3301 struct mlx5_ifc_sqerr2rts_qp_out_bits { 3302 u8 status[0x8]; 3303 u8 reserved_at_8[0x18]; 3304 3305 u8 syndrome[0x20]; 3306 3307 u8 reserved_at_40[0x40]; 3308 }; 3309 3310 struct mlx5_ifc_sqerr2rts_qp_in_bits { 3311 u8 opcode[0x10]; 3312 u8 reserved_at_10[0x10]; 3313 3314 u8 reserved_at_20[0x10]; 3315 u8 op_mod[0x10]; 3316 3317 u8 reserved_at_40[0x8]; 3318 u8 qpn[0x18]; 3319 3320 u8 reserved_at_60[0x20]; 3321 3322 u8 opt_param_mask[0x20]; 3323 3324 u8 reserved_at_a0[0x20]; 3325 3326 struct mlx5_ifc_qpc_bits qpc; 3327 3328 u8 reserved_at_800[0x80]; 3329 }; 3330 3331 struct mlx5_ifc_sqd2rts_qp_out_bits { 3332 u8 status[0x8]; 3333 u8 reserved_at_8[0x18]; 3334 3335 u8 syndrome[0x20]; 3336 3337 u8 reserved_at_40[0x40]; 3338 }; 3339 3340 struct mlx5_ifc_sqd2rts_qp_in_bits { 3341 u8 opcode[0x10]; 3342 u8 reserved_at_10[0x10]; 3343 3344 u8 reserved_at_20[0x10]; 3345 u8 op_mod[0x10]; 3346 3347 u8 reserved_at_40[0x8]; 3348 u8 qpn[0x18]; 3349 3350 u8 reserved_at_60[0x20]; 3351 3352 u8 opt_param_mask[0x20]; 3353 3354 u8 reserved_at_a0[0x20]; 3355 3356 struct mlx5_ifc_qpc_bits qpc; 3357 3358 u8 reserved_at_800[0x80]; 3359 }; 3360 3361 struct mlx5_ifc_set_roce_address_out_bits { 3362 u8 status[0x8]; 3363 u8 reserved_at_8[0x18]; 3364 3365 u8 syndrome[0x20]; 3366 3367 u8 reserved_at_40[0x40]; 3368 }; 3369 3370 struct mlx5_ifc_set_roce_address_in_bits { 3371 u8 opcode[0x10]; 3372 u8 reserved_at_10[0x10]; 3373 3374 u8 reserved_at_20[0x10]; 3375 u8 op_mod[0x10]; 3376 3377 u8 roce_address_index[0x10]; 3378 u8 reserved_at_50[0xc]; 3379 u8 vhca_port_num[0x4]; 3380 3381 u8 reserved_at_60[0x20]; 3382 3383 struct mlx5_ifc_roce_addr_layout_bits roce_address; 3384 }; 3385 3386 struct mlx5_ifc_set_mad_demux_out_bits { 3387 u8 status[0x8]; 3388 u8 reserved_at_8[0x18]; 3389 3390 u8 syndrome[0x20]; 3391 3392 u8 reserved_at_40[0x40]; 3393 }; 3394 3395 enum { 3396 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0, 3397 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2, 3398 }; 3399 3400 struct mlx5_ifc_set_mad_demux_in_bits { 3401 u8 opcode[0x10]; 3402 u8 reserved_at_10[0x10]; 3403 3404 u8 reserved_at_20[0x10]; 3405 u8 op_mod[0x10]; 3406 3407 u8 reserved_at_40[0x20]; 3408 3409 u8 reserved_at_60[0x6]; 3410 u8 demux_mode[0x2]; 3411 u8 reserved_at_68[0x18]; 3412 }; 3413 3414 struct mlx5_ifc_set_l2_table_entry_out_bits { 3415 u8 status[0x8]; 3416 u8 reserved_at_8[0x18]; 3417 3418 u8 syndrome[0x20]; 3419 3420 u8 reserved_at_40[0x40]; 3421 }; 3422 3423 struct mlx5_ifc_set_l2_table_entry_in_bits { 3424 u8 opcode[0x10]; 3425 u8 reserved_at_10[0x10]; 3426 3427 u8 reserved_at_20[0x10]; 3428 u8 op_mod[0x10]; 3429 3430 u8 reserved_at_40[0x60]; 3431 3432 u8 reserved_at_a0[0x8]; 3433 u8 table_index[0x18]; 3434 3435 u8 reserved_at_c0[0x20]; 3436 3437 u8 reserved_at_e0[0x13]; 3438 u8 vlan_valid[0x1]; 3439 u8 vlan[0xc]; 3440 3441 struct mlx5_ifc_mac_address_layout_bits mac_address; 3442 3443 u8 reserved_at_140[0xc0]; 3444 }; 3445 3446 struct mlx5_ifc_set_issi_out_bits { 3447 u8 status[0x8]; 3448 u8 reserved_at_8[0x18]; 3449 3450 u8 syndrome[0x20]; 3451 3452 u8 reserved_at_40[0x40]; 3453 }; 3454 3455 struct mlx5_ifc_set_issi_in_bits { 3456 u8 opcode[0x10]; 3457 u8 reserved_at_10[0x10]; 3458 3459 u8 reserved_at_20[0x10]; 3460 u8 op_mod[0x10]; 3461 3462 u8 reserved_at_40[0x10]; 3463 u8 current_issi[0x10]; 3464 3465 u8 reserved_at_60[0x20]; 3466 }; 3467 3468 struct mlx5_ifc_set_hca_cap_out_bits { 3469 u8 status[0x8]; 3470 u8 reserved_at_8[0x18]; 3471 3472 u8 syndrome[0x20]; 3473 3474 u8 reserved_at_40[0x40]; 3475 }; 3476 3477 struct mlx5_ifc_set_hca_cap_in_bits { 3478 u8 opcode[0x10]; 3479 u8 reserved_at_10[0x10]; 3480 3481 u8 reserved_at_20[0x10]; 3482 u8 op_mod[0x10]; 3483 3484 u8 reserved_at_40[0x40]; 3485 3486 union mlx5_ifc_hca_cap_union_bits capability; 3487 }; 3488 3489 enum { 3490 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0, 3491 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1, 3492 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2, 3493 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3 3494 }; 3495 3496 struct mlx5_ifc_set_fte_out_bits { 3497 u8 status[0x8]; 3498 u8 reserved_at_8[0x18]; 3499 3500 u8 syndrome[0x20]; 3501 3502 u8 reserved_at_40[0x40]; 3503 }; 3504 3505 struct mlx5_ifc_set_fte_in_bits { 3506 u8 opcode[0x10]; 3507 u8 reserved_at_10[0x10]; 3508 3509 u8 reserved_at_20[0x10]; 3510 u8 op_mod[0x10]; 3511 3512 u8 other_vport[0x1]; 3513 u8 reserved_at_41[0xf]; 3514 u8 vport_number[0x10]; 3515 3516 u8 reserved_at_60[0x20]; 3517 3518 u8 table_type[0x8]; 3519 u8 reserved_at_88[0x18]; 3520 3521 u8 reserved_at_a0[0x8]; 3522 u8 table_id[0x18]; 3523 3524 u8 reserved_at_c0[0x18]; 3525 u8 modify_enable_mask[0x8]; 3526 3527 u8 reserved_at_e0[0x20]; 3528 3529 u8 flow_index[0x20]; 3530 3531 u8 reserved_at_120[0xe0]; 3532 3533 struct mlx5_ifc_flow_context_bits flow_context; 3534 }; 3535 3536 struct mlx5_ifc_rts2rts_qp_out_bits { 3537 u8 status[0x8]; 3538 u8 reserved_at_8[0x18]; 3539 3540 u8 syndrome[0x20]; 3541 3542 u8 reserved_at_40[0x40]; 3543 }; 3544 3545 struct mlx5_ifc_rts2rts_qp_in_bits { 3546 u8 opcode[0x10]; 3547 u8 reserved_at_10[0x10]; 3548 3549 u8 reserved_at_20[0x10]; 3550 u8 op_mod[0x10]; 3551 3552 u8 reserved_at_40[0x8]; 3553 u8 qpn[0x18]; 3554 3555 u8 reserved_at_60[0x20]; 3556 3557 u8 opt_param_mask[0x20]; 3558 3559 u8 reserved_at_a0[0x20]; 3560 3561 struct mlx5_ifc_qpc_bits qpc; 3562 3563 u8 reserved_at_800[0x80]; 3564 }; 3565 3566 struct mlx5_ifc_rtr2rts_qp_out_bits { 3567 u8 status[0x8]; 3568 u8 reserved_at_8[0x18]; 3569 3570 u8 syndrome[0x20]; 3571 3572 u8 reserved_at_40[0x40]; 3573 }; 3574 3575 struct mlx5_ifc_rtr2rts_qp_in_bits { 3576 u8 opcode[0x10]; 3577 u8 reserved_at_10[0x10]; 3578 3579 u8 reserved_at_20[0x10]; 3580 u8 op_mod[0x10]; 3581 3582 u8 reserved_at_40[0x8]; 3583 u8 qpn[0x18]; 3584 3585 u8 reserved_at_60[0x20]; 3586 3587 u8 opt_param_mask[0x20]; 3588 3589 u8 reserved_at_a0[0x20]; 3590 3591 struct mlx5_ifc_qpc_bits qpc; 3592 3593 u8 reserved_at_800[0x80]; 3594 }; 3595 3596 struct mlx5_ifc_rst2init_qp_out_bits { 3597 u8 status[0x8]; 3598 u8 reserved_at_8[0x18]; 3599 3600 u8 syndrome[0x20]; 3601 3602 u8 reserved_at_40[0x40]; 3603 }; 3604 3605 struct mlx5_ifc_rst2init_qp_in_bits { 3606 u8 opcode[0x10]; 3607 u8 reserved_at_10[0x10]; 3608 3609 u8 reserved_at_20[0x10]; 3610 u8 op_mod[0x10]; 3611 3612 u8 reserved_at_40[0x8]; 3613 u8 qpn[0x18]; 3614 3615 u8 reserved_at_60[0x20]; 3616 3617 u8 opt_param_mask[0x20]; 3618 3619 u8 reserved_at_a0[0x20]; 3620 3621 struct mlx5_ifc_qpc_bits qpc; 3622 3623 u8 reserved_at_800[0x80]; 3624 }; 3625 3626 struct mlx5_ifc_query_xrq_out_bits { 3627 u8 status[0x8]; 3628 u8 reserved_at_8[0x18]; 3629 3630 u8 syndrome[0x20]; 3631 3632 u8 reserved_at_40[0x40]; 3633 3634 struct mlx5_ifc_xrqc_bits xrq_context; 3635 }; 3636 3637 struct mlx5_ifc_query_xrq_in_bits { 3638 u8 opcode[0x10]; 3639 u8 reserved_at_10[0x10]; 3640 3641 u8 reserved_at_20[0x10]; 3642 u8 op_mod[0x10]; 3643 3644 u8 reserved_at_40[0x8]; 3645 u8 xrqn[0x18]; 3646 3647 u8 reserved_at_60[0x20]; 3648 }; 3649 3650 struct mlx5_ifc_query_xrc_srq_out_bits { 3651 u8 status[0x8]; 3652 u8 reserved_at_8[0x18]; 3653 3654 u8 syndrome[0x20]; 3655 3656 u8 reserved_at_40[0x40]; 3657 3658 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 3659 3660 u8 reserved_at_280[0x600]; 3661 3662 u8 pas[0][0x40]; 3663 }; 3664 3665 struct mlx5_ifc_query_xrc_srq_in_bits { 3666 u8 opcode[0x10]; 3667 u8 reserved_at_10[0x10]; 3668 3669 u8 reserved_at_20[0x10]; 3670 u8 op_mod[0x10]; 3671 3672 u8 reserved_at_40[0x8]; 3673 u8 xrc_srqn[0x18]; 3674 3675 u8 reserved_at_60[0x20]; 3676 }; 3677 3678 enum { 3679 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0, 3680 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1, 3681 }; 3682 3683 struct mlx5_ifc_query_vport_state_out_bits { 3684 u8 status[0x8]; 3685 u8 reserved_at_8[0x18]; 3686 3687 u8 syndrome[0x20]; 3688 3689 u8 reserved_at_40[0x20]; 3690 3691 u8 reserved_at_60[0x18]; 3692 u8 admin_state[0x4]; 3693 u8 state[0x4]; 3694 }; 3695 3696 enum { 3697 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT = 0x0, 3698 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_ESW_VPORT = 0x1, 3699 }; 3700 3701 struct mlx5_ifc_query_vport_state_in_bits { 3702 u8 opcode[0x10]; 3703 u8 reserved_at_10[0x10]; 3704 3705 u8 reserved_at_20[0x10]; 3706 u8 op_mod[0x10]; 3707 3708 u8 other_vport[0x1]; 3709 u8 reserved_at_41[0xf]; 3710 u8 vport_number[0x10]; 3711 3712 u8 reserved_at_60[0x20]; 3713 }; 3714 3715 struct mlx5_ifc_query_vnic_env_out_bits { 3716 u8 status[0x8]; 3717 u8 reserved_at_8[0x18]; 3718 3719 u8 syndrome[0x20]; 3720 3721 u8 reserved_at_40[0x40]; 3722 3723 struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env; 3724 }; 3725 3726 enum { 3727 MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS = 0x0, 3728 }; 3729 3730 struct mlx5_ifc_query_vnic_env_in_bits { 3731 u8 opcode[0x10]; 3732 u8 reserved_at_10[0x10]; 3733 3734 u8 reserved_at_20[0x10]; 3735 u8 op_mod[0x10]; 3736 3737 u8 other_vport[0x1]; 3738 u8 reserved_at_41[0xf]; 3739 u8 vport_number[0x10]; 3740 3741 u8 reserved_at_60[0x20]; 3742 }; 3743 3744 struct mlx5_ifc_query_vport_counter_out_bits { 3745 u8 status[0x8]; 3746 u8 reserved_at_8[0x18]; 3747 3748 u8 syndrome[0x20]; 3749 3750 u8 reserved_at_40[0x40]; 3751 3752 struct mlx5_ifc_traffic_counter_bits received_errors; 3753 3754 struct mlx5_ifc_traffic_counter_bits transmit_errors; 3755 3756 struct mlx5_ifc_traffic_counter_bits received_ib_unicast; 3757 3758 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast; 3759 3760 struct mlx5_ifc_traffic_counter_bits received_ib_multicast; 3761 3762 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast; 3763 3764 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast; 3765 3766 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast; 3767 3768 struct mlx5_ifc_traffic_counter_bits received_eth_unicast; 3769 3770 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast; 3771 3772 struct mlx5_ifc_traffic_counter_bits received_eth_multicast; 3773 3774 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast; 3775 3776 u8 reserved_at_680[0xa00]; 3777 }; 3778 3779 enum { 3780 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0, 3781 }; 3782 3783 struct mlx5_ifc_query_vport_counter_in_bits { 3784 u8 opcode[0x10]; 3785 u8 reserved_at_10[0x10]; 3786 3787 u8 reserved_at_20[0x10]; 3788 u8 op_mod[0x10]; 3789 3790 u8 other_vport[0x1]; 3791 u8 reserved_at_41[0xb]; 3792 u8 port_num[0x4]; 3793 u8 vport_number[0x10]; 3794 3795 u8 reserved_at_60[0x60]; 3796 3797 u8 clear[0x1]; 3798 u8 reserved_at_c1[0x1f]; 3799 3800 u8 reserved_at_e0[0x20]; 3801 }; 3802 3803 struct mlx5_ifc_query_tis_out_bits { 3804 u8 status[0x8]; 3805 u8 reserved_at_8[0x18]; 3806 3807 u8 syndrome[0x20]; 3808 3809 u8 reserved_at_40[0x40]; 3810 3811 struct mlx5_ifc_tisc_bits tis_context; 3812 }; 3813 3814 struct mlx5_ifc_query_tis_in_bits { 3815 u8 opcode[0x10]; 3816 u8 reserved_at_10[0x10]; 3817 3818 u8 reserved_at_20[0x10]; 3819 u8 op_mod[0x10]; 3820 3821 u8 reserved_at_40[0x8]; 3822 u8 tisn[0x18]; 3823 3824 u8 reserved_at_60[0x20]; 3825 }; 3826 3827 struct mlx5_ifc_query_tir_out_bits { 3828 u8 status[0x8]; 3829 u8 reserved_at_8[0x18]; 3830 3831 u8 syndrome[0x20]; 3832 3833 u8 reserved_at_40[0xc0]; 3834 3835 struct mlx5_ifc_tirc_bits tir_context; 3836 }; 3837 3838 struct mlx5_ifc_query_tir_in_bits { 3839 u8 opcode[0x10]; 3840 u8 reserved_at_10[0x10]; 3841 3842 u8 reserved_at_20[0x10]; 3843 u8 op_mod[0x10]; 3844 3845 u8 reserved_at_40[0x8]; 3846 u8 tirn[0x18]; 3847 3848 u8 reserved_at_60[0x20]; 3849 }; 3850 3851 struct mlx5_ifc_query_srq_out_bits { 3852 u8 status[0x8]; 3853 u8 reserved_at_8[0x18]; 3854 3855 u8 syndrome[0x20]; 3856 3857 u8 reserved_at_40[0x40]; 3858 3859 struct mlx5_ifc_srqc_bits srq_context_entry; 3860 3861 u8 reserved_at_280[0x600]; 3862 3863 u8 pas[0][0x40]; 3864 }; 3865 3866 struct mlx5_ifc_query_srq_in_bits { 3867 u8 opcode[0x10]; 3868 u8 reserved_at_10[0x10]; 3869 3870 u8 reserved_at_20[0x10]; 3871 u8 op_mod[0x10]; 3872 3873 u8 reserved_at_40[0x8]; 3874 u8 srqn[0x18]; 3875 3876 u8 reserved_at_60[0x20]; 3877 }; 3878 3879 struct mlx5_ifc_query_sq_out_bits { 3880 u8 status[0x8]; 3881 u8 reserved_at_8[0x18]; 3882 3883 u8 syndrome[0x20]; 3884 3885 u8 reserved_at_40[0xc0]; 3886 3887 struct mlx5_ifc_sqc_bits sq_context; 3888 }; 3889 3890 struct mlx5_ifc_query_sq_in_bits { 3891 u8 opcode[0x10]; 3892 u8 reserved_at_10[0x10]; 3893 3894 u8 reserved_at_20[0x10]; 3895 u8 op_mod[0x10]; 3896 3897 u8 reserved_at_40[0x8]; 3898 u8 sqn[0x18]; 3899 3900 u8 reserved_at_60[0x20]; 3901 }; 3902 3903 struct mlx5_ifc_query_special_contexts_out_bits { 3904 u8 status[0x8]; 3905 u8 reserved_at_8[0x18]; 3906 3907 u8 syndrome[0x20]; 3908 3909 u8 dump_fill_mkey[0x20]; 3910 3911 u8 resd_lkey[0x20]; 3912 3913 u8 null_mkey[0x20]; 3914 3915 u8 reserved_at_a0[0x60]; 3916 }; 3917 3918 struct mlx5_ifc_query_special_contexts_in_bits { 3919 u8 opcode[0x10]; 3920 u8 reserved_at_10[0x10]; 3921 3922 u8 reserved_at_20[0x10]; 3923 u8 op_mod[0x10]; 3924 3925 u8 reserved_at_40[0x40]; 3926 }; 3927 3928 struct mlx5_ifc_query_scheduling_element_out_bits { 3929 u8 opcode[0x10]; 3930 u8 reserved_at_10[0x10]; 3931 3932 u8 reserved_at_20[0x10]; 3933 u8 op_mod[0x10]; 3934 3935 u8 reserved_at_40[0xc0]; 3936 3937 struct mlx5_ifc_scheduling_context_bits scheduling_context; 3938 3939 u8 reserved_at_300[0x100]; 3940 }; 3941 3942 enum { 3943 SCHEDULING_HIERARCHY_E_SWITCH = 0x2, 3944 }; 3945 3946 struct mlx5_ifc_query_scheduling_element_in_bits { 3947 u8 opcode[0x10]; 3948 u8 reserved_at_10[0x10]; 3949 3950 u8 reserved_at_20[0x10]; 3951 u8 op_mod[0x10]; 3952 3953 u8 scheduling_hierarchy[0x8]; 3954 u8 reserved_at_48[0x18]; 3955 3956 u8 scheduling_element_id[0x20]; 3957 3958 u8 reserved_at_80[0x180]; 3959 }; 3960 3961 struct mlx5_ifc_query_rqt_out_bits { 3962 u8 status[0x8]; 3963 u8 reserved_at_8[0x18]; 3964 3965 u8 syndrome[0x20]; 3966 3967 u8 reserved_at_40[0xc0]; 3968 3969 struct mlx5_ifc_rqtc_bits rqt_context; 3970 }; 3971 3972 struct mlx5_ifc_query_rqt_in_bits { 3973 u8 opcode[0x10]; 3974 u8 reserved_at_10[0x10]; 3975 3976 u8 reserved_at_20[0x10]; 3977 u8 op_mod[0x10]; 3978 3979 u8 reserved_at_40[0x8]; 3980 u8 rqtn[0x18]; 3981 3982 u8 reserved_at_60[0x20]; 3983 }; 3984 3985 struct mlx5_ifc_query_rq_out_bits { 3986 u8 status[0x8]; 3987 u8 reserved_at_8[0x18]; 3988 3989 u8 syndrome[0x20]; 3990 3991 u8 reserved_at_40[0xc0]; 3992 3993 struct mlx5_ifc_rqc_bits rq_context; 3994 }; 3995 3996 struct mlx5_ifc_query_rq_in_bits { 3997 u8 opcode[0x10]; 3998 u8 reserved_at_10[0x10]; 3999 4000 u8 reserved_at_20[0x10]; 4001 u8 op_mod[0x10]; 4002 4003 u8 reserved_at_40[0x8]; 4004 u8 rqn[0x18]; 4005 4006 u8 reserved_at_60[0x20]; 4007 }; 4008 4009 struct mlx5_ifc_query_roce_address_out_bits { 4010 u8 status[0x8]; 4011 u8 reserved_at_8[0x18]; 4012 4013 u8 syndrome[0x20]; 4014 4015 u8 reserved_at_40[0x40]; 4016 4017 struct mlx5_ifc_roce_addr_layout_bits roce_address; 4018 }; 4019 4020 struct mlx5_ifc_query_roce_address_in_bits { 4021 u8 opcode[0x10]; 4022 u8 reserved_at_10[0x10]; 4023 4024 u8 reserved_at_20[0x10]; 4025 u8 op_mod[0x10]; 4026 4027 u8 roce_address_index[0x10]; 4028 u8 reserved_at_50[0xc]; 4029 u8 vhca_port_num[0x4]; 4030 4031 u8 reserved_at_60[0x20]; 4032 }; 4033 4034 struct mlx5_ifc_query_rmp_out_bits { 4035 u8 status[0x8]; 4036 u8 reserved_at_8[0x18]; 4037 4038 u8 syndrome[0x20]; 4039 4040 u8 reserved_at_40[0xc0]; 4041 4042 struct mlx5_ifc_rmpc_bits rmp_context; 4043 }; 4044 4045 struct mlx5_ifc_query_rmp_in_bits { 4046 u8 opcode[0x10]; 4047 u8 reserved_at_10[0x10]; 4048 4049 u8 reserved_at_20[0x10]; 4050 u8 op_mod[0x10]; 4051 4052 u8 reserved_at_40[0x8]; 4053 u8 rmpn[0x18]; 4054 4055 u8 reserved_at_60[0x20]; 4056 }; 4057 4058 struct mlx5_ifc_query_qp_out_bits { 4059 u8 status[0x8]; 4060 u8 reserved_at_8[0x18]; 4061 4062 u8 syndrome[0x20]; 4063 4064 u8 reserved_at_40[0x40]; 4065 4066 u8 opt_param_mask[0x20]; 4067 4068 u8 reserved_at_a0[0x20]; 4069 4070 struct mlx5_ifc_qpc_bits qpc; 4071 4072 u8 reserved_at_800[0x80]; 4073 4074 u8 pas[0][0x40]; 4075 }; 4076 4077 struct mlx5_ifc_query_qp_in_bits { 4078 u8 opcode[0x10]; 4079 u8 reserved_at_10[0x10]; 4080 4081 u8 reserved_at_20[0x10]; 4082 u8 op_mod[0x10]; 4083 4084 u8 reserved_at_40[0x8]; 4085 u8 qpn[0x18]; 4086 4087 u8 reserved_at_60[0x20]; 4088 }; 4089 4090 struct mlx5_ifc_query_q_counter_out_bits { 4091 u8 status[0x8]; 4092 u8 reserved_at_8[0x18]; 4093 4094 u8 syndrome[0x20]; 4095 4096 u8 reserved_at_40[0x40]; 4097 4098 u8 rx_write_requests[0x20]; 4099 4100 u8 reserved_at_a0[0x20]; 4101 4102 u8 rx_read_requests[0x20]; 4103 4104 u8 reserved_at_e0[0x20]; 4105 4106 u8 rx_atomic_requests[0x20]; 4107 4108 u8 reserved_at_120[0x20]; 4109 4110 u8 rx_dct_connect[0x20]; 4111 4112 u8 reserved_at_160[0x20]; 4113 4114 u8 out_of_buffer[0x20]; 4115 4116 u8 reserved_at_1a0[0x20]; 4117 4118 u8 out_of_sequence[0x20]; 4119 4120 u8 reserved_at_1e0[0x20]; 4121 4122 u8 duplicate_request[0x20]; 4123 4124 u8 reserved_at_220[0x20]; 4125 4126 u8 rnr_nak_retry_err[0x20]; 4127 4128 u8 reserved_at_260[0x20]; 4129 4130 u8 packet_seq_err[0x20]; 4131 4132 u8 reserved_at_2a0[0x20]; 4133 4134 u8 implied_nak_seq_err[0x20]; 4135 4136 u8 reserved_at_2e0[0x20]; 4137 4138 u8 local_ack_timeout_err[0x20]; 4139 4140 u8 reserved_at_320[0xa0]; 4141 4142 u8 resp_local_length_error[0x20]; 4143 4144 u8 req_local_length_error[0x20]; 4145 4146 u8 resp_local_qp_error[0x20]; 4147 4148 u8 local_operation_error[0x20]; 4149 4150 u8 resp_local_protection[0x20]; 4151 4152 u8 req_local_protection[0x20]; 4153 4154 u8 resp_cqe_error[0x20]; 4155 4156 u8 req_cqe_error[0x20]; 4157 4158 u8 req_mw_binding[0x20]; 4159 4160 u8 req_bad_response[0x20]; 4161 4162 u8 req_remote_invalid_request[0x20]; 4163 4164 u8 resp_remote_invalid_request[0x20]; 4165 4166 u8 req_remote_access_errors[0x20]; 4167 4168 u8 resp_remote_access_errors[0x20]; 4169 4170 u8 req_remote_operation_errors[0x20]; 4171 4172 u8 req_transport_retries_exceeded[0x20]; 4173 4174 u8 cq_overflow[0x20]; 4175 4176 u8 resp_cqe_flush_error[0x20]; 4177 4178 u8 req_cqe_flush_error[0x20]; 4179 4180 u8 reserved_at_620[0x1e0]; 4181 }; 4182 4183 struct mlx5_ifc_query_q_counter_in_bits { 4184 u8 opcode[0x10]; 4185 u8 reserved_at_10[0x10]; 4186 4187 u8 reserved_at_20[0x10]; 4188 u8 op_mod[0x10]; 4189 4190 u8 reserved_at_40[0x80]; 4191 4192 u8 clear[0x1]; 4193 u8 reserved_at_c1[0x1f]; 4194 4195 u8 reserved_at_e0[0x18]; 4196 u8 counter_set_id[0x8]; 4197 }; 4198 4199 struct mlx5_ifc_query_pages_out_bits { 4200 u8 status[0x8]; 4201 u8 reserved_at_8[0x18]; 4202 4203 u8 syndrome[0x20]; 4204 4205 u8 reserved_at_40[0x10]; 4206 u8 function_id[0x10]; 4207 4208 u8 num_pages[0x20]; 4209 }; 4210 4211 enum { 4212 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1, 4213 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2, 4214 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3, 4215 }; 4216 4217 struct mlx5_ifc_query_pages_in_bits { 4218 u8 opcode[0x10]; 4219 u8 reserved_at_10[0x10]; 4220 4221 u8 reserved_at_20[0x10]; 4222 u8 op_mod[0x10]; 4223 4224 u8 reserved_at_40[0x10]; 4225 u8 function_id[0x10]; 4226 4227 u8 reserved_at_60[0x20]; 4228 }; 4229 4230 struct mlx5_ifc_query_nic_vport_context_out_bits { 4231 u8 status[0x8]; 4232 u8 reserved_at_8[0x18]; 4233 4234 u8 syndrome[0x20]; 4235 4236 u8 reserved_at_40[0x40]; 4237 4238 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 4239 }; 4240 4241 struct mlx5_ifc_query_nic_vport_context_in_bits { 4242 u8 opcode[0x10]; 4243 u8 reserved_at_10[0x10]; 4244 4245 u8 reserved_at_20[0x10]; 4246 u8 op_mod[0x10]; 4247 4248 u8 other_vport[0x1]; 4249 u8 reserved_at_41[0xf]; 4250 u8 vport_number[0x10]; 4251 4252 u8 reserved_at_60[0x5]; 4253 u8 allowed_list_type[0x3]; 4254 u8 reserved_at_68[0x18]; 4255 }; 4256 4257 struct mlx5_ifc_query_mkey_out_bits { 4258 u8 status[0x8]; 4259 u8 reserved_at_8[0x18]; 4260 4261 u8 syndrome[0x20]; 4262 4263 u8 reserved_at_40[0x40]; 4264 4265 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 4266 4267 u8 reserved_at_280[0x600]; 4268 4269 u8 bsf0_klm0_pas_mtt0_1[16][0x8]; 4270 4271 u8 bsf1_klm1_pas_mtt2_3[16][0x8]; 4272 }; 4273 4274 struct mlx5_ifc_query_mkey_in_bits { 4275 u8 opcode[0x10]; 4276 u8 reserved_at_10[0x10]; 4277 4278 u8 reserved_at_20[0x10]; 4279 u8 op_mod[0x10]; 4280 4281 u8 reserved_at_40[0x8]; 4282 u8 mkey_index[0x18]; 4283 4284 u8 pg_access[0x1]; 4285 u8 reserved_at_61[0x1f]; 4286 }; 4287 4288 struct mlx5_ifc_query_mad_demux_out_bits { 4289 u8 status[0x8]; 4290 u8 reserved_at_8[0x18]; 4291 4292 u8 syndrome[0x20]; 4293 4294 u8 reserved_at_40[0x40]; 4295 4296 u8 mad_dumux_parameters_block[0x20]; 4297 }; 4298 4299 struct mlx5_ifc_query_mad_demux_in_bits { 4300 u8 opcode[0x10]; 4301 u8 reserved_at_10[0x10]; 4302 4303 u8 reserved_at_20[0x10]; 4304 u8 op_mod[0x10]; 4305 4306 u8 reserved_at_40[0x40]; 4307 }; 4308 4309 struct mlx5_ifc_query_l2_table_entry_out_bits { 4310 u8 status[0x8]; 4311 u8 reserved_at_8[0x18]; 4312 4313 u8 syndrome[0x20]; 4314 4315 u8 reserved_at_40[0xa0]; 4316 4317 u8 reserved_at_e0[0x13]; 4318 u8 vlan_valid[0x1]; 4319 u8 vlan[0xc]; 4320 4321 struct mlx5_ifc_mac_address_layout_bits mac_address; 4322 4323 u8 reserved_at_140[0xc0]; 4324 }; 4325 4326 struct mlx5_ifc_query_l2_table_entry_in_bits { 4327 u8 opcode[0x10]; 4328 u8 reserved_at_10[0x10]; 4329 4330 u8 reserved_at_20[0x10]; 4331 u8 op_mod[0x10]; 4332 4333 u8 reserved_at_40[0x60]; 4334 4335 u8 reserved_at_a0[0x8]; 4336 u8 table_index[0x18]; 4337 4338 u8 reserved_at_c0[0x140]; 4339 }; 4340 4341 struct mlx5_ifc_query_issi_out_bits { 4342 u8 status[0x8]; 4343 u8 reserved_at_8[0x18]; 4344 4345 u8 syndrome[0x20]; 4346 4347 u8 reserved_at_40[0x10]; 4348 u8 current_issi[0x10]; 4349 4350 u8 reserved_at_60[0xa0]; 4351 4352 u8 reserved_at_100[76][0x8]; 4353 u8 supported_issi_dw0[0x20]; 4354 }; 4355 4356 struct mlx5_ifc_query_issi_in_bits { 4357 u8 opcode[0x10]; 4358 u8 reserved_at_10[0x10]; 4359 4360 u8 reserved_at_20[0x10]; 4361 u8 op_mod[0x10]; 4362 4363 u8 reserved_at_40[0x40]; 4364 }; 4365 4366 struct mlx5_ifc_set_driver_version_out_bits { 4367 u8 status[0x8]; 4368 u8 reserved_0[0x18]; 4369 4370 u8 syndrome[0x20]; 4371 u8 reserved_1[0x40]; 4372 }; 4373 4374 struct mlx5_ifc_set_driver_version_in_bits { 4375 u8 opcode[0x10]; 4376 u8 reserved_0[0x10]; 4377 4378 u8 reserved_1[0x10]; 4379 u8 op_mod[0x10]; 4380 4381 u8 reserved_2[0x40]; 4382 u8 driver_version[64][0x8]; 4383 }; 4384 4385 struct mlx5_ifc_query_hca_vport_pkey_out_bits { 4386 u8 status[0x8]; 4387 u8 reserved_at_8[0x18]; 4388 4389 u8 syndrome[0x20]; 4390 4391 u8 reserved_at_40[0x40]; 4392 4393 struct mlx5_ifc_pkey_bits pkey[0]; 4394 }; 4395 4396 struct mlx5_ifc_query_hca_vport_pkey_in_bits { 4397 u8 opcode[0x10]; 4398 u8 reserved_at_10[0x10]; 4399 4400 u8 reserved_at_20[0x10]; 4401 u8 op_mod[0x10]; 4402 4403 u8 other_vport[0x1]; 4404 u8 reserved_at_41[0xb]; 4405 u8 port_num[0x4]; 4406 u8 vport_number[0x10]; 4407 4408 u8 reserved_at_60[0x10]; 4409 u8 pkey_index[0x10]; 4410 }; 4411 4412 enum { 4413 MLX5_HCA_VPORT_SEL_PORT_GUID = 1 << 0, 4414 MLX5_HCA_VPORT_SEL_NODE_GUID = 1 << 1, 4415 MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2, 4416 }; 4417 4418 struct mlx5_ifc_query_hca_vport_gid_out_bits { 4419 u8 status[0x8]; 4420 u8 reserved_at_8[0x18]; 4421 4422 u8 syndrome[0x20]; 4423 4424 u8 reserved_at_40[0x20]; 4425 4426 u8 gids_num[0x10]; 4427 u8 reserved_at_70[0x10]; 4428 4429 struct mlx5_ifc_array128_auto_bits gid[0]; 4430 }; 4431 4432 struct mlx5_ifc_query_hca_vport_gid_in_bits { 4433 u8 opcode[0x10]; 4434 u8 reserved_at_10[0x10]; 4435 4436 u8 reserved_at_20[0x10]; 4437 u8 op_mod[0x10]; 4438 4439 u8 other_vport[0x1]; 4440 u8 reserved_at_41[0xb]; 4441 u8 port_num[0x4]; 4442 u8 vport_number[0x10]; 4443 4444 u8 reserved_at_60[0x10]; 4445 u8 gid_index[0x10]; 4446 }; 4447 4448 struct mlx5_ifc_query_hca_vport_context_out_bits { 4449 u8 status[0x8]; 4450 u8 reserved_at_8[0x18]; 4451 4452 u8 syndrome[0x20]; 4453 4454 u8 reserved_at_40[0x40]; 4455 4456 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 4457 }; 4458 4459 struct mlx5_ifc_query_hca_vport_context_in_bits { 4460 u8 opcode[0x10]; 4461 u8 reserved_at_10[0x10]; 4462 4463 u8 reserved_at_20[0x10]; 4464 u8 op_mod[0x10]; 4465 4466 u8 other_vport[0x1]; 4467 u8 reserved_at_41[0xb]; 4468 u8 port_num[0x4]; 4469 u8 vport_number[0x10]; 4470 4471 u8 reserved_at_60[0x20]; 4472 }; 4473 4474 struct mlx5_ifc_query_hca_cap_out_bits { 4475 u8 status[0x8]; 4476 u8 reserved_at_8[0x18]; 4477 4478 u8 syndrome[0x20]; 4479 4480 u8 reserved_at_40[0x40]; 4481 4482 union mlx5_ifc_hca_cap_union_bits capability; 4483 }; 4484 4485 struct mlx5_ifc_query_hca_cap_in_bits { 4486 u8 opcode[0x10]; 4487 u8 reserved_at_10[0x10]; 4488 4489 u8 reserved_at_20[0x10]; 4490 u8 op_mod[0x10]; 4491 4492 u8 reserved_at_40[0x40]; 4493 }; 4494 4495 struct mlx5_ifc_query_flow_table_out_bits { 4496 u8 status[0x8]; 4497 u8 reserved_at_8[0x18]; 4498 4499 u8 syndrome[0x20]; 4500 4501 u8 reserved_at_40[0x80]; 4502 4503 u8 reserved_at_c0[0x8]; 4504 u8 level[0x8]; 4505 u8 reserved_at_d0[0x8]; 4506 u8 log_size[0x8]; 4507 4508 u8 reserved_at_e0[0x120]; 4509 }; 4510 4511 struct mlx5_ifc_query_flow_table_in_bits { 4512 u8 opcode[0x10]; 4513 u8 reserved_at_10[0x10]; 4514 4515 u8 reserved_at_20[0x10]; 4516 u8 op_mod[0x10]; 4517 4518 u8 reserved_at_40[0x40]; 4519 4520 u8 table_type[0x8]; 4521 u8 reserved_at_88[0x18]; 4522 4523 u8 reserved_at_a0[0x8]; 4524 u8 table_id[0x18]; 4525 4526 u8 reserved_at_c0[0x140]; 4527 }; 4528 4529 struct mlx5_ifc_query_fte_out_bits { 4530 u8 status[0x8]; 4531 u8 reserved_at_8[0x18]; 4532 4533 u8 syndrome[0x20]; 4534 4535 u8 reserved_at_40[0x1c0]; 4536 4537 struct mlx5_ifc_flow_context_bits flow_context; 4538 }; 4539 4540 struct mlx5_ifc_query_fte_in_bits { 4541 u8 opcode[0x10]; 4542 u8 reserved_at_10[0x10]; 4543 4544 u8 reserved_at_20[0x10]; 4545 u8 op_mod[0x10]; 4546 4547 u8 reserved_at_40[0x40]; 4548 4549 u8 table_type[0x8]; 4550 u8 reserved_at_88[0x18]; 4551 4552 u8 reserved_at_a0[0x8]; 4553 u8 table_id[0x18]; 4554 4555 u8 reserved_at_c0[0x40]; 4556 4557 u8 flow_index[0x20]; 4558 4559 u8 reserved_at_120[0xe0]; 4560 }; 4561 4562 enum { 4563 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 4564 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 4565 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 4566 }; 4567 4568 struct mlx5_ifc_query_flow_group_out_bits { 4569 u8 status[0x8]; 4570 u8 reserved_at_8[0x18]; 4571 4572 u8 syndrome[0x20]; 4573 4574 u8 reserved_at_40[0xa0]; 4575 4576 u8 start_flow_index[0x20]; 4577 4578 u8 reserved_at_100[0x20]; 4579 4580 u8 end_flow_index[0x20]; 4581 4582 u8 reserved_at_140[0xa0]; 4583 4584 u8 reserved_at_1e0[0x18]; 4585 u8 match_criteria_enable[0x8]; 4586 4587 struct mlx5_ifc_fte_match_param_bits match_criteria; 4588 4589 u8 reserved_at_1200[0xe00]; 4590 }; 4591 4592 struct mlx5_ifc_query_flow_group_in_bits { 4593 u8 opcode[0x10]; 4594 u8 reserved_at_10[0x10]; 4595 4596 u8 reserved_at_20[0x10]; 4597 u8 op_mod[0x10]; 4598 4599 u8 reserved_at_40[0x40]; 4600 4601 u8 table_type[0x8]; 4602 u8 reserved_at_88[0x18]; 4603 4604 u8 reserved_at_a0[0x8]; 4605 u8 table_id[0x18]; 4606 4607 u8 group_id[0x20]; 4608 4609 u8 reserved_at_e0[0x120]; 4610 }; 4611 4612 struct mlx5_ifc_query_flow_counter_out_bits { 4613 u8 status[0x8]; 4614 u8 reserved_at_8[0x18]; 4615 4616 u8 syndrome[0x20]; 4617 4618 u8 reserved_at_40[0x40]; 4619 4620 struct mlx5_ifc_traffic_counter_bits flow_statistics[0]; 4621 }; 4622 4623 struct mlx5_ifc_query_flow_counter_in_bits { 4624 u8 opcode[0x10]; 4625 u8 reserved_at_10[0x10]; 4626 4627 u8 reserved_at_20[0x10]; 4628 u8 op_mod[0x10]; 4629 4630 u8 reserved_at_40[0x80]; 4631 4632 u8 clear[0x1]; 4633 u8 reserved_at_c1[0xf]; 4634 u8 num_of_counters[0x10]; 4635 4636 u8 flow_counter_id[0x20]; 4637 }; 4638 4639 struct mlx5_ifc_query_esw_vport_context_out_bits { 4640 u8 status[0x8]; 4641 u8 reserved_at_8[0x18]; 4642 4643 u8 syndrome[0x20]; 4644 4645 u8 reserved_at_40[0x40]; 4646 4647 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 4648 }; 4649 4650 struct mlx5_ifc_query_esw_vport_context_in_bits { 4651 u8 opcode[0x10]; 4652 u8 reserved_at_10[0x10]; 4653 4654 u8 reserved_at_20[0x10]; 4655 u8 op_mod[0x10]; 4656 4657 u8 other_vport[0x1]; 4658 u8 reserved_at_41[0xf]; 4659 u8 vport_number[0x10]; 4660 4661 u8 reserved_at_60[0x20]; 4662 }; 4663 4664 struct mlx5_ifc_modify_esw_vport_context_out_bits { 4665 u8 status[0x8]; 4666 u8 reserved_at_8[0x18]; 4667 4668 u8 syndrome[0x20]; 4669 4670 u8 reserved_at_40[0x40]; 4671 }; 4672 4673 struct mlx5_ifc_esw_vport_context_fields_select_bits { 4674 u8 reserved_at_0[0x1c]; 4675 u8 vport_cvlan_insert[0x1]; 4676 u8 vport_svlan_insert[0x1]; 4677 u8 vport_cvlan_strip[0x1]; 4678 u8 vport_svlan_strip[0x1]; 4679 }; 4680 4681 struct mlx5_ifc_modify_esw_vport_context_in_bits { 4682 u8 opcode[0x10]; 4683 u8 reserved_at_10[0x10]; 4684 4685 u8 reserved_at_20[0x10]; 4686 u8 op_mod[0x10]; 4687 4688 u8 other_vport[0x1]; 4689 u8 reserved_at_41[0xf]; 4690 u8 vport_number[0x10]; 4691 4692 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select; 4693 4694 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 4695 }; 4696 4697 struct mlx5_ifc_query_eq_out_bits { 4698 u8 status[0x8]; 4699 u8 reserved_at_8[0x18]; 4700 4701 u8 syndrome[0x20]; 4702 4703 u8 reserved_at_40[0x40]; 4704 4705 struct mlx5_ifc_eqc_bits eq_context_entry; 4706 4707 u8 reserved_at_280[0x40]; 4708 4709 u8 event_bitmask[0x40]; 4710 4711 u8 reserved_at_300[0x580]; 4712 4713 u8 pas[0][0x40]; 4714 }; 4715 4716 struct mlx5_ifc_query_eq_in_bits { 4717 u8 opcode[0x10]; 4718 u8 reserved_at_10[0x10]; 4719 4720 u8 reserved_at_20[0x10]; 4721 u8 op_mod[0x10]; 4722 4723 u8 reserved_at_40[0x18]; 4724 u8 eq_number[0x8]; 4725 4726 u8 reserved_at_60[0x20]; 4727 }; 4728 4729 struct mlx5_ifc_encap_header_in_bits { 4730 u8 reserved_at_0[0x5]; 4731 u8 header_type[0x3]; 4732 u8 reserved_at_8[0xe]; 4733 u8 encap_header_size[0xa]; 4734 4735 u8 reserved_at_20[0x10]; 4736 u8 encap_header[2][0x8]; 4737 4738 u8 more_encap_header[0][0x8]; 4739 }; 4740 4741 struct mlx5_ifc_query_encap_header_out_bits { 4742 u8 status[0x8]; 4743 u8 reserved_at_8[0x18]; 4744 4745 u8 syndrome[0x20]; 4746 4747 u8 reserved_at_40[0xa0]; 4748 4749 struct mlx5_ifc_encap_header_in_bits encap_header[0]; 4750 }; 4751 4752 struct mlx5_ifc_query_encap_header_in_bits { 4753 u8 opcode[0x10]; 4754 u8 reserved_at_10[0x10]; 4755 4756 u8 reserved_at_20[0x10]; 4757 u8 op_mod[0x10]; 4758 4759 u8 encap_id[0x20]; 4760 4761 u8 reserved_at_60[0xa0]; 4762 }; 4763 4764 struct mlx5_ifc_alloc_encap_header_out_bits { 4765 u8 status[0x8]; 4766 u8 reserved_at_8[0x18]; 4767 4768 u8 syndrome[0x20]; 4769 4770 u8 encap_id[0x20]; 4771 4772 u8 reserved_at_60[0x20]; 4773 }; 4774 4775 struct mlx5_ifc_alloc_encap_header_in_bits { 4776 u8 opcode[0x10]; 4777 u8 reserved_at_10[0x10]; 4778 4779 u8 reserved_at_20[0x10]; 4780 u8 op_mod[0x10]; 4781 4782 u8 reserved_at_40[0xa0]; 4783 4784 struct mlx5_ifc_encap_header_in_bits encap_header; 4785 }; 4786 4787 struct mlx5_ifc_dealloc_encap_header_out_bits { 4788 u8 status[0x8]; 4789 u8 reserved_at_8[0x18]; 4790 4791 u8 syndrome[0x20]; 4792 4793 u8 reserved_at_40[0x40]; 4794 }; 4795 4796 struct mlx5_ifc_dealloc_encap_header_in_bits { 4797 u8 opcode[0x10]; 4798 u8 reserved_at_10[0x10]; 4799 4800 u8 reserved_20[0x10]; 4801 u8 op_mod[0x10]; 4802 4803 u8 encap_id[0x20]; 4804 4805 u8 reserved_60[0x20]; 4806 }; 4807 4808 struct mlx5_ifc_set_action_in_bits { 4809 u8 action_type[0x4]; 4810 u8 field[0xc]; 4811 u8 reserved_at_10[0x3]; 4812 u8 offset[0x5]; 4813 u8 reserved_at_18[0x3]; 4814 u8 length[0x5]; 4815 4816 u8 data[0x20]; 4817 }; 4818 4819 struct mlx5_ifc_add_action_in_bits { 4820 u8 action_type[0x4]; 4821 u8 field[0xc]; 4822 u8 reserved_at_10[0x10]; 4823 4824 u8 data[0x20]; 4825 }; 4826 4827 union mlx5_ifc_set_action_in_add_action_in_auto_bits { 4828 struct mlx5_ifc_set_action_in_bits set_action_in; 4829 struct mlx5_ifc_add_action_in_bits add_action_in; 4830 u8 reserved_at_0[0x40]; 4831 }; 4832 4833 enum { 4834 MLX5_ACTION_TYPE_SET = 0x1, 4835 MLX5_ACTION_TYPE_ADD = 0x2, 4836 }; 4837 4838 enum { 4839 MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16 = 0x1, 4840 MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0 = 0x2, 4841 MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE = 0x3, 4842 MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16 = 0x4, 4843 MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0 = 0x5, 4844 MLX5_ACTION_IN_FIELD_OUT_IP_DSCP = 0x6, 4845 MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS = 0x7, 4846 MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT = 0x8, 4847 MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT = 0x9, 4848 MLX5_ACTION_IN_FIELD_OUT_IP_TTL = 0xa, 4849 MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT = 0xb, 4850 MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT = 0xc, 4851 MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96 = 0xd, 4852 MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64 = 0xe, 4853 MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32 = 0xf, 4854 MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0 = 0x10, 4855 MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96 = 0x11, 4856 MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64 = 0x12, 4857 MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32 = 0x13, 4858 MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0 = 0x14, 4859 MLX5_ACTION_IN_FIELD_OUT_SIPV4 = 0x15, 4860 MLX5_ACTION_IN_FIELD_OUT_DIPV4 = 0x16, 4861 MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47, 4862 }; 4863 4864 struct mlx5_ifc_alloc_modify_header_context_out_bits { 4865 u8 status[0x8]; 4866 u8 reserved_at_8[0x18]; 4867 4868 u8 syndrome[0x20]; 4869 4870 u8 modify_header_id[0x20]; 4871 4872 u8 reserved_at_60[0x20]; 4873 }; 4874 4875 struct mlx5_ifc_alloc_modify_header_context_in_bits { 4876 u8 opcode[0x10]; 4877 u8 reserved_at_10[0x10]; 4878 4879 u8 reserved_at_20[0x10]; 4880 u8 op_mod[0x10]; 4881 4882 u8 reserved_at_40[0x20]; 4883 4884 u8 table_type[0x8]; 4885 u8 reserved_at_68[0x10]; 4886 u8 num_of_actions[0x8]; 4887 4888 union mlx5_ifc_set_action_in_add_action_in_auto_bits actions[0]; 4889 }; 4890 4891 struct mlx5_ifc_dealloc_modify_header_context_out_bits { 4892 u8 status[0x8]; 4893 u8 reserved_at_8[0x18]; 4894 4895 u8 syndrome[0x20]; 4896 4897 u8 reserved_at_40[0x40]; 4898 }; 4899 4900 struct mlx5_ifc_dealloc_modify_header_context_in_bits { 4901 u8 opcode[0x10]; 4902 u8 reserved_at_10[0x10]; 4903 4904 u8 reserved_at_20[0x10]; 4905 u8 op_mod[0x10]; 4906 4907 u8 modify_header_id[0x20]; 4908 4909 u8 reserved_at_60[0x20]; 4910 }; 4911 4912 struct mlx5_ifc_query_dct_out_bits { 4913 u8 status[0x8]; 4914 u8 reserved_at_8[0x18]; 4915 4916 u8 syndrome[0x20]; 4917 4918 u8 reserved_at_40[0x40]; 4919 4920 struct mlx5_ifc_dctc_bits dct_context_entry; 4921 4922 u8 reserved_at_280[0x180]; 4923 }; 4924 4925 struct mlx5_ifc_query_dct_in_bits { 4926 u8 opcode[0x10]; 4927 u8 reserved_at_10[0x10]; 4928 4929 u8 reserved_at_20[0x10]; 4930 u8 op_mod[0x10]; 4931 4932 u8 reserved_at_40[0x8]; 4933 u8 dctn[0x18]; 4934 4935 u8 reserved_at_60[0x20]; 4936 }; 4937 4938 struct mlx5_ifc_query_cq_out_bits { 4939 u8 status[0x8]; 4940 u8 reserved_at_8[0x18]; 4941 4942 u8 syndrome[0x20]; 4943 4944 u8 reserved_at_40[0x40]; 4945 4946 struct mlx5_ifc_cqc_bits cq_context; 4947 4948 u8 reserved_at_280[0x600]; 4949 4950 u8 pas[0][0x40]; 4951 }; 4952 4953 struct mlx5_ifc_query_cq_in_bits { 4954 u8 opcode[0x10]; 4955 u8 reserved_at_10[0x10]; 4956 4957 u8 reserved_at_20[0x10]; 4958 u8 op_mod[0x10]; 4959 4960 u8 reserved_at_40[0x8]; 4961 u8 cqn[0x18]; 4962 4963 u8 reserved_at_60[0x20]; 4964 }; 4965 4966 struct mlx5_ifc_query_cong_status_out_bits { 4967 u8 status[0x8]; 4968 u8 reserved_at_8[0x18]; 4969 4970 u8 syndrome[0x20]; 4971 4972 u8 reserved_at_40[0x20]; 4973 4974 u8 enable[0x1]; 4975 u8 tag_enable[0x1]; 4976 u8 reserved_at_62[0x1e]; 4977 }; 4978 4979 struct mlx5_ifc_query_cong_status_in_bits { 4980 u8 opcode[0x10]; 4981 u8 reserved_at_10[0x10]; 4982 4983 u8 reserved_at_20[0x10]; 4984 u8 op_mod[0x10]; 4985 4986 u8 reserved_at_40[0x18]; 4987 u8 priority[0x4]; 4988 u8 cong_protocol[0x4]; 4989 4990 u8 reserved_at_60[0x20]; 4991 }; 4992 4993 struct mlx5_ifc_query_cong_statistics_out_bits { 4994 u8 status[0x8]; 4995 u8 reserved_at_8[0x18]; 4996 4997 u8 syndrome[0x20]; 4998 4999 u8 reserved_at_40[0x40]; 5000 5001 u8 rp_cur_flows[0x20]; 5002 5003 u8 sum_flows[0x20]; 5004 5005 u8 rp_cnp_ignored_high[0x20]; 5006 5007 u8 rp_cnp_ignored_low[0x20]; 5008 5009 u8 rp_cnp_handled_high[0x20]; 5010 5011 u8 rp_cnp_handled_low[0x20]; 5012 5013 u8 reserved_at_140[0x100]; 5014 5015 u8 time_stamp_high[0x20]; 5016 5017 u8 time_stamp_low[0x20]; 5018 5019 u8 accumulators_period[0x20]; 5020 5021 u8 np_ecn_marked_roce_packets_high[0x20]; 5022 5023 u8 np_ecn_marked_roce_packets_low[0x20]; 5024 5025 u8 np_cnp_sent_high[0x20]; 5026 5027 u8 np_cnp_sent_low[0x20]; 5028 5029 u8 reserved_at_320[0x560]; 5030 }; 5031 5032 struct mlx5_ifc_query_cong_statistics_in_bits { 5033 u8 opcode[0x10]; 5034 u8 reserved_at_10[0x10]; 5035 5036 u8 reserved_at_20[0x10]; 5037 u8 op_mod[0x10]; 5038 5039 u8 clear[0x1]; 5040 u8 reserved_at_41[0x1f]; 5041 5042 u8 reserved_at_60[0x20]; 5043 }; 5044 5045 struct mlx5_ifc_query_cong_params_out_bits { 5046 u8 status[0x8]; 5047 u8 reserved_at_8[0x18]; 5048 5049 u8 syndrome[0x20]; 5050 5051 u8 reserved_at_40[0x40]; 5052 5053 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 5054 }; 5055 5056 struct mlx5_ifc_query_cong_params_in_bits { 5057 u8 opcode[0x10]; 5058 u8 reserved_at_10[0x10]; 5059 5060 u8 reserved_at_20[0x10]; 5061 u8 op_mod[0x10]; 5062 5063 u8 reserved_at_40[0x1c]; 5064 u8 cong_protocol[0x4]; 5065 5066 u8 reserved_at_60[0x20]; 5067 }; 5068 5069 struct mlx5_ifc_query_adapter_out_bits { 5070 u8 status[0x8]; 5071 u8 reserved_at_8[0x18]; 5072 5073 u8 syndrome[0x20]; 5074 5075 u8 reserved_at_40[0x40]; 5076 5077 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct; 5078 }; 5079 5080 struct mlx5_ifc_query_adapter_in_bits { 5081 u8 opcode[0x10]; 5082 u8 reserved_at_10[0x10]; 5083 5084 u8 reserved_at_20[0x10]; 5085 u8 op_mod[0x10]; 5086 5087 u8 reserved_at_40[0x40]; 5088 }; 5089 5090 struct mlx5_ifc_qp_2rst_out_bits { 5091 u8 status[0x8]; 5092 u8 reserved_at_8[0x18]; 5093 5094 u8 syndrome[0x20]; 5095 5096 u8 reserved_at_40[0x40]; 5097 }; 5098 5099 struct mlx5_ifc_qp_2rst_in_bits { 5100 u8 opcode[0x10]; 5101 u8 reserved_at_10[0x10]; 5102 5103 u8 reserved_at_20[0x10]; 5104 u8 op_mod[0x10]; 5105 5106 u8 reserved_at_40[0x8]; 5107 u8 qpn[0x18]; 5108 5109 u8 reserved_at_60[0x20]; 5110 }; 5111 5112 struct mlx5_ifc_qp_2err_out_bits { 5113 u8 status[0x8]; 5114 u8 reserved_at_8[0x18]; 5115 5116 u8 syndrome[0x20]; 5117 5118 u8 reserved_at_40[0x40]; 5119 }; 5120 5121 struct mlx5_ifc_qp_2err_in_bits { 5122 u8 opcode[0x10]; 5123 u8 reserved_at_10[0x10]; 5124 5125 u8 reserved_at_20[0x10]; 5126 u8 op_mod[0x10]; 5127 5128 u8 reserved_at_40[0x8]; 5129 u8 qpn[0x18]; 5130 5131 u8 reserved_at_60[0x20]; 5132 }; 5133 5134 struct mlx5_ifc_page_fault_resume_out_bits { 5135 u8 status[0x8]; 5136 u8 reserved_at_8[0x18]; 5137 5138 u8 syndrome[0x20]; 5139 5140 u8 reserved_at_40[0x40]; 5141 }; 5142 5143 struct mlx5_ifc_page_fault_resume_in_bits { 5144 u8 opcode[0x10]; 5145 u8 reserved_at_10[0x10]; 5146 5147 u8 reserved_at_20[0x10]; 5148 u8 op_mod[0x10]; 5149 5150 u8 error[0x1]; 5151 u8 reserved_at_41[0x4]; 5152 u8 page_fault_type[0x3]; 5153 u8 wq_number[0x18]; 5154 5155 u8 reserved_at_60[0x8]; 5156 u8 token[0x18]; 5157 }; 5158 5159 struct mlx5_ifc_nop_out_bits { 5160 u8 status[0x8]; 5161 u8 reserved_at_8[0x18]; 5162 5163 u8 syndrome[0x20]; 5164 5165 u8 reserved_at_40[0x40]; 5166 }; 5167 5168 struct mlx5_ifc_nop_in_bits { 5169 u8 opcode[0x10]; 5170 u8 reserved_at_10[0x10]; 5171 5172 u8 reserved_at_20[0x10]; 5173 u8 op_mod[0x10]; 5174 5175 u8 reserved_at_40[0x40]; 5176 }; 5177 5178 struct mlx5_ifc_modify_vport_state_out_bits { 5179 u8 status[0x8]; 5180 u8 reserved_at_8[0x18]; 5181 5182 u8 syndrome[0x20]; 5183 5184 u8 reserved_at_40[0x40]; 5185 }; 5186 5187 struct mlx5_ifc_modify_vport_state_in_bits { 5188 u8 opcode[0x10]; 5189 u8 reserved_at_10[0x10]; 5190 5191 u8 reserved_at_20[0x10]; 5192 u8 op_mod[0x10]; 5193 5194 u8 other_vport[0x1]; 5195 u8 reserved_at_41[0xf]; 5196 u8 vport_number[0x10]; 5197 5198 u8 reserved_at_60[0x18]; 5199 u8 admin_state[0x4]; 5200 u8 reserved_at_7c[0x4]; 5201 }; 5202 5203 struct mlx5_ifc_modify_tis_out_bits { 5204 u8 status[0x8]; 5205 u8 reserved_at_8[0x18]; 5206 5207 u8 syndrome[0x20]; 5208 5209 u8 reserved_at_40[0x40]; 5210 }; 5211 5212 struct mlx5_ifc_modify_tis_bitmask_bits { 5213 u8 reserved_at_0[0x20]; 5214 5215 u8 reserved_at_20[0x1d]; 5216 u8 lag_tx_port_affinity[0x1]; 5217 u8 strict_lag_tx_port_affinity[0x1]; 5218 u8 prio[0x1]; 5219 }; 5220 5221 struct mlx5_ifc_modify_tis_in_bits { 5222 u8 opcode[0x10]; 5223 u8 reserved_at_10[0x10]; 5224 5225 u8 reserved_at_20[0x10]; 5226 u8 op_mod[0x10]; 5227 5228 u8 reserved_at_40[0x8]; 5229 u8 tisn[0x18]; 5230 5231 u8 reserved_at_60[0x20]; 5232 5233 struct mlx5_ifc_modify_tis_bitmask_bits bitmask; 5234 5235 u8 reserved_at_c0[0x40]; 5236 5237 struct mlx5_ifc_tisc_bits ctx; 5238 }; 5239 5240 struct mlx5_ifc_modify_tir_bitmask_bits { 5241 u8 reserved_at_0[0x20]; 5242 5243 u8 reserved_at_20[0x1b]; 5244 u8 self_lb_en[0x1]; 5245 u8 reserved_at_3c[0x1]; 5246 u8 hash[0x1]; 5247 u8 reserved_at_3e[0x1]; 5248 u8 lro[0x1]; 5249 }; 5250 5251 struct mlx5_ifc_modify_tir_out_bits { 5252 u8 status[0x8]; 5253 u8 reserved_at_8[0x18]; 5254 5255 u8 syndrome[0x20]; 5256 5257 u8 reserved_at_40[0x40]; 5258 }; 5259 5260 struct mlx5_ifc_modify_tir_in_bits { 5261 u8 opcode[0x10]; 5262 u8 reserved_at_10[0x10]; 5263 5264 u8 reserved_at_20[0x10]; 5265 u8 op_mod[0x10]; 5266 5267 u8 reserved_at_40[0x8]; 5268 u8 tirn[0x18]; 5269 5270 u8 reserved_at_60[0x20]; 5271 5272 struct mlx5_ifc_modify_tir_bitmask_bits bitmask; 5273 5274 u8 reserved_at_c0[0x40]; 5275 5276 struct mlx5_ifc_tirc_bits ctx; 5277 }; 5278 5279 struct mlx5_ifc_modify_sq_out_bits { 5280 u8 status[0x8]; 5281 u8 reserved_at_8[0x18]; 5282 5283 u8 syndrome[0x20]; 5284 5285 u8 reserved_at_40[0x40]; 5286 }; 5287 5288 struct mlx5_ifc_modify_sq_in_bits { 5289 u8 opcode[0x10]; 5290 u8 reserved_at_10[0x10]; 5291 5292 u8 reserved_at_20[0x10]; 5293 u8 op_mod[0x10]; 5294 5295 u8 sq_state[0x4]; 5296 u8 reserved_at_44[0x4]; 5297 u8 sqn[0x18]; 5298 5299 u8 reserved_at_60[0x20]; 5300 5301 u8 modify_bitmask[0x40]; 5302 5303 u8 reserved_at_c0[0x40]; 5304 5305 struct mlx5_ifc_sqc_bits ctx; 5306 }; 5307 5308 struct mlx5_ifc_modify_scheduling_element_out_bits { 5309 u8 status[0x8]; 5310 u8 reserved_at_8[0x18]; 5311 5312 u8 syndrome[0x20]; 5313 5314 u8 reserved_at_40[0x1c0]; 5315 }; 5316 5317 enum { 5318 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1, 5319 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2, 5320 }; 5321 5322 struct mlx5_ifc_modify_scheduling_element_in_bits { 5323 u8 opcode[0x10]; 5324 u8 reserved_at_10[0x10]; 5325 5326 u8 reserved_at_20[0x10]; 5327 u8 op_mod[0x10]; 5328 5329 u8 scheduling_hierarchy[0x8]; 5330 u8 reserved_at_48[0x18]; 5331 5332 u8 scheduling_element_id[0x20]; 5333 5334 u8 reserved_at_80[0x20]; 5335 5336 u8 modify_bitmask[0x20]; 5337 5338 u8 reserved_at_c0[0x40]; 5339 5340 struct mlx5_ifc_scheduling_context_bits scheduling_context; 5341 5342 u8 reserved_at_300[0x100]; 5343 }; 5344 5345 struct mlx5_ifc_modify_rqt_out_bits { 5346 u8 status[0x8]; 5347 u8 reserved_at_8[0x18]; 5348 5349 u8 syndrome[0x20]; 5350 5351 u8 reserved_at_40[0x40]; 5352 }; 5353 5354 struct mlx5_ifc_rqt_bitmask_bits { 5355 u8 reserved_at_0[0x20]; 5356 5357 u8 reserved_at_20[0x1f]; 5358 u8 rqn_list[0x1]; 5359 }; 5360 5361 struct mlx5_ifc_modify_rqt_in_bits { 5362 u8 opcode[0x10]; 5363 u8 reserved_at_10[0x10]; 5364 5365 u8 reserved_at_20[0x10]; 5366 u8 op_mod[0x10]; 5367 5368 u8 reserved_at_40[0x8]; 5369 u8 rqtn[0x18]; 5370 5371 u8 reserved_at_60[0x20]; 5372 5373 struct mlx5_ifc_rqt_bitmask_bits bitmask; 5374 5375 u8 reserved_at_c0[0x40]; 5376 5377 struct mlx5_ifc_rqtc_bits ctx; 5378 }; 5379 5380 struct mlx5_ifc_modify_rq_out_bits { 5381 u8 status[0x8]; 5382 u8 reserved_at_8[0x18]; 5383 5384 u8 syndrome[0x20]; 5385 5386 u8 reserved_at_40[0x40]; 5387 }; 5388 5389 enum { 5390 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1, 5391 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2, 5392 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3, 5393 }; 5394 5395 struct mlx5_ifc_modify_rq_in_bits { 5396 u8 opcode[0x10]; 5397 u8 reserved_at_10[0x10]; 5398 5399 u8 reserved_at_20[0x10]; 5400 u8 op_mod[0x10]; 5401 5402 u8 rq_state[0x4]; 5403 u8 reserved_at_44[0x4]; 5404 u8 rqn[0x18]; 5405 5406 u8 reserved_at_60[0x20]; 5407 5408 u8 modify_bitmask[0x40]; 5409 5410 u8 reserved_at_c0[0x40]; 5411 5412 struct mlx5_ifc_rqc_bits ctx; 5413 }; 5414 5415 struct mlx5_ifc_modify_rmp_out_bits { 5416 u8 status[0x8]; 5417 u8 reserved_at_8[0x18]; 5418 5419 u8 syndrome[0x20]; 5420 5421 u8 reserved_at_40[0x40]; 5422 }; 5423 5424 struct mlx5_ifc_rmp_bitmask_bits { 5425 u8 reserved_at_0[0x20]; 5426 5427 u8 reserved_at_20[0x1f]; 5428 u8 lwm[0x1]; 5429 }; 5430 5431 struct mlx5_ifc_modify_rmp_in_bits { 5432 u8 opcode[0x10]; 5433 u8 reserved_at_10[0x10]; 5434 5435 u8 reserved_at_20[0x10]; 5436 u8 op_mod[0x10]; 5437 5438 u8 rmp_state[0x4]; 5439 u8 reserved_at_44[0x4]; 5440 u8 rmpn[0x18]; 5441 5442 u8 reserved_at_60[0x20]; 5443 5444 struct mlx5_ifc_rmp_bitmask_bits bitmask; 5445 5446 u8 reserved_at_c0[0x40]; 5447 5448 struct mlx5_ifc_rmpc_bits ctx; 5449 }; 5450 5451 struct mlx5_ifc_modify_nic_vport_context_out_bits { 5452 u8 status[0x8]; 5453 u8 reserved_at_8[0x18]; 5454 5455 u8 syndrome[0x20]; 5456 5457 u8 reserved_at_40[0x40]; 5458 }; 5459 5460 struct mlx5_ifc_modify_nic_vport_field_select_bits { 5461 u8 reserved_at_0[0x12]; 5462 u8 affiliation[0x1]; 5463 u8 reserved_at_e[0x1]; 5464 u8 disable_uc_local_lb[0x1]; 5465 u8 disable_mc_local_lb[0x1]; 5466 u8 node_guid[0x1]; 5467 u8 port_guid[0x1]; 5468 u8 min_inline[0x1]; 5469 u8 mtu[0x1]; 5470 u8 change_event[0x1]; 5471 u8 promisc[0x1]; 5472 u8 permanent_address[0x1]; 5473 u8 addresses_list[0x1]; 5474 u8 roce_en[0x1]; 5475 u8 reserved_at_1f[0x1]; 5476 }; 5477 5478 struct mlx5_ifc_modify_nic_vport_context_in_bits { 5479 u8 opcode[0x10]; 5480 u8 reserved_at_10[0x10]; 5481 5482 u8 reserved_at_20[0x10]; 5483 u8 op_mod[0x10]; 5484 5485 u8 other_vport[0x1]; 5486 u8 reserved_at_41[0xf]; 5487 u8 vport_number[0x10]; 5488 5489 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select; 5490 5491 u8 reserved_at_80[0x780]; 5492 5493 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 5494 }; 5495 5496 struct mlx5_ifc_modify_hca_vport_context_out_bits { 5497 u8 status[0x8]; 5498 u8 reserved_at_8[0x18]; 5499 5500 u8 syndrome[0x20]; 5501 5502 u8 reserved_at_40[0x40]; 5503 }; 5504 5505 struct mlx5_ifc_modify_hca_vport_context_in_bits { 5506 u8 opcode[0x10]; 5507 u8 reserved_at_10[0x10]; 5508 5509 u8 reserved_at_20[0x10]; 5510 u8 op_mod[0x10]; 5511 5512 u8 other_vport[0x1]; 5513 u8 reserved_at_41[0xb]; 5514 u8 port_num[0x4]; 5515 u8 vport_number[0x10]; 5516 5517 u8 reserved_at_60[0x20]; 5518 5519 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 5520 }; 5521 5522 struct mlx5_ifc_modify_cq_out_bits { 5523 u8 status[0x8]; 5524 u8 reserved_at_8[0x18]; 5525 5526 u8 syndrome[0x20]; 5527 5528 u8 reserved_at_40[0x40]; 5529 }; 5530 5531 enum { 5532 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0, 5533 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1, 5534 }; 5535 5536 struct mlx5_ifc_modify_cq_in_bits { 5537 u8 opcode[0x10]; 5538 u8 reserved_at_10[0x10]; 5539 5540 u8 reserved_at_20[0x10]; 5541 u8 op_mod[0x10]; 5542 5543 u8 reserved_at_40[0x8]; 5544 u8 cqn[0x18]; 5545 5546 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select; 5547 5548 struct mlx5_ifc_cqc_bits cq_context; 5549 5550 u8 reserved_at_280[0x600]; 5551 5552 u8 pas[0][0x40]; 5553 }; 5554 5555 struct mlx5_ifc_modify_cong_status_out_bits { 5556 u8 status[0x8]; 5557 u8 reserved_at_8[0x18]; 5558 5559 u8 syndrome[0x20]; 5560 5561 u8 reserved_at_40[0x40]; 5562 }; 5563 5564 struct mlx5_ifc_modify_cong_status_in_bits { 5565 u8 opcode[0x10]; 5566 u8 reserved_at_10[0x10]; 5567 5568 u8 reserved_at_20[0x10]; 5569 u8 op_mod[0x10]; 5570 5571 u8 reserved_at_40[0x18]; 5572 u8 priority[0x4]; 5573 u8 cong_protocol[0x4]; 5574 5575 u8 enable[0x1]; 5576 u8 tag_enable[0x1]; 5577 u8 reserved_at_62[0x1e]; 5578 }; 5579 5580 struct mlx5_ifc_modify_cong_params_out_bits { 5581 u8 status[0x8]; 5582 u8 reserved_at_8[0x18]; 5583 5584 u8 syndrome[0x20]; 5585 5586 u8 reserved_at_40[0x40]; 5587 }; 5588 5589 struct mlx5_ifc_modify_cong_params_in_bits { 5590 u8 opcode[0x10]; 5591 u8 reserved_at_10[0x10]; 5592 5593 u8 reserved_at_20[0x10]; 5594 u8 op_mod[0x10]; 5595 5596 u8 reserved_at_40[0x1c]; 5597 u8 cong_protocol[0x4]; 5598 5599 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select; 5600 5601 u8 reserved_at_80[0x80]; 5602 5603 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 5604 }; 5605 5606 struct mlx5_ifc_manage_pages_out_bits { 5607 u8 status[0x8]; 5608 u8 reserved_at_8[0x18]; 5609 5610 u8 syndrome[0x20]; 5611 5612 u8 output_num_entries[0x20]; 5613 5614 u8 reserved_at_60[0x20]; 5615 5616 u8 pas[0][0x40]; 5617 }; 5618 5619 enum { 5620 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL = 0x0, 5621 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS = 0x1, 5622 MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES = 0x2, 5623 }; 5624 5625 struct mlx5_ifc_manage_pages_in_bits { 5626 u8 opcode[0x10]; 5627 u8 reserved_at_10[0x10]; 5628 5629 u8 reserved_at_20[0x10]; 5630 u8 op_mod[0x10]; 5631 5632 u8 reserved_at_40[0x10]; 5633 u8 function_id[0x10]; 5634 5635 u8 input_num_entries[0x20]; 5636 5637 u8 pas[0][0x40]; 5638 }; 5639 5640 struct mlx5_ifc_mad_ifc_out_bits { 5641 u8 status[0x8]; 5642 u8 reserved_at_8[0x18]; 5643 5644 u8 syndrome[0x20]; 5645 5646 u8 reserved_at_40[0x40]; 5647 5648 u8 response_mad_packet[256][0x8]; 5649 }; 5650 5651 struct mlx5_ifc_mad_ifc_in_bits { 5652 u8 opcode[0x10]; 5653 u8 reserved_at_10[0x10]; 5654 5655 u8 reserved_at_20[0x10]; 5656 u8 op_mod[0x10]; 5657 5658 u8 remote_lid[0x10]; 5659 u8 reserved_at_50[0x8]; 5660 u8 port[0x8]; 5661 5662 u8 reserved_at_60[0x20]; 5663 5664 u8 mad[256][0x8]; 5665 }; 5666 5667 struct mlx5_ifc_init_hca_out_bits { 5668 u8 status[0x8]; 5669 u8 reserved_at_8[0x18]; 5670 5671 u8 syndrome[0x20]; 5672 5673 u8 reserved_at_40[0x40]; 5674 }; 5675 5676 struct mlx5_ifc_init_hca_in_bits { 5677 u8 opcode[0x10]; 5678 u8 reserved_at_10[0x10]; 5679 5680 u8 reserved_at_20[0x10]; 5681 u8 op_mod[0x10]; 5682 5683 u8 reserved_at_40[0x40]; 5684 u8 sw_owner_id[4][0x20]; 5685 }; 5686 5687 struct mlx5_ifc_init2rtr_qp_out_bits { 5688 u8 status[0x8]; 5689 u8 reserved_at_8[0x18]; 5690 5691 u8 syndrome[0x20]; 5692 5693 u8 reserved_at_40[0x40]; 5694 }; 5695 5696 struct mlx5_ifc_init2rtr_qp_in_bits { 5697 u8 opcode[0x10]; 5698 u8 reserved_at_10[0x10]; 5699 5700 u8 reserved_at_20[0x10]; 5701 u8 op_mod[0x10]; 5702 5703 u8 reserved_at_40[0x8]; 5704 u8 qpn[0x18]; 5705 5706 u8 reserved_at_60[0x20]; 5707 5708 u8 opt_param_mask[0x20]; 5709 5710 u8 reserved_at_a0[0x20]; 5711 5712 struct mlx5_ifc_qpc_bits qpc; 5713 5714 u8 reserved_at_800[0x80]; 5715 }; 5716 5717 struct mlx5_ifc_init2init_qp_out_bits { 5718 u8 status[0x8]; 5719 u8 reserved_at_8[0x18]; 5720 5721 u8 syndrome[0x20]; 5722 5723 u8 reserved_at_40[0x40]; 5724 }; 5725 5726 struct mlx5_ifc_init2init_qp_in_bits { 5727 u8 opcode[0x10]; 5728 u8 reserved_at_10[0x10]; 5729 5730 u8 reserved_at_20[0x10]; 5731 u8 op_mod[0x10]; 5732 5733 u8 reserved_at_40[0x8]; 5734 u8 qpn[0x18]; 5735 5736 u8 reserved_at_60[0x20]; 5737 5738 u8 opt_param_mask[0x20]; 5739 5740 u8 reserved_at_a0[0x20]; 5741 5742 struct mlx5_ifc_qpc_bits qpc; 5743 5744 u8 reserved_at_800[0x80]; 5745 }; 5746 5747 struct mlx5_ifc_get_dropped_packet_log_out_bits { 5748 u8 status[0x8]; 5749 u8 reserved_at_8[0x18]; 5750 5751 u8 syndrome[0x20]; 5752 5753 u8 reserved_at_40[0x40]; 5754 5755 u8 packet_headers_log[128][0x8]; 5756 5757 u8 packet_syndrome[64][0x8]; 5758 }; 5759 5760 struct mlx5_ifc_get_dropped_packet_log_in_bits { 5761 u8 opcode[0x10]; 5762 u8 reserved_at_10[0x10]; 5763 5764 u8 reserved_at_20[0x10]; 5765 u8 op_mod[0x10]; 5766 5767 u8 reserved_at_40[0x40]; 5768 }; 5769 5770 struct mlx5_ifc_gen_eqe_in_bits { 5771 u8 opcode[0x10]; 5772 u8 reserved_at_10[0x10]; 5773 5774 u8 reserved_at_20[0x10]; 5775 u8 op_mod[0x10]; 5776 5777 u8 reserved_at_40[0x18]; 5778 u8 eq_number[0x8]; 5779 5780 u8 reserved_at_60[0x20]; 5781 5782 u8 eqe[64][0x8]; 5783 }; 5784 5785 struct mlx5_ifc_gen_eq_out_bits { 5786 u8 status[0x8]; 5787 u8 reserved_at_8[0x18]; 5788 5789 u8 syndrome[0x20]; 5790 5791 u8 reserved_at_40[0x40]; 5792 }; 5793 5794 struct mlx5_ifc_enable_hca_out_bits { 5795 u8 status[0x8]; 5796 u8 reserved_at_8[0x18]; 5797 5798 u8 syndrome[0x20]; 5799 5800 u8 reserved_at_40[0x20]; 5801 }; 5802 5803 struct mlx5_ifc_enable_hca_in_bits { 5804 u8 opcode[0x10]; 5805 u8 reserved_at_10[0x10]; 5806 5807 u8 reserved_at_20[0x10]; 5808 u8 op_mod[0x10]; 5809 5810 u8 reserved_at_40[0x10]; 5811 u8 function_id[0x10]; 5812 5813 u8 reserved_at_60[0x20]; 5814 }; 5815 5816 struct mlx5_ifc_drain_dct_out_bits { 5817 u8 status[0x8]; 5818 u8 reserved_at_8[0x18]; 5819 5820 u8 syndrome[0x20]; 5821 5822 u8 reserved_at_40[0x40]; 5823 }; 5824 5825 struct mlx5_ifc_drain_dct_in_bits { 5826 u8 opcode[0x10]; 5827 u8 reserved_at_10[0x10]; 5828 5829 u8 reserved_at_20[0x10]; 5830 u8 op_mod[0x10]; 5831 5832 u8 reserved_at_40[0x8]; 5833 u8 dctn[0x18]; 5834 5835 u8 reserved_at_60[0x20]; 5836 }; 5837 5838 struct mlx5_ifc_disable_hca_out_bits { 5839 u8 status[0x8]; 5840 u8 reserved_at_8[0x18]; 5841 5842 u8 syndrome[0x20]; 5843 5844 u8 reserved_at_40[0x20]; 5845 }; 5846 5847 struct mlx5_ifc_disable_hca_in_bits { 5848 u8 opcode[0x10]; 5849 u8 reserved_at_10[0x10]; 5850 5851 u8 reserved_at_20[0x10]; 5852 u8 op_mod[0x10]; 5853 5854 u8 reserved_at_40[0x10]; 5855 u8 function_id[0x10]; 5856 5857 u8 reserved_at_60[0x20]; 5858 }; 5859 5860 struct mlx5_ifc_detach_from_mcg_out_bits { 5861 u8 status[0x8]; 5862 u8 reserved_at_8[0x18]; 5863 5864 u8 syndrome[0x20]; 5865 5866 u8 reserved_at_40[0x40]; 5867 }; 5868 5869 struct mlx5_ifc_detach_from_mcg_in_bits { 5870 u8 opcode[0x10]; 5871 u8 reserved_at_10[0x10]; 5872 5873 u8 reserved_at_20[0x10]; 5874 u8 op_mod[0x10]; 5875 5876 u8 reserved_at_40[0x8]; 5877 u8 qpn[0x18]; 5878 5879 u8 reserved_at_60[0x20]; 5880 5881 u8 multicast_gid[16][0x8]; 5882 }; 5883 5884 struct mlx5_ifc_destroy_xrq_out_bits { 5885 u8 status[0x8]; 5886 u8 reserved_at_8[0x18]; 5887 5888 u8 syndrome[0x20]; 5889 5890 u8 reserved_at_40[0x40]; 5891 }; 5892 5893 struct mlx5_ifc_destroy_xrq_in_bits { 5894 u8 opcode[0x10]; 5895 u8 reserved_at_10[0x10]; 5896 5897 u8 reserved_at_20[0x10]; 5898 u8 op_mod[0x10]; 5899 5900 u8 reserved_at_40[0x8]; 5901 u8 xrqn[0x18]; 5902 5903 u8 reserved_at_60[0x20]; 5904 }; 5905 5906 struct mlx5_ifc_destroy_xrc_srq_out_bits { 5907 u8 status[0x8]; 5908 u8 reserved_at_8[0x18]; 5909 5910 u8 syndrome[0x20]; 5911 5912 u8 reserved_at_40[0x40]; 5913 }; 5914 5915 struct mlx5_ifc_destroy_xrc_srq_in_bits { 5916 u8 opcode[0x10]; 5917 u8 reserved_at_10[0x10]; 5918 5919 u8 reserved_at_20[0x10]; 5920 u8 op_mod[0x10]; 5921 5922 u8 reserved_at_40[0x8]; 5923 u8 xrc_srqn[0x18]; 5924 5925 u8 reserved_at_60[0x20]; 5926 }; 5927 5928 struct mlx5_ifc_destroy_tis_out_bits { 5929 u8 status[0x8]; 5930 u8 reserved_at_8[0x18]; 5931 5932 u8 syndrome[0x20]; 5933 5934 u8 reserved_at_40[0x40]; 5935 }; 5936 5937 struct mlx5_ifc_destroy_tis_in_bits { 5938 u8 opcode[0x10]; 5939 u8 reserved_at_10[0x10]; 5940 5941 u8 reserved_at_20[0x10]; 5942 u8 op_mod[0x10]; 5943 5944 u8 reserved_at_40[0x8]; 5945 u8 tisn[0x18]; 5946 5947 u8 reserved_at_60[0x20]; 5948 }; 5949 5950 struct mlx5_ifc_destroy_tir_out_bits { 5951 u8 status[0x8]; 5952 u8 reserved_at_8[0x18]; 5953 5954 u8 syndrome[0x20]; 5955 5956 u8 reserved_at_40[0x40]; 5957 }; 5958 5959 struct mlx5_ifc_destroy_tir_in_bits { 5960 u8 opcode[0x10]; 5961 u8 reserved_at_10[0x10]; 5962 5963 u8 reserved_at_20[0x10]; 5964 u8 op_mod[0x10]; 5965 5966 u8 reserved_at_40[0x8]; 5967 u8 tirn[0x18]; 5968 5969 u8 reserved_at_60[0x20]; 5970 }; 5971 5972 struct mlx5_ifc_destroy_srq_out_bits { 5973 u8 status[0x8]; 5974 u8 reserved_at_8[0x18]; 5975 5976 u8 syndrome[0x20]; 5977 5978 u8 reserved_at_40[0x40]; 5979 }; 5980 5981 struct mlx5_ifc_destroy_srq_in_bits { 5982 u8 opcode[0x10]; 5983 u8 reserved_at_10[0x10]; 5984 5985 u8 reserved_at_20[0x10]; 5986 u8 op_mod[0x10]; 5987 5988 u8 reserved_at_40[0x8]; 5989 u8 srqn[0x18]; 5990 5991 u8 reserved_at_60[0x20]; 5992 }; 5993 5994 struct mlx5_ifc_destroy_sq_out_bits { 5995 u8 status[0x8]; 5996 u8 reserved_at_8[0x18]; 5997 5998 u8 syndrome[0x20]; 5999 6000 u8 reserved_at_40[0x40]; 6001 }; 6002 6003 struct mlx5_ifc_destroy_sq_in_bits { 6004 u8 opcode[0x10]; 6005 u8 reserved_at_10[0x10]; 6006 6007 u8 reserved_at_20[0x10]; 6008 u8 op_mod[0x10]; 6009 6010 u8 reserved_at_40[0x8]; 6011 u8 sqn[0x18]; 6012 6013 u8 reserved_at_60[0x20]; 6014 }; 6015 6016 struct mlx5_ifc_destroy_scheduling_element_out_bits { 6017 u8 status[0x8]; 6018 u8 reserved_at_8[0x18]; 6019 6020 u8 syndrome[0x20]; 6021 6022 u8 reserved_at_40[0x1c0]; 6023 }; 6024 6025 struct mlx5_ifc_destroy_scheduling_element_in_bits { 6026 u8 opcode[0x10]; 6027 u8 reserved_at_10[0x10]; 6028 6029 u8 reserved_at_20[0x10]; 6030 u8 op_mod[0x10]; 6031 6032 u8 scheduling_hierarchy[0x8]; 6033 u8 reserved_at_48[0x18]; 6034 6035 u8 scheduling_element_id[0x20]; 6036 6037 u8 reserved_at_80[0x180]; 6038 }; 6039 6040 struct mlx5_ifc_destroy_rqt_out_bits { 6041 u8 status[0x8]; 6042 u8 reserved_at_8[0x18]; 6043 6044 u8 syndrome[0x20]; 6045 6046 u8 reserved_at_40[0x40]; 6047 }; 6048 6049 struct mlx5_ifc_destroy_rqt_in_bits { 6050 u8 opcode[0x10]; 6051 u8 reserved_at_10[0x10]; 6052 6053 u8 reserved_at_20[0x10]; 6054 u8 op_mod[0x10]; 6055 6056 u8 reserved_at_40[0x8]; 6057 u8 rqtn[0x18]; 6058 6059 u8 reserved_at_60[0x20]; 6060 }; 6061 6062 struct mlx5_ifc_destroy_rq_out_bits { 6063 u8 status[0x8]; 6064 u8 reserved_at_8[0x18]; 6065 6066 u8 syndrome[0x20]; 6067 6068 u8 reserved_at_40[0x40]; 6069 }; 6070 6071 struct mlx5_ifc_destroy_rq_in_bits { 6072 u8 opcode[0x10]; 6073 u8 reserved_at_10[0x10]; 6074 6075 u8 reserved_at_20[0x10]; 6076 u8 op_mod[0x10]; 6077 6078 u8 reserved_at_40[0x8]; 6079 u8 rqn[0x18]; 6080 6081 u8 reserved_at_60[0x20]; 6082 }; 6083 6084 struct mlx5_ifc_set_delay_drop_params_in_bits { 6085 u8 opcode[0x10]; 6086 u8 reserved_at_10[0x10]; 6087 6088 u8 reserved_at_20[0x10]; 6089 u8 op_mod[0x10]; 6090 6091 u8 reserved_at_40[0x20]; 6092 6093 u8 reserved_at_60[0x10]; 6094 u8 delay_drop_timeout[0x10]; 6095 }; 6096 6097 struct mlx5_ifc_set_delay_drop_params_out_bits { 6098 u8 status[0x8]; 6099 u8 reserved_at_8[0x18]; 6100 6101 u8 syndrome[0x20]; 6102 6103 u8 reserved_at_40[0x40]; 6104 }; 6105 6106 struct mlx5_ifc_destroy_rmp_out_bits { 6107 u8 status[0x8]; 6108 u8 reserved_at_8[0x18]; 6109 6110 u8 syndrome[0x20]; 6111 6112 u8 reserved_at_40[0x40]; 6113 }; 6114 6115 struct mlx5_ifc_destroy_rmp_in_bits { 6116 u8 opcode[0x10]; 6117 u8 reserved_at_10[0x10]; 6118 6119 u8 reserved_at_20[0x10]; 6120 u8 op_mod[0x10]; 6121 6122 u8 reserved_at_40[0x8]; 6123 u8 rmpn[0x18]; 6124 6125 u8 reserved_at_60[0x20]; 6126 }; 6127 6128 struct mlx5_ifc_destroy_qp_out_bits { 6129 u8 status[0x8]; 6130 u8 reserved_at_8[0x18]; 6131 6132 u8 syndrome[0x20]; 6133 6134 u8 reserved_at_40[0x40]; 6135 }; 6136 6137 struct mlx5_ifc_destroy_qp_in_bits { 6138 u8 opcode[0x10]; 6139 u8 reserved_at_10[0x10]; 6140 6141 u8 reserved_at_20[0x10]; 6142 u8 op_mod[0x10]; 6143 6144 u8 reserved_at_40[0x8]; 6145 u8 qpn[0x18]; 6146 6147 u8 reserved_at_60[0x20]; 6148 }; 6149 6150 struct mlx5_ifc_destroy_psv_out_bits { 6151 u8 status[0x8]; 6152 u8 reserved_at_8[0x18]; 6153 6154 u8 syndrome[0x20]; 6155 6156 u8 reserved_at_40[0x40]; 6157 }; 6158 6159 struct mlx5_ifc_destroy_psv_in_bits { 6160 u8 opcode[0x10]; 6161 u8 reserved_at_10[0x10]; 6162 6163 u8 reserved_at_20[0x10]; 6164 u8 op_mod[0x10]; 6165 6166 u8 reserved_at_40[0x8]; 6167 u8 psvn[0x18]; 6168 6169 u8 reserved_at_60[0x20]; 6170 }; 6171 6172 struct mlx5_ifc_destroy_mkey_out_bits { 6173 u8 status[0x8]; 6174 u8 reserved_at_8[0x18]; 6175 6176 u8 syndrome[0x20]; 6177 6178 u8 reserved_at_40[0x40]; 6179 }; 6180 6181 struct mlx5_ifc_destroy_mkey_in_bits { 6182 u8 opcode[0x10]; 6183 u8 reserved_at_10[0x10]; 6184 6185 u8 reserved_at_20[0x10]; 6186 u8 op_mod[0x10]; 6187 6188 u8 reserved_at_40[0x8]; 6189 u8 mkey_index[0x18]; 6190 6191 u8 reserved_at_60[0x20]; 6192 }; 6193 6194 struct mlx5_ifc_destroy_flow_table_out_bits { 6195 u8 status[0x8]; 6196 u8 reserved_at_8[0x18]; 6197 6198 u8 syndrome[0x20]; 6199 6200 u8 reserved_at_40[0x40]; 6201 }; 6202 6203 struct mlx5_ifc_destroy_flow_table_in_bits { 6204 u8 opcode[0x10]; 6205 u8 reserved_at_10[0x10]; 6206 6207 u8 reserved_at_20[0x10]; 6208 u8 op_mod[0x10]; 6209 6210 u8 other_vport[0x1]; 6211 u8 reserved_at_41[0xf]; 6212 u8 vport_number[0x10]; 6213 6214 u8 reserved_at_60[0x20]; 6215 6216 u8 table_type[0x8]; 6217 u8 reserved_at_88[0x18]; 6218 6219 u8 reserved_at_a0[0x8]; 6220 u8 table_id[0x18]; 6221 6222 u8 reserved_at_c0[0x140]; 6223 }; 6224 6225 struct mlx5_ifc_destroy_flow_group_out_bits { 6226 u8 status[0x8]; 6227 u8 reserved_at_8[0x18]; 6228 6229 u8 syndrome[0x20]; 6230 6231 u8 reserved_at_40[0x40]; 6232 }; 6233 6234 struct mlx5_ifc_destroy_flow_group_in_bits { 6235 u8 opcode[0x10]; 6236 u8 reserved_at_10[0x10]; 6237 6238 u8 reserved_at_20[0x10]; 6239 u8 op_mod[0x10]; 6240 6241 u8 other_vport[0x1]; 6242 u8 reserved_at_41[0xf]; 6243 u8 vport_number[0x10]; 6244 6245 u8 reserved_at_60[0x20]; 6246 6247 u8 table_type[0x8]; 6248 u8 reserved_at_88[0x18]; 6249 6250 u8 reserved_at_a0[0x8]; 6251 u8 table_id[0x18]; 6252 6253 u8 group_id[0x20]; 6254 6255 u8 reserved_at_e0[0x120]; 6256 }; 6257 6258 struct mlx5_ifc_destroy_eq_out_bits { 6259 u8 status[0x8]; 6260 u8 reserved_at_8[0x18]; 6261 6262 u8 syndrome[0x20]; 6263 6264 u8 reserved_at_40[0x40]; 6265 }; 6266 6267 struct mlx5_ifc_destroy_eq_in_bits { 6268 u8 opcode[0x10]; 6269 u8 reserved_at_10[0x10]; 6270 6271 u8 reserved_at_20[0x10]; 6272 u8 op_mod[0x10]; 6273 6274 u8 reserved_at_40[0x18]; 6275 u8 eq_number[0x8]; 6276 6277 u8 reserved_at_60[0x20]; 6278 }; 6279 6280 struct mlx5_ifc_destroy_dct_out_bits { 6281 u8 status[0x8]; 6282 u8 reserved_at_8[0x18]; 6283 6284 u8 syndrome[0x20]; 6285 6286 u8 reserved_at_40[0x40]; 6287 }; 6288 6289 struct mlx5_ifc_destroy_dct_in_bits { 6290 u8 opcode[0x10]; 6291 u8 reserved_at_10[0x10]; 6292 6293 u8 reserved_at_20[0x10]; 6294 u8 op_mod[0x10]; 6295 6296 u8 reserved_at_40[0x8]; 6297 u8 dctn[0x18]; 6298 6299 u8 reserved_at_60[0x20]; 6300 }; 6301 6302 struct mlx5_ifc_destroy_cq_out_bits { 6303 u8 status[0x8]; 6304 u8 reserved_at_8[0x18]; 6305 6306 u8 syndrome[0x20]; 6307 6308 u8 reserved_at_40[0x40]; 6309 }; 6310 6311 struct mlx5_ifc_destroy_cq_in_bits { 6312 u8 opcode[0x10]; 6313 u8 reserved_at_10[0x10]; 6314 6315 u8 reserved_at_20[0x10]; 6316 u8 op_mod[0x10]; 6317 6318 u8 reserved_at_40[0x8]; 6319 u8 cqn[0x18]; 6320 6321 u8 reserved_at_60[0x20]; 6322 }; 6323 6324 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits { 6325 u8 status[0x8]; 6326 u8 reserved_at_8[0x18]; 6327 6328 u8 syndrome[0x20]; 6329 6330 u8 reserved_at_40[0x40]; 6331 }; 6332 6333 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits { 6334 u8 opcode[0x10]; 6335 u8 reserved_at_10[0x10]; 6336 6337 u8 reserved_at_20[0x10]; 6338 u8 op_mod[0x10]; 6339 6340 u8 reserved_at_40[0x20]; 6341 6342 u8 reserved_at_60[0x10]; 6343 u8 vxlan_udp_port[0x10]; 6344 }; 6345 6346 struct mlx5_ifc_delete_l2_table_entry_out_bits { 6347 u8 status[0x8]; 6348 u8 reserved_at_8[0x18]; 6349 6350 u8 syndrome[0x20]; 6351 6352 u8 reserved_at_40[0x40]; 6353 }; 6354 6355 struct mlx5_ifc_delete_l2_table_entry_in_bits { 6356 u8 opcode[0x10]; 6357 u8 reserved_at_10[0x10]; 6358 6359 u8 reserved_at_20[0x10]; 6360 u8 op_mod[0x10]; 6361 6362 u8 reserved_at_40[0x60]; 6363 6364 u8 reserved_at_a0[0x8]; 6365 u8 table_index[0x18]; 6366 6367 u8 reserved_at_c0[0x140]; 6368 }; 6369 6370 struct mlx5_ifc_delete_fte_out_bits { 6371 u8 status[0x8]; 6372 u8 reserved_at_8[0x18]; 6373 6374 u8 syndrome[0x20]; 6375 6376 u8 reserved_at_40[0x40]; 6377 }; 6378 6379 struct mlx5_ifc_delete_fte_in_bits { 6380 u8 opcode[0x10]; 6381 u8 reserved_at_10[0x10]; 6382 6383 u8 reserved_at_20[0x10]; 6384 u8 op_mod[0x10]; 6385 6386 u8 other_vport[0x1]; 6387 u8 reserved_at_41[0xf]; 6388 u8 vport_number[0x10]; 6389 6390 u8 reserved_at_60[0x20]; 6391 6392 u8 table_type[0x8]; 6393 u8 reserved_at_88[0x18]; 6394 6395 u8 reserved_at_a0[0x8]; 6396 u8 table_id[0x18]; 6397 6398 u8 reserved_at_c0[0x40]; 6399 6400 u8 flow_index[0x20]; 6401 6402 u8 reserved_at_120[0xe0]; 6403 }; 6404 6405 struct mlx5_ifc_dealloc_xrcd_out_bits { 6406 u8 status[0x8]; 6407 u8 reserved_at_8[0x18]; 6408 6409 u8 syndrome[0x20]; 6410 6411 u8 reserved_at_40[0x40]; 6412 }; 6413 6414 struct mlx5_ifc_dealloc_xrcd_in_bits { 6415 u8 opcode[0x10]; 6416 u8 reserved_at_10[0x10]; 6417 6418 u8 reserved_at_20[0x10]; 6419 u8 op_mod[0x10]; 6420 6421 u8 reserved_at_40[0x8]; 6422 u8 xrcd[0x18]; 6423 6424 u8 reserved_at_60[0x20]; 6425 }; 6426 6427 struct mlx5_ifc_dealloc_uar_out_bits { 6428 u8 status[0x8]; 6429 u8 reserved_at_8[0x18]; 6430 6431 u8 syndrome[0x20]; 6432 6433 u8 reserved_at_40[0x40]; 6434 }; 6435 6436 struct mlx5_ifc_dealloc_uar_in_bits { 6437 u8 opcode[0x10]; 6438 u8 reserved_at_10[0x10]; 6439 6440 u8 reserved_at_20[0x10]; 6441 u8 op_mod[0x10]; 6442 6443 u8 reserved_at_40[0x8]; 6444 u8 uar[0x18]; 6445 6446 u8 reserved_at_60[0x20]; 6447 }; 6448 6449 struct mlx5_ifc_dealloc_transport_domain_out_bits { 6450 u8 status[0x8]; 6451 u8 reserved_at_8[0x18]; 6452 6453 u8 syndrome[0x20]; 6454 6455 u8 reserved_at_40[0x40]; 6456 }; 6457 6458 struct mlx5_ifc_dealloc_transport_domain_in_bits { 6459 u8 opcode[0x10]; 6460 u8 reserved_at_10[0x10]; 6461 6462 u8 reserved_at_20[0x10]; 6463 u8 op_mod[0x10]; 6464 6465 u8 reserved_at_40[0x8]; 6466 u8 transport_domain[0x18]; 6467 6468 u8 reserved_at_60[0x20]; 6469 }; 6470 6471 struct mlx5_ifc_dealloc_q_counter_out_bits { 6472 u8 status[0x8]; 6473 u8 reserved_at_8[0x18]; 6474 6475 u8 syndrome[0x20]; 6476 6477 u8 reserved_at_40[0x40]; 6478 }; 6479 6480 struct mlx5_ifc_dealloc_q_counter_in_bits { 6481 u8 opcode[0x10]; 6482 u8 reserved_at_10[0x10]; 6483 6484 u8 reserved_at_20[0x10]; 6485 u8 op_mod[0x10]; 6486 6487 u8 reserved_at_40[0x18]; 6488 u8 counter_set_id[0x8]; 6489 6490 u8 reserved_at_60[0x20]; 6491 }; 6492 6493 struct mlx5_ifc_dealloc_pd_out_bits { 6494 u8 status[0x8]; 6495 u8 reserved_at_8[0x18]; 6496 6497 u8 syndrome[0x20]; 6498 6499 u8 reserved_at_40[0x40]; 6500 }; 6501 6502 struct mlx5_ifc_dealloc_pd_in_bits { 6503 u8 opcode[0x10]; 6504 u8 reserved_at_10[0x10]; 6505 6506 u8 reserved_at_20[0x10]; 6507 u8 op_mod[0x10]; 6508 6509 u8 reserved_at_40[0x8]; 6510 u8 pd[0x18]; 6511 6512 u8 reserved_at_60[0x20]; 6513 }; 6514 6515 struct mlx5_ifc_dealloc_flow_counter_out_bits { 6516 u8 status[0x8]; 6517 u8 reserved_at_8[0x18]; 6518 6519 u8 syndrome[0x20]; 6520 6521 u8 reserved_at_40[0x40]; 6522 }; 6523 6524 struct mlx5_ifc_dealloc_flow_counter_in_bits { 6525 u8 opcode[0x10]; 6526 u8 reserved_at_10[0x10]; 6527 6528 u8 reserved_at_20[0x10]; 6529 u8 op_mod[0x10]; 6530 6531 u8 flow_counter_id[0x20]; 6532 6533 u8 reserved_at_60[0x20]; 6534 }; 6535 6536 struct mlx5_ifc_create_xrq_out_bits { 6537 u8 status[0x8]; 6538 u8 reserved_at_8[0x18]; 6539 6540 u8 syndrome[0x20]; 6541 6542 u8 reserved_at_40[0x8]; 6543 u8 xrqn[0x18]; 6544 6545 u8 reserved_at_60[0x20]; 6546 }; 6547 6548 struct mlx5_ifc_create_xrq_in_bits { 6549 u8 opcode[0x10]; 6550 u8 reserved_at_10[0x10]; 6551 6552 u8 reserved_at_20[0x10]; 6553 u8 op_mod[0x10]; 6554 6555 u8 reserved_at_40[0x40]; 6556 6557 struct mlx5_ifc_xrqc_bits xrq_context; 6558 }; 6559 6560 struct mlx5_ifc_create_xrc_srq_out_bits { 6561 u8 status[0x8]; 6562 u8 reserved_at_8[0x18]; 6563 6564 u8 syndrome[0x20]; 6565 6566 u8 reserved_at_40[0x8]; 6567 u8 xrc_srqn[0x18]; 6568 6569 u8 reserved_at_60[0x20]; 6570 }; 6571 6572 struct mlx5_ifc_create_xrc_srq_in_bits { 6573 u8 opcode[0x10]; 6574 u8 reserved_at_10[0x10]; 6575 6576 u8 reserved_at_20[0x10]; 6577 u8 op_mod[0x10]; 6578 6579 u8 reserved_at_40[0x40]; 6580 6581 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 6582 6583 u8 reserved_at_280[0x600]; 6584 6585 u8 pas[0][0x40]; 6586 }; 6587 6588 struct mlx5_ifc_create_tis_out_bits { 6589 u8 status[0x8]; 6590 u8 reserved_at_8[0x18]; 6591 6592 u8 syndrome[0x20]; 6593 6594 u8 reserved_at_40[0x8]; 6595 u8 tisn[0x18]; 6596 6597 u8 reserved_at_60[0x20]; 6598 }; 6599 6600 struct mlx5_ifc_create_tis_in_bits { 6601 u8 opcode[0x10]; 6602 u8 reserved_at_10[0x10]; 6603 6604 u8 reserved_at_20[0x10]; 6605 u8 op_mod[0x10]; 6606 6607 u8 reserved_at_40[0xc0]; 6608 6609 struct mlx5_ifc_tisc_bits ctx; 6610 }; 6611 6612 struct mlx5_ifc_create_tir_out_bits { 6613 u8 status[0x8]; 6614 u8 reserved_at_8[0x18]; 6615 6616 u8 syndrome[0x20]; 6617 6618 u8 reserved_at_40[0x8]; 6619 u8 tirn[0x18]; 6620 6621 u8 reserved_at_60[0x20]; 6622 }; 6623 6624 struct mlx5_ifc_create_tir_in_bits { 6625 u8 opcode[0x10]; 6626 u8 reserved_at_10[0x10]; 6627 6628 u8 reserved_at_20[0x10]; 6629 u8 op_mod[0x10]; 6630 6631 u8 reserved_at_40[0xc0]; 6632 6633 struct mlx5_ifc_tirc_bits ctx; 6634 }; 6635 6636 struct mlx5_ifc_create_srq_out_bits { 6637 u8 status[0x8]; 6638 u8 reserved_at_8[0x18]; 6639 6640 u8 syndrome[0x20]; 6641 6642 u8 reserved_at_40[0x8]; 6643 u8 srqn[0x18]; 6644 6645 u8 reserved_at_60[0x20]; 6646 }; 6647 6648 struct mlx5_ifc_create_srq_in_bits { 6649 u8 opcode[0x10]; 6650 u8 reserved_at_10[0x10]; 6651 6652 u8 reserved_at_20[0x10]; 6653 u8 op_mod[0x10]; 6654 6655 u8 reserved_at_40[0x40]; 6656 6657 struct mlx5_ifc_srqc_bits srq_context_entry; 6658 6659 u8 reserved_at_280[0x600]; 6660 6661 u8 pas[0][0x40]; 6662 }; 6663 6664 struct mlx5_ifc_create_sq_out_bits { 6665 u8 status[0x8]; 6666 u8 reserved_at_8[0x18]; 6667 6668 u8 syndrome[0x20]; 6669 6670 u8 reserved_at_40[0x8]; 6671 u8 sqn[0x18]; 6672 6673 u8 reserved_at_60[0x20]; 6674 }; 6675 6676 struct mlx5_ifc_create_sq_in_bits { 6677 u8 opcode[0x10]; 6678 u8 reserved_at_10[0x10]; 6679 6680 u8 reserved_at_20[0x10]; 6681 u8 op_mod[0x10]; 6682 6683 u8 reserved_at_40[0xc0]; 6684 6685 struct mlx5_ifc_sqc_bits ctx; 6686 }; 6687 6688 struct mlx5_ifc_create_scheduling_element_out_bits { 6689 u8 status[0x8]; 6690 u8 reserved_at_8[0x18]; 6691 6692 u8 syndrome[0x20]; 6693 6694 u8 reserved_at_40[0x40]; 6695 6696 u8 scheduling_element_id[0x20]; 6697 6698 u8 reserved_at_a0[0x160]; 6699 }; 6700 6701 struct mlx5_ifc_create_scheduling_element_in_bits { 6702 u8 opcode[0x10]; 6703 u8 reserved_at_10[0x10]; 6704 6705 u8 reserved_at_20[0x10]; 6706 u8 op_mod[0x10]; 6707 6708 u8 scheduling_hierarchy[0x8]; 6709 u8 reserved_at_48[0x18]; 6710 6711 u8 reserved_at_60[0xa0]; 6712 6713 struct mlx5_ifc_scheduling_context_bits scheduling_context; 6714 6715 u8 reserved_at_300[0x100]; 6716 }; 6717 6718 struct mlx5_ifc_create_rqt_out_bits { 6719 u8 status[0x8]; 6720 u8 reserved_at_8[0x18]; 6721 6722 u8 syndrome[0x20]; 6723 6724 u8 reserved_at_40[0x8]; 6725 u8 rqtn[0x18]; 6726 6727 u8 reserved_at_60[0x20]; 6728 }; 6729 6730 struct mlx5_ifc_create_rqt_in_bits { 6731 u8 opcode[0x10]; 6732 u8 reserved_at_10[0x10]; 6733 6734 u8 reserved_at_20[0x10]; 6735 u8 op_mod[0x10]; 6736 6737 u8 reserved_at_40[0xc0]; 6738 6739 struct mlx5_ifc_rqtc_bits rqt_context; 6740 }; 6741 6742 struct mlx5_ifc_create_rq_out_bits { 6743 u8 status[0x8]; 6744 u8 reserved_at_8[0x18]; 6745 6746 u8 syndrome[0x20]; 6747 6748 u8 reserved_at_40[0x8]; 6749 u8 rqn[0x18]; 6750 6751 u8 reserved_at_60[0x20]; 6752 }; 6753 6754 struct mlx5_ifc_create_rq_in_bits { 6755 u8 opcode[0x10]; 6756 u8 reserved_at_10[0x10]; 6757 6758 u8 reserved_at_20[0x10]; 6759 u8 op_mod[0x10]; 6760 6761 u8 reserved_at_40[0xc0]; 6762 6763 struct mlx5_ifc_rqc_bits ctx; 6764 }; 6765 6766 struct mlx5_ifc_create_rmp_out_bits { 6767 u8 status[0x8]; 6768 u8 reserved_at_8[0x18]; 6769 6770 u8 syndrome[0x20]; 6771 6772 u8 reserved_at_40[0x8]; 6773 u8 rmpn[0x18]; 6774 6775 u8 reserved_at_60[0x20]; 6776 }; 6777 6778 struct mlx5_ifc_create_rmp_in_bits { 6779 u8 opcode[0x10]; 6780 u8 reserved_at_10[0x10]; 6781 6782 u8 reserved_at_20[0x10]; 6783 u8 op_mod[0x10]; 6784 6785 u8 reserved_at_40[0xc0]; 6786 6787 struct mlx5_ifc_rmpc_bits ctx; 6788 }; 6789 6790 struct mlx5_ifc_create_qp_out_bits { 6791 u8 status[0x8]; 6792 u8 reserved_at_8[0x18]; 6793 6794 u8 syndrome[0x20]; 6795 6796 u8 reserved_at_40[0x8]; 6797 u8 qpn[0x18]; 6798 6799 u8 reserved_at_60[0x20]; 6800 }; 6801 6802 struct mlx5_ifc_create_qp_in_bits { 6803 u8 opcode[0x10]; 6804 u8 reserved_at_10[0x10]; 6805 6806 u8 reserved_at_20[0x10]; 6807 u8 op_mod[0x10]; 6808 6809 u8 reserved_at_40[0x40]; 6810 6811 u8 opt_param_mask[0x20]; 6812 6813 u8 reserved_at_a0[0x20]; 6814 6815 struct mlx5_ifc_qpc_bits qpc; 6816 6817 u8 reserved_at_800[0x80]; 6818 6819 u8 pas[0][0x40]; 6820 }; 6821 6822 struct mlx5_ifc_create_psv_out_bits { 6823 u8 status[0x8]; 6824 u8 reserved_at_8[0x18]; 6825 6826 u8 syndrome[0x20]; 6827 6828 u8 reserved_at_40[0x40]; 6829 6830 u8 reserved_at_80[0x8]; 6831 u8 psv0_index[0x18]; 6832 6833 u8 reserved_at_a0[0x8]; 6834 u8 psv1_index[0x18]; 6835 6836 u8 reserved_at_c0[0x8]; 6837 u8 psv2_index[0x18]; 6838 6839 u8 reserved_at_e0[0x8]; 6840 u8 psv3_index[0x18]; 6841 }; 6842 6843 struct mlx5_ifc_create_psv_in_bits { 6844 u8 opcode[0x10]; 6845 u8 reserved_at_10[0x10]; 6846 6847 u8 reserved_at_20[0x10]; 6848 u8 op_mod[0x10]; 6849 6850 u8 num_psv[0x4]; 6851 u8 reserved_at_44[0x4]; 6852 u8 pd[0x18]; 6853 6854 u8 reserved_at_60[0x20]; 6855 }; 6856 6857 struct mlx5_ifc_create_mkey_out_bits { 6858 u8 status[0x8]; 6859 u8 reserved_at_8[0x18]; 6860 6861 u8 syndrome[0x20]; 6862 6863 u8 reserved_at_40[0x8]; 6864 u8 mkey_index[0x18]; 6865 6866 u8 reserved_at_60[0x20]; 6867 }; 6868 6869 struct mlx5_ifc_create_mkey_in_bits { 6870 u8 opcode[0x10]; 6871 u8 reserved_at_10[0x10]; 6872 6873 u8 reserved_at_20[0x10]; 6874 u8 op_mod[0x10]; 6875 6876 u8 reserved_at_40[0x20]; 6877 6878 u8 pg_access[0x1]; 6879 u8 reserved_at_61[0x1f]; 6880 6881 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 6882 6883 u8 reserved_at_280[0x80]; 6884 6885 u8 translations_octword_actual_size[0x20]; 6886 6887 u8 reserved_at_320[0x560]; 6888 6889 u8 klm_pas_mtt[0][0x20]; 6890 }; 6891 6892 struct mlx5_ifc_create_flow_table_out_bits { 6893 u8 status[0x8]; 6894 u8 reserved_at_8[0x18]; 6895 6896 u8 syndrome[0x20]; 6897 6898 u8 reserved_at_40[0x8]; 6899 u8 table_id[0x18]; 6900 6901 u8 reserved_at_60[0x20]; 6902 }; 6903 6904 struct mlx5_ifc_flow_table_context_bits { 6905 u8 encap_en[0x1]; 6906 u8 decap_en[0x1]; 6907 u8 reserved_at_2[0x2]; 6908 u8 table_miss_action[0x4]; 6909 u8 level[0x8]; 6910 u8 reserved_at_10[0x8]; 6911 u8 log_size[0x8]; 6912 6913 u8 reserved_at_20[0x8]; 6914 u8 table_miss_id[0x18]; 6915 6916 u8 reserved_at_40[0x8]; 6917 u8 lag_master_next_table_id[0x18]; 6918 6919 u8 reserved_at_60[0xe0]; 6920 }; 6921 6922 struct mlx5_ifc_create_flow_table_in_bits { 6923 u8 opcode[0x10]; 6924 u8 reserved_at_10[0x10]; 6925 6926 u8 reserved_at_20[0x10]; 6927 u8 op_mod[0x10]; 6928 6929 u8 other_vport[0x1]; 6930 u8 reserved_at_41[0xf]; 6931 u8 vport_number[0x10]; 6932 6933 u8 reserved_at_60[0x20]; 6934 6935 u8 table_type[0x8]; 6936 u8 reserved_at_88[0x18]; 6937 6938 u8 reserved_at_a0[0x20]; 6939 6940 struct mlx5_ifc_flow_table_context_bits flow_table_context; 6941 }; 6942 6943 struct mlx5_ifc_create_flow_group_out_bits { 6944 u8 status[0x8]; 6945 u8 reserved_at_8[0x18]; 6946 6947 u8 syndrome[0x20]; 6948 6949 u8 reserved_at_40[0x8]; 6950 u8 group_id[0x18]; 6951 6952 u8 reserved_at_60[0x20]; 6953 }; 6954 6955 enum { 6956 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 6957 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 6958 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 6959 }; 6960 6961 struct mlx5_ifc_create_flow_group_in_bits { 6962 u8 opcode[0x10]; 6963 u8 reserved_at_10[0x10]; 6964 6965 u8 reserved_at_20[0x10]; 6966 u8 op_mod[0x10]; 6967 6968 u8 other_vport[0x1]; 6969 u8 reserved_at_41[0xf]; 6970 u8 vport_number[0x10]; 6971 6972 u8 reserved_at_60[0x20]; 6973 6974 u8 table_type[0x8]; 6975 u8 reserved_at_88[0x18]; 6976 6977 u8 reserved_at_a0[0x8]; 6978 u8 table_id[0x18]; 6979 6980 u8 reserved_at_c0[0x20]; 6981 6982 u8 start_flow_index[0x20]; 6983 6984 u8 reserved_at_100[0x20]; 6985 6986 u8 end_flow_index[0x20]; 6987 6988 u8 reserved_at_140[0xa0]; 6989 6990 u8 reserved_at_1e0[0x18]; 6991 u8 match_criteria_enable[0x8]; 6992 6993 struct mlx5_ifc_fte_match_param_bits match_criteria; 6994 6995 u8 reserved_at_1200[0xe00]; 6996 }; 6997 6998 struct mlx5_ifc_create_eq_out_bits { 6999 u8 status[0x8]; 7000 u8 reserved_at_8[0x18]; 7001 7002 u8 syndrome[0x20]; 7003 7004 u8 reserved_at_40[0x18]; 7005 u8 eq_number[0x8]; 7006 7007 u8 reserved_at_60[0x20]; 7008 }; 7009 7010 struct mlx5_ifc_create_eq_in_bits { 7011 u8 opcode[0x10]; 7012 u8 reserved_at_10[0x10]; 7013 7014 u8 reserved_at_20[0x10]; 7015 u8 op_mod[0x10]; 7016 7017 u8 reserved_at_40[0x40]; 7018 7019 struct mlx5_ifc_eqc_bits eq_context_entry; 7020 7021 u8 reserved_at_280[0x40]; 7022 7023 u8 event_bitmask[0x40]; 7024 7025 u8 reserved_at_300[0x580]; 7026 7027 u8 pas[0][0x40]; 7028 }; 7029 7030 struct mlx5_ifc_create_dct_out_bits { 7031 u8 status[0x8]; 7032 u8 reserved_at_8[0x18]; 7033 7034 u8 syndrome[0x20]; 7035 7036 u8 reserved_at_40[0x8]; 7037 u8 dctn[0x18]; 7038 7039 u8 reserved_at_60[0x20]; 7040 }; 7041 7042 struct mlx5_ifc_create_dct_in_bits { 7043 u8 opcode[0x10]; 7044 u8 reserved_at_10[0x10]; 7045 7046 u8 reserved_at_20[0x10]; 7047 u8 op_mod[0x10]; 7048 7049 u8 reserved_at_40[0x40]; 7050 7051 struct mlx5_ifc_dctc_bits dct_context_entry; 7052 7053 u8 reserved_at_280[0x180]; 7054 }; 7055 7056 struct mlx5_ifc_create_cq_out_bits { 7057 u8 status[0x8]; 7058 u8 reserved_at_8[0x18]; 7059 7060 u8 syndrome[0x20]; 7061 7062 u8 reserved_at_40[0x8]; 7063 u8 cqn[0x18]; 7064 7065 u8 reserved_at_60[0x20]; 7066 }; 7067 7068 struct mlx5_ifc_create_cq_in_bits { 7069 u8 opcode[0x10]; 7070 u8 reserved_at_10[0x10]; 7071 7072 u8 reserved_at_20[0x10]; 7073 u8 op_mod[0x10]; 7074 7075 u8 reserved_at_40[0x40]; 7076 7077 struct mlx5_ifc_cqc_bits cq_context; 7078 7079 u8 reserved_at_280[0x600]; 7080 7081 u8 pas[0][0x40]; 7082 }; 7083 7084 struct mlx5_ifc_config_int_moderation_out_bits { 7085 u8 status[0x8]; 7086 u8 reserved_at_8[0x18]; 7087 7088 u8 syndrome[0x20]; 7089 7090 u8 reserved_at_40[0x4]; 7091 u8 min_delay[0xc]; 7092 u8 int_vector[0x10]; 7093 7094 u8 reserved_at_60[0x20]; 7095 }; 7096 7097 enum { 7098 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0, 7099 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1, 7100 }; 7101 7102 struct mlx5_ifc_config_int_moderation_in_bits { 7103 u8 opcode[0x10]; 7104 u8 reserved_at_10[0x10]; 7105 7106 u8 reserved_at_20[0x10]; 7107 u8 op_mod[0x10]; 7108 7109 u8 reserved_at_40[0x4]; 7110 u8 min_delay[0xc]; 7111 u8 int_vector[0x10]; 7112 7113 u8 reserved_at_60[0x20]; 7114 }; 7115 7116 struct mlx5_ifc_attach_to_mcg_out_bits { 7117 u8 status[0x8]; 7118 u8 reserved_at_8[0x18]; 7119 7120 u8 syndrome[0x20]; 7121 7122 u8 reserved_at_40[0x40]; 7123 }; 7124 7125 struct mlx5_ifc_attach_to_mcg_in_bits { 7126 u8 opcode[0x10]; 7127 u8 reserved_at_10[0x10]; 7128 7129 u8 reserved_at_20[0x10]; 7130 u8 op_mod[0x10]; 7131 7132 u8 reserved_at_40[0x8]; 7133 u8 qpn[0x18]; 7134 7135 u8 reserved_at_60[0x20]; 7136 7137 u8 multicast_gid[16][0x8]; 7138 }; 7139 7140 struct mlx5_ifc_arm_xrq_out_bits { 7141 u8 status[0x8]; 7142 u8 reserved_at_8[0x18]; 7143 7144 u8 syndrome[0x20]; 7145 7146 u8 reserved_at_40[0x40]; 7147 }; 7148 7149 struct mlx5_ifc_arm_xrq_in_bits { 7150 u8 opcode[0x10]; 7151 u8 reserved_at_10[0x10]; 7152 7153 u8 reserved_at_20[0x10]; 7154 u8 op_mod[0x10]; 7155 7156 u8 reserved_at_40[0x8]; 7157 u8 xrqn[0x18]; 7158 7159 u8 reserved_at_60[0x10]; 7160 u8 lwm[0x10]; 7161 }; 7162 7163 struct mlx5_ifc_arm_xrc_srq_out_bits { 7164 u8 status[0x8]; 7165 u8 reserved_at_8[0x18]; 7166 7167 u8 syndrome[0x20]; 7168 7169 u8 reserved_at_40[0x40]; 7170 }; 7171 7172 enum { 7173 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1, 7174 }; 7175 7176 struct mlx5_ifc_arm_xrc_srq_in_bits { 7177 u8 opcode[0x10]; 7178 u8 reserved_at_10[0x10]; 7179 7180 u8 reserved_at_20[0x10]; 7181 u8 op_mod[0x10]; 7182 7183 u8 reserved_at_40[0x8]; 7184 u8 xrc_srqn[0x18]; 7185 7186 u8 reserved_at_60[0x10]; 7187 u8 lwm[0x10]; 7188 }; 7189 7190 struct mlx5_ifc_arm_rq_out_bits { 7191 u8 status[0x8]; 7192 u8 reserved_at_8[0x18]; 7193 7194 u8 syndrome[0x20]; 7195 7196 u8 reserved_at_40[0x40]; 7197 }; 7198 7199 enum { 7200 MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1, 7201 MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2, 7202 }; 7203 7204 struct mlx5_ifc_arm_rq_in_bits { 7205 u8 opcode[0x10]; 7206 u8 reserved_at_10[0x10]; 7207 7208 u8 reserved_at_20[0x10]; 7209 u8 op_mod[0x10]; 7210 7211 u8 reserved_at_40[0x8]; 7212 u8 srq_number[0x18]; 7213 7214 u8 reserved_at_60[0x10]; 7215 u8 lwm[0x10]; 7216 }; 7217 7218 struct mlx5_ifc_arm_dct_out_bits { 7219 u8 status[0x8]; 7220 u8 reserved_at_8[0x18]; 7221 7222 u8 syndrome[0x20]; 7223 7224 u8 reserved_at_40[0x40]; 7225 }; 7226 7227 struct mlx5_ifc_arm_dct_in_bits { 7228 u8 opcode[0x10]; 7229 u8 reserved_at_10[0x10]; 7230 7231 u8 reserved_at_20[0x10]; 7232 u8 op_mod[0x10]; 7233 7234 u8 reserved_at_40[0x8]; 7235 u8 dct_number[0x18]; 7236 7237 u8 reserved_at_60[0x20]; 7238 }; 7239 7240 struct mlx5_ifc_alloc_xrcd_out_bits { 7241 u8 status[0x8]; 7242 u8 reserved_at_8[0x18]; 7243 7244 u8 syndrome[0x20]; 7245 7246 u8 reserved_at_40[0x8]; 7247 u8 xrcd[0x18]; 7248 7249 u8 reserved_at_60[0x20]; 7250 }; 7251 7252 struct mlx5_ifc_alloc_xrcd_in_bits { 7253 u8 opcode[0x10]; 7254 u8 reserved_at_10[0x10]; 7255 7256 u8 reserved_at_20[0x10]; 7257 u8 op_mod[0x10]; 7258 7259 u8 reserved_at_40[0x40]; 7260 }; 7261 7262 struct mlx5_ifc_alloc_uar_out_bits { 7263 u8 status[0x8]; 7264 u8 reserved_at_8[0x18]; 7265 7266 u8 syndrome[0x20]; 7267 7268 u8 reserved_at_40[0x8]; 7269 u8 uar[0x18]; 7270 7271 u8 reserved_at_60[0x20]; 7272 }; 7273 7274 struct mlx5_ifc_alloc_uar_in_bits { 7275 u8 opcode[0x10]; 7276 u8 reserved_at_10[0x10]; 7277 7278 u8 reserved_at_20[0x10]; 7279 u8 op_mod[0x10]; 7280 7281 u8 reserved_at_40[0x40]; 7282 }; 7283 7284 struct mlx5_ifc_alloc_transport_domain_out_bits { 7285 u8 status[0x8]; 7286 u8 reserved_at_8[0x18]; 7287 7288 u8 syndrome[0x20]; 7289 7290 u8 reserved_at_40[0x8]; 7291 u8 transport_domain[0x18]; 7292 7293 u8 reserved_at_60[0x20]; 7294 }; 7295 7296 struct mlx5_ifc_alloc_transport_domain_in_bits { 7297 u8 opcode[0x10]; 7298 u8 reserved_at_10[0x10]; 7299 7300 u8 reserved_at_20[0x10]; 7301 u8 op_mod[0x10]; 7302 7303 u8 reserved_at_40[0x40]; 7304 }; 7305 7306 struct mlx5_ifc_alloc_q_counter_out_bits { 7307 u8 status[0x8]; 7308 u8 reserved_at_8[0x18]; 7309 7310 u8 syndrome[0x20]; 7311 7312 u8 reserved_at_40[0x18]; 7313 u8 counter_set_id[0x8]; 7314 7315 u8 reserved_at_60[0x20]; 7316 }; 7317 7318 struct mlx5_ifc_alloc_q_counter_in_bits { 7319 u8 opcode[0x10]; 7320 u8 reserved_at_10[0x10]; 7321 7322 u8 reserved_at_20[0x10]; 7323 u8 op_mod[0x10]; 7324 7325 u8 reserved_at_40[0x40]; 7326 }; 7327 7328 struct mlx5_ifc_alloc_pd_out_bits { 7329 u8 status[0x8]; 7330 u8 reserved_at_8[0x18]; 7331 7332 u8 syndrome[0x20]; 7333 7334 u8 reserved_at_40[0x8]; 7335 u8 pd[0x18]; 7336 7337 u8 reserved_at_60[0x20]; 7338 }; 7339 7340 struct mlx5_ifc_alloc_pd_in_bits { 7341 u8 opcode[0x10]; 7342 u8 reserved_at_10[0x10]; 7343 7344 u8 reserved_at_20[0x10]; 7345 u8 op_mod[0x10]; 7346 7347 u8 reserved_at_40[0x40]; 7348 }; 7349 7350 struct mlx5_ifc_alloc_flow_counter_out_bits { 7351 u8 status[0x8]; 7352 u8 reserved_at_8[0x18]; 7353 7354 u8 syndrome[0x20]; 7355 7356 u8 flow_counter_id[0x20]; 7357 7358 u8 reserved_at_60[0x20]; 7359 }; 7360 7361 struct mlx5_ifc_alloc_flow_counter_in_bits { 7362 u8 opcode[0x10]; 7363 u8 reserved_at_10[0x10]; 7364 7365 u8 reserved_at_20[0x10]; 7366 u8 op_mod[0x10]; 7367 7368 u8 reserved_at_40[0x40]; 7369 }; 7370 7371 struct mlx5_ifc_add_vxlan_udp_dport_out_bits { 7372 u8 status[0x8]; 7373 u8 reserved_at_8[0x18]; 7374 7375 u8 syndrome[0x20]; 7376 7377 u8 reserved_at_40[0x40]; 7378 }; 7379 7380 struct mlx5_ifc_add_vxlan_udp_dport_in_bits { 7381 u8 opcode[0x10]; 7382 u8 reserved_at_10[0x10]; 7383 7384 u8 reserved_at_20[0x10]; 7385 u8 op_mod[0x10]; 7386 7387 u8 reserved_at_40[0x20]; 7388 7389 u8 reserved_at_60[0x10]; 7390 u8 vxlan_udp_port[0x10]; 7391 }; 7392 7393 struct mlx5_ifc_set_pp_rate_limit_out_bits { 7394 u8 status[0x8]; 7395 u8 reserved_at_8[0x18]; 7396 7397 u8 syndrome[0x20]; 7398 7399 u8 reserved_at_40[0x40]; 7400 }; 7401 7402 struct mlx5_ifc_set_pp_rate_limit_in_bits { 7403 u8 opcode[0x10]; 7404 u8 reserved_at_10[0x10]; 7405 7406 u8 reserved_at_20[0x10]; 7407 u8 op_mod[0x10]; 7408 7409 u8 reserved_at_40[0x10]; 7410 u8 rate_limit_index[0x10]; 7411 7412 u8 reserved_at_60[0x20]; 7413 7414 u8 rate_limit[0x20]; 7415 7416 u8 burst_upper_bound[0x20]; 7417 7418 u8 reserved_at_c0[0x10]; 7419 u8 typical_packet_size[0x10]; 7420 7421 u8 reserved_at_e0[0x120]; 7422 }; 7423 7424 struct mlx5_ifc_access_register_out_bits { 7425 u8 status[0x8]; 7426 u8 reserved_at_8[0x18]; 7427 7428 u8 syndrome[0x20]; 7429 7430 u8 reserved_at_40[0x40]; 7431 7432 u8 register_data[0][0x20]; 7433 }; 7434 7435 enum { 7436 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0, 7437 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1, 7438 }; 7439 7440 struct mlx5_ifc_access_register_in_bits { 7441 u8 opcode[0x10]; 7442 u8 reserved_at_10[0x10]; 7443 7444 u8 reserved_at_20[0x10]; 7445 u8 op_mod[0x10]; 7446 7447 u8 reserved_at_40[0x10]; 7448 u8 register_id[0x10]; 7449 7450 u8 argument[0x20]; 7451 7452 u8 register_data[0][0x20]; 7453 }; 7454 7455 struct mlx5_ifc_sltp_reg_bits { 7456 u8 status[0x4]; 7457 u8 version[0x4]; 7458 u8 local_port[0x8]; 7459 u8 pnat[0x2]; 7460 u8 reserved_at_12[0x2]; 7461 u8 lane[0x4]; 7462 u8 reserved_at_18[0x8]; 7463 7464 u8 reserved_at_20[0x20]; 7465 7466 u8 reserved_at_40[0x7]; 7467 u8 polarity[0x1]; 7468 u8 ob_tap0[0x8]; 7469 u8 ob_tap1[0x8]; 7470 u8 ob_tap2[0x8]; 7471 7472 u8 reserved_at_60[0xc]; 7473 u8 ob_preemp_mode[0x4]; 7474 u8 ob_reg[0x8]; 7475 u8 ob_bias[0x8]; 7476 7477 u8 reserved_at_80[0x20]; 7478 }; 7479 7480 struct mlx5_ifc_slrg_reg_bits { 7481 u8 status[0x4]; 7482 u8 version[0x4]; 7483 u8 local_port[0x8]; 7484 u8 pnat[0x2]; 7485 u8 reserved_at_12[0x2]; 7486 u8 lane[0x4]; 7487 u8 reserved_at_18[0x8]; 7488 7489 u8 time_to_link_up[0x10]; 7490 u8 reserved_at_30[0xc]; 7491 u8 grade_lane_speed[0x4]; 7492 7493 u8 grade_version[0x8]; 7494 u8 grade[0x18]; 7495 7496 u8 reserved_at_60[0x4]; 7497 u8 height_grade_type[0x4]; 7498 u8 height_grade[0x18]; 7499 7500 u8 height_dz[0x10]; 7501 u8 height_dv[0x10]; 7502 7503 u8 reserved_at_a0[0x10]; 7504 u8 height_sigma[0x10]; 7505 7506 u8 reserved_at_c0[0x20]; 7507 7508 u8 reserved_at_e0[0x4]; 7509 u8 phase_grade_type[0x4]; 7510 u8 phase_grade[0x18]; 7511 7512 u8 reserved_at_100[0x8]; 7513 u8 phase_eo_pos[0x8]; 7514 u8 reserved_at_110[0x8]; 7515 u8 phase_eo_neg[0x8]; 7516 7517 u8 ffe_set_tested[0x10]; 7518 u8 test_errors_per_lane[0x10]; 7519 }; 7520 7521 struct mlx5_ifc_pvlc_reg_bits { 7522 u8 reserved_at_0[0x8]; 7523 u8 local_port[0x8]; 7524 u8 reserved_at_10[0x10]; 7525 7526 u8 reserved_at_20[0x1c]; 7527 u8 vl_hw_cap[0x4]; 7528 7529 u8 reserved_at_40[0x1c]; 7530 u8 vl_admin[0x4]; 7531 7532 u8 reserved_at_60[0x1c]; 7533 u8 vl_operational[0x4]; 7534 }; 7535 7536 struct mlx5_ifc_pude_reg_bits { 7537 u8 swid[0x8]; 7538 u8 local_port[0x8]; 7539 u8 reserved_at_10[0x4]; 7540 u8 admin_status[0x4]; 7541 u8 reserved_at_18[0x4]; 7542 u8 oper_status[0x4]; 7543 7544 u8 reserved_at_20[0x60]; 7545 }; 7546 7547 struct mlx5_ifc_ptys_reg_bits { 7548 u8 reserved_at_0[0x1]; 7549 u8 an_disable_admin[0x1]; 7550 u8 an_disable_cap[0x1]; 7551 u8 reserved_at_3[0x5]; 7552 u8 local_port[0x8]; 7553 u8 reserved_at_10[0xd]; 7554 u8 proto_mask[0x3]; 7555 7556 u8 an_status[0x4]; 7557 u8 reserved_at_24[0x3c]; 7558 7559 u8 eth_proto_capability[0x20]; 7560 7561 u8 ib_link_width_capability[0x10]; 7562 u8 ib_proto_capability[0x10]; 7563 7564 u8 reserved_at_a0[0x20]; 7565 7566 u8 eth_proto_admin[0x20]; 7567 7568 u8 ib_link_width_admin[0x10]; 7569 u8 ib_proto_admin[0x10]; 7570 7571 u8 reserved_at_100[0x20]; 7572 7573 u8 eth_proto_oper[0x20]; 7574 7575 u8 ib_link_width_oper[0x10]; 7576 u8 ib_proto_oper[0x10]; 7577 7578 u8 reserved_at_160[0x1c]; 7579 u8 connector_type[0x4]; 7580 7581 u8 eth_proto_lp_advertise[0x20]; 7582 7583 u8 reserved_at_1a0[0x60]; 7584 }; 7585 7586 struct mlx5_ifc_mlcr_reg_bits { 7587 u8 reserved_at_0[0x8]; 7588 u8 local_port[0x8]; 7589 u8 reserved_at_10[0x20]; 7590 7591 u8 beacon_duration[0x10]; 7592 u8 reserved_at_40[0x10]; 7593 7594 u8 beacon_remain[0x10]; 7595 }; 7596 7597 struct mlx5_ifc_ptas_reg_bits { 7598 u8 reserved_at_0[0x20]; 7599 7600 u8 algorithm_options[0x10]; 7601 u8 reserved_at_30[0x4]; 7602 u8 repetitions_mode[0x4]; 7603 u8 num_of_repetitions[0x8]; 7604 7605 u8 grade_version[0x8]; 7606 u8 height_grade_type[0x4]; 7607 u8 phase_grade_type[0x4]; 7608 u8 height_grade_weight[0x8]; 7609 u8 phase_grade_weight[0x8]; 7610 7611 u8 gisim_measure_bits[0x10]; 7612 u8 adaptive_tap_measure_bits[0x10]; 7613 7614 u8 ber_bath_high_error_threshold[0x10]; 7615 u8 ber_bath_mid_error_threshold[0x10]; 7616 7617 u8 ber_bath_low_error_threshold[0x10]; 7618 u8 one_ratio_high_threshold[0x10]; 7619 7620 u8 one_ratio_high_mid_threshold[0x10]; 7621 u8 one_ratio_low_mid_threshold[0x10]; 7622 7623 u8 one_ratio_low_threshold[0x10]; 7624 u8 ndeo_error_threshold[0x10]; 7625 7626 u8 mixer_offset_step_size[0x10]; 7627 u8 reserved_at_110[0x8]; 7628 u8 mix90_phase_for_voltage_bath[0x8]; 7629 7630 u8 mixer_offset_start[0x10]; 7631 u8 mixer_offset_end[0x10]; 7632 7633 u8 reserved_at_140[0x15]; 7634 u8 ber_test_time[0xb]; 7635 }; 7636 7637 struct mlx5_ifc_pspa_reg_bits { 7638 u8 swid[0x8]; 7639 u8 local_port[0x8]; 7640 u8 sub_port[0x8]; 7641 u8 reserved_at_18[0x8]; 7642 7643 u8 reserved_at_20[0x20]; 7644 }; 7645 7646 struct mlx5_ifc_pqdr_reg_bits { 7647 u8 reserved_at_0[0x8]; 7648 u8 local_port[0x8]; 7649 u8 reserved_at_10[0x5]; 7650 u8 prio[0x3]; 7651 u8 reserved_at_18[0x6]; 7652 u8 mode[0x2]; 7653 7654 u8 reserved_at_20[0x20]; 7655 7656 u8 reserved_at_40[0x10]; 7657 u8 min_threshold[0x10]; 7658 7659 u8 reserved_at_60[0x10]; 7660 u8 max_threshold[0x10]; 7661 7662 u8 reserved_at_80[0x10]; 7663 u8 mark_probability_denominator[0x10]; 7664 7665 u8 reserved_at_a0[0x60]; 7666 }; 7667 7668 struct mlx5_ifc_ppsc_reg_bits { 7669 u8 reserved_at_0[0x8]; 7670 u8 local_port[0x8]; 7671 u8 reserved_at_10[0x10]; 7672 7673 u8 reserved_at_20[0x60]; 7674 7675 u8 reserved_at_80[0x1c]; 7676 u8 wrps_admin[0x4]; 7677 7678 u8 reserved_at_a0[0x1c]; 7679 u8 wrps_status[0x4]; 7680 7681 u8 reserved_at_c0[0x8]; 7682 u8 up_threshold[0x8]; 7683 u8 reserved_at_d0[0x8]; 7684 u8 down_threshold[0x8]; 7685 7686 u8 reserved_at_e0[0x20]; 7687 7688 u8 reserved_at_100[0x1c]; 7689 u8 srps_admin[0x4]; 7690 7691 u8 reserved_at_120[0x1c]; 7692 u8 srps_status[0x4]; 7693 7694 u8 reserved_at_140[0x40]; 7695 }; 7696 7697 struct mlx5_ifc_pplr_reg_bits { 7698 u8 reserved_at_0[0x8]; 7699 u8 local_port[0x8]; 7700 u8 reserved_at_10[0x10]; 7701 7702 u8 reserved_at_20[0x8]; 7703 u8 lb_cap[0x8]; 7704 u8 reserved_at_30[0x8]; 7705 u8 lb_en[0x8]; 7706 }; 7707 7708 struct mlx5_ifc_pplm_reg_bits { 7709 u8 reserved_at_0[0x8]; 7710 u8 local_port[0x8]; 7711 u8 reserved_at_10[0x10]; 7712 7713 u8 reserved_at_20[0x20]; 7714 7715 u8 port_profile_mode[0x8]; 7716 u8 static_port_profile[0x8]; 7717 u8 active_port_profile[0x8]; 7718 u8 reserved_at_58[0x8]; 7719 7720 u8 retransmission_active[0x8]; 7721 u8 fec_mode_active[0x18]; 7722 7723 u8 reserved_at_80[0x20]; 7724 }; 7725 7726 struct mlx5_ifc_ppcnt_reg_bits { 7727 u8 swid[0x8]; 7728 u8 local_port[0x8]; 7729 u8 pnat[0x2]; 7730 u8 reserved_at_12[0x8]; 7731 u8 grp[0x6]; 7732 7733 u8 clr[0x1]; 7734 u8 reserved_at_21[0x1c]; 7735 u8 prio_tc[0x3]; 7736 7737 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set; 7738 }; 7739 7740 struct mlx5_ifc_mpcnt_reg_bits { 7741 u8 reserved_at_0[0x8]; 7742 u8 pcie_index[0x8]; 7743 u8 reserved_at_10[0xa]; 7744 u8 grp[0x6]; 7745 7746 u8 clr[0x1]; 7747 u8 reserved_at_21[0x1f]; 7748 7749 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set; 7750 }; 7751 7752 struct mlx5_ifc_ppad_reg_bits { 7753 u8 reserved_at_0[0x3]; 7754 u8 single_mac[0x1]; 7755 u8 reserved_at_4[0x4]; 7756 u8 local_port[0x8]; 7757 u8 mac_47_32[0x10]; 7758 7759 u8 mac_31_0[0x20]; 7760 7761 u8 reserved_at_40[0x40]; 7762 }; 7763 7764 struct mlx5_ifc_pmtu_reg_bits { 7765 u8 reserved_at_0[0x8]; 7766 u8 local_port[0x8]; 7767 u8 reserved_at_10[0x10]; 7768 7769 u8 max_mtu[0x10]; 7770 u8 reserved_at_30[0x10]; 7771 7772 u8 admin_mtu[0x10]; 7773 u8 reserved_at_50[0x10]; 7774 7775 u8 oper_mtu[0x10]; 7776 u8 reserved_at_70[0x10]; 7777 }; 7778 7779 struct mlx5_ifc_pmpr_reg_bits { 7780 u8 reserved_at_0[0x8]; 7781 u8 module[0x8]; 7782 u8 reserved_at_10[0x10]; 7783 7784 u8 reserved_at_20[0x18]; 7785 u8 attenuation_5g[0x8]; 7786 7787 u8 reserved_at_40[0x18]; 7788 u8 attenuation_7g[0x8]; 7789 7790 u8 reserved_at_60[0x18]; 7791 u8 attenuation_12g[0x8]; 7792 }; 7793 7794 struct mlx5_ifc_pmpe_reg_bits { 7795 u8 reserved_at_0[0x8]; 7796 u8 module[0x8]; 7797 u8 reserved_at_10[0xc]; 7798 u8 module_status[0x4]; 7799 7800 u8 reserved_at_20[0x60]; 7801 }; 7802 7803 struct mlx5_ifc_pmpc_reg_bits { 7804 u8 module_state_updated[32][0x8]; 7805 }; 7806 7807 struct mlx5_ifc_pmlpn_reg_bits { 7808 u8 reserved_at_0[0x4]; 7809 u8 mlpn_status[0x4]; 7810 u8 local_port[0x8]; 7811 u8 reserved_at_10[0x10]; 7812 7813 u8 e[0x1]; 7814 u8 reserved_at_21[0x1f]; 7815 }; 7816 7817 struct mlx5_ifc_pmlp_reg_bits { 7818 u8 rxtx[0x1]; 7819 u8 reserved_at_1[0x7]; 7820 u8 local_port[0x8]; 7821 u8 reserved_at_10[0x8]; 7822 u8 width[0x8]; 7823 7824 u8 lane0_module_mapping[0x20]; 7825 7826 u8 lane1_module_mapping[0x20]; 7827 7828 u8 lane2_module_mapping[0x20]; 7829 7830 u8 lane3_module_mapping[0x20]; 7831 7832 u8 reserved_at_a0[0x160]; 7833 }; 7834 7835 struct mlx5_ifc_pmaos_reg_bits { 7836 u8 reserved_at_0[0x8]; 7837 u8 module[0x8]; 7838 u8 reserved_at_10[0x4]; 7839 u8 admin_status[0x4]; 7840 u8 reserved_at_18[0x4]; 7841 u8 oper_status[0x4]; 7842 7843 u8 ase[0x1]; 7844 u8 ee[0x1]; 7845 u8 reserved_at_22[0x1c]; 7846 u8 e[0x2]; 7847 7848 u8 reserved_at_40[0x40]; 7849 }; 7850 7851 struct mlx5_ifc_plpc_reg_bits { 7852 u8 reserved_at_0[0x4]; 7853 u8 profile_id[0xc]; 7854 u8 reserved_at_10[0x4]; 7855 u8 proto_mask[0x4]; 7856 u8 reserved_at_18[0x8]; 7857 7858 u8 reserved_at_20[0x10]; 7859 u8 lane_speed[0x10]; 7860 7861 u8 reserved_at_40[0x17]; 7862 u8 lpbf[0x1]; 7863 u8 fec_mode_policy[0x8]; 7864 7865 u8 retransmission_capability[0x8]; 7866 u8 fec_mode_capability[0x18]; 7867 7868 u8 retransmission_support_admin[0x8]; 7869 u8 fec_mode_support_admin[0x18]; 7870 7871 u8 retransmission_request_admin[0x8]; 7872 u8 fec_mode_request_admin[0x18]; 7873 7874 u8 reserved_at_c0[0x80]; 7875 }; 7876 7877 struct mlx5_ifc_plib_reg_bits { 7878 u8 reserved_at_0[0x8]; 7879 u8 local_port[0x8]; 7880 u8 reserved_at_10[0x8]; 7881 u8 ib_port[0x8]; 7882 7883 u8 reserved_at_20[0x60]; 7884 }; 7885 7886 struct mlx5_ifc_plbf_reg_bits { 7887 u8 reserved_at_0[0x8]; 7888 u8 local_port[0x8]; 7889 u8 reserved_at_10[0xd]; 7890 u8 lbf_mode[0x3]; 7891 7892 u8 reserved_at_20[0x20]; 7893 }; 7894 7895 struct mlx5_ifc_pipg_reg_bits { 7896 u8 reserved_at_0[0x8]; 7897 u8 local_port[0x8]; 7898 u8 reserved_at_10[0x10]; 7899 7900 u8 dic[0x1]; 7901 u8 reserved_at_21[0x19]; 7902 u8 ipg[0x4]; 7903 u8 reserved_at_3e[0x2]; 7904 }; 7905 7906 struct mlx5_ifc_pifr_reg_bits { 7907 u8 reserved_at_0[0x8]; 7908 u8 local_port[0x8]; 7909 u8 reserved_at_10[0x10]; 7910 7911 u8 reserved_at_20[0xe0]; 7912 7913 u8 port_filter[8][0x20]; 7914 7915 u8 port_filter_update_en[8][0x20]; 7916 }; 7917 7918 struct mlx5_ifc_pfcc_reg_bits { 7919 u8 reserved_at_0[0x8]; 7920 u8 local_port[0x8]; 7921 u8 reserved_at_10[0xb]; 7922 u8 ppan_mask_n[0x1]; 7923 u8 minor_stall_mask[0x1]; 7924 u8 critical_stall_mask[0x1]; 7925 u8 reserved_at_1e[0x2]; 7926 7927 u8 ppan[0x4]; 7928 u8 reserved_at_24[0x4]; 7929 u8 prio_mask_tx[0x8]; 7930 u8 reserved_at_30[0x8]; 7931 u8 prio_mask_rx[0x8]; 7932 7933 u8 pptx[0x1]; 7934 u8 aptx[0x1]; 7935 u8 pptx_mask_n[0x1]; 7936 u8 reserved_at_43[0x5]; 7937 u8 pfctx[0x8]; 7938 u8 reserved_at_50[0x10]; 7939 7940 u8 pprx[0x1]; 7941 u8 aprx[0x1]; 7942 u8 pprx_mask_n[0x1]; 7943 u8 reserved_at_63[0x5]; 7944 u8 pfcrx[0x8]; 7945 u8 reserved_at_70[0x10]; 7946 7947 u8 device_stall_minor_watermark[0x10]; 7948 u8 device_stall_critical_watermark[0x10]; 7949 7950 u8 reserved_at_a0[0x60]; 7951 }; 7952 7953 struct mlx5_ifc_pelc_reg_bits { 7954 u8 op[0x4]; 7955 u8 reserved_at_4[0x4]; 7956 u8 local_port[0x8]; 7957 u8 reserved_at_10[0x10]; 7958 7959 u8 op_admin[0x8]; 7960 u8 op_capability[0x8]; 7961 u8 op_request[0x8]; 7962 u8 op_active[0x8]; 7963 7964 u8 admin[0x40]; 7965 7966 u8 capability[0x40]; 7967 7968 u8 request[0x40]; 7969 7970 u8 active[0x40]; 7971 7972 u8 reserved_at_140[0x80]; 7973 }; 7974 7975 struct mlx5_ifc_peir_reg_bits { 7976 u8 reserved_at_0[0x8]; 7977 u8 local_port[0x8]; 7978 u8 reserved_at_10[0x10]; 7979 7980 u8 reserved_at_20[0xc]; 7981 u8 error_count[0x4]; 7982 u8 reserved_at_30[0x10]; 7983 7984 u8 reserved_at_40[0xc]; 7985 u8 lane[0x4]; 7986 u8 reserved_at_50[0x8]; 7987 u8 error_type[0x8]; 7988 }; 7989 7990 struct mlx5_ifc_pcam_enhanced_features_bits { 7991 u8 reserved_at_0[0x76]; 7992 7993 u8 pfcc_mask[0x1]; 7994 u8 reserved_at_77[0x4]; 7995 u8 rx_buffer_fullness_counters[0x1]; 7996 u8 ptys_connector_type[0x1]; 7997 u8 reserved_at_7d[0x1]; 7998 u8 ppcnt_discard_group[0x1]; 7999 u8 ppcnt_statistical_group[0x1]; 8000 }; 8001 8002 struct mlx5_ifc_pcam_reg_bits { 8003 u8 reserved_at_0[0x8]; 8004 u8 feature_group[0x8]; 8005 u8 reserved_at_10[0x8]; 8006 u8 access_reg_group[0x8]; 8007 8008 u8 reserved_at_20[0x20]; 8009 8010 union { 8011 u8 reserved_at_0[0x80]; 8012 } port_access_reg_cap_mask; 8013 8014 u8 reserved_at_c0[0x80]; 8015 8016 union { 8017 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features; 8018 u8 reserved_at_0[0x80]; 8019 } feature_cap_mask; 8020 8021 u8 reserved_at_1c0[0xc0]; 8022 }; 8023 8024 struct mlx5_ifc_mcam_enhanced_features_bits { 8025 u8 reserved_at_0[0x7b]; 8026 u8 pcie_outbound_stalled[0x1]; 8027 u8 tx_overflow_buffer_pkt[0x1]; 8028 u8 mtpps_enh_out_per_adj[0x1]; 8029 u8 mtpps_fs[0x1]; 8030 u8 pcie_performance_group[0x1]; 8031 }; 8032 8033 struct mlx5_ifc_mcam_access_reg_bits { 8034 u8 reserved_at_0[0x1c]; 8035 u8 mcda[0x1]; 8036 u8 mcc[0x1]; 8037 u8 mcqi[0x1]; 8038 u8 reserved_at_1f[0x1]; 8039 8040 u8 regs_95_to_64[0x20]; 8041 u8 regs_63_to_32[0x20]; 8042 u8 regs_31_to_0[0x20]; 8043 }; 8044 8045 struct mlx5_ifc_mcam_reg_bits { 8046 u8 reserved_at_0[0x8]; 8047 u8 feature_group[0x8]; 8048 u8 reserved_at_10[0x8]; 8049 u8 access_reg_group[0x8]; 8050 8051 u8 reserved_at_20[0x20]; 8052 8053 union { 8054 struct mlx5_ifc_mcam_access_reg_bits access_regs; 8055 u8 reserved_at_0[0x80]; 8056 } mng_access_reg_cap_mask; 8057 8058 u8 reserved_at_c0[0x80]; 8059 8060 union { 8061 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features; 8062 u8 reserved_at_0[0x80]; 8063 } mng_feature_cap_mask; 8064 8065 u8 reserved_at_1c0[0x80]; 8066 }; 8067 8068 struct mlx5_ifc_qcam_access_reg_cap_mask { 8069 u8 qcam_access_reg_cap_mask_127_to_20[0x6C]; 8070 u8 qpdpm[0x1]; 8071 u8 qcam_access_reg_cap_mask_18_to_4[0x0F]; 8072 u8 qdpm[0x1]; 8073 u8 qpts[0x1]; 8074 u8 qcap[0x1]; 8075 u8 qcam_access_reg_cap_mask_0[0x1]; 8076 }; 8077 8078 struct mlx5_ifc_qcam_qos_feature_cap_mask { 8079 u8 qcam_qos_feature_cap_mask_127_to_1[0x7F]; 8080 u8 qpts_trust_both[0x1]; 8081 }; 8082 8083 struct mlx5_ifc_qcam_reg_bits { 8084 u8 reserved_at_0[0x8]; 8085 u8 feature_group[0x8]; 8086 u8 reserved_at_10[0x8]; 8087 u8 access_reg_group[0x8]; 8088 u8 reserved_at_20[0x20]; 8089 8090 union { 8091 struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap; 8092 u8 reserved_at_0[0x80]; 8093 } qos_access_reg_cap_mask; 8094 8095 u8 reserved_at_c0[0x80]; 8096 8097 union { 8098 struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap; 8099 u8 reserved_at_0[0x80]; 8100 } qos_feature_cap_mask; 8101 8102 u8 reserved_at_1c0[0x80]; 8103 }; 8104 8105 struct mlx5_ifc_pcap_reg_bits { 8106 u8 reserved_at_0[0x8]; 8107 u8 local_port[0x8]; 8108 u8 reserved_at_10[0x10]; 8109 8110 u8 port_capability_mask[4][0x20]; 8111 }; 8112 8113 struct mlx5_ifc_paos_reg_bits { 8114 u8 swid[0x8]; 8115 u8 local_port[0x8]; 8116 u8 reserved_at_10[0x4]; 8117 u8 admin_status[0x4]; 8118 u8 reserved_at_18[0x4]; 8119 u8 oper_status[0x4]; 8120 8121 u8 ase[0x1]; 8122 u8 ee[0x1]; 8123 u8 reserved_at_22[0x1c]; 8124 u8 e[0x2]; 8125 8126 u8 reserved_at_40[0x40]; 8127 }; 8128 8129 struct mlx5_ifc_pamp_reg_bits { 8130 u8 reserved_at_0[0x8]; 8131 u8 opamp_group[0x8]; 8132 u8 reserved_at_10[0xc]; 8133 u8 opamp_group_type[0x4]; 8134 8135 u8 start_index[0x10]; 8136 u8 reserved_at_30[0x4]; 8137 u8 num_of_indices[0xc]; 8138 8139 u8 index_data[18][0x10]; 8140 }; 8141 8142 struct mlx5_ifc_pcmr_reg_bits { 8143 u8 reserved_at_0[0x8]; 8144 u8 local_port[0x8]; 8145 u8 reserved_at_10[0x2e]; 8146 u8 fcs_cap[0x1]; 8147 u8 reserved_at_3f[0x1f]; 8148 u8 fcs_chk[0x1]; 8149 u8 reserved_at_5f[0x1]; 8150 }; 8151 8152 struct mlx5_ifc_lane_2_module_mapping_bits { 8153 u8 reserved_at_0[0x6]; 8154 u8 rx_lane[0x2]; 8155 u8 reserved_at_8[0x6]; 8156 u8 tx_lane[0x2]; 8157 u8 reserved_at_10[0x8]; 8158 u8 module[0x8]; 8159 }; 8160 8161 struct mlx5_ifc_bufferx_reg_bits { 8162 u8 reserved_at_0[0x6]; 8163 u8 lossy[0x1]; 8164 u8 epsb[0x1]; 8165 u8 reserved_at_8[0xc]; 8166 u8 size[0xc]; 8167 8168 u8 xoff_threshold[0x10]; 8169 u8 xon_threshold[0x10]; 8170 }; 8171 8172 struct mlx5_ifc_set_node_in_bits { 8173 u8 node_description[64][0x8]; 8174 }; 8175 8176 struct mlx5_ifc_register_power_settings_bits { 8177 u8 reserved_at_0[0x18]; 8178 u8 power_settings_level[0x8]; 8179 8180 u8 reserved_at_20[0x60]; 8181 }; 8182 8183 struct mlx5_ifc_register_host_endianness_bits { 8184 u8 he[0x1]; 8185 u8 reserved_at_1[0x1f]; 8186 8187 u8 reserved_at_20[0x60]; 8188 }; 8189 8190 struct mlx5_ifc_umr_pointer_desc_argument_bits { 8191 u8 reserved_at_0[0x20]; 8192 8193 u8 mkey[0x20]; 8194 8195 u8 addressh_63_32[0x20]; 8196 8197 u8 addressl_31_0[0x20]; 8198 }; 8199 8200 struct mlx5_ifc_ud_adrs_vector_bits { 8201 u8 dc_key[0x40]; 8202 8203 u8 ext[0x1]; 8204 u8 reserved_at_41[0x7]; 8205 u8 destination_qp_dct[0x18]; 8206 8207 u8 static_rate[0x4]; 8208 u8 sl_eth_prio[0x4]; 8209 u8 fl[0x1]; 8210 u8 mlid[0x7]; 8211 u8 rlid_udp_sport[0x10]; 8212 8213 u8 reserved_at_80[0x20]; 8214 8215 u8 rmac_47_16[0x20]; 8216 8217 u8 rmac_15_0[0x10]; 8218 u8 tclass[0x8]; 8219 u8 hop_limit[0x8]; 8220 8221 u8 reserved_at_e0[0x1]; 8222 u8 grh[0x1]; 8223 u8 reserved_at_e2[0x2]; 8224 u8 src_addr_index[0x8]; 8225 u8 flow_label[0x14]; 8226 8227 u8 rgid_rip[16][0x8]; 8228 }; 8229 8230 struct mlx5_ifc_pages_req_event_bits { 8231 u8 reserved_at_0[0x10]; 8232 u8 function_id[0x10]; 8233 8234 u8 num_pages[0x20]; 8235 8236 u8 reserved_at_40[0xa0]; 8237 }; 8238 8239 struct mlx5_ifc_eqe_bits { 8240 u8 reserved_at_0[0x8]; 8241 u8 event_type[0x8]; 8242 u8 reserved_at_10[0x8]; 8243 u8 event_sub_type[0x8]; 8244 8245 u8 reserved_at_20[0xe0]; 8246 8247 union mlx5_ifc_event_auto_bits event_data; 8248 8249 u8 reserved_at_1e0[0x10]; 8250 u8 signature[0x8]; 8251 u8 reserved_at_1f8[0x7]; 8252 u8 owner[0x1]; 8253 }; 8254 8255 enum { 8256 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7, 8257 }; 8258 8259 struct mlx5_ifc_cmd_queue_entry_bits { 8260 u8 type[0x8]; 8261 u8 reserved_at_8[0x18]; 8262 8263 u8 input_length[0x20]; 8264 8265 u8 input_mailbox_pointer_63_32[0x20]; 8266 8267 u8 input_mailbox_pointer_31_9[0x17]; 8268 u8 reserved_at_77[0x9]; 8269 8270 u8 command_input_inline_data[16][0x8]; 8271 8272 u8 command_output_inline_data[16][0x8]; 8273 8274 u8 output_mailbox_pointer_63_32[0x20]; 8275 8276 u8 output_mailbox_pointer_31_9[0x17]; 8277 u8 reserved_at_1b7[0x9]; 8278 8279 u8 output_length[0x20]; 8280 8281 u8 token[0x8]; 8282 u8 signature[0x8]; 8283 u8 reserved_at_1f0[0x8]; 8284 u8 status[0x7]; 8285 u8 ownership[0x1]; 8286 }; 8287 8288 struct mlx5_ifc_cmd_out_bits { 8289 u8 status[0x8]; 8290 u8 reserved_at_8[0x18]; 8291 8292 u8 syndrome[0x20]; 8293 8294 u8 command_output[0x20]; 8295 }; 8296 8297 struct mlx5_ifc_cmd_in_bits { 8298 u8 opcode[0x10]; 8299 u8 reserved_at_10[0x10]; 8300 8301 u8 reserved_at_20[0x10]; 8302 u8 op_mod[0x10]; 8303 8304 u8 command[0][0x20]; 8305 }; 8306 8307 struct mlx5_ifc_cmd_if_box_bits { 8308 u8 mailbox_data[512][0x8]; 8309 8310 u8 reserved_at_1000[0x180]; 8311 8312 u8 next_pointer_63_32[0x20]; 8313 8314 u8 next_pointer_31_10[0x16]; 8315 u8 reserved_at_11b6[0xa]; 8316 8317 u8 block_number[0x20]; 8318 8319 u8 reserved_at_11e0[0x8]; 8320 u8 token[0x8]; 8321 u8 ctrl_signature[0x8]; 8322 u8 signature[0x8]; 8323 }; 8324 8325 struct mlx5_ifc_mtt_bits { 8326 u8 ptag_63_32[0x20]; 8327 8328 u8 ptag_31_8[0x18]; 8329 u8 reserved_at_38[0x6]; 8330 u8 wr_en[0x1]; 8331 u8 rd_en[0x1]; 8332 }; 8333 8334 struct mlx5_ifc_query_wol_rol_out_bits { 8335 u8 status[0x8]; 8336 u8 reserved_at_8[0x18]; 8337 8338 u8 syndrome[0x20]; 8339 8340 u8 reserved_at_40[0x10]; 8341 u8 rol_mode[0x8]; 8342 u8 wol_mode[0x8]; 8343 8344 u8 reserved_at_60[0x20]; 8345 }; 8346 8347 struct mlx5_ifc_query_wol_rol_in_bits { 8348 u8 opcode[0x10]; 8349 u8 reserved_at_10[0x10]; 8350 8351 u8 reserved_at_20[0x10]; 8352 u8 op_mod[0x10]; 8353 8354 u8 reserved_at_40[0x40]; 8355 }; 8356 8357 struct mlx5_ifc_set_wol_rol_out_bits { 8358 u8 status[0x8]; 8359 u8 reserved_at_8[0x18]; 8360 8361 u8 syndrome[0x20]; 8362 8363 u8 reserved_at_40[0x40]; 8364 }; 8365 8366 struct mlx5_ifc_set_wol_rol_in_bits { 8367 u8 opcode[0x10]; 8368 u8 reserved_at_10[0x10]; 8369 8370 u8 reserved_at_20[0x10]; 8371 u8 op_mod[0x10]; 8372 8373 u8 rol_mode_valid[0x1]; 8374 u8 wol_mode_valid[0x1]; 8375 u8 reserved_at_42[0xe]; 8376 u8 rol_mode[0x8]; 8377 u8 wol_mode[0x8]; 8378 8379 u8 reserved_at_60[0x20]; 8380 }; 8381 8382 enum { 8383 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0, 8384 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1, 8385 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2, 8386 }; 8387 8388 enum { 8389 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0, 8390 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1, 8391 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2, 8392 }; 8393 8394 enum { 8395 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR = 0x1, 8396 MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC = 0x7, 8397 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR = 0x8, 8398 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR = 0x9, 8399 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR = 0xa, 8400 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR = 0xb, 8401 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN = 0xc, 8402 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR = 0xd, 8403 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV = 0xe, 8404 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR = 0xf, 8405 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR = 0x10, 8406 }; 8407 8408 struct mlx5_ifc_initial_seg_bits { 8409 u8 fw_rev_minor[0x10]; 8410 u8 fw_rev_major[0x10]; 8411 8412 u8 cmd_interface_rev[0x10]; 8413 u8 fw_rev_subminor[0x10]; 8414 8415 u8 reserved_at_40[0x40]; 8416 8417 u8 cmdq_phy_addr_63_32[0x20]; 8418 8419 u8 cmdq_phy_addr_31_12[0x14]; 8420 u8 reserved_at_b4[0x2]; 8421 u8 nic_interface[0x2]; 8422 u8 log_cmdq_size[0x4]; 8423 u8 log_cmdq_stride[0x4]; 8424 8425 u8 command_doorbell_vector[0x20]; 8426 8427 u8 reserved_at_e0[0xf00]; 8428 8429 u8 initializing[0x1]; 8430 u8 reserved_at_fe1[0x4]; 8431 u8 nic_interface_supported[0x3]; 8432 u8 reserved_at_fe8[0x18]; 8433 8434 struct mlx5_ifc_health_buffer_bits health_buffer; 8435 8436 u8 no_dram_nic_offset[0x20]; 8437 8438 u8 reserved_at_1220[0x6e40]; 8439 8440 u8 reserved_at_8060[0x1f]; 8441 u8 clear_int[0x1]; 8442 8443 u8 health_syndrome[0x8]; 8444 u8 health_counter[0x18]; 8445 8446 u8 reserved_at_80a0[0x17fc0]; 8447 }; 8448 8449 struct mlx5_ifc_mtpps_reg_bits { 8450 u8 reserved_at_0[0xc]; 8451 u8 cap_number_of_pps_pins[0x4]; 8452 u8 reserved_at_10[0x4]; 8453 u8 cap_max_num_of_pps_in_pins[0x4]; 8454 u8 reserved_at_18[0x4]; 8455 u8 cap_max_num_of_pps_out_pins[0x4]; 8456 8457 u8 reserved_at_20[0x24]; 8458 u8 cap_pin_3_mode[0x4]; 8459 u8 reserved_at_48[0x4]; 8460 u8 cap_pin_2_mode[0x4]; 8461 u8 reserved_at_50[0x4]; 8462 u8 cap_pin_1_mode[0x4]; 8463 u8 reserved_at_58[0x4]; 8464 u8 cap_pin_0_mode[0x4]; 8465 8466 u8 reserved_at_60[0x4]; 8467 u8 cap_pin_7_mode[0x4]; 8468 u8 reserved_at_68[0x4]; 8469 u8 cap_pin_6_mode[0x4]; 8470 u8 reserved_at_70[0x4]; 8471 u8 cap_pin_5_mode[0x4]; 8472 u8 reserved_at_78[0x4]; 8473 u8 cap_pin_4_mode[0x4]; 8474 8475 u8 field_select[0x20]; 8476 u8 reserved_at_a0[0x60]; 8477 8478 u8 enable[0x1]; 8479 u8 reserved_at_101[0xb]; 8480 u8 pattern[0x4]; 8481 u8 reserved_at_110[0x4]; 8482 u8 pin_mode[0x4]; 8483 u8 pin[0x8]; 8484 8485 u8 reserved_at_120[0x20]; 8486 8487 u8 time_stamp[0x40]; 8488 8489 u8 out_pulse_duration[0x10]; 8490 u8 out_periodic_adjustment[0x10]; 8491 u8 enhanced_out_periodic_adjustment[0x20]; 8492 8493 u8 reserved_at_1c0[0x20]; 8494 }; 8495 8496 struct mlx5_ifc_mtppse_reg_bits { 8497 u8 reserved_at_0[0x18]; 8498 u8 pin[0x8]; 8499 u8 event_arm[0x1]; 8500 u8 reserved_at_21[0x1b]; 8501 u8 event_generation_mode[0x4]; 8502 u8 reserved_at_40[0x40]; 8503 }; 8504 8505 struct mlx5_ifc_mcqi_cap_bits { 8506 u8 supported_info_bitmask[0x20]; 8507 8508 u8 component_size[0x20]; 8509 8510 u8 max_component_size[0x20]; 8511 8512 u8 log_mcda_word_size[0x4]; 8513 u8 reserved_at_64[0xc]; 8514 u8 mcda_max_write_size[0x10]; 8515 8516 u8 rd_en[0x1]; 8517 u8 reserved_at_81[0x1]; 8518 u8 match_chip_id[0x1]; 8519 u8 match_psid[0x1]; 8520 u8 check_user_timestamp[0x1]; 8521 u8 match_base_guid_mac[0x1]; 8522 u8 reserved_at_86[0x1a]; 8523 }; 8524 8525 struct mlx5_ifc_mcqi_reg_bits { 8526 u8 read_pending_component[0x1]; 8527 u8 reserved_at_1[0xf]; 8528 u8 component_index[0x10]; 8529 8530 u8 reserved_at_20[0x20]; 8531 8532 u8 reserved_at_40[0x1b]; 8533 u8 info_type[0x5]; 8534 8535 u8 info_size[0x20]; 8536 8537 u8 offset[0x20]; 8538 8539 u8 reserved_at_a0[0x10]; 8540 u8 data_size[0x10]; 8541 8542 u8 data[0][0x20]; 8543 }; 8544 8545 struct mlx5_ifc_mcc_reg_bits { 8546 u8 reserved_at_0[0x4]; 8547 u8 time_elapsed_since_last_cmd[0xc]; 8548 u8 reserved_at_10[0x8]; 8549 u8 instruction[0x8]; 8550 8551 u8 reserved_at_20[0x10]; 8552 u8 component_index[0x10]; 8553 8554 u8 reserved_at_40[0x8]; 8555 u8 update_handle[0x18]; 8556 8557 u8 handle_owner_type[0x4]; 8558 u8 handle_owner_host_id[0x4]; 8559 u8 reserved_at_68[0x1]; 8560 u8 control_progress[0x7]; 8561 u8 error_code[0x8]; 8562 u8 reserved_at_78[0x4]; 8563 u8 control_state[0x4]; 8564 8565 u8 component_size[0x20]; 8566 8567 u8 reserved_at_a0[0x60]; 8568 }; 8569 8570 struct mlx5_ifc_mcda_reg_bits { 8571 u8 reserved_at_0[0x8]; 8572 u8 update_handle[0x18]; 8573 8574 u8 offset[0x20]; 8575 8576 u8 reserved_at_40[0x10]; 8577 u8 size[0x10]; 8578 8579 u8 reserved_at_60[0x20]; 8580 8581 u8 data[0][0x20]; 8582 }; 8583 8584 union mlx5_ifc_ports_control_registers_document_bits { 8585 struct mlx5_ifc_bufferx_reg_bits bufferx_reg; 8586 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 8587 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 8588 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 8589 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 8590 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 8591 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 8592 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout; 8593 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping; 8594 struct mlx5_ifc_pamp_reg_bits pamp_reg; 8595 struct mlx5_ifc_paos_reg_bits paos_reg; 8596 struct mlx5_ifc_pcap_reg_bits pcap_reg; 8597 struct mlx5_ifc_peir_reg_bits peir_reg; 8598 struct mlx5_ifc_pelc_reg_bits pelc_reg; 8599 struct mlx5_ifc_pfcc_reg_bits pfcc_reg; 8600 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 8601 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 8602 struct mlx5_ifc_pifr_reg_bits pifr_reg; 8603 struct mlx5_ifc_pipg_reg_bits pipg_reg; 8604 struct mlx5_ifc_plbf_reg_bits plbf_reg; 8605 struct mlx5_ifc_plib_reg_bits plib_reg; 8606 struct mlx5_ifc_plpc_reg_bits plpc_reg; 8607 struct mlx5_ifc_pmaos_reg_bits pmaos_reg; 8608 struct mlx5_ifc_pmlp_reg_bits pmlp_reg; 8609 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg; 8610 struct mlx5_ifc_pmpc_reg_bits pmpc_reg; 8611 struct mlx5_ifc_pmpe_reg_bits pmpe_reg; 8612 struct mlx5_ifc_pmpr_reg_bits pmpr_reg; 8613 struct mlx5_ifc_pmtu_reg_bits pmtu_reg; 8614 struct mlx5_ifc_ppad_reg_bits ppad_reg; 8615 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg; 8616 struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg; 8617 struct mlx5_ifc_pplm_reg_bits pplm_reg; 8618 struct mlx5_ifc_pplr_reg_bits pplr_reg; 8619 struct mlx5_ifc_ppsc_reg_bits ppsc_reg; 8620 struct mlx5_ifc_pqdr_reg_bits pqdr_reg; 8621 struct mlx5_ifc_pspa_reg_bits pspa_reg; 8622 struct mlx5_ifc_ptas_reg_bits ptas_reg; 8623 struct mlx5_ifc_ptys_reg_bits ptys_reg; 8624 struct mlx5_ifc_mlcr_reg_bits mlcr_reg; 8625 struct mlx5_ifc_pude_reg_bits pude_reg; 8626 struct mlx5_ifc_pvlc_reg_bits pvlc_reg; 8627 struct mlx5_ifc_slrg_reg_bits slrg_reg; 8628 struct mlx5_ifc_sltp_reg_bits sltp_reg; 8629 struct mlx5_ifc_mtpps_reg_bits mtpps_reg; 8630 struct mlx5_ifc_mtppse_reg_bits mtppse_reg; 8631 struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg; 8632 struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits; 8633 struct mlx5_ifc_fpga_cap_bits fpga_cap_bits; 8634 struct mlx5_ifc_mcqi_reg_bits mcqi_reg; 8635 struct mlx5_ifc_mcc_reg_bits mcc_reg; 8636 struct mlx5_ifc_mcda_reg_bits mcda_reg; 8637 u8 reserved_at_0[0x60e0]; 8638 }; 8639 8640 union mlx5_ifc_debug_enhancements_document_bits { 8641 struct mlx5_ifc_health_buffer_bits health_buffer; 8642 u8 reserved_at_0[0x200]; 8643 }; 8644 8645 union mlx5_ifc_uplink_pci_interface_document_bits { 8646 struct mlx5_ifc_initial_seg_bits initial_seg; 8647 u8 reserved_at_0[0x20060]; 8648 }; 8649 8650 struct mlx5_ifc_set_flow_table_root_out_bits { 8651 u8 status[0x8]; 8652 u8 reserved_at_8[0x18]; 8653 8654 u8 syndrome[0x20]; 8655 8656 u8 reserved_at_40[0x40]; 8657 }; 8658 8659 struct mlx5_ifc_set_flow_table_root_in_bits { 8660 u8 opcode[0x10]; 8661 u8 reserved_at_10[0x10]; 8662 8663 u8 reserved_at_20[0x10]; 8664 u8 op_mod[0x10]; 8665 8666 u8 other_vport[0x1]; 8667 u8 reserved_at_41[0xf]; 8668 u8 vport_number[0x10]; 8669 8670 u8 reserved_at_60[0x20]; 8671 8672 u8 table_type[0x8]; 8673 u8 reserved_at_88[0x18]; 8674 8675 u8 reserved_at_a0[0x8]; 8676 u8 table_id[0x18]; 8677 8678 u8 reserved_at_c0[0x8]; 8679 u8 underlay_qpn[0x18]; 8680 u8 reserved_at_e0[0x120]; 8681 }; 8682 8683 enum { 8684 MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = (1UL << 0), 8685 MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15), 8686 }; 8687 8688 struct mlx5_ifc_modify_flow_table_out_bits { 8689 u8 status[0x8]; 8690 u8 reserved_at_8[0x18]; 8691 8692 u8 syndrome[0x20]; 8693 8694 u8 reserved_at_40[0x40]; 8695 }; 8696 8697 struct mlx5_ifc_modify_flow_table_in_bits { 8698 u8 opcode[0x10]; 8699 u8 reserved_at_10[0x10]; 8700 8701 u8 reserved_at_20[0x10]; 8702 u8 op_mod[0x10]; 8703 8704 u8 other_vport[0x1]; 8705 u8 reserved_at_41[0xf]; 8706 u8 vport_number[0x10]; 8707 8708 u8 reserved_at_60[0x10]; 8709 u8 modify_field_select[0x10]; 8710 8711 u8 table_type[0x8]; 8712 u8 reserved_at_88[0x18]; 8713 8714 u8 reserved_at_a0[0x8]; 8715 u8 table_id[0x18]; 8716 8717 struct mlx5_ifc_flow_table_context_bits flow_table_context; 8718 }; 8719 8720 struct mlx5_ifc_ets_tcn_config_reg_bits { 8721 u8 g[0x1]; 8722 u8 b[0x1]; 8723 u8 r[0x1]; 8724 u8 reserved_at_3[0x9]; 8725 u8 group[0x4]; 8726 u8 reserved_at_10[0x9]; 8727 u8 bw_allocation[0x7]; 8728 8729 u8 reserved_at_20[0xc]; 8730 u8 max_bw_units[0x4]; 8731 u8 reserved_at_30[0x8]; 8732 u8 max_bw_value[0x8]; 8733 }; 8734 8735 struct mlx5_ifc_ets_global_config_reg_bits { 8736 u8 reserved_at_0[0x2]; 8737 u8 r[0x1]; 8738 u8 reserved_at_3[0x1d]; 8739 8740 u8 reserved_at_20[0xc]; 8741 u8 max_bw_units[0x4]; 8742 u8 reserved_at_30[0x8]; 8743 u8 max_bw_value[0x8]; 8744 }; 8745 8746 struct mlx5_ifc_qetc_reg_bits { 8747 u8 reserved_at_0[0x8]; 8748 u8 port_number[0x8]; 8749 u8 reserved_at_10[0x30]; 8750 8751 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8]; 8752 struct mlx5_ifc_ets_global_config_reg_bits global_configuration; 8753 }; 8754 8755 struct mlx5_ifc_qpdpm_dscp_reg_bits { 8756 u8 e[0x1]; 8757 u8 reserved_at_01[0x0b]; 8758 u8 prio[0x04]; 8759 }; 8760 8761 struct mlx5_ifc_qpdpm_reg_bits { 8762 u8 reserved_at_0[0x8]; 8763 u8 local_port[0x8]; 8764 u8 reserved_at_10[0x10]; 8765 struct mlx5_ifc_qpdpm_dscp_reg_bits dscp[64]; 8766 }; 8767 8768 struct mlx5_ifc_qpts_reg_bits { 8769 u8 reserved_at_0[0x8]; 8770 u8 local_port[0x8]; 8771 u8 reserved_at_10[0x2d]; 8772 u8 trust_state[0x3]; 8773 }; 8774 8775 struct mlx5_ifc_qtct_reg_bits { 8776 u8 reserved_at_0[0x8]; 8777 u8 port_number[0x8]; 8778 u8 reserved_at_10[0xd]; 8779 u8 prio[0x3]; 8780 8781 u8 reserved_at_20[0x1d]; 8782 u8 tclass[0x3]; 8783 }; 8784 8785 struct mlx5_ifc_mcia_reg_bits { 8786 u8 l[0x1]; 8787 u8 reserved_at_1[0x7]; 8788 u8 module[0x8]; 8789 u8 reserved_at_10[0x8]; 8790 u8 status[0x8]; 8791 8792 u8 i2c_device_address[0x8]; 8793 u8 page_number[0x8]; 8794 u8 device_address[0x10]; 8795 8796 u8 reserved_at_40[0x10]; 8797 u8 size[0x10]; 8798 8799 u8 reserved_at_60[0x20]; 8800 8801 u8 dword_0[0x20]; 8802 u8 dword_1[0x20]; 8803 u8 dword_2[0x20]; 8804 u8 dword_3[0x20]; 8805 u8 dword_4[0x20]; 8806 u8 dword_5[0x20]; 8807 u8 dword_6[0x20]; 8808 u8 dword_7[0x20]; 8809 u8 dword_8[0x20]; 8810 u8 dword_9[0x20]; 8811 u8 dword_10[0x20]; 8812 u8 dword_11[0x20]; 8813 }; 8814 8815 struct mlx5_ifc_dcbx_param_bits { 8816 u8 dcbx_cee_cap[0x1]; 8817 u8 dcbx_ieee_cap[0x1]; 8818 u8 dcbx_standby_cap[0x1]; 8819 u8 reserved_at_0[0x5]; 8820 u8 port_number[0x8]; 8821 u8 reserved_at_10[0xa]; 8822 u8 max_application_table_size[6]; 8823 u8 reserved_at_20[0x15]; 8824 u8 version_oper[0x3]; 8825 u8 reserved_at_38[5]; 8826 u8 version_admin[0x3]; 8827 u8 willing_admin[0x1]; 8828 u8 reserved_at_41[0x3]; 8829 u8 pfc_cap_oper[0x4]; 8830 u8 reserved_at_48[0x4]; 8831 u8 pfc_cap_admin[0x4]; 8832 u8 reserved_at_50[0x4]; 8833 u8 num_of_tc_oper[0x4]; 8834 u8 reserved_at_58[0x4]; 8835 u8 num_of_tc_admin[0x4]; 8836 u8 remote_willing[0x1]; 8837 u8 reserved_at_61[3]; 8838 u8 remote_pfc_cap[4]; 8839 u8 reserved_at_68[0x14]; 8840 u8 remote_num_of_tc[0x4]; 8841 u8 reserved_at_80[0x18]; 8842 u8 error[0x8]; 8843 u8 reserved_at_a0[0x160]; 8844 }; 8845 8846 struct mlx5_ifc_lagc_bits { 8847 u8 reserved_at_0[0x1d]; 8848 u8 lag_state[0x3]; 8849 8850 u8 reserved_at_20[0x14]; 8851 u8 tx_remap_affinity_2[0x4]; 8852 u8 reserved_at_38[0x4]; 8853 u8 tx_remap_affinity_1[0x4]; 8854 }; 8855 8856 struct mlx5_ifc_create_lag_out_bits { 8857 u8 status[0x8]; 8858 u8 reserved_at_8[0x18]; 8859 8860 u8 syndrome[0x20]; 8861 8862 u8 reserved_at_40[0x40]; 8863 }; 8864 8865 struct mlx5_ifc_create_lag_in_bits { 8866 u8 opcode[0x10]; 8867 u8 reserved_at_10[0x10]; 8868 8869 u8 reserved_at_20[0x10]; 8870 u8 op_mod[0x10]; 8871 8872 struct mlx5_ifc_lagc_bits ctx; 8873 }; 8874 8875 struct mlx5_ifc_modify_lag_out_bits { 8876 u8 status[0x8]; 8877 u8 reserved_at_8[0x18]; 8878 8879 u8 syndrome[0x20]; 8880 8881 u8 reserved_at_40[0x40]; 8882 }; 8883 8884 struct mlx5_ifc_modify_lag_in_bits { 8885 u8 opcode[0x10]; 8886 u8 reserved_at_10[0x10]; 8887 8888 u8 reserved_at_20[0x10]; 8889 u8 op_mod[0x10]; 8890 8891 u8 reserved_at_40[0x20]; 8892 u8 field_select[0x20]; 8893 8894 struct mlx5_ifc_lagc_bits ctx; 8895 }; 8896 8897 struct mlx5_ifc_query_lag_out_bits { 8898 u8 status[0x8]; 8899 u8 reserved_at_8[0x18]; 8900 8901 u8 syndrome[0x20]; 8902 8903 u8 reserved_at_40[0x40]; 8904 8905 struct mlx5_ifc_lagc_bits ctx; 8906 }; 8907 8908 struct mlx5_ifc_query_lag_in_bits { 8909 u8 opcode[0x10]; 8910 u8 reserved_at_10[0x10]; 8911 8912 u8 reserved_at_20[0x10]; 8913 u8 op_mod[0x10]; 8914 8915 u8 reserved_at_40[0x40]; 8916 }; 8917 8918 struct mlx5_ifc_destroy_lag_out_bits { 8919 u8 status[0x8]; 8920 u8 reserved_at_8[0x18]; 8921 8922 u8 syndrome[0x20]; 8923 8924 u8 reserved_at_40[0x40]; 8925 }; 8926 8927 struct mlx5_ifc_destroy_lag_in_bits { 8928 u8 opcode[0x10]; 8929 u8 reserved_at_10[0x10]; 8930 8931 u8 reserved_at_20[0x10]; 8932 u8 op_mod[0x10]; 8933 8934 u8 reserved_at_40[0x40]; 8935 }; 8936 8937 struct mlx5_ifc_create_vport_lag_out_bits { 8938 u8 status[0x8]; 8939 u8 reserved_at_8[0x18]; 8940 8941 u8 syndrome[0x20]; 8942 8943 u8 reserved_at_40[0x40]; 8944 }; 8945 8946 struct mlx5_ifc_create_vport_lag_in_bits { 8947 u8 opcode[0x10]; 8948 u8 reserved_at_10[0x10]; 8949 8950 u8 reserved_at_20[0x10]; 8951 u8 op_mod[0x10]; 8952 8953 u8 reserved_at_40[0x40]; 8954 }; 8955 8956 struct mlx5_ifc_destroy_vport_lag_out_bits { 8957 u8 status[0x8]; 8958 u8 reserved_at_8[0x18]; 8959 8960 u8 syndrome[0x20]; 8961 8962 u8 reserved_at_40[0x40]; 8963 }; 8964 8965 struct mlx5_ifc_destroy_vport_lag_in_bits { 8966 u8 opcode[0x10]; 8967 u8 reserved_at_10[0x10]; 8968 8969 u8 reserved_at_20[0x10]; 8970 u8 op_mod[0x10]; 8971 8972 u8 reserved_at_40[0x40]; 8973 }; 8974 8975 struct mlx5_ifc_alloc_memic_in_bits { 8976 u8 opcode[0x10]; 8977 u8 reserved_at_10[0x10]; 8978 8979 u8 reserved_at_20[0x10]; 8980 u8 op_mod[0x10]; 8981 8982 u8 reserved_at_30[0x20]; 8983 8984 u8 reserved_at_40[0x18]; 8985 u8 log_memic_addr_alignment[0x8]; 8986 8987 u8 range_start_addr[0x40]; 8988 8989 u8 range_size[0x20]; 8990 8991 u8 memic_size[0x20]; 8992 }; 8993 8994 struct mlx5_ifc_alloc_memic_out_bits { 8995 u8 status[0x8]; 8996 u8 reserved_at_8[0x18]; 8997 8998 u8 syndrome[0x20]; 8999 9000 u8 memic_start_addr[0x40]; 9001 }; 9002 9003 struct mlx5_ifc_dealloc_memic_in_bits { 9004 u8 opcode[0x10]; 9005 u8 reserved_at_10[0x10]; 9006 9007 u8 reserved_at_20[0x10]; 9008 u8 op_mod[0x10]; 9009 9010 u8 reserved_at_40[0x40]; 9011 9012 u8 memic_start_addr[0x40]; 9013 9014 u8 memic_size[0x20]; 9015 9016 u8 reserved_at_e0[0x20]; 9017 }; 9018 9019 struct mlx5_ifc_dealloc_memic_out_bits { 9020 u8 status[0x8]; 9021 u8 reserved_at_8[0x18]; 9022 9023 u8 syndrome[0x20]; 9024 9025 u8 reserved_at_40[0x40]; 9026 }; 9027 9028 #endif /* MLX5_IFC_H */ 9029