1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 #ifndef MLX5_IFC_H 33 #define MLX5_IFC_H 34 35 #include "mlx5_ifc_fpga.h" 36 37 enum { 38 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0, 39 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1, 40 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2, 41 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3, 42 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13, 43 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14, 44 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c, 45 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d, 46 MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4, 47 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5, 48 MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED = 0x7, 49 MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT = 0xc, 50 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10, 51 MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR = 0x11, 52 MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR = 0x12, 53 MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR = 0x8, 54 MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE = 0x9, 55 MLX5_EVENT_TYPE_CODING_GPIO_EVENT = 0x15, 56 MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19, 57 MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a, 58 MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT = 0x1b, 59 MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT = 0x1f, 60 MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa, 61 MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb, 62 MLX5_EVENT_TYPE_CODING_FPGA_ERROR = 0x20, 63 MLX5_EVENT_TYPE_CODING_FPGA_QP_ERROR = 0x21 64 }; 65 66 enum { 67 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0, 68 MLX5_SET_HCA_CAP_OP_MOD_ETHERNET_OFFLOADS = 0x1, 69 MLX5_SET_HCA_CAP_OP_MOD_ODP = 0x2, 70 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3, 71 MLX5_SET_HCA_CAP_OP_MOD_ROCE = 0x4, 72 MLX5_SET_HCA_CAP_OP_MOD_IPSEC = 0x15, 73 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE2 = 0x20, 74 MLX5_SET_HCA_CAP_OP_MOD_PORT_SELECTION = 0x25, 75 }; 76 77 enum { 78 MLX5_SHARED_RESOURCE_UID = 0xffff, 79 }; 80 81 enum { 82 MLX5_OBJ_TYPE_SW_ICM = 0x0008, 83 MLX5_OBJ_TYPE_GENEVE_TLV_OPT = 0x000b, 84 MLX5_OBJ_TYPE_VIRTIO_NET_Q = 0x000d, 85 MLX5_OBJ_TYPE_VIRTIO_Q_COUNTERS = 0x001c, 86 MLX5_OBJ_TYPE_MATCH_DEFINER = 0x0018, 87 MLX5_OBJ_TYPE_HEADER_MODIFY_ARGUMENT = 0x23, 88 MLX5_OBJ_TYPE_STC = 0x0040, 89 MLX5_OBJ_TYPE_RTC = 0x0041, 90 MLX5_OBJ_TYPE_STE = 0x0042, 91 MLX5_OBJ_TYPE_MODIFY_HDR_PATTERN = 0x0043, 92 MLX5_OBJ_TYPE_PAGE_TRACK = 0x46, 93 MLX5_OBJ_TYPE_MKEY = 0xff01, 94 MLX5_OBJ_TYPE_QP = 0xff02, 95 MLX5_OBJ_TYPE_PSV = 0xff03, 96 MLX5_OBJ_TYPE_RMP = 0xff04, 97 MLX5_OBJ_TYPE_XRC_SRQ = 0xff05, 98 MLX5_OBJ_TYPE_RQ = 0xff06, 99 MLX5_OBJ_TYPE_SQ = 0xff07, 100 MLX5_OBJ_TYPE_TIR = 0xff08, 101 MLX5_OBJ_TYPE_TIS = 0xff09, 102 MLX5_OBJ_TYPE_DCT = 0xff0a, 103 MLX5_OBJ_TYPE_XRQ = 0xff0b, 104 MLX5_OBJ_TYPE_RQT = 0xff0e, 105 MLX5_OBJ_TYPE_FLOW_COUNTER = 0xff0f, 106 MLX5_OBJ_TYPE_CQ = 0xff10, 107 MLX5_OBJ_TYPE_FT_ALIAS = 0xff15, 108 }; 109 110 enum { 111 MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM = (1ULL << MLX5_OBJ_TYPE_SW_ICM), 112 MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT = (1ULL << 11), 113 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q = (1ULL << 13), 114 MLX5_GENERAL_OBJ_TYPES_CAP_HEADER_MODIFY_ARGUMENT = 115 (1ULL << MLX5_OBJ_TYPE_HEADER_MODIFY_ARGUMENT), 116 MLX5_GENERAL_OBJ_TYPES_CAP_MACSEC_OFFLOAD = (1ULL << 39), 117 }; 118 119 enum { 120 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100, 121 MLX5_CMD_OP_QUERY_ADAPTER = 0x101, 122 MLX5_CMD_OP_INIT_HCA = 0x102, 123 MLX5_CMD_OP_TEARDOWN_HCA = 0x103, 124 MLX5_CMD_OP_ENABLE_HCA = 0x104, 125 MLX5_CMD_OP_DISABLE_HCA = 0x105, 126 MLX5_CMD_OP_QUERY_PAGES = 0x107, 127 MLX5_CMD_OP_MANAGE_PAGES = 0x108, 128 MLX5_CMD_OP_SET_HCA_CAP = 0x109, 129 MLX5_CMD_OP_QUERY_ISSI = 0x10a, 130 MLX5_CMD_OP_SET_ISSI = 0x10b, 131 MLX5_CMD_OP_SET_DRIVER_VERSION = 0x10d, 132 MLX5_CMD_OP_QUERY_SF_PARTITION = 0x111, 133 MLX5_CMD_OP_ALLOC_SF = 0x113, 134 MLX5_CMD_OP_DEALLOC_SF = 0x114, 135 MLX5_CMD_OP_SUSPEND_VHCA = 0x115, 136 MLX5_CMD_OP_RESUME_VHCA = 0x116, 137 MLX5_CMD_OP_QUERY_VHCA_MIGRATION_STATE = 0x117, 138 MLX5_CMD_OP_SAVE_VHCA_STATE = 0x118, 139 MLX5_CMD_OP_LOAD_VHCA_STATE = 0x119, 140 MLX5_CMD_OP_CREATE_MKEY = 0x200, 141 MLX5_CMD_OP_QUERY_MKEY = 0x201, 142 MLX5_CMD_OP_DESTROY_MKEY = 0x202, 143 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203, 144 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204, 145 MLX5_CMD_OP_ALLOC_MEMIC = 0x205, 146 MLX5_CMD_OP_DEALLOC_MEMIC = 0x206, 147 MLX5_CMD_OP_MODIFY_MEMIC = 0x207, 148 MLX5_CMD_OP_CREATE_EQ = 0x301, 149 MLX5_CMD_OP_DESTROY_EQ = 0x302, 150 MLX5_CMD_OP_QUERY_EQ = 0x303, 151 MLX5_CMD_OP_GEN_EQE = 0x304, 152 MLX5_CMD_OP_CREATE_CQ = 0x400, 153 MLX5_CMD_OP_DESTROY_CQ = 0x401, 154 MLX5_CMD_OP_QUERY_CQ = 0x402, 155 MLX5_CMD_OP_MODIFY_CQ = 0x403, 156 MLX5_CMD_OP_CREATE_QP = 0x500, 157 MLX5_CMD_OP_DESTROY_QP = 0x501, 158 MLX5_CMD_OP_RST2INIT_QP = 0x502, 159 MLX5_CMD_OP_INIT2RTR_QP = 0x503, 160 MLX5_CMD_OP_RTR2RTS_QP = 0x504, 161 MLX5_CMD_OP_RTS2RTS_QP = 0x505, 162 MLX5_CMD_OP_SQERR2RTS_QP = 0x506, 163 MLX5_CMD_OP_2ERR_QP = 0x507, 164 MLX5_CMD_OP_2RST_QP = 0x50a, 165 MLX5_CMD_OP_QUERY_QP = 0x50b, 166 MLX5_CMD_OP_SQD_RTS_QP = 0x50c, 167 MLX5_CMD_OP_INIT2INIT_QP = 0x50e, 168 MLX5_CMD_OP_CREATE_PSV = 0x600, 169 MLX5_CMD_OP_DESTROY_PSV = 0x601, 170 MLX5_CMD_OP_CREATE_SRQ = 0x700, 171 MLX5_CMD_OP_DESTROY_SRQ = 0x701, 172 MLX5_CMD_OP_QUERY_SRQ = 0x702, 173 MLX5_CMD_OP_ARM_RQ = 0x703, 174 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705, 175 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706, 176 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707, 177 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708, 178 MLX5_CMD_OP_CREATE_DCT = 0x710, 179 MLX5_CMD_OP_DESTROY_DCT = 0x711, 180 MLX5_CMD_OP_DRAIN_DCT = 0x712, 181 MLX5_CMD_OP_QUERY_DCT = 0x713, 182 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714, 183 MLX5_CMD_OP_CREATE_XRQ = 0x717, 184 MLX5_CMD_OP_DESTROY_XRQ = 0x718, 185 MLX5_CMD_OP_QUERY_XRQ = 0x719, 186 MLX5_CMD_OP_ARM_XRQ = 0x71a, 187 MLX5_CMD_OP_QUERY_XRQ_DC_PARAMS_ENTRY = 0x725, 188 MLX5_CMD_OP_SET_XRQ_DC_PARAMS_ENTRY = 0x726, 189 MLX5_CMD_OP_QUERY_XRQ_ERROR_PARAMS = 0x727, 190 MLX5_CMD_OP_RELEASE_XRQ_ERROR = 0x729, 191 MLX5_CMD_OP_MODIFY_XRQ = 0x72a, 192 MLX5_CMD_OP_QUERY_ESW_FUNCTIONS = 0x740, 193 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750, 194 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751, 195 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752, 196 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753, 197 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754, 198 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755, 199 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760, 200 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761, 201 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762, 202 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763, 203 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764, 204 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765, 205 MLX5_CMD_OP_QUERY_VNIC_ENV = 0x76f, 206 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770, 207 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771, 208 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772, 209 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773, 210 MLX5_CMD_OP_SET_MONITOR_COUNTER = 0x774, 211 MLX5_CMD_OP_ARM_MONITOR_COUNTER = 0x775, 212 MLX5_CMD_OP_SET_PP_RATE_LIMIT = 0x780, 213 MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781, 214 MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT = 0x782, 215 MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT = 0x783, 216 MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT = 0x784, 217 MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT = 0x785, 218 MLX5_CMD_OP_CREATE_QOS_PARA_VPORT = 0x786, 219 MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT = 0x787, 220 MLX5_CMD_OP_ALLOC_PD = 0x800, 221 MLX5_CMD_OP_DEALLOC_PD = 0x801, 222 MLX5_CMD_OP_ALLOC_UAR = 0x802, 223 MLX5_CMD_OP_DEALLOC_UAR = 0x803, 224 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804, 225 MLX5_CMD_OP_ACCESS_REG = 0x805, 226 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806, 227 MLX5_CMD_OP_DETACH_FROM_MCG = 0x807, 228 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a, 229 MLX5_CMD_OP_MAD_IFC = 0x50d, 230 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b, 231 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c, 232 MLX5_CMD_OP_NOP = 0x80d, 233 MLX5_CMD_OP_ALLOC_XRCD = 0x80e, 234 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f, 235 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816, 236 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817, 237 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822, 238 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823, 239 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824, 240 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825, 241 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826, 242 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827, 243 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828, 244 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829, 245 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a, 246 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b, 247 MLX5_CMD_OP_SET_WOL_ROL = 0x830, 248 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831, 249 MLX5_CMD_OP_CREATE_LAG = 0x840, 250 MLX5_CMD_OP_MODIFY_LAG = 0x841, 251 MLX5_CMD_OP_QUERY_LAG = 0x842, 252 MLX5_CMD_OP_DESTROY_LAG = 0x843, 253 MLX5_CMD_OP_CREATE_VPORT_LAG = 0x844, 254 MLX5_CMD_OP_DESTROY_VPORT_LAG = 0x845, 255 MLX5_CMD_OP_CREATE_TIR = 0x900, 256 MLX5_CMD_OP_MODIFY_TIR = 0x901, 257 MLX5_CMD_OP_DESTROY_TIR = 0x902, 258 MLX5_CMD_OP_QUERY_TIR = 0x903, 259 MLX5_CMD_OP_CREATE_SQ = 0x904, 260 MLX5_CMD_OP_MODIFY_SQ = 0x905, 261 MLX5_CMD_OP_DESTROY_SQ = 0x906, 262 MLX5_CMD_OP_QUERY_SQ = 0x907, 263 MLX5_CMD_OP_CREATE_RQ = 0x908, 264 MLX5_CMD_OP_MODIFY_RQ = 0x909, 265 MLX5_CMD_OP_SET_DELAY_DROP_PARAMS = 0x910, 266 MLX5_CMD_OP_DESTROY_RQ = 0x90a, 267 MLX5_CMD_OP_QUERY_RQ = 0x90b, 268 MLX5_CMD_OP_CREATE_RMP = 0x90c, 269 MLX5_CMD_OP_MODIFY_RMP = 0x90d, 270 MLX5_CMD_OP_DESTROY_RMP = 0x90e, 271 MLX5_CMD_OP_QUERY_RMP = 0x90f, 272 MLX5_CMD_OP_CREATE_TIS = 0x912, 273 MLX5_CMD_OP_MODIFY_TIS = 0x913, 274 MLX5_CMD_OP_DESTROY_TIS = 0x914, 275 MLX5_CMD_OP_QUERY_TIS = 0x915, 276 MLX5_CMD_OP_CREATE_RQT = 0x916, 277 MLX5_CMD_OP_MODIFY_RQT = 0x917, 278 MLX5_CMD_OP_DESTROY_RQT = 0x918, 279 MLX5_CMD_OP_QUERY_RQT = 0x919, 280 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f, 281 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930, 282 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931, 283 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932, 284 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933, 285 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934, 286 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935, 287 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936, 288 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937, 289 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938, 290 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939, 291 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a, 292 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b, 293 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c, 294 MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT = 0x93d, 295 MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT = 0x93e, 296 MLX5_CMD_OP_QUERY_PACKET_REFORMAT_CONTEXT = 0x93f, 297 MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT = 0x940, 298 MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941, 299 MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT = 0x942, 300 MLX5_CMD_OP_FPGA_CREATE_QP = 0x960, 301 MLX5_CMD_OP_FPGA_MODIFY_QP = 0x961, 302 MLX5_CMD_OP_FPGA_QUERY_QP = 0x962, 303 MLX5_CMD_OP_FPGA_DESTROY_QP = 0x963, 304 MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS = 0x964, 305 MLX5_CMD_OP_CREATE_GENERAL_OBJECT = 0xa00, 306 MLX5_CMD_OP_MODIFY_GENERAL_OBJECT = 0xa01, 307 MLX5_CMD_OP_QUERY_GENERAL_OBJECT = 0xa02, 308 MLX5_CMD_OP_DESTROY_GENERAL_OBJECT = 0xa03, 309 MLX5_CMD_OP_CREATE_UCTX = 0xa04, 310 MLX5_CMD_OP_DESTROY_UCTX = 0xa06, 311 MLX5_CMD_OP_CREATE_UMEM = 0xa08, 312 MLX5_CMD_OP_DESTROY_UMEM = 0xa0a, 313 MLX5_CMD_OP_SYNC_STEERING = 0xb00, 314 MLX5_CMD_OP_QUERY_VHCA_STATE = 0xb0d, 315 MLX5_CMD_OP_MODIFY_VHCA_STATE = 0xb0e, 316 MLX5_CMD_OP_SYNC_CRYPTO = 0xb12, 317 MLX5_CMD_OP_ALLOW_OTHER_VHCA_ACCESS = 0xb16, 318 MLX5_CMD_OP_GENERATE_WQE = 0xb17, 319 MLX5_CMD_OPCODE_QUERY_VUID = 0xb22, 320 MLX5_CMD_OP_MAX 321 }; 322 323 /* Valid range for general commands that don't work over an object */ 324 enum { 325 MLX5_CMD_OP_GENERAL_START = 0xb00, 326 MLX5_CMD_OP_GENERAL_END = 0xd00, 327 }; 328 329 enum { 330 MLX5_FT_NIC_RX_2_NIC_RX_RDMA = BIT(0), 331 MLX5_FT_NIC_TX_RDMA_2_NIC_TX = BIT(1), 332 }; 333 334 enum { 335 MLX5_CMD_OP_MOD_UPDATE_HEADER_MODIFY_ARGUMENT = 0x1, 336 }; 337 338 struct mlx5_ifc_flow_table_fields_supported_bits { 339 u8 outer_dmac[0x1]; 340 u8 outer_smac[0x1]; 341 u8 outer_ether_type[0x1]; 342 u8 outer_ip_version[0x1]; 343 u8 outer_first_prio[0x1]; 344 u8 outer_first_cfi[0x1]; 345 u8 outer_first_vid[0x1]; 346 u8 outer_ipv4_ttl[0x1]; 347 u8 outer_second_prio[0x1]; 348 u8 outer_second_cfi[0x1]; 349 u8 outer_second_vid[0x1]; 350 u8 reserved_at_b[0x1]; 351 u8 outer_sip[0x1]; 352 u8 outer_dip[0x1]; 353 u8 outer_frag[0x1]; 354 u8 outer_ip_protocol[0x1]; 355 u8 outer_ip_ecn[0x1]; 356 u8 outer_ip_dscp[0x1]; 357 u8 outer_udp_sport[0x1]; 358 u8 outer_udp_dport[0x1]; 359 u8 outer_tcp_sport[0x1]; 360 u8 outer_tcp_dport[0x1]; 361 u8 outer_tcp_flags[0x1]; 362 u8 outer_gre_protocol[0x1]; 363 u8 outer_gre_key[0x1]; 364 u8 outer_vxlan_vni[0x1]; 365 u8 outer_geneve_vni[0x1]; 366 u8 outer_geneve_oam[0x1]; 367 u8 outer_geneve_protocol_type[0x1]; 368 u8 outer_geneve_opt_len[0x1]; 369 u8 source_vhca_port[0x1]; 370 u8 source_eswitch_port[0x1]; 371 372 u8 inner_dmac[0x1]; 373 u8 inner_smac[0x1]; 374 u8 inner_ether_type[0x1]; 375 u8 inner_ip_version[0x1]; 376 u8 inner_first_prio[0x1]; 377 u8 inner_first_cfi[0x1]; 378 u8 inner_first_vid[0x1]; 379 u8 reserved_at_27[0x1]; 380 u8 inner_second_prio[0x1]; 381 u8 inner_second_cfi[0x1]; 382 u8 inner_second_vid[0x1]; 383 u8 reserved_at_2b[0x1]; 384 u8 inner_sip[0x1]; 385 u8 inner_dip[0x1]; 386 u8 inner_frag[0x1]; 387 u8 inner_ip_protocol[0x1]; 388 u8 inner_ip_ecn[0x1]; 389 u8 inner_ip_dscp[0x1]; 390 u8 inner_udp_sport[0x1]; 391 u8 inner_udp_dport[0x1]; 392 u8 inner_tcp_sport[0x1]; 393 u8 inner_tcp_dport[0x1]; 394 u8 inner_tcp_flags[0x1]; 395 u8 reserved_at_37[0x9]; 396 397 u8 geneve_tlv_option_0_data[0x1]; 398 u8 geneve_tlv_option_0_exist[0x1]; 399 u8 reserved_at_42[0x3]; 400 u8 outer_first_mpls_over_udp[0x4]; 401 u8 outer_first_mpls_over_gre[0x4]; 402 u8 inner_first_mpls[0x4]; 403 u8 outer_first_mpls[0x4]; 404 u8 reserved_at_55[0x2]; 405 u8 outer_esp_spi[0x1]; 406 u8 reserved_at_58[0x2]; 407 u8 bth_dst_qp[0x1]; 408 u8 reserved_at_5b[0x5]; 409 410 u8 reserved_at_60[0x18]; 411 u8 metadata_reg_c_7[0x1]; 412 u8 metadata_reg_c_6[0x1]; 413 u8 metadata_reg_c_5[0x1]; 414 u8 metadata_reg_c_4[0x1]; 415 u8 metadata_reg_c_3[0x1]; 416 u8 metadata_reg_c_2[0x1]; 417 u8 metadata_reg_c_1[0x1]; 418 u8 metadata_reg_c_0[0x1]; 419 }; 420 421 /* Table 2170 - Flow Table Fields Supported 2 Format */ 422 struct mlx5_ifc_flow_table_fields_supported_2_bits { 423 u8 reserved_at_0[0x2]; 424 u8 inner_l4_type[0x1]; 425 u8 outer_l4_type[0x1]; 426 u8 reserved_at_4[0xa]; 427 u8 bth_opcode[0x1]; 428 u8 reserved_at_f[0x1]; 429 u8 tunnel_header_0_1[0x1]; 430 u8 reserved_at_11[0xf]; 431 432 u8 reserved_at_20[0x60]; 433 }; 434 435 struct mlx5_ifc_flow_table_prop_layout_bits { 436 u8 ft_support[0x1]; 437 u8 reserved_at_1[0x1]; 438 u8 flow_counter[0x1]; 439 u8 flow_modify_en[0x1]; 440 u8 modify_root[0x1]; 441 u8 identified_miss_table_mode[0x1]; 442 u8 flow_table_modify[0x1]; 443 u8 reformat[0x1]; 444 u8 decap[0x1]; 445 u8 reset_root_to_default[0x1]; 446 u8 pop_vlan[0x1]; 447 u8 push_vlan[0x1]; 448 u8 reserved_at_c[0x1]; 449 u8 pop_vlan_2[0x1]; 450 u8 push_vlan_2[0x1]; 451 u8 reformat_and_vlan_action[0x1]; 452 u8 reserved_at_10[0x1]; 453 u8 sw_owner[0x1]; 454 u8 reformat_l3_tunnel_to_l2[0x1]; 455 u8 reformat_l2_to_l3_tunnel[0x1]; 456 u8 reformat_and_modify_action[0x1]; 457 u8 ignore_flow_level[0x1]; 458 u8 reserved_at_16[0x1]; 459 u8 table_miss_action_domain[0x1]; 460 u8 termination_table[0x1]; 461 u8 reformat_and_fwd_to_table[0x1]; 462 u8 reserved_at_1a[0x2]; 463 u8 ipsec_encrypt[0x1]; 464 u8 ipsec_decrypt[0x1]; 465 u8 sw_owner_v2[0x1]; 466 u8 reserved_at_1f[0x1]; 467 468 u8 termination_table_raw_traffic[0x1]; 469 u8 reserved_at_21[0x1]; 470 u8 log_max_ft_size[0x6]; 471 u8 log_max_modify_header_context[0x8]; 472 u8 max_modify_header_actions[0x8]; 473 u8 max_ft_level[0x8]; 474 475 u8 reformat_add_esp_trasport[0x1]; 476 u8 reformat_l2_to_l3_esp_tunnel[0x1]; 477 u8 reformat_add_esp_transport_over_udp[0x1]; 478 u8 reformat_del_esp_trasport[0x1]; 479 u8 reformat_l3_esp_tunnel_to_l2[0x1]; 480 u8 reformat_del_esp_transport_over_udp[0x1]; 481 u8 execute_aso[0x1]; 482 u8 reserved_at_47[0x19]; 483 484 u8 reserved_at_60[0x2]; 485 u8 reformat_insert[0x1]; 486 u8 reformat_remove[0x1]; 487 u8 macsec_encrypt[0x1]; 488 u8 macsec_decrypt[0x1]; 489 u8 reserved_at_66[0x2]; 490 u8 reformat_add_macsec[0x1]; 491 u8 reformat_remove_macsec[0x1]; 492 u8 reparse[0x1]; 493 u8 reserved_at_6b[0x1]; 494 u8 cross_vhca_object[0x1]; 495 u8 reformat_l2_to_l3_audp_tunnel[0x1]; 496 u8 reformat_l3_audp_tunnel_to_l2[0x1]; 497 u8 ignore_flow_level_rtc_valid[0x1]; 498 u8 reserved_at_70[0x8]; 499 u8 log_max_ft_num[0x8]; 500 501 u8 reserved_at_80[0x10]; 502 u8 log_max_flow_counter[0x8]; 503 u8 log_max_destination[0x8]; 504 505 u8 reserved_at_a0[0x18]; 506 u8 log_max_flow[0x8]; 507 508 u8 reserved_at_c0[0x40]; 509 510 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support; 511 512 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support; 513 }; 514 515 struct mlx5_ifc_odp_per_transport_service_cap_bits { 516 u8 send[0x1]; 517 u8 receive[0x1]; 518 u8 write[0x1]; 519 u8 read[0x1]; 520 u8 atomic[0x1]; 521 u8 srq_receive[0x1]; 522 u8 reserved_at_6[0x1a]; 523 }; 524 525 struct mlx5_ifc_ipv4_layout_bits { 526 u8 reserved_at_0[0x60]; 527 528 u8 ipv4[0x20]; 529 }; 530 531 struct mlx5_ifc_ipv6_layout_bits { 532 u8 ipv6[16][0x8]; 533 }; 534 535 struct mlx5_ifc_ipv6_simple_layout_bits { 536 u8 ipv6_127_96[0x20]; 537 u8 ipv6_95_64[0x20]; 538 u8 ipv6_63_32[0x20]; 539 u8 ipv6_31_0[0x20]; 540 }; 541 542 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits { 543 struct mlx5_ifc_ipv6_simple_layout_bits ipv6_simple_layout; 544 struct mlx5_ifc_ipv6_layout_bits ipv6_layout; 545 struct mlx5_ifc_ipv4_layout_bits ipv4_layout; 546 u8 reserved_at_0[0x80]; 547 }; 548 549 enum { 550 MLX5_PACKET_L4_TYPE_NONE, 551 MLX5_PACKET_L4_TYPE_TCP, 552 MLX5_PACKET_L4_TYPE_UDP, 553 }; 554 555 struct mlx5_ifc_fte_match_set_lyr_2_4_bits { 556 u8 smac_47_16[0x20]; 557 558 u8 smac_15_0[0x10]; 559 u8 ethertype[0x10]; 560 561 u8 dmac_47_16[0x20]; 562 563 u8 dmac_15_0[0x10]; 564 u8 first_prio[0x3]; 565 u8 first_cfi[0x1]; 566 u8 first_vid[0xc]; 567 568 u8 ip_protocol[0x8]; 569 u8 ip_dscp[0x6]; 570 u8 ip_ecn[0x2]; 571 u8 cvlan_tag[0x1]; 572 u8 svlan_tag[0x1]; 573 u8 frag[0x1]; 574 u8 ip_version[0x4]; 575 u8 tcp_flags[0x9]; 576 577 u8 tcp_sport[0x10]; 578 u8 tcp_dport[0x10]; 579 580 u8 l4_type[0x2]; 581 u8 reserved_at_c2[0xe]; 582 u8 ipv4_ihl[0x4]; 583 u8 reserved_at_c4[0x4]; 584 585 u8 ttl_hoplimit[0x8]; 586 587 u8 udp_sport[0x10]; 588 u8 udp_dport[0x10]; 589 590 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6; 591 592 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6; 593 }; 594 595 struct mlx5_ifc_nvgre_key_bits { 596 u8 hi[0x18]; 597 u8 lo[0x8]; 598 }; 599 600 union mlx5_ifc_gre_key_bits { 601 struct mlx5_ifc_nvgre_key_bits nvgre; 602 u8 key[0x20]; 603 }; 604 605 struct mlx5_ifc_fte_match_set_misc_bits { 606 u8 gre_c_present[0x1]; 607 u8 reserved_at_1[0x1]; 608 u8 gre_k_present[0x1]; 609 u8 gre_s_present[0x1]; 610 u8 source_vhca_port[0x4]; 611 u8 source_sqn[0x18]; 612 613 u8 source_eswitch_owner_vhca_id[0x10]; 614 u8 source_port[0x10]; 615 616 u8 outer_second_prio[0x3]; 617 u8 outer_second_cfi[0x1]; 618 u8 outer_second_vid[0xc]; 619 u8 inner_second_prio[0x3]; 620 u8 inner_second_cfi[0x1]; 621 u8 inner_second_vid[0xc]; 622 623 u8 outer_second_cvlan_tag[0x1]; 624 u8 inner_second_cvlan_tag[0x1]; 625 u8 outer_second_svlan_tag[0x1]; 626 u8 inner_second_svlan_tag[0x1]; 627 u8 reserved_at_64[0xc]; 628 u8 gre_protocol[0x10]; 629 630 union mlx5_ifc_gre_key_bits gre_key; 631 632 u8 vxlan_vni[0x18]; 633 u8 bth_opcode[0x8]; 634 635 u8 geneve_vni[0x18]; 636 u8 reserved_at_d8[0x6]; 637 u8 geneve_tlv_option_0_exist[0x1]; 638 u8 geneve_oam[0x1]; 639 640 u8 reserved_at_e0[0xc]; 641 u8 outer_ipv6_flow_label[0x14]; 642 643 u8 reserved_at_100[0xc]; 644 u8 inner_ipv6_flow_label[0x14]; 645 646 u8 reserved_at_120[0xa]; 647 u8 geneve_opt_len[0x6]; 648 u8 geneve_protocol_type[0x10]; 649 650 u8 reserved_at_140[0x8]; 651 u8 bth_dst_qp[0x18]; 652 u8 inner_esp_spi[0x20]; 653 u8 outer_esp_spi[0x20]; 654 u8 reserved_at_1a0[0x60]; 655 }; 656 657 struct mlx5_ifc_fte_match_mpls_bits { 658 u8 mpls_label[0x14]; 659 u8 mpls_exp[0x3]; 660 u8 mpls_s_bos[0x1]; 661 u8 mpls_ttl[0x8]; 662 }; 663 664 struct mlx5_ifc_fte_match_set_misc2_bits { 665 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls; 666 667 struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls; 668 669 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre; 670 671 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp; 672 673 u8 metadata_reg_c_7[0x20]; 674 675 u8 metadata_reg_c_6[0x20]; 676 677 u8 metadata_reg_c_5[0x20]; 678 679 u8 metadata_reg_c_4[0x20]; 680 681 u8 metadata_reg_c_3[0x20]; 682 683 u8 metadata_reg_c_2[0x20]; 684 685 u8 metadata_reg_c_1[0x20]; 686 687 u8 metadata_reg_c_0[0x20]; 688 689 u8 metadata_reg_a[0x20]; 690 691 u8 reserved_at_1a0[0x8]; 692 693 u8 macsec_syndrome[0x8]; 694 u8 ipsec_syndrome[0x8]; 695 u8 reserved_at_1b8[0x8]; 696 697 u8 reserved_at_1c0[0x40]; 698 }; 699 700 struct mlx5_ifc_fte_match_set_misc3_bits { 701 u8 inner_tcp_seq_num[0x20]; 702 703 u8 outer_tcp_seq_num[0x20]; 704 705 u8 inner_tcp_ack_num[0x20]; 706 707 u8 outer_tcp_ack_num[0x20]; 708 709 u8 reserved_at_80[0x8]; 710 u8 outer_vxlan_gpe_vni[0x18]; 711 712 u8 outer_vxlan_gpe_next_protocol[0x8]; 713 u8 outer_vxlan_gpe_flags[0x8]; 714 u8 reserved_at_b0[0x10]; 715 716 u8 icmp_header_data[0x20]; 717 718 u8 icmpv6_header_data[0x20]; 719 720 u8 icmp_type[0x8]; 721 u8 icmp_code[0x8]; 722 u8 icmpv6_type[0x8]; 723 u8 icmpv6_code[0x8]; 724 725 u8 geneve_tlv_option_0_data[0x20]; 726 727 u8 gtpu_teid[0x20]; 728 729 u8 gtpu_msg_type[0x8]; 730 u8 gtpu_msg_flags[0x8]; 731 u8 reserved_at_170[0x10]; 732 733 u8 gtpu_dw_2[0x20]; 734 735 u8 gtpu_first_ext_dw_0[0x20]; 736 737 u8 gtpu_dw_0[0x20]; 738 739 u8 reserved_at_1e0[0x20]; 740 }; 741 742 struct mlx5_ifc_fte_match_set_misc4_bits { 743 u8 prog_sample_field_value_0[0x20]; 744 745 u8 prog_sample_field_id_0[0x20]; 746 747 u8 prog_sample_field_value_1[0x20]; 748 749 u8 prog_sample_field_id_1[0x20]; 750 751 u8 prog_sample_field_value_2[0x20]; 752 753 u8 prog_sample_field_id_2[0x20]; 754 755 u8 prog_sample_field_value_3[0x20]; 756 757 u8 prog_sample_field_id_3[0x20]; 758 759 u8 reserved_at_100[0x100]; 760 }; 761 762 struct mlx5_ifc_fte_match_set_misc5_bits { 763 u8 macsec_tag_0[0x20]; 764 765 u8 macsec_tag_1[0x20]; 766 767 u8 macsec_tag_2[0x20]; 768 769 u8 macsec_tag_3[0x20]; 770 771 u8 tunnel_header_0[0x20]; 772 773 u8 tunnel_header_1[0x20]; 774 775 u8 tunnel_header_2[0x20]; 776 777 u8 tunnel_header_3[0x20]; 778 779 u8 reserved_at_100[0x100]; 780 }; 781 782 struct mlx5_ifc_cmd_pas_bits { 783 u8 pa_h[0x20]; 784 785 u8 pa_l[0x14]; 786 u8 reserved_at_34[0xc]; 787 }; 788 789 struct mlx5_ifc_uint64_bits { 790 u8 hi[0x20]; 791 792 u8 lo[0x20]; 793 }; 794 795 enum { 796 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0, 797 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7, 798 MLX5_ADS_STAT_RATE_10GBPS = 0x8, 799 MLX5_ADS_STAT_RATE_30GBPS = 0x9, 800 MLX5_ADS_STAT_RATE_5GBPS = 0xa, 801 MLX5_ADS_STAT_RATE_20GBPS = 0xb, 802 MLX5_ADS_STAT_RATE_40GBPS = 0xc, 803 MLX5_ADS_STAT_RATE_60GBPS = 0xd, 804 MLX5_ADS_STAT_RATE_80GBPS = 0xe, 805 MLX5_ADS_STAT_RATE_120GBPS = 0xf, 806 }; 807 808 struct mlx5_ifc_ads_bits { 809 u8 fl[0x1]; 810 u8 free_ar[0x1]; 811 u8 reserved_at_2[0xe]; 812 u8 pkey_index[0x10]; 813 814 u8 plane_index[0x8]; 815 u8 grh[0x1]; 816 u8 mlid[0x7]; 817 u8 rlid[0x10]; 818 819 u8 ack_timeout[0x5]; 820 u8 reserved_at_45[0x3]; 821 u8 src_addr_index[0x8]; 822 u8 reserved_at_50[0x4]; 823 u8 stat_rate[0x4]; 824 u8 hop_limit[0x8]; 825 826 u8 reserved_at_60[0x4]; 827 u8 tclass[0x8]; 828 u8 flow_label[0x14]; 829 830 u8 rgid_rip[16][0x8]; 831 832 u8 reserved_at_100[0x4]; 833 u8 f_dscp[0x1]; 834 u8 f_ecn[0x1]; 835 u8 reserved_at_106[0x1]; 836 u8 f_eth_prio[0x1]; 837 u8 ecn[0x2]; 838 u8 dscp[0x6]; 839 u8 udp_sport[0x10]; 840 841 u8 dei_cfi[0x1]; 842 u8 eth_prio[0x3]; 843 u8 sl[0x4]; 844 u8 vhca_port_num[0x8]; 845 u8 rmac_47_32[0x10]; 846 847 u8 rmac_31_0[0x20]; 848 }; 849 850 struct mlx5_ifc_flow_table_nic_cap_bits { 851 u8 nic_rx_multi_path_tirs[0x1]; 852 u8 nic_rx_multi_path_tirs_fts[0x1]; 853 u8 allow_sniffer_and_nic_rx_shared_tir[0x1]; 854 u8 reserved_at_3[0x4]; 855 u8 sw_owner_reformat_supported[0x1]; 856 u8 reserved_at_8[0x18]; 857 858 u8 encap_general_header[0x1]; 859 u8 reserved_at_21[0xa]; 860 u8 log_max_packet_reformat_context[0x5]; 861 u8 reserved_at_30[0x6]; 862 u8 max_encap_header_size[0xa]; 863 u8 reserved_at_40[0x1c0]; 864 865 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive; 866 867 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_rdma; 868 869 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer; 870 871 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit; 872 873 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_rdma; 874 875 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer; 876 877 u8 reserved_at_e00[0x600]; 878 879 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_receive; 880 881 u8 reserved_at_1480[0x80]; 882 883 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_receive_rdma; 884 885 u8 reserved_at_1580[0x280]; 886 887 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_transmit_rdma; 888 889 u8 reserved_at_1880[0x780]; 890 891 u8 sw_steering_nic_rx_action_drop_icm_address[0x40]; 892 893 u8 sw_steering_nic_tx_action_drop_icm_address[0x40]; 894 895 u8 sw_steering_nic_tx_action_allow_icm_address[0x40]; 896 897 u8 reserved_at_20c0[0x5f40]; 898 }; 899 900 struct mlx5_ifc_port_selection_cap_bits { 901 u8 reserved_at_0[0x10]; 902 u8 port_select_flow_table[0x1]; 903 u8 reserved_at_11[0x1]; 904 u8 port_select_flow_table_bypass[0x1]; 905 u8 reserved_at_13[0xd]; 906 907 u8 reserved_at_20[0x1e0]; 908 909 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_port_selection; 910 911 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_port_selection; 912 913 u8 reserved_at_480[0x7b80]; 914 }; 915 916 enum { 917 MLX5_FDB_TO_VPORT_REG_C_0 = 0x01, 918 MLX5_FDB_TO_VPORT_REG_C_1 = 0x02, 919 MLX5_FDB_TO_VPORT_REG_C_2 = 0x04, 920 MLX5_FDB_TO_VPORT_REG_C_3 = 0x08, 921 MLX5_FDB_TO_VPORT_REG_C_4 = 0x10, 922 MLX5_FDB_TO_VPORT_REG_C_5 = 0x20, 923 MLX5_FDB_TO_VPORT_REG_C_6 = 0x40, 924 MLX5_FDB_TO_VPORT_REG_C_7 = 0x80, 925 }; 926 927 struct mlx5_ifc_flow_table_eswitch_cap_bits { 928 u8 fdb_to_vport_reg_c_id[0x8]; 929 u8 reserved_at_8[0x5]; 930 u8 fdb_uplink_hairpin[0x1]; 931 u8 fdb_multi_path_any_table_limit_regc[0x1]; 932 u8 reserved_at_f[0x1]; 933 u8 fdb_dynamic_tunnel[0x1]; 934 u8 reserved_at_11[0x1]; 935 u8 fdb_multi_path_any_table[0x1]; 936 u8 reserved_at_13[0x2]; 937 u8 fdb_modify_header_fwd_to_table[0x1]; 938 u8 fdb_ipv4_ttl_modify[0x1]; 939 u8 flow_source[0x1]; 940 u8 reserved_at_18[0x2]; 941 u8 multi_fdb_encap[0x1]; 942 u8 egress_acl_forward_to_vport[0x1]; 943 u8 fdb_multi_path_to_table[0x1]; 944 u8 reserved_at_1d[0x3]; 945 946 u8 reserved_at_20[0x1e0]; 947 948 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb; 949 950 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress; 951 952 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress; 953 954 u8 reserved_at_800[0xC00]; 955 956 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_esw_fdb; 957 958 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_bitmask_support_2_esw_fdb; 959 960 u8 reserved_at_1500[0x300]; 961 962 u8 sw_steering_fdb_action_drop_icm_address_rx[0x40]; 963 964 u8 sw_steering_fdb_action_drop_icm_address_tx[0x40]; 965 966 u8 sw_steering_uplink_icm_address_rx[0x40]; 967 968 u8 sw_steering_uplink_icm_address_tx[0x40]; 969 970 u8 reserved_at_1900[0x6700]; 971 }; 972 973 struct mlx5_ifc_wqe_based_flow_table_cap_bits { 974 u8 reserved_at_0[0x3]; 975 u8 log_max_num_ste[0x5]; 976 u8 reserved_at_8[0x3]; 977 u8 log_max_num_stc[0x5]; 978 u8 reserved_at_10[0x3]; 979 u8 log_max_num_rtc[0x5]; 980 u8 reserved_at_18[0x3]; 981 u8 log_max_num_header_modify_pattern[0x5]; 982 983 u8 rtc_hash_split_table[0x1]; 984 u8 rtc_linear_lookup_table[0x1]; 985 u8 reserved_at_22[0x1]; 986 u8 stc_alloc_log_granularity[0x5]; 987 u8 reserved_at_28[0x3]; 988 u8 stc_alloc_log_max[0x5]; 989 u8 reserved_at_30[0x3]; 990 u8 ste_alloc_log_granularity[0x5]; 991 u8 reserved_at_38[0x3]; 992 u8 ste_alloc_log_max[0x5]; 993 994 u8 reserved_at_40[0xb]; 995 u8 rtc_reparse_mode[0x5]; 996 u8 reserved_at_50[0x3]; 997 u8 rtc_index_mode[0x5]; 998 u8 reserved_at_58[0x3]; 999 u8 rtc_log_depth_max[0x5]; 1000 1001 u8 reserved_at_60[0x10]; 1002 u8 ste_format[0x10]; 1003 1004 u8 stc_action_type[0x80]; 1005 1006 u8 header_insert_type[0x10]; 1007 u8 header_remove_type[0x10]; 1008 1009 u8 trivial_match_definer[0x20]; 1010 1011 u8 reserved_at_140[0x1b]; 1012 u8 rtc_max_num_hash_definer_gen_wqe[0x5]; 1013 1014 u8 reserved_at_160[0x18]; 1015 u8 access_index_mode[0x8]; 1016 1017 u8 reserved_at_180[0x10]; 1018 u8 ste_format_gen_wqe[0x10]; 1019 1020 u8 linear_match_definer_reg_c3[0x20]; 1021 1022 u8 fdb_jump_to_tir_stc[0x1]; 1023 u8 reserved_at_1c1[0x1f]; 1024 }; 1025 1026 struct mlx5_ifc_esw_cap_bits { 1027 u8 reserved_at_0[0x1d]; 1028 u8 merged_eswitch[0x1]; 1029 u8 reserved_at_1e[0x2]; 1030 1031 u8 reserved_at_20[0x40]; 1032 1033 u8 esw_manager_vport_number_valid[0x1]; 1034 u8 reserved_at_61[0xf]; 1035 u8 esw_manager_vport_number[0x10]; 1036 1037 u8 reserved_at_80[0x780]; 1038 }; 1039 1040 enum { 1041 MLX5_COUNTER_SOURCE_ESWITCH = 0x0, 1042 MLX5_COUNTER_FLOW_ESWITCH = 0x1, 1043 }; 1044 1045 struct mlx5_ifc_e_switch_cap_bits { 1046 u8 vport_svlan_strip[0x1]; 1047 u8 vport_cvlan_strip[0x1]; 1048 u8 vport_svlan_insert[0x1]; 1049 u8 vport_cvlan_insert_if_not_exist[0x1]; 1050 u8 vport_cvlan_insert_overwrite[0x1]; 1051 u8 reserved_at_5[0x1]; 1052 u8 vport_cvlan_insert_always[0x1]; 1053 u8 esw_shared_ingress_acl[0x1]; 1054 u8 esw_uplink_ingress_acl[0x1]; 1055 u8 root_ft_on_other_esw[0x1]; 1056 u8 reserved_at_a[0xf]; 1057 u8 esw_functions_changed[0x1]; 1058 u8 reserved_at_1a[0x1]; 1059 u8 ecpf_vport_exists[0x1]; 1060 u8 counter_eswitch_affinity[0x1]; 1061 u8 merged_eswitch[0x1]; 1062 u8 nic_vport_node_guid_modify[0x1]; 1063 u8 nic_vport_port_guid_modify[0x1]; 1064 1065 u8 vxlan_encap_decap[0x1]; 1066 u8 nvgre_encap_decap[0x1]; 1067 u8 reserved_at_22[0x1]; 1068 u8 log_max_fdb_encap_uplink[0x5]; 1069 u8 reserved_at_21[0x3]; 1070 u8 log_max_packet_reformat_context[0x5]; 1071 u8 reserved_2b[0x6]; 1072 u8 max_encap_header_size[0xa]; 1073 1074 u8 reserved_at_40[0xb]; 1075 u8 log_max_esw_sf[0x5]; 1076 u8 esw_sf_base_id[0x10]; 1077 1078 u8 reserved_at_60[0x7a0]; 1079 1080 }; 1081 1082 struct mlx5_ifc_qos_cap_bits { 1083 u8 packet_pacing[0x1]; 1084 u8 esw_scheduling[0x1]; 1085 u8 esw_bw_share[0x1]; 1086 u8 esw_rate_limit[0x1]; 1087 u8 reserved_at_4[0x1]; 1088 u8 packet_pacing_burst_bound[0x1]; 1089 u8 packet_pacing_typical_size[0x1]; 1090 u8 reserved_at_7[0x1]; 1091 u8 nic_sq_scheduling[0x1]; 1092 u8 nic_bw_share[0x1]; 1093 u8 nic_rate_limit[0x1]; 1094 u8 packet_pacing_uid[0x1]; 1095 u8 log_esw_max_sched_depth[0x4]; 1096 u8 reserved_at_10[0x10]; 1097 1098 u8 reserved_at_20[0x9]; 1099 u8 esw_cross_esw_sched[0x1]; 1100 u8 reserved_at_2a[0x1]; 1101 u8 log_max_qos_nic_queue_group[0x5]; 1102 u8 reserved_at_30[0x10]; 1103 1104 u8 packet_pacing_max_rate[0x20]; 1105 1106 u8 packet_pacing_min_rate[0x20]; 1107 1108 u8 reserved_at_80[0xb]; 1109 u8 log_esw_max_rate_limit[0x5]; 1110 u8 packet_pacing_rate_table_size[0x10]; 1111 1112 u8 esw_element_type[0x10]; 1113 u8 esw_tsar_type[0x10]; 1114 1115 u8 reserved_at_c0[0x10]; 1116 u8 max_qos_para_vport[0x10]; 1117 1118 u8 max_tsar_bw_share[0x20]; 1119 1120 u8 nic_element_type[0x10]; 1121 u8 nic_tsar_type[0x10]; 1122 1123 u8 reserved_at_120[0x3]; 1124 u8 log_meter_aso_granularity[0x5]; 1125 u8 reserved_at_128[0x3]; 1126 u8 log_meter_aso_max_alloc[0x5]; 1127 u8 reserved_at_130[0x3]; 1128 u8 log_max_num_meter_aso[0x5]; 1129 u8 reserved_at_138[0x8]; 1130 1131 u8 reserved_at_140[0x6c0]; 1132 }; 1133 1134 struct mlx5_ifc_debug_cap_bits { 1135 u8 core_dump_general[0x1]; 1136 u8 core_dump_qp[0x1]; 1137 u8 reserved_at_2[0x7]; 1138 u8 resource_dump[0x1]; 1139 u8 reserved_at_a[0x16]; 1140 1141 u8 reserved_at_20[0x2]; 1142 u8 stall_detect[0x1]; 1143 u8 reserved_at_23[0x1d]; 1144 1145 u8 reserved_at_40[0x7c0]; 1146 }; 1147 1148 struct mlx5_ifc_per_protocol_networking_offload_caps_bits { 1149 u8 csum_cap[0x1]; 1150 u8 vlan_cap[0x1]; 1151 u8 lro_cap[0x1]; 1152 u8 lro_psh_flag[0x1]; 1153 u8 lro_time_stamp[0x1]; 1154 u8 reserved_at_5[0x2]; 1155 u8 wqe_vlan_insert[0x1]; 1156 u8 self_lb_en_modifiable[0x1]; 1157 u8 reserved_at_9[0x2]; 1158 u8 max_lso_cap[0x5]; 1159 u8 multi_pkt_send_wqe[0x2]; 1160 u8 wqe_inline_mode[0x2]; 1161 u8 rss_ind_tbl_cap[0x4]; 1162 u8 reg_umr_sq[0x1]; 1163 u8 scatter_fcs[0x1]; 1164 u8 enhanced_multi_pkt_send_wqe[0x1]; 1165 u8 tunnel_lso_const_out_ip_id[0x1]; 1166 u8 tunnel_lro_gre[0x1]; 1167 u8 tunnel_lro_vxlan[0x1]; 1168 u8 tunnel_stateless_gre[0x1]; 1169 u8 tunnel_stateless_vxlan[0x1]; 1170 1171 u8 swp[0x1]; 1172 u8 swp_csum[0x1]; 1173 u8 swp_lso[0x1]; 1174 u8 cqe_checksum_full[0x1]; 1175 u8 tunnel_stateless_geneve_tx[0x1]; 1176 u8 tunnel_stateless_mpls_over_udp[0x1]; 1177 u8 tunnel_stateless_mpls_over_gre[0x1]; 1178 u8 tunnel_stateless_vxlan_gpe[0x1]; 1179 u8 tunnel_stateless_ipv4_over_vxlan[0x1]; 1180 u8 tunnel_stateless_ip_over_ip[0x1]; 1181 u8 insert_trailer[0x1]; 1182 u8 reserved_at_2b[0x1]; 1183 u8 tunnel_stateless_ip_over_ip_rx[0x1]; 1184 u8 tunnel_stateless_ip_over_ip_tx[0x1]; 1185 u8 reserved_at_2e[0x2]; 1186 u8 max_vxlan_udp_ports[0x8]; 1187 u8 swp_csum_l4_partial[0x1]; 1188 u8 reserved_at_39[0x5]; 1189 u8 max_geneve_opt_len[0x1]; 1190 u8 tunnel_stateless_geneve_rx[0x1]; 1191 1192 u8 reserved_at_40[0x10]; 1193 u8 lro_min_mss_size[0x10]; 1194 1195 u8 reserved_at_60[0x120]; 1196 1197 u8 lro_timer_supported_periods[4][0x20]; 1198 1199 u8 reserved_at_200[0x600]; 1200 }; 1201 1202 enum { 1203 MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING = 0x0, 1204 MLX5_TIMESTAMP_FORMAT_CAP_REAL_TIME = 0x1, 1205 MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING_AND_REAL_TIME = 0x2, 1206 }; 1207 1208 struct mlx5_ifc_roce_cap_bits { 1209 u8 roce_apm[0x1]; 1210 u8 reserved_at_1[0x3]; 1211 u8 sw_r_roce_src_udp_port[0x1]; 1212 u8 fl_rc_qp_when_roce_disabled[0x1]; 1213 u8 fl_rc_qp_when_roce_enabled[0x1]; 1214 u8 roce_cc_general[0x1]; 1215 u8 qp_ooo_transmit_default[0x1]; 1216 u8 reserved_at_9[0x15]; 1217 u8 qp_ts_format[0x2]; 1218 1219 u8 reserved_at_20[0x60]; 1220 1221 u8 reserved_at_80[0xc]; 1222 u8 l3_type[0x4]; 1223 u8 reserved_at_90[0x8]; 1224 u8 roce_version[0x8]; 1225 1226 u8 reserved_at_a0[0x10]; 1227 u8 r_roce_dest_udp_port[0x10]; 1228 1229 u8 r_roce_max_src_udp_port[0x10]; 1230 u8 r_roce_min_src_udp_port[0x10]; 1231 1232 u8 reserved_at_e0[0x10]; 1233 u8 roce_address_table_size[0x10]; 1234 1235 u8 reserved_at_100[0x700]; 1236 }; 1237 1238 struct mlx5_ifc_sync_steering_in_bits { 1239 u8 opcode[0x10]; 1240 u8 uid[0x10]; 1241 1242 u8 reserved_at_20[0x10]; 1243 u8 op_mod[0x10]; 1244 1245 u8 reserved_at_40[0xc0]; 1246 }; 1247 1248 struct mlx5_ifc_sync_steering_out_bits { 1249 u8 status[0x8]; 1250 u8 reserved_at_8[0x18]; 1251 1252 u8 syndrome[0x20]; 1253 1254 u8 reserved_at_40[0x40]; 1255 }; 1256 1257 struct mlx5_ifc_sync_crypto_in_bits { 1258 u8 opcode[0x10]; 1259 u8 uid[0x10]; 1260 1261 u8 reserved_at_20[0x10]; 1262 u8 op_mod[0x10]; 1263 1264 u8 reserved_at_40[0x20]; 1265 1266 u8 reserved_at_60[0x10]; 1267 u8 crypto_type[0x10]; 1268 1269 u8 reserved_at_80[0x80]; 1270 }; 1271 1272 struct mlx5_ifc_sync_crypto_out_bits { 1273 u8 status[0x8]; 1274 u8 reserved_at_8[0x18]; 1275 1276 u8 syndrome[0x20]; 1277 1278 u8 reserved_at_40[0x40]; 1279 }; 1280 1281 struct mlx5_ifc_device_mem_cap_bits { 1282 u8 memic[0x1]; 1283 u8 reserved_at_1[0x1f]; 1284 1285 u8 reserved_at_20[0xb]; 1286 u8 log_min_memic_alloc_size[0x5]; 1287 u8 reserved_at_30[0x8]; 1288 u8 log_max_memic_addr_alignment[0x8]; 1289 1290 u8 memic_bar_start_addr[0x40]; 1291 1292 u8 memic_bar_size[0x20]; 1293 1294 u8 max_memic_size[0x20]; 1295 1296 u8 steering_sw_icm_start_address[0x40]; 1297 1298 u8 reserved_at_100[0x8]; 1299 u8 log_header_modify_sw_icm_size[0x8]; 1300 u8 reserved_at_110[0x2]; 1301 u8 log_sw_icm_alloc_granularity[0x6]; 1302 u8 log_steering_sw_icm_size[0x8]; 1303 1304 u8 log_indirect_encap_sw_icm_size[0x8]; 1305 u8 reserved_at_128[0x10]; 1306 u8 log_header_modify_pattern_sw_icm_size[0x8]; 1307 1308 u8 header_modify_sw_icm_start_address[0x40]; 1309 1310 u8 reserved_at_180[0x40]; 1311 1312 u8 header_modify_pattern_sw_icm_start_address[0x40]; 1313 1314 u8 memic_operations[0x20]; 1315 1316 u8 reserved_at_220[0x20]; 1317 1318 u8 indirect_encap_sw_icm_start_address[0x40]; 1319 1320 u8 reserved_at_280[0x580]; 1321 }; 1322 1323 struct mlx5_ifc_device_event_cap_bits { 1324 u8 user_affiliated_events[4][0x40]; 1325 1326 u8 user_unaffiliated_events[4][0x40]; 1327 }; 1328 1329 struct mlx5_ifc_virtio_emulation_cap_bits { 1330 u8 desc_tunnel_offload_type[0x1]; 1331 u8 eth_frame_offload_type[0x1]; 1332 u8 virtio_version_1_0[0x1]; 1333 u8 device_features_bits_mask[0xd]; 1334 u8 event_mode[0x8]; 1335 u8 virtio_queue_type[0x8]; 1336 1337 u8 max_tunnel_desc[0x10]; 1338 u8 reserved_at_30[0x3]; 1339 u8 log_doorbell_stride[0x5]; 1340 u8 reserved_at_38[0x3]; 1341 u8 log_doorbell_bar_size[0x5]; 1342 1343 u8 doorbell_bar_offset[0x40]; 1344 1345 u8 max_emulated_devices[0x8]; 1346 u8 max_num_virtio_queues[0x18]; 1347 1348 u8 reserved_at_a0[0x20]; 1349 1350 u8 reserved_at_c0[0x13]; 1351 u8 desc_group_mkey_supported[0x1]; 1352 u8 freeze_to_rdy_supported[0x1]; 1353 u8 reserved_at_d5[0xb]; 1354 1355 u8 reserved_at_e0[0x20]; 1356 1357 u8 umem_1_buffer_param_a[0x20]; 1358 1359 u8 umem_1_buffer_param_b[0x20]; 1360 1361 u8 umem_2_buffer_param_a[0x20]; 1362 1363 u8 umem_2_buffer_param_b[0x20]; 1364 1365 u8 umem_3_buffer_param_a[0x20]; 1366 1367 u8 umem_3_buffer_param_b[0x20]; 1368 1369 u8 reserved_at_1c0[0x640]; 1370 }; 1371 1372 enum { 1373 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0, 1374 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2, 1375 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4, 1376 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8, 1377 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10, 1378 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20, 1379 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40, 1380 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80, 1381 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100, 1382 }; 1383 1384 enum { 1385 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1, 1386 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2, 1387 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4, 1388 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8, 1389 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10, 1390 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20, 1391 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40, 1392 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80, 1393 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100, 1394 }; 1395 1396 struct mlx5_ifc_atomic_caps_bits { 1397 u8 reserved_at_0[0x40]; 1398 1399 u8 atomic_req_8B_endianness_mode[0x2]; 1400 u8 reserved_at_42[0x4]; 1401 u8 supported_atomic_req_8B_endianness_mode_1[0x1]; 1402 1403 u8 reserved_at_47[0x19]; 1404 1405 u8 reserved_at_60[0x20]; 1406 1407 u8 reserved_at_80[0x10]; 1408 u8 atomic_operations[0x10]; 1409 1410 u8 reserved_at_a0[0x10]; 1411 u8 atomic_size_qp[0x10]; 1412 1413 u8 reserved_at_c0[0x10]; 1414 u8 atomic_size_dc[0x10]; 1415 1416 u8 reserved_at_e0[0x720]; 1417 }; 1418 1419 struct mlx5_ifc_odp_scheme_cap_bits { 1420 u8 reserved_at_0[0x40]; 1421 1422 u8 sig[0x1]; 1423 u8 reserved_at_41[0x4]; 1424 u8 page_prefetch[0x1]; 1425 u8 reserved_at_46[0x1a]; 1426 1427 u8 reserved_at_60[0x20]; 1428 1429 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps; 1430 1431 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps; 1432 1433 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps; 1434 1435 struct mlx5_ifc_odp_per_transport_service_cap_bits xrc_odp_caps; 1436 1437 struct mlx5_ifc_odp_per_transport_service_cap_bits dc_odp_caps; 1438 1439 u8 reserved_at_120[0xe0]; 1440 }; 1441 1442 struct mlx5_ifc_odp_cap_bits { 1443 struct mlx5_ifc_odp_scheme_cap_bits transport_page_fault_scheme_cap; 1444 1445 struct mlx5_ifc_odp_scheme_cap_bits memory_page_fault_scheme_cap; 1446 1447 u8 reserved_at_400[0x200]; 1448 1449 u8 mem_page_fault[0x1]; 1450 u8 reserved_at_601[0x1f]; 1451 1452 u8 reserved_at_620[0x1e0]; 1453 }; 1454 1455 struct mlx5_ifc_tls_cap_bits { 1456 u8 tls_1_2_aes_gcm_128[0x1]; 1457 u8 tls_1_3_aes_gcm_128[0x1]; 1458 u8 tls_1_2_aes_gcm_256[0x1]; 1459 u8 tls_1_3_aes_gcm_256[0x1]; 1460 u8 reserved_at_4[0x1c]; 1461 1462 u8 reserved_at_20[0x7e0]; 1463 }; 1464 1465 struct mlx5_ifc_ipsec_cap_bits { 1466 u8 ipsec_full_offload[0x1]; 1467 u8 ipsec_crypto_offload[0x1]; 1468 u8 ipsec_esn[0x1]; 1469 u8 ipsec_crypto_esp_aes_gcm_256_encrypt[0x1]; 1470 u8 ipsec_crypto_esp_aes_gcm_128_encrypt[0x1]; 1471 u8 ipsec_crypto_esp_aes_gcm_256_decrypt[0x1]; 1472 u8 ipsec_crypto_esp_aes_gcm_128_decrypt[0x1]; 1473 u8 reserved_at_7[0x4]; 1474 u8 log_max_ipsec_offload[0x5]; 1475 u8 reserved_at_10[0x10]; 1476 1477 u8 min_log_ipsec_full_replay_window[0x8]; 1478 u8 max_log_ipsec_full_replay_window[0x8]; 1479 u8 reserved_at_30[0x7d0]; 1480 }; 1481 1482 struct mlx5_ifc_macsec_cap_bits { 1483 u8 macsec_epn[0x1]; 1484 u8 reserved_at_1[0x2]; 1485 u8 macsec_crypto_esp_aes_gcm_256_encrypt[0x1]; 1486 u8 macsec_crypto_esp_aes_gcm_128_encrypt[0x1]; 1487 u8 macsec_crypto_esp_aes_gcm_256_decrypt[0x1]; 1488 u8 macsec_crypto_esp_aes_gcm_128_decrypt[0x1]; 1489 u8 reserved_at_7[0x4]; 1490 u8 log_max_macsec_offload[0x5]; 1491 u8 reserved_at_10[0x10]; 1492 1493 u8 min_log_macsec_full_replay_window[0x8]; 1494 u8 max_log_macsec_full_replay_window[0x8]; 1495 u8 reserved_at_30[0x10]; 1496 1497 u8 reserved_at_40[0x7c0]; 1498 }; 1499 1500 enum { 1501 MLX5_WQ_TYPE_LINKED_LIST = 0x0, 1502 MLX5_WQ_TYPE_CYCLIC = 0x1, 1503 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2, 1504 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3, 1505 }; 1506 1507 enum { 1508 MLX5_WQ_END_PAD_MODE_NONE = 0x0, 1509 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1, 1510 }; 1511 1512 enum { 1513 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0, 1514 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1, 1515 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2, 1516 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3, 1517 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4, 1518 }; 1519 1520 enum { 1521 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0, 1522 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1, 1523 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2, 1524 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3, 1525 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4, 1526 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5, 1527 }; 1528 1529 enum { 1530 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0, 1531 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1, 1532 }; 1533 1534 enum { 1535 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0, 1536 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1, 1537 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3, 1538 }; 1539 1540 enum { 1541 MLX5_CAP_PORT_TYPE_IB = 0x0, 1542 MLX5_CAP_PORT_TYPE_ETH = 0x1, 1543 }; 1544 1545 enum { 1546 MLX5_CAP_UMR_FENCE_STRONG = 0x0, 1547 MLX5_CAP_UMR_FENCE_SMALL = 0x1, 1548 MLX5_CAP_UMR_FENCE_NONE = 0x2, 1549 }; 1550 1551 enum { 1552 MLX5_FLEX_IPV4_OVER_VXLAN_ENABLED = 1 << 0, 1553 MLX5_FLEX_IPV6_OVER_VXLAN_ENABLED = 1 << 1, 1554 MLX5_FLEX_IPV6_OVER_IP_ENABLED = 1 << 2, 1555 MLX5_FLEX_PARSER_GENEVE_ENABLED = 1 << 3, 1556 MLX5_FLEX_PARSER_MPLS_OVER_GRE_ENABLED = 1 << 4, 1557 MLX5_FLEX_PARSER_MPLS_OVER_UDP_ENABLED = 1 << 5, 1558 MLX5_FLEX_P_BIT_VXLAN_GPE_ENABLED = 1 << 6, 1559 MLX5_FLEX_PARSER_VXLAN_GPE_ENABLED = 1 << 7, 1560 MLX5_FLEX_PARSER_ICMP_V4_ENABLED = 1 << 8, 1561 MLX5_FLEX_PARSER_ICMP_V6_ENABLED = 1 << 9, 1562 MLX5_FLEX_PARSER_GENEVE_TLV_OPTION_0_ENABLED = 1 << 10, 1563 MLX5_FLEX_PARSER_GTPU_ENABLED = 1 << 11, 1564 MLX5_FLEX_PARSER_GTPU_DW_2_ENABLED = 1 << 16, 1565 MLX5_FLEX_PARSER_GTPU_FIRST_EXT_DW_0_ENABLED = 1 << 17, 1566 MLX5_FLEX_PARSER_GTPU_DW_0_ENABLED = 1 << 18, 1567 MLX5_FLEX_PARSER_GTPU_TEID_ENABLED = 1 << 19, 1568 }; 1569 1570 enum { 1571 MLX5_UCTX_CAP_RAW_TX = 1UL << 0, 1572 MLX5_UCTX_CAP_INTERNAL_DEV_RES = 1UL << 1, 1573 MLX5_UCTX_CAP_RDMA_CTRL = 1UL << 3, 1574 MLX5_UCTX_CAP_RDMA_CTRL_OTHER_VHCA = 1UL << 4, 1575 }; 1576 1577 #define MLX5_FC_BULK_SIZE_FACTOR 128 1578 1579 enum mlx5_fc_bulk_alloc_bitmask { 1580 MLX5_FC_BULK_128 = (1 << 0), 1581 MLX5_FC_BULK_256 = (1 << 1), 1582 MLX5_FC_BULK_512 = (1 << 2), 1583 MLX5_FC_BULK_1024 = (1 << 3), 1584 MLX5_FC_BULK_2048 = (1 << 4), 1585 MLX5_FC_BULK_4096 = (1 << 5), 1586 MLX5_FC_BULK_8192 = (1 << 6), 1587 MLX5_FC_BULK_16384 = (1 << 7), 1588 }; 1589 1590 #define MLX5_FC_BULK_NUM_FCS(fc_enum) (MLX5_FC_BULK_SIZE_FACTOR * (fc_enum)) 1591 1592 #define MLX5_FT_MAX_MULTIPATH_LEVEL 63 1593 1594 enum { 1595 MLX5_STEERING_FORMAT_CONNECTX_5 = 0, 1596 MLX5_STEERING_FORMAT_CONNECTX_6DX = 1, 1597 MLX5_STEERING_FORMAT_CONNECTX_7 = 2, 1598 MLX5_STEERING_FORMAT_CONNECTX_8 = 3, 1599 }; 1600 1601 struct mlx5_ifc_cmd_hca_cap_bits { 1602 u8 reserved_at_0[0x6]; 1603 u8 page_request_disable[0x1]; 1604 u8 abs_native_port_num[0x1]; 1605 u8 reserved_at_8[0x8]; 1606 u8 shared_object_to_user_object_allowed[0x1]; 1607 u8 reserved_at_13[0xe]; 1608 u8 vhca_resource_manager[0x1]; 1609 1610 u8 hca_cap_2[0x1]; 1611 u8 create_lag_when_not_master_up[0x1]; 1612 u8 dtor[0x1]; 1613 u8 event_on_vhca_state_teardown_request[0x1]; 1614 u8 event_on_vhca_state_in_use[0x1]; 1615 u8 event_on_vhca_state_active[0x1]; 1616 u8 event_on_vhca_state_allocated[0x1]; 1617 u8 event_on_vhca_state_invalid[0x1]; 1618 u8 reserved_at_28[0x8]; 1619 u8 vhca_id[0x10]; 1620 1621 u8 reserved_at_40[0x40]; 1622 1623 u8 log_max_srq_sz[0x8]; 1624 u8 log_max_qp_sz[0x8]; 1625 u8 event_cap[0x1]; 1626 u8 reserved_at_91[0x2]; 1627 u8 isolate_vl_tc_new[0x1]; 1628 u8 reserved_at_94[0x4]; 1629 u8 prio_tag_required[0x1]; 1630 u8 reserved_at_99[0x2]; 1631 u8 log_max_qp[0x5]; 1632 1633 u8 reserved_at_a0[0x3]; 1634 u8 ece_support[0x1]; 1635 u8 reserved_at_a4[0x5]; 1636 u8 reg_c_preserve[0x1]; 1637 u8 reserved_at_aa[0x1]; 1638 u8 log_max_srq[0x5]; 1639 u8 reserved_at_b0[0x1]; 1640 u8 uplink_follow[0x1]; 1641 u8 ts_cqe_to_dest_cqn[0x1]; 1642 u8 reserved_at_b3[0x6]; 1643 u8 go_back_n[0x1]; 1644 u8 reserved_at_ba[0x6]; 1645 1646 u8 max_sgl_for_optimized_performance[0x8]; 1647 u8 log_max_cq_sz[0x8]; 1648 u8 relaxed_ordering_write_umr[0x1]; 1649 u8 relaxed_ordering_read_umr[0x1]; 1650 u8 reserved_at_d2[0x7]; 1651 u8 virtio_net_device_emualtion_manager[0x1]; 1652 u8 virtio_blk_device_emualtion_manager[0x1]; 1653 u8 log_max_cq[0x5]; 1654 1655 u8 log_max_eq_sz[0x8]; 1656 u8 relaxed_ordering_write[0x1]; 1657 u8 relaxed_ordering_read_pci_enabled[0x1]; 1658 u8 log_max_mkey[0x6]; 1659 u8 reserved_at_f0[0x6]; 1660 u8 terminate_scatter_list_mkey[0x1]; 1661 u8 repeated_mkey[0x1]; 1662 u8 dump_fill_mkey[0x1]; 1663 u8 reserved_at_f9[0x2]; 1664 u8 fast_teardown[0x1]; 1665 u8 log_max_eq[0x4]; 1666 1667 u8 max_indirection[0x8]; 1668 u8 fixed_buffer_size[0x1]; 1669 u8 log_max_mrw_sz[0x7]; 1670 u8 force_teardown[0x1]; 1671 u8 reserved_at_111[0x1]; 1672 u8 log_max_bsf_list_size[0x6]; 1673 u8 umr_extended_translation_offset[0x1]; 1674 u8 null_mkey[0x1]; 1675 u8 log_max_klm_list_size[0x6]; 1676 1677 u8 reserved_at_120[0x2]; 1678 u8 qpc_extension[0x1]; 1679 u8 reserved_at_123[0x7]; 1680 u8 log_max_ra_req_dc[0x6]; 1681 u8 reserved_at_130[0x2]; 1682 u8 eth_wqe_too_small[0x1]; 1683 u8 reserved_at_133[0x6]; 1684 u8 vnic_env_cq_overrun[0x1]; 1685 u8 log_max_ra_res_dc[0x6]; 1686 1687 u8 reserved_at_140[0x5]; 1688 u8 release_all_pages[0x1]; 1689 u8 must_not_use[0x1]; 1690 u8 reserved_at_147[0x2]; 1691 u8 roce_accl[0x1]; 1692 u8 log_max_ra_req_qp[0x6]; 1693 u8 reserved_at_150[0xa]; 1694 u8 log_max_ra_res_qp[0x6]; 1695 1696 u8 end_pad[0x1]; 1697 u8 cc_query_allowed[0x1]; 1698 u8 cc_modify_allowed[0x1]; 1699 u8 start_pad[0x1]; 1700 u8 cache_line_128byte[0x1]; 1701 u8 reserved_at_165[0x4]; 1702 u8 rts2rts_qp_counters_set_id[0x1]; 1703 u8 reserved_at_16a[0x2]; 1704 u8 vnic_env_int_rq_oob[0x1]; 1705 u8 sbcam_reg[0x1]; 1706 u8 reserved_at_16e[0x1]; 1707 u8 qcam_reg[0x1]; 1708 u8 gid_table_size[0x10]; 1709 1710 u8 out_of_seq_cnt[0x1]; 1711 u8 vport_counters[0x1]; 1712 u8 retransmission_q_counters[0x1]; 1713 u8 debug[0x1]; 1714 u8 modify_rq_counter_set_id[0x1]; 1715 u8 rq_delay_drop[0x1]; 1716 u8 max_qp_cnt[0xa]; 1717 u8 pkey_table_size[0x10]; 1718 1719 u8 vport_group_manager[0x1]; 1720 u8 vhca_group_manager[0x1]; 1721 u8 ib_virt[0x1]; 1722 u8 eth_virt[0x1]; 1723 u8 vnic_env_queue_counters[0x1]; 1724 u8 ets[0x1]; 1725 u8 nic_flow_table[0x1]; 1726 u8 eswitch_manager[0x1]; 1727 u8 device_memory[0x1]; 1728 u8 mcam_reg[0x1]; 1729 u8 pcam_reg[0x1]; 1730 u8 local_ca_ack_delay[0x5]; 1731 u8 port_module_event[0x1]; 1732 u8 enhanced_error_q_counters[0x1]; 1733 u8 ports_check[0x1]; 1734 u8 reserved_at_1b3[0x1]; 1735 u8 disable_link_up[0x1]; 1736 u8 beacon_led[0x1]; 1737 u8 port_type[0x2]; 1738 u8 num_ports[0x8]; 1739 1740 u8 reserved_at_1c0[0x1]; 1741 u8 pps[0x1]; 1742 u8 pps_modify[0x1]; 1743 u8 log_max_msg[0x5]; 1744 u8 reserved_at_1c8[0x4]; 1745 u8 max_tc[0x4]; 1746 u8 temp_warn_event[0x1]; 1747 u8 dcbx[0x1]; 1748 u8 general_notification_event[0x1]; 1749 u8 reserved_at_1d3[0x2]; 1750 u8 fpga[0x1]; 1751 u8 rol_s[0x1]; 1752 u8 rol_g[0x1]; 1753 u8 reserved_at_1d8[0x1]; 1754 u8 wol_s[0x1]; 1755 u8 wol_g[0x1]; 1756 u8 wol_a[0x1]; 1757 u8 wol_b[0x1]; 1758 u8 wol_m[0x1]; 1759 u8 wol_u[0x1]; 1760 u8 wol_p[0x1]; 1761 1762 u8 stat_rate_support[0x10]; 1763 u8 reserved_at_1f0[0x1]; 1764 u8 pci_sync_for_fw_update_event[0x1]; 1765 u8 reserved_at_1f2[0x6]; 1766 u8 init2_lag_tx_port_affinity[0x1]; 1767 u8 reserved_at_1fa[0x2]; 1768 u8 wqe_based_flow_table_update_cap[0x1]; 1769 u8 cqe_version[0x4]; 1770 1771 u8 compact_address_vector[0x1]; 1772 u8 striding_rq[0x1]; 1773 u8 reserved_at_202[0x1]; 1774 u8 ipoib_enhanced_offloads[0x1]; 1775 u8 ipoib_basic_offloads[0x1]; 1776 u8 reserved_at_205[0x1]; 1777 u8 repeated_block_disabled[0x1]; 1778 u8 umr_modify_entity_size_disabled[0x1]; 1779 u8 umr_modify_atomic_disabled[0x1]; 1780 u8 umr_indirect_mkey_disabled[0x1]; 1781 u8 umr_fence[0x2]; 1782 u8 dc_req_scat_data_cqe[0x1]; 1783 u8 reserved_at_20d[0x2]; 1784 u8 drain_sigerr[0x1]; 1785 u8 cmdif_checksum[0x2]; 1786 u8 sigerr_cqe[0x1]; 1787 u8 reserved_at_213[0x1]; 1788 u8 wq_signature[0x1]; 1789 u8 sctr_data_cqe[0x1]; 1790 u8 reserved_at_216[0x1]; 1791 u8 sho[0x1]; 1792 u8 tph[0x1]; 1793 u8 rf[0x1]; 1794 u8 dct[0x1]; 1795 u8 qos[0x1]; 1796 u8 eth_net_offloads[0x1]; 1797 u8 roce[0x1]; 1798 u8 atomic[0x1]; 1799 u8 reserved_at_21f[0x1]; 1800 1801 u8 cq_oi[0x1]; 1802 u8 cq_resize[0x1]; 1803 u8 cq_moderation[0x1]; 1804 u8 cq_period_mode_modify[0x1]; 1805 u8 reserved_at_224[0x2]; 1806 u8 cq_eq_remap[0x1]; 1807 u8 pg[0x1]; 1808 u8 block_lb_mc[0x1]; 1809 u8 reserved_at_229[0x1]; 1810 u8 scqe_break_moderation[0x1]; 1811 u8 cq_period_start_from_cqe[0x1]; 1812 u8 cd[0x1]; 1813 u8 reserved_at_22d[0x1]; 1814 u8 apm[0x1]; 1815 u8 vector_calc[0x1]; 1816 u8 umr_ptr_rlky[0x1]; 1817 u8 imaicl[0x1]; 1818 u8 qp_packet_based[0x1]; 1819 u8 reserved_at_233[0x3]; 1820 u8 qkv[0x1]; 1821 u8 pkv[0x1]; 1822 u8 set_deth_sqpn[0x1]; 1823 u8 reserved_at_239[0x3]; 1824 u8 xrc[0x1]; 1825 u8 ud[0x1]; 1826 u8 uc[0x1]; 1827 u8 rc[0x1]; 1828 1829 u8 uar_4k[0x1]; 1830 u8 reserved_at_241[0x7]; 1831 u8 fl_rc_qp_when_roce_disabled[0x1]; 1832 u8 regexp_params[0x1]; 1833 u8 uar_sz[0x6]; 1834 u8 port_selection_cap[0x1]; 1835 u8 nic_cap_reg[0x1]; 1836 u8 umem_uid_0[0x1]; 1837 u8 reserved_at_253[0x5]; 1838 u8 log_pg_sz[0x8]; 1839 1840 u8 bf[0x1]; 1841 u8 driver_version[0x1]; 1842 u8 pad_tx_eth_packet[0x1]; 1843 u8 reserved_at_263[0x3]; 1844 u8 mkey_by_name[0x1]; 1845 u8 reserved_at_267[0x4]; 1846 1847 u8 log_bf_reg_size[0x5]; 1848 1849 u8 disciplined_fr_counter[0x1]; 1850 u8 reserved_at_271[0x2]; 1851 u8 qp_error_syndrome[0x1]; 1852 u8 reserved_at_274[0x2]; 1853 u8 lag_dct[0x2]; 1854 u8 lag_tx_port_affinity[0x1]; 1855 u8 lag_native_fdb_selection[0x1]; 1856 u8 reserved_at_27a[0x1]; 1857 u8 lag_master[0x1]; 1858 u8 num_lag_ports[0x4]; 1859 1860 u8 reserved_at_280[0x10]; 1861 u8 max_wqe_sz_sq[0x10]; 1862 1863 u8 reserved_at_2a0[0xb]; 1864 u8 shampo[0x1]; 1865 u8 reserved_at_2ac[0x4]; 1866 u8 max_wqe_sz_rq[0x10]; 1867 1868 u8 max_flow_counter_31_16[0x10]; 1869 u8 max_wqe_sz_sq_dc[0x10]; 1870 1871 u8 reserved_at_2e0[0x7]; 1872 u8 max_qp_mcg[0x19]; 1873 1874 u8 reserved_at_300[0x10]; 1875 u8 flow_counter_bulk_alloc[0x8]; 1876 u8 log_max_mcg[0x8]; 1877 1878 u8 reserved_at_320[0x3]; 1879 u8 log_max_transport_domain[0x5]; 1880 u8 reserved_at_328[0x2]; 1881 u8 relaxed_ordering_read[0x1]; 1882 u8 log_max_pd[0x5]; 1883 u8 dp_ordering_ooo_all_ud[0x1]; 1884 u8 dp_ordering_ooo_all_uc[0x1]; 1885 u8 dp_ordering_ooo_all_xrc[0x1]; 1886 u8 dp_ordering_ooo_all_dc[0x1]; 1887 u8 dp_ordering_ooo_all_rc[0x1]; 1888 u8 pcie_reset_using_hotreset_method[0x1]; 1889 u8 pci_sync_for_fw_update_with_driver_unload[0x1]; 1890 u8 vnic_env_cnt_steering_fail[0x1]; 1891 u8 vport_counter_local_loopback[0x1]; 1892 u8 q_counter_aggregation[0x1]; 1893 u8 q_counter_other_vport[0x1]; 1894 u8 log_max_xrcd[0x5]; 1895 1896 u8 nic_receive_steering_discard[0x1]; 1897 u8 receive_discard_vport_down[0x1]; 1898 u8 transmit_discard_vport_down[0x1]; 1899 u8 eq_overrun_count[0x1]; 1900 u8 reserved_at_344[0x1]; 1901 u8 invalid_command_count[0x1]; 1902 u8 quota_exceeded_count[0x1]; 1903 u8 reserved_at_347[0x1]; 1904 u8 log_max_flow_counter_bulk[0x8]; 1905 u8 max_flow_counter_15_0[0x10]; 1906 1907 1908 u8 reserved_at_360[0x3]; 1909 u8 log_max_rq[0x5]; 1910 u8 reserved_at_368[0x3]; 1911 u8 log_max_sq[0x5]; 1912 u8 reserved_at_370[0x3]; 1913 u8 log_max_tir[0x5]; 1914 u8 reserved_at_378[0x3]; 1915 u8 log_max_tis[0x5]; 1916 1917 u8 basic_cyclic_rcv_wqe[0x1]; 1918 u8 reserved_at_381[0x2]; 1919 u8 log_max_rmp[0x5]; 1920 u8 reserved_at_388[0x3]; 1921 u8 log_max_rqt[0x5]; 1922 u8 reserved_at_390[0x3]; 1923 u8 log_max_rqt_size[0x5]; 1924 u8 reserved_at_398[0x3]; 1925 u8 log_max_tis_per_sq[0x5]; 1926 1927 u8 ext_stride_num_range[0x1]; 1928 u8 roce_rw_supported[0x1]; 1929 u8 log_max_current_uc_list_wr_supported[0x1]; 1930 u8 log_max_stride_sz_rq[0x5]; 1931 u8 reserved_at_3a8[0x3]; 1932 u8 log_min_stride_sz_rq[0x5]; 1933 u8 reserved_at_3b0[0x3]; 1934 u8 log_max_stride_sz_sq[0x5]; 1935 u8 reserved_at_3b8[0x3]; 1936 u8 log_min_stride_sz_sq[0x5]; 1937 1938 u8 hairpin[0x1]; 1939 u8 reserved_at_3c1[0x2]; 1940 u8 log_max_hairpin_queues[0x5]; 1941 u8 reserved_at_3c8[0x3]; 1942 u8 log_max_hairpin_wq_data_sz[0x5]; 1943 u8 reserved_at_3d0[0x3]; 1944 u8 log_max_hairpin_num_packets[0x5]; 1945 u8 reserved_at_3d8[0x3]; 1946 u8 log_max_wq_sz[0x5]; 1947 1948 u8 nic_vport_change_event[0x1]; 1949 u8 disable_local_lb_uc[0x1]; 1950 u8 disable_local_lb_mc[0x1]; 1951 u8 log_min_hairpin_wq_data_sz[0x5]; 1952 u8 reserved_at_3e8[0x1]; 1953 u8 silent_mode[0x1]; 1954 u8 vhca_state[0x1]; 1955 u8 log_max_vlan_list[0x5]; 1956 u8 reserved_at_3f0[0x3]; 1957 u8 log_max_current_mc_list[0x5]; 1958 u8 reserved_at_3f8[0x3]; 1959 u8 log_max_current_uc_list[0x5]; 1960 1961 u8 general_obj_types[0x40]; 1962 1963 u8 sq_ts_format[0x2]; 1964 u8 rq_ts_format[0x2]; 1965 u8 steering_format_version[0x4]; 1966 u8 create_qp_start_hint[0x18]; 1967 1968 u8 reserved_at_460[0x1]; 1969 u8 ats[0x1]; 1970 u8 cross_vhca_rqt[0x1]; 1971 u8 log_max_uctx[0x5]; 1972 u8 reserved_at_468[0x1]; 1973 u8 crypto[0x1]; 1974 u8 ipsec_offload[0x1]; 1975 u8 log_max_umem[0x5]; 1976 u8 max_num_eqs[0x10]; 1977 1978 u8 reserved_at_480[0x1]; 1979 u8 tls_tx[0x1]; 1980 u8 tls_rx[0x1]; 1981 u8 log_max_l2_table[0x5]; 1982 u8 reserved_at_488[0x8]; 1983 u8 log_uar_page_sz[0x10]; 1984 1985 u8 reserved_at_4a0[0x20]; 1986 u8 device_frequency_mhz[0x20]; 1987 u8 device_frequency_khz[0x20]; 1988 1989 u8 reserved_at_500[0x20]; 1990 u8 num_of_uars_per_page[0x20]; 1991 1992 u8 flex_parser_protocols[0x20]; 1993 1994 u8 max_geneve_tlv_options[0x8]; 1995 u8 reserved_at_568[0x3]; 1996 u8 max_geneve_tlv_option_data_len[0x5]; 1997 u8 reserved_at_570[0x1]; 1998 u8 adv_rdma[0x1]; 1999 u8 reserved_at_572[0x7]; 2000 u8 adv_virtualization[0x1]; 2001 u8 reserved_at_57a[0x6]; 2002 2003 u8 reserved_at_580[0xb]; 2004 u8 log_max_dci_stream_channels[0x5]; 2005 u8 reserved_at_590[0x3]; 2006 u8 log_max_dci_errored_streams[0x5]; 2007 u8 reserved_at_598[0x8]; 2008 2009 u8 reserved_at_5a0[0x10]; 2010 u8 enhanced_cqe_compression[0x1]; 2011 u8 reserved_at_5b1[0x1]; 2012 u8 crossing_vhca_mkey[0x1]; 2013 u8 log_max_dek[0x5]; 2014 u8 reserved_at_5b8[0x4]; 2015 u8 mini_cqe_resp_stride_index[0x1]; 2016 u8 cqe_128_always[0x1]; 2017 u8 cqe_compression_128[0x1]; 2018 u8 cqe_compression[0x1]; 2019 2020 u8 cqe_compression_timeout[0x10]; 2021 u8 cqe_compression_max_num[0x10]; 2022 2023 u8 reserved_at_5e0[0x8]; 2024 u8 flex_parser_id_gtpu_dw_0[0x4]; 2025 u8 reserved_at_5ec[0x4]; 2026 u8 tag_matching[0x1]; 2027 u8 rndv_offload_rc[0x1]; 2028 u8 rndv_offload_dc[0x1]; 2029 u8 log_tag_matching_list_sz[0x5]; 2030 u8 reserved_at_5f8[0x3]; 2031 u8 log_max_xrq[0x5]; 2032 2033 u8 affiliate_nic_vport_criteria[0x8]; 2034 u8 native_port_num[0x8]; 2035 u8 num_vhca_ports[0x8]; 2036 u8 flex_parser_id_gtpu_teid[0x4]; 2037 u8 reserved_at_61c[0x2]; 2038 u8 sw_owner_id[0x1]; 2039 u8 reserved_at_61f[0x1]; 2040 2041 u8 max_num_of_monitor_counters[0x10]; 2042 u8 num_ppcnt_monitor_counters[0x10]; 2043 2044 u8 max_num_sf[0x10]; 2045 u8 num_q_monitor_counters[0x10]; 2046 2047 u8 reserved_at_660[0x20]; 2048 2049 u8 sf[0x1]; 2050 u8 sf_set_partition[0x1]; 2051 u8 reserved_at_682[0x1]; 2052 u8 log_max_sf[0x5]; 2053 u8 apu[0x1]; 2054 u8 reserved_at_689[0x4]; 2055 u8 migration[0x1]; 2056 u8 reserved_at_68e[0x2]; 2057 u8 log_min_sf_size[0x8]; 2058 u8 max_num_sf_partitions[0x8]; 2059 2060 u8 uctx_cap[0x20]; 2061 2062 u8 reserved_at_6c0[0x4]; 2063 u8 flex_parser_id_geneve_tlv_option_0[0x4]; 2064 u8 flex_parser_id_icmp_dw1[0x4]; 2065 u8 flex_parser_id_icmp_dw0[0x4]; 2066 u8 flex_parser_id_icmpv6_dw1[0x4]; 2067 u8 flex_parser_id_icmpv6_dw0[0x4]; 2068 u8 flex_parser_id_outer_first_mpls_over_gre[0x4]; 2069 u8 flex_parser_id_outer_first_mpls_over_udp_label[0x4]; 2070 2071 u8 max_num_match_definer[0x10]; 2072 u8 sf_base_id[0x10]; 2073 2074 u8 flex_parser_id_gtpu_dw_2[0x4]; 2075 u8 flex_parser_id_gtpu_first_ext_dw_0[0x4]; 2076 u8 num_total_dynamic_vf_msix[0x18]; 2077 u8 reserved_at_720[0x14]; 2078 u8 dynamic_msix_table_size[0xc]; 2079 u8 reserved_at_740[0xc]; 2080 u8 min_dynamic_vf_msix_table_size[0x4]; 2081 u8 reserved_at_750[0x2]; 2082 u8 data_direct[0x1]; 2083 u8 reserved_at_753[0x1]; 2084 u8 max_dynamic_vf_msix_table_size[0xc]; 2085 2086 u8 reserved_at_760[0x3]; 2087 u8 log_max_num_header_modify_argument[0x5]; 2088 u8 log_header_modify_argument_granularity_offset[0x4]; 2089 u8 log_header_modify_argument_granularity[0x4]; 2090 u8 reserved_at_770[0x3]; 2091 u8 log_header_modify_argument_max_alloc[0x5]; 2092 u8 reserved_at_778[0x8]; 2093 2094 u8 vhca_tunnel_commands[0x40]; 2095 u8 match_definer_format_supported[0x40]; 2096 }; 2097 2098 enum { 2099 MLX5_CROSS_VHCA_OBJ_TO_OBJ_SUPPORTED_LOCAL_FLOW_TABLE_TO_REMOTE_FLOW_TABLE_MISS = 0x80000, 2100 MLX5_CROSS_VHCA_OBJ_TO_OBJ_SUPPORTED_LOCAL_FLOW_TABLE_ROOT_TO_REMOTE_FLOW_TABLE = (1ULL << 20), 2101 }; 2102 2103 enum { 2104 MLX5_ALLOWED_OBJ_FOR_OTHER_VHCA_ACCESS_FLOW_TABLE = 0x200, 2105 }; 2106 2107 struct mlx5_ifc_cmd_hca_cap_2_bits { 2108 u8 reserved_at_0[0x80]; 2109 2110 u8 migratable[0x1]; 2111 u8 reserved_at_81[0x7]; 2112 u8 dp_ordering_force[0x1]; 2113 u8 reserved_at_89[0x9]; 2114 u8 query_vuid[0x1]; 2115 u8 reserved_at_93[0x5]; 2116 u8 umr_log_entity_size_5[0x1]; 2117 u8 reserved_at_99[0x7]; 2118 2119 u8 max_reformat_insert_size[0x8]; 2120 u8 max_reformat_insert_offset[0x8]; 2121 u8 max_reformat_remove_size[0x8]; 2122 u8 max_reformat_remove_offset[0x8]; 2123 2124 u8 reserved_at_c0[0x8]; 2125 u8 migration_multi_load[0x1]; 2126 u8 migration_tracking_state[0x1]; 2127 u8 multiplane_qp_ud[0x1]; 2128 u8 reserved_at_cb[0x5]; 2129 u8 migration_in_chunks[0x1]; 2130 u8 reserved_at_d1[0x1]; 2131 u8 sf_eq_usage[0x1]; 2132 u8 reserved_at_d3[0x5]; 2133 u8 multiplane[0x1]; 2134 u8 reserved_at_d9[0x7]; 2135 2136 u8 cross_vhca_object_to_object_supported[0x20]; 2137 2138 u8 allowed_object_for_other_vhca_access[0x40]; 2139 2140 u8 reserved_at_140[0x60]; 2141 2142 u8 flow_table_type_2_type[0x8]; 2143 u8 reserved_at_1a8[0x2]; 2144 u8 format_select_dw_8_6_ext[0x1]; 2145 u8 log_min_mkey_entity_size[0x5]; 2146 u8 reserved_at_1b0[0x10]; 2147 2148 u8 general_obj_types_127_64[0x40]; 2149 u8 reserved_at_200[0x20]; 2150 2151 u8 reserved_at_220[0x1]; 2152 u8 sw_vhca_id_valid[0x1]; 2153 u8 sw_vhca_id[0xe]; 2154 u8 reserved_at_230[0x10]; 2155 2156 u8 reserved_at_240[0xb]; 2157 u8 ts_cqe_metadata_size2wqe_counter[0x5]; 2158 u8 reserved_at_250[0x10]; 2159 2160 u8 reserved_at_260[0x20]; 2161 2162 u8 format_select_dw_gtpu_dw_0[0x8]; 2163 u8 format_select_dw_gtpu_dw_1[0x8]; 2164 u8 format_select_dw_gtpu_dw_2[0x8]; 2165 u8 format_select_dw_gtpu_first_ext_dw_0[0x8]; 2166 2167 u8 generate_wqe_type[0x20]; 2168 2169 u8 reserved_at_2c0[0xc0]; 2170 2171 u8 reserved_at_380[0xb]; 2172 u8 min_mkey_log_entity_size_fixed_buffer[0x5]; 2173 u8 ec_vf_vport_base[0x10]; 2174 2175 u8 reserved_at_3a0[0x2]; 2176 u8 max_mkey_log_entity_size_fixed_buffer[0x6]; 2177 u8 reserved_at_3a8[0x2]; 2178 u8 max_mkey_log_entity_size_mtt[0x6]; 2179 u8 max_rqt_vhca_id[0x10]; 2180 2181 u8 reserved_at_3c0[0x20]; 2182 2183 u8 reserved_at_3e0[0x10]; 2184 u8 pcc_ifa2[0x1]; 2185 u8 reserved_at_3f1[0xf]; 2186 2187 u8 reserved_at_400[0x1]; 2188 u8 min_mkey_log_entity_size_fixed_buffer_valid[0x1]; 2189 u8 reserved_at_402[0xe]; 2190 u8 return_reg_id[0x10]; 2191 2192 u8 reserved_at_420[0x1c]; 2193 u8 flow_table_hash_type[0x4]; 2194 2195 u8 reserved_at_440[0x8]; 2196 u8 max_num_eqs_24b[0x18]; 2197 u8 reserved_at_460[0x3a0]; 2198 }; 2199 2200 enum mlx5_ifc_flow_destination_type { 2201 MLX5_IFC_FLOW_DESTINATION_TYPE_VPORT = 0x0, 2202 MLX5_IFC_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1, 2203 MLX5_IFC_FLOW_DESTINATION_TYPE_TIR = 0x2, 2204 MLX5_IFC_FLOW_DESTINATION_TYPE_FLOW_SAMPLER = 0x6, 2205 MLX5_IFC_FLOW_DESTINATION_TYPE_UPLINK = 0x8, 2206 MLX5_IFC_FLOW_DESTINATION_TYPE_TABLE_TYPE = 0xA, 2207 }; 2208 2209 enum mlx5_flow_table_miss_action { 2210 MLX5_FLOW_TABLE_MISS_ACTION_DEF, 2211 MLX5_FLOW_TABLE_MISS_ACTION_FWD, 2212 MLX5_FLOW_TABLE_MISS_ACTION_SWITCH_DOMAIN, 2213 }; 2214 2215 struct mlx5_ifc_dest_format_struct_bits { 2216 u8 destination_type[0x8]; 2217 u8 destination_id[0x18]; 2218 2219 u8 destination_eswitch_owner_vhca_id_valid[0x1]; 2220 u8 packet_reformat[0x1]; 2221 u8 reserved_at_22[0x6]; 2222 u8 destination_table_type[0x8]; 2223 u8 destination_eswitch_owner_vhca_id[0x10]; 2224 }; 2225 2226 struct mlx5_ifc_flow_counter_list_bits { 2227 u8 flow_counter_id[0x20]; 2228 2229 u8 reserved_at_20[0x20]; 2230 }; 2231 2232 struct mlx5_ifc_extended_dest_format_bits { 2233 struct mlx5_ifc_dest_format_struct_bits destination_entry; 2234 2235 u8 packet_reformat_id[0x20]; 2236 2237 u8 reserved_at_60[0x20]; 2238 }; 2239 2240 union mlx5_ifc_dest_format_flow_counter_list_auto_bits { 2241 struct mlx5_ifc_extended_dest_format_bits extended_dest_format; 2242 struct mlx5_ifc_flow_counter_list_bits flow_counter_list; 2243 }; 2244 2245 struct mlx5_ifc_fte_match_param_bits { 2246 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers; 2247 2248 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters; 2249 2250 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers; 2251 2252 struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2; 2253 2254 struct mlx5_ifc_fte_match_set_misc3_bits misc_parameters_3; 2255 2256 struct mlx5_ifc_fte_match_set_misc4_bits misc_parameters_4; 2257 2258 struct mlx5_ifc_fte_match_set_misc5_bits misc_parameters_5; 2259 2260 u8 reserved_at_e00[0x200]; 2261 }; 2262 2263 enum { 2264 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0, 2265 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1, 2266 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2, 2267 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3, 2268 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4, 2269 }; 2270 2271 struct mlx5_ifc_rx_hash_field_select_bits { 2272 u8 l3_prot_type[0x1]; 2273 u8 l4_prot_type[0x1]; 2274 u8 selected_fields[0x1e]; 2275 }; 2276 2277 enum { 2278 MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0, 2279 MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1, 2280 }; 2281 2282 enum { 2283 MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0, 2284 MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1, 2285 }; 2286 2287 struct mlx5_ifc_wq_bits { 2288 u8 wq_type[0x4]; 2289 u8 wq_signature[0x1]; 2290 u8 end_padding_mode[0x2]; 2291 u8 cd_slave[0x1]; 2292 u8 reserved_at_8[0x18]; 2293 2294 u8 hds_skip_first_sge[0x1]; 2295 u8 log2_hds_buf_size[0x3]; 2296 u8 reserved_at_24[0x7]; 2297 u8 page_offset[0x5]; 2298 u8 lwm[0x10]; 2299 2300 u8 reserved_at_40[0x8]; 2301 u8 pd[0x18]; 2302 2303 u8 reserved_at_60[0x8]; 2304 u8 uar_page[0x18]; 2305 2306 u8 dbr_addr[0x40]; 2307 2308 u8 hw_counter[0x20]; 2309 2310 u8 sw_counter[0x20]; 2311 2312 u8 reserved_at_100[0xc]; 2313 u8 log_wq_stride[0x4]; 2314 u8 reserved_at_110[0x3]; 2315 u8 log_wq_pg_sz[0x5]; 2316 u8 reserved_at_118[0x3]; 2317 u8 log_wq_sz[0x5]; 2318 2319 u8 dbr_umem_valid[0x1]; 2320 u8 wq_umem_valid[0x1]; 2321 u8 reserved_at_122[0x1]; 2322 u8 log_hairpin_num_packets[0x5]; 2323 u8 reserved_at_128[0x3]; 2324 u8 log_hairpin_data_sz[0x5]; 2325 2326 u8 reserved_at_130[0x4]; 2327 u8 log_wqe_num_of_strides[0x4]; 2328 u8 two_byte_shift_en[0x1]; 2329 u8 reserved_at_139[0x4]; 2330 u8 log_wqe_stride_size[0x3]; 2331 2332 u8 dbr_umem_id[0x20]; 2333 u8 wq_umem_id[0x20]; 2334 2335 u8 wq_umem_offset[0x40]; 2336 2337 u8 headers_mkey[0x20]; 2338 2339 u8 shampo_enable[0x1]; 2340 u8 reserved_at_1e1[0x1]; 2341 u8 shampo_mode[0x2]; 2342 u8 reserved_at_1e4[0x1]; 2343 u8 log_reservation_size[0x3]; 2344 u8 reserved_at_1e8[0x5]; 2345 u8 log_max_num_of_packets_per_reservation[0x3]; 2346 u8 reserved_at_1f0[0x6]; 2347 u8 log_headers_entry_size[0x2]; 2348 u8 reserved_at_1f8[0x4]; 2349 u8 log_headers_buffer_entry_num[0x4]; 2350 2351 u8 reserved_at_200[0x400]; 2352 2353 struct mlx5_ifc_cmd_pas_bits pas[]; 2354 }; 2355 2356 struct mlx5_ifc_rq_num_bits { 2357 u8 reserved_at_0[0x8]; 2358 u8 rq_num[0x18]; 2359 }; 2360 2361 struct mlx5_ifc_rq_vhca_bits { 2362 u8 reserved_at_0[0x8]; 2363 u8 rq_num[0x18]; 2364 u8 reserved_at_20[0x10]; 2365 u8 rq_vhca_id[0x10]; 2366 }; 2367 2368 struct mlx5_ifc_mac_address_layout_bits { 2369 u8 reserved_at_0[0x10]; 2370 u8 mac_addr_47_32[0x10]; 2371 2372 u8 mac_addr_31_0[0x20]; 2373 }; 2374 2375 struct mlx5_ifc_vlan_layout_bits { 2376 u8 reserved_at_0[0x14]; 2377 u8 vlan[0x0c]; 2378 2379 u8 reserved_at_20[0x20]; 2380 }; 2381 2382 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits { 2383 u8 reserved_at_0[0xa0]; 2384 2385 u8 min_time_between_cnps[0x20]; 2386 2387 u8 reserved_at_c0[0x12]; 2388 u8 cnp_dscp[0x6]; 2389 u8 reserved_at_d8[0x4]; 2390 u8 cnp_prio_mode[0x1]; 2391 u8 cnp_802p_prio[0x3]; 2392 2393 u8 reserved_at_e0[0x720]; 2394 }; 2395 2396 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits { 2397 u8 reserved_at_0[0x60]; 2398 2399 u8 reserved_at_60[0x4]; 2400 u8 clamp_tgt_rate[0x1]; 2401 u8 reserved_at_65[0x3]; 2402 u8 clamp_tgt_rate_after_time_inc[0x1]; 2403 u8 reserved_at_69[0x17]; 2404 2405 u8 reserved_at_80[0x20]; 2406 2407 u8 rpg_time_reset[0x20]; 2408 2409 u8 rpg_byte_reset[0x20]; 2410 2411 u8 rpg_threshold[0x20]; 2412 2413 u8 rpg_max_rate[0x20]; 2414 2415 u8 rpg_ai_rate[0x20]; 2416 2417 u8 rpg_hai_rate[0x20]; 2418 2419 u8 rpg_gd[0x20]; 2420 2421 u8 rpg_min_dec_fac[0x20]; 2422 2423 u8 rpg_min_rate[0x20]; 2424 2425 u8 reserved_at_1c0[0xe0]; 2426 2427 u8 rate_to_set_on_first_cnp[0x20]; 2428 2429 u8 dce_tcp_g[0x20]; 2430 2431 u8 dce_tcp_rtt[0x20]; 2432 2433 u8 rate_reduce_monitor_period[0x20]; 2434 2435 u8 reserved_at_320[0x20]; 2436 2437 u8 initial_alpha_value[0x20]; 2438 2439 u8 reserved_at_360[0x4a0]; 2440 }; 2441 2442 struct mlx5_ifc_cong_control_r_roce_general_bits { 2443 u8 reserved_at_0[0x80]; 2444 2445 u8 reserved_at_80[0x10]; 2446 u8 rtt_resp_dscp_valid[0x1]; 2447 u8 reserved_at_91[0x9]; 2448 u8 rtt_resp_dscp[0x6]; 2449 2450 u8 reserved_at_a0[0x760]; 2451 }; 2452 2453 struct mlx5_ifc_cong_control_802_1qau_rp_bits { 2454 u8 reserved_at_0[0x80]; 2455 2456 u8 rppp_max_rps[0x20]; 2457 2458 u8 rpg_time_reset[0x20]; 2459 2460 u8 rpg_byte_reset[0x20]; 2461 2462 u8 rpg_threshold[0x20]; 2463 2464 u8 rpg_max_rate[0x20]; 2465 2466 u8 rpg_ai_rate[0x20]; 2467 2468 u8 rpg_hai_rate[0x20]; 2469 2470 u8 rpg_gd[0x20]; 2471 2472 u8 rpg_min_dec_fac[0x20]; 2473 2474 u8 rpg_min_rate[0x20]; 2475 2476 u8 reserved_at_1c0[0x640]; 2477 }; 2478 2479 enum { 2480 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1, 2481 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2, 2482 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4, 2483 }; 2484 2485 struct mlx5_ifc_resize_field_select_bits { 2486 u8 resize_field_select[0x20]; 2487 }; 2488 2489 struct mlx5_ifc_resource_dump_bits { 2490 u8 more_dump[0x1]; 2491 u8 inline_dump[0x1]; 2492 u8 reserved_at_2[0xa]; 2493 u8 seq_num[0x4]; 2494 u8 segment_type[0x10]; 2495 2496 u8 reserved_at_20[0x10]; 2497 u8 vhca_id[0x10]; 2498 2499 u8 index1[0x20]; 2500 2501 u8 index2[0x20]; 2502 2503 u8 num_of_obj1[0x10]; 2504 u8 num_of_obj2[0x10]; 2505 2506 u8 reserved_at_a0[0x20]; 2507 2508 u8 device_opaque[0x40]; 2509 2510 u8 mkey[0x20]; 2511 2512 u8 size[0x20]; 2513 2514 u8 address[0x40]; 2515 2516 u8 inline_data[52][0x20]; 2517 }; 2518 2519 struct mlx5_ifc_resource_dump_menu_record_bits { 2520 u8 reserved_at_0[0x4]; 2521 u8 num_of_obj2_supports_active[0x1]; 2522 u8 num_of_obj2_supports_all[0x1]; 2523 u8 must_have_num_of_obj2[0x1]; 2524 u8 support_num_of_obj2[0x1]; 2525 u8 num_of_obj1_supports_active[0x1]; 2526 u8 num_of_obj1_supports_all[0x1]; 2527 u8 must_have_num_of_obj1[0x1]; 2528 u8 support_num_of_obj1[0x1]; 2529 u8 must_have_index2[0x1]; 2530 u8 support_index2[0x1]; 2531 u8 must_have_index1[0x1]; 2532 u8 support_index1[0x1]; 2533 u8 segment_type[0x10]; 2534 2535 u8 segment_name[4][0x20]; 2536 2537 u8 index1_name[4][0x20]; 2538 2539 u8 index2_name[4][0x20]; 2540 }; 2541 2542 struct mlx5_ifc_resource_dump_segment_header_bits { 2543 u8 length_dw[0x10]; 2544 u8 segment_type[0x10]; 2545 }; 2546 2547 struct mlx5_ifc_resource_dump_command_segment_bits { 2548 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2549 2550 u8 segment_called[0x10]; 2551 u8 vhca_id[0x10]; 2552 2553 u8 index1[0x20]; 2554 2555 u8 index2[0x20]; 2556 2557 u8 num_of_obj1[0x10]; 2558 u8 num_of_obj2[0x10]; 2559 }; 2560 2561 struct mlx5_ifc_resource_dump_error_segment_bits { 2562 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2563 2564 u8 reserved_at_20[0x10]; 2565 u8 syndrome_id[0x10]; 2566 2567 u8 reserved_at_40[0x40]; 2568 2569 u8 error[8][0x20]; 2570 }; 2571 2572 struct mlx5_ifc_resource_dump_info_segment_bits { 2573 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2574 2575 u8 reserved_at_20[0x18]; 2576 u8 dump_version[0x8]; 2577 2578 u8 hw_version[0x20]; 2579 2580 u8 fw_version[0x20]; 2581 }; 2582 2583 struct mlx5_ifc_resource_dump_menu_segment_bits { 2584 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2585 2586 u8 reserved_at_20[0x10]; 2587 u8 num_of_records[0x10]; 2588 2589 struct mlx5_ifc_resource_dump_menu_record_bits record[]; 2590 }; 2591 2592 struct mlx5_ifc_resource_dump_resource_segment_bits { 2593 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2594 2595 u8 reserved_at_20[0x20]; 2596 2597 u8 index1[0x20]; 2598 2599 u8 index2[0x20]; 2600 2601 u8 payload[][0x20]; 2602 }; 2603 2604 struct mlx5_ifc_resource_dump_terminate_segment_bits { 2605 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2606 }; 2607 2608 struct mlx5_ifc_menu_resource_dump_response_bits { 2609 struct mlx5_ifc_resource_dump_info_segment_bits info; 2610 struct mlx5_ifc_resource_dump_command_segment_bits cmd; 2611 struct mlx5_ifc_resource_dump_menu_segment_bits menu; 2612 struct mlx5_ifc_resource_dump_terminate_segment_bits terminate; 2613 }; 2614 2615 enum { 2616 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1, 2617 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2, 2618 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4, 2619 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8, 2620 }; 2621 2622 struct mlx5_ifc_modify_field_select_bits { 2623 u8 modify_field_select[0x20]; 2624 }; 2625 2626 struct mlx5_ifc_field_select_r_roce_np_bits { 2627 u8 field_select_r_roce_np[0x20]; 2628 }; 2629 2630 struct mlx5_ifc_field_select_r_roce_rp_bits { 2631 u8 field_select_r_roce_rp[0x20]; 2632 }; 2633 2634 enum { 2635 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4, 2636 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8, 2637 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10, 2638 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20, 2639 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40, 2640 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80, 2641 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100, 2642 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200, 2643 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400, 2644 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800, 2645 }; 2646 2647 struct mlx5_ifc_field_select_802_1qau_rp_bits { 2648 u8 field_select_8021qaurp[0x20]; 2649 }; 2650 2651 struct mlx5_ifc_phys_layer_recovery_cntrs_bits { 2652 u8 total_successful_recovery_events[0x20]; 2653 2654 u8 reserved_at_20[0x7a0]; 2655 }; 2656 2657 struct mlx5_ifc_phys_layer_cntrs_bits { 2658 u8 time_since_last_clear_high[0x20]; 2659 2660 u8 time_since_last_clear_low[0x20]; 2661 2662 u8 symbol_errors_high[0x20]; 2663 2664 u8 symbol_errors_low[0x20]; 2665 2666 u8 sync_headers_errors_high[0x20]; 2667 2668 u8 sync_headers_errors_low[0x20]; 2669 2670 u8 edpl_bip_errors_lane0_high[0x20]; 2671 2672 u8 edpl_bip_errors_lane0_low[0x20]; 2673 2674 u8 edpl_bip_errors_lane1_high[0x20]; 2675 2676 u8 edpl_bip_errors_lane1_low[0x20]; 2677 2678 u8 edpl_bip_errors_lane2_high[0x20]; 2679 2680 u8 edpl_bip_errors_lane2_low[0x20]; 2681 2682 u8 edpl_bip_errors_lane3_high[0x20]; 2683 2684 u8 edpl_bip_errors_lane3_low[0x20]; 2685 2686 u8 fc_fec_corrected_blocks_lane0_high[0x20]; 2687 2688 u8 fc_fec_corrected_blocks_lane0_low[0x20]; 2689 2690 u8 fc_fec_corrected_blocks_lane1_high[0x20]; 2691 2692 u8 fc_fec_corrected_blocks_lane1_low[0x20]; 2693 2694 u8 fc_fec_corrected_blocks_lane2_high[0x20]; 2695 2696 u8 fc_fec_corrected_blocks_lane2_low[0x20]; 2697 2698 u8 fc_fec_corrected_blocks_lane3_high[0x20]; 2699 2700 u8 fc_fec_corrected_blocks_lane3_low[0x20]; 2701 2702 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20]; 2703 2704 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20]; 2705 2706 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20]; 2707 2708 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20]; 2709 2710 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20]; 2711 2712 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20]; 2713 2714 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20]; 2715 2716 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20]; 2717 2718 u8 rs_fec_corrected_blocks_high[0x20]; 2719 2720 u8 rs_fec_corrected_blocks_low[0x20]; 2721 2722 u8 rs_fec_uncorrectable_blocks_high[0x20]; 2723 2724 u8 rs_fec_uncorrectable_blocks_low[0x20]; 2725 2726 u8 rs_fec_no_errors_blocks_high[0x20]; 2727 2728 u8 rs_fec_no_errors_blocks_low[0x20]; 2729 2730 u8 rs_fec_single_error_blocks_high[0x20]; 2731 2732 u8 rs_fec_single_error_blocks_low[0x20]; 2733 2734 u8 rs_fec_corrected_symbols_total_high[0x20]; 2735 2736 u8 rs_fec_corrected_symbols_total_low[0x20]; 2737 2738 u8 rs_fec_corrected_symbols_lane0_high[0x20]; 2739 2740 u8 rs_fec_corrected_symbols_lane0_low[0x20]; 2741 2742 u8 rs_fec_corrected_symbols_lane1_high[0x20]; 2743 2744 u8 rs_fec_corrected_symbols_lane1_low[0x20]; 2745 2746 u8 rs_fec_corrected_symbols_lane2_high[0x20]; 2747 2748 u8 rs_fec_corrected_symbols_lane2_low[0x20]; 2749 2750 u8 rs_fec_corrected_symbols_lane3_high[0x20]; 2751 2752 u8 rs_fec_corrected_symbols_lane3_low[0x20]; 2753 2754 u8 link_down_events[0x20]; 2755 2756 u8 successful_recovery_events[0x20]; 2757 2758 u8 reserved_at_640[0x180]; 2759 }; 2760 2761 struct mlx5_ifc_phys_layer_statistical_cntrs_bits { 2762 u8 time_since_last_clear_high[0x20]; 2763 2764 u8 time_since_last_clear_low[0x20]; 2765 2766 u8 phy_received_bits_high[0x20]; 2767 2768 u8 phy_received_bits_low[0x20]; 2769 2770 u8 phy_symbol_errors_high[0x20]; 2771 2772 u8 phy_symbol_errors_low[0x20]; 2773 2774 u8 phy_corrected_bits_high[0x20]; 2775 2776 u8 phy_corrected_bits_low[0x20]; 2777 2778 u8 phy_corrected_bits_lane0_high[0x20]; 2779 2780 u8 phy_corrected_bits_lane0_low[0x20]; 2781 2782 u8 phy_corrected_bits_lane1_high[0x20]; 2783 2784 u8 phy_corrected_bits_lane1_low[0x20]; 2785 2786 u8 phy_corrected_bits_lane2_high[0x20]; 2787 2788 u8 phy_corrected_bits_lane2_low[0x20]; 2789 2790 u8 phy_corrected_bits_lane3_high[0x20]; 2791 2792 u8 phy_corrected_bits_lane3_low[0x20]; 2793 2794 u8 reserved_at_200[0x5c0]; 2795 }; 2796 2797 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits { 2798 u8 symbol_error_counter[0x10]; 2799 2800 u8 link_error_recovery_counter[0x8]; 2801 2802 u8 link_downed_counter[0x8]; 2803 2804 u8 port_rcv_errors[0x10]; 2805 2806 u8 port_rcv_remote_physical_errors[0x10]; 2807 2808 u8 port_rcv_switch_relay_errors[0x10]; 2809 2810 u8 port_xmit_discards[0x10]; 2811 2812 u8 port_xmit_constraint_errors[0x8]; 2813 2814 u8 port_rcv_constraint_errors[0x8]; 2815 2816 u8 reserved_at_70[0x8]; 2817 2818 u8 link_overrun_errors[0x8]; 2819 2820 u8 reserved_at_80[0x10]; 2821 2822 u8 vl_15_dropped[0x10]; 2823 2824 u8 reserved_at_a0[0x80]; 2825 2826 u8 port_xmit_wait[0x20]; 2827 }; 2828 2829 struct mlx5_ifc_ib_ext_port_cntrs_grp_data_layout_bits { 2830 u8 reserved_at_0[0x300]; 2831 2832 u8 port_xmit_data_high[0x20]; 2833 2834 u8 port_xmit_data_low[0x20]; 2835 2836 u8 port_rcv_data_high[0x20]; 2837 2838 u8 port_rcv_data_low[0x20]; 2839 2840 u8 port_xmit_pkts_high[0x20]; 2841 2842 u8 port_xmit_pkts_low[0x20]; 2843 2844 u8 port_rcv_pkts_high[0x20]; 2845 2846 u8 port_rcv_pkts_low[0x20]; 2847 2848 u8 reserved_at_400[0x80]; 2849 2850 u8 port_unicast_xmit_pkts_high[0x20]; 2851 2852 u8 port_unicast_xmit_pkts_low[0x20]; 2853 2854 u8 port_multicast_xmit_pkts_high[0x20]; 2855 2856 u8 port_multicast_xmit_pkts_low[0x20]; 2857 2858 u8 port_unicast_rcv_pkts_high[0x20]; 2859 2860 u8 port_unicast_rcv_pkts_low[0x20]; 2861 2862 u8 port_multicast_rcv_pkts_high[0x20]; 2863 2864 u8 port_multicast_rcv_pkts_low[0x20]; 2865 2866 u8 reserved_at_580[0x240]; 2867 }; 2868 2869 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits { 2870 u8 transmit_queue_high[0x20]; 2871 2872 u8 transmit_queue_low[0x20]; 2873 2874 u8 no_buffer_discard_uc_high[0x20]; 2875 2876 u8 no_buffer_discard_uc_low[0x20]; 2877 2878 u8 reserved_at_80[0x740]; 2879 }; 2880 2881 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits { 2882 u8 wred_discard_high[0x20]; 2883 2884 u8 wred_discard_low[0x20]; 2885 2886 u8 ecn_marked_tc_high[0x20]; 2887 2888 u8 ecn_marked_tc_low[0x20]; 2889 2890 u8 reserved_at_80[0x740]; 2891 }; 2892 2893 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits { 2894 u8 rx_octets_high[0x20]; 2895 2896 u8 rx_octets_low[0x20]; 2897 2898 u8 reserved_at_40[0xc0]; 2899 2900 u8 rx_frames_high[0x20]; 2901 2902 u8 rx_frames_low[0x20]; 2903 2904 u8 tx_octets_high[0x20]; 2905 2906 u8 tx_octets_low[0x20]; 2907 2908 u8 reserved_at_180[0xc0]; 2909 2910 u8 tx_frames_high[0x20]; 2911 2912 u8 tx_frames_low[0x20]; 2913 2914 u8 rx_pause_high[0x20]; 2915 2916 u8 rx_pause_low[0x20]; 2917 2918 u8 rx_pause_duration_high[0x20]; 2919 2920 u8 rx_pause_duration_low[0x20]; 2921 2922 u8 tx_pause_high[0x20]; 2923 2924 u8 tx_pause_low[0x20]; 2925 2926 u8 tx_pause_duration_high[0x20]; 2927 2928 u8 tx_pause_duration_low[0x20]; 2929 2930 u8 rx_pause_transition_high[0x20]; 2931 2932 u8 rx_pause_transition_low[0x20]; 2933 2934 u8 rx_discards_high[0x20]; 2935 2936 u8 rx_discards_low[0x20]; 2937 2938 u8 device_stall_minor_watermark_cnt_high[0x20]; 2939 2940 u8 device_stall_minor_watermark_cnt_low[0x20]; 2941 2942 u8 device_stall_critical_watermark_cnt_high[0x20]; 2943 2944 u8 device_stall_critical_watermark_cnt_low[0x20]; 2945 2946 u8 reserved_at_480[0x340]; 2947 }; 2948 2949 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits { 2950 u8 port_transmit_wait_high[0x20]; 2951 2952 u8 port_transmit_wait_low[0x20]; 2953 2954 u8 reserved_at_40[0x100]; 2955 2956 u8 rx_buffer_almost_full_high[0x20]; 2957 2958 u8 rx_buffer_almost_full_low[0x20]; 2959 2960 u8 rx_buffer_full_high[0x20]; 2961 2962 u8 rx_buffer_full_low[0x20]; 2963 2964 u8 rx_icrc_encapsulated_high[0x20]; 2965 2966 u8 rx_icrc_encapsulated_low[0x20]; 2967 2968 u8 reserved_at_200[0x5c0]; 2969 }; 2970 2971 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits { 2972 u8 dot3stats_alignment_errors_high[0x20]; 2973 2974 u8 dot3stats_alignment_errors_low[0x20]; 2975 2976 u8 dot3stats_fcs_errors_high[0x20]; 2977 2978 u8 dot3stats_fcs_errors_low[0x20]; 2979 2980 u8 dot3stats_single_collision_frames_high[0x20]; 2981 2982 u8 dot3stats_single_collision_frames_low[0x20]; 2983 2984 u8 dot3stats_multiple_collision_frames_high[0x20]; 2985 2986 u8 dot3stats_multiple_collision_frames_low[0x20]; 2987 2988 u8 dot3stats_sqe_test_errors_high[0x20]; 2989 2990 u8 dot3stats_sqe_test_errors_low[0x20]; 2991 2992 u8 dot3stats_deferred_transmissions_high[0x20]; 2993 2994 u8 dot3stats_deferred_transmissions_low[0x20]; 2995 2996 u8 dot3stats_late_collisions_high[0x20]; 2997 2998 u8 dot3stats_late_collisions_low[0x20]; 2999 3000 u8 dot3stats_excessive_collisions_high[0x20]; 3001 3002 u8 dot3stats_excessive_collisions_low[0x20]; 3003 3004 u8 dot3stats_internal_mac_transmit_errors_high[0x20]; 3005 3006 u8 dot3stats_internal_mac_transmit_errors_low[0x20]; 3007 3008 u8 dot3stats_carrier_sense_errors_high[0x20]; 3009 3010 u8 dot3stats_carrier_sense_errors_low[0x20]; 3011 3012 u8 dot3stats_frame_too_longs_high[0x20]; 3013 3014 u8 dot3stats_frame_too_longs_low[0x20]; 3015 3016 u8 dot3stats_internal_mac_receive_errors_high[0x20]; 3017 3018 u8 dot3stats_internal_mac_receive_errors_low[0x20]; 3019 3020 u8 dot3stats_symbol_errors_high[0x20]; 3021 3022 u8 dot3stats_symbol_errors_low[0x20]; 3023 3024 u8 dot3control_in_unknown_opcodes_high[0x20]; 3025 3026 u8 dot3control_in_unknown_opcodes_low[0x20]; 3027 3028 u8 dot3in_pause_frames_high[0x20]; 3029 3030 u8 dot3in_pause_frames_low[0x20]; 3031 3032 u8 dot3out_pause_frames_high[0x20]; 3033 3034 u8 dot3out_pause_frames_low[0x20]; 3035 3036 u8 reserved_at_400[0x3c0]; 3037 }; 3038 3039 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits { 3040 u8 ether_stats_drop_events_high[0x20]; 3041 3042 u8 ether_stats_drop_events_low[0x20]; 3043 3044 u8 ether_stats_octets_high[0x20]; 3045 3046 u8 ether_stats_octets_low[0x20]; 3047 3048 u8 ether_stats_pkts_high[0x20]; 3049 3050 u8 ether_stats_pkts_low[0x20]; 3051 3052 u8 ether_stats_broadcast_pkts_high[0x20]; 3053 3054 u8 ether_stats_broadcast_pkts_low[0x20]; 3055 3056 u8 ether_stats_multicast_pkts_high[0x20]; 3057 3058 u8 ether_stats_multicast_pkts_low[0x20]; 3059 3060 u8 ether_stats_crc_align_errors_high[0x20]; 3061 3062 u8 ether_stats_crc_align_errors_low[0x20]; 3063 3064 u8 ether_stats_undersize_pkts_high[0x20]; 3065 3066 u8 ether_stats_undersize_pkts_low[0x20]; 3067 3068 u8 ether_stats_oversize_pkts_high[0x20]; 3069 3070 u8 ether_stats_oversize_pkts_low[0x20]; 3071 3072 u8 ether_stats_fragments_high[0x20]; 3073 3074 u8 ether_stats_fragments_low[0x20]; 3075 3076 u8 ether_stats_jabbers_high[0x20]; 3077 3078 u8 ether_stats_jabbers_low[0x20]; 3079 3080 u8 ether_stats_collisions_high[0x20]; 3081 3082 u8 ether_stats_collisions_low[0x20]; 3083 3084 u8 ether_stats_pkts64octets_high[0x20]; 3085 3086 u8 ether_stats_pkts64octets_low[0x20]; 3087 3088 u8 ether_stats_pkts65to127octets_high[0x20]; 3089 3090 u8 ether_stats_pkts65to127octets_low[0x20]; 3091 3092 u8 ether_stats_pkts128to255octets_high[0x20]; 3093 3094 u8 ether_stats_pkts128to255octets_low[0x20]; 3095 3096 u8 ether_stats_pkts256to511octets_high[0x20]; 3097 3098 u8 ether_stats_pkts256to511octets_low[0x20]; 3099 3100 u8 ether_stats_pkts512to1023octets_high[0x20]; 3101 3102 u8 ether_stats_pkts512to1023octets_low[0x20]; 3103 3104 u8 ether_stats_pkts1024to1518octets_high[0x20]; 3105 3106 u8 ether_stats_pkts1024to1518octets_low[0x20]; 3107 3108 u8 ether_stats_pkts1519to2047octets_high[0x20]; 3109 3110 u8 ether_stats_pkts1519to2047octets_low[0x20]; 3111 3112 u8 ether_stats_pkts2048to4095octets_high[0x20]; 3113 3114 u8 ether_stats_pkts2048to4095octets_low[0x20]; 3115 3116 u8 ether_stats_pkts4096to8191octets_high[0x20]; 3117 3118 u8 ether_stats_pkts4096to8191octets_low[0x20]; 3119 3120 u8 ether_stats_pkts8192to10239octets_high[0x20]; 3121 3122 u8 ether_stats_pkts8192to10239octets_low[0x20]; 3123 3124 u8 reserved_at_540[0x280]; 3125 }; 3126 3127 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits { 3128 u8 if_in_octets_high[0x20]; 3129 3130 u8 if_in_octets_low[0x20]; 3131 3132 u8 if_in_ucast_pkts_high[0x20]; 3133 3134 u8 if_in_ucast_pkts_low[0x20]; 3135 3136 u8 if_in_discards_high[0x20]; 3137 3138 u8 if_in_discards_low[0x20]; 3139 3140 u8 if_in_errors_high[0x20]; 3141 3142 u8 if_in_errors_low[0x20]; 3143 3144 u8 if_in_unknown_protos_high[0x20]; 3145 3146 u8 if_in_unknown_protos_low[0x20]; 3147 3148 u8 if_out_octets_high[0x20]; 3149 3150 u8 if_out_octets_low[0x20]; 3151 3152 u8 if_out_ucast_pkts_high[0x20]; 3153 3154 u8 if_out_ucast_pkts_low[0x20]; 3155 3156 u8 if_out_discards_high[0x20]; 3157 3158 u8 if_out_discards_low[0x20]; 3159 3160 u8 if_out_errors_high[0x20]; 3161 3162 u8 if_out_errors_low[0x20]; 3163 3164 u8 if_in_multicast_pkts_high[0x20]; 3165 3166 u8 if_in_multicast_pkts_low[0x20]; 3167 3168 u8 if_in_broadcast_pkts_high[0x20]; 3169 3170 u8 if_in_broadcast_pkts_low[0x20]; 3171 3172 u8 if_out_multicast_pkts_high[0x20]; 3173 3174 u8 if_out_multicast_pkts_low[0x20]; 3175 3176 u8 if_out_broadcast_pkts_high[0x20]; 3177 3178 u8 if_out_broadcast_pkts_low[0x20]; 3179 3180 u8 reserved_at_340[0x480]; 3181 }; 3182 3183 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits { 3184 u8 a_frames_transmitted_ok_high[0x20]; 3185 3186 u8 a_frames_transmitted_ok_low[0x20]; 3187 3188 u8 a_frames_received_ok_high[0x20]; 3189 3190 u8 a_frames_received_ok_low[0x20]; 3191 3192 u8 a_frame_check_sequence_errors_high[0x20]; 3193 3194 u8 a_frame_check_sequence_errors_low[0x20]; 3195 3196 u8 a_alignment_errors_high[0x20]; 3197 3198 u8 a_alignment_errors_low[0x20]; 3199 3200 u8 a_octets_transmitted_ok_high[0x20]; 3201 3202 u8 a_octets_transmitted_ok_low[0x20]; 3203 3204 u8 a_octets_received_ok_high[0x20]; 3205 3206 u8 a_octets_received_ok_low[0x20]; 3207 3208 u8 a_multicast_frames_xmitted_ok_high[0x20]; 3209 3210 u8 a_multicast_frames_xmitted_ok_low[0x20]; 3211 3212 u8 a_broadcast_frames_xmitted_ok_high[0x20]; 3213 3214 u8 a_broadcast_frames_xmitted_ok_low[0x20]; 3215 3216 u8 a_multicast_frames_received_ok_high[0x20]; 3217 3218 u8 a_multicast_frames_received_ok_low[0x20]; 3219 3220 u8 a_broadcast_frames_received_ok_high[0x20]; 3221 3222 u8 a_broadcast_frames_received_ok_low[0x20]; 3223 3224 u8 a_in_range_length_errors_high[0x20]; 3225 3226 u8 a_in_range_length_errors_low[0x20]; 3227 3228 u8 a_out_of_range_length_field_high[0x20]; 3229 3230 u8 a_out_of_range_length_field_low[0x20]; 3231 3232 u8 a_frame_too_long_errors_high[0x20]; 3233 3234 u8 a_frame_too_long_errors_low[0x20]; 3235 3236 u8 a_symbol_error_during_carrier_high[0x20]; 3237 3238 u8 a_symbol_error_during_carrier_low[0x20]; 3239 3240 u8 a_mac_control_frames_transmitted_high[0x20]; 3241 3242 u8 a_mac_control_frames_transmitted_low[0x20]; 3243 3244 u8 a_mac_control_frames_received_high[0x20]; 3245 3246 u8 a_mac_control_frames_received_low[0x20]; 3247 3248 u8 a_unsupported_opcodes_received_high[0x20]; 3249 3250 u8 a_unsupported_opcodes_received_low[0x20]; 3251 3252 u8 a_pause_mac_ctrl_frames_received_high[0x20]; 3253 3254 u8 a_pause_mac_ctrl_frames_received_low[0x20]; 3255 3256 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20]; 3257 3258 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20]; 3259 3260 u8 reserved_at_4c0[0x300]; 3261 }; 3262 3263 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits { 3264 u8 life_time_counter_high[0x20]; 3265 3266 u8 life_time_counter_low[0x20]; 3267 3268 u8 rx_errors[0x20]; 3269 3270 u8 tx_errors[0x20]; 3271 3272 u8 l0_to_recovery_eieos[0x20]; 3273 3274 u8 l0_to_recovery_ts[0x20]; 3275 3276 u8 l0_to_recovery_framing[0x20]; 3277 3278 u8 l0_to_recovery_retrain[0x20]; 3279 3280 u8 crc_error_dllp[0x20]; 3281 3282 u8 crc_error_tlp[0x20]; 3283 3284 u8 tx_overflow_buffer_pkt_high[0x20]; 3285 3286 u8 tx_overflow_buffer_pkt_low[0x20]; 3287 3288 u8 outbound_stalled_reads[0x20]; 3289 3290 u8 outbound_stalled_writes[0x20]; 3291 3292 u8 outbound_stalled_reads_events[0x20]; 3293 3294 u8 outbound_stalled_writes_events[0x20]; 3295 3296 u8 reserved_at_200[0x5c0]; 3297 }; 3298 3299 struct mlx5_ifc_cmd_inter_comp_event_bits { 3300 u8 command_completion_vector[0x20]; 3301 3302 u8 reserved_at_20[0xc0]; 3303 }; 3304 3305 struct mlx5_ifc_stall_vl_event_bits { 3306 u8 reserved_at_0[0x18]; 3307 u8 port_num[0x1]; 3308 u8 reserved_at_19[0x3]; 3309 u8 vl[0x4]; 3310 3311 u8 reserved_at_20[0xa0]; 3312 }; 3313 3314 struct mlx5_ifc_db_bf_congestion_event_bits { 3315 u8 event_subtype[0x8]; 3316 u8 reserved_at_8[0x8]; 3317 u8 congestion_level[0x8]; 3318 u8 reserved_at_18[0x8]; 3319 3320 u8 reserved_at_20[0xa0]; 3321 }; 3322 3323 struct mlx5_ifc_gpio_event_bits { 3324 u8 reserved_at_0[0x60]; 3325 3326 u8 gpio_event_hi[0x20]; 3327 3328 u8 gpio_event_lo[0x20]; 3329 3330 u8 reserved_at_a0[0x40]; 3331 }; 3332 3333 struct mlx5_ifc_port_state_change_event_bits { 3334 u8 reserved_at_0[0x40]; 3335 3336 u8 port_num[0x4]; 3337 u8 reserved_at_44[0x1c]; 3338 3339 u8 reserved_at_60[0x80]; 3340 }; 3341 3342 struct mlx5_ifc_dropped_packet_logged_bits { 3343 u8 reserved_at_0[0xe0]; 3344 }; 3345 3346 struct mlx5_ifc_nic_cap_reg_bits { 3347 u8 reserved_at_0[0x1a]; 3348 u8 vhca_icm_ctrl[0x1]; 3349 u8 reserved_at_1b[0x5]; 3350 3351 u8 reserved_at_20[0x60]; 3352 }; 3353 3354 struct mlx5_ifc_default_timeout_bits { 3355 u8 to_multiplier[0x3]; 3356 u8 reserved_at_3[0x9]; 3357 u8 to_value[0x14]; 3358 }; 3359 3360 struct mlx5_ifc_dtor_reg_bits { 3361 u8 reserved_at_0[0x20]; 3362 3363 struct mlx5_ifc_default_timeout_bits pcie_toggle_to; 3364 3365 u8 reserved_at_40[0x60]; 3366 3367 struct mlx5_ifc_default_timeout_bits health_poll_to; 3368 3369 struct mlx5_ifc_default_timeout_bits full_crdump_to; 3370 3371 struct mlx5_ifc_default_timeout_bits fw_reset_to; 3372 3373 struct mlx5_ifc_default_timeout_bits flush_on_err_to; 3374 3375 struct mlx5_ifc_default_timeout_bits pci_sync_update_to; 3376 3377 struct mlx5_ifc_default_timeout_bits tear_down_to; 3378 3379 struct mlx5_ifc_default_timeout_bits fsm_reactivate_to; 3380 3381 struct mlx5_ifc_default_timeout_bits reclaim_pages_to; 3382 3383 struct mlx5_ifc_default_timeout_bits reclaim_vfs_pages_to; 3384 3385 struct mlx5_ifc_default_timeout_bits reset_unload_to; 3386 3387 u8 reserved_at_1c0[0x20]; 3388 }; 3389 3390 struct mlx5_ifc_vhca_icm_ctrl_reg_bits { 3391 u8 vhca_id_valid[0x1]; 3392 u8 reserved_at_1[0xf]; 3393 u8 vhca_id[0x10]; 3394 3395 u8 reserved_at_20[0xa0]; 3396 3397 u8 cur_alloc_icm[0x20]; 3398 3399 u8 reserved_at_e0[0x120]; 3400 }; 3401 3402 enum { 3403 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1, 3404 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2, 3405 }; 3406 3407 struct mlx5_ifc_cq_error_bits { 3408 u8 reserved_at_0[0x8]; 3409 u8 cqn[0x18]; 3410 3411 u8 reserved_at_20[0x20]; 3412 3413 u8 reserved_at_40[0x18]; 3414 u8 syndrome[0x8]; 3415 3416 u8 reserved_at_60[0x80]; 3417 }; 3418 3419 struct mlx5_ifc_rdma_page_fault_event_bits { 3420 u8 bytes_committed[0x20]; 3421 3422 u8 r_key[0x20]; 3423 3424 u8 reserved_at_40[0x10]; 3425 u8 packet_len[0x10]; 3426 3427 u8 rdma_op_len[0x20]; 3428 3429 u8 rdma_va[0x40]; 3430 3431 u8 reserved_at_c0[0x5]; 3432 u8 rdma[0x1]; 3433 u8 write[0x1]; 3434 u8 requestor[0x1]; 3435 u8 qp_number[0x18]; 3436 }; 3437 3438 struct mlx5_ifc_wqe_associated_page_fault_event_bits { 3439 u8 bytes_committed[0x20]; 3440 3441 u8 reserved_at_20[0x10]; 3442 u8 wqe_index[0x10]; 3443 3444 u8 reserved_at_40[0x10]; 3445 u8 len[0x10]; 3446 3447 u8 reserved_at_60[0x60]; 3448 3449 u8 reserved_at_c0[0x5]; 3450 u8 rdma[0x1]; 3451 u8 write_read[0x1]; 3452 u8 requestor[0x1]; 3453 u8 qpn[0x18]; 3454 }; 3455 3456 struct mlx5_ifc_qp_events_bits { 3457 u8 reserved_at_0[0xa0]; 3458 3459 u8 type[0x8]; 3460 u8 reserved_at_a8[0x18]; 3461 3462 u8 reserved_at_c0[0x8]; 3463 u8 qpn_rqn_sqn[0x18]; 3464 }; 3465 3466 struct mlx5_ifc_dct_events_bits { 3467 u8 reserved_at_0[0xc0]; 3468 3469 u8 reserved_at_c0[0x8]; 3470 u8 dct_number[0x18]; 3471 }; 3472 3473 struct mlx5_ifc_comp_event_bits { 3474 u8 reserved_at_0[0xc0]; 3475 3476 u8 reserved_at_c0[0x8]; 3477 u8 cq_number[0x18]; 3478 }; 3479 3480 enum { 3481 MLX5_QPC_STATE_RST = 0x0, 3482 MLX5_QPC_STATE_INIT = 0x1, 3483 MLX5_QPC_STATE_RTR = 0x2, 3484 MLX5_QPC_STATE_RTS = 0x3, 3485 MLX5_QPC_STATE_SQER = 0x4, 3486 MLX5_QPC_STATE_ERR = 0x6, 3487 MLX5_QPC_STATE_SQD = 0x7, 3488 MLX5_QPC_STATE_SUSPENDED = 0x9, 3489 }; 3490 3491 enum { 3492 MLX5_QPC_ST_RC = 0x0, 3493 MLX5_QPC_ST_UC = 0x1, 3494 MLX5_QPC_ST_UD = 0x2, 3495 MLX5_QPC_ST_XRC = 0x3, 3496 MLX5_QPC_ST_DCI = 0x5, 3497 MLX5_QPC_ST_QP0 = 0x7, 3498 MLX5_QPC_ST_QP1 = 0x8, 3499 MLX5_QPC_ST_RAW_DATAGRAM = 0x9, 3500 MLX5_QPC_ST_REG_UMR = 0xc, 3501 }; 3502 3503 enum { 3504 MLX5_QPC_PM_STATE_ARMED = 0x0, 3505 MLX5_QPC_PM_STATE_REARM = 0x1, 3506 MLX5_QPC_PM_STATE_RESERVED = 0x2, 3507 MLX5_QPC_PM_STATE_MIGRATED = 0x3, 3508 }; 3509 3510 enum { 3511 MLX5_QPC_OFFLOAD_TYPE_RNDV = 0x1, 3512 }; 3513 3514 enum { 3515 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0, 3516 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1, 3517 }; 3518 3519 enum { 3520 MLX5_QPC_MTU_256_BYTES = 0x1, 3521 MLX5_QPC_MTU_512_BYTES = 0x2, 3522 MLX5_QPC_MTU_1K_BYTES = 0x3, 3523 MLX5_QPC_MTU_2K_BYTES = 0x4, 3524 MLX5_QPC_MTU_4K_BYTES = 0x5, 3525 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7, 3526 }; 3527 3528 enum { 3529 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1, 3530 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2, 3531 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3, 3532 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4, 3533 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5, 3534 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6, 3535 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7, 3536 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8, 3537 }; 3538 3539 enum { 3540 MLX5_QPC_CS_REQ_DISABLE = 0x0, 3541 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11, 3542 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22, 3543 }; 3544 3545 enum { 3546 MLX5_QPC_CS_RES_DISABLE = 0x0, 3547 MLX5_QPC_CS_RES_UP_TO_32B = 0x1, 3548 MLX5_QPC_CS_RES_UP_TO_64B = 0x2, 3549 }; 3550 3551 enum { 3552 MLX5_TIMESTAMP_FORMAT_FREE_RUNNING = 0x0, 3553 MLX5_TIMESTAMP_FORMAT_DEFAULT = 0x1, 3554 MLX5_TIMESTAMP_FORMAT_REAL_TIME = 0x2, 3555 }; 3556 3557 struct mlx5_ifc_qpc_bits { 3558 u8 state[0x4]; 3559 u8 lag_tx_port_affinity[0x4]; 3560 u8 st[0x8]; 3561 u8 reserved_at_10[0x2]; 3562 u8 isolate_vl_tc[0x1]; 3563 u8 pm_state[0x2]; 3564 u8 reserved_at_15[0x1]; 3565 u8 req_e2e_credit_mode[0x2]; 3566 u8 offload_type[0x4]; 3567 u8 end_padding_mode[0x2]; 3568 u8 reserved_at_1e[0x2]; 3569 3570 u8 wq_signature[0x1]; 3571 u8 block_lb_mc[0x1]; 3572 u8 atomic_like_write_en[0x1]; 3573 u8 latency_sensitive[0x1]; 3574 u8 reserved_at_24[0x1]; 3575 u8 drain_sigerr[0x1]; 3576 u8 reserved_at_26[0x1]; 3577 u8 dp_ordering_force[0x1]; 3578 u8 pd[0x18]; 3579 3580 u8 mtu[0x3]; 3581 u8 log_msg_max[0x5]; 3582 u8 reserved_at_48[0x1]; 3583 u8 log_rq_size[0x4]; 3584 u8 log_rq_stride[0x3]; 3585 u8 no_sq[0x1]; 3586 u8 log_sq_size[0x4]; 3587 u8 reserved_at_55[0x1]; 3588 u8 retry_mode[0x2]; 3589 u8 ts_format[0x2]; 3590 u8 reserved_at_5a[0x1]; 3591 u8 rlky[0x1]; 3592 u8 ulp_stateless_offload_mode[0x4]; 3593 3594 u8 counter_set_id[0x8]; 3595 u8 uar_page[0x18]; 3596 3597 u8 reserved_at_80[0x8]; 3598 u8 user_index[0x18]; 3599 3600 u8 reserved_at_a0[0x3]; 3601 u8 log_page_size[0x5]; 3602 u8 remote_qpn[0x18]; 3603 3604 struct mlx5_ifc_ads_bits primary_address_path; 3605 3606 struct mlx5_ifc_ads_bits secondary_address_path; 3607 3608 u8 log_ack_req_freq[0x4]; 3609 u8 reserved_at_384[0x4]; 3610 u8 log_sra_max[0x3]; 3611 u8 reserved_at_38b[0x2]; 3612 u8 retry_count[0x3]; 3613 u8 rnr_retry[0x3]; 3614 u8 reserved_at_393[0x1]; 3615 u8 fre[0x1]; 3616 u8 cur_rnr_retry[0x3]; 3617 u8 cur_retry_count[0x3]; 3618 u8 reserved_at_39b[0x5]; 3619 3620 u8 reserved_at_3a0[0x20]; 3621 3622 u8 reserved_at_3c0[0x8]; 3623 u8 next_send_psn[0x18]; 3624 3625 u8 reserved_at_3e0[0x3]; 3626 u8 log_num_dci_stream_channels[0x5]; 3627 u8 cqn_snd[0x18]; 3628 3629 u8 reserved_at_400[0x3]; 3630 u8 log_num_dci_errored_streams[0x5]; 3631 u8 deth_sqpn[0x18]; 3632 3633 u8 reserved_at_420[0x20]; 3634 3635 u8 reserved_at_440[0x8]; 3636 u8 last_acked_psn[0x18]; 3637 3638 u8 reserved_at_460[0x8]; 3639 u8 ssn[0x18]; 3640 3641 u8 reserved_at_480[0x8]; 3642 u8 log_rra_max[0x3]; 3643 u8 reserved_at_48b[0x1]; 3644 u8 atomic_mode[0x4]; 3645 u8 rre[0x1]; 3646 u8 rwe[0x1]; 3647 u8 rae[0x1]; 3648 u8 reserved_at_493[0x1]; 3649 u8 page_offset[0x6]; 3650 u8 reserved_at_49a[0x2]; 3651 u8 dp_ordering_1[0x1]; 3652 u8 cd_slave_receive[0x1]; 3653 u8 cd_slave_send[0x1]; 3654 u8 cd_master[0x1]; 3655 3656 u8 reserved_at_4a0[0x3]; 3657 u8 min_rnr_nak[0x5]; 3658 u8 next_rcv_psn[0x18]; 3659 3660 u8 reserved_at_4c0[0x8]; 3661 u8 xrcd[0x18]; 3662 3663 u8 reserved_at_4e0[0x8]; 3664 u8 cqn_rcv[0x18]; 3665 3666 u8 dbr_addr[0x40]; 3667 3668 u8 q_key[0x20]; 3669 3670 u8 reserved_at_560[0x5]; 3671 u8 rq_type[0x3]; 3672 u8 srqn_rmpn_xrqn[0x18]; 3673 3674 u8 reserved_at_580[0x8]; 3675 u8 rmsn[0x18]; 3676 3677 u8 hw_sq_wqebb_counter[0x10]; 3678 u8 sw_sq_wqebb_counter[0x10]; 3679 3680 u8 hw_rq_counter[0x20]; 3681 3682 u8 sw_rq_counter[0x20]; 3683 3684 u8 reserved_at_600[0x20]; 3685 3686 u8 reserved_at_620[0xf]; 3687 u8 cgs[0x1]; 3688 u8 cs_req[0x8]; 3689 u8 cs_res[0x8]; 3690 3691 u8 dc_access_key[0x40]; 3692 3693 u8 reserved_at_680[0x3]; 3694 u8 dbr_umem_valid[0x1]; 3695 3696 u8 reserved_at_684[0xbc]; 3697 }; 3698 3699 struct mlx5_ifc_roce_addr_layout_bits { 3700 u8 source_l3_address[16][0x8]; 3701 3702 u8 reserved_at_80[0x3]; 3703 u8 vlan_valid[0x1]; 3704 u8 vlan_id[0xc]; 3705 u8 source_mac_47_32[0x10]; 3706 3707 u8 source_mac_31_0[0x20]; 3708 3709 u8 reserved_at_c0[0x14]; 3710 u8 roce_l3_type[0x4]; 3711 u8 roce_version[0x8]; 3712 3713 u8 reserved_at_e0[0x20]; 3714 }; 3715 3716 struct mlx5_ifc_crypto_cap_bits { 3717 u8 reserved_at_0[0x3]; 3718 u8 synchronize_dek[0x1]; 3719 u8 int_kek_manual[0x1]; 3720 u8 int_kek_auto[0x1]; 3721 u8 reserved_at_6[0x1a]; 3722 3723 u8 reserved_at_20[0x3]; 3724 u8 log_dek_max_alloc[0x5]; 3725 u8 reserved_at_28[0x3]; 3726 u8 log_max_num_deks[0x5]; 3727 u8 reserved_at_30[0x10]; 3728 3729 u8 reserved_at_40[0x20]; 3730 3731 u8 reserved_at_60[0x3]; 3732 u8 log_dek_granularity[0x5]; 3733 u8 reserved_at_68[0x3]; 3734 u8 log_max_num_int_kek[0x5]; 3735 u8 sw_wrapped_dek[0x10]; 3736 3737 u8 reserved_at_80[0x780]; 3738 }; 3739 3740 struct mlx5_ifc_shampo_cap_bits { 3741 u8 reserved_at_0[0x3]; 3742 u8 shampo_log_max_reservation_size[0x5]; 3743 u8 reserved_at_8[0x3]; 3744 u8 shampo_log_min_reservation_size[0x5]; 3745 u8 shampo_min_mss_size[0x10]; 3746 3747 u8 shampo_header_split[0x1]; 3748 u8 shampo_header_split_data_merge[0x1]; 3749 u8 reserved_at_22[0x1]; 3750 u8 shampo_log_max_headers_entry_size[0x5]; 3751 u8 reserved_at_28[0x18]; 3752 3753 u8 reserved_at_40[0x7c0]; 3754 }; 3755 3756 union mlx5_ifc_hca_cap_union_bits { 3757 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap; 3758 struct mlx5_ifc_cmd_hca_cap_2_bits cmd_hca_cap_2; 3759 struct mlx5_ifc_odp_cap_bits odp_cap; 3760 struct mlx5_ifc_atomic_caps_bits atomic_caps; 3761 struct mlx5_ifc_roce_cap_bits roce_cap; 3762 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps; 3763 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap; 3764 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap; 3765 struct mlx5_ifc_wqe_based_flow_table_cap_bits wqe_based_flow_table_cap; 3766 struct mlx5_ifc_esw_cap_bits esw_cap; 3767 struct mlx5_ifc_e_switch_cap_bits e_switch_cap; 3768 struct mlx5_ifc_port_selection_cap_bits port_selection_cap; 3769 struct mlx5_ifc_qos_cap_bits qos_cap; 3770 struct mlx5_ifc_debug_cap_bits debug_cap; 3771 struct mlx5_ifc_fpga_cap_bits fpga_cap; 3772 struct mlx5_ifc_tls_cap_bits tls_cap; 3773 struct mlx5_ifc_device_mem_cap_bits device_mem_cap; 3774 struct mlx5_ifc_virtio_emulation_cap_bits virtio_emulation_cap; 3775 struct mlx5_ifc_macsec_cap_bits macsec_cap; 3776 struct mlx5_ifc_crypto_cap_bits crypto_cap; 3777 struct mlx5_ifc_ipsec_cap_bits ipsec_cap; 3778 u8 reserved_at_0[0x8000]; 3779 }; 3780 3781 enum { 3782 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1, 3783 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2, 3784 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4, 3785 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8, 3786 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT = 0x10, 3787 MLX5_FLOW_CONTEXT_ACTION_DECAP = 0x20, 3788 MLX5_FLOW_CONTEXT_ACTION_MOD_HDR = 0x40, 3789 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP = 0x80, 3790 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100, 3791 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2 = 0x400, 3792 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2 = 0x800, 3793 MLX5_FLOW_CONTEXT_ACTION_CRYPTO_DECRYPT = 0x1000, 3794 MLX5_FLOW_CONTEXT_ACTION_CRYPTO_ENCRYPT = 0x2000, 3795 MLX5_FLOW_CONTEXT_ACTION_EXECUTE_ASO = 0x4000, 3796 }; 3797 3798 enum { 3799 MLX5_FLOW_CONTEXT_FLOW_SOURCE_ANY_VPORT = 0x0, 3800 MLX5_FLOW_CONTEXT_FLOW_SOURCE_UPLINK = 0x1, 3801 MLX5_FLOW_CONTEXT_FLOW_SOURCE_LOCAL_VPORT = 0x2, 3802 }; 3803 3804 enum { 3805 MLX5_FLOW_CONTEXT_ENCRYPT_DECRYPT_TYPE_IPSEC = 0x0, 3806 MLX5_FLOW_CONTEXT_ENCRYPT_DECRYPT_TYPE_MACSEC = 0x1, 3807 }; 3808 3809 struct mlx5_ifc_vlan_bits { 3810 u8 ethtype[0x10]; 3811 u8 prio[0x3]; 3812 u8 cfi[0x1]; 3813 u8 vid[0xc]; 3814 }; 3815 3816 enum { 3817 MLX5_FLOW_METER_COLOR_RED = 0x0, 3818 MLX5_FLOW_METER_COLOR_YELLOW = 0x1, 3819 MLX5_FLOW_METER_COLOR_GREEN = 0x2, 3820 MLX5_FLOW_METER_COLOR_UNDEFINED = 0x3, 3821 }; 3822 3823 enum { 3824 MLX5_EXE_ASO_FLOW_METER = 0x2, 3825 }; 3826 3827 struct mlx5_ifc_exe_aso_ctrl_flow_meter_bits { 3828 u8 return_reg_id[0x4]; 3829 u8 aso_type[0x4]; 3830 u8 reserved_at_8[0x14]; 3831 u8 action[0x1]; 3832 u8 init_color[0x2]; 3833 u8 meter_id[0x1]; 3834 }; 3835 3836 union mlx5_ifc_exe_aso_ctrl { 3837 struct mlx5_ifc_exe_aso_ctrl_flow_meter_bits exe_aso_ctrl_flow_meter; 3838 }; 3839 3840 struct mlx5_ifc_execute_aso_bits { 3841 u8 valid[0x1]; 3842 u8 reserved_at_1[0x7]; 3843 u8 aso_object_id[0x18]; 3844 3845 union mlx5_ifc_exe_aso_ctrl exe_aso_ctrl; 3846 }; 3847 3848 struct mlx5_ifc_flow_context_bits { 3849 struct mlx5_ifc_vlan_bits push_vlan; 3850 3851 u8 group_id[0x20]; 3852 3853 u8 reserved_at_40[0x8]; 3854 u8 flow_tag[0x18]; 3855 3856 u8 reserved_at_60[0x10]; 3857 u8 action[0x10]; 3858 3859 u8 extended_destination[0x1]; 3860 u8 uplink_hairpin_en[0x1]; 3861 u8 flow_source[0x2]; 3862 u8 encrypt_decrypt_type[0x4]; 3863 u8 destination_list_size[0x18]; 3864 3865 u8 reserved_at_a0[0x8]; 3866 u8 flow_counter_list_size[0x18]; 3867 3868 u8 packet_reformat_id[0x20]; 3869 3870 u8 modify_header_id[0x20]; 3871 3872 struct mlx5_ifc_vlan_bits push_vlan_2; 3873 3874 u8 encrypt_decrypt_obj_id[0x20]; 3875 u8 reserved_at_140[0xc0]; 3876 3877 struct mlx5_ifc_fte_match_param_bits match_value; 3878 3879 struct mlx5_ifc_execute_aso_bits execute_aso[4]; 3880 3881 u8 reserved_at_1300[0x500]; 3882 3883 union mlx5_ifc_dest_format_flow_counter_list_auto_bits destination[]; 3884 }; 3885 3886 enum { 3887 MLX5_XRC_SRQC_STATE_GOOD = 0x0, 3888 MLX5_XRC_SRQC_STATE_ERROR = 0x1, 3889 }; 3890 3891 struct mlx5_ifc_xrc_srqc_bits { 3892 u8 state[0x4]; 3893 u8 log_xrc_srq_size[0x4]; 3894 u8 reserved_at_8[0x18]; 3895 3896 u8 wq_signature[0x1]; 3897 u8 cont_srq[0x1]; 3898 u8 reserved_at_22[0x1]; 3899 u8 rlky[0x1]; 3900 u8 basic_cyclic_rcv_wqe[0x1]; 3901 u8 log_rq_stride[0x3]; 3902 u8 xrcd[0x18]; 3903 3904 u8 page_offset[0x6]; 3905 u8 reserved_at_46[0x1]; 3906 u8 dbr_umem_valid[0x1]; 3907 u8 cqn[0x18]; 3908 3909 u8 reserved_at_60[0x20]; 3910 3911 u8 user_index_equal_xrc_srqn[0x1]; 3912 u8 reserved_at_81[0x1]; 3913 u8 log_page_size[0x6]; 3914 u8 user_index[0x18]; 3915 3916 u8 reserved_at_a0[0x20]; 3917 3918 u8 reserved_at_c0[0x8]; 3919 u8 pd[0x18]; 3920 3921 u8 lwm[0x10]; 3922 u8 wqe_cnt[0x10]; 3923 3924 u8 reserved_at_100[0x40]; 3925 3926 u8 db_record_addr_h[0x20]; 3927 3928 u8 db_record_addr_l[0x1e]; 3929 u8 reserved_at_17e[0x2]; 3930 3931 u8 reserved_at_180[0x80]; 3932 }; 3933 3934 struct mlx5_ifc_vnic_diagnostic_statistics_bits { 3935 u8 counter_error_queues[0x20]; 3936 3937 u8 total_error_queues[0x20]; 3938 3939 u8 send_queue_priority_update_flow[0x20]; 3940 3941 u8 reserved_at_60[0x20]; 3942 3943 u8 nic_receive_steering_discard[0x40]; 3944 3945 u8 receive_discard_vport_down[0x40]; 3946 3947 u8 transmit_discard_vport_down[0x40]; 3948 3949 u8 async_eq_overrun[0x20]; 3950 3951 u8 comp_eq_overrun[0x20]; 3952 3953 u8 reserved_at_180[0x20]; 3954 3955 u8 invalid_command[0x20]; 3956 3957 u8 quota_exceeded_command[0x20]; 3958 3959 u8 internal_rq_out_of_buffer[0x20]; 3960 3961 u8 cq_overrun[0x20]; 3962 3963 u8 eth_wqe_too_small[0x20]; 3964 3965 u8 reserved_at_220[0xc0]; 3966 3967 u8 generated_pkt_steering_fail[0x40]; 3968 3969 u8 handled_pkt_steering_fail[0x40]; 3970 3971 u8 reserved_at_360[0xc80]; 3972 }; 3973 3974 struct mlx5_ifc_traffic_counter_bits { 3975 u8 packets[0x40]; 3976 3977 u8 octets[0x40]; 3978 }; 3979 3980 struct mlx5_ifc_tisc_bits { 3981 u8 strict_lag_tx_port_affinity[0x1]; 3982 u8 tls_en[0x1]; 3983 u8 reserved_at_2[0x2]; 3984 u8 lag_tx_port_affinity[0x04]; 3985 3986 u8 reserved_at_8[0x4]; 3987 u8 prio[0x4]; 3988 u8 reserved_at_10[0x10]; 3989 3990 u8 reserved_at_20[0x100]; 3991 3992 u8 reserved_at_120[0x8]; 3993 u8 transport_domain[0x18]; 3994 3995 u8 reserved_at_140[0x8]; 3996 u8 underlay_qpn[0x18]; 3997 3998 u8 reserved_at_160[0x8]; 3999 u8 pd[0x18]; 4000 4001 u8 reserved_at_180[0x380]; 4002 }; 4003 4004 enum { 4005 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0, 4006 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1, 4007 }; 4008 4009 enum { 4010 MLX5_TIRC_PACKET_MERGE_MASK_IPV4_LRO = BIT(0), 4011 MLX5_TIRC_PACKET_MERGE_MASK_IPV6_LRO = BIT(1), 4012 }; 4013 4014 enum { 4015 MLX5_RX_HASH_FN_NONE = 0x0, 4016 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1, 4017 MLX5_RX_HASH_FN_TOEPLITZ = 0x2, 4018 }; 4019 4020 enum { 4021 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST = 0x1, 4022 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST = 0x2, 4023 }; 4024 4025 struct mlx5_ifc_tirc_bits { 4026 u8 reserved_at_0[0x20]; 4027 4028 u8 disp_type[0x4]; 4029 u8 tls_en[0x1]; 4030 u8 reserved_at_25[0x1b]; 4031 4032 u8 reserved_at_40[0x40]; 4033 4034 u8 reserved_at_80[0x4]; 4035 u8 lro_timeout_period_usecs[0x10]; 4036 u8 packet_merge_mask[0x4]; 4037 u8 lro_max_ip_payload_size[0x8]; 4038 4039 u8 reserved_at_a0[0x40]; 4040 4041 u8 reserved_at_e0[0x8]; 4042 u8 inline_rqn[0x18]; 4043 4044 u8 rx_hash_symmetric[0x1]; 4045 u8 reserved_at_101[0x1]; 4046 u8 tunneled_offload_en[0x1]; 4047 u8 reserved_at_103[0x5]; 4048 u8 indirect_table[0x18]; 4049 4050 u8 rx_hash_fn[0x4]; 4051 u8 reserved_at_124[0x2]; 4052 u8 self_lb_block[0x2]; 4053 u8 transport_domain[0x18]; 4054 4055 u8 rx_hash_toeplitz_key[10][0x20]; 4056 4057 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer; 4058 4059 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner; 4060 4061 u8 reserved_at_2c0[0x4c0]; 4062 }; 4063 4064 enum { 4065 MLX5_SRQC_STATE_GOOD = 0x0, 4066 MLX5_SRQC_STATE_ERROR = 0x1, 4067 }; 4068 4069 struct mlx5_ifc_srqc_bits { 4070 u8 state[0x4]; 4071 u8 log_srq_size[0x4]; 4072 u8 reserved_at_8[0x18]; 4073 4074 u8 wq_signature[0x1]; 4075 u8 cont_srq[0x1]; 4076 u8 reserved_at_22[0x1]; 4077 u8 rlky[0x1]; 4078 u8 reserved_at_24[0x1]; 4079 u8 log_rq_stride[0x3]; 4080 u8 xrcd[0x18]; 4081 4082 u8 page_offset[0x6]; 4083 u8 reserved_at_46[0x2]; 4084 u8 cqn[0x18]; 4085 4086 u8 reserved_at_60[0x20]; 4087 4088 u8 reserved_at_80[0x2]; 4089 u8 log_page_size[0x6]; 4090 u8 reserved_at_88[0x18]; 4091 4092 u8 reserved_at_a0[0x20]; 4093 4094 u8 reserved_at_c0[0x8]; 4095 u8 pd[0x18]; 4096 4097 u8 lwm[0x10]; 4098 u8 wqe_cnt[0x10]; 4099 4100 u8 reserved_at_100[0x40]; 4101 4102 u8 dbr_addr[0x40]; 4103 4104 u8 reserved_at_180[0x80]; 4105 }; 4106 4107 enum { 4108 MLX5_SQC_STATE_RST = 0x0, 4109 MLX5_SQC_STATE_RDY = 0x1, 4110 MLX5_SQC_STATE_ERR = 0x3, 4111 }; 4112 4113 struct mlx5_ifc_sqc_bits { 4114 u8 rlky[0x1]; 4115 u8 cd_master[0x1]; 4116 u8 fre[0x1]; 4117 u8 flush_in_error_en[0x1]; 4118 u8 allow_multi_pkt_send_wqe[0x1]; 4119 u8 min_wqe_inline_mode[0x3]; 4120 u8 state[0x4]; 4121 u8 reg_umr[0x1]; 4122 u8 allow_swp[0x1]; 4123 u8 hairpin[0x1]; 4124 u8 non_wire[0x1]; 4125 u8 reserved_at_10[0xa]; 4126 u8 ts_format[0x2]; 4127 u8 reserved_at_1c[0x4]; 4128 4129 u8 reserved_at_20[0x8]; 4130 u8 user_index[0x18]; 4131 4132 u8 reserved_at_40[0x8]; 4133 u8 cqn[0x18]; 4134 4135 u8 reserved_at_60[0x8]; 4136 u8 hairpin_peer_rq[0x18]; 4137 4138 u8 reserved_at_80[0x10]; 4139 u8 hairpin_peer_vhca[0x10]; 4140 4141 u8 reserved_at_a0[0x20]; 4142 4143 u8 reserved_at_c0[0x8]; 4144 u8 ts_cqe_to_dest_cqn[0x18]; 4145 4146 u8 reserved_at_e0[0x10]; 4147 u8 packet_pacing_rate_limit_index[0x10]; 4148 u8 tis_lst_sz[0x10]; 4149 u8 qos_queue_group_id[0x10]; 4150 4151 u8 reserved_at_120[0x40]; 4152 4153 u8 reserved_at_160[0x8]; 4154 u8 tis_num_0[0x18]; 4155 4156 struct mlx5_ifc_wq_bits wq; 4157 }; 4158 4159 enum { 4160 SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0, 4161 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1, 4162 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2, 4163 SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3, 4164 SCHEDULING_CONTEXT_ELEMENT_TYPE_QUEUE_GROUP = 0x4, 4165 SCHEDULING_CONTEXT_ELEMENT_TYPE_RATE_LIMIT = 0x5, 4166 }; 4167 4168 enum { 4169 ELEMENT_TYPE_CAP_MASK_TSAR = 1 << 0, 4170 ELEMENT_TYPE_CAP_MASK_VPORT = 1 << 1, 4171 ELEMENT_TYPE_CAP_MASK_VPORT_TC = 1 << 2, 4172 ELEMENT_TYPE_CAP_MASK_PARA_VPORT_TC = 1 << 3, 4173 ELEMENT_TYPE_CAP_MASK_QUEUE_GROUP = 1 << 4, 4174 ELEMENT_TYPE_CAP_MASK_RATE_LIMIT = 1 << 5, 4175 }; 4176 4177 enum { 4178 TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0, 4179 TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1, 4180 TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2, 4181 TSAR_ELEMENT_TSAR_TYPE_TC_ARB = 0x3, 4182 }; 4183 4184 enum { 4185 TSAR_TYPE_CAP_MASK_DWRR = 1 << 0, 4186 TSAR_TYPE_CAP_MASK_ROUND_ROBIN = 1 << 1, 4187 TSAR_TYPE_CAP_MASK_ETS = 1 << 2, 4188 TSAR_TYPE_CAP_MASK_TC_ARB = 1 << 3, 4189 }; 4190 4191 struct mlx5_ifc_tsar_element_bits { 4192 u8 traffic_class[0x4]; 4193 u8 reserved_at_4[0x4]; 4194 u8 tsar_type[0x8]; 4195 u8 reserved_at_10[0x10]; 4196 }; 4197 4198 struct mlx5_ifc_vport_element_bits { 4199 u8 reserved_at_0[0x4]; 4200 u8 eswitch_owner_vhca_id_valid[0x1]; 4201 u8 eswitch_owner_vhca_id[0xb]; 4202 u8 vport_number[0x10]; 4203 }; 4204 4205 struct mlx5_ifc_vport_tc_element_bits { 4206 u8 traffic_class[0x4]; 4207 u8 eswitch_owner_vhca_id_valid[0x1]; 4208 u8 eswitch_owner_vhca_id[0xb]; 4209 u8 vport_number[0x10]; 4210 }; 4211 4212 union mlx5_ifc_element_attributes_bits { 4213 struct mlx5_ifc_tsar_element_bits tsar; 4214 struct mlx5_ifc_vport_element_bits vport; 4215 struct mlx5_ifc_vport_tc_element_bits vport_tc; 4216 u8 reserved_at_0[0x20]; 4217 }; 4218 4219 struct mlx5_ifc_scheduling_context_bits { 4220 u8 element_type[0x8]; 4221 u8 reserved_at_8[0x18]; 4222 4223 union mlx5_ifc_element_attributes_bits element_attributes; 4224 4225 u8 parent_element_id[0x20]; 4226 4227 u8 reserved_at_60[0x40]; 4228 4229 u8 bw_share[0x20]; 4230 4231 u8 max_average_bw[0x20]; 4232 4233 u8 max_bw_obj_id[0x20]; 4234 4235 u8 reserved_at_100[0x100]; 4236 }; 4237 4238 struct mlx5_ifc_rqtc_bits { 4239 u8 reserved_at_0[0xa0]; 4240 4241 u8 reserved_at_a0[0x5]; 4242 u8 list_q_type[0x3]; 4243 u8 reserved_at_a8[0x8]; 4244 u8 rqt_max_size[0x10]; 4245 4246 u8 rq_vhca_id_format[0x1]; 4247 u8 reserved_at_c1[0xf]; 4248 u8 rqt_actual_size[0x10]; 4249 4250 u8 reserved_at_e0[0x6a0]; 4251 4252 union { 4253 DECLARE_FLEX_ARRAY(struct mlx5_ifc_rq_num_bits, rq_num); 4254 DECLARE_FLEX_ARRAY(struct mlx5_ifc_rq_vhca_bits, rq_vhca); 4255 }; 4256 }; 4257 4258 enum { 4259 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0, 4260 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1, 4261 }; 4262 4263 enum { 4264 MLX5_RQC_STATE_RST = 0x0, 4265 MLX5_RQC_STATE_RDY = 0x1, 4266 MLX5_RQC_STATE_ERR = 0x3, 4267 }; 4268 4269 enum { 4270 MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_BYTE = 0x0, 4271 MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_STRIDE = 0x1, 4272 MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_PAGE = 0x2, 4273 }; 4274 4275 enum { 4276 MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_NO_MATCH = 0x0, 4277 MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_EXTENDED = 0x1, 4278 MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_FIVE_TUPLE = 0x2, 4279 }; 4280 4281 struct mlx5_ifc_rqc_bits { 4282 u8 rlky[0x1]; 4283 u8 delay_drop_en[0x1]; 4284 u8 scatter_fcs[0x1]; 4285 u8 vsd[0x1]; 4286 u8 mem_rq_type[0x4]; 4287 u8 state[0x4]; 4288 u8 reserved_at_c[0x1]; 4289 u8 flush_in_error_en[0x1]; 4290 u8 hairpin[0x1]; 4291 u8 reserved_at_f[0xb]; 4292 u8 ts_format[0x2]; 4293 u8 reserved_at_1c[0x4]; 4294 4295 u8 reserved_at_20[0x8]; 4296 u8 user_index[0x18]; 4297 4298 u8 reserved_at_40[0x8]; 4299 u8 cqn[0x18]; 4300 4301 u8 counter_set_id[0x8]; 4302 u8 reserved_at_68[0x18]; 4303 4304 u8 reserved_at_80[0x8]; 4305 u8 rmpn[0x18]; 4306 4307 u8 reserved_at_a0[0x8]; 4308 u8 hairpin_peer_sq[0x18]; 4309 4310 u8 reserved_at_c0[0x10]; 4311 u8 hairpin_peer_vhca[0x10]; 4312 4313 u8 reserved_at_e0[0x46]; 4314 u8 shampo_no_match_alignment_granularity[0x2]; 4315 u8 reserved_at_128[0x6]; 4316 u8 shampo_match_criteria_type[0x2]; 4317 u8 reservation_timeout[0x10]; 4318 4319 u8 reserved_at_140[0x40]; 4320 4321 struct mlx5_ifc_wq_bits wq; 4322 }; 4323 4324 enum { 4325 MLX5_RMPC_STATE_RDY = 0x1, 4326 MLX5_RMPC_STATE_ERR = 0x3, 4327 }; 4328 4329 struct mlx5_ifc_rmpc_bits { 4330 u8 reserved_at_0[0x8]; 4331 u8 state[0x4]; 4332 u8 reserved_at_c[0x14]; 4333 4334 u8 basic_cyclic_rcv_wqe[0x1]; 4335 u8 reserved_at_21[0x1f]; 4336 4337 u8 reserved_at_40[0x140]; 4338 4339 struct mlx5_ifc_wq_bits wq; 4340 }; 4341 4342 enum { 4343 VHCA_ID_TYPE_HW = 0, 4344 VHCA_ID_TYPE_SW = 1, 4345 }; 4346 4347 struct mlx5_ifc_nic_vport_context_bits { 4348 u8 reserved_at_0[0x5]; 4349 u8 min_wqe_inline_mode[0x3]; 4350 u8 reserved_at_8[0x15]; 4351 u8 disable_mc_local_lb[0x1]; 4352 u8 disable_uc_local_lb[0x1]; 4353 u8 roce_en[0x1]; 4354 4355 u8 arm_change_event[0x1]; 4356 u8 reserved_at_21[0x1a]; 4357 u8 event_on_mtu[0x1]; 4358 u8 event_on_promisc_change[0x1]; 4359 u8 event_on_vlan_change[0x1]; 4360 u8 event_on_mc_address_change[0x1]; 4361 u8 event_on_uc_address_change[0x1]; 4362 4363 u8 vhca_id_type[0x1]; 4364 u8 reserved_at_41[0xb]; 4365 u8 affiliation_criteria[0x4]; 4366 u8 affiliated_vhca_id[0x10]; 4367 4368 u8 reserved_at_60[0xa0]; 4369 4370 u8 reserved_at_100[0x1]; 4371 u8 sd_group[0x3]; 4372 u8 reserved_at_104[0x1c]; 4373 4374 u8 reserved_at_120[0x10]; 4375 u8 mtu[0x10]; 4376 4377 u8 system_image_guid[0x40]; 4378 u8 port_guid[0x40]; 4379 u8 node_guid[0x40]; 4380 4381 u8 reserved_at_200[0x140]; 4382 u8 qkey_violation_counter[0x10]; 4383 u8 reserved_at_350[0x430]; 4384 4385 u8 promisc_uc[0x1]; 4386 u8 promisc_mc[0x1]; 4387 u8 promisc_all[0x1]; 4388 u8 reserved_at_783[0x2]; 4389 u8 allowed_list_type[0x3]; 4390 u8 reserved_at_788[0xc]; 4391 u8 allowed_list_size[0xc]; 4392 4393 struct mlx5_ifc_mac_address_layout_bits permanent_address; 4394 4395 u8 reserved_at_7e0[0x20]; 4396 4397 u8 current_uc_mac_address[][0x40]; 4398 }; 4399 4400 enum { 4401 MLX5_MKC_ACCESS_MODE_PA = 0x0, 4402 MLX5_MKC_ACCESS_MODE_MTT = 0x1, 4403 MLX5_MKC_ACCESS_MODE_KLMS = 0x2, 4404 MLX5_MKC_ACCESS_MODE_KSM = 0x3, 4405 MLX5_MKC_ACCESS_MODE_SW_ICM = 0x4, 4406 MLX5_MKC_ACCESS_MODE_MEMIC = 0x5, 4407 MLX5_MKC_ACCESS_MODE_CROSSING = 0x6, 4408 }; 4409 4410 struct mlx5_ifc_mkc_bits { 4411 u8 reserved_at_0[0x1]; 4412 u8 free[0x1]; 4413 u8 reserved_at_2[0x1]; 4414 u8 access_mode_4_2[0x3]; 4415 u8 reserved_at_6[0x7]; 4416 u8 relaxed_ordering_write[0x1]; 4417 u8 reserved_at_e[0x1]; 4418 u8 small_fence_on_rdma_read_response[0x1]; 4419 u8 umr_en[0x1]; 4420 u8 a[0x1]; 4421 u8 rw[0x1]; 4422 u8 rr[0x1]; 4423 u8 lw[0x1]; 4424 u8 lr[0x1]; 4425 u8 access_mode_1_0[0x2]; 4426 u8 reserved_at_18[0x2]; 4427 u8 ma_translation_mode[0x2]; 4428 u8 reserved_at_1c[0x4]; 4429 4430 u8 qpn[0x18]; 4431 u8 mkey_7_0[0x8]; 4432 4433 u8 reserved_at_40[0x20]; 4434 4435 u8 length64[0x1]; 4436 u8 bsf_en[0x1]; 4437 u8 sync_umr[0x1]; 4438 u8 reserved_at_63[0x2]; 4439 u8 expected_sigerr_count[0x1]; 4440 u8 reserved_at_66[0x1]; 4441 u8 en_rinval[0x1]; 4442 u8 pd[0x18]; 4443 4444 u8 start_addr[0x40]; 4445 4446 u8 len[0x40]; 4447 4448 u8 bsf_octword_size[0x20]; 4449 4450 u8 reserved_at_120[0x60]; 4451 4452 u8 crossing_target_vhca_id[0x10]; 4453 u8 reserved_at_190[0x10]; 4454 4455 u8 translations_octword_size[0x20]; 4456 4457 u8 reserved_at_1c0[0x19]; 4458 u8 relaxed_ordering_read[0x1]; 4459 u8 log_page_size[0x6]; 4460 4461 u8 reserved_at_1e0[0x20]; 4462 }; 4463 4464 struct mlx5_ifc_pkey_bits { 4465 u8 reserved_at_0[0x10]; 4466 u8 pkey[0x10]; 4467 }; 4468 4469 struct mlx5_ifc_array128_auto_bits { 4470 u8 array128_auto[16][0x8]; 4471 }; 4472 4473 struct mlx5_ifc_hca_vport_context_bits { 4474 u8 field_select[0x20]; 4475 4476 u8 reserved_at_20[0xe0]; 4477 4478 u8 sm_virt_aware[0x1]; 4479 u8 has_smi[0x1]; 4480 u8 has_raw[0x1]; 4481 u8 grh_required[0x1]; 4482 u8 reserved_at_104[0x4]; 4483 u8 num_port_plane[0x8]; 4484 u8 port_physical_state[0x4]; 4485 u8 vport_state_policy[0x4]; 4486 u8 port_state[0x4]; 4487 u8 vport_state[0x4]; 4488 4489 u8 reserved_at_120[0x20]; 4490 4491 u8 system_image_guid[0x40]; 4492 4493 u8 port_guid[0x40]; 4494 4495 u8 node_guid[0x40]; 4496 4497 u8 cap_mask1[0x20]; 4498 4499 u8 cap_mask1_field_select[0x20]; 4500 4501 u8 cap_mask2[0x20]; 4502 4503 u8 cap_mask2_field_select[0x20]; 4504 4505 u8 reserved_at_280[0x80]; 4506 4507 u8 lid[0x10]; 4508 u8 reserved_at_310[0x4]; 4509 u8 init_type_reply[0x4]; 4510 u8 lmc[0x3]; 4511 u8 subnet_timeout[0x5]; 4512 4513 u8 sm_lid[0x10]; 4514 u8 sm_sl[0x4]; 4515 u8 reserved_at_334[0xc]; 4516 4517 u8 qkey_violation_counter[0x10]; 4518 u8 pkey_violation_counter[0x10]; 4519 4520 u8 reserved_at_360[0xca0]; 4521 }; 4522 4523 struct mlx5_ifc_esw_vport_context_bits { 4524 u8 fdb_to_vport_reg_c[0x1]; 4525 u8 reserved_at_1[0x2]; 4526 u8 vport_svlan_strip[0x1]; 4527 u8 vport_cvlan_strip[0x1]; 4528 u8 vport_svlan_insert[0x1]; 4529 u8 vport_cvlan_insert[0x2]; 4530 u8 fdb_to_vport_reg_c_id[0x8]; 4531 u8 reserved_at_10[0x10]; 4532 4533 u8 reserved_at_20[0x20]; 4534 4535 u8 svlan_cfi[0x1]; 4536 u8 svlan_pcp[0x3]; 4537 u8 svlan_id[0xc]; 4538 u8 cvlan_cfi[0x1]; 4539 u8 cvlan_pcp[0x3]; 4540 u8 cvlan_id[0xc]; 4541 4542 u8 reserved_at_60[0x720]; 4543 4544 u8 sw_steering_vport_icm_address_rx[0x40]; 4545 4546 u8 sw_steering_vport_icm_address_tx[0x40]; 4547 }; 4548 4549 enum { 4550 MLX5_EQC_STATUS_OK = 0x0, 4551 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa, 4552 }; 4553 4554 enum { 4555 MLX5_EQC_ST_ARMED = 0x9, 4556 MLX5_EQC_ST_FIRED = 0xa, 4557 }; 4558 4559 struct mlx5_ifc_eqc_bits { 4560 u8 status[0x4]; 4561 u8 reserved_at_4[0x9]; 4562 u8 ec[0x1]; 4563 u8 oi[0x1]; 4564 u8 reserved_at_f[0x5]; 4565 u8 st[0x4]; 4566 u8 reserved_at_18[0x8]; 4567 4568 u8 reserved_at_20[0x20]; 4569 4570 u8 reserved_at_40[0x14]; 4571 u8 page_offset[0x6]; 4572 u8 reserved_at_5a[0x6]; 4573 4574 u8 reserved_at_60[0x3]; 4575 u8 log_eq_size[0x5]; 4576 u8 uar_page[0x18]; 4577 4578 u8 reserved_at_80[0x20]; 4579 4580 u8 reserved_at_a0[0x14]; 4581 u8 intr[0xc]; 4582 4583 u8 reserved_at_c0[0x3]; 4584 u8 log_page_size[0x5]; 4585 u8 reserved_at_c8[0x18]; 4586 4587 u8 reserved_at_e0[0x60]; 4588 4589 u8 reserved_at_140[0x8]; 4590 u8 consumer_counter[0x18]; 4591 4592 u8 reserved_at_160[0x8]; 4593 u8 producer_counter[0x18]; 4594 4595 u8 reserved_at_180[0x80]; 4596 }; 4597 4598 enum { 4599 MLX5_DCTC_STATE_ACTIVE = 0x0, 4600 MLX5_DCTC_STATE_DRAINING = 0x1, 4601 MLX5_DCTC_STATE_DRAINED = 0x2, 4602 }; 4603 4604 enum { 4605 MLX5_DCTC_CS_RES_DISABLE = 0x0, 4606 MLX5_DCTC_CS_RES_NA = 0x1, 4607 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2, 4608 }; 4609 4610 enum { 4611 MLX5_DCTC_MTU_256_BYTES = 0x1, 4612 MLX5_DCTC_MTU_512_BYTES = 0x2, 4613 MLX5_DCTC_MTU_1K_BYTES = 0x3, 4614 MLX5_DCTC_MTU_2K_BYTES = 0x4, 4615 MLX5_DCTC_MTU_4K_BYTES = 0x5, 4616 }; 4617 4618 struct mlx5_ifc_dctc_bits { 4619 u8 reserved_at_0[0x4]; 4620 u8 state[0x4]; 4621 u8 reserved_at_8[0x18]; 4622 4623 u8 reserved_at_20[0x7]; 4624 u8 dp_ordering_force[0x1]; 4625 u8 user_index[0x18]; 4626 4627 u8 reserved_at_40[0x8]; 4628 u8 cqn[0x18]; 4629 4630 u8 counter_set_id[0x8]; 4631 u8 atomic_mode[0x4]; 4632 u8 rre[0x1]; 4633 u8 rwe[0x1]; 4634 u8 rae[0x1]; 4635 u8 atomic_like_write_en[0x1]; 4636 u8 latency_sensitive[0x1]; 4637 u8 rlky[0x1]; 4638 u8 free_ar[0x1]; 4639 u8 reserved_at_73[0x1]; 4640 u8 dp_ordering_1[0x1]; 4641 u8 reserved_at_75[0xb]; 4642 4643 u8 reserved_at_80[0x8]; 4644 u8 cs_res[0x8]; 4645 u8 reserved_at_90[0x3]; 4646 u8 min_rnr_nak[0x5]; 4647 u8 reserved_at_98[0x8]; 4648 4649 u8 reserved_at_a0[0x8]; 4650 u8 srqn_xrqn[0x18]; 4651 4652 u8 reserved_at_c0[0x8]; 4653 u8 pd[0x18]; 4654 4655 u8 tclass[0x8]; 4656 u8 reserved_at_e8[0x4]; 4657 u8 flow_label[0x14]; 4658 4659 u8 dc_access_key[0x40]; 4660 4661 u8 reserved_at_140[0x5]; 4662 u8 mtu[0x3]; 4663 u8 port[0x8]; 4664 u8 pkey_index[0x10]; 4665 4666 u8 reserved_at_160[0x8]; 4667 u8 my_addr_index[0x8]; 4668 u8 reserved_at_170[0x8]; 4669 u8 hop_limit[0x8]; 4670 4671 u8 dc_access_key_violation_count[0x20]; 4672 4673 u8 reserved_at_1a0[0x14]; 4674 u8 dei_cfi[0x1]; 4675 u8 eth_prio[0x3]; 4676 u8 ecn[0x2]; 4677 u8 dscp[0x6]; 4678 4679 u8 reserved_at_1c0[0x20]; 4680 u8 ece[0x20]; 4681 }; 4682 4683 enum { 4684 MLX5_CQC_STATUS_OK = 0x0, 4685 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9, 4686 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa, 4687 }; 4688 4689 enum { 4690 MLX5_CQC_CQE_SZ_64_BYTES = 0x0, 4691 MLX5_CQC_CQE_SZ_128_BYTES = 0x1, 4692 }; 4693 4694 enum { 4695 MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED = 0x6, 4696 MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED = 0x9, 4697 MLX5_CQC_ST_FIRED = 0xa, 4698 }; 4699 4700 enum mlx5_cq_period_mode { 4701 MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0, 4702 MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1, 4703 MLX5_CQ_PERIOD_NUM_MODES, 4704 }; 4705 4706 struct mlx5_ifc_cqc_bits { 4707 u8 status[0x4]; 4708 u8 reserved_at_4[0x2]; 4709 u8 dbr_umem_valid[0x1]; 4710 u8 apu_cq[0x1]; 4711 u8 cqe_sz[0x3]; 4712 u8 cc[0x1]; 4713 u8 reserved_at_c[0x1]; 4714 u8 scqe_break_moderation_en[0x1]; 4715 u8 oi[0x1]; 4716 u8 cq_period_mode[0x2]; 4717 u8 cqe_comp_en[0x1]; 4718 u8 mini_cqe_res_format[0x2]; 4719 u8 st[0x4]; 4720 u8 reserved_at_18[0x6]; 4721 u8 cqe_compression_layout[0x2]; 4722 4723 u8 reserved_at_20[0x20]; 4724 4725 u8 reserved_at_40[0x14]; 4726 u8 page_offset[0x6]; 4727 u8 reserved_at_5a[0x6]; 4728 4729 u8 reserved_at_60[0x3]; 4730 u8 log_cq_size[0x5]; 4731 u8 uar_page[0x18]; 4732 4733 u8 reserved_at_80[0x4]; 4734 u8 cq_period[0xc]; 4735 u8 cq_max_count[0x10]; 4736 4737 u8 c_eqn_or_apu_element[0x20]; 4738 4739 u8 reserved_at_c0[0x3]; 4740 u8 log_page_size[0x5]; 4741 u8 reserved_at_c8[0x18]; 4742 4743 u8 reserved_at_e0[0x20]; 4744 4745 u8 reserved_at_100[0x8]; 4746 u8 last_notified_index[0x18]; 4747 4748 u8 reserved_at_120[0x8]; 4749 u8 last_solicit_index[0x18]; 4750 4751 u8 reserved_at_140[0x8]; 4752 u8 consumer_counter[0x18]; 4753 4754 u8 reserved_at_160[0x8]; 4755 u8 producer_counter[0x18]; 4756 4757 u8 reserved_at_180[0x40]; 4758 4759 u8 dbr_addr[0x40]; 4760 }; 4761 4762 union mlx5_ifc_cong_control_roce_ecn_auto_bits { 4763 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp; 4764 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp; 4765 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np; 4766 struct mlx5_ifc_cong_control_r_roce_general_bits cong_control_r_roce_general; 4767 u8 reserved_at_0[0x800]; 4768 }; 4769 4770 struct mlx5_ifc_query_adapter_param_block_bits { 4771 u8 reserved_at_0[0xc0]; 4772 4773 u8 reserved_at_c0[0x8]; 4774 u8 ieee_vendor_id[0x18]; 4775 4776 u8 reserved_at_e0[0x10]; 4777 u8 vsd_vendor_id[0x10]; 4778 4779 u8 vsd[208][0x8]; 4780 4781 u8 vsd_contd_psid[16][0x8]; 4782 }; 4783 4784 enum { 4785 MLX5_XRQC_STATE_GOOD = 0x0, 4786 MLX5_XRQC_STATE_ERROR = 0x1, 4787 }; 4788 4789 enum { 4790 MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0, 4791 MLX5_XRQC_TOPOLOGY_TAG_MATCHING = 0x1, 4792 }; 4793 4794 enum { 4795 MLX5_XRQC_OFFLOAD_RNDV = 0x1, 4796 }; 4797 4798 struct mlx5_ifc_tag_matching_topology_context_bits { 4799 u8 log_matching_list_sz[0x4]; 4800 u8 reserved_at_4[0xc]; 4801 u8 append_next_index[0x10]; 4802 4803 u8 sw_phase_cnt[0x10]; 4804 u8 hw_phase_cnt[0x10]; 4805 4806 u8 reserved_at_40[0x40]; 4807 }; 4808 4809 struct mlx5_ifc_xrqc_bits { 4810 u8 state[0x4]; 4811 u8 rlkey[0x1]; 4812 u8 reserved_at_5[0xf]; 4813 u8 topology[0x4]; 4814 u8 reserved_at_18[0x4]; 4815 u8 offload[0x4]; 4816 4817 u8 reserved_at_20[0x8]; 4818 u8 user_index[0x18]; 4819 4820 u8 reserved_at_40[0x8]; 4821 u8 cqn[0x18]; 4822 4823 u8 reserved_at_60[0xa0]; 4824 4825 struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context; 4826 4827 u8 reserved_at_180[0x280]; 4828 4829 struct mlx5_ifc_wq_bits wq; 4830 }; 4831 4832 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits { 4833 struct mlx5_ifc_modify_field_select_bits modify_field_select; 4834 struct mlx5_ifc_resize_field_select_bits resize_field_select; 4835 u8 reserved_at_0[0x20]; 4836 }; 4837 4838 union mlx5_ifc_field_select_802_1_r_roce_auto_bits { 4839 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp; 4840 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp; 4841 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np; 4842 u8 reserved_at_0[0x20]; 4843 }; 4844 4845 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits { 4846 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 4847 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 4848 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 4849 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 4850 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 4851 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 4852 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout; 4853 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout; 4854 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 4855 struct mlx5_ifc_ib_ext_port_cntrs_grp_data_layout_bits ib_ext_port_cntrs_grp_data_layout; 4856 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 4857 struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs; 4858 struct mlx5_ifc_phys_layer_recovery_cntrs_bits phys_layer_recovery_cntrs; 4859 u8 reserved_at_0[0x7c0]; 4860 }; 4861 4862 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits { 4863 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout; 4864 u8 reserved_at_0[0x7c0]; 4865 }; 4866 4867 union mlx5_ifc_event_auto_bits { 4868 struct mlx5_ifc_comp_event_bits comp_event; 4869 struct mlx5_ifc_dct_events_bits dct_events; 4870 struct mlx5_ifc_qp_events_bits qp_events; 4871 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event; 4872 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event; 4873 struct mlx5_ifc_cq_error_bits cq_error; 4874 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged; 4875 struct mlx5_ifc_port_state_change_event_bits port_state_change_event; 4876 struct mlx5_ifc_gpio_event_bits gpio_event; 4877 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event; 4878 struct mlx5_ifc_stall_vl_event_bits stall_vl_event; 4879 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event; 4880 u8 reserved_at_0[0xe0]; 4881 }; 4882 4883 struct mlx5_ifc_health_buffer_bits { 4884 u8 reserved_at_0[0x100]; 4885 4886 u8 assert_existptr[0x20]; 4887 4888 u8 assert_callra[0x20]; 4889 4890 u8 reserved_at_140[0x20]; 4891 4892 u8 time[0x20]; 4893 4894 u8 fw_version[0x20]; 4895 4896 u8 hw_id[0x20]; 4897 4898 u8 rfr[0x1]; 4899 u8 reserved_at_1c1[0x3]; 4900 u8 valid[0x1]; 4901 u8 severity[0x3]; 4902 u8 reserved_at_1c8[0x18]; 4903 4904 u8 irisc_index[0x8]; 4905 u8 synd[0x8]; 4906 u8 ext_synd[0x10]; 4907 }; 4908 4909 struct mlx5_ifc_register_loopback_control_bits { 4910 u8 no_lb[0x1]; 4911 u8 reserved_at_1[0x7]; 4912 u8 port[0x8]; 4913 u8 reserved_at_10[0x10]; 4914 4915 u8 reserved_at_20[0x60]; 4916 }; 4917 4918 enum { 4919 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0, 4920 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1, 4921 }; 4922 4923 struct mlx5_ifc_teardown_hca_out_bits { 4924 u8 status[0x8]; 4925 u8 reserved_at_8[0x18]; 4926 4927 u8 syndrome[0x20]; 4928 4929 u8 reserved_at_40[0x3f]; 4930 4931 u8 state[0x1]; 4932 }; 4933 4934 enum { 4935 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0, 4936 MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE = 0x1, 4937 MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN = 0x2, 4938 }; 4939 4940 struct mlx5_ifc_teardown_hca_in_bits { 4941 u8 opcode[0x10]; 4942 u8 reserved_at_10[0x10]; 4943 4944 u8 reserved_at_20[0x10]; 4945 u8 op_mod[0x10]; 4946 4947 u8 reserved_at_40[0x10]; 4948 u8 profile[0x10]; 4949 4950 u8 reserved_at_60[0x20]; 4951 }; 4952 4953 struct mlx5_ifc_sqerr2rts_qp_out_bits { 4954 u8 status[0x8]; 4955 u8 reserved_at_8[0x18]; 4956 4957 u8 syndrome[0x20]; 4958 4959 u8 reserved_at_40[0x40]; 4960 }; 4961 4962 struct mlx5_ifc_sqerr2rts_qp_in_bits { 4963 u8 opcode[0x10]; 4964 u8 uid[0x10]; 4965 4966 u8 reserved_at_20[0x10]; 4967 u8 op_mod[0x10]; 4968 4969 u8 reserved_at_40[0x8]; 4970 u8 qpn[0x18]; 4971 4972 u8 reserved_at_60[0x20]; 4973 4974 u8 opt_param_mask[0x20]; 4975 4976 u8 reserved_at_a0[0x20]; 4977 4978 struct mlx5_ifc_qpc_bits qpc; 4979 4980 u8 reserved_at_800[0x80]; 4981 }; 4982 4983 struct mlx5_ifc_sqd2rts_qp_out_bits { 4984 u8 status[0x8]; 4985 u8 reserved_at_8[0x18]; 4986 4987 u8 syndrome[0x20]; 4988 4989 u8 reserved_at_40[0x40]; 4990 }; 4991 4992 struct mlx5_ifc_sqd2rts_qp_in_bits { 4993 u8 opcode[0x10]; 4994 u8 uid[0x10]; 4995 4996 u8 reserved_at_20[0x10]; 4997 u8 op_mod[0x10]; 4998 4999 u8 reserved_at_40[0x8]; 5000 u8 qpn[0x18]; 5001 5002 u8 reserved_at_60[0x20]; 5003 5004 u8 opt_param_mask[0x20]; 5005 5006 u8 reserved_at_a0[0x20]; 5007 5008 struct mlx5_ifc_qpc_bits qpc; 5009 5010 u8 reserved_at_800[0x80]; 5011 }; 5012 5013 struct mlx5_ifc_set_roce_address_out_bits { 5014 u8 status[0x8]; 5015 u8 reserved_at_8[0x18]; 5016 5017 u8 syndrome[0x20]; 5018 5019 u8 reserved_at_40[0x40]; 5020 }; 5021 5022 struct mlx5_ifc_set_roce_address_in_bits { 5023 u8 opcode[0x10]; 5024 u8 reserved_at_10[0x10]; 5025 5026 u8 reserved_at_20[0x10]; 5027 u8 op_mod[0x10]; 5028 5029 u8 roce_address_index[0x10]; 5030 u8 reserved_at_50[0xc]; 5031 u8 vhca_port_num[0x4]; 5032 5033 u8 reserved_at_60[0x20]; 5034 5035 struct mlx5_ifc_roce_addr_layout_bits roce_address; 5036 }; 5037 5038 struct mlx5_ifc_set_mad_demux_out_bits { 5039 u8 status[0x8]; 5040 u8 reserved_at_8[0x18]; 5041 5042 u8 syndrome[0x20]; 5043 5044 u8 reserved_at_40[0x40]; 5045 }; 5046 5047 enum { 5048 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0, 5049 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2, 5050 }; 5051 5052 struct mlx5_ifc_set_mad_demux_in_bits { 5053 u8 opcode[0x10]; 5054 u8 reserved_at_10[0x10]; 5055 5056 u8 reserved_at_20[0x10]; 5057 u8 op_mod[0x10]; 5058 5059 u8 reserved_at_40[0x20]; 5060 5061 u8 reserved_at_60[0x6]; 5062 u8 demux_mode[0x2]; 5063 u8 reserved_at_68[0x18]; 5064 }; 5065 5066 struct mlx5_ifc_set_l2_table_entry_out_bits { 5067 u8 status[0x8]; 5068 u8 reserved_at_8[0x18]; 5069 5070 u8 syndrome[0x20]; 5071 5072 u8 reserved_at_40[0x40]; 5073 }; 5074 5075 struct mlx5_ifc_set_l2_table_entry_in_bits { 5076 u8 opcode[0x10]; 5077 u8 reserved_at_10[0x10]; 5078 5079 u8 reserved_at_20[0x10]; 5080 u8 op_mod[0x10]; 5081 5082 u8 reserved_at_40[0x60]; 5083 5084 u8 reserved_at_a0[0x8]; 5085 u8 table_index[0x18]; 5086 5087 u8 reserved_at_c0[0x20]; 5088 5089 u8 reserved_at_e0[0x10]; 5090 u8 silent_mode_valid[0x1]; 5091 u8 silent_mode[0x1]; 5092 u8 reserved_at_f2[0x1]; 5093 u8 vlan_valid[0x1]; 5094 u8 vlan[0xc]; 5095 5096 struct mlx5_ifc_mac_address_layout_bits mac_address; 5097 5098 u8 reserved_at_140[0xc0]; 5099 }; 5100 5101 struct mlx5_ifc_set_issi_out_bits { 5102 u8 status[0x8]; 5103 u8 reserved_at_8[0x18]; 5104 5105 u8 syndrome[0x20]; 5106 5107 u8 reserved_at_40[0x40]; 5108 }; 5109 5110 struct mlx5_ifc_set_issi_in_bits { 5111 u8 opcode[0x10]; 5112 u8 reserved_at_10[0x10]; 5113 5114 u8 reserved_at_20[0x10]; 5115 u8 op_mod[0x10]; 5116 5117 u8 reserved_at_40[0x10]; 5118 u8 current_issi[0x10]; 5119 5120 u8 reserved_at_60[0x20]; 5121 }; 5122 5123 struct mlx5_ifc_set_hca_cap_out_bits { 5124 u8 status[0x8]; 5125 u8 reserved_at_8[0x18]; 5126 5127 u8 syndrome[0x20]; 5128 5129 u8 reserved_at_40[0x40]; 5130 }; 5131 5132 struct mlx5_ifc_set_hca_cap_in_bits { 5133 u8 opcode[0x10]; 5134 u8 reserved_at_10[0x10]; 5135 5136 u8 reserved_at_20[0x10]; 5137 u8 op_mod[0x10]; 5138 5139 u8 other_function[0x1]; 5140 u8 ec_vf_function[0x1]; 5141 u8 reserved_at_42[0xe]; 5142 u8 function_id[0x10]; 5143 5144 u8 reserved_at_60[0x20]; 5145 5146 union mlx5_ifc_hca_cap_union_bits capability; 5147 }; 5148 5149 enum { 5150 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0, 5151 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1, 5152 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2, 5153 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3, 5154 MLX5_SET_FTE_MODIFY_ENABLE_MASK_IPSEC_OBJ_ID = 0x4 5155 }; 5156 5157 struct mlx5_ifc_set_fte_out_bits { 5158 u8 status[0x8]; 5159 u8 reserved_at_8[0x18]; 5160 5161 u8 syndrome[0x20]; 5162 5163 u8 reserved_at_40[0x40]; 5164 }; 5165 5166 struct mlx5_ifc_set_fte_in_bits { 5167 u8 opcode[0x10]; 5168 u8 reserved_at_10[0x10]; 5169 5170 u8 reserved_at_20[0x10]; 5171 u8 op_mod[0x10]; 5172 5173 u8 other_vport[0x1]; 5174 u8 reserved_at_41[0xf]; 5175 u8 vport_number[0x10]; 5176 5177 u8 reserved_at_60[0x20]; 5178 5179 u8 table_type[0x8]; 5180 u8 reserved_at_88[0x18]; 5181 5182 u8 reserved_at_a0[0x8]; 5183 u8 table_id[0x18]; 5184 5185 u8 ignore_flow_level[0x1]; 5186 u8 reserved_at_c1[0x17]; 5187 u8 modify_enable_mask[0x8]; 5188 5189 u8 reserved_at_e0[0x20]; 5190 5191 u8 flow_index[0x20]; 5192 5193 u8 reserved_at_120[0xe0]; 5194 5195 struct mlx5_ifc_flow_context_bits flow_context; 5196 }; 5197 5198 struct mlx5_ifc_dest_format_bits { 5199 u8 destination_type[0x8]; 5200 u8 destination_id[0x18]; 5201 5202 u8 destination_eswitch_owner_vhca_id_valid[0x1]; 5203 u8 packet_reformat[0x1]; 5204 u8 reserved_at_22[0xe]; 5205 u8 destination_eswitch_owner_vhca_id[0x10]; 5206 }; 5207 5208 struct mlx5_ifc_rts2rts_qp_out_bits { 5209 u8 status[0x8]; 5210 u8 reserved_at_8[0x18]; 5211 5212 u8 syndrome[0x20]; 5213 5214 u8 reserved_at_40[0x20]; 5215 u8 ece[0x20]; 5216 }; 5217 5218 struct mlx5_ifc_rts2rts_qp_in_bits { 5219 u8 opcode[0x10]; 5220 u8 uid[0x10]; 5221 5222 u8 reserved_at_20[0x10]; 5223 u8 op_mod[0x10]; 5224 5225 u8 reserved_at_40[0x8]; 5226 u8 qpn[0x18]; 5227 5228 u8 reserved_at_60[0x20]; 5229 5230 u8 opt_param_mask[0x20]; 5231 5232 u8 ece[0x20]; 5233 5234 struct mlx5_ifc_qpc_bits qpc; 5235 5236 u8 reserved_at_800[0x80]; 5237 }; 5238 5239 struct mlx5_ifc_rtr2rts_qp_out_bits { 5240 u8 status[0x8]; 5241 u8 reserved_at_8[0x18]; 5242 5243 u8 syndrome[0x20]; 5244 5245 u8 reserved_at_40[0x20]; 5246 u8 ece[0x20]; 5247 }; 5248 5249 struct mlx5_ifc_rtr2rts_qp_in_bits { 5250 u8 opcode[0x10]; 5251 u8 uid[0x10]; 5252 5253 u8 reserved_at_20[0x10]; 5254 u8 op_mod[0x10]; 5255 5256 u8 reserved_at_40[0x8]; 5257 u8 qpn[0x18]; 5258 5259 u8 reserved_at_60[0x20]; 5260 5261 u8 opt_param_mask[0x20]; 5262 5263 u8 ece[0x20]; 5264 5265 struct mlx5_ifc_qpc_bits qpc; 5266 5267 u8 reserved_at_800[0x80]; 5268 }; 5269 5270 struct mlx5_ifc_rst2init_qp_out_bits { 5271 u8 status[0x8]; 5272 u8 reserved_at_8[0x18]; 5273 5274 u8 syndrome[0x20]; 5275 5276 u8 reserved_at_40[0x20]; 5277 u8 ece[0x20]; 5278 }; 5279 5280 struct mlx5_ifc_rst2init_qp_in_bits { 5281 u8 opcode[0x10]; 5282 u8 uid[0x10]; 5283 5284 u8 reserved_at_20[0x10]; 5285 u8 op_mod[0x10]; 5286 5287 u8 reserved_at_40[0x8]; 5288 u8 qpn[0x18]; 5289 5290 u8 reserved_at_60[0x20]; 5291 5292 u8 opt_param_mask[0x20]; 5293 5294 u8 ece[0x20]; 5295 5296 struct mlx5_ifc_qpc_bits qpc; 5297 5298 u8 reserved_at_800[0x80]; 5299 }; 5300 5301 struct mlx5_ifc_query_xrq_out_bits { 5302 u8 status[0x8]; 5303 u8 reserved_at_8[0x18]; 5304 5305 u8 syndrome[0x20]; 5306 5307 u8 reserved_at_40[0x40]; 5308 5309 struct mlx5_ifc_xrqc_bits xrq_context; 5310 }; 5311 5312 struct mlx5_ifc_query_xrq_in_bits { 5313 u8 opcode[0x10]; 5314 u8 reserved_at_10[0x10]; 5315 5316 u8 reserved_at_20[0x10]; 5317 u8 op_mod[0x10]; 5318 5319 u8 reserved_at_40[0x8]; 5320 u8 xrqn[0x18]; 5321 5322 u8 reserved_at_60[0x20]; 5323 }; 5324 5325 struct mlx5_ifc_query_xrc_srq_out_bits { 5326 u8 status[0x8]; 5327 u8 reserved_at_8[0x18]; 5328 5329 u8 syndrome[0x20]; 5330 5331 u8 reserved_at_40[0x40]; 5332 5333 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 5334 5335 u8 reserved_at_280[0x600]; 5336 5337 u8 pas[][0x40]; 5338 }; 5339 5340 struct mlx5_ifc_query_xrc_srq_in_bits { 5341 u8 opcode[0x10]; 5342 u8 reserved_at_10[0x10]; 5343 5344 u8 reserved_at_20[0x10]; 5345 u8 op_mod[0x10]; 5346 5347 u8 reserved_at_40[0x8]; 5348 u8 xrc_srqn[0x18]; 5349 5350 u8 reserved_at_60[0x20]; 5351 }; 5352 5353 enum { 5354 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0, 5355 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1, 5356 }; 5357 5358 struct mlx5_ifc_query_vport_state_out_bits { 5359 u8 status[0x8]; 5360 u8 reserved_at_8[0x18]; 5361 5362 u8 syndrome[0x20]; 5363 5364 u8 reserved_at_40[0x20]; 5365 5366 u8 reserved_at_60[0x18]; 5367 u8 admin_state[0x4]; 5368 u8 state[0x4]; 5369 }; 5370 5371 struct mlx5_ifc_array1024_auto_bits { 5372 u8 array1024_auto[32][0x20]; 5373 }; 5374 5375 struct mlx5_ifc_query_vuid_in_bits { 5376 u8 opcode[0x10]; 5377 u8 uid[0x10]; 5378 5379 u8 reserved_at_20[0x40]; 5380 5381 u8 query_vfs_vuid[0x1]; 5382 u8 data_direct[0x1]; 5383 u8 reserved_at_62[0xe]; 5384 u8 vhca_id[0x10]; 5385 }; 5386 5387 struct mlx5_ifc_query_vuid_out_bits { 5388 u8 status[0x8]; 5389 u8 reserved_at_8[0x18]; 5390 5391 u8 syndrome[0x20]; 5392 5393 u8 reserved_at_40[0x1a0]; 5394 5395 u8 reserved_at_1e0[0x10]; 5396 u8 num_of_entries[0x10]; 5397 5398 struct mlx5_ifc_array1024_auto_bits vuid[]; 5399 }; 5400 5401 enum { 5402 MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT = 0x0, 5403 MLX5_VPORT_STATE_OP_MOD_ESW_VPORT = 0x1, 5404 MLX5_VPORT_STATE_OP_MOD_UPLINK = 0x2, 5405 }; 5406 5407 struct mlx5_ifc_arm_monitor_counter_in_bits { 5408 u8 opcode[0x10]; 5409 u8 uid[0x10]; 5410 5411 u8 reserved_at_20[0x10]; 5412 u8 op_mod[0x10]; 5413 5414 u8 reserved_at_40[0x20]; 5415 5416 u8 reserved_at_60[0x20]; 5417 }; 5418 5419 struct mlx5_ifc_arm_monitor_counter_out_bits { 5420 u8 status[0x8]; 5421 u8 reserved_at_8[0x18]; 5422 5423 u8 syndrome[0x20]; 5424 5425 u8 reserved_at_40[0x40]; 5426 }; 5427 5428 enum { 5429 MLX5_QUERY_MONITOR_CNT_TYPE_PPCNT = 0x0, 5430 MLX5_QUERY_MONITOR_CNT_TYPE_Q_COUNTER = 0x1, 5431 }; 5432 5433 enum mlx5_monitor_counter_ppcnt { 5434 MLX5_QUERY_MONITOR_PPCNT_IN_RANGE_LENGTH_ERRORS = 0x0, 5435 MLX5_QUERY_MONITOR_PPCNT_OUT_OF_RANGE_LENGTH_FIELD = 0x1, 5436 MLX5_QUERY_MONITOR_PPCNT_FRAME_TOO_LONG_ERRORS = 0x2, 5437 MLX5_QUERY_MONITOR_PPCNT_FRAME_CHECK_SEQUENCE_ERRORS = 0x3, 5438 MLX5_QUERY_MONITOR_PPCNT_ALIGNMENT_ERRORS = 0x4, 5439 MLX5_QUERY_MONITOR_PPCNT_IF_OUT_DISCARDS = 0x5, 5440 }; 5441 5442 enum { 5443 MLX5_QUERY_MONITOR_Q_COUNTER_RX_OUT_OF_BUFFER = 0x4, 5444 }; 5445 5446 struct mlx5_ifc_monitor_counter_output_bits { 5447 u8 reserved_at_0[0x4]; 5448 u8 type[0x4]; 5449 u8 reserved_at_8[0x8]; 5450 u8 counter[0x10]; 5451 5452 u8 counter_group_id[0x20]; 5453 }; 5454 5455 #define MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 (6) 5456 #define MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1 (1) 5457 #define MLX5_CMD_SET_MONITOR_NUM_COUNTER (MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 +\ 5458 MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1) 5459 5460 struct mlx5_ifc_set_monitor_counter_in_bits { 5461 u8 opcode[0x10]; 5462 u8 uid[0x10]; 5463 5464 u8 reserved_at_20[0x10]; 5465 u8 op_mod[0x10]; 5466 5467 u8 reserved_at_40[0x10]; 5468 u8 num_of_counters[0x10]; 5469 5470 u8 reserved_at_60[0x20]; 5471 5472 struct mlx5_ifc_monitor_counter_output_bits monitor_counter[MLX5_CMD_SET_MONITOR_NUM_COUNTER]; 5473 }; 5474 5475 struct mlx5_ifc_set_monitor_counter_out_bits { 5476 u8 status[0x8]; 5477 u8 reserved_at_8[0x18]; 5478 5479 u8 syndrome[0x20]; 5480 5481 u8 reserved_at_40[0x40]; 5482 }; 5483 5484 struct mlx5_ifc_query_vport_state_in_bits { 5485 u8 opcode[0x10]; 5486 u8 reserved_at_10[0x10]; 5487 5488 u8 reserved_at_20[0x10]; 5489 u8 op_mod[0x10]; 5490 5491 u8 other_vport[0x1]; 5492 u8 reserved_at_41[0xf]; 5493 u8 vport_number[0x10]; 5494 5495 u8 reserved_at_60[0x20]; 5496 }; 5497 5498 struct mlx5_ifc_query_vnic_env_out_bits { 5499 u8 status[0x8]; 5500 u8 reserved_at_8[0x18]; 5501 5502 u8 syndrome[0x20]; 5503 5504 u8 reserved_at_40[0x40]; 5505 5506 struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env; 5507 }; 5508 5509 enum { 5510 MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS = 0x0, 5511 }; 5512 5513 struct mlx5_ifc_query_vnic_env_in_bits { 5514 u8 opcode[0x10]; 5515 u8 reserved_at_10[0x10]; 5516 5517 u8 reserved_at_20[0x10]; 5518 u8 op_mod[0x10]; 5519 5520 u8 other_vport[0x1]; 5521 u8 reserved_at_41[0xf]; 5522 u8 vport_number[0x10]; 5523 5524 u8 reserved_at_60[0x20]; 5525 }; 5526 5527 struct mlx5_ifc_query_vport_counter_out_bits { 5528 u8 status[0x8]; 5529 u8 reserved_at_8[0x18]; 5530 5531 u8 syndrome[0x20]; 5532 5533 u8 reserved_at_40[0x40]; 5534 5535 struct mlx5_ifc_traffic_counter_bits received_errors; 5536 5537 struct mlx5_ifc_traffic_counter_bits transmit_errors; 5538 5539 struct mlx5_ifc_traffic_counter_bits received_ib_unicast; 5540 5541 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast; 5542 5543 struct mlx5_ifc_traffic_counter_bits received_ib_multicast; 5544 5545 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast; 5546 5547 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast; 5548 5549 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast; 5550 5551 struct mlx5_ifc_traffic_counter_bits received_eth_unicast; 5552 5553 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast; 5554 5555 struct mlx5_ifc_traffic_counter_bits received_eth_multicast; 5556 5557 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast; 5558 5559 struct mlx5_ifc_traffic_counter_bits local_loopback; 5560 5561 u8 reserved_at_700[0x980]; 5562 }; 5563 5564 enum { 5565 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0, 5566 }; 5567 5568 struct mlx5_ifc_query_vport_counter_in_bits { 5569 u8 opcode[0x10]; 5570 u8 reserved_at_10[0x10]; 5571 5572 u8 reserved_at_20[0x10]; 5573 u8 op_mod[0x10]; 5574 5575 u8 other_vport[0x1]; 5576 u8 reserved_at_41[0xb]; 5577 u8 port_num[0x4]; 5578 u8 vport_number[0x10]; 5579 5580 u8 reserved_at_60[0x60]; 5581 5582 u8 clear[0x1]; 5583 u8 reserved_at_c1[0x1f]; 5584 5585 u8 reserved_at_e0[0x20]; 5586 }; 5587 5588 struct mlx5_ifc_query_tis_out_bits { 5589 u8 status[0x8]; 5590 u8 reserved_at_8[0x18]; 5591 5592 u8 syndrome[0x20]; 5593 5594 u8 reserved_at_40[0x40]; 5595 5596 struct mlx5_ifc_tisc_bits tis_context; 5597 }; 5598 5599 struct mlx5_ifc_query_tis_in_bits { 5600 u8 opcode[0x10]; 5601 u8 reserved_at_10[0x10]; 5602 5603 u8 reserved_at_20[0x10]; 5604 u8 op_mod[0x10]; 5605 5606 u8 reserved_at_40[0x8]; 5607 u8 tisn[0x18]; 5608 5609 u8 reserved_at_60[0x20]; 5610 }; 5611 5612 struct mlx5_ifc_query_tir_out_bits { 5613 u8 status[0x8]; 5614 u8 reserved_at_8[0x18]; 5615 5616 u8 syndrome[0x20]; 5617 5618 u8 reserved_at_40[0xc0]; 5619 5620 struct mlx5_ifc_tirc_bits tir_context; 5621 }; 5622 5623 struct mlx5_ifc_query_tir_in_bits { 5624 u8 opcode[0x10]; 5625 u8 reserved_at_10[0x10]; 5626 5627 u8 reserved_at_20[0x10]; 5628 u8 op_mod[0x10]; 5629 5630 u8 reserved_at_40[0x8]; 5631 u8 tirn[0x18]; 5632 5633 u8 reserved_at_60[0x20]; 5634 }; 5635 5636 struct mlx5_ifc_query_srq_out_bits { 5637 u8 status[0x8]; 5638 u8 reserved_at_8[0x18]; 5639 5640 u8 syndrome[0x20]; 5641 5642 u8 reserved_at_40[0x40]; 5643 5644 struct mlx5_ifc_srqc_bits srq_context_entry; 5645 5646 u8 reserved_at_280[0x600]; 5647 5648 u8 pas[][0x40]; 5649 }; 5650 5651 struct mlx5_ifc_query_srq_in_bits { 5652 u8 opcode[0x10]; 5653 u8 reserved_at_10[0x10]; 5654 5655 u8 reserved_at_20[0x10]; 5656 u8 op_mod[0x10]; 5657 5658 u8 reserved_at_40[0x8]; 5659 u8 srqn[0x18]; 5660 5661 u8 reserved_at_60[0x20]; 5662 }; 5663 5664 struct mlx5_ifc_query_sq_out_bits { 5665 u8 status[0x8]; 5666 u8 reserved_at_8[0x18]; 5667 5668 u8 syndrome[0x20]; 5669 5670 u8 reserved_at_40[0xc0]; 5671 5672 struct mlx5_ifc_sqc_bits sq_context; 5673 }; 5674 5675 struct mlx5_ifc_query_sq_in_bits { 5676 u8 opcode[0x10]; 5677 u8 reserved_at_10[0x10]; 5678 5679 u8 reserved_at_20[0x10]; 5680 u8 op_mod[0x10]; 5681 5682 u8 reserved_at_40[0x8]; 5683 u8 sqn[0x18]; 5684 5685 u8 reserved_at_60[0x20]; 5686 }; 5687 5688 struct mlx5_ifc_query_special_contexts_out_bits { 5689 u8 status[0x8]; 5690 u8 reserved_at_8[0x18]; 5691 5692 u8 syndrome[0x20]; 5693 5694 u8 dump_fill_mkey[0x20]; 5695 5696 u8 resd_lkey[0x20]; 5697 5698 u8 null_mkey[0x20]; 5699 5700 u8 terminate_scatter_list_mkey[0x20]; 5701 5702 u8 repeated_mkey[0x20]; 5703 5704 u8 reserved_at_a0[0x20]; 5705 }; 5706 5707 struct mlx5_ifc_query_special_contexts_in_bits { 5708 u8 opcode[0x10]; 5709 u8 reserved_at_10[0x10]; 5710 5711 u8 reserved_at_20[0x10]; 5712 u8 op_mod[0x10]; 5713 5714 u8 reserved_at_40[0x40]; 5715 }; 5716 5717 struct mlx5_ifc_query_scheduling_element_out_bits { 5718 u8 opcode[0x10]; 5719 u8 reserved_at_10[0x10]; 5720 5721 u8 reserved_at_20[0x10]; 5722 u8 op_mod[0x10]; 5723 5724 u8 reserved_at_40[0xc0]; 5725 5726 struct mlx5_ifc_scheduling_context_bits scheduling_context; 5727 5728 u8 reserved_at_300[0x100]; 5729 }; 5730 5731 enum { 5732 SCHEDULING_HIERARCHY_E_SWITCH = 0x2, 5733 SCHEDULING_HIERARCHY_NIC = 0x3, 5734 }; 5735 5736 struct mlx5_ifc_query_scheduling_element_in_bits { 5737 u8 opcode[0x10]; 5738 u8 reserved_at_10[0x10]; 5739 5740 u8 reserved_at_20[0x10]; 5741 u8 op_mod[0x10]; 5742 5743 u8 scheduling_hierarchy[0x8]; 5744 u8 reserved_at_48[0x18]; 5745 5746 u8 scheduling_element_id[0x20]; 5747 5748 u8 reserved_at_80[0x180]; 5749 }; 5750 5751 struct mlx5_ifc_query_rqt_out_bits { 5752 u8 status[0x8]; 5753 u8 reserved_at_8[0x18]; 5754 5755 u8 syndrome[0x20]; 5756 5757 u8 reserved_at_40[0xc0]; 5758 5759 struct mlx5_ifc_rqtc_bits rqt_context; 5760 }; 5761 5762 struct mlx5_ifc_query_rqt_in_bits { 5763 u8 opcode[0x10]; 5764 u8 reserved_at_10[0x10]; 5765 5766 u8 reserved_at_20[0x10]; 5767 u8 op_mod[0x10]; 5768 5769 u8 reserved_at_40[0x8]; 5770 u8 rqtn[0x18]; 5771 5772 u8 reserved_at_60[0x20]; 5773 }; 5774 5775 struct mlx5_ifc_query_rq_out_bits { 5776 u8 status[0x8]; 5777 u8 reserved_at_8[0x18]; 5778 5779 u8 syndrome[0x20]; 5780 5781 u8 reserved_at_40[0xc0]; 5782 5783 struct mlx5_ifc_rqc_bits rq_context; 5784 }; 5785 5786 struct mlx5_ifc_query_rq_in_bits { 5787 u8 opcode[0x10]; 5788 u8 reserved_at_10[0x10]; 5789 5790 u8 reserved_at_20[0x10]; 5791 u8 op_mod[0x10]; 5792 5793 u8 reserved_at_40[0x8]; 5794 u8 rqn[0x18]; 5795 5796 u8 reserved_at_60[0x20]; 5797 }; 5798 5799 struct mlx5_ifc_query_roce_address_out_bits { 5800 u8 status[0x8]; 5801 u8 reserved_at_8[0x18]; 5802 5803 u8 syndrome[0x20]; 5804 5805 u8 reserved_at_40[0x40]; 5806 5807 struct mlx5_ifc_roce_addr_layout_bits roce_address; 5808 }; 5809 5810 struct mlx5_ifc_query_roce_address_in_bits { 5811 u8 opcode[0x10]; 5812 u8 reserved_at_10[0x10]; 5813 5814 u8 reserved_at_20[0x10]; 5815 u8 op_mod[0x10]; 5816 5817 u8 roce_address_index[0x10]; 5818 u8 reserved_at_50[0xc]; 5819 u8 vhca_port_num[0x4]; 5820 5821 u8 reserved_at_60[0x20]; 5822 }; 5823 5824 struct mlx5_ifc_query_rmp_out_bits { 5825 u8 status[0x8]; 5826 u8 reserved_at_8[0x18]; 5827 5828 u8 syndrome[0x20]; 5829 5830 u8 reserved_at_40[0xc0]; 5831 5832 struct mlx5_ifc_rmpc_bits rmp_context; 5833 }; 5834 5835 struct mlx5_ifc_query_rmp_in_bits { 5836 u8 opcode[0x10]; 5837 u8 reserved_at_10[0x10]; 5838 5839 u8 reserved_at_20[0x10]; 5840 u8 op_mod[0x10]; 5841 5842 u8 reserved_at_40[0x8]; 5843 u8 rmpn[0x18]; 5844 5845 u8 reserved_at_60[0x20]; 5846 }; 5847 5848 struct mlx5_ifc_cqe_error_syndrome_bits { 5849 u8 hw_error_syndrome[0x8]; 5850 u8 hw_syndrome_type[0x4]; 5851 u8 reserved_at_c[0x4]; 5852 u8 vendor_error_syndrome[0x8]; 5853 u8 syndrome[0x8]; 5854 }; 5855 5856 struct mlx5_ifc_qp_context_extension_bits { 5857 u8 reserved_at_0[0x60]; 5858 5859 struct mlx5_ifc_cqe_error_syndrome_bits error_syndrome; 5860 5861 u8 reserved_at_80[0x580]; 5862 }; 5863 5864 struct mlx5_ifc_qpc_extension_and_pas_list_in_bits { 5865 struct mlx5_ifc_qp_context_extension_bits qpc_data_extension; 5866 5867 u8 pas[0][0x40]; 5868 }; 5869 5870 struct mlx5_ifc_qp_pas_list_in_bits { 5871 struct mlx5_ifc_cmd_pas_bits pas[0]; 5872 }; 5873 5874 union mlx5_ifc_qp_pas_or_qpc_ext_and_pas_bits { 5875 struct mlx5_ifc_qp_pas_list_in_bits qp_pas_list; 5876 struct mlx5_ifc_qpc_extension_and_pas_list_in_bits qpc_ext_and_pas_list; 5877 }; 5878 5879 struct mlx5_ifc_query_qp_out_bits { 5880 u8 status[0x8]; 5881 u8 reserved_at_8[0x18]; 5882 5883 u8 syndrome[0x20]; 5884 5885 u8 reserved_at_40[0x40]; 5886 5887 u8 opt_param_mask[0x20]; 5888 5889 u8 ece[0x20]; 5890 5891 struct mlx5_ifc_qpc_bits qpc; 5892 5893 u8 reserved_at_800[0x80]; 5894 5895 union mlx5_ifc_qp_pas_or_qpc_ext_and_pas_bits qp_pas_or_qpc_ext_and_pas; 5896 }; 5897 5898 struct mlx5_ifc_query_qp_in_bits { 5899 u8 opcode[0x10]; 5900 u8 reserved_at_10[0x10]; 5901 5902 u8 reserved_at_20[0x10]; 5903 u8 op_mod[0x10]; 5904 5905 u8 qpc_ext[0x1]; 5906 u8 reserved_at_41[0x7]; 5907 u8 qpn[0x18]; 5908 5909 u8 reserved_at_60[0x20]; 5910 }; 5911 5912 struct mlx5_ifc_query_q_counter_out_bits { 5913 u8 status[0x8]; 5914 u8 reserved_at_8[0x18]; 5915 5916 u8 syndrome[0x20]; 5917 5918 u8 reserved_at_40[0x40]; 5919 5920 u8 rx_write_requests[0x20]; 5921 5922 u8 reserved_at_a0[0x20]; 5923 5924 u8 rx_read_requests[0x20]; 5925 5926 u8 reserved_at_e0[0x20]; 5927 5928 u8 rx_atomic_requests[0x20]; 5929 5930 u8 reserved_at_120[0x20]; 5931 5932 u8 rx_dct_connect[0x20]; 5933 5934 u8 reserved_at_160[0x20]; 5935 5936 u8 out_of_buffer[0x20]; 5937 5938 u8 reserved_at_1a0[0x20]; 5939 5940 u8 out_of_sequence[0x20]; 5941 5942 u8 reserved_at_1e0[0x20]; 5943 5944 u8 duplicate_request[0x20]; 5945 5946 u8 reserved_at_220[0x20]; 5947 5948 u8 rnr_nak_retry_err[0x20]; 5949 5950 u8 reserved_at_260[0x20]; 5951 5952 u8 packet_seq_err[0x20]; 5953 5954 u8 reserved_at_2a0[0x20]; 5955 5956 u8 implied_nak_seq_err[0x20]; 5957 5958 u8 reserved_at_2e0[0x20]; 5959 5960 u8 local_ack_timeout_err[0x20]; 5961 5962 u8 reserved_at_320[0x60]; 5963 5964 u8 req_rnr_retries_exceeded[0x20]; 5965 5966 u8 reserved_at_3a0[0x20]; 5967 5968 u8 resp_local_length_error[0x20]; 5969 5970 u8 req_local_length_error[0x20]; 5971 5972 u8 resp_local_qp_error[0x20]; 5973 5974 u8 local_operation_error[0x20]; 5975 5976 u8 resp_local_protection[0x20]; 5977 5978 u8 req_local_protection[0x20]; 5979 5980 u8 resp_cqe_error[0x20]; 5981 5982 u8 req_cqe_error[0x20]; 5983 5984 u8 req_mw_binding[0x20]; 5985 5986 u8 req_bad_response[0x20]; 5987 5988 u8 req_remote_invalid_request[0x20]; 5989 5990 u8 resp_remote_invalid_request[0x20]; 5991 5992 u8 req_remote_access_errors[0x20]; 5993 5994 u8 resp_remote_access_errors[0x20]; 5995 5996 u8 req_remote_operation_errors[0x20]; 5997 5998 u8 req_transport_retries_exceeded[0x20]; 5999 6000 u8 cq_overflow[0x20]; 6001 6002 u8 resp_cqe_flush_error[0x20]; 6003 6004 u8 req_cqe_flush_error[0x20]; 6005 6006 u8 reserved_at_620[0x20]; 6007 6008 u8 roce_adp_retrans[0x20]; 6009 6010 u8 roce_adp_retrans_to[0x20]; 6011 6012 u8 roce_slow_restart[0x20]; 6013 6014 u8 roce_slow_restart_cnps[0x20]; 6015 6016 u8 roce_slow_restart_trans[0x20]; 6017 6018 u8 reserved_at_6e0[0x120]; 6019 }; 6020 6021 struct mlx5_ifc_query_q_counter_in_bits { 6022 u8 opcode[0x10]; 6023 u8 reserved_at_10[0x10]; 6024 6025 u8 reserved_at_20[0x10]; 6026 u8 op_mod[0x10]; 6027 6028 u8 other_vport[0x1]; 6029 u8 reserved_at_41[0xf]; 6030 u8 vport_number[0x10]; 6031 6032 u8 reserved_at_60[0x60]; 6033 6034 u8 clear[0x1]; 6035 u8 aggregate[0x1]; 6036 u8 reserved_at_c2[0x1e]; 6037 6038 u8 reserved_at_e0[0x18]; 6039 u8 counter_set_id[0x8]; 6040 }; 6041 6042 struct mlx5_ifc_query_pages_out_bits { 6043 u8 status[0x8]; 6044 u8 reserved_at_8[0x18]; 6045 6046 u8 syndrome[0x20]; 6047 6048 u8 embedded_cpu_function[0x1]; 6049 u8 reserved_at_41[0xf]; 6050 u8 function_id[0x10]; 6051 6052 u8 num_pages[0x20]; 6053 }; 6054 6055 enum { 6056 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1, 6057 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2, 6058 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3, 6059 }; 6060 6061 struct mlx5_ifc_query_pages_in_bits { 6062 u8 opcode[0x10]; 6063 u8 reserved_at_10[0x10]; 6064 6065 u8 reserved_at_20[0x10]; 6066 u8 op_mod[0x10]; 6067 6068 u8 embedded_cpu_function[0x1]; 6069 u8 reserved_at_41[0xf]; 6070 u8 function_id[0x10]; 6071 6072 u8 reserved_at_60[0x20]; 6073 }; 6074 6075 struct mlx5_ifc_query_nic_vport_context_out_bits { 6076 u8 status[0x8]; 6077 u8 reserved_at_8[0x18]; 6078 6079 u8 syndrome[0x20]; 6080 6081 u8 reserved_at_40[0x40]; 6082 6083 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 6084 }; 6085 6086 struct mlx5_ifc_query_nic_vport_context_in_bits { 6087 u8 opcode[0x10]; 6088 u8 reserved_at_10[0x10]; 6089 6090 u8 reserved_at_20[0x10]; 6091 u8 op_mod[0x10]; 6092 6093 u8 other_vport[0x1]; 6094 u8 reserved_at_41[0xf]; 6095 u8 vport_number[0x10]; 6096 6097 u8 reserved_at_60[0x5]; 6098 u8 allowed_list_type[0x3]; 6099 u8 reserved_at_68[0x18]; 6100 }; 6101 6102 struct mlx5_ifc_query_mkey_out_bits { 6103 u8 status[0x8]; 6104 u8 reserved_at_8[0x18]; 6105 6106 u8 syndrome[0x20]; 6107 6108 u8 reserved_at_40[0x40]; 6109 6110 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 6111 6112 u8 reserved_at_280[0x600]; 6113 6114 u8 bsf0_klm0_pas_mtt0_1[16][0x8]; 6115 6116 u8 bsf1_klm1_pas_mtt2_3[16][0x8]; 6117 }; 6118 6119 struct mlx5_ifc_query_mkey_in_bits { 6120 u8 opcode[0x10]; 6121 u8 reserved_at_10[0x10]; 6122 6123 u8 reserved_at_20[0x10]; 6124 u8 op_mod[0x10]; 6125 6126 u8 reserved_at_40[0x8]; 6127 u8 mkey_index[0x18]; 6128 6129 u8 pg_access[0x1]; 6130 u8 reserved_at_61[0x1f]; 6131 }; 6132 6133 struct mlx5_ifc_query_mad_demux_out_bits { 6134 u8 status[0x8]; 6135 u8 reserved_at_8[0x18]; 6136 6137 u8 syndrome[0x20]; 6138 6139 u8 reserved_at_40[0x40]; 6140 6141 u8 mad_dumux_parameters_block[0x20]; 6142 }; 6143 6144 struct mlx5_ifc_query_mad_demux_in_bits { 6145 u8 opcode[0x10]; 6146 u8 reserved_at_10[0x10]; 6147 6148 u8 reserved_at_20[0x10]; 6149 u8 op_mod[0x10]; 6150 6151 u8 reserved_at_40[0x40]; 6152 }; 6153 6154 struct mlx5_ifc_query_l2_table_entry_out_bits { 6155 u8 status[0x8]; 6156 u8 reserved_at_8[0x18]; 6157 6158 u8 syndrome[0x20]; 6159 6160 u8 reserved_at_40[0xa0]; 6161 6162 u8 reserved_at_e0[0x13]; 6163 u8 vlan_valid[0x1]; 6164 u8 vlan[0xc]; 6165 6166 struct mlx5_ifc_mac_address_layout_bits mac_address; 6167 6168 u8 reserved_at_140[0xc0]; 6169 }; 6170 6171 struct mlx5_ifc_query_l2_table_entry_in_bits { 6172 u8 opcode[0x10]; 6173 u8 reserved_at_10[0x10]; 6174 6175 u8 reserved_at_20[0x10]; 6176 u8 op_mod[0x10]; 6177 6178 u8 reserved_at_40[0x60]; 6179 6180 u8 reserved_at_a0[0x8]; 6181 u8 table_index[0x18]; 6182 6183 u8 reserved_at_c0[0x140]; 6184 }; 6185 6186 struct mlx5_ifc_query_issi_out_bits { 6187 u8 status[0x8]; 6188 u8 reserved_at_8[0x18]; 6189 6190 u8 syndrome[0x20]; 6191 6192 u8 reserved_at_40[0x10]; 6193 u8 current_issi[0x10]; 6194 6195 u8 reserved_at_60[0xa0]; 6196 6197 u8 reserved_at_100[76][0x8]; 6198 u8 supported_issi_dw0[0x20]; 6199 }; 6200 6201 struct mlx5_ifc_query_issi_in_bits { 6202 u8 opcode[0x10]; 6203 u8 reserved_at_10[0x10]; 6204 6205 u8 reserved_at_20[0x10]; 6206 u8 op_mod[0x10]; 6207 6208 u8 reserved_at_40[0x40]; 6209 }; 6210 6211 struct mlx5_ifc_set_driver_version_out_bits { 6212 u8 status[0x8]; 6213 u8 reserved_0[0x18]; 6214 6215 u8 syndrome[0x20]; 6216 u8 reserved_1[0x40]; 6217 }; 6218 6219 struct mlx5_ifc_set_driver_version_in_bits { 6220 u8 opcode[0x10]; 6221 u8 reserved_0[0x10]; 6222 6223 u8 reserved_1[0x10]; 6224 u8 op_mod[0x10]; 6225 6226 u8 reserved_2[0x40]; 6227 u8 driver_version[64][0x8]; 6228 }; 6229 6230 struct mlx5_ifc_query_hca_vport_pkey_out_bits { 6231 u8 status[0x8]; 6232 u8 reserved_at_8[0x18]; 6233 6234 u8 syndrome[0x20]; 6235 6236 u8 reserved_at_40[0x40]; 6237 6238 struct mlx5_ifc_pkey_bits pkey[]; 6239 }; 6240 6241 struct mlx5_ifc_query_hca_vport_pkey_in_bits { 6242 u8 opcode[0x10]; 6243 u8 reserved_at_10[0x10]; 6244 6245 u8 reserved_at_20[0x10]; 6246 u8 op_mod[0x10]; 6247 6248 u8 other_vport[0x1]; 6249 u8 reserved_at_41[0xb]; 6250 u8 port_num[0x4]; 6251 u8 vport_number[0x10]; 6252 6253 u8 reserved_at_60[0x10]; 6254 u8 pkey_index[0x10]; 6255 }; 6256 6257 enum { 6258 MLX5_HCA_VPORT_SEL_PORT_GUID = 1 << 0, 6259 MLX5_HCA_VPORT_SEL_NODE_GUID = 1 << 1, 6260 MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2, 6261 }; 6262 6263 struct mlx5_ifc_query_hca_vport_gid_out_bits { 6264 u8 status[0x8]; 6265 u8 reserved_at_8[0x18]; 6266 6267 u8 syndrome[0x20]; 6268 6269 u8 reserved_at_40[0x20]; 6270 6271 u8 gids_num[0x10]; 6272 u8 reserved_at_70[0x10]; 6273 6274 struct mlx5_ifc_array128_auto_bits gid[]; 6275 }; 6276 6277 struct mlx5_ifc_query_hca_vport_gid_in_bits { 6278 u8 opcode[0x10]; 6279 u8 reserved_at_10[0x10]; 6280 6281 u8 reserved_at_20[0x10]; 6282 u8 op_mod[0x10]; 6283 6284 u8 other_vport[0x1]; 6285 u8 reserved_at_41[0xb]; 6286 u8 port_num[0x4]; 6287 u8 vport_number[0x10]; 6288 6289 u8 reserved_at_60[0x10]; 6290 u8 gid_index[0x10]; 6291 }; 6292 6293 struct mlx5_ifc_query_hca_vport_context_out_bits { 6294 u8 status[0x8]; 6295 u8 reserved_at_8[0x18]; 6296 6297 u8 syndrome[0x20]; 6298 6299 u8 reserved_at_40[0x40]; 6300 6301 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 6302 }; 6303 6304 struct mlx5_ifc_query_hca_vport_context_in_bits { 6305 u8 opcode[0x10]; 6306 u8 reserved_at_10[0x10]; 6307 6308 u8 reserved_at_20[0x10]; 6309 u8 op_mod[0x10]; 6310 6311 u8 other_vport[0x1]; 6312 u8 reserved_at_41[0xb]; 6313 u8 port_num[0x4]; 6314 u8 vport_number[0x10]; 6315 6316 u8 reserved_at_60[0x20]; 6317 }; 6318 6319 struct mlx5_ifc_query_hca_cap_out_bits { 6320 u8 status[0x8]; 6321 u8 reserved_at_8[0x18]; 6322 6323 u8 syndrome[0x20]; 6324 6325 u8 reserved_at_40[0x40]; 6326 6327 union mlx5_ifc_hca_cap_union_bits capability; 6328 }; 6329 6330 struct mlx5_ifc_query_hca_cap_in_bits { 6331 u8 opcode[0x10]; 6332 u8 reserved_at_10[0x10]; 6333 6334 u8 reserved_at_20[0x10]; 6335 u8 op_mod[0x10]; 6336 6337 u8 other_function[0x1]; 6338 u8 ec_vf_function[0x1]; 6339 u8 reserved_at_42[0xe]; 6340 u8 function_id[0x10]; 6341 6342 u8 reserved_at_60[0x20]; 6343 }; 6344 6345 struct mlx5_ifc_other_hca_cap_bits { 6346 u8 roce[0x1]; 6347 u8 reserved_at_1[0x27f]; 6348 }; 6349 6350 struct mlx5_ifc_query_other_hca_cap_out_bits { 6351 u8 status[0x8]; 6352 u8 reserved_at_8[0x18]; 6353 6354 u8 syndrome[0x20]; 6355 6356 u8 reserved_at_40[0x40]; 6357 6358 struct mlx5_ifc_other_hca_cap_bits other_capability; 6359 }; 6360 6361 struct mlx5_ifc_query_other_hca_cap_in_bits { 6362 u8 opcode[0x10]; 6363 u8 reserved_at_10[0x10]; 6364 6365 u8 reserved_at_20[0x10]; 6366 u8 op_mod[0x10]; 6367 6368 u8 reserved_at_40[0x10]; 6369 u8 function_id[0x10]; 6370 6371 u8 reserved_at_60[0x20]; 6372 }; 6373 6374 struct mlx5_ifc_modify_other_hca_cap_out_bits { 6375 u8 status[0x8]; 6376 u8 reserved_at_8[0x18]; 6377 6378 u8 syndrome[0x20]; 6379 6380 u8 reserved_at_40[0x40]; 6381 }; 6382 6383 struct mlx5_ifc_modify_other_hca_cap_in_bits { 6384 u8 opcode[0x10]; 6385 u8 reserved_at_10[0x10]; 6386 6387 u8 reserved_at_20[0x10]; 6388 u8 op_mod[0x10]; 6389 6390 u8 reserved_at_40[0x10]; 6391 u8 function_id[0x10]; 6392 u8 field_select[0x20]; 6393 6394 struct mlx5_ifc_other_hca_cap_bits other_capability; 6395 }; 6396 6397 struct mlx5_ifc_sw_owner_icm_root_params_bits { 6398 u8 sw_owner_icm_root_1[0x40]; 6399 6400 u8 sw_owner_icm_root_0[0x40]; 6401 }; 6402 6403 struct mlx5_ifc_rtc_params_bits { 6404 u8 rtc_id_0[0x20]; 6405 6406 u8 rtc_id_1[0x20]; 6407 6408 u8 reserved_at_40[0x40]; 6409 }; 6410 6411 struct mlx5_ifc_flow_table_context_bits { 6412 u8 reformat_en[0x1]; 6413 u8 decap_en[0x1]; 6414 u8 sw_owner[0x1]; 6415 u8 termination_table[0x1]; 6416 u8 table_miss_action[0x4]; 6417 u8 level[0x8]; 6418 u8 rtc_valid[0x1]; 6419 u8 reserved_at_11[0x7]; 6420 u8 log_size[0x8]; 6421 6422 u8 reserved_at_20[0x8]; 6423 u8 table_miss_id[0x18]; 6424 6425 u8 reserved_at_40[0x8]; 6426 u8 lag_master_next_table_id[0x18]; 6427 6428 u8 reserved_at_60[0x60]; 6429 6430 union { 6431 struct mlx5_ifc_sw_owner_icm_root_params_bits sws; 6432 struct mlx5_ifc_rtc_params_bits hws; 6433 }; 6434 }; 6435 6436 struct mlx5_ifc_query_flow_table_out_bits { 6437 u8 status[0x8]; 6438 u8 reserved_at_8[0x18]; 6439 6440 u8 syndrome[0x20]; 6441 6442 u8 reserved_at_40[0x80]; 6443 6444 struct mlx5_ifc_flow_table_context_bits flow_table_context; 6445 }; 6446 6447 struct mlx5_ifc_query_flow_table_in_bits { 6448 u8 opcode[0x10]; 6449 u8 reserved_at_10[0x10]; 6450 6451 u8 reserved_at_20[0x10]; 6452 u8 op_mod[0x10]; 6453 6454 u8 reserved_at_40[0x40]; 6455 6456 u8 table_type[0x8]; 6457 u8 reserved_at_88[0x18]; 6458 6459 u8 reserved_at_a0[0x8]; 6460 u8 table_id[0x18]; 6461 6462 u8 reserved_at_c0[0x140]; 6463 }; 6464 6465 struct mlx5_ifc_query_fte_out_bits { 6466 u8 status[0x8]; 6467 u8 reserved_at_8[0x18]; 6468 6469 u8 syndrome[0x20]; 6470 6471 u8 reserved_at_40[0x1c0]; 6472 6473 struct mlx5_ifc_flow_context_bits flow_context; 6474 }; 6475 6476 struct mlx5_ifc_query_fte_in_bits { 6477 u8 opcode[0x10]; 6478 u8 reserved_at_10[0x10]; 6479 6480 u8 reserved_at_20[0x10]; 6481 u8 op_mod[0x10]; 6482 6483 u8 reserved_at_40[0x40]; 6484 6485 u8 table_type[0x8]; 6486 u8 reserved_at_88[0x18]; 6487 6488 u8 reserved_at_a0[0x8]; 6489 u8 table_id[0x18]; 6490 6491 u8 reserved_at_c0[0x40]; 6492 6493 u8 flow_index[0x20]; 6494 6495 u8 reserved_at_120[0xe0]; 6496 }; 6497 6498 struct mlx5_ifc_match_definer_format_0_bits { 6499 u8 reserved_at_0[0x100]; 6500 6501 u8 metadata_reg_c_0[0x20]; 6502 6503 u8 metadata_reg_c_1[0x20]; 6504 6505 u8 outer_dmac_47_16[0x20]; 6506 6507 u8 outer_dmac_15_0[0x10]; 6508 u8 outer_ethertype[0x10]; 6509 6510 u8 reserved_at_180[0x1]; 6511 u8 sx_sniffer[0x1]; 6512 u8 functional_lb[0x1]; 6513 u8 outer_ip_frag[0x1]; 6514 u8 outer_qp_type[0x2]; 6515 u8 outer_encap_type[0x2]; 6516 u8 port_number[0x2]; 6517 u8 outer_l3_type[0x2]; 6518 u8 outer_l4_type[0x2]; 6519 u8 outer_first_vlan_type[0x2]; 6520 u8 outer_first_vlan_prio[0x3]; 6521 u8 outer_first_vlan_cfi[0x1]; 6522 u8 outer_first_vlan_vid[0xc]; 6523 6524 u8 outer_l4_type_ext[0x4]; 6525 u8 reserved_at_1a4[0x2]; 6526 u8 outer_ipsec_layer[0x2]; 6527 u8 outer_l2_type[0x2]; 6528 u8 force_lb[0x1]; 6529 u8 outer_l2_ok[0x1]; 6530 u8 outer_l3_ok[0x1]; 6531 u8 outer_l4_ok[0x1]; 6532 u8 outer_second_vlan_type[0x2]; 6533 u8 outer_second_vlan_prio[0x3]; 6534 u8 outer_second_vlan_cfi[0x1]; 6535 u8 outer_second_vlan_vid[0xc]; 6536 6537 u8 outer_smac_47_16[0x20]; 6538 6539 u8 outer_smac_15_0[0x10]; 6540 u8 inner_ipv4_checksum_ok[0x1]; 6541 u8 inner_l4_checksum_ok[0x1]; 6542 u8 outer_ipv4_checksum_ok[0x1]; 6543 u8 outer_l4_checksum_ok[0x1]; 6544 u8 inner_l3_ok[0x1]; 6545 u8 inner_l4_ok[0x1]; 6546 u8 outer_l3_ok_duplicate[0x1]; 6547 u8 outer_l4_ok_duplicate[0x1]; 6548 u8 outer_tcp_cwr[0x1]; 6549 u8 outer_tcp_ece[0x1]; 6550 u8 outer_tcp_urg[0x1]; 6551 u8 outer_tcp_ack[0x1]; 6552 u8 outer_tcp_psh[0x1]; 6553 u8 outer_tcp_rst[0x1]; 6554 u8 outer_tcp_syn[0x1]; 6555 u8 outer_tcp_fin[0x1]; 6556 }; 6557 6558 struct mlx5_ifc_match_definer_format_22_bits { 6559 u8 reserved_at_0[0x100]; 6560 6561 u8 outer_ip_src_addr[0x20]; 6562 6563 u8 outer_ip_dest_addr[0x20]; 6564 6565 u8 outer_l4_sport[0x10]; 6566 u8 outer_l4_dport[0x10]; 6567 6568 u8 reserved_at_160[0x1]; 6569 u8 sx_sniffer[0x1]; 6570 u8 functional_lb[0x1]; 6571 u8 outer_ip_frag[0x1]; 6572 u8 outer_qp_type[0x2]; 6573 u8 outer_encap_type[0x2]; 6574 u8 port_number[0x2]; 6575 u8 outer_l3_type[0x2]; 6576 u8 outer_l4_type[0x2]; 6577 u8 outer_first_vlan_type[0x2]; 6578 u8 outer_first_vlan_prio[0x3]; 6579 u8 outer_first_vlan_cfi[0x1]; 6580 u8 outer_first_vlan_vid[0xc]; 6581 6582 u8 metadata_reg_c_0[0x20]; 6583 6584 u8 outer_dmac_47_16[0x20]; 6585 6586 u8 outer_smac_47_16[0x20]; 6587 6588 u8 outer_smac_15_0[0x10]; 6589 u8 outer_dmac_15_0[0x10]; 6590 }; 6591 6592 struct mlx5_ifc_match_definer_format_23_bits { 6593 u8 reserved_at_0[0x100]; 6594 6595 u8 inner_ip_src_addr[0x20]; 6596 6597 u8 inner_ip_dest_addr[0x20]; 6598 6599 u8 inner_l4_sport[0x10]; 6600 u8 inner_l4_dport[0x10]; 6601 6602 u8 reserved_at_160[0x1]; 6603 u8 sx_sniffer[0x1]; 6604 u8 functional_lb[0x1]; 6605 u8 inner_ip_frag[0x1]; 6606 u8 inner_qp_type[0x2]; 6607 u8 inner_encap_type[0x2]; 6608 u8 port_number[0x2]; 6609 u8 inner_l3_type[0x2]; 6610 u8 inner_l4_type[0x2]; 6611 u8 inner_first_vlan_type[0x2]; 6612 u8 inner_first_vlan_prio[0x3]; 6613 u8 inner_first_vlan_cfi[0x1]; 6614 u8 inner_first_vlan_vid[0xc]; 6615 6616 u8 tunnel_header_0[0x20]; 6617 6618 u8 inner_dmac_47_16[0x20]; 6619 6620 u8 inner_smac_47_16[0x20]; 6621 6622 u8 inner_smac_15_0[0x10]; 6623 u8 inner_dmac_15_0[0x10]; 6624 }; 6625 6626 struct mlx5_ifc_match_definer_format_29_bits { 6627 u8 reserved_at_0[0xc0]; 6628 6629 u8 outer_ip_dest_addr[0x80]; 6630 6631 u8 outer_ip_src_addr[0x80]; 6632 6633 u8 outer_l4_sport[0x10]; 6634 u8 outer_l4_dport[0x10]; 6635 6636 u8 reserved_at_1e0[0x20]; 6637 }; 6638 6639 struct mlx5_ifc_match_definer_format_30_bits { 6640 u8 reserved_at_0[0xa0]; 6641 6642 u8 outer_ip_dest_addr[0x80]; 6643 6644 u8 outer_ip_src_addr[0x80]; 6645 6646 u8 outer_dmac_47_16[0x20]; 6647 6648 u8 outer_smac_47_16[0x20]; 6649 6650 u8 outer_smac_15_0[0x10]; 6651 u8 outer_dmac_15_0[0x10]; 6652 }; 6653 6654 struct mlx5_ifc_match_definer_format_31_bits { 6655 u8 reserved_at_0[0xc0]; 6656 6657 u8 inner_ip_dest_addr[0x80]; 6658 6659 u8 inner_ip_src_addr[0x80]; 6660 6661 u8 inner_l4_sport[0x10]; 6662 u8 inner_l4_dport[0x10]; 6663 6664 u8 reserved_at_1e0[0x20]; 6665 }; 6666 6667 struct mlx5_ifc_match_definer_format_32_bits { 6668 u8 reserved_at_0[0xa0]; 6669 6670 u8 inner_ip_dest_addr[0x80]; 6671 6672 u8 inner_ip_src_addr[0x80]; 6673 6674 u8 inner_dmac_47_16[0x20]; 6675 6676 u8 inner_smac_47_16[0x20]; 6677 6678 u8 inner_smac_15_0[0x10]; 6679 u8 inner_dmac_15_0[0x10]; 6680 }; 6681 6682 enum { 6683 MLX5_IFC_DEFINER_FORMAT_ID_SELECT = 61, 6684 }; 6685 6686 #define MLX5_IFC_DEFINER_FORMAT_OFFSET_UNUSED 0x0 6687 #define MLX5_IFC_DEFINER_FORMAT_OFFSET_OUTER_ETH_PKT_LEN 0x48 6688 #define MLX5_IFC_DEFINER_DW_SELECTORS_NUM 9 6689 #define MLX5_IFC_DEFINER_BYTE_SELECTORS_NUM 8 6690 6691 struct mlx5_ifc_match_definer_match_mask_bits { 6692 u8 reserved_at_1c0[5][0x20]; 6693 u8 match_dw_8[0x20]; 6694 u8 match_dw_7[0x20]; 6695 u8 match_dw_6[0x20]; 6696 u8 match_dw_5[0x20]; 6697 u8 match_dw_4[0x20]; 6698 u8 match_dw_3[0x20]; 6699 u8 match_dw_2[0x20]; 6700 u8 match_dw_1[0x20]; 6701 u8 match_dw_0[0x20]; 6702 6703 u8 match_byte_7[0x8]; 6704 u8 match_byte_6[0x8]; 6705 u8 match_byte_5[0x8]; 6706 u8 match_byte_4[0x8]; 6707 6708 u8 match_byte_3[0x8]; 6709 u8 match_byte_2[0x8]; 6710 u8 match_byte_1[0x8]; 6711 u8 match_byte_0[0x8]; 6712 }; 6713 6714 struct mlx5_ifc_match_definer_bits { 6715 u8 modify_field_select[0x40]; 6716 6717 u8 reserved_at_40[0x40]; 6718 6719 u8 reserved_at_80[0x10]; 6720 u8 format_id[0x10]; 6721 6722 u8 reserved_at_a0[0x60]; 6723 6724 u8 format_select_dw3[0x8]; 6725 u8 format_select_dw2[0x8]; 6726 u8 format_select_dw1[0x8]; 6727 u8 format_select_dw0[0x8]; 6728 6729 u8 format_select_dw7[0x8]; 6730 u8 format_select_dw6[0x8]; 6731 u8 format_select_dw5[0x8]; 6732 u8 format_select_dw4[0x8]; 6733 6734 u8 reserved_at_100[0x18]; 6735 u8 format_select_dw8[0x8]; 6736 6737 u8 reserved_at_120[0x20]; 6738 6739 u8 format_select_byte3[0x8]; 6740 u8 format_select_byte2[0x8]; 6741 u8 format_select_byte1[0x8]; 6742 u8 format_select_byte0[0x8]; 6743 6744 u8 format_select_byte7[0x8]; 6745 u8 format_select_byte6[0x8]; 6746 u8 format_select_byte5[0x8]; 6747 u8 format_select_byte4[0x8]; 6748 6749 u8 reserved_at_180[0x40]; 6750 6751 union { 6752 struct { 6753 u8 match_mask[16][0x20]; 6754 }; 6755 struct mlx5_ifc_match_definer_match_mask_bits match_mask_format; 6756 }; 6757 }; 6758 6759 struct mlx5_ifc_general_obj_create_param_bits { 6760 u8 alias_object[0x1]; 6761 u8 reserved_at_1[0x2]; 6762 u8 log_obj_range[0x5]; 6763 u8 reserved_at_8[0x18]; 6764 }; 6765 6766 struct mlx5_ifc_general_obj_query_param_bits { 6767 u8 alias_object[0x1]; 6768 u8 obj_offset[0x1f]; 6769 }; 6770 6771 struct mlx5_ifc_general_obj_in_cmd_hdr_bits { 6772 u8 opcode[0x10]; 6773 u8 uid[0x10]; 6774 6775 u8 vhca_tunnel_id[0x10]; 6776 u8 obj_type[0x10]; 6777 6778 u8 obj_id[0x20]; 6779 6780 union { 6781 struct mlx5_ifc_general_obj_create_param_bits create; 6782 struct mlx5_ifc_general_obj_query_param_bits query; 6783 } op_param; 6784 }; 6785 6786 struct mlx5_ifc_general_obj_out_cmd_hdr_bits { 6787 u8 status[0x8]; 6788 u8 reserved_at_8[0x18]; 6789 6790 u8 syndrome[0x20]; 6791 6792 u8 obj_id[0x20]; 6793 6794 u8 reserved_at_60[0x20]; 6795 }; 6796 6797 struct mlx5_ifc_allow_other_vhca_access_in_bits { 6798 u8 opcode[0x10]; 6799 u8 uid[0x10]; 6800 u8 reserved_at_20[0x10]; 6801 u8 op_mod[0x10]; 6802 u8 reserved_at_40[0x50]; 6803 u8 object_type_to_be_accessed[0x10]; 6804 u8 object_id_to_be_accessed[0x20]; 6805 u8 reserved_at_c0[0x40]; 6806 union { 6807 u8 access_key_raw[0x100]; 6808 u8 access_key[8][0x20]; 6809 }; 6810 }; 6811 6812 struct mlx5_ifc_allow_other_vhca_access_out_bits { 6813 u8 status[0x8]; 6814 u8 reserved_at_8[0x18]; 6815 u8 syndrome[0x20]; 6816 u8 reserved_at_40[0x40]; 6817 }; 6818 6819 struct mlx5_ifc_modify_header_arg_bits { 6820 u8 reserved_at_0[0x80]; 6821 6822 u8 reserved_at_80[0x8]; 6823 u8 access_pd[0x18]; 6824 }; 6825 6826 struct mlx5_ifc_create_modify_header_arg_in_bits { 6827 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 6828 struct mlx5_ifc_modify_header_arg_bits arg; 6829 }; 6830 6831 struct mlx5_ifc_create_match_definer_in_bits { 6832 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 6833 6834 struct mlx5_ifc_match_definer_bits obj_context; 6835 }; 6836 6837 struct mlx5_ifc_create_match_definer_out_bits { 6838 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 6839 }; 6840 6841 struct mlx5_ifc_alias_context_bits { 6842 u8 vhca_id_to_be_accessed[0x10]; 6843 u8 reserved_at_10[0xd]; 6844 u8 status[0x3]; 6845 u8 object_id_to_be_accessed[0x20]; 6846 u8 reserved_at_40[0x40]; 6847 union { 6848 u8 access_key_raw[0x100]; 6849 u8 access_key[8][0x20]; 6850 }; 6851 u8 metadata[0x80]; 6852 }; 6853 6854 struct mlx5_ifc_create_alias_obj_in_bits { 6855 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 6856 struct mlx5_ifc_alias_context_bits alias_ctx; 6857 }; 6858 6859 enum { 6860 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 6861 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 6862 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 6863 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3, 6864 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_3 = 0x4, 6865 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_4 = 0x5, 6866 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_5 = 0x6, 6867 }; 6868 6869 struct mlx5_ifc_query_flow_group_out_bits { 6870 u8 status[0x8]; 6871 u8 reserved_at_8[0x18]; 6872 6873 u8 syndrome[0x20]; 6874 6875 u8 reserved_at_40[0xa0]; 6876 6877 u8 start_flow_index[0x20]; 6878 6879 u8 reserved_at_100[0x20]; 6880 6881 u8 end_flow_index[0x20]; 6882 6883 u8 reserved_at_140[0xa0]; 6884 6885 u8 reserved_at_1e0[0x18]; 6886 u8 match_criteria_enable[0x8]; 6887 6888 struct mlx5_ifc_fte_match_param_bits match_criteria; 6889 6890 u8 reserved_at_1200[0xe00]; 6891 }; 6892 6893 struct mlx5_ifc_query_flow_group_in_bits { 6894 u8 opcode[0x10]; 6895 u8 reserved_at_10[0x10]; 6896 6897 u8 reserved_at_20[0x10]; 6898 u8 op_mod[0x10]; 6899 6900 u8 reserved_at_40[0x40]; 6901 6902 u8 table_type[0x8]; 6903 u8 reserved_at_88[0x18]; 6904 6905 u8 reserved_at_a0[0x8]; 6906 u8 table_id[0x18]; 6907 6908 u8 group_id[0x20]; 6909 6910 u8 reserved_at_e0[0x120]; 6911 }; 6912 6913 struct mlx5_ifc_query_flow_counter_out_bits { 6914 u8 status[0x8]; 6915 u8 reserved_at_8[0x18]; 6916 6917 u8 syndrome[0x20]; 6918 6919 u8 reserved_at_40[0x40]; 6920 6921 struct mlx5_ifc_traffic_counter_bits flow_statistics[]; 6922 }; 6923 6924 struct mlx5_ifc_query_flow_counter_in_bits { 6925 u8 opcode[0x10]; 6926 u8 reserved_at_10[0x10]; 6927 6928 u8 reserved_at_20[0x10]; 6929 u8 op_mod[0x10]; 6930 6931 u8 reserved_at_40[0x80]; 6932 6933 u8 clear[0x1]; 6934 u8 reserved_at_c1[0xf]; 6935 u8 num_of_counters[0x10]; 6936 6937 u8 flow_counter_id[0x20]; 6938 }; 6939 6940 struct mlx5_ifc_query_esw_vport_context_out_bits { 6941 u8 status[0x8]; 6942 u8 reserved_at_8[0x18]; 6943 6944 u8 syndrome[0x20]; 6945 6946 u8 reserved_at_40[0x40]; 6947 6948 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 6949 }; 6950 6951 struct mlx5_ifc_query_esw_vport_context_in_bits { 6952 u8 opcode[0x10]; 6953 u8 reserved_at_10[0x10]; 6954 6955 u8 reserved_at_20[0x10]; 6956 u8 op_mod[0x10]; 6957 6958 u8 other_vport[0x1]; 6959 u8 reserved_at_41[0xf]; 6960 u8 vport_number[0x10]; 6961 6962 u8 reserved_at_60[0x20]; 6963 }; 6964 6965 struct mlx5_ifc_modify_esw_vport_context_out_bits { 6966 u8 status[0x8]; 6967 u8 reserved_at_8[0x18]; 6968 6969 u8 syndrome[0x20]; 6970 6971 u8 reserved_at_40[0x40]; 6972 }; 6973 6974 struct mlx5_ifc_esw_vport_context_fields_select_bits { 6975 u8 reserved_at_0[0x1b]; 6976 u8 fdb_to_vport_reg_c_id[0x1]; 6977 u8 vport_cvlan_insert[0x1]; 6978 u8 vport_svlan_insert[0x1]; 6979 u8 vport_cvlan_strip[0x1]; 6980 u8 vport_svlan_strip[0x1]; 6981 }; 6982 6983 struct mlx5_ifc_modify_esw_vport_context_in_bits { 6984 u8 opcode[0x10]; 6985 u8 reserved_at_10[0x10]; 6986 6987 u8 reserved_at_20[0x10]; 6988 u8 op_mod[0x10]; 6989 6990 u8 other_vport[0x1]; 6991 u8 reserved_at_41[0xf]; 6992 u8 vport_number[0x10]; 6993 6994 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select; 6995 6996 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 6997 }; 6998 6999 struct mlx5_ifc_query_eq_out_bits { 7000 u8 status[0x8]; 7001 u8 reserved_at_8[0x18]; 7002 7003 u8 syndrome[0x20]; 7004 7005 u8 reserved_at_40[0x40]; 7006 7007 struct mlx5_ifc_eqc_bits eq_context_entry; 7008 7009 u8 reserved_at_280[0x40]; 7010 7011 u8 event_bitmask[0x40]; 7012 7013 u8 reserved_at_300[0x580]; 7014 7015 u8 pas[][0x40]; 7016 }; 7017 7018 struct mlx5_ifc_query_eq_in_bits { 7019 u8 opcode[0x10]; 7020 u8 reserved_at_10[0x10]; 7021 7022 u8 reserved_at_20[0x10]; 7023 u8 op_mod[0x10]; 7024 7025 u8 reserved_at_40[0x18]; 7026 u8 eq_number[0x8]; 7027 7028 u8 reserved_at_60[0x20]; 7029 }; 7030 7031 struct mlx5_ifc_packet_reformat_context_in_bits { 7032 u8 reformat_type[0x8]; 7033 u8 reserved_at_8[0x4]; 7034 u8 reformat_param_0[0x4]; 7035 u8 reserved_at_10[0x6]; 7036 u8 reformat_data_size[0xa]; 7037 7038 u8 reformat_param_1[0x8]; 7039 u8 reserved_at_28[0x8]; 7040 u8 reformat_data[2][0x8]; 7041 7042 u8 more_reformat_data[][0x8]; 7043 }; 7044 7045 struct mlx5_ifc_query_packet_reformat_context_out_bits { 7046 u8 status[0x8]; 7047 u8 reserved_at_8[0x18]; 7048 7049 u8 syndrome[0x20]; 7050 7051 u8 reserved_at_40[0xa0]; 7052 7053 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context[]; 7054 }; 7055 7056 struct mlx5_ifc_query_packet_reformat_context_in_bits { 7057 u8 opcode[0x10]; 7058 u8 reserved_at_10[0x10]; 7059 7060 u8 reserved_at_20[0x10]; 7061 u8 op_mod[0x10]; 7062 7063 u8 packet_reformat_id[0x20]; 7064 7065 u8 reserved_at_60[0xa0]; 7066 }; 7067 7068 struct mlx5_ifc_alloc_packet_reformat_context_out_bits { 7069 u8 status[0x8]; 7070 u8 reserved_at_8[0x18]; 7071 7072 u8 syndrome[0x20]; 7073 7074 u8 packet_reformat_id[0x20]; 7075 7076 u8 reserved_at_60[0x20]; 7077 }; 7078 7079 enum { 7080 MLX5_REFORMAT_CONTEXT_ANCHOR_MAC_START = 0x1, 7081 MLX5_REFORMAT_CONTEXT_ANCHOR_VLAN_START = 0x2, 7082 MLX5_REFORMAT_CONTEXT_ANCHOR_IP_START = 0x7, 7083 MLX5_REFORMAT_CONTEXT_ANCHOR_TCP_UDP_START = 0x9, 7084 }; 7085 7086 enum mlx5_reformat_ctx_type { 7087 MLX5_REFORMAT_TYPE_L2_TO_VXLAN = 0x0, 7088 MLX5_REFORMAT_TYPE_L2_TO_NVGRE = 0x1, 7089 MLX5_REFORMAT_TYPE_L2_TO_L2_TUNNEL = 0x2, 7090 MLX5_REFORMAT_TYPE_L3_TUNNEL_TO_L2 = 0x3, 7091 MLX5_REFORMAT_TYPE_L2_TO_L3_TUNNEL = 0x4, 7092 MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_IPV4 = 0x5, 7093 MLX5_REFORMAT_TYPE_L2_TO_L3_ESP_TUNNEL = 0x6, 7094 MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_UDPV4 = 0x7, 7095 MLX5_REFORMAT_TYPE_DEL_ESP_TRANSPORT = 0x8, 7096 MLX5_REFORMAT_TYPE_L3_ESP_TUNNEL_TO_L2 = 0x9, 7097 MLX5_REFORMAT_TYPE_DEL_ESP_TRANSPORT_OVER_UDP = 0xa, 7098 MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_IPV6 = 0xb, 7099 MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_UDPV6 = 0xc, 7100 MLX5_REFORMAT_TYPE_INSERT_HDR = 0xf, 7101 MLX5_REFORMAT_TYPE_REMOVE_HDR = 0x10, 7102 MLX5_REFORMAT_TYPE_ADD_MACSEC = 0x11, 7103 MLX5_REFORMAT_TYPE_DEL_MACSEC = 0x12, 7104 }; 7105 7106 struct mlx5_ifc_alloc_packet_reformat_context_in_bits { 7107 u8 opcode[0x10]; 7108 u8 reserved_at_10[0x10]; 7109 7110 u8 reserved_at_20[0x10]; 7111 u8 op_mod[0x10]; 7112 7113 u8 reserved_at_40[0xa0]; 7114 7115 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context; 7116 }; 7117 7118 struct mlx5_ifc_dealloc_packet_reformat_context_out_bits { 7119 u8 status[0x8]; 7120 u8 reserved_at_8[0x18]; 7121 7122 u8 syndrome[0x20]; 7123 7124 u8 reserved_at_40[0x40]; 7125 }; 7126 7127 struct mlx5_ifc_dealloc_packet_reformat_context_in_bits { 7128 u8 opcode[0x10]; 7129 u8 reserved_at_10[0x10]; 7130 7131 u8 reserved_20[0x10]; 7132 u8 op_mod[0x10]; 7133 7134 u8 packet_reformat_id[0x20]; 7135 7136 u8 reserved_60[0x20]; 7137 }; 7138 7139 struct mlx5_ifc_set_action_in_bits { 7140 u8 action_type[0x4]; 7141 u8 field[0xc]; 7142 u8 reserved_at_10[0x3]; 7143 u8 offset[0x5]; 7144 u8 reserved_at_18[0x3]; 7145 u8 length[0x5]; 7146 7147 u8 data[0x20]; 7148 }; 7149 7150 struct mlx5_ifc_add_action_in_bits { 7151 u8 action_type[0x4]; 7152 u8 field[0xc]; 7153 u8 reserved_at_10[0x10]; 7154 7155 u8 data[0x20]; 7156 }; 7157 7158 struct mlx5_ifc_copy_action_in_bits { 7159 u8 action_type[0x4]; 7160 u8 src_field[0xc]; 7161 u8 reserved_at_10[0x3]; 7162 u8 src_offset[0x5]; 7163 u8 reserved_at_18[0x3]; 7164 u8 length[0x5]; 7165 7166 u8 reserved_at_20[0x4]; 7167 u8 dst_field[0xc]; 7168 u8 reserved_at_30[0x3]; 7169 u8 dst_offset[0x5]; 7170 u8 reserved_at_38[0x8]; 7171 }; 7172 7173 union mlx5_ifc_set_add_copy_action_in_auto_bits { 7174 struct mlx5_ifc_set_action_in_bits set_action_in; 7175 struct mlx5_ifc_add_action_in_bits add_action_in; 7176 struct mlx5_ifc_copy_action_in_bits copy_action_in; 7177 u8 reserved_at_0[0x40]; 7178 }; 7179 7180 enum { 7181 MLX5_ACTION_TYPE_SET = 0x1, 7182 MLX5_ACTION_TYPE_ADD = 0x2, 7183 MLX5_ACTION_TYPE_COPY = 0x3, 7184 }; 7185 7186 enum { 7187 MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16 = 0x1, 7188 MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0 = 0x2, 7189 MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE = 0x3, 7190 MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16 = 0x4, 7191 MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0 = 0x5, 7192 MLX5_ACTION_IN_FIELD_OUT_IP_DSCP = 0x6, 7193 MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS = 0x7, 7194 MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT = 0x8, 7195 MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT = 0x9, 7196 MLX5_ACTION_IN_FIELD_OUT_IP_TTL = 0xa, 7197 MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT = 0xb, 7198 MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT = 0xc, 7199 MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96 = 0xd, 7200 MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64 = 0xe, 7201 MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32 = 0xf, 7202 MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0 = 0x10, 7203 MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96 = 0x11, 7204 MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64 = 0x12, 7205 MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32 = 0x13, 7206 MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0 = 0x14, 7207 MLX5_ACTION_IN_FIELD_OUT_SIPV4 = 0x15, 7208 MLX5_ACTION_IN_FIELD_OUT_DIPV4 = 0x16, 7209 MLX5_ACTION_IN_FIELD_OUT_FIRST_VID = 0x17, 7210 MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47, 7211 MLX5_ACTION_IN_FIELD_METADATA_REG_A = 0x49, 7212 MLX5_ACTION_IN_FIELD_METADATA_REG_B = 0x50, 7213 MLX5_ACTION_IN_FIELD_METADATA_REG_C_0 = 0x51, 7214 MLX5_ACTION_IN_FIELD_METADATA_REG_C_1 = 0x52, 7215 MLX5_ACTION_IN_FIELD_METADATA_REG_C_2 = 0x53, 7216 MLX5_ACTION_IN_FIELD_METADATA_REG_C_3 = 0x54, 7217 MLX5_ACTION_IN_FIELD_METADATA_REG_C_4 = 0x55, 7218 MLX5_ACTION_IN_FIELD_METADATA_REG_C_5 = 0x56, 7219 MLX5_ACTION_IN_FIELD_METADATA_REG_C_6 = 0x57, 7220 MLX5_ACTION_IN_FIELD_METADATA_REG_C_7 = 0x58, 7221 MLX5_ACTION_IN_FIELD_OUT_TCP_SEQ_NUM = 0x59, 7222 MLX5_ACTION_IN_FIELD_OUT_TCP_ACK_NUM = 0x5B, 7223 MLX5_ACTION_IN_FIELD_IPSEC_SYNDROME = 0x5D, 7224 MLX5_ACTION_IN_FIELD_OUT_EMD_47_32 = 0x6F, 7225 MLX5_ACTION_IN_FIELD_OUT_EMD_31_0 = 0x70, 7226 }; 7227 7228 struct mlx5_ifc_alloc_modify_header_context_out_bits { 7229 u8 status[0x8]; 7230 u8 reserved_at_8[0x18]; 7231 7232 u8 syndrome[0x20]; 7233 7234 u8 modify_header_id[0x20]; 7235 7236 u8 reserved_at_60[0x20]; 7237 }; 7238 7239 struct mlx5_ifc_alloc_modify_header_context_in_bits { 7240 u8 opcode[0x10]; 7241 u8 reserved_at_10[0x10]; 7242 7243 u8 reserved_at_20[0x10]; 7244 u8 op_mod[0x10]; 7245 7246 u8 reserved_at_40[0x20]; 7247 7248 u8 table_type[0x8]; 7249 u8 reserved_at_68[0x10]; 7250 u8 num_of_actions[0x8]; 7251 7252 union mlx5_ifc_set_add_copy_action_in_auto_bits actions[]; 7253 }; 7254 7255 struct mlx5_ifc_dealloc_modify_header_context_out_bits { 7256 u8 status[0x8]; 7257 u8 reserved_at_8[0x18]; 7258 7259 u8 syndrome[0x20]; 7260 7261 u8 reserved_at_40[0x40]; 7262 }; 7263 7264 struct mlx5_ifc_dealloc_modify_header_context_in_bits { 7265 u8 opcode[0x10]; 7266 u8 reserved_at_10[0x10]; 7267 7268 u8 reserved_at_20[0x10]; 7269 u8 op_mod[0x10]; 7270 7271 u8 modify_header_id[0x20]; 7272 7273 u8 reserved_at_60[0x20]; 7274 }; 7275 7276 struct mlx5_ifc_query_modify_header_context_in_bits { 7277 u8 opcode[0x10]; 7278 u8 uid[0x10]; 7279 7280 u8 reserved_at_20[0x10]; 7281 u8 op_mod[0x10]; 7282 7283 u8 modify_header_id[0x20]; 7284 7285 u8 reserved_at_60[0xa0]; 7286 }; 7287 7288 struct mlx5_ifc_query_dct_out_bits { 7289 u8 status[0x8]; 7290 u8 reserved_at_8[0x18]; 7291 7292 u8 syndrome[0x20]; 7293 7294 u8 reserved_at_40[0x40]; 7295 7296 struct mlx5_ifc_dctc_bits dct_context_entry; 7297 7298 u8 reserved_at_280[0x180]; 7299 }; 7300 7301 struct mlx5_ifc_query_dct_in_bits { 7302 u8 opcode[0x10]; 7303 u8 reserved_at_10[0x10]; 7304 7305 u8 reserved_at_20[0x10]; 7306 u8 op_mod[0x10]; 7307 7308 u8 reserved_at_40[0x8]; 7309 u8 dctn[0x18]; 7310 7311 u8 reserved_at_60[0x20]; 7312 }; 7313 7314 struct mlx5_ifc_query_cq_out_bits { 7315 u8 status[0x8]; 7316 u8 reserved_at_8[0x18]; 7317 7318 u8 syndrome[0x20]; 7319 7320 u8 reserved_at_40[0x40]; 7321 7322 struct mlx5_ifc_cqc_bits cq_context; 7323 7324 u8 reserved_at_280[0x600]; 7325 7326 u8 pas[][0x40]; 7327 }; 7328 7329 struct mlx5_ifc_query_cq_in_bits { 7330 u8 opcode[0x10]; 7331 u8 reserved_at_10[0x10]; 7332 7333 u8 reserved_at_20[0x10]; 7334 u8 op_mod[0x10]; 7335 7336 u8 reserved_at_40[0x8]; 7337 u8 cqn[0x18]; 7338 7339 u8 reserved_at_60[0x20]; 7340 }; 7341 7342 struct mlx5_ifc_query_cong_status_out_bits { 7343 u8 status[0x8]; 7344 u8 reserved_at_8[0x18]; 7345 7346 u8 syndrome[0x20]; 7347 7348 u8 reserved_at_40[0x20]; 7349 7350 u8 enable[0x1]; 7351 u8 tag_enable[0x1]; 7352 u8 reserved_at_62[0x1e]; 7353 }; 7354 7355 struct mlx5_ifc_query_cong_status_in_bits { 7356 u8 opcode[0x10]; 7357 u8 reserved_at_10[0x10]; 7358 7359 u8 reserved_at_20[0x10]; 7360 u8 op_mod[0x10]; 7361 7362 u8 reserved_at_40[0x18]; 7363 u8 priority[0x4]; 7364 u8 cong_protocol[0x4]; 7365 7366 u8 reserved_at_60[0x20]; 7367 }; 7368 7369 struct mlx5_ifc_query_cong_statistics_out_bits { 7370 u8 status[0x8]; 7371 u8 reserved_at_8[0x18]; 7372 7373 u8 syndrome[0x20]; 7374 7375 u8 reserved_at_40[0x40]; 7376 7377 u8 rp_cur_flows[0x20]; 7378 7379 u8 sum_flows[0x20]; 7380 7381 u8 rp_cnp_ignored_high[0x20]; 7382 7383 u8 rp_cnp_ignored_low[0x20]; 7384 7385 u8 rp_cnp_handled_high[0x20]; 7386 7387 u8 rp_cnp_handled_low[0x20]; 7388 7389 u8 reserved_at_140[0x100]; 7390 7391 u8 time_stamp_high[0x20]; 7392 7393 u8 time_stamp_low[0x20]; 7394 7395 u8 accumulators_period[0x20]; 7396 7397 u8 np_ecn_marked_roce_packets_high[0x20]; 7398 7399 u8 np_ecn_marked_roce_packets_low[0x20]; 7400 7401 u8 np_cnp_sent_high[0x20]; 7402 7403 u8 np_cnp_sent_low[0x20]; 7404 7405 u8 reserved_at_320[0x560]; 7406 }; 7407 7408 struct mlx5_ifc_query_cong_statistics_in_bits { 7409 u8 opcode[0x10]; 7410 u8 reserved_at_10[0x10]; 7411 7412 u8 reserved_at_20[0x10]; 7413 u8 op_mod[0x10]; 7414 7415 u8 clear[0x1]; 7416 u8 reserved_at_41[0x1f]; 7417 7418 u8 reserved_at_60[0x20]; 7419 }; 7420 7421 struct mlx5_ifc_query_cong_params_out_bits { 7422 u8 status[0x8]; 7423 u8 reserved_at_8[0x18]; 7424 7425 u8 syndrome[0x20]; 7426 7427 u8 reserved_at_40[0x40]; 7428 7429 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 7430 }; 7431 7432 struct mlx5_ifc_query_cong_params_in_bits { 7433 u8 opcode[0x10]; 7434 u8 reserved_at_10[0x10]; 7435 7436 u8 reserved_at_20[0x10]; 7437 u8 op_mod[0x10]; 7438 7439 u8 reserved_at_40[0x1c]; 7440 u8 cong_protocol[0x4]; 7441 7442 u8 reserved_at_60[0x20]; 7443 }; 7444 7445 struct mlx5_ifc_query_adapter_out_bits { 7446 u8 status[0x8]; 7447 u8 reserved_at_8[0x18]; 7448 7449 u8 syndrome[0x20]; 7450 7451 u8 reserved_at_40[0x40]; 7452 7453 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct; 7454 }; 7455 7456 struct mlx5_ifc_query_adapter_in_bits { 7457 u8 opcode[0x10]; 7458 u8 reserved_at_10[0x10]; 7459 7460 u8 reserved_at_20[0x10]; 7461 u8 op_mod[0x10]; 7462 7463 u8 reserved_at_40[0x40]; 7464 }; 7465 7466 struct mlx5_ifc_qp_2rst_out_bits { 7467 u8 status[0x8]; 7468 u8 reserved_at_8[0x18]; 7469 7470 u8 syndrome[0x20]; 7471 7472 u8 reserved_at_40[0x40]; 7473 }; 7474 7475 struct mlx5_ifc_qp_2rst_in_bits { 7476 u8 opcode[0x10]; 7477 u8 uid[0x10]; 7478 7479 u8 reserved_at_20[0x10]; 7480 u8 op_mod[0x10]; 7481 7482 u8 reserved_at_40[0x8]; 7483 u8 qpn[0x18]; 7484 7485 u8 reserved_at_60[0x20]; 7486 }; 7487 7488 struct mlx5_ifc_qp_2err_out_bits { 7489 u8 status[0x8]; 7490 u8 reserved_at_8[0x18]; 7491 7492 u8 syndrome[0x20]; 7493 7494 u8 reserved_at_40[0x40]; 7495 }; 7496 7497 struct mlx5_ifc_qp_2err_in_bits { 7498 u8 opcode[0x10]; 7499 u8 uid[0x10]; 7500 7501 u8 reserved_at_20[0x10]; 7502 u8 op_mod[0x10]; 7503 7504 u8 reserved_at_40[0x8]; 7505 u8 qpn[0x18]; 7506 7507 u8 reserved_at_60[0x20]; 7508 }; 7509 7510 struct mlx5_ifc_trans_page_fault_info_bits { 7511 u8 error[0x1]; 7512 u8 reserved_at_1[0x4]; 7513 u8 page_fault_type[0x3]; 7514 u8 wq_number[0x18]; 7515 7516 u8 reserved_at_20[0x8]; 7517 u8 fault_token[0x18]; 7518 }; 7519 7520 struct mlx5_ifc_mem_page_fault_info_bits { 7521 u8 error[0x1]; 7522 u8 reserved_at_1[0xf]; 7523 u8 fault_token_47_32[0x10]; 7524 7525 u8 fault_token_31_0[0x20]; 7526 }; 7527 7528 union mlx5_ifc_page_fault_resume_in_page_fault_info_auto_bits { 7529 struct mlx5_ifc_trans_page_fault_info_bits trans_page_fault_info; 7530 struct mlx5_ifc_mem_page_fault_info_bits mem_page_fault_info; 7531 u8 reserved_at_0[0x40]; 7532 }; 7533 7534 struct mlx5_ifc_page_fault_resume_out_bits { 7535 u8 status[0x8]; 7536 u8 reserved_at_8[0x18]; 7537 7538 u8 syndrome[0x20]; 7539 7540 u8 reserved_at_40[0x40]; 7541 }; 7542 7543 struct mlx5_ifc_page_fault_resume_in_bits { 7544 u8 opcode[0x10]; 7545 u8 reserved_at_10[0x10]; 7546 7547 u8 reserved_at_20[0x10]; 7548 u8 op_mod[0x10]; 7549 7550 union mlx5_ifc_page_fault_resume_in_page_fault_info_auto_bits 7551 page_fault_info; 7552 }; 7553 7554 struct mlx5_ifc_nop_out_bits { 7555 u8 status[0x8]; 7556 u8 reserved_at_8[0x18]; 7557 7558 u8 syndrome[0x20]; 7559 7560 u8 reserved_at_40[0x40]; 7561 }; 7562 7563 struct mlx5_ifc_nop_in_bits { 7564 u8 opcode[0x10]; 7565 u8 reserved_at_10[0x10]; 7566 7567 u8 reserved_at_20[0x10]; 7568 u8 op_mod[0x10]; 7569 7570 u8 reserved_at_40[0x40]; 7571 }; 7572 7573 struct mlx5_ifc_modify_vport_state_out_bits { 7574 u8 status[0x8]; 7575 u8 reserved_at_8[0x18]; 7576 7577 u8 syndrome[0x20]; 7578 7579 u8 reserved_at_40[0x40]; 7580 }; 7581 7582 struct mlx5_ifc_modify_vport_state_in_bits { 7583 u8 opcode[0x10]; 7584 u8 reserved_at_10[0x10]; 7585 7586 u8 reserved_at_20[0x10]; 7587 u8 op_mod[0x10]; 7588 7589 u8 other_vport[0x1]; 7590 u8 reserved_at_41[0xf]; 7591 u8 vport_number[0x10]; 7592 7593 u8 reserved_at_60[0x18]; 7594 u8 admin_state[0x4]; 7595 u8 reserved_at_7c[0x4]; 7596 }; 7597 7598 struct mlx5_ifc_modify_tis_out_bits { 7599 u8 status[0x8]; 7600 u8 reserved_at_8[0x18]; 7601 7602 u8 syndrome[0x20]; 7603 7604 u8 reserved_at_40[0x40]; 7605 }; 7606 7607 struct mlx5_ifc_modify_tis_bitmask_bits { 7608 u8 reserved_at_0[0x20]; 7609 7610 u8 reserved_at_20[0x1d]; 7611 u8 lag_tx_port_affinity[0x1]; 7612 u8 strict_lag_tx_port_affinity[0x1]; 7613 u8 prio[0x1]; 7614 }; 7615 7616 struct mlx5_ifc_modify_tis_in_bits { 7617 u8 opcode[0x10]; 7618 u8 uid[0x10]; 7619 7620 u8 reserved_at_20[0x10]; 7621 u8 op_mod[0x10]; 7622 7623 u8 reserved_at_40[0x8]; 7624 u8 tisn[0x18]; 7625 7626 u8 reserved_at_60[0x20]; 7627 7628 struct mlx5_ifc_modify_tis_bitmask_bits bitmask; 7629 7630 u8 reserved_at_c0[0x40]; 7631 7632 struct mlx5_ifc_tisc_bits ctx; 7633 }; 7634 7635 struct mlx5_ifc_modify_tir_bitmask_bits { 7636 u8 reserved_at_0[0x20]; 7637 7638 u8 reserved_at_20[0x1b]; 7639 u8 self_lb_en[0x1]; 7640 u8 reserved_at_3c[0x1]; 7641 u8 hash[0x1]; 7642 u8 reserved_at_3e[0x1]; 7643 u8 packet_merge[0x1]; 7644 }; 7645 7646 struct mlx5_ifc_modify_tir_out_bits { 7647 u8 status[0x8]; 7648 u8 reserved_at_8[0x18]; 7649 7650 u8 syndrome[0x20]; 7651 7652 u8 reserved_at_40[0x40]; 7653 }; 7654 7655 struct mlx5_ifc_modify_tir_in_bits { 7656 u8 opcode[0x10]; 7657 u8 uid[0x10]; 7658 7659 u8 reserved_at_20[0x10]; 7660 u8 op_mod[0x10]; 7661 7662 u8 reserved_at_40[0x8]; 7663 u8 tirn[0x18]; 7664 7665 u8 reserved_at_60[0x20]; 7666 7667 struct mlx5_ifc_modify_tir_bitmask_bits bitmask; 7668 7669 u8 reserved_at_c0[0x40]; 7670 7671 struct mlx5_ifc_tirc_bits ctx; 7672 }; 7673 7674 struct mlx5_ifc_modify_sq_out_bits { 7675 u8 status[0x8]; 7676 u8 reserved_at_8[0x18]; 7677 7678 u8 syndrome[0x20]; 7679 7680 u8 reserved_at_40[0x40]; 7681 }; 7682 7683 struct mlx5_ifc_modify_sq_in_bits { 7684 u8 opcode[0x10]; 7685 u8 uid[0x10]; 7686 7687 u8 reserved_at_20[0x10]; 7688 u8 op_mod[0x10]; 7689 7690 u8 sq_state[0x4]; 7691 u8 reserved_at_44[0x4]; 7692 u8 sqn[0x18]; 7693 7694 u8 reserved_at_60[0x20]; 7695 7696 u8 modify_bitmask[0x40]; 7697 7698 u8 reserved_at_c0[0x40]; 7699 7700 struct mlx5_ifc_sqc_bits ctx; 7701 }; 7702 7703 struct mlx5_ifc_modify_scheduling_element_out_bits { 7704 u8 status[0x8]; 7705 u8 reserved_at_8[0x18]; 7706 7707 u8 syndrome[0x20]; 7708 7709 u8 reserved_at_40[0x1c0]; 7710 }; 7711 7712 enum { 7713 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1, 7714 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2, 7715 }; 7716 7717 struct mlx5_ifc_modify_scheduling_element_in_bits { 7718 u8 opcode[0x10]; 7719 u8 reserved_at_10[0x10]; 7720 7721 u8 reserved_at_20[0x10]; 7722 u8 op_mod[0x10]; 7723 7724 u8 scheduling_hierarchy[0x8]; 7725 u8 reserved_at_48[0x18]; 7726 7727 u8 scheduling_element_id[0x20]; 7728 7729 u8 reserved_at_80[0x20]; 7730 7731 u8 modify_bitmask[0x20]; 7732 7733 u8 reserved_at_c0[0x40]; 7734 7735 struct mlx5_ifc_scheduling_context_bits scheduling_context; 7736 7737 u8 reserved_at_300[0x100]; 7738 }; 7739 7740 struct mlx5_ifc_modify_rqt_out_bits { 7741 u8 status[0x8]; 7742 u8 reserved_at_8[0x18]; 7743 7744 u8 syndrome[0x20]; 7745 7746 u8 reserved_at_40[0x40]; 7747 }; 7748 7749 struct mlx5_ifc_rqt_bitmask_bits { 7750 u8 reserved_at_0[0x20]; 7751 7752 u8 reserved_at_20[0x1f]; 7753 u8 rqn_list[0x1]; 7754 }; 7755 7756 struct mlx5_ifc_modify_rqt_in_bits { 7757 u8 opcode[0x10]; 7758 u8 uid[0x10]; 7759 7760 u8 reserved_at_20[0x10]; 7761 u8 op_mod[0x10]; 7762 7763 u8 reserved_at_40[0x8]; 7764 u8 rqtn[0x18]; 7765 7766 u8 reserved_at_60[0x20]; 7767 7768 struct mlx5_ifc_rqt_bitmask_bits bitmask; 7769 7770 u8 reserved_at_c0[0x40]; 7771 7772 struct mlx5_ifc_rqtc_bits ctx; 7773 }; 7774 7775 struct mlx5_ifc_modify_rq_out_bits { 7776 u8 status[0x8]; 7777 u8 reserved_at_8[0x18]; 7778 7779 u8 syndrome[0x20]; 7780 7781 u8 reserved_at_40[0x40]; 7782 }; 7783 7784 enum { 7785 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1, 7786 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2, 7787 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3, 7788 }; 7789 7790 struct mlx5_ifc_modify_rq_in_bits { 7791 u8 opcode[0x10]; 7792 u8 uid[0x10]; 7793 7794 u8 reserved_at_20[0x10]; 7795 u8 op_mod[0x10]; 7796 7797 u8 rq_state[0x4]; 7798 u8 reserved_at_44[0x4]; 7799 u8 rqn[0x18]; 7800 7801 u8 reserved_at_60[0x20]; 7802 7803 u8 modify_bitmask[0x40]; 7804 7805 u8 reserved_at_c0[0x40]; 7806 7807 struct mlx5_ifc_rqc_bits ctx; 7808 }; 7809 7810 struct mlx5_ifc_modify_rmp_out_bits { 7811 u8 status[0x8]; 7812 u8 reserved_at_8[0x18]; 7813 7814 u8 syndrome[0x20]; 7815 7816 u8 reserved_at_40[0x40]; 7817 }; 7818 7819 struct mlx5_ifc_rmp_bitmask_bits { 7820 u8 reserved_at_0[0x20]; 7821 7822 u8 reserved_at_20[0x1f]; 7823 u8 lwm[0x1]; 7824 }; 7825 7826 struct mlx5_ifc_modify_rmp_in_bits { 7827 u8 opcode[0x10]; 7828 u8 uid[0x10]; 7829 7830 u8 reserved_at_20[0x10]; 7831 u8 op_mod[0x10]; 7832 7833 u8 rmp_state[0x4]; 7834 u8 reserved_at_44[0x4]; 7835 u8 rmpn[0x18]; 7836 7837 u8 reserved_at_60[0x20]; 7838 7839 struct mlx5_ifc_rmp_bitmask_bits bitmask; 7840 7841 u8 reserved_at_c0[0x40]; 7842 7843 struct mlx5_ifc_rmpc_bits ctx; 7844 }; 7845 7846 struct mlx5_ifc_modify_nic_vport_context_out_bits { 7847 u8 status[0x8]; 7848 u8 reserved_at_8[0x18]; 7849 7850 u8 syndrome[0x20]; 7851 7852 u8 reserved_at_40[0x40]; 7853 }; 7854 7855 struct mlx5_ifc_modify_nic_vport_field_select_bits { 7856 u8 reserved_at_0[0x12]; 7857 u8 affiliation[0x1]; 7858 u8 reserved_at_13[0x1]; 7859 u8 disable_uc_local_lb[0x1]; 7860 u8 disable_mc_local_lb[0x1]; 7861 u8 node_guid[0x1]; 7862 u8 port_guid[0x1]; 7863 u8 min_inline[0x1]; 7864 u8 mtu[0x1]; 7865 u8 change_event[0x1]; 7866 u8 promisc[0x1]; 7867 u8 permanent_address[0x1]; 7868 u8 addresses_list[0x1]; 7869 u8 roce_en[0x1]; 7870 u8 reserved_at_1f[0x1]; 7871 }; 7872 7873 struct mlx5_ifc_modify_nic_vport_context_in_bits { 7874 u8 opcode[0x10]; 7875 u8 reserved_at_10[0x10]; 7876 7877 u8 reserved_at_20[0x10]; 7878 u8 op_mod[0x10]; 7879 7880 u8 other_vport[0x1]; 7881 u8 reserved_at_41[0xf]; 7882 u8 vport_number[0x10]; 7883 7884 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select; 7885 7886 u8 reserved_at_80[0x780]; 7887 7888 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 7889 }; 7890 7891 struct mlx5_ifc_modify_hca_vport_context_out_bits { 7892 u8 status[0x8]; 7893 u8 reserved_at_8[0x18]; 7894 7895 u8 syndrome[0x20]; 7896 7897 u8 reserved_at_40[0x40]; 7898 }; 7899 7900 struct mlx5_ifc_modify_hca_vport_context_in_bits { 7901 u8 opcode[0x10]; 7902 u8 reserved_at_10[0x10]; 7903 7904 u8 reserved_at_20[0x10]; 7905 u8 op_mod[0x10]; 7906 7907 u8 other_vport[0x1]; 7908 u8 reserved_at_41[0xb]; 7909 u8 port_num[0x4]; 7910 u8 vport_number[0x10]; 7911 7912 u8 reserved_at_60[0x20]; 7913 7914 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 7915 }; 7916 7917 struct mlx5_ifc_modify_cq_out_bits { 7918 u8 status[0x8]; 7919 u8 reserved_at_8[0x18]; 7920 7921 u8 syndrome[0x20]; 7922 7923 u8 reserved_at_40[0x40]; 7924 }; 7925 7926 enum { 7927 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0, 7928 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1, 7929 }; 7930 7931 struct mlx5_ifc_modify_cq_in_bits { 7932 u8 opcode[0x10]; 7933 u8 uid[0x10]; 7934 7935 u8 reserved_at_20[0x10]; 7936 u8 op_mod[0x10]; 7937 7938 u8 reserved_at_40[0x8]; 7939 u8 cqn[0x18]; 7940 7941 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select; 7942 7943 struct mlx5_ifc_cqc_bits cq_context; 7944 7945 u8 reserved_at_280[0x60]; 7946 7947 u8 cq_umem_valid[0x1]; 7948 u8 reserved_at_2e1[0x1f]; 7949 7950 u8 reserved_at_300[0x580]; 7951 7952 u8 pas[][0x40]; 7953 }; 7954 7955 struct mlx5_ifc_modify_cong_status_out_bits { 7956 u8 status[0x8]; 7957 u8 reserved_at_8[0x18]; 7958 7959 u8 syndrome[0x20]; 7960 7961 u8 reserved_at_40[0x40]; 7962 }; 7963 7964 struct mlx5_ifc_modify_cong_status_in_bits { 7965 u8 opcode[0x10]; 7966 u8 reserved_at_10[0x10]; 7967 7968 u8 reserved_at_20[0x10]; 7969 u8 op_mod[0x10]; 7970 7971 u8 reserved_at_40[0x18]; 7972 u8 priority[0x4]; 7973 u8 cong_protocol[0x4]; 7974 7975 u8 enable[0x1]; 7976 u8 tag_enable[0x1]; 7977 u8 reserved_at_62[0x1e]; 7978 }; 7979 7980 struct mlx5_ifc_modify_cong_params_out_bits { 7981 u8 status[0x8]; 7982 u8 reserved_at_8[0x18]; 7983 7984 u8 syndrome[0x20]; 7985 7986 u8 reserved_at_40[0x40]; 7987 }; 7988 7989 struct mlx5_ifc_modify_cong_params_in_bits { 7990 u8 opcode[0x10]; 7991 u8 reserved_at_10[0x10]; 7992 7993 u8 reserved_at_20[0x10]; 7994 u8 op_mod[0x10]; 7995 7996 u8 reserved_at_40[0x1c]; 7997 u8 cong_protocol[0x4]; 7998 7999 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select; 8000 8001 u8 reserved_at_80[0x80]; 8002 8003 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 8004 }; 8005 8006 struct mlx5_ifc_manage_pages_out_bits { 8007 u8 status[0x8]; 8008 u8 reserved_at_8[0x18]; 8009 8010 u8 syndrome[0x20]; 8011 8012 u8 output_num_entries[0x20]; 8013 8014 u8 reserved_at_60[0x20]; 8015 8016 u8 pas[][0x40]; 8017 }; 8018 8019 enum { 8020 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL = 0x0, 8021 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS = 0x1, 8022 MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES = 0x2, 8023 }; 8024 8025 struct mlx5_ifc_manage_pages_in_bits { 8026 u8 opcode[0x10]; 8027 u8 reserved_at_10[0x10]; 8028 8029 u8 reserved_at_20[0x10]; 8030 u8 op_mod[0x10]; 8031 8032 u8 embedded_cpu_function[0x1]; 8033 u8 reserved_at_41[0xf]; 8034 u8 function_id[0x10]; 8035 8036 u8 input_num_entries[0x20]; 8037 8038 u8 pas[][0x40]; 8039 }; 8040 8041 struct mlx5_ifc_mad_ifc_out_bits { 8042 u8 status[0x8]; 8043 u8 reserved_at_8[0x18]; 8044 8045 u8 syndrome[0x20]; 8046 8047 u8 reserved_at_40[0x40]; 8048 8049 u8 response_mad_packet[256][0x8]; 8050 }; 8051 8052 struct mlx5_ifc_mad_ifc_in_bits { 8053 u8 opcode[0x10]; 8054 u8 reserved_at_10[0x10]; 8055 8056 u8 reserved_at_20[0x10]; 8057 u8 op_mod[0x10]; 8058 8059 u8 remote_lid[0x10]; 8060 u8 plane_index[0x8]; 8061 u8 port[0x8]; 8062 8063 u8 reserved_at_60[0x20]; 8064 8065 u8 mad[256][0x8]; 8066 }; 8067 8068 struct mlx5_ifc_init_hca_out_bits { 8069 u8 status[0x8]; 8070 u8 reserved_at_8[0x18]; 8071 8072 u8 syndrome[0x20]; 8073 8074 u8 reserved_at_40[0x40]; 8075 }; 8076 8077 struct mlx5_ifc_init_hca_in_bits { 8078 u8 opcode[0x10]; 8079 u8 reserved_at_10[0x10]; 8080 8081 u8 reserved_at_20[0x10]; 8082 u8 op_mod[0x10]; 8083 8084 u8 reserved_at_40[0x20]; 8085 8086 u8 reserved_at_60[0x2]; 8087 u8 sw_vhca_id[0xe]; 8088 u8 reserved_at_70[0x10]; 8089 8090 u8 sw_owner_id[4][0x20]; 8091 }; 8092 8093 struct mlx5_ifc_init2rtr_qp_out_bits { 8094 u8 status[0x8]; 8095 u8 reserved_at_8[0x18]; 8096 8097 u8 syndrome[0x20]; 8098 8099 u8 reserved_at_40[0x20]; 8100 u8 ece[0x20]; 8101 }; 8102 8103 struct mlx5_ifc_init2rtr_qp_in_bits { 8104 u8 opcode[0x10]; 8105 u8 uid[0x10]; 8106 8107 u8 reserved_at_20[0x10]; 8108 u8 op_mod[0x10]; 8109 8110 u8 reserved_at_40[0x8]; 8111 u8 qpn[0x18]; 8112 8113 u8 reserved_at_60[0x20]; 8114 8115 u8 opt_param_mask[0x20]; 8116 8117 u8 ece[0x20]; 8118 8119 struct mlx5_ifc_qpc_bits qpc; 8120 8121 u8 reserved_at_800[0x80]; 8122 }; 8123 8124 struct mlx5_ifc_init2init_qp_out_bits { 8125 u8 status[0x8]; 8126 u8 reserved_at_8[0x18]; 8127 8128 u8 syndrome[0x20]; 8129 8130 u8 reserved_at_40[0x20]; 8131 u8 ece[0x20]; 8132 }; 8133 8134 struct mlx5_ifc_init2init_qp_in_bits { 8135 u8 opcode[0x10]; 8136 u8 uid[0x10]; 8137 8138 u8 reserved_at_20[0x10]; 8139 u8 op_mod[0x10]; 8140 8141 u8 reserved_at_40[0x8]; 8142 u8 qpn[0x18]; 8143 8144 u8 reserved_at_60[0x20]; 8145 8146 u8 opt_param_mask[0x20]; 8147 8148 u8 ece[0x20]; 8149 8150 struct mlx5_ifc_qpc_bits qpc; 8151 8152 u8 reserved_at_800[0x80]; 8153 }; 8154 8155 struct mlx5_ifc_get_dropped_packet_log_out_bits { 8156 u8 status[0x8]; 8157 u8 reserved_at_8[0x18]; 8158 8159 u8 syndrome[0x20]; 8160 8161 u8 reserved_at_40[0x40]; 8162 8163 u8 packet_headers_log[128][0x8]; 8164 8165 u8 packet_syndrome[64][0x8]; 8166 }; 8167 8168 struct mlx5_ifc_get_dropped_packet_log_in_bits { 8169 u8 opcode[0x10]; 8170 u8 reserved_at_10[0x10]; 8171 8172 u8 reserved_at_20[0x10]; 8173 u8 op_mod[0x10]; 8174 8175 u8 reserved_at_40[0x40]; 8176 }; 8177 8178 struct mlx5_ifc_gen_eqe_in_bits { 8179 u8 opcode[0x10]; 8180 u8 reserved_at_10[0x10]; 8181 8182 u8 reserved_at_20[0x10]; 8183 u8 op_mod[0x10]; 8184 8185 u8 reserved_at_40[0x18]; 8186 u8 eq_number[0x8]; 8187 8188 u8 reserved_at_60[0x20]; 8189 8190 u8 eqe[64][0x8]; 8191 }; 8192 8193 struct mlx5_ifc_gen_eq_out_bits { 8194 u8 status[0x8]; 8195 u8 reserved_at_8[0x18]; 8196 8197 u8 syndrome[0x20]; 8198 8199 u8 reserved_at_40[0x40]; 8200 }; 8201 8202 struct mlx5_ifc_enable_hca_out_bits { 8203 u8 status[0x8]; 8204 u8 reserved_at_8[0x18]; 8205 8206 u8 syndrome[0x20]; 8207 8208 u8 reserved_at_40[0x20]; 8209 }; 8210 8211 struct mlx5_ifc_enable_hca_in_bits { 8212 u8 opcode[0x10]; 8213 u8 reserved_at_10[0x10]; 8214 8215 u8 reserved_at_20[0x10]; 8216 u8 op_mod[0x10]; 8217 8218 u8 embedded_cpu_function[0x1]; 8219 u8 reserved_at_41[0xf]; 8220 u8 function_id[0x10]; 8221 8222 u8 reserved_at_60[0x20]; 8223 }; 8224 8225 struct mlx5_ifc_drain_dct_out_bits { 8226 u8 status[0x8]; 8227 u8 reserved_at_8[0x18]; 8228 8229 u8 syndrome[0x20]; 8230 8231 u8 reserved_at_40[0x40]; 8232 }; 8233 8234 struct mlx5_ifc_drain_dct_in_bits { 8235 u8 opcode[0x10]; 8236 u8 uid[0x10]; 8237 8238 u8 reserved_at_20[0x10]; 8239 u8 op_mod[0x10]; 8240 8241 u8 reserved_at_40[0x8]; 8242 u8 dctn[0x18]; 8243 8244 u8 reserved_at_60[0x20]; 8245 }; 8246 8247 struct mlx5_ifc_disable_hca_out_bits { 8248 u8 status[0x8]; 8249 u8 reserved_at_8[0x18]; 8250 8251 u8 syndrome[0x20]; 8252 8253 u8 reserved_at_40[0x20]; 8254 }; 8255 8256 struct mlx5_ifc_disable_hca_in_bits { 8257 u8 opcode[0x10]; 8258 u8 reserved_at_10[0x10]; 8259 8260 u8 reserved_at_20[0x10]; 8261 u8 op_mod[0x10]; 8262 8263 u8 embedded_cpu_function[0x1]; 8264 u8 reserved_at_41[0xf]; 8265 u8 function_id[0x10]; 8266 8267 u8 reserved_at_60[0x20]; 8268 }; 8269 8270 struct mlx5_ifc_detach_from_mcg_out_bits { 8271 u8 status[0x8]; 8272 u8 reserved_at_8[0x18]; 8273 8274 u8 syndrome[0x20]; 8275 8276 u8 reserved_at_40[0x40]; 8277 }; 8278 8279 struct mlx5_ifc_detach_from_mcg_in_bits { 8280 u8 opcode[0x10]; 8281 u8 uid[0x10]; 8282 8283 u8 reserved_at_20[0x10]; 8284 u8 op_mod[0x10]; 8285 8286 u8 reserved_at_40[0x8]; 8287 u8 qpn[0x18]; 8288 8289 u8 reserved_at_60[0x20]; 8290 8291 u8 multicast_gid[16][0x8]; 8292 }; 8293 8294 struct mlx5_ifc_destroy_xrq_out_bits { 8295 u8 status[0x8]; 8296 u8 reserved_at_8[0x18]; 8297 8298 u8 syndrome[0x20]; 8299 8300 u8 reserved_at_40[0x40]; 8301 }; 8302 8303 struct mlx5_ifc_destroy_xrq_in_bits { 8304 u8 opcode[0x10]; 8305 u8 uid[0x10]; 8306 8307 u8 reserved_at_20[0x10]; 8308 u8 op_mod[0x10]; 8309 8310 u8 reserved_at_40[0x8]; 8311 u8 xrqn[0x18]; 8312 8313 u8 reserved_at_60[0x20]; 8314 }; 8315 8316 struct mlx5_ifc_destroy_xrc_srq_out_bits { 8317 u8 status[0x8]; 8318 u8 reserved_at_8[0x18]; 8319 8320 u8 syndrome[0x20]; 8321 8322 u8 reserved_at_40[0x40]; 8323 }; 8324 8325 struct mlx5_ifc_destroy_xrc_srq_in_bits { 8326 u8 opcode[0x10]; 8327 u8 uid[0x10]; 8328 8329 u8 reserved_at_20[0x10]; 8330 u8 op_mod[0x10]; 8331 8332 u8 reserved_at_40[0x8]; 8333 u8 xrc_srqn[0x18]; 8334 8335 u8 reserved_at_60[0x20]; 8336 }; 8337 8338 struct mlx5_ifc_destroy_tis_out_bits { 8339 u8 status[0x8]; 8340 u8 reserved_at_8[0x18]; 8341 8342 u8 syndrome[0x20]; 8343 8344 u8 reserved_at_40[0x40]; 8345 }; 8346 8347 struct mlx5_ifc_destroy_tis_in_bits { 8348 u8 opcode[0x10]; 8349 u8 uid[0x10]; 8350 8351 u8 reserved_at_20[0x10]; 8352 u8 op_mod[0x10]; 8353 8354 u8 reserved_at_40[0x8]; 8355 u8 tisn[0x18]; 8356 8357 u8 reserved_at_60[0x20]; 8358 }; 8359 8360 struct mlx5_ifc_destroy_tir_out_bits { 8361 u8 status[0x8]; 8362 u8 reserved_at_8[0x18]; 8363 8364 u8 syndrome[0x20]; 8365 8366 u8 reserved_at_40[0x40]; 8367 }; 8368 8369 struct mlx5_ifc_destroy_tir_in_bits { 8370 u8 opcode[0x10]; 8371 u8 uid[0x10]; 8372 8373 u8 reserved_at_20[0x10]; 8374 u8 op_mod[0x10]; 8375 8376 u8 reserved_at_40[0x8]; 8377 u8 tirn[0x18]; 8378 8379 u8 reserved_at_60[0x20]; 8380 }; 8381 8382 struct mlx5_ifc_destroy_srq_out_bits { 8383 u8 status[0x8]; 8384 u8 reserved_at_8[0x18]; 8385 8386 u8 syndrome[0x20]; 8387 8388 u8 reserved_at_40[0x40]; 8389 }; 8390 8391 struct mlx5_ifc_destroy_srq_in_bits { 8392 u8 opcode[0x10]; 8393 u8 uid[0x10]; 8394 8395 u8 reserved_at_20[0x10]; 8396 u8 op_mod[0x10]; 8397 8398 u8 reserved_at_40[0x8]; 8399 u8 srqn[0x18]; 8400 8401 u8 reserved_at_60[0x20]; 8402 }; 8403 8404 struct mlx5_ifc_destroy_sq_out_bits { 8405 u8 status[0x8]; 8406 u8 reserved_at_8[0x18]; 8407 8408 u8 syndrome[0x20]; 8409 8410 u8 reserved_at_40[0x40]; 8411 }; 8412 8413 struct mlx5_ifc_destroy_sq_in_bits { 8414 u8 opcode[0x10]; 8415 u8 uid[0x10]; 8416 8417 u8 reserved_at_20[0x10]; 8418 u8 op_mod[0x10]; 8419 8420 u8 reserved_at_40[0x8]; 8421 u8 sqn[0x18]; 8422 8423 u8 reserved_at_60[0x20]; 8424 }; 8425 8426 struct mlx5_ifc_destroy_scheduling_element_out_bits { 8427 u8 status[0x8]; 8428 u8 reserved_at_8[0x18]; 8429 8430 u8 syndrome[0x20]; 8431 8432 u8 reserved_at_40[0x1c0]; 8433 }; 8434 8435 struct mlx5_ifc_destroy_scheduling_element_in_bits { 8436 u8 opcode[0x10]; 8437 u8 reserved_at_10[0x10]; 8438 8439 u8 reserved_at_20[0x10]; 8440 u8 op_mod[0x10]; 8441 8442 u8 scheduling_hierarchy[0x8]; 8443 u8 reserved_at_48[0x18]; 8444 8445 u8 scheduling_element_id[0x20]; 8446 8447 u8 reserved_at_80[0x180]; 8448 }; 8449 8450 struct mlx5_ifc_destroy_rqt_out_bits { 8451 u8 status[0x8]; 8452 u8 reserved_at_8[0x18]; 8453 8454 u8 syndrome[0x20]; 8455 8456 u8 reserved_at_40[0x40]; 8457 }; 8458 8459 struct mlx5_ifc_destroy_rqt_in_bits { 8460 u8 opcode[0x10]; 8461 u8 uid[0x10]; 8462 8463 u8 reserved_at_20[0x10]; 8464 u8 op_mod[0x10]; 8465 8466 u8 reserved_at_40[0x8]; 8467 u8 rqtn[0x18]; 8468 8469 u8 reserved_at_60[0x20]; 8470 }; 8471 8472 struct mlx5_ifc_destroy_rq_out_bits { 8473 u8 status[0x8]; 8474 u8 reserved_at_8[0x18]; 8475 8476 u8 syndrome[0x20]; 8477 8478 u8 reserved_at_40[0x40]; 8479 }; 8480 8481 struct mlx5_ifc_destroy_rq_in_bits { 8482 u8 opcode[0x10]; 8483 u8 uid[0x10]; 8484 8485 u8 reserved_at_20[0x10]; 8486 u8 op_mod[0x10]; 8487 8488 u8 reserved_at_40[0x8]; 8489 u8 rqn[0x18]; 8490 8491 u8 reserved_at_60[0x20]; 8492 }; 8493 8494 struct mlx5_ifc_set_delay_drop_params_in_bits { 8495 u8 opcode[0x10]; 8496 u8 reserved_at_10[0x10]; 8497 8498 u8 reserved_at_20[0x10]; 8499 u8 op_mod[0x10]; 8500 8501 u8 reserved_at_40[0x20]; 8502 8503 u8 reserved_at_60[0x10]; 8504 u8 delay_drop_timeout[0x10]; 8505 }; 8506 8507 struct mlx5_ifc_set_delay_drop_params_out_bits { 8508 u8 status[0x8]; 8509 u8 reserved_at_8[0x18]; 8510 8511 u8 syndrome[0x20]; 8512 8513 u8 reserved_at_40[0x40]; 8514 }; 8515 8516 struct mlx5_ifc_destroy_rmp_out_bits { 8517 u8 status[0x8]; 8518 u8 reserved_at_8[0x18]; 8519 8520 u8 syndrome[0x20]; 8521 8522 u8 reserved_at_40[0x40]; 8523 }; 8524 8525 struct mlx5_ifc_destroy_rmp_in_bits { 8526 u8 opcode[0x10]; 8527 u8 uid[0x10]; 8528 8529 u8 reserved_at_20[0x10]; 8530 u8 op_mod[0x10]; 8531 8532 u8 reserved_at_40[0x8]; 8533 u8 rmpn[0x18]; 8534 8535 u8 reserved_at_60[0x20]; 8536 }; 8537 8538 struct mlx5_ifc_destroy_qp_out_bits { 8539 u8 status[0x8]; 8540 u8 reserved_at_8[0x18]; 8541 8542 u8 syndrome[0x20]; 8543 8544 u8 reserved_at_40[0x40]; 8545 }; 8546 8547 struct mlx5_ifc_destroy_qp_in_bits { 8548 u8 opcode[0x10]; 8549 u8 uid[0x10]; 8550 8551 u8 reserved_at_20[0x10]; 8552 u8 op_mod[0x10]; 8553 8554 u8 reserved_at_40[0x8]; 8555 u8 qpn[0x18]; 8556 8557 u8 reserved_at_60[0x20]; 8558 }; 8559 8560 struct mlx5_ifc_destroy_psv_out_bits { 8561 u8 status[0x8]; 8562 u8 reserved_at_8[0x18]; 8563 8564 u8 syndrome[0x20]; 8565 8566 u8 reserved_at_40[0x40]; 8567 }; 8568 8569 struct mlx5_ifc_destroy_psv_in_bits { 8570 u8 opcode[0x10]; 8571 u8 reserved_at_10[0x10]; 8572 8573 u8 reserved_at_20[0x10]; 8574 u8 op_mod[0x10]; 8575 8576 u8 reserved_at_40[0x8]; 8577 u8 psvn[0x18]; 8578 8579 u8 reserved_at_60[0x20]; 8580 }; 8581 8582 struct mlx5_ifc_destroy_mkey_out_bits { 8583 u8 status[0x8]; 8584 u8 reserved_at_8[0x18]; 8585 8586 u8 syndrome[0x20]; 8587 8588 u8 reserved_at_40[0x40]; 8589 }; 8590 8591 struct mlx5_ifc_destroy_mkey_in_bits { 8592 u8 opcode[0x10]; 8593 u8 uid[0x10]; 8594 8595 u8 reserved_at_20[0x10]; 8596 u8 op_mod[0x10]; 8597 8598 u8 reserved_at_40[0x8]; 8599 u8 mkey_index[0x18]; 8600 8601 u8 reserved_at_60[0x20]; 8602 }; 8603 8604 struct mlx5_ifc_destroy_flow_table_out_bits { 8605 u8 status[0x8]; 8606 u8 reserved_at_8[0x18]; 8607 8608 u8 syndrome[0x20]; 8609 8610 u8 reserved_at_40[0x40]; 8611 }; 8612 8613 struct mlx5_ifc_destroy_flow_table_in_bits { 8614 u8 opcode[0x10]; 8615 u8 reserved_at_10[0x10]; 8616 8617 u8 reserved_at_20[0x10]; 8618 u8 op_mod[0x10]; 8619 8620 u8 other_vport[0x1]; 8621 u8 reserved_at_41[0xf]; 8622 u8 vport_number[0x10]; 8623 8624 u8 reserved_at_60[0x20]; 8625 8626 u8 table_type[0x8]; 8627 u8 reserved_at_88[0x18]; 8628 8629 u8 reserved_at_a0[0x8]; 8630 u8 table_id[0x18]; 8631 8632 u8 reserved_at_c0[0x140]; 8633 }; 8634 8635 struct mlx5_ifc_destroy_flow_group_out_bits { 8636 u8 status[0x8]; 8637 u8 reserved_at_8[0x18]; 8638 8639 u8 syndrome[0x20]; 8640 8641 u8 reserved_at_40[0x40]; 8642 }; 8643 8644 struct mlx5_ifc_destroy_flow_group_in_bits { 8645 u8 opcode[0x10]; 8646 u8 reserved_at_10[0x10]; 8647 8648 u8 reserved_at_20[0x10]; 8649 u8 op_mod[0x10]; 8650 8651 u8 other_vport[0x1]; 8652 u8 reserved_at_41[0xf]; 8653 u8 vport_number[0x10]; 8654 8655 u8 reserved_at_60[0x20]; 8656 8657 u8 table_type[0x8]; 8658 u8 reserved_at_88[0x18]; 8659 8660 u8 reserved_at_a0[0x8]; 8661 u8 table_id[0x18]; 8662 8663 u8 group_id[0x20]; 8664 8665 u8 reserved_at_e0[0x120]; 8666 }; 8667 8668 struct mlx5_ifc_destroy_eq_out_bits { 8669 u8 status[0x8]; 8670 u8 reserved_at_8[0x18]; 8671 8672 u8 syndrome[0x20]; 8673 8674 u8 reserved_at_40[0x40]; 8675 }; 8676 8677 struct mlx5_ifc_destroy_eq_in_bits { 8678 u8 opcode[0x10]; 8679 u8 reserved_at_10[0x10]; 8680 8681 u8 reserved_at_20[0x10]; 8682 u8 op_mod[0x10]; 8683 8684 u8 reserved_at_40[0x18]; 8685 u8 eq_number[0x8]; 8686 8687 u8 reserved_at_60[0x20]; 8688 }; 8689 8690 struct mlx5_ifc_destroy_dct_out_bits { 8691 u8 status[0x8]; 8692 u8 reserved_at_8[0x18]; 8693 8694 u8 syndrome[0x20]; 8695 8696 u8 reserved_at_40[0x40]; 8697 }; 8698 8699 struct mlx5_ifc_destroy_dct_in_bits { 8700 u8 opcode[0x10]; 8701 u8 uid[0x10]; 8702 8703 u8 reserved_at_20[0x10]; 8704 u8 op_mod[0x10]; 8705 8706 u8 reserved_at_40[0x8]; 8707 u8 dctn[0x18]; 8708 8709 u8 reserved_at_60[0x20]; 8710 }; 8711 8712 struct mlx5_ifc_destroy_cq_out_bits { 8713 u8 status[0x8]; 8714 u8 reserved_at_8[0x18]; 8715 8716 u8 syndrome[0x20]; 8717 8718 u8 reserved_at_40[0x40]; 8719 }; 8720 8721 struct mlx5_ifc_destroy_cq_in_bits { 8722 u8 opcode[0x10]; 8723 u8 uid[0x10]; 8724 8725 u8 reserved_at_20[0x10]; 8726 u8 op_mod[0x10]; 8727 8728 u8 reserved_at_40[0x8]; 8729 u8 cqn[0x18]; 8730 8731 u8 reserved_at_60[0x20]; 8732 }; 8733 8734 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits { 8735 u8 status[0x8]; 8736 u8 reserved_at_8[0x18]; 8737 8738 u8 syndrome[0x20]; 8739 8740 u8 reserved_at_40[0x40]; 8741 }; 8742 8743 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits { 8744 u8 opcode[0x10]; 8745 u8 reserved_at_10[0x10]; 8746 8747 u8 reserved_at_20[0x10]; 8748 u8 op_mod[0x10]; 8749 8750 u8 reserved_at_40[0x20]; 8751 8752 u8 reserved_at_60[0x10]; 8753 u8 vxlan_udp_port[0x10]; 8754 }; 8755 8756 struct mlx5_ifc_delete_l2_table_entry_out_bits { 8757 u8 status[0x8]; 8758 u8 reserved_at_8[0x18]; 8759 8760 u8 syndrome[0x20]; 8761 8762 u8 reserved_at_40[0x40]; 8763 }; 8764 8765 struct mlx5_ifc_delete_l2_table_entry_in_bits { 8766 u8 opcode[0x10]; 8767 u8 reserved_at_10[0x10]; 8768 8769 u8 reserved_at_20[0x10]; 8770 u8 op_mod[0x10]; 8771 8772 u8 reserved_at_40[0x60]; 8773 8774 u8 reserved_at_a0[0x8]; 8775 u8 table_index[0x18]; 8776 8777 u8 reserved_at_c0[0x140]; 8778 }; 8779 8780 struct mlx5_ifc_delete_fte_out_bits { 8781 u8 status[0x8]; 8782 u8 reserved_at_8[0x18]; 8783 8784 u8 syndrome[0x20]; 8785 8786 u8 reserved_at_40[0x40]; 8787 }; 8788 8789 struct mlx5_ifc_delete_fte_in_bits { 8790 u8 opcode[0x10]; 8791 u8 reserved_at_10[0x10]; 8792 8793 u8 reserved_at_20[0x10]; 8794 u8 op_mod[0x10]; 8795 8796 u8 other_vport[0x1]; 8797 u8 reserved_at_41[0xf]; 8798 u8 vport_number[0x10]; 8799 8800 u8 reserved_at_60[0x20]; 8801 8802 u8 table_type[0x8]; 8803 u8 reserved_at_88[0x18]; 8804 8805 u8 reserved_at_a0[0x8]; 8806 u8 table_id[0x18]; 8807 8808 u8 reserved_at_c0[0x40]; 8809 8810 u8 flow_index[0x20]; 8811 8812 u8 reserved_at_120[0xe0]; 8813 }; 8814 8815 struct mlx5_ifc_dealloc_xrcd_out_bits { 8816 u8 status[0x8]; 8817 u8 reserved_at_8[0x18]; 8818 8819 u8 syndrome[0x20]; 8820 8821 u8 reserved_at_40[0x40]; 8822 }; 8823 8824 struct mlx5_ifc_dealloc_xrcd_in_bits { 8825 u8 opcode[0x10]; 8826 u8 uid[0x10]; 8827 8828 u8 reserved_at_20[0x10]; 8829 u8 op_mod[0x10]; 8830 8831 u8 reserved_at_40[0x8]; 8832 u8 xrcd[0x18]; 8833 8834 u8 reserved_at_60[0x20]; 8835 }; 8836 8837 struct mlx5_ifc_dealloc_uar_out_bits { 8838 u8 status[0x8]; 8839 u8 reserved_at_8[0x18]; 8840 8841 u8 syndrome[0x20]; 8842 8843 u8 reserved_at_40[0x40]; 8844 }; 8845 8846 struct mlx5_ifc_dealloc_uar_in_bits { 8847 u8 opcode[0x10]; 8848 u8 uid[0x10]; 8849 8850 u8 reserved_at_20[0x10]; 8851 u8 op_mod[0x10]; 8852 8853 u8 reserved_at_40[0x8]; 8854 u8 uar[0x18]; 8855 8856 u8 reserved_at_60[0x20]; 8857 }; 8858 8859 struct mlx5_ifc_dealloc_transport_domain_out_bits { 8860 u8 status[0x8]; 8861 u8 reserved_at_8[0x18]; 8862 8863 u8 syndrome[0x20]; 8864 8865 u8 reserved_at_40[0x40]; 8866 }; 8867 8868 struct mlx5_ifc_dealloc_transport_domain_in_bits { 8869 u8 opcode[0x10]; 8870 u8 uid[0x10]; 8871 8872 u8 reserved_at_20[0x10]; 8873 u8 op_mod[0x10]; 8874 8875 u8 reserved_at_40[0x8]; 8876 u8 transport_domain[0x18]; 8877 8878 u8 reserved_at_60[0x20]; 8879 }; 8880 8881 struct mlx5_ifc_dealloc_q_counter_out_bits { 8882 u8 status[0x8]; 8883 u8 reserved_at_8[0x18]; 8884 8885 u8 syndrome[0x20]; 8886 8887 u8 reserved_at_40[0x40]; 8888 }; 8889 8890 struct mlx5_ifc_dealloc_q_counter_in_bits { 8891 u8 opcode[0x10]; 8892 u8 reserved_at_10[0x10]; 8893 8894 u8 reserved_at_20[0x10]; 8895 u8 op_mod[0x10]; 8896 8897 u8 reserved_at_40[0x18]; 8898 u8 counter_set_id[0x8]; 8899 8900 u8 reserved_at_60[0x20]; 8901 }; 8902 8903 struct mlx5_ifc_dealloc_pd_out_bits { 8904 u8 status[0x8]; 8905 u8 reserved_at_8[0x18]; 8906 8907 u8 syndrome[0x20]; 8908 8909 u8 reserved_at_40[0x40]; 8910 }; 8911 8912 struct mlx5_ifc_dealloc_pd_in_bits { 8913 u8 opcode[0x10]; 8914 u8 uid[0x10]; 8915 8916 u8 reserved_at_20[0x10]; 8917 u8 op_mod[0x10]; 8918 8919 u8 reserved_at_40[0x8]; 8920 u8 pd[0x18]; 8921 8922 u8 reserved_at_60[0x20]; 8923 }; 8924 8925 struct mlx5_ifc_dealloc_flow_counter_out_bits { 8926 u8 status[0x8]; 8927 u8 reserved_at_8[0x18]; 8928 8929 u8 syndrome[0x20]; 8930 8931 u8 reserved_at_40[0x40]; 8932 }; 8933 8934 struct mlx5_ifc_dealloc_flow_counter_in_bits { 8935 u8 opcode[0x10]; 8936 u8 reserved_at_10[0x10]; 8937 8938 u8 reserved_at_20[0x10]; 8939 u8 op_mod[0x10]; 8940 8941 u8 flow_counter_id[0x20]; 8942 8943 u8 reserved_at_60[0x20]; 8944 }; 8945 8946 struct mlx5_ifc_create_xrq_out_bits { 8947 u8 status[0x8]; 8948 u8 reserved_at_8[0x18]; 8949 8950 u8 syndrome[0x20]; 8951 8952 u8 reserved_at_40[0x8]; 8953 u8 xrqn[0x18]; 8954 8955 u8 reserved_at_60[0x20]; 8956 }; 8957 8958 struct mlx5_ifc_create_xrq_in_bits { 8959 u8 opcode[0x10]; 8960 u8 uid[0x10]; 8961 8962 u8 reserved_at_20[0x10]; 8963 u8 op_mod[0x10]; 8964 8965 u8 reserved_at_40[0x40]; 8966 8967 struct mlx5_ifc_xrqc_bits xrq_context; 8968 }; 8969 8970 struct mlx5_ifc_create_xrc_srq_out_bits { 8971 u8 status[0x8]; 8972 u8 reserved_at_8[0x18]; 8973 8974 u8 syndrome[0x20]; 8975 8976 u8 reserved_at_40[0x8]; 8977 u8 xrc_srqn[0x18]; 8978 8979 u8 reserved_at_60[0x20]; 8980 }; 8981 8982 struct mlx5_ifc_create_xrc_srq_in_bits { 8983 u8 opcode[0x10]; 8984 u8 uid[0x10]; 8985 8986 u8 reserved_at_20[0x10]; 8987 u8 op_mod[0x10]; 8988 8989 u8 reserved_at_40[0x40]; 8990 8991 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 8992 8993 u8 reserved_at_280[0x60]; 8994 8995 u8 xrc_srq_umem_valid[0x1]; 8996 u8 reserved_at_2e1[0x1f]; 8997 8998 u8 reserved_at_300[0x580]; 8999 9000 u8 pas[][0x40]; 9001 }; 9002 9003 struct mlx5_ifc_create_tis_out_bits { 9004 u8 status[0x8]; 9005 u8 reserved_at_8[0x18]; 9006 9007 u8 syndrome[0x20]; 9008 9009 u8 reserved_at_40[0x8]; 9010 u8 tisn[0x18]; 9011 9012 u8 reserved_at_60[0x20]; 9013 }; 9014 9015 struct mlx5_ifc_create_tis_in_bits { 9016 u8 opcode[0x10]; 9017 u8 uid[0x10]; 9018 9019 u8 reserved_at_20[0x10]; 9020 u8 op_mod[0x10]; 9021 9022 u8 reserved_at_40[0xc0]; 9023 9024 struct mlx5_ifc_tisc_bits ctx; 9025 }; 9026 9027 struct mlx5_ifc_create_tir_out_bits { 9028 u8 status[0x8]; 9029 u8 icm_address_63_40[0x18]; 9030 9031 u8 syndrome[0x20]; 9032 9033 u8 icm_address_39_32[0x8]; 9034 u8 tirn[0x18]; 9035 9036 u8 icm_address_31_0[0x20]; 9037 }; 9038 9039 struct mlx5_ifc_create_tir_in_bits { 9040 u8 opcode[0x10]; 9041 u8 uid[0x10]; 9042 9043 u8 reserved_at_20[0x10]; 9044 u8 op_mod[0x10]; 9045 9046 u8 reserved_at_40[0xc0]; 9047 9048 struct mlx5_ifc_tirc_bits ctx; 9049 }; 9050 9051 struct mlx5_ifc_create_srq_out_bits { 9052 u8 status[0x8]; 9053 u8 reserved_at_8[0x18]; 9054 9055 u8 syndrome[0x20]; 9056 9057 u8 reserved_at_40[0x8]; 9058 u8 srqn[0x18]; 9059 9060 u8 reserved_at_60[0x20]; 9061 }; 9062 9063 struct mlx5_ifc_create_srq_in_bits { 9064 u8 opcode[0x10]; 9065 u8 uid[0x10]; 9066 9067 u8 reserved_at_20[0x10]; 9068 u8 op_mod[0x10]; 9069 9070 u8 reserved_at_40[0x40]; 9071 9072 struct mlx5_ifc_srqc_bits srq_context_entry; 9073 9074 u8 reserved_at_280[0x600]; 9075 9076 u8 pas[][0x40]; 9077 }; 9078 9079 struct mlx5_ifc_create_sq_out_bits { 9080 u8 status[0x8]; 9081 u8 reserved_at_8[0x18]; 9082 9083 u8 syndrome[0x20]; 9084 9085 u8 reserved_at_40[0x8]; 9086 u8 sqn[0x18]; 9087 9088 u8 reserved_at_60[0x20]; 9089 }; 9090 9091 struct mlx5_ifc_create_sq_in_bits { 9092 u8 opcode[0x10]; 9093 u8 uid[0x10]; 9094 9095 u8 reserved_at_20[0x10]; 9096 u8 op_mod[0x10]; 9097 9098 u8 reserved_at_40[0xc0]; 9099 9100 struct mlx5_ifc_sqc_bits ctx; 9101 }; 9102 9103 struct mlx5_ifc_create_scheduling_element_out_bits { 9104 u8 status[0x8]; 9105 u8 reserved_at_8[0x18]; 9106 9107 u8 syndrome[0x20]; 9108 9109 u8 reserved_at_40[0x40]; 9110 9111 u8 scheduling_element_id[0x20]; 9112 9113 u8 reserved_at_a0[0x160]; 9114 }; 9115 9116 struct mlx5_ifc_create_scheduling_element_in_bits { 9117 u8 opcode[0x10]; 9118 u8 reserved_at_10[0x10]; 9119 9120 u8 reserved_at_20[0x10]; 9121 u8 op_mod[0x10]; 9122 9123 u8 scheduling_hierarchy[0x8]; 9124 u8 reserved_at_48[0x18]; 9125 9126 u8 reserved_at_60[0xa0]; 9127 9128 struct mlx5_ifc_scheduling_context_bits scheduling_context; 9129 9130 u8 reserved_at_300[0x100]; 9131 }; 9132 9133 struct mlx5_ifc_create_rqt_out_bits { 9134 u8 status[0x8]; 9135 u8 reserved_at_8[0x18]; 9136 9137 u8 syndrome[0x20]; 9138 9139 u8 reserved_at_40[0x8]; 9140 u8 rqtn[0x18]; 9141 9142 u8 reserved_at_60[0x20]; 9143 }; 9144 9145 struct mlx5_ifc_create_rqt_in_bits { 9146 u8 opcode[0x10]; 9147 u8 uid[0x10]; 9148 9149 u8 reserved_at_20[0x10]; 9150 u8 op_mod[0x10]; 9151 9152 u8 reserved_at_40[0xc0]; 9153 9154 struct mlx5_ifc_rqtc_bits rqt_context; 9155 }; 9156 9157 struct mlx5_ifc_create_rq_out_bits { 9158 u8 status[0x8]; 9159 u8 reserved_at_8[0x18]; 9160 9161 u8 syndrome[0x20]; 9162 9163 u8 reserved_at_40[0x8]; 9164 u8 rqn[0x18]; 9165 9166 u8 reserved_at_60[0x20]; 9167 }; 9168 9169 struct mlx5_ifc_create_rq_in_bits { 9170 u8 opcode[0x10]; 9171 u8 uid[0x10]; 9172 9173 u8 reserved_at_20[0x10]; 9174 u8 op_mod[0x10]; 9175 9176 u8 reserved_at_40[0xc0]; 9177 9178 struct mlx5_ifc_rqc_bits ctx; 9179 }; 9180 9181 struct mlx5_ifc_create_rmp_out_bits { 9182 u8 status[0x8]; 9183 u8 reserved_at_8[0x18]; 9184 9185 u8 syndrome[0x20]; 9186 9187 u8 reserved_at_40[0x8]; 9188 u8 rmpn[0x18]; 9189 9190 u8 reserved_at_60[0x20]; 9191 }; 9192 9193 struct mlx5_ifc_create_rmp_in_bits { 9194 u8 opcode[0x10]; 9195 u8 uid[0x10]; 9196 9197 u8 reserved_at_20[0x10]; 9198 u8 op_mod[0x10]; 9199 9200 u8 reserved_at_40[0xc0]; 9201 9202 struct mlx5_ifc_rmpc_bits ctx; 9203 }; 9204 9205 struct mlx5_ifc_create_qp_out_bits { 9206 u8 status[0x8]; 9207 u8 reserved_at_8[0x18]; 9208 9209 u8 syndrome[0x20]; 9210 9211 u8 reserved_at_40[0x8]; 9212 u8 qpn[0x18]; 9213 9214 u8 ece[0x20]; 9215 }; 9216 9217 struct mlx5_ifc_create_qp_in_bits { 9218 u8 opcode[0x10]; 9219 u8 uid[0x10]; 9220 9221 u8 reserved_at_20[0x10]; 9222 u8 op_mod[0x10]; 9223 9224 u8 qpc_ext[0x1]; 9225 u8 reserved_at_41[0x7]; 9226 u8 input_qpn[0x18]; 9227 9228 u8 reserved_at_60[0x20]; 9229 u8 opt_param_mask[0x20]; 9230 9231 u8 ece[0x20]; 9232 9233 struct mlx5_ifc_qpc_bits qpc; 9234 9235 u8 wq_umem_offset[0x40]; 9236 9237 u8 wq_umem_id[0x20]; 9238 9239 u8 wq_umem_valid[0x1]; 9240 u8 reserved_at_861[0x1f]; 9241 9242 u8 pas[][0x40]; 9243 }; 9244 9245 struct mlx5_ifc_create_psv_out_bits { 9246 u8 status[0x8]; 9247 u8 reserved_at_8[0x18]; 9248 9249 u8 syndrome[0x20]; 9250 9251 u8 reserved_at_40[0x40]; 9252 9253 u8 reserved_at_80[0x8]; 9254 u8 psv0_index[0x18]; 9255 9256 u8 reserved_at_a0[0x8]; 9257 u8 psv1_index[0x18]; 9258 9259 u8 reserved_at_c0[0x8]; 9260 u8 psv2_index[0x18]; 9261 9262 u8 reserved_at_e0[0x8]; 9263 u8 psv3_index[0x18]; 9264 }; 9265 9266 struct mlx5_ifc_create_psv_in_bits { 9267 u8 opcode[0x10]; 9268 u8 reserved_at_10[0x10]; 9269 9270 u8 reserved_at_20[0x10]; 9271 u8 op_mod[0x10]; 9272 9273 u8 num_psv[0x4]; 9274 u8 reserved_at_44[0x4]; 9275 u8 pd[0x18]; 9276 9277 u8 reserved_at_60[0x20]; 9278 }; 9279 9280 struct mlx5_ifc_create_mkey_out_bits { 9281 u8 status[0x8]; 9282 u8 reserved_at_8[0x18]; 9283 9284 u8 syndrome[0x20]; 9285 9286 u8 reserved_at_40[0x8]; 9287 u8 mkey_index[0x18]; 9288 9289 u8 reserved_at_60[0x20]; 9290 }; 9291 9292 struct mlx5_ifc_create_mkey_in_bits { 9293 u8 opcode[0x10]; 9294 u8 uid[0x10]; 9295 9296 u8 reserved_at_20[0x10]; 9297 u8 op_mod[0x10]; 9298 9299 u8 reserved_at_40[0x20]; 9300 9301 u8 pg_access[0x1]; 9302 u8 mkey_umem_valid[0x1]; 9303 u8 data_direct[0x1]; 9304 u8 reserved_at_63[0x1d]; 9305 9306 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 9307 9308 u8 reserved_at_280[0x80]; 9309 9310 u8 translations_octword_actual_size[0x20]; 9311 9312 u8 reserved_at_320[0x560]; 9313 9314 u8 klm_pas_mtt[][0x20]; 9315 }; 9316 9317 enum { 9318 MLX5_FLOW_TABLE_TYPE_NIC_RX = 0x0, 9319 MLX5_FLOW_TABLE_TYPE_NIC_TX = 0x1, 9320 MLX5_FLOW_TABLE_TYPE_ESW_EGRESS_ACL = 0x2, 9321 MLX5_FLOW_TABLE_TYPE_ESW_INGRESS_ACL = 0x3, 9322 MLX5_FLOW_TABLE_TYPE_FDB = 0X4, 9323 MLX5_FLOW_TABLE_TYPE_SNIFFER_RX = 0X5, 9324 MLX5_FLOW_TABLE_TYPE_SNIFFER_TX = 0X6, 9325 }; 9326 9327 struct mlx5_ifc_create_flow_table_out_bits { 9328 u8 status[0x8]; 9329 u8 icm_address_63_40[0x18]; 9330 9331 u8 syndrome[0x20]; 9332 9333 u8 icm_address_39_32[0x8]; 9334 u8 table_id[0x18]; 9335 9336 u8 icm_address_31_0[0x20]; 9337 }; 9338 9339 struct mlx5_ifc_create_flow_table_in_bits { 9340 u8 opcode[0x10]; 9341 u8 uid[0x10]; 9342 9343 u8 reserved_at_20[0x10]; 9344 u8 op_mod[0x10]; 9345 9346 u8 other_vport[0x1]; 9347 u8 reserved_at_41[0xf]; 9348 u8 vport_number[0x10]; 9349 9350 u8 reserved_at_60[0x20]; 9351 9352 u8 table_type[0x8]; 9353 u8 reserved_at_88[0x18]; 9354 9355 u8 reserved_at_a0[0x20]; 9356 9357 struct mlx5_ifc_flow_table_context_bits flow_table_context; 9358 }; 9359 9360 struct mlx5_ifc_create_flow_group_out_bits { 9361 u8 status[0x8]; 9362 u8 reserved_at_8[0x18]; 9363 9364 u8 syndrome[0x20]; 9365 9366 u8 reserved_at_40[0x8]; 9367 u8 group_id[0x18]; 9368 9369 u8 reserved_at_60[0x20]; 9370 }; 9371 9372 enum { 9373 MLX5_CREATE_FLOW_GROUP_IN_GROUP_TYPE_TCAM_SUBTABLE = 0x0, 9374 MLX5_CREATE_FLOW_GROUP_IN_GROUP_TYPE_HASH_SPLIT = 0x1, 9375 }; 9376 9377 enum { 9378 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 9379 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 9380 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 9381 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3, 9382 }; 9383 9384 struct mlx5_ifc_create_flow_group_in_bits { 9385 u8 opcode[0x10]; 9386 u8 reserved_at_10[0x10]; 9387 9388 u8 reserved_at_20[0x10]; 9389 u8 op_mod[0x10]; 9390 9391 u8 other_vport[0x1]; 9392 u8 reserved_at_41[0xf]; 9393 u8 vport_number[0x10]; 9394 9395 u8 reserved_at_60[0x20]; 9396 9397 u8 table_type[0x8]; 9398 u8 reserved_at_88[0x4]; 9399 u8 group_type[0x4]; 9400 u8 reserved_at_90[0x10]; 9401 9402 u8 reserved_at_a0[0x8]; 9403 u8 table_id[0x18]; 9404 9405 u8 source_eswitch_owner_vhca_id_valid[0x1]; 9406 9407 u8 reserved_at_c1[0x1f]; 9408 9409 u8 start_flow_index[0x20]; 9410 9411 u8 reserved_at_100[0x20]; 9412 9413 u8 end_flow_index[0x20]; 9414 9415 u8 reserved_at_140[0x10]; 9416 u8 match_definer_id[0x10]; 9417 9418 u8 reserved_at_160[0x80]; 9419 9420 u8 reserved_at_1e0[0x18]; 9421 u8 match_criteria_enable[0x8]; 9422 9423 struct mlx5_ifc_fte_match_param_bits match_criteria; 9424 9425 u8 reserved_at_1200[0xe00]; 9426 }; 9427 9428 struct mlx5_ifc_create_eq_out_bits { 9429 u8 status[0x8]; 9430 u8 reserved_at_8[0x18]; 9431 9432 u8 syndrome[0x20]; 9433 9434 u8 reserved_at_40[0x18]; 9435 u8 eq_number[0x8]; 9436 9437 u8 reserved_at_60[0x20]; 9438 }; 9439 9440 struct mlx5_ifc_create_eq_in_bits { 9441 u8 opcode[0x10]; 9442 u8 uid[0x10]; 9443 9444 u8 reserved_at_20[0x10]; 9445 u8 op_mod[0x10]; 9446 9447 u8 reserved_at_40[0x40]; 9448 9449 struct mlx5_ifc_eqc_bits eq_context_entry; 9450 9451 u8 reserved_at_280[0x40]; 9452 9453 u8 event_bitmask[4][0x40]; 9454 9455 u8 reserved_at_3c0[0x4c0]; 9456 9457 u8 pas[][0x40]; 9458 }; 9459 9460 struct mlx5_ifc_create_dct_out_bits { 9461 u8 status[0x8]; 9462 u8 reserved_at_8[0x18]; 9463 9464 u8 syndrome[0x20]; 9465 9466 u8 reserved_at_40[0x8]; 9467 u8 dctn[0x18]; 9468 9469 u8 ece[0x20]; 9470 }; 9471 9472 struct mlx5_ifc_create_dct_in_bits { 9473 u8 opcode[0x10]; 9474 u8 uid[0x10]; 9475 9476 u8 reserved_at_20[0x10]; 9477 u8 op_mod[0x10]; 9478 9479 u8 reserved_at_40[0x40]; 9480 9481 struct mlx5_ifc_dctc_bits dct_context_entry; 9482 9483 u8 reserved_at_280[0x180]; 9484 }; 9485 9486 struct mlx5_ifc_create_cq_out_bits { 9487 u8 status[0x8]; 9488 u8 reserved_at_8[0x18]; 9489 9490 u8 syndrome[0x20]; 9491 9492 u8 reserved_at_40[0x8]; 9493 u8 cqn[0x18]; 9494 9495 u8 reserved_at_60[0x20]; 9496 }; 9497 9498 struct mlx5_ifc_create_cq_in_bits { 9499 u8 opcode[0x10]; 9500 u8 uid[0x10]; 9501 9502 u8 reserved_at_20[0x10]; 9503 u8 op_mod[0x10]; 9504 9505 u8 reserved_at_40[0x40]; 9506 9507 struct mlx5_ifc_cqc_bits cq_context; 9508 9509 u8 reserved_at_280[0x60]; 9510 9511 u8 cq_umem_valid[0x1]; 9512 u8 reserved_at_2e1[0x59f]; 9513 9514 u8 pas[][0x40]; 9515 }; 9516 9517 struct mlx5_ifc_config_int_moderation_out_bits { 9518 u8 status[0x8]; 9519 u8 reserved_at_8[0x18]; 9520 9521 u8 syndrome[0x20]; 9522 9523 u8 reserved_at_40[0x4]; 9524 u8 min_delay[0xc]; 9525 u8 int_vector[0x10]; 9526 9527 u8 reserved_at_60[0x20]; 9528 }; 9529 9530 enum { 9531 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0, 9532 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1, 9533 }; 9534 9535 struct mlx5_ifc_config_int_moderation_in_bits { 9536 u8 opcode[0x10]; 9537 u8 reserved_at_10[0x10]; 9538 9539 u8 reserved_at_20[0x10]; 9540 u8 op_mod[0x10]; 9541 9542 u8 reserved_at_40[0x4]; 9543 u8 min_delay[0xc]; 9544 u8 int_vector[0x10]; 9545 9546 u8 reserved_at_60[0x20]; 9547 }; 9548 9549 struct mlx5_ifc_attach_to_mcg_out_bits { 9550 u8 status[0x8]; 9551 u8 reserved_at_8[0x18]; 9552 9553 u8 syndrome[0x20]; 9554 9555 u8 reserved_at_40[0x40]; 9556 }; 9557 9558 struct mlx5_ifc_attach_to_mcg_in_bits { 9559 u8 opcode[0x10]; 9560 u8 uid[0x10]; 9561 9562 u8 reserved_at_20[0x10]; 9563 u8 op_mod[0x10]; 9564 9565 u8 reserved_at_40[0x8]; 9566 u8 qpn[0x18]; 9567 9568 u8 reserved_at_60[0x20]; 9569 9570 u8 multicast_gid[16][0x8]; 9571 }; 9572 9573 struct mlx5_ifc_arm_xrq_out_bits { 9574 u8 status[0x8]; 9575 u8 reserved_at_8[0x18]; 9576 9577 u8 syndrome[0x20]; 9578 9579 u8 reserved_at_40[0x40]; 9580 }; 9581 9582 struct mlx5_ifc_arm_xrq_in_bits { 9583 u8 opcode[0x10]; 9584 u8 reserved_at_10[0x10]; 9585 9586 u8 reserved_at_20[0x10]; 9587 u8 op_mod[0x10]; 9588 9589 u8 reserved_at_40[0x8]; 9590 u8 xrqn[0x18]; 9591 9592 u8 reserved_at_60[0x10]; 9593 u8 lwm[0x10]; 9594 }; 9595 9596 struct mlx5_ifc_arm_xrc_srq_out_bits { 9597 u8 status[0x8]; 9598 u8 reserved_at_8[0x18]; 9599 9600 u8 syndrome[0x20]; 9601 9602 u8 reserved_at_40[0x40]; 9603 }; 9604 9605 enum { 9606 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1, 9607 }; 9608 9609 struct mlx5_ifc_arm_xrc_srq_in_bits { 9610 u8 opcode[0x10]; 9611 u8 uid[0x10]; 9612 9613 u8 reserved_at_20[0x10]; 9614 u8 op_mod[0x10]; 9615 9616 u8 reserved_at_40[0x8]; 9617 u8 xrc_srqn[0x18]; 9618 9619 u8 reserved_at_60[0x10]; 9620 u8 lwm[0x10]; 9621 }; 9622 9623 struct mlx5_ifc_arm_rq_out_bits { 9624 u8 status[0x8]; 9625 u8 reserved_at_8[0x18]; 9626 9627 u8 syndrome[0x20]; 9628 9629 u8 reserved_at_40[0x40]; 9630 }; 9631 9632 enum { 9633 MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1, 9634 MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2, 9635 }; 9636 9637 struct mlx5_ifc_arm_rq_in_bits { 9638 u8 opcode[0x10]; 9639 u8 uid[0x10]; 9640 9641 u8 reserved_at_20[0x10]; 9642 u8 op_mod[0x10]; 9643 9644 u8 reserved_at_40[0x8]; 9645 u8 srq_number[0x18]; 9646 9647 u8 reserved_at_60[0x10]; 9648 u8 lwm[0x10]; 9649 }; 9650 9651 struct mlx5_ifc_arm_dct_out_bits { 9652 u8 status[0x8]; 9653 u8 reserved_at_8[0x18]; 9654 9655 u8 syndrome[0x20]; 9656 9657 u8 reserved_at_40[0x40]; 9658 }; 9659 9660 struct mlx5_ifc_arm_dct_in_bits { 9661 u8 opcode[0x10]; 9662 u8 reserved_at_10[0x10]; 9663 9664 u8 reserved_at_20[0x10]; 9665 u8 op_mod[0x10]; 9666 9667 u8 reserved_at_40[0x8]; 9668 u8 dct_number[0x18]; 9669 9670 u8 reserved_at_60[0x20]; 9671 }; 9672 9673 struct mlx5_ifc_alloc_xrcd_out_bits { 9674 u8 status[0x8]; 9675 u8 reserved_at_8[0x18]; 9676 9677 u8 syndrome[0x20]; 9678 9679 u8 reserved_at_40[0x8]; 9680 u8 xrcd[0x18]; 9681 9682 u8 reserved_at_60[0x20]; 9683 }; 9684 9685 struct mlx5_ifc_alloc_xrcd_in_bits { 9686 u8 opcode[0x10]; 9687 u8 uid[0x10]; 9688 9689 u8 reserved_at_20[0x10]; 9690 u8 op_mod[0x10]; 9691 9692 u8 reserved_at_40[0x40]; 9693 }; 9694 9695 struct mlx5_ifc_alloc_uar_out_bits { 9696 u8 status[0x8]; 9697 u8 reserved_at_8[0x18]; 9698 9699 u8 syndrome[0x20]; 9700 9701 u8 reserved_at_40[0x8]; 9702 u8 uar[0x18]; 9703 9704 u8 reserved_at_60[0x20]; 9705 }; 9706 9707 struct mlx5_ifc_alloc_uar_in_bits { 9708 u8 opcode[0x10]; 9709 u8 uid[0x10]; 9710 9711 u8 reserved_at_20[0x10]; 9712 u8 op_mod[0x10]; 9713 9714 u8 reserved_at_40[0x40]; 9715 }; 9716 9717 struct mlx5_ifc_alloc_transport_domain_out_bits { 9718 u8 status[0x8]; 9719 u8 reserved_at_8[0x18]; 9720 9721 u8 syndrome[0x20]; 9722 9723 u8 reserved_at_40[0x8]; 9724 u8 transport_domain[0x18]; 9725 9726 u8 reserved_at_60[0x20]; 9727 }; 9728 9729 struct mlx5_ifc_alloc_transport_domain_in_bits { 9730 u8 opcode[0x10]; 9731 u8 uid[0x10]; 9732 9733 u8 reserved_at_20[0x10]; 9734 u8 op_mod[0x10]; 9735 9736 u8 reserved_at_40[0x40]; 9737 }; 9738 9739 struct mlx5_ifc_alloc_q_counter_out_bits { 9740 u8 status[0x8]; 9741 u8 reserved_at_8[0x18]; 9742 9743 u8 syndrome[0x20]; 9744 9745 u8 reserved_at_40[0x18]; 9746 u8 counter_set_id[0x8]; 9747 9748 u8 reserved_at_60[0x20]; 9749 }; 9750 9751 struct mlx5_ifc_alloc_q_counter_in_bits { 9752 u8 opcode[0x10]; 9753 u8 uid[0x10]; 9754 9755 u8 reserved_at_20[0x10]; 9756 u8 op_mod[0x10]; 9757 9758 u8 reserved_at_40[0x40]; 9759 }; 9760 9761 struct mlx5_ifc_alloc_pd_out_bits { 9762 u8 status[0x8]; 9763 u8 reserved_at_8[0x18]; 9764 9765 u8 syndrome[0x20]; 9766 9767 u8 reserved_at_40[0x8]; 9768 u8 pd[0x18]; 9769 9770 u8 reserved_at_60[0x20]; 9771 }; 9772 9773 struct mlx5_ifc_alloc_pd_in_bits { 9774 u8 opcode[0x10]; 9775 u8 uid[0x10]; 9776 9777 u8 reserved_at_20[0x10]; 9778 u8 op_mod[0x10]; 9779 9780 u8 reserved_at_40[0x40]; 9781 }; 9782 9783 struct mlx5_ifc_alloc_flow_counter_out_bits { 9784 u8 status[0x8]; 9785 u8 reserved_at_8[0x18]; 9786 9787 u8 syndrome[0x20]; 9788 9789 u8 flow_counter_id[0x20]; 9790 9791 u8 reserved_at_60[0x20]; 9792 }; 9793 9794 struct mlx5_ifc_alloc_flow_counter_in_bits { 9795 u8 opcode[0x10]; 9796 u8 reserved_at_10[0x10]; 9797 9798 u8 reserved_at_20[0x10]; 9799 u8 op_mod[0x10]; 9800 9801 u8 reserved_at_40[0x33]; 9802 u8 flow_counter_bulk_log_size[0x5]; 9803 u8 flow_counter_bulk[0x8]; 9804 }; 9805 9806 struct mlx5_ifc_add_vxlan_udp_dport_out_bits { 9807 u8 status[0x8]; 9808 u8 reserved_at_8[0x18]; 9809 9810 u8 syndrome[0x20]; 9811 9812 u8 reserved_at_40[0x40]; 9813 }; 9814 9815 struct mlx5_ifc_add_vxlan_udp_dport_in_bits { 9816 u8 opcode[0x10]; 9817 u8 reserved_at_10[0x10]; 9818 9819 u8 reserved_at_20[0x10]; 9820 u8 op_mod[0x10]; 9821 9822 u8 reserved_at_40[0x20]; 9823 9824 u8 reserved_at_60[0x10]; 9825 u8 vxlan_udp_port[0x10]; 9826 }; 9827 9828 struct mlx5_ifc_set_pp_rate_limit_out_bits { 9829 u8 status[0x8]; 9830 u8 reserved_at_8[0x18]; 9831 9832 u8 syndrome[0x20]; 9833 9834 u8 reserved_at_40[0x40]; 9835 }; 9836 9837 struct mlx5_ifc_set_pp_rate_limit_context_bits { 9838 u8 rate_limit[0x20]; 9839 9840 u8 burst_upper_bound[0x20]; 9841 9842 u8 reserved_at_40[0x10]; 9843 u8 typical_packet_size[0x10]; 9844 9845 u8 reserved_at_60[0x120]; 9846 }; 9847 9848 struct mlx5_ifc_set_pp_rate_limit_in_bits { 9849 u8 opcode[0x10]; 9850 u8 uid[0x10]; 9851 9852 u8 reserved_at_20[0x10]; 9853 u8 op_mod[0x10]; 9854 9855 u8 reserved_at_40[0x10]; 9856 u8 rate_limit_index[0x10]; 9857 9858 u8 reserved_at_60[0x20]; 9859 9860 struct mlx5_ifc_set_pp_rate_limit_context_bits ctx; 9861 }; 9862 9863 struct mlx5_ifc_access_register_out_bits { 9864 u8 status[0x8]; 9865 u8 reserved_at_8[0x18]; 9866 9867 u8 syndrome[0x20]; 9868 9869 u8 reserved_at_40[0x40]; 9870 9871 u8 register_data[][0x20]; 9872 }; 9873 9874 enum { 9875 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0, 9876 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1, 9877 }; 9878 9879 struct mlx5_ifc_access_register_in_bits { 9880 u8 opcode[0x10]; 9881 u8 reserved_at_10[0x10]; 9882 9883 u8 reserved_at_20[0x10]; 9884 u8 op_mod[0x10]; 9885 9886 u8 reserved_at_40[0x10]; 9887 u8 register_id[0x10]; 9888 9889 u8 argument[0x20]; 9890 9891 u8 register_data[][0x20]; 9892 }; 9893 9894 struct mlx5_ifc_sltp_reg_bits { 9895 u8 status[0x4]; 9896 u8 version[0x4]; 9897 u8 local_port[0x8]; 9898 u8 pnat[0x2]; 9899 u8 reserved_at_12[0x2]; 9900 u8 lane[0x4]; 9901 u8 reserved_at_18[0x8]; 9902 9903 u8 reserved_at_20[0x20]; 9904 9905 u8 reserved_at_40[0x7]; 9906 u8 polarity[0x1]; 9907 u8 ob_tap0[0x8]; 9908 u8 ob_tap1[0x8]; 9909 u8 ob_tap2[0x8]; 9910 9911 u8 reserved_at_60[0xc]; 9912 u8 ob_preemp_mode[0x4]; 9913 u8 ob_reg[0x8]; 9914 u8 ob_bias[0x8]; 9915 9916 u8 reserved_at_80[0x20]; 9917 }; 9918 9919 struct mlx5_ifc_slrg_reg_bits { 9920 u8 status[0x4]; 9921 u8 version[0x4]; 9922 u8 local_port[0x8]; 9923 u8 pnat[0x2]; 9924 u8 reserved_at_12[0x2]; 9925 u8 lane[0x4]; 9926 u8 reserved_at_18[0x8]; 9927 9928 u8 time_to_link_up[0x10]; 9929 u8 reserved_at_30[0xc]; 9930 u8 grade_lane_speed[0x4]; 9931 9932 u8 grade_version[0x8]; 9933 u8 grade[0x18]; 9934 9935 u8 reserved_at_60[0x4]; 9936 u8 height_grade_type[0x4]; 9937 u8 height_grade[0x18]; 9938 9939 u8 height_dz[0x10]; 9940 u8 height_dv[0x10]; 9941 9942 u8 reserved_at_a0[0x10]; 9943 u8 height_sigma[0x10]; 9944 9945 u8 reserved_at_c0[0x20]; 9946 9947 u8 reserved_at_e0[0x4]; 9948 u8 phase_grade_type[0x4]; 9949 u8 phase_grade[0x18]; 9950 9951 u8 reserved_at_100[0x8]; 9952 u8 phase_eo_pos[0x8]; 9953 u8 reserved_at_110[0x8]; 9954 u8 phase_eo_neg[0x8]; 9955 9956 u8 ffe_set_tested[0x10]; 9957 u8 test_errors_per_lane[0x10]; 9958 }; 9959 9960 struct mlx5_ifc_pvlc_reg_bits { 9961 u8 reserved_at_0[0x8]; 9962 u8 local_port[0x8]; 9963 u8 reserved_at_10[0x10]; 9964 9965 u8 reserved_at_20[0x1c]; 9966 u8 vl_hw_cap[0x4]; 9967 9968 u8 reserved_at_40[0x1c]; 9969 u8 vl_admin[0x4]; 9970 9971 u8 reserved_at_60[0x1c]; 9972 u8 vl_operational[0x4]; 9973 }; 9974 9975 struct mlx5_ifc_pude_reg_bits { 9976 u8 swid[0x8]; 9977 u8 local_port[0x8]; 9978 u8 reserved_at_10[0x4]; 9979 u8 admin_status[0x4]; 9980 u8 reserved_at_18[0x4]; 9981 u8 oper_status[0x4]; 9982 9983 u8 reserved_at_20[0x60]; 9984 }; 9985 9986 struct mlx5_ifc_ptys_reg_bits { 9987 u8 reserved_at_0[0x1]; 9988 u8 an_disable_admin[0x1]; 9989 u8 an_disable_cap[0x1]; 9990 u8 reserved_at_3[0x5]; 9991 u8 local_port[0x8]; 9992 u8 reserved_at_10[0x8]; 9993 u8 plane_ind[0x4]; 9994 u8 reserved_at_1c[0x1]; 9995 u8 proto_mask[0x3]; 9996 9997 u8 an_status[0x4]; 9998 u8 reserved_at_24[0xc]; 9999 u8 data_rate_oper[0x10]; 10000 10001 u8 ext_eth_proto_capability[0x20]; 10002 10003 u8 eth_proto_capability[0x20]; 10004 10005 u8 ib_link_width_capability[0x10]; 10006 u8 ib_proto_capability[0x10]; 10007 10008 u8 ext_eth_proto_admin[0x20]; 10009 10010 u8 eth_proto_admin[0x20]; 10011 10012 u8 ib_link_width_admin[0x10]; 10013 u8 ib_proto_admin[0x10]; 10014 10015 u8 ext_eth_proto_oper[0x20]; 10016 10017 u8 eth_proto_oper[0x20]; 10018 10019 u8 ib_link_width_oper[0x10]; 10020 u8 ib_proto_oper[0x10]; 10021 10022 u8 reserved_at_160[0x1c]; 10023 u8 connector_type[0x4]; 10024 10025 u8 eth_proto_lp_advertise[0x20]; 10026 10027 u8 reserved_at_1a0[0x60]; 10028 }; 10029 10030 struct mlx5_ifc_mlcr_reg_bits { 10031 u8 reserved_at_0[0x8]; 10032 u8 local_port[0x8]; 10033 u8 reserved_at_10[0x20]; 10034 10035 u8 beacon_duration[0x10]; 10036 u8 reserved_at_40[0x10]; 10037 10038 u8 beacon_remain[0x10]; 10039 }; 10040 10041 struct mlx5_ifc_ptas_reg_bits { 10042 u8 reserved_at_0[0x20]; 10043 10044 u8 algorithm_options[0x10]; 10045 u8 reserved_at_30[0x4]; 10046 u8 repetitions_mode[0x4]; 10047 u8 num_of_repetitions[0x8]; 10048 10049 u8 grade_version[0x8]; 10050 u8 height_grade_type[0x4]; 10051 u8 phase_grade_type[0x4]; 10052 u8 height_grade_weight[0x8]; 10053 u8 phase_grade_weight[0x8]; 10054 10055 u8 gisim_measure_bits[0x10]; 10056 u8 adaptive_tap_measure_bits[0x10]; 10057 10058 u8 ber_bath_high_error_threshold[0x10]; 10059 u8 ber_bath_mid_error_threshold[0x10]; 10060 10061 u8 ber_bath_low_error_threshold[0x10]; 10062 u8 one_ratio_high_threshold[0x10]; 10063 10064 u8 one_ratio_high_mid_threshold[0x10]; 10065 u8 one_ratio_low_mid_threshold[0x10]; 10066 10067 u8 one_ratio_low_threshold[0x10]; 10068 u8 ndeo_error_threshold[0x10]; 10069 10070 u8 mixer_offset_step_size[0x10]; 10071 u8 reserved_at_110[0x8]; 10072 u8 mix90_phase_for_voltage_bath[0x8]; 10073 10074 u8 mixer_offset_start[0x10]; 10075 u8 mixer_offset_end[0x10]; 10076 10077 u8 reserved_at_140[0x15]; 10078 u8 ber_test_time[0xb]; 10079 }; 10080 10081 struct mlx5_ifc_pspa_reg_bits { 10082 u8 swid[0x8]; 10083 u8 local_port[0x8]; 10084 u8 sub_port[0x8]; 10085 u8 reserved_at_18[0x8]; 10086 10087 u8 reserved_at_20[0x20]; 10088 }; 10089 10090 struct mlx5_ifc_pqdr_reg_bits { 10091 u8 reserved_at_0[0x8]; 10092 u8 local_port[0x8]; 10093 u8 reserved_at_10[0x5]; 10094 u8 prio[0x3]; 10095 u8 reserved_at_18[0x6]; 10096 u8 mode[0x2]; 10097 10098 u8 reserved_at_20[0x20]; 10099 10100 u8 reserved_at_40[0x10]; 10101 u8 min_threshold[0x10]; 10102 10103 u8 reserved_at_60[0x10]; 10104 u8 max_threshold[0x10]; 10105 10106 u8 reserved_at_80[0x10]; 10107 u8 mark_probability_denominator[0x10]; 10108 10109 u8 reserved_at_a0[0x60]; 10110 }; 10111 10112 struct mlx5_ifc_ppsc_reg_bits { 10113 u8 reserved_at_0[0x8]; 10114 u8 local_port[0x8]; 10115 u8 reserved_at_10[0x10]; 10116 10117 u8 reserved_at_20[0x60]; 10118 10119 u8 reserved_at_80[0x1c]; 10120 u8 wrps_admin[0x4]; 10121 10122 u8 reserved_at_a0[0x1c]; 10123 u8 wrps_status[0x4]; 10124 10125 u8 reserved_at_c0[0x8]; 10126 u8 up_threshold[0x8]; 10127 u8 reserved_at_d0[0x8]; 10128 u8 down_threshold[0x8]; 10129 10130 u8 reserved_at_e0[0x20]; 10131 10132 u8 reserved_at_100[0x1c]; 10133 u8 srps_admin[0x4]; 10134 10135 u8 reserved_at_120[0x1c]; 10136 u8 srps_status[0x4]; 10137 10138 u8 reserved_at_140[0x40]; 10139 }; 10140 10141 struct mlx5_ifc_pplr_reg_bits { 10142 u8 reserved_at_0[0x8]; 10143 u8 local_port[0x8]; 10144 u8 reserved_at_10[0x10]; 10145 10146 u8 reserved_at_20[0x8]; 10147 u8 lb_cap[0x8]; 10148 u8 reserved_at_30[0x8]; 10149 u8 lb_en[0x8]; 10150 }; 10151 10152 struct mlx5_ifc_pplm_reg_bits { 10153 u8 reserved_at_0[0x8]; 10154 u8 local_port[0x8]; 10155 u8 reserved_at_10[0x10]; 10156 10157 u8 reserved_at_20[0x20]; 10158 10159 u8 port_profile_mode[0x8]; 10160 u8 static_port_profile[0x8]; 10161 u8 active_port_profile[0x8]; 10162 u8 reserved_at_58[0x8]; 10163 10164 u8 retransmission_active[0x8]; 10165 u8 fec_mode_active[0x18]; 10166 10167 u8 rs_fec_correction_bypass_cap[0x4]; 10168 u8 reserved_at_84[0x8]; 10169 u8 fec_override_cap_56g[0x4]; 10170 u8 fec_override_cap_100g[0x4]; 10171 u8 fec_override_cap_50g[0x4]; 10172 u8 fec_override_cap_25g[0x4]; 10173 u8 fec_override_cap_10g_40g[0x4]; 10174 10175 u8 rs_fec_correction_bypass_admin[0x4]; 10176 u8 reserved_at_a4[0x8]; 10177 u8 fec_override_admin_56g[0x4]; 10178 u8 fec_override_admin_100g[0x4]; 10179 u8 fec_override_admin_50g[0x4]; 10180 u8 fec_override_admin_25g[0x4]; 10181 u8 fec_override_admin_10g_40g[0x4]; 10182 10183 u8 fec_override_cap_400g_8x[0x10]; 10184 u8 fec_override_cap_200g_4x[0x10]; 10185 10186 u8 fec_override_cap_100g_2x[0x10]; 10187 u8 fec_override_cap_50g_1x[0x10]; 10188 10189 u8 fec_override_admin_400g_8x[0x10]; 10190 u8 fec_override_admin_200g_4x[0x10]; 10191 10192 u8 fec_override_admin_100g_2x[0x10]; 10193 u8 fec_override_admin_50g_1x[0x10]; 10194 10195 u8 fec_override_cap_800g_8x[0x10]; 10196 u8 fec_override_cap_400g_4x[0x10]; 10197 10198 u8 fec_override_cap_200g_2x[0x10]; 10199 u8 fec_override_cap_100g_1x[0x10]; 10200 10201 u8 reserved_at_180[0xa0]; 10202 10203 u8 fec_override_admin_800g_8x[0x10]; 10204 u8 fec_override_admin_400g_4x[0x10]; 10205 10206 u8 fec_override_admin_200g_2x[0x10]; 10207 u8 fec_override_admin_100g_1x[0x10]; 10208 10209 u8 reserved_at_260[0x60]; 10210 10211 u8 fec_override_cap_1600g_8x[0x10]; 10212 u8 fec_override_cap_800g_4x[0x10]; 10213 10214 u8 fec_override_cap_400g_2x[0x10]; 10215 u8 fec_override_cap_200g_1x[0x10]; 10216 10217 u8 fec_override_admin_1600g_8x[0x10]; 10218 u8 fec_override_admin_800g_4x[0x10]; 10219 10220 u8 fec_override_admin_400g_2x[0x10]; 10221 u8 fec_override_admin_200g_1x[0x10]; 10222 10223 u8 reserved_at_340[0x80]; 10224 }; 10225 10226 struct mlx5_ifc_ppcnt_reg_bits { 10227 u8 swid[0x8]; 10228 u8 local_port[0x8]; 10229 u8 pnat[0x2]; 10230 u8 reserved_at_12[0x8]; 10231 u8 grp[0x6]; 10232 10233 u8 clr[0x1]; 10234 u8 reserved_at_21[0x13]; 10235 u8 plane_ind[0x4]; 10236 u8 reserved_at_38[0x3]; 10237 u8 prio_tc[0x5]; 10238 10239 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set; 10240 }; 10241 10242 struct mlx5_ifc_mpein_reg_bits { 10243 u8 reserved_at_0[0x2]; 10244 u8 depth[0x6]; 10245 u8 pcie_index[0x8]; 10246 u8 node[0x8]; 10247 u8 reserved_at_18[0x8]; 10248 10249 u8 capability_mask[0x20]; 10250 10251 u8 reserved_at_40[0x8]; 10252 u8 link_width_enabled[0x8]; 10253 u8 link_speed_enabled[0x10]; 10254 10255 u8 lane0_physical_position[0x8]; 10256 u8 link_width_active[0x8]; 10257 u8 link_speed_active[0x10]; 10258 10259 u8 num_of_pfs[0x10]; 10260 u8 num_of_vfs[0x10]; 10261 10262 u8 bdf0[0x10]; 10263 u8 reserved_at_b0[0x10]; 10264 10265 u8 max_read_request_size[0x4]; 10266 u8 max_payload_size[0x4]; 10267 u8 reserved_at_c8[0x5]; 10268 u8 pwr_status[0x3]; 10269 u8 port_type[0x4]; 10270 u8 reserved_at_d4[0xb]; 10271 u8 lane_reversal[0x1]; 10272 10273 u8 reserved_at_e0[0x14]; 10274 u8 pci_power[0xc]; 10275 10276 u8 reserved_at_100[0x20]; 10277 10278 u8 device_status[0x10]; 10279 u8 port_state[0x8]; 10280 u8 reserved_at_138[0x8]; 10281 10282 u8 reserved_at_140[0x10]; 10283 u8 receiver_detect_result[0x10]; 10284 10285 u8 reserved_at_160[0x20]; 10286 }; 10287 10288 struct mlx5_ifc_mpcnt_reg_bits { 10289 u8 reserved_at_0[0x8]; 10290 u8 pcie_index[0x8]; 10291 u8 reserved_at_10[0xa]; 10292 u8 grp[0x6]; 10293 10294 u8 clr[0x1]; 10295 u8 reserved_at_21[0x1f]; 10296 10297 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set; 10298 }; 10299 10300 struct mlx5_ifc_ppad_reg_bits { 10301 u8 reserved_at_0[0x3]; 10302 u8 single_mac[0x1]; 10303 u8 reserved_at_4[0x4]; 10304 u8 local_port[0x8]; 10305 u8 mac_47_32[0x10]; 10306 10307 u8 mac_31_0[0x20]; 10308 10309 u8 reserved_at_40[0x40]; 10310 }; 10311 10312 struct mlx5_ifc_pmtu_reg_bits { 10313 u8 reserved_at_0[0x8]; 10314 u8 local_port[0x8]; 10315 u8 reserved_at_10[0x10]; 10316 10317 u8 max_mtu[0x10]; 10318 u8 reserved_at_30[0x10]; 10319 10320 u8 admin_mtu[0x10]; 10321 u8 reserved_at_50[0x10]; 10322 10323 u8 oper_mtu[0x10]; 10324 u8 reserved_at_70[0x10]; 10325 }; 10326 10327 struct mlx5_ifc_pmpr_reg_bits { 10328 u8 reserved_at_0[0x8]; 10329 u8 module[0x8]; 10330 u8 reserved_at_10[0x10]; 10331 10332 u8 reserved_at_20[0x18]; 10333 u8 attenuation_5g[0x8]; 10334 10335 u8 reserved_at_40[0x18]; 10336 u8 attenuation_7g[0x8]; 10337 10338 u8 reserved_at_60[0x18]; 10339 u8 attenuation_12g[0x8]; 10340 }; 10341 10342 struct mlx5_ifc_pmpe_reg_bits { 10343 u8 reserved_at_0[0x8]; 10344 u8 module[0x8]; 10345 u8 reserved_at_10[0xc]; 10346 u8 module_status[0x4]; 10347 10348 u8 reserved_at_20[0x60]; 10349 }; 10350 10351 struct mlx5_ifc_pmpc_reg_bits { 10352 u8 module_state_updated[32][0x8]; 10353 }; 10354 10355 struct mlx5_ifc_pmlpn_reg_bits { 10356 u8 reserved_at_0[0x4]; 10357 u8 mlpn_status[0x4]; 10358 u8 local_port[0x8]; 10359 u8 reserved_at_10[0x10]; 10360 10361 u8 e[0x1]; 10362 u8 reserved_at_21[0x1f]; 10363 }; 10364 10365 struct mlx5_ifc_pmlp_reg_bits { 10366 u8 rxtx[0x1]; 10367 u8 reserved_at_1[0x7]; 10368 u8 local_port[0x8]; 10369 u8 reserved_at_10[0x8]; 10370 u8 width[0x8]; 10371 10372 u8 lane0_module_mapping[0x20]; 10373 10374 u8 lane1_module_mapping[0x20]; 10375 10376 u8 lane2_module_mapping[0x20]; 10377 10378 u8 lane3_module_mapping[0x20]; 10379 10380 u8 reserved_at_a0[0x160]; 10381 }; 10382 10383 struct mlx5_ifc_pmaos_reg_bits { 10384 u8 reserved_at_0[0x8]; 10385 u8 module[0x8]; 10386 u8 reserved_at_10[0x4]; 10387 u8 admin_status[0x4]; 10388 u8 reserved_at_18[0x4]; 10389 u8 oper_status[0x4]; 10390 10391 u8 ase[0x1]; 10392 u8 ee[0x1]; 10393 u8 reserved_at_22[0x1c]; 10394 u8 e[0x2]; 10395 10396 u8 reserved_at_40[0x40]; 10397 }; 10398 10399 struct mlx5_ifc_plpc_reg_bits { 10400 u8 reserved_at_0[0x4]; 10401 u8 profile_id[0xc]; 10402 u8 reserved_at_10[0x4]; 10403 u8 proto_mask[0x4]; 10404 u8 reserved_at_18[0x8]; 10405 10406 u8 reserved_at_20[0x10]; 10407 u8 lane_speed[0x10]; 10408 10409 u8 reserved_at_40[0x17]; 10410 u8 lpbf[0x1]; 10411 u8 fec_mode_policy[0x8]; 10412 10413 u8 retransmission_capability[0x8]; 10414 u8 fec_mode_capability[0x18]; 10415 10416 u8 retransmission_support_admin[0x8]; 10417 u8 fec_mode_support_admin[0x18]; 10418 10419 u8 retransmission_request_admin[0x8]; 10420 u8 fec_mode_request_admin[0x18]; 10421 10422 u8 reserved_at_c0[0x80]; 10423 }; 10424 10425 struct mlx5_ifc_plib_reg_bits { 10426 u8 reserved_at_0[0x8]; 10427 u8 local_port[0x8]; 10428 u8 reserved_at_10[0x8]; 10429 u8 ib_port[0x8]; 10430 10431 u8 reserved_at_20[0x60]; 10432 }; 10433 10434 struct mlx5_ifc_plbf_reg_bits { 10435 u8 reserved_at_0[0x8]; 10436 u8 local_port[0x8]; 10437 u8 reserved_at_10[0xd]; 10438 u8 lbf_mode[0x3]; 10439 10440 u8 reserved_at_20[0x20]; 10441 }; 10442 10443 struct mlx5_ifc_pipg_reg_bits { 10444 u8 reserved_at_0[0x8]; 10445 u8 local_port[0x8]; 10446 u8 reserved_at_10[0x10]; 10447 10448 u8 dic[0x1]; 10449 u8 reserved_at_21[0x19]; 10450 u8 ipg[0x4]; 10451 u8 reserved_at_3e[0x2]; 10452 }; 10453 10454 struct mlx5_ifc_pifr_reg_bits { 10455 u8 reserved_at_0[0x8]; 10456 u8 local_port[0x8]; 10457 u8 reserved_at_10[0x10]; 10458 10459 u8 reserved_at_20[0xe0]; 10460 10461 u8 port_filter[8][0x20]; 10462 10463 u8 port_filter_update_en[8][0x20]; 10464 }; 10465 10466 struct mlx5_ifc_pfcc_reg_bits { 10467 u8 reserved_at_0[0x8]; 10468 u8 local_port[0x8]; 10469 u8 reserved_at_10[0xb]; 10470 u8 ppan_mask_n[0x1]; 10471 u8 minor_stall_mask[0x1]; 10472 u8 critical_stall_mask[0x1]; 10473 u8 reserved_at_1e[0x2]; 10474 10475 u8 ppan[0x4]; 10476 u8 reserved_at_24[0x4]; 10477 u8 prio_mask_tx[0x8]; 10478 u8 reserved_at_30[0x8]; 10479 u8 prio_mask_rx[0x8]; 10480 10481 u8 pptx[0x1]; 10482 u8 aptx[0x1]; 10483 u8 pptx_mask_n[0x1]; 10484 u8 reserved_at_43[0x5]; 10485 u8 pfctx[0x8]; 10486 u8 reserved_at_50[0x10]; 10487 10488 u8 pprx[0x1]; 10489 u8 aprx[0x1]; 10490 u8 pprx_mask_n[0x1]; 10491 u8 reserved_at_63[0x5]; 10492 u8 pfcrx[0x8]; 10493 u8 reserved_at_70[0x10]; 10494 10495 u8 device_stall_minor_watermark[0x10]; 10496 u8 device_stall_critical_watermark[0x10]; 10497 10498 u8 reserved_at_a0[0x60]; 10499 }; 10500 10501 struct mlx5_ifc_pelc_reg_bits { 10502 u8 op[0x4]; 10503 u8 reserved_at_4[0x4]; 10504 u8 local_port[0x8]; 10505 u8 reserved_at_10[0x10]; 10506 10507 u8 op_admin[0x8]; 10508 u8 op_capability[0x8]; 10509 u8 op_request[0x8]; 10510 u8 op_active[0x8]; 10511 10512 u8 admin[0x40]; 10513 10514 u8 capability[0x40]; 10515 10516 u8 request[0x40]; 10517 10518 u8 active[0x40]; 10519 10520 u8 reserved_at_140[0x80]; 10521 }; 10522 10523 struct mlx5_ifc_peir_reg_bits { 10524 u8 reserved_at_0[0x8]; 10525 u8 local_port[0x8]; 10526 u8 reserved_at_10[0x10]; 10527 10528 u8 reserved_at_20[0xc]; 10529 u8 error_count[0x4]; 10530 u8 reserved_at_30[0x10]; 10531 10532 u8 reserved_at_40[0xc]; 10533 u8 lane[0x4]; 10534 u8 reserved_at_50[0x8]; 10535 u8 error_type[0x8]; 10536 }; 10537 10538 struct mlx5_ifc_mpegc_reg_bits { 10539 u8 reserved_at_0[0x30]; 10540 u8 field_select[0x10]; 10541 10542 u8 tx_overflow_sense[0x1]; 10543 u8 mark_cqe[0x1]; 10544 u8 mark_cnp[0x1]; 10545 u8 reserved_at_43[0x1b]; 10546 u8 tx_lossy_overflow_oper[0x2]; 10547 10548 u8 reserved_at_60[0x100]; 10549 }; 10550 10551 struct mlx5_ifc_mpir_reg_bits { 10552 u8 sdm[0x1]; 10553 u8 reserved_at_1[0x1b]; 10554 u8 host_buses[0x4]; 10555 10556 u8 reserved_at_20[0x20]; 10557 10558 u8 local_port[0x8]; 10559 u8 reserved_at_28[0x18]; 10560 10561 u8 reserved_at_60[0x20]; 10562 }; 10563 10564 enum { 10565 MLX5_MTUTC_FREQ_ADJ_UNITS_PPB = 0x0, 10566 MLX5_MTUTC_FREQ_ADJ_UNITS_SCALED_PPM = 0x1, 10567 }; 10568 10569 enum { 10570 MLX5_MTUTC_OPERATION_SET_TIME_IMMEDIATE = 0x1, 10571 MLX5_MTUTC_OPERATION_ADJUST_TIME = 0x2, 10572 MLX5_MTUTC_OPERATION_ADJUST_FREQ_UTC = 0x3, 10573 }; 10574 10575 struct mlx5_ifc_mtutc_reg_bits { 10576 u8 reserved_at_0[0x5]; 10577 u8 freq_adj_units[0x3]; 10578 u8 reserved_at_8[0x3]; 10579 u8 log_max_freq_adjustment[0x5]; 10580 10581 u8 reserved_at_10[0xc]; 10582 u8 operation[0x4]; 10583 10584 u8 freq_adjustment[0x20]; 10585 10586 u8 reserved_at_40[0x40]; 10587 10588 u8 utc_sec[0x20]; 10589 10590 u8 reserved_at_a0[0x2]; 10591 u8 utc_nsec[0x1e]; 10592 10593 u8 time_adjustment[0x20]; 10594 }; 10595 10596 struct mlx5_ifc_pcam_enhanced_features_bits { 10597 u8 reserved_at_0[0x10]; 10598 u8 ppcnt_recovery_counters[0x1]; 10599 u8 reserved_at_11[0xc]; 10600 u8 fec_200G_per_lane_in_pplm[0x1]; 10601 u8 reserved_at_1e[0x2a]; 10602 u8 fec_100G_per_lane_in_pplm[0x1]; 10603 u8 reserved_at_49[0x1f]; 10604 u8 fec_50G_per_lane_in_pplm[0x1]; 10605 u8 reserved_at_69[0x4]; 10606 u8 rx_icrc_encapsulated_counter[0x1]; 10607 u8 reserved_at_6e[0x4]; 10608 u8 ptys_extended_ethernet[0x1]; 10609 u8 reserved_at_73[0x3]; 10610 u8 pfcc_mask[0x1]; 10611 u8 reserved_at_77[0x3]; 10612 u8 per_lane_error_counters[0x1]; 10613 u8 rx_buffer_fullness_counters[0x1]; 10614 u8 ptys_connector_type[0x1]; 10615 u8 reserved_at_7d[0x1]; 10616 u8 ppcnt_discard_group[0x1]; 10617 u8 ppcnt_statistical_group[0x1]; 10618 }; 10619 10620 struct mlx5_ifc_pcam_regs_5000_to_507f_bits { 10621 u8 port_access_reg_cap_mask_127_to_96[0x20]; 10622 u8 port_access_reg_cap_mask_95_to_64[0x20]; 10623 10624 u8 port_access_reg_cap_mask_63_to_36[0x1c]; 10625 u8 pplm[0x1]; 10626 u8 port_access_reg_cap_mask_34_to_32[0x3]; 10627 10628 u8 port_access_reg_cap_mask_31_to_13[0x13]; 10629 u8 pbmc[0x1]; 10630 u8 pptb[0x1]; 10631 u8 port_access_reg_cap_mask_10_to_09[0x2]; 10632 u8 ppcnt[0x1]; 10633 u8 port_access_reg_cap_mask_07_to_00[0x8]; 10634 }; 10635 10636 struct mlx5_ifc_pcam_reg_bits { 10637 u8 reserved_at_0[0x8]; 10638 u8 feature_group[0x8]; 10639 u8 reserved_at_10[0x8]; 10640 u8 access_reg_group[0x8]; 10641 10642 u8 reserved_at_20[0x20]; 10643 10644 union { 10645 struct mlx5_ifc_pcam_regs_5000_to_507f_bits regs_5000_to_507f; 10646 u8 reserved_at_0[0x80]; 10647 } port_access_reg_cap_mask; 10648 10649 u8 reserved_at_c0[0x80]; 10650 10651 union { 10652 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features; 10653 u8 reserved_at_0[0x80]; 10654 } feature_cap_mask; 10655 10656 u8 reserved_at_1c0[0xc0]; 10657 }; 10658 10659 struct mlx5_ifc_mcam_enhanced_features_bits { 10660 u8 reserved_at_0[0x50]; 10661 u8 mtutc_freq_adj_units[0x1]; 10662 u8 mtutc_time_adjustment_extended_range[0x1]; 10663 u8 reserved_at_52[0xb]; 10664 u8 mcia_32dwords[0x1]; 10665 u8 out_pulse_duration_ns[0x1]; 10666 u8 npps_period[0x1]; 10667 u8 reserved_at_60[0xa]; 10668 u8 reset_state[0x1]; 10669 u8 ptpcyc2realtime_modify[0x1]; 10670 u8 reserved_at_6c[0x2]; 10671 u8 pci_status_and_power[0x1]; 10672 u8 reserved_at_6f[0x5]; 10673 u8 mark_tx_action_cnp[0x1]; 10674 u8 mark_tx_action_cqe[0x1]; 10675 u8 dynamic_tx_overflow[0x1]; 10676 u8 reserved_at_77[0x4]; 10677 u8 pcie_outbound_stalled[0x1]; 10678 u8 tx_overflow_buffer_pkt[0x1]; 10679 u8 mtpps_enh_out_per_adj[0x1]; 10680 u8 mtpps_fs[0x1]; 10681 u8 pcie_performance_group[0x1]; 10682 }; 10683 10684 struct mlx5_ifc_mcam_access_reg_bits { 10685 u8 reserved_at_0[0x1c]; 10686 u8 mcda[0x1]; 10687 u8 mcc[0x1]; 10688 u8 mcqi[0x1]; 10689 u8 mcqs[0x1]; 10690 10691 u8 regs_95_to_90[0x6]; 10692 u8 mpir[0x1]; 10693 u8 regs_88_to_87[0x2]; 10694 u8 mpegc[0x1]; 10695 u8 mtutc[0x1]; 10696 u8 regs_84_to_68[0x11]; 10697 u8 tracer_registers[0x4]; 10698 10699 u8 regs_63_to_46[0x12]; 10700 u8 mrtc[0x1]; 10701 u8 regs_44_to_41[0x4]; 10702 u8 mfrl[0x1]; 10703 u8 regs_39_to_32[0x8]; 10704 10705 u8 regs_31_to_11[0x15]; 10706 u8 mtmp[0x1]; 10707 u8 regs_9_to_0[0xa]; 10708 }; 10709 10710 struct mlx5_ifc_mcam_access_reg_bits1 { 10711 u8 regs_127_to_96[0x20]; 10712 10713 u8 regs_95_to_64[0x20]; 10714 10715 u8 regs_63_to_32[0x20]; 10716 10717 u8 regs_31_to_0[0x20]; 10718 }; 10719 10720 struct mlx5_ifc_mcam_access_reg_bits2 { 10721 u8 regs_127_to_99[0x1d]; 10722 u8 mirc[0x1]; 10723 u8 regs_97_to_96[0x2]; 10724 10725 u8 regs_95_to_87[0x09]; 10726 u8 synce_registers[0x2]; 10727 u8 regs_84_to_64[0x15]; 10728 10729 u8 regs_63_to_32[0x20]; 10730 10731 u8 regs_31_to_0[0x20]; 10732 }; 10733 10734 struct mlx5_ifc_mcam_access_reg_bits3 { 10735 u8 regs_127_to_96[0x20]; 10736 10737 u8 regs_95_to_64[0x20]; 10738 10739 u8 regs_63_to_32[0x20]; 10740 10741 u8 regs_31_to_3[0x1d]; 10742 u8 mrtcq[0x1]; 10743 u8 mtctr[0x1]; 10744 u8 mtptm[0x1]; 10745 }; 10746 10747 struct mlx5_ifc_mcam_reg_bits { 10748 u8 reserved_at_0[0x8]; 10749 u8 feature_group[0x8]; 10750 u8 reserved_at_10[0x8]; 10751 u8 access_reg_group[0x8]; 10752 10753 u8 reserved_at_20[0x20]; 10754 10755 union { 10756 struct mlx5_ifc_mcam_access_reg_bits access_regs; 10757 struct mlx5_ifc_mcam_access_reg_bits1 access_regs1; 10758 struct mlx5_ifc_mcam_access_reg_bits2 access_regs2; 10759 struct mlx5_ifc_mcam_access_reg_bits3 access_regs3; 10760 u8 reserved_at_0[0x80]; 10761 } mng_access_reg_cap_mask; 10762 10763 u8 reserved_at_c0[0x80]; 10764 10765 union { 10766 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features; 10767 u8 reserved_at_0[0x80]; 10768 } mng_feature_cap_mask; 10769 10770 u8 reserved_at_1c0[0x80]; 10771 }; 10772 10773 struct mlx5_ifc_qcam_access_reg_cap_mask { 10774 u8 qcam_access_reg_cap_mask_127_to_20[0x6C]; 10775 u8 qpdpm[0x1]; 10776 u8 qcam_access_reg_cap_mask_18_to_4[0x0F]; 10777 u8 qdpm[0x1]; 10778 u8 qpts[0x1]; 10779 u8 qcap[0x1]; 10780 u8 qcam_access_reg_cap_mask_0[0x1]; 10781 }; 10782 10783 struct mlx5_ifc_qcam_qos_feature_cap_mask { 10784 u8 qcam_qos_feature_cap_mask_127_to_1[0x7F]; 10785 u8 qpts_trust_both[0x1]; 10786 }; 10787 10788 struct mlx5_ifc_qcam_reg_bits { 10789 u8 reserved_at_0[0x8]; 10790 u8 feature_group[0x8]; 10791 u8 reserved_at_10[0x8]; 10792 u8 access_reg_group[0x8]; 10793 u8 reserved_at_20[0x20]; 10794 10795 union { 10796 struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap; 10797 u8 reserved_at_0[0x80]; 10798 } qos_access_reg_cap_mask; 10799 10800 u8 reserved_at_c0[0x80]; 10801 10802 union { 10803 struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap; 10804 u8 reserved_at_0[0x80]; 10805 } qos_feature_cap_mask; 10806 10807 u8 reserved_at_1c0[0x80]; 10808 }; 10809 10810 struct mlx5_ifc_core_dump_reg_bits { 10811 u8 reserved_at_0[0x18]; 10812 u8 core_dump_type[0x8]; 10813 10814 u8 reserved_at_20[0x30]; 10815 u8 vhca_id[0x10]; 10816 10817 u8 reserved_at_60[0x8]; 10818 u8 qpn[0x18]; 10819 u8 reserved_at_80[0x180]; 10820 }; 10821 10822 struct mlx5_ifc_pcap_reg_bits { 10823 u8 reserved_at_0[0x8]; 10824 u8 local_port[0x8]; 10825 u8 reserved_at_10[0x10]; 10826 10827 u8 port_capability_mask[4][0x20]; 10828 }; 10829 10830 struct mlx5_ifc_paos_reg_bits { 10831 u8 swid[0x8]; 10832 u8 local_port[0x8]; 10833 u8 reserved_at_10[0x4]; 10834 u8 admin_status[0x4]; 10835 u8 reserved_at_18[0x4]; 10836 u8 oper_status[0x4]; 10837 10838 u8 ase[0x1]; 10839 u8 ee[0x1]; 10840 u8 reserved_at_22[0x1c]; 10841 u8 e[0x2]; 10842 10843 u8 reserved_at_40[0x40]; 10844 }; 10845 10846 struct mlx5_ifc_pamp_reg_bits { 10847 u8 reserved_at_0[0x8]; 10848 u8 opamp_group[0x8]; 10849 u8 reserved_at_10[0xc]; 10850 u8 opamp_group_type[0x4]; 10851 10852 u8 start_index[0x10]; 10853 u8 reserved_at_30[0x4]; 10854 u8 num_of_indices[0xc]; 10855 10856 u8 index_data[18][0x10]; 10857 }; 10858 10859 struct mlx5_ifc_pcmr_reg_bits { 10860 u8 reserved_at_0[0x8]; 10861 u8 local_port[0x8]; 10862 u8 reserved_at_10[0x10]; 10863 10864 u8 entropy_force_cap[0x1]; 10865 u8 entropy_calc_cap[0x1]; 10866 u8 entropy_gre_calc_cap[0x1]; 10867 u8 reserved_at_23[0xf]; 10868 u8 rx_ts_over_crc_cap[0x1]; 10869 u8 reserved_at_33[0xb]; 10870 u8 fcs_cap[0x1]; 10871 u8 reserved_at_3f[0x1]; 10872 10873 u8 entropy_force[0x1]; 10874 u8 entropy_calc[0x1]; 10875 u8 entropy_gre_calc[0x1]; 10876 u8 reserved_at_43[0xf]; 10877 u8 rx_ts_over_crc[0x1]; 10878 u8 reserved_at_53[0xb]; 10879 u8 fcs_chk[0x1]; 10880 u8 reserved_at_5f[0x1]; 10881 }; 10882 10883 struct mlx5_ifc_lane_2_module_mapping_bits { 10884 u8 reserved_at_0[0x4]; 10885 u8 rx_lane[0x4]; 10886 u8 reserved_at_8[0x4]; 10887 u8 tx_lane[0x4]; 10888 u8 reserved_at_10[0x8]; 10889 u8 module[0x8]; 10890 }; 10891 10892 struct mlx5_ifc_bufferx_reg_bits { 10893 u8 reserved_at_0[0x6]; 10894 u8 lossy[0x1]; 10895 u8 epsb[0x1]; 10896 u8 reserved_at_8[0x8]; 10897 u8 size[0x10]; 10898 10899 u8 xoff_threshold[0x10]; 10900 u8 xon_threshold[0x10]; 10901 }; 10902 10903 struct mlx5_ifc_set_node_in_bits { 10904 u8 node_description[64][0x8]; 10905 }; 10906 10907 struct mlx5_ifc_register_power_settings_bits { 10908 u8 reserved_at_0[0x18]; 10909 u8 power_settings_level[0x8]; 10910 10911 u8 reserved_at_20[0x60]; 10912 }; 10913 10914 struct mlx5_ifc_register_host_endianness_bits { 10915 u8 he[0x1]; 10916 u8 reserved_at_1[0x1f]; 10917 10918 u8 reserved_at_20[0x60]; 10919 }; 10920 10921 struct mlx5_ifc_umr_pointer_desc_argument_bits { 10922 u8 reserved_at_0[0x20]; 10923 10924 u8 mkey[0x20]; 10925 10926 u8 addressh_63_32[0x20]; 10927 10928 u8 addressl_31_0[0x20]; 10929 }; 10930 10931 struct mlx5_ifc_ud_adrs_vector_bits { 10932 u8 dc_key[0x40]; 10933 10934 u8 ext[0x1]; 10935 u8 reserved_at_41[0x7]; 10936 u8 destination_qp_dct[0x18]; 10937 10938 u8 static_rate[0x4]; 10939 u8 sl_eth_prio[0x4]; 10940 u8 fl[0x1]; 10941 u8 mlid[0x7]; 10942 u8 rlid_udp_sport[0x10]; 10943 10944 u8 reserved_at_80[0x20]; 10945 10946 u8 rmac_47_16[0x20]; 10947 10948 u8 rmac_15_0[0x10]; 10949 u8 tclass[0x8]; 10950 u8 hop_limit[0x8]; 10951 10952 u8 reserved_at_e0[0x1]; 10953 u8 grh[0x1]; 10954 u8 reserved_at_e2[0x2]; 10955 u8 src_addr_index[0x8]; 10956 u8 flow_label[0x14]; 10957 10958 u8 rgid_rip[16][0x8]; 10959 }; 10960 10961 struct mlx5_ifc_pages_req_event_bits { 10962 u8 reserved_at_0[0x10]; 10963 u8 function_id[0x10]; 10964 10965 u8 num_pages[0x20]; 10966 10967 u8 reserved_at_40[0xa0]; 10968 }; 10969 10970 struct mlx5_ifc_eqe_bits { 10971 u8 reserved_at_0[0x8]; 10972 u8 event_type[0x8]; 10973 u8 reserved_at_10[0x8]; 10974 u8 event_sub_type[0x8]; 10975 10976 u8 reserved_at_20[0xe0]; 10977 10978 union mlx5_ifc_event_auto_bits event_data; 10979 10980 u8 reserved_at_1e0[0x10]; 10981 u8 signature[0x8]; 10982 u8 reserved_at_1f8[0x7]; 10983 u8 owner[0x1]; 10984 }; 10985 10986 enum { 10987 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7, 10988 }; 10989 10990 struct mlx5_ifc_cmd_queue_entry_bits { 10991 u8 type[0x8]; 10992 u8 reserved_at_8[0x18]; 10993 10994 u8 input_length[0x20]; 10995 10996 u8 input_mailbox_pointer_63_32[0x20]; 10997 10998 u8 input_mailbox_pointer_31_9[0x17]; 10999 u8 reserved_at_77[0x9]; 11000 11001 u8 command_input_inline_data[16][0x8]; 11002 11003 u8 command_output_inline_data[16][0x8]; 11004 11005 u8 output_mailbox_pointer_63_32[0x20]; 11006 11007 u8 output_mailbox_pointer_31_9[0x17]; 11008 u8 reserved_at_1b7[0x9]; 11009 11010 u8 output_length[0x20]; 11011 11012 u8 token[0x8]; 11013 u8 signature[0x8]; 11014 u8 reserved_at_1f0[0x8]; 11015 u8 status[0x7]; 11016 u8 ownership[0x1]; 11017 }; 11018 11019 struct mlx5_ifc_cmd_out_bits { 11020 u8 status[0x8]; 11021 u8 reserved_at_8[0x18]; 11022 11023 u8 syndrome[0x20]; 11024 11025 u8 command_output[0x20]; 11026 }; 11027 11028 struct mlx5_ifc_cmd_in_bits { 11029 u8 opcode[0x10]; 11030 u8 reserved_at_10[0x10]; 11031 11032 u8 reserved_at_20[0x10]; 11033 u8 op_mod[0x10]; 11034 11035 u8 command[][0x20]; 11036 }; 11037 11038 struct mlx5_ifc_cmd_if_box_bits { 11039 u8 mailbox_data[512][0x8]; 11040 11041 u8 reserved_at_1000[0x180]; 11042 11043 u8 next_pointer_63_32[0x20]; 11044 11045 u8 next_pointer_31_10[0x16]; 11046 u8 reserved_at_11b6[0xa]; 11047 11048 u8 block_number[0x20]; 11049 11050 u8 reserved_at_11e0[0x8]; 11051 u8 token[0x8]; 11052 u8 ctrl_signature[0x8]; 11053 u8 signature[0x8]; 11054 }; 11055 11056 struct mlx5_ifc_mtt_bits { 11057 u8 ptag_63_32[0x20]; 11058 11059 u8 ptag_31_8[0x18]; 11060 u8 reserved_at_38[0x6]; 11061 u8 wr_en[0x1]; 11062 u8 rd_en[0x1]; 11063 }; 11064 11065 struct mlx5_ifc_query_wol_rol_out_bits { 11066 u8 status[0x8]; 11067 u8 reserved_at_8[0x18]; 11068 11069 u8 syndrome[0x20]; 11070 11071 u8 reserved_at_40[0x10]; 11072 u8 rol_mode[0x8]; 11073 u8 wol_mode[0x8]; 11074 11075 u8 reserved_at_60[0x20]; 11076 }; 11077 11078 struct mlx5_ifc_query_wol_rol_in_bits { 11079 u8 opcode[0x10]; 11080 u8 reserved_at_10[0x10]; 11081 11082 u8 reserved_at_20[0x10]; 11083 u8 op_mod[0x10]; 11084 11085 u8 reserved_at_40[0x40]; 11086 }; 11087 11088 struct mlx5_ifc_set_wol_rol_out_bits { 11089 u8 status[0x8]; 11090 u8 reserved_at_8[0x18]; 11091 11092 u8 syndrome[0x20]; 11093 11094 u8 reserved_at_40[0x40]; 11095 }; 11096 11097 struct mlx5_ifc_set_wol_rol_in_bits { 11098 u8 opcode[0x10]; 11099 u8 reserved_at_10[0x10]; 11100 11101 u8 reserved_at_20[0x10]; 11102 u8 op_mod[0x10]; 11103 11104 u8 rol_mode_valid[0x1]; 11105 u8 wol_mode_valid[0x1]; 11106 u8 reserved_at_42[0xe]; 11107 u8 rol_mode[0x8]; 11108 u8 wol_mode[0x8]; 11109 11110 u8 reserved_at_60[0x20]; 11111 }; 11112 11113 enum { 11114 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0, 11115 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1, 11116 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2, 11117 MLX5_INITIAL_SEG_NIC_INTERFACE_SW_RESET = 0x7, 11118 }; 11119 11120 enum { 11121 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0, 11122 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1, 11123 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2, 11124 }; 11125 11126 enum { 11127 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR = 0x1, 11128 MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC = 0x7, 11129 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR = 0x8, 11130 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR = 0x9, 11131 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR = 0xa, 11132 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR = 0xb, 11133 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN = 0xc, 11134 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR = 0xd, 11135 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV = 0xe, 11136 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR = 0xf, 11137 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR = 0x10, 11138 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PCI_POISONED_ERR = 0x12, 11139 MLX5_INITIAL_SEG_HEALTH_SYNDROME_TRUST_LOCKDOWN_ERR = 0x13, 11140 }; 11141 11142 struct mlx5_ifc_initial_seg_bits { 11143 u8 fw_rev_minor[0x10]; 11144 u8 fw_rev_major[0x10]; 11145 11146 u8 cmd_interface_rev[0x10]; 11147 u8 fw_rev_subminor[0x10]; 11148 11149 u8 reserved_at_40[0x40]; 11150 11151 u8 cmdq_phy_addr_63_32[0x20]; 11152 11153 u8 cmdq_phy_addr_31_12[0x14]; 11154 u8 reserved_at_b4[0x2]; 11155 u8 nic_interface[0x2]; 11156 u8 log_cmdq_size[0x4]; 11157 u8 log_cmdq_stride[0x4]; 11158 11159 u8 command_doorbell_vector[0x20]; 11160 11161 u8 reserved_at_e0[0xf00]; 11162 11163 u8 initializing[0x1]; 11164 u8 reserved_at_fe1[0x4]; 11165 u8 nic_interface_supported[0x3]; 11166 u8 embedded_cpu[0x1]; 11167 u8 reserved_at_fe9[0x17]; 11168 11169 struct mlx5_ifc_health_buffer_bits health_buffer; 11170 11171 u8 no_dram_nic_offset[0x20]; 11172 11173 u8 reserved_at_1220[0x6e40]; 11174 11175 u8 reserved_at_8060[0x1f]; 11176 u8 clear_int[0x1]; 11177 11178 u8 health_syndrome[0x8]; 11179 u8 health_counter[0x18]; 11180 11181 u8 reserved_at_80a0[0x17fc0]; 11182 }; 11183 11184 struct mlx5_ifc_mtpps_reg_bits { 11185 u8 reserved_at_0[0xc]; 11186 u8 cap_number_of_pps_pins[0x4]; 11187 u8 reserved_at_10[0x4]; 11188 u8 cap_max_num_of_pps_in_pins[0x4]; 11189 u8 reserved_at_18[0x4]; 11190 u8 cap_max_num_of_pps_out_pins[0x4]; 11191 11192 u8 reserved_at_20[0x13]; 11193 u8 cap_log_min_npps_period[0x5]; 11194 u8 reserved_at_38[0x3]; 11195 u8 cap_log_min_out_pulse_duration_ns[0x5]; 11196 11197 u8 reserved_at_40[0x4]; 11198 u8 cap_pin_3_mode[0x4]; 11199 u8 reserved_at_48[0x4]; 11200 u8 cap_pin_2_mode[0x4]; 11201 u8 reserved_at_50[0x4]; 11202 u8 cap_pin_1_mode[0x4]; 11203 u8 reserved_at_58[0x4]; 11204 u8 cap_pin_0_mode[0x4]; 11205 11206 u8 reserved_at_60[0x4]; 11207 u8 cap_pin_7_mode[0x4]; 11208 u8 reserved_at_68[0x4]; 11209 u8 cap_pin_6_mode[0x4]; 11210 u8 reserved_at_70[0x4]; 11211 u8 cap_pin_5_mode[0x4]; 11212 u8 reserved_at_78[0x4]; 11213 u8 cap_pin_4_mode[0x4]; 11214 11215 u8 field_select[0x20]; 11216 u8 reserved_at_a0[0x20]; 11217 11218 u8 npps_period[0x40]; 11219 11220 u8 enable[0x1]; 11221 u8 reserved_at_101[0xb]; 11222 u8 pattern[0x4]; 11223 u8 reserved_at_110[0x4]; 11224 u8 pin_mode[0x4]; 11225 u8 pin[0x8]; 11226 11227 u8 reserved_at_120[0x2]; 11228 u8 out_pulse_duration_ns[0x1e]; 11229 11230 u8 time_stamp[0x40]; 11231 11232 u8 out_pulse_duration[0x10]; 11233 u8 out_periodic_adjustment[0x10]; 11234 u8 enhanced_out_periodic_adjustment[0x20]; 11235 11236 u8 reserved_at_1c0[0x20]; 11237 }; 11238 11239 struct mlx5_ifc_mtppse_reg_bits { 11240 u8 reserved_at_0[0x18]; 11241 u8 pin[0x8]; 11242 u8 event_arm[0x1]; 11243 u8 reserved_at_21[0x1b]; 11244 u8 event_generation_mode[0x4]; 11245 u8 reserved_at_40[0x40]; 11246 }; 11247 11248 struct mlx5_ifc_mcqs_reg_bits { 11249 u8 last_index_flag[0x1]; 11250 u8 reserved_at_1[0x7]; 11251 u8 fw_device[0x8]; 11252 u8 component_index[0x10]; 11253 11254 u8 reserved_at_20[0x10]; 11255 u8 identifier[0x10]; 11256 11257 u8 reserved_at_40[0x17]; 11258 u8 component_status[0x5]; 11259 u8 component_update_state[0x4]; 11260 11261 u8 last_update_state_changer_type[0x4]; 11262 u8 last_update_state_changer_host_id[0x4]; 11263 u8 reserved_at_68[0x18]; 11264 }; 11265 11266 struct mlx5_ifc_mcqi_cap_bits { 11267 u8 supported_info_bitmask[0x20]; 11268 11269 u8 component_size[0x20]; 11270 11271 u8 max_component_size[0x20]; 11272 11273 u8 log_mcda_word_size[0x4]; 11274 u8 reserved_at_64[0xc]; 11275 u8 mcda_max_write_size[0x10]; 11276 11277 u8 rd_en[0x1]; 11278 u8 reserved_at_81[0x1]; 11279 u8 match_chip_id[0x1]; 11280 u8 match_psid[0x1]; 11281 u8 check_user_timestamp[0x1]; 11282 u8 match_base_guid_mac[0x1]; 11283 u8 reserved_at_86[0x1a]; 11284 }; 11285 11286 struct mlx5_ifc_mcqi_version_bits { 11287 u8 reserved_at_0[0x2]; 11288 u8 build_time_valid[0x1]; 11289 u8 user_defined_time_valid[0x1]; 11290 u8 reserved_at_4[0x14]; 11291 u8 version_string_length[0x8]; 11292 11293 u8 version[0x20]; 11294 11295 u8 build_time[0x40]; 11296 11297 u8 user_defined_time[0x40]; 11298 11299 u8 build_tool_version[0x20]; 11300 11301 u8 reserved_at_e0[0x20]; 11302 11303 u8 version_string[92][0x8]; 11304 }; 11305 11306 struct mlx5_ifc_mcqi_activation_method_bits { 11307 u8 pending_server_ac_power_cycle[0x1]; 11308 u8 pending_server_dc_power_cycle[0x1]; 11309 u8 pending_server_reboot[0x1]; 11310 u8 pending_fw_reset[0x1]; 11311 u8 auto_activate[0x1]; 11312 u8 all_hosts_sync[0x1]; 11313 u8 device_hw_reset[0x1]; 11314 u8 reserved_at_7[0x19]; 11315 }; 11316 11317 union mlx5_ifc_mcqi_reg_data_bits { 11318 struct mlx5_ifc_mcqi_cap_bits mcqi_caps; 11319 struct mlx5_ifc_mcqi_version_bits mcqi_version; 11320 struct mlx5_ifc_mcqi_activation_method_bits mcqi_activation_mathod; 11321 }; 11322 11323 struct mlx5_ifc_mcqi_reg_bits { 11324 u8 read_pending_component[0x1]; 11325 u8 reserved_at_1[0xf]; 11326 u8 component_index[0x10]; 11327 11328 u8 reserved_at_20[0x20]; 11329 11330 u8 reserved_at_40[0x1b]; 11331 u8 info_type[0x5]; 11332 11333 u8 info_size[0x20]; 11334 11335 u8 offset[0x20]; 11336 11337 u8 reserved_at_a0[0x10]; 11338 u8 data_size[0x10]; 11339 11340 union mlx5_ifc_mcqi_reg_data_bits data[]; 11341 }; 11342 11343 struct mlx5_ifc_mcc_reg_bits { 11344 u8 reserved_at_0[0x4]; 11345 u8 time_elapsed_since_last_cmd[0xc]; 11346 u8 reserved_at_10[0x8]; 11347 u8 instruction[0x8]; 11348 11349 u8 reserved_at_20[0x10]; 11350 u8 component_index[0x10]; 11351 11352 u8 reserved_at_40[0x8]; 11353 u8 update_handle[0x18]; 11354 11355 u8 handle_owner_type[0x4]; 11356 u8 handle_owner_host_id[0x4]; 11357 u8 reserved_at_68[0x1]; 11358 u8 control_progress[0x7]; 11359 u8 error_code[0x8]; 11360 u8 reserved_at_78[0x4]; 11361 u8 control_state[0x4]; 11362 11363 u8 component_size[0x20]; 11364 11365 u8 reserved_at_a0[0x60]; 11366 }; 11367 11368 struct mlx5_ifc_mcda_reg_bits { 11369 u8 reserved_at_0[0x8]; 11370 u8 update_handle[0x18]; 11371 11372 u8 offset[0x20]; 11373 11374 u8 reserved_at_40[0x10]; 11375 u8 size[0x10]; 11376 11377 u8 reserved_at_60[0x20]; 11378 11379 u8 data[][0x20]; 11380 }; 11381 11382 enum { 11383 MLX5_MFRL_REG_PCI_RESET_METHOD_LINK_TOGGLE = 0, 11384 MLX5_MFRL_REG_PCI_RESET_METHOD_HOT_RESET = 1, 11385 }; 11386 11387 enum { 11388 MLX5_MFRL_REG_RESET_STATE_IDLE = 0, 11389 MLX5_MFRL_REG_RESET_STATE_IN_NEGOTIATION = 1, 11390 MLX5_MFRL_REG_RESET_STATE_RESET_IN_PROGRESS = 2, 11391 MLX5_MFRL_REG_RESET_STATE_NEG_TIMEOUT = 3, 11392 MLX5_MFRL_REG_RESET_STATE_NACK = 4, 11393 MLX5_MFRL_REG_RESET_STATE_UNLOAD_TIMEOUT = 5, 11394 }; 11395 11396 enum { 11397 MLX5_MFRL_REG_RESET_TYPE_FULL_CHIP = BIT(0), 11398 MLX5_MFRL_REG_RESET_TYPE_NET_PORT_ALIVE = BIT(1), 11399 }; 11400 11401 enum { 11402 MLX5_MFRL_REG_RESET_LEVEL0 = BIT(0), 11403 MLX5_MFRL_REG_RESET_LEVEL3 = BIT(3), 11404 MLX5_MFRL_REG_RESET_LEVEL6 = BIT(6), 11405 }; 11406 11407 struct mlx5_ifc_mfrl_reg_bits { 11408 u8 reserved_at_0[0x20]; 11409 11410 u8 reserved_at_20[0x2]; 11411 u8 pci_sync_for_fw_update_start[0x1]; 11412 u8 pci_sync_for_fw_update_resp[0x2]; 11413 u8 rst_type_sel[0x3]; 11414 u8 pci_reset_req_method[0x3]; 11415 u8 reserved_at_2b[0x1]; 11416 u8 reset_state[0x4]; 11417 u8 reset_type[0x8]; 11418 u8 reset_level[0x8]; 11419 }; 11420 11421 struct mlx5_ifc_mirc_reg_bits { 11422 u8 reserved_at_0[0x18]; 11423 u8 status_code[0x8]; 11424 11425 u8 reserved_at_20[0x20]; 11426 }; 11427 11428 struct mlx5_ifc_pddr_monitor_opcode_bits { 11429 u8 reserved_at_0[0x10]; 11430 u8 monitor_opcode[0x10]; 11431 }; 11432 11433 union mlx5_ifc_pddr_troubleshooting_page_status_opcode_auto_bits { 11434 struct mlx5_ifc_pddr_monitor_opcode_bits pddr_monitor_opcode; 11435 u8 reserved_at_0[0x20]; 11436 }; 11437 11438 enum { 11439 /* Monitor opcodes */ 11440 MLX5_PDDR_REG_TRBLSH_GROUP_OPCODE_MONITOR = 0x0, 11441 }; 11442 11443 struct mlx5_ifc_pddr_troubleshooting_page_bits { 11444 u8 reserved_at_0[0x10]; 11445 u8 group_opcode[0x10]; 11446 11447 union mlx5_ifc_pddr_troubleshooting_page_status_opcode_auto_bits status_opcode; 11448 11449 u8 reserved_at_40[0x20]; 11450 11451 u8 status_message[59][0x20]; 11452 }; 11453 11454 union mlx5_ifc_pddr_reg_page_data_auto_bits { 11455 struct mlx5_ifc_pddr_troubleshooting_page_bits pddr_troubleshooting_page; 11456 u8 reserved_at_0[0x7c0]; 11457 }; 11458 11459 enum { 11460 MLX5_PDDR_REG_PAGE_SELECT_TROUBLESHOOTING_INFO_PAGE = 0x1, 11461 }; 11462 11463 struct mlx5_ifc_pddr_reg_bits { 11464 u8 reserved_at_0[0x8]; 11465 u8 local_port[0x8]; 11466 u8 pnat[0x2]; 11467 u8 reserved_at_12[0xe]; 11468 11469 u8 reserved_at_20[0x18]; 11470 u8 page_select[0x8]; 11471 11472 union mlx5_ifc_pddr_reg_page_data_auto_bits page_data; 11473 }; 11474 11475 struct mlx5_ifc_mrtc_reg_bits { 11476 u8 time_synced[0x1]; 11477 u8 reserved_at_1[0x1f]; 11478 11479 u8 reserved_at_20[0x20]; 11480 11481 u8 time_h[0x20]; 11482 11483 u8 time_l[0x20]; 11484 }; 11485 11486 struct mlx5_ifc_mtcap_reg_bits { 11487 u8 reserved_at_0[0x19]; 11488 u8 sensor_count[0x7]; 11489 11490 u8 reserved_at_20[0x20]; 11491 11492 u8 sensor_map[0x40]; 11493 }; 11494 11495 struct mlx5_ifc_mtmp_reg_bits { 11496 u8 reserved_at_0[0x14]; 11497 u8 sensor_index[0xc]; 11498 11499 u8 reserved_at_20[0x10]; 11500 u8 temperature[0x10]; 11501 11502 u8 mte[0x1]; 11503 u8 mtr[0x1]; 11504 u8 reserved_at_42[0xe]; 11505 u8 max_temperature[0x10]; 11506 11507 u8 tee[0x2]; 11508 u8 reserved_at_62[0xe]; 11509 u8 temp_threshold_hi[0x10]; 11510 11511 u8 reserved_at_80[0x10]; 11512 u8 temp_threshold_lo[0x10]; 11513 11514 u8 reserved_at_a0[0x20]; 11515 11516 u8 sensor_name_hi[0x20]; 11517 u8 sensor_name_lo[0x20]; 11518 }; 11519 11520 struct mlx5_ifc_mtptm_reg_bits { 11521 u8 reserved_at_0[0x10]; 11522 u8 psta[0x1]; 11523 u8 reserved_at_11[0xf]; 11524 11525 u8 reserved_at_20[0x60]; 11526 }; 11527 11528 enum { 11529 MLX5_MTCTR_REQUEST_NOP = 0x0, 11530 MLX5_MTCTR_REQUEST_PTM_ROOT_CLOCK = 0x1, 11531 MLX5_MTCTR_REQUEST_FREE_RUNNING_COUNTER = 0x2, 11532 MLX5_MTCTR_REQUEST_REAL_TIME_CLOCK = 0x3, 11533 }; 11534 11535 struct mlx5_ifc_mtctr_reg_bits { 11536 u8 first_clock_timestamp_request[0x8]; 11537 u8 second_clock_timestamp_request[0x8]; 11538 u8 reserved_at_10[0x10]; 11539 11540 u8 first_clock_valid[0x1]; 11541 u8 second_clock_valid[0x1]; 11542 u8 reserved_at_22[0x1e]; 11543 11544 u8 first_clock_timestamp[0x40]; 11545 u8 second_clock_timestamp[0x40]; 11546 }; 11547 11548 union mlx5_ifc_ports_control_registers_document_bits { 11549 struct mlx5_ifc_bufferx_reg_bits bufferx_reg; 11550 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 11551 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 11552 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 11553 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 11554 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 11555 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 11556 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout; 11557 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout; 11558 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping; 11559 struct mlx5_ifc_pamp_reg_bits pamp_reg; 11560 struct mlx5_ifc_paos_reg_bits paos_reg; 11561 struct mlx5_ifc_pcap_reg_bits pcap_reg; 11562 struct mlx5_ifc_pddr_monitor_opcode_bits pddr_monitor_opcode; 11563 struct mlx5_ifc_pddr_reg_bits pddr_reg; 11564 struct mlx5_ifc_pddr_troubleshooting_page_bits pddr_troubleshooting_page; 11565 struct mlx5_ifc_peir_reg_bits peir_reg; 11566 struct mlx5_ifc_pelc_reg_bits pelc_reg; 11567 struct mlx5_ifc_pfcc_reg_bits pfcc_reg; 11568 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 11569 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 11570 struct mlx5_ifc_pifr_reg_bits pifr_reg; 11571 struct mlx5_ifc_pipg_reg_bits pipg_reg; 11572 struct mlx5_ifc_plbf_reg_bits plbf_reg; 11573 struct mlx5_ifc_plib_reg_bits plib_reg; 11574 struct mlx5_ifc_plpc_reg_bits plpc_reg; 11575 struct mlx5_ifc_pmaos_reg_bits pmaos_reg; 11576 struct mlx5_ifc_pmlp_reg_bits pmlp_reg; 11577 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg; 11578 struct mlx5_ifc_pmpc_reg_bits pmpc_reg; 11579 struct mlx5_ifc_pmpe_reg_bits pmpe_reg; 11580 struct mlx5_ifc_pmpr_reg_bits pmpr_reg; 11581 struct mlx5_ifc_pmtu_reg_bits pmtu_reg; 11582 struct mlx5_ifc_ppad_reg_bits ppad_reg; 11583 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg; 11584 struct mlx5_ifc_mpein_reg_bits mpein_reg; 11585 struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg; 11586 struct mlx5_ifc_pplm_reg_bits pplm_reg; 11587 struct mlx5_ifc_pplr_reg_bits pplr_reg; 11588 struct mlx5_ifc_ppsc_reg_bits ppsc_reg; 11589 struct mlx5_ifc_pqdr_reg_bits pqdr_reg; 11590 struct mlx5_ifc_pspa_reg_bits pspa_reg; 11591 struct mlx5_ifc_ptas_reg_bits ptas_reg; 11592 struct mlx5_ifc_ptys_reg_bits ptys_reg; 11593 struct mlx5_ifc_mlcr_reg_bits mlcr_reg; 11594 struct mlx5_ifc_pude_reg_bits pude_reg; 11595 struct mlx5_ifc_pvlc_reg_bits pvlc_reg; 11596 struct mlx5_ifc_slrg_reg_bits slrg_reg; 11597 struct mlx5_ifc_sltp_reg_bits sltp_reg; 11598 struct mlx5_ifc_mtpps_reg_bits mtpps_reg; 11599 struct mlx5_ifc_mtppse_reg_bits mtppse_reg; 11600 struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg; 11601 struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits; 11602 struct mlx5_ifc_fpga_cap_bits fpga_cap_bits; 11603 struct mlx5_ifc_mcqi_reg_bits mcqi_reg; 11604 struct mlx5_ifc_mcc_reg_bits mcc_reg; 11605 struct mlx5_ifc_mcda_reg_bits mcda_reg; 11606 struct mlx5_ifc_mirc_reg_bits mirc_reg; 11607 struct mlx5_ifc_mfrl_reg_bits mfrl_reg; 11608 struct mlx5_ifc_mtutc_reg_bits mtutc_reg; 11609 struct mlx5_ifc_mrtc_reg_bits mrtc_reg; 11610 struct mlx5_ifc_mtcap_reg_bits mtcap_reg; 11611 struct mlx5_ifc_mtmp_reg_bits mtmp_reg; 11612 struct mlx5_ifc_mtptm_reg_bits mtptm_reg; 11613 struct mlx5_ifc_mtctr_reg_bits mtctr_reg; 11614 u8 reserved_at_0[0x60e0]; 11615 }; 11616 11617 union mlx5_ifc_debug_enhancements_document_bits { 11618 struct mlx5_ifc_health_buffer_bits health_buffer; 11619 u8 reserved_at_0[0x200]; 11620 }; 11621 11622 union mlx5_ifc_uplink_pci_interface_document_bits { 11623 struct mlx5_ifc_initial_seg_bits initial_seg; 11624 u8 reserved_at_0[0x20060]; 11625 }; 11626 11627 struct mlx5_ifc_set_flow_table_root_out_bits { 11628 u8 status[0x8]; 11629 u8 reserved_at_8[0x18]; 11630 11631 u8 syndrome[0x20]; 11632 11633 u8 reserved_at_40[0x40]; 11634 }; 11635 11636 struct mlx5_ifc_set_flow_table_root_in_bits { 11637 u8 opcode[0x10]; 11638 u8 reserved_at_10[0x10]; 11639 11640 u8 reserved_at_20[0x10]; 11641 u8 op_mod[0x10]; 11642 11643 u8 other_vport[0x1]; 11644 u8 reserved_at_41[0xf]; 11645 u8 vport_number[0x10]; 11646 11647 u8 reserved_at_60[0x20]; 11648 11649 u8 table_type[0x8]; 11650 u8 reserved_at_88[0x7]; 11651 u8 table_of_other_vport[0x1]; 11652 u8 table_vport_number[0x10]; 11653 11654 u8 reserved_at_a0[0x8]; 11655 u8 table_id[0x18]; 11656 11657 u8 reserved_at_c0[0x8]; 11658 u8 underlay_qpn[0x18]; 11659 u8 table_eswitch_owner_vhca_id_valid[0x1]; 11660 u8 reserved_at_e1[0xf]; 11661 u8 table_eswitch_owner_vhca_id[0x10]; 11662 u8 reserved_at_100[0x100]; 11663 }; 11664 11665 enum { 11666 MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = (1UL << 0), 11667 MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15), 11668 }; 11669 11670 struct mlx5_ifc_modify_flow_table_out_bits { 11671 u8 status[0x8]; 11672 u8 reserved_at_8[0x18]; 11673 11674 u8 syndrome[0x20]; 11675 11676 u8 reserved_at_40[0x40]; 11677 }; 11678 11679 struct mlx5_ifc_modify_flow_table_in_bits { 11680 u8 opcode[0x10]; 11681 u8 reserved_at_10[0x10]; 11682 11683 u8 reserved_at_20[0x10]; 11684 u8 op_mod[0x10]; 11685 11686 u8 other_vport[0x1]; 11687 u8 reserved_at_41[0xf]; 11688 u8 vport_number[0x10]; 11689 11690 u8 reserved_at_60[0x10]; 11691 u8 modify_field_select[0x10]; 11692 11693 u8 table_type[0x8]; 11694 u8 reserved_at_88[0x18]; 11695 11696 u8 reserved_at_a0[0x8]; 11697 u8 table_id[0x18]; 11698 11699 struct mlx5_ifc_flow_table_context_bits flow_table_context; 11700 }; 11701 11702 struct mlx5_ifc_ets_tcn_config_reg_bits { 11703 u8 g[0x1]; 11704 u8 b[0x1]; 11705 u8 r[0x1]; 11706 u8 reserved_at_3[0x9]; 11707 u8 group[0x4]; 11708 u8 reserved_at_10[0x9]; 11709 u8 bw_allocation[0x7]; 11710 11711 u8 reserved_at_20[0xc]; 11712 u8 max_bw_units[0x4]; 11713 u8 reserved_at_30[0x8]; 11714 u8 max_bw_value[0x8]; 11715 }; 11716 11717 struct mlx5_ifc_ets_global_config_reg_bits { 11718 u8 reserved_at_0[0x2]; 11719 u8 r[0x1]; 11720 u8 reserved_at_3[0x1d]; 11721 11722 u8 reserved_at_20[0xc]; 11723 u8 max_bw_units[0x4]; 11724 u8 reserved_at_30[0x8]; 11725 u8 max_bw_value[0x8]; 11726 }; 11727 11728 struct mlx5_ifc_qetc_reg_bits { 11729 u8 reserved_at_0[0x8]; 11730 u8 port_number[0x8]; 11731 u8 reserved_at_10[0x30]; 11732 11733 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8]; 11734 struct mlx5_ifc_ets_global_config_reg_bits global_configuration; 11735 }; 11736 11737 struct mlx5_ifc_qpdpm_dscp_reg_bits { 11738 u8 e[0x1]; 11739 u8 reserved_at_01[0x0b]; 11740 u8 prio[0x04]; 11741 }; 11742 11743 struct mlx5_ifc_qpdpm_reg_bits { 11744 u8 reserved_at_0[0x8]; 11745 u8 local_port[0x8]; 11746 u8 reserved_at_10[0x10]; 11747 struct mlx5_ifc_qpdpm_dscp_reg_bits dscp[64]; 11748 }; 11749 11750 struct mlx5_ifc_qpts_reg_bits { 11751 u8 reserved_at_0[0x8]; 11752 u8 local_port[0x8]; 11753 u8 reserved_at_10[0x2d]; 11754 u8 trust_state[0x3]; 11755 }; 11756 11757 struct mlx5_ifc_pptb_reg_bits { 11758 u8 reserved_at_0[0x2]; 11759 u8 mm[0x2]; 11760 u8 reserved_at_4[0x4]; 11761 u8 local_port[0x8]; 11762 u8 reserved_at_10[0x6]; 11763 u8 cm[0x1]; 11764 u8 um[0x1]; 11765 u8 pm[0x8]; 11766 11767 u8 prio_x_buff[0x20]; 11768 11769 u8 pm_msb[0x8]; 11770 u8 reserved_at_48[0x10]; 11771 u8 ctrl_buff[0x4]; 11772 u8 untagged_buff[0x4]; 11773 }; 11774 11775 struct mlx5_ifc_sbcam_reg_bits { 11776 u8 reserved_at_0[0x8]; 11777 u8 feature_group[0x8]; 11778 u8 reserved_at_10[0x8]; 11779 u8 access_reg_group[0x8]; 11780 11781 u8 reserved_at_20[0x20]; 11782 11783 u8 sb_access_reg_cap_mask[4][0x20]; 11784 11785 u8 reserved_at_c0[0x80]; 11786 11787 u8 sb_feature_cap_mask[4][0x20]; 11788 11789 u8 reserved_at_1c0[0x40]; 11790 11791 u8 cap_total_buffer_size[0x20]; 11792 11793 u8 cap_cell_size[0x10]; 11794 u8 cap_max_pg_buffers[0x8]; 11795 u8 cap_num_pool_supported[0x8]; 11796 11797 u8 reserved_at_240[0x8]; 11798 u8 cap_sbsr_stat_size[0x8]; 11799 u8 cap_max_tclass_data[0x8]; 11800 u8 cap_max_cpu_ingress_tclass_sb[0x8]; 11801 }; 11802 11803 struct mlx5_ifc_pbmc_reg_bits { 11804 u8 reserved_at_0[0x8]; 11805 u8 local_port[0x8]; 11806 u8 reserved_at_10[0x10]; 11807 11808 u8 xoff_timer_value[0x10]; 11809 u8 xoff_refresh[0x10]; 11810 11811 u8 reserved_at_40[0x9]; 11812 u8 fullness_threshold[0x7]; 11813 u8 port_buffer_size[0x10]; 11814 11815 struct mlx5_ifc_bufferx_reg_bits buffer[10]; 11816 11817 u8 reserved_at_2e0[0x80]; 11818 }; 11819 11820 struct mlx5_ifc_sbpr_reg_bits { 11821 u8 desc[0x1]; 11822 u8 snap[0x1]; 11823 u8 reserved_at_2[0x4]; 11824 u8 dir[0x2]; 11825 u8 reserved_at_8[0x14]; 11826 u8 pool[0x4]; 11827 11828 u8 infi_size[0x1]; 11829 u8 reserved_at_21[0x7]; 11830 u8 size[0x18]; 11831 11832 u8 reserved_at_40[0x1c]; 11833 u8 mode[0x4]; 11834 11835 u8 reserved_at_60[0x8]; 11836 u8 buff_occupancy[0x18]; 11837 11838 u8 clr[0x1]; 11839 u8 reserved_at_81[0x7]; 11840 u8 max_buff_occupancy[0x18]; 11841 11842 u8 reserved_at_a0[0x8]; 11843 u8 ext_buff_occupancy[0x18]; 11844 }; 11845 11846 struct mlx5_ifc_sbcm_reg_bits { 11847 u8 desc[0x1]; 11848 u8 snap[0x1]; 11849 u8 reserved_at_2[0x6]; 11850 u8 local_port[0x8]; 11851 u8 pnat[0x2]; 11852 u8 pg_buff[0x6]; 11853 u8 reserved_at_18[0x6]; 11854 u8 dir[0x2]; 11855 11856 u8 reserved_at_20[0x1f]; 11857 u8 exc[0x1]; 11858 11859 u8 reserved_at_40[0x40]; 11860 11861 u8 reserved_at_80[0x8]; 11862 u8 buff_occupancy[0x18]; 11863 11864 u8 clr[0x1]; 11865 u8 reserved_at_a1[0x7]; 11866 u8 max_buff_occupancy[0x18]; 11867 11868 u8 reserved_at_c0[0x8]; 11869 u8 min_buff[0x18]; 11870 11871 u8 infi_max[0x1]; 11872 u8 reserved_at_e1[0x7]; 11873 u8 max_buff[0x18]; 11874 11875 u8 reserved_at_100[0x20]; 11876 11877 u8 reserved_at_120[0x1c]; 11878 u8 pool[0x4]; 11879 }; 11880 11881 struct mlx5_ifc_qtct_reg_bits { 11882 u8 reserved_at_0[0x8]; 11883 u8 port_number[0x8]; 11884 u8 reserved_at_10[0xd]; 11885 u8 prio[0x3]; 11886 11887 u8 reserved_at_20[0x1d]; 11888 u8 tclass[0x3]; 11889 }; 11890 11891 struct mlx5_ifc_mcia_reg_bits { 11892 u8 l[0x1]; 11893 u8 reserved_at_1[0x7]; 11894 u8 module[0x8]; 11895 u8 reserved_at_10[0x8]; 11896 u8 status[0x8]; 11897 11898 u8 i2c_device_address[0x8]; 11899 u8 page_number[0x8]; 11900 u8 device_address[0x10]; 11901 11902 u8 reserved_at_40[0x10]; 11903 u8 size[0x10]; 11904 11905 u8 reserved_at_60[0x20]; 11906 11907 u8 dword_0[0x20]; 11908 u8 dword_1[0x20]; 11909 u8 dword_2[0x20]; 11910 u8 dword_3[0x20]; 11911 u8 dword_4[0x20]; 11912 u8 dword_5[0x20]; 11913 u8 dword_6[0x20]; 11914 u8 dword_7[0x20]; 11915 u8 dword_8[0x20]; 11916 u8 dword_9[0x20]; 11917 u8 dword_10[0x20]; 11918 u8 dword_11[0x20]; 11919 }; 11920 11921 struct mlx5_ifc_dcbx_param_bits { 11922 u8 dcbx_cee_cap[0x1]; 11923 u8 dcbx_ieee_cap[0x1]; 11924 u8 dcbx_standby_cap[0x1]; 11925 u8 reserved_at_3[0x5]; 11926 u8 port_number[0x8]; 11927 u8 reserved_at_10[0xa]; 11928 u8 max_application_table_size[6]; 11929 u8 reserved_at_20[0x15]; 11930 u8 version_oper[0x3]; 11931 u8 reserved_at_38[5]; 11932 u8 version_admin[0x3]; 11933 u8 willing_admin[0x1]; 11934 u8 reserved_at_41[0x3]; 11935 u8 pfc_cap_oper[0x4]; 11936 u8 reserved_at_48[0x4]; 11937 u8 pfc_cap_admin[0x4]; 11938 u8 reserved_at_50[0x4]; 11939 u8 num_of_tc_oper[0x4]; 11940 u8 reserved_at_58[0x4]; 11941 u8 num_of_tc_admin[0x4]; 11942 u8 remote_willing[0x1]; 11943 u8 reserved_at_61[3]; 11944 u8 remote_pfc_cap[4]; 11945 u8 reserved_at_68[0x14]; 11946 u8 remote_num_of_tc[0x4]; 11947 u8 reserved_at_80[0x18]; 11948 u8 error[0x8]; 11949 u8 reserved_at_a0[0x160]; 11950 }; 11951 11952 enum { 11953 MLX5_LAG_PORT_SELECT_MODE_QUEUE_AFFINITY = 0, 11954 MLX5_LAG_PORT_SELECT_MODE_PORT_SELECT_FT = 1, 11955 MLX5_LAG_PORT_SELECT_MODE_PORT_SELECT_MPESW = 2, 11956 }; 11957 11958 struct mlx5_ifc_lagc_bits { 11959 u8 fdb_selection_mode[0x1]; 11960 u8 reserved_at_1[0x14]; 11961 u8 port_select_mode[0x3]; 11962 u8 reserved_at_18[0x5]; 11963 u8 lag_state[0x3]; 11964 11965 u8 reserved_at_20[0xc]; 11966 u8 active_port[0x4]; 11967 u8 reserved_at_30[0x4]; 11968 u8 tx_remap_affinity_2[0x4]; 11969 u8 reserved_at_38[0x4]; 11970 u8 tx_remap_affinity_1[0x4]; 11971 }; 11972 11973 struct mlx5_ifc_create_lag_out_bits { 11974 u8 status[0x8]; 11975 u8 reserved_at_8[0x18]; 11976 11977 u8 syndrome[0x20]; 11978 11979 u8 reserved_at_40[0x40]; 11980 }; 11981 11982 struct mlx5_ifc_create_lag_in_bits { 11983 u8 opcode[0x10]; 11984 u8 reserved_at_10[0x10]; 11985 11986 u8 reserved_at_20[0x10]; 11987 u8 op_mod[0x10]; 11988 11989 struct mlx5_ifc_lagc_bits ctx; 11990 }; 11991 11992 struct mlx5_ifc_modify_lag_out_bits { 11993 u8 status[0x8]; 11994 u8 reserved_at_8[0x18]; 11995 11996 u8 syndrome[0x20]; 11997 11998 u8 reserved_at_40[0x40]; 11999 }; 12000 12001 struct mlx5_ifc_modify_lag_in_bits { 12002 u8 opcode[0x10]; 12003 u8 reserved_at_10[0x10]; 12004 12005 u8 reserved_at_20[0x10]; 12006 u8 op_mod[0x10]; 12007 12008 u8 reserved_at_40[0x20]; 12009 u8 field_select[0x20]; 12010 12011 struct mlx5_ifc_lagc_bits ctx; 12012 }; 12013 12014 struct mlx5_ifc_query_lag_out_bits { 12015 u8 status[0x8]; 12016 u8 reserved_at_8[0x18]; 12017 12018 u8 syndrome[0x20]; 12019 12020 struct mlx5_ifc_lagc_bits ctx; 12021 }; 12022 12023 struct mlx5_ifc_query_lag_in_bits { 12024 u8 opcode[0x10]; 12025 u8 reserved_at_10[0x10]; 12026 12027 u8 reserved_at_20[0x10]; 12028 u8 op_mod[0x10]; 12029 12030 u8 reserved_at_40[0x40]; 12031 }; 12032 12033 struct mlx5_ifc_destroy_lag_out_bits { 12034 u8 status[0x8]; 12035 u8 reserved_at_8[0x18]; 12036 12037 u8 syndrome[0x20]; 12038 12039 u8 reserved_at_40[0x40]; 12040 }; 12041 12042 struct mlx5_ifc_destroy_lag_in_bits { 12043 u8 opcode[0x10]; 12044 u8 reserved_at_10[0x10]; 12045 12046 u8 reserved_at_20[0x10]; 12047 u8 op_mod[0x10]; 12048 12049 u8 reserved_at_40[0x40]; 12050 }; 12051 12052 struct mlx5_ifc_create_vport_lag_out_bits { 12053 u8 status[0x8]; 12054 u8 reserved_at_8[0x18]; 12055 12056 u8 syndrome[0x20]; 12057 12058 u8 reserved_at_40[0x40]; 12059 }; 12060 12061 struct mlx5_ifc_create_vport_lag_in_bits { 12062 u8 opcode[0x10]; 12063 u8 reserved_at_10[0x10]; 12064 12065 u8 reserved_at_20[0x10]; 12066 u8 op_mod[0x10]; 12067 12068 u8 reserved_at_40[0x40]; 12069 }; 12070 12071 struct mlx5_ifc_destroy_vport_lag_out_bits { 12072 u8 status[0x8]; 12073 u8 reserved_at_8[0x18]; 12074 12075 u8 syndrome[0x20]; 12076 12077 u8 reserved_at_40[0x40]; 12078 }; 12079 12080 struct mlx5_ifc_destroy_vport_lag_in_bits { 12081 u8 opcode[0x10]; 12082 u8 reserved_at_10[0x10]; 12083 12084 u8 reserved_at_20[0x10]; 12085 u8 op_mod[0x10]; 12086 12087 u8 reserved_at_40[0x40]; 12088 }; 12089 12090 enum { 12091 MLX5_MODIFY_MEMIC_OP_MOD_ALLOC, 12092 MLX5_MODIFY_MEMIC_OP_MOD_DEALLOC, 12093 }; 12094 12095 struct mlx5_ifc_modify_memic_in_bits { 12096 u8 opcode[0x10]; 12097 u8 uid[0x10]; 12098 12099 u8 reserved_at_20[0x10]; 12100 u8 op_mod[0x10]; 12101 12102 u8 reserved_at_40[0x20]; 12103 12104 u8 reserved_at_60[0x18]; 12105 u8 memic_operation_type[0x8]; 12106 12107 u8 memic_start_addr[0x40]; 12108 12109 u8 reserved_at_c0[0x140]; 12110 }; 12111 12112 struct mlx5_ifc_modify_memic_out_bits { 12113 u8 status[0x8]; 12114 u8 reserved_at_8[0x18]; 12115 12116 u8 syndrome[0x20]; 12117 12118 u8 reserved_at_40[0x40]; 12119 12120 u8 memic_operation_addr[0x40]; 12121 12122 u8 reserved_at_c0[0x140]; 12123 }; 12124 12125 struct mlx5_ifc_alloc_memic_in_bits { 12126 u8 opcode[0x10]; 12127 u8 reserved_at_10[0x10]; 12128 12129 u8 reserved_at_20[0x10]; 12130 u8 op_mod[0x10]; 12131 12132 u8 reserved_at_30[0x20]; 12133 12134 u8 reserved_at_40[0x18]; 12135 u8 log_memic_addr_alignment[0x8]; 12136 12137 u8 range_start_addr[0x40]; 12138 12139 u8 range_size[0x20]; 12140 12141 u8 memic_size[0x20]; 12142 }; 12143 12144 struct mlx5_ifc_alloc_memic_out_bits { 12145 u8 status[0x8]; 12146 u8 reserved_at_8[0x18]; 12147 12148 u8 syndrome[0x20]; 12149 12150 u8 memic_start_addr[0x40]; 12151 }; 12152 12153 struct mlx5_ifc_dealloc_memic_in_bits { 12154 u8 opcode[0x10]; 12155 u8 reserved_at_10[0x10]; 12156 12157 u8 reserved_at_20[0x10]; 12158 u8 op_mod[0x10]; 12159 12160 u8 reserved_at_40[0x40]; 12161 12162 u8 memic_start_addr[0x40]; 12163 12164 u8 memic_size[0x20]; 12165 12166 u8 reserved_at_e0[0x20]; 12167 }; 12168 12169 struct mlx5_ifc_dealloc_memic_out_bits { 12170 u8 status[0x8]; 12171 u8 reserved_at_8[0x18]; 12172 12173 u8 syndrome[0x20]; 12174 12175 u8 reserved_at_40[0x40]; 12176 }; 12177 12178 struct mlx5_ifc_umem_bits { 12179 u8 reserved_at_0[0x80]; 12180 12181 u8 ats[0x1]; 12182 u8 reserved_at_81[0x1a]; 12183 u8 log_page_size[0x5]; 12184 12185 u8 page_offset[0x20]; 12186 12187 u8 num_of_mtt[0x40]; 12188 12189 struct mlx5_ifc_mtt_bits mtt[]; 12190 }; 12191 12192 struct mlx5_ifc_uctx_bits { 12193 u8 cap[0x20]; 12194 12195 u8 reserved_at_20[0x160]; 12196 }; 12197 12198 struct mlx5_ifc_sw_icm_bits { 12199 u8 modify_field_select[0x40]; 12200 12201 u8 reserved_at_40[0x18]; 12202 u8 log_sw_icm_size[0x8]; 12203 12204 u8 reserved_at_60[0x20]; 12205 12206 u8 sw_icm_start_addr[0x40]; 12207 12208 u8 reserved_at_c0[0x140]; 12209 }; 12210 12211 struct mlx5_ifc_geneve_tlv_option_bits { 12212 u8 modify_field_select[0x40]; 12213 12214 u8 reserved_at_40[0x18]; 12215 u8 geneve_option_fte_index[0x8]; 12216 12217 u8 option_class[0x10]; 12218 u8 option_type[0x8]; 12219 u8 reserved_at_78[0x3]; 12220 u8 option_data_length[0x5]; 12221 12222 u8 reserved_at_80[0x180]; 12223 }; 12224 12225 struct mlx5_ifc_create_umem_in_bits { 12226 u8 opcode[0x10]; 12227 u8 uid[0x10]; 12228 12229 u8 reserved_at_20[0x10]; 12230 u8 op_mod[0x10]; 12231 12232 u8 reserved_at_40[0x40]; 12233 12234 struct mlx5_ifc_umem_bits umem; 12235 }; 12236 12237 struct mlx5_ifc_create_umem_out_bits { 12238 u8 status[0x8]; 12239 u8 reserved_at_8[0x18]; 12240 12241 u8 syndrome[0x20]; 12242 12243 u8 reserved_at_40[0x8]; 12244 u8 umem_id[0x18]; 12245 12246 u8 reserved_at_60[0x20]; 12247 }; 12248 12249 struct mlx5_ifc_destroy_umem_in_bits { 12250 u8 opcode[0x10]; 12251 u8 uid[0x10]; 12252 12253 u8 reserved_at_20[0x10]; 12254 u8 op_mod[0x10]; 12255 12256 u8 reserved_at_40[0x8]; 12257 u8 umem_id[0x18]; 12258 12259 u8 reserved_at_60[0x20]; 12260 }; 12261 12262 struct mlx5_ifc_destroy_umem_out_bits { 12263 u8 status[0x8]; 12264 u8 reserved_at_8[0x18]; 12265 12266 u8 syndrome[0x20]; 12267 12268 u8 reserved_at_40[0x40]; 12269 }; 12270 12271 struct mlx5_ifc_create_uctx_in_bits { 12272 u8 opcode[0x10]; 12273 u8 reserved_at_10[0x10]; 12274 12275 u8 reserved_at_20[0x10]; 12276 u8 op_mod[0x10]; 12277 12278 u8 reserved_at_40[0x40]; 12279 12280 struct mlx5_ifc_uctx_bits uctx; 12281 }; 12282 12283 struct mlx5_ifc_create_uctx_out_bits { 12284 u8 status[0x8]; 12285 u8 reserved_at_8[0x18]; 12286 12287 u8 syndrome[0x20]; 12288 12289 u8 reserved_at_40[0x10]; 12290 u8 uid[0x10]; 12291 12292 u8 reserved_at_60[0x20]; 12293 }; 12294 12295 struct mlx5_ifc_destroy_uctx_in_bits { 12296 u8 opcode[0x10]; 12297 u8 reserved_at_10[0x10]; 12298 12299 u8 reserved_at_20[0x10]; 12300 u8 op_mod[0x10]; 12301 12302 u8 reserved_at_40[0x10]; 12303 u8 uid[0x10]; 12304 12305 u8 reserved_at_60[0x20]; 12306 }; 12307 12308 struct mlx5_ifc_destroy_uctx_out_bits { 12309 u8 status[0x8]; 12310 u8 reserved_at_8[0x18]; 12311 12312 u8 syndrome[0x20]; 12313 12314 u8 reserved_at_40[0x40]; 12315 }; 12316 12317 struct mlx5_ifc_create_sw_icm_in_bits { 12318 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 12319 struct mlx5_ifc_sw_icm_bits sw_icm; 12320 }; 12321 12322 struct mlx5_ifc_create_geneve_tlv_option_in_bits { 12323 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 12324 struct mlx5_ifc_geneve_tlv_option_bits geneve_tlv_opt; 12325 }; 12326 12327 struct mlx5_ifc_mtrc_string_db_param_bits { 12328 u8 string_db_base_address[0x20]; 12329 12330 u8 reserved_at_20[0x8]; 12331 u8 string_db_size[0x18]; 12332 }; 12333 12334 struct mlx5_ifc_mtrc_cap_bits { 12335 u8 trace_owner[0x1]; 12336 u8 trace_to_memory[0x1]; 12337 u8 reserved_at_2[0x4]; 12338 u8 trc_ver[0x2]; 12339 u8 reserved_at_8[0x14]; 12340 u8 num_string_db[0x4]; 12341 12342 u8 first_string_trace[0x8]; 12343 u8 num_string_trace[0x8]; 12344 u8 reserved_at_30[0x28]; 12345 12346 u8 log_max_trace_buffer_size[0x8]; 12347 12348 u8 reserved_at_60[0x20]; 12349 12350 struct mlx5_ifc_mtrc_string_db_param_bits string_db_param[8]; 12351 12352 u8 reserved_at_280[0x180]; 12353 }; 12354 12355 struct mlx5_ifc_mtrc_conf_bits { 12356 u8 reserved_at_0[0x1c]; 12357 u8 trace_mode[0x4]; 12358 u8 reserved_at_20[0x18]; 12359 u8 log_trace_buffer_size[0x8]; 12360 u8 trace_mkey[0x20]; 12361 u8 reserved_at_60[0x3a0]; 12362 }; 12363 12364 struct mlx5_ifc_mtrc_stdb_bits { 12365 u8 string_db_index[0x4]; 12366 u8 reserved_at_4[0x4]; 12367 u8 read_size[0x18]; 12368 u8 start_offset[0x20]; 12369 u8 string_db_data[]; 12370 }; 12371 12372 struct mlx5_ifc_mtrc_ctrl_bits { 12373 u8 trace_status[0x2]; 12374 u8 reserved_at_2[0x2]; 12375 u8 arm_event[0x1]; 12376 u8 reserved_at_5[0xb]; 12377 u8 modify_field_select[0x10]; 12378 u8 reserved_at_20[0x2b]; 12379 u8 current_timestamp52_32[0x15]; 12380 u8 current_timestamp31_0[0x20]; 12381 u8 reserved_at_80[0x180]; 12382 }; 12383 12384 struct mlx5_ifc_host_params_context_bits { 12385 u8 host_number[0x8]; 12386 u8 reserved_at_8[0x5]; 12387 u8 host_pf_not_exist[0x1]; 12388 u8 reserved_at_14[0x1]; 12389 u8 host_pf_disabled[0x1]; 12390 u8 host_num_of_vfs[0x10]; 12391 12392 u8 host_total_vfs[0x10]; 12393 u8 host_pci_bus[0x10]; 12394 12395 u8 reserved_at_40[0x10]; 12396 u8 host_pci_device[0x10]; 12397 12398 u8 reserved_at_60[0x10]; 12399 u8 host_pci_function[0x10]; 12400 12401 u8 reserved_at_80[0x180]; 12402 }; 12403 12404 struct mlx5_ifc_query_esw_functions_in_bits { 12405 u8 opcode[0x10]; 12406 u8 reserved_at_10[0x10]; 12407 12408 u8 reserved_at_20[0x10]; 12409 u8 op_mod[0x10]; 12410 12411 u8 reserved_at_40[0x40]; 12412 }; 12413 12414 struct mlx5_ifc_query_esw_functions_out_bits { 12415 u8 status[0x8]; 12416 u8 reserved_at_8[0x18]; 12417 12418 u8 syndrome[0x20]; 12419 12420 u8 reserved_at_40[0x40]; 12421 12422 struct mlx5_ifc_host_params_context_bits host_params_context; 12423 12424 u8 reserved_at_280[0x180]; 12425 u8 host_sf_enable[][0x40]; 12426 }; 12427 12428 struct mlx5_ifc_sf_partition_bits { 12429 u8 reserved_at_0[0x10]; 12430 u8 log_num_sf[0x8]; 12431 u8 log_sf_bar_size[0x8]; 12432 }; 12433 12434 struct mlx5_ifc_query_sf_partitions_out_bits { 12435 u8 status[0x8]; 12436 u8 reserved_at_8[0x18]; 12437 12438 u8 syndrome[0x20]; 12439 12440 u8 reserved_at_40[0x18]; 12441 u8 num_sf_partitions[0x8]; 12442 12443 u8 reserved_at_60[0x20]; 12444 12445 struct mlx5_ifc_sf_partition_bits sf_partition[]; 12446 }; 12447 12448 struct mlx5_ifc_query_sf_partitions_in_bits { 12449 u8 opcode[0x10]; 12450 u8 reserved_at_10[0x10]; 12451 12452 u8 reserved_at_20[0x10]; 12453 u8 op_mod[0x10]; 12454 12455 u8 reserved_at_40[0x40]; 12456 }; 12457 12458 struct mlx5_ifc_dealloc_sf_out_bits { 12459 u8 status[0x8]; 12460 u8 reserved_at_8[0x18]; 12461 12462 u8 syndrome[0x20]; 12463 12464 u8 reserved_at_40[0x40]; 12465 }; 12466 12467 struct mlx5_ifc_dealloc_sf_in_bits { 12468 u8 opcode[0x10]; 12469 u8 reserved_at_10[0x10]; 12470 12471 u8 reserved_at_20[0x10]; 12472 u8 op_mod[0x10]; 12473 12474 u8 reserved_at_40[0x10]; 12475 u8 function_id[0x10]; 12476 12477 u8 reserved_at_60[0x20]; 12478 }; 12479 12480 struct mlx5_ifc_alloc_sf_out_bits { 12481 u8 status[0x8]; 12482 u8 reserved_at_8[0x18]; 12483 12484 u8 syndrome[0x20]; 12485 12486 u8 reserved_at_40[0x40]; 12487 }; 12488 12489 struct mlx5_ifc_alloc_sf_in_bits { 12490 u8 opcode[0x10]; 12491 u8 reserved_at_10[0x10]; 12492 12493 u8 reserved_at_20[0x10]; 12494 u8 op_mod[0x10]; 12495 12496 u8 reserved_at_40[0x10]; 12497 u8 function_id[0x10]; 12498 12499 u8 reserved_at_60[0x20]; 12500 }; 12501 12502 struct mlx5_ifc_affiliated_event_header_bits { 12503 u8 reserved_at_0[0x10]; 12504 u8 obj_type[0x10]; 12505 12506 u8 obj_id[0x20]; 12507 }; 12508 12509 enum { 12510 MLX5_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = 0xc, 12511 MLX5_GENERAL_OBJECT_TYPES_IPSEC = 0x13, 12512 MLX5_GENERAL_OBJECT_TYPES_SAMPLER = 0x20, 12513 MLX5_GENERAL_OBJECT_TYPES_FLOW_METER_ASO = 0x24, 12514 MLX5_GENERAL_OBJECT_TYPES_MACSEC = 0x27, 12515 MLX5_GENERAL_OBJECT_TYPES_INT_KEK = 0x47, 12516 MLX5_GENERAL_OBJECT_TYPES_RDMA_CTRL = 0x53, 12517 MLX5_GENERAL_OBJECT_TYPES_PCIE_CONG_EVENT = 0x58, 12518 MLX5_GENERAL_OBJECT_TYPES_FLOW_TABLE_ALIAS = 0xff15, 12519 }; 12520 12521 enum { 12522 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = 12523 BIT_ULL(MLX5_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY), 12524 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_IPSEC = 12525 BIT_ULL(MLX5_GENERAL_OBJECT_TYPES_IPSEC), 12526 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_SAMPLER = 12527 BIT_ULL(MLX5_GENERAL_OBJECT_TYPES_SAMPLER), 12528 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_FLOW_METER_ASO = 12529 BIT_ULL(MLX5_GENERAL_OBJECT_TYPES_FLOW_METER_ASO), 12530 }; 12531 12532 enum { 12533 MLX5_HCA_CAP_2_GENERAL_OBJECT_TYPES_RDMA_CTRL = 12534 BIT_ULL(MLX5_GENERAL_OBJECT_TYPES_RDMA_CTRL - 0x40), 12535 MLX5_HCA_CAP_2_GENERAL_OBJECT_TYPES_PCIE_CONG_EVENT = 12536 BIT_ULL(MLX5_GENERAL_OBJECT_TYPES_PCIE_CONG_EVENT - 0x40), 12537 }; 12538 12539 enum { 12540 MLX5_IPSEC_OBJECT_ICV_LEN_16B, 12541 }; 12542 12543 enum { 12544 MLX5_IPSEC_ASO_REG_C_0_1 = 0x0, 12545 MLX5_IPSEC_ASO_REG_C_2_3 = 0x1, 12546 MLX5_IPSEC_ASO_REG_C_4_5 = 0x2, 12547 MLX5_IPSEC_ASO_REG_C_6_7 = 0x3, 12548 }; 12549 12550 enum { 12551 MLX5_IPSEC_ASO_MODE = 0x0, 12552 MLX5_IPSEC_ASO_REPLAY_PROTECTION = 0x1, 12553 MLX5_IPSEC_ASO_INC_SN = 0x2, 12554 }; 12555 12556 enum { 12557 MLX5_IPSEC_ASO_REPLAY_WIN_32BIT = 0x0, 12558 MLX5_IPSEC_ASO_REPLAY_WIN_64BIT = 0x1, 12559 MLX5_IPSEC_ASO_REPLAY_WIN_128BIT = 0x2, 12560 MLX5_IPSEC_ASO_REPLAY_WIN_256BIT = 0x3, 12561 }; 12562 12563 struct mlx5_ifc_ipsec_aso_bits { 12564 u8 valid[0x1]; 12565 u8 reserved_at_201[0x1]; 12566 u8 mode[0x2]; 12567 u8 window_sz[0x2]; 12568 u8 soft_lft_arm[0x1]; 12569 u8 hard_lft_arm[0x1]; 12570 u8 remove_flow_enable[0x1]; 12571 u8 esn_event_arm[0x1]; 12572 u8 reserved_at_20a[0x16]; 12573 12574 u8 remove_flow_pkt_cnt[0x20]; 12575 12576 u8 remove_flow_soft_lft[0x20]; 12577 12578 u8 reserved_at_260[0x80]; 12579 12580 u8 mode_parameter[0x20]; 12581 12582 u8 replay_protection_window[0x100]; 12583 }; 12584 12585 struct mlx5_ifc_ipsec_obj_bits { 12586 u8 modify_field_select[0x40]; 12587 u8 full_offload[0x1]; 12588 u8 reserved_at_41[0x1]; 12589 u8 esn_en[0x1]; 12590 u8 esn_overlap[0x1]; 12591 u8 reserved_at_44[0x2]; 12592 u8 icv_length[0x2]; 12593 u8 reserved_at_48[0x4]; 12594 u8 aso_return_reg[0x4]; 12595 u8 reserved_at_50[0x10]; 12596 12597 u8 esn_msb[0x20]; 12598 12599 u8 reserved_at_80[0x8]; 12600 u8 dekn[0x18]; 12601 12602 u8 salt[0x20]; 12603 12604 u8 implicit_iv[0x40]; 12605 12606 u8 reserved_at_100[0x8]; 12607 u8 ipsec_aso_access_pd[0x18]; 12608 u8 reserved_at_120[0xe0]; 12609 12610 struct mlx5_ifc_ipsec_aso_bits ipsec_aso; 12611 }; 12612 12613 struct mlx5_ifc_create_ipsec_obj_in_bits { 12614 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12615 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 12616 }; 12617 12618 enum { 12619 MLX5_MODIFY_IPSEC_BITMASK_ESN_OVERLAP = BIT(0), 12620 MLX5_MODIFY_IPSEC_BITMASK_ESN_MSB = BIT(1), 12621 }; 12622 12623 struct mlx5_ifc_query_ipsec_obj_out_bits { 12624 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 12625 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 12626 }; 12627 12628 struct mlx5_ifc_modify_ipsec_obj_in_bits { 12629 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12630 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 12631 }; 12632 12633 enum { 12634 MLX5_MACSEC_ASO_REPLAY_PROTECTION = 0x1, 12635 }; 12636 12637 enum { 12638 MLX5_MACSEC_ASO_REPLAY_WIN_32BIT = 0x0, 12639 MLX5_MACSEC_ASO_REPLAY_WIN_64BIT = 0x1, 12640 MLX5_MACSEC_ASO_REPLAY_WIN_128BIT = 0x2, 12641 MLX5_MACSEC_ASO_REPLAY_WIN_256BIT = 0x3, 12642 }; 12643 12644 #define MLX5_MACSEC_ASO_INC_SN 0x2 12645 #define MLX5_MACSEC_ASO_REG_C_4_5 0x2 12646 12647 struct mlx5_ifc_macsec_aso_bits { 12648 u8 valid[0x1]; 12649 u8 reserved_at_1[0x1]; 12650 u8 mode[0x2]; 12651 u8 window_size[0x2]; 12652 u8 soft_lifetime_arm[0x1]; 12653 u8 hard_lifetime_arm[0x1]; 12654 u8 remove_flow_enable[0x1]; 12655 u8 epn_event_arm[0x1]; 12656 u8 reserved_at_a[0x16]; 12657 12658 u8 remove_flow_packet_count[0x20]; 12659 12660 u8 remove_flow_soft_lifetime[0x20]; 12661 12662 u8 reserved_at_60[0x80]; 12663 12664 u8 mode_parameter[0x20]; 12665 12666 u8 replay_protection_window[8][0x20]; 12667 }; 12668 12669 struct mlx5_ifc_macsec_offload_obj_bits { 12670 u8 modify_field_select[0x40]; 12671 12672 u8 confidentiality_en[0x1]; 12673 u8 reserved_at_41[0x1]; 12674 u8 epn_en[0x1]; 12675 u8 epn_overlap[0x1]; 12676 u8 reserved_at_44[0x2]; 12677 u8 confidentiality_offset[0x2]; 12678 u8 reserved_at_48[0x4]; 12679 u8 aso_return_reg[0x4]; 12680 u8 reserved_at_50[0x10]; 12681 12682 u8 epn_msb[0x20]; 12683 12684 u8 reserved_at_80[0x8]; 12685 u8 dekn[0x18]; 12686 12687 u8 reserved_at_a0[0x20]; 12688 12689 u8 sci[0x40]; 12690 12691 u8 reserved_at_100[0x8]; 12692 u8 macsec_aso_access_pd[0x18]; 12693 12694 u8 reserved_at_120[0x60]; 12695 12696 u8 salt[3][0x20]; 12697 12698 u8 reserved_at_1e0[0x20]; 12699 12700 struct mlx5_ifc_macsec_aso_bits macsec_aso; 12701 }; 12702 12703 struct mlx5_ifc_create_macsec_obj_in_bits { 12704 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12705 struct mlx5_ifc_macsec_offload_obj_bits macsec_object; 12706 }; 12707 12708 struct mlx5_ifc_modify_macsec_obj_in_bits { 12709 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12710 struct mlx5_ifc_macsec_offload_obj_bits macsec_object; 12711 }; 12712 12713 enum { 12714 MLX5_MODIFY_MACSEC_BITMASK_EPN_OVERLAP = BIT(0), 12715 MLX5_MODIFY_MACSEC_BITMASK_EPN_MSB = BIT(1), 12716 }; 12717 12718 struct mlx5_ifc_query_macsec_obj_out_bits { 12719 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 12720 struct mlx5_ifc_macsec_offload_obj_bits macsec_object; 12721 }; 12722 12723 struct mlx5_ifc_wrapped_dek_bits { 12724 u8 gcm_iv[0x60]; 12725 12726 u8 reserved_at_60[0x20]; 12727 12728 u8 const0[0x1]; 12729 u8 key_size[0x1]; 12730 u8 reserved_at_82[0x2]; 12731 u8 key2_invalid[0x1]; 12732 u8 reserved_at_85[0x3]; 12733 u8 pd[0x18]; 12734 12735 u8 key_purpose[0x5]; 12736 u8 reserved_at_a5[0x13]; 12737 u8 kek_id[0x8]; 12738 12739 u8 reserved_at_c0[0x40]; 12740 12741 u8 key1[0x8][0x20]; 12742 12743 u8 key2[0x8][0x20]; 12744 12745 u8 reserved_at_300[0x40]; 12746 12747 u8 const1[0x1]; 12748 u8 reserved_at_341[0x1f]; 12749 12750 u8 reserved_at_360[0x20]; 12751 12752 u8 auth_tag[0x80]; 12753 }; 12754 12755 struct mlx5_ifc_encryption_key_obj_bits { 12756 u8 modify_field_select[0x40]; 12757 12758 u8 state[0x8]; 12759 u8 sw_wrapped[0x1]; 12760 u8 reserved_at_49[0xb]; 12761 u8 key_size[0x4]; 12762 u8 reserved_at_58[0x4]; 12763 u8 key_purpose[0x4]; 12764 12765 u8 reserved_at_60[0x8]; 12766 u8 pd[0x18]; 12767 12768 u8 reserved_at_80[0x100]; 12769 12770 u8 opaque[0x40]; 12771 12772 u8 reserved_at_1c0[0x40]; 12773 12774 u8 key[8][0x80]; 12775 12776 u8 sw_wrapped_dek[8][0x80]; 12777 12778 u8 reserved_at_a00[0x600]; 12779 }; 12780 12781 struct mlx5_ifc_create_encryption_key_in_bits { 12782 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12783 struct mlx5_ifc_encryption_key_obj_bits encryption_key_object; 12784 }; 12785 12786 struct mlx5_ifc_modify_encryption_key_in_bits { 12787 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12788 struct mlx5_ifc_encryption_key_obj_bits encryption_key_object; 12789 }; 12790 12791 enum { 12792 MLX5_FLOW_METER_MODE_BYTES_IP_LENGTH = 0x0, 12793 MLX5_FLOW_METER_MODE_BYTES_CALC_WITH_L2 = 0x1, 12794 MLX5_FLOW_METER_MODE_BYTES_CALC_WITH_L2_IPG = 0x2, 12795 MLX5_FLOW_METER_MODE_NUM_PACKETS = 0x3, 12796 }; 12797 12798 struct mlx5_ifc_flow_meter_parameters_bits { 12799 u8 valid[0x1]; 12800 u8 bucket_overflow[0x1]; 12801 u8 start_color[0x2]; 12802 u8 both_buckets_on_green[0x1]; 12803 u8 reserved_at_5[0x1]; 12804 u8 meter_mode[0x2]; 12805 u8 reserved_at_8[0x18]; 12806 12807 u8 reserved_at_20[0x20]; 12808 12809 u8 reserved_at_40[0x3]; 12810 u8 cbs_exponent[0x5]; 12811 u8 cbs_mantissa[0x8]; 12812 u8 reserved_at_50[0x3]; 12813 u8 cir_exponent[0x5]; 12814 u8 cir_mantissa[0x8]; 12815 12816 u8 reserved_at_60[0x20]; 12817 12818 u8 reserved_at_80[0x3]; 12819 u8 ebs_exponent[0x5]; 12820 u8 ebs_mantissa[0x8]; 12821 u8 reserved_at_90[0x3]; 12822 u8 eir_exponent[0x5]; 12823 u8 eir_mantissa[0x8]; 12824 12825 u8 reserved_at_a0[0x60]; 12826 }; 12827 12828 struct mlx5_ifc_flow_meter_aso_obj_bits { 12829 u8 modify_field_select[0x40]; 12830 12831 u8 reserved_at_40[0x40]; 12832 12833 u8 reserved_at_80[0x8]; 12834 u8 meter_aso_access_pd[0x18]; 12835 12836 u8 reserved_at_a0[0x160]; 12837 12838 struct mlx5_ifc_flow_meter_parameters_bits flow_meter_parameters[2]; 12839 }; 12840 12841 struct mlx5_ifc_create_flow_meter_aso_obj_in_bits { 12842 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 12843 struct mlx5_ifc_flow_meter_aso_obj_bits flow_meter_aso_obj; 12844 }; 12845 12846 struct mlx5_ifc_int_kek_obj_bits { 12847 u8 modify_field_select[0x40]; 12848 12849 u8 state[0x8]; 12850 u8 auto_gen[0x1]; 12851 u8 reserved_at_49[0xb]; 12852 u8 key_size[0x4]; 12853 u8 reserved_at_58[0x8]; 12854 12855 u8 reserved_at_60[0x8]; 12856 u8 pd[0x18]; 12857 12858 u8 reserved_at_80[0x180]; 12859 u8 key[8][0x80]; 12860 12861 u8 reserved_at_600[0x200]; 12862 }; 12863 12864 struct mlx5_ifc_create_int_kek_obj_in_bits { 12865 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12866 struct mlx5_ifc_int_kek_obj_bits int_kek_object; 12867 }; 12868 12869 struct mlx5_ifc_create_int_kek_obj_out_bits { 12870 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 12871 struct mlx5_ifc_int_kek_obj_bits int_kek_object; 12872 }; 12873 12874 struct mlx5_ifc_sampler_obj_bits { 12875 u8 modify_field_select[0x40]; 12876 12877 u8 table_type[0x8]; 12878 u8 level[0x8]; 12879 u8 reserved_at_50[0xf]; 12880 u8 ignore_flow_level[0x1]; 12881 12882 u8 sample_ratio[0x20]; 12883 12884 u8 reserved_at_80[0x8]; 12885 u8 sample_table_id[0x18]; 12886 12887 u8 reserved_at_a0[0x8]; 12888 u8 default_table_id[0x18]; 12889 12890 u8 sw_steering_icm_address_rx[0x40]; 12891 u8 sw_steering_icm_address_tx[0x40]; 12892 12893 u8 reserved_at_140[0xa0]; 12894 }; 12895 12896 struct mlx5_ifc_create_sampler_obj_in_bits { 12897 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12898 struct mlx5_ifc_sampler_obj_bits sampler_object; 12899 }; 12900 12901 struct mlx5_ifc_query_sampler_obj_out_bits { 12902 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 12903 struct mlx5_ifc_sampler_obj_bits sampler_object; 12904 }; 12905 12906 enum { 12907 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_128 = 0x0, 12908 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_256 = 0x1, 12909 }; 12910 12911 enum { 12912 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_PURPOSE_TLS = 0x1, 12913 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_PURPOSE_IPSEC = 0x2, 12914 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_PURPOSE_MACSEC = 0x4, 12915 }; 12916 12917 struct mlx5_ifc_tls_static_params_bits { 12918 u8 const_2[0x2]; 12919 u8 tls_version[0x4]; 12920 u8 const_1[0x2]; 12921 u8 reserved_at_8[0x14]; 12922 u8 encryption_standard[0x4]; 12923 12924 u8 reserved_at_20[0x20]; 12925 12926 u8 initial_record_number[0x40]; 12927 12928 u8 resync_tcp_sn[0x20]; 12929 12930 u8 gcm_iv[0x20]; 12931 12932 u8 implicit_iv[0x40]; 12933 12934 u8 reserved_at_100[0x8]; 12935 u8 dek_index[0x18]; 12936 12937 u8 reserved_at_120[0xe0]; 12938 }; 12939 12940 struct mlx5_ifc_tls_progress_params_bits { 12941 u8 next_record_tcp_sn[0x20]; 12942 12943 u8 hw_resync_tcp_sn[0x20]; 12944 12945 u8 record_tracker_state[0x2]; 12946 u8 auth_state[0x2]; 12947 u8 reserved_at_44[0x4]; 12948 u8 hw_offset_record_number[0x18]; 12949 }; 12950 12951 enum { 12952 MLX5_MTT_PERM_READ = 1 << 0, 12953 MLX5_MTT_PERM_WRITE = 1 << 1, 12954 MLX5_MTT_PERM_RW = MLX5_MTT_PERM_READ | MLX5_MTT_PERM_WRITE, 12955 }; 12956 12957 enum { 12958 MLX5_SUSPEND_VHCA_IN_OP_MOD_SUSPEND_INITIATOR = 0x0, 12959 MLX5_SUSPEND_VHCA_IN_OP_MOD_SUSPEND_RESPONDER = 0x1, 12960 }; 12961 12962 struct mlx5_ifc_suspend_vhca_in_bits { 12963 u8 opcode[0x10]; 12964 u8 uid[0x10]; 12965 12966 u8 reserved_at_20[0x10]; 12967 u8 op_mod[0x10]; 12968 12969 u8 reserved_at_40[0x10]; 12970 u8 vhca_id[0x10]; 12971 12972 u8 reserved_at_60[0x20]; 12973 }; 12974 12975 struct mlx5_ifc_suspend_vhca_out_bits { 12976 u8 status[0x8]; 12977 u8 reserved_at_8[0x18]; 12978 12979 u8 syndrome[0x20]; 12980 12981 u8 reserved_at_40[0x40]; 12982 }; 12983 12984 enum { 12985 MLX5_RESUME_VHCA_IN_OP_MOD_RESUME_RESPONDER = 0x0, 12986 MLX5_RESUME_VHCA_IN_OP_MOD_RESUME_INITIATOR = 0x1, 12987 }; 12988 12989 struct mlx5_ifc_resume_vhca_in_bits { 12990 u8 opcode[0x10]; 12991 u8 uid[0x10]; 12992 12993 u8 reserved_at_20[0x10]; 12994 u8 op_mod[0x10]; 12995 12996 u8 reserved_at_40[0x10]; 12997 u8 vhca_id[0x10]; 12998 12999 u8 reserved_at_60[0x20]; 13000 }; 13001 13002 struct mlx5_ifc_resume_vhca_out_bits { 13003 u8 status[0x8]; 13004 u8 reserved_at_8[0x18]; 13005 13006 u8 syndrome[0x20]; 13007 13008 u8 reserved_at_40[0x40]; 13009 }; 13010 13011 struct mlx5_ifc_query_vhca_migration_state_in_bits { 13012 u8 opcode[0x10]; 13013 u8 uid[0x10]; 13014 13015 u8 reserved_at_20[0x10]; 13016 u8 op_mod[0x10]; 13017 13018 u8 incremental[0x1]; 13019 u8 chunk[0x1]; 13020 u8 reserved_at_42[0xe]; 13021 u8 vhca_id[0x10]; 13022 13023 u8 reserved_at_60[0x20]; 13024 }; 13025 13026 struct mlx5_ifc_query_vhca_migration_state_out_bits { 13027 u8 status[0x8]; 13028 u8 reserved_at_8[0x18]; 13029 13030 u8 syndrome[0x20]; 13031 13032 u8 reserved_at_40[0x40]; 13033 13034 u8 required_umem_size[0x20]; 13035 13036 u8 reserved_at_a0[0x20]; 13037 13038 u8 remaining_total_size[0x40]; 13039 13040 u8 reserved_at_100[0x100]; 13041 }; 13042 13043 struct mlx5_ifc_save_vhca_state_in_bits { 13044 u8 opcode[0x10]; 13045 u8 uid[0x10]; 13046 13047 u8 reserved_at_20[0x10]; 13048 u8 op_mod[0x10]; 13049 13050 u8 incremental[0x1]; 13051 u8 set_track[0x1]; 13052 u8 reserved_at_42[0xe]; 13053 u8 vhca_id[0x10]; 13054 13055 u8 reserved_at_60[0x20]; 13056 13057 u8 va[0x40]; 13058 13059 u8 mkey[0x20]; 13060 13061 u8 size[0x20]; 13062 }; 13063 13064 struct mlx5_ifc_save_vhca_state_out_bits { 13065 u8 status[0x8]; 13066 u8 reserved_at_8[0x18]; 13067 13068 u8 syndrome[0x20]; 13069 13070 u8 actual_image_size[0x20]; 13071 13072 u8 next_required_umem_size[0x20]; 13073 }; 13074 13075 struct mlx5_ifc_load_vhca_state_in_bits { 13076 u8 opcode[0x10]; 13077 u8 uid[0x10]; 13078 13079 u8 reserved_at_20[0x10]; 13080 u8 op_mod[0x10]; 13081 13082 u8 reserved_at_40[0x10]; 13083 u8 vhca_id[0x10]; 13084 13085 u8 reserved_at_60[0x20]; 13086 13087 u8 va[0x40]; 13088 13089 u8 mkey[0x20]; 13090 13091 u8 size[0x20]; 13092 }; 13093 13094 struct mlx5_ifc_load_vhca_state_out_bits { 13095 u8 status[0x8]; 13096 u8 reserved_at_8[0x18]; 13097 13098 u8 syndrome[0x20]; 13099 13100 u8 reserved_at_40[0x40]; 13101 }; 13102 13103 struct mlx5_ifc_adv_rdma_cap_bits { 13104 u8 rdma_transport_manager[0x1]; 13105 u8 rdma_transport_manager_other_eswitch[0x1]; 13106 u8 reserved_at_2[0x1e]; 13107 13108 u8 rcx_type[0x8]; 13109 u8 reserved_at_28[0x2]; 13110 u8 ps_entry_log_max_value[0x6]; 13111 u8 reserved_at_30[0x6]; 13112 u8 qp_max_ps_num_entry[0xa]; 13113 13114 u8 mp_max_num_queues[0x8]; 13115 u8 ps_user_context_max_log_size[0x8]; 13116 u8 message_based_qp_and_striding_wq[0x8]; 13117 u8 reserved_at_58[0x8]; 13118 13119 u8 max_receive_send_message_size_stride[0x10]; 13120 u8 reserved_at_70[0x10]; 13121 13122 u8 max_receive_send_message_size_byte[0x20]; 13123 13124 u8 reserved_at_a0[0x160]; 13125 13126 struct mlx5_ifc_flow_table_prop_layout_bits rdma_transport_rx_flow_table_properties; 13127 13128 struct mlx5_ifc_flow_table_prop_layout_bits rdma_transport_tx_flow_table_properties; 13129 13130 struct mlx5_ifc_flow_table_fields_supported_2_bits rdma_transport_rx_ft_field_support_2; 13131 13132 struct mlx5_ifc_flow_table_fields_supported_2_bits rdma_transport_tx_ft_field_support_2; 13133 13134 struct mlx5_ifc_flow_table_fields_supported_2_bits rdma_transport_rx_ft_field_bitmask_support_2; 13135 13136 struct mlx5_ifc_flow_table_fields_supported_2_bits rdma_transport_tx_ft_field_bitmask_support_2; 13137 13138 u8 reserved_at_800[0x3800]; 13139 }; 13140 13141 struct mlx5_ifc_adv_virtualization_cap_bits { 13142 u8 reserved_at_0[0x3]; 13143 u8 pg_track_log_max_num[0x5]; 13144 u8 pg_track_max_num_range[0x8]; 13145 u8 pg_track_log_min_addr_space[0x8]; 13146 u8 pg_track_log_max_addr_space[0x8]; 13147 13148 u8 reserved_at_20[0x3]; 13149 u8 pg_track_log_min_msg_size[0x5]; 13150 u8 reserved_at_28[0x3]; 13151 u8 pg_track_log_max_msg_size[0x5]; 13152 u8 reserved_at_30[0x3]; 13153 u8 pg_track_log_min_page_size[0x5]; 13154 u8 reserved_at_38[0x3]; 13155 u8 pg_track_log_max_page_size[0x5]; 13156 13157 u8 reserved_at_40[0x7c0]; 13158 }; 13159 13160 struct mlx5_ifc_page_track_report_entry_bits { 13161 u8 dirty_address_high[0x20]; 13162 13163 u8 dirty_address_low[0x20]; 13164 }; 13165 13166 enum { 13167 MLX5_PAGE_TRACK_STATE_TRACKING, 13168 MLX5_PAGE_TRACK_STATE_REPORTING, 13169 MLX5_PAGE_TRACK_STATE_ERROR, 13170 }; 13171 13172 struct mlx5_ifc_page_track_range_bits { 13173 u8 start_address[0x40]; 13174 13175 u8 length[0x40]; 13176 }; 13177 13178 struct mlx5_ifc_page_track_bits { 13179 u8 modify_field_select[0x40]; 13180 13181 u8 reserved_at_40[0x10]; 13182 u8 vhca_id[0x10]; 13183 13184 u8 reserved_at_60[0x20]; 13185 13186 u8 state[0x4]; 13187 u8 track_type[0x4]; 13188 u8 log_addr_space_size[0x8]; 13189 u8 reserved_at_90[0x3]; 13190 u8 log_page_size[0x5]; 13191 u8 reserved_at_98[0x3]; 13192 u8 log_msg_size[0x5]; 13193 13194 u8 reserved_at_a0[0x8]; 13195 u8 reporting_qpn[0x18]; 13196 13197 u8 reserved_at_c0[0x18]; 13198 u8 num_ranges[0x8]; 13199 13200 u8 reserved_at_e0[0x20]; 13201 13202 u8 range_start_address[0x40]; 13203 13204 u8 length[0x40]; 13205 13206 struct mlx5_ifc_page_track_range_bits track_range[0]; 13207 }; 13208 13209 struct mlx5_ifc_create_page_track_obj_in_bits { 13210 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 13211 struct mlx5_ifc_page_track_bits obj_context; 13212 }; 13213 13214 struct mlx5_ifc_modify_page_track_obj_in_bits { 13215 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 13216 struct mlx5_ifc_page_track_bits obj_context; 13217 }; 13218 13219 struct mlx5_ifc_query_page_track_obj_out_bits { 13220 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 13221 struct mlx5_ifc_page_track_bits obj_context; 13222 }; 13223 13224 struct mlx5_ifc_msecq_reg_bits { 13225 u8 reserved_at_0[0x20]; 13226 13227 u8 reserved_at_20[0x12]; 13228 u8 network_option[0x2]; 13229 u8 local_ssm_code[0x4]; 13230 u8 local_enhanced_ssm_code[0x8]; 13231 13232 u8 local_clock_identity[0x40]; 13233 13234 u8 reserved_at_80[0x180]; 13235 }; 13236 13237 enum { 13238 MLX5_MSEES_FIELD_SELECT_ENABLE = BIT(0), 13239 MLX5_MSEES_FIELD_SELECT_ADMIN_STATUS = BIT(1), 13240 MLX5_MSEES_FIELD_SELECT_ADMIN_FREQ_MEASURE = BIT(2), 13241 }; 13242 13243 enum mlx5_msees_admin_status { 13244 MLX5_MSEES_ADMIN_STATUS_FREE_RUNNING = 0x0, 13245 MLX5_MSEES_ADMIN_STATUS_TRACK = 0x1, 13246 }; 13247 13248 enum mlx5_msees_oper_status { 13249 MLX5_MSEES_OPER_STATUS_FREE_RUNNING = 0x0, 13250 MLX5_MSEES_OPER_STATUS_SELF_TRACK = 0x1, 13251 MLX5_MSEES_OPER_STATUS_OTHER_TRACK = 0x2, 13252 MLX5_MSEES_OPER_STATUS_HOLDOVER = 0x3, 13253 MLX5_MSEES_OPER_STATUS_FAIL_HOLDOVER = 0x4, 13254 MLX5_MSEES_OPER_STATUS_FAIL_FREE_RUNNING = 0x5, 13255 }; 13256 13257 enum mlx5_msees_failure_reason { 13258 MLX5_MSEES_FAILURE_REASON_UNDEFINED_ERROR = 0x0, 13259 MLX5_MSEES_FAILURE_REASON_PORT_DOWN = 0x1, 13260 MLX5_MSEES_FAILURE_REASON_TOO_HIGH_FREQUENCY_DIFF = 0x2, 13261 MLX5_MSEES_FAILURE_REASON_NET_SYNCHRONIZER_DEVICE_ERROR = 0x3, 13262 MLX5_MSEES_FAILURE_REASON_LACK_OF_RESOURCES = 0x4, 13263 }; 13264 13265 struct mlx5_ifc_msees_reg_bits { 13266 u8 reserved_at_0[0x8]; 13267 u8 local_port[0x8]; 13268 u8 pnat[0x2]; 13269 u8 lp_msb[0x2]; 13270 u8 reserved_at_14[0xc]; 13271 13272 u8 field_select[0x20]; 13273 13274 u8 admin_status[0x4]; 13275 u8 oper_status[0x4]; 13276 u8 ho_acq[0x1]; 13277 u8 reserved_at_49[0xc]; 13278 u8 admin_freq_measure[0x1]; 13279 u8 oper_freq_measure[0x1]; 13280 u8 failure_reason[0x9]; 13281 13282 u8 frequency_diff[0x20]; 13283 13284 u8 reserved_at_80[0x180]; 13285 }; 13286 13287 struct mlx5_ifc_mrtcq_reg_bits { 13288 u8 reserved_at_0[0x40]; 13289 13290 u8 rt_clock_identity[0x40]; 13291 13292 u8 reserved_at_80[0x180]; 13293 }; 13294 13295 struct mlx5_ifc_pcie_cong_event_obj_bits { 13296 u8 modify_select_field[0x40]; 13297 13298 u8 inbound_event_en[0x1]; 13299 u8 outbound_event_en[0x1]; 13300 u8 reserved_at_42[0x1e]; 13301 13302 u8 reserved_at_60[0x1]; 13303 u8 inbound_cong_state[0x3]; 13304 u8 reserved_at_64[0x1]; 13305 u8 outbound_cong_state[0x3]; 13306 u8 reserved_at_68[0x18]; 13307 13308 u8 inbound_cong_low_threshold[0x10]; 13309 u8 inbound_cong_high_threshold[0x10]; 13310 13311 u8 outbound_cong_low_threshold[0x10]; 13312 u8 outbound_cong_high_threshold[0x10]; 13313 13314 u8 reserved_at_e0[0x340]; 13315 }; 13316 13317 struct mlx5_ifc_pcie_cong_event_cmd_in_bits { 13318 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 13319 struct mlx5_ifc_pcie_cong_event_obj_bits cong_obj; 13320 }; 13321 13322 struct mlx5_ifc_pcie_cong_event_cmd_out_bits { 13323 struct mlx5_ifc_general_obj_out_cmd_hdr_bits hdr; 13324 struct mlx5_ifc_pcie_cong_event_obj_bits cong_obj; 13325 }; 13326 13327 enum mlx5e_pcie_cong_event_mod_field { 13328 MLX5_PCIE_CONG_EVENT_MOD_EVENT_EN = BIT(0), 13329 MLX5_PCIE_CONG_EVENT_MOD_THRESH = BIT(2), 13330 }; 13331 13332 #endif /* MLX5_IFC_H */ 13333