xref: /linux/include/linux/mlx5/mlx5_ifc.h (revision a7ddedc84c59a645ef970b992f7cda5bffc70cc0) 
1 /*
2  * Copyright (c) 2013-2015, Mellanox Technologies, Ltd.  All rights reserved.
3  *
4  * This software is available to you under a choice of one of two
5  * licenses.  You may choose to be licensed under the terms of the GNU
6  * General Public License (GPL) Version 2, available from the file
7  * COPYING in the main directory of this source tree, or the
8  * OpenIB.org BSD license below:
9  *
10  *     Redistribution and use in source and binary forms, with or
11  *     without modification, are permitted provided that the following
12  *     conditions are met:
13  *
14  *      - Redistributions of source code must retain the above
15  *        copyright notice, this list of conditions and the following
16  *        disclaimer.
17  *
18  *      - Redistributions in binary form must reproduce the above
19  *        copyright notice, this list of conditions and the following
20  *        disclaimer in the documentation and/or other materials
21  *        provided with the distribution.
22  *
23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30  * SOFTWARE.
31 */
32 #ifndef MLX5_IFC_H
33 #define MLX5_IFC_H
34 
35 #include "mlx5_ifc_fpga.h"
36 
37 enum {
38 	MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS                   = 0x0,
39 	MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED             = 0x1,
40 	MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED           = 0x2,
41 	MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED                  = 0x3,
42 	MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED                    = 0x13,
43 	MLX5_EVENT_TYPE_CODING_SRQ_LIMIT                           = 0x14,
44 	MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED          = 0x1c,
45 	MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION            = 0x1d,
46 	MLX5_EVENT_TYPE_CODING_CQ_ERROR                            = 0x4,
47 	MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR         = 0x5,
48 	MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED               = 0x7,
49 	MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT                    = 0xc,
50 	MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR      = 0x10,
51 	MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR     = 0x11,
52 	MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR        = 0x12,
53 	MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR                      = 0x8,
54 	MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE                   = 0x9,
55 	MLX5_EVENT_TYPE_CODING_GPIO_EVENT                          = 0x15,
56 	MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19,
57 	MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a,
58 	MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT                      = 0x1b,
59 	MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT         = 0x1f,
60 	MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION        = 0xa,
61 	MLX5_EVENT_TYPE_CODING_PAGE_REQUEST                        = 0xb,
62 	MLX5_EVENT_TYPE_CODING_FPGA_ERROR                          = 0x20,
63 	MLX5_EVENT_TYPE_CODING_FPGA_QP_ERROR                       = 0x21
64 };
65 
66 enum {
67 	MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE        = 0x0,
68 	MLX5_SET_HCA_CAP_OP_MOD_ETHERNET_OFFLOADS     = 0x1,
69 	MLX5_SET_HCA_CAP_OP_MOD_ODP                   = 0x2,
70 	MLX5_SET_HCA_CAP_OP_MOD_ATOMIC                = 0x3,
71 	MLX5_SET_HCA_CAP_OP_MOD_ROCE                  = 0x4,
72 	MLX5_SET_HCA_CAP_OP_MOD_IPSEC                 = 0x15,
73 	MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE2       = 0x20,
74 	MLX5_SET_HCA_CAP_OP_MOD_PORT_SELECTION        = 0x25,
75 };
76 
77 enum {
78 	MLX5_SHARED_RESOURCE_UID = 0xffff,
79 };
80 
81 enum {
82 	MLX5_OBJ_TYPE_SW_ICM = 0x0008,
83 	MLX5_OBJ_TYPE_GENEVE_TLV_OPT = 0x000b,
84 	MLX5_OBJ_TYPE_VIRTIO_NET_Q = 0x000d,
85 	MLX5_OBJ_TYPE_VIRTIO_Q_COUNTERS = 0x001c,
86 	MLX5_OBJ_TYPE_MATCH_DEFINER = 0x0018,
87 	MLX5_OBJ_TYPE_HEADER_MODIFY_ARGUMENT  = 0x23,
88 	MLX5_OBJ_TYPE_STC = 0x0040,
89 	MLX5_OBJ_TYPE_RTC = 0x0041,
90 	MLX5_OBJ_TYPE_STE = 0x0042,
91 	MLX5_OBJ_TYPE_MODIFY_HDR_PATTERN = 0x0043,
92 	MLX5_OBJ_TYPE_PAGE_TRACK = 0x46,
93 	MLX5_OBJ_TYPE_MKEY = 0xff01,
94 	MLX5_OBJ_TYPE_QP = 0xff02,
95 	MLX5_OBJ_TYPE_PSV = 0xff03,
96 	MLX5_OBJ_TYPE_RMP = 0xff04,
97 	MLX5_OBJ_TYPE_XRC_SRQ = 0xff05,
98 	MLX5_OBJ_TYPE_RQ = 0xff06,
99 	MLX5_OBJ_TYPE_SQ = 0xff07,
100 	MLX5_OBJ_TYPE_TIR = 0xff08,
101 	MLX5_OBJ_TYPE_TIS = 0xff09,
102 	MLX5_OBJ_TYPE_DCT = 0xff0a,
103 	MLX5_OBJ_TYPE_XRQ = 0xff0b,
104 	MLX5_OBJ_TYPE_RQT = 0xff0e,
105 	MLX5_OBJ_TYPE_FLOW_COUNTER = 0xff0f,
106 	MLX5_OBJ_TYPE_CQ = 0xff10,
107 	MLX5_OBJ_TYPE_FT_ALIAS = 0xff15,
108 };
109 
110 enum {
111 	MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM = (1ULL << MLX5_OBJ_TYPE_SW_ICM),
112 	MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT = (1ULL << 11),
113 	MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q = (1ULL << 13),
114 	MLX5_GENERAL_OBJ_TYPES_CAP_HEADER_MODIFY_ARGUMENT =
115 		(1ULL << MLX5_OBJ_TYPE_HEADER_MODIFY_ARGUMENT),
116 	MLX5_GENERAL_OBJ_TYPES_CAP_MACSEC_OFFLOAD = (1ULL << 39),
117 };
118 
119 enum {
120 	MLX5_CMD_OP_QUERY_HCA_CAP                 = 0x100,
121 	MLX5_CMD_OP_QUERY_ADAPTER                 = 0x101,
122 	MLX5_CMD_OP_INIT_HCA                      = 0x102,
123 	MLX5_CMD_OP_TEARDOWN_HCA                  = 0x103,
124 	MLX5_CMD_OP_ENABLE_HCA                    = 0x104,
125 	MLX5_CMD_OP_DISABLE_HCA                   = 0x105,
126 	MLX5_CMD_OP_QUERY_PAGES                   = 0x107,
127 	MLX5_CMD_OP_MANAGE_PAGES                  = 0x108,
128 	MLX5_CMD_OP_SET_HCA_CAP                   = 0x109,
129 	MLX5_CMD_OP_QUERY_ISSI                    = 0x10a,
130 	MLX5_CMD_OP_SET_ISSI                      = 0x10b,
131 	MLX5_CMD_OP_SET_DRIVER_VERSION            = 0x10d,
132 	MLX5_CMD_OP_QUERY_SF_PARTITION            = 0x111,
133 	MLX5_CMD_OP_ALLOC_SF                      = 0x113,
134 	MLX5_CMD_OP_DEALLOC_SF                    = 0x114,
135 	MLX5_CMD_OP_SUSPEND_VHCA                  = 0x115,
136 	MLX5_CMD_OP_RESUME_VHCA                   = 0x116,
137 	MLX5_CMD_OP_QUERY_VHCA_MIGRATION_STATE    = 0x117,
138 	MLX5_CMD_OP_SAVE_VHCA_STATE               = 0x118,
139 	MLX5_CMD_OP_LOAD_VHCA_STATE               = 0x119,
140 	MLX5_CMD_OP_CREATE_MKEY                   = 0x200,
141 	MLX5_CMD_OP_QUERY_MKEY                    = 0x201,
142 	MLX5_CMD_OP_DESTROY_MKEY                  = 0x202,
143 	MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS        = 0x203,
144 	MLX5_CMD_OP_PAGE_FAULT_RESUME             = 0x204,
145 	MLX5_CMD_OP_ALLOC_MEMIC                   = 0x205,
146 	MLX5_CMD_OP_DEALLOC_MEMIC                 = 0x206,
147 	MLX5_CMD_OP_MODIFY_MEMIC                  = 0x207,
148 	MLX5_CMD_OP_CREATE_EQ                     = 0x301,
149 	MLX5_CMD_OP_DESTROY_EQ                    = 0x302,
150 	MLX5_CMD_OP_QUERY_EQ                      = 0x303,
151 	MLX5_CMD_OP_GEN_EQE                       = 0x304,
152 	MLX5_CMD_OP_CREATE_CQ                     = 0x400,
153 	MLX5_CMD_OP_DESTROY_CQ                    = 0x401,
154 	MLX5_CMD_OP_QUERY_CQ                      = 0x402,
155 	MLX5_CMD_OP_MODIFY_CQ                     = 0x403,
156 	MLX5_CMD_OP_CREATE_QP                     = 0x500,
157 	MLX5_CMD_OP_DESTROY_QP                    = 0x501,
158 	MLX5_CMD_OP_RST2INIT_QP                   = 0x502,
159 	MLX5_CMD_OP_INIT2RTR_QP                   = 0x503,
160 	MLX5_CMD_OP_RTR2RTS_QP                    = 0x504,
161 	MLX5_CMD_OP_RTS2RTS_QP                    = 0x505,
162 	MLX5_CMD_OP_SQERR2RTS_QP                  = 0x506,
163 	MLX5_CMD_OP_2ERR_QP                       = 0x507,
164 	MLX5_CMD_OP_2RST_QP                       = 0x50a,
165 	MLX5_CMD_OP_QUERY_QP                      = 0x50b,
166 	MLX5_CMD_OP_SQD_RTS_QP                    = 0x50c,
167 	MLX5_CMD_OP_INIT2INIT_QP                  = 0x50e,
168 	MLX5_CMD_OP_CREATE_PSV                    = 0x600,
169 	MLX5_CMD_OP_DESTROY_PSV                   = 0x601,
170 	MLX5_CMD_OP_CREATE_SRQ                    = 0x700,
171 	MLX5_CMD_OP_DESTROY_SRQ                   = 0x701,
172 	MLX5_CMD_OP_QUERY_SRQ                     = 0x702,
173 	MLX5_CMD_OP_ARM_RQ                        = 0x703,
174 	MLX5_CMD_OP_CREATE_XRC_SRQ                = 0x705,
175 	MLX5_CMD_OP_DESTROY_XRC_SRQ               = 0x706,
176 	MLX5_CMD_OP_QUERY_XRC_SRQ                 = 0x707,
177 	MLX5_CMD_OP_ARM_XRC_SRQ                   = 0x708,
178 	MLX5_CMD_OP_CREATE_DCT                    = 0x710,
179 	MLX5_CMD_OP_DESTROY_DCT                   = 0x711,
180 	MLX5_CMD_OP_DRAIN_DCT                     = 0x712,
181 	MLX5_CMD_OP_QUERY_DCT                     = 0x713,
182 	MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION     = 0x714,
183 	MLX5_CMD_OP_CREATE_XRQ                    = 0x717,
184 	MLX5_CMD_OP_DESTROY_XRQ                   = 0x718,
185 	MLX5_CMD_OP_QUERY_XRQ                     = 0x719,
186 	MLX5_CMD_OP_ARM_XRQ                       = 0x71a,
187 	MLX5_CMD_OP_QUERY_XRQ_DC_PARAMS_ENTRY     = 0x725,
188 	MLX5_CMD_OP_SET_XRQ_DC_PARAMS_ENTRY       = 0x726,
189 	MLX5_CMD_OP_QUERY_XRQ_ERROR_PARAMS        = 0x727,
190 	MLX5_CMD_OP_RELEASE_XRQ_ERROR             = 0x729,
191 	MLX5_CMD_OP_MODIFY_XRQ                    = 0x72a,
192 	MLX5_CMD_OPCODE_QUERY_DELEGATED_VHCA      = 0x732,
193 	MLX5_CMD_OPCODE_CREATE_ESW_VPORT          = 0x733,
194 	MLX5_CMD_OPCODE_DESTROY_ESW_VPORT         = 0x734,
195 	MLX5_CMD_OP_QUERY_ESW_FUNCTIONS           = 0x740,
196 	MLX5_CMD_OP_QUERY_VPORT_STATE             = 0x750,
197 	MLX5_CMD_OP_MODIFY_VPORT_STATE            = 0x751,
198 	MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT       = 0x752,
199 	MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT      = 0x753,
200 	MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT       = 0x754,
201 	MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT      = 0x755,
202 	MLX5_CMD_OP_QUERY_ROCE_ADDRESS            = 0x760,
203 	MLX5_CMD_OP_SET_ROCE_ADDRESS              = 0x761,
204 	MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT       = 0x762,
205 	MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT      = 0x763,
206 	MLX5_CMD_OP_QUERY_HCA_VPORT_GID           = 0x764,
207 	MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY          = 0x765,
208 	MLX5_CMD_OP_QUERY_VNIC_ENV                = 0x76f,
209 	MLX5_CMD_OP_QUERY_VPORT_COUNTER           = 0x770,
210 	MLX5_CMD_OP_ALLOC_Q_COUNTER               = 0x771,
211 	MLX5_CMD_OP_DEALLOC_Q_COUNTER             = 0x772,
212 	MLX5_CMD_OP_QUERY_Q_COUNTER               = 0x773,
213 	MLX5_CMD_OP_SET_MONITOR_COUNTER           = 0x774,
214 	MLX5_CMD_OP_ARM_MONITOR_COUNTER           = 0x775,
215 	MLX5_CMD_OP_SET_PP_RATE_LIMIT             = 0x780,
216 	MLX5_CMD_OP_QUERY_RATE_LIMIT              = 0x781,
217 	MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT      = 0x782,
218 	MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT     = 0x783,
219 	MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT       = 0x784,
220 	MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT      = 0x785,
221 	MLX5_CMD_OP_CREATE_QOS_PARA_VPORT         = 0x786,
222 	MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT        = 0x787,
223 	MLX5_CMD_OP_ALLOC_PD                      = 0x800,
224 	MLX5_CMD_OP_DEALLOC_PD                    = 0x801,
225 	MLX5_CMD_OP_ALLOC_UAR                     = 0x802,
226 	MLX5_CMD_OP_DEALLOC_UAR                   = 0x803,
227 	MLX5_CMD_OP_CONFIG_INT_MODERATION         = 0x804,
228 	MLX5_CMD_OP_ACCESS_REG                    = 0x805,
229 	MLX5_CMD_OP_ATTACH_TO_MCG                 = 0x806,
230 	MLX5_CMD_OP_DETACH_FROM_MCG               = 0x807,
231 	MLX5_CMD_OP_GET_DROPPED_PACKET_LOG        = 0x80a,
232 	MLX5_CMD_OP_MAD_IFC                       = 0x50d,
233 	MLX5_CMD_OP_QUERY_MAD_DEMUX               = 0x80b,
234 	MLX5_CMD_OP_SET_MAD_DEMUX                 = 0x80c,
235 	MLX5_CMD_OP_NOP                           = 0x80d,
236 	MLX5_CMD_OP_ALLOC_XRCD                    = 0x80e,
237 	MLX5_CMD_OP_DEALLOC_XRCD                  = 0x80f,
238 	MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN        = 0x816,
239 	MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN      = 0x817,
240 	MLX5_CMD_OP_QUERY_CONG_STATUS             = 0x822,
241 	MLX5_CMD_OP_MODIFY_CONG_STATUS            = 0x823,
242 	MLX5_CMD_OP_QUERY_CONG_PARAMS             = 0x824,
243 	MLX5_CMD_OP_MODIFY_CONG_PARAMS            = 0x825,
244 	MLX5_CMD_OP_QUERY_CONG_STATISTICS         = 0x826,
245 	MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT           = 0x827,
246 	MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT        = 0x828,
247 	MLX5_CMD_OP_SET_L2_TABLE_ENTRY            = 0x829,
248 	MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY          = 0x82a,
249 	MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY         = 0x82b,
250 	MLX5_CMD_OP_SET_WOL_ROL                   = 0x830,
251 	MLX5_CMD_OP_QUERY_WOL_ROL                 = 0x831,
252 	MLX5_CMD_OP_CREATE_LAG                    = 0x840,
253 	MLX5_CMD_OP_MODIFY_LAG                    = 0x841,
254 	MLX5_CMD_OP_QUERY_LAG                     = 0x842,
255 	MLX5_CMD_OP_DESTROY_LAG                   = 0x843,
256 	MLX5_CMD_OP_CREATE_VPORT_LAG              = 0x844,
257 	MLX5_CMD_OP_DESTROY_VPORT_LAG             = 0x845,
258 	MLX5_CMD_OP_CREATE_TIR                    = 0x900,
259 	MLX5_CMD_OP_MODIFY_TIR                    = 0x901,
260 	MLX5_CMD_OP_DESTROY_TIR                   = 0x902,
261 	MLX5_CMD_OP_QUERY_TIR                     = 0x903,
262 	MLX5_CMD_OP_CREATE_SQ                     = 0x904,
263 	MLX5_CMD_OP_MODIFY_SQ                     = 0x905,
264 	MLX5_CMD_OP_DESTROY_SQ                    = 0x906,
265 	MLX5_CMD_OP_QUERY_SQ                      = 0x907,
266 	MLX5_CMD_OP_CREATE_RQ                     = 0x908,
267 	MLX5_CMD_OP_MODIFY_RQ                     = 0x909,
268 	MLX5_CMD_OP_SET_DELAY_DROP_PARAMS         = 0x910,
269 	MLX5_CMD_OP_DESTROY_RQ                    = 0x90a,
270 	MLX5_CMD_OP_QUERY_RQ                      = 0x90b,
271 	MLX5_CMD_OP_CREATE_RMP                    = 0x90c,
272 	MLX5_CMD_OP_MODIFY_RMP                    = 0x90d,
273 	MLX5_CMD_OP_DESTROY_RMP                   = 0x90e,
274 	MLX5_CMD_OP_QUERY_RMP                     = 0x90f,
275 	MLX5_CMD_OP_CREATE_TIS                    = 0x912,
276 	MLX5_CMD_OP_MODIFY_TIS                    = 0x913,
277 	MLX5_CMD_OP_DESTROY_TIS                   = 0x914,
278 	MLX5_CMD_OP_QUERY_TIS                     = 0x915,
279 	MLX5_CMD_OP_CREATE_RQT                    = 0x916,
280 	MLX5_CMD_OP_MODIFY_RQT                    = 0x917,
281 	MLX5_CMD_OP_DESTROY_RQT                   = 0x918,
282 	MLX5_CMD_OP_QUERY_RQT                     = 0x919,
283 	MLX5_CMD_OP_SET_FLOW_TABLE_ROOT		  = 0x92f,
284 	MLX5_CMD_OP_CREATE_FLOW_TABLE             = 0x930,
285 	MLX5_CMD_OP_DESTROY_FLOW_TABLE            = 0x931,
286 	MLX5_CMD_OP_QUERY_FLOW_TABLE              = 0x932,
287 	MLX5_CMD_OP_CREATE_FLOW_GROUP             = 0x933,
288 	MLX5_CMD_OP_DESTROY_FLOW_GROUP            = 0x934,
289 	MLX5_CMD_OP_QUERY_FLOW_GROUP              = 0x935,
290 	MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY          = 0x936,
291 	MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY        = 0x937,
292 	MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY       = 0x938,
293 	MLX5_CMD_OP_ALLOC_FLOW_COUNTER            = 0x939,
294 	MLX5_CMD_OP_DEALLOC_FLOW_COUNTER          = 0x93a,
295 	MLX5_CMD_OP_QUERY_FLOW_COUNTER            = 0x93b,
296 	MLX5_CMD_OP_MODIFY_FLOW_TABLE             = 0x93c,
297 	MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT = 0x93d,
298 	MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT = 0x93e,
299 	MLX5_CMD_OP_QUERY_PACKET_REFORMAT_CONTEXT = 0x93f,
300 	MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT   = 0x940,
301 	MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941,
302 	MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT   = 0x942,
303 	MLX5_CMD_OP_FPGA_CREATE_QP                = 0x960,
304 	MLX5_CMD_OP_FPGA_MODIFY_QP                = 0x961,
305 	MLX5_CMD_OP_FPGA_QUERY_QP                 = 0x962,
306 	MLX5_CMD_OP_FPGA_DESTROY_QP               = 0x963,
307 	MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS        = 0x964,
308 	MLX5_CMD_OP_CREATE_GENERAL_OBJECT         = 0xa00,
309 	MLX5_CMD_OP_MODIFY_GENERAL_OBJECT         = 0xa01,
310 	MLX5_CMD_OP_QUERY_GENERAL_OBJECT          = 0xa02,
311 	MLX5_CMD_OP_DESTROY_GENERAL_OBJECT        = 0xa03,
312 	MLX5_CMD_OP_CREATE_UCTX                   = 0xa04,
313 	MLX5_CMD_OP_DESTROY_UCTX                  = 0xa06,
314 	MLX5_CMD_OP_CREATE_UMEM                   = 0xa08,
315 	MLX5_CMD_OP_DESTROY_UMEM                  = 0xa0a,
316 	MLX5_CMD_OP_SYNC_STEERING                 = 0xb00,
317 	MLX5_CMD_OP_PSP_GEN_SPI                   = 0xb10,
318 	MLX5_CMD_OP_PSP_ROTATE_KEY                = 0xb11,
319 	MLX5_CMD_OP_QUERY_VHCA_STATE              = 0xb0d,
320 	MLX5_CMD_OP_MODIFY_VHCA_STATE             = 0xb0e,
321 	MLX5_CMD_OP_SYNC_CRYPTO                   = 0xb12,
322 	MLX5_CMD_OP_ALLOW_OTHER_VHCA_ACCESS       = 0xb16,
323 	MLX5_CMD_OP_GENERATE_WQE                  = 0xb17,
324 	MLX5_CMD_OPCODE_QUERY_VUID                = 0xb22,
325 	MLX5_CMD_OP_MAX
326 };
327 
328 /* Valid range for general commands that don't work over an object */
329 enum {
330 	MLX5_CMD_OP_GENERAL_START = 0xb00,
331 	MLX5_CMD_OP_GENERAL_END = 0xd00,
332 };
333 
334 enum {
335 	MLX5_FT_NIC_RX_2_NIC_RX_RDMA = BIT(0),
336 	MLX5_FT_NIC_TX_RDMA_2_NIC_TX = BIT(1),
337 };
338 
339 enum {
340 	MLX5_CMD_OP_MOD_UPDATE_HEADER_MODIFY_ARGUMENT = 0x1,
341 };
342 
343 struct mlx5_ifc_flow_table_fields_supported_bits {
344 	u8         outer_dmac[0x1];
345 	u8         outer_smac[0x1];
346 	u8         outer_ether_type[0x1];
347 	u8         outer_ip_version[0x1];
348 	u8         outer_first_prio[0x1];
349 	u8         outer_first_cfi[0x1];
350 	u8         outer_first_vid[0x1];
351 	u8         outer_ipv4_ttl[0x1];
352 	u8         outer_second_prio[0x1];
353 	u8         outer_second_cfi[0x1];
354 	u8         outer_second_vid[0x1];
355 	u8         reserved_at_b[0x1];
356 	u8         outer_sip[0x1];
357 	u8         outer_dip[0x1];
358 	u8         outer_frag[0x1];
359 	u8         outer_ip_protocol[0x1];
360 	u8         outer_ip_ecn[0x1];
361 	u8         outer_ip_dscp[0x1];
362 	u8         outer_udp_sport[0x1];
363 	u8         outer_udp_dport[0x1];
364 	u8         outer_tcp_sport[0x1];
365 	u8         outer_tcp_dport[0x1];
366 	u8         outer_tcp_flags[0x1];
367 	u8         outer_gre_protocol[0x1];
368 	u8         outer_gre_key[0x1];
369 	u8         outer_vxlan_vni[0x1];
370 	u8         outer_geneve_vni[0x1];
371 	u8         outer_geneve_oam[0x1];
372 	u8         outer_geneve_protocol_type[0x1];
373 	u8         outer_geneve_opt_len[0x1];
374 	u8         source_vhca_port[0x1];
375 	u8         source_eswitch_port[0x1];
376 
377 	u8         inner_dmac[0x1];
378 	u8         inner_smac[0x1];
379 	u8         inner_ether_type[0x1];
380 	u8         inner_ip_version[0x1];
381 	u8         inner_first_prio[0x1];
382 	u8         inner_first_cfi[0x1];
383 	u8         inner_first_vid[0x1];
384 	u8         reserved_at_27[0x1];
385 	u8         inner_second_prio[0x1];
386 	u8         inner_second_cfi[0x1];
387 	u8         inner_second_vid[0x1];
388 	u8         reserved_at_2b[0x1];
389 	u8         inner_sip[0x1];
390 	u8         inner_dip[0x1];
391 	u8         inner_frag[0x1];
392 	u8         inner_ip_protocol[0x1];
393 	u8         inner_ip_ecn[0x1];
394 	u8         inner_ip_dscp[0x1];
395 	u8         inner_udp_sport[0x1];
396 	u8         inner_udp_dport[0x1];
397 	u8         inner_tcp_sport[0x1];
398 	u8         inner_tcp_dport[0x1];
399 	u8         inner_tcp_flags[0x1];
400 	u8         reserved_at_37[0x9];
401 
402 	u8         geneve_tlv_option_0_data[0x1];
403 	u8         geneve_tlv_option_0_exist[0x1];
404 	u8         reserved_at_42[0x3];
405 	u8         outer_first_mpls_over_udp[0x4];
406 	u8         outer_first_mpls_over_gre[0x4];
407 	u8         inner_first_mpls[0x4];
408 	u8         outer_first_mpls[0x4];
409 	u8         reserved_at_55[0x2];
410 	u8	   outer_esp_spi[0x1];
411 	u8         reserved_at_58[0x2];
412 	u8         bth_dst_qp[0x1];
413 	u8         reserved_at_5b[0x5];
414 
415 	u8         reserved_at_60[0x18];
416 	u8         metadata_reg_c_7[0x1];
417 	u8         metadata_reg_c_6[0x1];
418 	u8         metadata_reg_c_5[0x1];
419 	u8         metadata_reg_c_4[0x1];
420 	u8         metadata_reg_c_3[0x1];
421 	u8         metadata_reg_c_2[0x1];
422 	u8         metadata_reg_c_1[0x1];
423 	u8         metadata_reg_c_0[0x1];
424 };
425 
426 /* Table 2170 - Flow Table Fields Supported 2 Format */
427 struct mlx5_ifc_flow_table_fields_supported_2_bits {
428 	u8         inner_l4_type_ext[0x1];
429 	u8         outer_l4_type_ext[0x1];
430 	u8         inner_l4_type[0x1];
431 	u8         outer_l4_type[0x1];
432 	u8         reserved_at_4[0xa];
433 	u8         bth_opcode[0x1];
434 	u8         reserved_at_f[0x1];
435 	u8         tunnel_header_0_1[0x1];
436 	u8         reserved_at_11[0xf];
437 
438 	u8         reserved_at_20[0xf];
439 	u8         ipsec_next_header[0x1];
440 	u8         reserved_at_30[0x10];
441 
442 	u8         reserved_at_40[0x40];
443 };
444 
445 struct mlx5_ifc_flow_table_prop_layout_bits {
446 	u8         ft_support[0x1];
447 	u8         reserved_at_1[0x1];
448 	u8         flow_counter[0x1];
449 	u8	   flow_modify_en[0x1];
450 	u8         modify_root[0x1];
451 	u8         identified_miss_table_mode[0x1];
452 	u8         flow_table_modify[0x1];
453 	u8         reformat[0x1];
454 	u8         decap[0x1];
455 	u8         reset_root_to_default[0x1];
456 	u8         pop_vlan[0x1];
457 	u8         push_vlan[0x1];
458 	u8         reserved_at_c[0x1];
459 	u8         pop_vlan_2[0x1];
460 	u8         push_vlan_2[0x1];
461 	u8	   reformat_and_vlan_action[0x1];
462 	u8	   reserved_at_10[0x1];
463 	u8         sw_owner[0x1];
464 	u8	   reformat_l3_tunnel_to_l2[0x1];
465 	u8	   reformat_l2_to_l3_tunnel[0x1];
466 	u8	   reformat_and_modify_action[0x1];
467 	u8	   ignore_flow_level[0x1];
468 	u8         reserved_at_16[0x1];
469 	u8	   table_miss_action_domain[0x1];
470 	u8         termination_table[0x1];
471 	u8         reformat_and_fwd_to_table[0x1];
472 	u8         reserved_at_1a[0x2];
473 	u8         ipsec_encrypt[0x1];
474 	u8         ipsec_decrypt[0x1];
475 	u8         sw_owner_v2[0x1];
476 	u8         reserved_at_1f[0x1];
477 
478 	u8         termination_table_raw_traffic[0x1];
479 	u8         reserved_at_21[0x1];
480 	u8         log_max_ft_size[0x6];
481 	u8         log_max_modify_header_context[0x8];
482 	u8         max_modify_header_actions[0x8];
483 	u8         max_ft_level[0x8];
484 
485 	u8         reformat_add_esp_trasport[0x1];
486 	u8         reformat_l2_to_l3_esp_tunnel[0x1];
487 	u8         reformat_add_esp_transport_over_udp[0x1];
488 	u8         reformat_del_esp_trasport[0x1];
489 	u8         reformat_l3_esp_tunnel_to_l2[0x1];
490 	u8         reformat_del_esp_transport_over_udp[0x1];
491 	u8         execute_aso[0x1];
492 	u8         reserved_at_47[0x19];
493 
494 	u8         reformat_l2_to_l3_psp_tunnel[0x1];
495 	u8         reformat_l3_psp_tunnel_to_l2[0x1];
496 	u8         reformat_insert[0x1];
497 	u8         reformat_remove[0x1];
498 	u8         macsec_encrypt[0x1];
499 	u8         macsec_decrypt[0x1];
500 	u8         psp_encrypt[0x1];
501 	u8         psp_decrypt[0x1];
502 	u8         reformat_add_macsec[0x1];
503 	u8         reformat_remove_macsec[0x1];
504 	u8         reparse[0x1];
505 	u8         reserved_at_6b[0x1];
506 	u8         cross_vhca_object[0x1];
507 	u8         reformat_l2_to_l3_audp_tunnel[0x1];
508 	u8         reformat_l3_audp_tunnel_to_l2[0x1];
509 	u8         ignore_flow_level_rtc_valid[0x1];
510 	u8         reserved_at_70[0x8];
511 	u8         log_max_ft_num[0x8];
512 
513 	u8         reserved_at_80[0x10];
514 	u8         log_max_flow_counter[0x8];
515 	u8         log_max_destination[0x8];
516 
517 	u8         reserved_at_a0[0x18];
518 	u8         log_max_flow[0x8];
519 
520 	u8         reserved_at_c0[0x40];
521 
522 	struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
523 
524 	struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
525 };
526 
527 struct mlx5_ifc_odp_per_transport_service_cap_bits {
528 	u8         send[0x1];
529 	u8         receive[0x1];
530 	u8         write[0x1];
531 	u8         read[0x1];
532 	u8         atomic[0x1];
533 	u8         srq_receive[0x1];
534 	u8         reserved_at_6[0x1a];
535 };
536 
537 struct mlx5_ifc_ipv4_layout_bits {
538 	u8         reserved_at_0[0x60];
539 
540 	u8         ipv4[0x20];
541 };
542 
543 struct mlx5_ifc_ipv6_layout_bits {
544 	u8         ipv6[16][0x8];
545 };
546 
547 struct mlx5_ifc_ipv6_simple_layout_bits {
548 	u8         ipv6_127_96[0x20];
549 	u8         ipv6_95_64[0x20];
550 	u8         ipv6_63_32[0x20];
551 	u8         ipv6_31_0[0x20];
552 };
553 
554 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits {
555 	struct mlx5_ifc_ipv6_simple_layout_bits ipv6_simple_layout;
556 	struct mlx5_ifc_ipv6_layout_bits ipv6_layout;
557 	struct mlx5_ifc_ipv4_layout_bits ipv4_layout;
558 	u8         reserved_at_0[0x80];
559 };
560 
561 enum {
562 	MLX5_PACKET_L4_TYPE_NONE,
563 	MLX5_PACKET_L4_TYPE_TCP,
564 	MLX5_PACKET_L4_TYPE_UDP,
565 };
566 
567 enum {
568 	MLX5_PACKET_L4_TYPE_EXT_NONE,
569 	MLX5_PACKET_L4_TYPE_EXT_TCP,
570 	MLX5_PACKET_L4_TYPE_EXT_UDP,
571 	MLX5_PACKET_L4_TYPE_EXT_ICMP,
572 };
573 
574 struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
575 	u8         smac_47_16[0x20];
576 
577 	u8         smac_15_0[0x10];
578 	u8         ethertype[0x10];
579 
580 	u8         dmac_47_16[0x20];
581 
582 	u8         dmac_15_0[0x10];
583 	u8         first_prio[0x3];
584 	u8         first_cfi[0x1];
585 	u8         first_vid[0xc];
586 
587 	u8         ip_protocol[0x8];
588 	u8         ip_dscp[0x6];
589 	u8         ip_ecn[0x2];
590 	u8         cvlan_tag[0x1];
591 	u8         svlan_tag[0x1];
592 	u8         frag[0x1];
593 	u8         ip_version[0x4];
594 	u8         tcp_flags[0x9];
595 
596 	u8         tcp_sport[0x10];
597 	u8         tcp_dport[0x10];
598 
599 	u8         l4_type[0x2];
600 	u8         l4_type_ext[0x4];
601 	u8         reserved_at_c6[0xa];
602 	u8         ipv4_ihl[0x4];
603 	u8         reserved_at_d4[0x4];
604 	u8         ttl_hoplimit[0x8];
605 
606 	u8         udp_sport[0x10];
607 	u8         udp_dport[0x10];
608 
609 	union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
610 
611 	union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
612 };
613 
614 struct mlx5_ifc_nvgre_key_bits {
615 	u8 hi[0x18];
616 	u8 lo[0x8];
617 };
618 
619 union mlx5_ifc_gre_key_bits {
620 	struct mlx5_ifc_nvgre_key_bits nvgre;
621 	u8 key[0x20];
622 };
623 
624 struct mlx5_ifc_fte_match_set_misc_bits {
625 	u8         gre_c_present[0x1];
626 	u8         reserved_at_1[0x1];
627 	u8         gre_k_present[0x1];
628 	u8         gre_s_present[0x1];
629 	u8         source_vhca_port[0x4];
630 	u8         source_sqn[0x18];
631 
632 	u8         source_eswitch_owner_vhca_id[0x10];
633 	u8         source_port[0x10];
634 
635 	u8         outer_second_prio[0x3];
636 	u8         outer_second_cfi[0x1];
637 	u8         outer_second_vid[0xc];
638 	u8         inner_second_prio[0x3];
639 	u8         inner_second_cfi[0x1];
640 	u8         inner_second_vid[0xc];
641 
642 	u8         outer_second_cvlan_tag[0x1];
643 	u8         inner_second_cvlan_tag[0x1];
644 	u8         outer_second_svlan_tag[0x1];
645 	u8         inner_second_svlan_tag[0x1];
646 	u8         reserved_at_64[0xc];
647 	u8         gre_protocol[0x10];
648 
649 	union mlx5_ifc_gre_key_bits gre_key;
650 
651 	u8         vxlan_vni[0x18];
652 	u8         bth_opcode[0x8];
653 
654 	u8         geneve_vni[0x18];
655 	u8         reserved_at_d8[0x6];
656 	u8         geneve_tlv_option_0_exist[0x1];
657 	u8         geneve_oam[0x1];
658 
659 	u8         reserved_at_e0[0xc];
660 	u8         outer_ipv6_flow_label[0x14];
661 
662 	u8         reserved_at_100[0xc];
663 	u8         inner_ipv6_flow_label[0x14];
664 
665 	u8         reserved_at_120[0xa];
666 	u8         geneve_opt_len[0x6];
667 	u8         geneve_protocol_type[0x10];
668 
669 	u8         reserved_at_140[0x8];
670 	u8         bth_dst_qp[0x18];
671 	u8	   inner_esp_spi[0x20];
672 	u8	   outer_esp_spi[0x20];
673 	u8         reserved_at_1a0[0x60];
674 };
675 
676 struct mlx5_ifc_fte_match_mpls_bits {
677 	u8         mpls_label[0x14];
678 	u8         mpls_exp[0x3];
679 	u8         mpls_s_bos[0x1];
680 	u8         mpls_ttl[0x8];
681 };
682 
683 struct mlx5_ifc_fte_match_set_misc2_bits {
684 	struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls;
685 
686 	struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls;
687 
688 	struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre;
689 
690 	struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp;
691 
692 	u8         metadata_reg_c_7[0x20];
693 
694 	u8         metadata_reg_c_6[0x20];
695 
696 	u8         metadata_reg_c_5[0x20];
697 
698 	u8         metadata_reg_c_4[0x20];
699 
700 	u8         metadata_reg_c_3[0x20];
701 
702 	u8         metadata_reg_c_2[0x20];
703 
704 	u8         metadata_reg_c_1[0x20];
705 
706 	u8         metadata_reg_c_0[0x20];
707 
708 	u8         metadata_reg_a[0x20];
709 
710 	u8         psp_syndrome[0x8];
711 	u8         macsec_syndrome[0x8];
712 	u8         ipsec_syndrome[0x8];
713 	u8         ipsec_next_header[0x8];
714 
715 	u8         reserved_at_1c0[0x40];
716 };
717 
718 struct mlx5_ifc_fte_match_set_misc3_bits {
719 	u8         inner_tcp_seq_num[0x20];
720 
721 	u8         outer_tcp_seq_num[0x20];
722 
723 	u8         inner_tcp_ack_num[0x20];
724 
725 	u8         outer_tcp_ack_num[0x20];
726 
727 	u8	   reserved_at_80[0x8];
728 	u8         outer_vxlan_gpe_vni[0x18];
729 
730 	u8         outer_vxlan_gpe_next_protocol[0x8];
731 	u8         outer_vxlan_gpe_flags[0x8];
732 	u8	   reserved_at_b0[0x10];
733 
734 	u8	   icmp_header_data[0x20];
735 
736 	u8	   icmpv6_header_data[0x20];
737 
738 	u8	   icmp_type[0x8];
739 	u8	   icmp_code[0x8];
740 	u8	   icmpv6_type[0x8];
741 	u8	   icmpv6_code[0x8];
742 
743 	u8         geneve_tlv_option_0_data[0x20];
744 
745 	u8	   gtpu_teid[0x20];
746 
747 	u8	   gtpu_msg_type[0x8];
748 	u8	   gtpu_msg_flags[0x8];
749 	u8	   reserved_at_170[0x10];
750 
751 	u8	   gtpu_dw_2[0x20];
752 
753 	u8	   gtpu_first_ext_dw_0[0x20];
754 
755 	u8	   gtpu_dw_0[0x20];
756 
757 	u8	   reserved_at_1e0[0x20];
758 };
759 
760 struct mlx5_ifc_fte_match_set_misc4_bits {
761 	u8         prog_sample_field_value_0[0x20];
762 
763 	u8         prog_sample_field_id_0[0x20];
764 
765 	u8         prog_sample_field_value_1[0x20];
766 
767 	u8         prog_sample_field_id_1[0x20];
768 
769 	u8         prog_sample_field_value_2[0x20];
770 
771 	u8         prog_sample_field_id_2[0x20];
772 
773 	u8         prog_sample_field_value_3[0x20];
774 
775 	u8         prog_sample_field_id_3[0x20];
776 
777 	u8         reserved_at_100[0x100];
778 };
779 
780 struct mlx5_ifc_fte_match_set_misc5_bits {
781 	u8         macsec_tag_0[0x20];
782 
783 	u8         macsec_tag_1[0x20];
784 
785 	u8         macsec_tag_2[0x20];
786 
787 	u8         macsec_tag_3[0x20];
788 
789 	u8         tunnel_header_0[0x20];
790 
791 	u8         tunnel_header_1[0x20];
792 
793 	u8         tunnel_header_2[0x20];
794 
795 	u8         tunnel_header_3[0x20];
796 
797 	u8         reserved_at_100[0x100];
798 };
799 
800 struct mlx5_ifc_cmd_pas_bits {
801 	u8         pa_h[0x20];
802 
803 	u8         pa_l[0x14];
804 	u8         reserved_at_34[0xc];
805 };
806 
807 struct mlx5_ifc_uint64_bits {
808 	u8         hi[0x20];
809 
810 	u8         lo[0x20];
811 };
812 
813 enum {
814 	MLX5_ADS_STAT_RATE_NO_LIMIT  = 0x0,
815 	MLX5_ADS_STAT_RATE_2_5GBPS   = 0x7,
816 	MLX5_ADS_STAT_RATE_10GBPS    = 0x8,
817 	MLX5_ADS_STAT_RATE_30GBPS    = 0x9,
818 	MLX5_ADS_STAT_RATE_5GBPS     = 0xa,
819 	MLX5_ADS_STAT_RATE_20GBPS    = 0xb,
820 	MLX5_ADS_STAT_RATE_40GBPS    = 0xc,
821 	MLX5_ADS_STAT_RATE_60GBPS    = 0xd,
822 	MLX5_ADS_STAT_RATE_80GBPS    = 0xe,
823 	MLX5_ADS_STAT_RATE_120GBPS   = 0xf,
824 };
825 
826 struct mlx5_ifc_ads_bits {
827 	u8         fl[0x1];
828 	u8         free_ar[0x1];
829 	u8         reserved_at_2[0xe];
830 	u8         pkey_index[0x10];
831 
832 	u8         plane_index[0x8];
833 	u8         grh[0x1];
834 	u8         mlid[0x7];
835 	u8         rlid[0x10];
836 
837 	u8         ack_timeout[0x5];
838 	u8         reserved_at_45[0x3];
839 	u8         src_addr_index[0x8];
840 	u8         reserved_at_50[0x4];
841 	u8         stat_rate[0x4];
842 	u8         hop_limit[0x8];
843 
844 	u8         reserved_at_60[0x4];
845 	u8         tclass[0x8];
846 	u8         flow_label[0x14];
847 
848 	u8         rgid_rip[16][0x8];
849 
850 	u8         reserved_at_100[0x4];
851 	u8         f_dscp[0x1];
852 	u8         f_ecn[0x1];
853 	u8         reserved_at_106[0x1];
854 	u8         f_eth_prio[0x1];
855 	u8         ecn[0x2];
856 	u8         dscp[0x6];
857 	u8         udp_sport[0x10];
858 
859 	u8         dei_cfi[0x1];
860 	u8         eth_prio[0x3];
861 	u8         sl[0x4];
862 	u8         vhca_port_num[0x8];
863 	u8         rmac_47_32[0x10];
864 
865 	u8         rmac_31_0[0x20];
866 };
867 
868 struct mlx5_ifc_flow_table_nic_cap_bits {
869 	u8         nic_rx_multi_path_tirs[0x1];
870 	u8         nic_rx_multi_path_tirs_fts[0x1];
871 	u8         allow_sniffer_and_nic_rx_shared_tir[0x1];
872 	u8	   reserved_at_3[0x4];
873 	u8	   sw_owner_reformat_supported[0x1];
874 	u8	   reserved_at_8[0x18];
875 
876 	u8	   encap_general_header[0x1];
877 	u8	   reserved_at_21[0xa];
878 	u8	   log_max_packet_reformat_context[0x5];
879 	u8	   reserved_at_30[0x6];
880 	u8	   max_encap_header_size[0xa];
881 	u8	   reserved_at_40[0x1c0];
882 
883 	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
884 
885 	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_rdma;
886 
887 	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
888 
889 	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
890 
891 	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_rdma;
892 
893 	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
894 
895 	u8         reserved_at_e00[0x600];
896 
897 	struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_receive;
898 
899 	u8         reserved_at_1480[0x80];
900 
901 	struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_receive_rdma;
902 
903 	u8         reserved_at_1580[0x280];
904 
905 	struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_transmit_rdma;
906 
907 	u8         reserved_at_1880[0x780];
908 
909 	u8         sw_steering_nic_rx_action_drop_icm_address[0x40];
910 
911 	u8         sw_steering_nic_tx_action_drop_icm_address[0x40];
912 
913 	u8         sw_steering_nic_tx_action_allow_icm_address[0x40];
914 
915 	u8         reserved_at_20c0[0x5f40];
916 };
917 
918 struct mlx5_ifc_port_selection_cap_bits {
919 	u8         reserved_at_0[0x10];
920 	u8         port_select_flow_table[0x1];
921 	u8         reserved_at_11[0x1];
922 	u8         port_select_flow_table_bypass[0x1];
923 	u8         reserved_at_13[0xd];
924 
925 	u8         reserved_at_20[0x1e0];
926 
927 	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_port_selection;
928 
929 	struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_port_selection;
930 
931 	u8         reserved_at_480[0x7b80];
932 };
933 
934 enum {
935 	MLX5_FDB_TO_VPORT_REG_C_0 = 0x01,
936 	MLX5_FDB_TO_VPORT_REG_C_1 = 0x02,
937 	MLX5_FDB_TO_VPORT_REG_C_2 = 0x04,
938 	MLX5_FDB_TO_VPORT_REG_C_3 = 0x08,
939 	MLX5_FDB_TO_VPORT_REG_C_4 = 0x10,
940 	MLX5_FDB_TO_VPORT_REG_C_5 = 0x20,
941 	MLX5_FDB_TO_VPORT_REG_C_6 = 0x40,
942 	MLX5_FDB_TO_VPORT_REG_C_7 = 0x80,
943 };
944 
945 struct mlx5_ifc_flow_table_eswitch_cap_bits {
946 	u8      fdb_to_vport_reg_c_id[0x8];
947 	u8      reserved_at_8[0x5];
948 	u8      fdb_uplink_hairpin[0x1];
949 	u8      fdb_multi_path_any_table_limit_regc[0x1];
950 	u8      reserved_at_f[0x1];
951 	u8      fdb_dynamic_tunnel[0x1];
952 	u8      reserved_at_11[0x1];
953 	u8      fdb_multi_path_any_table[0x1];
954 	u8      reserved_at_13[0x2];
955 	u8      fdb_modify_header_fwd_to_table[0x1];
956 	u8      fdb_ipv4_ttl_modify[0x1];
957 	u8      flow_source[0x1];
958 	u8      reserved_at_18[0x2];
959 	u8      multi_fdb_encap[0x1];
960 	u8      egress_acl_forward_to_vport[0x1];
961 	u8      fdb_multi_path_to_table[0x1];
962 	u8      reserved_at_1d[0x3];
963 
964 	u8      reserved_at_20[0x1e0];
965 
966 	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb;
967 
968 	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress;
969 
970 	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress;
971 
972 	u8      reserved_at_800[0xC00];
973 
974 	struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_esw_fdb;
975 
976 	struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_bitmask_support_2_esw_fdb;
977 
978 	u8      reserved_at_1500[0x300];
979 
980 	u8      sw_steering_fdb_action_drop_icm_address_rx[0x40];
981 
982 	u8      sw_steering_fdb_action_drop_icm_address_tx[0x40];
983 
984 	u8      sw_steering_uplink_icm_address_rx[0x40];
985 
986 	u8      sw_steering_uplink_icm_address_tx[0x40];
987 
988 	u8      reserved_at_1900[0x6700];
989 };
990 
991 struct mlx5_ifc_wqe_based_flow_table_cap_bits {
992 	u8         reserved_at_0[0x3];
993 	u8         log_max_num_ste[0x5];
994 	u8         reserved_at_8[0x3];
995 	u8         log_max_num_stc[0x5];
996 	u8         reserved_at_10[0x3];
997 	u8         log_max_num_rtc[0x5];
998 	u8         reserved_at_18[0x3];
999 	u8         log_max_num_header_modify_pattern[0x5];
1000 
1001 	u8         rtc_hash_split_table[0x1];
1002 	u8         rtc_linear_lookup_table[0x1];
1003 	u8         reserved_at_22[0x1];
1004 	u8         stc_alloc_log_granularity[0x5];
1005 	u8         reserved_at_28[0x3];
1006 	u8         stc_alloc_log_max[0x5];
1007 	u8         reserved_at_30[0x3];
1008 	u8         ste_alloc_log_granularity[0x5];
1009 	u8         reserved_at_38[0x3];
1010 	u8         ste_alloc_log_max[0x5];
1011 
1012 	u8         reserved_at_40[0xb];
1013 	u8         rtc_reparse_mode[0x5];
1014 	u8         reserved_at_50[0x3];
1015 	u8         rtc_index_mode[0x5];
1016 	u8         reserved_at_58[0x3];
1017 	u8         rtc_log_depth_max[0x5];
1018 
1019 	u8         reserved_at_60[0x10];
1020 	u8         ste_format[0x10];
1021 
1022 	u8         stc_action_type[0x80];
1023 
1024 	u8         header_insert_type[0x10];
1025 	u8         header_remove_type[0x10];
1026 
1027 	u8         trivial_match_definer[0x20];
1028 
1029 	u8         reserved_at_140[0x1b];
1030 	u8         rtc_max_num_hash_definer_gen_wqe[0x5];
1031 
1032 	u8         reserved_at_160[0x18];
1033 	u8         access_index_mode[0x8];
1034 
1035 	u8         reserved_at_180[0x10];
1036 	u8         ste_format_gen_wqe[0x10];
1037 
1038 	u8         linear_match_definer_reg_c3[0x20];
1039 
1040 	u8         fdb_jump_to_tir_stc[0x1];
1041 	u8         reserved_at_1c1[0x1f];
1042 };
1043 
1044 struct mlx5_ifc_esw_cap_bits {
1045 	u8         reserved_at_0[0x1d];
1046 	u8         merged_eswitch[0x1];
1047 	u8         reserved_at_1e[0x2];
1048 
1049 	u8         reserved_at_20[0x40];
1050 
1051 	u8         esw_manager_vport_number_valid[0x1];
1052 	u8         reserved_at_61[0xf];
1053 	u8         esw_manager_vport_number[0x10];
1054 
1055 	u8         reserved_at_80[0x780];
1056 };
1057 
1058 enum {
1059 	MLX5_COUNTER_SOURCE_ESWITCH = 0x0,
1060 	MLX5_COUNTER_FLOW_ESWITCH   = 0x1,
1061 };
1062 
1063 struct mlx5_ifc_e_switch_cap_bits {
1064 	u8         vport_svlan_strip[0x1];
1065 	u8         vport_cvlan_strip[0x1];
1066 	u8         vport_svlan_insert[0x1];
1067 	u8         vport_cvlan_insert_if_not_exist[0x1];
1068 	u8         vport_cvlan_insert_overwrite[0x1];
1069 	u8         reserved_at_5[0x1];
1070 	u8         vport_cvlan_insert_always[0x1];
1071 	u8         esw_shared_ingress_acl[0x1];
1072 	u8         esw_uplink_ingress_acl[0x1];
1073 	u8         root_ft_on_other_esw[0x1];
1074 	u8         reserved_at_a[0xf];
1075 	u8         esw_functions_changed[0x1];
1076 	u8         reserved_at_1a[0x1];
1077 	u8         ecpf_vport_exists[0x1];
1078 	u8         counter_eswitch_affinity[0x1];
1079 	u8         merged_eswitch[0x1];
1080 	u8         nic_vport_node_guid_modify[0x1];
1081 	u8         nic_vport_port_guid_modify[0x1];
1082 
1083 	u8         vxlan_encap_decap[0x1];
1084 	u8         nvgre_encap_decap[0x1];
1085 	u8         reserved_at_22[0x1];
1086 	u8         log_max_fdb_encap_uplink[0x5];
1087 	u8         reserved_at_21[0x3];
1088 	u8         log_max_packet_reformat_context[0x5];
1089 	u8         reserved_2b[0x6];
1090 	u8         max_encap_header_size[0xa];
1091 
1092 	u8         reserved_at_40[0xb];
1093 	u8         log_max_esw_sf[0x5];
1094 	u8         esw_sf_base_id[0x10];
1095 
1096 	u8         reserved_at_60[0x7a0];
1097 
1098 };
1099 
1100 struct mlx5_ifc_qos_cap_bits {
1101 	u8         packet_pacing[0x1];
1102 	u8         esw_scheduling[0x1];
1103 	u8         esw_bw_share[0x1];
1104 	u8         esw_rate_limit[0x1];
1105 	u8         reserved_at_4[0x1];
1106 	u8         packet_pacing_burst_bound[0x1];
1107 	u8         packet_pacing_typical_size[0x1];
1108 	u8         reserved_at_7[0x1];
1109 	u8         nic_sq_scheduling[0x1];
1110 	u8         nic_bw_share[0x1];
1111 	u8         nic_rate_limit[0x1];
1112 	u8         packet_pacing_uid[0x1];
1113 	u8         log_esw_max_sched_depth[0x4];
1114 	u8         reserved_at_10[0x10];
1115 
1116 	u8         reserved_at_20[0x9];
1117 	u8         esw_cross_esw_sched[0x1];
1118 	u8         reserved_at_2a[0x1];
1119 	u8         log_max_qos_nic_queue_group[0x5];
1120 	u8         reserved_at_30[0x10];
1121 
1122 	u8         packet_pacing_max_rate[0x20];
1123 
1124 	u8         packet_pacing_min_rate[0x20];
1125 
1126 	u8         reserved_at_80[0xb];
1127 	u8         log_esw_max_rate_limit[0x5];
1128 	u8         packet_pacing_rate_table_size[0x10];
1129 
1130 	u8         esw_element_type[0x10];
1131 	u8         esw_tsar_type[0x10];
1132 
1133 	u8         reserved_at_c0[0x10];
1134 	u8         max_qos_para_vport[0x10];
1135 
1136 	u8         max_tsar_bw_share[0x20];
1137 
1138 	u8         nic_element_type[0x10];
1139 	u8         nic_tsar_type[0x10];
1140 
1141 	u8         reserved_at_120[0x3];
1142 	u8         log_meter_aso_granularity[0x5];
1143 	u8         reserved_at_128[0x3];
1144 	u8         log_meter_aso_max_alloc[0x5];
1145 	u8         reserved_at_130[0x3];
1146 	u8         log_max_num_meter_aso[0x5];
1147 	u8         reserved_at_138[0x8];
1148 
1149 	u8         reserved_at_140[0x6c0];
1150 };
1151 
1152 struct mlx5_ifc_debug_cap_bits {
1153 	u8         core_dump_general[0x1];
1154 	u8         core_dump_qp[0x1];
1155 	u8         reserved_at_2[0x7];
1156 	u8         resource_dump[0x1];
1157 	u8         reserved_at_a[0x16];
1158 
1159 	u8         reserved_at_20[0x2];
1160 	u8         stall_detect[0x1];
1161 	u8         reserved_at_23[0x1d];
1162 
1163 	u8         reserved_at_40[0x7c0];
1164 };
1165 
1166 struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
1167 	u8         csum_cap[0x1];
1168 	u8         vlan_cap[0x1];
1169 	u8         lro_cap[0x1];
1170 	u8         lro_psh_flag[0x1];
1171 	u8         lro_time_stamp[0x1];
1172 	u8         reserved_at_5[0x2];
1173 	u8         wqe_vlan_insert[0x1];
1174 	u8         self_lb_en_modifiable[0x1];
1175 	u8         reserved_at_9[0x2];
1176 	u8         max_lso_cap[0x5];
1177 	u8         multi_pkt_send_wqe[0x2];
1178 	u8	   wqe_inline_mode[0x2];
1179 	u8         rss_ind_tbl_cap[0x4];
1180 	u8         reg_umr_sq[0x1];
1181 	u8         scatter_fcs[0x1];
1182 	u8         enhanced_multi_pkt_send_wqe[0x1];
1183 	u8         tunnel_lso_const_out_ip_id[0x1];
1184 	u8         tunnel_lro_gre[0x1];
1185 	u8         tunnel_lro_vxlan[0x1];
1186 	u8         tunnel_stateless_gre[0x1];
1187 	u8         tunnel_stateless_vxlan[0x1];
1188 
1189 	u8         swp[0x1];
1190 	u8         swp_csum[0x1];
1191 	u8         swp_lso[0x1];
1192 	u8         cqe_checksum_full[0x1];
1193 	u8         tunnel_stateless_geneve_tx[0x1];
1194 	u8         tunnel_stateless_mpls_over_udp[0x1];
1195 	u8         tunnel_stateless_mpls_over_gre[0x1];
1196 	u8         tunnel_stateless_vxlan_gpe[0x1];
1197 	u8         tunnel_stateless_ipv4_over_vxlan[0x1];
1198 	u8         tunnel_stateless_ip_over_ip[0x1];
1199 	u8         insert_trailer[0x1];
1200 	u8         reserved_at_2b[0x1];
1201 	u8         tunnel_stateless_ip_over_ip_rx[0x1];
1202 	u8         tunnel_stateless_ip_over_ip_tx[0x1];
1203 	u8         reserved_at_2e[0x2];
1204 	u8         max_vxlan_udp_ports[0x8];
1205 	u8         swp_csum_l4_partial[0x1];
1206 	u8         reserved_at_39[0x5];
1207 	u8         max_geneve_opt_len[0x1];
1208 	u8         tunnel_stateless_geneve_rx[0x1];
1209 
1210 	u8         reserved_at_40[0x10];
1211 	u8         lro_min_mss_size[0x10];
1212 
1213 	u8         reserved_at_60[0x120];
1214 
1215 	u8         lro_timer_supported_periods[4][0x20];
1216 
1217 	u8         reserved_at_200[0x600];
1218 };
1219 
1220 enum {
1221 	MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING               = 0x0,
1222 	MLX5_TIMESTAMP_FORMAT_CAP_REAL_TIME                  = 0x1,
1223 	MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING_AND_REAL_TIME = 0x2,
1224 };
1225 
1226 struct mlx5_ifc_roce_cap_bits {
1227 	u8         roce_apm[0x1];
1228 	u8         reserved_at_1[0x3];
1229 	u8         sw_r_roce_src_udp_port[0x1];
1230 	u8         fl_rc_qp_when_roce_disabled[0x1];
1231 	u8         fl_rc_qp_when_roce_enabled[0x1];
1232 	u8         roce_cc_general[0x1];
1233 	u8	   qp_ooo_transmit_default[0x1];
1234 	u8         reserved_at_9[0x15];
1235 	u8	   qp_ts_format[0x2];
1236 
1237 	u8         reserved_at_20[0x60];
1238 
1239 	u8         reserved_at_80[0xc];
1240 	u8         l3_type[0x4];
1241 	u8         reserved_at_90[0x8];
1242 	u8         roce_version[0x8];
1243 
1244 	u8         reserved_at_a0[0x10];
1245 	u8         r_roce_dest_udp_port[0x10];
1246 
1247 	u8         r_roce_max_src_udp_port[0x10];
1248 	u8         r_roce_min_src_udp_port[0x10];
1249 
1250 	u8         reserved_at_e0[0x10];
1251 	u8         roce_address_table_size[0x10];
1252 
1253 	u8         reserved_at_100[0x700];
1254 };
1255 
1256 struct mlx5_ifc_sync_steering_in_bits {
1257 	u8         opcode[0x10];
1258 	u8         uid[0x10];
1259 
1260 	u8         reserved_at_20[0x10];
1261 	u8         op_mod[0x10];
1262 
1263 	u8         reserved_at_40[0xc0];
1264 };
1265 
1266 struct mlx5_ifc_sync_steering_out_bits {
1267 	u8         status[0x8];
1268 	u8         reserved_at_8[0x18];
1269 
1270 	u8         syndrome[0x20];
1271 
1272 	u8         reserved_at_40[0x40];
1273 };
1274 
1275 struct mlx5_ifc_sync_crypto_in_bits {
1276 	u8         opcode[0x10];
1277 	u8         uid[0x10];
1278 
1279 	u8         reserved_at_20[0x10];
1280 	u8         op_mod[0x10];
1281 
1282 	u8         reserved_at_40[0x20];
1283 
1284 	u8         reserved_at_60[0x10];
1285 	u8         crypto_type[0x10];
1286 
1287 	u8         reserved_at_80[0x80];
1288 };
1289 
1290 struct mlx5_ifc_sync_crypto_out_bits {
1291 	u8         status[0x8];
1292 	u8         reserved_at_8[0x18];
1293 
1294 	u8         syndrome[0x20];
1295 
1296 	u8         reserved_at_40[0x40];
1297 };
1298 
1299 struct mlx5_ifc_device_mem_cap_bits {
1300 	u8         memic[0x1];
1301 	u8         reserved_at_1[0x1f];
1302 
1303 	u8         reserved_at_20[0xb];
1304 	u8         log_min_memic_alloc_size[0x5];
1305 	u8         reserved_at_30[0x8];
1306 	u8	   log_max_memic_addr_alignment[0x8];
1307 
1308 	u8         memic_bar_start_addr[0x40];
1309 
1310 	u8         memic_bar_size[0x20];
1311 
1312 	u8         max_memic_size[0x20];
1313 
1314 	u8         steering_sw_icm_start_address[0x40];
1315 
1316 	u8         reserved_at_100[0x8];
1317 	u8         log_header_modify_sw_icm_size[0x8];
1318 	u8         reserved_at_110[0x2];
1319 	u8         log_sw_icm_alloc_granularity[0x6];
1320 	u8         log_steering_sw_icm_size[0x8];
1321 
1322 	u8         log_indirect_encap_sw_icm_size[0x8];
1323 	u8         reserved_at_128[0x10];
1324 	u8         log_header_modify_pattern_sw_icm_size[0x8];
1325 
1326 	u8         header_modify_sw_icm_start_address[0x40];
1327 
1328 	u8         reserved_at_180[0x40];
1329 
1330 	u8         header_modify_pattern_sw_icm_start_address[0x40];
1331 
1332 	u8         memic_operations[0x20];
1333 
1334 	u8         reserved_at_220[0x20];
1335 
1336 	u8         indirect_encap_sw_icm_start_address[0x40];
1337 
1338 	u8         reserved_at_280[0x580];
1339 };
1340 
1341 struct mlx5_ifc_device_event_cap_bits {
1342 	u8         user_affiliated_events[4][0x40];
1343 
1344 	u8         user_unaffiliated_events[4][0x40];
1345 };
1346 
1347 struct mlx5_ifc_virtio_emulation_cap_bits {
1348 	u8         desc_tunnel_offload_type[0x1];
1349 	u8         eth_frame_offload_type[0x1];
1350 	u8         virtio_version_1_0[0x1];
1351 	u8         device_features_bits_mask[0xd];
1352 	u8         event_mode[0x8];
1353 	u8         virtio_queue_type[0x8];
1354 
1355 	u8         max_tunnel_desc[0x10];
1356 	u8         reserved_at_30[0x3];
1357 	u8         log_doorbell_stride[0x5];
1358 	u8         reserved_at_38[0x3];
1359 	u8         log_doorbell_bar_size[0x5];
1360 
1361 	u8         doorbell_bar_offset[0x40];
1362 
1363 	u8         max_emulated_devices[0x8];
1364 	u8         max_num_virtio_queues[0x18];
1365 
1366 	u8         reserved_at_a0[0x20];
1367 
1368 	u8	   reserved_at_c0[0x13];
1369 	u8         desc_group_mkey_supported[0x1];
1370 	u8         freeze_to_rdy_supported[0x1];
1371 	u8         reserved_at_d5[0xb];
1372 
1373 	u8         reserved_at_e0[0x20];
1374 
1375 	u8         umem_1_buffer_param_a[0x20];
1376 
1377 	u8         umem_1_buffer_param_b[0x20];
1378 
1379 	u8         umem_2_buffer_param_a[0x20];
1380 
1381 	u8         umem_2_buffer_param_b[0x20];
1382 
1383 	u8         umem_3_buffer_param_a[0x20];
1384 
1385 	u8         umem_3_buffer_param_b[0x20];
1386 
1387 	u8         reserved_at_1c0[0x640];
1388 };
1389 
1390 enum {
1391 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE     = 0x0,
1392 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES    = 0x2,
1393 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES    = 0x4,
1394 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES    = 0x8,
1395 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES   = 0x10,
1396 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES   = 0x20,
1397 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES   = 0x40,
1398 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES  = 0x80,
1399 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES  = 0x100,
1400 };
1401 
1402 enum {
1403 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE     = 0x1,
1404 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES    = 0x2,
1405 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES    = 0x4,
1406 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES    = 0x8,
1407 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES   = 0x10,
1408 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES   = 0x20,
1409 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES   = 0x40,
1410 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES  = 0x80,
1411 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES  = 0x100,
1412 };
1413 
1414 struct mlx5_ifc_atomic_caps_bits {
1415 	u8         reserved_at_0[0x40];
1416 
1417 	u8         atomic_req_8B_endianness_mode[0x2];
1418 	u8         reserved_at_42[0x4];
1419 	u8         supported_atomic_req_8B_endianness_mode_1[0x1];
1420 
1421 	u8         reserved_at_47[0x19];
1422 
1423 	u8         reserved_at_60[0x20];
1424 
1425 	u8         reserved_at_80[0x10];
1426 	u8         atomic_operations[0x10];
1427 
1428 	u8         reserved_at_a0[0x10];
1429 	u8         atomic_size_qp[0x10];
1430 
1431 	u8         reserved_at_c0[0x10];
1432 	u8         atomic_size_dc[0x10];
1433 
1434 	u8         reserved_at_e0[0x720];
1435 };
1436 
1437 struct mlx5_ifc_odp_scheme_cap_bits {
1438 	u8         reserved_at_0[0x40];
1439 
1440 	u8         sig[0x1];
1441 	u8         reserved_at_41[0x4];
1442 	u8         page_prefetch[0x1];
1443 	u8         reserved_at_46[0x1a];
1444 
1445 	u8         reserved_at_60[0x20];
1446 
1447 	struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
1448 
1449 	struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
1450 
1451 	struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
1452 
1453 	struct mlx5_ifc_odp_per_transport_service_cap_bits xrc_odp_caps;
1454 
1455 	struct mlx5_ifc_odp_per_transport_service_cap_bits dc_odp_caps;
1456 
1457 	u8         reserved_at_120[0xe0];
1458 };
1459 
1460 struct mlx5_ifc_odp_cap_bits {
1461 	struct mlx5_ifc_odp_scheme_cap_bits transport_page_fault_scheme_cap;
1462 
1463 	struct mlx5_ifc_odp_scheme_cap_bits memory_page_fault_scheme_cap;
1464 
1465 	u8         reserved_at_400[0x200];
1466 
1467 	u8         mem_page_fault[0x1];
1468 	u8         reserved_at_601[0x1f];
1469 
1470 	u8         reserved_at_620[0x1e0];
1471 };
1472 
1473 struct mlx5_ifc_tls_cap_bits {
1474 	u8         tls_1_2_aes_gcm_128[0x1];
1475 	u8         tls_1_3_aes_gcm_128[0x1];
1476 	u8         tls_1_2_aes_gcm_256[0x1];
1477 	u8         tls_1_3_aes_gcm_256[0x1];
1478 	u8         reserved_at_4[0x1c];
1479 
1480 	u8         reserved_at_20[0x7e0];
1481 };
1482 
1483 struct mlx5_ifc_ipsec_cap_bits {
1484 	u8         ipsec_full_offload[0x1];
1485 	u8         ipsec_crypto_offload[0x1];
1486 	u8         ipsec_esn[0x1];
1487 	u8         ipsec_crypto_esp_aes_gcm_256_encrypt[0x1];
1488 	u8         ipsec_crypto_esp_aes_gcm_128_encrypt[0x1];
1489 	u8         ipsec_crypto_esp_aes_gcm_256_decrypt[0x1];
1490 	u8         ipsec_crypto_esp_aes_gcm_128_decrypt[0x1];
1491 	u8         reserved_at_7[0x4];
1492 	u8         log_max_ipsec_offload[0x5];
1493 	u8         reserved_at_10[0x10];
1494 
1495 	u8         min_log_ipsec_full_replay_window[0x8];
1496 	u8         max_log_ipsec_full_replay_window[0x8];
1497 	u8         reserved_at_30[0x7d0];
1498 };
1499 
1500 struct mlx5_ifc_macsec_cap_bits {
1501 	u8    macsec_epn[0x1];
1502 	u8    reserved_at_1[0x2];
1503 	u8    macsec_crypto_esp_aes_gcm_256_encrypt[0x1];
1504 	u8    macsec_crypto_esp_aes_gcm_128_encrypt[0x1];
1505 	u8    macsec_crypto_esp_aes_gcm_256_decrypt[0x1];
1506 	u8    macsec_crypto_esp_aes_gcm_128_decrypt[0x1];
1507 	u8    reserved_at_7[0x4];
1508 	u8    log_max_macsec_offload[0x5];
1509 	u8    reserved_at_10[0x10];
1510 
1511 	u8    min_log_macsec_full_replay_window[0x8];
1512 	u8    max_log_macsec_full_replay_window[0x8];
1513 	u8    reserved_at_30[0x10];
1514 
1515 	u8    reserved_at_40[0x7c0];
1516 };
1517 
1518 struct mlx5_ifc_psp_cap_bits {
1519 	u8         reserved_at_0[0x1];
1520 	u8         psp_crypto_offload[0x1];
1521 	u8         reserved_at_2[0x1];
1522 	u8         psp_crypto_esp_aes_gcm_256_encrypt[0x1];
1523 	u8         psp_crypto_esp_aes_gcm_128_encrypt[0x1];
1524 	u8         psp_crypto_esp_aes_gcm_256_decrypt[0x1];
1525 	u8         psp_crypto_esp_aes_gcm_128_decrypt[0x1];
1526 	u8         reserved_at_7[0x4];
1527 	u8         log_max_num_of_psp_spi[0x5];
1528 	u8         reserved_at_10[0x10];
1529 
1530 	u8         reserved_at_20[0x7e0];
1531 };
1532 
1533 enum {
1534 	MLX5_WQ_TYPE_LINKED_LIST  = 0x0,
1535 	MLX5_WQ_TYPE_CYCLIC       = 0x1,
1536 	MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2,
1537 	MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3,
1538 };
1539 
1540 enum {
1541 	MLX5_WQ_END_PAD_MODE_NONE   = 0x0,
1542 	MLX5_WQ_END_PAD_MODE_ALIGN  = 0x1,
1543 };
1544 
1545 enum {
1546 	MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES    = 0x0,
1547 	MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES   = 0x1,
1548 	MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES   = 0x2,
1549 	MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES   = 0x3,
1550 	MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES  = 0x4,
1551 };
1552 
1553 enum {
1554 	MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES  = 0x0,
1555 	MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES  = 0x1,
1556 	MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES  = 0x2,
1557 	MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES   = 0x3,
1558 	MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES   = 0x4,
1559 	MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES   = 0x5,
1560 };
1561 
1562 enum {
1563 	MLX5_CMD_HCA_CAP_PORT_TYPE_IB        = 0x0,
1564 	MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET  = 0x1,
1565 };
1566 
1567 enum {
1568 	MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED       = 0x0,
1569 	MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE  = 0x1,
1570 	MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED        = 0x3,
1571 };
1572 
1573 enum {
1574 	MLX5_CAP_PORT_TYPE_IB  = 0x0,
1575 	MLX5_CAP_PORT_TYPE_ETH = 0x1,
1576 };
1577 
1578 enum {
1579 	MLX5_CAP_UMR_FENCE_STRONG	= 0x0,
1580 	MLX5_CAP_UMR_FENCE_SMALL	= 0x1,
1581 	MLX5_CAP_UMR_FENCE_NONE		= 0x2,
1582 };
1583 
1584 enum {
1585 	MLX5_FLEX_IPV4_OVER_VXLAN_ENABLED	= 1 << 0,
1586 	MLX5_FLEX_IPV6_OVER_VXLAN_ENABLED	= 1 << 1,
1587 	MLX5_FLEX_IPV6_OVER_IP_ENABLED		= 1 << 2,
1588 	MLX5_FLEX_PARSER_GENEVE_ENABLED		= 1 << 3,
1589 	MLX5_FLEX_PARSER_MPLS_OVER_GRE_ENABLED	= 1 << 4,
1590 	MLX5_FLEX_PARSER_MPLS_OVER_UDP_ENABLED	= 1 << 5,
1591 	MLX5_FLEX_P_BIT_VXLAN_GPE_ENABLED	= 1 << 6,
1592 	MLX5_FLEX_PARSER_VXLAN_GPE_ENABLED	= 1 << 7,
1593 	MLX5_FLEX_PARSER_ICMP_V4_ENABLED	= 1 << 8,
1594 	MLX5_FLEX_PARSER_ICMP_V6_ENABLED	= 1 << 9,
1595 	MLX5_FLEX_PARSER_GENEVE_TLV_OPTION_0_ENABLED = 1 << 10,
1596 	MLX5_FLEX_PARSER_GTPU_ENABLED		= 1 << 11,
1597 	MLX5_FLEX_PARSER_GTPU_DW_2_ENABLED	= 1 << 16,
1598 	MLX5_FLEX_PARSER_GTPU_FIRST_EXT_DW_0_ENABLED = 1 << 17,
1599 	MLX5_FLEX_PARSER_GTPU_DW_0_ENABLED	= 1 << 18,
1600 	MLX5_FLEX_PARSER_GTPU_TEID_ENABLED	= 1 << 19,
1601 };
1602 
1603 enum {
1604 	MLX5_UCTX_CAP_RAW_TX = 1UL << 0,
1605 	MLX5_UCTX_CAP_INTERNAL_DEV_RES = 1UL << 1,
1606 	MLX5_UCTX_CAP_RDMA_CTRL = 1UL << 3,
1607 	MLX5_UCTX_CAP_RDMA_CTRL_OTHER_VHCA = 1UL << 4,
1608 };
1609 
1610 #define MLX5_FC_BULK_SIZE_FACTOR 128
1611 
1612 enum mlx5_fc_bulk_alloc_bitmask {
1613 	MLX5_FC_BULK_128   = (1 << 0),
1614 	MLX5_FC_BULK_256   = (1 << 1),
1615 	MLX5_FC_BULK_512   = (1 << 2),
1616 	MLX5_FC_BULK_1024  = (1 << 3),
1617 	MLX5_FC_BULK_2048  = (1 << 4),
1618 	MLX5_FC_BULK_4096  = (1 << 5),
1619 	MLX5_FC_BULK_8192  = (1 << 6),
1620 	MLX5_FC_BULK_16384 = (1 << 7),
1621 };
1622 
1623 #define MLX5_FC_BULK_NUM_FCS(fc_enum) (MLX5_FC_BULK_SIZE_FACTOR * (fc_enum))
1624 
1625 #define MLX5_FT_MAX_MULTIPATH_LEVEL 63
1626 
1627 enum {
1628 	MLX5_STEERING_FORMAT_CONNECTX_5   = 0,
1629 	MLX5_STEERING_FORMAT_CONNECTX_6DX = 1,
1630 	MLX5_STEERING_FORMAT_CONNECTX_7   = 2,
1631 	MLX5_STEERING_FORMAT_CONNECTX_8   = 3,
1632 };
1633 
1634 struct mlx5_ifc_cmd_hca_cap_bits {
1635 	u8         reserved_at_0[0x6];
1636 	u8         page_request_disable[0x1];
1637 	u8         abs_native_port_num[0x1];
1638 	u8         reserved_at_8[0x8];
1639 	u8         shared_object_to_user_object_allowed[0x1];
1640 	u8         reserved_at_13[0xe];
1641 	u8         vhca_resource_manager[0x1];
1642 
1643 	u8         hca_cap_2[0x1];
1644 	u8         create_lag_when_not_master_up[0x1];
1645 	u8         dtor[0x1];
1646 	u8         event_on_vhca_state_teardown_request[0x1];
1647 	u8         event_on_vhca_state_in_use[0x1];
1648 	u8         event_on_vhca_state_active[0x1];
1649 	u8         event_on_vhca_state_allocated[0x1];
1650 	u8         event_on_vhca_state_invalid[0x1];
1651 	u8         reserved_at_28[0x8];
1652 	u8         vhca_id[0x10];
1653 
1654 	u8         reserved_at_40[0x40];
1655 
1656 	u8         log_max_srq_sz[0x8];
1657 	u8         log_max_qp_sz[0x8];
1658 	u8         event_cap[0x1];
1659 	u8         reserved_at_91[0x2];
1660 	u8         isolate_vl_tc_new[0x1];
1661 	u8         reserved_at_94[0x4];
1662 	u8         prio_tag_required[0x1];
1663 	u8         reserved_at_99[0x2];
1664 	u8         log_max_qp[0x5];
1665 
1666 	u8         reserved_at_a0[0x3];
1667 	u8	   ece_support[0x1];
1668 	u8	   reserved_at_a4[0x5];
1669 	u8         reg_c_preserve[0x1];
1670 	u8         reserved_at_aa[0x1];
1671 	u8         log_max_srq[0x5];
1672 	u8         reserved_at_b0[0x1];
1673 	u8         uplink_follow[0x1];
1674 	u8         ts_cqe_to_dest_cqn[0x1];
1675 	u8         reserved_at_b3[0x6];
1676 	u8         go_back_n[0x1];
1677 	u8         reserved_at_ba[0x6];
1678 
1679 	u8         max_sgl_for_optimized_performance[0x8];
1680 	u8         log_max_cq_sz[0x8];
1681 	u8         relaxed_ordering_write_umr[0x1];
1682 	u8         relaxed_ordering_read_umr[0x1];
1683 	u8         reserved_at_d2[0x7];
1684 	u8         virtio_net_device_emualtion_manager[0x1];
1685 	u8         virtio_blk_device_emualtion_manager[0x1];
1686 	u8         log_max_cq[0x5];
1687 
1688 	u8         log_max_eq_sz[0x8];
1689 	u8         relaxed_ordering_write[0x1];
1690 	u8         relaxed_ordering_read_pci_enabled[0x1];
1691 	u8         log_max_mkey[0x6];
1692 	u8         reserved_at_f0[0x6];
1693 	u8	   terminate_scatter_list_mkey[0x1];
1694 	u8	   repeated_mkey[0x1];
1695 	u8         dump_fill_mkey[0x1];
1696 	u8         reserved_at_f9[0x2];
1697 	u8         fast_teardown[0x1];
1698 	u8         log_max_eq[0x4];
1699 
1700 	u8         max_indirection[0x8];
1701 	u8         fixed_buffer_size[0x1];
1702 	u8         log_max_mrw_sz[0x7];
1703 	u8         force_teardown[0x1];
1704 	u8         reserved_at_111[0x1];
1705 	u8         log_max_bsf_list_size[0x6];
1706 	u8         umr_extended_translation_offset[0x1];
1707 	u8         null_mkey[0x1];
1708 	u8         log_max_klm_list_size[0x6];
1709 
1710 	u8         reserved_at_120[0x2];
1711 	u8	   qpc_extension[0x1];
1712 	u8	   reserved_at_123[0x7];
1713 	u8         log_max_ra_req_dc[0x6];
1714 	u8         reserved_at_130[0x2];
1715 	u8         eth_wqe_too_small[0x1];
1716 	u8         reserved_at_133[0x6];
1717 	u8         vnic_env_cq_overrun[0x1];
1718 	u8         log_max_ra_res_dc[0x6];
1719 
1720 	u8         reserved_at_140[0x5];
1721 	u8         release_all_pages[0x1];
1722 	u8         must_not_use[0x1];
1723 	u8         reserved_at_147[0x2];
1724 	u8         roce_accl[0x1];
1725 	u8         log_max_ra_req_qp[0x6];
1726 	u8         reserved_at_150[0xa];
1727 	u8         log_max_ra_res_qp[0x6];
1728 
1729 	u8         end_pad[0x1];
1730 	u8         cc_query_allowed[0x1];
1731 	u8         cc_modify_allowed[0x1];
1732 	u8         start_pad[0x1];
1733 	u8         cache_line_128byte[0x1];
1734 	u8         reserved_at_165[0x4];
1735 	u8         rts2rts_qp_counters_set_id[0x1];
1736 	u8         reserved_at_16a[0x2];
1737 	u8         vnic_env_int_rq_oob[0x1];
1738 	u8         sbcam_reg[0x1];
1739 	u8         reserved_at_16e[0x1];
1740 	u8         qcam_reg[0x1];
1741 	u8         gid_table_size[0x10];
1742 
1743 	u8         out_of_seq_cnt[0x1];
1744 	u8         vport_counters[0x1];
1745 	u8         retransmission_q_counters[0x1];
1746 	u8         debug[0x1];
1747 	u8         modify_rq_counter_set_id[0x1];
1748 	u8         rq_delay_drop[0x1];
1749 	u8         max_qp_cnt[0xa];
1750 	u8         pkey_table_size[0x10];
1751 
1752 	u8         vport_group_manager[0x1];
1753 	u8         vhca_group_manager[0x1];
1754 	u8         ib_virt[0x1];
1755 	u8         eth_virt[0x1];
1756 	u8         vnic_env_queue_counters[0x1];
1757 	u8         ets[0x1];
1758 	u8         nic_flow_table[0x1];
1759 	u8         eswitch_manager[0x1];
1760 	u8         device_memory[0x1];
1761 	u8         mcam_reg[0x1];
1762 	u8         pcam_reg[0x1];
1763 	u8         local_ca_ack_delay[0x5];
1764 	u8         port_module_event[0x1];
1765 	u8         enhanced_error_q_counters[0x1];
1766 	u8         ports_check[0x1];
1767 	u8         reserved_at_1b3[0x1];
1768 	u8         disable_link_up[0x1];
1769 	u8         beacon_led[0x1];
1770 	u8         port_type[0x2];
1771 	u8         num_ports[0x8];
1772 
1773 	u8         reserved_at_1c0[0x1];
1774 	u8         pps[0x1];
1775 	u8         pps_modify[0x1];
1776 	u8         log_max_msg[0x5];
1777 	u8         reserved_at_1c8[0x4];
1778 	u8         max_tc[0x4];
1779 	u8         temp_warn_event[0x1];
1780 	u8         dcbx[0x1];
1781 	u8         general_notification_event[0x1];
1782 	u8         reserved_at_1d3[0x2];
1783 	u8         fpga[0x1];
1784 	u8         rol_s[0x1];
1785 	u8         rol_g[0x1];
1786 	u8         reserved_at_1d8[0x1];
1787 	u8         wol_s[0x1];
1788 	u8         wol_g[0x1];
1789 	u8         wol_a[0x1];
1790 	u8         wol_b[0x1];
1791 	u8         wol_m[0x1];
1792 	u8         wol_u[0x1];
1793 	u8         wol_p[0x1];
1794 
1795 	u8         stat_rate_support[0x10];
1796 	u8         reserved_at_1f0[0x1];
1797 	u8         pci_sync_for_fw_update_event[0x1];
1798 	u8         reserved_at_1f2[0x6];
1799 	u8         init2_lag_tx_port_affinity[0x1];
1800 	u8         reserved_at_1fa[0x2];
1801 	u8         wqe_based_flow_table_update_cap[0x1];
1802 	u8         cqe_version[0x4];
1803 
1804 	u8         compact_address_vector[0x1];
1805 	u8         striding_rq[0x1];
1806 	u8         reserved_at_202[0x1];
1807 	u8         ipoib_enhanced_offloads[0x1];
1808 	u8         ipoib_basic_offloads[0x1];
1809 	u8         reserved_at_205[0x1];
1810 	u8         repeated_block_disabled[0x1];
1811 	u8         umr_modify_entity_size_disabled[0x1];
1812 	u8         umr_modify_atomic_disabled[0x1];
1813 	u8         umr_indirect_mkey_disabled[0x1];
1814 	u8         umr_fence[0x2];
1815 	u8         dc_req_scat_data_cqe[0x1];
1816 	u8         reserved_at_20d[0x2];
1817 	u8         drain_sigerr[0x1];
1818 	u8         cmdif_checksum[0x2];
1819 	u8         sigerr_cqe[0x1];
1820 	u8         reserved_at_213[0x1];
1821 	u8         wq_signature[0x1];
1822 	u8         sctr_data_cqe[0x1];
1823 	u8         reserved_at_216[0x1];
1824 	u8         sho[0x1];
1825 	u8         tph[0x1];
1826 	u8         rf[0x1];
1827 	u8         dct[0x1];
1828 	u8         qos[0x1];
1829 	u8         eth_net_offloads[0x1];
1830 	u8         roce[0x1];
1831 	u8         atomic[0x1];
1832 	u8         reserved_at_21f[0x1];
1833 
1834 	u8         cq_oi[0x1];
1835 	u8         cq_resize[0x1];
1836 	u8         cq_moderation[0x1];
1837 	u8         cq_period_mode_modify[0x1];
1838 	u8         reserved_at_224[0x2];
1839 	u8         cq_eq_remap[0x1];
1840 	u8         pg[0x1];
1841 	u8         block_lb_mc[0x1];
1842 	u8         reserved_at_229[0x1];
1843 	u8         scqe_break_moderation[0x1];
1844 	u8         cq_period_start_from_cqe[0x1];
1845 	u8         cd[0x1];
1846 	u8         reserved_at_22d[0x1];
1847 	u8         apm[0x1];
1848 	u8         vector_calc[0x1];
1849 	u8         umr_ptr_rlky[0x1];
1850 	u8	   imaicl[0x1];
1851 	u8	   qp_packet_based[0x1];
1852 	u8         reserved_at_233[0x3];
1853 	u8         qkv[0x1];
1854 	u8         pkv[0x1];
1855 	u8         set_deth_sqpn[0x1];
1856 	u8         reserved_at_239[0x3];
1857 	u8         xrc[0x1];
1858 	u8         ud[0x1];
1859 	u8         uc[0x1];
1860 	u8         rc[0x1];
1861 
1862 	u8         uar_4k[0x1];
1863 	u8         reserved_at_241[0x7];
1864 	u8         fl_rc_qp_when_roce_disabled[0x1];
1865 	u8         regexp_params[0x1];
1866 	u8         uar_sz[0x6];
1867 	u8         port_selection_cap[0x1];
1868 	u8         nic_cap_reg[0x1];
1869 	u8         umem_uid_0[0x1];
1870 	u8         reserved_at_253[0x5];
1871 	u8         log_pg_sz[0x8];
1872 
1873 	u8         bf[0x1];
1874 	u8         driver_version[0x1];
1875 	u8         pad_tx_eth_packet[0x1];
1876 	u8         reserved_at_263[0x3];
1877 	u8         mkey_by_name[0x1];
1878 	u8         reserved_at_267[0x4];
1879 
1880 	u8         log_bf_reg_size[0x5];
1881 
1882 	u8         disciplined_fr_counter[0x1];
1883 	u8         reserved_at_271[0x2];
1884 	u8	   qp_error_syndrome[0x1];
1885 	u8	   reserved_at_274[0x2];
1886 	u8         lag_dct[0x2];
1887 	u8         lag_tx_port_affinity[0x1];
1888 	u8         lag_native_fdb_selection[0x1];
1889 	u8         reserved_at_27a[0x1];
1890 	u8         lag_master[0x1];
1891 	u8         num_lag_ports[0x4];
1892 
1893 	u8         reserved_at_280[0x10];
1894 	u8         max_wqe_sz_sq[0x10];
1895 
1896 	u8         reserved_at_2a0[0x7];
1897 	u8         mkey_pcie_tph[0x1];
1898 	u8         reserved_at_2a8[0x2];
1899 
1900 	u8         psp[0x1];
1901 	u8         shampo[0x1];
1902 	u8         reserved_at_2ac[0x4];
1903 	u8         max_wqe_sz_rq[0x10];
1904 
1905 	u8         max_flow_counter_31_16[0x10];
1906 	u8         max_wqe_sz_sq_dc[0x10];
1907 
1908 	u8         reserved_at_2e0[0x7];
1909 	u8         max_qp_mcg[0x19];
1910 
1911 	u8         reserved_at_300[0x10];
1912 	u8         flow_counter_bulk_alloc[0x8];
1913 	u8         log_max_mcg[0x8];
1914 
1915 	u8         reserved_at_320[0x3];
1916 	u8         log_max_transport_domain[0x5];
1917 	u8         reserved_at_328[0x2];
1918 	u8	   relaxed_ordering_read[0x1];
1919 	u8         log_max_pd[0x5];
1920 	u8         dp_ordering_ooo_all_ud[0x1];
1921 	u8         dp_ordering_ooo_all_uc[0x1];
1922 	u8         dp_ordering_ooo_all_xrc[0x1];
1923 	u8         dp_ordering_ooo_all_dc[0x1];
1924 	u8         dp_ordering_ooo_all_rc[0x1];
1925 	u8         pcie_reset_using_hotreset_method[0x1];
1926 	u8         pci_sync_for_fw_update_with_driver_unload[0x1];
1927 	u8         vnic_env_cnt_steering_fail[0x1];
1928 	u8         vport_counter_local_loopback[0x1];
1929 	u8         q_counter_aggregation[0x1];
1930 	u8         q_counter_other_vport[0x1];
1931 	u8         log_max_xrcd[0x5];
1932 
1933 	u8         nic_receive_steering_discard[0x1];
1934 	u8         receive_discard_vport_down[0x1];
1935 	u8         transmit_discard_vport_down[0x1];
1936 	u8         eq_overrun_count[0x1];
1937 	u8         reserved_at_344[0x1];
1938 	u8         invalid_command_count[0x1];
1939 	u8         quota_exceeded_count[0x1];
1940 	u8         reserved_at_347[0x1];
1941 	u8         log_max_flow_counter_bulk[0x8];
1942 	u8         max_flow_counter_15_0[0x10];
1943 
1944 
1945 	u8         reserved_at_360[0x3];
1946 	u8         log_max_rq[0x5];
1947 	u8         reserved_at_368[0x3];
1948 	u8         log_max_sq[0x5];
1949 	u8         reserved_at_370[0x3];
1950 	u8         log_max_tir[0x5];
1951 	u8         reserved_at_378[0x3];
1952 	u8         log_max_tis[0x5];
1953 
1954 	u8         basic_cyclic_rcv_wqe[0x1];
1955 	u8         reserved_at_381[0x2];
1956 	u8         log_max_rmp[0x5];
1957 	u8         reserved_at_388[0x3];
1958 	u8         log_max_rqt[0x5];
1959 	u8         reserved_at_390[0x3];
1960 	u8         log_max_rqt_size[0x5];
1961 	u8         reserved_at_398[0x3];
1962 	u8         log_max_tis_per_sq[0x5];
1963 
1964 	u8         ext_stride_num_range[0x1];
1965 	u8         roce_rw_supported[0x1];
1966 	u8         log_max_current_uc_list_wr_supported[0x1];
1967 	u8         log_max_stride_sz_rq[0x5];
1968 	u8         reserved_at_3a8[0x3];
1969 	u8         log_min_stride_sz_rq[0x5];
1970 	u8         reserved_at_3b0[0x3];
1971 	u8         log_max_stride_sz_sq[0x5];
1972 	u8         reserved_at_3b8[0x3];
1973 	u8         log_min_stride_sz_sq[0x5];
1974 
1975 	u8         hairpin[0x1];
1976 	u8         reserved_at_3c1[0x2];
1977 	u8         log_max_hairpin_queues[0x5];
1978 	u8         reserved_at_3c8[0x3];
1979 	u8         log_max_hairpin_wq_data_sz[0x5];
1980 	u8         reserved_at_3d0[0x3];
1981 	u8         log_max_hairpin_num_packets[0x5];
1982 	u8         reserved_at_3d8[0x3];
1983 	u8         log_max_wq_sz[0x5];
1984 
1985 	u8         nic_vport_change_event[0x1];
1986 	u8         disable_local_lb_uc[0x1];
1987 	u8         disable_local_lb_mc[0x1];
1988 	u8         log_min_hairpin_wq_data_sz[0x5];
1989 	u8         reserved_at_3e8[0x1];
1990 	u8         silent_mode[0x1];
1991 	u8         vhca_state[0x1];
1992 	u8         log_max_vlan_list[0x5];
1993 	u8         reserved_at_3f0[0x3];
1994 	u8         log_max_current_mc_list[0x5];
1995 	u8         reserved_at_3f8[0x3];
1996 	u8         log_max_current_uc_list[0x5];
1997 
1998 	u8         general_obj_types[0x40];
1999 
2000 	u8         sq_ts_format[0x2];
2001 	u8         rq_ts_format[0x2];
2002 	u8         steering_format_version[0x4];
2003 	u8         create_qp_start_hint[0x18];
2004 
2005 	u8         reserved_at_460[0x1];
2006 	u8         ats[0x1];
2007 	u8         cross_vhca_rqt[0x1];
2008 	u8         log_max_uctx[0x5];
2009 	u8         reserved_at_468[0x1];
2010 	u8         crypto[0x1];
2011 	u8         ipsec_offload[0x1];
2012 	u8         log_max_umem[0x5];
2013 	u8         max_num_eqs[0x10];
2014 
2015 	u8         reserved_at_480[0x1];
2016 	u8         tls_tx[0x1];
2017 	u8         tls_rx[0x1];
2018 	u8         log_max_l2_table[0x5];
2019 	u8         reserved_at_488[0x8];
2020 	u8         log_uar_page_sz[0x10];
2021 
2022 	u8         reserved_at_4a0[0x20];
2023 	u8         device_frequency_mhz[0x20];
2024 	u8         device_frequency_khz[0x20];
2025 
2026 	u8         reserved_at_500[0x20];
2027 	u8	   num_of_uars_per_page[0x20];
2028 
2029 	u8         flex_parser_protocols[0x20];
2030 
2031 	u8         max_geneve_tlv_options[0x8];
2032 	u8         reserved_at_568[0x3];
2033 	u8         max_geneve_tlv_option_data_len[0x5];
2034 	u8         reserved_at_570[0x1];
2035 	u8         adv_rdma[0x1];
2036 	u8         reserved_at_572[0x7];
2037 	u8         adv_virtualization[0x1];
2038 	u8         reserved_at_57a[0x6];
2039 
2040 	u8	   reserved_at_580[0xb];
2041 	u8	   log_max_dci_stream_channels[0x5];
2042 	u8	   reserved_at_590[0x3];
2043 	u8	   log_max_dci_errored_streams[0x5];
2044 	u8	   reserved_at_598[0x8];
2045 
2046 	u8         reserved_at_5a0[0x10];
2047 	u8         enhanced_cqe_compression[0x1];
2048 	u8         reserved_at_5b1[0x1];
2049 	u8         crossing_vhca_mkey[0x1];
2050 	u8         log_max_dek[0x5];
2051 	u8         reserved_at_5b8[0x4];
2052 	u8         mini_cqe_resp_stride_index[0x1];
2053 	u8         cqe_128_always[0x1];
2054 	u8         cqe_compression_128[0x1];
2055 	u8         cqe_compression[0x1];
2056 
2057 	u8         cqe_compression_timeout[0x10];
2058 	u8         cqe_compression_max_num[0x10];
2059 
2060 	u8         reserved_at_5e0[0x8];
2061 	u8         flex_parser_id_gtpu_dw_0[0x4];
2062 	u8         reserved_at_5ec[0x4];
2063 	u8         tag_matching[0x1];
2064 	u8         rndv_offload_rc[0x1];
2065 	u8         rndv_offload_dc[0x1];
2066 	u8         log_tag_matching_list_sz[0x5];
2067 	u8         reserved_at_5f8[0x3];
2068 	u8         log_max_xrq[0x5];
2069 
2070 	u8	   affiliate_nic_vport_criteria[0x8];
2071 	u8	   native_port_num[0x8];
2072 	u8	   num_vhca_ports[0x8];
2073 	u8         flex_parser_id_gtpu_teid[0x4];
2074 	u8         reserved_at_61c[0x2];
2075 	u8	   sw_owner_id[0x1];
2076 	u8         reserved_at_61f[0x1];
2077 
2078 	u8         max_num_of_monitor_counters[0x10];
2079 	u8         num_ppcnt_monitor_counters[0x10];
2080 
2081 	u8         max_num_sf[0x10];
2082 	u8         num_q_monitor_counters[0x10];
2083 
2084 	u8         reserved_at_660[0x20];
2085 
2086 	u8         sf[0x1];
2087 	u8         sf_set_partition[0x1];
2088 	u8         reserved_at_682[0x1];
2089 	u8         log_max_sf[0x5];
2090 	u8         apu[0x1];
2091 	u8         reserved_at_689[0x4];
2092 	u8         migration[0x1];
2093 	u8         reserved_at_68e[0x2];
2094 	u8         log_min_sf_size[0x8];
2095 	u8         max_num_sf_partitions[0x8];
2096 
2097 	u8         uctx_cap[0x20];
2098 
2099 	u8         reserved_at_6c0[0x4];
2100 	u8         flex_parser_id_geneve_tlv_option_0[0x4];
2101 	u8         flex_parser_id_icmp_dw1[0x4];
2102 	u8         flex_parser_id_icmp_dw0[0x4];
2103 	u8         flex_parser_id_icmpv6_dw1[0x4];
2104 	u8         flex_parser_id_icmpv6_dw0[0x4];
2105 	u8         flex_parser_id_outer_first_mpls_over_gre[0x4];
2106 	u8         flex_parser_id_outer_first_mpls_over_udp_label[0x4];
2107 
2108 	u8         max_num_match_definer[0x10];
2109 	u8	   sf_base_id[0x10];
2110 
2111 	u8         flex_parser_id_gtpu_dw_2[0x4];
2112 	u8         flex_parser_id_gtpu_first_ext_dw_0[0x4];
2113 	u8	   num_total_dynamic_vf_msix[0x18];
2114 	u8	   reserved_at_720[0x14];
2115 	u8	   dynamic_msix_table_size[0xc];
2116 	u8	   reserved_at_740[0xc];
2117 	u8	   min_dynamic_vf_msix_table_size[0x4];
2118 	u8	   reserved_at_750[0x2];
2119 	u8	   data_direct[0x1];
2120 	u8	   reserved_at_753[0x1];
2121 	u8	   max_dynamic_vf_msix_table_size[0xc];
2122 
2123 	u8         reserved_at_760[0x3];
2124 	u8         log_max_num_header_modify_argument[0x5];
2125 	u8         log_header_modify_argument_granularity_offset[0x4];
2126 	u8         log_header_modify_argument_granularity[0x4];
2127 	u8         reserved_at_770[0x3];
2128 	u8         log_header_modify_argument_max_alloc[0x5];
2129 	u8         reserved_at_778[0x8];
2130 
2131 	u8	   vhca_tunnel_commands[0x40];
2132 	u8         match_definer_format_supported[0x40];
2133 };
2134 
2135 enum {
2136 	MLX5_CROSS_VHCA_OBJ_TO_OBJ_SUPPORTED_LOCAL_FLOW_TABLE_TO_REMOTE_FLOW_TABLE_MISS  = 0x80000,
2137 	MLX5_CROSS_VHCA_OBJ_TO_OBJ_SUPPORTED_LOCAL_FLOW_TABLE_ROOT_TO_REMOTE_FLOW_TABLE  = (1ULL << 20),
2138 };
2139 
2140 enum {
2141 	MLX5_ALLOWED_OBJ_FOR_OTHER_VHCA_ACCESS_FLOW_TABLE       = 0x200,
2142 };
2143 
2144 struct mlx5_ifc_cmd_hca_cap_2_bits {
2145 	u8	   reserved_at_0[0x80];
2146 
2147 	u8         migratable[0x1];
2148 	u8         reserved_at_81[0x7];
2149 	u8         dp_ordering_force[0x1];
2150 	u8         reserved_at_89[0x9];
2151 	u8         query_vuid[0x1];
2152 	u8         reserved_at_93[0x5];
2153 	u8         umr_log_entity_size_5[0x1];
2154 	u8         reserved_at_99[0x7];
2155 
2156 	u8	   max_reformat_insert_size[0x8];
2157 	u8	   max_reformat_insert_offset[0x8];
2158 	u8	   max_reformat_remove_size[0x8];
2159 	u8	   max_reformat_remove_offset[0x8];
2160 
2161 	u8	   reserved_at_c0[0x8];
2162 	u8	   migration_multi_load[0x1];
2163 	u8	   migration_tracking_state[0x1];
2164 	u8	   multiplane_qp_ud[0x1];
2165 	u8	   reserved_at_cb[0x5];
2166 	u8	   migration_in_chunks[0x1];
2167 	u8	   reserved_at_d1[0x1];
2168 	u8	   sf_eq_usage[0x1];
2169 	u8	   reserved_at_d3[0x5];
2170 	u8	   multiplane[0x1];
2171 	u8	   reserved_at_d9[0x7];
2172 
2173 	u8	   cross_vhca_object_to_object_supported[0x20];
2174 
2175 	u8	   allowed_object_for_other_vhca_access[0x40];
2176 
2177 	u8	   reserved_at_140[0x60];
2178 
2179 	u8	   flow_table_type_2_type[0x8];
2180 	u8	   reserved_at_1a8[0x2];
2181 	u8         format_select_dw_8_6_ext[0x1];
2182 	u8	   log_min_mkey_entity_size[0x5];
2183 	u8	   reserved_at_1b0[0x10];
2184 
2185 	u8	   general_obj_types_127_64[0x40];
2186 	u8	   reserved_at_200[0x20];
2187 
2188 	u8	   reserved_at_220[0x1];
2189 	u8	   sw_vhca_id_valid[0x1];
2190 	u8	   sw_vhca_id[0xe];
2191 	u8	   reserved_at_230[0x10];
2192 
2193 	u8	   reserved_at_240[0xb];
2194 	u8	   ts_cqe_metadata_size2wqe_counter[0x5];
2195 	u8	   reserved_at_250[0x10];
2196 
2197 	u8	   reserved_at_260[0x20];
2198 
2199 	u8	   format_select_dw_gtpu_dw_0[0x8];
2200 	u8	   format_select_dw_gtpu_dw_1[0x8];
2201 	u8	   format_select_dw_gtpu_dw_2[0x8];
2202 	u8	   format_select_dw_gtpu_first_ext_dw_0[0x8];
2203 
2204 	u8	   generate_wqe_type[0x20];
2205 
2206 	u8	   reserved_at_2c0[0xc0];
2207 
2208 	u8	   reserved_at_380[0xb];
2209 	u8	   min_mkey_log_entity_size_fixed_buffer[0x5];
2210 	u8	   ec_vf_vport_base[0x10];
2211 
2212 	u8	   reserved_at_3a0[0x2];
2213 	u8	   max_mkey_log_entity_size_fixed_buffer[0x6];
2214 	u8	   reserved_at_3a8[0x2];
2215 	u8	   max_mkey_log_entity_size_mtt[0x6];
2216 	u8	   max_rqt_vhca_id[0x10];
2217 
2218 	u8	   reserved_at_3c0[0x20];
2219 
2220 	u8	   reserved_at_3e0[0x10];
2221 	u8	   pcc_ifa2[0x1];
2222 	u8	   reserved_at_3f1[0xf];
2223 
2224 	u8	   reserved_at_400[0x1];
2225 	u8	   min_mkey_log_entity_size_fixed_buffer_valid[0x1];
2226 	u8	   reserved_at_402[0xe];
2227 	u8	   return_reg_id[0x10];
2228 
2229 	u8	   reserved_at_420[0x1c];
2230 	u8	   flow_table_hash_type[0x4];
2231 
2232 	u8	   reserved_at_440[0x8];
2233 	u8	   max_num_eqs_24b[0x18];
2234 
2235 	u8         reserved_at_460[0x160];
2236 
2237 	u8         query_adjacent_functions_id[0x1];
2238 	u8         ingress_egress_esw_vport_connect[0x1];
2239 	u8         function_id_type_vhca_id[0x1];
2240 	u8         reserved_at_5c3[0xd];
2241 	u8         delegate_vhca_management_profiles[0x10];
2242 
2243 	u8         delegated_vhca_max[0x10];
2244 	u8         delegate_vhca_max[0x10];
2245 
2246 	u8         reserved_at_600[0x200];
2247 };
2248 
2249 enum mlx5_ifc_flow_destination_type {
2250 	MLX5_IFC_FLOW_DESTINATION_TYPE_VPORT        = 0x0,
2251 	MLX5_IFC_FLOW_DESTINATION_TYPE_FLOW_TABLE   = 0x1,
2252 	MLX5_IFC_FLOW_DESTINATION_TYPE_TIR          = 0x2,
2253 	MLX5_IFC_FLOW_DESTINATION_TYPE_FLOW_SAMPLER = 0x6,
2254 	MLX5_IFC_FLOW_DESTINATION_TYPE_UPLINK       = 0x8,
2255 	MLX5_IFC_FLOW_DESTINATION_TYPE_TABLE_TYPE   = 0xA,
2256 };
2257 
2258 enum mlx5_flow_table_miss_action {
2259 	MLX5_FLOW_TABLE_MISS_ACTION_DEF,
2260 	MLX5_FLOW_TABLE_MISS_ACTION_FWD,
2261 	MLX5_FLOW_TABLE_MISS_ACTION_SWITCH_DOMAIN,
2262 };
2263 
2264 struct mlx5_ifc_dest_format_struct_bits {
2265 	u8         destination_type[0x8];
2266 	u8         destination_id[0x18];
2267 
2268 	u8         destination_eswitch_owner_vhca_id_valid[0x1];
2269 	u8         packet_reformat[0x1];
2270 	u8         reserved_at_22[0x6];
2271 	u8         destination_table_type[0x8];
2272 	u8         destination_eswitch_owner_vhca_id[0x10];
2273 };
2274 
2275 struct mlx5_ifc_flow_counter_list_bits {
2276 	u8         flow_counter_id[0x20];
2277 
2278 	u8         reserved_at_20[0x20];
2279 };
2280 
2281 struct mlx5_ifc_extended_dest_format_bits {
2282 	struct mlx5_ifc_dest_format_struct_bits destination_entry;
2283 
2284 	u8         packet_reformat_id[0x20];
2285 
2286 	u8         reserved_at_60[0x20];
2287 };
2288 
2289 union mlx5_ifc_dest_format_flow_counter_list_auto_bits {
2290 	struct mlx5_ifc_extended_dest_format_bits extended_dest_format;
2291 	struct mlx5_ifc_flow_counter_list_bits flow_counter_list;
2292 };
2293 
2294 struct mlx5_ifc_fte_match_param_bits {
2295 	struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
2296 
2297 	struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
2298 
2299 	struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
2300 
2301 	struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2;
2302 
2303 	struct mlx5_ifc_fte_match_set_misc3_bits misc_parameters_3;
2304 
2305 	struct mlx5_ifc_fte_match_set_misc4_bits misc_parameters_4;
2306 
2307 	struct mlx5_ifc_fte_match_set_misc5_bits misc_parameters_5;
2308 
2309 	u8         reserved_at_e00[0x200];
2310 };
2311 
2312 enum {
2313 	MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP     = 0x0,
2314 	MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP     = 0x1,
2315 	MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT   = 0x2,
2316 	MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT   = 0x3,
2317 	MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI  = 0x4,
2318 };
2319 
2320 struct mlx5_ifc_rx_hash_field_select_bits {
2321 	u8         l3_prot_type[0x1];
2322 	u8         l4_prot_type[0x1];
2323 	u8         selected_fields[0x1e];
2324 };
2325 
2326 enum {
2327 	MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST  = 0x0,
2328 	MLX5_WQ_WQ_TYPE_WQ_CYCLIC       = 0x1,
2329 };
2330 
2331 enum {
2332 	MLX5_WQ_END_PADDING_MODE_END_PAD_NONE   = 0x0,
2333 	MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN  = 0x1,
2334 };
2335 
2336 struct mlx5_ifc_wq_bits {
2337 	u8         wq_type[0x4];
2338 	u8         wq_signature[0x1];
2339 	u8         end_padding_mode[0x2];
2340 	u8         cd_slave[0x1];
2341 	u8         reserved_at_8[0x18];
2342 
2343 	u8         hds_skip_first_sge[0x1];
2344 	u8         log2_hds_buf_size[0x3];
2345 	u8         reserved_at_24[0x7];
2346 	u8         page_offset[0x5];
2347 	u8         lwm[0x10];
2348 
2349 	u8         reserved_at_40[0x8];
2350 	u8         pd[0x18];
2351 
2352 	u8         reserved_at_60[0x8];
2353 	u8         uar_page[0x18];
2354 
2355 	u8         dbr_addr[0x40];
2356 
2357 	u8         hw_counter[0x20];
2358 
2359 	u8         sw_counter[0x20];
2360 
2361 	u8         reserved_at_100[0xc];
2362 	u8         log_wq_stride[0x4];
2363 	u8         reserved_at_110[0x3];
2364 	u8         log_wq_pg_sz[0x5];
2365 	u8         reserved_at_118[0x3];
2366 	u8         log_wq_sz[0x5];
2367 
2368 	u8         dbr_umem_valid[0x1];
2369 	u8         wq_umem_valid[0x1];
2370 	u8         reserved_at_122[0x1];
2371 	u8         log_hairpin_num_packets[0x5];
2372 	u8         reserved_at_128[0x3];
2373 	u8         log_hairpin_data_sz[0x5];
2374 
2375 	u8         reserved_at_130[0x4];
2376 	u8         log_wqe_num_of_strides[0x4];
2377 	u8         two_byte_shift_en[0x1];
2378 	u8         reserved_at_139[0x4];
2379 	u8         log_wqe_stride_size[0x3];
2380 
2381 	u8         dbr_umem_id[0x20];
2382 	u8         wq_umem_id[0x20];
2383 
2384 	u8         wq_umem_offset[0x40];
2385 
2386 	u8         headers_mkey[0x20];
2387 
2388 	u8         shampo_enable[0x1];
2389 	u8         reserved_at_1e1[0x1];
2390 	u8         shampo_mode[0x2];
2391 	u8         reserved_at_1e4[0x1];
2392 	u8         log_reservation_size[0x3];
2393 	u8         reserved_at_1e8[0x5];
2394 	u8         log_max_num_of_packets_per_reservation[0x3];
2395 	u8         reserved_at_1f0[0x6];
2396 	u8         log_headers_entry_size[0x2];
2397 	u8         reserved_at_1f8[0x4];
2398 	u8         log_headers_buffer_entry_num[0x4];
2399 
2400 	u8         reserved_at_200[0x400];
2401 
2402 	struct mlx5_ifc_cmd_pas_bits pas[];
2403 };
2404 
2405 struct mlx5_ifc_rq_num_bits {
2406 	u8         reserved_at_0[0x8];
2407 	u8         rq_num[0x18];
2408 };
2409 
2410 struct mlx5_ifc_rq_vhca_bits {
2411 	u8         reserved_at_0[0x8];
2412 	u8         rq_num[0x18];
2413 	u8         reserved_at_20[0x10];
2414 	u8         rq_vhca_id[0x10];
2415 };
2416 
2417 struct mlx5_ifc_mac_address_layout_bits {
2418 	u8         reserved_at_0[0x10];
2419 	u8         mac_addr_47_32[0x10];
2420 
2421 	u8         mac_addr_31_0[0x20];
2422 };
2423 
2424 struct mlx5_ifc_vlan_layout_bits {
2425 	u8         reserved_at_0[0x14];
2426 	u8         vlan[0x0c];
2427 
2428 	u8         reserved_at_20[0x20];
2429 };
2430 
2431 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
2432 	u8         reserved_at_0[0xa0];
2433 
2434 	u8         min_time_between_cnps[0x20];
2435 
2436 	u8         reserved_at_c0[0x12];
2437 	u8         cnp_dscp[0x6];
2438 	u8         reserved_at_d8[0x4];
2439 	u8         cnp_prio_mode[0x1];
2440 	u8         cnp_802p_prio[0x3];
2441 
2442 	u8         reserved_at_e0[0x720];
2443 };
2444 
2445 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
2446 	u8         reserved_at_0[0x60];
2447 
2448 	u8         reserved_at_60[0x4];
2449 	u8         clamp_tgt_rate[0x1];
2450 	u8         reserved_at_65[0x3];
2451 	u8         clamp_tgt_rate_after_time_inc[0x1];
2452 	u8         reserved_at_69[0x17];
2453 
2454 	u8         reserved_at_80[0x20];
2455 
2456 	u8         rpg_time_reset[0x20];
2457 
2458 	u8         rpg_byte_reset[0x20];
2459 
2460 	u8         rpg_threshold[0x20];
2461 
2462 	u8         rpg_max_rate[0x20];
2463 
2464 	u8         rpg_ai_rate[0x20];
2465 
2466 	u8         rpg_hai_rate[0x20];
2467 
2468 	u8         rpg_gd[0x20];
2469 
2470 	u8         rpg_min_dec_fac[0x20];
2471 
2472 	u8         rpg_min_rate[0x20];
2473 
2474 	u8         reserved_at_1c0[0xe0];
2475 
2476 	u8         rate_to_set_on_first_cnp[0x20];
2477 
2478 	u8         dce_tcp_g[0x20];
2479 
2480 	u8         dce_tcp_rtt[0x20];
2481 
2482 	u8         rate_reduce_monitor_period[0x20];
2483 
2484 	u8         reserved_at_320[0x20];
2485 
2486 	u8         initial_alpha_value[0x20];
2487 
2488 	u8         reserved_at_360[0x4a0];
2489 };
2490 
2491 struct mlx5_ifc_cong_control_r_roce_general_bits {
2492 	u8         reserved_at_0[0x80];
2493 
2494 	u8         reserved_at_80[0x10];
2495 	u8         rtt_resp_dscp_valid[0x1];
2496 	u8         reserved_at_91[0x9];
2497 	u8         rtt_resp_dscp[0x6];
2498 
2499 	u8         reserved_at_a0[0x760];
2500 };
2501 
2502 struct mlx5_ifc_cong_control_802_1qau_rp_bits {
2503 	u8         reserved_at_0[0x80];
2504 
2505 	u8         rppp_max_rps[0x20];
2506 
2507 	u8         rpg_time_reset[0x20];
2508 
2509 	u8         rpg_byte_reset[0x20];
2510 
2511 	u8         rpg_threshold[0x20];
2512 
2513 	u8         rpg_max_rate[0x20];
2514 
2515 	u8         rpg_ai_rate[0x20];
2516 
2517 	u8         rpg_hai_rate[0x20];
2518 
2519 	u8         rpg_gd[0x20];
2520 
2521 	u8         rpg_min_dec_fac[0x20];
2522 
2523 	u8         rpg_min_rate[0x20];
2524 
2525 	u8         reserved_at_1c0[0x640];
2526 };
2527 
2528 enum {
2529 	MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE    = 0x1,
2530 	MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET    = 0x2,
2531 	MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE  = 0x4,
2532 };
2533 
2534 struct mlx5_ifc_resize_field_select_bits {
2535 	u8         resize_field_select[0x20];
2536 };
2537 
2538 struct mlx5_ifc_resource_dump_bits {
2539 	u8         more_dump[0x1];
2540 	u8         inline_dump[0x1];
2541 	u8         reserved_at_2[0xa];
2542 	u8         seq_num[0x4];
2543 	u8         segment_type[0x10];
2544 
2545 	u8         reserved_at_20[0x10];
2546 	u8         vhca_id[0x10];
2547 
2548 	u8         index1[0x20];
2549 
2550 	u8         index2[0x20];
2551 
2552 	u8         num_of_obj1[0x10];
2553 	u8         num_of_obj2[0x10];
2554 
2555 	u8         reserved_at_a0[0x20];
2556 
2557 	u8         device_opaque[0x40];
2558 
2559 	u8         mkey[0x20];
2560 
2561 	u8         size[0x20];
2562 
2563 	u8         address[0x40];
2564 
2565 	u8         inline_data[52][0x20];
2566 };
2567 
2568 struct mlx5_ifc_resource_dump_menu_record_bits {
2569 	u8         reserved_at_0[0x4];
2570 	u8         num_of_obj2_supports_active[0x1];
2571 	u8         num_of_obj2_supports_all[0x1];
2572 	u8         must_have_num_of_obj2[0x1];
2573 	u8         support_num_of_obj2[0x1];
2574 	u8         num_of_obj1_supports_active[0x1];
2575 	u8         num_of_obj1_supports_all[0x1];
2576 	u8         must_have_num_of_obj1[0x1];
2577 	u8         support_num_of_obj1[0x1];
2578 	u8         must_have_index2[0x1];
2579 	u8         support_index2[0x1];
2580 	u8         must_have_index1[0x1];
2581 	u8         support_index1[0x1];
2582 	u8         segment_type[0x10];
2583 
2584 	u8         segment_name[4][0x20];
2585 
2586 	u8         index1_name[4][0x20];
2587 
2588 	u8         index2_name[4][0x20];
2589 };
2590 
2591 struct mlx5_ifc_resource_dump_segment_header_bits {
2592 	u8         length_dw[0x10];
2593 	u8         segment_type[0x10];
2594 };
2595 
2596 struct mlx5_ifc_resource_dump_command_segment_bits {
2597 	struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2598 
2599 	u8         segment_called[0x10];
2600 	u8         vhca_id[0x10];
2601 
2602 	u8         index1[0x20];
2603 
2604 	u8         index2[0x20];
2605 
2606 	u8         num_of_obj1[0x10];
2607 	u8         num_of_obj2[0x10];
2608 };
2609 
2610 struct mlx5_ifc_resource_dump_error_segment_bits {
2611 	struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2612 
2613 	u8         reserved_at_20[0x10];
2614 	u8         syndrome_id[0x10];
2615 
2616 	u8         reserved_at_40[0x40];
2617 
2618 	u8         error[8][0x20];
2619 };
2620 
2621 struct mlx5_ifc_resource_dump_info_segment_bits {
2622 	struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2623 
2624 	u8         reserved_at_20[0x18];
2625 	u8         dump_version[0x8];
2626 
2627 	u8         hw_version[0x20];
2628 
2629 	u8         fw_version[0x20];
2630 };
2631 
2632 struct mlx5_ifc_resource_dump_menu_segment_bits {
2633 	struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2634 
2635 	u8         reserved_at_20[0x10];
2636 	u8         num_of_records[0x10];
2637 
2638 	struct mlx5_ifc_resource_dump_menu_record_bits record[];
2639 };
2640 
2641 struct mlx5_ifc_resource_dump_resource_segment_bits {
2642 	struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2643 
2644 	u8         reserved_at_20[0x20];
2645 
2646 	u8         index1[0x20];
2647 
2648 	u8         index2[0x20];
2649 
2650 	u8         payload[][0x20];
2651 };
2652 
2653 struct mlx5_ifc_resource_dump_terminate_segment_bits {
2654 	struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2655 };
2656 
2657 struct mlx5_ifc_menu_resource_dump_response_bits {
2658 	struct mlx5_ifc_resource_dump_info_segment_bits info;
2659 	struct mlx5_ifc_resource_dump_command_segment_bits cmd;
2660 	struct mlx5_ifc_resource_dump_menu_segment_bits menu;
2661 	struct mlx5_ifc_resource_dump_terminate_segment_bits terminate;
2662 };
2663 
2664 enum {
2665 	MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD     = 0x1,
2666 	MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT  = 0x2,
2667 	MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI            = 0x4,
2668 	MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN         = 0x8,
2669 };
2670 
2671 struct mlx5_ifc_modify_field_select_bits {
2672 	u8         modify_field_select[0x20];
2673 };
2674 
2675 struct mlx5_ifc_field_select_r_roce_np_bits {
2676 	u8         field_select_r_roce_np[0x20];
2677 };
2678 
2679 struct mlx5_ifc_field_select_r_roce_rp_bits {
2680 	u8         field_select_r_roce_rp[0x20];
2681 };
2682 
2683 enum {
2684 	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS     = 0x4,
2685 	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET   = 0x8,
2686 	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET   = 0x10,
2687 	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD    = 0x20,
2688 	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE     = 0x40,
2689 	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE      = 0x80,
2690 	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE     = 0x100,
2691 	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD           = 0x200,
2692 	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC  = 0x400,
2693 	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE     = 0x800,
2694 };
2695 
2696 struct mlx5_ifc_field_select_802_1qau_rp_bits {
2697 	u8         field_select_8021qaurp[0x20];
2698 };
2699 
2700 struct mlx5_ifc_phys_layer_recovery_cntrs_bits {
2701 	u8         total_successful_recovery_events[0x20];
2702 
2703 	u8         reserved_at_20[0x7a0];
2704 };
2705 
2706 struct mlx5_ifc_phys_layer_cntrs_bits {
2707 	u8         time_since_last_clear_high[0x20];
2708 
2709 	u8         time_since_last_clear_low[0x20];
2710 
2711 	u8         symbol_errors_high[0x20];
2712 
2713 	u8         symbol_errors_low[0x20];
2714 
2715 	u8         sync_headers_errors_high[0x20];
2716 
2717 	u8         sync_headers_errors_low[0x20];
2718 
2719 	u8         edpl_bip_errors_lane0_high[0x20];
2720 
2721 	u8         edpl_bip_errors_lane0_low[0x20];
2722 
2723 	u8         edpl_bip_errors_lane1_high[0x20];
2724 
2725 	u8         edpl_bip_errors_lane1_low[0x20];
2726 
2727 	u8         edpl_bip_errors_lane2_high[0x20];
2728 
2729 	u8         edpl_bip_errors_lane2_low[0x20];
2730 
2731 	u8         edpl_bip_errors_lane3_high[0x20];
2732 
2733 	u8         edpl_bip_errors_lane3_low[0x20];
2734 
2735 	u8         fc_fec_corrected_blocks_lane0_high[0x20];
2736 
2737 	u8         fc_fec_corrected_blocks_lane0_low[0x20];
2738 
2739 	u8         fc_fec_corrected_blocks_lane1_high[0x20];
2740 
2741 	u8         fc_fec_corrected_blocks_lane1_low[0x20];
2742 
2743 	u8         fc_fec_corrected_blocks_lane2_high[0x20];
2744 
2745 	u8         fc_fec_corrected_blocks_lane2_low[0x20];
2746 
2747 	u8         fc_fec_corrected_blocks_lane3_high[0x20];
2748 
2749 	u8         fc_fec_corrected_blocks_lane3_low[0x20];
2750 
2751 	u8         fc_fec_uncorrectable_blocks_lane0_high[0x20];
2752 
2753 	u8         fc_fec_uncorrectable_blocks_lane0_low[0x20];
2754 
2755 	u8         fc_fec_uncorrectable_blocks_lane1_high[0x20];
2756 
2757 	u8         fc_fec_uncorrectable_blocks_lane1_low[0x20];
2758 
2759 	u8         fc_fec_uncorrectable_blocks_lane2_high[0x20];
2760 
2761 	u8         fc_fec_uncorrectable_blocks_lane2_low[0x20];
2762 
2763 	u8         fc_fec_uncorrectable_blocks_lane3_high[0x20];
2764 
2765 	u8         fc_fec_uncorrectable_blocks_lane3_low[0x20];
2766 
2767 	u8         rs_fec_corrected_blocks_high[0x20];
2768 
2769 	u8         rs_fec_corrected_blocks_low[0x20];
2770 
2771 	u8         rs_fec_uncorrectable_blocks_high[0x20];
2772 
2773 	u8         rs_fec_uncorrectable_blocks_low[0x20];
2774 
2775 	u8         rs_fec_no_errors_blocks_high[0x20];
2776 
2777 	u8         rs_fec_no_errors_blocks_low[0x20];
2778 
2779 	u8         rs_fec_single_error_blocks_high[0x20];
2780 
2781 	u8         rs_fec_single_error_blocks_low[0x20];
2782 
2783 	u8         rs_fec_corrected_symbols_total_high[0x20];
2784 
2785 	u8         rs_fec_corrected_symbols_total_low[0x20];
2786 
2787 	u8         rs_fec_corrected_symbols_lane0_high[0x20];
2788 
2789 	u8         rs_fec_corrected_symbols_lane0_low[0x20];
2790 
2791 	u8         rs_fec_corrected_symbols_lane1_high[0x20];
2792 
2793 	u8         rs_fec_corrected_symbols_lane1_low[0x20];
2794 
2795 	u8         rs_fec_corrected_symbols_lane2_high[0x20];
2796 
2797 	u8         rs_fec_corrected_symbols_lane2_low[0x20];
2798 
2799 	u8         rs_fec_corrected_symbols_lane3_high[0x20];
2800 
2801 	u8         rs_fec_corrected_symbols_lane3_low[0x20];
2802 
2803 	u8         link_down_events[0x20];
2804 
2805 	u8         successful_recovery_events[0x20];
2806 
2807 	u8         reserved_at_640[0x180];
2808 };
2809 
2810 struct mlx5_ifc_phys_layer_statistical_cntrs_bits {
2811 	u8         time_since_last_clear_high[0x20];
2812 
2813 	u8         time_since_last_clear_low[0x20];
2814 
2815 	u8         phy_received_bits_high[0x20];
2816 
2817 	u8         phy_received_bits_low[0x20];
2818 
2819 	u8         phy_symbol_errors_high[0x20];
2820 
2821 	u8         phy_symbol_errors_low[0x20];
2822 
2823 	u8         phy_corrected_bits_high[0x20];
2824 
2825 	u8         phy_corrected_bits_low[0x20];
2826 
2827 	u8         phy_corrected_bits_lane0_high[0x20];
2828 
2829 	u8         phy_corrected_bits_lane0_low[0x20];
2830 
2831 	u8         phy_corrected_bits_lane1_high[0x20];
2832 
2833 	u8         phy_corrected_bits_lane1_low[0x20];
2834 
2835 	u8         phy_corrected_bits_lane2_high[0x20];
2836 
2837 	u8         phy_corrected_bits_lane2_low[0x20];
2838 
2839 	u8         phy_corrected_bits_lane3_high[0x20];
2840 
2841 	u8         phy_corrected_bits_lane3_low[0x20];
2842 
2843 	u8         reserved_at_200[0x5c0];
2844 };
2845 
2846 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits {
2847 	u8	   symbol_error_counter[0x10];
2848 
2849 	u8         link_error_recovery_counter[0x8];
2850 
2851 	u8         link_downed_counter[0x8];
2852 
2853 	u8         port_rcv_errors[0x10];
2854 
2855 	u8         port_rcv_remote_physical_errors[0x10];
2856 
2857 	u8         port_rcv_switch_relay_errors[0x10];
2858 
2859 	u8         port_xmit_discards[0x10];
2860 
2861 	u8         port_xmit_constraint_errors[0x8];
2862 
2863 	u8         port_rcv_constraint_errors[0x8];
2864 
2865 	u8         reserved_at_70[0x8];
2866 
2867 	u8         link_overrun_errors[0x8];
2868 
2869 	u8	   reserved_at_80[0x10];
2870 
2871 	u8         vl_15_dropped[0x10];
2872 
2873 	u8	   reserved_at_a0[0x80];
2874 
2875 	u8         port_xmit_wait[0x20];
2876 };
2877 
2878 struct mlx5_ifc_ib_ext_port_cntrs_grp_data_layout_bits {
2879 	u8         reserved_at_0[0x300];
2880 
2881 	u8         port_xmit_data_high[0x20];
2882 
2883 	u8         port_xmit_data_low[0x20];
2884 
2885 	u8         port_rcv_data_high[0x20];
2886 
2887 	u8         port_rcv_data_low[0x20];
2888 
2889 	u8         port_xmit_pkts_high[0x20];
2890 
2891 	u8         port_xmit_pkts_low[0x20];
2892 
2893 	u8         port_rcv_pkts_high[0x20];
2894 
2895 	u8         port_rcv_pkts_low[0x20];
2896 
2897 	u8         reserved_at_400[0x80];
2898 
2899 	u8         port_unicast_xmit_pkts_high[0x20];
2900 
2901 	u8         port_unicast_xmit_pkts_low[0x20];
2902 
2903 	u8         port_multicast_xmit_pkts_high[0x20];
2904 
2905 	u8         port_multicast_xmit_pkts_low[0x20];
2906 
2907 	u8         port_unicast_rcv_pkts_high[0x20];
2908 
2909 	u8         port_unicast_rcv_pkts_low[0x20];
2910 
2911 	u8         port_multicast_rcv_pkts_high[0x20];
2912 
2913 	u8         port_multicast_rcv_pkts_low[0x20];
2914 
2915 	u8         reserved_at_580[0x240];
2916 };
2917 
2918 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits {
2919 	u8         transmit_queue_high[0x20];
2920 
2921 	u8         transmit_queue_low[0x20];
2922 
2923 	u8         no_buffer_discard_uc_high[0x20];
2924 
2925 	u8         no_buffer_discard_uc_low[0x20];
2926 
2927 	u8         reserved_at_80[0x740];
2928 };
2929 
2930 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits {
2931 	u8         wred_discard_high[0x20];
2932 
2933 	u8         wred_discard_low[0x20];
2934 
2935 	u8         ecn_marked_tc_high[0x20];
2936 
2937 	u8         ecn_marked_tc_low[0x20];
2938 
2939 	u8         reserved_at_80[0x740];
2940 };
2941 
2942 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
2943 	u8         rx_octets_high[0x20];
2944 
2945 	u8         rx_octets_low[0x20];
2946 
2947 	u8         reserved_at_40[0xc0];
2948 
2949 	u8         rx_frames_high[0x20];
2950 
2951 	u8         rx_frames_low[0x20];
2952 
2953 	u8         tx_octets_high[0x20];
2954 
2955 	u8         tx_octets_low[0x20];
2956 
2957 	u8         reserved_at_180[0xc0];
2958 
2959 	u8         tx_frames_high[0x20];
2960 
2961 	u8         tx_frames_low[0x20];
2962 
2963 	u8         rx_pause_high[0x20];
2964 
2965 	u8         rx_pause_low[0x20];
2966 
2967 	u8         rx_pause_duration_high[0x20];
2968 
2969 	u8         rx_pause_duration_low[0x20];
2970 
2971 	u8         tx_pause_high[0x20];
2972 
2973 	u8         tx_pause_low[0x20];
2974 
2975 	u8         tx_pause_duration_high[0x20];
2976 
2977 	u8         tx_pause_duration_low[0x20];
2978 
2979 	u8         rx_pause_transition_high[0x20];
2980 
2981 	u8         rx_pause_transition_low[0x20];
2982 
2983 	u8         rx_discards_high[0x20];
2984 
2985 	u8         rx_discards_low[0x20];
2986 
2987 	u8         device_stall_minor_watermark_cnt_high[0x20];
2988 
2989 	u8         device_stall_minor_watermark_cnt_low[0x20];
2990 
2991 	u8         device_stall_critical_watermark_cnt_high[0x20];
2992 
2993 	u8         device_stall_critical_watermark_cnt_low[0x20];
2994 
2995 	u8         reserved_at_480[0x340];
2996 };
2997 
2998 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
2999 	u8         port_transmit_wait_high[0x20];
3000 
3001 	u8         port_transmit_wait_low[0x20];
3002 
3003 	u8         reserved_at_40[0x100];
3004 
3005 	u8         rx_buffer_almost_full_high[0x20];
3006 
3007 	u8         rx_buffer_almost_full_low[0x20];
3008 
3009 	u8         rx_buffer_full_high[0x20];
3010 
3011 	u8         rx_buffer_full_low[0x20];
3012 
3013 	u8         rx_icrc_encapsulated_high[0x20];
3014 
3015 	u8         rx_icrc_encapsulated_low[0x20];
3016 
3017 	u8         reserved_at_200[0x5c0];
3018 };
3019 
3020 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
3021 	u8         dot3stats_alignment_errors_high[0x20];
3022 
3023 	u8         dot3stats_alignment_errors_low[0x20];
3024 
3025 	u8         dot3stats_fcs_errors_high[0x20];
3026 
3027 	u8         dot3stats_fcs_errors_low[0x20];
3028 
3029 	u8         dot3stats_single_collision_frames_high[0x20];
3030 
3031 	u8         dot3stats_single_collision_frames_low[0x20];
3032 
3033 	u8         dot3stats_multiple_collision_frames_high[0x20];
3034 
3035 	u8         dot3stats_multiple_collision_frames_low[0x20];
3036 
3037 	u8         dot3stats_sqe_test_errors_high[0x20];
3038 
3039 	u8         dot3stats_sqe_test_errors_low[0x20];
3040 
3041 	u8         dot3stats_deferred_transmissions_high[0x20];
3042 
3043 	u8         dot3stats_deferred_transmissions_low[0x20];
3044 
3045 	u8         dot3stats_late_collisions_high[0x20];
3046 
3047 	u8         dot3stats_late_collisions_low[0x20];
3048 
3049 	u8         dot3stats_excessive_collisions_high[0x20];
3050 
3051 	u8         dot3stats_excessive_collisions_low[0x20];
3052 
3053 	u8         dot3stats_internal_mac_transmit_errors_high[0x20];
3054 
3055 	u8         dot3stats_internal_mac_transmit_errors_low[0x20];
3056 
3057 	u8         dot3stats_carrier_sense_errors_high[0x20];
3058 
3059 	u8         dot3stats_carrier_sense_errors_low[0x20];
3060 
3061 	u8         dot3stats_frame_too_longs_high[0x20];
3062 
3063 	u8         dot3stats_frame_too_longs_low[0x20];
3064 
3065 	u8         dot3stats_internal_mac_receive_errors_high[0x20];
3066 
3067 	u8         dot3stats_internal_mac_receive_errors_low[0x20];
3068 
3069 	u8         dot3stats_symbol_errors_high[0x20];
3070 
3071 	u8         dot3stats_symbol_errors_low[0x20];
3072 
3073 	u8         dot3control_in_unknown_opcodes_high[0x20];
3074 
3075 	u8         dot3control_in_unknown_opcodes_low[0x20];
3076 
3077 	u8         dot3in_pause_frames_high[0x20];
3078 
3079 	u8         dot3in_pause_frames_low[0x20];
3080 
3081 	u8         dot3out_pause_frames_high[0x20];
3082 
3083 	u8         dot3out_pause_frames_low[0x20];
3084 
3085 	u8         reserved_at_400[0x3c0];
3086 };
3087 
3088 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
3089 	u8         ether_stats_drop_events_high[0x20];
3090 
3091 	u8         ether_stats_drop_events_low[0x20];
3092 
3093 	u8         ether_stats_octets_high[0x20];
3094 
3095 	u8         ether_stats_octets_low[0x20];
3096 
3097 	u8         ether_stats_pkts_high[0x20];
3098 
3099 	u8         ether_stats_pkts_low[0x20];
3100 
3101 	u8         ether_stats_broadcast_pkts_high[0x20];
3102 
3103 	u8         ether_stats_broadcast_pkts_low[0x20];
3104 
3105 	u8         ether_stats_multicast_pkts_high[0x20];
3106 
3107 	u8         ether_stats_multicast_pkts_low[0x20];
3108 
3109 	u8         ether_stats_crc_align_errors_high[0x20];
3110 
3111 	u8         ether_stats_crc_align_errors_low[0x20];
3112 
3113 	u8         ether_stats_undersize_pkts_high[0x20];
3114 
3115 	u8         ether_stats_undersize_pkts_low[0x20];
3116 
3117 	u8         ether_stats_oversize_pkts_high[0x20];
3118 
3119 	u8         ether_stats_oversize_pkts_low[0x20];
3120 
3121 	u8         ether_stats_fragments_high[0x20];
3122 
3123 	u8         ether_stats_fragments_low[0x20];
3124 
3125 	u8         ether_stats_jabbers_high[0x20];
3126 
3127 	u8         ether_stats_jabbers_low[0x20];
3128 
3129 	u8         ether_stats_collisions_high[0x20];
3130 
3131 	u8         ether_stats_collisions_low[0x20];
3132 
3133 	u8         ether_stats_pkts64octets_high[0x20];
3134 
3135 	u8         ether_stats_pkts64octets_low[0x20];
3136 
3137 	u8         ether_stats_pkts65to127octets_high[0x20];
3138 
3139 	u8         ether_stats_pkts65to127octets_low[0x20];
3140 
3141 	u8         ether_stats_pkts128to255octets_high[0x20];
3142 
3143 	u8         ether_stats_pkts128to255octets_low[0x20];
3144 
3145 	u8         ether_stats_pkts256to511octets_high[0x20];
3146 
3147 	u8         ether_stats_pkts256to511octets_low[0x20];
3148 
3149 	u8         ether_stats_pkts512to1023octets_high[0x20];
3150 
3151 	u8         ether_stats_pkts512to1023octets_low[0x20];
3152 
3153 	u8         ether_stats_pkts1024to1518octets_high[0x20];
3154 
3155 	u8         ether_stats_pkts1024to1518octets_low[0x20];
3156 
3157 	u8         ether_stats_pkts1519to2047octets_high[0x20];
3158 
3159 	u8         ether_stats_pkts1519to2047octets_low[0x20];
3160 
3161 	u8         ether_stats_pkts2048to4095octets_high[0x20];
3162 
3163 	u8         ether_stats_pkts2048to4095octets_low[0x20];
3164 
3165 	u8         ether_stats_pkts4096to8191octets_high[0x20];
3166 
3167 	u8         ether_stats_pkts4096to8191octets_low[0x20];
3168 
3169 	u8         ether_stats_pkts8192to10239octets_high[0x20];
3170 
3171 	u8         ether_stats_pkts8192to10239octets_low[0x20];
3172 
3173 	u8         reserved_at_540[0x280];
3174 };
3175 
3176 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
3177 	u8         if_in_octets_high[0x20];
3178 
3179 	u8         if_in_octets_low[0x20];
3180 
3181 	u8         if_in_ucast_pkts_high[0x20];
3182 
3183 	u8         if_in_ucast_pkts_low[0x20];
3184 
3185 	u8         if_in_discards_high[0x20];
3186 
3187 	u8         if_in_discards_low[0x20];
3188 
3189 	u8         if_in_errors_high[0x20];
3190 
3191 	u8         if_in_errors_low[0x20];
3192 
3193 	u8         if_in_unknown_protos_high[0x20];
3194 
3195 	u8         if_in_unknown_protos_low[0x20];
3196 
3197 	u8         if_out_octets_high[0x20];
3198 
3199 	u8         if_out_octets_low[0x20];
3200 
3201 	u8         if_out_ucast_pkts_high[0x20];
3202 
3203 	u8         if_out_ucast_pkts_low[0x20];
3204 
3205 	u8         if_out_discards_high[0x20];
3206 
3207 	u8         if_out_discards_low[0x20];
3208 
3209 	u8         if_out_errors_high[0x20];
3210 
3211 	u8         if_out_errors_low[0x20];
3212 
3213 	u8         if_in_multicast_pkts_high[0x20];
3214 
3215 	u8         if_in_multicast_pkts_low[0x20];
3216 
3217 	u8         if_in_broadcast_pkts_high[0x20];
3218 
3219 	u8         if_in_broadcast_pkts_low[0x20];
3220 
3221 	u8         if_out_multicast_pkts_high[0x20];
3222 
3223 	u8         if_out_multicast_pkts_low[0x20];
3224 
3225 	u8         if_out_broadcast_pkts_high[0x20];
3226 
3227 	u8         if_out_broadcast_pkts_low[0x20];
3228 
3229 	u8         reserved_at_340[0x480];
3230 };
3231 
3232 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
3233 	u8         a_frames_transmitted_ok_high[0x20];
3234 
3235 	u8         a_frames_transmitted_ok_low[0x20];
3236 
3237 	u8         a_frames_received_ok_high[0x20];
3238 
3239 	u8         a_frames_received_ok_low[0x20];
3240 
3241 	u8         a_frame_check_sequence_errors_high[0x20];
3242 
3243 	u8         a_frame_check_sequence_errors_low[0x20];
3244 
3245 	u8         a_alignment_errors_high[0x20];
3246 
3247 	u8         a_alignment_errors_low[0x20];
3248 
3249 	u8         a_octets_transmitted_ok_high[0x20];
3250 
3251 	u8         a_octets_transmitted_ok_low[0x20];
3252 
3253 	u8         a_octets_received_ok_high[0x20];
3254 
3255 	u8         a_octets_received_ok_low[0x20];
3256 
3257 	u8         a_multicast_frames_xmitted_ok_high[0x20];
3258 
3259 	u8         a_multicast_frames_xmitted_ok_low[0x20];
3260 
3261 	u8         a_broadcast_frames_xmitted_ok_high[0x20];
3262 
3263 	u8         a_broadcast_frames_xmitted_ok_low[0x20];
3264 
3265 	u8         a_multicast_frames_received_ok_high[0x20];
3266 
3267 	u8         a_multicast_frames_received_ok_low[0x20];
3268 
3269 	u8         a_broadcast_frames_received_ok_high[0x20];
3270 
3271 	u8         a_broadcast_frames_received_ok_low[0x20];
3272 
3273 	u8         a_in_range_length_errors_high[0x20];
3274 
3275 	u8         a_in_range_length_errors_low[0x20];
3276 
3277 	u8         a_out_of_range_length_field_high[0x20];
3278 
3279 	u8         a_out_of_range_length_field_low[0x20];
3280 
3281 	u8         a_frame_too_long_errors_high[0x20];
3282 
3283 	u8         a_frame_too_long_errors_low[0x20];
3284 
3285 	u8         a_symbol_error_during_carrier_high[0x20];
3286 
3287 	u8         a_symbol_error_during_carrier_low[0x20];
3288 
3289 	u8         a_mac_control_frames_transmitted_high[0x20];
3290 
3291 	u8         a_mac_control_frames_transmitted_low[0x20];
3292 
3293 	u8         a_mac_control_frames_received_high[0x20];
3294 
3295 	u8         a_mac_control_frames_received_low[0x20];
3296 
3297 	u8         a_unsupported_opcodes_received_high[0x20];
3298 
3299 	u8         a_unsupported_opcodes_received_low[0x20];
3300 
3301 	u8         a_pause_mac_ctrl_frames_received_high[0x20];
3302 
3303 	u8         a_pause_mac_ctrl_frames_received_low[0x20];
3304 
3305 	u8         a_pause_mac_ctrl_frames_transmitted_high[0x20];
3306 
3307 	u8         a_pause_mac_ctrl_frames_transmitted_low[0x20];
3308 
3309 	u8         reserved_at_4c0[0x300];
3310 };
3311 
3312 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits {
3313 	u8         life_time_counter_high[0x20];
3314 
3315 	u8         life_time_counter_low[0x20];
3316 
3317 	u8         rx_errors[0x20];
3318 
3319 	u8         tx_errors[0x20];
3320 
3321 	u8         l0_to_recovery_eieos[0x20];
3322 
3323 	u8         l0_to_recovery_ts[0x20];
3324 
3325 	u8         l0_to_recovery_framing[0x20];
3326 
3327 	u8         l0_to_recovery_retrain[0x20];
3328 
3329 	u8         crc_error_dllp[0x20];
3330 
3331 	u8         crc_error_tlp[0x20];
3332 
3333 	u8         tx_overflow_buffer_pkt_high[0x20];
3334 
3335 	u8         tx_overflow_buffer_pkt_low[0x20];
3336 
3337 	u8         outbound_stalled_reads[0x20];
3338 
3339 	u8         outbound_stalled_writes[0x20];
3340 
3341 	u8         outbound_stalled_reads_events[0x20];
3342 
3343 	u8         outbound_stalled_writes_events[0x20];
3344 
3345 	u8         reserved_at_200[0x5c0];
3346 };
3347 
3348 struct mlx5_ifc_cmd_inter_comp_event_bits {
3349 	u8         command_completion_vector[0x20];
3350 
3351 	u8         reserved_at_20[0xc0];
3352 };
3353 
3354 struct mlx5_ifc_stall_vl_event_bits {
3355 	u8         reserved_at_0[0x18];
3356 	u8         port_num[0x1];
3357 	u8         reserved_at_19[0x3];
3358 	u8         vl[0x4];
3359 
3360 	u8         reserved_at_20[0xa0];
3361 };
3362 
3363 struct mlx5_ifc_db_bf_congestion_event_bits {
3364 	u8         event_subtype[0x8];
3365 	u8         reserved_at_8[0x8];
3366 	u8         congestion_level[0x8];
3367 	u8         reserved_at_18[0x8];
3368 
3369 	u8         reserved_at_20[0xa0];
3370 };
3371 
3372 struct mlx5_ifc_gpio_event_bits {
3373 	u8         reserved_at_0[0x60];
3374 
3375 	u8         gpio_event_hi[0x20];
3376 
3377 	u8         gpio_event_lo[0x20];
3378 
3379 	u8         reserved_at_a0[0x40];
3380 };
3381 
3382 struct mlx5_ifc_port_state_change_event_bits {
3383 	u8         reserved_at_0[0x40];
3384 
3385 	u8         port_num[0x4];
3386 	u8         reserved_at_44[0x1c];
3387 
3388 	u8         reserved_at_60[0x80];
3389 };
3390 
3391 struct mlx5_ifc_dropped_packet_logged_bits {
3392 	u8         reserved_at_0[0xe0];
3393 };
3394 
3395 struct mlx5_ifc_nic_cap_reg_bits {
3396 	u8	   reserved_at_0[0x1a];
3397 	u8	   vhca_icm_ctrl[0x1];
3398 	u8	   reserved_at_1b[0x5];
3399 
3400 	u8	   reserved_at_20[0x60];
3401 };
3402 
3403 struct mlx5_ifc_default_timeout_bits {
3404 	u8         to_multiplier[0x3];
3405 	u8         reserved_at_3[0x9];
3406 	u8         to_value[0x14];
3407 };
3408 
3409 struct mlx5_ifc_dtor_reg_bits {
3410 	u8         reserved_at_0[0x20];
3411 
3412 	struct mlx5_ifc_default_timeout_bits pcie_toggle_to;
3413 
3414 	u8         reserved_at_40[0x60];
3415 
3416 	struct mlx5_ifc_default_timeout_bits health_poll_to;
3417 
3418 	struct mlx5_ifc_default_timeout_bits full_crdump_to;
3419 
3420 	struct mlx5_ifc_default_timeout_bits fw_reset_to;
3421 
3422 	struct mlx5_ifc_default_timeout_bits flush_on_err_to;
3423 
3424 	struct mlx5_ifc_default_timeout_bits pci_sync_update_to;
3425 
3426 	struct mlx5_ifc_default_timeout_bits tear_down_to;
3427 
3428 	struct mlx5_ifc_default_timeout_bits fsm_reactivate_to;
3429 
3430 	struct mlx5_ifc_default_timeout_bits reclaim_pages_to;
3431 
3432 	struct mlx5_ifc_default_timeout_bits reclaim_vfs_pages_to;
3433 
3434 	struct mlx5_ifc_default_timeout_bits reset_unload_to;
3435 
3436 	u8         reserved_at_1c0[0x20];
3437 };
3438 
3439 struct mlx5_ifc_vhca_icm_ctrl_reg_bits {
3440 	u8	   vhca_id_valid[0x1];
3441 	u8	   reserved_at_1[0xf];
3442 	u8	   vhca_id[0x10];
3443 
3444 	u8	   reserved_at_20[0xa0];
3445 
3446 	u8	   cur_alloc_icm[0x20];
3447 
3448 	u8	   reserved_at_e0[0x120];
3449 };
3450 
3451 enum {
3452 	MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN                 = 0x1,
3453 	MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR  = 0x2,
3454 };
3455 
3456 struct mlx5_ifc_cq_error_bits {
3457 	u8         reserved_at_0[0x8];
3458 	u8         cqn[0x18];
3459 
3460 	u8         reserved_at_20[0x20];
3461 
3462 	u8         reserved_at_40[0x18];
3463 	u8         syndrome[0x8];
3464 
3465 	u8         reserved_at_60[0x80];
3466 };
3467 
3468 struct mlx5_ifc_rdma_page_fault_event_bits {
3469 	u8         bytes_committed[0x20];
3470 
3471 	u8         r_key[0x20];
3472 
3473 	u8         reserved_at_40[0x10];
3474 	u8         packet_len[0x10];
3475 
3476 	u8         rdma_op_len[0x20];
3477 
3478 	u8         rdma_va[0x40];
3479 
3480 	u8         reserved_at_c0[0x5];
3481 	u8         rdma[0x1];
3482 	u8         write[0x1];
3483 	u8         requestor[0x1];
3484 	u8         qp_number[0x18];
3485 };
3486 
3487 struct mlx5_ifc_wqe_associated_page_fault_event_bits {
3488 	u8         bytes_committed[0x20];
3489 
3490 	u8         reserved_at_20[0x10];
3491 	u8         wqe_index[0x10];
3492 
3493 	u8         reserved_at_40[0x10];
3494 	u8         len[0x10];
3495 
3496 	u8         reserved_at_60[0x60];
3497 
3498 	u8         reserved_at_c0[0x5];
3499 	u8         rdma[0x1];
3500 	u8         write_read[0x1];
3501 	u8         requestor[0x1];
3502 	u8         qpn[0x18];
3503 };
3504 
3505 struct mlx5_ifc_qp_events_bits {
3506 	u8         reserved_at_0[0xa0];
3507 
3508 	u8         type[0x8];
3509 	u8         reserved_at_a8[0x18];
3510 
3511 	u8         reserved_at_c0[0x8];
3512 	u8         qpn_rqn_sqn[0x18];
3513 };
3514 
3515 struct mlx5_ifc_dct_events_bits {
3516 	u8         reserved_at_0[0xc0];
3517 
3518 	u8         reserved_at_c0[0x8];
3519 	u8         dct_number[0x18];
3520 };
3521 
3522 struct mlx5_ifc_comp_event_bits {
3523 	u8         reserved_at_0[0xc0];
3524 
3525 	u8         reserved_at_c0[0x8];
3526 	u8         cq_number[0x18];
3527 };
3528 
3529 enum {
3530 	MLX5_QPC_STATE_RST        = 0x0,
3531 	MLX5_QPC_STATE_INIT       = 0x1,
3532 	MLX5_QPC_STATE_RTR        = 0x2,
3533 	MLX5_QPC_STATE_RTS        = 0x3,
3534 	MLX5_QPC_STATE_SQER       = 0x4,
3535 	MLX5_QPC_STATE_ERR        = 0x6,
3536 	MLX5_QPC_STATE_SQD        = 0x7,
3537 	MLX5_QPC_STATE_SUSPENDED  = 0x9,
3538 };
3539 
3540 enum {
3541 	MLX5_QPC_ST_RC            = 0x0,
3542 	MLX5_QPC_ST_UC            = 0x1,
3543 	MLX5_QPC_ST_UD            = 0x2,
3544 	MLX5_QPC_ST_XRC           = 0x3,
3545 	MLX5_QPC_ST_DCI           = 0x5,
3546 	MLX5_QPC_ST_QP0           = 0x7,
3547 	MLX5_QPC_ST_QP1           = 0x8,
3548 	MLX5_QPC_ST_RAW_DATAGRAM  = 0x9,
3549 	MLX5_QPC_ST_REG_UMR       = 0xc,
3550 };
3551 
3552 enum {
3553 	MLX5_QPC_PM_STATE_ARMED     = 0x0,
3554 	MLX5_QPC_PM_STATE_REARM     = 0x1,
3555 	MLX5_QPC_PM_STATE_RESERVED  = 0x2,
3556 	MLX5_QPC_PM_STATE_MIGRATED  = 0x3,
3557 };
3558 
3559 enum {
3560 	MLX5_QPC_OFFLOAD_TYPE_RNDV  = 0x1,
3561 };
3562 
3563 enum {
3564 	MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS                = 0x0,
3565 	MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT  = 0x1,
3566 };
3567 
3568 enum {
3569 	MLX5_QPC_MTU_256_BYTES        = 0x1,
3570 	MLX5_QPC_MTU_512_BYTES        = 0x2,
3571 	MLX5_QPC_MTU_1K_BYTES         = 0x3,
3572 	MLX5_QPC_MTU_2K_BYTES         = 0x4,
3573 	MLX5_QPC_MTU_4K_BYTES         = 0x5,
3574 	MLX5_QPC_MTU_RAW_ETHERNET_QP  = 0x7,
3575 };
3576 
3577 enum {
3578 	MLX5_QPC_ATOMIC_MODE_IB_SPEC     = 0x1,
3579 	MLX5_QPC_ATOMIC_MODE_ONLY_8B     = 0x2,
3580 	MLX5_QPC_ATOMIC_MODE_UP_TO_8B    = 0x3,
3581 	MLX5_QPC_ATOMIC_MODE_UP_TO_16B   = 0x4,
3582 	MLX5_QPC_ATOMIC_MODE_UP_TO_32B   = 0x5,
3583 	MLX5_QPC_ATOMIC_MODE_UP_TO_64B   = 0x6,
3584 	MLX5_QPC_ATOMIC_MODE_UP_TO_128B  = 0x7,
3585 	MLX5_QPC_ATOMIC_MODE_UP_TO_256B  = 0x8,
3586 };
3587 
3588 enum {
3589 	MLX5_QPC_CS_REQ_DISABLE    = 0x0,
3590 	MLX5_QPC_CS_REQ_UP_TO_32B  = 0x11,
3591 	MLX5_QPC_CS_REQ_UP_TO_64B  = 0x22,
3592 };
3593 
3594 enum {
3595 	MLX5_QPC_CS_RES_DISABLE    = 0x0,
3596 	MLX5_QPC_CS_RES_UP_TO_32B  = 0x1,
3597 	MLX5_QPC_CS_RES_UP_TO_64B  = 0x2,
3598 };
3599 
3600 enum {
3601 	MLX5_TIMESTAMP_FORMAT_FREE_RUNNING = 0x0,
3602 	MLX5_TIMESTAMP_FORMAT_DEFAULT      = 0x1,
3603 	MLX5_TIMESTAMP_FORMAT_REAL_TIME    = 0x2,
3604 };
3605 
3606 struct mlx5_ifc_qpc_bits {
3607 	u8         state[0x4];
3608 	u8         lag_tx_port_affinity[0x4];
3609 	u8         st[0x8];
3610 	u8         reserved_at_10[0x2];
3611 	u8	   isolate_vl_tc[0x1];
3612 	u8         pm_state[0x2];
3613 	u8         reserved_at_15[0x1];
3614 	u8         req_e2e_credit_mode[0x2];
3615 	u8         offload_type[0x4];
3616 	u8         end_padding_mode[0x2];
3617 	u8         reserved_at_1e[0x2];
3618 
3619 	u8         wq_signature[0x1];
3620 	u8         block_lb_mc[0x1];
3621 	u8         atomic_like_write_en[0x1];
3622 	u8         latency_sensitive[0x1];
3623 	u8         reserved_at_24[0x1];
3624 	u8         drain_sigerr[0x1];
3625 	u8         reserved_at_26[0x1];
3626 	u8         dp_ordering_force[0x1];
3627 	u8         pd[0x18];
3628 
3629 	u8         mtu[0x3];
3630 	u8         log_msg_max[0x5];
3631 	u8         reserved_at_48[0x1];
3632 	u8         log_rq_size[0x4];
3633 	u8         log_rq_stride[0x3];
3634 	u8         no_sq[0x1];
3635 	u8         log_sq_size[0x4];
3636 	u8         reserved_at_55[0x1];
3637 	u8	   retry_mode[0x2];
3638 	u8	   ts_format[0x2];
3639 	u8         reserved_at_5a[0x1];
3640 	u8         rlky[0x1];
3641 	u8         ulp_stateless_offload_mode[0x4];
3642 
3643 	u8         counter_set_id[0x8];
3644 	u8         uar_page[0x18];
3645 
3646 	u8         reserved_at_80[0x8];
3647 	u8         user_index[0x18];
3648 
3649 	u8         reserved_at_a0[0x3];
3650 	u8         log_page_size[0x5];
3651 	u8         remote_qpn[0x18];
3652 
3653 	struct mlx5_ifc_ads_bits primary_address_path;
3654 
3655 	struct mlx5_ifc_ads_bits secondary_address_path;
3656 
3657 	u8         log_ack_req_freq[0x4];
3658 	u8         reserved_at_384[0x4];
3659 	u8         log_sra_max[0x3];
3660 	u8         reserved_at_38b[0x2];
3661 	u8         retry_count[0x3];
3662 	u8         rnr_retry[0x3];
3663 	u8         reserved_at_393[0x1];
3664 	u8         fre[0x1];
3665 	u8         cur_rnr_retry[0x3];
3666 	u8         cur_retry_count[0x3];
3667 	u8         reserved_at_39b[0x5];
3668 
3669 	u8         reserved_at_3a0[0x20];
3670 
3671 	u8         reserved_at_3c0[0x8];
3672 	u8         next_send_psn[0x18];
3673 
3674 	u8         reserved_at_3e0[0x3];
3675 	u8	   log_num_dci_stream_channels[0x5];
3676 	u8         cqn_snd[0x18];
3677 
3678 	u8         reserved_at_400[0x3];
3679 	u8	   log_num_dci_errored_streams[0x5];
3680 	u8         deth_sqpn[0x18];
3681 
3682 	u8         reserved_at_420[0x20];
3683 
3684 	u8         reserved_at_440[0x8];
3685 	u8         last_acked_psn[0x18];
3686 
3687 	u8         reserved_at_460[0x8];
3688 	u8         ssn[0x18];
3689 
3690 	u8         reserved_at_480[0x8];
3691 	u8         log_rra_max[0x3];
3692 	u8         reserved_at_48b[0x1];
3693 	u8         atomic_mode[0x4];
3694 	u8         rre[0x1];
3695 	u8         rwe[0x1];
3696 	u8         rae[0x1];
3697 	u8         reserved_at_493[0x1];
3698 	u8         page_offset[0x6];
3699 	u8         reserved_at_49a[0x2];
3700 	u8         dp_ordering_1[0x1];
3701 	u8         cd_slave_receive[0x1];
3702 	u8         cd_slave_send[0x1];
3703 	u8         cd_master[0x1];
3704 
3705 	u8         reserved_at_4a0[0x3];
3706 	u8         min_rnr_nak[0x5];
3707 	u8         next_rcv_psn[0x18];
3708 
3709 	u8         reserved_at_4c0[0x8];
3710 	u8         xrcd[0x18];
3711 
3712 	u8         reserved_at_4e0[0x8];
3713 	u8         cqn_rcv[0x18];
3714 
3715 	u8         dbr_addr[0x40];
3716 
3717 	u8         q_key[0x20];
3718 
3719 	u8         reserved_at_560[0x5];
3720 	u8         rq_type[0x3];
3721 	u8         srqn_rmpn_xrqn[0x18];
3722 
3723 	u8         reserved_at_580[0x8];
3724 	u8         rmsn[0x18];
3725 
3726 	u8         hw_sq_wqebb_counter[0x10];
3727 	u8         sw_sq_wqebb_counter[0x10];
3728 
3729 	u8         hw_rq_counter[0x20];
3730 
3731 	u8         sw_rq_counter[0x20];
3732 
3733 	u8         reserved_at_600[0x20];
3734 
3735 	u8         reserved_at_620[0xf];
3736 	u8         cgs[0x1];
3737 	u8         cs_req[0x8];
3738 	u8         cs_res[0x8];
3739 
3740 	u8         dc_access_key[0x40];
3741 
3742 	u8         reserved_at_680[0x3];
3743 	u8         dbr_umem_valid[0x1];
3744 
3745 	u8         reserved_at_684[0xbc];
3746 };
3747 
3748 struct mlx5_ifc_roce_addr_layout_bits {
3749 	u8         source_l3_address[16][0x8];
3750 
3751 	u8         reserved_at_80[0x3];
3752 	u8         vlan_valid[0x1];
3753 	u8         vlan_id[0xc];
3754 	u8         source_mac_47_32[0x10];
3755 
3756 	u8         source_mac_31_0[0x20];
3757 
3758 	u8         reserved_at_c0[0x14];
3759 	u8         roce_l3_type[0x4];
3760 	u8         roce_version[0x8];
3761 
3762 	u8         reserved_at_e0[0x20];
3763 };
3764 
3765 struct mlx5_ifc_crypto_cap_bits {
3766 	u8    reserved_at_0[0x3];
3767 	u8    synchronize_dek[0x1];
3768 	u8    int_kek_manual[0x1];
3769 	u8    int_kek_auto[0x1];
3770 	u8    reserved_at_6[0x1a];
3771 
3772 	u8    reserved_at_20[0x3];
3773 	u8    log_dek_max_alloc[0x5];
3774 	u8    reserved_at_28[0x3];
3775 	u8    log_max_num_deks[0x5];
3776 	u8    reserved_at_30[0x10];
3777 
3778 	u8    reserved_at_40[0x20];
3779 
3780 	u8    reserved_at_60[0x3];
3781 	u8    log_dek_granularity[0x5];
3782 	u8    reserved_at_68[0x3];
3783 	u8    log_max_num_int_kek[0x5];
3784 	u8    sw_wrapped_dek[0x10];
3785 
3786 	u8    reserved_at_80[0x780];
3787 };
3788 
3789 struct mlx5_ifc_shampo_cap_bits {
3790 	u8    reserved_at_0[0x3];
3791 	u8    shampo_log_max_reservation_size[0x5];
3792 	u8    reserved_at_8[0x3];
3793 	u8    shampo_log_min_reservation_size[0x5];
3794 	u8    shampo_min_mss_size[0x10];
3795 
3796 	u8    shampo_header_split[0x1];
3797 	u8    shampo_header_split_data_merge[0x1];
3798 	u8    reserved_at_22[0x1];
3799 	u8    shampo_log_max_headers_entry_size[0x5];
3800 	u8    reserved_at_28[0x18];
3801 
3802 	u8    reserved_at_40[0x7c0];
3803 };
3804 
3805 union mlx5_ifc_hca_cap_union_bits {
3806 	struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
3807 	struct mlx5_ifc_cmd_hca_cap_2_bits cmd_hca_cap_2;
3808 	struct mlx5_ifc_odp_cap_bits odp_cap;
3809 	struct mlx5_ifc_atomic_caps_bits atomic_caps;
3810 	struct mlx5_ifc_roce_cap_bits roce_cap;
3811 	struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
3812 	struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
3813 	struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap;
3814 	struct mlx5_ifc_wqe_based_flow_table_cap_bits wqe_based_flow_table_cap;
3815 	struct mlx5_ifc_esw_cap_bits esw_cap;
3816 	struct mlx5_ifc_e_switch_cap_bits e_switch_cap;
3817 	struct mlx5_ifc_port_selection_cap_bits port_selection_cap;
3818 	struct mlx5_ifc_qos_cap_bits qos_cap;
3819 	struct mlx5_ifc_debug_cap_bits debug_cap;
3820 	struct mlx5_ifc_fpga_cap_bits fpga_cap;
3821 	struct mlx5_ifc_tls_cap_bits tls_cap;
3822 	struct mlx5_ifc_device_mem_cap_bits device_mem_cap;
3823 	struct mlx5_ifc_virtio_emulation_cap_bits virtio_emulation_cap;
3824 	struct mlx5_ifc_macsec_cap_bits macsec_cap;
3825 	struct mlx5_ifc_crypto_cap_bits crypto_cap;
3826 	struct mlx5_ifc_ipsec_cap_bits ipsec_cap;
3827 	struct mlx5_ifc_psp_cap_bits psp_cap;
3828 	u8         reserved_at_0[0x8000];
3829 };
3830 
3831 enum {
3832 	MLX5_FLOW_CONTEXT_ACTION_ALLOW     = 0x1,
3833 	MLX5_FLOW_CONTEXT_ACTION_DROP      = 0x2,
3834 	MLX5_FLOW_CONTEXT_ACTION_FWD_DEST  = 0x4,
3835 	MLX5_FLOW_CONTEXT_ACTION_COUNT     = 0x8,
3836 	MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT = 0x10,
3837 	MLX5_FLOW_CONTEXT_ACTION_DECAP     = 0x20,
3838 	MLX5_FLOW_CONTEXT_ACTION_MOD_HDR   = 0x40,
3839 	MLX5_FLOW_CONTEXT_ACTION_VLAN_POP  = 0x80,
3840 	MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100,
3841 	MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2  = 0x400,
3842 	MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2 = 0x800,
3843 	MLX5_FLOW_CONTEXT_ACTION_CRYPTO_DECRYPT = 0x1000,
3844 	MLX5_FLOW_CONTEXT_ACTION_CRYPTO_ENCRYPT = 0x2000,
3845 	MLX5_FLOW_CONTEXT_ACTION_EXECUTE_ASO = 0x4000,
3846 };
3847 
3848 enum {
3849 	MLX5_FLOW_CONTEXT_FLOW_SOURCE_ANY_VPORT         = 0x0,
3850 	MLX5_FLOW_CONTEXT_FLOW_SOURCE_UPLINK            = 0x1,
3851 	MLX5_FLOW_CONTEXT_FLOW_SOURCE_LOCAL_VPORT       = 0x2,
3852 };
3853 
3854 enum {
3855 	MLX5_FLOW_CONTEXT_ENCRYPT_DECRYPT_TYPE_IPSEC   = 0x0,
3856 	MLX5_FLOW_CONTEXT_ENCRYPT_DECRYPT_TYPE_MACSEC  = 0x1,
3857 	MLX5_FLOW_CONTEXT_ENCRYPT_DECRYPT_TYPE_PSP     = 0x2,
3858 };
3859 
3860 struct mlx5_ifc_vlan_bits {
3861 	u8         ethtype[0x10];
3862 	u8         prio[0x3];
3863 	u8         cfi[0x1];
3864 	u8         vid[0xc];
3865 };
3866 
3867 enum {
3868 	MLX5_FLOW_METER_COLOR_RED	= 0x0,
3869 	MLX5_FLOW_METER_COLOR_YELLOW	= 0x1,
3870 	MLX5_FLOW_METER_COLOR_GREEN	= 0x2,
3871 	MLX5_FLOW_METER_COLOR_UNDEFINED	= 0x3,
3872 };
3873 
3874 enum {
3875 	MLX5_EXE_ASO_FLOW_METER		= 0x2,
3876 };
3877 
3878 struct mlx5_ifc_exe_aso_ctrl_flow_meter_bits {
3879 	u8        return_reg_id[0x4];
3880 	u8        aso_type[0x4];
3881 	u8        reserved_at_8[0x14];
3882 	u8        action[0x1];
3883 	u8        init_color[0x2];
3884 	u8        meter_id[0x1];
3885 };
3886 
3887 union mlx5_ifc_exe_aso_ctrl {
3888 	struct mlx5_ifc_exe_aso_ctrl_flow_meter_bits exe_aso_ctrl_flow_meter;
3889 };
3890 
3891 struct mlx5_ifc_execute_aso_bits {
3892 	u8        valid[0x1];
3893 	u8        reserved_at_1[0x7];
3894 	u8        aso_object_id[0x18];
3895 
3896 	union mlx5_ifc_exe_aso_ctrl exe_aso_ctrl;
3897 };
3898 
3899 struct mlx5_ifc_flow_context_bits {
3900 	struct mlx5_ifc_vlan_bits push_vlan;
3901 
3902 	u8         group_id[0x20];
3903 
3904 	u8         reserved_at_40[0x8];
3905 	u8         flow_tag[0x18];
3906 
3907 	u8         reserved_at_60[0x10];
3908 	u8         action[0x10];
3909 
3910 	u8         extended_destination[0x1];
3911 	u8         uplink_hairpin_en[0x1];
3912 	u8         flow_source[0x2];
3913 	u8         encrypt_decrypt_type[0x4];
3914 	u8         destination_list_size[0x18];
3915 
3916 	u8         reserved_at_a0[0x8];
3917 	u8         flow_counter_list_size[0x18];
3918 
3919 	u8         packet_reformat_id[0x20];
3920 
3921 	u8         modify_header_id[0x20];
3922 
3923 	struct mlx5_ifc_vlan_bits push_vlan_2;
3924 
3925 	u8         encrypt_decrypt_obj_id[0x20];
3926 	u8         reserved_at_140[0xc0];
3927 
3928 	struct mlx5_ifc_fte_match_param_bits match_value;
3929 
3930 	struct mlx5_ifc_execute_aso_bits execute_aso[4];
3931 
3932 	u8         reserved_at_1300[0x500];
3933 
3934 	union mlx5_ifc_dest_format_flow_counter_list_auto_bits destination[];
3935 };
3936 
3937 enum {
3938 	MLX5_XRC_SRQC_STATE_GOOD   = 0x0,
3939 	MLX5_XRC_SRQC_STATE_ERROR  = 0x1,
3940 };
3941 
3942 struct mlx5_ifc_xrc_srqc_bits {
3943 	u8         state[0x4];
3944 	u8         log_xrc_srq_size[0x4];
3945 	u8         reserved_at_8[0x18];
3946 
3947 	u8         wq_signature[0x1];
3948 	u8         cont_srq[0x1];
3949 	u8         reserved_at_22[0x1];
3950 	u8         rlky[0x1];
3951 	u8         basic_cyclic_rcv_wqe[0x1];
3952 	u8         log_rq_stride[0x3];
3953 	u8         xrcd[0x18];
3954 
3955 	u8         page_offset[0x6];
3956 	u8         reserved_at_46[0x1];
3957 	u8         dbr_umem_valid[0x1];
3958 	u8         cqn[0x18];
3959 
3960 	u8         reserved_at_60[0x20];
3961 
3962 	u8         user_index_equal_xrc_srqn[0x1];
3963 	u8         reserved_at_81[0x1];
3964 	u8         log_page_size[0x6];
3965 	u8         user_index[0x18];
3966 
3967 	u8         reserved_at_a0[0x20];
3968 
3969 	u8         reserved_at_c0[0x8];
3970 	u8         pd[0x18];
3971 
3972 	u8         lwm[0x10];
3973 	u8         wqe_cnt[0x10];
3974 
3975 	u8         reserved_at_100[0x40];
3976 
3977 	u8         db_record_addr_h[0x20];
3978 
3979 	u8         db_record_addr_l[0x1e];
3980 	u8         reserved_at_17e[0x2];
3981 
3982 	u8         reserved_at_180[0x80];
3983 };
3984 
3985 struct mlx5_ifc_vnic_diagnostic_statistics_bits {
3986 	u8         counter_error_queues[0x20];
3987 
3988 	u8         total_error_queues[0x20];
3989 
3990 	u8         send_queue_priority_update_flow[0x20];
3991 
3992 	u8         reserved_at_60[0x20];
3993 
3994 	u8         nic_receive_steering_discard[0x40];
3995 
3996 	u8         receive_discard_vport_down[0x40];
3997 
3998 	u8         transmit_discard_vport_down[0x40];
3999 
4000 	u8         async_eq_overrun[0x20];
4001 
4002 	u8         comp_eq_overrun[0x20];
4003 
4004 	u8         reserved_at_180[0x20];
4005 
4006 	u8         invalid_command[0x20];
4007 
4008 	u8         quota_exceeded_command[0x20];
4009 
4010 	u8         internal_rq_out_of_buffer[0x20];
4011 
4012 	u8         cq_overrun[0x20];
4013 
4014 	u8         eth_wqe_too_small[0x20];
4015 
4016 	u8         reserved_at_220[0xc0];
4017 
4018 	u8         generated_pkt_steering_fail[0x40];
4019 
4020 	u8         handled_pkt_steering_fail[0x40];
4021 
4022 	u8         reserved_at_360[0xc80];
4023 };
4024 
4025 struct mlx5_ifc_traffic_counter_bits {
4026 	u8         packets[0x40];
4027 
4028 	u8         octets[0x40];
4029 };
4030 
4031 struct mlx5_ifc_tisc_bits {
4032 	u8         strict_lag_tx_port_affinity[0x1];
4033 	u8         tls_en[0x1];
4034 	u8         reserved_at_2[0x2];
4035 	u8         lag_tx_port_affinity[0x04];
4036 
4037 	u8         reserved_at_8[0x4];
4038 	u8         prio[0x4];
4039 	u8         reserved_at_10[0x10];
4040 
4041 	u8         reserved_at_20[0x100];
4042 
4043 	u8         reserved_at_120[0x8];
4044 	u8         transport_domain[0x18];
4045 
4046 	u8         reserved_at_140[0x8];
4047 	u8         underlay_qpn[0x18];
4048 
4049 	u8         reserved_at_160[0x8];
4050 	u8         pd[0x18];
4051 
4052 	u8         reserved_at_180[0x380];
4053 };
4054 
4055 enum {
4056 	MLX5_TIRC_DISP_TYPE_DIRECT    = 0x0,
4057 	MLX5_TIRC_DISP_TYPE_INDIRECT  = 0x1,
4058 };
4059 
4060 enum {
4061 	MLX5_TIRC_PACKET_MERGE_MASK_IPV4_LRO  = BIT(0),
4062 	MLX5_TIRC_PACKET_MERGE_MASK_IPV6_LRO  = BIT(1),
4063 };
4064 
4065 enum {
4066 	MLX5_RX_HASH_FN_NONE           = 0x0,
4067 	MLX5_RX_HASH_FN_INVERTED_XOR8  = 0x1,
4068 	MLX5_RX_HASH_FN_TOEPLITZ       = 0x2,
4069 };
4070 
4071 enum {
4072 	MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST    = 0x1,
4073 	MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST  = 0x2,
4074 };
4075 
4076 struct mlx5_ifc_tirc_bits {
4077 	u8         reserved_at_0[0x20];
4078 
4079 	u8         disp_type[0x4];
4080 	u8         tls_en[0x1];
4081 	u8         reserved_at_25[0x1b];
4082 
4083 	u8         reserved_at_40[0x40];
4084 
4085 	u8         reserved_at_80[0x4];
4086 	u8         lro_timeout_period_usecs[0x10];
4087 	u8         packet_merge_mask[0x4];
4088 	u8         lro_max_ip_payload_size[0x8];
4089 
4090 	u8         reserved_at_a0[0x40];
4091 
4092 	u8         reserved_at_e0[0x8];
4093 	u8         inline_rqn[0x18];
4094 
4095 	u8         rx_hash_symmetric[0x1];
4096 	u8         reserved_at_101[0x1];
4097 	u8         tunneled_offload_en[0x1];
4098 	u8         reserved_at_103[0x5];
4099 	u8         indirect_table[0x18];
4100 
4101 	u8         rx_hash_fn[0x4];
4102 	u8         reserved_at_124[0x2];
4103 	u8         self_lb_block[0x2];
4104 	u8         transport_domain[0x18];
4105 
4106 	u8         rx_hash_toeplitz_key[10][0x20];
4107 
4108 	struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
4109 
4110 	struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
4111 
4112 	u8         reserved_at_2c0[0x4c0];
4113 };
4114 
4115 enum {
4116 	MLX5_SRQC_STATE_GOOD   = 0x0,
4117 	MLX5_SRQC_STATE_ERROR  = 0x1,
4118 };
4119 
4120 struct mlx5_ifc_srqc_bits {
4121 	u8         state[0x4];
4122 	u8         log_srq_size[0x4];
4123 	u8         reserved_at_8[0x18];
4124 
4125 	u8         wq_signature[0x1];
4126 	u8         cont_srq[0x1];
4127 	u8         reserved_at_22[0x1];
4128 	u8         rlky[0x1];
4129 	u8         reserved_at_24[0x1];
4130 	u8         log_rq_stride[0x3];
4131 	u8         xrcd[0x18];
4132 
4133 	u8         page_offset[0x6];
4134 	u8         reserved_at_46[0x2];
4135 	u8         cqn[0x18];
4136 
4137 	u8         reserved_at_60[0x20];
4138 
4139 	u8         reserved_at_80[0x2];
4140 	u8         log_page_size[0x6];
4141 	u8         reserved_at_88[0x18];
4142 
4143 	u8         reserved_at_a0[0x20];
4144 
4145 	u8         reserved_at_c0[0x8];
4146 	u8         pd[0x18];
4147 
4148 	u8         lwm[0x10];
4149 	u8         wqe_cnt[0x10];
4150 
4151 	u8         reserved_at_100[0x40];
4152 
4153 	u8         dbr_addr[0x40];
4154 
4155 	u8         reserved_at_180[0x80];
4156 };
4157 
4158 enum {
4159 	MLX5_SQC_STATE_RST  = 0x0,
4160 	MLX5_SQC_STATE_RDY  = 0x1,
4161 	MLX5_SQC_STATE_ERR  = 0x3,
4162 };
4163 
4164 struct mlx5_ifc_sqc_bits {
4165 	u8         rlky[0x1];
4166 	u8         cd_master[0x1];
4167 	u8         fre[0x1];
4168 	u8         flush_in_error_en[0x1];
4169 	u8         allow_multi_pkt_send_wqe[0x1];
4170 	u8	   min_wqe_inline_mode[0x3];
4171 	u8         state[0x4];
4172 	u8         reg_umr[0x1];
4173 	u8         allow_swp[0x1];
4174 	u8         hairpin[0x1];
4175 	u8         non_wire[0x1];
4176 	u8         reserved_at_10[0xa];
4177 	u8	   ts_format[0x2];
4178 	u8	   reserved_at_1c[0x4];
4179 
4180 	u8         reserved_at_20[0x8];
4181 	u8         user_index[0x18];
4182 
4183 	u8         reserved_at_40[0x8];
4184 	u8         cqn[0x18];
4185 
4186 	u8         reserved_at_60[0x8];
4187 	u8         hairpin_peer_rq[0x18];
4188 
4189 	u8         reserved_at_80[0x10];
4190 	u8         hairpin_peer_vhca[0x10];
4191 
4192 	u8         reserved_at_a0[0x20];
4193 
4194 	u8         reserved_at_c0[0x8];
4195 	u8         ts_cqe_to_dest_cqn[0x18];
4196 
4197 	u8         reserved_at_e0[0x10];
4198 	u8         packet_pacing_rate_limit_index[0x10];
4199 	u8         tis_lst_sz[0x10];
4200 	u8         qos_queue_group_id[0x10];
4201 
4202 	u8         reserved_at_120[0x40];
4203 
4204 	u8         reserved_at_160[0x8];
4205 	u8         tis_num_0[0x18];
4206 
4207 	struct mlx5_ifc_wq_bits wq;
4208 };
4209 
4210 enum {
4211 	SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0,
4212 	SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1,
4213 	SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2,
4214 	SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3,
4215 	SCHEDULING_CONTEXT_ELEMENT_TYPE_QUEUE_GROUP = 0x4,
4216 	SCHEDULING_CONTEXT_ELEMENT_TYPE_RATE_LIMIT = 0x5,
4217 };
4218 
4219 enum {
4220 	ELEMENT_TYPE_CAP_MASK_TSAR		= 1 << 0,
4221 	ELEMENT_TYPE_CAP_MASK_VPORT		= 1 << 1,
4222 	ELEMENT_TYPE_CAP_MASK_VPORT_TC		= 1 << 2,
4223 	ELEMENT_TYPE_CAP_MASK_PARA_VPORT_TC	= 1 << 3,
4224 	ELEMENT_TYPE_CAP_MASK_QUEUE_GROUP	= 1 << 4,
4225 	ELEMENT_TYPE_CAP_MASK_RATE_LIMIT	= 1 << 5,
4226 };
4227 
4228 enum {
4229 	TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0,
4230 	TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1,
4231 	TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2,
4232 	TSAR_ELEMENT_TSAR_TYPE_TC_ARB = 0x3,
4233 };
4234 
4235 enum {
4236 	TSAR_TYPE_CAP_MASK_DWRR		= 1 << 0,
4237 	TSAR_TYPE_CAP_MASK_ROUND_ROBIN	= 1 << 1,
4238 	TSAR_TYPE_CAP_MASK_ETS		= 1 << 2,
4239 	TSAR_TYPE_CAP_MASK_TC_ARB       = 1 << 3,
4240 };
4241 
4242 struct mlx5_ifc_tsar_element_bits {
4243 	u8         traffic_class[0x4];
4244 	u8         reserved_at_4[0x4];
4245 	u8         tsar_type[0x8];
4246 	u8         reserved_at_10[0x10];
4247 };
4248 
4249 struct mlx5_ifc_vport_element_bits {
4250 	u8         reserved_at_0[0x4];
4251 	u8         eswitch_owner_vhca_id_valid[0x1];
4252 	u8         eswitch_owner_vhca_id[0xb];
4253 	u8         vport_number[0x10];
4254 };
4255 
4256 struct mlx5_ifc_vport_tc_element_bits {
4257 	u8         traffic_class[0x4];
4258 	u8         eswitch_owner_vhca_id_valid[0x1];
4259 	u8         eswitch_owner_vhca_id[0xb];
4260 	u8         vport_number[0x10];
4261 };
4262 
4263 union mlx5_ifc_element_attributes_bits {
4264 	struct mlx5_ifc_tsar_element_bits tsar;
4265 	struct mlx5_ifc_vport_element_bits vport;
4266 	struct mlx5_ifc_vport_tc_element_bits vport_tc;
4267 	u8 reserved_at_0[0x20];
4268 };
4269 
4270 struct mlx5_ifc_scheduling_context_bits {
4271 	u8         element_type[0x8];
4272 	u8         reserved_at_8[0x18];
4273 
4274 	union mlx5_ifc_element_attributes_bits element_attributes;
4275 
4276 	u8         parent_element_id[0x20];
4277 
4278 	u8         reserved_at_60[0x40];
4279 
4280 	u8         bw_share[0x20];
4281 
4282 	u8         max_average_bw[0x20];
4283 
4284 	u8         max_bw_obj_id[0x20];
4285 
4286 	u8         reserved_at_100[0x100];
4287 };
4288 
4289 struct mlx5_ifc_rqtc_bits {
4290 	u8    reserved_at_0[0xa0];
4291 
4292 	u8    reserved_at_a0[0x5];
4293 	u8    list_q_type[0x3];
4294 	u8    reserved_at_a8[0x8];
4295 	u8    rqt_max_size[0x10];
4296 
4297 	u8    rq_vhca_id_format[0x1];
4298 	u8    reserved_at_c1[0xf];
4299 	u8    rqt_actual_size[0x10];
4300 
4301 	u8    reserved_at_e0[0x6a0];
4302 
4303 	union {
4304 		DECLARE_FLEX_ARRAY(struct mlx5_ifc_rq_num_bits, rq_num);
4305 		DECLARE_FLEX_ARRAY(struct mlx5_ifc_rq_vhca_bits, rq_vhca);
4306 	};
4307 };
4308 
4309 enum {
4310 	MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE  = 0x0,
4311 	MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP     = 0x1,
4312 };
4313 
4314 enum {
4315 	MLX5_RQC_STATE_RST  = 0x0,
4316 	MLX5_RQC_STATE_RDY  = 0x1,
4317 	MLX5_RQC_STATE_ERR  = 0x3,
4318 };
4319 
4320 enum {
4321 	MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_BYTE    = 0x0,
4322 	MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_STRIDE  = 0x1,
4323 	MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_PAGE    = 0x2,
4324 };
4325 
4326 enum {
4327 	MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_NO_MATCH    = 0x0,
4328 	MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_EXTENDED    = 0x1,
4329 	MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_FIVE_TUPLE  = 0x2,
4330 };
4331 
4332 struct mlx5_ifc_rqc_bits {
4333 	u8         rlky[0x1];
4334 	u8	   delay_drop_en[0x1];
4335 	u8         scatter_fcs[0x1];
4336 	u8         vsd[0x1];
4337 	u8         mem_rq_type[0x4];
4338 	u8         state[0x4];
4339 	u8         reserved_at_c[0x1];
4340 	u8         flush_in_error_en[0x1];
4341 	u8         hairpin[0x1];
4342 	u8         reserved_at_f[0xb];
4343 	u8	   ts_format[0x2];
4344 	u8	   reserved_at_1c[0x4];
4345 
4346 	u8         reserved_at_20[0x8];
4347 	u8         user_index[0x18];
4348 
4349 	u8         reserved_at_40[0x8];
4350 	u8         cqn[0x18];
4351 
4352 	u8         counter_set_id[0x8];
4353 	u8         reserved_at_68[0x18];
4354 
4355 	u8         reserved_at_80[0x8];
4356 	u8         rmpn[0x18];
4357 
4358 	u8         reserved_at_a0[0x8];
4359 	u8         hairpin_peer_sq[0x18];
4360 
4361 	u8         reserved_at_c0[0x10];
4362 	u8         hairpin_peer_vhca[0x10];
4363 
4364 	u8         reserved_at_e0[0x46];
4365 	u8         shampo_no_match_alignment_granularity[0x2];
4366 	u8         reserved_at_128[0x6];
4367 	u8         shampo_match_criteria_type[0x2];
4368 	u8         reservation_timeout[0x10];
4369 
4370 	u8         reserved_at_140[0x40];
4371 
4372 	struct mlx5_ifc_wq_bits wq;
4373 };
4374 
4375 enum {
4376 	MLX5_RMPC_STATE_RDY  = 0x1,
4377 	MLX5_RMPC_STATE_ERR  = 0x3,
4378 };
4379 
4380 struct mlx5_ifc_rmpc_bits {
4381 	u8         reserved_at_0[0x8];
4382 	u8         state[0x4];
4383 	u8         reserved_at_c[0x14];
4384 
4385 	u8         basic_cyclic_rcv_wqe[0x1];
4386 	u8         reserved_at_21[0x1f];
4387 
4388 	u8         reserved_at_40[0x140];
4389 
4390 	struct mlx5_ifc_wq_bits wq;
4391 };
4392 
4393 enum {
4394 	VHCA_ID_TYPE_HW = 0,
4395 	VHCA_ID_TYPE_SW = 1,
4396 };
4397 
4398 struct mlx5_ifc_nic_vport_context_bits {
4399 	u8         reserved_at_0[0x5];
4400 	u8         min_wqe_inline_mode[0x3];
4401 	u8         reserved_at_8[0x15];
4402 	u8         disable_mc_local_lb[0x1];
4403 	u8         disable_uc_local_lb[0x1];
4404 	u8         roce_en[0x1];
4405 
4406 	u8         arm_change_event[0x1];
4407 	u8         reserved_at_21[0x1a];
4408 	u8         event_on_mtu[0x1];
4409 	u8         event_on_promisc_change[0x1];
4410 	u8         event_on_vlan_change[0x1];
4411 	u8         event_on_mc_address_change[0x1];
4412 	u8         event_on_uc_address_change[0x1];
4413 
4414 	u8         vhca_id_type[0x1];
4415 	u8         reserved_at_41[0xb];
4416 	u8	   affiliation_criteria[0x4];
4417 	u8	   affiliated_vhca_id[0x10];
4418 
4419 	u8	   reserved_at_60[0xa0];
4420 
4421 	u8	   reserved_at_100[0x1];
4422 	u8         sd_group[0x3];
4423 	u8	   reserved_at_104[0x1c];
4424 
4425 	u8	   reserved_at_120[0x10];
4426 	u8         mtu[0x10];
4427 
4428 	u8         system_image_guid[0x40];
4429 	u8         port_guid[0x40];
4430 	u8         node_guid[0x40];
4431 
4432 	u8         reserved_at_200[0x140];
4433 	u8         qkey_violation_counter[0x10];
4434 	u8         reserved_at_350[0x430];
4435 
4436 	u8         promisc_uc[0x1];
4437 	u8         promisc_mc[0x1];
4438 	u8         promisc_all[0x1];
4439 	u8         reserved_at_783[0x2];
4440 	u8         allowed_list_type[0x3];
4441 	u8         reserved_at_788[0xc];
4442 	u8         allowed_list_size[0xc];
4443 
4444 	struct mlx5_ifc_mac_address_layout_bits permanent_address;
4445 
4446 	u8         reserved_at_7e0[0x20];
4447 
4448 	u8         current_uc_mac_address[][0x40];
4449 };
4450 
4451 enum {
4452 	MLX5_MKC_ACCESS_MODE_PA    = 0x0,
4453 	MLX5_MKC_ACCESS_MODE_MTT   = 0x1,
4454 	MLX5_MKC_ACCESS_MODE_KLMS  = 0x2,
4455 	MLX5_MKC_ACCESS_MODE_KSM   = 0x3,
4456 	MLX5_MKC_ACCESS_MODE_SW_ICM = 0x4,
4457 	MLX5_MKC_ACCESS_MODE_MEMIC = 0x5,
4458 	MLX5_MKC_ACCESS_MODE_CROSSING = 0x6,
4459 };
4460 
4461 enum {
4462 	MLX5_MKC_PCIE_TPH_NO_STEERING_TAG_INDEX = 0,
4463 };
4464 
4465 struct mlx5_ifc_mkc_bits {
4466 	u8         reserved_at_0[0x1];
4467 	u8         free[0x1];
4468 	u8         reserved_at_2[0x1];
4469 	u8         access_mode_4_2[0x3];
4470 	u8         reserved_at_6[0x7];
4471 	u8         relaxed_ordering_write[0x1];
4472 	u8         reserved_at_e[0x1];
4473 	u8         small_fence_on_rdma_read_response[0x1];
4474 	u8         umr_en[0x1];
4475 	u8         a[0x1];
4476 	u8         rw[0x1];
4477 	u8         rr[0x1];
4478 	u8         lw[0x1];
4479 	u8         lr[0x1];
4480 	u8         access_mode_1_0[0x2];
4481 	u8         reserved_at_18[0x2];
4482 	u8         ma_translation_mode[0x2];
4483 	u8         reserved_at_1c[0x4];
4484 
4485 	u8         qpn[0x18];
4486 	u8         mkey_7_0[0x8];
4487 
4488 	u8         reserved_at_40[0x20];
4489 
4490 	u8         length64[0x1];
4491 	u8         bsf_en[0x1];
4492 	u8         sync_umr[0x1];
4493 	u8         reserved_at_63[0x2];
4494 	u8         expected_sigerr_count[0x1];
4495 	u8         reserved_at_66[0x1];
4496 	u8         en_rinval[0x1];
4497 	u8         pd[0x18];
4498 
4499 	u8         start_addr[0x40];
4500 
4501 	u8         len[0x40];
4502 
4503 	u8         bsf_octword_size[0x20];
4504 
4505 	u8         reserved_at_120[0x60];
4506 
4507 	u8         crossing_target_vhca_id[0x10];
4508 	u8         reserved_at_190[0x10];
4509 
4510 	u8         translations_octword_size[0x20];
4511 
4512 	u8         reserved_at_1c0[0x19];
4513 	u8         relaxed_ordering_read[0x1];
4514 	u8         log_page_size[0x6];
4515 
4516 	u8         reserved_at_1e0[0x5];
4517 	u8         pcie_tph_en[0x1];
4518 	u8         pcie_tph_ph[0x2];
4519 	u8         pcie_tph_steering_tag_index[0x8];
4520 	u8         reserved_at_1f0[0x10];
4521 };
4522 
4523 struct mlx5_ifc_pkey_bits {
4524 	u8         reserved_at_0[0x10];
4525 	u8         pkey[0x10];
4526 };
4527 
4528 struct mlx5_ifc_array128_auto_bits {
4529 	u8         array128_auto[16][0x8];
4530 };
4531 
4532 struct mlx5_ifc_hca_vport_context_bits {
4533 	u8         field_select[0x20];
4534 
4535 	u8         reserved_at_20[0xe0];
4536 
4537 	u8         sm_virt_aware[0x1];
4538 	u8         has_smi[0x1];
4539 	u8         has_raw[0x1];
4540 	u8         grh_required[0x1];
4541 	u8         reserved_at_104[0x4];
4542 	u8         num_port_plane[0x8];
4543 	u8         port_physical_state[0x4];
4544 	u8         vport_state_policy[0x4];
4545 	u8         port_state[0x4];
4546 	u8         vport_state[0x4];
4547 
4548 	u8         reserved_at_120[0x20];
4549 
4550 	u8         system_image_guid[0x40];
4551 
4552 	u8         port_guid[0x40];
4553 
4554 	u8         node_guid[0x40];
4555 
4556 	u8         cap_mask1[0x20];
4557 
4558 	u8         cap_mask1_field_select[0x20];
4559 
4560 	u8         cap_mask2[0x20];
4561 
4562 	u8         cap_mask2_field_select[0x20];
4563 
4564 	u8         reserved_at_280[0x80];
4565 
4566 	u8         lid[0x10];
4567 	u8         reserved_at_310[0x4];
4568 	u8         init_type_reply[0x4];
4569 	u8         lmc[0x3];
4570 	u8         subnet_timeout[0x5];
4571 
4572 	u8         sm_lid[0x10];
4573 	u8         sm_sl[0x4];
4574 	u8         reserved_at_334[0xc];
4575 
4576 	u8         qkey_violation_counter[0x10];
4577 	u8         pkey_violation_counter[0x10];
4578 
4579 	u8         reserved_at_360[0xca0];
4580 };
4581 
4582 struct mlx5_ifc_esw_vport_context_bits {
4583 	u8         fdb_to_vport_reg_c[0x1];
4584 	u8         reserved_at_1[0x2];
4585 	u8         vport_svlan_strip[0x1];
4586 	u8         vport_cvlan_strip[0x1];
4587 	u8         vport_svlan_insert[0x1];
4588 	u8         vport_cvlan_insert[0x2];
4589 	u8         fdb_to_vport_reg_c_id[0x8];
4590 	u8         reserved_at_10[0x10];
4591 
4592 	u8         reserved_at_20[0x20];
4593 
4594 	u8         svlan_cfi[0x1];
4595 	u8         svlan_pcp[0x3];
4596 	u8         svlan_id[0xc];
4597 	u8         cvlan_cfi[0x1];
4598 	u8         cvlan_pcp[0x3];
4599 	u8         cvlan_id[0xc];
4600 
4601 	u8         reserved_at_60[0x720];
4602 
4603 	u8         sw_steering_vport_icm_address_rx[0x40];
4604 
4605 	u8         sw_steering_vport_icm_address_tx[0x40];
4606 };
4607 
4608 enum {
4609 	MLX5_EQC_STATUS_OK                = 0x0,
4610 	MLX5_EQC_STATUS_EQ_WRITE_FAILURE  = 0xa,
4611 };
4612 
4613 enum {
4614 	MLX5_EQC_ST_ARMED  = 0x9,
4615 	MLX5_EQC_ST_FIRED  = 0xa,
4616 };
4617 
4618 struct mlx5_ifc_eqc_bits {
4619 	u8         status[0x4];
4620 	u8         reserved_at_4[0x9];
4621 	u8         ec[0x1];
4622 	u8         oi[0x1];
4623 	u8         reserved_at_f[0x5];
4624 	u8         st[0x4];
4625 	u8         reserved_at_18[0x8];
4626 
4627 	u8         reserved_at_20[0x20];
4628 
4629 	u8         reserved_at_40[0x14];
4630 	u8         page_offset[0x6];
4631 	u8         reserved_at_5a[0x6];
4632 
4633 	u8         reserved_at_60[0x3];
4634 	u8         log_eq_size[0x5];
4635 	u8         uar_page[0x18];
4636 
4637 	u8         reserved_at_80[0x20];
4638 
4639 	u8         reserved_at_a0[0x14];
4640 	u8         intr[0xc];
4641 
4642 	u8         reserved_at_c0[0x3];
4643 	u8         log_page_size[0x5];
4644 	u8         reserved_at_c8[0x18];
4645 
4646 	u8         reserved_at_e0[0x60];
4647 
4648 	u8         reserved_at_140[0x8];
4649 	u8         consumer_counter[0x18];
4650 
4651 	u8         reserved_at_160[0x8];
4652 	u8         producer_counter[0x18];
4653 
4654 	u8         reserved_at_180[0x80];
4655 };
4656 
4657 enum {
4658 	MLX5_DCTC_STATE_ACTIVE    = 0x0,
4659 	MLX5_DCTC_STATE_DRAINING  = 0x1,
4660 	MLX5_DCTC_STATE_DRAINED   = 0x2,
4661 };
4662 
4663 enum {
4664 	MLX5_DCTC_CS_RES_DISABLE    = 0x0,
4665 	MLX5_DCTC_CS_RES_NA         = 0x1,
4666 	MLX5_DCTC_CS_RES_UP_TO_64B  = 0x2,
4667 };
4668 
4669 enum {
4670 	MLX5_DCTC_MTU_256_BYTES  = 0x1,
4671 	MLX5_DCTC_MTU_512_BYTES  = 0x2,
4672 	MLX5_DCTC_MTU_1K_BYTES   = 0x3,
4673 	MLX5_DCTC_MTU_2K_BYTES   = 0x4,
4674 	MLX5_DCTC_MTU_4K_BYTES   = 0x5,
4675 };
4676 
4677 struct mlx5_ifc_dctc_bits {
4678 	u8         reserved_at_0[0x4];
4679 	u8         state[0x4];
4680 	u8         reserved_at_8[0x18];
4681 
4682 	u8         reserved_at_20[0x7];
4683 	u8         dp_ordering_force[0x1];
4684 	u8         user_index[0x18];
4685 
4686 	u8         reserved_at_40[0x8];
4687 	u8         cqn[0x18];
4688 
4689 	u8         counter_set_id[0x8];
4690 	u8         atomic_mode[0x4];
4691 	u8         rre[0x1];
4692 	u8         rwe[0x1];
4693 	u8         rae[0x1];
4694 	u8         atomic_like_write_en[0x1];
4695 	u8         latency_sensitive[0x1];
4696 	u8         rlky[0x1];
4697 	u8         free_ar[0x1];
4698 	u8         reserved_at_73[0x1];
4699 	u8         dp_ordering_1[0x1];
4700 	u8         reserved_at_75[0xb];
4701 
4702 	u8         reserved_at_80[0x8];
4703 	u8         cs_res[0x8];
4704 	u8         reserved_at_90[0x3];
4705 	u8         min_rnr_nak[0x5];
4706 	u8         reserved_at_98[0x8];
4707 
4708 	u8         reserved_at_a0[0x8];
4709 	u8         srqn_xrqn[0x18];
4710 
4711 	u8         reserved_at_c0[0x8];
4712 	u8         pd[0x18];
4713 
4714 	u8         tclass[0x8];
4715 	u8         reserved_at_e8[0x4];
4716 	u8         flow_label[0x14];
4717 
4718 	u8         dc_access_key[0x40];
4719 
4720 	u8         reserved_at_140[0x5];
4721 	u8         mtu[0x3];
4722 	u8         port[0x8];
4723 	u8         pkey_index[0x10];
4724 
4725 	u8         reserved_at_160[0x8];
4726 	u8         my_addr_index[0x8];
4727 	u8         reserved_at_170[0x8];
4728 	u8         hop_limit[0x8];
4729 
4730 	u8         dc_access_key_violation_count[0x20];
4731 
4732 	u8         reserved_at_1a0[0x14];
4733 	u8         dei_cfi[0x1];
4734 	u8         eth_prio[0x3];
4735 	u8         ecn[0x2];
4736 	u8         dscp[0x6];
4737 
4738 	u8         reserved_at_1c0[0x20];
4739 	u8         ece[0x20];
4740 };
4741 
4742 enum {
4743 	MLX5_CQC_STATUS_OK             = 0x0,
4744 	MLX5_CQC_STATUS_CQ_OVERFLOW    = 0x9,
4745 	MLX5_CQC_STATUS_CQ_WRITE_FAIL  = 0xa,
4746 };
4747 
4748 enum {
4749 	MLX5_CQC_CQE_SZ_64_BYTES   = 0x0,
4750 	MLX5_CQC_CQE_SZ_128_BYTES  = 0x1,
4751 };
4752 
4753 enum {
4754 	MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED  = 0x6,
4755 	MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED            = 0x9,
4756 	MLX5_CQC_ST_FIRED                                 = 0xa,
4757 };
4758 
4759 enum mlx5_cq_period_mode {
4760 	MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0,
4761 	MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1,
4762 	MLX5_CQ_PERIOD_NUM_MODES,
4763 };
4764 
4765 struct mlx5_ifc_cqc_bits {
4766 	u8         status[0x4];
4767 	u8         reserved_at_4[0x2];
4768 	u8         dbr_umem_valid[0x1];
4769 	u8         apu_cq[0x1];
4770 	u8         cqe_sz[0x3];
4771 	u8         cc[0x1];
4772 	u8         reserved_at_c[0x1];
4773 	u8         scqe_break_moderation_en[0x1];
4774 	u8         oi[0x1];
4775 	u8         cq_period_mode[0x2];
4776 	u8         cqe_comp_en[0x1];
4777 	u8         mini_cqe_res_format[0x2];
4778 	u8         st[0x4];
4779 	u8         reserved_at_18[0x6];
4780 	u8         cqe_compression_layout[0x2];
4781 
4782 	u8         reserved_at_20[0x20];
4783 
4784 	u8         reserved_at_40[0x14];
4785 	u8         page_offset[0x6];
4786 	u8         reserved_at_5a[0x6];
4787 
4788 	u8         reserved_at_60[0x3];
4789 	u8         log_cq_size[0x5];
4790 	u8         uar_page[0x18];
4791 
4792 	u8         reserved_at_80[0x4];
4793 	u8         cq_period[0xc];
4794 	u8         cq_max_count[0x10];
4795 
4796 	u8         c_eqn_or_apu_element[0x20];
4797 
4798 	u8         reserved_at_c0[0x3];
4799 	u8         log_page_size[0x5];
4800 	u8         reserved_at_c8[0x18];
4801 
4802 	u8         reserved_at_e0[0x20];
4803 
4804 	u8         reserved_at_100[0x8];
4805 	u8         last_notified_index[0x18];
4806 
4807 	u8         reserved_at_120[0x8];
4808 	u8         last_solicit_index[0x18];
4809 
4810 	u8         reserved_at_140[0x8];
4811 	u8         consumer_counter[0x18];
4812 
4813 	u8         reserved_at_160[0x8];
4814 	u8         producer_counter[0x18];
4815 
4816 	u8         reserved_at_180[0x40];
4817 
4818 	u8         dbr_addr[0x40];
4819 };
4820 
4821 union mlx5_ifc_cong_control_roce_ecn_auto_bits {
4822 	struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
4823 	struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
4824 	struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
4825 	struct mlx5_ifc_cong_control_r_roce_general_bits cong_control_r_roce_general;
4826 	u8         reserved_at_0[0x800];
4827 };
4828 
4829 struct mlx5_ifc_query_adapter_param_block_bits {
4830 	u8         reserved_at_0[0xc0];
4831 
4832 	u8         reserved_at_c0[0x8];
4833 	u8         ieee_vendor_id[0x18];
4834 
4835 	u8         reserved_at_e0[0x10];
4836 	u8         vsd_vendor_id[0x10];
4837 
4838 	u8         vsd[208][0x8];
4839 
4840 	u8         vsd_contd_psid[16][0x8];
4841 };
4842 
4843 enum {
4844 	MLX5_XRQC_STATE_GOOD   = 0x0,
4845 	MLX5_XRQC_STATE_ERROR  = 0x1,
4846 };
4847 
4848 enum {
4849 	MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0,
4850 	MLX5_XRQC_TOPOLOGY_TAG_MATCHING        = 0x1,
4851 };
4852 
4853 enum {
4854 	MLX5_XRQC_OFFLOAD_RNDV = 0x1,
4855 };
4856 
4857 struct mlx5_ifc_tag_matching_topology_context_bits {
4858 	u8         log_matching_list_sz[0x4];
4859 	u8         reserved_at_4[0xc];
4860 	u8         append_next_index[0x10];
4861 
4862 	u8         sw_phase_cnt[0x10];
4863 	u8         hw_phase_cnt[0x10];
4864 
4865 	u8         reserved_at_40[0x40];
4866 };
4867 
4868 struct mlx5_ifc_xrqc_bits {
4869 	u8         state[0x4];
4870 	u8         rlkey[0x1];
4871 	u8         reserved_at_5[0xf];
4872 	u8         topology[0x4];
4873 	u8         reserved_at_18[0x4];
4874 	u8         offload[0x4];
4875 
4876 	u8         reserved_at_20[0x8];
4877 	u8         user_index[0x18];
4878 
4879 	u8         reserved_at_40[0x8];
4880 	u8         cqn[0x18];
4881 
4882 	u8         reserved_at_60[0xa0];
4883 
4884 	struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context;
4885 
4886 	u8         reserved_at_180[0x280];
4887 
4888 	struct mlx5_ifc_wq_bits wq;
4889 };
4890 
4891 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits {
4892 	struct mlx5_ifc_modify_field_select_bits modify_field_select;
4893 	struct mlx5_ifc_resize_field_select_bits resize_field_select;
4894 	u8         reserved_at_0[0x20];
4895 };
4896 
4897 union mlx5_ifc_field_select_802_1_r_roce_auto_bits {
4898 	struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp;
4899 	struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp;
4900 	struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np;
4901 	u8         reserved_at_0[0x20];
4902 };
4903 
4904 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
4905 	struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
4906 	struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
4907 	struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
4908 	struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
4909 	struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
4910 	struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
4911 	struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout;
4912 	struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout;
4913 	struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
4914 	struct mlx5_ifc_ib_ext_port_cntrs_grp_data_layout_bits ib_ext_port_cntrs_grp_data_layout;
4915 	struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
4916 	struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs;
4917 	struct mlx5_ifc_phys_layer_recovery_cntrs_bits phys_layer_recovery_cntrs;
4918 	u8         reserved_at_0[0x7c0];
4919 };
4920 
4921 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits {
4922 	struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout;
4923 	u8         reserved_at_0[0x7c0];
4924 };
4925 
4926 union mlx5_ifc_event_auto_bits {
4927 	struct mlx5_ifc_comp_event_bits comp_event;
4928 	struct mlx5_ifc_dct_events_bits dct_events;
4929 	struct mlx5_ifc_qp_events_bits qp_events;
4930 	struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event;
4931 	struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event;
4932 	struct mlx5_ifc_cq_error_bits cq_error;
4933 	struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged;
4934 	struct mlx5_ifc_port_state_change_event_bits port_state_change_event;
4935 	struct mlx5_ifc_gpio_event_bits gpio_event;
4936 	struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event;
4937 	struct mlx5_ifc_stall_vl_event_bits stall_vl_event;
4938 	struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event;
4939 	u8         reserved_at_0[0xe0];
4940 };
4941 
4942 struct mlx5_ifc_health_buffer_bits {
4943 	u8         reserved_at_0[0x100];
4944 
4945 	u8         assert_existptr[0x20];
4946 
4947 	u8         assert_callra[0x20];
4948 
4949 	u8         reserved_at_140[0x20];
4950 
4951 	u8         time[0x20];
4952 
4953 	u8         fw_version[0x20];
4954 
4955 	u8         hw_id[0x20];
4956 
4957 	u8         rfr[0x1];
4958 	u8         reserved_at_1c1[0x3];
4959 	u8         valid[0x1];
4960 	u8         severity[0x3];
4961 	u8         reserved_at_1c8[0x18];
4962 
4963 	u8         irisc_index[0x8];
4964 	u8         synd[0x8];
4965 	u8         ext_synd[0x10];
4966 };
4967 
4968 struct mlx5_ifc_register_loopback_control_bits {
4969 	u8         no_lb[0x1];
4970 	u8         reserved_at_1[0x7];
4971 	u8         port[0x8];
4972 	u8         reserved_at_10[0x10];
4973 
4974 	u8         reserved_at_20[0x60];
4975 };
4976 
4977 enum {
4978 	MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0,
4979 	MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1,
4980 };
4981 
4982 struct mlx5_ifc_teardown_hca_out_bits {
4983 	u8         status[0x8];
4984 	u8         reserved_at_8[0x18];
4985 
4986 	u8         syndrome[0x20];
4987 
4988 	u8         reserved_at_40[0x3f];
4989 
4990 	u8         state[0x1];
4991 };
4992 
4993 enum {
4994 	MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE  = 0x0,
4995 	MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE     = 0x1,
4996 	MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN = 0x2,
4997 };
4998 
4999 struct mlx5_ifc_teardown_hca_in_bits {
5000 	u8         opcode[0x10];
5001 	u8         reserved_at_10[0x10];
5002 
5003 	u8         reserved_at_20[0x10];
5004 	u8         op_mod[0x10];
5005 
5006 	u8         reserved_at_40[0x10];
5007 	u8         profile[0x10];
5008 
5009 	u8         reserved_at_60[0x20];
5010 };
5011 
5012 struct mlx5_ifc_sqerr2rts_qp_out_bits {
5013 	u8         status[0x8];
5014 	u8         reserved_at_8[0x18];
5015 
5016 	u8         syndrome[0x20];
5017 
5018 	u8         reserved_at_40[0x40];
5019 };
5020 
5021 struct mlx5_ifc_sqerr2rts_qp_in_bits {
5022 	u8         opcode[0x10];
5023 	u8         uid[0x10];
5024 
5025 	u8         reserved_at_20[0x10];
5026 	u8         op_mod[0x10];
5027 
5028 	u8         reserved_at_40[0x8];
5029 	u8         qpn[0x18];
5030 
5031 	u8         reserved_at_60[0x20];
5032 
5033 	u8         opt_param_mask[0x20];
5034 
5035 	u8         reserved_at_a0[0x20];
5036 
5037 	struct mlx5_ifc_qpc_bits qpc;
5038 
5039 	u8         reserved_at_800[0x80];
5040 };
5041 
5042 struct mlx5_ifc_sqd2rts_qp_out_bits {
5043 	u8         status[0x8];
5044 	u8         reserved_at_8[0x18];
5045 
5046 	u8         syndrome[0x20];
5047 
5048 	u8         reserved_at_40[0x40];
5049 };
5050 
5051 struct mlx5_ifc_sqd2rts_qp_in_bits {
5052 	u8         opcode[0x10];
5053 	u8         uid[0x10];
5054 
5055 	u8         reserved_at_20[0x10];
5056 	u8         op_mod[0x10];
5057 
5058 	u8         reserved_at_40[0x8];
5059 	u8         qpn[0x18];
5060 
5061 	u8         reserved_at_60[0x20];
5062 
5063 	u8         opt_param_mask[0x20];
5064 
5065 	u8         reserved_at_a0[0x20];
5066 
5067 	struct mlx5_ifc_qpc_bits qpc;
5068 
5069 	u8         reserved_at_800[0x80];
5070 };
5071 
5072 struct mlx5_ifc_set_roce_address_out_bits {
5073 	u8         status[0x8];
5074 	u8         reserved_at_8[0x18];
5075 
5076 	u8         syndrome[0x20];
5077 
5078 	u8         reserved_at_40[0x40];
5079 };
5080 
5081 struct mlx5_ifc_set_roce_address_in_bits {
5082 	u8         opcode[0x10];
5083 	u8         reserved_at_10[0x10];
5084 
5085 	u8         reserved_at_20[0x10];
5086 	u8         op_mod[0x10];
5087 
5088 	u8         roce_address_index[0x10];
5089 	u8         reserved_at_50[0xc];
5090 	u8	   vhca_port_num[0x4];
5091 
5092 	u8         reserved_at_60[0x20];
5093 
5094 	struct mlx5_ifc_roce_addr_layout_bits roce_address;
5095 };
5096 
5097 struct mlx5_ifc_set_mad_demux_out_bits {
5098 	u8         status[0x8];
5099 	u8         reserved_at_8[0x18];
5100 
5101 	u8         syndrome[0x20];
5102 
5103 	u8         reserved_at_40[0x40];
5104 };
5105 
5106 enum {
5107 	MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL   = 0x0,
5108 	MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE  = 0x2,
5109 };
5110 
5111 struct mlx5_ifc_set_mad_demux_in_bits {
5112 	u8         opcode[0x10];
5113 	u8         reserved_at_10[0x10];
5114 
5115 	u8         reserved_at_20[0x10];
5116 	u8         op_mod[0x10];
5117 
5118 	u8         reserved_at_40[0x20];
5119 
5120 	u8         reserved_at_60[0x6];
5121 	u8         demux_mode[0x2];
5122 	u8         reserved_at_68[0x18];
5123 };
5124 
5125 struct mlx5_ifc_set_l2_table_entry_out_bits {
5126 	u8         status[0x8];
5127 	u8         reserved_at_8[0x18];
5128 
5129 	u8         syndrome[0x20];
5130 
5131 	u8         reserved_at_40[0x40];
5132 };
5133 
5134 struct mlx5_ifc_set_l2_table_entry_in_bits {
5135 	u8         opcode[0x10];
5136 	u8         reserved_at_10[0x10];
5137 
5138 	u8         reserved_at_20[0x10];
5139 	u8         op_mod[0x10];
5140 
5141 	u8         reserved_at_40[0x60];
5142 
5143 	u8         reserved_at_a0[0x8];
5144 	u8         table_index[0x18];
5145 
5146 	u8         reserved_at_c0[0x20];
5147 
5148 	u8         reserved_at_e0[0x10];
5149 	u8         silent_mode_valid[0x1];
5150 	u8         silent_mode[0x1];
5151 	u8         reserved_at_f2[0x1];
5152 	u8         vlan_valid[0x1];
5153 	u8         vlan[0xc];
5154 
5155 	struct mlx5_ifc_mac_address_layout_bits mac_address;
5156 
5157 	u8         reserved_at_140[0xc0];
5158 };
5159 
5160 struct mlx5_ifc_set_issi_out_bits {
5161 	u8         status[0x8];
5162 	u8         reserved_at_8[0x18];
5163 
5164 	u8         syndrome[0x20];
5165 
5166 	u8         reserved_at_40[0x40];
5167 };
5168 
5169 struct mlx5_ifc_set_issi_in_bits {
5170 	u8         opcode[0x10];
5171 	u8         reserved_at_10[0x10];
5172 
5173 	u8         reserved_at_20[0x10];
5174 	u8         op_mod[0x10];
5175 
5176 	u8         reserved_at_40[0x10];
5177 	u8         current_issi[0x10];
5178 
5179 	u8         reserved_at_60[0x20];
5180 };
5181 
5182 struct mlx5_ifc_set_hca_cap_out_bits {
5183 	u8         status[0x8];
5184 	u8         reserved_at_8[0x18];
5185 
5186 	u8         syndrome[0x20];
5187 
5188 	u8         reserved_at_40[0x40];
5189 };
5190 
5191 struct mlx5_ifc_set_hca_cap_in_bits {
5192 	u8         opcode[0x10];
5193 	u8         reserved_at_10[0x10];
5194 
5195 	u8         reserved_at_20[0x10];
5196 	u8         op_mod[0x10];
5197 
5198 	u8         other_function[0x1];
5199 	u8         ec_vf_function[0x1];
5200 	u8         reserved_at_42[0x1];
5201 	u8         function_id_type[0x1];
5202 	u8         reserved_at_44[0xc];
5203 	u8         function_id[0x10];
5204 
5205 	u8         reserved_at_60[0x20];
5206 
5207 	union mlx5_ifc_hca_cap_union_bits capability;
5208 };
5209 
5210 enum {
5211 	MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION    = 0x0,
5212 	MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG  = 0x1,
5213 	MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST    = 0x2,
5214 	MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS    = 0x3,
5215 	MLX5_SET_FTE_MODIFY_ENABLE_MASK_IPSEC_OBJ_ID    = 0x4
5216 };
5217 
5218 struct mlx5_ifc_set_fte_out_bits {
5219 	u8         status[0x8];
5220 	u8         reserved_at_8[0x18];
5221 
5222 	u8         syndrome[0x20];
5223 
5224 	u8         reserved_at_40[0x40];
5225 };
5226 
5227 struct mlx5_ifc_set_fte_in_bits {
5228 	u8         opcode[0x10];
5229 	u8         reserved_at_10[0x10];
5230 
5231 	u8         reserved_at_20[0x10];
5232 	u8         op_mod[0x10];
5233 
5234 	u8         other_vport[0x1];
5235 	u8         reserved_at_41[0xf];
5236 	u8         vport_number[0x10];
5237 
5238 	u8         reserved_at_60[0x20];
5239 
5240 	u8         table_type[0x8];
5241 	u8         reserved_at_88[0x18];
5242 
5243 	u8         reserved_at_a0[0x8];
5244 	u8         table_id[0x18];
5245 
5246 	u8         ignore_flow_level[0x1];
5247 	u8         reserved_at_c1[0x17];
5248 	u8         modify_enable_mask[0x8];
5249 
5250 	u8         reserved_at_e0[0x20];
5251 
5252 	u8         flow_index[0x20];
5253 
5254 	u8         reserved_at_120[0xe0];
5255 
5256 	struct mlx5_ifc_flow_context_bits flow_context;
5257 };
5258 
5259 struct mlx5_ifc_dest_format_bits {
5260 	u8         destination_type[0x8];
5261 	u8         destination_id[0x18];
5262 
5263 	u8         destination_eswitch_owner_vhca_id_valid[0x1];
5264 	u8         packet_reformat[0x1];
5265 	u8         reserved_at_22[0xe];
5266 	u8         destination_eswitch_owner_vhca_id[0x10];
5267 };
5268 
5269 struct mlx5_ifc_rts2rts_qp_out_bits {
5270 	u8         status[0x8];
5271 	u8         reserved_at_8[0x18];
5272 
5273 	u8         syndrome[0x20];
5274 
5275 	u8         reserved_at_40[0x20];
5276 	u8         ece[0x20];
5277 };
5278 
5279 struct mlx5_ifc_rts2rts_qp_in_bits {
5280 	u8         opcode[0x10];
5281 	u8         uid[0x10];
5282 
5283 	u8         reserved_at_20[0x10];
5284 	u8         op_mod[0x10];
5285 
5286 	u8         reserved_at_40[0x8];
5287 	u8         qpn[0x18];
5288 
5289 	u8         reserved_at_60[0x20];
5290 
5291 	u8         opt_param_mask[0x20];
5292 
5293 	u8         ece[0x20];
5294 
5295 	struct mlx5_ifc_qpc_bits qpc;
5296 
5297 	u8         reserved_at_800[0x80];
5298 };
5299 
5300 struct mlx5_ifc_rtr2rts_qp_out_bits {
5301 	u8         status[0x8];
5302 	u8         reserved_at_8[0x18];
5303 
5304 	u8         syndrome[0x20];
5305 
5306 	u8         reserved_at_40[0x20];
5307 	u8         ece[0x20];
5308 };
5309 
5310 struct mlx5_ifc_rtr2rts_qp_in_bits {
5311 	u8         opcode[0x10];
5312 	u8         uid[0x10];
5313 
5314 	u8         reserved_at_20[0x10];
5315 	u8         op_mod[0x10];
5316 
5317 	u8         reserved_at_40[0x8];
5318 	u8         qpn[0x18];
5319 
5320 	u8         reserved_at_60[0x20];
5321 
5322 	u8         opt_param_mask[0x20];
5323 
5324 	u8         ece[0x20];
5325 
5326 	struct mlx5_ifc_qpc_bits qpc;
5327 
5328 	u8         reserved_at_800[0x80];
5329 };
5330 
5331 struct mlx5_ifc_rst2init_qp_out_bits {
5332 	u8         status[0x8];
5333 	u8         reserved_at_8[0x18];
5334 
5335 	u8         syndrome[0x20];
5336 
5337 	u8         reserved_at_40[0x20];
5338 	u8         ece[0x20];
5339 };
5340 
5341 struct mlx5_ifc_rst2init_qp_in_bits {
5342 	u8         opcode[0x10];
5343 	u8         uid[0x10];
5344 
5345 	u8         reserved_at_20[0x10];
5346 	u8         op_mod[0x10];
5347 
5348 	u8         reserved_at_40[0x8];
5349 	u8         qpn[0x18];
5350 
5351 	u8         reserved_at_60[0x20];
5352 
5353 	u8         opt_param_mask[0x20];
5354 
5355 	u8         ece[0x20];
5356 
5357 	struct mlx5_ifc_qpc_bits qpc;
5358 
5359 	u8         reserved_at_800[0x80];
5360 };
5361 
5362 struct mlx5_ifc_query_xrq_out_bits {
5363 	u8         status[0x8];
5364 	u8         reserved_at_8[0x18];
5365 
5366 	u8         syndrome[0x20];
5367 
5368 	u8         reserved_at_40[0x40];
5369 
5370 	struct mlx5_ifc_xrqc_bits xrq_context;
5371 };
5372 
5373 struct mlx5_ifc_query_xrq_in_bits {
5374 	u8         opcode[0x10];
5375 	u8         reserved_at_10[0x10];
5376 
5377 	u8         reserved_at_20[0x10];
5378 	u8         op_mod[0x10];
5379 
5380 	u8         reserved_at_40[0x8];
5381 	u8         xrqn[0x18];
5382 
5383 	u8         reserved_at_60[0x20];
5384 };
5385 
5386 struct mlx5_ifc_query_xrc_srq_out_bits {
5387 	u8         status[0x8];
5388 	u8         reserved_at_8[0x18];
5389 
5390 	u8         syndrome[0x20];
5391 
5392 	u8         reserved_at_40[0x40];
5393 
5394 	struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
5395 
5396 	u8         reserved_at_280[0x600];
5397 
5398 	u8         pas[][0x40];
5399 };
5400 
5401 struct mlx5_ifc_query_xrc_srq_in_bits {
5402 	u8         opcode[0x10];
5403 	u8         reserved_at_10[0x10];
5404 
5405 	u8         reserved_at_20[0x10];
5406 	u8         op_mod[0x10];
5407 
5408 	u8         reserved_at_40[0x8];
5409 	u8         xrc_srqn[0x18];
5410 
5411 	u8         reserved_at_60[0x20];
5412 };
5413 
5414 enum {
5415 	MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN  = 0x0,
5416 	MLX5_QUERY_VPORT_STATE_OUT_STATE_UP    = 0x1,
5417 };
5418 
5419 struct mlx5_ifc_query_vport_state_out_bits {
5420 	u8         status[0x8];
5421 	u8         reserved_at_8[0x18];
5422 
5423 	u8         syndrome[0x20];
5424 
5425 	u8         reserved_at_40[0x20];
5426 
5427 	u8         reserved_at_60[0x18];
5428 	u8         admin_state[0x4];
5429 	u8         state[0x4];
5430 };
5431 
5432 struct mlx5_ifc_array1024_auto_bits {
5433 	u8         array1024_auto[32][0x20];
5434 };
5435 
5436 struct mlx5_ifc_query_vuid_in_bits {
5437 	u8         opcode[0x10];
5438 	u8         uid[0x10];
5439 
5440 	u8         reserved_at_20[0x40];
5441 
5442 	u8         query_vfs_vuid[0x1];
5443 	u8         data_direct[0x1];
5444 	u8         reserved_at_62[0xe];
5445 	u8         vhca_id[0x10];
5446 };
5447 
5448 struct mlx5_ifc_query_vuid_out_bits {
5449 	u8        status[0x8];
5450 	u8        reserved_at_8[0x18];
5451 
5452 	u8        syndrome[0x20];
5453 
5454 	u8        reserved_at_40[0x1a0];
5455 
5456 	u8        reserved_at_1e0[0x10];
5457 	u8        num_of_entries[0x10];
5458 
5459 	struct mlx5_ifc_array1024_auto_bits vuid[];
5460 };
5461 
5462 enum {
5463 	MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT  = 0x0,
5464 	MLX5_VPORT_STATE_OP_MOD_ESW_VPORT   = 0x1,
5465 	MLX5_VPORT_STATE_OP_MOD_UPLINK      = 0x2,
5466 };
5467 
5468 struct mlx5_ifc_arm_monitor_counter_in_bits {
5469 	u8         opcode[0x10];
5470 	u8         uid[0x10];
5471 
5472 	u8         reserved_at_20[0x10];
5473 	u8         op_mod[0x10];
5474 
5475 	u8         reserved_at_40[0x20];
5476 
5477 	u8         reserved_at_60[0x20];
5478 };
5479 
5480 struct mlx5_ifc_arm_monitor_counter_out_bits {
5481 	u8         status[0x8];
5482 	u8         reserved_at_8[0x18];
5483 
5484 	u8         syndrome[0x20];
5485 
5486 	u8         reserved_at_40[0x40];
5487 };
5488 
5489 enum {
5490 	MLX5_QUERY_MONITOR_CNT_TYPE_PPCNT     = 0x0,
5491 	MLX5_QUERY_MONITOR_CNT_TYPE_Q_COUNTER = 0x1,
5492 };
5493 
5494 enum mlx5_monitor_counter_ppcnt {
5495 	MLX5_QUERY_MONITOR_PPCNT_IN_RANGE_LENGTH_ERRORS      = 0x0,
5496 	MLX5_QUERY_MONITOR_PPCNT_OUT_OF_RANGE_LENGTH_FIELD   = 0x1,
5497 	MLX5_QUERY_MONITOR_PPCNT_FRAME_TOO_LONG_ERRORS       = 0x2,
5498 	MLX5_QUERY_MONITOR_PPCNT_FRAME_CHECK_SEQUENCE_ERRORS = 0x3,
5499 	MLX5_QUERY_MONITOR_PPCNT_ALIGNMENT_ERRORS            = 0x4,
5500 	MLX5_QUERY_MONITOR_PPCNT_IF_OUT_DISCARDS             = 0x5,
5501 };
5502 
5503 enum {
5504 	MLX5_QUERY_MONITOR_Q_COUNTER_RX_OUT_OF_BUFFER     = 0x4,
5505 };
5506 
5507 struct mlx5_ifc_monitor_counter_output_bits {
5508 	u8         reserved_at_0[0x4];
5509 	u8         type[0x4];
5510 	u8         reserved_at_8[0x8];
5511 	u8         counter[0x10];
5512 
5513 	u8         counter_group_id[0x20];
5514 };
5515 
5516 #define MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 (6)
5517 #define MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1    (1)
5518 #define MLX5_CMD_SET_MONITOR_NUM_COUNTER (MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 +\
5519 					  MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1)
5520 
5521 struct mlx5_ifc_set_monitor_counter_in_bits {
5522 	u8         opcode[0x10];
5523 	u8         uid[0x10];
5524 
5525 	u8         reserved_at_20[0x10];
5526 	u8         op_mod[0x10];
5527 
5528 	u8         reserved_at_40[0x10];
5529 	u8         num_of_counters[0x10];
5530 
5531 	u8         reserved_at_60[0x20];
5532 
5533 	struct mlx5_ifc_monitor_counter_output_bits monitor_counter[MLX5_CMD_SET_MONITOR_NUM_COUNTER];
5534 };
5535 
5536 struct mlx5_ifc_set_monitor_counter_out_bits {
5537 	u8         status[0x8];
5538 	u8         reserved_at_8[0x18];
5539 
5540 	u8         syndrome[0x20];
5541 
5542 	u8         reserved_at_40[0x40];
5543 };
5544 
5545 struct mlx5_ifc_query_vport_state_in_bits {
5546 	u8         opcode[0x10];
5547 	u8         reserved_at_10[0x10];
5548 
5549 	u8         reserved_at_20[0x10];
5550 	u8         op_mod[0x10];
5551 
5552 	u8         other_vport[0x1];
5553 	u8         reserved_at_41[0xf];
5554 	u8         vport_number[0x10];
5555 
5556 	u8         reserved_at_60[0x20];
5557 };
5558 
5559 struct mlx5_ifc_query_vnic_env_out_bits {
5560 	u8         status[0x8];
5561 	u8         reserved_at_8[0x18];
5562 
5563 	u8         syndrome[0x20];
5564 
5565 	u8         reserved_at_40[0x40];
5566 
5567 	struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env;
5568 };
5569 
5570 enum {
5571 	MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS  = 0x0,
5572 };
5573 
5574 struct mlx5_ifc_query_vnic_env_in_bits {
5575 	u8         opcode[0x10];
5576 	u8         reserved_at_10[0x10];
5577 
5578 	u8         reserved_at_20[0x10];
5579 	u8         op_mod[0x10];
5580 
5581 	u8         other_vport[0x1];
5582 	u8         reserved_at_41[0xf];
5583 	u8         vport_number[0x10];
5584 
5585 	u8         reserved_at_60[0x20];
5586 };
5587 
5588 struct mlx5_ifc_query_vport_counter_out_bits {
5589 	u8         status[0x8];
5590 	u8         reserved_at_8[0x18];
5591 
5592 	u8         syndrome[0x20];
5593 
5594 	u8         reserved_at_40[0x40];
5595 
5596 	struct mlx5_ifc_traffic_counter_bits received_errors;
5597 
5598 	struct mlx5_ifc_traffic_counter_bits transmit_errors;
5599 
5600 	struct mlx5_ifc_traffic_counter_bits received_ib_unicast;
5601 
5602 	struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast;
5603 
5604 	struct mlx5_ifc_traffic_counter_bits received_ib_multicast;
5605 
5606 	struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast;
5607 
5608 	struct mlx5_ifc_traffic_counter_bits received_eth_broadcast;
5609 
5610 	struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast;
5611 
5612 	struct mlx5_ifc_traffic_counter_bits received_eth_unicast;
5613 
5614 	struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast;
5615 
5616 	struct mlx5_ifc_traffic_counter_bits received_eth_multicast;
5617 
5618 	struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast;
5619 
5620 	struct mlx5_ifc_traffic_counter_bits local_loopback;
5621 
5622 	u8         reserved_at_700[0x980];
5623 };
5624 
5625 enum {
5626 	MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS  = 0x0,
5627 };
5628 
5629 struct mlx5_ifc_query_vport_counter_in_bits {
5630 	u8         opcode[0x10];
5631 	u8         reserved_at_10[0x10];
5632 
5633 	u8         reserved_at_20[0x10];
5634 	u8         op_mod[0x10];
5635 
5636 	u8         other_vport[0x1];
5637 	u8         reserved_at_41[0xb];
5638 	u8	   port_num[0x4];
5639 	u8         vport_number[0x10];
5640 
5641 	u8         reserved_at_60[0x60];
5642 
5643 	u8         clear[0x1];
5644 	u8         reserved_at_c1[0x1f];
5645 
5646 	u8         reserved_at_e0[0x20];
5647 };
5648 
5649 struct mlx5_ifc_query_tis_out_bits {
5650 	u8         status[0x8];
5651 	u8         reserved_at_8[0x18];
5652 
5653 	u8         syndrome[0x20];
5654 
5655 	u8         reserved_at_40[0x40];
5656 
5657 	struct mlx5_ifc_tisc_bits tis_context;
5658 };
5659 
5660 struct mlx5_ifc_query_tis_in_bits {
5661 	u8         opcode[0x10];
5662 	u8         reserved_at_10[0x10];
5663 
5664 	u8         reserved_at_20[0x10];
5665 	u8         op_mod[0x10];
5666 
5667 	u8         reserved_at_40[0x8];
5668 	u8         tisn[0x18];
5669 
5670 	u8         reserved_at_60[0x20];
5671 };
5672 
5673 struct mlx5_ifc_query_tir_out_bits {
5674 	u8         status[0x8];
5675 	u8         reserved_at_8[0x18];
5676 
5677 	u8         syndrome[0x20];
5678 
5679 	u8         reserved_at_40[0xc0];
5680 
5681 	struct mlx5_ifc_tirc_bits tir_context;
5682 };
5683 
5684 struct mlx5_ifc_query_tir_in_bits {
5685 	u8         opcode[0x10];
5686 	u8         reserved_at_10[0x10];
5687 
5688 	u8         reserved_at_20[0x10];
5689 	u8         op_mod[0x10];
5690 
5691 	u8         reserved_at_40[0x8];
5692 	u8         tirn[0x18];
5693 
5694 	u8         reserved_at_60[0x20];
5695 };
5696 
5697 struct mlx5_ifc_query_srq_out_bits {
5698 	u8         status[0x8];
5699 	u8         reserved_at_8[0x18];
5700 
5701 	u8         syndrome[0x20];
5702 
5703 	u8         reserved_at_40[0x40];
5704 
5705 	struct mlx5_ifc_srqc_bits srq_context_entry;
5706 
5707 	u8         reserved_at_280[0x600];
5708 
5709 	u8         pas[][0x40];
5710 };
5711 
5712 struct mlx5_ifc_query_srq_in_bits {
5713 	u8         opcode[0x10];
5714 	u8         reserved_at_10[0x10];
5715 
5716 	u8         reserved_at_20[0x10];
5717 	u8         op_mod[0x10];
5718 
5719 	u8         reserved_at_40[0x8];
5720 	u8         srqn[0x18];
5721 
5722 	u8         reserved_at_60[0x20];
5723 };
5724 
5725 struct mlx5_ifc_query_sq_out_bits {
5726 	u8         status[0x8];
5727 	u8         reserved_at_8[0x18];
5728 
5729 	u8         syndrome[0x20];
5730 
5731 	u8         reserved_at_40[0xc0];
5732 
5733 	struct mlx5_ifc_sqc_bits sq_context;
5734 };
5735 
5736 struct mlx5_ifc_query_sq_in_bits {
5737 	u8         opcode[0x10];
5738 	u8         reserved_at_10[0x10];
5739 
5740 	u8         reserved_at_20[0x10];
5741 	u8         op_mod[0x10];
5742 
5743 	u8         reserved_at_40[0x8];
5744 	u8         sqn[0x18];
5745 
5746 	u8         reserved_at_60[0x20];
5747 };
5748 
5749 struct mlx5_ifc_query_special_contexts_out_bits {
5750 	u8         status[0x8];
5751 	u8         reserved_at_8[0x18];
5752 
5753 	u8         syndrome[0x20];
5754 
5755 	u8         dump_fill_mkey[0x20];
5756 
5757 	u8         resd_lkey[0x20];
5758 
5759 	u8         null_mkey[0x20];
5760 
5761 	u8	   terminate_scatter_list_mkey[0x20];
5762 
5763 	u8	   repeated_mkey[0x20];
5764 
5765 	u8         reserved_at_a0[0x20];
5766 };
5767 
5768 struct mlx5_ifc_query_special_contexts_in_bits {
5769 	u8         opcode[0x10];
5770 	u8         reserved_at_10[0x10];
5771 
5772 	u8         reserved_at_20[0x10];
5773 	u8         op_mod[0x10];
5774 
5775 	u8         reserved_at_40[0x40];
5776 };
5777 
5778 struct mlx5_ifc_query_scheduling_element_out_bits {
5779 	u8         opcode[0x10];
5780 	u8         reserved_at_10[0x10];
5781 
5782 	u8         reserved_at_20[0x10];
5783 	u8         op_mod[0x10];
5784 
5785 	u8         reserved_at_40[0xc0];
5786 
5787 	struct mlx5_ifc_scheduling_context_bits scheduling_context;
5788 
5789 	u8         reserved_at_300[0x100];
5790 };
5791 
5792 enum {
5793 	SCHEDULING_HIERARCHY_E_SWITCH = 0x2,
5794 	SCHEDULING_HIERARCHY_NIC = 0x3,
5795 };
5796 
5797 struct mlx5_ifc_query_scheduling_element_in_bits {
5798 	u8         opcode[0x10];
5799 	u8         reserved_at_10[0x10];
5800 
5801 	u8         reserved_at_20[0x10];
5802 	u8         op_mod[0x10];
5803 
5804 	u8         scheduling_hierarchy[0x8];
5805 	u8         reserved_at_48[0x18];
5806 
5807 	u8         scheduling_element_id[0x20];
5808 
5809 	u8         reserved_at_80[0x180];
5810 };
5811 
5812 struct mlx5_ifc_query_rqt_out_bits {
5813 	u8         status[0x8];
5814 	u8         reserved_at_8[0x18];
5815 
5816 	u8         syndrome[0x20];
5817 
5818 	u8         reserved_at_40[0xc0];
5819 
5820 	struct mlx5_ifc_rqtc_bits rqt_context;
5821 };
5822 
5823 struct mlx5_ifc_query_rqt_in_bits {
5824 	u8         opcode[0x10];
5825 	u8         reserved_at_10[0x10];
5826 
5827 	u8         reserved_at_20[0x10];
5828 	u8         op_mod[0x10];
5829 
5830 	u8         reserved_at_40[0x8];
5831 	u8         rqtn[0x18];
5832 
5833 	u8         reserved_at_60[0x20];
5834 };
5835 
5836 struct mlx5_ifc_query_rq_out_bits {
5837 	u8         status[0x8];
5838 	u8         reserved_at_8[0x18];
5839 
5840 	u8         syndrome[0x20];
5841 
5842 	u8         reserved_at_40[0xc0];
5843 
5844 	struct mlx5_ifc_rqc_bits rq_context;
5845 };
5846 
5847 struct mlx5_ifc_query_rq_in_bits {
5848 	u8         opcode[0x10];
5849 	u8         reserved_at_10[0x10];
5850 
5851 	u8         reserved_at_20[0x10];
5852 	u8         op_mod[0x10];
5853 
5854 	u8         reserved_at_40[0x8];
5855 	u8         rqn[0x18];
5856 
5857 	u8         reserved_at_60[0x20];
5858 };
5859 
5860 struct mlx5_ifc_query_roce_address_out_bits {
5861 	u8         status[0x8];
5862 	u8         reserved_at_8[0x18];
5863 
5864 	u8         syndrome[0x20];
5865 
5866 	u8         reserved_at_40[0x40];
5867 
5868 	struct mlx5_ifc_roce_addr_layout_bits roce_address;
5869 };
5870 
5871 struct mlx5_ifc_query_roce_address_in_bits {
5872 	u8         opcode[0x10];
5873 	u8         reserved_at_10[0x10];
5874 
5875 	u8         reserved_at_20[0x10];
5876 	u8         op_mod[0x10];
5877 
5878 	u8         roce_address_index[0x10];
5879 	u8         reserved_at_50[0xc];
5880 	u8	   vhca_port_num[0x4];
5881 
5882 	u8         reserved_at_60[0x20];
5883 };
5884 
5885 struct mlx5_ifc_query_rmp_out_bits {
5886 	u8         status[0x8];
5887 	u8         reserved_at_8[0x18];
5888 
5889 	u8         syndrome[0x20];
5890 
5891 	u8         reserved_at_40[0xc0];
5892 
5893 	struct mlx5_ifc_rmpc_bits rmp_context;
5894 };
5895 
5896 struct mlx5_ifc_query_rmp_in_bits {
5897 	u8         opcode[0x10];
5898 	u8         reserved_at_10[0x10];
5899 
5900 	u8         reserved_at_20[0x10];
5901 	u8         op_mod[0x10];
5902 
5903 	u8         reserved_at_40[0x8];
5904 	u8         rmpn[0x18];
5905 
5906 	u8         reserved_at_60[0x20];
5907 };
5908 
5909 struct mlx5_ifc_cqe_error_syndrome_bits {
5910 	u8         hw_error_syndrome[0x8];
5911 	u8         hw_syndrome_type[0x4];
5912 	u8         reserved_at_c[0x4];
5913 	u8         vendor_error_syndrome[0x8];
5914 	u8         syndrome[0x8];
5915 };
5916 
5917 struct mlx5_ifc_qp_context_extension_bits {
5918 	u8         reserved_at_0[0x60];
5919 
5920 	struct mlx5_ifc_cqe_error_syndrome_bits error_syndrome;
5921 
5922 	u8         reserved_at_80[0x580];
5923 };
5924 
5925 struct mlx5_ifc_qpc_extension_and_pas_list_in_bits {
5926 	struct mlx5_ifc_qp_context_extension_bits qpc_data_extension;
5927 
5928 	u8         pas[0][0x40];
5929 };
5930 
5931 struct mlx5_ifc_qp_pas_list_in_bits {
5932 	struct mlx5_ifc_cmd_pas_bits pas[0];
5933 };
5934 
5935 union mlx5_ifc_qp_pas_or_qpc_ext_and_pas_bits {
5936 	struct mlx5_ifc_qp_pas_list_in_bits qp_pas_list;
5937 	struct mlx5_ifc_qpc_extension_and_pas_list_in_bits qpc_ext_and_pas_list;
5938 };
5939 
5940 struct mlx5_ifc_query_qp_out_bits {
5941 	u8         status[0x8];
5942 	u8         reserved_at_8[0x18];
5943 
5944 	u8         syndrome[0x20];
5945 
5946 	u8         reserved_at_40[0x40];
5947 
5948 	u8         opt_param_mask[0x20];
5949 
5950 	u8         ece[0x20];
5951 
5952 	struct mlx5_ifc_qpc_bits qpc;
5953 
5954 	u8         reserved_at_800[0x80];
5955 
5956 	union mlx5_ifc_qp_pas_or_qpc_ext_and_pas_bits qp_pas_or_qpc_ext_and_pas;
5957 };
5958 
5959 struct mlx5_ifc_query_qp_in_bits {
5960 	u8         opcode[0x10];
5961 	u8         reserved_at_10[0x10];
5962 
5963 	u8         reserved_at_20[0x10];
5964 	u8         op_mod[0x10];
5965 
5966 	u8         qpc_ext[0x1];
5967 	u8         reserved_at_41[0x7];
5968 	u8         qpn[0x18];
5969 
5970 	u8         reserved_at_60[0x20];
5971 };
5972 
5973 struct mlx5_ifc_query_q_counter_out_bits {
5974 	u8         status[0x8];
5975 	u8         reserved_at_8[0x18];
5976 
5977 	u8         syndrome[0x20];
5978 
5979 	u8         reserved_at_40[0x40];
5980 
5981 	u8         rx_write_requests[0x20];
5982 
5983 	u8         reserved_at_a0[0x20];
5984 
5985 	u8         rx_read_requests[0x20];
5986 
5987 	u8         reserved_at_e0[0x20];
5988 
5989 	u8         rx_atomic_requests[0x20];
5990 
5991 	u8         reserved_at_120[0x20];
5992 
5993 	u8         rx_dct_connect[0x20];
5994 
5995 	u8         reserved_at_160[0x20];
5996 
5997 	u8         out_of_buffer[0x20];
5998 
5999 	u8         reserved_at_1a0[0x20];
6000 
6001 	u8         out_of_sequence[0x20];
6002 
6003 	u8         reserved_at_1e0[0x20];
6004 
6005 	u8         duplicate_request[0x20];
6006 
6007 	u8         reserved_at_220[0x20];
6008 
6009 	u8         rnr_nak_retry_err[0x20];
6010 
6011 	u8         reserved_at_260[0x20];
6012 
6013 	u8         packet_seq_err[0x20];
6014 
6015 	u8         reserved_at_2a0[0x20];
6016 
6017 	u8         implied_nak_seq_err[0x20];
6018 
6019 	u8         reserved_at_2e0[0x20];
6020 
6021 	u8         local_ack_timeout_err[0x20];
6022 
6023 	u8         reserved_at_320[0x60];
6024 
6025 	u8         req_rnr_retries_exceeded[0x20];
6026 
6027 	u8         reserved_at_3a0[0x20];
6028 
6029 	u8         resp_local_length_error[0x20];
6030 
6031 	u8         req_local_length_error[0x20];
6032 
6033 	u8         resp_local_qp_error[0x20];
6034 
6035 	u8         local_operation_error[0x20];
6036 
6037 	u8         resp_local_protection[0x20];
6038 
6039 	u8         req_local_protection[0x20];
6040 
6041 	u8         resp_cqe_error[0x20];
6042 
6043 	u8         req_cqe_error[0x20];
6044 
6045 	u8         req_mw_binding[0x20];
6046 
6047 	u8         req_bad_response[0x20];
6048 
6049 	u8         req_remote_invalid_request[0x20];
6050 
6051 	u8         resp_remote_invalid_request[0x20];
6052 
6053 	u8         req_remote_access_errors[0x20];
6054 
6055 	u8	   resp_remote_access_errors[0x20];
6056 
6057 	u8         req_remote_operation_errors[0x20];
6058 
6059 	u8         req_transport_retries_exceeded[0x20];
6060 
6061 	u8         cq_overflow[0x20];
6062 
6063 	u8         resp_cqe_flush_error[0x20];
6064 
6065 	u8         req_cqe_flush_error[0x20];
6066 
6067 	u8         reserved_at_620[0x20];
6068 
6069 	u8         roce_adp_retrans[0x20];
6070 
6071 	u8         roce_adp_retrans_to[0x20];
6072 
6073 	u8         roce_slow_restart[0x20];
6074 
6075 	u8         roce_slow_restart_cnps[0x20];
6076 
6077 	u8         roce_slow_restart_trans[0x20];
6078 
6079 	u8         reserved_at_6e0[0x120];
6080 };
6081 
6082 struct mlx5_ifc_query_q_counter_in_bits {
6083 	u8         opcode[0x10];
6084 	u8         reserved_at_10[0x10];
6085 
6086 	u8         reserved_at_20[0x10];
6087 	u8         op_mod[0x10];
6088 
6089 	u8         other_vport[0x1];
6090 	u8         reserved_at_41[0xf];
6091 	u8         vport_number[0x10];
6092 
6093 	u8         reserved_at_60[0x60];
6094 
6095 	u8         clear[0x1];
6096 	u8         aggregate[0x1];
6097 	u8         reserved_at_c2[0x1e];
6098 
6099 	u8         reserved_at_e0[0x18];
6100 	u8         counter_set_id[0x8];
6101 };
6102 
6103 struct mlx5_ifc_query_pages_out_bits {
6104 	u8         status[0x8];
6105 	u8         reserved_at_8[0x18];
6106 
6107 	u8         syndrome[0x20];
6108 
6109 	u8         embedded_cpu_function[0x1];
6110 	u8         reserved_at_41[0xf];
6111 	u8         function_id[0x10];
6112 
6113 	u8         num_pages[0x20];
6114 };
6115 
6116 enum {
6117 	MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES     = 0x1,
6118 	MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES     = 0x2,
6119 	MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES  = 0x3,
6120 };
6121 
6122 struct mlx5_ifc_query_pages_in_bits {
6123 	u8         opcode[0x10];
6124 	u8         reserved_at_10[0x10];
6125 
6126 	u8         reserved_at_20[0x10];
6127 	u8         op_mod[0x10];
6128 
6129 	u8         embedded_cpu_function[0x1];
6130 	u8         reserved_at_41[0xf];
6131 	u8         function_id[0x10];
6132 
6133 	u8         reserved_at_60[0x20];
6134 };
6135 
6136 struct mlx5_ifc_query_nic_vport_context_out_bits {
6137 	u8         status[0x8];
6138 	u8         reserved_at_8[0x18];
6139 
6140 	u8         syndrome[0x20];
6141 
6142 	u8         reserved_at_40[0x40];
6143 
6144 	struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
6145 };
6146 
6147 struct mlx5_ifc_query_nic_vport_context_in_bits {
6148 	u8         opcode[0x10];
6149 	u8         reserved_at_10[0x10];
6150 
6151 	u8         reserved_at_20[0x10];
6152 	u8         op_mod[0x10];
6153 
6154 	u8         other_vport[0x1];
6155 	u8         reserved_at_41[0xf];
6156 	u8         vport_number[0x10];
6157 
6158 	u8         reserved_at_60[0x5];
6159 	u8         allowed_list_type[0x3];
6160 	u8         reserved_at_68[0x18];
6161 };
6162 
6163 struct mlx5_ifc_query_mkey_out_bits {
6164 	u8         status[0x8];
6165 	u8         reserved_at_8[0x18];
6166 
6167 	u8         syndrome[0x20];
6168 
6169 	u8         reserved_at_40[0x40];
6170 
6171 	struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
6172 
6173 	u8         reserved_at_280[0x600];
6174 
6175 	u8         bsf0_klm0_pas_mtt0_1[16][0x8];
6176 
6177 	u8         bsf1_klm1_pas_mtt2_3[16][0x8];
6178 };
6179 
6180 struct mlx5_ifc_query_mkey_in_bits {
6181 	u8         opcode[0x10];
6182 	u8         reserved_at_10[0x10];
6183 
6184 	u8         reserved_at_20[0x10];
6185 	u8         op_mod[0x10];
6186 
6187 	u8         reserved_at_40[0x8];
6188 	u8         mkey_index[0x18];
6189 
6190 	u8         pg_access[0x1];
6191 	u8         reserved_at_61[0x1f];
6192 };
6193 
6194 struct mlx5_ifc_query_mad_demux_out_bits {
6195 	u8         status[0x8];
6196 	u8         reserved_at_8[0x18];
6197 
6198 	u8         syndrome[0x20];
6199 
6200 	u8         reserved_at_40[0x40];
6201 
6202 	u8         mad_dumux_parameters_block[0x20];
6203 };
6204 
6205 struct mlx5_ifc_query_mad_demux_in_bits {
6206 	u8         opcode[0x10];
6207 	u8         reserved_at_10[0x10];
6208 
6209 	u8         reserved_at_20[0x10];
6210 	u8         op_mod[0x10];
6211 
6212 	u8         reserved_at_40[0x40];
6213 };
6214 
6215 struct mlx5_ifc_query_l2_table_entry_out_bits {
6216 	u8         status[0x8];
6217 	u8         reserved_at_8[0x18];
6218 
6219 	u8         syndrome[0x20];
6220 
6221 	u8         reserved_at_40[0xa0];
6222 
6223 	u8         reserved_at_e0[0x13];
6224 	u8         vlan_valid[0x1];
6225 	u8         vlan[0xc];
6226 
6227 	struct mlx5_ifc_mac_address_layout_bits mac_address;
6228 
6229 	u8         reserved_at_140[0xc0];
6230 };
6231 
6232 struct mlx5_ifc_query_l2_table_entry_in_bits {
6233 	u8         opcode[0x10];
6234 	u8         reserved_at_10[0x10];
6235 
6236 	u8         reserved_at_20[0x10];
6237 	u8         op_mod[0x10];
6238 
6239 	u8         reserved_at_40[0x60];
6240 
6241 	u8         reserved_at_a0[0x8];
6242 	u8         table_index[0x18];
6243 
6244 	u8         reserved_at_c0[0x140];
6245 };
6246 
6247 struct mlx5_ifc_query_issi_out_bits {
6248 	u8         status[0x8];
6249 	u8         reserved_at_8[0x18];
6250 
6251 	u8         syndrome[0x20];
6252 
6253 	u8         reserved_at_40[0x10];
6254 	u8         current_issi[0x10];
6255 
6256 	u8         reserved_at_60[0xa0];
6257 
6258 	u8         reserved_at_100[76][0x8];
6259 	u8         supported_issi_dw0[0x20];
6260 };
6261 
6262 struct mlx5_ifc_query_issi_in_bits {
6263 	u8         opcode[0x10];
6264 	u8         reserved_at_10[0x10];
6265 
6266 	u8         reserved_at_20[0x10];
6267 	u8         op_mod[0x10];
6268 
6269 	u8         reserved_at_40[0x40];
6270 };
6271 
6272 struct mlx5_ifc_set_driver_version_out_bits {
6273 	u8         status[0x8];
6274 	u8         reserved_0[0x18];
6275 
6276 	u8         syndrome[0x20];
6277 	u8         reserved_1[0x40];
6278 };
6279 
6280 struct mlx5_ifc_set_driver_version_in_bits {
6281 	u8         opcode[0x10];
6282 	u8         reserved_0[0x10];
6283 
6284 	u8         reserved_1[0x10];
6285 	u8         op_mod[0x10];
6286 
6287 	u8         reserved_2[0x40];
6288 	u8         driver_version[64][0x8];
6289 };
6290 
6291 struct mlx5_ifc_query_hca_vport_pkey_out_bits {
6292 	u8         status[0x8];
6293 	u8         reserved_at_8[0x18];
6294 
6295 	u8         syndrome[0x20];
6296 
6297 	u8         reserved_at_40[0x40];
6298 
6299 	struct mlx5_ifc_pkey_bits pkey[];
6300 };
6301 
6302 struct mlx5_ifc_query_hca_vport_pkey_in_bits {
6303 	u8         opcode[0x10];
6304 	u8         reserved_at_10[0x10];
6305 
6306 	u8         reserved_at_20[0x10];
6307 	u8         op_mod[0x10];
6308 
6309 	u8         other_vport[0x1];
6310 	u8         reserved_at_41[0xb];
6311 	u8         port_num[0x4];
6312 	u8         vport_number[0x10];
6313 
6314 	u8         reserved_at_60[0x10];
6315 	u8         pkey_index[0x10];
6316 };
6317 
6318 enum {
6319 	MLX5_HCA_VPORT_SEL_PORT_GUID	= 1 << 0,
6320 	MLX5_HCA_VPORT_SEL_NODE_GUID	= 1 << 1,
6321 	MLX5_HCA_VPORT_SEL_STATE_POLICY	= 1 << 2,
6322 };
6323 
6324 struct mlx5_ifc_query_hca_vport_gid_out_bits {
6325 	u8         status[0x8];
6326 	u8         reserved_at_8[0x18];
6327 
6328 	u8         syndrome[0x20];
6329 
6330 	u8         reserved_at_40[0x20];
6331 
6332 	u8         gids_num[0x10];
6333 	u8         reserved_at_70[0x10];
6334 
6335 	struct mlx5_ifc_array128_auto_bits gid[];
6336 };
6337 
6338 struct mlx5_ifc_query_hca_vport_gid_in_bits {
6339 	u8         opcode[0x10];
6340 	u8         reserved_at_10[0x10];
6341 
6342 	u8         reserved_at_20[0x10];
6343 	u8         op_mod[0x10];
6344 
6345 	u8         other_vport[0x1];
6346 	u8         reserved_at_41[0xb];
6347 	u8         port_num[0x4];
6348 	u8         vport_number[0x10];
6349 
6350 	u8         reserved_at_60[0x10];
6351 	u8         gid_index[0x10];
6352 };
6353 
6354 struct mlx5_ifc_query_hca_vport_context_out_bits {
6355 	u8         status[0x8];
6356 	u8         reserved_at_8[0x18];
6357 
6358 	u8         syndrome[0x20];
6359 
6360 	u8         reserved_at_40[0x40];
6361 
6362 	struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
6363 };
6364 
6365 struct mlx5_ifc_query_hca_vport_context_in_bits {
6366 	u8         opcode[0x10];
6367 	u8         reserved_at_10[0x10];
6368 
6369 	u8         reserved_at_20[0x10];
6370 	u8         op_mod[0x10];
6371 
6372 	u8         other_vport[0x1];
6373 	u8         reserved_at_41[0xb];
6374 	u8         port_num[0x4];
6375 	u8         vport_number[0x10];
6376 
6377 	u8         reserved_at_60[0x20];
6378 };
6379 
6380 struct mlx5_ifc_query_hca_cap_out_bits {
6381 	u8         status[0x8];
6382 	u8         reserved_at_8[0x18];
6383 
6384 	u8         syndrome[0x20];
6385 
6386 	u8         reserved_at_40[0x40];
6387 
6388 	union mlx5_ifc_hca_cap_union_bits capability;
6389 };
6390 
6391 struct mlx5_ifc_query_hca_cap_in_bits {
6392 	u8         opcode[0x10];
6393 	u8         reserved_at_10[0x10];
6394 
6395 	u8         reserved_at_20[0x10];
6396 	u8         op_mod[0x10];
6397 
6398 	u8         other_function[0x1];
6399 	u8         ec_vf_function[0x1];
6400 	u8         reserved_at_42[0x1];
6401 	u8         function_id_type[0x1];
6402 	u8         reserved_at_44[0xc];
6403 	u8         function_id[0x10];
6404 
6405 	u8         reserved_at_60[0x20];
6406 };
6407 
6408 struct mlx5_ifc_other_hca_cap_bits {
6409 	u8         roce[0x1];
6410 	u8         reserved_at_1[0x27f];
6411 };
6412 
6413 struct mlx5_ifc_query_other_hca_cap_out_bits {
6414 	u8         status[0x8];
6415 	u8         reserved_at_8[0x18];
6416 
6417 	u8         syndrome[0x20];
6418 
6419 	u8         reserved_at_40[0x40];
6420 
6421 	struct     mlx5_ifc_other_hca_cap_bits other_capability;
6422 };
6423 
6424 struct mlx5_ifc_query_other_hca_cap_in_bits {
6425 	u8         opcode[0x10];
6426 	u8         reserved_at_10[0x10];
6427 
6428 	u8         reserved_at_20[0x10];
6429 	u8         op_mod[0x10];
6430 
6431 	u8         reserved_at_40[0x10];
6432 	u8         function_id[0x10];
6433 
6434 	u8         reserved_at_60[0x20];
6435 };
6436 
6437 struct mlx5_ifc_modify_other_hca_cap_out_bits {
6438 	u8         status[0x8];
6439 	u8         reserved_at_8[0x18];
6440 
6441 	u8         syndrome[0x20];
6442 
6443 	u8         reserved_at_40[0x40];
6444 };
6445 
6446 struct mlx5_ifc_modify_other_hca_cap_in_bits {
6447 	u8         opcode[0x10];
6448 	u8         reserved_at_10[0x10];
6449 
6450 	u8         reserved_at_20[0x10];
6451 	u8         op_mod[0x10];
6452 
6453 	u8         reserved_at_40[0x10];
6454 	u8         function_id[0x10];
6455 	u8         field_select[0x20];
6456 
6457 	struct     mlx5_ifc_other_hca_cap_bits other_capability;
6458 };
6459 
6460 struct mlx5_ifc_sw_owner_icm_root_params_bits {
6461 	u8         sw_owner_icm_root_1[0x40];
6462 
6463 	u8         sw_owner_icm_root_0[0x40];
6464 };
6465 
6466 struct mlx5_ifc_rtc_params_bits {
6467 	u8         rtc_id_0[0x20];
6468 
6469 	u8         rtc_id_1[0x20];
6470 
6471 	u8         reserved_at_40[0x40];
6472 };
6473 
6474 struct mlx5_ifc_flow_table_context_bits {
6475 	u8         reformat_en[0x1];
6476 	u8         decap_en[0x1];
6477 	u8         sw_owner[0x1];
6478 	u8         termination_table[0x1];
6479 	u8         table_miss_action[0x4];
6480 	u8         level[0x8];
6481 	u8         rtc_valid[0x1];
6482 	u8         reserved_at_11[0x7];
6483 	u8         log_size[0x8];
6484 
6485 	u8         reserved_at_20[0x8];
6486 	u8         table_miss_id[0x18];
6487 
6488 	u8         reserved_at_40[0x8];
6489 	u8         lag_master_next_table_id[0x18];
6490 
6491 	u8         reserved_at_60[0x60];
6492 
6493 	union {
6494 		struct mlx5_ifc_sw_owner_icm_root_params_bits sws;
6495 		struct mlx5_ifc_rtc_params_bits hws;
6496 	};
6497 };
6498 
6499 struct mlx5_ifc_query_flow_table_out_bits {
6500 	u8         status[0x8];
6501 	u8         reserved_at_8[0x18];
6502 
6503 	u8         syndrome[0x20];
6504 
6505 	u8         reserved_at_40[0x80];
6506 
6507 	struct mlx5_ifc_flow_table_context_bits flow_table_context;
6508 };
6509 
6510 struct mlx5_ifc_query_flow_table_in_bits {
6511 	u8         opcode[0x10];
6512 	u8         reserved_at_10[0x10];
6513 
6514 	u8         reserved_at_20[0x10];
6515 	u8         op_mod[0x10];
6516 
6517 	u8         reserved_at_40[0x40];
6518 
6519 	u8         table_type[0x8];
6520 	u8         reserved_at_88[0x18];
6521 
6522 	u8         reserved_at_a0[0x8];
6523 	u8         table_id[0x18];
6524 
6525 	u8         reserved_at_c0[0x140];
6526 };
6527 
6528 struct mlx5_ifc_query_fte_out_bits {
6529 	u8         status[0x8];
6530 	u8         reserved_at_8[0x18];
6531 
6532 	u8         syndrome[0x20];
6533 
6534 	u8         reserved_at_40[0x1c0];
6535 
6536 	struct mlx5_ifc_flow_context_bits flow_context;
6537 };
6538 
6539 struct mlx5_ifc_query_fte_in_bits {
6540 	u8         opcode[0x10];
6541 	u8         reserved_at_10[0x10];
6542 
6543 	u8         reserved_at_20[0x10];
6544 	u8         op_mod[0x10];
6545 
6546 	u8         reserved_at_40[0x40];
6547 
6548 	u8         table_type[0x8];
6549 	u8         reserved_at_88[0x18];
6550 
6551 	u8         reserved_at_a0[0x8];
6552 	u8         table_id[0x18];
6553 
6554 	u8         reserved_at_c0[0x40];
6555 
6556 	u8         flow_index[0x20];
6557 
6558 	u8         reserved_at_120[0xe0];
6559 };
6560 
6561 struct mlx5_ifc_match_definer_format_0_bits {
6562 	u8         reserved_at_0[0x100];
6563 
6564 	u8         metadata_reg_c_0[0x20];
6565 
6566 	u8         metadata_reg_c_1[0x20];
6567 
6568 	u8         outer_dmac_47_16[0x20];
6569 
6570 	u8         outer_dmac_15_0[0x10];
6571 	u8         outer_ethertype[0x10];
6572 
6573 	u8         reserved_at_180[0x1];
6574 	u8         sx_sniffer[0x1];
6575 	u8         functional_lb[0x1];
6576 	u8         outer_ip_frag[0x1];
6577 	u8         outer_qp_type[0x2];
6578 	u8         outer_encap_type[0x2];
6579 	u8         port_number[0x2];
6580 	u8         outer_l3_type[0x2];
6581 	u8         outer_l4_type[0x2];
6582 	u8         outer_first_vlan_type[0x2];
6583 	u8         outer_first_vlan_prio[0x3];
6584 	u8         outer_first_vlan_cfi[0x1];
6585 	u8         outer_first_vlan_vid[0xc];
6586 
6587 	u8         outer_l4_type_ext[0x4];
6588 	u8         reserved_at_1a4[0x2];
6589 	u8         outer_ipsec_layer[0x2];
6590 	u8         outer_l2_type[0x2];
6591 	u8         force_lb[0x1];
6592 	u8         outer_l2_ok[0x1];
6593 	u8         outer_l3_ok[0x1];
6594 	u8         outer_l4_ok[0x1];
6595 	u8         outer_second_vlan_type[0x2];
6596 	u8         outer_second_vlan_prio[0x3];
6597 	u8         outer_second_vlan_cfi[0x1];
6598 	u8         outer_second_vlan_vid[0xc];
6599 
6600 	u8         outer_smac_47_16[0x20];
6601 
6602 	u8         outer_smac_15_0[0x10];
6603 	u8         inner_ipv4_checksum_ok[0x1];
6604 	u8         inner_l4_checksum_ok[0x1];
6605 	u8         outer_ipv4_checksum_ok[0x1];
6606 	u8         outer_l4_checksum_ok[0x1];
6607 	u8         inner_l3_ok[0x1];
6608 	u8         inner_l4_ok[0x1];
6609 	u8         outer_l3_ok_duplicate[0x1];
6610 	u8         outer_l4_ok_duplicate[0x1];
6611 	u8         outer_tcp_cwr[0x1];
6612 	u8         outer_tcp_ece[0x1];
6613 	u8         outer_tcp_urg[0x1];
6614 	u8         outer_tcp_ack[0x1];
6615 	u8         outer_tcp_psh[0x1];
6616 	u8         outer_tcp_rst[0x1];
6617 	u8         outer_tcp_syn[0x1];
6618 	u8         outer_tcp_fin[0x1];
6619 };
6620 
6621 struct mlx5_ifc_match_definer_format_22_bits {
6622 	u8         reserved_at_0[0x100];
6623 
6624 	u8         outer_ip_src_addr[0x20];
6625 
6626 	u8         outer_ip_dest_addr[0x20];
6627 
6628 	u8         outer_l4_sport[0x10];
6629 	u8         outer_l4_dport[0x10];
6630 
6631 	u8         reserved_at_160[0x1];
6632 	u8         sx_sniffer[0x1];
6633 	u8         functional_lb[0x1];
6634 	u8         outer_ip_frag[0x1];
6635 	u8         outer_qp_type[0x2];
6636 	u8         outer_encap_type[0x2];
6637 	u8         port_number[0x2];
6638 	u8         outer_l3_type[0x2];
6639 	u8         outer_l4_type[0x2];
6640 	u8         outer_first_vlan_type[0x2];
6641 	u8         outer_first_vlan_prio[0x3];
6642 	u8         outer_first_vlan_cfi[0x1];
6643 	u8         outer_first_vlan_vid[0xc];
6644 
6645 	u8         metadata_reg_c_0[0x20];
6646 
6647 	u8         outer_dmac_47_16[0x20];
6648 
6649 	u8         outer_smac_47_16[0x20];
6650 
6651 	u8         outer_smac_15_0[0x10];
6652 	u8         outer_dmac_15_0[0x10];
6653 };
6654 
6655 struct mlx5_ifc_match_definer_format_23_bits {
6656 	u8         reserved_at_0[0x100];
6657 
6658 	u8         inner_ip_src_addr[0x20];
6659 
6660 	u8         inner_ip_dest_addr[0x20];
6661 
6662 	u8         inner_l4_sport[0x10];
6663 	u8         inner_l4_dport[0x10];
6664 
6665 	u8         reserved_at_160[0x1];
6666 	u8         sx_sniffer[0x1];
6667 	u8         functional_lb[0x1];
6668 	u8         inner_ip_frag[0x1];
6669 	u8         inner_qp_type[0x2];
6670 	u8         inner_encap_type[0x2];
6671 	u8         port_number[0x2];
6672 	u8         inner_l3_type[0x2];
6673 	u8         inner_l4_type[0x2];
6674 	u8         inner_first_vlan_type[0x2];
6675 	u8         inner_first_vlan_prio[0x3];
6676 	u8         inner_first_vlan_cfi[0x1];
6677 	u8         inner_first_vlan_vid[0xc];
6678 
6679 	u8         tunnel_header_0[0x20];
6680 
6681 	u8         inner_dmac_47_16[0x20];
6682 
6683 	u8         inner_smac_47_16[0x20];
6684 
6685 	u8         inner_smac_15_0[0x10];
6686 	u8         inner_dmac_15_0[0x10];
6687 };
6688 
6689 struct mlx5_ifc_match_definer_format_29_bits {
6690 	u8         reserved_at_0[0xc0];
6691 
6692 	u8         outer_ip_dest_addr[0x80];
6693 
6694 	u8         outer_ip_src_addr[0x80];
6695 
6696 	u8         outer_l4_sport[0x10];
6697 	u8         outer_l4_dport[0x10];
6698 
6699 	u8         reserved_at_1e0[0x20];
6700 };
6701 
6702 struct mlx5_ifc_match_definer_format_30_bits {
6703 	u8         reserved_at_0[0xa0];
6704 
6705 	u8         outer_ip_dest_addr[0x80];
6706 
6707 	u8         outer_ip_src_addr[0x80];
6708 
6709 	u8         outer_dmac_47_16[0x20];
6710 
6711 	u8         outer_smac_47_16[0x20];
6712 
6713 	u8         outer_smac_15_0[0x10];
6714 	u8         outer_dmac_15_0[0x10];
6715 };
6716 
6717 struct mlx5_ifc_match_definer_format_31_bits {
6718 	u8         reserved_at_0[0xc0];
6719 
6720 	u8         inner_ip_dest_addr[0x80];
6721 
6722 	u8         inner_ip_src_addr[0x80];
6723 
6724 	u8         inner_l4_sport[0x10];
6725 	u8         inner_l4_dport[0x10];
6726 
6727 	u8         reserved_at_1e0[0x20];
6728 };
6729 
6730 struct mlx5_ifc_match_definer_format_32_bits {
6731 	u8         reserved_at_0[0xa0];
6732 
6733 	u8         inner_ip_dest_addr[0x80];
6734 
6735 	u8         inner_ip_src_addr[0x80];
6736 
6737 	u8         inner_dmac_47_16[0x20];
6738 
6739 	u8         inner_smac_47_16[0x20];
6740 
6741 	u8         inner_smac_15_0[0x10];
6742 	u8         inner_dmac_15_0[0x10];
6743 };
6744 
6745 enum {
6746 	MLX5_IFC_DEFINER_FORMAT_ID_SELECT = 61,
6747 };
6748 
6749 #define MLX5_IFC_DEFINER_FORMAT_OFFSET_UNUSED 0x0
6750 #define MLX5_IFC_DEFINER_FORMAT_OFFSET_OUTER_ETH_PKT_LEN 0x48
6751 #define MLX5_IFC_DEFINER_DW_SELECTORS_NUM 9
6752 #define MLX5_IFC_DEFINER_BYTE_SELECTORS_NUM 8
6753 
6754 struct mlx5_ifc_match_definer_match_mask_bits {
6755 	u8         reserved_at_1c0[5][0x20];
6756 	u8         match_dw_8[0x20];
6757 	u8         match_dw_7[0x20];
6758 	u8         match_dw_6[0x20];
6759 	u8         match_dw_5[0x20];
6760 	u8         match_dw_4[0x20];
6761 	u8         match_dw_3[0x20];
6762 	u8         match_dw_2[0x20];
6763 	u8         match_dw_1[0x20];
6764 	u8         match_dw_0[0x20];
6765 
6766 	u8         match_byte_7[0x8];
6767 	u8         match_byte_6[0x8];
6768 	u8         match_byte_5[0x8];
6769 	u8         match_byte_4[0x8];
6770 
6771 	u8         match_byte_3[0x8];
6772 	u8         match_byte_2[0x8];
6773 	u8         match_byte_1[0x8];
6774 	u8         match_byte_0[0x8];
6775 };
6776 
6777 struct mlx5_ifc_match_definer_bits {
6778 	u8         modify_field_select[0x40];
6779 
6780 	u8         reserved_at_40[0x40];
6781 
6782 	u8         reserved_at_80[0x10];
6783 	u8         format_id[0x10];
6784 
6785 	u8         reserved_at_a0[0x60];
6786 
6787 	u8         format_select_dw3[0x8];
6788 	u8         format_select_dw2[0x8];
6789 	u8         format_select_dw1[0x8];
6790 	u8         format_select_dw0[0x8];
6791 
6792 	u8         format_select_dw7[0x8];
6793 	u8         format_select_dw6[0x8];
6794 	u8         format_select_dw5[0x8];
6795 	u8         format_select_dw4[0x8];
6796 
6797 	u8         reserved_at_100[0x18];
6798 	u8         format_select_dw8[0x8];
6799 
6800 	u8         reserved_at_120[0x20];
6801 
6802 	u8         format_select_byte3[0x8];
6803 	u8         format_select_byte2[0x8];
6804 	u8         format_select_byte1[0x8];
6805 	u8         format_select_byte0[0x8];
6806 
6807 	u8         format_select_byte7[0x8];
6808 	u8         format_select_byte6[0x8];
6809 	u8         format_select_byte5[0x8];
6810 	u8         format_select_byte4[0x8];
6811 
6812 	u8         reserved_at_180[0x40];
6813 
6814 	union {
6815 		struct {
6816 			u8         match_mask[16][0x20];
6817 		};
6818 		struct mlx5_ifc_match_definer_match_mask_bits match_mask_format;
6819 	};
6820 };
6821 
6822 struct mlx5_ifc_general_obj_create_param_bits {
6823 	u8         alias_object[0x1];
6824 	u8         reserved_at_1[0x2];
6825 	u8         log_obj_range[0x5];
6826 	u8         reserved_at_8[0x18];
6827 };
6828 
6829 struct mlx5_ifc_general_obj_query_param_bits {
6830 	u8         alias_object[0x1];
6831 	u8         obj_offset[0x1f];
6832 };
6833 
6834 struct mlx5_ifc_general_obj_in_cmd_hdr_bits {
6835 	u8         opcode[0x10];
6836 	u8         uid[0x10];
6837 
6838 	u8         vhca_tunnel_id[0x10];
6839 	u8         obj_type[0x10];
6840 
6841 	u8         obj_id[0x20];
6842 
6843 	union {
6844 		struct mlx5_ifc_general_obj_create_param_bits create;
6845 		struct mlx5_ifc_general_obj_query_param_bits query;
6846 	} op_param;
6847 };
6848 
6849 struct mlx5_ifc_general_obj_out_cmd_hdr_bits {
6850 	u8         status[0x8];
6851 	u8         reserved_at_8[0x18];
6852 
6853 	u8         syndrome[0x20];
6854 
6855 	u8         obj_id[0x20];
6856 
6857 	u8         reserved_at_60[0x20];
6858 };
6859 
6860 struct mlx5_ifc_allow_other_vhca_access_in_bits {
6861 	u8 opcode[0x10];
6862 	u8 uid[0x10];
6863 	u8 reserved_at_20[0x10];
6864 	u8 op_mod[0x10];
6865 	u8 reserved_at_40[0x50];
6866 	u8 object_type_to_be_accessed[0x10];
6867 	u8 object_id_to_be_accessed[0x20];
6868 	u8 reserved_at_c0[0x40];
6869 	union {
6870 		u8 access_key_raw[0x100];
6871 		u8 access_key[8][0x20];
6872 	};
6873 };
6874 
6875 struct mlx5_ifc_allow_other_vhca_access_out_bits {
6876 	u8 status[0x8];
6877 	u8 reserved_at_8[0x18];
6878 	u8 syndrome[0x20];
6879 	u8 reserved_at_40[0x40];
6880 };
6881 
6882 struct mlx5_ifc_modify_header_arg_bits {
6883 	u8         reserved_at_0[0x80];
6884 
6885 	u8         reserved_at_80[0x8];
6886 	u8         access_pd[0x18];
6887 };
6888 
6889 struct mlx5_ifc_create_modify_header_arg_in_bits {
6890 	struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
6891 	struct mlx5_ifc_modify_header_arg_bits arg;
6892 };
6893 
6894 struct mlx5_ifc_create_match_definer_in_bits {
6895 	struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
6896 
6897 	struct mlx5_ifc_match_definer_bits obj_context;
6898 };
6899 
6900 struct mlx5_ifc_create_match_definer_out_bits {
6901 	struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr;
6902 };
6903 
6904 struct mlx5_ifc_alias_context_bits {
6905 	u8 vhca_id_to_be_accessed[0x10];
6906 	u8 reserved_at_10[0xd];
6907 	u8 status[0x3];
6908 	u8 object_id_to_be_accessed[0x20];
6909 	u8 reserved_at_40[0x40];
6910 	union {
6911 		u8 access_key_raw[0x100];
6912 		u8 access_key[8][0x20];
6913 	};
6914 	u8 metadata[0x80];
6915 };
6916 
6917 struct mlx5_ifc_create_alias_obj_in_bits {
6918 	struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
6919 	struct mlx5_ifc_alias_context_bits alias_ctx;
6920 };
6921 
6922 enum {
6923 	MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS    = 0x0,
6924 	MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS  = 0x1,
6925 	MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS    = 0x2,
6926 	MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3,
6927 	MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_3 = 0x4,
6928 	MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_4 = 0x5,
6929 	MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_5 = 0x6,
6930 };
6931 
6932 struct mlx5_ifc_query_flow_group_out_bits {
6933 	u8         status[0x8];
6934 	u8         reserved_at_8[0x18];
6935 
6936 	u8         syndrome[0x20];
6937 
6938 	u8         reserved_at_40[0xa0];
6939 
6940 	u8         start_flow_index[0x20];
6941 
6942 	u8         reserved_at_100[0x20];
6943 
6944 	u8         end_flow_index[0x20];
6945 
6946 	u8         reserved_at_140[0xa0];
6947 
6948 	u8         reserved_at_1e0[0x18];
6949 	u8         match_criteria_enable[0x8];
6950 
6951 	struct mlx5_ifc_fte_match_param_bits match_criteria;
6952 
6953 	u8         reserved_at_1200[0xe00];
6954 };
6955 
6956 struct mlx5_ifc_query_flow_group_in_bits {
6957 	u8         opcode[0x10];
6958 	u8         reserved_at_10[0x10];
6959 
6960 	u8         reserved_at_20[0x10];
6961 	u8         op_mod[0x10];
6962 
6963 	u8         reserved_at_40[0x40];
6964 
6965 	u8         table_type[0x8];
6966 	u8         reserved_at_88[0x18];
6967 
6968 	u8         reserved_at_a0[0x8];
6969 	u8         table_id[0x18];
6970 
6971 	u8         group_id[0x20];
6972 
6973 	u8         reserved_at_e0[0x120];
6974 };
6975 
6976 struct mlx5_ifc_query_flow_counter_out_bits {
6977 	u8         status[0x8];
6978 	u8         reserved_at_8[0x18];
6979 
6980 	u8         syndrome[0x20];
6981 
6982 	u8         reserved_at_40[0x40];
6983 
6984 	struct mlx5_ifc_traffic_counter_bits flow_statistics[];
6985 };
6986 
6987 struct mlx5_ifc_query_flow_counter_in_bits {
6988 	u8         opcode[0x10];
6989 	u8         reserved_at_10[0x10];
6990 
6991 	u8         reserved_at_20[0x10];
6992 	u8         op_mod[0x10];
6993 
6994 	u8         reserved_at_40[0x80];
6995 
6996 	u8         clear[0x1];
6997 	u8         reserved_at_c1[0xf];
6998 	u8         num_of_counters[0x10];
6999 
7000 	u8         flow_counter_id[0x20];
7001 };
7002 
7003 struct mlx5_ifc_query_esw_vport_context_out_bits {
7004 	u8         status[0x8];
7005 	u8         reserved_at_8[0x18];
7006 
7007 	u8         syndrome[0x20];
7008 
7009 	u8         reserved_at_40[0x40];
7010 
7011 	struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
7012 };
7013 
7014 struct mlx5_ifc_query_esw_vport_context_in_bits {
7015 	u8         opcode[0x10];
7016 	u8         reserved_at_10[0x10];
7017 
7018 	u8         reserved_at_20[0x10];
7019 	u8         op_mod[0x10];
7020 
7021 	u8         other_vport[0x1];
7022 	u8         reserved_at_41[0xf];
7023 	u8         vport_number[0x10];
7024 
7025 	u8         reserved_at_60[0x20];
7026 };
7027 
7028 struct mlx5_ifc_destroy_esw_vport_out_bits {
7029 	u8         status[0x8];
7030 	u8         reserved_at_8[0x18];
7031 
7032 	u8         syndrome[0x20];
7033 
7034 	u8         reserved_at_40[0x20];
7035 };
7036 
7037 struct mlx5_ifc_destroy_esw_vport_in_bits {
7038 	u8         opcode[0x10];
7039 	u8         uid[0x10];
7040 
7041 	u8         reserved_at_20[0x10];
7042 	u8         op_mod[0x10];
7043 
7044 	u8         reserved_at_40[0x10];
7045 	u8         vport_num[0x10];
7046 
7047 	u8         reserved_at_60[0x20];
7048 };
7049 
7050 struct mlx5_ifc_modify_esw_vport_context_out_bits {
7051 	u8         status[0x8];
7052 	u8         reserved_at_8[0x18];
7053 
7054 	u8         syndrome[0x20];
7055 
7056 	u8         reserved_at_40[0x40];
7057 };
7058 
7059 struct mlx5_ifc_esw_vport_context_fields_select_bits {
7060 	u8         reserved_at_0[0x1b];
7061 	u8         fdb_to_vport_reg_c_id[0x1];
7062 	u8         vport_cvlan_insert[0x1];
7063 	u8         vport_svlan_insert[0x1];
7064 	u8         vport_cvlan_strip[0x1];
7065 	u8         vport_svlan_strip[0x1];
7066 };
7067 
7068 struct mlx5_ifc_modify_esw_vport_context_in_bits {
7069 	u8         opcode[0x10];
7070 	u8         reserved_at_10[0x10];
7071 
7072 	u8         reserved_at_20[0x10];
7073 	u8         op_mod[0x10];
7074 
7075 	u8         other_vport[0x1];
7076 	u8         reserved_at_41[0xf];
7077 	u8         vport_number[0x10];
7078 
7079 	struct mlx5_ifc_esw_vport_context_fields_select_bits field_select;
7080 
7081 	struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
7082 };
7083 
7084 struct mlx5_ifc_query_eq_out_bits {
7085 	u8         status[0x8];
7086 	u8         reserved_at_8[0x18];
7087 
7088 	u8         syndrome[0x20];
7089 
7090 	u8         reserved_at_40[0x40];
7091 
7092 	struct mlx5_ifc_eqc_bits eq_context_entry;
7093 
7094 	u8         reserved_at_280[0x40];
7095 
7096 	u8         event_bitmask[0x40];
7097 
7098 	u8         reserved_at_300[0x580];
7099 
7100 	u8         pas[][0x40];
7101 };
7102 
7103 struct mlx5_ifc_query_eq_in_bits {
7104 	u8         opcode[0x10];
7105 	u8         reserved_at_10[0x10];
7106 
7107 	u8         reserved_at_20[0x10];
7108 	u8         op_mod[0x10];
7109 
7110 	u8         reserved_at_40[0x18];
7111 	u8         eq_number[0x8];
7112 
7113 	u8         reserved_at_60[0x20];
7114 };
7115 
7116 struct mlx5_ifc_packet_reformat_context_in_bits {
7117 	u8         reformat_type[0x8];
7118 	u8         reserved_at_8[0x4];
7119 	u8         reformat_param_0[0x4];
7120 	u8         reserved_at_10[0x6];
7121 	u8         reformat_data_size[0xa];
7122 
7123 	u8         reformat_param_1[0x8];
7124 	u8         reserved_at_28[0x8];
7125 	u8         reformat_data[2][0x8];
7126 
7127 	u8         more_reformat_data[][0x8];
7128 };
7129 
7130 struct mlx5_ifc_query_packet_reformat_context_out_bits {
7131 	u8         status[0x8];
7132 	u8         reserved_at_8[0x18];
7133 
7134 	u8         syndrome[0x20];
7135 
7136 	u8         reserved_at_40[0xa0];
7137 
7138 	struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context[];
7139 };
7140 
7141 struct mlx5_ifc_query_packet_reformat_context_in_bits {
7142 	u8         opcode[0x10];
7143 	u8         reserved_at_10[0x10];
7144 
7145 	u8         reserved_at_20[0x10];
7146 	u8         op_mod[0x10];
7147 
7148 	u8         packet_reformat_id[0x20];
7149 
7150 	u8         reserved_at_60[0xa0];
7151 };
7152 
7153 struct mlx5_ifc_alloc_packet_reformat_context_out_bits {
7154 	u8         status[0x8];
7155 	u8         reserved_at_8[0x18];
7156 
7157 	u8         syndrome[0x20];
7158 
7159 	u8         packet_reformat_id[0x20];
7160 
7161 	u8         reserved_at_60[0x20];
7162 };
7163 
7164 enum {
7165 	MLX5_REFORMAT_CONTEXT_ANCHOR_MAC_START = 0x1,
7166 	MLX5_REFORMAT_CONTEXT_ANCHOR_VLAN_START = 0x2,
7167 	MLX5_REFORMAT_CONTEXT_ANCHOR_IP_START = 0x7,
7168 	MLX5_REFORMAT_CONTEXT_ANCHOR_TCP_UDP_START = 0x9,
7169 };
7170 
7171 enum mlx5_reformat_ctx_type {
7172 	MLX5_REFORMAT_TYPE_L2_TO_VXLAN = 0x0,
7173 	MLX5_REFORMAT_TYPE_L2_TO_NVGRE = 0x1,
7174 	MLX5_REFORMAT_TYPE_L2_TO_L2_TUNNEL = 0x2,
7175 	MLX5_REFORMAT_TYPE_L3_TUNNEL_TO_L2 = 0x3,
7176 	MLX5_REFORMAT_TYPE_L2_TO_L3_TUNNEL = 0x4,
7177 	MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_IPV4 = 0x5,
7178 	MLX5_REFORMAT_TYPE_L2_TO_L3_ESP_TUNNEL = 0x6,
7179 	MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_UDPV4 = 0x7,
7180 	MLX5_REFORMAT_TYPE_DEL_ESP_TRANSPORT = 0x8,
7181 	MLX5_REFORMAT_TYPE_L3_ESP_TUNNEL_TO_L2 = 0x9,
7182 	MLX5_REFORMAT_TYPE_DEL_ESP_TRANSPORT_OVER_UDP = 0xa,
7183 	MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_IPV6 = 0xb,
7184 	MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_UDPV6 = 0xc,
7185 	MLX5_REFORMAT_TYPE_ADD_PSP_TUNNEL = 0xd,
7186 	MLX5_REFORMAT_TYPE_DEL_PSP_TUNNEL = 0xe,
7187 	MLX5_REFORMAT_TYPE_INSERT_HDR = 0xf,
7188 	MLX5_REFORMAT_TYPE_REMOVE_HDR = 0x10,
7189 	MLX5_REFORMAT_TYPE_ADD_MACSEC = 0x11,
7190 	MLX5_REFORMAT_TYPE_DEL_MACSEC = 0x12,
7191 };
7192 
7193 struct mlx5_ifc_alloc_packet_reformat_context_in_bits {
7194 	u8         opcode[0x10];
7195 	u8         reserved_at_10[0x10];
7196 
7197 	u8         reserved_at_20[0x10];
7198 	u8         op_mod[0x10];
7199 
7200 	u8         reserved_at_40[0xa0];
7201 
7202 	struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context;
7203 };
7204 
7205 struct mlx5_ifc_dealloc_packet_reformat_context_out_bits {
7206 	u8         status[0x8];
7207 	u8         reserved_at_8[0x18];
7208 
7209 	u8         syndrome[0x20];
7210 
7211 	u8         reserved_at_40[0x40];
7212 };
7213 
7214 struct mlx5_ifc_dealloc_packet_reformat_context_in_bits {
7215 	u8         opcode[0x10];
7216 	u8         reserved_at_10[0x10];
7217 
7218 	u8         reserved_20[0x10];
7219 	u8         op_mod[0x10];
7220 
7221 	u8         packet_reformat_id[0x20];
7222 
7223 	u8         reserved_60[0x20];
7224 };
7225 
7226 struct mlx5_ifc_set_action_in_bits {
7227 	u8         action_type[0x4];
7228 	u8         field[0xc];
7229 	u8         reserved_at_10[0x3];
7230 	u8         offset[0x5];
7231 	u8         reserved_at_18[0x3];
7232 	u8         length[0x5];
7233 
7234 	u8         data[0x20];
7235 };
7236 
7237 struct mlx5_ifc_add_action_in_bits {
7238 	u8         action_type[0x4];
7239 	u8         field[0xc];
7240 	u8         reserved_at_10[0x10];
7241 
7242 	u8         data[0x20];
7243 };
7244 
7245 struct mlx5_ifc_copy_action_in_bits {
7246 	u8         action_type[0x4];
7247 	u8         src_field[0xc];
7248 	u8         reserved_at_10[0x3];
7249 	u8         src_offset[0x5];
7250 	u8         reserved_at_18[0x3];
7251 	u8         length[0x5];
7252 
7253 	u8         reserved_at_20[0x4];
7254 	u8         dst_field[0xc];
7255 	u8         reserved_at_30[0x3];
7256 	u8         dst_offset[0x5];
7257 	u8         reserved_at_38[0x8];
7258 };
7259 
7260 union mlx5_ifc_set_add_copy_action_in_auto_bits {
7261 	struct mlx5_ifc_set_action_in_bits  set_action_in;
7262 	struct mlx5_ifc_add_action_in_bits  add_action_in;
7263 	struct mlx5_ifc_copy_action_in_bits copy_action_in;
7264 	u8         reserved_at_0[0x40];
7265 };
7266 
7267 enum {
7268 	MLX5_ACTION_TYPE_SET   = 0x1,
7269 	MLX5_ACTION_TYPE_ADD   = 0x2,
7270 	MLX5_ACTION_TYPE_COPY  = 0x3,
7271 };
7272 
7273 enum {
7274 	MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16    = 0x1,
7275 	MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0     = 0x2,
7276 	MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE     = 0x3,
7277 	MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16    = 0x4,
7278 	MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0     = 0x5,
7279 	MLX5_ACTION_IN_FIELD_OUT_IP_DSCP       = 0x6,
7280 	MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS     = 0x7,
7281 	MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT     = 0x8,
7282 	MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT     = 0x9,
7283 	MLX5_ACTION_IN_FIELD_OUT_IP_TTL        = 0xa,
7284 	MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT     = 0xb,
7285 	MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT     = 0xc,
7286 	MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96  = 0xd,
7287 	MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64   = 0xe,
7288 	MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32   = 0xf,
7289 	MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0    = 0x10,
7290 	MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96  = 0x11,
7291 	MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64   = 0x12,
7292 	MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32   = 0x13,
7293 	MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0    = 0x14,
7294 	MLX5_ACTION_IN_FIELD_OUT_SIPV4         = 0x15,
7295 	MLX5_ACTION_IN_FIELD_OUT_DIPV4         = 0x16,
7296 	MLX5_ACTION_IN_FIELD_OUT_FIRST_VID     = 0x17,
7297 	MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47,
7298 	MLX5_ACTION_IN_FIELD_METADATA_REG_A    = 0x49,
7299 	MLX5_ACTION_IN_FIELD_METADATA_REG_B    = 0x50,
7300 	MLX5_ACTION_IN_FIELD_METADATA_REG_C_0  = 0x51,
7301 	MLX5_ACTION_IN_FIELD_METADATA_REG_C_1  = 0x52,
7302 	MLX5_ACTION_IN_FIELD_METADATA_REG_C_2  = 0x53,
7303 	MLX5_ACTION_IN_FIELD_METADATA_REG_C_3  = 0x54,
7304 	MLX5_ACTION_IN_FIELD_METADATA_REG_C_4  = 0x55,
7305 	MLX5_ACTION_IN_FIELD_METADATA_REG_C_5  = 0x56,
7306 	MLX5_ACTION_IN_FIELD_METADATA_REG_C_6  = 0x57,
7307 	MLX5_ACTION_IN_FIELD_METADATA_REG_C_7  = 0x58,
7308 	MLX5_ACTION_IN_FIELD_OUT_TCP_SEQ_NUM   = 0x59,
7309 	MLX5_ACTION_IN_FIELD_OUT_TCP_ACK_NUM   = 0x5B,
7310 	MLX5_ACTION_IN_FIELD_IPSEC_SYNDROME    = 0x5D,
7311 	MLX5_ACTION_IN_FIELD_OUT_EMD_47_32     = 0x6F,
7312 	MLX5_ACTION_IN_FIELD_OUT_EMD_31_0      = 0x70,
7313 	MLX5_ACTION_IN_FIELD_PSP_SYNDROME      = 0x71,
7314 };
7315 
7316 struct mlx5_ifc_alloc_modify_header_context_out_bits {
7317 	u8         status[0x8];
7318 	u8         reserved_at_8[0x18];
7319 
7320 	u8         syndrome[0x20];
7321 
7322 	u8         modify_header_id[0x20];
7323 
7324 	u8         reserved_at_60[0x20];
7325 };
7326 
7327 struct mlx5_ifc_alloc_modify_header_context_in_bits {
7328 	u8         opcode[0x10];
7329 	u8         reserved_at_10[0x10];
7330 
7331 	u8         reserved_at_20[0x10];
7332 	u8         op_mod[0x10];
7333 
7334 	u8         reserved_at_40[0x20];
7335 
7336 	u8         table_type[0x8];
7337 	u8         reserved_at_68[0x10];
7338 	u8         num_of_actions[0x8];
7339 
7340 	union mlx5_ifc_set_add_copy_action_in_auto_bits actions[];
7341 };
7342 
7343 struct mlx5_ifc_dealloc_modify_header_context_out_bits {
7344 	u8         status[0x8];
7345 	u8         reserved_at_8[0x18];
7346 
7347 	u8         syndrome[0x20];
7348 
7349 	u8         reserved_at_40[0x40];
7350 };
7351 
7352 struct mlx5_ifc_dealloc_modify_header_context_in_bits {
7353 	u8         opcode[0x10];
7354 	u8         reserved_at_10[0x10];
7355 
7356 	u8         reserved_at_20[0x10];
7357 	u8         op_mod[0x10];
7358 
7359 	u8         modify_header_id[0x20];
7360 
7361 	u8         reserved_at_60[0x20];
7362 };
7363 
7364 struct mlx5_ifc_query_modify_header_context_in_bits {
7365 	u8         opcode[0x10];
7366 	u8         uid[0x10];
7367 
7368 	u8         reserved_at_20[0x10];
7369 	u8         op_mod[0x10];
7370 
7371 	u8         modify_header_id[0x20];
7372 
7373 	u8         reserved_at_60[0xa0];
7374 };
7375 
7376 struct mlx5_ifc_query_dct_out_bits {
7377 	u8         status[0x8];
7378 	u8         reserved_at_8[0x18];
7379 
7380 	u8         syndrome[0x20];
7381 
7382 	u8         reserved_at_40[0x40];
7383 
7384 	struct mlx5_ifc_dctc_bits dct_context_entry;
7385 
7386 	u8         reserved_at_280[0x180];
7387 };
7388 
7389 struct mlx5_ifc_query_dct_in_bits {
7390 	u8         opcode[0x10];
7391 	u8         reserved_at_10[0x10];
7392 
7393 	u8         reserved_at_20[0x10];
7394 	u8         op_mod[0x10];
7395 
7396 	u8         reserved_at_40[0x8];
7397 	u8         dctn[0x18];
7398 
7399 	u8         reserved_at_60[0x20];
7400 };
7401 
7402 struct mlx5_ifc_query_cq_out_bits {
7403 	u8         status[0x8];
7404 	u8         reserved_at_8[0x18];
7405 
7406 	u8         syndrome[0x20];
7407 
7408 	u8         reserved_at_40[0x40];
7409 
7410 	struct mlx5_ifc_cqc_bits cq_context;
7411 
7412 	u8         reserved_at_280[0x600];
7413 
7414 	u8         pas[][0x40];
7415 };
7416 
7417 struct mlx5_ifc_query_cq_in_bits {
7418 	u8         opcode[0x10];
7419 	u8         reserved_at_10[0x10];
7420 
7421 	u8         reserved_at_20[0x10];
7422 	u8         op_mod[0x10];
7423 
7424 	u8         reserved_at_40[0x8];
7425 	u8         cqn[0x18];
7426 
7427 	u8         reserved_at_60[0x20];
7428 };
7429 
7430 struct mlx5_ifc_query_cong_status_out_bits {
7431 	u8         status[0x8];
7432 	u8         reserved_at_8[0x18];
7433 
7434 	u8         syndrome[0x20];
7435 
7436 	u8         reserved_at_40[0x20];
7437 
7438 	u8         enable[0x1];
7439 	u8         tag_enable[0x1];
7440 	u8         reserved_at_62[0x1e];
7441 };
7442 
7443 struct mlx5_ifc_query_cong_status_in_bits {
7444 	u8         opcode[0x10];
7445 	u8         reserved_at_10[0x10];
7446 
7447 	u8         reserved_at_20[0x10];
7448 	u8         op_mod[0x10];
7449 
7450 	u8         reserved_at_40[0x18];
7451 	u8         priority[0x4];
7452 	u8         cong_protocol[0x4];
7453 
7454 	u8         reserved_at_60[0x20];
7455 };
7456 
7457 struct mlx5_ifc_query_cong_statistics_out_bits {
7458 	u8         status[0x8];
7459 	u8         reserved_at_8[0x18];
7460 
7461 	u8         syndrome[0x20];
7462 
7463 	u8         reserved_at_40[0x40];
7464 
7465 	u8         rp_cur_flows[0x20];
7466 
7467 	u8         sum_flows[0x20];
7468 
7469 	u8         rp_cnp_ignored_high[0x20];
7470 
7471 	u8         rp_cnp_ignored_low[0x20];
7472 
7473 	u8         rp_cnp_handled_high[0x20];
7474 
7475 	u8         rp_cnp_handled_low[0x20];
7476 
7477 	u8         reserved_at_140[0x100];
7478 
7479 	u8         time_stamp_high[0x20];
7480 
7481 	u8         time_stamp_low[0x20];
7482 
7483 	u8         accumulators_period[0x20];
7484 
7485 	u8         np_ecn_marked_roce_packets_high[0x20];
7486 
7487 	u8         np_ecn_marked_roce_packets_low[0x20];
7488 
7489 	u8         np_cnp_sent_high[0x20];
7490 
7491 	u8         np_cnp_sent_low[0x20];
7492 
7493 	u8         reserved_at_320[0x560];
7494 };
7495 
7496 struct mlx5_ifc_query_cong_statistics_in_bits {
7497 	u8         opcode[0x10];
7498 	u8         reserved_at_10[0x10];
7499 
7500 	u8         reserved_at_20[0x10];
7501 	u8         op_mod[0x10];
7502 
7503 	u8         clear[0x1];
7504 	u8         reserved_at_41[0x1f];
7505 
7506 	u8         reserved_at_60[0x20];
7507 };
7508 
7509 struct mlx5_ifc_query_cong_params_out_bits {
7510 	u8         status[0x8];
7511 	u8         reserved_at_8[0x18];
7512 
7513 	u8         syndrome[0x20];
7514 
7515 	u8         reserved_at_40[0x40];
7516 
7517 	union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
7518 };
7519 
7520 struct mlx5_ifc_query_cong_params_in_bits {
7521 	u8         opcode[0x10];
7522 	u8         reserved_at_10[0x10];
7523 
7524 	u8         reserved_at_20[0x10];
7525 	u8         op_mod[0x10];
7526 
7527 	u8         reserved_at_40[0x1c];
7528 	u8         cong_protocol[0x4];
7529 
7530 	u8         reserved_at_60[0x20];
7531 };
7532 
7533 struct mlx5_ifc_query_adapter_out_bits {
7534 	u8         status[0x8];
7535 	u8         reserved_at_8[0x18];
7536 
7537 	u8         syndrome[0x20];
7538 
7539 	u8         reserved_at_40[0x40];
7540 
7541 	struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct;
7542 };
7543 
7544 struct mlx5_ifc_query_adapter_in_bits {
7545 	u8         opcode[0x10];
7546 	u8         reserved_at_10[0x10];
7547 
7548 	u8         reserved_at_20[0x10];
7549 	u8         op_mod[0x10];
7550 
7551 	u8         reserved_at_40[0x40];
7552 };
7553 
7554 struct mlx5_ifc_function_vhca_rid_info_reg_bits {
7555 	u8         host_number[0x8];
7556 	u8         host_pci_device_function[0x8];
7557 	u8         host_pci_bus[0x8];
7558 	u8         reserved_at_18[0x3];
7559 	u8         pci_bus_assigned[0x1];
7560 	u8         function_type[0x4];
7561 
7562 	u8         parent_pci_device_function[0x8];
7563 	u8         parent_pci_bus[0x8];
7564 	u8         vhca_id[0x10];
7565 
7566 	u8         reserved_at_40[0x10];
7567 	u8         function_id[0x10];
7568 
7569 	u8         reserved_at_60[0x20];
7570 };
7571 
7572 struct mlx5_ifc_delegated_function_vhca_rid_info_bits {
7573 	struct mlx5_ifc_function_vhca_rid_info_reg_bits function_vhca_rid_info;
7574 
7575 	u8         reserved_at_80[0x18];
7576 	u8         manage_profile[0x8];
7577 
7578 	u8         reserved_at_a0[0x60];
7579 };
7580 
7581 struct mlx5_ifc_query_delegated_vhca_out_bits {
7582 	u8         status[0x8];
7583 	u8         reserved_at_8[0x18];
7584 
7585 	u8         syndrome[0x20];
7586 
7587 	u8         reserved_at_40[0x20];
7588 
7589 	u8         reserved_at_60[0x10];
7590 	u8         functions_count[0x10];
7591 
7592 	u8         reserved_at_80[0x80];
7593 
7594 	struct mlx5_ifc_delegated_function_vhca_rid_info_bits
7595 			delegated_function_vhca_rid_info[];
7596 };
7597 
7598 struct mlx5_ifc_query_delegated_vhca_in_bits {
7599 	u8         opcode[0x10];
7600 	u8         uid[0x10];
7601 
7602 	u8         reserved_at_20[0x10];
7603 	u8         op_mod[0x10];
7604 
7605 	u8         reserved_at_40[0x40];
7606 };
7607 
7608 struct mlx5_ifc_create_esw_vport_out_bits {
7609 	u8         status[0x8];
7610 	u8         reserved_at_8[0x18];
7611 
7612 	u8         syndrome[0x20];
7613 
7614 	u8         reserved_at_40[0x20];
7615 
7616 	u8         reserved_at_60[0x10];
7617 	u8         vport_num[0x10];
7618 };
7619 
7620 struct mlx5_ifc_create_esw_vport_in_bits {
7621 	u8         opcode[0x10];
7622 	u8         reserved_at_10[0x10];
7623 
7624 	u8         reserved_at_20[0x10];
7625 	u8         op_mod[0x10];
7626 
7627 	u8         reserved_at_40[0x10];
7628 	u8         managed_vhca_id[0x10];
7629 
7630 	u8         reserved_at_60[0x20];
7631 };
7632 
7633 struct mlx5_ifc_qp_2rst_out_bits {
7634 	u8         status[0x8];
7635 	u8         reserved_at_8[0x18];
7636 
7637 	u8         syndrome[0x20];
7638 
7639 	u8         reserved_at_40[0x40];
7640 };
7641 
7642 struct mlx5_ifc_qp_2rst_in_bits {
7643 	u8         opcode[0x10];
7644 	u8         uid[0x10];
7645 
7646 	u8         reserved_at_20[0x10];
7647 	u8         op_mod[0x10];
7648 
7649 	u8         reserved_at_40[0x8];
7650 	u8         qpn[0x18];
7651 
7652 	u8         reserved_at_60[0x20];
7653 };
7654 
7655 struct mlx5_ifc_qp_2err_out_bits {
7656 	u8         status[0x8];
7657 	u8         reserved_at_8[0x18];
7658 
7659 	u8         syndrome[0x20];
7660 
7661 	u8         reserved_at_40[0x40];
7662 };
7663 
7664 struct mlx5_ifc_qp_2err_in_bits {
7665 	u8         opcode[0x10];
7666 	u8         uid[0x10];
7667 
7668 	u8         reserved_at_20[0x10];
7669 	u8         op_mod[0x10];
7670 
7671 	u8         reserved_at_40[0x8];
7672 	u8         qpn[0x18];
7673 
7674 	u8         reserved_at_60[0x20];
7675 };
7676 
7677 struct mlx5_ifc_trans_page_fault_info_bits {
7678 	u8         error[0x1];
7679 	u8         reserved_at_1[0x4];
7680 	u8         page_fault_type[0x3];
7681 	u8         wq_number[0x18];
7682 
7683 	u8         reserved_at_20[0x8];
7684 	u8         fault_token[0x18];
7685 };
7686 
7687 struct mlx5_ifc_mem_page_fault_info_bits {
7688 	u8          error[0x1];
7689 	u8          reserved_at_1[0xf];
7690 	u8          fault_token_47_32[0x10];
7691 
7692 	u8          fault_token_31_0[0x20];
7693 };
7694 
7695 union mlx5_ifc_page_fault_resume_in_page_fault_info_auto_bits {
7696 	struct mlx5_ifc_trans_page_fault_info_bits trans_page_fault_info;
7697 	struct mlx5_ifc_mem_page_fault_info_bits mem_page_fault_info;
7698 	u8          reserved_at_0[0x40];
7699 };
7700 
7701 struct mlx5_ifc_page_fault_resume_out_bits {
7702 	u8         status[0x8];
7703 	u8         reserved_at_8[0x18];
7704 
7705 	u8         syndrome[0x20];
7706 
7707 	u8         reserved_at_40[0x40];
7708 };
7709 
7710 struct mlx5_ifc_page_fault_resume_in_bits {
7711 	u8         opcode[0x10];
7712 	u8         reserved_at_10[0x10];
7713 
7714 	u8         reserved_at_20[0x10];
7715 	u8         op_mod[0x10];
7716 
7717 	union mlx5_ifc_page_fault_resume_in_page_fault_info_auto_bits
7718 		page_fault_info;
7719 };
7720 
7721 struct mlx5_ifc_nop_out_bits {
7722 	u8         status[0x8];
7723 	u8         reserved_at_8[0x18];
7724 
7725 	u8         syndrome[0x20];
7726 
7727 	u8         reserved_at_40[0x40];
7728 };
7729 
7730 struct mlx5_ifc_nop_in_bits {
7731 	u8         opcode[0x10];
7732 	u8         reserved_at_10[0x10];
7733 
7734 	u8         reserved_at_20[0x10];
7735 	u8         op_mod[0x10];
7736 
7737 	u8         reserved_at_40[0x40];
7738 };
7739 
7740 struct mlx5_ifc_modify_vport_state_out_bits {
7741 	u8         status[0x8];
7742 	u8         reserved_at_8[0x18];
7743 
7744 	u8         syndrome[0x20];
7745 
7746 	u8         reserved_at_40[0x40];
7747 };
7748 
7749 struct mlx5_ifc_modify_vport_state_in_bits {
7750 	u8         opcode[0x10];
7751 	u8         reserved_at_10[0x10];
7752 
7753 	u8         reserved_at_20[0x10];
7754 	u8         op_mod[0x10];
7755 
7756 	u8         other_vport[0x1];
7757 	u8         reserved_at_41[0xf];
7758 	u8         vport_number[0x10];
7759 
7760 	u8         reserved_at_60[0x10];
7761 	u8         ingress_connect[0x1];
7762 	u8         egress_connect[0x1];
7763 	u8         ingress_connect_valid[0x1];
7764 	u8         egress_connect_valid[0x1];
7765 	u8         reserved_at_74[0x4];
7766 	u8         admin_state[0x4];
7767 	u8         reserved_at_7c[0x4];
7768 };
7769 
7770 struct mlx5_ifc_modify_tis_out_bits {
7771 	u8         status[0x8];
7772 	u8         reserved_at_8[0x18];
7773 
7774 	u8         syndrome[0x20];
7775 
7776 	u8         reserved_at_40[0x40];
7777 };
7778 
7779 struct mlx5_ifc_modify_tis_bitmask_bits {
7780 	u8         reserved_at_0[0x20];
7781 
7782 	u8         reserved_at_20[0x1d];
7783 	u8         lag_tx_port_affinity[0x1];
7784 	u8         strict_lag_tx_port_affinity[0x1];
7785 	u8         prio[0x1];
7786 };
7787 
7788 struct mlx5_ifc_modify_tis_in_bits {
7789 	u8         opcode[0x10];
7790 	u8         uid[0x10];
7791 
7792 	u8         reserved_at_20[0x10];
7793 	u8         op_mod[0x10];
7794 
7795 	u8         reserved_at_40[0x8];
7796 	u8         tisn[0x18];
7797 
7798 	u8         reserved_at_60[0x20];
7799 
7800 	struct mlx5_ifc_modify_tis_bitmask_bits bitmask;
7801 
7802 	u8         reserved_at_c0[0x40];
7803 
7804 	struct mlx5_ifc_tisc_bits ctx;
7805 };
7806 
7807 struct mlx5_ifc_modify_tir_bitmask_bits {
7808 	u8	   reserved_at_0[0x20];
7809 
7810 	u8         reserved_at_20[0x1b];
7811 	u8         self_lb_en[0x1];
7812 	u8         reserved_at_3c[0x1];
7813 	u8         hash[0x1];
7814 	u8         reserved_at_3e[0x1];
7815 	u8         packet_merge[0x1];
7816 };
7817 
7818 struct mlx5_ifc_modify_tir_out_bits {
7819 	u8         status[0x8];
7820 	u8         reserved_at_8[0x18];
7821 
7822 	u8         syndrome[0x20];
7823 
7824 	u8         reserved_at_40[0x40];
7825 };
7826 
7827 struct mlx5_ifc_modify_tir_in_bits {
7828 	u8         opcode[0x10];
7829 	u8         uid[0x10];
7830 
7831 	u8         reserved_at_20[0x10];
7832 	u8         op_mod[0x10];
7833 
7834 	u8         reserved_at_40[0x8];
7835 	u8         tirn[0x18];
7836 
7837 	u8         reserved_at_60[0x20];
7838 
7839 	struct mlx5_ifc_modify_tir_bitmask_bits bitmask;
7840 
7841 	u8         reserved_at_c0[0x40];
7842 
7843 	struct mlx5_ifc_tirc_bits ctx;
7844 };
7845 
7846 struct mlx5_ifc_modify_sq_out_bits {
7847 	u8         status[0x8];
7848 	u8         reserved_at_8[0x18];
7849 
7850 	u8         syndrome[0x20];
7851 
7852 	u8         reserved_at_40[0x40];
7853 };
7854 
7855 struct mlx5_ifc_modify_sq_in_bits {
7856 	u8         opcode[0x10];
7857 	u8         uid[0x10];
7858 
7859 	u8         reserved_at_20[0x10];
7860 	u8         op_mod[0x10];
7861 
7862 	u8         sq_state[0x4];
7863 	u8         reserved_at_44[0x4];
7864 	u8         sqn[0x18];
7865 
7866 	u8         reserved_at_60[0x20];
7867 
7868 	u8         modify_bitmask[0x40];
7869 
7870 	u8         reserved_at_c0[0x40];
7871 
7872 	struct mlx5_ifc_sqc_bits ctx;
7873 };
7874 
7875 struct mlx5_ifc_modify_scheduling_element_out_bits {
7876 	u8         status[0x8];
7877 	u8         reserved_at_8[0x18];
7878 
7879 	u8         syndrome[0x20];
7880 
7881 	u8         reserved_at_40[0x1c0];
7882 };
7883 
7884 enum {
7885 	MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1,
7886 	MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2,
7887 };
7888 
7889 struct mlx5_ifc_modify_scheduling_element_in_bits {
7890 	u8         opcode[0x10];
7891 	u8         reserved_at_10[0x10];
7892 
7893 	u8         reserved_at_20[0x10];
7894 	u8         op_mod[0x10];
7895 
7896 	u8         scheduling_hierarchy[0x8];
7897 	u8         reserved_at_48[0x18];
7898 
7899 	u8         scheduling_element_id[0x20];
7900 
7901 	u8         reserved_at_80[0x20];
7902 
7903 	u8         modify_bitmask[0x20];
7904 
7905 	u8         reserved_at_c0[0x40];
7906 
7907 	struct mlx5_ifc_scheduling_context_bits scheduling_context;
7908 
7909 	u8         reserved_at_300[0x100];
7910 };
7911 
7912 struct mlx5_ifc_modify_rqt_out_bits {
7913 	u8         status[0x8];
7914 	u8         reserved_at_8[0x18];
7915 
7916 	u8         syndrome[0x20];
7917 
7918 	u8         reserved_at_40[0x40];
7919 };
7920 
7921 struct mlx5_ifc_rqt_bitmask_bits {
7922 	u8	   reserved_at_0[0x20];
7923 
7924 	u8         reserved_at_20[0x1f];
7925 	u8         rqn_list[0x1];
7926 };
7927 
7928 struct mlx5_ifc_modify_rqt_in_bits {
7929 	u8         opcode[0x10];
7930 	u8         uid[0x10];
7931 
7932 	u8         reserved_at_20[0x10];
7933 	u8         op_mod[0x10];
7934 
7935 	u8         reserved_at_40[0x8];
7936 	u8         rqtn[0x18];
7937 
7938 	u8         reserved_at_60[0x20];
7939 
7940 	struct mlx5_ifc_rqt_bitmask_bits bitmask;
7941 
7942 	u8         reserved_at_c0[0x40];
7943 
7944 	struct mlx5_ifc_rqtc_bits ctx;
7945 };
7946 
7947 struct mlx5_ifc_modify_rq_out_bits {
7948 	u8         status[0x8];
7949 	u8         reserved_at_8[0x18];
7950 
7951 	u8         syndrome[0x20];
7952 
7953 	u8         reserved_at_40[0x40];
7954 };
7955 
7956 enum {
7957 	MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1,
7958 	MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2,
7959 	MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3,
7960 };
7961 
7962 struct mlx5_ifc_modify_rq_in_bits {
7963 	u8         opcode[0x10];
7964 	u8         uid[0x10];
7965 
7966 	u8         reserved_at_20[0x10];
7967 	u8         op_mod[0x10];
7968 
7969 	u8         rq_state[0x4];
7970 	u8         reserved_at_44[0x4];
7971 	u8         rqn[0x18];
7972 
7973 	u8         reserved_at_60[0x20];
7974 
7975 	u8         modify_bitmask[0x40];
7976 
7977 	u8         reserved_at_c0[0x40];
7978 
7979 	struct mlx5_ifc_rqc_bits ctx;
7980 };
7981 
7982 struct mlx5_ifc_modify_rmp_out_bits {
7983 	u8         status[0x8];
7984 	u8         reserved_at_8[0x18];
7985 
7986 	u8         syndrome[0x20];
7987 
7988 	u8         reserved_at_40[0x40];
7989 };
7990 
7991 struct mlx5_ifc_rmp_bitmask_bits {
7992 	u8	   reserved_at_0[0x20];
7993 
7994 	u8         reserved_at_20[0x1f];
7995 	u8         lwm[0x1];
7996 };
7997 
7998 struct mlx5_ifc_modify_rmp_in_bits {
7999 	u8         opcode[0x10];
8000 	u8         uid[0x10];
8001 
8002 	u8         reserved_at_20[0x10];
8003 	u8         op_mod[0x10];
8004 
8005 	u8         rmp_state[0x4];
8006 	u8         reserved_at_44[0x4];
8007 	u8         rmpn[0x18];
8008 
8009 	u8         reserved_at_60[0x20];
8010 
8011 	struct mlx5_ifc_rmp_bitmask_bits bitmask;
8012 
8013 	u8         reserved_at_c0[0x40];
8014 
8015 	struct mlx5_ifc_rmpc_bits ctx;
8016 };
8017 
8018 struct mlx5_ifc_modify_nic_vport_context_out_bits {
8019 	u8         status[0x8];
8020 	u8         reserved_at_8[0x18];
8021 
8022 	u8         syndrome[0x20];
8023 
8024 	u8         reserved_at_40[0x40];
8025 };
8026 
8027 struct mlx5_ifc_modify_nic_vport_field_select_bits {
8028 	u8         reserved_at_0[0x12];
8029 	u8	   affiliation[0x1];
8030 	u8	   reserved_at_13[0x1];
8031 	u8         disable_uc_local_lb[0x1];
8032 	u8         disable_mc_local_lb[0x1];
8033 	u8         node_guid[0x1];
8034 	u8         port_guid[0x1];
8035 	u8         min_inline[0x1];
8036 	u8         mtu[0x1];
8037 	u8         change_event[0x1];
8038 	u8         promisc[0x1];
8039 	u8         permanent_address[0x1];
8040 	u8         addresses_list[0x1];
8041 	u8         roce_en[0x1];
8042 	u8         reserved_at_1f[0x1];
8043 };
8044 
8045 struct mlx5_ifc_modify_nic_vport_context_in_bits {
8046 	u8         opcode[0x10];
8047 	u8         reserved_at_10[0x10];
8048 
8049 	u8         reserved_at_20[0x10];
8050 	u8         op_mod[0x10];
8051 
8052 	u8         other_vport[0x1];
8053 	u8         reserved_at_41[0xf];
8054 	u8         vport_number[0x10];
8055 
8056 	struct mlx5_ifc_modify_nic_vport_field_select_bits field_select;
8057 
8058 	u8         reserved_at_80[0x780];
8059 
8060 	struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
8061 };
8062 
8063 struct mlx5_ifc_modify_hca_vport_context_out_bits {
8064 	u8         status[0x8];
8065 	u8         reserved_at_8[0x18];
8066 
8067 	u8         syndrome[0x20];
8068 
8069 	u8         reserved_at_40[0x40];
8070 };
8071 
8072 struct mlx5_ifc_modify_hca_vport_context_in_bits {
8073 	u8         opcode[0x10];
8074 	u8         reserved_at_10[0x10];
8075 
8076 	u8         reserved_at_20[0x10];
8077 	u8         op_mod[0x10];
8078 
8079 	u8         other_vport[0x1];
8080 	u8         reserved_at_41[0xb];
8081 	u8         port_num[0x4];
8082 	u8         vport_number[0x10];
8083 
8084 	u8         reserved_at_60[0x20];
8085 
8086 	struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
8087 };
8088 
8089 struct mlx5_ifc_modify_cq_out_bits {
8090 	u8         status[0x8];
8091 	u8         reserved_at_8[0x18];
8092 
8093 	u8         syndrome[0x20];
8094 
8095 	u8         reserved_at_40[0x40];
8096 };
8097 
8098 enum {
8099 	MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ  = 0x0,
8100 	MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ  = 0x1,
8101 };
8102 
8103 struct mlx5_ifc_modify_cq_in_bits {
8104 	u8         opcode[0x10];
8105 	u8         uid[0x10];
8106 
8107 	u8         reserved_at_20[0x10];
8108 	u8         op_mod[0x10];
8109 
8110 	u8         reserved_at_40[0x8];
8111 	u8         cqn[0x18];
8112 
8113 	union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select;
8114 
8115 	struct mlx5_ifc_cqc_bits cq_context;
8116 
8117 	u8         reserved_at_280[0x60];
8118 
8119 	u8         cq_umem_valid[0x1];
8120 	u8         reserved_at_2e1[0x1f];
8121 
8122 	u8         reserved_at_300[0x580];
8123 
8124 	u8         pas[][0x40];
8125 };
8126 
8127 struct mlx5_ifc_modify_cong_status_out_bits {
8128 	u8         status[0x8];
8129 	u8         reserved_at_8[0x18];
8130 
8131 	u8         syndrome[0x20];
8132 
8133 	u8         reserved_at_40[0x40];
8134 };
8135 
8136 struct mlx5_ifc_modify_cong_status_in_bits {
8137 	u8         opcode[0x10];
8138 	u8         reserved_at_10[0x10];
8139 
8140 	u8         reserved_at_20[0x10];
8141 	u8         op_mod[0x10];
8142 
8143 	u8         reserved_at_40[0x18];
8144 	u8         priority[0x4];
8145 	u8         cong_protocol[0x4];
8146 
8147 	u8         enable[0x1];
8148 	u8         tag_enable[0x1];
8149 	u8         reserved_at_62[0x1e];
8150 };
8151 
8152 struct mlx5_ifc_modify_cong_params_out_bits {
8153 	u8         status[0x8];
8154 	u8         reserved_at_8[0x18];
8155 
8156 	u8         syndrome[0x20];
8157 
8158 	u8         reserved_at_40[0x40];
8159 };
8160 
8161 struct mlx5_ifc_modify_cong_params_in_bits {
8162 	u8         opcode[0x10];
8163 	u8         reserved_at_10[0x10];
8164 
8165 	u8         reserved_at_20[0x10];
8166 	u8         op_mod[0x10];
8167 
8168 	u8         reserved_at_40[0x1c];
8169 	u8         cong_protocol[0x4];
8170 
8171 	union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select;
8172 
8173 	u8         reserved_at_80[0x80];
8174 
8175 	union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
8176 };
8177 
8178 struct mlx5_ifc_manage_pages_out_bits {
8179 	u8         status[0x8];
8180 	u8         reserved_at_8[0x18];
8181 
8182 	u8         syndrome[0x20];
8183 
8184 	u8         output_num_entries[0x20];
8185 
8186 	u8         reserved_at_60[0x20];
8187 
8188 	u8         pas[][0x40];
8189 };
8190 
8191 enum {
8192 	MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL     = 0x0,
8193 	MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS  = 0x1,
8194 	MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES    = 0x2,
8195 };
8196 
8197 struct mlx5_ifc_manage_pages_in_bits {
8198 	u8         opcode[0x10];
8199 	u8         reserved_at_10[0x10];
8200 
8201 	u8         reserved_at_20[0x10];
8202 	u8         op_mod[0x10];
8203 
8204 	u8         embedded_cpu_function[0x1];
8205 	u8         reserved_at_41[0xf];
8206 	u8         function_id[0x10];
8207 
8208 	u8         input_num_entries[0x20];
8209 
8210 	u8         pas[][0x40];
8211 };
8212 
8213 struct mlx5_ifc_mad_ifc_out_bits {
8214 	u8         status[0x8];
8215 	u8         reserved_at_8[0x18];
8216 
8217 	u8         syndrome[0x20];
8218 
8219 	u8         reserved_at_40[0x40];
8220 
8221 	u8         response_mad_packet[256][0x8];
8222 };
8223 
8224 struct mlx5_ifc_mad_ifc_in_bits {
8225 	u8         opcode[0x10];
8226 	u8         reserved_at_10[0x10];
8227 
8228 	u8         reserved_at_20[0x10];
8229 	u8         op_mod[0x10];
8230 
8231 	u8         remote_lid[0x10];
8232 	u8         plane_index[0x8];
8233 	u8         port[0x8];
8234 
8235 	u8         reserved_at_60[0x20];
8236 
8237 	u8         mad[256][0x8];
8238 };
8239 
8240 struct mlx5_ifc_init_hca_out_bits {
8241 	u8         status[0x8];
8242 	u8         reserved_at_8[0x18];
8243 
8244 	u8         syndrome[0x20];
8245 
8246 	u8         reserved_at_40[0x40];
8247 };
8248 
8249 struct mlx5_ifc_init_hca_in_bits {
8250 	u8         opcode[0x10];
8251 	u8         reserved_at_10[0x10];
8252 
8253 	u8         reserved_at_20[0x10];
8254 	u8         op_mod[0x10];
8255 
8256 	u8         reserved_at_40[0x20];
8257 
8258 	u8         reserved_at_60[0x2];
8259 	u8         sw_vhca_id[0xe];
8260 	u8         reserved_at_70[0x10];
8261 
8262 	u8	   sw_owner_id[4][0x20];
8263 };
8264 
8265 struct mlx5_ifc_init2rtr_qp_out_bits {
8266 	u8         status[0x8];
8267 	u8         reserved_at_8[0x18];
8268 
8269 	u8         syndrome[0x20];
8270 
8271 	u8         reserved_at_40[0x20];
8272 	u8         ece[0x20];
8273 };
8274 
8275 struct mlx5_ifc_init2rtr_qp_in_bits {
8276 	u8         opcode[0x10];
8277 	u8         uid[0x10];
8278 
8279 	u8         reserved_at_20[0x10];
8280 	u8         op_mod[0x10];
8281 
8282 	u8         reserved_at_40[0x8];
8283 	u8         qpn[0x18];
8284 
8285 	u8         reserved_at_60[0x20];
8286 
8287 	u8         opt_param_mask[0x20];
8288 
8289 	u8         ece[0x20];
8290 
8291 	struct mlx5_ifc_qpc_bits qpc;
8292 
8293 	u8         reserved_at_800[0x80];
8294 };
8295 
8296 struct mlx5_ifc_init2init_qp_out_bits {
8297 	u8         status[0x8];
8298 	u8         reserved_at_8[0x18];
8299 
8300 	u8         syndrome[0x20];
8301 
8302 	u8         reserved_at_40[0x20];
8303 	u8         ece[0x20];
8304 };
8305 
8306 struct mlx5_ifc_init2init_qp_in_bits {
8307 	u8         opcode[0x10];
8308 	u8         uid[0x10];
8309 
8310 	u8         reserved_at_20[0x10];
8311 	u8         op_mod[0x10];
8312 
8313 	u8         reserved_at_40[0x8];
8314 	u8         qpn[0x18];
8315 
8316 	u8         reserved_at_60[0x20];
8317 
8318 	u8         opt_param_mask[0x20];
8319 
8320 	u8         ece[0x20];
8321 
8322 	struct mlx5_ifc_qpc_bits qpc;
8323 
8324 	u8         reserved_at_800[0x80];
8325 };
8326 
8327 struct mlx5_ifc_get_dropped_packet_log_out_bits {
8328 	u8         status[0x8];
8329 	u8         reserved_at_8[0x18];
8330 
8331 	u8         syndrome[0x20];
8332 
8333 	u8         reserved_at_40[0x40];
8334 
8335 	u8         packet_headers_log[128][0x8];
8336 
8337 	u8         packet_syndrome[64][0x8];
8338 };
8339 
8340 struct mlx5_ifc_get_dropped_packet_log_in_bits {
8341 	u8         opcode[0x10];
8342 	u8         reserved_at_10[0x10];
8343 
8344 	u8         reserved_at_20[0x10];
8345 	u8         op_mod[0x10];
8346 
8347 	u8         reserved_at_40[0x40];
8348 };
8349 
8350 struct mlx5_ifc_gen_eqe_in_bits {
8351 	u8         opcode[0x10];
8352 	u8         reserved_at_10[0x10];
8353 
8354 	u8         reserved_at_20[0x10];
8355 	u8         op_mod[0x10];
8356 
8357 	u8         reserved_at_40[0x18];
8358 	u8         eq_number[0x8];
8359 
8360 	u8         reserved_at_60[0x20];
8361 
8362 	u8         eqe[64][0x8];
8363 };
8364 
8365 struct mlx5_ifc_gen_eq_out_bits {
8366 	u8         status[0x8];
8367 	u8         reserved_at_8[0x18];
8368 
8369 	u8         syndrome[0x20];
8370 
8371 	u8         reserved_at_40[0x40];
8372 };
8373 
8374 struct mlx5_ifc_enable_hca_out_bits {
8375 	u8         status[0x8];
8376 	u8         reserved_at_8[0x18];
8377 
8378 	u8         syndrome[0x20];
8379 
8380 	u8         reserved_at_40[0x20];
8381 };
8382 
8383 struct mlx5_ifc_enable_hca_in_bits {
8384 	u8         opcode[0x10];
8385 	u8         reserved_at_10[0x10];
8386 
8387 	u8         reserved_at_20[0x10];
8388 	u8         op_mod[0x10];
8389 
8390 	u8         embedded_cpu_function[0x1];
8391 	u8         reserved_at_41[0xf];
8392 	u8         function_id[0x10];
8393 
8394 	u8         reserved_at_60[0x20];
8395 };
8396 
8397 struct mlx5_ifc_drain_dct_out_bits {
8398 	u8         status[0x8];
8399 	u8         reserved_at_8[0x18];
8400 
8401 	u8         syndrome[0x20];
8402 
8403 	u8         reserved_at_40[0x40];
8404 };
8405 
8406 struct mlx5_ifc_drain_dct_in_bits {
8407 	u8         opcode[0x10];
8408 	u8         uid[0x10];
8409 
8410 	u8         reserved_at_20[0x10];
8411 	u8         op_mod[0x10];
8412 
8413 	u8         reserved_at_40[0x8];
8414 	u8         dctn[0x18];
8415 
8416 	u8         reserved_at_60[0x20];
8417 };
8418 
8419 struct mlx5_ifc_disable_hca_out_bits {
8420 	u8         status[0x8];
8421 	u8         reserved_at_8[0x18];
8422 
8423 	u8         syndrome[0x20];
8424 
8425 	u8         reserved_at_40[0x20];
8426 };
8427 
8428 struct mlx5_ifc_disable_hca_in_bits {
8429 	u8         opcode[0x10];
8430 	u8         reserved_at_10[0x10];
8431 
8432 	u8         reserved_at_20[0x10];
8433 	u8         op_mod[0x10];
8434 
8435 	u8         embedded_cpu_function[0x1];
8436 	u8         reserved_at_41[0xf];
8437 	u8         function_id[0x10];
8438 
8439 	u8         reserved_at_60[0x20];
8440 };
8441 
8442 struct mlx5_ifc_detach_from_mcg_out_bits {
8443 	u8         status[0x8];
8444 	u8         reserved_at_8[0x18];
8445 
8446 	u8         syndrome[0x20];
8447 
8448 	u8         reserved_at_40[0x40];
8449 };
8450 
8451 struct mlx5_ifc_detach_from_mcg_in_bits {
8452 	u8         opcode[0x10];
8453 	u8         uid[0x10];
8454 
8455 	u8         reserved_at_20[0x10];
8456 	u8         op_mod[0x10];
8457 
8458 	u8         reserved_at_40[0x8];
8459 	u8         qpn[0x18];
8460 
8461 	u8         reserved_at_60[0x20];
8462 
8463 	u8         multicast_gid[16][0x8];
8464 };
8465 
8466 struct mlx5_ifc_destroy_xrq_out_bits {
8467 	u8         status[0x8];
8468 	u8         reserved_at_8[0x18];
8469 
8470 	u8         syndrome[0x20];
8471 
8472 	u8         reserved_at_40[0x40];
8473 };
8474 
8475 struct mlx5_ifc_destroy_xrq_in_bits {
8476 	u8         opcode[0x10];
8477 	u8         uid[0x10];
8478 
8479 	u8         reserved_at_20[0x10];
8480 	u8         op_mod[0x10];
8481 
8482 	u8         reserved_at_40[0x8];
8483 	u8         xrqn[0x18];
8484 
8485 	u8         reserved_at_60[0x20];
8486 };
8487 
8488 struct mlx5_ifc_destroy_xrc_srq_out_bits {
8489 	u8         status[0x8];
8490 	u8         reserved_at_8[0x18];
8491 
8492 	u8         syndrome[0x20];
8493 
8494 	u8         reserved_at_40[0x40];
8495 };
8496 
8497 struct mlx5_ifc_destroy_xrc_srq_in_bits {
8498 	u8         opcode[0x10];
8499 	u8         uid[0x10];
8500 
8501 	u8         reserved_at_20[0x10];
8502 	u8         op_mod[0x10];
8503 
8504 	u8         reserved_at_40[0x8];
8505 	u8         xrc_srqn[0x18];
8506 
8507 	u8         reserved_at_60[0x20];
8508 };
8509 
8510 struct mlx5_ifc_destroy_tis_out_bits {
8511 	u8         status[0x8];
8512 	u8         reserved_at_8[0x18];
8513 
8514 	u8         syndrome[0x20];
8515 
8516 	u8         reserved_at_40[0x40];
8517 };
8518 
8519 struct mlx5_ifc_destroy_tis_in_bits {
8520 	u8         opcode[0x10];
8521 	u8         uid[0x10];
8522 
8523 	u8         reserved_at_20[0x10];
8524 	u8         op_mod[0x10];
8525 
8526 	u8         reserved_at_40[0x8];
8527 	u8         tisn[0x18];
8528 
8529 	u8         reserved_at_60[0x20];
8530 };
8531 
8532 struct mlx5_ifc_destroy_tir_out_bits {
8533 	u8         status[0x8];
8534 	u8         reserved_at_8[0x18];
8535 
8536 	u8         syndrome[0x20];
8537 
8538 	u8         reserved_at_40[0x40];
8539 };
8540 
8541 struct mlx5_ifc_destroy_tir_in_bits {
8542 	u8         opcode[0x10];
8543 	u8         uid[0x10];
8544 
8545 	u8         reserved_at_20[0x10];
8546 	u8         op_mod[0x10];
8547 
8548 	u8         reserved_at_40[0x8];
8549 	u8         tirn[0x18];
8550 
8551 	u8         reserved_at_60[0x20];
8552 };
8553 
8554 struct mlx5_ifc_destroy_srq_out_bits {
8555 	u8         status[0x8];
8556 	u8         reserved_at_8[0x18];
8557 
8558 	u8         syndrome[0x20];
8559 
8560 	u8         reserved_at_40[0x40];
8561 };
8562 
8563 struct mlx5_ifc_destroy_srq_in_bits {
8564 	u8         opcode[0x10];
8565 	u8         uid[0x10];
8566 
8567 	u8         reserved_at_20[0x10];
8568 	u8         op_mod[0x10];
8569 
8570 	u8         reserved_at_40[0x8];
8571 	u8         srqn[0x18];
8572 
8573 	u8         reserved_at_60[0x20];
8574 };
8575 
8576 struct mlx5_ifc_destroy_sq_out_bits {
8577 	u8         status[0x8];
8578 	u8         reserved_at_8[0x18];
8579 
8580 	u8         syndrome[0x20];
8581 
8582 	u8         reserved_at_40[0x40];
8583 };
8584 
8585 struct mlx5_ifc_destroy_sq_in_bits {
8586 	u8         opcode[0x10];
8587 	u8         uid[0x10];
8588 
8589 	u8         reserved_at_20[0x10];
8590 	u8         op_mod[0x10];
8591 
8592 	u8         reserved_at_40[0x8];
8593 	u8         sqn[0x18];
8594 
8595 	u8         reserved_at_60[0x20];
8596 };
8597 
8598 struct mlx5_ifc_destroy_scheduling_element_out_bits {
8599 	u8         status[0x8];
8600 	u8         reserved_at_8[0x18];
8601 
8602 	u8         syndrome[0x20];
8603 
8604 	u8         reserved_at_40[0x1c0];
8605 };
8606 
8607 struct mlx5_ifc_destroy_scheduling_element_in_bits {
8608 	u8         opcode[0x10];
8609 	u8         reserved_at_10[0x10];
8610 
8611 	u8         reserved_at_20[0x10];
8612 	u8         op_mod[0x10];
8613 
8614 	u8         scheduling_hierarchy[0x8];
8615 	u8         reserved_at_48[0x18];
8616 
8617 	u8         scheduling_element_id[0x20];
8618 
8619 	u8         reserved_at_80[0x180];
8620 };
8621 
8622 struct mlx5_ifc_destroy_rqt_out_bits {
8623 	u8         status[0x8];
8624 	u8         reserved_at_8[0x18];
8625 
8626 	u8         syndrome[0x20];
8627 
8628 	u8         reserved_at_40[0x40];
8629 };
8630 
8631 struct mlx5_ifc_destroy_rqt_in_bits {
8632 	u8         opcode[0x10];
8633 	u8         uid[0x10];
8634 
8635 	u8         reserved_at_20[0x10];
8636 	u8         op_mod[0x10];
8637 
8638 	u8         reserved_at_40[0x8];
8639 	u8         rqtn[0x18];
8640 
8641 	u8         reserved_at_60[0x20];
8642 };
8643 
8644 struct mlx5_ifc_destroy_rq_out_bits {
8645 	u8         status[0x8];
8646 	u8         reserved_at_8[0x18];
8647 
8648 	u8         syndrome[0x20];
8649 
8650 	u8         reserved_at_40[0x40];
8651 };
8652 
8653 struct mlx5_ifc_destroy_rq_in_bits {
8654 	u8         opcode[0x10];
8655 	u8         uid[0x10];
8656 
8657 	u8         reserved_at_20[0x10];
8658 	u8         op_mod[0x10];
8659 
8660 	u8         reserved_at_40[0x8];
8661 	u8         rqn[0x18];
8662 
8663 	u8         reserved_at_60[0x20];
8664 };
8665 
8666 struct mlx5_ifc_set_delay_drop_params_in_bits {
8667 	u8         opcode[0x10];
8668 	u8         reserved_at_10[0x10];
8669 
8670 	u8         reserved_at_20[0x10];
8671 	u8         op_mod[0x10];
8672 
8673 	u8         reserved_at_40[0x20];
8674 
8675 	u8         reserved_at_60[0x10];
8676 	u8         delay_drop_timeout[0x10];
8677 };
8678 
8679 struct mlx5_ifc_set_delay_drop_params_out_bits {
8680 	u8         status[0x8];
8681 	u8         reserved_at_8[0x18];
8682 
8683 	u8         syndrome[0x20];
8684 
8685 	u8         reserved_at_40[0x40];
8686 };
8687 
8688 struct mlx5_ifc_destroy_rmp_out_bits {
8689 	u8         status[0x8];
8690 	u8         reserved_at_8[0x18];
8691 
8692 	u8         syndrome[0x20];
8693 
8694 	u8         reserved_at_40[0x40];
8695 };
8696 
8697 struct mlx5_ifc_destroy_rmp_in_bits {
8698 	u8         opcode[0x10];
8699 	u8         uid[0x10];
8700 
8701 	u8         reserved_at_20[0x10];
8702 	u8         op_mod[0x10];
8703 
8704 	u8         reserved_at_40[0x8];
8705 	u8         rmpn[0x18];
8706 
8707 	u8         reserved_at_60[0x20];
8708 };
8709 
8710 struct mlx5_ifc_destroy_qp_out_bits {
8711 	u8         status[0x8];
8712 	u8         reserved_at_8[0x18];
8713 
8714 	u8         syndrome[0x20];
8715 
8716 	u8         reserved_at_40[0x40];
8717 };
8718 
8719 struct mlx5_ifc_destroy_qp_in_bits {
8720 	u8         opcode[0x10];
8721 	u8         uid[0x10];
8722 
8723 	u8         reserved_at_20[0x10];
8724 	u8         op_mod[0x10];
8725 
8726 	u8         reserved_at_40[0x8];
8727 	u8         qpn[0x18];
8728 
8729 	u8         reserved_at_60[0x20];
8730 };
8731 
8732 struct mlx5_ifc_destroy_psv_out_bits {
8733 	u8         status[0x8];
8734 	u8         reserved_at_8[0x18];
8735 
8736 	u8         syndrome[0x20];
8737 
8738 	u8         reserved_at_40[0x40];
8739 };
8740 
8741 struct mlx5_ifc_destroy_psv_in_bits {
8742 	u8         opcode[0x10];
8743 	u8         reserved_at_10[0x10];
8744 
8745 	u8         reserved_at_20[0x10];
8746 	u8         op_mod[0x10];
8747 
8748 	u8         reserved_at_40[0x8];
8749 	u8         psvn[0x18];
8750 
8751 	u8         reserved_at_60[0x20];
8752 };
8753 
8754 struct mlx5_ifc_destroy_mkey_out_bits {
8755 	u8         status[0x8];
8756 	u8         reserved_at_8[0x18];
8757 
8758 	u8         syndrome[0x20];
8759 
8760 	u8         reserved_at_40[0x40];
8761 };
8762 
8763 struct mlx5_ifc_destroy_mkey_in_bits {
8764 	u8         opcode[0x10];
8765 	u8         uid[0x10];
8766 
8767 	u8         reserved_at_20[0x10];
8768 	u8         op_mod[0x10];
8769 
8770 	u8         reserved_at_40[0x8];
8771 	u8         mkey_index[0x18];
8772 
8773 	u8         reserved_at_60[0x20];
8774 };
8775 
8776 struct mlx5_ifc_destroy_flow_table_out_bits {
8777 	u8         status[0x8];
8778 	u8         reserved_at_8[0x18];
8779 
8780 	u8         syndrome[0x20];
8781 
8782 	u8         reserved_at_40[0x40];
8783 };
8784 
8785 struct mlx5_ifc_destroy_flow_table_in_bits {
8786 	u8         opcode[0x10];
8787 	u8         reserved_at_10[0x10];
8788 
8789 	u8         reserved_at_20[0x10];
8790 	u8         op_mod[0x10];
8791 
8792 	u8         other_vport[0x1];
8793 	u8         reserved_at_41[0xf];
8794 	u8         vport_number[0x10];
8795 
8796 	u8         reserved_at_60[0x20];
8797 
8798 	u8         table_type[0x8];
8799 	u8         reserved_at_88[0x18];
8800 
8801 	u8         reserved_at_a0[0x8];
8802 	u8         table_id[0x18];
8803 
8804 	u8         reserved_at_c0[0x140];
8805 };
8806 
8807 struct mlx5_ifc_destroy_flow_group_out_bits {
8808 	u8         status[0x8];
8809 	u8         reserved_at_8[0x18];
8810 
8811 	u8         syndrome[0x20];
8812 
8813 	u8         reserved_at_40[0x40];
8814 };
8815 
8816 struct mlx5_ifc_destroy_flow_group_in_bits {
8817 	u8         opcode[0x10];
8818 	u8         reserved_at_10[0x10];
8819 
8820 	u8         reserved_at_20[0x10];
8821 	u8         op_mod[0x10];
8822 
8823 	u8         other_vport[0x1];
8824 	u8         reserved_at_41[0xf];
8825 	u8         vport_number[0x10];
8826 
8827 	u8         reserved_at_60[0x20];
8828 
8829 	u8         table_type[0x8];
8830 	u8         reserved_at_88[0x18];
8831 
8832 	u8         reserved_at_a0[0x8];
8833 	u8         table_id[0x18];
8834 
8835 	u8         group_id[0x20];
8836 
8837 	u8         reserved_at_e0[0x120];
8838 };
8839 
8840 struct mlx5_ifc_destroy_eq_out_bits {
8841 	u8         status[0x8];
8842 	u8         reserved_at_8[0x18];
8843 
8844 	u8         syndrome[0x20];
8845 
8846 	u8         reserved_at_40[0x40];
8847 };
8848 
8849 struct mlx5_ifc_destroy_eq_in_bits {
8850 	u8         opcode[0x10];
8851 	u8         reserved_at_10[0x10];
8852 
8853 	u8         reserved_at_20[0x10];
8854 	u8         op_mod[0x10];
8855 
8856 	u8         reserved_at_40[0x18];
8857 	u8         eq_number[0x8];
8858 
8859 	u8         reserved_at_60[0x20];
8860 };
8861 
8862 struct mlx5_ifc_destroy_dct_out_bits {
8863 	u8         status[0x8];
8864 	u8         reserved_at_8[0x18];
8865 
8866 	u8         syndrome[0x20];
8867 
8868 	u8         reserved_at_40[0x40];
8869 };
8870 
8871 struct mlx5_ifc_destroy_dct_in_bits {
8872 	u8         opcode[0x10];
8873 	u8         uid[0x10];
8874 
8875 	u8         reserved_at_20[0x10];
8876 	u8         op_mod[0x10];
8877 
8878 	u8         reserved_at_40[0x8];
8879 	u8         dctn[0x18];
8880 
8881 	u8         reserved_at_60[0x20];
8882 };
8883 
8884 struct mlx5_ifc_destroy_cq_out_bits {
8885 	u8         status[0x8];
8886 	u8         reserved_at_8[0x18];
8887 
8888 	u8         syndrome[0x20];
8889 
8890 	u8         reserved_at_40[0x40];
8891 };
8892 
8893 struct mlx5_ifc_destroy_cq_in_bits {
8894 	u8         opcode[0x10];
8895 	u8         uid[0x10];
8896 
8897 	u8         reserved_at_20[0x10];
8898 	u8         op_mod[0x10];
8899 
8900 	u8         reserved_at_40[0x8];
8901 	u8         cqn[0x18];
8902 
8903 	u8         reserved_at_60[0x20];
8904 };
8905 
8906 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits {
8907 	u8         status[0x8];
8908 	u8         reserved_at_8[0x18];
8909 
8910 	u8         syndrome[0x20];
8911 
8912 	u8         reserved_at_40[0x40];
8913 };
8914 
8915 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits {
8916 	u8         opcode[0x10];
8917 	u8         reserved_at_10[0x10];
8918 
8919 	u8         reserved_at_20[0x10];
8920 	u8         op_mod[0x10];
8921 
8922 	u8         reserved_at_40[0x20];
8923 
8924 	u8         reserved_at_60[0x10];
8925 	u8         vxlan_udp_port[0x10];
8926 };
8927 
8928 struct mlx5_ifc_delete_l2_table_entry_out_bits {
8929 	u8         status[0x8];
8930 	u8         reserved_at_8[0x18];
8931 
8932 	u8         syndrome[0x20];
8933 
8934 	u8         reserved_at_40[0x40];
8935 };
8936 
8937 struct mlx5_ifc_delete_l2_table_entry_in_bits {
8938 	u8         opcode[0x10];
8939 	u8         reserved_at_10[0x10];
8940 
8941 	u8         reserved_at_20[0x10];
8942 	u8         op_mod[0x10];
8943 
8944 	u8         reserved_at_40[0x60];
8945 
8946 	u8         reserved_at_a0[0x8];
8947 	u8         table_index[0x18];
8948 
8949 	u8         reserved_at_c0[0x140];
8950 };
8951 
8952 struct mlx5_ifc_delete_fte_out_bits {
8953 	u8         status[0x8];
8954 	u8         reserved_at_8[0x18];
8955 
8956 	u8         syndrome[0x20];
8957 
8958 	u8         reserved_at_40[0x40];
8959 };
8960 
8961 struct mlx5_ifc_delete_fte_in_bits {
8962 	u8         opcode[0x10];
8963 	u8         reserved_at_10[0x10];
8964 
8965 	u8         reserved_at_20[0x10];
8966 	u8         op_mod[0x10];
8967 
8968 	u8         other_vport[0x1];
8969 	u8         reserved_at_41[0xf];
8970 	u8         vport_number[0x10];
8971 
8972 	u8         reserved_at_60[0x20];
8973 
8974 	u8         table_type[0x8];
8975 	u8         reserved_at_88[0x18];
8976 
8977 	u8         reserved_at_a0[0x8];
8978 	u8         table_id[0x18];
8979 
8980 	u8         reserved_at_c0[0x40];
8981 
8982 	u8         flow_index[0x20];
8983 
8984 	u8         reserved_at_120[0xe0];
8985 };
8986 
8987 struct mlx5_ifc_dealloc_xrcd_out_bits {
8988 	u8         status[0x8];
8989 	u8         reserved_at_8[0x18];
8990 
8991 	u8         syndrome[0x20];
8992 
8993 	u8         reserved_at_40[0x40];
8994 };
8995 
8996 struct mlx5_ifc_dealloc_xrcd_in_bits {
8997 	u8         opcode[0x10];
8998 	u8         uid[0x10];
8999 
9000 	u8         reserved_at_20[0x10];
9001 	u8         op_mod[0x10];
9002 
9003 	u8         reserved_at_40[0x8];
9004 	u8         xrcd[0x18];
9005 
9006 	u8         reserved_at_60[0x20];
9007 };
9008 
9009 struct mlx5_ifc_dealloc_uar_out_bits {
9010 	u8         status[0x8];
9011 	u8         reserved_at_8[0x18];
9012 
9013 	u8         syndrome[0x20];
9014 
9015 	u8         reserved_at_40[0x40];
9016 };
9017 
9018 struct mlx5_ifc_dealloc_uar_in_bits {
9019 	u8         opcode[0x10];
9020 	u8         uid[0x10];
9021 
9022 	u8         reserved_at_20[0x10];
9023 	u8         op_mod[0x10];
9024 
9025 	u8         reserved_at_40[0x8];
9026 	u8         uar[0x18];
9027 
9028 	u8         reserved_at_60[0x20];
9029 };
9030 
9031 struct mlx5_ifc_dealloc_transport_domain_out_bits {
9032 	u8         status[0x8];
9033 	u8         reserved_at_8[0x18];
9034 
9035 	u8         syndrome[0x20];
9036 
9037 	u8         reserved_at_40[0x40];
9038 };
9039 
9040 struct mlx5_ifc_dealloc_transport_domain_in_bits {
9041 	u8         opcode[0x10];
9042 	u8         uid[0x10];
9043 
9044 	u8         reserved_at_20[0x10];
9045 	u8         op_mod[0x10];
9046 
9047 	u8         reserved_at_40[0x8];
9048 	u8         transport_domain[0x18];
9049 
9050 	u8         reserved_at_60[0x20];
9051 };
9052 
9053 struct mlx5_ifc_dealloc_q_counter_out_bits {
9054 	u8         status[0x8];
9055 	u8         reserved_at_8[0x18];
9056 
9057 	u8         syndrome[0x20];
9058 
9059 	u8         reserved_at_40[0x40];
9060 };
9061 
9062 struct mlx5_ifc_dealloc_q_counter_in_bits {
9063 	u8         opcode[0x10];
9064 	u8         reserved_at_10[0x10];
9065 
9066 	u8         reserved_at_20[0x10];
9067 	u8         op_mod[0x10];
9068 
9069 	u8         reserved_at_40[0x18];
9070 	u8         counter_set_id[0x8];
9071 
9072 	u8         reserved_at_60[0x20];
9073 };
9074 
9075 struct mlx5_ifc_dealloc_pd_out_bits {
9076 	u8         status[0x8];
9077 	u8         reserved_at_8[0x18];
9078 
9079 	u8         syndrome[0x20];
9080 
9081 	u8         reserved_at_40[0x40];
9082 };
9083 
9084 struct mlx5_ifc_dealloc_pd_in_bits {
9085 	u8         opcode[0x10];
9086 	u8         uid[0x10];
9087 
9088 	u8         reserved_at_20[0x10];
9089 	u8         op_mod[0x10];
9090 
9091 	u8         reserved_at_40[0x8];
9092 	u8         pd[0x18];
9093 
9094 	u8         reserved_at_60[0x20];
9095 };
9096 
9097 struct mlx5_ifc_dealloc_flow_counter_out_bits {
9098 	u8         status[0x8];
9099 	u8         reserved_at_8[0x18];
9100 
9101 	u8         syndrome[0x20];
9102 
9103 	u8         reserved_at_40[0x40];
9104 };
9105 
9106 struct mlx5_ifc_dealloc_flow_counter_in_bits {
9107 	u8         opcode[0x10];
9108 	u8         reserved_at_10[0x10];
9109 
9110 	u8         reserved_at_20[0x10];
9111 	u8         op_mod[0x10];
9112 
9113 	u8         flow_counter_id[0x20];
9114 
9115 	u8         reserved_at_60[0x20];
9116 };
9117 
9118 struct mlx5_ifc_create_xrq_out_bits {
9119 	u8         status[0x8];
9120 	u8         reserved_at_8[0x18];
9121 
9122 	u8         syndrome[0x20];
9123 
9124 	u8         reserved_at_40[0x8];
9125 	u8         xrqn[0x18];
9126 
9127 	u8         reserved_at_60[0x20];
9128 };
9129 
9130 struct mlx5_ifc_create_xrq_in_bits {
9131 	u8         opcode[0x10];
9132 	u8         uid[0x10];
9133 
9134 	u8         reserved_at_20[0x10];
9135 	u8         op_mod[0x10];
9136 
9137 	u8         reserved_at_40[0x40];
9138 
9139 	struct mlx5_ifc_xrqc_bits xrq_context;
9140 };
9141 
9142 struct mlx5_ifc_create_xrc_srq_out_bits {
9143 	u8         status[0x8];
9144 	u8         reserved_at_8[0x18];
9145 
9146 	u8         syndrome[0x20];
9147 
9148 	u8         reserved_at_40[0x8];
9149 	u8         xrc_srqn[0x18];
9150 
9151 	u8         reserved_at_60[0x20];
9152 };
9153 
9154 struct mlx5_ifc_create_xrc_srq_in_bits {
9155 	u8         opcode[0x10];
9156 	u8         uid[0x10];
9157 
9158 	u8         reserved_at_20[0x10];
9159 	u8         op_mod[0x10];
9160 
9161 	u8         reserved_at_40[0x40];
9162 
9163 	struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
9164 
9165 	u8         reserved_at_280[0x60];
9166 
9167 	u8         xrc_srq_umem_valid[0x1];
9168 	u8         reserved_at_2e1[0x1f];
9169 
9170 	u8         reserved_at_300[0x580];
9171 
9172 	u8         pas[][0x40];
9173 };
9174 
9175 struct mlx5_ifc_create_tis_out_bits {
9176 	u8         status[0x8];
9177 	u8         reserved_at_8[0x18];
9178 
9179 	u8         syndrome[0x20];
9180 
9181 	u8         reserved_at_40[0x8];
9182 	u8         tisn[0x18];
9183 
9184 	u8         reserved_at_60[0x20];
9185 };
9186 
9187 struct mlx5_ifc_create_tis_in_bits {
9188 	u8         opcode[0x10];
9189 	u8         uid[0x10];
9190 
9191 	u8         reserved_at_20[0x10];
9192 	u8         op_mod[0x10];
9193 
9194 	u8         reserved_at_40[0xc0];
9195 
9196 	struct mlx5_ifc_tisc_bits ctx;
9197 };
9198 
9199 struct mlx5_ifc_create_tir_out_bits {
9200 	u8         status[0x8];
9201 	u8         icm_address_63_40[0x18];
9202 
9203 	u8         syndrome[0x20];
9204 
9205 	u8         icm_address_39_32[0x8];
9206 	u8         tirn[0x18];
9207 
9208 	u8         icm_address_31_0[0x20];
9209 };
9210 
9211 struct mlx5_ifc_create_tir_in_bits {
9212 	u8         opcode[0x10];
9213 	u8         uid[0x10];
9214 
9215 	u8         reserved_at_20[0x10];
9216 	u8         op_mod[0x10];
9217 
9218 	u8         reserved_at_40[0xc0];
9219 
9220 	struct mlx5_ifc_tirc_bits ctx;
9221 };
9222 
9223 struct mlx5_ifc_create_srq_out_bits {
9224 	u8         status[0x8];
9225 	u8         reserved_at_8[0x18];
9226 
9227 	u8         syndrome[0x20];
9228 
9229 	u8         reserved_at_40[0x8];
9230 	u8         srqn[0x18];
9231 
9232 	u8         reserved_at_60[0x20];
9233 };
9234 
9235 struct mlx5_ifc_create_srq_in_bits {
9236 	u8         opcode[0x10];
9237 	u8         uid[0x10];
9238 
9239 	u8         reserved_at_20[0x10];
9240 	u8         op_mod[0x10];
9241 
9242 	u8         reserved_at_40[0x40];
9243 
9244 	struct mlx5_ifc_srqc_bits srq_context_entry;
9245 
9246 	u8         reserved_at_280[0x600];
9247 
9248 	u8         pas[][0x40];
9249 };
9250 
9251 struct mlx5_ifc_create_sq_out_bits {
9252 	u8         status[0x8];
9253 	u8         reserved_at_8[0x18];
9254 
9255 	u8         syndrome[0x20];
9256 
9257 	u8         reserved_at_40[0x8];
9258 	u8         sqn[0x18];
9259 
9260 	u8         reserved_at_60[0x20];
9261 };
9262 
9263 struct mlx5_ifc_create_sq_in_bits {
9264 	u8         opcode[0x10];
9265 	u8         uid[0x10];
9266 
9267 	u8         reserved_at_20[0x10];
9268 	u8         op_mod[0x10];
9269 
9270 	u8         reserved_at_40[0xc0];
9271 
9272 	struct mlx5_ifc_sqc_bits ctx;
9273 };
9274 
9275 struct mlx5_ifc_create_scheduling_element_out_bits {
9276 	u8         status[0x8];
9277 	u8         reserved_at_8[0x18];
9278 
9279 	u8         syndrome[0x20];
9280 
9281 	u8         reserved_at_40[0x40];
9282 
9283 	u8         scheduling_element_id[0x20];
9284 
9285 	u8         reserved_at_a0[0x160];
9286 };
9287 
9288 struct mlx5_ifc_create_scheduling_element_in_bits {
9289 	u8         opcode[0x10];
9290 	u8         reserved_at_10[0x10];
9291 
9292 	u8         reserved_at_20[0x10];
9293 	u8         op_mod[0x10];
9294 
9295 	u8         scheduling_hierarchy[0x8];
9296 	u8         reserved_at_48[0x18];
9297 
9298 	u8         reserved_at_60[0xa0];
9299 
9300 	struct mlx5_ifc_scheduling_context_bits scheduling_context;
9301 
9302 	u8         reserved_at_300[0x100];
9303 };
9304 
9305 struct mlx5_ifc_create_rqt_out_bits {
9306 	u8         status[0x8];
9307 	u8         reserved_at_8[0x18];
9308 
9309 	u8         syndrome[0x20];
9310 
9311 	u8         reserved_at_40[0x8];
9312 	u8         rqtn[0x18];
9313 
9314 	u8         reserved_at_60[0x20];
9315 };
9316 
9317 struct mlx5_ifc_create_rqt_in_bits {
9318 	u8         opcode[0x10];
9319 	u8         uid[0x10];
9320 
9321 	u8         reserved_at_20[0x10];
9322 	u8         op_mod[0x10];
9323 
9324 	u8         reserved_at_40[0xc0];
9325 
9326 	struct mlx5_ifc_rqtc_bits rqt_context;
9327 };
9328 
9329 struct mlx5_ifc_create_rq_out_bits {
9330 	u8         status[0x8];
9331 	u8         reserved_at_8[0x18];
9332 
9333 	u8         syndrome[0x20];
9334 
9335 	u8         reserved_at_40[0x8];
9336 	u8         rqn[0x18];
9337 
9338 	u8         reserved_at_60[0x20];
9339 };
9340 
9341 struct mlx5_ifc_create_rq_in_bits {
9342 	u8         opcode[0x10];
9343 	u8         uid[0x10];
9344 
9345 	u8         reserved_at_20[0x10];
9346 	u8         op_mod[0x10];
9347 
9348 	u8         reserved_at_40[0xc0];
9349 
9350 	struct mlx5_ifc_rqc_bits ctx;
9351 };
9352 
9353 struct mlx5_ifc_create_rmp_out_bits {
9354 	u8         status[0x8];
9355 	u8         reserved_at_8[0x18];
9356 
9357 	u8         syndrome[0x20];
9358 
9359 	u8         reserved_at_40[0x8];
9360 	u8         rmpn[0x18];
9361 
9362 	u8         reserved_at_60[0x20];
9363 };
9364 
9365 struct mlx5_ifc_create_rmp_in_bits {
9366 	u8         opcode[0x10];
9367 	u8         uid[0x10];
9368 
9369 	u8         reserved_at_20[0x10];
9370 	u8         op_mod[0x10];
9371 
9372 	u8         reserved_at_40[0xc0];
9373 
9374 	struct mlx5_ifc_rmpc_bits ctx;
9375 };
9376 
9377 struct mlx5_ifc_create_qp_out_bits {
9378 	u8         status[0x8];
9379 	u8         reserved_at_8[0x18];
9380 
9381 	u8         syndrome[0x20];
9382 
9383 	u8         reserved_at_40[0x8];
9384 	u8         qpn[0x18];
9385 
9386 	u8         ece[0x20];
9387 };
9388 
9389 struct mlx5_ifc_create_qp_in_bits {
9390 	u8         opcode[0x10];
9391 	u8         uid[0x10];
9392 
9393 	u8         reserved_at_20[0x10];
9394 	u8         op_mod[0x10];
9395 
9396 	u8         qpc_ext[0x1];
9397 	u8         reserved_at_41[0x7];
9398 	u8         input_qpn[0x18];
9399 
9400 	u8         reserved_at_60[0x20];
9401 	u8         opt_param_mask[0x20];
9402 
9403 	u8         ece[0x20];
9404 
9405 	struct mlx5_ifc_qpc_bits qpc;
9406 
9407 	u8         wq_umem_offset[0x40];
9408 
9409 	u8         wq_umem_id[0x20];
9410 
9411 	u8         wq_umem_valid[0x1];
9412 	u8         reserved_at_861[0x1f];
9413 
9414 	u8         pas[][0x40];
9415 };
9416 
9417 struct mlx5_ifc_create_psv_out_bits {
9418 	u8         status[0x8];
9419 	u8         reserved_at_8[0x18];
9420 
9421 	u8         syndrome[0x20];
9422 
9423 	u8         reserved_at_40[0x40];
9424 
9425 	u8         reserved_at_80[0x8];
9426 	u8         psv0_index[0x18];
9427 
9428 	u8         reserved_at_a0[0x8];
9429 	u8         psv1_index[0x18];
9430 
9431 	u8         reserved_at_c0[0x8];
9432 	u8         psv2_index[0x18];
9433 
9434 	u8         reserved_at_e0[0x8];
9435 	u8         psv3_index[0x18];
9436 };
9437 
9438 struct mlx5_ifc_create_psv_in_bits {
9439 	u8         opcode[0x10];
9440 	u8         reserved_at_10[0x10];
9441 
9442 	u8         reserved_at_20[0x10];
9443 	u8         op_mod[0x10];
9444 
9445 	u8         num_psv[0x4];
9446 	u8         reserved_at_44[0x4];
9447 	u8         pd[0x18];
9448 
9449 	u8         reserved_at_60[0x20];
9450 };
9451 
9452 struct mlx5_ifc_create_mkey_out_bits {
9453 	u8         status[0x8];
9454 	u8         reserved_at_8[0x18];
9455 
9456 	u8         syndrome[0x20];
9457 
9458 	u8         reserved_at_40[0x8];
9459 	u8         mkey_index[0x18];
9460 
9461 	u8         reserved_at_60[0x20];
9462 };
9463 
9464 struct mlx5_ifc_create_mkey_in_bits {
9465 	u8         opcode[0x10];
9466 	u8         uid[0x10];
9467 
9468 	u8         reserved_at_20[0x10];
9469 	u8         op_mod[0x10];
9470 
9471 	u8         reserved_at_40[0x20];
9472 
9473 	u8         pg_access[0x1];
9474 	u8         mkey_umem_valid[0x1];
9475 	u8         data_direct[0x1];
9476 	u8         reserved_at_63[0x1d];
9477 
9478 	struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
9479 
9480 	u8         reserved_at_280[0x80];
9481 
9482 	u8         translations_octword_actual_size[0x20];
9483 
9484 	u8         reserved_at_320[0x560];
9485 
9486 	u8         klm_pas_mtt[][0x20];
9487 };
9488 
9489 enum {
9490 	MLX5_FLOW_TABLE_TYPE_NIC_RX		= 0x0,
9491 	MLX5_FLOW_TABLE_TYPE_NIC_TX		= 0x1,
9492 	MLX5_FLOW_TABLE_TYPE_ESW_EGRESS_ACL	= 0x2,
9493 	MLX5_FLOW_TABLE_TYPE_ESW_INGRESS_ACL	= 0x3,
9494 	MLX5_FLOW_TABLE_TYPE_FDB		= 0X4,
9495 	MLX5_FLOW_TABLE_TYPE_SNIFFER_RX		= 0X5,
9496 	MLX5_FLOW_TABLE_TYPE_SNIFFER_TX		= 0X6,
9497 };
9498 
9499 struct mlx5_ifc_create_flow_table_out_bits {
9500 	u8         status[0x8];
9501 	u8         icm_address_63_40[0x18];
9502 
9503 	u8         syndrome[0x20];
9504 
9505 	u8         icm_address_39_32[0x8];
9506 	u8         table_id[0x18];
9507 
9508 	u8         icm_address_31_0[0x20];
9509 };
9510 
9511 struct mlx5_ifc_create_flow_table_in_bits {
9512 	u8         opcode[0x10];
9513 	u8         uid[0x10];
9514 
9515 	u8         reserved_at_20[0x10];
9516 	u8         op_mod[0x10];
9517 
9518 	u8         other_vport[0x1];
9519 	u8         reserved_at_41[0xf];
9520 	u8         vport_number[0x10];
9521 
9522 	u8         reserved_at_60[0x20];
9523 
9524 	u8         table_type[0x8];
9525 	u8         reserved_at_88[0x18];
9526 
9527 	u8         reserved_at_a0[0x20];
9528 
9529 	struct mlx5_ifc_flow_table_context_bits flow_table_context;
9530 };
9531 
9532 struct mlx5_ifc_create_flow_group_out_bits {
9533 	u8         status[0x8];
9534 	u8         reserved_at_8[0x18];
9535 
9536 	u8         syndrome[0x20];
9537 
9538 	u8         reserved_at_40[0x8];
9539 	u8         group_id[0x18];
9540 
9541 	u8         reserved_at_60[0x20];
9542 };
9543 
9544 enum {
9545 	MLX5_CREATE_FLOW_GROUP_IN_GROUP_TYPE_TCAM_SUBTABLE  = 0x0,
9546 	MLX5_CREATE_FLOW_GROUP_IN_GROUP_TYPE_HASH_SPLIT     = 0x1,
9547 };
9548 
9549 enum {
9550 	MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS     = 0x0,
9551 	MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS   = 0x1,
9552 	MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS     = 0x2,
9553 	MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3,
9554 };
9555 
9556 struct mlx5_ifc_create_flow_group_in_bits {
9557 	u8         opcode[0x10];
9558 	u8         reserved_at_10[0x10];
9559 
9560 	u8         reserved_at_20[0x10];
9561 	u8         op_mod[0x10];
9562 
9563 	u8         other_vport[0x1];
9564 	u8         reserved_at_41[0xf];
9565 	u8         vport_number[0x10];
9566 
9567 	u8         reserved_at_60[0x20];
9568 
9569 	u8         table_type[0x8];
9570 	u8         reserved_at_88[0x4];
9571 	u8         group_type[0x4];
9572 	u8         reserved_at_90[0x10];
9573 
9574 	u8         reserved_at_a0[0x8];
9575 	u8         table_id[0x18];
9576 
9577 	u8         source_eswitch_owner_vhca_id_valid[0x1];
9578 
9579 	u8         reserved_at_c1[0x1f];
9580 
9581 	u8         start_flow_index[0x20];
9582 
9583 	u8         reserved_at_100[0x20];
9584 
9585 	u8         end_flow_index[0x20];
9586 
9587 	u8         reserved_at_140[0x10];
9588 	u8         match_definer_id[0x10];
9589 
9590 	u8         reserved_at_160[0x80];
9591 
9592 	u8         reserved_at_1e0[0x18];
9593 	u8         match_criteria_enable[0x8];
9594 
9595 	struct mlx5_ifc_fte_match_param_bits match_criteria;
9596 
9597 	u8         reserved_at_1200[0xe00];
9598 };
9599 
9600 struct mlx5_ifc_create_eq_out_bits {
9601 	u8         status[0x8];
9602 	u8         reserved_at_8[0x18];
9603 
9604 	u8         syndrome[0x20];
9605 
9606 	u8         reserved_at_40[0x18];
9607 	u8         eq_number[0x8];
9608 
9609 	u8         reserved_at_60[0x20];
9610 };
9611 
9612 struct mlx5_ifc_create_eq_in_bits {
9613 	u8         opcode[0x10];
9614 	u8         uid[0x10];
9615 
9616 	u8         reserved_at_20[0x10];
9617 	u8         op_mod[0x10];
9618 
9619 	u8         reserved_at_40[0x40];
9620 
9621 	struct mlx5_ifc_eqc_bits eq_context_entry;
9622 
9623 	u8         reserved_at_280[0x40];
9624 
9625 	u8         event_bitmask[4][0x40];
9626 
9627 	u8         reserved_at_3c0[0x4c0];
9628 
9629 	u8         pas[][0x40];
9630 };
9631 
9632 struct mlx5_ifc_create_dct_out_bits {
9633 	u8         status[0x8];
9634 	u8         reserved_at_8[0x18];
9635 
9636 	u8         syndrome[0x20];
9637 
9638 	u8         reserved_at_40[0x8];
9639 	u8         dctn[0x18];
9640 
9641 	u8         ece[0x20];
9642 };
9643 
9644 struct mlx5_ifc_create_dct_in_bits {
9645 	u8         opcode[0x10];
9646 	u8         uid[0x10];
9647 
9648 	u8         reserved_at_20[0x10];
9649 	u8         op_mod[0x10];
9650 
9651 	u8         reserved_at_40[0x40];
9652 
9653 	struct mlx5_ifc_dctc_bits dct_context_entry;
9654 
9655 	u8         reserved_at_280[0x180];
9656 };
9657 
9658 struct mlx5_ifc_create_cq_out_bits {
9659 	u8         status[0x8];
9660 	u8         reserved_at_8[0x18];
9661 
9662 	u8         syndrome[0x20];
9663 
9664 	u8         reserved_at_40[0x8];
9665 	u8         cqn[0x18];
9666 
9667 	u8         reserved_at_60[0x20];
9668 };
9669 
9670 struct mlx5_ifc_create_cq_in_bits {
9671 	u8         opcode[0x10];
9672 	u8         uid[0x10];
9673 
9674 	u8         reserved_at_20[0x10];
9675 	u8         op_mod[0x10];
9676 
9677 	u8         reserved_at_40[0x40];
9678 
9679 	struct mlx5_ifc_cqc_bits cq_context;
9680 
9681 	u8         reserved_at_280[0x60];
9682 
9683 	u8         cq_umem_valid[0x1];
9684 	u8         reserved_at_2e1[0x59f];
9685 
9686 	u8         pas[][0x40];
9687 };
9688 
9689 struct mlx5_ifc_config_int_moderation_out_bits {
9690 	u8         status[0x8];
9691 	u8         reserved_at_8[0x18];
9692 
9693 	u8         syndrome[0x20];
9694 
9695 	u8         reserved_at_40[0x4];
9696 	u8         min_delay[0xc];
9697 	u8         int_vector[0x10];
9698 
9699 	u8         reserved_at_60[0x20];
9700 };
9701 
9702 enum {
9703 	MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE  = 0x0,
9704 	MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ   = 0x1,
9705 };
9706 
9707 struct mlx5_ifc_config_int_moderation_in_bits {
9708 	u8         opcode[0x10];
9709 	u8         reserved_at_10[0x10];
9710 
9711 	u8         reserved_at_20[0x10];
9712 	u8         op_mod[0x10];
9713 
9714 	u8         reserved_at_40[0x4];
9715 	u8         min_delay[0xc];
9716 	u8         int_vector[0x10];
9717 
9718 	u8         reserved_at_60[0x20];
9719 };
9720 
9721 struct mlx5_ifc_attach_to_mcg_out_bits {
9722 	u8         status[0x8];
9723 	u8         reserved_at_8[0x18];
9724 
9725 	u8         syndrome[0x20];
9726 
9727 	u8         reserved_at_40[0x40];
9728 };
9729 
9730 struct mlx5_ifc_attach_to_mcg_in_bits {
9731 	u8         opcode[0x10];
9732 	u8         uid[0x10];
9733 
9734 	u8         reserved_at_20[0x10];
9735 	u8         op_mod[0x10];
9736 
9737 	u8         reserved_at_40[0x8];
9738 	u8         qpn[0x18];
9739 
9740 	u8         reserved_at_60[0x20];
9741 
9742 	u8         multicast_gid[16][0x8];
9743 };
9744 
9745 struct mlx5_ifc_arm_xrq_out_bits {
9746 	u8         status[0x8];
9747 	u8         reserved_at_8[0x18];
9748 
9749 	u8         syndrome[0x20];
9750 
9751 	u8         reserved_at_40[0x40];
9752 };
9753 
9754 struct mlx5_ifc_arm_xrq_in_bits {
9755 	u8         opcode[0x10];
9756 	u8         reserved_at_10[0x10];
9757 
9758 	u8         reserved_at_20[0x10];
9759 	u8         op_mod[0x10];
9760 
9761 	u8         reserved_at_40[0x8];
9762 	u8         xrqn[0x18];
9763 
9764 	u8         reserved_at_60[0x10];
9765 	u8         lwm[0x10];
9766 };
9767 
9768 struct mlx5_ifc_arm_xrc_srq_out_bits {
9769 	u8         status[0x8];
9770 	u8         reserved_at_8[0x18];
9771 
9772 	u8         syndrome[0x20];
9773 
9774 	u8         reserved_at_40[0x40];
9775 };
9776 
9777 enum {
9778 	MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ  = 0x1,
9779 };
9780 
9781 struct mlx5_ifc_arm_xrc_srq_in_bits {
9782 	u8         opcode[0x10];
9783 	u8         uid[0x10];
9784 
9785 	u8         reserved_at_20[0x10];
9786 	u8         op_mod[0x10];
9787 
9788 	u8         reserved_at_40[0x8];
9789 	u8         xrc_srqn[0x18];
9790 
9791 	u8         reserved_at_60[0x10];
9792 	u8         lwm[0x10];
9793 };
9794 
9795 struct mlx5_ifc_arm_rq_out_bits {
9796 	u8         status[0x8];
9797 	u8         reserved_at_8[0x18];
9798 
9799 	u8         syndrome[0x20];
9800 
9801 	u8         reserved_at_40[0x40];
9802 };
9803 
9804 enum {
9805 	MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1,
9806 	MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2,
9807 };
9808 
9809 struct mlx5_ifc_arm_rq_in_bits {
9810 	u8         opcode[0x10];
9811 	u8         uid[0x10];
9812 
9813 	u8         reserved_at_20[0x10];
9814 	u8         op_mod[0x10];
9815 
9816 	u8         reserved_at_40[0x8];
9817 	u8         srq_number[0x18];
9818 
9819 	u8         reserved_at_60[0x10];
9820 	u8         lwm[0x10];
9821 };
9822 
9823 struct mlx5_ifc_arm_dct_out_bits {
9824 	u8         status[0x8];
9825 	u8         reserved_at_8[0x18];
9826 
9827 	u8         syndrome[0x20];
9828 
9829 	u8         reserved_at_40[0x40];
9830 };
9831 
9832 struct mlx5_ifc_arm_dct_in_bits {
9833 	u8         opcode[0x10];
9834 	u8         reserved_at_10[0x10];
9835 
9836 	u8         reserved_at_20[0x10];
9837 	u8         op_mod[0x10];
9838 
9839 	u8         reserved_at_40[0x8];
9840 	u8         dct_number[0x18];
9841 
9842 	u8         reserved_at_60[0x20];
9843 };
9844 
9845 struct mlx5_ifc_alloc_xrcd_out_bits {
9846 	u8         status[0x8];
9847 	u8         reserved_at_8[0x18];
9848 
9849 	u8         syndrome[0x20];
9850 
9851 	u8         reserved_at_40[0x8];
9852 	u8         xrcd[0x18];
9853 
9854 	u8         reserved_at_60[0x20];
9855 };
9856 
9857 struct mlx5_ifc_alloc_xrcd_in_bits {
9858 	u8         opcode[0x10];
9859 	u8         uid[0x10];
9860 
9861 	u8         reserved_at_20[0x10];
9862 	u8         op_mod[0x10];
9863 
9864 	u8         reserved_at_40[0x40];
9865 };
9866 
9867 struct mlx5_ifc_alloc_uar_out_bits {
9868 	u8         status[0x8];
9869 	u8         reserved_at_8[0x18];
9870 
9871 	u8         syndrome[0x20];
9872 
9873 	u8         reserved_at_40[0x8];
9874 	u8         uar[0x18];
9875 
9876 	u8         reserved_at_60[0x20];
9877 };
9878 
9879 struct mlx5_ifc_alloc_uar_in_bits {
9880 	u8         opcode[0x10];
9881 	u8         uid[0x10];
9882 
9883 	u8         reserved_at_20[0x10];
9884 	u8         op_mod[0x10];
9885 
9886 	u8         reserved_at_40[0x40];
9887 };
9888 
9889 struct mlx5_ifc_alloc_transport_domain_out_bits {
9890 	u8         status[0x8];
9891 	u8         reserved_at_8[0x18];
9892 
9893 	u8         syndrome[0x20];
9894 
9895 	u8         reserved_at_40[0x8];
9896 	u8         transport_domain[0x18];
9897 
9898 	u8         reserved_at_60[0x20];
9899 };
9900 
9901 struct mlx5_ifc_alloc_transport_domain_in_bits {
9902 	u8         opcode[0x10];
9903 	u8         uid[0x10];
9904 
9905 	u8         reserved_at_20[0x10];
9906 	u8         op_mod[0x10];
9907 
9908 	u8         reserved_at_40[0x40];
9909 };
9910 
9911 struct mlx5_ifc_alloc_q_counter_out_bits {
9912 	u8         status[0x8];
9913 	u8         reserved_at_8[0x18];
9914 
9915 	u8         syndrome[0x20];
9916 
9917 	u8         reserved_at_40[0x18];
9918 	u8         counter_set_id[0x8];
9919 
9920 	u8         reserved_at_60[0x20];
9921 };
9922 
9923 struct mlx5_ifc_alloc_q_counter_in_bits {
9924 	u8         opcode[0x10];
9925 	u8         uid[0x10];
9926 
9927 	u8         reserved_at_20[0x10];
9928 	u8         op_mod[0x10];
9929 
9930 	u8         reserved_at_40[0x40];
9931 };
9932 
9933 struct mlx5_ifc_alloc_pd_out_bits {
9934 	u8         status[0x8];
9935 	u8         reserved_at_8[0x18];
9936 
9937 	u8         syndrome[0x20];
9938 
9939 	u8         reserved_at_40[0x8];
9940 	u8         pd[0x18];
9941 
9942 	u8         reserved_at_60[0x20];
9943 };
9944 
9945 struct mlx5_ifc_alloc_pd_in_bits {
9946 	u8         opcode[0x10];
9947 	u8         uid[0x10];
9948 
9949 	u8         reserved_at_20[0x10];
9950 	u8         op_mod[0x10];
9951 
9952 	u8         reserved_at_40[0x40];
9953 };
9954 
9955 struct mlx5_ifc_alloc_flow_counter_out_bits {
9956 	u8         status[0x8];
9957 	u8         reserved_at_8[0x18];
9958 
9959 	u8         syndrome[0x20];
9960 
9961 	u8         flow_counter_id[0x20];
9962 
9963 	u8         reserved_at_60[0x20];
9964 };
9965 
9966 struct mlx5_ifc_alloc_flow_counter_in_bits {
9967 	u8         opcode[0x10];
9968 	u8         reserved_at_10[0x10];
9969 
9970 	u8         reserved_at_20[0x10];
9971 	u8         op_mod[0x10];
9972 
9973 	u8         reserved_at_40[0x33];
9974 	u8         flow_counter_bulk_log_size[0x5];
9975 	u8         flow_counter_bulk[0x8];
9976 };
9977 
9978 struct mlx5_ifc_add_vxlan_udp_dport_out_bits {
9979 	u8         status[0x8];
9980 	u8         reserved_at_8[0x18];
9981 
9982 	u8         syndrome[0x20];
9983 
9984 	u8         reserved_at_40[0x40];
9985 };
9986 
9987 struct mlx5_ifc_add_vxlan_udp_dport_in_bits {
9988 	u8         opcode[0x10];
9989 	u8         reserved_at_10[0x10];
9990 
9991 	u8         reserved_at_20[0x10];
9992 	u8         op_mod[0x10];
9993 
9994 	u8         reserved_at_40[0x20];
9995 
9996 	u8         reserved_at_60[0x10];
9997 	u8         vxlan_udp_port[0x10];
9998 };
9999 
10000 struct mlx5_ifc_set_pp_rate_limit_out_bits {
10001 	u8         status[0x8];
10002 	u8         reserved_at_8[0x18];
10003 
10004 	u8         syndrome[0x20];
10005 
10006 	u8         reserved_at_40[0x40];
10007 };
10008 
10009 struct mlx5_ifc_set_pp_rate_limit_context_bits {
10010 	u8         rate_limit[0x20];
10011 
10012 	u8	   burst_upper_bound[0x20];
10013 
10014 	u8         reserved_at_40[0x10];
10015 	u8	   typical_packet_size[0x10];
10016 
10017 	u8         reserved_at_60[0x120];
10018 };
10019 
10020 struct mlx5_ifc_set_pp_rate_limit_in_bits {
10021 	u8         opcode[0x10];
10022 	u8         uid[0x10];
10023 
10024 	u8         reserved_at_20[0x10];
10025 	u8         op_mod[0x10];
10026 
10027 	u8         reserved_at_40[0x10];
10028 	u8         rate_limit_index[0x10];
10029 
10030 	u8         reserved_at_60[0x20];
10031 
10032 	struct mlx5_ifc_set_pp_rate_limit_context_bits ctx;
10033 };
10034 
10035 struct mlx5_ifc_access_register_out_bits {
10036 	u8         status[0x8];
10037 	u8         reserved_at_8[0x18];
10038 
10039 	u8         syndrome[0x20];
10040 
10041 	u8         reserved_at_40[0x40];
10042 
10043 	u8         register_data[][0x20];
10044 };
10045 
10046 enum {
10047 	MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE  = 0x0,
10048 	MLX5_ACCESS_REGISTER_IN_OP_MOD_READ   = 0x1,
10049 };
10050 
10051 struct mlx5_ifc_access_register_in_bits {
10052 	u8         opcode[0x10];
10053 	u8         reserved_at_10[0x10];
10054 
10055 	u8         reserved_at_20[0x10];
10056 	u8         op_mod[0x10];
10057 
10058 	u8         reserved_at_40[0x10];
10059 	u8         register_id[0x10];
10060 
10061 	u8         argument[0x20];
10062 
10063 	u8         register_data[][0x20];
10064 };
10065 
10066 struct mlx5_ifc_sltp_reg_bits {
10067 	u8         status[0x4];
10068 	u8         version[0x4];
10069 	u8         local_port[0x8];
10070 	u8         pnat[0x2];
10071 	u8         reserved_at_12[0x2];
10072 	u8         lane[0x4];
10073 	u8         reserved_at_18[0x8];
10074 
10075 	u8         reserved_at_20[0x20];
10076 
10077 	u8         reserved_at_40[0x7];
10078 	u8         polarity[0x1];
10079 	u8         ob_tap0[0x8];
10080 	u8         ob_tap1[0x8];
10081 	u8         ob_tap2[0x8];
10082 
10083 	u8         reserved_at_60[0xc];
10084 	u8         ob_preemp_mode[0x4];
10085 	u8         ob_reg[0x8];
10086 	u8         ob_bias[0x8];
10087 
10088 	u8         reserved_at_80[0x20];
10089 };
10090 
10091 struct mlx5_ifc_slrg_reg_bits {
10092 	u8         status[0x4];
10093 	u8         version[0x4];
10094 	u8         local_port[0x8];
10095 	u8         pnat[0x2];
10096 	u8         reserved_at_12[0x2];
10097 	u8         lane[0x4];
10098 	u8         reserved_at_18[0x8];
10099 
10100 	u8         time_to_link_up[0x10];
10101 	u8         reserved_at_30[0xc];
10102 	u8         grade_lane_speed[0x4];
10103 
10104 	u8         grade_version[0x8];
10105 	u8         grade[0x18];
10106 
10107 	u8         reserved_at_60[0x4];
10108 	u8         height_grade_type[0x4];
10109 	u8         height_grade[0x18];
10110 
10111 	u8         height_dz[0x10];
10112 	u8         height_dv[0x10];
10113 
10114 	u8         reserved_at_a0[0x10];
10115 	u8         height_sigma[0x10];
10116 
10117 	u8         reserved_at_c0[0x20];
10118 
10119 	u8         reserved_at_e0[0x4];
10120 	u8         phase_grade_type[0x4];
10121 	u8         phase_grade[0x18];
10122 
10123 	u8         reserved_at_100[0x8];
10124 	u8         phase_eo_pos[0x8];
10125 	u8         reserved_at_110[0x8];
10126 	u8         phase_eo_neg[0x8];
10127 
10128 	u8         ffe_set_tested[0x10];
10129 	u8         test_errors_per_lane[0x10];
10130 };
10131 
10132 struct mlx5_ifc_pvlc_reg_bits {
10133 	u8         reserved_at_0[0x8];
10134 	u8         local_port[0x8];
10135 	u8         reserved_at_10[0x10];
10136 
10137 	u8         reserved_at_20[0x1c];
10138 	u8         vl_hw_cap[0x4];
10139 
10140 	u8         reserved_at_40[0x1c];
10141 	u8         vl_admin[0x4];
10142 
10143 	u8         reserved_at_60[0x1c];
10144 	u8         vl_operational[0x4];
10145 };
10146 
10147 struct mlx5_ifc_pude_reg_bits {
10148 	u8         swid[0x8];
10149 	u8         local_port[0x8];
10150 	u8         reserved_at_10[0x4];
10151 	u8         admin_status[0x4];
10152 	u8         reserved_at_18[0x4];
10153 	u8         oper_status[0x4];
10154 
10155 	u8         reserved_at_20[0x60];
10156 };
10157 
10158 enum {
10159 	MLX5_PTYS_CONNECTOR_TYPE_PORT_DA = 0x7,
10160 };
10161 
10162 struct mlx5_ifc_ptys_reg_bits {
10163 	u8         reserved_at_0[0x1];
10164 	u8         an_disable_admin[0x1];
10165 	u8         an_disable_cap[0x1];
10166 	u8         reserved_at_3[0x5];
10167 	u8         local_port[0x8];
10168 	u8         reserved_at_10[0x8];
10169 	u8         plane_ind[0x4];
10170 	u8         reserved_at_1c[0x1];
10171 	u8         proto_mask[0x3];
10172 
10173 	u8         an_status[0x4];
10174 	u8         reserved_at_24[0xc];
10175 	u8         data_rate_oper[0x10];
10176 
10177 	u8         ext_eth_proto_capability[0x20];
10178 
10179 	u8         eth_proto_capability[0x20];
10180 
10181 	u8         ib_link_width_capability[0x10];
10182 	u8         ib_proto_capability[0x10];
10183 
10184 	u8         ext_eth_proto_admin[0x20];
10185 
10186 	u8         eth_proto_admin[0x20];
10187 
10188 	u8         ib_link_width_admin[0x10];
10189 	u8         ib_proto_admin[0x10];
10190 
10191 	u8         ext_eth_proto_oper[0x20];
10192 
10193 	u8         eth_proto_oper[0x20];
10194 
10195 	u8         ib_link_width_oper[0x10];
10196 	u8         ib_proto_oper[0x10];
10197 
10198 	u8         reserved_at_160[0x8];
10199 	u8         lane_rate_oper[0x14];
10200 	u8         connector_type[0x4];
10201 
10202 	u8         eth_proto_lp_advertise[0x20];
10203 
10204 	u8         reserved_at_1a0[0x60];
10205 };
10206 
10207 struct mlx5_ifc_mlcr_reg_bits {
10208 	u8         reserved_at_0[0x8];
10209 	u8         local_port[0x8];
10210 	u8         reserved_at_10[0x20];
10211 
10212 	u8         beacon_duration[0x10];
10213 	u8         reserved_at_40[0x10];
10214 
10215 	u8         beacon_remain[0x10];
10216 };
10217 
10218 struct mlx5_ifc_ptas_reg_bits {
10219 	u8         reserved_at_0[0x20];
10220 
10221 	u8         algorithm_options[0x10];
10222 	u8         reserved_at_30[0x4];
10223 	u8         repetitions_mode[0x4];
10224 	u8         num_of_repetitions[0x8];
10225 
10226 	u8         grade_version[0x8];
10227 	u8         height_grade_type[0x4];
10228 	u8         phase_grade_type[0x4];
10229 	u8         height_grade_weight[0x8];
10230 	u8         phase_grade_weight[0x8];
10231 
10232 	u8         gisim_measure_bits[0x10];
10233 	u8         adaptive_tap_measure_bits[0x10];
10234 
10235 	u8         ber_bath_high_error_threshold[0x10];
10236 	u8         ber_bath_mid_error_threshold[0x10];
10237 
10238 	u8         ber_bath_low_error_threshold[0x10];
10239 	u8         one_ratio_high_threshold[0x10];
10240 
10241 	u8         one_ratio_high_mid_threshold[0x10];
10242 	u8         one_ratio_low_mid_threshold[0x10];
10243 
10244 	u8         one_ratio_low_threshold[0x10];
10245 	u8         ndeo_error_threshold[0x10];
10246 
10247 	u8         mixer_offset_step_size[0x10];
10248 	u8         reserved_at_110[0x8];
10249 	u8         mix90_phase_for_voltage_bath[0x8];
10250 
10251 	u8         mixer_offset_start[0x10];
10252 	u8         mixer_offset_end[0x10];
10253 
10254 	u8         reserved_at_140[0x15];
10255 	u8         ber_test_time[0xb];
10256 };
10257 
10258 struct mlx5_ifc_pspa_reg_bits {
10259 	u8         swid[0x8];
10260 	u8         local_port[0x8];
10261 	u8         sub_port[0x8];
10262 	u8         reserved_at_18[0x8];
10263 
10264 	u8         reserved_at_20[0x20];
10265 };
10266 
10267 struct mlx5_ifc_pqdr_reg_bits {
10268 	u8         reserved_at_0[0x8];
10269 	u8         local_port[0x8];
10270 	u8         reserved_at_10[0x5];
10271 	u8         prio[0x3];
10272 	u8         reserved_at_18[0x6];
10273 	u8         mode[0x2];
10274 
10275 	u8         reserved_at_20[0x20];
10276 
10277 	u8         reserved_at_40[0x10];
10278 	u8         min_threshold[0x10];
10279 
10280 	u8         reserved_at_60[0x10];
10281 	u8         max_threshold[0x10];
10282 
10283 	u8         reserved_at_80[0x10];
10284 	u8         mark_probability_denominator[0x10];
10285 
10286 	u8         reserved_at_a0[0x60];
10287 };
10288 
10289 struct mlx5_ifc_ppsc_reg_bits {
10290 	u8         reserved_at_0[0x8];
10291 	u8         local_port[0x8];
10292 	u8         reserved_at_10[0x10];
10293 
10294 	u8         reserved_at_20[0x60];
10295 
10296 	u8         reserved_at_80[0x1c];
10297 	u8         wrps_admin[0x4];
10298 
10299 	u8         reserved_at_a0[0x1c];
10300 	u8         wrps_status[0x4];
10301 
10302 	u8         reserved_at_c0[0x8];
10303 	u8         up_threshold[0x8];
10304 	u8         reserved_at_d0[0x8];
10305 	u8         down_threshold[0x8];
10306 
10307 	u8         reserved_at_e0[0x20];
10308 
10309 	u8         reserved_at_100[0x1c];
10310 	u8         srps_admin[0x4];
10311 
10312 	u8         reserved_at_120[0x1c];
10313 	u8         srps_status[0x4];
10314 
10315 	u8         reserved_at_140[0x40];
10316 };
10317 
10318 struct mlx5_ifc_pplr_reg_bits {
10319 	u8         reserved_at_0[0x8];
10320 	u8         local_port[0x8];
10321 	u8         reserved_at_10[0x10];
10322 
10323 	u8         reserved_at_20[0x8];
10324 	u8         lb_cap[0x8];
10325 	u8         reserved_at_30[0x8];
10326 	u8         lb_en[0x8];
10327 };
10328 
10329 struct mlx5_ifc_pplm_reg_bits {
10330 	u8         reserved_at_0[0x8];
10331 	u8	   local_port[0x8];
10332 	u8	   reserved_at_10[0x10];
10333 
10334 	u8	   reserved_at_20[0x20];
10335 
10336 	u8	   port_profile_mode[0x8];
10337 	u8	   static_port_profile[0x8];
10338 	u8	   active_port_profile[0x8];
10339 	u8	   reserved_at_58[0x8];
10340 
10341 	u8	   retransmission_active[0x8];
10342 	u8	   fec_mode_active[0x18];
10343 
10344 	u8	   rs_fec_correction_bypass_cap[0x4];
10345 	u8	   reserved_at_84[0x8];
10346 	u8	   fec_override_cap_56g[0x4];
10347 	u8	   fec_override_cap_100g[0x4];
10348 	u8	   fec_override_cap_50g[0x4];
10349 	u8	   fec_override_cap_25g[0x4];
10350 	u8	   fec_override_cap_10g_40g[0x4];
10351 
10352 	u8	   rs_fec_correction_bypass_admin[0x4];
10353 	u8	   reserved_at_a4[0x8];
10354 	u8	   fec_override_admin_56g[0x4];
10355 	u8	   fec_override_admin_100g[0x4];
10356 	u8	   fec_override_admin_50g[0x4];
10357 	u8	   fec_override_admin_25g[0x4];
10358 	u8	   fec_override_admin_10g_40g[0x4];
10359 
10360 	u8         fec_override_cap_400g_8x[0x10];
10361 	u8         fec_override_cap_200g_4x[0x10];
10362 
10363 	u8         fec_override_cap_100g_2x[0x10];
10364 	u8         fec_override_cap_50g_1x[0x10];
10365 
10366 	u8         fec_override_admin_400g_8x[0x10];
10367 	u8         fec_override_admin_200g_4x[0x10];
10368 
10369 	u8         fec_override_admin_100g_2x[0x10];
10370 	u8         fec_override_admin_50g_1x[0x10];
10371 
10372 	u8         fec_override_cap_800g_8x[0x10];
10373 	u8         fec_override_cap_400g_4x[0x10];
10374 
10375 	u8         fec_override_cap_200g_2x[0x10];
10376 	u8         fec_override_cap_100g_1x[0x10];
10377 
10378 	u8         reserved_at_180[0xa0];
10379 
10380 	u8         fec_override_admin_800g_8x[0x10];
10381 	u8         fec_override_admin_400g_4x[0x10];
10382 
10383 	u8         fec_override_admin_200g_2x[0x10];
10384 	u8         fec_override_admin_100g_1x[0x10];
10385 
10386 	u8         reserved_at_260[0x60];
10387 
10388 	u8         fec_override_cap_1600g_8x[0x10];
10389 	u8         fec_override_cap_800g_4x[0x10];
10390 
10391 	u8         fec_override_cap_400g_2x[0x10];
10392 	u8         fec_override_cap_200g_1x[0x10];
10393 
10394 	u8         fec_override_admin_1600g_8x[0x10];
10395 	u8         fec_override_admin_800g_4x[0x10];
10396 
10397 	u8         fec_override_admin_400g_2x[0x10];
10398 	u8         fec_override_admin_200g_1x[0x10];
10399 
10400 	u8         reserved_at_340[0x80];
10401 };
10402 
10403 struct mlx5_ifc_ppcnt_reg_bits {
10404 	u8         swid[0x8];
10405 	u8         local_port[0x8];
10406 	u8         pnat[0x2];
10407 	u8         reserved_at_12[0x8];
10408 	u8         grp[0x6];
10409 
10410 	u8         clr[0x1];
10411 	u8         reserved_at_21[0x13];
10412 	u8         plane_ind[0x4];
10413 	u8         reserved_at_38[0x3];
10414 	u8         prio_tc[0x5];
10415 
10416 	union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set;
10417 };
10418 
10419 struct mlx5_ifc_mpein_reg_bits {
10420 	u8         reserved_at_0[0x2];
10421 	u8         depth[0x6];
10422 	u8         pcie_index[0x8];
10423 	u8         node[0x8];
10424 	u8         reserved_at_18[0x8];
10425 
10426 	u8         capability_mask[0x20];
10427 
10428 	u8         reserved_at_40[0x8];
10429 	u8         link_width_enabled[0x8];
10430 	u8         link_speed_enabled[0x10];
10431 
10432 	u8         lane0_physical_position[0x8];
10433 	u8         link_width_active[0x8];
10434 	u8         link_speed_active[0x10];
10435 
10436 	u8         num_of_pfs[0x10];
10437 	u8         num_of_vfs[0x10];
10438 
10439 	u8         bdf0[0x10];
10440 	u8         reserved_at_b0[0x10];
10441 
10442 	u8         max_read_request_size[0x4];
10443 	u8         max_payload_size[0x4];
10444 	u8         reserved_at_c8[0x5];
10445 	u8         pwr_status[0x3];
10446 	u8         port_type[0x4];
10447 	u8         reserved_at_d4[0xb];
10448 	u8         lane_reversal[0x1];
10449 
10450 	u8         reserved_at_e0[0x14];
10451 	u8         pci_power[0xc];
10452 
10453 	u8         reserved_at_100[0x20];
10454 
10455 	u8         device_status[0x10];
10456 	u8         port_state[0x8];
10457 	u8         reserved_at_138[0x8];
10458 
10459 	u8         reserved_at_140[0x10];
10460 	u8         receiver_detect_result[0x10];
10461 
10462 	u8         reserved_at_160[0x20];
10463 };
10464 
10465 struct mlx5_ifc_mpcnt_reg_bits {
10466 	u8         reserved_at_0[0x8];
10467 	u8         pcie_index[0x8];
10468 	u8         reserved_at_10[0xa];
10469 	u8         grp[0x6];
10470 
10471 	u8         clr[0x1];
10472 	u8         reserved_at_21[0x1f];
10473 
10474 	union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set;
10475 };
10476 
10477 struct mlx5_ifc_ppad_reg_bits {
10478 	u8         reserved_at_0[0x3];
10479 	u8         single_mac[0x1];
10480 	u8         reserved_at_4[0x4];
10481 	u8         local_port[0x8];
10482 	u8         mac_47_32[0x10];
10483 
10484 	u8         mac_31_0[0x20];
10485 
10486 	u8         reserved_at_40[0x40];
10487 };
10488 
10489 struct mlx5_ifc_pmtu_reg_bits {
10490 	u8         reserved_at_0[0x8];
10491 	u8         local_port[0x8];
10492 	u8         reserved_at_10[0x10];
10493 
10494 	u8         max_mtu[0x10];
10495 	u8         reserved_at_30[0x10];
10496 
10497 	u8         admin_mtu[0x10];
10498 	u8         reserved_at_50[0x10];
10499 
10500 	u8         oper_mtu[0x10];
10501 	u8         reserved_at_70[0x10];
10502 };
10503 
10504 struct mlx5_ifc_pmpr_reg_bits {
10505 	u8         reserved_at_0[0x8];
10506 	u8         module[0x8];
10507 	u8         reserved_at_10[0x10];
10508 
10509 	u8         reserved_at_20[0x18];
10510 	u8         attenuation_5g[0x8];
10511 
10512 	u8         reserved_at_40[0x18];
10513 	u8         attenuation_7g[0x8];
10514 
10515 	u8         reserved_at_60[0x18];
10516 	u8         attenuation_12g[0x8];
10517 };
10518 
10519 struct mlx5_ifc_pmpe_reg_bits {
10520 	u8         reserved_at_0[0x8];
10521 	u8         module[0x8];
10522 	u8         reserved_at_10[0xc];
10523 	u8         module_status[0x4];
10524 
10525 	u8         reserved_at_20[0x60];
10526 };
10527 
10528 struct mlx5_ifc_pmpc_reg_bits {
10529 	u8         module_state_updated[32][0x8];
10530 };
10531 
10532 struct mlx5_ifc_pmlpn_reg_bits {
10533 	u8         reserved_at_0[0x4];
10534 	u8         mlpn_status[0x4];
10535 	u8         local_port[0x8];
10536 	u8         reserved_at_10[0x10];
10537 
10538 	u8         e[0x1];
10539 	u8         reserved_at_21[0x1f];
10540 };
10541 
10542 struct mlx5_ifc_pmlp_reg_bits {
10543 	u8         rxtx[0x1];
10544 	u8         reserved_at_1[0x7];
10545 	u8         local_port[0x8];
10546 	u8         reserved_at_10[0x8];
10547 	u8         width[0x8];
10548 
10549 	u8         lane0_module_mapping[0x20];
10550 
10551 	u8         lane1_module_mapping[0x20];
10552 
10553 	u8         lane2_module_mapping[0x20];
10554 
10555 	u8         lane3_module_mapping[0x20];
10556 
10557 	u8         reserved_at_a0[0x160];
10558 };
10559 
10560 struct mlx5_ifc_pmaos_reg_bits {
10561 	u8         reserved_at_0[0x8];
10562 	u8         module[0x8];
10563 	u8         reserved_at_10[0x4];
10564 	u8         admin_status[0x4];
10565 	u8         reserved_at_18[0x4];
10566 	u8         oper_status[0x4];
10567 
10568 	u8         ase[0x1];
10569 	u8         ee[0x1];
10570 	u8         reserved_at_22[0x1c];
10571 	u8         e[0x2];
10572 
10573 	u8         reserved_at_40[0x40];
10574 };
10575 
10576 struct mlx5_ifc_plpc_reg_bits {
10577 	u8         reserved_at_0[0x4];
10578 	u8         profile_id[0xc];
10579 	u8         reserved_at_10[0x4];
10580 	u8         proto_mask[0x4];
10581 	u8         reserved_at_18[0x8];
10582 
10583 	u8         reserved_at_20[0x10];
10584 	u8         lane_speed[0x10];
10585 
10586 	u8         reserved_at_40[0x17];
10587 	u8         lpbf[0x1];
10588 	u8         fec_mode_policy[0x8];
10589 
10590 	u8         retransmission_capability[0x8];
10591 	u8         fec_mode_capability[0x18];
10592 
10593 	u8         retransmission_support_admin[0x8];
10594 	u8         fec_mode_support_admin[0x18];
10595 
10596 	u8         retransmission_request_admin[0x8];
10597 	u8         fec_mode_request_admin[0x18];
10598 
10599 	u8         reserved_at_c0[0x80];
10600 };
10601 
10602 struct mlx5_ifc_plib_reg_bits {
10603 	u8         reserved_at_0[0x8];
10604 	u8         local_port[0x8];
10605 	u8         reserved_at_10[0x8];
10606 	u8         ib_port[0x8];
10607 
10608 	u8         reserved_at_20[0x60];
10609 };
10610 
10611 struct mlx5_ifc_plbf_reg_bits {
10612 	u8         reserved_at_0[0x8];
10613 	u8         local_port[0x8];
10614 	u8         reserved_at_10[0xd];
10615 	u8         lbf_mode[0x3];
10616 
10617 	u8         reserved_at_20[0x20];
10618 };
10619 
10620 struct mlx5_ifc_pipg_reg_bits {
10621 	u8         reserved_at_0[0x8];
10622 	u8         local_port[0x8];
10623 	u8         reserved_at_10[0x10];
10624 
10625 	u8         dic[0x1];
10626 	u8         reserved_at_21[0x19];
10627 	u8         ipg[0x4];
10628 	u8         reserved_at_3e[0x2];
10629 };
10630 
10631 struct mlx5_ifc_pifr_reg_bits {
10632 	u8         reserved_at_0[0x8];
10633 	u8         local_port[0x8];
10634 	u8         reserved_at_10[0x10];
10635 
10636 	u8         reserved_at_20[0xe0];
10637 
10638 	u8         port_filter[8][0x20];
10639 
10640 	u8         port_filter_update_en[8][0x20];
10641 };
10642 
10643 enum {
10644 	MLX5_BUF_OWNERSHIP_UNKNOWN	= 0x0,
10645 	MLX5_BUF_OWNERSHIP_FW_OWNED	= 0x1,
10646 	MLX5_BUF_OWNERSHIP_SW_OWNED	= 0x2,
10647 };
10648 
10649 struct mlx5_ifc_pfcc_reg_bits {
10650 	u8         reserved_at_0[0x4];
10651 	u8	   buf_ownership[0x2];
10652 	u8	   reserved_at_6[0x2];
10653 	u8         local_port[0x8];
10654 	u8         reserved_at_10[0xa];
10655 	u8	   cable_length_mask[0x1];
10656 	u8         ppan_mask_n[0x1];
10657 	u8         minor_stall_mask[0x1];
10658 	u8         critical_stall_mask[0x1];
10659 	u8         reserved_at_1e[0x2];
10660 
10661 	u8         ppan[0x4];
10662 	u8         reserved_at_24[0x4];
10663 	u8         prio_mask_tx[0x8];
10664 	u8         reserved_at_30[0x8];
10665 	u8         prio_mask_rx[0x8];
10666 
10667 	u8         pptx[0x1];
10668 	u8         aptx[0x1];
10669 	u8         pptx_mask_n[0x1];
10670 	u8         reserved_at_43[0x5];
10671 	u8         pfctx[0x8];
10672 	u8         reserved_at_50[0x10];
10673 
10674 	u8         pprx[0x1];
10675 	u8         aprx[0x1];
10676 	u8         pprx_mask_n[0x1];
10677 	u8         reserved_at_63[0x5];
10678 	u8         pfcrx[0x8];
10679 	u8         reserved_at_70[0x10];
10680 
10681 	u8         device_stall_minor_watermark[0x10];
10682 	u8         device_stall_critical_watermark[0x10];
10683 
10684 	u8	   reserved_at_a0[0x18];
10685 	u8	   cable_length[0x8];
10686 
10687 	u8         reserved_at_c0[0x40];
10688 };
10689 
10690 struct mlx5_ifc_pelc_reg_bits {
10691 	u8         op[0x4];
10692 	u8         reserved_at_4[0x4];
10693 	u8         local_port[0x8];
10694 	u8         reserved_at_10[0x10];
10695 
10696 	u8         op_admin[0x8];
10697 	u8         op_capability[0x8];
10698 	u8         op_request[0x8];
10699 	u8         op_active[0x8];
10700 
10701 	u8         admin[0x40];
10702 
10703 	u8         capability[0x40];
10704 
10705 	u8         request[0x40];
10706 
10707 	u8         active[0x40];
10708 
10709 	u8         reserved_at_140[0x80];
10710 };
10711 
10712 struct mlx5_ifc_peir_reg_bits {
10713 	u8         reserved_at_0[0x8];
10714 	u8         local_port[0x8];
10715 	u8         reserved_at_10[0x10];
10716 
10717 	u8         reserved_at_20[0xc];
10718 	u8         error_count[0x4];
10719 	u8         reserved_at_30[0x10];
10720 
10721 	u8         reserved_at_40[0xc];
10722 	u8         lane[0x4];
10723 	u8         reserved_at_50[0x8];
10724 	u8         error_type[0x8];
10725 };
10726 
10727 struct mlx5_ifc_mpegc_reg_bits {
10728 	u8         reserved_at_0[0x30];
10729 	u8         field_select[0x10];
10730 
10731 	u8         tx_overflow_sense[0x1];
10732 	u8         mark_cqe[0x1];
10733 	u8         mark_cnp[0x1];
10734 	u8         reserved_at_43[0x1b];
10735 	u8         tx_lossy_overflow_oper[0x2];
10736 
10737 	u8         reserved_at_60[0x100];
10738 };
10739 
10740 struct mlx5_ifc_mpir_reg_bits {
10741 	u8         sdm[0x1];
10742 	u8         reserved_at_1[0x1b];
10743 	u8         host_buses[0x4];
10744 
10745 	u8         reserved_at_20[0x20];
10746 
10747 	u8         local_port[0x8];
10748 	u8         reserved_at_28[0x18];
10749 
10750 	u8         reserved_at_60[0x20];
10751 };
10752 
10753 enum {
10754 	MLX5_MTUTC_FREQ_ADJ_UNITS_PPB          = 0x0,
10755 	MLX5_MTUTC_FREQ_ADJ_UNITS_SCALED_PPM   = 0x1,
10756 };
10757 
10758 enum {
10759 	MLX5_MTUTC_OPERATION_SET_TIME_IMMEDIATE   = 0x1,
10760 	MLX5_MTUTC_OPERATION_ADJUST_TIME          = 0x2,
10761 	MLX5_MTUTC_OPERATION_ADJUST_FREQ_UTC      = 0x3,
10762 };
10763 
10764 struct mlx5_ifc_mtutc_reg_bits {
10765 	u8         reserved_at_0[0x5];
10766 	u8         freq_adj_units[0x3];
10767 	u8         reserved_at_8[0x3];
10768 	u8         log_max_freq_adjustment[0x5];
10769 
10770 	u8         reserved_at_10[0xc];
10771 	u8         operation[0x4];
10772 
10773 	u8         freq_adjustment[0x20];
10774 
10775 	u8         reserved_at_40[0x40];
10776 
10777 	u8         utc_sec[0x20];
10778 
10779 	u8         reserved_at_a0[0x2];
10780 	u8         utc_nsec[0x1e];
10781 
10782 	u8         time_adjustment[0x20];
10783 };
10784 
10785 struct mlx5_ifc_pcam_enhanced_features_bits {
10786 	u8         reserved_at_0[0x10];
10787 	u8         ppcnt_recovery_counters[0x1];
10788 	u8         reserved_at_11[0x7];
10789 	u8	   cable_length[0x1];
10790 	u8	   reserved_at_19[0x4];
10791 	u8         fec_200G_per_lane_in_pplm[0x1];
10792 	u8         reserved_at_1e[0x2a];
10793 	u8         fec_100G_per_lane_in_pplm[0x1];
10794 	u8         reserved_at_49[0xa];
10795 	u8	   buffer_ownership[0x1];
10796 	u8	   resereved_at_54[0x14];
10797 	u8         fec_50G_per_lane_in_pplm[0x1];
10798 	u8         reserved_at_69[0x4];
10799 	u8         rx_icrc_encapsulated_counter[0x1];
10800 	u8	   reserved_at_6e[0x4];
10801 	u8         ptys_extended_ethernet[0x1];
10802 	u8	   reserved_at_73[0x3];
10803 	u8         pfcc_mask[0x1];
10804 	u8         reserved_at_77[0x3];
10805 	u8         per_lane_error_counters[0x1];
10806 	u8         rx_buffer_fullness_counters[0x1];
10807 	u8         ptys_connector_type[0x1];
10808 	u8         reserved_at_7d[0x1];
10809 	u8         ppcnt_discard_group[0x1];
10810 	u8         ppcnt_statistical_group[0x1];
10811 };
10812 
10813 struct mlx5_ifc_pcam_regs_5000_to_507f_bits {
10814 	u8         port_access_reg_cap_mask_127_to_96[0x20];
10815 	u8         port_access_reg_cap_mask_95_to_64[0x20];
10816 
10817 	u8         port_access_reg_cap_mask_63_to_36[0x1c];
10818 	u8         pplm[0x1];
10819 	u8         port_access_reg_cap_mask_34_to_32[0x3];
10820 
10821 	u8         port_access_reg_cap_mask_31_to_13[0x13];
10822 	u8         pbmc[0x1];
10823 	u8         pptb[0x1];
10824 	u8         port_access_reg_cap_mask_10_to_09[0x2];
10825 	u8         ppcnt[0x1];
10826 	u8         port_access_reg_cap_mask_07_to_00[0x8];
10827 };
10828 
10829 struct mlx5_ifc_pcam_reg_bits {
10830 	u8         reserved_at_0[0x8];
10831 	u8         feature_group[0x8];
10832 	u8         reserved_at_10[0x8];
10833 	u8         access_reg_group[0x8];
10834 
10835 	u8         reserved_at_20[0x20];
10836 
10837 	union {
10838 		struct mlx5_ifc_pcam_regs_5000_to_507f_bits regs_5000_to_507f;
10839 		u8         reserved_at_0[0x80];
10840 	} port_access_reg_cap_mask;
10841 
10842 	u8         reserved_at_c0[0x80];
10843 
10844 	union {
10845 		struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features;
10846 		u8         reserved_at_0[0x80];
10847 	} feature_cap_mask;
10848 
10849 	u8         reserved_at_1c0[0xc0];
10850 };
10851 
10852 struct mlx5_ifc_mcam_enhanced_features_bits {
10853 	u8         reserved_at_0[0x50];
10854 	u8         mtutc_freq_adj_units[0x1];
10855 	u8         mtutc_time_adjustment_extended_range[0x1];
10856 	u8         reserved_at_52[0xb];
10857 	u8         mcia_32dwords[0x1];
10858 	u8         out_pulse_duration_ns[0x1];
10859 	u8         npps_period[0x1];
10860 	u8         reserved_at_60[0xa];
10861 	u8         reset_state[0x1];
10862 	u8         ptpcyc2realtime_modify[0x1];
10863 	u8         reserved_at_6c[0x2];
10864 	u8         pci_status_and_power[0x1];
10865 	u8         reserved_at_6f[0x5];
10866 	u8         mark_tx_action_cnp[0x1];
10867 	u8         mark_tx_action_cqe[0x1];
10868 	u8         dynamic_tx_overflow[0x1];
10869 	u8         reserved_at_77[0x4];
10870 	u8         pcie_outbound_stalled[0x1];
10871 	u8         tx_overflow_buffer_pkt[0x1];
10872 	u8         mtpps_enh_out_per_adj[0x1];
10873 	u8         mtpps_fs[0x1];
10874 	u8         pcie_performance_group[0x1];
10875 };
10876 
10877 struct mlx5_ifc_mcam_access_reg_bits {
10878 	u8         reserved_at_0[0x1c];
10879 	u8         mcda[0x1];
10880 	u8         mcc[0x1];
10881 	u8         mcqi[0x1];
10882 	u8         mcqs[0x1];
10883 
10884 	u8         regs_95_to_90[0x6];
10885 	u8         mpir[0x1];
10886 	u8         regs_88_to_87[0x2];
10887 	u8         mpegc[0x1];
10888 	u8         mtutc[0x1];
10889 	u8         regs_84_to_68[0x11];
10890 	u8         tracer_registers[0x4];
10891 
10892 	u8         regs_63_to_46[0x12];
10893 	u8         mrtc[0x1];
10894 	u8         regs_44_to_41[0x4];
10895 	u8         mfrl[0x1];
10896 	u8         regs_39_to_32[0x8];
10897 
10898 	u8         regs_31_to_11[0x15];
10899 	u8         mtmp[0x1];
10900 	u8         regs_9_to_0[0xa];
10901 };
10902 
10903 struct mlx5_ifc_mcam_access_reg_bits1 {
10904 	u8         regs_127_to_96[0x20];
10905 
10906 	u8         regs_95_to_64[0x20];
10907 
10908 	u8         regs_63_to_32[0x20];
10909 
10910 	u8         regs_31_to_0[0x20];
10911 };
10912 
10913 struct mlx5_ifc_mcam_access_reg_bits2 {
10914 	u8         regs_127_to_99[0x1d];
10915 	u8         mirc[0x1];
10916 	u8         regs_97_to_96[0x2];
10917 
10918 	u8         regs_95_to_87[0x09];
10919 	u8         synce_registers[0x2];
10920 	u8         regs_84_to_64[0x15];
10921 
10922 	u8         regs_63_to_32[0x20];
10923 
10924 	u8         regs_31_to_0[0x20];
10925 };
10926 
10927 struct mlx5_ifc_mcam_access_reg_bits3 {
10928 	u8         regs_127_to_96[0x20];
10929 
10930 	u8         regs_95_to_64[0x20];
10931 
10932 	u8         regs_63_to_32[0x20];
10933 
10934 	u8         regs_31_to_3[0x1d];
10935 	u8         mrtcq[0x1];
10936 	u8         mtctr[0x1];
10937 	u8         mtptm[0x1];
10938 };
10939 
10940 struct mlx5_ifc_mcam_reg_bits {
10941 	u8         reserved_at_0[0x8];
10942 	u8         feature_group[0x8];
10943 	u8         reserved_at_10[0x8];
10944 	u8         access_reg_group[0x8];
10945 
10946 	u8         reserved_at_20[0x20];
10947 
10948 	union {
10949 		struct mlx5_ifc_mcam_access_reg_bits access_regs;
10950 		struct mlx5_ifc_mcam_access_reg_bits1 access_regs1;
10951 		struct mlx5_ifc_mcam_access_reg_bits2 access_regs2;
10952 		struct mlx5_ifc_mcam_access_reg_bits3 access_regs3;
10953 		u8         reserved_at_0[0x80];
10954 	} mng_access_reg_cap_mask;
10955 
10956 	u8         reserved_at_c0[0x80];
10957 
10958 	union {
10959 		struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features;
10960 		u8         reserved_at_0[0x80];
10961 	} mng_feature_cap_mask;
10962 
10963 	u8         reserved_at_1c0[0x80];
10964 };
10965 
10966 struct mlx5_ifc_qcam_access_reg_cap_mask {
10967 	u8         qcam_access_reg_cap_mask_127_to_20[0x6C];
10968 	u8         qpdpm[0x1];
10969 	u8         qcam_access_reg_cap_mask_18_to_4[0x0F];
10970 	u8         qdpm[0x1];
10971 	u8         qpts[0x1];
10972 	u8         qcap[0x1];
10973 	u8         qcam_access_reg_cap_mask_0[0x1];
10974 };
10975 
10976 struct mlx5_ifc_qcam_qos_feature_cap_mask {
10977 	u8         qcam_qos_feature_cap_mask_127_to_1[0x7F];
10978 	u8         qpts_trust_both[0x1];
10979 };
10980 
10981 struct mlx5_ifc_qcam_reg_bits {
10982 	u8         reserved_at_0[0x8];
10983 	u8         feature_group[0x8];
10984 	u8         reserved_at_10[0x8];
10985 	u8         access_reg_group[0x8];
10986 	u8         reserved_at_20[0x20];
10987 
10988 	union {
10989 		struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap;
10990 		u8  reserved_at_0[0x80];
10991 	} qos_access_reg_cap_mask;
10992 
10993 	u8         reserved_at_c0[0x80];
10994 
10995 	union {
10996 		struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap;
10997 		u8  reserved_at_0[0x80];
10998 	} qos_feature_cap_mask;
10999 
11000 	u8         reserved_at_1c0[0x80];
11001 };
11002 
11003 struct mlx5_ifc_core_dump_reg_bits {
11004 	u8         reserved_at_0[0x18];
11005 	u8         core_dump_type[0x8];
11006 
11007 	u8         reserved_at_20[0x30];
11008 	u8         vhca_id[0x10];
11009 
11010 	u8         reserved_at_60[0x8];
11011 	u8         qpn[0x18];
11012 	u8         reserved_at_80[0x180];
11013 };
11014 
11015 struct mlx5_ifc_pcap_reg_bits {
11016 	u8         reserved_at_0[0x8];
11017 	u8         local_port[0x8];
11018 	u8         reserved_at_10[0x10];
11019 
11020 	u8         port_capability_mask[4][0x20];
11021 };
11022 
11023 struct mlx5_ifc_paos_reg_bits {
11024 	u8         swid[0x8];
11025 	u8         local_port[0x8];
11026 	u8         reserved_at_10[0x4];
11027 	u8         admin_status[0x4];
11028 	u8         reserved_at_18[0x4];
11029 	u8         oper_status[0x4];
11030 
11031 	u8         ase[0x1];
11032 	u8         ee[0x1];
11033 	u8         reserved_at_22[0x1c];
11034 	u8         e[0x2];
11035 
11036 	u8         reserved_at_40[0x40];
11037 };
11038 
11039 struct mlx5_ifc_pamp_reg_bits {
11040 	u8         reserved_at_0[0x8];
11041 	u8         opamp_group[0x8];
11042 	u8         reserved_at_10[0xc];
11043 	u8         opamp_group_type[0x4];
11044 
11045 	u8         start_index[0x10];
11046 	u8         reserved_at_30[0x4];
11047 	u8         num_of_indices[0xc];
11048 
11049 	u8         index_data[18][0x10];
11050 };
11051 
11052 struct mlx5_ifc_pcmr_reg_bits {
11053 	u8         reserved_at_0[0x8];
11054 	u8         local_port[0x8];
11055 	u8         reserved_at_10[0x10];
11056 
11057 	u8         entropy_force_cap[0x1];
11058 	u8         entropy_calc_cap[0x1];
11059 	u8         entropy_gre_calc_cap[0x1];
11060 	u8         reserved_at_23[0xf];
11061 	u8         rx_ts_over_crc_cap[0x1];
11062 	u8         reserved_at_33[0xb];
11063 	u8         fcs_cap[0x1];
11064 	u8         reserved_at_3f[0x1];
11065 
11066 	u8         entropy_force[0x1];
11067 	u8         entropy_calc[0x1];
11068 	u8         entropy_gre_calc[0x1];
11069 	u8         reserved_at_43[0xf];
11070 	u8         rx_ts_over_crc[0x1];
11071 	u8         reserved_at_53[0xb];
11072 	u8         fcs_chk[0x1];
11073 	u8         reserved_at_5f[0x1];
11074 };
11075 
11076 struct mlx5_ifc_lane_2_module_mapping_bits {
11077 	u8         reserved_at_0[0x4];
11078 	u8         rx_lane[0x4];
11079 	u8         reserved_at_8[0x4];
11080 	u8         tx_lane[0x4];
11081 	u8         reserved_at_10[0x8];
11082 	u8         module[0x8];
11083 };
11084 
11085 struct mlx5_ifc_bufferx_reg_bits {
11086 	u8         reserved_at_0[0x6];
11087 	u8         lossy[0x1];
11088 	u8         epsb[0x1];
11089 	u8         reserved_at_8[0x8];
11090 	u8         size[0x10];
11091 
11092 	u8         xoff_threshold[0x10];
11093 	u8         xon_threshold[0x10];
11094 };
11095 
11096 struct mlx5_ifc_set_node_in_bits {
11097 	u8         node_description[64][0x8];
11098 };
11099 
11100 struct mlx5_ifc_register_power_settings_bits {
11101 	u8         reserved_at_0[0x18];
11102 	u8         power_settings_level[0x8];
11103 
11104 	u8         reserved_at_20[0x60];
11105 };
11106 
11107 struct mlx5_ifc_register_host_endianness_bits {
11108 	u8         he[0x1];
11109 	u8         reserved_at_1[0x1f];
11110 
11111 	u8         reserved_at_20[0x60];
11112 };
11113 
11114 struct mlx5_ifc_umr_pointer_desc_argument_bits {
11115 	u8         reserved_at_0[0x20];
11116 
11117 	u8         mkey[0x20];
11118 
11119 	u8         addressh_63_32[0x20];
11120 
11121 	u8         addressl_31_0[0x20];
11122 };
11123 
11124 struct mlx5_ifc_ud_adrs_vector_bits {
11125 	u8         dc_key[0x40];
11126 
11127 	u8         ext[0x1];
11128 	u8         reserved_at_41[0x7];
11129 	u8         destination_qp_dct[0x18];
11130 
11131 	u8         static_rate[0x4];
11132 	u8         sl_eth_prio[0x4];
11133 	u8         fl[0x1];
11134 	u8         mlid[0x7];
11135 	u8         rlid_udp_sport[0x10];
11136 
11137 	u8         reserved_at_80[0x20];
11138 
11139 	u8         rmac_47_16[0x20];
11140 
11141 	u8         rmac_15_0[0x10];
11142 	u8         tclass[0x8];
11143 	u8         hop_limit[0x8];
11144 
11145 	u8         reserved_at_e0[0x1];
11146 	u8         grh[0x1];
11147 	u8         reserved_at_e2[0x2];
11148 	u8         src_addr_index[0x8];
11149 	u8         flow_label[0x14];
11150 
11151 	u8         rgid_rip[16][0x8];
11152 };
11153 
11154 struct mlx5_ifc_pages_req_event_bits {
11155 	u8         reserved_at_0[0x10];
11156 	u8         function_id[0x10];
11157 
11158 	u8         num_pages[0x20];
11159 
11160 	u8         reserved_at_40[0xa0];
11161 };
11162 
11163 struct mlx5_ifc_eqe_bits {
11164 	u8         reserved_at_0[0x8];
11165 	u8         event_type[0x8];
11166 	u8         reserved_at_10[0x8];
11167 	u8         event_sub_type[0x8];
11168 
11169 	u8         reserved_at_20[0xe0];
11170 
11171 	union mlx5_ifc_event_auto_bits event_data;
11172 
11173 	u8         reserved_at_1e0[0x10];
11174 	u8         signature[0x8];
11175 	u8         reserved_at_1f8[0x7];
11176 	u8         owner[0x1];
11177 };
11178 
11179 enum {
11180 	MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT  = 0x7,
11181 };
11182 
11183 struct mlx5_ifc_cmd_queue_entry_bits {
11184 	u8         type[0x8];
11185 	u8         reserved_at_8[0x18];
11186 
11187 	u8         input_length[0x20];
11188 
11189 	u8         input_mailbox_pointer_63_32[0x20];
11190 
11191 	u8         input_mailbox_pointer_31_9[0x17];
11192 	u8         reserved_at_77[0x9];
11193 
11194 	u8         command_input_inline_data[16][0x8];
11195 
11196 	u8         command_output_inline_data[16][0x8];
11197 
11198 	u8         output_mailbox_pointer_63_32[0x20];
11199 
11200 	u8         output_mailbox_pointer_31_9[0x17];
11201 	u8         reserved_at_1b7[0x9];
11202 
11203 	u8         output_length[0x20];
11204 
11205 	u8         token[0x8];
11206 	u8         signature[0x8];
11207 	u8         reserved_at_1f0[0x8];
11208 	u8         status[0x7];
11209 	u8         ownership[0x1];
11210 };
11211 
11212 struct mlx5_ifc_cmd_out_bits {
11213 	u8         status[0x8];
11214 	u8         reserved_at_8[0x18];
11215 
11216 	u8         syndrome[0x20];
11217 
11218 	u8         command_output[0x20];
11219 };
11220 
11221 struct mlx5_ifc_cmd_in_bits {
11222 	u8         opcode[0x10];
11223 	u8         reserved_at_10[0x10];
11224 
11225 	u8         reserved_at_20[0x10];
11226 	u8         op_mod[0x10];
11227 
11228 	u8         command[][0x20];
11229 };
11230 
11231 struct mlx5_ifc_cmd_if_box_bits {
11232 	u8         mailbox_data[512][0x8];
11233 
11234 	u8         reserved_at_1000[0x180];
11235 
11236 	u8         next_pointer_63_32[0x20];
11237 
11238 	u8         next_pointer_31_10[0x16];
11239 	u8         reserved_at_11b6[0xa];
11240 
11241 	u8         block_number[0x20];
11242 
11243 	u8         reserved_at_11e0[0x8];
11244 	u8         token[0x8];
11245 	u8         ctrl_signature[0x8];
11246 	u8         signature[0x8];
11247 };
11248 
11249 struct mlx5_ifc_mtt_bits {
11250 	u8         ptag_63_32[0x20];
11251 
11252 	u8         ptag_31_8[0x18];
11253 	u8         reserved_at_38[0x6];
11254 	u8         wr_en[0x1];
11255 	u8         rd_en[0x1];
11256 };
11257 
11258 struct mlx5_ifc_query_wol_rol_out_bits {
11259 	u8         status[0x8];
11260 	u8         reserved_at_8[0x18];
11261 
11262 	u8         syndrome[0x20];
11263 
11264 	u8         reserved_at_40[0x10];
11265 	u8         rol_mode[0x8];
11266 	u8         wol_mode[0x8];
11267 
11268 	u8         reserved_at_60[0x20];
11269 };
11270 
11271 struct mlx5_ifc_query_wol_rol_in_bits {
11272 	u8         opcode[0x10];
11273 	u8         reserved_at_10[0x10];
11274 
11275 	u8         reserved_at_20[0x10];
11276 	u8         op_mod[0x10];
11277 
11278 	u8         reserved_at_40[0x40];
11279 };
11280 
11281 struct mlx5_ifc_set_wol_rol_out_bits {
11282 	u8         status[0x8];
11283 	u8         reserved_at_8[0x18];
11284 
11285 	u8         syndrome[0x20];
11286 
11287 	u8         reserved_at_40[0x40];
11288 };
11289 
11290 struct mlx5_ifc_set_wol_rol_in_bits {
11291 	u8         opcode[0x10];
11292 	u8         reserved_at_10[0x10];
11293 
11294 	u8         reserved_at_20[0x10];
11295 	u8         op_mod[0x10];
11296 
11297 	u8         rol_mode_valid[0x1];
11298 	u8         wol_mode_valid[0x1];
11299 	u8         reserved_at_42[0xe];
11300 	u8         rol_mode[0x8];
11301 	u8         wol_mode[0x8];
11302 
11303 	u8         reserved_at_60[0x20];
11304 };
11305 
11306 enum {
11307 	MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER  = 0x0,
11308 	MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED     = 0x1,
11309 	MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC  = 0x2,
11310 	MLX5_INITIAL_SEG_NIC_INTERFACE_SW_RESET     = 0x7,
11311 };
11312 
11313 enum {
11314 	MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER  = 0x0,
11315 	MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED     = 0x1,
11316 	MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC  = 0x2,
11317 };
11318 
11319 enum {
11320 	MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR              = 0x1,
11321 	MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC                   = 0x7,
11322 	MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR                 = 0x8,
11323 	MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR                   = 0x9,
11324 	MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR            = 0xa,
11325 	MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR                 = 0xb,
11326 	MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN  = 0xc,
11327 	MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR                    = 0xd,
11328 	MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV                       = 0xe,
11329 	MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR                    = 0xf,
11330 	MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR                = 0x10,
11331 	MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PCI_POISONED_ERR         = 0x12,
11332 	MLX5_INITIAL_SEG_HEALTH_SYNDROME_TRUST_LOCKDOWN_ERR           = 0x13,
11333 };
11334 
11335 struct mlx5_ifc_initial_seg_bits {
11336 	u8         fw_rev_minor[0x10];
11337 	u8         fw_rev_major[0x10];
11338 
11339 	u8         cmd_interface_rev[0x10];
11340 	u8         fw_rev_subminor[0x10];
11341 
11342 	u8         reserved_at_40[0x40];
11343 
11344 	u8         cmdq_phy_addr_63_32[0x20];
11345 
11346 	u8         cmdq_phy_addr_31_12[0x14];
11347 	u8         reserved_at_b4[0x2];
11348 	u8         nic_interface[0x2];
11349 	u8         log_cmdq_size[0x4];
11350 	u8         log_cmdq_stride[0x4];
11351 
11352 	u8         command_doorbell_vector[0x20];
11353 
11354 	u8         reserved_at_e0[0xf00];
11355 
11356 	u8         initializing[0x1];
11357 	u8         reserved_at_fe1[0x4];
11358 	u8         nic_interface_supported[0x3];
11359 	u8         embedded_cpu[0x1];
11360 	u8         reserved_at_fe9[0x17];
11361 
11362 	struct mlx5_ifc_health_buffer_bits health_buffer;
11363 
11364 	u8         no_dram_nic_offset[0x20];
11365 
11366 	u8         reserved_at_1220[0x6e40];
11367 
11368 	u8         reserved_at_8060[0x1f];
11369 	u8         clear_int[0x1];
11370 
11371 	u8         health_syndrome[0x8];
11372 	u8         health_counter[0x18];
11373 
11374 	u8         reserved_at_80a0[0x17fc0];
11375 };
11376 
11377 struct mlx5_ifc_mtpps_reg_bits {
11378 	u8         reserved_at_0[0xc];
11379 	u8         cap_number_of_pps_pins[0x4];
11380 	u8         reserved_at_10[0x4];
11381 	u8         cap_max_num_of_pps_in_pins[0x4];
11382 	u8         reserved_at_18[0x4];
11383 	u8         cap_max_num_of_pps_out_pins[0x4];
11384 
11385 	u8         reserved_at_20[0x13];
11386 	u8         cap_log_min_npps_period[0x5];
11387 	u8         reserved_at_38[0x3];
11388 	u8         cap_log_min_out_pulse_duration_ns[0x5];
11389 
11390 	u8         reserved_at_40[0x4];
11391 	u8         cap_pin_3_mode[0x4];
11392 	u8         reserved_at_48[0x4];
11393 	u8         cap_pin_2_mode[0x4];
11394 	u8         reserved_at_50[0x4];
11395 	u8         cap_pin_1_mode[0x4];
11396 	u8         reserved_at_58[0x4];
11397 	u8         cap_pin_0_mode[0x4];
11398 
11399 	u8         reserved_at_60[0x4];
11400 	u8         cap_pin_7_mode[0x4];
11401 	u8         reserved_at_68[0x4];
11402 	u8         cap_pin_6_mode[0x4];
11403 	u8         reserved_at_70[0x4];
11404 	u8         cap_pin_5_mode[0x4];
11405 	u8         reserved_at_78[0x4];
11406 	u8         cap_pin_4_mode[0x4];
11407 
11408 	u8         field_select[0x20];
11409 	u8         reserved_at_a0[0x20];
11410 
11411 	u8         npps_period[0x40];
11412 
11413 	u8         enable[0x1];
11414 	u8         reserved_at_101[0xb];
11415 	u8         pattern[0x4];
11416 	u8         reserved_at_110[0x4];
11417 	u8         pin_mode[0x4];
11418 	u8         pin[0x8];
11419 
11420 	u8         reserved_at_120[0x2];
11421 	u8         out_pulse_duration_ns[0x1e];
11422 
11423 	u8         time_stamp[0x40];
11424 
11425 	u8         out_pulse_duration[0x10];
11426 	u8         out_periodic_adjustment[0x10];
11427 	u8         enhanced_out_periodic_adjustment[0x20];
11428 
11429 	u8         reserved_at_1c0[0x20];
11430 };
11431 
11432 struct mlx5_ifc_mtppse_reg_bits {
11433 	u8         reserved_at_0[0x18];
11434 	u8         pin[0x8];
11435 	u8         event_arm[0x1];
11436 	u8         reserved_at_21[0x1b];
11437 	u8         event_generation_mode[0x4];
11438 	u8         reserved_at_40[0x40];
11439 };
11440 
11441 struct mlx5_ifc_mcqs_reg_bits {
11442 	u8         last_index_flag[0x1];
11443 	u8         reserved_at_1[0x7];
11444 	u8         fw_device[0x8];
11445 	u8         component_index[0x10];
11446 
11447 	u8         reserved_at_20[0x10];
11448 	u8         identifier[0x10];
11449 
11450 	u8         reserved_at_40[0x17];
11451 	u8         component_status[0x5];
11452 	u8         component_update_state[0x4];
11453 
11454 	u8         last_update_state_changer_type[0x4];
11455 	u8         last_update_state_changer_host_id[0x4];
11456 	u8         reserved_at_68[0x18];
11457 };
11458 
11459 struct mlx5_ifc_mcqi_cap_bits {
11460 	u8         supported_info_bitmask[0x20];
11461 
11462 	u8         component_size[0x20];
11463 
11464 	u8         max_component_size[0x20];
11465 
11466 	u8         log_mcda_word_size[0x4];
11467 	u8         reserved_at_64[0xc];
11468 	u8         mcda_max_write_size[0x10];
11469 
11470 	u8         rd_en[0x1];
11471 	u8         reserved_at_81[0x1];
11472 	u8         match_chip_id[0x1];
11473 	u8         match_psid[0x1];
11474 	u8         check_user_timestamp[0x1];
11475 	u8         match_base_guid_mac[0x1];
11476 	u8         reserved_at_86[0x1a];
11477 };
11478 
11479 struct mlx5_ifc_mcqi_version_bits {
11480 	u8         reserved_at_0[0x2];
11481 	u8         build_time_valid[0x1];
11482 	u8         user_defined_time_valid[0x1];
11483 	u8         reserved_at_4[0x14];
11484 	u8         version_string_length[0x8];
11485 
11486 	u8         version[0x20];
11487 
11488 	u8         build_time[0x40];
11489 
11490 	u8         user_defined_time[0x40];
11491 
11492 	u8         build_tool_version[0x20];
11493 
11494 	u8         reserved_at_e0[0x20];
11495 
11496 	u8         version_string[92][0x8];
11497 };
11498 
11499 struct mlx5_ifc_mcqi_activation_method_bits {
11500 	u8         pending_server_ac_power_cycle[0x1];
11501 	u8         pending_server_dc_power_cycle[0x1];
11502 	u8         pending_server_reboot[0x1];
11503 	u8         pending_fw_reset[0x1];
11504 	u8         auto_activate[0x1];
11505 	u8         all_hosts_sync[0x1];
11506 	u8         device_hw_reset[0x1];
11507 	u8         reserved_at_7[0x19];
11508 };
11509 
11510 union mlx5_ifc_mcqi_reg_data_bits {
11511 	struct mlx5_ifc_mcqi_cap_bits               mcqi_caps;
11512 	struct mlx5_ifc_mcqi_version_bits           mcqi_version;
11513 	struct mlx5_ifc_mcqi_activation_method_bits mcqi_activation_mathod;
11514 };
11515 
11516 struct mlx5_ifc_mcqi_reg_bits {
11517 	u8         read_pending_component[0x1];
11518 	u8         reserved_at_1[0xf];
11519 	u8         component_index[0x10];
11520 
11521 	u8         reserved_at_20[0x20];
11522 
11523 	u8         reserved_at_40[0x1b];
11524 	u8         info_type[0x5];
11525 
11526 	u8         info_size[0x20];
11527 
11528 	u8         offset[0x20];
11529 
11530 	u8         reserved_at_a0[0x10];
11531 	u8         data_size[0x10];
11532 
11533 	union mlx5_ifc_mcqi_reg_data_bits data[];
11534 };
11535 
11536 struct mlx5_ifc_mcc_reg_bits {
11537 	u8         reserved_at_0[0x4];
11538 	u8         time_elapsed_since_last_cmd[0xc];
11539 	u8         reserved_at_10[0x8];
11540 	u8         instruction[0x8];
11541 
11542 	u8         reserved_at_20[0x10];
11543 	u8         component_index[0x10];
11544 
11545 	u8         reserved_at_40[0x8];
11546 	u8         update_handle[0x18];
11547 
11548 	u8         handle_owner_type[0x4];
11549 	u8         handle_owner_host_id[0x4];
11550 	u8         reserved_at_68[0x1];
11551 	u8         control_progress[0x7];
11552 	u8         error_code[0x8];
11553 	u8         reserved_at_78[0x4];
11554 	u8         control_state[0x4];
11555 
11556 	u8         component_size[0x20];
11557 
11558 	u8         reserved_at_a0[0x60];
11559 };
11560 
11561 struct mlx5_ifc_mcda_reg_bits {
11562 	u8         reserved_at_0[0x8];
11563 	u8         update_handle[0x18];
11564 
11565 	u8         offset[0x20];
11566 
11567 	u8         reserved_at_40[0x10];
11568 	u8         size[0x10];
11569 
11570 	u8         reserved_at_60[0x20];
11571 
11572 	u8         data[][0x20];
11573 };
11574 
11575 enum {
11576 	MLX5_MFRL_REG_PCI_RESET_METHOD_LINK_TOGGLE = 0,
11577 	MLX5_MFRL_REG_PCI_RESET_METHOD_HOT_RESET = 1,
11578 };
11579 
11580 enum {
11581 	MLX5_MFRL_REG_RESET_STATE_IDLE = 0,
11582 	MLX5_MFRL_REG_RESET_STATE_IN_NEGOTIATION = 1,
11583 	MLX5_MFRL_REG_RESET_STATE_RESET_IN_PROGRESS = 2,
11584 	MLX5_MFRL_REG_RESET_STATE_NEG_TIMEOUT = 3,
11585 	MLX5_MFRL_REG_RESET_STATE_NACK = 4,
11586 	MLX5_MFRL_REG_RESET_STATE_UNLOAD_TIMEOUT = 5,
11587 };
11588 
11589 enum {
11590 	MLX5_MFRL_REG_RESET_TYPE_FULL_CHIP = BIT(0),
11591 	MLX5_MFRL_REG_RESET_TYPE_NET_PORT_ALIVE = BIT(1),
11592 };
11593 
11594 enum {
11595 	MLX5_MFRL_REG_RESET_LEVEL0 = BIT(0),
11596 	MLX5_MFRL_REG_RESET_LEVEL3 = BIT(3),
11597 	MLX5_MFRL_REG_RESET_LEVEL6 = BIT(6),
11598 };
11599 
11600 struct mlx5_ifc_mfrl_reg_bits {
11601 	u8         reserved_at_0[0x20];
11602 
11603 	u8         reserved_at_20[0x2];
11604 	u8         pci_sync_for_fw_update_start[0x1];
11605 	u8         pci_sync_for_fw_update_resp[0x2];
11606 	u8         rst_type_sel[0x3];
11607 	u8         pci_reset_req_method[0x3];
11608 	u8         reserved_at_2b[0x1];
11609 	u8         reset_state[0x4];
11610 	u8         reset_type[0x8];
11611 	u8         reset_level[0x8];
11612 };
11613 
11614 struct mlx5_ifc_mirc_reg_bits {
11615 	u8         reserved_at_0[0x18];
11616 	u8         status_code[0x8];
11617 
11618 	u8         reserved_at_20[0x20];
11619 };
11620 
11621 struct mlx5_ifc_pddr_monitor_opcode_bits {
11622 	u8         reserved_at_0[0x10];
11623 	u8         monitor_opcode[0x10];
11624 };
11625 
11626 union mlx5_ifc_pddr_troubleshooting_page_status_opcode_auto_bits {
11627 	struct mlx5_ifc_pddr_monitor_opcode_bits pddr_monitor_opcode;
11628 	u8         reserved_at_0[0x20];
11629 };
11630 
11631 enum {
11632 	/* Monitor opcodes */
11633 	MLX5_PDDR_REG_TRBLSH_GROUP_OPCODE_MONITOR = 0x0,
11634 };
11635 
11636 struct mlx5_ifc_pddr_troubleshooting_page_bits {
11637 	u8         reserved_at_0[0x10];
11638 	u8         group_opcode[0x10];
11639 
11640 	union mlx5_ifc_pddr_troubleshooting_page_status_opcode_auto_bits status_opcode;
11641 
11642 	u8         reserved_at_40[0x20];
11643 
11644 	u8         status_message[59][0x20];
11645 };
11646 
11647 union mlx5_ifc_pddr_reg_page_data_auto_bits {
11648 	struct mlx5_ifc_pddr_troubleshooting_page_bits pddr_troubleshooting_page;
11649 	u8         reserved_at_0[0x7c0];
11650 };
11651 
11652 enum {
11653 	MLX5_PDDR_REG_PAGE_SELECT_TROUBLESHOOTING_INFO_PAGE      = 0x1,
11654 };
11655 
11656 struct mlx5_ifc_pddr_reg_bits {
11657 	u8         reserved_at_0[0x8];
11658 	u8         local_port[0x8];
11659 	u8         pnat[0x2];
11660 	u8         reserved_at_12[0xe];
11661 
11662 	u8         reserved_at_20[0x18];
11663 	u8         page_select[0x8];
11664 
11665 	union mlx5_ifc_pddr_reg_page_data_auto_bits page_data;
11666 };
11667 
11668 struct mlx5_ifc_mrtc_reg_bits {
11669 	u8         time_synced[0x1];
11670 	u8         reserved_at_1[0x1f];
11671 
11672 	u8         reserved_at_20[0x20];
11673 
11674 	u8         time_h[0x20];
11675 
11676 	u8         time_l[0x20];
11677 };
11678 
11679 struct mlx5_ifc_mtcap_reg_bits {
11680 	u8         reserved_at_0[0x19];
11681 	u8         sensor_count[0x7];
11682 
11683 	u8         reserved_at_20[0x20];
11684 
11685 	u8         sensor_map[0x40];
11686 };
11687 
11688 struct mlx5_ifc_mtmp_reg_bits {
11689 	u8         reserved_at_0[0x14];
11690 	u8         sensor_index[0xc];
11691 
11692 	u8         reserved_at_20[0x10];
11693 	u8         temperature[0x10];
11694 
11695 	u8         mte[0x1];
11696 	u8         mtr[0x1];
11697 	u8         reserved_at_42[0xe];
11698 	u8         max_temperature[0x10];
11699 
11700 	u8         tee[0x2];
11701 	u8         reserved_at_62[0xe];
11702 	u8         temp_threshold_hi[0x10];
11703 
11704 	u8         reserved_at_80[0x10];
11705 	u8         temp_threshold_lo[0x10];
11706 
11707 	u8         reserved_at_a0[0x20];
11708 
11709 	u8         sensor_name_hi[0x20];
11710 	u8         sensor_name_lo[0x20];
11711 };
11712 
11713 struct mlx5_ifc_mtptm_reg_bits {
11714 	u8         reserved_at_0[0x10];
11715 	u8         psta[0x1];
11716 	u8         reserved_at_11[0xf];
11717 
11718 	u8         reserved_at_20[0x60];
11719 };
11720 
11721 enum {
11722 	MLX5_MTCTR_REQUEST_NOP = 0x0,
11723 	MLX5_MTCTR_REQUEST_PTM_ROOT_CLOCK = 0x1,
11724 	MLX5_MTCTR_REQUEST_FREE_RUNNING_COUNTER = 0x2,
11725 	MLX5_MTCTR_REQUEST_REAL_TIME_CLOCK = 0x3,
11726 };
11727 
11728 struct mlx5_ifc_mtctr_reg_bits {
11729 	u8         first_clock_timestamp_request[0x8];
11730 	u8         second_clock_timestamp_request[0x8];
11731 	u8         reserved_at_10[0x10];
11732 
11733 	u8         first_clock_valid[0x1];
11734 	u8         second_clock_valid[0x1];
11735 	u8         reserved_at_22[0x1e];
11736 
11737 	u8         first_clock_timestamp[0x40];
11738 	u8         second_clock_timestamp[0x40];
11739 };
11740 
11741 union mlx5_ifc_ports_control_registers_document_bits {
11742 	struct mlx5_ifc_bufferx_reg_bits bufferx_reg;
11743 	struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
11744 	struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
11745 	struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
11746 	struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
11747 	struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
11748 	struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
11749 	struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout;
11750 	struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout;
11751 	struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping;
11752 	struct mlx5_ifc_pamp_reg_bits pamp_reg;
11753 	struct mlx5_ifc_paos_reg_bits paos_reg;
11754 	struct mlx5_ifc_pcap_reg_bits pcap_reg;
11755 	struct mlx5_ifc_pddr_monitor_opcode_bits pddr_monitor_opcode;
11756 	struct mlx5_ifc_pddr_reg_bits pddr_reg;
11757 	struct mlx5_ifc_pddr_troubleshooting_page_bits pddr_troubleshooting_page;
11758 	struct mlx5_ifc_peir_reg_bits peir_reg;
11759 	struct mlx5_ifc_pelc_reg_bits pelc_reg;
11760 	struct mlx5_ifc_pfcc_reg_bits pfcc_reg;
11761 	struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
11762 	struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
11763 	struct mlx5_ifc_pifr_reg_bits pifr_reg;
11764 	struct mlx5_ifc_pipg_reg_bits pipg_reg;
11765 	struct mlx5_ifc_plbf_reg_bits plbf_reg;
11766 	struct mlx5_ifc_plib_reg_bits plib_reg;
11767 	struct mlx5_ifc_plpc_reg_bits plpc_reg;
11768 	struct mlx5_ifc_pmaos_reg_bits pmaos_reg;
11769 	struct mlx5_ifc_pmlp_reg_bits pmlp_reg;
11770 	struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg;
11771 	struct mlx5_ifc_pmpc_reg_bits pmpc_reg;
11772 	struct mlx5_ifc_pmpe_reg_bits pmpe_reg;
11773 	struct mlx5_ifc_pmpr_reg_bits pmpr_reg;
11774 	struct mlx5_ifc_pmtu_reg_bits pmtu_reg;
11775 	struct mlx5_ifc_ppad_reg_bits ppad_reg;
11776 	struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg;
11777 	struct mlx5_ifc_mpein_reg_bits mpein_reg;
11778 	struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg;
11779 	struct mlx5_ifc_pplm_reg_bits pplm_reg;
11780 	struct mlx5_ifc_pplr_reg_bits pplr_reg;
11781 	struct mlx5_ifc_ppsc_reg_bits ppsc_reg;
11782 	struct mlx5_ifc_pqdr_reg_bits pqdr_reg;
11783 	struct mlx5_ifc_pspa_reg_bits pspa_reg;
11784 	struct mlx5_ifc_ptas_reg_bits ptas_reg;
11785 	struct mlx5_ifc_ptys_reg_bits ptys_reg;
11786 	struct mlx5_ifc_mlcr_reg_bits mlcr_reg;
11787 	struct mlx5_ifc_pude_reg_bits pude_reg;
11788 	struct mlx5_ifc_pvlc_reg_bits pvlc_reg;
11789 	struct mlx5_ifc_slrg_reg_bits slrg_reg;
11790 	struct mlx5_ifc_sltp_reg_bits sltp_reg;
11791 	struct mlx5_ifc_mtpps_reg_bits mtpps_reg;
11792 	struct mlx5_ifc_mtppse_reg_bits mtppse_reg;
11793 	struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg;
11794 	struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits;
11795 	struct mlx5_ifc_fpga_cap_bits fpga_cap_bits;
11796 	struct mlx5_ifc_mcqi_reg_bits mcqi_reg;
11797 	struct mlx5_ifc_mcc_reg_bits mcc_reg;
11798 	struct mlx5_ifc_mcda_reg_bits mcda_reg;
11799 	struct mlx5_ifc_mirc_reg_bits mirc_reg;
11800 	struct mlx5_ifc_mfrl_reg_bits mfrl_reg;
11801 	struct mlx5_ifc_mtutc_reg_bits mtutc_reg;
11802 	struct mlx5_ifc_mrtc_reg_bits mrtc_reg;
11803 	struct mlx5_ifc_mtcap_reg_bits mtcap_reg;
11804 	struct mlx5_ifc_mtmp_reg_bits mtmp_reg;
11805 	struct mlx5_ifc_mtptm_reg_bits mtptm_reg;
11806 	struct mlx5_ifc_mtctr_reg_bits mtctr_reg;
11807 	u8         reserved_at_0[0x60e0];
11808 };
11809 
11810 union mlx5_ifc_debug_enhancements_document_bits {
11811 	struct mlx5_ifc_health_buffer_bits health_buffer;
11812 	u8         reserved_at_0[0x200];
11813 };
11814 
11815 union mlx5_ifc_uplink_pci_interface_document_bits {
11816 	struct mlx5_ifc_initial_seg_bits initial_seg;
11817 	u8         reserved_at_0[0x20060];
11818 };
11819 
11820 struct mlx5_ifc_set_flow_table_root_out_bits {
11821 	u8         status[0x8];
11822 	u8         reserved_at_8[0x18];
11823 
11824 	u8         syndrome[0x20];
11825 
11826 	u8         reserved_at_40[0x40];
11827 };
11828 
11829 struct mlx5_ifc_set_flow_table_root_in_bits {
11830 	u8         opcode[0x10];
11831 	u8         reserved_at_10[0x10];
11832 
11833 	u8         reserved_at_20[0x10];
11834 	u8         op_mod[0x10];
11835 
11836 	u8         other_vport[0x1];
11837 	u8         reserved_at_41[0xf];
11838 	u8         vport_number[0x10];
11839 
11840 	u8         reserved_at_60[0x20];
11841 
11842 	u8         table_type[0x8];
11843 	u8         reserved_at_88[0x7];
11844 	u8         table_of_other_vport[0x1];
11845 	u8         table_vport_number[0x10];
11846 
11847 	u8         reserved_at_a0[0x8];
11848 	u8         table_id[0x18];
11849 
11850 	u8         reserved_at_c0[0x8];
11851 	u8         underlay_qpn[0x18];
11852 	u8         table_eswitch_owner_vhca_id_valid[0x1];
11853 	u8         reserved_at_e1[0xf];
11854 	u8         table_eswitch_owner_vhca_id[0x10];
11855 	u8         reserved_at_100[0x100];
11856 };
11857 
11858 enum {
11859 	MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID     = (1UL << 0),
11860 	MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15),
11861 };
11862 
11863 struct mlx5_ifc_modify_flow_table_out_bits {
11864 	u8         status[0x8];
11865 	u8         reserved_at_8[0x18];
11866 
11867 	u8         syndrome[0x20];
11868 
11869 	u8         reserved_at_40[0x40];
11870 };
11871 
11872 struct mlx5_ifc_modify_flow_table_in_bits {
11873 	u8         opcode[0x10];
11874 	u8         reserved_at_10[0x10];
11875 
11876 	u8         reserved_at_20[0x10];
11877 	u8         op_mod[0x10];
11878 
11879 	u8         other_vport[0x1];
11880 	u8         reserved_at_41[0xf];
11881 	u8         vport_number[0x10];
11882 
11883 	u8         reserved_at_60[0x10];
11884 	u8         modify_field_select[0x10];
11885 
11886 	u8         table_type[0x8];
11887 	u8         reserved_at_88[0x18];
11888 
11889 	u8         reserved_at_a0[0x8];
11890 	u8         table_id[0x18];
11891 
11892 	struct mlx5_ifc_flow_table_context_bits flow_table_context;
11893 };
11894 
11895 struct mlx5_ifc_ets_tcn_config_reg_bits {
11896 	u8         g[0x1];
11897 	u8         b[0x1];
11898 	u8         r[0x1];
11899 	u8         reserved_at_3[0x9];
11900 	u8         group[0x4];
11901 	u8         reserved_at_10[0x9];
11902 	u8         bw_allocation[0x7];
11903 
11904 	u8         reserved_at_20[0xc];
11905 	u8         max_bw_units[0x4];
11906 	u8         reserved_at_30[0x8];
11907 	u8         max_bw_value[0x8];
11908 };
11909 
11910 struct mlx5_ifc_ets_global_config_reg_bits {
11911 	u8         reserved_at_0[0x2];
11912 	u8         r[0x1];
11913 	u8         reserved_at_3[0x1d];
11914 
11915 	u8         reserved_at_20[0xc];
11916 	u8         max_bw_units[0x4];
11917 	u8         reserved_at_30[0x8];
11918 	u8         max_bw_value[0x8];
11919 };
11920 
11921 struct mlx5_ifc_qetc_reg_bits {
11922 	u8                                         reserved_at_0[0x8];
11923 	u8                                         port_number[0x8];
11924 	u8                                         reserved_at_10[0x30];
11925 
11926 	struct mlx5_ifc_ets_tcn_config_reg_bits    tc_configuration[0x8];
11927 	struct mlx5_ifc_ets_global_config_reg_bits global_configuration;
11928 };
11929 
11930 struct mlx5_ifc_qpdpm_dscp_reg_bits {
11931 	u8         e[0x1];
11932 	u8         reserved_at_01[0x0b];
11933 	u8         prio[0x04];
11934 };
11935 
11936 struct mlx5_ifc_qpdpm_reg_bits {
11937 	u8                                     reserved_at_0[0x8];
11938 	u8                                     local_port[0x8];
11939 	u8                                     reserved_at_10[0x10];
11940 	struct mlx5_ifc_qpdpm_dscp_reg_bits    dscp[64];
11941 };
11942 
11943 struct mlx5_ifc_qpts_reg_bits {
11944 	u8         reserved_at_0[0x8];
11945 	u8         local_port[0x8];
11946 	u8         reserved_at_10[0x2d];
11947 	u8         trust_state[0x3];
11948 };
11949 
11950 struct mlx5_ifc_pptb_reg_bits {
11951 	u8         reserved_at_0[0x2];
11952 	u8         mm[0x2];
11953 	u8         reserved_at_4[0x4];
11954 	u8         local_port[0x8];
11955 	u8         reserved_at_10[0x6];
11956 	u8         cm[0x1];
11957 	u8         um[0x1];
11958 	u8         pm[0x8];
11959 
11960 	u8         prio_x_buff[0x20];
11961 
11962 	u8         pm_msb[0x8];
11963 	u8         reserved_at_48[0x10];
11964 	u8         ctrl_buff[0x4];
11965 	u8         untagged_buff[0x4];
11966 };
11967 
11968 struct mlx5_ifc_sbcam_reg_bits {
11969 	u8         reserved_at_0[0x8];
11970 	u8         feature_group[0x8];
11971 	u8         reserved_at_10[0x8];
11972 	u8         access_reg_group[0x8];
11973 
11974 	u8         reserved_at_20[0x20];
11975 
11976 	u8         sb_access_reg_cap_mask[4][0x20];
11977 
11978 	u8         reserved_at_c0[0x80];
11979 
11980 	u8         sb_feature_cap_mask[4][0x20];
11981 
11982 	u8         reserved_at_1c0[0x40];
11983 
11984 	u8         cap_total_buffer_size[0x20];
11985 
11986 	u8         cap_cell_size[0x10];
11987 	u8         cap_max_pg_buffers[0x8];
11988 	u8         cap_num_pool_supported[0x8];
11989 
11990 	u8         reserved_at_240[0x8];
11991 	u8         cap_sbsr_stat_size[0x8];
11992 	u8         cap_max_tclass_data[0x8];
11993 	u8         cap_max_cpu_ingress_tclass_sb[0x8];
11994 };
11995 
11996 struct mlx5_ifc_pbmc_reg_bits {
11997 	u8         reserved_at_0[0x8];
11998 	u8         local_port[0x8];
11999 	u8         reserved_at_10[0x10];
12000 
12001 	u8         xoff_timer_value[0x10];
12002 	u8         xoff_refresh[0x10];
12003 
12004 	u8         reserved_at_40[0x9];
12005 	u8         fullness_threshold[0x7];
12006 	u8         port_buffer_size[0x10];
12007 
12008 	struct mlx5_ifc_bufferx_reg_bits buffer[10];
12009 
12010 	u8         reserved_at_2e0[0x80];
12011 };
12012 
12013 struct mlx5_ifc_sbpr_reg_bits {
12014 	u8         desc[0x1];
12015 	u8         snap[0x1];
12016 	u8         reserved_at_2[0x4];
12017 	u8         dir[0x2];
12018 	u8         reserved_at_8[0x14];
12019 	u8         pool[0x4];
12020 
12021 	u8         infi_size[0x1];
12022 	u8         reserved_at_21[0x7];
12023 	u8         size[0x18];
12024 
12025 	u8         reserved_at_40[0x1c];
12026 	u8         mode[0x4];
12027 
12028 	u8         reserved_at_60[0x8];
12029 	u8         buff_occupancy[0x18];
12030 
12031 	u8         clr[0x1];
12032 	u8         reserved_at_81[0x7];
12033 	u8         max_buff_occupancy[0x18];
12034 
12035 	u8         reserved_at_a0[0x8];
12036 	u8         ext_buff_occupancy[0x18];
12037 };
12038 
12039 struct mlx5_ifc_sbcm_reg_bits {
12040 	u8         desc[0x1];
12041 	u8         snap[0x1];
12042 	u8         reserved_at_2[0x6];
12043 	u8         local_port[0x8];
12044 	u8         pnat[0x2];
12045 	u8         pg_buff[0x6];
12046 	u8         reserved_at_18[0x6];
12047 	u8         dir[0x2];
12048 
12049 	u8         reserved_at_20[0x1f];
12050 	u8         exc[0x1];
12051 
12052 	u8         reserved_at_40[0x40];
12053 
12054 	u8         reserved_at_80[0x8];
12055 	u8         buff_occupancy[0x18];
12056 
12057 	u8         clr[0x1];
12058 	u8         reserved_at_a1[0x7];
12059 	u8         max_buff_occupancy[0x18];
12060 
12061 	u8         reserved_at_c0[0x8];
12062 	u8         min_buff[0x18];
12063 
12064 	u8         infi_max[0x1];
12065 	u8         reserved_at_e1[0x7];
12066 	u8         max_buff[0x18];
12067 
12068 	u8         reserved_at_100[0x20];
12069 
12070 	u8         reserved_at_120[0x1c];
12071 	u8         pool[0x4];
12072 };
12073 
12074 struct mlx5_ifc_qtct_reg_bits {
12075 	u8         reserved_at_0[0x8];
12076 	u8         port_number[0x8];
12077 	u8         reserved_at_10[0xd];
12078 	u8         prio[0x3];
12079 
12080 	u8         reserved_at_20[0x1d];
12081 	u8         tclass[0x3];
12082 };
12083 
12084 struct mlx5_ifc_mcia_reg_bits {
12085 	u8         l[0x1];
12086 	u8         reserved_at_1[0x7];
12087 	u8         module[0x8];
12088 	u8         reserved_at_10[0x8];
12089 	u8         status[0x8];
12090 
12091 	u8         i2c_device_address[0x8];
12092 	u8         page_number[0x8];
12093 	u8         device_address[0x10];
12094 
12095 	u8         reserved_at_40[0x10];
12096 	u8         size[0x10];
12097 
12098 	u8         reserved_at_60[0x20];
12099 
12100 	u8         dword_0[0x20];
12101 	u8         dword_1[0x20];
12102 	u8         dword_2[0x20];
12103 	u8         dword_3[0x20];
12104 	u8         dword_4[0x20];
12105 	u8         dword_5[0x20];
12106 	u8         dword_6[0x20];
12107 	u8         dword_7[0x20];
12108 	u8         dword_8[0x20];
12109 	u8         dword_9[0x20];
12110 	u8         dword_10[0x20];
12111 	u8         dword_11[0x20];
12112 };
12113 
12114 struct mlx5_ifc_dcbx_param_bits {
12115 	u8         dcbx_cee_cap[0x1];
12116 	u8         dcbx_ieee_cap[0x1];
12117 	u8         dcbx_standby_cap[0x1];
12118 	u8         reserved_at_3[0x5];
12119 	u8         port_number[0x8];
12120 	u8         reserved_at_10[0xa];
12121 	u8         max_application_table_size[6];
12122 	u8         reserved_at_20[0x15];
12123 	u8         version_oper[0x3];
12124 	u8         reserved_at_38[5];
12125 	u8         version_admin[0x3];
12126 	u8         willing_admin[0x1];
12127 	u8         reserved_at_41[0x3];
12128 	u8         pfc_cap_oper[0x4];
12129 	u8         reserved_at_48[0x4];
12130 	u8         pfc_cap_admin[0x4];
12131 	u8         reserved_at_50[0x4];
12132 	u8         num_of_tc_oper[0x4];
12133 	u8         reserved_at_58[0x4];
12134 	u8         num_of_tc_admin[0x4];
12135 	u8         remote_willing[0x1];
12136 	u8         reserved_at_61[3];
12137 	u8         remote_pfc_cap[4];
12138 	u8         reserved_at_68[0x14];
12139 	u8         remote_num_of_tc[0x4];
12140 	u8         reserved_at_80[0x18];
12141 	u8         error[0x8];
12142 	u8         reserved_at_a0[0x160];
12143 };
12144 
12145 enum {
12146 	MLX5_LAG_PORT_SELECT_MODE_QUEUE_AFFINITY = 0,
12147 	MLX5_LAG_PORT_SELECT_MODE_PORT_SELECT_FT = 1,
12148 	MLX5_LAG_PORT_SELECT_MODE_PORT_SELECT_MPESW = 2,
12149 };
12150 
12151 struct mlx5_ifc_lagc_bits {
12152 	u8         fdb_selection_mode[0x1];
12153 	u8         reserved_at_1[0x14];
12154 	u8         port_select_mode[0x3];
12155 	u8         reserved_at_18[0x5];
12156 	u8         lag_state[0x3];
12157 
12158 	u8         reserved_at_20[0xc];
12159 	u8         active_port[0x4];
12160 	u8         reserved_at_30[0x4];
12161 	u8         tx_remap_affinity_2[0x4];
12162 	u8         reserved_at_38[0x4];
12163 	u8         tx_remap_affinity_1[0x4];
12164 };
12165 
12166 struct mlx5_ifc_create_lag_out_bits {
12167 	u8         status[0x8];
12168 	u8         reserved_at_8[0x18];
12169 
12170 	u8         syndrome[0x20];
12171 
12172 	u8         reserved_at_40[0x40];
12173 };
12174 
12175 struct mlx5_ifc_create_lag_in_bits {
12176 	u8         opcode[0x10];
12177 	u8         reserved_at_10[0x10];
12178 
12179 	u8         reserved_at_20[0x10];
12180 	u8         op_mod[0x10];
12181 
12182 	struct mlx5_ifc_lagc_bits ctx;
12183 };
12184 
12185 struct mlx5_ifc_modify_lag_out_bits {
12186 	u8         status[0x8];
12187 	u8         reserved_at_8[0x18];
12188 
12189 	u8         syndrome[0x20];
12190 
12191 	u8         reserved_at_40[0x40];
12192 };
12193 
12194 struct mlx5_ifc_modify_lag_in_bits {
12195 	u8         opcode[0x10];
12196 	u8         reserved_at_10[0x10];
12197 
12198 	u8         reserved_at_20[0x10];
12199 	u8         op_mod[0x10];
12200 
12201 	u8         reserved_at_40[0x20];
12202 	u8         field_select[0x20];
12203 
12204 	struct mlx5_ifc_lagc_bits ctx;
12205 };
12206 
12207 struct mlx5_ifc_query_lag_out_bits {
12208 	u8         status[0x8];
12209 	u8         reserved_at_8[0x18];
12210 
12211 	u8         syndrome[0x20];
12212 
12213 	struct mlx5_ifc_lagc_bits ctx;
12214 };
12215 
12216 struct mlx5_ifc_query_lag_in_bits {
12217 	u8         opcode[0x10];
12218 	u8         reserved_at_10[0x10];
12219 
12220 	u8         reserved_at_20[0x10];
12221 	u8         op_mod[0x10];
12222 
12223 	u8         reserved_at_40[0x40];
12224 };
12225 
12226 struct mlx5_ifc_destroy_lag_out_bits {
12227 	u8         status[0x8];
12228 	u8         reserved_at_8[0x18];
12229 
12230 	u8         syndrome[0x20];
12231 
12232 	u8         reserved_at_40[0x40];
12233 };
12234 
12235 struct mlx5_ifc_destroy_lag_in_bits {
12236 	u8         opcode[0x10];
12237 	u8         reserved_at_10[0x10];
12238 
12239 	u8         reserved_at_20[0x10];
12240 	u8         op_mod[0x10];
12241 
12242 	u8         reserved_at_40[0x40];
12243 };
12244 
12245 struct mlx5_ifc_create_vport_lag_out_bits {
12246 	u8         status[0x8];
12247 	u8         reserved_at_8[0x18];
12248 
12249 	u8         syndrome[0x20];
12250 
12251 	u8         reserved_at_40[0x40];
12252 };
12253 
12254 struct mlx5_ifc_create_vport_lag_in_bits {
12255 	u8         opcode[0x10];
12256 	u8         reserved_at_10[0x10];
12257 
12258 	u8         reserved_at_20[0x10];
12259 	u8         op_mod[0x10];
12260 
12261 	u8         reserved_at_40[0x40];
12262 };
12263 
12264 struct mlx5_ifc_destroy_vport_lag_out_bits {
12265 	u8         status[0x8];
12266 	u8         reserved_at_8[0x18];
12267 
12268 	u8         syndrome[0x20];
12269 
12270 	u8         reserved_at_40[0x40];
12271 };
12272 
12273 struct mlx5_ifc_destroy_vport_lag_in_bits {
12274 	u8         opcode[0x10];
12275 	u8         reserved_at_10[0x10];
12276 
12277 	u8         reserved_at_20[0x10];
12278 	u8         op_mod[0x10];
12279 
12280 	u8         reserved_at_40[0x40];
12281 };
12282 
12283 enum {
12284 	MLX5_MODIFY_MEMIC_OP_MOD_ALLOC,
12285 	MLX5_MODIFY_MEMIC_OP_MOD_DEALLOC,
12286 };
12287 
12288 struct mlx5_ifc_modify_memic_in_bits {
12289 	u8         opcode[0x10];
12290 	u8         uid[0x10];
12291 
12292 	u8         reserved_at_20[0x10];
12293 	u8         op_mod[0x10];
12294 
12295 	u8         reserved_at_40[0x20];
12296 
12297 	u8         reserved_at_60[0x18];
12298 	u8         memic_operation_type[0x8];
12299 
12300 	u8         memic_start_addr[0x40];
12301 
12302 	u8         reserved_at_c0[0x140];
12303 };
12304 
12305 struct mlx5_ifc_modify_memic_out_bits {
12306 	u8         status[0x8];
12307 	u8         reserved_at_8[0x18];
12308 
12309 	u8         syndrome[0x20];
12310 
12311 	u8         reserved_at_40[0x40];
12312 
12313 	u8         memic_operation_addr[0x40];
12314 
12315 	u8         reserved_at_c0[0x140];
12316 };
12317 
12318 struct mlx5_ifc_alloc_memic_in_bits {
12319 	u8         opcode[0x10];
12320 	u8         reserved_at_10[0x10];
12321 
12322 	u8         reserved_at_20[0x10];
12323 	u8         op_mod[0x10];
12324 
12325 	u8         reserved_at_30[0x20];
12326 
12327 	u8	   reserved_at_40[0x18];
12328 	u8	   log_memic_addr_alignment[0x8];
12329 
12330 	u8         range_start_addr[0x40];
12331 
12332 	u8         range_size[0x20];
12333 
12334 	u8         memic_size[0x20];
12335 };
12336 
12337 struct mlx5_ifc_alloc_memic_out_bits {
12338 	u8         status[0x8];
12339 	u8         reserved_at_8[0x18];
12340 
12341 	u8         syndrome[0x20];
12342 
12343 	u8         memic_start_addr[0x40];
12344 };
12345 
12346 struct mlx5_ifc_dealloc_memic_in_bits {
12347 	u8         opcode[0x10];
12348 	u8         reserved_at_10[0x10];
12349 
12350 	u8         reserved_at_20[0x10];
12351 	u8         op_mod[0x10];
12352 
12353 	u8         reserved_at_40[0x40];
12354 
12355 	u8         memic_start_addr[0x40];
12356 
12357 	u8         memic_size[0x20];
12358 
12359 	u8         reserved_at_e0[0x20];
12360 };
12361 
12362 struct mlx5_ifc_dealloc_memic_out_bits {
12363 	u8         status[0x8];
12364 	u8         reserved_at_8[0x18];
12365 
12366 	u8         syndrome[0x20];
12367 
12368 	u8         reserved_at_40[0x40];
12369 };
12370 
12371 struct mlx5_ifc_umem_bits {
12372 	u8         reserved_at_0[0x80];
12373 
12374 	u8         ats[0x1];
12375 	u8         reserved_at_81[0x1a];
12376 	u8         log_page_size[0x5];
12377 
12378 	u8         page_offset[0x20];
12379 
12380 	u8         num_of_mtt[0x40];
12381 
12382 	struct mlx5_ifc_mtt_bits  mtt[];
12383 };
12384 
12385 struct mlx5_ifc_uctx_bits {
12386 	u8         cap[0x20];
12387 
12388 	u8         reserved_at_20[0x160];
12389 };
12390 
12391 struct mlx5_ifc_sw_icm_bits {
12392 	u8         modify_field_select[0x40];
12393 
12394 	u8	   reserved_at_40[0x18];
12395 	u8         log_sw_icm_size[0x8];
12396 
12397 	u8         reserved_at_60[0x20];
12398 
12399 	u8         sw_icm_start_addr[0x40];
12400 
12401 	u8         reserved_at_c0[0x140];
12402 };
12403 
12404 struct mlx5_ifc_geneve_tlv_option_bits {
12405 	u8         modify_field_select[0x40];
12406 
12407 	u8         reserved_at_40[0x18];
12408 	u8         geneve_option_fte_index[0x8];
12409 
12410 	u8         option_class[0x10];
12411 	u8         option_type[0x8];
12412 	u8         reserved_at_78[0x3];
12413 	u8         option_data_length[0x5];
12414 
12415 	u8         reserved_at_80[0x180];
12416 };
12417 
12418 struct mlx5_ifc_create_umem_in_bits {
12419 	u8         opcode[0x10];
12420 	u8         uid[0x10];
12421 
12422 	u8         reserved_at_20[0x10];
12423 	u8         op_mod[0x10];
12424 
12425 	u8         reserved_at_40[0x40];
12426 
12427 	struct mlx5_ifc_umem_bits  umem;
12428 };
12429 
12430 struct mlx5_ifc_create_umem_out_bits {
12431 	u8         status[0x8];
12432 	u8         reserved_at_8[0x18];
12433 
12434 	u8         syndrome[0x20];
12435 
12436 	u8         reserved_at_40[0x8];
12437 	u8         umem_id[0x18];
12438 
12439 	u8         reserved_at_60[0x20];
12440 };
12441 
12442 struct mlx5_ifc_destroy_umem_in_bits {
12443 	u8        opcode[0x10];
12444 	u8        uid[0x10];
12445 
12446 	u8        reserved_at_20[0x10];
12447 	u8        op_mod[0x10];
12448 
12449 	u8        reserved_at_40[0x8];
12450 	u8        umem_id[0x18];
12451 
12452 	u8        reserved_at_60[0x20];
12453 };
12454 
12455 struct mlx5_ifc_destroy_umem_out_bits {
12456 	u8        status[0x8];
12457 	u8        reserved_at_8[0x18];
12458 
12459 	u8        syndrome[0x20];
12460 
12461 	u8        reserved_at_40[0x40];
12462 };
12463 
12464 struct mlx5_ifc_create_uctx_in_bits {
12465 	u8         opcode[0x10];
12466 	u8         reserved_at_10[0x10];
12467 
12468 	u8         reserved_at_20[0x10];
12469 	u8         op_mod[0x10];
12470 
12471 	u8         reserved_at_40[0x40];
12472 
12473 	struct mlx5_ifc_uctx_bits  uctx;
12474 };
12475 
12476 struct mlx5_ifc_create_uctx_out_bits {
12477 	u8         status[0x8];
12478 	u8         reserved_at_8[0x18];
12479 
12480 	u8         syndrome[0x20];
12481 
12482 	u8         reserved_at_40[0x10];
12483 	u8         uid[0x10];
12484 
12485 	u8         reserved_at_60[0x20];
12486 };
12487 
12488 struct mlx5_ifc_destroy_uctx_in_bits {
12489 	u8         opcode[0x10];
12490 	u8         reserved_at_10[0x10];
12491 
12492 	u8         reserved_at_20[0x10];
12493 	u8         op_mod[0x10];
12494 
12495 	u8         reserved_at_40[0x10];
12496 	u8         uid[0x10];
12497 
12498 	u8         reserved_at_60[0x20];
12499 };
12500 
12501 struct mlx5_ifc_destroy_uctx_out_bits {
12502 	u8         status[0x8];
12503 	u8         reserved_at_8[0x18];
12504 
12505 	u8         syndrome[0x20];
12506 
12507 	u8          reserved_at_40[0x40];
12508 };
12509 
12510 struct mlx5_ifc_create_sw_icm_in_bits {
12511 	struct mlx5_ifc_general_obj_in_cmd_hdr_bits   hdr;
12512 	struct mlx5_ifc_sw_icm_bits		      sw_icm;
12513 };
12514 
12515 struct mlx5_ifc_create_geneve_tlv_option_in_bits {
12516 	struct mlx5_ifc_general_obj_in_cmd_hdr_bits   hdr;
12517 	struct mlx5_ifc_geneve_tlv_option_bits        geneve_tlv_opt;
12518 };
12519 
12520 struct mlx5_ifc_mtrc_string_db_param_bits {
12521 	u8         string_db_base_address[0x20];
12522 
12523 	u8         reserved_at_20[0x8];
12524 	u8         string_db_size[0x18];
12525 };
12526 
12527 struct mlx5_ifc_mtrc_cap_bits {
12528 	u8         trace_owner[0x1];
12529 	u8         trace_to_memory[0x1];
12530 	u8         reserved_at_2[0x4];
12531 	u8         trc_ver[0x2];
12532 	u8         reserved_at_8[0x14];
12533 	u8         num_string_db[0x4];
12534 
12535 	u8         first_string_trace[0x8];
12536 	u8         num_string_trace[0x8];
12537 	u8         reserved_at_30[0x28];
12538 
12539 	u8         log_max_trace_buffer_size[0x8];
12540 
12541 	u8         reserved_at_60[0x20];
12542 
12543 	struct mlx5_ifc_mtrc_string_db_param_bits string_db_param[8];
12544 
12545 	u8         reserved_at_280[0x180];
12546 };
12547 
12548 struct mlx5_ifc_mtrc_conf_bits {
12549 	u8         reserved_at_0[0x1c];
12550 	u8         trace_mode[0x4];
12551 	u8         reserved_at_20[0x18];
12552 	u8         log_trace_buffer_size[0x8];
12553 	u8         trace_mkey[0x20];
12554 	u8         reserved_at_60[0x3a0];
12555 };
12556 
12557 struct mlx5_ifc_mtrc_stdb_bits {
12558 	u8         string_db_index[0x4];
12559 	u8         reserved_at_4[0x4];
12560 	u8         read_size[0x18];
12561 	u8         start_offset[0x20];
12562 	u8         string_db_data[];
12563 };
12564 
12565 struct mlx5_ifc_mtrc_ctrl_bits {
12566 	u8         trace_status[0x2];
12567 	u8         reserved_at_2[0x2];
12568 	u8         arm_event[0x1];
12569 	u8         reserved_at_5[0xb];
12570 	u8         modify_field_select[0x10];
12571 	u8         reserved_at_20[0x2b];
12572 	u8         current_timestamp52_32[0x15];
12573 	u8         current_timestamp31_0[0x20];
12574 	u8         reserved_at_80[0x180];
12575 };
12576 
12577 struct mlx5_ifc_host_params_context_bits {
12578 	u8         host_number[0x8];
12579 	u8         reserved_at_8[0x5];
12580 	u8         host_pf_not_exist[0x1];
12581 	u8         reserved_at_14[0x1];
12582 	u8         host_pf_disabled[0x1];
12583 	u8         host_num_of_vfs[0x10];
12584 
12585 	u8         host_total_vfs[0x10];
12586 	u8         host_pci_bus[0x10];
12587 
12588 	u8         reserved_at_40[0x10];
12589 	u8         host_pci_device[0x10];
12590 
12591 	u8         reserved_at_60[0x10];
12592 	u8         host_pci_function[0x10];
12593 
12594 	u8         reserved_at_80[0x180];
12595 };
12596 
12597 struct mlx5_ifc_query_esw_functions_in_bits {
12598 	u8         opcode[0x10];
12599 	u8         reserved_at_10[0x10];
12600 
12601 	u8         reserved_at_20[0x10];
12602 	u8         op_mod[0x10];
12603 
12604 	u8         reserved_at_40[0x40];
12605 };
12606 
12607 struct mlx5_ifc_query_esw_functions_out_bits {
12608 	u8         status[0x8];
12609 	u8         reserved_at_8[0x18];
12610 
12611 	u8         syndrome[0x20];
12612 
12613 	u8         reserved_at_40[0x40];
12614 
12615 	struct mlx5_ifc_host_params_context_bits host_params_context;
12616 
12617 	u8         reserved_at_280[0x180];
12618 	u8         host_sf_enable[][0x40];
12619 };
12620 
12621 struct mlx5_ifc_sf_partition_bits {
12622 	u8         reserved_at_0[0x10];
12623 	u8         log_num_sf[0x8];
12624 	u8         log_sf_bar_size[0x8];
12625 };
12626 
12627 struct mlx5_ifc_query_sf_partitions_out_bits {
12628 	u8         status[0x8];
12629 	u8         reserved_at_8[0x18];
12630 
12631 	u8         syndrome[0x20];
12632 
12633 	u8         reserved_at_40[0x18];
12634 	u8         num_sf_partitions[0x8];
12635 
12636 	u8         reserved_at_60[0x20];
12637 
12638 	struct mlx5_ifc_sf_partition_bits sf_partition[];
12639 };
12640 
12641 struct mlx5_ifc_query_sf_partitions_in_bits {
12642 	u8         opcode[0x10];
12643 	u8         reserved_at_10[0x10];
12644 
12645 	u8         reserved_at_20[0x10];
12646 	u8         op_mod[0x10];
12647 
12648 	u8         reserved_at_40[0x40];
12649 };
12650 
12651 struct mlx5_ifc_dealloc_sf_out_bits {
12652 	u8         status[0x8];
12653 	u8         reserved_at_8[0x18];
12654 
12655 	u8         syndrome[0x20];
12656 
12657 	u8         reserved_at_40[0x40];
12658 };
12659 
12660 struct mlx5_ifc_dealloc_sf_in_bits {
12661 	u8         opcode[0x10];
12662 	u8         reserved_at_10[0x10];
12663 
12664 	u8         reserved_at_20[0x10];
12665 	u8         op_mod[0x10];
12666 
12667 	u8         reserved_at_40[0x10];
12668 	u8         function_id[0x10];
12669 
12670 	u8         reserved_at_60[0x20];
12671 };
12672 
12673 struct mlx5_ifc_alloc_sf_out_bits {
12674 	u8         status[0x8];
12675 	u8         reserved_at_8[0x18];
12676 
12677 	u8         syndrome[0x20];
12678 
12679 	u8         reserved_at_40[0x40];
12680 };
12681 
12682 struct mlx5_ifc_alloc_sf_in_bits {
12683 	u8         opcode[0x10];
12684 	u8         reserved_at_10[0x10];
12685 
12686 	u8         reserved_at_20[0x10];
12687 	u8         op_mod[0x10];
12688 
12689 	u8         reserved_at_40[0x10];
12690 	u8         function_id[0x10];
12691 
12692 	u8         reserved_at_60[0x20];
12693 };
12694 
12695 struct mlx5_ifc_affiliated_event_header_bits {
12696 	u8         reserved_at_0[0x10];
12697 	u8         obj_type[0x10];
12698 
12699 	u8         obj_id[0x20];
12700 };
12701 
12702 enum {
12703 	MLX5_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = 0xc,
12704 	MLX5_GENERAL_OBJECT_TYPES_IPSEC = 0x13,
12705 	MLX5_GENERAL_OBJECT_TYPES_SAMPLER = 0x20,
12706 	MLX5_GENERAL_OBJECT_TYPES_FLOW_METER_ASO = 0x24,
12707 	MLX5_GENERAL_OBJECT_TYPES_MACSEC = 0x27,
12708 	MLX5_GENERAL_OBJECT_TYPES_INT_KEK = 0x47,
12709 	MLX5_GENERAL_OBJECT_TYPES_RDMA_CTRL = 0x53,
12710 	MLX5_GENERAL_OBJECT_TYPES_PCIE_CONG_EVENT = 0x58,
12711 	MLX5_GENERAL_OBJECT_TYPES_FLOW_TABLE_ALIAS = 0xff15,
12712 };
12713 
12714 enum {
12715 	MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY =
12716 		BIT_ULL(MLX5_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY),
12717 	MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_IPSEC =
12718 		BIT_ULL(MLX5_GENERAL_OBJECT_TYPES_IPSEC),
12719 	MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_SAMPLER =
12720 		BIT_ULL(MLX5_GENERAL_OBJECT_TYPES_SAMPLER),
12721 	MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_FLOW_METER_ASO =
12722 		BIT_ULL(MLX5_GENERAL_OBJECT_TYPES_FLOW_METER_ASO),
12723 };
12724 
12725 enum {
12726 	MLX5_HCA_CAP_2_GENERAL_OBJECT_TYPES_RDMA_CTRL =
12727 		BIT_ULL(MLX5_GENERAL_OBJECT_TYPES_RDMA_CTRL - 0x40),
12728 	MLX5_HCA_CAP_2_GENERAL_OBJECT_TYPES_PCIE_CONG_EVENT =
12729 		BIT_ULL(MLX5_GENERAL_OBJECT_TYPES_PCIE_CONG_EVENT - 0x40),
12730 };
12731 
12732 enum {
12733 	MLX5_IPSEC_OBJECT_ICV_LEN_16B,
12734 };
12735 
12736 enum {
12737 	MLX5_IPSEC_ASO_REG_C_0_1 = 0x0,
12738 	MLX5_IPSEC_ASO_REG_C_2_3 = 0x1,
12739 	MLX5_IPSEC_ASO_REG_C_4_5 = 0x2,
12740 	MLX5_IPSEC_ASO_REG_C_6_7 = 0x3,
12741 };
12742 
12743 enum {
12744 	MLX5_IPSEC_ASO_MODE              = 0x0,
12745 	MLX5_IPSEC_ASO_REPLAY_PROTECTION = 0x1,
12746 	MLX5_IPSEC_ASO_INC_SN            = 0x2,
12747 };
12748 
12749 enum {
12750 	MLX5_IPSEC_ASO_REPLAY_WIN_32BIT  = 0x0,
12751 	MLX5_IPSEC_ASO_REPLAY_WIN_64BIT  = 0x1,
12752 	MLX5_IPSEC_ASO_REPLAY_WIN_128BIT = 0x2,
12753 	MLX5_IPSEC_ASO_REPLAY_WIN_256BIT = 0x3,
12754 };
12755 
12756 struct mlx5_ifc_ipsec_aso_bits {
12757 	u8         valid[0x1];
12758 	u8         reserved_at_201[0x1];
12759 	u8         mode[0x2];
12760 	u8         window_sz[0x2];
12761 	u8         soft_lft_arm[0x1];
12762 	u8         hard_lft_arm[0x1];
12763 	u8         remove_flow_enable[0x1];
12764 	u8         esn_event_arm[0x1];
12765 	u8         reserved_at_20a[0x16];
12766 
12767 	u8         remove_flow_pkt_cnt[0x20];
12768 
12769 	u8         remove_flow_soft_lft[0x20];
12770 
12771 	u8         reserved_at_260[0x80];
12772 
12773 	u8         mode_parameter[0x20];
12774 
12775 	u8         replay_protection_window[0x100];
12776 };
12777 
12778 struct mlx5_ifc_ipsec_obj_bits {
12779 	u8         modify_field_select[0x40];
12780 	u8         full_offload[0x1];
12781 	u8         reserved_at_41[0x1];
12782 	u8         esn_en[0x1];
12783 	u8         esn_overlap[0x1];
12784 	u8         reserved_at_44[0x2];
12785 	u8         icv_length[0x2];
12786 	u8         reserved_at_48[0x4];
12787 	u8         aso_return_reg[0x4];
12788 	u8         reserved_at_50[0x10];
12789 
12790 	u8         esn_msb[0x20];
12791 
12792 	u8         reserved_at_80[0x8];
12793 	u8         dekn[0x18];
12794 
12795 	u8         salt[0x20];
12796 
12797 	u8         implicit_iv[0x40];
12798 
12799 	u8         reserved_at_100[0x8];
12800 	u8         ipsec_aso_access_pd[0x18];
12801 	u8         reserved_at_120[0xe0];
12802 
12803 	struct mlx5_ifc_ipsec_aso_bits ipsec_aso;
12804 };
12805 
12806 struct mlx5_ifc_create_ipsec_obj_in_bits {
12807 	struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
12808 	struct mlx5_ifc_ipsec_obj_bits ipsec_object;
12809 };
12810 
12811 enum {
12812 	MLX5_MODIFY_IPSEC_BITMASK_ESN_OVERLAP = BIT(0),
12813 	MLX5_MODIFY_IPSEC_BITMASK_ESN_MSB = BIT(1),
12814 };
12815 
12816 struct mlx5_ifc_query_ipsec_obj_out_bits {
12817 	struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr;
12818 	struct mlx5_ifc_ipsec_obj_bits ipsec_object;
12819 };
12820 
12821 struct mlx5_ifc_modify_ipsec_obj_in_bits {
12822 	struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
12823 	struct mlx5_ifc_ipsec_obj_bits ipsec_object;
12824 };
12825 
12826 enum {
12827 	MLX5_MACSEC_ASO_REPLAY_PROTECTION = 0x1,
12828 };
12829 
12830 enum {
12831 	MLX5_MACSEC_ASO_REPLAY_WIN_32BIT  = 0x0,
12832 	MLX5_MACSEC_ASO_REPLAY_WIN_64BIT  = 0x1,
12833 	MLX5_MACSEC_ASO_REPLAY_WIN_128BIT = 0x2,
12834 	MLX5_MACSEC_ASO_REPLAY_WIN_256BIT = 0x3,
12835 };
12836 
12837 #define MLX5_MACSEC_ASO_INC_SN  0x2
12838 #define MLX5_MACSEC_ASO_REG_C_4_5 0x2
12839 
12840 struct mlx5_ifc_macsec_aso_bits {
12841 	u8    valid[0x1];
12842 	u8    reserved_at_1[0x1];
12843 	u8    mode[0x2];
12844 	u8    window_size[0x2];
12845 	u8    soft_lifetime_arm[0x1];
12846 	u8    hard_lifetime_arm[0x1];
12847 	u8    remove_flow_enable[0x1];
12848 	u8    epn_event_arm[0x1];
12849 	u8    reserved_at_a[0x16];
12850 
12851 	u8    remove_flow_packet_count[0x20];
12852 
12853 	u8    remove_flow_soft_lifetime[0x20];
12854 
12855 	u8    reserved_at_60[0x80];
12856 
12857 	u8    mode_parameter[0x20];
12858 
12859 	u8    replay_protection_window[8][0x20];
12860 };
12861 
12862 struct mlx5_ifc_macsec_offload_obj_bits {
12863 	u8    modify_field_select[0x40];
12864 
12865 	u8    confidentiality_en[0x1];
12866 	u8    reserved_at_41[0x1];
12867 	u8    epn_en[0x1];
12868 	u8    epn_overlap[0x1];
12869 	u8    reserved_at_44[0x2];
12870 	u8    confidentiality_offset[0x2];
12871 	u8    reserved_at_48[0x4];
12872 	u8    aso_return_reg[0x4];
12873 	u8    reserved_at_50[0x10];
12874 
12875 	u8    epn_msb[0x20];
12876 
12877 	u8    reserved_at_80[0x8];
12878 	u8    dekn[0x18];
12879 
12880 	u8    reserved_at_a0[0x20];
12881 
12882 	u8    sci[0x40];
12883 
12884 	u8    reserved_at_100[0x8];
12885 	u8    macsec_aso_access_pd[0x18];
12886 
12887 	u8    reserved_at_120[0x60];
12888 
12889 	u8    salt[3][0x20];
12890 
12891 	u8    reserved_at_1e0[0x20];
12892 
12893 	struct mlx5_ifc_macsec_aso_bits macsec_aso;
12894 };
12895 
12896 struct mlx5_ifc_create_macsec_obj_in_bits {
12897 	struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
12898 	struct mlx5_ifc_macsec_offload_obj_bits macsec_object;
12899 };
12900 
12901 struct mlx5_ifc_modify_macsec_obj_in_bits {
12902 	struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
12903 	struct mlx5_ifc_macsec_offload_obj_bits macsec_object;
12904 };
12905 
12906 enum {
12907 	MLX5_MODIFY_MACSEC_BITMASK_EPN_OVERLAP = BIT(0),
12908 	MLX5_MODIFY_MACSEC_BITMASK_EPN_MSB = BIT(1),
12909 };
12910 
12911 struct mlx5_ifc_query_macsec_obj_out_bits {
12912 	struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr;
12913 	struct mlx5_ifc_macsec_offload_obj_bits macsec_object;
12914 };
12915 
12916 struct mlx5_ifc_wrapped_dek_bits {
12917 	u8         gcm_iv[0x60];
12918 
12919 	u8         reserved_at_60[0x20];
12920 
12921 	u8         const0[0x1];
12922 	u8         key_size[0x1];
12923 	u8         reserved_at_82[0x2];
12924 	u8         key2_invalid[0x1];
12925 	u8         reserved_at_85[0x3];
12926 	u8         pd[0x18];
12927 
12928 	u8         key_purpose[0x5];
12929 	u8         reserved_at_a5[0x13];
12930 	u8         kek_id[0x8];
12931 
12932 	u8         reserved_at_c0[0x40];
12933 
12934 	u8         key1[0x8][0x20];
12935 
12936 	u8         key2[0x8][0x20];
12937 
12938 	u8         reserved_at_300[0x40];
12939 
12940 	u8         const1[0x1];
12941 	u8         reserved_at_341[0x1f];
12942 
12943 	u8         reserved_at_360[0x20];
12944 
12945 	u8         auth_tag[0x80];
12946 };
12947 
12948 struct mlx5_ifc_encryption_key_obj_bits {
12949 	u8         modify_field_select[0x40];
12950 
12951 	u8         state[0x8];
12952 	u8         sw_wrapped[0x1];
12953 	u8         reserved_at_49[0xb];
12954 	u8         key_size[0x4];
12955 	u8         reserved_at_58[0x4];
12956 	u8         key_purpose[0x4];
12957 
12958 	u8         reserved_at_60[0x8];
12959 	u8         pd[0x18];
12960 
12961 	u8         reserved_at_80[0x100];
12962 
12963 	u8         opaque[0x40];
12964 
12965 	u8         reserved_at_1c0[0x40];
12966 
12967 	u8         key[8][0x80];
12968 
12969 	u8         sw_wrapped_dek[8][0x80];
12970 
12971 	u8         reserved_at_a00[0x600];
12972 };
12973 
12974 struct mlx5_ifc_create_encryption_key_in_bits {
12975 	struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
12976 	struct mlx5_ifc_encryption_key_obj_bits encryption_key_object;
12977 };
12978 
12979 struct mlx5_ifc_modify_encryption_key_in_bits {
12980 	struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
12981 	struct mlx5_ifc_encryption_key_obj_bits encryption_key_object;
12982 };
12983 
12984 enum {
12985 	MLX5_FLOW_METER_MODE_BYTES_IP_LENGTH		= 0x0,
12986 	MLX5_FLOW_METER_MODE_BYTES_CALC_WITH_L2		= 0x1,
12987 	MLX5_FLOW_METER_MODE_BYTES_CALC_WITH_L2_IPG	= 0x2,
12988 	MLX5_FLOW_METER_MODE_NUM_PACKETS		= 0x3,
12989 };
12990 
12991 struct mlx5_ifc_flow_meter_parameters_bits {
12992 	u8         valid[0x1];
12993 	u8         bucket_overflow[0x1];
12994 	u8         start_color[0x2];
12995 	u8         both_buckets_on_green[0x1];
12996 	u8         reserved_at_5[0x1];
12997 	u8         meter_mode[0x2];
12998 	u8         reserved_at_8[0x18];
12999 
13000 	u8         reserved_at_20[0x20];
13001 
13002 	u8         reserved_at_40[0x3];
13003 	u8         cbs_exponent[0x5];
13004 	u8         cbs_mantissa[0x8];
13005 	u8         reserved_at_50[0x3];
13006 	u8         cir_exponent[0x5];
13007 	u8         cir_mantissa[0x8];
13008 
13009 	u8         reserved_at_60[0x20];
13010 
13011 	u8         reserved_at_80[0x3];
13012 	u8         ebs_exponent[0x5];
13013 	u8         ebs_mantissa[0x8];
13014 	u8         reserved_at_90[0x3];
13015 	u8         eir_exponent[0x5];
13016 	u8         eir_mantissa[0x8];
13017 
13018 	u8         reserved_at_a0[0x60];
13019 };
13020 
13021 struct mlx5_ifc_flow_meter_aso_obj_bits {
13022 	u8         modify_field_select[0x40];
13023 
13024 	u8         reserved_at_40[0x40];
13025 
13026 	u8         reserved_at_80[0x8];
13027 	u8         meter_aso_access_pd[0x18];
13028 
13029 	u8         reserved_at_a0[0x160];
13030 
13031 	struct mlx5_ifc_flow_meter_parameters_bits flow_meter_parameters[2];
13032 };
13033 
13034 struct mlx5_ifc_create_flow_meter_aso_obj_in_bits {
13035 	struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
13036 	struct mlx5_ifc_flow_meter_aso_obj_bits flow_meter_aso_obj;
13037 };
13038 
13039 struct mlx5_ifc_int_kek_obj_bits {
13040 	u8         modify_field_select[0x40];
13041 
13042 	u8         state[0x8];
13043 	u8         auto_gen[0x1];
13044 	u8         reserved_at_49[0xb];
13045 	u8         key_size[0x4];
13046 	u8         reserved_at_58[0x8];
13047 
13048 	u8         reserved_at_60[0x8];
13049 	u8         pd[0x18];
13050 
13051 	u8         reserved_at_80[0x180];
13052 	u8         key[8][0x80];
13053 
13054 	u8         reserved_at_600[0x200];
13055 };
13056 
13057 struct mlx5_ifc_create_int_kek_obj_in_bits {
13058 	struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
13059 	struct mlx5_ifc_int_kek_obj_bits int_kek_object;
13060 };
13061 
13062 struct mlx5_ifc_create_int_kek_obj_out_bits {
13063 	struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr;
13064 	struct mlx5_ifc_int_kek_obj_bits int_kek_object;
13065 };
13066 
13067 struct mlx5_ifc_sampler_obj_bits {
13068 	u8         modify_field_select[0x40];
13069 
13070 	u8         table_type[0x8];
13071 	u8         level[0x8];
13072 	u8         reserved_at_50[0xf];
13073 	u8         ignore_flow_level[0x1];
13074 
13075 	u8         sample_ratio[0x20];
13076 
13077 	u8         reserved_at_80[0x8];
13078 	u8         sample_table_id[0x18];
13079 
13080 	u8         reserved_at_a0[0x8];
13081 	u8         default_table_id[0x18];
13082 
13083 	u8         sw_steering_icm_address_rx[0x40];
13084 	u8         sw_steering_icm_address_tx[0x40];
13085 
13086 	u8         reserved_at_140[0xa0];
13087 };
13088 
13089 struct mlx5_ifc_create_sampler_obj_in_bits {
13090 	struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
13091 	struct mlx5_ifc_sampler_obj_bits sampler_object;
13092 };
13093 
13094 struct mlx5_ifc_query_sampler_obj_out_bits {
13095 	struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr;
13096 	struct mlx5_ifc_sampler_obj_bits sampler_object;
13097 };
13098 
13099 enum {
13100 	MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_128 = 0x0,
13101 	MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_256 = 0x1,
13102 };
13103 
13104 enum {
13105 	MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_PURPOSE_TLS = 0x1,
13106 	MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_PURPOSE_IPSEC = 0x2,
13107 	MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_PURPOSE_MACSEC = 0x4,
13108 	MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_PURPOSE_PSP = 0x6,
13109 };
13110 
13111 struct mlx5_ifc_tls_static_params_bits {
13112 	u8         const_2[0x2];
13113 	u8         tls_version[0x4];
13114 	u8         const_1[0x2];
13115 	u8         reserved_at_8[0x14];
13116 	u8         encryption_standard[0x4];
13117 
13118 	u8         reserved_at_20[0x20];
13119 
13120 	u8         initial_record_number[0x40];
13121 
13122 	u8         resync_tcp_sn[0x20];
13123 
13124 	u8         gcm_iv[0x20];
13125 
13126 	u8         implicit_iv[0x40];
13127 
13128 	u8         reserved_at_100[0x8];
13129 	u8         dek_index[0x18];
13130 
13131 	u8         reserved_at_120[0xe0];
13132 };
13133 
13134 struct mlx5_ifc_tls_progress_params_bits {
13135 	u8         next_record_tcp_sn[0x20];
13136 
13137 	u8         hw_resync_tcp_sn[0x20];
13138 
13139 	u8         record_tracker_state[0x2];
13140 	u8         auth_state[0x2];
13141 	u8         reserved_at_44[0x4];
13142 	u8         hw_offset_record_number[0x18];
13143 };
13144 
13145 enum {
13146 	MLX5_MTT_PERM_READ	= 1 << 0,
13147 	MLX5_MTT_PERM_WRITE	= 1 << 1,
13148 	MLX5_MTT_PERM_RW	= MLX5_MTT_PERM_READ | MLX5_MTT_PERM_WRITE,
13149 };
13150 
13151 enum {
13152 	MLX5_SUSPEND_VHCA_IN_OP_MOD_SUSPEND_INITIATOR  = 0x0,
13153 	MLX5_SUSPEND_VHCA_IN_OP_MOD_SUSPEND_RESPONDER  = 0x1,
13154 };
13155 
13156 struct mlx5_ifc_suspend_vhca_in_bits {
13157 	u8         opcode[0x10];
13158 	u8         uid[0x10];
13159 
13160 	u8         reserved_at_20[0x10];
13161 	u8         op_mod[0x10];
13162 
13163 	u8         reserved_at_40[0x10];
13164 	u8         vhca_id[0x10];
13165 
13166 	u8         reserved_at_60[0x20];
13167 };
13168 
13169 struct mlx5_ifc_suspend_vhca_out_bits {
13170 	u8         status[0x8];
13171 	u8         reserved_at_8[0x18];
13172 
13173 	u8         syndrome[0x20];
13174 
13175 	u8         reserved_at_40[0x40];
13176 };
13177 
13178 enum {
13179 	MLX5_RESUME_VHCA_IN_OP_MOD_RESUME_RESPONDER  = 0x0,
13180 	MLX5_RESUME_VHCA_IN_OP_MOD_RESUME_INITIATOR  = 0x1,
13181 };
13182 
13183 struct mlx5_ifc_resume_vhca_in_bits {
13184 	u8         opcode[0x10];
13185 	u8         uid[0x10];
13186 
13187 	u8         reserved_at_20[0x10];
13188 	u8         op_mod[0x10];
13189 
13190 	u8         reserved_at_40[0x10];
13191 	u8         vhca_id[0x10];
13192 
13193 	u8         reserved_at_60[0x20];
13194 };
13195 
13196 struct mlx5_ifc_resume_vhca_out_bits {
13197 	u8         status[0x8];
13198 	u8         reserved_at_8[0x18];
13199 
13200 	u8         syndrome[0x20];
13201 
13202 	u8         reserved_at_40[0x40];
13203 };
13204 
13205 struct mlx5_ifc_query_vhca_migration_state_in_bits {
13206 	u8         opcode[0x10];
13207 	u8         uid[0x10];
13208 
13209 	u8         reserved_at_20[0x10];
13210 	u8         op_mod[0x10];
13211 
13212 	u8         incremental[0x1];
13213 	u8         chunk[0x1];
13214 	u8         reserved_at_42[0xe];
13215 	u8         vhca_id[0x10];
13216 
13217 	u8         reserved_at_60[0x20];
13218 };
13219 
13220 struct mlx5_ifc_query_vhca_migration_state_out_bits {
13221 	u8         status[0x8];
13222 	u8         reserved_at_8[0x18];
13223 
13224 	u8         syndrome[0x20];
13225 
13226 	u8         reserved_at_40[0x40];
13227 
13228 	u8         required_umem_size[0x20];
13229 
13230 	u8         reserved_at_a0[0x20];
13231 
13232 	u8         remaining_total_size[0x40];
13233 
13234 	u8         reserved_at_100[0x100];
13235 };
13236 
13237 struct mlx5_ifc_save_vhca_state_in_bits {
13238 	u8         opcode[0x10];
13239 	u8         uid[0x10];
13240 
13241 	u8         reserved_at_20[0x10];
13242 	u8         op_mod[0x10];
13243 
13244 	u8         incremental[0x1];
13245 	u8         set_track[0x1];
13246 	u8         reserved_at_42[0xe];
13247 	u8         vhca_id[0x10];
13248 
13249 	u8         reserved_at_60[0x20];
13250 
13251 	u8         va[0x40];
13252 
13253 	u8         mkey[0x20];
13254 
13255 	u8         size[0x20];
13256 };
13257 
13258 struct mlx5_ifc_save_vhca_state_out_bits {
13259 	u8         status[0x8];
13260 	u8         reserved_at_8[0x18];
13261 
13262 	u8         syndrome[0x20];
13263 
13264 	u8         actual_image_size[0x20];
13265 
13266 	u8         next_required_umem_size[0x20];
13267 };
13268 
13269 struct mlx5_ifc_load_vhca_state_in_bits {
13270 	u8         opcode[0x10];
13271 	u8         uid[0x10];
13272 
13273 	u8         reserved_at_20[0x10];
13274 	u8         op_mod[0x10];
13275 
13276 	u8         reserved_at_40[0x10];
13277 	u8         vhca_id[0x10];
13278 
13279 	u8         reserved_at_60[0x20];
13280 
13281 	u8         va[0x40];
13282 
13283 	u8         mkey[0x20];
13284 
13285 	u8         size[0x20];
13286 };
13287 
13288 struct mlx5_ifc_load_vhca_state_out_bits {
13289 	u8         status[0x8];
13290 	u8         reserved_at_8[0x18];
13291 
13292 	u8         syndrome[0x20];
13293 
13294 	u8         reserved_at_40[0x40];
13295 };
13296 
13297 struct mlx5_ifc_adv_rdma_cap_bits {
13298 	u8         rdma_transport_manager[0x1];
13299 	u8         rdma_transport_manager_other_eswitch[0x1];
13300 	u8         reserved_at_2[0x1e];
13301 
13302 	u8         rcx_type[0x8];
13303 	u8         reserved_at_28[0x2];
13304 	u8         ps_entry_log_max_value[0x6];
13305 	u8         reserved_at_30[0x6];
13306 	u8         qp_max_ps_num_entry[0xa];
13307 
13308 	u8         mp_max_num_queues[0x8];
13309 	u8         ps_user_context_max_log_size[0x8];
13310 	u8         message_based_qp_and_striding_wq[0x8];
13311 	u8         reserved_at_58[0x8];
13312 
13313 	u8         max_receive_send_message_size_stride[0x10];
13314 	u8         reserved_at_70[0x10];
13315 
13316 	u8         max_receive_send_message_size_byte[0x20];
13317 
13318 	u8         reserved_at_a0[0x160];
13319 
13320 	struct mlx5_ifc_flow_table_prop_layout_bits rdma_transport_rx_flow_table_properties;
13321 
13322 	struct mlx5_ifc_flow_table_prop_layout_bits rdma_transport_tx_flow_table_properties;
13323 
13324 	struct mlx5_ifc_flow_table_fields_supported_2_bits rdma_transport_rx_ft_field_support_2;
13325 
13326 	struct mlx5_ifc_flow_table_fields_supported_2_bits rdma_transport_tx_ft_field_support_2;
13327 
13328 	struct mlx5_ifc_flow_table_fields_supported_2_bits rdma_transport_rx_ft_field_bitmask_support_2;
13329 
13330 	struct mlx5_ifc_flow_table_fields_supported_2_bits rdma_transport_tx_ft_field_bitmask_support_2;
13331 
13332 	u8         reserved_at_800[0x3800];
13333 };
13334 
13335 struct mlx5_ifc_adv_virtualization_cap_bits {
13336 	u8         reserved_at_0[0x3];
13337 	u8         pg_track_log_max_num[0x5];
13338 	u8         pg_track_max_num_range[0x8];
13339 	u8         pg_track_log_min_addr_space[0x8];
13340 	u8         pg_track_log_max_addr_space[0x8];
13341 
13342 	u8         reserved_at_20[0x3];
13343 	u8         pg_track_log_min_msg_size[0x5];
13344 	u8         reserved_at_28[0x3];
13345 	u8         pg_track_log_max_msg_size[0x5];
13346 	u8         reserved_at_30[0x3];
13347 	u8         pg_track_log_min_page_size[0x5];
13348 	u8         reserved_at_38[0x3];
13349 	u8         pg_track_log_max_page_size[0x5];
13350 
13351 	u8         reserved_at_40[0x7c0];
13352 };
13353 
13354 struct mlx5_ifc_page_track_report_entry_bits {
13355 	u8         dirty_address_high[0x20];
13356 
13357 	u8         dirty_address_low[0x20];
13358 };
13359 
13360 enum {
13361 	MLX5_PAGE_TRACK_STATE_TRACKING,
13362 	MLX5_PAGE_TRACK_STATE_REPORTING,
13363 	MLX5_PAGE_TRACK_STATE_ERROR,
13364 };
13365 
13366 struct mlx5_ifc_page_track_range_bits {
13367 	u8         start_address[0x40];
13368 
13369 	u8         length[0x40];
13370 };
13371 
13372 struct mlx5_ifc_page_track_bits {
13373 	u8         modify_field_select[0x40];
13374 
13375 	u8         reserved_at_40[0x10];
13376 	u8         vhca_id[0x10];
13377 
13378 	u8         reserved_at_60[0x20];
13379 
13380 	u8         state[0x4];
13381 	u8         track_type[0x4];
13382 	u8         log_addr_space_size[0x8];
13383 	u8         reserved_at_90[0x3];
13384 	u8         log_page_size[0x5];
13385 	u8         reserved_at_98[0x3];
13386 	u8         log_msg_size[0x5];
13387 
13388 	u8         reserved_at_a0[0x8];
13389 	u8         reporting_qpn[0x18];
13390 
13391 	u8         reserved_at_c0[0x18];
13392 	u8         num_ranges[0x8];
13393 
13394 	u8         reserved_at_e0[0x20];
13395 
13396 	u8         range_start_address[0x40];
13397 
13398 	u8         length[0x40];
13399 
13400 	struct     mlx5_ifc_page_track_range_bits track_range[0];
13401 };
13402 
13403 struct mlx5_ifc_create_page_track_obj_in_bits {
13404 	struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
13405 	struct mlx5_ifc_page_track_bits obj_context;
13406 };
13407 
13408 struct mlx5_ifc_modify_page_track_obj_in_bits {
13409 	struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
13410 	struct mlx5_ifc_page_track_bits obj_context;
13411 };
13412 
13413 struct mlx5_ifc_query_page_track_obj_out_bits {
13414 	struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr;
13415 	struct mlx5_ifc_page_track_bits obj_context;
13416 };
13417 
13418 struct mlx5_ifc_msecq_reg_bits {
13419 	u8         reserved_at_0[0x20];
13420 
13421 	u8         reserved_at_20[0x12];
13422 	u8         network_option[0x2];
13423 	u8         local_ssm_code[0x4];
13424 	u8         local_enhanced_ssm_code[0x8];
13425 
13426 	u8         local_clock_identity[0x40];
13427 
13428 	u8         reserved_at_80[0x180];
13429 };
13430 
13431 enum {
13432 	MLX5_MSEES_FIELD_SELECT_ENABLE			= BIT(0),
13433 	MLX5_MSEES_FIELD_SELECT_ADMIN_STATUS		= BIT(1),
13434 	MLX5_MSEES_FIELD_SELECT_ADMIN_FREQ_MEASURE	= BIT(2),
13435 };
13436 
13437 enum mlx5_msees_admin_status {
13438 	MLX5_MSEES_ADMIN_STATUS_FREE_RUNNING		= 0x0,
13439 	MLX5_MSEES_ADMIN_STATUS_TRACK			= 0x1,
13440 };
13441 
13442 enum mlx5_msees_oper_status {
13443 	MLX5_MSEES_OPER_STATUS_FREE_RUNNING		= 0x0,
13444 	MLX5_MSEES_OPER_STATUS_SELF_TRACK		= 0x1,
13445 	MLX5_MSEES_OPER_STATUS_OTHER_TRACK		= 0x2,
13446 	MLX5_MSEES_OPER_STATUS_HOLDOVER			= 0x3,
13447 	MLX5_MSEES_OPER_STATUS_FAIL_HOLDOVER		= 0x4,
13448 	MLX5_MSEES_OPER_STATUS_FAIL_FREE_RUNNING	= 0x5,
13449 };
13450 
13451 enum mlx5_msees_failure_reason {
13452 	MLX5_MSEES_FAILURE_REASON_UNDEFINED_ERROR		= 0x0,
13453 	MLX5_MSEES_FAILURE_REASON_PORT_DOWN			= 0x1,
13454 	MLX5_MSEES_FAILURE_REASON_TOO_HIGH_FREQUENCY_DIFF	= 0x2,
13455 	MLX5_MSEES_FAILURE_REASON_NET_SYNCHRONIZER_DEVICE_ERROR	= 0x3,
13456 	MLX5_MSEES_FAILURE_REASON_LACK_OF_RESOURCES		= 0x4,
13457 };
13458 
13459 struct mlx5_ifc_msees_reg_bits {
13460 	u8         reserved_at_0[0x8];
13461 	u8         local_port[0x8];
13462 	u8         pnat[0x2];
13463 	u8         lp_msb[0x2];
13464 	u8         reserved_at_14[0xc];
13465 
13466 	u8         field_select[0x20];
13467 
13468 	u8         admin_status[0x4];
13469 	u8         oper_status[0x4];
13470 	u8         ho_acq[0x1];
13471 	u8         reserved_at_49[0xc];
13472 	u8         admin_freq_measure[0x1];
13473 	u8         oper_freq_measure[0x1];
13474 	u8         failure_reason[0x9];
13475 
13476 	u8         frequency_diff[0x20];
13477 
13478 	u8         reserved_at_80[0x180];
13479 };
13480 
13481 struct mlx5_ifc_mrtcq_reg_bits {
13482 	u8         reserved_at_0[0x40];
13483 
13484 	u8         rt_clock_identity[0x40];
13485 
13486 	u8         reserved_at_80[0x180];
13487 };
13488 
13489 struct mlx5_ifc_pcie_cong_event_obj_bits {
13490 	u8         modify_select_field[0x40];
13491 
13492 	u8         inbound_event_en[0x1];
13493 	u8         outbound_event_en[0x1];
13494 	u8         reserved_at_42[0x1e];
13495 
13496 	u8         reserved_at_60[0x1];
13497 	u8         inbound_cong_state[0x3];
13498 	u8         reserved_at_64[0x1];
13499 	u8         outbound_cong_state[0x3];
13500 	u8         reserved_at_68[0x18];
13501 
13502 	u8         inbound_cong_low_threshold[0x10];
13503 	u8         inbound_cong_high_threshold[0x10];
13504 
13505 	u8         outbound_cong_low_threshold[0x10];
13506 	u8         outbound_cong_high_threshold[0x10];
13507 
13508 	u8         reserved_at_e0[0x340];
13509 };
13510 
13511 struct mlx5_ifc_pcie_cong_event_cmd_in_bits {
13512 	struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
13513 	struct mlx5_ifc_pcie_cong_event_obj_bits cong_obj;
13514 };
13515 
13516 struct mlx5_ifc_pcie_cong_event_cmd_out_bits {
13517 	struct mlx5_ifc_general_obj_out_cmd_hdr_bits hdr;
13518 	struct mlx5_ifc_pcie_cong_event_obj_bits cong_obj;
13519 };
13520 
13521 enum mlx5e_pcie_cong_event_mod_field {
13522 	MLX5_PCIE_CONG_EVENT_MOD_EVENT_EN = BIT(0),
13523 	MLX5_PCIE_CONG_EVENT_MOD_THRESH   = BIT(2),
13524 };
13525 
13526 struct mlx5_ifc_psp_rotate_key_in_bits {
13527 	u8         opcode[0x10];
13528 	u8         uid[0x10];
13529 
13530 	u8         reserved_at_20[0x10];
13531 	u8         op_mod[0x10];
13532 
13533 	u8         reserved_at_40[0x40];
13534 };
13535 
13536 struct mlx5_ifc_psp_rotate_key_out_bits {
13537 	u8         status[0x8];
13538 	u8         reserved_at_8[0x18];
13539 
13540 	u8         syndrome[0x20];
13541 
13542 	u8         reserved_at_40[0x40];
13543 };
13544 
13545 enum mlx5_psp_gen_spi_in_key_size {
13546 	MLX5_PSP_GEN_SPI_IN_KEY_SIZE_128 = 0x0,
13547 	MLX5_PSP_GEN_SPI_IN_KEY_SIZE_256 = 0x1,
13548 };
13549 
13550 struct mlx5_ifc_key_spi_bits {
13551 	u8         spi[0x20];
13552 
13553 	u8         reserved_at_20[0x60];
13554 
13555 	u8         key[8][0x20];
13556 };
13557 
13558 struct mlx5_ifc_psp_gen_spi_in_bits {
13559 	u8         opcode[0x10];
13560 	u8         uid[0x10];
13561 
13562 	u8         reserved_at_20[0x10];
13563 	u8         op_mod[0x10];
13564 
13565 	u8         reserved_at_40[0x20];
13566 
13567 	u8         key_size[0x2];
13568 	u8         reserved_at_62[0xe];
13569 	u8         num_of_spi[0x10];
13570 };
13571 
13572 struct mlx5_ifc_psp_gen_spi_out_bits {
13573 	u8         status[0x8];
13574 	u8         reserved_at_8[0x18];
13575 
13576 	u8         syndrome[0x20];
13577 
13578 	u8         reserved_at_40[0x10];
13579 	u8         num_of_spi[0x10];
13580 
13581 	u8         reserved_at_60[0x20];
13582 
13583 	struct mlx5_ifc_key_spi_bits key_spi[];
13584 };
13585 
13586 #endif /* MLX5_IFC_H */
13587