1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 #ifndef MLX5_IFC_H 33 #define MLX5_IFC_H 34 35 #include "mlx5_ifc_fpga.h" 36 37 enum { 38 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0, 39 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1, 40 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2, 41 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3, 42 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13, 43 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14, 44 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c, 45 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d, 46 MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4, 47 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5, 48 MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED = 0x7, 49 MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT = 0xc, 50 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10, 51 MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR = 0x11, 52 MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR = 0x12, 53 MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR = 0x8, 54 MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE = 0x9, 55 MLX5_EVENT_TYPE_CODING_GPIO_EVENT = 0x15, 56 MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19, 57 MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a, 58 MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT = 0x1b, 59 MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT = 0x1f, 60 MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa, 61 MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb, 62 MLX5_EVENT_TYPE_CODING_FPGA_ERROR = 0x20, 63 MLX5_EVENT_TYPE_CODING_FPGA_QP_ERROR = 0x21 64 }; 65 66 enum { 67 MLX5_MODIFY_TIR_BITMASK_LRO = 0x0, 68 MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE = 0x1, 69 MLX5_MODIFY_TIR_BITMASK_HASH = 0x2, 70 MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN = 0x3 71 }; 72 73 enum { 74 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0, 75 MLX5_SET_HCA_CAP_OP_MOD_ODP = 0x2, 76 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3, 77 }; 78 79 enum { 80 MLX5_SHARED_RESOURCE_UID = 0xffff, 81 }; 82 83 enum { 84 MLX5_OBJ_TYPE_SW_ICM = 0x0008, 85 }; 86 87 enum { 88 MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM = (1ULL << MLX5_OBJ_TYPE_SW_ICM), 89 MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT = (1ULL << 11), 90 }; 91 92 enum { 93 MLX5_OBJ_TYPE_GENEVE_TLV_OPT = 0x000b, 94 }; 95 96 enum { 97 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100, 98 MLX5_CMD_OP_QUERY_ADAPTER = 0x101, 99 MLX5_CMD_OP_INIT_HCA = 0x102, 100 MLX5_CMD_OP_TEARDOWN_HCA = 0x103, 101 MLX5_CMD_OP_ENABLE_HCA = 0x104, 102 MLX5_CMD_OP_DISABLE_HCA = 0x105, 103 MLX5_CMD_OP_QUERY_PAGES = 0x107, 104 MLX5_CMD_OP_MANAGE_PAGES = 0x108, 105 MLX5_CMD_OP_SET_HCA_CAP = 0x109, 106 MLX5_CMD_OP_QUERY_ISSI = 0x10a, 107 MLX5_CMD_OP_SET_ISSI = 0x10b, 108 MLX5_CMD_OP_SET_DRIVER_VERSION = 0x10d, 109 MLX5_CMD_OP_CREATE_MKEY = 0x200, 110 MLX5_CMD_OP_QUERY_MKEY = 0x201, 111 MLX5_CMD_OP_DESTROY_MKEY = 0x202, 112 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203, 113 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204, 114 MLX5_CMD_OP_ALLOC_MEMIC = 0x205, 115 MLX5_CMD_OP_DEALLOC_MEMIC = 0x206, 116 MLX5_CMD_OP_CREATE_EQ = 0x301, 117 MLX5_CMD_OP_DESTROY_EQ = 0x302, 118 MLX5_CMD_OP_QUERY_EQ = 0x303, 119 MLX5_CMD_OP_GEN_EQE = 0x304, 120 MLX5_CMD_OP_CREATE_CQ = 0x400, 121 MLX5_CMD_OP_DESTROY_CQ = 0x401, 122 MLX5_CMD_OP_QUERY_CQ = 0x402, 123 MLX5_CMD_OP_MODIFY_CQ = 0x403, 124 MLX5_CMD_OP_CREATE_QP = 0x500, 125 MLX5_CMD_OP_DESTROY_QP = 0x501, 126 MLX5_CMD_OP_RST2INIT_QP = 0x502, 127 MLX5_CMD_OP_INIT2RTR_QP = 0x503, 128 MLX5_CMD_OP_RTR2RTS_QP = 0x504, 129 MLX5_CMD_OP_RTS2RTS_QP = 0x505, 130 MLX5_CMD_OP_SQERR2RTS_QP = 0x506, 131 MLX5_CMD_OP_2ERR_QP = 0x507, 132 MLX5_CMD_OP_2RST_QP = 0x50a, 133 MLX5_CMD_OP_QUERY_QP = 0x50b, 134 MLX5_CMD_OP_SQD_RTS_QP = 0x50c, 135 MLX5_CMD_OP_INIT2INIT_QP = 0x50e, 136 MLX5_CMD_OP_CREATE_PSV = 0x600, 137 MLX5_CMD_OP_DESTROY_PSV = 0x601, 138 MLX5_CMD_OP_CREATE_SRQ = 0x700, 139 MLX5_CMD_OP_DESTROY_SRQ = 0x701, 140 MLX5_CMD_OP_QUERY_SRQ = 0x702, 141 MLX5_CMD_OP_ARM_RQ = 0x703, 142 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705, 143 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706, 144 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707, 145 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708, 146 MLX5_CMD_OP_CREATE_DCT = 0x710, 147 MLX5_CMD_OP_DESTROY_DCT = 0x711, 148 MLX5_CMD_OP_DRAIN_DCT = 0x712, 149 MLX5_CMD_OP_QUERY_DCT = 0x713, 150 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714, 151 MLX5_CMD_OP_CREATE_XRQ = 0x717, 152 MLX5_CMD_OP_DESTROY_XRQ = 0x718, 153 MLX5_CMD_OP_QUERY_XRQ = 0x719, 154 MLX5_CMD_OP_ARM_XRQ = 0x71a, 155 MLX5_CMD_OP_QUERY_XRQ_DC_PARAMS_ENTRY = 0x725, 156 MLX5_CMD_OP_SET_XRQ_DC_PARAMS_ENTRY = 0x726, 157 MLX5_CMD_OP_QUERY_XRQ_ERROR_PARAMS = 0x727, 158 MLX5_CMD_OP_QUERY_ESW_FUNCTIONS = 0x740, 159 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750, 160 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751, 161 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752, 162 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753, 163 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754, 164 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755, 165 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760, 166 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761, 167 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762, 168 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763, 169 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764, 170 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765, 171 MLX5_CMD_OP_QUERY_VNIC_ENV = 0x76f, 172 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770, 173 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771, 174 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772, 175 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773, 176 MLX5_CMD_OP_SET_MONITOR_COUNTER = 0x774, 177 MLX5_CMD_OP_ARM_MONITOR_COUNTER = 0x775, 178 MLX5_CMD_OP_SET_PP_RATE_LIMIT = 0x780, 179 MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781, 180 MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT = 0x782, 181 MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT = 0x783, 182 MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT = 0x784, 183 MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT = 0x785, 184 MLX5_CMD_OP_CREATE_QOS_PARA_VPORT = 0x786, 185 MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT = 0x787, 186 MLX5_CMD_OP_ALLOC_PD = 0x800, 187 MLX5_CMD_OP_DEALLOC_PD = 0x801, 188 MLX5_CMD_OP_ALLOC_UAR = 0x802, 189 MLX5_CMD_OP_DEALLOC_UAR = 0x803, 190 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804, 191 MLX5_CMD_OP_ACCESS_REG = 0x805, 192 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806, 193 MLX5_CMD_OP_DETACH_FROM_MCG = 0x807, 194 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a, 195 MLX5_CMD_OP_MAD_IFC = 0x50d, 196 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b, 197 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c, 198 MLX5_CMD_OP_NOP = 0x80d, 199 MLX5_CMD_OP_ALLOC_XRCD = 0x80e, 200 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f, 201 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816, 202 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817, 203 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822, 204 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823, 205 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824, 206 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825, 207 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826, 208 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827, 209 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828, 210 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829, 211 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a, 212 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b, 213 MLX5_CMD_OP_SET_WOL_ROL = 0x830, 214 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831, 215 MLX5_CMD_OP_CREATE_LAG = 0x840, 216 MLX5_CMD_OP_MODIFY_LAG = 0x841, 217 MLX5_CMD_OP_QUERY_LAG = 0x842, 218 MLX5_CMD_OP_DESTROY_LAG = 0x843, 219 MLX5_CMD_OP_CREATE_VPORT_LAG = 0x844, 220 MLX5_CMD_OP_DESTROY_VPORT_LAG = 0x845, 221 MLX5_CMD_OP_CREATE_TIR = 0x900, 222 MLX5_CMD_OP_MODIFY_TIR = 0x901, 223 MLX5_CMD_OP_DESTROY_TIR = 0x902, 224 MLX5_CMD_OP_QUERY_TIR = 0x903, 225 MLX5_CMD_OP_CREATE_SQ = 0x904, 226 MLX5_CMD_OP_MODIFY_SQ = 0x905, 227 MLX5_CMD_OP_DESTROY_SQ = 0x906, 228 MLX5_CMD_OP_QUERY_SQ = 0x907, 229 MLX5_CMD_OP_CREATE_RQ = 0x908, 230 MLX5_CMD_OP_MODIFY_RQ = 0x909, 231 MLX5_CMD_OP_SET_DELAY_DROP_PARAMS = 0x910, 232 MLX5_CMD_OP_DESTROY_RQ = 0x90a, 233 MLX5_CMD_OP_QUERY_RQ = 0x90b, 234 MLX5_CMD_OP_CREATE_RMP = 0x90c, 235 MLX5_CMD_OP_MODIFY_RMP = 0x90d, 236 MLX5_CMD_OP_DESTROY_RMP = 0x90e, 237 MLX5_CMD_OP_QUERY_RMP = 0x90f, 238 MLX5_CMD_OP_CREATE_TIS = 0x912, 239 MLX5_CMD_OP_MODIFY_TIS = 0x913, 240 MLX5_CMD_OP_DESTROY_TIS = 0x914, 241 MLX5_CMD_OP_QUERY_TIS = 0x915, 242 MLX5_CMD_OP_CREATE_RQT = 0x916, 243 MLX5_CMD_OP_MODIFY_RQT = 0x917, 244 MLX5_CMD_OP_DESTROY_RQT = 0x918, 245 MLX5_CMD_OP_QUERY_RQT = 0x919, 246 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f, 247 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930, 248 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931, 249 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932, 250 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933, 251 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934, 252 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935, 253 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936, 254 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937, 255 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938, 256 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939, 257 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a, 258 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b, 259 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c, 260 MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT = 0x93d, 261 MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT = 0x93e, 262 MLX5_CMD_OP_QUERY_PACKET_REFORMAT_CONTEXT = 0x93f, 263 MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT = 0x940, 264 MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941, 265 MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT = 0x942, 266 MLX5_CMD_OP_FPGA_CREATE_QP = 0x960, 267 MLX5_CMD_OP_FPGA_MODIFY_QP = 0x961, 268 MLX5_CMD_OP_FPGA_QUERY_QP = 0x962, 269 MLX5_CMD_OP_FPGA_DESTROY_QP = 0x963, 270 MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS = 0x964, 271 MLX5_CMD_OP_CREATE_GENERAL_OBJECT = 0xa00, 272 MLX5_CMD_OP_MODIFY_GENERAL_OBJECT = 0xa01, 273 MLX5_CMD_OP_QUERY_GENERAL_OBJECT = 0xa02, 274 MLX5_CMD_OP_DESTROY_GENERAL_OBJECT = 0xa03, 275 MLX5_CMD_OP_CREATE_UCTX = 0xa04, 276 MLX5_CMD_OP_DESTROY_UCTX = 0xa06, 277 MLX5_CMD_OP_CREATE_UMEM = 0xa08, 278 MLX5_CMD_OP_DESTROY_UMEM = 0xa0a, 279 MLX5_CMD_OP_MAX 280 }; 281 282 /* Valid range for general commands that don't work over an object */ 283 enum { 284 MLX5_CMD_OP_GENERAL_START = 0xb00, 285 MLX5_CMD_OP_GENERAL_END = 0xd00, 286 }; 287 288 struct mlx5_ifc_flow_table_fields_supported_bits { 289 u8 outer_dmac[0x1]; 290 u8 outer_smac[0x1]; 291 u8 outer_ether_type[0x1]; 292 u8 outer_ip_version[0x1]; 293 u8 outer_first_prio[0x1]; 294 u8 outer_first_cfi[0x1]; 295 u8 outer_first_vid[0x1]; 296 u8 outer_ipv4_ttl[0x1]; 297 u8 outer_second_prio[0x1]; 298 u8 outer_second_cfi[0x1]; 299 u8 outer_second_vid[0x1]; 300 u8 reserved_at_b[0x1]; 301 u8 outer_sip[0x1]; 302 u8 outer_dip[0x1]; 303 u8 outer_frag[0x1]; 304 u8 outer_ip_protocol[0x1]; 305 u8 outer_ip_ecn[0x1]; 306 u8 outer_ip_dscp[0x1]; 307 u8 outer_udp_sport[0x1]; 308 u8 outer_udp_dport[0x1]; 309 u8 outer_tcp_sport[0x1]; 310 u8 outer_tcp_dport[0x1]; 311 u8 outer_tcp_flags[0x1]; 312 u8 outer_gre_protocol[0x1]; 313 u8 outer_gre_key[0x1]; 314 u8 outer_vxlan_vni[0x1]; 315 u8 outer_geneve_vni[0x1]; 316 u8 outer_geneve_oam[0x1]; 317 u8 outer_geneve_protocol_type[0x1]; 318 u8 outer_geneve_opt_len[0x1]; 319 u8 reserved_at_1e[0x1]; 320 u8 source_eswitch_port[0x1]; 321 322 u8 inner_dmac[0x1]; 323 u8 inner_smac[0x1]; 324 u8 inner_ether_type[0x1]; 325 u8 inner_ip_version[0x1]; 326 u8 inner_first_prio[0x1]; 327 u8 inner_first_cfi[0x1]; 328 u8 inner_first_vid[0x1]; 329 u8 reserved_at_27[0x1]; 330 u8 inner_second_prio[0x1]; 331 u8 inner_second_cfi[0x1]; 332 u8 inner_second_vid[0x1]; 333 u8 reserved_at_2b[0x1]; 334 u8 inner_sip[0x1]; 335 u8 inner_dip[0x1]; 336 u8 inner_frag[0x1]; 337 u8 inner_ip_protocol[0x1]; 338 u8 inner_ip_ecn[0x1]; 339 u8 inner_ip_dscp[0x1]; 340 u8 inner_udp_sport[0x1]; 341 u8 inner_udp_dport[0x1]; 342 u8 inner_tcp_sport[0x1]; 343 u8 inner_tcp_dport[0x1]; 344 u8 inner_tcp_flags[0x1]; 345 u8 reserved_at_37[0x9]; 346 347 u8 geneve_tlv_option_0_data[0x1]; 348 u8 reserved_at_41[0x4]; 349 u8 outer_first_mpls_over_udp[0x4]; 350 u8 outer_first_mpls_over_gre[0x4]; 351 u8 inner_first_mpls[0x4]; 352 u8 outer_first_mpls[0x4]; 353 u8 reserved_at_55[0x2]; 354 u8 outer_esp_spi[0x1]; 355 u8 reserved_at_58[0x2]; 356 u8 bth_dst_qp[0x1]; 357 358 u8 reserved_at_5b[0x25]; 359 }; 360 361 struct mlx5_ifc_flow_table_prop_layout_bits { 362 u8 ft_support[0x1]; 363 u8 reserved_at_1[0x1]; 364 u8 flow_counter[0x1]; 365 u8 flow_modify_en[0x1]; 366 u8 modify_root[0x1]; 367 u8 identified_miss_table_mode[0x1]; 368 u8 flow_table_modify[0x1]; 369 u8 reformat[0x1]; 370 u8 decap[0x1]; 371 u8 reserved_at_9[0x1]; 372 u8 pop_vlan[0x1]; 373 u8 push_vlan[0x1]; 374 u8 reserved_at_c[0x1]; 375 u8 pop_vlan_2[0x1]; 376 u8 push_vlan_2[0x1]; 377 u8 reformat_and_vlan_action[0x1]; 378 u8 reserved_at_10[0x1]; 379 u8 sw_owner[0x1]; 380 u8 reformat_l3_tunnel_to_l2[0x1]; 381 u8 reformat_l2_to_l3_tunnel[0x1]; 382 u8 reformat_and_modify_action[0x1]; 383 u8 reserved_at_15[0x2]; 384 u8 table_miss_action_domain[0x1]; 385 u8 termination_table[0x1]; 386 u8 reserved_at_19[0x7]; 387 u8 reserved_at_20[0x2]; 388 u8 log_max_ft_size[0x6]; 389 u8 log_max_modify_header_context[0x8]; 390 u8 max_modify_header_actions[0x8]; 391 u8 max_ft_level[0x8]; 392 393 u8 reserved_at_40[0x20]; 394 395 u8 reserved_at_60[0x18]; 396 u8 log_max_ft_num[0x8]; 397 398 u8 reserved_at_80[0x18]; 399 u8 log_max_destination[0x8]; 400 401 u8 log_max_flow_counter[0x8]; 402 u8 reserved_at_a8[0x10]; 403 u8 log_max_flow[0x8]; 404 405 u8 reserved_at_c0[0x40]; 406 407 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support; 408 409 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support; 410 }; 411 412 struct mlx5_ifc_odp_per_transport_service_cap_bits { 413 u8 send[0x1]; 414 u8 receive[0x1]; 415 u8 write[0x1]; 416 u8 read[0x1]; 417 u8 atomic[0x1]; 418 u8 srq_receive[0x1]; 419 u8 reserved_at_6[0x1a]; 420 }; 421 422 struct mlx5_ifc_fte_match_set_lyr_2_4_bits { 423 u8 smac_47_16[0x20]; 424 425 u8 smac_15_0[0x10]; 426 u8 ethertype[0x10]; 427 428 u8 dmac_47_16[0x20]; 429 430 u8 dmac_15_0[0x10]; 431 u8 first_prio[0x3]; 432 u8 first_cfi[0x1]; 433 u8 first_vid[0xc]; 434 435 u8 ip_protocol[0x8]; 436 u8 ip_dscp[0x6]; 437 u8 ip_ecn[0x2]; 438 u8 cvlan_tag[0x1]; 439 u8 svlan_tag[0x1]; 440 u8 frag[0x1]; 441 u8 ip_version[0x4]; 442 u8 tcp_flags[0x9]; 443 444 u8 tcp_sport[0x10]; 445 u8 tcp_dport[0x10]; 446 447 u8 reserved_at_c0[0x18]; 448 u8 ttl_hoplimit[0x8]; 449 450 u8 udp_sport[0x10]; 451 u8 udp_dport[0x10]; 452 453 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6; 454 455 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6; 456 }; 457 458 struct mlx5_ifc_nvgre_key_bits { 459 u8 hi[0x18]; 460 u8 lo[0x8]; 461 }; 462 463 union mlx5_ifc_gre_key_bits { 464 struct mlx5_ifc_nvgre_key_bits nvgre; 465 u8 key[0x20]; 466 }; 467 468 struct mlx5_ifc_fte_match_set_misc_bits { 469 u8 reserved_at_0[0x8]; 470 u8 source_sqn[0x18]; 471 472 u8 source_eswitch_owner_vhca_id[0x10]; 473 u8 source_port[0x10]; 474 475 u8 outer_second_prio[0x3]; 476 u8 outer_second_cfi[0x1]; 477 u8 outer_second_vid[0xc]; 478 u8 inner_second_prio[0x3]; 479 u8 inner_second_cfi[0x1]; 480 u8 inner_second_vid[0xc]; 481 482 u8 outer_second_cvlan_tag[0x1]; 483 u8 inner_second_cvlan_tag[0x1]; 484 u8 outer_second_svlan_tag[0x1]; 485 u8 inner_second_svlan_tag[0x1]; 486 u8 reserved_at_64[0xc]; 487 u8 gre_protocol[0x10]; 488 489 union mlx5_ifc_gre_key_bits gre_key; 490 491 u8 vxlan_vni[0x18]; 492 u8 reserved_at_b8[0x8]; 493 494 u8 geneve_vni[0x18]; 495 u8 reserved_at_d8[0x7]; 496 u8 geneve_oam[0x1]; 497 498 u8 reserved_at_e0[0xc]; 499 u8 outer_ipv6_flow_label[0x14]; 500 501 u8 reserved_at_100[0xc]; 502 u8 inner_ipv6_flow_label[0x14]; 503 504 u8 reserved_at_120[0xa]; 505 u8 geneve_opt_len[0x6]; 506 u8 geneve_protocol_type[0x10]; 507 508 u8 reserved_at_140[0x8]; 509 u8 bth_dst_qp[0x18]; 510 u8 reserved_at_160[0x20]; 511 u8 outer_esp_spi[0x20]; 512 u8 reserved_at_1a0[0x60]; 513 }; 514 515 struct mlx5_ifc_fte_match_mpls_bits { 516 u8 mpls_label[0x14]; 517 u8 mpls_exp[0x3]; 518 u8 mpls_s_bos[0x1]; 519 u8 mpls_ttl[0x8]; 520 }; 521 522 struct mlx5_ifc_fte_match_set_misc2_bits { 523 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls; 524 525 struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls; 526 527 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre; 528 529 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp; 530 531 u8 reserved_at_80[0x100]; 532 533 u8 metadata_reg_a[0x20]; 534 535 u8 reserved_at_1a0[0x60]; 536 }; 537 538 struct mlx5_ifc_fte_match_set_misc3_bits { 539 u8 reserved_at_0[0x120]; 540 u8 geneve_tlv_option_0_data[0x20]; 541 u8 reserved_at_140[0xc0]; 542 }; 543 544 struct mlx5_ifc_cmd_pas_bits { 545 u8 pa_h[0x20]; 546 547 u8 pa_l[0x14]; 548 u8 reserved_at_34[0xc]; 549 }; 550 551 struct mlx5_ifc_uint64_bits { 552 u8 hi[0x20]; 553 554 u8 lo[0x20]; 555 }; 556 557 enum { 558 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0, 559 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7, 560 MLX5_ADS_STAT_RATE_10GBPS = 0x8, 561 MLX5_ADS_STAT_RATE_30GBPS = 0x9, 562 MLX5_ADS_STAT_RATE_5GBPS = 0xa, 563 MLX5_ADS_STAT_RATE_20GBPS = 0xb, 564 MLX5_ADS_STAT_RATE_40GBPS = 0xc, 565 MLX5_ADS_STAT_RATE_60GBPS = 0xd, 566 MLX5_ADS_STAT_RATE_80GBPS = 0xe, 567 MLX5_ADS_STAT_RATE_120GBPS = 0xf, 568 }; 569 570 struct mlx5_ifc_ads_bits { 571 u8 fl[0x1]; 572 u8 free_ar[0x1]; 573 u8 reserved_at_2[0xe]; 574 u8 pkey_index[0x10]; 575 576 u8 reserved_at_20[0x8]; 577 u8 grh[0x1]; 578 u8 mlid[0x7]; 579 u8 rlid[0x10]; 580 581 u8 ack_timeout[0x5]; 582 u8 reserved_at_45[0x3]; 583 u8 src_addr_index[0x8]; 584 u8 reserved_at_50[0x4]; 585 u8 stat_rate[0x4]; 586 u8 hop_limit[0x8]; 587 588 u8 reserved_at_60[0x4]; 589 u8 tclass[0x8]; 590 u8 flow_label[0x14]; 591 592 u8 rgid_rip[16][0x8]; 593 594 u8 reserved_at_100[0x4]; 595 u8 f_dscp[0x1]; 596 u8 f_ecn[0x1]; 597 u8 reserved_at_106[0x1]; 598 u8 f_eth_prio[0x1]; 599 u8 ecn[0x2]; 600 u8 dscp[0x6]; 601 u8 udp_sport[0x10]; 602 603 u8 dei_cfi[0x1]; 604 u8 eth_prio[0x3]; 605 u8 sl[0x4]; 606 u8 vhca_port_num[0x8]; 607 u8 rmac_47_32[0x10]; 608 609 u8 rmac_31_0[0x20]; 610 }; 611 612 struct mlx5_ifc_flow_table_nic_cap_bits { 613 u8 nic_rx_multi_path_tirs[0x1]; 614 u8 nic_rx_multi_path_tirs_fts[0x1]; 615 u8 allow_sniffer_and_nic_rx_shared_tir[0x1]; 616 u8 reserved_at_3[0x1d]; 617 u8 encap_general_header[0x1]; 618 u8 reserved_at_21[0xa]; 619 u8 log_max_packet_reformat_context[0x5]; 620 u8 reserved_at_30[0x6]; 621 u8 max_encap_header_size[0xa]; 622 u8 reserved_at_40[0x1c0]; 623 624 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive; 625 626 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_rdma; 627 628 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer; 629 630 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit; 631 632 u8 reserved_at_a00[0x200]; 633 634 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer; 635 636 u8 reserved_at_e00[0x7200]; 637 }; 638 639 struct mlx5_ifc_flow_table_eswitch_cap_bits { 640 u8 reserved_at_0[0x1a]; 641 u8 multi_fdb_encap[0x1]; 642 u8 reserved_at_1b[0x1]; 643 u8 fdb_multi_path_to_table[0x1]; 644 u8 reserved_at_1d[0x3]; 645 646 u8 reserved_at_20[0x1e0]; 647 648 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb; 649 650 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress; 651 652 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress; 653 654 u8 reserved_at_800[0x7800]; 655 }; 656 657 enum { 658 MLX5_COUNTER_SOURCE_ESWITCH = 0x0, 659 MLX5_COUNTER_FLOW_ESWITCH = 0x1, 660 }; 661 662 struct mlx5_ifc_e_switch_cap_bits { 663 u8 vport_svlan_strip[0x1]; 664 u8 vport_cvlan_strip[0x1]; 665 u8 vport_svlan_insert[0x1]; 666 u8 vport_cvlan_insert_if_not_exist[0x1]; 667 u8 vport_cvlan_insert_overwrite[0x1]; 668 u8 reserved_at_5[0x14]; 669 u8 esw_functions_changed[0x1]; 670 u8 reserved_at_1a[0x1]; 671 u8 ecpf_vport_exists[0x1]; 672 u8 counter_eswitch_affinity[0x1]; 673 u8 merged_eswitch[0x1]; 674 u8 nic_vport_node_guid_modify[0x1]; 675 u8 nic_vport_port_guid_modify[0x1]; 676 677 u8 vxlan_encap_decap[0x1]; 678 u8 nvgre_encap_decap[0x1]; 679 u8 reserved_at_22[0x1]; 680 u8 log_max_fdb_encap_uplink[0x5]; 681 u8 reserved_at_21[0x3]; 682 u8 log_max_packet_reformat_context[0x5]; 683 u8 reserved_2b[0x6]; 684 u8 max_encap_header_size[0xa]; 685 686 u8 reserved_40[0x7c0]; 687 688 }; 689 690 struct mlx5_ifc_qos_cap_bits { 691 u8 packet_pacing[0x1]; 692 u8 esw_scheduling[0x1]; 693 u8 esw_bw_share[0x1]; 694 u8 esw_rate_limit[0x1]; 695 u8 reserved_at_4[0x1]; 696 u8 packet_pacing_burst_bound[0x1]; 697 u8 packet_pacing_typical_size[0x1]; 698 u8 reserved_at_7[0x19]; 699 700 u8 reserved_at_20[0x20]; 701 702 u8 packet_pacing_max_rate[0x20]; 703 704 u8 packet_pacing_min_rate[0x20]; 705 706 u8 reserved_at_80[0x10]; 707 u8 packet_pacing_rate_table_size[0x10]; 708 709 u8 esw_element_type[0x10]; 710 u8 esw_tsar_type[0x10]; 711 712 u8 reserved_at_c0[0x10]; 713 u8 max_qos_para_vport[0x10]; 714 715 u8 max_tsar_bw_share[0x20]; 716 717 u8 reserved_at_100[0x700]; 718 }; 719 720 struct mlx5_ifc_debug_cap_bits { 721 u8 core_dump_general[0x1]; 722 u8 core_dump_qp[0x1]; 723 u8 reserved_at_2[0x1e]; 724 725 u8 reserved_at_20[0x2]; 726 u8 stall_detect[0x1]; 727 u8 reserved_at_23[0x1d]; 728 729 u8 reserved_at_40[0x7c0]; 730 }; 731 732 struct mlx5_ifc_per_protocol_networking_offload_caps_bits { 733 u8 csum_cap[0x1]; 734 u8 vlan_cap[0x1]; 735 u8 lro_cap[0x1]; 736 u8 lro_psh_flag[0x1]; 737 u8 lro_time_stamp[0x1]; 738 u8 reserved_at_5[0x2]; 739 u8 wqe_vlan_insert[0x1]; 740 u8 self_lb_en_modifiable[0x1]; 741 u8 reserved_at_9[0x2]; 742 u8 max_lso_cap[0x5]; 743 u8 multi_pkt_send_wqe[0x2]; 744 u8 wqe_inline_mode[0x2]; 745 u8 rss_ind_tbl_cap[0x4]; 746 u8 reg_umr_sq[0x1]; 747 u8 scatter_fcs[0x1]; 748 u8 enhanced_multi_pkt_send_wqe[0x1]; 749 u8 tunnel_lso_const_out_ip_id[0x1]; 750 u8 reserved_at_1c[0x2]; 751 u8 tunnel_stateless_gre[0x1]; 752 u8 tunnel_stateless_vxlan[0x1]; 753 754 u8 swp[0x1]; 755 u8 swp_csum[0x1]; 756 u8 swp_lso[0x1]; 757 u8 reserved_at_23[0xd]; 758 u8 max_vxlan_udp_ports[0x8]; 759 u8 reserved_at_38[0x6]; 760 u8 max_geneve_opt_len[0x1]; 761 u8 tunnel_stateless_geneve_rx[0x1]; 762 763 u8 reserved_at_40[0x10]; 764 u8 lro_min_mss_size[0x10]; 765 766 u8 reserved_at_60[0x120]; 767 768 u8 lro_timer_supported_periods[4][0x20]; 769 770 u8 reserved_at_200[0x600]; 771 }; 772 773 struct mlx5_ifc_roce_cap_bits { 774 u8 roce_apm[0x1]; 775 u8 reserved_at_1[0x1f]; 776 777 u8 reserved_at_20[0x60]; 778 779 u8 reserved_at_80[0xc]; 780 u8 l3_type[0x4]; 781 u8 reserved_at_90[0x8]; 782 u8 roce_version[0x8]; 783 784 u8 reserved_at_a0[0x10]; 785 u8 r_roce_dest_udp_port[0x10]; 786 787 u8 r_roce_max_src_udp_port[0x10]; 788 u8 r_roce_min_src_udp_port[0x10]; 789 790 u8 reserved_at_e0[0x10]; 791 u8 roce_address_table_size[0x10]; 792 793 u8 reserved_at_100[0x700]; 794 }; 795 796 struct mlx5_ifc_device_mem_cap_bits { 797 u8 memic[0x1]; 798 u8 reserved_at_1[0x1f]; 799 800 u8 reserved_at_20[0xb]; 801 u8 log_min_memic_alloc_size[0x5]; 802 u8 reserved_at_30[0x8]; 803 u8 log_max_memic_addr_alignment[0x8]; 804 805 u8 memic_bar_start_addr[0x40]; 806 807 u8 memic_bar_size[0x20]; 808 809 u8 max_memic_size[0x20]; 810 811 u8 steering_sw_icm_start_address[0x40]; 812 813 u8 reserved_at_100[0x8]; 814 u8 log_header_modify_sw_icm_size[0x8]; 815 u8 reserved_at_110[0x2]; 816 u8 log_sw_icm_alloc_granularity[0x6]; 817 u8 log_steering_sw_icm_size[0x8]; 818 819 u8 reserved_at_120[0x20]; 820 821 u8 header_modify_sw_icm_start_address[0x40]; 822 823 u8 reserved_at_180[0x680]; 824 }; 825 826 enum { 827 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0, 828 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2, 829 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4, 830 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8, 831 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10, 832 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20, 833 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40, 834 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80, 835 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100, 836 }; 837 838 enum { 839 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1, 840 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2, 841 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4, 842 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8, 843 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10, 844 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20, 845 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40, 846 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80, 847 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100, 848 }; 849 850 struct mlx5_ifc_atomic_caps_bits { 851 u8 reserved_at_0[0x40]; 852 853 u8 atomic_req_8B_endianness_mode[0x2]; 854 u8 reserved_at_42[0x4]; 855 u8 supported_atomic_req_8B_endianness_mode_1[0x1]; 856 857 u8 reserved_at_47[0x19]; 858 859 u8 reserved_at_60[0x20]; 860 861 u8 reserved_at_80[0x10]; 862 u8 atomic_operations[0x10]; 863 864 u8 reserved_at_a0[0x10]; 865 u8 atomic_size_qp[0x10]; 866 867 u8 reserved_at_c0[0x10]; 868 u8 atomic_size_dc[0x10]; 869 870 u8 reserved_at_e0[0x720]; 871 }; 872 873 struct mlx5_ifc_odp_cap_bits { 874 u8 reserved_at_0[0x40]; 875 876 u8 sig[0x1]; 877 u8 reserved_at_41[0x1f]; 878 879 u8 reserved_at_60[0x20]; 880 881 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps; 882 883 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps; 884 885 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps; 886 887 struct mlx5_ifc_odp_per_transport_service_cap_bits xrc_odp_caps; 888 889 u8 reserved_at_100[0x700]; 890 }; 891 892 struct mlx5_ifc_calc_op { 893 u8 reserved_at_0[0x10]; 894 u8 reserved_at_10[0x9]; 895 u8 op_swap_endianness[0x1]; 896 u8 op_min[0x1]; 897 u8 op_xor[0x1]; 898 u8 op_or[0x1]; 899 u8 op_and[0x1]; 900 u8 op_max[0x1]; 901 u8 op_add[0x1]; 902 }; 903 904 struct mlx5_ifc_vector_calc_cap_bits { 905 u8 calc_matrix[0x1]; 906 u8 reserved_at_1[0x1f]; 907 u8 reserved_at_20[0x8]; 908 u8 max_vec_count[0x8]; 909 u8 reserved_at_30[0xd]; 910 u8 max_chunk_size[0x3]; 911 struct mlx5_ifc_calc_op calc0; 912 struct mlx5_ifc_calc_op calc1; 913 struct mlx5_ifc_calc_op calc2; 914 struct mlx5_ifc_calc_op calc3; 915 916 u8 reserved_at_c0[0x720]; 917 }; 918 919 enum { 920 MLX5_WQ_TYPE_LINKED_LIST = 0x0, 921 MLX5_WQ_TYPE_CYCLIC = 0x1, 922 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2, 923 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3, 924 }; 925 926 enum { 927 MLX5_WQ_END_PAD_MODE_NONE = 0x0, 928 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1, 929 }; 930 931 enum { 932 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0, 933 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1, 934 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2, 935 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3, 936 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4, 937 }; 938 939 enum { 940 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0, 941 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1, 942 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2, 943 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3, 944 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4, 945 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5, 946 }; 947 948 enum { 949 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0, 950 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1, 951 }; 952 953 enum { 954 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0, 955 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1, 956 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3, 957 }; 958 959 enum { 960 MLX5_CAP_PORT_TYPE_IB = 0x0, 961 MLX5_CAP_PORT_TYPE_ETH = 0x1, 962 }; 963 964 enum { 965 MLX5_CAP_UMR_FENCE_STRONG = 0x0, 966 MLX5_CAP_UMR_FENCE_SMALL = 0x1, 967 MLX5_CAP_UMR_FENCE_NONE = 0x2, 968 }; 969 970 enum { 971 MLX5_UCTX_CAP_RAW_TX = 1UL << 0, 972 MLX5_UCTX_CAP_INTERNAL_DEV_RES = 1UL << 1, 973 }; 974 975 struct mlx5_ifc_cmd_hca_cap_bits { 976 u8 reserved_at_0[0x30]; 977 u8 vhca_id[0x10]; 978 979 u8 reserved_at_40[0x40]; 980 981 u8 log_max_srq_sz[0x8]; 982 u8 log_max_qp_sz[0x8]; 983 u8 reserved_at_90[0x8]; 984 u8 prio_tag_required[0x1]; 985 u8 reserved_at_99[0x2]; 986 u8 log_max_qp[0x5]; 987 988 u8 reserved_at_a0[0xb]; 989 u8 log_max_srq[0x5]; 990 u8 reserved_at_b0[0x10]; 991 992 u8 reserved_at_c0[0x8]; 993 u8 log_max_cq_sz[0x8]; 994 u8 reserved_at_d0[0xb]; 995 u8 log_max_cq[0x5]; 996 997 u8 log_max_eq_sz[0x8]; 998 u8 reserved_at_e8[0x2]; 999 u8 log_max_mkey[0x6]; 1000 u8 reserved_at_f0[0x8]; 1001 u8 dump_fill_mkey[0x1]; 1002 u8 reserved_at_f9[0x2]; 1003 u8 fast_teardown[0x1]; 1004 u8 log_max_eq[0x4]; 1005 1006 u8 max_indirection[0x8]; 1007 u8 fixed_buffer_size[0x1]; 1008 u8 log_max_mrw_sz[0x7]; 1009 u8 force_teardown[0x1]; 1010 u8 reserved_at_111[0x1]; 1011 u8 log_max_bsf_list_size[0x6]; 1012 u8 umr_extended_translation_offset[0x1]; 1013 u8 null_mkey[0x1]; 1014 u8 log_max_klm_list_size[0x6]; 1015 1016 u8 reserved_at_120[0xa]; 1017 u8 log_max_ra_req_dc[0x6]; 1018 u8 reserved_at_130[0xa]; 1019 u8 log_max_ra_res_dc[0x6]; 1020 1021 u8 reserved_at_140[0xa]; 1022 u8 log_max_ra_req_qp[0x6]; 1023 u8 reserved_at_150[0xa]; 1024 u8 log_max_ra_res_qp[0x6]; 1025 1026 u8 end_pad[0x1]; 1027 u8 cc_query_allowed[0x1]; 1028 u8 cc_modify_allowed[0x1]; 1029 u8 start_pad[0x1]; 1030 u8 cache_line_128byte[0x1]; 1031 u8 reserved_at_165[0xa]; 1032 u8 qcam_reg[0x1]; 1033 u8 gid_table_size[0x10]; 1034 1035 u8 out_of_seq_cnt[0x1]; 1036 u8 vport_counters[0x1]; 1037 u8 retransmission_q_counters[0x1]; 1038 u8 debug[0x1]; 1039 u8 modify_rq_counter_set_id[0x1]; 1040 u8 rq_delay_drop[0x1]; 1041 u8 max_qp_cnt[0xa]; 1042 u8 pkey_table_size[0x10]; 1043 1044 u8 vport_group_manager[0x1]; 1045 u8 vhca_group_manager[0x1]; 1046 u8 ib_virt[0x1]; 1047 u8 eth_virt[0x1]; 1048 u8 vnic_env_queue_counters[0x1]; 1049 u8 ets[0x1]; 1050 u8 nic_flow_table[0x1]; 1051 u8 eswitch_manager[0x1]; 1052 u8 device_memory[0x1]; 1053 u8 mcam_reg[0x1]; 1054 u8 pcam_reg[0x1]; 1055 u8 local_ca_ack_delay[0x5]; 1056 u8 port_module_event[0x1]; 1057 u8 enhanced_error_q_counters[0x1]; 1058 u8 ports_check[0x1]; 1059 u8 reserved_at_1b3[0x1]; 1060 u8 disable_link_up[0x1]; 1061 u8 beacon_led[0x1]; 1062 u8 port_type[0x2]; 1063 u8 num_ports[0x8]; 1064 1065 u8 reserved_at_1c0[0x1]; 1066 u8 pps[0x1]; 1067 u8 pps_modify[0x1]; 1068 u8 log_max_msg[0x5]; 1069 u8 reserved_at_1c8[0x4]; 1070 u8 max_tc[0x4]; 1071 u8 temp_warn_event[0x1]; 1072 u8 dcbx[0x1]; 1073 u8 general_notification_event[0x1]; 1074 u8 reserved_at_1d3[0x2]; 1075 u8 fpga[0x1]; 1076 u8 rol_s[0x1]; 1077 u8 rol_g[0x1]; 1078 u8 reserved_at_1d8[0x1]; 1079 u8 wol_s[0x1]; 1080 u8 wol_g[0x1]; 1081 u8 wol_a[0x1]; 1082 u8 wol_b[0x1]; 1083 u8 wol_m[0x1]; 1084 u8 wol_u[0x1]; 1085 u8 wol_p[0x1]; 1086 1087 u8 stat_rate_support[0x10]; 1088 u8 reserved_at_1f0[0xc]; 1089 u8 cqe_version[0x4]; 1090 1091 u8 compact_address_vector[0x1]; 1092 u8 striding_rq[0x1]; 1093 u8 reserved_at_202[0x1]; 1094 u8 ipoib_enhanced_offloads[0x1]; 1095 u8 ipoib_basic_offloads[0x1]; 1096 u8 reserved_at_205[0x1]; 1097 u8 repeated_block_disabled[0x1]; 1098 u8 umr_modify_entity_size_disabled[0x1]; 1099 u8 umr_modify_atomic_disabled[0x1]; 1100 u8 umr_indirect_mkey_disabled[0x1]; 1101 u8 umr_fence[0x2]; 1102 u8 dc_req_scat_data_cqe[0x1]; 1103 u8 reserved_at_20d[0x2]; 1104 u8 drain_sigerr[0x1]; 1105 u8 cmdif_checksum[0x2]; 1106 u8 sigerr_cqe[0x1]; 1107 u8 reserved_at_213[0x1]; 1108 u8 wq_signature[0x1]; 1109 u8 sctr_data_cqe[0x1]; 1110 u8 reserved_at_216[0x1]; 1111 u8 sho[0x1]; 1112 u8 tph[0x1]; 1113 u8 rf[0x1]; 1114 u8 dct[0x1]; 1115 u8 qos[0x1]; 1116 u8 eth_net_offloads[0x1]; 1117 u8 roce[0x1]; 1118 u8 atomic[0x1]; 1119 u8 reserved_at_21f[0x1]; 1120 1121 u8 cq_oi[0x1]; 1122 u8 cq_resize[0x1]; 1123 u8 cq_moderation[0x1]; 1124 u8 reserved_at_223[0x3]; 1125 u8 cq_eq_remap[0x1]; 1126 u8 pg[0x1]; 1127 u8 block_lb_mc[0x1]; 1128 u8 reserved_at_229[0x1]; 1129 u8 scqe_break_moderation[0x1]; 1130 u8 cq_period_start_from_cqe[0x1]; 1131 u8 cd[0x1]; 1132 u8 reserved_at_22d[0x1]; 1133 u8 apm[0x1]; 1134 u8 vector_calc[0x1]; 1135 u8 umr_ptr_rlky[0x1]; 1136 u8 imaicl[0x1]; 1137 u8 qp_packet_based[0x1]; 1138 u8 reserved_at_233[0x3]; 1139 u8 qkv[0x1]; 1140 u8 pkv[0x1]; 1141 u8 set_deth_sqpn[0x1]; 1142 u8 reserved_at_239[0x3]; 1143 u8 xrc[0x1]; 1144 u8 ud[0x1]; 1145 u8 uc[0x1]; 1146 u8 rc[0x1]; 1147 1148 u8 uar_4k[0x1]; 1149 u8 reserved_at_241[0x9]; 1150 u8 uar_sz[0x6]; 1151 u8 reserved_at_250[0x8]; 1152 u8 log_pg_sz[0x8]; 1153 1154 u8 bf[0x1]; 1155 u8 driver_version[0x1]; 1156 u8 pad_tx_eth_packet[0x1]; 1157 u8 reserved_at_263[0x8]; 1158 u8 log_bf_reg_size[0x5]; 1159 1160 u8 reserved_at_270[0xb]; 1161 u8 lag_master[0x1]; 1162 u8 num_lag_ports[0x4]; 1163 1164 u8 reserved_at_280[0x10]; 1165 u8 max_wqe_sz_sq[0x10]; 1166 1167 u8 reserved_at_2a0[0x10]; 1168 u8 max_wqe_sz_rq[0x10]; 1169 1170 u8 max_flow_counter_31_16[0x10]; 1171 u8 max_wqe_sz_sq_dc[0x10]; 1172 1173 u8 reserved_at_2e0[0x7]; 1174 u8 max_qp_mcg[0x19]; 1175 1176 u8 reserved_at_300[0x18]; 1177 u8 log_max_mcg[0x8]; 1178 1179 u8 reserved_at_320[0x3]; 1180 u8 log_max_transport_domain[0x5]; 1181 u8 reserved_at_328[0x3]; 1182 u8 log_max_pd[0x5]; 1183 u8 reserved_at_330[0xb]; 1184 u8 log_max_xrcd[0x5]; 1185 1186 u8 nic_receive_steering_discard[0x1]; 1187 u8 receive_discard_vport_down[0x1]; 1188 u8 transmit_discard_vport_down[0x1]; 1189 u8 reserved_at_343[0x5]; 1190 u8 log_max_flow_counter_bulk[0x8]; 1191 u8 max_flow_counter_15_0[0x10]; 1192 1193 1194 u8 reserved_at_360[0x3]; 1195 u8 log_max_rq[0x5]; 1196 u8 reserved_at_368[0x3]; 1197 u8 log_max_sq[0x5]; 1198 u8 reserved_at_370[0x3]; 1199 u8 log_max_tir[0x5]; 1200 u8 reserved_at_378[0x3]; 1201 u8 log_max_tis[0x5]; 1202 1203 u8 basic_cyclic_rcv_wqe[0x1]; 1204 u8 reserved_at_381[0x2]; 1205 u8 log_max_rmp[0x5]; 1206 u8 reserved_at_388[0x3]; 1207 u8 log_max_rqt[0x5]; 1208 u8 reserved_at_390[0x3]; 1209 u8 log_max_rqt_size[0x5]; 1210 u8 reserved_at_398[0x3]; 1211 u8 log_max_tis_per_sq[0x5]; 1212 1213 u8 ext_stride_num_range[0x1]; 1214 u8 reserved_at_3a1[0x2]; 1215 u8 log_max_stride_sz_rq[0x5]; 1216 u8 reserved_at_3a8[0x3]; 1217 u8 log_min_stride_sz_rq[0x5]; 1218 u8 reserved_at_3b0[0x3]; 1219 u8 log_max_stride_sz_sq[0x5]; 1220 u8 reserved_at_3b8[0x3]; 1221 u8 log_min_stride_sz_sq[0x5]; 1222 1223 u8 hairpin[0x1]; 1224 u8 reserved_at_3c1[0x2]; 1225 u8 log_max_hairpin_queues[0x5]; 1226 u8 reserved_at_3c8[0x3]; 1227 u8 log_max_hairpin_wq_data_sz[0x5]; 1228 u8 reserved_at_3d0[0x3]; 1229 u8 log_max_hairpin_num_packets[0x5]; 1230 u8 reserved_at_3d8[0x3]; 1231 u8 log_max_wq_sz[0x5]; 1232 1233 u8 nic_vport_change_event[0x1]; 1234 u8 disable_local_lb_uc[0x1]; 1235 u8 disable_local_lb_mc[0x1]; 1236 u8 log_min_hairpin_wq_data_sz[0x5]; 1237 u8 reserved_at_3e8[0x3]; 1238 u8 log_max_vlan_list[0x5]; 1239 u8 reserved_at_3f0[0x3]; 1240 u8 log_max_current_mc_list[0x5]; 1241 u8 reserved_at_3f8[0x3]; 1242 u8 log_max_current_uc_list[0x5]; 1243 1244 u8 general_obj_types[0x40]; 1245 1246 u8 reserved_at_440[0x20]; 1247 1248 u8 reserved_at_460[0x3]; 1249 u8 log_max_uctx[0x5]; 1250 u8 reserved_at_468[0x3]; 1251 u8 log_max_umem[0x5]; 1252 u8 max_num_eqs[0x10]; 1253 1254 u8 reserved_at_480[0x3]; 1255 u8 log_max_l2_table[0x5]; 1256 u8 reserved_at_488[0x8]; 1257 u8 log_uar_page_sz[0x10]; 1258 1259 u8 reserved_at_4a0[0x20]; 1260 u8 device_frequency_mhz[0x20]; 1261 u8 device_frequency_khz[0x20]; 1262 1263 u8 reserved_at_500[0x20]; 1264 u8 num_of_uars_per_page[0x20]; 1265 1266 u8 flex_parser_protocols[0x20]; 1267 1268 u8 max_geneve_tlv_options[0x8]; 1269 u8 reserved_at_568[0x3]; 1270 u8 max_geneve_tlv_option_data_len[0x5]; 1271 u8 reserved_at_570[0x10]; 1272 1273 u8 reserved_at_580[0x3c]; 1274 u8 mini_cqe_resp_stride_index[0x1]; 1275 u8 cqe_128_always[0x1]; 1276 u8 cqe_compression_128[0x1]; 1277 u8 cqe_compression[0x1]; 1278 1279 u8 cqe_compression_timeout[0x10]; 1280 u8 cqe_compression_max_num[0x10]; 1281 1282 u8 reserved_at_5e0[0x10]; 1283 u8 tag_matching[0x1]; 1284 u8 rndv_offload_rc[0x1]; 1285 u8 rndv_offload_dc[0x1]; 1286 u8 log_tag_matching_list_sz[0x5]; 1287 u8 reserved_at_5f8[0x3]; 1288 u8 log_max_xrq[0x5]; 1289 1290 u8 affiliate_nic_vport_criteria[0x8]; 1291 u8 native_port_num[0x8]; 1292 u8 num_vhca_ports[0x8]; 1293 u8 reserved_at_618[0x6]; 1294 u8 sw_owner_id[0x1]; 1295 u8 reserved_at_61f[0x1]; 1296 1297 u8 max_num_of_monitor_counters[0x10]; 1298 u8 num_ppcnt_monitor_counters[0x10]; 1299 1300 u8 reserved_at_640[0x10]; 1301 u8 num_q_monitor_counters[0x10]; 1302 1303 u8 reserved_at_660[0x40]; 1304 1305 u8 uctx_cap[0x20]; 1306 1307 u8 reserved_at_6c0[0x4]; 1308 u8 flex_parser_id_geneve_tlv_option_0[0x4]; 1309 u8 reserved_at_6c8[0x138]; 1310 }; 1311 1312 enum mlx5_flow_destination_type { 1313 MLX5_FLOW_DESTINATION_TYPE_VPORT = 0x0, 1314 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1, 1315 MLX5_FLOW_DESTINATION_TYPE_TIR = 0x2, 1316 1317 MLX5_FLOW_DESTINATION_TYPE_PORT = 0x99, 1318 MLX5_FLOW_DESTINATION_TYPE_COUNTER = 0x100, 1319 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE_NUM = 0x101, 1320 }; 1321 1322 enum mlx5_flow_table_miss_action { 1323 MLX5_FLOW_TABLE_MISS_ACTION_DEF, 1324 MLX5_FLOW_TABLE_MISS_ACTION_FWD, 1325 MLX5_FLOW_TABLE_MISS_ACTION_SWITCH_DOMAIN, 1326 }; 1327 1328 struct mlx5_ifc_dest_format_struct_bits { 1329 u8 destination_type[0x8]; 1330 u8 destination_id[0x18]; 1331 1332 u8 destination_eswitch_owner_vhca_id_valid[0x1]; 1333 u8 packet_reformat[0x1]; 1334 u8 reserved_at_22[0xe]; 1335 u8 destination_eswitch_owner_vhca_id[0x10]; 1336 }; 1337 1338 struct mlx5_ifc_flow_counter_list_bits { 1339 u8 flow_counter_id[0x20]; 1340 1341 u8 reserved_at_20[0x20]; 1342 }; 1343 1344 struct mlx5_ifc_extended_dest_format_bits { 1345 struct mlx5_ifc_dest_format_struct_bits destination_entry; 1346 1347 u8 packet_reformat_id[0x20]; 1348 1349 u8 reserved_at_60[0x20]; 1350 }; 1351 1352 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits { 1353 struct mlx5_ifc_dest_format_struct_bits dest_format_struct; 1354 struct mlx5_ifc_flow_counter_list_bits flow_counter_list; 1355 u8 reserved_at_0[0x40]; 1356 }; 1357 1358 struct mlx5_ifc_fte_match_param_bits { 1359 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers; 1360 1361 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters; 1362 1363 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers; 1364 1365 struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2; 1366 1367 struct mlx5_ifc_fte_match_set_misc3_bits misc_parameters_3; 1368 1369 u8 reserved_at_a00[0x600]; 1370 }; 1371 1372 enum { 1373 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0, 1374 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1, 1375 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2, 1376 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3, 1377 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4, 1378 }; 1379 1380 struct mlx5_ifc_rx_hash_field_select_bits { 1381 u8 l3_prot_type[0x1]; 1382 u8 l4_prot_type[0x1]; 1383 u8 selected_fields[0x1e]; 1384 }; 1385 1386 enum { 1387 MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0, 1388 MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1, 1389 }; 1390 1391 enum { 1392 MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0, 1393 MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1, 1394 }; 1395 1396 struct mlx5_ifc_wq_bits { 1397 u8 wq_type[0x4]; 1398 u8 wq_signature[0x1]; 1399 u8 end_padding_mode[0x2]; 1400 u8 cd_slave[0x1]; 1401 u8 reserved_at_8[0x18]; 1402 1403 u8 hds_skip_first_sge[0x1]; 1404 u8 log2_hds_buf_size[0x3]; 1405 u8 reserved_at_24[0x7]; 1406 u8 page_offset[0x5]; 1407 u8 lwm[0x10]; 1408 1409 u8 reserved_at_40[0x8]; 1410 u8 pd[0x18]; 1411 1412 u8 reserved_at_60[0x8]; 1413 u8 uar_page[0x18]; 1414 1415 u8 dbr_addr[0x40]; 1416 1417 u8 hw_counter[0x20]; 1418 1419 u8 sw_counter[0x20]; 1420 1421 u8 reserved_at_100[0xc]; 1422 u8 log_wq_stride[0x4]; 1423 u8 reserved_at_110[0x3]; 1424 u8 log_wq_pg_sz[0x5]; 1425 u8 reserved_at_118[0x3]; 1426 u8 log_wq_sz[0x5]; 1427 1428 u8 dbr_umem_valid[0x1]; 1429 u8 wq_umem_valid[0x1]; 1430 u8 reserved_at_122[0x1]; 1431 u8 log_hairpin_num_packets[0x5]; 1432 u8 reserved_at_128[0x3]; 1433 u8 log_hairpin_data_sz[0x5]; 1434 1435 u8 reserved_at_130[0x4]; 1436 u8 log_wqe_num_of_strides[0x4]; 1437 u8 two_byte_shift_en[0x1]; 1438 u8 reserved_at_139[0x4]; 1439 u8 log_wqe_stride_size[0x3]; 1440 1441 u8 reserved_at_140[0x4c0]; 1442 1443 struct mlx5_ifc_cmd_pas_bits pas[0]; 1444 }; 1445 1446 struct mlx5_ifc_rq_num_bits { 1447 u8 reserved_at_0[0x8]; 1448 u8 rq_num[0x18]; 1449 }; 1450 1451 struct mlx5_ifc_mac_address_layout_bits { 1452 u8 reserved_at_0[0x10]; 1453 u8 mac_addr_47_32[0x10]; 1454 1455 u8 mac_addr_31_0[0x20]; 1456 }; 1457 1458 struct mlx5_ifc_vlan_layout_bits { 1459 u8 reserved_at_0[0x14]; 1460 u8 vlan[0x0c]; 1461 1462 u8 reserved_at_20[0x20]; 1463 }; 1464 1465 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits { 1466 u8 reserved_at_0[0xa0]; 1467 1468 u8 min_time_between_cnps[0x20]; 1469 1470 u8 reserved_at_c0[0x12]; 1471 u8 cnp_dscp[0x6]; 1472 u8 reserved_at_d8[0x4]; 1473 u8 cnp_prio_mode[0x1]; 1474 u8 cnp_802p_prio[0x3]; 1475 1476 u8 reserved_at_e0[0x720]; 1477 }; 1478 1479 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits { 1480 u8 reserved_at_0[0x60]; 1481 1482 u8 reserved_at_60[0x4]; 1483 u8 clamp_tgt_rate[0x1]; 1484 u8 reserved_at_65[0x3]; 1485 u8 clamp_tgt_rate_after_time_inc[0x1]; 1486 u8 reserved_at_69[0x17]; 1487 1488 u8 reserved_at_80[0x20]; 1489 1490 u8 rpg_time_reset[0x20]; 1491 1492 u8 rpg_byte_reset[0x20]; 1493 1494 u8 rpg_threshold[0x20]; 1495 1496 u8 rpg_max_rate[0x20]; 1497 1498 u8 rpg_ai_rate[0x20]; 1499 1500 u8 rpg_hai_rate[0x20]; 1501 1502 u8 rpg_gd[0x20]; 1503 1504 u8 rpg_min_dec_fac[0x20]; 1505 1506 u8 rpg_min_rate[0x20]; 1507 1508 u8 reserved_at_1c0[0xe0]; 1509 1510 u8 rate_to_set_on_first_cnp[0x20]; 1511 1512 u8 dce_tcp_g[0x20]; 1513 1514 u8 dce_tcp_rtt[0x20]; 1515 1516 u8 rate_reduce_monitor_period[0x20]; 1517 1518 u8 reserved_at_320[0x20]; 1519 1520 u8 initial_alpha_value[0x20]; 1521 1522 u8 reserved_at_360[0x4a0]; 1523 }; 1524 1525 struct mlx5_ifc_cong_control_802_1qau_rp_bits { 1526 u8 reserved_at_0[0x80]; 1527 1528 u8 rppp_max_rps[0x20]; 1529 1530 u8 rpg_time_reset[0x20]; 1531 1532 u8 rpg_byte_reset[0x20]; 1533 1534 u8 rpg_threshold[0x20]; 1535 1536 u8 rpg_max_rate[0x20]; 1537 1538 u8 rpg_ai_rate[0x20]; 1539 1540 u8 rpg_hai_rate[0x20]; 1541 1542 u8 rpg_gd[0x20]; 1543 1544 u8 rpg_min_dec_fac[0x20]; 1545 1546 u8 rpg_min_rate[0x20]; 1547 1548 u8 reserved_at_1c0[0x640]; 1549 }; 1550 1551 enum { 1552 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1, 1553 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2, 1554 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4, 1555 }; 1556 1557 struct mlx5_ifc_resize_field_select_bits { 1558 u8 resize_field_select[0x20]; 1559 }; 1560 1561 enum { 1562 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1, 1563 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2, 1564 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4, 1565 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8, 1566 }; 1567 1568 struct mlx5_ifc_modify_field_select_bits { 1569 u8 modify_field_select[0x20]; 1570 }; 1571 1572 struct mlx5_ifc_field_select_r_roce_np_bits { 1573 u8 field_select_r_roce_np[0x20]; 1574 }; 1575 1576 struct mlx5_ifc_field_select_r_roce_rp_bits { 1577 u8 field_select_r_roce_rp[0x20]; 1578 }; 1579 1580 enum { 1581 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4, 1582 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8, 1583 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10, 1584 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20, 1585 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40, 1586 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80, 1587 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100, 1588 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200, 1589 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400, 1590 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800, 1591 }; 1592 1593 struct mlx5_ifc_field_select_802_1qau_rp_bits { 1594 u8 field_select_8021qaurp[0x20]; 1595 }; 1596 1597 struct mlx5_ifc_phys_layer_cntrs_bits { 1598 u8 time_since_last_clear_high[0x20]; 1599 1600 u8 time_since_last_clear_low[0x20]; 1601 1602 u8 symbol_errors_high[0x20]; 1603 1604 u8 symbol_errors_low[0x20]; 1605 1606 u8 sync_headers_errors_high[0x20]; 1607 1608 u8 sync_headers_errors_low[0x20]; 1609 1610 u8 edpl_bip_errors_lane0_high[0x20]; 1611 1612 u8 edpl_bip_errors_lane0_low[0x20]; 1613 1614 u8 edpl_bip_errors_lane1_high[0x20]; 1615 1616 u8 edpl_bip_errors_lane1_low[0x20]; 1617 1618 u8 edpl_bip_errors_lane2_high[0x20]; 1619 1620 u8 edpl_bip_errors_lane2_low[0x20]; 1621 1622 u8 edpl_bip_errors_lane3_high[0x20]; 1623 1624 u8 edpl_bip_errors_lane3_low[0x20]; 1625 1626 u8 fc_fec_corrected_blocks_lane0_high[0x20]; 1627 1628 u8 fc_fec_corrected_blocks_lane0_low[0x20]; 1629 1630 u8 fc_fec_corrected_blocks_lane1_high[0x20]; 1631 1632 u8 fc_fec_corrected_blocks_lane1_low[0x20]; 1633 1634 u8 fc_fec_corrected_blocks_lane2_high[0x20]; 1635 1636 u8 fc_fec_corrected_blocks_lane2_low[0x20]; 1637 1638 u8 fc_fec_corrected_blocks_lane3_high[0x20]; 1639 1640 u8 fc_fec_corrected_blocks_lane3_low[0x20]; 1641 1642 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20]; 1643 1644 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20]; 1645 1646 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20]; 1647 1648 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20]; 1649 1650 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20]; 1651 1652 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20]; 1653 1654 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20]; 1655 1656 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20]; 1657 1658 u8 rs_fec_corrected_blocks_high[0x20]; 1659 1660 u8 rs_fec_corrected_blocks_low[0x20]; 1661 1662 u8 rs_fec_uncorrectable_blocks_high[0x20]; 1663 1664 u8 rs_fec_uncorrectable_blocks_low[0x20]; 1665 1666 u8 rs_fec_no_errors_blocks_high[0x20]; 1667 1668 u8 rs_fec_no_errors_blocks_low[0x20]; 1669 1670 u8 rs_fec_single_error_blocks_high[0x20]; 1671 1672 u8 rs_fec_single_error_blocks_low[0x20]; 1673 1674 u8 rs_fec_corrected_symbols_total_high[0x20]; 1675 1676 u8 rs_fec_corrected_symbols_total_low[0x20]; 1677 1678 u8 rs_fec_corrected_symbols_lane0_high[0x20]; 1679 1680 u8 rs_fec_corrected_symbols_lane0_low[0x20]; 1681 1682 u8 rs_fec_corrected_symbols_lane1_high[0x20]; 1683 1684 u8 rs_fec_corrected_symbols_lane1_low[0x20]; 1685 1686 u8 rs_fec_corrected_symbols_lane2_high[0x20]; 1687 1688 u8 rs_fec_corrected_symbols_lane2_low[0x20]; 1689 1690 u8 rs_fec_corrected_symbols_lane3_high[0x20]; 1691 1692 u8 rs_fec_corrected_symbols_lane3_low[0x20]; 1693 1694 u8 link_down_events[0x20]; 1695 1696 u8 successful_recovery_events[0x20]; 1697 1698 u8 reserved_at_640[0x180]; 1699 }; 1700 1701 struct mlx5_ifc_phys_layer_statistical_cntrs_bits { 1702 u8 time_since_last_clear_high[0x20]; 1703 1704 u8 time_since_last_clear_low[0x20]; 1705 1706 u8 phy_received_bits_high[0x20]; 1707 1708 u8 phy_received_bits_low[0x20]; 1709 1710 u8 phy_symbol_errors_high[0x20]; 1711 1712 u8 phy_symbol_errors_low[0x20]; 1713 1714 u8 phy_corrected_bits_high[0x20]; 1715 1716 u8 phy_corrected_bits_low[0x20]; 1717 1718 u8 phy_corrected_bits_lane0_high[0x20]; 1719 1720 u8 phy_corrected_bits_lane0_low[0x20]; 1721 1722 u8 phy_corrected_bits_lane1_high[0x20]; 1723 1724 u8 phy_corrected_bits_lane1_low[0x20]; 1725 1726 u8 phy_corrected_bits_lane2_high[0x20]; 1727 1728 u8 phy_corrected_bits_lane2_low[0x20]; 1729 1730 u8 phy_corrected_bits_lane3_high[0x20]; 1731 1732 u8 phy_corrected_bits_lane3_low[0x20]; 1733 1734 u8 reserved_at_200[0x5c0]; 1735 }; 1736 1737 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits { 1738 u8 symbol_error_counter[0x10]; 1739 1740 u8 link_error_recovery_counter[0x8]; 1741 1742 u8 link_downed_counter[0x8]; 1743 1744 u8 port_rcv_errors[0x10]; 1745 1746 u8 port_rcv_remote_physical_errors[0x10]; 1747 1748 u8 port_rcv_switch_relay_errors[0x10]; 1749 1750 u8 port_xmit_discards[0x10]; 1751 1752 u8 port_xmit_constraint_errors[0x8]; 1753 1754 u8 port_rcv_constraint_errors[0x8]; 1755 1756 u8 reserved_at_70[0x8]; 1757 1758 u8 link_overrun_errors[0x8]; 1759 1760 u8 reserved_at_80[0x10]; 1761 1762 u8 vl_15_dropped[0x10]; 1763 1764 u8 reserved_at_a0[0x80]; 1765 1766 u8 port_xmit_wait[0x20]; 1767 }; 1768 1769 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits { 1770 u8 transmit_queue_high[0x20]; 1771 1772 u8 transmit_queue_low[0x20]; 1773 1774 u8 reserved_at_40[0x780]; 1775 }; 1776 1777 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits { 1778 u8 rx_octets_high[0x20]; 1779 1780 u8 rx_octets_low[0x20]; 1781 1782 u8 reserved_at_40[0xc0]; 1783 1784 u8 rx_frames_high[0x20]; 1785 1786 u8 rx_frames_low[0x20]; 1787 1788 u8 tx_octets_high[0x20]; 1789 1790 u8 tx_octets_low[0x20]; 1791 1792 u8 reserved_at_180[0xc0]; 1793 1794 u8 tx_frames_high[0x20]; 1795 1796 u8 tx_frames_low[0x20]; 1797 1798 u8 rx_pause_high[0x20]; 1799 1800 u8 rx_pause_low[0x20]; 1801 1802 u8 rx_pause_duration_high[0x20]; 1803 1804 u8 rx_pause_duration_low[0x20]; 1805 1806 u8 tx_pause_high[0x20]; 1807 1808 u8 tx_pause_low[0x20]; 1809 1810 u8 tx_pause_duration_high[0x20]; 1811 1812 u8 tx_pause_duration_low[0x20]; 1813 1814 u8 rx_pause_transition_high[0x20]; 1815 1816 u8 rx_pause_transition_low[0x20]; 1817 1818 u8 reserved_at_3c0[0x40]; 1819 1820 u8 device_stall_minor_watermark_cnt_high[0x20]; 1821 1822 u8 device_stall_minor_watermark_cnt_low[0x20]; 1823 1824 u8 device_stall_critical_watermark_cnt_high[0x20]; 1825 1826 u8 device_stall_critical_watermark_cnt_low[0x20]; 1827 1828 u8 reserved_at_480[0x340]; 1829 }; 1830 1831 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits { 1832 u8 port_transmit_wait_high[0x20]; 1833 1834 u8 port_transmit_wait_low[0x20]; 1835 1836 u8 reserved_at_40[0x100]; 1837 1838 u8 rx_buffer_almost_full_high[0x20]; 1839 1840 u8 rx_buffer_almost_full_low[0x20]; 1841 1842 u8 rx_buffer_full_high[0x20]; 1843 1844 u8 rx_buffer_full_low[0x20]; 1845 1846 u8 rx_icrc_encapsulated_high[0x20]; 1847 1848 u8 rx_icrc_encapsulated_low[0x20]; 1849 1850 u8 reserved_at_200[0x5c0]; 1851 }; 1852 1853 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits { 1854 u8 dot3stats_alignment_errors_high[0x20]; 1855 1856 u8 dot3stats_alignment_errors_low[0x20]; 1857 1858 u8 dot3stats_fcs_errors_high[0x20]; 1859 1860 u8 dot3stats_fcs_errors_low[0x20]; 1861 1862 u8 dot3stats_single_collision_frames_high[0x20]; 1863 1864 u8 dot3stats_single_collision_frames_low[0x20]; 1865 1866 u8 dot3stats_multiple_collision_frames_high[0x20]; 1867 1868 u8 dot3stats_multiple_collision_frames_low[0x20]; 1869 1870 u8 dot3stats_sqe_test_errors_high[0x20]; 1871 1872 u8 dot3stats_sqe_test_errors_low[0x20]; 1873 1874 u8 dot3stats_deferred_transmissions_high[0x20]; 1875 1876 u8 dot3stats_deferred_transmissions_low[0x20]; 1877 1878 u8 dot3stats_late_collisions_high[0x20]; 1879 1880 u8 dot3stats_late_collisions_low[0x20]; 1881 1882 u8 dot3stats_excessive_collisions_high[0x20]; 1883 1884 u8 dot3stats_excessive_collisions_low[0x20]; 1885 1886 u8 dot3stats_internal_mac_transmit_errors_high[0x20]; 1887 1888 u8 dot3stats_internal_mac_transmit_errors_low[0x20]; 1889 1890 u8 dot3stats_carrier_sense_errors_high[0x20]; 1891 1892 u8 dot3stats_carrier_sense_errors_low[0x20]; 1893 1894 u8 dot3stats_frame_too_longs_high[0x20]; 1895 1896 u8 dot3stats_frame_too_longs_low[0x20]; 1897 1898 u8 dot3stats_internal_mac_receive_errors_high[0x20]; 1899 1900 u8 dot3stats_internal_mac_receive_errors_low[0x20]; 1901 1902 u8 dot3stats_symbol_errors_high[0x20]; 1903 1904 u8 dot3stats_symbol_errors_low[0x20]; 1905 1906 u8 dot3control_in_unknown_opcodes_high[0x20]; 1907 1908 u8 dot3control_in_unknown_opcodes_low[0x20]; 1909 1910 u8 dot3in_pause_frames_high[0x20]; 1911 1912 u8 dot3in_pause_frames_low[0x20]; 1913 1914 u8 dot3out_pause_frames_high[0x20]; 1915 1916 u8 dot3out_pause_frames_low[0x20]; 1917 1918 u8 reserved_at_400[0x3c0]; 1919 }; 1920 1921 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits { 1922 u8 ether_stats_drop_events_high[0x20]; 1923 1924 u8 ether_stats_drop_events_low[0x20]; 1925 1926 u8 ether_stats_octets_high[0x20]; 1927 1928 u8 ether_stats_octets_low[0x20]; 1929 1930 u8 ether_stats_pkts_high[0x20]; 1931 1932 u8 ether_stats_pkts_low[0x20]; 1933 1934 u8 ether_stats_broadcast_pkts_high[0x20]; 1935 1936 u8 ether_stats_broadcast_pkts_low[0x20]; 1937 1938 u8 ether_stats_multicast_pkts_high[0x20]; 1939 1940 u8 ether_stats_multicast_pkts_low[0x20]; 1941 1942 u8 ether_stats_crc_align_errors_high[0x20]; 1943 1944 u8 ether_stats_crc_align_errors_low[0x20]; 1945 1946 u8 ether_stats_undersize_pkts_high[0x20]; 1947 1948 u8 ether_stats_undersize_pkts_low[0x20]; 1949 1950 u8 ether_stats_oversize_pkts_high[0x20]; 1951 1952 u8 ether_stats_oversize_pkts_low[0x20]; 1953 1954 u8 ether_stats_fragments_high[0x20]; 1955 1956 u8 ether_stats_fragments_low[0x20]; 1957 1958 u8 ether_stats_jabbers_high[0x20]; 1959 1960 u8 ether_stats_jabbers_low[0x20]; 1961 1962 u8 ether_stats_collisions_high[0x20]; 1963 1964 u8 ether_stats_collisions_low[0x20]; 1965 1966 u8 ether_stats_pkts64octets_high[0x20]; 1967 1968 u8 ether_stats_pkts64octets_low[0x20]; 1969 1970 u8 ether_stats_pkts65to127octets_high[0x20]; 1971 1972 u8 ether_stats_pkts65to127octets_low[0x20]; 1973 1974 u8 ether_stats_pkts128to255octets_high[0x20]; 1975 1976 u8 ether_stats_pkts128to255octets_low[0x20]; 1977 1978 u8 ether_stats_pkts256to511octets_high[0x20]; 1979 1980 u8 ether_stats_pkts256to511octets_low[0x20]; 1981 1982 u8 ether_stats_pkts512to1023octets_high[0x20]; 1983 1984 u8 ether_stats_pkts512to1023octets_low[0x20]; 1985 1986 u8 ether_stats_pkts1024to1518octets_high[0x20]; 1987 1988 u8 ether_stats_pkts1024to1518octets_low[0x20]; 1989 1990 u8 ether_stats_pkts1519to2047octets_high[0x20]; 1991 1992 u8 ether_stats_pkts1519to2047octets_low[0x20]; 1993 1994 u8 ether_stats_pkts2048to4095octets_high[0x20]; 1995 1996 u8 ether_stats_pkts2048to4095octets_low[0x20]; 1997 1998 u8 ether_stats_pkts4096to8191octets_high[0x20]; 1999 2000 u8 ether_stats_pkts4096to8191octets_low[0x20]; 2001 2002 u8 ether_stats_pkts8192to10239octets_high[0x20]; 2003 2004 u8 ether_stats_pkts8192to10239octets_low[0x20]; 2005 2006 u8 reserved_at_540[0x280]; 2007 }; 2008 2009 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits { 2010 u8 if_in_octets_high[0x20]; 2011 2012 u8 if_in_octets_low[0x20]; 2013 2014 u8 if_in_ucast_pkts_high[0x20]; 2015 2016 u8 if_in_ucast_pkts_low[0x20]; 2017 2018 u8 if_in_discards_high[0x20]; 2019 2020 u8 if_in_discards_low[0x20]; 2021 2022 u8 if_in_errors_high[0x20]; 2023 2024 u8 if_in_errors_low[0x20]; 2025 2026 u8 if_in_unknown_protos_high[0x20]; 2027 2028 u8 if_in_unknown_protos_low[0x20]; 2029 2030 u8 if_out_octets_high[0x20]; 2031 2032 u8 if_out_octets_low[0x20]; 2033 2034 u8 if_out_ucast_pkts_high[0x20]; 2035 2036 u8 if_out_ucast_pkts_low[0x20]; 2037 2038 u8 if_out_discards_high[0x20]; 2039 2040 u8 if_out_discards_low[0x20]; 2041 2042 u8 if_out_errors_high[0x20]; 2043 2044 u8 if_out_errors_low[0x20]; 2045 2046 u8 if_in_multicast_pkts_high[0x20]; 2047 2048 u8 if_in_multicast_pkts_low[0x20]; 2049 2050 u8 if_in_broadcast_pkts_high[0x20]; 2051 2052 u8 if_in_broadcast_pkts_low[0x20]; 2053 2054 u8 if_out_multicast_pkts_high[0x20]; 2055 2056 u8 if_out_multicast_pkts_low[0x20]; 2057 2058 u8 if_out_broadcast_pkts_high[0x20]; 2059 2060 u8 if_out_broadcast_pkts_low[0x20]; 2061 2062 u8 reserved_at_340[0x480]; 2063 }; 2064 2065 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits { 2066 u8 a_frames_transmitted_ok_high[0x20]; 2067 2068 u8 a_frames_transmitted_ok_low[0x20]; 2069 2070 u8 a_frames_received_ok_high[0x20]; 2071 2072 u8 a_frames_received_ok_low[0x20]; 2073 2074 u8 a_frame_check_sequence_errors_high[0x20]; 2075 2076 u8 a_frame_check_sequence_errors_low[0x20]; 2077 2078 u8 a_alignment_errors_high[0x20]; 2079 2080 u8 a_alignment_errors_low[0x20]; 2081 2082 u8 a_octets_transmitted_ok_high[0x20]; 2083 2084 u8 a_octets_transmitted_ok_low[0x20]; 2085 2086 u8 a_octets_received_ok_high[0x20]; 2087 2088 u8 a_octets_received_ok_low[0x20]; 2089 2090 u8 a_multicast_frames_xmitted_ok_high[0x20]; 2091 2092 u8 a_multicast_frames_xmitted_ok_low[0x20]; 2093 2094 u8 a_broadcast_frames_xmitted_ok_high[0x20]; 2095 2096 u8 a_broadcast_frames_xmitted_ok_low[0x20]; 2097 2098 u8 a_multicast_frames_received_ok_high[0x20]; 2099 2100 u8 a_multicast_frames_received_ok_low[0x20]; 2101 2102 u8 a_broadcast_frames_received_ok_high[0x20]; 2103 2104 u8 a_broadcast_frames_received_ok_low[0x20]; 2105 2106 u8 a_in_range_length_errors_high[0x20]; 2107 2108 u8 a_in_range_length_errors_low[0x20]; 2109 2110 u8 a_out_of_range_length_field_high[0x20]; 2111 2112 u8 a_out_of_range_length_field_low[0x20]; 2113 2114 u8 a_frame_too_long_errors_high[0x20]; 2115 2116 u8 a_frame_too_long_errors_low[0x20]; 2117 2118 u8 a_symbol_error_during_carrier_high[0x20]; 2119 2120 u8 a_symbol_error_during_carrier_low[0x20]; 2121 2122 u8 a_mac_control_frames_transmitted_high[0x20]; 2123 2124 u8 a_mac_control_frames_transmitted_low[0x20]; 2125 2126 u8 a_mac_control_frames_received_high[0x20]; 2127 2128 u8 a_mac_control_frames_received_low[0x20]; 2129 2130 u8 a_unsupported_opcodes_received_high[0x20]; 2131 2132 u8 a_unsupported_opcodes_received_low[0x20]; 2133 2134 u8 a_pause_mac_ctrl_frames_received_high[0x20]; 2135 2136 u8 a_pause_mac_ctrl_frames_received_low[0x20]; 2137 2138 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20]; 2139 2140 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20]; 2141 2142 u8 reserved_at_4c0[0x300]; 2143 }; 2144 2145 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits { 2146 u8 life_time_counter_high[0x20]; 2147 2148 u8 life_time_counter_low[0x20]; 2149 2150 u8 rx_errors[0x20]; 2151 2152 u8 tx_errors[0x20]; 2153 2154 u8 l0_to_recovery_eieos[0x20]; 2155 2156 u8 l0_to_recovery_ts[0x20]; 2157 2158 u8 l0_to_recovery_framing[0x20]; 2159 2160 u8 l0_to_recovery_retrain[0x20]; 2161 2162 u8 crc_error_dllp[0x20]; 2163 2164 u8 crc_error_tlp[0x20]; 2165 2166 u8 tx_overflow_buffer_pkt_high[0x20]; 2167 2168 u8 tx_overflow_buffer_pkt_low[0x20]; 2169 2170 u8 outbound_stalled_reads[0x20]; 2171 2172 u8 outbound_stalled_writes[0x20]; 2173 2174 u8 outbound_stalled_reads_events[0x20]; 2175 2176 u8 outbound_stalled_writes_events[0x20]; 2177 2178 u8 reserved_at_200[0x5c0]; 2179 }; 2180 2181 struct mlx5_ifc_cmd_inter_comp_event_bits { 2182 u8 command_completion_vector[0x20]; 2183 2184 u8 reserved_at_20[0xc0]; 2185 }; 2186 2187 struct mlx5_ifc_stall_vl_event_bits { 2188 u8 reserved_at_0[0x18]; 2189 u8 port_num[0x1]; 2190 u8 reserved_at_19[0x3]; 2191 u8 vl[0x4]; 2192 2193 u8 reserved_at_20[0xa0]; 2194 }; 2195 2196 struct mlx5_ifc_db_bf_congestion_event_bits { 2197 u8 event_subtype[0x8]; 2198 u8 reserved_at_8[0x8]; 2199 u8 congestion_level[0x8]; 2200 u8 reserved_at_18[0x8]; 2201 2202 u8 reserved_at_20[0xa0]; 2203 }; 2204 2205 struct mlx5_ifc_gpio_event_bits { 2206 u8 reserved_at_0[0x60]; 2207 2208 u8 gpio_event_hi[0x20]; 2209 2210 u8 gpio_event_lo[0x20]; 2211 2212 u8 reserved_at_a0[0x40]; 2213 }; 2214 2215 struct mlx5_ifc_port_state_change_event_bits { 2216 u8 reserved_at_0[0x40]; 2217 2218 u8 port_num[0x4]; 2219 u8 reserved_at_44[0x1c]; 2220 2221 u8 reserved_at_60[0x80]; 2222 }; 2223 2224 struct mlx5_ifc_dropped_packet_logged_bits { 2225 u8 reserved_at_0[0xe0]; 2226 }; 2227 2228 enum { 2229 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1, 2230 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2, 2231 }; 2232 2233 struct mlx5_ifc_cq_error_bits { 2234 u8 reserved_at_0[0x8]; 2235 u8 cqn[0x18]; 2236 2237 u8 reserved_at_20[0x20]; 2238 2239 u8 reserved_at_40[0x18]; 2240 u8 syndrome[0x8]; 2241 2242 u8 reserved_at_60[0x80]; 2243 }; 2244 2245 struct mlx5_ifc_rdma_page_fault_event_bits { 2246 u8 bytes_committed[0x20]; 2247 2248 u8 r_key[0x20]; 2249 2250 u8 reserved_at_40[0x10]; 2251 u8 packet_len[0x10]; 2252 2253 u8 rdma_op_len[0x20]; 2254 2255 u8 rdma_va[0x40]; 2256 2257 u8 reserved_at_c0[0x5]; 2258 u8 rdma[0x1]; 2259 u8 write[0x1]; 2260 u8 requestor[0x1]; 2261 u8 qp_number[0x18]; 2262 }; 2263 2264 struct mlx5_ifc_wqe_associated_page_fault_event_bits { 2265 u8 bytes_committed[0x20]; 2266 2267 u8 reserved_at_20[0x10]; 2268 u8 wqe_index[0x10]; 2269 2270 u8 reserved_at_40[0x10]; 2271 u8 len[0x10]; 2272 2273 u8 reserved_at_60[0x60]; 2274 2275 u8 reserved_at_c0[0x5]; 2276 u8 rdma[0x1]; 2277 u8 write_read[0x1]; 2278 u8 requestor[0x1]; 2279 u8 qpn[0x18]; 2280 }; 2281 2282 struct mlx5_ifc_qp_events_bits { 2283 u8 reserved_at_0[0xa0]; 2284 2285 u8 type[0x8]; 2286 u8 reserved_at_a8[0x18]; 2287 2288 u8 reserved_at_c0[0x8]; 2289 u8 qpn_rqn_sqn[0x18]; 2290 }; 2291 2292 struct mlx5_ifc_dct_events_bits { 2293 u8 reserved_at_0[0xc0]; 2294 2295 u8 reserved_at_c0[0x8]; 2296 u8 dct_number[0x18]; 2297 }; 2298 2299 struct mlx5_ifc_comp_event_bits { 2300 u8 reserved_at_0[0xc0]; 2301 2302 u8 reserved_at_c0[0x8]; 2303 u8 cq_number[0x18]; 2304 }; 2305 2306 enum { 2307 MLX5_QPC_STATE_RST = 0x0, 2308 MLX5_QPC_STATE_INIT = 0x1, 2309 MLX5_QPC_STATE_RTR = 0x2, 2310 MLX5_QPC_STATE_RTS = 0x3, 2311 MLX5_QPC_STATE_SQER = 0x4, 2312 MLX5_QPC_STATE_ERR = 0x6, 2313 MLX5_QPC_STATE_SQD = 0x7, 2314 MLX5_QPC_STATE_SUSPENDED = 0x9, 2315 }; 2316 2317 enum { 2318 MLX5_QPC_ST_RC = 0x0, 2319 MLX5_QPC_ST_UC = 0x1, 2320 MLX5_QPC_ST_UD = 0x2, 2321 MLX5_QPC_ST_XRC = 0x3, 2322 MLX5_QPC_ST_DCI = 0x5, 2323 MLX5_QPC_ST_QP0 = 0x7, 2324 MLX5_QPC_ST_QP1 = 0x8, 2325 MLX5_QPC_ST_RAW_DATAGRAM = 0x9, 2326 MLX5_QPC_ST_REG_UMR = 0xc, 2327 }; 2328 2329 enum { 2330 MLX5_QPC_PM_STATE_ARMED = 0x0, 2331 MLX5_QPC_PM_STATE_REARM = 0x1, 2332 MLX5_QPC_PM_STATE_RESERVED = 0x2, 2333 MLX5_QPC_PM_STATE_MIGRATED = 0x3, 2334 }; 2335 2336 enum { 2337 MLX5_QPC_OFFLOAD_TYPE_RNDV = 0x1, 2338 }; 2339 2340 enum { 2341 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0, 2342 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1, 2343 }; 2344 2345 enum { 2346 MLX5_QPC_MTU_256_BYTES = 0x1, 2347 MLX5_QPC_MTU_512_BYTES = 0x2, 2348 MLX5_QPC_MTU_1K_BYTES = 0x3, 2349 MLX5_QPC_MTU_2K_BYTES = 0x4, 2350 MLX5_QPC_MTU_4K_BYTES = 0x5, 2351 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7, 2352 }; 2353 2354 enum { 2355 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1, 2356 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2, 2357 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3, 2358 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4, 2359 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5, 2360 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6, 2361 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7, 2362 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8, 2363 }; 2364 2365 enum { 2366 MLX5_QPC_CS_REQ_DISABLE = 0x0, 2367 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11, 2368 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22, 2369 }; 2370 2371 enum { 2372 MLX5_QPC_CS_RES_DISABLE = 0x0, 2373 MLX5_QPC_CS_RES_UP_TO_32B = 0x1, 2374 MLX5_QPC_CS_RES_UP_TO_64B = 0x2, 2375 }; 2376 2377 struct mlx5_ifc_qpc_bits { 2378 u8 state[0x4]; 2379 u8 lag_tx_port_affinity[0x4]; 2380 u8 st[0x8]; 2381 u8 reserved_at_10[0x3]; 2382 u8 pm_state[0x2]; 2383 u8 reserved_at_15[0x1]; 2384 u8 req_e2e_credit_mode[0x2]; 2385 u8 offload_type[0x4]; 2386 u8 end_padding_mode[0x2]; 2387 u8 reserved_at_1e[0x2]; 2388 2389 u8 wq_signature[0x1]; 2390 u8 block_lb_mc[0x1]; 2391 u8 atomic_like_write_en[0x1]; 2392 u8 latency_sensitive[0x1]; 2393 u8 reserved_at_24[0x1]; 2394 u8 drain_sigerr[0x1]; 2395 u8 reserved_at_26[0x2]; 2396 u8 pd[0x18]; 2397 2398 u8 mtu[0x3]; 2399 u8 log_msg_max[0x5]; 2400 u8 reserved_at_48[0x1]; 2401 u8 log_rq_size[0x4]; 2402 u8 log_rq_stride[0x3]; 2403 u8 no_sq[0x1]; 2404 u8 log_sq_size[0x4]; 2405 u8 reserved_at_55[0x6]; 2406 u8 rlky[0x1]; 2407 u8 ulp_stateless_offload_mode[0x4]; 2408 2409 u8 counter_set_id[0x8]; 2410 u8 uar_page[0x18]; 2411 2412 u8 reserved_at_80[0x8]; 2413 u8 user_index[0x18]; 2414 2415 u8 reserved_at_a0[0x3]; 2416 u8 log_page_size[0x5]; 2417 u8 remote_qpn[0x18]; 2418 2419 struct mlx5_ifc_ads_bits primary_address_path; 2420 2421 struct mlx5_ifc_ads_bits secondary_address_path; 2422 2423 u8 log_ack_req_freq[0x4]; 2424 u8 reserved_at_384[0x4]; 2425 u8 log_sra_max[0x3]; 2426 u8 reserved_at_38b[0x2]; 2427 u8 retry_count[0x3]; 2428 u8 rnr_retry[0x3]; 2429 u8 reserved_at_393[0x1]; 2430 u8 fre[0x1]; 2431 u8 cur_rnr_retry[0x3]; 2432 u8 cur_retry_count[0x3]; 2433 u8 reserved_at_39b[0x5]; 2434 2435 u8 reserved_at_3a0[0x20]; 2436 2437 u8 reserved_at_3c0[0x8]; 2438 u8 next_send_psn[0x18]; 2439 2440 u8 reserved_at_3e0[0x8]; 2441 u8 cqn_snd[0x18]; 2442 2443 u8 reserved_at_400[0x8]; 2444 u8 deth_sqpn[0x18]; 2445 2446 u8 reserved_at_420[0x20]; 2447 2448 u8 reserved_at_440[0x8]; 2449 u8 last_acked_psn[0x18]; 2450 2451 u8 reserved_at_460[0x8]; 2452 u8 ssn[0x18]; 2453 2454 u8 reserved_at_480[0x8]; 2455 u8 log_rra_max[0x3]; 2456 u8 reserved_at_48b[0x1]; 2457 u8 atomic_mode[0x4]; 2458 u8 rre[0x1]; 2459 u8 rwe[0x1]; 2460 u8 rae[0x1]; 2461 u8 reserved_at_493[0x1]; 2462 u8 page_offset[0x6]; 2463 u8 reserved_at_49a[0x3]; 2464 u8 cd_slave_receive[0x1]; 2465 u8 cd_slave_send[0x1]; 2466 u8 cd_master[0x1]; 2467 2468 u8 reserved_at_4a0[0x3]; 2469 u8 min_rnr_nak[0x5]; 2470 u8 next_rcv_psn[0x18]; 2471 2472 u8 reserved_at_4c0[0x8]; 2473 u8 xrcd[0x18]; 2474 2475 u8 reserved_at_4e0[0x8]; 2476 u8 cqn_rcv[0x18]; 2477 2478 u8 dbr_addr[0x40]; 2479 2480 u8 q_key[0x20]; 2481 2482 u8 reserved_at_560[0x5]; 2483 u8 rq_type[0x3]; 2484 u8 srqn_rmpn_xrqn[0x18]; 2485 2486 u8 reserved_at_580[0x8]; 2487 u8 rmsn[0x18]; 2488 2489 u8 hw_sq_wqebb_counter[0x10]; 2490 u8 sw_sq_wqebb_counter[0x10]; 2491 2492 u8 hw_rq_counter[0x20]; 2493 2494 u8 sw_rq_counter[0x20]; 2495 2496 u8 reserved_at_600[0x20]; 2497 2498 u8 reserved_at_620[0xf]; 2499 u8 cgs[0x1]; 2500 u8 cs_req[0x8]; 2501 u8 cs_res[0x8]; 2502 2503 u8 dc_access_key[0x40]; 2504 2505 u8 reserved_at_680[0x3]; 2506 u8 dbr_umem_valid[0x1]; 2507 2508 u8 reserved_at_684[0xbc]; 2509 }; 2510 2511 struct mlx5_ifc_roce_addr_layout_bits { 2512 u8 source_l3_address[16][0x8]; 2513 2514 u8 reserved_at_80[0x3]; 2515 u8 vlan_valid[0x1]; 2516 u8 vlan_id[0xc]; 2517 u8 source_mac_47_32[0x10]; 2518 2519 u8 source_mac_31_0[0x20]; 2520 2521 u8 reserved_at_c0[0x14]; 2522 u8 roce_l3_type[0x4]; 2523 u8 roce_version[0x8]; 2524 2525 u8 reserved_at_e0[0x20]; 2526 }; 2527 2528 union mlx5_ifc_hca_cap_union_bits { 2529 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap; 2530 struct mlx5_ifc_odp_cap_bits odp_cap; 2531 struct mlx5_ifc_atomic_caps_bits atomic_caps; 2532 struct mlx5_ifc_roce_cap_bits roce_cap; 2533 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps; 2534 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap; 2535 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap; 2536 struct mlx5_ifc_e_switch_cap_bits e_switch_cap; 2537 struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap; 2538 struct mlx5_ifc_qos_cap_bits qos_cap; 2539 struct mlx5_ifc_debug_cap_bits debug_cap; 2540 struct mlx5_ifc_fpga_cap_bits fpga_cap; 2541 u8 reserved_at_0[0x8000]; 2542 }; 2543 2544 enum { 2545 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1, 2546 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2, 2547 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4, 2548 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8, 2549 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT = 0x10, 2550 MLX5_FLOW_CONTEXT_ACTION_DECAP = 0x20, 2551 MLX5_FLOW_CONTEXT_ACTION_MOD_HDR = 0x40, 2552 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP = 0x80, 2553 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100, 2554 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2 = 0x400, 2555 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2 = 0x800, 2556 }; 2557 2558 struct mlx5_ifc_vlan_bits { 2559 u8 ethtype[0x10]; 2560 u8 prio[0x3]; 2561 u8 cfi[0x1]; 2562 u8 vid[0xc]; 2563 }; 2564 2565 struct mlx5_ifc_flow_context_bits { 2566 struct mlx5_ifc_vlan_bits push_vlan; 2567 2568 u8 group_id[0x20]; 2569 2570 u8 reserved_at_40[0x8]; 2571 u8 flow_tag[0x18]; 2572 2573 u8 reserved_at_60[0x10]; 2574 u8 action[0x10]; 2575 2576 u8 extended_destination[0x1]; 2577 u8 reserved_at_80[0x7]; 2578 u8 destination_list_size[0x18]; 2579 2580 u8 reserved_at_a0[0x8]; 2581 u8 flow_counter_list_size[0x18]; 2582 2583 u8 packet_reformat_id[0x20]; 2584 2585 u8 modify_header_id[0x20]; 2586 2587 struct mlx5_ifc_vlan_bits push_vlan_2; 2588 2589 u8 reserved_at_120[0xe0]; 2590 2591 struct mlx5_ifc_fte_match_param_bits match_value; 2592 2593 u8 reserved_at_1200[0x600]; 2594 2595 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[0]; 2596 }; 2597 2598 enum { 2599 MLX5_XRC_SRQC_STATE_GOOD = 0x0, 2600 MLX5_XRC_SRQC_STATE_ERROR = 0x1, 2601 }; 2602 2603 struct mlx5_ifc_xrc_srqc_bits { 2604 u8 state[0x4]; 2605 u8 log_xrc_srq_size[0x4]; 2606 u8 reserved_at_8[0x18]; 2607 2608 u8 wq_signature[0x1]; 2609 u8 cont_srq[0x1]; 2610 u8 reserved_at_22[0x1]; 2611 u8 rlky[0x1]; 2612 u8 basic_cyclic_rcv_wqe[0x1]; 2613 u8 log_rq_stride[0x3]; 2614 u8 xrcd[0x18]; 2615 2616 u8 page_offset[0x6]; 2617 u8 reserved_at_46[0x1]; 2618 u8 dbr_umem_valid[0x1]; 2619 u8 cqn[0x18]; 2620 2621 u8 reserved_at_60[0x20]; 2622 2623 u8 user_index_equal_xrc_srqn[0x1]; 2624 u8 reserved_at_81[0x1]; 2625 u8 log_page_size[0x6]; 2626 u8 user_index[0x18]; 2627 2628 u8 reserved_at_a0[0x20]; 2629 2630 u8 reserved_at_c0[0x8]; 2631 u8 pd[0x18]; 2632 2633 u8 lwm[0x10]; 2634 u8 wqe_cnt[0x10]; 2635 2636 u8 reserved_at_100[0x40]; 2637 2638 u8 db_record_addr_h[0x20]; 2639 2640 u8 db_record_addr_l[0x1e]; 2641 u8 reserved_at_17e[0x2]; 2642 2643 u8 reserved_at_180[0x80]; 2644 }; 2645 2646 struct mlx5_ifc_vnic_diagnostic_statistics_bits { 2647 u8 counter_error_queues[0x20]; 2648 2649 u8 total_error_queues[0x20]; 2650 2651 u8 send_queue_priority_update_flow[0x20]; 2652 2653 u8 reserved_at_60[0x20]; 2654 2655 u8 nic_receive_steering_discard[0x40]; 2656 2657 u8 receive_discard_vport_down[0x40]; 2658 2659 u8 transmit_discard_vport_down[0x40]; 2660 2661 u8 reserved_at_140[0xec0]; 2662 }; 2663 2664 struct mlx5_ifc_traffic_counter_bits { 2665 u8 packets[0x40]; 2666 2667 u8 octets[0x40]; 2668 }; 2669 2670 struct mlx5_ifc_tisc_bits { 2671 u8 strict_lag_tx_port_affinity[0x1]; 2672 u8 reserved_at_1[0x3]; 2673 u8 lag_tx_port_affinity[0x04]; 2674 2675 u8 reserved_at_8[0x4]; 2676 u8 prio[0x4]; 2677 u8 reserved_at_10[0x10]; 2678 2679 u8 reserved_at_20[0x100]; 2680 2681 u8 reserved_at_120[0x8]; 2682 u8 transport_domain[0x18]; 2683 2684 u8 reserved_at_140[0x8]; 2685 u8 underlay_qpn[0x18]; 2686 u8 reserved_at_160[0x3a0]; 2687 }; 2688 2689 enum { 2690 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0, 2691 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1, 2692 }; 2693 2694 enum { 2695 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO = 0x1, 2696 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO = 0x2, 2697 }; 2698 2699 enum { 2700 MLX5_RX_HASH_FN_NONE = 0x0, 2701 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1, 2702 MLX5_RX_HASH_FN_TOEPLITZ = 0x2, 2703 }; 2704 2705 enum { 2706 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST = 0x1, 2707 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST = 0x2, 2708 }; 2709 2710 struct mlx5_ifc_tirc_bits { 2711 u8 reserved_at_0[0x20]; 2712 2713 u8 disp_type[0x4]; 2714 u8 reserved_at_24[0x1c]; 2715 2716 u8 reserved_at_40[0x40]; 2717 2718 u8 reserved_at_80[0x4]; 2719 u8 lro_timeout_period_usecs[0x10]; 2720 u8 lro_enable_mask[0x4]; 2721 u8 lro_max_ip_payload_size[0x8]; 2722 2723 u8 reserved_at_a0[0x40]; 2724 2725 u8 reserved_at_e0[0x8]; 2726 u8 inline_rqn[0x18]; 2727 2728 u8 rx_hash_symmetric[0x1]; 2729 u8 reserved_at_101[0x1]; 2730 u8 tunneled_offload_en[0x1]; 2731 u8 reserved_at_103[0x5]; 2732 u8 indirect_table[0x18]; 2733 2734 u8 rx_hash_fn[0x4]; 2735 u8 reserved_at_124[0x2]; 2736 u8 self_lb_block[0x2]; 2737 u8 transport_domain[0x18]; 2738 2739 u8 rx_hash_toeplitz_key[10][0x20]; 2740 2741 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer; 2742 2743 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner; 2744 2745 u8 reserved_at_2c0[0x4c0]; 2746 }; 2747 2748 enum { 2749 MLX5_SRQC_STATE_GOOD = 0x0, 2750 MLX5_SRQC_STATE_ERROR = 0x1, 2751 }; 2752 2753 struct mlx5_ifc_srqc_bits { 2754 u8 state[0x4]; 2755 u8 log_srq_size[0x4]; 2756 u8 reserved_at_8[0x18]; 2757 2758 u8 wq_signature[0x1]; 2759 u8 cont_srq[0x1]; 2760 u8 reserved_at_22[0x1]; 2761 u8 rlky[0x1]; 2762 u8 reserved_at_24[0x1]; 2763 u8 log_rq_stride[0x3]; 2764 u8 xrcd[0x18]; 2765 2766 u8 page_offset[0x6]; 2767 u8 reserved_at_46[0x2]; 2768 u8 cqn[0x18]; 2769 2770 u8 reserved_at_60[0x20]; 2771 2772 u8 reserved_at_80[0x2]; 2773 u8 log_page_size[0x6]; 2774 u8 reserved_at_88[0x18]; 2775 2776 u8 reserved_at_a0[0x20]; 2777 2778 u8 reserved_at_c0[0x8]; 2779 u8 pd[0x18]; 2780 2781 u8 lwm[0x10]; 2782 u8 wqe_cnt[0x10]; 2783 2784 u8 reserved_at_100[0x40]; 2785 2786 u8 dbr_addr[0x40]; 2787 2788 u8 reserved_at_180[0x80]; 2789 }; 2790 2791 enum { 2792 MLX5_SQC_STATE_RST = 0x0, 2793 MLX5_SQC_STATE_RDY = 0x1, 2794 MLX5_SQC_STATE_ERR = 0x3, 2795 }; 2796 2797 struct mlx5_ifc_sqc_bits { 2798 u8 rlky[0x1]; 2799 u8 cd_master[0x1]; 2800 u8 fre[0x1]; 2801 u8 flush_in_error_en[0x1]; 2802 u8 allow_multi_pkt_send_wqe[0x1]; 2803 u8 min_wqe_inline_mode[0x3]; 2804 u8 state[0x4]; 2805 u8 reg_umr[0x1]; 2806 u8 allow_swp[0x1]; 2807 u8 hairpin[0x1]; 2808 u8 reserved_at_f[0x11]; 2809 2810 u8 reserved_at_20[0x8]; 2811 u8 user_index[0x18]; 2812 2813 u8 reserved_at_40[0x8]; 2814 u8 cqn[0x18]; 2815 2816 u8 reserved_at_60[0x8]; 2817 u8 hairpin_peer_rq[0x18]; 2818 2819 u8 reserved_at_80[0x10]; 2820 u8 hairpin_peer_vhca[0x10]; 2821 2822 u8 reserved_at_a0[0x50]; 2823 2824 u8 packet_pacing_rate_limit_index[0x10]; 2825 u8 tis_lst_sz[0x10]; 2826 u8 reserved_at_110[0x10]; 2827 2828 u8 reserved_at_120[0x40]; 2829 2830 u8 reserved_at_160[0x8]; 2831 u8 tis_num_0[0x18]; 2832 2833 struct mlx5_ifc_wq_bits wq; 2834 }; 2835 2836 enum { 2837 SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0, 2838 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1, 2839 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2, 2840 SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3, 2841 }; 2842 2843 struct mlx5_ifc_scheduling_context_bits { 2844 u8 element_type[0x8]; 2845 u8 reserved_at_8[0x18]; 2846 2847 u8 element_attributes[0x20]; 2848 2849 u8 parent_element_id[0x20]; 2850 2851 u8 reserved_at_60[0x40]; 2852 2853 u8 bw_share[0x20]; 2854 2855 u8 max_average_bw[0x20]; 2856 2857 u8 reserved_at_e0[0x120]; 2858 }; 2859 2860 struct mlx5_ifc_rqtc_bits { 2861 u8 reserved_at_0[0xa0]; 2862 2863 u8 reserved_at_a0[0x10]; 2864 u8 rqt_max_size[0x10]; 2865 2866 u8 reserved_at_c0[0x10]; 2867 u8 rqt_actual_size[0x10]; 2868 2869 u8 reserved_at_e0[0x6a0]; 2870 2871 struct mlx5_ifc_rq_num_bits rq_num[0]; 2872 }; 2873 2874 enum { 2875 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0, 2876 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1, 2877 }; 2878 2879 enum { 2880 MLX5_RQC_STATE_RST = 0x0, 2881 MLX5_RQC_STATE_RDY = 0x1, 2882 MLX5_RQC_STATE_ERR = 0x3, 2883 }; 2884 2885 struct mlx5_ifc_rqc_bits { 2886 u8 rlky[0x1]; 2887 u8 delay_drop_en[0x1]; 2888 u8 scatter_fcs[0x1]; 2889 u8 vsd[0x1]; 2890 u8 mem_rq_type[0x4]; 2891 u8 state[0x4]; 2892 u8 reserved_at_c[0x1]; 2893 u8 flush_in_error_en[0x1]; 2894 u8 hairpin[0x1]; 2895 u8 reserved_at_f[0x11]; 2896 2897 u8 reserved_at_20[0x8]; 2898 u8 user_index[0x18]; 2899 2900 u8 reserved_at_40[0x8]; 2901 u8 cqn[0x18]; 2902 2903 u8 counter_set_id[0x8]; 2904 u8 reserved_at_68[0x18]; 2905 2906 u8 reserved_at_80[0x8]; 2907 u8 rmpn[0x18]; 2908 2909 u8 reserved_at_a0[0x8]; 2910 u8 hairpin_peer_sq[0x18]; 2911 2912 u8 reserved_at_c0[0x10]; 2913 u8 hairpin_peer_vhca[0x10]; 2914 2915 u8 reserved_at_e0[0xa0]; 2916 2917 struct mlx5_ifc_wq_bits wq; 2918 }; 2919 2920 enum { 2921 MLX5_RMPC_STATE_RDY = 0x1, 2922 MLX5_RMPC_STATE_ERR = 0x3, 2923 }; 2924 2925 struct mlx5_ifc_rmpc_bits { 2926 u8 reserved_at_0[0x8]; 2927 u8 state[0x4]; 2928 u8 reserved_at_c[0x14]; 2929 2930 u8 basic_cyclic_rcv_wqe[0x1]; 2931 u8 reserved_at_21[0x1f]; 2932 2933 u8 reserved_at_40[0x140]; 2934 2935 struct mlx5_ifc_wq_bits wq; 2936 }; 2937 2938 struct mlx5_ifc_nic_vport_context_bits { 2939 u8 reserved_at_0[0x5]; 2940 u8 min_wqe_inline_mode[0x3]; 2941 u8 reserved_at_8[0x15]; 2942 u8 disable_mc_local_lb[0x1]; 2943 u8 disable_uc_local_lb[0x1]; 2944 u8 roce_en[0x1]; 2945 2946 u8 arm_change_event[0x1]; 2947 u8 reserved_at_21[0x1a]; 2948 u8 event_on_mtu[0x1]; 2949 u8 event_on_promisc_change[0x1]; 2950 u8 event_on_vlan_change[0x1]; 2951 u8 event_on_mc_address_change[0x1]; 2952 u8 event_on_uc_address_change[0x1]; 2953 2954 u8 reserved_at_40[0xc]; 2955 2956 u8 affiliation_criteria[0x4]; 2957 u8 affiliated_vhca_id[0x10]; 2958 2959 u8 reserved_at_60[0xd0]; 2960 2961 u8 mtu[0x10]; 2962 2963 u8 system_image_guid[0x40]; 2964 u8 port_guid[0x40]; 2965 u8 node_guid[0x40]; 2966 2967 u8 reserved_at_200[0x140]; 2968 u8 qkey_violation_counter[0x10]; 2969 u8 reserved_at_350[0x430]; 2970 2971 u8 promisc_uc[0x1]; 2972 u8 promisc_mc[0x1]; 2973 u8 promisc_all[0x1]; 2974 u8 reserved_at_783[0x2]; 2975 u8 allowed_list_type[0x3]; 2976 u8 reserved_at_788[0xc]; 2977 u8 allowed_list_size[0xc]; 2978 2979 struct mlx5_ifc_mac_address_layout_bits permanent_address; 2980 2981 u8 reserved_at_7e0[0x20]; 2982 2983 u8 current_uc_mac_address[0][0x40]; 2984 }; 2985 2986 enum { 2987 MLX5_MKC_ACCESS_MODE_PA = 0x0, 2988 MLX5_MKC_ACCESS_MODE_MTT = 0x1, 2989 MLX5_MKC_ACCESS_MODE_KLMS = 0x2, 2990 MLX5_MKC_ACCESS_MODE_KSM = 0x3, 2991 MLX5_MKC_ACCESS_MODE_SW_ICM = 0x4, 2992 MLX5_MKC_ACCESS_MODE_MEMIC = 0x5, 2993 }; 2994 2995 struct mlx5_ifc_mkc_bits { 2996 u8 reserved_at_0[0x1]; 2997 u8 free[0x1]; 2998 u8 reserved_at_2[0x1]; 2999 u8 access_mode_4_2[0x3]; 3000 u8 reserved_at_6[0x7]; 3001 u8 relaxed_ordering_write[0x1]; 3002 u8 reserved_at_e[0x1]; 3003 u8 small_fence_on_rdma_read_response[0x1]; 3004 u8 umr_en[0x1]; 3005 u8 a[0x1]; 3006 u8 rw[0x1]; 3007 u8 rr[0x1]; 3008 u8 lw[0x1]; 3009 u8 lr[0x1]; 3010 u8 access_mode_1_0[0x2]; 3011 u8 reserved_at_18[0x8]; 3012 3013 u8 qpn[0x18]; 3014 u8 mkey_7_0[0x8]; 3015 3016 u8 reserved_at_40[0x20]; 3017 3018 u8 length64[0x1]; 3019 u8 bsf_en[0x1]; 3020 u8 sync_umr[0x1]; 3021 u8 reserved_at_63[0x2]; 3022 u8 expected_sigerr_count[0x1]; 3023 u8 reserved_at_66[0x1]; 3024 u8 en_rinval[0x1]; 3025 u8 pd[0x18]; 3026 3027 u8 start_addr[0x40]; 3028 3029 u8 len[0x40]; 3030 3031 u8 bsf_octword_size[0x20]; 3032 3033 u8 reserved_at_120[0x80]; 3034 3035 u8 translations_octword_size[0x20]; 3036 3037 u8 reserved_at_1c0[0x1b]; 3038 u8 log_page_size[0x5]; 3039 3040 u8 reserved_at_1e0[0x20]; 3041 }; 3042 3043 struct mlx5_ifc_pkey_bits { 3044 u8 reserved_at_0[0x10]; 3045 u8 pkey[0x10]; 3046 }; 3047 3048 struct mlx5_ifc_array128_auto_bits { 3049 u8 array128_auto[16][0x8]; 3050 }; 3051 3052 struct mlx5_ifc_hca_vport_context_bits { 3053 u8 field_select[0x20]; 3054 3055 u8 reserved_at_20[0xe0]; 3056 3057 u8 sm_virt_aware[0x1]; 3058 u8 has_smi[0x1]; 3059 u8 has_raw[0x1]; 3060 u8 grh_required[0x1]; 3061 u8 reserved_at_104[0xc]; 3062 u8 port_physical_state[0x4]; 3063 u8 vport_state_policy[0x4]; 3064 u8 port_state[0x4]; 3065 u8 vport_state[0x4]; 3066 3067 u8 reserved_at_120[0x20]; 3068 3069 u8 system_image_guid[0x40]; 3070 3071 u8 port_guid[0x40]; 3072 3073 u8 node_guid[0x40]; 3074 3075 u8 cap_mask1[0x20]; 3076 3077 u8 cap_mask1_field_select[0x20]; 3078 3079 u8 cap_mask2[0x20]; 3080 3081 u8 cap_mask2_field_select[0x20]; 3082 3083 u8 reserved_at_280[0x80]; 3084 3085 u8 lid[0x10]; 3086 u8 reserved_at_310[0x4]; 3087 u8 init_type_reply[0x4]; 3088 u8 lmc[0x3]; 3089 u8 subnet_timeout[0x5]; 3090 3091 u8 sm_lid[0x10]; 3092 u8 sm_sl[0x4]; 3093 u8 reserved_at_334[0xc]; 3094 3095 u8 qkey_violation_counter[0x10]; 3096 u8 pkey_violation_counter[0x10]; 3097 3098 u8 reserved_at_360[0xca0]; 3099 }; 3100 3101 struct mlx5_ifc_esw_vport_context_bits { 3102 u8 reserved_at_0[0x3]; 3103 u8 vport_svlan_strip[0x1]; 3104 u8 vport_cvlan_strip[0x1]; 3105 u8 vport_svlan_insert[0x1]; 3106 u8 vport_cvlan_insert[0x2]; 3107 u8 reserved_at_8[0x18]; 3108 3109 u8 reserved_at_20[0x20]; 3110 3111 u8 svlan_cfi[0x1]; 3112 u8 svlan_pcp[0x3]; 3113 u8 svlan_id[0xc]; 3114 u8 cvlan_cfi[0x1]; 3115 u8 cvlan_pcp[0x3]; 3116 u8 cvlan_id[0xc]; 3117 3118 u8 reserved_at_60[0x7a0]; 3119 }; 3120 3121 enum { 3122 MLX5_EQC_STATUS_OK = 0x0, 3123 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa, 3124 }; 3125 3126 enum { 3127 MLX5_EQC_ST_ARMED = 0x9, 3128 MLX5_EQC_ST_FIRED = 0xa, 3129 }; 3130 3131 struct mlx5_ifc_eqc_bits { 3132 u8 status[0x4]; 3133 u8 reserved_at_4[0x9]; 3134 u8 ec[0x1]; 3135 u8 oi[0x1]; 3136 u8 reserved_at_f[0x5]; 3137 u8 st[0x4]; 3138 u8 reserved_at_18[0x8]; 3139 3140 u8 reserved_at_20[0x20]; 3141 3142 u8 reserved_at_40[0x14]; 3143 u8 page_offset[0x6]; 3144 u8 reserved_at_5a[0x6]; 3145 3146 u8 reserved_at_60[0x3]; 3147 u8 log_eq_size[0x5]; 3148 u8 uar_page[0x18]; 3149 3150 u8 reserved_at_80[0x20]; 3151 3152 u8 reserved_at_a0[0x18]; 3153 u8 intr[0x8]; 3154 3155 u8 reserved_at_c0[0x3]; 3156 u8 log_page_size[0x5]; 3157 u8 reserved_at_c8[0x18]; 3158 3159 u8 reserved_at_e0[0x60]; 3160 3161 u8 reserved_at_140[0x8]; 3162 u8 consumer_counter[0x18]; 3163 3164 u8 reserved_at_160[0x8]; 3165 u8 producer_counter[0x18]; 3166 3167 u8 reserved_at_180[0x80]; 3168 }; 3169 3170 enum { 3171 MLX5_DCTC_STATE_ACTIVE = 0x0, 3172 MLX5_DCTC_STATE_DRAINING = 0x1, 3173 MLX5_DCTC_STATE_DRAINED = 0x2, 3174 }; 3175 3176 enum { 3177 MLX5_DCTC_CS_RES_DISABLE = 0x0, 3178 MLX5_DCTC_CS_RES_NA = 0x1, 3179 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2, 3180 }; 3181 3182 enum { 3183 MLX5_DCTC_MTU_256_BYTES = 0x1, 3184 MLX5_DCTC_MTU_512_BYTES = 0x2, 3185 MLX5_DCTC_MTU_1K_BYTES = 0x3, 3186 MLX5_DCTC_MTU_2K_BYTES = 0x4, 3187 MLX5_DCTC_MTU_4K_BYTES = 0x5, 3188 }; 3189 3190 struct mlx5_ifc_dctc_bits { 3191 u8 reserved_at_0[0x4]; 3192 u8 state[0x4]; 3193 u8 reserved_at_8[0x18]; 3194 3195 u8 reserved_at_20[0x8]; 3196 u8 user_index[0x18]; 3197 3198 u8 reserved_at_40[0x8]; 3199 u8 cqn[0x18]; 3200 3201 u8 counter_set_id[0x8]; 3202 u8 atomic_mode[0x4]; 3203 u8 rre[0x1]; 3204 u8 rwe[0x1]; 3205 u8 rae[0x1]; 3206 u8 atomic_like_write_en[0x1]; 3207 u8 latency_sensitive[0x1]; 3208 u8 rlky[0x1]; 3209 u8 free_ar[0x1]; 3210 u8 reserved_at_73[0xd]; 3211 3212 u8 reserved_at_80[0x8]; 3213 u8 cs_res[0x8]; 3214 u8 reserved_at_90[0x3]; 3215 u8 min_rnr_nak[0x5]; 3216 u8 reserved_at_98[0x8]; 3217 3218 u8 reserved_at_a0[0x8]; 3219 u8 srqn_xrqn[0x18]; 3220 3221 u8 reserved_at_c0[0x8]; 3222 u8 pd[0x18]; 3223 3224 u8 tclass[0x8]; 3225 u8 reserved_at_e8[0x4]; 3226 u8 flow_label[0x14]; 3227 3228 u8 dc_access_key[0x40]; 3229 3230 u8 reserved_at_140[0x5]; 3231 u8 mtu[0x3]; 3232 u8 port[0x8]; 3233 u8 pkey_index[0x10]; 3234 3235 u8 reserved_at_160[0x8]; 3236 u8 my_addr_index[0x8]; 3237 u8 reserved_at_170[0x8]; 3238 u8 hop_limit[0x8]; 3239 3240 u8 dc_access_key_violation_count[0x20]; 3241 3242 u8 reserved_at_1a0[0x14]; 3243 u8 dei_cfi[0x1]; 3244 u8 eth_prio[0x3]; 3245 u8 ecn[0x2]; 3246 u8 dscp[0x6]; 3247 3248 u8 reserved_at_1c0[0x40]; 3249 }; 3250 3251 enum { 3252 MLX5_CQC_STATUS_OK = 0x0, 3253 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9, 3254 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa, 3255 }; 3256 3257 enum { 3258 MLX5_CQC_CQE_SZ_64_BYTES = 0x0, 3259 MLX5_CQC_CQE_SZ_128_BYTES = 0x1, 3260 }; 3261 3262 enum { 3263 MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED = 0x6, 3264 MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED = 0x9, 3265 MLX5_CQC_ST_FIRED = 0xa, 3266 }; 3267 3268 enum { 3269 MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0, 3270 MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1, 3271 MLX5_CQ_PERIOD_NUM_MODES 3272 }; 3273 3274 struct mlx5_ifc_cqc_bits { 3275 u8 status[0x4]; 3276 u8 reserved_at_4[0x2]; 3277 u8 dbr_umem_valid[0x1]; 3278 u8 reserved_at_7[0x1]; 3279 u8 cqe_sz[0x3]; 3280 u8 cc[0x1]; 3281 u8 reserved_at_c[0x1]; 3282 u8 scqe_break_moderation_en[0x1]; 3283 u8 oi[0x1]; 3284 u8 cq_period_mode[0x2]; 3285 u8 cqe_comp_en[0x1]; 3286 u8 mini_cqe_res_format[0x2]; 3287 u8 st[0x4]; 3288 u8 reserved_at_18[0x8]; 3289 3290 u8 reserved_at_20[0x20]; 3291 3292 u8 reserved_at_40[0x14]; 3293 u8 page_offset[0x6]; 3294 u8 reserved_at_5a[0x6]; 3295 3296 u8 reserved_at_60[0x3]; 3297 u8 log_cq_size[0x5]; 3298 u8 uar_page[0x18]; 3299 3300 u8 reserved_at_80[0x4]; 3301 u8 cq_period[0xc]; 3302 u8 cq_max_count[0x10]; 3303 3304 u8 reserved_at_a0[0x18]; 3305 u8 c_eqn[0x8]; 3306 3307 u8 reserved_at_c0[0x3]; 3308 u8 log_page_size[0x5]; 3309 u8 reserved_at_c8[0x18]; 3310 3311 u8 reserved_at_e0[0x20]; 3312 3313 u8 reserved_at_100[0x8]; 3314 u8 last_notified_index[0x18]; 3315 3316 u8 reserved_at_120[0x8]; 3317 u8 last_solicit_index[0x18]; 3318 3319 u8 reserved_at_140[0x8]; 3320 u8 consumer_counter[0x18]; 3321 3322 u8 reserved_at_160[0x8]; 3323 u8 producer_counter[0x18]; 3324 3325 u8 reserved_at_180[0x40]; 3326 3327 u8 dbr_addr[0x40]; 3328 }; 3329 3330 union mlx5_ifc_cong_control_roce_ecn_auto_bits { 3331 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp; 3332 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp; 3333 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np; 3334 u8 reserved_at_0[0x800]; 3335 }; 3336 3337 struct mlx5_ifc_query_adapter_param_block_bits { 3338 u8 reserved_at_0[0xc0]; 3339 3340 u8 reserved_at_c0[0x8]; 3341 u8 ieee_vendor_id[0x18]; 3342 3343 u8 reserved_at_e0[0x10]; 3344 u8 vsd_vendor_id[0x10]; 3345 3346 u8 vsd[208][0x8]; 3347 3348 u8 vsd_contd_psid[16][0x8]; 3349 }; 3350 3351 enum { 3352 MLX5_XRQC_STATE_GOOD = 0x0, 3353 MLX5_XRQC_STATE_ERROR = 0x1, 3354 }; 3355 3356 enum { 3357 MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0, 3358 MLX5_XRQC_TOPOLOGY_TAG_MATCHING = 0x1, 3359 }; 3360 3361 enum { 3362 MLX5_XRQC_OFFLOAD_RNDV = 0x1, 3363 }; 3364 3365 struct mlx5_ifc_tag_matching_topology_context_bits { 3366 u8 log_matching_list_sz[0x4]; 3367 u8 reserved_at_4[0xc]; 3368 u8 append_next_index[0x10]; 3369 3370 u8 sw_phase_cnt[0x10]; 3371 u8 hw_phase_cnt[0x10]; 3372 3373 u8 reserved_at_40[0x40]; 3374 }; 3375 3376 struct mlx5_ifc_xrqc_bits { 3377 u8 state[0x4]; 3378 u8 rlkey[0x1]; 3379 u8 reserved_at_5[0xf]; 3380 u8 topology[0x4]; 3381 u8 reserved_at_18[0x4]; 3382 u8 offload[0x4]; 3383 3384 u8 reserved_at_20[0x8]; 3385 u8 user_index[0x18]; 3386 3387 u8 reserved_at_40[0x8]; 3388 u8 cqn[0x18]; 3389 3390 u8 reserved_at_60[0xa0]; 3391 3392 struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context; 3393 3394 u8 reserved_at_180[0x280]; 3395 3396 struct mlx5_ifc_wq_bits wq; 3397 }; 3398 3399 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits { 3400 struct mlx5_ifc_modify_field_select_bits modify_field_select; 3401 struct mlx5_ifc_resize_field_select_bits resize_field_select; 3402 u8 reserved_at_0[0x20]; 3403 }; 3404 3405 union mlx5_ifc_field_select_802_1_r_roce_auto_bits { 3406 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp; 3407 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp; 3408 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np; 3409 u8 reserved_at_0[0x20]; 3410 }; 3411 3412 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits { 3413 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 3414 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 3415 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 3416 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 3417 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 3418 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 3419 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout; 3420 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 3421 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 3422 struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs; 3423 u8 reserved_at_0[0x7c0]; 3424 }; 3425 3426 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits { 3427 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout; 3428 u8 reserved_at_0[0x7c0]; 3429 }; 3430 3431 union mlx5_ifc_event_auto_bits { 3432 struct mlx5_ifc_comp_event_bits comp_event; 3433 struct mlx5_ifc_dct_events_bits dct_events; 3434 struct mlx5_ifc_qp_events_bits qp_events; 3435 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event; 3436 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event; 3437 struct mlx5_ifc_cq_error_bits cq_error; 3438 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged; 3439 struct mlx5_ifc_port_state_change_event_bits port_state_change_event; 3440 struct mlx5_ifc_gpio_event_bits gpio_event; 3441 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event; 3442 struct mlx5_ifc_stall_vl_event_bits stall_vl_event; 3443 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event; 3444 u8 reserved_at_0[0xe0]; 3445 }; 3446 3447 struct mlx5_ifc_health_buffer_bits { 3448 u8 reserved_at_0[0x100]; 3449 3450 u8 assert_existptr[0x20]; 3451 3452 u8 assert_callra[0x20]; 3453 3454 u8 reserved_at_140[0x40]; 3455 3456 u8 fw_version[0x20]; 3457 3458 u8 hw_id[0x20]; 3459 3460 u8 reserved_at_1c0[0x20]; 3461 3462 u8 irisc_index[0x8]; 3463 u8 synd[0x8]; 3464 u8 ext_synd[0x10]; 3465 }; 3466 3467 struct mlx5_ifc_register_loopback_control_bits { 3468 u8 no_lb[0x1]; 3469 u8 reserved_at_1[0x7]; 3470 u8 port[0x8]; 3471 u8 reserved_at_10[0x10]; 3472 3473 u8 reserved_at_20[0x60]; 3474 }; 3475 3476 struct mlx5_ifc_vport_tc_element_bits { 3477 u8 traffic_class[0x4]; 3478 u8 reserved_at_4[0xc]; 3479 u8 vport_number[0x10]; 3480 }; 3481 3482 struct mlx5_ifc_vport_element_bits { 3483 u8 reserved_at_0[0x10]; 3484 u8 vport_number[0x10]; 3485 }; 3486 3487 enum { 3488 TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0, 3489 TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1, 3490 TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2, 3491 }; 3492 3493 struct mlx5_ifc_tsar_element_bits { 3494 u8 reserved_at_0[0x8]; 3495 u8 tsar_type[0x8]; 3496 u8 reserved_at_10[0x10]; 3497 }; 3498 3499 enum { 3500 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0, 3501 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1, 3502 }; 3503 3504 struct mlx5_ifc_teardown_hca_out_bits { 3505 u8 status[0x8]; 3506 u8 reserved_at_8[0x18]; 3507 3508 u8 syndrome[0x20]; 3509 3510 u8 reserved_at_40[0x3f]; 3511 3512 u8 state[0x1]; 3513 }; 3514 3515 enum { 3516 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0, 3517 MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE = 0x1, 3518 MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN = 0x2, 3519 }; 3520 3521 struct mlx5_ifc_teardown_hca_in_bits { 3522 u8 opcode[0x10]; 3523 u8 reserved_at_10[0x10]; 3524 3525 u8 reserved_at_20[0x10]; 3526 u8 op_mod[0x10]; 3527 3528 u8 reserved_at_40[0x10]; 3529 u8 profile[0x10]; 3530 3531 u8 reserved_at_60[0x20]; 3532 }; 3533 3534 struct mlx5_ifc_sqerr2rts_qp_out_bits { 3535 u8 status[0x8]; 3536 u8 reserved_at_8[0x18]; 3537 3538 u8 syndrome[0x20]; 3539 3540 u8 reserved_at_40[0x40]; 3541 }; 3542 3543 struct mlx5_ifc_sqerr2rts_qp_in_bits { 3544 u8 opcode[0x10]; 3545 u8 uid[0x10]; 3546 3547 u8 reserved_at_20[0x10]; 3548 u8 op_mod[0x10]; 3549 3550 u8 reserved_at_40[0x8]; 3551 u8 qpn[0x18]; 3552 3553 u8 reserved_at_60[0x20]; 3554 3555 u8 opt_param_mask[0x20]; 3556 3557 u8 reserved_at_a0[0x20]; 3558 3559 struct mlx5_ifc_qpc_bits qpc; 3560 3561 u8 reserved_at_800[0x80]; 3562 }; 3563 3564 struct mlx5_ifc_sqd2rts_qp_out_bits { 3565 u8 status[0x8]; 3566 u8 reserved_at_8[0x18]; 3567 3568 u8 syndrome[0x20]; 3569 3570 u8 reserved_at_40[0x40]; 3571 }; 3572 3573 struct mlx5_ifc_sqd2rts_qp_in_bits { 3574 u8 opcode[0x10]; 3575 u8 uid[0x10]; 3576 3577 u8 reserved_at_20[0x10]; 3578 u8 op_mod[0x10]; 3579 3580 u8 reserved_at_40[0x8]; 3581 u8 qpn[0x18]; 3582 3583 u8 reserved_at_60[0x20]; 3584 3585 u8 opt_param_mask[0x20]; 3586 3587 u8 reserved_at_a0[0x20]; 3588 3589 struct mlx5_ifc_qpc_bits qpc; 3590 3591 u8 reserved_at_800[0x80]; 3592 }; 3593 3594 struct mlx5_ifc_set_roce_address_out_bits { 3595 u8 status[0x8]; 3596 u8 reserved_at_8[0x18]; 3597 3598 u8 syndrome[0x20]; 3599 3600 u8 reserved_at_40[0x40]; 3601 }; 3602 3603 struct mlx5_ifc_set_roce_address_in_bits { 3604 u8 opcode[0x10]; 3605 u8 reserved_at_10[0x10]; 3606 3607 u8 reserved_at_20[0x10]; 3608 u8 op_mod[0x10]; 3609 3610 u8 roce_address_index[0x10]; 3611 u8 reserved_at_50[0xc]; 3612 u8 vhca_port_num[0x4]; 3613 3614 u8 reserved_at_60[0x20]; 3615 3616 struct mlx5_ifc_roce_addr_layout_bits roce_address; 3617 }; 3618 3619 struct mlx5_ifc_set_mad_demux_out_bits { 3620 u8 status[0x8]; 3621 u8 reserved_at_8[0x18]; 3622 3623 u8 syndrome[0x20]; 3624 3625 u8 reserved_at_40[0x40]; 3626 }; 3627 3628 enum { 3629 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0, 3630 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2, 3631 }; 3632 3633 struct mlx5_ifc_set_mad_demux_in_bits { 3634 u8 opcode[0x10]; 3635 u8 reserved_at_10[0x10]; 3636 3637 u8 reserved_at_20[0x10]; 3638 u8 op_mod[0x10]; 3639 3640 u8 reserved_at_40[0x20]; 3641 3642 u8 reserved_at_60[0x6]; 3643 u8 demux_mode[0x2]; 3644 u8 reserved_at_68[0x18]; 3645 }; 3646 3647 struct mlx5_ifc_set_l2_table_entry_out_bits { 3648 u8 status[0x8]; 3649 u8 reserved_at_8[0x18]; 3650 3651 u8 syndrome[0x20]; 3652 3653 u8 reserved_at_40[0x40]; 3654 }; 3655 3656 struct mlx5_ifc_set_l2_table_entry_in_bits { 3657 u8 opcode[0x10]; 3658 u8 reserved_at_10[0x10]; 3659 3660 u8 reserved_at_20[0x10]; 3661 u8 op_mod[0x10]; 3662 3663 u8 reserved_at_40[0x60]; 3664 3665 u8 reserved_at_a0[0x8]; 3666 u8 table_index[0x18]; 3667 3668 u8 reserved_at_c0[0x20]; 3669 3670 u8 reserved_at_e0[0x13]; 3671 u8 vlan_valid[0x1]; 3672 u8 vlan[0xc]; 3673 3674 struct mlx5_ifc_mac_address_layout_bits mac_address; 3675 3676 u8 reserved_at_140[0xc0]; 3677 }; 3678 3679 struct mlx5_ifc_set_issi_out_bits { 3680 u8 status[0x8]; 3681 u8 reserved_at_8[0x18]; 3682 3683 u8 syndrome[0x20]; 3684 3685 u8 reserved_at_40[0x40]; 3686 }; 3687 3688 struct mlx5_ifc_set_issi_in_bits { 3689 u8 opcode[0x10]; 3690 u8 reserved_at_10[0x10]; 3691 3692 u8 reserved_at_20[0x10]; 3693 u8 op_mod[0x10]; 3694 3695 u8 reserved_at_40[0x10]; 3696 u8 current_issi[0x10]; 3697 3698 u8 reserved_at_60[0x20]; 3699 }; 3700 3701 struct mlx5_ifc_set_hca_cap_out_bits { 3702 u8 status[0x8]; 3703 u8 reserved_at_8[0x18]; 3704 3705 u8 syndrome[0x20]; 3706 3707 u8 reserved_at_40[0x40]; 3708 }; 3709 3710 struct mlx5_ifc_set_hca_cap_in_bits { 3711 u8 opcode[0x10]; 3712 u8 reserved_at_10[0x10]; 3713 3714 u8 reserved_at_20[0x10]; 3715 u8 op_mod[0x10]; 3716 3717 u8 reserved_at_40[0x40]; 3718 3719 union mlx5_ifc_hca_cap_union_bits capability; 3720 }; 3721 3722 enum { 3723 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0, 3724 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1, 3725 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2, 3726 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3 3727 }; 3728 3729 struct mlx5_ifc_set_fte_out_bits { 3730 u8 status[0x8]; 3731 u8 reserved_at_8[0x18]; 3732 3733 u8 syndrome[0x20]; 3734 3735 u8 reserved_at_40[0x40]; 3736 }; 3737 3738 struct mlx5_ifc_set_fte_in_bits { 3739 u8 opcode[0x10]; 3740 u8 reserved_at_10[0x10]; 3741 3742 u8 reserved_at_20[0x10]; 3743 u8 op_mod[0x10]; 3744 3745 u8 other_vport[0x1]; 3746 u8 reserved_at_41[0xf]; 3747 u8 vport_number[0x10]; 3748 3749 u8 reserved_at_60[0x20]; 3750 3751 u8 table_type[0x8]; 3752 u8 reserved_at_88[0x18]; 3753 3754 u8 reserved_at_a0[0x8]; 3755 u8 table_id[0x18]; 3756 3757 u8 reserved_at_c0[0x18]; 3758 u8 modify_enable_mask[0x8]; 3759 3760 u8 reserved_at_e0[0x20]; 3761 3762 u8 flow_index[0x20]; 3763 3764 u8 reserved_at_120[0xe0]; 3765 3766 struct mlx5_ifc_flow_context_bits flow_context; 3767 }; 3768 3769 struct mlx5_ifc_rts2rts_qp_out_bits { 3770 u8 status[0x8]; 3771 u8 reserved_at_8[0x18]; 3772 3773 u8 syndrome[0x20]; 3774 3775 u8 reserved_at_40[0x40]; 3776 }; 3777 3778 struct mlx5_ifc_rts2rts_qp_in_bits { 3779 u8 opcode[0x10]; 3780 u8 uid[0x10]; 3781 3782 u8 reserved_at_20[0x10]; 3783 u8 op_mod[0x10]; 3784 3785 u8 reserved_at_40[0x8]; 3786 u8 qpn[0x18]; 3787 3788 u8 reserved_at_60[0x20]; 3789 3790 u8 opt_param_mask[0x20]; 3791 3792 u8 reserved_at_a0[0x20]; 3793 3794 struct mlx5_ifc_qpc_bits qpc; 3795 3796 u8 reserved_at_800[0x80]; 3797 }; 3798 3799 struct mlx5_ifc_rtr2rts_qp_out_bits { 3800 u8 status[0x8]; 3801 u8 reserved_at_8[0x18]; 3802 3803 u8 syndrome[0x20]; 3804 3805 u8 reserved_at_40[0x40]; 3806 }; 3807 3808 struct mlx5_ifc_rtr2rts_qp_in_bits { 3809 u8 opcode[0x10]; 3810 u8 uid[0x10]; 3811 3812 u8 reserved_at_20[0x10]; 3813 u8 op_mod[0x10]; 3814 3815 u8 reserved_at_40[0x8]; 3816 u8 qpn[0x18]; 3817 3818 u8 reserved_at_60[0x20]; 3819 3820 u8 opt_param_mask[0x20]; 3821 3822 u8 reserved_at_a0[0x20]; 3823 3824 struct mlx5_ifc_qpc_bits qpc; 3825 3826 u8 reserved_at_800[0x80]; 3827 }; 3828 3829 struct mlx5_ifc_rst2init_qp_out_bits { 3830 u8 status[0x8]; 3831 u8 reserved_at_8[0x18]; 3832 3833 u8 syndrome[0x20]; 3834 3835 u8 reserved_at_40[0x40]; 3836 }; 3837 3838 struct mlx5_ifc_rst2init_qp_in_bits { 3839 u8 opcode[0x10]; 3840 u8 uid[0x10]; 3841 3842 u8 reserved_at_20[0x10]; 3843 u8 op_mod[0x10]; 3844 3845 u8 reserved_at_40[0x8]; 3846 u8 qpn[0x18]; 3847 3848 u8 reserved_at_60[0x20]; 3849 3850 u8 opt_param_mask[0x20]; 3851 3852 u8 reserved_at_a0[0x20]; 3853 3854 struct mlx5_ifc_qpc_bits qpc; 3855 3856 u8 reserved_at_800[0x80]; 3857 }; 3858 3859 struct mlx5_ifc_query_xrq_out_bits { 3860 u8 status[0x8]; 3861 u8 reserved_at_8[0x18]; 3862 3863 u8 syndrome[0x20]; 3864 3865 u8 reserved_at_40[0x40]; 3866 3867 struct mlx5_ifc_xrqc_bits xrq_context; 3868 }; 3869 3870 struct mlx5_ifc_query_xrq_in_bits { 3871 u8 opcode[0x10]; 3872 u8 reserved_at_10[0x10]; 3873 3874 u8 reserved_at_20[0x10]; 3875 u8 op_mod[0x10]; 3876 3877 u8 reserved_at_40[0x8]; 3878 u8 xrqn[0x18]; 3879 3880 u8 reserved_at_60[0x20]; 3881 }; 3882 3883 struct mlx5_ifc_query_xrc_srq_out_bits { 3884 u8 status[0x8]; 3885 u8 reserved_at_8[0x18]; 3886 3887 u8 syndrome[0x20]; 3888 3889 u8 reserved_at_40[0x40]; 3890 3891 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 3892 3893 u8 reserved_at_280[0x600]; 3894 3895 u8 pas[0][0x40]; 3896 }; 3897 3898 struct mlx5_ifc_query_xrc_srq_in_bits { 3899 u8 opcode[0x10]; 3900 u8 reserved_at_10[0x10]; 3901 3902 u8 reserved_at_20[0x10]; 3903 u8 op_mod[0x10]; 3904 3905 u8 reserved_at_40[0x8]; 3906 u8 xrc_srqn[0x18]; 3907 3908 u8 reserved_at_60[0x20]; 3909 }; 3910 3911 enum { 3912 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0, 3913 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1, 3914 }; 3915 3916 struct mlx5_ifc_query_vport_state_out_bits { 3917 u8 status[0x8]; 3918 u8 reserved_at_8[0x18]; 3919 3920 u8 syndrome[0x20]; 3921 3922 u8 reserved_at_40[0x20]; 3923 3924 u8 reserved_at_60[0x18]; 3925 u8 admin_state[0x4]; 3926 u8 state[0x4]; 3927 }; 3928 3929 enum { 3930 MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT = 0x0, 3931 MLX5_VPORT_STATE_OP_MOD_ESW_VPORT = 0x1, 3932 }; 3933 3934 struct mlx5_ifc_arm_monitor_counter_in_bits { 3935 u8 opcode[0x10]; 3936 u8 uid[0x10]; 3937 3938 u8 reserved_at_20[0x10]; 3939 u8 op_mod[0x10]; 3940 3941 u8 reserved_at_40[0x20]; 3942 3943 u8 reserved_at_60[0x20]; 3944 }; 3945 3946 struct mlx5_ifc_arm_monitor_counter_out_bits { 3947 u8 status[0x8]; 3948 u8 reserved_at_8[0x18]; 3949 3950 u8 syndrome[0x20]; 3951 3952 u8 reserved_at_40[0x40]; 3953 }; 3954 3955 enum { 3956 MLX5_QUERY_MONITOR_CNT_TYPE_PPCNT = 0x0, 3957 MLX5_QUERY_MONITOR_CNT_TYPE_Q_COUNTER = 0x1, 3958 }; 3959 3960 enum mlx5_monitor_counter_ppcnt { 3961 MLX5_QUERY_MONITOR_PPCNT_IN_RANGE_LENGTH_ERRORS = 0x0, 3962 MLX5_QUERY_MONITOR_PPCNT_OUT_OF_RANGE_LENGTH_FIELD = 0x1, 3963 MLX5_QUERY_MONITOR_PPCNT_FRAME_TOO_LONG_ERRORS = 0x2, 3964 MLX5_QUERY_MONITOR_PPCNT_FRAME_CHECK_SEQUENCE_ERRORS = 0x3, 3965 MLX5_QUERY_MONITOR_PPCNT_ALIGNMENT_ERRORS = 0x4, 3966 MLX5_QUERY_MONITOR_PPCNT_IF_OUT_DISCARDS = 0x5, 3967 }; 3968 3969 enum { 3970 MLX5_QUERY_MONITOR_Q_COUNTER_RX_OUT_OF_BUFFER = 0x4, 3971 }; 3972 3973 struct mlx5_ifc_monitor_counter_output_bits { 3974 u8 reserved_at_0[0x4]; 3975 u8 type[0x4]; 3976 u8 reserved_at_8[0x8]; 3977 u8 counter[0x10]; 3978 3979 u8 counter_group_id[0x20]; 3980 }; 3981 3982 #define MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 (6) 3983 #define MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1 (1) 3984 #define MLX5_CMD_SET_MONITOR_NUM_COUNTER (MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 +\ 3985 MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1) 3986 3987 struct mlx5_ifc_set_monitor_counter_in_bits { 3988 u8 opcode[0x10]; 3989 u8 uid[0x10]; 3990 3991 u8 reserved_at_20[0x10]; 3992 u8 op_mod[0x10]; 3993 3994 u8 reserved_at_40[0x10]; 3995 u8 num_of_counters[0x10]; 3996 3997 u8 reserved_at_60[0x20]; 3998 3999 struct mlx5_ifc_monitor_counter_output_bits monitor_counter[MLX5_CMD_SET_MONITOR_NUM_COUNTER]; 4000 }; 4001 4002 struct mlx5_ifc_set_monitor_counter_out_bits { 4003 u8 status[0x8]; 4004 u8 reserved_at_8[0x18]; 4005 4006 u8 syndrome[0x20]; 4007 4008 u8 reserved_at_40[0x40]; 4009 }; 4010 4011 struct mlx5_ifc_query_vport_state_in_bits { 4012 u8 opcode[0x10]; 4013 u8 reserved_at_10[0x10]; 4014 4015 u8 reserved_at_20[0x10]; 4016 u8 op_mod[0x10]; 4017 4018 u8 other_vport[0x1]; 4019 u8 reserved_at_41[0xf]; 4020 u8 vport_number[0x10]; 4021 4022 u8 reserved_at_60[0x20]; 4023 }; 4024 4025 struct mlx5_ifc_query_vnic_env_out_bits { 4026 u8 status[0x8]; 4027 u8 reserved_at_8[0x18]; 4028 4029 u8 syndrome[0x20]; 4030 4031 u8 reserved_at_40[0x40]; 4032 4033 struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env; 4034 }; 4035 4036 enum { 4037 MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS = 0x0, 4038 }; 4039 4040 struct mlx5_ifc_query_vnic_env_in_bits { 4041 u8 opcode[0x10]; 4042 u8 reserved_at_10[0x10]; 4043 4044 u8 reserved_at_20[0x10]; 4045 u8 op_mod[0x10]; 4046 4047 u8 other_vport[0x1]; 4048 u8 reserved_at_41[0xf]; 4049 u8 vport_number[0x10]; 4050 4051 u8 reserved_at_60[0x20]; 4052 }; 4053 4054 struct mlx5_ifc_query_vport_counter_out_bits { 4055 u8 status[0x8]; 4056 u8 reserved_at_8[0x18]; 4057 4058 u8 syndrome[0x20]; 4059 4060 u8 reserved_at_40[0x40]; 4061 4062 struct mlx5_ifc_traffic_counter_bits received_errors; 4063 4064 struct mlx5_ifc_traffic_counter_bits transmit_errors; 4065 4066 struct mlx5_ifc_traffic_counter_bits received_ib_unicast; 4067 4068 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast; 4069 4070 struct mlx5_ifc_traffic_counter_bits received_ib_multicast; 4071 4072 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast; 4073 4074 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast; 4075 4076 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast; 4077 4078 struct mlx5_ifc_traffic_counter_bits received_eth_unicast; 4079 4080 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast; 4081 4082 struct mlx5_ifc_traffic_counter_bits received_eth_multicast; 4083 4084 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast; 4085 4086 u8 reserved_at_680[0xa00]; 4087 }; 4088 4089 enum { 4090 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0, 4091 }; 4092 4093 struct mlx5_ifc_query_vport_counter_in_bits { 4094 u8 opcode[0x10]; 4095 u8 reserved_at_10[0x10]; 4096 4097 u8 reserved_at_20[0x10]; 4098 u8 op_mod[0x10]; 4099 4100 u8 other_vport[0x1]; 4101 u8 reserved_at_41[0xb]; 4102 u8 port_num[0x4]; 4103 u8 vport_number[0x10]; 4104 4105 u8 reserved_at_60[0x60]; 4106 4107 u8 clear[0x1]; 4108 u8 reserved_at_c1[0x1f]; 4109 4110 u8 reserved_at_e0[0x20]; 4111 }; 4112 4113 struct mlx5_ifc_query_tis_out_bits { 4114 u8 status[0x8]; 4115 u8 reserved_at_8[0x18]; 4116 4117 u8 syndrome[0x20]; 4118 4119 u8 reserved_at_40[0x40]; 4120 4121 struct mlx5_ifc_tisc_bits tis_context; 4122 }; 4123 4124 struct mlx5_ifc_query_tis_in_bits { 4125 u8 opcode[0x10]; 4126 u8 reserved_at_10[0x10]; 4127 4128 u8 reserved_at_20[0x10]; 4129 u8 op_mod[0x10]; 4130 4131 u8 reserved_at_40[0x8]; 4132 u8 tisn[0x18]; 4133 4134 u8 reserved_at_60[0x20]; 4135 }; 4136 4137 struct mlx5_ifc_query_tir_out_bits { 4138 u8 status[0x8]; 4139 u8 reserved_at_8[0x18]; 4140 4141 u8 syndrome[0x20]; 4142 4143 u8 reserved_at_40[0xc0]; 4144 4145 struct mlx5_ifc_tirc_bits tir_context; 4146 }; 4147 4148 struct mlx5_ifc_query_tir_in_bits { 4149 u8 opcode[0x10]; 4150 u8 reserved_at_10[0x10]; 4151 4152 u8 reserved_at_20[0x10]; 4153 u8 op_mod[0x10]; 4154 4155 u8 reserved_at_40[0x8]; 4156 u8 tirn[0x18]; 4157 4158 u8 reserved_at_60[0x20]; 4159 }; 4160 4161 struct mlx5_ifc_query_srq_out_bits { 4162 u8 status[0x8]; 4163 u8 reserved_at_8[0x18]; 4164 4165 u8 syndrome[0x20]; 4166 4167 u8 reserved_at_40[0x40]; 4168 4169 struct mlx5_ifc_srqc_bits srq_context_entry; 4170 4171 u8 reserved_at_280[0x600]; 4172 4173 u8 pas[0][0x40]; 4174 }; 4175 4176 struct mlx5_ifc_query_srq_in_bits { 4177 u8 opcode[0x10]; 4178 u8 reserved_at_10[0x10]; 4179 4180 u8 reserved_at_20[0x10]; 4181 u8 op_mod[0x10]; 4182 4183 u8 reserved_at_40[0x8]; 4184 u8 srqn[0x18]; 4185 4186 u8 reserved_at_60[0x20]; 4187 }; 4188 4189 struct mlx5_ifc_query_sq_out_bits { 4190 u8 status[0x8]; 4191 u8 reserved_at_8[0x18]; 4192 4193 u8 syndrome[0x20]; 4194 4195 u8 reserved_at_40[0xc0]; 4196 4197 struct mlx5_ifc_sqc_bits sq_context; 4198 }; 4199 4200 struct mlx5_ifc_query_sq_in_bits { 4201 u8 opcode[0x10]; 4202 u8 reserved_at_10[0x10]; 4203 4204 u8 reserved_at_20[0x10]; 4205 u8 op_mod[0x10]; 4206 4207 u8 reserved_at_40[0x8]; 4208 u8 sqn[0x18]; 4209 4210 u8 reserved_at_60[0x20]; 4211 }; 4212 4213 struct mlx5_ifc_query_special_contexts_out_bits { 4214 u8 status[0x8]; 4215 u8 reserved_at_8[0x18]; 4216 4217 u8 syndrome[0x20]; 4218 4219 u8 dump_fill_mkey[0x20]; 4220 4221 u8 resd_lkey[0x20]; 4222 4223 u8 null_mkey[0x20]; 4224 4225 u8 reserved_at_a0[0x60]; 4226 }; 4227 4228 struct mlx5_ifc_query_special_contexts_in_bits { 4229 u8 opcode[0x10]; 4230 u8 reserved_at_10[0x10]; 4231 4232 u8 reserved_at_20[0x10]; 4233 u8 op_mod[0x10]; 4234 4235 u8 reserved_at_40[0x40]; 4236 }; 4237 4238 struct mlx5_ifc_query_scheduling_element_out_bits { 4239 u8 opcode[0x10]; 4240 u8 reserved_at_10[0x10]; 4241 4242 u8 reserved_at_20[0x10]; 4243 u8 op_mod[0x10]; 4244 4245 u8 reserved_at_40[0xc0]; 4246 4247 struct mlx5_ifc_scheduling_context_bits scheduling_context; 4248 4249 u8 reserved_at_300[0x100]; 4250 }; 4251 4252 enum { 4253 SCHEDULING_HIERARCHY_E_SWITCH = 0x2, 4254 }; 4255 4256 struct mlx5_ifc_query_scheduling_element_in_bits { 4257 u8 opcode[0x10]; 4258 u8 reserved_at_10[0x10]; 4259 4260 u8 reserved_at_20[0x10]; 4261 u8 op_mod[0x10]; 4262 4263 u8 scheduling_hierarchy[0x8]; 4264 u8 reserved_at_48[0x18]; 4265 4266 u8 scheduling_element_id[0x20]; 4267 4268 u8 reserved_at_80[0x180]; 4269 }; 4270 4271 struct mlx5_ifc_query_rqt_out_bits { 4272 u8 status[0x8]; 4273 u8 reserved_at_8[0x18]; 4274 4275 u8 syndrome[0x20]; 4276 4277 u8 reserved_at_40[0xc0]; 4278 4279 struct mlx5_ifc_rqtc_bits rqt_context; 4280 }; 4281 4282 struct mlx5_ifc_query_rqt_in_bits { 4283 u8 opcode[0x10]; 4284 u8 reserved_at_10[0x10]; 4285 4286 u8 reserved_at_20[0x10]; 4287 u8 op_mod[0x10]; 4288 4289 u8 reserved_at_40[0x8]; 4290 u8 rqtn[0x18]; 4291 4292 u8 reserved_at_60[0x20]; 4293 }; 4294 4295 struct mlx5_ifc_query_rq_out_bits { 4296 u8 status[0x8]; 4297 u8 reserved_at_8[0x18]; 4298 4299 u8 syndrome[0x20]; 4300 4301 u8 reserved_at_40[0xc0]; 4302 4303 struct mlx5_ifc_rqc_bits rq_context; 4304 }; 4305 4306 struct mlx5_ifc_query_rq_in_bits { 4307 u8 opcode[0x10]; 4308 u8 reserved_at_10[0x10]; 4309 4310 u8 reserved_at_20[0x10]; 4311 u8 op_mod[0x10]; 4312 4313 u8 reserved_at_40[0x8]; 4314 u8 rqn[0x18]; 4315 4316 u8 reserved_at_60[0x20]; 4317 }; 4318 4319 struct mlx5_ifc_query_roce_address_out_bits { 4320 u8 status[0x8]; 4321 u8 reserved_at_8[0x18]; 4322 4323 u8 syndrome[0x20]; 4324 4325 u8 reserved_at_40[0x40]; 4326 4327 struct mlx5_ifc_roce_addr_layout_bits roce_address; 4328 }; 4329 4330 struct mlx5_ifc_query_roce_address_in_bits { 4331 u8 opcode[0x10]; 4332 u8 reserved_at_10[0x10]; 4333 4334 u8 reserved_at_20[0x10]; 4335 u8 op_mod[0x10]; 4336 4337 u8 roce_address_index[0x10]; 4338 u8 reserved_at_50[0xc]; 4339 u8 vhca_port_num[0x4]; 4340 4341 u8 reserved_at_60[0x20]; 4342 }; 4343 4344 struct mlx5_ifc_query_rmp_out_bits { 4345 u8 status[0x8]; 4346 u8 reserved_at_8[0x18]; 4347 4348 u8 syndrome[0x20]; 4349 4350 u8 reserved_at_40[0xc0]; 4351 4352 struct mlx5_ifc_rmpc_bits rmp_context; 4353 }; 4354 4355 struct mlx5_ifc_query_rmp_in_bits { 4356 u8 opcode[0x10]; 4357 u8 reserved_at_10[0x10]; 4358 4359 u8 reserved_at_20[0x10]; 4360 u8 op_mod[0x10]; 4361 4362 u8 reserved_at_40[0x8]; 4363 u8 rmpn[0x18]; 4364 4365 u8 reserved_at_60[0x20]; 4366 }; 4367 4368 struct mlx5_ifc_query_qp_out_bits { 4369 u8 status[0x8]; 4370 u8 reserved_at_8[0x18]; 4371 4372 u8 syndrome[0x20]; 4373 4374 u8 reserved_at_40[0x40]; 4375 4376 u8 opt_param_mask[0x20]; 4377 4378 u8 reserved_at_a0[0x20]; 4379 4380 struct mlx5_ifc_qpc_bits qpc; 4381 4382 u8 reserved_at_800[0x80]; 4383 4384 u8 pas[0][0x40]; 4385 }; 4386 4387 struct mlx5_ifc_query_qp_in_bits { 4388 u8 opcode[0x10]; 4389 u8 reserved_at_10[0x10]; 4390 4391 u8 reserved_at_20[0x10]; 4392 u8 op_mod[0x10]; 4393 4394 u8 reserved_at_40[0x8]; 4395 u8 qpn[0x18]; 4396 4397 u8 reserved_at_60[0x20]; 4398 }; 4399 4400 struct mlx5_ifc_query_q_counter_out_bits { 4401 u8 status[0x8]; 4402 u8 reserved_at_8[0x18]; 4403 4404 u8 syndrome[0x20]; 4405 4406 u8 reserved_at_40[0x40]; 4407 4408 u8 rx_write_requests[0x20]; 4409 4410 u8 reserved_at_a0[0x20]; 4411 4412 u8 rx_read_requests[0x20]; 4413 4414 u8 reserved_at_e0[0x20]; 4415 4416 u8 rx_atomic_requests[0x20]; 4417 4418 u8 reserved_at_120[0x20]; 4419 4420 u8 rx_dct_connect[0x20]; 4421 4422 u8 reserved_at_160[0x20]; 4423 4424 u8 out_of_buffer[0x20]; 4425 4426 u8 reserved_at_1a0[0x20]; 4427 4428 u8 out_of_sequence[0x20]; 4429 4430 u8 reserved_at_1e0[0x20]; 4431 4432 u8 duplicate_request[0x20]; 4433 4434 u8 reserved_at_220[0x20]; 4435 4436 u8 rnr_nak_retry_err[0x20]; 4437 4438 u8 reserved_at_260[0x20]; 4439 4440 u8 packet_seq_err[0x20]; 4441 4442 u8 reserved_at_2a0[0x20]; 4443 4444 u8 implied_nak_seq_err[0x20]; 4445 4446 u8 reserved_at_2e0[0x20]; 4447 4448 u8 local_ack_timeout_err[0x20]; 4449 4450 u8 reserved_at_320[0xa0]; 4451 4452 u8 resp_local_length_error[0x20]; 4453 4454 u8 req_local_length_error[0x20]; 4455 4456 u8 resp_local_qp_error[0x20]; 4457 4458 u8 local_operation_error[0x20]; 4459 4460 u8 resp_local_protection[0x20]; 4461 4462 u8 req_local_protection[0x20]; 4463 4464 u8 resp_cqe_error[0x20]; 4465 4466 u8 req_cqe_error[0x20]; 4467 4468 u8 req_mw_binding[0x20]; 4469 4470 u8 req_bad_response[0x20]; 4471 4472 u8 req_remote_invalid_request[0x20]; 4473 4474 u8 resp_remote_invalid_request[0x20]; 4475 4476 u8 req_remote_access_errors[0x20]; 4477 4478 u8 resp_remote_access_errors[0x20]; 4479 4480 u8 req_remote_operation_errors[0x20]; 4481 4482 u8 req_transport_retries_exceeded[0x20]; 4483 4484 u8 cq_overflow[0x20]; 4485 4486 u8 resp_cqe_flush_error[0x20]; 4487 4488 u8 req_cqe_flush_error[0x20]; 4489 4490 u8 reserved_at_620[0x1e0]; 4491 }; 4492 4493 struct mlx5_ifc_query_q_counter_in_bits { 4494 u8 opcode[0x10]; 4495 u8 reserved_at_10[0x10]; 4496 4497 u8 reserved_at_20[0x10]; 4498 u8 op_mod[0x10]; 4499 4500 u8 reserved_at_40[0x80]; 4501 4502 u8 clear[0x1]; 4503 u8 reserved_at_c1[0x1f]; 4504 4505 u8 reserved_at_e0[0x18]; 4506 u8 counter_set_id[0x8]; 4507 }; 4508 4509 struct mlx5_ifc_query_pages_out_bits { 4510 u8 status[0x8]; 4511 u8 reserved_at_8[0x18]; 4512 4513 u8 syndrome[0x20]; 4514 4515 u8 embedded_cpu_function[0x1]; 4516 u8 reserved_at_41[0xf]; 4517 u8 function_id[0x10]; 4518 4519 u8 num_pages[0x20]; 4520 }; 4521 4522 enum { 4523 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1, 4524 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2, 4525 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3, 4526 }; 4527 4528 struct mlx5_ifc_query_pages_in_bits { 4529 u8 opcode[0x10]; 4530 u8 reserved_at_10[0x10]; 4531 4532 u8 reserved_at_20[0x10]; 4533 u8 op_mod[0x10]; 4534 4535 u8 embedded_cpu_function[0x1]; 4536 u8 reserved_at_41[0xf]; 4537 u8 function_id[0x10]; 4538 4539 u8 reserved_at_60[0x20]; 4540 }; 4541 4542 struct mlx5_ifc_query_nic_vport_context_out_bits { 4543 u8 status[0x8]; 4544 u8 reserved_at_8[0x18]; 4545 4546 u8 syndrome[0x20]; 4547 4548 u8 reserved_at_40[0x40]; 4549 4550 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 4551 }; 4552 4553 struct mlx5_ifc_query_nic_vport_context_in_bits { 4554 u8 opcode[0x10]; 4555 u8 reserved_at_10[0x10]; 4556 4557 u8 reserved_at_20[0x10]; 4558 u8 op_mod[0x10]; 4559 4560 u8 other_vport[0x1]; 4561 u8 reserved_at_41[0xf]; 4562 u8 vport_number[0x10]; 4563 4564 u8 reserved_at_60[0x5]; 4565 u8 allowed_list_type[0x3]; 4566 u8 reserved_at_68[0x18]; 4567 }; 4568 4569 struct mlx5_ifc_query_mkey_out_bits { 4570 u8 status[0x8]; 4571 u8 reserved_at_8[0x18]; 4572 4573 u8 syndrome[0x20]; 4574 4575 u8 reserved_at_40[0x40]; 4576 4577 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 4578 4579 u8 reserved_at_280[0x600]; 4580 4581 u8 bsf0_klm0_pas_mtt0_1[16][0x8]; 4582 4583 u8 bsf1_klm1_pas_mtt2_3[16][0x8]; 4584 }; 4585 4586 struct mlx5_ifc_query_mkey_in_bits { 4587 u8 opcode[0x10]; 4588 u8 reserved_at_10[0x10]; 4589 4590 u8 reserved_at_20[0x10]; 4591 u8 op_mod[0x10]; 4592 4593 u8 reserved_at_40[0x8]; 4594 u8 mkey_index[0x18]; 4595 4596 u8 pg_access[0x1]; 4597 u8 reserved_at_61[0x1f]; 4598 }; 4599 4600 struct mlx5_ifc_query_mad_demux_out_bits { 4601 u8 status[0x8]; 4602 u8 reserved_at_8[0x18]; 4603 4604 u8 syndrome[0x20]; 4605 4606 u8 reserved_at_40[0x40]; 4607 4608 u8 mad_dumux_parameters_block[0x20]; 4609 }; 4610 4611 struct mlx5_ifc_query_mad_demux_in_bits { 4612 u8 opcode[0x10]; 4613 u8 reserved_at_10[0x10]; 4614 4615 u8 reserved_at_20[0x10]; 4616 u8 op_mod[0x10]; 4617 4618 u8 reserved_at_40[0x40]; 4619 }; 4620 4621 struct mlx5_ifc_query_l2_table_entry_out_bits { 4622 u8 status[0x8]; 4623 u8 reserved_at_8[0x18]; 4624 4625 u8 syndrome[0x20]; 4626 4627 u8 reserved_at_40[0xa0]; 4628 4629 u8 reserved_at_e0[0x13]; 4630 u8 vlan_valid[0x1]; 4631 u8 vlan[0xc]; 4632 4633 struct mlx5_ifc_mac_address_layout_bits mac_address; 4634 4635 u8 reserved_at_140[0xc0]; 4636 }; 4637 4638 struct mlx5_ifc_query_l2_table_entry_in_bits { 4639 u8 opcode[0x10]; 4640 u8 reserved_at_10[0x10]; 4641 4642 u8 reserved_at_20[0x10]; 4643 u8 op_mod[0x10]; 4644 4645 u8 reserved_at_40[0x60]; 4646 4647 u8 reserved_at_a0[0x8]; 4648 u8 table_index[0x18]; 4649 4650 u8 reserved_at_c0[0x140]; 4651 }; 4652 4653 struct mlx5_ifc_query_issi_out_bits { 4654 u8 status[0x8]; 4655 u8 reserved_at_8[0x18]; 4656 4657 u8 syndrome[0x20]; 4658 4659 u8 reserved_at_40[0x10]; 4660 u8 current_issi[0x10]; 4661 4662 u8 reserved_at_60[0xa0]; 4663 4664 u8 reserved_at_100[76][0x8]; 4665 u8 supported_issi_dw0[0x20]; 4666 }; 4667 4668 struct mlx5_ifc_query_issi_in_bits { 4669 u8 opcode[0x10]; 4670 u8 reserved_at_10[0x10]; 4671 4672 u8 reserved_at_20[0x10]; 4673 u8 op_mod[0x10]; 4674 4675 u8 reserved_at_40[0x40]; 4676 }; 4677 4678 struct mlx5_ifc_set_driver_version_out_bits { 4679 u8 status[0x8]; 4680 u8 reserved_0[0x18]; 4681 4682 u8 syndrome[0x20]; 4683 u8 reserved_1[0x40]; 4684 }; 4685 4686 struct mlx5_ifc_set_driver_version_in_bits { 4687 u8 opcode[0x10]; 4688 u8 reserved_0[0x10]; 4689 4690 u8 reserved_1[0x10]; 4691 u8 op_mod[0x10]; 4692 4693 u8 reserved_2[0x40]; 4694 u8 driver_version[64][0x8]; 4695 }; 4696 4697 struct mlx5_ifc_query_hca_vport_pkey_out_bits { 4698 u8 status[0x8]; 4699 u8 reserved_at_8[0x18]; 4700 4701 u8 syndrome[0x20]; 4702 4703 u8 reserved_at_40[0x40]; 4704 4705 struct mlx5_ifc_pkey_bits pkey[0]; 4706 }; 4707 4708 struct mlx5_ifc_query_hca_vport_pkey_in_bits { 4709 u8 opcode[0x10]; 4710 u8 reserved_at_10[0x10]; 4711 4712 u8 reserved_at_20[0x10]; 4713 u8 op_mod[0x10]; 4714 4715 u8 other_vport[0x1]; 4716 u8 reserved_at_41[0xb]; 4717 u8 port_num[0x4]; 4718 u8 vport_number[0x10]; 4719 4720 u8 reserved_at_60[0x10]; 4721 u8 pkey_index[0x10]; 4722 }; 4723 4724 enum { 4725 MLX5_HCA_VPORT_SEL_PORT_GUID = 1 << 0, 4726 MLX5_HCA_VPORT_SEL_NODE_GUID = 1 << 1, 4727 MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2, 4728 }; 4729 4730 struct mlx5_ifc_query_hca_vport_gid_out_bits { 4731 u8 status[0x8]; 4732 u8 reserved_at_8[0x18]; 4733 4734 u8 syndrome[0x20]; 4735 4736 u8 reserved_at_40[0x20]; 4737 4738 u8 gids_num[0x10]; 4739 u8 reserved_at_70[0x10]; 4740 4741 struct mlx5_ifc_array128_auto_bits gid[0]; 4742 }; 4743 4744 struct mlx5_ifc_query_hca_vport_gid_in_bits { 4745 u8 opcode[0x10]; 4746 u8 reserved_at_10[0x10]; 4747 4748 u8 reserved_at_20[0x10]; 4749 u8 op_mod[0x10]; 4750 4751 u8 other_vport[0x1]; 4752 u8 reserved_at_41[0xb]; 4753 u8 port_num[0x4]; 4754 u8 vport_number[0x10]; 4755 4756 u8 reserved_at_60[0x10]; 4757 u8 gid_index[0x10]; 4758 }; 4759 4760 struct mlx5_ifc_query_hca_vport_context_out_bits { 4761 u8 status[0x8]; 4762 u8 reserved_at_8[0x18]; 4763 4764 u8 syndrome[0x20]; 4765 4766 u8 reserved_at_40[0x40]; 4767 4768 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 4769 }; 4770 4771 struct mlx5_ifc_query_hca_vport_context_in_bits { 4772 u8 opcode[0x10]; 4773 u8 reserved_at_10[0x10]; 4774 4775 u8 reserved_at_20[0x10]; 4776 u8 op_mod[0x10]; 4777 4778 u8 other_vport[0x1]; 4779 u8 reserved_at_41[0xb]; 4780 u8 port_num[0x4]; 4781 u8 vport_number[0x10]; 4782 4783 u8 reserved_at_60[0x20]; 4784 }; 4785 4786 struct mlx5_ifc_query_hca_cap_out_bits { 4787 u8 status[0x8]; 4788 u8 reserved_at_8[0x18]; 4789 4790 u8 syndrome[0x20]; 4791 4792 u8 reserved_at_40[0x40]; 4793 4794 union mlx5_ifc_hca_cap_union_bits capability; 4795 }; 4796 4797 struct mlx5_ifc_query_hca_cap_in_bits { 4798 u8 opcode[0x10]; 4799 u8 reserved_at_10[0x10]; 4800 4801 u8 reserved_at_20[0x10]; 4802 u8 op_mod[0x10]; 4803 4804 u8 reserved_at_40[0x40]; 4805 }; 4806 4807 struct mlx5_ifc_query_flow_table_out_bits { 4808 u8 status[0x8]; 4809 u8 reserved_at_8[0x18]; 4810 4811 u8 syndrome[0x20]; 4812 4813 u8 reserved_at_40[0x80]; 4814 4815 u8 reserved_at_c0[0x8]; 4816 u8 level[0x8]; 4817 u8 reserved_at_d0[0x8]; 4818 u8 log_size[0x8]; 4819 4820 u8 reserved_at_e0[0x120]; 4821 }; 4822 4823 struct mlx5_ifc_query_flow_table_in_bits { 4824 u8 opcode[0x10]; 4825 u8 reserved_at_10[0x10]; 4826 4827 u8 reserved_at_20[0x10]; 4828 u8 op_mod[0x10]; 4829 4830 u8 reserved_at_40[0x40]; 4831 4832 u8 table_type[0x8]; 4833 u8 reserved_at_88[0x18]; 4834 4835 u8 reserved_at_a0[0x8]; 4836 u8 table_id[0x18]; 4837 4838 u8 reserved_at_c0[0x140]; 4839 }; 4840 4841 struct mlx5_ifc_query_fte_out_bits { 4842 u8 status[0x8]; 4843 u8 reserved_at_8[0x18]; 4844 4845 u8 syndrome[0x20]; 4846 4847 u8 reserved_at_40[0x1c0]; 4848 4849 struct mlx5_ifc_flow_context_bits flow_context; 4850 }; 4851 4852 struct mlx5_ifc_query_fte_in_bits { 4853 u8 opcode[0x10]; 4854 u8 reserved_at_10[0x10]; 4855 4856 u8 reserved_at_20[0x10]; 4857 u8 op_mod[0x10]; 4858 4859 u8 reserved_at_40[0x40]; 4860 4861 u8 table_type[0x8]; 4862 u8 reserved_at_88[0x18]; 4863 4864 u8 reserved_at_a0[0x8]; 4865 u8 table_id[0x18]; 4866 4867 u8 reserved_at_c0[0x40]; 4868 4869 u8 flow_index[0x20]; 4870 4871 u8 reserved_at_120[0xe0]; 4872 }; 4873 4874 enum { 4875 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 4876 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 4877 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 4878 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3, 4879 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_3 = 0x4, 4880 }; 4881 4882 struct mlx5_ifc_query_flow_group_out_bits { 4883 u8 status[0x8]; 4884 u8 reserved_at_8[0x18]; 4885 4886 u8 syndrome[0x20]; 4887 4888 u8 reserved_at_40[0xa0]; 4889 4890 u8 start_flow_index[0x20]; 4891 4892 u8 reserved_at_100[0x20]; 4893 4894 u8 end_flow_index[0x20]; 4895 4896 u8 reserved_at_140[0xa0]; 4897 4898 u8 reserved_at_1e0[0x18]; 4899 u8 match_criteria_enable[0x8]; 4900 4901 struct mlx5_ifc_fte_match_param_bits match_criteria; 4902 4903 u8 reserved_at_1200[0xe00]; 4904 }; 4905 4906 struct mlx5_ifc_query_flow_group_in_bits { 4907 u8 opcode[0x10]; 4908 u8 reserved_at_10[0x10]; 4909 4910 u8 reserved_at_20[0x10]; 4911 u8 op_mod[0x10]; 4912 4913 u8 reserved_at_40[0x40]; 4914 4915 u8 table_type[0x8]; 4916 u8 reserved_at_88[0x18]; 4917 4918 u8 reserved_at_a0[0x8]; 4919 u8 table_id[0x18]; 4920 4921 u8 group_id[0x20]; 4922 4923 u8 reserved_at_e0[0x120]; 4924 }; 4925 4926 struct mlx5_ifc_query_flow_counter_out_bits { 4927 u8 status[0x8]; 4928 u8 reserved_at_8[0x18]; 4929 4930 u8 syndrome[0x20]; 4931 4932 u8 reserved_at_40[0x40]; 4933 4934 struct mlx5_ifc_traffic_counter_bits flow_statistics[0]; 4935 }; 4936 4937 struct mlx5_ifc_query_flow_counter_in_bits { 4938 u8 opcode[0x10]; 4939 u8 reserved_at_10[0x10]; 4940 4941 u8 reserved_at_20[0x10]; 4942 u8 op_mod[0x10]; 4943 4944 u8 reserved_at_40[0x80]; 4945 4946 u8 clear[0x1]; 4947 u8 reserved_at_c1[0xf]; 4948 u8 num_of_counters[0x10]; 4949 4950 u8 flow_counter_id[0x20]; 4951 }; 4952 4953 struct mlx5_ifc_query_esw_vport_context_out_bits { 4954 u8 status[0x8]; 4955 u8 reserved_at_8[0x18]; 4956 4957 u8 syndrome[0x20]; 4958 4959 u8 reserved_at_40[0x40]; 4960 4961 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 4962 }; 4963 4964 struct mlx5_ifc_query_esw_vport_context_in_bits { 4965 u8 opcode[0x10]; 4966 u8 reserved_at_10[0x10]; 4967 4968 u8 reserved_at_20[0x10]; 4969 u8 op_mod[0x10]; 4970 4971 u8 other_vport[0x1]; 4972 u8 reserved_at_41[0xf]; 4973 u8 vport_number[0x10]; 4974 4975 u8 reserved_at_60[0x20]; 4976 }; 4977 4978 struct mlx5_ifc_modify_esw_vport_context_out_bits { 4979 u8 status[0x8]; 4980 u8 reserved_at_8[0x18]; 4981 4982 u8 syndrome[0x20]; 4983 4984 u8 reserved_at_40[0x40]; 4985 }; 4986 4987 struct mlx5_ifc_esw_vport_context_fields_select_bits { 4988 u8 reserved_at_0[0x1c]; 4989 u8 vport_cvlan_insert[0x1]; 4990 u8 vport_svlan_insert[0x1]; 4991 u8 vport_cvlan_strip[0x1]; 4992 u8 vport_svlan_strip[0x1]; 4993 }; 4994 4995 struct mlx5_ifc_modify_esw_vport_context_in_bits { 4996 u8 opcode[0x10]; 4997 u8 reserved_at_10[0x10]; 4998 4999 u8 reserved_at_20[0x10]; 5000 u8 op_mod[0x10]; 5001 5002 u8 other_vport[0x1]; 5003 u8 reserved_at_41[0xf]; 5004 u8 vport_number[0x10]; 5005 5006 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select; 5007 5008 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 5009 }; 5010 5011 struct mlx5_ifc_query_eq_out_bits { 5012 u8 status[0x8]; 5013 u8 reserved_at_8[0x18]; 5014 5015 u8 syndrome[0x20]; 5016 5017 u8 reserved_at_40[0x40]; 5018 5019 struct mlx5_ifc_eqc_bits eq_context_entry; 5020 5021 u8 reserved_at_280[0x40]; 5022 5023 u8 event_bitmask[0x40]; 5024 5025 u8 reserved_at_300[0x580]; 5026 5027 u8 pas[0][0x40]; 5028 }; 5029 5030 struct mlx5_ifc_query_eq_in_bits { 5031 u8 opcode[0x10]; 5032 u8 reserved_at_10[0x10]; 5033 5034 u8 reserved_at_20[0x10]; 5035 u8 op_mod[0x10]; 5036 5037 u8 reserved_at_40[0x18]; 5038 u8 eq_number[0x8]; 5039 5040 u8 reserved_at_60[0x20]; 5041 }; 5042 5043 struct mlx5_ifc_packet_reformat_context_in_bits { 5044 u8 reserved_at_0[0x5]; 5045 u8 reformat_type[0x3]; 5046 u8 reserved_at_8[0xe]; 5047 u8 reformat_data_size[0xa]; 5048 5049 u8 reserved_at_20[0x10]; 5050 u8 reformat_data[2][0x8]; 5051 5052 u8 more_reformat_data[0][0x8]; 5053 }; 5054 5055 struct mlx5_ifc_query_packet_reformat_context_out_bits { 5056 u8 status[0x8]; 5057 u8 reserved_at_8[0x18]; 5058 5059 u8 syndrome[0x20]; 5060 5061 u8 reserved_at_40[0xa0]; 5062 5063 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context[0]; 5064 }; 5065 5066 struct mlx5_ifc_query_packet_reformat_context_in_bits { 5067 u8 opcode[0x10]; 5068 u8 reserved_at_10[0x10]; 5069 5070 u8 reserved_at_20[0x10]; 5071 u8 op_mod[0x10]; 5072 5073 u8 packet_reformat_id[0x20]; 5074 5075 u8 reserved_at_60[0xa0]; 5076 }; 5077 5078 struct mlx5_ifc_alloc_packet_reformat_context_out_bits { 5079 u8 status[0x8]; 5080 u8 reserved_at_8[0x18]; 5081 5082 u8 syndrome[0x20]; 5083 5084 u8 packet_reformat_id[0x20]; 5085 5086 u8 reserved_at_60[0x20]; 5087 }; 5088 5089 enum { 5090 MLX5_REFORMAT_TYPE_L2_TO_VXLAN = 0x0, 5091 MLX5_REFORMAT_TYPE_L2_TO_NVGRE = 0x1, 5092 MLX5_REFORMAT_TYPE_L2_TO_L2_TUNNEL = 0x2, 5093 MLX5_REFORMAT_TYPE_L3_TUNNEL_TO_L2 = 0x3, 5094 MLX5_REFORMAT_TYPE_L2_TO_L3_TUNNEL = 0x4, 5095 }; 5096 5097 struct mlx5_ifc_alloc_packet_reformat_context_in_bits { 5098 u8 opcode[0x10]; 5099 u8 reserved_at_10[0x10]; 5100 5101 u8 reserved_at_20[0x10]; 5102 u8 op_mod[0x10]; 5103 5104 u8 reserved_at_40[0xa0]; 5105 5106 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context; 5107 }; 5108 5109 struct mlx5_ifc_dealloc_packet_reformat_context_out_bits { 5110 u8 status[0x8]; 5111 u8 reserved_at_8[0x18]; 5112 5113 u8 syndrome[0x20]; 5114 5115 u8 reserved_at_40[0x40]; 5116 }; 5117 5118 struct mlx5_ifc_dealloc_packet_reformat_context_in_bits { 5119 u8 opcode[0x10]; 5120 u8 reserved_at_10[0x10]; 5121 5122 u8 reserved_20[0x10]; 5123 u8 op_mod[0x10]; 5124 5125 u8 packet_reformat_id[0x20]; 5126 5127 u8 reserved_60[0x20]; 5128 }; 5129 5130 struct mlx5_ifc_set_action_in_bits { 5131 u8 action_type[0x4]; 5132 u8 field[0xc]; 5133 u8 reserved_at_10[0x3]; 5134 u8 offset[0x5]; 5135 u8 reserved_at_18[0x3]; 5136 u8 length[0x5]; 5137 5138 u8 data[0x20]; 5139 }; 5140 5141 struct mlx5_ifc_add_action_in_bits { 5142 u8 action_type[0x4]; 5143 u8 field[0xc]; 5144 u8 reserved_at_10[0x10]; 5145 5146 u8 data[0x20]; 5147 }; 5148 5149 union mlx5_ifc_set_action_in_add_action_in_auto_bits { 5150 struct mlx5_ifc_set_action_in_bits set_action_in; 5151 struct mlx5_ifc_add_action_in_bits add_action_in; 5152 u8 reserved_at_0[0x40]; 5153 }; 5154 5155 enum { 5156 MLX5_ACTION_TYPE_SET = 0x1, 5157 MLX5_ACTION_TYPE_ADD = 0x2, 5158 }; 5159 5160 enum { 5161 MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16 = 0x1, 5162 MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0 = 0x2, 5163 MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE = 0x3, 5164 MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16 = 0x4, 5165 MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0 = 0x5, 5166 MLX5_ACTION_IN_FIELD_OUT_IP_DSCP = 0x6, 5167 MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS = 0x7, 5168 MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT = 0x8, 5169 MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT = 0x9, 5170 MLX5_ACTION_IN_FIELD_OUT_IP_TTL = 0xa, 5171 MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT = 0xb, 5172 MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT = 0xc, 5173 MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96 = 0xd, 5174 MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64 = 0xe, 5175 MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32 = 0xf, 5176 MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0 = 0x10, 5177 MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96 = 0x11, 5178 MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64 = 0x12, 5179 MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32 = 0x13, 5180 MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0 = 0x14, 5181 MLX5_ACTION_IN_FIELD_OUT_SIPV4 = 0x15, 5182 MLX5_ACTION_IN_FIELD_OUT_DIPV4 = 0x16, 5183 MLX5_ACTION_IN_FIELD_OUT_FIRST_VID = 0x17, 5184 MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47, 5185 }; 5186 5187 struct mlx5_ifc_alloc_modify_header_context_out_bits { 5188 u8 status[0x8]; 5189 u8 reserved_at_8[0x18]; 5190 5191 u8 syndrome[0x20]; 5192 5193 u8 modify_header_id[0x20]; 5194 5195 u8 reserved_at_60[0x20]; 5196 }; 5197 5198 struct mlx5_ifc_alloc_modify_header_context_in_bits { 5199 u8 opcode[0x10]; 5200 u8 reserved_at_10[0x10]; 5201 5202 u8 reserved_at_20[0x10]; 5203 u8 op_mod[0x10]; 5204 5205 u8 reserved_at_40[0x20]; 5206 5207 u8 table_type[0x8]; 5208 u8 reserved_at_68[0x10]; 5209 u8 num_of_actions[0x8]; 5210 5211 union mlx5_ifc_set_action_in_add_action_in_auto_bits actions[0]; 5212 }; 5213 5214 struct mlx5_ifc_dealloc_modify_header_context_out_bits { 5215 u8 status[0x8]; 5216 u8 reserved_at_8[0x18]; 5217 5218 u8 syndrome[0x20]; 5219 5220 u8 reserved_at_40[0x40]; 5221 }; 5222 5223 struct mlx5_ifc_dealloc_modify_header_context_in_bits { 5224 u8 opcode[0x10]; 5225 u8 reserved_at_10[0x10]; 5226 5227 u8 reserved_at_20[0x10]; 5228 u8 op_mod[0x10]; 5229 5230 u8 modify_header_id[0x20]; 5231 5232 u8 reserved_at_60[0x20]; 5233 }; 5234 5235 struct mlx5_ifc_query_dct_out_bits { 5236 u8 status[0x8]; 5237 u8 reserved_at_8[0x18]; 5238 5239 u8 syndrome[0x20]; 5240 5241 u8 reserved_at_40[0x40]; 5242 5243 struct mlx5_ifc_dctc_bits dct_context_entry; 5244 5245 u8 reserved_at_280[0x180]; 5246 }; 5247 5248 struct mlx5_ifc_query_dct_in_bits { 5249 u8 opcode[0x10]; 5250 u8 reserved_at_10[0x10]; 5251 5252 u8 reserved_at_20[0x10]; 5253 u8 op_mod[0x10]; 5254 5255 u8 reserved_at_40[0x8]; 5256 u8 dctn[0x18]; 5257 5258 u8 reserved_at_60[0x20]; 5259 }; 5260 5261 struct mlx5_ifc_query_cq_out_bits { 5262 u8 status[0x8]; 5263 u8 reserved_at_8[0x18]; 5264 5265 u8 syndrome[0x20]; 5266 5267 u8 reserved_at_40[0x40]; 5268 5269 struct mlx5_ifc_cqc_bits cq_context; 5270 5271 u8 reserved_at_280[0x600]; 5272 5273 u8 pas[0][0x40]; 5274 }; 5275 5276 struct mlx5_ifc_query_cq_in_bits { 5277 u8 opcode[0x10]; 5278 u8 reserved_at_10[0x10]; 5279 5280 u8 reserved_at_20[0x10]; 5281 u8 op_mod[0x10]; 5282 5283 u8 reserved_at_40[0x8]; 5284 u8 cqn[0x18]; 5285 5286 u8 reserved_at_60[0x20]; 5287 }; 5288 5289 struct mlx5_ifc_query_cong_status_out_bits { 5290 u8 status[0x8]; 5291 u8 reserved_at_8[0x18]; 5292 5293 u8 syndrome[0x20]; 5294 5295 u8 reserved_at_40[0x20]; 5296 5297 u8 enable[0x1]; 5298 u8 tag_enable[0x1]; 5299 u8 reserved_at_62[0x1e]; 5300 }; 5301 5302 struct mlx5_ifc_query_cong_status_in_bits { 5303 u8 opcode[0x10]; 5304 u8 reserved_at_10[0x10]; 5305 5306 u8 reserved_at_20[0x10]; 5307 u8 op_mod[0x10]; 5308 5309 u8 reserved_at_40[0x18]; 5310 u8 priority[0x4]; 5311 u8 cong_protocol[0x4]; 5312 5313 u8 reserved_at_60[0x20]; 5314 }; 5315 5316 struct mlx5_ifc_query_cong_statistics_out_bits { 5317 u8 status[0x8]; 5318 u8 reserved_at_8[0x18]; 5319 5320 u8 syndrome[0x20]; 5321 5322 u8 reserved_at_40[0x40]; 5323 5324 u8 rp_cur_flows[0x20]; 5325 5326 u8 sum_flows[0x20]; 5327 5328 u8 rp_cnp_ignored_high[0x20]; 5329 5330 u8 rp_cnp_ignored_low[0x20]; 5331 5332 u8 rp_cnp_handled_high[0x20]; 5333 5334 u8 rp_cnp_handled_low[0x20]; 5335 5336 u8 reserved_at_140[0x100]; 5337 5338 u8 time_stamp_high[0x20]; 5339 5340 u8 time_stamp_low[0x20]; 5341 5342 u8 accumulators_period[0x20]; 5343 5344 u8 np_ecn_marked_roce_packets_high[0x20]; 5345 5346 u8 np_ecn_marked_roce_packets_low[0x20]; 5347 5348 u8 np_cnp_sent_high[0x20]; 5349 5350 u8 np_cnp_sent_low[0x20]; 5351 5352 u8 reserved_at_320[0x560]; 5353 }; 5354 5355 struct mlx5_ifc_query_cong_statistics_in_bits { 5356 u8 opcode[0x10]; 5357 u8 reserved_at_10[0x10]; 5358 5359 u8 reserved_at_20[0x10]; 5360 u8 op_mod[0x10]; 5361 5362 u8 clear[0x1]; 5363 u8 reserved_at_41[0x1f]; 5364 5365 u8 reserved_at_60[0x20]; 5366 }; 5367 5368 struct mlx5_ifc_query_cong_params_out_bits { 5369 u8 status[0x8]; 5370 u8 reserved_at_8[0x18]; 5371 5372 u8 syndrome[0x20]; 5373 5374 u8 reserved_at_40[0x40]; 5375 5376 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 5377 }; 5378 5379 struct mlx5_ifc_query_cong_params_in_bits { 5380 u8 opcode[0x10]; 5381 u8 reserved_at_10[0x10]; 5382 5383 u8 reserved_at_20[0x10]; 5384 u8 op_mod[0x10]; 5385 5386 u8 reserved_at_40[0x1c]; 5387 u8 cong_protocol[0x4]; 5388 5389 u8 reserved_at_60[0x20]; 5390 }; 5391 5392 struct mlx5_ifc_query_adapter_out_bits { 5393 u8 status[0x8]; 5394 u8 reserved_at_8[0x18]; 5395 5396 u8 syndrome[0x20]; 5397 5398 u8 reserved_at_40[0x40]; 5399 5400 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct; 5401 }; 5402 5403 struct mlx5_ifc_query_adapter_in_bits { 5404 u8 opcode[0x10]; 5405 u8 reserved_at_10[0x10]; 5406 5407 u8 reserved_at_20[0x10]; 5408 u8 op_mod[0x10]; 5409 5410 u8 reserved_at_40[0x40]; 5411 }; 5412 5413 struct mlx5_ifc_qp_2rst_out_bits { 5414 u8 status[0x8]; 5415 u8 reserved_at_8[0x18]; 5416 5417 u8 syndrome[0x20]; 5418 5419 u8 reserved_at_40[0x40]; 5420 }; 5421 5422 struct mlx5_ifc_qp_2rst_in_bits { 5423 u8 opcode[0x10]; 5424 u8 uid[0x10]; 5425 5426 u8 reserved_at_20[0x10]; 5427 u8 op_mod[0x10]; 5428 5429 u8 reserved_at_40[0x8]; 5430 u8 qpn[0x18]; 5431 5432 u8 reserved_at_60[0x20]; 5433 }; 5434 5435 struct mlx5_ifc_qp_2err_out_bits { 5436 u8 status[0x8]; 5437 u8 reserved_at_8[0x18]; 5438 5439 u8 syndrome[0x20]; 5440 5441 u8 reserved_at_40[0x40]; 5442 }; 5443 5444 struct mlx5_ifc_qp_2err_in_bits { 5445 u8 opcode[0x10]; 5446 u8 uid[0x10]; 5447 5448 u8 reserved_at_20[0x10]; 5449 u8 op_mod[0x10]; 5450 5451 u8 reserved_at_40[0x8]; 5452 u8 qpn[0x18]; 5453 5454 u8 reserved_at_60[0x20]; 5455 }; 5456 5457 struct mlx5_ifc_page_fault_resume_out_bits { 5458 u8 status[0x8]; 5459 u8 reserved_at_8[0x18]; 5460 5461 u8 syndrome[0x20]; 5462 5463 u8 reserved_at_40[0x40]; 5464 }; 5465 5466 struct mlx5_ifc_page_fault_resume_in_bits { 5467 u8 opcode[0x10]; 5468 u8 reserved_at_10[0x10]; 5469 5470 u8 reserved_at_20[0x10]; 5471 u8 op_mod[0x10]; 5472 5473 u8 error[0x1]; 5474 u8 reserved_at_41[0x4]; 5475 u8 page_fault_type[0x3]; 5476 u8 wq_number[0x18]; 5477 5478 u8 reserved_at_60[0x8]; 5479 u8 token[0x18]; 5480 }; 5481 5482 struct mlx5_ifc_nop_out_bits { 5483 u8 status[0x8]; 5484 u8 reserved_at_8[0x18]; 5485 5486 u8 syndrome[0x20]; 5487 5488 u8 reserved_at_40[0x40]; 5489 }; 5490 5491 struct mlx5_ifc_nop_in_bits { 5492 u8 opcode[0x10]; 5493 u8 reserved_at_10[0x10]; 5494 5495 u8 reserved_at_20[0x10]; 5496 u8 op_mod[0x10]; 5497 5498 u8 reserved_at_40[0x40]; 5499 }; 5500 5501 struct mlx5_ifc_modify_vport_state_out_bits { 5502 u8 status[0x8]; 5503 u8 reserved_at_8[0x18]; 5504 5505 u8 syndrome[0x20]; 5506 5507 u8 reserved_at_40[0x40]; 5508 }; 5509 5510 struct mlx5_ifc_modify_vport_state_in_bits { 5511 u8 opcode[0x10]; 5512 u8 reserved_at_10[0x10]; 5513 5514 u8 reserved_at_20[0x10]; 5515 u8 op_mod[0x10]; 5516 5517 u8 other_vport[0x1]; 5518 u8 reserved_at_41[0xf]; 5519 u8 vport_number[0x10]; 5520 5521 u8 reserved_at_60[0x18]; 5522 u8 admin_state[0x4]; 5523 u8 reserved_at_7c[0x4]; 5524 }; 5525 5526 struct mlx5_ifc_modify_tis_out_bits { 5527 u8 status[0x8]; 5528 u8 reserved_at_8[0x18]; 5529 5530 u8 syndrome[0x20]; 5531 5532 u8 reserved_at_40[0x40]; 5533 }; 5534 5535 struct mlx5_ifc_modify_tis_bitmask_bits { 5536 u8 reserved_at_0[0x20]; 5537 5538 u8 reserved_at_20[0x1d]; 5539 u8 lag_tx_port_affinity[0x1]; 5540 u8 strict_lag_tx_port_affinity[0x1]; 5541 u8 prio[0x1]; 5542 }; 5543 5544 struct mlx5_ifc_modify_tis_in_bits { 5545 u8 opcode[0x10]; 5546 u8 uid[0x10]; 5547 5548 u8 reserved_at_20[0x10]; 5549 u8 op_mod[0x10]; 5550 5551 u8 reserved_at_40[0x8]; 5552 u8 tisn[0x18]; 5553 5554 u8 reserved_at_60[0x20]; 5555 5556 struct mlx5_ifc_modify_tis_bitmask_bits bitmask; 5557 5558 u8 reserved_at_c0[0x40]; 5559 5560 struct mlx5_ifc_tisc_bits ctx; 5561 }; 5562 5563 struct mlx5_ifc_modify_tir_bitmask_bits { 5564 u8 reserved_at_0[0x20]; 5565 5566 u8 reserved_at_20[0x1b]; 5567 u8 self_lb_en[0x1]; 5568 u8 reserved_at_3c[0x1]; 5569 u8 hash[0x1]; 5570 u8 reserved_at_3e[0x1]; 5571 u8 lro[0x1]; 5572 }; 5573 5574 struct mlx5_ifc_modify_tir_out_bits { 5575 u8 status[0x8]; 5576 u8 reserved_at_8[0x18]; 5577 5578 u8 syndrome[0x20]; 5579 5580 u8 reserved_at_40[0x40]; 5581 }; 5582 5583 struct mlx5_ifc_modify_tir_in_bits { 5584 u8 opcode[0x10]; 5585 u8 uid[0x10]; 5586 5587 u8 reserved_at_20[0x10]; 5588 u8 op_mod[0x10]; 5589 5590 u8 reserved_at_40[0x8]; 5591 u8 tirn[0x18]; 5592 5593 u8 reserved_at_60[0x20]; 5594 5595 struct mlx5_ifc_modify_tir_bitmask_bits bitmask; 5596 5597 u8 reserved_at_c0[0x40]; 5598 5599 struct mlx5_ifc_tirc_bits ctx; 5600 }; 5601 5602 struct mlx5_ifc_modify_sq_out_bits { 5603 u8 status[0x8]; 5604 u8 reserved_at_8[0x18]; 5605 5606 u8 syndrome[0x20]; 5607 5608 u8 reserved_at_40[0x40]; 5609 }; 5610 5611 struct mlx5_ifc_modify_sq_in_bits { 5612 u8 opcode[0x10]; 5613 u8 uid[0x10]; 5614 5615 u8 reserved_at_20[0x10]; 5616 u8 op_mod[0x10]; 5617 5618 u8 sq_state[0x4]; 5619 u8 reserved_at_44[0x4]; 5620 u8 sqn[0x18]; 5621 5622 u8 reserved_at_60[0x20]; 5623 5624 u8 modify_bitmask[0x40]; 5625 5626 u8 reserved_at_c0[0x40]; 5627 5628 struct mlx5_ifc_sqc_bits ctx; 5629 }; 5630 5631 struct mlx5_ifc_modify_scheduling_element_out_bits { 5632 u8 status[0x8]; 5633 u8 reserved_at_8[0x18]; 5634 5635 u8 syndrome[0x20]; 5636 5637 u8 reserved_at_40[0x1c0]; 5638 }; 5639 5640 enum { 5641 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1, 5642 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2, 5643 }; 5644 5645 struct mlx5_ifc_modify_scheduling_element_in_bits { 5646 u8 opcode[0x10]; 5647 u8 reserved_at_10[0x10]; 5648 5649 u8 reserved_at_20[0x10]; 5650 u8 op_mod[0x10]; 5651 5652 u8 scheduling_hierarchy[0x8]; 5653 u8 reserved_at_48[0x18]; 5654 5655 u8 scheduling_element_id[0x20]; 5656 5657 u8 reserved_at_80[0x20]; 5658 5659 u8 modify_bitmask[0x20]; 5660 5661 u8 reserved_at_c0[0x40]; 5662 5663 struct mlx5_ifc_scheduling_context_bits scheduling_context; 5664 5665 u8 reserved_at_300[0x100]; 5666 }; 5667 5668 struct mlx5_ifc_modify_rqt_out_bits { 5669 u8 status[0x8]; 5670 u8 reserved_at_8[0x18]; 5671 5672 u8 syndrome[0x20]; 5673 5674 u8 reserved_at_40[0x40]; 5675 }; 5676 5677 struct mlx5_ifc_rqt_bitmask_bits { 5678 u8 reserved_at_0[0x20]; 5679 5680 u8 reserved_at_20[0x1f]; 5681 u8 rqn_list[0x1]; 5682 }; 5683 5684 struct mlx5_ifc_modify_rqt_in_bits { 5685 u8 opcode[0x10]; 5686 u8 uid[0x10]; 5687 5688 u8 reserved_at_20[0x10]; 5689 u8 op_mod[0x10]; 5690 5691 u8 reserved_at_40[0x8]; 5692 u8 rqtn[0x18]; 5693 5694 u8 reserved_at_60[0x20]; 5695 5696 struct mlx5_ifc_rqt_bitmask_bits bitmask; 5697 5698 u8 reserved_at_c0[0x40]; 5699 5700 struct mlx5_ifc_rqtc_bits ctx; 5701 }; 5702 5703 struct mlx5_ifc_modify_rq_out_bits { 5704 u8 status[0x8]; 5705 u8 reserved_at_8[0x18]; 5706 5707 u8 syndrome[0x20]; 5708 5709 u8 reserved_at_40[0x40]; 5710 }; 5711 5712 enum { 5713 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1, 5714 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2, 5715 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3, 5716 }; 5717 5718 struct mlx5_ifc_modify_rq_in_bits { 5719 u8 opcode[0x10]; 5720 u8 uid[0x10]; 5721 5722 u8 reserved_at_20[0x10]; 5723 u8 op_mod[0x10]; 5724 5725 u8 rq_state[0x4]; 5726 u8 reserved_at_44[0x4]; 5727 u8 rqn[0x18]; 5728 5729 u8 reserved_at_60[0x20]; 5730 5731 u8 modify_bitmask[0x40]; 5732 5733 u8 reserved_at_c0[0x40]; 5734 5735 struct mlx5_ifc_rqc_bits ctx; 5736 }; 5737 5738 struct mlx5_ifc_modify_rmp_out_bits { 5739 u8 status[0x8]; 5740 u8 reserved_at_8[0x18]; 5741 5742 u8 syndrome[0x20]; 5743 5744 u8 reserved_at_40[0x40]; 5745 }; 5746 5747 struct mlx5_ifc_rmp_bitmask_bits { 5748 u8 reserved_at_0[0x20]; 5749 5750 u8 reserved_at_20[0x1f]; 5751 u8 lwm[0x1]; 5752 }; 5753 5754 struct mlx5_ifc_modify_rmp_in_bits { 5755 u8 opcode[0x10]; 5756 u8 uid[0x10]; 5757 5758 u8 reserved_at_20[0x10]; 5759 u8 op_mod[0x10]; 5760 5761 u8 rmp_state[0x4]; 5762 u8 reserved_at_44[0x4]; 5763 u8 rmpn[0x18]; 5764 5765 u8 reserved_at_60[0x20]; 5766 5767 struct mlx5_ifc_rmp_bitmask_bits bitmask; 5768 5769 u8 reserved_at_c0[0x40]; 5770 5771 struct mlx5_ifc_rmpc_bits ctx; 5772 }; 5773 5774 struct mlx5_ifc_modify_nic_vport_context_out_bits { 5775 u8 status[0x8]; 5776 u8 reserved_at_8[0x18]; 5777 5778 u8 syndrome[0x20]; 5779 5780 u8 reserved_at_40[0x40]; 5781 }; 5782 5783 struct mlx5_ifc_modify_nic_vport_field_select_bits { 5784 u8 reserved_at_0[0x12]; 5785 u8 affiliation[0x1]; 5786 u8 reserved_at_13[0x1]; 5787 u8 disable_uc_local_lb[0x1]; 5788 u8 disable_mc_local_lb[0x1]; 5789 u8 node_guid[0x1]; 5790 u8 port_guid[0x1]; 5791 u8 min_inline[0x1]; 5792 u8 mtu[0x1]; 5793 u8 change_event[0x1]; 5794 u8 promisc[0x1]; 5795 u8 permanent_address[0x1]; 5796 u8 addresses_list[0x1]; 5797 u8 roce_en[0x1]; 5798 u8 reserved_at_1f[0x1]; 5799 }; 5800 5801 struct mlx5_ifc_modify_nic_vport_context_in_bits { 5802 u8 opcode[0x10]; 5803 u8 reserved_at_10[0x10]; 5804 5805 u8 reserved_at_20[0x10]; 5806 u8 op_mod[0x10]; 5807 5808 u8 other_vport[0x1]; 5809 u8 reserved_at_41[0xf]; 5810 u8 vport_number[0x10]; 5811 5812 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select; 5813 5814 u8 reserved_at_80[0x780]; 5815 5816 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 5817 }; 5818 5819 struct mlx5_ifc_modify_hca_vport_context_out_bits { 5820 u8 status[0x8]; 5821 u8 reserved_at_8[0x18]; 5822 5823 u8 syndrome[0x20]; 5824 5825 u8 reserved_at_40[0x40]; 5826 }; 5827 5828 struct mlx5_ifc_modify_hca_vport_context_in_bits { 5829 u8 opcode[0x10]; 5830 u8 reserved_at_10[0x10]; 5831 5832 u8 reserved_at_20[0x10]; 5833 u8 op_mod[0x10]; 5834 5835 u8 other_vport[0x1]; 5836 u8 reserved_at_41[0xb]; 5837 u8 port_num[0x4]; 5838 u8 vport_number[0x10]; 5839 5840 u8 reserved_at_60[0x20]; 5841 5842 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 5843 }; 5844 5845 struct mlx5_ifc_modify_cq_out_bits { 5846 u8 status[0x8]; 5847 u8 reserved_at_8[0x18]; 5848 5849 u8 syndrome[0x20]; 5850 5851 u8 reserved_at_40[0x40]; 5852 }; 5853 5854 enum { 5855 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0, 5856 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1, 5857 }; 5858 5859 struct mlx5_ifc_modify_cq_in_bits { 5860 u8 opcode[0x10]; 5861 u8 uid[0x10]; 5862 5863 u8 reserved_at_20[0x10]; 5864 u8 op_mod[0x10]; 5865 5866 u8 reserved_at_40[0x8]; 5867 u8 cqn[0x18]; 5868 5869 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select; 5870 5871 struct mlx5_ifc_cqc_bits cq_context; 5872 5873 u8 reserved_at_280[0x40]; 5874 5875 u8 cq_umem_valid[0x1]; 5876 u8 reserved_at_2c1[0x5bf]; 5877 5878 u8 pas[0][0x40]; 5879 }; 5880 5881 struct mlx5_ifc_modify_cong_status_out_bits { 5882 u8 status[0x8]; 5883 u8 reserved_at_8[0x18]; 5884 5885 u8 syndrome[0x20]; 5886 5887 u8 reserved_at_40[0x40]; 5888 }; 5889 5890 struct mlx5_ifc_modify_cong_status_in_bits { 5891 u8 opcode[0x10]; 5892 u8 reserved_at_10[0x10]; 5893 5894 u8 reserved_at_20[0x10]; 5895 u8 op_mod[0x10]; 5896 5897 u8 reserved_at_40[0x18]; 5898 u8 priority[0x4]; 5899 u8 cong_protocol[0x4]; 5900 5901 u8 enable[0x1]; 5902 u8 tag_enable[0x1]; 5903 u8 reserved_at_62[0x1e]; 5904 }; 5905 5906 struct mlx5_ifc_modify_cong_params_out_bits { 5907 u8 status[0x8]; 5908 u8 reserved_at_8[0x18]; 5909 5910 u8 syndrome[0x20]; 5911 5912 u8 reserved_at_40[0x40]; 5913 }; 5914 5915 struct mlx5_ifc_modify_cong_params_in_bits { 5916 u8 opcode[0x10]; 5917 u8 reserved_at_10[0x10]; 5918 5919 u8 reserved_at_20[0x10]; 5920 u8 op_mod[0x10]; 5921 5922 u8 reserved_at_40[0x1c]; 5923 u8 cong_protocol[0x4]; 5924 5925 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select; 5926 5927 u8 reserved_at_80[0x80]; 5928 5929 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 5930 }; 5931 5932 struct mlx5_ifc_manage_pages_out_bits { 5933 u8 status[0x8]; 5934 u8 reserved_at_8[0x18]; 5935 5936 u8 syndrome[0x20]; 5937 5938 u8 output_num_entries[0x20]; 5939 5940 u8 reserved_at_60[0x20]; 5941 5942 u8 pas[0][0x40]; 5943 }; 5944 5945 enum { 5946 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL = 0x0, 5947 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS = 0x1, 5948 MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES = 0x2, 5949 }; 5950 5951 struct mlx5_ifc_manage_pages_in_bits { 5952 u8 opcode[0x10]; 5953 u8 reserved_at_10[0x10]; 5954 5955 u8 reserved_at_20[0x10]; 5956 u8 op_mod[0x10]; 5957 5958 u8 embedded_cpu_function[0x1]; 5959 u8 reserved_at_41[0xf]; 5960 u8 function_id[0x10]; 5961 5962 u8 input_num_entries[0x20]; 5963 5964 u8 pas[0][0x40]; 5965 }; 5966 5967 struct mlx5_ifc_mad_ifc_out_bits { 5968 u8 status[0x8]; 5969 u8 reserved_at_8[0x18]; 5970 5971 u8 syndrome[0x20]; 5972 5973 u8 reserved_at_40[0x40]; 5974 5975 u8 response_mad_packet[256][0x8]; 5976 }; 5977 5978 struct mlx5_ifc_mad_ifc_in_bits { 5979 u8 opcode[0x10]; 5980 u8 reserved_at_10[0x10]; 5981 5982 u8 reserved_at_20[0x10]; 5983 u8 op_mod[0x10]; 5984 5985 u8 remote_lid[0x10]; 5986 u8 reserved_at_50[0x8]; 5987 u8 port[0x8]; 5988 5989 u8 reserved_at_60[0x20]; 5990 5991 u8 mad[256][0x8]; 5992 }; 5993 5994 struct mlx5_ifc_init_hca_out_bits { 5995 u8 status[0x8]; 5996 u8 reserved_at_8[0x18]; 5997 5998 u8 syndrome[0x20]; 5999 6000 u8 reserved_at_40[0x40]; 6001 }; 6002 6003 struct mlx5_ifc_init_hca_in_bits { 6004 u8 opcode[0x10]; 6005 u8 reserved_at_10[0x10]; 6006 6007 u8 reserved_at_20[0x10]; 6008 u8 op_mod[0x10]; 6009 6010 u8 reserved_at_40[0x40]; 6011 u8 sw_owner_id[4][0x20]; 6012 }; 6013 6014 struct mlx5_ifc_init2rtr_qp_out_bits { 6015 u8 status[0x8]; 6016 u8 reserved_at_8[0x18]; 6017 6018 u8 syndrome[0x20]; 6019 6020 u8 reserved_at_40[0x40]; 6021 }; 6022 6023 struct mlx5_ifc_init2rtr_qp_in_bits { 6024 u8 opcode[0x10]; 6025 u8 uid[0x10]; 6026 6027 u8 reserved_at_20[0x10]; 6028 u8 op_mod[0x10]; 6029 6030 u8 reserved_at_40[0x8]; 6031 u8 qpn[0x18]; 6032 6033 u8 reserved_at_60[0x20]; 6034 6035 u8 opt_param_mask[0x20]; 6036 6037 u8 reserved_at_a0[0x20]; 6038 6039 struct mlx5_ifc_qpc_bits qpc; 6040 6041 u8 reserved_at_800[0x80]; 6042 }; 6043 6044 struct mlx5_ifc_init2init_qp_out_bits { 6045 u8 status[0x8]; 6046 u8 reserved_at_8[0x18]; 6047 6048 u8 syndrome[0x20]; 6049 6050 u8 reserved_at_40[0x40]; 6051 }; 6052 6053 struct mlx5_ifc_init2init_qp_in_bits { 6054 u8 opcode[0x10]; 6055 u8 uid[0x10]; 6056 6057 u8 reserved_at_20[0x10]; 6058 u8 op_mod[0x10]; 6059 6060 u8 reserved_at_40[0x8]; 6061 u8 qpn[0x18]; 6062 6063 u8 reserved_at_60[0x20]; 6064 6065 u8 opt_param_mask[0x20]; 6066 6067 u8 reserved_at_a0[0x20]; 6068 6069 struct mlx5_ifc_qpc_bits qpc; 6070 6071 u8 reserved_at_800[0x80]; 6072 }; 6073 6074 struct mlx5_ifc_get_dropped_packet_log_out_bits { 6075 u8 status[0x8]; 6076 u8 reserved_at_8[0x18]; 6077 6078 u8 syndrome[0x20]; 6079 6080 u8 reserved_at_40[0x40]; 6081 6082 u8 packet_headers_log[128][0x8]; 6083 6084 u8 packet_syndrome[64][0x8]; 6085 }; 6086 6087 struct mlx5_ifc_get_dropped_packet_log_in_bits { 6088 u8 opcode[0x10]; 6089 u8 reserved_at_10[0x10]; 6090 6091 u8 reserved_at_20[0x10]; 6092 u8 op_mod[0x10]; 6093 6094 u8 reserved_at_40[0x40]; 6095 }; 6096 6097 struct mlx5_ifc_gen_eqe_in_bits { 6098 u8 opcode[0x10]; 6099 u8 reserved_at_10[0x10]; 6100 6101 u8 reserved_at_20[0x10]; 6102 u8 op_mod[0x10]; 6103 6104 u8 reserved_at_40[0x18]; 6105 u8 eq_number[0x8]; 6106 6107 u8 reserved_at_60[0x20]; 6108 6109 u8 eqe[64][0x8]; 6110 }; 6111 6112 struct mlx5_ifc_gen_eq_out_bits { 6113 u8 status[0x8]; 6114 u8 reserved_at_8[0x18]; 6115 6116 u8 syndrome[0x20]; 6117 6118 u8 reserved_at_40[0x40]; 6119 }; 6120 6121 struct mlx5_ifc_enable_hca_out_bits { 6122 u8 status[0x8]; 6123 u8 reserved_at_8[0x18]; 6124 6125 u8 syndrome[0x20]; 6126 6127 u8 reserved_at_40[0x20]; 6128 }; 6129 6130 struct mlx5_ifc_enable_hca_in_bits { 6131 u8 opcode[0x10]; 6132 u8 reserved_at_10[0x10]; 6133 6134 u8 reserved_at_20[0x10]; 6135 u8 op_mod[0x10]; 6136 6137 u8 embedded_cpu_function[0x1]; 6138 u8 reserved_at_41[0xf]; 6139 u8 function_id[0x10]; 6140 6141 u8 reserved_at_60[0x20]; 6142 }; 6143 6144 struct mlx5_ifc_drain_dct_out_bits { 6145 u8 status[0x8]; 6146 u8 reserved_at_8[0x18]; 6147 6148 u8 syndrome[0x20]; 6149 6150 u8 reserved_at_40[0x40]; 6151 }; 6152 6153 struct mlx5_ifc_drain_dct_in_bits { 6154 u8 opcode[0x10]; 6155 u8 uid[0x10]; 6156 6157 u8 reserved_at_20[0x10]; 6158 u8 op_mod[0x10]; 6159 6160 u8 reserved_at_40[0x8]; 6161 u8 dctn[0x18]; 6162 6163 u8 reserved_at_60[0x20]; 6164 }; 6165 6166 struct mlx5_ifc_disable_hca_out_bits { 6167 u8 status[0x8]; 6168 u8 reserved_at_8[0x18]; 6169 6170 u8 syndrome[0x20]; 6171 6172 u8 reserved_at_40[0x20]; 6173 }; 6174 6175 struct mlx5_ifc_disable_hca_in_bits { 6176 u8 opcode[0x10]; 6177 u8 reserved_at_10[0x10]; 6178 6179 u8 reserved_at_20[0x10]; 6180 u8 op_mod[0x10]; 6181 6182 u8 embedded_cpu_function[0x1]; 6183 u8 reserved_at_41[0xf]; 6184 u8 function_id[0x10]; 6185 6186 u8 reserved_at_60[0x20]; 6187 }; 6188 6189 struct mlx5_ifc_detach_from_mcg_out_bits { 6190 u8 status[0x8]; 6191 u8 reserved_at_8[0x18]; 6192 6193 u8 syndrome[0x20]; 6194 6195 u8 reserved_at_40[0x40]; 6196 }; 6197 6198 struct mlx5_ifc_detach_from_mcg_in_bits { 6199 u8 opcode[0x10]; 6200 u8 uid[0x10]; 6201 6202 u8 reserved_at_20[0x10]; 6203 u8 op_mod[0x10]; 6204 6205 u8 reserved_at_40[0x8]; 6206 u8 qpn[0x18]; 6207 6208 u8 reserved_at_60[0x20]; 6209 6210 u8 multicast_gid[16][0x8]; 6211 }; 6212 6213 struct mlx5_ifc_destroy_xrq_out_bits { 6214 u8 status[0x8]; 6215 u8 reserved_at_8[0x18]; 6216 6217 u8 syndrome[0x20]; 6218 6219 u8 reserved_at_40[0x40]; 6220 }; 6221 6222 struct mlx5_ifc_destroy_xrq_in_bits { 6223 u8 opcode[0x10]; 6224 u8 uid[0x10]; 6225 6226 u8 reserved_at_20[0x10]; 6227 u8 op_mod[0x10]; 6228 6229 u8 reserved_at_40[0x8]; 6230 u8 xrqn[0x18]; 6231 6232 u8 reserved_at_60[0x20]; 6233 }; 6234 6235 struct mlx5_ifc_destroy_xrc_srq_out_bits { 6236 u8 status[0x8]; 6237 u8 reserved_at_8[0x18]; 6238 6239 u8 syndrome[0x20]; 6240 6241 u8 reserved_at_40[0x40]; 6242 }; 6243 6244 struct mlx5_ifc_destroy_xrc_srq_in_bits { 6245 u8 opcode[0x10]; 6246 u8 uid[0x10]; 6247 6248 u8 reserved_at_20[0x10]; 6249 u8 op_mod[0x10]; 6250 6251 u8 reserved_at_40[0x8]; 6252 u8 xrc_srqn[0x18]; 6253 6254 u8 reserved_at_60[0x20]; 6255 }; 6256 6257 struct mlx5_ifc_destroy_tis_out_bits { 6258 u8 status[0x8]; 6259 u8 reserved_at_8[0x18]; 6260 6261 u8 syndrome[0x20]; 6262 6263 u8 reserved_at_40[0x40]; 6264 }; 6265 6266 struct mlx5_ifc_destroy_tis_in_bits { 6267 u8 opcode[0x10]; 6268 u8 uid[0x10]; 6269 6270 u8 reserved_at_20[0x10]; 6271 u8 op_mod[0x10]; 6272 6273 u8 reserved_at_40[0x8]; 6274 u8 tisn[0x18]; 6275 6276 u8 reserved_at_60[0x20]; 6277 }; 6278 6279 struct mlx5_ifc_destroy_tir_out_bits { 6280 u8 status[0x8]; 6281 u8 reserved_at_8[0x18]; 6282 6283 u8 syndrome[0x20]; 6284 6285 u8 reserved_at_40[0x40]; 6286 }; 6287 6288 struct mlx5_ifc_destroy_tir_in_bits { 6289 u8 opcode[0x10]; 6290 u8 uid[0x10]; 6291 6292 u8 reserved_at_20[0x10]; 6293 u8 op_mod[0x10]; 6294 6295 u8 reserved_at_40[0x8]; 6296 u8 tirn[0x18]; 6297 6298 u8 reserved_at_60[0x20]; 6299 }; 6300 6301 struct mlx5_ifc_destroy_srq_out_bits { 6302 u8 status[0x8]; 6303 u8 reserved_at_8[0x18]; 6304 6305 u8 syndrome[0x20]; 6306 6307 u8 reserved_at_40[0x40]; 6308 }; 6309 6310 struct mlx5_ifc_destroy_srq_in_bits { 6311 u8 opcode[0x10]; 6312 u8 uid[0x10]; 6313 6314 u8 reserved_at_20[0x10]; 6315 u8 op_mod[0x10]; 6316 6317 u8 reserved_at_40[0x8]; 6318 u8 srqn[0x18]; 6319 6320 u8 reserved_at_60[0x20]; 6321 }; 6322 6323 struct mlx5_ifc_destroy_sq_out_bits { 6324 u8 status[0x8]; 6325 u8 reserved_at_8[0x18]; 6326 6327 u8 syndrome[0x20]; 6328 6329 u8 reserved_at_40[0x40]; 6330 }; 6331 6332 struct mlx5_ifc_destroy_sq_in_bits { 6333 u8 opcode[0x10]; 6334 u8 uid[0x10]; 6335 6336 u8 reserved_at_20[0x10]; 6337 u8 op_mod[0x10]; 6338 6339 u8 reserved_at_40[0x8]; 6340 u8 sqn[0x18]; 6341 6342 u8 reserved_at_60[0x20]; 6343 }; 6344 6345 struct mlx5_ifc_destroy_scheduling_element_out_bits { 6346 u8 status[0x8]; 6347 u8 reserved_at_8[0x18]; 6348 6349 u8 syndrome[0x20]; 6350 6351 u8 reserved_at_40[0x1c0]; 6352 }; 6353 6354 struct mlx5_ifc_destroy_scheduling_element_in_bits { 6355 u8 opcode[0x10]; 6356 u8 reserved_at_10[0x10]; 6357 6358 u8 reserved_at_20[0x10]; 6359 u8 op_mod[0x10]; 6360 6361 u8 scheduling_hierarchy[0x8]; 6362 u8 reserved_at_48[0x18]; 6363 6364 u8 scheduling_element_id[0x20]; 6365 6366 u8 reserved_at_80[0x180]; 6367 }; 6368 6369 struct mlx5_ifc_destroy_rqt_out_bits { 6370 u8 status[0x8]; 6371 u8 reserved_at_8[0x18]; 6372 6373 u8 syndrome[0x20]; 6374 6375 u8 reserved_at_40[0x40]; 6376 }; 6377 6378 struct mlx5_ifc_destroy_rqt_in_bits { 6379 u8 opcode[0x10]; 6380 u8 uid[0x10]; 6381 6382 u8 reserved_at_20[0x10]; 6383 u8 op_mod[0x10]; 6384 6385 u8 reserved_at_40[0x8]; 6386 u8 rqtn[0x18]; 6387 6388 u8 reserved_at_60[0x20]; 6389 }; 6390 6391 struct mlx5_ifc_destroy_rq_out_bits { 6392 u8 status[0x8]; 6393 u8 reserved_at_8[0x18]; 6394 6395 u8 syndrome[0x20]; 6396 6397 u8 reserved_at_40[0x40]; 6398 }; 6399 6400 struct mlx5_ifc_destroy_rq_in_bits { 6401 u8 opcode[0x10]; 6402 u8 uid[0x10]; 6403 6404 u8 reserved_at_20[0x10]; 6405 u8 op_mod[0x10]; 6406 6407 u8 reserved_at_40[0x8]; 6408 u8 rqn[0x18]; 6409 6410 u8 reserved_at_60[0x20]; 6411 }; 6412 6413 struct mlx5_ifc_set_delay_drop_params_in_bits { 6414 u8 opcode[0x10]; 6415 u8 reserved_at_10[0x10]; 6416 6417 u8 reserved_at_20[0x10]; 6418 u8 op_mod[0x10]; 6419 6420 u8 reserved_at_40[0x20]; 6421 6422 u8 reserved_at_60[0x10]; 6423 u8 delay_drop_timeout[0x10]; 6424 }; 6425 6426 struct mlx5_ifc_set_delay_drop_params_out_bits { 6427 u8 status[0x8]; 6428 u8 reserved_at_8[0x18]; 6429 6430 u8 syndrome[0x20]; 6431 6432 u8 reserved_at_40[0x40]; 6433 }; 6434 6435 struct mlx5_ifc_destroy_rmp_out_bits { 6436 u8 status[0x8]; 6437 u8 reserved_at_8[0x18]; 6438 6439 u8 syndrome[0x20]; 6440 6441 u8 reserved_at_40[0x40]; 6442 }; 6443 6444 struct mlx5_ifc_destroy_rmp_in_bits { 6445 u8 opcode[0x10]; 6446 u8 uid[0x10]; 6447 6448 u8 reserved_at_20[0x10]; 6449 u8 op_mod[0x10]; 6450 6451 u8 reserved_at_40[0x8]; 6452 u8 rmpn[0x18]; 6453 6454 u8 reserved_at_60[0x20]; 6455 }; 6456 6457 struct mlx5_ifc_destroy_qp_out_bits { 6458 u8 status[0x8]; 6459 u8 reserved_at_8[0x18]; 6460 6461 u8 syndrome[0x20]; 6462 6463 u8 reserved_at_40[0x40]; 6464 }; 6465 6466 struct mlx5_ifc_destroy_qp_in_bits { 6467 u8 opcode[0x10]; 6468 u8 uid[0x10]; 6469 6470 u8 reserved_at_20[0x10]; 6471 u8 op_mod[0x10]; 6472 6473 u8 reserved_at_40[0x8]; 6474 u8 qpn[0x18]; 6475 6476 u8 reserved_at_60[0x20]; 6477 }; 6478 6479 struct mlx5_ifc_destroy_psv_out_bits { 6480 u8 status[0x8]; 6481 u8 reserved_at_8[0x18]; 6482 6483 u8 syndrome[0x20]; 6484 6485 u8 reserved_at_40[0x40]; 6486 }; 6487 6488 struct mlx5_ifc_destroy_psv_in_bits { 6489 u8 opcode[0x10]; 6490 u8 reserved_at_10[0x10]; 6491 6492 u8 reserved_at_20[0x10]; 6493 u8 op_mod[0x10]; 6494 6495 u8 reserved_at_40[0x8]; 6496 u8 psvn[0x18]; 6497 6498 u8 reserved_at_60[0x20]; 6499 }; 6500 6501 struct mlx5_ifc_destroy_mkey_out_bits { 6502 u8 status[0x8]; 6503 u8 reserved_at_8[0x18]; 6504 6505 u8 syndrome[0x20]; 6506 6507 u8 reserved_at_40[0x40]; 6508 }; 6509 6510 struct mlx5_ifc_destroy_mkey_in_bits { 6511 u8 opcode[0x10]; 6512 u8 reserved_at_10[0x10]; 6513 6514 u8 reserved_at_20[0x10]; 6515 u8 op_mod[0x10]; 6516 6517 u8 reserved_at_40[0x8]; 6518 u8 mkey_index[0x18]; 6519 6520 u8 reserved_at_60[0x20]; 6521 }; 6522 6523 struct mlx5_ifc_destroy_flow_table_out_bits { 6524 u8 status[0x8]; 6525 u8 reserved_at_8[0x18]; 6526 6527 u8 syndrome[0x20]; 6528 6529 u8 reserved_at_40[0x40]; 6530 }; 6531 6532 struct mlx5_ifc_destroy_flow_table_in_bits { 6533 u8 opcode[0x10]; 6534 u8 reserved_at_10[0x10]; 6535 6536 u8 reserved_at_20[0x10]; 6537 u8 op_mod[0x10]; 6538 6539 u8 other_vport[0x1]; 6540 u8 reserved_at_41[0xf]; 6541 u8 vport_number[0x10]; 6542 6543 u8 reserved_at_60[0x20]; 6544 6545 u8 table_type[0x8]; 6546 u8 reserved_at_88[0x18]; 6547 6548 u8 reserved_at_a0[0x8]; 6549 u8 table_id[0x18]; 6550 6551 u8 reserved_at_c0[0x140]; 6552 }; 6553 6554 struct mlx5_ifc_destroy_flow_group_out_bits { 6555 u8 status[0x8]; 6556 u8 reserved_at_8[0x18]; 6557 6558 u8 syndrome[0x20]; 6559 6560 u8 reserved_at_40[0x40]; 6561 }; 6562 6563 struct mlx5_ifc_destroy_flow_group_in_bits { 6564 u8 opcode[0x10]; 6565 u8 reserved_at_10[0x10]; 6566 6567 u8 reserved_at_20[0x10]; 6568 u8 op_mod[0x10]; 6569 6570 u8 other_vport[0x1]; 6571 u8 reserved_at_41[0xf]; 6572 u8 vport_number[0x10]; 6573 6574 u8 reserved_at_60[0x20]; 6575 6576 u8 table_type[0x8]; 6577 u8 reserved_at_88[0x18]; 6578 6579 u8 reserved_at_a0[0x8]; 6580 u8 table_id[0x18]; 6581 6582 u8 group_id[0x20]; 6583 6584 u8 reserved_at_e0[0x120]; 6585 }; 6586 6587 struct mlx5_ifc_destroy_eq_out_bits { 6588 u8 status[0x8]; 6589 u8 reserved_at_8[0x18]; 6590 6591 u8 syndrome[0x20]; 6592 6593 u8 reserved_at_40[0x40]; 6594 }; 6595 6596 struct mlx5_ifc_destroy_eq_in_bits { 6597 u8 opcode[0x10]; 6598 u8 reserved_at_10[0x10]; 6599 6600 u8 reserved_at_20[0x10]; 6601 u8 op_mod[0x10]; 6602 6603 u8 reserved_at_40[0x18]; 6604 u8 eq_number[0x8]; 6605 6606 u8 reserved_at_60[0x20]; 6607 }; 6608 6609 struct mlx5_ifc_destroy_dct_out_bits { 6610 u8 status[0x8]; 6611 u8 reserved_at_8[0x18]; 6612 6613 u8 syndrome[0x20]; 6614 6615 u8 reserved_at_40[0x40]; 6616 }; 6617 6618 struct mlx5_ifc_destroy_dct_in_bits { 6619 u8 opcode[0x10]; 6620 u8 uid[0x10]; 6621 6622 u8 reserved_at_20[0x10]; 6623 u8 op_mod[0x10]; 6624 6625 u8 reserved_at_40[0x8]; 6626 u8 dctn[0x18]; 6627 6628 u8 reserved_at_60[0x20]; 6629 }; 6630 6631 struct mlx5_ifc_destroy_cq_out_bits { 6632 u8 status[0x8]; 6633 u8 reserved_at_8[0x18]; 6634 6635 u8 syndrome[0x20]; 6636 6637 u8 reserved_at_40[0x40]; 6638 }; 6639 6640 struct mlx5_ifc_destroy_cq_in_bits { 6641 u8 opcode[0x10]; 6642 u8 uid[0x10]; 6643 6644 u8 reserved_at_20[0x10]; 6645 u8 op_mod[0x10]; 6646 6647 u8 reserved_at_40[0x8]; 6648 u8 cqn[0x18]; 6649 6650 u8 reserved_at_60[0x20]; 6651 }; 6652 6653 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits { 6654 u8 status[0x8]; 6655 u8 reserved_at_8[0x18]; 6656 6657 u8 syndrome[0x20]; 6658 6659 u8 reserved_at_40[0x40]; 6660 }; 6661 6662 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits { 6663 u8 opcode[0x10]; 6664 u8 reserved_at_10[0x10]; 6665 6666 u8 reserved_at_20[0x10]; 6667 u8 op_mod[0x10]; 6668 6669 u8 reserved_at_40[0x20]; 6670 6671 u8 reserved_at_60[0x10]; 6672 u8 vxlan_udp_port[0x10]; 6673 }; 6674 6675 struct mlx5_ifc_delete_l2_table_entry_out_bits { 6676 u8 status[0x8]; 6677 u8 reserved_at_8[0x18]; 6678 6679 u8 syndrome[0x20]; 6680 6681 u8 reserved_at_40[0x40]; 6682 }; 6683 6684 struct mlx5_ifc_delete_l2_table_entry_in_bits { 6685 u8 opcode[0x10]; 6686 u8 reserved_at_10[0x10]; 6687 6688 u8 reserved_at_20[0x10]; 6689 u8 op_mod[0x10]; 6690 6691 u8 reserved_at_40[0x60]; 6692 6693 u8 reserved_at_a0[0x8]; 6694 u8 table_index[0x18]; 6695 6696 u8 reserved_at_c0[0x140]; 6697 }; 6698 6699 struct mlx5_ifc_delete_fte_out_bits { 6700 u8 status[0x8]; 6701 u8 reserved_at_8[0x18]; 6702 6703 u8 syndrome[0x20]; 6704 6705 u8 reserved_at_40[0x40]; 6706 }; 6707 6708 struct mlx5_ifc_delete_fte_in_bits { 6709 u8 opcode[0x10]; 6710 u8 reserved_at_10[0x10]; 6711 6712 u8 reserved_at_20[0x10]; 6713 u8 op_mod[0x10]; 6714 6715 u8 other_vport[0x1]; 6716 u8 reserved_at_41[0xf]; 6717 u8 vport_number[0x10]; 6718 6719 u8 reserved_at_60[0x20]; 6720 6721 u8 table_type[0x8]; 6722 u8 reserved_at_88[0x18]; 6723 6724 u8 reserved_at_a0[0x8]; 6725 u8 table_id[0x18]; 6726 6727 u8 reserved_at_c0[0x40]; 6728 6729 u8 flow_index[0x20]; 6730 6731 u8 reserved_at_120[0xe0]; 6732 }; 6733 6734 struct mlx5_ifc_dealloc_xrcd_out_bits { 6735 u8 status[0x8]; 6736 u8 reserved_at_8[0x18]; 6737 6738 u8 syndrome[0x20]; 6739 6740 u8 reserved_at_40[0x40]; 6741 }; 6742 6743 struct mlx5_ifc_dealloc_xrcd_in_bits { 6744 u8 opcode[0x10]; 6745 u8 uid[0x10]; 6746 6747 u8 reserved_at_20[0x10]; 6748 u8 op_mod[0x10]; 6749 6750 u8 reserved_at_40[0x8]; 6751 u8 xrcd[0x18]; 6752 6753 u8 reserved_at_60[0x20]; 6754 }; 6755 6756 struct mlx5_ifc_dealloc_uar_out_bits { 6757 u8 status[0x8]; 6758 u8 reserved_at_8[0x18]; 6759 6760 u8 syndrome[0x20]; 6761 6762 u8 reserved_at_40[0x40]; 6763 }; 6764 6765 struct mlx5_ifc_dealloc_uar_in_bits { 6766 u8 opcode[0x10]; 6767 u8 reserved_at_10[0x10]; 6768 6769 u8 reserved_at_20[0x10]; 6770 u8 op_mod[0x10]; 6771 6772 u8 reserved_at_40[0x8]; 6773 u8 uar[0x18]; 6774 6775 u8 reserved_at_60[0x20]; 6776 }; 6777 6778 struct mlx5_ifc_dealloc_transport_domain_out_bits { 6779 u8 status[0x8]; 6780 u8 reserved_at_8[0x18]; 6781 6782 u8 syndrome[0x20]; 6783 6784 u8 reserved_at_40[0x40]; 6785 }; 6786 6787 struct mlx5_ifc_dealloc_transport_domain_in_bits { 6788 u8 opcode[0x10]; 6789 u8 uid[0x10]; 6790 6791 u8 reserved_at_20[0x10]; 6792 u8 op_mod[0x10]; 6793 6794 u8 reserved_at_40[0x8]; 6795 u8 transport_domain[0x18]; 6796 6797 u8 reserved_at_60[0x20]; 6798 }; 6799 6800 struct mlx5_ifc_dealloc_q_counter_out_bits { 6801 u8 status[0x8]; 6802 u8 reserved_at_8[0x18]; 6803 6804 u8 syndrome[0x20]; 6805 6806 u8 reserved_at_40[0x40]; 6807 }; 6808 6809 struct mlx5_ifc_dealloc_q_counter_in_bits { 6810 u8 opcode[0x10]; 6811 u8 reserved_at_10[0x10]; 6812 6813 u8 reserved_at_20[0x10]; 6814 u8 op_mod[0x10]; 6815 6816 u8 reserved_at_40[0x18]; 6817 u8 counter_set_id[0x8]; 6818 6819 u8 reserved_at_60[0x20]; 6820 }; 6821 6822 struct mlx5_ifc_dealloc_pd_out_bits { 6823 u8 status[0x8]; 6824 u8 reserved_at_8[0x18]; 6825 6826 u8 syndrome[0x20]; 6827 6828 u8 reserved_at_40[0x40]; 6829 }; 6830 6831 struct mlx5_ifc_dealloc_pd_in_bits { 6832 u8 opcode[0x10]; 6833 u8 uid[0x10]; 6834 6835 u8 reserved_at_20[0x10]; 6836 u8 op_mod[0x10]; 6837 6838 u8 reserved_at_40[0x8]; 6839 u8 pd[0x18]; 6840 6841 u8 reserved_at_60[0x20]; 6842 }; 6843 6844 struct mlx5_ifc_dealloc_flow_counter_out_bits { 6845 u8 status[0x8]; 6846 u8 reserved_at_8[0x18]; 6847 6848 u8 syndrome[0x20]; 6849 6850 u8 reserved_at_40[0x40]; 6851 }; 6852 6853 struct mlx5_ifc_dealloc_flow_counter_in_bits { 6854 u8 opcode[0x10]; 6855 u8 reserved_at_10[0x10]; 6856 6857 u8 reserved_at_20[0x10]; 6858 u8 op_mod[0x10]; 6859 6860 u8 flow_counter_id[0x20]; 6861 6862 u8 reserved_at_60[0x20]; 6863 }; 6864 6865 struct mlx5_ifc_create_xrq_out_bits { 6866 u8 status[0x8]; 6867 u8 reserved_at_8[0x18]; 6868 6869 u8 syndrome[0x20]; 6870 6871 u8 reserved_at_40[0x8]; 6872 u8 xrqn[0x18]; 6873 6874 u8 reserved_at_60[0x20]; 6875 }; 6876 6877 struct mlx5_ifc_create_xrq_in_bits { 6878 u8 opcode[0x10]; 6879 u8 uid[0x10]; 6880 6881 u8 reserved_at_20[0x10]; 6882 u8 op_mod[0x10]; 6883 6884 u8 reserved_at_40[0x40]; 6885 6886 struct mlx5_ifc_xrqc_bits xrq_context; 6887 }; 6888 6889 struct mlx5_ifc_create_xrc_srq_out_bits { 6890 u8 status[0x8]; 6891 u8 reserved_at_8[0x18]; 6892 6893 u8 syndrome[0x20]; 6894 6895 u8 reserved_at_40[0x8]; 6896 u8 xrc_srqn[0x18]; 6897 6898 u8 reserved_at_60[0x20]; 6899 }; 6900 6901 struct mlx5_ifc_create_xrc_srq_in_bits { 6902 u8 opcode[0x10]; 6903 u8 uid[0x10]; 6904 6905 u8 reserved_at_20[0x10]; 6906 u8 op_mod[0x10]; 6907 6908 u8 reserved_at_40[0x40]; 6909 6910 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 6911 6912 u8 reserved_at_280[0x60]; 6913 6914 u8 xrc_srq_umem_valid[0x1]; 6915 u8 reserved_at_2e1[0x1f]; 6916 6917 u8 reserved_at_300[0x580]; 6918 6919 u8 pas[0][0x40]; 6920 }; 6921 6922 struct mlx5_ifc_create_tis_out_bits { 6923 u8 status[0x8]; 6924 u8 reserved_at_8[0x18]; 6925 6926 u8 syndrome[0x20]; 6927 6928 u8 reserved_at_40[0x8]; 6929 u8 tisn[0x18]; 6930 6931 u8 reserved_at_60[0x20]; 6932 }; 6933 6934 struct mlx5_ifc_create_tis_in_bits { 6935 u8 opcode[0x10]; 6936 u8 uid[0x10]; 6937 6938 u8 reserved_at_20[0x10]; 6939 u8 op_mod[0x10]; 6940 6941 u8 reserved_at_40[0xc0]; 6942 6943 struct mlx5_ifc_tisc_bits ctx; 6944 }; 6945 6946 struct mlx5_ifc_create_tir_out_bits { 6947 u8 status[0x8]; 6948 u8 icm_address_63_40[0x18]; 6949 6950 u8 syndrome[0x20]; 6951 6952 u8 icm_address_39_32[0x8]; 6953 u8 tirn[0x18]; 6954 6955 u8 icm_address_31_0[0x20]; 6956 }; 6957 6958 struct mlx5_ifc_create_tir_in_bits { 6959 u8 opcode[0x10]; 6960 u8 uid[0x10]; 6961 6962 u8 reserved_at_20[0x10]; 6963 u8 op_mod[0x10]; 6964 6965 u8 reserved_at_40[0xc0]; 6966 6967 struct mlx5_ifc_tirc_bits ctx; 6968 }; 6969 6970 struct mlx5_ifc_create_srq_out_bits { 6971 u8 status[0x8]; 6972 u8 reserved_at_8[0x18]; 6973 6974 u8 syndrome[0x20]; 6975 6976 u8 reserved_at_40[0x8]; 6977 u8 srqn[0x18]; 6978 6979 u8 reserved_at_60[0x20]; 6980 }; 6981 6982 struct mlx5_ifc_create_srq_in_bits { 6983 u8 opcode[0x10]; 6984 u8 uid[0x10]; 6985 6986 u8 reserved_at_20[0x10]; 6987 u8 op_mod[0x10]; 6988 6989 u8 reserved_at_40[0x40]; 6990 6991 struct mlx5_ifc_srqc_bits srq_context_entry; 6992 6993 u8 reserved_at_280[0x600]; 6994 6995 u8 pas[0][0x40]; 6996 }; 6997 6998 struct mlx5_ifc_create_sq_out_bits { 6999 u8 status[0x8]; 7000 u8 reserved_at_8[0x18]; 7001 7002 u8 syndrome[0x20]; 7003 7004 u8 reserved_at_40[0x8]; 7005 u8 sqn[0x18]; 7006 7007 u8 reserved_at_60[0x20]; 7008 }; 7009 7010 struct mlx5_ifc_create_sq_in_bits { 7011 u8 opcode[0x10]; 7012 u8 uid[0x10]; 7013 7014 u8 reserved_at_20[0x10]; 7015 u8 op_mod[0x10]; 7016 7017 u8 reserved_at_40[0xc0]; 7018 7019 struct mlx5_ifc_sqc_bits ctx; 7020 }; 7021 7022 struct mlx5_ifc_create_scheduling_element_out_bits { 7023 u8 status[0x8]; 7024 u8 reserved_at_8[0x18]; 7025 7026 u8 syndrome[0x20]; 7027 7028 u8 reserved_at_40[0x40]; 7029 7030 u8 scheduling_element_id[0x20]; 7031 7032 u8 reserved_at_a0[0x160]; 7033 }; 7034 7035 struct mlx5_ifc_create_scheduling_element_in_bits { 7036 u8 opcode[0x10]; 7037 u8 reserved_at_10[0x10]; 7038 7039 u8 reserved_at_20[0x10]; 7040 u8 op_mod[0x10]; 7041 7042 u8 scheduling_hierarchy[0x8]; 7043 u8 reserved_at_48[0x18]; 7044 7045 u8 reserved_at_60[0xa0]; 7046 7047 struct mlx5_ifc_scheduling_context_bits scheduling_context; 7048 7049 u8 reserved_at_300[0x100]; 7050 }; 7051 7052 struct mlx5_ifc_create_rqt_out_bits { 7053 u8 status[0x8]; 7054 u8 reserved_at_8[0x18]; 7055 7056 u8 syndrome[0x20]; 7057 7058 u8 reserved_at_40[0x8]; 7059 u8 rqtn[0x18]; 7060 7061 u8 reserved_at_60[0x20]; 7062 }; 7063 7064 struct mlx5_ifc_create_rqt_in_bits { 7065 u8 opcode[0x10]; 7066 u8 uid[0x10]; 7067 7068 u8 reserved_at_20[0x10]; 7069 u8 op_mod[0x10]; 7070 7071 u8 reserved_at_40[0xc0]; 7072 7073 struct mlx5_ifc_rqtc_bits rqt_context; 7074 }; 7075 7076 struct mlx5_ifc_create_rq_out_bits { 7077 u8 status[0x8]; 7078 u8 reserved_at_8[0x18]; 7079 7080 u8 syndrome[0x20]; 7081 7082 u8 reserved_at_40[0x8]; 7083 u8 rqn[0x18]; 7084 7085 u8 reserved_at_60[0x20]; 7086 }; 7087 7088 struct mlx5_ifc_create_rq_in_bits { 7089 u8 opcode[0x10]; 7090 u8 uid[0x10]; 7091 7092 u8 reserved_at_20[0x10]; 7093 u8 op_mod[0x10]; 7094 7095 u8 reserved_at_40[0xc0]; 7096 7097 struct mlx5_ifc_rqc_bits ctx; 7098 }; 7099 7100 struct mlx5_ifc_create_rmp_out_bits { 7101 u8 status[0x8]; 7102 u8 reserved_at_8[0x18]; 7103 7104 u8 syndrome[0x20]; 7105 7106 u8 reserved_at_40[0x8]; 7107 u8 rmpn[0x18]; 7108 7109 u8 reserved_at_60[0x20]; 7110 }; 7111 7112 struct mlx5_ifc_create_rmp_in_bits { 7113 u8 opcode[0x10]; 7114 u8 uid[0x10]; 7115 7116 u8 reserved_at_20[0x10]; 7117 u8 op_mod[0x10]; 7118 7119 u8 reserved_at_40[0xc0]; 7120 7121 struct mlx5_ifc_rmpc_bits ctx; 7122 }; 7123 7124 struct mlx5_ifc_create_qp_out_bits { 7125 u8 status[0x8]; 7126 u8 reserved_at_8[0x18]; 7127 7128 u8 syndrome[0x20]; 7129 7130 u8 reserved_at_40[0x8]; 7131 u8 qpn[0x18]; 7132 7133 u8 reserved_at_60[0x20]; 7134 }; 7135 7136 struct mlx5_ifc_create_qp_in_bits { 7137 u8 opcode[0x10]; 7138 u8 uid[0x10]; 7139 7140 u8 reserved_at_20[0x10]; 7141 u8 op_mod[0x10]; 7142 7143 u8 reserved_at_40[0x40]; 7144 7145 u8 opt_param_mask[0x20]; 7146 7147 u8 reserved_at_a0[0x20]; 7148 7149 struct mlx5_ifc_qpc_bits qpc; 7150 7151 u8 reserved_at_800[0x60]; 7152 7153 u8 wq_umem_valid[0x1]; 7154 u8 reserved_at_861[0x1f]; 7155 7156 u8 pas[0][0x40]; 7157 }; 7158 7159 struct mlx5_ifc_create_psv_out_bits { 7160 u8 status[0x8]; 7161 u8 reserved_at_8[0x18]; 7162 7163 u8 syndrome[0x20]; 7164 7165 u8 reserved_at_40[0x40]; 7166 7167 u8 reserved_at_80[0x8]; 7168 u8 psv0_index[0x18]; 7169 7170 u8 reserved_at_a0[0x8]; 7171 u8 psv1_index[0x18]; 7172 7173 u8 reserved_at_c0[0x8]; 7174 u8 psv2_index[0x18]; 7175 7176 u8 reserved_at_e0[0x8]; 7177 u8 psv3_index[0x18]; 7178 }; 7179 7180 struct mlx5_ifc_create_psv_in_bits { 7181 u8 opcode[0x10]; 7182 u8 reserved_at_10[0x10]; 7183 7184 u8 reserved_at_20[0x10]; 7185 u8 op_mod[0x10]; 7186 7187 u8 num_psv[0x4]; 7188 u8 reserved_at_44[0x4]; 7189 u8 pd[0x18]; 7190 7191 u8 reserved_at_60[0x20]; 7192 }; 7193 7194 struct mlx5_ifc_create_mkey_out_bits { 7195 u8 status[0x8]; 7196 u8 reserved_at_8[0x18]; 7197 7198 u8 syndrome[0x20]; 7199 7200 u8 reserved_at_40[0x8]; 7201 u8 mkey_index[0x18]; 7202 7203 u8 reserved_at_60[0x20]; 7204 }; 7205 7206 struct mlx5_ifc_create_mkey_in_bits { 7207 u8 opcode[0x10]; 7208 u8 reserved_at_10[0x10]; 7209 7210 u8 reserved_at_20[0x10]; 7211 u8 op_mod[0x10]; 7212 7213 u8 reserved_at_40[0x20]; 7214 7215 u8 pg_access[0x1]; 7216 u8 mkey_umem_valid[0x1]; 7217 u8 reserved_at_62[0x1e]; 7218 7219 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 7220 7221 u8 reserved_at_280[0x80]; 7222 7223 u8 translations_octword_actual_size[0x20]; 7224 7225 u8 reserved_at_320[0x560]; 7226 7227 u8 klm_pas_mtt[0][0x20]; 7228 }; 7229 7230 struct mlx5_ifc_create_flow_table_out_bits { 7231 u8 status[0x8]; 7232 u8 reserved_at_8[0x18]; 7233 7234 u8 syndrome[0x20]; 7235 7236 u8 reserved_at_40[0x8]; 7237 u8 table_id[0x18]; 7238 7239 u8 reserved_at_60[0x20]; 7240 }; 7241 7242 struct mlx5_ifc_flow_table_context_bits { 7243 u8 reformat_en[0x1]; 7244 u8 decap_en[0x1]; 7245 u8 reserved_at_2[0x1]; 7246 u8 termination_table[0x1]; 7247 u8 table_miss_action[0x4]; 7248 u8 level[0x8]; 7249 u8 reserved_at_10[0x8]; 7250 u8 log_size[0x8]; 7251 7252 u8 reserved_at_20[0x8]; 7253 u8 table_miss_id[0x18]; 7254 7255 u8 reserved_at_40[0x8]; 7256 u8 lag_master_next_table_id[0x18]; 7257 7258 u8 reserved_at_60[0xe0]; 7259 }; 7260 7261 struct mlx5_ifc_create_flow_table_in_bits { 7262 u8 opcode[0x10]; 7263 u8 reserved_at_10[0x10]; 7264 7265 u8 reserved_at_20[0x10]; 7266 u8 op_mod[0x10]; 7267 7268 u8 other_vport[0x1]; 7269 u8 reserved_at_41[0xf]; 7270 u8 vport_number[0x10]; 7271 7272 u8 reserved_at_60[0x20]; 7273 7274 u8 table_type[0x8]; 7275 u8 reserved_at_88[0x18]; 7276 7277 u8 reserved_at_a0[0x20]; 7278 7279 struct mlx5_ifc_flow_table_context_bits flow_table_context; 7280 }; 7281 7282 struct mlx5_ifc_create_flow_group_out_bits { 7283 u8 status[0x8]; 7284 u8 reserved_at_8[0x18]; 7285 7286 u8 syndrome[0x20]; 7287 7288 u8 reserved_at_40[0x8]; 7289 u8 group_id[0x18]; 7290 7291 u8 reserved_at_60[0x20]; 7292 }; 7293 7294 enum { 7295 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 7296 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 7297 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 7298 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3, 7299 }; 7300 7301 struct mlx5_ifc_create_flow_group_in_bits { 7302 u8 opcode[0x10]; 7303 u8 reserved_at_10[0x10]; 7304 7305 u8 reserved_at_20[0x10]; 7306 u8 op_mod[0x10]; 7307 7308 u8 other_vport[0x1]; 7309 u8 reserved_at_41[0xf]; 7310 u8 vport_number[0x10]; 7311 7312 u8 reserved_at_60[0x20]; 7313 7314 u8 table_type[0x8]; 7315 u8 reserved_at_88[0x18]; 7316 7317 u8 reserved_at_a0[0x8]; 7318 u8 table_id[0x18]; 7319 7320 u8 source_eswitch_owner_vhca_id_valid[0x1]; 7321 7322 u8 reserved_at_c1[0x1f]; 7323 7324 u8 start_flow_index[0x20]; 7325 7326 u8 reserved_at_100[0x20]; 7327 7328 u8 end_flow_index[0x20]; 7329 7330 u8 reserved_at_140[0xa0]; 7331 7332 u8 reserved_at_1e0[0x18]; 7333 u8 match_criteria_enable[0x8]; 7334 7335 struct mlx5_ifc_fte_match_param_bits match_criteria; 7336 7337 u8 reserved_at_1200[0xe00]; 7338 }; 7339 7340 struct mlx5_ifc_create_eq_out_bits { 7341 u8 status[0x8]; 7342 u8 reserved_at_8[0x18]; 7343 7344 u8 syndrome[0x20]; 7345 7346 u8 reserved_at_40[0x18]; 7347 u8 eq_number[0x8]; 7348 7349 u8 reserved_at_60[0x20]; 7350 }; 7351 7352 struct mlx5_ifc_create_eq_in_bits { 7353 u8 opcode[0x10]; 7354 u8 uid[0x10]; 7355 7356 u8 reserved_at_20[0x10]; 7357 u8 op_mod[0x10]; 7358 7359 u8 reserved_at_40[0x40]; 7360 7361 struct mlx5_ifc_eqc_bits eq_context_entry; 7362 7363 u8 reserved_at_280[0x40]; 7364 7365 u8 event_bitmask[0x40]; 7366 7367 u8 reserved_at_300[0x580]; 7368 7369 u8 pas[0][0x40]; 7370 }; 7371 7372 struct mlx5_ifc_create_dct_out_bits { 7373 u8 status[0x8]; 7374 u8 reserved_at_8[0x18]; 7375 7376 u8 syndrome[0x20]; 7377 7378 u8 reserved_at_40[0x8]; 7379 u8 dctn[0x18]; 7380 7381 u8 reserved_at_60[0x20]; 7382 }; 7383 7384 struct mlx5_ifc_create_dct_in_bits { 7385 u8 opcode[0x10]; 7386 u8 uid[0x10]; 7387 7388 u8 reserved_at_20[0x10]; 7389 u8 op_mod[0x10]; 7390 7391 u8 reserved_at_40[0x40]; 7392 7393 struct mlx5_ifc_dctc_bits dct_context_entry; 7394 7395 u8 reserved_at_280[0x180]; 7396 }; 7397 7398 struct mlx5_ifc_create_cq_out_bits { 7399 u8 status[0x8]; 7400 u8 reserved_at_8[0x18]; 7401 7402 u8 syndrome[0x20]; 7403 7404 u8 reserved_at_40[0x8]; 7405 u8 cqn[0x18]; 7406 7407 u8 reserved_at_60[0x20]; 7408 }; 7409 7410 struct mlx5_ifc_create_cq_in_bits { 7411 u8 opcode[0x10]; 7412 u8 uid[0x10]; 7413 7414 u8 reserved_at_20[0x10]; 7415 u8 op_mod[0x10]; 7416 7417 u8 reserved_at_40[0x40]; 7418 7419 struct mlx5_ifc_cqc_bits cq_context; 7420 7421 u8 reserved_at_280[0x60]; 7422 7423 u8 cq_umem_valid[0x1]; 7424 u8 reserved_at_2e1[0x59f]; 7425 7426 u8 pas[0][0x40]; 7427 }; 7428 7429 struct mlx5_ifc_config_int_moderation_out_bits { 7430 u8 status[0x8]; 7431 u8 reserved_at_8[0x18]; 7432 7433 u8 syndrome[0x20]; 7434 7435 u8 reserved_at_40[0x4]; 7436 u8 min_delay[0xc]; 7437 u8 int_vector[0x10]; 7438 7439 u8 reserved_at_60[0x20]; 7440 }; 7441 7442 enum { 7443 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0, 7444 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1, 7445 }; 7446 7447 struct mlx5_ifc_config_int_moderation_in_bits { 7448 u8 opcode[0x10]; 7449 u8 reserved_at_10[0x10]; 7450 7451 u8 reserved_at_20[0x10]; 7452 u8 op_mod[0x10]; 7453 7454 u8 reserved_at_40[0x4]; 7455 u8 min_delay[0xc]; 7456 u8 int_vector[0x10]; 7457 7458 u8 reserved_at_60[0x20]; 7459 }; 7460 7461 struct mlx5_ifc_attach_to_mcg_out_bits { 7462 u8 status[0x8]; 7463 u8 reserved_at_8[0x18]; 7464 7465 u8 syndrome[0x20]; 7466 7467 u8 reserved_at_40[0x40]; 7468 }; 7469 7470 struct mlx5_ifc_attach_to_mcg_in_bits { 7471 u8 opcode[0x10]; 7472 u8 uid[0x10]; 7473 7474 u8 reserved_at_20[0x10]; 7475 u8 op_mod[0x10]; 7476 7477 u8 reserved_at_40[0x8]; 7478 u8 qpn[0x18]; 7479 7480 u8 reserved_at_60[0x20]; 7481 7482 u8 multicast_gid[16][0x8]; 7483 }; 7484 7485 struct mlx5_ifc_arm_xrq_out_bits { 7486 u8 status[0x8]; 7487 u8 reserved_at_8[0x18]; 7488 7489 u8 syndrome[0x20]; 7490 7491 u8 reserved_at_40[0x40]; 7492 }; 7493 7494 struct mlx5_ifc_arm_xrq_in_bits { 7495 u8 opcode[0x10]; 7496 u8 reserved_at_10[0x10]; 7497 7498 u8 reserved_at_20[0x10]; 7499 u8 op_mod[0x10]; 7500 7501 u8 reserved_at_40[0x8]; 7502 u8 xrqn[0x18]; 7503 7504 u8 reserved_at_60[0x10]; 7505 u8 lwm[0x10]; 7506 }; 7507 7508 struct mlx5_ifc_arm_xrc_srq_out_bits { 7509 u8 status[0x8]; 7510 u8 reserved_at_8[0x18]; 7511 7512 u8 syndrome[0x20]; 7513 7514 u8 reserved_at_40[0x40]; 7515 }; 7516 7517 enum { 7518 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1, 7519 }; 7520 7521 struct mlx5_ifc_arm_xrc_srq_in_bits { 7522 u8 opcode[0x10]; 7523 u8 uid[0x10]; 7524 7525 u8 reserved_at_20[0x10]; 7526 u8 op_mod[0x10]; 7527 7528 u8 reserved_at_40[0x8]; 7529 u8 xrc_srqn[0x18]; 7530 7531 u8 reserved_at_60[0x10]; 7532 u8 lwm[0x10]; 7533 }; 7534 7535 struct mlx5_ifc_arm_rq_out_bits { 7536 u8 status[0x8]; 7537 u8 reserved_at_8[0x18]; 7538 7539 u8 syndrome[0x20]; 7540 7541 u8 reserved_at_40[0x40]; 7542 }; 7543 7544 enum { 7545 MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1, 7546 MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2, 7547 }; 7548 7549 struct mlx5_ifc_arm_rq_in_bits { 7550 u8 opcode[0x10]; 7551 u8 uid[0x10]; 7552 7553 u8 reserved_at_20[0x10]; 7554 u8 op_mod[0x10]; 7555 7556 u8 reserved_at_40[0x8]; 7557 u8 srq_number[0x18]; 7558 7559 u8 reserved_at_60[0x10]; 7560 u8 lwm[0x10]; 7561 }; 7562 7563 struct mlx5_ifc_arm_dct_out_bits { 7564 u8 status[0x8]; 7565 u8 reserved_at_8[0x18]; 7566 7567 u8 syndrome[0x20]; 7568 7569 u8 reserved_at_40[0x40]; 7570 }; 7571 7572 struct mlx5_ifc_arm_dct_in_bits { 7573 u8 opcode[0x10]; 7574 u8 reserved_at_10[0x10]; 7575 7576 u8 reserved_at_20[0x10]; 7577 u8 op_mod[0x10]; 7578 7579 u8 reserved_at_40[0x8]; 7580 u8 dct_number[0x18]; 7581 7582 u8 reserved_at_60[0x20]; 7583 }; 7584 7585 struct mlx5_ifc_alloc_xrcd_out_bits { 7586 u8 status[0x8]; 7587 u8 reserved_at_8[0x18]; 7588 7589 u8 syndrome[0x20]; 7590 7591 u8 reserved_at_40[0x8]; 7592 u8 xrcd[0x18]; 7593 7594 u8 reserved_at_60[0x20]; 7595 }; 7596 7597 struct mlx5_ifc_alloc_xrcd_in_bits { 7598 u8 opcode[0x10]; 7599 u8 uid[0x10]; 7600 7601 u8 reserved_at_20[0x10]; 7602 u8 op_mod[0x10]; 7603 7604 u8 reserved_at_40[0x40]; 7605 }; 7606 7607 struct mlx5_ifc_alloc_uar_out_bits { 7608 u8 status[0x8]; 7609 u8 reserved_at_8[0x18]; 7610 7611 u8 syndrome[0x20]; 7612 7613 u8 reserved_at_40[0x8]; 7614 u8 uar[0x18]; 7615 7616 u8 reserved_at_60[0x20]; 7617 }; 7618 7619 struct mlx5_ifc_alloc_uar_in_bits { 7620 u8 opcode[0x10]; 7621 u8 reserved_at_10[0x10]; 7622 7623 u8 reserved_at_20[0x10]; 7624 u8 op_mod[0x10]; 7625 7626 u8 reserved_at_40[0x40]; 7627 }; 7628 7629 struct mlx5_ifc_alloc_transport_domain_out_bits { 7630 u8 status[0x8]; 7631 u8 reserved_at_8[0x18]; 7632 7633 u8 syndrome[0x20]; 7634 7635 u8 reserved_at_40[0x8]; 7636 u8 transport_domain[0x18]; 7637 7638 u8 reserved_at_60[0x20]; 7639 }; 7640 7641 struct mlx5_ifc_alloc_transport_domain_in_bits { 7642 u8 opcode[0x10]; 7643 u8 uid[0x10]; 7644 7645 u8 reserved_at_20[0x10]; 7646 u8 op_mod[0x10]; 7647 7648 u8 reserved_at_40[0x40]; 7649 }; 7650 7651 struct mlx5_ifc_alloc_q_counter_out_bits { 7652 u8 status[0x8]; 7653 u8 reserved_at_8[0x18]; 7654 7655 u8 syndrome[0x20]; 7656 7657 u8 reserved_at_40[0x18]; 7658 u8 counter_set_id[0x8]; 7659 7660 u8 reserved_at_60[0x20]; 7661 }; 7662 7663 struct mlx5_ifc_alloc_q_counter_in_bits { 7664 u8 opcode[0x10]; 7665 u8 uid[0x10]; 7666 7667 u8 reserved_at_20[0x10]; 7668 u8 op_mod[0x10]; 7669 7670 u8 reserved_at_40[0x40]; 7671 }; 7672 7673 struct mlx5_ifc_alloc_pd_out_bits { 7674 u8 status[0x8]; 7675 u8 reserved_at_8[0x18]; 7676 7677 u8 syndrome[0x20]; 7678 7679 u8 reserved_at_40[0x8]; 7680 u8 pd[0x18]; 7681 7682 u8 reserved_at_60[0x20]; 7683 }; 7684 7685 struct mlx5_ifc_alloc_pd_in_bits { 7686 u8 opcode[0x10]; 7687 u8 uid[0x10]; 7688 7689 u8 reserved_at_20[0x10]; 7690 u8 op_mod[0x10]; 7691 7692 u8 reserved_at_40[0x40]; 7693 }; 7694 7695 struct mlx5_ifc_alloc_flow_counter_out_bits { 7696 u8 status[0x8]; 7697 u8 reserved_at_8[0x18]; 7698 7699 u8 syndrome[0x20]; 7700 7701 u8 flow_counter_id[0x20]; 7702 7703 u8 reserved_at_60[0x20]; 7704 }; 7705 7706 struct mlx5_ifc_alloc_flow_counter_in_bits { 7707 u8 opcode[0x10]; 7708 u8 reserved_at_10[0x10]; 7709 7710 u8 reserved_at_20[0x10]; 7711 u8 op_mod[0x10]; 7712 7713 u8 reserved_at_40[0x40]; 7714 }; 7715 7716 struct mlx5_ifc_add_vxlan_udp_dport_out_bits { 7717 u8 status[0x8]; 7718 u8 reserved_at_8[0x18]; 7719 7720 u8 syndrome[0x20]; 7721 7722 u8 reserved_at_40[0x40]; 7723 }; 7724 7725 struct mlx5_ifc_add_vxlan_udp_dport_in_bits { 7726 u8 opcode[0x10]; 7727 u8 reserved_at_10[0x10]; 7728 7729 u8 reserved_at_20[0x10]; 7730 u8 op_mod[0x10]; 7731 7732 u8 reserved_at_40[0x20]; 7733 7734 u8 reserved_at_60[0x10]; 7735 u8 vxlan_udp_port[0x10]; 7736 }; 7737 7738 struct mlx5_ifc_set_pp_rate_limit_out_bits { 7739 u8 status[0x8]; 7740 u8 reserved_at_8[0x18]; 7741 7742 u8 syndrome[0x20]; 7743 7744 u8 reserved_at_40[0x40]; 7745 }; 7746 7747 struct mlx5_ifc_set_pp_rate_limit_in_bits { 7748 u8 opcode[0x10]; 7749 u8 reserved_at_10[0x10]; 7750 7751 u8 reserved_at_20[0x10]; 7752 u8 op_mod[0x10]; 7753 7754 u8 reserved_at_40[0x10]; 7755 u8 rate_limit_index[0x10]; 7756 7757 u8 reserved_at_60[0x20]; 7758 7759 u8 rate_limit[0x20]; 7760 7761 u8 burst_upper_bound[0x20]; 7762 7763 u8 reserved_at_c0[0x10]; 7764 u8 typical_packet_size[0x10]; 7765 7766 u8 reserved_at_e0[0x120]; 7767 }; 7768 7769 struct mlx5_ifc_access_register_out_bits { 7770 u8 status[0x8]; 7771 u8 reserved_at_8[0x18]; 7772 7773 u8 syndrome[0x20]; 7774 7775 u8 reserved_at_40[0x40]; 7776 7777 u8 register_data[0][0x20]; 7778 }; 7779 7780 enum { 7781 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0, 7782 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1, 7783 }; 7784 7785 struct mlx5_ifc_access_register_in_bits { 7786 u8 opcode[0x10]; 7787 u8 reserved_at_10[0x10]; 7788 7789 u8 reserved_at_20[0x10]; 7790 u8 op_mod[0x10]; 7791 7792 u8 reserved_at_40[0x10]; 7793 u8 register_id[0x10]; 7794 7795 u8 argument[0x20]; 7796 7797 u8 register_data[0][0x20]; 7798 }; 7799 7800 struct mlx5_ifc_sltp_reg_bits { 7801 u8 status[0x4]; 7802 u8 version[0x4]; 7803 u8 local_port[0x8]; 7804 u8 pnat[0x2]; 7805 u8 reserved_at_12[0x2]; 7806 u8 lane[0x4]; 7807 u8 reserved_at_18[0x8]; 7808 7809 u8 reserved_at_20[0x20]; 7810 7811 u8 reserved_at_40[0x7]; 7812 u8 polarity[0x1]; 7813 u8 ob_tap0[0x8]; 7814 u8 ob_tap1[0x8]; 7815 u8 ob_tap2[0x8]; 7816 7817 u8 reserved_at_60[0xc]; 7818 u8 ob_preemp_mode[0x4]; 7819 u8 ob_reg[0x8]; 7820 u8 ob_bias[0x8]; 7821 7822 u8 reserved_at_80[0x20]; 7823 }; 7824 7825 struct mlx5_ifc_slrg_reg_bits { 7826 u8 status[0x4]; 7827 u8 version[0x4]; 7828 u8 local_port[0x8]; 7829 u8 pnat[0x2]; 7830 u8 reserved_at_12[0x2]; 7831 u8 lane[0x4]; 7832 u8 reserved_at_18[0x8]; 7833 7834 u8 time_to_link_up[0x10]; 7835 u8 reserved_at_30[0xc]; 7836 u8 grade_lane_speed[0x4]; 7837 7838 u8 grade_version[0x8]; 7839 u8 grade[0x18]; 7840 7841 u8 reserved_at_60[0x4]; 7842 u8 height_grade_type[0x4]; 7843 u8 height_grade[0x18]; 7844 7845 u8 height_dz[0x10]; 7846 u8 height_dv[0x10]; 7847 7848 u8 reserved_at_a0[0x10]; 7849 u8 height_sigma[0x10]; 7850 7851 u8 reserved_at_c0[0x20]; 7852 7853 u8 reserved_at_e0[0x4]; 7854 u8 phase_grade_type[0x4]; 7855 u8 phase_grade[0x18]; 7856 7857 u8 reserved_at_100[0x8]; 7858 u8 phase_eo_pos[0x8]; 7859 u8 reserved_at_110[0x8]; 7860 u8 phase_eo_neg[0x8]; 7861 7862 u8 ffe_set_tested[0x10]; 7863 u8 test_errors_per_lane[0x10]; 7864 }; 7865 7866 struct mlx5_ifc_pvlc_reg_bits { 7867 u8 reserved_at_0[0x8]; 7868 u8 local_port[0x8]; 7869 u8 reserved_at_10[0x10]; 7870 7871 u8 reserved_at_20[0x1c]; 7872 u8 vl_hw_cap[0x4]; 7873 7874 u8 reserved_at_40[0x1c]; 7875 u8 vl_admin[0x4]; 7876 7877 u8 reserved_at_60[0x1c]; 7878 u8 vl_operational[0x4]; 7879 }; 7880 7881 struct mlx5_ifc_pude_reg_bits { 7882 u8 swid[0x8]; 7883 u8 local_port[0x8]; 7884 u8 reserved_at_10[0x4]; 7885 u8 admin_status[0x4]; 7886 u8 reserved_at_18[0x4]; 7887 u8 oper_status[0x4]; 7888 7889 u8 reserved_at_20[0x60]; 7890 }; 7891 7892 struct mlx5_ifc_ptys_reg_bits { 7893 u8 reserved_at_0[0x1]; 7894 u8 an_disable_admin[0x1]; 7895 u8 an_disable_cap[0x1]; 7896 u8 reserved_at_3[0x5]; 7897 u8 local_port[0x8]; 7898 u8 reserved_at_10[0xd]; 7899 u8 proto_mask[0x3]; 7900 7901 u8 an_status[0x4]; 7902 u8 reserved_at_24[0x1c]; 7903 7904 u8 ext_eth_proto_capability[0x20]; 7905 7906 u8 eth_proto_capability[0x20]; 7907 7908 u8 ib_link_width_capability[0x10]; 7909 u8 ib_proto_capability[0x10]; 7910 7911 u8 ext_eth_proto_admin[0x20]; 7912 7913 u8 eth_proto_admin[0x20]; 7914 7915 u8 ib_link_width_admin[0x10]; 7916 u8 ib_proto_admin[0x10]; 7917 7918 u8 ext_eth_proto_oper[0x20]; 7919 7920 u8 eth_proto_oper[0x20]; 7921 7922 u8 ib_link_width_oper[0x10]; 7923 u8 ib_proto_oper[0x10]; 7924 7925 u8 reserved_at_160[0x1c]; 7926 u8 connector_type[0x4]; 7927 7928 u8 eth_proto_lp_advertise[0x20]; 7929 7930 u8 reserved_at_1a0[0x60]; 7931 }; 7932 7933 struct mlx5_ifc_mlcr_reg_bits { 7934 u8 reserved_at_0[0x8]; 7935 u8 local_port[0x8]; 7936 u8 reserved_at_10[0x20]; 7937 7938 u8 beacon_duration[0x10]; 7939 u8 reserved_at_40[0x10]; 7940 7941 u8 beacon_remain[0x10]; 7942 }; 7943 7944 struct mlx5_ifc_ptas_reg_bits { 7945 u8 reserved_at_0[0x20]; 7946 7947 u8 algorithm_options[0x10]; 7948 u8 reserved_at_30[0x4]; 7949 u8 repetitions_mode[0x4]; 7950 u8 num_of_repetitions[0x8]; 7951 7952 u8 grade_version[0x8]; 7953 u8 height_grade_type[0x4]; 7954 u8 phase_grade_type[0x4]; 7955 u8 height_grade_weight[0x8]; 7956 u8 phase_grade_weight[0x8]; 7957 7958 u8 gisim_measure_bits[0x10]; 7959 u8 adaptive_tap_measure_bits[0x10]; 7960 7961 u8 ber_bath_high_error_threshold[0x10]; 7962 u8 ber_bath_mid_error_threshold[0x10]; 7963 7964 u8 ber_bath_low_error_threshold[0x10]; 7965 u8 one_ratio_high_threshold[0x10]; 7966 7967 u8 one_ratio_high_mid_threshold[0x10]; 7968 u8 one_ratio_low_mid_threshold[0x10]; 7969 7970 u8 one_ratio_low_threshold[0x10]; 7971 u8 ndeo_error_threshold[0x10]; 7972 7973 u8 mixer_offset_step_size[0x10]; 7974 u8 reserved_at_110[0x8]; 7975 u8 mix90_phase_for_voltage_bath[0x8]; 7976 7977 u8 mixer_offset_start[0x10]; 7978 u8 mixer_offset_end[0x10]; 7979 7980 u8 reserved_at_140[0x15]; 7981 u8 ber_test_time[0xb]; 7982 }; 7983 7984 struct mlx5_ifc_pspa_reg_bits { 7985 u8 swid[0x8]; 7986 u8 local_port[0x8]; 7987 u8 sub_port[0x8]; 7988 u8 reserved_at_18[0x8]; 7989 7990 u8 reserved_at_20[0x20]; 7991 }; 7992 7993 struct mlx5_ifc_pqdr_reg_bits { 7994 u8 reserved_at_0[0x8]; 7995 u8 local_port[0x8]; 7996 u8 reserved_at_10[0x5]; 7997 u8 prio[0x3]; 7998 u8 reserved_at_18[0x6]; 7999 u8 mode[0x2]; 8000 8001 u8 reserved_at_20[0x20]; 8002 8003 u8 reserved_at_40[0x10]; 8004 u8 min_threshold[0x10]; 8005 8006 u8 reserved_at_60[0x10]; 8007 u8 max_threshold[0x10]; 8008 8009 u8 reserved_at_80[0x10]; 8010 u8 mark_probability_denominator[0x10]; 8011 8012 u8 reserved_at_a0[0x60]; 8013 }; 8014 8015 struct mlx5_ifc_ppsc_reg_bits { 8016 u8 reserved_at_0[0x8]; 8017 u8 local_port[0x8]; 8018 u8 reserved_at_10[0x10]; 8019 8020 u8 reserved_at_20[0x60]; 8021 8022 u8 reserved_at_80[0x1c]; 8023 u8 wrps_admin[0x4]; 8024 8025 u8 reserved_at_a0[0x1c]; 8026 u8 wrps_status[0x4]; 8027 8028 u8 reserved_at_c0[0x8]; 8029 u8 up_threshold[0x8]; 8030 u8 reserved_at_d0[0x8]; 8031 u8 down_threshold[0x8]; 8032 8033 u8 reserved_at_e0[0x20]; 8034 8035 u8 reserved_at_100[0x1c]; 8036 u8 srps_admin[0x4]; 8037 8038 u8 reserved_at_120[0x1c]; 8039 u8 srps_status[0x4]; 8040 8041 u8 reserved_at_140[0x40]; 8042 }; 8043 8044 struct mlx5_ifc_pplr_reg_bits { 8045 u8 reserved_at_0[0x8]; 8046 u8 local_port[0x8]; 8047 u8 reserved_at_10[0x10]; 8048 8049 u8 reserved_at_20[0x8]; 8050 u8 lb_cap[0x8]; 8051 u8 reserved_at_30[0x8]; 8052 u8 lb_en[0x8]; 8053 }; 8054 8055 struct mlx5_ifc_pplm_reg_bits { 8056 u8 reserved_at_0[0x8]; 8057 u8 local_port[0x8]; 8058 u8 reserved_at_10[0x10]; 8059 8060 u8 reserved_at_20[0x20]; 8061 8062 u8 port_profile_mode[0x8]; 8063 u8 static_port_profile[0x8]; 8064 u8 active_port_profile[0x8]; 8065 u8 reserved_at_58[0x8]; 8066 8067 u8 retransmission_active[0x8]; 8068 u8 fec_mode_active[0x18]; 8069 8070 u8 rs_fec_correction_bypass_cap[0x4]; 8071 u8 reserved_at_84[0x8]; 8072 u8 fec_override_cap_56g[0x4]; 8073 u8 fec_override_cap_100g[0x4]; 8074 u8 fec_override_cap_50g[0x4]; 8075 u8 fec_override_cap_25g[0x4]; 8076 u8 fec_override_cap_10g_40g[0x4]; 8077 8078 u8 rs_fec_correction_bypass_admin[0x4]; 8079 u8 reserved_at_a4[0x8]; 8080 u8 fec_override_admin_56g[0x4]; 8081 u8 fec_override_admin_100g[0x4]; 8082 u8 fec_override_admin_50g[0x4]; 8083 u8 fec_override_admin_25g[0x4]; 8084 u8 fec_override_admin_10g_40g[0x4]; 8085 }; 8086 8087 struct mlx5_ifc_ppcnt_reg_bits { 8088 u8 swid[0x8]; 8089 u8 local_port[0x8]; 8090 u8 pnat[0x2]; 8091 u8 reserved_at_12[0x8]; 8092 u8 grp[0x6]; 8093 8094 u8 clr[0x1]; 8095 u8 reserved_at_21[0x1c]; 8096 u8 prio_tc[0x3]; 8097 8098 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set; 8099 }; 8100 8101 struct mlx5_ifc_mpein_reg_bits { 8102 u8 reserved_at_0[0x2]; 8103 u8 depth[0x6]; 8104 u8 pcie_index[0x8]; 8105 u8 node[0x8]; 8106 u8 reserved_at_18[0x8]; 8107 8108 u8 capability_mask[0x20]; 8109 8110 u8 reserved_at_40[0x8]; 8111 u8 link_width_enabled[0x8]; 8112 u8 link_speed_enabled[0x10]; 8113 8114 u8 lane0_physical_position[0x8]; 8115 u8 link_width_active[0x8]; 8116 u8 link_speed_active[0x10]; 8117 8118 u8 num_of_pfs[0x10]; 8119 u8 num_of_vfs[0x10]; 8120 8121 u8 bdf0[0x10]; 8122 u8 reserved_at_b0[0x10]; 8123 8124 u8 max_read_request_size[0x4]; 8125 u8 max_payload_size[0x4]; 8126 u8 reserved_at_c8[0x5]; 8127 u8 pwr_status[0x3]; 8128 u8 port_type[0x4]; 8129 u8 reserved_at_d4[0xb]; 8130 u8 lane_reversal[0x1]; 8131 8132 u8 reserved_at_e0[0x14]; 8133 u8 pci_power[0xc]; 8134 8135 u8 reserved_at_100[0x20]; 8136 8137 u8 device_status[0x10]; 8138 u8 port_state[0x8]; 8139 u8 reserved_at_138[0x8]; 8140 8141 u8 reserved_at_140[0x10]; 8142 u8 receiver_detect_result[0x10]; 8143 8144 u8 reserved_at_160[0x20]; 8145 }; 8146 8147 struct mlx5_ifc_mpcnt_reg_bits { 8148 u8 reserved_at_0[0x8]; 8149 u8 pcie_index[0x8]; 8150 u8 reserved_at_10[0xa]; 8151 u8 grp[0x6]; 8152 8153 u8 clr[0x1]; 8154 u8 reserved_at_21[0x1f]; 8155 8156 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set; 8157 }; 8158 8159 struct mlx5_ifc_ppad_reg_bits { 8160 u8 reserved_at_0[0x3]; 8161 u8 single_mac[0x1]; 8162 u8 reserved_at_4[0x4]; 8163 u8 local_port[0x8]; 8164 u8 mac_47_32[0x10]; 8165 8166 u8 mac_31_0[0x20]; 8167 8168 u8 reserved_at_40[0x40]; 8169 }; 8170 8171 struct mlx5_ifc_pmtu_reg_bits { 8172 u8 reserved_at_0[0x8]; 8173 u8 local_port[0x8]; 8174 u8 reserved_at_10[0x10]; 8175 8176 u8 max_mtu[0x10]; 8177 u8 reserved_at_30[0x10]; 8178 8179 u8 admin_mtu[0x10]; 8180 u8 reserved_at_50[0x10]; 8181 8182 u8 oper_mtu[0x10]; 8183 u8 reserved_at_70[0x10]; 8184 }; 8185 8186 struct mlx5_ifc_pmpr_reg_bits { 8187 u8 reserved_at_0[0x8]; 8188 u8 module[0x8]; 8189 u8 reserved_at_10[0x10]; 8190 8191 u8 reserved_at_20[0x18]; 8192 u8 attenuation_5g[0x8]; 8193 8194 u8 reserved_at_40[0x18]; 8195 u8 attenuation_7g[0x8]; 8196 8197 u8 reserved_at_60[0x18]; 8198 u8 attenuation_12g[0x8]; 8199 }; 8200 8201 struct mlx5_ifc_pmpe_reg_bits { 8202 u8 reserved_at_0[0x8]; 8203 u8 module[0x8]; 8204 u8 reserved_at_10[0xc]; 8205 u8 module_status[0x4]; 8206 8207 u8 reserved_at_20[0x60]; 8208 }; 8209 8210 struct mlx5_ifc_pmpc_reg_bits { 8211 u8 module_state_updated[32][0x8]; 8212 }; 8213 8214 struct mlx5_ifc_pmlpn_reg_bits { 8215 u8 reserved_at_0[0x4]; 8216 u8 mlpn_status[0x4]; 8217 u8 local_port[0x8]; 8218 u8 reserved_at_10[0x10]; 8219 8220 u8 e[0x1]; 8221 u8 reserved_at_21[0x1f]; 8222 }; 8223 8224 struct mlx5_ifc_pmlp_reg_bits { 8225 u8 rxtx[0x1]; 8226 u8 reserved_at_1[0x7]; 8227 u8 local_port[0x8]; 8228 u8 reserved_at_10[0x8]; 8229 u8 width[0x8]; 8230 8231 u8 lane0_module_mapping[0x20]; 8232 8233 u8 lane1_module_mapping[0x20]; 8234 8235 u8 lane2_module_mapping[0x20]; 8236 8237 u8 lane3_module_mapping[0x20]; 8238 8239 u8 reserved_at_a0[0x160]; 8240 }; 8241 8242 struct mlx5_ifc_pmaos_reg_bits { 8243 u8 reserved_at_0[0x8]; 8244 u8 module[0x8]; 8245 u8 reserved_at_10[0x4]; 8246 u8 admin_status[0x4]; 8247 u8 reserved_at_18[0x4]; 8248 u8 oper_status[0x4]; 8249 8250 u8 ase[0x1]; 8251 u8 ee[0x1]; 8252 u8 reserved_at_22[0x1c]; 8253 u8 e[0x2]; 8254 8255 u8 reserved_at_40[0x40]; 8256 }; 8257 8258 struct mlx5_ifc_plpc_reg_bits { 8259 u8 reserved_at_0[0x4]; 8260 u8 profile_id[0xc]; 8261 u8 reserved_at_10[0x4]; 8262 u8 proto_mask[0x4]; 8263 u8 reserved_at_18[0x8]; 8264 8265 u8 reserved_at_20[0x10]; 8266 u8 lane_speed[0x10]; 8267 8268 u8 reserved_at_40[0x17]; 8269 u8 lpbf[0x1]; 8270 u8 fec_mode_policy[0x8]; 8271 8272 u8 retransmission_capability[0x8]; 8273 u8 fec_mode_capability[0x18]; 8274 8275 u8 retransmission_support_admin[0x8]; 8276 u8 fec_mode_support_admin[0x18]; 8277 8278 u8 retransmission_request_admin[0x8]; 8279 u8 fec_mode_request_admin[0x18]; 8280 8281 u8 reserved_at_c0[0x80]; 8282 }; 8283 8284 struct mlx5_ifc_plib_reg_bits { 8285 u8 reserved_at_0[0x8]; 8286 u8 local_port[0x8]; 8287 u8 reserved_at_10[0x8]; 8288 u8 ib_port[0x8]; 8289 8290 u8 reserved_at_20[0x60]; 8291 }; 8292 8293 struct mlx5_ifc_plbf_reg_bits { 8294 u8 reserved_at_0[0x8]; 8295 u8 local_port[0x8]; 8296 u8 reserved_at_10[0xd]; 8297 u8 lbf_mode[0x3]; 8298 8299 u8 reserved_at_20[0x20]; 8300 }; 8301 8302 struct mlx5_ifc_pipg_reg_bits { 8303 u8 reserved_at_0[0x8]; 8304 u8 local_port[0x8]; 8305 u8 reserved_at_10[0x10]; 8306 8307 u8 dic[0x1]; 8308 u8 reserved_at_21[0x19]; 8309 u8 ipg[0x4]; 8310 u8 reserved_at_3e[0x2]; 8311 }; 8312 8313 struct mlx5_ifc_pifr_reg_bits { 8314 u8 reserved_at_0[0x8]; 8315 u8 local_port[0x8]; 8316 u8 reserved_at_10[0x10]; 8317 8318 u8 reserved_at_20[0xe0]; 8319 8320 u8 port_filter[8][0x20]; 8321 8322 u8 port_filter_update_en[8][0x20]; 8323 }; 8324 8325 struct mlx5_ifc_pfcc_reg_bits { 8326 u8 reserved_at_0[0x8]; 8327 u8 local_port[0x8]; 8328 u8 reserved_at_10[0xb]; 8329 u8 ppan_mask_n[0x1]; 8330 u8 minor_stall_mask[0x1]; 8331 u8 critical_stall_mask[0x1]; 8332 u8 reserved_at_1e[0x2]; 8333 8334 u8 ppan[0x4]; 8335 u8 reserved_at_24[0x4]; 8336 u8 prio_mask_tx[0x8]; 8337 u8 reserved_at_30[0x8]; 8338 u8 prio_mask_rx[0x8]; 8339 8340 u8 pptx[0x1]; 8341 u8 aptx[0x1]; 8342 u8 pptx_mask_n[0x1]; 8343 u8 reserved_at_43[0x5]; 8344 u8 pfctx[0x8]; 8345 u8 reserved_at_50[0x10]; 8346 8347 u8 pprx[0x1]; 8348 u8 aprx[0x1]; 8349 u8 pprx_mask_n[0x1]; 8350 u8 reserved_at_63[0x5]; 8351 u8 pfcrx[0x8]; 8352 u8 reserved_at_70[0x10]; 8353 8354 u8 device_stall_minor_watermark[0x10]; 8355 u8 device_stall_critical_watermark[0x10]; 8356 8357 u8 reserved_at_a0[0x60]; 8358 }; 8359 8360 struct mlx5_ifc_pelc_reg_bits { 8361 u8 op[0x4]; 8362 u8 reserved_at_4[0x4]; 8363 u8 local_port[0x8]; 8364 u8 reserved_at_10[0x10]; 8365 8366 u8 op_admin[0x8]; 8367 u8 op_capability[0x8]; 8368 u8 op_request[0x8]; 8369 u8 op_active[0x8]; 8370 8371 u8 admin[0x40]; 8372 8373 u8 capability[0x40]; 8374 8375 u8 request[0x40]; 8376 8377 u8 active[0x40]; 8378 8379 u8 reserved_at_140[0x80]; 8380 }; 8381 8382 struct mlx5_ifc_peir_reg_bits { 8383 u8 reserved_at_0[0x8]; 8384 u8 local_port[0x8]; 8385 u8 reserved_at_10[0x10]; 8386 8387 u8 reserved_at_20[0xc]; 8388 u8 error_count[0x4]; 8389 u8 reserved_at_30[0x10]; 8390 8391 u8 reserved_at_40[0xc]; 8392 u8 lane[0x4]; 8393 u8 reserved_at_50[0x8]; 8394 u8 error_type[0x8]; 8395 }; 8396 8397 struct mlx5_ifc_mpegc_reg_bits { 8398 u8 reserved_at_0[0x30]; 8399 u8 field_select[0x10]; 8400 8401 u8 tx_overflow_sense[0x1]; 8402 u8 mark_cqe[0x1]; 8403 u8 mark_cnp[0x1]; 8404 u8 reserved_at_43[0x1b]; 8405 u8 tx_lossy_overflow_oper[0x2]; 8406 8407 u8 reserved_at_60[0x100]; 8408 }; 8409 8410 struct mlx5_ifc_pcam_enhanced_features_bits { 8411 u8 reserved_at_0[0x6d]; 8412 u8 rx_icrc_encapsulated_counter[0x1]; 8413 u8 reserved_at_6e[0x4]; 8414 u8 ptys_extended_ethernet[0x1]; 8415 u8 reserved_at_73[0x3]; 8416 u8 pfcc_mask[0x1]; 8417 u8 reserved_at_77[0x3]; 8418 u8 per_lane_error_counters[0x1]; 8419 u8 rx_buffer_fullness_counters[0x1]; 8420 u8 ptys_connector_type[0x1]; 8421 u8 reserved_at_7d[0x1]; 8422 u8 ppcnt_discard_group[0x1]; 8423 u8 ppcnt_statistical_group[0x1]; 8424 }; 8425 8426 struct mlx5_ifc_pcam_regs_5000_to_507f_bits { 8427 u8 port_access_reg_cap_mask_127_to_96[0x20]; 8428 u8 port_access_reg_cap_mask_95_to_64[0x20]; 8429 8430 u8 port_access_reg_cap_mask_63_to_36[0x1c]; 8431 u8 pplm[0x1]; 8432 u8 port_access_reg_cap_mask_34_to_32[0x3]; 8433 8434 u8 port_access_reg_cap_mask_31_to_13[0x13]; 8435 u8 pbmc[0x1]; 8436 u8 pptb[0x1]; 8437 u8 port_access_reg_cap_mask_10_to_09[0x2]; 8438 u8 ppcnt[0x1]; 8439 u8 port_access_reg_cap_mask_07_to_00[0x8]; 8440 }; 8441 8442 struct mlx5_ifc_pcam_reg_bits { 8443 u8 reserved_at_0[0x8]; 8444 u8 feature_group[0x8]; 8445 u8 reserved_at_10[0x8]; 8446 u8 access_reg_group[0x8]; 8447 8448 u8 reserved_at_20[0x20]; 8449 8450 union { 8451 struct mlx5_ifc_pcam_regs_5000_to_507f_bits regs_5000_to_507f; 8452 u8 reserved_at_0[0x80]; 8453 } port_access_reg_cap_mask; 8454 8455 u8 reserved_at_c0[0x80]; 8456 8457 union { 8458 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features; 8459 u8 reserved_at_0[0x80]; 8460 } feature_cap_mask; 8461 8462 u8 reserved_at_1c0[0xc0]; 8463 }; 8464 8465 struct mlx5_ifc_mcam_enhanced_features_bits { 8466 u8 reserved_at_0[0x6e]; 8467 u8 pci_status_and_power[0x1]; 8468 u8 reserved_at_6f[0x5]; 8469 u8 mark_tx_action_cnp[0x1]; 8470 u8 mark_tx_action_cqe[0x1]; 8471 u8 dynamic_tx_overflow[0x1]; 8472 u8 reserved_at_77[0x4]; 8473 u8 pcie_outbound_stalled[0x1]; 8474 u8 tx_overflow_buffer_pkt[0x1]; 8475 u8 mtpps_enh_out_per_adj[0x1]; 8476 u8 mtpps_fs[0x1]; 8477 u8 pcie_performance_group[0x1]; 8478 }; 8479 8480 struct mlx5_ifc_mcam_access_reg_bits { 8481 u8 reserved_at_0[0x1c]; 8482 u8 mcda[0x1]; 8483 u8 mcc[0x1]; 8484 u8 mcqi[0x1]; 8485 u8 reserved_at_1f[0x1]; 8486 8487 u8 regs_95_to_87[0x9]; 8488 u8 mpegc[0x1]; 8489 u8 regs_85_to_68[0x12]; 8490 u8 tracer_registers[0x4]; 8491 8492 u8 regs_63_to_32[0x20]; 8493 u8 regs_31_to_0[0x20]; 8494 }; 8495 8496 struct mlx5_ifc_mcam_reg_bits { 8497 u8 reserved_at_0[0x8]; 8498 u8 feature_group[0x8]; 8499 u8 reserved_at_10[0x8]; 8500 u8 access_reg_group[0x8]; 8501 8502 u8 reserved_at_20[0x20]; 8503 8504 union { 8505 struct mlx5_ifc_mcam_access_reg_bits access_regs; 8506 u8 reserved_at_0[0x80]; 8507 } mng_access_reg_cap_mask; 8508 8509 u8 reserved_at_c0[0x80]; 8510 8511 union { 8512 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features; 8513 u8 reserved_at_0[0x80]; 8514 } mng_feature_cap_mask; 8515 8516 u8 reserved_at_1c0[0x80]; 8517 }; 8518 8519 struct mlx5_ifc_qcam_access_reg_cap_mask { 8520 u8 qcam_access_reg_cap_mask_127_to_20[0x6C]; 8521 u8 qpdpm[0x1]; 8522 u8 qcam_access_reg_cap_mask_18_to_4[0x0F]; 8523 u8 qdpm[0x1]; 8524 u8 qpts[0x1]; 8525 u8 qcap[0x1]; 8526 u8 qcam_access_reg_cap_mask_0[0x1]; 8527 }; 8528 8529 struct mlx5_ifc_qcam_qos_feature_cap_mask { 8530 u8 qcam_qos_feature_cap_mask_127_to_1[0x7F]; 8531 u8 qpts_trust_both[0x1]; 8532 }; 8533 8534 struct mlx5_ifc_qcam_reg_bits { 8535 u8 reserved_at_0[0x8]; 8536 u8 feature_group[0x8]; 8537 u8 reserved_at_10[0x8]; 8538 u8 access_reg_group[0x8]; 8539 u8 reserved_at_20[0x20]; 8540 8541 union { 8542 struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap; 8543 u8 reserved_at_0[0x80]; 8544 } qos_access_reg_cap_mask; 8545 8546 u8 reserved_at_c0[0x80]; 8547 8548 union { 8549 struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap; 8550 u8 reserved_at_0[0x80]; 8551 } qos_feature_cap_mask; 8552 8553 u8 reserved_at_1c0[0x80]; 8554 }; 8555 8556 struct mlx5_ifc_core_dump_reg_bits { 8557 u8 reserved_at_0[0x18]; 8558 u8 core_dump_type[0x8]; 8559 8560 u8 reserved_at_20[0x30]; 8561 u8 vhca_id[0x10]; 8562 8563 u8 reserved_at_60[0x8]; 8564 u8 qpn[0x18]; 8565 u8 reserved_at_80[0x180]; 8566 }; 8567 8568 struct mlx5_ifc_pcap_reg_bits { 8569 u8 reserved_at_0[0x8]; 8570 u8 local_port[0x8]; 8571 u8 reserved_at_10[0x10]; 8572 8573 u8 port_capability_mask[4][0x20]; 8574 }; 8575 8576 struct mlx5_ifc_paos_reg_bits { 8577 u8 swid[0x8]; 8578 u8 local_port[0x8]; 8579 u8 reserved_at_10[0x4]; 8580 u8 admin_status[0x4]; 8581 u8 reserved_at_18[0x4]; 8582 u8 oper_status[0x4]; 8583 8584 u8 ase[0x1]; 8585 u8 ee[0x1]; 8586 u8 reserved_at_22[0x1c]; 8587 u8 e[0x2]; 8588 8589 u8 reserved_at_40[0x40]; 8590 }; 8591 8592 struct mlx5_ifc_pamp_reg_bits { 8593 u8 reserved_at_0[0x8]; 8594 u8 opamp_group[0x8]; 8595 u8 reserved_at_10[0xc]; 8596 u8 opamp_group_type[0x4]; 8597 8598 u8 start_index[0x10]; 8599 u8 reserved_at_30[0x4]; 8600 u8 num_of_indices[0xc]; 8601 8602 u8 index_data[18][0x10]; 8603 }; 8604 8605 struct mlx5_ifc_pcmr_reg_bits { 8606 u8 reserved_at_0[0x8]; 8607 u8 local_port[0x8]; 8608 u8 reserved_at_10[0x10]; 8609 u8 entropy_force_cap[0x1]; 8610 u8 entropy_calc_cap[0x1]; 8611 u8 entropy_gre_calc_cap[0x1]; 8612 u8 reserved_at_23[0x1b]; 8613 u8 fcs_cap[0x1]; 8614 u8 reserved_at_3f[0x1]; 8615 u8 entropy_force[0x1]; 8616 u8 entropy_calc[0x1]; 8617 u8 entropy_gre_calc[0x1]; 8618 u8 reserved_at_43[0x1b]; 8619 u8 fcs_chk[0x1]; 8620 u8 reserved_at_5f[0x1]; 8621 }; 8622 8623 struct mlx5_ifc_lane_2_module_mapping_bits { 8624 u8 reserved_at_0[0x6]; 8625 u8 rx_lane[0x2]; 8626 u8 reserved_at_8[0x6]; 8627 u8 tx_lane[0x2]; 8628 u8 reserved_at_10[0x8]; 8629 u8 module[0x8]; 8630 }; 8631 8632 struct mlx5_ifc_bufferx_reg_bits { 8633 u8 reserved_at_0[0x6]; 8634 u8 lossy[0x1]; 8635 u8 epsb[0x1]; 8636 u8 reserved_at_8[0xc]; 8637 u8 size[0xc]; 8638 8639 u8 xoff_threshold[0x10]; 8640 u8 xon_threshold[0x10]; 8641 }; 8642 8643 struct mlx5_ifc_set_node_in_bits { 8644 u8 node_description[64][0x8]; 8645 }; 8646 8647 struct mlx5_ifc_register_power_settings_bits { 8648 u8 reserved_at_0[0x18]; 8649 u8 power_settings_level[0x8]; 8650 8651 u8 reserved_at_20[0x60]; 8652 }; 8653 8654 struct mlx5_ifc_register_host_endianness_bits { 8655 u8 he[0x1]; 8656 u8 reserved_at_1[0x1f]; 8657 8658 u8 reserved_at_20[0x60]; 8659 }; 8660 8661 struct mlx5_ifc_umr_pointer_desc_argument_bits { 8662 u8 reserved_at_0[0x20]; 8663 8664 u8 mkey[0x20]; 8665 8666 u8 addressh_63_32[0x20]; 8667 8668 u8 addressl_31_0[0x20]; 8669 }; 8670 8671 struct mlx5_ifc_ud_adrs_vector_bits { 8672 u8 dc_key[0x40]; 8673 8674 u8 ext[0x1]; 8675 u8 reserved_at_41[0x7]; 8676 u8 destination_qp_dct[0x18]; 8677 8678 u8 static_rate[0x4]; 8679 u8 sl_eth_prio[0x4]; 8680 u8 fl[0x1]; 8681 u8 mlid[0x7]; 8682 u8 rlid_udp_sport[0x10]; 8683 8684 u8 reserved_at_80[0x20]; 8685 8686 u8 rmac_47_16[0x20]; 8687 8688 u8 rmac_15_0[0x10]; 8689 u8 tclass[0x8]; 8690 u8 hop_limit[0x8]; 8691 8692 u8 reserved_at_e0[0x1]; 8693 u8 grh[0x1]; 8694 u8 reserved_at_e2[0x2]; 8695 u8 src_addr_index[0x8]; 8696 u8 flow_label[0x14]; 8697 8698 u8 rgid_rip[16][0x8]; 8699 }; 8700 8701 struct mlx5_ifc_pages_req_event_bits { 8702 u8 reserved_at_0[0x10]; 8703 u8 function_id[0x10]; 8704 8705 u8 num_pages[0x20]; 8706 8707 u8 reserved_at_40[0xa0]; 8708 }; 8709 8710 struct mlx5_ifc_eqe_bits { 8711 u8 reserved_at_0[0x8]; 8712 u8 event_type[0x8]; 8713 u8 reserved_at_10[0x8]; 8714 u8 event_sub_type[0x8]; 8715 8716 u8 reserved_at_20[0xe0]; 8717 8718 union mlx5_ifc_event_auto_bits event_data; 8719 8720 u8 reserved_at_1e0[0x10]; 8721 u8 signature[0x8]; 8722 u8 reserved_at_1f8[0x7]; 8723 u8 owner[0x1]; 8724 }; 8725 8726 enum { 8727 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7, 8728 }; 8729 8730 struct mlx5_ifc_cmd_queue_entry_bits { 8731 u8 type[0x8]; 8732 u8 reserved_at_8[0x18]; 8733 8734 u8 input_length[0x20]; 8735 8736 u8 input_mailbox_pointer_63_32[0x20]; 8737 8738 u8 input_mailbox_pointer_31_9[0x17]; 8739 u8 reserved_at_77[0x9]; 8740 8741 u8 command_input_inline_data[16][0x8]; 8742 8743 u8 command_output_inline_data[16][0x8]; 8744 8745 u8 output_mailbox_pointer_63_32[0x20]; 8746 8747 u8 output_mailbox_pointer_31_9[0x17]; 8748 u8 reserved_at_1b7[0x9]; 8749 8750 u8 output_length[0x20]; 8751 8752 u8 token[0x8]; 8753 u8 signature[0x8]; 8754 u8 reserved_at_1f0[0x8]; 8755 u8 status[0x7]; 8756 u8 ownership[0x1]; 8757 }; 8758 8759 struct mlx5_ifc_cmd_out_bits { 8760 u8 status[0x8]; 8761 u8 reserved_at_8[0x18]; 8762 8763 u8 syndrome[0x20]; 8764 8765 u8 command_output[0x20]; 8766 }; 8767 8768 struct mlx5_ifc_cmd_in_bits { 8769 u8 opcode[0x10]; 8770 u8 reserved_at_10[0x10]; 8771 8772 u8 reserved_at_20[0x10]; 8773 u8 op_mod[0x10]; 8774 8775 u8 command[0][0x20]; 8776 }; 8777 8778 struct mlx5_ifc_cmd_if_box_bits { 8779 u8 mailbox_data[512][0x8]; 8780 8781 u8 reserved_at_1000[0x180]; 8782 8783 u8 next_pointer_63_32[0x20]; 8784 8785 u8 next_pointer_31_10[0x16]; 8786 u8 reserved_at_11b6[0xa]; 8787 8788 u8 block_number[0x20]; 8789 8790 u8 reserved_at_11e0[0x8]; 8791 u8 token[0x8]; 8792 u8 ctrl_signature[0x8]; 8793 u8 signature[0x8]; 8794 }; 8795 8796 struct mlx5_ifc_mtt_bits { 8797 u8 ptag_63_32[0x20]; 8798 8799 u8 ptag_31_8[0x18]; 8800 u8 reserved_at_38[0x6]; 8801 u8 wr_en[0x1]; 8802 u8 rd_en[0x1]; 8803 }; 8804 8805 struct mlx5_ifc_query_wol_rol_out_bits { 8806 u8 status[0x8]; 8807 u8 reserved_at_8[0x18]; 8808 8809 u8 syndrome[0x20]; 8810 8811 u8 reserved_at_40[0x10]; 8812 u8 rol_mode[0x8]; 8813 u8 wol_mode[0x8]; 8814 8815 u8 reserved_at_60[0x20]; 8816 }; 8817 8818 struct mlx5_ifc_query_wol_rol_in_bits { 8819 u8 opcode[0x10]; 8820 u8 reserved_at_10[0x10]; 8821 8822 u8 reserved_at_20[0x10]; 8823 u8 op_mod[0x10]; 8824 8825 u8 reserved_at_40[0x40]; 8826 }; 8827 8828 struct mlx5_ifc_set_wol_rol_out_bits { 8829 u8 status[0x8]; 8830 u8 reserved_at_8[0x18]; 8831 8832 u8 syndrome[0x20]; 8833 8834 u8 reserved_at_40[0x40]; 8835 }; 8836 8837 struct mlx5_ifc_set_wol_rol_in_bits { 8838 u8 opcode[0x10]; 8839 u8 reserved_at_10[0x10]; 8840 8841 u8 reserved_at_20[0x10]; 8842 u8 op_mod[0x10]; 8843 8844 u8 rol_mode_valid[0x1]; 8845 u8 wol_mode_valid[0x1]; 8846 u8 reserved_at_42[0xe]; 8847 u8 rol_mode[0x8]; 8848 u8 wol_mode[0x8]; 8849 8850 u8 reserved_at_60[0x20]; 8851 }; 8852 8853 enum { 8854 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0, 8855 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1, 8856 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2, 8857 }; 8858 8859 enum { 8860 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0, 8861 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1, 8862 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2, 8863 }; 8864 8865 enum { 8866 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR = 0x1, 8867 MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC = 0x7, 8868 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR = 0x8, 8869 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR = 0x9, 8870 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR = 0xa, 8871 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR = 0xb, 8872 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN = 0xc, 8873 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR = 0xd, 8874 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV = 0xe, 8875 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR = 0xf, 8876 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR = 0x10, 8877 }; 8878 8879 struct mlx5_ifc_initial_seg_bits { 8880 u8 fw_rev_minor[0x10]; 8881 u8 fw_rev_major[0x10]; 8882 8883 u8 cmd_interface_rev[0x10]; 8884 u8 fw_rev_subminor[0x10]; 8885 8886 u8 reserved_at_40[0x40]; 8887 8888 u8 cmdq_phy_addr_63_32[0x20]; 8889 8890 u8 cmdq_phy_addr_31_12[0x14]; 8891 u8 reserved_at_b4[0x2]; 8892 u8 nic_interface[0x2]; 8893 u8 log_cmdq_size[0x4]; 8894 u8 log_cmdq_stride[0x4]; 8895 8896 u8 command_doorbell_vector[0x20]; 8897 8898 u8 reserved_at_e0[0xf00]; 8899 8900 u8 initializing[0x1]; 8901 u8 reserved_at_fe1[0x4]; 8902 u8 nic_interface_supported[0x3]; 8903 u8 embedded_cpu[0x1]; 8904 u8 reserved_at_fe9[0x17]; 8905 8906 struct mlx5_ifc_health_buffer_bits health_buffer; 8907 8908 u8 no_dram_nic_offset[0x20]; 8909 8910 u8 reserved_at_1220[0x6e40]; 8911 8912 u8 reserved_at_8060[0x1f]; 8913 u8 clear_int[0x1]; 8914 8915 u8 health_syndrome[0x8]; 8916 u8 health_counter[0x18]; 8917 8918 u8 reserved_at_80a0[0x17fc0]; 8919 }; 8920 8921 struct mlx5_ifc_mtpps_reg_bits { 8922 u8 reserved_at_0[0xc]; 8923 u8 cap_number_of_pps_pins[0x4]; 8924 u8 reserved_at_10[0x4]; 8925 u8 cap_max_num_of_pps_in_pins[0x4]; 8926 u8 reserved_at_18[0x4]; 8927 u8 cap_max_num_of_pps_out_pins[0x4]; 8928 8929 u8 reserved_at_20[0x24]; 8930 u8 cap_pin_3_mode[0x4]; 8931 u8 reserved_at_48[0x4]; 8932 u8 cap_pin_2_mode[0x4]; 8933 u8 reserved_at_50[0x4]; 8934 u8 cap_pin_1_mode[0x4]; 8935 u8 reserved_at_58[0x4]; 8936 u8 cap_pin_0_mode[0x4]; 8937 8938 u8 reserved_at_60[0x4]; 8939 u8 cap_pin_7_mode[0x4]; 8940 u8 reserved_at_68[0x4]; 8941 u8 cap_pin_6_mode[0x4]; 8942 u8 reserved_at_70[0x4]; 8943 u8 cap_pin_5_mode[0x4]; 8944 u8 reserved_at_78[0x4]; 8945 u8 cap_pin_4_mode[0x4]; 8946 8947 u8 field_select[0x20]; 8948 u8 reserved_at_a0[0x60]; 8949 8950 u8 enable[0x1]; 8951 u8 reserved_at_101[0xb]; 8952 u8 pattern[0x4]; 8953 u8 reserved_at_110[0x4]; 8954 u8 pin_mode[0x4]; 8955 u8 pin[0x8]; 8956 8957 u8 reserved_at_120[0x20]; 8958 8959 u8 time_stamp[0x40]; 8960 8961 u8 out_pulse_duration[0x10]; 8962 u8 out_periodic_adjustment[0x10]; 8963 u8 enhanced_out_periodic_adjustment[0x20]; 8964 8965 u8 reserved_at_1c0[0x20]; 8966 }; 8967 8968 struct mlx5_ifc_mtppse_reg_bits { 8969 u8 reserved_at_0[0x18]; 8970 u8 pin[0x8]; 8971 u8 event_arm[0x1]; 8972 u8 reserved_at_21[0x1b]; 8973 u8 event_generation_mode[0x4]; 8974 u8 reserved_at_40[0x40]; 8975 }; 8976 8977 struct mlx5_ifc_mcqi_cap_bits { 8978 u8 supported_info_bitmask[0x20]; 8979 8980 u8 component_size[0x20]; 8981 8982 u8 max_component_size[0x20]; 8983 8984 u8 log_mcda_word_size[0x4]; 8985 u8 reserved_at_64[0xc]; 8986 u8 mcda_max_write_size[0x10]; 8987 8988 u8 rd_en[0x1]; 8989 u8 reserved_at_81[0x1]; 8990 u8 match_chip_id[0x1]; 8991 u8 match_psid[0x1]; 8992 u8 check_user_timestamp[0x1]; 8993 u8 match_base_guid_mac[0x1]; 8994 u8 reserved_at_86[0x1a]; 8995 }; 8996 8997 struct mlx5_ifc_mcqi_reg_bits { 8998 u8 read_pending_component[0x1]; 8999 u8 reserved_at_1[0xf]; 9000 u8 component_index[0x10]; 9001 9002 u8 reserved_at_20[0x20]; 9003 9004 u8 reserved_at_40[0x1b]; 9005 u8 info_type[0x5]; 9006 9007 u8 info_size[0x20]; 9008 9009 u8 offset[0x20]; 9010 9011 u8 reserved_at_a0[0x10]; 9012 u8 data_size[0x10]; 9013 9014 u8 data[0][0x20]; 9015 }; 9016 9017 struct mlx5_ifc_mcc_reg_bits { 9018 u8 reserved_at_0[0x4]; 9019 u8 time_elapsed_since_last_cmd[0xc]; 9020 u8 reserved_at_10[0x8]; 9021 u8 instruction[0x8]; 9022 9023 u8 reserved_at_20[0x10]; 9024 u8 component_index[0x10]; 9025 9026 u8 reserved_at_40[0x8]; 9027 u8 update_handle[0x18]; 9028 9029 u8 handle_owner_type[0x4]; 9030 u8 handle_owner_host_id[0x4]; 9031 u8 reserved_at_68[0x1]; 9032 u8 control_progress[0x7]; 9033 u8 error_code[0x8]; 9034 u8 reserved_at_78[0x4]; 9035 u8 control_state[0x4]; 9036 9037 u8 component_size[0x20]; 9038 9039 u8 reserved_at_a0[0x60]; 9040 }; 9041 9042 struct mlx5_ifc_mcda_reg_bits { 9043 u8 reserved_at_0[0x8]; 9044 u8 update_handle[0x18]; 9045 9046 u8 offset[0x20]; 9047 9048 u8 reserved_at_40[0x10]; 9049 u8 size[0x10]; 9050 9051 u8 reserved_at_60[0x20]; 9052 9053 u8 data[0][0x20]; 9054 }; 9055 9056 union mlx5_ifc_ports_control_registers_document_bits { 9057 struct mlx5_ifc_bufferx_reg_bits bufferx_reg; 9058 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 9059 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 9060 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 9061 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 9062 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 9063 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 9064 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout; 9065 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping; 9066 struct mlx5_ifc_pamp_reg_bits pamp_reg; 9067 struct mlx5_ifc_paos_reg_bits paos_reg; 9068 struct mlx5_ifc_pcap_reg_bits pcap_reg; 9069 struct mlx5_ifc_peir_reg_bits peir_reg; 9070 struct mlx5_ifc_pelc_reg_bits pelc_reg; 9071 struct mlx5_ifc_pfcc_reg_bits pfcc_reg; 9072 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 9073 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 9074 struct mlx5_ifc_pifr_reg_bits pifr_reg; 9075 struct mlx5_ifc_pipg_reg_bits pipg_reg; 9076 struct mlx5_ifc_plbf_reg_bits plbf_reg; 9077 struct mlx5_ifc_plib_reg_bits plib_reg; 9078 struct mlx5_ifc_plpc_reg_bits plpc_reg; 9079 struct mlx5_ifc_pmaos_reg_bits pmaos_reg; 9080 struct mlx5_ifc_pmlp_reg_bits pmlp_reg; 9081 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg; 9082 struct mlx5_ifc_pmpc_reg_bits pmpc_reg; 9083 struct mlx5_ifc_pmpe_reg_bits pmpe_reg; 9084 struct mlx5_ifc_pmpr_reg_bits pmpr_reg; 9085 struct mlx5_ifc_pmtu_reg_bits pmtu_reg; 9086 struct mlx5_ifc_ppad_reg_bits ppad_reg; 9087 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg; 9088 struct mlx5_ifc_mpein_reg_bits mpein_reg; 9089 struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg; 9090 struct mlx5_ifc_pplm_reg_bits pplm_reg; 9091 struct mlx5_ifc_pplr_reg_bits pplr_reg; 9092 struct mlx5_ifc_ppsc_reg_bits ppsc_reg; 9093 struct mlx5_ifc_pqdr_reg_bits pqdr_reg; 9094 struct mlx5_ifc_pspa_reg_bits pspa_reg; 9095 struct mlx5_ifc_ptas_reg_bits ptas_reg; 9096 struct mlx5_ifc_ptys_reg_bits ptys_reg; 9097 struct mlx5_ifc_mlcr_reg_bits mlcr_reg; 9098 struct mlx5_ifc_pude_reg_bits pude_reg; 9099 struct mlx5_ifc_pvlc_reg_bits pvlc_reg; 9100 struct mlx5_ifc_slrg_reg_bits slrg_reg; 9101 struct mlx5_ifc_sltp_reg_bits sltp_reg; 9102 struct mlx5_ifc_mtpps_reg_bits mtpps_reg; 9103 struct mlx5_ifc_mtppse_reg_bits mtppse_reg; 9104 struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg; 9105 struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits; 9106 struct mlx5_ifc_fpga_cap_bits fpga_cap_bits; 9107 struct mlx5_ifc_mcqi_reg_bits mcqi_reg; 9108 struct mlx5_ifc_mcc_reg_bits mcc_reg; 9109 struct mlx5_ifc_mcda_reg_bits mcda_reg; 9110 u8 reserved_at_0[0x60e0]; 9111 }; 9112 9113 union mlx5_ifc_debug_enhancements_document_bits { 9114 struct mlx5_ifc_health_buffer_bits health_buffer; 9115 u8 reserved_at_0[0x200]; 9116 }; 9117 9118 union mlx5_ifc_uplink_pci_interface_document_bits { 9119 struct mlx5_ifc_initial_seg_bits initial_seg; 9120 u8 reserved_at_0[0x20060]; 9121 }; 9122 9123 struct mlx5_ifc_set_flow_table_root_out_bits { 9124 u8 status[0x8]; 9125 u8 reserved_at_8[0x18]; 9126 9127 u8 syndrome[0x20]; 9128 9129 u8 reserved_at_40[0x40]; 9130 }; 9131 9132 struct mlx5_ifc_set_flow_table_root_in_bits { 9133 u8 opcode[0x10]; 9134 u8 reserved_at_10[0x10]; 9135 9136 u8 reserved_at_20[0x10]; 9137 u8 op_mod[0x10]; 9138 9139 u8 other_vport[0x1]; 9140 u8 reserved_at_41[0xf]; 9141 u8 vport_number[0x10]; 9142 9143 u8 reserved_at_60[0x20]; 9144 9145 u8 table_type[0x8]; 9146 u8 reserved_at_88[0x18]; 9147 9148 u8 reserved_at_a0[0x8]; 9149 u8 table_id[0x18]; 9150 9151 u8 reserved_at_c0[0x8]; 9152 u8 underlay_qpn[0x18]; 9153 u8 reserved_at_e0[0x120]; 9154 }; 9155 9156 enum { 9157 MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = (1UL << 0), 9158 MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15), 9159 }; 9160 9161 struct mlx5_ifc_modify_flow_table_out_bits { 9162 u8 status[0x8]; 9163 u8 reserved_at_8[0x18]; 9164 9165 u8 syndrome[0x20]; 9166 9167 u8 reserved_at_40[0x40]; 9168 }; 9169 9170 struct mlx5_ifc_modify_flow_table_in_bits { 9171 u8 opcode[0x10]; 9172 u8 reserved_at_10[0x10]; 9173 9174 u8 reserved_at_20[0x10]; 9175 u8 op_mod[0x10]; 9176 9177 u8 other_vport[0x1]; 9178 u8 reserved_at_41[0xf]; 9179 u8 vport_number[0x10]; 9180 9181 u8 reserved_at_60[0x10]; 9182 u8 modify_field_select[0x10]; 9183 9184 u8 table_type[0x8]; 9185 u8 reserved_at_88[0x18]; 9186 9187 u8 reserved_at_a0[0x8]; 9188 u8 table_id[0x18]; 9189 9190 struct mlx5_ifc_flow_table_context_bits flow_table_context; 9191 }; 9192 9193 struct mlx5_ifc_ets_tcn_config_reg_bits { 9194 u8 g[0x1]; 9195 u8 b[0x1]; 9196 u8 r[0x1]; 9197 u8 reserved_at_3[0x9]; 9198 u8 group[0x4]; 9199 u8 reserved_at_10[0x9]; 9200 u8 bw_allocation[0x7]; 9201 9202 u8 reserved_at_20[0xc]; 9203 u8 max_bw_units[0x4]; 9204 u8 reserved_at_30[0x8]; 9205 u8 max_bw_value[0x8]; 9206 }; 9207 9208 struct mlx5_ifc_ets_global_config_reg_bits { 9209 u8 reserved_at_0[0x2]; 9210 u8 r[0x1]; 9211 u8 reserved_at_3[0x1d]; 9212 9213 u8 reserved_at_20[0xc]; 9214 u8 max_bw_units[0x4]; 9215 u8 reserved_at_30[0x8]; 9216 u8 max_bw_value[0x8]; 9217 }; 9218 9219 struct mlx5_ifc_qetc_reg_bits { 9220 u8 reserved_at_0[0x8]; 9221 u8 port_number[0x8]; 9222 u8 reserved_at_10[0x30]; 9223 9224 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8]; 9225 struct mlx5_ifc_ets_global_config_reg_bits global_configuration; 9226 }; 9227 9228 struct mlx5_ifc_qpdpm_dscp_reg_bits { 9229 u8 e[0x1]; 9230 u8 reserved_at_01[0x0b]; 9231 u8 prio[0x04]; 9232 }; 9233 9234 struct mlx5_ifc_qpdpm_reg_bits { 9235 u8 reserved_at_0[0x8]; 9236 u8 local_port[0x8]; 9237 u8 reserved_at_10[0x10]; 9238 struct mlx5_ifc_qpdpm_dscp_reg_bits dscp[64]; 9239 }; 9240 9241 struct mlx5_ifc_qpts_reg_bits { 9242 u8 reserved_at_0[0x8]; 9243 u8 local_port[0x8]; 9244 u8 reserved_at_10[0x2d]; 9245 u8 trust_state[0x3]; 9246 }; 9247 9248 struct mlx5_ifc_pptb_reg_bits { 9249 u8 reserved_at_0[0x2]; 9250 u8 mm[0x2]; 9251 u8 reserved_at_4[0x4]; 9252 u8 local_port[0x8]; 9253 u8 reserved_at_10[0x6]; 9254 u8 cm[0x1]; 9255 u8 um[0x1]; 9256 u8 pm[0x8]; 9257 9258 u8 prio_x_buff[0x20]; 9259 9260 u8 pm_msb[0x8]; 9261 u8 reserved_at_48[0x10]; 9262 u8 ctrl_buff[0x4]; 9263 u8 untagged_buff[0x4]; 9264 }; 9265 9266 struct mlx5_ifc_pbmc_reg_bits { 9267 u8 reserved_at_0[0x8]; 9268 u8 local_port[0x8]; 9269 u8 reserved_at_10[0x10]; 9270 9271 u8 xoff_timer_value[0x10]; 9272 u8 xoff_refresh[0x10]; 9273 9274 u8 reserved_at_40[0x9]; 9275 u8 fullness_threshold[0x7]; 9276 u8 port_buffer_size[0x10]; 9277 9278 struct mlx5_ifc_bufferx_reg_bits buffer[10]; 9279 9280 u8 reserved_at_2e0[0x40]; 9281 }; 9282 9283 struct mlx5_ifc_qtct_reg_bits { 9284 u8 reserved_at_0[0x8]; 9285 u8 port_number[0x8]; 9286 u8 reserved_at_10[0xd]; 9287 u8 prio[0x3]; 9288 9289 u8 reserved_at_20[0x1d]; 9290 u8 tclass[0x3]; 9291 }; 9292 9293 struct mlx5_ifc_mcia_reg_bits { 9294 u8 l[0x1]; 9295 u8 reserved_at_1[0x7]; 9296 u8 module[0x8]; 9297 u8 reserved_at_10[0x8]; 9298 u8 status[0x8]; 9299 9300 u8 i2c_device_address[0x8]; 9301 u8 page_number[0x8]; 9302 u8 device_address[0x10]; 9303 9304 u8 reserved_at_40[0x10]; 9305 u8 size[0x10]; 9306 9307 u8 reserved_at_60[0x20]; 9308 9309 u8 dword_0[0x20]; 9310 u8 dword_1[0x20]; 9311 u8 dword_2[0x20]; 9312 u8 dword_3[0x20]; 9313 u8 dword_4[0x20]; 9314 u8 dword_5[0x20]; 9315 u8 dword_6[0x20]; 9316 u8 dword_7[0x20]; 9317 u8 dword_8[0x20]; 9318 u8 dword_9[0x20]; 9319 u8 dword_10[0x20]; 9320 u8 dword_11[0x20]; 9321 }; 9322 9323 struct mlx5_ifc_dcbx_param_bits { 9324 u8 dcbx_cee_cap[0x1]; 9325 u8 dcbx_ieee_cap[0x1]; 9326 u8 dcbx_standby_cap[0x1]; 9327 u8 reserved_at_3[0x5]; 9328 u8 port_number[0x8]; 9329 u8 reserved_at_10[0xa]; 9330 u8 max_application_table_size[6]; 9331 u8 reserved_at_20[0x15]; 9332 u8 version_oper[0x3]; 9333 u8 reserved_at_38[5]; 9334 u8 version_admin[0x3]; 9335 u8 willing_admin[0x1]; 9336 u8 reserved_at_41[0x3]; 9337 u8 pfc_cap_oper[0x4]; 9338 u8 reserved_at_48[0x4]; 9339 u8 pfc_cap_admin[0x4]; 9340 u8 reserved_at_50[0x4]; 9341 u8 num_of_tc_oper[0x4]; 9342 u8 reserved_at_58[0x4]; 9343 u8 num_of_tc_admin[0x4]; 9344 u8 remote_willing[0x1]; 9345 u8 reserved_at_61[3]; 9346 u8 remote_pfc_cap[4]; 9347 u8 reserved_at_68[0x14]; 9348 u8 remote_num_of_tc[0x4]; 9349 u8 reserved_at_80[0x18]; 9350 u8 error[0x8]; 9351 u8 reserved_at_a0[0x160]; 9352 }; 9353 9354 struct mlx5_ifc_lagc_bits { 9355 u8 reserved_at_0[0x1d]; 9356 u8 lag_state[0x3]; 9357 9358 u8 reserved_at_20[0x14]; 9359 u8 tx_remap_affinity_2[0x4]; 9360 u8 reserved_at_38[0x4]; 9361 u8 tx_remap_affinity_1[0x4]; 9362 }; 9363 9364 struct mlx5_ifc_create_lag_out_bits { 9365 u8 status[0x8]; 9366 u8 reserved_at_8[0x18]; 9367 9368 u8 syndrome[0x20]; 9369 9370 u8 reserved_at_40[0x40]; 9371 }; 9372 9373 struct mlx5_ifc_create_lag_in_bits { 9374 u8 opcode[0x10]; 9375 u8 reserved_at_10[0x10]; 9376 9377 u8 reserved_at_20[0x10]; 9378 u8 op_mod[0x10]; 9379 9380 struct mlx5_ifc_lagc_bits ctx; 9381 }; 9382 9383 struct mlx5_ifc_modify_lag_out_bits { 9384 u8 status[0x8]; 9385 u8 reserved_at_8[0x18]; 9386 9387 u8 syndrome[0x20]; 9388 9389 u8 reserved_at_40[0x40]; 9390 }; 9391 9392 struct mlx5_ifc_modify_lag_in_bits { 9393 u8 opcode[0x10]; 9394 u8 reserved_at_10[0x10]; 9395 9396 u8 reserved_at_20[0x10]; 9397 u8 op_mod[0x10]; 9398 9399 u8 reserved_at_40[0x20]; 9400 u8 field_select[0x20]; 9401 9402 struct mlx5_ifc_lagc_bits ctx; 9403 }; 9404 9405 struct mlx5_ifc_query_lag_out_bits { 9406 u8 status[0x8]; 9407 u8 reserved_at_8[0x18]; 9408 9409 u8 syndrome[0x20]; 9410 9411 u8 reserved_at_40[0x40]; 9412 9413 struct mlx5_ifc_lagc_bits ctx; 9414 }; 9415 9416 struct mlx5_ifc_query_lag_in_bits { 9417 u8 opcode[0x10]; 9418 u8 reserved_at_10[0x10]; 9419 9420 u8 reserved_at_20[0x10]; 9421 u8 op_mod[0x10]; 9422 9423 u8 reserved_at_40[0x40]; 9424 }; 9425 9426 struct mlx5_ifc_destroy_lag_out_bits { 9427 u8 status[0x8]; 9428 u8 reserved_at_8[0x18]; 9429 9430 u8 syndrome[0x20]; 9431 9432 u8 reserved_at_40[0x40]; 9433 }; 9434 9435 struct mlx5_ifc_destroy_lag_in_bits { 9436 u8 opcode[0x10]; 9437 u8 reserved_at_10[0x10]; 9438 9439 u8 reserved_at_20[0x10]; 9440 u8 op_mod[0x10]; 9441 9442 u8 reserved_at_40[0x40]; 9443 }; 9444 9445 struct mlx5_ifc_create_vport_lag_out_bits { 9446 u8 status[0x8]; 9447 u8 reserved_at_8[0x18]; 9448 9449 u8 syndrome[0x20]; 9450 9451 u8 reserved_at_40[0x40]; 9452 }; 9453 9454 struct mlx5_ifc_create_vport_lag_in_bits { 9455 u8 opcode[0x10]; 9456 u8 reserved_at_10[0x10]; 9457 9458 u8 reserved_at_20[0x10]; 9459 u8 op_mod[0x10]; 9460 9461 u8 reserved_at_40[0x40]; 9462 }; 9463 9464 struct mlx5_ifc_destroy_vport_lag_out_bits { 9465 u8 status[0x8]; 9466 u8 reserved_at_8[0x18]; 9467 9468 u8 syndrome[0x20]; 9469 9470 u8 reserved_at_40[0x40]; 9471 }; 9472 9473 struct mlx5_ifc_destroy_vport_lag_in_bits { 9474 u8 opcode[0x10]; 9475 u8 reserved_at_10[0x10]; 9476 9477 u8 reserved_at_20[0x10]; 9478 u8 op_mod[0x10]; 9479 9480 u8 reserved_at_40[0x40]; 9481 }; 9482 9483 struct mlx5_ifc_alloc_memic_in_bits { 9484 u8 opcode[0x10]; 9485 u8 reserved_at_10[0x10]; 9486 9487 u8 reserved_at_20[0x10]; 9488 u8 op_mod[0x10]; 9489 9490 u8 reserved_at_30[0x20]; 9491 9492 u8 reserved_at_40[0x18]; 9493 u8 log_memic_addr_alignment[0x8]; 9494 9495 u8 range_start_addr[0x40]; 9496 9497 u8 range_size[0x20]; 9498 9499 u8 memic_size[0x20]; 9500 }; 9501 9502 struct mlx5_ifc_alloc_memic_out_bits { 9503 u8 status[0x8]; 9504 u8 reserved_at_8[0x18]; 9505 9506 u8 syndrome[0x20]; 9507 9508 u8 memic_start_addr[0x40]; 9509 }; 9510 9511 struct mlx5_ifc_dealloc_memic_in_bits { 9512 u8 opcode[0x10]; 9513 u8 reserved_at_10[0x10]; 9514 9515 u8 reserved_at_20[0x10]; 9516 u8 op_mod[0x10]; 9517 9518 u8 reserved_at_40[0x40]; 9519 9520 u8 memic_start_addr[0x40]; 9521 9522 u8 memic_size[0x20]; 9523 9524 u8 reserved_at_e0[0x20]; 9525 }; 9526 9527 struct mlx5_ifc_dealloc_memic_out_bits { 9528 u8 status[0x8]; 9529 u8 reserved_at_8[0x18]; 9530 9531 u8 syndrome[0x20]; 9532 9533 u8 reserved_at_40[0x40]; 9534 }; 9535 9536 struct mlx5_ifc_general_obj_in_cmd_hdr_bits { 9537 u8 opcode[0x10]; 9538 u8 uid[0x10]; 9539 9540 u8 reserved_at_20[0x10]; 9541 u8 obj_type[0x10]; 9542 9543 u8 obj_id[0x20]; 9544 9545 u8 reserved_at_60[0x20]; 9546 }; 9547 9548 struct mlx5_ifc_general_obj_out_cmd_hdr_bits { 9549 u8 status[0x8]; 9550 u8 reserved_at_8[0x18]; 9551 9552 u8 syndrome[0x20]; 9553 9554 u8 obj_id[0x20]; 9555 9556 u8 reserved_at_60[0x20]; 9557 }; 9558 9559 struct mlx5_ifc_umem_bits { 9560 u8 reserved_at_0[0x80]; 9561 9562 u8 reserved_at_80[0x1b]; 9563 u8 log_page_size[0x5]; 9564 9565 u8 page_offset[0x20]; 9566 9567 u8 num_of_mtt[0x40]; 9568 9569 struct mlx5_ifc_mtt_bits mtt[0]; 9570 }; 9571 9572 struct mlx5_ifc_uctx_bits { 9573 u8 cap[0x20]; 9574 9575 u8 reserved_at_20[0x160]; 9576 }; 9577 9578 struct mlx5_ifc_sw_icm_bits { 9579 u8 modify_field_select[0x40]; 9580 9581 u8 reserved_at_40[0x18]; 9582 u8 log_sw_icm_size[0x8]; 9583 9584 u8 reserved_at_60[0x20]; 9585 9586 u8 sw_icm_start_addr[0x40]; 9587 9588 u8 reserved_at_c0[0x140]; 9589 }; 9590 9591 struct mlx5_ifc_geneve_tlv_option_bits { 9592 u8 modify_field_select[0x40]; 9593 9594 u8 reserved_at_40[0x18]; 9595 u8 geneve_option_fte_index[0x8]; 9596 9597 u8 option_class[0x10]; 9598 u8 option_type[0x8]; 9599 u8 reserved_at_78[0x3]; 9600 u8 option_data_length[0x5]; 9601 9602 u8 reserved_at_80[0x180]; 9603 }; 9604 9605 struct mlx5_ifc_create_umem_in_bits { 9606 u8 opcode[0x10]; 9607 u8 uid[0x10]; 9608 9609 u8 reserved_at_20[0x10]; 9610 u8 op_mod[0x10]; 9611 9612 u8 reserved_at_40[0x40]; 9613 9614 struct mlx5_ifc_umem_bits umem; 9615 }; 9616 9617 struct mlx5_ifc_create_uctx_in_bits { 9618 u8 opcode[0x10]; 9619 u8 reserved_at_10[0x10]; 9620 9621 u8 reserved_at_20[0x10]; 9622 u8 op_mod[0x10]; 9623 9624 u8 reserved_at_40[0x40]; 9625 9626 struct mlx5_ifc_uctx_bits uctx; 9627 }; 9628 9629 struct mlx5_ifc_destroy_uctx_in_bits { 9630 u8 opcode[0x10]; 9631 u8 reserved_at_10[0x10]; 9632 9633 u8 reserved_at_20[0x10]; 9634 u8 op_mod[0x10]; 9635 9636 u8 reserved_at_40[0x10]; 9637 u8 uid[0x10]; 9638 9639 u8 reserved_at_60[0x20]; 9640 }; 9641 9642 struct mlx5_ifc_create_sw_icm_in_bits { 9643 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 9644 struct mlx5_ifc_sw_icm_bits sw_icm; 9645 }; 9646 9647 struct mlx5_ifc_create_geneve_tlv_option_in_bits { 9648 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 9649 struct mlx5_ifc_geneve_tlv_option_bits geneve_tlv_opt; 9650 }; 9651 9652 struct mlx5_ifc_mtrc_string_db_param_bits { 9653 u8 string_db_base_address[0x20]; 9654 9655 u8 reserved_at_20[0x8]; 9656 u8 string_db_size[0x18]; 9657 }; 9658 9659 struct mlx5_ifc_mtrc_cap_bits { 9660 u8 trace_owner[0x1]; 9661 u8 trace_to_memory[0x1]; 9662 u8 reserved_at_2[0x4]; 9663 u8 trc_ver[0x2]; 9664 u8 reserved_at_8[0x14]; 9665 u8 num_string_db[0x4]; 9666 9667 u8 first_string_trace[0x8]; 9668 u8 num_string_trace[0x8]; 9669 u8 reserved_at_30[0x28]; 9670 9671 u8 log_max_trace_buffer_size[0x8]; 9672 9673 u8 reserved_at_60[0x20]; 9674 9675 struct mlx5_ifc_mtrc_string_db_param_bits string_db_param[8]; 9676 9677 u8 reserved_at_280[0x180]; 9678 }; 9679 9680 struct mlx5_ifc_mtrc_conf_bits { 9681 u8 reserved_at_0[0x1c]; 9682 u8 trace_mode[0x4]; 9683 u8 reserved_at_20[0x18]; 9684 u8 log_trace_buffer_size[0x8]; 9685 u8 trace_mkey[0x20]; 9686 u8 reserved_at_60[0x3a0]; 9687 }; 9688 9689 struct mlx5_ifc_mtrc_stdb_bits { 9690 u8 string_db_index[0x4]; 9691 u8 reserved_at_4[0x4]; 9692 u8 read_size[0x18]; 9693 u8 start_offset[0x20]; 9694 u8 string_db_data[0]; 9695 }; 9696 9697 struct mlx5_ifc_mtrc_ctrl_bits { 9698 u8 trace_status[0x2]; 9699 u8 reserved_at_2[0x2]; 9700 u8 arm_event[0x1]; 9701 u8 reserved_at_5[0xb]; 9702 u8 modify_field_select[0x10]; 9703 u8 reserved_at_20[0x2b]; 9704 u8 current_timestamp52_32[0x15]; 9705 u8 current_timestamp31_0[0x20]; 9706 u8 reserved_at_80[0x180]; 9707 }; 9708 9709 struct mlx5_ifc_host_params_context_bits { 9710 u8 host_number[0x8]; 9711 u8 reserved_at_8[0x8]; 9712 u8 host_num_of_vfs[0x10]; 9713 9714 u8 reserved_at_20[0x10]; 9715 u8 host_pci_bus[0x10]; 9716 9717 u8 reserved_at_40[0x10]; 9718 u8 host_pci_device[0x10]; 9719 9720 u8 reserved_at_60[0x10]; 9721 u8 host_pci_function[0x10]; 9722 9723 u8 reserved_at_80[0x180]; 9724 }; 9725 9726 struct mlx5_ifc_query_esw_functions_in_bits { 9727 u8 opcode[0x10]; 9728 u8 reserved_at_10[0x10]; 9729 9730 u8 reserved_at_20[0x10]; 9731 u8 op_mod[0x10]; 9732 9733 u8 reserved_at_40[0x40]; 9734 }; 9735 9736 struct mlx5_ifc_query_esw_functions_out_bits { 9737 u8 status[0x8]; 9738 u8 reserved_at_8[0x18]; 9739 9740 u8 syndrome[0x20]; 9741 9742 u8 reserved_at_40[0x40]; 9743 9744 struct mlx5_ifc_host_params_context_bits host_params_context; 9745 9746 u8 reserved_at_280[0x180]; 9747 }; 9748 9749 #endif /* MLX5_IFC_H */ 9750