1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 #ifndef MLX5_IFC_H 33 #define MLX5_IFC_H 34 35 #include "mlx5_ifc_fpga.h" 36 37 enum { 38 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0, 39 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1, 40 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2, 41 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3, 42 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13, 43 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14, 44 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c, 45 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d, 46 MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4, 47 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5, 48 MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED = 0x7, 49 MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT = 0xc, 50 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10, 51 MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR = 0x11, 52 MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR = 0x12, 53 MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR = 0x8, 54 MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE = 0x9, 55 MLX5_EVENT_TYPE_CODING_GPIO_EVENT = 0x15, 56 MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19, 57 MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a, 58 MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT = 0x1b, 59 MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT = 0x1f, 60 MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa, 61 MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb, 62 MLX5_EVENT_TYPE_CODING_FPGA_ERROR = 0x20, 63 MLX5_EVENT_TYPE_CODING_FPGA_QP_ERROR = 0x21 64 }; 65 66 enum { 67 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0, 68 MLX5_SET_HCA_CAP_OP_MOD_ETHERNET_OFFLOADS = 0x1, 69 MLX5_SET_HCA_CAP_OP_MOD_ODP = 0x2, 70 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3, 71 MLX5_SET_HCA_CAP_OP_MOD_ROCE = 0x4, 72 MLX5_SET_HCA_CAP_OP_MOD_IPSEC = 0x15, 73 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE2 = 0x20, 74 MLX5_SET_HCA_CAP_OP_MOD_PORT_SELECTION = 0x25, 75 }; 76 77 enum { 78 MLX5_SHARED_RESOURCE_UID = 0xffff, 79 }; 80 81 enum { 82 MLX5_OBJ_TYPE_SW_ICM = 0x0008, 83 MLX5_OBJ_TYPE_HEADER_MODIFY_ARGUMENT = 0x23, 84 }; 85 86 enum { 87 MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM = (1ULL << MLX5_OBJ_TYPE_SW_ICM), 88 MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT = (1ULL << 11), 89 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q = (1ULL << 13), 90 MLX5_GENERAL_OBJ_TYPES_CAP_HEADER_MODIFY_ARGUMENT = 91 (1ULL << MLX5_OBJ_TYPE_HEADER_MODIFY_ARGUMENT), 92 MLX5_GENERAL_OBJ_TYPES_CAP_MACSEC_OFFLOAD = (1ULL << 39), 93 }; 94 95 enum { 96 MLX5_OBJ_TYPE_GENEVE_TLV_OPT = 0x000b, 97 MLX5_OBJ_TYPE_VIRTIO_NET_Q = 0x000d, 98 MLX5_OBJ_TYPE_VIRTIO_Q_COUNTERS = 0x001c, 99 MLX5_OBJ_TYPE_MATCH_DEFINER = 0x0018, 100 MLX5_OBJ_TYPE_PAGE_TRACK = 0x46, 101 MLX5_OBJ_TYPE_MKEY = 0xff01, 102 MLX5_OBJ_TYPE_QP = 0xff02, 103 MLX5_OBJ_TYPE_PSV = 0xff03, 104 MLX5_OBJ_TYPE_RMP = 0xff04, 105 MLX5_OBJ_TYPE_XRC_SRQ = 0xff05, 106 MLX5_OBJ_TYPE_RQ = 0xff06, 107 MLX5_OBJ_TYPE_SQ = 0xff07, 108 MLX5_OBJ_TYPE_TIR = 0xff08, 109 MLX5_OBJ_TYPE_TIS = 0xff09, 110 MLX5_OBJ_TYPE_DCT = 0xff0a, 111 MLX5_OBJ_TYPE_XRQ = 0xff0b, 112 MLX5_OBJ_TYPE_RQT = 0xff0e, 113 MLX5_OBJ_TYPE_FLOW_COUNTER = 0xff0f, 114 MLX5_OBJ_TYPE_CQ = 0xff10, 115 }; 116 117 enum { 118 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100, 119 MLX5_CMD_OP_QUERY_ADAPTER = 0x101, 120 MLX5_CMD_OP_INIT_HCA = 0x102, 121 MLX5_CMD_OP_TEARDOWN_HCA = 0x103, 122 MLX5_CMD_OP_ENABLE_HCA = 0x104, 123 MLX5_CMD_OP_DISABLE_HCA = 0x105, 124 MLX5_CMD_OP_QUERY_PAGES = 0x107, 125 MLX5_CMD_OP_MANAGE_PAGES = 0x108, 126 MLX5_CMD_OP_SET_HCA_CAP = 0x109, 127 MLX5_CMD_OP_QUERY_ISSI = 0x10a, 128 MLX5_CMD_OP_SET_ISSI = 0x10b, 129 MLX5_CMD_OP_SET_DRIVER_VERSION = 0x10d, 130 MLX5_CMD_OP_QUERY_SF_PARTITION = 0x111, 131 MLX5_CMD_OP_ALLOC_SF = 0x113, 132 MLX5_CMD_OP_DEALLOC_SF = 0x114, 133 MLX5_CMD_OP_SUSPEND_VHCA = 0x115, 134 MLX5_CMD_OP_RESUME_VHCA = 0x116, 135 MLX5_CMD_OP_QUERY_VHCA_MIGRATION_STATE = 0x117, 136 MLX5_CMD_OP_SAVE_VHCA_STATE = 0x118, 137 MLX5_CMD_OP_LOAD_VHCA_STATE = 0x119, 138 MLX5_CMD_OP_CREATE_MKEY = 0x200, 139 MLX5_CMD_OP_QUERY_MKEY = 0x201, 140 MLX5_CMD_OP_DESTROY_MKEY = 0x202, 141 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203, 142 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204, 143 MLX5_CMD_OP_ALLOC_MEMIC = 0x205, 144 MLX5_CMD_OP_DEALLOC_MEMIC = 0x206, 145 MLX5_CMD_OP_MODIFY_MEMIC = 0x207, 146 MLX5_CMD_OP_CREATE_EQ = 0x301, 147 MLX5_CMD_OP_DESTROY_EQ = 0x302, 148 MLX5_CMD_OP_QUERY_EQ = 0x303, 149 MLX5_CMD_OP_GEN_EQE = 0x304, 150 MLX5_CMD_OP_CREATE_CQ = 0x400, 151 MLX5_CMD_OP_DESTROY_CQ = 0x401, 152 MLX5_CMD_OP_QUERY_CQ = 0x402, 153 MLX5_CMD_OP_MODIFY_CQ = 0x403, 154 MLX5_CMD_OP_CREATE_QP = 0x500, 155 MLX5_CMD_OP_DESTROY_QP = 0x501, 156 MLX5_CMD_OP_RST2INIT_QP = 0x502, 157 MLX5_CMD_OP_INIT2RTR_QP = 0x503, 158 MLX5_CMD_OP_RTR2RTS_QP = 0x504, 159 MLX5_CMD_OP_RTS2RTS_QP = 0x505, 160 MLX5_CMD_OP_SQERR2RTS_QP = 0x506, 161 MLX5_CMD_OP_2ERR_QP = 0x507, 162 MLX5_CMD_OP_2RST_QP = 0x50a, 163 MLX5_CMD_OP_QUERY_QP = 0x50b, 164 MLX5_CMD_OP_SQD_RTS_QP = 0x50c, 165 MLX5_CMD_OP_INIT2INIT_QP = 0x50e, 166 MLX5_CMD_OP_CREATE_PSV = 0x600, 167 MLX5_CMD_OP_DESTROY_PSV = 0x601, 168 MLX5_CMD_OP_CREATE_SRQ = 0x700, 169 MLX5_CMD_OP_DESTROY_SRQ = 0x701, 170 MLX5_CMD_OP_QUERY_SRQ = 0x702, 171 MLX5_CMD_OP_ARM_RQ = 0x703, 172 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705, 173 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706, 174 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707, 175 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708, 176 MLX5_CMD_OP_CREATE_DCT = 0x710, 177 MLX5_CMD_OP_DESTROY_DCT = 0x711, 178 MLX5_CMD_OP_DRAIN_DCT = 0x712, 179 MLX5_CMD_OP_QUERY_DCT = 0x713, 180 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714, 181 MLX5_CMD_OP_CREATE_XRQ = 0x717, 182 MLX5_CMD_OP_DESTROY_XRQ = 0x718, 183 MLX5_CMD_OP_QUERY_XRQ = 0x719, 184 MLX5_CMD_OP_ARM_XRQ = 0x71a, 185 MLX5_CMD_OP_QUERY_XRQ_DC_PARAMS_ENTRY = 0x725, 186 MLX5_CMD_OP_SET_XRQ_DC_PARAMS_ENTRY = 0x726, 187 MLX5_CMD_OP_QUERY_XRQ_ERROR_PARAMS = 0x727, 188 MLX5_CMD_OP_RELEASE_XRQ_ERROR = 0x729, 189 MLX5_CMD_OP_MODIFY_XRQ = 0x72a, 190 MLX5_CMD_OP_QUERY_ESW_FUNCTIONS = 0x740, 191 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750, 192 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751, 193 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752, 194 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753, 195 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754, 196 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755, 197 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760, 198 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761, 199 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762, 200 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763, 201 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764, 202 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765, 203 MLX5_CMD_OP_QUERY_VNIC_ENV = 0x76f, 204 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770, 205 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771, 206 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772, 207 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773, 208 MLX5_CMD_OP_SET_MONITOR_COUNTER = 0x774, 209 MLX5_CMD_OP_ARM_MONITOR_COUNTER = 0x775, 210 MLX5_CMD_OP_SET_PP_RATE_LIMIT = 0x780, 211 MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781, 212 MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT = 0x782, 213 MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT = 0x783, 214 MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT = 0x784, 215 MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT = 0x785, 216 MLX5_CMD_OP_CREATE_QOS_PARA_VPORT = 0x786, 217 MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT = 0x787, 218 MLX5_CMD_OP_ALLOC_PD = 0x800, 219 MLX5_CMD_OP_DEALLOC_PD = 0x801, 220 MLX5_CMD_OP_ALLOC_UAR = 0x802, 221 MLX5_CMD_OP_DEALLOC_UAR = 0x803, 222 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804, 223 MLX5_CMD_OP_ACCESS_REG = 0x805, 224 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806, 225 MLX5_CMD_OP_DETACH_FROM_MCG = 0x807, 226 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a, 227 MLX5_CMD_OP_MAD_IFC = 0x50d, 228 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b, 229 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c, 230 MLX5_CMD_OP_NOP = 0x80d, 231 MLX5_CMD_OP_ALLOC_XRCD = 0x80e, 232 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f, 233 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816, 234 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817, 235 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822, 236 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823, 237 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824, 238 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825, 239 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826, 240 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827, 241 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828, 242 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829, 243 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a, 244 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b, 245 MLX5_CMD_OP_SET_WOL_ROL = 0x830, 246 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831, 247 MLX5_CMD_OP_CREATE_LAG = 0x840, 248 MLX5_CMD_OP_MODIFY_LAG = 0x841, 249 MLX5_CMD_OP_QUERY_LAG = 0x842, 250 MLX5_CMD_OP_DESTROY_LAG = 0x843, 251 MLX5_CMD_OP_CREATE_VPORT_LAG = 0x844, 252 MLX5_CMD_OP_DESTROY_VPORT_LAG = 0x845, 253 MLX5_CMD_OP_CREATE_TIR = 0x900, 254 MLX5_CMD_OP_MODIFY_TIR = 0x901, 255 MLX5_CMD_OP_DESTROY_TIR = 0x902, 256 MLX5_CMD_OP_QUERY_TIR = 0x903, 257 MLX5_CMD_OP_CREATE_SQ = 0x904, 258 MLX5_CMD_OP_MODIFY_SQ = 0x905, 259 MLX5_CMD_OP_DESTROY_SQ = 0x906, 260 MLX5_CMD_OP_QUERY_SQ = 0x907, 261 MLX5_CMD_OP_CREATE_RQ = 0x908, 262 MLX5_CMD_OP_MODIFY_RQ = 0x909, 263 MLX5_CMD_OP_SET_DELAY_DROP_PARAMS = 0x910, 264 MLX5_CMD_OP_DESTROY_RQ = 0x90a, 265 MLX5_CMD_OP_QUERY_RQ = 0x90b, 266 MLX5_CMD_OP_CREATE_RMP = 0x90c, 267 MLX5_CMD_OP_MODIFY_RMP = 0x90d, 268 MLX5_CMD_OP_DESTROY_RMP = 0x90e, 269 MLX5_CMD_OP_QUERY_RMP = 0x90f, 270 MLX5_CMD_OP_CREATE_TIS = 0x912, 271 MLX5_CMD_OP_MODIFY_TIS = 0x913, 272 MLX5_CMD_OP_DESTROY_TIS = 0x914, 273 MLX5_CMD_OP_QUERY_TIS = 0x915, 274 MLX5_CMD_OP_CREATE_RQT = 0x916, 275 MLX5_CMD_OP_MODIFY_RQT = 0x917, 276 MLX5_CMD_OP_DESTROY_RQT = 0x918, 277 MLX5_CMD_OP_QUERY_RQT = 0x919, 278 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f, 279 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930, 280 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931, 281 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932, 282 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933, 283 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934, 284 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935, 285 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936, 286 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937, 287 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938, 288 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939, 289 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a, 290 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b, 291 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c, 292 MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT = 0x93d, 293 MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT = 0x93e, 294 MLX5_CMD_OP_QUERY_PACKET_REFORMAT_CONTEXT = 0x93f, 295 MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT = 0x940, 296 MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941, 297 MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT = 0x942, 298 MLX5_CMD_OP_FPGA_CREATE_QP = 0x960, 299 MLX5_CMD_OP_FPGA_MODIFY_QP = 0x961, 300 MLX5_CMD_OP_FPGA_QUERY_QP = 0x962, 301 MLX5_CMD_OP_FPGA_DESTROY_QP = 0x963, 302 MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS = 0x964, 303 MLX5_CMD_OP_CREATE_GENERAL_OBJECT = 0xa00, 304 MLX5_CMD_OP_MODIFY_GENERAL_OBJECT = 0xa01, 305 MLX5_CMD_OP_QUERY_GENERAL_OBJECT = 0xa02, 306 MLX5_CMD_OP_DESTROY_GENERAL_OBJECT = 0xa03, 307 MLX5_CMD_OP_CREATE_UCTX = 0xa04, 308 MLX5_CMD_OP_DESTROY_UCTX = 0xa06, 309 MLX5_CMD_OP_CREATE_UMEM = 0xa08, 310 MLX5_CMD_OP_DESTROY_UMEM = 0xa0a, 311 MLX5_CMD_OP_SYNC_STEERING = 0xb00, 312 MLX5_CMD_OP_QUERY_VHCA_STATE = 0xb0d, 313 MLX5_CMD_OP_MODIFY_VHCA_STATE = 0xb0e, 314 MLX5_CMD_OP_SYNC_CRYPTO = 0xb12, 315 MLX5_CMD_OP_ALLOW_OTHER_VHCA_ACCESS = 0xb16, 316 MLX5_CMD_OP_MAX 317 }; 318 319 /* Valid range for general commands that don't work over an object */ 320 enum { 321 MLX5_CMD_OP_GENERAL_START = 0xb00, 322 MLX5_CMD_OP_GENERAL_END = 0xd00, 323 }; 324 325 enum { 326 MLX5_FT_NIC_RX_2_NIC_RX_RDMA = BIT(0), 327 MLX5_FT_NIC_TX_RDMA_2_NIC_TX = BIT(1), 328 }; 329 330 enum { 331 MLX5_CMD_OP_MOD_UPDATE_HEADER_MODIFY_ARGUMENT = 0x1, 332 }; 333 334 struct mlx5_ifc_flow_table_fields_supported_bits { 335 u8 outer_dmac[0x1]; 336 u8 outer_smac[0x1]; 337 u8 outer_ether_type[0x1]; 338 u8 outer_ip_version[0x1]; 339 u8 outer_first_prio[0x1]; 340 u8 outer_first_cfi[0x1]; 341 u8 outer_first_vid[0x1]; 342 u8 outer_ipv4_ttl[0x1]; 343 u8 outer_second_prio[0x1]; 344 u8 outer_second_cfi[0x1]; 345 u8 outer_second_vid[0x1]; 346 u8 reserved_at_b[0x1]; 347 u8 outer_sip[0x1]; 348 u8 outer_dip[0x1]; 349 u8 outer_frag[0x1]; 350 u8 outer_ip_protocol[0x1]; 351 u8 outer_ip_ecn[0x1]; 352 u8 outer_ip_dscp[0x1]; 353 u8 outer_udp_sport[0x1]; 354 u8 outer_udp_dport[0x1]; 355 u8 outer_tcp_sport[0x1]; 356 u8 outer_tcp_dport[0x1]; 357 u8 outer_tcp_flags[0x1]; 358 u8 outer_gre_protocol[0x1]; 359 u8 outer_gre_key[0x1]; 360 u8 outer_vxlan_vni[0x1]; 361 u8 outer_geneve_vni[0x1]; 362 u8 outer_geneve_oam[0x1]; 363 u8 outer_geneve_protocol_type[0x1]; 364 u8 outer_geneve_opt_len[0x1]; 365 u8 source_vhca_port[0x1]; 366 u8 source_eswitch_port[0x1]; 367 368 u8 inner_dmac[0x1]; 369 u8 inner_smac[0x1]; 370 u8 inner_ether_type[0x1]; 371 u8 inner_ip_version[0x1]; 372 u8 inner_first_prio[0x1]; 373 u8 inner_first_cfi[0x1]; 374 u8 inner_first_vid[0x1]; 375 u8 reserved_at_27[0x1]; 376 u8 inner_second_prio[0x1]; 377 u8 inner_second_cfi[0x1]; 378 u8 inner_second_vid[0x1]; 379 u8 reserved_at_2b[0x1]; 380 u8 inner_sip[0x1]; 381 u8 inner_dip[0x1]; 382 u8 inner_frag[0x1]; 383 u8 inner_ip_protocol[0x1]; 384 u8 inner_ip_ecn[0x1]; 385 u8 inner_ip_dscp[0x1]; 386 u8 inner_udp_sport[0x1]; 387 u8 inner_udp_dport[0x1]; 388 u8 inner_tcp_sport[0x1]; 389 u8 inner_tcp_dport[0x1]; 390 u8 inner_tcp_flags[0x1]; 391 u8 reserved_at_37[0x9]; 392 393 u8 geneve_tlv_option_0_data[0x1]; 394 u8 geneve_tlv_option_0_exist[0x1]; 395 u8 reserved_at_42[0x3]; 396 u8 outer_first_mpls_over_udp[0x4]; 397 u8 outer_first_mpls_over_gre[0x4]; 398 u8 inner_first_mpls[0x4]; 399 u8 outer_first_mpls[0x4]; 400 u8 reserved_at_55[0x2]; 401 u8 outer_esp_spi[0x1]; 402 u8 reserved_at_58[0x2]; 403 u8 bth_dst_qp[0x1]; 404 u8 reserved_at_5b[0x5]; 405 406 u8 reserved_at_60[0x18]; 407 u8 metadata_reg_c_7[0x1]; 408 u8 metadata_reg_c_6[0x1]; 409 u8 metadata_reg_c_5[0x1]; 410 u8 metadata_reg_c_4[0x1]; 411 u8 metadata_reg_c_3[0x1]; 412 u8 metadata_reg_c_2[0x1]; 413 u8 metadata_reg_c_1[0x1]; 414 u8 metadata_reg_c_0[0x1]; 415 }; 416 417 /* Table 2170 - Flow Table Fields Supported 2 Format */ 418 struct mlx5_ifc_flow_table_fields_supported_2_bits { 419 u8 reserved_at_0[0x2]; 420 u8 inner_l4_type[0x1]; 421 u8 outer_l4_type[0x1]; 422 u8 reserved_at_4[0xa]; 423 u8 bth_opcode[0x1]; 424 u8 reserved_at_f[0x1]; 425 u8 tunnel_header_0_1[0x1]; 426 u8 reserved_at_11[0xf]; 427 428 u8 reserved_at_20[0x60]; 429 }; 430 431 struct mlx5_ifc_flow_table_prop_layout_bits { 432 u8 ft_support[0x1]; 433 u8 reserved_at_1[0x1]; 434 u8 flow_counter[0x1]; 435 u8 flow_modify_en[0x1]; 436 u8 modify_root[0x1]; 437 u8 identified_miss_table_mode[0x1]; 438 u8 flow_table_modify[0x1]; 439 u8 reformat[0x1]; 440 u8 decap[0x1]; 441 u8 reset_root_to_default[0x1]; 442 u8 pop_vlan[0x1]; 443 u8 push_vlan[0x1]; 444 u8 reserved_at_c[0x1]; 445 u8 pop_vlan_2[0x1]; 446 u8 push_vlan_2[0x1]; 447 u8 reformat_and_vlan_action[0x1]; 448 u8 reserved_at_10[0x1]; 449 u8 sw_owner[0x1]; 450 u8 reformat_l3_tunnel_to_l2[0x1]; 451 u8 reformat_l2_to_l3_tunnel[0x1]; 452 u8 reformat_and_modify_action[0x1]; 453 u8 ignore_flow_level[0x1]; 454 u8 reserved_at_16[0x1]; 455 u8 table_miss_action_domain[0x1]; 456 u8 termination_table[0x1]; 457 u8 reformat_and_fwd_to_table[0x1]; 458 u8 reserved_at_1a[0x2]; 459 u8 ipsec_encrypt[0x1]; 460 u8 ipsec_decrypt[0x1]; 461 u8 sw_owner_v2[0x1]; 462 u8 reserved_at_1f[0x1]; 463 464 u8 termination_table_raw_traffic[0x1]; 465 u8 reserved_at_21[0x1]; 466 u8 log_max_ft_size[0x6]; 467 u8 log_max_modify_header_context[0x8]; 468 u8 max_modify_header_actions[0x8]; 469 u8 max_ft_level[0x8]; 470 471 u8 reformat_add_esp_trasport[0x1]; 472 u8 reformat_l2_to_l3_esp_tunnel[0x1]; 473 u8 reformat_add_esp_transport_over_udp[0x1]; 474 u8 reformat_del_esp_trasport[0x1]; 475 u8 reformat_l3_esp_tunnel_to_l2[0x1]; 476 u8 reformat_del_esp_transport_over_udp[0x1]; 477 u8 execute_aso[0x1]; 478 u8 reserved_at_47[0x19]; 479 480 u8 reserved_at_60[0x2]; 481 u8 reformat_insert[0x1]; 482 u8 reformat_remove[0x1]; 483 u8 macsec_encrypt[0x1]; 484 u8 macsec_decrypt[0x1]; 485 u8 reserved_at_66[0x2]; 486 u8 reformat_add_macsec[0x1]; 487 u8 reformat_remove_macsec[0x1]; 488 u8 reserved_at_6a[0xe]; 489 u8 log_max_ft_num[0x8]; 490 491 u8 reserved_at_80[0x10]; 492 u8 log_max_flow_counter[0x8]; 493 u8 log_max_destination[0x8]; 494 495 u8 reserved_at_a0[0x18]; 496 u8 log_max_flow[0x8]; 497 498 u8 reserved_at_c0[0x40]; 499 500 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support; 501 502 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support; 503 }; 504 505 struct mlx5_ifc_odp_per_transport_service_cap_bits { 506 u8 send[0x1]; 507 u8 receive[0x1]; 508 u8 write[0x1]; 509 u8 read[0x1]; 510 u8 atomic[0x1]; 511 u8 srq_receive[0x1]; 512 u8 reserved_at_6[0x1a]; 513 }; 514 515 struct mlx5_ifc_ipv4_layout_bits { 516 u8 reserved_at_0[0x60]; 517 518 u8 ipv4[0x20]; 519 }; 520 521 struct mlx5_ifc_ipv6_layout_bits { 522 u8 ipv6[16][0x8]; 523 }; 524 525 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits { 526 struct mlx5_ifc_ipv6_layout_bits ipv6_layout; 527 struct mlx5_ifc_ipv4_layout_bits ipv4_layout; 528 u8 reserved_at_0[0x80]; 529 }; 530 531 enum { 532 MLX5_PACKET_L4_TYPE_NONE, 533 MLX5_PACKET_L4_TYPE_TCP, 534 MLX5_PACKET_L4_TYPE_UDP, 535 }; 536 537 struct mlx5_ifc_fte_match_set_lyr_2_4_bits { 538 u8 smac_47_16[0x20]; 539 540 u8 smac_15_0[0x10]; 541 u8 ethertype[0x10]; 542 543 u8 dmac_47_16[0x20]; 544 545 u8 dmac_15_0[0x10]; 546 u8 first_prio[0x3]; 547 u8 first_cfi[0x1]; 548 u8 first_vid[0xc]; 549 550 u8 ip_protocol[0x8]; 551 u8 ip_dscp[0x6]; 552 u8 ip_ecn[0x2]; 553 u8 cvlan_tag[0x1]; 554 u8 svlan_tag[0x1]; 555 u8 frag[0x1]; 556 u8 ip_version[0x4]; 557 u8 tcp_flags[0x9]; 558 559 u8 tcp_sport[0x10]; 560 u8 tcp_dport[0x10]; 561 562 u8 l4_type[0x2]; 563 u8 reserved_at_c2[0xe]; 564 u8 ipv4_ihl[0x4]; 565 u8 reserved_at_c4[0x4]; 566 567 u8 ttl_hoplimit[0x8]; 568 569 u8 udp_sport[0x10]; 570 u8 udp_dport[0x10]; 571 572 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6; 573 574 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6; 575 }; 576 577 struct mlx5_ifc_nvgre_key_bits { 578 u8 hi[0x18]; 579 u8 lo[0x8]; 580 }; 581 582 union mlx5_ifc_gre_key_bits { 583 struct mlx5_ifc_nvgre_key_bits nvgre; 584 u8 key[0x20]; 585 }; 586 587 struct mlx5_ifc_fte_match_set_misc_bits { 588 u8 gre_c_present[0x1]; 589 u8 reserved_at_1[0x1]; 590 u8 gre_k_present[0x1]; 591 u8 gre_s_present[0x1]; 592 u8 source_vhca_port[0x4]; 593 u8 source_sqn[0x18]; 594 595 u8 source_eswitch_owner_vhca_id[0x10]; 596 u8 source_port[0x10]; 597 598 u8 outer_second_prio[0x3]; 599 u8 outer_second_cfi[0x1]; 600 u8 outer_second_vid[0xc]; 601 u8 inner_second_prio[0x3]; 602 u8 inner_second_cfi[0x1]; 603 u8 inner_second_vid[0xc]; 604 605 u8 outer_second_cvlan_tag[0x1]; 606 u8 inner_second_cvlan_tag[0x1]; 607 u8 outer_second_svlan_tag[0x1]; 608 u8 inner_second_svlan_tag[0x1]; 609 u8 reserved_at_64[0xc]; 610 u8 gre_protocol[0x10]; 611 612 union mlx5_ifc_gre_key_bits gre_key; 613 614 u8 vxlan_vni[0x18]; 615 u8 bth_opcode[0x8]; 616 617 u8 geneve_vni[0x18]; 618 u8 reserved_at_d8[0x6]; 619 u8 geneve_tlv_option_0_exist[0x1]; 620 u8 geneve_oam[0x1]; 621 622 u8 reserved_at_e0[0xc]; 623 u8 outer_ipv6_flow_label[0x14]; 624 625 u8 reserved_at_100[0xc]; 626 u8 inner_ipv6_flow_label[0x14]; 627 628 u8 reserved_at_120[0xa]; 629 u8 geneve_opt_len[0x6]; 630 u8 geneve_protocol_type[0x10]; 631 632 u8 reserved_at_140[0x8]; 633 u8 bth_dst_qp[0x18]; 634 u8 inner_esp_spi[0x20]; 635 u8 outer_esp_spi[0x20]; 636 u8 reserved_at_1a0[0x60]; 637 }; 638 639 struct mlx5_ifc_fte_match_mpls_bits { 640 u8 mpls_label[0x14]; 641 u8 mpls_exp[0x3]; 642 u8 mpls_s_bos[0x1]; 643 u8 mpls_ttl[0x8]; 644 }; 645 646 struct mlx5_ifc_fte_match_set_misc2_bits { 647 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls; 648 649 struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls; 650 651 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre; 652 653 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp; 654 655 u8 metadata_reg_c_7[0x20]; 656 657 u8 metadata_reg_c_6[0x20]; 658 659 u8 metadata_reg_c_5[0x20]; 660 661 u8 metadata_reg_c_4[0x20]; 662 663 u8 metadata_reg_c_3[0x20]; 664 665 u8 metadata_reg_c_2[0x20]; 666 667 u8 metadata_reg_c_1[0x20]; 668 669 u8 metadata_reg_c_0[0x20]; 670 671 u8 metadata_reg_a[0x20]; 672 673 u8 reserved_at_1a0[0x8]; 674 675 u8 macsec_syndrome[0x8]; 676 u8 ipsec_syndrome[0x8]; 677 u8 reserved_at_1b8[0x8]; 678 679 u8 reserved_at_1c0[0x40]; 680 }; 681 682 struct mlx5_ifc_fte_match_set_misc3_bits { 683 u8 inner_tcp_seq_num[0x20]; 684 685 u8 outer_tcp_seq_num[0x20]; 686 687 u8 inner_tcp_ack_num[0x20]; 688 689 u8 outer_tcp_ack_num[0x20]; 690 691 u8 reserved_at_80[0x8]; 692 u8 outer_vxlan_gpe_vni[0x18]; 693 694 u8 outer_vxlan_gpe_next_protocol[0x8]; 695 u8 outer_vxlan_gpe_flags[0x8]; 696 u8 reserved_at_b0[0x10]; 697 698 u8 icmp_header_data[0x20]; 699 700 u8 icmpv6_header_data[0x20]; 701 702 u8 icmp_type[0x8]; 703 u8 icmp_code[0x8]; 704 u8 icmpv6_type[0x8]; 705 u8 icmpv6_code[0x8]; 706 707 u8 geneve_tlv_option_0_data[0x20]; 708 709 u8 gtpu_teid[0x20]; 710 711 u8 gtpu_msg_type[0x8]; 712 u8 gtpu_msg_flags[0x8]; 713 u8 reserved_at_170[0x10]; 714 715 u8 gtpu_dw_2[0x20]; 716 717 u8 gtpu_first_ext_dw_0[0x20]; 718 719 u8 gtpu_dw_0[0x20]; 720 721 u8 reserved_at_1e0[0x20]; 722 }; 723 724 struct mlx5_ifc_fte_match_set_misc4_bits { 725 u8 prog_sample_field_value_0[0x20]; 726 727 u8 prog_sample_field_id_0[0x20]; 728 729 u8 prog_sample_field_value_1[0x20]; 730 731 u8 prog_sample_field_id_1[0x20]; 732 733 u8 prog_sample_field_value_2[0x20]; 734 735 u8 prog_sample_field_id_2[0x20]; 736 737 u8 prog_sample_field_value_3[0x20]; 738 739 u8 prog_sample_field_id_3[0x20]; 740 741 u8 reserved_at_100[0x100]; 742 }; 743 744 struct mlx5_ifc_fte_match_set_misc5_bits { 745 u8 macsec_tag_0[0x20]; 746 747 u8 macsec_tag_1[0x20]; 748 749 u8 macsec_tag_2[0x20]; 750 751 u8 macsec_tag_3[0x20]; 752 753 u8 tunnel_header_0[0x20]; 754 755 u8 tunnel_header_1[0x20]; 756 757 u8 tunnel_header_2[0x20]; 758 759 u8 tunnel_header_3[0x20]; 760 761 u8 reserved_at_100[0x100]; 762 }; 763 764 struct mlx5_ifc_cmd_pas_bits { 765 u8 pa_h[0x20]; 766 767 u8 pa_l[0x14]; 768 u8 reserved_at_34[0xc]; 769 }; 770 771 struct mlx5_ifc_uint64_bits { 772 u8 hi[0x20]; 773 774 u8 lo[0x20]; 775 }; 776 777 enum { 778 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0, 779 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7, 780 MLX5_ADS_STAT_RATE_10GBPS = 0x8, 781 MLX5_ADS_STAT_RATE_30GBPS = 0x9, 782 MLX5_ADS_STAT_RATE_5GBPS = 0xa, 783 MLX5_ADS_STAT_RATE_20GBPS = 0xb, 784 MLX5_ADS_STAT_RATE_40GBPS = 0xc, 785 MLX5_ADS_STAT_RATE_60GBPS = 0xd, 786 MLX5_ADS_STAT_RATE_80GBPS = 0xe, 787 MLX5_ADS_STAT_RATE_120GBPS = 0xf, 788 }; 789 790 struct mlx5_ifc_ads_bits { 791 u8 fl[0x1]; 792 u8 free_ar[0x1]; 793 u8 reserved_at_2[0xe]; 794 u8 pkey_index[0x10]; 795 796 u8 reserved_at_20[0x8]; 797 u8 grh[0x1]; 798 u8 mlid[0x7]; 799 u8 rlid[0x10]; 800 801 u8 ack_timeout[0x5]; 802 u8 reserved_at_45[0x3]; 803 u8 src_addr_index[0x8]; 804 u8 reserved_at_50[0x4]; 805 u8 stat_rate[0x4]; 806 u8 hop_limit[0x8]; 807 808 u8 reserved_at_60[0x4]; 809 u8 tclass[0x8]; 810 u8 flow_label[0x14]; 811 812 u8 rgid_rip[16][0x8]; 813 814 u8 reserved_at_100[0x4]; 815 u8 f_dscp[0x1]; 816 u8 f_ecn[0x1]; 817 u8 reserved_at_106[0x1]; 818 u8 f_eth_prio[0x1]; 819 u8 ecn[0x2]; 820 u8 dscp[0x6]; 821 u8 udp_sport[0x10]; 822 823 u8 dei_cfi[0x1]; 824 u8 eth_prio[0x3]; 825 u8 sl[0x4]; 826 u8 vhca_port_num[0x8]; 827 u8 rmac_47_32[0x10]; 828 829 u8 rmac_31_0[0x20]; 830 }; 831 832 struct mlx5_ifc_flow_table_nic_cap_bits { 833 u8 nic_rx_multi_path_tirs[0x1]; 834 u8 nic_rx_multi_path_tirs_fts[0x1]; 835 u8 allow_sniffer_and_nic_rx_shared_tir[0x1]; 836 u8 reserved_at_3[0x4]; 837 u8 sw_owner_reformat_supported[0x1]; 838 u8 reserved_at_8[0x18]; 839 840 u8 encap_general_header[0x1]; 841 u8 reserved_at_21[0xa]; 842 u8 log_max_packet_reformat_context[0x5]; 843 u8 reserved_at_30[0x6]; 844 u8 max_encap_header_size[0xa]; 845 u8 reserved_at_40[0x1c0]; 846 847 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive; 848 849 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_rdma; 850 851 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer; 852 853 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit; 854 855 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_rdma; 856 857 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer; 858 859 u8 reserved_at_e00[0x600]; 860 861 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_receive; 862 863 u8 reserved_at_1480[0x80]; 864 865 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_receive_rdma; 866 867 u8 reserved_at_1580[0x280]; 868 869 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_transmit_rdma; 870 871 u8 reserved_at_1880[0x780]; 872 873 u8 sw_steering_nic_rx_action_drop_icm_address[0x40]; 874 875 u8 sw_steering_nic_tx_action_drop_icm_address[0x40]; 876 877 u8 sw_steering_nic_tx_action_allow_icm_address[0x40]; 878 879 u8 reserved_at_20c0[0x5f40]; 880 }; 881 882 struct mlx5_ifc_port_selection_cap_bits { 883 u8 reserved_at_0[0x10]; 884 u8 port_select_flow_table[0x1]; 885 u8 reserved_at_11[0x1]; 886 u8 port_select_flow_table_bypass[0x1]; 887 u8 reserved_at_13[0xd]; 888 889 u8 reserved_at_20[0x1e0]; 890 891 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_port_selection; 892 893 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_port_selection; 894 895 u8 reserved_at_480[0x7b80]; 896 }; 897 898 enum { 899 MLX5_FDB_TO_VPORT_REG_C_0 = 0x01, 900 MLX5_FDB_TO_VPORT_REG_C_1 = 0x02, 901 MLX5_FDB_TO_VPORT_REG_C_2 = 0x04, 902 MLX5_FDB_TO_VPORT_REG_C_3 = 0x08, 903 MLX5_FDB_TO_VPORT_REG_C_4 = 0x10, 904 MLX5_FDB_TO_VPORT_REG_C_5 = 0x20, 905 MLX5_FDB_TO_VPORT_REG_C_6 = 0x40, 906 MLX5_FDB_TO_VPORT_REG_C_7 = 0x80, 907 }; 908 909 struct mlx5_ifc_flow_table_eswitch_cap_bits { 910 u8 fdb_to_vport_reg_c_id[0x8]; 911 u8 reserved_at_8[0x5]; 912 u8 fdb_uplink_hairpin[0x1]; 913 u8 fdb_multi_path_any_table_limit_regc[0x1]; 914 u8 reserved_at_f[0x3]; 915 u8 fdb_multi_path_any_table[0x1]; 916 u8 reserved_at_13[0x2]; 917 u8 fdb_modify_header_fwd_to_table[0x1]; 918 u8 fdb_ipv4_ttl_modify[0x1]; 919 u8 flow_source[0x1]; 920 u8 reserved_at_18[0x2]; 921 u8 multi_fdb_encap[0x1]; 922 u8 egress_acl_forward_to_vport[0x1]; 923 u8 fdb_multi_path_to_table[0x1]; 924 u8 reserved_at_1d[0x3]; 925 926 u8 reserved_at_20[0x1e0]; 927 928 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb; 929 930 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress; 931 932 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress; 933 934 u8 reserved_at_800[0xC00]; 935 936 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_esw_fdb; 937 938 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_bitmask_support_2_esw_fdb; 939 940 u8 reserved_at_1500[0x300]; 941 942 u8 sw_steering_fdb_action_drop_icm_address_rx[0x40]; 943 944 u8 sw_steering_fdb_action_drop_icm_address_tx[0x40]; 945 946 u8 sw_steering_uplink_icm_address_rx[0x40]; 947 948 u8 sw_steering_uplink_icm_address_tx[0x40]; 949 950 u8 reserved_at_1900[0x6700]; 951 }; 952 953 enum { 954 MLX5_COUNTER_SOURCE_ESWITCH = 0x0, 955 MLX5_COUNTER_FLOW_ESWITCH = 0x1, 956 }; 957 958 struct mlx5_ifc_e_switch_cap_bits { 959 u8 vport_svlan_strip[0x1]; 960 u8 vport_cvlan_strip[0x1]; 961 u8 vport_svlan_insert[0x1]; 962 u8 vport_cvlan_insert_if_not_exist[0x1]; 963 u8 vport_cvlan_insert_overwrite[0x1]; 964 u8 reserved_at_5[0x1]; 965 u8 vport_cvlan_insert_always[0x1]; 966 u8 esw_shared_ingress_acl[0x1]; 967 u8 esw_uplink_ingress_acl[0x1]; 968 u8 root_ft_on_other_esw[0x1]; 969 u8 reserved_at_a[0xf]; 970 u8 esw_functions_changed[0x1]; 971 u8 reserved_at_1a[0x1]; 972 u8 ecpf_vport_exists[0x1]; 973 u8 counter_eswitch_affinity[0x1]; 974 u8 merged_eswitch[0x1]; 975 u8 nic_vport_node_guid_modify[0x1]; 976 u8 nic_vport_port_guid_modify[0x1]; 977 978 u8 vxlan_encap_decap[0x1]; 979 u8 nvgre_encap_decap[0x1]; 980 u8 reserved_at_22[0x1]; 981 u8 log_max_fdb_encap_uplink[0x5]; 982 u8 reserved_at_21[0x3]; 983 u8 log_max_packet_reformat_context[0x5]; 984 u8 reserved_2b[0x6]; 985 u8 max_encap_header_size[0xa]; 986 987 u8 reserved_at_40[0xb]; 988 u8 log_max_esw_sf[0x5]; 989 u8 esw_sf_base_id[0x10]; 990 991 u8 reserved_at_60[0x7a0]; 992 993 }; 994 995 struct mlx5_ifc_qos_cap_bits { 996 u8 packet_pacing[0x1]; 997 u8 esw_scheduling[0x1]; 998 u8 esw_bw_share[0x1]; 999 u8 esw_rate_limit[0x1]; 1000 u8 reserved_at_4[0x1]; 1001 u8 packet_pacing_burst_bound[0x1]; 1002 u8 packet_pacing_typical_size[0x1]; 1003 u8 reserved_at_7[0x1]; 1004 u8 nic_sq_scheduling[0x1]; 1005 u8 nic_bw_share[0x1]; 1006 u8 nic_rate_limit[0x1]; 1007 u8 packet_pacing_uid[0x1]; 1008 u8 log_esw_max_sched_depth[0x4]; 1009 u8 reserved_at_10[0x10]; 1010 1011 u8 reserved_at_20[0xb]; 1012 u8 log_max_qos_nic_queue_group[0x5]; 1013 u8 reserved_at_30[0x10]; 1014 1015 u8 packet_pacing_max_rate[0x20]; 1016 1017 u8 packet_pacing_min_rate[0x20]; 1018 1019 u8 reserved_at_80[0x10]; 1020 u8 packet_pacing_rate_table_size[0x10]; 1021 1022 u8 esw_element_type[0x10]; 1023 u8 esw_tsar_type[0x10]; 1024 1025 u8 reserved_at_c0[0x10]; 1026 u8 max_qos_para_vport[0x10]; 1027 1028 u8 max_tsar_bw_share[0x20]; 1029 1030 u8 reserved_at_100[0x20]; 1031 1032 u8 reserved_at_120[0x3]; 1033 u8 log_meter_aso_granularity[0x5]; 1034 u8 reserved_at_128[0x3]; 1035 u8 log_meter_aso_max_alloc[0x5]; 1036 u8 reserved_at_130[0x3]; 1037 u8 log_max_num_meter_aso[0x5]; 1038 u8 reserved_at_138[0x8]; 1039 1040 u8 reserved_at_140[0x6c0]; 1041 }; 1042 1043 struct mlx5_ifc_debug_cap_bits { 1044 u8 core_dump_general[0x1]; 1045 u8 core_dump_qp[0x1]; 1046 u8 reserved_at_2[0x7]; 1047 u8 resource_dump[0x1]; 1048 u8 reserved_at_a[0x16]; 1049 1050 u8 reserved_at_20[0x2]; 1051 u8 stall_detect[0x1]; 1052 u8 reserved_at_23[0x1d]; 1053 1054 u8 reserved_at_40[0x7c0]; 1055 }; 1056 1057 struct mlx5_ifc_per_protocol_networking_offload_caps_bits { 1058 u8 csum_cap[0x1]; 1059 u8 vlan_cap[0x1]; 1060 u8 lro_cap[0x1]; 1061 u8 lro_psh_flag[0x1]; 1062 u8 lro_time_stamp[0x1]; 1063 u8 reserved_at_5[0x2]; 1064 u8 wqe_vlan_insert[0x1]; 1065 u8 self_lb_en_modifiable[0x1]; 1066 u8 reserved_at_9[0x2]; 1067 u8 max_lso_cap[0x5]; 1068 u8 multi_pkt_send_wqe[0x2]; 1069 u8 wqe_inline_mode[0x2]; 1070 u8 rss_ind_tbl_cap[0x4]; 1071 u8 reg_umr_sq[0x1]; 1072 u8 scatter_fcs[0x1]; 1073 u8 enhanced_multi_pkt_send_wqe[0x1]; 1074 u8 tunnel_lso_const_out_ip_id[0x1]; 1075 u8 tunnel_lro_gre[0x1]; 1076 u8 tunnel_lro_vxlan[0x1]; 1077 u8 tunnel_stateless_gre[0x1]; 1078 u8 tunnel_stateless_vxlan[0x1]; 1079 1080 u8 swp[0x1]; 1081 u8 swp_csum[0x1]; 1082 u8 swp_lso[0x1]; 1083 u8 cqe_checksum_full[0x1]; 1084 u8 tunnel_stateless_geneve_tx[0x1]; 1085 u8 tunnel_stateless_mpls_over_udp[0x1]; 1086 u8 tunnel_stateless_mpls_over_gre[0x1]; 1087 u8 tunnel_stateless_vxlan_gpe[0x1]; 1088 u8 tunnel_stateless_ipv4_over_vxlan[0x1]; 1089 u8 tunnel_stateless_ip_over_ip[0x1]; 1090 u8 insert_trailer[0x1]; 1091 u8 reserved_at_2b[0x1]; 1092 u8 tunnel_stateless_ip_over_ip_rx[0x1]; 1093 u8 tunnel_stateless_ip_over_ip_tx[0x1]; 1094 u8 reserved_at_2e[0x2]; 1095 u8 max_vxlan_udp_ports[0x8]; 1096 u8 swp_csum_l4_partial[0x1]; 1097 u8 reserved_at_39[0x5]; 1098 u8 max_geneve_opt_len[0x1]; 1099 u8 tunnel_stateless_geneve_rx[0x1]; 1100 1101 u8 reserved_at_40[0x10]; 1102 u8 lro_min_mss_size[0x10]; 1103 1104 u8 reserved_at_60[0x120]; 1105 1106 u8 lro_timer_supported_periods[4][0x20]; 1107 1108 u8 reserved_at_200[0x600]; 1109 }; 1110 1111 enum { 1112 MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING = 0x0, 1113 MLX5_TIMESTAMP_FORMAT_CAP_REAL_TIME = 0x1, 1114 MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING_AND_REAL_TIME = 0x2, 1115 }; 1116 1117 struct mlx5_ifc_roce_cap_bits { 1118 u8 roce_apm[0x1]; 1119 u8 reserved_at_1[0x3]; 1120 u8 sw_r_roce_src_udp_port[0x1]; 1121 u8 fl_rc_qp_when_roce_disabled[0x1]; 1122 u8 fl_rc_qp_when_roce_enabled[0x1]; 1123 u8 roce_cc_general[0x1]; 1124 u8 qp_ooo_transmit_default[0x1]; 1125 u8 reserved_at_9[0x15]; 1126 u8 qp_ts_format[0x2]; 1127 1128 u8 reserved_at_20[0x60]; 1129 1130 u8 reserved_at_80[0xc]; 1131 u8 l3_type[0x4]; 1132 u8 reserved_at_90[0x8]; 1133 u8 roce_version[0x8]; 1134 1135 u8 reserved_at_a0[0x10]; 1136 u8 r_roce_dest_udp_port[0x10]; 1137 1138 u8 r_roce_max_src_udp_port[0x10]; 1139 u8 r_roce_min_src_udp_port[0x10]; 1140 1141 u8 reserved_at_e0[0x10]; 1142 u8 roce_address_table_size[0x10]; 1143 1144 u8 reserved_at_100[0x700]; 1145 }; 1146 1147 struct mlx5_ifc_sync_steering_in_bits { 1148 u8 opcode[0x10]; 1149 u8 uid[0x10]; 1150 1151 u8 reserved_at_20[0x10]; 1152 u8 op_mod[0x10]; 1153 1154 u8 reserved_at_40[0xc0]; 1155 }; 1156 1157 struct mlx5_ifc_sync_steering_out_bits { 1158 u8 status[0x8]; 1159 u8 reserved_at_8[0x18]; 1160 1161 u8 syndrome[0x20]; 1162 1163 u8 reserved_at_40[0x40]; 1164 }; 1165 1166 struct mlx5_ifc_sync_crypto_in_bits { 1167 u8 opcode[0x10]; 1168 u8 uid[0x10]; 1169 1170 u8 reserved_at_20[0x10]; 1171 u8 op_mod[0x10]; 1172 1173 u8 reserved_at_40[0x20]; 1174 1175 u8 reserved_at_60[0x10]; 1176 u8 crypto_type[0x10]; 1177 1178 u8 reserved_at_80[0x80]; 1179 }; 1180 1181 struct mlx5_ifc_sync_crypto_out_bits { 1182 u8 status[0x8]; 1183 u8 reserved_at_8[0x18]; 1184 1185 u8 syndrome[0x20]; 1186 1187 u8 reserved_at_40[0x40]; 1188 }; 1189 1190 struct mlx5_ifc_device_mem_cap_bits { 1191 u8 memic[0x1]; 1192 u8 reserved_at_1[0x1f]; 1193 1194 u8 reserved_at_20[0xb]; 1195 u8 log_min_memic_alloc_size[0x5]; 1196 u8 reserved_at_30[0x8]; 1197 u8 log_max_memic_addr_alignment[0x8]; 1198 1199 u8 memic_bar_start_addr[0x40]; 1200 1201 u8 memic_bar_size[0x20]; 1202 1203 u8 max_memic_size[0x20]; 1204 1205 u8 steering_sw_icm_start_address[0x40]; 1206 1207 u8 reserved_at_100[0x8]; 1208 u8 log_header_modify_sw_icm_size[0x8]; 1209 u8 reserved_at_110[0x2]; 1210 u8 log_sw_icm_alloc_granularity[0x6]; 1211 u8 log_steering_sw_icm_size[0x8]; 1212 1213 u8 log_indirect_encap_sw_icm_size[0x8]; 1214 u8 reserved_at_128[0x10]; 1215 u8 log_header_modify_pattern_sw_icm_size[0x8]; 1216 1217 u8 header_modify_sw_icm_start_address[0x40]; 1218 1219 u8 reserved_at_180[0x40]; 1220 1221 u8 header_modify_pattern_sw_icm_start_address[0x40]; 1222 1223 u8 memic_operations[0x20]; 1224 1225 u8 reserved_at_220[0x20]; 1226 1227 u8 indirect_encap_sw_icm_start_address[0x40]; 1228 1229 u8 reserved_at_280[0x580]; 1230 }; 1231 1232 struct mlx5_ifc_device_event_cap_bits { 1233 u8 user_affiliated_events[4][0x40]; 1234 1235 u8 user_unaffiliated_events[4][0x40]; 1236 }; 1237 1238 struct mlx5_ifc_virtio_emulation_cap_bits { 1239 u8 desc_tunnel_offload_type[0x1]; 1240 u8 eth_frame_offload_type[0x1]; 1241 u8 virtio_version_1_0[0x1]; 1242 u8 device_features_bits_mask[0xd]; 1243 u8 event_mode[0x8]; 1244 u8 virtio_queue_type[0x8]; 1245 1246 u8 max_tunnel_desc[0x10]; 1247 u8 reserved_at_30[0x3]; 1248 u8 log_doorbell_stride[0x5]; 1249 u8 reserved_at_38[0x3]; 1250 u8 log_doorbell_bar_size[0x5]; 1251 1252 u8 doorbell_bar_offset[0x40]; 1253 1254 u8 max_emulated_devices[0x8]; 1255 u8 max_num_virtio_queues[0x18]; 1256 1257 u8 reserved_at_a0[0x20]; 1258 1259 u8 reserved_at_c0[0x13]; 1260 u8 desc_group_mkey_supported[0x1]; 1261 u8 freeze_to_rdy_supported[0x1]; 1262 u8 reserved_at_d5[0xb]; 1263 1264 u8 reserved_at_e0[0x20]; 1265 1266 u8 umem_1_buffer_param_a[0x20]; 1267 1268 u8 umem_1_buffer_param_b[0x20]; 1269 1270 u8 umem_2_buffer_param_a[0x20]; 1271 1272 u8 umem_2_buffer_param_b[0x20]; 1273 1274 u8 umem_3_buffer_param_a[0x20]; 1275 1276 u8 umem_3_buffer_param_b[0x20]; 1277 1278 u8 reserved_at_1c0[0x640]; 1279 }; 1280 1281 enum { 1282 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0, 1283 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2, 1284 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4, 1285 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8, 1286 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10, 1287 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20, 1288 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40, 1289 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80, 1290 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100, 1291 }; 1292 1293 enum { 1294 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1, 1295 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2, 1296 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4, 1297 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8, 1298 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10, 1299 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20, 1300 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40, 1301 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80, 1302 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100, 1303 }; 1304 1305 struct mlx5_ifc_atomic_caps_bits { 1306 u8 reserved_at_0[0x40]; 1307 1308 u8 atomic_req_8B_endianness_mode[0x2]; 1309 u8 reserved_at_42[0x4]; 1310 u8 supported_atomic_req_8B_endianness_mode_1[0x1]; 1311 1312 u8 reserved_at_47[0x19]; 1313 1314 u8 reserved_at_60[0x20]; 1315 1316 u8 reserved_at_80[0x10]; 1317 u8 atomic_operations[0x10]; 1318 1319 u8 reserved_at_a0[0x10]; 1320 u8 atomic_size_qp[0x10]; 1321 1322 u8 reserved_at_c0[0x10]; 1323 u8 atomic_size_dc[0x10]; 1324 1325 u8 reserved_at_e0[0x720]; 1326 }; 1327 1328 struct mlx5_ifc_odp_cap_bits { 1329 u8 reserved_at_0[0x40]; 1330 1331 u8 sig[0x1]; 1332 u8 reserved_at_41[0x1f]; 1333 1334 u8 reserved_at_60[0x20]; 1335 1336 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps; 1337 1338 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps; 1339 1340 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps; 1341 1342 struct mlx5_ifc_odp_per_transport_service_cap_bits xrc_odp_caps; 1343 1344 struct mlx5_ifc_odp_per_transport_service_cap_bits dc_odp_caps; 1345 1346 u8 reserved_at_120[0x6E0]; 1347 }; 1348 1349 struct mlx5_ifc_tls_cap_bits { 1350 u8 tls_1_2_aes_gcm_128[0x1]; 1351 u8 tls_1_3_aes_gcm_128[0x1]; 1352 u8 tls_1_2_aes_gcm_256[0x1]; 1353 u8 tls_1_3_aes_gcm_256[0x1]; 1354 u8 reserved_at_4[0x1c]; 1355 1356 u8 reserved_at_20[0x7e0]; 1357 }; 1358 1359 struct mlx5_ifc_ipsec_cap_bits { 1360 u8 ipsec_full_offload[0x1]; 1361 u8 ipsec_crypto_offload[0x1]; 1362 u8 ipsec_esn[0x1]; 1363 u8 ipsec_crypto_esp_aes_gcm_256_encrypt[0x1]; 1364 u8 ipsec_crypto_esp_aes_gcm_128_encrypt[0x1]; 1365 u8 ipsec_crypto_esp_aes_gcm_256_decrypt[0x1]; 1366 u8 ipsec_crypto_esp_aes_gcm_128_decrypt[0x1]; 1367 u8 reserved_at_7[0x4]; 1368 u8 log_max_ipsec_offload[0x5]; 1369 u8 reserved_at_10[0x10]; 1370 1371 u8 min_log_ipsec_full_replay_window[0x8]; 1372 u8 max_log_ipsec_full_replay_window[0x8]; 1373 u8 reserved_at_30[0x7d0]; 1374 }; 1375 1376 struct mlx5_ifc_macsec_cap_bits { 1377 u8 macsec_epn[0x1]; 1378 u8 reserved_at_1[0x2]; 1379 u8 macsec_crypto_esp_aes_gcm_256_encrypt[0x1]; 1380 u8 macsec_crypto_esp_aes_gcm_128_encrypt[0x1]; 1381 u8 macsec_crypto_esp_aes_gcm_256_decrypt[0x1]; 1382 u8 macsec_crypto_esp_aes_gcm_128_decrypt[0x1]; 1383 u8 reserved_at_7[0x4]; 1384 u8 log_max_macsec_offload[0x5]; 1385 u8 reserved_at_10[0x10]; 1386 1387 u8 min_log_macsec_full_replay_window[0x8]; 1388 u8 max_log_macsec_full_replay_window[0x8]; 1389 u8 reserved_at_30[0x10]; 1390 1391 u8 reserved_at_40[0x7c0]; 1392 }; 1393 1394 enum { 1395 MLX5_WQ_TYPE_LINKED_LIST = 0x0, 1396 MLX5_WQ_TYPE_CYCLIC = 0x1, 1397 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2, 1398 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3, 1399 }; 1400 1401 enum { 1402 MLX5_WQ_END_PAD_MODE_NONE = 0x0, 1403 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1, 1404 }; 1405 1406 enum { 1407 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0, 1408 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1, 1409 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2, 1410 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3, 1411 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4, 1412 }; 1413 1414 enum { 1415 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0, 1416 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1, 1417 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2, 1418 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3, 1419 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4, 1420 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5, 1421 }; 1422 1423 enum { 1424 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0, 1425 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1, 1426 }; 1427 1428 enum { 1429 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0, 1430 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1, 1431 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3, 1432 }; 1433 1434 enum { 1435 MLX5_CAP_PORT_TYPE_IB = 0x0, 1436 MLX5_CAP_PORT_TYPE_ETH = 0x1, 1437 }; 1438 1439 enum { 1440 MLX5_CAP_UMR_FENCE_STRONG = 0x0, 1441 MLX5_CAP_UMR_FENCE_SMALL = 0x1, 1442 MLX5_CAP_UMR_FENCE_NONE = 0x2, 1443 }; 1444 1445 enum { 1446 MLX5_FLEX_PARSER_GENEVE_ENABLED = 1 << 3, 1447 MLX5_FLEX_PARSER_MPLS_OVER_GRE_ENABLED = 1 << 4, 1448 MLX5_FLEX_PARSER_MPLS_OVER_UDP_ENABLED = 1 << 5, 1449 MLX5_FLEX_PARSER_VXLAN_GPE_ENABLED = 1 << 7, 1450 MLX5_FLEX_PARSER_ICMP_V4_ENABLED = 1 << 8, 1451 MLX5_FLEX_PARSER_ICMP_V6_ENABLED = 1 << 9, 1452 MLX5_FLEX_PARSER_GENEVE_TLV_OPTION_0_ENABLED = 1 << 10, 1453 MLX5_FLEX_PARSER_GTPU_ENABLED = 1 << 11, 1454 MLX5_FLEX_PARSER_GTPU_DW_2_ENABLED = 1 << 16, 1455 MLX5_FLEX_PARSER_GTPU_FIRST_EXT_DW_0_ENABLED = 1 << 17, 1456 MLX5_FLEX_PARSER_GTPU_DW_0_ENABLED = 1 << 18, 1457 MLX5_FLEX_PARSER_GTPU_TEID_ENABLED = 1 << 19, 1458 }; 1459 1460 enum { 1461 MLX5_UCTX_CAP_RAW_TX = 1UL << 0, 1462 MLX5_UCTX_CAP_INTERNAL_DEV_RES = 1UL << 1, 1463 }; 1464 1465 #define MLX5_FC_BULK_SIZE_FACTOR 128 1466 1467 enum mlx5_fc_bulk_alloc_bitmask { 1468 MLX5_FC_BULK_128 = (1 << 0), 1469 MLX5_FC_BULK_256 = (1 << 1), 1470 MLX5_FC_BULK_512 = (1 << 2), 1471 MLX5_FC_BULK_1024 = (1 << 3), 1472 MLX5_FC_BULK_2048 = (1 << 4), 1473 MLX5_FC_BULK_4096 = (1 << 5), 1474 MLX5_FC_BULK_8192 = (1 << 6), 1475 MLX5_FC_BULK_16384 = (1 << 7), 1476 }; 1477 1478 #define MLX5_FC_BULK_NUM_FCS(fc_enum) (MLX5_FC_BULK_SIZE_FACTOR * (fc_enum)) 1479 1480 #define MLX5_FT_MAX_MULTIPATH_LEVEL 63 1481 1482 enum { 1483 MLX5_STEERING_FORMAT_CONNECTX_5 = 0, 1484 MLX5_STEERING_FORMAT_CONNECTX_6DX = 1, 1485 MLX5_STEERING_FORMAT_CONNECTX_7 = 2, 1486 }; 1487 1488 struct mlx5_ifc_cmd_hca_cap_bits { 1489 u8 reserved_at_0[0x6]; 1490 u8 page_request_disable[0x1]; 1491 u8 reserved_at_7[0x9]; 1492 u8 shared_object_to_user_object_allowed[0x1]; 1493 u8 reserved_at_13[0xe]; 1494 u8 vhca_resource_manager[0x1]; 1495 1496 u8 hca_cap_2[0x1]; 1497 u8 create_lag_when_not_master_up[0x1]; 1498 u8 dtor[0x1]; 1499 u8 event_on_vhca_state_teardown_request[0x1]; 1500 u8 event_on_vhca_state_in_use[0x1]; 1501 u8 event_on_vhca_state_active[0x1]; 1502 u8 event_on_vhca_state_allocated[0x1]; 1503 u8 event_on_vhca_state_invalid[0x1]; 1504 u8 reserved_at_28[0x8]; 1505 u8 vhca_id[0x10]; 1506 1507 u8 reserved_at_40[0x40]; 1508 1509 u8 log_max_srq_sz[0x8]; 1510 u8 log_max_qp_sz[0x8]; 1511 u8 event_cap[0x1]; 1512 u8 reserved_at_91[0x2]; 1513 u8 isolate_vl_tc_new[0x1]; 1514 u8 reserved_at_94[0x4]; 1515 u8 prio_tag_required[0x1]; 1516 u8 reserved_at_99[0x2]; 1517 u8 log_max_qp[0x5]; 1518 1519 u8 reserved_at_a0[0x3]; 1520 u8 ece_support[0x1]; 1521 u8 reserved_at_a4[0x5]; 1522 u8 reg_c_preserve[0x1]; 1523 u8 reserved_at_aa[0x1]; 1524 u8 log_max_srq[0x5]; 1525 u8 reserved_at_b0[0x1]; 1526 u8 uplink_follow[0x1]; 1527 u8 ts_cqe_to_dest_cqn[0x1]; 1528 u8 reserved_at_b3[0x6]; 1529 u8 go_back_n[0x1]; 1530 u8 reserved_at_ba[0x6]; 1531 1532 u8 max_sgl_for_optimized_performance[0x8]; 1533 u8 log_max_cq_sz[0x8]; 1534 u8 relaxed_ordering_write_umr[0x1]; 1535 u8 relaxed_ordering_read_umr[0x1]; 1536 u8 reserved_at_d2[0x7]; 1537 u8 virtio_net_device_emualtion_manager[0x1]; 1538 u8 virtio_blk_device_emualtion_manager[0x1]; 1539 u8 log_max_cq[0x5]; 1540 1541 u8 log_max_eq_sz[0x8]; 1542 u8 relaxed_ordering_write[0x1]; 1543 u8 relaxed_ordering_read_pci_enabled[0x1]; 1544 u8 log_max_mkey[0x6]; 1545 u8 reserved_at_f0[0x6]; 1546 u8 terminate_scatter_list_mkey[0x1]; 1547 u8 repeated_mkey[0x1]; 1548 u8 dump_fill_mkey[0x1]; 1549 u8 reserved_at_f9[0x2]; 1550 u8 fast_teardown[0x1]; 1551 u8 log_max_eq[0x4]; 1552 1553 u8 max_indirection[0x8]; 1554 u8 fixed_buffer_size[0x1]; 1555 u8 log_max_mrw_sz[0x7]; 1556 u8 force_teardown[0x1]; 1557 u8 reserved_at_111[0x1]; 1558 u8 log_max_bsf_list_size[0x6]; 1559 u8 umr_extended_translation_offset[0x1]; 1560 u8 null_mkey[0x1]; 1561 u8 log_max_klm_list_size[0x6]; 1562 1563 u8 reserved_at_120[0x2]; 1564 u8 qpc_extension[0x1]; 1565 u8 reserved_at_123[0x7]; 1566 u8 log_max_ra_req_dc[0x6]; 1567 u8 reserved_at_130[0x2]; 1568 u8 eth_wqe_too_small[0x1]; 1569 u8 reserved_at_133[0x6]; 1570 u8 vnic_env_cq_overrun[0x1]; 1571 u8 log_max_ra_res_dc[0x6]; 1572 1573 u8 reserved_at_140[0x5]; 1574 u8 release_all_pages[0x1]; 1575 u8 must_not_use[0x1]; 1576 u8 reserved_at_147[0x2]; 1577 u8 roce_accl[0x1]; 1578 u8 log_max_ra_req_qp[0x6]; 1579 u8 reserved_at_150[0xa]; 1580 u8 log_max_ra_res_qp[0x6]; 1581 1582 u8 end_pad[0x1]; 1583 u8 cc_query_allowed[0x1]; 1584 u8 cc_modify_allowed[0x1]; 1585 u8 start_pad[0x1]; 1586 u8 cache_line_128byte[0x1]; 1587 u8 reserved_at_165[0x4]; 1588 u8 rts2rts_qp_counters_set_id[0x1]; 1589 u8 reserved_at_16a[0x2]; 1590 u8 vnic_env_int_rq_oob[0x1]; 1591 u8 sbcam_reg[0x1]; 1592 u8 reserved_at_16e[0x1]; 1593 u8 qcam_reg[0x1]; 1594 u8 gid_table_size[0x10]; 1595 1596 u8 out_of_seq_cnt[0x1]; 1597 u8 vport_counters[0x1]; 1598 u8 retransmission_q_counters[0x1]; 1599 u8 debug[0x1]; 1600 u8 modify_rq_counter_set_id[0x1]; 1601 u8 rq_delay_drop[0x1]; 1602 u8 max_qp_cnt[0xa]; 1603 u8 pkey_table_size[0x10]; 1604 1605 u8 vport_group_manager[0x1]; 1606 u8 vhca_group_manager[0x1]; 1607 u8 ib_virt[0x1]; 1608 u8 eth_virt[0x1]; 1609 u8 vnic_env_queue_counters[0x1]; 1610 u8 ets[0x1]; 1611 u8 nic_flow_table[0x1]; 1612 u8 eswitch_manager[0x1]; 1613 u8 device_memory[0x1]; 1614 u8 mcam_reg[0x1]; 1615 u8 pcam_reg[0x1]; 1616 u8 local_ca_ack_delay[0x5]; 1617 u8 port_module_event[0x1]; 1618 u8 enhanced_error_q_counters[0x1]; 1619 u8 ports_check[0x1]; 1620 u8 reserved_at_1b3[0x1]; 1621 u8 disable_link_up[0x1]; 1622 u8 beacon_led[0x1]; 1623 u8 port_type[0x2]; 1624 u8 num_ports[0x8]; 1625 1626 u8 reserved_at_1c0[0x1]; 1627 u8 pps[0x1]; 1628 u8 pps_modify[0x1]; 1629 u8 log_max_msg[0x5]; 1630 u8 reserved_at_1c8[0x4]; 1631 u8 max_tc[0x4]; 1632 u8 temp_warn_event[0x1]; 1633 u8 dcbx[0x1]; 1634 u8 general_notification_event[0x1]; 1635 u8 reserved_at_1d3[0x2]; 1636 u8 fpga[0x1]; 1637 u8 rol_s[0x1]; 1638 u8 rol_g[0x1]; 1639 u8 reserved_at_1d8[0x1]; 1640 u8 wol_s[0x1]; 1641 u8 wol_g[0x1]; 1642 u8 wol_a[0x1]; 1643 u8 wol_b[0x1]; 1644 u8 wol_m[0x1]; 1645 u8 wol_u[0x1]; 1646 u8 wol_p[0x1]; 1647 1648 u8 stat_rate_support[0x10]; 1649 u8 reserved_at_1f0[0x1]; 1650 u8 pci_sync_for_fw_update_event[0x1]; 1651 u8 reserved_at_1f2[0x6]; 1652 u8 init2_lag_tx_port_affinity[0x1]; 1653 u8 reserved_at_1fa[0x3]; 1654 u8 cqe_version[0x4]; 1655 1656 u8 compact_address_vector[0x1]; 1657 u8 striding_rq[0x1]; 1658 u8 reserved_at_202[0x1]; 1659 u8 ipoib_enhanced_offloads[0x1]; 1660 u8 ipoib_basic_offloads[0x1]; 1661 u8 reserved_at_205[0x1]; 1662 u8 repeated_block_disabled[0x1]; 1663 u8 umr_modify_entity_size_disabled[0x1]; 1664 u8 umr_modify_atomic_disabled[0x1]; 1665 u8 umr_indirect_mkey_disabled[0x1]; 1666 u8 umr_fence[0x2]; 1667 u8 dc_req_scat_data_cqe[0x1]; 1668 u8 reserved_at_20d[0x2]; 1669 u8 drain_sigerr[0x1]; 1670 u8 cmdif_checksum[0x2]; 1671 u8 sigerr_cqe[0x1]; 1672 u8 reserved_at_213[0x1]; 1673 u8 wq_signature[0x1]; 1674 u8 sctr_data_cqe[0x1]; 1675 u8 reserved_at_216[0x1]; 1676 u8 sho[0x1]; 1677 u8 tph[0x1]; 1678 u8 rf[0x1]; 1679 u8 dct[0x1]; 1680 u8 qos[0x1]; 1681 u8 eth_net_offloads[0x1]; 1682 u8 roce[0x1]; 1683 u8 atomic[0x1]; 1684 u8 reserved_at_21f[0x1]; 1685 1686 u8 cq_oi[0x1]; 1687 u8 cq_resize[0x1]; 1688 u8 cq_moderation[0x1]; 1689 u8 cq_period_mode_modify[0x1]; 1690 u8 reserved_at_224[0x2]; 1691 u8 cq_eq_remap[0x1]; 1692 u8 pg[0x1]; 1693 u8 block_lb_mc[0x1]; 1694 u8 reserved_at_229[0x1]; 1695 u8 scqe_break_moderation[0x1]; 1696 u8 cq_period_start_from_cqe[0x1]; 1697 u8 cd[0x1]; 1698 u8 reserved_at_22d[0x1]; 1699 u8 apm[0x1]; 1700 u8 vector_calc[0x1]; 1701 u8 umr_ptr_rlky[0x1]; 1702 u8 imaicl[0x1]; 1703 u8 qp_packet_based[0x1]; 1704 u8 reserved_at_233[0x3]; 1705 u8 qkv[0x1]; 1706 u8 pkv[0x1]; 1707 u8 set_deth_sqpn[0x1]; 1708 u8 reserved_at_239[0x3]; 1709 u8 xrc[0x1]; 1710 u8 ud[0x1]; 1711 u8 uc[0x1]; 1712 u8 rc[0x1]; 1713 1714 u8 uar_4k[0x1]; 1715 u8 reserved_at_241[0x7]; 1716 u8 fl_rc_qp_when_roce_disabled[0x1]; 1717 u8 regexp_params[0x1]; 1718 u8 uar_sz[0x6]; 1719 u8 port_selection_cap[0x1]; 1720 u8 reserved_at_251[0x1]; 1721 u8 umem_uid_0[0x1]; 1722 u8 reserved_at_253[0x5]; 1723 u8 log_pg_sz[0x8]; 1724 1725 u8 bf[0x1]; 1726 u8 driver_version[0x1]; 1727 u8 pad_tx_eth_packet[0x1]; 1728 u8 reserved_at_263[0x3]; 1729 u8 mkey_by_name[0x1]; 1730 u8 reserved_at_267[0x4]; 1731 1732 u8 log_bf_reg_size[0x5]; 1733 1734 u8 reserved_at_270[0x3]; 1735 u8 qp_error_syndrome[0x1]; 1736 u8 reserved_at_274[0x2]; 1737 u8 lag_dct[0x2]; 1738 u8 lag_tx_port_affinity[0x1]; 1739 u8 lag_native_fdb_selection[0x1]; 1740 u8 reserved_at_27a[0x1]; 1741 u8 lag_master[0x1]; 1742 u8 num_lag_ports[0x4]; 1743 1744 u8 reserved_at_280[0x10]; 1745 u8 max_wqe_sz_sq[0x10]; 1746 1747 u8 reserved_at_2a0[0xb]; 1748 u8 shampo[0x1]; 1749 u8 reserved_at_2ac[0x4]; 1750 u8 max_wqe_sz_rq[0x10]; 1751 1752 u8 max_flow_counter_31_16[0x10]; 1753 u8 max_wqe_sz_sq_dc[0x10]; 1754 1755 u8 reserved_at_2e0[0x7]; 1756 u8 max_qp_mcg[0x19]; 1757 1758 u8 reserved_at_300[0x10]; 1759 u8 flow_counter_bulk_alloc[0x8]; 1760 u8 log_max_mcg[0x8]; 1761 1762 u8 reserved_at_320[0x3]; 1763 u8 log_max_transport_domain[0x5]; 1764 u8 reserved_at_328[0x2]; 1765 u8 relaxed_ordering_read[0x1]; 1766 u8 log_max_pd[0x5]; 1767 u8 reserved_at_330[0x6]; 1768 u8 pci_sync_for_fw_update_with_driver_unload[0x1]; 1769 u8 vnic_env_cnt_steering_fail[0x1]; 1770 u8 vport_counter_local_loopback[0x1]; 1771 u8 q_counter_aggregation[0x1]; 1772 u8 q_counter_other_vport[0x1]; 1773 u8 log_max_xrcd[0x5]; 1774 1775 u8 nic_receive_steering_discard[0x1]; 1776 u8 receive_discard_vport_down[0x1]; 1777 u8 transmit_discard_vport_down[0x1]; 1778 u8 eq_overrun_count[0x1]; 1779 u8 reserved_at_344[0x1]; 1780 u8 invalid_command_count[0x1]; 1781 u8 quota_exceeded_count[0x1]; 1782 u8 reserved_at_347[0x1]; 1783 u8 log_max_flow_counter_bulk[0x8]; 1784 u8 max_flow_counter_15_0[0x10]; 1785 1786 1787 u8 reserved_at_360[0x3]; 1788 u8 log_max_rq[0x5]; 1789 u8 reserved_at_368[0x3]; 1790 u8 log_max_sq[0x5]; 1791 u8 reserved_at_370[0x3]; 1792 u8 log_max_tir[0x5]; 1793 u8 reserved_at_378[0x3]; 1794 u8 log_max_tis[0x5]; 1795 1796 u8 basic_cyclic_rcv_wqe[0x1]; 1797 u8 reserved_at_381[0x2]; 1798 u8 log_max_rmp[0x5]; 1799 u8 reserved_at_388[0x3]; 1800 u8 log_max_rqt[0x5]; 1801 u8 reserved_at_390[0x3]; 1802 u8 log_max_rqt_size[0x5]; 1803 u8 reserved_at_398[0x3]; 1804 u8 log_max_tis_per_sq[0x5]; 1805 1806 u8 ext_stride_num_range[0x1]; 1807 u8 roce_rw_supported[0x1]; 1808 u8 log_max_current_uc_list_wr_supported[0x1]; 1809 u8 log_max_stride_sz_rq[0x5]; 1810 u8 reserved_at_3a8[0x3]; 1811 u8 log_min_stride_sz_rq[0x5]; 1812 u8 reserved_at_3b0[0x3]; 1813 u8 log_max_stride_sz_sq[0x5]; 1814 u8 reserved_at_3b8[0x3]; 1815 u8 log_min_stride_sz_sq[0x5]; 1816 1817 u8 hairpin[0x1]; 1818 u8 reserved_at_3c1[0x2]; 1819 u8 log_max_hairpin_queues[0x5]; 1820 u8 reserved_at_3c8[0x3]; 1821 u8 log_max_hairpin_wq_data_sz[0x5]; 1822 u8 reserved_at_3d0[0x3]; 1823 u8 log_max_hairpin_num_packets[0x5]; 1824 u8 reserved_at_3d8[0x3]; 1825 u8 log_max_wq_sz[0x5]; 1826 1827 u8 nic_vport_change_event[0x1]; 1828 u8 disable_local_lb_uc[0x1]; 1829 u8 disable_local_lb_mc[0x1]; 1830 u8 log_min_hairpin_wq_data_sz[0x5]; 1831 u8 reserved_at_3e8[0x1]; 1832 u8 silent_mode[0x1]; 1833 u8 vhca_state[0x1]; 1834 u8 log_max_vlan_list[0x5]; 1835 u8 reserved_at_3f0[0x3]; 1836 u8 log_max_current_mc_list[0x5]; 1837 u8 reserved_at_3f8[0x3]; 1838 u8 log_max_current_uc_list[0x5]; 1839 1840 u8 general_obj_types[0x40]; 1841 1842 u8 sq_ts_format[0x2]; 1843 u8 rq_ts_format[0x2]; 1844 u8 steering_format_version[0x4]; 1845 u8 create_qp_start_hint[0x18]; 1846 1847 u8 reserved_at_460[0x1]; 1848 u8 ats[0x1]; 1849 u8 cross_vhca_rqt[0x1]; 1850 u8 log_max_uctx[0x5]; 1851 u8 reserved_at_468[0x1]; 1852 u8 crypto[0x1]; 1853 u8 ipsec_offload[0x1]; 1854 u8 log_max_umem[0x5]; 1855 u8 max_num_eqs[0x10]; 1856 1857 u8 reserved_at_480[0x1]; 1858 u8 tls_tx[0x1]; 1859 u8 tls_rx[0x1]; 1860 u8 log_max_l2_table[0x5]; 1861 u8 reserved_at_488[0x8]; 1862 u8 log_uar_page_sz[0x10]; 1863 1864 u8 reserved_at_4a0[0x20]; 1865 u8 device_frequency_mhz[0x20]; 1866 u8 device_frequency_khz[0x20]; 1867 1868 u8 reserved_at_500[0x20]; 1869 u8 num_of_uars_per_page[0x20]; 1870 1871 u8 flex_parser_protocols[0x20]; 1872 1873 u8 max_geneve_tlv_options[0x8]; 1874 u8 reserved_at_568[0x3]; 1875 u8 max_geneve_tlv_option_data_len[0x5]; 1876 u8 reserved_at_570[0x9]; 1877 u8 adv_virtualization[0x1]; 1878 u8 reserved_at_57a[0x6]; 1879 1880 u8 reserved_at_580[0xb]; 1881 u8 log_max_dci_stream_channels[0x5]; 1882 u8 reserved_at_590[0x3]; 1883 u8 log_max_dci_errored_streams[0x5]; 1884 u8 reserved_at_598[0x8]; 1885 1886 u8 reserved_at_5a0[0x10]; 1887 u8 enhanced_cqe_compression[0x1]; 1888 u8 reserved_at_5b1[0x2]; 1889 u8 log_max_dek[0x5]; 1890 u8 reserved_at_5b8[0x4]; 1891 u8 mini_cqe_resp_stride_index[0x1]; 1892 u8 cqe_128_always[0x1]; 1893 u8 cqe_compression_128[0x1]; 1894 u8 cqe_compression[0x1]; 1895 1896 u8 cqe_compression_timeout[0x10]; 1897 u8 cqe_compression_max_num[0x10]; 1898 1899 u8 reserved_at_5e0[0x8]; 1900 u8 flex_parser_id_gtpu_dw_0[0x4]; 1901 u8 reserved_at_5ec[0x4]; 1902 u8 tag_matching[0x1]; 1903 u8 rndv_offload_rc[0x1]; 1904 u8 rndv_offload_dc[0x1]; 1905 u8 log_tag_matching_list_sz[0x5]; 1906 u8 reserved_at_5f8[0x3]; 1907 u8 log_max_xrq[0x5]; 1908 1909 u8 affiliate_nic_vport_criteria[0x8]; 1910 u8 native_port_num[0x8]; 1911 u8 num_vhca_ports[0x8]; 1912 u8 flex_parser_id_gtpu_teid[0x4]; 1913 u8 reserved_at_61c[0x2]; 1914 u8 sw_owner_id[0x1]; 1915 u8 reserved_at_61f[0x1]; 1916 1917 u8 max_num_of_monitor_counters[0x10]; 1918 u8 num_ppcnt_monitor_counters[0x10]; 1919 1920 u8 max_num_sf[0x10]; 1921 u8 num_q_monitor_counters[0x10]; 1922 1923 u8 reserved_at_660[0x20]; 1924 1925 u8 sf[0x1]; 1926 u8 sf_set_partition[0x1]; 1927 u8 reserved_at_682[0x1]; 1928 u8 log_max_sf[0x5]; 1929 u8 apu[0x1]; 1930 u8 reserved_at_689[0x4]; 1931 u8 migration[0x1]; 1932 u8 reserved_at_68e[0x2]; 1933 u8 log_min_sf_size[0x8]; 1934 u8 max_num_sf_partitions[0x8]; 1935 1936 u8 uctx_cap[0x20]; 1937 1938 u8 reserved_at_6c0[0x4]; 1939 u8 flex_parser_id_geneve_tlv_option_0[0x4]; 1940 u8 flex_parser_id_icmp_dw1[0x4]; 1941 u8 flex_parser_id_icmp_dw0[0x4]; 1942 u8 flex_parser_id_icmpv6_dw1[0x4]; 1943 u8 flex_parser_id_icmpv6_dw0[0x4]; 1944 u8 flex_parser_id_outer_first_mpls_over_gre[0x4]; 1945 u8 flex_parser_id_outer_first_mpls_over_udp_label[0x4]; 1946 1947 u8 max_num_match_definer[0x10]; 1948 u8 sf_base_id[0x10]; 1949 1950 u8 flex_parser_id_gtpu_dw_2[0x4]; 1951 u8 flex_parser_id_gtpu_first_ext_dw_0[0x4]; 1952 u8 num_total_dynamic_vf_msix[0x18]; 1953 u8 reserved_at_720[0x14]; 1954 u8 dynamic_msix_table_size[0xc]; 1955 u8 reserved_at_740[0xc]; 1956 u8 min_dynamic_vf_msix_table_size[0x4]; 1957 u8 reserved_at_750[0x4]; 1958 u8 max_dynamic_vf_msix_table_size[0xc]; 1959 1960 u8 reserved_at_760[0x3]; 1961 u8 log_max_num_header_modify_argument[0x5]; 1962 u8 reserved_at_768[0x4]; 1963 u8 log_header_modify_argument_granularity[0x4]; 1964 u8 reserved_at_770[0x3]; 1965 u8 log_header_modify_argument_max_alloc[0x5]; 1966 u8 reserved_at_778[0x8]; 1967 1968 u8 vhca_tunnel_commands[0x40]; 1969 u8 match_definer_format_supported[0x40]; 1970 }; 1971 1972 enum { 1973 MLX5_CROSS_VHCA_OBJ_TO_OBJ_SUPPORTED_LOCAL_FLOW_TABLE_TO_REMOTE_FLOW_TABLE_MISS = 0x80000, 1974 MLX5_CROSS_VHCA_OBJ_TO_OBJ_SUPPORTED_LOCAL_FLOW_TABLE_ROOT_TO_REMOTE_FLOW_TABLE = (1ULL << 20), 1975 }; 1976 1977 enum { 1978 MLX5_ALLOWED_OBJ_FOR_OTHER_VHCA_ACCESS_FLOW_TABLE = 0x200, 1979 }; 1980 1981 struct mlx5_ifc_cmd_hca_cap_2_bits { 1982 u8 reserved_at_0[0x80]; 1983 1984 u8 migratable[0x1]; 1985 u8 reserved_at_81[0x1f]; 1986 1987 u8 max_reformat_insert_size[0x8]; 1988 u8 max_reformat_insert_offset[0x8]; 1989 u8 max_reformat_remove_size[0x8]; 1990 u8 max_reformat_remove_offset[0x8]; 1991 1992 u8 reserved_at_c0[0x8]; 1993 u8 migration_multi_load[0x1]; 1994 u8 migration_tracking_state[0x1]; 1995 u8 reserved_at_ca[0x6]; 1996 u8 migration_in_chunks[0x1]; 1997 u8 reserved_at_d1[0xf]; 1998 1999 u8 cross_vhca_object_to_object_supported[0x20]; 2000 2001 u8 allowed_object_for_other_vhca_access[0x40]; 2002 2003 u8 reserved_at_140[0x60]; 2004 2005 u8 flow_table_type_2_type[0x8]; 2006 u8 reserved_at_1a8[0x3]; 2007 u8 log_min_mkey_entity_size[0x5]; 2008 u8 reserved_at_1b0[0x10]; 2009 2010 u8 reserved_at_1c0[0x60]; 2011 2012 u8 reserved_at_220[0x1]; 2013 u8 sw_vhca_id_valid[0x1]; 2014 u8 sw_vhca_id[0xe]; 2015 u8 reserved_at_230[0x10]; 2016 2017 u8 reserved_at_240[0xb]; 2018 u8 ts_cqe_metadata_size2wqe_counter[0x5]; 2019 u8 reserved_at_250[0x10]; 2020 2021 u8 reserved_at_260[0x120]; 2022 u8 reserved_at_380[0xb]; 2023 u8 min_mkey_log_entity_size_fixed_buffer[0x5]; 2024 u8 ec_vf_vport_base[0x10]; 2025 2026 u8 reserved_at_3a0[0x10]; 2027 u8 max_rqt_vhca_id[0x10]; 2028 2029 u8 reserved_at_3c0[0x20]; 2030 2031 u8 reserved_at_3e0[0x10]; 2032 u8 pcc_ifa2[0x1]; 2033 u8 reserved_at_3f1[0xf]; 2034 2035 u8 reserved_at_400[0x1]; 2036 u8 min_mkey_log_entity_size_fixed_buffer_valid[0x1]; 2037 u8 reserved_at_402[0x1e]; 2038 2039 u8 reserved_at_420[0x3e0]; 2040 }; 2041 2042 enum mlx5_ifc_flow_destination_type { 2043 MLX5_IFC_FLOW_DESTINATION_TYPE_VPORT = 0x0, 2044 MLX5_IFC_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1, 2045 MLX5_IFC_FLOW_DESTINATION_TYPE_TIR = 0x2, 2046 MLX5_IFC_FLOW_DESTINATION_TYPE_FLOW_SAMPLER = 0x6, 2047 MLX5_IFC_FLOW_DESTINATION_TYPE_UPLINK = 0x8, 2048 MLX5_IFC_FLOW_DESTINATION_TYPE_TABLE_TYPE = 0xA, 2049 }; 2050 2051 enum mlx5_flow_table_miss_action { 2052 MLX5_FLOW_TABLE_MISS_ACTION_DEF, 2053 MLX5_FLOW_TABLE_MISS_ACTION_FWD, 2054 MLX5_FLOW_TABLE_MISS_ACTION_SWITCH_DOMAIN, 2055 }; 2056 2057 struct mlx5_ifc_dest_format_struct_bits { 2058 u8 destination_type[0x8]; 2059 u8 destination_id[0x18]; 2060 2061 u8 destination_eswitch_owner_vhca_id_valid[0x1]; 2062 u8 packet_reformat[0x1]; 2063 u8 reserved_at_22[0x6]; 2064 u8 destination_table_type[0x8]; 2065 u8 destination_eswitch_owner_vhca_id[0x10]; 2066 }; 2067 2068 struct mlx5_ifc_flow_counter_list_bits { 2069 u8 flow_counter_id[0x20]; 2070 2071 u8 reserved_at_20[0x20]; 2072 }; 2073 2074 struct mlx5_ifc_extended_dest_format_bits { 2075 struct mlx5_ifc_dest_format_struct_bits destination_entry; 2076 2077 u8 packet_reformat_id[0x20]; 2078 2079 u8 reserved_at_60[0x20]; 2080 }; 2081 2082 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits { 2083 struct mlx5_ifc_extended_dest_format_bits extended_dest_format; 2084 struct mlx5_ifc_flow_counter_list_bits flow_counter_list; 2085 }; 2086 2087 struct mlx5_ifc_fte_match_param_bits { 2088 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers; 2089 2090 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters; 2091 2092 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers; 2093 2094 struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2; 2095 2096 struct mlx5_ifc_fte_match_set_misc3_bits misc_parameters_3; 2097 2098 struct mlx5_ifc_fte_match_set_misc4_bits misc_parameters_4; 2099 2100 struct mlx5_ifc_fte_match_set_misc5_bits misc_parameters_5; 2101 2102 u8 reserved_at_e00[0x200]; 2103 }; 2104 2105 enum { 2106 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0, 2107 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1, 2108 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2, 2109 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3, 2110 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4, 2111 }; 2112 2113 struct mlx5_ifc_rx_hash_field_select_bits { 2114 u8 l3_prot_type[0x1]; 2115 u8 l4_prot_type[0x1]; 2116 u8 selected_fields[0x1e]; 2117 }; 2118 2119 enum { 2120 MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0, 2121 MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1, 2122 }; 2123 2124 enum { 2125 MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0, 2126 MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1, 2127 }; 2128 2129 struct mlx5_ifc_wq_bits { 2130 u8 wq_type[0x4]; 2131 u8 wq_signature[0x1]; 2132 u8 end_padding_mode[0x2]; 2133 u8 cd_slave[0x1]; 2134 u8 reserved_at_8[0x18]; 2135 2136 u8 hds_skip_first_sge[0x1]; 2137 u8 log2_hds_buf_size[0x3]; 2138 u8 reserved_at_24[0x7]; 2139 u8 page_offset[0x5]; 2140 u8 lwm[0x10]; 2141 2142 u8 reserved_at_40[0x8]; 2143 u8 pd[0x18]; 2144 2145 u8 reserved_at_60[0x8]; 2146 u8 uar_page[0x18]; 2147 2148 u8 dbr_addr[0x40]; 2149 2150 u8 hw_counter[0x20]; 2151 2152 u8 sw_counter[0x20]; 2153 2154 u8 reserved_at_100[0xc]; 2155 u8 log_wq_stride[0x4]; 2156 u8 reserved_at_110[0x3]; 2157 u8 log_wq_pg_sz[0x5]; 2158 u8 reserved_at_118[0x3]; 2159 u8 log_wq_sz[0x5]; 2160 2161 u8 dbr_umem_valid[0x1]; 2162 u8 wq_umem_valid[0x1]; 2163 u8 reserved_at_122[0x1]; 2164 u8 log_hairpin_num_packets[0x5]; 2165 u8 reserved_at_128[0x3]; 2166 u8 log_hairpin_data_sz[0x5]; 2167 2168 u8 reserved_at_130[0x4]; 2169 u8 log_wqe_num_of_strides[0x4]; 2170 u8 two_byte_shift_en[0x1]; 2171 u8 reserved_at_139[0x4]; 2172 u8 log_wqe_stride_size[0x3]; 2173 2174 u8 reserved_at_140[0x80]; 2175 2176 u8 headers_mkey[0x20]; 2177 2178 u8 shampo_enable[0x1]; 2179 u8 reserved_at_1e1[0x4]; 2180 u8 log_reservation_size[0x3]; 2181 u8 reserved_at_1e8[0x5]; 2182 u8 log_max_num_of_packets_per_reservation[0x3]; 2183 u8 reserved_at_1f0[0x6]; 2184 u8 log_headers_entry_size[0x2]; 2185 u8 reserved_at_1f8[0x4]; 2186 u8 log_headers_buffer_entry_num[0x4]; 2187 2188 u8 reserved_at_200[0x400]; 2189 2190 struct mlx5_ifc_cmd_pas_bits pas[]; 2191 }; 2192 2193 struct mlx5_ifc_rq_num_bits { 2194 u8 reserved_at_0[0x8]; 2195 u8 rq_num[0x18]; 2196 }; 2197 2198 struct mlx5_ifc_rq_vhca_bits { 2199 u8 reserved_at_0[0x8]; 2200 u8 rq_num[0x18]; 2201 u8 reserved_at_20[0x10]; 2202 u8 rq_vhca_id[0x10]; 2203 }; 2204 2205 struct mlx5_ifc_mac_address_layout_bits { 2206 u8 reserved_at_0[0x10]; 2207 u8 mac_addr_47_32[0x10]; 2208 2209 u8 mac_addr_31_0[0x20]; 2210 }; 2211 2212 struct mlx5_ifc_vlan_layout_bits { 2213 u8 reserved_at_0[0x14]; 2214 u8 vlan[0x0c]; 2215 2216 u8 reserved_at_20[0x20]; 2217 }; 2218 2219 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits { 2220 u8 reserved_at_0[0xa0]; 2221 2222 u8 min_time_between_cnps[0x20]; 2223 2224 u8 reserved_at_c0[0x12]; 2225 u8 cnp_dscp[0x6]; 2226 u8 reserved_at_d8[0x4]; 2227 u8 cnp_prio_mode[0x1]; 2228 u8 cnp_802p_prio[0x3]; 2229 2230 u8 reserved_at_e0[0x720]; 2231 }; 2232 2233 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits { 2234 u8 reserved_at_0[0x60]; 2235 2236 u8 reserved_at_60[0x4]; 2237 u8 clamp_tgt_rate[0x1]; 2238 u8 reserved_at_65[0x3]; 2239 u8 clamp_tgt_rate_after_time_inc[0x1]; 2240 u8 reserved_at_69[0x17]; 2241 2242 u8 reserved_at_80[0x20]; 2243 2244 u8 rpg_time_reset[0x20]; 2245 2246 u8 rpg_byte_reset[0x20]; 2247 2248 u8 rpg_threshold[0x20]; 2249 2250 u8 rpg_max_rate[0x20]; 2251 2252 u8 rpg_ai_rate[0x20]; 2253 2254 u8 rpg_hai_rate[0x20]; 2255 2256 u8 rpg_gd[0x20]; 2257 2258 u8 rpg_min_dec_fac[0x20]; 2259 2260 u8 rpg_min_rate[0x20]; 2261 2262 u8 reserved_at_1c0[0xe0]; 2263 2264 u8 rate_to_set_on_first_cnp[0x20]; 2265 2266 u8 dce_tcp_g[0x20]; 2267 2268 u8 dce_tcp_rtt[0x20]; 2269 2270 u8 rate_reduce_monitor_period[0x20]; 2271 2272 u8 reserved_at_320[0x20]; 2273 2274 u8 initial_alpha_value[0x20]; 2275 2276 u8 reserved_at_360[0x4a0]; 2277 }; 2278 2279 struct mlx5_ifc_cong_control_r_roce_general_bits { 2280 u8 reserved_at_0[0x80]; 2281 2282 u8 reserved_at_80[0x10]; 2283 u8 rtt_resp_dscp_valid[0x1]; 2284 u8 reserved_at_91[0x9]; 2285 u8 rtt_resp_dscp[0x6]; 2286 2287 u8 reserved_at_a0[0x760]; 2288 }; 2289 2290 struct mlx5_ifc_cong_control_802_1qau_rp_bits { 2291 u8 reserved_at_0[0x80]; 2292 2293 u8 rppp_max_rps[0x20]; 2294 2295 u8 rpg_time_reset[0x20]; 2296 2297 u8 rpg_byte_reset[0x20]; 2298 2299 u8 rpg_threshold[0x20]; 2300 2301 u8 rpg_max_rate[0x20]; 2302 2303 u8 rpg_ai_rate[0x20]; 2304 2305 u8 rpg_hai_rate[0x20]; 2306 2307 u8 rpg_gd[0x20]; 2308 2309 u8 rpg_min_dec_fac[0x20]; 2310 2311 u8 rpg_min_rate[0x20]; 2312 2313 u8 reserved_at_1c0[0x640]; 2314 }; 2315 2316 enum { 2317 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1, 2318 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2, 2319 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4, 2320 }; 2321 2322 struct mlx5_ifc_resize_field_select_bits { 2323 u8 resize_field_select[0x20]; 2324 }; 2325 2326 struct mlx5_ifc_resource_dump_bits { 2327 u8 more_dump[0x1]; 2328 u8 inline_dump[0x1]; 2329 u8 reserved_at_2[0xa]; 2330 u8 seq_num[0x4]; 2331 u8 segment_type[0x10]; 2332 2333 u8 reserved_at_20[0x10]; 2334 u8 vhca_id[0x10]; 2335 2336 u8 index1[0x20]; 2337 2338 u8 index2[0x20]; 2339 2340 u8 num_of_obj1[0x10]; 2341 u8 num_of_obj2[0x10]; 2342 2343 u8 reserved_at_a0[0x20]; 2344 2345 u8 device_opaque[0x40]; 2346 2347 u8 mkey[0x20]; 2348 2349 u8 size[0x20]; 2350 2351 u8 address[0x40]; 2352 2353 u8 inline_data[52][0x20]; 2354 }; 2355 2356 struct mlx5_ifc_resource_dump_menu_record_bits { 2357 u8 reserved_at_0[0x4]; 2358 u8 num_of_obj2_supports_active[0x1]; 2359 u8 num_of_obj2_supports_all[0x1]; 2360 u8 must_have_num_of_obj2[0x1]; 2361 u8 support_num_of_obj2[0x1]; 2362 u8 num_of_obj1_supports_active[0x1]; 2363 u8 num_of_obj1_supports_all[0x1]; 2364 u8 must_have_num_of_obj1[0x1]; 2365 u8 support_num_of_obj1[0x1]; 2366 u8 must_have_index2[0x1]; 2367 u8 support_index2[0x1]; 2368 u8 must_have_index1[0x1]; 2369 u8 support_index1[0x1]; 2370 u8 segment_type[0x10]; 2371 2372 u8 segment_name[4][0x20]; 2373 2374 u8 index1_name[4][0x20]; 2375 2376 u8 index2_name[4][0x20]; 2377 }; 2378 2379 struct mlx5_ifc_resource_dump_segment_header_bits { 2380 u8 length_dw[0x10]; 2381 u8 segment_type[0x10]; 2382 }; 2383 2384 struct mlx5_ifc_resource_dump_command_segment_bits { 2385 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2386 2387 u8 segment_called[0x10]; 2388 u8 vhca_id[0x10]; 2389 2390 u8 index1[0x20]; 2391 2392 u8 index2[0x20]; 2393 2394 u8 num_of_obj1[0x10]; 2395 u8 num_of_obj2[0x10]; 2396 }; 2397 2398 struct mlx5_ifc_resource_dump_error_segment_bits { 2399 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2400 2401 u8 reserved_at_20[0x10]; 2402 u8 syndrome_id[0x10]; 2403 2404 u8 reserved_at_40[0x40]; 2405 2406 u8 error[8][0x20]; 2407 }; 2408 2409 struct mlx5_ifc_resource_dump_info_segment_bits { 2410 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2411 2412 u8 reserved_at_20[0x18]; 2413 u8 dump_version[0x8]; 2414 2415 u8 hw_version[0x20]; 2416 2417 u8 fw_version[0x20]; 2418 }; 2419 2420 struct mlx5_ifc_resource_dump_menu_segment_bits { 2421 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2422 2423 u8 reserved_at_20[0x10]; 2424 u8 num_of_records[0x10]; 2425 2426 struct mlx5_ifc_resource_dump_menu_record_bits record[]; 2427 }; 2428 2429 struct mlx5_ifc_resource_dump_resource_segment_bits { 2430 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2431 2432 u8 reserved_at_20[0x20]; 2433 2434 u8 index1[0x20]; 2435 2436 u8 index2[0x20]; 2437 2438 u8 payload[][0x20]; 2439 }; 2440 2441 struct mlx5_ifc_resource_dump_terminate_segment_bits { 2442 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2443 }; 2444 2445 struct mlx5_ifc_menu_resource_dump_response_bits { 2446 struct mlx5_ifc_resource_dump_info_segment_bits info; 2447 struct mlx5_ifc_resource_dump_command_segment_bits cmd; 2448 struct mlx5_ifc_resource_dump_menu_segment_bits menu; 2449 struct mlx5_ifc_resource_dump_terminate_segment_bits terminate; 2450 }; 2451 2452 enum { 2453 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1, 2454 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2, 2455 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4, 2456 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8, 2457 }; 2458 2459 struct mlx5_ifc_modify_field_select_bits { 2460 u8 modify_field_select[0x20]; 2461 }; 2462 2463 struct mlx5_ifc_field_select_r_roce_np_bits { 2464 u8 field_select_r_roce_np[0x20]; 2465 }; 2466 2467 struct mlx5_ifc_field_select_r_roce_rp_bits { 2468 u8 field_select_r_roce_rp[0x20]; 2469 }; 2470 2471 enum { 2472 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4, 2473 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8, 2474 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10, 2475 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20, 2476 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40, 2477 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80, 2478 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100, 2479 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200, 2480 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400, 2481 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800, 2482 }; 2483 2484 struct mlx5_ifc_field_select_802_1qau_rp_bits { 2485 u8 field_select_8021qaurp[0x20]; 2486 }; 2487 2488 struct mlx5_ifc_phys_layer_cntrs_bits { 2489 u8 time_since_last_clear_high[0x20]; 2490 2491 u8 time_since_last_clear_low[0x20]; 2492 2493 u8 symbol_errors_high[0x20]; 2494 2495 u8 symbol_errors_low[0x20]; 2496 2497 u8 sync_headers_errors_high[0x20]; 2498 2499 u8 sync_headers_errors_low[0x20]; 2500 2501 u8 edpl_bip_errors_lane0_high[0x20]; 2502 2503 u8 edpl_bip_errors_lane0_low[0x20]; 2504 2505 u8 edpl_bip_errors_lane1_high[0x20]; 2506 2507 u8 edpl_bip_errors_lane1_low[0x20]; 2508 2509 u8 edpl_bip_errors_lane2_high[0x20]; 2510 2511 u8 edpl_bip_errors_lane2_low[0x20]; 2512 2513 u8 edpl_bip_errors_lane3_high[0x20]; 2514 2515 u8 edpl_bip_errors_lane3_low[0x20]; 2516 2517 u8 fc_fec_corrected_blocks_lane0_high[0x20]; 2518 2519 u8 fc_fec_corrected_blocks_lane0_low[0x20]; 2520 2521 u8 fc_fec_corrected_blocks_lane1_high[0x20]; 2522 2523 u8 fc_fec_corrected_blocks_lane1_low[0x20]; 2524 2525 u8 fc_fec_corrected_blocks_lane2_high[0x20]; 2526 2527 u8 fc_fec_corrected_blocks_lane2_low[0x20]; 2528 2529 u8 fc_fec_corrected_blocks_lane3_high[0x20]; 2530 2531 u8 fc_fec_corrected_blocks_lane3_low[0x20]; 2532 2533 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20]; 2534 2535 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20]; 2536 2537 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20]; 2538 2539 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20]; 2540 2541 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20]; 2542 2543 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20]; 2544 2545 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20]; 2546 2547 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20]; 2548 2549 u8 rs_fec_corrected_blocks_high[0x20]; 2550 2551 u8 rs_fec_corrected_blocks_low[0x20]; 2552 2553 u8 rs_fec_uncorrectable_blocks_high[0x20]; 2554 2555 u8 rs_fec_uncorrectable_blocks_low[0x20]; 2556 2557 u8 rs_fec_no_errors_blocks_high[0x20]; 2558 2559 u8 rs_fec_no_errors_blocks_low[0x20]; 2560 2561 u8 rs_fec_single_error_blocks_high[0x20]; 2562 2563 u8 rs_fec_single_error_blocks_low[0x20]; 2564 2565 u8 rs_fec_corrected_symbols_total_high[0x20]; 2566 2567 u8 rs_fec_corrected_symbols_total_low[0x20]; 2568 2569 u8 rs_fec_corrected_symbols_lane0_high[0x20]; 2570 2571 u8 rs_fec_corrected_symbols_lane0_low[0x20]; 2572 2573 u8 rs_fec_corrected_symbols_lane1_high[0x20]; 2574 2575 u8 rs_fec_corrected_symbols_lane1_low[0x20]; 2576 2577 u8 rs_fec_corrected_symbols_lane2_high[0x20]; 2578 2579 u8 rs_fec_corrected_symbols_lane2_low[0x20]; 2580 2581 u8 rs_fec_corrected_symbols_lane3_high[0x20]; 2582 2583 u8 rs_fec_corrected_symbols_lane3_low[0x20]; 2584 2585 u8 link_down_events[0x20]; 2586 2587 u8 successful_recovery_events[0x20]; 2588 2589 u8 reserved_at_640[0x180]; 2590 }; 2591 2592 struct mlx5_ifc_phys_layer_statistical_cntrs_bits { 2593 u8 time_since_last_clear_high[0x20]; 2594 2595 u8 time_since_last_clear_low[0x20]; 2596 2597 u8 phy_received_bits_high[0x20]; 2598 2599 u8 phy_received_bits_low[0x20]; 2600 2601 u8 phy_symbol_errors_high[0x20]; 2602 2603 u8 phy_symbol_errors_low[0x20]; 2604 2605 u8 phy_corrected_bits_high[0x20]; 2606 2607 u8 phy_corrected_bits_low[0x20]; 2608 2609 u8 phy_corrected_bits_lane0_high[0x20]; 2610 2611 u8 phy_corrected_bits_lane0_low[0x20]; 2612 2613 u8 phy_corrected_bits_lane1_high[0x20]; 2614 2615 u8 phy_corrected_bits_lane1_low[0x20]; 2616 2617 u8 phy_corrected_bits_lane2_high[0x20]; 2618 2619 u8 phy_corrected_bits_lane2_low[0x20]; 2620 2621 u8 phy_corrected_bits_lane3_high[0x20]; 2622 2623 u8 phy_corrected_bits_lane3_low[0x20]; 2624 2625 u8 reserved_at_200[0x5c0]; 2626 }; 2627 2628 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits { 2629 u8 symbol_error_counter[0x10]; 2630 2631 u8 link_error_recovery_counter[0x8]; 2632 2633 u8 link_downed_counter[0x8]; 2634 2635 u8 port_rcv_errors[0x10]; 2636 2637 u8 port_rcv_remote_physical_errors[0x10]; 2638 2639 u8 port_rcv_switch_relay_errors[0x10]; 2640 2641 u8 port_xmit_discards[0x10]; 2642 2643 u8 port_xmit_constraint_errors[0x8]; 2644 2645 u8 port_rcv_constraint_errors[0x8]; 2646 2647 u8 reserved_at_70[0x8]; 2648 2649 u8 link_overrun_errors[0x8]; 2650 2651 u8 reserved_at_80[0x10]; 2652 2653 u8 vl_15_dropped[0x10]; 2654 2655 u8 reserved_at_a0[0x80]; 2656 2657 u8 port_xmit_wait[0x20]; 2658 }; 2659 2660 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits { 2661 u8 transmit_queue_high[0x20]; 2662 2663 u8 transmit_queue_low[0x20]; 2664 2665 u8 no_buffer_discard_uc_high[0x20]; 2666 2667 u8 no_buffer_discard_uc_low[0x20]; 2668 2669 u8 reserved_at_80[0x740]; 2670 }; 2671 2672 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits { 2673 u8 wred_discard_high[0x20]; 2674 2675 u8 wred_discard_low[0x20]; 2676 2677 u8 ecn_marked_tc_high[0x20]; 2678 2679 u8 ecn_marked_tc_low[0x20]; 2680 2681 u8 reserved_at_80[0x740]; 2682 }; 2683 2684 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits { 2685 u8 rx_octets_high[0x20]; 2686 2687 u8 rx_octets_low[0x20]; 2688 2689 u8 reserved_at_40[0xc0]; 2690 2691 u8 rx_frames_high[0x20]; 2692 2693 u8 rx_frames_low[0x20]; 2694 2695 u8 tx_octets_high[0x20]; 2696 2697 u8 tx_octets_low[0x20]; 2698 2699 u8 reserved_at_180[0xc0]; 2700 2701 u8 tx_frames_high[0x20]; 2702 2703 u8 tx_frames_low[0x20]; 2704 2705 u8 rx_pause_high[0x20]; 2706 2707 u8 rx_pause_low[0x20]; 2708 2709 u8 rx_pause_duration_high[0x20]; 2710 2711 u8 rx_pause_duration_low[0x20]; 2712 2713 u8 tx_pause_high[0x20]; 2714 2715 u8 tx_pause_low[0x20]; 2716 2717 u8 tx_pause_duration_high[0x20]; 2718 2719 u8 tx_pause_duration_low[0x20]; 2720 2721 u8 rx_pause_transition_high[0x20]; 2722 2723 u8 rx_pause_transition_low[0x20]; 2724 2725 u8 rx_discards_high[0x20]; 2726 2727 u8 rx_discards_low[0x20]; 2728 2729 u8 device_stall_minor_watermark_cnt_high[0x20]; 2730 2731 u8 device_stall_minor_watermark_cnt_low[0x20]; 2732 2733 u8 device_stall_critical_watermark_cnt_high[0x20]; 2734 2735 u8 device_stall_critical_watermark_cnt_low[0x20]; 2736 2737 u8 reserved_at_480[0x340]; 2738 }; 2739 2740 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits { 2741 u8 port_transmit_wait_high[0x20]; 2742 2743 u8 port_transmit_wait_low[0x20]; 2744 2745 u8 reserved_at_40[0x100]; 2746 2747 u8 rx_buffer_almost_full_high[0x20]; 2748 2749 u8 rx_buffer_almost_full_low[0x20]; 2750 2751 u8 rx_buffer_full_high[0x20]; 2752 2753 u8 rx_buffer_full_low[0x20]; 2754 2755 u8 rx_icrc_encapsulated_high[0x20]; 2756 2757 u8 rx_icrc_encapsulated_low[0x20]; 2758 2759 u8 reserved_at_200[0x5c0]; 2760 }; 2761 2762 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits { 2763 u8 dot3stats_alignment_errors_high[0x20]; 2764 2765 u8 dot3stats_alignment_errors_low[0x20]; 2766 2767 u8 dot3stats_fcs_errors_high[0x20]; 2768 2769 u8 dot3stats_fcs_errors_low[0x20]; 2770 2771 u8 dot3stats_single_collision_frames_high[0x20]; 2772 2773 u8 dot3stats_single_collision_frames_low[0x20]; 2774 2775 u8 dot3stats_multiple_collision_frames_high[0x20]; 2776 2777 u8 dot3stats_multiple_collision_frames_low[0x20]; 2778 2779 u8 dot3stats_sqe_test_errors_high[0x20]; 2780 2781 u8 dot3stats_sqe_test_errors_low[0x20]; 2782 2783 u8 dot3stats_deferred_transmissions_high[0x20]; 2784 2785 u8 dot3stats_deferred_transmissions_low[0x20]; 2786 2787 u8 dot3stats_late_collisions_high[0x20]; 2788 2789 u8 dot3stats_late_collisions_low[0x20]; 2790 2791 u8 dot3stats_excessive_collisions_high[0x20]; 2792 2793 u8 dot3stats_excessive_collisions_low[0x20]; 2794 2795 u8 dot3stats_internal_mac_transmit_errors_high[0x20]; 2796 2797 u8 dot3stats_internal_mac_transmit_errors_low[0x20]; 2798 2799 u8 dot3stats_carrier_sense_errors_high[0x20]; 2800 2801 u8 dot3stats_carrier_sense_errors_low[0x20]; 2802 2803 u8 dot3stats_frame_too_longs_high[0x20]; 2804 2805 u8 dot3stats_frame_too_longs_low[0x20]; 2806 2807 u8 dot3stats_internal_mac_receive_errors_high[0x20]; 2808 2809 u8 dot3stats_internal_mac_receive_errors_low[0x20]; 2810 2811 u8 dot3stats_symbol_errors_high[0x20]; 2812 2813 u8 dot3stats_symbol_errors_low[0x20]; 2814 2815 u8 dot3control_in_unknown_opcodes_high[0x20]; 2816 2817 u8 dot3control_in_unknown_opcodes_low[0x20]; 2818 2819 u8 dot3in_pause_frames_high[0x20]; 2820 2821 u8 dot3in_pause_frames_low[0x20]; 2822 2823 u8 dot3out_pause_frames_high[0x20]; 2824 2825 u8 dot3out_pause_frames_low[0x20]; 2826 2827 u8 reserved_at_400[0x3c0]; 2828 }; 2829 2830 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits { 2831 u8 ether_stats_drop_events_high[0x20]; 2832 2833 u8 ether_stats_drop_events_low[0x20]; 2834 2835 u8 ether_stats_octets_high[0x20]; 2836 2837 u8 ether_stats_octets_low[0x20]; 2838 2839 u8 ether_stats_pkts_high[0x20]; 2840 2841 u8 ether_stats_pkts_low[0x20]; 2842 2843 u8 ether_stats_broadcast_pkts_high[0x20]; 2844 2845 u8 ether_stats_broadcast_pkts_low[0x20]; 2846 2847 u8 ether_stats_multicast_pkts_high[0x20]; 2848 2849 u8 ether_stats_multicast_pkts_low[0x20]; 2850 2851 u8 ether_stats_crc_align_errors_high[0x20]; 2852 2853 u8 ether_stats_crc_align_errors_low[0x20]; 2854 2855 u8 ether_stats_undersize_pkts_high[0x20]; 2856 2857 u8 ether_stats_undersize_pkts_low[0x20]; 2858 2859 u8 ether_stats_oversize_pkts_high[0x20]; 2860 2861 u8 ether_stats_oversize_pkts_low[0x20]; 2862 2863 u8 ether_stats_fragments_high[0x20]; 2864 2865 u8 ether_stats_fragments_low[0x20]; 2866 2867 u8 ether_stats_jabbers_high[0x20]; 2868 2869 u8 ether_stats_jabbers_low[0x20]; 2870 2871 u8 ether_stats_collisions_high[0x20]; 2872 2873 u8 ether_stats_collisions_low[0x20]; 2874 2875 u8 ether_stats_pkts64octets_high[0x20]; 2876 2877 u8 ether_stats_pkts64octets_low[0x20]; 2878 2879 u8 ether_stats_pkts65to127octets_high[0x20]; 2880 2881 u8 ether_stats_pkts65to127octets_low[0x20]; 2882 2883 u8 ether_stats_pkts128to255octets_high[0x20]; 2884 2885 u8 ether_stats_pkts128to255octets_low[0x20]; 2886 2887 u8 ether_stats_pkts256to511octets_high[0x20]; 2888 2889 u8 ether_stats_pkts256to511octets_low[0x20]; 2890 2891 u8 ether_stats_pkts512to1023octets_high[0x20]; 2892 2893 u8 ether_stats_pkts512to1023octets_low[0x20]; 2894 2895 u8 ether_stats_pkts1024to1518octets_high[0x20]; 2896 2897 u8 ether_stats_pkts1024to1518octets_low[0x20]; 2898 2899 u8 ether_stats_pkts1519to2047octets_high[0x20]; 2900 2901 u8 ether_stats_pkts1519to2047octets_low[0x20]; 2902 2903 u8 ether_stats_pkts2048to4095octets_high[0x20]; 2904 2905 u8 ether_stats_pkts2048to4095octets_low[0x20]; 2906 2907 u8 ether_stats_pkts4096to8191octets_high[0x20]; 2908 2909 u8 ether_stats_pkts4096to8191octets_low[0x20]; 2910 2911 u8 ether_stats_pkts8192to10239octets_high[0x20]; 2912 2913 u8 ether_stats_pkts8192to10239octets_low[0x20]; 2914 2915 u8 reserved_at_540[0x280]; 2916 }; 2917 2918 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits { 2919 u8 if_in_octets_high[0x20]; 2920 2921 u8 if_in_octets_low[0x20]; 2922 2923 u8 if_in_ucast_pkts_high[0x20]; 2924 2925 u8 if_in_ucast_pkts_low[0x20]; 2926 2927 u8 if_in_discards_high[0x20]; 2928 2929 u8 if_in_discards_low[0x20]; 2930 2931 u8 if_in_errors_high[0x20]; 2932 2933 u8 if_in_errors_low[0x20]; 2934 2935 u8 if_in_unknown_protos_high[0x20]; 2936 2937 u8 if_in_unknown_protos_low[0x20]; 2938 2939 u8 if_out_octets_high[0x20]; 2940 2941 u8 if_out_octets_low[0x20]; 2942 2943 u8 if_out_ucast_pkts_high[0x20]; 2944 2945 u8 if_out_ucast_pkts_low[0x20]; 2946 2947 u8 if_out_discards_high[0x20]; 2948 2949 u8 if_out_discards_low[0x20]; 2950 2951 u8 if_out_errors_high[0x20]; 2952 2953 u8 if_out_errors_low[0x20]; 2954 2955 u8 if_in_multicast_pkts_high[0x20]; 2956 2957 u8 if_in_multicast_pkts_low[0x20]; 2958 2959 u8 if_in_broadcast_pkts_high[0x20]; 2960 2961 u8 if_in_broadcast_pkts_low[0x20]; 2962 2963 u8 if_out_multicast_pkts_high[0x20]; 2964 2965 u8 if_out_multicast_pkts_low[0x20]; 2966 2967 u8 if_out_broadcast_pkts_high[0x20]; 2968 2969 u8 if_out_broadcast_pkts_low[0x20]; 2970 2971 u8 reserved_at_340[0x480]; 2972 }; 2973 2974 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits { 2975 u8 a_frames_transmitted_ok_high[0x20]; 2976 2977 u8 a_frames_transmitted_ok_low[0x20]; 2978 2979 u8 a_frames_received_ok_high[0x20]; 2980 2981 u8 a_frames_received_ok_low[0x20]; 2982 2983 u8 a_frame_check_sequence_errors_high[0x20]; 2984 2985 u8 a_frame_check_sequence_errors_low[0x20]; 2986 2987 u8 a_alignment_errors_high[0x20]; 2988 2989 u8 a_alignment_errors_low[0x20]; 2990 2991 u8 a_octets_transmitted_ok_high[0x20]; 2992 2993 u8 a_octets_transmitted_ok_low[0x20]; 2994 2995 u8 a_octets_received_ok_high[0x20]; 2996 2997 u8 a_octets_received_ok_low[0x20]; 2998 2999 u8 a_multicast_frames_xmitted_ok_high[0x20]; 3000 3001 u8 a_multicast_frames_xmitted_ok_low[0x20]; 3002 3003 u8 a_broadcast_frames_xmitted_ok_high[0x20]; 3004 3005 u8 a_broadcast_frames_xmitted_ok_low[0x20]; 3006 3007 u8 a_multicast_frames_received_ok_high[0x20]; 3008 3009 u8 a_multicast_frames_received_ok_low[0x20]; 3010 3011 u8 a_broadcast_frames_received_ok_high[0x20]; 3012 3013 u8 a_broadcast_frames_received_ok_low[0x20]; 3014 3015 u8 a_in_range_length_errors_high[0x20]; 3016 3017 u8 a_in_range_length_errors_low[0x20]; 3018 3019 u8 a_out_of_range_length_field_high[0x20]; 3020 3021 u8 a_out_of_range_length_field_low[0x20]; 3022 3023 u8 a_frame_too_long_errors_high[0x20]; 3024 3025 u8 a_frame_too_long_errors_low[0x20]; 3026 3027 u8 a_symbol_error_during_carrier_high[0x20]; 3028 3029 u8 a_symbol_error_during_carrier_low[0x20]; 3030 3031 u8 a_mac_control_frames_transmitted_high[0x20]; 3032 3033 u8 a_mac_control_frames_transmitted_low[0x20]; 3034 3035 u8 a_mac_control_frames_received_high[0x20]; 3036 3037 u8 a_mac_control_frames_received_low[0x20]; 3038 3039 u8 a_unsupported_opcodes_received_high[0x20]; 3040 3041 u8 a_unsupported_opcodes_received_low[0x20]; 3042 3043 u8 a_pause_mac_ctrl_frames_received_high[0x20]; 3044 3045 u8 a_pause_mac_ctrl_frames_received_low[0x20]; 3046 3047 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20]; 3048 3049 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20]; 3050 3051 u8 reserved_at_4c0[0x300]; 3052 }; 3053 3054 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits { 3055 u8 life_time_counter_high[0x20]; 3056 3057 u8 life_time_counter_low[0x20]; 3058 3059 u8 rx_errors[0x20]; 3060 3061 u8 tx_errors[0x20]; 3062 3063 u8 l0_to_recovery_eieos[0x20]; 3064 3065 u8 l0_to_recovery_ts[0x20]; 3066 3067 u8 l0_to_recovery_framing[0x20]; 3068 3069 u8 l0_to_recovery_retrain[0x20]; 3070 3071 u8 crc_error_dllp[0x20]; 3072 3073 u8 crc_error_tlp[0x20]; 3074 3075 u8 tx_overflow_buffer_pkt_high[0x20]; 3076 3077 u8 tx_overflow_buffer_pkt_low[0x20]; 3078 3079 u8 outbound_stalled_reads[0x20]; 3080 3081 u8 outbound_stalled_writes[0x20]; 3082 3083 u8 outbound_stalled_reads_events[0x20]; 3084 3085 u8 outbound_stalled_writes_events[0x20]; 3086 3087 u8 reserved_at_200[0x5c0]; 3088 }; 3089 3090 struct mlx5_ifc_cmd_inter_comp_event_bits { 3091 u8 command_completion_vector[0x20]; 3092 3093 u8 reserved_at_20[0xc0]; 3094 }; 3095 3096 struct mlx5_ifc_stall_vl_event_bits { 3097 u8 reserved_at_0[0x18]; 3098 u8 port_num[0x1]; 3099 u8 reserved_at_19[0x3]; 3100 u8 vl[0x4]; 3101 3102 u8 reserved_at_20[0xa0]; 3103 }; 3104 3105 struct mlx5_ifc_db_bf_congestion_event_bits { 3106 u8 event_subtype[0x8]; 3107 u8 reserved_at_8[0x8]; 3108 u8 congestion_level[0x8]; 3109 u8 reserved_at_18[0x8]; 3110 3111 u8 reserved_at_20[0xa0]; 3112 }; 3113 3114 struct mlx5_ifc_gpio_event_bits { 3115 u8 reserved_at_0[0x60]; 3116 3117 u8 gpio_event_hi[0x20]; 3118 3119 u8 gpio_event_lo[0x20]; 3120 3121 u8 reserved_at_a0[0x40]; 3122 }; 3123 3124 struct mlx5_ifc_port_state_change_event_bits { 3125 u8 reserved_at_0[0x40]; 3126 3127 u8 port_num[0x4]; 3128 u8 reserved_at_44[0x1c]; 3129 3130 u8 reserved_at_60[0x80]; 3131 }; 3132 3133 struct mlx5_ifc_dropped_packet_logged_bits { 3134 u8 reserved_at_0[0xe0]; 3135 }; 3136 3137 struct mlx5_ifc_default_timeout_bits { 3138 u8 to_multiplier[0x3]; 3139 u8 reserved_at_3[0x9]; 3140 u8 to_value[0x14]; 3141 }; 3142 3143 struct mlx5_ifc_dtor_reg_bits { 3144 u8 reserved_at_0[0x20]; 3145 3146 struct mlx5_ifc_default_timeout_bits pcie_toggle_to; 3147 3148 u8 reserved_at_40[0x60]; 3149 3150 struct mlx5_ifc_default_timeout_bits health_poll_to; 3151 3152 struct mlx5_ifc_default_timeout_bits full_crdump_to; 3153 3154 struct mlx5_ifc_default_timeout_bits fw_reset_to; 3155 3156 struct mlx5_ifc_default_timeout_bits flush_on_err_to; 3157 3158 struct mlx5_ifc_default_timeout_bits pci_sync_update_to; 3159 3160 struct mlx5_ifc_default_timeout_bits tear_down_to; 3161 3162 struct mlx5_ifc_default_timeout_bits fsm_reactivate_to; 3163 3164 struct mlx5_ifc_default_timeout_bits reclaim_pages_to; 3165 3166 struct mlx5_ifc_default_timeout_bits reclaim_vfs_pages_to; 3167 3168 struct mlx5_ifc_default_timeout_bits reset_unload_to; 3169 3170 u8 reserved_at_1c0[0x20]; 3171 }; 3172 3173 enum { 3174 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1, 3175 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2, 3176 }; 3177 3178 struct mlx5_ifc_cq_error_bits { 3179 u8 reserved_at_0[0x8]; 3180 u8 cqn[0x18]; 3181 3182 u8 reserved_at_20[0x20]; 3183 3184 u8 reserved_at_40[0x18]; 3185 u8 syndrome[0x8]; 3186 3187 u8 reserved_at_60[0x80]; 3188 }; 3189 3190 struct mlx5_ifc_rdma_page_fault_event_bits { 3191 u8 bytes_committed[0x20]; 3192 3193 u8 r_key[0x20]; 3194 3195 u8 reserved_at_40[0x10]; 3196 u8 packet_len[0x10]; 3197 3198 u8 rdma_op_len[0x20]; 3199 3200 u8 rdma_va[0x40]; 3201 3202 u8 reserved_at_c0[0x5]; 3203 u8 rdma[0x1]; 3204 u8 write[0x1]; 3205 u8 requestor[0x1]; 3206 u8 qp_number[0x18]; 3207 }; 3208 3209 struct mlx5_ifc_wqe_associated_page_fault_event_bits { 3210 u8 bytes_committed[0x20]; 3211 3212 u8 reserved_at_20[0x10]; 3213 u8 wqe_index[0x10]; 3214 3215 u8 reserved_at_40[0x10]; 3216 u8 len[0x10]; 3217 3218 u8 reserved_at_60[0x60]; 3219 3220 u8 reserved_at_c0[0x5]; 3221 u8 rdma[0x1]; 3222 u8 write_read[0x1]; 3223 u8 requestor[0x1]; 3224 u8 qpn[0x18]; 3225 }; 3226 3227 struct mlx5_ifc_qp_events_bits { 3228 u8 reserved_at_0[0xa0]; 3229 3230 u8 type[0x8]; 3231 u8 reserved_at_a8[0x18]; 3232 3233 u8 reserved_at_c0[0x8]; 3234 u8 qpn_rqn_sqn[0x18]; 3235 }; 3236 3237 struct mlx5_ifc_dct_events_bits { 3238 u8 reserved_at_0[0xc0]; 3239 3240 u8 reserved_at_c0[0x8]; 3241 u8 dct_number[0x18]; 3242 }; 3243 3244 struct mlx5_ifc_comp_event_bits { 3245 u8 reserved_at_0[0xc0]; 3246 3247 u8 reserved_at_c0[0x8]; 3248 u8 cq_number[0x18]; 3249 }; 3250 3251 enum { 3252 MLX5_QPC_STATE_RST = 0x0, 3253 MLX5_QPC_STATE_INIT = 0x1, 3254 MLX5_QPC_STATE_RTR = 0x2, 3255 MLX5_QPC_STATE_RTS = 0x3, 3256 MLX5_QPC_STATE_SQER = 0x4, 3257 MLX5_QPC_STATE_ERR = 0x6, 3258 MLX5_QPC_STATE_SQD = 0x7, 3259 MLX5_QPC_STATE_SUSPENDED = 0x9, 3260 }; 3261 3262 enum { 3263 MLX5_QPC_ST_RC = 0x0, 3264 MLX5_QPC_ST_UC = 0x1, 3265 MLX5_QPC_ST_UD = 0x2, 3266 MLX5_QPC_ST_XRC = 0x3, 3267 MLX5_QPC_ST_DCI = 0x5, 3268 MLX5_QPC_ST_QP0 = 0x7, 3269 MLX5_QPC_ST_QP1 = 0x8, 3270 MLX5_QPC_ST_RAW_DATAGRAM = 0x9, 3271 MLX5_QPC_ST_REG_UMR = 0xc, 3272 }; 3273 3274 enum { 3275 MLX5_QPC_PM_STATE_ARMED = 0x0, 3276 MLX5_QPC_PM_STATE_REARM = 0x1, 3277 MLX5_QPC_PM_STATE_RESERVED = 0x2, 3278 MLX5_QPC_PM_STATE_MIGRATED = 0x3, 3279 }; 3280 3281 enum { 3282 MLX5_QPC_OFFLOAD_TYPE_RNDV = 0x1, 3283 }; 3284 3285 enum { 3286 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0, 3287 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1, 3288 }; 3289 3290 enum { 3291 MLX5_QPC_MTU_256_BYTES = 0x1, 3292 MLX5_QPC_MTU_512_BYTES = 0x2, 3293 MLX5_QPC_MTU_1K_BYTES = 0x3, 3294 MLX5_QPC_MTU_2K_BYTES = 0x4, 3295 MLX5_QPC_MTU_4K_BYTES = 0x5, 3296 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7, 3297 }; 3298 3299 enum { 3300 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1, 3301 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2, 3302 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3, 3303 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4, 3304 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5, 3305 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6, 3306 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7, 3307 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8, 3308 }; 3309 3310 enum { 3311 MLX5_QPC_CS_REQ_DISABLE = 0x0, 3312 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11, 3313 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22, 3314 }; 3315 3316 enum { 3317 MLX5_QPC_CS_RES_DISABLE = 0x0, 3318 MLX5_QPC_CS_RES_UP_TO_32B = 0x1, 3319 MLX5_QPC_CS_RES_UP_TO_64B = 0x2, 3320 }; 3321 3322 enum { 3323 MLX5_TIMESTAMP_FORMAT_FREE_RUNNING = 0x0, 3324 MLX5_TIMESTAMP_FORMAT_DEFAULT = 0x1, 3325 MLX5_TIMESTAMP_FORMAT_REAL_TIME = 0x2, 3326 }; 3327 3328 struct mlx5_ifc_qpc_bits { 3329 u8 state[0x4]; 3330 u8 lag_tx_port_affinity[0x4]; 3331 u8 st[0x8]; 3332 u8 reserved_at_10[0x2]; 3333 u8 isolate_vl_tc[0x1]; 3334 u8 pm_state[0x2]; 3335 u8 reserved_at_15[0x1]; 3336 u8 req_e2e_credit_mode[0x2]; 3337 u8 offload_type[0x4]; 3338 u8 end_padding_mode[0x2]; 3339 u8 reserved_at_1e[0x2]; 3340 3341 u8 wq_signature[0x1]; 3342 u8 block_lb_mc[0x1]; 3343 u8 atomic_like_write_en[0x1]; 3344 u8 latency_sensitive[0x1]; 3345 u8 reserved_at_24[0x1]; 3346 u8 drain_sigerr[0x1]; 3347 u8 reserved_at_26[0x2]; 3348 u8 pd[0x18]; 3349 3350 u8 mtu[0x3]; 3351 u8 log_msg_max[0x5]; 3352 u8 reserved_at_48[0x1]; 3353 u8 log_rq_size[0x4]; 3354 u8 log_rq_stride[0x3]; 3355 u8 no_sq[0x1]; 3356 u8 log_sq_size[0x4]; 3357 u8 reserved_at_55[0x1]; 3358 u8 retry_mode[0x2]; 3359 u8 ts_format[0x2]; 3360 u8 reserved_at_5a[0x1]; 3361 u8 rlky[0x1]; 3362 u8 ulp_stateless_offload_mode[0x4]; 3363 3364 u8 counter_set_id[0x8]; 3365 u8 uar_page[0x18]; 3366 3367 u8 reserved_at_80[0x8]; 3368 u8 user_index[0x18]; 3369 3370 u8 reserved_at_a0[0x3]; 3371 u8 log_page_size[0x5]; 3372 u8 remote_qpn[0x18]; 3373 3374 struct mlx5_ifc_ads_bits primary_address_path; 3375 3376 struct mlx5_ifc_ads_bits secondary_address_path; 3377 3378 u8 log_ack_req_freq[0x4]; 3379 u8 reserved_at_384[0x4]; 3380 u8 log_sra_max[0x3]; 3381 u8 reserved_at_38b[0x2]; 3382 u8 retry_count[0x3]; 3383 u8 rnr_retry[0x3]; 3384 u8 reserved_at_393[0x1]; 3385 u8 fre[0x1]; 3386 u8 cur_rnr_retry[0x3]; 3387 u8 cur_retry_count[0x3]; 3388 u8 reserved_at_39b[0x5]; 3389 3390 u8 reserved_at_3a0[0x20]; 3391 3392 u8 reserved_at_3c0[0x8]; 3393 u8 next_send_psn[0x18]; 3394 3395 u8 reserved_at_3e0[0x3]; 3396 u8 log_num_dci_stream_channels[0x5]; 3397 u8 cqn_snd[0x18]; 3398 3399 u8 reserved_at_400[0x3]; 3400 u8 log_num_dci_errored_streams[0x5]; 3401 u8 deth_sqpn[0x18]; 3402 3403 u8 reserved_at_420[0x20]; 3404 3405 u8 reserved_at_440[0x8]; 3406 u8 last_acked_psn[0x18]; 3407 3408 u8 reserved_at_460[0x8]; 3409 u8 ssn[0x18]; 3410 3411 u8 reserved_at_480[0x8]; 3412 u8 log_rra_max[0x3]; 3413 u8 reserved_at_48b[0x1]; 3414 u8 atomic_mode[0x4]; 3415 u8 rre[0x1]; 3416 u8 rwe[0x1]; 3417 u8 rae[0x1]; 3418 u8 reserved_at_493[0x1]; 3419 u8 page_offset[0x6]; 3420 u8 reserved_at_49a[0x3]; 3421 u8 cd_slave_receive[0x1]; 3422 u8 cd_slave_send[0x1]; 3423 u8 cd_master[0x1]; 3424 3425 u8 reserved_at_4a0[0x3]; 3426 u8 min_rnr_nak[0x5]; 3427 u8 next_rcv_psn[0x18]; 3428 3429 u8 reserved_at_4c0[0x8]; 3430 u8 xrcd[0x18]; 3431 3432 u8 reserved_at_4e0[0x8]; 3433 u8 cqn_rcv[0x18]; 3434 3435 u8 dbr_addr[0x40]; 3436 3437 u8 q_key[0x20]; 3438 3439 u8 reserved_at_560[0x5]; 3440 u8 rq_type[0x3]; 3441 u8 srqn_rmpn_xrqn[0x18]; 3442 3443 u8 reserved_at_580[0x8]; 3444 u8 rmsn[0x18]; 3445 3446 u8 hw_sq_wqebb_counter[0x10]; 3447 u8 sw_sq_wqebb_counter[0x10]; 3448 3449 u8 hw_rq_counter[0x20]; 3450 3451 u8 sw_rq_counter[0x20]; 3452 3453 u8 reserved_at_600[0x20]; 3454 3455 u8 reserved_at_620[0xf]; 3456 u8 cgs[0x1]; 3457 u8 cs_req[0x8]; 3458 u8 cs_res[0x8]; 3459 3460 u8 dc_access_key[0x40]; 3461 3462 u8 reserved_at_680[0x3]; 3463 u8 dbr_umem_valid[0x1]; 3464 3465 u8 reserved_at_684[0xbc]; 3466 }; 3467 3468 struct mlx5_ifc_roce_addr_layout_bits { 3469 u8 source_l3_address[16][0x8]; 3470 3471 u8 reserved_at_80[0x3]; 3472 u8 vlan_valid[0x1]; 3473 u8 vlan_id[0xc]; 3474 u8 source_mac_47_32[0x10]; 3475 3476 u8 source_mac_31_0[0x20]; 3477 3478 u8 reserved_at_c0[0x14]; 3479 u8 roce_l3_type[0x4]; 3480 u8 roce_version[0x8]; 3481 3482 u8 reserved_at_e0[0x20]; 3483 }; 3484 3485 struct mlx5_ifc_crypto_cap_bits { 3486 u8 reserved_at_0[0x3]; 3487 u8 synchronize_dek[0x1]; 3488 u8 int_kek_manual[0x1]; 3489 u8 int_kek_auto[0x1]; 3490 u8 reserved_at_6[0x1a]; 3491 3492 u8 reserved_at_20[0x3]; 3493 u8 log_dek_max_alloc[0x5]; 3494 u8 reserved_at_28[0x3]; 3495 u8 log_max_num_deks[0x5]; 3496 u8 reserved_at_30[0x10]; 3497 3498 u8 reserved_at_40[0x20]; 3499 3500 u8 reserved_at_60[0x3]; 3501 u8 log_dek_granularity[0x5]; 3502 u8 reserved_at_68[0x3]; 3503 u8 log_max_num_int_kek[0x5]; 3504 u8 sw_wrapped_dek[0x10]; 3505 3506 u8 reserved_at_80[0x780]; 3507 }; 3508 3509 union mlx5_ifc_hca_cap_union_bits { 3510 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap; 3511 struct mlx5_ifc_cmd_hca_cap_2_bits cmd_hca_cap_2; 3512 struct mlx5_ifc_odp_cap_bits odp_cap; 3513 struct mlx5_ifc_atomic_caps_bits atomic_caps; 3514 struct mlx5_ifc_roce_cap_bits roce_cap; 3515 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps; 3516 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap; 3517 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap; 3518 struct mlx5_ifc_e_switch_cap_bits e_switch_cap; 3519 struct mlx5_ifc_port_selection_cap_bits port_selection_cap; 3520 struct mlx5_ifc_qos_cap_bits qos_cap; 3521 struct mlx5_ifc_debug_cap_bits debug_cap; 3522 struct mlx5_ifc_fpga_cap_bits fpga_cap; 3523 struct mlx5_ifc_tls_cap_bits tls_cap; 3524 struct mlx5_ifc_device_mem_cap_bits device_mem_cap; 3525 struct mlx5_ifc_virtio_emulation_cap_bits virtio_emulation_cap; 3526 struct mlx5_ifc_macsec_cap_bits macsec_cap; 3527 struct mlx5_ifc_crypto_cap_bits crypto_cap; 3528 struct mlx5_ifc_ipsec_cap_bits ipsec_cap; 3529 u8 reserved_at_0[0x8000]; 3530 }; 3531 3532 enum { 3533 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1, 3534 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2, 3535 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4, 3536 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8, 3537 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT = 0x10, 3538 MLX5_FLOW_CONTEXT_ACTION_DECAP = 0x20, 3539 MLX5_FLOW_CONTEXT_ACTION_MOD_HDR = 0x40, 3540 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP = 0x80, 3541 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100, 3542 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2 = 0x400, 3543 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2 = 0x800, 3544 MLX5_FLOW_CONTEXT_ACTION_CRYPTO_DECRYPT = 0x1000, 3545 MLX5_FLOW_CONTEXT_ACTION_CRYPTO_ENCRYPT = 0x2000, 3546 MLX5_FLOW_CONTEXT_ACTION_EXECUTE_ASO = 0x4000, 3547 }; 3548 3549 enum { 3550 MLX5_FLOW_CONTEXT_FLOW_SOURCE_ANY_VPORT = 0x0, 3551 MLX5_FLOW_CONTEXT_FLOW_SOURCE_UPLINK = 0x1, 3552 MLX5_FLOW_CONTEXT_FLOW_SOURCE_LOCAL_VPORT = 0x2, 3553 }; 3554 3555 enum { 3556 MLX5_FLOW_CONTEXT_ENCRYPT_DECRYPT_TYPE_IPSEC = 0x0, 3557 MLX5_FLOW_CONTEXT_ENCRYPT_DECRYPT_TYPE_MACSEC = 0x1, 3558 }; 3559 3560 struct mlx5_ifc_vlan_bits { 3561 u8 ethtype[0x10]; 3562 u8 prio[0x3]; 3563 u8 cfi[0x1]; 3564 u8 vid[0xc]; 3565 }; 3566 3567 enum { 3568 MLX5_FLOW_METER_COLOR_RED = 0x0, 3569 MLX5_FLOW_METER_COLOR_YELLOW = 0x1, 3570 MLX5_FLOW_METER_COLOR_GREEN = 0x2, 3571 MLX5_FLOW_METER_COLOR_UNDEFINED = 0x3, 3572 }; 3573 3574 enum { 3575 MLX5_EXE_ASO_FLOW_METER = 0x2, 3576 }; 3577 3578 struct mlx5_ifc_exe_aso_ctrl_flow_meter_bits { 3579 u8 return_reg_id[0x4]; 3580 u8 aso_type[0x4]; 3581 u8 reserved_at_8[0x14]; 3582 u8 action[0x1]; 3583 u8 init_color[0x2]; 3584 u8 meter_id[0x1]; 3585 }; 3586 3587 union mlx5_ifc_exe_aso_ctrl { 3588 struct mlx5_ifc_exe_aso_ctrl_flow_meter_bits exe_aso_ctrl_flow_meter; 3589 }; 3590 3591 struct mlx5_ifc_execute_aso_bits { 3592 u8 valid[0x1]; 3593 u8 reserved_at_1[0x7]; 3594 u8 aso_object_id[0x18]; 3595 3596 union mlx5_ifc_exe_aso_ctrl exe_aso_ctrl; 3597 }; 3598 3599 struct mlx5_ifc_flow_context_bits { 3600 struct mlx5_ifc_vlan_bits push_vlan; 3601 3602 u8 group_id[0x20]; 3603 3604 u8 reserved_at_40[0x8]; 3605 u8 flow_tag[0x18]; 3606 3607 u8 reserved_at_60[0x10]; 3608 u8 action[0x10]; 3609 3610 u8 extended_destination[0x1]; 3611 u8 uplink_hairpin_en[0x1]; 3612 u8 flow_source[0x2]; 3613 u8 encrypt_decrypt_type[0x4]; 3614 u8 destination_list_size[0x18]; 3615 3616 u8 reserved_at_a0[0x8]; 3617 u8 flow_counter_list_size[0x18]; 3618 3619 u8 packet_reformat_id[0x20]; 3620 3621 u8 modify_header_id[0x20]; 3622 3623 struct mlx5_ifc_vlan_bits push_vlan_2; 3624 3625 u8 encrypt_decrypt_obj_id[0x20]; 3626 u8 reserved_at_140[0xc0]; 3627 3628 struct mlx5_ifc_fte_match_param_bits match_value; 3629 3630 struct mlx5_ifc_execute_aso_bits execute_aso[4]; 3631 3632 u8 reserved_at_1300[0x500]; 3633 3634 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[]; 3635 }; 3636 3637 enum { 3638 MLX5_XRC_SRQC_STATE_GOOD = 0x0, 3639 MLX5_XRC_SRQC_STATE_ERROR = 0x1, 3640 }; 3641 3642 struct mlx5_ifc_xrc_srqc_bits { 3643 u8 state[0x4]; 3644 u8 log_xrc_srq_size[0x4]; 3645 u8 reserved_at_8[0x18]; 3646 3647 u8 wq_signature[0x1]; 3648 u8 cont_srq[0x1]; 3649 u8 reserved_at_22[0x1]; 3650 u8 rlky[0x1]; 3651 u8 basic_cyclic_rcv_wqe[0x1]; 3652 u8 log_rq_stride[0x3]; 3653 u8 xrcd[0x18]; 3654 3655 u8 page_offset[0x6]; 3656 u8 reserved_at_46[0x1]; 3657 u8 dbr_umem_valid[0x1]; 3658 u8 cqn[0x18]; 3659 3660 u8 reserved_at_60[0x20]; 3661 3662 u8 user_index_equal_xrc_srqn[0x1]; 3663 u8 reserved_at_81[0x1]; 3664 u8 log_page_size[0x6]; 3665 u8 user_index[0x18]; 3666 3667 u8 reserved_at_a0[0x20]; 3668 3669 u8 reserved_at_c0[0x8]; 3670 u8 pd[0x18]; 3671 3672 u8 lwm[0x10]; 3673 u8 wqe_cnt[0x10]; 3674 3675 u8 reserved_at_100[0x40]; 3676 3677 u8 db_record_addr_h[0x20]; 3678 3679 u8 db_record_addr_l[0x1e]; 3680 u8 reserved_at_17e[0x2]; 3681 3682 u8 reserved_at_180[0x80]; 3683 }; 3684 3685 struct mlx5_ifc_vnic_diagnostic_statistics_bits { 3686 u8 counter_error_queues[0x20]; 3687 3688 u8 total_error_queues[0x20]; 3689 3690 u8 send_queue_priority_update_flow[0x20]; 3691 3692 u8 reserved_at_60[0x20]; 3693 3694 u8 nic_receive_steering_discard[0x40]; 3695 3696 u8 receive_discard_vport_down[0x40]; 3697 3698 u8 transmit_discard_vport_down[0x40]; 3699 3700 u8 async_eq_overrun[0x20]; 3701 3702 u8 comp_eq_overrun[0x20]; 3703 3704 u8 reserved_at_180[0x20]; 3705 3706 u8 invalid_command[0x20]; 3707 3708 u8 quota_exceeded_command[0x20]; 3709 3710 u8 internal_rq_out_of_buffer[0x20]; 3711 3712 u8 cq_overrun[0x20]; 3713 3714 u8 eth_wqe_too_small[0x20]; 3715 3716 u8 reserved_at_220[0xc0]; 3717 3718 u8 generated_pkt_steering_fail[0x40]; 3719 3720 u8 handled_pkt_steering_fail[0x40]; 3721 3722 u8 reserved_at_360[0xc80]; 3723 }; 3724 3725 struct mlx5_ifc_traffic_counter_bits { 3726 u8 packets[0x40]; 3727 3728 u8 octets[0x40]; 3729 }; 3730 3731 struct mlx5_ifc_tisc_bits { 3732 u8 strict_lag_tx_port_affinity[0x1]; 3733 u8 tls_en[0x1]; 3734 u8 reserved_at_2[0x2]; 3735 u8 lag_tx_port_affinity[0x04]; 3736 3737 u8 reserved_at_8[0x4]; 3738 u8 prio[0x4]; 3739 u8 reserved_at_10[0x10]; 3740 3741 u8 reserved_at_20[0x100]; 3742 3743 u8 reserved_at_120[0x8]; 3744 u8 transport_domain[0x18]; 3745 3746 u8 reserved_at_140[0x8]; 3747 u8 underlay_qpn[0x18]; 3748 3749 u8 reserved_at_160[0x8]; 3750 u8 pd[0x18]; 3751 3752 u8 reserved_at_180[0x380]; 3753 }; 3754 3755 enum { 3756 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0, 3757 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1, 3758 }; 3759 3760 enum { 3761 MLX5_TIRC_PACKET_MERGE_MASK_IPV4_LRO = BIT(0), 3762 MLX5_TIRC_PACKET_MERGE_MASK_IPV6_LRO = BIT(1), 3763 }; 3764 3765 enum { 3766 MLX5_RX_HASH_FN_NONE = 0x0, 3767 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1, 3768 MLX5_RX_HASH_FN_TOEPLITZ = 0x2, 3769 }; 3770 3771 enum { 3772 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST = 0x1, 3773 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST = 0x2, 3774 }; 3775 3776 struct mlx5_ifc_tirc_bits { 3777 u8 reserved_at_0[0x20]; 3778 3779 u8 disp_type[0x4]; 3780 u8 tls_en[0x1]; 3781 u8 reserved_at_25[0x1b]; 3782 3783 u8 reserved_at_40[0x40]; 3784 3785 u8 reserved_at_80[0x4]; 3786 u8 lro_timeout_period_usecs[0x10]; 3787 u8 packet_merge_mask[0x4]; 3788 u8 lro_max_ip_payload_size[0x8]; 3789 3790 u8 reserved_at_a0[0x40]; 3791 3792 u8 reserved_at_e0[0x8]; 3793 u8 inline_rqn[0x18]; 3794 3795 u8 rx_hash_symmetric[0x1]; 3796 u8 reserved_at_101[0x1]; 3797 u8 tunneled_offload_en[0x1]; 3798 u8 reserved_at_103[0x5]; 3799 u8 indirect_table[0x18]; 3800 3801 u8 rx_hash_fn[0x4]; 3802 u8 reserved_at_124[0x2]; 3803 u8 self_lb_block[0x2]; 3804 u8 transport_domain[0x18]; 3805 3806 u8 rx_hash_toeplitz_key[10][0x20]; 3807 3808 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer; 3809 3810 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner; 3811 3812 u8 reserved_at_2c0[0x4c0]; 3813 }; 3814 3815 enum { 3816 MLX5_SRQC_STATE_GOOD = 0x0, 3817 MLX5_SRQC_STATE_ERROR = 0x1, 3818 }; 3819 3820 struct mlx5_ifc_srqc_bits { 3821 u8 state[0x4]; 3822 u8 log_srq_size[0x4]; 3823 u8 reserved_at_8[0x18]; 3824 3825 u8 wq_signature[0x1]; 3826 u8 cont_srq[0x1]; 3827 u8 reserved_at_22[0x1]; 3828 u8 rlky[0x1]; 3829 u8 reserved_at_24[0x1]; 3830 u8 log_rq_stride[0x3]; 3831 u8 xrcd[0x18]; 3832 3833 u8 page_offset[0x6]; 3834 u8 reserved_at_46[0x2]; 3835 u8 cqn[0x18]; 3836 3837 u8 reserved_at_60[0x20]; 3838 3839 u8 reserved_at_80[0x2]; 3840 u8 log_page_size[0x6]; 3841 u8 reserved_at_88[0x18]; 3842 3843 u8 reserved_at_a0[0x20]; 3844 3845 u8 reserved_at_c0[0x8]; 3846 u8 pd[0x18]; 3847 3848 u8 lwm[0x10]; 3849 u8 wqe_cnt[0x10]; 3850 3851 u8 reserved_at_100[0x40]; 3852 3853 u8 dbr_addr[0x40]; 3854 3855 u8 reserved_at_180[0x80]; 3856 }; 3857 3858 enum { 3859 MLX5_SQC_STATE_RST = 0x0, 3860 MLX5_SQC_STATE_RDY = 0x1, 3861 MLX5_SQC_STATE_ERR = 0x3, 3862 }; 3863 3864 struct mlx5_ifc_sqc_bits { 3865 u8 rlky[0x1]; 3866 u8 cd_master[0x1]; 3867 u8 fre[0x1]; 3868 u8 flush_in_error_en[0x1]; 3869 u8 allow_multi_pkt_send_wqe[0x1]; 3870 u8 min_wqe_inline_mode[0x3]; 3871 u8 state[0x4]; 3872 u8 reg_umr[0x1]; 3873 u8 allow_swp[0x1]; 3874 u8 hairpin[0x1]; 3875 u8 reserved_at_f[0xb]; 3876 u8 ts_format[0x2]; 3877 u8 reserved_at_1c[0x4]; 3878 3879 u8 reserved_at_20[0x8]; 3880 u8 user_index[0x18]; 3881 3882 u8 reserved_at_40[0x8]; 3883 u8 cqn[0x18]; 3884 3885 u8 reserved_at_60[0x8]; 3886 u8 hairpin_peer_rq[0x18]; 3887 3888 u8 reserved_at_80[0x10]; 3889 u8 hairpin_peer_vhca[0x10]; 3890 3891 u8 reserved_at_a0[0x20]; 3892 3893 u8 reserved_at_c0[0x8]; 3894 u8 ts_cqe_to_dest_cqn[0x18]; 3895 3896 u8 reserved_at_e0[0x10]; 3897 u8 packet_pacing_rate_limit_index[0x10]; 3898 u8 tis_lst_sz[0x10]; 3899 u8 qos_queue_group_id[0x10]; 3900 3901 u8 reserved_at_120[0x40]; 3902 3903 u8 reserved_at_160[0x8]; 3904 u8 tis_num_0[0x18]; 3905 3906 struct mlx5_ifc_wq_bits wq; 3907 }; 3908 3909 enum { 3910 SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0, 3911 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1, 3912 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2, 3913 SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3, 3914 SCHEDULING_CONTEXT_ELEMENT_TYPE_QUEUE_GROUP = 0x4, 3915 }; 3916 3917 enum { 3918 ELEMENT_TYPE_CAP_MASK_TSAR = 1 << 0, 3919 ELEMENT_TYPE_CAP_MASK_VPORT = 1 << 1, 3920 ELEMENT_TYPE_CAP_MASK_VPORT_TC = 1 << 2, 3921 ELEMENT_TYPE_CAP_MASK_PARA_VPORT_TC = 1 << 3, 3922 }; 3923 3924 struct mlx5_ifc_scheduling_context_bits { 3925 u8 element_type[0x8]; 3926 u8 reserved_at_8[0x18]; 3927 3928 u8 element_attributes[0x20]; 3929 3930 u8 parent_element_id[0x20]; 3931 3932 u8 reserved_at_60[0x40]; 3933 3934 u8 bw_share[0x20]; 3935 3936 u8 max_average_bw[0x20]; 3937 3938 u8 reserved_at_e0[0x120]; 3939 }; 3940 3941 struct mlx5_ifc_rqtc_bits { 3942 u8 reserved_at_0[0xa0]; 3943 3944 u8 reserved_at_a0[0x5]; 3945 u8 list_q_type[0x3]; 3946 u8 reserved_at_a8[0x8]; 3947 u8 rqt_max_size[0x10]; 3948 3949 u8 rq_vhca_id_format[0x1]; 3950 u8 reserved_at_c1[0xf]; 3951 u8 rqt_actual_size[0x10]; 3952 3953 u8 reserved_at_e0[0x6a0]; 3954 3955 union { 3956 DECLARE_FLEX_ARRAY(struct mlx5_ifc_rq_num_bits, rq_num); 3957 DECLARE_FLEX_ARRAY(struct mlx5_ifc_rq_vhca_bits, rq_vhca); 3958 }; 3959 }; 3960 3961 enum { 3962 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0, 3963 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1, 3964 }; 3965 3966 enum { 3967 MLX5_RQC_STATE_RST = 0x0, 3968 MLX5_RQC_STATE_RDY = 0x1, 3969 MLX5_RQC_STATE_ERR = 0x3, 3970 }; 3971 3972 enum { 3973 MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_BYTE = 0x0, 3974 MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_STRIDE = 0x1, 3975 MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_PAGE = 0x2, 3976 }; 3977 3978 enum { 3979 MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_NO_MATCH = 0x0, 3980 MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_EXTENDED = 0x1, 3981 MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_FIVE_TUPLE = 0x2, 3982 }; 3983 3984 struct mlx5_ifc_rqc_bits { 3985 u8 rlky[0x1]; 3986 u8 delay_drop_en[0x1]; 3987 u8 scatter_fcs[0x1]; 3988 u8 vsd[0x1]; 3989 u8 mem_rq_type[0x4]; 3990 u8 state[0x4]; 3991 u8 reserved_at_c[0x1]; 3992 u8 flush_in_error_en[0x1]; 3993 u8 hairpin[0x1]; 3994 u8 reserved_at_f[0xb]; 3995 u8 ts_format[0x2]; 3996 u8 reserved_at_1c[0x4]; 3997 3998 u8 reserved_at_20[0x8]; 3999 u8 user_index[0x18]; 4000 4001 u8 reserved_at_40[0x8]; 4002 u8 cqn[0x18]; 4003 4004 u8 counter_set_id[0x8]; 4005 u8 reserved_at_68[0x18]; 4006 4007 u8 reserved_at_80[0x8]; 4008 u8 rmpn[0x18]; 4009 4010 u8 reserved_at_a0[0x8]; 4011 u8 hairpin_peer_sq[0x18]; 4012 4013 u8 reserved_at_c0[0x10]; 4014 u8 hairpin_peer_vhca[0x10]; 4015 4016 u8 reserved_at_e0[0x46]; 4017 u8 shampo_no_match_alignment_granularity[0x2]; 4018 u8 reserved_at_128[0x6]; 4019 u8 shampo_match_criteria_type[0x2]; 4020 u8 reservation_timeout[0x10]; 4021 4022 u8 reserved_at_140[0x40]; 4023 4024 struct mlx5_ifc_wq_bits wq; 4025 }; 4026 4027 enum { 4028 MLX5_RMPC_STATE_RDY = 0x1, 4029 MLX5_RMPC_STATE_ERR = 0x3, 4030 }; 4031 4032 struct mlx5_ifc_rmpc_bits { 4033 u8 reserved_at_0[0x8]; 4034 u8 state[0x4]; 4035 u8 reserved_at_c[0x14]; 4036 4037 u8 basic_cyclic_rcv_wqe[0x1]; 4038 u8 reserved_at_21[0x1f]; 4039 4040 u8 reserved_at_40[0x140]; 4041 4042 struct mlx5_ifc_wq_bits wq; 4043 }; 4044 4045 enum { 4046 VHCA_ID_TYPE_HW = 0, 4047 VHCA_ID_TYPE_SW = 1, 4048 }; 4049 4050 struct mlx5_ifc_nic_vport_context_bits { 4051 u8 reserved_at_0[0x5]; 4052 u8 min_wqe_inline_mode[0x3]; 4053 u8 reserved_at_8[0x15]; 4054 u8 disable_mc_local_lb[0x1]; 4055 u8 disable_uc_local_lb[0x1]; 4056 u8 roce_en[0x1]; 4057 4058 u8 arm_change_event[0x1]; 4059 u8 reserved_at_21[0x1a]; 4060 u8 event_on_mtu[0x1]; 4061 u8 event_on_promisc_change[0x1]; 4062 u8 event_on_vlan_change[0x1]; 4063 u8 event_on_mc_address_change[0x1]; 4064 u8 event_on_uc_address_change[0x1]; 4065 4066 u8 vhca_id_type[0x1]; 4067 u8 reserved_at_41[0xb]; 4068 u8 affiliation_criteria[0x4]; 4069 u8 affiliated_vhca_id[0x10]; 4070 4071 u8 reserved_at_60[0xa0]; 4072 4073 u8 reserved_at_100[0x1]; 4074 u8 sd_group[0x3]; 4075 u8 reserved_at_104[0x1c]; 4076 4077 u8 reserved_at_120[0x10]; 4078 u8 mtu[0x10]; 4079 4080 u8 system_image_guid[0x40]; 4081 u8 port_guid[0x40]; 4082 u8 node_guid[0x40]; 4083 4084 u8 reserved_at_200[0x140]; 4085 u8 qkey_violation_counter[0x10]; 4086 u8 reserved_at_350[0x430]; 4087 4088 u8 promisc_uc[0x1]; 4089 u8 promisc_mc[0x1]; 4090 u8 promisc_all[0x1]; 4091 u8 reserved_at_783[0x2]; 4092 u8 allowed_list_type[0x3]; 4093 u8 reserved_at_788[0xc]; 4094 u8 allowed_list_size[0xc]; 4095 4096 struct mlx5_ifc_mac_address_layout_bits permanent_address; 4097 4098 u8 reserved_at_7e0[0x20]; 4099 4100 u8 current_uc_mac_address[][0x40]; 4101 }; 4102 4103 enum { 4104 MLX5_MKC_ACCESS_MODE_PA = 0x0, 4105 MLX5_MKC_ACCESS_MODE_MTT = 0x1, 4106 MLX5_MKC_ACCESS_MODE_KLMS = 0x2, 4107 MLX5_MKC_ACCESS_MODE_KSM = 0x3, 4108 MLX5_MKC_ACCESS_MODE_SW_ICM = 0x4, 4109 MLX5_MKC_ACCESS_MODE_MEMIC = 0x5, 4110 }; 4111 4112 struct mlx5_ifc_mkc_bits { 4113 u8 reserved_at_0[0x1]; 4114 u8 free[0x1]; 4115 u8 reserved_at_2[0x1]; 4116 u8 access_mode_4_2[0x3]; 4117 u8 reserved_at_6[0x7]; 4118 u8 relaxed_ordering_write[0x1]; 4119 u8 reserved_at_e[0x1]; 4120 u8 small_fence_on_rdma_read_response[0x1]; 4121 u8 umr_en[0x1]; 4122 u8 a[0x1]; 4123 u8 rw[0x1]; 4124 u8 rr[0x1]; 4125 u8 lw[0x1]; 4126 u8 lr[0x1]; 4127 u8 access_mode_1_0[0x2]; 4128 u8 reserved_at_18[0x2]; 4129 u8 ma_translation_mode[0x2]; 4130 u8 reserved_at_1c[0x4]; 4131 4132 u8 qpn[0x18]; 4133 u8 mkey_7_0[0x8]; 4134 4135 u8 reserved_at_40[0x20]; 4136 4137 u8 length64[0x1]; 4138 u8 bsf_en[0x1]; 4139 u8 sync_umr[0x1]; 4140 u8 reserved_at_63[0x2]; 4141 u8 expected_sigerr_count[0x1]; 4142 u8 reserved_at_66[0x1]; 4143 u8 en_rinval[0x1]; 4144 u8 pd[0x18]; 4145 4146 u8 start_addr[0x40]; 4147 4148 u8 len[0x40]; 4149 4150 u8 bsf_octword_size[0x20]; 4151 4152 u8 reserved_at_120[0x80]; 4153 4154 u8 translations_octword_size[0x20]; 4155 4156 u8 reserved_at_1c0[0x19]; 4157 u8 relaxed_ordering_read[0x1]; 4158 u8 reserved_at_1d9[0x1]; 4159 u8 log_page_size[0x5]; 4160 4161 u8 reserved_at_1e0[0x20]; 4162 }; 4163 4164 struct mlx5_ifc_pkey_bits { 4165 u8 reserved_at_0[0x10]; 4166 u8 pkey[0x10]; 4167 }; 4168 4169 struct mlx5_ifc_array128_auto_bits { 4170 u8 array128_auto[16][0x8]; 4171 }; 4172 4173 struct mlx5_ifc_hca_vport_context_bits { 4174 u8 field_select[0x20]; 4175 4176 u8 reserved_at_20[0xe0]; 4177 4178 u8 sm_virt_aware[0x1]; 4179 u8 has_smi[0x1]; 4180 u8 has_raw[0x1]; 4181 u8 grh_required[0x1]; 4182 u8 reserved_at_104[0xc]; 4183 u8 port_physical_state[0x4]; 4184 u8 vport_state_policy[0x4]; 4185 u8 port_state[0x4]; 4186 u8 vport_state[0x4]; 4187 4188 u8 reserved_at_120[0x20]; 4189 4190 u8 system_image_guid[0x40]; 4191 4192 u8 port_guid[0x40]; 4193 4194 u8 node_guid[0x40]; 4195 4196 u8 cap_mask1[0x20]; 4197 4198 u8 cap_mask1_field_select[0x20]; 4199 4200 u8 cap_mask2[0x20]; 4201 4202 u8 cap_mask2_field_select[0x20]; 4203 4204 u8 reserved_at_280[0x80]; 4205 4206 u8 lid[0x10]; 4207 u8 reserved_at_310[0x4]; 4208 u8 init_type_reply[0x4]; 4209 u8 lmc[0x3]; 4210 u8 subnet_timeout[0x5]; 4211 4212 u8 sm_lid[0x10]; 4213 u8 sm_sl[0x4]; 4214 u8 reserved_at_334[0xc]; 4215 4216 u8 qkey_violation_counter[0x10]; 4217 u8 pkey_violation_counter[0x10]; 4218 4219 u8 reserved_at_360[0xca0]; 4220 }; 4221 4222 struct mlx5_ifc_esw_vport_context_bits { 4223 u8 fdb_to_vport_reg_c[0x1]; 4224 u8 reserved_at_1[0x2]; 4225 u8 vport_svlan_strip[0x1]; 4226 u8 vport_cvlan_strip[0x1]; 4227 u8 vport_svlan_insert[0x1]; 4228 u8 vport_cvlan_insert[0x2]; 4229 u8 fdb_to_vport_reg_c_id[0x8]; 4230 u8 reserved_at_10[0x10]; 4231 4232 u8 reserved_at_20[0x20]; 4233 4234 u8 svlan_cfi[0x1]; 4235 u8 svlan_pcp[0x3]; 4236 u8 svlan_id[0xc]; 4237 u8 cvlan_cfi[0x1]; 4238 u8 cvlan_pcp[0x3]; 4239 u8 cvlan_id[0xc]; 4240 4241 u8 reserved_at_60[0x720]; 4242 4243 u8 sw_steering_vport_icm_address_rx[0x40]; 4244 4245 u8 sw_steering_vport_icm_address_tx[0x40]; 4246 }; 4247 4248 enum { 4249 MLX5_EQC_STATUS_OK = 0x0, 4250 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa, 4251 }; 4252 4253 enum { 4254 MLX5_EQC_ST_ARMED = 0x9, 4255 MLX5_EQC_ST_FIRED = 0xa, 4256 }; 4257 4258 struct mlx5_ifc_eqc_bits { 4259 u8 status[0x4]; 4260 u8 reserved_at_4[0x9]; 4261 u8 ec[0x1]; 4262 u8 oi[0x1]; 4263 u8 reserved_at_f[0x5]; 4264 u8 st[0x4]; 4265 u8 reserved_at_18[0x8]; 4266 4267 u8 reserved_at_20[0x20]; 4268 4269 u8 reserved_at_40[0x14]; 4270 u8 page_offset[0x6]; 4271 u8 reserved_at_5a[0x6]; 4272 4273 u8 reserved_at_60[0x3]; 4274 u8 log_eq_size[0x5]; 4275 u8 uar_page[0x18]; 4276 4277 u8 reserved_at_80[0x20]; 4278 4279 u8 reserved_at_a0[0x14]; 4280 u8 intr[0xc]; 4281 4282 u8 reserved_at_c0[0x3]; 4283 u8 log_page_size[0x5]; 4284 u8 reserved_at_c8[0x18]; 4285 4286 u8 reserved_at_e0[0x60]; 4287 4288 u8 reserved_at_140[0x8]; 4289 u8 consumer_counter[0x18]; 4290 4291 u8 reserved_at_160[0x8]; 4292 u8 producer_counter[0x18]; 4293 4294 u8 reserved_at_180[0x80]; 4295 }; 4296 4297 enum { 4298 MLX5_DCTC_STATE_ACTIVE = 0x0, 4299 MLX5_DCTC_STATE_DRAINING = 0x1, 4300 MLX5_DCTC_STATE_DRAINED = 0x2, 4301 }; 4302 4303 enum { 4304 MLX5_DCTC_CS_RES_DISABLE = 0x0, 4305 MLX5_DCTC_CS_RES_NA = 0x1, 4306 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2, 4307 }; 4308 4309 enum { 4310 MLX5_DCTC_MTU_256_BYTES = 0x1, 4311 MLX5_DCTC_MTU_512_BYTES = 0x2, 4312 MLX5_DCTC_MTU_1K_BYTES = 0x3, 4313 MLX5_DCTC_MTU_2K_BYTES = 0x4, 4314 MLX5_DCTC_MTU_4K_BYTES = 0x5, 4315 }; 4316 4317 struct mlx5_ifc_dctc_bits { 4318 u8 reserved_at_0[0x4]; 4319 u8 state[0x4]; 4320 u8 reserved_at_8[0x18]; 4321 4322 u8 reserved_at_20[0x8]; 4323 u8 user_index[0x18]; 4324 4325 u8 reserved_at_40[0x8]; 4326 u8 cqn[0x18]; 4327 4328 u8 counter_set_id[0x8]; 4329 u8 atomic_mode[0x4]; 4330 u8 rre[0x1]; 4331 u8 rwe[0x1]; 4332 u8 rae[0x1]; 4333 u8 atomic_like_write_en[0x1]; 4334 u8 latency_sensitive[0x1]; 4335 u8 rlky[0x1]; 4336 u8 free_ar[0x1]; 4337 u8 reserved_at_73[0xd]; 4338 4339 u8 reserved_at_80[0x8]; 4340 u8 cs_res[0x8]; 4341 u8 reserved_at_90[0x3]; 4342 u8 min_rnr_nak[0x5]; 4343 u8 reserved_at_98[0x8]; 4344 4345 u8 reserved_at_a0[0x8]; 4346 u8 srqn_xrqn[0x18]; 4347 4348 u8 reserved_at_c0[0x8]; 4349 u8 pd[0x18]; 4350 4351 u8 tclass[0x8]; 4352 u8 reserved_at_e8[0x4]; 4353 u8 flow_label[0x14]; 4354 4355 u8 dc_access_key[0x40]; 4356 4357 u8 reserved_at_140[0x5]; 4358 u8 mtu[0x3]; 4359 u8 port[0x8]; 4360 u8 pkey_index[0x10]; 4361 4362 u8 reserved_at_160[0x8]; 4363 u8 my_addr_index[0x8]; 4364 u8 reserved_at_170[0x8]; 4365 u8 hop_limit[0x8]; 4366 4367 u8 dc_access_key_violation_count[0x20]; 4368 4369 u8 reserved_at_1a0[0x14]; 4370 u8 dei_cfi[0x1]; 4371 u8 eth_prio[0x3]; 4372 u8 ecn[0x2]; 4373 u8 dscp[0x6]; 4374 4375 u8 reserved_at_1c0[0x20]; 4376 u8 ece[0x20]; 4377 }; 4378 4379 enum { 4380 MLX5_CQC_STATUS_OK = 0x0, 4381 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9, 4382 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa, 4383 }; 4384 4385 enum { 4386 MLX5_CQC_CQE_SZ_64_BYTES = 0x0, 4387 MLX5_CQC_CQE_SZ_128_BYTES = 0x1, 4388 }; 4389 4390 enum { 4391 MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED = 0x6, 4392 MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED = 0x9, 4393 MLX5_CQC_ST_FIRED = 0xa, 4394 }; 4395 4396 enum mlx5_cq_period_mode { 4397 MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0, 4398 MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1, 4399 MLX5_CQ_PERIOD_NUM_MODES, 4400 }; 4401 4402 struct mlx5_ifc_cqc_bits { 4403 u8 status[0x4]; 4404 u8 reserved_at_4[0x2]; 4405 u8 dbr_umem_valid[0x1]; 4406 u8 apu_cq[0x1]; 4407 u8 cqe_sz[0x3]; 4408 u8 cc[0x1]; 4409 u8 reserved_at_c[0x1]; 4410 u8 scqe_break_moderation_en[0x1]; 4411 u8 oi[0x1]; 4412 u8 cq_period_mode[0x2]; 4413 u8 cqe_comp_en[0x1]; 4414 u8 mini_cqe_res_format[0x2]; 4415 u8 st[0x4]; 4416 u8 reserved_at_18[0x6]; 4417 u8 cqe_compression_layout[0x2]; 4418 4419 u8 reserved_at_20[0x20]; 4420 4421 u8 reserved_at_40[0x14]; 4422 u8 page_offset[0x6]; 4423 u8 reserved_at_5a[0x6]; 4424 4425 u8 reserved_at_60[0x3]; 4426 u8 log_cq_size[0x5]; 4427 u8 uar_page[0x18]; 4428 4429 u8 reserved_at_80[0x4]; 4430 u8 cq_period[0xc]; 4431 u8 cq_max_count[0x10]; 4432 4433 u8 c_eqn_or_apu_element[0x20]; 4434 4435 u8 reserved_at_c0[0x3]; 4436 u8 log_page_size[0x5]; 4437 u8 reserved_at_c8[0x18]; 4438 4439 u8 reserved_at_e0[0x20]; 4440 4441 u8 reserved_at_100[0x8]; 4442 u8 last_notified_index[0x18]; 4443 4444 u8 reserved_at_120[0x8]; 4445 u8 last_solicit_index[0x18]; 4446 4447 u8 reserved_at_140[0x8]; 4448 u8 consumer_counter[0x18]; 4449 4450 u8 reserved_at_160[0x8]; 4451 u8 producer_counter[0x18]; 4452 4453 u8 reserved_at_180[0x40]; 4454 4455 u8 dbr_addr[0x40]; 4456 }; 4457 4458 union mlx5_ifc_cong_control_roce_ecn_auto_bits { 4459 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp; 4460 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp; 4461 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np; 4462 struct mlx5_ifc_cong_control_r_roce_general_bits cong_control_r_roce_general; 4463 u8 reserved_at_0[0x800]; 4464 }; 4465 4466 struct mlx5_ifc_query_adapter_param_block_bits { 4467 u8 reserved_at_0[0xc0]; 4468 4469 u8 reserved_at_c0[0x8]; 4470 u8 ieee_vendor_id[0x18]; 4471 4472 u8 reserved_at_e0[0x10]; 4473 u8 vsd_vendor_id[0x10]; 4474 4475 u8 vsd[208][0x8]; 4476 4477 u8 vsd_contd_psid[16][0x8]; 4478 }; 4479 4480 enum { 4481 MLX5_XRQC_STATE_GOOD = 0x0, 4482 MLX5_XRQC_STATE_ERROR = 0x1, 4483 }; 4484 4485 enum { 4486 MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0, 4487 MLX5_XRQC_TOPOLOGY_TAG_MATCHING = 0x1, 4488 }; 4489 4490 enum { 4491 MLX5_XRQC_OFFLOAD_RNDV = 0x1, 4492 }; 4493 4494 struct mlx5_ifc_tag_matching_topology_context_bits { 4495 u8 log_matching_list_sz[0x4]; 4496 u8 reserved_at_4[0xc]; 4497 u8 append_next_index[0x10]; 4498 4499 u8 sw_phase_cnt[0x10]; 4500 u8 hw_phase_cnt[0x10]; 4501 4502 u8 reserved_at_40[0x40]; 4503 }; 4504 4505 struct mlx5_ifc_xrqc_bits { 4506 u8 state[0x4]; 4507 u8 rlkey[0x1]; 4508 u8 reserved_at_5[0xf]; 4509 u8 topology[0x4]; 4510 u8 reserved_at_18[0x4]; 4511 u8 offload[0x4]; 4512 4513 u8 reserved_at_20[0x8]; 4514 u8 user_index[0x18]; 4515 4516 u8 reserved_at_40[0x8]; 4517 u8 cqn[0x18]; 4518 4519 u8 reserved_at_60[0xa0]; 4520 4521 struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context; 4522 4523 u8 reserved_at_180[0x280]; 4524 4525 struct mlx5_ifc_wq_bits wq; 4526 }; 4527 4528 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits { 4529 struct mlx5_ifc_modify_field_select_bits modify_field_select; 4530 struct mlx5_ifc_resize_field_select_bits resize_field_select; 4531 u8 reserved_at_0[0x20]; 4532 }; 4533 4534 union mlx5_ifc_field_select_802_1_r_roce_auto_bits { 4535 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp; 4536 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp; 4537 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np; 4538 u8 reserved_at_0[0x20]; 4539 }; 4540 4541 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits { 4542 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 4543 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 4544 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 4545 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 4546 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 4547 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 4548 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout; 4549 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout; 4550 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 4551 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 4552 struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs; 4553 u8 reserved_at_0[0x7c0]; 4554 }; 4555 4556 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits { 4557 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout; 4558 u8 reserved_at_0[0x7c0]; 4559 }; 4560 4561 union mlx5_ifc_event_auto_bits { 4562 struct mlx5_ifc_comp_event_bits comp_event; 4563 struct mlx5_ifc_dct_events_bits dct_events; 4564 struct mlx5_ifc_qp_events_bits qp_events; 4565 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event; 4566 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event; 4567 struct mlx5_ifc_cq_error_bits cq_error; 4568 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged; 4569 struct mlx5_ifc_port_state_change_event_bits port_state_change_event; 4570 struct mlx5_ifc_gpio_event_bits gpio_event; 4571 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event; 4572 struct mlx5_ifc_stall_vl_event_bits stall_vl_event; 4573 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event; 4574 u8 reserved_at_0[0xe0]; 4575 }; 4576 4577 struct mlx5_ifc_health_buffer_bits { 4578 u8 reserved_at_0[0x100]; 4579 4580 u8 assert_existptr[0x20]; 4581 4582 u8 assert_callra[0x20]; 4583 4584 u8 reserved_at_140[0x20]; 4585 4586 u8 time[0x20]; 4587 4588 u8 fw_version[0x20]; 4589 4590 u8 hw_id[0x20]; 4591 4592 u8 rfr[0x1]; 4593 u8 reserved_at_1c1[0x3]; 4594 u8 valid[0x1]; 4595 u8 severity[0x3]; 4596 u8 reserved_at_1c8[0x18]; 4597 4598 u8 irisc_index[0x8]; 4599 u8 synd[0x8]; 4600 u8 ext_synd[0x10]; 4601 }; 4602 4603 struct mlx5_ifc_register_loopback_control_bits { 4604 u8 no_lb[0x1]; 4605 u8 reserved_at_1[0x7]; 4606 u8 port[0x8]; 4607 u8 reserved_at_10[0x10]; 4608 4609 u8 reserved_at_20[0x60]; 4610 }; 4611 4612 struct mlx5_ifc_vport_tc_element_bits { 4613 u8 traffic_class[0x4]; 4614 u8 reserved_at_4[0xc]; 4615 u8 vport_number[0x10]; 4616 }; 4617 4618 struct mlx5_ifc_vport_element_bits { 4619 u8 reserved_at_0[0x10]; 4620 u8 vport_number[0x10]; 4621 }; 4622 4623 enum { 4624 TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0, 4625 TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1, 4626 TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2, 4627 }; 4628 4629 struct mlx5_ifc_tsar_element_bits { 4630 u8 reserved_at_0[0x8]; 4631 u8 tsar_type[0x8]; 4632 u8 reserved_at_10[0x10]; 4633 }; 4634 4635 enum { 4636 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0, 4637 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1, 4638 }; 4639 4640 struct mlx5_ifc_teardown_hca_out_bits { 4641 u8 status[0x8]; 4642 u8 reserved_at_8[0x18]; 4643 4644 u8 syndrome[0x20]; 4645 4646 u8 reserved_at_40[0x3f]; 4647 4648 u8 state[0x1]; 4649 }; 4650 4651 enum { 4652 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0, 4653 MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE = 0x1, 4654 MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN = 0x2, 4655 }; 4656 4657 struct mlx5_ifc_teardown_hca_in_bits { 4658 u8 opcode[0x10]; 4659 u8 reserved_at_10[0x10]; 4660 4661 u8 reserved_at_20[0x10]; 4662 u8 op_mod[0x10]; 4663 4664 u8 reserved_at_40[0x10]; 4665 u8 profile[0x10]; 4666 4667 u8 reserved_at_60[0x20]; 4668 }; 4669 4670 struct mlx5_ifc_sqerr2rts_qp_out_bits { 4671 u8 status[0x8]; 4672 u8 reserved_at_8[0x18]; 4673 4674 u8 syndrome[0x20]; 4675 4676 u8 reserved_at_40[0x40]; 4677 }; 4678 4679 struct mlx5_ifc_sqerr2rts_qp_in_bits { 4680 u8 opcode[0x10]; 4681 u8 uid[0x10]; 4682 4683 u8 reserved_at_20[0x10]; 4684 u8 op_mod[0x10]; 4685 4686 u8 reserved_at_40[0x8]; 4687 u8 qpn[0x18]; 4688 4689 u8 reserved_at_60[0x20]; 4690 4691 u8 opt_param_mask[0x20]; 4692 4693 u8 reserved_at_a0[0x20]; 4694 4695 struct mlx5_ifc_qpc_bits qpc; 4696 4697 u8 reserved_at_800[0x80]; 4698 }; 4699 4700 struct mlx5_ifc_sqd2rts_qp_out_bits { 4701 u8 status[0x8]; 4702 u8 reserved_at_8[0x18]; 4703 4704 u8 syndrome[0x20]; 4705 4706 u8 reserved_at_40[0x40]; 4707 }; 4708 4709 struct mlx5_ifc_sqd2rts_qp_in_bits { 4710 u8 opcode[0x10]; 4711 u8 uid[0x10]; 4712 4713 u8 reserved_at_20[0x10]; 4714 u8 op_mod[0x10]; 4715 4716 u8 reserved_at_40[0x8]; 4717 u8 qpn[0x18]; 4718 4719 u8 reserved_at_60[0x20]; 4720 4721 u8 opt_param_mask[0x20]; 4722 4723 u8 reserved_at_a0[0x20]; 4724 4725 struct mlx5_ifc_qpc_bits qpc; 4726 4727 u8 reserved_at_800[0x80]; 4728 }; 4729 4730 struct mlx5_ifc_set_roce_address_out_bits { 4731 u8 status[0x8]; 4732 u8 reserved_at_8[0x18]; 4733 4734 u8 syndrome[0x20]; 4735 4736 u8 reserved_at_40[0x40]; 4737 }; 4738 4739 struct mlx5_ifc_set_roce_address_in_bits { 4740 u8 opcode[0x10]; 4741 u8 reserved_at_10[0x10]; 4742 4743 u8 reserved_at_20[0x10]; 4744 u8 op_mod[0x10]; 4745 4746 u8 roce_address_index[0x10]; 4747 u8 reserved_at_50[0xc]; 4748 u8 vhca_port_num[0x4]; 4749 4750 u8 reserved_at_60[0x20]; 4751 4752 struct mlx5_ifc_roce_addr_layout_bits roce_address; 4753 }; 4754 4755 struct mlx5_ifc_set_mad_demux_out_bits { 4756 u8 status[0x8]; 4757 u8 reserved_at_8[0x18]; 4758 4759 u8 syndrome[0x20]; 4760 4761 u8 reserved_at_40[0x40]; 4762 }; 4763 4764 enum { 4765 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0, 4766 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2, 4767 }; 4768 4769 struct mlx5_ifc_set_mad_demux_in_bits { 4770 u8 opcode[0x10]; 4771 u8 reserved_at_10[0x10]; 4772 4773 u8 reserved_at_20[0x10]; 4774 u8 op_mod[0x10]; 4775 4776 u8 reserved_at_40[0x20]; 4777 4778 u8 reserved_at_60[0x6]; 4779 u8 demux_mode[0x2]; 4780 u8 reserved_at_68[0x18]; 4781 }; 4782 4783 struct mlx5_ifc_set_l2_table_entry_out_bits { 4784 u8 status[0x8]; 4785 u8 reserved_at_8[0x18]; 4786 4787 u8 syndrome[0x20]; 4788 4789 u8 reserved_at_40[0x40]; 4790 }; 4791 4792 struct mlx5_ifc_set_l2_table_entry_in_bits { 4793 u8 opcode[0x10]; 4794 u8 reserved_at_10[0x10]; 4795 4796 u8 reserved_at_20[0x10]; 4797 u8 op_mod[0x10]; 4798 4799 u8 reserved_at_40[0x60]; 4800 4801 u8 reserved_at_a0[0x8]; 4802 u8 table_index[0x18]; 4803 4804 u8 reserved_at_c0[0x20]; 4805 4806 u8 reserved_at_e0[0x10]; 4807 u8 silent_mode_valid[0x1]; 4808 u8 silent_mode[0x1]; 4809 u8 reserved_at_f2[0x1]; 4810 u8 vlan_valid[0x1]; 4811 u8 vlan[0xc]; 4812 4813 struct mlx5_ifc_mac_address_layout_bits mac_address; 4814 4815 u8 reserved_at_140[0xc0]; 4816 }; 4817 4818 struct mlx5_ifc_set_issi_out_bits { 4819 u8 status[0x8]; 4820 u8 reserved_at_8[0x18]; 4821 4822 u8 syndrome[0x20]; 4823 4824 u8 reserved_at_40[0x40]; 4825 }; 4826 4827 struct mlx5_ifc_set_issi_in_bits { 4828 u8 opcode[0x10]; 4829 u8 reserved_at_10[0x10]; 4830 4831 u8 reserved_at_20[0x10]; 4832 u8 op_mod[0x10]; 4833 4834 u8 reserved_at_40[0x10]; 4835 u8 current_issi[0x10]; 4836 4837 u8 reserved_at_60[0x20]; 4838 }; 4839 4840 struct mlx5_ifc_set_hca_cap_out_bits { 4841 u8 status[0x8]; 4842 u8 reserved_at_8[0x18]; 4843 4844 u8 syndrome[0x20]; 4845 4846 u8 reserved_at_40[0x40]; 4847 }; 4848 4849 struct mlx5_ifc_set_hca_cap_in_bits { 4850 u8 opcode[0x10]; 4851 u8 reserved_at_10[0x10]; 4852 4853 u8 reserved_at_20[0x10]; 4854 u8 op_mod[0x10]; 4855 4856 u8 other_function[0x1]; 4857 u8 ec_vf_function[0x1]; 4858 u8 reserved_at_42[0xe]; 4859 u8 function_id[0x10]; 4860 4861 u8 reserved_at_60[0x20]; 4862 4863 union mlx5_ifc_hca_cap_union_bits capability; 4864 }; 4865 4866 enum { 4867 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0, 4868 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1, 4869 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2, 4870 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3, 4871 MLX5_SET_FTE_MODIFY_ENABLE_MASK_IPSEC_OBJ_ID = 0x4 4872 }; 4873 4874 struct mlx5_ifc_set_fte_out_bits { 4875 u8 status[0x8]; 4876 u8 reserved_at_8[0x18]; 4877 4878 u8 syndrome[0x20]; 4879 4880 u8 reserved_at_40[0x40]; 4881 }; 4882 4883 struct mlx5_ifc_set_fte_in_bits { 4884 u8 opcode[0x10]; 4885 u8 reserved_at_10[0x10]; 4886 4887 u8 reserved_at_20[0x10]; 4888 u8 op_mod[0x10]; 4889 4890 u8 other_vport[0x1]; 4891 u8 reserved_at_41[0xf]; 4892 u8 vport_number[0x10]; 4893 4894 u8 reserved_at_60[0x20]; 4895 4896 u8 table_type[0x8]; 4897 u8 reserved_at_88[0x18]; 4898 4899 u8 reserved_at_a0[0x8]; 4900 u8 table_id[0x18]; 4901 4902 u8 ignore_flow_level[0x1]; 4903 u8 reserved_at_c1[0x17]; 4904 u8 modify_enable_mask[0x8]; 4905 4906 u8 reserved_at_e0[0x20]; 4907 4908 u8 flow_index[0x20]; 4909 4910 u8 reserved_at_120[0xe0]; 4911 4912 struct mlx5_ifc_flow_context_bits flow_context; 4913 }; 4914 4915 struct mlx5_ifc_rts2rts_qp_out_bits { 4916 u8 status[0x8]; 4917 u8 reserved_at_8[0x18]; 4918 4919 u8 syndrome[0x20]; 4920 4921 u8 reserved_at_40[0x20]; 4922 u8 ece[0x20]; 4923 }; 4924 4925 struct mlx5_ifc_rts2rts_qp_in_bits { 4926 u8 opcode[0x10]; 4927 u8 uid[0x10]; 4928 4929 u8 reserved_at_20[0x10]; 4930 u8 op_mod[0x10]; 4931 4932 u8 reserved_at_40[0x8]; 4933 u8 qpn[0x18]; 4934 4935 u8 reserved_at_60[0x20]; 4936 4937 u8 opt_param_mask[0x20]; 4938 4939 u8 ece[0x20]; 4940 4941 struct mlx5_ifc_qpc_bits qpc; 4942 4943 u8 reserved_at_800[0x80]; 4944 }; 4945 4946 struct mlx5_ifc_rtr2rts_qp_out_bits { 4947 u8 status[0x8]; 4948 u8 reserved_at_8[0x18]; 4949 4950 u8 syndrome[0x20]; 4951 4952 u8 reserved_at_40[0x20]; 4953 u8 ece[0x20]; 4954 }; 4955 4956 struct mlx5_ifc_rtr2rts_qp_in_bits { 4957 u8 opcode[0x10]; 4958 u8 uid[0x10]; 4959 4960 u8 reserved_at_20[0x10]; 4961 u8 op_mod[0x10]; 4962 4963 u8 reserved_at_40[0x8]; 4964 u8 qpn[0x18]; 4965 4966 u8 reserved_at_60[0x20]; 4967 4968 u8 opt_param_mask[0x20]; 4969 4970 u8 ece[0x20]; 4971 4972 struct mlx5_ifc_qpc_bits qpc; 4973 4974 u8 reserved_at_800[0x80]; 4975 }; 4976 4977 struct mlx5_ifc_rst2init_qp_out_bits { 4978 u8 status[0x8]; 4979 u8 reserved_at_8[0x18]; 4980 4981 u8 syndrome[0x20]; 4982 4983 u8 reserved_at_40[0x20]; 4984 u8 ece[0x20]; 4985 }; 4986 4987 struct mlx5_ifc_rst2init_qp_in_bits { 4988 u8 opcode[0x10]; 4989 u8 uid[0x10]; 4990 4991 u8 reserved_at_20[0x10]; 4992 u8 op_mod[0x10]; 4993 4994 u8 reserved_at_40[0x8]; 4995 u8 qpn[0x18]; 4996 4997 u8 reserved_at_60[0x20]; 4998 4999 u8 opt_param_mask[0x20]; 5000 5001 u8 ece[0x20]; 5002 5003 struct mlx5_ifc_qpc_bits qpc; 5004 5005 u8 reserved_at_800[0x80]; 5006 }; 5007 5008 struct mlx5_ifc_query_xrq_out_bits { 5009 u8 status[0x8]; 5010 u8 reserved_at_8[0x18]; 5011 5012 u8 syndrome[0x20]; 5013 5014 u8 reserved_at_40[0x40]; 5015 5016 struct mlx5_ifc_xrqc_bits xrq_context; 5017 }; 5018 5019 struct mlx5_ifc_query_xrq_in_bits { 5020 u8 opcode[0x10]; 5021 u8 reserved_at_10[0x10]; 5022 5023 u8 reserved_at_20[0x10]; 5024 u8 op_mod[0x10]; 5025 5026 u8 reserved_at_40[0x8]; 5027 u8 xrqn[0x18]; 5028 5029 u8 reserved_at_60[0x20]; 5030 }; 5031 5032 struct mlx5_ifc_query_xrc_srq_out_bits { 5033 u8 status[0x8]; 5034 u8 reserved_at_8[0x18]; 5035 5036 u8 syndrome[0x20]; 5037 5038 u8 reserved_at_40[0x40]; 5039 5040 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 5041 5042 u8 reserved_at_280[0x600]; 5043 5044 u8 pas[][0x40]; 5045 }; 5046 5047 struct mlx5_ifc_query_xrc_srq_in_bits { 5048 u8 opcode[0x10]; 5049 u8 reserved_at_10[0x10]; 5050 5051 u8 reserved_at_20[0x10]; 5052 u8 op_mod[0x10]; 5053 5054 u8 reserved_at_40[0x8]; 5055 u8 xrc_srqn[0x18]; 5056 5057 u8 reserved_at_60[0x20]; 5058 }; 5059 5060 enum { 5061 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0, 5062 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1, 5063 }; 5064 5065 struct mlx5_ifc_query_vport_state_out_bits { 5066 u8 status[0x8]; 5067 u8 reserved_at_8[0x18]; 5068 5069 u8 syndrome[0x20]; 5070 5071 u8 reserved_at_40[0x20]; 5072 5073 u8 reserved_at_60[0x18]; 5074 u8 admin_state[0x4]; 5075 u8 state[0x4]; 5076 }; 5077 5078 enum { 5079 MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT = 0x0, 5080 MLX5_VPORT_STATE_OP_MOD_ESW_VPORT = 0x1, 5081 MLX5_VPORT_STATE_OP_MOD_UPLINK = 0x2, 5082 }; 5083 5084 struct mlx5_ifc_arm_monitor_counter_in_bits { 5085 u8 opcode[0x10]; 5086 u8 uid[0x10]; 5087 5088 u8 reserved_at_20[0x10]; 5089 u8 op_mod[0x10]; 5090 5091 u8 reserved_at_40[0x20]; 5092 5093 u8 reserved_at_60[0x20]; 5094 }; 5095 5096 struct mlx5_ifc_arm_monitor_counter_out_bits { 5097 u8 status[0x8]; 5098 u8 reserved_at_8[0x18]; 5099 5100 u8 syndrome[0x20]; 5101 5102 u8 reserved_at_40[0x40]; 5103 }; 5104 5105 enum { 5106 MLX5_QUERY_MONITOR_CNT_TYPE_PPCNT = 0x0, 5107 MLX5_QUERY_MONITOR_CNT_TYPE_Q_COUNTER = 0x1, 5108 }; 5109 5110 enum mlx5_monitor_counter_ppcnt { 5111 MLX5_QUERY_MONITOR_PPCNT_IN_RANGE_LENGTH_ERRORS = 0x0, 5112 MLX5_QUERY_MONITOR_PPCNT_OUT_OF_RANGE_LENGTH_FIELD = 0x1, 5113 MLX5_QUERY_MONITOR_PPCNT_FRAME_TOO_LONG_ERRORS = 0x2, 5114 MLX5_QUERY_MONITOR_PPCNT_FRAME_CHECK_SEQUENCE_ERRORS = 0x3, 5115 MLX5_QUERY_MONITOR_PPCNT_ALIGNMENT_ERRORS = 0x4, 5116 MLX5_QUERY_MONITOR_PPCNT_IF_OUT_DISCARDS = 0x5, 5117 }; 5118 5119 enum { 5120 MLX5_QUERY_MONITOR_Q_COUNTER_RX_OUT_OF_BUFFER = 0x4, 5121 }; 5122 5123 struct mlx5_ifc_monitor_counter_output_bits { 5124 u8 reserved_at_0[0x4]; 5125 u8 type[0x4]; 5126 u8 reserved_at_8[0x8]; 5127 u8 counter[0x10]; 5128 5129 u8 counter_group_id[0x20]; 5130 }; 5131 5132 #define MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 (6) 5133 #define MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1 (1) 5134 #define MLX5_CMD_SET_MONITOR_NUM_COUNTER (MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 +\ 5135 MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1) 5136 5137 struct mlx5_ifc_set_monitor_counter_in_bits { 5138 u8 opcode[0x10]; 5139 u8 uid[0x10]; 5140 5141 u8 reserved_at_20[0x10]; 5142 u8 op_mod[0x10]; 5143 5144 u8 reserved_at_40[0x10]; 5145 u8 num_of_counters[0x10]; 5146 5147 u8 reserved_at_60[0x20]; 5148 5149 struct mlx5_ifc_monitor_counter_output_bits monitor_counter[MLX5_CMD_SET_MONITOR_NUM_COUNTER]; 5150 }; 5151 5152 struct mlx5_ifc_set_monitor_counter_out_bits { 5153 u8 status[0x8]; 5154 u8 reserved_at_8[0x18]; 5155 5156 u8 syndrome[0x20]; 5157 5158 u8 reserved_at_40[0x40]; 5159 }; 5160 5161 struct mlx5_ifc_query_vport_state_in_bits { 5162 u8 opcode[0x10]; 5163 u8 reserved_at_10[0x10]; 5164 5165 u8 reserved_at_20[0x10]; 5166 u8 op_mod[0x10]; 5167 5168 u8 other_vport[0x1]; 5169 u8 reserved_at_41[0xf]; 5170 u8 vport_number[0x10]; 5171 5172 u8 reserved_at_60[0x20]; 5173 }; 5174 5175 struct mlx5_ifc_query_vnic_env_out_bits { 5176 u8 status[0x8]; 5177 u8 reserved_at_8[0x18]; 5178 5179 u8 syndrome[0x20]; 5180 5181 u8 reserved_at_40[0x40]; 5182 5183 struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env; 5184 }; 5185 5186 enum { 5187 MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS = 0x0, 5188 }; 5189 5190 struct mlx5_ifc_query_vnic_env_in_bits { 5191 u8 opcode[0x10]; 5192 u8 reserved_at_10[0x10]; 5193 5194 u8 reserved_at_20[0x10]; 5195 u8 op_mod[0x10]; 5196 5197 u8 other_vport[0x1]; 5198 u8 reserved_at_41[0xf]; 5199 u8 vport_number[0x10]; 5200 5201 u8 reserved_at_60[0x20]; 5202 }; 5203 5204 struct mlx5_ifc_query_vport_counter_out_bits { 5205 u8 status[0x8]; 5206 u8 reserved_at_8[0x18]; 5207 5208 u8 syndrome[0x20]; 5209 5210 u8 reserved_at_40[0x40]; 5211 5212 struct mlx5_ifc_traffic_counter_bits received_errors; 5213 5214 struct mlx5_ifc_traffic_counter_bits transmit_errors; 5215 5216 struct mlx5_ifc_traffic_counter_bits received_ib_unicast; 5217 5218 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast; 5219 5220 struct mlx5_ifc_traffic_counter_bits received_ib_multicast; 5221 5222 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast; 5223 5224 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast; 5225 5226 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast; 5227 5228 struct mlx5_ifc_traffic_counter_bits received_eth_unicast; 5229 5230 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast; 5231 5232 struct mlx5_ifc_traffic_counter_bits received_eth_multicast; 5233 5234 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast; 5235 5236 struct mlx5_ifc_traffic_counter_bits local_loopback; 5237 5238 u8 reserved_at_700[0x980]; 5239 }; 5240 5241 enum { 5242 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0, 5243 }; 5244 5245 struct mlx5_ifc_query_vport_counter_in_bits { 5246 u8 opcode[0x10]; 5247 u8 reserved_at_10[0x10]; 5248 5249 u8 reserved_at_20[0x10]; 5250 u8 op_mod[0x10]; 5251 5252 u8 other_vport[0x1]; 5253 u8 reserved_at_41[0xb]; 5254 u8 port_num[0x4]; 5255 u8 vport_number[0x10]; 5256 5257 u8 reserved_at_60[0x60]; 5258 5259 u8 clear[0x1]; 5260 u8 reserved_at_c1[0x1f]; 5261 5262 u8 reserved_at_e0[0x20]; 5263 }; 5264 5265 struct mlx5_ifc_query_tis_out_bits { 5266 u8 status[0x8]; 5267 u8 reserved_at_8[0x18]; 5268 5269 u8 syndrome[0x20]; 5270 5271 u8 reserved_at_40[0x40]; 5272 5273 struct mlx5_ifc_tisc_bits tis_context; 5274 }; 5275 5276 struct mlx5_ifc_query_tis_in_bits { 5277 u8 opcode[0x10]; 5278 u8 reserved_at_10[0x10]; 5279 5280 u8 reserved_at_20[0x10]; 5281 u8 op_mod[0x10]; 5282 5283 u8 reserved_at_40[0x8]; 5284 u8 tisn[0x18]; 5285 5286 u8 reserved_at_60[0x20]; 5287 }; 5288 5289 struct mlx5_ifc_query_tir_out_bits { 5290 u8 status[0x8]; 5291 u8 reserved_at_8[0x18]; 5292 5293 u8 syndrome[0x20]; 5294 5295 u8 reserved_at_40[0xc0]; 5296 5297 struct mlx5_ifc_tirc_bits tir_context; 5298 }; 5299 5300 struct mlx5_ifc_query_tir_in_bits { 5301 u8 opcode[0x10]; 5302 u8 reserved_at_10[0x10]; 5303 5304 u8 reserved_at_20[0x10]; 5305 u8 op_mod[0x10]; 5306 5307 u8 reserved_at_40[0x8]; 5308 u8 tirn[0x18]; 5309 5310 u8 reserved_at_60[0x20]; 5311 }; 5312 5313 struct mlx5_ifc_query_srq_out_bits { 5314 u8 status[0x8]; 5315 u8 reserved_at_8[0x18]; 5316 5317 u8 syndrome[0x20]; 5318 5319 u8 reserved_at_40[0x40]; 5320 5321 struct mlx5_ifc_srqc_bits srq_context_entry; 5322 5323 u8 reserved_at_280[0x600]; 5324 5325 u8 pas[][0x40]; 5326 }; 5327 5328 struct mlx5_ifc_query_srq_in_bits { 5329 u8 opcode[0x10]; 5330 u8 reserved_at_10[0x10]; 5331 5332 u8 reserved_at_20[0x10]; 5333 u8 op_mod[0x10]; 5334 5335 u8 reserved_at_40[0x8]; 5336 u8 srqn[0x18]; 5337 5338 u8 reserved_at_60[0x20]; 5339 }; 5340 5341 struct mlx5_ifc_query_sq_out_bits { 5342 u8 status[0x8]; 5343 u8 reserved_at_8[0x18]; 5344 5345 u8 syndrome[0x20]; 5346 5347 u8 reserved_at_40[0xc0]; 5348 5349 struct mlx5_ifc_sqc_bits sq_context; 5350 }; 5351 5352 struct mlx5_ifc_query_sq_in_bits { 5353 u8 opcode[0x10]; 5354 u8 reserved_at_10[0x10]; 5355 5356 u8 reserved_at_20[0x10]; 5357 u8 op_mod[0x10]; 5358 5359 u8 reserved_at_40[0x8]; 5360 u8 sqn[0x18]; 5361 5362 u8 reserved_at_60[0x20]; 5363 }; 5364 5365 struct mlx5_ifc_query_special_contexts_out_bits { 5366 u8 status[0x8]; 5367 u8 reserved_at_8[0x18]; 5368 5369 u8 syndrome[0x20]; 5370 5371 u8 dump_fill_mkey[0x20]; 5372 5373 u8 resd_lkey[0x20]; 5374 5375 u8 null_mkey[0x20]; 5376 5377 u8 terminate_scatter_list_mkey[0x20]; 5378 5379 u8 repeated_mkey[0x20]; 5380 5381 u8 reserved_at_a0[0x20]; 5382 }; 5383 5384 struct mlx5_ifc_query_special_contexts_in_bits { 5385 u8 opcode[0x10]; 5386 u8 reserved_at_10[0x10]; 5387 5388 u8 reserved_at_20[0x10]; 5389 u8 op_mod[0x10]; 5390 5391 u8 reserved_at_40[0x40]; 5392 }; 5393 5394 struct mlx5_ifc_query_scheduling_element_out_bits { 5395 u8 opcode[0x10]; 5396 u8 reserved_at_10[0x10]; 5397 5398 u8 reserved_at_20[0x10]; 5399 u8 op_mod[0x10]; 5400 5401 u8 reserved_at_40[0xc0]; 5402 5403 struct mlx5_ifc_scheduling_context_bits scheduling_context; 5404 5405 u8 reserved_at_300[0x100]; 5406 }; 5407 5408 enum { 5409 SCHEDULING_HIERARCHY_E_SWITCH = 0x2, 5410 SCHEDULING_HIERARCHY_NIC = 0x3, 5411 }; 5412 5413 struct mlx5_ifc_query_scheduling_element_in_bits { 5414 u8 opcode[0x10]; 5415 u8 reserved_at_10[0x10]; 5416 5417 u8 reserved_at_20[0x10]; 5418 u8 op_mod[0x10]; 5419 5420 u8 scheduling_hierarchy[0x8]; 5421 u8 reserved_at_48[0x18]; 5422 5423 u8 scheduling_element_id[0x20]; 5424 5425 u8 reserved_at_80[0x180]; 5426 }; 5427 5428 struct mlx5_ifc_query_rqt_out_bits { 5429 u8 status[0x8]; 5430 u8 reserved_at_8[0x18]; 5431 5432 u8 syndrome[0x20]; 5433 5434 u8 reserved_at_40[0xc0]; 5435 5436 struct mlx5_ifc_rqtc_bits rqt_context; 5437 }; 5438 5439 struct mlx5_ifc_query_rqt_in_bits { 5440 u8 opcode[0x10]; 5441 u8 reserved_at_10[0x10]; 5442 5443 u8 reserved_at_20[0x10]; 5444 u8 op_mod[0x10]; 5445 5446 u8 reserved_at_40[0x8]; 5447 u8 rqtn[0x18]; 5448 5449 u8 reserved_at_60[0x20]; 5450 }; 5451 5452 struct mlx5_ifc_query_rq_out_bits { 5453 u8 status[0x8]; 5454 u8 reserved_at_8[0x18]; 5455 5456 u8 syndrome[0x20]; 5457 5458 u8 reserved_at_40[0xc0]; 5459 5460 struct mlx5_ifc_rqc_bits rq_context; 5461 }; 5462 5463 struct mlx5_ifc_query_rq_in_bits { 5464 u8 opcode[0x10]; 5465 u8 reserved_at_10[0x10]; 5466 5467 u8 reserved_at_20[0x10]; 5468 u8 op_mod[0x10]; 5469 5470 u8 reserved_at_40[0x8]; 5471 u8 rqn[0x18]; 5472 5473 u8 reserved_at_60[0x20]; 5474 }; 5475 5476 struct mlx5_ifc_query_roce_address_out_bits { 5477 u8 status[0x8]; 5478 u8 reserved_at_8[0x18]; 5479 5480 u8 syndrome[0x20]; 5481 5482 u8 reserved_at_40[0x40]; 5483 5484 struct mlx5_ifc_roce_addr_layout_bits roce_address; 5485 }; 5486 5487 struct mlx5_ifc_query_roce_address_in_bits { 5488 u8 opcode[0x10]; 5489 u8 reserved_at_10[0x10]; 5490 5491 u8 reserved_at_20[0x10]; 5492 u8 op_mod[0x10]; 5493 5494 u8 roce_address_index[0x10]; 5495 u8 reserved_at_50[0xc]; 5496 u8 vhca_port_num[0x4]; 5497 5498 u8 reserved_at_60[0x20]; 5499 }; 5500 5501 struct mlx5_ifc_query_rmp_out_bits { 5502 u8 status[0x8]; 5503 u8 reserved_at_8[0x18]; 5504 5505 u8 syndrome[0x20]; 5506 5507 u8 reserved_at_40[0xc0]; 5508 5509 struct mlx5_ifc_rmpc_bits rmp_context; 5510 }; 5511 5512 struct mlx5_ifc_query_rmp_in_bits { 5513 u8 opcode[0x10]; 5514 u8 reserved_at_10[0x10]; 5515 5516 u8 reserved_at_20[0x10]; 5517 u8 op_mod[0x10]; 5518 5519 u8 reserved_at_40[0x8]; 5520 u8 rmpn[0x18]; 5521 5522 u8 reserved_at_60[0x20]; 5523 }; 5524 5525 struct mlx5_ifc_cqe_error_syndrome_bits { 5526 u8 hw_error_syndrome[0x8]; 5527 u8 hw_syndrome_type[0x4]; 5528 u8 reserved_at_c[0x4]; 5529 u8 vendor_error_syndrome[0x8]; 5530 u8 syndrome[0x8]; 5531 }; 5532 5533 struct mlx5_ifc_qp_context_extension_bits { 5534 u8 reserved_at_0[0x60]; 5535 5536 struct mlx5_ifc_cqe_error_syndrome_bits error_syndrome; 5537 5538 u8 reserved_at_80[0x580]; 5539 }; 5540 5541 struct mlx5_ifc_qpc_extension_and_pas_list_in_bits { 5542 struct mlx5_ifc_qp_context_extension_bits qpc_data_extension; 5543 5544 u8 pas[0][0x40]; 5545 }; 5546 5547 struct mlx5_ifc_qp_pas_list_in_bits { 5548 struct mlx5_ifc_cmd_pas_bits pas[0]; 5549 }; 5550 5551 union mlx5_ifc_qp_pas_or_qpc_ext_and_pas_bits { 5552 struct mlx5_ifc_qp_pas_list_in_bits qp_pas_list; 5553 struct mlx5_ifc_qpc_extension_and_pas_list_in_bits qpc_ext_and_pas_list; 5554 }; 5555 5556 struct mlx5_ifc_query_qp_out_bits { 5557 u8 status[0x8]; 5558 u8 reserved_at_8[0x18]; 5559 5560 u8 syndrome[0x20]; 5561 5562 u8 reserved_at_40[0x40]; 5563 5564 u8 opt_param_mask[0x20]; 5565 5566 u8 ece[0x20]; 5567 5568 struct mlx5_ifc_qpc_bits qpc; 5569 5570 u8 reserved_at_800[0x80]; 5571 5572 union mlx5_ifc_qp_pas_or_qpc_ext_and_pas_bits qp_pas_or_qpc_ext_and_pas; 5573 }; 5574 5575 struct mlx5_ifc_query_qp_in_bits { 5576 u8 opcode[0x10]; 5577 u8 reserved_at_10[0x10]; 5578 5579 u8 reserved_at_20[0x10]; 5580 u8 op_mod[0x10]; 5581 5582 u8 qpc_ext[0x1]; 5583 u8 reserved_at_41[0x7]; 5584 u8 qpn[0x18]; 5585 5586 u8 reserved_at_60[0x20]; 5587 }; 5588 5589 struct mlx5_ifc_query_q_counter_out_bits { 5590 u8 status[0x8]; 5591 u8 reserved_at_8[0x18]; 5592 5593 u8 syndrome[0x20]; 5594 5595 u8 reserved_at_40[0x40]; 5596 5597 u8 rx_write_requests[0x20]; 5598 5599 u8 reserved_at_a0[0x20]; 5600 5601 u8 rx_read_requests[0x20]; 5602 5603 u8 reserved_at_e0[0x20]; 5604 5605 u8 rx_atomic_requests[0x20]; 5606 5607 u8 reserved_at_120[0x20]; 5608 5609 u8 rx_dct_connect[0x20]; 5610 5611 u8 reserved_at_160[0x20]; 5612 5613 u8 out_of_buffer[0x20]; 5614 5615 u8 reserved_at_1a0[0x20]; 5616 5617 u8 out_of_sequence[0x20]; 5618 5619 u8 reserved_at_1e0[0x20]; 5620 5621 u8 duplicate_request[0x20]; 5622 5623 u8 reserved_at_220[0x20]; 5624 5625 u8 rnr_nak_retry_err[0x20]; 5626 5627 u8 reserved_at_260[0x20]; 5628 5629 u8 packet_seq_err[0x20]; 5630 5631 u8 reserved_at_2a0[0x20]; 5632 5633 u8 implied_nak_seq_err[0x20]; 5634 5635 u8 reserved_at_2e0[0x20]; 5636 5637 u8 local_ack_timeout_err[0x20]; 5638 5639 u8 reserved_at_320[0xa0]; 5640 5641 u8 resp_local_length_error[0x20]; 5642 5643 u8 req_local_length_error[0x20]; 5644 5645 u8 resp_local_qp_error[0x20]; 5646 5647 u8 local_operation_error[0x20]; 5648 5649 u8 resp_local_protection[0x20]; 5650 5651 u8 req_local_protection[0x20]; 5652 5653 u8 resp_cqe_error[0x20]; 5654 5655 u8 req_cqe_error[0x20]; 5656 5657 u8 req_mw_binding[0x20]; 5658 5659 u8 req_bad_response[0x20]; 5660 5661 u8 req_remote_invalid_request[0x20]; 5662 5663 u8 resp_remote_invalid_request[0x20]; 5664 5665 u8 req_remote_access_errors[0x20]; 5666 5667 u8 resp_remote_access_errors[0x20]; 5668 5669 u8 req_remote_operation_errors[0x20]; 5670 5671 u8 req_transport_retries_exceeded[0x20]; 5672 5673 u8 cq_overflow[0x20]; 5674 5675 u8 resp_cqe_flush_error[0x20]; 5676 5677 u8 req_cqe_flush_error[0x20]; 5678 5679 u8 reserved_at_620[0x20]; 5680 5681 u8 roce_adp_retrans[0x20]; 5682 5683 u8 roce_adp_retrans_to[0x20]; 5684 5685 u8 roce_slow_restart[0x20]; 5686 5687 u8 roce_slow_restart_cnps[0x20]; 5688 5689 u8 roce_slow_restart_trans[0x20]; 5690 5691 u8 reserved_at_6e0[0x120]; 5692 }; 5693 5694 struct mlx5_ifc_query_q_counter_in_bits { 5695 u8 opcode[0x10]; 5696 u8 reserved_at_10[0x10]; 5697 5698 u8 reserved_at_20[0x10]; 5699 u8 op_mod[0x10]; 5700 5701 u8 other_vport[0x1]; 5702 u8 reserved_at_41[0xf]; 5703 u8 vport_number[0x10]; 5704 5705 u8 reserved_at_60[0x60]; 5706 5707 u8 clear[0x1]; 5708 u8 aggregate[0x1]; 5709 u8 reserved_at_c2[0x1e]; 5710 5711 u8 reserved_at_e0[0x18]; 5712 u8 counter_set_id[0x8]; 5713 }; 5714 5715 struct mlx5_ifc_query_pages_out_bits { 5716 u8 status[0x8]; 5717 u8 reserved_at_8[0x18]; 5718 5719 u8 syndrome[0x20]; 5720 5721 u8 embedded_cpu_function[0x1]; 5722 u8 reserved_at_41[0xf]; 5723 u8 function_id[0x10]; 5724 5725 u8 num_pages[0x20]; 5726 }; 5727 5728 enum { 5729 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1, 5730 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2, 5731 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3, 5732 }; 5733 5734 struct mlx5_ifc_query_pages_in_bits { 5735 u8 opcode[0x10]; 5736 u8 reserved_at_10[0x10]; 5737 5738 u8 reserved_at_20[0x10]; 5739 u8 op_mod[0x10]; 5740 5741 u8 embedded_cpu_function[0x1]; 5742 u8 reserved_at_41[0xf]; 5743 u8 function_id[0x10]; 5744 5745 u8 reserved_at_60[0x20]; 5746 }; 5747 5748 struct mlx5_ifc_query_nic_vport_context_out_bits { 5749 u8 status[0x8]; 5750 u8 reserved_at_8[0x18]; 5751 5752 u8 syndrome[0x20]; 5753 5754 u8 reserved_at_40[0x40]; 5755 5756 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 5757 }; 5758 5759 struct mlx5_ifc_query_nic_vport_context_in_bits { 5760 u8 opcode[0x10]; 5761 u8 reserved_at_10[0x10]; 5762 5763 u8 reserved_at_20[0x10]; 5764 u8 op_mod[0x10]; 5765 5766 u8 other_vport[0x1]; 5767 u8 reserved_at_41[0xf]; 5768 u8 vport_number[0x10]; 5769 5770 u8 reserved_at_60[0x5]; 5771 u8 allowed_list_type[0x3]; 5772 u8 reserved_at_68[0x18]; 5773 }; 5774 5775 struct mlx5_ifc_query_mkey_out_bits { 5776 u8 status[0x8]; 5777 u8 reserved_at_8[0x18]; 5778 5779 u8 syndrome[0x20]; 5780 5781 u8 reserved_at_40[0x40]; 5782 5783 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 5784 5785 u8 reserved_at_280[0x600]; 5786 5787 u8 bsf0_klm0_pas_mtt0_1[16][0x8]; 5788 5789 u8 bsf1_klm1_pas_mtt2_3[16][0x8]; 5790 }; 5791 5792 struct mlx5_ifc_query_mkey_in_bits { 5793 u8 opcode[0x10]; 5794 u8 reserved_at_10[0x10]; 5795 5796 u8 reserved_at_20[0x10]; 5797 u8 op_mod[0x10]; 5798 5799 u8 reserved_at_40[0x8]; 5800 u8 mkey_index[0x18]; 5801 5802 u8 pg_access[0x1]; 5803 u8 reserved_at_61[0x1f]; 5804 }; 5805 5806 struct mlx5_ifc_query_mad_demux_out_bits { 5807 u8 status[0x8]; 5808 u8 reserved_at_8[0x18]; 5809 5810 u8 syndrome[0x20]; 5811 5812 u8 reserved_at_40[0x40]; 5813 5814 u8 mad_dumux_parameters_block[0x20]; 5815 }; 5816 5817 struct mlx5_ifc_query_mad_demux_in_bits { 5818 u8 opcode[0x10]; 5819 u8 reserved_at_10[0x10]; 5820 5821 u8 reserved_at_20[0x10]; 5822 u8 op_mod[0x10]; 5823 5824 u8 reserved_at_40[0x40]; 5825 }; 5826 5827 struct mlx5_ifc_query_l2_table_entry_out_bits { 5828 u8 status[0x8]; 5829 u8 reserved_at_8[0x18]; 5830 5831 u8 syndrome[0x20]; 5832 5833 u8 reserved_at_40[0xa0]; 5834 5835 u8 reserved_at_e0[0x13]; 5836 u8 vlan_valid[0x1]; 5837 u8 vlan[0xc]; 5838 5839 struct mlx5_ifc_mac_address_layout_bits mac_address; 5840 5841 u8 reserved_at_140[0xc0]; 5842 }; 5843 5844 struct mlx5_ifc_query_l2_table_entry_in_bits { 5845 u8 opcode[0x10]; 5846 u8 reserved_at_10[0x10]; 5847 5848 u8 reserved_at_20[0x10]; 5849 u8 op_mod[0x10]; 5850 5851 u8 reserved_at_40[0x60]; 5852 5853 u8 reserved_at_a0[0x8]; 5854 u8 table_index[0x18]; 5855 5856 u8 reserved_at_c0[0x140]; 5857 }; 5858 5859 struct mlx5_ifc_query_issi_out_bits { 5860 u8 status[0x8]; 5861 u8 reserved_at_8[0x18]; 5862 5863 u8 syndrome[0x20]; 5864 5865 u8 reserved_at_40[0x10]; 5866 u8 current_issi[0x10]; 5867 5868 u8 reserved_at_60[0xa0]; 5869 5870 u8 reserved_at_100[76][0x8]; 5871 u8 supported_issi_dw0[0x20]; 5872 }; 5873 5874 struct mlx5_ifc_query_issi_in_bits { 5875 u8 opcode[0x10]; 5876 u8 reserved_at_10[0x10]; 5877 5878 u8 reserved_at_20[0x10]; 5879 u8 op_mod[0x10]; 5880 5881 u8 reserved_at_40[0x40]; 5882 }; 5883 5884 struct mlx5_ifc_set_driver_version_out_bits { 5885 u8 status[0x8]; 5886 u8 reserved_0[0x18]; 5887 5888 u8 syndrome[0x20]; 5889 u8 reserved_1[0x40]; 5890 }; 5891 5892 struct mlx5_ifc_set_driver_version_in_bits { 5893 u8 opcode[0x10]; 5894 u8 reserved_0[0x10]; 5895 5896 u8 reserved_1[0x10]; 5897 u8 op_mod[0x10]; 5898 5899 u8 reserved_2[0x40]; 5900 u8 driver_version[64][0x8]; 5901 }; 5902 5903 struct mlx5_ifc_query_hca_vport_pkey_out_bits { 5904 u8 status[0x8]; 5905 u8 reserved_at_8[0x18]; 5906 5907 u8 syndrome[0x20]; 5908 5909 u8 reserved_at_40[0x40]; 5910 5911 struct mlx5_ifc_pkey_bits pkey[]; 5912 }; 5913 5914 struct mlx5_ifc_query_hca_vport_pkey_in_bits { 5915 u8 opcode[0x10]; 5916 u8 reserved_at_10[0x10]; 5917 5918 u8 reserved_at_20[0x10]; 5919 u8 op_mod[0x10]; 5920 5921 u8 other_vport[0x1]; 5922 u8 reserved_at_41[0xb]; 5923 u8 port_num[0x4]; 5924 u8 vport_number[0x10]; 5925 5926 u8 reserved_at_60[0x10]; 5927 u8 pkey_index[0x10]; 5928 }; 5929 5930 enum { 5931 MLX5_HCA_VPORT_SEL_PORT_GUID = 1 << 0, 5932 MLX5_HCA_VPORT_SEL_NODE_GUID = 1 << 1, 5933 MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2, 5934 }; 5935 5936 struct mlx5_ifc_query_hca_vport_gid_out_bits { 5937 u8 status[0x8]; 5938 u8 reserved_at_8[0x18]; 5939 5940 u8 syndrome[0x20]; 5941 5942 u8 reserved_at_40[0x20]; 5943 5944 u8 gids_num[0x10]; 5945 u8 reserved_at_70[0x10]; 5946 5947 struct mlx5_ifc_array128_auto_bits gid[]; 5948 }; 5949 5950 struct mlx5_ifc_query_hca_vport_gid_in_bits { 5951 u8 opcode[0x10]; 5952 u8 reserved_at_10[0x10]; 5953 5954 u8 reserved_at_20[0x10]; 5955 u8 op_mod[0x10]; 5956 5957 u8 other_vport[0x1]; 5958 u8 reserved_at_41[0xb]; 5959 u8 port_num[0x4]; 5960 u8 vport_number[0x10]; 5961 5962 u8 reserved_at_60[0x10]; 5963 u8 gid_index[0x10]; 5964 }; 5965 5966 struct mlx5_ifc_query_hca_vport_context_out_bits { 5967 u8 status[0x8]; 5968 u8 reserved_at_8[0x18]; 5969 5970 u8 syndrome[0x20]; 5971 5972 u8 reserved_at_40[0x40]; 5973 5974 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 5975 }; 5976 5977 struct mlx5_ifc_query_hca_vport_context_in_bits { 5978 u8 opcode[0x10]; 5979 u8 reserved_at_10[0x10]; 5980 5981 u8 reserved_at_20[0x10]; 5982 u8 op_mod[0x10]; 5983 5984 u8 other_vport[0x1]; 5985 u8 reserved_at_41[0xb]; 5986 u8 port_num[0x4]; 5987 u8 vport_number[0x10]; 5988 5989 u8 reserved_at_60[0x20]; 5990 }; 5991 5992 struct mlx5_ifc_query_hca_cap_out_bits { 5993 u8 status[0x8]; 5994 u8 reserved_at_8[0x18]; 5995 5996 u8 syndrome[0x20]; 5997 5998 u8 reserved_at_40[0x40]; 5999 6000 union mlx5_ifc_hca_cap_union_bits capability; 6001 }; 6002 6003 struct mlx5_ifc_query_hca_cap_in_bits { 6004 u8 opcode[0x10]; 6005 u8 reserved_at_10[0x10]; 6006 6007 u8 reserved_at_20[0x10]; 6008 u8 op_mod[0x10]; 6009 6010 u8 other_function[0x1]; 6011 u8 ec_vf_function[0x1]; 6012 u8 reserved_at_42[0xe]; 6013 u8 function_id[0x10]; 6014 6015 u8 reserved_at_60[0x20]; 6016 }; 6017 6018 struct mlx5_ifc_other_hca_cap_bits { 6019 u8 roce[0x1]; 6020 u8 reserved_at_1[0x27f]; 6021 }; 6022 6023 struct mlx5_ifc_query_other_hca_cap_out_bits { 6024 u8 status[0x8]; 6025 u8 reserved_at_8[0x18]; 6026 6027 u8 syndrome[0x20]; 6028 6029 u8 reserved_at_40[0x40]; 6030 6031 struct mlx5_ifc_other_hca_cap_bits other_capability; 6032 }; 6033 6034 struct mlx5_ifc_query_other_hca_cap_in_bits { 6035 u8 opcode[0x10]; 6036 u8 reserved_at_10[0x10]; 6037 6038 u8 reserved_at_20[0x10]; 6039 u8 op_mod[0x10]; 6040 6041 u8 reserved_at_40[0x10]; 6042 u8 function_id[0x10]; 6043 6044 u8 reserved_at_60[0x20]; 6045 }; 6046 6047 struct mlx5_ifc_modify_other_hca_cap_out_bits { 6048 u8 status[0x8]; 6049 u8 reserved_at_8[0x18]; 6050 6051 u8 syndrome[0x20]; 6052 6053 u8 reserved_at_40[0x40]; 6054 }; 6055 6056 struct mlx5_ifc_modify_other_hca_cap_in_bits { 6057 u8 opcode[0x10]; 6058 u8 reserved_at_10[0x10]; 6059 6060 u8 reserved_at_20[0x10]; 6061 u8 op_mod[0x10]; 6062 6063 u8 reserved_at_40[0x10]; 6064 u8 function_id[0x10]; 6065 u8 field_select[0x20]; 6066 6067 struct mlx5_ifc_other_hca_cap_bits other_capability; 6068 }; 6069 6070 struct mlx5_ifc_flow_table_context_bits { 6071 u8 reformat_en[0x1]; 6072 u8 decap_en[0x1]; 6073 u8 sw_owner[0x1]; 6074 u8 termination_table[0x1]; 6075 u8 table_miss_action[0x4]; 6076 u8 level[0x8]; 6077 u8 reserved_at_10[0x8]; 6078 u8 log_size[0x8]; 6079 6080 u8 reserved_at_20[0x8]; 6081 u8 table_miss_id[0x18]; 6082 6083 u8 reserved_at_40[0x8]; 6084 u8 lag_master_next_table_id[0x18]; 6085 6086 u8 reserved_at_60[0x60]; 6087 6088 u8 sw_owner_icm_root_1[0x40]; 6089 6090 u8 sw_owner_icm_root_0[0x40]; 6091 6092 }; 6093 6094 struct mlx5_ifc_query_flow_table_out_bits { 6095 u8 status[0x8]; 6096 u8 reserved_at_8[0x18]; 6097 6098 u8 syndrome[0x20]; 6099 6100 u8 reserved_at_40[0x80]; 6101 6102 struct mlx5_ifc_flow_table_context_bits flow_table_context; 6103 }; 6104 6105 struct mlx5_ifc_query_flow_table_in_bits { 6106 u8 opcode[0x10]; 6107 u8 reserved_at_10[0x10]; 6108 6109 u8 reserved_at_20[0x10]; 6110 u8 op_mod[0x10]; 6111 6112 u8 reserved_at_40[0x40]; 6113 6114 u8 table_type[0x8]; 6115 u8 reserved_at_88[0x18]; 6116 6117 u8 reserved_at_a0[0x8]; 6118 u8 table_id[0x18]; 6119 6120 u8 reserved_at_c0[0x140]; 6121 }; 6122 6123 struct mlx5_ifc_query_fte_out_bits { 6124 u8 status[0x8]; 6125 u8 reserved_at_8[0x18]; 6126 6127 u8 syndrome[0x20]; 6128 6129 u8 reserved_at_40[0x1c0]; 6130 6131 struct mlx5_ifc_flow_context_bits flow_context; 6132 }; 6133 6134 struct mlx5_ifc_query_fte_in_bits { 6135 u8 opcode[0x10]; 6136 u8 reserved_at_10[0x10]; 6137 6138 u8 reserved_at_20[0x10]; 6139 u8 op_mod[0x10]; 6140 6141 u8 reserved_at_40[0x40]; 6142 6143 u8 table_type[0x8]; 6144 u8 reserved_at_88[0x18]; 6145 6146 u8 reserved_at_a0[0x8]; 6147 u8 table_id[0x18]; 6148 6149 u8 reserved_at_c0[0x40]; 6150 6151 u8 flow_index[0x20]; 6152 6153 u8 reserved_at_120[0xe0]; 6154 }; 6155 6156 struct mlx5_ifc_match_definer_format_0_bits { 6157 u8 reserved_at_0[0x100]; 6158 6159 u8 metadata_reg_c_0[0x20]; 6160 6161 u8 metadata_reg_c_1[0x20]; 6162 6163 u8 outer_dmac_47_16[0x20]; 6164 6165 u8 outer_dmac_15_0[0x10]; 6166 u8 outer_ethertype[0x10]; 6167 6168 u8 reserved_at_180[0x1]; 6169 u8 sx_sniffer[0x1]; 6170 u8 functional_lb[0x1]; 6171 u8 outer_ip_frag[0x1]; 6172 u8 outer_qp_type[0x2]; 6173 u8 outer_encap_type[0x2]; 6174 u8 port_number[0x2]; 6175 u8 outer_l3_type[0x2]; 6176 u8 outer_l4_type[0x2]; 6177 u8 outer_first_vlan_type[0x2]; 6178 u8 outer_first_vlan_prio[0x3]; 6179 u8 outer_first_vlan_cfi[0x1]; 6180 u8 outer_first_vlan_vid[0xc]; 6181 6182 u8 outer_l4_type_ext[0x4]; 6183 u8 reserved_at_1a4[0x2]; 6184 u8 outer_ipsec_layer[0x2]; 6185 u8 outer_l2_type[0x2]; 6186 u8 force_lb[0x1]; 6187 u8 outer_l2_ok[0x1]; 6188 u8 outer_l3_ok[0x1]; 6189 u8 outer_l4_ok[0x1]; 6190 u8 outer_second_vlan_type[0x2]; 6191 u8 outer_second_vlan_prio[0x3]; 6192 u8 outer_second_vlan_cfi[0x1]; 6193 u8 outer_second_vlan_vid[0xc]; 6194 6195 u8 outer_smac_47_16[0x20]; 6196 6197 u8 outer_smac_15_0[0x10]; 6198 u8 inner_ipv4_checksum_ok[0x1]; 6199 u8 inner_l4_checksum_ok[0x1]; 6200 u8 outer_ipv4_checksum_ok[0x1]; 6201 u8 outer_l4_checksum_ok[0x1]; 6202 u8 inner_l3_ok[0x1]; 6203 u8 inner_l4_ok[0x1]; 6204 u8 outer_l3_ok_duplicate[0x1]; 6205 u8 outer_l4_ok_duplicate[0x1]; 6206 u8 outer_tcp_cwr[0x1]; 6207 u8 outer_tcp_ece[0x1]; 6208 u8 outer_tcp_urg[0x1]; 6209 u8 outer_tcp_ack[0x1]; 6210 u8 outer_tcp_psh[0x1]; 6211 u8 outer_tcp_rst[0x1]; 6212 u8 outer_tcp_syn[0x1]; 6213 u8 outer_tcp_fin[0x1]; 6214 }; 6215 6216 struct mlx5_ifc_match_definer_format_22_bits { 6217 u8 reserved_at_0[0x100]; 6218 6219 u8 outer_ip_src_addr[0x20]; 6220 6221 u8 outer_ip_dest_addr[0x20]; 6222 6223 u8 outer_l4_sport[0x10]; 6224 u8 outer_l4_dport[0x10]; 6225 6226 u8 reserved_at_160[0x1]; 6227 u8 sx_sniffer[0x1]; 6228 u8 functional_lb[0x1]; 6229 u8 outer_ip_frag[0x1]; 6230 u8 outer_qp_type[0x2]; 6231 u8 outer_encap_type[0x2]; 6232 u8 port_number[0x2]; 6233 u8 outer_l3_type[0x2]; 6234 u8 outer_l4_type[0x2]; 6235 u8 outer_first_vlan_type[0x2]; 6236 u8 outer_first_vlan_prio[0x3]; 6237 u8 outer_first_vlan_cfi[0x1]; 6238 u8 outer_first_vlan_vid[0xc]; 6239 6240 u8 metadata_reg_c_0[0x20]; 6241 6242 u8 outer_dmac_47_16[0x20]; 6243 6244 u8 outer_smac_47_16[0x20]; 6245 6246 u8 outer_smac_15_0[0x10]; 6247 u8 outer_dmac_15_0[0x10]; 6248 }; 6249 6250 struct mlx5_ifc_match_definer_format_23_bits { 6251 u8 reserved_at_0[0x100]; 6252 6253 u8 inner_ip_src_addr[0x20]; 6254 6255 u8 inner_ip_dest_addr[0x20]; 6256 6257 u8 inner_l4_sport[0x10]; 6258 u8 inner_l4_dport[0x10]; 6259 6260 u8 reserved_at_160[0x1]; 6261 u8 sx_sniffer[0x1]; 6262 u8 functional_lb[0x1]; 6263 u8 inner_ip_frag[0x1]; 6264 u8 inner_qp_type[0x2]; 6265 u8 inner_encap_type[0x2]; 6266 u8 port_number[0x2]; 6267 u8 inner_l3_type[0x2]; 6268 u8 inner_l4_type[0x2]; 6269 u8 inner_first_vlan_type[0x2]; 6270 u8 inner_first_vlan_prio[0x3]; 6271 u8 inner_first_vlan_cfi[0x1]; 6272 u8 inner_first_vlan_vid[0xc]; 6273 6274 u8 tunnel_header_0[0x20]; 6275 6276 u8 inner_dmac_47_16[0x20]; 6277 6278 u8 inner_smac_47_16[0x20]; 6279 6280 u8 inner_smac_15_0[0x10]; 6281 u8 inner_dmac_15_0[0x10]; 6282 }; 6283 6284 struct mlx5_ifc_match_definer_format_29_bits { 6285 u8 reserved_at_0[0xc0]; 6286 6287 u8 outer_ip_dest_addr[0x80]; 6288 6289 u8 outer_ip_src_addr[0x80]; 6290 6291 u8 outer_l4_sport[0x10]; 6292 u8 outer_l4_dport[0x10]; 6293 6294 u8 reserved_at_1e0[0x20]; 6295 }; 6296 6297 struct mlx5_ifc_match_definer_format_30_bits { 6298 u8 reserved_at_0[0xa0]; 6299 6300 u8 outer_ip_dest_addr[0x80]; 6301 6302 u8 outer_ip_src_addr[0x80]; 6303 6304 u8 outer_dmac_47_16[0x20]; 6305 6306 u8 outer_smac_47_16[0x20]; 6307 6308 u8 outer_smac_15_0[0x10]; 6309 u8 outer_dmac_15_0[0x10]; 6310 }; 6311 6312 struct mlx5_ifc_match_definer_format_31_bits { 6313 u8 reserved_at_0[0xc0]; 6314 6315 u8 inner_ip_dest_addr[0x80]; 6316 6317 u8 inner_ip_src_addr[0x80]; 6318 6319 u8 inner_l4_sport[0x10]; 6320 u8 inner_l4_dport[0x10]; 6321 6322 u8 reserved_at_1e0[0x20]; 6323 }; 6324 6325 struct mlx5_ifc_match_definer_format_32_bits { 6326 u8 reserved_at_0[0xa0]; 6327 6328 u8 inner_ip_dest_addr[0x80]; 6329 6330 u8 inner_ip_src_addr[0x80]; 6331 6332 u8 inner_dmac_47_16[0x20]; 6333 6334 u8 inner_smac_47_16[0x20]; 6335 6336 u8 inner_smac_15_0[0x10]; 6337 u8 inner_dmac_15_0[0x10]; 6338 }; 6339 6340 enum { 6341 MLX5_IFC_DEFINER_FORMAT_ID_SELECT = 61, 6342 }; 6343 6344 #define MLX5_IFC_DEFINER_FORMAT_OFFSET_UNUSED 0x0 6345 #define MLX5_IFC_DEFINER_FORMAT_OFFSET_OUTER_ETH_PKT_LEN 0x48 6346 #define MLX5_IFC_DEFINER_DW_SELECTORS_NUM 9 6347 #define MLX5_IFC_DEFINER_BYTE_SELECTORS_NUM 8 6348 6349 struct mlx5_ifc_match_definer_match_mask_bits { 6350 u8 reserved_at_1c0[5][0x20]; 6351 u8 match_dw_8[0x20]; 6352 u8 match_dw_7[0x20]; 6353 u8 match_dw_6[0x20]; 6354 u8 match_dw_5[0x20]; 6355 u8 match_dw_4[0x20]; 6356 u8 match_dw_3[0x20]; 6357 u8 match_dw_2[0x20]; 6358 u8 match_dw_1[0x20]; 6359 u8 match_dw_0[0x20]; 6360 6361 u8 match_byte_7[0x8]; 6362 u8 match_byte_6[0x8]; 6363 u8 match_byte_5[0x8]; 6364 u8 match_byte_4[0x8]; 6365 6366 u8 match_byte_3[0x8]; 6367 u8 match_byte_2[0x8]; 6368 u8 match_byte_1[0x8]; 6369 u8 match_byte_0[0x8]; 6370 }; 6371 6372 struct mlx5_ifc_match_definer_bits { 6373 u8 modify_field_select[0x40]; 6374 6375 u8 reserved_at_40[0x40]; 6376 6377 u8 reserved_at_80[0x10]; 6378 u8 format_id[0x10]; 6379 6380 u8 reserved_at_a0[0x60]; 6381 6382 u8 format_select_dw3[0x8]; 6383 u8 format_select_dw2[0x8]; 6384 u8 format_select_dw1[0x8]; 6385 u8 format_select_dw0[0x8]; 6386 6387 u8 format_select_dw7[0x8]; 6388 u8 format_select_dw6[0x8]; 6389 u8 format_select_dw5[0x8]; 6390 u8 format_select_dw4[0x8]; 6391 6392 u8 reserved_at_100[0x18]; 6393 u8 format_select_dw8[0x8]; 6394 6395 u8 reserved_at_120[0x20]; 6396 6397 u8 format_select_byte3[0x8]; 6398 u8 format_select_byte2[0x8]; 6399 u8 format_select_byte1[0x8]; 6400 u8 format_select_byte0[0x8]; 6401 6402 u8 format_select_byte7[0x8]; 6403 u8 format_select_byte6[0x8]; 6404 u8 format_select_byte5[0x8]; 6405 u8 format_select_byte4[0x8]; 6406 6407 u8 reserved_at_180[0x40]; 6408 6409 union { 6410 struct { 6411 u8 match_mask[16][0x20]; 6412 }; 6413 struct mlx5_ifc_match_definer_match_mask_bits match_mask_format; 6414 }; 6415 }; 6416 6417 struct mlx5_ifc_general_obj_create_param_bits { 6418 u8 alias_object[0x1]; 6419 u8 reserved_at_1[0x2]; 6420 u8 log_obj_range[0x5]; 6421 u8 reserved_at_8[0x18]; 6422 }; 6423 6424 struct mlx5_ifc_general_obj_query_param_bits { 6425 u8 alias_object[0x1]; 6426 u8 obj_offset[0x1f]; 6427 }; 6428 6429 struct mlx5_ifc_general_obj_in_cmd_hdr_bits { 6430 u8 opcode[0x10]; 6431 u8 uid[0x10]; 6432 6433 u8 vhca_tunnel_id[0x10]; 6434 u8 obj_type[0x10]; 6435 6436 u8 obj_id[0x20]; 6437 6438 union { 6439 struct mlx5_ifc_general_obj_create_param_bits create; 6440 struct mlx5_ifc_general_obj_query_param_bits query; 6441 } op_param; 6442 }; 6443 6444 struct mlx5_ifc_general_obj_out_cmd_hdr_bits { 6445 u8 status[0x8]; 6446 u8 reserved_at_8[0x18]; 6447 6448 u8 syndrome[0x20]; 6449 6450 u8 obj_id[0x20]; 6451 6452 u8 reserved_at_60[0x20]; 6453 }; 6454 6455 struct mlx5_ifc_allow_other_vhca_access_in_bits { 6456 u8 opcode[0x10]; 6457 u8 uid[0x10]; 6458 u8 reserved_at_20[0x10]; 6459 u8 op_mod[0x10]; 6460 u8 reserved_at_40[0x50]; 6461 u8 object_type_to_be_accessed[0x10]; 6462 u8 object_id_to_be_accessed[0x20]; 6463 u8 reserved_at_c0[0x40]; 6464 union { 6465 u8 access_key_raw[0x100]; 6466 u8 access_key[8][0x20]; 6467 }; 6468 }; 6469 6470 struct mlx5_ifc_allow_other_vhca_access_out_bits { 6471 u8 status[0x8]; 6472 u8 reserved_at_8[0x18]; 6473 u8 syndrome[0x20]; 6474 u8 reserved_at_40[0x40]; 6475 }; 6476 6477 struct mlx5_ifc_modify_header_arg_bits { 6478 u8 reserved_at_0[0x80]; 6479 6480 u8 reserved_at_80[0x8]; 6481 u8 access_pd[0x18]; 6482 }; 6483 6484 struct mlx5_ifc_create_modify_header_arg_in_bits { 6485 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 6486 struct mlx5_ifc_modify_header_arg_bits arg; 6487 }; 6488 6489 struct mlx5_ifc_create_match_definer_in_bits { 6490 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 6491 6492 struct mlx5_ifc_match_definer_bits obj_context; 6493 }; 6494 6495 struct mlx5_ifc_create_match_definer_out_bits { 6496 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 6497 }; 6498 6499 struct mlx5_ifc_alias_context_bits { 6500 u8 vhca_id_to_be_accessed[0x10]; 6501 u8 reserved_at_10[0xd]; 6502 u8 status[0x3]; 6503 u8 object_id_to_be_accessed[0x20]; 6504 u8 reserved_at_40[0x40]; 6505 union { 6506 u8 access_key_raw[0x100]; 6507 u8 access_key[8][0x20]; 6508 }; 6509 u8 metadata[0x80]; 6510 }; 6511 6512 struct mlx5_ifc_create_alias_obj_in_bits { 6513 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 6514 struct mlx5_ifc_alias_context_bits alias_ctx; 6515 }; 6516 6517 enum { 6518 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 6519 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 6520 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 6521 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3, 6522 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_3 = 0x4, 6523 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_4 = 0x5, 6524 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_5 = 0x6, 6525 }; 6526 6527 struct mlx5_ifc_query_flow_group_out_bits { 6528 u8 status[0x8]; 6529 u8 reserved_at_8[0x18]; 6530 6531 u8 syndrome[0x20]; 6532 6533 u8 reserved_at_40[0xa0]; 6534 6535 u8 start_flow_index[0x20]; 6536 6537 u8 reserved_at_100[0x20]; 6538 6539 u8 end_flow_index[0x20]; 6540 6541 u8 reserved_at_140[0xa0]; 6542 6543 u8 reserved_at_1e0[0x18]; 6544 u8 match_criteria_enable[0x8]; 6545 6546 struct mlx5_ifc_fte_match_param_bits match_criteria; 6547 6548 u8 reserved_at_1200[0xe00]; 6549 }; 6550 6551 struct mlx5_ifc_query_flow_group_in_bits { 6552 u8 opcode[0x10]; 6553 u8 reserved_at_10[0x10]; 6554 6555 u8 reserved_at_20[0x10]; 6556 u8 op_mod[0x10]; 6557 6558 u8 reserved_at_40[0x40]; 6559 6560 u8 table_type[0x8]; 6561 u8 reserved_at_88[0x18]; 6562 6563 u8 reserved_at_a0[0x8]; 6564 u8 table_id[0x18]; 6565 6566 u8 group_id[0x20]; 6567 6568 u8 reserved_at_e0[0x120]; 6569 }; 6570 6571 struct mlx5_ifc_query_flow_counter_out_bits { 6572 u8 status[0x8]; 6573 u8 reserved_at_8[0x18]; 6574 6575 u8 syndrome[0x20]; 6576 6577 u8 reserved_at_40[0x40]; 6578 6579 struct mlx5_ifc_traffic_counter_bits flow_statistics[]; 6580 }; 6581 6582 struct mlx5_ifc_query_flow_counter_in_bits { 6583 u8 opcode[0x10]; 6584 u8 reserved_at_10[0x10]; 6585 6586 u8 reserved_at_20[0x10]; 6587 u8 op_mod[0x10]; 6588 6589 u8 reserved_at_40[0x80]; 6590 6591 u8 clear[0x1]; 6592 u8 reserved_at_c1[0xf]; 6593 u8 num_of_counters[0x10]; 6594 6595 u8 flow_counter_id[0x20]; 6596 }; 6597 6598 struct mlx5_ifc_query_esw_vport_context_out_bits { 6599 u8 status[0x8]; 6600 u8 reserved_at_8[0x18]; 6601 6602 u8 syndrome[0x20]; 6603 6604 u8 reserved_at_40[0x40]; 6605 6606 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 6607 }; 6608 6609 struct mlx5_ifc_query_esw_vport_context_in_bits { 6610 u8 opcode[0x10]; 6611 u8 reserved_at_10[0x10]; 6612 6613 u8 reserved_at_20[0x10]; 6614 u8 op_mod[0x10]; 6615 6616 u8 other_vport[0x1]; 6617 u8 reserved_at_41[0xf]; 6618 u8 vport_number[0x10]; 6619 6620 u8 reserved_at_60[0x20]; 6621 }; 6622 6623 struct mlx5_ifc_modify_esw_vport_context_out_bits { 6624 u8 status[0x8]; 6625 u8 reserved_at_8[0x18]; 6626 6627 u8 syndrome[0x20]; 6628 6629 u8 reserved_at_40[0x40]; 6630 }; 6631 6632 struct mlx5_ifc_esw_vport_context_fields_select_bits { 6633 u8 reserved_at_0[0x1b]; 6634 u8 fdb_to_vport_reg_c_id[0x1]; 6635 u8 vport_cvlan_insert[0x1]; 6636 u8 vport_svlan_insert[0x1]; 6637 u8 vport_cvlan_strip[0x1]; 6638 u8 vport_svlan_strip[0x1]; 6639 }; 6640 6641 struct mlx5_ifc_modify_esw_vport_context_in_bits { 6642 u8 opcode[0x10]; 6643 u8 reserved_at_10[0x10]; 6644 6645 u8 reserved_at_20[0x10]; 6646 u8 op_mod[0x10]; 6647 6648 u8 other_vport[0x1]; 6649 u8 reserved_at_41[0xf]; 6650 u8 vport_number[0x10]; 6651 6652 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select; 6653 6654 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 6655 }; 6656 6657 struct mlx5_ifc_query_eq_out_bits { 6658 u8 status[0x8]; 6659 u8 reserved_at_8[0x18]; 6660 6661 u8 syndrome[0x20]; 6662 6663 u8 reserved_at_40[0x40]; 6664 6665 struct mlx5_ifc_eqc_bits eq_context_entry; 6666 6667 u8 reserved_at_280[0x40]; 6668 6669 u8 event_bitmask[0x40]; 6670 6671 u8 reserved_at_300[0x580]; 6672 6673 u8 pas[][0x40]; 6674 }; 6675 6676 struct mlx5_ifc_query_eq_in_bits { 6677 u8 opcode[0x10]; 6678 u8 reserved_at_10[0x10]; 6679 6680 u8 reserved_at_20[0x10]; 6681 u8 op_mod[0x10]; 6682 6683 u8 reserved_at_40[0x18]; 6684 u8 eq_number[0x8]; 6685 6686 u8 reserved_at_60[0x20]; 6687 }; 6688 6689 struct mlx5_ifc_packet_reformat_context_in_bits { 6690 u8 reformat_type[0x8]; 6691 u8 reserved_at_8[0x4]; 6692 u8 reformat_param_0[0x4]; 6693 u8 reserved_at_10[0x6]; 6694 u8 reformat_data_size[0xa]; 6695 6696 u8 reformat_param_1[0x8]; 6697 u8 reserved_at_28[0x8]; 6698 u8 reformat_data[2][0x8]; 6699 6700 u8 more_reformat_data[][0x8]; 6701 }; 6702 6703 struct mlx5_ifc_query_packet_reformat_context_out_bits { 6704 u8 status[0x8]; 6705 u8 reserved_at_8[0x18]; 6706 6707 u8 syndrome[0x20]; 6708 6709 u8 reserved_at_40[0xa0]; 6710 6711 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context[]; 6712 }; 6713 6714 struct mlx5_ifc_query_packet_reformat_context_in_bits { 6715 u8 opcode[0x10]; 6716 u8 reserved_at_10[0x10]; 6717 6718 u8 reserved_at_20[0x10]; 6719 u8 op_mod[0x10]; 6720 6721 u8 packet_reformat_id[0x20]; 6722 6723 u8 reserved_at_60[0xa0]; 6724 }; 6725 6726 struct mlx5_ifc_alloc_packet_reformat_context_out_bits { 6727 u8 status[0x8]; 6728 u8 reserved_at_8[0x18]; 6729 6730 u8 syndrome[0x20]; 6731 6732 u8 packet_reformat_id[0x20]; 6733 6734 u8 reserved_at_60[0x20]; 6735 }; 6736 6737 enum { 6738 MLX5_REFORMAT_CONTEXT_ANCHOR_MAC_START = 0x1, 6739 MLX5_REFORMAT_CONTEXT_ANCHOR_IP_START = 0x7, 6740 MLX5_REFORMAT_CONTEXT_ANCHOR_TCP_UDP_START = 0x9, 6741 }; 6742 6743 enum mlx5_reformat_ctx_type { 6744 MLX5_REFORMAT_TYPE_L2_TO_VXLAN = 0x0, 6745 MLX5_REFORMAT_TYPE_L2_TO_NVGRE = 0x1, 6746 MLX5_REFORMAT_TYPE_L2_TO_L2_TUNNEL = 0x2, 6747 MLX5_REFORMAT_TYPE_L3_TUNNEL_TO_L2 = 0x3, 6748 MLX5_REFORMAT_TYPE_L2_TO_L3_TUNNEL = 0x4, 6749 MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_IPV4 = 0x5, 6750 MLX5_REFORMAT_TYPE_L2_TO_L3_ESP_TUNNEL = 0x6, 6751 MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_UDPV4 = 0x7, 6752 MLX5_REFORMAT_TYPE_DEL_ESP_TRANSPORT = 0x8, 6753 MLX5_REFORMAT_TYPE_L3_ESP_TUNNEL_TO_L2 = 0x9, 6754 MLX5_REFORMAT_TYPE_DEL_ESP_TRANSPORT_OVER_UDP = 0xa, 6755 MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_IPV6 = 0xb, 6756 MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_UDPV6 = 0xc, 6757 MLX5_REFORMAT_TYPE_INSERT_HDR = 0xf, 6758 MLX5_REFORMAT_TYPE_REMOVE_HDR = 0x10, 6759 MLX5_REFORMAT_TYPE_ADD_MACSEC = 0x11, 6760 MLX5_REFORMAT_TYPE_DEL_MACSEC = 0x12, 6761 }; 6762 6763 struct mlx5_ifc_alloc_packet_reformat_context_in_bits { 6764 u8 opcode[0x10]; 6765 u8 reserved_at_10[0x10]; 6766 6767 u8 reserved_at_20[0x10]; 6768 u8 op_mod[0x10]; 6769 6770 u8 reserved_at_40[0xa0]; 6771 6772 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context; 6773 }; 6774 6775 struct mlx5_ifc_dealloc_packet_reformat_context_out_bits { 6776 u8 status[0x8]; 6777 u8 reserved_at_8[0x18]; 6778 6779 u8 syndrome[0x20]; 6780 6781 u8 reserved_at_40[0x40]; 6782 }; 6783 6784 struct mlx5_ifc_dealloc_packet_reformat_context_in_bits { 6785 u8 opcode[0x10]; 6786 u8 reserved_at_10[0x10]; 6787 6788 u8 reserved_20[0x10]; 6789 u8 op_mod[0x10]; 6790 6791 u8 packet_reformat_id[0x20]; 6792 6793 u8 reserved_60[0x20]; 6794 }; 6795 6796 struct mlx5_ifc_set_action_in_bits { 6797 u8 action_type[0x4]; 6798 u8 field[0xc]; 6799 u8 reserved_at_10[0x3]; 6800 u8 offset[0x5]; 6801 u8 reserved_at_18[0x3]; 6802 u8 length[0x5]; 6803 6804 u8 data[0x20]; 6805 }; 6806 6807 struct mlx5_ifc_add_action_in_bits { 6808 u8 action_type[0x4]; 6809 u8 field[0xc]; 6810 u8 reserved_at_10[0x10]; 6811 6812 u8 data[0x20]; 6813 }; 6814 6815 struct mlx5_ifc_copy_action_in_bits { 6816 u8 action_type[0x4]; 6817 u8 src_field[0xc]; 6818 u8 reserved_at_10[0x3]; 6819 u8 src_offset[0x5]; 6820 u8 reserved_at_18[0x3]; 6821 u8 length[0x5]; 6822 6823 u8 reserved_at_20[0x4]; 6824 u8 dst_field[0xc]; 6825 u8 reserved_at_30[0x3]; 6826 u8 dst_offset[0x5]; 6827 u8 reserved_at_38[0x8]; 6828 }; 6829 6830 union mlx5_ifc_set_add_copy_action_in_auto_bits { 6831 struct mlx5_ifc_set_action_in_bits set_action_in; 6832 struct mlx5_ifc_add_action_in_bits add_action_in; 6833 struct mlx5_ifc_copy_action_in_bits copy_action_in; 6834 u8 reserved_at_0[0x40]; 6835 }; 6836 6837 enum { 6838 MLX5_ACTION_TYPE_SET = 0x1, 6839 MLX5_ACTION_TYPE_ADD = 0x2, 6840 MLX5_ACTION_TYPE_COPY = 0x3, 6841 }; 6842 6843 enum { 6844 MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16 = 0x1, 6845 MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0 = 0x2, 6846 MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE = 0x3, 6847 MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16 = 0x4, 6848 MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0 = 0x5, 6849 MLX5_ACTION_IN_FIELD_OUT_IP_DSCP = 0x6, 6850 MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS = 0x7, 6851 MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT = 0x8, 6852 MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT = 0x9, 6853 MLX5_ACTION_IN_FIELD_OUT_IP_TTL = 0xa, 6854 MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT = 0xb, 6855 MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT = 0xc, 6856 MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96 = 0xd, 6857 MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64 = 0xe, 6858 MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32 = 0xf, 6859 MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0 = 0x10, 6860 MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96 = 0x11, 6861 MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64 = 0x12, 6862 MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32 = 0x13, 6863 MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0 = 0x14, 6864 MLX5_ACTION_IN_FIELD_OUT_SIPV4 = 0x15, 6865 MLX5_ACTION_IN_FIELD_OUT_DIPV4 = 0x16, 6866 MLX5_ACTION_IN_FIELD_OUT_FIRST_VID = 0x17, 6867 MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47, 6868 MLX5_ACTION_IN_FIELD_METADATA_REG_A = 0x49, 6869 MLX5_ACTION_IN_FIELD_METADATA_REG_B = 0x50, 6870 MLX5_ACTION_IN_FIELD_METADATA_REG_C_0 = 0x51, 6871 MLX5_ACTION_IN_FIELD_METADATA_REG_C_1 = 0x52, 6872 MLX5_ACTION_IN_FIELD_METADATA_REG_C_2 = 0x53, 6873 MLX5_ACTION_IN_FIELD_METADATA_REG_C_3 = 0x54, 6874 MLX5_ACTION_IN_FIELD_METADATA_REG_C_4 = 0x55, 6875 MLX5_ACTION_IN_FIELD_METADATA_REG_C_5 = 0x56, 6876 MLX5_ACTION_IN_FIELD_METADATA_REG_C_6 = 0x57, 6877 MLX5_ACTION_IN_FIELD_METADATA_REG_C_7 = 0x58, 6878 MLX5_ACTION_IN_FIELD_OUT_TCP_SEQ_NUM = 0x59, 6879 MLX5_ACTION_IN_FIELD_OUT_TCP_ACK_NUM = 0x5B, 6880 MLX5_ACTION_IN_FIELD_IPSEC_SYNDROME = 0x5D, 6881 MLX5_ACTION_IN_FIELD_OUT_EMD_47_32 = 0x6F, 6882 MLX5_ACTION_IN_FIELD_OUT_EMD_31_0 = 0x70, 6883 }; 6884 6885 struct mlx5_ifc_alloc_modify_header_context_out_bits { 6886 u8 status[0x8]; 6887 u8 reserved_at_8[0x18]; 6888 6889 u8 syndrome[0x20]; 6890 6891 u8 modify_header_id[0x20]; 6892 6893 u8 reserved_at_60[0x20]; 6894 }; 6895 6896 struct mlx5_ifc_alloc_modify_header_context_in_bits { 6897 u8 opcode[0x10]; 6898 u8 reserved_at_10[0x10]; 6899 6900 u8 reserved_at_20[0x10]; 6901 u8 op_mod[0x10]; 6902 6903 u8 reserved_at_40[0x20]; 6904 6905 u8 table_type[0x8]; 6906 u8 reserved_at_68[0x10]; 6907 u8 num_of_actions[0x8]; 6908 6909 union mlx5_ifc_set_add_copy_action_in_auto_bits actions[]; 6910 }; 6911 6912 struct mlx5_ifc_dealloc_modify_header_context_out_bits { 6913 u8 status[0x8]; 6914 u8 reserved_at_8[0x18]; 6915 6916 u8 syndrome[0x20]; 6917 6918 u8 reserved_at_40[0x40]; 6919 }; 6920 6921 struct mlx5_ifc_dealloc_modify_header_context_in_bits { 6922 u8 opcode[0x10]; 6923 u8 reserved_at_10[0x10]; 6924 6925 u8 reserved_at_20[0x10]; 6926 u8 op_mod[0x10]; 6927 6928 u8 modify_header_id[0x20]; 6929 6930 u8 reserved_at_60[0x20]; 6931 }; 6932 6933 struct mlx5_ifc_query_modify_header_context_in_bits { 6934 u8 opcode[0x10]; 6935 u8 uid[0x10]; 6936 6937 u8 reserved_at_20[0x10]; 6938 u8 op_mod[0x10]; 6939 6940 u8 modify_header_id[0x20]; 6941 6942 u8 reserved_at_60[0xa0]; 6943 }; 6944 6945 struct mlx5_ifc_query_dct_out_bits { 6946 u8 status[0x8]; 6947 u8 reserved_at_8[0x18]; 6948 6949 u8 syndrome[0x20]; 6950 6951 u8 reserved_at_40[0x40]; 6952 6953 struct mlx5_ifc_dctc_bits dct_context_entry; 6954 6955 u8 reserved_at_280[0x180]; 6956 }; 6957 6958 struct mlx5_ifc_query_dct_in_bits { 6959 u8 opcode[0x10]; 6960 u8 reserved_at_10[0x10]; 6961 6962 u8 reserved_at_20[0x10]; 6963 u8 op_mod[0x10]; 6964 6965 u8 reserved_at_40[0x8]; 6966 u8 dctn[0x18]; 6967 6968 u8 reserved_at_60[0x20]; 6969 }; 6970 6971 struct mlx5_ifc_query_cq_out_bits { 6972 u8 status[0x8]; 6973 u8 reserved_at_8[0x18]; 6974 6975 u8 syndrome[0x20]; 6976 6977 u8 reserved_at_40[0x40]; 6978 6979 struct mlx5_ifc_cqc_bits cq_context; 6980 6981 u8 reserved_at_280[0x600]; 6982 6983 u8 pas[][0x40]; 6984 }; 6985 6986 struct mlx5_ifc_query_cq_in_bits { 6987 u8 opcode[0x10]; 6988 u8 reserved_at_10[0x10]; 6989 6990 u8 reserved_at_20[0x10]; 6991 u8 op_mod[0x10]; 6992 6993 u8 reserved_at_40[0x8]; 6994 u8 cqn[0x18]; 6995 6996 u8 reserved_at_60[0x20]; 6997 }; 6998 6999 struct mlx5_ifc_query_cong_status_out_bits { 7000 u8 status[0x8]; 7001 u8 reserved_at_8[0x18]; 7002 7003 u8 syndrome[0x20]; 7004 7005 u8 reserved_at_40[0x20]; 7006 7007 u8 enable[0x1]; 7008 u8 tag_enable[0x1]; 7009 u8 reserved_at_62[0x1e]; 7010 }; 7011 7012 struct mlx5_ifc_query_cong_status_in_bits { 7013 u8 opcode[0x10]; 7014 u8 reserved_at_10[0x10]; 7015 7016 u8 reserved_at_20[0x10]; 7017 u8 op_mod[0x10]; 7018 7019 u8 reserved_at_40[0x18]; 7020 u8 priority[0x4]; 7021 u8 cong_protocol[0x4]; 7022 7023 u8 reserved_at_60[0x20]; 7024 }; 7025 7026 struct mlx5_ifc_query_cong_statistics_out_bits { 7027 u8 status[0x8]; 7028 u8 reserved_at_8[0x18]; 7029 7030 u8 syndrome[0x20]; 7031 7032 u8 reserved_at_40[0x40]; 7033 7034 u8 rp_cur_flows[0x20]; 7035 7036 u8 sum_flows[0x20]; 7037 7038 u8 rp_cnp_ignored_high[0x20]; 7039 7040 u8 rp_cnp_ignored_low[0x20]; 7041 7042 u8 rp_cnp_handled_high[0x20]; 7043 7044 u8 rp_cnp_handled_low[0x20]; 7045 7046 u8 reserved_at_140[0x100]; 7047 7048 u8 time_stamp_high[0x20]; 7049 7050 u8 time_stamp_low[0x20]; 7051 7052 u8 accumulators_period[0x20]; 7053 7054 u8 np_ecn_marked_roce_packets_high[0x20]; 7055 7056 u8 np_ecn_marked_roce_packets_low[0x20]; 7057 7058 u8 np_cnp_sent_high[0x20]; 7059 7060 u8 np_cnp_sent_low[0x20]; 7061 7062 u8 reserved_at_320[0x560]; 7063 }; 7064 7065 struct mlx5_ifc_query_cong_statistics_in_bits { 7066 u8 opcode[0x10]; 7067 u8 reserved_at_10[0x10]; 7068 7069 u8 reserved_at_20[0x10]; 7070 u8 op_mod[0x10]; 7071 7072 u8 clear[0x1]; 7073 u8 reserved_at_41[0x1f]; 7074 7075 u8 reserved_at_60[0x20]; 7076 }; 7077 7078 struct mlx5_ifc_query_cong_params_out_bits { 7079 u8 status[0x8]; 7080 u8 reserved_at_8[0x18]; 7081 7082 u8 syndrome[0x20]; 7083 7084 u8 reserved_at_40[0x40]; 7085 7086 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 7087 }; 7088 7089 struct mlx5_ifc_query_cong_params_in_bits { 7090 u8 opcode[0x10]; 7091 u8 reserved_at_10[0x10]; 7092 7093 u8 reserved_at_20[0x10]; 7094 u8 op_mod[0x10]; 7095 7096 u8 reserved_at_40[0x1c]; 7097 u8 cong_protocol[0x4]; 7098 7099 u8 reserved_at_60[0x20]; 7100 }; 7101 7102 struct mlx5_ifc_query_adapter_out_bits { 7103 u8 status[0x8]; 7104 u8 reserved_at_8[0x18]; 7105 7106 u8 syndrome[0x20]; 7107 7108 u8 reserved_at_40[0x40]; 7109 7110 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct; 7111 }; 7112 7113 struct mlx5_ifc_query_adapter_in_bits { 7114 u8 opcode[0x10]; 7115 u8 reserved_at_10[0x10]; 7116 7117 u8 reserved_at_20[0x10]; 7118 u8 op_mod[0x10]; 7119 7120 u8 reserved_at_40[0x40]; 7121 }; 7122 7123 struct mlx5_ifc_qp_2rst_out_bits { 7124 u8 status[0x8]; 7125 u8 reserved_at_8[0x18]; 7126 7127 u8 syndrome[0x20]; 7128 7129 u8 reserved_at_40[0x40]; 7130 }; 7131 7132 struct mlx5_ifc_qp_2rst_in_bits { 7133 u8 opcode[0x10]; 7134 u8 uid[0x10]; 7135 7136 u8 reserved_at_20[0x10]; 7137 u8 op_mod[0x10]; 7138 7139 u8 reserved_at_40[0x8]; 7140 u8 qpn[0x18]; 7141 7142 u8 reserved_at_60[0x20]; 7143 }; 7144 7145 struct mlx5_ifc_qp_2err_out_bits { 7146 u8 status[0x8]; 7147 u8 reserved_at_8[0x18]; 7148 7149 u8 syndrome[0x20]; 7150 7151 u8 reserved_at_40[0x40]; 7152 }; 7153 7154 struct mlx5_ifc_qp_2err_in_bits { 7155 u8 opcode[0x10]; 7156 u8 uid[0x10]; 7157 7158 u8 reserved_at_20[0x10]; 7159 u8 op_mod[0x10]; 7160 7161 u8 reserved_at_40[0x8]; 7162 u8 qpn[0x18]; 7163 7164 u8 reserved_at_60[0x20]; 7165 }; 7166 7167 struct mlx5_ifc_page_fault_resume_out_bits { 7168 u8 status[0x8]; 7169 u8 reserved_at_8[0x18]; 7170 7171 u8 syndrome[0x20]; 7172 7173 u8 reserved_at_40[0x40]; 7174 }; 7175 7176 struct mlx5_ifc_page_fault_resume_in_bits { 7177 u8 opcode[0x10]; 7178 u8 reserved_at_10[0x10]; 7179 7180 u8 reserved_at_20[0x10]; 7181 u8 op_mod[0x10]; 7182 7183 u8 error[0x1]; 7184 u8 reserved_at_41[0x4]; 7185 u8 page_fault_type[0x3]; 7186 u8 wq_number[0x18]; 7187 7188 u8 reserved_at_60[0x8]; 7189 u8 token[0x18]; 7190 }; 7191 7192 struct mlx5_ifc_nop_out_bits { 7193 u8 status[0x8]; 7194 u8 reserved_at_8[0x18]; 7195 7196 u8 syndrome[0x20]; 7197 7198 u8 reserved_at_40[0x40]; 7199 }; 7200 7201 struct mlx5_ifc_nop_in_bits { 7202 u8 opcode[0x10]; 7203 u8 reserved_at_10[0x10]; 7204 7205 u8 reserved_at_20[0x10]; 7206 u8 op_mod[0x10]; 7207 7208 u8 reserved_at_40[0x40]; 7209 }; 7210 7211 struct mlx5_ifc_modify_vport_state_out_bits { 7212 u8 status[0x8]; 7213 u8 reserved_at_8[0x18]; 7214 7215 u8 syndrome[0x20]; 7216 7217 u8 reserved_at_40[0x40]; 7218 }; 7219 7220 struct mlx5_ifc_modify_vport_state_in_bits { 7221 u8 opcode[0x10]; 7222 u8 reserved_at_10[0x10]; 7223 7224 u8 reserved_at_20[0x10]; 7225 u8 op_mod[0x10]; 7226 7227 u8 other_vport[0x1]; 7228 u8 reserved_at_41[0xf]; 7229 u8 vport_number[0x10]; 7230 7231 u8 reserved_at_60[0x18]; 7232 u8 admin_state[0x4]; 7233 u8 reserved_at_7c[0x4]; 7234 }; 7235 7236 struct mlx5_ifc_modify_tis_out_bits { 7237 u8 status[0x8]; 7238 u8 reserved_at_8[0x18]; 7239 7240 u8 syndrome[0x20]; 7241 7242 u8 reserved_at_40[0x40]; 7243 }; 7244 7245 struct mlx5_ifc_modify_tis_bitmask_bits { 7246 u8 reserved_at_0[0x20]; 7247 7248 u8 reserved_at_20[0x1d]; 7249 u8 lag_tx_port_affinity[0x1]; 7250 u8 strict_lag_tx_port_affinity[0x1]; 7251 u8 prio[0x1]; 7252 }; 7253 7254 struct mlx5_ifc_modify_tis_in_bits { 7255 u8 opcode[0x10]; 7256 u8 uid[0x10]; 7257 7258 u8 reserved_at_20[0x10]; 7259 u8 op_mod[0x10]; 7260 7261 u8 reserved_at_40[0x8]; 7262 u8 tisn[0x18]; 7263 7264 u8 reserved_at_60[0x20]; 7265 7266 struct mlx5_ifc_modify_tis_bitmask_bits bitmask; 7267 7268 u8 reserved_at_c0[0x40]; 7269 7270 struct mlx5_ifc_tisc_bits ctx; 7271 }; 7272 7273 struct mlx5_ifc_modify_tir_bitmask_bits { 7274 u8 reserved_at_0[0x20]; 7275 7276 u8 reserved_at_20[0x1b]; 7277 u8 self_lb_en[0x1]; 7278 u8 reserved_at_3c[0x1]; 7279 u8 hash[0x1]; 7280 u8 reserved_at_3e[0x1]; 7281 u8 packet_merge[0x1]; 7282 }; 7283 7284 struct mlx5_ifc_modify_tir_out_bits { 7285 u8 status[0x8]; 7286 u8 reserved_at_8[0x18]; 7287 7288 u8 syndrome[0x20]; 7289 7290 u8 reserved_at_40[0x40]; 7291 }; 7292 7293 struct mlx5_ifc_modify_tir_in_bits { 7294 u8 opcode[0x10]; 7295 u8 uid[0x10]; 7296 7297 u8 reserved_at_20[0x10]; 7298 u8 op_mod[0x10]; 7299 7300 u8 reserved_at_40[0x8]; 7301 u8 tirn[0x18]; 7302 7303 u8 reserved_at_60[0x20]; 7304 7305 struct mlx5_ifc_modify_tir_bitmask_bits bitmask; 7306 7307 u8 reserved_at_c0[0x40]; 7308 7309 struct mlx5_ifc_tirc_bits ctx; 7310 }; 7311 7312 struct mlx5_ifc_modify_sq_out_bits { 7313 u8 status[0x8]; 7314 u8 reserved_at_8[0x18]; 7315 7316 u8 syndrome[0x20]; 7317 7318 u8 reserved_at_40[0x40]; 7319 }; 7320 7321 struct mlx5_ifc_modify_sq_in_bits { 7322 u8 opcode[0x10]; 7323 u8 uid[0x10]; 7324 7325 u8 reserved_at_20[0x10]; 7326 u8 op_mod[0x10]; 7327 7328 u8 sq_state[0x4]; 7329 u8 reserved_at_44[0x4]; 7330 u8 sqn[0x18]; 7331 7332 u8 reserved_at_60[0x20]; 7333 7334 u8 modify_bitmask[0x40]; 7335 7336 u8 reserved_at_c0[0x40]; 7337 7338 struct mlx5_ifc_sqc_bits ctx; 7339 }; 7340 7341 struct mlx5_ifc_modify_scheduling_element_out_bits { 7342 u8 status[0x8]; 7343 u8 reserved_at_8[0x18]; 7344 7345 u8 syndrome[0x20]; 7346 7347 u8 reserved_at_40[0x1c0]; 7348 }; 7349 7350 enum { 7351 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1, 7352 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2, 7353 }; 7354 7355 struct mlx5_ifc_modify_scheduling_element_in_bits { 7356 u8 opcode[0x10]; 7357 u8 reserved_at_10[0x10]; 7358 7359 u8 reserved_at_20[0x10]; 7360 u8 op_mod[0x10]; 7361 7362 u8 scheduling_hierarchy[0x8]; 7363 u8 reserved_at_48[0x18]; 7364 7365 u8 scheduling_element_id[0x20]; 7366 7367 u8 reserved_at_80[0x20]; 7368 7369 u8 modify_bitmask[0x20]; 7370 7371 u8 reserved_at_c0[0x40]; 7372 7373 struct mlx5_ifc_scheduling_context_bits scheduling_context; 7374 7375 u8 reserved_at_300[0x100]; 7376 }; 7377 7378 struct mlx5_ifc_modify_rqt_out_bits { 7379 u8 status[0x8]; 7380 u8 reserved_at_8[0x18]; 7381 7382 u8 syndrome[0x20]; 7383 7384 u8 reserved_at_40[0x40]; 7385 }; 7386 7387 struct mlx5_ifc_rqt_bitmask_bits { 7388 u8 reserved_at_0[0x20]; 7389 7390 u8 reserved_at_20[0x1f]; 7391 u8 rqn_list[0x1]; 7392 }; 7393 7394 struct mlx5_ifc_modify_rqt_in_bits { 7395 u8 opcode[0x10]; 7396 u8 uid[0x10]; 7397 7398 u8 reserved_at_20[0x10]; 7399 u8 op_mod[0x10]; 7400 7401 u8 reserved_at_40[0x8]; 7402 u8 rqtn[0x18]; 7403 7404 u8 reserved_at_60[0x20]; 7405 7406 struct mlx5_ifc_rqt_bitmask_bits bitmask; 7407 7408 u8 reserved_at_c0[0x40]; 7409 7410 struct mlx5_ifc_rqtc_bits ctx; 7411 }; 7412 7413 struct mlx5_ifc_modify_rq_out_bits { 7414 u8 status[0x8]; 7415 u8 reserved_at_8[0x18]; 7416 7417 u8 syndrome[0x20]; 7418 7419 u8 reserved_at_40[0x40]; 7420 }; 7421 7422 enum { 7423 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1, 7424 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2, 7425 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3, 7426 }; 7427 7428 struct mlx5_ifc_modify_rq_in_bits { 7429 u8 opcode[0x10]; 7430 u8 uid[0x10]; 7431 7432 u8 reserved_at_20[0x10]; 7433 u8 op_mod[0x10]; 7434 7435 u8 rq_state[0x4]; 7436 u8 reserved_at_44[0x4]; 7437 u8 rqn[0x18]; 7438 7439 u8 reserved_at_60[0x20]; 7440 7441 u8 modify_bitmask[0x40]; 7442 7443 u8 reserved_at_c0[0x40]; 7444 7445 struct mlx5_ifc_rqc_bits ctx; 7446 }; 7447 7448 struct mlx5_ifc_modify_rmp_out_bits { 7449 u8 status[0x8]; 7450 u8 reserved_at_8[0x18]; 7451 7452 u8 syndrome[0x20]; 7453 7454 u8 reserved_at_40[0x40]; 7455 }; 7456 7457 struct mlx5_ifc_rmp_bitmask_bits { 7458 u8 reserved_at_0[0x20]; 7459 7460 u8 reserved_at_20[0x1f]; 7461 u8 lwm[0x1]; 7462 }; 7463 7464 struct mlx5_ifc_modify_rmp_in_bits { 7465 u8 opcode[0x10]; 7466 u8 uid[0x10]; 7467 7468 u8 reserved_at_20[0x10]; 7469 u8 op_mod[0x10]; 7470 7471 u8 rmp_state[0x4]; 7472 u8 reserved_at_44[0x4]; 7473 u8 rmpn[0x18]; 7474 7475 u8 reserved_at_60[0x20]; 7476 7477 struct mlx5_ifc_rmp_bitmask_bits bitmask; 7478 7479 u8 reserved_at_c0[0x40]; 7480 7481 struct mlx5_ifc_rmpc_bits ctx; 7482 }; 7483 7484 struct mlx5_ifc_modify_nic_vport_context_out_bits { 7485 u8 status[0x8]; 7486 u8 reserved_at_8[0x18]; 7487 7488 u8 syndrome[0x20]; 7489 7490 u8 reserved_at_40[0x40]; 7491 }; 7492 7493 struct mlx5_ifc_modify_nic_vport_field_select_bits { 7494 u8 reserved_at_0[0x12]; 7495 u8 affiliation[0x1]; 7496 u8 reserved_at_13[0x1]; 7497 u8 disable_uc_local_lb[0x1]; 7498 u8 disable_mc_local_lb[0x1]; 7499 u8 node_guid[0x1]; 7500 u8 port_guid[0x1]; 7501 u8 min_inline[0x1]; 7502 u8 mtu[0x1]; 7503 u8 change_event[0x1]; 7504 u8 promisc[0x1]; 7505 u8 permanent_address[0x1]; 7506 u8 addresses_list[0x1]; 7507 u8 roce_en[0x1]; 7508 u8 reserved_at_1f[0x1]; 7509 }; 7510 7511 struct mlx5_ifc_modify_nic_vport_context_in_bits { 7512 u8 opcode[0x10]; 7513 u8 reserved_at_10[0x10]; 7514 7515 u8 reserved_at_20[0x10]; 7516 u8 op_mod[0x10]; 7517 7518 u8 other_vport[0x1]; 7519 u8 reserved_at_41[0xf]; 7520 u8 vport_number[0x10]; 7521 7522 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select; 7523 7524 u8 reserved_at_80[0x780]; 7525 7526 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 7527 }; 7528 7529 struct mlx5_ifc_modify_hca_vport_context_out_bits { 7530 u8 status[0x8]; 7531 u8 reserved_at_8[0x18]; 7532 7533 u8 syndrome[0x20]; 7534 7535 u8 reserved_at_40[0x40]; 7536 }; 7537 7538 struct mlx5_ifc_modify_hca_vport_context_in_bits { 7539 u8 opcode[0x10]; 7540 u8 reserved_at_10[0x10]; 7541 7542 u8 reserved_at_20[0x10]; 7543 u8 op_mod[0x10]; 7544 7545 u8 other_vport[0x1]; 7546 u8 reserved_at_41[0xb]; 7547 u8 port_num[0x4]; 7548 u8 vport_number[0x10]; 7549 7550 u8 reserved_at_60[0x20]; 7551 7552 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 7553 }; 7554 7555 struct mlx5_ifc_modify_cq_out_bits { 7556 u8 status[0x8]; 7557 u8 reserved_at_8[0x18]; 7558 7559 u8 syndrome[0x20]; 7560 7561 u8 reserved_at_40[0x40]; 7562 }; 7563 7564 enum { 7565 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0, 7566 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1, 7567 }; 7568 7569 struct mlx5_ifc_modify_cq_in_bits { 7570 u8 opcode[0x10]; 7571 u8 uid[0x10]; 7572 7573 u8 reserved_at_20[0x10]; 7574 u8 op_mod[0x10]; 7575 7576 u8 reserved_at_40[0x8]; 7577 u8 cqn[0x18]; 7578 7579 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select; 7580 7581 struct mlx5_ifc_cqc_bits cq_context; 7582 7583 u8 reserved_at_280[0x60]; 7584 7585 u8 cq_umem_valid[0x1]; 7586 u8 reserved_at_2e1[0x1f]; 7587 7588 u8 reserved_at_300[0x580]; 7589 7590 u8 pas[][0x40]; 7591 }; 7592 7593 struct mlx5_ifc_modify_cong_status_out_bits { 7594 u8 status[0x8]; 7595 u8 reserved_at_8[0x18]; 7596 7597 u8 syndrome[0x20]; 7598 7599 u8 reserved_at_40[0x40]; 7600 }; 7601 7602 struct mlx5_ifc_modify_cong_status_in_bits { 7603 u8 opcode[0x10]; 7604 u8 reserved_at_10[0x10]; 7605 7606 u8 reserved_at_20[0x10]; 7607 u8 op_mod[0x10]; 7608 7609 u8 reserved_at_40[0x18]; 7610 u8 priority[0x4]; 7611 u8 cong_protocol[0x4]; 7612 7613 u8 enable[0x1]; 7614 u8 tag_enable[0x1]; 7615 u8 reserved_at_62[0x1e]; 7616 }; 7617 7618 struct mlx5_ifc_modify_cong_params_out_bits { 7619 u8 status[0x8]; 7620 u8 reserved_at_8[0x18]; 7621 7622 u8 syndrome[0x20]; 7623 7624 u8 reserved_at_40[0x40]; 7625 }; 7626 7627 struct mlx5_ifc_modify_cong_params_in_bits { 7628 u8 opcode[0x10]; 7629 u8 reserved_at_10[0x10]; 7630 7631 u8 reserved_at_20[0x10]; 7632 u8 op_mod[0x10]; 7633 7634 u8 reserved_at_40[0x1c]; 7635 u8 cong_protocol[0x4]; 7636 7637 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select; 7638 7639 u8 reserved_at_80[0x80]; 7640 7641 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 7642 }; 7643 7644 struct mlx5_ifc_manage_pages_out_bits { 7645 u8 status[0x8]; 7646 u8 reserved_at_8[0x18]; 7647 7648 u8 syndrome[0x20]; 7649 7650 u8 output_num_entries[0x20]; 7651 7652 u8 reserved_at_60[0x20]; 7653 7654 u8 pas[][0x40]; 7655 }; 7656 7657 enum { 7658 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL = 0x0, 7659 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS = 0x1, 7660 MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES = 0x2, 7661 }; 7662 7663 struct mlx5_ifc_manage_pages_in_bits { 7664 u8 opcode[0x10]; 7665 u8 reserved_at_10[0x10]; 7666 7667 u8 reserved_at_20[0x10]; 7668 u8 op_mod[0x10]; 7669 7670 u8 embedded_cpu_function[0x1]; 7671 u8 reserved_at_41[0xf]; 7672 u8 function_id[0x10]; 7673 7674 u8 input_num_entries[0x20]; 7675 7676 u8 pas[][0x40]; 7677 }; 7678 7679 struct mlx5_ifc_mad_ifc_out_bits { 7680 u8 status[0x8]; 7681 u8 reserved_at_8[0x18]; 7682 7683 u8 syndrome[0x20]; 7684 7685 u8 reserved_at_40[0x40]; 7686 7687 u8 response_mad_packet[256][0x8]; 7688 }; 7689 7690 struct mlx5_ifc_mad_ifc_in_bits { 7691 u8 opcode[0x10]; 7692 u8 reserved_at_10[0x10]; 7693 7694 u8 reserved_at_20[0x10]; 7695 u8 op_mod[0x10]; 7696 7697 u8 remote_lid[0x10]; 7698 u8 reserved_at_50[0x8]; 7699 u8 port[0x8]; 7700 7701 u8 reserved_at_60[0x20]; 7702 7703 u8 mad[256][0x8]; 7704 }; 7705 7706 struct mlx5_ifc_init_hca_out_bits { 7707 u8 status[0x8]; 7708 u8 reserved_at_8[0x18]; 7709 7710 u8 syndrome[0x20]; 7711 7712 u8 reserved_at_40[0x40]; 7713 }; 7714 7715 struct mlx5_ifc_init_hca_in_bits { 7716 u8 opcode[0x10]; 7717 u8 reserved_at_10[0x10]; 7718 7719 u8 reserved_at_20[0x10]; 7720 u8 op_mod[0x10]; 7721 7722 u8 reserved_at_40[0x20]; 7723 7724 u8 reserved_at_60[0x2]; 7725 u8 sw_vhca_id[0xe]; 7726 u8 reserved_at_70[0x10]; 7727 7728 u8 sw_owner_id[4][0x20]; 7729 }; 7730 7731 struct mlx5_ifc_init2rtr_qp_out_bits { 7732 u8 status[0x8]; 7733 u8 reserved_at_8[0x18]; 7734 7735 u8 syndrome[0x20]; 7736 7737 u8 reserved_at_40[0x20]; 7738 u8 ece[0x20]; 7739 }; 7740 7741 struct mlx5_ifc_init2rtr_qp_in_bits { 7742 u8 opcode[0x10]; 7743 u8 uid[0x10]; 7744 7745 u8 reserved_at_20[0x10]; 7746 u8 op_mod[0x10]; 7747 7748 u8 reserved_at_40[0x8]; 7749 u8 qpn[0x18]; 7750 7751 u8 reserved_at_60[0x20]; 7752 7753 u8 opt_param_mask[0x20]; 7754 7755 u8 ece[0x20]; 7756 7757 struct mlx5_ifc_qpc_bits qpc; 7758 7759 u8 reserved_at_800[0x80]; 7760 }; 7761 7762 struct mlx5_ifc_init2init_qp_out_bits { 7763 u8 status[0x8]; 7764 u8 reserved_at_8[0x18]; 7765 7766 u8 syndrome[0x20]; 7767 7768 u8 reserved_at_40[0x20]; 7769 u8 ece[0x20]; 7770 }; 7771 7772 struct mlx5_ifc_init2init_qp_in_bits { 7773 u8 opcode[0x10]; 7774 u8 uid[0x10]; 7775 7776 u8 reserved_at_20[0x10]; 7777 u8 op_mod[0x10]; 7778 7779 u8 reserved_at_40[0x8]; 7780 u8 qpn[0x18]; 7781 7782 u8 reserved_at_60[0x20]; 7783 7784 u8 opt_param_mask[0x20]; 7785 7786 u8 ece[0x20]; 7787 7788 struct mlx5_ifc_qpc_bits qpc; 7789 7790 u8 reserved_at_800[0x80]; 7791 }; 7792 7793 struct mlx5_ifc_get_dropped_packet_log_out_bits { 7794 u8 status[0x8]; 7795 u8 reserved_at_8[0x18]; 7796 7797 u8 syndrome[0x20]; 7798 7799 u8 reserved_at_40[0x40]; 7800 7801 u8 packet_headers_log[128][0x8]; 7802 7803 u8 packet_syndrome[64][0x8]; 7804 }; 7805 7806 struct mlx5_ifc_get_dropped_packet_log_in_bits { 7807 u8 opcode[0x10]; 7808 u8 reserved_at_10[0x10]; 7809 7810 u8 reserved_at_20[0x10]; 7811 u8 op_mod[0x10]; 7812 7813 u8 reserved_at_40[0x40]; 7814 }; 7815 7816 struct mlx5_ifc_gen_eqe_in_bits { 7817 u8 opcode[0x10]; 7818 u8 reserved_at_10[0x10]; 7819 7820 u8 reserved_at_20[0x10]; 7821 u8 op_mod[0x10]; 7822 7823 u8 reserved_at_40[0x18]; 7824 u8 eq_number[0x8]; 7825 7826 u8 reserved_at_60[0x20]; 7827 7828 u8 eqe[64][0x8]; 7829 }; 7830 7831 struct mlx5_ifc_gen_eq_out_bits { 7832 u8 status[0x8]; 7833 u8 reserved_at_8[0x18]; 7834 7835 u8 syndrome[0x20]; 7836 7837 u8 reserved_at_40[0x40]; 7838 }; 7839 7840 struct mlx5_ifc_enable_hca_out_bits { 7841 u8 status[0x8]; 7842 u8 reserved_at_8[0x18]; 7843 7844 u8 syndrome[0x20]; 7845 7846 u8 reserved_at_40[0x20]; 7847 }; 7848 7849 struct mlx5_ifc_enable_hca_in_bits { 7850 u8 opcode[0x10]; 7851 u8 reserved_at_10[0x10]; 7852 7853 u8 reserved_at_20[0x10]; 7854 u8 op_mod[0x10]; 7855 7856 u8 embedded_cpu_function[0x1]; 7857 u8 reserved_at_41[0xf]; 7858 u8 function_id[0x10]; 7859 7860 u8 reserved_at_60[0x20]; 7861 }; 7862 7863 struct mlx5_ifc_drain_dct_out_bits { 7864 u8 status[0x8]; 7865 u8 reserved_at_8[0x18]; 7866 7867 u8 syndrome[0x20]; 7868 7869 u8 reserved_at_40[0x40]; 7870 }; 7871 7872 struct mlx5_ifc_drain_dct_in_bits { 7873 u8 opcode[0x10]; 7874 u8 uid[0x10]; 7875 7876 u8 reserved_at_20[0x10]; 7877 u8 op_mod[0x10]; 7878 7879 u8 reserved_at_40[0x8]; 7880 u8 dctn[0x18]; 7881 7882 u8 reserved_at_60[0x20]; 7883 }; 7884 7885 struct mlx5_ifc_disable_hca_out_bits { 7886 u8 status[0x8]; 7887 u8 reserved_at_8[0x18]; 7888 7889 u8 syndrome[0x20]; 7890 7891 u8 reserved_at_40[0x20]; 7892 }; 7893 7894 struct mlx5_ifc_disable_hca_in_bits { 7895 u8 opcode[0x10]; 7896 u8 reserved_at_10[0x10]; 7897 7898 u8 reserved_at_20[0x10]; 7899 u8 op_mod[0x10]; 7900 7901 u8 embedded_cpu_function[0x1]; 7902 u8 reserved_at_41[0xf]; 7903 u8 function_id[0x10]; 7904 7905 u8 reserved_at_60[0x20]; 7906 }; 7907 7908 struct mlx5_ifc_detach_from_mcg_out_bits { 7909 u8 status[0x8]; 7910 u8 reserved_at_8[0x18]; 7911 7912 u8 syndrome[0x20]; 7913 7914 u8 reserved_at_40[0x40]; 7915 }; 7916 7917 struct mlx5_ifc_detach_from_mcg_in_bits { 7918 u8 opcode[0x10]; 7919 u8 uid[0x10]; 7920 7921 u8 reserved_at_20[0x10]; 7922 u8 op_mod[0x10]; 7923 7924 u8 reserved_at_40[0x8]; 7925 u8 qpn[0x18]; 7926 7927 u8 reserved_at_60[0x20]; 7928 7929 u8 multicast_gid[16][0x8]; 7930 }; 7931 7932 struct mlx5_ifc_destroy_xrq_out_bits { 7933 u8 status[0x8]; 7934 u8 reserved_at_8[0x18]; 7935 7936 u8 syndrome[0x20]; 7937 7938 u8 reserved_at_40[0x40]; 7939 }; 7940 7941 struct mlx5_ifc_destroy_xrq_in_bits { 7942 u8 opcode[0x10]; 7943 u8 uid[0x10]; 7944 7945 u8 reserved_at_20[0x10]; 7946 u8 op_mod[0x10]; 7947 7948 u8 reserved_at_40[0x8]; 7949 u8 xrqn[0x18]; 7950 7951 u8 reserved_at_60[0x20]; 7952 }; 7953 7954 struct mlx5_ifc_destroy_xrc_srq_out_bits { 7955 u8 status[0x8]; 7956 u8 reserved_at_8[0x18]; 7957 7958 u8 syndrome[0x20]; 7959 7960 u8 reserved_at_40[0x40]; 7961 }; 7962 7963 struct mlx5_ifc_destroy_xrc_srq_in_bits { 7964 u8 opcode[0x10]; 7965 u8 uid[0x10]; 7966 7967 u8 reserved_at_20[0x10]; 7968 u8 op_mod[0x10]; 7969 7970 u8 reserved_at_40[0x8]; 7971 u8 xrc_srqn[0x18]; 7972 7973 u8 reserved_at_60[0x20]; 7974 }; 7975 7976 struct mlx5_ifc_destroy_tis_out_bits { 7977 u8 status[0x8]; 7978 u8 reserved_at_8[0x18]; 7979 7980 u8 syndrome[0x20]; 7981 7982 u8 reserved_at_40[0x40]; 7983 }; 7984 7985 struct mlx5_ifc_destroy_tis_in_bits { 7986 u8 opcode[0x10]; 7987 u8 uid[0x10]; 7988 7989 u8 reserved_at_20[0x10]; 7990 u8 op_mod[0x10]; 7991 7992 u8 reserved_at_40[0x8]; 7993 u8 tisn[0x18]; 7994 7995 u8 reserved_at_60[0x20]; 7996 }; 7997 7998 struct mlx5_ifc_destroy_tir_out_bits { 7999 u8 status[0x8]; 8000 u8 reserved_at_8[0x18]; 8001 8002 u8 syndrome[0x20]; 8003 8004 u8 reserved_at_40[0x40]; 8005 }; 8006 8007 struct mlx5_ifc_destroy_tir_in_bits { 8008 u8 opcode[0x10]; 8009 u8 uid[0x10]; 8010 8011 u8 reserved_at_20[0x10]; 8012 u8 op_mod[0x10]; 8013 8014 u8 reserved_at_40[0x8]; 8015 u8 tirn[0x18]; 8016 8017 u8 reserved_at_60[0x20]; 8018 }; 8019 8020 struct mlx5_ifc_destroy_srq_out_bits { 8021 u8 status[0x8]; 8022 u8 reserved_at_8[0x18]; 8023 8024 u8 syndrome[0x20]; 8025 8026 u8 reserved_at_40[0x40]; 8027 }; 8028 8029 struct mlx5_ifc_destroy_srq_in_bits { 8030 u8 opcode[0x10]; 8031 u8 uid[0x10]; 8032 8033 u8 reserved_at_20[0x10]; 8034 u8 op_mod[0x10]; 8035 8036 u8 reserved_at_40[0x8]; 8037 u8 srqn[0x18]; 8038 8039 u8 reserved_at_60[0x20]; 8040 }; 8041 8042 struct mlx5_ifc_destroy_sq_out_bits { 8043 u8 status[0x8]; 8044 u8 reserved_at_8[0x18]; 8045 8046 u8 syndrome[0x20]; 8047 8048 u8 reserved_at_40[0x40]; 8049 }; 8050 8051 struct mlx5_ifc_destroy_sq_in_bits { 8052 u8 opcode[0x10]; 8053 u8 uid[0x10]; 8054 8055 u8 reserved_at_20[0x10]; 8056 u8 op_mod[0x10]; 8057 8058 u8 reserved_at_40[0x8]; 8059 u8 sqn[0x18]; 8060 8061 u8 reserved_at_60[0x20]; 8062 }; 8063 8064 struct mlx5_ifc_destroy_scheduling_element_out_bits { 8065 u8 status[0x8]; 8066 u8 reserved_at_8[0x18]; 8067 8068 u8 syndrome[0x20]; 8069 8070 u8 reserved_at_40[0x1c0]; 8071 }; 8072 8073 struct mlx5_ifc_destroy_scheduling_element_in_bits { 8074 u8 opcode[0x10]; 8075 u8 reserved_at_10[0x10]; 8076 8077 u8 reserved_at_20[0x10]; 8078 u8 op_mod[0x10]; 8079 8080 u8 scheduling_hierarchy[0x8]; 8081 u8 reserved_at_48[0x18]; 8082 8083 u8 scheduling_element_id[0x20]; 8084 8085 u8 reserved_at_80[0x180]; 8086 }; 8087 8088 struct mlx5_ifc_destroy_rqt_out_bits { 8089 u8 status[0x8]; 8090 u8 reserved_at_8[0x18]; 8091 8092 u8 syndrome[0x20]; 8093 8094 u8 reserved_at_40[0x40]; 8095 }; 8096 8097 struct mlx5_ifc_destroy_rqt_in_bits { 8098 u8 opcode[0x10]; 8099 u8 uid[0x10]; 8100 8101 u8 reserved_at_20[0x10]; 8102 u8 op_mod[0x10]; 8103 8104 u8 reserved_at_40[0x8]; 8105 u8 rqtn[0x18]; 8106 8107 u8 reserved_at_60[0x20]; 8108 }; 8109 8110 struct mlx5_ifc_destroy_rq_out_bits { 8111 u8 status[0x8]; 8112 u8 reserved_at_8[0x18]; 8113 8114 u8 syndrome[0x20]; 8115 8116 u8 reserved_at_40[0x40]; 8117 }; 8118 8119 struct mlx5_ifc_destroy_rq_in_bits { 8120 u8 opcode[0x10]; 8121 u8 uid[0x10]; 8122 8123 u8 reserved_at_20[0x10]; 8124 u8 op_mod[0x10]; 8125 8126 u8 reserved_at_40[0x8]; 8127 u8 rqn[0x18]; 8128 8129 u8 reserved_at_60[0x20]; 8130 }; 8131 8132 struct mlx5_ifc_set_delay_drop_params_in_bits { 8133 u8 opcode[0x10]; 8134 u8 reserved_at_10[0x10]; 8135 8136 u8 reserved_at_20[0x10]; 8137 u8 op_mod[0x10]; 8138 8139 u8 reserved_at_40[0x20]; 8140 8141 u8 reserved_at_60[0x10]; 8142 u8 delay_drop_timeout[0x10]; 8143 }; 8144 8145 struct mlx5_ifc_set_delay_drop_params_out_bits { 8146 u8 status[0x8]; 8147 u8 reserved_at_8[0x18]; 8148 8149 u8 syndrome[0x20]; 8150 8151 u8 reserved_at_40[0x40]; 8152 }; 8153 8154 struct mlx5_ifc_destroy_rmp_out_bits { 8155 u8 status[0x8]; 8156 u8 reserved_at_8[0x18]; 8157 8158 u8 syndrome[0x20]; 8159 8160 u8 reserved_at_40[0x40]; 8161 }; 8162 8163 struct mlx5_ifc_destroy_rmp_in_bits { 8164 u8 opcode[0x10]; 8165 u8 uid[0x10]; 8166 8167 u8 reserved_at_20[0x10]; 8168 u8 op_mod[0x10]; 8169 8170 u8 reserved_at_40[0x8]; 8171 u8 rmpn[0x18]; 8172 8173 u8 reserved_at_60[0x20]; 8174 }; 8175 8176 struct mlx5_ifc_destroy_qp_out_bits { 8177 u8 status[0x8]; 8178 u8 reserved_at_8[0x18]; 8179 8180 u8 syndrome[0x20]; 8181 8182 u8 reserved_at_40[0x40]; 8183 }; 8184 8185 struct mlx5_ifc_destroy_qp_in_bits { 8186 u8 opcode[0x10]; 8187 u8 uid[0x10]; 8188 8189 u8 reserved_at_20[0x10]; 8190 u8 op_mod[0x10]; 8191 8192 u8 reserved_at_40[0x8]; 8193 u8 qpn[0x18]; 8194 8195 u8 reserved_at_60[0x20]; 8196 }; 8197 8198 struct mlx5_ifc_destroy_psv_out_bits { 8199 u8 status[0x8]; 8200 u8 reserved_at_8[0x18]; 8201 8202 u8 syndrome[0x20]; 8203 8204 u8 reserved_at_40[0x40]; 8205 }; 8206 8207 struct mlx5_ifc_destroy_psv_in_bits { 8208 u8 opcode[0x10]; 8209 u8 reserved_at_10[0x10]; 8210 8211 u8 reserved_at_20[0x10]; 8212 u8 op_mod[0x10]; 8213 8214 u8 reserved_at_40[0x8]; 8215 u8 psvn[0x18]; 8216 8217 u8 reserved_at_60[0x20]; 8218 }; 8219 8220 struct mlx5_ifc_destroy_mkey_out_bits { 8221 u8 status[0x8]; 8222 u8 reserved_at_8[0x18]; 8223 8224 u8 syndrome[0x20]; 8225 8226 u8 reserved_at_40[0x40]; 8227 }; 8228 8229 struct mlx5_ifc_destroy_mkey_in_bits { 8230 u8 opcode[0x10]; 8231 u8 uid[0x10]; 8232 8233 u8 reserved_at_20[0x10]; 8234 u8 op_mod[0x10]; 8235 8236 u8 reserved_at_40[0x8]; 8237 u8 mkey_index[0x18]; 8238 8239 u8 reserved_at_60[0x20]; 8240 }; 8241 8242 struct mlx5_ifc_destroy_flow_table_out_bits { 8243 u8 status[0x8]; 8244 u8 reserved_at_8[0x18]; 8245 8246 u8 syndrome[0x20]; 8247 8248 u8 reserved_at_40[0x40]; 8249 }; 8250 8251 struct mlx5_ifc_destroy_flow_table_in_bits { 8252 u8 opcode[0x10]; 8253 u8 reserved_at_10[0x10]; 8254 8255 u8 reserved_at_20[0x10]; 8256 u8 op_mod[0x10]; 8257 8258 u8 other_vport[0x1]; 8259 u8 reserved_at_41[0xf]; 8260 u8 vport_number[0x10]; 8261 8262 u8 reserved_at_60[0x20]; 8263 8264 u8 table_type[0x8]; 8265 u8 reserved_at_88[0x18]; 8266 8267 u8 reserved_at_a0[0x8]; 8268 u8 table_id[0x18]; 8269 8270 u8 reserved_at_c0[0x140]; 8271 }; 8272 8273 struct mlx5_ifc_destroy_flow_group_out_bits { 8274 u8 status[0x8]; 8275 u8 reserved_at_8[0x18]; 8276 8277 u8 syndrome[0x20]; 8278 8279 u8 reserved_at_40[0x40]; 8280 }; 8281 8282 struct mlx5_ifc_destroy_flow_group_in_bits { 8283 u8 opcode[0x10]; 8284 u8 reserved_at_10[0x10]; 8285 8286 u8 reserved_at_20[0x10]; 8287 u8 op_mod[0x10]; 8288 8289 u8 other_vport[0x1]; 8290 u8 reserved_at_41[0xf]; 8291 u8 vport_number[0x10]; 8292 8293 u8 reserved_at_60[0x20]; 8294 8295 u8 table_type[0x8]; 8296 u8 reserved_at_88[0x18]; 8297 8298 u8 reserved_at_a0[0x8]; 8299 u8 table_id[0x18]; 8300 8301 u8 group_id[0x20]; 8302 8303 u8 reserved_at_e0[0x120]; 8304 }; 8305 8306 struct mlx5_ifc_destroy_eq_out_bits { 8307 u8 status[0x8]; 8308 u8 reserved_at_8[0x18]; 8309 8310 u8 syndrome[0x20]; 8311 8312 u8 reserved_at_40[0x40]; 8313 }; 8314 8315 struct mlx5_ifc_destroy_eq_in_bits { 8316 u8 opcode[0x10]; 8317 u8 reserved_at_10[0x10]; 8318 8319 u8 reserved_at_20[0x10]; 8320 u8 op_mod[0x10]; 8321 8322 u8 reserved_at_40[0x18]; 8323 u8 eq_number[0x8]; 8324 8325 u8 reserved_at_60[0x20]; 8326 }; 8327 8328 struct mlx5_ifc_destroy_dct_out_bits { 8329 u8 status[0x8]; 8330 u8 reserved_at_8[0x18]; 8331 8332 u8 syndrome[0x20]; 8333 8334 u8 reserved_at_40[0x40]; 8335 }; 8336 8337 struct mlx5_ifc_destroy_dct_in_bits { 8338 u8 opcode[0x10]; 8339 u8 uid[0x10]; 8340 8341 u8 reserved_at_20[0x10]; 8342 u8 op_mod[0x10]; 8343 8344 u8 reserved_at_40[0x8]; 8345 u8 dctn[0x18]; 8346 8347 u8 reserved_at_60[0x20]; 8348 }; 8349 8350 struct mlx5_ifc_destroy_cq_out_bits { 8351 u8 status[0x8]; 8352 u8 reserved_at_8[0x18]; 8353 8354 u8 syndrome[0x20]; 8355 8356 u8 reserved_at_40[0x40]; 8357 }; 8358 8359 struct mlx5_ifc_destroy_cq_in_bits { 8360 u8 opcode[0x10]; 8361 u8 uid[0x10]; 8362 8363 u8 reserved_at_20[0x10]; 8364 u8 op_mod[0x10]; 8365 8366 u8 reserved_at_40[0x8]; 8367 u8 cqn[0x18]; 8368 8369 u8 reserved_at_60[0x20]; 8370 }; 8371 8372 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits { 8373 u8 status[0x8]; 8374 u8 reserved_at_8[0x18]; 8375 8376 u8 syndrome[0x20]; 8377 8378 u8 reserved_at_40[0x40]; 8379 }; 8380 8381 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits { 8382 u8 opcode[0x10]; 8383 u8 reserved_at_10[0x10]; 8384 8385 u8 reserved_at_20[0x10]; 8386 u8 op_mod[0x10]; 8387 8388 u8 reserved_at_40[0x20]; 8389 8390 u8 reserved_at_60[0x10]; 8391 u8 vxlan_udp_port[0x10]; 8392 }; 8393 8394 struct mlx5_ifc_delete_l2_table_entry_out_bits { 8395 u8 status[0x8]; 8396 u8 reserved_at_8[0x18]; 8397 8398 u8 syndrome[0x20]; 8399 8400 u8 reserved_at_40[0x40]; 8401 }; 8402 8403 struct mlx5_ifc_delete_l2_table_entry_in_bits { 8404 u8 opcode[0x10]; 8405 u8 reserved_at_10[0x10]; 8406 8407 u8 reserved_at_20[0x10]; 8408 u8 op_mod[0x10]; 8409 8410 u8 reserved_at_40[0x60]; 8411 8412 u8 reserved_at_a0[0x8]; 8413 u8 table_index[0x18]; 8414 8415 u8 reserved_at_c0[0x140]; 8416 }; 8417 8418 struct mlx5_ifc_delete_fte_out_bits { 8419 u8 status[0x8]; 8420 u8 reserved_at_8[0x18]; 8421 8422 u8 syndrome[0x20]; 8423 8424 u8 reserved_at_40[0x40]; 8425 }; 8426 8427 struct mlx5_ifc_delete_fte_in_bits { 8428 u8 opcode[0x10]; 8429 u8 reserved_at_10[0x10]; 8430 8431 u8 reserved_at_20[0x10]; 8432 u8 op_mod[0x10]; 8433 8434 u8 other_vport[0x1]; 8435 u8 reserved_at_41[0xf]; 8436 u8 vport_number[0x10]; 8437 8438 u8 reserved_at_60[0x20]; 8439 8440 u8 table_type[0x8]; 8441 u8 reserved_at_88[0x18]; 8442 8443 u8 reserved_at_a0[0x8]; 8444 u8 table_id[0x18]; 8445 8446 u8 reserved_at_c0[0x40]; 8447 8448 u8 flow_index[0x20]; 8449 8450 u8 reserved_at_120[0xe0]; 8451 }; 8452 8453 struct mlx5_ifc_dealloc_xrcd_out_bits { 8454 u8 status[0x8]; 8455 u8 reserved_at_8[0x18]; 8456 8457 u8 syndrome[0x20]; 8458 8459 u8 reserved_at_40[0x40]; 8460 }; 8461 8462 struct mlx5_ifc_dealloc_xrcd_in_bits { 8463 u8 opcode[0x10]; 8464 u8 uid[0x10]; 8465 8466 u8 reserved_at_20[0x10]; 8467 u8 op_mod[0x10]; 8468 8469 u8 reserved_at_40[0x8]; 8470 u8 xrcd[0x18]; 8471 8472 u8 reserved_at_60[0x20]; 8473 }; 8474 8475 struct mlx5_ifc_dealloc_uar_out_bits { 8476 u8 status[0x8]; 8477 u8 reserved_at_8[0x18]; 8478 8479 u8 syndrome[0x20]; 8480 8481 u8 reserved_at_40[0x40]; 8482 }; 8483 8484 struct mlx5_ifc_dealloc_uar_in_bits { 8485 u8 opcode[0x10]; 8486 u8 uid[0x10]; 8487 8488 u8 reserved_at_20[0x10]; 8489 u8 op_mod[0x10]; 8490 8491 u8 reserved_at_40[0x8]; 8492 u8 uar[0x18]; 8493 8494 u8 reserved_at_60[0x20]; 8495 }; 8496 8497 struct mlx5_ifc_dealloc_transport_domain_out_bits { 8498 u8 status[0x8]; 8499 u8 reserved_at_8[0x18]; 8500 8501 u8 syndrome[0x20]; 8502 8503 u8 reserved_at_40[0x40]; 8504 }; 8505 8506 struct mlx5_ifc_dealloc_transport_domain_in_bits { 8507 u8 opcode[0x10]; 8508 u8 uid[0x10]; 8509 8510 u8 reserved_at_20[0x10]; 8511 u8 op_mod[0x10]; 8512 8513 u8 reserved_at_40[0x8]; 8514 u8 transport_domain[0x18]; 8515 8516 u8 reserved_at_60[0x20]; 8517 }; 8518 8519 struct mlx5_ifc_dealloc_q_counter_out_bits { 8520 u8 status[0x8]; 8521 u8 reserved_at_8[0x18]; 8522 8523 u8 syndrome[0x20]; 8524 8525 u8 reserved_at_40[0x40]; 8526 }; 8527 8528 struct mlx5_ifc_dealloc_q_counter_in_bits { 8529 u8 opcode[0x10]; 8530 u8 reserved_at_10[0x10]; 8531 8532 u8 reserved_at_20[0x10]; 8533 u8 op_mod[0x10]; 8534 8535 u8 reserved_at_40[0x18]; 8536 u8 counter_set_id[0x8]; 8537 8538 u8 reserved_at_60[0x20]; 8539 }; 8540 8541 struct mlx5_ifc_dealloc_pd_out_bits { 8542 u8 status[0x8]; 8543 u8 reserved_at_8[0x18]; 8544 8545 u8 syndrome[0x20]; 8546 8547 u8 reserved_at_40[0x40]; 8548 }; 8549 8550 struct mlx5_ifc_dealloc_pd_in_bits { 8551 u8 opcode[0x10]; 8552 u8 uid[0x10]; 8553 8554 u8 reserved_at_20[0x10]; 8555 u8 op_mod[0x10]; 8556 8557 u8 reserved_at_40[0x8]; 8558 u8 pd[0x18]; 8559 8560 u8 reserved_at_60[0x20]; 8561 }; 8562 8563 struct mlx5_ifc_dealloc_flow_counter_out_bits { 8564 u8 status[0x8]; 8565 u8 reserved_at_8[0x18]; 8566 8567 u8 syndrome[0x20]; 8568 8569 u8 reserved_at_40[0x40]; 8570 }; 8571 8572 struct mlx5_ifc_dealloc_flow_counter_in_bits { 8573 u8 opcode[0x10]; 8574 u8 reserved_at_10[0x10]; 8575 8576 u8 reserved_at_20[0x10]; 8577 u8 op_mod[0x10]; 8578 8579 u8 flow_counter_id[0x20]; 8580 8581 u8 reserved_at_60[0x20]; 8582 }; 8583 8584 struct mlx5_ifc_create_xrq_out_bits { 8585 u8 status[0x8]; 8586 u8 reserved_at_8[0x18]; 8587 8588 u8 syndrome[0x20]; 8589 8590 u8 reserved_at_40[0x8]; 8591 u8 xrqn[0x18]; 8592 8593 u8 reserved_at_60[0x20]; 8594 }; 8595 8596 struct mlx5_ifc_create_xrq_in_bits { 8597 u8 opcode[0x10]; 8598 u8 uid[0x10]; 8599 8600 u8 reserved_at_20[0x10]; 8601 u8 op_mod[0x10]; 8602 8603 u8 reserved_at_40[0x40]; 8604 8605 struct mlx5_ifc_xrqc_bits xrq_context; 8606 }; 8607 8608 struct mlx5_ifc_create_xrc_srq_out_bits { 8609 u8 status[0x8]; 8610 u8 reserved_at_8[0x18]; 8611 8612 u8 syndrome[0x20]; 8613 8614 u8 reserved_at_40[0x8]; 8615 u8 xrc_srqn[0x18]; 8616 8617 u8 reserved_at_60[0x20]; 8618 }; 8619 8620 struct mlx5_ifc_create_xrc_srq_in_bits { 8621 u8 opcode[0x10]; 8622 u8 uid[0x10]; 8623 8624 u8 reserved_at_20[0x10]; 8625 u8 op_mod[0x10]; 8626 8627 u8 reserved_at_40[0x40]; 8628 8629 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 8630 8631 u8 reserved_at_280[0x60]; 8632 8633 u8 xrc_srq_umem_valid[0x1]; 8634 u8 reserved_at_2e1[0x1f]; 8635 8636 u8 reserved_at_300[0x580]; 8637 8638 u8 pas[][0x40]; 8639 }; 8640 8641 struct mlx5_ifc_create_tis_out_bits { 8642 u8 status[0x8]; 8643 u8 reserved_at_8[0x18]; 8644 8645 u8 syndrome[0x20]; 8646 8647 u8 reserved_at_40[0x8]; 8648 u8 tisn[0x18]; 8649 8650 u8 reserved_at_60[0x20]; 8651 }; 8652 8653 struct mlx5_ifc_create_tis_in_bits { 8654 u8 opcode[0x10]; 8655 u8 uid[0x10]; 8656 8657 u8 reserved_at_20[0x10]; 8658 u8 op_mod[0x10]; 8659 8660 u8 reserved_at_40[0xc0]; 8661 8662 struct mlx5_ifc_tisc_bits ctx; 8663 }; 8664 8665 struct mlx5_ifc_create_tir_out_bits { 8666 u8 status[0x8]; 8667 u8 icm_address_63_40[0x18]; 8668 8669 u8 syndrome[0x20]; 8670 8671 u8 icm_address_39_32[0x8]; 8672 u8 tirn[0x18]; 8673 8674 u8 icm_address_31_0[0x20]; 8675 }; 8676 8677 struct mlx5_ifc_create_tir_in_bits { 8678 u8 opcode[0x10]; 8679 u8 uid[0x10]; 8680 8681 u8 reserved_at_20[0x10]; 8682 u8 op_mod[0x10]; 8683 8684 u8 reserved_at_40[0xc0]; 8685 8686 struct mlx5_ifc_tirc_bits ctx; 8687 }; 8688 8689 struct mlx5_ifc_create_srq_out_bits { 8690 u8 status[0x8]; 8691 u8 reserved_at_8[0x18]; 8692 8693 u8 syndrome[0x20]; 8694 8695 u8 reserved_at_40[0x8]; 8696 u8 srqn[0x18]; 8697 8698 u8 reserved_at_60[0x20]; 8699 }; 8700 8701 struct mlx5_ifc_create_srq_in_bits { 8702 u8 opcode[0x10]; 8703 u8 uid[0x10]; 8704 8705 u8 reserved_at_20[0x10]; 8706 u8 op_mod[0x10]; 8707 8708 u8 reserved_at_40[0x40]; 8709 8710 struct mlx5_ifc_srqc_bits srq_context_entry; 8711 8712 u8 reserved_at_280[0x600]; 8713 8714 u8 pas[][0x40]; 8715 }; 8716 8717 struct mlx5_ifc_create_sq_out_bits { 8718 u8 status[0x8]; 8719 u8 reserved_at_8[0x18]; 8720 8721 u8 syndrome[0x20]; 8722 8723 u8 reserved_at_40[0x8]; 8724 u8 sqn[0x18]; 8725 8726 u8 reserved_at_60[0x20]; 8727 }; 8728 8729 struct mlx5_ifc_create_sq_in_bits { 8730 u8 opcode[0x10]; 8731 u8 uid[0x10]; 8732 8733 u8 reserved_at_20[0x10]; 8734 u8 op_mod[0x10]; 8735 8736 u8 reserved_at_40[0xc0]; 8737 8738 struct mlx5_ifc_sqc_bits ctx; 8739 }; 8740 8741 struct mlx5_ifc_create_scheduling_element_out_bits { 8742 u8 status[0x8]; 8743 u8 reserved_at_8[0x18]; 8744 8745 u8 syndrome[0x20]; 8746 8747 u8 reserved_at_40[0x40]; 8748 8749 u8 scheduling_element_id[0x20]; 8750 8751 u8 reserved_at_a0[0x160]; 8752 }; 8753 8754 struct mlx5_ifc_create_scheduling_element_in_bits { 8755 u8 opcode[0x10]; 8756 u8 reserved_at_10[0x10]; 8757 8758 u8 reserved_at_20[0x10]; 8759 u8 op_mod[0x10]; 8760 8761 u8 scheduling_hierarchy[0x8]; 8762 u8 reserved_at_48[0x18]; 8763 8764 u8 reserved_at_60[0xa0]; 8765 8766 struct mlx5_ifc_scheduling_context_bits scheduling_context; 8767 8768 u8 reserved_at_300[0x100]; 8769 }; 8770 8771 struct mlx5_ifc_create_rqt_out_bits { 8772 u8 status[0x8]; 8773 u8 reserved_at_8[0x18]; 8774 8775 u8 syndrome[0x20]; 8776 8777 u8 reserved_at_40[0x8]; 8778 u8 rqtn[0x18]; 8779 8780 u8 reserved_at_60[0x20]; 8781 }; 8782 8783 struct mlx5_ifc_create_rqt_in_bits { 8784 u8 opcode[0x10]; 8785 u8 uid[0x10]; 8786 8787 u8 reserved_at_20[0x10]; 8788 u8 op_mod[0x10]; 8789 8790 u8 reserved_at_40[0xc0]; 8791 8792 struct mlx5_ifc_rqtc_bits rqt_context; 8793 }; 8794 8795 struct mlx5_ifc_create_rq_out_bits { 8796 u8 status[0x8]; 8797 u8 reserved_at_8[0x18]; 8798 8799 u8 syndrome[0x20]; 8800 8801 u8 reserved_at_40[0x8]; 8802 u8 rqn[0x18]; 8803 8804 u8 reserved_at_60[0x20]; 8805 }; 8806 8807 struct mlx5_ifc_create_rq_in_bits { 8808 u8 opcode[0x10]; 8809 u8 uid[0x10]; 8810 8811 u8 reserved_at_20[0x10]; 8812 u8 op_mod[0x10]; 8813 8814 u8 reserved_at_40[0xc0]; 8815 8816 struct mlx5_ifc_rqc_bits ctx; 8817 }; 8818 8819 struct mlx5_ifc_create_rmp_out_bits { 8820 u8 status[0x8]; 8821 u8 reserved_at_8[0x18]; 8822 8823 u8 syndrome[0x20]; 8824 8825 u8 reserved_at_40[0x8]; 8826 u8 rmpn[0x18]; 8827 8828 u8 reserved_at_60[0x20]; 8829 }; 8830 8831 struct mlx5_ifc_create_rmp_in_bits { 8832 u8 opcode[0x10]; 8833 u8 uid[0x10]; 8834 8835 u8 reserved_at_20[0x10]; 8836 u8 op_mod[0x10]; 8837 8838 u8 reserved_at_40[0xc0]; 8839 8840 struct mlx5_ifc_rmpc_bits ctx; 8841 }; 8842 8843 struct mlx5_ifc_create_qp_out_bits { 8844 u8 status[0x8]; 8845 u8 reserved_at_8[0x18]; 8846 8847 u8 syndrome[0x20]; 8848 8849 u8 reserved_at_40[0x8]; 8850 u8 qpn[0x18]; 8851 8852 u8 ece[0x20]; 8853 }; 8854 8855 struct mlx5_ifc_create_qp_in_bits { 8856 u8 opcode[0x10]; 8857 u8 uid[0x10]; 8858 8859 u8 reserved_at_20[0x10]; 8860 u8 op_mod[0x10]; 8861 8862 u8 qpc_ext[0x1]; 8863 u8 reserved_at_41[0x7]; 8864 u8 input_qpn[0x18]; 8865 8866 u8 reserved_at_60[0x20]; 8867 u8 opt_param_mask[0x20]; 8868 8869 u8 ece[0x20]; 8870 8871 struct mlx5_ifc_qpc_bits qpc; 8872 8873 u8 reserved_at_800[0x60]; 8874 8875 u8 wq_umem_valid[0x1]; 8876 u8 reserved_at_861[0x1f]; 8877 8878 u8 pas[][0x40]; 8879 }; 8880 8881 struct mlx5_ifc_create_psv_out_bits { 8882 u8 status[0x8]; 8883 u8 reserved_at_8[0x18]; 8884 8885 u8 syndrome[0x20]; 8886 8887 u8 reserved_at_40[0x40]; 8888 8889 u8 reserved_at_80[0x8]; 8890 u8 psv0_index[0x18]; 8891 8892 u8 reserved_at_a0[0x8]; 8893 u8 psv1_index[0x18]; 8894 8895 u8 reserved_at_c0[0x8]; 8896 u8 psv2_index[0x18]; 8897 8898 u8 reserved_at_e0[0x8]; 8899 u8 psv3_index[0x18]; 8900 }; 8901 8902 struct mlx5_ifc_create_psv_in_bits { 8903 u8 opcode[0x10]; 8904 u8 reserved_at_10[0x10]; 8905 8906 u8 reserved_at_20[0x10]; 8907 u8 op_mod[0x10]; 8908 8909 u8 num_psv[0x4]; 8910 u8 reserved_at_44[0x4]; 8911 u8 pd[0x18]; 8912 8913 u8 reserved_at_60[0x20]; 8914 }; 8915 8916 struct mlx5_ifc_create_mkey_out_bits { 8917 u8 status[0x8]; 8918 u8 reserved_at_8[0x18]; 8919 8920 u8 syndrome[0x20]; 8921 8922 u8 reserved_at_40[0x8]; 8923 u8 mkey_index[0x18]; 8924 8925 u8 reserved_at_60[0x20]; 8926 }; 8927 8928 struct mlx5_ifc_create_mkey_in_bits { 8929 u8 opcode[0x10]; 8930 u8 uid[0x10]; 8931 8932 u8 reserved_at_20[0x10]; 8933 u8 op_mod[0x10]; 8934 8935 u8 reserved_at_40[0x20]; 8936 8937 u8 pg_access[0x1]; 8938 u8 mkey_umem_valid[0x1]; 8939 u8 reserved_at_62[0x1e]; 8940 8941 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 8942 8943 u8 reserved_at_280[0x80]; 8944 8945 u8 translations_octword_actual_size[0x20]; 8946 8947 u8 reserved_at_320[0x560]; 8948 8949 u8 klm_pas_mtt[][0x20]; 8950 }; 8951 8952 enum { 8953 MLX5_FLOW_TABLE_TYPE_NIC_RX = 0x0, 8954 MLX5_FLOW_TABLE_TYPE_NIC_TX = 0x1, 8955 MLX5_FLOW_TABLE_TYPE_ESW_EGRESS_ACL = 0x2, 8956 MLX5_FLOW_TABLE_TYPE_ESW_INGRESS_ACL = 0x3, 8957 MLX5_FLOW_TABLE_TYPE_FDB = 0X4, 8958 MLX5_FLOW_TABLE_TYPE_SNIFFER_RX = 0X5, 8959 MLX5_FLOW_TABLE_TYPE_SNIFFER_TX = 0X6, 8960 }; 8961 8962 struct mlx5_ifc_create_flow_table_out_bits { 8963 u8 status[0x8]; 8964 u8 icm_address_63_40[0x18]; 8965 8966 u8 syndrome[0x20]; 8967 8968 u8 icm_address_39_32[0x8]; 8969 u8 table_id[0x18]; 8970 8971 u8 icm_address_31_0[0x20]; 8972 }; 8973 8974 struct mlx5_ifc_create_flow_table_in_bits { 8975 u8 opcode[0x10]; 8976 u8 uid[0x10]; 8977 8978 u8 reserved_at_20[0x10]; 8979 u8 op_mod[0x10]; 8980 8981 u8 other_vport[0x1]; 8982 u8 reserved_at_41[0xf]; 8983 u8 vport_number[0x10]; 8984 8985 u8 reserved_at_60[0x20]; 8986 8987 u8 table_type[0x8]; 8988 u8 reserved_at_88[0x18]; 8989 8990 u8 reserved_at_a0[0x20]; 8991 8992 struct mlx5_ifc_flow_table_context_bits flow_table_context; 8993 }; 8994 8995 struct mlx5_ifc_create_flow_group_out_bits { 8996 u8 status[0x8]; 8997 u8 reserved_at_8[0x18]; 8998 8999 u8 syndrome[0x20]; 9000 9001 u8 reserved_at_40[0x8]; 9002 u8 group_id[0x18]; 9003 9004 u8 reserved_at_60[0x20]; 9005 }; 9006 9007 enum { 9008 MLX5_CREATE_FLOW_GROUP_IN_GROUP_TYPE_TCAM_SUBTABLE = 0x0, 9009 MLX5_CREATE_FLOW_GROUP_IN_GROUP_TYPE_HASH_SPLIT = 0x1, 9010 }; 9011 9012 enum { 9013 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 9014 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 9015 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 9016 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3, 9017 }; 9018 9019 struct mlx5_ifc_create_flow_group_in_bits { 9020 u8 opcode[0x10]; 9021 u8 reserved_at_10[0x10]; 9022 9023 u8 reserved_at_20[0x10]; 9024 u8 op_mod[0x10]; 9025 9026 u8 other_vport[0x1]; 9027 u8 reserved_at_41[0xf]; 9028 u8 vport_number[0x10]; 9029 9030 u8 reserved_at_60[0x20]; 9031 9032 u8 table_type[0x8]; 9033 u8 reserved_at_88[0x4]; 9034 u8 group_type[0x4]; 9035 u8 reserved_at_90[0x10]; 9036 9037 u8 reserved_at_a0[0x8]; 9038 u8 table_id[0x18]; 9039 9040 u8 source_eswitch_owner_vhca_id_valid[0x1]; 9041 9042 u8 reserved_at_c1[0x1f]; 9043 9044 u8 start_flow_index[0x20]; 9045 9046 u8 reserved_at_100[0x20]; 9047 9048 u8 end_flow_index[0x20]; 9049 9050 u8 reserved_at_140[0x10]; 9051 u8 match_definer_id[0x10]; 9052 9053 u8 reserved_at_160[0x80]; 9054 9055 u8 reserved_at_1e0[0x18]; 9056 u8 match_criteria_enable[0x8]; 9057 9058 struct mlx5_ifc_fte_match_param_bits match_criteria; 9059 9060 u8 reserved_at_1200[0xe00]; 9061 }; 9062 9063 struct mlx5_ifc_create_eq_out_bits { 9064 u8 status[0x8]; 9065 u8 reserved_at_8[0x18]; 9066 9067 u8 syndrome[0x20]; 9068 9069 u8 reserved_at_40[0x18]; 9070 u8 eq_number[0x8]; 9071 9072 u8 reserved_at_60[0x20]; 9073 }; 9074 9075 struct mlx5_ifc_create_eq_in_bits { 9076 u8 opcode[0x10]; 9077 u8 uid[0x10]; 9078 9079 u8 reserved_at_20[0x10]; 9080 u8 op_mod[0x10]; 9081 9082 u8 reserved_at_40[0x40]; 9083 9084 struct mlx5_ifc_eqc_bits eq_context_entry; 9085 9086 u8 reserved_at_280[0x40]; 9087 9088 u8 event_bitmask[4][0x40]; 9089 9090 u8 reserved_at_3c0[0x4c0]; 9091 9092 u8 pas[][0x40]; 9093 }; 9094 9095 struct mlx5_ifc_create_dct_out_bits { 9096 u8 status[0x8]; 9097 u8 reserved_at_8[0x18]; 9098 9099 u8 syndrome[0x20]; 9100 9101 u8 reserved_at_40[0x8]; 9102 u8 dctn[0x18]; 9103 9104 u8 ece[0x20]; 9105 }; 9106 9107 struct mlx5_ifc_create_dct_in_bits { 9108 u8 opcode[0x10]; 9109 u8 uid[0x10]; 9110 9111 u8 reserved_at_20[0x10]; 9112 u8 op_mod[0x10]; 9113 9114 u8 reserved_at_40[0x40]; 9115 9116 struct mlx5_ifc_dctc_bits dct_context_entry; 9117 9118 u8 reserved_at_280[0x180]; 9119 }; 9120 9121 struct mlx5_ifc_create_cq_out_bits { 9122 u8 status[0x8]; 9123 u8 reserved_at_8[0x18]; 9124 9125 u8 syndrome[0x20]; 9126 9127 u8 reserved_at_40[0x8]; 9128 u8 cqn[0x18]; 9129 9130 u8 reserved_at_60[0x20]; 9131 }; 9132 9133 struct mlx5_ifc_create_cq_in_bits { 9134 u8 opcode[0x10]; 9135 u8 uid[0x10]; 9136 9137 u8 reserved_at_20[0x10]; 9138 u8 op_mod[0x10]; 9139 9140 u8 reserved_at_40[0x40]; 9141 9142 struct mlx5_ifc_cqc_bits cq_context; 9143 9144 u8 reserved_at_280[0x60]; 9145 9146 u8 cq_umem_valid[0x1]; 9147 u8 reserved_at_2e1[0x59f]; 9148 9149 u8 pas[][0x40]; 9150 }; 9151 9152 struct mlx5_ifc_config_int_moderation_out_bits { 9153 u8 status[0x8]; 9154 u8 reserved_at_8[0x18]; 9155 9156 u8 syndrome[0x20]; 9157 9158 u8 reserved_at_40[0x4]; 9159 u8 min_delay[0xc]; 9160 u8 int_vector[0x10]; 9161 9162 u8 reserved_at_60[0x20]; 9163 }; 9164 9165 enum { 9166 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0, 9167 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1, 9168 }; 9169 9170 struct mlx5_ifc_config_int_moderation_in_bits { 9171 u8 opcode[0x10]; 9172 u8 reserved_at_10[0x10]; 9173 9174 u8 reserved_at_20[0x10]; 9175 u8 op_mod[0x10]; 9176 9177 u8 reserved_at_40[0x4]; 9178 u8 min_delay[0xc]; 9179 u8 int_vector[0x10]; 9180 9181 u8 reserved_at_60[0x20]; 9182 }; 9183 9184 struct mlx5_ifc_attach_to_mcg_out_bits { 9185 u8 status[0x8]; 9186 u8 reserved_at_8[0x18]; 9187 9188 u8 syndrome[0x20]; 9189 9190 u8 reserved_at_40[0x40]; 9191 }; 9192 9193 struct mlx5_ifc_attach_to_mcg_in_bits { 9194 u8 opcode[0x10]; 9195 u8 uid[0x10]; 9196 9197 u8 reserved_at_20[0x10]; 9198 u8 op_mod[0x10]; 9199 9200 u8 reserved_at_40[0x8]; 9201 u8 qpn[0x18]; 9202 9203 u8 reserved_at_60[0x20]; 9204 9205 u8 multicast_gid[16][0x8]; 9206 }; 9207 9208 struct mlx5_ifc_arm_xrq_out_bits { 9209 u8 status[0x8]; 9210 u8 reserved_at_8[0x18]; 9211 9212 u8 syndrome[0x20]; 9213 9214 u8 reserved_at_40[0x40]; 9215 }; 9216 9217 struct mlx5_ifc_arm_xrq_in_bits { 9218 u8 opcode[0x10]; 9219 u8 reserved_at_10[0x10]; 9220 9221 u8 reserved_at_20[0x10]; 9222 u8 op_mod[0x10]; 9223 9224 u8 reserved_at_40[0x8]; 9225 u8 xrqn[0x18]; 9226 9227 u8 reserved_at_60[0x10]; 9228 u8 lwm[0x10]; 9229 }; 9230 9231 struct mlx5_ifc_arm_xrc_srq_out_bits { 9232 u8 status[0x8]; 9233 u8 reserved_at_8[0x18]; 9234 9235 u8 syndrome[0x20]; 9236 9237 u8 reserved_at_40[0x40]; 9238 }; 9239 9240 enum { 9241 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1, 9242 }; 9243 9244 struct mlx5_ifc_arm_xrc_srq_in_bits { 9245 u8 opcode[0x10]; 9246 u8 uid[0x10]; 9247 9248 u8 reserved_at_20[0x10]; 9249 u8 op_mod[0x10]; 9250 9251 u8 reserved_at_40[0x8]; 9252 u8 xrc_srqn[0x18]; 9253 9254 u8 reserved_at_60[0x10]; 9255 u8 lwm[0x10]; 9256 }; 9257 9258 struct mlx5_ifc_arm_rq_out_bits { 9259 u8 status[0x8]; 9260 u8 reserved_at_8[0x18]; 9261 9262 u8 syndrome[0x20]; 9263 9264 u8 reserved_at_40[0x40]; 9265 }; 9266 9267 enum { 9268 MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1, 9269 MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2, 9270 }; 9271 9272 struct mlx5_ifc_arm_rq_in_bits { 9273 u8 opcode[0x10]; 9274 u8 uid[0x10]; 9275 9276 u8 reserved_at_20[0x10]; 9277 u8 op_mod[0x10]; 9278 9279 u8 reserved_at_40[0x8]; 9280 u8 srq_number[0x18]; 9281 9282 u8 reserved_at_60[0x10]; 9283 u8 lwm[0x10]; 9284 }; 9285 9286 struct mlx5_ifc_arm_dct_out_bits { 9287 u8 status[0x8]; 9288 u8 reserved_at_8[0x18]; 9289 9290 u8 syndrome[0x20]; 9291 9292 u8 reserved_at_40[0x40]; 9293 }; 9294 9295 struct mlx5_ifc_arm_dct_in_bits { 9296 u8 opcode[0x10]; 9297 u8 reserved_at_10[0x10]; 9298 9299 u8 reserved_at_20[0x10]; 9300 u8 op_mod[0x10]; 9301 9302 u8 reserved_at_40[0x8]; 9303 u8 dct_number[0x18]; 9304 9305 u8 reserved_at_60[0x20]; 9306 }; 9307 9308 struct mlx5_ifc_alloc_xrcd_out_bits { 9309 u8 status[0x8]; 9310 u8 reserved_at_8[0x18]; 9311 9312 u8 syndrome[0x20]; 9313 9314 u8 reserved_at_40[0x8]; 9315 u8 xrcd[0x18]; 9316 9317 u8 reserved_at_60[0x20]; 9318 }; 9319 9320 struct mlx5_ifc_alloc_xrcd_in_bits { 9321 u8 opcode[0x10]; 9322 u8 uid[0x10]; 9323 9324 u8 reserved_at_20[0x10]; 9325 u8 op_mod[0x10]; 9326 9327 u8 reserved_at_40[0x40]; 9328 }; 9329 9330 struct mlx5_ifc_alloc_uar_out_bits { 9331 u8 status[0x8]; 9332 u8 reserved_at_8[0x18]; 9333 9334 u8 syndrome[0x20]; 9335 9336 u8 reserved_at_40[0x8]; 9337 u8 uar[0x18]; 9338 9339 u8 reserved_at_60[0x20]; 9340 }; 9341 9342 struct mlx5_ifc_alloc_uar_in_bits { 9343 u8 opcode[0x10]; 9344 u8 uid[0x10]; 9345 9346 u8 reserved_at_20[0x10]; 9347 u8 op_mod[0x10]; 9348 9349 u8 reserved_at_40[0x40]; 9350 }; 9351 9352 struct mlx5_ifc_alloc_transport_domain_out_bits { 9353 u8 status[0x8]; 9354 u8 reserved_at_8[0x18]; 9355 9356 u8 syndrome[0x20]; 9357 9358 u8 reserved_at_40[0x8]; 9359 u8 transport_domain[0x18]; 9360 9361 u8 reserved_at_60[0x20]; 9362 }; 9363 9364 struct mlx5_ifc_alloc_transport_domain_in_bits { 9365 u8 opcode[0x10]; 9366 u8 uid[0x10]; 9367 9368 u8 reserved_at_20[0x10]; 9369 u8 op_mod[0x10]; 9370 9371 u8 reserved_at_40[0x40]; 9372 }; 9373 9374 struct mlx5_ifc_alloc_q_counter_out_bits { 9375 u8 status[0x8]; 9376 u8 reserved_at_8[0x18]; 9377 9378 u8 syndrome[0x20]; 9379 9380 u8 reserved_at_40[0x18]; 9381 u8 counter_set_id[0x8]; 9382 9383 u8 reserved_at_60[0x20]; 9384 }; 9385 9386 struct mlx5_ifc_alloc_q_counter_in_bits { 9387 u8 opcode[0x10]; 9388 u8 uid[0x10]; 9389 9390 u8 reserved_at_20[0x10]; 9391 u8 op_mod[0x10]; 9392 9393 u8 reserved_at_40[0x40]; 9394 }; 9395 9396 struct mlx5_ifc_alloc_pd_out_bits { 9397 u8 status[0x8]; 9398 u8 reserved_at_8[0x18]; 9399 9400 u8 syndrome[0x20]; 9401 9402 u8 reserved_at_40[0x8]; 9403 u8 pd[0x18]; 9404 9405 u8 reserved_at_60[0x20]; 9406 }; 9407 9408 struct mlx5_ifc_alloc_pd_in_bits { 9409 u8 opcode[0x10]; 9410 u8 uid[0x10]; 9411 9412 u8 reserved_at_20[0x10]; 9413 u8 op_mod[0x10]; 9414 9415 u8 reserved_at_40[0x40]; 9416 }; 9417 9418 struct mlx5_ifc_alloc_flow_counter_out_bits { 9419 u8 status[0x8]; 9420 u8 reserved_at_8[0x18]; 9421 9422 u8 syndrome[0x20]; 9423 9424 u8 flow_counter_id[0x20]; 9425 9426 u8 reserved_at_60[0x20]; 9427 }; 9428 9429 struct mlx5_ifc_alloc_flow_counter_in_bits { 9430 u8 opcode[0x10]; 9431 u8 reserved_at_10[0x10]; 9432 9433 u8 reserved_at_20[0x10]; 9434 u8 op_mod[0x10]; 9435 9436 u8 reserved_at_40[0x33]; 9437 u8 flow_counter_bulk_log_size[0x5]; 9438 u8 flow_counter_bulk[0x8]; 9439 }; 9440 9441 struct mlx5_ifc_add_vxlan_udp_dport_out_bits { 9442 u8 status[0x8]; 9443 u8 reserved_at_8[0x18]; 9444 9445 u8 syndrome[0x20]; 9446 9447 u8 reserved_at_40[0x40]; 9448 }; 9449 9450 struct mlx5_ifc_add_vxlan_udp_dport_in_bits { 9451 u8 opcode[0x10]; 9452 u8 reserved_at_10[0x10]; 9453 9454 u8 reserved_at_20[0x10]; 9455 u8 op_mod[0x10]; 9456 9457 u8 reserved_at_40[0x20]; 9458 9459 u8 reserved_at_60[0x10]; 9460 u8 vxlan_udp_port[0x10]; 9461 }; 9462 9463 struct mlx5_ifc_set_pp_rate_limit_out_bits { 9464 u8 status[0x8]; 9465 u8 reserved_at_8[0x18]; 9466 9467 u8 syndrome[0x20]; 9468 9469 u8 reserved_at_40[0x40]; 9470 }; 9471 9472 struct mlx5_ifc_set_pp_rate_limit_context_bits { 9473 u8 rate_limit[0x20]; 9474 9475 u8 burst_upper_bound[0x20]; 9476 9477 u8 reserved_at_40[0x10]; 9478 u8 typical_packet_size[0x10]; 9479 9480 u8 reserved_at_60[0x120]; 9481 }; 9482 9483 struct mlx5_ifc_set_pp_rate_limit_in_bits { 9484 u8 opcode[0x10]; 9485 u8 uid[0x10]; 9486 9487 u8 reserved_at_20[0x10]; 9488 u8 op_mod[0x10]; 9489 9490 u8 reserved_at_40[0x10]; 9491 u8 rate_limit_index[0x10]; 9492 9493 u8 reserved_at_60[0x20]; 9494 9495 struct mlx5_ifc_set_pp_rate_limit_context_bits ctx; 9496 }; 9497 9498 struct mlx5_ifc_access_register_out_bits { 9499 u8 status[0x8]; 9500 u8 reserved_at_8[0x18]; 9501 9502 u8 syndrome[0x20]; 9503 9504 u8 reserved_at_40[0x40]; 9505 9506 u8 register_data[][0x20]; 9507 }; 9508 9509 enum { 9510 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0, 9511 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1, 9512 }; 9513 9514 struct mlx5_ifc_access_register_in_bits { 9515 u8 opcode[0x10]; 9516 u8 reserved_at_10[0x10]; 9517 9518 u8 reserved_at_20[0x10]; 9519 u8 op_mod[0x10]; 9520 9521 u8 reserved_at_40[0x10]; 9522 u8 register_id[0x10]; 9523 9524 u8 argument[0x20]; 9525 9526 u8 register_data[][0x20]; 9527 }; 9528 9529 struct mlx5_ifc_sltp_reg_bits { 9530 u8 status[0x4]; 9531 u8 version[0x4]; 9532 u8 local_port[0x8]; 9533 u8 pnat[0x2]; 9534 u8 reserved_at_12[0x2]; 9535 u8 lane[0x4]; 9536 u8 reserved_at_18[0x8]; 9537 9538 u8 reserved_at_20[0x20]; 9539 9540 u8 reserved_at_40[0x7]; 9541 u8 polarity[0x1]; 9542 u8 ob_tap0[0x8]; 9543 u8 ob_tap1[0x8]; 9544 u8 ob_tap2[0x8]; 9545 9546 u8 reserved_at_60[0xc]; 9547 u8 ob_preemp_mode[0x4]; 9548 u8 ob_reg[0x8]; 9549 u8 ob_bias[0x8]; 9550 9551 u8 reserved_at_80[0x20]; 9552 }; 9553 9554 struct mlx5_ifc_slrg_reg_bits { 9555 u8 status[0x4]; 9556 u8 version[0x4]; 9557 u8 local_port[0x8]; 9558 u8 pnat[0x2]; 9559 u8 reserved_at_12[0x2]; 9560 u8 lane[0x4]; 9561 u8 reserved_at_18[0x8]; 9562 9563 u8 time_to_link_up[0x10]; 9564 u8 reserved_at_30[0xc]; 9565 u8 grade_lane_speed[0x4]; 9566 9567 u8 grade_version[0x8]; 9568 u8 grade[0x18]; 9569 9570 u8 reserved_at_60[0x4]; 9571 u8 height_grade_type[0x4]; 9572 u8 height_grade[0x18]; 9573 9574 u8 height_dz[0x10]; 9575 u8 height_dv[0x10]; 9576 9577 u8 reserved_at_a0[0x10]; 9578 u8 height_sigma[0x10]; 9579 9580 u8 reserved_at_c0[0x20]; 9581 9582 u8 reserved_at_e0[0x4]; 9583 u8 phase_grade_type[0x4]; 9584 u8 phase_grade[0x18]; 9585 9586 u8 reserved_at_100[0x8]; 9587 u8 phase_eo_pos[0x8]; 9588 u8 reserved_at_110[0x8]; 9589 u8 phase_eo_neg[0x8]; 9590 9591 u8 ffe_set_tested[0x10]; 9592 u8 test_errors_per_lane[0x10]; 9593 }; 9594 9595 struct mlx5_ifc_pvlc_reg_bits { 9596 u8 reserved_at_0[0x8]; 9597 u8 local_port[0x8]; 9598 u8 reserved_at_10[0x10]; 9599 9600 u8 reserved_at_20[0x1c]; 9601 u8 vl_hw_cap[0x4]; 9602 9603 u8 reserved_at_40[0x1c]; 9604 u8 vl_admin[0x4]; 9605 9606 u8 reserved_at_60[0x1c]; 9607 u8 vl_operational[0x4]; 9608 }; 9609 9610 struct mlx5_ifc_pude_reg_bits { 9611 u8 swid[0x8]; 9612 u8 local_port[0x8]; 9613 u8 reserved_at_10[0x4]; 9614 u8 admin_status[0x4]; 9615 u8 reserved_at_18[0x4]; 9616 u8 oper_status[0x4]; 9617 9618 u8 reserved_at_20[0x60]; 9619 }; 9620 9621 struct mlx5_ifc_ptys_reg_bits { 9622 u8 reserved_at_0[0x1]; 9623 u8 an_disable_admin[0x1]; 9624 u8 an_disable_cap[0x1]; 9625 u8 reserved_at_3[0x5]; 9626 u8 local_port[0x8]; 9627 u8 reserved_at_10[0xd]; 9628 u8 proto_mask[0x3]; 9629 9630 u8 an_status[0x4]; 9631 u8 reserved_at_24[0xc]; 9632 u8 data_rate_oper[0x10]; 9633 9634 u8 ext_eth_proto_capability[0x20]; 9635 9636 u8 eth_proto_capability[0x20]; 9637 9638 u8 ib_link_width_capability[0x10]; 9639 u8 ib_proto_capability[0x10]; 9640 9641 u8 ext_eth_proto_admin[0x20]; 9642 9643 u8 eth_proto_admin[0x20]; 9644 9645 u8 ib_link_width_admin[0x10]; 9646 u8 ib_proto_admin[0x10]; 9647 9648 u8 ext_eth_proto_oper[0x20]; 9649 9650 u8 eth_proto_oper[0x20]; 9651 9652 u8 ib_link_width_oper[0x10]; 9653 u8 ib_proto_oper[0x10]; 9654 9655 u8 reserved_at_160[0x1c]; 9656 u8 connector_type[0x4]; 9657 9658 u8 eth_proto_lp_advertise[0x20]; 9659 9660 u8 reserved_at_1a0[0x60]; 9661 }; 9662 9663 struct mlx5_ifc_mlcr_reg_bits { 9664 u8 reserved_at_0[0x8]; 9665 u8 local_port[0x8]; 9666 u8 reserved_at_10[0x20]; 9667 9668 u8 beacon_duration[0x10]; 9669 u8 reserved_at_40[0x10]; 9670 9671 u8 beacon_remain[0x10]; 9672 }; 9673 9674 struct mlx5_ifc_ptas_reg_bits { 9675 u8 reserved_at_0[0x20]; 9676 9677 u8 algorithm_options[0x10]; 9678 u8 reserved_at_30[0x4]; 9679 u8 repetitions_mode[0x4]; 9680 u8 num_of_repetitions[0x8]; 9681 9682 u8 grade_version[0x8]; 9683 u8 height_grade_type[0x4]; 9684 u8 phase_grade_type[0x4]; 9685 u8 height_grade_weight[0x8]; 9686 u8 phase_grade_weight[0x8]; 9687 9688 u8 gisim_measure_bits[0x10]; 9689 u8 adaptive_tap_measure_bits[0x10]; 9690 9691 u8 ber_bath_high_error_threshold[0x10]; 9692 u8 ber_bath_mid_error_threshold[0x10]; 9693 9694 u8 ber_bath_low_error_threshold[0x10]; 9695 u8 one_ratio_high_threshold[0x10]; 9696 9697 u8 one_ratio_high_mid_threshold[0x10]; 9698 u8 one_ratio_low_mid_threshold[0x10]; 9699 9700 u8 one_ratio_low_threshold[0x10]; 9701 u8 ndeo_error_threshold[0x10]; 9702 9703 u8 mixer_offset_step_size[0x10]; 9704 u8 reserved_at_110[0x8]; 9705 u8 mix90_phase_for_voltage_bath[0x8]; 9706 9707 u8 mixer_offset_start[0x10]; 9708 u8 mixer_offset_end[0x10]; 9709 9710 u8 reserved_at_140[0x15]; 9711 u8 ber_test_time[0xb]; 9712 }; 9713 9714 struct mlx5_ifc_pspa_reg_bits { 9715 u8 swid[0x8]; 9716 u8 local_port[0x8]; 9717 u8 sub_port[0x8]; 9718 u8 reserved_at_18[0x8]; 9719 9720 u8 reserved_at_20[0x20]; 9721 }; 9722 9723 struct mlx5_ifc_pqdr_reg_bits { 9724 u8 reserved_at_0[0x8]; 9725 u8 local_port[0x8]; 9726 u8 reserved_at_10[0x5]; 9727 u8 prio[0x3]; 9728 u8 reserved_at_18[0x6]; 9729 u8 mode[0x2]; 9730 9731 u8 reserved_at_20[0x20]; 9732 9733 u8 reserved_at_40[0x10]; 9734 u8 min_threshold[0x10]; 9735 9736 u8 reserved_at_60[0x10]; 9737 u8 max_threshold[0x10]; 9738 9739 u8 reserved_at_80[0x10]; 9740 u8 mark_probability_denominator[0x10]; 9741 9742 u8 reserved_at_a0[0x60]; 9743 }; 9744 9745 struct mlx5_ifc_ppsc_reg_bits { 9746 u8 reserved_at_0[0x8]; 9747 u8 local_port[0x8]; 9748 u8 reserved_at_10[0x10]; 9749 9750 u8 reserved_at_20[0x60]; 9751 9752 u8 reserved_at_80[0x1c]; 9753 u8 wrps_admin[0x4]; 9754 9755 u8 reserved_at_a0[0x1c]; 9756 u8 wrps_status[0x4]; 9757 9758 u8 reserved_at_c0[0x8]; 9759 u8 up_threshold[0x8]; 9760 u8 reserved_at_d0[0x8]; 9761 u8 down_threshold[0x8]; 9762 9763 u8 reserved_at_e0[0x20]; 9764 9765 u8 reserved_at_100[0x1c]; 9766 u8 srps_admin[0x4]; 9767 9768 u8 reserved_at_120[0x1c]; 9769 u8 srps_status[0x4]; 9770 9771 u8 reserved_at_140[0x40]; 9772 }; 9773 9774 struct mlx5_ifc_pplr_reg_bits { 9775 u8 reserved_at_0[0x8]; 9776 u8 local_port[0x8]; 9777 u8 reserved_at_10[0x10]; 9778 9779 u8 reserved_at_20[0x8]; 9780 u8 lb_cap[0x8]; 9781 u8 reserved_at_30[0x8]; 9782 u8 lb_en[0x8]; 9783 }; 9784 9785 struct mlx5_ifc_pplm_reg_bits { 9786 u8 reserved_at_0[0x8]; 9787 u8 local_port[0x8]; 9788 u8 reserved_at_10[0x10]; 9789 9790 u8 reserved_at_20[0x20]; 9791 9792 u8 port_profile_mode[0x8]; 9793 u8 static_port_profile[0x8]; 9794 u8 active_port_profile[0x8]; 9795 u8 reserved_at_58[0x8]; 9796 9797 u8 retransmission_active[0x8]; 9798 u8 fec_mode_active[0x18]; 9799 9800 u8 rs_fec_correction_bypass_cap[0x4]; 9801 u8 reserved_at_84[0x8]; 9802 u8 fec_override_cap_56g[0x4]; 9803 u8 fec_override_cap_100g[0x4]; 9804 u8 fec_override_cap_50g[0x4]; 9805 u8 fec_override_cap_25g[0x4]; 9806 u8 fec_override_cap_10g_40g[0x4]; 9807 9808 u8 rs_fec_correction_bypass_admin[0x4]; 9809 u8 reserved_at_a4[0x8]; 9810 u8 fec_override_admin_56g[0x4]; 9811 u8 fec_override_admin_100g[0x4]; 9812 u8 fec_override_admin_50g[0x4]; 9813 u8 fec_override_admin_25g[0x4]; 9814 u8 fec_override_admin_10g_40g[0x4]; 9815 9816 u8 fec_override_cap_400g_8x[0x10]; 9817 u8 fec_override_cap_200g_4x[0x10]; 9818 9819 u8 fec_override_cap_100g_2x[0x10]; 9820 u8 fec_override_cap_50g_1x[0x10]; 9821 9822 u8 fec_override_admin_400g_8x[0x10]; 9823 u8 fec_override_admin_200g_4x[0x10]; 9824 9825 u8 fec_override_admin_100g_2x[0x10]; 9826 u8 fec_override_admin_50g_1x[0x10]; 9827 9828 u8 fec_override_cap_800g_8x[0x10]; 9829 u8 fec_override_cap_400g_4x[0x10]; 9830 9831 u8 fec_override_cap_200g_2x[0x10]; 9832 u8 fec_override_cap_100g_1x[0x10]; 9833 9834 u8 reserved_at_180[0xa0]; 9835 9836 u8 fec_override_admin_800g_8x[0x10]; 9837 u8 fec_override_admin_400g_4x[0x10]; 9838 9839 u8 fec_override_admin_200g_2x[0x10]; 9840 u8 fec_override_admin_100g_1x[0x10]; 9841 9842 u8 reserved_at_260[0x20]; 9843 }; 9844 9845 struct mlx5_ifc_ppcnt_reg_bits { 9846 u8 swid[0x8]; 9847 u8 local_port[0x8]; 9848 u8 pnat[0x2]; 9849 u8 reserved_at_12[0x8]; 9850 u8 grp[0x6]; 9851 9852 u8 clr[0x1]; 9853 u8 reserved_at_21[0x1c]; 9854 u8 prio_tc[0x3]; 9855 9856 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set; 9857 }; 9858 9859 struct mlx5_ifc_mpein_reg_bits { 9860 u8 reserved_at_0[0x2]; 9861 u8 depth[0x6]; 9862 u8 pcie_index[0x8]; 9863 u8 node[0x8]; 9864 u8 reserved_at_18[0x8]; 9865 9866 u8 capability_mask[0x20]; 9867 9868 u8 reserved_at_40[0x8]; 9869 u8 link_width_enabled[0x8]; 9870 u8 link_speed_enabled[0x10]; 9871 9872 u8 lane0_physical_position[0x8]; 9873 u8 link_width_active[0x8]; 9874 u8 link_speed_active[0x10]; 9875 9876 u8 num_of_pfs[0x10]; 9877 u8 num_of_vfs[0x10]; 9878 9879 u8 bdf0[0x10]; 9880 u8 reserved_at_b0[0x10]; 9881 9882 u8 max_read_request_size[0x4]; 9883 u8 max_payload_size[0x4]; 9884 u8 reserved_at_c8[0x5]; 9885 u8 pwr_status[0x3]; 9886 u8 port_type[0x4]; 9887 u8 reserved_at_d4[0xb]; 9888 u8 lane_reversal[0x1]; 9889 9890 u8 reserved_at_e0[0x14]; 9891 u8 pci_power[0xc]; 9892 9893 u8 reserved_at_100[0x20]; 9894 9895 u8 device_status[0x10]; 9896 u8 port_state[0x8]; 9897 u8 reserved_at_138[0x8]; 9898 9899 u8 reserved_at_140[0x10]; 9900 u8 receiver_detect_result[0x10]; 9901 9902 u8 reserved_at_160[0x20]; 9903 }; 9904 9905 struct mlx5_ifc_mpcnt_reg_bits { 9906 u8 reserved_at_0[0x8]; 9907 u8 pcie_index[0x8]; 9908 u8 reserved_at_10[0xa]; 9909 u8 grp[0x6]; 9910 9911 u8 clr[0x1]; 9912 u8 reserved_at_21[0x1f]; 9913 9914 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set; 9915 }; 9916 9917 struct mlx5_ifc_ppad_reg_bits { 9918 u8 reserved_at_0[0x3]; 9919 u8 single_mac[0x1]; 9920 u8 reserved_at_4[0x4]; 9921 u8 local_port[0x8]; 9922 u8 mac_47_32[0x10]; 9923 9924 u8 mac_31_0[0x20]; 9925 9926 u8 reserved_at_40[0x40]; 9927 }; 9928 9929 struct mlx5_ifc_pmtu_reg_bits { 9930 u8 reserved_at_0[0x8]; 9931 u8 local_port[0x8]; 9932 u8 reserved_at_10[0x10]; 9933 9934 u8 max_mtu[0x10]; 9935 u8 reserved_at_30[0x10]; 9936 9937 u8 admin_mtu[0x10]; 9938 u8 reserved_at_50[0x10]; 9939 9940 u8 oper_mtu[0x10]; 9941 u8 reserved_at_70[0x10]; 9942 }; 9943 9944 struct mlx5_ifc_pmpr_reg_bits { 9945 u8 reserved_at_0[0x8]; 9946 u8 module[0x8]; 9947 u8 reserved_at_10[0x10]; 9948 9949 u8 reserved_at_20[0x18]; 9950 u8 attenuation_5g[0x8]; 9951 9952 u8 reserved_at_40[0x18]; 9953 u8 attenuation_7g[0x8]; 9954 9955 u8 reserved_at_60[0x18]; 9956 u8 attenuation_12g[0x8]; 9957 }; 9958 9959 struct mlx5_ifc_pmpe_reg_bits { 9960 u8 reserved_at_0[0x8]; 9961 u8 module[0x8]; 9962 u8 reserved_at_10[0xc]; 9963 u8 module_status[0x4]; 9964 9965 u8 reserved_at_20[0x60]; 9966 }; 9967 9968 struct mlx5_ifc_pmpc_reg_bits { 9969 u8 module_state_updated[32][0x8]; 9970 }; 9971 9972 struct mlx5_ifc_pmlpn_reg_bits { 9973 u8 reserved_at_0[0x4]; 9974 u8 mlpn_status[0x4]; 9975 u8 local_port[0x8]; 9976 u8 reserved_at_10[0x10]; 9977 9978 u8 e[0x1]; 9979 u8 reserved_at_21[0x1f]; 9980 }; 9981 9982 struct mlx5_ifc_pmlp_reg_bits { 9983 u8 rxtx[0x1]; 9984 u8 reserved_at_1[0x7]; 9985 u8 local_port[0x8]; 9986 u8 reserved_at_10[0x8]; 9987 u8 width[0x8]; 9988 9989 u8 lane0_module_mapping[0x20]; 9990 9991 u8 lane1_module_mapping[0x20]; 9992 9993 u8 lane2_module_mapping[0x20]; 9994 9995 u8 lane3_module_mapping[0x20]; 9996 9997 u8 reserved_at_a0[0x160]; 9998 }; 9999 10000 struct mlx5_ifc_pmaos_reg_bits { 10001 u8 reserved_at_0[0x8]; 10002 u8 module[0x8]; 10003 u8 reserved_at_10[0x4]; 10004 u8 admin_status[0x4]; 10005 u8 reserved_at_18[0x4]; 10006 u8 oper_status[0x4]; 10007 10008 u8 ase[0x1]; 10009 u8 ee[0x1]; 10010 u8 reserved_at_22[0x1c]; 10011 u8 e[0x2]; 10012 10013 u8 reserved_at_40[0x40]; 10014 }; 10015 10016 struct mlx5_ifc_plpc_reg_bits { 10017 u8 reserved_at_0[0x4]; 10018 u8 profile_id[0xc]; 10019 u8 reserved_at_10[0x4]; 10020 u8 proto_mask[0x4]; 10021 u8 reserved_at_18[0x8]; 10022 10023 u8 reserved_at_20[0x10]; 10024 u8 lane_speed[0x10]; 10025 10026 u8 reserved_at_40[0x17]; 10027 u8 lpbf[0x1]; 10028 u8 fec_mode_policy[0x8]; 10029 10030 u8 retransmission_capability[0x8]; 10031 u8 fec_mode_capability[0x18]; 10032 10033 u8 retransmission_support_admin[0x8]; 10034 u8 fec_mode_support_admin[0x18]; 10035 10036 u8 retransmission_request_admin[0x8]; 10037 u8 fec_mode_request_admin[0x18]; 10038 10039 u8 reserved_at_c0[0x80]; 10040 }; 10041 10042 struct mlx5_ifc_plib_reg_bits { 10043 u8 reserved_at_0[0x8]; 10044 u8 local_port[0x8]; 10045 u8 reserved_at_10[0x8]; 10046 u8 ib_port[0x8]; 10047 10048 u8 reserved_at_20[0x60]; 10049 }; 10050 10051 struct mlx5_ifc_plbf_reg_bits { 10052 u8 reserved_at_0[0x8]; 10053 u8 local_port[0x8]; 10054 u8 reserved_at_10[0xd]; 10055 u8 lbf_mode[0x3]; 10056 10057 u8 reserved_at_20[0x20]; 10058 }; 10059 10060 struct mlx5_ifc_pipg_reg_bits { 10061 u8 reserved_at_0[0x8]; 10062 u8 local_port[0x8]; 10063 u8 reserved_at_10[0x10]; 10064 10065 u8 dic[0x1]; 10066 u8 reserved_at_21[0x19]; 10067 u8 ipg[0x4]; 10068 u8 reserved_at_3e[0x2]; 10069 }; 10070 10071 struct mlx5_ifc_pifr_reg_bits { 10072 u8 reserved_at_0[0x8]; 10073 u8 local_port[0x8]; 10074 u8 reserved_at_10[0x10]; 10075 10076 u8 reserved_at_20[0xe0]; 10077 10078 u8 port_filter[8][0x20]; 10079 10080 u8 port_filter_update_en[8][0x20]; 10081 }; 10082 10083 struct mlx5_ifc_pfcc_reg_bits { 10084 u8 reserved_at_0[0x8]; 10085 u8 local_port[0x8]; 10086 u8 reserved_at_10[0xb]; 10087 u8 ppan_mask_n[0x1]; 10088 u8 minor_stall_mask[0x1]; 10089 u8 critical_stall_mask[0x1]; 10090 u8 reserved_at_1e[0x2]; 10091 10092 u8 ppan[0x4]; 10093 u8 reserved_at_24[0x4]; 10094 u8 prio_mask_tx[0x8]; 10095 u8 reserved_at_30[0x8]; 10096 u8 prio_mask_rx[0x8]; 10097 10098 u8 pptx[0x1]; 10099 u8 aptx[0x1]; 10100 u8 pptx_mask_n[0x1]; 10101 u8 reserved_at_43[0x5]; 10102 u8 pfctx[0x8]; 10103 u8 reserved_at_50[0x10]; 10104 10105 u8 pprx[0x1]; 10106 u8 aprx[0x1]; 10107 u8 pprx_mask_n[0x1]; 10108 u8 reserved_at_63[0x5]; 10109 u8 pfcrx[0x8]; 10110 u8 reserved_at_70[0x10]; 10111 10112 u8 device_stall_minor_watermark[0x10]; 10113 u8 device_stall_critical_watermark[0x10]; 10114 10115 u8 reserved_at_a0[0x60]; 10116 }; 10117 10118 struct mlx5_ifc_pelc_reg_bits { 10119 u8 op[0x4]; 10120 u8 reserved_at_4[0x4]; 10121 u8 local_port[0x8]; 10122 u8 reserved_at_10[0x10]; 10123 10124 u8 op_admin[0x8]; 10125 u8 op_capability[0x8]; 10126 u8 op_request[0x8]; 10127 u8 op_active[0x8]; 10128 10129 u8 admin[0x40]; 10130 10131 u8 capability[0x40]; 10132 10133 u8 request[0x40]; 10134 10135 u8 active[0x40]; 10136 10137 u8 reserved_at_140[0x80]; 10138 }; 10139 10140 struct mlx5_ifc_peir_reg_bits { 10141 u8 reserved_at_0[0x8]; 10142 u8 local_port[0x8]; 10143 u8 reserved_at_10[0x10]; 10144 10145 u8 reserved_at_20[0xc]; 10146 u8 error_count[0x4]; 10147 u8 reserved_at_30[0x10]; 10148 10149 u8 reserved_at_40[0xc]; 10150 u8 lane[0x4]; 10151 u8 reserved_at_50[0x8]; 10152 u8 error_type[0x8]; 10153 }; 10154 10155 struct mlx5_ifc_mpegc_reg_bits { 10156 u8 reserved_at_0[0x30]; 10157 u8 field_select[0x10]; 10158 10159 u8 tx_overflow_sense[0x1]; 10160 u8 mark_cqe[0x1]; 10161 u8 mark_cnp[0x1]; 10162 u8 reserved_at_43[0x1b]; 10163 u8 tx_lossy_overflow_oper[0x2]; 10164 10165 u8 reserved_at_60[0x100]; 10166 }; 10167 10168 struct mlx5_ifc_mpir_reg_bits { 10169 u8 sdm[0x1]; 10170 u8 reserved_at_1[0x1b]; 10171 u8 host_buses[0x4]; 10172 10173 u8 reserved_at_20[0x20]; 10174 10175 u8 local_port[0x8]; 10176 u8 reserved_at_28[0x18]; 10177 10178 u8 reserved_at_60[0x20]; 10179 }; 10180 10181 enum { 10182 MLX5_MTUTC_FREQ_ADJ_UNITS_PPB = 0x0, 10183 MLX5_MTUTC_FREQ_ADJ_UNITS_SCALED_PPM = 0x1, 10184 }; 10185 10186 enum { 10187 MLX5_MTUTC_OPERATION_SET_TIME_IMMEDIATE = 0x1, 10188 MLX5_MTUTC_OPERATION_ADJUST_TIME = 0x2, 10189 MLX5_MTUTC_OPERATION_ADJUST_FREQ_UTC = 0x3, 10190 }; 10191 10192 struct mlx5_ifc_mtutc_reg_bits { 10193 u8 reserved_at_0[0x5]; 10194 u8 freq_adj_units[0x3]; 10195 u8 reserved_at_8[0x3]; 10196 u8 log_max_freq_adjustment[0x5]; 10197 10198 u8 reserved_at_10[0xc]; 10199 u8 operation[0x4]; 10200 10201 u8 freq_adjustment[0x20]; 10202 10203 u8 reserved_at_40[0x40]; 10204 10205 u8 utc_sec[0x20]; 10206 10207 u8 reserved_at_a0[0x2]; 10208 u8 utc_nsec[0x1e]; 10209 10210 u8 time_adjustment[0x20]; 10211 }; 10212 10213 struct mlx5_ifc_pcam_enhanced_features_bits { 10214 u8 reserved_at_0[0x48]; 10215 u8 fec_100G_per_lane_in_pplm[0x1]; 10216 u8 reserved_at_49[0x1f]; 10217 u8 fec_50G_per_lane_in_pplm[0x1]; 10218 u8 reserved_at_69[0x4]; 10219 u8 rx_icrc_encapsulated_counter[0x1]; 10220 u8 reserved_at_6e[0x4]; 10221 u8 ptys_extended_ethernet[0x1]; 10222 u8 reserved_at_73[0x3]; 10223 u8 pfcc_mask[0x1]; 10224 u8 reserved_at_77[0x3]; 10225 u8 per_lane_error_counters[0x1]; 10226 u8 rx_buffer_fullness_counters[0x1]; 10227 u8 ptys_connector_type[0x1]; 10228 u8 reserved_at_7d[0x1]; 10229 u8 ppcnt_discard_group[0x1]; 10230 u8 ppcnt_statistical_group[0x1]; 10231 }; 10232 10233 struct mlx5_ifc_pcam_regs_5000_to_507f_bits { 10234 u8 port_access_reg_cap_mask_127_to_96[0x20]; 10235 u8 port_access_reg_cap_mask_95_to_64[0x20]; 10236 10237 u8 port_access_reg_cap_mask_63_to_36[0x1c]; 10238 u8 pplm[0x1]; 10239 u8 port_access_reg_cap_mask_34_to_32[0x3]; 10240 10241 u8 port_access_reg_cap_mask_31_to_13[0x13]; 10242 u8 pbmc[0x1]; 10243 u8 pptb[0x1]; 10244 u8 port_access_reg_cap_mask_10_to_09[0x2]; 10245 u8 ppcnt[0x1]; 10246 u8 port_access_reg_cap_mask_07_to_00[0x8]; 10247 }; 10248 10249 struct mlx5_ifc_pcam_reg_bits { 10250 u8 reserved_at_0[0x8]; 10251 u8 feature_group[0x8]; 10252 u8 reserved_at_10[0x8]; 10253 u8 access_reg_group[0x8]; 10254 10255 u8 reserved_at_20[0x20]; 10256 10257 union { 10258 struct mlx5_ifc_pcam_regs_5000_to_507f_bits regs_5000_to_507f; 10259 u8 reserved_at_0[0x80]; 10260 } port_access_reg_cap_mask; 10261 10262 u8 reserved_at_c0[0x80]; 10263 10264 union { 10265 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features; 10266 u8 reserved_at_0[0x80]; 10267 } feature_cap_mask; 10268 10269 u8 reserved_at_1c0[0xc0]; 10270 }; 10271 10272 struct mlx5_ifc_mcam_enhanced_features_bits { 10273 u8 reserved_at_0[0x50]; 10274 u8 mtutc_freq_adj_units[0x1]; 10275 u8 mtutc_time_adjustment_extended_range[0x1]; 10276 u8 reserved_at_52[0xb]; 10277 u8 mcia_32dwords[0x1]; 10278 u8 out_pulse_duration_ns[0x1]; 10279 u8 npps_period[0x1]; 10280 u8 reserved_at_60[0xa]; 10281 u8 reset_state[0x1]; 10282 u8 ptpcyc2realtime_modify[0x1]; 10283 u8 reserved_at_6c[0x2]; 10284 u8 pci_status_and_power[0x1]; 10285 u8 reserved_at_6f[0x5]; 10286 u8 mark_tx_action_cnp[0x1]; 10287 u8 mark_tx_action_cqe[0x1]; 10288 u8 dynamic_tx_overflow[0x1]; 10289 u8 reserved_at_77[0x4]; 10290 u8 pcie_outbound_stalled[0x1]; 10291 u8 tx_overflow_buffer_pkt[0x1]; 10292 u8 mtpps_enh_out_per_adj[0x1]; 10293 u8 mtpps_fs[0x1]; 10294 u8 pcie_performance_group[0x1]; 10295 }; 10296 10297 struct mlx5_ifc_mcam_access_reg_bits { 10298 u8 reserved_at_0[0x1c]; 10299 u8 mcda[0x1]; 10300 u8 mcc[0x1]; 10301 u8 mcqi[0x1]; 10302 u8 mcqs[0x1]; 10303 10304 u8 regs_95_to_90[0x6]; 10305 u8 mpir[0x1]; 10306 u8 regs_88_to_87[0x2]; 10307 u8 mpegc[0x1]; 10308 u8 mtutc[0x1]; 10309 u8 regs_84_to_68[0x11]; 10310 u8 tracer_registers[0x4]; 10311 10312 u8 regs_63_to_46[0x12]; 10313 u8 mrtc[0x1]; 10314 u8 regs_44_to_41[0x4]; 10315 u8 mfrl[0x1]; 10316 u8 regs_39_to_32[0x8]; 10317 10318 u8 regs_31_to_11[0x15]; 10319 u8 mtmp[0x1]; 10320 u8 regs_9_to_0[0xa]; 10321 }; 10322 10323 struct mlx5_ifc_mcam_access_reg_bits1 { 10324 u8 regs_127_to_96[0x20]; 10325 10326 u8 regs_95_to_64[0x20]; 10327 10328 u8 regs_63_to_32[0x20]; 10329 10330 u8 regs_31_to_0[0x20]; 10331 }; 10332 10333 struct mlx5_ifc_mcam_access_reg_bits2 { 10334 u8 regs_127_to_99[0x1d]; 10335 u8 mirc[0x1]; 10336 u8 regs_97_to_96[0x2]; 10337 10338 u8 regs_95_to_87[0x09]; 10339 u8 synce_registers[0x2]; 10340 u8 regs_84_to_64[0x15]; 10341 10342 u8 regs_63_to_32[0x20]; 10343 10344 u8 regs_31_to_0[0x20]; 10345 }; 10346 10347 struct mlx5_ifc_mcam_reg_bits { 10348 u8 reserved_at_0[0x8]; 10349 u8 feature_group[0x8]; 10350 u8 reserved_at_10[0x8]; 10351 u8 access_reg_group[0x8]; 10352 10353 u8 reserved_at_20[0x20]; 10354 10355 union { 10356 struct mlx5_ifc_mcam_access_reg_bits access_regs; 10357 struct mlx5_ifc_mcam_access_reg_bits1 access_regs1; 10358 struct mlx5_ifc_mcam_access_reg_bits2 access_regs2; 10359 u8 reserved_at_0[0x80]; 10360 } mng_access_reg_cap_mask; 10361 10362 u8 reserved_at_c0[0x80]; 10363 10364 union { 10365 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features; 10366 u8 reserved_at_0[0x80]; 10367 } mng_feature_cap_mask; 10368 10369 u8 reserved_at_1c0[0x80]; 10370 }; 10371 10372 struct mlx5_ifc_qcam_access_reg_cap_mask { 10373 u8 qcam_access_reg_cap_mask_127_to_20[0x6C]; 10374 u8 qpdpm[0x1]; 10375 u8 qcam_access_reg_cap_mask_18_to_4[0x0F]; 10376 u8 qdpm[0x1]; 10377 u8 qpts[0x1]; 10378 u8 qcap[0x1]; 10379 u8 qcam_access_reg_cap_mask_0[0x1]; 10380 }; 10381 10382 struct mlx5_ifc_qcam_qos_feature_cap_mask { 10383 u8 qcam_qos_feature_cap_mask_127_to_1[0x7F]; 10384 u8 qpts_trust_both[0x1]; 10385 }; 10386 10387 struct mlx5_ifc_qcam_reg_bits { 10388 u8 reserved_at_0[0x8]; 10389 u8 feature_group[0x8]; 10390 u8 reserved_at_10[0x8]; 10391 u8 access_reg_group[0x8]; 10392 u8 reserved_at_20[0x20]; 10393 10394 union { 10395 struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap; 10396 u8 reserved_at_0[0x80]; 10397 } qos_access_reg_cap_mask; 10398 10399 u8 reserved_at_c0[0x80]; 10400 10401 union { 10402 struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap; 10403 u8 reserved_at_0[0x80]; 10404 } qos_feature_cap_mask; 10405 10406 u8 reserved_at_1c0[0x80]; 10407 }; 10408 10409 struct mlx5_ifc_core_dump_reg_bits { 10410 u8 reserved_at_0[0x18]; 10411 u8 core_dump_type[0x8]; 10412 10413 u8 reserved_at_20[0x30]; 10414 u8 vhca_id[0x10]; 10415 10416 u8 reserved_at_60[0x8]; 10417 u8 qpn[0x18]; 10418 u8 reserved_at_80[0x180]; 10419 }; 10420 10421 struct mlx5_ifc_pcap_reg_bits { 10422 u8 reserved_at_0[0x8]; 10423 u8 local_port[0x8]; 10424 u8 reserved_at_10[0x10]; 10425 10426 u8 port_capability_mask[4][0x20]; 10427 }; 10428 10429 struct mlx5_ifc_paos_reg_bits { 10430 u8 swid[0x8]; 10431 u8 local_port[0x8]; 10432 u8 reserved_at_10[0x4]; 10433 u8 admin_status[0x4]; 10434 u8 reserved_at_18[0x4]; 10435 u8 oper_status[0x4]; 10436 10437 u8 ase[0x1]; 10438 u8 ee[0x1]; 10439 u8 reserved_at_22[0x1c]; 10440 u8 e[0x2]; 10441 10442 u8 reserved_at_40[0x40]; 10443 }; 10444 10445 struct mlx5_ifc_pamp_reg_bits { 10446 u8 reserved_at_0[0x8]; 10447 u8 opamp_group[0x8]; 10448 u8 reserved_at_10[0xc]; 10449 u8 opamp_group_type[0x4]; 10450 10451 u8 start_index[0x10]; 10452 u8 reserved_at_30[0x4]; 10453 u8 num_of_indices[0xc]; 10454 10455 u8 index_data[18][0x10]; 10456 }; 10457 10458 struct mlx5_ifc_pcmr_reg_bits { 10459 u8 reserved_at_0[0x8]; 10460 u8 local_port[0x8]; 10461 u8 reserved_at_10[0x10]; 10462 10463 u8 entropy_force_cap[0x1]; 10464 u8 entropy_calc_cap[0x1]; 10465 u8 entropy_gre_calc_cap[0x1]; 10466 u8 reserved_at_23[0xf]; 10467 u8 rx_ts_over_crc_cap[0x1]; 10468 u8 reserved_at_33[0xb]; 10469 u8 fcs_cap[0x1]; 10470 u8 reserved_at_3f[0x1]; 10471 10472 u8 entropy_force[0x1]; 10473 u8 entropy_calc[0x1]; 10474 u8 entropy_gre_calc[0x1]; 10475 u8 reserved_at_43[0xf]; 10476 u8 rx_ts_over_crc[0x1]; 10477 u8 reserved_at_53[0xb]; 10478 u8 fcs_chk[0x1]; 10479 u8 reserved_at_5f[0x1]; 10480 }; 10481 10482 struct mlx5_ifc_lane_2_module_mapping_bits { 10483 u8 reserved_at_0[0x4]; 10484 u8 rx_lane[0x4]; 10485 u8 reserved_at_8[0x4]; 10486 u8 tx_lane[0x4]; 10487 u8 reserved_at_10[0x8]; 10488 u8 module[0x8]; 10489 }; 10490 10491 struct mlx5_ifc_bufferx_reg_bits { 10492 u8 reserved_at_0[0x6]; 10493 u8 lossy[0x1]; 10494 u8 epsb[0x1]; 10495 u8 reserved_at_8[0x8]; 10496 u8 size[0x10]; 10497 10498 u8 xoff_threshold[0x10]; 10499 u8 xon_threshold[0x10]; 10500 }; 10501 10502 struct mlx5_ifc_set_node_in_bits { 10503 u8 node_description[64][0x8]; 10504 }; 10505 10506 struct mlx5_ifc_register_power_settings_bits { 10507 u8 reserved_at_0[0x18]; 10508 u8 power_settings_level[0x8]; 10509 10510 u8 reserved_at_20[0x60]; 10511 }; 10512 10513 struct mlx5_ifc_register_host_endianness_bits { 10514 u8 he[0x1]; 10515 u8 reserved_at_1[0x1f]; 10516 10517 u8 reserved_at_20[0x60]; 10518 }; 10519 10520 struct mlx5_ifc_umr_pointer_desc_argument_bits { 10521 u8 reserved_at_0[0x20]; 10522 10523 u8 mkey[0x20]; 10524 10525 u8 addressh_63_32[0x20]; 10526 10527 u8 addressl_31_0[0x20]; 10528 }; 10529 10530 struct mlx5_ifc_ud_adrs_vector_bits { 10531 u8 dc_key[0x40]; 10532 10533 u8 ext[0x1]; 10534 u8 reserved_at_41[0x7]; 10535 u8 destination_qp_dct[0x18]; 10536 10537 u8 static_rate[0x4]; 10538 u8 sl_eth_prio[0x4]; 10539 u8 fl[0x1]; 10540 u8 mlid[0x7]; 10541 u8 rlid_udp_sport[0x10]; 10542 10543 u8 reserved_at_80[0x20]; 10544 10545 u8 rmac_47_16[0x20]; 10546 10547 u8 rmac_15_0[0x10]; 10548 u8 tclass[0x8]; 10549 u8 hop_limit[0x8]; 10550 10551 u8 reserved_at_e0[0x1]; 10552 u8 grh[0x1]; 10553 u8 reserved_at_e2[0x2]; 10554 u8 src_addr_index[0x8]; 10555 u8 flow_label[0x14]; 10556 10557 u8 rgid_rip[16][0x8]; 10558 }; 10559 10560 struct mlx5_ifc_pages_req_event_bits { 10561 u8 reserved_at_0[0x10]; 10562 u8 function_id[0x10]; 10563 10564 u8 num_pages[0x20]; 10565 10566 u8 reserved_at_40[0xa0]; 10567 }; 10568 10569 struct mlx5_ifc_eqe_bits { 10570 u8 reserved_at_0[0x8]; 10571 u8 event_type[0x8]; 10572 u8 reserved_at_10[0x8]; 10573 u8 event_sub_type[0x8]; 10574 10575 u8 reserved_at_20[0xe0]; 10576 10577 union mlx5_ifc_event_auto_bits event_data; 10578 10579 u8 reserved_at_1e0[0x10]; 10580 u8 signature[0x8]; 10581 u8 reserved_at_1f8[0x7]; 10582 u8 owner[0x1]; 10583 }; 10584 10585 enum { 10586 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7, 10587 }; 10588 10589 struct mlx5_ifc_cmd_queue_entry_bits { 10590 u8 type[0x8]; 10591 u8 reserved_at_8[0x18]; 10592 10593 u8 input_length[0x20]; 10594 10595 u8 input_mailbox_pointer_63_32[0x20]; 10596 10597 u8 input_mailbox_pointer_31_9[0x17]; 10598 u8 reserved_at_77[0x9]; 10599 10600 u8 command_input_inline_data[16][0x8]; 10601 10602 u8 command_output_inline_data[16][0x8]; 10603 10604 u8 output_mailbox_pointer_63_32[0x20]; 10605 10606 u8 output_mailbox_pointer_31_9[0x17]; 10607 u8 reserved_at_1b7[0x9]; 10608 10609 u8 output_length[0x20]; 10610 10611 u8 token[0x8]; 10612 u8 signature[0x8]; 10613 u8 reserved_at_1f0[0x8]; 10614 u8 status[0x7]; 10615 u8 ownership[0x1]; 10616 }; 10617 10618 struct mlx5_ifc_cmd_out_bits { 10619 u8 status[0x8]; 10620 u8 reserved_at_8[0x18]; 10621 10622 u8 syndrome[0x20]; 10623 10624 u8 command_output[0x20]; 10625 }; 10626 10627 struct mlx5_ifc_cmd_in_bits { 10628 u8 opcode[0x10]; 10629 u8 reserved_at_10[0x10]; 10630 10631 u8 reserved_at_20[0x10]; 10632 u8 op_mod[0x10]; 10633 10634 u8 command[][0x20]; 10635 }; 10636 10637 struct mlx5_ifc_cmd_if_box_bits { 10638 u8 mailbox_data[512][0x8]; 10639 10640 u8 reserved_at_1000[0x180]; 10641 10642 u8 next_pointer_63_32[0x20]; 10643 10644 u8 next_pointer_31_10[0x16]; 10645 u8 reserved_at_11b6[0xa]; 10646 10647 u8 block_number[0x20]; 10648 10649 u8 reserved_at_11e0[0x8]; 10650 u8 token[0x8]; 10651 u8 ctrl_signature[0x8]; 10652 u8 signature[0x8]; 10653 }; 10654 10655 struct mlx5_ifc_mtt_bits { 10656 u8 ptag_63_32[0x20]; 10657 10658 u8 ptag_31_8[0x18]; 10659 u8 reserved_at_38[0x6]; 10660 u8 wr_en[0x1]; 10661 u8 rd_en[0x1]; 10662 }; 10663 10664 struct mlx5_ifc_query_wol_rol_out_bits { 10665 u8 status[0x8]; 10666 u8 reserved_at_8[0x18]; 10667 10668 u8 syndrome[0x20]; 10669 10670 u8 reserved_at_40[0x10]; 10671 u8 rol_mode[0x8]; 10672 u8 wol_mode[0x8]; 10673 10674 u8 reserved_at_60[0x20]; 10675 }; 10676 10677 struct mlx5_ifc_query_wol_rol_in_bits { 10678 u8 opcode[0x10]; 10679 u8 reserved_at_10[0x10]; 10680 10681 u8 reserved_at_20[0x10]; 10682 u8 op_mod[0x10]; 10683 10684 u8 reserved_at_40[0x40]; 10685 }; 10686 10687 struct mlx5_ifc_set_wol_rol_out_bits { 10688 u8 status[0x8]; 10689 u8 reserved_at_8[0x18]; 10690 10691 u8 syndrome[0x20]; 10692 10693 u8 reserved_at_40[0x40]; 10694 }; 10695 10696 struct mlx5_ifc_set_wol_rol_in_bits { 10697 u8 opcode[0x10]; 10698 u8 reserved_at_10[0x10]; 10699 10700 u8 reserved_at_20[0x10]; 10701 u8 op_mod[0x10]; 10702 10703 u8 rol_mode_valid[0x1]; 10704 u8 wol_mode_valid[0x1]; 10705 u8 reserved_at_42[0xe]; 10706 u8 rol_mode[0x8]; 10707 u8 wol_mode[0x8]; 10708 10709 u8 reserved_at_60[0x20]; 10710 }; 10711 10712 enum { 10713 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0, 10714 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1, 10715 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2, 10716 MLX5_INITIAL_SEG_NIC_INTERFACE_SW_RESET = 0x7, 10717 }; 10718 10719 enum { 10720 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0, 10721 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1, 10722 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2, 10723 }; 10724 10725 enum { 10726 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR = 0x1, 10727 MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC = 0x7, 10728 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR = 0x8, 10729 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR = 0x9, 10730 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR = 0xa, 10731 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR = 0xb, 10732 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN = 0xc, 10733 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR = 0xd, 10734 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV = 0xe, 10735 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR = 0xf, 10736 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR = 0x10, 10737 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PCI_POISONED_ERR = 0x12, 10738 }; 10739 10740 struct mlx5_ifc_initial_seg_bits { 10741 u8 fw_rev_minor[0x10]; 10742 u8 fw_rev_major[0x10]; 10743 10744 u8 cmd_interface_rev[0x10]; 10745 u8 fw_rev_subminor[0x10]; 10746 10747 u8 reserved_at_40[0x40]; 10748 10749 u8 cmdq_phy_addr_63_32[0x20]; 10750 10751 u8 cmdq_phy_addr_31_12[0x14]; 10752 u8 reserved_at_b4[0x2]; 10753 u8 nic_interface[0x2]; 10754 u8 log_cmdq_size[0x4]; 10755 u8 log_cmdq_stride[0x4]; 10756 10757 u8 command_doorbell_vector[0x20]; 10758 10759 u8 reserved_at_e0[0xf00]; 10760 10761 u8 initializing[0x1]; 10762 u8 reserved_at_fe1[0x4]; 10763 u8 nic_interface_supported[0x3]; 10764 u8 embedded_cpu[0x1]; 10765 u8 reserved_at_fe9[0x17]; 10766 10767 struct mlx5_ifc_health_buffer_bits health_buffer; 10768 10769 u8 no_dram_nic_offset[0x20]; 10770 10771 u8 reserved_at_1220[0x6e40]; 10772 10773 u8 reserved_at_8060[0x1f]; 10774 u8 clear_int[0x1]; 10775 10776 u8 health_syndrome[0x8]; 10777 u8 health_counter[0x18]; 10778 10779 u8 reserved_at_80a0[0x17fc0]; 10780 }; 10781 10782 struct mlx5_ifc_mtpps_reg_bits { 10783 u8 reserved_at_0[0xc]; 10784 u8 cap_number_of_pps_pins[0x4]; 10785 u8 reserved_at_10[0x4]; 10786 u8 cap_max_num_of_pps_in_pins[0x4]; 10787 u8 reserved_at_18[0x4]; 10788 u8 cap_max_num_of_pps_out_pins[0x4]; 10789 10790 u8 reserved_at_20[0x13]; 10791 u8 cap_log_min_npps_period[0x5]; 10792 u8 reserved_at_38[0x3]; 10793 u8 cap_log_min_out_pulse_duration_ns[0x5]; 10794 10795 u8 reserved_at_40[0x4]; 10796 u8 cap_pin_3_mode[0x4]; 10797 u8 reserved_at_48[0x4]; 10798 u8 cap_pin_2_mode[0x4]; 10799 u8 reserved_at_50[0x4]; 10800 u8 cap_pin_1_mode[0x4]; 10801 u8 reserved_at_58[0x4]; 10802 u8 cap_pin_0_mode[0x4]; 10803 10804 u8 reserved_at_60[0x4]; 10805 u8 cap_pin_7_mode[0x4]; 10806 u8 reserved_at_68[0x4]; 10807 u8 cap_pin_6_mode[0x4]; 10808 u8 reserved_at_70[0x4]; 10809 u8 cap_pin_5_mode[0x4]; 10810 u8 reserved_at_78[0x4]; 10811 u8 cap_pin_4_mode[0x4]; 10812 10813 u8 field_select[0x20]; 10814 u8 reserved_at_a0[0x20]; 10815 10816 u8 npps_period[0x40]; 10817 10818 u8 enable[0x1]; 10819 u8 reserved_at_101[0xb]; 10820 u8 pattern[0x4]; 10821 u8 reserved_at_110[0x4]; 10822 u8 pin_mode[0x4]; 10823 u8 pin[0x8]; 10824 10825 u8 reserved_at_120[0x2]; 10826 u8 out_pulse_duration_ns[0x1e]; 10827 10828 u8 time_stamp[0x40]; 10829 10830 u8 out_pulse_duration[0x10]; 10831 u8 out_periodic_adjustment[0x10]; 10832 u8 enhanced_out_periodic_adjustment[0x20]; 10833 10834 u8 reserved_at_1c0[0x20]; 10835 }; 10836 10837 struct mlx5_ifc_mtppse_reg_bits { 10838 u8 reserved_at_0[0x18]; 10839 u8 pin[0x8]; 10840 u8 event_arm[0x1]; 10841 u8 reserved_at_21[0x1b]; 10842 u8 event_generation_mode[0x4]; 10843 u8 reserved_at_40[0x40]; 10844 }; 10845 10846 struct mlx5_ifc_mcqs_reg_bits { 10847 u8 last_index_flag[0x1]; 10848 u8 reserved_at_1[0x7]; 10849 u8 fw_device[0x8]; 10850 u8 component_index[0x10]; 10851 10852 u8 reserved_at_20[0x10]; 10853 u8 identifier[0x10]; 10854 10855 u8 reserved_at_40[0x17]; 10856 u8 component_status[0x5]; 10857 u8 component_update_state[0x4]; 10858 10859 u8 last_update_state_changer_type[0x4]; 10860 u8 last_update_state_changer_host_id[0x4]; 10861 u8 reserved_at_68[0x18]; 10862 }; 10863 10864 struct mlx5_ifc_mcqi_cap_bits { 10865 u8 supported_info_bitmask[0x20]; 10866 10867 u8 component_size[0x20]; 10868 10869 u8 max_component_size[0x20]; 10870 10871 u8 log_mcda_word_size[0x4]; 10872 u8 reserved_at_64[0xc]; 10873 u8 mcda_max_write_size[0x10]; 10874 10875 u8 rd_en[0x1]; 10876 u8 reserved_at_81[0x1]; 10877 u8 match_chip_id[0x1]; 10878 u8 match_psid[0x1]; 10879 u8 check_user_timestamp[0x1]; 10880 u8 match_base_guid_mac[0x1]; 10881 u8 reserved_at_86[0x1a]; 10882 }; 10883 10884 struct mlx5_ifc_mcqi_version_bits { 10885 u8 reserved_at_0[0x2]; 10886 u8 build_time_valid[0x1]; 10887 u8 user_defined_time_valid[0x1]; 10888 u8 reserved_at_4[0x14]; 10889 u8 version_string_length[0x8]; 10890 10891 u8 version[0x20]; 10892 10893 u8 build_time[0x40]; 10894 10895 u8 user_defined_time[0x40]; 10896 10897 u8 build_tool_version[0x20]; 10898 10899 u8 reserved_at_e0[0x20]; 10900 10901 u8 version_string[92][0x8]; 10902 }; 10903 10904 struct mlx5_ifc_mcqi_activation_method_bits { 10905 u8 pending_server_ac_power_cycle[0x1]; 10906 u8 pending_server_dc_power_cycle[0x1]; 10907 u8 pending_server_reboot[0x1]; 10908 u8 pending_fw_reset[0x1]; 10909 u8 auto_activate[0x1]; 10910 u8 all_hosts_sync[0x1]; 10911 u8 device_hw_reset[0x1]; 10912 u8 reserved_at_7[0x19]; 10913 }; 10914 10915 union mlx5_ifc_mcqi_reg_data_bits { 10916 struct mlx5_ifc_mcqi_cap_bits mcqi_caps; 10917 struct mlx5_ifc_mcqi_version_bits mcqi_version; 10918 struct mlx5_ifc_mcqi_activation_method_bits mcqi_activation_mathod; 10919 }; 10920 10921 struct mlx5_ifc_mcqi_reg_bits { 10922 u8 read_pending_component[0x1]; 10923 u8 reserved_at_1[0xf]; 10924 u8 component_index[0x10]; 10925 10926 u8 reserved_at_20[0x20]; 10927 10928 u8 reserved_at_40[0x1b]; 10929 u8 info_type[0x5]; 10930 10931 u8 info_size[0x20]; 10932 10933 u8 offset[0x20]; 10934 10935 u8 reserved_at_a0[0x10]; 10936 u8 data_size[0x10]; 10937 10938 union mlx5_ifc_mcqi_reg_data_bits data[]; 10939 }; 10940 10941 struct mlx5_ifc_mcc_reg_bits { 10942 u8 reserved_at_0[0x4]; 10943 u8 time_elapsed_since_last_cmd[0xc]; 10944 u8 reserved_at_10[0x8]; 10945 u8 instruction[0x8]; 10946 10947 u8 reserved_at_20[0x10]; 10948 u8 component_index[0x10]; 10949 10950 u8 reserved_at_40[0x8]; 10951 u8 update_handle[0x18]; 10952 10953 u8 handle_owner_type[0x4]; 10954 u8 handle_owner_host_id[0x4]; 10955 u8 reserved_at_68[0x1]; 10956 u8 control_progress[0x7]; 10957 u8 error_code[0x8]; 10958 u8 reserved_at_78[0x4]; 10959 u8 control_state[0x4]; 10960 10961 u8 component_size[0x20]; 10962 10963 u8 reserved_at_a0[0x60]; 10964 }; 10965 10966 struct mlx5_ifc_mcda_reg_bits { 10967 u8 reserved_at_0[0x8]; 10968 u8 update_handle[0x18]; 10969 10970 u8 offset[0x20]; 10971 10972 u8 reserved_at_40[0x10]; 10973 u8 size[0x10]; 10974 10975 u8 reserved_at_60[0x20]; 10976 10977 u8 data[][0x20]; 10978 }; 10979 10980 enum { 10981 MLX5_MFRL_REG_RESET_STATE_IDLE = 0, 10982 MLX5_MFRL_REG_RESET_STATE_IN_NEGOTIATION = 1, 10983 MLX5_MFRL_REG_RESET_STATE_RESET_IN_PROGRESS = 2, 10984 MLX5_MFRL_REG_RESET_STATE_NEG_TIMEOUT = 3, 10985 MLX5_MFRL_REG_RESET_STATE_NACK = 4, 10986 MLX5_MFRL_REG_RESET_STATE_UNLOAD_TIMEOUT = 5, 10987 }; 10988 10989 enum { 10990 MLX5_MFRL_REG_RESET_TYPE_FULL_CHIP = BIT(0), 10991 MLX5_MFRL_REG_RESET_TYPE_NET_PORT_ALIVE = BIT(1), 10992 }; 10993 10994 enum { 10995 MLX5_MFRL_REG_RESET_LEVEL0 = BIT(0), 10996 MLX5_MFRL_REG_RESET_LEVEL3 = BIT(3), 10997 MLX5_MFRL_REG_RESET_LEVEL6 = BIT(6), 10998 }; 10999 11000 struct mlx5_ifc_mfrl_reg_bits { 11001 u8 reserved_at_0[0x20]; 11002 11003 u8 reserved_at_20[0x2]; 11004 u8 pci_sync_for_fw_update_start[0x1]; 11005 u8 pci_sync_for_fw_update_resp[0x2]; 11006 u8 rst_type_sel[0x3]; 11007 u8 reserved_at_28[0x4]; 11008 u8 reset_state[0x4]; 11009 u8 reset_type[0x8]; 11010 u8 reset_level[0x8]; 11011 }; 11012 11013 struct mlx5_ifc_mirc_reg_bits { 11014 u8 reserved_at_0[0x18]; 11015 u8 status_code[0x8]; 11016 11017 u8 reserved_at_20[0x20]; 11018 }; 11019 11020 struct mlx5_ifc_pddr_monitor_opcode_bits { 11021 u8 reserved_at_0[0x10]; 11022 u8 monitor_opcode[0x10]; 11023 }; 11024 11025 union mlx5_ifc_pddr_troubleshooting_page_status_opcode_auto_bits { 11026 struct mlx5_ifc_pddr_monitor_opcode_bits pddr_monitor_opcode; 11027 u8 reserved_at_0[0x20]; 11028 }; 11029 11030 enum { 11031 /* Monitor opcodes */ 11032 MLX5_PDDR_REG_TRBLSH_GROUP_OPCODE_MONITOR = 0x0, 11033 }; 11034 11035 struct mlx5_ifc_pddr_troubleshooting_page_bits { 11036 u8 reserved_at_0[0x10]; 11037 u8 group_opcode[0x10]; 11038 11039 union mlx5_ifc_pddr_troubleshooting_page_status_opcode_auto_bits status_opcode; 11040 11041 u8 reserved_at_40[0x20]; 11042 11043 u8 status_message[59][0x20]; 11044 }; 11045 11046 union mlx5_ifc_pddr_reg_page_data_auto_bits { 11047 struct mlx5_ifc_pddr_troubleshooting_page_bits pddr_troubleshooting_page; 11048 u8 reserved_at_0[0x7c0]; 11049 }; 11050 11051 enum { 11052 MLX5_PDDR_REG_PAGE_SELECT_TROUBLESHOOTING_INFO_PAGE = 0x1, 11053 }; 11054 11055 struct mlx5_ifc_pddr_reg_bits { 11056 u8 reserved_at_0[0x8]; 11057 u8 local_port[0x8]; 11058 u8 pnat[0x2]; 11059 u8 reserved_at_12[0xe]; 11060 11061 u8 reserved_at_20[0x18]; 11062 u8 page_select[0x8]; 11063 11064 union mlx5_ifc_pddr_reg_page_data_auto_bits page_data; 11065 }; 11066 11067 struct mlx5_ifc_mrtc_reg_bits { 11068 u8 time_synced[0x1]; 11069 u8 reserved_at_1[0x1f]; 11070 11071 u8 reserved_at_20[0x20]; 11072 11073 u8 time_h[0x20]; 11074 11075 u8 time_l[0x20]; 11076 }; 11077 11078 struct mlx5_ifc_mtcap_reg_bits { 11079 u8 reserved_at_0[0x19]; 11080 u8 sensor_count[0x7]; 11081 11082 u8 reserved_at_20[0x20]; 11083 11084 u8 sensor_map[0x40]; 11085 }; 11086 11087 struct mlx5_ifc_mtmp_reg_bits { 11088 u8 reserved_at_0[0x14]; 11089 u8 sensor_index[0xc]; 11090 11091 u8 reserved_at_20[0x10]; 11092 u8 temperature[0x10]; 11093 11094 u8 mte[0x1]; 11095 u8 mtr[0x1]; 11096 u8 reserved_at_42[0xe]; 11097 u8 max_temperature[0x10]; 11098 11099 u8 tee[0x2]; 11100 u8 reserved_at_62[0xe]; 11101 u8 temp_threshold_hi[0x10]; 11102 11103 u8 reserved_at_80[0x10]; 11104 u8 temp_threshold_lo[0x10]; 11105 11106 u8 reserved_at_a0[0x20]; 11107 11108 u8 sensor_name_hi[0x20]; 11109 u8 sensor_name_lo[0x20]; 11110 }; 11111 11112 union mlx5_ifc_ports_control_registers_document_bits { 11113 struct mlx5_ifc_bufferx_reg_bits bufferx_reg; 11114 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 11115 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 11116 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 11117 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 11118 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 11119 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 11120 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout; 11121 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout; 11122 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping; 11123 struct mlx5_ifc_pamp_reg_bits pamp_reg; 11124 struct mlx5_ifc_paos_reg_bits paos_reg; 11125 struct mlx5_ifc_pcap_reg_bits pcap_reg; 11126 struct mlx5_ifc_pddr_monitor_opcode_bits pddr_monitor_opcode; 11127 struct mlx5_ifc_pddr_reg_bits pddr_reg; 11128 struct mlx5_ifc_pddr_troubleshooting_page_bits pddr_troubleshooting_page; 11129 struct mlx5_ifc_peir_reg_bits peir_reg; 11130 struct mlx5_ifc_pelc_reg_bits pelc_reg; 11131 struct mlx5_ifc_pfcc_reg_bits pfcc_reg; 11132 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 11133 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 11134 struct mlx5_ifc_pifr_reg_bits pifr_reg; 11135 struct mlx5_ifc_pipg_reg_bits pipg_reg; 11136 struct mlx5_ifc_plbf_reg_bits plbf_reg; 11137 struct mlx5_ifc_plib_reg_bits plib_reg; 11138 struct mlx5_ifc_plpc_reg_bits plpc_reg; 11139 struct mlx5_ifc_pmaos_reg_bits pmaos_reg; 11140 struct mlx5_ifc_pmlp_reg_bits pmlp_reg; 11141 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg; 11142 struct mlx5_ifc_pmpc_reg_bits pmpc_reg; 11143 struct mlx5_ifc_pmpe_reg_bits pmpe_reg; 11144 struct mlx5_ifc_pmpr_reg_bits pmpr_reg; 11145 struct mlx5_ifc_pmtu_reg_bits pmtu_reg; 11146 struct mlx5_ifc_ppad_reg_bits ppad_reg; 11147 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg; 11148 struct mlx5_ifc_mpein_reg_bits mpein_reg; 11149 struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg; 11150 struct mlx5_ifc_pplm_reg_bits pplm_reg; 11151 struct mlx5_ifc_pplr_reg_bits pplr_reg; 11152 struct mlx5_ifc_ppsc_reg_bits ppsc_reg; 11153 struct mlx5_ifc_pqdr_reg_bits pqdr_reg; 11154 struct mlx5_ifc_pspa_reg_bits pspa_reg; 11155 struct mlx5_ifc_ptas_reg_bits ptas_reg; 11156 struct mlx5_ifc_ptys_reg_bits ptys_reg; 11157 struct mlx5_ifc_mlcr_reg_bits mlcr_reg; 11158 struct mlx5_ifc_pude_reg_bits pude_reg; 11159 struct mlx5_ifc_pvlc_reg_bits pvlc_reg; 11160 struct mlx5_ifc_slrg_reg_bits slrg_reg; 11161 struct mlx5_ifc_sltp_reg_bits sltp_reg; 11162 struct mlx5_ifc_mtpps_reg_bits mtpps_reg; 11163 struct mlx5_ifc_mtppse_reg_bits mtppse_reg; 11164 struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg; 11165 struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits; 11166 struct mlx5_ifc_fpga_cap_bits fpga_cap_bits; 11167 struct mlx5_ifc_mcqi_reg_bits mcqi_reg; 11168 struct mlx5_ifc_mcc_reg_bits mcc_reg; 11169 struct mlx5_ifc_mcda_reg_bits mcda_reg; 11170 struct mlx5_ifc_mirc_reg_bits mirc_reg; 11171 struct mlx5_ifc_mfrl_reg_bits mfrl_reg; 11172 struct mlx5_ifc_mtutc_reg_bits mtutc_reg; 11173 struct mlx5_ifc_mrtc_reg_bits mrtc_reg; 11174 struct mlx5_ifc_mtcap_reg_bits mtcap_reg; 11175 struct mlx5_ifc_mtmp_reg_bits mtmp_reg; 11176 u8 reserved_at_0[0x60e0]; 11177 }; 11178 11179 union mlx5_ifc_debug_enhancements_document_bits { 11180 struct mlx5_ifc_health_buffer_bits health_buffer; 11181 u8 reserved_at_0[0x200]; 11182 }; 11183 11184 union mlx5_ifc_uplink_pci_interface_document_bits { 11185 struct mlx5_ifc_initial_seg_bits initial_seg; 11186 u8 reserved_at_0[0x20060]; 11187 }; 11188 11189 struct mlx5_ifc_set_flow_table_root_out_bits { 11190 u8 status[0x8]; 11191 u8 reserved_at_8[0x18]; 11192 11193 u8 syndrome[0x20]; 11194 11195 u8 reserved_at_40[0x40]; 11196 }; 11197 11198 struct mlx5_ifc_set_flow_table_root_in_bits { 11199 u8 opcode[0x10]; 11200 u8 reserved_at_10[0x10]; 11201 11202 u8 reserved_at_20[0x10]; 11203 u8 op_mod[0x10]; 11204 11205 u8 other_vport[0x1]; 11206 u8 reserved_at_41[0xf]; 11207 u8 vport_number[0x10]; 11208 11209 u8 reserved_at_60[0x20]; 11210 11211 u8 table_type[0x8]; 11212 u8 reserved_at_88[0x7]; 11213 u8 table_of_other_vport[0x1]; 11214 u8 table_vport_number[0x10]; 11215 11216 u8 reserved_at_a0[0x8]; 11217 u8 table_id[0x18]; 11218 11219 u8 reserved_at_c0[0x8]; 11220 u8 underlay_qpn[0x18]; 11221 u8 table_eswitch_owner_vhca_id_valid[0x1]; 11222 u8 reserved_at_e1[0xf]; 11223 u8 table_eswitch_owner_vhca_id[0x10]; 11224 u8 reserved_at_100[0x100]; 11225 }; 11226 11227 enum { 11228 MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = (1UL << 0), 11229 MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15), 11230 }; 11231 11232 struct mlx5_ifc_modify_flow_table_out_bits { 11233 u8 status[0x8]; 11234 u8 reserved_at_8[0x18]; 11235 11236 u8 syndrome[0x20]; 11237 11238 u8 reserved_at_40[0x40]; 11239 }; 11240 11241 struct mlx5_ifc_modify_flow_table_in_bits { 11242 u8 opcode[0x10]; 11243 u8 reserved_at_10[0x10]; 11244 11245 u8 reserved_at_20[0x10]; 11246 u8 op_mod[0x10]; 11247 11248 u8 other_vport[0x1]; 11249 u8 reserved_at_41[0xf]; 11250 u8 vport_number[0x10]; 11251 11252 u8 reserved_at_60[0x10]; 11253 u8 modify_field_select[0x10]; 11254 11255 u8 table_type[0x8]; 11256 u8 reserved_at_88[0x18]; 11257 11258 u8 reserved_at_a0[0x8]; 11259 u8 table_id[0x18]; 11260 11261 struct mlx5_ifc_flow_table_context_bits flow_table_context; 11262 }; 11263 11264 struct mlx5_ifc_ets_tcn_config_reg_bits { 11265 u8 g[0x1]; 11266 u8 b[0x1]; 11267 u8 r[0x1]; 11268 u8 reserved_at_3[0x9]; 11269 u8 group[0x4]; 11270 u8 reserved_at_10[0x9]; 11271 u8 bw_allocation[0x7]; 11272 11273 u8 reserved_at_20[0xc]; 11274 u8 max_bw_units[0x4]; 11275 u8 reserved_at_30[0x8]; 11276 u8 max_bw_value[0x8]; 11277 }; 11278 11279 struct mlx5_ifc_ets_global_config_reg_bits { 11280 u8 reserved_at_0[0x2]; 11281 u8 r[0x1]; 11282 u8 reserved_at_3[0x1d]; 11283 11284 u8 reserved_at_20[0xc]; 11285 u8 max_bw_units[0x4]; 11286 u8 reserved_at_30[0x8]; 11287 u8 max_bw_value[0x8]; 11288 }; 11289 11290 struct mlx5_ifc_qetc_reg_bits { 11291 u8 reserved_at_0[0x8]; 11292 u8 port_number[0x8]; 11293 u8 reserved_at_10[0x30]; 11294 11295 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8]; 11296 struct mlx5_ifc_ets_global_config_reg_bits global_configuration; 11297 }; 11298 11299 struct mlx5_ifc_qpdpm_dscp_reg_bits { 11300 u8 e[0x1]; 11301 u8 reserved_at_01[0x0b]; 11302 u8 prio[0x04]; 11303 }; 11304 11305 struct mlx5_ifc_qpdpm_reg_bits { 11306 u8 reserved_at_0[0x8]; 11307 u8 local_port[0x8]; 11308 u8 reserved_at_10[0x10]; 11309 struct mlx5_ifc_qpdpm_dscp_reg_bits dscp[64]; 11310 }; 11311 11312 struct mlx5_ifc_qpts_reg_bits { 11313 u8 reserved_at_0[0x8]; 11314 u8 local_port[0x8]; 11315 u8 reserved_at_10[0x2d]; 11316 u8 trust_state[0x3]; 11317 }; 11318 11319 struct mlx5_ifc_pptb_reg_bits { 11320 u8 reserved_at_0[0x2]; 11321 u8 mm[0x2]; 11322 u8 reserved_at_4[0x4]; 11323 u8 local_port[0x8]; 11324 u8 reserved_at_10[0x6]; 11325 u8 cm[0x1]; 11326 u8 um[0x1]; 11327 u8 pm[0x8]; 11328 11329 u8 prio_x_buff[0x20]; 11330 11331 u8 pm_msb[0x8]; 11332 u8 reserved_at_48[0x10]; 11333 u8 ctrl_buff[0x4]; 11334 u8 untagged_buff[0x4]; 11335 }; 11336 11337 struct mlx5_ifc_sbcam_reg_bits { 11338 u8 reserved_at_0[0x8]; 11339 u8 feature_group[0x8]; 11340 u8 reserved_at_10[0x8]; 11341 u8 access_reg_group[0x8]; 11342 11343 u8 reserved_at_20[0x20]; 11344 11345 u8 sb_access_reg_cap_mask[4][0x20]; 11346 11347 u8 reserved_at_c0[0x80]; 11348 11349 u8 sb_feature_cap_mask[4][0x20]; 11350 11351 u8 reserved_at_1c0[0x40]; 11352 11353 u8 cap_total_buffer_size[0x20]; 11354 11355 u8 cap_cell_size[0x10]; 11356 u8 cap_max_pg_buffers[0x8]; 11357 u8 cap_num_pool_supported[0x8]; 11358 11359 u8 reserved_at_240[0x8]; 11360 u8 cap_sbsr_stat_size[0x8]; 11361 u8 cap_max_tclass_data[0x8]; 11362 u8 cap_max_cpu_ingress_tclass_sb[0x8]; 11363 }; 11364 11365 struct mlx5_ifc_pbmc_reg_bits { 11366 u8 reserved_at_0[0x8]; 11367 u8 local_port[0x8]; 11368 u8 reserved_at_10[0x10]; 11369 11370 u8 xoff_timer_value[0x10]; 11371 u8 xoff_refresh[0x10]; 11372 11373 u8 reserved_at_40[0x9]; 11374 u8 fullness_threshold[0x7]; 11375 u8 port_buffer_size[0x10]; 11376 11377 struct mlx5_ifc_bufferx_reg_bits buffer[10]; 11378 11379 u8 reserved_at_2e0[0x80]; 11380 }; 11381 11382 struct mlx5_ifc_sbpr_reg_bits { 11383 u8 desc[0x1]; 11384 u8 snap[0x1]; 11385 u8 reserved_at_2[0x4]; 11386 u8 dir[0x2]; 11387 u8 reserved_at_8[0x14]; 11388 u8 pool[0x4]; 11389 11390 u8 infi_size[0x1]; 11391 u8 reserved_at_21[0x7]; 11392 u8 size[0x18]; 11393 11394 u8 reserved_at_40[0x1c]; 11395 u8 mode[0x4]; 11396 11397 u8 reserved_at_60[0x8]; 11398 u8 buff_occupancy[0x18]; 11399 11400 u8 clr[0x1]; 11401 u8 reserved_at_81[0x7]; 11402 u8 max_buff_occupancy[0x18]; 11403 11404 u8 reserved_at_a0[0x8]; 11405 u8 ext_buff_occupancy[0x18]; 11406 }; 11407 11408 struct mlx5_ifc_sbcm_reg_bits { 11409 u8 desc[0x1]; 11410 u8 snap[0x1]; 11411 u8 reserved_at_2[0x6]; 11412 u8 local_port[0x8]; 11413 u8 pnat[0x2]; 11414 u8 pg_buff[0x6]; 11415 u8 reserved_at_18[0x6]; 11416 u8 dir[0x2]; 11417 11418 u8 reserved_at_20[0x1f]; 11419 u8 exc[0x1]; 11420 11421 u8 reserved_at_40[0x40]; 11422 11423 u8 reserved_at_80[0x8]; 11424 u8 buff_occupancy[0x18]; 11425 11426 u8 clr[0x1]; 11427 u8 reserved_at_a1[0x7]; 11428 u8 max_buff_occupancy[0x18]; 11429 11430 u8 reserved_at_c0[0x8]; 11431 u8 min_buff[0x18]; 11432 11433 u8 infi_max[0x1]; 11434 u8 reserved_at_e1[0x7]; 11435 u8 max_buff[0x18]; 11436 11437 u8 reserved_at_100[0x20]; 11438 11439 u8 reserved_at_120[0x1c]; 11440 u8 pool[0x4]; 11441 }; 11442 11443 struct mlx5_ifc_qtct_reg_bits { 11444 u8 reserved_at_0[0x8]; 11445 u8 port_number[0x8]; 11446 u8 reserved_at_10[0xd]; 11447 u8 prio[0x3]; 11448 11449 u8 reserved_at_20[0x1d]; 11450 u8 tclass[0x3]; 11451 }; 11452 11453 struct mlx5_ifc_mcia_reg_bits { 11454 u8 l[0x1]; 11455 u8 reserved_at_1[0x7]; 11456 u8 module[0x8]; 11457 u8 reserved_at_10[0x8]; 11458 u8 status[0x8]; 11459 11460 u8 i2c_device_address[0x8]; 11461 u8 page_number[0x8]; 11462 u8 device_address[0x10]; 11463 11464 u8 reserved_at_40[0x10]; 11465 u8 size[0x10]; 11466 11467 u8 reserved_at_60[0x20]; 11468 11469 u8 dword_0[0x20]; 11470 u8 dword_1[0x20]; 11471 u8 dword_2[0x20]; 11472 u8 dword_3[0x20]; 11473 u8 dword_4[0x20]; 11474 u8 dword_5[0x20]; 11475 u8 dword_6[0x20]; 11476 u8 dword_7[0x20]; 11477 u8 dword_8[0x20]; 11478 u8 dword_9[0x20]; 11479 u8 dword_10[0x20]; 11480 u8 dword_11[0x20]; 11481 }; 11482 11483 struct mlx5_ifc_dcbx_param_bits { 11484 u8 dcbx_cee_cap[0x1]; 11485 u8 dcbx_ieee_cap[0x1]; 11486 u8 dcbx_standby_cap[0x1]; 11487 u8 reserved_at_3[0x5]; 11488 u8 port_number[0x8]; 11489 u8 reserved_at_10[0xa]; 11490 u8 max_application_table_size[6]; 11491 u8 reserved_at_20[0x15]; 11492 u8 version_oper[0x3]; 11493 u8 reserved_at_38[5]; 11494 u8 version_admin[0x3]; 11495 u8 willing_admin[0x1]; 11496 u8 reserved_at_41[0x3]; 11497 u8 pfc_cap_oper[0x4]; 11498 u8 reserved_at_48[0x4]; 11499 u8 pfc_cap_admin[0x4]; 11500 u8 reserved_at_50[0x4]; 11501 u8 num_of_tc_oper[0x4]; 11502 u8 reserved_at_58[0x4]; 11503 u8 num_of_tc_admin[0x4]; 11504 u8 remote_willing[0x1]; 11505 u8 reserved_at_61[3]; 11506 u8 remote_pfc_cap[4]; 11507 u8 reserved_at_68[0x14]; 11508 u8 remote_num_of_tc[0x4]; 11509 u8 reserved_at_80[0x18]; 11510 u8 error[0x8]; 11511 u8 reserved_at_a0[0x160]; 11512 }; 11513 11514 enum { 11515 MLX5_LAG_PORT_SELECT_MODE_QUEUE_AFFINITY = 0, 11516 MLX5_LAG_PORT_SELECT_MODE_PORT_SELECT_FT = 1, 11517 MLX5_LAG_PORT_SELECT_MODE_PORT_SELECT_MPESW = 2, 11518 }; 11519 11520 struct mlx5_ifc_lagc_bits { 11521 u8 fdb_selection_mode[0x1]; 11522 u8 reserved_at_1[0x14]; 11523 u8 port_select_mode[0x3]; 11524 u8 reserved_at_18[0x5]; 11525 u8 lag_state[0x3]; 11526 11527 u8 reserved_at_20[0xc]; 11528 u8 active_port[0x4]; 11529 u8 reserved_at_30[0x4]; 11530 u8 tx_remap_affinity_2[0x4]; 11531 u8 reserved_at_38[0x4]; 11532 u8 tx_remap_affinity_1[0x4]; 11533 }; 11534 11535 struct mlx5_ifc_create_lag_out_bits { 11536 u8 status[0x8]; 11537 u8 reserved_at_8[0x18]; 11538 11539 u8 syndrome[0x20]; 11540 11541 u8 reserved_at_40[0x40]; 11542 }; 11543 11544 struct mlx5_ifc_create_lag_in_bits { 11545 u8 opcode[0x10]; 11546 u8 reserved_at_10[0x10]; 11547 11548 u8 reserved_at_20[0x10]; 11549 u8 op_mod[0x10]; 11550 11551 struct mlx5_ifc_lagc_bits ctx; 11552 }; 11553 11554 struct mlx5_ifc_modify_lag_out_bits { 11555 u8 status[0x8]; 11556 u8 reserved_at_8[0x18]; 11557 11558 u8 syndrome[0x20]; 11559 11560 u8 reserved_at_40[0x40]; 11561 }; 11562 11563 struct mlx5_ifc_modify_lag_in_bits { 11564 u8 opcode[0x10]; 11565 u8 reserved_at_10[0x10]; 11566 11567 u8 reserved_at_20[0x10]; 11568 u8 op_mod[0x10]; 11569 11570 u8 reserved_at_40[0x20]; 11571 u8 field_select[0x20]; 11572 11573 struct mlx5_ifc_lagc_bits ctx; 11574 }; 11575 11576 struct mlx5_ifc_query_lag_out_bits { 11577 u8 status[0x8]; 11578 u8 reserved_at_8[0x18]; 11579 11580 u8 syndrome[0x20]; 11581 11582 struct mlx5_ifc_lagc_bits ctx; 11583 }; 11584 11585 struct mlx5_ifc_query_lag_in_bits { 11586 u8 opcode[0x10]; 11587 u8 reserved_at_10[0x10]; 11588 11589 u8 reserved_at_20[0x10]; 11590 u8 op_mod[0x10]; 11591 11592 u8 reserved_at_40[0x40]; 11593 }; 11594 11595 struct mlx5_ifc_destroy_lag_out_bits { 11596 u8 status[0x8]; 11597 u8 reserved_at_8[0x18]; 11598 11599 u8 syndrome[0x20]; 11600 11601 u8 reserved_at_40[0x40]; 11602 }; 11603 11604 struct mlx5_ifc_destroy_lag_in_bits { 11605 u8 opcode[0x10]; 11606 u8 reserved_at_10[0x10]; 11607 11608 u8 reserved_at_20[0x10]; 11609 u8 op_mod[0x10]; 11610 11611 u8 reserved_at_40[0x40]; 11612 }; 11613 11614 struct mlx5_ifc_create_vport_lag_out_bits { 11615 u8 status[0x8]; 11616 u8 reserved_at_8[0x18]; 11617 11618 u8 syndrome[0x20]; 11619 11620 u8 reserved_at_40[0x40]; 11621 }; 11622 11623 struct mlx5_ifc_create_vport_lag_in_bits { 11624 u8 opcode[0x10]; 11625 u8 reserved_at_10[0x10]; 11626 11627 u8 reserved_at_20[0x10]; 11628 u8 op_mod[0x10]; 11629 11630 u8 reserved_at_40[0x40]; 11631 }; 11632 11633 struct mlx5_ifc_destroy_vport_lag_out_bits { 11634 u8 status[0x8]; 11635 u8 reserved_at_8[0x18]; 11636 11637 u8 syndrome[0x20]; 11638 11639 u8 reserved_at_40[0x40]; 11640 }; 11641 11642 struct mlx5_ifc_destroy_vport_lag_in_bits { 11643 u8 opcode[0x10]; 11644 u8 reserved_at_10[0x10]; 11645 11646 u8 reserved_at_20[0x10]; 11647 u8 op_mod[0x10]; 11648 11649 u8 reserved_at_40[0x40]; 11650 }; 11651 11652 enum { 11653 MLX5_MODIFY_MEMIC_OP_MOD_ALLOC, 11654 MLX5_MODIFY_MEMIC_OP_MOD_DEALLOC, 11655 }; 11656 11657 struct mlx5_ifc_modify_memic_in_bits { 11658 u8 opcode[0x10]; 11659 u8 uid[0x10]; 11660 11661 u8 reserved_at_20[0x10]; 11662 u8 op_mod[0x10]; 11663 11664 u8 reserved_at_40[0x20]; 11665 11666 u8 reserved_at_60[0x18]; 11667 u8 memic_operation_type[0x8]; 11668 11669 u8 memic_start_addr[0x40]; 11670 11671 u8 reserved_at_c0[0x140]; 11672 }; 11673 11674 struct mlx5_ifc_modify_memic_out_bits { 11675 u8 status[0x8]; 11676 u8 reserved_at_8[0x18]; 11677 11678 u8 syndrome[0x20]; 11679 11680 u8 reserved_at_40[0x40]; 11681 11682 u8 memic_operation_addr[0x40]; 11683 11684 u8 reserved_at_c0[0x140]; 11685 }; 11686 11687 struct mlx5_ifc_alloc_memic_in_bits { 11688 u8 opcode[0x10]; 11689 u8 reserved_at_10[0x10]; 11690 11691 u8 reserved_at_20[0x10]; 11692 u8 op_mod[0x10]; 11693 11694 u8 reserved_at_30[0x20]; 11695 11696 u8 reserved_at_40[0x18]; 11697 u8 log_memic_addr_alignment[0x8]; 11698 11699 u8 range_start_addr[0x40]; 11700 11701 u8 range_size[0x20]; 11702 11703 u8 memic_size[0x20]; 11704 }; 11705 11706 struct mlx5_ifc_alloc_memic_out_bits { 11707 u8 status[0x8]; 11708 u8 reserved_at_8[0x18]; 11709 11710 u8 syndrome[0x20]; 11711 11712 u8 memic_start_addr[0x40]; 11713 }; 11714 11715 struct mlx5_ifc_dealloc_memic_in_bits { 11716 u8 opcode[0x10]; 11717 u8 reserved_at_10[0x10]; 11718 11719 u8 reserved_at_20[0x10]; 11720 u8 op_mod[0x10]; 11721 11722 u8 reserved_at_40[0x40]; 11723 11724 u8 memic_start_addr[0x40]; 11725 11726 u8 memic_size[0x20]; 11727 11728 u8 reserved_at_e0[0x20]; 11729 }; 11730 11731 struct mlx5_ifc_dealloc_memic_out_bits { 11732 u8 status[0x8]; 11733 u8 reserved_at_8[0x18]; 11734 11735 u8 syndrome[0x20]; 11736 11737 u8 reserved_at_40[0x40]; 11738 }; 11739 11740 struct mlx5_ifc_umem_bits { 11741 u8 reserved_at_0[0x80]; 11742 11743 u8 ats[0x1]; 11744 u8 reserved_at_81[0x1a]; 11745 u8 log_page_size[0x5]; 11746 11747 u8 page_offset[0x20]; 11748 11749 u8 num_of_mtt[0x40]; 11750 11751 struct mlx5_ifc_mtt_bits mtt[]; 11752 }; 11753 11754 struct mlx5_ifc_uctx_bits { 11755 u8 cap[0x20]; 11756 11757 u8 reserved_at_20[0x160]; 11758 }; 11759 11760 struct mlx5_ifc_sw_icm_bits { 11761 u8 modify_field_select[0x40]; 11762 11763 u8 reserved_at_40[0x18]; 11764 u8 log_sw_icm_size[0x8]; 11765 11766 u8 reserved_at_60[0x20]; 11767 11768 u8 sw_icm_start_addr[0x40]; 11769 11770 u8 reserved_at_c0[0x140]; 11771 }; 11772 11773 struct mlx5_ifc_geneve_tlv_option_bits { 11774 u8 modify_field_select[0x40]; 11775 11776 u8 reserved_at_40[0x18]; 11777 u8 geneve_option_fte_index[0x8]; 11778 11779 u8 option_class[0x10]; 11780 u8 option_type[0x8]; 11781 u8 reserved_at_78[0x3]; 11782 u8 option_data_length[0x5]; 11783 11784 u8 reserved_at_80[0x180]; 11785 }; 11786 11787 struct mlx5_ifc_create_umem_in_bits { 11788 u8 opcode[0x10]; 11789 u8 uid[0x10]; 11790 11791 u8 reserved_at_20[0x10]; 11792 u8 op_mod[0x10]; 11793 11794 u8 reserved_at_40[0x40]; 11795 11796 struct mlx5_ifc_umem_bits umem; 11797 }; 11798 11799 struct mlx5_ifc_create_umem_out_bits { 11800 u8 status[0x8]; 11801 u8 reserved_at_8[0x18]; 11802 11803 u8 syndrome[0x20]; 11804 11805 u8 reserved_at_40[0x8]; 11806 u8 umem_id[0x18]; 11807 11808 u8 reserved_at_60[0x20]; 11809 }; 11810 11811 struct mlx5_ifc_destroy_umem_in_bits { 11812 u8 opcode[0x10]; 11813 u8 uid[0x10]; 11814 11815 u8 reserved_at_20[0x10]; 11816 u8 op_mod[0x10]; 11817 11818 u8 reserved_at_40[0x8]; 11819 u8 umem_id[0x18]; 11820 11821 u8 reserved_at_60[0x20]; 11822 }; 11823 11824 struct mlx5_ifc_destroy_umem_out_bits { 11825 u8 status[0x8]; 11826 u8 reserved_at_8[0x18]; 11827 11828 u8 syndrome[0x20]; 11829 11830 u8 reserved_at_40[0x40]; 11831 }; 11832 11833 struct mlx5_ifc_create_uctx_in_bits { 11834 u8 opcode[0x10]; 11835 u8 reserved_at_10[0x10]; 11836 11837 u8 reserved_at_20[0x10]; 11838 u8 op_mod[0x10]; 11839 11840 u8 reserved_at_40[0x40]; 11841 11842 struct mlx5_ifc_uctx_bits uctx; 11843 }; 11844 11845 struct mlx5_ifc_create_uctx_out_bits { 11846 u8 status[0x8]; 11847 u8 reserved_at_8[0x18]; 11848 11849 u8 syndrome[0x20]; 11850 11851 u8 reserved_at_40[0x10]; 11852 u8 uid[0x10]; 11853 11854 u8 reserved_at_60[0x20]; 11855 }; 11856 11857 struct mlx5_ifc_destroy_uctx_in_bits { 11858 u8 opcode[0x10]; 11859 u8 reserved_at_10[0x10]; 11860 11861 u8 reserved_at_20[0x10]; 11862 u8 op_mod[0x10]; 11863 11864 u8 reserved_at_40[0x10]; 11865 u8 uid[0x10]; 11866 11867 u8 reserved_at_60[0x20]; 11868 }; 11869 11870 struct mlx5_ifc_destroy_uctx_out_bits { 11871 u8 status[0x8]; 11872 u8 reserved_at_8[0x18]; 11873 11874 u8 syndrome[0x20]; 11875 11876 u8 reserved_at_40[0x40]; 11877 }; 11878 11879 struct mlx5_ifc_create_sw_icm_in_bits { 11880 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 11881 struct mlx5_ifc_sw_icm_bits sw_icm; 11882 }; 11883 11884 struct mlx5_ifc_create_geneve_tlv_option_in_bits { 11885 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 11886 struct mlx5_ifc_geneve_tlv_option_bits geneve_tlv_opt; 11887 }; 11888 11889 struct mlx5_ifc_mtrc_string_db_param_bits { 11890 u8 string_db_base_address[0x20]; 11891 11892 u8 reserved_at_20[0x8]; 11893 u8 string_db_size[0x18]; 11894 }; 11895 11896 struct mlx5_ifc_mtrc_cap_bits { 11897 u8 trace_owner[0x1]; 11898 u8 trace_to_memory[0x1]; 11899 u8 reserved_at_2[0x4]; 11900 u8 trc_ver[0x2]; 11901 u8 reserved_at_8[0x14]; 11902 u8 num_string_db[0x4]; 11903 11904 u8 first_string_trace[0x8]; 11905 u8 num_string_trace[0x8]; 11906 u8 reserved_at_30[0x28]; 11907 11908 u8 log_max_trace_buffer_size[0x8]; 11909 11910 u8 reserved_at_60[0x20]; 11911 11912 struct mlx5_ifc_mtrc_string_db_param_bits string_db_param[8]; 11913 11914 u8 reserved_at_280[0x180]; 11915 }; 11916 11917 struct mlx5_ifc_mtrc_conf_bits { 11918 u8 reserved_at_0[0x1c]; 11919 u8 trace_mode[0x4]; 11920 u8 reserved_at_20[0x18]; 11921 u8 log_trace_buffer_size[0x8]; 11922 u8 trace_mkey[0x20]; 11923 u8 reserved_at_60[0x3a0]; 11924 }; 11925 11926 struct mlx5_ifc_mtrc_stdb_bits { 11927 u8 string_db_index[0x4]; 11928 u8 reserved_at_4[0x4]; 11929 u8 read_size[0x18]; 11930 u8 start_offset[0x20]; 11931 u8 string_db_data[]; 11932 }; 11933 11934 struct mlx5_ifc_mtrc_ctrl_bits { 11935 u8 trace_status[0x2]; 11936 u8 reserved_at_2[0x2]; 11937 u8 arm_event[0x1]; 11938 u8 reserved_at_5[0xb]; 11939 u8 modify_field_select[0x10]; 11940 u8 reserved_at_20[0x2b]; 11941 u8 current_timestamp52_32[0x15]; 11942 u8 current_timestamp31_0[0x20]; 11943 u8 reserved_at_80[0x180]; 11944 }; 11945 11946 struct mlx5_ifc_host_params_context_bits { 11947 u8 host_number[0x8]; 11948 u8 reserved_at_8[0x7]; 11949 u8 host_pf_disabled[0x1]; 11950 u8 host_num_of_vfs[0x10]; 11951 11952 u8 host_total_vfs[0x10]; 11953 u8 host_pci_bus[0x10]; 11954 11955 u8 reserved_at_40[0x10]; 11956 u8 host_pci_device[0x10]; 11957 11958 u8 reserved_at_60[0x10]; 11959 u8 host_pci_function[0x10]; 11960 11961 u8 reserved_at_80[0x180]; 11962 }; 11963 11964 struct mlx5_ifc_query_esw_functions_in_bits { 11965 u8 opcode[0x10]; 11966 u8 reserved_at_10[0x10]; 11967 11968 u8 reserved_at_20[0x10]; 11969 u8 op_mod[0x10]; 11970 11971 u8 reserved_at_40[0x40]; 11972 }; 11973 11974 struct mlx5_ifc_query_esw_functions_out_bits { 11975 u8 status[0x8]; 11976 u8 reserved_at_8[0x18]; 11977 11978 u8 syndrome[0x20]; 11979 11980 u8 reserved_at_40[0x40]; 11981 11982 struct mlx5_ifc_host_params_context_bits host_params_context; 11983 11984 u8 reserved_at_280[0x180]; 11985 u8 host_sf_enable[][0x40]; 11986 }; 11987 11988 struct mlx5_ifc_sf_partition_bits { 11989 u8 reserved_at_0[0x10]; 11990 u8 log_num_sf[0x8]; 11991 u8 log_sf_bar_size[0x8]; 11992 }; 11993 11994 struct mlx5_ifc_query_sf_partitions_out_bits { 11995 u8 status[0x8]; 11996 u8 reserved_at_8[0x18]; 11997 11998 u8 syndrome[0x20]; 11999 12000 u8 reserved_at_40[0x18]; 12001 u8 num_sf_partitions[0x8]; 12002 12003 u8 reserved_at_60[0x20]; 12004 12005 struct mlx5_ifc_sf_partition_bits sf_partition[]; 12006 }; 12007 12008 struct mlx5_ifc_query_sf_partitions_in_bits { 12009 u8 opcode[0x10]; 12010 u8 reserved_at_10[0x10]; 12011 12012 u8 reserved_at_20[0x10]; 12013 u8 op_mod[0x10]; 12014 12015 u8 reserved_at_40[0x40]; 12016 }; 12017 12018 struct mlx5_ifc_dealloc_sf_out_bits { 12019 u8 status[0x8]; 12020 u8 reserved_at_8[0x18]; 12021 12022 u8 syndrome[0x20]; 12023 12024 u8 reserved_at_40[0x40]; 12025 }; 12026 12027 struct mlx5_ifc_dealloc_sf_in_bits { 12028 u8 opcode[0x10]; 12029 u8 reserved_at_10[0x10]; 12030 12031 u8 reserved_at_20[0x10]; 12032 u8 op_mod[0x10]; 12033 12034 u8 reserved_at_40[0x10]; 12035 u8 function_id[0x10]; 12036 12037 u8 reserved_at_60[0x20]; 12038 }; 12039 12040 struct mlx5_ifc_alloc_sf_out_bits { 12041 u8 status[0x8]; 12042 u8 reserved_at_8[0x18]; 12043 12044 u8 syndrome[0x20]; 12045 12046 u8 reserved_at_40[0x40]; 12047 }; 12048 12049 struct mlx5_ifc_alloc_sf_in_bits { 12050 u8 opcode[0x10]; 12051 u8 reserved_at_10[0x10]; 12052 12053 u8 reserved_at_20[0x10]; 12054 u8 op_mod[0x10]; 12055 12056 u8 reserved_at_40[0x10]; 12057 u8 function_id[0x10]; 12058 12059 u8 reserved_at_60[0x20]; 12060 }; 12061 12062 struct mlx5_ifc_affiliated_event_header_bits { 12063 u8 reserved_at_0[0x10]; 12064 u8 obj_type[0x10]; 12065 12066 u8 obj_id[0x20]; 12067 }; 12068 12069 enum { 12070 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = BIT_ULL(0xc), 12071 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_IPSEC = BIT_ULL(0x13), 12072 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_SAMPLER = BIT_ULL(0x20), 12073 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_FLOW_METER_ASO = BIT_ULL(0x24), 12074 }; 12075 12076 enum { 12077 MLX5_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = 0xc, 12078 MLX5_GENERAL_OBJECT_TYPES_IPSEC = 0x13, 12079 MLX5_GENERAL_OBJECT_TYPES_SAMPLER = 0x20, 12080 MLX5_GENERAL_OBJECT_TYPES_FLOW_METER_ASO = 0x24, 12081 MLX5_GENERAL_OBJECT_TYPES_MACSEC = 0x27, 12082 MLX5_GENERAL_OBJECT_TYPES_INT_KEK = 0x47, 12083 MLX5_GENERAL_OBJECT_TYPES_FLOW_TABLE_ALIAS = 0xff15, 12084 }; 12085 12086 enum { 12087 MLX5_IPSEC_OBJECT_ICV_LEN_16B, 12088 }; 12089 12090 enum { 12091 MLX5_IPSEC_ASO_REG_C_0_1 = 0x0, 12092 MLX5_IPSEC_ASO_REG_C_2_3 = 0x1, 12093 MLX5_IPSEC_ASO_REG_C_4_5 = 0x2, 12094 MLX5_IPSEC_ASO_REG_C_6_7 = 0x3, 12095 }; 12096 12097 enum { 12098 MLX5_IPSEC_ASO_MODE = 0x0, 12099 MLX5_IPSEC_ASO_REPLAY_PROTECTION = 0x1, 12100 MLX5_IPSEC_ASO_INC_SN = 0x2, 12101 }; 12102 12103 enum { 12104 MLX5_IPSEC_ASO_REPLAY_WIN_32BIT = 0x0, 12105 MLX5_IPSEC_ASO_REPLAY_WIN_64BIT = 0x1, 12106 MLX5_IPSEC_ASO_REPLAY_WIN_128BIT = 0x2, 12107 MLX5_IPSEC_ASO_REPLAY_WIN_256BIT = 0x3, 12108 }; 12109 12110 struct mlx5_ifc_ipsec_aso_bits { 12111 u8 valid[0x1]; 12112 u8 reserved_at_201[0x1]; 12113 u8 mode[0x2]; 12114 u8 window_sz[0x2]; 12115 u8 soft_lft_arm[0x1]; 12116 u8 hard_lft_arm[0x1]; 12117 u8 remove_flow_enable[0x1]; 12118 u8 esn_event_arm[0x1]; 12119 u8 reserved_at_20a[0x16]; 12120 12121 u8 remove_flow_pkt_cnt[0x20]; 12122 12123 u8 remove_flow_soft_lft[0x20]; 12124 12125 u8 reserved_at_260[0x80]; 12126 12127 u8 mode_parameter[0x20]; 12128 12129 u8 replay_protection_window[0x100]; 12130 }; 12131 12132 struct mlx5_ifc_ipsec_obj_bits { 12133 u8 modify_field_select[0x40]; 12134 u8 full_offload[0x1]; 12135 u8 reserved_at_41[0x1]; 12136 u8 esn_en[0x1]; 12137 u8 esn_overlap[0x1]; 12138 u8 reserved_at_44[0x2]; 12139 u8 icv_length[0x2]; 12140 u8 reserved_at_48[0x4]; 12141 u8 aso_return_reg[0x4]; 12142 u8 reserved_at_50[0x10]; 12143 12144 u8 esn_msb[0x20]; 12145 12146 u8 reserved_at_80[0x8]; 12147 u8 dekn[0x18]; 12148 12149 u8 salt[0x20]; 12150 12151 u8 implicit_iv[0x40]; 12152 12153 u8 reserved_at_100[0x8]; 12154 u8 ipsec_aso_access_pd[0x18]; 12155 u8 reserved_at_120[0xe0]; 12156 12157 struct mlx5_ifc_ipsec_aso_bits ipsec_aso; 12158 }; 12159 12160 struct mlx5_ifc_create_ipsec_obj_in_bits { 12161 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12162 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 12163 }; 12164 12165 enum { 12166 MLX5_MODIFY_IPSEC_BITMASK_ESN_OVERLAP = BIT(0), 12167 MLX5_MODIFY_IPSEC_BITMASK_ESN_MSB = BIT(1), 12168 }; 12169 12170 struct mlx5_ifc_query_ipsec_obj_out_bits { 12171 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 12172 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 12173 }; 12174 12175 struct mlx5_ifc_modify_ipsec_obj_in_bits { 12176 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12177 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 12178 }; 12179 12180 enum { 12181 MLX5_MACSEC_ASO_REPLAY_PROTECTION = 0x1, 12182 }; 12183 12184 enum { 12185 MLX5_MACSEC_ASO_REPLAY_WIN_32BIT = 0x0, 12186 MLX5_MACSEC_ASO_REPLAY_WIN_64BIT = 0x1, 12187 MLX5_MACSEC_ASO_REPLAY_WIN_128BIT = 0x2, 12188 MLX5_MACSEC_ASO_REPLAY_WIN_256BIT = 0x3, 12189 }; 12190 12191 #define MLX5_MACSEC_ASO_INC_SN 0x2 12192 #define MLX5_MACSEC_ASO_REG_C_4_5 0x2 12193 12194 struct mlx5_ifc_macsec_aso_bits { 12195 u8 valid[0x1]; 12196 u8 reserved_at_1[0x1]; 12197 u8 mode[0x2]; 12198 u8 window_size[0x2]; 12199 u8 soft_lifetime_arm[0x1]; 12200 u8 hard_lifetime_arm[0x1]; 12201 u8 remove_flow_enable[0x1]; 12202 u8 epn_event_arm[0x1]; 12203 u8 reserved_at_a[0x16]; 12204 12205 u8 remove_flow_packet_count[0x20]; 12206 12207 u8 remove_flow_soft_lifetime[0x20]; 12208 12209 u8 reserved_at_60[0x80]; 12210 12211 u8 mode_parameter[0x20]; 12212 12213 u8 replay_protection_window[8][0x20]; 12214 }; 12215 12216 struct mlx5_ifc_macsec_offload_obj_bits { 12217 u8 modify_field_select[0x40]; 12218 12219 u8 confidentiality_en[0x1]; 12220 u8 reserved_at_41[0x1]; 12221 u8 epn_en[0x1]; 12222 u8 epn_overlap[0x1]; 12223 u8 reserved_at_44[0x2]; 12224 u8 confidentiality_offset[0x2]; 12225 u8 reserved_at_48[0x4]; 12226 u8 aso_return_reg[0x4]; 12227 u8 reserved_at_50[0x10]; 12228 12229 u8 epn_msb[0x20]; 12230 12231 u8 reserved_at_80[0x8]; 12232 u8 dekn[0x18]; 12233 12234 u8 reserved_at_a0[0x20]; 12235 12236 u8 sci[0x40]; 12237 12238 u8 reserved_at_100[0x8]; 12239 u8 macsec_aso_access_pd[0x18]; 12240 12241 u8 reserved_at_120[0x60]; 12242 12243 u8 salt[3][0x20]; 12244 12245 u8 reserved_at_1e0[0x20]; 12246 12247 struct mlx5_ifc_macsec_aso_bits macsec_aso; 12248 }; 12249 12250 struct mlx5_ifc_create_macsec_obj_in_bits { 12251 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12252 struct mlx5_ifc_macsec_offload_obj_bits macsec_object; 12253 }; 12254 12255 struct mlx5_ifc_modify_macsec_obj_in_bits { 12256 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12257 struct mlx5_ifc_macsec_offload_obj_bits macsec_object; 12258 }; 12259 12260 enum { 12261 MLX5_MODIFY_MACSEC_BITMASK_EPN_OVERLAP = BIT(0), 12262 MLX5_MODIFY_MACSEC_BITMASK_EPN_MSB = BIT(1), 12263 }; 12264 12265 struct mlx5_ifc_query_macsec_obj_out_bits { 12266 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 12267 struct mlx5_ifc_macsec_offload_obj_bits macsec_object; 12268 }; 12269 12270 struct mlx5_ifc_wrapped_dek_bits { 12271 u8 gcm_iv[0x60]; 12272 12273 u8 reserved_at_60[0x20]; 12274 12275 u8 const0[0x1]; 12276 u8 key_size[0x1]; 12277 u8 reserved_at_82[0x2]; 12278 u8 key2_invalid[0x1]; 12279 u8 reserved_at_85[0x3]; 12280 u8 pd[0x18]; 12281 12282 u8 key_purpose[0x5]; 12283 u8 reserved_at_a5[0x13]; 12284 u8 kek_id[0x8]; 12285 12286 u8 reserved_at_c0[0x40]; 12287 12288 u8 key1[0x8][0x20]; 12289 12290 u8 key2[0x8][0x20]; 12291 12292 u8 reserved_at_300[0x40]; 12293 12294 u8 const1[0x1]; 12295 u8 reserved_at_341[0x1f]; 12296 12297 u8 reserved_at_360[0x20]; 12298 12299 u8 auth_tag[0x80]; 12300 }; 12301 12302 struct mlx5_ifc_encryption_key_obj_bits { 12303 u8 modify_field_select[0x40]; 12304 12305 u8 state[0x8]; 12306 u8 sw_wrapped[0x1]; 12307 u8 reserved_at_49[0xb]; 12308 u8 key_size[0x4]; 12309 u8 reserved_at_58[0x4]; 12310 u8 key_purpose[0x4]; 12311 12312 u8 reserved_at_60[0x8]; 12313 u8 pd[0x18]; 12314 12315 u8 reserved_at_80[0x100]; 12316 12317 u8 opaque[0x40]; 12318 12319 u8 reserved_at_1c0[0x40]; 12320 12321 u8 key[8][0x80]; 12322 12323 u8 sw_wrapped_dek[8][0x80]; 12324 12325 u8 reserved_at_a00[0x600]; 12326 }; 12327 12328 struct mlx5_ifc_create_encryption_key_in_bits { 12329 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12330 struct mlx5_ifc_encryption_key_obj_bits encryption_key_object; 12331 }; 12332 12333 struct mlx5_ifc_modify_encryption_key_in_bits { 12334 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12335 struct mlx5_ifc_encryption_key_obj_bits encryption_key_object; 12336 }; 12337 12338 enum { 12339 MLX5_FLOW_METER_MODE_BYTES_IP_LENGTH = 0x0, 12340 MLX5_FLOW_METER_MODE_BYTES_CALC_WITH_L2 = 0x1, 12341 MLX5_FLOW_METER_MODE_BYTES_CALC_WITH_L2_IPG = 0x2, 12342 MLX5_FLOW_METER_MODE_NUM_PACKETS = 0x3, 12343 }; 12344 12345 struct mlx5_ifc_flow_meter_parameters_bits { 12346 u8 valid[0x1]; 12347 u8 bucket_overflow[0x1]; 12348 u8 start_color[0x2]; 12349 u8 both_buckets_on_green[0x1]; 12350 u8 reserved_at_5[0x1]; 12351 u8 meter_mode[0x2]; 12352 u8 reserved_at_8[0x18]; 12353 12354 u8 reserved_at_20[0x20]; 12355 12356 u8 reserved_at_40[0x3]; 12357 u8 cbs_exponent[0x5]; 12358 u8 cbs_mantissa[0x8]; 12359 u8 reserved_at_50[0x3]; 12360 u8 cir_exponent[0x5]; 12361 u8 cir_mantissa[0x8]; 12362 12363 u8 reserved_at_60[0x20]; 12364 12365 u8 reserved_at_80[0x3]; 12366 u8 ebs_exponent[0x5]; 12367 u8 ebs_mantissa[0x8]; 12368 u8 reserved_at_90[0x3]; 12369 u8 eir_exponent[0x5]; 12370 u8 eir_mantissa[0x8]; 12371 12372 u8 reserved_at_a0[0x60]; 12373 }; 12374 12375 struct mlx5_ifc_flow_meter_aso_obj_bits { 12376 u8 modify_field_select[0x40]; 12377 12378 u8 reserved_at_40[0x40]; 12379 12380 u8 reserved_at_80[0x8]; 12381 u8 meter_aso_access_pd[0x18]; 12382 12383 u8 reserved_at_a0[0x160]; 12384 12385 struct mlx5_ifc_flow_meter_parameters_bits flow_meter_parameters[2]; 12386 }; 12387 12388 struct mlx5_ifc_create_flow_meter_aso_obj_in_bits { 12389 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 12390 struct mlx5_ifc_flow_meter_aso_obj_bits flow_meter_aso_obj; 12391 }; 12392 12393 struct mlx5_ifc_int_kek_obj_bits { 12394 u8 modify_field_select[0x40]; 12395 12396 u8 state[0x8]; 12397 u8 auto_gen[0x1]; 12398 u8 reserved_at_49[0xb]; 12399 u8 key_size[0x4]; 12400 u8 reserved_at_58[0x8]; 12401 12402 u8 reserved_at_60[0x8]; 12403 u8 pd[0x18]; 12404 12405 u8 reserved_at_80[0x180]; 12406 u8 key[8][0x80]; 12407 12408 u8 reserved_at_600[0x200]; 12409 }; 12410 12411 struct mlx5_ifc_create_int_kek_obj_in_bits { 12412 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12413 struct mlx5_ifc_int_kek_obj_bits int_kek_object; 12414 }; 12415 12416 struct mlx5_ifc_create_int_kek_obj_out_bits { 12417 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 12418 struct mlx5_ifc_int_kek_obj_bits int_kek_object; 12419 }; 12420 12421 struct mlx5_ifc_sampler_obj_bits { 12422 u8 modify_field_select[0x40]; 12423 12424 u8 table_type[0x8]; 12425 u8 level[0x8]; 12426 u8 reserved_at_50[0xf]; 12427 u8 ignore_flow_level[0x1]; 12428 12429 u8 sample_ratio[0x20]; 12430 12431 u8 reserved_at_80[0x8]; 12432 u8 sample_table_id[0x18]; 12433 12434 u8 reserved_at_a0[0x8]; 12435 u8 default_table_id[0x18]; 12436 12437 u8 sw_steering_icm_address_rx[0x40]; 12438 u8 sw_steering_icm_address_tx[0x40]; 12439 12440 u8 reserved_at_140[0xa0]; 12441 }; 12442 12443 struct mlx5_ifc_create_sampler_obj_in_bits { 12444 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12445 struct mlx5_ifc_sampler_obj_bits sampler_object; 12446 }; 12447 12448 struct mlx5_ifc_query_sampler_obj_out_bits { 12449 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 12450 struct mlx5_ifc_sampler_obj_bits sampler_object; 12451 }; 12452 12453 enum { 12454 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_128 = 0x0, 12455 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_256 = 0x1, 12456 }; 12457 12458 enum { 12459 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_PURPOSE_TLS = 0x1, 12460 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_PURPOSE_IPSEC = 0x2, 12461 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_PURPOSE_MACSEC = 0x4, 12462 }; 12463 12464 struct mlx5_ifc_tls_static_params_bits { 12465 u8 const_2[0x2]; 12466 u8 tls_version[0x4]; 12467 u8 const_1[0x2]; 12468 u8 reserved_at_8[0x14]; 12469 u8 encryption_standard[0x4]; 12470 12471 u8 reserved_at_20[0x20]; 12472 12473 u8 initial_record_number[0x40]; 12474 12475 u8 resync_tcp_sn[0x20]; 12476 12477 u8 gcm_iv[0x20]; 12478 12479 u8 implicit_iv[0x40]; 12480 12481 u8 reserved_at_100[0x8]; 12482 u8 dek_index[0x18]; 12483 12484 u8 reserved_at_120[0xe0]; 12485 }; 12486 12487 struct mlx5_ifc_tls_progress_params_bits { 12488 u8 next_record_tcp_sn[0x20]; 12489 12490 u8 hw_resync_tcp_sn[0x20]; 12491 12492 u8 record_tracker_state[0x2]; 12493 u8 auth_state[0x2]; 12494 u8 reserved_at_44[0x4]; 12495 u8 hw_offset_record_number[0x18]; 12496 }; 12497 12498 enum { 12499 MLX5_MTT_PERM_READ = 1 << 0, 12500 MLX5_MTT_PERM_WRITE = 1 << 1, 12501 MLX5_MTT_PERM_RW = MLX5_MTT_PERM_READ | MLX5_MTT_PERM_WRITE, 12502 }; 12503 12504 enum { 12505 MLX5_SUSPEND_VHCA_IN_OP_MOD_SUSPEND_INITIATOR = 0x0, 12506 MLX5_SUSPEND_VHCA_IN_OP_MOD_SUSPEND_RESPONDER = 0x1, 12507 }; 12508 12509 struct mlx5_ifc_suspend_vhca_in_bits { 12510 u8 opcode[0x10]; 12511 u8 uid[0x10]; 12512 12513 u8 reserved_at_20[0x10]; 12514 u8 op_mod[0x10]; 12515 12516 u8 reserved_at_40[0x10]; 12517 u8 vhca_id[0x10]; 12518 12519 u8 reserved_at_60[0x20]; 12520 }; 12521 12522 struct mlx5_ifc_suspend_vhca_out_bits { 12523 u8 status[0x8]; 12524 u8 reserved_at_8[0x18]; 12525 12526 u8 syndrome[0x20]; 12527 12528 u8 reserved_at_40[0x40]; 12529 }; 12530 12531 enum { 12532 MLX5_RESUME_VHCA_IN_OP_MOD_RESUME_RESPONDER = 0x0, 12533 MLX5_RESUME_VHCA_IN_OP_MOD_RESUME_INITIATOR = 0x1, 12534 }; 12535 12536 struct mlx5_ifc_resume_vhca_in_bits { 12537 u8 opcode[0x10]; 12538 u8 uid[0x10]; 12539 12540 u8 reserved_at_20[0x10]; 12541 u8 op_mod[0x10]; 12542 12543 u8 reserved_at_40[0x10]; 12544 u8 vhca_id[0x10]; 12545 12546 u8 reserved_at_60[0x20]; 12547 }; 12548 12549 struct mlx5_ifc_resume_vhca_out_bits { 12550 u8 status[0x8]; 12551 u8 reserved_at_8[0x18]; 12552 12553 u8 syndrome[0x20]; 12554 12555 u8 reserved_at_40[0x40]; 12556 }; 12557 12558 struct mlx5_ifc_query_vhca_migration_state_in_bits { 12559 u8 opcode[0x10]; 12560 u8 uid[0x10]; 12561 12562 u8 reserved_at_20[0x10]; 12563 u8 op_mod[0x10]; 12564 12565 u8 incremental[0x1]; 12566 u8 chunk[0x1]; 12567 u8 reserved_at_42[0xe]; 12568 u8 vhca_id[0x10]; 12569 12570 u8 reserved_at_60[0x20]; 12571 }; 12572 12573 struct mlx5_ifc_query_vhca_migration_state_out_bits { 12574 u8 status[0x8]; 12575 u8 reserved_at_8[0x18]; 12576 12577 u8 syndrome[0x20]; 12578 12579 u8 reserved_at_40[0x40]; 12580 12581 u8 required_umem_size[0x20]; 12582 12583 u8 reserved_at_a0[0x20]; 12584 12585 u8 remaining_total_size[0x40]; 12586 12587 u8 reserved_at_100[0x100]; 12588 }; 12589 12590 struct mlx5_ifc_save_vhca_state_in_bits { 12591 u8 opcode[0x10]; 12592 u8 uid[0x10]; 12593 12594 u8 reserved_at_20[0x10]; 12595 u8 op_mod[0x10]; 12596 12597 u8 incremental[0x1]; 12598 u8 set_track[0x1]; 12599 u8 reserved_at_42[0xe]; 12600 u8 vhca_id[0x10]; 12601 12602 u8 reserved_at_60[0x20]; 12603 12604 u8 va[0x40]; 12605 12606 u8 mkey[0x20]; 12607 12608 u8 size[0x20]; 12609 }; 12610 12611 struct mlx5_ifc_save_vhca_state_out_bits { 12612 u8 status[0x8]; 12613 u8 reserved_at_8[0x18]; 12614 12615 u8 syndrome[0x20]; 12616 12617 u8 actual_image_size[0x20]; 12618 12619 u8 next_required_umem_size[0x20]; 12620 }; 12621 12622 struct mlx5_ifc_load_vhca_state_in_bits { 12623 u8 opcode[0x10]; 12624 u8 uid[0x10]; 12625 12626 u8 reserved_at_20[0x10]; 12627 u8 op_mod[0x10]; 12628 12629 u8 reserved_at_40[0x10]; 12630 u8 vhca_id[0x10]; 12631 12632 u8 reserved_at_60[0x20]; 12633 12634 u8 va[0x40]; 12635 12636 u8 mkey[0x20]; 12637 12638 u8 size[0x20]; 12639 }; 12640 12641 struct mlx5_ifc_load_vhca_state_out_bits { 12642 u8 status[0x8]; 12643 u8 reserved_at_8[0x18]; 12644 12645 u8 syndrome[0x20]; 12646 12647 u8 reserved_at_40[0x40]; 12648 }; 12649 12650 struct mlx5_ifc_adv_virtualization_cap_bits { 12651 u8 reserved_at_0[0x3]; 12652 u8 pg_track_log_max_num[0x5]; 12653 u8 pg_track_max_num_range[0x8]; 12654 u8 pg_track_log_min_addr_space[0x8]; 12655 u8 pg_track_log_max_addr_space[0x8]; 12656 12657 u8 reserved_at_20[0x3]; 12658 u8 pg_track_log_min_msg_size[0x5]; 12659 u8 reserved_at_28[0x3]; 12660 u8 pg_track_log_max_msg_size[0x5]; 12661 u8 reserved_at_30[0x3]; 12662 u8 pg_track_log_min_page_size[0x5]; 12663 u8 reserved_at_38[0x3]; 12664 u8 pg_track_log_max_page_size[0x5]; 12665 12666 u8 reserved_at_40[0x7c0]; 12667 }; 12668 12669 struct mlx5_ifc_page_track_report_entry_bits { 12670 u8 dirty_address_high[0x20]; 12671 12672 u8 dirty_address_low[0x20]; 12673 }; 12674 12675 enum { 12676 MLX5_PAGE_TRACK_STATE_TRACKING, 12677 MLX5_PAGE_TRACK_STATE_REPORTING, 12678 MLX5_PAGE_TRACK_STATE_ERROR, 12679 }; 12680 12681 struct mlx5_ifc_page_track_range_bits { 12682 u8 start_address[0x40]; 12683 12684 u8 length[0x40]; 12685 }; 12686 12687 struct mlx5_ifc_page_track_bits { 12688 u8 modify_field_select[0x40]; 12689 12690 u8 reserved_at_40[0x10]; 12691 u8 vhca_id[0x10]; 12692 12693 u8 reserved_at_60[0x20]; 12694 12695 u8 state[0x4]; 12696 u8 track_type[0x4]; 12697 u8 log_addr_space_size[0x8]; 12698 u8 reserved_at_90[0x3]; 12699 u8 log_page_size[0x5]; 12700 u8 reserved_at_98[0x3]; 12701 u8 log_msg_size[0x5]; 12702 12703 u8 reserved_at_a0[0x8]; 12704 u8 reporting_qpn[0x18]; 12705 12706 u8 reserved_at_c0[0x18]; 12707 u8 num_ranges[0x8]; 12708 12709 u8 reserved_at_e0[0x20]; 12710 12711 u8 range_start_address[0x40]; 12712 12713 u8 length[0x40]; 12714 12715 struct mlx5_ifc_page_track_range_bits track_range[0]; 12716 }; 12717 12718 struct mlx5_ifc_create_page_track_obj_in_bits { 12719 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12720 struct mlx5_ifc_page_track_bits obj_context; 12721 }; 12722 12723 struct mlx5_ifc_modify_page_track_obj_in_bits { 12724 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12725 struct mlx5_ifc_page_track_bits obj_context; 12726 }; 12727 12728 struct mlx5_ifc_query_page_track_obj_out_bits { 12729 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 12730 struct mlx5_ifc_page_track_bits obj_context; 12731 }; 12732 12733 struct mlx5_ifc_msecq_reg_bits { 12734 u8 reserved_at_0[0x20]; 12735 12736 u8 reserved_at_20[0x12]; 12737 u8 network_option[0x2]; 12738 u8 local_ssm_code[0x4]; 12739 u8 local_enhanced_ssm_code[0x8]; 12740 12741 u8 local_clock_identity[0x40]; 12742 12743 u8 reserved_at_80[0x180]; 12744 }; 12745 12746 enum { 12747 MLX5_MSEES_FIELD_SELECT_ENABLE = BIT(0), 12748 MLX5_MSEES_FIELD_SELECT_ADMIN_STATUS = BIT(1), 12749 MLX5_MSEES_FIELD_SELECT_ADMIN_FREQ_MEASURE = BIT(2), 12750 }; 12751 12752 enum mlx5_msees_admin_status { 12753 MLX5_MSEES_ADMIN_STATUS_FREE_RUNNING = 0x0, 12754 MLX5_MSEES_ADMIN_STATUS_TRACK = 0x1, 12755 }; 12756 12757 enum mlx5_msees_oper_status { 12758 MLX5_MSEES_OPER_STATUS_FREE_RUNNING = 0x0, 12759 MLX5_MSEES_OPER_STATUS_SELF_TRACK = 0x1, 12760 MLX5_MSEES_OPER_STATUS_OTHER_TRACK = 0x2, 12761 MLX5_MSEES_OPER_STATUS_HOLDOVER = 0x3, 12762 MLX5_MSEES_OPER_STATUS_FAIL_HOLDOVER = 0x4, 12763 MLX5_MSEES_OPER_STATUS_FAIL_FREE_RUNNING = 0x5, 12764 }; 12765 12766 enum mlx5_msees_failure_reason { 12767 MLX5_MSEES_FAILURE_REASON_UNDEFINED_ERROR = 0x0, 12768 MLX5_MSEES_FAILURE_REASON_PORT_DOWN = 0x1, 12769 MLX5_MSEES_FAILURE_REASON_TOO_HIGH_FREQUENCY_DIFF = 0x2, 12770 MLX5_MSEES_FAILURE_REASON_NET_SYNCHRONIZER_DEVICE_ERROR = 0x3, 12771 MLX5_MSEES_FAILURE_REASON_LACK_OF_RESOURCES = 0x4, 12772 }; 12773 12774 struct mlx5_ifc_msees_reg_bits { 12775 u8 reserved_at_0[0x8]; 12776 u8 local_port[0x8]; 12777 u8 pnat[0x2]; 12778 u8 lp_msb[0x2]; 12779 u8 reserved_at_14[0xc]; 12780 12781 u8 field_select[0x20]; 12782 12783 u8 admin_status[0x4]; 12784 u8 oper_status[0x4]; 12785 u8 ho_acq[0x1]; 12786 u8 reserved_at_49[0xc]; 12787 u8 admin_freq_measure[0x1]; 12788 u8 oper_freq_measure[0x1]; 12789 u8 failure_reason[0x9]; 12790 12791 u8 frequency_diff[0x20]; 12792 12793 u8 reserved_at_80[0x180]; 12794 }; 12795 12796 #endif /* MLX5_IFC_H */ 12797