1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 #ifndef MLX5_IFC_H 33 #define MLX5_IFC_H 34 35 #include "mlx5_ifc_fpga.h" 36 37 enum { 38 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0, 39 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1, 40 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2, 41 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3, 42 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13, 43 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14, 44 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c, 45 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d, 46 MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4, 47 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5, 48 MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED = 0x7, 49 MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT = 0xc, 50 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10, 51 MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR = 0x11, 52 MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR = 0x12, 53 MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR = 0x8, 54 MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE = 0x9, 55 MLX5_EVENT_TYPE_CODING_GPIO_EVENT = 0x15, 56 MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19, 57 MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a, 58 MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT = 0x1b, 59 MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT = 0x1f, 60 MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa, 61 MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb, 62 MLX5_EVENT_TYPE_CODING_FPGA_ERROR = 0x20, 63 MLX5_EVENT_TYPE_CODING_FPGA_QP_ERROR = 0x21 64 }; 65 66 enum { 67 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0, 68 MLX5_SET_HCA_CAP_OP_MOD_ODP = 0x2, 69 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3, 70 MLX5_SET_HCA_CAP_OP_MOD_ROCE = 0x4, 71 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE2 = 0x20, 72 MLX5_SET_HCA_CAP_OP_MOD_PORT_SELECTION = 0x25, 73 }; 74 75 enum { 76 MLX5_SHARED_RESOURCE_UID = 0xffff, 77 }; 78 79 enum { 80 MLX5_OBJ_TYPE_SW_ICM = 0x0008, 81 MLX5_OBJ_TYPE_HEADER_MODIFY_ARGUMENT = 0x23, 82 }; 83 84 enum { 85 MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM = (1ULL << MLX5_OBJ_TYPE_SW_ICM), 86 MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT = (1ULL << 11), 87 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q = (1ULL << 13), 88 MLX5_GENERAL_OBJ_TYPES_CAP_HEADER_MODIFY_ARGUMENT = 89 (1ULL << MLX5_OBJ_TYPE_HEADER_MODIFY_ARGUMENT), 90 MLX5_GENERAL_OBJ_TYPES_CAP_MACSEC_OFFLOAD = (1ULL << 39), 91 }; 92 93 enum { 94 MLX5_OBJ_TYPE_GENEVE_TLV_OPT = 0x000b, 95 MLX5_OBJ_TYPE_VIRTIO_NET_Q = 0x000d, 96 MLX5_OBJ_TYPE_VIRTIO_Q_COUNTERS = 0x001c, 97 MLX5_OBJ_TYPE_MATCH_DEFINER = 0x0018, 98 MLX5_OBJ_TYPE_PAGE_TRACK = 0x46, 99 MLX5_OBJ_TYPE_MKEY = 0xff01, 100 MLX5_OBJ_TYPE_QP = 0xff02, 101 MLX5_OBJ_TYPE_PSV = 0xff03, 102 MLX5_OBJ_TYPE_RMP = 0xff04, 103 MLX5_OBJ_TYPE_XRC_SRQ = 0xff05, 104 MLX5_OBJ_TYPE_RQ = 0xff06, 105 MLX5_OBJ_TYPE_SQ = 0xff07, 106 MLX5_OBJ_TYPE_TIR = 0xff08, 107 MLX5_OBJ_TYPE_TIS = 0xff09, 108 MLX5_OBJ_TYPE_DCT = 0xff0a, 109 MLX5_OBJ_TYPE_XRQ = 0xff0b, 110 MLX5_OBJ_TYPE_RQT = 0xff0e, 111 MLX5_OBJ_TYPE_FLOW_COUNTER = 0xff0f, 112 MLX5_OBJ_TYPE_CQ = 0xff10, 113 }; 114 115 enum { 116 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100, 117 MLX5_CMD_OP_QUERY_ADAPTER = 0x101, 118 MLX5_CMD_OP_INIT_HCA = 0x102, 119 MLX5_CMD_OP_TEARDOWN_HCA = 0x103, 120 MLX5_CMD_OP_ENABLE_HCA = 0x104, 121 MLX5_CMD_OP_DISABLE_HCA = 0x105, 122 MLX5_CMD_OP_QUERY_PAGES = 0x107, 123 MLX5_CMD_OP_MANAGE_PAGES = 0x108, 124 MLX5_CMD_OP_SET_HCA_CAP = 0x109, 125 MLX5_CMD_OP_QUERY_ISSI = 0x10a, 126 MLX5_CMD_OP_SET_ISSI = 0x10b, 127 MLX5_CMD_OP_SET_DRIVER_VERSION = 0x10d, 128 MLX5_CMD_OP_QUERY_SF_PARTITION = 0x111, 129 MLX5_CMD_OP_ALLOC_SF = 0x113, 130 MLX5_CMD_OP_DEALLOC_SF = 0x114, 131 MLX5_CMD_OP_SUSPEND_VHCA = 0x115, 132 MLX5_CMD_OP_RESUME_VHCA = 0x116, 133 MLX5_CMD_OP_QUERY_VHCA_MIGRATION_STATE = 0x117, 134 MLX5_CMD_OP_SAVE_VHCA_STATE = 0x118, 135 MLX5_CMD_OP_LOAD_VHCA_STATE = 0x119, 136 MLX5_CMD_OP_CREATE_MKEY = 0x200, 137 MLX5_CMD_OP_QUERY_MKEY = 0x201, 138 MLX5_CMD_OP_DESTROY_MKEY = 0x202, 139 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203, 140 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204, 141 MLX5_CMD_OP_ALLOC_MEMIC = 0x205, 142 MLX5_CMD_OP_DEALLOC_MEMIC = 0x206, 143 MLX5_CMD_OP_MODIFY_MEMIC = 0x207, 144 MLX5_CMD_OP_CREATE_EQ = 0x301, 145 MLX5_CMD_OP_DESTROY_EQ = 0x302, 146 MLX5_CMD_OP_QUERY_EQ = 0x303, 147 MLX5_CMD_OP_GEN_EQE = 0x304, 148 MLX5_CMD_OP_CREATE_CQ = 0x400, 149 MLX5_CMD_OP_DESTROY_CQ = 0x401, 150 MLX5_CMD_OP_QUERY_CQ = 0x402, 151 MLX5_CMD_OP_MODIFY_CQ = 0x403, 152 MLX5_CMD_OP_CREATE_QP = 0x500, 153 MLX5_CMD_OP_DESTROY_QP = 0x501, 154 MLX5_CMD_OP_RST2INIT_QP = 0x502, 155 MLX5_CMD_OP_INIT2RTR_QP = 0x503, 156 MLX5_CMD_OP_RTR2RTS_QP = 0x504, 157 MLX5_CMD_OP_RTS2RTS_QP = 0x505, 158 MLX5_CMD_OP_SQERR2RTS_QP = 0x506, 159 MLX5_CMD_OP_2ERR_QP = 0x507, 160 MLX5_CMD_OP_2RST_QP = 0x50a, 161 MLX5_CMD_OP_QUERY_QP = 0x50b, 162 MLX5_CMD_OP_SQD_RTS_QP = 0x50c, 163 MLX5_CMD_OP_INIT2INIT_QP = 0x50e, 164 MLX5_CMD_OP_CREATE_PSV = 0x600, 165 MLX5_CMD_OP_DESTROY_PSV = 0x601, 166 MLX5_CMD_OP_CREATE_SRQ = 0x700, 167 MLX5_CMD_OP_DESTROY_SRQ = 0x701, 168 MLX5_CMD_OP_QUERY_SRQ = 0x702, 169 MLX5_CMD_OP_ARM_RQ = 0x703, 170 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705, 171 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706, 172 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707, 173 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708, 174 MLX5_CMD_OP_CREATE_DCT = 0x710, 175 MLX5_CMD_OP_DESTROY_DCT = 0x711, 176 MLX5_CMD_OP_DRAIN_DCT = 0x712, 177 MLX5_CMD_OP_QUERY_DCT = 0x713, 178 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714, 179 MLX5_CMD_OP_CREATE_XRQ = 0x717, 180 MLX5_CMD_OP_DESTROY_XRQ = 0x718, 181 MLX5_CMD_OP_QUERY_XRQ = 0x719, 182 MLX5_CMD_OP_ARM_XRQ = 0x71a, 183 MLX5_CMD_OP_QUERY_XRQ_DC_PARAMS_ENTRY = 0x725, 184 MLX5_CMD_OP_SET_XRQ_DC_PARAMS_ENTRY = 0x726, 185 MLX5_CMD_OP_QUERY_XRQ_ERROR_PARAMS = 0x727, 186 MLX5_CMD_OP_RELEASE_XRQ_ERROR = 0x729, 187 MLX5_CMD_OP_MODIFY_XRQ = 0x72a, 188 MLX5_CMD_OP_QUERY_ESW_FUNCTIONS = 0x740, 189 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750, 190 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751, 191 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752, 192 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753, 193 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754, 194 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755, 195 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760, 196 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761, 197 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762, 198 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763, 199 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764, 200 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765, 201 MLX5_CMD_OP_QUERY_VNIC_ENV = 0x76f, 202 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770, 203 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771, 204 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772, 205 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773, 206 MLX5_CMD_OP_SET_MONITOR_COUNTER = 0x774, 207 MLX5_CMD_OP_ARM_MONITOR_COUNTER = 0x775, 208 MLX5_CMD_OP_SET_PP_RATE_LIMIT = 0x780, 209 MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781, 210 MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT = 0x782, 211 MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT = 0x783, 212 MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT = 0x784, 213 MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT = 0x785, 214 MLX5_CMD_OP_CREATE_QOS_PARA_VPORT = 0x786, 215 MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT = 0x787, 216 MLX5_CMD_OP_ALLOC_PD = 0x800, 217 MLX5_CMD_OP_DEALLOC_PD = 0x801, 218 MLX5_CMD_OP_ALLOC_UAR = 0x802, 219 MLX5_CMD_OP_DEALLOC_UAR = 0x803, 220 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804, 221 MLX5_CMD_OP_ACCESS_REG = 0x805, 222 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806, 223 MLX5_CMD_OP_DETACH_FROM_MCG = 0x807, 224 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a, 225 MLX5_CMD_OP_MAD_IFC = 0x50d, 226 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b, 227 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c, 228 MLX5_CMD_OP_NOP = 0x80d, 229 MLX5_CMD_OP_ALLOC_XRCD = 0x80e, 230 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f, 231 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816, 232 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817, 233 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822, 234 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823, 235 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824, 236 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825, 237 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826, 238 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827, 239 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828, 240 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829, 241 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a, 242 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b, 243 MLX5_CMD_OP_SET_WOL_ROL = 0x830, 244 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831, 245 MLX5_CMD_OP_CREATE_LAG = 0x840, 246 MLX5_CMD_OP_MODIFY_LAG = 0x841, 247 MLX5_CMD_OP_QUERY_LAG = 0x842, 248 MLX5_CMD_OP_DESTROY_LAG = 0x843, 249 MLX5_CMD_OP_CREATE_VPORT_LAG = 0x844, 250 MLX5_CMD_OP_DESTROY_VPORT_LAG = 0x845, 251 MLX5_CMD_OP_CREATE_TIR = 0x900, 252 MLX5_CMD_OP_MODIFY_TIR = 0x901, 253 MLX5_CMD_OP_DESTROY_TIR = 0x902, 254 MLX5_CMD_OP_QUERY_TIR = 0x903, 255 MLX5_CMD_OP_CREATE_SQ = 0x904, 256 MLX5_CMD_OP_MODIFY_SQ = 0x905, 257 MLX5_CMD_OP_DESTROY_SQ = 0x906, 258 MLX5_CMD_OP_QUERY_SQ = 0x907, 259 MLX5_CMD_OP_CREATE_RQ = 0x908, 260 MLX5_CMD_OP_MODIFY_RQ = 0x909, 261 MLX5_CMD_OP_SET_DELAY_DROP_PARAMS = 0x910, 262 MLX5_CMD_OP_DESTROY_RQ = 0x90a, 263 MLX5_CMD_OP_QUERY_RQ = 0x90b, 264 MLX5_CMD_OP_CREATE_RMP = 0x90c, 265 MLX5_CMD_OP_MODIFY_RMP = 0x90d, 266 MLX5_CMD_OP_DESTROY_RMP = 0x90e, 267 MLX5_CMD_OP_QUERY_RMP = 0x90f, 268 MLX5_CMD_OP_CREATE_TIS = 0x912, 269 MLX5_CMD_OP_MODIFY_TIS = 0x913, 270 MLX5_CMD_OP_DESTROY_TIS = 0x914, 271 MLX5_CMD_OP_QUERY_TIS = 0x915, 272 MLX5_CMD_OP_CREATE_RQT = 0x916, 273 MLX5_CMD_OP_MODIFY_RQT = 0x917, 274 MLX5_CMD_OP_DESTROY_RQT = 0x918, 275 MLX5_CMD_OP_QUERY_RQT = 0x919, 276 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f, 277 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930, 278 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931, 279 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932, 280 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933, 281 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934, 282 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935, 283 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936, 284 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937, 285 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938, 286 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939, 287 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a, 288 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b, 289 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c, 290 MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT = 0x93d, 291 MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT = 0x93e, 292 MLX5_CMD_OP_QUERY_PACKET_REFORMAT_CONTEXT = 0x93f, 293 MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT = 0x940, 294 MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941, 295 MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT = 0x942, 296 MLX5_CMD_OP_FPGA_CREATE_QP = 0x960, 297 MLX5_CMD_OP_FPGA_MODIFY_QP = 0x961, 298 MLX5_CMD_OP_FPGA_QUERY_QP = 0x962, 299 MLX5_CMD_OP_FPGA_DESTROY_QP = 0x963, 300 MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS = 0x964, 301 MLX5_CMD_OP_CREATE_GENERAL_OBJECT = 0xa00, 302 MLX5_CMD_OP_MODIFY_GENERAL_OBJECT = 0xa01, 303 MLX5_CMD_OP_QUERY_GENERAL_OBJECT = 0xa02, 304 MLX5_CMD_OP_DESTROY_GENERAL_OBJECT = 0xa03, 305 MLX5_CMD_OP_CREATE_UCTX = 0xa04, 306 MLX5_CMD_OP_DESTROY_UCTX = 0xa06, 307 MLX5_CMD_OP_CREATE_UMEM = 0xa08, 308 MLX5_CMD_OP_DESTROY_UMEM = 0xa0a, 309 MLX5_CMD_OP_SYNC_STEERING = 0xb00, 310 MLX5_CMD_OP_QUERY_VHCA_STATE = 0xb0d, 311 MLX5_CMD_OP_MODIFY_VHCA_STATE = 0xb0e, 312 MLX5_CMD_OP_SYNC_CRYPTO = 0xb12, 313 MLX5_CMD_OP_MAX 314 }; 315 316 /* Valid range for general commands that don't work over an object */ 317 enum { 318 MLX5_CMD_OP_GENERAL_START = 0xb00, 319 MLX5_CMD_OP_GENERAL_END = 0xd00, 320 }; 321 322 enum { 323 MLX5_FT_NIC_RX_2_NIC_RX_RDMA = BIT(0), 324 MLX5_FT_NIC_TX_RDMA_2_NIC_TX = BIT(1), 325 }; 326 327 enum { 328 MLX5_CMD_OP_MOD_UPDATE_HEADER_MODIFY_ARGUMENT = 0x1, 329 }; 330 331 struct mlx5_ifc_flow_table_fields_supported_bits { 332 u8 outer_dmac[0x1]; 333 u8 outer_smac[0x1]; 334 u8 outer_ether_type[0x1]; 335 u8 outer_ip_version[0x1]; 336 u8 outer_first_prio[0x1]; 337 u8 outer_first_cfi[0x1]; 338 u8 outer_first_vid[0x1]; 339 u8 outer_ipv4_ttl[0x1]; 340 u8 outer_second_prio[0x1]; 341 u8 outer_second_cfi[0x1]; 342 u8 outer_second_vid[0x1]; 343 u8 reserved_at_b[0x1]; 344 u8 outer_sip[0x1]; 345 u8 outer_dip[0x1]; 346 u8 outer_frag[0x1]; 347 u8 outer_ip_protocol[0x1]; 348 u8 outer_ip_ecn[0x1]; 349 u8 outer_ip_dscp[0x1]; 350 u8 outer_udp_sport[0x1]; 351 u8 outer_udp_dport[0x1]; 352 u8 outer_tcp_sport[0x1]; 353 u8 outer_tcp_dport[0x1]; 354 u8 outer_tcp_flags[0x1]; 355 u8 outer_gre_protocol[0x1]; 356 u8 outer_gre_key[0x1]; 357 u8 outer_vxlan_vni[0x1]; 358 u8 outer_geneve_vni[0x1]; 359 u8 outer_geneve_oam[0x1]; 360 u8 outer_geneve_protocol_type[0x1]; 361 u8 outer_geneve_opt_len[0x1]; 362 u8 source_vhca_port[0x1]; 363 u8 source_eswitch_port[0x1]; 364 365 u8 inner_dmac[0x1]; 366 u8 inner_smac[0x1]; 367 u8 inner_ether_type[0x1]; 368 u8 inner_ip_version[0x1]; 369 u8 inner_first_prio[0x1]; 370 u8 inner_first_cfi[0x1]; 371 u8 inner_first_vid[0x1]; 372 u8 reserved_at_27[0x1]; 373 u8 inner_second_prio[0x1]; 374 u8 inner_second_cfi[0x1]; 375 u8 inner_second_vid[0x1]; 376 u8 reserved_at_2b[0x1]; 377 u8 inner_sip[0x1]; 378 u8 inner_dip[0x1]; 379 u8 inner_frag[0x1]; 380 u8 inner_ip_protocol[0x1]; 381 u8 inner_ip_ecn[0x1]; 382 u8 inner_ip_dscp[0x1]; 383 u8 inner_udp_sport[0x1]; 384 u8 inner_udp_dport[0x1]; 385 u8 inner_tcp_sport[0x1]; 386 u8 inner_tcp_dport[0x1]; 387 u8 inner_tcp_flags[0x1]; 388 u8 reserved_at_37[0x9]; 389 390 u8 geneve_tlv_option_0_data[0x1]; 391 u8 geneve_tlv_option_0_exist[0x1]; 392 u8 reserved_at_42[0x3]; 393 u8 outer_first_mpls_over_udp[0x4]; 394 u8 outer_first_mpls_over_gre[0x4]; 395 u8 inner_first_mpls[0x4]; 396 u8 outer_first_mpls[0x4]; 397 u8 reserved_at_55[0x2]; 398 u8 outer_esp_spi[0x1]; 399 u8 reserved_at_58[0x2]; 400 u8 bth_dst_qp[0x1]; 401 u8 reserved_at_5b[0x5]; 402 403 u8 reserved_at_60[0x18]; 404 u8 metadata_reg_c_7[0x1]; 405 u8 metadata_reg_c_6[0x1]; 406 u8 metadata_reg_c_5[0x1]; 407 u8 metadata_reg_c_4[0x1]; 408 u8 metadata_reg_c_3[0x1]; 409 u8 metadata_reg_c_2[0x1]; 410 u8 metadata_reg_c_1[0x1]; 411 u8 metadata_reg_c_0[0x1]; 412 }; 413 414 /* Table 2170 - Flow Table Fields Supported 2 Format */ 415 struct mlx5_ifc_flow_table_fields_supported_2_bits { 416 u8 reserved_at_0[0xe]; 417 u8 bth_opcode[0x1]; 418 u8 reserved_at_f[0x1]; 419 u8 tunnel_header_0_1[0x1]; 420 u8 reserved_at_11[0xf]; 421 422 u8 reserved_at_20[0x60]; 423 }; 424 425 struct mlx5_ifc_flow_table_prop_layout_bits { 426 u8 ft_support[0x1]; 427 u8 reserved_at_1[0x1]; 428 u8 flow_counter[0x1]; 429 u8 flow_modify_en[0x1]; 430 u8 modify_root[0x1]; 431 u8 identified_miss_table_mode[0x1]; 432 u8 flow_table_modify[0x1]; 433 u8 reformat[0x1]; 434 u8 decap[0x1]; 435 u8 reserved_at_9[0x1]; 436 u8 pop_vlan[0x1]; 437 u8 push_vlan[0x1]; 438 u8 reserved_at_c[0x1]; 439 u8 pop_vlan_2[0x1]; 440 u8 push_vlan_2[0x1]; 441 u8 reformat_and_vlan_action[0x1]; 442 u8 reserved_at_10[0x1]; 443 u8 sw_owner[0x1]; 444 u8 reformat_l3_tunnel_to_l2[0x1]; 445 u8 reformat_l2_to_l3_tunnel[0x1]; 446 u8 reformat_and_modify_action[0x1]; 447 u8 ignore_flow_level[0x1]; 448 u8 reserved_at_16[0x1]; 449 u8 table_miss_action_domain[0x1]; 450 u8 termination_table[0x1]; 451 u8 reformat_and_fwd_to_table[0x1]; 452 u8 reserved_at_1a[0x2]; 453 u8 ipsec_encrypt[0x1]; 454 u8 ipsec_decrypt[0x1]; 455 u8 sw_owner_v2[0x1]; 456 u8 reserved_at_1f[0x1]; 457 458 u8 termination_table_raw_traffic[0x1]; 459 u8 reserved_at_21[0x1]; 460 u8 log_max_ft_size[0x6]; 461 u8 log_max_modify_header_context[0x8]; 462 u8 max_modify_header_actions[0x8]; 463 u8 max_ft_level[0x8]; 464 465 u8 reformat_add_esp_trasport[0x1]; 466 u8 reformat_l2_to_l3_esp_tunnel[0x1]; 467 u8 reserved_at_42[0x1]; 468 u8 reformat_del_esp_trasport[0x1]; 469 u8 reformat_l3_esp_tunnel_to_l2[0x1]; 470 u8 reserved_at_45[0x1]; 471 u8 execute_aso[0x1]; 472 u8 reserved_at_47[0x19]; 473 474 u8 reserved_at_60[0x2]; 475 u8 reformat_insert[0x1]; 476 u8 reformat_remove[0x1]; 477 u8 macsec_encrypt[0x1]; 478 u8 macsec_decrypt[0x1]; 479 u8 reserved_at_66[0x2]; 480 u8 reformat_add_macsec[0x1]; 481 u8 reformat_remove_macsec[0x1]; 482 u8 reserved_at_6a[0xe]; 483 u8 log_max_ft_num[0x8]; 484 485 u8 reserved_at_80[0x10]; 486 u8 log_max_flow_counter[0x8]; 487 u8 log_max_destination[0x8]; 488 489 u8 reserved_at_a0[0x18]; 490 u8 log_max_flow[0x8]; 491 492 u8 reserved_at_c0[0x40]; 493 494 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support; 495 496 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support; 497 }; 498 499 struct mlx5_ifc_odp_per_transport_service_cap_bits { 500 u8 send[0x1]; 501 u8 receive[0x1]; 502 u8 write[0x1]; 503 u8 read[0x1]; 504 u8 atomic[0x1]; 505 u8 srq_receive[0x1]; 506 u8 reserved_at_6[0x1a]; 507 }; 508 509 struct mlx5_ifc_ipv4_layout_bits { 510 u8 reserved_at_0[0x60]; 511 512 u8 ipv4[0x20]; 513 }; 514 515 struct mlx5_ifc_ipv6_layout_bits { 516 u8 ipv6[16][0x8]; 517 }; 518 519 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits { 520 struct mlx5_ifc_ipv6_layout_bits ipv6_layout; 521 struct mlx5_ifc_ipv4_layout_bits ipv4_layout; 522 u8 reserved_at_0[0x80]; 523 }; 524 525 struct mlx5_ifc_fte_match_set_lyr_2_4_bits { 526 u8 smac_47_16[0x20]; 527 528 u8 smac_15_0[0x10]; 529 u8 ethertype[0x10]; 530 531 u8 dmac_47_16[0x20]; 532 533 u8 dmac_15_0[0x10]; 534 u8 first_prio[0x3]; 535 u8 first_cfi[0x1]; 536 u8 first_vid[0xc]; 537 538 u8 ip_protocol[0x8]; 539 u8 ip_dscp[0x6]; 540 u8 ip_ecn[0x2]; 541 u8 cvlan_tag[0x1]; 542 u8 svlan_tag[0x1]; 543 u8 frag[0x1]; 544 u8 ip_version[0x4]; 545 u8 tcp_flags[0x9]; 546 547 u8 tcp_sport[0x10]; 548 u8 tcp_dport[0x10]; 549 550 u8 reserved_at_c0[0x10]; 551 u8 ipv4_ihl[0x4]; 552 u8 reserved_at_c4[0x4]; 553 554 u8 ttl_hoplimit[0x8]; 555 556 u8 udp_sport[0x10]; 557 u8 udp_dport[0x10]; 558 559 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6; 560 561 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6; 562 }; 563 564 struct mlx5_ifc_nvgre_key_bits { 565 u8 hi[0x18]; 566 u8 lo[0x8]; 567 }; 568 569 union mlx5_ifc_gre_key_bits { 570 struct mlx5_ifc_nvgre_key_bits nvgre; 571 u8 key[0x20]; 572 }; 573 574 struct mlx5_ifc_fte_match_set_misc_bits { 575 u8 gre_c_present[0x1]; 576 u8 reserved_at_1[0x1]; 577 u8 gre_k_present[0x1]; 578 u8 gre_s_present[0x1]; 579 u8 source_vhca_port[0x4]; 580 u8 source_sqn[0x18]; 581 582 u8 source_eswitch_owner_vhca_id[0x10]; 583 u8 source_port[0x10]; 584 585 u8 outer_second_prio[0x3]; 586 u8 outer_second_cfi[0x1]; 587 u8 outer_second_vid[0xc]; 588 u8 inner_second_prio[0x3]; 589 u8 inner_second_cfi[0x1]; 590 u8 inner_second_vid[0xc]; 591 592 u8 outer_second_cvlan_tag[0x1]; 593 u8 inner_second_cvlan_tag[0x1]; 594 u8 outer_second_svlan_tag[0x1]; 595 u8 inner_second_svlan_tag[0x1]; 596 u8 reserved_at_64[0xc]; 597 u8 gre_protocol[0x10]; 598 599 union mlx5_ifc_gre_key_bits gre_key; 600 601 u8 vxlan_vni[0x18]; 602 u8 bth_opcode[0x8]; 603 604 u8 geneve_vni[0x18]; 605 u8 reserved_at_d8[0x6]; 606 u8 geneve_tlv_option_0_exist[0x1]; 607 u8 geneve_oam[0x1]; 608 609 u8 reserved_at_e0[0xc]; 610 u8 outer_ipv6_flow_label[0x14]; 611 612 u8 reserved_at_100[0xc]; 613 u8 inner_ipv6_flow_label[0x14]; 614 615 u8 reserved_at_120[0xa]; 616 u8 geneve_opt_len[0x6]; 617 u8 geneve_protocol_type[0x10]; 618 619 u8 reserved_at_140[0x8]; 620 u8 bth_dst_qp[0x18]; 621 u8 reserved_at_160[0x20]; 622 u8 outer_esp_spi[0x20]; 623 u8 reserved_at_1a0[0x60]; 624 }; 625 626 struct mlx5_ifc_fte_match_mpls_bits { 627 u8 mpls_label[0x14]; 628 u8 mpls_exp[0x3]; 629 u8 mpls_s_bos[0x1]; 630 u8 mpls_ttl[0x8]; 631 }; 632 633 struct mlx5_ifc_fte_match_set_misc2_bits { 634 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls; 635 636 struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls; 637 638 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre; 639 640 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp; 641 642 u8 metadata_reg_c_7[0x20]; 643 644 u8 metadata_reg_c_6[0x20]; 645 646 u8 metadata_reg_c_5[0x20]; 647 648 u8 metadata_reg_c_4[0x20]; 649 650 u8 metadata_reg_c_3[0x20]; 651 652 u8 metadata_reg_c_2[0x20]; 653 654 u8 metadata_reg_c_1[0x20]; 655 656 u8 metadata_reg_c_0[0x20]; 657 658 u8 metadata_reg_a[0x20]; 659 660 u8 reserved_at_1a0[0x8]; 661 662 u8 macsec_syndrome[0x8]; 663 u8 ipsec_syndrome[0x8]; 664 u8 reserved_at_1b8[0x8]; 665 666 u8 reserved_at_1c0[0x40]; 667 }; 668 669 struct mlx5_ifc_fte_match_set_misc3_bits { 670 u8 inner_tcp_seq_num[0x20]; 671 672 u8 outer_tcp_seq_num[0x20]; 673 674 u8 inner_tcp_ack_num[0x20]; 675 676 u8 outer_tcp_ack_num[0x20]; 677 678 u8 reserved_at_80[0x8]; 679 u8 outer_vxlan_gpe_vni[0x18]; 680 681 u8 outer_vxlan_gpe_next_protocol[0x8]; 682 u8 outer_vxlan_gpe_flags[0x8]; 683 u8 reserved_at_b0[0x10]; 684 685 u8 icmp_header_data[0x20]; 686 687 u8 icmpv6_header_data[0x20]; 688 689 u8 icmp_type[0x8]; 690 u8 icmp_code[0x8]; 691 u8 icmpv6_type[0x8]; 692 u8 icmpv6_code[0x8]; 693 694 u8 geneve_tlv_option_0_data[0x20]; 695 696 u8 gtpu_teid[0x20]; 697 698 u8 gtpu_msg_type[0x8]; 699 u8 gtpu_msg_flags[0x8]; 700 u8 reserved_at_170[0x10]; 701 702 u8 gtpu_dw_2[0x20]; 703 704 u8 gtpu_first_ext_dw_0[0x20]; 705 706 u8 gtpu_dw_0[0x20]; 707 708 u8 reserved_at_1e0[0x20]; 709 }; 710 711 struct mlx5_ifc_fte_match_set_misc4_bits { 712 u8 prog_sample_field_value_0[0x20]; 713 714 u8 prog_sample_field_id_0[0x20]; 715 716 u8 prog_sample_field_value_1[0x20]; 717 718 u8 prog_sample_field_id_1[0x20]; 719 720 u8 prog_sample_field_value_2[0x20]; 721 722 u8 prog_sample_field_id_2[0x20]; 723 724 u8 prog_sample_field_value_3[0x20]; 725 726 u8 prog_sample_field_id_3[0x20]; 727 728 u8 reserved_at_100[0x100]; 729 }; 730 731 struct mlx5_ifc_fte_match_set_misc5_bits { 732 u8 macsec_tag_0[0x20]; 733 734 u8 macsec_tag_1[0x20]; 735 736 u8 macsec_tag_2[0x20]; 737 738 u8 macsec_tag_3[0x20]; 739 740 u8 tunnel_header_0[0x20]; 741 742 u8 tunnel_header_1[0x20]; 743 744 u8 tunnel_header_2[0x20]; 745 746 u8 tunnel_header_3[0x20]; 747 748 u8 reserved_at_100[0x100]; 749 }; 750 751 struct mlx5_ifc_cmd_pas_bits { 752 u8 pa_h[0x20]; 753 754 u8 pa_l[0x14]; 755 u8 reserved_at_34[0xc]; 756 }; 757 758 struct mlx5_ifc_uint64_bits { 759 u8 hi[0x20]; 760 761 u8 lo[0x20]; 762 }; 763 764 enum { 765 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0, 766 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7, 767 MLX5_ADS_STAT_RATE_10GBPS = 0x8, 768 MLX5_ADS_STAT_RATE_30GBPS = 0x9, 769 MLX5_ADS_STAT_RATE_5GBPS = 0xa, 770 MLX5_ADS_STAT_RATE_20GBPS = 0xb, 771 MLX5_ADS_STAT_RATE_40GBPS = 0xc, 772 MLX5_ADS_STAT_RATE_60GBPS = 0xd, 773 MLX5_ADS_STAT_RATE_80GBPS = 0xe, 774 MLX5_ADS_STAT_RATE_120GBPS = 0xf, 775 }; 776 777 struct mlx5_ifc_ads_bits { 778 u8 fl[0x1]; 779 u8 free_ar[0x1]; 780 u8 reserved_at_2[0xe]; 781 u8 pkey_index[0x10]; 782 783 u8 reserved_at_20[0x8]; 784 u8 grh[0x1]; 785 u8 mlid[0x7]; 786 u8 rlid[0x10]; 787 788 u8 ack_timeout[0x5]; 789 u8 reserved_at_45[0x3]; 790 u8 src_addr_index[0x8]; 791 u8 reserved_at_50[0x4]; 792 u8 stat_rate[0x4]; 793 u8 hop_limit[0x8]; 794 795 u8 reserved_at_60[0x4]; 796 u8 tclass[0x8]; 797 u8 flow_label[0x14]; 798 799 u8 rgid_rip[16][0x8]; 800 801 u8 reserved_at_100[0x4]; 802 u8 f_dscp[0x1]; 803 u8 f_ecn[0x1]; 804 u8 reserved_at_106[0x1]; 805 u8 f_eth_prio[0x1]; 806 u8 ecn[0x2]; 807 u8 dscp[0x6]; 808 u8 udp_sport[0x10]; 809 810 u8 dei_cfi[0x1]; 811 u8 eth_prio[0x3]; 812 u8 sl[0x4]; 813 u8 vhca_port_num[0x8]; 814 u8 rmac_47_32[0x10]; 815 816 u8 rmac_31_0[0x20]; 817 }; 818 819 struct mlx5_ifc_flow_table_nic_cap_bits { 820 u8 nic_rx_multi_path_tirs[0x1]; 821 u8 nic_rx_multi_path_tirs_fts[0x1]; 822 u8 allow_sniffer_and_nic_rx_shared_tir[0x1]; 823 u8 reserved_at_3[0x4]; 824 u8 sw_owner_reformat_supported[0x1]; 825 u8 reserved_at_8[0x18]; 826 827 u8 encap_general_header[0x1]; 828 u8 reserved_at_21[0xa]; 829 u8 log_max_packet_reformat_context[0x5]; 830 u8 reserved_at_30[0x6]; 831 u8 max_encap_header_size[0xa]; 832 u8 reserved_at_40[0x1c0]; 833 834 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive; 835 836 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_rdma; 837 838 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer; 839 840 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit; 841 842 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_rdma; 843 844 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer; 845 846 u8 reserved_at_e00[0x700]; 847 848 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_receive_rdma; 849 850 u8 reserved_at_1580[0x280]; 851 852 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_transmit_rdma; 853 854 u8 reserved_at_1880[0x780]; 855 856 u8 sw_steering_nic_rx_action_drop_icm_address[0x40]; 857 858 u8 sw_steering_nic_tx_action_drop_icm_address[0x40]; 859 860 u8 sw_steering_nic_tx_action_allow_icm_address[0x40]; 861 862 u8 reserved_at_20c0[0x5f40]; 863 }; 864 865 struct mlx5_ifc_port_selection_cap_bits { 866 u8 reserved_at_0[0x10]; 867 u8 port_select_flow_table[0x1]; 868 u8 reserved_at_11[0x1]; 869 u8 port_select_flow_table_bypass[0x1]; 870 u8 reserved_at_13[0xd]; 871 872 u8 reserved_at_20[0x1e0]; 873 874 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_port_selection; 875 876 u8 reserved_at_400[0x7c00]; 877 }; 878 879 enum { 880 MLX5_FDB_TO_VPORT_REG_C_0 = 0x01, 881 MLX5_FDB_TO_VPORT_REG_C_1 = 0x02, 882 MLX5_FDB_TO_VPORT_REG_C_2 = 0x04, 883 MLX5_FDB_TO_VPORT_REG_C_3 = 0x08, 884 MLX5_FDB_TO_VPORT_REG_C_4 = 0x10, 885 MLX5_FDB_TO_VPORT_REG_C_5 = 0x20, 886 MLX5_FDB_TO_VPORT_REG_C_6 = 0x40, 887 MLX5_FDB_TO_VPORT_REG_C_7 = 0x80, 888 }; 889 890 struct mlx5_ifc_flow_table_eswitch_cap_bits { 891 u8 fdb_to_vport_reg_c_id[0x8]; 892 u8 reserved_at_8[0x5]; 893 u8 fdb_uplink_hairpin[0x1]; 894 u8 fdb_multi_path_any_table_limit_regc[0x1]; 895 u8 reserved_at_f[0x3]; 896 u8 fdb_multi_path_any_table[0x1]; 897 u8 reserved_at_13[0x2]; 898 u8 fdb_modify_header_fwd_to_table[0x1]; 899 u8 fdb_ipv4_ttl_modify[0x1]; 900 u8 flow_source[0x1]; 901 u8 reserved_at_18[0x2]; 902 u8 multi_fdb_encap[0x1]; 903 u8 egress_acl_forward_to_vport[0x1]; 904 u8 fdb_multi_path_to_table[0x1]; 905 u8 reserved_at_1d[0x3]; 906 907 u8 reserved_at_20[0x1e0]; 908 909 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb; 910 911 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress; 912 913 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress; 914 915 u8 reserved_at_800[0xC00]; 916 917 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_esw_fdb; 918 919 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_bitmask_support_2_esw_fdb; 920 921 u8 reserved_at_1500[0x300]; 922 923 u8 sw_steering_fdb_action_drop_icm_address_rx[0x40]; 924 925 u8 sw_steering_fdb_action_drop_icm_address_tx[0x40]; 926 927 u8 sw_steering_uplink_icm_address_rx[0x40]; 928 929 u8 sw_steering_uplink_icm_address_tx[0x40]; 930 931 u8 reserved_at_1900[0x6700]; 932 }; 933 934 enum { 935 MLX5_COUNTER_SOURCE_ESWITCH = 0x0, 936 MLX5_COUNTER_FLOW_ESWITCH = 0x1, 937 }; 938 939 struct mlx5_ifc_e_switch_cap_bits { 940 u8 vport_svlan_strip[0x1]; 941 u8 vport_cvlan_strip[0x1]; 942 u8 vport_svlan_insert[0x1]; 943 u8 vport_cvlan_insert_if_not_exist[0x1]; 944 u8 vport_cvlan_insert_overwrite[0x1]; 945 u8 reserved_at_5[0x1]; 946 u8 vport_cvlan_insert_always[0x1]; 947 u8 esw_shared_ingress_acl[0x1]; 948 u8 esw_uplink_ingress_acl[0x1]; 949 u8 root_ft_on_other_esw[0x1]; 950 u8 reserved_at_a[0xf]; 951 u8 esw_functions_changed[0x1]; 952 u8 reserved_at_1a[0x1]; 953 u8 ecpf_vport_exists[0x1]; 954 u8 counter_eswitch_affinity[0x1]; 955 u8 merged_eswitch[0x1]; 956 u8 nic_vport_node_guid_modify[0x1]; 957 u8 nic_vport_port_guid_modify[0x1]; 958 959 u8 vxlan_encap_decap[0x1]; 960 u8 nvgre_encap_decap[0x1]; 961 u8 reserved_at_22[0x1]; 962 u8 log_max_fdb_encap_uplink[0x5]; 963 u8 reserved_at_21[0x3]; 964 u8 log_max_packet_reformat_context[0x5]; 965 u8 reserved_2b[0x6]; 966 u8 max_encap_header_size[0xa]; 967 968 u8 reserved_at_40[0xb]; 969 u8 log_max_esw_sf[0x5]; 970 u8 esw_sf_base_id[0x10]; 971 972 u8 reserved_at_60[0x7a0]; 973 974 }; 975 976 struct mlx5_ifc_qos_cap_bits { 977 u8 packet_pacing[0x1]; 978 u8 esw_scheduling[0x1]; 979 u8 esw_bw_share[0x1]; 980 u8 esw_rate_limit[0x1]; 981 u8 reserved_at_4[0x1]; 982 u8 packet_pacing_burst_bound[0x1]; 983 u8 packet_pacing_typical_size[0x1]; 984 u8 reserved_at_7[0x1]; 985 u8 nic_sq_scheduling[0x1]; 986 u8 nic_bw_share[0x1]; 987 u8 nic_rate_limit[0x1]; 988 u8 packet_pacing_uid[0x1]; 989 u8 log_esw_max_sched_depth[0x4]; 990 u8 reserved_at_10[0x10]; 991 992 u8 reserved_at_20[0xb]; 993 u8 log_max_qos_nic_queue_group[0x5]; 994 u8 reserved_at_30[0x10]; 995 996 u8 packet_pacing_max_rate[0x20]; 997 998 u8 packet_pacing_min_rate[0x20]; 999 1000 u8 reserved_at_80[0x10]; 1001 u8 packet_pacing_rate_table_size[0x10]; 1002 1003 u8 esw_element_type[0x10]; 1004 u8 esw_tsar_type[0x10]; 1005 1006 u8 reserved_at_c0[0x10]; 1007 u8 max_qos_para_vport[0x10]; 1008 1009 u8 max_tsar_bw_share[0x20]; 1010 1011 u8 reserved_at_100[0x20]; 1012 1013 u8 reserved_at_120[0x3]; 1014 u8 log_meter_aso_granularity[0x5]; 1015 u8 reserved_at_128[0x3]; 1016 u8 log_meter_aso_max_alloc[0x5]; 1017 u8 reserved_at_130[0x3]; 1018 u8 log_max_num_meter_aso[0x5]; 1019 u8 reserved_at_138[0x8]; 1020 1021 u8 reserved_at_140[0x6c0]; 1022 }; 1023 1024 struct mlx5_ifc_debug_cap_bits { 1025 u8 core_dump_general[0x1]; 1026 u8 core_dump_qp[0x1]; 1027 u8 reserved_at_2[0x7]; 1028 u8 resource_dump[0x1]; 1029 u8 reserved_at_a[0x16]; 1030 1031 u8 reserved_at_20[0x2]; 1032 u8 stall_detect[0x1]; 1033 u8 reserved_at_23[0x1d]; 1034 1035 u8 reserved_at_40[0x7c0]; 1036 }; 1037 1038 struct mlx5_ifc_per_protocol_networking_offload_caps_bits { 1039 u8 csum_cap[0x1]; 1040 u8 vlan_cap[0x1]; 1041 u8 lro_cap[0x1]; 1042 u8 lro_psh_flag[0x1]; 1043 u8 lro_time_stamp[0x1]; 1044 u8 reserved_at_5[0x2]; 1045 u8 wqe_vlan_insert[0x1]; 1046 u8 self_lb_en_modifiable[0x1]; 1047 u8 reserved_at_9[0x2]; 1048 u8 max_lso_cap[0x5]; 1049 u8 multi_pkt_send_wqe[0x2]; 1050 u8 wqe_inline_mode[0x2]; 1051 u8 rss_ind_tbl_cap[0x4]; 1052 u8 reg_umr_sq[0x1]; 1053 u8 scatter_fcs[0x1]; 1054 u8 enhanced_multi_pkt_send_wqe[0x1]; 1055 u8 tunnel_lso_const_out_ip_id[0x1]; 1056 u8 tunnel_lro_gre[0x1]; 1057 u8 tunnel_lro_vxlan[0x1]; 1058 u8 tunnel_stateless_gre[0x1]; 1059 u8 tunnel_stateless_vxlan[0x1]; 1060 1061 u8 swp[0x1]; 1062 u8 swp_csum[0x1]; 1063 u8 swp_lso[0x1]; 1064 u8 cqe_checksum_full[0x1]; 1065 u8 tunnel_stateless_geneve_tx[0x1]; 1066 u8 tunnel_stateless_mpls_over_udp[0x1]; 1067 u8 tunnel_stateless_mpls_over_gre[0x1]; 1068 u8 tunnel_stateless_vxlan_gpe[0x1]; 1069 u8 tunnel_stateless_ipv4_over_vxlan[0x1]; 1070 u8 tunnel_stateless_ip_over_ip[0x1]; 1071 u8 insert_trailer[0x1]; 1072 u8 reserved_at_2b[0x1]; 1073 u8 tunnel_stateless_ip_over_ip_rx[0x1]; 1074 u8 tunnel_stateless_ip_over_ip_tx[0x1]; 1075 u8 reserved_at_2e[0x2]; 1076 u8 max_vxlan_udp_ports[0x8]; 1077 u8 reserved_at_38[0x6]; 1078 u8 max_geneve_opt_len[0x1]; 1079 u8 tunnel_stateless_geneve_rx[0x1]; 1080 1081 u8 reserved_at_40[0x10]; 1082 u8 lro_min_mss_size[0x10]; 1083 1084 u8 reserved_at_60[0x120]; 1085 1086 u8 lro_timer_supported_periods[4][0x20]; 1087 1088 u8 reserved_at_200[0x600]; 1089 }; 1090 1091 enum { 1092 MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING = 0x0, 1093 MLX5_TIMESTAMP_FORMAT_CAP_REAL_TIME = 0x1, 1094 MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING_AND_REAL_TIME = 0x2, 1095 }; 1096 1097 struct mlx5_ifc_roce_cap_bits { 1098 u8 roce_apm[0x1]; 1099 u8 reserved_at_1[0x3]; 1100 u8 sw_r_roce_src_udp_port[0x1]; 1101 u8 fl_rc_qp_when_roce_disabled[0x1]; 1102 u8 fl_rc_qp_when_roce_enabled[0x1]; 1103 u8 reserved_at_7[0x1]; 1104 u8 qp_ooo_transmit_default[0x1]; 1105 u8 reserved_at_9[0x15]; 1106 u8 qp_ts_format[0x2]; 1107 1108 u8 reserved_at_20[0x60]; 1109 1110 u8 reserved_at_80[0xc]; 1111 u8 l3_type[0x4]; 1112 u8 reserved_at_90[0x8]; 1113 u8 roce_version[0x8]; 1114 1115 u8 reserved_at_a0[0x10]; 1116 u8 r_roce_dest_udp_port[0x10]; 1117 1118 u8 r_roce_max_src_udp_port[0x10]; 1119 u8 r_roce_min_src_udp_port[0x10]; 1120 1121 u8 reserved_at_e0[0x10]; 1122 u8 roce_address_table_size[0x10]; 1123 1124 u8 reserved_at_100[0x700]; 1125 }; 1126 1127 struct mlx5_ifc_sync_steering_in_bits { 1128 u8 opcode[0x10]; 1129 u8 uid[0x10]; 1130 1131 u8 reserved_at_20[0x10]; 1132 u8 op_mod[0x10]; 1133 1134 u8 reserved_at_40[0xc0]; 1135 }; 1136 1137 struct mlx5_ifc_sync_steering_out_bits { 1138 u8 status[0x8]; 1139 u8 reserved_at_8[0x18]; 1140 1141 u8 syndrome[0x20]; 1142 1143 u8 reserved_at_40[0x40]; 1144 }; 1145 1146 struct mlx5_ifc_sync_crypto_in_bits { 1147 u8 opcode[0x10]; 1148 u8 uid[0x10]; 1149 1150 u8 reserved_at_20[0x10]; 1151 u8 op_mod[0x10]; 1152 1153 u8 reserved_at_40[0x20]; 1154 1155 u8 reserved_at_60[0x10]; 1156 u8 crypto_type[0x10]; 1157 1158 u8 reserved_at_80[0x80]; 1159 }; 1160 1161 struct mlx5_ifc_sync_crypto_out_bits { 1162 u8 status[0x8]; 1163 u8 reserved_at_8[0x18]; 1164 1165 u8 syndrome[0x20]; 1166 1167 u8 reserved_at_40[0x40]; 1168 }; 1169 1170 struct mlx5_ifc_device_mem_cap_bits { 1171 u8 memic[0x1]; 1172 u8 reserved_at_1[0x1f]; 1173 1174 u8 reserved_at_20[0xb]; 1175 u8 log_min_memic_alloc_size[0x5]; 1176 u8 reserved_at_30[0x8]; 1177 u8 log_max_memic_addr_alignment[0x8]; 1178 1179 u8 memic_bar_start_addr[0x40]; 1180 1181 u8 memic_bar_size[0x20]; 1182 1183 u8 max_memic_size[0x20]; 1184 1185 u8 steering_sw_icm_start_address[0x40]; 1186 1187 u8 reserved_at_100[0x8]; 1188 u8 log_header_modify_sw_icm_size[0x8]; 1189 u8 reserved_at_110[0x2]; 1190 u8 log_sw_icm_alloc_granularity[0x6]; 1191 u8 log_steering_sw_icm_size[0x8]; 1192 1193 u8 reserved_at_120[0x18]; 1194 u8 log_header_modify_pattern_sw_icm_size[0x8]; 1195 1196 u8 header_modify_sw_icm_start_address[0x40]; 1197 1198 u8 reserved_at_180[0x40]; 1199 1200 u8 header_modify_pattern_sw_icm_start_address[0x40]; 1201 1202 u8 memic_operations[0x20]; 1203 1204 u8 reserved_at_220[0x5e0]; 1205 }; 1206 1207 struct mlx5_ifc_device_event_cap_bits { 1208 u8 user_affiliated_events[4][0x40]; 1209 1210 u8 user_unaffiliated_events[4][0x40]; 1211 }; 1212 1213 struct mlx5_ifc_virtio_emulation_cap_bits { 1214 u8 desc_tunnel_offload_type[0x1]; 1215 u8 eth_frame_offload_type[0x1]; 1216 u8 virtio_version_1_0[0x1]; 1217 u8 device_features_bits_mask[0xd]; 1218 u8 event_mode[0x8]; 1219 u8 virtio_queue_type[0x8]; 1220 1221 u8 max_tunnel_desc[0x10]; 1222 u8 reserved_at_30[0x3]; 1223 u8 log_doorbell_stride[0x5]; 1224 u8 reserved_at_38[0x3]; 1225 u8 log_doorbell_bar_size[0x5]; 1226 1227 u8 doorbell_bar_offset[0x40]; 1228 1229 u8 max_emulated_devices[0x8]; 1230 u8 max_num_virtio_queues[0x18]; 1231 1232 u8 reserved_at_a0[0x60]; 1233 1234 u8 umem_1_buffer_param_a[0x20]; 1235 1236 u8 umem_1_buffer_param_b[0x20]; 1237 1238 u8 umem_2_buffer_param_a[0x20]; 1239 1240 u8 umem_2_buffer_param_b[0x20]; 1241 1242 u8 umem_3_buffer_param_a[0x20]; 1243 1244 u8 umem_3_buffer_param_b[0x20]; 1245 1246 u8 reserved_at_1c0[0x640]; 1247 }; 1248 1249 enum { 1250 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0, 1251 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2, 1252 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4, 1253 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8, 1254 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10, 1255 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20, 1256 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40, 1257 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80, 1258 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100, 1259 }; 1260 1261 enum { 1262 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1, 1263 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2, 1264 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4, 1265 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8, 1266 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10, 1267 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20, 1268 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40, 1269 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80, 1270 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100, 1271 }; 1272 1273 struct mlx5_ifc_atomic_caps_bits { 1274 u8 reserved_at_0[0x40]; 1275 1276 u8 atomic_req_8B_endianness_mode[0x2]; 1277 u8 reserved_at_42[0x4]; 1278 u8 supported_atomic_req_8B_endianness_mode_1[0x1]; 1279 1280 u8 reserved_at_47[0x19]; 1281 1282 u8 reserved_at_60[0x20]; 1283 1284 u8 reserved_at_80[0x10]; 1285 u8 atomic_operations[0x10]; 1286 1287 u8 reserved_at_a0[0x10]; 1288 u8 atomic_size_qp[0x10]; 1289 1290 u8 reserved_at_c0[0x10]; 1291 u8 atomic_size_dc[0x10]; 1292 1293 u8 reserved_at_e0[0x720]; 1294 }; 1295 1296 struct mlx5_ifc_odp_cap_bits { 1297 u8 reserved_at_0[0x40]; 1298 1299 u8 sig[0x1]; 1300 u8 reserved_at_41[0x1f]; 1301 1302 u8 reserved_at_60[0x20]; 1303 1304 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps; 1305 1306 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps; 1307 1308 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps; 1309 1310 struct mlx5_ifc_odp_per_transport_service_cap_bits xrc_odp_caps; 1311 1312 struct mlx5_ifc_odp_per_transport_service_cap_bits dc_odp_caps; 1313 1314 u8 reserved_at_120[0x6E0]; 1315 }; 1316 1317 struct mlx5_ifc_calc_op { 1318 u8 reserved_at_0[0x10]; 1319 u8 reserved_at_10[0x9]; 1320 u8 op_swap_endianness[0x1]; 1321 u8 op_min[0x1]; 1322 u8 op_xor[0x1]; 1323 u8 op_or[0x1]; 1324 u8 op_and[0x1]; 1325 u8 op_max[0x1]; 1326 u8 op_add[0x1]; 1327 }; 1328 1329 struct mlx5_ifc_vector_calc_cap_bits { 1330 u8 calc_matrix[0x1]; 1331 u8 reserved_at_1[0x1f]; 1332 u8 reserved_at_20[0x8]; 1333 u8 max_vec_count[0x8]; 1334 u8 reserved_at_30[0xd]; 1335 u8 max_chunk_size[0x3]; 1336 struct mlx5_ifc_calc_op calc0; 1337 struct mlx5_ifc_calc_op calc1; 1338 struct mlx5_ifc_calc_op calc2; 1339 struct mlx5_ifc_calc_op calc3; 1340 1341 u8 reserved_at_c0[0x720]; 1342 }; 1343 1344 struct mlx5_ifc_tls_cap_bits { 1345 u8 tls_1_2_aes_gcm_128[0x1]; 1346 u8 tls_1_3_aes_gcm_128[0x1]; 1347 u8 tls_1_2_aes_gcm_256[0x1]; 1348 u8 tls_1_3_aes_gcm_256[0x1]; 1349 u8 reserved_at_4[0x1c]; 1350 1351 u8 reserved_at_20[0x7e0]; 1352 }; 1353 1354 struct mlx5_ifc_ipsec_cap_bits { 1355 u8 ipsec_full_offload[0x1]; 1356 u8 ipsec_crypto_offload[0x1]; 1357 u8 ipsec_esn[0x1]; 1358 u8 ipsec_crypto_esp_aes_gcm_256_encrypt[0x1]; 1359 u8 ipsec_crypto_esp_aes_gcm_128_encrypt[0x1]; 1360 u8 ipsec_crypto_esp_aes_gcm_256_decrypt[0x1]; 1361 u8 ipsec_crypto_esp_aes_gcm_128_decrypt[0x1]; 1362 u8 reserved_at_7[0x4]; 1363 u8 log_max_ipsec_offload[0x5]; 1364 u8 reserved_at_10[0x10]; 1365 1366 u8 min_log_ipsec_full_replay_window[0x8]; 1367 u8 max_log_ipsec_full_replay_window[0x8]; 1368 u8 reserved_at_30[0x7d0]; 1369 }; 1370 1371 struct mlx5_ifc_macsec_cap_bits { 1372 u8 macsec_epn[0x1]; 1373 u8 reserved_at_1[0x2]; 1374 u8 macsec_crypto_esp_aes_gcm_256_encrypt[0x1]; 1375 u8 macsec_crypto_esp_aes_gcm_128_encrypt[0x1]; 1376 u8 macsec_crypto_esp_aes_gcm_256_decrypt[0x1]; 1377 u8 macsec_crypto_esp_aes_gcm_128_decrypt[0x1]; 1378 u8 reserved_at_7[0x4]; 1379 u8 log_max_macsec_offload[0x5]; 1380 u8 reserved_at_10[0x10]; 1381 1382 u8 min_log_macsec_full_replay_window[0x8]; 1383 u8 max_log_macsec_full_replay_window[0x8]; 1384 u8 reserved_at_30[0x10]; 1385 1386 u8 reserved_at_40[0x7c0]; 1387 }; 1388 1389 enum { 1390 MLX5_WQ_TYPE_LINKED_LIST = 0x0, 1391 MLX5_WQ_TYPE_CYCLIC = 0x1, 1392 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2, 1393 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3, 1394 }; 1395 1396 enum { 1397 MLX5_WQ_END_PAD_MODE_NONE = 0x0, 1398 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1, 1399 }; 1400 1401 enum { 1402 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0, 1403 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1, 1404 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2, 1405 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3, 1406 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4, 1407 }; 1408 1409 enum { 1410 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0, 1411 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1, 1412 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2, 1413 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3, 1414 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4, 1415 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5, 1416 }; 1417 1418 enum { 1419 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0, 1420 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1, 1421 }; 1422 1423 enum { 1424 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0, 1425 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1, 1426 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3, 1427 }; 1428 1429 enum { 1430 MLX5_CAP_PORT_TYPE_IB = 0x0, 1431 MLX5_CAP_PORT_TYPE_ETH = 0x1, 1432 }; 1433 1434 enum { 1435 MLX5_CAP_UMR_FENCE_STRONG = 0x0, 1436 MLX5_CAP_UMR_FENCE_SMALL = 0x1, 1437 MLX5_CAP_UMR_FENCE_NONE = 0x2, 1438 }; 1439 1440 enum { 1441 MLX5_FLEX_PARSER_GENEVE_ENABLED = 1 << 3, 1442 MLX5_FLEX_PARSER_MPLS_OVER_GRE_ENABLED = 1 << 4, 1443 MLX5_FLEX_PARSER_MPLS_OVER_UDP_ENABLED = 1 << 5, 1444 MLX5_FLEX_PARSER_VXLAN_GPE_ENABLED = 1 << 7, 1445 MLX5_FLEX_PARSER_ICMP_V4_ENABLED = 1 << 8, 1446 MLX5_FLEX_PARSER_ICMP_V6_ENABLED = 1 << 9, 1447 MLX5_FLEX_PARSER_GENEVE_TLV_OPTION_0_ENABLED = 1 << 10, 1448 MLX5_FLEX_PARSER_GTPU_ENABLED = 1 << 11, 1449 MLX5_FLEX_PARSER_GTPU_DW_2_ENABLED = 1 << 16, 1450 MLX5_FLEX_PARSER_GTPU_FIRST_EXT_DW_0_ENABLED = 1 << 17, 1451 MLX5_FLEX_PARSER_GTPU_DW_0_ENABLED = 1 << 18, 1452 MLX5_FLEX_PARSER_GTPU_TEID_ENABLED = 1 << 19, 1453 }; 1454 1455 enum { 1456 MLX5_UCTX_CAP_RAW_TX = 1UL << 0, 1457 MLX5_UCTX_CAP_INTERNAL_DEV_RES = 1UL << 1, 1458 }; 1459 1460 #define MLX5_FC_BULK_SIZE_FACTOR 128 1461 1462 enum mlx5_fc_bulk_alloc_bitmask { 1463 MLX5_FC_BULK_128 = (1 << 0), 1464 MLX5_FC_BULK_256 = (1 << 1), 1465 MLX5_FC_BULK_512 = (1 << 2), 1466 MLX5_FC_BULK_1024 = (1 << 3), 1467 MLX5_FC_BULK_2048 = (1 << 4), 1468 MLX5_FC_BULK_4096 = (1 << 5), 1469 MLX5_FC_BULK_8192 = (1 << 6), 1470 MLX5_FC_BULK_16384 = (1 << 7), 1471 }; 1472 1473 #define MLX5_FC_BULK_NUM_FCS(fc_enum) (MLX5_FC_BULK_SIZE_FACTOR * (fc_enum)) 1474 1475 #define MLX5_FT_MAX_MULTIPATH_LEVEL 63 1476 1477 enum { 1478 MLX5_STEERING_FORMAT_CONNECTX_5 = 0, 1479 MLX5_STEERING_FORMAT_CONNECTX_6DX = 1, 1480 MLX5_STEERING_FORMAT_CONNECTX_7 = 2, 1481 }; 1482 1483 struct mlx5_ifc_cmd_hca_cap_bits { 1484 u8 reserved_at_0[0x10]; 1485 u8 shared_object_to_user_object_allowed[0x1]; 1486 u8 reserved_at_13[0xe]; 1487 u8 vhca_resource_manager[0x1]; 1488 1489 u8 hca_cap_2[0x1]; 1490 u8 create_lag_when_not_master_up[0x1]; 1491 u8 dtor[0x1]; 1492 u8 event_on_vhca_state_teardown_request[0x1]; 1493 u8 event_on_vhca_state_in_use[0x1]; 1494 u8 event_on_vhca_state_active[0x1]; 1495 u8 event_on_vhca_state_allocated[0x1]; 1496 u8 event_on_vhca_state_invalid[0x1]; 1497 u8 reserved_at_28[0x8]; 1498 u8 vhca_id[0x10]; 1499 1500 u8 reserved_at_40[0x40]; 1501 1502 u8 log_max_srq_sz[0x8]; 1503 u8 log_max_qp_sz[0x8]; 1504 u8 event_cap[0x1]; 1505 u8 reserved_at_91[0x2]; 1506 u8 isolate_vl_tc_new[0x1]; 1507 u8 reserved_at_94[0x4]; 1508 u8 prio_tag_required[0x1]; 1509 u8 reserved_at_99[0x2]; 1510 u8 log_max_qp[0x5]; 1511 1512 u8 reserved_at_a0[0x3]; 1513 u8 ece_support[0x1]; 1514 u8 reserved_at_a4[0x5]; 1515 u8 reg_c_preserve[0x1]; 1516 u8 reserved_at_aa[0x1]; 1517 u8 log_max_srq[0x5]; 1518 u8 reserved_at_b0[0x1]; 1519 u8 uplink_follow[0x1]; 1520 u8 ts_cqe_to_dest_cqn[0x1]; 1521 u8 reserved_at_b3[0x6]; 1522 u8 go_back_n[0x1]; 1523 u8 shampo[0x1]; 1524 u8 reserved_at_bb[0x5]; 1525 1526 u8 max_sgl_for_optimized_performance[0x8]; 1527 u8 log_max_cq_sz[0x8]; 1528 u8 relaxed_ordering_write_umr[0x1]; 1529 u8 relaxed_ordering_read_umr[0x1]; 1530 u8 reserved_at_d2[0x7]; 1531 u8 virtio_net_device_emualtion_manager[0x1]; 1532 u8 virtio_blk_device_emualtion_manager[0x1]; 1533 u8 log_max_cq[0x5]; 1534 1535 u8 log_max_eq_sz[0x8]; 1536 u8 relaxed_ordering_write[0x1]; 1537 u8 relaxed_ordering_read_pci_enabled[0x1]; 1538 u8 log_max_mkey[0x6]; 1539 u8 reserved_at_f0[0x6]; 1540 u8 terminate_scatter_list_mkey[0x1]; 1541 u8 repeated_mkey[0x1]; 1542 u8 dump_fill_mkey[0x1]; 1543 u8 reserved_at_f9[0x2]; 1544 u8 fast_teardown[0x1]; 1545 u8 log_max_eq[0x4]; 1546 1547 u8 max_indirection[0x8]; 1548 u8 fixed_buffer_size[0x1]; 1549 u8 log_max_mrw_sz[0x7]; 1550 u8 force_teardown[0x1]; 1551 u8 reserved_at_111[0x1]; 1552 u8 log_max_bsf_list_size[0x6]; 1553 u8 umr_extended_translation_offset[0x1]; 1554 u8 null_mkey[0x1]; 1555 u8 log_max_klm_list_size[0x6]; 1556 1557 u8 reserved_at_120[0x2]; 1558 u8 qpc_extension[0x1]; 1559 u8 reserved_at_123[0x7]; 1560 u8 log_max_ra_req_dc[0x6]; 1561 u8 reserved_at_130[0x2]; 1562 u8 eth_wqe_too_small[0x1]; 1563 u8 reserved_at_133[0x6]; 1564 u8 vnic_env_cq_overrun[0x1]; 1565 u8 log_max_ra_res_dc[0x6]; 1566 1567 u8 reserved_at_140[0x5]; 1568 u8 release_all_pages[0x1]; 1569 u8 must_not_use[0x1]; 1570 u8 reserved_at_147[0x2]; 1571 u8 roce_accl[0x1]; 1572 u8 log_max_ra_req_qp[0x6]; 1573 u8 reserved_at_150[0xa]; 1574 u8 log_max_ra_res_qp[0x6]; 1575 1576 u8 end_pad[0x1]; 1577 u8 cc_query_allowed[0x1]; 1578 u8 cc_modify_allowed[0x1]; 1579 u8 start_pad[0x1]; 1580 u8 cache_line_128byte[0x1]; 1581 u8 reserved_at_165[0x4]; 1582 u8 rts2rts_qp_counters_set_id[0x1]; 1583 u8 reserved_at_16a[0x2]; 1584 u8 vnic_env_int_rq_oob[0x1]; 1585 u8 sbcam_reg[0x1]; 1586 u8 reserved_at_16e[0x1]; 1587 u8 qcam_reg[0x1]; 1588 u8 gid_table_size[0x10]; 1589 1590 u8 out_of_seq_cnt[0x1]; 1591 u8 vport_counters[0x1]; 1592 u8 retransmission_q_counters[0x1]; 1593 u8 debug[0x1]; 1594 u8 modify_rq_counter_set_id[0x1]; 1595 u8 rq_delay_drop[0x1]; 1596 u8 max_qp_cnt[0xa]; 1597 u8 pkey_table_size[0x10]; 1598 1599 u8 vport_group_manager[0x1]; 1600 u8 vhca_group_manager[0x1]; 1601 u8 ib_virt[0x1]; 1602 u8 eth_virt[0x1]; 1603 u8 vnic_env_queue_counters[0x1]; 1604 u8 ets[0x1]; 1605 u8 nic_flow_table[0x1]; 1606 u8 eswitch_manager[0x1]; 1607 u8 device_memory[0x1]; 1608 u8 mcam_reg[0x1]; 1609 u8 pcam_reg[0x1]; 1610 u8 local_ca_ack_delay[0x5]; 1611 u8 port_module_event[0x1]; 1612 u8 enhanced_error_q_counters[0x1]; 1613 u8 ports_check[0x1]; 1614 u8 reserved_at_1b3[0x1]; 1615 u8 disable_link_up[0x1]; 1616 u8 beacon_led[0x1]; 1617 u8 port_type[0x2]; 1618 u8 num_ports[0x8]; 1619 1620 u8 reserved_at_1c0[0x1]; 1621 u8 pps[0x1]; 1622 u8 pps_modify[0x1]; 1623 u8 log_max_msg[0x5]; 1624 u8 reserved_at_1c8[0x4]; 1625 u8 max_tc[0x4]; 1626 u8 temp_warn_event[0x1]; 1627 u8 dcbx[0x1]; 1628 u8 general_notification_event[0x1]; 1629 u8 reserved_at_1d3[0x2]; 1630 u8 fpga[0x1]; 1631 u8 rol_s[0x1]; 1632 u8 rol_g[0x1]; 1633 u8 reserved_at_1d8[0x1]; 1634 u8 wol_s[0x1]; 1635 u8 wol_g[0x1]; 1636 u8 wol_a[0x1]; 1637 u8 wol_b[0x1]; 1638 u8 wol_m[0x1]; 1639 u8 wol_u[0x1]; 1640 u8 wol_p[0x1]; 1641 1642 u8 stat_rate_support[0x10]; 1643 u8 reserved_at_1f0[0x1]; 1644 u8 pci_sync_for_fw_update_event[0x1]; 1645 u8 reserved_at_1f2[0x6]; 1646 u8 init2_lag_tx_port_affinity[0x1]; 1647 u8 reserved_at_1fa[0x3]; 1648 u8 cqe_version[0x4]; 1649 1650 u8 compact_address_vector[0x1]; 1651 u8 striding_rq[0x1]; 1652 u8 reserved_at_202[0x1]; 1653 u8 ipoib_enhanced_offloads[0x1]; 1654 u8 ipoib_basic_offloads[0x1]; 1655 u8 reserved_at_205[0x1]; 1656 u8 repeated_block_disabled[0x1]; 1657 u8 umr_modify_entity_size_disabled[0x1]; 1658 u8 umr_modify_atomic_disabled[0x1]; 1659 u8 umr_indirect_mkey_disabled[0x1]; 1660 u8 umr_fence[0x2]; 1661 u8 dc_req_scat_data_cqe[0x1]; 1662 u8 reserved_at_20d[0x2]; 1663 u8 drain_sigerr[0x1]; 1664 u8 cmdif_checksum[0x2]; 1665 u8 sigerr_cqe[0x1]; 1666 u8 reserved_at_213[0x1]; 1667 u8 wq_signature[0x1]; 1668 u8 sctr_data_cqe[0x1]; 1669 u8 reserved_at_216[0x1]; 1670 u8 sho[0x1]; 1671 u8 tph[0x1]; 1672 u8 rf[0x1]; 1673 u8 dct[0x1]; 1674 u8 qos[0x1]; 1675 u8 eth_net_offloads[0x1]; 1676 u8 roce[0x1]; 1677 u8 atomic[0x1]; 1678 u8 reserved_at_21f[0x1]; 1679 1680 u8 cq_oi[0x1]; 1681 u8 cq_resize[0x1]; 1682 u8 cq_moderation[0x1]; 1683 u8 reserved_at_223[0x3]; 1684 u8 cq_eq_remap[0x1]; 1685 u8 pg[0x1]; 1686 u8 block_lb_mc[0x1]; 1687 u8 reserved_at_229[0x1]; 1688 u8 scqe_break_moderation[0x1]; 1689 u8 cq_period_start_from_cqe[0x1]; 1690 u8 cd[0x1]; 1691 u8 reserved_at_22d[0x1]; 1692 u8 apm[0x1]; 1693 u8 vector_calc[0x1]; 1694 u8 umr_ptr_rlky[0x1]; 1695 u8 imaicl[0x1]; 1696 u8 qp_packet_based[0x1]; 1697 u8 reserved_at_233[0x3]; 1698 u8 qkv[0x1]; 1699 u8 pkv[0x1]; 1700 u8 set_deth_sqpn[0x1]; 1701 u8 reserved_at_239[0x3]; 1702 u8 xrc[0x1]; 1703 u8 ud[0x1]; 1704 u8 uc[0x1]; 1705 u8 rc[0x1]; 1706 1707 u8 uar_4k[0x1]; 1708 u8 reserved_at_241[0x7]; 1709 u8 fl_rc_qp_when_roce_disabled[0x1]; 1710 u8 regexp_params[0x1]; 1711 u8 uar_sz[0x6]; 1712 u8 port_selection_cap[0x1]; 1713 u8 reserved_at_248[0x1]; 1714 u8 umem_uid_0[0x1]; 1715 u8 reserved_at_250[0x5]; 1716 u8 log_pg_sz[0x8]; 1717 1718 u8 bf[0x1]; 1719 u8 driver_version[0x1]; 1720 u8 pad_tx_eth_packet[0x1]; 1721 u8 reserved_at_263[0x3]; 1722 u8 mkey_by_name[0x1]; 1723 u8 reserved_at_267[0x4]; 1724 1725 u8 log_bf_reg_size[0x5]; 1726 1727 u8 reserved_at_270[0x3]; 1728 u8 qp_error_syndrome[0x1]; 1729 u8 reserved_at_274[0x2]; 1730 u8 lag_dct[0x2]; 1731 u8 lag_tx_port_affinity[0x1]; 1732 u8 lag_native_fdb_selection[0x1]; 1733 u8 reserved_at_27a[0x1]; 1734 u8 lag_master[0x1]; 1735 u8 num_lag_ports[0x4]; 1736 1737 u8 reserved_at_280[0x10]; 1738 u8 max_wqe_sz_sq[0x10]; 1739 1740 u8 reserved_at_2a0[0x10]; 1741 u8 max_wqe_sz_rq[0x10]; 1742 1743 u8 max_flow_counter_31_16[0x10]; 1744 u8 max_wqe_sz_sq_dc[0x10]; 1745 1746 u8 reserved_at_2e0[0x7]; 1747 u8 max_qp_mcg[0x19]; 1748 1749 u8 reserved_at_300[0x10]; 1750 u8 flow_counter_bulk_alloc[0x8]; 1751 u8 log_max_mcg[0x8]; 1752 1753 u8 reserved_at_320[0x3]; 1754 u8 log_max_transport_domain[0x5]; 1755 u8 reserved_at_328[0x2]; 1756 u8 relaxed_ordering_read[0x1]; 1757 u8 log_max_pd[0x5]; 1758 u8 reserved_at_330[0x7]; 1759 u8 vnic_env_cnt_steering_fail[0x1]; 1760 u8 reserved_at_338[0x1]; 1761 u8 q_counter_aggregation[0x1]; 1762 u8 q_counter_other_vport[0x1]; 1763 u8 log_max_xrcd[0x5]; 1764 1765 u8 nic_receive_steering_discard[0x1]; 1766 u8 receive_discard_vport_down[0x1]; 1767 u8 transmit_discard_vport_down[0x1]; 1768 u8 eq_overrun_count[0x1]; 1769 u8 reserved_at_344[0x1]; 1770 u8 invalid_command_count[0x1]; 1771 u8 quota_exceeded_count[0x1]; 1772 u8 reserved_at_347[0x1]; 1773 u8 log_max_flow_counter_bulk[0x8]; 1774 u8 max_flow_counter_15_0[0x10]; 1775 1776 1777 u8 reserved_at_360[0x3]; 1778 u8 log_max_rq[0x5]; 1779 u8 reserved_at_368[0x3]; 1780 u8 log_max_sq[0x5]; 1781 u8 reserved_at_370[0x3]; 1782 u8 log_max_tir[0x5]; 1783 u8 reserved_at_378[0x3]; 1784 u8 log_max_tis[0x5]; 1785 1786 u8 basic_cyclic_rcv_wqe[0x1]; 1787 u8 reserved_at_381[0x2]; 1788 u8 log_max_rmp[0x5]; 1789 u8 reserved_at_388[0x3]; 1790 u8 log_max_rqt[0x5]; 1791 u8 reserved_at_390[0x3]; 1792 u8 log_max_rqt_size[0x5]; 1793 u8 reserved_at_398[0x3]; 1794 u8 log_max_tis_per_sq[0x5]; 1795 1796 u8 ext_stride_num_range[0x1]; 1797 u8 roce_rw_supported[0x1]; 1798 u8 log_max_current_uc_list_wr_supported[0x1]; 1799 u8 log_max_stride_sz_rq[0x5]; 1800 u8 reserved_at_3a8[0x3]; 1801 u8 log_min_stride_sz_rq[0x5]; 1802 u8 reserved_at_3b0[0x3]; 1803 u8 log_max_stride_sz_sq[0x5]; 1804 u8 reserved_at_3b8[0x3]; 1805 u8 log_min_stride_sz_sq[0x5]; 1806 1807 u8 hairpin[0x1]; 1808 u8 reserved_at_3c1[0x2]; 1809 u8 log_max_hairpin_queues[0x5]; 1810 u8 reserved_at_3c8[0x3]; 1811 u8 log_max_hairpin_wq_data_sz[0x5]; 1812 u8 reserved_at_3d0[0x3]; 1813 u8 log_max_hairpin_num_packets[0x5]; 1814 u8 reserved_at_3d8[0x3]; 1815 u8 log_max_wq_sz[0x5]; 1816 1817 u8 nic_vport_change_event[0x1]; 1818 u8 disable_local_lb_uc[0x1]; 1819 u8 disable_local_lb_mc[0x1]; 1820 u8 log_min_hairpin_wq_data_sz[0x5]; 1821 u8 reserved_at_3e8[0x2]; 1822 u8 vhca_state[0x1]; 1823 u8 log_max_vlan_list[0x5]; 1824 u8 reserved_at_3f0[0x3]; 1825 u8 log_max_current_mc_list[0x5]; 1826 u8 reserved_at_3f8[0x3]; 1827 u8 log_max_current_uc_list[0x5]; 1828 1829 u8 general_obj_types[0x40]; 1830 1831 u8 sq_ts_format[0x2]; 1832 u8 rq_ts_format[0x2]; 1833 u8 steering_format_version[0x4]; 1834 u8 create_qp_start_hint[0x18]; 1835 1836 u8 reserved_at_460[0x1]; 1837 u8 ats[0x1]; 1838 u8 reserved_at_462[0x1]; 1839 u8 log_max_uctx[0x5]; 1840 u8 reserved_at_468[0x1]; 1841 u8 crypto[0x1]; 1842 u8 ipsec_offload[0x1]; 1843 u8 log_max_umem[0x5]; 1844 u8 max_num_eqs[0x10]; 1845 1846 u8 reserved_at_480[0x1]; 1847 u8 tls_tx[0x1]; 1848 u8 tls_rx[0x1]; 1849 u8 log_max_l2_table[0x5]; 1850 u8 reserved_at_488[0x8]; 1851 u8 log_uar_page_sz[0x10]; 1852 1853 u8 reserved_at_4a0[0x20]; 1854 u8 device_frequency_mhz[0x20]; 1855 u8 device_frequency_khz[0x20]; 1856 1857 u8 reserved_at_500[0x20]; 1858 u8 num_of_uars_per_page[0x20]; 1859 1860 u8 flex_parser_protocols[0x20]; 1861 1862 u8 max_geneve_tlv_options[0x8]; 1863 u8 reserved_at_568[0x3]; 1864 u8 max_geneve_tlv_option_data_len[0x5]; 1865 u8 reserved_at_570[0x9]; 1866 u8 adv_virtualization[0x1]; 1867 u8 reserved_at_57a[0x6]; 1868 1869 u8 reserved_at_580[0xb]; 1870 u8 log_max_dci_stream_channels[0x5]; 1871 u8 reserved_at_590[0x3]; 1872 u8 log_max_dci_errored_streams[0x5]; 1873 u8 reserved_at_598[0x8]; 1874 1875 u8 reserved_at_5a0[0x10]; 1876 u8 enhanced_cqe_compression[0x1]; 1877 u8 reserved_at_5b1[0x2]; 1878 u8 log_max_dek[0x5]; 1879 u8 reserved_at_5b8[0x4]; 1880 u8 mini_cqe_resp_stride_index[0x1]; 1881 u8 cqe_128_always[0x1]; 1882 u8 cqe_compression_128[0x1]; 1883 u8 cqe_compression[0x1]; 1884 1885 u8 cqe_compression_timeout[0x10]; 1886 u8 cqe_compression_max_num[0x10]; 1887 1888 u8 reserved_at_5e0[0x8]; 1889 u8 flex_parser_id_gtpu_dw_0[0x4]; 1890 u8 reserved_at_5ec[0x4]; 1891 u8 tag_matching[0x1]; 1892 u8 rndv_offload_rc[0x1]; 1893 u8 rndv_offload_dc[0x1]; 1894 u8 log_tag_matching_list_sz[0x5]; 1895 u8 reserved_at_5f8[0x3]; 1896 u8 log_max_xrq[0x5]; 1897 1898 u8 affiliate_nic_vport_criteria[0x8]; 1899 u8 native_port_num[0x8]; 1900 u8 num_vhca_ports[0x8]; 1901 u8 flex_parser_id_gtpu_teid[0x4]; 1902 u8 reserved_at_61c[0x2]; 1903 u8 sw_owner_id[0x1]; 1904 u8 reserved_at_61f[0x1]; 1905 1906 u8 max_num_of_monitor_counters[0x10]; 1907 u8 num_ppcnt_monitor_counters[0x10]; 1908 1909 u8 max_num_sf[0x10]; 1910 u8 num_q_monitor_counters[0x10]; 1911 1912 u8 reserved_at_660[0x20]; 1913 1914 u8 sf[0x1]; 1915 u8 sf_set_partition[0x1]; 1916 u8 reserved_at_682[0x1]; 1917 u8 log_max_sf[0x5]; 1918 u8 apu[0x1]; 1919 u8 reserved_at_689[0x4]; 1920 u8 migration[0x1]; 1921 u8 reserved_at_68e[0x2]; 1922 u8 log_min_sf_size[0x8]; 1923 u8 max_num_sf_partitions[0x8]; 1924 1925 u8 uctx_cap[0x20]; 1926 1927 u8 reserved_at_6c0[0x4]; 1928 u8 flex_parser_id_geneve_tlv_option_0[0x4]; 1929 u8 flex_parser_id_icmp_dw1[0x4]; 1930 u8 flex_parser_id_icmp_dw0[0x4]; 1931 u8 flex_parser_id_icmpv6_dw1[0x4]; 1932 u8 flex_parser_id_icmpv6_dw0[0x4]; 1933 u8 flex_parser_id_outer_first_mpls_over_gre[0x4]; 1934 u8 flex_parser_id_outer_first_mpls_over_udp_label[0x4]; 1935 1936 u8 max_num_match_definer[0x10]; 1937 u8 sf_base_id[0x10]; 1938 1939 u8 flex_parser_id_gtpu_dw_2[0x4]; 1940 u8 flex_parser_id_gtpu_first_ext_dw_0[0x4]; 1941 u8 num_total_dynamic_vf_msix[0x18]; 1942 u8 reserved_at_720[0x14]; 1943 u8 dynamic_msix_table_size[0xc]; 1944 u8 reserved_at_740[0xc]; 1945 u8 min_dynamic_vf_msix_table_size[0x4]; 1946 u8 reserved_at_750[0x4]; 1947 u8 max_dynamic_vf_msix_table_size[0xc]; 1948 1949 u8 reserved_at_760[0x3]; 1950 u8 log_max_num_header_modify_argument[0x5]; 1951 u8 reserved_at_768[0x4]; 1952 u8 log_header_modify_argument_granularity[0x4]; 1953 u8 reserved_at_770[0x3]; 1954 u8 log_header_modify_argument_max_alloc[0x5]; 1955 u8 reserved_at_778[0x8]; 1956 1957 u8 vhca_tunnel_commands[0x40]; 1958 u8 match_definer_format_supported[0x40]; 1959 }; 1960 1961 struct mlx5_ifc_cmd_hca_cap_2_bits { 1962 u8 reserved_at_0[0x80]; 1963 1964 u8 migratable[0x1]; 1965 u8 reserved_at_81[0x1f]; 1966 1967 u8 max_reformat_insert_size[0x8]; 1968 u8 max_reformat_insert_offset[0x8]; 1969 u8 max_reformat_remove_size[0x8]; 1970 u8 max_reformat_remove_offset[0x8]; 1971 1972 u8 reserved_at_c0[0x8]; 1973 u8 migration_multi_load[0x1]; 1974 u8 migration_tracking_state[0x1]; 1975 u8 reserved_at_ca[0x16]; 1976 1977 u8 reserved_at_e0[0xc0]; 1978 1979 u8 flow_table_type_2_type[0x8]; 1980 u8 reserved_at_1a8[0x3]; 1981 u8 log_min_mkey_entity_size[0x5]; 1982 u8 reserved_at_1b0[0x10]; 1983 1984 u8 reserved_at_1c0[0x60]; 1985 1986 u8 reserved_at_220[0x1]; 1987 u8 sw_vhca_id_valid[0x1]; 1988 u8 sw_vhca_id[0xe]; 1989 u8 reserved_at_230[0x10]; 1990 1991 u8 reserved_at_240[0xb]; 1992 u8 ts_cqe_metadata_size2wqe_counter[0x5]; 1993 u8 reserved_at_250[0x10]; 1994 1995 u8 reserved_at_260[0x5a0]; 1996 }; 1997 1998 enum mlx5_ifc_flow_destination_type { 1999 MLX5_IFC_FLOW_DESTINATION_TYPE_VPORT = 0x0, 2000 MLX5_IFC_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1, 2001 MLX5_IFC_FLOW_DESTINATION_TYPE_TIR = 0x2, 2002 MLX5_IFC_FLOW_DESTINATION_TYPE_FLOW_SAMPLER = 0x6, 2003 MLX5_IFC_FLOW_DESTINATION_TYPE_UPLINK = 0x8, 2004 MLX5_IFC_FLOW_DESTINATION_TYPE_TABLE_TYPE = 0xA, 2005 }; 2006 2007 enum mlx5_flow_table_miss_action { 2008 MLX5_FLOW_TABLE_MISS_ACTION_DEF, 2009 MLX5_FLOW_TABLE_MISS_ACTION_FWD, 2010 MLX5_FLOW_TABLE_MISS_ACTION_SWITCH_DOMAIN, 2011 }; 2012 2013 struct mlx5_ifc_dest_format_struct_bits { 2014 u8 destination_type[0x8]; 2015 u8 destination_id[0x18]; 2016 2017 u8 destination_eswitch_owner_vhca_id_valid[0x1]; 2018 u8 packet_reformat[0x1]; 2019 u8 reserved_at_22[0x6]; 2020 u8 destination_table_type[0x8]; 2021 u8 destination_eswitch_owner_vhca_id[0x10]; 2022 }; 2023 2024 struct mlx5_ifc_flow_counter_list_bits { 2025 u8 flow_counter_id[0x20]; 2026 2027 u8 reserved_at_20[0x20]; 2028 }; 2029 2030 struct mlx5_ifc_extended_dest_format_bits { 2031 struct mlx5_ifc_dest_format_struct_bits destination_entry; 2032 2033 u8 packet_reformat_id[0x20]; 2034 2035 u8 reserved_at_60[0x20]; 2036 }; 2037 2038 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits { 2039 struct mlx5_ifc_extended_dest_format_bits extended_dest_format; 2040 struct mlx5_ifc_flow_counter_list_bits flow_counter_list; 2041 }; 2042 2043 struct mlx5_ifc_fte_match_param_bits { 2044 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers; 2045 2046 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters; 2047 2048 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers; 2049 2050 struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2; 2051 2052 struct mlx5_ifc_fte_match_set_misc3_bits misc_parameters_3; 2053 2054 struct mlx5_ifc_fte_match_set_misc4_bits misc_parameters_4; 2055 2056 struct mlx5_ifc_fte_match_set_misc5_bits misc_parameters_5; 2057 2058 u8 reserved_at_e00[0x200]; 2059 }; 2060 2061 enum { 2062 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0, 2063 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1, 2064 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2, 2065 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3, 2066 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4, 2067 }; 2068 2069 struct mlx5_ifc_rx_hash_field_select_bits { 2070 u8 l3_prot_type[0x1]; 2071 u8 l4_prot_type[0x1]; 2072 u8 selected_fields[0x1e]; 2073 }; 2074 2075 enum { 2076 MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0, 2077 MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1, 2078 }; 2079 2080 enum { 2081 MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0, 2082 MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1, 2083 }; 2084 2085 struct mlx5_ifc_wq_bits { 2086 u8 wq_type[0x4]; 2087 u8 wq_signature[0x1]; 2088 u8 end_padding_mode[0x2]; 2089 u8 cd_slave[0x1]; 2090 u8 reserved_at_8[0x18]; 2091 2092 u8 hds_skip_first_sge[0x1]; 2093 u8 log2_hds_buf_size[0x3]; 2094 u8 reserved_at_24[0x7]; 2095 u8 page_offset[0x5]; 2096 u8 lwm[0x10]; 2097 2098 u8 reserved_at_40[0x8]; 2099 u8 pd[0x18]; 2100 2101 u8 reserved_at_60[0x8]; 2102 u8 uar_page[0x18]; 2103 2104 u8 dbr_addr[0x40]; 2105 2106 u8 hw_counter[0x20]; 2107 2108 u8 sw_counter[0x20]; 2109 2110 u8 reserved_at_100[0xc]; 2111 u8 log_wq_stride[0x4]; 2112 u8 reserved_at_110[0x3]; 2113 u8 log_wq_pg_sz[0x5]; 2114 u8 reserved_at_118[0x3]; 2115 u8 log_wq_sz[0x5]; 2116 2117 u8 dbr_umem_valid[0x1]; 2118 u8 wq_umem_valid[0x1]; 2119 u8 reserved_at_122[0x1]; 2120 u8 log_hairpin_num_packets[0x5]; 2121 u8 reserved_at_128[0x3]; 2122 u8 log_hairpin_data_sz[0x5]; 2123 2124 u8 reserved_at_130[0x4]; 2125 u8 log_wqe_num_of_strides[0x4]; 2126 u8 two_byte_shift_en[0x1]; 2127 u8 reserved_at_139[0x4]; 2128 u8 log_wqe_stride_size[0x3]; 2129 2130 u8 reserved_at_140[0x80]; 2131 2132 u8 headers_mkey[0x20]; 2133 2134 u8 shampo_enable[0x1]; 2135 u8 reserved_at_1e1[0x4]; 2136 u8 log_reservation_size[0x3]; 2137 u8 reserved_at_1e8[0x5]; 2138 u8 log_max_num_of_packets_per_reservation[0x3]; 2139 u8 reserved_at_1f0[0x6]; 2140 u8 log_headers_entry_size[0x2]; 2141 u8 reserved_at_1f8[0x4]; 2142 u8 log_headers_buffer_entry_num[0x4]; 2143 2144 u8 reserved_at_200[0x400]; 2145 2146 struct mlx5_ifc_cmd_pas_bits pas[]; 2147 }; 2148 2149 struct mlx5_ifc_rq_num_bits { 2150 u8 reserved_at_0[0x8]; 2151 u8 rq_num[0x18]; 2152 }; 2153 2154 struct mlx5_ifc_mac_address_layout_bits { 2155 u8 reserved_at_0[0x10]; 2156 u8 mac_addr_47_32[0x10]; 2157 2158 u8 mac_addr_31_0[0x20]; 2159 }; 2160 2161 struct mlx5_ifc_vlan_layout_bits { 2162 u8 reserved_at_0[0x14]; 2163 u8 vlan[0x0c]; 2164 2165 u8 reserved_at_20[0x20]; 2166 }; 2167 2168 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits { 2169 u8 reserved_at_0[0xa0]; 2170 2171 u8 min_time_between_cnps[0x20]; 2172 2173 u8 reserved_at_c0[0x12]; 2174 u8 cnp_dscp[0x6]; 2175 u8 reserved_at_d8[0x4]; 2176 u8 cnp_prio_mode[0x1]; 2177 u8 cnp_802p_prio[0x3]; 2178 2179 u8 reserved_at_e0[0x720]; 2180 }; 2181 2182 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits { 2183 u8 reserved_at_0[0x60]; 2184 2185 u8 reserved_at_60[0x4]; 2186 u8 clamp_tgt_rate[0x1]; 2187 u8 reserved_at_65[0x3]; 2188 u8 clamp_tgt_rate_after_time_inc[0x1]; 2189 u8 reserved_at_69[0x17]; 2190 2191 u8 reserved_at_80[0x20]; 2192 2193 u8 rpg_time_reset[0x20]; 2194 2195 u8 rpg_byte_reset[0x20]; 2196 2197 u8 rpg_threshold[0x20]; 2198 2199 u8 rpg_max_rate[0x20]; 2200 2201 u8 rpg_ai_rate[0x20]; 2202 2203 u8 rpg_hai_rate[0x20]; 2204 2205 u8 rpg_gd[0x20]; 2206 2207 u8 rpg_min_dec_fac[0x20]; 2208 2209 u8 rpg_min_rate[0x20]; 2210 2211 u8 reserved_at_1c0[0xe0]; 2212 2213 u8 rate_to_set_on_first_cnp[0x20]; 2214 2215 u8 dce_tcp_g[0x20]; 2216 2217 u8 dce_tcp_rtt[0x20]; 2218 2219 u8 rate_reduce_monitor_period[0x20]; 2220 2221 u8 reserved_at_320[0x20]; 2222 2223 u8 initial_alpha_value[0x20]; 2224 2225 u8 reserved_at_360[0x4a0]; 2226 }; 2227 2228 struct mlx5_ifc_cong_control_r_roce_general_bits { 2229 u8 reserved_at_0[0x80]; 2230 2231 u8 reserved_at_80[0x10]; 2232 u8 rtt_resp_dscp_valid[0x1]; 2233 u8 reserved_at_91[0x9]; 2234 u8 rtt_resp_dscp[0x6]; 2235 2236 u8 reserved_at_a0[0x760]; 2237 }; 2238 2239 struct mlx5_ifc_cong_control_802_1qau_rp_bits { 2240 u8 reserved_at_0[0x80]; 2241 2242 u8 rppp_max_rps[0x20]; 2243 2244 u8 rpg_time_reset[0x20]; 2245 2246 u8 rpg_byte_reset[0x20]; 2247 2248 u8 rpg_threshold[0x20]; 2249 2250 u8 rpg_max_rate[0x20]; 2251 2252 u8 rpg_ai_rate[0x20]; 2253 2254 u8 rpg_hai_rate[0x20]; 2255 2256 u8 rpg_gd[0x20]; 2257 2258 u8 rpg_min_dec_fac[0x20]; 2259 2260 u8 rpg_min_rate[0x20]; 2261 2262 u8 reserved_at_1c0[0x640]; 2263 }; 2264 2265 enum { 2266 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1, 2267 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2, 2268 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4, 2269 }; 2270 2271 struct mlx5_ifc_resize_field_select_bits { 2272 u8 resize_field_select[0x20]; 2273 }; 2274 2275 struct mlx5_ifc_resource_dump_bits { 2276 u8 more_dump[0x1]; 2277 u8 inline_dump[0x1]; 2278 u8 reserved_at_2[0xa]; 2279 u8 seq_num[0x4]; 2280 u8 segment_type[0x10]; 2281 2282 u8 reserved_at_20[0x10]; 2283 u8 vhca_id[0x10]; 2284 2285 u8 index1[0x20]; 2286 2287 u8 index2[0x20]; 2288 2289 u8 num_of_obj1[0x10]; 2290 u8 num_of_obj2[0x10]; 2291 2292 u8 reserved_at_a0[0x20]; 2293 2294 u8 device_opaque[0x40]; 2295 2296 u8 mkey[0x20]; 2297 2298 u8 size[0x20]; 2299 2300 u8 address[0x40]; 2301 2302 u8 inline_data[52][0x20]; 2303 }; 2304 2305 struct mlx5_ifc_resource_dump_menu_record_bits { 2306 u8 reserved_at_0[0x4]; 2307 u8 num_of_obj2_supports_active[0x1]; 2308 u8 num_of_obj2_supports_all[0x1]; 2309 u8 must_have_num_of_obj2[0x1]; 2310 u8 support_num_of_obj2[0x1]; 2311 u8 num_of_obj1_supports_active[0x1]; 2312 u8 num_of_obj1_supports_all[0x1]; 2313 u8 must_have_num_of_obj1[0x1]; 2314 u8 support_num_of_obj1[0x1]; 2315 u8 must_have_index2[0x1]; 2316 u8 support_index2[0x1]; 2317 u8 must_have_index1[0x1]; 2318 u8 support_index1[0x1]; 2319 u8 segment_type[0x10]; 2320 2321 u8 segment_name[4][0x20]; 2322 2323 u8 index1_name[4][0x20]; 2324 2325 u8 index2_name[4][0x20]; 2326 }; 2327 2328 struct mlx5_ifc_resource_dump_segment_header_bits { 2329 u8 length_dw[0x10]; 2330 u8 segment_type[0x10]; 2331 }; 2332 2333 struct mlx5_ifc_resource_dump_command_segment_bits { 2334 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2335 2336 u8 segment_called[0x10]; 2337 u8 vhca_id[0x10]; 2338 2339 u8 index1[0x20]; 2340 2341 u8 index2[0x20]; 2342 2343 u8 num_of_obj1[0x10]; 2344 u8 num_of_obj2[0x10]; 2345 }; 2346 2347 struct mlx5_ifc_resource_dump_error_segment_bits { 2348 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2349 2350 u8 reserved_at_20[0x10]; 2351 u8 syndrome_id[0x10]; 2352 2353 u8 reserved_at_40[0x40]; 2354 2355 u8 error[8][0x20]; 2356 }; 2357 2358 struct mlx5_ifc_resource_dump_info_segment_bits { 2359 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2360 2361 u8 reserved_at_20[0x18]; 2362 u8 dump_version[0x8]; 2363 2364 u8 hw_version[0x20]; 2365 2366 u8 fw_version[0x20]; 2367 }; 2368 2369 struct mlx5_ifc_resource_dump_menu_segment_bits { 2370 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2371 2372 u8 reserved_at_20[0x10]; 2373 u8 num_of_records[0x10]; 2374 2375 struct mlx5_ifc_resource_dump_menu_record_bits record[]; 2376 }; 2377 2378 struct mlx5_ifc_resource_dump_resource_segment_bits { 2379 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2380 2381 u8 reserved_at_20[0x20]; 2382 2383 u8 index1[0x20]; 2384 2385 u8 index2[0x20]; 2386 2387 u8 payload[][0x20]; 2388 }; 2389 2390 struct mlx5_ifc_resource_dump_terminate_segment_bits { 2391 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2392 }; 2393 2394 struct mlx5_ifc_menu_resource_dump_response_bits { 2395 struct mlx5_ifc_resource_dump_info_segment_bits info; 2396 struct mlx5_ifc_resource_dump_command_segment_bits cmd; 2397 struct mlx5_ifc_resource_dump_menu_segment_bits menu; 2398 struct mlx5_ifc_resource_dump_terminate_segment_bits terminate; 2399 }; 2400 2401 enum { 2402 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1, 2403 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2, 2404 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4, 2405 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8, 2406 }; 2407 2408 struct mlx5_ifc_modify_field_select_bits { 2409 u8 modify_field_select[0x20]; 2410 }; 2411 2412 struct mlx5_ifc_field_select_r_roce_np_bits { 2413 u8 field_select_r_roce_np[0x20]; 2414 }; 2415 2416 struct mlx5_ifc_field_select_r_roce_rp_bits { 2417 u8 field_select_r_roce_rp[0x20]; 2418 }; 2419 2420 enum { 2421 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4, 2422 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8, 2423 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10, 2424 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20, 2425 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40, 2426 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80, 2427 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100, 2428 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200, 2429 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400, 2430 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800, 2431 }; 2432 2433 struct mlx5_ifc_field_select_802_1qau_rp_bits { 2434 u8 field_select_8021qaurp[0x20]; 2435 }; 2436 2437 struct mlx5_ifc_phys_layer_cntrs_bits { 2438 u8 time_since_last_clear_high[0x20]; 2439 2440 u8 time_since_last_clear_low[0x20]; 2441 2442 u8 symbol_errors_high[0x20]; 2443 2444 u8 symbol_errors_low[0x20]; 2445 2446 u8 sync_headers_errors_high[0x20]; 2447 2448 u8 sync_headers_errors_low[0x20]; 2449 2450 u8 edpl_bip_errors_lane0_high[0x20]; 2451 2452 u8 edpl_bip_errors_lane0_low[0x20]; 2453 2454 u8 edpl_bip_errors_lane1_high[0x20]; 2455 2456 u8 edpl_bip_errors_lane1_low[0x20]; 2457 2458 u8 edpl_bip_errors_lane2_high[0x20]; 2459 2460 u8 edpl_bip_errors_lane2_low[0x20]; 2461 2462 u8 edpl_bip_errors_lane3_high[0x20]; 2463 2464 u8 edpl_bip_errors_lane3_low[0x20]; 2465 2466 u8 fc_fec_corrected_blocks_lane0_high[0x20]; 2467 2468 u8 fc_fec_corrected_blocks_lane0_low[0x20]; 2469 2470 u8 fc_fec_corrected_blocks_lane1_high[0x20]; 2471 2472 u8 fc_fec_corrected_blocks_lane1_low[0x20]; 2473 2474 u8 fc_fec_corrected_blocks_lane2_high[0x20]; 2475 2476 u8 fc_fec_corrected_blocks_lane2_low[0x20]; 2477 2478 u8 fc_fec_corrected_blocks_lane3_high[0x20]; 2479 2480 u8 fc_fec_corrected_blocks_lane3_low[0x20]; 2481 2482 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20]; 2483 2484 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20]; 2485 2486 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20]; 2487 2488 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20]; 2489 2490 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20]; 2491 2492 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20]; 2493 2494 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20]; 2495 2496 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20]; 2497 2498 u8 rs_fec_corrected_blocks_high[0x20]; 2499 2500 u8 rs_fec_corrected_blocks_low[0x20]; 2501 2502 u8 rs_fec_uncorrectable_blocks_high[0x20]; 2503 2504 u8 rs_fec_uncorrectable_blocks_low[0x20]; 2505 2506 u8 rs_fec_no_errors_blocks_high[0x20]; 2507 2508 u8 rs_fec_no_errors_blocks_low[0x20]; 2509 2510 u8 rs_fec_single_error_blocks_high[0x20]; 2511 2512 u8 rs_fec_single_error_blocks_low[0x20]; 2513 2514 u8 rs_fec_corrected_symbols_total_high[0x20]; 2515 2516 u8 rs_fec_corrected_symbols_total_low[0x20]; 2517 2518 u8 rs_fec_corrected_symbols_lane0_high[0x20]; 2519 2520 u8 rs_fec_corrected_symbols_lane0_low[0x20]; 2521 2522 u8 rs_fec_corrected_symbols_lane1_high[0x20]; 2523 2524 u8 rs_fec_corrected_symbols_lane1_low[0x20]; 2525 2526 u8 rs_fec_corrected_symbols_lane2_high[0x20]; 2527 2528 u8 rs_fec_corrected_symbols_lane2_low[0x20]; 2529 2530 u8 rs_fec_corrected_symbols_lane3_high[0x20]; 2531 2532 u8 rs_fec_corrected_symbols_lane3_low[0x20]; 2533 2534 u8 link_down_events[0x20]; 2535 2536 u8 successful_recovery_events[0x20]; 2537 2538 u8 reserved_at_640[0x180]; 2539 }; 2540 2541 struct mlx5_ifc_phys_layer_statistical_cntrs_bits { 2542 u8 time_since_last_clear_high[0x20]; 2543 2544 u8 time_since_last_clear_low[0x20]; 2545 2546 u8 phy_received_bits_high[0x20]; 2547 2548 u8 phy_received_bits_low[0x20]; 2549 2550 u8 phy_symbol_errors_high[0x20]; 2551 2552 u8 phy_symbol_errors_low[0x20]; 2553 2554 u8 phy_corrected_bits_high[0x20]; 2555 2556 u8 phy_corrected_bits_low[0x20]; 2557 2558 u8 phy_corrected_bits_lane0_high[0x20]; 2559 2560 u8 phy_corrected_bits_lane0_low[0x20]; 2561 2562 u8 phy_corrected_bits_lane1_high[0x20]; 2563 2564 u8 phy_corrected_bits_lane1_low[0x20]; 2565 2566 u8 phy_corrected_bits_lane2_high[0x20]; 2567 2568 u8 phy_corrected_bits_lane2_low[0x20]; 2569 2570 u8 phy_corrected_bits_lane3_high[0x20]; 2571 2572 u8 phy_corrected_bits_lane3_low[0x20]; 2573 2574 u8 reserved_at_200[0x5c0]; 2575 }; 2576 2577 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits { 2578 u8 symbol_error_counter[0x10]; 2579 2580 u8 link_error_recovery_counter[0x8]; 2581 2582 u8 link_downed_counter[0x8]; 2583 2584 u8 port_rcv_errors[0x10]; 2585 2586 u8 port_rcv_remote_physical_errors[0x10]; 2587 2588 u8 port_rcv_switch_relay_errors[0x10]; 2589 2590 u8 port_xmit_discards[0x10]; 2591 2592 u8 port_xmit_constraint_errors[0x8]; 2593 2594 u8 port_rcv_constraint_errors[0x8]; 2595 2596 u8 reserved_at_70[0x8]; 2597 2598 u8 link_overrun_errors[0x8]; 2599 2600 u8 reserved_at_80[0x10]; 2601 2602 u8 vl_15_dropped[0x10]; 2603 2604 u8 reserved_at_a0[0x80]; 2605 2606 u8 port_xmit_wait[0x20]; 2607 }; 2608 2609 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits { 2610 u8 transmit_queue_high[0x20]; 2611 2612 u8 transmit_queue_low[0x20]; 2613 2614 u8 no_buffer_discard_uc_high[0x20]; 2615 2616 u8 no_buffer_discard_uc_low[0x20]; 2617 2618 u8 reserved_at_80[0x740]; 2619 }; 2620 2621 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits { 2622 u8 wred_discard_high[0x20]; 2623 2624 u8 wred_discard_low[0x20]; 2625 2626 u8 ecn_marked_tc_high[0x20]; 2627 2628 u8 ecn_marked_tc_low[0x20]; 2629 2630 u8 reserved_at_80[0x740]; 2631 }; 2632 2633 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits { 2634 u8 rx_octets_high[0x20]; 2635 2636 u8 rx_octets_low[0x20]; 2637 2638 u8 reserved_at_40[0xc0]; 2639 2640 u8 rx_frames_high[0x20]; 2641 2642 u8 rx_frames_low[0x20]; 2643 2644 u8 tx_octets_high[0x20]; 2645 2646 u8 tx_octets_low[0x20]; 2647 2648 u8 reserved_at_180[0xc0]; 2649 2650 u8 tx_frames_high[0x20]; 2651 2652 u8 tx_frames_low[0x20]; 2653 2654 u8 rx_pause_high[0x20]; 2655 2656 u8 rx_pause_low[0x20]; 2657 2658 u8 rx_pause_duration_high[0x20]; 2659 2660 u8 rx_pause_duration_low[0x20]; 2661 2662 u8 tx_pause_high[0x20]; 2663 2664 u8 tx_pause_low[0x20]; 2665 2666 u8 tx_pause_duration_high[0x20]; 2667 2668 u8 tx_pause_duration_low[0x20]; 2669 2670 u8 rx_pause_transition_high[0x20]; 2671 2672 u8 rx_pause_transition_low[0x20]; 2673 2674 u8 rx_discards_high[0x20]; 2675 2676 u8 rx_discards_low[0x20]; 2677 2678 u8 device_stall_minor_watermark_cnt_high[0x20]; 2679 2680 u8 device_stall_minor_watermark_cnt_low[0x20]; 2681 2682 u8 device_stall_critical_watermark_cnt_high[0x20]; 2683 2684 u8 device_stall_critical_watermark_cnt_low[0x20]; 2685 2686 u8 reserved_at_480[0x340]; 2687 }; 2688 2689 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits { 2690 u8 port_transmit_wait_high[0x20]; 2691 2692 u8 port_transmit_wait_low[0x20]; 2693 2694 u8 reserved_at_40[0x100]; 2695 2696 u8 rx_buffer_almost_full_high[0x20]; 2697 2698 u8 rx_buffer_almost_full_low[0x20]; 2699 2700 u8 rx_buffer_full_high[0x20]; 2701 2702 u8 rx_buffer_full_low[0x20]; 2703 2704 u8 rx_icrc_encapsulated_high[0x20]; 2705 2706 u8 rx_icrc_encapsulated_low[0x20]; 2707 2708 u8 reserved_at_200[0x5c0]; 2709 }; 2710 2711 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits { 2712 u8 dot3stats_alignment_errors_high[0x20]; 2713 2714 u8 dot3stats_alignment_errors_low[0x20]; 2715 2716 u8 dot3stats_fcs_errors_high[0x20]; 2717 2718 u8 dot3stats_fcs_errors_low[0x20]; 2719 2720 u8 dot3stats_single_collision_frames_high[0x20]; 2721 2722 u8 dot3stats_single_collision_frames_low[0x20]; 2723 2724 u8 dot3stats_multiple_collision_frames_high[0x20]; 2725 2726 u8 dot3stats_multiple_collision_frames_low[0x20]; 2727 2728 u8 dot3stats_sqe_test_errors_high[0x20]; 2729 2730 u8 dot3stats_sqe_test_errors_low[0x20]; 2731 2732 u8 dot3stats_deferred_transmissions_high[0x20]; 2733 2734 u8 dot3stats_deferred_transmissions_low[0x20]; 2735 2736 u8 dot3stats_late_collisions_high[0x20]; 2737 2738 u8 dot3stats_late_collisions_low[0x20]; 2739 2740 u8 dot3stats_excessive_collisions_high[0x20]; 2741 2742 u8 dot3stats_excessive_collisions_low[0x20]; 2743 2744 u8 dot3stats_internal_mac_transmit_errors_high[0x20]; 2745 2746 u8 dot3stats_internal_mac_transmit_errors_low[0x20]; 2747 2748 u8 dot3stats_carrier_sense_errors_high[0x20]; 2749 2750 u8 dot3stats_carrier_sense_errors_low[0x20]; 2751 2752 u8 dot3stats_frame_too_longs_high[0x20]; 2753 2754 u8 dot3stats_frame_too_longs_low[0x20]; 2755 2756 u8 dot3stats_internal_mac_receive_errors_high[0x20]; 2757 2758 u8 dot3stats_internal_mac_receive_errors_low[0x20]; 2759 2760 u8 dot3stats_symbol_errors_high[0x20]; 2761 2762 u8 dot3stats_symbol_errors_low[0x20]; 2763 2764 u8 dot3control_in_unknown_opcodes_high[0x20]; 2765 2766 u8 dot3control_in_unknown_opcodes_low[0x20]; 2767 2768 u8 dot3in_pause_frames_high[0x20]; 2769 2770 u8 dot3in_pause_frames_low[0x20]; 2771 2772 u8 dot3out_pause_frames_high[0x20]; 2773 2774 u8 dot3out_pause_frames_low[0x20]; 2775 2776 u8 reserved_at_400[0x3c0]; 2777 }; 2778 2779 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits { 2780 u8 ether_stats_drop_events_high[0x20]; 2781 2782 u8 ether_stats_drop_events_low[0x20]; 2783 2784 u8 ether_stats_octets_high[0x20]; 2785 2786 u8 ether_stats_octets_low[0x20]; 2787 2788 u8 ether_stats_pkts_high[0x20]; 2789 2790 u8 ether_stats_pkts_low[0x20]; 2791 2792 u8 ether_stats_broadcast_pkts_high[0x20]; 2793 2794 u8 ether_stats_broadcast_pkts_low[0x20]; 2795 2796 u8 ether_stats_multicast_pkts_high[0x20]; 2797 2798 u8 ether_stats_multicast_pkts_low[0x20]; 2799 2800 u8 ether_stats_crc_align_errors_high[0x20]; 2801 2802 u8 ether_stats_crc_align_errors_low[0x20]; 2803 2804 u8 ether_stats_undersize_pkts_high[0x20]; 2805 2806 u8 ether_stats_undersize_pkts_low[0x20]; 2807 2808 u8 ether_stats_oversize_pkts_high[0x20]; 2809 2810 u8 ether_stats_oversize_pkts_low[0x20]; 2811 2812 u8 ether_stats_fragments_high[0x20]; 2813 2814 u8 ether_stats_fragments_low[0x20]; 2815 2816 u8 ether_stats_jabbers_high[0x20]; 2817 2818 u8 ether_stats_jabbers_low[0x20]; 2819 2820 u8 ether_stats_collisions_high[0x20]; 2821 2822 u8 ether_stats_collisions_low[0x20]; 2823 2824 u8 ether_stats_pkts64octets_high[0x20]; 2825 2826 u8 ether_stats_pkts64octets_low[0x20]; 2827 2828 u8 ether_stats_pkts65to127octets_high[0x20]; 2829 2830 u8 ether_stats_pkts65to127octets_low[0x20]; 2831 2832 u8 ether_stats_pkts128to255octets_high[0x20]; 2833 2834 u8 ether_stats_pkts128to255octets_low[0x20]; 2835 2836 u8 ether_stats_pkts256to511octets_high[0x20]; 2837 2838 u8 ether_stats_pkts256to511octets_low[0x20]; 2839 2840 u8 ether_stats_pkts512to1023octets_high[0x20]; 2841 2842 u8 ether_stats_pkts512to1023octets_low[0x20]; 2843 2844 u8 ether_stats_pkts1024to1518octets_high[0x20]; 2845 2846 u8 ether_stats_pkts1024to1518octets_low[0x20]; 2847 2848 u8 ether_stats_pkts1519to2047octets_high[0x20]; 2849 2850 u8 ether_stats_pkts1519to2047octets_low[0x20]; 2851 2852 u8 ether_stats_pkts2048to4095octets_high[0x20]; 2853 2854 u8 ether_stats_pkts2048to4095octets_low[0x20]; 2855 2856 u8 ether_stats_pkts4096to8191octets_high[0x20]; 2857 2858 u8 ether_stats_pkts4096to8191octets_low[0x20]; 2859 2860 u8 ether_stats_pkts8192to10239octets_high[0x20]; 2861 2862 u8 ether_stats_pkts8192to10239octets_low[0x20]; 2863 2864 u8 reserved_at_540[0x280]; 2865 }; 2866 2867 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits { 2868 u8 if_in_octets_high[0x20]; 2869 2870 u8 if_in_octets_low[0x20]; 2871 2872 u8 if_in_ucast_pkts_high[0x20]; 2873 2874 u8 if_in_ucast_pkts_low[0x20]; 2875 2876 u8 if_in_discards_high[0x20]; 2877 2878 u8 if_in_discards_low[0x20]; 2879 2880 u8 if_in_errors_high[0x20]; 2881 2882 u8 if_in_errors_low[0x20]; 2883 2884 u8 if_in_unknown_protos_high[0x20]; 2885 2886 u8 if_in_unknown_protos_low[0x20]; 2887 2888 u8 if_out_octets_high[0x20]; 2889 2890 u8 if_out_octets_low[0x20]; 2891 2892 u8 if_out_ucast_pkts_high[0x20]; 2893 2894 u8 if_out_ucast_pkts_low[0x20]; 2895 2896 u8 if_out_discards_high[0x20]; 2897 2898 u8 if_out_discards_low[0x20]; 2899 2900 u8 if_out_errors_high[0x20]; 2901 2902 u8 if_out_errors_low[0x20]; 2903 2904 u8 if_in_multicast_pkts_high[0x20]; 2905 2906 u8 if_in_multicast_pkts_low[0x20]; 2907 2908 u8 if_in_broadcast_pkts_high[0x20]; 2909 2910 u8 if_in_broadcast_pkts_low[0x20]; 2911 2912 u8 if_out_multicast_pkts_high[0x20]; 2913 2914 u8 if_out_multicast_pkts_low[0x20]; 2915 2916 u8 if_out_broadcast_pkts_high[0x20]; 2917 2918 u8 if_out_broadcast_pkts_low[0x20]; 2919 2920 u8 reserved_at_340[0x480]; 2921 }; 2922 2923 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits { 2924 u8 a_frames_transmitted_ok_high[0x20]; 2925 2926 u8 a_frames_transmitted_ok_low[0x20]; 2927 2928 u8 a_frames_received_ok_high[0x20]; 2929 2930 u8 a_frames_received_ok_low[0x20]; 2931 2932 u8 a_frame_check_sequence_errors_high[0x20]; 2933 2934 u8 a_frame_check_sequence_errors_low[0x20]; 2935 2936 u8 a_alignment_errors_high[0x20]; 2937 2938 u8 a_alignment_errors_low[0x20]; 2939 2940 u8 a_octets_transmitted_ok_high[0x20]; 2941 2942 u8 a_octets_transmitted_ok_low[0x20]; 2943 2944 u8 a_octets_received_ok_high[0x20]; 2945 2946 u8 a_octets_received_ok_low[0x20]; 2947 2948 u8 a_multicast_frames_xmitted_ok_high[0x20]; 2949 2950 u8 a_multicast_frames_xmitted_ok_low[0x20]; 2951 2952 u8 a_broadcast_frames_xmitted_ok_high[0x20]; 2953 2954 u8 a_broadcast_frames_xmitted_ok_low[0x20]; 2955 2956 u8 a_multicast_frames_received_ok_high[0x20]; 2957 2958 u8 a_multicast_frames_received_ok_low[0x20]; 2959 2960 u8 a_broadcast_frames_received_ok_high[0x20]; 2961 2962 u8 a_broadcast_frames_received_ok_low[0x20]; 2963 2964 u8 a_in_range_length_errors_high[0x20]; 2965 2966 u8 a_in_range_length_errors_low[0x20]; 2967 2968 u8 a_out_of_range_length_field_high[0x20]; 2969 2970 u8 a_out_of_range_length_field_low[0x20]; 2971 2972 u8 a_frame_too_long_errors_high[0x20]; 2973 2974 u8 a_frame_too_long_errors_low[0x20]; 2975 2976 u8 a_symbol_error_during_carrier_high[0x20]; 2977 2978 u8 a_symbol_error_during_carrier_low[0x20]; 2979 2980 u8 a_mac_control_frames_transmitted_high[0x20]; 2981 2982 u8 a_mac_control_frames_transmitted_low[0x20]; 2983 2984 u8 a_mac_control_frames_received_high[0x20]; 2985 2986 u8 a_mac_control_frames_received_low[0x20]; 2987 2988 u8 a_unsupported_opcodes_received_high[0x20]; 2989 2990 u8 a_unsupported_opcodes_received_low[0x20]; 2991 2992 u8 a_pause_mac_ctrl_frames_received_high[0x20]; 2993 2994 u8 a_pause_mac_ctrl_frames_received_low[0x20]; 2995 2996 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20]; 2997 2998 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20]; 2999 3000 u8 reserved_at_4c0[0x300]; 3001 }; 3002 3003 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits { 3004 u8 life_time_counter_high[0x20]; 3005 3006 u8 life_time_counter_low[0x20]; 3007 3008 u8 rx_errors[0x20]; 3009 3010 u8 tx_errors[0x20]; 3011 3012 u8 l0_to_recovery_eieos[0x20]; 3013 3014 u8 l0_to_recovery_ts[0x20]; 3015 3016 u8 l0_to_recovery_framing[0x20]; 3017 3018 u8 l0_to_recovery_retrain[0x20]; 3019 3020 u8 crc_error_dllp[0x20]; 3021 3022 u8 crc_error_tlp[0x20]; 3023 3024 u8 tx_overflow_buffer_pkt_high[0x20]; 3025 3026 u8 tx_overflow_buffer_pkt_low[0x20]; 3027 3028 u8 outbound_stalled_reads[0x20]; 3029 3030 u8 outbound_stalled_writes[0x20]; 3031 3032 u8 outbound_stalled_reads_events[0x20]; 3033 3034 u8 outbound_stalled_writes_events[0x20]; 3035 3036 u8 reserved_at_200[0x5c0]; 3037 }; 3038 3039 struct mlx5_ifc_cmd_inter_comp_event_bits { 3040 u8 command_completion_vector[0x20]; 3041 3042 u8 reserved_at_20[0xc0]; 3043 }; 3044 3045 struct mlx5_ifc_stall_vl_event_bits { 3046 u8 reserved_at_0[0x18]; 3047 u8 port_num[0x1]; 3048 u8 reserved_at_19[0x3]; 3049 u8 vl[0x4]; 3050 3051 u8 reserved_at_20[0xa0]; 3052 }; 3053 3054 struct mlx5_ifc_db_bf_congestion_event_bits { 3055 u8 event_subtype[0x8]; 3056 u8 reserved_at_8[0x8]; 3057 u8 congestion_level[0x8]; 3058 u8 reserved_at_18[0x8]; 3059 3060 u8 reserved_at_20[0xa0]; 3061 }; 3062 3063 struct mlx5_ifc_gpio_event_bits { 3064 u8 reserved_at_0[0x60]; 3065 3066 u8 gpio_event_hi[0x20]; 3067 3068 u8 gpio_event_lo[0x20]; 3069 3070 u8 reserved_at_a0[0x40]; 3071 }; 3072 3073 struct mlx5_ifc_port_state_change_event_bits { 3074 u8 reserved_at_0[0x40]; 3075 3076 u8 port_num[0x4]; 3077 u8 reserved_at_44[0x1c]; 3078 3079 u8 reserved_at_60[0x80]; 3080 }; 3081 3082 struct mlx5_ifc_dropped_packet_logged_bits { 3083 u8 reserved_at_0[0xe0]; 3084 }; 3085 3086 struct mlx5_ifc_default_timeout_bits { 3087 u8 to_multiplier[0x3]; 3088 u8 reserved_at_3[0x9]; 3089 u8 to_value[0x14]; 3090 }; 3091 3092 struct mlx5_ifc_dtor_reg_bits { 3093 u8 reserved_at_0[0x20]; 3094 3095 struct mlx5_ifc_default_timeout_bits pcie_toggle_to; 3096 3097 u8 reserved_at_40[0x60]; 3098 3099 struct mlx5_ifc_default_timeout_bits health_poll_to; 3100 3101 struct mlx5_ifc_default_timeout_bits full_crdump_to; 3102 3103 struct mlx5_ifc_default_timeout_bits fw_reset_to; 3104 3105 struct mlx5_ifc_default_timeout_bits flush_on_err_to; 3106 3107 struct mlx5_ifc_default_timeout_bits pci_sync_update_to; 3108 3109 struct mlx5_ifc_default_timeout_bits tear_down_to; 3110 3111 struct mlx5_ifc_default_timeout_bits fsm_reactivate_to; 3112 3113 struct mlx5_ifc_default_timeout_bits reclaim_pages_to; 3114 3115 struct mlx5_ifc_default_timeout_bits reclaim_vfs_pages_to; 3116 3117 u8 reserved_at_1c0[0x40]; 3118 }; 3119 3120 enum { 3121 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1, 3122 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2, 3123 }; 3124 3125 struct mlx5_ifc_cq_error_bits { 3126 u8 reserved_at_0[0x8]; 3127 u8 cqn[0x18]; 3128 3129 u8 reserved_at_20[0x20]; 3130 3131 u8 reserved_at_40[0x18]; 3132 u8 syndrome[0x8]; 3133 3134 u8 reserved_at_60[0x80]; 3135 }; 3136 3137 struct mlx5_ifc_rdma_page_fault_event_bits { 3138 u8 bytes_committed[0x20]; 3139 3140 u8 r_key[0x20]; 3141 3142 u8 reserved_at_40[0x10]; 3143 u8 packet_len[0x10]; 3144 3145 u8 rdma_op_len[0x20]; 3146 3147 u8 rdma_va[0x40]; 3148 3149 u8 reserved_at_c0[0x5]; 3150 u8 rdma[0x1]; 3151 u8 write[0x1]; 3152 u8 requestor[0x1]; 3153 u8 qp_number[0x18]; 3154 }; 3155 3156 struct mlx5_ifc_wqe_associated_page_fault_event_bits { 3157 u8 bytes_committed[0x20]; 3158 3159 u8 reserved_at_20[0x10]; 3160 u8 wqe_index[0x10]; 3161 3162 u8 reserved_at_40[0x10]; 3163 u8 len[0x10]; 3164 3165 u8 reserved_at_60[0x60]; 3166 3167 u8 reserved_at_c0[0x5]; 3168 u8 rdma[0x1]; 3169 u8 write_read[0x1]; 3170 u8 requestor[0x1]; 3171 u8 qpn[0x18]; 3172 }; 3173 3174 struct mlx5_ifc_qp_events_bits { 3175 u8 reserved_at_0[0xa0]; 3176 3177 u8 type[0x8]; 3178 u8 reserved_at_a8[0x18]; 3179 3180 u8 reserved_at_c0[0x8]; 3181 u8 qpn_rqn_sqn[0x18]; 3182 }; 3183 3184 struct mlx5_ifc_dct_events_bits { 3185 u8 reserved_at_0[0xc0]; 3186 3187 u8 reserved_at_c0[0x8]; 3188 u8 dct_number[0x18]; 3189 }; 3190 3191 struct mlx5_ifc_comp_event_bits { 3192 u8 reserved_at_0[0xc0]; 3193 3194 u8 reserved_at_c0[0x8]; 3195 u8 cq_number[0x18]; 3196 }; 3197 3198 enum { 3199 MLX5_QPC_STATE_RST = 0x0, 3200 MLX5_QPC_STATE_INIT = 0x1, 3201 MLX5_QPC_STATE_RTR = 0x2, 3202 MLX5_QPC_STATE_RTS = 0x3, 3203 MLX5_QPC_STATE_SQER = 0x4, 3204 MLX5_QPC_STATE_ERR = 0x6, 3205 MLX5_QPC_STATE_SQD = 0x7, 3206 MLX5_QPC_STATE_SUSPENDED = 0x9, 3207 }; 3208 3209 enum { 3210 MLX5_QPC_ST_RC = 0x0, 3211 MLX5_QPC_ST_UC = 0x1, 3212 MLX5_QPC_ST_UD = 0x2, 3213 MLX5_QPC_ST_XRC = 0x3, 3214 MLX5_QPC_ST_DCI = 0x5, 3215 MLX5_QPC_ST_QP0 = 0x7, 3216 MLX5_QPC_ST_QP1 = 0x8, 3217 MLX5_QPC_ST_RAW_DATAGRAM = 0x9, 3218 MLX5_QPC_ST_REG_UMR = 0xc, 3219 }; 3220 3221 enum { 3222 MLX5_QPC_PM_STATE_ARMED = 0x0, 3223 MLX5_QPC_PM_STATE_REARM = 0x1, 3224 MLX5_QPC_PM_STATE_RESERVED = 0x2, 3225 MLX5_QPC_PM_STATE_MIGRATED = 0x3, 3226 }; 3227 3228 enum { 3229 MLX5_QPC_OFFLOAD_TYPE_RNDV = 0x1, 3230 }; 3231 3232 enum { 3233 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0, 3234 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1, 3235 }; 3236 3237 enum { 3238 MLX5_QPC_MTU_256_BYTES = 0x1, 3239 MLX5_QPC_MTU_512_BYTES = 0x2, 3240 MLX5_QPC_MTU_1K_BYTES = 0x3, 3241 MLX5_QPC_MTU_2K_BYTES = 0x4, 3242 MLX5_QPC_MTU_4K_BYTES = 0x5, 3243 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7, 3244 }; 3245 3246 enum { 3247 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1, 3248 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2, 3249 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3, 3250 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4, 3251 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5, 3252 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6, 3253 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7, 3254 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8, 3255 }; 3256 3257 enum { 3258 MLX5_QPC_CS_REQ_DISABLE = 0x0, 3259 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11, 3260 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22, 3261 }; 3262 3263 enum { 3264 MLX5_QPC_CS_RES_DISABLE = 0x0, 3265 MLX5_QPC_CS_RES_UP_TO_32B = 0x1, 3266 MLX5_QPC_CS_RES_UP_TO_64B = 0x2, 3267 }; 3268 3269 enum { 3270 MLX5_TIMESTAMP_FORMAT_FREE_RUNNING = 0x0, 3271 MLX5_TIMESTAMP_FORMAT_DEFAULT = 0x1, 3272 MLX5_TIMESTAMP_FORMAT_REAL_TIME = 0x2, 3273 }; 3274 3275 struct mlx5_ifc_qpc_bits { 3276 u8 state[0x4]; 3277 u8 lag_tx_port_affinity[0x4]; 3278 u8 st[0x8]; 3279 u8 reserved_at_10[0x2]; 3280 u8 isolate_vl_tc[0x1]; 3281 u8 pm_state[0x2]; 3282 u8 reserved_at_15[0x1]; 3283 u8 req_e2e_credit_mode[0x2]; 3284 u8 offload_type[0x4]; 3285 u8 end_padding_mode[0x2]; 3286 u8 reserved_at_1e[0x2]; 3287 3288 u8 wq_signature[0x1]; 3289 u8 block_lb_mc[0x1]; 3290 u8 atomic_like_write_en[0x1]; 3291 u8 latency_sensitive[0x1]; 3292 u8 reserved_at_24[0x1]; 3293 u8 drain_sigerr[0x1]; 3294 u8 reserved_at_26[0x2]; 3295 u8 pd[0x18]; 3296 3297 u8 mtu[0x3]; 3298 u8 log_msg_max[0x5]; 3299 u8 reserved_at_48[0x1]; 3300 u8 log_rq_size[0x4]; 3301 u8 log_rq_stride[0x3]; 3302 u8 no_sq[0x1]; 3303 u8 log_sq_size[0x4]; 3304 u8 reserved_at_55[0x1]; 3305 u8 retry_mode[0x2]; 3306 u8 ts_format[0x2]; 3307 u8 reserved_at_5a[0x1]; 3308 u8 rlky[0x1]; 3309 u8 ulp_stateless_offload_mode[0x4]; 3310 3311 u8 counter_set_id[0x8]; 3312 u8 uar_page[0x18]; 3313 3314 u8 reserved_at_80[0x8]; 3315 u8 user_index[0x18]; 3316 3317 u8 reserved_at_a0[0x3]; 3318 u8 log_page_size[0x5]; 3319 u8 remote_qpn[0x18]; 3320 3321 struct mlx5_ifc_ads_bits primary_address_path; 3322 3323 struct mlx5_ifc_ads_bits secondary_address_path; 3324 3325 u8 log_ack_req_freq[0x4]; 3326 u8 reserved_at_384[0x4]; 3327 u8 log_sra_max[0x3]; 3328 u8 reserved_at_38b[0x2]; 3329 u8 retry_count[0x3]; 3330 u8 rnr_retry[0x3]; 3331 u8 reserved_at_393[0x1]; 3332 u8 fre[0x1]; 3333 u8 cur_rnr_retry[0x3]; 3334 u8 cur_retry_count[0x3]; 3335 u8 reserved_at_39b[0x5]; 3336 3337 u8 reserved_at_3a0[0x20]; 3338 3339 u8 reserved_at_3c0[0x8]; 3340 u8 next_send_psn[0x18]; 3341 3342 u8 reserved_at_3e0[0x3]; 3343 u8 log_num_dci_stream_channels[0x5]; 3344 u8 cqn_snd[0x18]; 3345 3346 u8 reserved_at_400[0x3]; 3347 u8 log_num_dci_errored_streams[0x5]; 3348 u8 deth_sqpn[0x18]; 3349 3350 u8 reserved_at_420[0x20]; 3351 3352 u8 reserved_at_440[0x8]; 3353 u8 last_acked_psn[0x18]; 3354 3355 u8 reserved_at_460[0x8]; 3356 u8 ssn[0x18]; 3357 3358 u8 reserved_at_480[0x8]; 3359 u8 log_rra_max[0x3]; 3360 u8 reserved_at_48b[0x1]; 3361 u8 atomic_mode[0x4]; 3362 u8 rre[0x1]; 3363 u8 rwe[0x1]; 3364 u8 rae[0x1]; 3365 u8 reserved_at_493[0x1]; 3366 u8 page_offset[0x6]; 3367 u8 reserved_at_49a[0x3]; 3368 u8 cd_slave_receive[0x1]; 3369 u8 cd_slave_send[0x1]; 3370 u8 cd_master[0x1]; 3371 3372 u8 reserved_at_4a0[0x3]; 3373 u8 min_rnr_nak[0x5]; 3374 u8 next_rcv_psn[0x18]; 3375 3376 u8 reserved_at_4c0[0x8]; 3377 u8 xrcd[0x18]; 3378 3379 u8 reserved_at_4e0[0x8]; 3380 u8 cqn_rcv[0x18]; 3381 3382 u8 dbr_addr[0x40]; 3383 3384 u8 q_key[0x20]; 3385 3386 u8 reserved_at_560[0x5]; 3387 u8 rq_type[0x3]; 3388 u8 srqn_rmpn_xrqn[0x18]; 3389 3390 u8 reserved_at_580[0x8]; 3391 u8 rmsn[0x18]; 3392 3393 u8 hw_sq_wqebb_counter[0x10]; 3394 u8 sw_sq_wqebb_counter[0x10]; 3395 3396 u8 hw_rq_counter[0x20]; 3397 3398 u8 sw_rq_counter[0x20]; 3399 3400 u8 reserved_at_600[0x20]; 3401 3402 u8 reserved_at_620[0xf]; 3403 u8 cgs[0x1]; 3404 u8 cs_req[0x8]; 3405 u8 cs_res[0x8]; 3406 3407 u8 dc_access_key[0x40]; 3408 3409 u8 reserved_at_680[0x3]; 3410 u8 dbr_umem_valid[0x1]; 3411 3412 u8 reserved_at_684[0xbc]; 3413 }; 3414 3415 struct mlx5_ifc_roce_addr_layout_bits { 3416 u8 source_l3_address[16][0x8]; 3417 3418 u8 reserved_at_80[0x3]; 3419 u8 vlan_valid[0x1]; 3420 u8 vlan_id[0xc]; 3421 u8 source_mac_47_32[0x10]; 3422 3423 u8 source_mac_31_0[0x20]; 3424 3425 u8 reserved_at_c0[0x14]; 3426 u8 roce_l3_type[0x4]; 3427 u8 roce_version[0x8]; 3428 3429 u8 reserved_at_e0[0x20]; 3430 }; 3431 3432 struct mlx5_ifc_shampo_cap_bits { 3433 u8 reserved_at_0[0x3]; 3434 u8 shampo_log_max_reservation_size[0x5]; 3435 u8 reserved_at_8[0x3]; 3436 u8 shampo_log_min_reservation_size[0x5]; 3437 u8 shampo_min_mss_size[0x10]; 3438 3439 u8 reserved_at_20[0x3]; 3440 u8 shampo_max_log_headers_entry_size[0x5]; 3441 u8 reserved_at_28[0x18]; 3442 3443 u8 reserved_at_40[0x7c0]; 3444 }; 3445 3446 struct mlx5_ifc_crypto_cap_bits { 3447 u8 reserved_at_0[0x3]; 3448 u8 synchronize_dek[0x1]; 3449 u8 int_kek_manual[0x1]; 3450 u8 int_kek_auto[0x1]; 3451 u8 reserved_at_6[0x1a]; 3452 3453 u8 reserved_at_20[0x3]; 3454 u8 log_dek_max_alloc[0x5]; 3455 u8 reserved_at_28[0x3]; 3456 u8 log_max_num_deks[0x5]; 3457 u8 reserved_at_30[0x10]; 3458 3459 u8 reserved_at_40[0x20]; 3460 3461 u8 reserved_at_60[0x3]; 3462 u8 log_dek_granularity[0x5]; 3463 u8 reserved_at_68[0x3]; 3464 u8 log_max_num_int_kek[0x5]; 3465 u8 sw_wrapped_dek[0x10]; 3466 3467 u8 reserved_at_80[0x780]; 3468 }; 3469 3470 union mlx5_ifc_hca_cap_union_bits { 3471 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap; 3472 struct mlx5_ifc_cmd_hca_cap_2_bits cmd_hca_cap_2; 3473 struct mlx5_ifc_odp_cap_bits odp_cap; 3474 struct mlx5_ifc_atomic_caps_bits atomic_caps; 3475 struct mlx5_ifc_roce_cap_bits roce_cap; 3476 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps; 3477 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap; 3478 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap; 3479 struct mlx5_ifc_e_switch_cap_bits e_switch_cap; 3480 struct mlx5_ifc_port_selection_cap_bits port_selection_cap; 3481 struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap; 3482 struct mlx5_ifc_qos_cap_bits qos_cap; 3483 struct mlx5_ifc_debug_cap_bits debug_cap; 3484 struct mlx5_ifc_fpga_cap_bits fpga_cap; 3485 struct mlx5_ifc_tls_cap_bits tls_cap; 3486 struct mlx5_ifc_device_mem_cap_bits device_mem_cap; 3487 struct mlx5_ifc_virtio_emulation_cap_bits virtio_emulation_cap; 3488 struct mlx5_ifc_shampo_cap_bits shampo_cap; 3489 struct mlx5_ifc_macsec_cap_bits macsec_cap; 3490 struct mlx5_ifc_crypto_cap_bits crypto_cap; 3491 u8 reserved_at_0[0x8000]; 3492 }; 3493 3494 enum { 3495 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1, 3496 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2, 3497 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4, 3498 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8, 3499 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT = 0x10, 3500 MLX5_FLOW_CONTEXT_ACTION_DECAP = 0x20, 3501 MLX5_FLOW_CONTEXT_ACTION_MOD_HDR = 0x40, 3502 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP = 0x80, 3503 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100, 3504 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2 = 0x400, 3505 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2 = 0x800, 3506 MLX5_FLOW_CONTEXT_ACTION_CRYPTO_DECRYPT = 0x1000, 3507 MLX5_FLOW_CONTEXT_ACTION_CRYPTO_ENCRYPT = 0x2000, 3508 MLX5_FLOW_CONTEXT_ACTION_EXECUTE_ASO = 0x4000, 3509 }; 3510 3511 enum { 3512 MLX5_FLOW_CONTEXT_FLOW_SOURCE_ANY_VPORT = 0x0, 3513 MLX5_FLOW_CONTEXT_FLOW_SOURCE_UPLINK = 0x1, 3514 MLX5_FLOW_CONTEXT_FLOW_SOURCE_LOCAL_VPORT = 0x2, 3515 }; 3516 3517 enum { 3518 MLX5_FLOW_CONTEXT_ENCRYPT_DECRYPT_TYPE_IPSEC = 0x0, 3519 MLX5_FLOW_CONTEXT_ENCRYPT_DECRYPT_TYPE_MACSEC = 0x1, 3520 }; 3521 3522 struct mlx5_ifc_vlan_bits { 3523 u8 ethtype[0x10]; 3524 u8 prio[0x3]; 3525 u8 cfi[0x1]; 3526 u8 vid[0xc]; 3527 }; 3528 3529 enum { 3530 MLX5_FLOW_METER_COLOR_RED = 0x0, 3531 MLX5_FLOW_METER_COLOR_YELLOW = 0x1, 3532 MLX5_FLOW_METER_COLOR_GREEN = 0x2, 3533 MLX5_FLOW_METER_COLOR_UNDEFINED = 0x3, 3534 }; 3535 3536 enum { 3537 MLX5_EXE_ASO_FLOW_METER = 0x2, 3538 }; 3539 3540 struct mlx5_ifc_exe_aso_ctrl_flow_meter_bits { 3541 u8 return_reg_id[0x4]; 3542 u8 aso_type[0x4]; 3543 u8 reserved_at_8[0x14]; 3544 u8 action[0x1]; 3545 u8 init_color[0x2]; 3546 u8 meter_id[0x1]; 3547 }; 3548 3549 union mlx5_ifc_exe_aso_ctrl { 3550 struct mlx5_ifc_exe_aso_ctrl_flow_meter_bits exe_aso_ctrl_flow_meter; 3551 }; 3552 3553 struct mlx5_ifc_execute_aso_bits { 3554 u8 valid[0x1]; 3555 u8 reserved_at_1[0x7]; 3556 u8 aso_object_id[0x18]; 3557 3558 union mlx5_ifc_exe_aso_ctrl exe_aso_ctrl; 3559 }; 3560 3561 struct mlx5_ifc_flow_context_bits { 3562 struct mlx5_ifc_vlan_bits push_vlan; 3563 3564 u8 group_id[0x20]; 3565 3566 u8 reserved_at_40[0x8]; 3567 u8 flow_tag[0x18]; 3568 3569 u8 reserved_at_60[0x10]; 3570 u8 action[0x10]; 3571 3572 u8 extended_destination[0x1]; 3573 u8 reserved_at_81[0x1]; 3574 u8 flow_source[0x2]; 3575 u8 encrypt_decrypt_type[0x4]; 3576 u8 destination_list_size[0x18]; 3577 3578 u8 reserved_at_a0[0x8]; 3579 u8 flow_counter_list_size[0x18]; 3580 3581 u8 packet_reformat_id[0x20]; 3582 3583 u8 modify_header_id[0x20]; 3584 3585 struct mlx5_ifc_vlan_bits push_vlan_2; 3586 3587 u8 encrypt_decrypt_obj_id[0x20]; 3588 u8 reserved_at_140[0xc0]; 3589 3590 struct mlx5_ifc_fte_match_param_bits match_value; 3591 3592 struct mlx5_ifc_execute_aso_bits execute_aso[4]; 3593 3594 u8 reserved_at_1300[0x500]; 3595 3596 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[]; 3597 }; 3598 3599 enum { 3600 MLX5_XRC_SRQC_STATE_GOOD = 0x0, 3601 MLX5_XRC_SRQC_STATE_ERROR = 0x1, 3602 }; 3603 3604 struct mlx5_ifc_xrc_srqc_bits { 3605 u8 state[0x4]; 3606 u8 log_xrc_srq_size[0x4]; 3607 u8 reserved_at_8[0x18]; 3608 3609 u8 wq_signature[0x1]; 3610 u8 cont_srq[0x1]; 3611 u8 reserved_at_22[0x1]; 3612 u8 rlky[0x1]; 3613 u8 basic_cyclic_rcv_wqe[0x1]; 3614 u8 log_rq_stride[0x3]; 3615 u8 xrcd[0x18]; 3616 3617 u8 page_offset[0x6]; 3618 u8 reserved_at_46[0x1]; 3619 u8 dbr_umem_valid[0x1]; 3620 u8 cqn[0x18]; 3621 3622 u8 reserved_at_60[0x20]; 3623 3624 u8 user_index_equal_xrc_srqn[0x1]; 3625 u8 reserved_at_81[0x1]; 3626 u8 log_page_size[0x6]; 3627 u8 user_index[0x18]; 3628 3629 u8 reserved_at_a0[0x20]; 3630 3631 u8 reserved_at_c0[0x8]; 3632 u8 pd[0x18]; 3633 3634 u8 lwm[0x10]; 3635 u8 wqe_cnt[0x10]; 3636 3637 u8 reserved_at_100[0x40]; 3638 3639 u8 db_record_addr_h[0x20]; 3640 3641 u8 db_record_addr_l[0x1e]; 3642 u8 reserved_at_17e[0x2]; 3643 3644 u8 reserved_at_180[0x80]; 3645 }; 3646 3647 struct mlx5_ifc_vnic_diagnostic_statistics_bits { 3648 u8 counter_error_queues[0x20]; 3649 3650 u8 total_error_queues[0x20]; 3651 3652 u8 send_queue_priority_update_flow[0x20]; 3653 3654 u8 reserved_at_60[0x20]; 3655 3656 u8 nic_receive_steering_discard[0x40]; 3657 3658 u8 receive_discard_vport_down[0x40]; 3659 3660 u8 transmit_discard_vport_down[0x40]; 3661 3662 u8 async_eq_overrun[0x20]; 3663 3664 u8 comp_eq_overrun[0x20]; 3665 3666 u8 reserved_at_180[0x20]; 3667 3668 u8 invalid_command[0x20]; 3669 3670 u8 quota_exceeded_command[0x20]; 3671 3672 u8 internal_rq_out_of_buffer[0x20]; 3673 3674 u8 cq_overrun[0x20]; 3675 3676 u8 eth_wqe_too_small[0x20]; 3677 3678 u8 reserved_at_220[0xc0]; 3679 3680 u8 generated_pkt_steering_fail[0x40]; 3681 3682 u8 handled_pkt_steering_fail[0x40]; 3683 3684 u8 reserved_at_360[0xc80]; 3685 }; 3686 3687 struct mlx5_ifc_traffic_counter_bits { 3688 u8 packets[0x40]; 3689 3690 u8 octets[0x40]; 3691 }; 3692 3693 struct mlx5_ifc_tisc_bits { 3694 u8 strict_lag_tx_port_affinity[0x1]; 3695 u8 tls_en[0x1]; 3696 u8 reserved_at_2[0x2]; 3697 u8 lag_tx_port_affinity[0x04]; 3698 3699 u8 reserved_at_8[0x4]; 3700 u8 prio[0x4]; 3701 u8 reserved_at_10[0x10]; 3702 3703 u8 reserved_at_20[0x100]; 3704 3705 u8 reserved_at_120[0x8]; 3706 u8 transport_domain[0x18]; 3707 3708 u8 reserved_at_140[0x8]; 3709 u8 underlay_qpn[0x18]; 3710 3711 u8 reserved_at_160[0x8]; 3712 u8 pd[0x18]; 3713 3714 u8 reserved_at_180[0x380]; 3715 }; 3716 3717 enum { 3718 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0, 3719 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1, 3720 }; 3721 3722 enum { 3723 MLX5_TIRC_PACKET_MERGE_MASK_IPV4_LRO = BIT(0), 3724 MLX5_TIRC_PACKET_MERGE_MASK_IPV6_LRO = BIT(1), 3725 }; 3726 3727 enum { 3728 MLX5_RX_HASH_FN_NONE = 0x0, 3729 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1, 3730 MLX5_RX_HASH_FN_TOEPLITZ = 0x2, 3731 }; 3732 3733 enum { 3734 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST = 0x1, 3735 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST = 0x2, 3736 }; 3737 3738 struct mlx5_ifc_tirc_bits { 3739 u8 reserved_at_0[0x20]; 3740 3741 u8 disp_type[0x4]; 3742 u8 tls_en[0x1]; 3743 u8 reserved_at_25[0x1b]; 3744 3745 u8 reserved_at_40[0x40]; 3746 3747 u8 reserved_at_80[0x4]; 3748 u8 lro_timeout_period_usecs[0x10]; 3749 u8 packet_merge_mask[0x4]; 3750 u8 lro_max_ip_payload_size[0x8]; 3751 3752 u8 reserved_at_a0[0x40]; 3753 3754 u8 reserved_at_e0[0x8]; 3755 u8 inline_rqn[0x18]; 3756 3757 u8 rx_hash_symmetric[0x1]; 3758 u8 reserved_at_101[0x1]; 3759 u8 tunneled_offload_en[0x1]; 3760 u8 reserved_at_103[0x5]; 3761 u8 indirect_table[0x18]; 3762 3763 u8 rx_hash_fn[0x4]; 3764 u8 reserved_at_124[0x2]; 3765 u8 self_lb_block[0x2]; 3766 u8 transport_domain[0x18]; 3767 3768 u8 rx_hash_toeplitz_key[10][0x20]; 3769 3770 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer; 3771 3772 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner; 3773 3774 u8 reserved_at_2c0[0x4c0]; 3775 }; 3776 3777 enum { 3778 MLX5_SRQC_STATE_GOOD = 0x0, 3779 MLX5_SRQC_STATE_ERROR = 0x1, 3780 }; 3781 3782 struct mlx5_ifc_srqc_bits { 3783 u8 state[0x4]; 3784 u8 log_srq_size[0x4]; 3785 u8 reserved_at_8[0x18]; 3786 3787 u8 wq_signature[0x1]; 3788 u8 cont_srq[0x1]; 3789 u8 reserved_at_22[0x1]; 3790 u8 rlky[0x1]; 3791 u8 reserved_at_24[0x1]; 3792 u8 log_rq_stride[0x3]; 3793 u8 xrcd[0x18]; 3794 3795 u8 page_offset[0x6]; 3796 u8 reserved_at_46[0x2]; 3797 u8 cqn[0x18]; 3798 3799 u8 reserved_at_60[0x20]; 3800 3801 u8 reserved_at_80[0x2]; 3802 u8 log_page_size[0x6]; 3803 u8 reserved_at_88[0x18]; 3804 3805 u8 reserved_at_a0[0x20]; 3806 3807 u8 reserved_at_c0[0x8]; 3808 u8 pd[0x18]; 3809 3810 u8 lwm[0x10]; 3811 u8 wqe_cnt[0x10]; 3812 3813 u8 reserved_at_100[0x40]; 3814 3815 u8 dbr_addr[0x40]; 3816 3817 u8 reserved_at_180[0x80]; 3818 }; 3819 3820 enum { 3821 MLX5_SQC_STATE_RST = 0x0, 3822 MLX5_SQC_STATE_RDY = 0x1, 3823 MLX5_SQC_STATE_ERR = 0x3, 3824 }; 3825 3826 struct mlx5_ifc_sqc_bits { 3827 u8 rlky[0x1]; 3828 u8 cd_master[0x1]; 3829 u8 fre[0x1]; 3830 u8 flush_in_error_en[0x1]; 3831 u8 allow_multi_pkt_send_wqe[0x1]; 3832 u8 min_wqe_inline_mode[0x3]; 3833 u8 state[0x4]; 3834 u8 reg_umr[0x1]; 3835 u8 allow_swp[0x1]; 3836 u8 hairpin[0x1]; 3837 u8 reserved_at_f[0xb]; 3838 u8 ts_format[0x2]; 3839 u8 reserved_at_1c[0x4]; 3840 3841 u8 reserved_at_20[0x8]; 3842 u8 user_index[0x18]; 3843 3844 u8 reserved_at_40[0x8]; 3845 u8 cqn[0x18]; 3846 3847 u8 reserved_at_60[0x8]; 3848 u8 hairpin_peer_rq[0x18]; 3849 3850 u8 reserved_at_80[0x10]; 3851 u8 hairpin_peer_vhca[0x10]; 3852 3853 u8 reserved_at_a0[0x20]; 3854 3855 u8 reserved_at_c0[0x8]; 3856 u8 ts_cqe_to_dest_cqn[0x18]; 3857 3858 u8 reserved_at_e0[0x10]; 3859 u8 packet_pacing_rate_limit_index[0x10]; 3860 u8 tis_lst_sz[0x10]; 3861 u8 qos_queue_group_id[0x10]; 3862 3863 u8 reserved_at_120[0x40]; 3864 3865 u8 reserved_at_160[0x8]; 3866 u8 tis_num_0[0x18]; 3867 3868 struct mlx5_ifc_wq_bits wq; 3869 }; 3870 3871 enum { 3872 SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0, 3873 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1, 3874 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2, 3875 SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3, 3876 SCHEDULING_CONTEXT_ELEMENT_TYPE_QUEUE_GROUP = 0x4, 3877 }; 3878 3879 enum { 3880 ELEMENT_TYPE_CAP_MASK_TASR = 1 << 0, 3881 ELEMENT_TYPE_CAP_MASK_VPORT = 1 << 1, 3882 ELEMENT_TYPE_CAP_MASK_VPORT_TC = 1 << 2, 3883 ELEMENT_TYPE_CAP_MASK_PARA_VPORT_TC = 1 << 3, 3884 }; 3885 3886 struct mlx5_ifc_scheduling_context_bits { 3887 u8 element_type[0x8]; 3888 u8 reserved_at_8[0x18]; 3889 3890 u8 element_attributes[0x20]; 3891 3892 u8 parent_element_id[0x20]; 3893 3894 u8 reserved_at_60[0x40]; 3895 3896 u8 bw_share[0x20]; 3897 3898 u8 max_average_bw[0x20]; 3899 3900 u8 reserved_at_e0[0x120]; 3901 }; 3902 3903 struct mlx5_ifc_rqtc_bits { 3904 u8 reserved_at_0[0xa0]; 3905 3906 u8 reserved_at_a0[0x5]; 3907 u8 list_q_type[0x3]; 3908 u8 reserved_at_a8[0x8]; 3909 u8 rqt_max_size[0x10]; 3910 3911 u8 rq_vhca_id_format[0x1]; 3912 u8 reserved_at_c1[0xf]; 3913 u8 rqt_actual_size[0x10]; 3914 3915 u8 reserved_at_e0[0x6a0]; 3916 3917 struct mlx5_ifc_rq_num_bits rq_num[]; 3918 }; 3919 3920 enum { 3921 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0, 3922 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1, 3923 }; 3924 3925 enum { 3926 MLX5_RQC_STATE_RST = 0x0, 3927 MLX5_RQC_STATE_RDY = 0x1, 3928 MLX5_RQC_STATE_ERR = 0x3, 3929 }; 3930 3931 enum { 3932 MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_BYTE = 0x0, 3933 MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_STRIDE = 0x1, 3934 MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_PAGE = 0x2, 3935 }; 3936 3937 enum { 3938 MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_NO_MATCH = 0x0, 3939 MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_EXTENDED = 0x1, 3940 MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_FIVE_TUPLE = 0x2, 3941 }; 3942 3943 struct mlx5_ifc_rqc_bits { 3944 u8 rlky[0x1]; 3945 u8 delay_drop_en[0x1]; 3946 u8 scatter_fcs[0x1]; 3947 u8 vsd[0x1]; 3948 u8 mem_rq_type[0x4]; 3949 u8 state[0x4]; 3950 u8 reserved_at_c[0x1]; 3951 u8 flush_in_error_en[0x1]; 3952 u8 hairpin[0x1]; 3953 u8 reserved_at_f[0xb]; 3954 u8 ts_format[0x2]; 3955 u8 reserved_at_1c[0x4]; 3956 3957 u8 reserved_at_20[0x8]; 3958 u8 user_index[0x18]; 3959 3960 u8 reserved_at_40[0x8]; 3961 u8 cqn[0x18]; 3962 3963 u8 counter_set_id[0x8]; 3964 u8 reserved_at_68[0x18]; 3965 3966 u8 reserved_at_80[0x8]; 3967 u8 rmpn[0x18]; 3968 3969 u8 reserved_at_a0[0x8]; 3970 u8 hairpin_peer_sq[0x18]; 3971 3972 u8 reserved_at_c0[0x10]; 3973 u8 hairpin_peer_vhca[0x10]; 3974 3975 u8 reserved_at_e0[0x46]; 3976 u8 shampo_no_match_alignment_granularity[0x2]; 3977 u8 reserved_at_128[0x6]; 3978 u8 shampo_match_criteria_type[0x2]; 3979 u8 reservation_timeout[0x10]; 3980 3981 u8 reserved_at_140[0x40]; 3982 3983 struct mlx5_ifc_wq_bits wq; 3984 }; 3985 3986 enum { 3987 MLX5_RMPC_STATE_RDY = 0x1, 3988 MLX5_RMPC_STATE_ERR = 0x3, 3989 }; 3990 3991 struct mlx5_ifc_rmpc_bits { 3992 u8 reserved_at_0[0x8]; 3993 u8 state[0x4]; 3994 u8 reserved_at_c[0x14]; 3995 3996 u8 basic_cyclic_rcv_wqe[0x1]; 3997 u8 reserved_at_21[0x1f]; 3998 3999 u8 reserved_at_40[0x140]; 4000 4001 struct mlx5_ifc_wq_bits wq; 4002 }; 4003 4004 enum { 4005 VHCA_ID_TYPE_HW = 0, 4006 VHCA_ID_TYPE_SW = 1, 4007 }; 4008 4009 struct mlx5_ifc_nic_vport_context_bits { 4010 u8 reserved_at_0[0x5]; 4011 u8 min_wqe_inline_mode[0x3]; 4012 u8 reserved_at_8[0x15]; 4013 u8 disable_mc_local_lb[0x1]; 4014 u8 disable_uc_local_lb[0x1]; 4015 u8 roce_en[0x1]; 4016 4017 u8 arm_change_event[0x1]; 4018 u8 reserved_at_21[0x1a]; 4019 u8 event_on_mtu[0x1]; 4020 u8 event_on_promisc_change[0x1]; 4021 u8 event_on_vlan_change[0x1]; 4022 u8 event_on_mc_address_change[0x1]; 4023 u8 event_on_uc_address_change[0x1]; 4024 4025 u8 vhca_id_type[0x1]; 4026 u8 reserved_at_41[0xb]; 4027 u8 affiliation_criteria[0x4]; 4028 u8 affiliated_vhca_id[0x10]; 4029 4030 u8 reserved_at_60[0xd0]; 4031 4032 u8 mtu[0x10]; 4033 4034 u8 system_image_guid[0x40]; 4035 u8 port_guid[0x40]; 4036 u8 node_guid[0x40]; 4037 4038 u8 reserved_at_200[0x140]; 4039 u8 qkey_violation_counter[0x10]; 4040 u8 reserved_at_350[0x430]; 4041 4042 u8 promisc_uc[0x1]; 4043 u8 promisc_mc[0x1]; 4044 u8 promisc_all[0x1]; 4045 u8 reserved_at_783[0x2]; 4046 u8 allowed_list_type[0x3]; 4047 u8 reserved_at_788[0xc]; 4048 u8 allowed_list_size[0xc]; 4049 4050 struct mlx5_ifc_mac_address_layout_bits permanent_address; 4051 4052 u8 reserved_at_7e0[0x20]; 4053 4054 u8 current_uc_mac_address[][0x40]; 4055 }; 4056 4057 enum { 4058 MLX5_MKC_ACCESS_MODE_PA = 0x0, 4059 MLX5_MKC_ACCESS_MODE_MTT = 0x1, 4060 MLX5_MKC_ACCESS_MODE_KLMS = 0x2, 4061 MLX5_MKC_ACCESS_MODE_KSM = 0x3, 4062 MLX5_MKC_ACCESS_MODE_SW_ICM = 0x4, 4063 MLX5_MKC_ACCESS_MODE_MEMIC = 0x5, 4064 }; 4065 4066 struct mlx5_ifc_mkc_bits { 4067 u8 reserved_at_0[0x1]; 4068 u8 free[0x1]; 4069 u8 reserved_at_2[0x1]; 4070 u8 access_mode_4_2[0x3]; 4071 u8 reserved_at_6[0x7]; 4072 u8 relaxed_ordering_write[0x1]; 4073 u8 reserved_at_e[0x1]; 4074 u8 small_fence_on_rdma_read_response[0x1]; 4075 u8 umr_en[0x1]; 4076 u8 a[0x1]; 4077 u8 rw[0x1]; 4078 u8 rr[0x1]; 4079 u8 lw[0x1]; 4080 u8 lr[0x1]; 4081 u8 access_mode_1_0[0x2]; 4082 u8 reserved_at_18[0x2]; 4083 u8 ma_translation_mode[0x2]; 4084 u8 reserved_at_1c[0x4]; 4085 4086 u8 qpn[0x18]; 4087 u8 mkey_7_0[0x8]; 4088 4089 u8 reserved_at_40[0x20]; 4090 4091 u8 length64[0x1]; 4092 u8 bsf_en[0x1]; 4093 u8 sync_umr[0x1]; 4094 u8 reserved_at_63[0x2]; 4095 u8 expected_sigerr_count[0x1]; 4096 u8 reserved_at_66[0x1]; 4097 u8 en_rinval[0x1]; 4098 u8 pd[0x18]; 4099 4100 u8 start_addr[0x40]; 4101 4102 u8 len[0x40]; 4103 4104 u8 bsf_octword_size[0x20]; 4105 4106 u8 reserved_at_120[0x80]; 4107 4108 u8 translations_octword_size[0x20]; 4109 4110 u8 reserved_at_1c0[0x19]; 4111 u8 relaxed_ordering_read[0x1]; 4112 u8 reserved_at_1d9[0x1]; 4113 u8 log_page_size[0x5]; 4114 4115 u8 reserved_at_1e0[0x20]; 4116 }; 4117 4118 struct mlx5_ifc_pkey_bits { 4119 u8 reserved_at_0[0x10]; 4120 u8 pkey[0x10]; 4121 }; 4122 4123 struct mlx5_ifc_array128_auto_bits { 4124 u8 array128_auto[16][0x8]; 4125 }; 4126 4127 struct mlx5_ifc_hca_vport_context_bits { 4128 u8 field_select[0x20]; 4129 4130 u8 reserved_at_20[0xe0]; 4131 4132 u8 sm_virt_aware[0x1]; 4133 u8 has_smi[0x1]; 4134 u8 has_raw[0x1]; 4135 u8 grh_required[0x1]; 4136 u8 reserved_at_104[0xc]; 4137 u8 port_physical_state[0x4]; 4138 u8 vport_state_policy[0x4]; 4139 u8 port_state[0x4]; 4140 u8 vport_state[0x4]; 4141 4142 u8 reserved_at_120[0x20]; 4143 4144 u8 system_image_guid[0x40]; 4145 4146 u8 port_guid[0x40]; 4147 4148 u8 node_guid[0x40]; 4149 4150 u8 cap_mask1[0x20]; 4151 4152 u8 cap_mask1_field_select[0x20]; 4153 4154 u8 cap_mask2[0x20]; 4155 4156 u8 cap_mask2_field_select[0x20]; 4157 4158 u8 reserved_at_280[0x80]; 4159 4160 u8 lid[0x10]; 4161 u8 reserved_at_310[0x4]; 4162 u8 init_type_reply[0x4]; 4163 u8 lmc[0x3]; 4164 u8 subnet_timeout[0x5]; 4165 4166 u8 sm_lid[0x10]; 4167 u8 sm_sl[0x4]; 4168 u8 reserved_at_334[0xc]; 4169 4170 u8 qkey_violation_counter[0x10]; 4171 u8 pkey_violation_counter[0x10]; 4172 4173 u8 reserved_at_360[0xca0]; 4174 }; 4175 4176 struct mlx5_ifc_esw_vport_context_bits { 4177 u8 fdb_to_vport_reg_c[0x1]; 4178 u8 reserved_at_1[0x2]; 4179 u8 vport_svlan_strip[0x1]; 4180 u8 vport_cvlan_strip[0x1]; 4181 u8 vport_svlan_insert[0x1]; 4182 u8 vport_cvlan_insert[0x2]; 4183 u8 fdb_to_vport_reg_c_id[0x8]; 4184 u8 reserved_at_10[0x10]; 4185 4186 u8 reserved_at_20[0x20]; 4187 4188 u8 svlan_cfi[0x1]; 4189 u8 svlan_pcp[0x3]; 4190 u8 svlan_id[0xc]; 4191 u8 cvlan_cfi[0x1]; 4192 u8 cvlan_pcp[0x3]; 4193 u8 cvlan_id[0xc]; 4194 4195 u8 reserved_at_60[0x720]; 4196 4197 u8 sw_steering_vport_icm_address_rx[0x40]; 4198 4199 u8 sw_steering_vport_icm_address_tx[0x40]; 4200 }; 4201 4202 enum { 4203 MLX5_EQC_STATUS_OK = 0x0, 4204 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa, 4205 }; 4206 4207 enum { 4208 MLX5_EQC_ST_ARMED = 0x9, 4209 MLX5_EQC_ST_FIRED = 0xa, 4210 }; 4211 4212 struct mlx5_ifc_eqc_bits { 4213 u8 status[0x4]; 4214 u8 reserved_at_4[0x9]; 4215 u8 ec[0x1]; 4216 u8 oi[0x1]; 4217 u8 reserved_at_f[0x5]; 4218 u8 st[0x4]; 4219 u8 reserved_at_18[0x8]; 4220 4221 u8 reserved_at_20[0x20]; 4222 4223 u8 reserved_at_40[0x14]; 4224 u8 page_offset[0x6]; 4225 u8 reserved_at_5a[0x6]; 4226 4227 u8 reserved_at_60[0x3]; 4228 u8 log_eq_size[0x5]; 4229 u8 uar_page[0x18]; 4230 4231 u8 reserved_at_80[0x20]; 4232 4233 u8 reserved_at_a0[0x14]; 4234 u8 intr[0xc]; 4235 4236 u8 reserved_at_c0[0x3]; 4237 u8 log_page_size[0x5]; 4238 u8 reserved_at_c8[0x18]; 4239 4240 u8 reserved_at_e0[0x60]; 4241 4242 u8 reserved_at_140[0x8]; 4243 u8 consumer_counter[0x18]; 4244 4245 u8 reserved_at_160[0x8]; 4246 u8 producer_counter[0x18]; 4247 4248 u8 reserved_at_180[0x80]; 4249 }; 4250 4251 enum { 4252 MLX5_DCTC_STATE_ACTIVE = 0x0, 4253 MLX5_DCTC_STATE_DRAINING = 0x1, 4254 MLX5_DCTC_STATE_DRAINED = 0x2, 4255 }; 4256 4257 enum { 4258 MLX5_DCTC_CS_RES_DISABLE = 0x0, 4259 MLX5_DCTC_CS_RES_NA = 0x1, 4260 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2, 4261 }; 4262 4263 enum { 4264 MLX5_DCTC_MTU_256_BYTES = 0x1, 4265 MLX5_DCTC_MTU_512_BYTES = 0x2, 4266 MLX5_DCTC_MTU_1K_BYTES = 0x3, 4267 MLX5_DCTC_MTU_2K_BYTES = 0x4, 4268 MLX5_DCTC_MTU_4K_BYTES = 0x5, 4269 }; 4270 4271 struct mlx5_ifc_dctc_bits { 4272 u8 reserved_at_0[0x4]; 4273 u8 state[0x4]; 4274 u8 reserved_at_8[0x18]; 4275 4276 u8 reserved_at_20[0x8]; 4277 u8 user_index[0x18]; 4278 4279 u8 reserved_at_40[0x8]; 4280 u8 cqn[0x18]; 4281 4282 u8 counter_set_id[0x8]; 4283 u8 atomic_mode[0x4]; 4284 u8 rre[0x1]; 4285 u8 rwe[0x1]; 4286 u8 rae[0x1]; 4287 u8 atomic_like_write_en[0x1]; 4288 u8 latency_sensitive[0x1]; 4289 u8 rlky[0x1]; 4290 u8 free_ar[0x1]; 4291 u8 reserved_at_73[0xd]; 4292 4293 u8 reserved_at_80[0x8]; 4294 u8 cs_res[0x8]; 4295 u8 reserved_at_90[0x3]; 4296 u8 min_rnr_nak[0x5]; 4297 u8 reserved_at_98[0x8]; 4298 4299 u8 reserved_at_a0[0x8]; 4300 u8 srqn_xrqn[0x18]; 4301 4302 u8 reserved_at_c0[0x8]; 4303 u8 pd[0x18]; 4304 4305 u8 tclass[0x8]; 4306 u8 reserved_at_e8[0x4]; 4307 u8 flow_label[0x14]; 4308 4309 u8 dc_access_key[0x40]; 4310 4311 u8 reserved_at_140[0x5]; 4312 u8 mtu[0x3]; 4313 u8 port[0x8]; 4314 u8 pkey_index[0x10]; 4315 4316 u8 reserved_at_160[0x8]; 4317 u8 my_addr_index[0x8]; 4318 u8 reserved_at_170[0x8]; 4319 u8 hop_limit[0x8]; 4320 4321 u8 dc_access_key_violation_count[0x20]; 4322 4323 u8 reserved_at_1a0[0x14]; 4324 u8 dei_cfi[0x1]; 4325 u8 eth_prio[0x3]; 4326 u8 ecn[0x2]; 4327 u8 dscp[0x6]; 4328 4329 u8 reserved_at_1c0[0x20]; 4330 u8 ece[0x20]; 4331 }; 4332 4333 enum { 4334 MLX5_CQC_STATUS_OK = 0x0, 4335 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9, 4336 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa, 4337 }; 4338 4339 enum { 4340 MLX5_CQC_CQE_SZ_64_BYTES = 0x0, 4341 MLX5_CQC_CQE_SZ_128_BYTES = 0x1, 4342 }; 4343 4344 enum { 4345 MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED = 0x6, 4346 MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED = 0x9, 4347 MLX5_CQC_ST_FIRED = 0xa, 4348 }; 4349 4350 enum { 4351 MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0, 4352 MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1, 4353 MLX5_CQ_PERIOD_NUM_MODES 4354 }; 4355 4356 struct mlx5_ifc_cqc_bits { 4357 u8 status[0x4]; 4358 u8 reserved_at_4[0x2]; 4359 u8 dbr_umem_valid[0x1]; 4360 u8 apu_cq[0x1]; 4361 u8 cqe_sz[0x3]; 4362 u8 cc[0x1]; 4363 u8 reserved_at_c[0x1]; 4364 u8 scqe_break_moderation_en[0x1]; 4365 u8 oi[0x1]; 4366 u8 cq_period_mode[0x2]; 4367 u8 cqe_comp_en[0x1]; 4368 u8 mini_cqe_res_format[0x2]; 4369 u8 st[0x4]; 4370 u8 reserved_at_18[0x6]; 4371 u8 cqe_compression_layout[0x2]; 4372 4373 u8 reserved_at_20[0x20]; 4374 4375 u8 reserved_at_40[0x14]; 4376 u8 page_offset[0x6]; 4377 u8 reserved_at_5a[0x6]; 4378 4379 u8 reserved_at_60[0x3]; 4380 u8 log_cq_size[0x5]; 4381 u8 uar_page[0x18]; 4382 4383 u8 reserved_at_80[0x4]; 4384 u8 cq_period[0xc]; 4385 u8 cq_max_count[0x10]; 4386 4387 u8 c_eqn_or_apu_element[0x20]; 4388 4389 u8 reserved_at_c0[0x3]; 4390 u8 log_page_size[0x5]; 4391 u8 reserved_at_c8[0x18]; 4392 4393 u8 reserved_at_e0[0x20]; 4394 4395 u8 reserved_at_100[0x8]; 4396 u8 last_notified_index[0x18]; 4397 4398 u8 reserved_at_120[0x8]; 4399 u8 last_solicit_index[0x18]; 4400 4401 u8 reserved_at_140[0x8]; 4402 u8 consumer_counter[0x18]; 4403 4404 u8 reserved_at_160[0x8]; 4405 u8 producer_counter[0x18]; 4406 4407 u8 reserved_at_180[0x40]; 4408 4409 u8 dbr_addr[0x40]; 4410 }; 4411 4412 union mlx5_ifc_cong_control_roce_ecn_auto_bits { 4413 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp; 4414 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp; 4415 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np; 4416 struct mlx5_ifc_cong_control_r_roce_general_bits cong_control_r_roce_general; 4417 u8 reserved_at_0[0x800]; 4418 }; 4419 4420 struct mlx5_ifc_query_adapter_param_block_bits { 4421 u8 reserved_at_0[0xc0]; 4422 4423 u8 reserved_at_c0[0x8]; 4424 u8 ieee_vendor_id[0x18]; 4425 4426 u8 reserved_at_e0[0x10]; 4427 u8 vsd_vendor_id[0x10]; 4428 4429 u8 vsd[208][0x8]; 4430 4431 u8 vsd_contd_psid[16][0x8]; 4432 }; 4433 4434 enum { 4435 MLX5_XRQC_STATE_GOOD = 0x0, 4436 MLX5_XRQC_STATE_ERROR = 0x1, 4437 }; 4438 4439 enum { 4440 MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0, 4441 MLX5_XRQC_TOPOLOGY_TAG_MATCHING = 0x1, 4442 }; 4443 4444 enum { 4445 MLX5_XRQC_OFFLOAD_RNDV = 0x1, 4446 }; 4447 4448 struct mlx5_ifc_tag_matching_topology_context_bits { 4449 u8 log_matching_list_sz[0x4]; 4450 u8 reserved_at_4[0xc]; 4451 u8 append_next_index[0x10]; 4452 4453 u8 sw_phase_cnt[0x10]; 4454 u8 hw_phase_cnt[0x10]; 4455 4456 u8 reserved_at_40[0x40]; 4457 }; 4458 4459 struct mlx5_ifc_xrqc_bits { 4460 u8 state[0x4]; 4461 u8 rlkey[0x1]; 4462 u8 reserved_at_5[0xf]; 4463 u8 topology[0x4]; 4464 u8 reserved_at_18[0x4]; 4465 u8 offload[0x4]; 4466 4467 u8 reserved_at_20[0x8]; 4468 u8 user_index[0x18]; 4469 4470 u8 reserved_at_40[0x8]; 4471 u8 cqn[0x18]; 4472 4473 u8 reserved_at_60[0xa0]; 4474 4475 struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context; 4476 4477 u8 reserved_at_180[0x280]; 4478 4479 struct mlx5_ifc_wq_bits wq; 4480 }; 4481 4482 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits { 4483 struct mlx5_ifc_modify_field_select_bits modify_field_select; 4484 struct mlx5_ifc_resize_field_select_bits resize_field_select; 4485 u8 reserved_at_0[0x20]; 4486 }; 4487 4488 union mlx5_ifc_field_select_802_1_r_roce_auto_bits { 4489 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp; 4490 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp; 4491 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np; 4492 u8 reserved_at_0[0x20]; 4493 }; 4494 4495 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits { 4496 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 4497 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 4498 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 4499 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 4500 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 4501 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 4502 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout; 4503 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout; 4504 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 4505 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 4506 struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs; 4507 u8 reserved_at_0[0x7c0]; 4508 }; 4509 4510 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits { 4511 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout; 4512 u8 reserved_at_0[0x7c0]; 4513 }; 4514 4515 union mlx5_ifc_event_auto_bits { 4516 struct mlx5_ifc_comp_event_bits comp_event; 4517 struct mlx5_ifc_dct_events_bits dct_events; 4518 struct mlx5_ifc_qp_events_bits qp_events; 4519 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event; 4520 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event; 4521 struct mlx5_ifc_cq_error_bits cq_error; 4522 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged; 4523 struct mlx5_ifc_port_state_change_event_bits port_state_change_event; 4524 struct mlx5_ifc_gpio_event_bits gpio_event; 4525 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event; 4526 struct mlx5_ifc_stall_vl_event_bits stall_vl_event; 4527 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event; 4528 u8 reserved_at_0[0xe0]; 4529 }; 4530 4531 struct mlx5_ifc_health_buffer_bits { 4532 u8 reserved_at_0[0x100]; 4533 4534 u8 assert_existptr[0x20]; 4535 4536 u8 assert_callra[0x20]; 4537 4538 u8 reserved_at_140[0x20]; 4539 4540 u8 time[0x20]; 4541 4542 u8 fw_version[0x20]; 4543 4544 u8 hw_id[0x20]; 4545 4546 u8 rfr[0x1]; 4547 u8 reserved_at_1c1[0x3]; 4548 u8 valid[0x1]; 4549 u8 severity[0x3]; 4550 u8 reserved_at_1c8[0x18]; 4551 4552 u8 irisc_index[0x8]; 4553 u8 synd[0x8]; 4554 u8 ext_synd[0x10]; 4555 }; 4556 4557 struct mlx5_ifc_register_loopback_control_bits { 4558 u8 no_lb[0x1]; 4559 u8 reserved_at_1[0x7]; 4560 u8 port[0x8]; 4561 u8 reserved_at_10[0x10]; 4562 4563 u8 reserved_at_20[0x60]; 4564 }; 4565 4566 struct mlx5_ifc_vport_tc_element_bits { 4567 u8 traffic_class[0x4]; 4568 u8 reserved_at_4[0xc]; 4569 u8 vport_number[0x10]; 4570 }; 4571 4572 struct mlx5_ifc_vport_element_bits { 4573 u8 reserved_at_0[0x10]; 4574 u8 vport_number[0x10]; 4575 }; 4576 4577 enum { 4578 TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0, 4579 TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1, 4580 TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2, 4581 }; 4582 4583 struct mlx5_ifc_tsar_element_bits { 4584 u8 reserved_at_0[0x8]; 4585 u8 tsar_type[0x8]; 4586 u8 reserved_at_10[0x10]; 4587 }; 4588 4589 enum { 4590 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0, 4591 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1, 4592 }; 4593 4594 struct mlx5_ifc_teardown_hca_out_bits { 4595 u8 status[0x8]; 4596 u8 reserved_at_8[0x18]; 4597 4598 u8 syndrome[0x20]; 4599 4600 u8 reserved_at_40[0x3f]; 4601 4602 u8 state[0x1]; 4603 }; 4604 4605 enum { 4606 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0, 4607 MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE = 0x1, 4608 MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN = 0x2, 4609 }; 4610 4611 struct mlx5_ifc_teardown_hca_in_bits { 4612 u8 opcode[0x10]; 4613 u8 reserved_at_10[0x10]; 4614 4615 u8 reserved_at_20[0x10]; 4616 u8 op_mod[0x10]; 4617 4618 u8 reserved_at_40[0x10]; 4619 u8 profile[0x10]; 4620 4621 u8 reserved_at_60[0x20]; 4622 }; 4623 4624 struct mlx5_ifc_sqerr2rts_qp_out_bits { 4625 u8 status[0x8]; 4626 u8 reserved_at_8[0x18]; 4627 4628 u8 syndrome[0x20]; 4629 4630 u8 reserved_at_40[0x40]; 4631 }; 4632 4633 struct mlx5_ifc_sqerr2rts_qp_in_bits { 4634 u8 opcode[0x10]; 4635 u8 uid[0x10]; 4636 4637 u8 reserved_at_20[0x10]; 4638 u8 op_mod[0x10]; 4639 4640 u8 reserved_at_40[0x8]; 4641 u8 qpn[0x18]; 4642 4643 u8 reserved_at_60[0x20]; 4644 4645 u8 opt_param_mask[0x20]; 4646 4647 u8 reserved_at_a0[0x20]; 4648 4649 struct mlx5_ifc_qpc_bits qpc; 4650 4651 u8 reserved_at_800[0x80]; 4652 }; 4653 4654 struct mlx5_ifc_sqd2rts_qp_out_bits { 4655 u8 status[0x8]; 4656 u8 reserved_at_8[0x18]; 4657 4658 u8 syndrome[0x20]; 4659 4660 u8 reserved_at_40[0x40]; 4661 }; 4662 4663 struct mlx5_ifc_sqd2rts_qp_in_bits { 4664 u8 opcode[0x10]; 4665 u8 uid[0x10]; 4666 4667 u8 reserved_at_20[0x10]; 4668 u8 op_mod[0x10]; 4669 4670 u8 reserved_at_40[0x8]; 4671 u8 qpn[0x18]; 4672 4673 u8 reserved_at_60[0x20]; 4674 4675 u8 opt_param_mask[0x20]; 4676 4677 u8 reserved_at_a0[0x20]; 4678 4679 struct mlx5_ifc_qpc_bits qpc; 4680 4681 u8 reserved_at_800[0x80]; 4682 }; 4683 4684 struct mlx5_ifc_set_roce_address_out_bits { 4685 u8 status[0x8]; 4686 u8 reserved_at_8[0x18]; 4687 4688 u8 syndrome[0x20]; 4689 4690 u8 reserved_at_40[0x40]; 4691 }; 4692 4693 struct mlx5_ifc_set_roce_address_in_bits { 4694 u8 opcode[0x10]; 4695 u8 reserved_at_10[0x10]; 4696 4697 u8 reserved_at_20[0x10]; 4698 u8 op_mod[0x10]; 4699 4700 u8 roce_address_index[0x10]; 4701 u8 reserved_at_50[0xc]; 4702 u8 vhca_port_num[0x4]; 4703 4704 u8 reserved_at_60[0x20]; 4705 4706 struct mlx5_ifc_roce_addr_layout_bits roce_address; 4707 }; 4708 4709 struct mlx5_ifc_set_mad_demux_out_bits { 4710 u8 status[0x8]; 4711 u8 reserved_at_8[0x18]; 4712 4713 u8 syndrome[0x20]; 4714 4715 u8 reserved_at_40[0x40]; 4716 }; 4717 4718 enum { 4719 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0, 4720 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2, 4721 }; 4722 4723 struct mlx5_ifc_set_mad_demux_in_bits { 4724 u8 opcode[0x10]; 4725 u8 reserved_at_10[0x10]; 4726 4727 u8 reserved_at_20[0x10]; 4728 u8 op_mod[0x10]; 4729 4730 u8 reserved_at_40[0x20]; 4731 4732 u8 reserved_at_60[0x6]; 4733 u8 demux_mode[0x2]; 4734 u8 reserved_at_68[0x18]; 4735 }; 4736 4737 struct mlx5_ifc_set_l2_table_entry_out_bits { 4738 u8 status[0x8]; 4739 u8 reserved_at_8[0x18]; 4740 4741 u8 syndrome[0x20]; 4742 4743 u8 reserved_at_40[0x40]; 4744 }; 4745 4746 struct mlx5_ifc_set_l2_table_entry_in_bits { 4747 u8 opcode[0x10]; 4748 u8 reserved_at_10[0x10]; 4749 4750 u8 reserved_at_20[0x10]; 4751 u8 op_mod[0x10]; 4752 4753 u8 reserved_at_40[0x60]; 4754 4755 u8 reserved_at_a0[0x8]; 4756 u8 table_index[0x18]; 4757 4758 u8 reserved_at_c0[0x20]; 4759 4760 u8 reserved_at_e0[0x13]; 4761 u8 vlan_valid[0x1]; 4762 u8 vlan[0xc]; 4763 4764 struct mlx5_ifc_mac_address_layout_bits mac_address; 4765 4766 u8 reserved_at_140[0xc0]; 4767 }; 4768 4769 struct mlx5_ifc_set_issi_out_bits { 4770 u8 status[0x8]; 4771 u8 reserved_at_8[0x18]; 4772 4773 u8 syndrome[0x20]; 4774 4775 u8 reserved_at_40[0x40]; 4776 }; 4777 4778 struct mlx5_ifc_set_issi_in_bits { 4779 u8 opcode[0x10]; 4780 u8 reserved_at_10[0x10]; 4781 4782 u8 reserved_at_20[0x10]; 4783 u8 op_mod[0x10]; 4784 4785 u8 reserved_at_40[0x10]; 4786 u8 current_issi[0x10]; 4787 4788 u8 reserved_at_60[0x20]; 4789 }; 4790 4791 struct mlx5_ifc_set_hca_cap_out_bits { 4792 u8 status[0x8]; 4793 u8 reserved_at_8[0x18]; 4794 4795 u8 syndrome[0x20]; 4796 4797 u8 reserved_at_40[0x40]; 4798 }; 4799 4800 struct mlx5_ifc_set_hca_cap_in_bits { 4801 u8 opcode[0x10]; 4802 u8 reserved_at_10[0x10]; 4803 4804 u8 reserved_at_20[0x10]; 4805 u8 op_mod[0x10]; 4806 4807 u8 other_function[0x1]; 4808 u8 reserved_at_41[0xf]; 4809 u8 function_id[0x10]; 4810 4811 u8 reserved_at_60[0x20]; 4812 4813 union mlx5_ifc_hca_cap_union_bits capability; 4814 }; 4815 4816 enum { 4817 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0, 4818 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1, 4819 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2, 4820 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3, 4821 MLX5_SET_FTE_MODIFY_ENABLE_MASK_IPSEC_OBJ_ID = 0x4 4822 }; 4823 4824 struct mlx5_ifc_set_fte_out_bits { 4825 u8 status[0x8]; 4826 u8 reserved_at_8[0x18]; 4827 4828 u8 syndrome[0x20]; 4829 4830 u8 reserved_at_40[0x40]; 4831 }; 4832 4833 struct mlx5_ifc_set_fte_in_bits { 4834 u8 opcode[0x10]; 4835 u8 reserved_at_10[0x10]; 4836 4837 u8 reserved_at_20[0x10]; 4838 u8 op_mod[0x10]; 4839 4840 u8 other_vport[0x1]; 4841 u8 reserved_at_41[0xf]; 4842 u8 vport_number[0x10]; 4843 4844 u8 reserved_at_60[0x20]; 4845 4846 u8 table_type[0x8]; 4847 u8 reserved_at_88[0x18]; 4848 4849 u8 reserved_at_a0[0x8]; 4850 u8 table_id[0x18]; 4851 4852 u8 ignore_flow_level[0x1]; 4853 u8 reserved_at_c1[0x17]; 4854 u8 modify_enable_mask[0x8]; 4855 4856 u8 reserved_at_e0[0x20]; 4857 4858 u8 flow_index[0x20]; 4859 4860 u8 reserved_at_120[0xe0]; 4861 4862 struct mlx5_ifc_flow_context_bits flow_context; 4863 }; 4864 4865 struct mlx5_ifc_rts2rts_qp_out_bits { 4866 u8 status[0x8]; 4867 u8 reserved_at_8[0x18]; 4868 4869 u8 syndrome[0x20]; 4870 4871 u8 reserved_at_40[0x20]; 4872 u8 ece[0x20]; 4873 }; 4874 4875 struct mlx5_ifc_rts2rts_qp_in_bits { 4876 u8 opcode[0x10]; 4877 u8 uid[0x10]; 4878 4879 u8 reserved_at_20[0x10]; 4880 u8 op_mod[0x10]; 4881 4882 u8 reserved_at_40[0x8]; 4883 u8 qpn[0x18]; 4884 4885 u8 reserved_at_60[0x20]; 4886 4887 u8 opt_param_mask[0x20]; 4888 4889 u8 ece[0x20]; 4890 4891 struct mlx5_ifc_qpc_bits qpc; 4892 4893 u8 reserved_at_800[0x80]; 4894 }; 4895 4896 struct mlx5_ifc_rtr2rts_qp_out_bits { 4897 u8 status[0x8]; 4898 u8 reserved_at_8[0x18]; 4899 4900 u8 syndrome[0x20]; 4901 4902 u8 reserved_at_40[0x20]; 4903 u8 ece[0x20]; 4904 }; 4905 4906 struct mlx5_ifc_rtr2rts_qp_in_bits { 4907 u8 opcode[0x10]; 4908 u8 uid[0x10]; 4909 4910 u8 reserved_at_20[0x10]; 4911 u8 op_mod[0x10]; 4912 4913 u8 reserved_at_40[0x8]; 4914 u8 qpn[0x18]; 4915 4916 u8 reserved_at_60[0x20]; 4917 4918 u8 opt_param_mask[0x20]; 4919 4920 u8 ece[0x20]; 4921 4922 struct mlx5_ifc_qpc_bits qpc; 4923 4924 u8 reserved_at_800[0x80]; 4925 }; 4926 4927 struct mlx5_ifc_rst2init_qp_out_bits { 4928 u8 status[0x8]; 4929 u8 reserved_at_8[0x18]; 4930 4931 u8 syndrome[0x20]; 4932 4933 u8 reserved_at_40[0x20]; 4934 u8 ece[0x20]; 4935 }; 4936 4937 struct mlx5_ifc_rst2init_qp_in_bits { 4938 u8 opcode[0x10]; 4939 u8 uid[0x10]; 4940 4941 u8 reserved_at_20[0x10]; 4942 u8 op_mod[0x10]; 4943 4944 u8 reserved_at_40[0x8]; 4945 u8 qpn[0x18]; 4946 4947 u8 reserved_at_60[0x20]; 4948 4949 u8 opt_param_mask[0x20]; 4950 4951 u8 ece[0x20]; 4952 4953 struct mlx5_ifc_qpc_bits qpc; 4954 4955 u8 reserved_at_800[0x80]; 4956 }; 4957 4958 struct mlx5_ifc_query_xrq_out_bits { 4959 u8 status[0x8]; 4960 u8 reserved_at_8[0x18]; 4961 4962 u8 syndrome[0x20]; 4963 4964 u8 reserved_at_40[0x40]; 4965 4966 struct mlx5_ifc_xrqc_bits xrq_context; 4967 }; 4968 4969 struct mlx5_ifc_query_xrq_in_bits { 4970 u8 opcode[0x10]; 4971 u8 reserved_at_10[0x10]; 4972 4973 u8 reserved_at_20[0x10]; 4974 u8 op_mod[0x10]; 4975 4976 u8 reserved_at_40[0x8]; 4977 u8 xrqn[0x18]; 4978 4979 u8 reserved_at_60[0x20]; 4980 }; 4981 4982 struct mlx5_ifc_query_xrc_srq_out_bits { 4983 u8 status[0x8]; 4984 u8 reserved_at_8[0x18]; 4985 4986 u8 syndrome[0x20]; 4987 4988 u8 reserved_at_40[0x40]; 4989 4990 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 4991 4992 u8 reserved_at_280[0x600]; 4993 4994 u8 pas[][0x40]; 4995 }; 4996 4997 struct mlx5_ifc_query_xrc_srq_in_bits { 4998 u8 opcode[0x10]; 4999 u8 reserved_at_10[0x10]; 5000 5001 u8 reserved_at_20[0x10]; 5002 u8 op_mod[0x10]; 5003 5004 u8 reserved_at_40[0x8]; 5005 u8 xrc_srqn[0x18]; 5006 5007 u8 reserved_at_60[0x20]; 5008 }; 5009 5010 enum { 5011 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0, 5012 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1, 5013 }; 5014 5015 struct mlx5_ifc_query_vport_state_out_bits { 5016 u8 status[0x8]; 5017 u8 reserved_at_8[0x18]; 5018 5019 u8 syndrome[0x20]; 5020 5021 u8 reserved_at_40[0x20]; 5022 5023 u8 reserved_at_60[0x18]; 5024 u8 admin_state[0x4]; 5025 u8 state[0x4]; 5026 }; 5027 5028 enum { 5029 MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT = 0x0, 5030 MLX5_VPORT_STATE_OP_MOD_ESW_VPORT = 0x1, 5031 MLX5_VPORT_STATE_OP_MOD_UPLINK = 0x2, 5032 }; 5033 5034 struct mlx5_ifc_arm_monitor_counter_in_bits { 5035 u8 opcode[0x10]; 5036 u8 uid[0x10]; 5037 5038 u8 reserved_at_20[0x10]; 5039 u8 op_mod[0x10]; 5040 5041 u8 reserved_at_40[0x20]; 5042 5043 u8 reserved_at_60[0x20]; 5044 }; 5045 5046 struct mlx5_ifc_arm_monitor_counter_out_bits { 5047 u8 status[0x8]; 5048 u8 reserved_at_8[0x18]; 5049 5050 u8 syndrome[0x20]; 5051 5052 u8 reserved_at_40[0x40]; 5053 }; 5054 5055 enum { 5056 MLX5_QUERY_MONITOR_CNT_TYPE_PPCNT = 0x0, 5057 MLX5_QUERY_MONITOR_CNT_TYPE_Q_COUNTER = 0x1, 5058 }; 5059 5060 enum mlx5_monitor_counter_ppcnt { 5061 MLX5_QUERY_MONITOR_PPCNT_IN_RANGE_LENGTH_ERRORS = 0x0, 5062 MLX5_QUERY_MONITOR_PPCNT_OUT_OF_RANGE_LENGTH_FIELD = 0x1, 5063 MLX5_QUERY_MONITOR_PPCNT_FRAME_TOO_LONG_ERRORS = 0x2, 5064 MLX5_QUERY_MONITOR_PPCNT_FRAME_CHECK_SEQUENCE_ERRORS = 0x3, 5065 MLX5_QUERY_MONITOR_PPCNT_ALIGNMENT_ERRORS = 0x4, 5066 MLX5_QUERY_MONITOR_PPCNT_IF_OUT_DISCARDS = 0x5, 5067 }; 5068 5069 enum { 5070 MLX5_QUERY_MONITOR_Q_COUNTER_RX_OUT_OF_BUFFER = 0x4, 5071 }; 5072 5073 struct mlx5_ifc_monitor_counter_output_bits { 5074 u8 reserved_at_0[0x4]; 5075 u8 type[0x4]; 5076 u8 reserved_at_8[0x8]; 5077 u8 counter[0x10]; 5078 5079 u8 counter_group_id[0x20]; 5080 }; 5081 5082 #define MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 (6) 5083 #define MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1 (1) 5084 #define MLX5_CMD_SET_MONITOR_NUM_COUNTER (MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 +\ 5085 MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1) 5086 5087 struct mlx5_ifc_set_monitor_counter_in_bits { 5088 u8 opcode[0x10]; 5089 u8 uid[0x10]; 5090 5091 u8 reserved_at_20[0x10]; 5092 u8 op_mod[0x10]; 5093 5094 u8 reserved_at_40[0x10]; 5095 u8 num_of_counters[0x10]; 5096 5097 u8 reserved_at_60[0x20]; 5098 5099 struct mlx5_ifc_monitor_counter_output_bits monitor_counter[MLX5_CMD_SET_MONITOR_NUM_COUNTER]; 5100 }; 5101 5102 struct mlx5_ifc_set_monitor_counter_out_bits { 5103 u8 status[0x8]; 5104 u8 reserved_at_8[0x18]; 5105 5106 u8 syndrome[0x20]; 5107 5108 u8 reserved_at_40[0x40]; 5109 }; 5110 5111 struct mlx5_ifc_query_vport_state_in_bits { 5112 u8 opcode[0x10]; 5113 u8 reserved_at_10[0x10]; 5114 5115 u8 reserved_at_20[0x10]; 5116 u8 op_mod[0x10]; 5117 5118 u8 other_vport[0x1]; 5119 u8 reserved_at_41[0xf]; 5120 u8 vport_number[0x10]; 5121 5122 u8 reserved_at_60[0x20]; 5123 }; 5124 5125 struct mlx5_ifc_query_vnic_env_out_bits { 5126 u8 status[0x8]; 5127 u8 reserved_at_8[0x18]; 5128 5129 u8 syndrome[0x20]; 5130 5131 u8 reserved_at_40[0x40]; 5132 5133 struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env; 5134 }; 5135 5136 enum { 5137 MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS = 0x0, 5138 }; 5139 5140 struct mlx5_ifc_query_vnic_env_in_bits { 5141 u8 opcode[0x10]; 5142 u8 reserved_at_10[0x10]; 5143 5144 u8 reserved_at_20[0x10]; 5145 u8 op_mod[0x10]; 5146 5147 u8 other_vport[0x1]; 5148 u8 reserved_at_41[0xf]; 5149 u8 vport_number[0x10]; 5150 5151 u8 reserved_at_60[0x20]; 5152 }; 5153 5154 struct mlx5_ifc_query_vport_counter_out_bits { 5155 u8 status[0x8]; 5156 u8 reserved_at_8[0x18]; 5157 5158 u8 syndrome[0x20]; 5159 5160 u8 reserved_at_40[0x40]; 5161 5162 struct mlx5_ifc_traffic_counter_bits received_errors; 5163 5164 struct mlx5_ifc_traffic_counter_bits transmit_errors; 5165 5166 struct mlx5_ifc_traffic_counter_bits received_ib_unicast; 5167 5168 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast; 5169 5170 struct mlx5_ifc_traffic_counter_bits received_ib_multicast; 5171 5172 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast; 5173 5174 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast; 5175 5176 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast; 5177 5178 struct mlx5_ifc_traffic_counter_bits received_eth_unicast; 5179 5180 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast; 5181 5182 struct mlx5_ifc_traffic_counter_bits received_eth_multicast; 5183 5184 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast; 5185 5186 u8 reserved_at_680[0xa00]; 5187 }; 5188 5189 enum { 5190 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0, 5191 }; 5192 5193 struct mlx5_ifc_query_vport_counter_in_bits { 5194 u8 opcode[0x10]; 5195 u8 reserved_at_10[0x10]; 5196 5197 u8 reserved_at_20[0x10]; 5198 u8 op_mod[0x10]; 5199 5200 u8 other_vport[0x1]; 5201 u8 reserved_at_41[0xb]; 5202 u8 port_num[0x4]; 5203 u8 vport_number[0x10]; 5204 5205 u8 reserved_at_60[0x60]; 5206 5207 u8 clear[0x1]; 5208 u8 reserved_at_c1[0x1f]; 5209 5210 u8 reserved_at_e0[0x20]; 5211 }; 5212 5213 struct mlx5_ifc_query_tis_out_bits { 5214 u8 status[0x8]; 5215 u8 reserved_at_8[0x18]; 5216 5217 u8 syndrome[0x20]; 5218 5219 u8 reserved_at_40[0x40]; 5220 5221 struct mlx5_ifc_tisc_bits tis_context; 5222 }; 5223 5224 struct mlx5_ifc_query_tis_in_bits { 5225 u8 opcode[0x10]; 5226 u8 reserved_at_10[0x10]; 5227 5228 u8 reserved_at_20[0x10]; 5229 u8 op_mod[0x10]; 5230 5231 u8 reserved_at_40[0x8]; 5232 u8 tisn[0x18]; 5233 5234 u8 reserved_at_60[0x20]; 5235 }; 5236 5237 struct mlx5_ifc_query_tir_out_bits { 5238 u8 status[0x8]; 5239 u8 reserved_at_8[0x18]; 5240 5241 u8 syndrome[0x20]; 5242 5243 u8 reserved_at_40[0xc0]; 5244 5245 struct mlx5_ifc_tirc_bits tir_context; 5246 }; 5247 5248 struct mlx5_ifc_query_tir_in_bits { 5249 u8 opcode[0x10]; 5250 u8 reserved_at_10[0x10]; 5251 5252 u8 reserved_at_20[0x10]; 5253 u8 op_mod[0x10]; 5254 5255 u8 reserved_at_40[0x8]; 5256 u8 tirn[0x18]; 5257 5258 u8 reserved_at_60[0x20]; 5259 }; 5260 5261 struct mlx5_ifc_query_srq_out_bits { 5262 u8 status[0x8]; 5263 u8 reserved_at_8[0x18]; 5264 5265 u8 syndrome[0x20]; 5266 5267 u8 reserved_at_40[0x40]; 5268 5269 struct mlx5_ifc_srqc_bits srq_context_entry; 5270 5271 u8 reserved_at_280[0x600]; 5272 5273 u8 pas[][0x40]; 5274 }; 5275 5276 struct mlx5_ifc_query_srq_in_bits { 5277 u8 opcode[0x10]; 5278 u8 reserved_at_10[0x10]; 5279 5280 u8 reserved_at_20[0x10]; 5281 u8 op_mod[0x10]; 5282 5283 u8 reserved_at_40[0x8]; 5284 u8 srqn[0x18]; 5285 5286 u8 reserved_at_60[0x20]; 5287 }; 5288 5289 struct mlx5_ifc_query_sq_out_bits { 5290 u8 status[0x8]; 5291 u8 reserved_at_8[0x18]; 5292 5293 u8 syndrome[0x20]; 5294 5295 u8 reserved_at_40[0xc0]; 5296 5297 struct mlx5_ifc_sqc_bits sq_context; 5298 }; 5299 5300 struct mlx5_ifc_query_sq_in_bits { 5301 u8 opcode[0x10]; 5302 u8 reserved_at_10[0x10]; 5303 5304 u8 reserved_at_20[0x10]; 5305 u8 op_mod[0x10]; 5306 5307 u8 reserved_at_40[0x8]; 5308 u8 sqn[0x18]; 5309 5310 u8 reserved_at_60[0x20]; 5311 }; 5312 5313 struct mlx5_ifc_query_special_contexts_out_bits { 5314 u8 status[0x8]; 5315 u8 reserved_at_8[0x18]; 5316 5317 u8 syndrome[0x20]; 5318 5319 u8 dump_fill_mkey[0x20]; 5320 5321 u8 resd_lkey[0x20]; 5322 5323 u8 null_mkey[0x20]; 5324 5325 u8 terminate_scatter_list_mkey[0x20]; 5326 5327 u8 repeated_mkey[0x20]; 5328 5329 u8 reserved_at_a0[0x20]; 5330 }; 5331 5332 struct mlx5_ifc_query_special_contexts_in_bits { 5333 u8 opcode[0x10]; 5334 u8 reserved_at_10[0x10]; 5335 5336 u8 reserved_at_20[0x10]; 5337 u8 op_mod[0x10]; 5338 5339 u8 reserved_at_40[0x40]; 5340 }; 5341 5342 struct mlx5_ifc_query_scheduling_element_out_bits { 5343 u8 opcode[0x10]; 5344 u8 reserved_at_10[0x10]; 5345 5346 u8 reserved_at_20[0x10]; 5347 u8 op_mod[0x10]; 5348 5349 u8 reserved_at_40[0xc0]; 5350 5351 struct mlx5_ifc_scheduling_context_bits scheduling_context; 5352 5353 u8 reserved_at_300[0x100]; 5354 }; 5355 5356 enum { 5357 SCHEDULING_HIERARCHY_E_SWITCH = 0x2, 5358 SCHEDULING_HIERARCHY_NIC = 0x3, 5359 }; 5360 5361 struct mlx5_ifc_query_scheduling_element_in_bits { 5362 u8 opcode[0x10]; 5363 u8 reserved_at_10[0x10]; 5364 5365 u8 reserved_at_20[0x10]; 5366 u8 op_mod[0x10]; 5367 5368 u8 scheduling_hierarchy[0x8]; 5369 u8 reserved_at_48[0x18]; 5370 5371 u8 scheduling_element_id[0x20]; 5372 5373 u8 reserved_at_80[0x180]; 5374 }; 5375 5376 struct mlx5_ifc_query_rqt_out_bits { 5377 u8 status[0x8]; 5378 u8 reserved_at_8[0x18]; 5379 5380 u8 syndrome[0x20]; 5381 5382 u8 reserved_at_40[0xc0]; 5383 5384 struct mlx5_ifc_rqtc_bits rqt_context; 5385 }; 5386 5387 struct mlx5_ifc_query_rqt_in_bits { 5388 u8 opcode[0x10]; 5389 u8 reserved_at_10[0x10]; 5390 5391 u8 reserved_at_20[0x10]; 5392 u8 op_mod[0x10]; 5393 5394 u8 reserved_at_40[0x8]; 5395 u8 rqtn[0x18]; 5396 5397 u8 reserved_at_60[0x20]; 5398 }; 5399 5400 struct mlx5_ifc_query_rq_out_bits { 5401 u8 status[0x8]; 5402 u8 reserved_at_8[0x18]; 5403 5404 u8 syndrome[0x20]; 5405 5406 u8 reserved_at_40[0xc0]; 5407 5408 struct mlx5_ifc_rqc_bits rq_context; 5409 }; 5410 5411 struct mlx5_ifc_query_rq_in_bits { 5412 u8 opcode[0x10]; 5413 u8 reserved_at_10[0x10]; 5414 5415 u8 reserved_at_20[0x10]; 5416 u8 op_mod[0x10]; 5417 5418 u8 reserved_at_40[0x8]; 5419 u8 rqn[0x18]; 5420 5421 u8 reserved_at_60[0x20]; 5422 }; 5423 5424 struct mlx5_ifc_query_roce_address_out_bits { 5425 u8 status[0x8]; 5426 u8 reserved_at_8[0x18]; 5427 5428 u8 syndrome[0x20]; 5429 5430 u8 reserved_at_40[0x40]; 5431 5432 struct mlx5_ifc_roce_addr_layout_bits roce_address; 5433 }; 5434 5435 struct mlx5_ifc_query_roce_address_in_bits { 5436 u8 opcode[0x10]; 5437 u8 reserved_at_10[0x10]; 5438 5439 u8 reserved_at_20[0x10]; 5440 u8 op_mod[0x10]; 5441 5442 u8 roce_address_index[0x10]; 5443 u8 reserved_at_50[0xc]; 5444 u8 vhca_port_num[0x4]; 5445 5446 u8 reserved_at_60[0x20]; 5447 }; 5448 5449 struct mlx5_ifc_query_rmp_out_bits { 5450 u8 status[0x8]; 5451 u8 reserved_at_8[0x18]; 5452 5453 u8 syndrome[0x20]; 5454 5455 u8 reserved_at_40[0xc0]; 5456 5457 struct mlx5_ifc_rmpc_bits rmp_context; 5458 }; 5459 5460 struct mlx5_ifc_query_rmp_in_bits { 5461 u8 opcode[0x10]; 5462 u8 reserved_at_10[0x10]; 5463 5464 u8 reserved_at_20[0x10]; 5465 u8 op_mod[0x10]; 5466 5467 u8 reserved_at_40[0x8]; 5468 u8 rmpn[0x18]; 5469 5470 u8 reserved_at_60[0x20]; 5471 }; 5472 5473 struct mlx5_ifc_cqe_error_syndrome_bits { 5474 u8 hw_error_syndrome[0x8]; 5475 u8 hw_syndrome_type[0x4]; 5476 u8 reserved_at_c[0x4]; 5477 u8 vendor_error_syndrome[0x8]; 5478 u8 syndrome[0x8]; 5479 }; 5480 5481 struct mlx5_ifc_qp_context_extension_bits { 5482 u8 reserved_at_0[0x60]; 5483 5484 struct mlx5_ifc_cqe_error_syndrome_bits error_syndrome; 5485 5486 u8 reserved_at_80[0x580]; 5487 }; 5488 5489 struct mlx5_ifc_qpc_extension_and_pas_list_in_bits { 5490 struct mlx5_ifc_qp_context_extension_bits qpc_data_extension; 5491 5492 u8 pas[0][0x40]; 5493 }; 5494 5495 struct mlx5_ifc_qp_pas_list_in_bits { 5496 struct mlx5_ifc_cmd_pas_bits pas[0]; 5497 }; 5498 5499 union mlx5_ifc_qp_pas_or_qpc_ext_and_pas_bits { 5500 struct mlx5_ifc_qp_pas_list_in_bits qp_pas_list; 5501 struct mlx5_ifc_qpc_extension_and_pas_list_in_bits qpc_ext_and_pas_list; 5502 }; 5503 5504 struct mlx5_ifc_query_qp_out_bits { 5505 u8 status[0x8]; 5506 u8 reserved_at_8[0x18]; 5507 5508 u8 syndrome[0x20]; 5509 5510 u8 reserved_at_40[0x40]; 5511 5512 u8 opt_param_mask[0x20]; 5513 5514 u8 ece[0x20]; 5515 5516 struct mlx5_ifc_qpc_bits qpc; 5517 5518 u8 reserved_at_800[0x80]; 5519 5520 union mlx5_ifc_qp_pas_or_qpc_ext_and_pas_bits qp_pas_or_qpc_ext_and_pas; 5521 }; 5522 5523 struct mlx5_ifc_query_qp_in_bits { 5524 u8 opcode[0x10]; 5525 u8 reserved_at_10[0x10]; 5526 5527 u8 reserved_at_20[0x10]; 5528 u8 op_mod[0x10]; 5529 5530 u8 qpc_ext[0x1]; 5531 u8 reserved_at_41[0x7]; 5532 u8 qpn[0x18]; 5533 5534 u8 reserved_at_60[0x20]; 5535 }; 5536 5537 struct mlx5_ifc_query_q_counter_out_bits { 5538 u8 status[0x8]; 5539 u8 reserved_at_8[0x18]; 5540 5541 u8 syndrome[0x20]; 5542 5543 u8 reserved_at_40[0x40]; 5544 5545 u8 rx_write_requests[0x20]; 5546 5547 u8 reserved_at_a0[0x20]; 5548 5549 u8 rx_read_requests[0x20]; 5550 5551 u8 reserved_at_e0[0x20]; 5552 5553 u8 rx_atomic_requests[0x20]; 5554 5555 u8 reserved_at_120[0x20]; 5556 5557 u8 rx_dct_connect[0x20]; 5558 5559 u8 reserved_at_160[0x20]; 5560 5561 u8 out_of_buffer[0x20]; 5562 5563 u8 reserved_at_1a0[0x20]; 5564 5565 u8 out_of_sequence[0x20]; 5566 5567 u8 reserved_at_1e0[0x20]; 5568 5569 u8 duplicate_request[0x20]; 5570 5571 u8 reserved_at_220[0x20]; 5572 5573 u8 rnr_nak_retry_err[0x20]; 5574 5575 u8 reserved_at_260[0x20]; 5576 5577 u8 packet_seq_err[0x20]; 5578 5579 u8 reserved_at_2a0[0x20]; 5580 5581 u8 implied_nak_seq_err[0x20]; 5582 5583 u8 reserved_at_2e0[0x20]; 5584 5585 u8 local_ack_timeout_err[0x20]; 5586 5587 u8 reserved_at_320[0xa0]; 5588 5589 u8 resp_local_length_error[0x20]; 5590 5591 u8 req_local_length_error[0x20]; 5592 5593 u8 resp_local_qp_error[0x20]; 5594 5595 u8 local_operation_error[0x20]; 5596 5597 u8 resp_local_protection[0x20]; 5598 5599 u8 req_local_protection[0x20]; 5600 5601 u8 resp_cqe_error[0x20]; 5602 5603 u8 req_cqe_error[0x20]; 5604 5605 u8 req_mw_binding[0x20]; 5606 5607 u8 req_bad_response[0x20]; 5608 5609 u8 req_remote_invalid_request[0x20]; 5610 5611 u8 resp_remote_invalid_request[0x20]; 5612 5613 u8 req_remote_access_errors[0x20]; 5614 5615 u8 resp_remote_access_errors[0x20]; 5616 5617 u8 req_remote_operation_errors[0x20]; 5618 5619 u8 req_transport_retries_exceeded[0x20]; 5620 5621 u8 cq_overflow[0x20]; 5622 5623 u8 resp_cqe_flush_error[0x20]; 5624 5625 u8 req_cqe_flush_error[0x20]; 5626 5627 u8 reserved_at_620[0x20]; 5628 5629 u8 roce_adp_retrans[0x20]; 5630 5631 u8 roce_adp_retrans_to[0x20]; 5632 5633 u8 roce_slow_restart[0x20]; 5634 5635 u8 roce_slow_restart_cnps[0x20]; 5636 5637 u8 roce_slow_restart_trans[0x20]; 5638 5639 u8 reserved_at_6e0[0x120]; 5640 }; 5641 5642 struct mlx5_ifc_query_q_counter_in_bits { 5643 u8 opcode[0x10]; 5644 u8 reserved_at_10[0x10]; 5645 5646 u8 reserved_at_20[0x10]; 5647 u8 op_mod[0x10]; 5648 5649 u8 other_vport[0x1]; 5650 u8 reserved_at_41[0xf]; 5651 u8 vport_number[0x10]; 5652 5653 u8 reserved_at_60[0x60]; 5654 5655 u8 clear[0x1]; 5656 u8 aggregate[0x1]; 5657 u8 reserved_at_c2[0x1e]; 5658 5659 u8 reserved_at_e0[0x18]; 5660 u8 counter_set_id[0x8]; 5661 }; 5662 5663 struct mlx5_ifc_query_pages_out_bits { 5664 u8 status[0x8]; 5665 u8 reserved_at_8[0x18]; 5666 5667 u8 syndrome[0x20]; 5668 5669 u8 embedded_cpu_function[0x1]; 5670 u8 reserved_at_41[0xf]; 5671 u8 function_id[0x10]; 5672 5673 u8 num_pages[0x20]; 5674 }; 5675 5676 enum { 5677 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1, 5678 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2, 5679 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3, 5680 }; 5681 5682 struct mlx5_ifc_query_pages_in_bits { 5683 u8 opcode[0x10]; 5684 u8 reserved_at_10[0x10]; 5685 5686 u8 reserved_at_20[0x10]; 5687 u8 op_mod[0x10]; 5688 5689 u8 embedded_cpu_function[0x1]; 5690 u8 reserved_at_41[0xf]; 5691 u8 function_id[0x10]; 5692 5693 u8 reserved_at_60[0x20]; 5694 }; 5695 5696 struct mlx5_ifc_query_nic_vport_context_out_bits { 5697 u8 status[0x8]; 5698 u8 reserved_at_8[0x18]; 5699 5700 u8 syndrome[0x20]; 5701 5702 u8 reserved_at_40[0x40]; 5703 5704 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 5705 }; 5706 5707 struct mlx5_ifc_query_nic_vport_context_in_bits { 5708 u8 opcode[0x10]; 5709 u8 reserved_at_10[0x10]; 5710 5711 u8 reserved_at_20[0x10]; 5712 u8 op_mod[0x10]; 5713 5714 u8 other_vport[0x1]; 5715 u8 reserved_at_41[0xf]; 5716 u8 vport_number[0x10]; 5717 5718 u8 reserved_at_60[0x5]; 5719 u8 allowed_list_type[0x3]; 5720 u8 reserved_at_68[0x18]; 5721 }; 5722 5723 struct mlx5_ifc_query_mkey_out_bits { 5724 u8 status[0x8]; 5725 u8 reserved_at_8[0x18]; 5726 5727 u8 syndrome[0x20]; 5728 5729 u8 reserved_at_40[0x40]; 5730 5731 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 5732 5733 u8 reserved_at_280[0x600]; 5734 5735 u8 bsf0_klm0_pas_mtt0_1[16][0x8]; 5736 5737 u8 bsf1_klm1_pas_mtt2_3[16][0x8]; 5738 }; 5739 5740 struct mlx5_ifc_query_mkey_in_bits { 5741 u8 opcode[0x10]; 5742 u8 reserved_at_10[0x10]; 5743 5744 u8 reserved_at_20[0x10]; 5745 u8 op_mod[0x10]; 5746 5747 u8 reserved_at_40[0x8]; 5748 u8 mkey_index[0x18]; 5749 5750 u8 pg_access[0x1]; 5751 u8 reserved_at_61[0x1f]; 5752 }; 5753 5754 struct mlx5_ifc_query_mad_demux_out_bits { 5755 u8 status[0x8]; 5756 u8 reserved_at_8[0x18]; 5757 5758 u8 syndrome[0x20]; 5759 5760 u8 reserved_at_40[0x40]; 5761 5762 u8 mad_dumux_parameters_block[0x20]; 5763 }; 5764 5765 struct mlx5_ifc_query_mad_demux_in_bits { 5766 u8 opcode[0x10]; 5767 u8 reserved_at_10[0x10]; 5768 5769 u8 reserved_at_20[0x10]; 5770 u8 op_mod[0x10]; 5771 5772 u8 reserved_at_40[0x40]; 5773 }; 5774 5775 struct mlx5_ifc_query_l2_table_entry_out_bits { 5776 u8 status[0x8]; 5777 u8 reserved_at_8[0x18]; 5778 5779 u8 syndrome[0x20]; 5780 5781 u8 reserved_at_40[0xa0]; 5782 5783 u8 reserved_at_e0[0x13]; 5784 u8 vlan_valid[0x1]; 5785 u8 vlan[0xc]; 5786 5787 struct mlx5_ifc_mac_address_layout_bits mac_address; 5788 5789 u8 reserved_at_140[0xc0]; 5790 }; 5791 5792 struct mlx5_ifc_query_l2_table_entry_in_bits { 5793 u8 opcode[0x10]; 5794 u8 reserved_at_10[0x10]; 5795 5796 u8 reserved_at_20[0x10]; 5797 u8 op_mod[0x10]; 5798 5799 u8 reserved_at_40[0x60]; 5800 5801 u8 reserved_at_a0[0x8]; 5802 u8 table_index[0x18]; 5803 5804 u8 reserved_at_c0[0x140]; 5805 }; 5806 5807 struct mlx5_ifc_query_issi_out_bits { 5808 u8 status[0x8]; 5809 u8 reserved_at_8[0x18]; 5810 5811 u8 syndrome[0x20]; 5812 5813 u8 reserved_at_40[0x10]; 5814 u8 current_issi[0x10]; 5815 5816 u8 reserved_at_60[0xa0]; 5817 5818 u8 reserved_at_100[76][0x8]; 5819 u8 supported_issi_dw0[0x20]; 5820 }; 5821 5822 struct mlx5_ifc_query_issi_in_bits { 5823 u8 opcode[0x10]; 5824 u8 reserved_at_10[0x10]; 5825 5826 u8 reserved_at_20[0x10]; 5827 u8 op_mod[0x10]; 5828 5829 u8 reserved_at_40[0x40]; 5830 }; 5831 5832 struct mlx5_ifc_set_driver_version_out_bits { 5833 u8 status[0x8]; 5834 u8 reserved_0[0x18]; 5835 5836 u8 syndrome[0x20]; 5837 u8 reserved_1[0x40]; 5838 }; 5839 5840 struct mlx5_ifc_set_driver_version_in_bits { 5841 u8 opcode[0x10]; 5842 u8 reserved_0[0x10]; 5843 5844 u8 reserved_1[0x10]; 5845 u8 op_mod[0x10]; 5846 5847 u8 reserved_2[0x40]; 5848 u8 driver_version[64][0x8]; 5849 }; 5850 5851 struct mlx5_ifc_query_hca_vport_pkey_out_bits { 5852 u8 status[0x8]; 5853 u8 reserved_at_8[0x18]; 5854 5855 u8 syndrome[0x20]; 5856 5857 u8 reserved_at_40[0x40]; 5858 5859 struct mlx5_ifc_pkey_bits pkey[]; 5860 }; 5861 5862 struct mlx5_ifc_query_hca_vport_pkey_in_bits { 5863 u8 opcode[0x10]; 5864 u8 reserved_at_10[0x10]; 5865 5866 u8 reserved_at_20[0x10]; 5867 u8 op_mod[0x10]; 5868 5869 u8 other_vport[0x1]; 5870 u8 reserved_at_41[0xb]; 5871 u8 port_num[0x4]; 5872 u8 vport_number[0x10]; 5873 5874 u8 reserved_at_60[0x10]; 5875 u8 pkey_index[0x10]; 5876 }; 5877 5878 enum { 5879 MLX5_HCA_VPORT_SEL_PORT_GUID = 1 << 0, 5880 MLX5_HCA_VPORT_SEL_NODE_GUID = 1 << 1, 5881 MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2, 5882 }; 5883 5884 struct mlx5_ifc_query_hca_vport_gid_out_bits { 5885 u8 status[0x8]; 5886 u8 reserved_at_8[0x18]; 5887 5888 u8 syndrome[0x20]; 5889 5890 u8 reserved_at_40[0x20]; 5891 5892 u8 gids_num[0x10]; 5893 u8 reserved_at_70[0x10]; 5894 5895 struct mlx5_ifc_array128_auto_bits gid[]; 5896 }; 5897 5898 struct mlx5_ifc_query_hca_vport_gid_in_bits { 5899 u8 opcode[0x10]; 5900 u8 reserved_at_10[0x10]; 5901 5902 u8 reserved_at_20[0x10]; 5903 u8 op_mod[0x10]; 5904 5905 u8 other_vport[0x1]; 5906 u8 reserved_at_41[0xb]; 5907 u8 port_num[0x4]; 5908 u8 vport_number[0x10]; 5909 5910 u8 reserved_at_60[0x10]; 5911 u8 gid_index[0x10]; 5912 }; 5913 5914 struct mlx5_ifc_query_hca_vport_context_out_bits { 5915 u8 status[0x8]; 5916 u8 reserved_at_8[0x18]; 5917 5918 u8 syndrome[0x20]; 5919 5920 u8 reserved_at_40[0x40]; 5921 5922 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 5923 }; 5924 5925 struct mlx5_ifc_query_hca_vport_context_in_bits { 5926 u8 opcode[0x10]; 5927 u8 reserved_at_10[0x10]; 5928 5929 u8 reserved_at_20[0x10]; 5930 u8 op_mod[0x10]; 5931 5932 u8 other_vport[0x1]; 5933 u8 reserved_at_41[0xb]; 5934 u8 port_num[0x4]; 5935 u8 vport_number[0x10]; 5936 5937 u8 reserved_at_60[0x20]; 5938 }; 5939 5940 struct mlx5_ifc_query_hca_cap_out_bits { 5941 u8 status[0x8]; 5942 u8 reserved_at_8[0x18]; 5943 5944 u8 syndrome[0x20]; 5945 5946 u8 reserved_at_40[0x40]; 5947 5948 union mlx5_ifc_hca_cap_union_bits capability; 5949 }; 5950 5951 struct mlx5_ifc_query_hca_cap_in_bits { 5952 u8 opcode[0x10]; 5953 u8 reserved_at_10[0x10]; 5954 5955 u8 reserved_at_20[0x10]; 5956 u8 op_mod[0x10]; 5957 5958 u8 other_function[0x1]; 5959 u8 reserved_at_41[0xf]; 5960 u8 function_id[0x10]; 5961 5962 u8 reserved_at_60[0x20]; 5963 }; 5964 5965 struct mlx5_ifc_other_hca_cap_bits { 5966 u8 roce[0x1]; 5967 u8 reserved_at_1[0x27f]; 5968 }; 5969 5970 struct mlx5_ifc_query_other_hca_cap_out_bits { 5971 u8 status[0x8]; 5972 u8 reserved_at_8[0x18]; 5973 5974 u8 syndrome[0x20]; 5975 5976 u8 reserved_at_40[0x40]; 5977 5978 struct mlx5_ifc_other_hca_cap_bits other_capability; 5979 }; 5980 5981 struct mlx5_ifc_query_other_hca_cap_in_bits { 5982 u8 opcode[0x10]; 5983 u8 reserved_at_10[0x10]; 5984 5985 u8 reserved_at_20[0x10]; 5986 u8 op_mod[0x10]; 5987 5988 u8 reserved_at_40[0x10]; 5989 u8 function_id[0x10]; 5990 5991 u8 reserved_at_60[0x20]; 5992 }; 5993 5994 struct mlx5_ifc_modify_other_hca_cap_out_bits { 5995 u8 status[0x8]; 5996 u8 reserved_at_8[0x18]; 5997 5998 u8 syndrome[0x20]; 5999 6000 u8 reserved_at_40[0x40]; 6001 }; 6002 6003 struct mlx5_ifc_modify_other_hca_cap_in_bits { 6004 u8 opcode[0x10]; 6005 u8 reserved_at_10[0x10]; 6006 6007 u8 reserved_at_20[0x10]; 6008 u8 op_mod[0x10]; 6009 6010 u8 reserved_at_40[0x10]; 6011 u8 function_id[0x10]; 6012 u8 field_select[0x20]; 6013 6014 struct mlx5_ifc_other_hca_cap_bits other_capability; 6015 }; 6016 6017 struct mlx5_ifc_flow_table_context_bits { 6018 u8 reformat_en[0x1]; 6019 u8 decap_en[0x1]; 6020 u8 sw_owner[0x1]; 6021 u8 termination_table[0x1]; 6022 u8 table_miss_action[0x4]; 6023 u8 level[0x8]; 6024 u8 reserved_at_10[0x8]; 6025 u8 log_size[0x8]; 6026 6027 u8 reserved_at_20[0x8]; 6028 u8 table_miss_id[0x18]; 6029 6030 u8 reserved_at_40[0x8]; 6031 u8 lag_master_next_table_id[0x18]; 6032 6033 u8 reserved_at_60[0x60]; 6034 6035 u8 sw_owner_icm_root_1[0x40]; 6036 6037 u8 sw_owner_icm_root_0[0x40]; 6038 6039 }; 6040 6041 struct mlx5_ifc_query_flow_table_out_bits { 6042 u8 status[0x8]; 6043 u8 reserved_at_8[0x18]; 6044 6045 u8 syndrome[0x20]; 6046 6047 u8 reserved_at_40[0x80]; 6048 6049 struct mlx5_ifc_flow_table_context_bits flow_table_context; 6050 }; 6051 6052 struct mlx5_ifc_query_flow_table_in_bits { 6053 u8 opcode[0x10]; 6054 u8 reserved_at_10[0x10]; 6055 6056 u8 reserved_at_20[0x10]; 6057 u8 op_mod[0x10]; 6058 6059 u8 reserved_at_40[0x40]; 6060 6061 u8 table_type[0x8]; 6062 u8 reserved_at_88[0x18]; 6063 6064 u8 reserved_at_a0[0x8]; 6065 u8 table_id[0x18]; 6066 6067 u8 reserved_at_c0[0x140]; 6068 }; 6069 6070 struct mlx5_ifc_query_fte_out_bits { 6071 u8 status[0x8]; 6072 u8 reserved_at_8[0x18]; 6073 6074 u8 syndrome[0x20]; 6075 6076 u8 reserved_at_40[0x1c0]; 6077 6078 struct mlx5_ifc_flow_context_bits flow_context; 6079 }; 6080 6081 struct mlx5_ifc_query_fte_in_bits { 6082 u8 opcode[0x10]; 6083 u8 reserved_at_10[0x10]; 6084 6085 u8 reserved_at_20[0x10]; 6086 u8 op_mod[0x10]; 6087 6088 u8 reserved_at_40[0x40]; 6089 6090 u8 table_type[0x8]; 6091 u8 reserved_at_88[0x18]; 6092 6093 u8 reserved_at_a0[0x8]; 6094 u8 table_id[0x18]; 6095 6096 u8 reserved_at_c0[0x40]; 6097 6098 u8 flow_index[0x20]; 6099 6100 u8 reserved_at_120[0xe0]; 6101 }; 6102 6103 struct mlx5_ifc_match_definer_format_0_bits { 6104 u8 reserved_at_0[0x100]; 6105 6106 u8 metadata_reg_c_0[0x20]; 6107 6108 u8 metadata_reg_c_1[0x20]; 6109 6110 u8 outer_dmac_47_16[0x20]; 6111 6112 u8 outer_dmac_15_0[0x10]; 6113 u8 outer_ethertype[0x10]; 6114 6115 u8 reserved_at_180[0x1]; 6116 u8 sx_sniffer[0x1]; 6117 u8 functional_lb[0x1]; 6118 u8 outer_ip_frag[0x1]; 6119 u8 outer_qp_type[0x2]; 6120 u8 outer_encap_type[0x2]; 6121 u8 port_number[0x2]; 6122 u8 outer_l3_type[0x2]; 6123 u8 outer_l4_type[0x2]; 6124 u8 outer_first_vlan_type[0x2]; 6125 u8 outer_first_vlan_prio[0x3]; 6126 u8 outer_first_vlan_cfi[0x1]; 6127 u8 outer_first_vlan_vid[0xc]; 6128 6129 u8 outer_l4_type_ext[0x4]; 6130 u8 reserved_at_1a4[0x2]; 6131 u8 outer_ipsec_layer[0x2]; 6132 u8 outer_l2_type[0x2]; 6133 u8 force_lb[0x1]; 6134 u8 outer_l2_ok[0x1]; 6135 u8 outer_l3_ok[0x1]; 6136 u8 outer_l4_ok[0x1]; 6137 u8 outer_second_vlan_type[0x2]; 6138 u8 outer_second_vlan_prio[0x3]; 6139 u8 outer_second_vlan_cfi[0x1]; 6140 u8 outer_second_vlan_vid[0xc]; 6141 6142 u8 outer_smac_47_16[0x20]; 6143 6144 u8 outer_smac_15_0[0x10]; 6145 u8 inner_ipv4_checksum_ok[0x1]; 6146 u8 inner_l4_checksum_ok[0x1]; 6147 u8 outer_ipv4_checksum_ok[0x1]; 6148 u8 outer_l4_checksum_ok[0x1]; 6149 u8 inner_l3_ok[0x1]; 6150 u8 inner_l4_ok[0x1]; 6151 u8 outer_l3_ok_duplicate[0x1]; 6152 u8 outer_l4_ok_duplicate[0x1]; 6153 u8 outer_tcp_cwr[0x1]; 6154 u8 outer_tcp_ece[0x1]; 6155 u8 outer_tcp_urg[0x1]; 6156 u8 outer_tcp_ack[0x1]; 6157 u8 outer_tcp_psh[0x1]; 6158 u8 outer_tcp_rst[0x1]; 6159 u8 outer_tcp_syn[0x1]; 6160 u8 outer_tcp_fin[0x1]; 6161 }; 6162 6163 struct mlx5_ifc_match_definer_format_22_bits { 6164 u8 reserved_at_0[0x100]; 6165 6166 u8 outer_ip_src_addr[0x20]; 6167 6168 u8 outer_ip_dest_addr[0x20]; 6169 6170 u8 outer_l4_sport[0x10]; 6171 u8 outer_l4_dport[0x10]; 6172 6173 u8 reserved_at_160[0x1]; 6174 u8 sx_sniffer[0x1]; 6175 u8 functional_lb[0x1]; 6176 u8 outer_ip_frag[0x1]; 6177 u8 outer_qp_type[0x2]; 6178 u8 outer_encap_type[0x2]; 6179 u8 port_number[0x2]; 6180 u8 outer_l3_type[0x2]; 6181 u8 outer_l4_type[0x2]; 6182 u8 outer_first_vlan_type[0x2]; 6183 u8 outer_first_vlan_prio[0x3]; 6184 u8 outer_first_vlan_cfi[0x1]; 6185 u8 outer_first_vlan_vid[0xc]; 6186 6187 u8 metadata_reg_c_0[0x20]; 6188 6189 u8 outer_dmac_47_16[0x20]; 6190 6191 u8 outer_smac_47_16[0x20]; 6192 6193 u8 outer_smac_15_0[0x10]; 6194 u8 outer_dmac_15_0[0x10]; 6195 }; 6196 6197 struct mlx5_ifc_match_definer_format_23_bits { 6198 u8 reserved_at_0[0x100]; 6199 6200 u8 inner_ip_src_addr[0x20]; 6201 6202 u8 inner_ip_dest_addr[0x20]; 6203 6204 u8 inner_l4_sport[0x10]; 6205 u8 inner_l4_dport[0x10]; 6206 6207 u8 reserved_at_160[0x1]; 6208 u8 sx_sniffer[0x1]; 6209 u8 functional_lb[0x1]; 6210 u8 inner_ip_frag[0x1]; 6211 u8 inner_qp_type[0x2]; 6212 u8 inner_encap_type[0x2]; 6213 u8 port_number[0x2]; 6214 u8 inner_l3_type[0x2]; 6215 u8 inner_l4_type[0x2]; 6216 u8 inner_first_vlan_type[0x2]; 6217 u8 inner_first_vlan_prio[0x3]; 6218 u8 inner_first_vlan_cfi[0x1]; 6219 u8 inner_first_vlan_vid[0xc]; 6220 6221 u8 tunnel_header_0[0x20]; 6222 6223 u8 inner_dmac_47_16[0x20]; 6224 6225 u8 inner_smac_47_16[0x20]; 6226 6227 u8 inner_smac_15_0[0x10]; 6228 u8 inner_dmac_15_0[0x10]; 6229 }; 6230 6231 struct mlx5_ifc_match_definer_format_29_bits { 6232 u8 reserved_at_0[0xc0]; 6233 6234 u8 outer_ip_dest_addr[0x80]; 6235 6236 u8 outer_ip_src_addr[0x80]; 6237 6238 u8 outer_l4_sport[0x10]; 6239 u8 outer_l4_dport[0x10]; 6240 6241 u8 reserved_at_1e0[0x20]; 6242 }; 6243 6244 struct mlx5_ifc_match_definer_format_30_bits { 6245 u8 reserved_at_0[0xa0]; 6246 6247 u8 outer_ip_dest_addr[0x80]; 6248 6249 u8 outer_ip_src_addr[0x80]; 6250 6251 u8 outer_dmac_47_16[0x20]; 6252 6253 u8 outer_smac_47_16[0x20]; 6254 6255 u8 outer_smac_15_0[0x10]; 6256 u8 outer_dmac_15_0[0x10]; 6257 }; 6258 6259 struct mlx5_ifc_match_definer_format_31_bits { 6260 u8 reserved_at_0[0xc0]; 6261 6262 u8 inner_ip_dest_addr[0x80]; 6263 6264 u8 inner_ip_src_addr[0x80]; 6265 6266 u8 inner_l4_sport[0x10]; 6267 u8 inner_l4_dport[0x10]; 6268 6269 u8 reserved_at_1e0[0x20]; 6270 }; 6271 6272 struct mlx5_ifc_match_definer_format_32_bits { 6273 u8 reserved_at_0[0xa0]; 6274 6275 u8 inner_ip_dest_addr[0x80]; 6276 6277 u8 inner_ip_src_addr[0x80]; 6278 6279 u8 inner_dmac_47_16[0x20]; 6280 6281 u8 inner_smac_47_16[0x20]; 6282 6283 u8 inner_smac_15_0[0x10]; 6284 u8 inner_dmac_15_0[0x10]; 6285 }; 6286 6287 enum { 6288 MLX5_IFC_DEFINER_FORMAT_ID_SELECT = 61, 6289 }; 6290 6291 #define MLX5_IFC_DEFINER_FORMAT_OFFSET_UNUSED 0x0 6292 #define MLX5_IFC_DEFINER_FORMAT_OFFSET_OUTER_ETH_PKT_LEN 0x48 6293 #define MLX5_IFC_DEFINER_DW_SELECTORS_NUM 9 6294 #define MLX5_IFC_DEFINER_BYTE_SELECTORS_NUM 8 6295 6296 struct mlx5_ifc_match_definer_match_mask_bits { 6297 u8 reserved_at_1c0[5][0x20]; 6298 u8 match_dw_8[0x20]; 6299 u8 match_dw_7[0x20]; 6300 u8 match_dw_6[0x20]; 6301 u8 match_dw_5[0x20]; 6302 u8 match_dw_4[0x20]; 6303 u8 match_dw_3[0x20]; 6304 u8 match_dw_2[0x20]; 6305 u8 match_dw_1[0x20]; 6306 u8 match_dw_0[0x20]; 6307 6308 u8 match_byte_7[0x8]; 6309 u8 match_byte_6[0x8]; 6310 u8 match_byte_5[0x8]; 6311 u8 match_byte_4[0x8]; 6312 6313 u8 match_byte_3[0x8]; 6314 u8 match_byte_2[0x8]; 6315 u8 match_byte_1[0x8]; 6316 u8 match_byte_0[0x8]; 6317 }; 6318 6319 struct mlx5_ifc_match_definer_bits { 6320 u8 modify_field_select[0x40]; 6321 6322 u8 reserved_at_40[0x40]; 6323 6324 u8 reserved_at_80[0x10]; 6325 u8 format_id[0x10]; 6326 6327 u8 reserved_at_a0[0x60]; 6328 6329 u8 format_select_dw3[0x8]; 6330 u8 format_select_dw2[0x8]; 6331 u8 format_select_dw1[0x8]; 6332 u8 format_select_dw0[0x8]; 6333 6334 u8 format_select_dw7[0x8]; 6335 u8 format_select_dw6[0x8]; 6336 u8 format_select_dw5[0x8]; 6337 u8 format_select_dw4[0x8]; 6338 6339 u8 reserved_at_100[0x18]; 6340 u8 format_select_dw8[0x8]; 6341 6342 u8 reserved_at_120[0x20]; 6343 6344 u8 format_select_byte3[0x8]; 6345 u8 format_select_byte2[0x8]; 6346 u8 format_select_byte1[0x8]; 6347 u8 format_select_byte0[0x8]; 6348 6349 u8 format_select_byte7[0x8]; 6350 u8 format_select_byte6[0x8]; 6351 u8 format_select_byte5[0x8]; 6352 u8 format_select_byte4[0x8]; 6353 6354 u8 reserved_at_180[0x40]; 6355 6356 union { 6357 struct { 6358 u8 match_mask[16][0x20]; 6359 }; 6360 struct mlx5_ifc_match_definer_match_mask_bits match_mask_format; 6361 }; 6362 }; 6363 6364 struct mlx5_ifc_general_obj_create_param_bits { 6365 u8 alias_object[0x1]; 6366 u8 reserved_at_1[0x2]; 6367 u8 log_obj_range[0x5]; 6368 u8 reserved_at_8[0x18]; 6369 }; 6370 6371 struct mlx5_ifc_general_obj_query_param_bits { 6372 u8 alias_object[0x1]; 6373 u8 obj_offset[0x1f]; 6374 }; 6375 6376 struct mlx5_ifc_general_obj_in_cmd_hdr_bits { 6377 u8 opcode[0x10]; 6378 u8 uid[0x10]; 6379 6380 u8 vhca_tunnel_id[0x10]; 6381 u8 obj_type[0x10]; 6382 6383 u8 obj_id[0x20]; 6384 6385 union { 6386 struct mlx5_ifc_general_obj_create_param_bits create; 6387 struct mlx5_ifc_general_obj_query_param_bits query; 6388 } op_param; 6389 }; 6390 6391 struct mlx5_ifc_general_obj_out_cmd_hdr_bits { 6392 u8 status[0x8]; 6393 u8 reserved_at_8[0x18]; 6394 6395 u8 syndrome[0x20]; 6396 6397 u8 obj_id[0x20]; 6398 6399 u8 reserved_at_60[0x20]; 6400 }; 6401 6402 struct mlx5_ifc_modify_header_arg_bits { 6403 u8 reserved_at_0[0x80]; 6404 6405 u8 reserved_at_80[0x8]; 6406 u8 access_pd[0x18]; 6407 }; 6408 6409 struct mlx5_ifc_create_modify_header_arg_in_bits { 6410 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 6411 struct mlx5_ifc_modify_header_arg_bits arg; 6412 }; 6413 6414 struct mlx5_ifc_create_match_definer_in_bits { 6415 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 6416 6417 struct mlx5_ifc_match_definer_bits obj_context; 6418 }; 6419 6420 struct mlx5_ifc_create_match_definer_out_bits { 6421 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 6422 }; 6423 6424 enum { 6425 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 6426 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 6427 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 6428 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3, 6429 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_3 = 0x4, 6430 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_4 = 0x5, 6431 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_5 = 0x6, 6432 }; 6433 6434 struct mlx5_ifc_query_flow_group_out_bits { 6435 u8 status[0x8]; 6436 u8 reserved_at_8[0x18]; 6437 6438 u8 syndrome[0x20]; 6439 6440 u8 reserved_at_40[0xa0]; 6441 6442 u8 start_flow_index[0x20]; 6443 6444 u8 reserved_at_100[0x20]; 6445 6446 u8 end_flow_index[0x20]; 6447 6448 u8 reserved_at_140[0xa0]; 6449 6450 u8 reserved_at_1e0[0x18]; 6451 u8 match_criteria_enable[0x8]; 6452 6453 struct mlx5_ifc_fte_match_param_bits match_criteria; 6454 6455 u8 reserved_at_1200[0xe00]; 6456 }; 6457 6458 struct mlx5_ifc_query_flow_group_in_bits { 6459 u8 opcode[0x10]; 6460 u8 reserved_at_10[0x10]; 6461 6462 u8 reserved_at_20[0x10]; 6463 u8 op_mod[0x10]; 6464 6465 u8 reserved_at_40[0x40]; 6466 6467 u8 table_type[0x8]; 6468 u8 reserved_at_88[0x18]; 6469 6470 u8 reserved_at_a0[0x8]; 6471 u8 table_id[0x18]; 6472 6473 u8 group_id[0x20]; 6474 6475 u8 reserved_at_e0[0x120]; 6476 }; 6477 6478 struct mlx5_ifc_query_flow_counter_out_bits { 6479 u8 status[0x8]; 6480 u8 reserved_at_8[0x18]; 6481 6482 u8 syndrome[0x20]; 6483 6484 u8 reserved_at_40[0x40]; 6485 6486 struct mlx5_ifc_traffic_counter_bits flow_statistics[]; 6487 }; 6488 6489 struct mlx5_ifc_query_flow_counter_in_bits { 6490 u8 opcode[0x10]; 6491 u8 reserved_at_10[0x10]; 6492 6493 u8 reserved_at_20[0x10]; 6494 u8 op_mod[0x10]; 6495 6496 u8 reserved_at_40[0x80]; 6497 6498 u8 clear[0x1]; 6499 u8 reserved_at_c1[0xf]; 6500 u8 num_of_counters[0x10]; 6501 6502 u8 flow_counter_id[0x20]; 6503 }; 6504 6505 struct mlx5_ifc_query_esw_vport_context_out_bits { 6506 u8 status[0x8]; 6507 u8 reserved_at_8[0x18]; 6508 6509 u8 syndrome[0x20]; 6510 6511 u8 reserved_at_40[0x40]; 6512 6513 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 6514 }; 6515 6516 struct mlx5_ifc_query_esw_vport_context_in_bits { 6517 u8 opcode[0x10]; 6518 u8 reserved_at_10[0x10]; 6519 6520 u8 reserved_at_20[0x10]; 6521 u8 op_mod[0x10]; 6522 6523 u8 other_vport[0x1]; 6524 u8 reserved_at_41[0xf]; 6525 u8 vport_number[0x10]; 6526 6527 u8 reserved_at_60[0x20]; 6528 }; 6529 6530 struct mlx5_ifc_modify_esw_vport_context_out_bits { 6531 u8 status[0x8]; 6532 u8 reserved_at_8[0x18]; 6533 6534 u8 syndrome[0x20]; 6535 6536 u8 reserved_at_40[0x40]; 6537 }; 6538 6539 struct mlx5_ifc_esw_vport_context_fields_select_bits { 6540 u8 reserved_at_0[0x1b]; 6541 u8 fdb_to_vport_reg_c_id[0x1]; 6542 u8 vport_cvlan_insert[0x1]; 6543 u8 vport_svlan_insert[0x1]; 6544 u8 vport_cvlan_strip[0x1]; 6545 u8 vport_svlan_strip[0x1]; 6546 }; 6547 6548 struct mlx5_ifc_modify_esw_vport_context_in_bits { 6549 u8 opcode[0x10]; 6550 u8 reserved_at_10[0x10]; 6551 6552 u8 reserved_at_20[0x10]; 6553 u8 op_mod[0x10]; 6554 6555 u8 other_vport[0x1]; 6556 u8 reserved_at_41[0xf]; 6557 u8 vport_number[0x10]; 6558 6559 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select; 6560 6561 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 6562 }; 6563 6564 struct mlx5_ifc_query_eq_out_bits { 6565 u8 status[0x8]; 6566 u8 reserved_at_8[0x18]; 6567 6568 u8 syndrome[0x20]; 6569 6570 u8 reserved_at_40[0x40]; 6571 6572 struct mlx5_ifc_eqc_bits eq_context_entry; 6573 6574 u8 reserved_at_280[0x40]; 6575 6576 u8 event_bitmask[0x40]; 6577 6578 u8 reserved_at_300[0x580]; 6579 6580 u8 pas[][0x40]; 6581 }; 6582 6583 struct mlx5_ifc_query_eq_in_bits { 6584 u8 opcode[0x10]; 6585 u8 reserved_at_10[0x10]; 6586 6587 u8 reserved_at_20[0x10]; 6588 u8 op_mod[0x10]; 6589 6590 u8 reserved_at_40[0x18]; 6591 u8 eq_number[0x8]; 6592 6593 u8 reserved_at_60[0x20]; 6594 }; 6595 6596 struct mlx5_ifc_packet_reformat_context_in_bits { 6597 u8 reformat_type[0x8]; 6598 u8 reserved_at_8[0x4]; 6599 u8 reformat_param_0[0x4]; 6600 u8 reserved_at_10[0x6]; 6601 u8 reformat_data_size[0xa]; 6602 6603 u8 reformat_param_1[0x8]; 6604 u8 reserved_at_28[0x8]; 6605 u8 reformat_data[2][0x8]; 6606 6607 u8 more_reformat_data[][0x8]; 6608 }; 6609 6610 struct mlx5_ifc_query_packet_reformat_context_out_bits { 6611 u8 status[0x8]; 6612 u8 reserved_at_8[0x18]; 6613 6614 u8 syndrome[0x20]; 6615 6616 u8 reserved_at_40[0xa0]; 6617 6618 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context[]; 6619 }; 6620 6621 struct mlx5_ifc_query_packet_reformat_context_in_bits { 6622 u8 opcode[0x10]; 6623 u8 reserved_at_10[0x10]; 6624 6625 u8 reserved_at_20[0x10]; 6626 u8 op_mod[0x10]; 6627 6628 u8 packet_reformat_id[0x20]; 6629 6630 u8 reserved_at_60[0xa0]; 6631 }; 6632 6633 struct mlx5_ifc_alloc_packet_reformat_context_out_bits { 6634 u8 status[0x8]; 6635 u8 reserved_at_8[0x18]; 6636 6637 u8 syndrome[0x20]; 6638 6639 u8 packet_reformat_id[0x20]; 6640 6641 u8 reserved_at_60[0x20]; 6642 }; 6643 6644 enum { 6645 MLX5_REFORMAT_CONTEXT_ANCHOR_MAC_START = 0x1, 6646 MLX5_REFORMAT_CONTEXT_ANCHOR_IP_START = 0x7, 6647 MLX5_REFORMAT_CONTEXT_ANCHOR_TCP_UDP_START = 0x9, 6648 }; 6649 6650 enum mlx5_reformat_ctx_type { 6651 MLX5_REFORMAT_TYPE_L2_TO_VXLAN = 0x0, 6652 MLX5_REFORMAT_TYPE_L2_TO_NVGRE = 0x1, 6653 MLX5_REFORMAT_TYPE_L2_TO_L2_TUNNEL = 0x2, 6654 MLX5_REFORMAT_TYPE_L3_TUNNEL_TO_L2 = 0x3, 6655 MLX5_REFORMAT_TYPE_L2_TO_L3_TUNNEL = 0x4, 6656 MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_IPV4 = 0x5, 6657 MLX5_REFORMAT_TYPE_L2_TO_L3_ESP_TUNNEL = 0x6, 6658 MLX5_REFORMAT_TYPE_DEL_ESP_TRANSPORT = 0x8, 6659 MLX5_REFORMAT_TYPE_L3_ESP_TUNNEL_TO_L2 = 0x9, 6660 MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_IPV6 = 0xb, 6661 MLX5_REFORMAT_TYPE_INSERT_HDR = 0xf, 6662 MLX5_REFORMAT_TYPE_REMOVE_HDR = 0x10, 6663 MLX5_REFORMAT_TYPE_ADD_MACSEC = 0x11, 6664 MLX5_REFORMAT_TYPE_DEL_MACSEC = 0x12, 6665 }; 6666 6667 struct mlx5_ifc_alloc_packet_reformat_context_in_bits { 6668 u8 opcode[0x10]; 6669 u8 reserved_at_10[0x10]; 6670 6671 u8 reserved_at_20[0x10]; 6672 u8 op_mod[0x10]; 6673 6674 u8 reserved_at_40[0xa0]; 6675 6676 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context; 6677 }; 6678 6679 struct mlx5_ifc_dealloc_packet_reformat_context_out_bits { 6680 u8 status[0x8]; 6681 u8 reserved_at_8[0x18]; 6682 6683 u8 syndrome[0x20]; 6684 6685 u8 reserved_at_40[0x40]; 6686 }; 6687 6688 struct mlx5_ifc_dealloc_packet_reformat_context_in_bits { 6689 u8 opcode[0x10]; 6690 u8 reserved_at_10[0x10]; 6691 6692 u8 reserved_20[0x10]; 6693 u8 op_mod[0x10]; 6694 6695 u8 packet_reformat_id[0x20]; 6696 6697 u8 reserved_60[0x20]; 6698 }; 6699 6700 struct mlx5_ifc_set_action_in_bits { 6701 u8 action_type[0x4]; 6702 u8 field[0xc]; 6703 u8 reserved_at_10[0x3]; 6704 u8 offset[0x5]; 6705 u8 reserved_at_18[0x3]; 6706 u8 length[0x5]; 6707 6708 u8 data[0x20]; 6709 }; 6710 6711 struct mlx5_ifc_add_action_in_bits { 6712 u8 action_type[0x4]; 6713 u8 field[0xc]; 6714 u8 reserved_at_10[0x10]; 6715 6716 u8 data[0x20]; 6717 }; 6718 6719 struct mlx5_ifc_copy_action_in_bits { 6720 u8 action_type[0x4]; 6721 u8 src_field[0xc]; 6722 u8 reserved_at_10[0x3]; 6723 u8 src_offset[0x5]; 6724 u8 reserved_at_18[0x3]; 6725 u8 length[0x5]; 6726 6727 u8 reserved_at_20[0x4]; 6728 u8 dst_field[0xc]; 6729 u8 reserved_at_30[0x3]; 6730 u8 dst_offset[0x5]; 6731 u8 reserved_at_38[0x8]; 6732 }; 6733 6734 union mlx5_ifc_set_add_copy_action_in_auto_bits { 6735 struct mlx5_ifc_set_action_in_bits set_action_in; 6736 struct mlx5_ifc_add_action_in_bits add_action_in; 6737 struct mlx5_ifc_copy_action_in_bits copy_action_in; 6738 u8 reserved_at_0[0x40]; 6739 }; 6740 6741 enum { 6742 MLX5_ACTION_TYPE_SET = 0x1, 6743 MLX5_ACTION_TYPE_ADD = 0x2, 6744 MLX5_ACTION_TYPE_COPY = 0x3, 6745 }; 6746 6747 enum { 6748 MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16 = 0x1, 6749 MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0 = 0x2, 6750 MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE = 0x3, 6751 MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16 = 0x4, 6752 MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0 = 0x5, 6753 MLX5_ACTION_IN_FIELD_OUT_IP_DSCP = 0x6, 6754 MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS = 0x7, 6755 MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT = 0x8, 6756 MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT = 0x9, 6757 MLX5_ACTION_IN_FIELD_OUT_IP_TTL = 0xa, 6758 MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT = 0xb, 6759 MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT = 0xc, 6760 MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96 = 0xd, 6761 MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64 = 0xe, 6762 MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32 = 0xf, 6763 MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0 = 0x10, 6764 MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96 = 0x11, 6765 MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64 = 0x12, 6766 MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32 = 0x13, 6767 MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0 = 0x14, 6768 MLX5_ACTION_IN_FIELD_OUT_SIPV4 = 0x15, 6769 MLX5_ACTION_IN_FIELD_OUT_DIPV4 = 0x16, 6770 MLX5_ACTION_IN_FIELD_OUT_FIRST_VID = 0x17, 6771 MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47, 6772 MLX5_ACTION_IN_FIELD_METADATA_REG_A = 0x49, 6773 MLX5_ACTION_IN_FIELD_METADATA_REG_B = 0x50, 6774 MLX5_ACTION_IN_FIELD_METADATA_REG_C_0 = 0x51, 6775 MLX5_ACTION_IN_FIELD_METADATA_REG_C_1 = 0x52, 6776 MLX5_ACTION_IN_FIELD_METADATA_REG_C_2 = 0x53, 6777 MLX5_ACTION_IN_FIELD_METADATA_REG_C_3 = 0x54, 6778 MLX5_ACTION_IN_FIELD_METADATA_REG_C_4 = 0x55, 6779 MLX5_ACTION_IN_FIELD_METADATA_REG_C_5 = 0x56, 6780 MLX5_ACTION_IN_FIELD_METADATA_REG_C_6 = 0x57, 6781 MLX5_ACTION_IN_FIELD_METADATA_REG_C_7 = 0x58, 6782 MLX5_ACTION_IN_FIELD_OUT_TCP_SEQ_NUM = 0x59, 6783 MLX5_ACTION_IN_FIELD_OUT_TCP_ACK_NUM = 0x5B, 6784 MLX5_ACTION_IN_FIELD_IPSEC_SYNDROME = 0x5D, 6785 MLX5_ACTION_IN_FIELD_OUT_EMD_47_32 = 0x6F, 6786 MLX5_ACTION_IN_FIELD_OUT_EMD_31_0 = 0x70, 6787 }; 6788 6789 struct mlx5_ifc_alloc_modify_header_context_out_bits { 6790 u8 status[0x8]; 6791 u8 reserved_at_8[0x18]; 6792 6793 u8 syndrome[0x20]; 6794 6795 u8 modify_header_id[0x20]; 6796 6797 u8 reserved_at_60[0x20]; 6798 }; 6799 6800 struct mlx5_ifc_alloc_modify_header_context_in_bits { 6801 u8 opcode[0x10]; 6802 u8 reserved_at_10[0x10]; 6803 6804 u8 reserved_at_20[0x10]; 6805 u8 op_mod[0x10]; 6806 6807 u8 reserved_at_40[0x20]; 6808 6809 u8 table_type[0x8]; 6810 u8 reserved_at_68[0x10]; 6811 u8 num_of_actions[0x8]; 6812 6813 union mlx5_ifc_set_add_copy_action_in_auto_bits actions[]; 6814 }; 6815 6816 struct mlx5_ifc_dealloc_modify_header_context_out_bits { 6817 u8 status[0x8]; 6818 u8 reserved_at_8[0x18]; 6819 6820 u8 syndrome[0x20]; 6821 6822 u8 reserved_at_40[0x40]; 6823 }; 6824 6825 struct mlx5_ifc_dealloc_modify_header_context_in_bits { 6826 u8 opcode[0x10]; 6827 u8 reserved_at_10[0x10]; 6828 6829 u8 reserved_at_20[0x10]; 6830 u8 op_mod[0x10]; 6831 6832 u8 modify_header_id[0x20]; 6833 6834 u8 reserved_at_60[0x20]; 6835 }; 6836 6837 struct mlx5_ifc_query_modify_header_context_in_bits { 6838 u8 opcode[0x10]; 6839 u8 uid[0x10]; 6840 6841 u8 reserved_at_20[0x10]; 6842 u8 op_mod[0x10]; 6843 6844 u8 modify_header_id[0x20]; 6845 6846 u8 reserved_at_60[0xa0]; 6847 }; 6848 6849 struct mlx5_ifc_query_dct_out_bits { 6850 u8 status[0x8]; 6851 u8 reserved_at_8[0x18]; 6852 6853 u8 syndrome[0x20]; 6854 6855 u8 reserved_at_40[0x40]; 6856 6857 struct mlx5_ifc_dctc_bits dct_context_entry; 6858 6859 u8 reserved_at_280[0x180]; 6860 }; 6861 6862 struct mlx5_ifc_query_dct_in_bits { 6863 u8 opcode[0x10]; 6864 u8 reserved_at_10[0x10]; 6865 6866 u8 reserved_at_20[0x10]; 6867 u8 op_mod[0x10]; 6868 6869 u8 reserved_at_40[0x8]; 6870 u8 dctn[0x18]; 6871 6872 u8 reserved_at_60[0x20]; 6873 }; 6874 6875 struct mlx5_ifc_query_cq_out_bits { 6876 u8 status[0x8]; 6877 u8 reserved_at_8[0x18]; 6878 6879 u8 syndrome[0x20]; 6880 6881 u8 reserved_at_40[0x40]; 6882 6883 struct mlx5_ifc_cqc_bits cq_context; 6884 6885 u8 reserved_at_280[0x600]; 6886 6887 u8 pas[][0x40]; 6888 }; 6889 6890 struct mlx5_ifc_query_cq_in_bits { 6891 u8 opcode[0x10]; 6892 u8 reserved_at_10[0x10]; 6893 6894 u8 reserved_at_20[0x10]; 6895 u8 op_mod[0x10]; 6896 6897 u8 reserved_at_40[0x8]; 6898 u8 cqn[0x18]; 6899 6900 u8 reserved_at_60[0x20]; 6901 }; 6902 6903 struct mlx5_ifc_query_cong_status_out_bits { 6904 u8 status[0x8]; 6905 u8 reserved_at_8[0x18]; 6906 6907 u8 syndrome[0x20]; 6908 6909 u8 reserved_at_40[0x20]; 6910 6911 u8 enable[0x1]; 6912 u8 tag_enable[0x1]; 6913 u8 reserved_at_62[0x1e]; 6914 }; 6915 6916 struct mlx5_ifc_query_cong_status_in_bits { 6917 u8 opcode[0x10]; 6918 u8 reserved_at_10[0x10]; 6919 6920 u8 reserved_at_20[0x10]; 6921 u8 op_mod[0x10]; 6922 6923 u8 reserved_at_40[0x18]; 6924 u8 priority[0x4]; 6925 u8 cong_protocol[0x4]; 6926 6927 u8 reserved_at_60[0x20]; 6928 }; 6929 6930 struct mlx5_ifc_query_cong_statistics_out_bits { 6931 u8 status[0x8]; 6932 u8 reserved_at_8[0x18]; 6933 6934 u8 syndrome[0x20]; 6935 6936 u8 reserved_at_40[0x40]; 6937 6938 u8 rp_cur_flows[0x20]; 6939 6940 u8 sum_flows[0x20]; 6941 6942 u8 rp_cnp_ignored_high[0x20]; 6943 6944 u8 rp_cnp_ignored_low[0x20]; 6945 6946 u8 rp_cnp_handled_high[0x20]; 6947 6948 u8 rp_cnp_handled_low[0x20]; 6949 6950 u8 reserved_at_140[0x100]; 6951 6952 u8 time_stamp_high[0x20]; 6953 6954 u8 time_stamp_low[0x20]; 6955 6956 u8 accumulators_period[0x20]; 6957 6958 u8 np_ecn_marked_roce_packets_high[0x20]; 6959 6960 u8 np_ecn_marked_roce_packets_low[0x20]; 6961 6962 u8 np_cnp_sent_high[0x20]; 6963 6964 u8 np_cnp_sent_low[0x20]; 6965 6966 u8 reserved_at_320[0x560]; 6967 }; 6968 6969 struct mlx5_ifc_query_cong_statistics_in_bits { 6970 u8 opcode[0x10]; 6971 u8 reserved_at_10[0x10]; 6972 6973 u8 reserved_at_20[0x10]; 6974 u8 op_mod[0x10]; 6975 6976 u8 clear[0x1]; 6977 u8 reserved_at_41[0x1f]; 6978 6979 u8 reserved_at_60[0x20]; 6980 }; 6981 6982 struct mlx5_ifc_query_cong_params_out_bits { 6983 u8 status[0x8]; 6984 u8 reserved_at_8[0x18]; 6985 6986 u8 syndrome[0x20]; 6987 6988 u8 reserved_at_40[0x40]; 6989 6990 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 6991 }; 6992 6993 struct mlx5_ifc_query_cong_params_in_bits { 6994 u8 opcode[0x10]; 6995 u8 reserved_at_10[0x10]; 6996 6997 u8 reserved_at_20[0x10]; 6998 u8 op_mod[0x10]; 6999 7000 u8 reserved_at_40[0x1c]; 7001 u8 cong_protocol[0x4]; 7002 7003 u8 reserved_at_60[0x20]; 7004 }; 7005 7006 struct mlx5_ifc_query_adapter_out_bits { 7007 u8 status[0x8]; 7008 u8 reserved_at_8[0x18]; 7009 7010 u8 syndrome[0x20]; 7011 7012 u8 reserved_at_40[0x40]; 7013 7014 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct; 7015 }; 7016 7017 struct mlx5_ifc_query_adapter_in_bits { 7018 u8 opcode[0x10]; 7019 u8 reserved_at_10[0x10]; 7020 7021 u8 reserved_at_20[0x10]; 7022 u8 op_mod[0x10]; 7023 7024 u8 reserved_at_40[0x40]; 7025 }; 7026 7027 struct mlx5_ifc_qp_2rst_out_bits { 7028 u8 status[0x8]; 7029 u8 reserved_at_8[0x18]; 7030 7031 u8 syndrome[0x20]; 7032 7033 u8 reserved_at_40[0x40]; 7034 }; 7035 7036 struct mlx5_ifc_qp_2rst_in_bits { 7037 u8 opcode[0x10]; 7038 u8 uid[0x10]; 7039 7040 u8 reserved_at_20[0x10]; 7041 u8 op_mod[0x10]; 7042 7043 u8 reserved_at_40[0x8]; 7044 u8 qpn[0x18]; 7045 7046 u8 reserved_at_60[0x20]; 7047 }; 7048 7049 struct mlx5_ifc_qp_2err_out_bits { 7050 u8 status[0x8]; 7051 u8 reserved_at_8[0x18]; 7052 7053 u8 syndrome[0x20]; 7054 7055 u8 reserved_at_40[0x40]; 7056 }; 7057 7058 struct mlx5_ifc_qp_2err_in_bits { 7059 u8 opcode[0x10]; 7060 u8 uid[0x10]; 7061 7062 u8 reserved_at_20[0x10]; 7063 u8 op_mod[0x10]; 7064 7065 u8 reserved_at_40[0x8]; 7066 u8 qpn[0x18]; 7067 7068 u8 reserved_at_60[0x20]; 7069 }; 7070 7071 struct mlx5_ifc_page_fault_resume_out_bits { 7072 u8 status[0x8]; 7073 u8 reserved_at_8[0x18]; 7074 7075 u8 syndrome[0x20]; 7076 7077 u8 reserved_at_40[0x40]; 7078 }; 7079 7080 struct mlx5_ifc_page_fault_resume_in_bits { 7081 u8 opcode[0x10]; 7082 u8 reserved_at_10[0x10]; 7083 7084 u8 reserved_at_20[0x10]; 7085 u8 op_mod[0x10]; 7086 7087 u8 error[0x1]; 7088 u8 reserved_at_41[0x4]; 7089 u8 page_fault_type[0x3]; 7090 u8 wq_number[0x18]; 7091 7092 u8 reserved_at_60[0x8]; 7093 u8 token[0x18]; 7094 }; 7095 7096 struct mlx5_ifc_nop_out_bits { 7097 u8 status[0x8]; 7098 u8 reserved_at_8[0x18]; 7099 7100 u8 syndrome[0x20]; 7101 7102 u8 reserved_at_40[0x40]; 7103 }; 7104 7105 struct mlx5_ifc_nop_in_bits { 7106 u8 opcode[0x10]; 7107 u8 reserved_at_10[0x10]; 7108 7109 u8 reserved_at_20[0x10]; 7110 u8 op_mod[0x10]; 7111 7112 u8 reserved_at_40[0x40]; 7113 }; 7114 7115 struct mlx5_ifc_modify_vport_state_out_bits { 7116 u8 status[0x8]; 7117 u8 reserved_at_8[0x18]; 7118 7119 u8 syndrome[0x20]; 7120 7121 u8 reserved_at_40[0x40]; 7122 }; 7123 7124 struct mlx5_ifc_modify_vport_state_in_bits { 7125 u8 opcode[0x10]; 7126 u8 reserved_at_10[0x10]; 7127 7128 u8 reserved_at_20[0x10]; 7129 u8 op_mod[0x10]; 7130 7131 u8 other_vport[0x1]; 7132 u8 reserved_at_41[0xf]; 7133 u8 vport_number[0x10]; 7134 7135 u8 reserved_at_60[0x18]; 7136 u8 admin_state[0x4]; 7137 u8 reserved_at_7c[0x4]; 7138 }; 7139 7140 struct mlx5_ifc_modify_tis_out_bits { 7141 u8 status[0x8]; 7142 u8 reserved_at_8[0x18]; 7143 7144 u8 syndrome[0x20]; 7145 7146 u8 reserved_at_40[0x40]; 7147 }; 7148 7149 struct mlx5_ifc_modify_tis_bitmask_bits { 7150 u8 reserved_at_0[0x20]; 7151 7152 u8 reserved_at_20[0x1d]; 7153 u8 lag_tx_port_affinity[0x1]; 7154 u8 strict_lag_tx_port_affinity[0x1]; 7155 u8 prio[0x1]; 7156 }; 7157 7158 struct mlx5_ifc_modify_tis_in_bits { 7159 u8 opcode[0x10]; 7160 u8 uid[0x10]; 7161 7162 u8 reserved_at_20[0x10]; 7163 u8 op_mod[0x10]; 7164 7165 u8 reserved_at_40[0x8]; 7166 u8 tisn[0x18]; 7167 7168 u8 reserved_at_60[0x20]; 7169 7170 struct mlx5_ifc_modify_tis_bitmask_bits bitmask; 7171 7172 u8 reserved_at_c0[0x40]; 7173 7174 struct mlx5_ifc_tisc_bits ctx; 7175 }; 7176 7177 struct mlx5_ifc_modify_tir_bitmask_bits { 7178 u8 reserved_at_0[0x20]; 7179 7180 u8 reserved_at_20[0x1b]; 7181 u8 self_lb_en[0x1]; 7182 u8 reserved_at_3c[0x1]; 7183 u8 hash[0x1]; 7184 u8 reserved_at_3e[0x1]; 7185 u8 packet_merge[0x1]; 7186 }; 7187 7188 struct mlx5_ifc_modify_tir_out_bits { 7189 u8 status[0x8]; 7190 u8 reserved_at_8[0x18]; 7191 7192 u8 syndrome[0x20]; 7193 7194 u8 reserved_at_40[0x40]; 7195 }; 7196 7197 struct mlx5_ifc_modify_tir_in_bits { 7198 u8 opcode[0x10]; 7199 u8 uid[0x10]; 7200 7201 u8 reserved_at_20[0x10]; 7202 u8 op_mod[0x10]; 7203 7204 u8 reserved_at_40[0x8]; 7205 u8 tirn[0x18]; 7206 7207 u8 reserved_at_60[0x20]; 7208 7209 struct mlx5_ifc_modify_tir_bitmask_bits bitmask; 7210 7211 u8 reserved_at_c0[0x40]; 7212 7213 struct mlx5_ifc_tirc_bits ctx; 7214 }; 7215 7216 struct mlx5_ifc_modify_sq_out_bits { 7217 u8 status[0x8]; 7218 u8 reserved_at_8[0x18]; 7219 7220 u8 syndrome[0x20]; 7221 7222 u8 reserved_at_40[0x40]; 7223 }; 7224 7225 struct mlx5_ifc_modify_sq_in_bits { 7226 u8 opcode[0x10]; 7227 u8 uid[0x10]; 7228 7229 u8 reserved_at_20[0x10]; 7230 u8 op_mod[0x10]; 7231 7232 u8 sq_state[0x4]; 7233 u8 reserved_at_44[0x4]; 7234 u8 sqn[0x18]; 7235 7236 u8 reserved_at_60[0x20]; 7237 7238 u8 modify_bitmask[0x40]; 7239 7240 u8 reserved_at_c0[0x40]; 7241 7242 struct mlx5_ifc_sqc_bits ctx; 7243 }; 7244 7245 struct mlx5_ifc_modify_scheduling_element_out_bits { 7246 u8 status[0x8]; 7247 u8 reserved_at_8[0x18]; 7248 7249 u8 syndrome[0x20]; 7250 7251 u8 reserved_at_40[0x1c0]; 7252 }; 7253 7254 enum { 7255 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1, 7256 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2, 7257 }; 7258 7259 struct mlx5_ifc_modify_scheduling_element_in_bits { 7260 u8 opcode[0x10]; 7261 u8 reserved_at_10[0x10]; 7262 7263 u8 reserved_at_20[0x10]; 7264 u8 op_mod[0x10]; 7265 7266 u8 scheduling_hierarchy[0x8]; 7267 u8 reserved_at_48[0x18]; 7268 7269 u8 scheduling_element_id[0x20]; 7270 7271 u8 reserved_at_80[0x20]; 7272 7273 u8 modify_bitmask[0x20]; 7274 7275 u8 reserved_at_c0[0x40]; 7276 7277 struct mlx5_ifc_scheduling_context_bits scheduling_context; 7278 7279 u8 reserved_at_300[0x100]; 7280 }; 7281 7282 struct mlx5_ifc_modify_rqt_out_bits { 7283 u8 status[0x8]; 7284 u8 reserved_at_8[0x18]; 7285 7286 u8 syndrome[0x20]; 7287 7288 u8 reserved_at_40[0x40]; 7289 }; 7290 7291 struct mlx5_ifc_rqt_bitmask_bits { 7292 u8 reserved_at_0[0x20]; 7293 7294 u8 reserved_at_20[0x1f]; 7295 u8 rqn_list[0x1]; 7296 }; 7297 7298 struct mlx5_ifc_modify_rqt_in_bits { 7299 u8 opcode[0x10]; 7300 u8 uid[0x10]; 7301 7302 u8 reserved_at_20[0x10]; 7303 u8 op_mod[0x10]; 7304 7305 u8 reserved_at_40[0x8]; 7306 u8 rqtn[0x18]; 7307 7308 u8 reserved_at_60[0x20]; 7309 7310 struct mlx5_ifc_rqt_bitmask_bits bitmask; 7311 7312 u8 reserved_at_c0[0x40]; 7313 7314 struct mlx5_ifc_rqtc_bits ctx; 7315 }; 7316 7317 struct mlx5_ifc_modify_rq_out_bits { 7318 u8 status[0x8]; 7319 u8 reserved_at_8[0x18]; 7320 7321 u8 syndrome[0x20]; 7322 7323 u8 reserved_at_40[0x40]; 7324 }; 7325 7326 enum { 7327 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1, 7328 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2, 7329 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3, 7330 }; 7331 7332 struct mlx5_ifc_modify_rq_in_bits { 7333 u8 opcode[0x10]; 7334 u8 uid[0x10]; 7335 7336 u8 reserved_at_20[0x10]; 7337 u8 op_mod[0x10]; 7338 7339 u8 rq_state[0x4]; 7340 u8 reserved_at_44[0x4]; 7341 u8 rqn[0x18]; 7342 7343 u8 reserved_at_60[0x20]; 7344 7345 u8 modify_bitmask[0x40]; 7346 7347 u8 reserved_at_c0[0x40]; 7348 7349 struct mlx5_ifc_rqc_bits ctx; 7350 }; 7351 7352 struct mlx5_ifc_modify_rmp_out_bits { 7353 u8 status[0x8]; 7354 u8 reserved_at_8[0x18]; 7355 7356 u8 syndrome[0x20]; 7357 7358 u8 reserved_at_40[0x40]; 7359 }; 7360 7361 struct mlx5_ifc_rmp_bitmask_bits { 7362 u8 reserved_at_0[0x20]; 7363 7364 u8 reserved_at_20[0x1f]; 7365 u8 lwm[0x1]; 7366 }; 7367 7368 struct mlx5_ifc_modify_rmp_in_bits { 7369 u8 opcode[0x10]; 7370 u8 uid[0x10]; 7371 7372 u8 reserved_at_20[0x10]; 7373 u8 op_mod[0x10]; 7374 7375 u8 rmp_state[0x4]; 7376 u8 reserved_at_44[0x4]; 7377 u8 rmpn[0x18]; 7378 7379 u8 reserved_at_60[0x20]; 7380 7381 struct mlx5_ifc_rmp_bitmask_bits bitmask; 7382 7383 u8 reserved_at_c0[0x40]; 7384 7385 struct mlx5_ifc_rmpc_bits ctx; 7386 }; 7387 7388 struct mlx5_ifc_modify_nic_vport_context_out_bits { 7389 u8 status[0x8]; 7390 u8 reserved_at_8[0x18]; 7391 7392 u8 syndrome[0x20]; 7393 7394 u8 reserved_at_40[0x40]; 7395 }; 7396 7397 struct mlx5_ifc_modify_nic_vport_field_select_bits { 7398 u8 reserved_at_0[0x12]; 7399 u8 affiliation[0x1]; 7400 u8 reserved_at_13[0x1]; 7401 u8 disable_uc_local_lb[0x1]; 7402 u8 disable_mc_local_lb[0x1]; 7403 u8 node_guid[0x1]; 7404 u8 port_guid[0x1]; 7405 u8 min_inline[0x1]; 7406 u8 mtu[0x1]; 7407 u8 change_event[0x1]; 7408 u8 promisc[0x1]; 7409 u8 permanent_address[0x1]; 7410 u8 addresses_list[0x1]; 7411 u8 roce_en[0x1]; 7412 u8 reserved_at_1f[0x1]; 7413 }; 7414 7415 struct mlx5_ifc_modify_nic_vport_context_in_bits { 7416 u8 opcode[0x10]; 7417 u8 reserved_at_10[0x10]; 7418 7419 u8 reserved_at_20[0x10]; 7420 u8 op_mod[0x10]; 7421 7422 u8 other_vport[0x1]; 7423 u8 reserved_at_41[0xf]; 7424 u8 vport_number[0x10]; 7425 7426 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select; 7427 7428 u8 reserved_at_80[0x780]; 7429 7430 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 7431 }; 7432 7433 struct mlx5_ifc_modify_hca_vport_context_out_bits { 7434 u8 status[0x8]; 7435 u8 reserved_at_8[0x18]; 7436 7437 u8 syndrome[0x20]; 7438 7439 u8 reserved_at_40[0x40]; 7440 }; 7441 7442 struct mlx5_ifc_modify_hca_vport_context_in_bits { 7443 u8 opcode[0x10]; 7444 u8 reserved_at_10[0x10]; 7445 7446 u8 reserved_at_20[0x10]; 7447 u8 op_mod[0x10]; 7448 7449 u8 other_vport[0x1]; 7450 u8 reserved_at_41[0xb]; 7451 u8 port_num[0x4]; 7452 u8 vport_number[0x10]; 7453 7454 u8 reserved_at_60[0x20]; 7455 7456 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 7457 }; 7458 7459 struct mlx5_ifc_modify_cq_out_bits { 7460 u8 status[0x8]; 7461 u8 reserved_at_8[0x18]; 7462 7463 u8 syndrome[0x20]; 7464 7465 u8 reserved_at_40[0x40]; 7466 }; 7467 7468 enum { 7469 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0, 7470 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1, 7471 }; 7472 7473 struct mlx5_ifc_modify_cq_in_bits { 7474 u8 opcode[0x10]; 7475 u8 uid[0x10]; 7476 7477 u8 reserved_at_20[0x10]; 7478 u8 op_mod[0x10]; 7479 7480 u8 reserved_at_40[0x8]; 7481 u8 cqn[0x18]; 7482 7483 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select; 7484 7485 struct mlx5_ifc_cqc_bits cq_context; 7486 7487 u8 reserved_at_280[0x60]; 7488 7489 u8 cq_umem_valid[0x1]; 7490 u8 reserved_at_2e1[0x1f]; 7491 7492 u8 reserved_at_300[0x580]; 7493 7494 u8 pas[][0x40]; 7495 }; 7496 7497 struct mlx5_ifc_modify_cong_status_out_bits { 7498 u8 status[0x8]; 7499 u8 reserved_at_8[0x18]; 7500 7501 u8 syndrome[0x20]; 7502 7503 u8 reserved_at_40[0x40]; 7504 }; 7505 7506 struct mlx5_ifc_modify_cong_status_in_bits { 7507 u8 opcode[0x10]; 7508 u8 reserved_at_10[0x10]; 7509 7510 u8 reserved_at_20[0x10]; 7511 u8 op_mod[0x10]; 7512 7513 u8 reserved_at_40[0x18]; 7514 u8 priority[0x4]; 7515 u8 cong_protocol[0x4]; 7516 7517 u8 enable[0x1]; 7518 u8 tag_enable[0x1]; 7519 u8 reserved_at_62[0x1e]; 7520 }; 7521 7522 struct mlx5_ifc_modify_cong_params_out_bits { 7523 u8 status[0x8]; 7524 u8 reserved_at_8[0x18]; 7525 7526 u8 syndrome[0x20]; 7527 7528 u8 reserved_at_40[0x40]; 7529 }; 7530 7531 struct mlx5_ifc_modify_cong_params_in_bits { 7532 u8 opcode[0x10]; 7533 u8 reserved_at_10[0x10]; 7534 7535 u8 reserved_at_20[0x10]; 7536 u8 op_mod[0x10]; 7537 7538 u8 reserved_at_40[0x1c]; 7539 u8 cong_protocol[0x4]; 7540 7541 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select; 7542 7543 u8 reserved_at_80[0x80]; 7544 7545 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 7546 }; 7547 7548 struct mlx5_ifc_manage_pages_out_bits { 7549 u8 status[0x8]; 7550 u8 reserved_at_8[0x18]; 7551 7552 u8 syndrome[0x20]; 7553 7554 u8 output_num_entries[0x20]; 7555 7556 u8 reserved_at_60[0x20]; 7557 7558 u8 pas[][0x40]; 7559 }; 7560 7561 enum { 7562 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL = 0x0, 7563 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS = 0x1, 7564 MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES = 0x2, 7565 }; 7566 7567 struct mlx5_ifc_manage_pages_in_bits { 7568 u8 opcode[0x10]; 7569 u8 reserved_at_10[0x10]; 7570 7571 u8 reserved_at_20[0x10]; 7572 u8 op_mod[0x10]; 7573 7574 u8 embedded_cpu_function[0x1]; 7575 u8 reserved_at_41[0xf]; 7576 u8 function_id[0x10]; 7577 7578 u8 input_num_entries[0x20]; 7579 7580 u8 pas[][0x40]; 7581 }; 7582 7583 struct mlx5_ifc_mad_ifc_out_bits { 7584 u8 status[0x8]; 7585 u8 reserved_at_8[0x18]; 7586 7587 u8 syndrome[0x20]; 7588 7589 u8 reserved_at_40[0x40]; 7590 7591 u8 response_mad_packet[256][0x8]; 7592 }; 7593 7594 struct mlx5_ifc_mad_ifc_in_bits { 7595 u8 opcode[0x10]; 7596 u8 reserved_at_10[0x10]; 7597 7598 u8 reserved_at_20[0x10]; 7599 u8 op_mod[0x10]; 7600 7601 u8 remote_lid[0x10]; 7602 u8 reserved_at_50[0x8]; 7603 u8 port[0x8]; 7604 7605 u8 reserved_at_60[0x20]; 7606 7607 u8 mad[256][0x8]; 7608 }; 7609 7610 struct mlx5_ifc_init_hca_out_bits { 7611 u8 status[0x8]; 7612 u8 reserved_at_8[0x18]; 7613 7614 u8 syndrome[0x20]; 7615 7616 u8 reserved_at_40[0x40]; 7617 }; 7618 7619 struct mlx5_ifc_init_hca_in_bits { 7620 u8 opcode[0x10]; 7621 u8 reserved_at_10[0x10]; 7622 7623 u8 reserved_at_20[0x10]; 7624 u8 op_mod[0x10]; 7625 7626 u8 reserved_at_40[0x20]; 7627 7628 u8 reserved_at_60[0x2]; 7629 u8 sw_vhca_id[0xe]; 7630 u8 reserved_at_70[0x10]; 7631 7632 u8 sw_owner_id[4][0x20]; 7633 }; 7634 7635 struct mlx5_ifc_init2rtr_qp_out_bits { 7636 u8 status[0x8]; 7637 u8 reserved_at_8[0x18]; 7638 7639 u8 syndrome[0x20]; 7640 7641 u8 reserved_at_40[0x20]; 7642 u8 ece[0x20]; 7643 }; 7644 7645 struct mlx5_ifc_init2rtr_qp_in_bits { 7646 u8 opcode[0x10]; 7647 u8 uid[0x10]; 7648 7649 u8 reserved_at_20[0x10]; 7650 u8 op_mod[0x10]; 7651 7652 u8 reserved_at_40[0x8]; 7653 u8 qpn[0x18]; 7654 7655 u8 reserved_at_60[0x20]; 7656 7657 u8 opt_param_mask[0x20]; 7658 7659 u8 ece[0x20]; 7660 7661 struct mlx5_ifc_qpc_bits qpc; 7662 7663 u8 reserved_at_800[0x80]; 7664 }; 7665 7666 struct mlx5_ifc_init2init_qp_out_bits { 7667 u8 status[0x8]; 7668 u8 reserved_at_8[0x18]; 7669 7670 u8 syndrome[0x20]; 7671 7672 u8 reserved_at_40[0x20]; 7673 u8 ece[0x20]; 7674 }; 7675 7676 struct mlx5_ifc_init2init_qp_in_bits { 7677 u8 opcode[0x10]; 7678 u8 uid[0x10]; 7679 7680 u8 reserved_at_20[0x10]; 7681 u8 op_mod[0x10]; 7682 7683 u8 reserved_at_40[0x8]; 7684 u8 qpn[0x18]; 7685 7686 u8 reserved_at_60[0x20]; 7687 7688 u8 opt_param_mask[0x20]; 7689 7690 u8 ece[0x20]; 7691 7692 struct mlx5_ifc_qpc_bits qpc; 7693 7694 u8 reserved_at_800[0x80]; 7695 }; 7696 7697 struct mlx5_ifc_get_dropped_packet_log_out_bits { 7698 u8 status[0x8]; 7699 u8 reserved_at_8[0x18]; 7700 7701 u8 syndrome[0x20]; 7702 7703 u8 reserved_at_40[0x40]; 7704 7705 u8 packet_headers_log[128][0x8]; 7706 7707 u8 packet_syndrome[64][0x8]; 7708 }; 7709 7710 struct mlx5_ifc_get_dropped_packet_log_in_bits { 7711 u8 opcode[0x10]; 7712 u8 reserved_at_10[0x10]; 7713 7714 u8 reserved_at_20[0x10]; 7715 u8 op_mod[0x10]; 7716 7717 u8 reserved_at_40[0x40]; 7718 }; 7719 7720 struct mlx5_ifc_gen_eqe_in_bits { 7721 u8 opcode[0x10]; 7722 u8 reserved_at_10[0x10]; 7723 7724 u8 reserved_at_20[0x10]; 7725 u8 op_mod[0x10]; 7726 7727 u8 reserved_at_40[0x18]; 7728 u8 eq_number[0x8]; 7729 7730 u8 reserved_at_60[0x20]; 7731 7732 u8 eqe[64][0x8]; 7733 }; 7734 7735 struct mlx5_ifc_gen_eq_out_bits { 7736 u8 status[0x8]; 7737 u8 reserved_at_8[0x18]; 7738 7739 u8 syndrome[0x20]; 7740 7741 u8 reserved_at_40[0x40]; 7742 }; 7743 7744 struct mlx5_ifc_enable_hca_out_bits { 7745 u8 status[0x8]; 7746 u8 reserved_at_8[0x18]; 7747 7748 u8 syndrome[0x20]; 7749 7750 u8 reserved_at_40[0x20]; 7751 }; 7752 7753 struct mlx5_ifc_enable_hca_in_bits { 7754 u8 opcode[0x10]; 7755 u8 reserved_at_10[0x10]; 7756 7757 u8 reserved_at_20[0x10]; 7758 u8 op_mod[0x10]; 7759 7760 u8 embedded_cpu_function[0x1]; 7761 u8 reserved_at_41[0xf]; 7762 u8 function_id[0x10]; 7763 7764 u8 reserved_at_60[0x20]; 7765 }; 7766 7767 struct mlx5_ifc_drain_dct_out_bits { 7768 u8 status[0x8]; 7769 u8 reserved_at_8[0x18]; 7770 7771 u8 syndrome[0x20]; 7772 7773 u8 reserved_at_40[0x40]; 7774 }; 7775 7776 struct mlx5_ifc_drain_dct_in_bits { 7777 u8 opcode[0x10]; 7778 u8 uid[0x10]; 7779 7780 u8 reserved_at_20[0x10]; 7781 u8 op_mod[0x10]; 7782 7783 u8 reserved_at_40[0x8]; 7784 u8 dctn[0x18]; 7785 7786 u8 reserved_at_60[0x20]; 7787 }; 7788 7789 struct mlx5_ifc_disable_hca_out_bits { 7790 u8 status[0x8]; 7791 u8 reserved_at_8[0x18]; 7792 7793 u8 syndrome[0x20]; 7794 7795 u8 reserved_at_40[0x20]; 7796 }; 7797 7798 struct mlx5_ifc_disable_hca_in_bits { 7799 u8 opcode[0x10]; 7800 u8 reserved_at_10[0x10]; 7801 7802 u8 reserved_at_20[0x10]; 7803 u8 op_mod[0x10]; 7804 7805 u8 embedded_cpu_function[0x1]; 7806 u8 reserved_at_41[0xf]; 7807 u8 function_id[0x10]; 7808 7809 u8 reserved_at_60[0x20]; 7810 }; 7811 7812 struct mlx5_ifc_detach_from_mcg_out_bits { 7813 u8 status[0x8]; 7814 u8 reserved_at_8[0x18]; 7815 7816 u8 syndrome[0x20]; 7817 7818 u8 reserved_at_40[0x40]; 7819 }; 7820 7821 struct mlx5_ifc_detach_from_mcg_in_bits { 7822 u8 opcode[0x10]; 7823 u8 uid[0x10]; 7824 7825 u8 reserved_at_20[0x10]; 7826 u8 op_mod[0x10]; 7827 7828 u8 reserved_at_40[0x8]; 7829 u8 qpn[0x18]; 7830 7831 u8 reserved_at_60[0x20]; 7832 7833 u8 multicast_gid[16][0x8]; 7834 }; 7835 7836 struct mlx5_ifc_destroy_xrq_out_bits { 7837 u8 status[0x8]; 7838 u8 reserved_at_8[0x18]; 7839 7840 u8 syndrome[0x20]; 7841 7842 u8 reserved_at_40[0x40]; 7843 }; 7844 7845 struct mlx5_ifc_destroy_xrq_in_bits { 7846 u8 opcode[0x10]; 7847 u8 uid[0x10]; 7848 7849 u8 reserved_at_20[0x10]; 7850 u8 op_mod[0x10]; 7851 7852 u8 reserved_at_40[0x8]; 7853 u8 xrqn[0x18]; 7854 7855 u8 reserved_at_60[0x20]; 7856 }; 7857 7858 struct mlx5_ifc_destroy_xrc_srq_out_bits { 7859 u8 status[0x8]; 7860 u8 reserved_at_8[0x18]; 7861 7862 u8 syndrome[0x20]; 7863 7864 u8 reserved_at_40[0x40]; 7865 }; 7866 7867 struct mlx5_ifc_destroy_xrc_srq_in_bits { 7868 u8 opcode[0x10]; 7869 u8 uid[0x10]; 7870 7871 u8 reserved_at_20[0x10]; 7872 u8 op_mod[0x10]; 7873 7874 u8 reserved_at_40[0x8]; 7875 u8 xrc_srqn[0x18]; 7876 7877 u8 reserved_at_60[0x20]; 7878 }; 7879 7880 struct mlx5_ifc_destroy_tis_out_bits { 7881 u8 status[0x8]; 7882 u8 reserved_at_8[0x18]; 7883 7884 u8 syndrome[0x20]; 7885 7886 u8 reserved_at_40[0x40]; 7887 }; 7888 7889 struct mlx5_ifc_destroy_tis_in_bits { 7890 u8 opcode[0x10]; 7891 u8 uid[0x10]; 7892 7893 u8 reserved_at_20[0x10]; 7894 u8 op_mod[0x10]; 7895 7896 u8 reserved_at_40[0x8]; 7897 u8 tisn[0x18]; 7898 7899 u8 reserved_at_60[0x20]; 7900 }; 7901 7902 struct mlx5_ifc_destroy_tir_out_bits { 7903 u8 status[0x8]; 7904 u8 reserved_at_8[0x18]; 7905 7906 u8 syndrome[0x20]; 7907 7908 u8 reserved_at_40[0x40]; 7909 }; 7910 7911 struct mlx5_ifc_destroy_tir_in_bits { 7912 u8 opcode[0x10]; 7913 u8 uid[0x10]; 7914 7915 u8 reserved_at_20[0x10]; 7916 u8 op_mod[0x10]; 7917 7918 u8 reserved_at_40[0x8]; 7919 u8 tirn[0x18]; 7920 7921 u8 reserved_at_60[0x20]; 7922 }; 7923 7924 struct mlx5_ifc_destroy_srq_out_bits { 7925 u8 status[0x8]; 7926 u8 reserved_at_8[0x18]; 7927 7928 u8 syndrome[0x20]; 7929 7930 u8 reserved_at_40[0x40]; 7931 }; 7932 7933 struct mlx5_ifc_destroy_srq_in_bits { 7934 u8 opcode[0x10]; 7935 u8 uid[0x10]; 7936 7937 u8 reserved_at_20[0x10]; 7938 u8 op_mod[0x10]; 7939 7940 u8 reserved_at_40[0x8]; 7941 u8 srqn[0x18]; 7942 7943 u8 reserved_at_60[0x20]; 7944 }; 7945 7946 struct mlx5_ifc_destroy_sq_out_bits { 7947 u8 status[0x8]; 7948 u8 reserved_at_8[0x18]; 7949 7950 u8 syndrome[0x20]; 7951 7952 u8 reserved_at_40[0x40]; 7953 }; 7954 7955 struct mlx5_ifc_destroy_sq_in_bits { 7956 u8 opcode[0x10]; 7957 u8 uid[0x10]; 7958 7959 u8 reserved_at_20[0x10]; 7960 u8 op_mod[0x10]; 7961 7962 u8 reserved_at_40[0x8]; 7963 u8 sqn[0x18]; 7964 7965 u8 reserved_at_60[0x20]; 7966 }; 7967 7968 struct mlx5_ifc_destroy_scheduling_element_out_bits { 7969 u8 status[0x8]; 7970 u8 reserved_at_8[0x18]; 7971 7972 u8 syndrome[0x20]; 7973 7974 u8 reserved_at_40[0x1c0]; 7975 }; 7976 7977 struct mlx5_ifc_destroy_scheduling_element_in_bits { 7978 u8 opcode[0x10]; 7979 u8 reserved_at_10[0x10]; 7980 7981 u8 reserved_at_20[0x10]; 7982 u8 op_mod[0x10]; 7983 7984 u8 scheduling_hierarchy[0x8]; 7985 u8 reserved_at_48[0x18]; 7986 7987 u8 scheduling_element_id[0x20]; 7988 7989 u8 reserved_at_80[0x180]; 7990 }; 7991 7992 struct mlx5_ifc_destroy_rqt_out_bits { 7993 u8 status[0x8]; 7994 u8 reserved_at_8[0x18]; 7995 7996 u8 syndrome[0x20]; 7997 7998 u8 reserved_at_40[0x40]; 7999 }; 8000 8001 struct mlx5_ifc_destroy_rqt_in_bits { 8002 u8 opcode[0x10]; 8003 u8 uid[0x10]; 8004 8005 u8 reserved_at_20[0x10]; 8006 u8 op_mod[0x10]; 8007 8008 u8 reserved_at_40[0x8]; 8009 u8 rqtn[0x18]; 8010 8011 u8 reserved_at_60[0x20]; 8012 }; 8013 8014 struct mlx5_ifc_destroy_rq_out_bits { 8015 u8 status[0x8]; 8016 u8 reserved_at_8[0x18]; 8017 8018 u8 syndrome[0x20]; 8019 8020 u8 reserved_at_40[0x40]; 8021 }; 8022 8023 struct mlx5_ifc_destroy_rq_in_bits { 8024 u8 opcode[0x10]; 8025 u8 uid[0x10]; 8026 8027 u8 reserved_at_20[0x10]; 8028 u8 op_mod[0x10]; 8029 8030 u8 reserved_at_40[0x8]; 8031 u8 rqn[0x18]; 8032 8033 u8 reserved_at_60[0x20]; 8034 }; 8035 8036 struct mlx5_ifc_set_delay_drop_params_in_bits { 8037 u8 opcode[0x10]; 8038 u8 reserved_at_10[0x10]; 8039 8040 u8 reserved_at_20[0x10]; 8041 u8 op_mod[0x10]; 8042 8043 u8 reserved_at_40[0x20]; 8044 8045 u8 reserved_at_60[0x10]; 8046 u8 delay_drop_timeout[0x10]; 8047 }; 8048 8049 struct mlx5_ifc_set_delay_drop_params_out_bits { 8050 u8 status[0x8]; 8051 u8 reserved_at_8[0x18]; 8052 8053 u8 syndrome[0x20]; 8054 8055 u8 reserved_at_40[0x40]; 8056 }; 8057 8058 struct mlx5_ifc_destroy_rmp_out_bits { 8059 u8 status[0x8]; 8060 u8 reserved_at_8[0x18]; 8061 8062 u8 syndrome[0x20]; 8063 8064 u8 reserved_at_40[0x40]; 8065 }; 8066 8067 struct mlx5_ifc_destroy_rmp_in_bits { 8068 u8 opcode[0x10]; 8069 u8 uid[0x10]; 8070 8071 u8 reserved_at_20[0x10]; 8072 u8 op_mod[0x10]; 8073 8074 u8 reserved_at_40[0x8]; 8075 u8 rmpn[0x18]; 8076 8077 u8 reserved_at_60[0x20]; 8078 }; 8079 8080 struct mlx5_ifc_destroy_qp_out_bits { 8081 u8 status[0x8]; 8082 u8 reserved_at_8[0x18]; 8083 8084 u8 syndrome[0x20]; 8085 8086 u8 reserved_at_40[0x40]; 8087 }; 8088 8089 struct mlx5_ifc_destroy_qp_in_bits { 8090 u8 opcode[0x10]; 8091 u8 uid[0x10]; 8092 8093 u8 reserved_at_20[0x10]; 8094 u8 op_mod[0x10]; 8095 8096 u8 reserved_at_40[0x8]; 8097 u8 qpn[0x18]; 8098 8099 u8 reserved_at_60[0x20]; 8100 }; 8101 8102 struct mlx5_ifc_destroy_psv_out_bits { 8103 u8 status[0x8]; 8104 u8 reserved_at_8[0x18]; 8105 8106 u8 syndrome[0x20]; 8107 8108 u8 reserved_at_40[0x40]; 8109 }; 8110 8111 struct mlx5_ifc_destroy_psv_in_bits { 8112 u8 opcode[0x10]; 8113 u8 reserved_at_10[0x10]; 8114 8115 u8 reserved_at_20[0x10]; 8116 u8 op_mod[0x10]; 8117 8118 u8 reserved_at_40[0x8]; 8119 u8 psvn[0x18]; 8120 8121 u8 reserved_at_60[0x20]; 8122 }; 8123 8124 struct mlx5_ifc_destroy_mkey_out_bits { 8125 u8 status[0x8]; 8126 u8 reserved_at_8[0x18]; 8127 8128 u8 syndrome[0x20]; 8129 8130 u8 reserved_at_40[0x40]; 8131 }; 8132 8133 struct mlx5_ifc_destroy_mkey_in_bits { 8134 u8 opcode[0x10]; 8135 u8 uid[0x10]; 8136 8137 u8 reserved_at_20[0x10]; 8138 u8 op_mod[0x10]; 8139 8140 u8 reserved_at_40[0x8]; 8141 u8 mkey_index[0x18]; 8142 8143 u8 reserved_at_60[0x20]; 8144 }; 8145 8146 struct mlx5_ifc_destroy_flow_table_out_bits { 8147 u8 status[0x8]; 8148 u8 reserved_at_8[0x18]; 8149 8150 u8 syndrome[0x20]; 8151 8152 u8 reserved_at_40[0x40]; 8153 }; 8154 8155 struct mlx5_ifc_destroy_flow_table_in_bits { 8156 u8 opcode[0x10]; 8157 u8 reserved_at_10[0x10]; 8158 8159 u8 reserved_at_20[0x10]; 8160 u8 op_mod[0x10]; 8161 8162 u8 other_vport[0x1]; 8163 u8 reserved_at_41[0xf]; 8164 u8 vport_number[0x10]; 8165 8166 u8 reserved_at_60[0x20]; 8167 8168 u8 table_type[0x8]; 8169 u8 reserved_at_88[0x18]; 8170 8171 u8 reserved_at_a0[0x8]; 8172 u8 table_id[0x18]; 8173 8174 u8 reserved_at_c0[0x140]; 8175 }; 8176 8177 struct mlx5_ifc_destroy_flow_group_out_bits { 8178 u8 status[0x8]; 8179 u8 reserved_at_8[0x18]; 8180 8181 u8 syndrome[0x20]; 8182 8183 u8 reserved_at_40[0x40]; 8184 }; 8185 8186 struct mlx5_ifc_destroy_flow_group_in_bits { 8187 u8 opcode[0x10]; 8188 u8 reserved_at_10[0x10]; 8189 8190 u8 reserved_at_20[0x10]; 8191 u8 op_mod[0x10]; 8192 8193 u8 other_vport[0x1]; 8194 u8 reserved_at_41[0xf]; 8195 u8 vport_number[0x10]; 8196 8197 u8 reserved_at_60[0x20]; 8198 8199 u8 table_type[0x8]; 8200 u8 reserved_at_88[0x18]; 8201 8202 u8 reserved_at_a0[0x8]; 8203 u8 table_id[0x18]; 8204 8205 u8 group_id[0x20]; 8206 8207 u8 reserved_at_e0[0x120]; 8208 }; 8209 8210 struct mlx5_ifc_destroy_eq_out_bits { 8211 u8 status[0x8]; 8212 u8 reserved_at_8[0x18]; 8213 8214 u8 syndrome[0x20]; 8215 8216 u8 reserved_at_40[0x40]; 8217 }; 8218 8219 struct mlx5_ifc_destroy_eq_in_bits { 8220 u8 opcode[0x10]; 8221 u8 reserved_at_10[0x10]; 8222 8223 u8 reserved_at_20[0x10]; 8224 u8 op_mod[0x10]; 8225 8226 u8 reserved_at_40[0x18]; 8227 u8 eq_number[0x8]; 8228 8229 u8 reserved_at_60[0x20]; 8230 }; 8231 8232 struct mlx5_ifc_destroy_dct_out_bits { 8233 u8 status[0x8]; 8234 u8 reserved_at_8[0x18]; 8235 8236 u8 syndrome[0x20]; 8237 8238 u8 reserved_at_40[0x40]; 8239 }; 8240 8241 struct mlx5_ifc_destroy_dct_in_bits { 8242 u8 opcode[0x10]; 8243 u8 uid[0x10]; 8244 8245 u8 reserved_at_20[0x10]; 8246 u8 op_mod[0x10]; 8247 8248 u8 reserved_at_40[0x8]; 8249 u8 dctn[0x18]; 8250 8251 u8 reserved_at_60[0x20]; 8252 }; 8253 8254 struct mlx5_ifc_destroy_cq_out_bits { 8255 u8 status[0x8]; 8256 u8 reserved_at_8[0x18]; 8257 8258 u8 syndrome[0x20]; 8259 8260 u8 reserved_at_40[0x40]; 8261 }; 8262 8263 struct mlx5_ifc_destroy_cq_in_bits { 8264 u8 opcode[0x10]; 8265 u8 uid[0x10]; 8266 8267 u8 reserved_at_20[0x10]; 8268 u8 op_mod[0x10]; 8269 8270 u8 reserved_at_40[0x8]; 8271 u8 cqn[0x18]; 8272 8273 u8 reserved_at_60[0x20]; 8274 }; 8275 8276 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits { 8277 u8 status[0x8]; 8278 u8 reserved_at_8[0x18]; 8279 8280 u8 syndrome[0x20]; 8281 8282 u8 reserved_at_40[0x40]; 8283 }; 8284 8285 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits { 8286 u8 opcode[0x10]; 8287 u8 reserved_at_10[0x10]; 8288 8289 u8 reserved_at_20[0x10]; 8290 u8 op_mod[0x10]; 8291 8292 u8 reserved_at_40[0x20]; 8293 8294 u8 reserved_at_60[0x10]; 8295 u8 vxlan_udp_port[0x10]; 8296 }; 8297 8298 struct mlx5_ifc_delete_l2_table_entry_out_bits { 8299 u8 status[0x8]; 8300 u8 reserved_at_8[0x18]; 8301 8302 u8 syndrome[0x20]; 8303 8304 u8 reserved_at_40[0x40]; 8305 }; 8306 8307 struct mlx5_ifc_delete_l2_table_entry_in_bits { 8308 u8 opcode[0x10]; 8309 u8 reserved_at_10[0x10]; 8310 8311 u8 reserved_at_20[0x10]; 8312 u8 op_mod[0x10]; 8313 8314 u8 reserved_at_40[0x60]; 8315 8316 u8 reserved_at_a0[0x8]; 8317 u8 table_index[0x18]; 8318 8319 u8 reserved_at_c0[0x140]; 8320 }; 8321 8322 struct mlx5_ifc_delete_fte_out_bits { 8323 u8 status[0x8]; 8324 u8 reserved_at_8[0x18]; 8325 8326 u8 syndrome[0x20]; 8327 8328 u8 reserved_at_40[0x40]; 8329 }; 8330 8331 struct mlx5_ifc_delete_fte_in_bits { 8332 u8 opcode[0x10]; 8333 u8 reserved_at_10[0x10]; 8334 8335 u8 reserved_at_20[0x10]; 8336 u8 op_mod[0x10]; 8337 8338 u8 other_vport[0x1]; 8339 u8 reserved_at_41[0xf]; 8340 u8 vport_number[0x10]; 8341 8342 u8 reserved_at_60[0x20]; 8343 8344 u8 table_type[0x8]; 8345 u8 reserved_at_88[0x18]; 8346 8347 u8 reserved_at_a0[0x8]; 8348 u8 table_id[0x18]; 8349 8350 u8 reserved_at_c0[0x40]; 8351 8352 u8 flow_index[0x20]; 8353 8354 u8 reserved_at_120[0xe0]; 8355 }; 8356 8357 struct mlx5_ifc_dealloc_xrcd_out_bits { 8358 u8 status[0x8]; 8359 u8 reserved_at_8[0x18]; 8360 8361 u8 syndrome[0x20]; 8362 8363 u8 reserved_at_40[0x40]; 8364 }; 8365 8366 struct mlx5_ifc_dealloc_xrcd_in_bits { 8367 u8 opcode[0x10]; 8368 u8 uid[0x10]; 8369 8370 u8 reserved_at_20[0x10]; 8371 u8 op_mod[0x10]; 8372 8373 u8 reserved_at_40[0x8]; 8374 u8 xrcd[0x18]; 8375 8376 u8 reserved_at_60[0x20]; 8377 }; 8378 8379 struct mlx5_ifc_dealloc_uar_out_bits { 8380 u8 status[0x8]; 8381 u8 reserved_at_8[0x18]; 8382 8383 u8 syndrome[0x20]; 8384 8385 u8 reserved_at_40[0x40]; 8386 }; 8387 8388 struct mlx5_ifc_dealloc_uar_in_bits { 8389 u8 opcode[0x10]; 8390 u8 uid[0x10]; 8391 8392 u8 reserved_at_20[0x10]; 8393 u8 op_mod[0x10]; 8394 8395 u8 reserved_at_40[0x8]; 8396 u8 uar[0x18]; 8397 8398 u8 reserved_at_60[0x20]; 8399 }; 8400 8401 struct mlx5_ifc_dealloc_transport_domain_out_bits { 8402 u8 status[0x8]; 8403 u8 reserved_at_8[0x18]; 8404 8405 u8 syndrome[0x20]; 8406 8407 u8 reserved_at_40[0x40]; 8408 }; 8409 8410 struct mlx5_ifc_dealloc_transport_domain_in_bits { 8411 u8 opcode[0x10]; 8412 u8 uid[0x10]; 8413 8414 u8 reserved_at_20[0x10]; 8415 u8 op_mod[0x10]; 8416 8417 u8 reserved_at_40[0x8]; 8418 u8 transport_domain[0x18]; 8419 8420 u8 reserved_at_60[0x20]; 8421 }; 8422 8423 struct mlx5_ifc_dealloc_q_counter_out_bits { 8424 u8 status[0x8]; 8425 u8 reserved_at_8[0x18]; 8426 8427 u8 syndrome[0x20]; 8428 8429 u8 reserved_at_40[0x40]; 8430 }; 8431 8432 struct mlx5_ifc_dealloc_q_counter_in_bits { 8433 u8 opcode[0x10]; 8434 u8 reserved_at_10[0x10]; 8435 8436 u8 reserved_at_20[0x10]; 8437 u8 op_mod[0x10]; 8438 8439 u8 reserved_at_40[0x18]; 8440 u8 counter_set_id[0x8]; 8441 8442 u8 reserved_at_60[0x20]; 8443 }; 8444 8445 struct mlx5_ifc_dealloc_pd_out_bits { 8446 u8 status[0x8]; 8447 u8 reserved_at_8[0x18]; 8448 8449 u8 syndrome[0x20]; 8450 8451 u8 reserved_at_40[0x40]; 8452 }; 8453 8454 struct mlx5_ifc_dealloc_pd_in_bits { 8455 u8 opcode[0x10]; 8456 u8 uid[0x10]; 8457 8458 u8 reserved_at_20[0x10]; 8459 u8 op_mod[0x10]; 8460 8461 u8 reserved_at_40[0x8]; 8462 u8 pd[0x18]; 8463 8464 u8 reserved_at_60[0x20]; 8465 }; 8466 8467 struct mlx5_ifc_dealloc_flow_counter_out_bits { 8468 u8 status[0x8]; 8469 u8 reserved_at_8[0x18]; 8470 8471 u8 syndrome[0x20]; 8472 8473 u8 reserved_at_40[0x40]; 8474 }; 8475 8476 struct mlx5_ifc_dealloc_flow_counter_in_bits { 8477 u8 opcode[0x10]; 8478 u8 reserved_at_10[0x10]; 8479 8480 u8 reserved_at_20[0x10]; 8481 u8 op_mod[0x10]; 8482 8483 u8 flow_counter_id[0x20]; 8484 8485 u8 reserved_at_60[0x20]; 8486 }; 8487 8488 struct mlx5_ifc_create_xrq_out_bits { 8489 u8 status[0x8]; 8490 u8 reserved_at_8[0x18]; 8491 8492 u8 syndrome[0x20]; 8493 8494 u8 reserved_at_40[0x8]; 8495 u8 xrqn[0x18]; 8496 8497 u8 reserved_at_60[0x20]; 8498 }; 8499 8500 struct mlx5_ifc_create_xrq_in_bits { 8501 u8 opcode[0x10]; 8502 u8 uid[0x10]; 8503 8504 u8 reserved_at_20[0x10]; 8505 u8 op_mod[0x10]; 8506 8507 u8 reserved_at_40[0x40]; 8508 8509 struct mlx5_ifc_xrqc_bits xrq_context; 8510 }; 8511 8512 struct mlx5_ifc_create_xrc_srq_out_bits { 8513 u8 status[0x8]; 8514 u8 reserved_at_8[0x18]; 8515 8516 u8 syndrome[0x20]; 8517 8518 u8 reserved_at_40[0x8]; 8519 u8 xrc_srqn[0x18]; 8520 8521 u8 reserved_at_60[0x20]; 8522 }; 8523 8524 struct mlx5_ifc_create_xrc_srq_in_bits { 8525 u8 opcode[0x10]; 8526 u8 uid[0x10]; 8527 8528 u8 reserved_at_20[0x10]; 8529 u8 op_mod[0x10]; 8530 8531 u8 reserved_at_40[0x40]; 8532 8533 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 8534 8535 u8 reserved_at_280[0x60]; 8536 8537 u8 xrc_srq_umem_valid[0x1]; 8538 u8 reserved_at_2e1[0x1f]; 8539 8540 u8 reserved_at_300[0x580]; 8541 8542 u8 pas[][0x40]; 8543 }; 8544 8545 struct mlx5_ifc_create_tis_out_bits { 8546 u8 status[0x8]; 8547 u8 reserved_at_8[0x18]; 8548 8549 u8 syndrome[0x20]; 8550 8551 u8 reserved_at_40[0x8]; 8552 u8 tisn[0x18]; 8553 8554 u8 reserved_at_60[0x20]; 8555 }; 8556 8557 struct mlx5_ifc_create_tis_in_bits { 8558 u8 opcode[0x10]; 8559 u8 uid[0x10]; 8560 8561 u8 reserved_at_20[0x10]; 8562 u8 op_mod[0x10]; 8563 8564 u8 reserved_at_40[0xc0]; 8565 8566 struct mlx5_ifc_tisc_bits ctx; 8567 }; 8568 8569 struct mlx5_ifc_create_tir_out_bits { 8570 u8 status[0x8]; 8571 u8 icm_address_63_40[0x18]; 8572 8573 u8 syndrome[0x20]; 8574 8575 u8 icm_address_39_32[0x8]; 8576 u8 tirn[0x18]; 8577 8578 u8 icm_address_31_0[0x20]; 8579 }; 8580 8581 struct mlx5_ifc_create_tir_in_bits { 8582 u8 opcode[0x10]; 8583 u8 uid[0x10]; 8584 8585 u8 reserved_at_20[0x10]; 8586 u8 op_mod[0x10]; 8587 8588 u8 reserved_at_40[0xc0]; 8589 8590 struct mlx5_ifc_tirc_bits ctx; 8591 }; 8592 8593 struct mlx5_ifc_create_srq_out_bits { 8594 u8 status[0x8]; 8595 u8 reserved_at_8[0x18]; 8596 8597 u8 syndrome[0x20]; 8598 8599 u8 reserved_at_40[0x8]; 8600 u8 srqn[0x18]; 8601 8602 u8 reserved_at_60[0x20]; 8603 }; 8604 8605 struct mlx5_ifc_create_srq_in_bits { 8606 u8 opcode[0x10]; 8607 u8 uid[0x10]; 8608 8609 u8 reserved_at_20[0x10]; 8610 u8 op_mod[0x10]; 8611 8612 u8 reserved_at_40[0x40]; 8613 8614 struct mlx5_ifc_srqc_bits srq_context_entry; 8615 8616 u8 reserved_at_280[0x600]; 8617 8618 u8 pas[][0x40]; 8619 }; 8620 8621 struct mlx5_ifc_create_sq_out_bits { 8622 u8 status[0x8]; 8623 u8 reserved_at_8[0x18]; 8624 8625 u8 syndrome[0x20]; 8626 8627 u8 reserved_at_40[0x8]; 8628 u8 sqn[0x18]; 8629 8630 u8 reserved_at_60[0x20]; 8631 }; 8632 8633 struct mlx5_ifc_create_sq_in_bits { 8634 u8 opcode[0x10]; 8635 u8 uid[0x10]; 8636 8637 u8 reserved_at_20[0x10]; 8638 u8 op_mod[0x10]; 8639 8640 u8 reserved_at_40[0xc0]; 8641 8642 struct mlx5_ifc_sqc_bits ctx; 8643 }; 8644 8645 struct mlx5_ifc_create_scheduling_element_out_bits { 8646 u8 status[0x8]; 8647 u8 reserved_at_8[0x18]; 8648 8649 u8 syndrome[0x20]; 8650 8651 u8 reserved_at_40[0x40]; 8652 8653 u8 scheduling_element_id[0x20]; 8654 8655 u8 reserved_at_a0[0x160]; 8656 }; 8657 8658 struct mlx5_ifc_create_scheduling_element_in_bits { 8659 u8 opcode[0x10]; 8660 u8 reserved_at_10[0x10]; 8661 8662 u8 reserved_at_20[0x10]; 8663 u8 op_mod[0x10]; 8664 8665 u8 scheduling_hierarchy[0x8]; 8666 u8 reserved_at_48[0x18]; 8667 8668 u8 reserved_at_60[0xa0]; 8669 8670 struct mlx5_ifc_scheduling_context_bits scheduling_context; 8671 8672 u8 reserved_at_300[0x100]; 8673 }; 8674 8675 struct mlx5_ifc_create_rqt_out_bits { 8676 u8 status[0x8]; 8677 u8 reserved_at_8[0x18]; 8678 8679 u8 syndrome[0x20]; 8680 8681 u8 reserved_at_40[0x8]; 8682 u8 rqtn[0x18]; 8683 8684 u8 reserved_at_60[0x20]; 8685 }; 8686 8687 struct mlx5_ifc_create_rqt_in_bits { 8688 u8 opcode[0x10]; 8689 u8 uid[0x10]; 8690 8691 u8 reserved_at_20[0x10]; 8692 u8 op_mod[0x10]; 8693 8694 u8 reserved_at_40[0xc0]; 8695 8696 struct mlx5_ifc_rqtc_bits rqt_context; 8697 }; 8698 8699 struct mlx5_ifc_create_rq_out_bits { 8700 u8 status[0x8]; 8701 u8 reserved_at_8[0x18]; 8702 8703 u8 syndrome[0x20]; 8704 8705 u8 reserved_at_40[0x8]; 8706 u8 rqn[0x18]; 8707 8708 u8 reserved_at_60[0x20]; 8709 }; 8710 8711 struct mlx5_ifc_create_rq_in_bits { 8712 u8 opcode[0x10]; 8713 u8 uid[0x10]; 8714 8715 u8 reserved_at_20[0x10]; 8716 u8 op_mod[0x10]; 8717 8718 u8 reserved_at_40[0xc0]; 8719 8720 struct mlx5_ifc_rqc_bits ctx; 8721 }; 8722 8723 struct mlx5_ifc_create_rmp_out_bits { 8724 u8 status[0x8]; 8725 u8 reserved_at_8[0x18]; 8726 8727 u8 syndrome[0x20]; 8728 8729 u8 reserved_at_40[0x8]; 8730 u8 rmpn[0x18]; 8731 8732 u8 reserved_at_60[0x20]; 8733 }; 8734 8735 struct mlx5_ifc_create_rmp_in_bits { 8736 u8 opcode[0x10]; 8737 u8 uid[0x10]; 8738 8739 u8 reserved_at_20[0x10]; 8740 u8 op_mod[0x10]; 8741 8742 u8 reserved_at_40[0xc0]; 8743 8744 struct mlx5_ifc_rmpc_bits ctx; 8745 }; 8746 8747 struct mlx5_ifc_create_qp_out_bits { 8748 u8 status[0x8]; 8749 u8 reserved_at_8[0x18]; 8750 8751 u8 syndrome[0x20]; 8752 8753 u8 reserved_at_40[0x8]; 8754 u8 qpn[0x18]; 8755 8756 u8 ece[0x20]; 8757 }; 8758 8759 struct mlx5_ifc_create_qp_in_bits { 8760 u8 opcode[0x10]; 8761 u8 uid[0x10]; 8762 8763 u8 reserved_at_20[0x10]; 8764 u8 op_mod[0x10]; 8765 8766 u8 qpc_ext[0x1]; 8767 u8 reserved_at_41[0x7]; 8768 u8 input_qpn[0x18]; 8769 8770 u8 reserved_at_60[0x20]; 8771 u8 opt_param_mask[0x20]; 8772 8773 u8 ece[0x20]; 8774 8775 struct mlx5_ifc_qpc_bits qpc; 8776 8777 u8 reserved_at_800[0x60]; 8778 8779 u8 wq_umem_valid[0x1]; 8780 u8 reserved_at_861[0x1f]; 8781 8782 u8 pas[][0x40]; 8783 }; 8784 8785 struct mlx5_ifc_create_psv_out_bits { 8786 u8 status[0x8]; 8787 u8 reserved_at_8[0x18]; 8788 8789 u8 syndrome[0x20]; 8790 8791 u8 reserved_at_40[0x40]; 8792 8793 u8 reserved_at_80[0x8]; 8794 u8 psv0_index[0x18]; 8795 8796 u8 reserved_at_a0[0x8]; 8797 u8 psv1_index[0x18]; 8798 8799 u8 reserved_at_c0[0x8]; 8800 u8 psv2_index[0x18]; 8801 8802 u8 reserved_at_e0[0x8]; 8803 u8 psv3_index[0x18]; 8804 }; 8805 8806 struct mlx5_ifc_create_psv_in_bits { 8807 u8 opcode[0x10]; 8808 u8 reserved_at_10[0x10]; 8809 8810 u8 reserved_at_20[0x10]; 8811 u8 op_mod[0x10]; 8812 8813 u8 num_psv[0x4]; 8814 u8 reserved_at_44[0x4]; 8815 u8 pd[0x18]; 8816 8817 u8 reserved_at_60[0x20]; 8818 }; 8819 8820 struct mlx5_ifc_create_mkey_out_bits { 8821 u8 status[0x8]; 8822 u8 reserved_at_8[0x18]; 8823 8824 u8 syndrome[0x20]; 8825 8826 u8 reserved_at_40[0x8]; 8827 u8 mkey_index[0x18]; 8828 8829 u8 reserved_at_60[0x20]; 8830 }; 8831 8832 struct mlx5_ifc_create_mkey_in_bits { 8833 u8 opcode[0x10]; 8834 u8 uid[0x10]; 8835 8836 u8 reserved_at_20[0x10]; 8837 u8 op_mod[0x10]; 8838 8839 u8 reserved_at_40[0x20]; 8840 8841 u8 pg_access[0x1]; 8842 u8 mkey_umem_valid[0x1]; 8843 u8 reserved_at_62[0x1e]; 8844 8845 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 8846 8847 u8 reserved_at_280[0x80]; 8848 8849 u8 translations_octword_actual_size[0x20]; 8850 8851 u8 reserved_at_320[0x560]; 8852 8853 u8 klm_pas_mtt[][0x20]; 8854 }; 8855 8856 enum { 8857 MLX5_FLOW_TABLE_TYPE_NIC_RX = 0x0, 8858 MLX5_FLOW_TABLE_TYPE_NIC_TX = 0x1, 8859 MLX5_FLOW_TABLE_TYPE_ESW_EGRESS_ACL = 0x2, 8860 MLX5_FLOW_TABLE_TYPE_ESW_INGRESS_ACL = 0x3, 8861 MLX5_FLOW_TABLE_TYPE_FDB = 0X4, 8862 MLX5_FLOW_TABLE_TYPE_SNIFFER_RX = 0X5, 8863 MLX5_FLOW_TABLE_TYPE_SNIFFER_TX = 0X6, 8864 }; 8865 8866 struct mlx5_ifc_create_flow_table_out_bits { 8867 u8 status[0x8]; 8868 u8 icm_address_63_40[0x18]; 8869 8870 u8 syndrome[0x20]; 8871 8872 u8 icm_address_39_32[0x8]; 8873 u8 table_id[0x18]; 8874 8875 u8 icm_address_31_0[0x20]; 8876 }; 8877 8878 struct mlx5_ifc_create_flow_table_in_bits { 8879 u8 opcode[0x10]; 8880 u8 uid[0x10]; 8881 8882 u8 reserved_at_20[0x10]; 8883 u8 op_mod[0x10]; 8884 8885 u8 other_vport[0x1]; 8886 u8 reserved_at_41[0xf]; 8887 u8 vport_number[0x10]; 8888 8889 u8 reserved_at_60[0x20]; 8890 8891 u8 table_type[0x8]; 8892 u8 reserved_at_88[0x18]; 8893 8894 u8 reserved_at_a0[0x20]; 8895 8896 struct mlx5_ifc_flow_table_context_bits flow_table_context; 8897 }; 8898 8899 struct mlx5_ifc_create_flow_group_out_bits { 8900 u8 status[0x8]; 8901 u8 reserved_at_8[0x18]; 8902 8903 u8 syndrome[0x20]; 8904 8905 u8 reserved_at_40[0x8]; 8906 u8 group_id[0x18]; 8907 8908 u8 reserved_at_60[0x20]; 8909 }; 8910 8911 enum { 8912 MLX5_CREATE_FLOW_GROUP_IN_GROUP_TYPE_TCAM_SUBTABLE = 0x0, 8913 MLX5_CREATE_FLOW_GROUP_IN_GROUP_TYPE_HASH_SPLIT = 0x1, 8914 }; 8915 8916 enum { 8917 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 8918 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 8919 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 8920 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3, 8921 }; 8922 8923 struct mlx5_ifc_create_flow_group_in_bits { 8924 u8 opcode[0x10]; 8925 u8 reserved_at_10[0x10]; 8926 8927 u8 reserved_at_20[0x10]; 8928 u8 op_mod[0x10]; 8929 8930 u8 other_vport[0x1]; 8931 u8 reserved_at_41[0xf]; 8932 u8 vport_number[0x10]; 8933 8934 u8 reserved_at_60[0x20]; 8935 8936 u8 table_type[0x8]; 8937 u8 reserved_at_88[0x4]; 8938 u8 group_type[0x4]; 8939 u8 reserved_at_90[0x10]; 8940 8941 u8 reserved_at_a0[0x8]; 8942 u8 table_id[0x18]; 8943 8944 u8 source_eswitch_owner_vhca_id_valid[0x1]; 8945 8946 u8 reserved_at_c1[0x1f]; 8947 8948 u8 start_flow_index[0x20]; 8949 8950 u8 reserved_at_100[0x20]; 8951 8952 u8 end_flow_index[0x20]; 8953 8954 u8 reserved_at_140[0x10]; 8955 u8 match_definer_id[0x10]; 8956 8957 u8 reserved_at_160[0x80]; 8958 8959 u8 reserved_at_1e0[0x18]; 8960 u8 match_criteria_enable[0x8]; 8961 8962 struct mlx5_ifc_fte_match_param_bits match_criteria; 8963 8964 u8 reserved_at_1200[0xe00]; 8965 }; 8966 8967 struct mlx5_ifc_create_eq_out_bits { 8968 u8 status[0x8]; 8969 u8 reserved_at_8[0x18]; 8970 8971 u8 syndrome[0x20]; 8972 8973 u8 reserved_at_40[0x18]; 8974 u8 eq_number[0x8]; 8975 8976 u8 reserved_at_60[0x20]; 8977 }; 8978 8979 struct mlx5_ifc_create_eq_in_bits { 8980 u8 opcode[0x10]; 8981 u8 uid[0x10]; 8982 8983 u8 reserved_at_20[0x10]; 8984 u8 op_mod[0x10]; 8985 8986 u8 reserved_at_40[0x40]; 8987 8988 struct mlx5_ifc_eqc_bits eq_context_entry; 8989 8990 u8 reserved_at_280[0x40]; 8991 8992 u8 event_bitmask[4][0x40]; 8993 8994 u8 reserved_at_3c0[0x4c0]; 8995 8996 u8 pas[][0x40]; 8997 }; 8998 8999 struct mlx5_ifc_create_dct_out_bits { 9000 u8 status[0x8]; 9001 u8 reserved_at_8[0x18]; 9002 9003 u8 syndrome[0x20]; 9004 9005 u8 reserved_at_40[0x8]; 9006 u8 dctn[0x18]; 9007 9008 u8 ece[0x20]; 9009 }; 9010 9011 struct mlx5_ifc_create_dct_in_bits { 9012 u8 opcode[0x10]; 9013 u8 uid[0x10]; 9014 9015 u8 reserved_at_20[0x10]; 9016 u8 op_mod[0x10]; 9017 9018 u8 reserved_at_40[0x40]; 9019 9020 struct mlx5_ifc_dctc_bits dct_context_entry; 9021 9022 u8 reserved_at_280[0x180]; 9023 }; 9024 9025 struct mlx5_ifc_create_cq_out_bits { 9026 u8 status[0x8]; 9027 u8 reserved_at_8[0x18]; 9028 9029 u8 syndrome[0x20]; 9030 9031 u8 reserved_at_40[0x8]; 9032 u8 cqn[0x18]; 9033 9034 u8 reserved_at_60[0x20]; 9035 }; 9036 9037 struct mlx5_ifc_create_cq_in_bits { 9038 u8 opcode[0x10]; 9039 u8 uid[0x10]; 9040 9041 u8 reserved_at_20[0x10]; 9042 u8 op_mod[0x10]; 9043 9044 u8 reserved_at_40[0x40]; 9045 9046 struct mlx5_ifc_cqc_bits cq_context; 9047 9048 u8 reserved_at_280[0x60]; 9049 9050 u8 cq_umem_valid[0x1]; 9051 u8 reserved_at_2e1[0x59f]; 9052 9053 u8 pas[][0x40]; 9054 }; 9055 9056 struct mlx5_ifc_config_int_moderation_out_bits { 9057 u8 status[0x8]; 9058 u8 reserved_at_8[0x18]; 9059 9060 u8 syndrome[0x20]; 9061 9062 u8 reserved_at_40[0x4]; 9063 u8 min_delay[0xc]; 9064 u8 int_vector[0x10]; 9065 9066 u8 reserved_at_60[0x20]; 9067 }; 9068 9069 enum { 9070 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0, 9071 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1, 9072 }; 9073 9074 struct mlx5_ifc_config_int_moderation_in_bits { 9075 u8 opcode[0x10]; 9076 u8 reserved_at_10[0x10]; 9077 9078 u8 reserved_at_20[0x10]; 9079 u8 op_mod[0x10]; 9080 9081 u8 reserved_at_40[0x4]; 9082 u8 min_delay[0xc]; 9083 u8 int_vector[0x10]; 9084 9085 u8 reserved_at_60[0x20]; 9086 }; 9087 9088 struct mlx5_ifc_attach_to_mcg_out_bits { 9089 u8 status[0x8]; 9090 u8 reserved_at_8[0x18]; 9091 9092 u8 syndrome[0x20]; 9093 9094 u8 reserved_at_40[0x40]; 9095 }; 9096 9097 struct mlx5_ifc_attach_to_mcg_in_bits { 9098 u8 opcode[0x10]; 9099 u8 uid[0x10]; 9100 9101 u8 reserved_at_20[0x10]; 9102 u8 op_mod[0x10]; 9103 9104 u8 reserved_at_40[0x8]; 9105 u8 qpn[0x18]; 9106 9107 u8 reserved_at_60[0x20]; 9108 9109 u8 multicast_gid[16][0x8]; 9110 }; 9111 9112 struct mlx5_ifc_arm_xrq_out_bits { 9113 u8 status[0x8]; 9114 u8 reserved_at_8[0x18]; 9115 9116 u8 syndrome[0x20]; 9117 9118 u8 reserved_at_40[0x40]; 9119 }; 9120 9121 struct mlx5_ifc_arm_xrq_in_bits { 9122 u8 opcode[0x10]; 9123 u8 reserved_at_10[0x10]; 9124 9125 u8 reserved_at_20[0x10]; 9126 u8 op_mod[0x10]; 9127 9128 u8 reserved_at_40[0x8]; 9129 u8 xrqn[0x18]; 9130 9131 u8 reserved_at_60[0x10]; 9132 u8 lwm[0x10]; 9133 }; 9134 9135 struct mlx5_ifc_arm_xrc_srq_out_bits { 9136 u8 status[0x8]; 9137 u8 reserved_at_8[0x18]; 9138 9139 u8 syndrome[0x20]; 9140 9141 u8 reserved_at_40[0x40]; 9142 }; 9143 9144 enum { 9145 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1, 9146 }; 9147 9148 struct mlx5_ifc_arm_xrc_srq_in_bits { 9149 u8 opcode[0x10]; 9150 u8 uid[0x10]; 9151 9152 u8 reserved_at_20[0x10]; 9153 u8 op_mod[0x10]; 9154 9155 u8 reserved_at_40[0x8]; 9156 u8 xrc_srqn[0x18]; 9157 9158 u8 reserved_at_60[0x10]; 9159 u8 lwm[0x10]; 9160 }; 9161 9162 struct mlx5_ifc_arm_rq_out_bits { 9163 u8 status[0x8]; 9164 u8 reserved_at_8[0x18]; 9165 9166 u8 syndrome[0x20]; 9167 9168 u8 reserved_at_40[0x40]; 9169 }; 9170 9171 enum { 9172 MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1, 9173 MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2, 9174 }; 9175 9176 struct mlx5_ifc_arm_rq_in_bits { 9177 u8 opcode[0x10]; 9178 u8 uid[0x10]; 9179 9180 u8 reserved_at_20[0x10]; 9181 u8 op_mod[0x10]; 9182 9183 u8 reserved_at_40[0x8]; 9184 u8 srq_number[0x18]; 9185 9186 u8 reserved_at_60[0x10]; 9187 u8 lwm[0x10]; 9188 }; 9189 9190 struct mlx5_ifc_arm_dct_out_bits { 9191 u8 status[0x8]; 9192 u8 reserved_at_8[0x18]; 9193 9194 u8 syndrome[0x20]; 9195 9196 u8 reserved_at_40[0x40]; 9197 }; 9198 9199 struct mlx5_ifc_arm_dct_in_bits { 9200 u8 opcode[0x10]; 9201 u8 reserved_at_10[0x10]; 9202 9203 u8 reserved_at_20[0x10]; 9204 u8 op_mod[0x10]; 9205 9206 u8 reserved_at_40[0x8]; 9207 u8 dct_number[0x18]; 9208 9209 u8 reserved_at_60[0x20]; 9210 }; 9211 9212 struct mlx5_ifc_alloc_xrcd_out_bits { 9213 u8 status[0x8]; 9214 u8 reserved_at_8[0x18]; 9215 9216 u8 syndrome[0x20]; 9217 9218 u8 reserved_at_40[0x8]; 9219 u8 xrcd[0x18]; 9220 9221 u8 reserved_at_60[0x20]; 9222 }; 9223 9224 struct mlx5_ifc_alloc_xrcd_in_bits { 9225 u8 opcode[0x10]; 9226 u8 uid[0x10]; 9227 9228 u8 reserved_at_20[0x10]; 9229 u8 op_mod[0x10]; 9230 9231 u8 reserved_at_40[0x40]; 9232 }; 9233 9234 struct mlx5_ifc_alloc_uar_out_bits { 9235 u8 status[0x8]; 9236 u8 reserved_at_8[0x18]; 9237 9238 u8 syndrome[0x20]; 9239 9240 u8 reserved_at_40[0x8]; 9241 u8 uar[0x18]; 9242 9243 u8 reserved_at_60[0x20]; 9244 }; 9245 9246 struct mlx5_ifc_alloc_uar_in_bits { 9247 u8 opcode[0x10]; 9248 u8 uid[0x10]; 9249 9250 u8 reserved_at_20[0x10]; 9251 u8 op_mod[0x10]; 9252 9253 u8 reserved_at_40[0x40]; 9254 }; 9255 9256 struct mlx5_ifc_alloc_transport_domain_out_bits { 9257 u8 status[0x8]; 9258 u8 reserved_at_8[0x18]; 9259 9260 u8 syndrome[0x20]; 9261 9262 u8 reserved_at_40[0x8]; 9263 u8 transport_domain[0x18]; 9264 9265 u8 reserved_at_60[0x20]; 9266 }; 9267 9268 struct mlx5_ifc_alloc_transport_domain_in_bits { 9269 u8 opcode[0x10]; 9270 u8 uid[0x10]; 9271 9272 u8 reserved_at_20[0x10]; 9273 u8 op_mod[0x10]; 9274 9275 u8 reserved_at_40[0x40]; 9276 }; 9277 9278 struct mlx5_ifc_alloc_q_counter_out_bits { 9279 u8 status[0x8]; 9280 u8 reserved_at_8[0x18]; 9281 9282 u8 syndrome[0x20]; 9283 9284 u8 reserved_at_40[0x18]; 9285 u8 counter_set_id[0x8]; 9286 9287 u8 reserved_at_60[0x20]; 9288 }; 9289 9290 struct mlx5_ifc_alloc_q_counter_in_bits { 9291 u8 opcode[0x10]; 9292 u8 uid[0x10]; 9293 9294 u8 reserved_at_20[0x10]; 9295 u8 op_mod[0x10]; 9296 9297 u8 reserved_at_40[0x40]; 9298 }; 9299 9300 struct mlx5_ifc_alloc_pd_out_bits { 9301 u8 status[0x8]; 9302 u8 reserved_at_8[0x18]; 9303 9304 u8 syndrome[0x20]; 9305 9306 u8 reserved_at_40[0x8]; 9307 u8 pd[0x18]; 9308 9309 u8 reserved_at_60[0x20]; 9310 }; 9311 9312 struct mlx5_ifc_alloc_pd_in_bits { 9313 u8 opcode[0x10]; 9314 u8 uid[0x10]; 9315 9316 u8 reserved_at_20[0x10]; 9317 u8 op_mod[0x10]; 9318 9319 u8 reserved_at_40[0x40]; 9320 }; 9321 9322 struct mlx5_ifc_alloc_flow_counter_out_bits { 9323 u8 status[0x8]; 9324 u8 reserved_at_8[0x18]; 9325 9326 u8 syndrome[0x20]; 9327 9328 u8 flow_counter_id[0x20]; 9329 9330 u8 reserved_at_60[0x20]; 9331 }; 9332 9333 struct mlx5_ifc_alloc_flow_counter_in_bits { 9334 u8 opcode[0x10]; 9335 u8 reserved_at_10[0x10]; 9336 9337 u8 reserved_at_20[0x10]; 9338 u8 op_mod[0x10]; 9339 9340 u8 reserved_at_40[0x33]; 9341 u8 flow_counter_bulk_log_size[0x5]; 9342 u8 flow_counter_bulk[0x8]; 9343 }; 9344 9345 struct mlx5_ifc_add_vxlan_udp_dport_out_bits { 9346 u8 status[0x8]; 9347 u8 reserved_at_8[0x18]; 9348 9349 u8 syndrome[0x20]; 9350 9351 u8 reserved_at_40[0x40]; 9352 }; 9353 9354 struct mlx5_ifc_add_vxlan_udp_dport_in_bits { 9355 u8 opcode[0x10]; 9356 u8 reserved_at_10[0x10]; 9357 9358 u8 reserved_at_20[0x10]; 9359 u8 op_mod[0x10]; 9360 9361 u8 reserved_at_40[0x20]; 9362 9363 u8 reserved_at_60[0x10]; 9364 u8 vxlan_udp_port[0x10]; 9365 }; 9366 9367 struct mlx5_ifc_set_pp_rate_limit_out_bits { 9368 u8 status[0x8]; 9369 u8 reserved_at_8[0x18]; 9370 9371 u8 syndrome[0x20]; 9372 9373 u8 reserved_at_40[0x40]; 9374 }; 9375 9376 struct mlx5_ifc_set_pp_rate_limit_context_bits { 9377 u8 rate_limit[0x20]; 9378 9379 u8 burst_upper_bound[0x20]; 9380 9381 u8 reserved_at_40[0x10]; 9382 u8 typical_packet_size[0x10]; 9383 9384 u8 reserved_at_60[0x120]; 9385 }; 9386 9387 struct mlx5_ifc_set_pp_rate_limit_in_bits { 9388 u8 opcode[0x10]; 9389 u8 uid[0x10]; 9390 9391 u8 reserved_at_20[0x10]; 9392 u8 op_mod[0x10]; 9393 9394 u8 reserved_at_40[0x10]; 9395 u8 rate_limit_index[0x10]; 9396 9397 u8 reserved_at_60[0x20]; 9398 9399 struct mlx5_ifc_set_pp_rate_limit_context_bits ctx; 9400 }; 9401 9402 struct mlx5_ifc_access_register_out_bits { 9403 u8 status[0x8]; 9404 u8 reserved_at_8[0x18]; 9405 9406 u8 syndrome[0x20]; 9407 9408 u8 reserved_at_40[0x40]; 9409 9410 u8 register_data[][0x20]; 9411 }; 9412 9413 enum { 9414 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0, 9415 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1, 9416 }; 9417 9418 struct mlx5_ifc_access_register_in_bits { 9419 u8 opcode[0x10]; 9420 u8 reserved_at_10[0x10]; 9421 9422 u8 reserved_at_20[0x10]; 9423 u8 op_mod[0x10]; 9424 9425 u8 reserved_at_40[0x10]; 9426 u8 register_id[0x10]; 9427 9428 u8 argument[0x20]; 9429 9430 u8 register_data[][0x20]; 9431 }; 9432 9433 struct mlx5_ifc_sltp_reg_bits { 9434 u8 status[0x4]; 9435 u8 version[0x4]; 9436 u8 local_port[0x8]; 9437 u8 pnat[0x2]; 9438 u8 reserved_at_12[0x2]; 9439 u8 lane[0x4]; 9440 u8 reserved_at_18[0x8]; 9441 9442 u8 reserved_at_20[0x20]; 9443 9444 u8 reserved_at_40[0x7]; 9445 u8 polarity[0x1]; 9446 u8 ob_tap0[0x8]; 9447 u8 ob_tap1[0x8]; 9448 u8 ob_tap2[0x8]; 9449 9450 u8 reserved_at_60[0xc]; 9451 u8 ob_preemp_mode[0x4]; 9452 u8 ob_reg[0x8]; 9453 u8 ob_bias[0x8]; 9454 9455 u8 reserved_at_80[0x20]; 9456 }; 9457 9458 struct mlx5_ifc_slrg_reg_bits { 9459 u8 status[0x4]; 9460 u8 version[0x4]; 9461 u8 local_port[0x8]; 9462 u8 pnat[0x2]; 9463 u8 reserved_at_12[0x2]; 9464 u8 lane[0x4]; 9465 u8 reserved_at_18[0x8]; 9466 9467 u8 time_to_link_up[0x10]; 9468 u8 reserved_at_30[0xc]; 9469 u8 grade_lane_speed[0x4]; 9470 9471 u8 grade_version[0x8]; 9472 u8 grade[0x18]; 9473 9474 u8 reserved_at_60[0x4]; 9475 u8 height_grade_type[0x4]; 9476 u8 height_grade[0x18]; 9477 9478 u8 height_dz[0x10]; 9479 u8 height_dv[0x10]; 9480 9481 u8 reserved_at_a0[0x10]; 9482 u8 height_sigma[0x10]; 9483 9484 u8 reserved_at_c0[0x20]; 9485 9486 u8 reserved_at_e0[0x4]; 9487 u8 phase_grade_type[0x4]; 9488 u8 phase_grade[0x18]; 9489 9490 u8 reserved_at_100[0x8]; 9491 u8 phase_eo_pos[0x8]; 9492 u8 reserved_at_110[0x8]; 9493 u8 phase_eo_neg[0x8]; 9494 9495 u8 ffe_set_tested[0x10]; 9496 u8 test_errors_per_lane[0x10]; 9497 }; 9498 9499 struct mlx5_ifc_pvlc_reg_bits { 9500 u8 reserved_at_0[0x8]; 9501 u8 local_port[0x8]; 9502 u8 reserved_at_10[0x10]; 9503 9504 u8 reserved_at_20[0x1c]; 9505 u8 vl_hw_cap[0x4]; 9506 9507 u8 reserved_at_40[0x1c]; 9508 u8 vl_admin[0x4]; 9509 9510 u8 reserved_at_60[0x1c]; 9511 u8 vl_operational[0x4]; 9512 }; 9513 9514 struct mlx5_ifc_pude_reg_bits { 9515 u8 swid[0x8]; 9516 u8 local_port[0x8]; 9517 u8 reserved_at_10[0x4]; 9518 u8 admin_status[0x4]; 9519 u8 reserved_at_18[0x4]; 9520 u8 oper_status[0x4]; 9521 9522 u8 reserved_at_20[0x60]; 9523 }; 9524 9525 struct mlx5_ifc_ptys_reg_bits { 9526 u8 reserved_at_0[0x1]; 9527 u8 an_disable_admin[0x1]; 9528 u8 an_disable_cap[0x1]; 9529 u8 reserved_at_3[0x5]; 9530 u8 local_port[0x8]; 9531 u8 reserved_at_10[0xd]; 9532 u8 proto_mask[0x3]; 9533 9534 u8 an_status[0x4]; 9535 u8 reserved_at_24[0xc]; 9536 u8 data_rate_oper[0x10]; 9537 9538 u8 ext_eth_proto_capability[0x20]; 9539 9540 u8 eth_proto_capability[0x20]; 9541 9542 u8 ib_link_width_capability[0x10]; 9543 u8 ib_proto_capability[0x10]; 9544 9545 u8 ext_eth_proto_admin[0x20]; 9546 9547 u8 eth_proto_admin[0x20]; 9548 9549 u8 ib_link_width_admin[0x10]; 9550 u8 ib_proto_admin[0x10]; 9551 9552 u8 ext_eth_proto_oper[0x20]; 9553 9554 u8 eth_proto_oper[0x20]; 9555 9556 u8 ib_link_width_oper[0x10]; 9557 u8 ib_proto_oper[0x10]; 9558 9559 u8 reserved_at_160[0x1c]; 9560 u8 connector_type[0x4]; 9561 9562 u8 eth_proto_lp_advertise[0x20]; 9563 9564 u8 reserved_at_1a0[0x60]; 9565 }; 9566 9567 struct mlx5_ifc_mlcr_reg_bits { 9568 u8 reserved_at_0[0x8]; 9569 u8 local_port[0x8]; 9570 u8 reserved_at_10[0x20]; 9571 9572 u8 beacon_duration[0x10]; 9573 u8 reserved_at_40[0x10]; 9574 9575 u8 beacon_remain[0x10]; 9576 }; 9577 9578 struct mlx5_ifc_ptas_reg_bits { 9579 u8 reserved_at_0[0x20]; 9580 9581 u8 algorithm_options[0x10]; 9582 u8 reserved_at_30[0x4]; 9583 u8 repetitions_mode[0x4]; 9584 u8 num_of_repetitions[0x8]; 9585 9586 u8 grade_version[0x8]; 9587 u8 height_grade_type[0x4]; 9588 u8 phase_grade_type[0x4]; 9589 u8 height_grade_weight[0x8]; 9590 u8 phase_grade_weight[0x8]; 9591 9592 u8 gisim_measure_bits[0x10]; 9593 u8 adaptive_tap_measure_bits[0x10]; 9594 9595 u8 ber_bath_high_error_threshold[0x10]; 9596 u8 ber_bath_mid_error_threshold[0x10]; 9597 9598 u8 ber_bath_low_error_threshold[0x10]; 9599 u8 one_ratio_high_threshold[0x10]; 9600 9601 u8 one_ratio_high_mid_threshold[0x10]; 9602 u8 one_ratio_low_mid_threshold[0x10]; 9603 9604 u8 one_ratio_low_threshold[0x10]; 9605 u8 ndeo_error_threshold[0x10]; 9606 9607 u8 mixer_offset_step_size[0x10]; 9608 u8 reserved_at_110[0x8]; 9609 u8 mix90_phase_for_voltage_bath[0x8]; 9610 9611 u8 mixer_offset_start[0x10]; 9612 u8 mixer_offset_end[0x10]; 9613 9614 u8 reserved_at_140[0x15]; 9615 u8 ber_test_time[0xb]; 9616 }; 9617 9618 struct mlx5_ifc_pspa_reg_bits { 9619 u8 swid[0x8]; 9620 u8 local_port[0x8]; 9621 u8 sub_port[0x8]; 9622 u8 reserved_at_18[0x8]; 9623 9624 u8 reserved_at_20[0x20]; 9625 }; 9626 9627 struct mlx5_ifc_pqdr_reg_bits { 9628 u8 reserved_at_0[0x8]; 9629 u8 local_port[0x8]; 9630 u8 reserved_at_10[0x5]; 9631 u8 prio[0x3]; 9632 u8 reserved_at_18[0x6]; 9633 u8 mode[0x2]; 9634 9635 u8 reserved_at_20[0x20]; 9636 9637 u8 reserved_at_40[0x10]; 9638 u8 min_threshold[0x10]; 9639 9640 u8 reserved_at_60[0x10]; 9641 u8 max_threshold[0x10]; 9642 9643 u8 reserved_at_80[0x10]; 9644 u8 mark_probability_denominator[0x10]; 9645 9646 u8 reserved_at_a0[0x60]; 9647 }; 9648 9649 struct mlx5_ifc_ppsc_reg_bits { 9650 u8 reserved_at_0[0x8]; 9651 u8 local_port[0x8]; 9652 u8 reserved_at_10[0x10]; 9653 9654 u8 reserved_at_20[0x60]; 9655 9656 u8 reserved_at_80[0x1c]; 9657 u8 wrps_admin[0x4]; 9658 9659 u8 reserved_at_a0[0x1c]; 9660 u8 wrps_status[0x4]; 9661 9662 u8 reserved_at_c0[0x8]; 9663 u8 up_threshold[0x8]; 9664 u8 reserved_at_d0[0x8]; 9665 u8 down_threshold[0x8]; 9666 9667 u8 reserved_at_e0[0x20]; 9668 9669 u8 reserved_at_100[0x1c]; 9670 u8 srps_admin[0x4]; 9671 9672 u8 reserved_at_120[0x1c]; 9673 u8 srps_status[0x4]; 9674 9675 u8 reserved_at_140[0x40]; 9676 }; 9677 9678 struct mlx5_ifc_pplr_reg_bits { 9679 u8 reserved_at_0[0x8]; 9680 u8 local_port[0x8]; 9681 u8 reserved_at_10[0x10]; 9682 9683 u8 reserved_at_20[0x8]; 9684 u8 lb_cap[0x8]; 9685 u8 reserved_at_30[0x8]; 9686 u8 lb_en[0x8]; 9687 }; 9688 9689 struct mlx5_ifc_pplm_reg_bits { 9690 u8 reserved_at_0[0x8]; 9691 u8 local_port[0x8]; 9692 u8 reserved_at_10[0x10]; 9693 9694 u8 reserved_at_20[0x20]; 9695 9696 u8 port_profile_mode[0x8]; 9697 u8 static_port_profile[0x8]; 9698 u8 active_port_profile[0x8]; 9699 u8 reserved_at_58[0x8]; 9700 9701 u8 retransmission_active[0x8]; 9702 u8 fec_mode_active[0x18]; 9703 9704 u8 rs_fec_correction_bypass_cap[0x4]; 9705 u8 reserved_at_84[0x8]; 9706 u8 fec_override_cap_56g[0x4]; 9707 u8 fec_override_cap_100g[0x4]; 9708 u8 fec_override_cap_50g[0x4]; 9709 u8 fec_override_cap_25g[0x4]; 9710 u8 fec_override_cap_10g_40g[0x4]; 9711 9712 u8 rs_fec_correction_bypass_admin[0x4]; 9713 u8 reserved_at_a4[0x8]; 9714 u8 fec_override_admin_56g[0x4]; 9715 u8 fec_override_admin_100g[0x4]; 9716 u8 fec_override_admin_50g[0x4]; 9717 u8 fec_override_admin_25g[0x4]; 9718 u8 fec_override_admin_10g_40g[0x4]; 9719 9720 u8 fec_override_cap_400g_8x[0x10]; 9721 u8 fec_override_cap_200g_4x[0x10]; 9722 9723 u8 fec_override_cap_100g_2x[0x10]; 9724 u8 fec_override_cap_50g_1x[0x10]; 9725 9726 u8 fec_override_admin_400g_8x[0x10]; 9727 u8 fec_override_admin_200g_4x[0x10]; 9728 9729 u8 fec_override_admin_100g_2x[0x10]; 9730 u8 fec_override_admin_50g_1x[0x10]; 9731 9732 u8 reserved_at_140[0x140]; 9733 }; 9734 9735 struct mlx5_ifc_ppcnt_reg_bits { 9736 u8 swid[0x8]; 9737 u8 local_port[0x8]; 9738 u8 pnat[0x2]; 9739 u8 reserved_at_12[0x8]; 9740 u8 grp[0x6]; 9741 9742 u8 clr[0x1]; 9743 u8 reserved_at_21[0x1c]; 9744 u8 prio_tc[0x3]; 9745 9746 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set; 9747 }; 9748 9749 struct mlx5_ifc_mpein_reg_bits { 9750 u8 reserved_at_0[0x2]; 9751 u8 depth[0x6]; 9752 u8 pcie_index[0x8]; 9753 u8 node[0x8]; 9754 u8 reserved_at_18[0x8]; 9755 9756 u8 capability_mask[0x20]; 9757 9758 u8 reserved_at_40[0x8]; 9759 u8 link_width_enabled[0x8]; 9760 u8 link_speed_enabled[0x10]; 9761 9762 u8 lane0_physical_position[0x8]; 9763 u8 link_width_active[0x8]; 9764 u8 link_speed_active[0x10]; 9765 9766 u8 num_of_pfs[0x10]; 9767 u8 num_of_vfs[0x10]; 9768 9769 u8 bdf0[0x10]; 9770 u8 reserved_at_b0[0x10]; 9771 9772 u8 max_read_request_size[0x4]; 9773 u8 max_payload_size[0x4]; 9774 u8 reserved_at_c8[0x5]; 9775 u8 pwr_status[0x3]; 9776 u8 port_type[0x4]; 9777 u8 reserved_at_d4[0xb]; 9778 u8 lane_reversal[0x1]; 9779 9780 u8 reserved_at_e0[0x14]; 9781 u8 pci_power[0xc]; 9782 9783 u8 reserved_at_100[0x20]; 9784 9785 u8 device_status[0x10]; 9786 u8 port_state[0x8]; 9787 u8 reserved_at_138[0x8]; 9788 9789 u8 reserved_at_140[0x10]; 9790 u8 receiver_detect_result[0x10]; 9791 9792 u8 reserved_at_160[0x20]; 9793 }; 9794 9795 struct mlx5_ifc_mpcnt_reg_bits { 9796 u8 reserved_at_0[0x8]; 9797 u8 pcie_index[0x8]; 9798 u8 reserved_at_10[0xa]; 9799 u8 grp[0x6]; 9800 9801 u8 clr[0x1]; 9802 u8 reserved_at_21[0x1f]; 9803 9804 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set; 9805 }; 9806 9807 struct mlx5_ifc_ppad_reg_bits { 9808 u8 reserved_at_0[0x3]; 9809 u8 single_mac[0x1]; 9810 u8 reserved_at_4[0x4]; 9811 u8 local_port[0x8]; 9812 u8 mac_47_32[0x10]; 9813 9814 u8 mac_31_0[0x20]; 9815 9816 u8 reserved_at_40[0x40]; 9817 }; 9818 9819 struct mlx5_ifc_pmtu_reg_bits { 9820 u8 reserved_at_0[0x8]; 9821 u8 local_port[0x8]; 9822 u8 reserved_at_10[0x10]; 9823 9824 u8 max_mtu[0x10]; 9825 u8 reserved_at_30[0x10]; 9826 9827 u8 admin_mtu[0x10]; 9828 u8 reserved_at_50[0x10]; 9829 9830 u8 oper_mtu[0x10]; 9831 u8 reserved_at_70[0x10]; 9832 }; 9833 9834 struct mlx5_ifc_pmpr_reg_bits { 9835 u8 reserved_at_0[0x8]; 9836 u8 module[0x8]; 9837 u8 reserved_at_10[0x10]; 9838 9839 u8 reserved_at_20[0x18]; 9840 u8 attenuation_5g[0x8]; 9841 9842 u8 reserved_at_40[0x18]; 9843 u8 attenuation_7g[0x8]; 9844 9845 u8 reserved_at_60[0x18]; 9846 u8 attenuation_12g[0x8]; 9847 }; 9848 9849 struct mlx5_ifc_pmpe_reg_bits { 9850 u8 reserved_at_0[0x8]; 9851 u8 module[0x8]; 9852 u8 reserved_at_10[0xc]; 9853 u8 module_status[0x4]; 9854 9855 u8 reserved_at_20[0x60]; 9856 }; 9857 9858 struct mlx5_ifc_pmpc_reg_bits { 9859 u8 module_state_updated[32][0x8]; 9860 }; 9861 9862 struct mlx5_ifc_pmlpn_reg_bits { 9863 u8 reserved_at_0[0x4]; 9864 u8 mlpn_status[0x4]; 9865 u8 local_port[0x8]; 9866 u8 reserved_at_10[0x10]; 9867 9868 u8 e[0x1]; 9869 u8 reserved_at_21[0x1f]; 9870 }; 9871 9872 struct mlx5_ifc_pmlp_reg_bits { 9873 u8 rxtx[0x1]; 9874 u8 reserved_at_1[0x7]; 9875 u8 local_port[0x8]; 9876 u8 reserved_at_10[0x8]; 9877 u8 width[0x8]; 9878 9879 u8 lane0_module_mapping[0x20]; 9880 9881 u8 lane1_module_mapping[0x20]; 9882 9883 u8 lane2_module_mapping[0x20]; 9884 9885 u8 lane3_module_mapping[0x20]; 9886 9887 u8 reserved_at_a0[0x160]; 9888 }; 9889 9890 struct mlx5_ifc_pmaos_reg_bits { 9891 u8 reserved_at_0[0x8]; 9892 u8 module[0x8]; 9893 u8 reserved_at_10[0x4]; 9894 u8 admin_status[0x4]; 9895 u8 reserved_at_18[0x4]; 9896 u8 oper_status[0x4]; 9897 9898 u8 ase[0x1]; 9899 u8 ee[0x1]; 9900 u8 reserved_at_22[0x1c]; 9901 u8 e[0x2]; 9902 9903 u8 reserved_at_40[0x40]; 9904 }; 9905 9906 struct mlx5_ifc_plpc_reg_bits { 9907 u8 reserved_at_0[0x4]; 9908 u8 profile_id[0xc]; 9909 u8 reserved_at_10[0x4]; 9910 u8 proto_mask[0x4]; 9911 u8 reserved_at_18[0x8]; 9912 9913 u8 reserved_at_20[0x10]; 9914 u8 lane_speed[0x10]; 9915 9916 u8 reserved_at_40[0x17]; 9917 u8 lpbf[0x1]; 9918 u8 fec_mode_policy[0x8]; 9919 9920 u8 retransmission_capability[0x8]; 9921 u8 fec_mode_capability[0x18]; 9922 9923 u8 retransmission_support_admin[0x8]; 9924 u8 fec_mode_support_admin[0x18]; 9925 9926 u8 retransmission_request_admin[0x8]; 9927 u8 fec_mode_request_admin[0x18]; 9928 9929 u8 reserved_at_c0[0x80]; 9930 }; 9931 9932 struct mlx5_ifc_plib_reg_bits { 9933 u8 reserved_at_0[0x8]; 9934 u8 local_port[0x8]; 9935 u8 reserved_at_10[0x8]; 9936 u8 ib_port[0x8]; 9937 9938 u8 reserved_at_20[0x60]; 9939 }; 9940 9941 struct mlx5_ifc_plbf_reg_bits { 9942 u8 reserved_at_0[0x8]; 9943 u8 local_port[0x8]; 9944 u8 reserved_at_10[0xd]; 9945 u8 lbf_mode[0x3]; 9946 9947 u8 reserved_at_20[0x20]; 9948 }; 9949 9950 struct mlx5_ifc_pipg_reg_bits { 9951 u8 reserved_at_0[0x8]; 9952 u8 local_port[0x8]; 9953 u8 reserved_at_10[0x10]; 9954 9955 u8 dic[0x1]; 9956 u8 reserved_at_21[0x19]; 9957 u8 ipg[0x4]; 9958 u8 reserved_at_3e[0x2]; 9959 }; 9960 9961 struct mlx5_ifc_pifr_reg_bits { 9962 u8 reserved_at_0[0x8]; 9963 u8 local_port[0x8]; 9964 u8 reserved_at_10[0x10]; 9965 9966 u8 reserved_at_20[0xe0]; 9967 9968 u8 port_filter[8][0x20]; 9969 9970 u8 port_filter_update_en[8][0x20]; 9971 }; 9972 9973 struct mlx5_ifc_pfcc_reg_bits { 9974 u8 reserved_at_0[0x8]; 9975 u8 local_port[0x8]; 9976 u8 reserved_at_10[0xb]; 9977 u8 ppan_mask_n[0x1]; 9978 u8 minor_stall_mask[0x1]; 9979 u8 critical_stall_mask[0x1]; 9980 u8 reserved_at_1e[0x2]; 9981 9982 u8 ppan[0x4]; 9983 u8 reserved_at_24[0x4]; 9984 u8 prio_mask_tx[0x8]; 9985 u8 reserved_at_30[0x8]; 9986 u8 prio_mask_rx[0x8]; 9987 9988 u8 pptx[0x1]; 9989 u8 aptx[0x1]; 9990 u8 pptx_mask_n[0x1]; 9991 u8 reserved_at_43[0x5]; 9992 u8 pfctx[0x8]; 9993 u8 reserved_at_50[0x10]; 9994 9995 u8 pprx[0x1]; 9996 u8 aprx[0x1]; 9997 u8 pprx_mask_n[0x1]; 9998 u8 reserved_at_63[0x5]; 9999 u8 pfcrx[0x8]; 10000 u8 reserved_at_70[0x10]; 10001 10002 u8 device_stall_minor_watermark[0x10]; 10003 u8 device_stall_critical_watermark[0x10]; 10004 10005 u8 reserved_at_a0[0x60]; 10006 }; 10007 10008 struct mlx5_ifc_pelc_reg_bits { 10009 u8 op[0x4]; 10010 u8 reserved_at_4[0x4]; 10011 u8 local_port[0x8]; 10012 u8 reserved_at_10[0x10]; 10013 10014 u8 op_admin[0x8]; 10015 u8 op_capability[0x8]; 10016 u8 op_request[0x8]; 10017 u8 op_active[0x8]; 10018 10019 u8 admin[0x40]; 10020 10021 u8 capability[0x40]; 10022 10023 u8 request[0x40]; 10024 10025 u8 active[0x40]; 10026 10027 u8 reserved_at_140[0x80]; 10028 }; 10029 10030 struct mlx5_ifc_peir_reg_bits { 10031 u8 reserved_at_0[0x8]; 10032 u8 local_port[0x8]; 10033 u8 reserved_at_10[0x10]; 10034 10035 u8 reserved_at_20[0xc]; 10036 u8 error_count[0x4]; 10037 u8 reserved_at_30[0x10]; 10038 10039 u8 reserved_at_40[0xc]; 10040 u8 lane[0x4]; 10041 u8 reserved_at_50[0x8]; 10042 u8 error_type[0x8]; 10043 }; 10044 10045 struct mlx5_ifc_mpegc_reg_bits { 10046 u8 reserved_at_0[0x30]; 10047 u8 field_select[0x10]; 10048 10049 u8 tx_overflow_sense[0x1]; 10050 u8 mark_cqe[0x1]; 10051 u8 mark_cnp[0x1]; 10052 u8 reserved_at_43[0x1b]; 10053 u8 tx_lossy_overflow_oper[0x2]; 10054 10055 u8 reserved_at_60[0x100]; 10056 }; 10057 10058 enum { 10059 MLX5_MTUTC_FREQ_ADJ_UNITS_PPB = 0x0, 10060 MLX5_MTUTC_FREQ_ADJ_UNITS_SCALED_PPM = 0x1, 10061 }; 10062 10063 enum { 10064 MLX5_MTUTC_OPERATION_SET_TIME_IMMEDIATE = 0x1, 10065 MLX5_MTUTC_OPERATION_ADJUST_TIME = 0x2, 10066 MLX5_MTUTC_OPERATION_ADJUST_FREQ_UTC = 0x3, 10067 }; 10068 10069 struct mlx5_ifc_mtutc_reg_bits { 10070 u8 reserved_at_0[0x5]; 10071 u8 freq_adj_units[0x3]; 10072 u8 reserved_at_8[0x14]; 10073 u8 operation[0x4]; 10074 10075 u8 freq_adjustment[0x20]; 10076 10077 u8 reserved_at_40[0x40]; 10078 10079 u8 utc_sec[0x20]; 10080 10081 u8 reserved_at_a0[0x2]; 10082 u8 utc_nsec[0x1e]; 10083 10084 u8 time_adjustment[0x20]; 10085 }; 10086 10087 struct mlx5_ifc_pcam_enhanced_features_bits { 10088 u8 reserved_at_0[0x68]; 10089 u8 fec_50G_per_lane_in_pplm[0x1]; 10090 u8 reserved_at_69[0x4]; 10091 u8 rx_icrc_encapsulated_counter[0x1]; 10092 u8 reserved_at_6e[0x4]; 10093 u8 ptys_extended_ethernet[0x1]; 10094 u8 reserved_at_73[0x3]; 10095 u8 pfcc_mask[0x1]; 10096 u8 reserved_at_77[0x3]; 10097 u8 per_lane_error_counters[0x1]; 10098 u8 rx_buffer_fullness_counters[0x1]; 10099 u8 ptys_connector_type[0x1]; 10100 u8 reserved_at_7d[0x1]; 10101 u8 ppcnt_discard_group[0x1]; 10102 u8 ppcnt_statistical_group[0x1]; 10103 }; 10104 10105 struct mlx5_ifc_pcam_regs_5000_to_507f_bits { 10106 u8 port_access_reg_cap_mask_127_to_96[0x20]; 10107 u8 port_access_reg_cap_mask_95_to_64[0x20]; 10108 10109 u8 port_access_reg_cap_mask_63_to_36[0x1c]; 10110 u8 pplm[0x1]; 10111 u8 port_access_reg_cap_mask_34_to_32[0x3]; 10112 10113 u8 port_access_reg_cap_mask_31_to_13[0x13]; 10114 u8 pbmc[0x1]; 10115 u8 pptb[0x1]; 10116 u8 port_access_reg_cap_mask_10_to_09[0x2]; 10117 u8 ppcnt[0x1]; 10118 u8 port_access_reg_cap_mask_07_to_00[0x8]; 10119 }; 10120 10121 struct mlx5_ifc_pcam_reg_bits { 10122 u8 reserved_at_0[0x8]; 10123 u8 feature_group[0x8]; 10124 u8 reserved_at_10[0x8]; 10125 u8 access_reg_group[0x8]; 10126 10127 u8 reserved_at_20[0x20]; 10128 10129 union { 10130 struct mlx5_ifc_pcam_regs_5000_to_507f_bits regs_5000_to_507f; 10131 u8 reserved_at_0[0x80]; 10132 } port_access_reg_cap_mask; 10133 10134 u8 reserved_at_c0[0x80]; 10135 10136 union { 10137 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features; 10138 u8 reserved_at_0[0x80]; 10139 } feature_cap_mask; 10140 10141 u8 reserved_at_1c0[0xc0]; 10142 }; 10143 10144 struct mlx5_ifc_mcam_enhanced_features_bits { 10145 u8 reserved_at_0[0x50]; 10146 u8 mtutc_freq_adj_units[0x1]; 10147 u8 mtutc_time_adjustment_extended_range[0x1]; 10148 u8 reserved_at_52[0xb]; 10149 u8 mcia_32dwords[0x1]; 10150 u8 out_pulse_duration_ns[0x1]; 10151 u8 npps_period[0x1]; 10152 u8 reserved_at_60[0xa]; 10153 u8 reset_state[0x1]; 10154 u8 ptpcyc2realtime_modify[0x1]; 10155 u8 reserved_at_6c[0x2]; 10156 u8 pci_status_and_power[0x1]; 10157 u8 reserved_at_6f[0x5]; 10158 u8 mark_tx_action_cnp[0x1]; 10159 u8 mark_tx_action_cqe[0x1]; 10160 u8 dynamic_tx_overflow[0x1]; 10161 u8 reserved_at_77[0x4]; 10162 u8 pcie_outbound_stalled[0x1]; 10163 u8 tx_overflow_buffer_pkt[0x1]; 10164 u8 mtpps_enh_out_per_adj[0x1]; 10165 u8 mtpps_fs[0x1]; 10166 u8 pcie_performance_group[0x1]; 10167 }; 10168 10169 struct mlx5_ifc_mcam_access_reg_bits { 10170 u8 reserved_at_0[0x1c]; 10171 u8 mcda[0x1]; 10172 u8 mcc[0x1]; 10173 u8 mcqi[0x1]; 10174 u8 mcqs[0x1]; 10175 10176 u8 regs_95_to_87[0x9]; 10177 u8 mpegc[0x1]; 10178 u8 mtutc[0x1]; 10179 u8 regs_84_to_68[0x11]; 10180 u8 tracer_registers[0x4]; 10181 10182 u8 regs_63_to_46[0x12]; 10183 u8 mrtc[0x1]; 10184 u8 regs_44_to_32[0xd]; 10185 10186 u8 regs_31_to_0[0x20]; 10187 }; 10188 10189 struct mlx5_ifc_mcam_access_reg_bits1 { 10190 u8 regs_127_to_96[0x20]; 10191 10192 u8 regs_95_to_64[0x20]; 10193 10194 u8 regs_63_to_32[0x20]; 10195 10196 u8 regs_31_to_0[0x20]; 10197 }; 10198 10199 struct mlx5_ifc_mcam_access_reg_bits2 { 10200 u8 regs_127_to_99[0x1d]; 10201 u8 mirc[0x1]; 10202 u8 regs_97_to_96[0x2]; 10203 10204 u8 regs_95_to_64[0x20]; 10205 10206 u8 regs_63_to_32[0x20]; 10207 10208 u8 regs_31_to_0[0x20]; 10209 }; 10210 10211 struct mlx5_ifc_mcam_reg_bits { 10212 u8 reserved_at_0[0x8]; 10213 u8 feature_group[0x8]; 10214 u8 reserved_at_10[0x8]; 10215 u8 access_reg_group[0x8]; 10216 10217 u8 reserved_at_20[0x20]; 10218 10219 union { 10220 struct mlx5_ifc_mcam_access_reg_bits access_regs; 10221 struct mlx5_ifc_mcam_access_reg_bits1 access_regs1; 10222 struct mlx5_ifc_mcam_access_reg_bits2 access_regs2; 10223 u8 reserved_at_0[0x80]; 10224 } mng_access_reg_cap_mask; 10225 10226 u8 reserved_at_c0[0x80]; 10227 10228 union { 10229 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features; 10230 u8 reserved_at_0[0x80]; 10231 } mng_feature_cap_mask; 10232 10233 u8 reserved_at_1c0[0x80]; 10234 }; 10235 10236 struct mlx5_ifc_qcam_access_reg_cap_mask { 10237 u8 qcam_access_reg_cap_mask_127_to_20[0x6C]; 10238 u8 qpdpm[0x1]; 10239 u8 qcam_access_reg_cap_mask_18_to_4[0x0F]; 10240 u8 qdpm[0x1]; 10241 u8 qpts[0x1]; 10242 u8 qcap[0x1]; 10243 u8 qcam_access_reg_cap_mask_0[0x1]; 10244 }; 10245 10246 struct mlx5_ifc_qcam_qos_feature_cap_mask { 10247 u8 qcam_qos_feature_cap_mask_127_to_1[0x7F]; 10248 u8 qpts_trust_both[0x1]; 10249 }; 10250 10251 struct mlx5_ifc_qcam_reg_bits { 10252 u8 reserved_at_0[0x8]; 10253 u8 feature_group[0x8]; 10254 u8 reserved_at_10[0x8]; 10255 u8 access_reg_group[0x8]; 10256 u8 reserved_at_20[0x20]; 10257 10258 union { 10259 struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap; 10260 u8 reserved_at_0[0x80]; 10261 } qos_access_reg_cap_mask; 10262 10263 u8 reserved_at_c0[0x80]; 10264 10265 union { 10266 struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap; 10267 u8 reserved_at_0[0x80]; 10268 } qos_feature_cap_mask; 10269 10270 u8 reserved_at_1c0[0x80]; 10271 }; 10272 10273 struct mlx5_ifc_core_dump_reg_bits { 10274 u8 reserved_at_0[0x18]; 10275 u8 core_dump_type[0x8]; 10276 10277 u8 reserved_at_20[0x30]; 10278 u8 vhca_id[0x10]; 10279 10280 u8 reserved_at_60[0x8]; 10281 u8 qpn[0x18]; 10282 u8 reserved_at_80[0x180]; 10283 }; 10284 10285 struct mlx5_ifc_pcap_reg_bits { 10286 u8 reserved_at_0[0x8]; 10287 u8 local_port[0x8]; 10288 u8 reserved_at_10[0x10]; 10289 10290 u8 port_capability_mask[4][0x20]; 10291 }; 10292 10293 struct mlx5_ifc_paos_reg_bits { 10294 u8 swid[0x8]; 10295 u8 local_port[0x8]; 10296 u8 reserved_at_10[0x4]; 10297 u8 admin_status[0x4]; 10298 u8 reserved_at_18[0x4]; 10299 u8 oper_status[0x4]; 10300 10301 u8 ase[0x1]; 10302 u8 ee[0x1]; 10303 u8 reserved_at_22[0x1c]; 10304 u8 e[0x2]; 10305 10306 u8 reserved_at_40[0x40]; 10307 }; 10308 10309 struct mlx5_ifc_pamp_reg_bits { 10310 u8 reserved_at_0[0x8]; 10311 u8 opamp_group[0x8]; 10312 u8 reserved_at_10[0xc]; 10313 u8 opamp_group_type[0x4]; 10314 10315 u8 start_index[0x10]; 10316 u8 reserved_at_30[0x4]; 10317 u8 num_of_indices[0xc]; 10318 10319 u8 index_data[18][0x10]; 10320 }; 10321 10322 struct mlx5_ifc_pcmr_reg_bits { 10323 u8 reserved_at_0[0x8]; 10324 u8 local_port[0x8]; 10325 u8 reserved_at_10[0x10]; 10326 10327 u8 entropy_force_cap[0x1]; 10328 u8 entropy_calc_cap[0x1]; 10329 u8 entropy_gre_calc_cap[0x1]; 10330 u8 reserved_at_23[0xf]; 10331 u8 rx_ts_over_crc_cap[0x1]; 10332 u8 reserved_at_33[0xb]; 10333 u8 fcs_cap[0x1]; 10334 u8 reserved_at_3f[0x1]; 10335 10336 u8 entropy_force[0x1]; 10337 u8 entropy_calc[0x1]; 10338 u8 entropy_gre_calc[0x1]; 10339 u8 reserved_at_43[0xf]; 10340 u8 rx_ts_over_crc[0x1]; 10341 u8 reserved_at_53[0xb]; 10342 u8 fcs_chk[0x1]; 10343 u8 reserved_at_5f[0x1]; 10344 }; 10345 10346 struct mlx5_ifc_lane_2_module_mapping_bits { 10347 u8 reserved_at_0[0x4]; 10348 u8 rx_lane[0x4]; 10349 u8 reserved_at_8[0x4]; 10350 u8 tx_lane[0x4]; 10351 u8 reserved_at_10[0x8]; 10352 u8 module[0x8]; 10353 }; 10354 10355 struct mlx5_ifc_bufferx_reg_bits { 10356 u8 reserved_at_0[0x6]; 10357 u8 lossy[0x1]; 10358 u8 epsb[0x1]; 10359 u8 reserved_at_8[0x8]; 10360 u8 size[0x10]; 10361 10362 u8 xoff_threshold[0x10]; 10363 u8 xon_threshold[0x10]; 10364 }; 10365 10366 struct mlx5_ifc_set_node_in_bits { 10367 u8 node_description[64][0x8]; 10368 }; 10369 10370 struct mlx5_ifc_register_power_settings_bits { 10371 u8 reserved_at_0[0x18]; 10372 u8 power_settings_level[0x8]; 10373 10374 u8 reserved_at_20[0x60]; 10375 }; 10376 10377 struct mlx5_ifc_register_host_endianness_bits { 10378 u8 he[0x1]; 10379 u8 reserved_at_1[0x1f]; 10380 10381 u8 reserved_at_20[0x60]; 10382 }; 10383 10384 struct mlx5_ifc_umr_pointer_desc_argument_bits { 10385 u8 reserved_at_0[0x20]; 10386 10387 u8 mkey[0x20]; 10388 10389 u8 addressh_63_32[0x20]; 10390 10391 u8 addressl_31_0[0x20]; 10392 }; 10393 10394 struct mlx5_ifc_ud_adrs_vector_bits { 10395 u8 dc_key[0x40]; 10396 10397 u8 ext[0x1]; 10398 u8 reserved_at_41[0x7]; 10399 u8 destination_qp_dct[0x18]; 10400 10401 u8 static_rate[0x4]; 10402 u8 sl_eth_prio[0x4]; 10403 u8 fl[0x1]; 10404 u8 mlid[0x7]; 10405 u8 rlid_udp_sport[0x10]; 10406 10407 u8 reserved_at_80[0x20]; 10408 10409 u8 rmac_47_16[0x20]; 10410 10411 u8 rmac_15_0[0x10]; 10412 u8 tclass[0x8]; 10413 u8 hop_limit[0x8]; 10414 10415 u8 reserved_at_e0[0x1]; 10416 u8 grh[0x1]; 10417 u8 reserved_at_e2[0x2]; 10418 u8 src_addr_index[0x8]; 10419 u8 flow_label[0x14]; 10420 10421 u8 rgid_rip[16][0x8]; 10422 }; 10423 10424 struct mlx5_ifc_pages_req_event_bits { 10425 u8 reserved_at_0[0x10]; 10426 u8 function_id[0x10]; 10427 10428 u8 num_pages[0x20]; 10429 10430 u8 reserved_at_40[0xa0]; 10431 }; 10432 10433 struct mlx5_ifc_eqe_bits { 10434 u8 reserved_at_0[0x8]; 10435 u8 event_type[0x8]; 10436 u8 reserved_at_10[0x8]; 10437 u8 event_sub_type[0x8]; 10438 10439 u8 reserved_at_20[0xe0]; 10440 10441 union mlx5_ifc_event_auto_bits event_data; 10442 10443 u8 reserved_at_1e0[0x10]; 10444 u8 signature[0x8]; 10445 u8 reserved_at_1f8[0x7]; 10446 u8 owner[0x1]; 10447 }; 10448 10449 enum { 10450 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7, 10451 }; 10452 10453 struct mlx5_ifc_cmd_queue_entry_bits { 10454 u8 type[0x8]; 10455 u8 reserved_at_8[0x18]; 10456 10457 u8 input_length[0x20]; 10458 10459 u8 input_mailbox_pointer_63_32[0x20]; 10460 10461 u8 input_mailbox_pointer_31_9[0x17]; 10462 u8 reserved_at_77[0x9]; 10463 10464 u8 command_input_inline_data[16][0x8]; 10465 10466 u8 command_output_inline_data[16][0x8]; 10467 10468 u8 output_mailbox_pointer_63_32[0x20]; 10469 10470 u8 output_mailbox_pointer_31_9[0x17]; 10471 u8 reserved_at_1b7[0x9]; 10472 10473 u8 output_length[0x20]; 10474 10475 u8 token[0x8]; 10476 u8 signature[0x8]; 10477 u8 reserved_at_1f0[0x8]; 10478 u8 status[0x7]; 10479 u8 ownership[0x1]; 10480 }; 10481 10482 struct mlx5_ifc_cmd_out_bits { 10483 u8 status[0x8]; 10484 u8 reserved_at_8[0x18]; 10485 10486 u8 syndrome[0x20]; 10487 10488 u8 command_output[0x20]; 10489 }; 10490 10491 struct mlx5_ifc_cmd_in_bits { 10492 u8 opcode[0x10]; 10493 u8 reserved_at_10[0x10]; 10494 10495 u8 reserved_at_20[0x10]; 10496 u8 op_mod[0x10]; 10497 10498 u8 command[][0x20]; 10499 }; 10500 10501 struct mlx5_ifc_cmd_if_box_bits { 10502 u8 mailbox_data[512][0x8]; 10503 10504 u8 reserved_at_1000[0x180]; 10505 10506 u8 next_pointer_63_32[0x20]; 10507 10508 u8 next_pointer_31_10[0x16]; 10509 u8 reserved_at_11b6[0xa]; 10510 10511 u8 block_number[0x20]; 10512 10513 u8 reserved_at_11e0[0x8]; 10514 u8 token[0x8]; 10515 u8 ctrl_signature[0x8]; 10516 u8 signature[0x8]; 10517 }; 10518 10519 struct mlx5_ifc_mtt_bits { 10520 u8 ptag_63_32[0x20]; 10521 10522 u8 ptag_31_8[0x18]; 10523 u8 reserved_at_38[0x6]; 10524 u8 wr_en[0x1]; 10525 u8 rd_en[0x1]; 10526 }; 10527 10528 struct mlx5_ifc_query_wol_rol_out_bits { 10529 u8 status[0x8]; 10530 u8 reserved_at_8[0x18]; 10531 10532 u8 syndrome[0x20]; 10533 10534 u8 reserved_at_40[0x10]; 10535 u8 rol_mode[0x8]; 10536 u8 wol_mode[0x8]; 10537 10538 u8 reserved_at_60[0x20]; 10539 }; 10540 10541 struct mlx5_ifc_query_wol_rol_in_bits { 10542 u8 opcode[0x10]; 10543 u8 reserved_at_10[0x10]; 10544 10545 u8 reserved_at_20[0x10]; 10546 u8 op_mod[0x10]; 10547 10548 u8 reserved_at_40[0x40]; 10549 }; 10550 10551 struct mlx5_ifc_set_wol_rol_out_bits { 10552 u8 status[0x8]; 10553 u8 reserved_at_8[0x18]; 10554 10555 u8 syndrome[0x20]; 10556 10557 u8 reserved_at_40[0x40]; 10558 }; 10559 10560 struct mlx5_ifc_set_wol_rol_in_bits { 10561 u8 opcode[0x10]; 10562 u8 reserved_at_10[0x10]; 10563 10564 u8 reserved_at_20[0x10]; 10565 u8 op_mod[0x10]; 10566 10567 u8 rol_mode_valid[0x1]; 10568 u8 wol_mode_valid[0x1]; 10569 u8 reserved_at_42[0xe]; 10570 u8 rol_mode[0x8]; 10571 u8 wol_mode[0x8]; 10572 10573 u8 reserved_at_60[0x20]; 10574 }; 10575 10576 enum { 10577 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0, 10578 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1, 10579 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2, 10580 }; 10581 10582 enum { 10583 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0, 10584 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1, 10585 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2, 10586 }; 10587 10588 enum { 10589 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR = 0x1, 10590 MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC = 0x7, 10591 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR = 0x8, 10592 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR = 0x9, 10593 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR = 0xa, 10594 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR = 0xb, 10595 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN = 0xc, 10596 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR = 0xd, 10597 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV = 0xe, 10598 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR = 0xf, 10599 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR = 0x10, 10600 }; 10601 10602 struct mlx5_ifc_initial_seg_bits { 10603 u8 fw_rev_minor[0x10]; 10604 u8 fw_rev_major[0x10]; 10605 10606 u8 cmd_interface_rev[0x10]; 10607 u8 fw_rev_subminor[0x10]; 10608 10609 u8 reserved_at_40[0x40]; 10610 10611 u8 cmdq_phy_addr_63_32[0x20]; 10612 10613 u8 cmdq_phy_addr_31_12[0x14]; 10614 u8 reserved_at_b4[0x2]; 10615 u8 nic_interface[0x2]; 10616 u8 log_cmdq_size[0x4]; 10617 u8 log_cmdq_stride[0x4]; 10618 10619 u8 command_doorbell_vector[0x20]; 10620 10621 u8 reserved_at_e0[0xf00]; 10622 10623 u8 initializing[0x1]; 10624 u8 reserved_at_fe1[0x4]; 10625 u8 nic_interface_supported[0x3]; 10626 u8 embedded_cpu[0x1]; 10627 u8 reserved_at_fe9[0x17]; 10628 10629 struct mlx5_ifc_health_buffer_bits health_buffer; 10630 10631 u8 no_dram_nic_offset[0x20]; 10632 10633 u8 reserved_at_1220[0x6e40]; 10634 10635 u8 reserved_at_8060[0x1f]; 10636 u8 clear_int[0x1]; 10637 10638 u8 health_syndrome[0x8]; 10639 u8 health_counter[0x18]; 10640 10641 u8 reserved_at_80a0[0x17fc0]; 10642 }; 10643 10644 struct mlx5_ifc_mtpps_reg_bits { 10645 u8 reserved_at_0[0xc]; 10646 u8 cap_number_of_pps_pins[0x4]; 10647 u8 reserved_at_10[0x4]; 10648 u8 cap_max_num_of_pps_in_pins[0x4]; 10649 u8 reserved_at_18[0x4]; 10650 u8 cap_max_num_of_pps_out_pins[0x4]; 10651 10652 u8 reserved_at_20[0x13]; 10653 u8 cap_log_min_npps_period[0x5]; 10654 u8 reserved_at_38[0x3]; 10655 u8 cap_log_min_out_pulse_duration_ns[0x5]; 10656 10657 u8 reserved_at_40[0x4]; 10658 u8 cap_pin_3_mode[0x4]; 10659 u8 reserved_at_48[0x4]; 10660 u8 cap_pin_2_mode[0x4]; 10661 u8 reserved_at_50[0x4]; 10662 u8 cap_pin_1_mode[0x4]; 10663 u8 reserved_at_58[0x4]; 10664 u8 cap_pin_0_mode[0x4]; 10665 10666 u8 reserved_at_60[0x4]; 10667 u8 cap_pin_7_mode[0x4]; 10668 u8 reserved_at_68[0x4]; 10669 u8 cap_pin_6_mode[0x4]; 10670 u8 reserved_at_70[0x4]; 10671 u8 cap_pin_5_mode[0x4]; 10672 u8 reserved_at_78[0x4]; 10673 u8 cap_pin_4_mode[0x4]; 10674 10675 u8 field_select[0x20]; 10676 u8 reserved_at_a0[0x20]; 10677 10678 u8 npps_period[0x40]; 10679 10680 u8 enable[0x1]; 10681 u8 reserved_at_101[0xb]; 10682 u8 pattern[0x4]; 10683 u8 reserved_at_110[0x4]; 10684 u8 pin_mode[0x4]; 10685 u8 pin[0x8]; 10686 10687 u8 reserved_at_120[0x2]; 10688 u8 out_pulse_duration_ns[0x1e]; 10689 10690 u8 time_stamp[0x40]; 10691 10692 u8 out_pulse_duration[0x10]; 10693 u8 out_periodic_adjustment[0x10]; 10694 u8 enhanced_out_periodic_adjustment[0x20]; 10695 10696 u8 reserved_at_1c0[0x20]; 10697 }; 10698 10699 struct mlx5_ifc_mtppse_reg_bits { 10700 u8 reserved_at_0[0x18]; 10701 u8 pin[0x8]; 10702 u8 event_arm[0x1]; 10703 u8 reserved_at_21[0x1b]; 10704 u8 event_generation_mode[0x4]; 10705 u8 reserved_at_40[0x40]; 10706 }; 10707 10708 struct mlx5_ifc_mcqs_reg_bits { 10709 u8 last_index_flag[0x1]; 10710 u8 reserved_at_1[0x7]; 10711 u8 fw_device[0x8]; 10712 u8 component_index[0x10]; 10713 10714 u8 reserved_at_20[0x10]; 10715 u8 identifier[0x10]; 10716 10717 u8 reserved_at_40[0x17]; 10718 u8 component_status[0x5]; 10719 u8 component_update_state[0x4]; 10720 10721 u8 last_update_state_changer_type[0x4]; 10722 u8 last_update_state_changer_host_id[0x4]; 10723 u8 reserved_at_68[0x18]; 10724 }; 10725 10726 struct mlx5_ifc_mcqi_cap_bits { 10727 u8 supported_info_bitmask[0x20]; 10728 10729 u8 component_size[0x20]; 10730 10731 u8 max_component_size[0x20]; 10732 10733 u8 log_mcda_word_size[0x4]; 10734 u8 reserved_at_64[0xc]; 10735 u8 mcda_max_write_size[0x10]; 10736 10737 u8 rd_en[0x1]; 10738 u8 reserved_at_81[0x1]; 10739 u8 match_chip_id[0x1]; 10740 u8 match_psid[0x1]; 10741 u8 check_user_timestamp[0x1]; 10742 u8 match_base_guid_mac[0x1]; 10743 u8 reserved_at_86[0x1a]; 10744 }; 10745 10746 struct mlx5_ifc_mcqi_version_bits { 10747 u8 reserved_at_0[0x2]; 10748 u8 build_time_valid[0x1]; 10749 u8 user_defined_time_valid[0x1]; 10750 u8 reserved_at_4[0x14]; 10751 u8 version_string_length[0x8]; 10752 10753 u8 version[0x20]; 10754 10755 u8 build_time[0x40]; 10756 10757 u8 user_defined_time[0x40]; 10758 10759 u8 build_tool_version[0x20]; 10760 10761 u8 reserved_at_e0[0x20]; 10762 10763 u8 version_string[92][0x8]; 10764 }; 10765 10766 struct mlx5_ifc_mcqi_activation_method_bits { 10767 u8 pending_server_ac_power_cycle[0x1]; 10768 u8 pending_server_dc_power_cycle[0x1]; 10769 u8 pending_server_reboot[0x1]; 10770 u8 pending_fw_reset[0x1]; 10771 u8 auto_activate[0x1]; 10772 u8 all_hosts_sync[0x1]; 10773 u8 device_hw_reset[0x1]; 10774 u8 reserved_at_7[0x19]; 10775 }; 10776 10777 union mlx5_ifc_mcqi_reg_data_bits { 10778 struct mlx5_ifc_mcqi_cap_bits mcqi_caps; 10779 struct mlx5_ifc_mcqi_version_bits mcqi_version; 10780 struct mlx5_ifc_mcqi_activation_method_bits mcqi_activation_mathod; 10781 }; 10782 10783 struct mlx5_ifc_mcqi_reg_bits { 10784 u8 read_pending_component[0x1]; 10785 u8 reserved_at_1[0xf]; 10786 u8 component_index[0x10]; 10787 10788 u8 reserved_at_20[0x20]; 10789 10790 u8 reserved_at_40[0x1b]; 10791 u8 info_type[0x5]; 10792 10793 u8 info_size[0x20]; 10794 10795 u8 offset[0x20]; 10796 10797 u8 reserved_at_a0[0x10]; 10798 u8 data_size[0x10]; 10799 10800 union mlx5_ifc_mcqi_reg_data_bits data[]; 10801 }; 10802 10803 struct mlx5_ifc_mcc_reg_bits { 10804 u8 reserved_at_0[0x4]; 10805 u8 time_elapsed_since_last_cmd[0xc]; 10806 u8 reserved_at_10[0x8]; 10807 u8 instruction[0x8]; 10808 10809 u8 reserved_at_20[0x10]; 10810 u8 component_index[0x10]; 10811 10812 u8 reserved_at_40[0x8]; 10813 u8 update_handle[0x18]; 10814 10815 u8 handle_owner_type[0x4]; 10816 u8 handle_owner_host_id[0x4]; 10817 u8 reserved_at_68[0x1]; 10818 u8 control_progress[0x7]; 10819 u8 error_code[0x8]; 10820 u8 reserved_at_78[0x4]; 10821 u8 control_state[0x4]; 10822 10823 u8 component_size[0x20]; 10824 10825 u8 reserved_at_a0[0x60]; 10826 }; 10827 10828 struct mlx5_ifc_mcda_reg_bits { 10829 u8 reserved_at_0[0x8]; 10830 u8 update_handle[0x18]; 10831 10832 u8 offset[0x20]; 10833 10834 u8 reserved_at_40[0x10]; 10835 u8 size[0x10]; 10836 10837 u8 reserved_at_60[0x20]; 10838 10839 u8 data[][0x20]; 10840 }; 10841 10842 enum { 10843 MLX5_MFRL_REG_RESET_STATE_IDLE = 0, 10844 MLX5_MFRL_REG_RESET_STATE_IN_NEGOTIATION = 1, 10845 MLX5_MFRL_REG_RESET_STATE_RESET_IN_PROGRESS = 2, 10846 MLX5_MFRL_REG_RESET_STATE_TIMEOUT = 3, 10847 MLX5_MFRL_REG_RESET_STATE_NACK = 4, 10848 }; 10849 10850 enum { 10851 MLX5_MFRL_REG_RESET_TYPE_FULL_CHIP = BIT(0), 10852 MLX5_MFRL_REG_RESET_TYPE_NET_PORT_ALIVE = BIT(1), 10853 }; 10854 10855 enum { 10856 MLX5_MFRL_REG_RESET_LEVEL0 = BIT(0), 10857 MLX5_MFRL_REG_RESET_LEVEL3 = BIT(3), 10858 MLX5_MFRL_REG_RESET_LEVEL6 = BIT(6), 10859 }; 10860 10861 struct mlx5_ifc_mfrl_reg_bits { 10862 u8 reserved_at_0[0x20]; 10863 10864 u8 reserved_at_20[0x2]; 10865 u8 pci_sync_for_fw_update_start[0x1]; 10866 u8 pci_sync_for_fw_update_resp[0x2]; 10867 u8 rst_type_sel[0x3]; 10868 u8 reserved_at_28[0x4]; 10869 u8 reset_state[0x4]; 10870 u8 reset_type[0x8]; 10871 u8 reset_level[0x8]; 10872 }; 10873 10874 struct mlx5_ifc_mirc_reg_bits { 10875 u8 reserved_at_0[0x18]; 10876 u8 status_code[0x8]; 10877 10878 u8 reserved_at_20[0x20]; 10879 }; 10880 10881 struct mlx5_ifc_pddr_monitor_opcode_bits { 10882 u8 reserved_at_0[0x10]; 10883 u8 monitor_opcode[0x10]; 10884 }; 10885 10886 union mlx5_ifc_pddr_troubleshooting_page_status_opcode_auto_bits { 10887 struct mlx5_ifc_pddr_monitor_opcode_bits pddr_monitor_opcode; 10888 u8 reserved_at_0[0x20]; 10889 }; 10890 10891 enum { 10892 /* Monitor opcodes */ 10893 MLX5_PDDR_REG_TRBLSH_GROUP_OPCODE_MONITOR = 0x0, 10894 }; 10895 10896 struct mlx5_ifc_pddr_troubleshooting_page_bits { 10897 u8 reserved_at_0[0x10]; 10898 u8 group_opcode[0x10]; 10899 10900 union mlx5_ifc_pddr_troubleshooting_page_status_opcode_auto_bits status_opcode; 10901 10902 u8 reserved_at_40[0x20]; 10903 10904 u8 status_message[59][0x20]; 10905 }; 10906 10907 union mlx5_ifc_pddr_reg_page_data_auto_bits { 10908 struct mlx5_ifc_pddr_troubleshooting_page_bits pddr_troubleshooting_page; 10909 u8 reserved_at_0[0x7c0]; 10910 }; 10911 10912 enum { 10913 MLX5_PDDR_REG_PAGE_SELECT_TROUBLESHOOTING_INFO_PAGE = 0x1, 10914 }; 10915 10916 struct mlx5_ifc_pddr_reg_bits { 10917 u8 reserved_at_0[0x8]; 10918 u8 local_port[0x8]; 10919 u8 pnat[0x2]; 10920 u8 reserved_at_12[0xe]; 10921 10922 u8 reserved_at_20[0x18]; 10923 u8 page_select[0x8]; 10924 10925 union mlx5_ifc_pddr_reg_page_data_auto_bits page_data; 10926 }; 10927 10928 struct mlx5_ifc_mrtc_reg_bits { 10929 u8 time_synced[0x1]; 10930 u8 reserved_at_1[0x1f]; 10931 10932 u8 reserved_at_20[0x20]; 10933 10934 u8 time_h[0x20]; 10935 10936 u8 time_l[0x20]; 10937 }; 10938 10939 struct mlx5_ifc_mtmp_reg_bits { 10940 u8 reserved_at_0[0x14]; 10941 u8 sensor_index[0xc]; 10942 10943 u8 reserved_at_20[0x10]; 10944 u8 temperature[0x10]; 10945 10946 u8 mte[0x1]; 10947 u8 mtr[0x1]; 10948 u8 reserved_at_42[0xe]; 10949 u8 max_temperature[0x10]; 10950 10951 u8 tee[0x2]; 10952 u8 reserved_at_62[0xe]; 10953 u8 temp_threshold_hi[0x10]; 10954 10955 u8 reserved_at_80[0x10]; 10956 u8 temp_threshold_lo[0x10]; 10957 10958 u8 reserved_at_a0[0x20]; 10959 10960 u8 sensor_name_hi[0x20]; 10961 u8 sensor_name_lo[0x20]; 10962 }; 10963 10964 union mlx5_ifc_ports_control_registers_document_bits { 10965 struct mlx5_ifc_bufferx_reg_bits bufferx_reg; 10966 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 10967 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 10968 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 10969 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 10970 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 10971 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 10972 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout; 10973 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout; 10974 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping; 10975 struct mlx5_ifc_pamp_reg_bits pamp_reg; 10976 struct mlx5_ifc_paos_reg_bits paos_reg; 10977 struct mlx5_ifc_pcap_reg_bits pcap_reg; 10978 struct mlx5_ifc_pddr_monitor_opcode_bits pddr_monitor_opcode; 10979 struct mlx5_ifc_pddr_reg_bits pddr_reg; 10980 struct mlx5_ifc_pddr_troubleshooting_page_bits pddr_troubleshooting_page; 10981 struct mlx5_ifc_peir_reg_bits peir_reg; 10982 struct mlx5_ifc_pelc_reg_bits pelc_reg; 10983 struct mlx5_ifc_pfcc_reg_bits pfcc_reg; 10984 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 10985 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 10986 struct mlx5_ifc_pifr_reg_bits pifr_reg; 10987 struct mlx5_ifc_pipg_reg_bits pipg_reg; 10988 struct mlx5_ifc_plbf_reg_bits plbf_reg; 10989 struct mlx5_ifc_plib_reg_bits plib_reg; 10990 struct mlx5_ifc_plpc_reg_bits plpc_reg; 10991 struct mlx5_ifc_pmaos_reg_bits pmaos_reg; 10992 struct mlx5_ifc_pmlp_reg_bits pmlp_reg; 10993 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg; 10994 struct mlx5_ifc_pmpc_reg_bits pmpc_reg; 10995 struct mlx5_ifc_pmpe_reg_bits pmpe_reg; 10996 struct mlx5_ifc_pmpr_reg_bits pmpr_reg; 10997 struct mlx5_ifc_pmtu_reg_bits pmtu_reg; 10998 struct mlx5_ifc_ppad_reg_bits ppad_reg; 10999 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg; 11000 struct mlx5_ifc_mpein_reg_bits mpein_reg; 11001 struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg; 11002 struct mlx5_ifc_pplm_reg_bits pplm_reg; 11003 struct mlx5_ifc_pplr_reg_bits pplr_reg; 11004 struct mlx5_ifc_ppsc_reg_bits ppsc_reg; 11005 struct mlx5_ifc_pqdr_reg_bits pqdr_reg; 11006 struct mlx5_ifc_pspa_reg_bits pspa_reg; 11007 struct mlx5_ifc_ptas_reg_bits ptas_reg; 11008 struct mlx5_ifc_ptys_reg_bits ptys_reg; 11009 struct mlx5_ifc_mlcr_reg_bits mlcr_reg; 11010 struct mlx5_ifc_pude_reg_bits pude_reg; 11011 struct mlx5_ifc_pvlc_reg_bits pvlc_reg; 11012 struct mlx5_ifc_slrg_reg_bits slrg_reg; 11013 struct mlx5_ifc_sltp_reg_bits sltp_reg; 11014 struct mlx5_ifc_mtpps_reg_bits mtpps_reg; 11015 struct mlx5_ifc_mtppse_reg_bits mtppse_reg; 11016 struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg; 11017 struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits; 11018 struct mlx5_ifc_fpga_cap_bits fpga_cap_bits; 11019 struct mlx5_ifc_mcqi_reg_bits mcqi_reg; 11020 struct mlx5_ifc_mcc_reg_bits mcc_reg; 11021 struct mlx5_ifc_mcda_reg_bits mcda_reg; 11022 struct mlx5_ifc_mirc_reg_bits mirc_reg; 11023 struct mlx5_ifc_mfrl_reg_bits mfrl_reg; 11024 struct mlx5_ifc_mtutc_reg_bits mtutc_reg; 11025 struct mlx5_ifc_mrtc_reg_bits mrtc_reg; 11026 struct mlx5_ifc_mtmp_reg_bits mtmp_reg; 11027 u8 reserved_at_0[0x60e0]; 11028 }; 11029 11030 union mlx5_ifc_debug_enhancements_document_bits { 11031 struct mlx5_ifc_health_buffer_bits health_buffer; 11032 u8 reserved_at_0[0x200]; 11033 }; 11034 11035 union mlx5_ifc_uplink_pci_interface_document_bits { 11036 struct mlx5_ifc_initial_seg_bits initial_seg; 11037 u8 reserved_at_0[0x20060]; 11038 }; 11039 11040 struct mlx5_ifc_set_flow_table_root_out_bits { 11041 u8 status[0x8]; 11042 u8 reserved_at_8[0x18]; 11043 11044 u8 syndrome[0x20]; 11045 11046 u8 reserved_at_40[0x40]; 11047 }; 11048 11049 struct mlx5_ifc_set_flow_table_root_in_bits { 11050 u8 opcode[0x10]; 11051 u8 reserved_at_10[0x10]; 11052 11053 u8 reserved_at_20[0x10]; 11054 u8 op_mod[0x10]; 11055 11056 u8 other_vport[0x1]; 11057 u8 reserved_at_41[0xf]; 11058 u8 vport_number[0x10]; 11059 11060 u8 reserved_at_60[0x20]; 11061 11062 u8 table_type[0x8]; 11063 u8 reserved_at_88[0x7]; 11064 u8 table_of_other_vport[0x1]; 11065 u8 table_vport_number[0x10]; 11066 11067 u8 reserved_at_a0[0x8]; 11068 u8 table_id[0x18]; 11069 11070 u8 reserved_at_c0[0x8]; 11071 u8 underlay_qpn[0x18]; 11072 u8 table_eswitch_owner_vhca_id_valid[0x1]; 11073 u8 reserved_at_e1[0xf]; 11074 u8 table_eswitch_owner_vhca_id[0x10]; 11075 u8 reserved_at_100[0x100]; 11076 }; 11077 11078 enum { 11079 MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = (1UL << 0), 11080 MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15), 11081 }; 11082 11083 struct mlx5_ifc_modify_flow_table_out_bits { 11084 u8 status[0x8]; 11085 u8 reserved_at_8[0x18]; 11086 11087 u8 syndrome[0x20]; 11088 11089 u8 reserved_at_40[0x40]; 11090 }; 11091 11092 struct mlx5_ifc_modify_flow_table_in_bits { 11093 u8 opcode[0x10]; 11094 u8 reserved_at_10[0x10]; 11095 11096 u8 reserved_at_20[0x10]; 11097 u8 op_mod[0x10]; 11098 11099 u8 other_vport[0x1]; 11100 u8 reserved_at_41[0xf]; 11101 u8 vport_number[0x10]; 11102 11103 u8 reserved_at_60[0x10]; 11104 u8 modify_field_select[0x10]; 11105 11106 u8 table_type[0x8]; 11107 u8 reserved_at_88[0x18]; 11108 11109 u8 reserved_at_a0[0x8]; 11110 u8 table_id[0x18]; 11111 11112 struct mlx5_ifc_flow_table_context_bits flow_table_context; 11113 }; 11114 11115 struct mlx5_ifc_ets_tcn_config_reg_bits { 11116 u8 g[0x1]; 11117 u8 b[0x1]; 11118 u8 r[0x1]; 11119 u8 reserved_at_3[0x9]; 11120 u8 group[0x4]; 11121 u8 reserved_at_10[0x9]; 11122 u8 bw_allocation[0x7]; 11123 11124 u8 reserved_at_20[0xc]; 11125 u8 max_bw_units[0x4]; 11126 u8 reserved_at_30[0x8]; 11127 u8 max_bw_value[0x8]; 11128 }; 11129 11130 struct mlx5_ifc_ets_global_config_reg_bits { 11131 u8 reserved_at_0[0x2]; 11132 u8 r[0x1]; 11133 u8 reserved_at_3[0x1d]; 11134 11135 u8 reserved_at_20[0xc]; 11136 u8 max_bw_units[0x4]; 11137 u8 reserved_at_30[0x8]; 11138 u8 max_bw_value[0x8]; 11139 }; 11140 11141 struct mlx5_ifc_qetc_reg_bits { 11142 u8 reserved_at_0[0x8]; 11143 u8 port_number[0x8]; 11144 u8 reserved_at_10[0x30]; 11145 11146 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8]; 11147 struct mlx5_ifc_ets_global_config_reg_bits global_configuration; 11148 }; 11149 11150 struct mlx5_ifc_qpdpm_dscp_reg_bits { 11151 u8 e[0x1]; 11152 u8 reserved_at_01[0x0b]; 11153 u8 prio[0x04]; 11154 }; 11155 11156 struct mlx5_ifc_qpdpm_reg_bits { 11157 u8 reserved_at_0[0x8]; 11158 u8 local_port[0x8]; 11159 u8 reserved_at_10[0x10]; 11160 struct mlx5_ifc_qpdpm_dscp_reg_bits dscp[64]; 11161 }; 11162 11163 struct mlx5_ifc_qpts_reg_bits { 11164 u8 reserved_at_0[0x8]; 11165 u8 local_port[0x8]; 11166 u8 reserved_at_10[0x2d]; 11167 u8 trust_state[0x3]; 11168 }; 11169 11170 struct mlx5_ifc_pptb_reg_bits { 11171 u8 reserved_at_0[0x2]; 11172 u8 mm[0x2]; 11173 u8 reserved_at_4[0x4]; 11174 u8 local_port[0x8]; 11175 u8 reserved_at_10[0x6]; 11176 u8 cm[0x1]; 11177 u8 um[0x1]; 11178 u8 pm[0x8]; 11179 11180 u8 prio_x_buff[0x20]; 11181 11182 u8 pm_msb[0x8]; 11183 u8 reserved_at_48[0x10]; 11184 u8 ctrl_buff[0x4]; 11185 u8 untagged_buff[0x4]; 11186 }; 11187 11188 struct mlx5_ifc_sbcam_reg_bits { 11189 u8 reserved_at_0[0x8]; 11190 u8 feature_group[0x8]; 11191 u8 reserved_at_10[0x8]; 11192 u8 access_reg_group[0x8]; 11193 11194 u8 reserved_at_20[0x20]; 11195 11196 u8 sb_access_reg_cap_mask[4][0x20]; 11197 11198 u8 reserved_at_c0[0x80]; 11199 11200 u8 sb_feature_cap_mask[4][0x20]; 11201 11202 u8 reserved_at_1c0[0x40]; 11203 11204 u8 cap_total_buffer_size[0x20]; 11205 11206 u8 cap_cell_size[0x10]; 11207 u8 cap_max_pg_buffers[0x8]; 11208 u8 cap_num_pool_supported[0x8]; 11209 11210 u8 reserved_at_240[0x8]; 11211 u8 cap_sbsr_stat_size[0x8]; 11212 u8 cap_max_tclass_data[0x8]; 11213 u8 cap_max_cpu_ingress_tclass_sb[0x8]; 11214 }; 11215 11216 struct mlx5_ifc_pbmc_reg_bits { 11217 u8 reserved_at_0[0x8]; 11218 u8 local_port[0x8]; 11219 u8 reserved_at_10[0x10]; 11220 11221 u8 xoff_timer_value[0x10]; 11222 u8 xoff_refresh[0x10]; 11223 11224 u8 reserved_at_40[0x9]; 11225 u8 fullness_threshold[0x7]; 11226 u8 port_buffer_size[0x10]; 11227 11228 struct mlx5_ifc_bufferx_reg_bits buffer[10]; 11229 11230 u8 reserved_at_2e0[0x80]; 11231 }; 11232 11233 struct mlx5_ifc_sbpr_reg_bits { 11234 u8 desc[0x1]; 11235 u8 snap[0x1]; 11236 u8 reserved_at_2[0x4]; 11237 u8 dir[0x2]; 11238 u8 reserved_at_8[0x14]; 11239 u8 pool[0x4]; 11240 11241 u8 infi_size[0x1]; 11242 u8 reserved_at_21[0x7]; 11243 u8 size[0x18]; 11244 11245 u8 reserved_at_40[0x1c]; 11246 u8 mode[0x4]; 11247 11248 u8 reserved_at_60[0x8]; 11249 u8 buff_occupancy[0x18]; 11250 11251 u8 clr[0x1]; 11252 u8 reserved_at_81[0x7]; 11253 u8 max_buff_occupancy[0x18]; 11254 11255 u8 reserved_at_a0[0x8]; 11256 u8 ext_buff_occupancy[0x18]; 11257 }; 11258 11259 struct mlx5_ifc_sbcm_reg_bits { 11260 u8 desc[0x1]; 11261 u8 snap[0x1]; 11262 u8 reserved_at_2[0x6]; 11263 u8 local_port[0x8]; 11264 u8 pnat[0x2]; 11265 u8 pg_buff[0x6]; 11266 u8 reserved_at_18[0x6]; 11267 u8 dir[0x2]; 11268 11269 u8 reserved_at_20[0x1f]; 11270 u8 exc[0x1]; 11271 11272 u8 reserved_at_40[0x40]; 11273 11274 u8 reserved_at_80[0x8]; 11275 u8 buff_occupancy[0x18]; 11276 11277 u8 clr[0x1]; 11278 u8 reserved_at_a1[0x7]; 11279 u8 max_buff_occupancy[0x18]; 11280 11281 u8 reserved_at_c0[0x8]; 11282 u8 min_buff[0x18]; 11283 11284 u8 infi_max[0x1]; 11285 u8 reserved_at_e1[0x7]; 11286 u8 max_buff[0x18]; 11287 11288 u8 reserved_at_100[0x20]; 11289 11290 u8 reserved_at_120[0x1c]; 11291 u8 pool[0x4]; 11292 }; 11293 11294 struct mlx5_ifc_qtct_reg_bits { 11295 u8 reserved_at_0[0x8]; 11296 u8 port_number[0x8]; 11297 u8 reserved_at_10[0xd]; 11298 u8 prio[0x3]; 11299 11300 u8 reserved_at_20[0x1d]; 11301 u8 tclass[0x3]; 11302 }; 11303 11304 struct mlx5_ifc_mcia_reg_bits { 11305 u8 l[0x1]; 11306 u8 reserved_at_1[0x7]; 11307 u8 module[0x8]; 11308 u8 reserved_at_10[0x8]; 11309 u8 status[0x8]; 11310 11311 u8 i2c_device_address[0x8]; 11312 u8 page_number[0x8]; 11313 u8 device_address[0x10]; 11314 11315 u8 reserved_at_40[0x10]; 11316 u8 size[0x10]; 11317 11318 u8 reserved_at_60[0x20]; 11319 11320 u8 dword_0[0x20]; 11321 u8 dword_1[0x20]; 11322 u8 dword_2[0x20]; 11323 u8 dword_3[0x20]; 11324 u8 dword_4[0x20]; 11325 u8 dword_5[0x20]; 11326 u8 dword_6[0x20]; 11327 u8 dword_7[0x20]; 11328 u8 dword_8[0x20]; 11329 u8 dword_9[0x20]; 11330 u8 dword_10[0x20]; 11331 u8 dword_11[0x20]; 11332 }; 11333 11334 struct mlx5_ifc_dcbx_param_bits { 11335 u8 dcbx_cee_cap[0x1]; 11336 u8 dcbx_ieee_cap[0x1]; 11337 u8 dcbx_standby_cap[0x1]; 11338 u8 reserved_at_3[0x5]; 11339 u8 port_number[0x8]; 11340 u8 reserved_at_10[0xa]; 11341 u8 max_application_table_size[6]; 11342 u8 reserved_at_20[0x15]; 11343 u8 version_oper[0x3]; 11344 u8 reserved_at_38[5]; 11345 u8 version_admin[0x3]; 11346 u8 willing_admin[0x1]; 11347 u8 reserved_at_41[0x3]; 11348 u8 pfc_cap_oper[0x4]; 11349 u8 reserved_at_48[0x4]; 11350 u8 pfc_cap_admin[0x4]; 11351 u8 reserved_at_50[0x4]; 11352 u8 num_of_tc_oper[0x4]; 11353 u8 reserved_at_58[0x4]; 11354 u8 num_of_tc_admin[0x4]; 11355 u8 remote_willing[0x1]; 11356 u8 reserved_at_61[3]; 11357 u8 remote_pfc_cap[4]; 11358 u8 reserved_at_68[0x14]; 11359 u8 remote_num_of_tc[0x4]; 11360 u8 reserved_at_80[0x18]; 11361 u8 error[0x8]; 11362 u8 reserved_at_a0[0x160]; 11363 }; 11364 11365 enum { 11366 MLX5_LAG_PORT_SELECT_MODE_QUEUE_AFFINITY = 0, 11367 MLX5_LAG_PORT_SELECT_MODE_PORT_SELECT_FT = 1, 11368 MLX5_LAG_PORT_SELECT_MODE_PORT_SELECT_MPESW = 2, 11369 }; 11370 11371 struct mlx5_ifc_lagc_bits { 11372 u8 fdb_selection_mode[0x1]; 11373 u8 reserved_at_1[0x14]; 11374 u8 port_select_mode[0x3]; 11375 u8 reserved_at_18[0x5]; 11376 u8 lag_state[0x3]; 11377 11378 u8 reserved_at_20[0xc]; 11379 u8 active_port[0x4]; 11380 u8 reserved_at_30[0x4]; 11381 u8 tx_remap_affinity_2[0x4]; 11382 u8 reserved_at_38[0x4]; 11383 u8 tx_remap_affinity_1[0x4]; 11384 }; 11385 11386 struct mlx5_ifc_create_lag_out_bits { 11387 u8 status[0x8]; 11388 u8 reserved_at_8[0x18]; 11389 11390 u8 syndrome[0x20]; 11391 11392 u8 reserved_at_40[0x40]; 11393 }; 11394 11395 struct mlx5_ifc_create_lag_in_bits { 11396 u8 opcode[0x10]; 11397 u8 reserved_at_10[0x10]; 11398 11399 u8 reserved_at_20[0x10]; 11400 u8 op_mod[0x10]; 11401 11402 struct mlx5_ifc_lagc_bits ctx; 11403 }; 11404 11405 struct mlx5_ifc_modify_lag_out_bits { 11406 u8 status[0x8]; 11407 u8 reserved_at_8[0x18]; 11408 11409 u8 syndrome[0x20]; 11410 11411 u8 reserved_at_40[0x40]; 11412 }; 11413 11414 struct mlx5_ifc_modify_lag_in_bits { 11415 u8 opcode[0x10]; 11416 u8 reserved_at_10[0x10]; 11417 11418 u8 reserved_at_20[0x10]; 11419 u8 op_mod[0x10]; 11420 11421 u8 reserved_at_40[0x20]; 11422 u8 field_select[0x20]; 11423 11424 struct mlx5_ifc_lagc_bits ctx; 11425 }; 11426 11427 struct mlx5_ifc_query_lag_out_bits { 11428 u8 status[0x8]; 11429 u8 reserved_at_8[0x18]; 11430 11431 u8 syndrome[0x20]; 11432 11433 struct mlx5_ifc_lagc_bits ctx; 11434 }; 11435 11436 struct mlx5_ifc_query_lag_in_bits { 11437 u8 opcode[0x10]; 11438 u8 reserved_at_10[0x10]; 11439 11440 u8 reserved_at_20[0x10]; 11441 u8 op_mod[0x10]; 11442 11443 u8 reserved_at_40[0x40]; 11444 }; 11445 11446 struct mlx5_ifc_destroy_lag_out_bits { 11447 u8 status[0x8]; 11448 u8 reserved_at_8[0x18]; 11449 11450 u8 syndrome[0x20]; 11451 11452 u8 reserved_at_40[0x40]; 11453 }; 11454 11455 struct mlx5_ifc_destroy_lag_in_bits { 11456 u8 opcode[0x10]; 11457 u8 reserved_at_10[0x10]; 11458 11459 u8 reserved_at_20[0x10]; 11460 u8 op_mod[0x10]; 11461 11462 u8 reserved_at_40[0x40]; 11463 }; 11464 11465 struct mlx5_ifc_create_vport_lag_out_bits { 11466 u8 status[0x8]; 11467 u8 reserved_at_8[0x18]; 11468 11469 u8 syndrome[0x20]; 11470 11471 u8 reserved_at_40[0x40]; 11472 }; 11473 11474 struct mlx5_ifc_create_vport_lag_in_bits { 11475 u8 opcode[0x10]; 11476 u8 reserved_at_10[0x10]; 11477 11478 u8 reserved_at_20[0x10]; 11479 u8 op_mod[0x10]; 11480 11481 u8 reserved_at_40[0x40]; 11482 }; 11483 11484 struct mlx5_ifc_destroy_vport_lag_out_bits { 11485 u8 status[0x8]; 11486 u8 reserved_at_8[0x18]; 11487 11488 u8 syndrome[0x20]; 11489 11490 u8 reserved_at_40[0x40]; 11491 }; 11492 11493 struct mlx5_ifc_destroy_vport_lag_in_bits { 11494 u8 opcode[0x10]; 11495 u8 reserved_at_10[0x10]; 11496 11497 u8 reserved_at_20[0x10]; 11498 u8 op_mod[0x10]; 11499 11500 u8 reserved_at_40[0x40]; 11501 }; 11502 11503 enum { 11504 MLX5_MODIFY_MEMIC_OP_MOD_ALLOC, 11505 MLX5_MODIFY_MEMIC_OP_MOD_DEALLOC, 11506 }; 11507 11508 struct mlx5_ifc_modify_memic_in_bits { 11509 u8 opcode[0x10]; 11510 u8 uid[0x10]; 11511 11512 u8 reserved_at_20[0x10]; 11513 u8 op_mod[0x10]; 11514 11515 u8 reserved_at_40[0x20]; 11516 11517 u8 reserved_at_60[0x18]; 11518 u8 memic_operation_type[0x8]; 11519 11520 u8 memic_start_addr[0x40]; 11521 11522 u8 reserved_at_c0[0x140]; 11523 }; 11524 11525 struct mlx5_ifc_modify_memic_out_bits { 11526 u8 status[0x8]; 11527 u8 reserved_at_8[0x18]; 11528 11529 u8 syndrome[0x20]; 11530 11531 u8 reserved_at_40[0x40]; 11532 11533 u8 memic_operation_addr[0x40]; 11534 11535 u8 reserved_at_c0[0x140]; 11536 }; 11537 11538 struct mlx5_ifc_alloc_memic_in_bits { 11539 u8 opcode[0x10]; 11540 u8 reserved_at_10[0x10]; 11541 11542 u8 reserved_at_20[0x10]; 11543 u8 op_mod[0x10]; 11544 11545 u8 reserved_at_30[0x20]; 11546 11547 u8 reserved_at_40[0x18]; 11548 u8 log_memic_addr_alignment[0x8]; 11549 11550 u8 range_start_addr[0x40]; 11551 11552 u8 range_size[0x20]; 11553 11554 u8 memic_size[0x20]; 11555 }; 11556 11557 struct mlx5_ifc_alloc_memic_out_bits { 11558 u8 status[0x8]; 11559 u8 reserved_at_8[0x18]; 11560 11561 u8 syndrome[0x20]; 11562 11563 u8 memic_start_addr[0x40]; 11564 }; 11565 11566 struct mlx5_ifc_dealloc_memic_in_bits { 11567 u8 opcode[0x10]; 11568 u8 reserved_at_10[0x10]; 11569 11570 u8 reserved_at_20[0x10]; 11571 u8 op_mod[0x10]; 11572 11573 u8 reserved_at_40[0x40]; 11574 11575 u8 memic_start_addr[0x40]; 11576 11577 u8 memic_size[0x20]; 11578 11579 u8 reserved_at_e0[0x20]; 11580 }; 11581 11582 struct mlx5_ifc_dealloc_memic_out_bits { 11583 u8 status[0x8]; 11584 u8 reserved_at_8[0x18]; 11585 11586 u8 syndrome[0x20]; 11587 11588 u8 reserved_at_40[0x40]; 11589 }; 11590 11591 struct mlx5_ifc_umem_bits { 11592 u8 reserved_at_0[0x80]; 11593 11594 u8 ats[0x1]; 11595 u8 reserved_at_81[0x1a]; 11596 u8 log_page_size[0x5]; 11597 11598 u8 page_offset[0x20]; 11599 11600 u8 num_of_mtt[0x40]; 11601 11602 struct mlx5_ifc_mtt_bits mtt[]; 11603 }; 11604 11605 struct mlx5_ifc_uctx_bits { 11606 u8 cap[0x20]; 11607 11608 u8 reserved_at_20[0x160]; 11609 }; 11610 11611 struct mlx5_ifc_sw_icm_bits { 11612 u8 modify_field_select[0x40]; 11613 11614 u8 reserved_at_40[0x18]; 11615 u8 log_sw_icm_size[0x8]; 11616 11617 u8 reserved_at_60[0x20]; 11618 11619 u8 sw_icm_start_addr[0x40]; 11620 11621 u8 reserved_at_c0[0x140]; 11622 }; 11623 11624 struct mlx5_ifc_geneve_tlv_option_bits { 11625 u8 modify_field_select[0x40]; 11626 11627 u8 reserved_at_40[0x18]; 11628 u8 geneve_option_fte_index[0x8]; 11629 11630 u8 option_class[0x10]; 11631 u8 option_type[0x8]; 11632 u8 reserved_at_78[0x3]; 11633 u8 option_data_length[0x5]; 11634 11635 u8 reserved_at_80[0x180]; 11636 }; 11637 11638 struct mlx5_ifc_create_umem_in_bits { 11639 u8 opcode[0x10]; 11640 u8 uid[0x10]; 11641 11642 u8 reserved_at_20[0x10]; 11643 u8 op_mod[0x10]; 11644 11645 u8 reserved_at_40[0x40]; 11646 11647 struct mlx5_ifc_umem_bits umem; 11648 }; 11649 11650 struct mlx5_ifc_create_umem_out_bits { 11651 u8 status[0x8]; 11652 u8 reserved_at_8[0x18]; 11653 11654 u8 syndrome[0x20]; 11655 11656 u8 reserved_at_40[0x8]; 11657 u8 umem_id[0x18]; 11658 11659 u8 reserved_at_60[0x20]; 11660 }; 11661 11662 struct mlx5_ifc_destroy_umem_in_bits { 11663 u8 opcode[0x10]; 11664 u8 uid[0x10]; 11665 11666 u8 reserved_at_20[0x10]; 11667 u8 op_mod[0x10]; 11668 11669 u8 reserved_at_40[0x8]; 11670 u8 umem_id[0x18]; 11671 11672 u8 reserved_at_60[0x20]; 11673 }; 11674 11675 struct mlx5_ifc_destroy_umem_out_bits { 11676 u8 status[0x8]; 11677 u8 reserved_at_8[0x18]; 11678 11679 u8 syndrome[0x20]; 11680 11681 u8 reserved_at_40[0x40]; 11682 }; 11683 11684 struct mlx5_ifc_create_uctx_in_bits { 11685 u8 opcode[0x10]; 11686 u8 reserved_at_10[0x10]; 11687 11688 u8 reserved_at_20[0x10]; 11689 u8 op_mod[0x10]; 11690 11691 u8 reserved_at_40[0x40]; 11692 11693 struct mlx5_ifc_uctx_bits uctx; 11694 }; 11695 11696 struct mlx5_ifc_create_uctx_out_bits { 11697 u8 status[0x8]; 11698 u8 reserved_at_8[0x18]; 11699 11700 u8 syndrome[0x20]; 11701 11702 u8 reserved_at_40[0x10]; 11703 u8 uid[0x10]; 11704 11705 u8 reserved_at_60[0x20]; 11706 }; 11707 11708 struct mlx5_ifc_destroy_uctx_in_bits { 11709 u8 opcode[0x10]; 11710 u8 reserved_at_10[0x10]; 11711 11712 u8 reserved_at_20[0x10]; 11713 u8 op_mod[0x10]; 11714 11715 u8 reserved_at_40[0x10]; 11716 u8 uid[0x10]; 11717 11718 u8 reserved_at_60[0x20]; 11719 }; 11720 11721 struct mlx5_ifc_destroy_uctx_out_bits { 11722 u8 status[0x8]; 11723 u8 reserved_at_8[0x18]; 11724 11725 u8 syndrome[0x20]; 11726 11727 u8 reserved_at_40[0x40]; 11728 }; 11729 11730 struct mlx5_ifc_create_sw_icm_in_bits { 11731 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 11732 struct mlx5_ifc_sw_icm_bits sw_icm; 11733 }; 11734 11735 struct mlx5_ifc_create_geneve_tlv_option_in_bits { 11736 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 11737 struct mlx5_ifc_geneve_tlv_option_bits geneve_tlv_opt; 11738 }; 11739 11740 struct mlx5_ifc_mtrc_string_db_param_bits { 11741 u8 string_db_base_address[0x20]; 11742 11743 u8 reserved_at_20[0x8]; 11744 u8 string_db_size[0x18]; 11745 }; 11746 11747 struct mlx5_ifc_mtrc_cap_bits { 11748 u8 trace_owner[0x1]; 11749 u8 trace_to_memory[0x1]; 11750 u8 reserved_at_2[0x4]; 11751 u8 trc_ver[0x2]; 11752 u8 reserved_at_8[0x14]; 11753 u8 num_string_db[0x4]; 11754 11755 u8 first_string_trace[0x8]; 11756 u8 num_string_trace[0x8]; 11757 u8 reserved_at_30[0x28]; 11758 11759 u8 log_max_trace_buffer_size[0x8]; 11760 11761 u8 reserved_at_60[0x20]; 11762 11763 struct mlx5_ifc_mtrc_string_db_param_bits string_db_param[8]; 11764 11765 u8 reserved_at_280[0x180]; 11766 }; 11767 11768 struct mlx5_ifc_mtrc_conf_bits { 11769 u8 reserved_at_0[0x1c]; 11770 u8 trace_mode[0x4]; 11771 u8 reserved_at_20[0x18]; 11772 u8 log_trace_buffer_size[0x8]; 11773 u8 trace_mkey[0x20]; 11774 u8 reserved_at_60[0x3a0]; 11775 }; 11776 11777 struct mlx5_ifc_mtrc_stdb_bits { 11778 u8 string_db_index[0x4]; 11779 u8 reserved_at_4[0x4]; 11780 u8 read_size[0x18]; 11781 u8 start_offset[0x20]; 11782 u8 string_db_data[]; 11783 }; 11784 11785 struct mlx5_ifc_mtrc_ctrl_bits { 11786 u8 trace_status[0x2]; 11787 u8 reserved_at_2[0x2]; 11788 u8 arm_event[0x1]; 11789 u8 reserved_at_5[0xb]; 11790 u8 modify_field_select[0x10]; 11791 u8 reserved_at_20[0x2b]; 11792 u8 current_timestamp52_32[0x15]; 11793 u8 current_timestamp31_0[0x20]; 11794 u8 reserved_at_80[0x180]; 11795 }; 11796 11797 struct mlx5_ifc_host_params_context_bits { 11798 u8 host_number[0x8]; 11799 u8 reserved_at_8[0x7]; 11800 u8 host_pf_disabled[0x1]; 11801 u8 host_num_of_vfs[0x10]; 11802 11803 u8 host_total_vfs[0x10]; 11804 u8 host_pci_bus[0x10]; 11805 11806 u8 reserved_at_40[0x10]; 11807 u8 host_pci_device[0x10]; 11808 11809 u8 reserved_at_60[0x10]; 11810 u8 host_pci_function[0x10]; 11811 11812 u8 reserved_at_80[0x180]; 11813 }; 11814 11815 struct mlx5_ifc_query_esw_functions_in_bits { 11816 u8 opcode[0x10]; 11817 u8 reserved_at_10[0x10]; 11818 11819 u8 reserved_at_20[0x10]; 11820 u8 op_mod[0x10]; 11821 11822 u8 reserved_at_40[0x40]; 11823 }; 11824 11825 struct mlx5_ifc_query_esw_functions_out_bits { 11826 u8 status[0x8]; 11827 u8 reserved_at_8[0x18]; 11828 11829 u8 syndrome[0x20]; 11830 11831 u8 reserved_at_40[0x40]; 11832 11833 struct mlx5_ifc_host_params_context_bits host_params_context; 11834 11835 u8 reserved_at_280[0x180]; 11836 u8 host_sf_enable[][0x40]; 11837 }; 11838 11839 struct mlx5_ifc_sf_partition_bits { 11840 u8 reserved_at_0[0x10]; 11841 u8 log_num_sf[0x8]; 11842 u8 log_sf_bar_size[0x8]; 11843 }; 11844 11845 struct mlx5_ifc_query_sf_partitions_out_bits { 11846 u8 status[0x8]; 11847 u8 reserved_at_8[0x18]; 11848 11849 u8 syndrome[0x20]; 11850 11851 u8 reserved_at_40[0x18]; 11852 u8 num_sf_partitions[0x8]; 11853 11854 u8 reserved_at_60[0x20]; 11855 11856 struct mlx5_ifc_sf_partition_bits sf_partition[]; 11857 }; 11858 11859 struct mlx5_ifc_query_sf_partitions_in_bits { 11860 u8 opcode[0x10]; 11861 u8 reserved_at_10[0x10]; 11862 11863 u8 reserved_at_20[0x10]; 11864 u8 op_mod[0x10]; 11865 11866 u8 reserved_at_40[0x40]; 11867 }; 11868 11869 struct mlx5_ifc_dealloc_sf_out_bits { 11870 u8 status[0x8]; 11871 u8 reserved_at_8[0x18]; 11872 11873 u8 syndrome[0x20]; 11874 11875 u8 reserved_at_40[0x40]; 11876 }; 11877 11878 struct mlx5_ifc_dealloc_sf_in_bits { 11879 u8 opcode[0x10]; 11880 u8 reserved_at_10[0x10]; 11881 11882 u8 reserved_at_20[0x10]; 11883 u8 op_mod[0x10]; 11884 11885 u8 reserved_at_40[0x10]; 11886 u8 function_id[0x10]; 11887 11888 u8 reserved_at_60[0x20]; 11889 }; 11890 11891 struct mlx5_ifc_alloc_sf_out_bits { 11892 u8 status[0x8]; 11893 u8 reserved_at_8[0x18]; 11894 11895 u8 syndrome[0x20]; 11896 11897 u8 reserved_at_40[0x40]; 11898 }; 11899 11900 struct mlx5_ifc_alloc_sf_in_bits { 11901 u8 opcode[0x10]; 11902 u8 reserved_at_10[0x10]; 11903 11904 u8 reserved_at_20[0x10]; 11905 u8 op_mod[0x10]; 11906 11907 u8 reserved_at_40[0x10]; 11908 u8 function_id[0x10]; 11909 11910 u8 reserved_at_60[0x20]; 11911 }; 11912 11913 struct mlx5_ifc_affiliated_event_header_bits { 11914 u8 reserved_at_0[0x10]; 11915 u8 obj_type[0x10]; 11916 11917 u8 obj_id[0x20]; 11918 }; 11919 11920 enum { 11921 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = BIT_ULL(0xc), 11922 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_IPSEC = BIT_ULL(0x13), 11923 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_SAMPLER = BIT_ULL(0x20), 11924 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_FLOW_METER_ASO = BIT_ULL(0x24), 11925 }; 11926 11927 enum { 11928 MLX5_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = 0xc, 11929 MLX5_GENERAL_OBJECT_TYPES_IPSEC = 0x13, 11930 MLX5_GENERAL_OBJECT_TYPES_SAMPLER = 0x20, 11931 MLX5_GENERAL_OBJECT_TYPES_FLOW_METER_ASO = 0x24, 11932 MLX5_GENERAL_OBJECT_TYPES_MACSEC = 0x27, 11933 MLX5_GENERAL_OBJECT_TYPES_INT_KEK = 0x47, 11934 }; 11935 11936 enum { 11937 MLX5_IPSEC_OBJECT_ICV_LEN_16B, 11938 }; 11939 11940 enum { 11941 MLX5_IPSEC_ASO_REG_C_0_1 = 0x0, 11942 MLX5_IPSEC_ASO_REG_C_2_3 = 0x1, 11943 MLX5_IPSEC_ASO_REG_C_4_5 = 0x2, 11944 MLX5_IPSEC_ASO_REG_C_6_7 = 0x3, 11945 }; 11946 11947 enum { 11948 MLX5_IPSEC_ASO_MODE = 0x0, 11949 MLX5_IPSEC_ASO_REPLAY_PROTECTION = 0x1, 11950 MLX5_IPSEC_ASO_INC_SN = 0x2, 11951 }; 11952 11953 struct mlx5_ifc_ipsec_aso_bits { 11954 u8 valid[0x1]; 11955 u8 reserved_at_201[0x1]; 11956 u8 mode[0x2]; 11957 u8 window_sz[0x2]; 11958 u8 soft_lft_arm[0x1]; 11959 u8 hard_lft_arm[0x1]; 11960 u8 remove_flow_enable[0x1]; 11961 u8 esn_event_arm[0x1]; 11962 u8 reserved_at_20a[0x16]; 11963 11964 u8 remove_flow_pkt_cnt[0x20]; 11965 11966 u8 remove_flow_soft_lft[0x20]; 11967 11968 u8 reserved_at_260[0x80]; 11969 11970 u8 mode_parameter[0x20]; 11971 11972 u8 replay_protection_window[0x100]; 11973 }; 11974 11975 struct mlx5_ifc_ipsec_obj_bits { 11976 u8 modify_field_select[0x40]; 11977 u8 full_offload[0x1]; 11978 u8 reserved_at_41[0x1]; 11979 u8 esn_en[0x1]; 11980 u8 esn_overlap[0x1]; 11981 u8 reserved_at_44[0x2]; 11982 u8 icv_length[0x2]; 11983 u8 reserved_at_48[0x4]; 11984 u8 aso_return_reg[0x4]; 11985 u8 reserved_at_50[0x10]; 11986 11987 u8 esn_msb[0x20]; 11988 11989 u8 reserved_at_80[0x8]; 11990 u8 dekn[0x18]; 11991 11992 u8 salt[0x20]; 11993 11994 u8 implicit_iv[0x40]; 11995 11996 u8 reserved_at_100[0x8]; 11997 u8 ipsec_aso_access_pd[0x18]; 11998 u8 reserved_at_120[0xe0]; 11999 12000 struct mlx5_ifc_ipsec_aso_bits ipsec_aso; 12001 }; 12002 12003 struct mlx5_ifc_create_ipsec_obj_in_bits { 12004 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12005 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 12006 }; 12007 12008 enum { 12009 MLX5_MODIFY_IPSEC_BITMASK_ESN_OVERLAP = BIT(0), 12010 MLX5_MODIFY_IPSEC_BITMASK_ESN_MSB = BIT(1), 12011 }; 12012 12013 struct mlx5_ifc_query_ipsec_obj_out_bits { 12014 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 12015 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 12016 }; 12017 12018 struct mlx5_ifc_modify_ipsec_obj_in_bits { 12019 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12020 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 12021 }; 12022 12023 enum { 12024 MLX5_MACSEC_ASO_REPLAY_PROTECTION = 0x1, 12025 }; 12026 12027 enum { 12028 MLX5_MACSEC_ASO_REPLAY_WIN_32BIT = 0x0, 12029 MLX5_MACSEC_ASO_REPLAY_WIN_64BIT = 0x1, 12030 MLX5_MACSEC_ASO_REPLAY_WIN_128BIT = 0x2, 12031 MLX5_MACSEC_ASO_REPLAY_WIN_256BIT = 0x3, 12032 }; 12033 12034 #define MLX5_MACSEC_ASO_INC_SN 0x2 12035 #define MLX5_MACSEC_ASO_REG_C_4_5 0x2 12036 12037 struct mlx5_ifc_macsec_aso_bits { 12038 u8 valid[0x1]; 12039 u8 reserved_at_1[0x1]; 12040 u8 mode[0x2]; 12041 u8 window_size[0x2]; 12042 u8 soft_lifetime_arm[0x1]; 12043 u8 hard_lifetime_arm[0x1]; 12044 u8 remove_flow_enable[0x1]; 12045 u8 epn_event_arm[0x1]; 12046 u8 reserved_at_a[0x16]; 12047 12048 u8 remove_flow_packet_count[0x20]; 12049 12050 u8 remove_flow_soft_lifetime[0x20]; 12051 12052 u8 reserved_at_60[0x80]; 12053 12054 u8 mode_parameter[0x20]; 12055 12056 u8 replay_protection_window[8][0x20]; 12057 }; 12058 12059 struct mlx5_ifc_macsec_offload_obj_bits { 12060 u8 modify_field_select[0x40]; 12061 12062 u8 confidentiality_en[0x1]; 12063 u8 reserved_at_41[0x1]; 12064 u8 epn_en[0x1]; 12065 u8 epn_overlap[0x1]; 12066 u8 reserved_at_44[0x2]; 12067 u8 confidentiality_offset[0x2]; 12068 u8 reserved_at_48[0x4]; 12069 u8 aso_return_reg[0x4]; 12070 u8 reserved_at_50[0x10]; 12071 12072 u8 epn_msb[0x20]; 12073 12074 u8 reserved_at_80[0x8]; 12075 u8 dekn[0x18]; 12076 12077 u8 reserved_at_a0[0x20]; 12078 12079 u8 sci[0x40]; 12080 12081 u8 reserved_at_100[0x8]; 12082 u8 macsec_aso_access_pd[0x18]; 12083 12084 u8 reserved_at_120[0x60]; 12085 12086 u8 salt[3][0x20]; 12087 12088 u8 reserved_at_1e0[0x20]; 12089 12090 struct mlx5_ifc_macsec_aso_bits macsec_aso; 12091 }; 12092 12093 struct mlx5_ifc_create_macsec_obj_in_bits { 12094 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12095 struct mlx5_ifc_macsec_offload_obj_bits macsec_object; 12096 }; 12097 12098 struct mlx5_ifc_modify_macsec_obj_in_bits { 12099 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12100 struct mlx5_ifc_macsec_offload_obj_bits macsec_object; 12101 }; 12102 12103 enum { 12104 MLX5_MODIFY_MACSEC_BITMASK_EPN_OVERLAP = BIT(0), 12105 MLX5_MODIFY_MACSEC_BITMASK_EPN_MSB = BIT(1), 12106 }; 12107 12108 struct mlx5_ifc_query_macsec_obj_out_bits { 12109 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 12110 struct mlx5_ifc_macsec_offload_obj_bits macsec_object; 12111 }; 12112 12113 struct mlx5_ifc_wrapped_dek_bits { 12114 u8 gcm_iv[0x60]; 12115 12116 u8 reserved_at_60[0x20]; 12117 12118 u8 const0[0x1]; 12119 u8 key_size[0x1]; 12120 u8 reserved_at_82[0x2]; 12121 u8 key2_invalid[0x1]; 12122 u8 reserved_at_85[0x3]; 12123 u8 pd[0x18]; 12124 12125 u8 key_purpose[0x5]; 12126 u8 reserved_at_a5[0x13]; 12127 u8 kek_id[0x8]; 12128 12129 u8 reserved_at_c0[0x40]; 12130 12131 u8 key1[0x8][0x20]; 12132 12133 u8 key2[0x8][0x20]; 12134 12135 u8 reserved_at_300[0x40]; 12136 12137 u8 const1[0x1]; 12138 u8 reserved_at_341[0x1f]; 12139 12140 u8 reserved_at_360[0x20]; 12141 12142 u8 auth_tag[0x80]; 12143 }; 12144 12145 struct mlx5_ifc_encryption_key_obj_bits { 12146 u8 modify_field_select[0x40]; 12147 12148 u8 state[0x8]; 12149 u8 sw_wrapped[0x1]; 12150 u8 reserved_at_49[0xb]; 12151 u8 key_size[0x4]; 12152 u8 reserved_at_58[0x4]; 12153 u8 key_purpose[0x4]; 12154 12155 u8 reserved_at_60[0x8]; 12156 u8 pd[0x18]; 12157 12158 u8 reserved_at_80[0x100]; 12159 12160 u8 opaque[0x40]; 12161 12162 u8 reserved_at_1c0[0x40]; 12163 12164 u8 key[8][0x80]; 12165 12166 u8 sw_wrapped_dek[8][0x80]; 12167 12168 u8 reserved_at_a00[0x600]; 12169 }; 12170 12171 struct mlx5_ifc_create_encryption_key_in_bits { 12172 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12173 struct mlx5_ifc_encryption_key_obj_bits encryption_key_object; 12174 }; 12175 12176 struct mlx5_ifc_modify_encryption_key_in_bits { 12177 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12178 struct mlx5_ifc_encryption_key_obj_bits encryption_key_object; 12179 }; 12180 12181 enum { 12182 MLX5_FLOW_METER_MODE_BYTES_IP_LENGTH = 0x0, 12183 MLX5_FLOW_METER_MODE_BYTES_CALC_WITH_L2 = 0x1, 12184 MLX5_FLOW_METER_MODE_BYTES_CALC_WITH_L2_IPG = 0x2, 12185 MLX5_FLOW_METER_MODE_NUM_PACKETS = 0x3, 12186 }; 12187 12188 struct mlx5_ifc_flow_meter_parameters_bits { 12189 u8 valid[0x1]; 12190 u8 bucket_overflow[0x1]; 12191 u8 start_color[0x2]; 12192 u8 both_buckets_on_green[0x1]; 12193 u8 reserved_at_5[0x1]; 12194 u8 meter_mode[0x2]; 12195 u8 reserved_at_8[0x18]; 12196 12197 u8 reserved_at_20[0x20]; 12198 12199 u8 reserved_at_40[0x3]; 12200 u8 cbs_exponent[0x5]; 12201 u8 cbs_mantissa[0x8]; 12202 u8 reserved_at_50[0x3]; 12203 u8 cir_exponent[0x5]; 12204 u8 cir_mantissa[0x8]; 12205 12206 u8 reserved_at_60[0x20]; 12207 12208 u8 reserved_at_80[0x3]; 12209 u8 ebs_exponent[0x5]; 12210 u8 ebs_mantissa[0x8]; 12211 u8 reserved_at_90[0x3]; 12212 u8 eir_exponent[0x5]; 12213 u8 eir_mantissa[0x8]; 12214 12215 u8 reserved_at_a0[0x60]; 12216 }; 12217 12218 struct mlx5_ifc_flow_meter_aso_obj_bits { 12219 u8 modify_field_select[0x40]; 12220 12221 u8 reserved_at_40[0x40]; 12222 12223 u8 reserved_at_80[0x8]; 12224 u8 meter_aso_access_pd[0x18]; 12225 12226 u8 reserved_at_a0[0x160]; 12227 12228 struct mlx5_ifc_flow_meter_parameters_bits flow_meter_parameters[2]; 12229 }; 12230 12231 struct mlx5_ifc_create_flow_meter_aso_obj_in_bits { 12232 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 12233 struct mlx5_ifc_flow_meter_aso_obj_bits flow_meter_aso_obj; 12234 }; 12235 12236 struct mlx5_ifc_int_kek_obj_bits { 12237 u8 modify_field_select[0x40]; 12238 12239 u8 state[0x8]; 12240 u8 auto_gen[0x1]; 12241 u8 reserved_at_49[0xb]; 12242 u8 key_size[0x4]; 12243 u8 reserved_at_58[0x8]; 12244 12245 u8 reserved_at_60[0x8]; 12246 u8 pd[0x18]; 12247 12248 u8 reserved_at_80[0x180]; 12249 u8 key[8][0x80]; 12250 12251 u8 reserved_at_600[0x200]; 12252 }; 12253 12254 struct mlx5_ifc_create_int_kek_obj_in_bits { 12255 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12256 struct mlx5_ifc_int_kek_obj_bits int_kek_object; 12257 }; 12258 12259 struct mlx5_ifc_create_int_kek_obj_out_bits { 12260 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 12261 struct mlx5_ifc_int_kek_obj_bits int_kek_object; 12262 }; 12263 12264 struct mlx5_ifc_sampler_obj_bits { 12265 u8 modify_field_select[0x40]; 12266 12267 u8 table_type[0x8]; 12268 u8 level[0x8]; 12269 u8 reserved_at_50[0xf]; 12270 u8 ignore_flow_level[0x1]; 12271 12272 u8 sample_ratio[0x20]; 12273 12274 u8 reserved_at_80[0x8]; 12275 u8 sample_table_id[0x18]; 12276 12277 u8 reserved_at_a0[0x8]; 12278 u8 default_table_id[0x18]; 12279 12280 u8 sw_steering_icm_address_rx[0x40]; 12281 u8 sw_steering_icm_address_tx[0x40]; 12282 12283 u8 reserved_at_140[0xa0]; 12284 }; 12285 12286 struct mlx5_ifc_create_sampler_obj_in_bits { 12287 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12288 struct mlx5_ifc_sampler_obj_bits sampler_object; 12289 }; 12290 12291 struct mlx5_ifc_query_sampler_obj_out_bits { 12292 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 12293 struct mlx5_ifc_sampler_obj_bits sampler_object; 12294 }; 12295 12296 enum { 12297 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_128 = 0x0, 12298 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_256 = 0x1, 12299 }; 12300 12301 enum { 12302 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_PURPOSE_TLS = 0x1, 12303 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_PURPOSE_IPSEC = 0x2, 12304 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_PURPOSE_MACSEC = 0x4, 12305 }; 12306 12307 struct mlx5_ifc_tls_static_params_bits { 12308 u8 const_2[0x2]; 12309 u8 tls_version[0x4]; 12310 u8 const_1[0x2]; 12311 u8 reserved_at_8[0x14]; 12312 u8 encryption_standard[0x4]; 12313 12314 u8 reserved_at_20[0x20]; 12315 12316 u8 initial_record_number[0x40]; 12317 12318 u8 resync_tcp_sn[0x20]; 12319 12320 u8 gcm_iv[0x20]; 12321 12322 u8 implicit_iv[0x40]; 12323 12324 u8 reserved_at_100[0x8]; 12325 u8 dek_index[0x18]; 12326 12327 u8 reserved_at_120[0xe0]; 12328 }; 12329 12330 struct mlx5_ifc_tls_progress_params_bits { 12331 u8 next_record_tcp_sn[0x20]; 12332 12333 u8 hw_resync_tcp_sn[0x20]; 12334 12335 u8 record_tracker_state[0x2]; 12336 u8 auth_state[0x2]; 12337 u8 reserved_at_44[0x4]; 12338 u8 hw_offset_record_number[0x18]; 12339 }; 12340 12341 enum { 12342 MLX5_MTT_PERM_READ = 1 << 0, 12343 MLX5_MTT_PERM_WRITE = 1 << 1, 12344 MLX5_MTT_PERM_RW = MLX5_MTT_PERM_READ | MLX5_MTT_PERM_WRITE, 12345 }; 12346 12347 enum { 12348 MLX5_SUSPEND_VHCA_IN_OP_MOD_SUSPEND_INITIATOR = 0x0, 12349 MLX5_SUSPEND_VHCA_IN_OP_MOD_SUSPEND_RESPONDER = 0x1, 12350 }; 12351 12352 struct mlx5_ifc_suspend_vhca_in_bits { 12353 u8 opcode[0x10]; 12354 u8 uid[0x10]; 12355 12356 u8 reserved_at_20[0x10]; 12357 u8 op_mod[0x10]; 12358 12359 u8 reserved_at_40[0x10]; 12360 u8 vhca_id[0x10]; 12361 12362 u8 reserved_at_60[0x20]; 12363 }; 12364 12365 struct mlx5_ifc_suspend_vhca_out_bits { 12366 u8 status[0x8]; 12367 u8 reserved_at_8[0x18]; 12368 12369 u8 syndrome[0x20]; 12370 12371 u8 reserved_at_40[0x40]; 12372 }; 12373 12374 enum { 12375 MLX5_RESUME_VHCA_IN_OP_MOD_RESUME_RESPONDER = 0x0, 12376 MLX5_RESUME_VHCA_IN_OP_MOD_RESUME_INITIATOR = 0x1, 12377 }; 12378 12379 struct mlx5_ifc_resume_vhca_in_bits { 12380 u8 opcode[0x10]; 12381 u8 uid[0x10]; 12382 12383 u8 reserved_at_20[0x10]; 12384 u8 op_mod[0x10]; 12385 12386 u8 reserved_at_40[0x10]; 12387 u8 vhca_id[0x10]; 12388 12389 u8 reserved_at_60[0x20]; 12390 }; 12391 12392 struct mlx5_ifc_resume_vhca_out_bits { 12393 u8 status[0x8]; 12394 u8 reserved_at_8[0x18]; 12395 12396 u8 syndrome[0x20]; 12397 12398 u8 reserved_at_40[0x40]; 12399 }; 12400 12401 struct mlx5_ifc_query_vhca_migration_state_in_bits { 12402 u8 opcode[0x10]; 12403 u8 uid[0x10]; 12404 12405 u8 reserved_at_20[0x10]; 12406 u8 op_mod[0x10]; 12407 12408 u8 incremental[0x1]; 12409 u8 reserved_at_41[0xf]; 12410 u8 vhca_id[0x10]; 12411 12412 u8 reserved_at_60[0x20]; 12413 }; 12414 12415 struct mlx5_ifc_query_vhca_migration_state_out_bits { 12416 u8 status[0x8]; 12417 u8 reserved_at_8[0x18]; 12418 12419 u8 syndrome[0x20]; 12420 12421 u8 reserved_at_40[0x40]; 12422 12423 u8 required_umem_size[0x20]; 12424 12425 u8 reserved_at_a0[0x160]; 12426 }; 12427 12428 struct mlx5_ifc_save_vhca_state_in_bits { 12429 u8 opcode[0x10]; 12430 u8 uid[0x10]; 12431 12432 u8 reserved_at_20[0x10]; 12433 u8 op_mod[0x10]; 12434 12435 u8 incremental[0x1]; 12436 u8 set_track[0x1]; 12437 u8 reserved_at_42[0xe]; 12438 u8 vhca_id[0x10]; 12439 12440 u8 reserved_at_60[0x20]; 12441 12442 u8 va[0x40]; 12443 12444 u8 mkey[0x20]; 12445 12446 u8 size[0x20]; 12447 }; 12448 12449 struct mlx5_ifc_save_vhca_state_out_bits { 12450 u8 status[0x8]; 12451 u8 reserved_at_8[0x18]; 12452 12453 u8 syndrome[0x20]; 12454 12455 u8 actual_image_size[0x20]; 12456 12457 u8 reserved_at_60[0x20]; 12458 }; 12459 12460 struct mlx5_ifc_load_vhca_state_in_bits { 12461 u8 opcode[0x10]; 12462 u8 uid[0x10]; 12463 12464 u8 reserved_at_20[0x10]; 12465 u8 op_mod[0x10]; 12466 12467 u8 reserved_at_40[0x10]; 12468 u8 vhca_id[0x10]; 12469 12470 u8 reserved_at_60[0x20]; 12471 12472 u8 va[0x40]; 12473 12474 u8 mkey[0x20]; 12475 12476 u8 size[0x20]; 12477 }; 12478 12479 struct mlx5_ifc_load_vhca_state_out_bits { 12480 u8 status[0x8]; 12481 u8 reserved_at_8[0x18]; 12482 12483 u8 syndrome[0x20]; 12484 12485 u8 reserved_at_40[0x40]; 12486 }; 12487 12488 struct mlx5_ifc_adv_virtualization_cap_bits { 12489 u8 reserved_at_0[0x3]; 12490 u8 pg_track_log_max_num[0x5]; 12491 u8 pg_track_max_num_range[0x8]; 12492 u8 pg_track_log_min_addr_space[0x8]; 12493 u8 pg_track_log_max_addr_space[0x8]; 12494 12495 u8 reserved_at_20[0x3]; 12496 u8 pg_track_log_min_msg_size[0x5]; 12497 u8 reserved_at_28[0x3]; 12498 u8 pg_track_log_max_msg_size[0x5]; 12499 u8 reserved_at_30[0x3]; 12500 u8 pg_track_log_min_page_size[0x5]; 12501 u8 reserved_at_38[0x3]; 12502 u8 pg_track_log_max_page_size[0x5]; 12503 12504 u8 reserved_at_40[0x7c0]; 12505 }; 12506 12507 struct mlx5_ifc_page_track_report_entry_bits { 12508 u8 dirty_address_high[0x20]; 12509 12510 u8 dirty_address_low[0x20]; 12511 }; 12512 12513 enum { 12514 MLX5_PAGE_TRACK_STATE_TRACKING, 12515 MLX5_PAGE_TRACK_STATE_REPORTING, 12516 MLX5_PAGE_TRACK_STATE_ERROR, 12517 }; 12518 12519 struct mlx5_ifc_page_track_range_bits { 12520 u8 start_address[0x40]; 12521 12522 u8 length[0x40]; 12523 }; 12524 12525 struct mlx5_ifc_page_track_bits { 12526 u8 modify_field_select[0x40]; 12527 12528 u8 reserved_at_40[0x10]; 12529 u8 vhca_id[0x10]; 12530 12531 u8 reserved_at_60[0x20]; 12532 12533 u8 state[0x4]; 12534 u8 track_type[0x4]; 12535 u8 log_addr_space_size[0x8]; 12536 u8 reserved_at_90[0x3]; 12537 u8 log_page_size[0x5]; 12538 u8 reserved_at_98[0x3]; 12539 u8 log_msg_size[0x5]; 12540 12541 u8 reserved_at_a0[0x8]; 12542 u8 reporting_qpn[0x18]; 12543 12544 u8 reserved_at_c0[0x18]; 12545 u8 num_ranges[0x8]; 12546 12547 u8 reserved_at_e0[0x20]; 12548 12549 u8 range_start_address[0x40]; 12550 12551 u8 length[0x40]; 12552 12553 struct mlx5_ifc_page_track_range_bits track_range[0]; 12554 }; 12555 12556 struct mlx5_ifc_create_page_track_obj_in_bits { 12557 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12558 struct mlx5_ifc_page_track_bits obj_context; 12559 }; 12560 12561 struct mlx5_ifc_modify_page_track_obj_in_bits { 12562 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12563 struct mlx5_ifc_page_track_bits obj_context; 12564 }; 12565 12566 #endif /* MLX5_IFC_H */ 12567