1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 #ifndef MLX5_IFC_H 33 #define MLX5_IFC_H 34 35 #include "mlx5_ifc_fpga.h" 36 37 enum { 38 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0, 39 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1, 40 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2, 41 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3, 42 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13, 43 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14, 44 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c, 45 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d, 46 MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4, 47 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5, 48 MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED = 0x7, 49 MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT = 0xc, 50 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10, 51 MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR = 0x11, 52 MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR = 0x12, 53 MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR = 0x8, 54 MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE = 0x9, 55 MLX5_EVENT_TYPE_CODING_GPIO_EVENT = 0x15, 56 MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19, 57 MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a, 58 MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT = 0x1b, 59 MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT = 0x1f, 60 MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa, 61 MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb, 62 MLX5_EVENT_TYPE_CODING_FPGA_ERROR = 0x20, 63 MLX5_EVENT_TYPE_CODING_FPGA_QP_ERROR = 0x21 64 }; 65 66 enum { 67 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0, 68 MLX5_SET_HCA_CAP_OP_MOD_ODP = 0x2, 69 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3, 70 MLX5_SET_HCA_CAP_OP_MOD_ROCE = 0x4, 71 }; 72 73 enum { 74 MLX5_SHARED_RESOURCE_UID = 0xffff, 75 }; 76 77 enum { 78 MLX5_OBJ_TYPE_SW_ICM = 0x0008, 79 }; 80 81 enum { 82 MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM = (1ULL << MLX5_OBJ_TYPE_SW_ICM), 83 MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT = (1ULL << 11), 84 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q = (1ULL << 13), 85 }; 86 87 enum { 88 MLX5_OBJ_TYPE_GENEVE_TLV_OPT = 0x000b, 89 MLX5_OBJ_TYPE_VIRTIO_NET_Q = 0x000d, 90 MLX5_OBJ_TYPE_VIRTIO_Q_COUNTERS = 0x001c, 91 MLX5_OBJ_TYPE_MATCH_DEFINER = 0x0018, 92 MLX5_OBJ_TYPE_MKEY = 0xff01, 93 MLX5_OBJ_TYPE_QP = 0xff02, 94 MLX5_OBJ_TYPE_PSV = 0xff03, 95 MLX5_OBJ_TYPE_RMP = 0xff04, 96 MLX5_OBJ_TYPE_XRC_SRQ = 0xff05, 97 MLX5_OBJ_TYPE_RQ = 0xff06, 98 MLX5_OBJ_TYPE_SQ = 0xff07, 99 MLX5_OBJ_TYPE_TIR = 0xff08, 100 MLX5_OBJ_TYPE_TIS = 0xff09, 101 MLX5_OBJ_TYPE_DCT = 0xff0a, 102 MLX5_OBJ_TYPE_XRQ = 0xff0b, 103 MLX5_OBJ_TYPE_RQT = 0xff0e, 104 MLX5_OBJ_TYPE_FLOW_COUNTER = 0xff0f, 105 MLX5_OBJ_TYPE_CQ = 0xff10, 106 }; 107 108 enum { 109 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100, 110 MLX5_CMD_OP_QUERY_ADAPTER = 0x101, 111 MLX5_CMD_OP_INIT_HCA = 0x102, 112 MLX5_CMD_OP_TEARDOWN_HCA = 0x103, 113 MLX5_CMD_OP_ENABLE_HCA = 0x104, 114 MLX5_CMD_OP_DISABLE_HCA = 0x105, 115 MLX5_CMD_OP_QUERY_PAGES = 0x107, 116 MLX5_CMD_OP_MANAGE_PAGES = 0x108, 117 MLX5_CMD_OP_SET_HCA_CAP = 0x109, 118 MLX5_CMD_OP_QUERY_ISSI = 0x10a, 119 MLX5_CMD_OP_SET_ISSI = 0x10b, 120 MLX5_CMD_OP_SET_DRIVER_VERSION = 0x10d, 121 MLX5_CMD_OP_QUERY_SF_PARTITION = 0x111, 122 MLX5_CMD_OP_ALLOC_SF = 0x113, 123 MLX5_CMD_OP_DEALLOC_SF = 0x114, 124 MLX5_CMD_OP_SUSPEND_VHCA = 0x115, 125 MLX5_CMD_OP_RESUME_VHCA = 0x116, 126 MLX5_CMD_OP_QUERY_VHCA_MIGRATION_STATE = 0x117, 127 MLX5_CMD_OP_SAVE_VHCA_STATE = 0x118, 128 MLX5_CMD_OP_LOAD_VHCA_STATE = 0x119, 129 MLX5_CMD_OP_CREATE_MKEY = 0x200, 130 MLX5_CMD_OP_QUERY_MKEY = 0x201, 131 MLX5_CMD_OP_DESTROY_MKEY = 0x202, 132 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203, 133 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204, 134 MLX5_CMD_OP_ALLOC_MEMIC = 0x205, 135 MLX5_CMD_OP_DEALLOC_MEMIC = 0x206, 136 MLX5_CMD_OP_MODIFY_MEMIC = 0x207, 137 MLX5_CMD_OP_CREATE_EQ = 0x301, 138 MLX5_CMD_OP_DESTROY_EQ = 0x302, 139 MLX5_CMD_OP_QUERY_EQ = 0x303, 140 MLX5_CMD_OP_GEN_EQE = 0x304, 141 MLX5_CMD_OP_CREATE_CQ = 0x400, 142 MLX5_CMD_OP_DESTROY_CQ = 0x401, 143 MLX5_CMD_OP_QUERY_CQ = 0x402, 144 MLX5_CMD_OP_MODIFY_CQ = 0x403, 145 MLX5_CMD_OP_CREATE_QP = 0x500, 146 MLX5_CMD_OP_DESTROY_QP = 0x501, 147 MLX5_CMD_OP_RST2INIT_QP = 0x502, 148 MLX5_CMD_OP_INIT2RTR_QP = 0x503, 149 MLX5_CMD_OP_RTR2RTS_QP = 0x504, 150 MLX5_CMD_OP_RTS2RTS_QP = 0x505, 151 MLX5_CMD_OP_SQERR2RTS_QP = 0x506, 152 MLX5_CMD_OP_2ERR_QP = 0x507, 153 MLX5_CMD_OP_2RST_QP = 0x50a, 154 MLX5_CMD_OP_QUERY_QP = 0x50b, 155 MLX5_CMD_OP_SQD_RTS_QP = 0x50c, 156 MLX5_CMD_OP_INIT2INIT_QP = 0x50e, 157 MLX5_CMD_OP_CREATE_PSV = 0x600, 158 MLX5_CMD_OP_DESTROY_PSV = 0x601, 159 MLX5_CMD_OP_CREATE_SRQ = 0x700, 160 MLX5_CMD_OP_DESTROY_SRQ = 0x701, 161 MLX5_CMD_OP_QUERY_SRQ = 0x702, 162 MLX5_CMD_OP_ARM_RQ = 0x703, 163 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705, 164 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706, 165 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707, 166 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708, 167 MLX5_CMD_OP_CREATE_DCT = 0x710, 168 MLX5_CMD_OP_DESTROY_DCT = 0x711, 169 MLX5_CMD_OP_DRAIN_DCT = 0x712, 170 MLX5_CMD_OP_QUERY_DCT = 0x713, 171 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714, 172 MLX5_CMD_OP_CREATE_XRQ = 0x717, 173 MLX5_CMD_OP_DESTROY_XRQ = 0x718, 174 MLX5_CMD_OP_QUERY_XRQ = 0x719, 175 MLX5_CMD_OP_ARM_XRQ = 0x71a, 176 MLX5_CMD_OP_QUERY_XRQ_DC_PARAMS_ENTRY = 0x725, 177 MLX5_CMD_OP_SET_XRQ_DC_PARAMS_ENTRY = 0x726, 178 MLX5_CMD_OP_QUERY_XRQ_ERROR_PARAMS = 0x727, 179 MLX5_CMD_OP_RELEASE_XRQ_ERROR = 0x729, 180 MLX5_CMD_OP_MODIFY_XRQ = 0x72a, 181 MLX5_CMD_OP_QUERY_ESW_FUNCTIONS = 0x740, 182 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750, 183 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751, 184 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752, 185 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753, 186 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754, 187 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755, 188 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760, 189 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761, 190 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762, 191 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763, 192 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764, 193 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765, 194 MLX5_CMD_OP_QUERY_VNIC_ENV = 0x76f, 195 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770, 196 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771, 197 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772, 198 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773, 199 MLX5_CMD_OP_SET_MONITOR_COUNTER = 0x774, 200 MLX5_CMD_OP_ARM_MONITOR_COUNTER = 0x775, 201 MLX5_CMD_OP_SET_PP_RATE_LIMIT = 0x780, 202 MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781, 203 MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT = 0x782, 204 MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT = 0x783, 205 MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT = 0x784, 206 MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT = 0x785, 207 MLX5_CMD_OP_CREATE_QOS_PARA_VPORT = 0x786, 208 MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT = 0x787, 209 MLX5_CMD_OP_ALLOC_PD = 0x800, 210 MLX5_CMD_OP_DEALLOC_PD = 0x801, 211 MLX5_CMD_OP_ALLOC_UAR = 0x802, 212 MLX5_CMD_OP_DEALLOC_UAR = 0x803, 213 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804, 214 MLX5_CMD_OP_ACCESS_REG = 0x805, 215 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806, 216 MLX5_CMD_OP_DETACH_FROM_MCG = 0x807, 217 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a, 218 MLX5_CMD_OP_MAD_IFC = 0x50d, 219 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b, 220 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c, 221 MLX5_CMD_OP_NOP = 0x80d, 222 MLX5_CMD_OP_ALLOC_XRCD = 0x80e, 223 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f, 224 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816, 225 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817, 226 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822, 227 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823, 228 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824, 229 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825, 230 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826, 231 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827, 232 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828, 233 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829, 234 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a, 235 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b, 236 MLX5_CMD_OP_SET_WOL_ROL = 0x830, 237 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831, 238 MLX5_CMD_OP_CREATE_LAG = 0x840, 239 MLX5_CMD_OP_MODIFY_LAG = 0x841, 240 MLX5_CMD_OP_QUERY_LAG = 0x842, 241 MLX5_CMD_OP_DESTROY_LAG = 0x843, 242 MLX5_CMD_OP_CREATE_VPORT_LAG = 0x844, 243 MLX5_CMD_OP_DESTROY_VPORT_LAG = 0x845, 244 MLX5_CMD_OP_CREATE_TIR = 0x900, 245 MLX5_CMD_OP_MODIFY_TIR = 0x901, 246 MLX5_CMD_OP_DESTROY_TIR = 0x902, 247 MLX5_CMD_OP_QUERY_TIR = 0x903, 248 MLX5_CMD_OP_CREATE_SQ = 0x904, 249 MLX5_CMD_OP_MODIFY_SQ = 0x905, 250 MLX5_CMD_OP_DESTROY_SQ = 0x906, 251 MLX5_CMD_OP_QUERY_SQ = 0x907, 252 MLX5_CMD_OP_CREATE_RQ = 0x908, 253 MLX5_CMD_OP_MODIFY_RQ = 0x909, 254 MLX5_CMD_OP_SET_DELAY_DROP_PARAMS = 0x910, 255 MLX5_CMD_OP_DESTROY_RQ = 0x90a, 256 MLX5_CMD_OP_QUERY_RQ = 0x90b, 257 MLX5_CMD_OP_CREATE_RMP = 0x90c, 258 MLX5_CMD_OP_MODIFY_RMP = 0x90d, 259 MLX5_CMD_OP_DESTROY_RMP = 0x90e, 260 MLX5_CMD_OP_QUERY_RMP = 0x90f, 261 MLX5_CMD_OP_CREATE_TIS = 0x912, 262 MLX5_CMD_OP_MODIFY_TIS = 0x913, 263 MLX5_CMD_OP_DESTROY_TIS = 0x914, 264 MLX5_CMD_OP_QUERY_TIS = 0x915, 265 MLX5_CMD_OP_CREATE_RQT = 0x916, 266 MLX5_CMD_OP_MODIFY_RQT = 0x917, 267 MLX5_CMD_OP_DESTROY_RQT = 0x918, 268 MLX5_CMD_OP_QUERY_RQT = 0x919, 269 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f, 270 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930, 271 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931, 272 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932, 273 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933, 274 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934, 275 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935, 276 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936, 277 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937, 278 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938, 279 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939, 280 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a, 281 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b, 282 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c, 283 MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT = 0x93d, 284 MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT = 0x93e, 285 MLX5_CMD_OP_QUERY_PACKET_REFORMAT_CONTEXT = 0x93f, 286 MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT = 0x940, 287 MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941, 288 MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT = 0x942, 289 MLX5_CMD_OP_FPGA_CREATE_QP = 0x960, 290 MLX5_CMD_OP_FPGA_MODIFY_QP = 0x961, 291 MLX5_CMD_OP_FPGA_QUERY_QP = 0x962, 292 MLX5_CMD_OP_FPGA_DESTROY_QP = 0x963, 293 MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS = 0x964, 294 MLX5_CMD_OP_CREATE_GENERAL_OBJECT = 0xa00, 295 MLX5_CMD_OP_MODIFY_GENERAL_OBJECT = 0xa01, 296 MLX5_CMD_OP_QUERY_GENERAL_OBJECT = 0xa02, 297 MLX5_CMD_OP_DESTROY_GENERAL_OBJECT = 0xa03, 298 MLX5_CMD_OP_CREATE_UCTX = 0xa04, 299 MLX5_CMD_OP_DESTROY_UCTX = 0xa06, 300 MLX5_CMD_OP_CREATE_UMEM = 0xa08, 301 MLX5_CMD_OP_DESTROY_UMEM = 0xa0a, 302 MLX5_CMD_OP_SYNC_STEERING = 0xb00, 303 MLX5_CMD_OP_QUERY_VHCA_STATE = 0xb0d, 304 MLX5_CMD_OP_MODIFY_VHCA_STATE = 0xb0e, 305 MLX5_CMD_OP_MAX 306 }; 307 308 /* Valid range for general commands that don't work over an object */ 309 enum { 310 MLX5_CMD_OP_GENERAL_START = 0xb00, 311 MLX5_CMD_OP_GENERAL_END = 0xd00, 312 }; 313 314 struct mlx5_ifc_flow_table_fields_supported_bits { 315 u8 outer_dmac[0x1]; 316 u8 outer_smac[0x1]; 317 u8 outer_ether_type[0x1]; 318 u8 outer_ip_version[0x1]; 319 u8 outer_first_prio[0x1]; 320 u8 outer_first_cfi[0x1]; 321 u8 outer_first_vid[0x1]; 322 u8 outer_ipv4_ttl[0x1]; 323 u8 outer_second_prio[0x1]; 324 u8 outer_second_cfi[0x1]; 325 u8 outer_second_vid[0x1]; 326 u8 reserved_at_b[0x1]; 327 u8 outer_sip[0x1]; 328 u8 outer_dip[0x1]; 329 u8 outer_frag[0x1]; 330 u8 outer_ip_protocol[0x1]; 331 u8 outer_ip_ecn[0x1]; 332 u8 outer_ip_dscp[0x1]; 333 u8 outer_udp_sport[0x1]; 334 u8 outer_udp_dport[0x1]; 335 u8 outer_tcp_sport[0x1]; 336 u8 outer_tcp_dport[0x1]; 337 u8 outer_tcp_flags[0x1]; 338 u8 outer_gre_protocol[0x1]; 339 u8 outer_gre_key[0x1]; 340 u8 outer_vxlan_vni[0x1]; 341 u8 outer_geneve_vni[0x1]; 342 u8 outer_geneve_oam[0x1]; 343 u8 outer_geneve_protocol_type[0x1]; 344 u8 outer_geneve_opt_len[0x1]; 345 u8 source_vhca_port[0x1]; 346 u8 source_eswitch_port[0x1]; 347 348 u8 inner_dmac[0x1]; 349 u8 inner_smac[0x1]; 350 u8 inner_ether_type[0x1]; 351 u8 inner_ip_version[0x1]; 352 u8 inner_first_prio[0x1]; 353 u8 inner_first_cfi[0x1]; 354 u8 inner_first_vid[0x1]; 355 u8 reserved_at_27[0x1]; 356 u8 inner_second_prio[0x1]; 357 u8 inner_second_cfi[0x1]; 358 u8 inner_second_vid[0x1]; 359 u8 reserved_at_2b[0x1]; 360 u8 inner_sip[0x1]; 361 u8 inner_dip[0x1]; 362 u8 inner_frag[0x1]; 363 u8 inner_ip_protocol[0x1]; 364 u8 inner_ip_ecn[0x1]; 365 u8 inner_ip_dscp[0x1]; 366 u8 inner_udp_sport[0x1]; 367 u8 inner_udp_dport[0x1]; 368 u8 inner_tcp_sport[0x1]; 369 u8 inner_tcp_dport[0x1]; 370 u8 inner_tcp_flags[0x1]; 371 u8 reserved_at_37[0x9]; 372 373 u8 geneve_tlv_option_0_data[0x1]; 374 u8 geneve_tlv_option_0_exist[0x1]; 375 u8 reserved_at_42[0x3]; 376 u8 outer_first_mpls_over_udp[0x4]; 377 u8 outer_first_mpls_over_gre[0x4]; 378 u8 inner_first_mpls[0x4]; 379 u8 outer_first_mpls[0x4]; 380 u8 reserved_at_55[0x2]; 381 u8 outer_esp_spi[0x1]; 382 u8 reserved_at_58[0x2]; 383 u8 bth_dst_qp[0x1]; 384 u8 reserved_at_5b[0x5]; 385 386 u8 reserved_at_60[0x18]; 387 u8 metadata_reg_c_7[0x1]; 388 u8 metadata_reg_c_6[0x1]; 389 u8 metadata_reg_c_5[0x1]; 390 u8 metadata_reg_c_4[0x1]; 391 u8 metadata_reg_c_3[0x1]; 392 u8 metadata_reg_c_2[0x1]; 393 u8 metadata_reg_c_1[0x1]; 394 u8 metadata_reg_c_0[0x1]; 395 }; 396 397 struct mlx5_ifc_flow_table_fields_supported_2_bits { 398 u8 reserved_at_0[0xe]; 399 u8 bth_opcode[0x1]; 400 u8 reserved_at_f[0x11]; 401 402 u8 reserved_at_20[0x60]; 403 }; 404 405 struct mlx5_ifc_flow_table_prop_layout_bits { 406 u8 ft_support[0x1]; 407 u8 reserved_at_1[0x1]; 408 u8 flow_counter[0x1]; 409 u8 flow_modify_en[0x1]; 410 u8 modify_root[0x1]; 411 u8 identified_miss_table_mode[0x1]; 412 u8 flow_table_modify[0x1]; 413 u8 reformat[0x1]; 414 u8 decap[0x1]; 415 u8 reserved_at_9[0x1]; 416 u8 pop_vlan[0x1]; 417 u8 push_vlan[0x1]; 418 u8 reserved_at_c[0x1]; 419 u8 pop_vlan_2[0x1]; 420 u8 push_vlan_2[0x1]; 421 u8 reformat_and_vlan_action[0x1]; 422 u8 reserved_at_10[0x1]; 423 u8 sw_owner[0x1]; 424 u8 reformat_l3_tunnel_to_l2[0x1]; 425 u8 reformat_l2_to_l3_tunnel[0x1]; 426 u8 reformat_and_modify_action[0x1]; 427 u8 ignore_flow_level[0x1]; 428 u8 reserved_at_16[0x1]; 429 u8 table_miss_action_domain[0x1]; 430 u8 termination_table[0x1]; 431 u8 reformat_and_fwd_to_table[0x1]; 432 u8 reserved_at_1a[0x2]; 433 u8 ipsec_encrypt[0x1]; 434 u8 ipsec_decrypt[0x1]; 435 u8 sw_owner_v2[0x1]; 436 u8 reserved_at_1f[0x1]; 437 438 u8 termination_table_raw_traffic[0x1]; 439 u8 reserved_at_21[0x1]; 440 u8 log_max_ft_size[0x6]; 441 u8 log_max_modify_header_context[0x8]; 442 u8 max_modify_header_actions[0x8]; 443 u8 max_ft_level[0x8]; 444 445 u8 reserved_at_40[0x6]; 446 u8 execute_aso[0x1]; 447 u8 reserved_at_47[0x19]; 448 449 u8 reserved_at_60[0x2]; 450 u8 reformat_insert[0x1]; 451 u8 reformat_remove[0x1]; 452 u8 reserver_at_64[0x14]; 453 u8 log_max_ft_num[0x8]; 454 455 u8 reserved_at_80[0x10]; 456 u8 log_max_flow_counter[0x8]; 457 u8 log_max_destination[0x8]; 458 459 u8 reserved_at_a0[0x18]; 460 u8 log_max_flow[0x8]; 461 462 u8 reserved_at_c0[0x40]; 463 464 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support; 465 466 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support; 467 }; 468 469 struct mlx5_ifc_odp_per_transport_service_cap_bits { 470 u8 send[0x1]; 471 u8 receive[0x1]; 472 u8 write[0x1]; 473 u8 read[0x1]; 474 u8 atomic[0x1]; 475 u8 srq_receive[0x1]; 476 u8 reserved_at_6[0x1a]; 477 }; 478 479 struct mlx5_ifc_fte_match_set_lyr_2_4_bits { 480 u8 smac_47_16[0x20]; 481 482 u8 smac_15_0[0x10]; 483 u8 ethertype[0x10]; 484 485 u8 dmac_47_16[0x20]; 486 487 u8 dmac_15_0[0x10]; 488 u8 first_prio[0x3]; 489 u8 first_cfi[0x1]; 490 u8 first_vid[0xc]; 491 492 u8 ip_protocol[0x8]; 493 u8 ip_dscp[0x6]; 494 u8 ip_ecn[0x2]; 495 u8 cvlan_tag[0x1]; 496 u8 svlan_tag[0x1]; 497 u8 frag[0x1]; 498 u8 ip_version[0x4]; 499 u8 tcp_flags[0x9]; 500 501 u8 tcp_sport[0x10]; 502 u8 tcp_dport[0x10]; 503 504 u8 reserved_at_c0[0x10]; 505 u8 ipv4_ihl[0x4]; 506 u8 reserved_at_c4[0x4]; 507 508 u8 ttl_hoplimit[0x8]; 509 510 u8 udp_sport[0x10]; 511 u8 udp_dport[0x10]; 512 513 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6; 514 515 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6; 516 }; 517 518 struct mlx5_ifc_nvgre_key_bits { 519 u8 hi[0x18]; 520 u8 lo[0x8]; 521 }; 522 523 union mlx5_ifc_gre_key_bits { 524 struct mlx5_ifc_nvgre_key_bits nvgre; 525 u8 key[0x20]; 526 }; 527 528 struct mlx5_ifc_fte_match_set_misc_bits { 529 u8 gre_c_present[0x1]; 530 u8 reserved_at_1[0x1]; 531 u8 gre_k_present[0x1]; 532 u8 gre_s_present[0x1]; 533 u8 source_vhca_port[0x4]; 534 u8 source_sqn[0x18]; 535 536 u8 source_eswitch_owner_vhca_id[0x10]; 537 u8 source_port[0x10]; 538 539 u8 outer_second_prio[0x3]; 540 u8 outer_second_cfi[0x1]; 541 u8 outer_second_vid[0xc]; 542 u8 inner_second_prio[0x3]; 543 u8 inner_second_cfi[0x1]; 544 u8 inner_second_vid[0xc]; 545 546 u8 outer_second_cvlan_tag[0x1]; 547 u8 inner_second_cvlan_tag[0x1]; 548 u8 outer_second_svlan_tag[0x1]; 549 u8 inner_second_svlan_tag[0x1]; 550 u8 reserved_at_64[0xc]; 551 u8 gre_protocol[0x10]; 552 553 union mlx5_ifc_gre_key_bits gre_key; 554 555 u8 vxlan_vni[0x18]; 556 u8 bth_opcode[0x8]; 557 558 u8 geneve_vni[0x18]; 559 u8 reserved_at_d8[0x6]; 560 u8 geneve_tlv_option_0_exist[0x1]; 561 u8 geneve_oam[0x1]; 562 563 u8 reserved_at_e0[0xc]; 564 u8 outer_ipv6_flow_label[0x14]; 565 566 u8 reserved_at_100[0xc]; 567 u8 inner_ipv6_flow_label[0x14]; 568 569 u8 reserved_at_120[0xa]; 570 u8 geneve_opt_len[0x6]; 571 u8 geneve_protocol_type[0x10]; 572 573 u8 reserved_at_140[0x8]; 574 u8 bth_dst_qp[0x18]; 575 u8 reserved_at_160[0x20]; 576 u8 outer_esp_spi[0x20]; 577 u8 reserved_at_1a0[0x60]; 578 }; 579 580 struct mlx5_ifc_fte_match_mpls_bits { 581 u8 mpls_label[0x14]; 582 u8 mpls_exp[0x3]; 583 u8 mpls_s_bos[0x1]; 584 u8 mpls_ttl[0x8]; 585 }; 586 587 struct mlx5_ifc_fte_match_set_misc2_bits { 588 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls; 589 590 struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls; 591 592 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre; 593 594 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp; 595 596 u8 metadata_reg_c_7[0x20]; 597 598 u8 metadata_reg_c_6[0x20]; 599 600 u8 metadata_reg_c_5[0x20]; 601 602 u8 metadata_reg_c_4[0x20]; 603 604 u8 metadata_reg_c_3[0x20]; 605 606 u8 metadata_reg_c_2[0x20]; 607 608 u8 metadata_reg_c_1[0x20]; 609 610 u8 metadata_reg_c_0[0x20]; 611 612 u8 metadata_reg_a[0x20]; 613 614 u8 reserved_at_1a0[0x60]; 615 }; 616 617 struct mlx5_ifc_fte_match_set_misc3_bits { 618 u8 inner_tcp_seq_num[0x20]; 619 620 u8 outer_tcp_seq_num[0x20]; 621 622 u8 inner_tcp_ack_num[0x20]; 623 624 u8 outer_tcp_ack_num[0x20]; 625 626 u8 reserved_at_80[0x8]; 627 u8 outer_vxlan_gpe_vni[0x18]; 628 629 u8 outer_vxlan_gpe_next_protocol[0x8]; 630 u8 outer_vxlan_gpe_flags[0x8]; 631 u8 reserved_at_b0[0x10]; 632 633 u8 icmp_header_data[0x20]; 634 635 u8 icmpv6_header_data[0x20]; 636 637 u8 icmp_type[0x8]; 638 u8 icmp_code[0x8]; 639 u8 icmpv6_type[0x8]; 640 u8 icmpv6_code[0x8]; 641 642 u8 geneve_tlv_option_0_data[0x20]; 643 644 u8 gtpu_teid[0x20]; 645 646 u8 gtpu_msg_type[0x8]; 647 u8 gtpu_msg_flags[0x8]; 648 u8 reserved_at_170[0x10]; 649 650 u8 gtpu_dw_2[0x20]; 651 652 u8 gtpu_first_ext_dw_0[0x20]; 653 654 u8 gtpu_dw_0[0x20]; 655 656 u8 reserved_at_1e0[0x20]; 657 }; 658 659 struct mlx5_ifc_fte_match_set_misc4_bits { 660 u8 prog_sample_field_value_0[0x20]; 661 662 u8 prog_sample_field_id_0[0x20]; 663 664 u8 prog_sample_field_value_1[0x20]; 665 666 u8 prog_sample_field_id_1[0x20]; 667 668 u8 prog_sample_field_value_2[0x20]; 669 670 u8 prog_sample_field_id_2[0x20]; 671 672 u8 prog_sample_field_value_3[0x20]; 673 674 u8 prog_sample_field_id_3[0x20]; 675 676 u8 reserved_at_100[0x100]; 677 }; 678 679 struct mlx5_ifc_fte_match_set_misc5_bits { 680 u8 macsec_tag_0[0x20]; 681 682 u8 macsec_tag_1[0x20]; 683 684 u8 macsec_tag_2[0x20]; 685 686 u8 macsec_tag_3[0x20]; 687 688 u8 tunnel_header_0[0x20]; 689 690 u8 tunnel_header_1[0x20]; 691 692 u8 tunnel_header_2[0x20]; 693 694 u8 tunnel_header_3[0x20]; 695 696 u8 reserved_at_100[0x100]; 697 }; 698 699 struct mlx5_ifc_cmd_pas_bits { 700 u8 pa_h[0x20]; 701 702 u8 pa_l[0x14]; 703 u8 reserved_at_34[0xc]; 704 }; 705 706 struct mlx5_ifc_uint64_bits { 707 u8 hi[0x20]; 708 709 u8 lo[0x20]; 710 }; 711 712 enum { 713 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0, 714 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7, 715 MLX5_ADS_STAT_RATE_10GBPS = 0x8, 716 MLX5_ADS_STAT_RATE_30GBPS = 0x9, 717 MLX5_ADS_STAT_RATE_5GBPS = 0xa, 718 MLX5_ADS_STAT_RATE_20GBPS = 0xb, 719 MLX5_ADS_STAT_RATE_40GBPS = 0xc, 720 MLX5_ADS_STAT_RATE_60GBPS = 0xd, 721 MLX5_ADS_STAT_RATE_80GBPS = 0xe, 722 MLX5_ADS_STAT_RATE_120GBPS = 0xf, 723 }; 724 725 struct mlx5_ifc_ads_bits { 726 u8 fl[0x1]; 727 u8 free_ar[0x1]; 728 u8 reserved_at_2[0xe]; 729 u8 pkey_index[0x10]; 730 731 u8 reserved_at_20[0x8]; 732 u8 grh[0x1]; 733 u8 mlid[0x7]; 734 u8 rlid[0x10]; 735 736 u8 ack_timeout[0x5]; 737 u8 reserved_at_45[0x3]; 738 u8 src_addr_index[0x8]; 739 u8 reserved_at_50[0x4]; 740 u8 stat_rate[0x4]; 741 u8 hop_limit[0x8]; 742 743 u8 reserved_at_60[0x4]; 744 u8 tclass[0x8]; 745 u8 flow_label[0x14]; 746 747 u8 rgid_rip[16][0x8]; 748 749 u8 reserved_at_100[0x4]; 750 u8 f_dscp[0x1]; 751 u8 f_ecn[0x1]; 752 u8 reserved_at_106[0x1]; 753 u8 f_eth_prio[0x1]; 754 u8 ecn[0x2]; 755 u8 dscp[0x6]; 756 u8 udp_sport[0x10]; 757 758 u8 dei_cfi[0x1]; 759 u8 eth_prio[0x3]; 760 u8 sl[0x4]; 761 u8 vhca_port_num[0x8]; 762 u8 rmac_47_32[0x10]; 763 764 u8 rmac_31_0[0x20]; 765 }; 766 767 struct mlx5_ifc_flow_table_nic_cap_bits { 768 u8 nic_rx_multi_path_tirs[0x1]; 769 u8 nic_rx_multi_path_tirs_fts[0x1]; 770 u8 allow_sniffer_and_nic_rx_shared_tir[0x1]; 771 u8 reserved_at_3[0x4]; 772 u8 sw_owner_reformat_supported[0x1]; 773 u8 reserved_at_8[0x18]; 774 775 u8 encap_general_header[0x1]; 776 u8 reserved_at_21[0xa]; 777 u8 log_max_packet_reformat_context[0x5]; 778 u8 reserved_at_30[0x6]; 779 u8 max_encap_header_size[0xa]; 780 u8 reserved_at_40[0x1c0]; 781 782 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive; 783 784 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_rdma; 785 786 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer; 787 788 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit; 789 790 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_rdma; 791 792 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer; 793 794 u8 reserved_at_e00[0x700]; 795 796 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_receive_rdma; 797 798 u8 reserved_at_1580[0x280]; 799 800 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_transmit_rdma; 801 802 u8 reserved_at_1880[0x780]; 803 804 u8 sw_steering_nic_rx_action_drop_icm_address[0x40]; 805 806 u8 sw_steering_nic_tx_action_drop_icm_address[0x40]; 807 808 u8 sw_steering_nic_tx_action_allow_icm_address[0x40]; 809 810 u8 reserved_at_20c0[0x5f40]; 811 }; 812 813 struct mlx5_ifc_port_selection_cap_bits { 814 u8 reserved_at_0[0x10]; 815 u8 port_select_flow_table[0x1]; 816 u8 reserved_at_11[0xf]; 817 818 u8 reserved_at_20[0x1e0]; 819 820 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_port_selection; 821 822 u8 reserved_at_400[0x7c00]; 823 }; 824 825 enum { 826 MLX5_FDB_TO_VPORT_REG_C_0 = 0x01, 827 MLX5_FDB_TO_VPORT_REG_C_1 = 0x02, 828 MLX5_FDB_TO_VPORT_REG_C_2 = 0x04, 829 MLX5_FDB_TO_VPORT_REG_C_3 = 0x08, 830 MLX5_FDB_TO_VPORT_REG_C_4 = 0x10, 831 MLX5_FDB_TO_VPORT_REG_C_5 = 0x20, 832 MLX5_FDB_TO_VPORT_REG_C_6 = 0x40, 833 MLX5_FDB_TO_VPORT_REG_C_7 = 0x80, 834 }; 835 836 struct mlx5_ifc_flow_table_eswitch_cap_bits { 837 u8 fdb_to_vport_reg_c_id[0x8]; 838 u8 reserved_at_8[0xd]; 839 u8 fdb_modify_header_fwd_to_table[0x1]; 840 u8 fdb_ipv4_ttl_modify[0x1]; 841 u8 flow_source[0x1]; 842 u8 reserved_at_18[0x2]; 843 u8 multi_fdb_encap[0x1]; 844 u8 egress_acl_forward_to_vport[0x1]; 845 u8 fdb_multi_path_to_table[0x1]; 846 u8 reserved_at_1d[0x3]; 847 848 u8 reserved_at_20[0x1e0]; 849 850 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb; 851 852 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress; 853 854 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress; 855 856 u8 reserved_at_800[0x1000]; 857 858 u8 sw_steering_fdb_action_drop_icm_address_rx[0x40]; 859 860 u8 sw_steering_fdb_action_drop_icm_address_tx[0x40]; 861 862 u8 sw_steering_uplink_icm_address_rx[0x40]; 863 864 u8 sw_steering_uplink_icm_address_tx[0x40]; 865 866 u8 reserved_at_1900[0x6700]; 867 }; 868 869 enum { 870 MLX5_COUNTER_SOURCE_ESWITCH = 0x0, 871 MLX5_COUNTER_FLOW_ESWITCH = 0x1, 872 }; 873 874 struct mlx5_ifc_e_switch_cap_bits { 875 u8 vport_svlan_strip[0x1]; 876 u8 vport_cvlan_strip[0x1]; 877 u8 vport_svlan_insert[0x1]; 878 u8 vport_cvlan_insert_if_not_exist[0x1]; 879 u8 vport_cvlan_insert_overwrite[0x1]; 880 u8 reserved_at_5[0x2]; 881 u8 esw_shared_ingress_acl[0x1]; 882 u8 esw_uplink_ingress_acl[0x1]; 883 u8 root_ft_on_other_esw[0x1]; 884 u8 reserved_at_a[0xf]; 885 u8 esw_functions_changed[0x1]; 886 u8 reserved_at_1a[0x1]; 887 u8 ecpf_vport_exists[0x1]; 888 u8 counter_eswitch_affinity[0x1]; 889 u8 merged_eswitch[0x1]; 890 u8 nic_vport_node_guid_modify[0x1]; 891 u8 nic_vport_port_guid_modify[0x1]; 892 893 u8 vxlan_encap_decap[0x1]; 894 u8 nvgre_encap_decap[0x1]; 895 u8 reserved_at_22[0x1]; 896 u8 log_max_fdb_encap_uplink[0x5]; 897 u8 reserved_at_21[0x3]; 898 u8 log_max_packet_reformat_context[0x5]; 899 u8 reserved_2b[0x6]; 900 u8 max_encap_header_size[0xa]; 901 902 u8 reserved_at_40[0xb]; 903 u8 log_max_esw_sf[0x5]; 904 u8 esw_sf_base_id[0x10]; 905 906 u8 reserved_at_60[0x7a0]; 907 908 }; 909 910 struct mlx5_ifc_qos_cap_bits { 911 u8 packet_pacing[0x1]; 912 u8 esw_scheduling[0x1]; 913 u8 esw_bw_share[0x1]; 914 u8 esw_rate_limit[0x1]; 915 u8 reserved_at_4[0x1]; 916 u8 packet_pacing_burst_bound[0x1]; 917 u8 packet_pacing_typical_size[0x1]; 918 u8 reserved_at_7[0x1]; 919 u8 nic_sq_scheduling[0x1]; 920 u8 nic_bw_share[0x1]; 921 u8 nic_rate_limit[0x1]; 922 u8 packet_pacing_uid[0x1]; 923 u8 log_esw_max_sched_depth[0x4]; 924 u8 reserved_at_10[0x10]; 925 926 u8 reserved_at_20[0xb]; 927 u8 log_max_qos_nic_queue_group[0x5]; 928 u8 reserved_at_30[0x10]; 929 930 u8 packet_pacing_max_rate[0x20]; 931 932 u8 packet_pacing_min_rate[0x20]; 933 934 u8 reserved_at_80[0x10]; 935 u8 packet_pacing_rate_table_size[0x10]; 936 937 u8 esw_element_type[0x10]; 938 u8 esw_tsar_type[0x10]; 939 940 u8 reserved_at_c0[0x10]; 941 u8 max_qos_para_vport[0x10]; 942 943 u8 max_tsar_bw_share[0x20]; 944 945 u8 reserved_at_100[0x20]; 946 947 u8 reserved_at_120[0x3]; 948 u8 log_meter_aso_granularity[0x5]; 949 u8 reserved_at_128[0x3]; 950 u8 log_meter_aso_max_alloc[0x5]; 951 u8 reserved_at_130[0x3]; 952 u8 log_max_num_meter_aso[0x5]; 953 u8 reserved_at_138[0x8]; 954 955 u8 reserved_at_140[0x6c0]; 956 }; 957 958 struct mlx5_ifc_debug_cap_bits { 959 u8 core_dump_general[0x1]; 960 u8 core_dump_qp[0x1]; 961 u8 reserved_at_2[0x7]; 962 u8 resource_dump[0x1]; 963 u8 reserved_at_a[0x16]; 964 965 u8 reserved_at_20[0x2]; 966 u8 stall_detect[0x1]; 967 u8 reserved_at_23[0x1d]; 968 969 u8 reserved_at_40[0x7c0]; 970 }; 971 972 struct mlx5_ifc_per_protocol_networking_offload_caps_bits { 973 u8 csum_cap[0x1]; 974 u8 vlan_cap[0x1]; 975 u8 lro_cap[0x1]; 976 u8 lro_psh_flag[0x1]; 977 u8 lro_time_stamp[0x1]; 978 u8 reserved_at_5[0x2]; 979 u8 wqe_vlan_insert[0x1]; 980 u8 self_lb_en_modifiable[0x1]; 981 u8 reserved_at_9[0x2]; 982 u8 max_lso_cap[0x5]; 983 u8 multi_pkt_send_wqe[0x2]; 984 u8 wqe_inline_mode[0x2]; 985 u8 rss_ind_tbl_cap[0x4]; 986 u8 reg_umr_sq[0x1]; 987 u8 scatter_fcs[0x1]; 988 u8 enhanced_multi_pkt_send_wqe[0x1]; 989 u8 tunnel_lso_const_out_ip_id[0x1]; 990 u8 tunnel_lro_gre[0x1]; 991 u8 tunnel_lro_vxlan[0x1]; 992 u8 tunnel_stateless_gre[0x1]; 993 u8 tunnel_stateless_vxlan[0x1]; 994 995 u8 swp[0x1]; 996 u8 swp_csum[0x1]; 997 u8 swp_lso[0x1]; 998 u8 cqe_checksum_full[0x1]; 999 u8 tunnel_stateless_geneve_tx[0x1]; 1000 u8 tunnel_stateless_mpls_over_udp[0x1]; 1001 u8 tunnel_stateless_mpls_over_gre[0x1]; 1002 u8 tunnel_stateless_vxlan_gpe[0x1]; 1003 u8 tunnel_stateless_ipv4_over_vxlan[0x1]; 1004 u8 tunnel_stateless_ip_over_ip[0x1]; 1005 u8 insert_trailer[0x1]; 1006 u8 reserved_at_2b[0x1]; 1007 u8 tunnel_stateless_ip_over_ip_rx[0x1]; 1008 u8 tunnel_stateless_ip_over_ip_tx[0x1]; 1009 u8 reserved_at_2e[0x2]; 1010 u8 max_vxlan_udp_ports[0x8]; 1011 u8 reserved_at_38[0x6]; 1012 u8 max_geneve_opt_len[0x1]; 1013 u8 tunnel_stateless_geneve_rx[0x1]; 1014 1015 u8 reserved_at_40[0x10]; 1016 u8 lro_min_mss_size[0x10]; 1017 1018 u8 reserved_at_60[0x120]; 1019 1020 u8 lro_timer_supported_periods[4][0x20]; 1021 1022 u8 reserved_at_200[0x600]; 1023 }; 1024 1025 enum { 1026 MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING = 0x0, 1027 MLX5_TIMESTAMP_FORMAT_CAP_REAL_TIME = 0x1, 1028 MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING_AND_REAL_TIME = 0x2, 1029 }; 1030 1031 struct mlx5_ifc_roce_cap_bits { 1032 u8 roce_apm[0x1]; 1033 u8 reserved_at_1[0x3]; 1034 u8 sw_r_roce_src_udp_port[0x1]; 1035 u8 fl_rc_qp_when_roce_disabled[0x1]; 1036 u8 fl_rc_qp_when_roce_enabled[0x1]; 1037 u8 reserved_at_7[0x17]; 1038 u8 qp_ts_format[0x2]; 1039 1040 u8 reserved_at_20[0x60]; 1041 1042 u8 reserved_at_80[0xc]; 1043 u8 l3_type[0x4]; 1044 u8 reserved_at_90[0x8]; 1045 u8 roce_version[0x8]; 1046 1047 u8 reserved_at_a0[0x10]; 1048 u8 r_roce_dest_udp_port[0x10]; 1049 1050 u8 r_roce_max_src_udp_port[0x10]; 1051 u8 r_roce_min_src_udp_port[0x10]; 1052 1053 u8 reserved_at_e0[0x10]; 1054 u8 roce_address_table_size[0x10]; 1055 1056 u8 reserved_at_100[0x700]; 1057 }; 1058 1059 struct mlx5_ifc_sync_steering_in_bits { 1060 u8 opcode[0x10]; 1061 u8 uid[0x10]; 1062 1063 u8 reserved_at_20[0x10]; 1064 u8 op_mod[0x10]; 1065 1066 u8 reserved_at_40[0xc0]; 1067 }; 1068 1069 struct mlx5_ifc_sync_steering_out_bits { 1070 u8 status[0x8]; 1071 u8 reserved_at_8[0x18]; 1072 1073 u8 syndrome[0x20]; 1074 1075 u8 reserved_at_40[0x40]; 1076 }; 1077 1078 struct mlx5_ifc_device_mem_cap_bits { 1079 u8 memic[0x1]; 1080 u8 reserved_at_1[0x1f]; 1081 1082 u8 reserved_at_20[0xb]; 1083 u8 log_min_memic_alloc_size[0x5]; 1084 u8 reserved_at_30[0x8]; 1085 u8 log_max_memic_addr_alignment[0x8]; 1086 1087 u8 memic_bar_start_addr[0x40]; 1088 1089 u8 memic_bar_size[0x20]; 1090 1091 u8 max_memic_size[0x20]; 1092 1093 u8 steering_sw_icm_start_address[0x40]; 1094 1095 u8 reserved_at_100[0x8]; 1096 u8 log_header_modify_sw_icm_size[0x8]; 1097 u8 reserved_at_110[0x2]; 1098 u8 log_sw_icm_alloc_granularity[0x6]; 1099 u8 log_steering_sw_icm_size[0x8]; 1100 1101 u8 reserved_at_120[0x18]; 1102 u8 log_header_modify_pattern_sw_icm_size[0x8]; 1103 1104 u8 header_modify_sw_icm_start_address[0x40]; 1105 1106 u8 reserved_at_180[0x40]; 1107 1108 u8 header_modify_pattern_sw_icm_start_address[0x40]; 1109 1110 u8 memic_operations[0x20]; 1111 1112 u8 reserved_at_220[0x5e0]; 1113 }; 1114 1115 struct mlx5_ifc_device_event_cap_bits { 1116 u8 user_affiliated_events[4][0x40]; 1117 1118 u8 user_unaffiliated_events[4][0x40]; 1119 }; 1120 1121 struct mlx5_ifc_virtio_emulation_cap_bits { 1122 u8 desc_tunnel_offload_type[0x1]; 1123 u8 eth_frame_offload_type[0x1]; 1124 u8 virtio_version_1_0[0x1]; 1125 u8 device_features_bits_mask[0xd]; 1126 u8 event_mode[0x8]; 1127 u8 virtio_queue_type[0x8]; 1128 1129 u8 max_tunnel_desc[0x10]; 1130 u8 reserved_at_30[0x3]; 1131 u8 log_doorbell_stride[0x5]; 1132 u8 reserved_at_38[0x3]; 1133 u8 log_doorbell_bar_size[0x5]; 1134 1135 u8 doorbell_bar_offset[0x40]; 1136 1137 u8 max_emulated_devices[0x8]; 1138 u8 max_num_virtio_queues[0x18]; 1139 1140 u8 reserved_at_a0[0x60]; 1141 1142 u8 umem_1_buffer_param_a[0x20]; 1143 1144 u8 umem_1_buffer_param_b[0x20]; 1145 1146 u8 umem_2_buffer_param_a[0x20]; 1147 1148 u8 umem_2_buffer_param_b[0x20]; 1149 1150 u8 umem_3_buffer_param_a[0x20]; 1151 1152 u8 umem_3_buffer_param_b[0x20]; 1153 1154 u8 reserved_at_1c0[0x640]; 1155 }; 1156 1157 enum { 1158 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0, 1159 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2, 1160 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4, 1161 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8, 1162 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10, 1163 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20, 1164 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40, 1165 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80, 1166 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100, 1167 }; 1168 1169 enum { 1170 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1, 1171 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2, 1172 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4, 1173 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8, 1174 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10, 1175 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20, 1176 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40, 1177 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80, 1178 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100, 1179 }; 1180 1181 struct mlx5_ifc_atomic_caps_bits { 1182 u8 reserved_at_0[0x40]; 1183 1184 u8 atomic_req_8B_endianness_mode[0x2]; 1185 u8 reserved_at_42[0x4]; 1186 u8 supported_atomic_req_8B_endianness_mode_1[0x1]; 1187 1188 u8 reserved_at_47[0x19]; 1189 1190 u8 reserved_at_60[0x20]; 1191 1192 u8 reserved_at_80[0x10]; 1193 u8 atomic_operations[0x10]; 1194 1195 u8 reserved_at_a0[0x10]; 1196 u8 atomic_size_qp[0x10]; 1197 1198 u8 reserved_at_c0[0x10]; 1199 u8 atomic_size_dc[0x10]; 1200 1201 u8 reserved_at_e0[0x720]; 1202 }; 1203 1204 struct mlx5_ifc_odp_cap_bits { 1205 u8 reserved_at_0[0x40]; 1206 1207 u8 sig[0x1]; 1208 u8 reserved_at_41[0x1f]; 1209 1210 u8 reserved_at_60[0x20]; 1211 1212 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps; 1213 1214 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps; 1215 1216 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps; 1217 1218 struct mlx5_ifc_odp_per_transport_service_cap_bits xrc_odp_caps; 1219 1220 struct mlx5_ifc_odp_per_transport_service_cap_bits dc_odp_caps; 1221 1222 u8 reserved_at_120[0x6E0]; 1223 }; 1224 1225 struct mlx5_ifc_calc_op { 1226 u8 reserved_at_0[0x10]; 1227 u8 reserved_at_10[0x9]; 1228 u8 op_swap_endianness[0x1]; 1229 u8 op_min[0x1]; 1230 u8 op_xor[0x1]; 1231 u8 op_or[0x1]; 1232 u8 op_and[0x1]; 1233 u8 op_max[0x1]; 1234 u8 op_add[0x1]; 1235 }; 1236 1237 struct mlx5_ifc_vector_calc_cap_bits { 1238 u8 calc_matrix[0x1]; 1239 u8 reserved_at_1[0x1f]; 1240 u8 reserved_at_20[0x8]; 1241 u8 max_vec_count[0x8]; 1242 u8 reserved_at_30[0xd]; 1243 u8 max_chunk_size[0x3]; 1244 struct mlx5_ifc_calc_op calc0; 1245 struct mlx5_ifc_calc_op calc1; 1246 struct mlx5_ifc_calc_op calc2; 1247 struct mlx5_ifc_calc_op calc3; 1248 1249 u8 reserved_at_c0[0x720]; 1250 }; 1251 1252 struct mlx5_ifc_tls_cap_bits { 1253 u8 tls_1_2_aes_gcm_128[0x1]; 1254 u8 tls_1_3_aes_gcm_128[0x1]; 1255 u8 tls_1_2_aes_gcm_256[0x1]; 1256 u8 tls_1_3_aes_gcm_256[0x1]; 1257 u8 reserved_at_4[0x1c]; 1258 1259 u8 reserved_at_20[0x7e0]; 1260 }; 1261 1262 struct mlx5_ifc_ipsec_cap_bits { 1263 u8 ipsec_full_offload[0x1]; 1264 u8 ipsec_crypto_offload[0x1]; 1265 u8 ipsec_esn[0x1]; 1266 u8 ipsec_crypto_esp_aes_gcm_256_encrypt[0x1]; 1267 u8 ipsec_crypto_esp_aes_gcm_128_encrypt[0x1]; 1268 u8 ipsec_crypto_esp_aes_gcm_256_decrypt[0x1]; 1269 u8 ipsec_crypto_esp_aes_gcm_128_decrypt[0x1]; 1270 u8 reserved_at_7[0x4]; 1271 u8 log_max_ipsec_offload[0x5]; 1272 u8 reserved_at_10[0x10]; 1273 1274 u8 min_log_ipsec_full_replay_window[0x8]; 1275 u8 max_log_ipsec_full_replay_window[0x8]; 1276 u8 reserved_at_30[0x7d0]; 1277 }; 1278 1279 enum { 1280 MLX5_WQ_TYPE_LINKED_LIST = 0x0, 1281 MLX5_WQ_TYPE_CYCLIC = 0x1, 1282 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2, 1283 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3, 1284 }; 1285 1286 enum { 1287 MLX5_WQ_END_PAD_MODE_NONE = 0x0, 1288 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1, 1289 }; 1290 1291 enum { 1292 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0, 1293 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1, 1294 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2, 1295 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3, 1296 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4, 1297 }; 1298 1299 enum { 1300 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0, 1301 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1, 1302 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2, 1303 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3, 1304 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4, 1305 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5, 1306 }; 1307 1308 enum { 1309 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0, 1310 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1, 1311 }; 1312 1313 enum { 1314 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0, 1315 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1, 1316 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3, 1317 }; 1318 1319 enum { 1320 MLX5_CAP_PORT_TYPE_IB = 0x0, 1321 MLX5_CAP_PORT_TYPE_ETH = 0x1, 1322 }; 1323 1324 enum { 1325 MLX5_CAP_UMR_FENCE_STRONG = 0x0, 1326 MLX5_CAP_UMR_FENCE_SMALL = 0x1, 1327 MLX5_CAP_UMR_FENCE_NONE = 0x2, 1328 }; 1329 1330 enum { 1331 MLX5_FLEX_PARSER_GENEVE_ENABLED = 1 << 3, 1332 MLX5_FLEX_PARSER_MPLS_OVER_GRE_ENABLED = 1 << 4, 1333 MLX5_FLEX_PARSER_MPLS_OVER_UDP_ENABLED = 1 << 5, 1334 MLX5_FLEX_PARSER_VXLAN_GPE_ENABLED = 1 << 7, 1335 MLX5_FLEX_PARSER_ICMP_V4_ENABLED = 1 << 8, 1336 MLX5_FLEX_PARSER_ICMP_V6_ENABLED = 1 << 9, 1337 MLX5_FLEX_PARSER_GENEVE_TLV_OPTION_0_ENABLED = 1 << 10, 1338 MLX5_FLEX_PARSER_GTPU_ENABLED = 1 << 11, 1339 MLX5_FLEX_PARSER_GTPU_DW_2_ENABLED = 1 << 16, 1340 MLX5_FLEX_PARSER_GTPU_FIRST_EXT_DW_0_ENABLED = 1 << 17, 1341 MLX5_FLEX_PARSER_GTPU_DW_0_ENABLED = 1 << 18, 1342 MLX5_FLEX_PARSER_GTPU_TEID_ENABLED = 1 << 19, 1343 }; 1344 1345 enum { 1346 MLX5_UCTX_CAP_RAW_TX = 1UL << 0, 1347 MLX5_UCTX_CAP_INTERNAL_DEV_RES = 1UL << 1, 1348 }; 1349 1350 #define MLX5_FC_BULK_SIZE_FACTOR 128 1351 1352 enum mlx5_fc_bulk_alloc_bitmask { 1353 MLX5_FC_BULK_128 = (1 << 0), 1354 MLX5_FC_BULK_256 = (1 << 1), 1355 MLX5_FC_BULK_512 = (1 << 2), 1356 MLX5_FC_BULK_1024 = (1 << 3), 1357 MLX5_FC_BULK_2048 = (1 << 4), 1358 MLX5_FC_BULK_4096 = (1 << 5), 1359 MLX5_FC_BULK_8192 = (1 << 6), 1360 MLX5_FC_BULK_16384 = (1 << 7), 1361 }; 1362 1363 #define MLX5_FC_BULK_NUM_FCS(fc_enum) (MLX5_FC_BULK_SIZE_FACTOR * (fc_enum)) 1364 1365 #define MLX5_FT_MAX_MULTIPATH_LEVEL 63 1366 1367 enum { 1368 MLX5_STEERING_FORMAT_CONNECTX_5 = 0, 1369 MLX5_STEERING_FORMAT_CONNECTX_6DX = 1, 1370 MLX5_STEERING_FORMAT_CONNECTX_7 = 2, 1371 }; 1372 1373 struct mlx5_ifc_cmd_hca_cap_bits { 1374 u8 reserved_at_0[0x1f]; 1375 u8 vhca_resource_manager[0x1]; 1376 1377 u8 hca_cap_2[0x1]; 1378 u8 create_lag_when_not_master_up[0x1]; 1379 u8 dtor[0x1]; 1380 u8 event_on_vhca_state_teardown_request[0x1]; 1381 u8 event_on_vhca_state_in_use[0x1]; 1382 u8 event_on_vhca_state_active[0x1]; 1383 u8 event_on_vhca_state_allocated[0x1]; 1384 u8 event_on_vhca_state_invalid[0x1]; 1385 u8 reserved_at_28[0x8]; 1386 u8 vhca_id[0x10]; 1387 1388 u8 reserved_at_40[0x40]; 1389 1390 u8 log_max_srq_sz[0x8]; 1391 u8 log_max_qp_sz[0x8]; 1392 u8 event_cap[0x1]; 1393 u8 reserved_at_91[0x2]; 1394 u8 isolate_vl_tc_new[0x1]; 1395 u8 reserved_at_94[0x4]; 1396 u8 prio_tag_required[0x1]; 1397 u8 reserved_at_99[0x2]; 1398 u8 log_max_qp[0x5]; 1399 1400 u8 reserved_at_a0[0x3]; 1401 u8 ece_support[0x1]; 1402 u8 reserved_at_a4[0x5]; 1403 u8 reg_c_preserve[0x1]; 1404 u8 reserved_at_aa[0x1]; 1405 u8 log_max_srq[0x5]; 1406 u8 reserved_at_b0[0x1]; 1407 u8 uplink_follow[0x1]; 1408 u8 ts_cqe_to_dest_cqn[0x1]; 1409 u8 reserved_at_b3[0x7]; 1410 u8 shampo[0x1]; 1411 u8 reserved_at_bb[0x5]; 1412 1413 u8 max_sgl_for_optimized_performance[0x8]; 1414 u8 log_max_cq_sz[0x8]; 1415 u8 relaxed_ordering_write_umr[0x1]; 1416 u8 relaxed_ordering_read_umr[0x1]; 1417 u8 reserved_at_d2[0x7]; 1418 u8 virtio_net_device_emualtion_manager[0x1]; 1419 u8 virtio_blk_device_emualtion_manager[0x1]; 1420 u8 log_max_cq[0x5]; 1421 1422 u8 log_max_eq_sz[0x8]; 1423 u8 relaxed_ordering_write[0x1]; 1424 u8 relaxed_ordering_read[0x1]; 1425 u8 log_max_mkey[0x6]; 1426 u8 reserved_at_f0[0x8]; 1427 u8 dump_fill_mkey[0x1]; 1428 u8 reserved_at_f9[0x2]; 1429 u8 fast_teardown[0x1]; 1430 u8 log_max_eq[0x4]; 1431 1432 u8 max_indirection[0x8]; 1433 u8 fixed_buffer_size[0x1]; 1434 u8 log_max_mrw_sz[0x7]; 1435 u8 force_teardown[0x1]; 1436 u8 reserved_at_111[0x1]; 1437 u8 log_max_bsf_list_size[0x6]; 1438 u8 umr_extended_translation_offset[0x1]; 1439 u8 null_mkey[0x1]; 1440 u8 log_max_klm_list_size[0x6]; 1441 1442 u8 reserved_at_120[0xa]; 1443 u8 log_max_ra_req_dc[0x6]; 1444 u8 reserved_at_130[0x9]; 1445 u8 vnic_env_cq_overrun[0x1]; 1446 u8 log_max_ra_res_dc[0x6]; 1447 1448 u8 reserved_at_140[0x5]; 1449 u8 release_all_pages[0x1]; 1450 u8 must_not_use[0x1]; 1451 u8 reserved_at_147[0x2]; 1452 u8 roce_accl[0x1]; 1453 u8 log_max_ra_req_qp[0x6]; 1454 u8 reserved_at_150[0xa]; 1455 u8 log_max_ra_res_qp[0x6]; 1456 1457 u8 end_pad[0x1]; 1458 u8 cc_query_allowed[0x1]; 1459 u8 cc_modify_allowed[0x1]; 1460 u8 start_pad[0x1]; 1461 u8 cache_line_128byte[0x1]; 1462 u8 reserved_at_165[0x4]; 1463 u8 rts2rts_qp_counters_set_id[0x1]; 1464 u8 reserved_at_16a[0x2]; 1465 u8 vnic_env_int_rq_oob[0x1]; 1466 u8 sbcam_reg[0x1]; 1467 u8 reserved_at_16e[0x1]; 1468 u8 qcam_reg[0x1]; 1469 u8 gid_table_size[0x10]; 1470 1471 u8 out_of_seq_cnt[0x1]; 1472 u8 vport_counters[0x1]; 1473 u8 retransmission_q_counters[0x1]; 1474 u8 debug[0x1]; 1475 u8 modify_rq_counter_set_id[0x1]; 1476 u8 rq_delay_drop[0x1]; 1477 u8 max_qp_cnt[0xa]; 1478 u8 pkey_table_size[0x10]; 1479 1480 u8 vport_group_manager[0x1]; 1481 u8 vhca_group_manager[0x1]; 1482 u8 ib_virt[0x1]; 1483 u8 eth_virt[0x1]; 1484 u8 vnic_env_queue_counters[0x1]; 1485 u8 ets[0x1]; 1486 u8 nic_flow_table[0x1]; 1487 u8 eswitch_manager[0x1]; 1488 u8 device_memory[0x1]; 1489 u8 mcam_reg[0x1]; 1490 u8 pcam_reg[0x1]; 1491 u8 local_ca_ack_delay[0x5]; 1492 u8 port_module_event[0x1]; 1493 u8 enhanced_error_q_counters[0x1]; 1494 u8 ports_check[0x1]; 1495 u8 reserved_at_1b3[0x1]; 1496 u8 disable_link_up[0x1]; 1497 u8 beacon_led[0x1]; 1498 u8 port_type[0x2]; 1499 u8 num_ports[0x8]; 1500 1501 u8 reserved_at_1c0[0x1]; 1502 u8 pps[0x1]; 1503 u8 pps_modify[0x1]; 1504 u8 log_max_msg[0x5]; 1505 u8 reserved_at_1c8[0x4]; 1506 u8 max_tc[0x4]; 1507 u8 temp_warn_event[0x1]; 1508 u8 dcbx[0x1]; 1509 u8 general_notification_event[0x1]; 1510 u8 reserved_at_1d3[0x2]; 1511 u8 fpga[0x1]; 1512 u8 rol_s[0x1]; 1513 u8 rol_g[0x1]; 1514 u8 reserved_at_1d8[0x1]; 1515 u8 wol_s[0x1]; 1516 u8 wol_g[0x1]; 1517 u8 wol_a[0x1]; 1518 u8 wol_b[0x1]; 1519 u8 wol_m[0x1]; 1520 u8 wol_u[0x1]; 1521 u8 wol_p[0x1]; 1522 1523 u8 stat_rate_support[0x10]; 1524 u8 reserved_at_1f0[0x1]; 1525 u8 pci_sync_for_fw_update_event[0x1]; 1526 u8 reserved_at_1f2[0x6]; 1527 u8 init2_lag_tx_port_affinity[0x1]; 1528 u8 reserved_at_1fa[0x3]; 1529 u8 cqe_version[0x4]; 1530 1531 u8 compact_address_vector[0x1]; 1532 u8 striding_rq[0x1]; 1533 u8 reserved_at_202[0x1]; 1534 u8 ipoib_enhanced_offloads[0x1]; 1535 u8 ipoib_basic_offloads[0x1]; 1536 u8 reserved_at_205[0x1]; 1537 u8 repeated_block_disabled[0x1]; 1538 u8 umr_modify_entity_size_disabled[0x1]; 1539 u8 umr_modify_atomic_disabled[0x1]; 1540 u8 umr_indirect_mkey_disabled[0x1]; 1541 u8 umr_fence[0x2]; 1542 u8 dc_req_scat_data_cqe[0x1]; 1543 u8 reserved_at_20d[0x2]; 1544 u8 drain_sigerr[0x1]; 1545 u8 cmdif_checksum[0x2]; 1546 u8 sigerr_cqe[0x1]; 1547 u8 reserved_at_213[0x1]; 1548 u8 wq_signature[0x1]; 1549 u8 sctr_data_cqe[0x1]; 1550 u8 reserved_at_216[0x1]; 1551 u8 sho[0x1]; 1552 u8 tph[0x1]; 1553 u8 rf[0x1]; 1554 u8 dct[0x1]; 1555 u8 qos[0x1]; 1556 u8 eth_net_offloads[0x1]; 1557 u8 roce[0x1]; 1558 u8 atomic[0x1]; 1559 u8 reserved_at_21f[0x1]; 1560 1561 u8 cq_oi[0x1]; 1562 u8 cq_resize[0x1]; 1563 u8 cq_moderation[0x1]; 1564 u8 reserved_at_223[0x3]; 1565 u8 cq_eq_remap[0x1]; 1566 u8 pg[0x1]; 1567 u8 block_lb_mc[0x1]; 1568 u8 reserved_at_229[0x1]; 1569 u8 scqe_break_moderation[0x1]; 1570 u8 cq_period_start_from_cqe[0x1]; 1571 u8 cd[0x1]; 1572 u8 reserved_at_22d[0x1]; 1573 u8 apm[0x1]; 1574 u8 vector_calc[0x1]; 1575 u8 umr_ptr_rlky[0x1]; 1576 u8 imaicl[0x1]; 1577 u8 qp_packet_based[0x1]; 1578 u8 reserved_at_233[0x3]; 1579 u8 qkv[0x1]; 1580 u8 pkv[0x1]; 1581 u8 set_deth_sqpn[0x1]; 1582 u8 reserved_at_239[0x3]; 1583 u8 xrc[0x1]; 1584 u8 ud[0x1]; 1585 u8 uc[0x1]; 1586 u8 rc[0x1]; 1587 1588 u8 uar_4k[0x1]; 1589 u8 reserved_at_241[0x9]; 1590 u8 uar_sz[0x6]; 1591 u8 port_selection_cap[0x1]; 1592 u8 reserved_at_248[0x1]; 1593 u8 umem_uid_0[0x1]; 1594 u8 reserved_at_250[0x5]; 1595 u8 log_pg_sz[0x8]; 1596 1597 u8 bf[0x1]; 1598 u8 driver_version[0x1]; 1599 u8 pad_tx_eth_packet[0x1]; 1600 u8 reserved_at_263[0x3]; 1601 u8 mkey_by_name[0x1]; 1602 u8 reserved_at_267[0x4]; 1603 1604 u8 log_bf_reg_size[0x5]; 1605 1606 u8 reserved_at_270[0x6]; 1607 u8 lag_dct[0x2]; 1608 u8 lag_tx_port_affinity[0x1]; 1609 u8 lag_native_fdb_selection[0x1]; 1610 u8 reserved_at_27a[0x1]; 1611 u8 lag_master[0x1]; 1612 u8 num_lag_ports[0x4]; 1613 1614 u8 reserved_at_280[0x10]; 1615 u8 max_wqe_sz_sq[0x10]; 1616 1617 u8 reserved_at_2a0[0x10]; 1618 u8 max_wqe_sz_rq[0x10]; 1619 1620 u8 max_flow_counter_31_16[0x10]; 1621 u8 max_wqe_sz_sq_dc[0x10]; 1622 1623 u8 reserved_at_2e0[0x7]; 1624 u8 max_qp_mcg[0x19]; 1625 1626 u8 reserved_at_300[0x10]; 1627 u8 flow_counter_bulk_alloc[0x8]; 1628 u8 log_max_mcg[0x8]; 1629 1630 u8 reserved_at_320[0x3]; 1631 u8 log_max_transport_domain[0x5]; 1632 u8 reserved_at_328[0x3]; 1633 u8 log_max_pd[0x5]; 1634 u8 reserved_at_330[0xb]; 1635 u8 log_max_xrcd[0x5]; 1636 1637 u8 nic_receive_steering_discard[0x1]; 1638 u8 receive_discard_vport_down[0x1]; 1639 u8 transmit_discard_vport_down[0x1]; 1640 u8 eq_overrun_count[0x1]; 1641 u8 reserved_at_344[0x1]; 1642 u8 invalid_command_count[0x1]; 1643 u8 quota_exceeded_count[0x1]; 1644 u8 reserved_at_347[0x1]; 1645 u8 log_max_flow_counter_bulk[0x8]; 1646 u8 max_flow_counter_15_0[0x10]; 1647 1648 1649 u8 reserved_at_360[0x3]; 1650 u8 log_max_rq[0x5]; 1651 u8 reserved_at_368[0x3]; 1652 u8 log_max_sq[0x5]; 1653 u8 reserved_at_370[0x3]; 1654 u8 log_max_tir[0x5]; 1655 u8 reserved_at_378[0x3]; 1656 u8 log_max_tis[0x5]; 1657 1658 u8 basic_cyclic_rcv_wqe[0x1]; 1659 u8 reserved_at_381[0x2]; 1660 u8 log_max_rmp[0x5]; 1661 u8 reserved_at_388[0x3]; 1662 u8 log_max_rqt[0x5]; 1663 u8 reserved_at_390[0x3]; 1664 u8 log_max_rqt_size[0x5]; 1665 u8 reserved_at_398[0x3]; 1666 u8 log_max_tis_per_sq[0x5]; 1667 1668 u8 ext_stride_num_range[0x1]; 1669 u8 roce_rw_supported[0x1]; 1670 u8 log_max_current_uc_list_wr_supported[0x1]; 1671 u8 log_max_stride_sz_rq[0x5]; 1672 u8 reserved_at_3a8[0x3]; 1673 u8 log_min_stride_sz_rq[0x5]; 1674 u8 reserved_at_3b0[0x3]; 1675 u8 log_max_stride_sz_sq[0x5]; 1676 u8 reserved_at_3b8[0x3]; 1677 u8 log_min_stride_sz_sq[0x5]; 1678 1679 u8 hairpin[0x1]; 1680 u8 reserved_at_3c1[0x2]; 1681 u8 log_max_hairpin_queues[0x5]; 1682 u8 reserved_at_3c8[0x3]; 1683 u8 log_max_hairpin_wq_data_sz[0x5]; 1684 u8 reserved_at_3d0[0x3]; 1685 u8 log_max_hairpin_num_packets[0x5]; 1686 u8 reserved_at_3d8[0x3]; 1687 u8 log_max_wq_sz[0x5]; 1688 1689 u8 nic_vport_change_event[0x1]; 1690 u8 disable_local_lb_uc[0x1]; 1691 u8 disable_local_lb_mc[0x1]; 1692 u8 log_min_hairpin_wq_data_sz[0x5]; 1693 u8 reserved_at_3e8[0x2]; 1694 u8 vhca_state[0x1]; 1695 u8 log_max_vlan_list[0x5]; 1696 u8 reserved_at_3f0[0x3]; 1697 u8 log_max_current_mc_list[0x5]; 1698 u8 reserved_at_3f8[0x3]; 1699 u8 log_max_current_uc_list[0x5]; 1700 1701 u8 general_obj_types[0x40]; 1702 1703 u8 sq_ts_format[0x2]; 1704 u8 rq_ts_format[0x2]; 1705 u8 steering_format_version[0x4]; 1706 u8 create_qp_start_hint[0x18]; 1707 1708 u8 reserved_at_460[0x3]; 1709 u8 log_max_uctx[0x5]; 1710 u8 reserved_at_468[0x2]; 1711 u8 ipsec_offload[0x1]; 1712 u8 log_max_umem[0x5]; 1713 u8 max_num_eqs[0x10]; 1714 1715 u8 reserved_at_480[0x1]; 1716 u8 tls_tx[0x1]; 1717 u8 tls_rx[0x1]; 1718 u8 log_max_l2_table[0x5]; 1719 u8 reserved_at_488[0x8]; 1720 u8 log_uar_page_sz[0x10]; 1721 1722 u8 reserved_at_4a0[0x20]; 1723 u8 device_frequency_mhz[0x20]; 1724 u8 device_frequency_khz[0x20]; 1725 1726 u8 reserved_at_500[0x20]; 1727 u8 num_of_uars_per_page[0x20]; 1728 1729 u8 flex_parser_protocols[0x20]; 1730 1731 u8 max_geneve_tlv_options[0x8]; 1732 u8 reserved_at_568[0x3]; 1733 u8 max_geneve_tlv_option_data_len[0x5]; 1734 u8 reserved_at_570[0x10]; 1735 1736 u8 reserved_at_580[0xb]; 1737 u8 log_max_dci_stream_channels[0x5]; 1738 u8 reserved_at_590[0x3]; 1739 u8 log_max_dci_errored_streams[0x5]; 1740 u8 reserved_at_598[0x8]; 1741 1742 u8 reserved_at_5a0[0x10]; 1743 u8 enhanced_cqe_compression[0x1]; 1744 u8 reserved_at_5b1[0x2]; 1745 u8 log_max_dek[0x5]; 1746 u8 reserved_at_5b8[0x4]; 1747 u8 mini_cqe_resp_stride_index[0x1]; 1748 u8 cqe_128_always[0x1]; 1749 u8 cqe_compression_128[0x1]; 1750 u8 cqe_compression[0x1]; 1751 1752 u8 cqe_compression_timeout[0x10]; 1753 u8 cqe_compression_max_num[0x10]; 1754 1755 u8 reserved_at_5e0[0x8]; 1756 u8 flex_parser_id_gtpu_dw_0[0x4]; 1757 u8 reserved_at_5ec[0x4]; 1758 u8 tag_matching[0x1]; 1759 u8 rndv_offload_rc[0x1]; 1760 u8 rndv_offload_dc[0x1]; 1761 u8 log_tag_matching_list_sz[0x5]; 1762 u8 reserved_at_5f8[0x3]; 1763 u8 log_max_xrq[0x5]; 1764 1765 u8 affiliate_nic_vport_criteria[0x8]; 1766 u8 native_port_num[0x8]; 1767 u8 num_vhca_ports[0x8]; 1768 u8 flex_parser_id_gtpu_teid[0x4]; 1769 u8 reserved_at_61c[0x2]; 1770 u8 sw_owner_id[0x1]; 1771 u8 reserved_at_61f[0x1]; 1772 1773 u8 max_num_of_monitor_counters[0x10]; 1774 u8 num_ppcnt_monitor_counters[0x10]; 1775 1776 u8 max_num_sf[0x10]; 1777 u8 num_q_monitor_counters[0x10]; 1778 1779 u8 reserved_at_660[0x20]; 1780 1781 u8 sf[0x1]; 1782 u8 sf_set_partition[0x1]; 1783 u8 reserved_at_682[0x1]; 1784 u8 log_max_sf[0x5]; 1785 u8 apu[0x1]; 1786 u8 reserved_at_689[0x4]; 1787 u8 migration[0x1]; 1788 u8 reserved_at_68e[0x2]; 1789 u8 log_min_sf_size[0x8]; 1790 u8 max_num_sf_partitions[0x8]; 1791 1792 u8 uctx_cap[0x20]; 1793 1794 u8 reserved_at_6c0[0x4]; 1795 u8 flex_parser_id_geneve_tlv_option_0[0x4]; 1796 u8 flex_parser_id_icmp_dw1[0x4]; 1797 u8 flex_parser_id_icmp_dw0[0x4]; 1798 u8 flex_parser_id_icmpv6_dw1[0x4]; 1799 u8 flex_parser_id_icmpv6_dw0[0x4]; 1800 u8 flex_parser_id_outer_first_mpls_over_gre[0x4]; 1801 u8 flex_parser_id_outer_first_mpls_over_udp_label[0x4]; 1802 1803 u8 max_num_match_definer[0x10]; 1804 u8 sf_base_id[0x10]; 1805 1806 u8 flex_parser_id_gtpu_dw_2[0x4]; 1807 u8 flex_parser_id_gtpu_first_ext_dw_0[0x4]; 1808 u8 num_total_dynamic_vf_msix[0x18]; 1809 u8 reserved_at_720[0x14]; 1810 u8 dynamic_msix_table_size[0xc]; 1811 u8 reserved_at_740[0xc]; 1812 u8 min_dynamic_vf_msix_table_size[0x4]; 1813 u8 reserved_at_750[0x4]; 1814 u8 max_dynamic_vf_msix_table_size[0xc]; 1815 1816 u8 reserved_at_760[0x20]; 1817 u8 vhca_tunnel_commands[0x40]; 1818 u8 match_definer_format_supported[0x40]; 1819 }; 1820 1821 struct mlx5_ifc_cmd_hca_cap_2_bits { 1822 u8 reserved_at_0[0xa0]; 1823 1824 u8 max_reformat_insert_size[0x8]; 1825 u8 max_reformat_insert_offset[0x8]; 1826 u8 max_reformat_remove_size[0x8]; 1827 u8 max_reformat_remove_offset[0x8]; 1828 1829 u8 reserved_at_c0[0x160]; 1830 1831 u8 reserved_at_220[0x1]; 1832 u8 sw_vhca_id_valid[0x1]; 1833 u8 sw_vhca_id[0xe]; 1834 u8 reserved_at_230[0x10]; 1835 1836 u8 reserved_at_240[0x5c0]; 1837 }; 1838 1839 enum mlx5_ifc_flow_destination_type { 1840 MLX5_IFC_FLOW_DESTINATION_TYPE_VPORT = 0x0, 1841 MLX5_IFC_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1, 1842 MLX5_IFC_FLOW_DESTINATION_TYPE_TIR = 0x2, 1843 MLX5_IFC_FLOW_DESTINATION_TYPE_FLOW_SAMPLER = 0x6, 1844 MLX5_IFC_FLOW_DESTINATION_TYPE_UPLINK = 0x8, 1845 }; 1846 1847 enum mlx5_flow_table_miss_action { 1848 MLX5_FLOW_TABLE_MISS_ACTION_DEF, 1849 MLX5_FLOW_TABLE_MISS_ACTION_FWD, 1850 MLX5_FLOW_TABLE_MISS_ACTION_SWITCH_DOMAIN, 1851 }; 1852 1853 struct mlx5_ifc_dest_format_struct_bits { 1854 u8 destination_type[0x8]; 1855 u8 destination_id[0x18]; 1856 1857 u8 destination_eswitch_owner_vhca_id_valid[0x1]; 1858 u8 packet_reformat[0x1]; 1859 u8 reserved_at_22[0xe]; 1860 u8 destination_eswitch_owner_vhca_id[0x10]; 1861 }; 1862 1863 struct mlx5_ifc_flow_counter_list_bits { 1864 u8 flow_counter_id[0x20]; 1865 1866 u8 reserved_at_20[0x20]; 1867 }; 1868 1869 struct mlx5_ifc_extended_dest_format_bits { 1870 struct mlx5_ifc_dest_format_struct_bits destination_entry; 1871 1872 u8 packet_reformat_id[0x20]; 1873 1874 u8 reserved_at_60[0x20]; 1875 }; 1876 1877 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits { 1878 struct mlx5_ifc_extended_dest_format_bits extended_dest_format; 1879 struct mlx5_ifc_flow_counter_list_bits flow_counter_list; 1880 }; 1881 1882 struct mlx5_ifc_fte_match_param_bits { 1883 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers; 1884 1885 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters; 1886 1887 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers; 1888 1889 struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2; 1890 1891 struct mlx5_ifc_fte_match_set_misc3_bits misc_parameters_3; 1892 1893 struct mlx5_ifc_fte_match_set_misc4_bits misc_parameters_4; 1894 1895 struct mlx5_ifc_fte_match_set_misc5_bits misc_parameters_5; 1896 1897 u8 reserved_at_e00[0x200]; 1898 }; 1899 1900 enum { 1901 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0, 1902 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1, 1903 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2, 1904 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3, 1905 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4, 1906 }; 1907 1908 struct mlx5_ifc_rx_hash_field_select_bits { 1909 u8 l3_prot_type[0x1]; 1910 u8 l4_prot_type[0x1]; 1911 u8 selected_fields[0x1e]; 1912 }; 1913 1914 enum { 1915 MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0, 1916 MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1, 1917 }; 1918 1919 enum { 1920 MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0, 1921 MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1, 1922 }; 1923 1924 struct mlx5_ifc_wq_bits { 1925 u8 wq_type[0x4]; 1926 u8 wq_signature[0x1]; 1927 u8 end_padding_mode[0x2]; 1928 u8 cd_slave[0x1]; 1929 u8 reserved_at_8[0x18]; 1930 1931 u8 hds_skip_first_sge[0x1]; 1932 u8 log2_hds_buf_size[0x3]; 1933 u8 reserved_at_24[0x7]; 1934 u8 page_offset[0x5]; 1935 u8 lwm[0x10]; 1936 1937 u8 reserved_at_40[0x8]; 1938 u8 pd[0x18]; 1939 1940 u8 reserved_at_60[0x8]; 1941 u8 uar_page[0x18]; 1942 1943 u8 dbr_addr[0x40]; 1944 1945 u8 hw_counter[0x20]; 1946 1947 u8 sw_counter[0x20]; 1948 1949 u8 reserved_at_100[0xc]; 1950 u8 log_wq_stride[0x4]; 1951 u8 reserved_at_110[0x3]; 1952 u8 log_wq_pg_sz[0x5]; 1953 u8 reserved_at_118[0x3]; 1954 u8 log_wq_sz[0x5]; 1955 1956 u8 dbr_umem_valid[0x1]; 1957 u8 wq_umem_valid[0x1]; 1958 u8 reserved_at_122[0x1]; 1959 u8 log_hairpin_num_packets[0x5]; 1960 u8 reserved_at_128[0x3]; 1961 u8 log_hairpin_data_sz[0x5]; 1962 1963 u8 reserved_at_130[0x4]; 1964 u8 log_wqe_num_of_strides[0x4]; 1965 u8 two_byte_shift_en[0x1]; 1966 u8 reserved_at_139[0x4]; 1967 u8 log_wqe_stride_size[0x3]; 1968 1969 u8 reserved_at_140[0x80]; 1970 1971 u8 headers_mkey[0x20]; 1972 1973 u8 shampo_enable[0x1]; 1974 u8 reserved_at_1e1[0x4]; 1975 u8 log_reservation_size[0x3]; 1976 u8 reserved_at_1e8[0x5]; 1977 u8 log_max_num_of_packets_per_reservation[0x3]; 1978 u8 reserved_at_1f0[0x6]; 1979 u8 log_headers_entry_size[0x2]; 1980 u8 reserved_at_1f8[0x4]; 1981 u8 log_headers_buffer_entry_num[0x4]; 1982 1983 u8 reserved_at_200[0x400]; 1984 1985 struct mlx5_ifc_cmd_pas_bits pas[]; 1986 }; 1987 1988 struct mlx5_ifc_rq_num_bits { 1989 u8 reserved_at_0[0x8]; 1990 u8 rq_num[0x18]; 1991 }; 1992 1993 struct mlx5_ifc_mac_address_layout_bits { 1994 u8 reserved_at_0[0x10]; 1995 u8 mac_addr_47_32[0x10]; 1996 1997 u8 mac_addr_31_0[0x20]; 1998 }; 1999 2000 struct mlx5_ifc_vlan_layout_bits { 2001 u8 reserved_at_0[0x14]; 2002 u8 vlan[0x0c]; 2003 2004 u8 reserved_at_20[0x20]; 2005 }; 2006 2007 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits { 2008 u8 reserved_at_0[0xa0]; 2009 2010 u8 min_time_between_cnps[0x20]; 2011 2012 u8 reserved_at_c0[0x12]; 2013 u8 cnp_dscp[0x6]; 2014 u8 reserved_at_d8[0x4]; 2015 u8 cnp_prio_mode[0x1]; 2016 u8 cnp_802p_prio[0x3]; 2017 2018 u8 reserved_at_e0[0x720]; 2019 }; 2020 2021 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits { 2022 u8 reserved_at_0[0x60]; 2023 2024 u8 reserved_at_60[0x4]; 2025 u8 clamp_tgt_rate[0x1]; 2026 u8 reserved_at_65[0x3]; 2027 u8 clamp_tgt_rate_after_time_inc[0x1]; 2028 u8 reserved_at_69[0x17]; 2029 2030 u8 reserved_at_80[0x20]; 2031 2032 u8 rpg_time_reset[0x20]; 2033 2034 u8 rpg_byte_reset[0x20]; 2035 2036 u8 rpg_threshold[0x20]; 2037 2038 u8 rpg_max_rate[0x20]; 2039 2040 u8 rpg_ai_rate[0x20]; 2041 2042 u8 rpg_hai_rate[0x20]; 2043 2044 u8 rpg_gd[0x20]; 2045 2046 u8 rpg_min_dec_fac[0x20]; 2047 2048 u8 rpg_min_rate[0x20]; 2049 2050 u8 reserved_at_1c0[0xe0]; 2051 2052 u8 rate_to_set_on_first_cnp[0x20]; 2053 2054 u8 dce_tcp_g[0x20]; 2055 2056 u8 dce_tcp_rtt[0x20]; 2057 2058 u8 rate_reduce_monitor_period[0x20]; 2059 2060 u8 reserved_at_320[0x20]; 2061 2062 u8 initial_alpha_value[0x20]; 2063 2064 u8 reserved_at_360[0x4a0]; 2065 }; 2066 2067 struct mlx5_ifc_cong_control_802_1qau_rp_bits { 2068 u8 reserved_at_0[0x80]; 2069 2070 u8 rppp_max_rps[0x20]; 2071 2072 u8 rpg_time_reset[0x20]; 2073 2074 u8 rpg_byte_reset[0x20]; 2075 2076 u8 rpg_threshold[0x20]; 2077 2078 u8 rpg_max_rate[0x20]; 2079 2080 u8 rpg_ai_rate[0x20]; 2081 2082 u8 rpg_hai_rate[0x20]; 2083 2084 u8 rpg_gd[0x20]; 2085 2086 u8 rpg_min_dec_fac[0x20]; 2087 2088 u8 rpg_min_rate[0x20]; 2089 2090 u8 reserved_at_1c0[0x640]; 2091 }; 2092 2093 enum { 2094 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1, 2095 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2, 2096 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4, 2097 }; 2098 2099 struct mlx5_ifc_resize_field_select_bits { 2100 u8 resize_field_select[0x20]; 2101 }; 2102 2103 struct mlx5_ifc_resource_dump_bits { 2104 u8 more_dump[0x1]; 2105 u8 inline_dump[0x1]; 2106 u8 reserved_at_2[0xa]; 2107 u8 seq_num[0x4]; 2108 u8 segment_type[0x10]; 2109 2110 u8 reserved_at_20[0x10]; 2111 u8 vhca_id[0x10]; 2112 2113 u8 index1[0x20]; 2114 2115 u8 index2[0x20]; 2116 2117 u8 num_of_obj1[0x10]; 2118 u8 num_of_obj2[0x10]; 2119 2120 u8 reserved_at_a0[0x20]; 2121 2122 u8 device_opaque[0x40]; 2123 2124 u8 mkey[0x20]; 2125 2126 u8 size[0x20]; 2127 2128 u8 address[0x40]; 2129 2130 u8 inline_data[52][0x20]; 2131 }; 2132 2133 struct mlx5_ifc_resource_dump_menu_record_bits { 2134 u8 reserved_at_0[0x4]; 2135 u8 num_of_obj2_supports_active[0x1]; 2136 u8 num_of_obj2_supports_all[0x1]; 2137 u8 must_have_num_of_obj2[0x1]; 2138 u8 support_num_of_obj2[0x1]; 2139 u8 num_of_obj1_supports_active[0x1]; 2140 u8 num_of_obj1_supports_all[0x1]; 2141 u8 must_have_num_of_obj1[0x1]; 2142 u8 support_num_of_obj1[0x1]; 2143 u8 must_have_index2[0x1]; 2144 u8 support_index2[0x1]; 2145 u8 must_have_index1[0x1]; 2146 u8 support_index1[0x1]; 2147 u8 segment_type[0x10]; 2148 2149 u8 segment_name[4][0x20]; 2150 2151 u8 index1_name[4][0x20]; 2152 2153 u8 index2_name[4][0x20]; 2154 }; 2155 2156 struct mlx5_ifc_resource_dump_segment_header_bits { 2157 u8 length_dw[0x10]; 2158 u8 segment_type[0x10]; 2159 }; 2160 2161 struct mlx5_ifc_resource_dump_command_segment_bits { 2162 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2163 2164 u8 segment_called[0x10]; 2165 u8 vhca_id[0x10]; 2166 2167 u8 index1[0x20]; 2168 2169 u8 index2[0x20]; 2170 2171 u8 num_of_obj1[0x10]; 2172 u8 num_of_obj2[0x10]; 2173 }; 2174 2175 struct mlx5_ifc_resource_dump_error_segment_bits { 2176 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2177 2178 u8 reserved_at_20[0x10]; 2179 u8 syndrome_id[0x10]; 2180 2181 u8 reserved_at_40[0x40]; 2182 2183 u8 error[8][0x20]; 2184 }; 2185 2186 struct mlx5_ifc_resource_dump_info_segment_bits { 2187 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2188 2189 u8 reserved_at_20[0x18]; 2190 u8 dump_version[0x8]; 2191 2192 u8 hw_version[0x20]; 2193 2194 u8 fw_version[0x20]; 2195 }; 2196 2197 struct mlx5_ifc_resource_dump_menu_segment_bits { 2198 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2199 2200 u8 reserved_at_20[0x10]; 2201 u8 num_of_records[0x10]; 2202 2203 struct mlx5_ifc_resource_dump_menu_record_bits record[]; 2204 }; 2205 2206 struct mlx5_ifc_resource_dump_resource_segment_bits { 2207 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2208 2209 u8 reserved_at_20[0x20]; 2210 2211 u8 index1[0x20]; 2212 2213 u8 index2[0x20]; 2214 2215 u8 payload[][0x20]; 2216 }; 2217 2218 struct mlx5_ifc_resource_dump_terminate_segment_bits { 2219 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2220 }; 2221 2222 struct mlx5_ifc_menu_resource_dump_response_bits { 2223 struct mlx5_ifc_resource_dump_info_segment_bits info; 2224 struct mlx5_ifc_resource_dump_command_segment_bits cmd; 2225 struct mlx5_ifc_resource_dump_menu_segment_bits menu; 2226 struct mlx5_ifc_resource_dump_terminate_segment_bits terminate; 2227 }; 2228 2229 enum { 2230 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1, 2231 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2, 2232 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4, 2233 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8, 2234 }; 2235 2236 struct mlx5_ifc_modify_field_select_bits { 2237 u8 modify_field_select[0x20]; 2238 }; 2239 2240 struct mlx5_ifc_field_select_r_roce_np_bits { 2241 u8 field_select_r_roce_np[0x20]; 2242 }; 2243 2244 struct mlx5_ifc_field_select_r_roce_rp_bits { 2245 u8 field_select_r_roce_rp[0x20]; 2246 }; 2247 2248 enum { 2249 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4, 2250 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8, 2251 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10, 2252 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20, 2253 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40, 2254 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80, 2255 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100, 2256 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200, 2257 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400, 2258 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800, 2259 }; 2260 2261 struct mlx5_ifc_field_select_802_1qau_rp_bits { 2262 u8 field_select_8021qaurp[0x20]; 2263 }; 2264 2265 struct mlx5_ifc_phys_layer_cntrs_bits { 2266 u8 time_since_last_clear_high[0x20]; 2267 2268 u8 time_since_last_clear_low[0x20]; 2269 2270 u8 symbol_errors_high[0x20]; 2271 2272 u8 symbol_errors_low[0x20]; 2273 2274 u8 sync_headers_errors_high[0x20]; 2275 2276 u8 sync_headers_errors_low[0x20]; 2277 2278 u8 edpl_bip_errors_lane0_high[0x20]; 2279 2280 u8 edpl_bip_errors_lane0_low[0x20]; 2281 2282 u8 edpl_bip_errors_lane1_high[0x20]; 2283 2284 u8 edpl_bip_errors_lane1_low[0x20]; 2285 2286 u8 edpl_bip_errors_lane2_high[0x20]; 2287 2288 u8 edpl_bip_errors_lane2_low[0x20]; 2289 2290 u8 edpl_bip_errors_lane3_high[0x20]; 2291 2292 u8 edpl_bip_errors_lane3_low[0x20]; 2293 2294 u8 fc_fec_corrected_blocks_lane0_high[0x20]; 2295 2296 u8 fc_fec_corrected_blocks_lane0_low[0x20]; 2297 2298 u8 fc_fec_corrected_blocks_lane1_high[0x20]; 2299 2300 u8 fc_fec_corrected_blocks_lane1_low[0x20]; 2301 2302 u8 fc_fec_corrected_blocks_lane2_high[0x20]; 2303 2304 u8 fc_fec_corrected_blocks_lane2_low[0x20]; 2305 2306 u8 fc_fec_corrected_blocks_lane3_high[0x20]; 2307 2308 u8 fc_fec_corrected_blocks_lane3_low[0x20]; 2309 2310 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20]; 2311 2312 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20]; 2313 2314 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20]; 2315 2316 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20]; 2317 2318 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20]; 2319 2320 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20]; 2321 2322 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20]; 2323 2324 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20]; 2325 2326 u8 rs_fec_corrected_blocks_high[0x20]; 2327 2328 u8 rs_fec_corrected_blocks_low[0x20]; 2329 2330 u8 rs_fec_uncorrectable_blocks_high[0x20]; 2331 2332 u8 rs_fec_uncorrectable_blocks_low[0x20]; 2333 2334 u8 rs_fec_no_errors_blocks_high[0x20]; 2335 2336 u8 rs_fec_no_errors_blocks_low[0x20]; 2337 2338 u8 rs_fec_single_error_blocks_high[0x20]; 2339 2340 u8 rs_fec_single_error_blocks_low[0x20]; 2341 2342 u8 rs_fec_corrected_symbols_total_high[0x20]; 2343 2344 u8 rs_fec_corrected_symbols_total_low[0x20]; 2345 2346 u8 rs_fec_corrected_symbols_lane0_high[0x20]; 2347 2348 u8 rs_fec_corrected_symbols_lane0_low[0x20]; 2349 2350 u8 rs_fec_corrected_symbols_lane1_high[0x20]; 2351 2352 u8 rs_fec_corrected_symbols_lane1_low[0x20]; 2353 2354 u8 rs_fec_corrected_symbols_lane2_high[0x20]; 2355 2356 u8 rs_fec_corrected_symbols_lane2_low[0x20]; 2357 2358 u8 rs_fec_corrected_symbols_lane3_high[0x20]; 2359 2360 u8 rs_fec_corrected_symbols_lane3_low[0x20]; 2361 2362 u8 link_down_events[0x20]; 2363 2364 u8 successful_recovery_events[0x20]; 2365 2366 u8 reserved_at_640[0x180]; 2367 }; 2368 2369 struct mlx5_ifc_phys_layer_statistical_cntrs_bits { 2370 u8 time_since_last_clear_high[0x20]; 2371 2372 u8 time_since_last_clear_low[0x20]; 2373 2374 u8 phy_received_bits_high[0x20]; 2375 2376 u8 phy_received_bits_low[0x20]; 2377 2378 u8 phy_symbol_errors_high[0x20]; 2379 2380 u8 phy_symbol_errors_low[0x20]; 2381 2382 u8 phy_corrected_bits_high[0x20]; 2383 2384 u8 phy_corrected_bits_low[0x20]; 2385 2386 u8 phy_corrected_bits_lane0_high[0x20]; 2387 2388 u8 phy_corrected_bits_lane0_low[0x20]; 2389 2390 u8 phy_corrected_bits_lane1_high[0x20]; 2391 2392 u8 phy_corrected_bits_lane1_low[0x20]; 2393 2394 u8 phy_corrected_bits_lane2_high[0x20]; 2395 2396 u8 phy_corrected_bits_lane2_low[0x20]; 2397 2398 u8 phy_corrected_bits_lane3_high[0x20]; 2399 2400 u8 phy_corrected_bits_lane3_low[0x20]; 2401 2402 u8 reserved_at_200[0x5c0]; 2403 }; 2404 2405 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits { 2406 u8 symbol_error_counter[0x10]; 2407 2408 u8 link_error_recovery_counter[0x8]; 2409 2410 u8 link_downed_counter[0x8]; 2411 2412 u8 port_rcv_errors[0x10]; 2413 2414 u8 port_rcv_remote_physical_errors[0x10]; 2415 2416 u8 port_rcv_switch_relay_errors[0x10]; 2417 2418 u8 port_xmit_discards[0x10]; 2419 2420 u8 port_xmit_constraint_errors[0x8]; 2421 2422 u8 port_rcv_constraint_errors[0x8]; 2423 2424 u8 reserved_at_70[0x8]; 2425 2426 u8 link_overrun_errors[0x8]; 2427 2428 u8 reserved_at_80[0x10]; 2429 2430 u8 vl_15_dropped[0x10]; 2431 2432 u8 reserved_at_a0[0x80]; 2433 2434 u8 port_xmit_wait[0x20]; 2435 }; 2436 2437 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits { 2438 u8 transmit_queue_high[0x20]; 2439 2440 u8 transmit_queue_low[0x20]; 2441 2442 u8 no_buffer_discard_uc_high[0x20]; 2443 2444 u8 no_buffer_discard_uc_low[0x20]; 2445 2446 u8 reserved_at_80[0x740]; 2447 }; 2448 2449 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits { 2450 u8 wred_discard_high[0x20]; 2451 2452 u8 wred_discard_low[0x20]; 2453 2454 u8 ecn_marked_tc_high[0x20]; 2455 2456 u8 ecn_marked_tc_low[0x20]; 2457 2458 u8 reserved_at_80[0x740]; 2459 }; 2460 2461 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits { 2462 u8 rx_octets_high[0x20]; 2463 2464 u8 rx_octets_low[0x20]; 2465 2466 u8 reserved_at_40[0xc0]; 2467 2468 u8 rx_frames_high[0x20]; 2469 2470 u8 rx_frames_low[0x20]; 2471 2472 u8 tx_octets_high[0x20]; 2473 2474 u8 tx_octets_low[0x20]; 2475 2476 u8 reserved_at_180[0xc0]; 2477 2478 u8 tx_frames_high[0x20]; 2479 2480 u8 tx_frames_low[0x20]; 2481 2482 u8 rx_pause_high[0x20]; 2483 2484 u8 rx_pause_low[0x20]; 2485 2486 u8 rx_pause_duration_high[0x20]; 2487 2488 u8 rx_pause_duration_low[0x20]; 2489 2490 u8 tx_pause_high[0x20]; 2491 2492 u8 tx_pause_low[0x20]; 2493 2494 u8 tx_pause_duration_high[0x20]; 2495 2496 u8 tx_pause_duration_low[0x20]; 2497 2498 u8 rx_pause_transition_high[0x20]; 2499 2500 u8 rx_pause_transition_low[0x20]; 2501 2502 u8 rx_discards_high[0x20]; 2503 2504 u8 rx_discards_low[0x20]; 2505 2506 u8 device_stall_minor_watermark_cnt_high[0x20]; 2507 2508 u8 device_stall_minor_watermark_cnt_low[0x20]; 2509 2510 u8 device_stall_critical_watermark_cnt_high[0x20]; 2511 2512 u8 device_stall_critical_watermark_cnt_low[0x20]; 2513 2514 u8 reserved_at_480[0x340]; 2515 }; 2516 2517 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits { 2518 u8 port_transmit_wait_high[0x20]; 2519 2520 u8 port_transmit_wait_low[0x20]; 2521 2522 u8 reserved_at_40[0x100]; 2523 2524 u8 rx_buffer_almost_full_high[0x20]; 2525 2526 u8 rx_buffer_almost_full_low[0x20]; 2527 2528 u8 rx_buffer_full_high[0x20]; 2529 2530 u8 rx_buffer_full_low[0x20]; 2531 2532 u8 rx_icrc_encapsulated_high[0x20]; 2533 2534 u8 rx_icrc_encapsulated_low[0x20]; 2535 2536 u8 reserved_at_200[0x5c0]; 2537 }; 2538 2539 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits { 2540 u8 dot3stats_alignment_errors_high[0x20]; 2541 2542 u8 dot3stats_alignment_errors_low[0x20]; 2543 2544 u8 dot3stats_fcs_errors_high[0x20]; 2545 2546 u8 dot3stats_fcs_errors_low[0x20]; 2547 2548 u8 dot3stats_single_collision_frames_high[0x20]; 2549 2550 u8 dot3stats_single_collision_frames_low[0x20]; 2551 2552 u8 dot3stats_multiple_collision_frames_high[0x20]; 2553 2554 u8 dot3stats_multiple_collision_frames_low[0x20]; 2555 2556 u8 dot3stats_sqe_test_errors_high[0x20]; 2557 2558 u8 dot3stats_sqe_test_errors_low[0x20]; 2559 2560 u8 dot3stats_deferred_transmissions_high[0x20]; 2561 2562 u8 dot3stats_deferred_transmissions_low[0x20]; 2563 2564 u8 dot3stats_late_collisions_high[0x20]; 2565 2566 u8 dot3stats_late_collisions_low[0x20]; 2567 2568 u8 dot3stats_excessive_collisions_high[0x20]; 2569 2570 u8 dot3stats_excessive_collisions_low[0x20]; 2571 2572 u8 dot3stats_internal_mac_transmit_errors_high[0x20]; 2573 2574 u8 dot3stats_internal_mac_transmit_errors_low[0x20]; 2575 2576 u8 dot3stats_carrier_sense_errors_high[0x20]; 2577 2578 u8 dot3stats_carrier_sense_errors_low[0x20]; 2579 2580 u8 dot3stats_frame_too_longs_high[0x20]; 2581 2582 u8 dot3stats_frame_too_longs_low[0x20]; 2583 2584 u8 dot3stats_internal_mac_receive_errors_high[0x20]; 2585 2586 u8 dot3stats_internal_mac_receive_errors_low[0x20]; 2587 2588 u8 dot3stats_symbol_errors_high[0x20]; 2589 2590 u8 dot3stats_symbol_errors_low[0x20]; 2591 2592 u8 dot3control_in_unknown_opcodes_high[0x20]; 2593 2594 u8 dot3control_in_unknown_opcodes_low[0x20]; 2595 2596 u8 dot3in_pause_frames_high[0x20]; 2597 2598 u8 dot3in_pause_frames_low[0x20]; 2599 2600 u8 dot3out_pause_frames_high[0x20]; 2601 2602 u8 dot3out_pause_frames_low[0x20]; 2603 2604 u8 reserved_at_400[0x3c0]; 2605 }; 2606 2607 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits { 2608 u8 ether_stats_drop_events_high[0x20]; 2609 2610 u8 ether_stats_drop_events_low[0x20]; 2611 2612 u8 ether_stats_octets_high[0x20]; 2613 2614 u8 ether_stats_octets_low[0x20]; 2615 2616 u8 ether_stats_pkts_high[0x20]; 2617 2618 u8 ether_stats_pkts_low[0x20]; 2619 2620 u8 ether_stats_broadcast_pkts_high[0x20]; 2621 2622 u8 ether_stats_broadcast_pkts_low[0x20]; 2623 2624 u8 ether_stats_multicast_pkts_high[0x20]; 2625 2626 u8 ether_stats_multicast_pkts_low[0x20]; 2627 2628 u8 ether_stats_crc_align_errors_high[0x20]; 2629 2630 u8 ether_stats_crc_align_errors_low[0x20]; 2631 2632 u8 ether_stats_undersize_pkts_high[0x20]; 2633 2634 u8 ether_stats_undersize_pkts_low[0x20]; 2635 2636 u8 ether_stats_oversize_pkts_high[0x20]; 2637 2638 u8 ether_stats_oversize_pkts_low[0x20]; 2639 2640 u8 ether_stats_fragments_high[0x20]; 2641 2642 u8 ether_stats_fragments_low[0x20]; 2643 2644 u8 ether_stats_jabbers_high[0x20]; 2645 2646 u8 ether_stats_jabbers_low[0x20]; 2647 2648 u8 ether_stats_collisions_high[0x20]; 2649 2650 u8 ether_stats_collisions_low[0x20]; 2651 2652 u8 ether_stats_pkts64octets_high[0x20]; 2653 2654 u8 ether_stats_pkts64octets_low[0x20]; 2655 2656 u8 ether_stats_pkts65to127octets_high[0x20]; 2657 2658 u8 ether_stats_pkts65to127octets_low[0x20]; 2659 2660 u8 ether_stats_pkts128to255octets_high[0x20]; 2661 2662 u8 ether_stats_pkts128to255octets_low[0x20]; 2663 2664 u8 ether_stats_pkts256to511octets_high[0x20]; 2665 2666 u8 ether_stats_pkts256to511octets_low[0x20]; 2667 2668 u8 ether_stats_pkts512to1023octets_high[0x20]; 2669 2670 u8 ether_stats_pkts512to1023octets_low[0x20]; 2671 2672 u8 ether_stats_pkts1024to1518octets_high[0x20]; 2673 2674 u8 ether_stats_pkts1024to1518octets_low[0x20]; 2675 2676 u8 ether_stats_pkts1519to2047octets_high[0x20]; 2677 2678 u8 ether_stats_pkts1519to2047octets_low[0x20]; 2679 2680 u8 ether_stats_pkts2048to4095octets_high[0x20]; 2681 2682 u8 ether_stats_pkts2048to4095octets_low[0x20]; 2683 2684 u8 ether_stats_pkts4096to8191octets_high[0x20]; 2685 2686 u8 ether_stats_pkts4096to8191octets_low[0x20]; 2687 2688 u8 ether_stats_pkts8192to10239octets_high[0x20]; 2689 2690 u8 ether_stats_pkts8192to10239octets_low[0x20]; 2691 2692 u8 reserved_at_540[0x280]; 2693 }; 2694 2695 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits { 2696 u8 if_in_octets_high[0x20]; 2697 2698 u8 if_in_octets_low[0x20]; 2699 2700 u8 if_in_ucast_pkts_high[0x20]; 2701 2702 u8 if_in_ucast_pkts_low[0x20]; 2703 2704 u8 if_in_discards_high[0x20]; 2705 2706 u8 if_in_discards_low[0x20]; 2707 2708 u8 if_in_errors_high[0x20]; 2709 2710 u8 if_in_errors_low[0x20]; 2711 2712 u8 if_in_unknown_protos_high[0x20]; 2713 2714 u8 if_in_unknown_protos_low[0x20]; 2715 2716 u8 if_out_octets_high[0x20]; 2717 2718 u8 if_out_octets_low[0x20]; 2719 2720 u8 if_out_ucast_pkts_high[0x20]; 2721 2722 u8 if_out_ucast_pkts_low[0x20]; 2723 2724 u8 if_out_discards_high[0x20]; 2725 2726 u8 if_out_discards_low[0x20]; 2727 2728 u8 if_out_errors_high[0x20]; 2729 2730 u8 if_out_errors_low[0x20]; 2731 2732 u8 if_in_multicast_pkts_high[0x20]; 2733 2734 u8 if_in_multicast_pkts_low[0x20]; 2735 2736 u8 if_in_broadcast_pkts_high[0x20]; 2737 2738 u8 if_in_broadcast_pkts_low[0x20]; 2739 2740 u8 if_out_multicast_pkts_high[0x20]; 2741 2742 u8 if_out_multicast_pkts_low[0x20]; 2743 2744 u8 if_out_broadcast_pkts_high[0x20]; 2745 2746 u8 if_out_broadcast_pkts_low[0x20]; 2747 2748 u8 reserved_at_340[0x480]; 2749 }; 2750 2751 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits { 2752 u8 a_frames_transmitted_ok_high[0x20]; 2753 2754 u8 a_frames_transmitted_ok_low[0x20]; 2755 2756 u8 a_frames_received_ok_high[0x20]; 2757 2758 u8 a_frames_received_ok_low[0x20]; 2759 2760 u8 a_frame_check_sequence_errors_high[0x20]; 2761 2762 u8 a_frame_check_sequence_errors_low[0x20]; 2763 2764 u8 a_alignment_errors_high[0x20]; 2765 2766 u8 a_alignment_errors_low[0x20]; 2767 2768 u8 a_octets_transmitted_ok_high[0x20]; 2769 2770 u8 a_octets_transmitted_ok_low[0x20]; 2771 2772 u8 a_octets_received_ok_high[0x20]; 2773 2774 u8 a_octets_received_ok_low[0x20]; 2775 2776 u8 a_multicast_frames_xmitted_ok_high[0x20]; 2777 2778 u8 a_multicast_frames_xmitted_ok_low[0x20]; 2779 2780 u8 a_broadcast_frames_xmitted_ok_high[0x20]; 2781 2782 u8 a_broadcast_frames_xmitted_ok_low[0x20]; 2783 2784 u8 a_multicast_frames_received_ok_high[0x20]; 2785 2786 u8 a_multicast_frames_received_ok_low[0x20]; 2787 2788 u8 a_broadcast_frames_received_ok_high[0x20]; 2789 2790 u8 a_broadcast_frames_received_ok_low[0x20]; 2791 2792 u8 a_in_range_length_errors_high[0x20]; 2793 2794 u8 a_in_range_length_errors_low[0x20]; 2795 2796 u8 a_out_of_range_length_field_high[0x20]; 2797 2798 u8 a_out_of_range_length_field_low[0x20]; 2799 2800 u8 a_frame_too_long_errors_high[0x20]; 2801 2802 u8 a_frame_too_long_errors_low[0x20]; 2803 2804 u8 a_symbol_error_during_carrier_high[0x20]; 2805 2806 u8 a_symbol_error_during_carrier_low[0x20]; 2807 2808 u8 a_mac_control_frames_transmitted_high[0x20]; 2809 2810 u8 a_mac_control_frames_transmitted_low[0x20]; 2811 2812 u8 a_mac_control_frames_received_high[0x20]; 2813 2814 u8 a_mac_control_frames_received_low[0x20]; 2815 2816 u8 a_unsupported_opcodes_received_high[0x20]; 2817 2818 u8 a_unsupported_opcodes_received_low[0x20]; 2819 2820 u8 a_pause_mac_ctrl_frames_received_high[0x20]; 2821 2822 u8 a_pause_mac_ctrl_frames_received_low[0x20]; 2823 2824 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20]; 2825 2826 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20]; 2827 2828 u8 reserved_at_4c0[0x300]; 2829 }; 2830 2831 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits { 2832 u8 life_time_counter_high[0x20]; 2833 2834 u8 life_time_counter_low[0x20]; 2835 2836 u8 rx_errors[0x20]; 2837 2838 u8 tx_errors[0x20]; 2839 2840 u8 l0_to_recovery_eieos[0x20]; 2841 2842 u8 l0_to_recovery_ts[0x20]; 2843 2844 u8 l0_to_recovery_framing[0x20]; 2845 2846 u8 l0_to_recovery_retrain[0x20]; 2847 2848 u8 crc_error_dllp[0x20]; 2849 2850 u8 crc_error_tlp[0x20]; 2851 2852 u8 tx_overflow_buffer_pkt_high[0x20]; 2853 2854 u8 tx_overflow_buffer_pkt_low[0x20]; 2855 2856 u8 outbound_stalled_reads[0x20]; 2857 2858 u8 outbound_stalled_writes[0x20]; 2859 2860 u8 outbound_stalled_reads_events[0x20]; 2861 2862 u8 outbound_stalled_writes_events[0x20]; 2863 2864 u8 reserved_at_200[0x5c0]; 2865 }; 2866 2867 struct mlx5_ifc_cmd_inter_comp_event_bits { 2868 u8 command_completion_vector[0x20]; 2869 2870 u8 reserved_at_20[0xc0]; 2871 }; 2872 2873 struct mlx5_ifc_stall_vl_event_bits { 2874 u8 reserved_at_0[0x18]; 2875 u8 port_num[0x1]; 2876 u8 reserved_at_19[0x3]; 2877 u8 vl[0x4]; 2878 2879 u8 reserved_at_20[0xa0]; 2880 }; 2881 2882 struct mlx5_ifc_db_bf_congestion_event_bits { 2883 u8 event_subtype[0x8]; 2884 u8 reserved_at_8[0x8]; 2885 u8 congestion_level[0x8]; 2886 u8 reserved_at_18[0x8]; 2887 2888 u8 reserved_at_20[0xa0]; 2889 }; 2890 2891 struct mlx5_ifc_gpio_event_bits { 2892 u8 reserved_at_0[0x60]; 2893 2894 u8 gpio_event_hi[0x20]; 2895 2896 u8 gpio_event_lo[0x20]; 2897 2898 u8 reserved_at_a0[0x40]; 2899 }; 2900 2901 struct mlx5_ifc_port_state_change_event_bits { 2902 u8 reserved_at_0[0x40]; 2903 2904 u8 port_num[0x4]; 2905 u8 reserved_at_44[0x1c]; 2906 2907 u8 reserved_at_60[0x80]; 2908 }; 2909 2910 struct mlx5_ifc_dropped_packet_logged_bits { 2911 u8 reserved_at_0[0xe0]; 2912 }; 2913 2914 struct mlx5_ifc_default_timeout_bits { 2915 u8 to_multiplier[0x3]; 2916 u8 reserved_at_3[0x9]; 2917 u8 to_value[0x14]; 2918 }; 2919 2920 struct mlx5_ifc_dtor_reg_bits { 2921 u8 reserved_at_0[0x20]; 2922 2923 struct mlx5_ifc_default_timeout_bits pcie_toggle_to; 2924 2925 u8 reserved_at_40[0x60]; 2926 2927 struct mlx5_ifc_default_timeout_bits health_poll_to; 2928 2929 struct mlx5_ifc_default_timeout_bits full_crdump_to; 2930 2931 struct mlx5_ifc_default_timeout_bits fw_reset_to; 2932 2933 struct mlx5_ifc_default_timeout_bits flush_on_err_to; 2934 2935 struct mlx5_ifc_default_timeout_bits pci_sync_update_to; 2936 2937 struct mlx5_ifc_default_timeout_bits tear_down_to; 2938 2939 struct mlx5_ifc_default_timeout_bits fsm_reactivate_to; 2940 2941 struct mlx5_ifc_default_timeout_bits reclaim_pages_to; 2942 2943 struct mlx5_ifc_default_timeout_bits reclaim_vfs_pages_to; 2944 2945 u8 reserved_at_1c0[0x40]; 2946 }; 2947 2948 enum { 2949 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1, 2950 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2, 2951 }; 2952 2953 struct mlx5_ifc_cq_error_bits { 2954 u8 reserved_at_0[0x8]; 2955 u8 cqn[0x18]; 2956 2957 u8 reserved_at_20[0x20]; 2958 2959 u8 reserved_at_40[0x18]; 2960 u8 syndrome[0x8]; 2961 2962 u8 reserved_at_60[0x80]; 2963 }; 2964 2965 struct mlx5_ifc_rdma_page_fault_event_bits { 2966 u8 bytes_committed[0x20]; 2967 2968 u8 r_key[0x20]; 2969 2970 u8 reserved_at_40[0x10]; 2971 u8 packet_len[0x10]; 2972 2973 u8 rdma_op_len[0x20]; 2974 2975 u8 rdma_va[0x40]; 2976 2977 u8 reserved_at_c0[0x5]; 2978 u8 rdma[0x1]; 2979 u8 write[0x1]; 2980 u8 requestor[0x1]; 2981 u8 qp_number[0x18]; 2982 }; 2983 2984 struct mlx5_ifc_wqe_associated_page_fault_event_bits { 2985 u8 bytes_committed[0x20]; 2986 2987 u8 reserved_at_20[0x10]; 2988 u8 wqe_index[0x10]; 2989 2990 u8 reserved_at_40[0x10]; 2991 u8 len[0x10]; 2992 2993 u8 reserved_at_60[0x60]; 2994 2995 u8 reserved_at_c0[0x5]; 2996 u8 rdma[0x1]; 2997 u8 write_read[0x1]; 2998 u8 requestor[0x1]; 2999 u8 qpn[0x18]; 3000 }; 3001 3002 struct mlx5_ifc_qp_events_bits { 3003 u8 reserved_at_0[0xa0]; 3004 3005 u8 type[0x8]; 3006 u8 reserved_at_a8[0x18]; 3007 3008 u8 reserved_at_c0[0x8]; 3009 u8 qpn_rqn_sqn[0x18]; 3010 }; 3011 3012 struct mlx5_ifc_dct_events_bits { 3013 u8 reserved_at_0[0xc0]; 3014 3015 u8 reserved_at_c0[0x8]; 3016 u8 dct_number[0x18]; 3017 }; 3018 3019 struct mlx5_ifc_comp_event_bits { 3020 u8 reserved_at_0[0xc0]; 3021 3022 u8 reserved_at_c0[0x8]; 3023 u8 cq_number[0x18]; 3024 }; 3025 3026 enum { 3027 MLX5_QPC_STATE_RST = 0x0, 3028 MLX5_QPC_STATE_INIT = 0x1, 3029 MLX5_QPC_STATE_RTR = 0x2, 3030 MLX5_QPC_STATE_RTS = 0x3, 3031 MLX5_QPC_STATE_SQER = 0x4, 3032 MLX5_QPC_STATE_ERR = 0x6, 3033 MLX5_QPC_STATE_SQD = 0x7, 3034 MLX5_QPC_STATE_SUSPENDED = 0x9, 3035 }; 3036 3037 enum { 3038 MLX5_QPC_ST_RC = 0x0, 3039 MLX5_QPC_ST_UC = 0x1, 3040 MLX5_QPC_ST_UD = 0x2, 3041 MLX5_QPC_ST_XRC = 0x3, 3042 MLX5_QPC_ST_DCI = 0x5, 3043 MLX5_QPC_ST_QP0 = 0x7, 3044 MLX5_QPC_ST_QP1 = 0x8, 3045 MLX5_QPC_ST_RAW_DATAGRAM = 0x9, 3046 MLX5_QPC_ST_REG_UMR = 0xc, 3047 }; 3048 3049 enum { 3050 MLX5_QPC_PM_STATE_ARMED = 0x0, 3051 MLX5_QPC_PM_STATE_REARM = 0x1, 3052 MLX5_QPC_PM_STATE_RESERVED = 0x2, 3053 MLX5_QPC_PM_STATE_MIGRATED = 0x3, 3054 }; 3055 3056 enum { 3057 MLX5_QPC_OFFLOAD_TYPE_RNDV = 0x1, 3058 }; 3059 3060 enum { 3061 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0, 3062 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1, 3063 }; 3064 3065 enum { 3066 MLX5_QPC_MTU_256_BYTES = 0x1, 3067 MLX5_QPC_MTU_512_BYTES = 0x2, 3068 MLX5_QPC_MTU_1K_BYTES = 0x3, 3069 MLX5_QPC_MTU_2K_BYTES = 0x4, 3070 MLX5_QPC_MTU_4K_BYTES = 0x5, 3071 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7, 3072 }; 3073 3074 enum { 3075 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1, 3076 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2, 3077 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3, 3078 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4, 3079 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5, 3080 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6, 3081 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7, 3082 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8, 3083 }; 3084 3085 enum { 3086 MLX5_QPC_CS_REQ_DISABLE = 0x0, 3087 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11, 3088 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22, 3089 }; 3090 3091 enum { 3092 MLX5_QPC_CS_RES_DISABLE = 0x0, 3093 MLX5_QPC_CS_RES_UP_TO_32B = 0x1, 3094 MLX5_QPC_CS_RES_UP_TO_64B = 0x2, 3095 }; 3096 3097 enum { 3098 MLX5_TIMESTAMP_FORMAT_FREE_RUNNING = 0x0, 3099 MLX5_TIMESTAMP_FORMAT_DEFAULT = 0x1, 3100 MLX5_TIMESTAMP_FORMAT_REAL_TIME = 0x2, 3101 }; 3102 3103 struct mlx5_ifc_qpc_bits { 3104 u8 state[0x4]; 3105 u8 lag_tx_port_affinity[0x4]; 3106 u8 st[0x8]; 3107 u8 reserved_at_10[0x2]; 3108 u8 isolate_vl_tc[0x1]; 3109 u8 pm_state[0x2]; 3110 u8 reserved_at_15[0x1]; 3111 u8 req_e2e_credit_mode[0x2]; 3112 u8 offload_type[0x4]; 3113 u8 end_padding_mode[0x2]; 3114 u8 reserved_at_1e[0x2]; 3115 3116 u8 wq_signature[0x1]; 3117 u8 block_lb_mc[0x1]; 3118 u8 atomic_like_write_en[0x1]; 3119 u8 latency_sensitive[0x1]; 3120 u8 reserved_at_24[0x1]; 3121 u8 drain_sigerr[0x1]; 3122 u8 reserved_at_26[0x2]; 3123 u8 pd[0x18]; 3124 3125 u8 mtu[0x3]; 3126 u8 log_msg_max[0x5]; 3127 u8 reserved_at_48[0x1]; 3128 u8 log_rq_size[0x4]; 3129 u8 log_rq_stride[0x3]; 3130 u8 no_sq[0x1]; 3131 u8 log_sq_size[0x4]; 3132 u8 reserved_at_55[0x3]; 3133 u8 ts_format[0x2]; 3134 u8 reserved_at_5a[0x1]; 3135 u8 rlky[0x1]; 3136 u8 ulp_stateless_offload_mode[0x4]; 3137 3138 u8 counter_set_id[0x8]; 3139 u8 uar_page[0x18]; 3140 3141 u8 reserved_at_80[0x8]; 3142 u8 user_index[0x18]; 3143 3144 u8 reserved_at_a0[0x3]; 3145 u8 log_page_size[0x5]; 3146 u8 remote_qpn[0x18]; 3147 3148 struct mlx5_ifc_ads_bits primary_address_path; 3149 3150 struct mlx5_ifc_ads_bits secondary_address_path; 3151 3152 u8 log_ack_req_freq[0x4]; 3153 u8 reserved_at_384[0x4]; 3154 u8 log_sra_max[0x3]; 3155 u8 reserved_at_38b[0x2]; 3156 u8 retry_count[0x3]; 3157 u8 rnr_retry[0x3]; 3158 u8 reserved_at_393[0x1]; 3159 u8 fre[0x1]; 3160 u8 cur_rnr_retry[0x3]; 3161 u8 cur_retry_count[0x3]; 3162 u8 reserved_at_39b[0x5]; 3163 3164 u8 reserved_at_3a0[0x20]; 3165 3166 u8 reserved_at_3c0[0x8]; 3167 u8 next_send_psn[0x18]; 3168 3169 u8 reserved_at_3e0[0x3]; 3170 u8 log_num_dci_stream_channels[0x5]; 3171 u8 cqn_snd[0x18]; 3172 3173 u8 reserved_at_400[0x3]; 3174 u8 log_num_dci_errored_streams[0x5]; 3175 u8 deth_sqpn[0x18]; 3176 3177 u8 reserved_at_420[0x20]; 3178 3179 u8 reserved_at_440[0x8]; 3180 u8 last_acked_psn[0x18]; 3181 3182 u8 reserved_at_460[0x8]; 3183 u8 ssn[0x18]; 3184 3185 u8 reserved_at_480[0x8]; 3186 u8 log_rra_max[0x3]; 3187 u8 reserved_at_48b[0x1]; 3188 u8 atomic_mode[0x4]; 3189 u8 rre[0x1]; 3190 u8 rwe[0x1]; 3191 u8 rae[0x1]; 3192 u8 reserved_at_493[0x1]; 3193 u8 page_offset[0x6]; 3194 u8 reserved_at_49a[0x3]; 3195 u8 cd_slave_receive[0x1]; 3196 u8 cd_slave_send[0x1]; 3197 u8 cd_master[0x1]; 3198 3199 u8 reserved_at_4a0[0x3]; 3200 u8 min_rnr_nak[0x5]; 3201 u8 next_rcv_psn[0x18]; 3202 3203 u8 reserved_at_4c0[0x8]; 3204 u8 xrcd[0x18]; 3205 3206 u8 reserved_at_4e0[0x8]; 3207 u8 cqn_rcv[0x18]; 3208 3209 u8 dbr_addr[0x40]; 3210 3211 u8 q_key[0x20]; 3212 3213 u8 reserved_at_560[0x5]; 3214 u8 rq_type[0x3]; 3215 u8 srqn_rmpn_xrqn[0x18]; 3216 3217 u8 reserved_at_580[0x8]; 3218 u8 rmsn[0x18]; 3219 3220 u8 hw_sq_wqebb_counter[0x10]; 3221 u8 sw_sq_wqebb_counter[0x10]; 3222 3223 u8 hw_rq_counter[0x20]; 3224 3225 u8 sw_rq_counter[0x20]; 3226 3227 u8 reserved_at_600[0x20]; 3228 3229 u8 reserved_at_620[0xf]; 3230 u8 cgs[0x1]; 3231 u8 cs_req[0x8]; 3232 u8 cs_res[0x8]; 3233 3234 u8 dc_access_key[0x40]; 3235 3236 u8 reserved_at_680[0x3]; 3237 u8 dbr_umem_valid[0x1]; 3238 3239 u8 reserved_at_684[0xbc]; 3240 }; 3241 3242 struct mlx5_ifc_roce_addr_layout_bits { 3243 u8 source_l3_address[16][0x8]; 3244 3245 u8 reserved_at_80[0x3]; 3246 u8 vlan_valid[0x1]; 3247 u8 vlan_id[0xc]; 3248 u8 source_mac_47_32[0x10]; 3249 3250 u8 source_mac_31_0[0x20]; 3251 3252 u8 reserved_at_c0[0x14]; 3253 u8 roce_l3_type[0x4]; 3254 u8 roce_version[0x8]; 3255 3256 u8 reserved_at_e0[0x20]; 3257 }; 3258 3259 struct mlx5_ifc_shampo_cap_bits { 3260 u8 reserved_at_0[0x3]; 3261 u8 shampo_log_max_reservation_size[0x5]; 3262 u8 reserved_at_8[0x3]; 3263 u8 shampo_log_min_reservation_size[0x5]; 3264 u8 shampo_min_mss_size[0x10]; 3265 3266 u8 reserved_at_20[0x3]; 3267 u8 shampo_max_log_headers_entry_size[0x5]; 3268 u8 reserved_at_28[0x18]; 3269 3270 u8 reserved_at_40[0x7c0]; 3271 }; 3272 3273 union mlx5_ifc_hca_cap_union_bits { 3274 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap; 3275 struct mlx5_ifc_cmd_hca_cap_2_bits cmd_hca_cap_2; 3276 struct mlx5_ifc_odp_cap_bits odp_cap; 3277 struct mlx5_ifc_atomic_caps_bits atomic_caps; 3278 struct mlx5_ifc_roce_cap_bits roce_cap; 3279 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps; 3280 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap; 3281 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap; 3282 struct mlx5_ifc_e_switch_cap_bits e_switch_cap; 3283 struct mlx5_ifc_port_selection_cap_bits port_selection_cap; 3284 struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap; 3285 struct mlx5_ifc_qos_cap_bits qos_cap; 3286 struct mlx5_ifc_debug_cap_bits debug_cap; 3287 struct mlx5_ifc_fpga_cap_bits fpga_cap; 3288 struct mlx5_ifc_tls_cap_bits tls_cap; 3289 struct mlx5_ifc_device_mem_cap_bits device_mem_cap; 3290 struct mlx5_ifc_virtio_emulation_cap_bits virtio_emulation_cap; 3291 struct mlx5_ifc_shampo_cap_bits shampo_cap; 3292 u8 reserved_at_0[0x8000]; 3293 }; 3294 3295 enum { 3296 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1, 3297 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2, 3298 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4, 3299 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8, 3300 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT = 0x10, 3301 MLX5_FLOW_CONTEXT_ACTION_DECAP = 0x20, 3302 MLX5_FLOW_CONTEXT_ACTION_MOD_HDR = 0x40, 3303 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP = 0x80, 3304 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100, 3305 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2 = 0x400, 3306 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2 = 0x800, 3307 MLX5_FLOW_CONTEXT_ACTION_IPSEC_DECRYPT = 0x1000, 3308 MLX5_FLOW_CONTEXT_ACTION_IPSEC_ENCRYPT = 0x2000, 3309 MLX5_FLOW_CONTEXT_ACTION_EXECUTE_ASO = 0x4000, 3310 }; 3311 3312 enum { 3313 MLX5_FLOW_CONTEXT_FLOW_SOURCE_ANY_VPORT = 0x0, 3314 MLX5_FLOW_CONTEXT_FLOW_SOURCE_UPLINK = 0x1, 3315 MLX5_FLOW_CONTEXT_FLOW_SOURCE_LOCAL_VPORT = 0x2, 3316 }; 3317 3318 struct mlx5_ifc_vlan_bits { 3319 u8 ethtype[0x10]; 3320 u8 prio[0x3]; 3321 u8 cfi[0x1]; 3322 u8 vid[0xc]; 3323 }; 3324 3325 enum { 3326 MLX5_FLOW_METER_COLOR_RED = 0x0, 3327 MLX5_FLOW_METER_COLOR_YELLOW = 0x1, 3328 MLX5_FLOW_METER_COLOR_GREEN = 0x2, 3329 MLX5_FLOW_METER_COLOR_UNDEFINED = 0x3, 3330 }; 3331 3332 enum { 3333 MLX5_EXE_ASO_FLOW_METER = 0x2, 3334 }; 3335 3336 struct mlx5_ifc_exe_aso_ctrl_flow_meter_bits { 3337 u8 return_reg_id[0x4]; 3338 u8 aso_type[0x4]; 3339 u8 reserved_at_8[0x14]; 3340 u8 action[0x1]; 3341 u8 init_color[0x2]; 3342 u8 meter_id[0x1]; 3343 }; 3344 3345 union mlx5_ifc_exe_aso_ctrl { 3346 struct mlx5_ifc_exe_aso_ctrl_flow_meter_bits exe_aso_ctrl_flow_meter; 3347 }; 3348 3349 struct mlx5_ifc_execute_aso_bits { 3350 u8 valid[0x1]; 3351 u8 reserved_at_1[0x7]; 3352 u8 aso_object_id[0x18]; 3353 3354 union mlx5_ifc_exe_aso_ctrl exe_aso_ctrl; 3355 }; 3356 3357 struct mlx5_ifc_flow_context_bits { 3358 struct mlx5_ifc_vlan_bits push_vlan; 3359 3360 u8 group_id[0x20]; 3361 3362 u8 reserved_at_40[0x8]; 3363 u8 flow_tag[0x18]; 3364 3365 u8 reserved_at_60[0x10]; 3366 u8 action[0x10]; 3367 3368 u8 extended_destination[0x1]; 3369 u8 reserved_at_81[0x1]; 3370 u8 flow_source[0x2]; 3371 u8 reserved_at_84[0x4]; 3372 u8 destination_list_size[0x18]; 3373 3374 u8 reserved_at_a0[0x8]; 3375 u8 flow_counter_list_size[0x18]; 3376 3377 u8 packet_reformat_id[0x20]; 3378 3379 u8 modify_header_id[0x20]; 3380 3381 struct mlx5_ifc_vlan_bits push_vlan_2; 3382 3383 u8 ipsec_obj_id[0x20]; 3384 u8 reserved_at_140[0xc0]; 3385 3386 struct mlx5_ifc_fte_match_param_bits match_value; 3387 3388 struct mlx5_ifc_execute_aso_bits execute_aso[4]; 3389 3390 u8 reserved_at_1300[0x500]; 3391 3392 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[]; 3393 }; 3394 3395 enum { 3396 MLX5_XRC_SRQC_STATE_GOOD = 0x0, 3397 MLX5_XRC_SRQC_STATE_ERROR = 0x1, 3398 }; 3399 3400 struct mlx5_ifc_xrc_srqc_bits { 3401 u8 state[0x4]; 3402 u8 log_xrc_srq_size[0x4]; 3403 u8 reserved_at_8[0x18]; 3404 3405 u8 wq_signature[0x1]; 3406 u8 cont_srq[0x1]; 3407 u8 reserved_at_22[0x1]; 3408 u8 rlky[0x1]; 3409 u8 basic_cyclic_rcv_wqe[0x1]; 3410 u8 log_rq_stride[0x3]; 3411 u8 xrcd[0x18]; 3412 3413 u8 page_offset[0x6]; 3414 u8 reserved_at_46[0x1]; 3415 u8 dbr_umem_valid[0x1]; 3416 u8 cqn[0x18]; 3417 3418 u8 reserved_at_60[0x20]; 3419 3420 u8 user_index_equal_xrc_srqn[0x1]; 3421 u8 reserved_at_81[0x1]; 3422 u8 log_page_size[0x6]; 3423 u8 user_index[0x18]; 3424 3425 u8 reserved_at_a0[0x20]; 3426 3427 u8 reserved_at_c0[0x8]; 3428 u8 pd[0x18]; 3429 3430 u8 lwm[0x10]; 3431 u8 wqe_cnt[0x10]; 3432 3433 u8 reserved_at_100[0x40]; 3434 3435 u8 db_record_addr_h[0x20]; 3436 3437 u8 db_record_addr_l[0x1e]; 3438 u8 reserved_at_17e[0x2]; 3439 3440 u8 reserved_at_180[0x80]; 3441 }; 3442 3443 struct mlx5_ifc_vnic_diagnostic_statistics_bits { 3444 u8 counter_error_queues[0x20]; 3445 3446 u8 total_error_queues[0x20]; 3447 3448 u8 send_queue_priority_update_flow[0x20]; 3449 3450 u8 reserved_at_60[0x20]; 3451 3452 u8 nic_receive_steering_discard[0x40]; 3453 3454 u8 receive_discard_vport_down[0x40]; 3455 3456 u8 transmit_discard_vport_down[0x40]; 3457 3458 u8 async_eq_overrun[0x20]; 3459 3460 u8 comp_eq_overrun[0x20]; 3461 3462 u8 reserved_at_180[0x20]; 3463 3464 u8 invalid_command[0x20]; 3465 3466 u8 quota_exceeded_command[0x20]; 3467 3468 u8 internal_rq_out_of_buffer[0x20]; 3469 3470 u8 cq_overrun[0x20]; 3471 3472 u8 reserved_at_220[0xde0]; 3473 }; 3474 3475 struct mlx5_ifc_traffic_counter_bits { 3476 u8 packets[0x40]; 3477 3478 u8 octets[0x40]; 3479 }; 3480 3481 struct mlx5_ifc_tisc_bits { 3482 u8 strict_lag_tx_port_affinity[0x1]; 3483 u8 tls_en[0x1]; 3484 u8 reserved_at_2[0x2]; 3485 u8 lag_tx_port_affinity[0x04]; 3486 3487 u8 reserved_at_8[0x4]; 3488 u8 prio[0x4]; 3489 u8 reserved_at_10[0x10]; 3490 3491 u8 reserved_at_20[0x100]; 3492 3493 u8 reserved_at_120[0x8]; 3494 u8 transport_domain[0x18]; 3495 3496 u8 reserved_at_140[0x8]; 3497 u8 underlay_qpn[0x18]; 3498 3499 u8 reserved_at_160[0x8]; 3500 u8 pd[0x18]; 3501 3502 u8 reserved_at_180[0x380]; 3503 }; 3504 3505 enum { 3506 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0, 3507 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1, 3508 }; 3509 3510 enum { 3511 MLX5_TIRC_PACKET_MERGE_MASK_IPV4_LRO = BIT(0), 3512 MLX5_TIRC_PACKET_MERGE_MASK_IPV6_LRO = BIT(1), 3513 }; 3514 3515 enum { 3516 MLX5_RX_HASH_FN_NONE = 0x0, 3517 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1, 3518 MLX5_RX_HASH_FN_TOEPLITZ = 0x2, 3519 }; 3520 3521 enum { 3522 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST = 0x1, 3523 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST = 0x2, 3524 }; 3525 3526 struct mlx5_ifc_tirc_bits { 3527 u8 reserved_at_0[0x20]; 3528 3529 u8 disp_type[0x4]; 3530 u8 tls_en[0x1]; 3531 u8 reserved_at_25[0x1b]; 3532 3533 u8 reserved_at_40[0x40]; 3534 3535 u8 reserved_at_80[0x4]; 3536 u8 lro_timeout_period_usecs[0x10]; 3537 u8 packet_merge_mask[0x4]; 3538 u8 lro_max_ip_payload_size[0x8]; 3539 3540 u8 reserved_at_a0[0x40]; 3541 3542 u8 reserved_at_e0[0x8]; 3543 u8 inline_rqn[0x18]; 3544 3545 u8 rx_hash_symmetric[0x1]; 3546 u8 reserved_at_101[0x1]; 3547 u8 tunneled_offload_en[0x1]; 3548 u8 reserved_at_103[0x5]; 3549 u8 indirect_table[0x18]; 3550 3551 u8 rx_hash_fn[0x4]; 3552 u8 reserved_at_124[0x2]; 3553 u8 self_lb_block[0x2]; 3554 u8 transport_domain[0x18]; 3555 3556 u8 rx_hash_toeplitz_key[10][0x20]; 3557 3558 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer; 3559 3560 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner; 3561 3562 u8 reserved_at_2c0[0x4c0]; 3563 }; 3564 3565 enum { 3566 MLX5_SRQC_STATE_GOOD = 0x0, 3567 MLX5_SRQC_STATE_ERROR = 0x1, 3568 }; 3569 3570 struct mlx5_ifc_srqc_bits { 3571 u8 state[0x4]; 3572 u8 log_srq_size[0x4]; 3573 u8 reserved_at_8[0x18]; 3574 3575 u8 wq_signature[0x1]; 3576 u8 cont_srq[0x1]; 3577 u8 reserved_at_22[0x1]; 3578 u8 rlky[0x1]; 3579 u8 reserved_at_24[0x1]; 3580 u8 log_rq_stride[0x3]; 3581 u8 xrcd[0x18]; 3582 3583 u8 page_offset[0x6]; 3584 u8 reserved_at_46[0x2]; 3585 u8 cqn[0x18]; 3586 3587 u8 reserved_at_60[0x20]; 3588 3589 u8 reserved_at_80[0x2]; 3590 u8 log_page_size[0x6]; 3591 u8 reserved_at_88[0x18]; 3592 3593 u8 reserved_at_a0[0x20]; 3594 3595 u8 reserved_at_c0[0x8]; 3596 u8 pd[0x18]; 3597 3598 u8 lwm[0x10]; 3599 u8 wqe_cnt[0x10]; 3600 3601 u8 reserved_at_100[0x40]; 3602 3603 u8 dbr_addr[0x40]; 3604 3605 u8 reserved_at_180[0x80]; 3606 }; 3607 3608 enum { 3609 MLX5_SQC_STATE_RST = 0x0, 3610 MLX5_SQC_STATE_RDY = 0x1, 3611 MLX5_SQC_STATE_ERR = 0x3, 3612 }; 3613 3614 struct mlx5_ifc_sqc_bits { 3615 u8 rlky[0x1]; 3616 u8 cd_master[0x1]; 3617 u8 fre[0x1]; 3618 u8 flush_in_error_en[0x1]; 3619 u8 allow_multi_pkt_send_wqe[0x1]; 3620 u8 min_wqe_inline_mode[0x3]; 3621 u8 state[0x4]; 3622 u8 reg_umr[0x1]; 3623 u8 allow_swp[0x1]; 3624 u8 hairpin[0x1]; 3625 u8 reserved_at_f[0xb]; 3626 u8 ts_format[0x2]; 3627 u8 reserved_at_1c[0x4]; 3628 3629 u8 reserved_at_20[0x8]; 3630 u8 user_index[0x18]; 3631 3632 u8 reserved_at_40[0x8]; 3633 u8 cqn[0x18]; 3634 3635 u8 reserved_at_60[0x8]; 3636 u8 hairpin_peer_rq[0x18]; 3637 3638 u8 reserved_at_80[0x10]; 3639 u8 hairpin_peer_vhca[0x10]; 3640 3641 u8 reserved_at_a0[0x20]; 3642 3643 u8 reserved_at_c0[0x8]; 3644 u8 ts_cqe_to_dest_cqn[0x18]; 3645 3646 u8 reserved_at_e0[0x10]; 3647 u8 packet_pacing_rate_limit_index[0x10]; 3648 u8 tis_lst_sz[0x10]; 3649 u8 qos_queue_group_id[0x10]; 3650 3651 u8 reserved_at_120[0x40]; 3652 3653 u8 reserved_at_160[0x8]; 3654 u8 tis_num_0[0x18]; 3655 3656 struct mlx5_ifc_wq_bits wq; 3657 }; 3658 3659 enum { 3660 SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0, 3661 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1, 3662 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2, 3663 SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3, 3664 SCHEDULING_CONTEXT_ELEMENT_TYPE_QUEUE_GROUP = 0x4, 3665 }; 3666 3667 enum { 3668 ELEMENT_TYPE_CAP_MASK_TASR = 1 << 0, 3669 ELEMENT_TYPE_CAP_MASK_VPORT = 1 << 1, 3670 ELEMENT_TYPE_CAP_MASK_VPORT_TC = 1 << 2, 3671 ELEMENT_TYPE_CAP_MASK_PARA_VPORT_TC = 1 << 3, 3672 }; 3673 3674 struct mlx5_ifc_scheduling_context_bits { 3675 u8 element_type[0x8]; 3676 u8 reserved_at_8[0x18]; 3677 3678 u8 element_attributes[0x20]; 3679 3680 u8 parent_element_id[0x20]; 3681 3682 u8 reserved_at_60[0x40]; 3683 3684 u8 bw_share[0x20]; 3685 3686 u8 max_average_bw[0x20]; 3687 3688 u8 reserved_at_e0[0x120]; 3689 }; 3690 3691 struct mlx5_ifc_rqtc_bits { 3692 u8 reserved_at_0[0xa0]; 3693 3694 u8 reserved_at_a0[0x5]; 3695 u8 list_q_type[0x3]; 3696 u8 reserved_at_a8[0x8]; 3697 u8 rqt_max_size[0x10]; 3698 3699 u8 rq_vhca_id_format[0x1]; 3700 u8 reserved_at_c1[0xf]; 3701 u8 rqt_actual_size[0x10]; 3702 3703 u8 reserved_at_e0[0x6a0]; 3704 3705 struct mlx5_ifc_rq_num_bits rq_num[]; 3706 }; 3707 3708 enum { 3709 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0, 3710 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1, 3711 }; 3712 3713 enum { 3714 MLX5_RQC_STATE_RST = 0x0, 3715 MLX5_RQC_STATE_RDY = 0x1, 3716 MLX5_RQC_STATE_ERR = 0x3, 3717 }; 3718 3719 enum { 3720 MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_BYTE = 0x0, 3721 MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_STRIDE = 0x1, 3722 MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_PAGE = 0x2, 3723 }; 3724 3725 enum { 3726 MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_NO_MATCH = 0x0, 3727 MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_EXTENDED = 0x1, 3728 MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_FIVE_TUPLE = 0x2, 3729 }; 3730 3731 struct mlx5_ifc_rqc_bits { 3732 u8 rlky[0x1]; 3733 u8 delay_drop_en[0x1]; 3734 u8 scatter_fcs[0x1]; 3735 u8 vsd[0x1]; 3736 u8 mem_rq_type[0x4]; 3737 u8 state[0x4]; 3738 u8 reserved_at_c[0x1]; 3739 u8 flush_in_error_en[0x1]; 3740 u8 hairpin[0x1]; 3741 u8 reserved_at_f[0xb]; 3742 u8 ts_format[0x2]; 3743 u8 reserved_at_1c[0x4]; 3744 3745 u8 reserved_at_20[0x8]; 3746 u8 user_index[0x18]; 3747 3748 u8 reserved_at_40[0x8]; 3749 u8 cqn[0x18]; 3750 3751 u8 counter_set_id[0x8]; 3752 u8 reserved_at_68[0x18]; 3753 3754 u8 reserved_at_80[0x8]; 3755 u8 rmpn[0x18]; 3756 3757 u8 reserved_at_a0[0x8]; 3758 u8 hairpin_peer_sq[0x18]; 3759 3760 u8 reserved_at_c0[0x10]; 3761 u8 hairpin_peer_vhca[0x10]; 3762 3763 u8 reserved_at_e0[0x46]; 3764 u8 shampo_no_match_alignment_granularity[0x2]; 3765 u8 reserved_at_128[0x6]; 3766 u8 shampo_match_criteria_type[0x2]; 3767 u8 reservation_timeout[0x10]; 3768 3769 u8 reserved_at_140[0x40]; 3770 3771 struct mlx5_ifc_wq_bits wq; 3772 }; 3773 3774 enum { 3775 MLX5_RMPC_STATE_RDY = 0x1, 3776 MLX5_RMPC_STATE_ERR = 0x3, 3777 }; 3778 3779 struct mlx5_ifc_rmpc_bits { 3780 u8 reserved_at_0[0x8]; 3781 u8 state[0x4]; 3782 u8 reserved_at_c[0x14]; 3783 3784 u8 basic_cyclic_rcv_wqe[0x1]; 3785 u8 reserved_at_21[0x1f]; 3786 3787 u8 reserved_at_40[0x140]; 3788 3789 struct mlx5_ifc_wq_bits wq; 3790 }; 3791 3792 enum { 3793 VHCA_ID_TYPE_HW = 0, 3794 VHCA_ID_TYPE_SW = 1, 3795 }; 3796 3797 struct mlx5_ifc_nic_vport_context_bits { 3798 u8 reserved_at_0[0x5]; 3799 u8 min_wqe_inline_mode[0x3]; 3800 u8 reserved_at_8[0x15]; 3801 u8 disable_mc_local_lb[0x1]; 3802 u8 disable_uc_local_lb[0x1]; 3803 u8 roce_en[0x1]; 3804 3805 u8 arm_change_event[0x1]; 3806 u8 reserved_at_21[0x1a]; 3807 u8 event_on_mtu[0x1]; 3808 u8 event_on_promisc_change[0x1]; 3809 u8 event_on_vlan_change[0x1]; 3810 u8 event_on_mc_address_change[0x1]; 3811 u8 event_on_uc_address_change[0x1]; 3812 3813 u8 vhca_id_type[0x1]; 3814 u8 reserved_at_41[0xb]; 3815 u8 affiliation_criteria[0x4]; 3816 u8 affiliated_vhca_id[0x10]; 3817 3818 u8 reserved_at_60[0xd0]; 3819 3820 u8 mtu[0x10]; 3821 3822 u8 system_image_guid[0x40]; 3823 u8 port_guid[0x40]; 3824 u8 node_guid[0x40]; 3825 3826 u8 reserved_at_200[0x140]; 3827 u8 qkey_violation_counter[0x10]; 3828 u8 reserved_at_350[0x430]; 3829 3830 u8 promisc_uc[0x1]; 3831 u8 promisc_mc[0x1]; 3832 u8 promisc_all[0x1]; 3833 u8 reserved_at_783[0x2]; 3834 u8 allowed_list_type[0x3]; 3835 u8 reserved_at_788[0xc]; 3836 u8 allowed_list_size[0xc]; 3837 3838 struct mlx5_ifc_mac_address_layout_bits permanent_address; 3839 3840 u8 reserved_at_7e0[0x20]; 3841 3842 u8 current_uc_mac_address[][0x40]; 3843 }; 3844 3845 enum { 3846 MLX5_MKC_ACCESS_MODE_PA = 0x0, 3847 MLX5_MKC_ACCESS_MODE_MTT = 0x1, 3848 MLX5_MKC_ACCESS_MODE_KLMS = 0x2, 3849 MLX5_MKC_ACCESS_MODE_KSM = 0x3, 3850 MLX5_MKC_ACCESS_MODE_SW_ICM = 0x4, 3851 MLX5_MKC_ACCESS_MODE_MEMIC = 0x5, 3852 }; 3853 3854 struct mlx5_ifc_mkc_bits { 3855 u8 reserved_at_0[0x1]; 3856 u8 free[0x1]; 3857 u8 reserved_at_2[0x1]; 3858 u8 access_mode_4_2[0x3]; 3859 u8 reserved_at_6[0x7]; 3860 u8 relaxed_ordering_write[0x1]; 3861 u8 reserved_at_e[0x1]; 3862 u8 small_fence_on_rdma_read_response[0x1]; 3863 u8 umr_en[0x1]; 3864 u8 a[0x1]; 3865 u8 rw[0x1]; 3866 u8 rr[0x1]; 3867 u8 lw[0x1]; 3868 u8 lr[0x1]; 3869 u8 access_mode_1_0[0x2]; 3870 u8 reserved_at_18[0x8]; 3871 3872 u8 qpn[0x18]; 3873 u8 mkey_7_0[0x8]; 3874 3875 u8 reserved_at_40[0x20]; 3876 3877 u8 length64[0x1]; 3878 u8 bsf_en[0x1]; 3879 u8 sync_umr[0x1]; 3880 u8 reserved_at_63[0x2]; 3881 u8 expected_sigerr_count[0x1]; 3882 u8 reserved_at_66[0x1]; 3883 u8 en_rinval[0x1]; 3884 u8 pd[0x18]; 3885 3886 u8 start_addr[0x40]; 3887 3888 u8 len[0x40]; 3889 3890 u8 bsf_octword_size[0x20]; 3891 3892 u8 reserved_at_120[0x80]; 3893 3894 u8 translations_octword_size[0x20]; 3895 3896 u8 reserved_at_1c0[0x19]; 3897 u8 relaxed_ordering_read[0x1]; 3898 u8 reserved_at_1d9[0x1]; 3899 u8 log_page_size[0x5]; 3900 3901 u8 reserved_at_1e0[0x20]; 3902 }; 3903 3904 struct mlx5_ifc_pkey_bits { 3905 u8 reserved_at_0[0x10]; 3906 u8 pkey[0x10]; 3907 }; 3908 3909 struct mlx5_ifc_array128_auto_bits { 3910 u8 array128_auto[16][0x8]; 3911 }; 3912 3913 struct mlx5_ifc_hca_vport_context_bits { 3914 u8 field_select[0x20]; 3915 3916 u8 reserved_at_20[0xe0]; 3917 3918 u8 sm_virt_aware[0x1]; 3919 u8 has_smi[0x1]; 3920 u8 has_raw[0x1]; 3921 u8 grh_required[0x1]; 3922 u8 reserved_at_104[0xc]; 3923 u8 port_physical_state[0x4]; 3924 u8 vport_state_policy[0x4]; 3925 u8 port_state[0x4]; 3926 u8 vport_state[0x4]; 3927 3928 u8 reserved_at_120[0x20]; 3929 3930 u8 system_image_guid[0x40]; 3931 3932 u8 port_guid[0x40]; 3933 3934 u8 node_guid[0x40]; 3935 3936 u8 cap_mask1[0x20]; 3937 3938 u8 cap_mask1_field_select[0x20]; 3939 3940 u8 cap_mask2[0x20]; 3941 3942 u8 cap_mask2_field_select[0x20]; 3943 3944 u8 reserved_at_280[0x80]; 3945 3946 u8 lid[0x10]; 3947 u8 reserved_at_310[0x4]; 3948 u8 init_type_reply[0x4]; 3949 u8 lmc[0x3]; 3950 u8 subnet_timeout[0x5]; 3951 3952 u8 sm_lid[0x10]; 3953 u8 sm_sl[0x4]; 3954 u8 reserved_at_334[0xc]; 3955 3956 u8 qkey_violation_counter[0x10]; 3957 u8 pkey_violation_counter[0x10]; 3958 3959 u8 reserved_at_360[0xca0]; 3960 }; 3961 3962 struct mlx5_ifc_esw_vport_context_bits { 3963 u8 fdb_to_vport_reg_c[0x1]; 3964 u8 reserved_at_1[0x2]; 3965 u8 vport_svlan_strip[0x1]; 3966 u8 vport_cvlan_strip[0x1]; 3967 u8 vport_svlan_insert[0x1]; 3968 u8 vport_cvlan_insert[0x2]; 3969 u8 fdb_to_vport_reg_c_id[0x8]; 3970 u8 reserved_at_10[0x10]; 3971 3972 u8 reserved_at_20[0x20]; 3973 3974 u8 svlan_cfi[0x1]; 3975 u8 svlan_pcp[0x3]; 3976 u8 svlan_id[0xc]; 3977 u8 cvlan_cfi[0x1]; 3978 u8 cvlan_pcp[0x3]; 3979 u8 cvlan_id[0xc]; 3980 3981 u8 reserved_at_60[0x720]; 3982 3983 u8 sw_steering_vport_icm_address_rx[0x40]; 3984 3985 u8 sw_steering_vport_icm_address_tx[0x40]; 3986 }; 3987 3988 enum { 3989 MLX5_EQC_STATUS_OK = 0x0, 3990 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa, 3991 }; 3992 3993 enum { 3994 MLX5_EQC_ST_ARMED = 0x9, 3995 MLX5_EQC_ST_FIRED = 0xa, 3996 }; 3997 3998 struct mlx5_ifc_eqc_bits { 3999 u8 status[0x4]; 4000 u8 reserved_at_4[0x9]; 4001 u8 ec[0x1]; 4002 u8 oi[0x1]; 4003 u8 reserved_at_f[0x5]; 4004 u8 st[0x4]; 4005 u8 reserved_at_18[0x8]; 4006 4007 u8 reserved_at_20[0x20]; 4008 4009 u8 reserved_at_40[0x14]; 4010 u8 page_offset[0x6]; 4011 u8 reserved_at_5a[0x6]; 4012 4013 u8 reserved_at_60[0x3]; 4014 u8 log_eq_size[0x5]; 4015 u8 uar_page[0x18]; 4016 4017 u8 reserved_at_80[0x20]; 4018 4019 u8 reserved_at_a0[0x14]; 4020 u8 intr[0xc]; 4021 4022 u8 reserved_at_c0[0x3]; 4023 u8 log_page_size[0x5]; 4024 u8 reserved_at_c8[0x18]; 4025 4026 u8 reserved_at_e0[0x60]; 4027 4028 u8 reserved_at_140[0x8]; 4029 u8 consumer_counter[0x18]; 4030 4031 u8 reserved_at_160[0x8]; 4032 u8 producer_counter[0x18]; 4033 4034 u8 reserved_at_180[0x80]; 4035 }; 4036 4037 enum { 4038 MLX5_DCTC_STATE_ACTIVE = 0x0, 4039 MLX5_DCTC_STATE_DRAINING = 0x1, 4040 MLX5_DCTC_STATE_DRAINED = 0x2, 4041 }; 4042 4043 enum { 4044 MLX5_DCTC_CS_RES_DISABLE = 0x0, 4045 MLX5_DCTC_CS_RES_NA = 0x1, 4046 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2, 4047 }; 4048 4049 enum { 4050 MLX5_DCTC_MTU_256_BYTES = 0x1, 4051 MLX5_DCTC_MTU_512_BYTES = 0x2, 4052 MLX5_DCTC_MTU_1K_BYTES = 0x3, 4053 MLX5_DCTC_MTU_2K_BYTES = 0x4, 4054 MLX5_DCTC_MTU_4K_BYTES = 0x5, 4055 }; 4056 4057 struct mlx5_ifc_dctc_bits { 4058 u8 reserved_at_0[0x4]; 4059 u8 state[0x4]; 4060 u8 reserved_at_8[0x18]; 4061 4062 u8 reserved_at_20[0x8]; 4063 u8 user_index[0x18]; 4064 4065 u8 reserved_at_40[0x8]; 4066 u8 cqn[0x18]; 4067 4068 u8 counter_set_id[0x8]; 4069 u8 atomic_mode[0x4]; 4070 u8 rre[0x1]; 4071 u8 rwe[0x1]; 4072 u8 rae[0x1]; 4073 u8 atomic_like_write_en[0x1]; 4074 u8 latency_sensitive[0x1]; 4075 u8 rlky[0x1]; 4076 u8 free_ar[0x1]; 4077 u8 reserved_at_73[0xd]; 4078 4079 u8 reserved_at_80[0x8]; 4080 u8 cs_res[0x8]; 4081 u8 reserved_at_90[0x3]; 4082 u8 min_rnr_nak[0x5]; 4083 u8 reserved_at_98[0x8]; 4084 4085 u8 reserved_at_a0[0x8]; 4086 u8 srqn_xrqn[0x18]; 4087 4088 u8 reserved_at_c0[0x8]; 4089 u8 pd[0x18]; 4090 4091 u8 tclass[0x8]; 4092 u8 reserved_at_e8[0x4]; 4093 u8 flow_label[0x14]; 4094 4095 u8 dc_access_key[0x40]; 4096 4097 u8 reserved_at_140[0x5]; 4098 u8 mtu[0x3]; 4099 u8 port[0x8]; 4100 u8 pkey_index[0x10]; 4101 4102 u8 reserved_at_160[0x8]; 4103 u8 my_addr_index[0x8]; 4104 u8 reserved_at_170[0x8]; 4105 u8 hop_limit[0x8]; 4106 4107 u8 dc_access_key_violation_count[0x20]; 4108 4109 u8 reserved_at_1a0[0x14]; 4110 u8 dei_cfi[0x1]; 4111 u8 eth_prio[0x3]; 4112 u8 ecn[0x2]; 4113 u8 dscp[0x6]; 4114 4115 u8 reserved_at_1c0[0x20]; 4116 u8 ece[0x20]; 4117 }; 4118 4119 enum { 4120 MLX5_CQC_STATUS_OK = 0x0, 4121 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9, 4122 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa, 4123 }; 4124 4125 enum { 4126 MLX5_CQC_CQE_SZ_64_BYTES = 0x0, 4127 MLX5_CQC_CQE_SZ_128_BYTES = 0x1, 4128 }; 4129 4130 enum { 4131 MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED = 0x6, 4132 MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED = 0x9, 4133 MLX5_CQC_ST_FIRED = 0xa, 4134 }; 4135 4136 enum { 4137 MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0, 4138 MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1, 4139 MLX5_CQ_PERIOD_NUM_MODES 4140 }; 4141 4142 struct mlx5_ifc_cqc_bits { 4143 u8 status[0x4]; 4144 u8 reserved_at_4[0x2]; 4145 u8 dbr_umem_valid[0x1]; 4146 u8 apu_cq[0x1]; 4147 u8 cqe_sz[0x3]; 4148 u8 cc[0x1]; 4149 u8 reserved_at_c[0x1]; 4150 u8 scqe_break_moderation_en[0x1]; 4151 u8 oi[0x1]; 4152 u8 cq_period_mode[0x2]; 4153 u8 cqe_comp_en[0x1]; 4154 u8 mini_cqe_res_format[0x2]; 4155 u8 st[0x4]; 4156 u8 reserved_at_18[0x6]; 4157 u8 cqe_compression_layout[0x2]; 4158 4159 u8 reserved_at_20[0x20]; 4160 4161 u8 reserved_at_40[0x14]; 4162 u8 page_offset[0x6]; 4163 u8 reserved_at_5a[0x6]; 4164 4165 u8 reserved_at_60[0x3]; 4166 u8 log_cq_size[0x5]; 4167 u8 uar_page[0x18]; 4168 4169 u8 reserved_at_80[0x4]; 4170 u8 cq_period[0xc]; 4171 u8 cq_max_count[0x10]; 4172 4173 u8 c_eqn_or_apu_element[0x20]; 4174 4175 u8 reserved_at_c0[0x3]; 4176 u8 log_page_size[0x5]; 4177 u8 reserved_at_c8[0x18]; 4178 4179 u8 reserved_at_e0[0x20]; 4180 4181 u8 reserved_at_100[0x8]; 4182 u8 last_notified_index[0x18]; 4183 4184 u8 reserved_at_120[0x8]; 4185 u8 last_solicit_index[0x18]; 4186 4187 u8 reserved_at_140[0x8]; 4188 u8 consumer_counter[0x18]; 4189 4190 u8 reserved_at_160[0x8]; 4191 u8 producer_counter[0x18]; 4192 4193 u8 reserved_at_180[0x40]; 4194 4195 u8 dbr_addr[0x40]; 4196 }; 4197 4198 union mlx5_ifc_cong_control_roce_ecn_auto_bits { 4199 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp; 4200 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp; 4201 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np; 4202 u8 reserved_at_0[0x800]; 4203 }; 4204 4205 struct mlx5_ifc_query_adapter_param_block_bits { 4206 u8 reserved_at_0[0xc0]; 4207 4208 u8 reserved_at_c0[0x8]; 4209 u8 ieee_vendor_id[0x18]; 4210 4211 u8 reserved_at_e0[0x10]; 4212 u8 vsd_vendor_id[0x10]; 4213 4214 u8 vsd[208][0x8]; 4215 4216 u8 vsd_contd_psid[16][0x8]; 4217 }; 4218 4219 enum { 4220 MLX5_XRQC_STATE_GOOD = 0x0, 4221 MLX5_XRQC_STATE_ERROR = 0x1, 4222 }; 4223 4224 enum { 4225 MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0, 4226 MLX5_XRQC_TOPOLOGY_TAG_MATCHING = 0x1, 4227 }; 4228 4229 enum { 4230 MLX5_XRQC_OFFLOAD_RNDV = 0x1, 4231 }; 4232 4233 struct mlx5_ifc_tag_matching_topology_context_bits { 4234 u8 log_matching_list_sz[0x4]; 4235 u8 reserved_at_4[0xc]; 4236 u8 append_next_index[0x10]; 4237 4238 u8 sw_phase_cnt[0x10]; 4239 u8 hw_phase_cnt[0x10]; 4240 4241 u8 reserved_at_40[0x40]; 4242 }; 4243 4244 struct mlx5_ifc_xrqc_bits { 4245 u8 state[0x4]; 4246 u8 rlkey[0x1]; 4247 u8 reserved_at_5[0xf]; 4248 u8 topology[0x4]; 4249 u8 reserved_at_18[0x4]; 4250 u8 offload[0x4]; 4251 4252 u8 reserved_at_20[0x8]; 4253 u8 user_index[0x18]; 4254 4255 u8 reserved_at_40[0x8]; 4256 u8 cqn[0x18]; 4257 4258 u8 reserved_at_60[0xa0]; 4259 4260 struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context; 4261 4262 u8 reserved_at_180[0x280]; 4263 4264 struct mlx5_ifc_wq_bits wq; 4265 }; 4266 4267 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits { 4268 struct mlx5_ifc_modify_field_select_bits modify_field_select; 4269 struct mlx5_ifc_resize_field_select_bits resize_field_select; 4270 u8 reserved_at_0[0x20]; 4271 }; 4272 4273 union mlx5_ifc_field_select_802_1_r_roce_auto_bits { 4274 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp; 4275 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp; 4276 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np; 4277 u8 reserved_at_0[0x20]; 4278 }; 4279 4280 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits { 4281 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 4282 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 4283 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 4284 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 4285 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 4286 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 4287 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout; 4288 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout; 4289 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 4290 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 4291 struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs; 4292 u8 reserved_at_0[0x7c0]; 4293 }; 4294 4295 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits { 4296 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout; 4297 u8 reserved_at_0[0x7c0]; 4298 }; 4299 4300 union mlx5_ifc_event_auto_bits { 4301 struct mlx5_ifc_comp_event_bits comp_event; 4302 struct mlx5_ifc_dct_events_bits dct_events; 4303 struct mlx5_ifc_qp_events_bits qp_events; 4304 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event; 4305 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event; 4306 struct mlx5_ifc_cq_error_bits cq_error; 4307 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged; 4308 struct mlx5_ifc_port_state_change_event_bits port_state_change_event; 4309 struct mlx5_ifc_gpio_event_bits gpio_event; 4310 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event; 4311 struct mlx5_ifc_stall_vl_event_bits stall_vl_event; 4312 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event; 4313 u8 reserved_at_0[0xe0]; 4314 }; 4315 4316 struct mlx5_ifc_health_buffer_bits { 4317 u8 reserved_at_0[0x100]; 4318 4319 u8 assert_existptr[0x20]; 4320 4321 u8 assert_callra[0x20]; 4322 4323 u8 reserved_at_140[0x20]; 4324 4325 u8 time[0x20]; 4326 4327 u8 fw_version[0x20]; 4328 4329 u8 hw_id[0x20]; 4330 4331 u8 rfr[0x1]; 4332 u8 reserved_at_1c1[0x3]; 4333 u8 valid[0x1]; 4334 u8 severity[0x3]; 4335 u8 reserved_at_1c8[0x18]; 4336 4337 u8 irisc_index[0x8]; 4338 u8 synd[0x8]; 4339 u8 ext_synd[0x10]; 4340 }; 4341 4342 struct mlx5_ifc_register_loopback_control_bits { 4343 u8 no_lb[0x1]; 4344 u8 reserved_at_1[0x7]; 4345 u8 port[0x8]; 4346 u8 reserved_at_10[0x10]; 4347 4348 u8 reserved_at_20[0x60]; 4349 }; 4350 4351 struct mlx5_ifc_vport_tc_element_bits { 4352 u8 traffic_class[0x4]; 4353 u8 reserved_at_4[0xc]; 4354 u8 vport_number[0x10]; 4355 }; 4356 4357 struct mlx5_ifc_vport_element_bits { 4358 u8 reserved_at_0[0x10]; 4359 u8 vport_number[0x10]; 4360 }; 4361 4362 enum { 4363 TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0, 4364 TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1, 4365 TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2, 4366 }; 4367 4368 struct mlx5_ifc_tsar_element_bits { 4369 u8 reserved_at_0[0x8]; 4370 u8 tsar_type[0x8]; 4371 u8 reserved_at_10[0x10]; 4372 }; 4373 4374 enum { 4375 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0, 4376 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1, 4377 }; 4378 4379 struct mlx5_ifc_teardown_hca_out_bits { 4380 u8 status[0x8]; 4381 u8 reserved_at_8[0x18]; 4382 4383 u8 syndrome[0x20]; 4384 4385 u8 reserved_at_40[0x3f]; 4386 4387 u8 state[0x1]; 4388 }; 4389 4390 enum { 4391 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0, 4392 MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE = 0x1, 4393 MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN = 0x2, 4394 }; 4395 4396 struct mlx5_ifc_teardown_hca_in_bits { 4397 u8 opcode[0x10]; 4398 u8 reserved_at_10[0x10]; 4399 4400 u8 reserved_at_20[0x10]; 4401 u8 op_mod[0x10]; 4402 4403 u8 reserved_at_40[0x10]; 4404 u8 profile[0x10]; 4405 4406 u8 reserved_at_60[0x20]; 4407 }; 4408 4409 struct mlx5_ifc_sqerr2rts_qp_out_bits { 4410 u8 status[0x8]; 4411 u8 reserved_at_8[0x18]; 4412 4413 u8 syndrome[0x20]; 4414 4415 u8 reserved_at_40[0x40]; 4416 }; 4417 4418 struct mlx5_ifc_sqerr2rts_qp_in_bits { 4419 u8 opcode[0x10]; 4420 u8 uid[0x10]; 4421 4422 u8 reserved_at_20[0x10]; 4423 u8 op_mod[0x10]; 4424 4425 u8 reserved_at_40[0x8]; 4426 u8 qpn[0x18]; 4427 4428 u8 reserved_at_60[0x20]; 4429 4430 u8 opt_param_mask[0x20]; 4431 4432 u8 reserved_at_a0[0x20]; 4433 4434 struct mlx5_ifc_qpc_bits qpc; 4435 4436 u8 reserved_at_800[0x80]; 4437 }; 4438 4439 struct mlx5_ifc_sqd2rts_qp_out_bits { 4440 u8 status[0x8]; 4441 u8 reserved_at_8[0x18]; 4442 4443 u8 syndrome[0x20]; 4444 4445 u8 reserved_at_40[0x40]; 4446 }; 4447 4448 struct mlx5_ifc_sqd2rts_qp_in_bits { 4449 u8 opcode[0x10]; 4450 u8 uid[0x10]; 4451 4452 u8 reserved_at_20[0x10]; 4453 u8 op_mod[0x10]; 4454 4455 u8 reserved_at_40[0x8]; 4456 u8 qpn[0x18]; 4457 4458 u8 reserved_at_60[0x20]; 4459 4460 u8 opt_param_mask[0x20]; 4461 4462 u8 reserved_at_a0[0x20]; 4463 4464 struct mlx5_ifc_qpc_bits qpc; 4465 4466 u8 reserved_at_800[0x80]; 4467 }; 4468 4469 struct mlx5_ifc_set_roce_address_out_bits { 4470 u8 status[0x8]; 4471 u8 reserved_at_8[0x18]; 4472 4473 u8 syndrome[0x20]; 4474 4475 u8 reserved_at_40[0x40]; 4476 }; 4477 4478 struct mlx5_ifc_set_roce_address_in_bits { 4479 u8 opcode[0x10]; 4480 u8 reserved_at_10[0x10]; 4481 4482 u8 reserved_at_20[0x10]; 4483 u8 op_mod[0x10]; 4484 4485 u8 roce_address_index[0x10]; 4486 u8 reserved_at_50[0xc]; 4487 u8 vhca_port_num[0x4]; 4488 4489 u8 reserved_at_60[0x20]; 4490 4491 struct mlx5_ifc_roce_addr_layout_bits roce_address; 4492 }; 4493 4494 struct mlx5_ifc_set_mad_demux_out_bits { 4495 u8 status[0x8]; 4496 u8 reserved_at_8[0x18]; 4497 4498 u8 syndrome[0x20]; 4499 4500 u8 reserved_at_40[0x40]; 4501 }; 4502 4503 enum { 4504 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0, 4505 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2, 4506 }; 4507 4508 struct mlx5_ifc_set_mad_demux_in_bits { 4509 u8 opcode[0x10]; 4510 u8 reserved_at_10[0x10]; 4511 4512 u8 reserved_at_20[0x10]; 4513 u8 op_mod[0x10]; 4514 4515 u8 reserved_at_40[0x20]; 4516 4517 u8 reserved_at_60[0x6]; 4518 u8 demux_mode[0x2]; 4519 u8 reserved_at_68[0x18]; 4520 }; 4521 4522 struct mlx5_ifc_set_l2_table_entry_out_bits { 4523 u8 status[0x8]; 4524 u8 reserved_at_8[0x18]; 4525 4526 u8 syndrome[0x20]; 4527 4528 u8 reserved_at_40[0x40]; 4529 }; 4530 4531 struct mlx5_ifc_set_l2_table_entry_in_bits { 4532 u8 opcode[0x10]; 4533 u8 reserved_at_10[0x10]; 4534 4535 u8 reserved_at_20[0x10]; 4536 u8 op_mod[0x10]; 4537 4538 u8 reserved_at_40[0x60]; 4539 4540 u8 reserved_at_a0[0x8]; 4541 u8 table_index[0x18]; 4542 4543 u8 reserved_at_c0[0x20]; 4544 4545 u8 reserved_at_e0[0x13]; 4546 u8 vlan_valid[0x1]; 4547 u8 vlan[0xc]; 4548 4549 struct mlx5_ifc_mac_address_layout_bits mac_address; 4550 4551 u8 reserved_at_140[0xc0]; 4552 }; 4553 4554 struct mlx5_ifc_set_issi_out_bits { 4555 u8 status[0x8]; 4556 u8 reserved_at_8[0x18]; 4557 4558 u8 syndrome[0x20]; 4559 4560 u8 reserved_at_40[0x40]; 4561 }; 4562 4563 struct mlx5_ifc_set_issi_in_bits { 4564 u8 opcode[0x10]; 4565 u8 reserved_at_10[0x10]; 4566 4567 u8 reserved_at_20[0x10]; 4568 u8 op_mod[0x10]; 4569 4570 u8 reserved_at_40[0x10]; 4571 u8 current_issi[0x10]; 4572 4573 u8 reserved_at_60[0x20]; 4574 }; 4575 4576 struct mlx5_ifc_set_hca_cap_out_bits { 4577 u8 status[0x8]; 4578 u8 reserved_at_8[0x18]; 4579 4580 u8 syndrome[0x20]; 4581 4582 u8 reserved_at_40[0x40]; 4583 }; 4584 4585 struct mlx5_ifc_set_hca_cap_in_bits { 4586 u8 opcode[0x10]; 4587 u8 reserved_at_10[0x10]; 4588 4589 u8 reserved_at_20[0x10]; 4590 u8 op_mod[0x10]; 4591 4592 u8 other_function[0x1]; 4593 u8 reserved_at_41[0xf]; 4594 u8 function_id[0x10]; 4595 4596 u8 reserved_at_60[0x20]; 4597 4598 union mlx5_ifc_hca_cap_union_bits capability; 4599 }; 4600 4601 enum { 4602 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0, 4603 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1, 4604 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2, 4605 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3, 4606 MLX5_SET_FTE_MODIFY_ENABLE_MASK_IPSEC_OBJ_ID = 0x4 4607 }; 4608 4609 struct mlx5_ifc_set_fte_out_bits { 4610 u8 status[0x8]; 4611 u8 reserved_at_8[0x18]; 4612 4613 u8 syndrome[0x20]; 4614 4615 u8 reserved_at_40[0x40]; 4616 }; 4617 4618 struct mlx5_ifc_set_fte_in_bits { 4619 u8 opcode[0x10]; 4620 u8 reserved_at_10[0x10]; 4621 4622 u8 reserved_at_20[0x10]; 4623 u8 op_mod[0x10]; 4624 4625 u8 other_vport[0x1]; 4626 u8 reserved_at_41[0xf]; 4627 u8 vport_number[0x10]; 4628 4629 u8 reserved_at_60[0x20]; 4630 4631 u8 table_type[0x8]; 4632 u8 reserved_at_88[0x18]; 4633 4634 u8 reserved_at_a0[0x8]; 4635 u8 table_id[0x18]; 4636 4637 u8 ignore_flow_level[0x1]; 4638 u8 reserved_at_c1[0x17]; 4639 u8 modify_enable_mask[0x8]; 4640 4641 u8 reserved_at_e0[0x20]; 4642 4643 u8 flow_index[0x20]; 4644 4645 u8 reserved_at_120[0xe0]; 4646 4647 struct mlx5_ifc_flow_context_bits flow_context; 4648 }; 4649 4650 struct mlx5_ifc_rts2rts_qp_out_bits { 4651 u8 status[0x8]; 4652 u8 reserved_at_8[0x18]; 4653 4654 u8 syndrome[0x20]; 4655 4656 u8 reserved_at_40[0x20]; 4657 u8 ece[0x20]; 4658 }; 4659 4660 struct mlx5_ifc_rts2rts_qp_in_bits { 4661 u8 opcode[0x10]; 4662 u8 uid[0x10]; 4663 4664 u8 reserved_at_20[0x10]; 4665 u8 op_mod[0x10]; 4666 4667 u8 reserved_at_40[0x8]; 4668 u8 qpn[0x18]; 4669 4670 u8 reserved_at_60[0x20]; 4671 4672 u8 opt_param_mask[0x20]; 4673 4674 u8 ece[0x20]; 4675 4676 struct mlx5_ifc_qpc_bits qpc; 4677 4678 u8 reserved_at_800[0x80]; 4679 }; 4680 4681 struct mlx5_ifc_rtr2rts_qp_out_bits { 4682 u8 status[0x8]; 4683 u8 reserved_at_8[0x18]; 4684 4685 u8 syndrome[0x20]; 4686 4687 u8 reserved_at_40[0x20]; 4688 u8 ece[0x20]; 4689 }; 4690 4691 struct mlx5_ifc_rtr2rts_qp_in_bits { 4692 u8 opcode[0x10]; 4693 u8 uid[0x10]; 4694 4695 u8 reserved_at_20[0x10]; 4696 u8 op_mod[0x10]; 4697 4698 u8 reserved_at_40[0x8]; 4699 u8 qpn[0x18]; 4700 4701 u8 reserved_at_60[0x20]; 4702 4703 u8 opt_param_mask[0x20]; 4704 4705 u8 ece[0x20]; 4706 4707 struct mlx5_ifc_qpc_bits qpc; 4708 4709 u8 reserved_at_800[0x80]; 4710 }; 4711 4712 struct mlx5_ifc_rst2init_qp_out_bits { 4713 u8 status[0x8]; 4714 u8 reserved_at_8[0x18]; 4715 4716 u8 syndrome[0x20]; 4717 4718 u8 reserved_at_40[0x20]; 4719 u8 ece[0x20]; 4720 }; 4721 4722 struct mlx5_ifc_rst2init_qp_in_bits { 4723 u8 opcode[0x10]; 4724 u8 uid[0x10]; 4725 4726 u8 reserved_at_20[0x10]; 4727 u8 op_mod[0x10]; 4728 4729 u8 reserved_at_40[0x8]; 4730 u8 qpn[0x18]; 4731 4732 u8 reserved_at_60[0x20]; 4733 4734 u8 opt_param_mask[0x20]; 4735 4736 u8 ece[0x20]; 4737 4738 struct mlx5_ifc_qpc_bits qpc; 4739 4740 u8 reserved_at_800[0x80]; 4741 }; 4742 4743 struct mlx5_ifc_query_xrq_out_bits { 4744 u8 status[0x8]; 4745 u8 reserved_at_8[0x18]; 4746 4747 u8 syndrome[0x20]; 4748 4749 u8 reserved_at_40[0x40]; 4750 4751 struct mlx5_ifc_xrqc_bits xrq_context; 4752 }; 4753 4754 struct mlx5_ifc_query_xrq_in_bits { 4755 u8 opcode[0x10]; 4756 u8 reserved_at_10[0x10]; 4757 4758 u8 reserved_at_20[0x10]; 4759 u8 op_mod[0x10]; 4760 4761 u8 reserved_at_40[0x8]; 4762 u8 xrqn[0x18]; 4763 4764 u8 reserved_at_60[0x20]; 4765 }; 4766 4767 struct mlx5_ifc_query_xrc_srq_out_bits { 4768 u8 status[0x8]; 4769 u8 reserved_at_8[0x18]; 4770 4771 u8 syndrome[0x20]; 4772 4773 u8 reserved_at_40[0x40]; 4774 4775 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 4776 4777 u8 reserved_at_280[0x600]; 4778 4779 u8 pas[][0x40]; 4780 }; 4781 4782 struct mlx5_ifc_query_xrc_srq_in_bits { 4783 u8 opcode[0x10]; 4784 u8 reserved_at_10[0x10]; 4785 4786 u8 reserved_at_20[0x10]; 4787 u8 op_mod[0x10]; 4788 4789 u8 reserved_at_40[0x8]; 4790 u8 xrc_srqn[0x18]; 4791 4792 u8 reserved_at_60[0x20]; 4793 }; 4794 4795 enum { 4796 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0, 4797 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1, 4798 }; 4799 4800 struct mlx5_ifc_query_vport_state_out_bits { 4801 u8 status[0x8]; 4802 u8 reserved_at_8[0x18]; 4803 4804 u8 syndrome[0x20]; 4805 4806 u8 reserved_at_40[0x20]; 4807 4808 u8 reserved_at_60[0x18]; 4809 u8 admin_state[0x4]; 4810 u8 state[0x4]; 4811 }; 4812 4813 enum { 4814 MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT = 0x0, 4815 MLX5_VPORT_STATE_OP_MOD_ESW_VPORT = 0x1, 4816 MLX5_VPORT_STATE_OP_MOD_UPLINK = 0x2, 4817 }; 4818 4819 struct mlx5_ifc_arm_monitor_counter_in_bits { 4820 u8 opcode[0x10]; 4821 u8 uid[0x10]; 4822 4823 u8 reserved_at_20[0x10]; 4824 u8 op_mod[0x10]; 4825 4826 u8 reserved_at_40[0x20]; 4827 4828 u8 reserved_at_60[0x20]; 4829 }; 4830 4831 struct mlx5_ifc_arm_monitor_counter_out_bits { 4832 u8 status[0x8]; 4833 u8 reserved_at_8[0x18]; 4834 4835 u8 syndrome[0x20]; 4836 4837 u8 reserved_at_40[0x40]; 4838 }; 4839 4840 enum { 4841 MLX5_QUERY_MONITOR_CNT_TYPE_PPCNT = 0x0, 4842 MLX5_QUERY_MONITOR_CNT_TYPE_Q_COUNTER = 0x1, 4843 }; 4844 4845 enum mlx5_monitor_counter_ppcnt { 4846 MLX5_QUERY_MONITOR_PPCNT_IN_RANGE_LENGTH_ERRORS = 0x0, 4847 MLX5_QUERY_MONITOR_PPCNT_OUT_OF_RANGE_LENGTH_FIELD = 0x1, 4848 MLX5_QUERY_MONITOR_PPCNT_FRAME_TOO_LONG_ERRORS = 0x2, 4849 MLX5_QUERY_MONITOR_PPCNT_FRAME_CHECK_SEQUENCE_ERRORS = 0x3, 4850 MLX5_QUERY_MONITOR_PPCNT_ALIGNMENT_ERRORS = 0x4, 4851 MLX5_QUERY_MONITOR_PPCNT_IF_OUT_DISCARDS = 0x5, 4852 }; 4853 4854 enum { 4855 MLX5_QUERY_MONITOR_Q_COUNTER_RX_OUT_OF_BUFFER = 0x4, 4856 }; 4857 4858 struct mlx5_ifc_monitor_counter_output_bits { 4859 u8 reserved_at_0[0x4]; 4860 u8 type[0x4]; 4861 u8 reserved_at_8[0x8]; 4862 u8 counter[0x10]; 4863 4864 u8 counter_group_id[0x20]; 4865 }; 4866 4867 #define MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 (6) 4868 #define MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1 (1) 4869 #define MLX5_CMD_SET_MONITOR_NUM_COUNTER (MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 +\ 4870 MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1) 4871 4872 struct mlx5_ifc_set_monitor_counter_in_bits { 4873 u8 opcode[0x10]; 4874 u8 uid[0x10]; 4875 4876 u8 reserved_at_20[0x10]; 4877 u8 op_mod[0x10]; 4878 4879 u8 reserved_at_40[0x10]; 4880 u8 num_of_counters[0x10]; 4881 4882 u8 reserved_at_60[0x20]; 4883 4884 struct mlx5_ifc_monitor_counter_output_bits monitor_counter[MLX5_CMD_SET_MONITOR_NUM_COUNTER]; 4885 }; 4886 4887 struct mlx5_ifc_set_monitor_counter_out_bits { 4888 u8 status[0x8]; 4889 u8 reserved_at_8[0x18]; 4890 4891 u8 syndrome[0x20]; 4892 4893 u8 reserved_at_40[0x40]; 4894 }; 4895 4896 struct mlx5_ifc_query_vport_state_in_bits { 4897 u8 opcode[0x10]; 4898 u8 reserved_at_10[0x10]; 4899 4900 u8 reserved_at_20[0x10]; 4901 u8 op_mod[0x10]; 4902 4903 u8 other_vport[0x1]; 4904 u8 reserved_at_41[0xf]; 4905 u8 vport_number[0x10]; 4906 4907 u8 reserved_at_60[0x20]; 4908 }; 4909 4910 struct mlx5_ifc_query_vnic_env_out_bits { 4911 u8 status[0x8]; 4912 u8 reserved_at_8[0x18]; 4913 4914 u8 syndrome[0x20]; 4915 4916 u8 reserved_at_40[0x40]; 4917 4918 struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env; 4919 }; 4920 4921 enum { 4922 MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS = 0x0, 4923 }; 4924 4925 struct mlx5_ifc_query_vnic_env_in_bits { 4926 u8 opcode[0x10]; 4927 u8 reserved_at_10[0x10]; 4928 4929 u8 reserved_at_20[0x10]; 4930 u8 op_mod[0x10]; 4931 4932 u8 other_vport[0x1]; 4933 u8 reserved_at_41[0xf]; 4934 u8 vport_number[0x10]; 4935 4936 u8 reserved_at_60[0x20]; 4937 }; 4938 4939 struct mlx5_ifc_query_vport_counter_out_bits { 4940 u8 status[0x8]; 4941 u8 reserved_at_8[0x18]; 4942 4943 u8 syndrome[0x20]; 4944 4945 u8 reserved_at_40[0x40]; 4946 4947 struct mlx5_ifc_traffic_counter_bits received_errors; 4948 4949 struct mlx5_ifc_traffic_counter_bits transmit_errors; 4950 4951 struct mlx5_ifc_traffic_counter_bits received_ib_unicast; 4952 4953 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast; 4954 4955 struct mlx5_ifc_traffic_counter_bits received_ib_multicast; 4956 4957 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast; 4958 4959 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast; 4960 4961 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast; 4962 4963 struct mlx5_ifc_traffic_counter_bits received_eth_unicast; 4964 4965 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast; 4966 4967 struct mlx5_ifc_traffic_counter_bits received_eth_multicast; 4968 4969 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast; 4970 4971 u8 reserved_at_680[0xa00]; 4972 }; 4973 4974 enum { 4975 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0, 4976 }; 4977 4978 struct mlx5_ifc_query_vport_counter_in_bits { 4979 u8 opcode[0x10]; 4980 u8 reserved_at_10[0x10]; 4981 4982 u8 reserved_at_20[0x10]; 4983 u8 op_mod[0x10]; 4984 4985 u8 other_vport[0x1]; 4986 u8 reserved_at_41[0xb]; 4987 u8 port_num[0x4]; 4988 u8 vport_number[0x10]; 4989 4990 u8 reserved_at_60[0x60]; 4991 4992 u8 clear[0x1]; 4993 u8 reserved_at_c1[0x1f]; 4994 4995 u8 reserved_at_e0[0x20]; 4996 }; 4997 4998 struct mlx5_ifc_query_tis_out_bits { 4999 u8 status[0x8]; 5000 u8 reserved_at_8[0x18]; 5001 5002 u8 syndrome[0x20]; 5003 5004 u8 reserved_at_40[0x40]; 5005 5006 struct mlx5_ifc_tisc_bits tis_context; 5007 }; 5008 5009 struct mlx5_ifc_query_tis_in_bits { 5010 u8 opcode[0x10]; 5011 u8 reserved_at_10[0x10]; 5012 5013 u8 reserved_at_20[0x10]; 5014 u8 op_mod[0x10]; 5015 5016 u8 reserved_at_40[0x8]; 5017 u8 tisn[0x18]; 5018 5019 u8 reserved_at_60[0x20]; 5020 }; 5021 5022 struct mlx5_ifc_query_tir_out_bits { 5023 u8 status[0x8]; 5024 u8 reserved_at_8[0x18]; 5025 5026 u8 syndrome[0x20]; 5027 5028 u8 reserved_at_40[0xc0]; 5029 5030 struct mlx5_ifc_tirc_bits tir_context; 5031 }; 5032 5033 struct mlx5_ifc_query_tir_in_bits { 5034 u8 opcode[0x10]; 5035 u8 reserved_at_10[0x10]; 5036 5037 u8 reserved_at_20[0x10]; 5038 u8 op_mod[0x10]; 5039 5040 u8 reserved_at_40[0x8]; 5041 u8 tirn[0x18]; 5042 5043 u8 reserved_at_60[0x20]; 5044 }; 5045 5046 struct mlx5_ifc_query_srq_out_bits { 5047 u8 status[0x8]; 5048 u8 reserved_at_8[0x18]; 5049 5050 u8 syndrome[0x20]; 5051 5052 u8 reserved_at_40[0x40]; 5053 5054 struct mlx5_ifc_srqc_bits srq_context_entry; 5055 5056 u8 reserved_at_280[0x600]; 5057 5058 u8 pas[][0x40]; 5059 }; 5060 5061 struct mlx5_ifc_query_srq_in_bits { 5062 u8 opcode[0x10]; 5063 u8 reserved_at_10[0x10]; 5064 5065 u8 reserved_at_20[0x10]; 5066 u8 op_mod[0x10]; 5067 5068 u8 reserved_at_40[0x8]; 5069 u8 srqn[0x18]; 5070 5071 u8 reserved_at_60[0x20]; 5072 }; 5073 5074 struct mlx5_ifc_query_sq_out_bits { 5075 u8 status[0x8]; 5076 u8 reserved_at_8[0x18]; 5077 5078 u8 syndrome[0x20]; 5079 5080 u8 reserved_at_40[0xc0]; 5081 5082 struct mlx5_ifc_sqc_bits sq_context; 5083 }; 5084 5085 struct mlx5_ifc_query_sq_in_bits { 5086 u8 opcode[0x10]; 5087 u8 reserved_at_10[0x10]; 5088 5089 u8 reserved_at_20[0x10]; 5090 u8 op_mod[0x10]; 5091 5092 u8 reserved_at_40[0x8]; 5093 u8 sqn[0x18]; 5094 5095 u8 reserved_at_60[0x20]; 5096 }; 5097 5098 struct mlx5_ifc_query_special_contexts_out_bits { 5099 u8 status[0x8]; 5100 u8 reserved_at_8[0x18]; 5101 5102 u8 syndrome[0x20]; 5103 5104 u8 dump_fill_mkey[0x20]; 5105 5106 u8 resd_lkey[0x20]; 5107 5108 u8 null_mkey[0x20]; 5109 5110 u8 reserved_at_a0[0x60]; 5111 }; 5112 5113 struct mlx5_ifc_query_special_contexts_in_bits { 5114 u8 opcode[0x10]; 5115 u8 reserved_at_10[0x10]; 5116 5117 u8 reserved_at_20[0x10]; 5118 u8 op_mod[0x10]; 5119 5120 u8 reserved_at_40[0x40]; 5121 }; 5122 5123 struct mlx5_ifc_query_scheduling_element_out_bits { 5124 u8 opcode[0x10]; 5125 u8 reserved_at_10[0x10]; 5126 5127 u8 reserved_at_20[0x10]; 5128 u8 op_mod[0x10]; 5129 5130 u8 reserved_at_40[0xc0]; 5131 5132 struct mlx5_ifc_scheduling_context_bits scheduling_context; 5133 5134 u8 reserved_at_300[0x100]; 5135 }; 5136 5137 enum { 5138 SCHEDULING_HIERARCHY_E_SWITCH = 0x2, 5139 SCHEDULING_HIERARCHY_NIC = 0x3, 5140 }; 5141 5142 struct mlx5_ifc_query_scheduling_element_in_bits { 5143 u8 opcode[0x10]; 5144 u8 reserved_at_10[0x10]; 5145 5146 u8 reserved_at_20[0x10]; 5147 u8 op_mod[0x10]; 5148 5149 u8 scheduling_hierarchy[0x8]; 5150 u8 reserved_at_48[0x18]; 5151 5152 u8 scheduling_element_id[0x20]; 5153 5154 u8 reserved_at_80[0x180]; 5155 }; 5156 5157 struct mlx5_ifc_query_rqt_out_bits { 5158 u8 status[0x8]; 5159 u8 reserved_at_8[0x18]; 5160 5161 u8 syndrome[0x20]; 5162 5163 u8 reserved_at_40[0xc0]; 5164 5165 struct mlx5_ifc_rqtc_bits rqt_context; 5166 }; 5167 5168 struct mlx5_ifc_query_rqt_in_bits { 5169 u8 opcode[0x10]; 5170 u8 reserved_at_10[0x10]; 5171 5172 u8 reserved_at_20[0x10]; 5173 u8 op_mod[0x10]; 5174 5175 u8 reserved_at_40[0x8]; 5176 u8 rqtn[0x18]; 5177 5178 u8 reserved_at_60[0x20]; 5179 }; 5180 5181 struct mlx5_ifc_query_rq_out_bits { 5182 u8 status[0x8]; 5183 u8 reserved_at_8[0x18]; 5184 5185 u8 syndrome[0x20]; 5186 5187 u8 reserved_at_40[0xc0]; 5188 5189 struct mlx5_ifc_rqc_bits rq_context; 5190 }; 5191 5192 struct mlx5_ifc_query_rq_in_bits { 5193 u8 opcode[0x10]; 5194 u8 reserved_at_10[0x10]; 5195 5196 u8 reserved_at_20[0x10]; 5197 u8 op_mod[0x10]; 5198 5199 u8 reserved_at_40[0x8]; 5200 u8 rqn[0x18]; 5201 5202 u8 reserved_at_60[0x20]; 5203 }; 5204 5205 struct mlx5_ifc_query_roce_address_out_bits { 5206 u8 status[0x8]; 5207 u8 reserved_at_8[0x18]; 5208 5209 u8 syndrome[0x20]; 5210 5211 u8 reserved_at_40[0x40]; 5212 5213 struct mlx5_ifc_roce_addr_layout_bits roce_address; 5214 }; 5215 5216 struct mlx5_ifc_query_roce_address_in_bits { 5217 u8 opcode[0x10]; 5218 u8 reserved_at_10[0x10]; 5219 5220 u8 reserved_at_20[0x10]; 5221 u8 op_mod[0x10]; 5222 5223 u8 roce_address_index[0x10]; 5224 u8 reserved_at_50[0xc]; 5225 u8 vhca_port_num[0x4]; 5226 5227 u8 reserved_at_60[0x20]; 5228 }; 5229 5230 struct mlx5_ifc_query_rmp_out_bits { 5231 u8 status[0x8]; 5232 u8 reserved_at_8[0x18]; 5233 5234 u8 syndrome[0x20]; 5235 5236 u8 reserved_at_40[0xc0]; 5237 5238 struct mlx5_ifc_rmpc_bits rmp_context; 5239 }; 5240 5241 struct mlx5_ifc_query_rmp_in_bits { 5242 u8 opcode[0x10]; 5243 u8 reserved_at_10[0x10]; 5244 5245 u8 reserved_at_20[0x10]; 5246 u8 op_mod[0x10]; 5247 5248 u8 reserved_at_40[0x8]; 5249 u8 rmpn[0x18]; 5250 5251 u8 reserved_at_60[0x20]; 5252 }; 5253 5254 struct mlx5_ifc_query_qp_out_bits { 5255 u8 status[0x8]; 5256 u8 reserved_at_8[0x18]; 5257 5258 u8 syndrome[0x20]; 5259 5260 u8 reserved_at_40[0x40]; 5261 5262 u8 opt_param_mask[0x20]; 5263 5264 u8 ece[0x20]; 5265 5266 struct mlx5_ifc_qpc_bits qpc; 5267 5268 u8 reserved_at_800[0x80]; 5269 5270 u8 pas[][0x40]; 5271 }; 5272 5273 struct mlx5_ifc_query_qp_in_bits { 5274 u8 opcode[0x10]; 5275 u8 reserved_at_10[0x10]; 5276 5277 u8 reserved_at_20[0x10]; 5278 u8 op_mod[0x10]; 5279 5280 u8 reserved_at_40[0x8]; 5281 u8 qpn[0x18]; 5282 5283 u8 reserved_at_60[0x20]; 5284 }; 5285 5286 struct mlx5_ifc_query_q_counter_out_bits { 5287 u8 status[0x8]; 5288 u8 reserved_at_8[0x18]; 5289 5290 u8 syndrome[0x20]; 5291 5292 u8 reserved_at_40[0x40]; 5293 5294 u8 rx_write_requests[0x20]; 5295 5296 u8 reserved_at_a0[0x20]; 5297 5298 u8 rx_read_requests[0x20]; 5299 5300 u8 reserved_at_e0[0x20]; 5301 5302 u8 rx_atomic_requests[0x20]; 5303 5304 u8 reserved_at_120[0x20]; 5305 5306 u8 rx_dct_connect[0x20]; 5307 5308 u8 reserved_at_160[0x20]; 5309 5310 u8 out_of_buffer[0x20]; 5311 5312 u8 reserved_at_1a0[0x20]; 5313 5314 u8 out_of_sequence[0x20]; 5315 5316 u8 reserved_at_1e0[0x20]; 5317 5318 u8 duplicate_request[0x20]; 5319 5320 u8 reserved_at_220[0x20]; 5321 5322 u8 rnr_nak_retry_err[0x20]; 5323 5324 u8 reserved_at_260[0x20]; 5325 5326 u8 packet_seq_err[0x20]; 5327 5328 u8 reserved_at_2a0[0x20]; 5329 5330 u8 implied_nak_seq_err[0x20]; 5331 5332 u8 reserved_at_2e0[0x20]; 5333 5334 u8 local_ack_timeout_err[0x20]; 5335 5336 u8 reserved_at_320[0xa0]; 5337 5338 u8 resp_local_length_error[0x20]; 5339 5340 u8 req_local_length_error[0x20]; 5341 5342 u8 resp_local_qp_error[0x20]; 5343 5344 u8 local_operation_error[0x20]; 5345 5346 u8 resp_local_protection[0x20]; 5347 5348 u8 req_local_protection[0x20]; 5349 5350 u8 resp_cqe_error[0x20]; 5351 5352 u8 req_cqe_error[0x20]; 5353 5354 u8 req_mw_binding[0x20]; 5355 5356 u8 req_bad_response[0x20]; 5357 5358 u8 req_remote_invalid_request[0x20]; 5359 5360 u8 resp_remote_invalid_request[0x20]; 5361 5362 u8 req_remote_access_errors[0x20]; 5363 5364 u8 resp_remote_access_errors[0x20]; 5365 5366 u8 req_remote_operation_errors[0x20]; 5367 5368 u8 req_transport_retries_exceeded[0x20]; 5369 5370 u8 cq_overflow[0x20]; 5371 5372 u8 resp_cqe_flush_error[0x20]; 5373 5374 u8 req_cqe_flush_error[0x20]; 5375 5376 u8 reserved_at_620[0x20]; 5377 5378 u8 roce_adp_retrans[0x20]; 5379 5380 u8 roce_adp_retrans_to[0x20]; 5381 5382 u8 roce_slow_restart[0x20]; 5383 5384 u8 roce_slow_restart_cnps[0x20]; 5385 5386 u8 roce_slow_restart_trans[0x20]; 5387 5388 u8 reserved_at_6e0[0x120]; 5389 }; 5390 5391 struct mlx5_ifc_query_q_counter_in_bits { 5392 u8 opcode[0x10]; 5393 u8 reserved_at_10[0x10]; 5394 5395 u8 reserved_at_20[0x10]; 5396 u8 op_mod[0x10]; 5397 5398 u8 reserved_at_40[0x80]; 5399 5400 u8 clear[0x1]; 5401 u8 reserved_at_c1[0x1f]; 5402 5403 u8 reserved_at_e0[0x18]; 5404 u8 counter_set_id[0x8]; 5405 }; 5406 5407 struct mlx5_ifc_query_pages_out_bits { 5408 u8 status[0x8]; 5409 u8 reserved_at_8[0x18]; 5410 5411 u8 syndrome[0x20]; 5412 5413 u8 embedded_cpu_function[0x1]; 5414 u8 reserved_at_41[0xf]; 5415 u8 function_id[0x10]; 5416 5417 u8 num_pages[0x20]; 5418 }; 5419 5420 enum { 5421 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1, 5422 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2, 5423 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3, 5424 }; 5425 5426 struct mlx5_ifc_query_pages_in_bits { 5427 u8 opcode[0x10]; 5428 u8 reserved_at_10[0x10]; 5429 5430 u8 reserved_at_20[0x10]; 5431 u8 op_mod[0x10]; 5432 5433 u8 embedded_cpu_function[0x1]; 5434 u8 reserved_at_41[0xf]; 5435 u8 function_id[0x10]; 5436 5437 u8 reserved_at_60[0x20]; 5438 }; 5439 5440 struct mlx5_ifc_query_nic_vport_context_out_bits { 5441 u8 status[0x8]; 5442 u8 reserved_at_8[0x18]; 5443 5444 u8 syndrome[0x20]; 5445 5446 u8 reserved_at_40[0x40]; 5447 5448 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 5449 }; 5450 5451 struct mlx5_ifc_query_nic_vport_context_in_bits { 5452 u8 opcode[0x10]; 5453 u8 reserved_at_10[0x10]; 5454 5455 u8 reserved_at_20[0x10]; 5456 u8 op_mod[0x10]; 5457 5458 u8 other_vport[0x1]; 5459 u8 reserved_at_41[0xf]; 5460 u8 vport_number[0x10]; 5461 5462 u8 reserved_at_60[0x5]; 5463 u8 allowed_list_type[0x3]; 5464 u8 reserved_at_68[0x18]; 5465 }; 5466 5467 struct mlx5_ifc_query_mkey_out_bits { 5468 u8 status[0x8]; 5469 u8 reserved_at_8[0x18]; 5470 5471 u8 syndrome[0x20]; 5472 5473 u8 reserved_at_40[0x40]; 5474 5475 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 5476 5477 u8 reserved_at_280[0x600]; 5478 5479 u8 bsf0_klm0_pas_mtt0_1[16][0x8]; 5480 5481 u8 bsf1_klm1_pas_mtt2_3[16][0x8]; 5482 }; 5483 5484 struct mlx5_ifc_query_mkey_in_bits { 5485 u8 opcode[0x10]; 5486 u8 reserved_at_10[0x10]; 5487 5488 u8 reserved_at_20[0x10]; 5489 u8 op_mod[0x10]; 5490 5491 u8 reserved_at_40[0x8]; 5492 u8 mkey_index[0x18]; 5493 5494 u8 pg_access[0x1]; 5495 u8 reserved_at_61[0x1f]; 5496 }; 5497 5498 struct mlx5_ifc_query_mad_demux_out_bits { 5499 u8 status[0x8]; 5500 u8 reserved_at_8[0x18]; 5501 5502 u8 syndrome[0x20]; 5503 5504 u8 reserved_at_40[0x40]; 5505 5506 u8 mad_dumux_parameters_block[0x20]; 5507 }; 5508 5509 struct mlx5_ifc_query_mad_demux_in_bits { 5510 u8 opcode[0x10]; 5511 u8 reserved_at_10[0x10]; 5512 5513 u8 reserved_at_20[0x10]; 5514 u8 op_mod[0x10]; 5515 5516 u8 reserved_at_40[0x40]; 5517 }; 5518 5519 struct mlx5_ifc_query_l2_table_entry_out_bits { 5520 u8 status[0x8]; 5521 u8 reserved_at_8[0x18]; 5522 5523 u8 syndrome[0x20]; 5524 5525 u8 reserved_at_40[0xa0]; 5526 5527 u8 reserved_at_e0[0x13]; 5528 u8 vlan_valid[0x1]; 5529 u8 vlan[0xc]; 5530 5531 struct mlx5_ifc_mac_address_layout_bits mac_address; 5532 5533 u8 reserved_at_140[0xc0]; 5534 }; 5535 5536 struct mlx5_ifc_query_l2_table_entry_in_bits { 5537 u8 opcode[0x10]; 5538 u8 reserved_at_10[0x10]; 5539 5540 u8 reserved_at_20[0x10]; 5541 u8 op_mod[0x10]; 5542 5543 u8 reserved_at_40[0x60]; 5544 5545 u8 reserved_at_a0[0x8]; 5546 u8 table_index[0x18]; 5547 5548 u8 reserved_at_c0[0x140]; 5549 }; 5550 5551 struct mlx5_ifc_query_issi_out_bits { 5552 u8 status[0x8]; 5553 u8 reserved_at_8[0x18]; 5554 5555 u8 syndrome[0x20]; 5556 5557 u8 reserved_at_40[0x10]; 5558 u8 current_issi[0x10]; 5559 5560 u8 reserved_at_60[0xa0]; 5561 5562 u8 reserved_at_100[76][0x8]; 5563 u8 supported_issi_dw0[0x20]; 5564 }; 5565 5566 struct mlx5_ifc_query_issi_in_bits { 5567 u8 opcode[0x10]; 5568 u8 reserved_at_10[0x10]; 5569 5570 u8 reserved_at_20[0x10]; 5571 u8 op_mod[0x10]; 5572 5573 u8 reserved_at_40[0x40]; 5574 }; 5575 5576 struct mlx5_ifc_set_driver_version_out_bits { 5577 u8 status[0x8]; 5578 u8 reserved_0[0x18]; 5579 5580 u8 syndrome[0x20]; 5581 u8 reserved_1[0x40]; 5582 }; 5583 5584 struct mlx5_ifc_set_driver_version_in_bits { 5585 u8 opcode[0x10]; 5586 u8 reserved_0[0x10]; 5587 5588 u8 reserved_1[0x10]; 5589 u8 op_mod[0x10]; 5590 5591 u8 reserved_2[0x40]; 5592 u8 driver_version[64][0x8]; 5593 }; 5594 5595 struct mlx5_ifc_query_hca_vport_pkey_out_bits { 5596 u8 status[0x8]; 5597 u8 reserved_at_8[0x18]; 5598 5599 u8 syndrome[0x20]; 5600 5601 u8 reserved_at_40[0x40]; 5602 5603 struct mlx5_ifc_pkey_bits pkey[]; 5604 }; 5605 5606 struct mlx5_ifc_query_hca_vport_pkey_in_bits { 5607 u8 opcode[0x10]; 5608 u8 reserved_at_10[0x10]; 5609 5610 u8 reserved_at_20[0x10]; 5611 u8 op_mod[0x10]; 5612 5613 u8 other_vport[0x1]; 5614 u8 reserved_at_41[0xb]; 5615 u8 port_num[0x4]; 5616 u8 vport_number[0x10]; 5617 5618 u8 reserved_at_60[0x10]; 5619 u8 pkey_index[0x10]; 5620 }; 5621 5622 enum { 5623 MLX5_HCA_VPORT_SEL_PORT_GUID = 1 << 0, 5624 MLX5_HCA_VPORT_SEL_NODE_GUID = 1 << 1, 5625 MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2, 5626 }; 5627 5628 struct mlx5_ifc_query_hca_vport_gid_out_bits { 5629 u8 status[0x8]; 5630 u8 reserved_at_8[0x18]; 5631 5632 u8 syndrome[0x20]; 5633 5634 u8 reserved_at_40[0x20]; 5635 5636 u8 gids_num[0x10]; 5637 u8 reserved_at_70[0x10]; 5638 5639 struct mlx5_ifc_array128_auto_bits gid[]; 5640 }; 5641 5642 struct mlx5_ifc_query_hca_vport_gid_in_bits { 5643 u8 opcode[0x10]; 5644 u8 reserved_at_10[0x10]; 5645 5646 u8 reserved_at_20[0x10]; 5647 u8 op_mod[0x10]; 5648 5649 u8 other_vport[0x1]; 5650 u8 reserved_at_41[0xb]; 5651 u8 port_num[0x4]; 5652 u8 vport_number[0x10]; 5653 5654 u8 reserved_at_60[0x10]; 5655 u8 gid_index[0x10]; 5656 }; 5657 5658 struct mlx5_ifc_query_hca_vport_context_out_bits { 5659 u8 status[0x8]; 5660 u8 reserved_at_8[0x18]; 5661 5662 u8 syndrome[0x20]; 5663 5664 u8 reserved_at_40[0x40]; 5665 5666 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 5667 }; 5668 5669 struct mlx5_ifc_query_hca_vport_context_in_bits { 5670 u8 opcode[0x10]; 5671 u8 reserved_at_10[0x10]; 5672 5673 u8 reserved_at_20[0x10]; 5674 u8 op_mod[0x10]; 5675 5676 u8 other_vport[0x1]; 5677 u8 reserved_at_41[0xb]; 5678 u8 port_num[0x4]; 5679 u8 vport_number[0x10]; 5680 5681 u8 reserved_at_60[0x20]; 5682 }; 5683 5684 struct mlx5_ifc_query_hca_cap_out_bits { 5685 u8 status[0x8]; 5686 u8 reserved_at_8[0x18]; 5687 5688 u8 syndrome[0x20]; 5689 5690 u8 reserved_at_40[0x40]; 5691 5692 union mlx5_ifc_hca_cap_union_bits capability; 5693 }; 5694 5695 struct mlx5_ifc_query_hca_cap_in_bits { 5696 u8 opcode[0x10]; 5697 u8 reserved_at_10[0x10]; 5698 5699 u8 reserved_at_20[0x10]; 5700 u8 op_mod[0x10]; 5701 5702 u8 other_function[0x1]; 5703 u8 reserved_at_41[0xf]; 5704 u8 function_id[0x10]; 5705 5706 u8 reserved_at_60[0x20]; 5707 }; 5708 5709 struct mlx5_ifc_other_hca_cap_bits { 5710 u8 roce[0x1]; 5711 u8 reserved_at_1[0x27f]; 5712 }; 5713 5714 struct mlx5_ifc_query_other_hca_cap_out_bits { 5715 u8 status[0x8]; 5716 u8 reserved_at_8[0x18]; 5717 5718 u8 syndrome[0x20]; 5719 5720 u8 reserved_at_40[0x40]; 5721 5722 struct mlx5_ifc_other_hca_cap_bits other_capability; 5723 }; 5724 5725 struct mlx5_ifc_query_other_hca_cap_in_bits { 5726 u8 opcode[0x10]; 5727 u8 reserved_at_10[0x10]; 5728 5729 u8 reserved_at_20[0x10]; 5730 u8 op_mod[0x10]; 5731 5732 u8 reserved_at_40[0x10]; 5733 u8 function_id[0x10]; 5734 5735 u8 reserved_at_60[0x20]; 5736 }; 5737 5738 struct mlx5_ifc_modify_other_hca_cap_out_bits { 5739 u8 status[0x8]; 5740 u8 reserved_at_8[0x18]; 5741 5742 u8 syndrome[0x20]; 5743 5744 u8 reserved_at_40[0x40]; 5745 }; 5746 5747 struct mlx5_ifc_modify_other_hca_cap_in_bits { 5748 u8 opcode[0x10]; 5749 u8 reserved_at_10[0x10]; 5750 5751 u8 reserved_at_20[0x10]; 5752 u8 op_mod[0x10]; 5753 5754 u8 reserved_at_40[0x10]; 5755 u8 function_id[0x10]; 5756 u8 field_select[0x20]; 5757 5758 struct mlx5_ifc_other_hca_cap_bits other_capability; 5759 }; 5760 5761 struct mlx5_ifc_flow_table_context_bits { 5762 u8 reformat_en[0x1]; 5763 u8 decap_en[0x1]; 5764 u8 sw_owner[0x1]; 5765 u8 termination_table[0x1]; 5766 u8 table_miss_action[0x4]; 5767 u8 level[0x8]; 5768 u8 reserved_at_10[0x8]; 5769 u8 log_size[0x8]; 5770 5771 u8 reserved_at_20[0x8]; 5772 u8 table_miss_id[0x18]; 5773 5774 u8 reserved_at_40[0x8]; 5775 u8 lag_master_next_table_id[0x18]; 5776 5777 u8 reserved_at_60[0x60]; 5778 5779 u8 sw_owner_icm_root_1[0x40]; 5780 5781 u8 sw_owner_icm_root_0[0x40]; 5782 5783 }; 5784 5785 struct mlx5_ifc_query_flow_table_out_bits { 5786 u8 status[0x8]; 5787 u8 reserved_at_8[0x18]; 5788 5789 u8 syndrome[0x20]; 5790 5791 u8 reserved_at_40[0x80]; 5792 5793 struct mlx5_ifc_flow_table_context_bits flow_table_context; 5794 }; 5795 5796 struct mlx5_ifc_query_flow_table_in_bits { 5797 u8 opcode[0x10]; 5798 u8 reserved_at_10[0x10]; 5799 5800 u8 reserved_at_20[0x10]; 5801 u8 op_mod[0x10]; 5802 5803 u8 reserved_at_40[0x40]; 5804 5805 u8 table_type[0x8]; 5806 u8 reserved_at_88[0x18]; 5807 5808 u8 reserved_at_a0[0x8]; 5809 u8 table_id[0x18]; 5810 5811 u8 reserved_at_c0[0x140]; 5812 }; 5813 5814 struct mlx5_ifc_query_fte_out_bits { 5815 u8 status[0x8]; 5816 u8 reserved_at_8[0x18]; 5817 5818 u8 syndrome[0x20]; 5819 5820 u8 reserved_at_40[0x1c0]; 5821 5822 struct mlx5_ifc_flow_context_bits flow_context; 5823 }; 5824 5825 struct mlx5_ifc_query_fte_in_bits { 5826 u8 opcode[0x10]; 5827 u8 reserved_at_10[0x10]; 5828 5829 u8 reserved_at_20[0x10]; 5830 u8 op_mod[0x10]; 5831 5832 u8 reserved_at_40[0x40]; 5833 5834 u8 table_type[0x8]; 5835 u8 reserved_at_88[0x18]; 5836 5837 u8 reserved_at_a0[0x8]; 5838 u8 table_id[0x18]; 5839 5840 u8 reserved_at_c0[0x40]; 5841 5842 u8 flow_index[0x20]; 5843 5844 u8 reserved_at_120[0xe0]; 5845 }; 5846 5847 struct mlx5_ifc_match_definer_format_0_bits { 5848 u8 reserved_at_0[0x100]; 5849 5850 u8 metadata_reg_c_0[0x20]; 5851 5852 u8 metadata_reg_c_1[0x20]; 5853 5854 u8 outer_dmac_47_16[0x20]; 5855 5856 u8 outer_dmac_15_0[0x10]; 5857 u8 outer_ethertype[0x10]; 5858 5859 u8 reserved_at_180[0x1]; 5860 u8 sx_sniffer[0x1]; 5861 u8 functional_lb[0x1]; 5862 u8 outer_ip_frag[0x1]; 5863 u8 outer_qp_type[0x2]; 5864 u8 outer_encap_type[0x2]; 5865 u8 port_number[0x2]; 5866 u8 outer_l3_type[0x2]; 5867 u8 outer_l4_type[0x2]; 5868 u8 outer_first_vlan_type[0x2]; 5869 u8 outer_first_vlan_prio[0x3]; 5870 u8 outer_first_vlan_cfi[0x1]; 5871 u8 outer_first_vlan_vid[0xc]; 5872 5873 u8 outer_l4_type_ext[0x4]; 5874 u8 reserved_at_1a4[0x2]; 5875 u8 outer_ipsec_layer[0x2]; 5876 u8 outer_l2_type[0x2]; 5877 u8 force_lb[0x1]; 5878 u8 outer_l2_ok[0x1]; 5879 u8 outer_l3_ok[0x1]; 5880 u8 outer_l4_ok[0x1]; 5881 u8 outer_second_vlan_type[0x2]; 5882 u8 outer_second_vlan_prio[0x3]; 5883 u8 outer_second_vlan_cfi[0x1]; 5884 u8 outer_second_vlan_vid[0xc]; 5885 5886 u8 outer_smac_47_16[0x20]; 5887 5888 u8 outer_smac_15_0[0x10]; 5889 u8 inner_ipv4_checksum_ok[0x1]; 5890 u8 inner_l4_checksum_ok[0x1]; 5891 u8 outer_ipv4_checksum_ok[0x1]; 5892 u8 outer_l4_checksum_ok[0x1]; 5893 u8 inner_l3_ok[0x1]; 5894 u8 inner_l4_ok[0x1]; 5895 u8 outer_l3_ok_duplicate[0x1]; 5896 u8 outer_l4_ok_duplicate[0x1]; 5897 u8 outer_tcp_cwr[0x1]; 5898 u8 outer_tcp_ece[0x1]; 5899 u8 outer_tcp_urg[0x1]; 5900 u8 outer_tcp_ack[0x1]; 5901 u8 outer_tcp_psh[0x1]; 5902 u8 outer_tcp_rst[0x1]; 5903 u8 outer_tcp_syn[0x1]; 5904 u8 outer_tcp_fin[0x1]; 5905 }; 5906 5907 struct mlx5_ifc_match_definer_format_22_bits { 5908 u8 reserved_at_0[0x100]; 5909 5910 u8 outer_ip_src_addr[0x20]; 5911 5912 u8 outer_ip_dest_addr[0x20]; 5913 5914 u8 outer_l4_sport[0x10]; 5915 u8 outer_l4_dport[0x10]; 5916 5917 u8 reserved_at_160[0x1]; 5918 u8 sx_sniffer[0x1]; 5919 u8 functional_lb[0x1]; 5920 u8 outer_ip_frag[0x1]; 5921 u8 outer_qp_type[0x2]; 5922 u8 outer_encap_type[0x2]; 5923 u8 port_number[0x2]; 5924 u8 outer_l3_type[0x2]; 5925 u8 outer_l4_type[0x2]; 5926 u8 outer_first_vlan_type[0x2]; 5927 u8 outer_first_vlan_prio[0x3]; 5928 u8 outer_first_vlan_cfi[0x1]; 5929 u8 outer_first_vlan_vid[0xc]; 5930 5931 u8 metadata_reg_c_0[0x20]; 5932 5933 u8 outer_dmac_47_16[0x20]; 5934 5935 u8 outer_smac_47_16[0x20]; 5936 5937 u8 outer_smac_15_0[0x10]; 5938 u8 outer_dmac_15_0[0x10]; 5939 }; 5940 5941 struct mlx5_ifc_match_definer_format_23_bits { 5942 u8 reserved_at_0[0x100]; 5943 5944 u8 inner_ip_src_addr[0x20]; 5945 5946 u8 inner_ip_dest_addr[0x20]; 5947 5948 u8 inner_l4_sport[0x10]; 5949 u8 inner_l4_dport[0x10]; 5950 5951 u8 reserved_at_160[0x1]; 5952 u8 sx_sniffer[0x1]; 5953 u8 functional_lb[0x1]; 5954 u8 inner_ip_frag[0x1]; 5955 u8 inner_qp_type[0x2]; 5956 u8 inner_encap_type[0x2]; 5957 u8 port_number[0x2]; 5958 u8 inner_l3_type[0x2]; 5959 u8 inner_l4_type[0x2]; 5960 u8 inner_first_vlan_type[0x2]; 5961 u8 inner_first_vlan_prio[0x3]; 5962 u8 inner_first_vlan_cfi[0x1]; 5963 u8 inner_first_vlan_vid[0xc]; 5964 5965 u8 tunnel_header_0[0x20]; 5966 5967 u8 inner_dmac_47_16[0x20]; 5968 5969 u8 inner_smac_47_16[0x20]; 5970 5971 u8 inner_smac_15_0[0x10]; 5972 u8 inner_dmac_15_0[0x10]; 5973 }; 5974 5975 struct mlx5_ifc_match_definer_format_29_bits { 5976 u8 reserved_at_0[0xc0]; 5977 5978 u8 outer_ip_dest_addr[0x80]; 5979 5980 u8 outer_ip_src_addr[0x80]; 5981 5982 u8 outer_l4_sport[0x10]; 5983 u8 outer_l4_dport[0x10]; 5984 5985 u8 reserved_at_1e0[0x20]; 5986 }; 5987 5988 struct mlx5_ifc_match_definer_format_30_bits { 5989 u8 reserved_at_0[0xa0]; 5990 5991 u8 outer_ip_dest_addr[0x80]; 5992 5993 u8 outer_ip_src_addr[0x80]; 5994 5995 u8 outer_dmac_47_16[0x20]; 5996 5997 u8 outer_smac_47_16[0x20]; 5998 5999 u8 outer_smac_15_0[0x10]; 6000 u8 outer_dmac_15_0[0x10]; 6001 }; 6002 6003 struct mlx5_ifc_match_definer_format_31_bits { 6004 u8 reserved_at_0[0xc0]; 6005 6006 u8 inner_ip_dest_addr[0x80]; 6007 6008 u8 inner_ip_src_addr[0x80]; 6009 6010 u8 inner_l4_sport[0x10]; 6011 u8 inner_l4_dport[0x10]; 6012 6013 u8 reserved_at_1e0[0x20]; 6014 }; 6015 6016 struct mlx5_ifc_match_definer_format_32_bits { 6017 u8 reserved_at_0[0xa0]; 6018 6019 u8 inner_ip_dest_addr[0x80]; 6020 6021 u8 inner_ip_src_addr[0x80]; 6022 6023 u8 inner_dmac_47_16[0x20]; 6024 6025 u8 inner_smac_47_16[0x20]; 6026 6027 u8 inner_smac_15_0[0x10]; 6028 u8 inner_dmac_15_0[0x10]; 6029 }; 6030 6031 struct mlx5_ifc_match_definer_bits { 6032 u8 modify_field_select[0x40]; 6033 6034 u8 reserved_at_40[0x40]; 6035 6036 u8 reserved_at_80[0x10]; 6037 u8 format_id[0x10]; 6038 6039 u8 reserved_at_a0[0x160]; 6040 6041 u8 match_mask[16][0x20]; 6042 }; 6043 6044 struct mlx5_ifc_general_obj_in_cmd_hdr_bits { 6045 u8 opcode[0x10]; 6046 u8 uid[0x10]; 6047 6048 u8 vhca_tunnel_id[0x10]; 6049 u8 obj_type[0x10]; 6050 6051 u8 obj_id[0x20]; 6052 6053 u8 reserved_at_60[0x3]; 6054 u8 log_obj_range[0x5]; 6055 u8 reserved_at_68[0x18]; 6056 }; 6057 6058 struct mlx5_ifc_general_obj_out_cmd_hdr_bits { 6059 u8 status[0x8]; 6060 u8 reserved_at_8[0x18]; 6061 6062 u8 syndrome[0x20]; 6063 6064 u8 obj_id[0x20]; 6065 6066 u8 reserved_at_60[0x20]; 6067 }; 6068 6069 struct mlx5_ifc_create_match_definer_in_bits { 6070 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 6071 6072 struct mlx5_ifc_match_definer_bits obj_context; 6073 }; 6074 6075 struct mlx5_ifc_create_match_definer_out_bits { 6076 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 6077 }; 6078 6079 enum { 6080 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 6081 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 6082 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 6083 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3, 6084 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_3 = 0x4, 6085 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_4 = 0x5, 6086 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_5 = 0x6, 6087 }; 6088 6089 struct mlx5_ifc_query_flow_group_out_bits { 6090 u8 status[0x8]; 6091 u8 reserved_at_8[0x18]; 6092 6093 u8 syndrome[0x20]; 6094 6095 u8 reserved_at_40[0xa0]; 6096 6097 u8 start_flow_index[0x20]; 6098 6099 u8 reserved_at_100[0x20]; 6100 6101 u8 end_flow_index[0x20]; 6102 6103 u8 reserved_at_140[0xa0]; 6104 6105 u8 reserved_at_1e0[0x18]; 6106 u8 match_criteria_enable[0x8]; 6107 6108 struct mlx5_ifc_fte_match_param_bits match_criteria; 6109 6110 u8 reserved_at_1200[0xe00]; 6111 }; 6112 6113 struct mlx5_ifc_query_flow_group_in_bits { 6114 u8 opcode[0x10]; 6115 u8 reserved_at_10[0x10]; 6116 6117 u8 reserved_at_20[0x10]; 6118 u8 op_mod[0x10]; 6119 6120 u8 reserved_at_40[0x40]; 6121 6122 u8 table_type[0x8]; 6123 u8 reserved_at_88[0x18]; 6124 6125 u8 reserved_at_a0[0x8]; 6126 u8 table_id[0x18]; 6127 6128 u8 group_id[0x20]; 6129 6130 u8 reserved_at_e0[0x120]; 6131 }; 6132 6133 struct mlx5_ifc_query_flow_counter_out_bits { 6134 u8 status[0x8]; 6135 u8 reserved_at_8[0x18]; 6136 6137 u8 syndrome[0x20]; 6138 6139 u8 reserved_at_40[0x40]; 6140 6141 struct mlx5_ifc_traffic_counter_bits flow_statistics[]; 6142 }; 6143 6144 struct mlx5_ifc_query_flow_counter_in_bits { 6145 u8 opcode[0x10]; 6146 u8 reserved_at_10[0x10]; 6147 6148 u8 reserved_at_20[0x10]; 6149 u8 op_mod[0x10]; 6150 6151 u8 reserved_at_40[0x80]; 6152 6153 u8 clear[0x1]; 6154 u8 reserved_at_c1[0xf]; 6155 u8 num_of_counters[0x10]; 6156 6157 u8 flow_counter_id[0x20]; 6158 }; 6159 6160 struct mlx5_ifc_query_esw_vport_context_out_bits { 6161 u8 status[0x8]; 6162 u8 reserved_at_8[0x18]; 6163 6164 u8 syndrome[0x20]; 6165 6166 u8 reserved_at_40[0x40]; 6167 6168 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 6169 }; 6170 6171 struct mlx5_ifc_query_esw_vport_context_in_bits { 6172 u8 opcode[0x10]; 6173 u8 reserved_at_10[0x10]; 6174 6175 u8 reserved_at_20[0x10]; 6176 u8 op_mod[0x10]; 6177 6178 u8 other_vport[0x1]; 6179 u8 reserved_at_41[0xf]; 6180 u8 vport_number[0x10]; 6181 6182 u8 reserved_at_60[0x20]; 6183 }; 6184 6185 struct mlx5_ifc_modify_esw_vport_context_out_bits { 6186 u8 status[0x8]; 6187 u8 reserved_at_8[0x18]; 6188 6189 u8 syndrome[0x20]; 6190 6191 u8 reserved_at_40[0x40]; 6192 }; 6193 6194 struct mlx5_ifc_esw_vport_context_fields_select_bits { 6195 u8 reserved_at_0[0x1b]; 6196 u8 fdb_to_vport_reg_c_id[0x1]; 6197 u8 vport_cvlan_insert[0x1]; 6198 u8 vport_svlan_insert[0x1]; 6199 u8 vport_cvlan_strip[0x1]; 6200 u8 vport_svlan_strip[0x1]; 6201 }; 6202 6203 struct mlx5_ifc_modify_esw_vport_context_in_bits { 6204 u8 opcode[0x10]; 6205 u8 reserved_at_10[0x10]; 6206 6207 u8 reserved_at_20[0x10]; 6208 u8 op_mod[0x10]; 6209 6210 u8 other_vport[0x1]; 6211 u8 reserved_at_41[0xf]; 6212 u8 vport_number[0x10]; 6213 6214 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select; 6215 6216 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 6217 }; 6218 6219 struct mlx5_ifc_query_eq_out_bits { 6220 u8 status[0x8]; 6221 u8 reserved_at_8[0x18]; 6222 6223 u8 syndrome[0x20]; 6224 6225 u8 reserved_at_40[0x40]; 6226 6227 struct mlx5_ifc_eqc_bits eq_context_entry; 6228 6229 u8 reserved_at_280[0x40]; 6230 6231 u8 event_bitmask[0x40]; 6232 6233 u8 reserved_at_300[0x580]; 6234 6235 u8 pas[][0x40]; 6236 }; 6237 6238 struct mlx5_ifc_query_eq_in_bits { 6239 u8 opcode[0x10]; 6240 u8 reserved_at_10[0x10]; 6241 6242 u8 reserved_at_20[0x10]; 6243 u8 op_mod[0x10]; 6244 6245 u8 reserved_at_40[0x18]; 6246 u8 eq_number[0x8]; 6247 6248 u8 reserved_at_60[0x20]; 6249 }; 6250 6251 struct mlx5_ifc_packet_reformat_context_in_bits { 6252 u8 reformat_type[0x8]; 6253 u8 reserved_at_8[0x4]; 6254 u8 reformat_param_0[0x4]; 6255 u8 reserved_at_10[0x6]; 6256 u8 reformat_data_size[0xa]; 6257 6258 u8 reformat_param_1[0x8]; 6259 u8 reserved_at_28[0x8]; 6260 u8 reformat_data[2][0x8]; 6261 6262 u8 more_reformat_data[][0x8]; 6263 }; 6264 6265 struct mlx5_ifc_query_packet_reformat_context_out_bits { 6266 u8 status[0x8]; 6267 u8 reserved_at_8[0x18]; 6268 6269 u8 syndrome[0x20]; 6270 6271 u8 reserved_at_40[0xa0]; 6272 6273 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context[]; 6274 }; 6275 6276 struct mlx5_ifc_query_packet_reformat_context_in_bits { 6277 u8 opcode[0x10]; 6278 u8 reserved_at_10[0x10]; 6279 6280 u8 reserved_at_20[0x10]; 6281 u8 op_mod[0x10]; 6282 6283 u8 packet_reformat_id[0x20]; 6284 6285 u8 reserved_at_60[0xa0]; 6286 }; 6287 6288 struct mlx5_ifc_alloc_packet_reformat_context_out_bits { 6289 u8 status[0x8]; 6290 u8 reserved_at_8[0x18]; 6291 6292 u8 syndrome[0x20]; 6293 6294 u8 packet_reformat_id[0x20]; 6295 6296 u8 reserved_at_60[0x20]; 6297 }; 6298 6299 enum { 6300 MLX5_REFORMAT_CONTEXT_ANCHOR_MAC_START = 0x1, 6301 MLX5_REFORMAT_CONTEXT_ANCHOR_IP_START = 0x7, 6302 MLX5_REFORMAT_CONTEXT_ANCHOR_TCP_UDP_START = 0x9, 6303 }; 6304 6305 enum mlx5_reformat_ctx_type { 6306 MLX5_REFORMAT_TYPE_L2_TO_VXLAN = 0x0, 6307 MLX5_REFORMAT_TYPE_L2_TO_NVGRE = 0x1, 6308 MLX5_REFORMAT_TYPE_L2_TO_L2_TUNNEL = 0x2, 6309 MLX5_REFORMAT_TYPE_L3_TUNNEL_TO_L2 = 0x3, 6310 MLX5_REFORMAT_TYPE_L2_TO_L3_TUNNEL = 0x4, 6311 MLX5_REFORMAT_TYPE_INSERT_HDR = 0xf, 6312 MLX5_REFORMAT_TYPE_REMOVE_HDR = 0x10, 6313 }; 6314 6315 struct mlx5_ifc_alloc_packet_reformat_context_in_bits { 6316 u8 opcode[0x10]; 6317 u8 reserved_at_10[0x10]; 6318 6319 u8 reserved_at_20[0x10]; 6320 u8 op_mod[0x10]; 6321 6322 u8 reserved_at_40[0xa0]; 6323 6324 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context; 6325 }; 6326 6327 struct mlx5_ifc_dealloc_packet_reformat_context_out_bits { 6328 u8 status[0x8]; 6329 u8 reserved_at_8[0x18]; 6330 6331 u8 syndrome[0x20]; 6332 6333 u8 reserved_at_40[0x40]; 6334 }; 6335 6336 struct mlx5_ifc_dealloc_packet_reformat_context_in_bits { 6337 u8 opcode[0x10]; 6338 u8 reserved_at_10[0x10]; 6339 6340 u8 reserved_20[0x10]; 6341 u8 op_mod[0x10]; 6342 6343 u8 packet_reformat_id[0x20]; 6344 6345 u8 reserved_60[0x20]; 6346 }; 6347 6348 struct mlx5_ifc_set_action_in_bits { 6349 u8 action_type[0x4]; 6350 u8 field[0xc]; 6351 u8 reserved_at_10[0x3]; 6352 u8 offset[0x5]; 6353 u8 reserved_at_18[0x3]; 6354 u8 length[0x5]; 6355 6356 u8 data[0x20]; 6357 }; 6358 6359 struct mlx5_ifc_add_action_in_bits { 6360 u8 action_type[0x4]; 6361 u8 field[0xc]; 6362 u8 reserved_at_10[0x10]; 6363 6364 u8 data[0x20]; 6365 }; 6366 6367 struct mlx5_ifc_copy_action_in_bits { 6368 u8 action_type[0x4]; 6369 u8 src_field[0xc]; 6370 u8 reserved_at_10[0x3]; 6371 u8 src_offset[0x5]; 6372 u8 reserved_at_18[0x3]; 6373 u8 length[0x5]; 6374 6375 u8 reserved_at_20[0x4]; 6376 u8 dst_field[0xc]; 6377 u8 reserved_at_30[0x3]; 6378 u8 dst_offset[0x5]; 6379 u8 reserved_at_38[0x8]; 6380 }; 6381 6382 union mlx5_ifc_set_add_copy_action_in_auto_bits { 6383 struct mlx5_ifc_set_action_in_bits set_action_in; 6384 struct mlx5_ifc_add_action_in_bits add_action_in; 6385 struct mlx5_ifc_copy_action_in_bits copy_action_in; 6386 u8 reserved_at_0[0x40]; 6387 }; 6388 6389 enum { 6390 MLX5_ACTION_TYPE_SET = 0x1, 6391 MLX5_ACTION_TYPE_ADD = 0x2, 6392 MLX5_ACTION_TYPE_COPY = 0x3, 6393 }; 6394 6395 enum { 6396 MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16 = 0x1, 6397 MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0 = 0x2, 6398 MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE = 0x3, 6399 MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16 = 0x4, 6400 MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0 = 0x5, 6401 MLX5_ACTION_IN_FIELD_OUT_IP_DSCP = 0x6, 6402 MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS = 0x7, 6403 MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT = 0x8, 6404 MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT = 0x9, 6405 MLX5_ACTION_IN_FIELD_OUT_IP_TTL = 0xa, 6406 MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT = 0xb, 6407 MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT = 0xc, 6408 MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96 = 0xd, 6409 MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64 = 0xe, 6410 MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32 = 0xf, 6411 MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0 = 0x10, 6412 MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96 = 0x11, 6413 MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64 = 0x12, 6414 MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32 = 0x13, 6415 MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0 = 0x14, 6416 MLX5_ACTION_IN_FIELD_OUT_SIPV4 = 0x15, 6417 MLX5_ACTION_IN_FIELD_OUT_DIPV4 = 0x16, 6418 MLX5_ACTION_IN_FIELD_OUT_FIRST_VID = 0x17, 6419 MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47, 6420 MLX5_ACTION_IN_FIELD_METADATA_REG_A = 0x49, 6421 MLX5_ACTION_IN_FIELD_METADATA_REG_B = 0x50, 6422 MLX5_ACTION_IN_FIELD_METADATA_REG_C_0 = 0x51, 6423 MLX5_ACTION_IN_FIELD_METADATA_REG_C_1 = 0x52, 6424 MLX5_ACTION_IN_FIELD_METADATA_REG_C_2 = 0x53, 6425 MLX5_ACTION_IN_FIELD_METADATA_REG_C_3 = 0x54, 6426 MLX5_ACTION_IN_FIELD_METADATA_REG_C_4 = 0x55, 6427 MLX5_ACTION_IN_FIELD_METADATA_REG_C_5 = 0x56, 6428 MLX5_ACTION_IN_FIELD_METADATA_REG_C_6 = 0x57, 6429 MLX5_ACTION_IN_FIELD_METADATA_REG_C_7 = 0x58, 6430 MLX5_ACTION_IN_FIELD_OUT_TCP_SEQ_NUM = 0x59, 6431 MLX5_ACTION_IN_FIELD_OUT_TCP_ACK_NUM = 0x5B, 6432 MLX5_ACTION_IN_FIELD_IPSEC_SYNDROME = 0x5D, 6433 MLX5_ACTION_IN_FIELD_OUT_EMD_47_32 = 0x6F, 6434 MLX5_ACTION_IN_FIELD_OUT_EMD_31_0 = 0x70, 6435 }; 6436 6437 struct mlx5_ifc_alloc_modify_header_context_out_bits { 6438 u8 status[0x8]; 6439 u8 reserved_at_8[0x18]; 6440 6441 u8 syndrome[0x20]; 6442 6443 u8 modify_header_id[0x20]; 6444 6445 u8 reserved_at_60[0x20]; 6446 }; 6447 6448 struct mlx5_ifc_alloc_modify_header_context_in_bits { 6449 u8 opcode[0x10]; 6450 u8 reserved_at_10[0x10]; 6451 6452 u8 reserved_at_20[0x10]; 6453 u8 op_mod[0x10]; 6454 6455 u8 reserved_at_40[0x20]; 6456 6457 u8 table_type[0x8]; 6458 u8 reserved_at_68[0x10]; 6459 u8 num_of_actions[0x8]; 6460 6461 union mlx5_ifc_set_add_copy_action_in_auto_bits actions[]; 6462 }; 6463 6464 struct mlx5_ifc_dealloc_modify_header_context_out_bits { 6465 u8 status[0x8]; 6466 u8 reserved_at_8[0x18]; 6467 6468 u8 syndrome[0x20]; 6469 6470 u8 reserved_at_40[0x40]; 6471 }; 6472 6473 struct mlx5_ifc_dealloc_modify_header_context_in_bits { 6474 u8 opcode[0x10]; 6475 u8 reserved_at_10[0x10]; 6476 6477 u8 reserved_at_20[0x10]; 6478 u8 op_mod[0x10]; 6479 6480 u8 modify_header_id[0x20]; 6481 6482 u8 reserved_at_60[0x20]; 6483 }; 6484 6485 struct mlx5_ifc_query_modify_header_context_in_bits { 6486 u8 opcode[0x10]; 6487 u8 uid[0x10]; 6488 6489 u8 reserved_at_20[0x10]; 6490 u8 op_mod[0x10]; 6491 6492 u8 modify_header_id[0x20]; 6493 6494 u8 reserved_at_60[0xa0]; 6495 }; 6496 6497 struct mlx5_ifc_query_dct_out_bits { 6498 u8 status[0x8]; 6499 u8 reserved_at_8[0x18]; 6500 6501 u8 syndrome[0x20]; 6502 6503 u8 reserved_at_40[0x40]; 6504 6505 struct mlx5_ifc_dctc_bits dct_context_entry; 6506 6507 u8 reserved_at_280[0x180]; 6508 }; 6509 6510 struct mlx5_ifc_query_dct_in_bits { 6511 u8 opcode[0x10]; 6512 u8 reserved_at_10[0x10]; 6513 6514 u8 reserved_at_20[0x10]; 6515 u8 op_mod[0x10]; 6516 6517 u8 reserved_at_40[0x8]; 6518 u8 dctn[0x18]; 6519 6520 u8 reserved_at_60[0x20]; 6521 }; 6522 6523 struct mlx5_ifc_query_cq_out_bits { 6524 u8 status[0x8]; 6525 u8 reserved_at_8[0x18]; 6526 6527 u8 syndrome[0x20]; 6528 6529 u8 reserved_at_40[0x40]; 6530 6531 struct mlx5_ifc_cqc_bits cq_context; 6532 6533 u8 reserved_at_280[0x600]; 6534 6535 u8 pas[][0x40]; 6536 }; 6537 6538 struct mlx5_ifc_query_cq_in_bits { 6539 u8 opcode[0x10]; 6540 u8 reserved_at_10[0x10]; 6541 6542 u8 reserved_at_20[0x10]; 6543 u8 op_mod[0x10]; 6544 6545 u8 reserved_at_40[0x8]; 6546 u8 cqn[0x18]; 6547 6548 u8 reserved_at_60[0x20]; 6549 }; 6550 6551 struct mlx5_ifc_query_cong_status_out_bits { 6552 u8 status[0x8]; 6553 u8 reserved_at_8[0x18]; 6554 6555 u8 syndrome[0x20]; 6556 6557 u8 reserved_at_40[0x20]; 6558 6559 u8 enable[0x1]; 6560 u8 tag_enable[0x1]; 6561 u8 reserved_at_62[0x1e]; 6562 }; 6563 6564 struct mlx5_ifc_query_cong_status_in_bits { 6565 u8 opcode[0x10]; 6566 u8 reserved_at_10[0x10]; 6567 6568 u8 reserved_at_20[0x10]; 6569 u8 op_mod[0x10]; 6570 6571 u8 reserved_at_40[0x18]; 6572 u8 priority[0x4]; 6573 u8 cong_protocol[0x4]; 6574 6575 u8 reserved_at_60[0x20]; 6576 }; 6577 6578 struct mlx5_ifc_query_cong_statistics_out_bits { 6579 u8 status[0x8]; 6580 u8 reserved_at_8[0x18]; 6581 6582 u8 syndrome[0x20]; 6583 6584 u8 reserved_at_40[0x40]; 6585 6586 u8 rp_cur_flows[0x20]; 6587 6588 u8 sum_flows[0x20]; 6589 6590 u8 rp_cnp_ignored_high[0x20]; 6591 6592 u8 rp_cnp_ignored_low[0x20]; 6593 6594 u8 rp_cnp_handled_high[0x20]; 6595 6596 u8 rp_cnp_handled_low[0x20]; 6597 6598 u8 reserved_at_140[0x100]; 6599 6600 u8 time_stamp_high[0x20]; 6601 6602 u8 time_stamp_low[0x20]; 6603 6604 u8 accumulators_period[0x20]; 6605 6606 u8 np_ecn_marked_roce_packets_high[0x20]; 6607 6608 u8 np_ecn_marked_roce_packets_low[0x20]; 6609 6610 u8 np_cnp_sent_high[0x20]; 6611 6612 u8 np_cnp_sent_low[0x20]; 6613 6614 u8 reserved_at_320[0x560]; 6615 }; 6616 6617 struct mlx5_ifc_query_cong_statistics_in_bits { 6618 u8 opcode[0x10]; 6619 u8 reserved_at_10[0x10]; 6620 6621 u8 reserved_at_20[0x10]; 6622 u8 op_mod[0x10]; 6623 6624 u8 clear[0x1]; 6625 u8 reserved_at_41[0x1f]; 6626 6627 u8 reserved_at_60[0x20]; 6628 }; 6629 6630 struct mlx5_ifc_query_cong_params_out_bits { 6631 u8 status[0x8]; 6632 u8 reserved_at_8[0x18]; 6633 6634 u8 syndrome[0x20]; 6635 6636 u8 reserved_at_40[0x40]; 6637 6638 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 6639 }; 6640 6641 struct mlx5_ifc_query_cong_params_in_bits { 6642 u8 opcode[0x10]; 6643 u8 reserved_at_10[0x10]; 6644 6645 u8 reserved_at_20[0x10]; 6646 u8 op_mod[0x10]; 6647 6648 u8 reserved_at_40[0x1c]; 6649 u8 cong_protocol[0x4]; 6650 6651 u8 reserved_at_60[0x20]; 6652 }; 6653 6654 struct mlx5_ifc_query_adapter_out_bits { 6655 u8 status[0x8]; 6656 u8 reserved_at_8[0x18]; 6657 6658 u8 syndrome[0x20]; 6659 6660 u8 reserved_at_40[0x40]; 6661 6662 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct; 6663 }; 6664 6665 struct mlx5_ifc_query_adapter_in_bits { 6666 u8 opcode[0x10]; 6667 u8 reserved_at_10[0x10]; 6668 6669 u8 reserved_at_20[0x10]; 6670 u8 op_mod[0x10]; 6671 6672 u8 reserved_at_40[0x40]; 6673 }; 6674 6675 struct mlx5_ifc_qp_2rst_out_bits { 6676 u8 status[0x8]; 6677 u8 reserved_at_8[0x18]; 6678 6679 u8 syndrome[0x20]; 6680 6681 u8 reserved_at_40[0x40]; 6682 }; 6683 6684 struct mlx5_ifc_qp_2rst_in_bits { 6685 u8 opcode[0x10]; 6686 u8 uid[0x10]; 6687 6688 u8 reserved_at_20[0x10]; 6689 u8 op_mod[0x10]; 6690 6691 u8 reserved_at_40[0x8]; 6692 u8 qpn[0x18]; 6693 6694 u8 reserved_at_60[0x20]; 6695 }; 6696 6697 struct mlx5_ifc_qp_2err_out_bits { 6698 u8 status[0x8]; 6699 u8 reserved_at_8[0x18]; 6700 6701 u8 syndrome[0x20]; 6702 6703 u8 reserved_at_40[0x40]; 6704 }; 6705 6706 struct mlx5_ifc_qp_2err_in_bits { 6707 u8 opcode[0x10]; 6708 u8 uid[0x10]; 6709 6710 u8 reserved_at_20[0x10]; 6711 u8 op_mod[0x10]; 6712 6713 u8 reserved_at_40[0x8]; 6714 u8 qpn[0x18]; 6715 6716 u8 reserved_at_60[0x20]; 6717 }; 6718 6719 struct mlx5_ifc_page_fault_resume_out_bits { 6720 u8 status[0x8]; 6721 u8 reserved_at_8[0x18]; 6722 6723 u8 syndrome[0x20]; 6724 6725 u8 reserved_at_40[0x40]; 6726 }; 6727 6728 struct mlx5_ifc_page_fault_resume_in_bits { 6729 u8 opcode[0x10]; 6730 u8 reserved_at_10[0x10]; 6731 6732 u8 reserved_at_20[0x10]; 6733 u8 op_mod[0x10]; 6734 6735 u8 error[0x1]; 6736 u8 reserved_at_41[0x4]; 6737 u8 page_fault_type[0x3]; 6738 u8 wq_number[0x18]; 6739 6740 u8 reserved_at_60[0x8]; 6741 u8 token[0x18]; 6742 }; 6743 6744 struct mlx5_ifc_nop_out_bits { 6745 u8 status[0x8]; 6746 u8 reserved_at_8[0x18]; 6747 6748 u8 syndrome[0x20]; 6749 6750 u8 reserved_at_40[0x40]; 6751 }; 6752 6753 struct mlx5_ifc_nop_in_bits { 6754 u8 opcode[0x10]; 6755 u8 reserved_at_10[0x10]; 6756 6757 u8 reserved_at_20[0x10]; 6758 u8 op_mod[0x10]; 6759 6760 u8 reserved_at_40[0x40]; 6761 }; 6762 6763 struct mlx5_ifc_modify_vport_state_out_bits { 6764 u8 status[0x8]; 6765 u8 reserved_at_8[0x18]; 6766 6767 u8 syndrome[0x20]; 6768 6769 u8 reserved_at_40[0x40]; 6770 }; 6771 6772 struct mlx5_ifc_modify_vport_state_in_bits { 6773 u8 opcode[0x10]; 6774 u8 reserved_at_10[0x10]; 6775 6776 u8 reserved_at_20[0x10]; 6777 u8 op_mod[0x10]; 6778 6779 u8 other_vport[0x1]; 6780 u8 reserved_at_41[0xf]; 6781 u8 vport_number[0x10]; 6782 6783 u8 reserved_at_60[0x18]; 6784 u8 admin_state[0x4]; 6785 u8 reserved_at_7c[0x4]; 6786 }; 6787 6788 struct mlx5_ifc_modify_tis_out_bits { 6789 u8 status[0x8]; 6790 u8 reserved_at_8[0x18]; 6791 6792 u8 syndrome[0x20]; 6793 6794 u8 reserved_at_40[0x40]; 6795 }; 6796 6797 struct mlx5_ifc_modify_tis_bitmask_bits { 6798 u8 reserved_at_0[0x20]; 6799 6800 u8 reserved_at_20[0x1d]; 6801 u8 lag_tx_port_affinity[0x1]; 6802 u8 strict_lag_tx_port_affinity[0x1]; 6803 u8 prio[0x1]; 6804 }; 6805 6806 struct mlx5_ifc_modify_tis_in_bits { 6807 u8 opcode[0x10]; 6808 u8 uid[0x10]; 6809 6810 u8 reserved_at_20[0x10]; 6811 u8 op_mod[0x10]; 6812 6813 u8 reserved_at_40[0x8]; 6814 u8 tisn[0x18]; 6815 6816 u8 reserved_at_60[0x20]; 6817 6818 struct mlx5_ifc_modify_tis_bitmask_bits bitmask; 6819 6820 u8 reserved_at_c0[0x40]; 6821 6822 struct mlx5_ifc_tisc_bits ctx; 6823 }; 6824 6825 struct mlx5_ifc_modify_tir_bitmask_bits { 6826 u8 reserved_at_0[0x20]; 6827 6828 u8 reserved_at_20[0x1b]; 6829 u8 self_lb_en[0x1]; 6830 u8 reserved_at_3c[0x1]; 6831 u8 hash[0x1]; 6832 u8 reserved_at_3e[0x1]; 6833 u8 packet_merge[0x1]; 6834 }; 6835 6836 struct mlx5_ifc_modify_tir_out_bits { 6837 u8 status[0x8]; 6838 u8 reserved_at_8[0x18]; 6839 6840 u8 syndrome[0x20]; 6841 6842 u8 reserved_at_40[0x40]; 6843 }; 6844 6845 struct mlx5_ifc_modify_tir_in_bits { 6846 u8 opcode[0x10]; 6847 u8 uid[0x10]; 6848 6849 u8 reserved_at_20[0x10]; 6850 u8 op_mod[0x10]; 6851 6852 u8 reserved_at_40[0x8]; 6853 u8 tirn[0x18]; 6854 6855 u8 reserved_at_60[0x20]; 6856 6857 struct mlx5_ifc_modify_tir_bitmask_bits bitmask; 6858 6859 u8 reserved_at_c0[0x40]; 6860 6861 struct mlx5_ifc_tirc_bits ctx; 6862 }; 6863 6864 struct mlx5_ifc_modify_sq_out_bits { 6865 u8 status[0x8]; 6866 u8 reserved_at_8[0x18]; 6867 6868 u8 syndrome[0x20]; 6869 6870 u8 reserved_at_40[0x40]; 6871 }; 6872 6873 struct mlx5_ifc_modify_sq_in_bits { 6874 u8 opcode[0x10]; 6875 u8 uid[0x10]; 6876 6877 u8 reserved_at_20[0x10]; 6878 u8 op_mod[0x10]; 6879 6880 u8 sq_state[0x4]; 6881 u8 reserved_at_44[0x4]; 6882 u8 sqn[0x18]; 6883 6884 u8 reserved_at_60[0x20]; 6885 6886 u8 modify_bitmask[0x40]; 6887 6888 u8 reserved_at_c0[0x40]; 6889 6890 struct mlx5_ifc_sqc_bits ctx; 6891 }; 6892 6893 struct mlx5_ifc_modify_scheduling_element_out_bits { 6894 u8 status[0x8]; 6895 u8 reserved_at_8[0x18]; 6896 6897 u8 syndrome[0x20]; 6898 6899 u8 reserved_at_40[0x1c0]; 6900 }; 6901 6902 enum { 6903 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1, 6904 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2, 6905 }; 6906 6907 struct mlx5_ifc_modify_scheduling_element_in_bits { 6908 u8 opcode[0x10]; 6909 u8 reserved_at_10[0x10]; 6910 6911 u8 reserved_at_20[0x10]; 6912 u8 op_mod[0x10]; 6913 6914 u8 scheduling_hierarchy[0x8]; 6915 u8 reserved_at_48[0x18]; 6916 6917 u8 scheduling_element_id[0x20]; 6918 6919 u8 reserved_at_80[0x20]; 6920 6921 u8 modify_bitmask[0x20]; 6922 6923 u8 reserved_at_c0[0x40]; 6924 6925 struct mlx5_ifc_scheduling_context_bits scheduling_context; 6926 6927 u8 reserved_at_300[0x100]; 6928 }; 6929 6930 struct mlx5_ifc_modify_rqt_out_bits { 6931 u8 status[0x8]; 6932 u8 reserved_at_8[0x18]; 6933 6934 u8 syndrome[0x20]; 6935 6936 u8 reserved_at_40[0x40]; 6937 }; 6938 6939 struct mlx5_ifc_rqt_bitmask_bits { 6940 u8 reserved_at_0[0x20]; 6941 6942 u8 reserved_at_20[0x1f]; 6943 u8 rqn_list[0x1]; 6944 }; 6945 6946 struct mlx5_ifc_modify_rqt_in_bits { 6947 u8 opcode[0x10]; 6948 u8 uid[0x10]; 6949 6950 u8 reserved_at_20[0x10]; 6951 u8 op_mod[0x10]; 6952 6953 u8 reserved_at_40[0x8]; 6954 u8 rqtn[0x18]; 6955 6956 u8 reserved_at_60[0x20]; 6957 6958 struct mlx5_ifc_rqt_bitmask_bits bitmask; 6959 6960 u8 reserved_at_c0[0x40]; 6961 6962 struct mlx5_ifc_rqtc_bits ctx; 6963 }; 6964 6965 struct mlx5_ifc_modify_rq_out_bits { 6966 u8 status[0x8]; 6967 u8 reserved_at_8[0x18]; 6968 6969 u8 syndrome[0x20]; 6970 6971 u8 reserved_at_40[0x40]; 6972 }; 6973 6974 enum { 6975 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1, 6976 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2, 6977 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3, 6978 }; 6979 6980 struct mlx5_ifc_modify_rq_in_bits { 6981 u8 opcode[0x10]; 6982 u8 uid[0x10]; 6983 6984 u8 reserved_at_20[0x10]; 6985 u8 op_mod[0x10]; 6986 6987 u8 rq_state[0x4]; 6988 u8 reserved_at_44[0x4]; 6989 u8 rqn[0x18]; 6990 6991 u8 reserved_at_60[0x20]; 6992 6993 u8 modify_bitmask[0x40]; 6994 6995 u8 reserved_at_c0[0x40]; 6996 6997 struct mlx5_ifc_rqc_bits ctx; 6998 }; 6999 7000 struct mlx5_ifc_modify_rmp_out_bits { 7001 u8 status[0x8]; 7002 u8 reserved_at_8[0x18]; 7003 7004 u8 syndrome[0x20]; 7005 7006 u8 reserved_at_40[0x40]; 7007 }; 7008 7009 struct mlx5_ifc_rmp_bitmask_bits { 7010 u8 reserved_at_0[0x20]; 7011 7012 u8 reserved_at_20[0x1f]; 7013 u8 lwm[0x1]; 7014 }; 7015 7016 struct mlx5_ifc_modify_rmp_in_bits { 7017 u8 opcode[0x10]; 7018 u8 uid[0x10]; 7019 7020 u8 reserved_at_20[0x10]; 7021 u8 op_mod[0x10]; 7022 7023 u8 rmp_state[0x4]; 7024 u8 reserved_at_44[0x4]; 7025 u8 rmpn[0x18]; 7026 7027 u8 reserved_at_60[0x20]; 7028 7029 struct mlx5_ifc_rmp_bitmask_bits bitmask; 7030 7031 u8 reserved_at_c0[0x40]; 7032 7033 struct mlx5_ifc_rmpc_bits ctx; 7034 }; 7035 7036 struct mlx5_ifc_modify_nic_vport_context_out_bits { 7037 u8 status[0x8]; 7038 u8 reserved_at_8[0x18]; 7039 7040 u8 syndrome[0x20]; 7041 7042 u8 reserved_at_40[0x40]; 7043 }; 7044 7045 struct mlx5_ifc_modify_nic_vport_field_select_bits { 7046 u8 reserved_at_0[0x12]; 7047 u8 affiliation[0x1]; 7048 u8 reserved_at_13[0x1]; 7049 u8 disable_uc_local_lb[0x1]; 7050 u8 disable_mc_local_lb[0x1]; 7051 u8 node_guid[0x1]; 7052 u8 port_guid[0x1]; 7053 u8 min_inline[0x1]; 7054 u8 mtu[0x1]; 7055 u8 change_event[0x1]; 7056 u8 promisc[0x1]; 7057 u8 permanent_address[0x1]; 7058 u8 addresses_list[0x1]; 7059 u8 roce_en[0x1]; 7060 u8 reserved_at_1f[0x1]; 7061 }; 7062 7063 struct mlx5_ifc_modify_nic_vport_context_in_bits { 7064 u8 opcode[0x10]; 7065 u8 reserved_at_10[0x10]; 7066 7067 u8 reserved_at_20[0x10]; 7068 u8 op_mod[0x10]; 7069 7070 u8 other_vport[0x1]; 7071 u8 reserved_at_41[0xf]; 7072 u8 vport_number[0x10]; 7073 7074 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select; 7075 7076 u8 reserved_at_80[0x780]; 7077 7078 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 7079 }; 7080 7081 struct mlx5_ifc_modify_hca_vport_context_out_bits { 7082 u8 status[0x8]; 7083 u8 reserved_at_8[0x18]; 7084 7085 u8 syndrome[0x20]; 7086 7087 u8 reserved_at_40[0x40]; 7088 }; 7089 7090 struct mlx5_ifc_modify_hca_vport_context_in_bits { 7091 u8 opcode[0x10]; 7092 u8 reserved_at_10[0x10]; 7093 7094 u8 reserved_at_20[0x10]; 7095 u8 op_mod[0x10]; 7096 7097 u8 other_vport[0x1]; 7098 u8 reserved_at_41[0xb]; 7099 u8 port_num[0x4]; 7100 u8 vport_number[0x10]; 7101 7102 u8 reserved_at_60[0x20]; 7103 7104 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 7105 }; 7106 7107 struct mlx5_ifc_modify_cq_out_bits { 7108 u8 status[0x8]; 7109 u8 reserved_at_8[0x18]; 7110 7111 u8 syndrome[0x20]; 7112 7113 u8 reserved_at_40[0x40]; 7114 }; 7115 7116 enum { 7117 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0, 7118 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1, 7119 }; 7120 7121 struct mlx5_ifc_modify_cq_in_bits { 7122 u8 opcode[0x10]; 7123 u8 uid[0x10]; 7124 7125 u8 reserved_at_20[0x10]; 7126 u8 op_mod[0x10]; 7127 7128 u8 reserved_at_40[0x8]; 7129 u8 cqn[0x18]; 7130 7131 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select; 7132 7133 struct mlx5_ifc_cqc_bits cq_context; 7134 7135 u8 reserved_at_280[0x60]; 7136 7137 u8 cq_umem_valid[0x1]; 7138 u8 reserved_at_2e1[0x1f]; 7139 7140 u8 reserved_at_300[0x580]; 7141 7142 u8 pas[][0x40]; 7143 }; 7144 7145 struct mlx5_ifc_modify_cong_status_out_bits { 7146 u8 status[0x8]; 7147 u8 reserved_at_8[0x18]; 7148 7149 u8 syndrome[0x20]; 7150 7151 u8 reserved_at_40[0x40]; 7152 }; 7153 7154 struct mlx5_ifc_modify_cong_status_in_bits { 7155 u8 opcode[0x10]; 7156 u8 reserved_at_10[0x10]; 7157 7158 u8 reserved_at_20[0x10]; 7159 u8 op_mod[0x10]; 7160 7161 u8 reserved_at_40[0x18]; 7162 u8 priority[0x4]; 7163 u8 cong_protocol[0x4]; 7164 7165 u8 enable[0x1]; 7166 u8 tag_enable[0x1]; 7167 u8 reserved_at_62[0x1e]; 7168 }; 7169 7170 struct mlx5_ifc_modify_cong_params_out_bits { 7171 u8 status[0x8]; 7172 u8 reserved_at_8[0x18]; 7173 7174 u8 syndrome[0x20]; 7175 7176 u8 reserved_at_40[0x40]; 7177 }; 7178 7179 struct mlx5_ifc_modify_cong_params_in_bits { 7180 u8 opcode[0x10]; 7181 u8 reserved_at_10[0x10]; 7182 7183 u8 reserved_at_20[0x10]; 7184 u8 op_mod[0x10]; 7185 7186 u8 reserved_at_40[0x1c]; 7187 u8 cong_protocol[0x4]; 7188 7189 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select; 7190 7191 u8 reserved_at_80[0x80]; 7192 7193 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 7194 }; 7195 7196 struct mlx5_ifc_manage_pages_out_bits { 7197 u8 status[0x8]; 7198 u8 reserved_at_8[0x18]; 7199 7200 u8 syndrome[0x20]; 7201 7202 u8 output_num_entries[0x20]; 7203 7204 u8 reserved_at_60[0x20]; 7205 7206 u8 pas[][0x40]; 7207 }; 7208 7209 enum { 7210 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL = 0x0, 7211 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS = 0x1, 7212 MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES = 0x2, 7213 }; 7214 7215 struct mlx5_ifc_manage_pages_in_bits { 7216 u8 opcode[0x10]; 7217 u8 reserved_at_10[0x10]; 7218 7219 u8 reserved_at_20[0x10]; 7220 u8 op_mod[0x10]; 7221 7222 u8 embedded_cpu_function[0x1]; 7223 u8 reserved_at_41[0xf]; 7224 u8 function_id[0x10]; 7225 7226 u8 input_num_entries[0x20]; 7227 7228 u8 pas[][0x40]; 7229 }; 7230 7231 struct mlx5_ifc_mad_ifc_out_bits { 7232 u8 status[0x8]; 7233 u8 reserved_at_8[0x18]; 7234 7235 u8 syndrome[0x20]; 7236 7237 u8 reserved_at_40[0x40]; 7238 7239 u8 response_mad_packet[256][0x8]; 7240 }; 7241 7242 struct mlx5_ifc_mad_ifc_in_bits { 7243 u8 opcode[0x10]; 7244 u8 reserved_at_10[0x10]; 7245 7246 u8 reserved_at_20[0x10]; 7247 u8 op_mod[0x10]; 7248 7249 u8 remote_lid[0x10]; 7250 u8 reserved_at_50[0x8]; 7251 u8 port[0x8]; 7252 7253 u8 reserved_at_60[0x20]; 7254 7255 u8 mad[256][0x8]; 7256 }; 7257 7258 struct mlx5_ifc_init_hca_out_bits { 7259 u8 status[0x8]; 7260 u8 reserved_at_8[0x18]; 7261 7262 u8 syndrome[0x20]; 7263 7264 u8 reserved_at_40[0x40]; 7265 }; 7266 7267 struct mlx5_ifc_init_hca_in_bits { 7268 u8 opcode[0x10]; 7269 u8 reserved_at_10[0x10]; 7270 7271 u8 reserved_at_20[0x10]; 7272 u8 op_mod[0x10]; 7273 7274 u8 reserved_at_40[0x20]; 7275 7276 u8 reserved_at_60[0x2]; 7277 u8 sw_vhca_id[0xe]; 7278 u8 reserved_at_70[0x10]; 7279 7280 u8 sw_owner_id[4][0x20]; 7281 }; 7282 7283 struct mlx5_ifc_init2rtr_qp_out_bits { 7284 u8 status[0x8]; 7285 u8 reserved_at_8[0x18]; 7286 7287 u8 syndrome[0x20]; 7288 7289 u8 reserved_at_40[0x20]; 7290 u8 ece[0x20]; 7291 }; 7292 7293 struct mlx5_ifc_init2rtr_qp_in_bits { 7294 u8 opcode[0x10]; 7295 u8 uid[0x10]; 7296 7297 u8 reserved_at_20[0x10]; 7298 u8 op_mod[0x10]; 7299 7300 u8 reserved_at_40[0x8]; 7301 u8 qpn[0x18]; 7302 7303 u8 reserved_at_60[0x20]; 7304 7305 u8 opt_param_mask[0x20]; 7306 7307 u8 ece[0x20]; 7308 7309 struct mlx5_ifc_qpc_bits qpc; 7310 7311 u8 reserved_at_800[0x80]; 7312 }; 7313 7314 struct mlx5_ifc_init2init_qp_out_bits { 7315 u8 status[0x8]; 7316 u8 reserved_at_8[0x18]; 7317 7318 u8 syndrome[0x20]; 7319 7320 u8 reserved_at_40[0x20]; 7321 u8 ece[0x20]; 7322 }; 7323 7324 struct mlx5_ifc_init2init_qp_in_bits { 7325 u8 opcode[0x10]; 7326 u8 uid[0x10]; 7327 7328 u8 reserved_at_20[0x10]; 7329 u8 op_mod[0x10]; 7330 7331 u8 reserved_at_40[0x8]; 7332 u8 qpn[0x18]; 7333 7334 u8 reserved_at_60[0x20]; 7335 7336 u8 opt_param_mask[0x20]; 7337 7338 u8 ece[0x20]; 7339 7340 struct mlx5_ifc_qpc_bits qpc; 7341 7342 u8 reserved_at_800[0x80]; 7343 }; 7344 7345 struct mlx5_ifc_get_dropped_packet_log_out_bits { 7346 u8 status[0x8]; 7347 u8 reserved_at_8[0x18]; 7348 7349 u8 syndrome[0x20]; 7350 7351 u8 reserved_at_40[0x40]; 7352 7353 u8 packet_headers_log[128][0x8]; 7354 7355 u8 packet_syndrome[64][0x8]; 7356 }; 7357 7358 struct mlx5_ifc_get_dropped_packet_log_in_bits { 7359 u8 opcode[0x10]; 7360 u8 reserved_at_10[0x10]; 7361 7362 u8 reserved_at_20[0x10]; 7363 u8 op_mod[0x10]; 7364 7365 u8 reserved_at_40[0x40]; 7366 }; 7367 7368 struct mlx5_ifc_gen_eqe_in_bits { 7369 u8 opcode[0x10]; 7370 u8 reserved_at_10[0x10]; 7371 7372 u8 reserved_at_20[0x10]; 7373 u8 op_mod[0x10]; 7374 7375 u8 reserved_at_40[0x18]; 7376 u8 eq_number[0x8]; 7377 7378 u8 reserved_at_60[0x20]; 7379 7380 u8 eqe[64][0x8]; 7381 }; 7382 7383 struct mlx5_ifc_gen_eq_out_bits { 7384 u8 status[0x8]; 7385 u8 reserved_at_8[0x18]; 7386 7387 u8 syndrome[0x20]; 7388 7389 u8 reserved_at_40[0x40]; 7390 }; 7391 7392 struct mlx5_ifc_enable_hca_out_bits { 7393 u8 status[0x8]; 7394 u8 reserved_at_8[0x18]; 7395 7396 u8 syndrome[0x20]; 7397 7398 u8 reserved_at_40[0x20]; 7399 }; 7400 7401 struct mlx5_ifc_enable_hca_in_bits { 7402 u8 opcode[0x10]; 7403 u8 reserved_at_10[0x10]; 7404 7405 u8 reserved_at_20[0x10]; 7406 u8 op_mod[0x10]; 7407 7408 u8 embedded_cpu_function[0x1]; 7409 u8 reserved_at_41[0xf]; 7410 u8 function_id[0x10]; 7411 7412 u8 reserved_at_60[0x20]; 7413 }; 7414 7415 struct mlx5_ifc_drain_dct_out_bits { 7416 u8 status[0x8]; 7417 u8 reserved_at_8[0x18]; 7418 7419 u8 syndrome[0x20]; 7420 7421 u8 reserved_at_40[0x40]; 7422 }; 7423 7424 struct mlx5_ifc_drain_dct_in_bits { 7425 u8 opcode[0x10]; 7426 u8 uid[0x10]; 7427 7428 u8 reserved_at_20[0x10]; 7429 u8 op_mod[0x10]; 7430 7431 u8 reserved_at_40[0x8]; 7432 u8 dctn[0x18]; 7433 7434 u8 reserved_at_60[0x20]; 7435 }; 7436 7437 struct mlx5_ifc_disable_hca_out_bits { 7438 u8 status[0x8]; 7439 u8 reserved_at_8[0x18]; 7440 7441 u8 syndrome[0x20]; 7442 7443 u8 reserved_at_40[0x20]; 7444 }; 7445 7446 struct mlx5_ifc_disable_hca_in_bits { 7447 u8 opcode[0x10]; 7448 u8 reserved_at_10[0x10]; 7449 7450 u8 reserved_at_20[0x10]; 7451 u8 op_mod[0x10]; 7452 7453 u8 embedded_cpu_function[0x1]; 7454 u8 reserved_at_41[0xf]; 7455 u8 function_id[0x10]; 7456 7457 u8 reserved_at_60[0x20]; 7458 }; 7459 7460 struct mlx5_ifc_detach_from_mcg_out_bits { 7461 u8 status[0x8]; 7462 u8 reserved_at_8[0x18]; 7463 7464 u8 syndrome[0x20]; 7465 7466 u8 reserved_at_40[0x40]; 7467 }; 7468 7469 struct mlx5_ifc_detach_from_mcg_in_bits { 7470 u8 opcode[0x10]; 7471 u8 uid[0x10]; 7472 7473 u8 reserved_at_20[0x10]; 7474 u8 op_mod[0x10]; 7475 7476 u8 reserved_at_40[0x8]; 7477 u8 qpn[0x18]; 7478 7479 u8 reserved_at_60[0x20]; 7480 7481 u8 multicast_gid[16][0x8]; 7482 }; 7483 7484 struct mlx5_ifc_destroy_xrq_out_bits { 7485 u8 status[0x8]; 7486 u8 reserved_at_8[0x18]; 7487 7488 u8 syndrome[0x20]; 7489 7490 u8 reserved_at_40[0x40]; 7491 }; 7492 7493 struct mlx5_ifc_destroy_xrq_in_bits { 7494 u8 opcode[0x10]; 7495 u8 uid[0x10]; 7496 7497 u8 reserved_at_20[0x10]; 7498 u8 op_mod[0x10]; 7499 7500 u8 reserved_at_40[0x8]; 7501 u8 xrqn[0x18]; 7502 7503 u8 reserved_at_60[0x20]; 7504 }; 7505 7506 struct mlx5_ifc_destroy_xrc_srq_out_bits { 7507 u8 status[0x8]; 7508 u8 reserved_at_8[0x18]; 7509 7510 u8 syndrome[0x20]; 7511 7512 u8 reserved_at_40[0x40]; 7513 }; 7514 7515 struct mlx5_ifc_destroy_xrc_srq_in_bits { 7516 u8 opcode[0x10]; 7517 u8 uid[0x10]; 7518 7519 u8 reserved_at_20[0x10]; 7520 u8 op_mod[0x10]; 7521 7522 u8 reserved_at_40[0x8]; 7523 u8 xrc_srqn[0x18]; 7524 7525 u8 reserved_at_60[0x20]; 7526 }; 7527 7528 struct mlx5_ifc_destroy_tis_out_bits { 7529 u8 status[0x8]; 7530 u8 reserved_at_8[0x18]; 7531 7532 u8 syndrome[0x20]; 7533 7534 u8 reserved_at_40[0x40]; 7535 }; 7536 7537 struct mlx5_ifc_destroy_tis_in_bits { 7538 u8 opcode[0x10]; 7539 u8 uid[0x10]; 7540 7541 u8 reserved_at_20[0x10]; 7542 u8 op_mod[0x10]; 7543 7544 u8 reserved_at_40[0x8]; 7545 u8 tisn[0x18]; 7546 7547 u8 reserved_at_60[0x20]; 7548 }; 7549 7550 struct mlx5_ifc_destroy_tir_out_bits { 7551 u8 status[0x8]; 7552 u8 reserved_at_8[0x18]; 7553 7554 u8 syndrome[0x20]; 7555 7556 u8 reserved_at_40[0x40]; 7557 }; 7558 7559 struct mlx5_ifc_destroy_tir_in_bits { 7560 u8 opcode[0x10]; 7561 u8 uid[0x10]; 7562 7563 u8 reserved_at_20[0x10]; 7564 u8 op_mod[0x10]; 7565 7566 u8 reserved_at_40[0x8]; 7567 u8 tirn[0x18]; 7568 7569 u8 reserved_at_60[0x20]; 7570 }; 7571 7572 struct mlx5_ifc_destroy_srq_out_bits { 7573 u8 status[0x8]; 7574 u8 reserved_at_8[0x18]; 7575 7576 u8 syndrome[0x20]; 7577 7578 u8 reserved_at_40[0x40]; 7579 }; 7580 7581 struct mlx5_ifc_destroy_srq_in_bits { 7582 u8 opcode[0x10]; 7583 u8 uid[0x10]; 7584 7585 u8 reserved_at_20[0x10]; 7586 u8 op_mod[0x10]; 7587 7588 u8 reserved_at_40[0x8]; 7589 u8 srqn[0x18]; 7590 7591 u8 reserved_at_60[0x20]; 7592 }; 7593 7594 struct mlx5_ifc_destroy_sq_out_bits { 7595 u8 status[0x8]; 7596 u8 reserved_at_8[0x18]; 7597 7598 u8 syndrome[0x20]; 7599 7600 u8 reserved_at_40[0x40]; 7601 }; 7602 7603 struct mlx5_ifc_destroy_sq_in_bits { 7604 u8 opcode[0x10]; 7605 u8 uid[0x10]; 7606 7607 u8 reserved_at_20[0x10]; 7608 u8 op_mod[0x10]; 7609 7610 u8 reserved_at_40[0x8]; 7611 u8 sqn[0x18]; 7612 7613 u8 reserved_at_60[0x20]; 7614 }; 7615 7616 struct mlx5_ifc_destroy_scheduling_element_out_bits { 7617 u8 status[0x8]; 7618 u8 reserved_at_8[0x18]; 7619 7620 u8 syndrome[0x20]; 7621 7622 u8 reserved_at_40[0x1c0]; 7623 }; 7624 7625 struct mlx5_ifc_destroy_scheduling_element_in_bits { 7626 u8 opcode[0x10]; 7627 u8 reserved_at_10[0x10]; 7628 7629 u8 reserved_at_20[0x10]; 7630 u8 op_mod[0x10]; 7631 7632 u8 scheduling_hierarchy[0x8]; 7633 u8 reserved_at_48[0x18]; 7634 7635 u8 scheduling_element_id[0x20]; 7636 7637 u8 reserved_at_80[0x180]; 7638 }; 7639 7640 struct mlx5_ifc_destroy_rqt_out_bits { 7641 u8 status[0x8]; 7642 u8 reserved_at_8[0x18]; 7643 7644 u8 syndrome[0x20]; 7645 7646 u8 reserved_at_40[0x40]; 7647 }; 7648 7649 struct mlx5_ifc_destroy_rqt_in_bits { 7650 u8 opcode[0x10]; 7651 u8 uid[0x10]; 7652 7653 u8 reserved_at_20[0x10]; 7654 u8 op_mod[0x10]; 7655 7656 u8 reserved_at_40[0x8]; 7657 u8 rqtn[0x18]; 7658 7659 u8 reserved_at_60[0x20]; 7660 }; 7661 7662 struct mlx5_ifc_destroy_rq_out_bits { 7663 u8 status[0x8]; 7664 u8 reserved_at_8[0x18]; 7665 7666 u8 syndrome[0x20]; 7667 7668 u8 reserved_at_40[0x40]; 7669 }; 7670 7671 struct mlx5_ifc_destroy_rq_in_bits { 7672 u8 opcode[0x10]; 7673 u8 uid[0x10]; 7674 7675 u8 reserved_at_20[0x10]; 7676 u8 op_mod[0x10]; 7677 7678 u8 reserved_at_40[0x8]; 7679 u8 rqn[0x18]; 7680 7681 u8 reserved_at_60[0x20]; 7682 }; 7683 7684 struct mlx5_ifc_set_delay_drop_params_in_bits { 7685 u8 opcode[0x10]; 7686 u8 reserved_at_10[0x10]; 7687 7688 u8 reserved_at_20[0x10]; 7689 u8 op_mod[0x10]; 7690 7691 u8 reserved_at_40[0x20]; 7692 7693 u8 reserved_at_60[0x10]; 7694 u8 delay_drop_timeout[0x10]; 7695 }; 7696 7697 struct mlx5_ifc_set_delay_drop_params_out_bits { 7698 u8 status[0x8]; 7699 u8 reserved_at_8[0x18]; 7700 7701 u8 syndrome[0x20]; 7702 7703 u8 reserved_at_40[0x40]; 7704 }; 7705 7706 struct mlx5_ifc_destroy_rmp_out_bits { 7707 u8 status[0x8]; 7708 u8 reserved_at_8[0x18]; 7709 7710 u8 syndrome[0x20]; 7711 7712 u8 reserved_at_40[0x40]; 7713 }; 7714 7715 struct mlx5_ifc_destroy_rmp_in_bits { 7716 u8 opcode[0x10]; 7717 u8 uid[0x10]; 7718 7719 u8 reserved_at_20[0x10]; 7720 u8 op_mod[0x10]; 7721 7722 u8 reserved_at_40[0x8]; 7723 u8 rmpn[0x18]; 7724 7725 u8 reserved_at_60[0x20]; 7726 }; 7727 7728 struct mlx5_ifc_destroy_qp_out_bits { 7729 u8 status[0x8]; 7730 u8 reserved_at_8[0x18]; 7731 7732 u8 syndrome[0x20]; 7733 7734 u8 reserved_at_40[0x40]; 7735 }; 7736 7737 struct mlx5_ifc_destroy_qp_in_bits { 7738 u8 opcode[0x10]; 7739 u8 uid[0x10]; 7740 7741 u8 reserved_at_20[0x10]; 7742 u8 op_mod[0x10]; 7743 7744 u8 reserved_at_40[0x8]; 7745 u8 qpn[0x18]; 7746 7747 u8 reserved_at_60[0x20]; 7748 }; 7749 7750 struct mlx5_ifc_destroy_psv_out_bits { 7751 u8 status[0x8]; 7752 u8 reserved_at_8[0x18]; 7753 7754 u8 syndrome[0x20]; 7755 7756 u8 reserved_at_40[0x40]; 7757 }; 7758 7759 struct mlx5_ifc_destroy_psv_in_bits { 7760 u8 opcode[0x10]; 7761 u8 reserved_at_10[0x10]; 7762 7763 u8 reserved_at_20[0x10]; 7764 u8 op_mod[0x10]; 7765 7766 u8 reserved_at_40[0x8]; 7767 u8 psvn[0x18]; 7768 7769 u8 reserved_at_60[0x20]; 7770 }; 7771 7772 struct mlx5_ifc_destroy_mkey_out_bits { 7773 u8 status[0x8]; 7774 u8 reserved_at_8[0x18]; 7775 7776 u8 syndrome[0x20]; 7777 7778 u8 reserved_at_40[0x40]; 7779 }; 7780 7781 struct mlx5_ifc_destroy_mkey_in_bits { 7782 u8 opcode[0x10]; 7783 u8 uid[0x10]; 7784 7785 u8 reserved_at_20[0x10]; 7786 u8 op_mod[0x10]; 7787 7788 u8 reserved_at_40[0x8]; 7789 u8 mkey_index[0x18]; 7790 7791 u8 reserved_at_60[0x20]; 7792 }; 7793 7794 struct mlx5_ifc_destroy_flow_table_out_bits { 7795 u8 status[0x8]; 7796 u8 reserved_at_8[0x18]; 7797 7798 u8 syndrome[0x20]; 7799 7800 u8 reserved_at_40[0x40]; 7801 }; 7802 7803 struct mlx5_ifc_destroy_flow_table_in_bits { 7804 u8 opcode[0x10]; 7805 u8 reserved_at_10[0x10]; 7806 7807 u8 reserved_at_20[0x10]; 7808 u8 op_mod[0x10]; 7809 7810 u8 other_vport[0x1]; 7811 u8 reserved_at_41[0xf]; 7812 u8 vport_number[0x10]; 7813 7814 u8 reserved_at_60[0x20]; 7815 7816 u8 table_type[0x8]; 7817 u8 reserved_at_88[0x18]; 7818 7819 u8 reserved_at_a0[0x8]; 7820 u8 table_id[0x18]; 7821 7822 u8 reserved_at_c0[0x140]; 7823 }; 7824 7825 struct mlx5_ifc_destroy_flow_group_out_bits { 7826 u8 status[0x8]; 7827 u8 reserved_at_8[0x18]; 7828 7829 u8 syndrome[0x20]; 7830 7831 u8 reserved_at_40[0x40]; 7832 }; 7833 7834 struct mlx5_ifc_destroy_flow_group_in_bits { 7835 u8 opcode[0x10]; 7836 u8 reserved_at_10[0x10]; 7837 7838 u8 reserved_at_20[0x10]; 7839 u8 op_mod[0x10]; 7840 7841 u8 other_vport[0x1]; 7842 u8 reserved_at_41[0xf]; 7843 u8 vport_number[0x10]; 7844 7845 u8 reserved_at_60[0x20]; 7846 7847 u8 table_type[0x8]; 7848 u8 reserved_at_88[0x18]; 7849 7850 u8 reserved_at_a0[0x8]; 7851 u8 table_id[0x18]; 7852 7853 u8 group_id[0x20]; 7854 7855 u8 reserved_at_e0[0x120]; 7856 }; 7857 7858 struct mlx5_ifc_destroy_eq_out_bits { 7859 u8 status[0x8]; 7860 u8 reserved_at_8[0x18]; 7861 7862 u8 syndrome[0x20]; 7863 7864 u8 reserved_at_40[0x40]; 7865 }; 7866 7867 struct mlx5_ifc_destroy_eq_in_bits { 7868 u8 opcode[0x10]; 7869 u8 reserved_at_10[0x10]; 7870 7871 u8 reserved_at_20[0x10]; 7872 u8 op_mod[0x10]; 7873 7874 u8 reserved_at_40[0x18]; 7875 u8 eq_number[0x8]; 7876 7877 u8 reserved_at_60[0x20]; 7878 }; 7879 7880 struct mlx5_ifc_destroy_dct_out_bits { 7881 u8 status[0x8]; 7882 u8 reserved_at_8[0x18]; 7883 7884 u8 syndrome[0x20]; 7885 7886 u8 reserved_at_40[0x40]; 7887 }; 7888 7889 struct mlx5_ifc_destroy_dct_in_bits { 7890 u8 opcode[0x10]; 7891 u8 uid[0x10]; 7892 7893 u8 reserved_at_20[0x10]; 7894 u8 op_mod[0x10]; 7895 7896 u8 reserved_at_40[0x8]; 7897 u8 dctn[0x18]; 7898 7899 u8 reserved_at_60[0x20]; 7900 }; 7901 7902 struct mlx5_ifc_destroy_cq_out_bits { 7903 u8 status[0x8]; 7904 u8 reserved_at_8[0x18]; 7905 7906 u8 syndrome[0x20]; 7907 7908 u8 reserved_at_40[0x40]; 7909 }; 7910 7911 struct mlx5_ifc_destroy_cq_in_bits { 7912 u8 opcode[0x10]; 7913 u8 uid[0x10]; 7914 7915 u8 reserved_at_20[0x10]; 7916 u8 op_mod[0x10]; 7917 7918 u8 reserved_at_40[0x8]; 7919 u8 cqn[0x18]; 7920 7921 u8 reserved_at_60[0x20]; 7922 }; 7923 7924 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits { 7925 u8 status[0x8]; 7926 u8 reserved_at_8[0x18]; 7927 7928 u8 syndrome[0x20]; 7929 7930 u8 reserved_at_40[0x40]; 7931 }; 7932 7933 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits { 7934 u8 opcode[0x10]; 7935 u8 reserved_at_10[0x10]; 7936 7937 u8 reserved_at_20[0x10]; 7938 u8 op_mod[0x10]; 7939 7940 u8 reserved_at_40[0x20]; 7941 7942 u8 reserved_at_60[0x10]; 7943 u8 vxlan_udp_port[0x10]; 7944 }; 7945 7946 struct mlx5_ifc_delete_l2_table_entry_out_bits { 7947 u8 status[0x8]; 7948 u8 reserved_at_8[0x18]; 7949 7950 u8 syndrome[0x20]; 7951 7952 u8 reserved_at_40[0x40]; 7953 }; 7954 7955 struct mlx5_ifc_delete_l2_table_entry_in_bits { 7956 u8 opcode[0x10]; 7957 u8 reserved_at_10[0x10]; 7958 7959 u8 reserved_at_20[0x10]; 7960 u8 op_mod[0x10]; 7961 7962 u8 reserved_at_40[0x60]; 7963 7964 u8 reserved_at_a0[0x8]; 7965 u8 table_index[0x18]; 7966 7967 u8 reserved_at_c0[0x140]; 7968 }; 7969 7970 struct mlx5_ifc_delete_fte_out_bits { 7971 u8 status[0x8]; 7972 u8 reserved_at_8[0x18]; 7973 7974 u8 syndrome[0x20]; 7975 7976 u8 reserved_at_40[0x40]; 7977 }; 7978 7979 struct mlx5_ifc_delete_fte_in_bits { 7980 u8 opcode[0x10]; 7981 u8 reserved_at_10[0x10]; 7982 7983 u8 reserved_at_20[0x10]; 7984 u8 op_mod[0x10]; 7985 7986 u8 other_vport[0x1]; 7987 u8 reserved_at_41[0xf]; 7988 u8 vport_number[0x10]; 7989 7990 u8 reserved_at_60[0x20]; 7991 7992 u8 table_type[0x8]; 7993 u8 reserved_at_88[0x18]; 7994 7995 u8 reserved_at_a0[0x8]; 7996 u8 table_id[0x18]; 7997 7998 u8 reserved_at_c0[0x40]; 7999 8000 u8 flow_index[0x20]; 8001 8002 u8 reserved_at_120[0xe0]; 8003 }; 8004 8005 struct mlx5_ifc_dealloc_xrcd_out_bits { 8006 u8 status[0x8]; 8007 u8 reserved_at_8[0x18]; 8008 8009 u8 syndrome[0x20]; 8010 8011 u8 reserved_at_40[0x40]; 8012 }; 8013 8014 struct mlx5_ifc_dealloc_xrcd_in_bits { 8015 u8 opcode[0x10]; 8016 u8 uid[0x10]; 8017 8018 u8 reserved_at_20[0x10]; 8019 u8 op_mod[0x10]; 8020 8021 u8 reserved_at_40[0x8]; 8022 u8 xrcd[0x18]; 8023 8024 u8 reserved_at_60[0x20]; 8025 }; 8026 8027 struct mlx5_ifc_dealloc_uar_out_bits { 8028 u8 status[0x8]; 8029 u8 reserved_at_8[0x18]; 8030 8031 u8 syndrome[0x20]; 8032 8033 u8 reserved_at_40[0x40]; 8034 }; 8035 8036 struct mlx5_ifc_dealloc_uar_in_bits { 8037 u8 opcode[0x10]; 8038 u8 uid[0x10]; 8039 8040 u8 reserved_at_20[0x10]; 8041 u8 op_mod[0x10]; 8042 8043 u8 reserved_at_40[0x8]; 8044 u8 uar[0x18]; 8045 8046 u8 reserved_at_60[0x20]; 8047 }; 8048 8049 struct mlx5_ifc_dealloc_transport_domain_out_bits { 8050 u8 status[0x8]; 8051 u8 reserved_at_8[0x18]; 8052 8053 u8 syndrome[0x20]; 8054 8055 u8 reserved_at_40[0x40]; 8056 }; 8057 8058 struct mlx5_ifc_dealloc_transport_domain_in_bits { 8059 u8 opcode[0x10]; 8060 u8 uid[0x10]; 8061 8062 u8 reserved_at_20[0x10]; 8063 u8 op_mod[0x10]; 8064 8065 u8 reserved_at_40[0x8]; 8066 u8 transport_domain[0x18]; 8067 8068 u8 reserved_at_60[0x20]; 8069 }; 8070 8071 struct mlx5_ifc_dealloc_q_counter_out_bits { 8072 u8 status[0x8]; 8073 u8 reserved_at_8[0x18]; 8074 8075 u8 syndrome[0x20]; 8076 8077 u8 reserved_at_40[0x40]; 8078 }; 8079 8080 struct mlx5_ifc_dealloc_q_counter_in_bits { 8081 u8 opcode[0x10]; 8082 u8 reserved_at_10[0x10]; 8083 8084 u8 reserved_at_20[0x10]; 8085 u8 op_mod[0x10]; 8086 8087 u8 reserved_at_40[0x18]; 8088 u8 counter_set_id[0x8]; 8089 8090 u8 reserved_at_60[0x20]; 8091 }; 8092 8093 struct mlx5_ifc_dealloc_pd_out_bits { 8094 u8 status[0x8]; 8095 u8 reserved_at_8[0x18]; 8096 8097 u8 syndrome[0x20]; 8098 8099 u8 reserved_at_40[0x40]; 8100 }; 8101 8102 struct mlx5_ifc_dealloc_pd_in_bits { 8103 u8 opcode[0x10]; 8104 u8 uid[0x10]; 8105 8106 u8 reserved_at_20[0x10]; 8107 u8 op_mod[0x10]; 8108 8109 u8 reserved_at_40[0x8]; 8110 u8 pd[0x18]; 8111 8112 u8 reserved_at_60[0x20]; 8113 }; 8114 8115 struct mlx5_ifc_dealloc_flow_counter_out_bits { 8116 u8 status[0x8]; 8117 u8 reserved_at_8[0x18]; 8118 8119 u8 syndrome[0x20]; 8120 8121 u8 reserved_at_40[0x40]; 8122 }; 8123 8124 struct mlx5_ifc_dealloc_flow_counter_in_bits { 8125 u8 opcode[0x10]; 8126 u8 reserved_at_10[0x10]; 8127 8128 u8 reserved_at_20[0x10]; 8129 u8 op_mod[0x10]; 8130 8131 u8 flow_counter_id[0x20]; 8132 8133 u8 reserved_at_60[0x20]; 8134 }; 8135 8136 struct mlx5_ifc_create_xrq_out_bits { 8137 u8 status[0x8]; 8138 u8 reserved_at_8[0x18]; 8139 8140 u8 syndrome[0x20]; 8141 8142 u8 reserved_at_40[0x8]; 8143 u8 xrqn[0x18]; 8144 8145 u8 reserved_at_60[0x20]; 8146 }; 8147 8148 struct mlx5_ifc_create_xrq_in_bits { 8149 u8 opcode[0x10]; 8150 u8 uid[0x10]; 8151 8152 u8 reserved_at_20[0x10]; 8153 u8 op_mod[0x10]; 8154 8155 u8 reserved_at_40[0x40]; 8156 8157 struct mlx5_ifc_xrqc_bits xrq_context; 8158 }; 8159 8160 struct mlx5_ifc_create_xrc_srq_out_bits { 8161 u8 status[0x8]; 8162 u8 reserved_at_8[0x18]; 8163 8164 u8 syndrome[0x20]; 8165 8166 u8 reserved_at_40[0x8]; 8167 u8 xrc_srqn[0x18]; 8168 8169 u8 reserved_at_60[0x20]; 8170 }; 8171 8172 struct mlx5_ifc_create_xrc_srq_in_bits { 8173 u8 opcode[0x10]; 8174 u8 uid[0x10]; 8175 8176 u8 reserved_at_20[0x10]; 8177 u8 op_mod[0x10]; 8178 8179 u8 reserved_at_40[0x40]; 8180 8181 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 8182 8183 u8 reserved_at_280[0x60]; 8184 8185 u8 xrc_srq_umem_valid[0x1]; 8186 u8 reserved_at_2e1[0x1f]; 8187 8188 u8 reserved_at_300[0x580]; 8189 8190 u8 pas[][0x40]; 8191 }; 8192 8193 struct mlx5_ifc_create_tis_out_bits { 8194 u8 status[0x8]; 8195 u8 reserved_at_8[0x18]; 8196 8197 u8 syndrome[0x20]; 8198 8199 u8 reserved_at_40[0x8]; 8200 u8 tisn[0x18]; 8201 8202 u8 reserved_at_60[0x20]; 8203 }; 8204 8205 struct mlx5_ifc_create_tis_in_bits { 8206 u8 opcode[0x10]; 8207 u8 uid[0x10]; 8208 8209 u8 reserved_at_20[0x10]; 8210 u8 op_mod[0x10]; 8211 8212 u8 reserved_at_40[0xc0]; 8213 8214 struct mlx5_ifc_tisc_bits ctx; 8215 }; 8216 8217 struct mlx5_ifc_create_tir_out_bits { 8218 u8 status[0x8]; 8219 u8 icm_address_63_40[0x18]; 8220 8221 u8 syndrome[0x20]; 8222 8223 u8 icm_address_39_32[0x8]; 8224 u8 tirn[0x18]; 8225 8226 u8 icm_address_31_0[0x20]; 8227 }; 8228 8229 struct mlx5_ifc_create_tir_in_bits { 8230 u8 opcode[0x10]; 8231 u8 uid[0x10]; 8232 8233 u8 reserved_at_20[0x10]; 8234 u8 op_mod[0x10]; 8235 8236 u8 reserved_at_40[0xc0]; 8237 8238 struct mlx5_ifc_tirc_bits ctx; 8239 }; 8240 8241 struct mlx5_ifc_create_srq_out_bits { 8242 u8 status[0x8]; 8243 u8 reserved_at_8[0x18]; 8244 8245 u8 syndrome[0x20]; 8246 8247 u8 reserved_at_40[0x8]; 8248 u8 srqn[0x18]; 8249 8250 u8 reserved_at_60[0x20]; 8251 }; 8252 8253 struct mlx5_ifc_create_srq_in_bits { 8254 u8 opcode[0x10]; 8255 u8 uid[0x10]; 8256 8257 u8 reserved_at_20[0x10]; 8258 u8 op_mod[0x10]; 8259 8260 u8 reserved_at_40[0x40]; 8261 8262 struct mlx5_ifc_srqc_bits srq_context_entry; 8263 8264 u8 reserved_at_280[0x600]; 8265 8266 u8 pas[][0x40]; 8267 }; 8268 8269 struct mlx5_ifc_create_sq_out_bits { 8270 u8 status[0x8]; 8271 u8 reserved_at_8[0x18]; 8272 8273 u8 syndrome[0x20]; 8274 8275 u8 reserved_at_40[0x8]; 8276 u8 sqn[0x18]; 8277 8278 u8 reserved_at_60[0x20]; 8279 }; 8280 8281 struct mlx5_ifc_create_sq_in_bits { 8282 u8 opcode[0x10]; 8283 u8 uid[0x10]; 8284 8285 u8 reserved_at_20[0x10]; 8286 u8 op_mod[0x10]; 8287 8288 u8 reserved_at_40[0xc0]; 8289 8290 struct mlx5_ifc_sqc_bits ctx; 8291 }; 8292 8293 struct mlx5_ifc_create_scheduling_element_out_bits { 8294 u8 status[0x8]; 8295 u8 reserved_at_8[0x18]; 8296 8297 u8 syndrome[0x20]; 8298 8299 u8 reserved_at_40[0x40]; 8300 8301 u8 scheduling_element_id[0x20]; 8302 8303 u8 reserved_at_a0[0x160]; 8304 }; 8305 8306 struct mlx5_ifc_create_scheduling_element_in_bits { 8307 u8 opcode[0x10]; 8308 u8 reserved_at_10[0x10]; 8309 8310 u8 reserved_at_20[0x10]; 8311 u8 op_mod[0x10]; 8312 8313 u8 scheduling_hierarchy[0x8]; 8314 u8 reserved_at_48[0x18]; 8315 8316 u8 reserved_at_60[0xa0]; 8317 8318 struct mlx5_ifc_scheduling_context_bits scheduling_context; 8319 8320 u8 reserved_at_300[0x100]; 8321 }; 8322 8323 struct mlx5_ifc_create_rqt_out_bits { 8324 u8 status[0x8]; 8325 u8 reserved_at_8[0x18]; 8326 8327 u8 syndrome[0x20]; 8328 8329 u8 reserved_at_40[0x8]; 8330 u8 rqtn[0x18]; 8331 8332 u8 reserved_at_60[0x20]; 8333 }; 8334 8335 struct mlx5_ifc_create_rqt_in_bits { 8336 u8 opcode[0x10]; 8337 u8 uid[0x10]; 8338 8339 u8 reserved_at_20[0x10]; 8340 u8 op_mod[0x10]; 8341 8342 u8 reserved_at_40[0xc0]; 8343 8344 struct mlx5_ifc_rqtc_bits rqt_context; 8345 }; 8346 8347 struct mlx5_ifc_create_rq_out_bits { 8348 u8 status[0x8]; 8349 u8 reserved_at_8[0x18]; 8350 8351 u8 syndrome[0x20]; 8352 8353 u8 reserved_at_40[0x8]; 8354 u8 rqn[0x18]; 8355 8356 u8 reserved_at_60[0x20]; 8357 }; 8358 8359 struct mlx5_ifc_create_rq_in_bits { 8360 u8 opcode[0x10]; 8361 u8 uid[0x10]; 8362 8363 u8 reserved_at_20[0x10]; 8364 u8 op_mod[0x10]; 8365 8366 u8 reserved_at_40[0xc0]; 8367 8368 struct mlx5_ifc_rqc_bits ctx; 8369 }; 8370 8371 struct mlx5_ifc_create_rmp_out_bits { 8372 u8 status[0x8]; 8373 u8 reserved_at_8[0x18]; 8374 8375 u8 syndrome[0x20]; 8376 8377 u8 reserved_at_40[0x8]; 8378 u8 rmpn[0x18]; 8379 8380 u8 reserved_at_60[0x20]; 8381 }; 8382 8383 struct mlx5_ifc_create_rmp_in_bits { 8384 u8 opcode[0x10]; 8385 u8 uid[0x10]; 8386 8387 u8 reserved_at_20[0x10]; 8388 u8 op_mod[0x10]; 8389 8390 u8 reserved_at_40[0xc0]; 8391 8392 struct mlx5_ifc_rmpc_bits ctx; 8393 }; 8394 8395 struct mlx5_ifc_create_qp_out_bits { 8396 u8 status[0x8]; 8397 u8 reserved_at_8[0x18]; 8398 8399 u8 syndrome[0x20]; 8400 8401 u8 reserved_at_40[0x8]; 8402 u8 qpn[0x18]; 8403 8404 u8 ece[0x20]; 8405 }; 8406 8407 struct mlx5_ifc_create_qp_in_bits { 8408 u8 opcode[0x10]; 8409 u8 uid[0x10]; 8410 8411 u8 reserved_at_20[0x10]; 8412 u8 op_mod[0x10]; 8413 8414 u8 reserved_at_40[0x8]; 8415 u8 input_qpn[0x18]; 8416 8417 u8 reserved_at_60[0x20]; 8418 u8 opt_param_mask[0x20]; 8419 8420 u8 ece[0x20]; 8421 8422 struct mlx5_ifc_qpc_bits qpc; 8423 8424 u8 reserved_at_800[0x60]; 8425 8426 u8 wq_umem_valid[0x1]; 8427 u8 reserved_at_861[0x1f]; 8428 8429 u8 pas[][0x40]; 8430 }; 8431 8432 struct mlx5_ifc_create_psv_out_bits { 8433 u8 status[0x8]; 8434 u8 reserved_at_8[0x18]; 8435 8436 u8 syndrome[0x20]; 8437 8438 u8 reserved_at_40[0x40]; 8439 8440 u8 reserved_at_80[0x8]; 8441 u8 psv0_index[0x18]; 8442 8443 u8 reserved_at_a0[0x8]; 8444 u8 psv1_index[0x18]; 8445 8446 u8 reserved_at_c0[0x8]; 8447 u8 psv2_index[0x18]; 8448 8449 u8 reserved_at_e0[0x8]; 8450 u8 psv3_index[0x18]; 8451 }; 8452 8453 struct mlx5_ifc_create_psv_in_bits { 8454 u8 opcode[0x10]; 8455 u8 reserved_at_10[0x10]; 8456 8457 u8 reserved_at_20[0x10]; 8458 u8 op_mod[0x10]; 8459 8460 u8 num_psv[0x4]; 8461 u8 reserved_at_44[0x4]; 8462 u8 pd[0x18]; 8463 8464 u8 reserved_at_60[0x20]; 8465 }; 8466 8467 struct mlx5_ifc_create_mkey_out_bits { 8468 u8 status[0x8]; 8469 u8 reserved_at_8[0x18]; 8470 8471 u8 syndrome[0x20]; 8472 8473 u8 reserved_at_40[0x8]; 8474 u8 mkey_index[0x18]; 8475 8476 u8 reserved_at_60[0x20]; 8477 }; 8478 8479 struct mlx5_ifc_create_mkey_in_bits { 8480 u8 opcode[0x10]; 8481 u8 uid[0x10]; 8482 8483 u8 reserved_at_20[0x10]; 8484 u8 op_mod[0x10]; 8485 8486 u8 reserved_at_40[0x20]; 8487 8488 u8 pg_access[0x1]; 8489 u8 mkey_umem_valid[0x1]; 8490 u8 reserved_at_62[0x1e]; 8491 8492 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 8493 8494 u8 reserved_at_280[0x80]; 8495 8496 u8 translations_octword_actual_size[0x20]; 8497 8498 u8 reserved_at_320[0x560]; 8499 8500 u8 klm_pas_mtt[][0x20]; 8501 }; 8502 8503 enum { 8504 MLX5_FLOW_TABLE_TYPE_NIC_RX = 0x0, 8505 MLX5_FLOW_TABLE_TYPE_NIC_TX = 0x1, 8506 MLX5_FLOW_TABLE_TYPE_ESW_EGRESS_ACL = 0x2, 8507 MLX5_FLOW_TABLE_TYPE_ESW_INGRESS_ACL = 0x3, 8508 MLX5_FLOW_TABLE_TYPE_FDB = 0X4, 8509 MLX5_FLOW_TABLE_TYPE_SNIFFER_RX = 0X5, 8510 MLX5_FLOW_TABLE_TYPE_SNIFFER_TX = 0X6, 8511 }; 8512 8513 struct mlx5_ifc_create_flow_table_out_bits { 8514 u8 status[0x8]; 8515 u8 icm_address_63_40[0x18]; 8516 8517 u8 syndrome[0x20]; 8518 8519 u8 icm_address_39_32[0x8]; 8520 u8 table_id[0x18]; 8521 8522 u8 icm_address_31_0[0x20]; 8523 }; 8524 8525 struct mlx5_ifc_create_flow_table_in_bits { 8526 u8 opcode[0x10]; 8527 u8 reserved_at_10[0x10]; 8528 8529 u8 reserved_at_20[0x10]; 8530 u8 op_mod[0x10]; 8531 8532 u8 other_vport[0x1]; 8533 u8 reserved_at_41[0xf]; 8534 u8 vport_number[0x10]; 8535 8536 u8 reserved_at_60[0x20]; 8537 8538 u8 table_type[0x8]; 8539 u8 reserved_at_88[0x18]; 8540 8541 u8 reserved_at_a0[0x20]; 8542 8543 struct mlx5_ifc_flow_table_context_bits flow_table_context; 8544 }; 8545 8546 struct mlx5_ifc_create_flow_group_out_bits { 8547 u8 status[0x8]; 8548 u8 reserved_at_8[0x18]; 8549 8550 u8 syndrome[0x20]; 8551 8552 u8 reserved_at_40[0x8]; 8553 u8 group_id[0x18]; 8554 8555 u8 reserved_at_60[0x20]; 8556 }; 8557 8558 enum { 8559 MLX5_CREATE_FLOW_GROUP_IN_GROUP_TYPE_TCAM_SUBTABLE = 0x0, 8560 MLX5_CREATE_FLOW_GROUP_IN_GROUP_TYPE_HASH_SPLIT = 0x1, 8561 }; 8562 8563 enum { 8564 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 8565 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 8566 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 8567 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3, 8568 }; 8569 8570 struct mlx5_ifc_create_flow_group_in_bits { 8571 u8 opcode[0x10]; 8572 u8 reserved_at_10[0x10]; 8573 8574 u8 reserved_at_20[0x10]; 8575 u8 op_mod[0x10]; 8576 8577 u8 other_vport[0x1]; 8578 u8 reserved_at_41[0xf]; 8579 u8 vport_number[0x10]; 8580 8581 u8 reserved_at_60[0x20]; 8582 8583 u8 table_type[0x8]; 8584 u8 reserved_at_88[0x4]; 8585 u8 group_type[0x4]; 8586 u8 reserved_at_90[0x10]; 8587 8588 u8 reserved_at_a0[0x8]; 8589 u8 table_id[0x18]; 8590 8591 u8 source_eswitch_owner_vhca_id_valid[0x1]; 8592 8593 u8 reserved_at_c1[0x1f]; 8594 8595 u8 start_flow_index[0x20]; 8596 8597 u8 reserved_at_100[0x20]; 8598 8599 u8 end_flow_index[0x20]; 8600 8601 u8 reserved_at_140[0x10]; 8602 u8 match_definer_id[0x10]; 8603 8604 u8 reserved_at_160[0x80]; 8605 8606 u8 reserved_at_1e0[0x18]; 8607 u8 match_criteria_enable[0x8]; 8608 8609 struct mlx5_ifc_fte_match_param_bits match_criteria; 8610 8611 u8 reserved_at_1200[0xe00]; 8612 }; 8613 8614 struct mlx5_ifc_create_eq_out_bits { 8615 u8 status[0x8]; 8616 u8 reserved_at_8[0x18]; 8617 8618 u8 syndrome[0x20]; 8619 8620 u8 reserved_at_40[0x18]; 8621 u8 eq_number[0x8]; 8622 8623 u8 reserved_at_60[0x20]; 8624 }; 8625 8626 struct mlx5_ifc_create_eq_in_bits { 8627 u8 opcode[0x10]; 8628 u8 uid[0x10]; 8629 8630 u8 reserved_at_20[0x10]; 8631 u8 op_mod[0x10]; 8632 8633 u8 reserved_at_40[0x40]; 8634 8635 struct mlx5_ifc_eqc_bits eq_context_entry; 8636 8637 u8 reserved_at_280[0x40]; 8638 8639 u8 event_bitmask[4][0x40]; 8640 8641 u8 reserved_at_3c0[0x4c0]; 8642 8643 u8 pas[][0x40]; 8644 }; 8645 8646 struct mlx5_ifc_create_dct_out_bits { 8647 u8 status[0x8]; 8648 u8 reserved_at_8[0x18]; 8649 8650 u8 syndrome[0x20]; 8651 8652 u8 reserved_at_40[0x8]; 8653 u8 dctn[0x18]; 8654 8655 u8 ece[0x20]; 8656 }; 8657 8658 struct mlx5_ifc_create_dct_in_bits { 8659 u8 opcode[0x10]; 8660 u8 uid[0x10]; 8661 8662 u8 reserved_at_20[0x10]; 8663 u8 op_mod[0x10]; 8664 8665 u8 reserved_at_40[0x40]; 8666 8667 struct mlx5_ifc_dctc_bits dct_context_entry; 8668 8669 u8 reserved_at_280[0x180]; 8670 }; 8671 8672 struct mlx5_ifc_create_cq_out_bits { 8673 u8 status[0x8]; 8674 u8 reserved_at_8[0x18]; 8675 8676 u8 syndrome[0x20]; 8677 8678 u8 reserved_at_40[0x8]; 8679 u8 cqn[0x18]; 8680 8681 u8 reserved_at_60[0x20]; 8682 }; 8683 8684 struct mlx5_ifc_create_cq_in_bits { 8685 u8 opcode[0x10]; 8686 u8 uid[0x10]; 8687 8688 u8 reserved_at_20[0x10]; 8689 u8 op_mod[0x10]; 8690 8691 u8 reserved_at_40[0x40]; 8692 8693 struct mlx5_ifc_cqc_bits cq_context; 8694 8695 u8 reserved_at_280[0x60]; 8696 8697 u8 cq_umem_valid[0x1]; 8698 u8 reserved_at_2e1[0x59f]; 8699 8700 u8 pas[][0x40]; 8701 }; 8702 8703 struct mlx5_ifc_config_int_moderation_out_bits { 8704 u8 status[0x8]; 8705 u8 reserved_at_8[0x18]; 8706 8707 u8 syndrome[0x20]; 8708 8709 u8 reserved_at_40[0x4]; 8710 u8 min_delay[0xc]; 8711 u8 int_vector[0x10]; 8712 8713 u8 reserved_at_60[0x20]; 8714 }; 8715 8716 enum { 8717 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0, 8718 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1, 8719 }; 8720 8721 struct mlx5_ifc_config_int_moderation_in_bits { 8722 u8 opcode[0x10]; 8723 u8 reserved_at_10[0x10]; 8724 8725 u8 reserved_at_20[0x10]; 8726 u8 op_mod[0x10]; 8727 8728 u8 reserved_at_40[0x4]; 8729 u8 min_delay[0xc]; 8730 u8 int_vector[0x10]; 8731 8732 u8 reserved_at_60[0x20]; 8733 }; 8734 8735 struct mlx5_ifc_attach_to_mcg_out_bits { 8736 u8 status[0x8]; 8737 u8 reserved_at_8[0x18]; 8738 8739 u8 syndrome[0x20]; 8740 8741 u8 reserved_at_40[0x40]; 8742 }; 8743 8744 struct mlx5_ifc_attach_to_mcg_in_bits { 8745 u8 opcode[0x10]; 8746 u8 uid[0x10]; 8747 8748 u8 reserved_at_20[0x10]; 8749 u8 op_mod[0x10]; 8750 8751 u8 reserved_at_40[0x8]; 8752 u8 qpn[0x18]; 8753 8754 u8 reserved_at_60[0x20]; 8755 8756 u8 multicast_gid[16][0x8]; 8757 }; 8758 8759 struct mlx5_ifc_arm_xrq_out_bits { 8760 u8 status[0x8]; 8761 u8 reserved_at_8[0x18]; 8762 8763 u8 syndrome[0x20]; 8764 8765 u8 reserved_at_40[0x40]; 8766 }; 8767 8768 struct mlx5_ifc_arm_xrq_in_bits { 8769 u8 opcode[0x10]; 8770 u8 reserved_at_10[0x10]; 8771 8772 u8 reserved_at_20[0x10]; 8773 u8 op_mod[0x10]; 8774 8775 u8 reserved_at_40[0x8]; 8776 u8 xrqn[0x18]; 8777 8778 u8 reserved_at_60[0x10]; 8779 u8 lwm[0x10]; 8780 }; 8781 8782 struct mlx5_ifc_arm_xrc_srq_out_bits { 8783 u8 status[0x8]; 8784 u8 reserved_at_8[0x18]; 8785 8786 u8 syndrome[0x20]; 8787 8788 u8 reserved_at_40[0x40]; 8789 }; 8790 8791 enum { 8792 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1, 8793 }; 8794 8795 struct mlx5_ifc_arm_xrc_srq_in_bits { 8796 u8 opcode[0x10]; 8797 u8 uid[0x10]; 8798 8799 u8 reserved_at_20[0x10]; 8800 u8 op_mod[0x10]; 8801 8802 u8 reserved_at_40[0x8]; 8803 u8 xrc_srqn[0x18]; 8804 8805 u8 reserved_at_60[0x10]; 8806 u8 lwm[0x10]; 8807 }; 8808 8809 struct mlx5_ifc_arm_rq_out_bits { 8810 u8 status[0x8]; 8811 u8 reserved_at_8[0x18]; 8812 8813 u8 syndrome[0x20]; 8814 8815 u8 reserved_at_40[0x40]; 8816 }; 8817 8818 enum { 8819 MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1, 8820 MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2, 8821 }; 8822 8823 struct mlx5_ifc_arm_rq_in_bits { 8824 u8 opcode[0x10]; 8825 u8 uid[0x10]; 8826 8827 u8 reserved_at_20[0x10]; 8828 u8 op_mod[0x10]; 8829 8830 u8 reserved_at_40[0x8]; 8831 u8 srq_number[0x18]; 8832 8833 u8 reserved_at_60[0x10]; 8834 u8 lwm[0x10]; 8835 }; 8836 8837 struct mlx5_ifc_arm_dct_out_bits { 8838 u8 status[0x8]; 8839 u8 reserved_at_8[0x18]; 8840 8841 u8 syndrome[0x20]; 8842 8843 u8 reserved_at_40[0x40]; 8844 }; 8845 8846 struct mlx5_ifc_arm_dct_in_bits { 8847 u8 opcode[0x10]; 8848 u8 reserved_at_10[0x10]; 8849 8850 u8 reserved_at_20[0x10]; 8851 u8 op_mod[0x10]; 8852 8853 u8 reserved_at_40[0x8]; 8854 u8 dct_number[0x18]; 8855 8856 u8 reserved_at_60[0x20]; 8857 }; 8858 8859 struct mlx5_ifc_alloc_xrcd_out_bits { 8860 u8 status[0x8]; 8861 u8 reserved_at_8[0x18]; 8862 8863 u8 syndrome[0x20]; 8864 8865 u8 reserved_at_40[0x8]; 8866 u8 xrcd[0x18]; 8867 8868 u8 reserved_at_60[0x20]; 8869 }; 8870 8871 struct mlx5_ifc_alloc_xrcd_in_bits { 8872 u8 opcode[0x10]; 8873 u8 uid[0x10]; 8874 8875 u8 reserved_at_20[0x10]; 8876 u8 op_mod[0x10]; 8877 8878 u8 reserved_at_40[0x40]; 8879 }; 8880 8881 struct mlx5_ifc_alloc_uar_out_bits { 8882 u8 status[0x8]; 8883 u8 reserved_at_8[0x18]; 8884 8885 u8 syndrome[0x20]; 8886 8887 u8 reserved_at_40[0x8]; 8888 u8 uar[0x18]; 8889 8890 u8 reserved_at_60[0x20]; 8891 }; 8892 8893 struct mlx5_ifc_alloc_uar_in_bits { 8894 u8 opcode[0x10]; 8895 u8 uid[0x10]; 8896 8897 u8 reserved_at_20[0x10]; 8898 u8 op_mod[0x10]; 8899 8900 u8 reserved_at_40[0x40]; 8901 }; 8902 8903 struct mlx5_ifc_alloc_transport_domain_out_bits { 8904 u8 status[0x8]; 8905 u8 reserved_at_8[0x18]; 8906 8907 u8 syndrome[0x20]; 8908 8909 u8 reserved_at_40[0x8]; 8910 u8 transport_domain[0x18]; 8911 8912 u8 reserved_at_60[0x20]; 8913 }; 8914 8915 struct mlx5_ifc_alloc_transport_domain_in_bits { 8916 u8 opcode[0x10]; 8917 u8 uid[0x10]; 8918 8919 u8 reserved_at_20[0x10]; 8920 u8 op_mod[0x10]; 8921 8922 u8 reserved_at_40[0x40]; 8923 }; 8924 8925 struct mlx5_ifc_alloc_q_counter_out_bits { 8926 u8 status[0x8]; 8927 u8 reserved_at_8[0x18]; 8928 8929 u8 syndrome[0x20]; 8930 8931 u8 reserved_at_40[0x18]; 8932 u8 counter_set_id[0x8]; 8933 8934 u8 reserved_at_60[0x20]; 8935 }; 8936 8937 struct mlx5_ifc_alloc_q_counter_in_bits { 8938 u8 opcode[0x10]; 8939 u8 uid[0x10]; 8940 8941 u8 reserved_at_20[0x10]; 8942 u8 op_mod[0x10]; 8943 8944 u8 reserved_at_40[0x40]; 8945 }; 8946 8947 struct mlx5_ifc_alloc_pd_out_bits { 8948 u8 status[0x8]; 8949 u8 reserved_at_8[0x18]; 8950 8951 u8 syndrome[0x20]; 8952 8953 u8 reserved_at_40[0x8]; 8954 u8 pd[0x18]; 8955 8956 u8 reserved_at_60[0x20]; 8957 }; 8958 8959 struct mlx5_ifc_alloc_pd_in_bits { 8960 u8 opcode[0x10]; 8961 u8 uid[0x10]; 8962 8963 u8 reserved_at_20[0x10]; 8964 u8 op_mod[0x10]; 8965 8966 u8 reserved_at_40[0x40]; 8967 }; 8968 8969 struct mlx5_ifc_alloc_flow_counter_out_bits { 8970 u8 status[0x8]; 8971 u8 reserved_at_8[0x18]; 8972 8973 u8 syndrome[0x20]; 8974 8975 u8 flow_counter_id[0x20]; 8976 8977 u8 reserved_at_60[0x20]; 8978 }; 8979 8980 struct mlx5_ifc_alloc_flow_counter_in_bits { 8981 u8 opcode[0x10]; 8982 u8 reserved_at_10[0x10]; 8983 8984 u8 reserved_at_20[0x10]; 8985 u8 op_mod[0x10]; 8986 8987 u8 reserved_at_40[0x38]; 8988 u8 flow_counter_bulk[0x8]; 8989 }; 8990 8991 struct mlx5_ifc_add_vxlan_udp_dport_out_bits { 8992 u8 status[0x8]; 8993 u8 reserved_at_8[0x18]; 8994 8995 u8 syndrome[0x20]; 8996 8997 u8 reserved_at_40[0x40]; 8998 }; 8999 9000 struct mlx5_ifc_add_vxlan_udp_dport_in_bits { 9001 u8 opcode[0x10]; 9002 u8 reserved_at_10[0x10]; 9003 9004 u8 reserved_at_20[0x10]; 9005 u8 op_mod[0x10]; 9006 9007 u8 reserved_at_40[0x20]; 9008 9009 u8 reserved_at_60[0x10]; 9010 u8 vxlan_udp_port[0x10]; 9011 }; 9012 9013 struct mlx5_ifc_set_pp_rate_limit_out_bits { 9014 u8 status[0x8]; 9015 u8 reserved_at_8[0x18]; 9016 9017 u8 syndrome[0x20]; 9018 9019 u8 reserved_at_40[0x40]; 9020 }; 9021 9022 struct mlx5_ifc_set_pp_rate_limit_context_bits { 9023 u8 rate_limit[0x20]; 9024 9025 u8 burst_upper_bound[0x20]; 9026 9027 u8 reserved_at_40[0x10]; 9028 u8 typical_packet_size[0x10]; 9029 9030 u8 reserved_at_60[0x120]; 9031 }; 9032 9033 struct mlx5_ifc_set_pp_rate_limit_in_bits { 9034 u8 opcode[0x10]; 9035 u8 uid[0x10]; 9036 9037 u8 reserved_at_20[0x10]; 9038 u8 op_mod[0x10]; 9039 9040 u8 reserved_at_40[0x10]; 9041 u8 rate_limit_index[0x10]; 9042 9043 u8 reserved_at_60[0x20]; 9044 9045 struct mlx5_ifc_set_pp_rate_limit_context_bits ctx; 9046 }; 9047 9048 struct mlx5_ifc_access_register_out_bits { 9049 u8 status[0x8]; 9050 u8 reserved_at_8[0x18]; 9051 9052 u8 syndrome[0x20]; 9053 9054 u8 reserved_at_40[0x40]; 9055 9056 u8 register_data[][0x20]; 9057 }; 9058 9059 enum { 9060 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0, 9061 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1, 9062 }; 9063 9064 struct mlx5_ifc_access_register_in_bits { 9065 u8 opcode[0x10]; 9066 u8 reserved_at_10[0x10]; 9067 9068 u8 reserved_at_20[0x10]; 9069 u8 op_mod[0x10]; 9070 9071 u8 reserved_at_40[0x10]; 9072 u8 register_id[0x10]; 9073 9074 u8 argument[0x20]; 9075 9076 u8 register_data[][0x20]; 9077 }; 9078 9079 struct mlx5_ifc_sltp_reg_bits { 9080 u8 status[0x4]; 9081 u8 version[0x4]; 9082 u8 local_port[0x8]; 9083 u8 pnat[0x2]; 9084 u8 reserved_at_12[0x2]; 9085 u8 lane[0x4]; 9086 u8 reserved_at_18[0x8]; 9087 9088 u8 reserved_at_20[0x20]; 9089 9090 u8 reserved_at_40[0x7]; 9091 u8 polarity[0x1]; 9092 u8 ob_tap0[0x8]; 9093 u8 ob_tap1[0x8]; 9094 u8 ob_tap2[0x8]; 9095 9096 u8 reserved_at_60[0xc]; 9097 u8 ob_preemp_mode[0x4]; 9098 u8 ob_reg[0x8]; 9099 u8 ob_bias[0x8]; 9100 9101 u8 reserved_at_80[0x20]; 9102 }; 9103 9104 struct mlx5_ifc_slrg_reg_bits { 9105 u8 status[0x4]; 9106 u8 version[0x4]; 9107 u8 local_port[0x8]; 9108 u8 pnat[0x2]; 9109 u8 reserved_at_12[0x2]; 9110 u8 lane[0x4]; 9111 u8 reserved_at_18[0x8]; 9112 9113 u8 time_to_link_up[0x10]; 9114 u8 reserved_at_30[0xc]; 9115 u8 grade_lane_speed[0x4]; 9116 9117 u8 grade_version[0x8]; 9118 u8 grade[0x18]; 9119 9120 u8 reserved_at_60[0x4]; 9121 u8 height_grade_type[0x4]; 9122 u8 height_grade[0x18]; 9123 9124 u8 height_dz[0x10]; 9125 u8 height_dv[0x10]; 9126 9127 u8 reserved_at_a0[0x10]; 9128 u8 height_sigma[0x10]; 9129 9130 u8 reserved_at_c0[0x20]; 9131 9132 u8 reserved_at_e0[0x4]; 9133 u8 phase_grade_type[0x4]; 9134 u8 phase_grade[0x18]; 9135 9136 u8 reserved_at_100[0x8]; 9137 u8 phase_eo_pos[0x8]; 9138 u8 reserved_at_110[0x8]; 9139 u8 phase_eo_neg[0x8]; 9140 9141 u8 ffe_set_tested[0x10]; 9142 u8 test_errors_per_lane[0x10]; 9143 }; 9144 9145 struct mlx5_ifc_pvlc_reg_bits { 9146 u8 reserved_at_0[0x8]; 9147 u8 local_port[0x8]; 9148 u8 reserved_at_10[0x10]; 9149 9150 u8 reserved_at_20[0x1c]; 9151 u8 vl_hw_cap[0x4]; 9152 9153 u8 reserved_at_40[0x1c]; 9154 u8 vl_admin[0x4]; 9155 9156 u8 reserved_at_60[0x1c]; 9157 u8 vl_operational[0x4]; 9158 }; 9159 9160 struct mlx5_ifc_pude_reg_bits { 9161 u8 swid[0x8]; 9162 u8 local_port[0x8]; 9163 u8 reserved_at_10[0x4]; 9164 u8 admin_status[0x4]; 9165 u8 reserved_at_18[0x4]; 9166 u8 oper_status[0x4]; 9167 9168 u8 reserved_at_20[0x60]; 9169 }; 9170 9171 struct mlx5_ifc_ptys_reg_bits { 9172 u8 reserved_at_0[0x1]; 9173 u8 an_disable_admin[0x1]; 9174 u8 an_disable_cap[0x1]; 9175 u8 reserved_at_3[0x5]; 9176 u8 local_port[0x8]; 9177 u8 reserved_at_10[0xd]; 9178 u8 proto_mask[0x3]; 9179 9180 u8 an_status[0x4]; 9181 u8 reserved_at_24[0xc]; 9182 u8 data_rate_oper[0x10]; 9183 9184 u8 ext_eth_proto_capability[0x20]; 9185 9186 u8 eth_proto_capability[0x20]; 9187 9188 u8 ib_link_width_capability[0x10]; 9189 u8 ib_proto_capability[0x10]; 9190 9191 u8 ext_eth_proto_admin[0x20]; 9192 9193 u8 eth_proto_admin[0x20]; 9194 9195 u8 ib_link_width_admin[0x10]; 9196 u8 ib_proto_admin[0x10]; 9197 9198 u8 ext_eth_proto_oper[0x20]; 9199 9200 u8 eth_proto_oper[0x20]; 9201 9202 u8 ib_link_width_oper[0x10]; 9203 u8 ib_proto_oper[0x10]; 9204 9205 u8 reserved_at_160[0x1c]; 9206 u8 connector_type[0x4]; 9207 9208 u8 eth_proto_lp_advertise[0x20]; 9209 9210 u8 reserved_at_1a0[0x60]; 9211 }; 9212 9213 struct mlx5_ifc_mlcr_reg_bits { 9214 u8 reserved_at_0[0x8]; 9215 u8 local_port[0x8]; 9216 u8 reserved_at_10[0x20]; 9217 9218 u8 beacon_duration[0x10]; 9219 u8 reserved_at_40[0x10]; 9220 9221 u8 beacon_remain[0x10]; 9222 }; 9223 9224 struct mlx5_ifc_ptas_reg_bits { 9225 u8 reserved_at_0[0x20]; 9226 9227 u8 algorithm_options[0x10]; 9228 u8 reserved_at_30[0x4]; 9229 u8 repetitions_mode[0x4]; 9230 u8 num_of_repetitions[0x8]; 9231 9232 u8 grade_version[0x8]; 9233 u8 height_grade_type[0x4]; 9234 u8 phase_grade_type[0x4]; 9235 u8 height_grade_weight[0x8]; 9236 u8 phase_grade_weight[0x8]; 9237 9238 u8 gisim_measure_bits[0x10]; 9239 u8 adaptive_tap_measure_bits[0x10]; 9240 9241 u8 ber_bath_high_error_threshold[0x10]; 9242 u8 ber_bath_mid_error_threshold[0x10]; 9243 9244 u8 ber_bath_low_error_threshold[0x10]; 9245 u8 one_ratio_high_threshold[0x10]; 9246 9247 u8 one_ratio_high_mid_threshold[0x10]; 9248 u8 one_ratio_low_mid_threshold[0x10]; 9249 9250 u8 one_ratio_low_threshold[0x10]; 9251 u8 ndeo_error_threshold[0x10]; 9252 9253 u8 mixer_offset_step_size[0x10]; 9254 u8 reserved_at_110[0x8]; 9255 u8 mix90_phase_for_voltage_bath[0x8]; 9256 9257 u8 mixer_offset_start[0x10]; 9258 u8 mixer_offset_end[0x10]; 9259 9260 u8 reserved_at_140[0x15]; 9261 u8 ber_test_time[0xb]; 9262 }; 9263 9264 struct mlx5_ifc_pspa_reg_bits { 9265 u8 swid[0x8]; 9266 u8 local_port[0x8]; 9267 u8 sub_port[0x8]; 9268 u8 reserved_at_18[0x8]; 9269 9270 u8 reserved_at_20[0x20]; 9271 }; 9272 9273 struct mlx5_ifc_pqdr_reg_bits { 9274 u8 reserved_at_0[0x8]; 9275 u8 local_port[0x8]; 9276 u8 reserved_at_10[0x5]; 9277 u8 prio[0x3]; 9278 u8 reserved_at_18[0x6]; 9279 u8 mode[0x2]; 9280 9281 u8 reserved_at_20[0x20]; 9282 9283 u8 reserved_at_40[0x10]; 9284 u8 min_threshold[0x10]; 9285 9286 u8 reserved_at_60[0x10]; 9287 u8 max_threshold[0x10]; 9288 9289 u8 reserved_at_80[0x10]; 9290 u8 mark_probability_denominator[0x10]; 9291 9292 u8 reserved_at_a0[0x60]; 9293 }; 9294 9295 struct mlx5_ifc_ppsc_reg_bits { 9296 u8 reserved_at_0[0x8]; 9297 u8 local_port[0x8]; 9298 u8 reserved_at_10[0x10]; 9299 9300 u8 reserved_at_20[0x60]; 9301 9302 u8 reserved_at_80[0x1c]; 9303 u8 wrps_admin[0x4]; 9304 9305 u8 reserved_at_a0[0x1c]; 9306 u8 wrps_status[0x4]; 9307 9308 u8 reserved_at_c0[0x8]; 9309 u8 up_threshold[0x8]; 9310 u8 reserved_at_d0[0x8]; 9311 u8 down_threshold[0x8]; 9312 9313 u8 reserved_at_e0[0x20]; 9314 9315 u8 reserved_at_100[0x1c]; 9316 u8 srps_admin[0x4]; 9317 9318 u8 reserved_at_120[0x1c]; 9319 u8 srps_status[0x4]; 9320 9321 u8 reserved_at_140[0x40]; 9322 }; 9323 9324 struct mlx5_ifc_pplr_reg_bits { 9325 u8 reserved_at_0[0x8]; 9326 u8 local_port[0x8]; 9327 u8 reserved_at_10[0x10]; 9328 9329 u8 reserved_at_20[0x8]; 9330 u8 lb_cap[0x8]; 9331 u8 reserved_at_30[0x8]; 9332 u8 lb_en[0x8]; 9333 }; 9334 9335 struct mlx5_ifc_pplm_reg_bits { 9336 u8 reserved_at_0[0x8]; 9337 u8 local_port[0x8]; 9338 u8 reserved_at_10[0x10]; 9339 9340 u8 reserved_at_20[0x20]; 9341 9342 u8 port_profile_mode[0x8]; 9343 u8 static_port_profile[0x8]; 9344 u8 active_port_profile[0x8]; 9345 u8 reserved_at_58[0x8]; 9346 9347 u8 retransmission_active[0x8]; 9348 u8 fec_mode_active[0x18]; 9349 9350 u8 rs_fec_correction_bypass_cap[0x4]; 9351 u8 reserved_at_84[0x8]; 9352 u8 fec_override_cap_56g[0x4]; 9353 u8 fec_override_cap_100g[0x4]; 9354 u8 fec_override_cap_50g[0x4]; 9355 u8 fec_override_cap_25g[0x4]; 9356 u8 fec_override_cap_10g_40g[0x4]; 9357 9358 u8 rs_fec_correction_bypass_admin[0x4]; 9359 u8 reserved_at_a4[0x8]; 9360 u8 fec_override_admin_56g[0x4]; 9361 u8 fec_override_admin_100g[0x4]; 9362 u8 fec_override_admin_50g[0x4]; 9363 u8 fec_override_admin_25g[0x4]; 9364 u8 fec_override_admin_10g_40g[0x4]; 9365 9366 u8 fec_override_cap_400g_8x[0x10]; 9367 u8 fec_override_cap_200g_4x[0x10]; 9368 9369 u8 fec_override_cap_100g_2x[0x10]; 9370 u8 fec_override_cap_50g_1x[0x10]; 9371 9372 u8 fec_override_admin_400g_8x[0x10]; 9373 u8 fec_override_admin_200g_4x[0x10]; 9374 9375 u8 fec_override_admin_100g_2x[0x10]; 9376 u8 fec_override_admin_50g_1x[0x10]; 9377 9378 u8 reserved_at_140[0x140]; 9379 }; 9380 9381 struct mlx5_ifc_ppcnt_reg_bits { 9382 u8 swid[0x8]; 9383 u8 local_port[0x8]; 9384 u8 pnat[0x2]; 9385 u8 reserved_at_12[0x8]; 9386 u8 grp[0x6]; 9387 9388 u8 clr[0x1]; 9389 u8 reserved_at_21[0x1c]; 9390 u8 prio_tc[0x3]; 9391 9392 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set; 9393 }; 9394 9395 struct mlx5_ifc_mpein_reg_bits { 9396 u8 reserved_at_0[0x2]; 9397 u8 depth[0x6]; 9398 u8 pcie_index[0x8]; 9399 u8 node[0x8]; 9400 u8 reserved_at_18[0x8]; 9401 9402 u8 capability_mask[0x20]; 9403 9404 u8 reserved_at_40[0x8]; 9405 u8 link_width_enabled[0x8]; 9406 u8 link_speed_enabled[0x10]; 9407 9408 u8 lane0_physical_position[0x8]; 9409 u8 link_width_active[0x8]; 9410 u8 link_speed_active[0x10]; 9411 9412 u8 num_of_pfs[0x10]; 9413 u8 num_of_vfs[0x10]; 9414 9415 u8 bdf0[0x10]; 9416 u8 reserved_at_b0[0x10]; 9417 9418 u8 max_read_request_size[0x4]; 9419 u8 max_payload_size[0x4]; 9420 u8 reserved_at_c8[0x5]; 9421 u8 pwr_status[0x3]; 9422 u8 port_type[0x4]; 9423 u8 reserved_at_d4[0xb]; 9424 u8 lane_reversal[0x1]; 9425 9426 u8 reserved_at_e0[0x14]; 9427 u8 pci_power[0xc]; 9428 9429 u8 reserved_at_100[0x20]; 9430 9431 u8 device_status[0x10]; 9432 u8 port_state[0x8]; 9433 u8 reserved_at_138[0x8]; 9434 9435 u8 reserved_at_140[0x10]; 9436 u8 receiver_detect_result[0x10]; 9437 9438 u8 reserved_at_160[0x20]; 9439 }; 9440 9441 struct mlx5_ifc_mpcnt_reg_bits { 9442 u8 reserved_at_0[0x8]; 9443 u8 pcie_index[0x8]; 9444 u8 reserved_at_10[0xa]; 9445 u8 grp[0x6]; 9446 9447 u8 clr[0x1]; 9448 u8 reserved_at_21[0x1f]; 9449 9450 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set; 9451 }; 9452 9453 struct mlx5_ifc_ppad_reg_bits { 9454 u8 reserved_at_0[0x3]; 9455 u8 single_mac[0x1]; 9456 u8 reserved_at_4[0x4]; 9457 u8 local_port[0x8]; 9458 u8 mac_47_32[0x10]; 9459 9460 u8 mac_31_0[0x20]; 9461 9462 u8 reserved_at_40[0x40]; 9463 }; 9464 9465 struct mlx5_ifc_pmtu_reg_bits { 9466 u8 reserved_at_0[0x8]; 9467 u8 local_port[0x8]; 9468 u8 reserved_at_10[0x10]; 9469 9470 u8 max_mtu[0x10]; 9471 u8 reserved_at_30[0x10]; 9472 9473 u8 admin_mtu[0x10]; 9474 u8 reserved_at_50[0x10]; 9475 9476 u8 oper_mtu[0x10]; 9477 u8 reserved_at_70[0x10]; 9478 }; 9479 9480 struct mlx5_ifc_pmpr_reg_bits { 9481 u8 reserved_at_0[0x8]; 9482 u8 module[0x8]; 9483 u8 reserved_at_10[0x10]; 9484 9485 u8 reserved_at_20[0x18]; 9486 u8 attenuation_5g[0x8]; 9487 9488 u8 reserved_at_40[0x18]; 9489 u8 attenuation_7g[0x8]; 9490 9491 u8 reserved_at_60[0x18]; 9492 u8 attenuation_12g[0x8]; 9493 }; 9494 9495 struct mlx5_ifc_pmpe_reg_bits { 9496 u8 reserved_at_0[0x8]; 9497 u8 module[0x8]; 9498 u8 reserved_at_10[0xc]; 9499 u8 module_status[0x4]; 9500 9501 u8 reserved_at_20[0x60]; 9502 }; 9503 9504 struct mlx5_ifc_pmpc_reg_bits { 9505 u8 module_state_updated[32][0x8]; 9506 }; 9507 9508 struct mlx5_ifc_pmlpn_reg_bits { 9509 u8 reserved_at_0[0x4]; 9510 u8 mlpn_status[0x4]; 9511 u8 local_port[0x8]; 9512 u8 reserved_at_10[0x10]; 9513 9514 u8 e[0x1]; 9515 u8 reserved_at_21[0x1f]; 9516 }; 9517 9518 struct mlx5_ifc_pmlp_reg_bits { 9519 u8 rxtx[0x1]; 9520 u8 reserved_at_1[0x7]; 9521 u8 local_port[0x8]; 9522 u8 reserved_at_10[0x8]; 9523 u8 width[0x8]; 9524 9525 u8 lane0_module_mapping[0x20]; 9526 9527 u8 lane1_module_mapping[0x20]; 9528 9529 u8 lane2_module_mapping[0x20]; 9530 9531 u8 lane3_module_mapping[0x20]; 9532 9533 u8 reserved_at_a0[0x160]; 9534 }; 9535 9536 struct mlx5_ifc_pmaos_reg_bits { 9537 u8 reserved_at_0[0x8]; 9538 u8 module[0x8]; 9539 u8 reserved_at_10[0x4]; 9540 u8 admin_status[0x4]; 9541 u8 reserved_at_18[0x4]; 9542 u8 oper_status[0x4]; 9543 9544 u8 ase[0x1]; 9545 u8 ee[0x1]; 9546 u8 reserved_at_22[0x1c]; 9547 u8 e[0x2]; 9548 9549 u8 reserved_at_40[0x40]; 9550 }; 9551 9552 struct mlx5_ifc_plpc_reg_bits { 9553 u8 reserved_at_0[0x4]; 9554 u8 profile_id[0xc]; 9555 u8 reserved_at_10[0x4]; 9556 u8 proto_mask[0x4]; 9557 u8 reserved_at_18[0x8]; 9558 9559 u8 reserved_at_20[0x10]; 9560 u8 lane_speed[0x10]; 9561 9562 u8 reserved_at_40[0x17]; 9563 u8 lpbf[0x1]; 9564 u8 fec_mode_policy[0x8]; 9565 9566 u8 retransmission_capability[0x8]; 9567 u8 fec_mode_capability[0x18]; 9568 9569 u8 retransmission_support_admin[0x8]; 9570 u8 fec_mode_support_admin[0x18]; 9571 9572 u8 retransmission_request_admin[0x8]; 9573 u8 fec_mode_request_admin[0x18]; 9574 9575 u8 reserved_at_c0[0x80]; 9576 }; 9577 9578 struct mlx5_ifc_plib_reg_bits { 9579 u8 reserved_at_0[0x8]; 9580 u8 local_port[0x8]; 9581 u8 reserved_at_10[0x8]; 9582 u8 ib_port[0x8]; 9583 9584 u8 reserved_at_20[0x60]; 9585 }; 9586 9587 struct mlx5_ifc_plbf_reg_bits { 9588 u8 reserved_at_0[0x8]; 9589 u8 local_port[0x8]; 9590 u8 reserved_at_10[0xd]; 9591 u8 lbf_mode[0x3]; 9592 9593 u8 reserved_at_20[0x20]; 9594 }; 9595 9596 struct mlx5_ifc_pipg_reg_bits { 9597 u8 reserved_at_0[0x8]; 9598 u8 local_port[0x8]; 9599 u8 reserved_at_10[0x10]; 9600 9601 u8 dic[0x1]; 9602 u8 reserved_at_21[0x19]; 9603 u8 ipg[0x4]; 9604 u8 reserved_at_3e[0x2]; 9605 }; 9606 9607 struct mlx5_ifc_pifr_reg_bits { 9608 u8 reserved_at_0[0x8]; 9609 u8 local_port[0x8]; 9610 u8 reserved_at_10[0x10]; 9611 9612 u8 reserved_at_20[0xe0]; 9613 9614 u8 port_filter[8][0x20]; 9615 9616 u8 port_filter_update_en[8][0x20]; 9617 }; 9618 9619 struct mlx5_ifc_pfcc_reg_bits { 9620 u8 reserved_at_0[0x8]; 9621 u8 local_port[0x8]; 9622 u8 reserved_at_10[0xb]; 9623 u8 ppan_mask_n[0x1]; 9624 u8 minor_stall_mask[0x1]; 9625 u8 critical_stall_mask[0x1]; 9626 u8 reserved_at_1e[0x2]; 9627 9628 u8 ppan[0x4]; 9629 u8 reserved_at_24[0x4]; 9630 u8 prio_mask_tx[0x8]; 9631 u8 reserved_at_30[0x8]; 9632 u8 prio_mask_rx[0x8]; 9633 9634 u8 pptx[0x1]; 9635 u8 aptx[0x1]; 9636 u8 pptx_mask_n[0x1]; 9637 u8 reserved_at_43[0x5]; 9638 u8 pfctx[0x8]; 9639 u8 reserved_at_50[0x10]; 9640 9641 u8 pprx[0x1]; 9642 u8 aprx[0x1]; 9643 u8 pprx_mask_n[0x1]; 9644 u8 reserved_at_63[0x5]; 9645 u8 pfcrx[0x8]; 9646 u8 reserved_at_70[0x10]; 9647 9648 u8 device_stall_minor_watermark[0x10]; 9649 u8 device_stall_critical_watermark[0x10]; 9650 9651 u8 reserved_at_a0[0x60]; 9652 }; 9653 9654 struct mlx5_ifc_pelc_reg_bits { 9655 u8 op[0x4]; 9656 u8 reserved_at_4[0x4]; 9657 u8 local_port[0x8]; 9658 u8 reserved_at_10[0x10]; 9659 9660 u8 op_admin[0x8]; 9661 u8 op_capability[0x8]; 9662 u8 op_request[0x8]; 9663 u8 op_active[0x8]; 9664 9665 u8 admin[0x40]; 9666 9667 u8 capability[0x40]; 9668 9669 u8 request[0x40]; 9670 9671 u8 active[0x40]; 9672 9673 u8 reserved_at_140[0x80]; 9674 }; 9675 9676 struct mlx5_ifc_peir_reg_bits { 9677 u8 reserved_at_0[0x8]; 9678 u8 local_port[0x8]; 9679 u8 reserved_at_10[0x10]; 9680 9681 u8 reserved_at_20[0xc]; 9682 u8 error_count[0x4]; 9683 u8 reserved_at_30[0x10]; 9684 9685 u8 reserved_at_40[0xc]; 9686 u8 lane[0x4]; 9687 u8 reserved_at_50[0x8]; 9688 u8 error_type[0x8]; 9689 }; 9690 9691 struct mlx5_ifc_mpegc_reg_bits { 9692 u8 reserved_at_0[0x30]; 9693 u8 field_select[0x10]; 9694 9695 u8 tx_overflow_sense[0x1]; 9696 u8 mark_cqe[0x1]; 9697 u8 mark_cnp[0x1]; 9698 u8 reserved_at_43[0x1b]; 9699 u8 tx_lossy_overflow_oper[0x2]; 9700 9701 u8 reserved_at_60[0x100]; 9702 }; 9703 9704 enum { 9705 MLX5_MTUTC_OPERATION_SET_TIME_IMMEDIATE = 0x1, 9706 MLX5_MTUTC_OPERATION_ADJUST_TIME = 0x2, 9707 MLX5_MTUTC_OPERATION_ADJUST_FREQ_UTC = 0x3, 9708 }; 9709 9710 struct mlx5_ifc_mtutc_reg_bits { 9711 u8 reserved_at_0[0x1c]; 9712 u8 operation[0x4]; 9713 9714 u8 freq_adjustment[0x20]; 9715 9716 u8 reserved_at_40[0x40]; 9717 9718 u8 utc_sec[0x20]; 9719 9720 u8 reserved_at_a0[0x2]; 9721 u8 utc_nsec[0x1e]; 9722 9723 u8 time_adjustment[0x20]; 9724 }; 9725 9726 struct mlx5_ifc_pcam_enhanced_features_bits { 9727 u8 reserved_at_0[0x68]; 9728 u8 fec_50G_per_lane_in_pplm[0x1]; 9729 u8 reserved_at_69[0x4]; 9730 u8 rx_icrc_encapsulated_counter[0x1]; 9731 u8 reserved_at_6e[0x4]; 9732 u8 ptys_extended_ethernet[0x1]; 9733 u8 reserved_at_73[0x3]; 9734 u8 pfcc_mask[0x1]; 9735 u8 reserved_at_77[0x3]; 9736 u8 per_lane_error_counters[0x1]; 9737 u8 rx_buffer_fullness_counters[0x1]; 9738 u8 ptys_connector_type[0x1]; 9739 u8 reserved_at_7d[0x1]; 9740 u8 ppcnt_discard_group[0x1]; 9741 u8 ppcnt_statistical_group[0x1]; 9742 }; 9743 9744 struct mlx5_ifc_pcam_regs_5000_to_507f_bits { 9745 u8 port_access_reg_cap_mask_127_to_96[0x20]; 9746 u8 port_access_reg_cap_mask_95_to_64[0x20]; 9747 9748 u8 port_access_reg_cap_mask_63_to_36[0x1c]; 9749 u8 pplm[0x1]; 9750 u8 port_access_reg_cap_mask_34_to_32[0x3]; 9751 9752 u8 port_access_reg_cap_mask_31_to_13[0x13]; 9753 u8 pbmc[0x1]; 9754 u8 pptb[0x1]; 9755 u8 port_access_reg_cap_mask_10_to_09[0x2]; 9756 u8 ppcnt[0x1]; 9757 u8 port_access_reg_cap_mask_07_to_00[0x8]; 9758 }; 9759 9760 struct mlx5_ifc_pcam_reg_bits { 9761 u8 reserved_at_0[0x8]; 9762 u8 feature_group[0x8]; 9763 u8 reserved_at_10[0x8]; 9764 u8 access_reg_group[0x8]; 9765 9766 u8 reserved_at_20[0x20]; 9767 9768 union { 9769 struct mlx5_ifc_pcam_regs_5000_to_507f_bits regs_5000_to_507f; 9770 u8 reserved_at_0[0x80]; 9771 } port_access_reg_cap_mask; 9772 9773 u8 reserved_at_c0[0x80]; 9774 9775 union { 9776 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features; 9777 u8 reserved_at_0[0x80]; 9778 } feature_cap_mask; 9779 9780 u8 reserved_at_1c0[0xc0]; 9781 }; 9782 9783 struct mlx5_ifc_mcam_enhanced_features_bits { 9784 u8 reserved_at_0[0x5d]; 9785 u8 mcia_32dwords[0x1]; 9786 u8 reserved_at_5e[0xc]; 9787 u8 reset_state[0x1]; 9788 u8 ptpcyc2realtime_modify[0x1]; 9789 u8 reserved_at_6c[0x2]; 9790 u8 pci_status_and_power[0x1]; 9791 u8 reserved_at_6f[0x5]; 9792 u8 mark_tx_action_cnp[0x1]; 9793 u8 mark_tx_action_cqe[0x1]; 9794 u8 dynamic_tx_overflow[0x1]; 9795 u8 reserved_at_77[0x4]; 9796 u8 pcie_outbound_stalled[0x1]; 9797 u8 tx_overflow_buffer_pkt[0x1]; 9798 u8 mtpps_enh_out_per_adj[0x1]; 9799 u8 mtpps_fs[0x1]; 9800 u8 pcie_performance_group[0x1]; 9801 }; 9802 9803 struct mlx5_ifc_mcam_access_reg_bits { 9804 u8 reserved_at_0[0x1c]; 9805 u8 mcda[0x1]; 9806 u8 mcc[0x1]; 9807 u8 mcqi[0x1]; 9808 u8 mcqs[0x1]; 9809 9810 u8 regs_95_to_87[0x9]; 9811 u8 mpegc[0x1]; 9812 u8 mtutc[0x1]; 9813 u8 regs_84_to_68[0x11]; 9814 u8 tracer_registers[0x4]; 9815 9816 u8 regs_63_to_46[0x12]; 9817 u8 mrtc[0x1]; 9818 u8 regs_44_to_32[0xd]; 9819 9820 u8 regs_31_to_0[0x20]; 9821 }; 9822 9823 struct mlx5_ifc_mcam_access_reg_bits1 { 9824 u8 regs_127_to_96[0x20]; 9825 9826 u8 regs_95_to_64[0x20]; 9827 9828 u8 regs_63_to_32[0x20]; 9829 9830 u8 regs_31_to_0[0x20]; 9831 }; 9832 9833 struct mlx5_ifc_mcam_access_reg_bits2 { 9834 u8 regs_127_to_99[0x1d]; 9835 u8 mirc[0x1]; 9836 u8 regs_97_to_96[0x2]; 9837 9838 u8 regs_95_to_64[0x20]; 9839 9840 u8 regs_63_to_32[0x20]; 9841 9842 u8 regs_31_to_0[0x20]; 9843 }; 9844 9845 struct mlx5_ifc_mcam_reg_bits { 9846 u8 reserved_at_0[0x8]; 9847 u8 feature_group[0x8]; 9848 u8 reserved_at_10[0x8]; 9849 u8 access_reg_group[0x8]; 9850 9851 u8 reserved_at_20[0x20]; 9852 9853 union { 9854 struct mlx5_ifc_mcam_access_reg_bits access_regs; 9855 struct mlx5_ifc_mcam_access_reg_bits1 access_regs1; 9856 struct mlx5_ifc_mcam_access_reg_bits2 access_regs2; 9857 u8 reserved_at_0[0x80]; 9858 } mng_access_reg_cap_mask; 9859 9860 u8 reserved_at_c0[0x80]; 9861 9862 union { 9863 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features; 9864 u8 reserved_at_0[0x80]; 9865 } mng_feature_cap_mask; 9866 9867 u8 reserved_at_1c0[0x80]; 9868 }; 9869 9870 struct mlx5_ifc_qcam_access_reg_cap_mask { 9871 u8 qcam_access_reg_cap_mask_127_to_20[0x6C]; 9872 u8 qpdpm[0x1]; 9873 u8 qcam_access_reg_cap_mask_18_to_4[0x0F]; 9874 u8 qdpm[0x1]; 9875 u8 qpts[0x1]; 9876 u8 qcap[0x1]; 9877 u8 qcam_access_reg_cap_mask_0[0x1]; 9878 }; 9879 9880 struct mlx5_ifc_qcam_qos_feature_cap_mask { 9881 u8 qcam_qos_feature_cap_mask_127_to_1[0x7F]; 9882 u8 qpts_trust_both[0x1]; 9883 }; 9884 9885 struct mlx5_ifc_qcam_reg_bits { 9886 u8 reserved_at_0[0x8]; 9887 u8 feature_group[0x8]; 9888 u8 reserved_at_10[0x8]; 9889 u8 access_reg_group[0x8]; 9890 u8 reserved_at_20[0x20]; 9891 9892 union { 9893 struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap; 9894 u8 reserved_at_0[0x80]; 9895 } qos_access_reg_cap_mask; 9896 9897 u8 reserved_at_c0[0x80]; 9898 9899 union { 9900 struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap; 9901 u8 reserved_at_0[0x80]; 9902 } qos_feature_cap_mask; 9903 9904 u8 reserved_at_1c0[0x80]; 9905 }; 9906 9907 struct mlx5_ifc_core_dump_reg_bits { 9908 u8 reserved_at_0[0x18]; 9909 u8 core_dump_type[0x8]; 9910 9911 u8 reserved_at_20[0x30]; 9912 u8 vhca_id[0x10]; 9913 9914 u8 reserved_at_60[0x8]; 9915 u8 qpn[0x18]; 9916 u8 reserved_at_80[0x180]; 9917 }; 9918 9919 struct mlx5_ifc_pcap_reg_bits { 9920 u8 reserved_at_0[0x8]; 9921 u8 local_port[0x8]; 9922 u8 reserved_at_10[0x10]; 9923 9924 u8 port_capability_mask[4][0x20]; 9925 }; 9926 9927 struct mlx5_ifc_paos_reg_bits { 9928 u8 swid[0x8]; 9929 u8 local_port[0x8]; 9930 u8 reserved_at_10[0x4]; 9931 u8 admin_status[0x4]; 9932 u8 reserved_at_18[0x4]; 9933 u8 oper_status[0x4]; 9934 9935 u8 ase[0x1]; 9936 u8 ee[0x1]; 9937 u8 reserved_at_22[0x1c]; 9938 u8 e[0x2]; 9939 9940 u8 reserved_at_40[0x40]; 9941 }; 9942 9943 struct mlx5_ifc_pamp_reg_bits { 9944 u8 reserved_at_0[0x8]; 9945 u8 opamp_group[0x8]; 9946 u8 reserved_at_10[0xc]; 9947 u8 opamp_group_type[0x4]; 9948 9949 u8 start_index[0x10]; 9950 u8 reserved_at_30[0x4]; 9951 u8 num_of_indices[0xc]; 9952 9953 u8 index_data[18][0x10]; 9954 }; 9955 9956 struct mlx5_ifc_pcmr_reg_bits { 9957 u8 reserved_at_0[0x8]; 9958 u8 local_port[0x8]; 9959 u8 reserved_at_10[0x10]; 9960 9961 u8 entropy_force_cap[0x1]; 9962 u8 entropy_calc_cap[0x1]; 9963 u8 entropy_gre_calc_cap[0x1]; 9964 u8 reserved_at_23[0xf]; 9965 u8 rx_ts_over_crc_cap[0x1]; 9966 u8 reserved_at_33[0xb]; 9967 u8 fcs_cap[0x1]; 9968 u8 reserved_at_3f[0x1]; 9969 9970 u8 entropy_force[0x1]; 9971 u8 entropy_calc[0x1]; 9972 u8 entropy_gre_calc[0x1]; 9973 u8 reserved_at_43[0xf]; 9974 u8 rx_ts_over_crc[0x1]; 9975 u8 reserved_at_53[0xb]; 9976 u8 fcs_chk[0x1]; 9977 u8 reserved_at_5f[0x1]; 9978 }; 9979 9980 struct mlx5_ifc_lane_2_module_mapping_bits { 9981 u8 reserved_at_0[0x4]; 9982 u8 rx_lane[0x4]; 9983 u8 reserved_at_8[0x4]; 9984 u8 tx_lane[0x4]; 9985 u8 reserved_at_10[0x8]; 9986 u8 module[0x8]; 9987 }; 9988 9989 struct mlx5_ifc_bufferx_reg_bits { 9990 u8 reserved_at_0[0x6]; 9991 u8 lossy[0x1]; 9992 u8 epsb[0x1]; 9993 u8 reserved_at_8[0x8]; 9994 u8 size[0x10]; 9995 9996 u8 xoff_threshold[0x10]; 9997 u8 xon_threshold[0x10]; 9998 }; 9999 10000 struct mlx5_ifc_set_node_in_bits { 10001 u8 node_description[64][0x8]; 10002 }; 10003 10004 struct mlx5_ifc_register_power_settings_bits { 10005 u8 reserved_at_0[0x18]; 10006 u8 power_settings_level[0x8]; 10007 10008 u8 reserved_at_20[0x60]; 10009 }; 10010 10011 struct mlx5_ifc_register_host_endianness_bits { 10012 u8 he[0x1]; 10013 u8 reserved_at_1[0x1f]; 10014 10015 u8 reserved_at_20[0x60]; 10016 }; 10017 10018 struct mlx5_ifc_umr_pointer_desc_argument_bits { 10019 u8 reserved_at_0[0x20]; 10020 10021 u8 mkey[0x20]; 10022 10023 u8 addressh_63_32[0x20]; 10024 10025 u8 addressl_31_0[0x20]; 10026 }; 10027 10028 struct mlx5_ifc_ud_adrs_vector_bits { 10029 u8 dc_key[0x40]; 10030 10031 u8 ext[0x1]; 10032 u8 reserved_at_41[0x7]; 10033 u8 destination_qp_dct[0x18]; 10034 10035 u8 static_rate[0x4]; 10036 u8 sl_eth_prio[0x4]; 10037 u8 fl[0x1]; 10038 u8 mlid[0x7]; 10039 u8 rlid_udp_sport[0x10]; 10040 10041 u8 reserved_at_80[0x20]; 10042 10043 u8 rmac_47_16[0x20]; 10044 10045 u8 rmac_15_0[0x10]; 10046 u8 tclass[0x8]; 10047 u8 hop_limit[0x8]; 10048 10049 u8 reserved_at_e0[0x1]; 10050 u8 grh[0x1]; 10051 u8 reserved_at_e2[0x2]; 10052 u8 src_addr_index[0x8]; 10053 u8 flow_label[0x14]; 10054 10055 u8 rgid_rip[16][0x8]; 10056 }; 10057 10058 struct mlx5_ifc_pages_req_event_bits { 10059 u8 reserved_at_0[0x10]; 10060 u8 function_id[0x10]; 10061 10062 u8 num_pages[0x20]; 10063 10064 u8 reserved_at_40[0xa0]; 10065 }; 10066 10067 struct mlx5_ifc_eqe_bits { 10068 u8 reserved_at_0[0x8]; 10069 u8 event_type[0x8]; 10070 u8 reserved_at_10[0x8]; 10071 u8 event_sub_type[0x8]; 10072 10073 u8 reserved_at_20[0xe0]; 10074 10075 union mlx5_ifc_event_auto_bits event_data; 10076 10077 u8 reserved_at_1e0[0x10]; 10078 u8 signature[0x8]; 10079 u8 reserved_at_1f8[0x7]; 10080 u8 owner[0x1]; 10081 }; 10082 10083 enum { 10084 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7, 10085 }; 10086 10087 struct mlx5_ifc_cmd_queue_entry_bits { 10088 u8 type[0x8]; 10089 u8 reserved_at_8[0x18]; 10090 10091 u8 input_length[0x20]; 10092 10093 u8 input_mailbox_pointer_63_32[0x20]; 10094 10095 u8 input_mailbox_pointer_31_9[0x17]; 10096 u8 reserved_at_77[0x9]; 10097 10098 u8 command_input_inline_data[16][0x8]; 10099 10100 u8 command_output_inline_data[16][0x8]; 10101 10102 u8 output_mailbox_pointer_63_32[0x20]; 10103 10104 u8 output_mailbox_pointer_31_9[0x17]; 10105 u8 reserved_at_1b7[0x9]; 10106 10107 u8 output_length[0x20]; 10108 10109 u8 token[0x8]; 10110 u8 signature[0x8]; 10111 u8 reserved_at_1f0[0x8]; 10112 u8 status[0x7]; 10113 u8 ownership[0x1]; 10114 }; 10115 10116 struct mlx5_ifc_cmd_out_bits { 10117 u8 status[0x8]; 10118 u8 reserved_at_8[0x18]; 10119 10120 u8 syndrome[0x20]; 10121 10122 u8 command_output[0x20]; 10123 }; 10124 10125 struct mlx5_ifc_cmd_in_bits { 10126 u8 opcode[0x10]; 10127 u8 reserved_at_10[0x10]; 10128 10129 u8 reserved_at_20[0x10]; 10130 u8 op_mod[0x10]; 10131 10132 u8 command[][0x20]; 10133 }; 10134 10135 struct mlx5_ifc_cmd_if_box_bits { 10136 u8 mailbox_data[512][0x8]; 10137 10138 u8 reserved_at_1000[0x180]; 10139 10140 u8 next_pointer_63_32[0x20]; 10141 10142 u8 next_pointer_31_10[0x16]; 10143 u8 reserved_at_11b6[0xa]; 10144 10145 u8 block_number[0x20]; 10146 10147 u8 reserved_at_11e0[0x8]; 10148 u8 token[0x8]; 10149 u8 ctrl_signature[0x8]; 10150 u8 signature[0x8]; 10151 }; 10152 10153 struct mlx5_ifc_mtt_bits { 10154 u8 ptag_63_32[0x20]; 10155 10156 u8 ptag_31_8[0x18]; 10157 u8 reserved_at_38[0x6]; 10158 u8 wr_en[0x1]; 10159 u8 rd_en[0x1]; 10160 }; 10161 10162 struct mlx5_ifc_query_wol_rol_out_bits { 10163 u8 status[0x8]; 10164 u8 reserved_at_8[0x18]; 10165 10166 u8 syndrome[0x20]; 10167 10168 u8 reserved_at_40[0x10]; 10169 u8 rol_mode[0x8]; 10170 u8 wol_mode[0x8]; 10171 10172 u8 reserved_at_60[0x20]; 10173 }; 10174 10175 struct mlx5_ifc_query_wol_rol_in_bits { 10176 u8 opcode[0x10]; 10177 u8 reserved_at_10[0x10]; 10178 10179 u8 reserved_at_20[0x10]; 10180 u8 op_mod[0x10]; 10181 10182 u8 reserved_at_40[0x40]; 10183 }; 10184 10185 struct mlx5_ifc_set_wol_rol_out_bits { 10186 u8 status[0x8]; 10187 u8 reserved_at_8[0x18]; 10188 10189 u8 syndrome[0x20]; 10190 10191 u8 reserved_at_40[0x40]; 10192 }; 10193 10194 struct mlx5_ifc_set_wol_rol_in_bits { 10195 u8 opcode[0x10]; 10196 u8 reserved_at_10[0x10]; 10197 10198 u8 reserved_at_20[0x10]; 10199 u8 op_mod[0x10]; 10200 10201 u8 rol_mode_valid[0x1]; 10202 u8 wol_mode_valid[0x1]; 10203 u8 reserved_at_42[0xe]; 10204 u8 rol_mode[0x8]; 10205 u8 wol_mode[0x8]; 10206 10207 u8 reserved_at_60[0x20]; 10208 }; 10209 10210 enum { 10211 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0, 10212 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1, 10213 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2, 10214 }; 10215 10216 enum { 10217 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0, 10218 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1, 10219 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2, 10220 }; 10221 10222 enum { 10223 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR = 0x1, 10224 MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC = 0x7, 10225 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR = 0x8, 10226 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR = 0x9, 10227 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR = 0xa, 10228 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR = 0xb, 10229 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN = 0xc, 10230 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR = 0xd, 10231 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV = 0xe, 10232 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR = 0xf, 10233 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR = 0x10, 10234 }; 10235 10236 struct mlx5_ifc_initial_seg_bits { 10237 u8 fw_rev_minor[0x10]; 10238 u8 fw_rev_major[0x10]; 10239 10240 u8 cmd_interface_rev[0x10]; 10241 u8 fw_rev_subminor[0x10]; 10242 10243 u8 reserved_at_40[0x40]; 10244 10245 u8 cmdq_phy_addr_63_32[0x20]; 10246 10247 u8 cmdq_phy_addr_31_12[0x14]; 10248 u8 reserved_at_b4[0x2]; 10249 u8 nic_interface[0x2]; 10250 u8 log_cmdq_size[0x4]; 10251 u8 log_cmdq_stride[0x4]; 10252 10253 u8 command_doorbell_vector[0x20]; 10254 10255 u8 reserved_at_e0[0xf00]; 10256 10257 u8 initializing[0x1]; 10258 u8 reserved_at_fe1[0x4]; 10259 u8 nic_interface_supported[0x3]; 10260 u8 embedded_cpu[0x1]; 10261 u8 reserved_at_fe9[0x17]; 10262 10263 struct mlx5_ifc_health_buffer_bits health_buffer; 10264 10265 u8 no_dram_nic_offset[0x20]; 10266 10267 u8 reserved_at_1220[0x6e40]; 10268 10269 u8 reserved_at_8060[0x1f]; 10270 u8 clear_int[0x1]; 10271 10272 u8 health_syndrome[0x8]; 10273 u8 health_counter[0x18]; 10274 10275 u8 reserved_at_80a0[0x17fc0]; 10276 }; 10277 10278 struct mlx5_ifc_mtpps_reg_bits { 10279 u8 reserved_at_0[0xc]; 10280 u8 cap_number_of_pps_pins[0x4]; 10281 u8 reserved_at_10[0x4]; 10282 u8 cap_max_num_of_pps_in_pins[0x4]; 10283 u8 reserved_at_18[0x4]; 10284 u8 cap_max_num_of_pps_out_pins[0x4]; 10285 10286 u8 reserved_at_20[0x24]; 10287 u8 cap_pin_3_mode[0x4]; 10288 u8 reserved_at_48[0x4]; 10289 u8 cap_pin_2_mode[0x4]; 10290 u8 reserved_at_50[0x4]; 10291 u8 cap_pin_1_mode[0x4]; 10292 u8 reserved_at_58[0x4]; 10293 u8 cap_pin_0_mode[0x4]; 10294 10295 u8 reserved_at_60[0x4]; 10296 u8 cap_pin_7_mode[0x4]; 10297 u8 reserved_at_68[0x4]; 10298 u8 cap_pin_6_mode[0x4]; 10299 u8 reserved_at_70[0x4]; 10300 u8 cap_pin_5_mode[0x4]; 10301 u8 reserved_at_78[0x4]; 10302 u8 cap_pin_4_mode[0x4]; 10303 10304 u8 field_select[0x20]; 10305 u8 reserved_at_a0[0x60]; 10306 10307 u8 enable[0x1]; 10308 u8 reserved_at_101[0xb]; 10309 u8 pattern[0x4]; 10310 u8 reserved_at_110[0x4]; 10311 u8 pin_mode[0x4]; 10312 u8 pin[0x8]; 10313 10314 u8 reserved_at_120[0x20]; 10315 10316 u8 time_stamp[0x40]; 10317 10318 u8 out_pulse_duration[0x10]; 10319 u8 out_periodic_adjustment[0x10]; 10320 u8 enhanced_out_periodic_adjustment[0x20]; 10321 10322 u8 reserved_at_1c0[0x20]; 10323 }; 10324 10325 struct mlx5_ifc_mtppse_reg_bits { 10326 u8 reserved_at_0[0x18]; 10327 u8 pin[0x8]; 10328 u8 event_arm[0x1]; 10329 u8 reserved_at_21[0x1b]; 10330 u8 event_generation_mode[0x4]; 10331 u8 reserved_at_40[0x40]; 10332 }; 10333 10334 struct mlx5_ifc_mcqs_reg_bits { 10335 u8 last_index_flag[0x1]; 10336 u8 reserved_at_1[0x7]; 10337 u8 fw_device[0x8]; 10338 u8 component_index[0x10]; 10339 10340 u8 reserved_at_20[0x10]; 10341 u8 identifier[0x10]; 10342 10343 u8 reserved_at_40[0x17]; 10344 u8 component_status[0x5]; 10345 u8 component_update_state[0x4]; 10346 10347 u8 last_update_state_changer_type[0x4]; 10348 u8 last_update_state_changer_host_id[0x4]; 10349 u8 reserved_at_68[0x18]; 10350 }; 10351 10352 struct mlx5_ifc_mcqi_cap_bits { 10353 u8 supported_info_bitmask[0x20]; 10354 10355 u8 component_size[0x20]; 10356 10357 u8 max_component_size[0x20]; 10358 10359 u8 log_mcda_word_size[0x4]; 10360 u8 reserved_at_64[0xc]; 10361 u8 mcda_max_write_size[0x10]; 10362 10363 u8 rd_en[0x1]; 10364 u8 reserved_at_81[0x1]; 10365 u8 match_chip_id[0x1]; 10366 u8 match_psid[0x1]; 10367 u8 check_user_timestamp[0x1]; 10368 u8 match_base_guid_mac[0x1]; 10369 u8 reserved_at_86[0x1a]; 10370 }; 10371 10372 struct mlx5_ifc_mcqi_version_bits { 10373 u8 reserved_at_0[0x2]; 10374 u8 build_time_valid[0x1]; 10375 u8 user_defined_time_valid[0x1]; 10376 u8 reserved_at_4[0x14]; 10377 u8 version_string_length[0x8]; 10378 10379 u8 version[0x20]; 10380 10381 u8 build_time[0x40]; 10382 10383 u8 user_defined_time[0x40]; 10384 10385 u8 build_tool_version[0x20]; 10386 10387 u8 reserved_at_e0[0x20]; 10388 10389 u8 version_string[92][0x8]; 10390 }; 10391 10392 struct mlx5_ifc_mcqi_activation_method_bits { 10393 u8 pending_server_ac_power_cycle[0x1]; 10394 u8 pending_server_dc_power_cycle[0x1]; 10395 u8 pending_server_reboot[0x1]; 10396 u8 pending_fw_reset[0x1]; 10397 u8 auto_activate[0x1]; 10398 u8 all_hosts_sync[0x1]; 10399 u8 device_hw_reset[0x1]; 10400 u8 reserved_at_7[0x19]; 10401 }; 10402 10403 union mlx5_ifc_mcqi_reg_data_bits { 10404 struct mlx5_ifc_mcqi_cap_bits mcqi_caps; 10405 struct mlx5_ifc_mcqi_version_bits mcqi_version; 10406 struct mlx5_ifc_mcqi_activation_method_bits mcqi_activation_mathod; 10407 }; 10408 10409 struct mlx5_ifc_mcqi_reg_bits { 10410 u8 read_pending_component[0x1]; 10411 u8 reserved_at_1[0xf]; 10412 u8 component_index[0x10]; 10413 10414 u8 reserved_at_20[0x20]; 10415 10416 u8 reserved_at_40[0x1b]; 10417 u8 info_type[0x5]; 10418 10419 u8 info_size[0x20]; 10420 10421 u8 offset[0x20]; 10422 10423 u8 reserved_at_a0[0x10]; 10424 u8 data_size[0x10]; 10425 10426 union mlx5_ifc_mcqi_reg_data_bits data[]; 10427 }; 10428 10429 struct mlx5_ifc_mcc_reg_bits { 10430 u8 reserved_at_0[0x4]; 10431 u8 time_elapsed_since_last_cmd[0xc]; 10432 u8 reserved_at_10[0x8]; 10433 u8 instruction[0x8]; 10434 10435 u8 reserved_at_20[0x10]; 10436 u8 component_index[0x10]; 10437 10438 u8 reserved_at_40[0x8]; 10439 u8 update_handle[0x18]; 10440 10441 u8 handle_owner_type[0x4]; 10442 u8 handle_owner_host_id[0x4]; 10443 u8 reserved_at_68[0x1]; 10444 u8 control_progress[0x7]; 10445 u8 error_code[0x8]; 10446 u8 reserved_at_78[0x4]; 10447 u8 control_state[0x4]; 10448 10449 u8 component_size[0x20]; 10450 10451 u8 reserved_at_a0[0x60]; 10452 }; 10453 10454 struct mlx5_ifc_mcda_reg_bits { 10455 u8 reserved_at_0[0x8]; 10456 u8 update_handle[0x18]; 10457 10458 u8 offset[0x20]; 10459 10460 u8 reserved_at_40[0x10]; 10461 u8 size[0x10]; 10462 10463 u8 reserved_at_60[0x20]; 10464 10465 u8 data[][0x20]; 10466 }; 10467 10468 enum { 10469 MLX5_MFRL_REG_RESET_STATE_IDLE = 0, 10470 MLX5_MFRL_REG_RESET_STATE_IN_NEGOTIATION = 1, 10471 MLX5_MFRL_REG_RESET_STATE_RESET_IN_PROGRESS = 2, 10472 MLX5_MFRL_REG_RESET_STATE_TIMEOUT = 3, 10473 MLX5_MFRL_REG_RESET_STATE_NACK = 4, 10474 }; 10475 10476 enum { 10477 MLX5_MFRL_REG_RESET_TYPE_FULL_CHIP = BIT(0), 10478 MLX5_MFRL_REG_RESET_TYPE_NET_PORT_ALIVE = BIT(1), 10479 }; 10480 10481 enum { 10482 MLX5_MFRL_REG_RESET_LEVEL0 = BIT(0), 10483 MLX5_MFRL_REG_RESET_LEVEL3 = BIT(3), 10484 MLX5_MFRL_REG_RESET_LEVEL6 = BIT(6), 10485 }; 10486 10487 struct mlx5_ifc_mfrl_reg_bits { 10488 u8 reserved_at_0[0x20]; 10489 10490 u8 reserved_at_20[0x2]; 10491 u8 pci_sync_for_fw_update_start[0x1]; 10492 u8 pci_sync_for_fw_update_resp[0x2]; 10493 u8 rst_type_sel[0x3]; 10494 u8 reserved_at_28[0x4]; 10495 u8 reset_state[0x4]; 10496 u8 reset_type[0x8]; 10497 u8 reset_level[0x8]; 10498 }; 10499 10500 struct mlx5_ifc_mirc_reg_bits { 10501 u8 reserved_at_0[0x18]; 10502 u8 status_code[0x8]; 10503 10504 u8 reserved_at_20[0x20]; 10505 }; 10506 10507 struct mlx5_ifc_pddr_monitor_opcode_bits { 10508 u8 reserved_at_0[0x10]; 10509 u8 monitor_opcode[0x10]; 10510 }; 10511 10512 union mlx5_ifc_pddr_troubleshooting_page_status_opcode_auto_bits { 10513 struct mlx5_ifc_pddr_monitor_opcode_bits pddr_monitor_opcode; 10514 u8 reserved_at_0[0x20]; 10515 }; 10516 10517 enum { 10518 /* Monitor opcodes */ 10519 MLX5_PDDR_REG_TRBLSH_GROUP_OPCODE_MONITOR = 0x0, 10520 }; 10521 10522 struct mlx5_ifc_pddr_troubleshooting_page_bits { 10523 u8 reserved_at_0[0x10]; 10524 u8 group_opcode[0x10]; 10525 10526 union mlx5_ifc_pddr_troubleshooting_page_status_opcode_auto_bits status_opcode; 10527 10528 u8 reserved_at_40[0x20]; 10529 10530 u8 status_message[59][0x20]; 10531 }; 10532 10533 union mlx5_ifc_pddr_reg_page_data_auto_bits { 10534 struct mlx5_ifc_pddr_troubleshooting_page_bits pddr_troubleshooting_page; 10535 u8 reserved_at_0[0x7c0]; 10536 }; 10537 10538 enum { 10539 MLX5_PDDR_REG_PAGE_SELECT_TROUBLESHOOTING_INFO_PAGE = 0x1, 10540 }; 10541 10542 struct mlx5_ifc_pddr_reg_bits { 10543 u8 reserved_at_0[0x8]; 10544 u8 local_port[0x8]; 10545 u8 pnat[0x2]; 10546 u8 reserved_at_12[0xe]; 10547 10548 u8 reserved_at_20[0x18]; 10549 u8 page_select[0x8]; 10550 10551 union mlx5_ifc_pddr_reg_page_data_auto_bits page_data; 10552 }; 10553 10554 struct mlx5_ifc_mrtc_reg_bits { 10555 u8 time_synced[0x1]; 10556 u8 reserved_at_1[0x1f]; 10557 10558 u8 reserved_at_20[0x20]; 10559 10560 u8 time_h[0x20]; 10561 10562 u8 time_l[0x20]; 10563 }; 10564 10565 union mlx5_ifc_ports_control_registers_document_bits { 10566 struct mlx5_ifc_bufferx_reg_bits bufferx_reg; 10567 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 10568 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 10569 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 10570 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 10571 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 10572 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 10573 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout; 10574 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout; 10575 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping; 10576 struct mlx5_ifc_pamp_reg_bits pamp_reg; 10577 struct mlx5_ifc_paos_reg_bits paos_reg; 10578 struct mlx5_ifc_pcap_reg_bits pcap_reg; 10579 struct mlx5_ifc_pddr_monitor_opcode_bits pddr_monitor_opcode; 10580 struct mlx5_ifc_pddr_reg_bits pddr_reg; 10581 struct mlx5_ifc_pddr_troubleshooting_page_bits pddr_troubleshooting_page; 10582 struct mlx5_ifc_peir_reg_bits peir_reg; 10583 struct mlx5_ifc_pelc_reg_bits pelc_reg; 10584 struct mlx5_ifc_pfcc_reg_bits pfcc_reg; 10585 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 10586 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 10587 struct mlx5_ifc_pifr_reg_bits pifr_reg; 10588 struct mlx5_ifc_pipg_reg_bits pipg_reg; 10589 struct mlx5_ifc_plbf_reg_bits plbf_reg; 10590 struct mlx5_ifc_plib_reg_bits plib_reg; 10591 struct mlx5_ifc_plpc_reg_bits plpc_reg; 10592 struct mlx5_ifc_pmaos_reg_bits pmaos_reg; 10593 struct mlx5_ifc_pmlp_reg_bits pmlp_reg; 10594 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg; 10595 struct mlx5_ifc_pmpc_reg_bits pmpc_reg; 10596 struct mlx5_ifc_pmpe_reg_bits pmpe_reg; 10597 struct mlx5_ifc_pmpr_reg_bits pmpr_reg; 10598 struct mlx5_ifc_pmtu_reg_bits pmtu_reg; 10599 struct mlx5_ifc_ppad_reg_bits ppad_reg; 10600 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg; 10601 struct mlx5_ifc_mpein_reg_bits mpein_reg; 10602 struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg; 10603 struct mlx5_ifc_pplm_reg_bits pplm_reg; 10604 struct mlx5_ifc_pplr_reg_bits pplr_reg; 10605 struct mlx5_ifc_ppsc_reg_bits ppsc_reg; 10606 struct mlx5_ifc_pqdr_reg_bits pqdr_reg; 10607 struct mlx5_ifc_pspa_reg_bits pspa_reg; 10608 struct mlx5_ifc_ptas_reg_bits ptas_reg; 10609 struct mlx5_ifc_ptys_reg_bits ptys_reg; 10610 struct mlx5_ifc_mlcr_reg_bits mlcr_reg; 10611 struct mlx5_ifc_pude_reg_bits pude_reg; 10612 struct mlx5_ifc_pvlc_reg_bits pvlc_reg; 10613 struct mlx5_ifc_slrg_reg_bits slrg_reg; 10614 struct mlx5_ifc_sltp_reg_bits sltp_reg; 10615 struct mlx5_ifc_mtpps_reg_bits mtpps_reg; 10616 struct mlx5_ifc_mtppse_reg_bits mtppse_reg; 10617 struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg; 10618 struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits; 10619 struct mlx5_ifc_fpga_cap_bits fpga_cap_bits; 10620 struct mlx5_ifc_mcqi_reg_bits mcqi_reg; 10621 struct mlx5_ifc_mcc_reg_bits mcc_reg; 10622 struct mlx5_ifc_mcda_reg_bits mcda_reg; 10623 struct mlx5_ifc_mirc_reg_bits mirc_reg; 10624 struct mlx5_ifc_mfrl_reg_bits mfrl_reg; 10625 struct mlx5_ifc_mtutc_reg_bits mtutc_reg; 10626 struct mlx5_ifc_mrtc_reg_bits mrtc_reg; 10627 u8 reserved_at_0[0x60e0]; 10628 }; 10629 10630 union mlx5_ifc_debug_enhancements_document_bits { 10631 struct mlx5_ifc_health_buffer_bits health_buffer; 10632 u8 reserved_at_0[0x200]; 10633 }; 10634 10635 union mlx5_ifc_uplink_pci_interface_document_bits { 10636 struct mlx5_ifc_initial_seg_bits initial_seg; 10637 u8 reserved_at_0[0x20060]; 10638 }; 10639 10640 struct mlx5_ifc_set_flow_table_root_out_bits { 10641 u8 status[0x8]; 10642 u8 reserved_at_8[0x18]; 10643 10644 u8 syndrome[0x20]; 10645 10646 u8 reserved_at_40[0x40]; 10647 }; 10648 10649 struct mlx5_ifc_set_flow_table_root_in_bits { 10650 u8 opcode[0x10]; 10651 u8 reserved_at_10[0x10]; 10652 10653 u8 reserved_at_20[0x10]; 10654 u8 op_mod[0x10]; 10655 10656 u8 other_vport[0x1]; 10657 u8 reserved_at_41[0xf]; 10658 u8 vport_number[0x10]; 10659 10660 u8 reserved_at_60[0x20]; 10661 10662 u8 table_type[0x8]; 10663 u8 reserved_at_88[0x7]; 10664 u8 table_of_other_vport[0x1]; 10665 u8 table_vport_number[0x10]; 10666 10667 u8 reserved_at_a0[0x8]; 10668 u8 table_id[0x18]; 10669 10670 u8 reserved_at_c0[0x8]; 10671 u8 underlay_qpn[0x18]; 10672 u8 table_eswitch_owner_vhca_id_valid[0x1]; 10673 u8 reserved_at_e1[0xf]; 10674 u8 table_eswitch_owner_vhca_id[0x10]; 10675 u8 reserved_at_100[0x100]; 10676 }; 10677 10678 enum { 10679 MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = (1UL << 0), 10680 MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15), 10681 }; 10682 10683 struct mlx5_ifc_modify_flow_table_out_bits { 10684 u8 status[0x8]; 10685 u8 reserved_at_8[0x18]; 10686 10687 u8 syndrome[0x20]; 10688 10689 u8 reserved_at_40[0x40]; 10690 }; 10691 10692 struct mlx5_ifc_modify_flow_table_in_bits { 10693 u8 opcode[0x10]; 10694 u8 reserved_at_10[0x10]; 10695 10696 u8 reserved_at_20[0x10]; 10697 u8 op_mod[0x10]; 10698 10699 u8 other_vport[0x1]; 10700 u8 reserved_at_41[0xf]; 10701 u8 vport_number[0x10]; 10702 10703 u8 reserved_at_60[0x10]; 10704 u8 modify_field_select[0x10]; 10705 10706 u8 table_type[0x8]; 10707 u8 reserved_at_88[0x18]; 10708 10709 u8 reserved_at_a0[0x8]; 10710 u8 table_id[0x18]; 10711 10712 struct mlx5_ifc_flow_table_context_bits flow_table_context; 10713 }; 10714 10715 struct mlx5_ifc_ets_tcn_config_reg_bits { 10716 u8 g[0x1]; 10717 u8 b[0x1]; 10718 u8 r[0x1]; 10719 u8 reserved_at_3[0x9]; 10720 u8 group[0x4]; 10721 u8 reserved_at_10[0x9]; 10722 u8 bw_allocation[0x7]; 10723 10724 u8 reserved_at_20[0xc]; 10725 u8 max_bw_units[0x4]; 10726 u8 reserved_at_30[0x8]; 10727 u8 max_bw_value[0x8]; 10728 }; 10729 10730 struct mlx5_ifc_ets_global_config_reg_bits { 10731 u8 reserved_at_0[0x2]; 10732 u8 r[0x1]; 10733 u8 reserved_at_3[0x1d]; 10734 10735 u8 reserved_at_20[0xc]; 10736 u8 max_bw_units[0x4]; 10737 u8 reserved_at_30[0x8]; 10738 u8 max_bw_value[0x8]; 10739 }; 10740 10741 struct mlx5_ifc_qetc_reg_bits { 10742 u8 reserved_at_0[0x8]; 10743 u8 port_number[0x8]; 10744 u8 reserved_at_10[0x30]; 10745 10746 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8]; 10747 struct mlx5_ifc_ets_global_config_reg_bits global_configuration; 10748 }; 10749 10750 struct mlx5_ifc_qpdpm_dscp_reg_bits { 10751 u8 e[0x1]; 10752 u8 reserved_at_01[0x0b]; 10753 u8 prio[0x04]; 10754 }; 10755 10756 struct mlx5_ifc_qpdpm_reg_bits { 10757 u8 reserved_at_0[0x8]; 10758 u8 local_port[0x8]; 10759 u8 reserved_at_10[0x10]; 10760 struct mlx5_ifc_qpdpm_dscp_reg_bits dscp[64]; 10761 }; 10762 10763 struct mlx5_ifc_qpts_reg_bits { 10764 u8 reserved_at_0[0x8]; 10765 u8 local_port[0x8]; 10766 u8 reserved_at_10[0x2d]; 10767 u8 trust_state[0x3]; 10768 }; 10769 10770 struct mlx5_ifc_pptb_reg_bits { 10771 u8 reserved_at_0[0x2]; 10772 u8 mm[0x2]; 10773 u8 reserved_at_4[0x4]; 10774 u8 local_port[0x8]; 10775 u8 reserved_at_10[0x6]; 10776 u8 cm[0x1]; 10777 u8 um[0x1]; 10778 u8 pm[0x8]; 10779 10780 u8 prio_x_buff[0x20]; 10781 10782 u8 pm_msb[0x8]; 10783 u8 reserved_at_48[0x10]; 10784 u8 ctrl_buff[0x4]; 10785 u8 untagged_buff[0x4]; 10786 }; 10787 10788 struct mlx5_ifc_sbcam_reg_bits { 10789 u8 reserved_at_0[0x8]; 10790 u8 feature_group[0x8]; 10791 u8 reserved_at_10[0x8]; 10792 u8 access_reg_group[0x8]; 10793 10794 u8 reserved_at_20[0x20]; 10795 10796 u8 sb_access_reg_cap_mask[4][0x20]; 10797 10798 u8 reserved_at_c0[0x80]; 10799 10800 u8 sb_feature_cap_mask[4][0x20]; 10801 10802 u8 reserved_at_1c0[0x40]; 10803 10804 u8 cap_total_buffer_size[0x20]; 10805 10806 u8 cap_cell_size[0x10]; 10807 u8 cap_max_pg_buffers[0x8]; 10808 u8 cap_num_pool_supported[0x8]; 10809 10810 u8 reserved_at_240[0x8]; 10811 u8 cap_sbsr_stat_size[0x8]; 10812 u8 cap_max_tclass_data[0x8]; 10813 u8 cap_max_cpu_ingress_tclass_sb[0x8]; 10814 }; 10815 10816 struct mlx5_ifc_pbmc_reg_bits { 10817 u8 reserved_at_0[0x8]; 10818 u8 local_port[0x8]; 10819 u8 reserved_at_10[0x10]; 10820 10821 u8 xoff_timer_value[0x10]; 10822 u8 xoff_refresh[0x10]; 10823 10824 u8 reserved_at_40[0x9]; 10825 u8 fullness_threshold[0x7]; 10826 u8 port_buffer_size[0x10]; 10827 10828 struct mlx5_ifc_bufferx_reg_bits buffer[10]; 10829 10830 u8 reserved_at_2e0[0x80]; 10831 }; 10832 10833 struct mlx5_ifc_qtct_reg_bits { 10834 u8 reserved_at_0[0x8]; 10835 u8 port_number[0x8]; 10836 u8 reserved_at_10[0xd]; 10837 u8 prio[0x3]; 10838 10839 u8 reserved_at_20[0x1d]; 10840 u8 tclass[0x3]; 10841 }; 10842 10843 struct mlx5_ifc_mcia_reg_bits { 10844 u8 l[0x1]; 10845 u8 reserved_at_1[0x7]; 10846 u8 module[0x8]; 10847 u8 reserved_at_10[0x8]; 10848 u8 status[0x8]; 10849 10850 u8 i2c_device_address[0x8]; 10851 u8 page_number[0x8]; 10852 u8 device_address[0x10]; 10853 10854 u8 reserved_at_40[0x10]; 10855 u8 size[0x10]; 10856 10857 u8 reserved_at_60[0x20]; 10858 10859 u8 dword_0[0x20]; 10860 u8 dword_1[0x20]; 10861 u8 dword_2[0x20]; 10862 u8 dword_3[0x20]; 10863 u8 dword_4[0x20]; 10864 u8 dword_5[0x20]; 10865 u8 dword_6[0x20]; 10866 u8 dword_7[0x20]; 10867 u8 dword_8[0x20]; 10868 u8 dword_9[0x20]; 10869 u8 dword_10[0x20]; 10870 u8 dword_11[0x20]; 10871 }; 10872 10873 struct mlx5_ifc_dcbx_param_bits { 10874 u8 dcbx_cee_cap[0x1]; 10875 u8 dcbx_ieee_cap[0x1]; 10876 u8 dcbx_standby_cap[0x1]; 10877 u8 reserved_at_3[0x5]; 10878 u8 port_number[0x8]; 10879 u8 reserved_at_10[0xa]; 10880 u8 max_application_table_size[6]; 10881 u8 reserved_at_20[0x15]; 10882 u8 version_oper[0x3]; 10883 u8 reserved_at_38[5]; 10884 u8 version_admin[0x3]; 10885 u8 willing_admin[0x1]; 10886 u8 reserved_at_41[0x3]; 10887 u8 pfc_cap_oper[0x4]; 10888 u8 reserved_at_48[0x4]; 10889 u8 pfc_cap_admin[0x4]; 10890 u8 reserved_at_50[0x4]; 10891 u8 num_of_tc_oper[0x4]; 10892 u8 reserved_at_58[0x4]; 10893 u8 num_of_tc_admin[0x4]; 10894 u8 remote_willing[0x1]; 10895 u8 reserved_at_61[3]; 10896 u8 remote_pfc_cap[4]; 10897 u8 reserved_at_68[0x14]; 10898 u8 remote_num_of_tc[0x4]; 10899 u8 reserved_at_80[0x18]; 10900 u8 error[0x8]; 10901 u8 reserved_at_a0[0x160]; 10902 }; 10903 10904 enum { 10905 MLX5_LAG_PORT_SELECT_MODE_QUEUE_AFFINITY = 0, 10906 MLX5_LAG_PORT_SELECT_MODE_PORT_SELECT_FT = 1, 10907 MLX5_LAG_PORT_SELECT_MODE_PORT_SELECT_MPESW = 2, 10908 }; 10909 10910 struct mlx5_ifc_lagc_bits { 10911 u8 fdb_selection_mode[0x1]; 10912 u8 reserved_at_1[0x14]; 10913 u8 port_select_mode[0x3]; 10914 u8 reserved_at_18[0x5]; 10915 u8 lag_state[0x3]; 10916 10917 u8 reserved_at_20[0x14]; 10918 u8 tx_remap_affinity_2[0x4]; 10919 u8 reserved_at_38[0x4]; 10920 u8 tx_remap_affinity_1[0x4]; 10921 }; 10922 10923 struct mlx5_ifc_create_lag_out_bits { 10924 u8 status[0x8]; 10925 u8 reserved_at_8[0x18]; 10926 10927 u8 syndrome[0x20]; 10928 10929 u8 reserved_at_40[0x40]; 10930 }; 10931 10932 struct mlx5_ifc_create_lag_in_bits { 10933 u8 opcode[0x10]; 10934 u8 reserved_at_10[0x10]; 10935 10936 u8 reserved_at_20[0x10]; 10937 u8 op_mod[0x10]; 10938 10939 struct mlx5_ifc_lagc_bits ctx; 10940 }; 10941 10942 struct mlx5_ifc_modify_lag_out_bits { 10943 u8 status[0x8]; 10944 u8 reserved_at_8[0x18]; 10945 10946 u8 syndrome[0x20]; 10947 10948 u8 reserved_at_40[0x40]; 10949 }; 10950 10951 struct mlx5_ifc_modify_lag_in_bits { 10952 u8 opcode[0x10]; 10953 u8 reserved_at_10[0x10]; 10954 10955 u8 reserved_at_20[0x10]; 10956 u8 op_mod[0x10]; 10957 10958 u8 reserved_at_40[0x20]; 10959 u8 field_select[0x20]; 10960 10961 struct mlx5_ifc_lagc_bits ctx; 10962 }; 10963 10964 struct mlx5_ifc_query_lag_out_bits { 10965 u8 status[0x8]; 10966 u8 reserved_at_8[0x18]; 10967 10968 u8 syndrome[0x20]; 10969 10970 struct mlx5_ifc_lagc_bits ctx; 10971 }; 10972 10973 struct mlx5_ifc_query_lag_in_bits { 10974 u8 opcode[0x10]; 10975 u8 reserved_at_10[0x10]; 10976 10977 u8 reserved_at_20[0x10]; 10978 u8 op_mod[0x10]; 10979 10980 u8 reserved_at_40[0x40]; 10981 }; 10982 10983 struct mlx5_ifc_destroy_lag_out_bits { 10984 u8 status[0x8]; 10985 u8 reserved_at_8[0x18]; 10986 10987 u8 syndrome[0x20]; 10988 10989 u8 reserved_at_40[0x40]; 10990 }; 10991 10992 struct mlx5_ifc_destroy_lag_in_bits { 10993 u8 opcode[0x10]; 10994 u8 reserved_at_10[0x10]; 10995 10996 u8 reserved_at_20[0x10]; 10997 u8 op_mod[0x10]; 10998 10999 u8 reserved_at_40[0x40]; 11000 }; 11001 11002 struct mlx5_ifc_create_vport_lag_out_bits { 11003 u8 status[0x8]; 11004 u8 reserved_at_8[0x18]; 11005 11006 u8 syndrome[0x20]; 11007 11008 u8 reserved_at_40[0x40]; 11009 }; 11010 11011 struct mlx5_ifc_create_vport_lag_in_bits { 11012 u8 opcode[0x10]; 11013 u8 reserved_at_10[0x10]; 11014 11015 u8 reserved_at_20[0x10]; 11016 u8 op_mod[0x10]; 11017 11018 u8 reserved_at_40[0x40]; 11019 }; 11020 11021 struct mlx5_ifc_destroy_vport_lag_out_bits { 11022 u8 status[0x8]; 11023 u8 reserved_at_8[0x18]; 11024 11025 u8 syndrome[0x20]; 11026 11027 u8 reserved_at_40[0x40]; 11028 }; 11029 11030 struct mlx5_ifc_destroy_vport_lag_in_bits { 11031 u8 opcode[0x10]; 11032 u8 reserved_at_10[0x10]; 11033 11034 u8 reserved_at_20[0x10]; 11035 u8 op_mod[0x10]; 11036 11037 u8 reserved_at_40[0x40]; 11038 }; 11039 11040 enum { 11041 MLX5_MODIFY_MEMIC_OP_MOD_ALLOC, 11042 MLX5_MODIFY_MEMIC_OP_MOD_DEALLOC, 11043 }; 11044 11045 struct mlx5_ifc_modify_memic_in_bits { 11046 u8 opcode[0x10]; 11047 u8 uid[0x10]; 11048 11049 u8 reserved_at_20[0x10]; 11050 u8 op_mod[0x10]; 11051 11052 u8 reserved_at_40[0x20]; 11053 11054 u8 reserved_at_60[0x18]; 11055 u8 memic_operation_type[0x8]; 11056 11057 u8 memic_start_addr[0x40]; 11058 11059 u8 reserved_at_c0[0x140]; 11060 }; 11061 11062 struct mlx5_ifc_modify_memic_out_bits { 11063 u8 status[0x8]; 11064 u8 reserved_at_8[0x18]; 11065 11066 u8 syndrome[0x20]; 11067 11068 u8 reserved_at_40[0x40]; 11069 11070 u8 memic_operation_addr[0x40]; 11071 11072 u8 reserved_at_c0[0x140]; 11073 }; 11074 11075 struct mlx5_ifc_alloc_memic_in_bits { 11076 u8 opcode[0x10]; 11077 u8 reserved_at_10[0x10]; 11078 11079 u8 reserved_at_20[0x10]; 11080 u8 op_mod[0x10]; 11081 11082 u8 reserved_at_30[0x20]; 11083 11084 u8 reserved_at_40[0x18]; 11085 u8 log_memic_addr_alignment[0x8]; 11086 11087 u8 range_start_addr[0x40]; 11088 11089 u8 range_size[0x20]; 11090 11091 u8 memic_size[0x20]; 11092 }; 11093 11094 struct mlx5_ifc_alloc_memic_out_bits { 11095 u8 status[0x8]; 11096 u8 reserved_at_8[0x18]; 11097 11098 u8 syndrome[0x20]; 11099 11100 u8 memic_start_addr[0x40]; 11101 }; 11102 11103 struct mlx5_ifc_dealloc_memic_in_bits { 11104 u8 opcode[0x10]; 11105 u8 reserved_at_10[0x10]; 11106 11107 u8 reserved_at_20[0x10]; 11108 u8 op_mod[0x10]; 11109 11110 u8 reserved_at_40[0x40]; 11111 11112 u8 memic_start_addr[0x40]; 11113 11114 u8 memic_size[0x20]; 11115 11116 u8 reserved_at_e0[0x20]; 11117 }; 11118 11119 struct mlx5_ifc_dealloc_memic_out_bits { 11120 u8 status[0x8]; 11121 u8 reserved_at_8[0x18]; 11122 11123 u8 syndrome[0x20]; 11124 11125 u8 reserved_at_40[0x40]; 11126 }; 11127 11128 struct mlx5_ifc_umem_bits { 11129 u8 reserved_at_0[0x80]; 11130 11131 u8 reserved_at_80[0x1b]; 11132 u8 log_page_size[0x5]; 11133 11134 u8 page_offset[0x20]; 11135 11136 u8 num_of_mtt[0x40]; 11137 11138 struct mlx5_ifc_mtt_bits mtt[]; 11139 }; 11140 11141 struct mlx5_ifc_uctx_bits { 11142 u8 cap[0x20]; 11143 11144 u8 reserved_at_20[0x160]; 11145 }; 11146 11147 struct mlx5_ifc_sw_icm_bits { 11148 u8 modify_field_select[0x40]; 11149 11150 u8 reserved_at_40[0x18]; 11151 u8 log_sw_icm_size[0x8]; 11152 11153 u8 reserved_at_60[0x20]; 11154 11155 u8 sw_icm_start_addr[0x40]; 11156 11157 u8 reserved_at_c0[0x140]; 11158 }; 11159 11160 struct mlx5_ifc_geneve_tlv_option_bits { 11161 u8 modify_field_select[0x40]; 11162 11163 u8 reserved_at_40[0x18]; 11164 u8 geneve_option_fte_index[0x8]; 11165 11166 u8 option_class[0x10]; 11167 u8 option_type[0x8]; 11168 u8 reserved_at_78[0x3]; 11169 u8 option_data_length[0x5]; 11170 11171 u8 reserved_at_80[0x180]; 11172 }; 11173 11174 struct mlx5_ifc_create_umem_in_bits { 11175 u8 opcode[0x10]; 11176 u8 uid[0x10]; 11177 11178 u8 reserved_at_20[0x10]; 11179 u8 op_mod[0x10]; 11180 11181 u8 reserved_at_40[0x40]; 11182 11183 struct mlx5_ifc_umem_bits umem; 11184 }; 11185 11186 struct mlx5_ifc_create_umem_out_bits { 11187 u8 status[0x8]; 11188 u8 reserved_at_8[0x18]; 11189 11190 u8 syndrome[0x20]; 11191 11192 u8 reserved_at_40[0x8]; 11193 u8 umem_id[0x18]; 11194 11195 u8 reserved_at_60[0x20]; 11196 }; 11197 11198 struct mlx5_ifc_destroy_umem_in_bits { 11199 u8 opcode[0x10]; 11200 u8 uid[0x10]; 11201 11202 u8 reserved_at_20[0x10]; 11203 u8 op_mod[0x10]; 11204 11205 u8 reserved_at_40[0x8]; 11206 u8 umem_id[0x18]; 11207 11208 u8 reserved_at_60[0x20]; 11209 }; 11210 11211 struct mlx5_ifc_destroy_umem_out_bits { 11212 u8 status[0x8]; 11213 u8 reserved_at_8[0x18]; 11214 11215 u8 syndrome[0x20]; 11216 11217 u8 reserved_at_40[0x40]; 11218 }; 11219 11220 struct mlx5_ifc_create_uctx_in_bits { 11221 u8 opcode[0x10]; 11222 u8 reserved_at_10[0x10]; 11223 11224 u8 reserved_at_20[0x10]; 11225 u8 op_mod[0x10]; 11226 11227 u8 reserved_at_40[0x40]; 11228 11229 struct mlx5_ifc_uctx_bits uctx; 11230 }; 11231 11232 struct mlx5_ifc_create_uctx_out_bits { 11233 u8 status[0x8]; 11234 u8 reserved_at_8[0x18]; 11235 11236 u8 syndrome[0x20]; 11237 11238 u8 reserved_at_40[0x10]; 11239 u8 uid[0x10]; 11240 11241 u8 reserved_at_60[0x20]; 11242 }; 11243 11244 struct mlx5_ifc_destroy_uctx_in_bits { 11245 u8 opcode[0x10]; 11246 u8 reserved_at_10[0x10]; 11247 11248 u8 reserved_at_20[0x10]; 11249 u8 op_mod[0x10]; 11250 11251 u8 reserved_at_40[0x10]; 11252 u8 uid[0x10]; 11253 11254 u8 reserved_at_60[0x20]; 11255 }; 11256 11257 struct mlx5_ifc_destroy_uctx_out_bits { 11258 u8 status[0x8]; 11259 u8 reserved_at_8[0x18]; 11260 11261 u8 syndrome[0x20]; 11262 11263 u8 reserved_at_40[0x40]; 11264 }; 11265 11266 struct mlx5_ifc_create_sw_icm_in_bits { 11267 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 11268 struct mlx5_ifc_sw_icm_bits sw_icm; 11269 }; 11270 11271 struct mlx5_ifc_create_geneve_tlv_option_in_bits { 11272 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 11273 struct mlx5_ifc_geneve_tlv_option_bits geneve_tlv_opt; 11274 }; 11275 11276 struct mlx5_ifc_mtrc_string_db_param_bits { 11277 u8 string_db_base_address[0x20]; 11278 11279 u8 reserved_at_20[0x8]; 11280 u8 string_db_size[0x18]; 11281 }; 11282 11283 struct mlx5_ifc_mtrc_cap_bits { 11284 u8 trace_owner[0x1]; 11285 u8 trace_to_memory[0x1]; 11286 u8 reserved_at_2[0x4]; 11287 u8 trc_ver[0x2]; 11288 u8 reserved_at_8[0x14]; 11289 u8 num_string_db[0x4]; 11290 11291 u8 first_string_trace[0x8]; 11292 u8 num_string_trace[0x8]; 11293 u8 reserved_at_30[0x28]; 11294 11295 u8 log_max_trace_buffer_size[0x8]; 11296 11297 u8 reserved_at_60[0x20]; 11298 11299 struct mlx5_ifc_mtrc_string_db_param_bits string_db_param[8]; 11300 11301 u8 reserved_at_280[0x180]; 11302 }; 11303 11304 struct mlx5_ifc_mtrc_conf_bits { 11305 u8 reserved_at_0[0x1c]; 11306 u8 trace_mode[0x4]; 11307 u8 reserved_at_20[0x18]; 11308 u8 log_trace_buffer_size[0x8]; 11309 u8 trace_mkey[0x20]; 11310 u8 reserved_at_60[0x3a0]; 11311 }; 11312 11313 struct mlx5_ifc_mtrc_stdb_bits { 11314 u8 string_db_index[0x4]; 11315 u8 reserved_at_4[0x4]; 11316 u8 read_size[0x18]; 11317 u8 start_offset[0x20]; 11318 u8 string_db_data[]; 11319 }; 11320 11321 struct mlx5_ifc_mtrc_ctrl_bits { 11322 u8 trace_status[0x2]; 11323 u8 reserved_at_2[0x2]; 11324 u8 arm_event[0x1]; 11325 u8 reserved_at_5[0xb]; 11326 u8 modify_field_select[0x10]; 11327 u8 reserved_at_20[0x2b]; 11328 u8 current_timestamp52_32[0x15]; 11329 u8 current_timestamp31_0[0x20]; 11330 u8 reserved_at_80[0x180]; 11331 }; 11332 11333 struct mlx5_ifc_host_params_context_bits { 11334 u8 host_number[0x8]; 11335 u8 reserved_at_8[0x7]; 11336 u8 host_pf_disabled[0x1]; 11337 u8 host_num_of_vfs[0x10]; 11338 11339 u8 host_total_vfs[0x10]; 11340 u8 host_pci_bus[0x10]; 11341 11342 u8 reserved_at_40[0x10]; 11343 u8 host_pci_device[0x10]; 11344 11345 u8 reserved_at_60[0x10]; 11346 u8 host_pci_function[0x10]; 11347 11348 u8 reserved_at_80[0x180]; 11349 }; 11350 11351 struct mlx5_ifc_query_esw_functions_in_bits { 11352 u8 opcode[0x10]; 11353 u8 reserved_at_10[0x10]; 11354 11355 u8 reserved_at_20[0x10]; 11356 u8 op_mod[0x10]; 11357 11358 u8 reserved_at_40[0x40]; 11359 }; 11360 11361 struct mlx5_ifc_query_esw_functions_out_bits { 11362 u8 status[0x8]; 11363 u8 reserved_at_8[0x18]; 11364 11365 u8 syndrome[0x20]; 11366 11367 u8 reserved_at_40[0x40]; 11368 11369 struct mlx5_ifc_host_params_context_bits host_params_context; 11370 11371 u8 reserved_at_280[0x180]; 11372 u8 host_sf_enable[][0x40]; 11373 }; 11374 11375 struct mlx5_ifc_sf_partition_bits { 11376 u8 reserved_at_0[0x10]; 11377 u8 log_num_sf[0x8]; 11378 u8 log_sf_bar_size[0x8]; 11379 }; 11380 11381 struct mlx5_ifc_query_sf_partitions_out_bits { 11382 u8 status[0x8]; 11383 u8 reserved_at_8[0x18]; 11384 11385 u8 syndrome[0x20]; 11386 11387 u8 reserved_at_40[0x18]; 11388 u8 num_sf_partitions[0x8]; 11389 11390 u8 reserved_at_60[0x20]; 11391 11392 struct mlx5_ifc_sf_partition_bits sf_partition[]; 11393 }; 11394 11395 struct mlx5_ifc_query_sf_partitions_in_bits { 11396 u8 opcode[0x10]; 11397 u8 reserved_at_10[0x10]; 11398 11399 u8 reserved_at_20[0x10]; 11400 u8 op_mod[0x10]; 11401 11402 u8 reserved_at_40[0x40]; 11403 }; 11404 11405 struct mlx5_ifc_dealloc_sf_out_bits { 11406 u8 status[0x8]; 11407 u8 reserved_at_8[0x18]; 11408 11409 u8 syndrome[0x20]; 11410 11411 u8 reserved_at_40[0x40]; 11412 }; 11413 11414 struct mlx5_ifc_dealloc_sf_in_bits { 11415 u8 opcode[0x10]; 11416 u8 reserved_at_10[0x10]; 11417 11418 u8 reserved_at_20[0x10]; 11419 u8 op_mod[0x10]; 11420 11421 u8 reserved_at_40[0x10]; 11422 u8 function_id[0x10]; 11423 11424 u8 reserved_at_60[0x20]; 11425 }; 11426 11427 struct mlx5_ifc_alloc_sf_out_bits { 11428 u8 status[0x8]; 11429 u8 reserved_at_8[0x18]; 11430 11431 u8 syndrome[0x20]; 11432 11433 u8 reserved_at_40[0x40]; 11434 }; 11435 11436 struct mlx5_ifc_alloc_sf_in_bits { 11437 u8 opcode[0x10]; 11438 u8 reserved_at_10[0x10]; 11439 11440 u8 reserved_at_20[0x10]; 11441 u8 op_mod[0x10]; 11442 11443 u8 reserved_at_40[0x10]; 11444 u8 function_id[0x10]; 11445 11446 u8 reserved_at_60[0x20]; 11447 }; 11448 11449 struct mlx5_ifc_affiliated_event_header_bits { 11450 u8 reserved_at_0[0x10]; 11451 u8 obj_type[0x10]; 11452 11453 u8 obj_id[0x20]; 11454 }; 11455 11456 enum { 11457 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = BIT_ULL(0xc), 11458 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_IPSEC = BIT_ULL(0x13), 11459 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_SAMPLER = BIT_ULL(0x20), 11460 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_FLOW_METER_ASO = BIT_ULL(0x24), 11461 }; 11462 11463 enum { 11464 MLX5_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = 0xc, 11465 MLX5_GENERAL_OBJECT_TYPES_IPSEC = 0x13, 11466 MLX5_GENERAL_OBJECT_TYPES_SAMPLER = 0x20, 11467 MLX5_GENERAL_OBJECT_TYPES_FLOW_METER_ASO = 0x24, 11468 }; 11469 11470 enum { 11471 MLX5_IPSEC_OBJECT_ICV_LEN_16B, 11472 }; 11473 11474 struct mlx5_ifc_ipsec_obj_bits { 11475 u8 modify_field_select[0x40]; 11476 u8 full_offload[0x1]; 11477 u8 reserved_at_41[0x1]; 11478 u8 esn_en[0x1]; 11479 u8 esn_overlap[0x1]; 11480 u8 reserved_at_44[0x2]; 11481 u8 icv_length[0x2]; 11482 u8 reserved_at_48[0x4]; 11483 u8 aso_return_reg[0x4]; 11484 u8 reserved_at_50[0x10]; 11485 11486 u8 esn_msb[0x20]; 11487 11488 u8 reserved_at_80[0x8]; 11489 u8 dekn[0x18]; 11490 11491 u8 salt[0x20]; 11492 11493 u8 implicit_iv[0x40]; 11494 11495 u8 reserved_at_100[0x700]; 11496 }; 11497 11498 struct mlx5_ifc_create_ipsec_obj_in_bits { 11499 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 11500 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 11501 }; 11502 11503 enum { 11504 MLX5_MODIFY_IPSEC_BITMASK_ESN_OVERLAP = BIT(0), 11505 MLX5_MODIFY_IPSEC_BITMASK_ESN_MSB = BIT(1), 11506 }; 11507 11508 struct mlx5_ifc_query_ipsec_obj_out_bits { 11509 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 11510 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 11511 }; 11512 11513 struct mlx5_ifc_modify_ipsec_obj_in_bits { 11514 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 11515 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 11516 }; 11517 11518 struct mlx5_ifc_encryption_key_obj_bits { 11519 u8 modify_field_select[0x40]; 11520 11521 u8 reserved_at_40[0x14]; 11522 u8 key_size[0x4]; 11523 u8 reserved_at_58[0x4]; 11524 u8 key_type[0x4]; 11525 11526 u8 reserved_at_60[0x8]; 11527 u8 pd[0x18]; 11528 11529 u8 reserved_at_80[0x180]; 11530 u8 key[8][0x20]; 11531 11532 u8 reserved_at_300[0x500]; 11533 }; 11534 11535 struct mlx5_ifc_create_encryption_key_in_bits { 11536 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 11537 struct mlx5_ifc_encryption_key_obj_bits encryption_key_object; 11538 }; 11539 11540 enum { 11541 MLX5_FLOW_METER_MODE_BYTES_IP_LENGTH = 0x0, 11542 MLX5_FLOW_METER_MODE_BYTES_CALC_WITH_L2 = 0x1, 11543 MLX5_FLOW_METER_MODE_BYTES_CALC_WITH_L2_IPG = 0x2, 11544 MLX5_FLOW_METER_MODE_NUM_PACKETS = 0x3, 11545 }; 11546 11547 struct mlx5_ifc_flow_meter_parameters_bits { 11548 u8 valid[0x1]; 11549 u8 bucket_overflow[0x1]; 11550 u8 start_color[0x2]; 11551 u8 both_buckets_on_green[0x1]; 11552 u8 reserved_at_5[0x1]; 11553 u8 meter_mode[0x2]; 11554 u8 reserved_at_8[0x18]; 11555 11556 u8 reserved_at_20[0x20]; 11557 11558 u8 reserved_at_40[0x3]; 11559 u8 cbs_exponent[0x5]; 11560 u8 cbs_mantissa[0x8]; 11561 u8 reserved_at_50[0x3]; 11562 u8 cir_exponent[0x5]; 11563 u8 cir_mantissa[0x8]; 11564 11565 u8 reserved_at_60[0x20]; 11566 11567 u8 reserved_at_80[0x3]; 11568 u8 ebs_exponent[0x5]; 11569 u8 ebs_mantissa[0x8]; 11570 u8 reserved_at_90[0x3]; 11571 u8 eir_exponent[0x5]; 11572 u8 eir_mantissa[0x8]; 11573 11574 u8 reserved_at_a0[0x60]; 11575 }; 11576 11577 struct mlx5_ifc_flow_meter_aso_obj_bits { 11578 u8 modify_field_select[0x40]; 11579 11580 u8 reserved_at_40[0x40]; 11581 11582 u8 reserved_at_80[0x8]; 11583 u8 meter_aso_access_pd[0x18]; 11584 11585 u8 reserved_at_a0[0x160]; 11586 11587 struct mlx5_ifc_flow_meter_parameters_bits flow_meter_parameters[2]; 11588 }; 11589 11590 struct mlx5_ifc_create_flow_meter_aso_obj_in_bits { 11591 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 11592 struct mlx5_ifc_flow_meter_aso_obj_bits flow_meter_aso_obj; 11593 }; 11594 11595 struct mlx5_ifc_sampler_obj_bits { 11596 u8 modify_field_select[0x40]; 11597 11598 u8 table_type[0x8]; 11599 u8 level[0x8]; 11600 u8 reserved_at_50[0xf]; 11601 u8 ignore_flow_level[0x1]; 11602 11603 u8 sample_ratio[0x20]; 11604 11605 u8 reserved_at_80[0x8]; 11606 u8 sample_table_id[0x18]; 11607 11608 u8 reserved_at_a0[0x8]; 11609 u8 default_table_id[0x18]; 11610 11611 u8 sw_steering_icm_address_rx[0x40]; 11612 u8 sw_steering_icm_address_tx[0x40]; 11613 11614 u8 reserved_at_140[0xa0]; 11615 }; 11616 11617 struct mlx5_ifc_create_sampler_obj_in_bits { 11618 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 11619 struct mlx5_ifc_sampler_obj_bits sampler_object; 11620 }; 11621 11622 struct mlx5_ifc_query_sampler_obj_out_bits { 11623 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 11624 struct mlx5_ifc_sampler_obj_bits sampler_object; 11625 }; 11626 11627 enum { 11628 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_128 = 0x0, 11629 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_256 = 0x1, 11630 }; 11631 11632 enum { 11633 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_TYPE_TLS = 0x1, 11634 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_TYPE_IPSEC = 0x2, 11635 }; 11636 11637 struct mlx5_ifc_tls_static_params_bits { 11638 u8 const_2[0x2]; 11639 u8 tls_version[0x4]; 11640 u8 const_1[0x2]; 11641 u8 reserved_at_8[0x14]; 11642 u8 encryption_standard[0x4]; 11643 11644 u8 reserved_at_20[0x20]; 11645 11646 u8 initial_record_number[0x40]; 11647 11648 u8 resync_tcp_sn[0x20]; 11649 11650 u8 gcm_iv[0x20]; 11651 11652 u8 implicit_iv[0x40]; 11653 11654 u8 reserved_at_100[0x8]; 11655 u8 dek_index[0x18]; 11656 11657 u8 reserved_at_120[0xe0]; 11658 }; 11659 11660 struct mlx5_ifc_tls_progress_params_bits { 11661 u8 next_record_tcp_sn[0x20]; 11662 11663 u8 hw_resync_tcp_sn[0x20]; 11664 11665 u8 record_tracker_state[0x2]; 11666 u8 auth_state[0x2]; 11667 u8 reserved_at_44[0x4]; 11668 u8 hw_offset_record_number[0x18]; 11669 }; 11670 11671 enum { 11672 MLX5_MTT_PERM_READ = 1 << 0, 11673 MLX5_MTT_PERM_WRITE = 1 << 1, 11674 MLX5_MTT_PERM_RW = MLX5_MTT_PERM_READ | MLX5_MTT_PERM_WRITE, 11675 }; 11676 11677 enum { 11678 MLX5_SUSPEND_VHCA_IN_OP_MOD_SUSPEND_INITIATOR = 0x0, 11679 MLX5_SUSPEND_VHCA_IN_OP_MOD_SUSPEND_RESPONDER = 0x1, 11680 }; 11681 11682 struct mlx5_ifc_suspend_vhca_in_bits { 11683 u8 opcode[0x10]; 11684 u8 uid[0x10]; 11685 11686 u8 reserved_at_20[0x10]; 11687 u8 op_mod[0x10]; 11688 11689 u8 reserved_at_40[0x10]; 11690 u8 vhca_id[0x10]; 11691 11692 u8 reserved_at_60[0x20]; 11693 }; 11694 11695 struct mlx5_ifc_suspend_vhca_out_bits { 11696 u8 status[0x8]; 11697 u8 reserved_at_8[0x18]; 11698 11699 u8 syndrome[0x20]; 11700 11701 u8 reserved_at_40[0x40]; 11702 }; 11703 11704 enum { 11705 MLX5_RESUME_VHCA_IN_OP_MOD_RESUME_RESPONDER = 0x0, 11706 MLX5_RESUME_VHCA_IN_OP_MOD_RESUME_INITIATOR = 0x1, 11707 }; 11708 11709 struct mlx5_ifc_resume_vhca_in_bits { 11710 u8 opcode[0x10]; 11711 u8 uid[0x10]; 11712 11713 u8 reserved_at_20[0x10]; 11714 u8 op_mod[0x10]; 11715 11716 u8 reserved_at_40[0x10]; 11717 u8 vhca_id[0x10]; 11718 11719 u8 reserved_at_60[0x20]; 11720 }; 11721 11722 struct mlx5_ifc_resume_vhca_out_bits { 11723 u8 status[0x8]; 11724 u8 reserved_at_8[0x18]; 11725 11726 u8 syndrome[0x20]; 11727 11728 u8 reserved_at_40[0x40]; 11729 }; 11730 11731 struct mlx5_ifc_query_vhca_migration_state_in_bits { 11732 u8 opcode[0x10]; 11733 u8 uid[0x10]; 11734 11735 u8 reserved_at_20[0x10]; 11736 u8 op_mod[0x10]; 11737 11738 u8 reserved_at_40[0x10]; 11739 u8 vhca_id[0x10]; 11740 11741 u8 reserved_at_60[0x20]; 11742 }; 11743 11744 struct mlx5_ifc_query_vhca_migration_state_out_bits { 11745 u8 status[0x8]; 11746 u8 reserved_at_8[0x18]; 11747 11748 u8 syndrome[0x20]; 11749 11750 u8 reserved_at_40[0x40]; 11751 11752 u8 required_umem_size[0x20]; 11753 11754 u8 reserved_at_a0[0x160]; 11755 }; 11756 11757 struct mlx5_ifc_save_vhca_state_in_bits { 11758 u8 opcode[0x10]; 11759 u8 uid[0x10]; 11760 11761 u8 reserved_at_20[0x10]; 11762 u8 op_mod[0x10]; 11763 11764 u8 reserved_at_40[0x10]; 11765 u8 vhca_id[0x10]; 11766 11767 u8 reserved_at_60[0x20]; 11768 11769 u8 va[0x40]; 11770 11771 u8 mkey[0x20]; 11772 11773 u8 size[0x20]; 11774 }; 11775 11776 struct mlx5_ifc_save_vhca_state_out_bits { 11777 u8 status[0x8]; 11778 u8 reserved_at_8[0x18]; 11779 11780 u8 syndrome[0x20]; 11781 11782 u8 actual_image_size[0x20]; 11783 11784 u8 reserved_at_60[0x20]; 11785 }; 11786 11787 struct mlx5_ifc_load_vhca_state_in_bits { 11788 u8 opcode[0x10]; 11789 u8 uid[0x10]; 11790 11791 u8 reserved_at_20[0x10]; 11792 u8 op_mod[0x10]; 11793 11794 u8 reserved_at_40[0x10]; 11795 u8 vhca_id[0x10]; 11796 11797 u8 reserved_at_60[0x20]; 11798 11799 u8 va[0x40]; 11800 11801 u8 mkey[0x20]; 11802 11803 u8 size[0x20]; 11804 }; 11805 11806 struct mlx5_ifc_load_vhca_state_out_bits { 11807 u8 status[0x8]; 11808 u8 reserved_at_8[0x18]; 11809 11810 u8 syndrome[0x20]; 11811 11812 u8 reserved_at_40[0x40]; 11813 }; 11814 11815 #endif /* MLX5_IFC_H */ 11816