1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 #ifndef MLX5_IFC_H 33 #define MLX5_IFC_H 34 35 #include "mlx5_ifc_fpga.h" 36 37 enum { 38 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0, 39 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1, 40 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2, 41 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3, 42 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13, 43 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14, 44 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c, 45 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d, 46 MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4, 47 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5, 48 MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED = 0x7, 49 MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT = 0xc, 50 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10, 51 MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR = 0x11, 52 MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR = 0x12, 53 MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR = 0x8, 54 MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE = 0x9, 55 MLX5_EVENT_TYPE_CODING_GPIO_EVENT = 0x15, 56 MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19, 57 MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a, 58 MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT = 0x1b, 59 MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT = 0x1f, 60 MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa, 61 MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb, 62 MLX5_EVENT_TYPE_CODING_FPGA_ERROR = 0x20, 63 MLX5_EVENT_TYPE_CODING_FPGA_QP_ERROR = 0x21 64 }; 65 66 enum { 67 MLX5_MODIFY_TIR_BITMASK_LRO = 0x0, 68 MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE = 0x1, 69 MLX5_MODIFY_TIR_BITMASK_HASH = 0x2, 70 MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN = 0x3 71 }; 72 73 enum { 74 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0, 75 MLX5_SET_HCA_CAP_OP_MOD_ODP = 0x2, 76 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3, 77 MLX5_SET_HCA_CAP_OP_MOD_ROCE = 0x4, 78 }; 79 80 enum { 81 MLX5_SHARED_RESOURCE_UID = 0xffff, 82 }; 83 84 enum { 85 MLX5_OBJ_TYPE_SW_ICM = 0x0008, 86 }; 87 88 enum { 89 MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM = (1ULL << MLX5_OBJ_TYPE_SW_ICM), 90 MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT = (1ULL << 11), 91 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q = (1ULL << 13), 92 }; 93 94 enum { 95 MLX5_OBJ_TYPE_GENEVE_TLV_OPT = 0x000b, 96 MLX5_OBJ_TYPE_VIRTIO_NET_Q = 0x000d, 97 MLX5_OBJ_TYPE_MKEY = 0xff01, 98 MLX5_OBJ_TYPE_QP = 0xff02, 99 MLX5_OBJ_TYPE_PSV = 0xff03, 100 MLX5_OBJ_TYPE_RMP = 0xff04, 101 MLX5_OBJ_TYPE_XRC_SRQ = 0xff05, 102 MLX5_OBJ_TYPE_RQ = 0xff06, 103 MLX5_OBJ_TYPE_SQ = 0xff07, 104 MLX5_OBJ_TYPE_TIR = 0xff08, 105 MLX5_OBJ_TYPE_TIS = 0xff09, 106 MLX5_OBJ_TYPE_DCT = 0xff0a, 107 MLX5_OBJ_TYPE_XRQ = 0xff0b, 108 MLX5_OBJ_TYPE_RQT = 0xff0e, 109 MLX5_OBJ_TYPE_FLOW_COUNTER = 0xff0f, 110 MLX5_OBJ_TYPE_CQ = 0xff10, 111 }; 112 113 enum { 114 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100, 115 MLX5_CMD_OP_QUERY_ADAPTER = 0x101, 116 MLX5_CMD_OP_INIT_HCA = 0x102, 117 MLX5_CMD_OP_TEARDOWN_HCA = 0x103, 118 MLX5_CMD_OP_ENABLE_HCA = 0x104, 119 MLX5_CMD_OP_DISABLE_HCA = 0x105, 120 MLX5_CMD_OP_QUERY_PAGES = 0x107, 121 MLX5_CMD_OP_MANAGE_PAGES = 0x108, 122 MLX5_CMD_OP_SET_HCA_CAP = 0x109, 123 MLX5_CMD_OP_QUERY_ISSI = 0x10a, 124 MLX5_CMD_OP_SET_ISSI = 0x10b, 125 MLX5_CMD_OP_SET_DRIVER_VERSION = 0x10d, 126 MLX5_CMD_OP_QUERY_SF_PARTITION = 0x111, 127 MLX5_CMD_OP_ALLOC_SF = 0x113, 128 MLX5_CMD_OP_DEALLOC_SF = 0x114, 129 MLX5_CMD_OP_CREATE_MKEY = 0x200, 130 MLX5_CMD_OP_QUERY_MKEY = 0x201, 131 MLX5_CMD_OP_DESTROY_MKEY = 0x202, 132 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203, 133 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204, 134 MLX5_CMD_OP_ALLOC_MEMIC = 0x205, 135 MLX5_CMD_OP_DEALLOC_MEMIC = 0x206, 136 MLX5_CMD_OP_CREATE_EQ = 0x301, 137 MLX5_CMD_OP_DESTROY_EQ = 0x302, 138 MLX5_CMD_OP_QUERY_EQ = 0x303, 139 MLX5_CMD_OP_GEN_EQE = 0x304, 140 MLX5_CMD_OP_CREATE_CQ = 0x400, 141 MLX5_CMD_OP_DESTROY_CQ = 0x401, 142 MLX5_CMD_OP_QUERY_CQ = 0x402, 143 MLX5_CMD_OP_MODIFY_CQ = 0x403, 144 MLX5_CMD_OP_CREATE_QP = 0x500, 145 MLX5_CMD_OP_DESTROY_QP = 0x501, 146 MLX5_CMD_OP_RST2INIT_QP = 0x502, 147 MLX5_CMD_OP_INIT2RTR_QP = 0x503, 148 MLX5_CMD_OP_RTR2RTS_QP = 0x504, 149 MLX5_CMD_OP_RTS2RTS_QP = 0x505, 150 MLX5_CMD_OP_SQERR2RTS_QP = 0x506, 151 MLX5_CMD_OP_2ERR_QP = 0x507, 152 MLX5_CMD_OP_2RST_QP = 0x50a, 153 MLX5_CMD_OP_QUERY_QP = 0x50b, 154 MLX5_CMD_OP_SQD_RTS_QP = 0x50c, 155 MLX5_CMD_OP_INIT2INIT_QP = 0x50e, 156 MLX5_CMD_OP_CREATE_PSV = 0x600, 157 MLX5_CMD_OP_DESTROY_PSV = 0x601, 158 MLX5_CMD_OP_CREATE_SRQ = 0x700, 159 MLX5_CMD_OP_DESTROY_SRQ = 0x701, 160 MLX5_CMD_OP_QUERY_SRQ = 0x702, 161 MLX5_CMD_OP_ARM_RQ = 0x703, 162 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705, 163 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706, 164 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707, 165 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708, 166 MLX5_CMD_OP_CREATE_DCT = 0x710, 167 MLX5_CMD_OP_DESTROY_DCT = 0x711, 168 MLX5_CMD_OP_DRAIN_DCT = 0x712, 169 MLX5_CMD_OP_QUERY_DCT = 0x713, 170 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714, 171 MLX5_CMD_OP_CREATE_XRQ = 0x717, 172 MLX5_CMD_OP_DESTROY_XRQ = 0x718, 173 MLX5_CMD_OP_QUERY_XRQ = 0x719, 174 MLX5_CMD_OP_ARM_XRQ = 0x71a, 175 MLX5_CMD_OP_QUERY_XRQ_DC_PARAMS_ENTRY = 0x725, 176 MLX5_CMD_OP_SET_XRQ_DC_PARAMS_ENTRY = 0x726, 177 MLX5_CMD_OP_QUERY_XRQ_ERROR_PARAMS = 0x727, 178 MLX5_CMD_OP_RELEASE_XRQ_ERROR = 0x729, 179 MLX5_CMD_OP_MODIFY_XRQ = 0x72a, 180 MLX5_CMD_OP_QUERY_ESW_FUNCTIONS = 0x740, 181 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750, 182 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751, 183 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752, 184 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753, 185 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754, 186 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755, 187 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760, 188 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761, 189 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762, 190 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763, 191 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764, 192 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765, 193 MLX5_CMD_OP_QUERY_VNIC_ENV = 0x76f, 194 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770, 195 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771, 196 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772, 197 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773, 198 MLX5_CMD_OP_SET_MONITOR_COUNTER = 0x774, 199 MLX5_CMD_OP_ARM_MONITOR_COUNTER = 0x775, 200 MLX5_CMD_OP_SET_PP_RATE_LIMIT = 0x780, 201 MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781, 202 MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT = 0x782, 203 MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT = 0x783, 204 MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT = 0x784, 205 MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT = 0x785, 206 MLX5_CMD_OP_CREATE_QOS_PARA_VPORT = 0x786, 207 MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT = 0x787, 208 MLX5_CMD_OP_ALLOC_PD = 0x800, 209 MLX5_CMD_OP_DEALLOC_PD = 0x801, 210 MLX5_CMD_OP_ALLOC_UAR = 0x802, 211 MLX5_CMD_OP_DEALLOC_UAR = 0x803, 212 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804, 213 MLX5_CMD_OP_ACCESS_REG = 0x805, 214 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806, 215 MLX5_CMD_OP_DETACH_FROM_MCG = 0x807, 216 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a, 217 MLX5_CMD_OP_MAD_IFC = 0x50d, 218 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b, 219 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c, 220 MLX5_CMD_OP_NOP = 0x80d, 221 MLX5_CMD_OP_ALLOC_XRCD = 0x80e, 222 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f, 223 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816, 224 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817, 225 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822, 226 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823, 227 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824, 228 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825, 229 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826, 230 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827, 231 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828, 232 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829, 233 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a, 234 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b, 235 MLX5_CMD_OP_SET_WOL_ROL = 0x830, 236 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831, 237 MLX5_CMD_OP_CREATE_LAG = 0x840, 238 MLX5_CMD_OP_MODIFY_LAG = 0x841, 239 MLX5_CMD_OP_QUERY_LAG = 0x842, 240 MLX5_CMD_OP_DESTROY_LAG = 0x843, 241 MLX5_CMD_OP_CREATE_VPORT_LAG = 0x844, 242 MLX5_CMD_OP_DESTROY_VPORT_LAG = 0x845, 243 MLX5_CMD_OP_CREATE_TIR = 0x900, 244 MLX5_CMD_OP_MODIFY_TIR = 0x901, 245 MLX5_CMD_OP_DESTROY_TIR = 0x902, 246 MLX5_CMD_OP_QUERY_TIR = 0x903, 247 MLX5_CMD_OP_CREATE_SQ = 0x904, 248 MLX5_CMD_OP_MODIFY_SQ = 0x905, 249 MLX5_CMD_OP_DESTROY_SQ = 0x906, 250 MLX5_CMD_OP_QUERY_SQ = 0x907, 251 MLX5_CMD_OP_CREATE_RQ = 0x908, 252 MLX5_CMD_OP_MODIFY_RQ = 0x909, 253 MLX5_CMD_OP_SET_DELAY_DROP_PARAMS = 0x910, 254 MLX5_CMD_OP_DESTROY_RQ = 0x90a, 255 MLX5_CMD_OP_QUERY_RQ = 0x90b, 256 MLX5_CMD_OP_CREATE_RMP = 0x90c, 257 MLX5_CMD_OP_MODIFY_RMP = 0x90d, 258 MLX5_CMD_OP_DESTROY_RMP = 0x90e, 259 MLX5_CMD_OP_QUERY_RMP = 0x90f, 260 MLX5_CMD_OP_CREATE_TIS = 0x912, 261 MLX5_CMD_OP_MODIFY_TIS = 0x913, 262 MLX5_CMD_OP_DESTROY_TIS = 0x914, 263 MLX5_CMD_OP_QUERY_TIS = 0x915, 264 MLX5_CMD_OP_CREATE_RQT = 0x916, 265 MLX5_CMD_OP_MODIFY_RQT = 0x917, 266 MLX5_CMD_OP_DESTROY_RQT = 0x918, 267 MLX5_CMD_OP_QUERY_RQT = 0x919, 268 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f, 269 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930, 270 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931, 271 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932, 272 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933, 273 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934, 274 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935, 275 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936, 276 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937, 277 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938, 278 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939, 279 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a, 280 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b, 281 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c, 282 MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT = 0x93d, 283 MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT = 0x93e, 284 MLX5_CMD_OP_QUERY_PACKET_REFORMAT_CONTEXT = 0x93f, 285 MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT = 0x940, 286 MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941, 287 MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT = 0x942, 288 MLX5_CMD_OP_FPGA_CREATE_QP = 0x960, 289 MLX5_CMD_OP_FPGA_MODIFY_QP = 0x961, 290 MLX5_CMD_OP_FPGA_QUERY_QP = 0x962, 291 MLX5_CMD_OP_FPGA_DESTROY_QP = 0x963, 292 MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS = 0x964, 293 MLX5_CMD_OP_CREATE_GENERAL_OBJECT = 0xa00, 294 MLX5_CMD_OP_MODIFY_GENERAL_OBJECT = 0xa01, 295 MLX5_CMD_OP_QUERY_GENERAL_OBJECT = 0xa02, 296 MLX5_CMD_OP_DESTROY_GENERAL_OBJECT = 0xa03, 297 MLX5_CMD_OP_CREATE_UCTX = 0xa04, 298 MLX5_CMD_OP_DESTROY_UCTX = 0xa06, 299 MLX5_CMD_OP_CREATE_UMEM = 0xa08, 300 MLX5_CMD_OP_DESTROY_UMEM = 0xa0a, 301 MLX5_CMD_OP_SYNC_STEERING = 0xb00, 302 MLX5_CMD_OP_QUERY_VHCA_STATE = 0xb0d, 303 MLX5_CMD_OP_MODIFY_VHCA_STATE = 0xb0e, 304 MLX5_CMD_OP_MAX 305 }; 306 307 /* Valid range for general commands that don't work over an object */ 308 enum { 309 MLX5_CMD_OP_GENERAL_START = 0xb00, 310 MLX5_CMD_OP_GENERAL_END = 0xd00, 311 }; 312 313 struct mlx5_ifc_flow_table_fields_supported_bits { 314 u8 outer_dmac[0x1]; 315 u8 outer_smac[0x1]; 316 u8 outer_ether_type[0x1]; 317 u8 outer_ip_version[0x1]; 318 u8 outer_first_prio[0x1]; 319 u8 outer_first_cfi[0x1]; 320 u8 outer_first_vid[0x1]; 321 u8 outer_ipv4_ttl[0x1]; 322 u8 outer_second_prio[0x1]; 323 u8 outer_second_cfi[0x1]; 324 u8 outer_second_vid[0x1]; 325 u8 reserved_at_b[0x1]; 326 u8 outer_sip[0x1]; 327 u8 outer_dip[0x1]; 328 u8 outer_frag[0x1]; 329 u8 outer_ip_protocol[0x1]; 330 u8 outer_ip_ecn[0x1]; 331 u8 outer_ip_dscp[0x1]; 332 u8 outer_udp_sport[0x1]; 333 u8 outer_udp_dport[0x1]; 334 u8 outer_tcp_sport[0x1]; 335 u8 outer_tcp_dport[0x1]; 336 u8 outer_tcp_flags[0x1]; 337 u8 outer_gre_protocol[0x1]; 338 u8 outer_gre_key[0x1]; 339 u8 outer_vxlan_vni[0x1]; 340 u8 outer_geneve_vni[0x1]; 341 u8 outer_geneve_oam[0x1]; 342 u8 outer_geneve_protocol_type[0x1]; 343 u8 outer_geneve_opt_len[0x1]; 344 u8 reserved_at_1e[0x1]; 345 u8 source_eswitch_port[0x1]; 346 347 u8 inner_dmac[0x1]; 348 u8 inner_smac[0x1]; 349 u8 inner_ether_type[0x1]; 350 u8 inner_ip_version[0x1]; 351 u8 inner_first_prio[0x1]; 352 u8 inner_first_cfi[0x1]; 353 u8 inner_first_vid[0x1]; 354 u8 reserved_at_27[0x1]; 355 u8 inner_second_prio[0x1]; 356 u8 inner_second_cfi[0x1]; 357 u8 inner_second_vid[0x1]; 358 u8 reserved_at_2b[0x1]; 359 u8 inner_sip[0x1]; 360 u8 inner_dip[0x1]; 361 u8 inner_frag[0x1]; 362 u8 inner_ip_protocol[0x1]; 363 u8 inner_ip_ecn[0x1]; 364 u8 inner_ip_dscp[0x1]; 365 u8 inner_udp_sport[0x1]; 366 u8 inner_udp_dport[0x1]; 367 u8 inner_tcp_sport[0x1]; 368 u8 inner_tcp_dport[0x1]; 369 u8 inner_tcp_flags[0x1]; 370 u8 reserved_at_37[0x9]; 371 372 u8 geneve_tlv_option_0_data[0x1]; 373 u8 reserved_at_41[0x4]; 374 u8 outer_first_mpls_over_udp[0x4]; 375 u8 outer_first_mpls_over_gre[0x4]; 376 u8 inner_first_mpls[0x4]; 377 u8 outer_first_mpls[0x4]; 378 u8 reserved_at_55[0x2]; 379 u8 outer_esp_spi[0x1]; 380 u8 reserved_at_58[0x2]; 381 u8 bth_dst_qp[0x1]; 382 u8 reserved_at_5b[0x5]; 383 384 u8 reserved_at_60[0x18]; 385 u8 metadata_reg_c_7[0x1]; 386 u8 metadata_reg_c_6[0x1]; 387 u8 metadata_reg_c_5[0x1]; 388 u8 metadata_reg_c_4[0x1]; 389 u8 metadata_reg_c_3[0x1]; 390 u8 metadata_reg_c_2[0x1]; 391 u8 metadata_reg_c_1[0x1]; 392 u8 metadata_reg_c_0[0x1]; 393 }; 394 395 struct mlx5_ifc_flow_table_prop_layout_bits { 396 u8 ft_support[0x1]; 397 u8 reserved_at_1[0x1]; 398 u8 flow_counter[0x1]; 399 u8 flow_modify_en[0x1]; 400 u8 modify_root[0x1]; 401 u8 identified_miss_table_mode[0x1]; 402 u8 flow_table_modify[0x1]; 403 u8 reformat[0x1]; 404 u8 decap[0x1]; 405 u8 reserved_at_9[0x1]; 406 u8 pop_vlan[0x1]; 407 u8 push_vlan[0x1]; 408 u8 reserved_at_c[0x1]; 409 u8 pop_vlan_2[0x1]; 410 u8 push_vlan_2[0x1]; 411 u8 reformat_and_vlan_action[0x1]; 412 u8 reserved_at_10[0x1]; 413 u8 sw_owner[0x1]; 414 u8 reformat_l3_tunnel_to_l2[0x1]; 415 u8 reformat_l2_to_l3_tunnel[0x1]; 416 u8 reformat_and_modify_action[0x1]; 417 u8 ignore_flow_level[0x1]; 418 u8 reserved_at_16[0x1]; 419 u8 table_miss_action_domain[0x1]; 420 u8 termination_table[0x1]; 421 u8 reformat_and_fwd_to_table[0x1]; 422 u8 reserved_at_1a[0x2]; 423 u8 ipsec_encrypt[0x1]; 424 u8 ipsec_decrypt[0x1]; 425 u8 sw_owner_v2[0x1]; 426 u8 reserved_at_1f[0x1]; 427 428 u8 termination_table_raw_traffic[0x1]; 429 u8 reserved_at_21[0x1]; 430 u8 log_max_ft_size[0x6]; 431 u8 log_max_modify_header_context[0x8]; 432 u8 max_modify_header_actions[0x8]; 433 u8 max_ft_level[0x8]; 434 435 u8 reserved_at_40[0x20]; 436 437 u8 reserved_at_60[0x18]; 438 u8 log_max_ft_num[0x8]; 439 440 u8 reserved_at_80[0x10]; 441 u8 log_max_flow_counter[0x8]; 442 u8 log_max_destination[0x8]; 443 444 u8 reserved_at_a0[0x18]; 445 u8 log_max_flow[0x8]; 446 447 u8 reserved_at_c0[0x40]; 448 449 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support; 450 451 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support; 452 }; 453 454 struct mlx5_ifc_odp_per_transport_service_cap_bits { 455 u8 send[0x1]; 456 u8 receive[0x1]; 457 u8 write[0x1]; 458 u8 read[0x1]; 459 u8 atomic[0x1]; 460 u8 srq_receive[0x1]; 461 u8 reserved_at_6[0x1a]; 462 }; 463 464 struct mlx5_ifc_fte_match_set_lyr_2_4_bits { 465 u8 smac_47_16[0x20]; 466 467 u8 smac_15_0[0x10]; 468 u8 ethertype[0x10]; 469 470 u8 dmac_47_16[0x20]; 471 472 u8 dmac_15_0[0x10]; 473 u8 first_prio[0x3]; 474 u8 first_cfi[0x1]; 475 u8 first_vid[0xc]; 476 477 u8 ip_protocol[0x8]; 478 u8 ip_dscp[0x6]; 479 u8 ip_ecn[0x2]; 480 u8 cvlan_tag[0x1]; 481 u8 svlan_tag[0x1]; 482 u8 frag[0x1]; 483 u8 ip_version[0x4]; 484 u8 tcp_flags[0x9]; 485 486 u8 tcp_sport[0x10]; 487 u8 tcp_dport[0x10]; 488 489 u8 reserved_at_c0[0x18]; 490 u8 ttl_hoplimit[0x8]; 491 492 u8 udp_sport[0x10]; 493 u8 udp_dport[0x10]; 494 495 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6; 496 497 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6; 498 }; 499 500 struct mlx5_ifc_nvgre_key_bits { 501 u8 hi[0x18]; 502 u8 lo[0x8]; 503 }; 504 505 union mlx5_ifc_gre_key_bits { 506 struct mlx5_ifc_nvgre_key_bits nvgre; 507 u8 key[0x20]; 508 }; 509 510 struct mlx5_ifc_fte_match_set_misc_bits { 511 u8 gre_c_present[0x1]; 512 u8 reserved_at_1[0x1]; 513 u8 gre_k_present[0x1]; 514 u8 gre_s_present[0x1]; 515 u8 source_vhca_port[0x4]; 516 u8 source_sqn[0x18]; 517 518 u8 source_eswitch_owner_vhca_id[0x10]; 519 u8 source_port[0x10]; 520 521 u8 outer_second_prio[0x3]; 522 u8 outer_second_cfi[0x1]; 523 u8 outer_second_vid[0xc]; 524 u8 inner_second_prio[0x3]; 525 u8 inner_second_cfi[0x1]; 526 u8 inner_second_vid[0xc]; 527 528 u8 outer_second_cvlan_tag[0x1]; 529 u8 inner_second_cvlan_tag[0x1]; 530 u8 outer_second_svlan_tag[0x1]; 531 u8 inner_second_svlan_tag[0x1]; 532 u8 reserved_at_64[0xc]; 533 u8 gre_protocol[0x10]; 534 535 union mlx5_ifc_gre_key_bits gre_key; 536 537 u8 vxlan_vni[0x18]; 538 u8 reserved_at_b8[0x8]; 539 540 u8 geneve_vni[0x18]; 541 u8 reserved_at_d8[0x7]; 542 u8 geneve_oam[0x1]; 543 544 u8 reserved_at_e0[0xc]; 545 u8 outer_ipv6_flow_label[0x14]; 546 547 u8 reserved_at_100[0xc]; 548 u8 inner_ipv6_flow_label[0x14]; 549 550 u8 reserved_at_120[0xa]; 551 u8 geneve_opt_len[0x6]; 552 u8 geneve_protocol_type[0x10]; 553 554 u8 reserved_at_140[0x8]; 555 u8 bth_dst_qp[0x18]; 556 u8 reserved_at_160[0x20]; 557 u8 outer_esp_spi[0x20]; 558 u8 reserved_at_1a0[0x60]; 559 }; 560 561 struct mlx5_ifc_fte_match_mpls_bits { 562 u8 mpls_label[0x14]; 563 u8 mpls_exp[0x3]; 564 u8 mpls_s_bos[0x1]; 565 u8 mpls_ttl[0x8]; 566 }; 567 568 struct mlx5_ifc_fte_match_set_misc2_bits { 569 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls; 570 571 struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls; 572 573 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre; 574 575 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp; 576 577 u8 metadata_reg_c_7[0x20]; 578 579 u8 metadata_reg_c_6[0x20]; 580 581 u8 metadata_reg_c_5[0x20]; 582 583 u8 metadata_reg_c_4[0x20]; 584 585 u8 metadata_reg_c_3[0x20]; 586 587 u8 metadata_reg_c_2[0x20]; 588 589 u8 metadata_reg_c_1[0x20]; 590 591 u8 metadata_reg_c_0[0x20]; 592 593 u8 metadata_reg_a[0x20]; 594 595 u8 reserved_at_1a0[0x60]; 596 }; 597 598 struct mlx5_ifc_fte_match_set_misc3_bits { 599 u8 inner_tcp_seq_num[0x20]; 600 601 u8 outer_tcp_seq_num[0x20]; 602 603 u8 inner_tcp_ack_num[0x20]; 604 605 u8 outer_tcp_ack_num[0x20]; 606 607 u8 reserved_at_80[0x8]; 608 u8 outer_vxlan_gpe_vni[0x18]; 609 610 u8 outer_vxlan_gpe_next_protocol[0x8]; 611 u8 outer_vxlan_gpe_flags[0x8]; 612 u8 reserved_at_b0[0x10]; 613 614 u8 icmp_header_data[0x20]; 615 616 u8 icmpv6_header_data[0x20]; 617 618 u8 icmp_type[0x8]; 619 u8 icmp_code[0x8]; 620 u8 icmpv6_type[0x8]; 621 u8 icmpv6_code[0x8]; 622 623 u8 geneve_tlv_option_0_data[0x20]; 624 625 u8 gtpu_teid[0x20]; 626 627 u8 gtpu_msg_type[0x8]; 628 u8 gtpu_msg_flags[0x8]; 629 u8 reserved_at_170[0x10]; 630 631 u8 gtpu_dw_2[0x20]; 632 633 u8 gtpu_first_ext_dw_0[0x20]; 634 635 u8 gtpu_dw_0[0x20]; 636 637 u8 reserved_at_1e0[0x20]; 638 }; 639 640 struct mlx5_ifc_fte_match_set_misc4_bits { 641 u8 prog_sample_field_value_0[0x20]; 642 643 u8 prog_sample_field_id_0[0x20]; 644 645 u8 prog_sample_field_value_1[0x20]; 646 647 u8 prog_sample_field_id_1[0x20]; 648 649 u8 prog_sample_field_value_2[0x20]; 650 651 u8 prog_sample_field_id_2[0x20]; 652 653 u8 prog_sample_field_value_3[0x20]; 654 655 u8 prog_sample_field_id_3[0x20]; 656 657 u8 reserved_at_100[0x100]; 658 }; 659 660 struct mlx5_ifc_cmd_pas_bits { 661 u8 pa_h[0x20]; 662 663 u8 pa_l[0x14]; 664 u8 reserved_at_34[0xc]; 665 }; 666 667 struct mlx5_ifc_uint64_bits { 668 u8 hi[0x20]; 669 670 u8 lo[0x20]; 671 }; 672 673 enum { 674 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0, 675 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7, 676 MLX5_ADS_STAT_RATE_10GBPS = 0x8, 677 MLX5_ADS_STAT_RATE_30GBPS = 0x9, 678 MLX5_ADS_STAT_RATE_5GBPS = 0xa, 679 MLX5_ADS_STAT_RATE_20GBPS = 0xb, 680 MLX5_ADS_STAT_RATE_40GBPS = 0xc, 681 MLX5_ADS_STAT_RATE_60GBPS = 0xd, 682 MLX5_ADS_STAT_RATE_80GBPS = 0xe, 683 MLX5_ADS_STAT_RATE_120GBPS = 0xf, 684 }; 685 686 struct mlx5_ifc_ads_bits { 687 u8 fl[0x1]; 688 u8 free_ar[0x1]; 689 u8 reserved_at_2[0xe]; 690 u8 pkey_index[0x10]; 691 692 u8 reserved_at_20[0x8]; 693 u8 grh[0x1]; 694 u8 mlid[0x7]; 695 u8 rlid[0x10]; 696 697 u8 ack_timeout[0x5]; 698 u8 reserved_at_45[0x3]; 699 u8 src_addr_index[0x8]; 700 u8 reserved_at_50[0x4]; 701 u8 stat_rate[0x4]; 702 u8 hop_limit[0x8]; 703 704 u8 reserved_at_60[0x4]; 705 u8 tclass[0x8]; 706 u8 flow_label[0x14]; 707 708 u8 rgid_rip[16][0x8]; 709 710 u8 reserved_at_100[0x4]; 711 u8 f_dscp[0x1]; 712 u8 f_ecn[0x1]; 713 u8 reserved_at_106[0x1]; 714 u8 f_eth_prio[0x1]; 715 u8 ecn[0x2]; 716 u8 dscp[0x6]; 717 u8 udp_sport[0x10]; 718 719 u8 dei_cfi[0x1]; 720 u8 eth_prio[0x3]; 721 u8 sl[0x4]; 722 u8 vhca_port_num[0x8]; 723 u8 rmac_47_32[0x10]; 724 725 u8 rmac_31_0[0x20]; 726 }; 727 728 struct mlx5_ifc_flow_table_nic_cap_bits { 729 u8 nic_rx_multi_path_tirs[0x1]; 730 u8 nic_rx_multi_path_tirs_fts[0x1]; 731 u8 allow_sniffer_and_nic_rx_shared_tir[0x1]; 732 u8 reserved_at_3[0x4]; 733 u8 sw_owner_reformat_supported[0x1]; 734 u8 reserved_at_8[0x18]; 735 736 u8 encap_general_header[0x1]; 737 u8 reserved_at_21[0xa]; 738 u8 log_max_packet_reformat_context[0x5]; 739 u8 reserved_at_30[0x6]; 740 u8 max_encap_header_size[0xa]; 741 u8 reserved_at_40[0x1c0]; 742 743 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive; 744 745 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_rdma; 746 747 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer; 748 749 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit; 750 751 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_rdma; 752 753 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer; 754 755 u8 reserved_at_e00[0x1200]; 756 757 u8 sw_steering_nic_rx_action_drop_icm_address[0x40]; 758 759 u8 sw_steering_nic_tx_action_drop_icm_address[0x40]; 760 761 u8 sw_steering_nic_tx_action_allow_icm_address[0x40]; 762 763 u8 reserved_at_20c0[0x5f40]; 764 }; 765 766 enum { 767 MLX5_FDB_TO_VPORT_REG_C_0 = 0x01, 768 MLX5_FDB_TO_VPORT_REG_C_1 = 0x02, 769 MLX5_FDB_TO_VPORT_REG_C_2 = 0x04, 770 MLX5_FDB_TO_VPORT_REG_C_3 = 0x08, 771 MLX5_FDB_TO_VPORT_REG_C_4 = 0x10, 772 MLX5_FDB_TO_VPORT_REG_C_5 = 0x20, 773 MLX5_FDB_TO_VPORT_REG_C_6 = 0x40, 774 MLX5_FDB_TO_VPORT_REG_C_7 = 0x80, 775 }; 776 777 struct mlx5_ifc_flow_table_eswitch_cap_bits { 778 u8 fdb_to_vport_reg_c_id[0x8]; 779 u8 reserved_at_8[0xd]; 780 u8 fdb_modify_header_fwd_to_table[0x1]; 781 u8 reserved_at_16[0x1]; 782 u8 flow_source[0x1]; 783 u8 reserved_at_18[0x2]; 784 u8 multi_fdb_encap[0x1]; 785 u8 egress_acl_forward_to_vport[0x1]; 786 u8 fdb_multi_path_to_table[0x1]; 787 u8 reserved_at_1d[0x3]; 788 789 u8 reserved_at_20[0x1e0]; 790 791 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb; 792 793 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress; 794 795 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress; 796 797 u8 reserved_at_800[0x1000]; 798 799 u8 sw_steering_fdb_action_drop_icm_address_rx[0x40]; 800 801 u8 sw_steering_fdb_action_drop_icm_address_tx[0x40]; 802 803 u8 sw_steering_uplink_icm_address_rx[0x40]; 804 805 u8 sw_steering_uplink_icm_address_tx[0x40]; 806 807 u8 reserved_at_1900[0x6700]; 808 }; 809 810 enum { 811 MLX5_COUNTER_SOURCE_ESWITCH = 0x0, 812 MLX5_COUNTER_FLOW_ESWITCH = 0x1, 813 }; 814 815 struct mlx5_ifc_e_switch_cap_bits { 816 u8 vport_svlan_strip[0x1]; 817 u8 vport_cvlan_strip[0x1]; 818 u8 vport_svlan_insert[0x1]; 819 u8 vport_cvlan_insert_if_not_exist[0x1]; 820 u8 vport_cvlan_insert_overwrite[0x1]; 821 u8 reserved_at_5[0x2]; 822 u8 esw_shared_ingress_acl[0x1]; 823 u8 esw_uplink_ingress_acl[0x1]; 824 u8 root_ft_on_other_esw[0x1]; 825 u8 reserved_at_a[0xf]; 826 u8 esw_functions_changed[0x1]; 827 u8 reserved_at_1a[0x1]; 828 u8 ecpf_vport_exists[0x1]; 829 u8 counter_eswitch_affinity[0x1]; 830 u8 merged_eswitch[0x1]; 831 u8 nic_vport_node_guid_modify[0x1]; 832 u8 nic_vport_port_guid_modify[0x1]; 833 834 u8 vxlan_encap_decap[0x1]; 835 u8 nvgre_encap_decap[0x1]; 836 u8 reserved_at_22[0x1]; 837 u8 log_max_fdb_encap_uplink[0x5]; 838 u8 reserved_at_21[0x3]; 839 u8 log_max_packet_reformat_context[0x5]; 840 u8 reserved_2b[0x6]; 841 u8 max_encap_header_size[0xa]; 842 843 u8 reserved_at_40[0xb]; 844 u8 log_max_esw_sf[0x5]; 845 u8 esw_sf_base_id[0x10]; 846 847 u8 reserved_at_60[0x7a0]; 848 849 }; 850 851 struct mlx5_ifc_qos_cap_bits { 852 u8 packet_pacing[0x1]; 853 u8 esw_scheduling[0x1]; 854 u8 esw_bw_share[0x1]; 855 u8 esw_rate_limit[0x1]; 856 u8 reserved_at_4[0x1]; 857 u8 packet_pacing_burst_bound[0x1]; 858 u8 packet_pacing_typical_size[0x1]; 859 u8 reserved_at_7[0x1]; 860 u8 nic_sq_scheduling[0x1]; 861 u8 nic_bw_share[0x1]; 862 u8 nic_rate_limit[0x1]; 863 u8 packet_pacing_uid[0x1]; 864 u8 reserved_at_c[0x14]; 865 866 u8 reserved_at_20[0xb]; 867 u8 log_max_qos_nic_queue_group[0x5]; 868 u8 reserved_at_30[0x10]; 869 870 u8 packet_pacing_max_rate[0x20]; 871 872 u8 packet_pacing_min_rate[0x20]; 873 874 u8 reserved_at_80[0x10]; 875 u8 packet_pacing_rate_table_size[0x10]; 876 877 u8 esw_element_type[0x10]; 878 u8 esw_tsar_type[0x10]; 879 880 u8 reserved_at_c0[0x10]; 881 u8 max_qos_para_vport[0x10]; 882 883 u8 max_tsar_bw_share[0x20]; 884 885 u8 reserved_at_100[0x700]; 886 }; 887 888 struct mlx5_ifc_debug_cap_bits { 889 u8 core_dump_general[0x1]; 890 u8 core_dump_qp[0x1]; 891 u8 reserved_at_2[0x7]; 892 u8 resource_dump[0x1]; 893 u8 reserved_at_a[0x16]; 894 895 u8 reserved_at_20[0x2]; 896 u8 stall_detect[0x1]; 897 u8 reserved_at_23[0x1d]; 898 899 u8 reserved_at_40[0x7c0]; 900 }; 901 902 struct mlx5_ifc_per_protocol_networking_offload_caps_bits { 903 u8 csum_cap[0x1]; 904 u8 vlan_cap[0x1]; 905 u8 lro_cap[0x1]; 906 u8 lro_psh_flag[0x1]; 907 u8 lro_time_stamp[0x1]; 908 u8 reserved_at_5[0x2]; 909 u8 wqe_vlan_insert[0x1]; 910 u8 self_lb_en_modifiable[0x1]; 911 u8 reserved_at_9[0x2]; 912 u8 max_lso_cap[0x5]; 913 u8 multi_pkt_send_wqe[0x2]; 914 u8 wqe_inline_mode[0x2]; 915 u8 rss_ind_tbl_cap[0x4]; 916 u8 reg_umr_sq[0x1]; 917 u8 scatter_fcs[0x1]; 918 u8 enhanced_multi_pkt_send_wqe[0x1]; 919 u8 tunnel_lso_const_out_ip_id[0x1]; 920 u8 reserved_at_1c[0x2]; 921 u8 tunnel_stateless_gre[0x1]; 922 u8 tunnel_stateless_vxlan[0x1]; 923 924 u8 swp[0x1]; 925 u8 swp_csum[0x1]; 926 u8 swp_lso[0x1]; 927 u8 cqe_checksum_full[0x1]; 928 u8 tunnel_stateless_geneve_tx[0x1]; 929 u8 tunnel_stateless_mpls_over_udp[0x1]; 930 u8 tunnel_stateless_mpls_over_gre[0x1]; 931 u8 tunnel_stateless_vxlan_gpe[0x1]; 932 u8 tunnel_stateless_ipv4_over_vxlan[0x1]; 933 u8 tunnel_stateless_ip_over_ip[0x1]; 934 u8 insert_trailer[0x1]; 935 u8 reserved_at_2b[0x1]; 936 u8 tunnel_stateless_ip_over_ip_rx[0x1]; 937 u8 tunnel_stateless_ip_over_ip_tx[0x1]; 938 u8 reserved_at_2e[0x2]; 939 u8 max_vxlan_udp_ports[0x8]; 940 u8 reserved_at_38[0x6]; 941 u8 max_geneve_opt_len[0x1]; 942 u8 tunnel_stateless_geneve_rx[0x1]; 943 944 u8 reserved_at_40[0x10]; 945 u8 lro_min_mss_size[0x10]; 946 947 u8 reserved_at_60[0x120]; 948 949 u8 lro_timer_supported_periods[4][0x20]; 950 951 u8 reserved_at_200[0x600]; 952 }; 953 954 enum { 955 MLX5_QP_TIMESTAMP_FORMAT_CAP_FREE_RUNNING = 0x0, 956 MLX5_QP_TIMESTAMP_FORMAT_CAP_REAL_TIME = 0x1, 957 MLX5_QP_TIMESTAMP_FORMAT_CAP_FREE_RUNNING_AND_REAL_TIME = 0x2, 958 }; 959 960 struct mlx5_ifc_roce_cap_bits { 961 u8 roce_apm[0x1]; 962 u8 reserved_at_1[0x3]; 963 u8 sw_r_roce_src_udp_port[0x1]; 964 u8 fl_rc_qp_when_roce_disabled[0x1]; 965 u8 fl_rc_qp_when_roce_enabled[0x1]; 966 u8 reserved_at_7[0x17]; 967 u8 qp_ts_format[0x2]; 968 969 u8 reserved_at_20[0x60]; 970 971 u8 reserved_at_80[0xc]; 972 u8 l3_type[0x4]; 973 u8 reserved_at_90[0x8]; 974 u8 roce_version[0x8]; 975 976 u8 reserved_at_a0[0x10]; 977 u8 r_roce_dest_udp_port[0x10]; 978 979 u8 r_roce_max_src_udp_port[0x10]; 980 u8 r_roce_min_src_udp_port[0x10]; 981 982 u8 reserved_at_e0[0x10]; 983 u8 roce_address_table_size[0x10]; 984 985 u8 reserved_at_100[0x700]; 986 }; 987 988 struct mlx5_ifc_sync_steering_in_bits { 989 u8 opcode[0x10]; 990 u8 uid[0x10]; 991 992 u8 reserved_at_20[0x10]; 993 u8 op_mod[0x10]; 994 995 u8 reserved_at_40[0xc0]; 996 }; 997 998 struct mlx5_ifc_sync_steering_out_bits { 999 u8 status[0x8]; 1000 u8 reserved_at_8[0x18]; 1001 1002 u8 syndrome[0x20]; 1003 1004 u8 reserved_at_40[0x40]; 1005 }; 1006 1007 struct mlx5_ifc_device_mem_cap_bits { 1008 u8 memic[0x1]; 1009 u8 reserved_at_1[0x1f]; 1010 1011 u8 reserved_at_20[0xb]; 1012 u8 log_min_memic_alloc_size[0x5]; 1013 u8 reserved_at_30[0x8]; 1014 u8 log_max_memic_addr_alignment[0x8]; 1015 1016 u8 memic_bar_start_addr[0x40]; 1017 1018 u8 memic_bar_size[0x20]; 1019 1020 u8 max_memic_size[0x20]; 1021 1022 u8 steering_sw_icm_start_address[0x40]; 1023 1024 u8 reserved_at_100[0x8]; 1025 u8 log_header_modify_sw_icm_size[0x8]; 1026 u8 reserved_at_110[0x2]; 1027 u8 log_sw_icm_alloc_granularity[0x6]; 1028 u8 log_steering_sw_icm_size[0x8]; 1029 1030 u8 reserved_at_120[0x20]; 1031 1032 u8 header_modify_sw_icm_start_address[0x40]; 1033 1034 u8 reserved_at_180[0x680]; 1035 }; 1036 1037 struct mlx5_ifc_device_event_cap_bits { 1038 u8 user_affiliated_events[4][0x40]; 1039 1040 u8 user_unaffiliated_events[4][0x40]; 1041 }; 1042 1043 struct mlx5_ifc_virtio_emulation_cap_bits { 1044 u8 desc_tunnel_offload_type[0x1]; 1045 u8 eth_frame_offload_type[0x1]; 1046 u8 virtio_version_1_0[0x1]; 1047 u8 device_features_bits_mask[0xd]; 1048 u8 event_mode[0x8]; 1049 u8 virtio_queue_type[0x8]; 1050 1051 u8 max_tunnel_desc[0x10]; 1052 u8 reserved_at_30[0x3]; 1053 u8 log_doorbell_stride[0x5]; 1054 u8 reserved_at_38[0x3]; 1055 u8 log_doorbell_bar_size[0x5]; 1056 1057 u8 doorbell_bar_offset[0x40]; 1058 1059 u8 max_emulated_devices[0x8]; 1060 u8 max_num_virtio_queues[0x18]; 1061 1062 u8 reserved_at_a0[0x60]; 1063 1064 u8 umem_1_buffer_param_a[0x20]; 1065 1066 u8 umem_1_buffer_param_b[0x20]; 1067 1068 u8 umem_2_buffer_param_a[0x20]; 1069 1070 u8 umem_2_buffer_param_b[0x20]; 1071 1072 u8 umem_3_buffer_param_a[0x20]; 1073 1074 u8 umem_3_buffer_param_b[0x20]; 1075 1076 u8 reserved_at_1c0[0x640]; 1077 }; 1078 1079 enum { 1080 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0, 1081 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2, 1082 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4, 1083 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8, 1084 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10, 1085 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20, 1086 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40, 1087 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80, 1088 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100, 1089 }; 1090 1091 enum { 1092 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1, 1093 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2, 1094 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4, 1095 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8, 1096 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10, 1097 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20, 1098 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40, 1099 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80, 1100 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100, 1101 }; 1102 1103 struct mlx5_ifc_atomic_caps_bits { 1104 u8 reserved_at_0[0x40]; 1105 1106 u8 atomic_req_8B_endianness_mode[0x2]; 1107 u8 reserved_at_42[0x4]; 1108 u8 supported_atomic_req_8B_endianness_mode_1[0x1]; 1109 1110 u8 reserved_at_47[0x19]; 1111 1112 u8 reserved_at_60[0x20]; 1113 1114 u8 reserved_at_80[0x10]; 1115 u8 atomic_operations[0x10]; 1116 1117 u8 reserved_at_a0[0x10]; 1118 u8 atomic_size_qp[0x10]; 1119 1120 u8 reserved_at_c0[0x10]; 1121 u8 atomic_size_dc[0x10]; 1122 1123 u8 reserved_at_e0[0x720]; 1124 }; 1125 1126 struct mlx5_ifc_odp_cap_bits { 1127 u8 reserved_at_0[0x40]; 1128 1129 u8 sig[0x1]; 1130 u8 reserved_at_41[0x1f]; 1131 1132 u8 reserved_at_60[0x20]; 1133 1134 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps; 1135 1136 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps; 1137 1138 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps; 1139 1140 struct mlx5_ifc_odp_per_transport_service_cap_bits xrc_odp_caps; 1141 1142 struct mlx5_ifc_odp_per_transport_service_cap_bits dc_odp_caps; 1143 1144 u8 reserved_at_120[0x6E0]; 1145 }; 1146 1147 struct mlx5_ifc_calc_op { 1148 u8 reserved_at_0[0x10]; 1149 u8 reserved_at_10[0x9]; 1150 u8 op_swap_endianness[0x1]; 1151 u8 op_min[0x1]; 1152 u8 op_xor[0x1]; 1153 u8 op_or[0x1]; 1154 u8 op_and[0x1]; 1155 u8 op_max[0x1]; 1156 u8 op_add[0x1]; 1157 }; 1158 1159 struct mlx5_ifc_vector_calc_cap_bits { 1160 u8 calc_matrix[0x1]; 1161 u8 reserved_at_1[0x1f]; 1162 u8 reserved_at_20[0x8]; 1163 u8 max_vec_count[0x8]; 1164 u8 reserved_at_30[0xd]; 1165 u8 max_chunk_size[0x3]; 1166 struct mlx5_ifc_calc_op calc0; 1167 struct mlx5_ifc_calc_op calc1; 1168 struct mlx5_ifc_calc_op calc2; 1169 struct mlx5_ifc_calc_op calc3; 1170 1171 u8 reserved_at_c0[0x720]; 1172 }; 1173 1174 struct mlx5_ifc_tls_cap_bits { 1175 u8 tls_1_2_aes_gcm_128[0x1]; 1176 u8 tls_1_3_aes_gcm_128[0x1]; 1177 u8 tls_1_2_aes_gcm_256[0x1]; 1178 u8 tls_1_3_aes_gcm_256[0x1]; 1179 u8 reserved_at_4[0x1c]; 1180 1181 u8 reserved_at_20[0x7e0]; 1182 }; 1183 1184 struct mlx5_ifc_ipsec_cap_bits { 1185 u8 ipsec_full_offload[0x1]; 1186 u8 ipsec_crypto_offload[0x1]; 1187 u8 ipsec_esn[0x1]; 1188 u8 ipsec_crypto_esp_aes_gcm_256_encrypt[0x1]; 1189 u8 ipsec_crypto_esp_aes_gcm_128_encrypt[0x1]; 1190 u8 ipsec_crypto_esp_aes_gcm_256_decrypt[0x1]; 1191 u8 ipsec_crypto_esp_aes_gcm_128_decrypt[0x1]; 1192 u8 reserved_at_7[0x4]; 1193 u8 log_max_ipsec_offload[0x5]; 1194 u8 reserved_at_10[0x10]; 1195 1196 u8 min_log_ipsec_full_replay_window[0x8]; 1197 u8 max_log_ipsec_full_replay_window[0x8]; 1198 u8 reserved_at_30[0x7d0]; 1199 }; 1200 1201 enum { 1202 MLX5_WQ_TYPE_LINKED_LIST = 0x0, 1203 MLX5_WQ_TYPE_CYCLIC = 0x1, 1204 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2, 1205 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3, 1206 }; 1207 1208 enum { 1209 MLX5_WQ_END_PAD_MODE_NONE = 0x0, 1210 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1, 1211 }; 1212 1213 enum { 1214 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0, 1215 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1, 1216 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2, 1217 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3, 1218 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4, 1219 }; 1220 1221 enum { 1222 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0, 1223 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1, 1224 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2, 1225 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3, 1226 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4, 1227 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5, 1228 }; 1229 1230 enum { 1231 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0, 1232 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1, 1233 }; 1234 1235 enum { 1236 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0, 1237 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1, 1238 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3, 1239 }; 1240 1241 enum { 1242 MLX5_CAP_PORT_TYPE_IB = 0x0, 1243 MLX5_CAP_PORT_TYPE_ETH = 0x1, 1244 }; 1245 1246 enum { 1247 MLX5_CAP_UMR_FENCE_STRONG = 0x0, 1248 MLX5_CAP_UMR_FENCE_SMALL = 0x1, 1249 MLX5_CAP_UMR_FENCE_NONE = 0x2, 1250 }; 1251 1252 enum { 1253 MLX5_FLEX_PARSER_GENEVE_ENABLED = 1 << 3, 1254 MLX5_FLEX_PARSER_MPLS_OVER_GRE_ENABLED = 1 << 4, 1255 mlx5_FLEX_PARSER_MPLS_OVER_UDP_ENABLED = 1 << 5, 1256 MLX5_FLEX_PARSER_VXLAN_GPE_ENABLED = 1 << 7, 1257 MLX5_FLEX_PARSER_ICMP_V4_ENABLED = 1 << 8, 1258 MLX5_FLEX_PARSER_ICMP_V6_ENABLED = 1 << 9, 1259 MLX5_FLEX_PARSER_GENEVE_TLV_OPTION_0_ENABLED = 1 << 10, 1260 MLX5_FLEX_PARSER_GTPU_ENABLED = 1 << 11, 1261 MLX5_FLEX_PARSER_GTPU_DW_2_ENABLED = 1 << 16, 1262 MLX5_FLEX_PARSER_GTPU_FIRST_EXT_DW_0_ENABLED = 1 << 17, 1263 MLX5_FLEX_PARSER_GTPU_DW_0_ENABLED = 1 << 18, 1264 MLX5_FLEX_PARSER_GTPU_TEID_ENABLED = 1 << 19, 1265 }; 1266 1267 enum { 1268 MLX5_UCTX_CAP_RAW_TX = 1UL << 0, 1269 MLX5_UCTX_CAP_INTERNAL_DEV_RES = 1UL << 1, 1270 }; 1271 1272 #define MLX5_FC_BULK_SIZE_FACTOR 128 1273 1274 enum mlx5_fc_bulk_alloc_bitmask { 1275 MLX5_FC_BULK_128 = (1 << 0), 1276 MLX5_FC_BULK_256 = (1 << 1), 1277 MLX5_FC_BULK_512 = (1 << 2), 1278 MLX5_FC_BULK_1024 = (1 << 3), 1279 MLX5_FC_BULK_2048 = (1 << 4), 1280 MLX5_FC_BULK_4096 = (1 << 5), 1281 MLX5_FC_BULK_8192 = (1 << 6), 1282 MLX5_FC_BULK_16384 = (1 << 7), 1283 }; 1284 1285 #define MLX5_FC_BULK_NUM_FCS(fc_enum) (MLX5_FC_BULK_SIZE_FACTOR * (fc_enum)) 1286 1287 enum { 1288 MLX5_STEERING_FORMAT_CONNECTX_5 = 0, 1289 MLX5_STEERING_FORMAT_CONNECTX_6DX = 1, 1290 }; 1291 1292 enum { 1293 MLX5_SQ_TIMESTAMP_FORMAT_CAP_FREE_RUNNING = 0x0, 1294 MLX5_SQ_TIMESTAMP_FORMAT_CAP_REAL_TIME = 0x1, 1295 MLX5_SQ_TIMESTAMP_FORMAT_CAP_FREE_RUNNING_AND_REAL_TIME = 0x2, 1296 }; 1297 1298 enum { 1299 MLX5_RQ_TIMESTAMP_FORMAT_CAP_FREE_RUNNING = 0x0, 1300 MLX5_RQ_TIMESTAMP_FORMAT_CAP_REAL_TIME = 0x1, 1301 MLX5_RQ_TIMESTAMP_FORMAT_CAP_FREE_RUNNING_AND_REAL_TIME = 0x2, 1302 }; 1303 1304 struct mlx5_ifc_cmd_hca_cap_bits { 1305 u8 reserved_at_0[0x1f]; 1306 u8 vhca_resource_manager[0x1]; 1307 1308 u8 reserved_at_20[0x3]; 1309 u8 event_on_vhca_state_teardown_request[0x1]; 1310 u8 event_on_vhca_state_in_use[0x1]; 1311 u8 event_on_vhca_state_active[0x1]; 1312 u8 event_on_vhca_state_allocated[0x1]; 1313 u8 event_on_vhca_state_invalid[0x1]; 1314 u8 reserved_at_28[0x8]; 1315 u8 vhca_id[0x10]; 1316 1317 u8 reserved_at_40[0x40]; 1318 1319 u8 log_max_srq_sz[0x8]; 1320 u8 log_max_qp_sz[0x8]; 1321 u8 event_cap[0x1]; 1322 u8 reserved_at_91[0x2]; 1323 u8 isolate_vl_tc_new[0x1]; 1324 u8 reserved_at_94[0x4]; 1325 u8 prio_tag_required[0x1]; 1326 u8 reserved_at_99[0x2]; 1327 u8 log_max_qp[0x5]; 1328 1329 u8 reserved_at_a0[0x3]; 1330 u8 ece_support[0x1]; 1331 u8 reserved_at_a4[0x5]; 1332 u8 reg_c_preserve[0x1]; 1333 u8 reserved_at_aa[0x1]; 1334 u8 log_max_srq[0x5]; 1335 u8 reserved_at_b0[0x1]; 1336 u8 uplink_follow[0x1]; 1337 u8 ts_cqe_to_dest_cqn[0x1]; 1338 u8 reserved_at_b3[0xd]; 1339 1340 u8 max_sgl_for_optimized_performance[0x8]; 1341 u8 log_max_cq_sz[0x8]; 1342 u8 relaxed_ordering_write_umr[0x1]; 1343 u8 relaxed_ordering_read_umr[0x1]; 1344 u8 reserved_at_d2[0x7]; 1345 u8 virtio_net_device_emualtion_manager[0x1]; 1346 u8 virtio_blk_device_emualtion_manager[0x1]; 1347 u8 log_max_cq[0x5]; 1348 1349 u8 log_max_eq_sz[0x8]; 1350 u8 relaxed_ordering_write[0x1]; 1351 u8 relaxed_ordering_read[0x1]; 1352 u8 log_max_mkey[0x6]; 1353 u8 reserved_at_f0[0x8]; 1354 u8 dump_fill_mkey[0x1]; 1355 u8 reserved_at_f9[0x2]; 1356 u8 fast_teardown[0x1]; 1357 u8 log_max_eq[0x4]; 1358 1359 u8 max_indirection[0x8]; 1360 u8 fixed_buffer_size[0x1]; 1361 u8 log_max_mrw_sz[0x7]; 1362 u8 force_teardown[0x1]; 1363 u8 reserved_at_111[0x1]; 1364 u8 log_max_bsf_list_size[0x6]; 1365 u8 umr_extended_translation_offset[0x1]; 1366 u8 null_mkey[0x1]; 1367 u8 log_max_klm_list_size[0x6]; 1368 1369 u8 reserved_at_120[0xa]; 1370 u8 log_max_ra_req_dc[0x6]; 1371 u8 reserved_at_130[0xa]; 1372 u8 log_max_ra_res_dc[0x6]; 1373 1374 u8 reserved_at_140[0x6]; 1375 u8 release_all_pages[0x1]; 1376 u8 reserved_at_147[0x2]; 1377 u8 roce_accl[0x1]; 1378 u8 log_max_ra_req_qp[0x6]; 1379 u8 reserved_at_150[0xa]; 1380 u8 log_max_ra_res_qp[0x6]; 1381 1382 u8 end_pad[0x1]; 1383 u8 cc_query_allowed[0x1]; 1384 u8 cc_modify_allowed[0x1]; 1385 u8 start_pad[0x1]; 1386 u8 cache_line_128byte[0x1]; 1387 u8 reserved_at_165[0x4]; 1388 u8 rts2rts_qp_counters_set_id[0x1]; 1389 u8 reserved_at_16a[0x2]; 1390 u8 vnic_env_int_rq_oob[0x1]; 1391 u8 sbcam_reg[0x1]; 1392 u8 reserved_at_16e[0x1]; 1393 u8 qcam_reg[0x1]; 1394 u8 gid_table_size[0x10]; 1395 1396 u8 out_of_seq_cnt[0x1]; 1397 u8 vport_counters[0x1]; 1398 u8 retransmission_q_counters[0x1]; 1399 u8 debug[0x1]; 1400 u8 modify_rq_counter_set_id[0x1]; 1401 u8 rq_delay_drop[0x1]; 1402 u8 max_qp_cnt[0xa]; 1403 u8 pkey_table_size[0x10]; 1404 1405 u8 vport_group_manager[0x1]; 1406 u8 vhca_group_manager[0x1]; 1407 u8 ib_virt[0x1]; 1408 u8 eth_virt[0x1]; 1409 u8 vnic_env_queue_counters[0x1]; 1410 u8 ets[0x1]; 1411 u8 nic_flow_table[0x1]; 1412 u8 eswitch_manager[0x1]; 1413 u8 device_memory[0x1]; 1414 u8 mcam_reg[0x1]; 1415 u8 pcam_reg[0x1]; 1416 u8 local_ca_ack_delay[0x5]; 1417 u8 port_module_event[0x1]; 1418 u8 enhanced_error_q_counters[0x1]; 1419 u8 ports_check[0x1]; 1420 u8 reserved_at_1b3[0x1]; 1421 u8 disable_link_up[0x1]; 1422 u8 beacon_led[0x1]; 1423 u8 port_type[0x2]; 1424 u8 num_ports[0x8]; 1425 1426 u8 reserved_at_1c0[0x1]; 1427 u8 pps[0x1]; 1428 u8 pps_modify[0x1]; 1429 u8 log_max_msg[0x5]; 1430 u8 reserved_at_1c8[0x4]; 1431 u8 max_tc[0x4]; 1432 u8 temp_warn_event[0x1]; 1433 u8 dcbx[0x1]; 1434 u8 general_notification_event[0x1]; 1435 u8 reserved_at_1d3[0x2]; 1436 u8 fpga[0x1]; 1437 u8 rol_s[0x1]; 1438 u8 rol_g[0x1]; 1439 u8 reserved_at_1d8[0x1]; 1440 u8 wol_s[0x1]; 1441 u8 wol_g[0x1]; 1442 u8 wol_a[0x1]; 1443 u8 wol_b[0x1]; 1444 u8 wol_m[0x1]; 1445 u8 wol_u[0x1]; 1446 u8 wol_p[0x1]; 1447 1448 u8 stat_rate_support[0x10]; 1449 u8 reserved_at_1f0[0x1]; 1450 u8 pci_sync_for_fw_update_event[0x1]; 1451 u8 reserved_at_1f2[0x6]; 1452 u8 init2_lag_tx_port_affinity[0x1]; 1453 u8 reserved_at_1fa[0x3]; 1454 u8 cqe_version[0x4]; 1455 1456 u8 compact_address_vector[0x1]; 1457 u8 striding_rq[0x1]; 1458 u8 reserved_at_202[0x1]; 1459 u8 ipoib_enhanced_offloads[0x1]; 1460 u8 ipoib_basic_offloads[0x1]; 1461 u8 reserved_at_205[0x1]; 1462 u8 repeated_block_disabled[0x1]; 1463 u8 umr_modify_entity_size_disabled[0x1]; 1464 u8 umr_modify_atomic_disabled[0x1]; 1465 u8 umr_indirect_mkey_disabled[0x1]; 1466 u8 umr_fence[0x2]; 1467 u8 dc_req_scat_data_cqe[0x1]; 1468 u8 reserved_at_20d[0x2]; 1469 u8 drain_sigerr[0x1]; 1470 u8 cmdif_checksum[0x2]; 1471 u8 sigerr_cqe[0x1]; 1472 u8 reserved_at_213[0x1]; 1473 u8 wq_signature[0x1]; 1474 u8 sctr_data_cqe[0x1]; 1475 u8 reserved_at_216[0x1]; 1476 u8 sho[0x1]; 1477 u8 tph[0x1]; 1478 u8 rf[0x1]; 1479 u8 dct[0x1]; 1480 u8 qos[0x1]; 1481 u8 eth_net_offloads[0x1]; 1482 u8 roce[0x1]; 1483 u8 atomic[0x1]; 1484 u8 reserved_at_21f[0x1]; 1485 1486 u8 cq_oi[0x1]; 1487 u8 cq_resize[0x1]; 1488 u8 cq_moderation[0x1]; 1489 u8 reserved_at_223[0x3]; 1490 u8 cq_eq_remap[0x1]; 1491 u8 pg[0x1]; 1492 u8 block_lb_mc[0x1]; 1493 u8 reserved_at_229[0x1]; 1494 u8 scqe_break_moderation[0x1]; 1495 u8 cq_period_start_from_cqe[0x1]; 1496 u8 cd[0x1]; 1497 u8 reserved_at_22d[0x1]; 1498 u8 apm[0x1]; 1499 u8 vector_calc[0x1]; 1500 u8 umr_ptr_rlky[0x1]; 1501 u8 imaicl[0x1]; 1502 u8 qp_packet_based[0x1]; 1503 u8 reserved_at_233[0x3]; 1504 u8 qkv[0x1]; 1505 u8 pkv[0x1]; 1506 u8 set_deth_sqpn[0x1]; 1507 u8 reserved_at_239[0x3]; 1508 u8 xrc[0x1]; 1509 u8 ud[0x1]; 1510 u8 uc[0x1]; 1511 u8 rc[0x1]; 1512 1513 u8 uar_4k[0x1]; 1514 u8 reserved_at_241[0x9]; 1515 u8 uar_sz[0x6]; 1516 u8 reserved_at_250[0x8]; 1517 u8 log_pg_sz[0x8]; 1518 1519 u8 bf[0x1]; 1520 u8 driver_version[0x1]; 1521 u8 pad_tx_eth_packet[0x1]; 1522 u8 reserved_at_263[0x3]; 1523 u8 mkey_by_name[0x1]; 1524 u8 reserved_at_267[0x4]; 1525 1526 u8 log_bf_reg_size[0x5]; 1527 1528 u8 reserved_at_270[0x6]; 1529 u8 lag_dct[0x2]; 1530 u8 lag_tx_port_affinity[0x1]; 1531 u8 lag_native_fdb_selection[0x1]; 1532 u8 reserved_at_27a[0x1]; 1533 u8 lag_master[0x1]; 1534 u8 num_lag_ports[0x4]; 1535 1536 u8 reserved_at_280[0x10]; 1537 u8 max_wqe_sz_sq[0x10]; 1538 1539 u8 reserved_at_2a0[0x10]; 1540 u8 max_wqe_sz_rq[0x10]; 1541 1542 u8 max_flow_counter_31_16[0x10]; 1543 u8 max_wqe_sz_sq_dc[0x10]; 1544 1545 u8 reserved_at_2e0[0x7]; 1546 u8 max_qp_mcg[0x19]; 1547 1548 u8 reserved_at_300[0x10]; 1549 u8 flow_counter_bulk_alloc[0x8]; 1550 u8 log_max_mcg[0x8]; 1551 1552 u8 reserved_at_320[0x3]; 1553 u8 log_max_transport_domain[0x5]; 1554 u8 reserved_at_328[0x3]; 1555 u8 log_max_pd[0x5]; 1556 u8 reserved_at_330[0xb]; 1557 u8 log_max_xrcd[0x5]; 1558 1559 u8 nic_receive_steering_discard[0x1]; 1560 u8 receive_discard_vport_down[0x1]; 1561 u8 transmit_discard_vport_down[0x1]; 1562 u8 reserved_at_343[0x5]; 1563 u8 log_max_flow_counter_bulk[0x8]; 1564 u8 max_flow_counter_15_0[0x10]; 1565 1566 1567 u8 reserved_at_360[0x3]; 1568 u8 log_max_rq[0x5]; 1569 u8 reserved_at_368[0x3]; 1570 u8 log_max_sq[0x5]; 1571 u8 reserved_at_370[0x3]; 1572 u8 log_max_tir[0x5]; 1573 u8 reserved_at_378[0x3]; 1574 u8 log_max_tis[0x5]; 1575 1576 u8 basic_cyclic_rcv_wqe[0x1]; 1577 u8 reserved_at_381[0x2]; 1578 u8 log_max_rmp[0x5]; 1579 u8 reserved_at_388[0x3]; 1580 u8 log_max_rqt[0x5]; 1581 u8 reserved_at_390[0x3]; 1582 u8 log_max_rqt_size[0x5]; 1583 u8 reserved_at_398[0x3]; 1584 u8 log_max_tis_per_sq[0x5]; 1585 1586 u8 ext_stride_num_range[0x1]; 1587 u8 reserved_at_3a1[0x2]; 1588 u8 log_max_stride_sz_rq[0x5]; 1589 u8 reserved_at_3a8[0x3]; 1590 u8 log_min_stride_sz_rq[0x5]; 1591 u8 reserved_at_3b0[0x3]; 1592 u8 log_max_stride_sz_sq[0x5]; 1593 u8 reserved_at_3b8[0x3]; 1594 u8 log_min_stride_sz_sq[0x5]; 1595 1596 u8 hairpin[0x1]; 1597 u8 reserved_at_3c1[0x2]; 1598 u8 log_max_hairpin_queues[0x5]; 1599 u8 reserved_at_3c8[0x3]; 1600 u8 log_max_hairpin_wq_data_sz[0x5]; 1601 u8 reserved_at_3d0[0x3]; 1602 u8 log_max_hairpin_num_packets[0x5]; 1603 u8 reserved_at_3d8[0x3]; 1604 u8 log_max_wq_sz[0x5]; 1605 1606 u8 nic_vport_change_event[0x1]; 1607 u8 disable_local_lb_uc[0x1]; 1608 u8 disable_local_lb_mc[0x1]; 1609 u8 log_min_hairpin_wq_data_sz[0x5]; 1610 u8 reserved_at_3e8[0x2]; 1611 u8 vhca_state[0x1]; 1612 u8 log_max_vlan_list[0x5]; 1613 u8 reserved_at_3f0[0x3]; 1614 u8 log_max_current_mc_list[0x5]; 1615 u8 reserved_at_3f8[0x3]; 1616 u8 log_max_current_uc_list[0x5]; 1617 1618 u8 general_obj_types[0x40]; 1619 1620 u8 sq_ts_format[0x2]; 1621 u8 rq_ts_format[0x2]; 1622 u8 steering_format_version[0x4]; 1623 u8 create_qp_start_hint[0x18]; 1624 1625 u8 reserved_at_460[0x3]; 1626 u8 log_max_uctx[0x5]; 1627 u8 reserved_at_468[0x2]; 1628 u8 ipsec_offload[0x1]; 1629 u8 log_max_umem[0x5]; 1630 u8 max_num_eqs[0x10]; 1631 1632 u8 reserved_at_480[0x1]; 1633 u8 tls_tx[0x1]; 1634 u8 tls_rx[0x1]; 1635 u8 log_max_l2_table[0x5]; 1636 u8 reserved_at_488[0x8]; 1637 u8 log_uar_page_sz[0x10]; 1638 1639 u8 reserved_at_4a0[0x20]; 1640 u8 device_frequency_mhz[0x20]; 1641 u8 device_frequency_khz[0x20]; 1642 1643 u8 reserved_at_500[0x20]; 1644 u8 num_of_uars_per_page[0x20]; 1645 1646 u8 flex_parser_protocols[0x20]; 1647 1648 u8 max_geneve_tlv_options[0x8]; 1649 u8 reserved_at_568[0x3]; 1650 u8 max_geneve_tlv_option_data_len[0x5]; 1651 u8 reserved_at_570[0x10]; 1652 1653 u8 reserved_at_580[0x33]; 1654 u8 log_max_dek[0x5]; 1655 u8 reserved_at_5b8[0x4]; 1656 u8 mini_cqe_resp_stride_index[0x1]; 1657 u8 cqe_128_always[0x1]; 1658 u8 cqe_compression_128[0x1]; 1659 u8 cqe_compression[0x1]; 1660 1661 u8 cqe_compression_timeout[0x10]; 1662 u8 cqe_compression_max_num[0x10]; 1663 1664 u8 reserved_at_5e0[0x8]; 1665 u8 flex_parser_id_gtpu_dw_0[0x4]; 1666 u8 reserved_at_5ec[0x4]; 1667 u8 tag_matching[0x1]; 1668 u8 rndv_offload_rc[0x1]; 1669 u8 rndv_offload_dc[0x1]; 1670 u8 log_tag_matching_list_sz[0x5]; 1671 u8 reserved_at_5f8[0x3]; 1672 u8 log_max_xrq[0x5]; 1673 1674 u8 affiliate_nic_vport_criteria[0x8]; 1675 u8 native_port_num[0x8]; 1676 u8 num_vhca_ports[0x8]; 1677 u8 flex_parser_id_gtpu_teid[0x4]; 1678 u8 reserved_at_61c[0x2]; 1679 u8 sw_owner_id[0x1]; 1680 u8 reserved_at_61f[0x1]; 1681 1682 u8 max_num_of_monitor_counters[0x10]; 1683 u8 num_ppcnt_monitor_counters[0x10]; 1684 1685 u8 max_num_sf[0x10]; 1686 u8 num_q_monitor_counters[0x10]; 1687 1688 u8 reserved_at_660[0x20]; 1689 1690 u8 sf[0x1]; 1691 u8 sf_set_partition[0x1]; 1692 u8 reserved_at_682[0x1]; 1693 u8 log_max_sf[0x5]; 1694 u8 apu[0x1]; 1695 u8 reserved_at_689[0x7]; 1696 u8 log_min_sf_size[0x8]; 1697 u8 max_num_sf_partitions[0x8]; 1698 1699 u8 uctx_cap[0x20]; 1700 1701 u8 reserved_at_6c0[0x4]; 1702 u8 flex_parser_id_geneve_tlv_option_0[0x4]; 1703 u8 flex_parser_id_icmp_dw1[0x4]; 1704 u8 flex_parser_id_icmp_dw0[0x4]; 1705 u8 flex_parser_id_icmpv6_dw1[0x4]; 1706 u8 flex_parser_id_icmpv6_dw0[0x4]; 1707 u8 flex_parser_id_outer_first_mpls_over_gre[0x4]; 1708 u8 flex_parser_id_outer_first_mpls_over_udp_label[0x4]; 1709 1710 u8 reserved_at_6e0[0x10]; 1711 u8 sf_base_id[0x10]; 1712 1713 u8 flex_parser_id_gtpu_dw_2[0x4]; 1714 u8 flex_parser_id_gtpu_first_ext_dw_0[0x4]; 1715 u8 num_total_dynamic_vf_msix[0x18]; 1716 u8 reserved_at_720[0x14]; 1717 u8 dynamic_msix_table_size[0xc]; 1718 u8 reserved_at_740[0xc]; 1719 u8 min_dynamic_vf_msix_table_size[0x4]; 1720 u8 reserved_at_750[0x4]; 1721 u8 max_dynamic_vf_msix_table_size[0xc]; 1722 1723 u8 reserved_at_760[0x20]; 1724 u8 vhca_tunnel_commands[0x40]; 1725 u8 reserved_at_7c0[0x40]; 1726 }; 1727 1728 enum mlx5_flow_destination_type { 1729 MLX5_FLOW_DESTINATION_TYPE_VPORT = 0x0, 1730 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1, 1731 MLX5_FLOW_DESTINATION_TYPE_TIR = 0x2, 1732 MLX5_FLOW_DESTINATION_TYPE_FLOW_SAMPLER = 0x6, 1733 1734 MLX5_FLOW_DESTINATION_TYPE_PORT = 0x99, 1735 MLX5_FLOW_DESTINATION_TYPE_COUNTER = 0x100, 1736 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE_NUM = 0x101, 1737 }; 1738 1739 enum mlx5_flow_table_miss_action { 1740 MLX5_FLOW_TABLE_MISS_ACTION_DEF, 1741 MLX5_FLOW_TABLE_MISS_ACTION_FWD, 1742 MLX5_FLOW_TABLE_MISS_ACTION_SWITCH_DOMAIN, 1743 }; 1744 1745 struct mlx5_ifc_dest_format_struct_bits { 1746 u8 destination_type[0x8]; 1747 u8 destination_id[0x18]; 1748 1749 u8 destination_eswitch_owner_vhca_id_valid[0x1]; 1750 u8 packet_reformat[0x1]; 1751 u8 reserved_at_22[0xe]; 1752 u8 destination_eswitch_owner_vhca_id[0x10]; 1753 }; 1754 1755 struct mlx5_ifc_flow_counter_list_bits { 1756 u8 flow_counter_id[0x20]; 1757 1758 u8 reserved_at_20[0x20]; 1759 }; 1760 1761 struct mlx5_ifc_extended_dest_format_bits { 1762 struct mlx5_ifc_dest_format_struct_bits destination_entry; 1763 1764 u8 packet_reformat_id[0x20]; 1765 1766 u8 reserved_at_60[0x20]; 1767 }; 1768 1769 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits { 1770 struct mlx5_ifc_extended_dest_format_bits extended_dest_format; 1771 struct mlx5_ifc_flow_counter_list_bits flow_counter_list; 1772 }; 1773 1774 struct mlx5_ifc_fte_match_param_bits { 1775 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers; 1776 1777 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters; 1778 1779 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers; 1780 1781 struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2; 1782 1783 struct mlx5_ifc_fte_match_set_misc3_bits misc_parameters_3; 1784 1785 struct mlx5_ifc_fte_match_set_misc4_bits misc_parameters_4; 1786 1787 u8 reserved_at_c00[0x400]; 1788 }; 1789 1790 enum { 1791 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0, 1792 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1, 1793 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2, 1794 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3, 1795 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4, 1796 }; 1797 1798 struct mlx5_ifc_rx_hash_field_select_bits { 1799 u8 l3_prot_type[0x1]; 1800 u8 l4_prot_type[0x1]; 1801 u8 selected_fields[0x1e]; 1802 }; 1803 1804 enum { 1805 MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0, 1806 MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1, 1807 }; 1808 1809 enum { 1810 MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0, 1811 MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1, 1812 }; 1813 1814 struct mlx5_ifc_wq_bits { 1815 u8 wq_type[0x4]; 1816 u8 wq_signature[0x1]; 1817 u8 end_padding_mode[0x2]; 1818 u8 cd_slave[0x1]; 1819 u8 reserved_at_8[0x18]; 1820 1821 u8 hds_skip_first_sge[0x1]; 1822 u8 log2_hds_buf_size[0x3]; 1823 u8 reserved_at_24[0x7]; 1824 u8 page_offset[0x5]; 1825 u8 lwm[0x10]; 1826 1827 u8 reserved_at_40[0x8]; 1828 u8 pd[0x18]; 1829 1830 u8 reserved_at_60[0x8]; 1831 u8 uar_page[0x18]; 1832 1833 u8 dbr_addr[0x40]; 1834 1835 u8 hw_counter[0x20]; 1836 1837 u8 sw_counter[0x20]; 1838 1839 u8 reserved_at_100[0xc]; 1840 u8 log_wq_stride[0x4]; 1841 u8 reserved_at_110[0x3]; 1842 u8 log_wq_pg_sz[0x5]; 1843 u8 reserved_at_118[0x3]; 1844 u8 log_wq_sz[0x5]; 1845 1846 u8 dbr_umem_valid[0x1]; 1847 u8 wq_umem_valid[0x1]; 1848 u8 reserved_at_122[0x1]; 1849 u8 log_hairpin_num_packets[0x5]; 1850 u8 reserved_at_128[0x3]; 1851 u8 log_hairpin_data_sz[0x5]; 1852 1853 u8 reserved_at_130[0x4]; 1854 u8 log_wqe_num_of_strides[0x4]; 1855 u8 two_byte_shift_en[0x1]; 1856 u8 reserved_at_139[0x4]; 1857 u8 log_wqe_stride_size[0x3]; 1858 1859 u8 reserved_at_140[0x4c0]; 1860 1861 struct mlx5_ifc_cmd_pas_bits pas[]; 1862 }; 1863 1864 struct mlx5_ifc_rq_num_bits { 1865 u8 reserved_at_0[0x8]; 1866 u8 rq_num[0x18]; 1867 }; 1868 1869 struct mlx5_ifc_mac_address_layout_bits { 1870 u8 reserved_at_0[0x10]; 1871 u8 mac_addr_47_32[0x10]; 1872 1873 u8 mac_addr_31_0[0x20]; 1874 }; 1875 1876 struct mlx5_ifc_vlan_layout_bits { 1877 u8 reserved_at_0[0x14]; 1878 u8 vlan[0x0c]; 1879 1880 u8 reserved_at_20[0x20]; 1881 }; 1882 1883 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits { 1884 u8 reserved_at_0[0xa0]; 1885 1886 u8 min_time_between_cnps[0x20]; 1887 1888 u8 reserved_at_c0[0x12]; 1889 u8 cnp_dscp[0x6]; 1890 u8 reserved_at_d8[0x4]; 1891 u8 cnp_prio_mode[0x1]; 1892 u8 cnp_802p_prio[0x3]; 1893 1894 u8 reserved_at_e0[0x720]; 1895 }; 1896 1897 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits { 1898 u8 reserved_at_0[0x60]; 1899 1900 u8 reserved_at_60[0x4]; 1901 u8 clamp_tgt_rate[0x1]; 1902 u8 reserved_at_65[0x3]; 1903 u8 clamp_tgt_rate_after_time_inc[0x1]; 1904 u8 reserved_at_69[0x17]; 1905 1906 u8 reserved_at_80[0x20]; 1907 1908 u8 rpg_time_reset[0x20]; 1909 1910 u8 rpg_byte_reset[0x20]; 1911 1912 u8 rpg_threshold[0x20]; 1913 1914 u8 rpg_max_rate[0x20]; 1915 1916 u8 rpg_ai_rate[0x20]; 1917 1918 u8 rpg_hai_rate[0x20]; 1919 1920 u8 rpg_gd[0x20]; 1921 1922 u8 rpg_min_dec_fac[0x20]; 1923 1924 u8 rpg_min_rate[0x20]; 1925 1926 u8 reserved_at_1c0[0xe0]; 1927 1928 u8 rate_to_set_on_first_cnp[0x20]; 1929 1930 u8 dce_tcp_g[0x20]; 1931 1932 u8 dce_tcp_rtt[0x20]; 1933 1934 u8 rate_reduce_monitor_period[0x20]; 1935 1936 u8 reserved_at_320[0x20]; 1937 1938 u8 initial_alpha_value[0x20]; 1939 1940 u8 reserved_at_360[0x4a0]; 1941 }; 1942 1943 struct mlx5_ifc_cong_control_802_1qau_rp_bits { 1944 u8 reserved_at_0[0x80]; 1945 1946 u8 rppp_max_rps[0x20]; 1947 1948 u8 rpg_time_reset[0x20]; 1949 1950 u8 rpg_byte_reset[0x20]; 1951 1952 u8 rpg_threshold[0x20]; 1953 1954 u8 rpg_max_rate[0x20]; 1955 1956 u8 rpg_ai_rate[0x20]; 1957 1958 u8 rpg_hai_rate[0x20]; 1959 1960 u8 rpg_gd[0x20]; 1961 1962 u8 rpg_min_dec_fac[0x20]; 1963 1964 u8 rpg_min_rate[0x20]; 1965 1966 u8 reserved_at_1c0[0x640]; 1967 }; 1968 1969 enum { 1970 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1, 1971 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2, 1972 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4, 1973 }; 1974 1975 struct mlx5_ifc_resize_field_select_bits { 1976 u8 resize_field_select[0x20]; 1977 }; 1978 1979 struct mlx5_ifc_resource_dump_bits { 1980 u8 more_dump[0x1]; 1981 u8 inline_dump[0x1]; 1982 u8 reserved_at_2[0xa]; 1983 u8 seq_num[0x4]; 1984 u8 segment_type[0x10]; 1985 1986 u8 reserved_at_20[0x10]; 1987 u8 vhca_id[0x10]; 1988 1989 u8 index1[0x20]; 1990 1991 u8 index2[0x20]; 1992 1993 u8 num_of_obj1[0x10]; 1994 u8 num_of_obj2[0x10]; 1995 1996 u8 reserved_at_a0[0x20]; 1997 1998 u8 device_opaque[0x40]; 1999 2000 u8 mkey[0x20]; 2001 2002 u8 size[0x20]; 2003 2004 u8 address[0x40]; 2005 2006 u8 inline_data[52][0x20]; 2007 }; 2008 2009 struct mlx5_ifc_resource_dump_menu_record_bits { 2010 u8 reserved_at_0[0x4]; 2011 u8 num_of_obj2_supports_active[0x1]; 2012 u8 num_of_obj2_supports_all[0x1]; 2013 u8 must_have_num_of_obj2[0x1]; 2014 u8 support_num_of_obj2[0x1]; 2015 u8 num_of_obj1_supports_active[0x1]; 2016 u8 num_of_obj1_supports_all[0x1]; 2017 u8 must_have_num_of_obj1[0x1]; 2018 u8 support_num_of_obj1[0x1]; 2019 u8 must_have_index2[0x1]; 2020 u8 support_index2[0x1]; 2021 u8 must_have_index1[0x1]; 2022 u8 support_index1[0x1]; 2023 u8 segment_type[0x10]; 2024 2025 u8 segment_name[4][0x20]; 2026 2027 u8 index1_name[4][0x20]; 2028 2029 u8 index2_name[4][0x20]; 2030 }; 2031 2032 struct mlx5_ifc_resource_dump_segment_header_bits { 2033 u8 length_dw[0x10]; 2034 u8 segment_type[0x10]; 2035 }; 2036 2037 struct mlx5_ifc_resource_dump_command_segment_bits { 2038 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2039 2040 u8 segment_called[0x10]; 2041 u8 vhca_id[0x10]; 2042 2043 u8 index1[0x20]; 2044 2045 u8 index2[0x20]; 2046 2047 u8 num_of_obj1[0x10]; 2048 u8 num_of_obj2[0x10]; 2049 }; 2050 2051 struct mlx5_ifc_resource_dump_error_segment_bits { 2052 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2053 2054 u8 reserved_at_20[0x10]; 2055 u8 syndrome_id[0x10]; 2056 2057 u8 reserved_at_40[0x40]; 2058 2059 u8 error[8][0x20]; 2060 }; 2061 2062 struct mlx5_ifc_resource_dump_info_segment_bits { 2063 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2064 2065 u8 reserved_at_20[0x18]; 2066 u8 dump_version[0x8]; 2067 2068 u8 hw_version[0x20]; 2069 2070 u8 fw_version[0x20]; 2071 }; 2072 2073 struct mlx5_ifc_resource_dump_menu_segment_bits { 2074 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2075 2076 u8 reserved_at_20[0x10]; 2077 u8 num_of_records[0x10]; 2078 2079 struct mlx5_ifc_resource_dump_menu_record_bits record[]; 2080 }; 2081 2082 struct mlx5_ifc_resource_dump_resource_segment_bits { 2083 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2084 2085 u8 reserved_at_20[0x20]; 2086 2087 u8 index1[0x20]; 2088 2089 u8 index2[0x20]; 2090 2091 u8 payload[][0x20]; 2092 }; 2093 2094 struct mlx5_ifc_resource_dump_terminate_segment_bits { 2095 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2096 }; 2097 2098 struct mlx5_ifc_menu_resource_dump_response_bits { 2099 struct mlx5_ifc_resource_dump_info_segment_bits info; 2100 struct mlx5_ifc_resource_dump_command_segment_bits cmd; 2101 struct mlx5_ifc_resource_dump_menu_segment_bits menu; 2102 struct mlx5_ifc_resource_dump_terminate_segment_bits terminate; 2103 }; 2104 2105 enum { 2106 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1, 2107 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2, 2108 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4, 2109 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8, 2110 }; 2111 2112 struct mlx5_ifc_modify_field_select_bits { 2113 u8 modify_field_select[0x20]; 2114 }; 2115 2116 struct mlx5_ifc_field_select_r_roce_np_bits { 2117 u8 field_select_r_roce_np[0x20]; 2118 }; 2119 2120 struct mlx5_ifc_field_select_r_roce_rp_bits { 2121 u8 field_select_r_roce_rp[0x20]; 2122 }; 2123 2124 enum { 2125 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4, 2126 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8, 2127 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10, 2128 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20, 2129 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40, 2130 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80, 2131 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100, 2132 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200, 2133 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400, 2134 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800, 2135 }; 2136 2137 struct mlx5_ifc_field_select_802_1qau_rp_bits { 2138 u8 field_select_8021qaurp[0x20]; 2139 }; 2140 2141 struct mlx5_ifc_phys_layer_cntrs_bits { 2142 u8 time_since_last_clear_high[0x20]; 2143 2144 u8 time_since_last_clear_low[0x20]; 2145 2146 u8 symbol_errors_high[0x20]; 2147 2148 u8 symbol_errors_low[0x20]; 2149 2150 u8 sync_headers_errors_high[0x20]; 2151 2152 u8 sync_headers_errors_low[0x20]; 2153 2154 u8 edpl_bip_errors_lane0_high[0x20]; 2155 2156 u8 edpl_bip_errors_lane0_low[0x20]; 2157 2158 u8 edpl_bip_errors_lane1_high[0x20]; 2159 2160 u8 edpl_bip_errors_lane1_low[0x20]; 2161 2162 u8 edpl_bip_errors_lane2_high[0x20]; 2163 2164 u8 edpl_bip_errors_lane2_low[0x20]; 2165 2166 u8 edpl_bip_errors_lane3_high[0x20]; 2167 2168 u8 edpl_bip_errors_lane3_low[0x20]; 2169 2170 u8 fc_fec_corrected_blocks_lane0_high[0x20]; 2171 2172 u8 fc_fec_corrected_blocks_lane0_low[0x20]; 2173 2174 u8 fc_fec_corrected_blocks_lane1_high[0x20]; 2175 2176 u8 fc_fec_corrected_blocks_lane1_low[0x20]; 2177 2178 u8 fc_fec_corrected_blocks_lane2_high[0x20]; 2179 2180 u8 fc_fec_corrected_blocks_lane2_low[0x20]; 2181 2182 u8 fc_fec_corrected_blocks_lane3_high[0x20]; 2183 2184 u8 fc_fec_corrected_blocks_lane3_low[0x20]; 2185 2186 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20]; 2187 2188 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20]; 2189 2190 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20]; 2191 2192 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20]; 2193 2194 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20]; 2195 2196 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20]; 2197 2198 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20]; 2199 2200 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20]; 2201 2202 u8 rs_fec_corrected_blocks_high[0x20]; 2203 2204 u8 rs_fec_corrected_blocks_low[0x20]; 2205 2206 u8 rs_fec_uncorrectable_blocks_high[0x20]; 2207 2208 u8 rs_fec_uncorrectable_blocks_low[0x20]; 2209 2210 u8 rs_fec_no_errors_blocks_high[0x20]; 2211 2212 u8 rs_fec_no_errors_blocks_low[0x20]; 2213 2214 u8 rs_fec_single_error_blocks_high[0x20]; 2215 2216 u8 rs_fec_single_error_blocks_low[0x20]; 2217 2218 u8 rs_fec_corrected_symbols_total_high[0x20]; 2219 2220 u8 rs_fec_corrected_symbols_total_low[0x20]; 2221 2222 u8 rs_fec_corrected_symbols_lane0_high[0x20]; 2223 2224 u8 rs_fec_corrected_symbols_lane0_low[0x20]; 2225 2226 u8 rs_fec_corrected_symbols_lane1_high[0x20]; 2227 2228 u8 rs_fec_corrected_symbols_lane1_low[0x20]; 2229 2230 u8 rs_fec_corrected_symbols_lane2_high[0x20]; 2231 2232 u8 rs_fec_corrected_symbols_lane2_low[0x20]; 2233 2234 u8 rs_fec_corrected_symbols_lane3_high[0x20]; 2235 2236 u8 rs_fec_corrected_symbols_lane3_low[0x20]; 2237 2238 u8 link_down_events[0x20]; 2239 2240 u8 successful_recovery_events[0x20]; 2241 2242 u8 reserved_at_640[0x180]; 2243 }; 2244 2245 struct mlx5_ifc_phys_layer_statistical_cntrs_bits { 2246 u8 time_since_last_clear_high[0x20]; 2247 2248 u8 time_since_last_clear_low[0x20]; 2249 2250 u8 phy_received_bits_high[0x20]; 2251 2252 u8 phy_received_bits_low[0x20]; 2253 2254 u8 phy_symbol_errors_high[0x20]; 2255 2256 u8 phy_symbol_errors_low[0x20]; 2257 2258 u8 phy_corrected_bits_high[0x20]; 2259 2260 u8 phy_corrected_bits_low[0x20]; 2261 2262 u8 phy_corrected_bits_lane0_high[0x20]; 2263 2264 u8 phy_corrected_bits_lane0_low[0x20]; 2265 2266 u8 phy_corrected_bits_lane1_high[0x20]; 2267 2268 u8 phy_corrected_bits_lane1_low[0x20]; 2269 2270 u8 phy_corrected_bits_lane2_high[0x20]; 2271 2272 u8 phy_corrected_bits_lane2_low[0x20]; 2273 2274 u8 phy_corrected_bits_lane3_high[0x20]; 2275 2276 u8 phy_corrected_bits_lane3_low[0x20]; 2277 2278 u8 reserved_at_200[0x5c0]; 2279 }; 2280 2281 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits { 2282 u8 symbol_error_counter[0x10]; 2283 2284 u8 link_error_recovery_counter[0x8]; 2285 2286 u8 link_downed_counter[0x8]; 2287 2288 u8 port_rcv_errors[0x10]; 2289 2290 u8 port_rcv_remote_physical_errors[0x10]; 2291 2292 u8 port_rcv_switch_relay_errors[0x10]; 2293 2294 u8 port_xmit_discards[0x10]; 2295 2296 u8 port_xmit_constraint_errors[0x8]; 2297 2298 u8 port_rcv_constraint_errors[0x8]; 2299 2300 u8 reserved_at_70[0x8]; 2301 2302 u8 link_overrun_errors[0x8]; 2303 2304 u8 reserved_at_80[0x10]; 2305 2306 u8 vl_15_dropped[0x10]; 2307 2308 u8 reserved_at_a0[0x80]; 2309 2310 u8 port_xmit_wait[0x20]; 2311 }; 2312 2313 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits { 2314 u8 transmit_queue_high[0x20]; 2315 2316 u8 transmit_queue_low[0x20]; 2317 2318 u8 no_buffer_discard_uc_high[0x20]; 2319 2320 u8 no_buffer_discard_uc_low[0x20]; 2321 2322 u8 reserved_at_80[0x740]; 2323 }; 2324 2325 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits { 2326 u8 wred_discard_high[0x20]; 2327 2328 u8 wred_discard_low[0x20]; 2329 2330 u8 ecn_marked_tc_high[0x20]; 2331 2332 u8 ecn_marked_tc_low[0x20]; 2333 2334 u8 reserved_at_80[0x740]; 2335 }; 2336 2337 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits { 2338 u8 rx_octets_high[0x20]; 2339 2340 u8 rx_octets_low[0x20]; 2341 2342 u8 reserved_at_40[0xc0]; 2343 2344 u8 rx_frames_high[0x20]; 2345 2346 u8 rx_frames_low[0x20]; 2347 2348 u8 tx_octets_high[0x20]; 2349 2350 u8 tx_octets_low[0x20]; 2351 2352 u8 reserved_at_180[0xc0]; 2353 2354 u8 tx_frames_high[0x20]; 2355 2356 u8 tx_frames_low[0x20]; 2357 2358 u8 rx_pause_high[0x20]; 2359 2360 u8 rx_pause_low[0x20]; 2361 2362 u8 rx_pause_duration_high[0x20]; 2363 2364 u8 rx_pause_duration_low[0x20]; 2365 2366 u8 tx_pause_high[0x20]; 2367 2368 u8 tx_pause_low[0x20]; 2369 2370 u8 tx_pause_duration_high[0x20]; 2371 2372 u8 tx_pause_duration_low[0x20]; 2373 2374 u8 rx_pause_transition_high[0x20]; 2375 2376 u8 rx_pause_transition_low[0x20]; 2377 2378 u8 rx_discards_high[0x20]; 2379 2380 u8 rx_discards_low[0x20]; 2381 2382 u8 device_stall_minor_watermark_cnt_high[0x20]; 2383 2384 u8 device_stall_minor_watermark_cnt_low[0x20]; 2385 2386 u8 device_stall_critical_watermark_cnt_high[0x20]; 2387 2388 u8 device_stall_critical_watermark_cnt_low[0x20]; 2389 2390 u8 reserved_at_480[0x340]; 2391 }; 2392 2393 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits { 2394 u8 port_transmit_wait_high[0x20]; 2395 2396 u8 port_transmit_wait_low[0x20]; 2397 2398 u8 reserved_at_40[0x100]; 2399 2400 u8 rx_buffer_almost_full_high[0x20]; 2401 2402 u8 rx_buffer_almost_full_low[0x20]; 2403 2404 u8 rx_buffer_full_high[0x20]; 2405 2406 u8 rx_buffer_full_low[0x20]; 2407 2408 u8 rx_icrc_encapsulated_high[0x20]; 2409 2410 u8 rx_icrc_encapsulated_low[0x20]; 2411 2412 u8 reserved_at_200[0x5c0]; 2413 }; 2414 2415 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits { 2416 u8 dot3stats_alignment_errors_high[0x20]; 2417 2418 u8 dot3stats_alignment_errors_low[0x20]; 2419 2420 u8 dot3stats_fcs_errors_high[0x20]; 2421 2422 u8 dot3stats_fcs_errors_low[0x20]; 2423 2424 u8 dot3stats_single_collision_frames_high[0x20]; 2425 2426 u8 dot3stats_single_collision_frames_low[0x20]; 2427 2428 u8 dot3stats_multiple_collision_frames_high[0x20]; 2429 2430 u8 dot3stats_multiple_collision_frames_low[0x20]; 2431 2432 u8 dot3stats_sqe_test_errors_high[0x20]; 2433 2434 u8 dot3stats_sqe_test_errors_low[0x20]; 2435 2436 u8 dot3stats_deferred_transmissions_high[0x20]; 2437 2438 u8 dot3stats_deferred_transmissions_low[0x20]; 2439 2440 u8 dot3stats_late_collisions_high[0x20]; 2441 2442 u8 dot3stats_late_collisions_low[0x20]; 2443 2444 u8 dot3stats_excessive_collisions_high[0x20]; 2445 2446 u8 dot3stats_excessive_collisions_low[0x20]; 2447 2448 u8 dot3stats_internal_mac_transmit_errors_high[0x20]; 2449 2450 u8 dot3stats_internal_mac_transmit_errors_low[0x20]; 2451 2452 u8 dot3stats_carrier_sense_errors_high[0x20]; 2453 2454 u8 dot3stats_carrier_sense_errors_low[0x20]; 2455 2456 u8 dot3stats_frame_too_longs_high[0x20]; 2457 2458 u8 dot3stats_frame_too_longs_low[0x20]; 2459 2460 u8 dot3stats_internal_mac_receive_errors_high[0x20]; 2461 2462 u8 dot3stats_internal_mac_receive_errors_low[0x20]; 2463 2464 u8 dot3stats_symbol_errors_high[0x20]; 2465 2466 u8 dot3stats_symbol_errors_low[0x20]; 2467 2468 u8 dot3control_in_unknown_opcodes_high[0x20]; 2469 2470 u8 dot3control_in_unknown_opcodes_low[0x20]; 2471 2472 u8 dot3in_pause_frames_high[0x20]; 2473 2474 u8 dot3in_pause_frames_low[0x20]; 2475 2476 u8 dot3out_pause_frames_high[0x20]; 2477 2478 u8 dot3out_pause_frames_low[0x20]; 2479 2480 u8 reserved_at_400[0x3c0]; 2481 }; 2482 2483 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits { 2484 u8 ether_stats_drop_events_high[0x20]; 2485 2486 u8 ether_stats_drop_events_low[0x20]; 2487 2488 u8 ether_stats_octets_high[0x20]; 2489 2490 u8 ether_stats_octets_low[0x20]; 2491 2492 u8 ether_stats_pkts_high[0x20]; 2493 2494 u8 ether_stats_pkts_low[0x20]; 2495 2496 u8 ether_stats_broadcast_pkts_high[0x20]; 2497 2498 u8 ether_stats_broadcast_pkts_low[0x20]; 2499 2500 u8 ether_stats_multicast_pkts_high[0x20]; 2501 2502 u8 ether_stats_multicast_pkts_low[0x20]; 2503 2504 u8 ether_stats_crc_align_errors_high[0x20]; 2505 2506 u8 ether_stats_crc_align_errors_low[0x20]; 2507 2508 u8 ether_stats_undersize_pkts_high[0x20]; 2509 2510 u8 ether_stats_undersize_pkts_low[0x20]; 2511 2512 u8 ether_stats_oversize_pkts_high[0x20]; 2513 2514 u8 ether_stats_oversize_pkts_low[0x20]; 2515 2516 u8 ether_stats_fragments_high[0x20]; 2517 2518 u8 ether_stats_fragments_low[0x20]; 2519 2520 u8 ether_stats_jabbers_high[0x20]; 2521 2522 u8 ether_stats_jabbers_low[0x20]; 2523 2524 u8 ether_stats_collisions_high[0x20]; 2525 2526 u8 ether_stats_collisions_low[0x20]; 2527 2528 u8 ether_stats_pkts64octets_high[0x20]; 2529 2530 u8 ether_stats_pkts64octets_low[0x20]; 2531 2532 u8 ether_stats_pkts65to127octets_high[0x20]; 2533 2534 u8 ether_stats_pkts65to127octets_low[0x20]; 2535 2536 u8 ether_stats_pkts128to255octets_high[0x20]; 2537 2538 u8 ether_stats_pkts128to255octets_low[0x20]; 2539 2540 u8 ether_stats_pkts256to511octets_high[0x20]; 2541 2542 u8 ether_stats_pkts256to511octets_low[0x20]; 2543 2544 u8 ether_stats_pkts512to1023octets_high[0x20]; 2545 2546 u8 ether_stats_pkts512to1023octets_low[0x20]; 2547 2548 u8 ether_stats_pkts1024to1518octets_high[0x20]; 2549 2550 u8 ether_stats_pkts1024to1518octets_low[0x20]; 2551 2552 u8 ether_stats_pkts1519to2047octets_high[0x20]; 2553 2554 u8 ether_stats_pkts1519to2047octets_low[0x20]; 2555 2556 u8 ether_stats_pkts2048to4095octets_high[0x20]; 2557 2558 u8 ether_stats_pkts2048to4095octets_low[0x20]; 2559 2560 u8 ether_stats_pkts4096to8191octets_high[0x20]; 2561 2562 u8 ether_stats_pkts4096to8191octets_low[0x20]; 2563 2564 u8 ether_stats_pkts8192to10239octets_high[0x20]; 2565 2566 u8 ether_stats_pkts8192to10239octets_low[0x20]; 2567 2568 u8 reserved_at_540[0x280]; 2569 }; 2570 2571 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits { 2572 u8 if_in_octets_high[0x20]; 2573 2574 u8 if_in_octets_low[0x20]; 2575 2576 u8 if_in_ucast_pkts_high[0x20]; 2577 2578 u8 if_in_ucast_pkts_low[0x20]; 2579 2580 u8 if_in_discards_high[0x20]; 2581 2582 u8 if_in_discards_low[0x20]; 2583 2584 u8 if_in_errors_high[0x20]; 2585 2586 u8 if_in_errors_low[0x20]; 2587 2588 u8 if_in_unknown_protos_high[0x20]; 2589 2590 u8 if_in_unknown_protos_low[0x20]; 2591 2592 u8 if_out_octets_high[0x20]; 2593 2594 u8 if_out_octets_low[0x20]; 2595 2596 u8 if_out_ucast_pkts_high[0x20]; 2597 2598 u8 if_out_ucast_pkts_low[0x20]; 2599 2600 u8 if_out_discards_high[0x20]; 2601 2602 u8 if_out_discards_low[0x20]; 2603 2604 u8 if_out_errors_high[0x20]; 2605 2606 u8 if_out_errors_low[0x20]; 2607 2608 u8 if_in_multicast_pkts_high[0x20]; 2609 2610 u8 if_in_multicast_pkts_low[0x20]; 2611 2612 u8 if_in_broadcast_pkts_high[0x20]; 2613 2614 u8 if_in_broadcast_pkts_low[0x20]; 2615 2616 u8 if_out_multicast_pkts_high[0x20]; 2617 2618 u8 if_out_multicast_pkts_low[0x20]; 2619 2620 u8 if_out_broadcast_pkts_high[0x20]; 2621 2622 u8 if_out_broadcast_pkts_low[0x20]; 2623 2624 u8 reserved_at_340[0x480]; 2625 }; 2626 2627 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits { 2628 u8 a_frames_transmitted_ok_high[0x20]; 2629 2630 u8 a_frames_transmitted_ok_low[0x20]; 2631 2632 u8 a_frames_received_ok_high[0x20]; 2633 2634 u8 a_frames_received_ok_low[0x20]; 2635 2636 u8 a_frame_check_sequence_errors_high[0x20]; 2637 2638 u8 a_frame_check_sequence_errors_low[0x20]; 2639 2640 u8 a_alignment_errors_high[0x20]; 2641 2642 u8 a_alignment_errors_low[0x20]; 2643 2644 u8 a_octets_transmitted_ok_high[0x20]; 2645 2646 u8 a_octets_transmitted_ok_low[0x20]; 2647 2648 u8 a_octets_received_ok_high[0x20]; 2649 2650 u8 a_octets_received_ok_low[0x20]; 2651 2652 u8 a_multicast_frames_xmitted_ok_high[0x20]; 2653 2654 u8 a_multicast_frames_xmitted_ok_low[0x20]; 2655 2656 u8 a_broadcast_frames_xmitted_ok_high[0x20]; 2657 2658 u8 a_broadcast_frames_xmitted_ok_low[0x20]; 2659 2660 u8 a_multicast_frames_received_ok_high[0x20]; 2661 2662 u8 a_multicast_frames_received_ok_low[0x20]; 2663 2664 u8 a_broadcast_frames_received_ok_high[0x20]; 2665 2666 u8 a_broadcast_frames_received_ok_low[0x20]; 2667 2668 u8 a_in_range_length_errors_high[0x20]; 2669 2670 u8 a_in_range_length_errors_low[0x20]; 2671 2672 u8 a_out_of_range_length_field_high[0x20]; 2673 2674 u8 a_out_of_range_length_field_low[0x20]; 2675 2676 u8 a_frame_too_long_errors_high[0x20]; 2677 2678 u8 a_frame_too_long_errors_low[0x20]; 2679 2680 u8 a_symbol_error_during_carrier_high[0x20]; 2681 2682 u8 a_symbol_error_during_carrier_low[0x20]; 2683 2684 u8 a_mac_control_frames_transmitted_high[0x20]; 2685 2686 u8 a_mac_control_frames_transmitted_low[0x20]; 2687 2688 u8 a_mac_control_frames_received_high[0x20]; 2689 2690 u8 a_mac_control_frames_received_low[0x20]; 2691 2692 u8 a_unsupported_opcodes_received_high[0x20]; 2693 2694 u8 a_unsupported_opcodes_received_low[0x20]; 2695 2696 u8 a_pause_mac_ctrl_frames_received_high[0x20]; 2697 2698 u8 a_pause_mac_ctrl_frames_received_low[0x20]; 2699 2700 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20]; 2701 2702 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20]; 2703 2704 u8 reserved_at_4c0[0x300]; 2705 }; 2706 2707 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits { 2708 u8 life_time_counter_high[0x20]; 2709 2710 u8 life_time_counter_low[0x20]; 2711 2712 u8 rx_errors[0x20]; 2713 2714 u8 tx_errors[0x20]; 2715 2716 u8 l0_to_recovery_eieos[0x20]; 2717 2718 u8 l0_to_recovery_ts[0x20]; 2719 2720 u8 l0_to_recovery_framing[0x20]; 2721 2722 u8 l0_to_recovery_retrain[0x20]; 2723 2724 u8 crc_error_dllp[0x20]; 2725 2726 u8 crc_error_tlp[0x20]; 2727 2728 u8 tx_overflow_buffer_pkt_high[0x20]; 2729 2730 u8 tx_overflow_buffer_pkt_low[0x20]; 2731 2732 u8 outbound_stalled_reads[0x20]; 2733 2734 u8 outbound_stalled_writes[0x20]; 2735 2736 u8 outbound_stalled_reads_events[0x20]; 2737 2738 u8 outbound_stalled_writes_events[0x20]; 2739 2740 u8 reserved_at_200[0x5c0]; 2741 }; 2742 2743 struct mlx5_ifc_cmd_inter_comp_event_bits { 2744 u8 command_completion_vector[0x20]; 2745 2746 u8 reserved_at_20[0xc0]; 2747 }; 2748 2749 struct mlx5_ifc_stall_vl_event_bits { 2750 u8 reserved_at_0[0x18]; 2751 u8 port_num[0x1]; 2752 u8 reserved_at_19[0x3]; 2753 u8 vl[0x4]; 2754 2755 u8 reserved_at_20[0xa0]; 2756 }; 2757 2758 struct mlx5_ifc_db_bf_congestion_event_bits { 2759 u8 event_subtype[0x8]; 2760 u8 reserved_at_8[0x8]; 2761 u8 congestion_level[0x8]; 2762 u8 reserved_at_18[0x8]; 2763 2764 u8 reserved_at_20[0xa0]; 2765 }; 2766 2767 struct mlx5_ifc_gpio_event_bits { 2768 u8 reserved_at_0[0x60]; 2769 2770 u8 gpio_event_hi[0x20]; 2771 2772 u8 gpio_event_lo[0x20]; 2773 2774 u8 reserved_at_a0[0x40]; 2775 }; 2776 2777 struct mlx5_ifc_port_state_change_event_bits { 2778 u8 reserved_at_0[0x40]; 2779 2780 u8 port_num[0x4]; 2781 u8 reserved_at_44[0x1c]; 2782 2783 u8 reserved_at_60[0x80]; 2784 }; 2785 2786 struct mlx5_ifc_dropped_packet_logged_bits { 2787 u8 reserved_at_0[0xe0]; 2788 }; 2789 2790 enum { 2791 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1, 2792 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2, 2793 }; 2794 2795 struct mlx5_ifc_cq_error_bits { 2796 u8 reserved_at_0[0x8]; 2797 u8 cqn[0x18]; 2798 2799 u8 reserved_at_20[0x20]; 2800 2801 u8 reserved_at_40[0x18]; 2802 u8 syndrome[0x8]; 2803 2804 u8 reserved_at_60[0x80]; 2805 }; 2806 2807 struct mlx5_ifc_rdma_page_fault_event_bits { 2808 u8 bytes_committed[0x20]; 2809 2810 u8 r_key[0x20]; 2811 2812 u8 reserved_at_40[0x10]; 2813 u8 packet_len[0x10]; 2814 2815 u8 rdma_op_len[0x20]; 2816 2817 u8 rdma_va[0x40]; 2818 2819 u8 reserved_at_c0[0x5]; 2820 u8 rdma[0x1]; 2821 u8 write[0x1]; 2822 u8 requestor[0x1]; 2823 u8 qp_number[0x18]; 2824 }; 2825 2826 struct mlx5_ifc_wqe_associated_page_fault_event_bits { 2827 u8 bytes_committed[0x20]; 2828 2829 u8 reserved_at_20[0x10]; 2830 u8 wqe_index[0x10]; 2831 2832 u8 reserved_at_40[0x10]; 2833 u8 len[0x10]; 2834 2835 u8 reserved_at_60[0x60]; 2836 2837 u8 reserved_at_c0[0x5]; 2838 u8 rdma[0x1]; 2839 u8 write_read[0x1]; 2840 u8 requestor[0x1]; 2841 u8 qpn[0x18]; 2842 }; 2843 2844 struct mlx5_ifc_qp_events_bits { 2845 u8 reserved_at_0[0xa0]; 2846 2847 u8 type[0x8]; 2848 u8 reserved_at_a8[0x18]; 2849 2850 u8 reserved_at_c0[0x8]; 2851 u8 qpn_rqn_sqn[0x18]; 2852 }; 2853 2854 struct mlx5_ifc_dct_events_bits { 2855 u8 reserved_at_0[0xc0]; 2856 2857 u8 reserved_at_c0[0x8]; 2858 u8 dct_number[0x18]; 2859 }; 2860 2861 struct mlx5_ifc_comp_event_bits { 2862 u8 reserved_at_0[0xc0]; 2863 2864 u8 reserved_at_c0[0x8]; 2865 u8 cq_number[0x18]; 2866 }; 2867 2868 enum { 2869 MLX5_QPC_STATE_RST = 0x0, 2870 MLX5_QPC_STATE_INIT = 0x1, 2871 MLX5_QPC_STATE_RTR = 0x2, 2872 MLX5_QPC_STATE_RTS = 0x3, 2873 MLX5_QPC_STATE_SQER = 0x4, 2874 MLX5_QPC_STATE_ERR = 0x6, 2875 MLX5_QPC_STATE_SQD = 0x7, 2876 MLX5_QPC_STATE_SUSPENDED = 0x9, 2877 }; 2878 2879 enum { 2880 MLX5_QPC_ST_RC = 0x0, 2881 MLX5_QPC_ST_UC = 0x1, 2882 MLX5_QPC_ST_UD = 0x2, 2883 MLX5_QPC_ST_XRC = 0x3, 2884 MLX5_QPC_ST_DCI = 0x5, 2885 MLX5_QPC_ST_QP0 = 0x7, 2886 MLX5_QPC_ST_QP1 = 0x8, 2887 MLX5_QPC_ST_RAW_DATAGRAM = 0x9, 2888 MLX5_QPC_ST_REG_UMR = 0xc, 2889 }; 2890 2891 enum { 2892 MLX5_QPC_PM_STATE_ARMED = 0x0, 2893 MLX5_QPC_PM_STATE_REARM = 0x1, 2894 MLX5_QPC_PM_STATE_RESERVED = 0x2, 2895 MLX5_QPC_PM_STATE_MIGRATED = 0x3, 2896 }; 2897 2898 enum { 2899 MLX5_QPC_OFFLOAD_TYPE_RNDV = 0x1, 2900 }; 2901 2902 enum { 2903 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0, 2904 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1, 2905 }; 2906 2907 enum { 2908 MLX5_QPC_MTU_256_BYTES = 0x1, 2909 MLX5_QPC_MTU_512_BYTES = 0x2, 2910 MLX5_QPC_MTU_1K_BYTES = 0x3, 2911 MLX5_QPC_MTU_2K_BYTES = 0x4, 2912 MLX5_QPC_MTU_4K_BYTES = 0x5, 2913 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7, 2914 }; 2915 2916 enum { 2917 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1, 2918 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2, 2919 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3, 2920 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4, 2921 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5, 2922 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6, 2923 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7, 2924 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8, 2925 }; 2926 2927 enum { 2928 MLX5_QPC_CS_REQ_DISABLE = 0x0, 2929 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11, 2930 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22, 2931 }; 2932 2933 enum { 2934 MLX5_QPC_CS_RES_DISABLE = 0x0, 2935 MLX5_QPC_CS_RES_UP_TO_32B = 0x1, 2936 MLX5_QPC_CS_RES_UP_TO_64B = 0x2, 2937 }; 2938 2939 enum { 2940 MLX5_QPC_TIMESTAMP_FORMAT_FREE_RUNNING = 0x0, 2941 MLX5_QPC_TIMESTAMP_FORMAT_DEFAULT = 0x1, 2942 MLX5_QPC_TIMESTAMP_FORMAT_REAL_TIME = 0x2, 2943 }; 2944 2945 struct mlx5_ifc_qpc_bits { 2946 u8 state[0x4]; 2947 u8 lag_tx_port_affinity[0x4]; 2948 u8 st[0x8]; 2949 u8 reserved_at_10[0x2]; 2950 u8 isolate_vl_tc[0x1]; 2951 u8 pm_state[0x2]; 2952 u8 reserved_at_15[0x1]; 2953 u8 req_e2e_credit_mode[0x2]; 2954 u8 offload_type[0x4]; 2955 u8 end_padding_mode[0x2]; 2956 u8 reserved_at_1e[0x2]; 2957 2958 u8 wq_signature[0x1]; 2959 u8 block_lb_mc[0x1]; 2960 u8 atomic_like_write_en[0x1]; 2961 u8 latency_sensitive[0x1]; 2962 u8 reserved_at_24[0x1]; 2963 u8 drain_sigerr[0x1]; 2964 u8 reserved_at_26[0x2]; 2965 u8 pd[0x18]; 2966 2967 u8 mtu[0x3]; 2968 u8 log_msg_max[0x5]; 2969 u8 reserved_at_48[0x1]; 2970 u8 log_rq_size[0x4]; 2971 u8 log_rq_stride[0x3]; 2972 u8 no_sq[0x1]; 2973 u8 log_sq_size[0x4]; 2974 u8 reserved_at_55[0x3]; 2975 u8 ts_format[0x2]; 2976 u8 reserved_at_5a[0x1]; 2977 u8 rlky[0x1]; 2978 u8 ulp_stateless_offload_mode[0x4]; 2979 2980 u8 counter_set_id[0x8]; 2981 u8 uar_page[0x18]; 2982 2983 u8 reserved_at_80[0x8]; 2984 u8 user_index[0x18]; 2985 2986 u8 reserved_at_a0[0x3]; 2987 u8 log_page_size[0x5]; 2988 u8 remote_qpn[0x18]; 2989 2990 struct mlx5_ifc_ads_bits primary_address_path; 2991 2992 struct mlx5_ifc_ads_bits secondary_address_path; 2993 2994 u8 log_ack_req_freq[0x4]; 2995 u8 reserved_at_384[0x4]; 2996 u8 log_sra_max[0x3]; 2997 u8 reserved_at_38b[0x2]; 2998 u8 retry_count[0x3]; 2999 u8 rnr_retry[0x3]; 3000 u8 reserved_at_393[0x1]; 3001 u8 fre[0x1]; 3002 u8 cur_rnr_retry[0x3]; 3003 u8 cur_retry_count[0x3]; 3004 u8 reserved_at_39b[0x5]; 3005 3006 u8 reserved_at_3a0[0x20]; 3007 3008 u8 reserved_at_3c0[0x8]; 3009 u8 next_send_psn[0x18]; 3010 3011 u8 reserved_at_3e0[0x8]; 3012 u8 cqn_snd[0x18]; 3013 3014 u8 reserved_at_400[0x8]; 3015 u8 deth_sqpn[0x18]; 3016 3017 u8 reserved_at_420[0x20]; 3018 3019 u8 reserved_at_440[0x8]; 3020 u8 last_acked_psn[0x18]; 3021 3022 u8 reserved_at_460[0x8]; 3023 u8 ssn[0x18]; 3024 3025 u8 reserved_at_480[0x8]; 3026 u8 log_rra_max[0x3]; 3027 u8 reserved_at_48b[0x1]; 3028 u8 atomic_mode[0x4]; 3029 u8 rre[0x1]; 3030 u8 rwe[0x1]; 3031 u8 rae[0x1]; 3032 u8 reserved_at_493[0x1]; 3033 u8 page_offset[0x6]; 3034 u8 reserved_at_49a[0x3]; 3035 u8 cd_slave_receive[0x1]; 3036 u8 cd_slave_send[0x1]; 3037 u8 cd_master[0x1]; 3038 3039 u8 reserved_at_4a0[0x3]; 3040 u8 min_rnr_nak[0x5]; 3041 u8 next_rcv_psn[0x18]; 3042 3043 u8 reserved_at_4c0[0x8]; 3044 u8 xrcd[0x18]; 3045 3046 u8 reserved_at_4e0[0x8]; 3047 u8 cqn_rcv[0x18]; 3048 3049 u8 dbr_addr[0x40]; 3050 3051 u8 q_key[0x20]; 3052 3053 u8 reserved_at_560[0x5]; 3054 u8 rq_type[0x3]; 3055 u8 srqn_rmpn_xrqn[0x18]; 3056 3057 u8 reserved_at_580[0x8]; 3058 u8 rmsn[0x18]; 3059 3060 u8 hw_sq_wqebb_counter[0x10]; 3061 u8 sw_sq_wqebb_counter[0x10]; 3062 3063 u8 hw_rq_counter[0x20]; 3064 3065 u8 sw_rq_counter[0x20]; 3066 3067 u8 reserved_at_600[0x20]; 3068 3069 u8 reserved_at_620[0xf]; 3070 u8 cgs[0x1]; 3071 u8 cs_req[0x8]; 3072 u8 cs_res[0x8]; 3073 3074 u8 dc_access_key[0x40]; 3075 3076 u8 reserved_at_680[0x3]; 3077 u8 dbr_umem_valid[0x1]; 3078 3079 u8 reserved_at_684[0xbc]; 3080 }; 3081 3082 struct mlx5_ifc_roce_addr_layout_bits { 3083 u8 source_l3_address[16][0x8]; 3084 3085 u8 reserved_at_80[0x3]; 3086 u8 vlan_valid[0x1]; 3087 u8 vlan_id[0xc]; 3088 u8 source_mac_47_32[0x10]; 3089 3090 u8 source_mac_31_0[0x20]; 3091 3092 u8 reserved_at_c0[0x14]; 3093 u8 roce_l3_type[0x4]; 3094 u8 roce_version[0x8]; 3095 3096 u8 reserved_at_e0[0x20]; 3097 }; 3098 3099 union mlx5_ifc_hca_cap_union_bits { 3100 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap; 3101 struct mlx5_ifc_odp_cap_bits odp_cap; 3102 struct mlx5_ifc_atomic_caps_bits atomic_caps; 3103 struct mlx5_ifc_roce_cap_bits roce_cap; 3104 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps; 3105 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap; 3106 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap; 3107 struct mlx5_ifc_e_switch_cap_bits e_switch_cap; 3108 struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap; 3109 struct mlx5_ifc_qos_cap_bits qos_cap; 3110 struct mlx5_ifc_debug_cap_bits debug_cap; 3111 struct mlx5_ifc_fpga_cap_bits fpga_cap; 3112 struct mlx5_ifc_tls_cap_bits tls_cap; 3113 struct mlx5_ifc_device_mem_cap_bits device_mem_cap; 3114 struct mlx5_ifc_virtio_emulation_cap_bits virtio_emulation_cap; 3115 u8 reserved_at_0[0x8000]; 3116 }; 3117 3118 enum { 3119 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1, 3120 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2, 3121 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4, 3122 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8, 3123 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT = 0x10, 3124 MLX5_FLOW_CONTEXT_ACTION_DECAP = 0x20, 3125 MLX5_FLOW_CONTEXT_ACTION_MOD_HDR = 0x40, 3126 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP = 0x80, 3127 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100, 3128 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2 = 0x400, 3129 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2 = 0x800, 3130 MLX5_FLOW_CONTEXT_ACTION_IPSEC_DECRYPT = 0x1000, 3131 MLX5_FLOW_CONTEXT_ACTION_IPSEC_ENCRYPT = 0x2000, 3132 }; 3133 3134 enum { 3135 MLX5_FLOW_CONTEXT_FLOW_SOURCE_ANY_VPORT = 0x0, 3136 MLX5_FLOW_CONTEXT_FLOW_SOURCE_UPLINK = 0x1, 3137 MLX5_FLOW_CONTEXT_FLOW_SOURCE_LOCAL_VPORT = 0x2, 3138 }; 3139 3140 struct mlx5_ifc_vlan_bits { 3141 u8 ethtype[0x10]; 3142 u8 prio[0x3]; 3143 u8 cfi[0x1]; 3144 u8 vid[0xc]; 3145 }; 3146 3147 struct mlx5_ifc_flow_context_bits { 3148 struct mlx5_ifc_vlan_bits push_vlan; 3149 3150 u8 group_id[0x20]; 3151 3152 u8 reserved_at_40[0x8]; 3153 u8 flow_tag[0x18]; 3154 3155 u8 reserved_at_60[0x10]; 3156 u8 action[0x10]; 3157 3158 u8 extended_destination[0x1]; 3159 u8 reserved_at_81[0x1]; 3160 u8 flow_source[0x2]; 3161 u8 reserved_at_84[0x4]; 3162 u8 destination_list_size[0x18]; 3163 3164 u8 reserved_at_a0[0x8]; 3165 u8 flow_counter_list_size[0x18]; 3166 3167 u8 packet_reformat_id[0x20]; 3168 3169 u8 modify_header_id[0x20]; 3170 3171 struct mlx5_ifc_vlan_bits push_vlan_2; 3172 3173 u8 ipsec_obj_id[0x20]; 3174 u8 reserved_at_140[0xc0]; 3175 3176 struct mlx5_ifc_fte_match_param_bits match_value; 3177 3178 u8 reserved_at_1200[0x600]; 3179 3180 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[]; 3181 }; 3182 3183 enum { 3184 MLX5_XRC_SRQC_STATE_GOOD = 0x0, 3185 MLX5_XRC_SRQC_STATE_ERROR = 0x1, 3186 }; 3187 3188 struct mlx5_ifc_xrc_srqc_bits { 3189 u8 state[0x4]; 3190 u8 log_xrc_srq_size[0x4]; 3191 u8 reserved_at_8[0x18]; 3192 3193 u8 wq_signature[0x1]; 3194 u8 cont_srq[0x1]; 3195 u8 reserved_at_22[0x1]; 3196 u8 rlky[0x1]; 3197 u8 basic_cyclic_rcv_wqe[0x1]; 3198 u8 log_rq_stride[0x3]; 3199 u8 xrcd[0x18]; 3200 3201 u8 page_offset[0x6]; 3202 u8 reserved_at_46[0x1]; 3203 u8 dbr_umem_valid[0x1]; 3204 u8 cqn[0x18]; 3205 3206 u8 reserved_at_60[0x20]; 3207 3208 u8 user_index_equal_xrc_srqn[0x1]; 3209 u8 reserved_at_81[0x1]; 3210 u8 log_page_size[0x6]; 3211 u8 user_index[0x18]; 3212 3213 u8 reserved_at_a0[0x20]; 3214 3215 u8 reserved_at_c0[0x8]; 3216 u8 pd[0x18]; 3217 3218 u8 lwm[0x10]; 3219 u8 wqe_cnt[0x10]; 3220 3221 u8 reserved_at_100[0x40]; 3222 3223 u8 db_record_addr_h[0x20]; 3224 3225 u8 db_record_addr_l[0x1e]; 3226 u8 reserved_at_17e[0x2]; 3227 3228 u8 reserved_at_180[0x80]; 3229 }; 3230 3231 struct mlx5_ifc_vnic_diagnostic_statistics_bits { 3232 u8 counter_error_queues[0x20]; 3233 3234 u8 total_error_queues[0x20]; 3235 3236 u8 send_queue_priority_update_flow[0x20]; 3237 3238 u8 reserved_at_60[0x20]; 3239 3240 u8 nic_receive_steering_discard[0x40]; 3241 3242 u8 receive_discard_vport_down[0x40]; 3243 3244 u8 transmit_discard_vport_down[0x40]; 3245 3246 u8 reserved_at_140[0xa0]; 3247 3248 u8 internal_rq_out_of_buffer[0x20]; 3249 3250 u8 reserved_at_200[0xe00]; 3251 }; 3252 3253 struct mlx5_ifc_traffic_counter_bits { 3254 u8 packets[0x40]; 3255 3256 u8 octets[0x40]; 3257 }; 3258 3259 struct mlx5_ifc_tisc_bits { 3260 u8 strict_lag_tx_port_affinity[0x1]; 3261 u8 tls_en[0x1]; 3262 u8 reserved_at_2[0x2]; 3263 u8 lag_tx_port_affinity[0x04]; 3264 3265 u8 reserved_at_8[0x4]; 3266 u8 prio[0x4]; 3267 u8 reserved_at_10[0x10]; 3268 3269 u8 reserved_at_20[0x100]; 3270 3271 u8 reserved_at_120[0x8]; 3272 u8 transport_domain[0x18]; 3273 3274 u8 reserved_at_140[0x8]; 3275 u8 underlay_qpn[0x18]; 3276 3277 u8 reserved_at_160[0x8]; 3278 u8 pd[0x18]; 3279 3280 u8 reserved_at_180[0x380]; 3281 }; 3282 3283 enum { 3284 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0, 3285 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1, 3286 }; 3287 3288 enum { 3289 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO = 0x1, 3290 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO = 0x2, 3291 }; 3292 3293 enum { 3294 MLX5_RX_HASH_FN_NONE = 0x0, 3295 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1, 3296 MLX5_RX_HASH_FN_TOEPLITZ = 0x2, 3297 }; 3298 3299 enum { 3300 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST = 0x1, 3301 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST = 0x2, 3302 }; 3303 3304 struct mlx5_ifc_tirc_bits { 3305 u8 reserved_at_0[0x20]; 3306 3307 u8 disp_type[0x4]; 3308 u8 tls_en[0x1]; 3309 u8 reserved_at_25[0x1b]; 3310 3311 u8 reserved_at_40[0x40]; 3312 3313 u8 reserved_at_80[0x4]; 3314 u8 lro_timeout_period_usecs[0x10]; 3315 u8 lro_enable_mask[0x4]; 3316 u8 lro_max_ip_payload_size[0x8]; 3317 3318 u8 reserved_at_a0[0x40]; 3319 3320 u8 reserved_at_e0[0x8]; 3321 u8 inline_rqn[0x18]; 3322 3323 u8 rx_hash_symmetric[0x1]; 3324 u8 reserved_at_101[0x1]; 3325 u8 tunneled_offload_en[0x1]; 3326 u8 reserved_at_103[0x5]; 3327 u8 indirect_table[0x18]; 3328 3329 u8 rx_hash_fn[0x4]; 3330 u8 reserved_at_124[0x2]; 3331 u8 self_lb_block[0x2]; 3332 u8 transport_domain[0x18]; 3333 3334 u8 rx_hash_toeplitz_key[10][0x20]; 3335 3336 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer; 3337 3338 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner; 3339 3340 u8 reserved_at_2c0[0x4c0]; 3341 }; 3342 3343 enum { 3344 MLX5_SRQC_STATE_GOOD = 0x0, 3345 MLX5_SRQC_STATE_ERROR = 0x1, 3346 }; 3347 3348 struct mlx5_ifc_srqc_bits { 3349 u8 state[0x4]; 3350 u8 log_srq_size[0x4]; 3351 u8 reserved_at_8[0x18]; 3352 3353 u8 wq_signature[0x1]; 3354 u8 cont_srq[0x1]; 3355 u8 reserved_at_22[0x1]; 3356 u8 rlky[0x1]; 3357 u8 reserved_at_24[0x1]; 3358 u8 log_rq_stride[0x3]; 3359 u8 xrcd[0x18]; 3360 3361 u8 page_offset[0x6]; 3362 u8 reserved_at_46[0x2]; 3363 u8 cqn[0x18]; 3364 3365 u8 reserved_at_60[0x20]; 3366 3367 u8 reserved_at_80[0x2]; 3368 u8 log_page_size[0x6]; 3369 u8 reserved_at_88[0x18]; 3370 3371 u8 reserved_at_a0[0x20]; 3372 3373 u8 reserved_at_c0[0x8]; 3374 u8 pd[0x18]; 3375 3376 u8 lwm[0x10]; 3377 u8 wqe_cnt[0x10]; 3378 3379 u8 reserved_at_100[0x40]; 3380 3381 u8 dbr_addr[0x40]; 3382 3383 u8 reserved_at_180[0x80]; 3384 }; 3385 3386 enum { 3387 MLX5_SQC_STATE_RST = 0x0, 3388 MLX5_SQC_STATE_RDY = 0x1, 3389 MLX5_SQC_STATE_ERR = 0x3, 3390 }; 3391 3392 enum { 3393 MLX5_SQC_TIMESTAMP_FORMAT_FREE_RUNNING = 0x0, 3394 MLX5_SQC_TIMESTAMP_FORMAT_DEFAULT = 0x1, 3395 MLX5_SQC_TIMESTAMP_FORMAT_REAL_TIME = 0x2, 3396 }; 3397 3398 struct mlx5_ifc_sqc_bits { 3399 u8 rlky[0x1]; 3400 u8 cd_master[0x1]; 3401 u8 fre[0x1]; 3402 u8 flush_in_error_en[0x1]; 3403 u8 allow_multi_pkt_send_wqe[0x1]; 3404 u8 min_wqe_inline_mode[0x3]; 3405 u8 state[0x4]; 3406 u8 reg_umr[0x1]; 3407 u8 allow_swp[0x1]; 3408 u8 hairpin[0x1]; 3409 u8 reserved_at_f[0xb]; 3410 u8 ts_format[0x2]; 3411 u8 reserved_at_1c[0x4]; 3412 3413 u8 reserved_at_20[0x8]; 3414 u8 user_index[0x18]; 3415 3416 u8 reserved_at_40[0x8]; 3417 u8 cqn[0x18]; 3418 3419 u8 reserved_at_60[0x8]; 3420 u8 hairpin_peer_rq[0x18]; 3421 3422 u8 reserved_at_80[0x10]; 3423 u8 hairpin_peer_vhca[0x10]; 3424 3425 u8 reserved_at_a0[0x20]; 3426 3427 u8 reserved_at_c0[0x8]; 3428 u8 ts_cqe_to_dest_cqn[0x18]; 3429 3430 u8 reserved_at_e0[0x10]; 3431 u8 packet_pacing_rate_limit_index[0x10]; 3432 u8 tis_lst_sz[0x10]; 3433 u8 qos_queue_group_id[0x10]; 3434 3435 u8 reserved_at_120[0x40]; 3436 3437 u8 reserved_at_160[0x8]; 3438 u8 tis_num_0[0x18]; 3439 3440 struct mlx5_ifc_wq_bits wq; 3441 }; 3442 3443 enum { 3444 SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0, 3445 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1, 3446 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2, 3447 SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3, 3448 SCHEDULING_CONTEXT_ELEMENT_TYPE_QUEUE_GROUP = 0x4, 3449 }; 3450 3451 enum { 3452 ELEMENT_TYPE_CAP_MASK_TASR = 1 << 0, 3453 ELEMENT_TYPE_CAP_MASK_VPORT = 1 << 1, 3454 ELEMENT_TYPE_CAP_MASK_VPORT_TC = 1 << 2, 3455 ELEMENT_TYPE_CAP_MASK_PARA_VPORT_TC = 1 << 3, 3456 }; 3457 3458 struct mlx5_ifc_scheduling_context_bits { 3459 u8 element_type[0x8]; 3460 u8 reserved_at_8[0x18]; 3461 3462 u8 element_attributes[0x20]; 3463 3464 u8 parent_element_id[0x20]; 3465 3466 u8 reserved_at_60[0x40]; 3467 3468 u8 bw_share[0x20]; 3469 3470 u8 max_average_bw[0x20]; 3471 3472 u8 reserved_at_e0[0x120]; 3473 }; 3474 3475 struct mlx5_ifc_rqtc_bits { 3476 u8 reserved_at_0[0xa0]; 3477 3478 u8 reserved_at_a0[0x5]; 3479 u8 list_q_type[0x3]; 3480 u8 reserved_at_a8[0x8]; 3481 u8 rqt_max_size[0x10]; 3482 3483 u8 rq_vhca_id_format[0x1]; 3484 u8 reserved_at_c1[0xf]; 3485 u8 rqt_actual_size[0x10]; 3486 3487 u8 reserved_at_e0[0x6a0]; 3488 3489 struct mlx5_ifc_rq_num_bits rq_num[]; 3490 }; 3491 3492 enum { 3493 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0, 3494 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1, 3495 }; 3496 3497 enum { 3498 MLX5_RQC_STATE_RST = 0x0, 3499 MLX5_RQC_STATE_RDY = 0x1, 3500 MLX5_RQC_STATE_ERR = 0x3, 3501 }; 3502 3503 enum { 3504 MLX5_RQC_TIMESTAMP_FORMAT_FREE_RUNNING = 0x0, 3505 MLX5_RQC_TIMESTAMP_FORMAT_DEFAULT = 0x1, 3506 MLX5_RQC_TIMESTAMP_FORMAT_REAL_TIME = 0x2, 3507 }; 3508 3509 struct mlx5_ifc_rqc_bits { 3510 u8 rlky[0x1]; 3511 u8 delay_drop_en[0x1]; 3512 u8 scatter_fcs[0x1]; 3513 u8 vsd[0x1]; 3514 u8 mem_rq_type[0x4]; 3515 u8 state[0x4]; 3516 u8 reserved_at_c[0x1]; 3517 u8 flush_in_error_en[0x1]; 3518 u8 hairpin[0x1]; 3519 u8 reserved_at_f[0xb]; 3520 u8 ts_format[0x2]; 3521 u8 reserved_at_1c[0x4]; 3522 3523 u8 reserved_at_20[0x8]; 3524 u8 user_index[0x18]; 3525 3526 u8 reserved_at_40[0x8]; 3527 u8 cqn[0x18]; 3528 3529 u8 counter_set_id[0x8]; 3530 u8 reserved_at_68[0x18]; 3531 3532 u8 reserved_at_80[0x8]; 3533 u8 rmpn[0x18]; 3534 3535 u8 reserved_at_a0[0x8]; 3536 u8 hairpin_peer_sq[0x18]; 3537 3538 u8 reserved_at_c0[0x10]; 3539 u8 hairpin_peer_vhca[0x10]; 3540 3541 u8 reserved_at_e0[0xa0]; 3542 3543 struct mlx5_ifc_wq_bits wq; 3544 }; 3545 3546 enum { 3547 MLX5_RMPC_STATE_RDY = 0x1, 3548 MLX5_RMPC_STATE_ERR = 0x3, 3549 }; 3550 3551 struct mlx5_ifc_rmpc_bits { 3552 u8 reserved_at_0[0x8]; 3553 u8 state[0x4]; 3554 u8 reserved_at_c[0x14]; 3555 3556 u8 basic_cyclic_rcv_wqe[0x1]; 3557 u8 reserved_at_21[0x1f]; 3558 3559 u8 reserved_at_40[0x140]; 3560 3561 struct mlx5_ifc_wq_bits wq; 3562 }; 3563 3564 struct mlx5_ifc_nic_vport_context_bits { 3565 u8 reserved_at_0[0x5]; 3566 u8 min_wqe_inline_mode[0x3]; 3567 u8 reserved_at_8[0x15]; 3568 u8 disable_mc_local_lb[0x1]; 3569 u8 disable_uc_local_lb[0x1]; 3570 u8 roce_en[0x1]; 3571 3572 u8 arm_change_event[0x1]; 3573 u8 reserved_at_21[0x1a]; 3574 u8 event_on_mtu[0x1]; 3575 u8 event_on_promisc_change[0x1]; 3576 u8 event_on_vlan_change[0x1]; 3577 u8 event_on_mc_address_change[0x1]; 3578 u8 event_on_uc_address_change[0x1]; 3579 3580 u8 reserved_at_40[0xc]; 3581 3582 u8 affiliation_criteria[0x4]; 3583 u8 affiliated_vhca_id[0x10]; 3584 3585 u8 reserved_at_60[0xd0]; 3586 3587 u8 mtu[0x10]; 3588 3589 u8 system_image_guid[0x40]; 3590 u8 port_guid[0x40]; 3591 u8 node_guid[0x40]; 3592 3593 u8 reserved_at_200[0x140]; 3594 u8 qkey_violation_counter[0x10]; 3595 u8 reserved_at_350[0x430]; 3596 3597 u8 promisc_uc[0x1]; 3598 u8 promisc_mc[0x1]; 3599 u8 promisc_all[0x1]; 3600 u8 reserved_at_783[0x2]; 3601 u8 allowed_list_type[0x3]; 3602 u8 reserved_at_788[0xc]; 3603 u8 allowed_list_size[0xc]; 3604 3605 struct mlx5_ifc_mac_address_layout_bits permanent_address; 3606 3607 u8 reserved_at_7e0[0x20]; 3608 3609 u8 current_uc_mac_address[][0x40]; 3610 }; 3611 3612 enum { 3613 MLX5_MKC_ACCESS_MODE_PA = 0x0, 3614 MLX5_MKC_ACCESS_MODE_MTT = 0x1, 3615 MLX5_MKC_ACCESS_MODE_KLMS = 0x2, 3616 MLX5_MKC_ACCESS_MODE_KSM = 0x3, 3617 MLX5_MKC_ACCESS_MODE_SW_ICM = 0x4, 3618 MLX5_MKC_ACCESS_MODE_MEMIC = 0x5, 3619 }; 3620 3621 struct mlx5_ifc_mkc_bits { 3622 u8 reserved_at_0[0x1]; 3623 u8 free[0x1]; 3624 u8 reserved_at_2[0x1]; 3625 u8 access_mode_4_2[0x3]; 3626 u8 reserved_at_6[0x7]; 3627 u8 relaxed_ordering_write[0x1]; 3628 u8 reserved_at_e[0x1]; 3629 u8 small_fence_on_rdma_read_response[0x1]; 3630 u8 umr_en[0x1]; 3631 u8 a[0x1]; 3632 u8 rw[0x1]; 3633 u8 rr[0x1]; 3634 u8 lw[0x1]; 3635 u8 lr[0x1]; 3636 u8 access_mode_1_0[0x2]; 3637 u8 reserved_at_18[0x8]; 3638 3639 u8 qpn[0x18]; 3640 u8 mkey_7_0[0x8]; 3641 3642 u8 reserved_at_40[0x20]; 3643 3644 u8 length64[0x1]; 3645 u8 bsf_en[0x1]; 3646 u8 sync_umr[0x1]; 3647 u8 reserved_at_63[0x2]; 3648 u8 expected_sigerr_count[0x1]; 3649 u8 reserved_at_66[0x1]; 3650 u8 en_rinval[0x1]; 3651 u8 pd[0x18]; 3652 3653 u8 start_addr[0x40]; 3654 3655 u8 len[0x40]; 3656 3657 u8 bsf_octword_size[0x20]; 3658 3659 u8 reserved_at_120[0x80]; 3660 3661 u8 translations_octword_size[0x20]; 3662 3663 u8 reserved_at_1c0[0x19]; 3664 u8 relaxed_ordering_read[0x1]; 3665 u8 reserved_at_1d9[0x1]; 3666 u8 log_page_size[0x5]; 3667 3668 u8 reserved_at_1e0[0x20]; 3669 }; 3670 3671 struct mlx5_ifc_pkey_bits { 3672 u8 reserved_at_0[0x10]; 3673 u8 pkey[0x10]; 3674 }; 3675 3676 struct mlx5_ifc_array128_auto_bits { 3677 u8 array128_auto[16][0x8]; 3678 }; 3679 3680 struct mlx5_ifc_hca_vport_context_bits { 3681 u8 field_select[0x20]; 3682 3683 u8 reserved_at_20[0xe0]; 3684 3685 u8 sm_virt_aware[0x1]; 3686 u8 has_smi[0x1]; 3687 u8 has_raw[0x1]; 3688 u8 grh_required[0x1]; 3689 u8 reserved_at_104[0xc]; 3690 u8 port_physical_state[0x4]; 3691 u8 vport_state_policy[0x4]; 3692 u8 port_state[0x4]; 3693 u8 vport_state[0x4]; 3694 3695 u8 reserved_at_120[0x20]; 3696 3697 u8 system_image_guid[0x40]; 3698 3699 u8 port_guid[0x40]; 3700 3701 u8 node_guid[0x40]; 3702 3703 u8 cap_mask1[0x20]; 3704 3705 u8 cap_mask1_field_select[0x20]; 3706 3707 u8 cap_mask2[0x20]; 3708 3709 u8 cap_mask2_field_select[0x20]; 3710 3711 u8 reserved_at_280[0x80]; 3712 3713 u8 lid[0x10]; 3714 u8 reserved_at_310[0x4]; 3715 u8 init_type_reply[0x4]; 3716 u8 lmc[0x3]; 3717 u8 subnet_timeout[0x5]; 3718 3719 u8 sm_lid[0x10]; 3720 u8 sm_sl[0x4]; 3721 u8 reserved_at_334[0xc]; 3722 3723 u8 qkey_violation_counter[0x10]; 3724 u8 pkey_violation_counter[0x10]; 3725 3726 u8 reserved_at_360[0xca0]; 3727 }; 3728 3729 struct mlx5_ifc_esw_vport_context_bits { 3730 u8 fdb_to_vport_reg_c[0x1]; 3731 u8 reserved_at_1[0x2]; 3732 u8 vport_svlan_strip[0x1]; 3733 u8 vport_cvlan_strip[0x1]; 3734 u8 vport_svlan_insert[0x1]; 3735 u8 vport_cvlan_insert[0x2]; 3736 u8 fdb_to_vport_reg_c_id[0x8]; 3737 u8 reserved_at_10[0x10]; 3738 3739 u8 reserved_at_20[0x20]; 3740 3741 u8 svlan_cfi[0x1]; 3742 u8 svlan_pcp[0x3]; 3743 u8 svlan_id[0xc]; 3744 u8 cvlan_cfi[0x1]; 3745 u8 cvlan_pcp[0x3]; 3746 u8 cvlan_id[0xc]; 3747 3748 u8 reserved_at_60[0x720]; 3749 3750 u8 sw_steering_vport_icm_address_rx[0x40]; 3751 3752 u8 sw_steering_vport_icm_address_tx[0x40]; 3753 }; 3754 3755 enum { 3756 MLX5_EQC_STATUS_OK = 0x0, 3757 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa, 3758 }; 3759 3760 enum { 3761 MLX5_EQC_ST_ARMED = 0x9, 3762 MLX5_EQC_ST_FIRED = 0xa, 3763 }; 3764 3765 struct mlx5_ifc_eqc_bits { 3766 u8 status[0x4]; 3767 u8 reserved_at_4[0x9]; 3768 u8 ec[0x1]; 3769 u8 oi[0x1]; 3770 u8 reserved_at_f[0x5]; 3771 u8 st[0x4]; 3772 u8 reserved_at_18[0x8]; 3773 3774 u8 reserved_at_20[0x20]; 3775 3776 u8 reserved_at_40[0x14]; 3777 u8 page_offset[0x6]; 3778 u8 reserved_at_5a[0x6]; 3779 3780 u8 reserved_at_60[0x3]; 3781 u8 log_eq_size[0x5]; 3782 u8 uar_page[0x18]; 3783 3784 u8 reserved_at_80[0x20]; 3785 3786 u8 reserved_at_a0[0x18]; 3787 u8 intr[0x8]; 3788 3789 u8 reserved_at_c0[0x3]; 3790 u8 log_page_size[0x5]; 3791 u8 reserved_at_c8[0x18]; 3792 3793 u8 reserved_at_e0[0x60]; 3794 3795 u8 reserved_at_140[0x8]; 3796 u8 consumer_counter[0x18]; 3797 3798 u8 reserved_at_160[0x8]; 3799 u8 producer_counter[0x18]; 3800 3801 u8 reserved_at_180[0x80]; 3802 }; 3803 3804 enum { 3805 MLX5_DCTC_STATE_ACTIVE = 0x0, 3806 MLX5_DCTC_STATE_DRAINING = 0x1, 3807 MLX5_DCTC_STATE_DRAINED = 0x2, 3808 }; 3809 3810 enum { 3811 MLX5_DCTC_CS_RES_DISABLE = 0x0, 3812 MLX5_DCTC_CS_RES_NA = 0x1, 3813 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2, 3814 }; 3815 3816 enum { 3817 MLX5_DCTC_MTU_256_BYTES = 0x1, 3818 MLX5_DCTC_MTU_512_BYTES = 0x2, 3819 MLX5_DCTC_MTU_1K_BYTES = 0x3, 3820 MLX5_DCTC_MTU_2K_BYTES = 0x4, 3821 MLX5_DCTC_MTU_4K_BYTES = 0x5, 3822 }; 3823 3824 struct mlx5_ifc_dctc_bits { 3825 u8 reserved_at_0[0x4]; 3826 u8 state[0x4]; 3827 u8 reserved_at_8[0x18]; 3828 3829 u8 reserved_at_20[0x8]; 3830 u8 user_index[0x18]; 3831 3832 u8 reserved_at_40[0x8]; 3833 u8 cqn[0x18]; 3834 3835 u8 counter_set_id[0x8]; 3836 u8 atomic_mode[0x4]; 3837 u8 rre[0x1]; 3838 u8 rwe[0x1]; 3839 u8 rae[0x1]; 3840 u8 atomic_like_write_en[0x1]; 3841 u8 latency_sensitive[0x1]; 3842 u8 rlky[0x1]; 3843 u8 free_ar[0x1]; 3844 u8 reserved_at_73[0xd]; 3845 3846 u8 reserved_at_80[0x8]; 3847 u8 cs_res[0x8]; 3848 u8 reserved_at_90[0x3]; 3849 u8 min_rnr_nak[0x5]; 3850 u8 reserved_at_98[0x8]; 3851 3852 u8 reserved_at_a0[0x8]; 3853 u8 srqn_xrqn[0x18]; 3854 3855 u8 reserved_at_c0[0x8]; 3856 u8 pd[0x18]; 3857 3858 u8 tclass[0x8]; 3859 u8 reserved_at_e8[0x4]; 3860 u8 flow_label[0x14]; 3861 3862 u8 dc_access_key[0x40]; 3863 3864 u8 reserved_at_140[0x5]; 3865 u8 mtu[0x3]; 3866 u8 port[0x8]; 3867 u8 pkey_index[0x10]; 3868 3869 u8 reserved_at_160[0x8]; 3870 u8 my_addr_index[0x8]; 3871 u8 reserved_at_170[0x8]; 3872 u8 hop_limit[0x8]; 3873 3874 u8 dc_access_key_violation_count[0x20]; 3875 3876 u8 reserved_at_1a0[0x14]; 3877 u8 dei_cfi[0x1]; 3878 u8 eth_prio[0x3]; 3879 u8 ecn[0x2]; 3880 u8 dscp[0x6]; 3881 3882 u8 reserved_at_1c0[0x20]; 3883 u8 ece[0x20]; 3884 }; 3885 3886 enum { 3887 MLX5_CQC_STATUS_OK = 0x0, 3888 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9, 3889 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa, 3890 }; 3891 3892 enum { 3893 MLX5_CQC_CQE_SZ_64_BYTES = 0x0, 3894 MLX5_CQC_CQE_SZ_128_BYTES = 0x1, 3895 }; 3896 3897 enum { 3898 MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED = 0x6, 3899 MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED = 0x9, 3900 MLX5_CQC_ST_FIRED = 0xa, 3901 }; 3902 3903 enum { 3904 MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0, 3905 MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1, 3906 MLX5_CQ_PERIOD_NUM_MODES 3907 }; 3908 3909 struct mlx5_ifc_cqc_bits { 3910 u8 status[0x4]; 3911 u8 reserved_at_4[0x2]; 3912 u8 dbr_umem_valid[0x1]; 3913 u8 apu_thread_cq[0x1]; 3914 u8 cqe_sz[0x3]; 3915 u8 cc[0x1]; 3916 u8 reserved_at_c[0x1]; 3917 u8 scqe_break_moderation_en[0x1]; 3918 u8 oi[0x1]; 3919 u8 cq_period_mode[0x2]; 3920 u8 cqe_comp_en[0x1]; 3921 u8 mini_cqe_res_format[0x2]; 3922 u8 st[0x4]; 3923 u8 reserved_at_18[0x8]; 3924 3925 u8 reserved_at_20[0x20]; 3926 3927 u8 reserved_at_40[0x14]; 3928 u8 page_offset[0x6]; 3929 u8 reserved_at_5a[0x6]; 3930 3931 u8 reserved_at_60[0x3]; 3932 u8 log_cq_size[0x5]; 3933 u8 uar_page[0x18]; 3934 3935 u8 reserved_at_80[0x4]; 3936 u8 cq_period[0xc]; 3937 u8 cq_max_count[0x10]; 3938 3939 u8 reserved_at_a0[0x18]; 3940 u8 c_eqn[0x8]; 3941 3942 u8 reserved_at_c0[0x3]; 3943 u8 log_page_size[0x5]; 3944 u8 reserved_at_c8[0x18]; 3945 3946 u8 reserved_at_e0[0x20]; 3947 3948 u8 reserved_at_100[0x8]; 3949 u8 last_notified_index[0x18]; 3950 3951 u8 reserved_at_120[0x8]; 3952 u8 last_solicit_index[0x18]; 3953 3954 u8 reserved_at_140[0x8]; 3955 u8 consumer_counter[0x18]; 3956 3957 u8 reserved_at_160[0x8]; 3958 u8 producer_counter[0x18]; 3959 3960 u8 reserved_at_180[0x40]; 3961 3962 u8 dbr_addr[0x40]; 3963 }; 3964 3965 union mlx5_ifc_cong_control_roce_ecn_auto_bits { 3966 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp; 3967 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp; 3968 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np; 3969 u8 reserved_at_0[0x800]; 3970 }; 3971 3972 struct mlx5_ifc_query_adapter_param_block_bits { 3973 u8 reserved_at_0[0xc0]; 3974 3975 u8 reserved_at_c0[0x8]; 3976 u8 ieee_vendor_id[0x18]; 3977 3978 u8 reserved_at_e0[0x10]; 3979 u8 vsd_vendor_id[0x10]; 3980 3981 u8 vsd[208][0x8]; 3982 3983 u8 vsd_contd_psid[16][0x8]; 3984 }; 3985 3986 enum { 3987 MLX5_XRQC_STATE_GOOD = 0x0, 3988 MLX5_XRQC_STATE_ERROR = 0x1, 3989 }; 3990 3991 enum { 3992 MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0, 3993 MLX5_XRQC_TOPOLOGY_TAG_MATCHING = 0x1, 3994 }; 3995 3996 enum { 3997 MLX5_XRQC_OFFLOAD_RNDV = 0x1, 3998 }; 3999 4000 struct mlx5_ifc_tag_matching_topology_context_bits { 4001 u8 log_matching_list_sz[0x4]; 4002 u8 reserved_at_4[0xc]; 4003 u8 append_next_index[0x10]; 4004 4005 u8 sw_phase_cnt[0x10]; 4006 u8 hw_phase_cnt[0x10]; 4007 4008 u8 reserved_at_40[0x40]; 4009 }; 4010 4011 struct mlx5_ifc_xrqc_bits { 4012 u8 state[0x4]; 4013 u8 rlkey[0x1]; 4014 u8 reserved_at_5[0xf]; 4015 u8 topology[0x4]; 4016 u8 reserved_at_18[0x4]; 4017 u8 offload[0x4]; 4018 4019 u8 reserved_at_20[0x8]; 4020 u8 user_index[0x18]; 4021 4022 u8 reserved_at_40[0x8]; 4023 u8 cqn[0x18]; 4024 4025 u8 reserved_at_60[0xa0]; 4026 4027 struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context; 4028 4029 u8 reserved_at_180[0x280]; 4030 4031 struct mlx5_ifc_wq_bits wq; 4032 }; 4033 4034 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits { 4035 struct mlx5_ifc_modify_field_select_bits modify_field_select; 4036 struct mlx5_ifc_resize_field_select_bits resize_field_select; 4037 u8 reserved_at_0[0x20]; 4038 }; 4039 4040 union mlx5_ifc_field_select_802_1_r_roce_auto_bits { 4041 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp; 4042 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp; 4043 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np; 4044 u8 reserved_at_0[0x20]; 4045 }; 4046 4047 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits { 4048 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 4049 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 4050 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 4051 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 4052 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 4053 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 4054 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout; 4055 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout; 4056 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 4057 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 4058 struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs; 4059 u8 reserved_at_0[0x7c0]; 4060 }; 4061 4062 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits { 4063 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout; 4064 u8 reserved_at_0[0x7c0]; 4065 }; 4066 4067 union mlx5_ifc_event_auto_bits { 4068 struct mlx5_ifc_comp_event_bits comp_event; 4069 struct mlx5_ifc_dct_events_bits dct_events; 4070 struct mlx5_ifc_qp_events_bits qp_events; 4071 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event; 4072 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event; 4073 struct mlx5_ifc_cq_error_bits cq_error; 4074 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged; 4075 struct mlx5_ifc_port_state_change_event_bits port_state_change_event; 4076 struct mlx5_ifc_gpio_event_bits gpio_event; 4077 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event; 4078 struct mlx5_ifc_stall_vl_event_bits stall_vl_event; 4079 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event; 4080 u8 reserved_at_0[0xe0]; 4081 }; 4082 4083 struct mlx5_ifc_health_buffer_bits { 4084 u8 reserved_at_0[0x100]; 4085 4086 u8 assert_existptr[0x20]; 4087 4088 u8 assert_callra[0x20]; 4089 4090 u8 reserved_at_140[0x40]; 4091 4092 u8 fw_version[0x20]; 4093 4094 u8 hw_id[0x20]; 4095 4096 u8 reserved_at_1c0[0x20]; 4097 4098 u8 irisc_index[0x8]; 4099 u8 synd[0x8]; 4100 u8 ext_synd[0x10]; 4101 }; 4102 4103 struct mlx5_ifc_register_loopback_control_bits { 4104 u8 no_lb[0x1]; 4105 u8 reserved_at_1[0x7]; 4106 u8 port[0x8]; 4107 u8 reserved_at_10[0x10]; 4108 4109 u8 reserved_at_20[0x60]; 4110 }; 4111 4112 struct mlx5_ifc_vport_tc_element_bits { 4113 u8 traffic_class[0x4]; 4114 u8 reserved_at_4[0xc]; 4115 u8 vport_number[0x10]; 4116 }; 4117 4118 struct mlx5_ifc_vport_element_bits { 4119 u8 reserved_at_0[0x10]; 4120 u8 vport_number[0x10]; 4121 }; 4122 4123 enum { 4124 TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0, 4125 TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1, 4126 TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2, 4127 }; 4128 4129 struct mlx5_ifc_tsar_element_bits { 4130 u8 reserved_at_0[0x8]; 4131 u8 tsar_type[0x8]; 4132 u8 reserved_at_10[0x10]; 4133 }; 4134 4135 enum { 4136 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0, 4137 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1, 4138 }; 4139 4140 struct mlx5_ifc_teardown_hca_out_bits { 4141 u8 status[0x8]; 4142 u8 reserved_at_8[0x18]; 4143 4144 u8 syndrome[0x20]; 4145 4146 u8 reserved_at_40[0x3f]; 4147 4148 u8 state[0x1]; 4149 }; 4150 4151 enum { 4152 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0, 4153 MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE = 0x1, 4154 MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN = 0x2, 4155 }; 4156 4157 struct mlx5_ifc_teardown_hca_in_bits { 4158 u8 opcode[0x10]; 4159 u8 reserved_at_10[0x10]; 4160 4161 u8 reserved_at_20[0x10]; 4162 u8 op_mod[0x10]; 4163 4164 u8 reserved_at_40[0x10]; 4165 u8 profile[0x10]; 4166 4167 u8 reserved_at_60[0x20]; 4168 }; 4169 4170 struct mlx5_ifc_sqerr2rts_qp_out_bits { 4171 u8 status[0x8]; 4172 u8 reserved_at_8[0x18]; 4173 4174 u8 syndrome[0x20]; 4175 4176 u8 reserved_at_40[0x40]; 4177 }; 4178 4179 struct mlx5_ifc_sqerr2rts_qp_in_bits { 4180 u8 opcode[0x10]; 4181 u8 uid[0x10]; 4182 4183 u8 reserved_at_20[0x10]; 4184 u8 op_mod[0x10]; 4185 4186 u8 reserved_at_40[0x8]; 4187 u8 qpn[0x18]; 4188 4189 u8 reserved_at_60[0x20]; 4190 4191 u8 opt_param_mask[0x20]; 4192 4193 u8 reserved_at_a0[0x20]; 4194 4195 struct mlx5_ifc_qpc_bits qpc; 4196 4197 u8 reserved_at_800[0x80]; 4198 }; 4199 4200 struct mlx5_ifc_sqd2rts_qp_out_bits { 4201 u8 status[0x8]; 4202 u8 reserved_at_8[0x18]; 4203 4204 u8 syndrome[0x20]; 4205 4206 u8 reserved_at_40[0x40]; 4207 }; 4208 4209 struct mlx5_ifc_sqd2rts_qp_in_bits { 4210 u8 opcode[0x10]; 4211 u8 uid[0x10]; 4212 4213 u8 reserved_at_20[0x10]; 4214 u8 op_mod[0x10]; 4215 4216 u8 reserved_at_40[0x8]; 4217 u8 qpn[0x18]; 4218 4219 u8 reserved_at_60[0x20]; 4220 4221 u8 opt_param_mask[0x20]; 4222 4223 u8 reserved_at_a0[0x20]; 4224 4225 struct mlx5_ifc_qpc_bits qpc; 4226 4227 u8 reserved_at_800[0x80]; 4228 }; 4229 4230 struct mlx5_ifc_set_roce_address_out_bits { 4231 u8 status[0x8]; 4232 u8 reserved_at_8[0x18]; 4233 4234 u8 syndrome[0x20]; 4235 4236 u8 reserved_at_40[0x40]; 4237 }; 4238 4239 struct mlx5_ifc_set_roce_address_in_bits { 4240 u8 opcode[0x10]; 4241 u8 reserved_at_10[0x10]; 4242 4243 u8 reserved_at_20[0x10]; 4244 u8 op_mod[0x10]; 4245 4246 u8 roce_address_index[0x10]; 4247 u8 reserved_at_50[0xc]; 4248 u8 vhca_port_num[0x4]; 4249 4250 u8 reserved_at_60[0x20]; 4251 4252 struct mlx5_ifc_roce_addr_layout_bits roce_address; 4253 }; 4254 4255 struct mlx5_ifc_set_mad_demux_out_bits { 4256 u8 status[0x8]; 4257 u8 reserved_at_8[0x18]; 4258 4259 u8 syndrome[0x20]; 4260 4261 u8 reserved_at_40[0x40]; 4262 }; 4263 4264 enum { 4265 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0, 4266 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2, 4267 }; 4268 4269 struct mlx5_ifc_set_mad_demux_in_bits { 4270 u8 opcode[0x10]; 4271 u8 reserved_at_10[0x10]; 4272 4273 u8 reserved_at_20[0x10]; 4274 u8 op_mod[0x10]; 4275 4276 u8 reserved_at_40[0x20]; 4277 4278 u8 reserved_at_60[0x6]; 4279 u8 demux_mode[0x2]; 4280 u8 reserved_at_68[0x18]; 4281 }; 4282 4283 struct mlx5_ifc_set_l2_table_entry_out_bits { 4284 u8 status[0x8]; 4285 u8 reserved_at_8[0x18]; 4286 4287 u8 syndrome[0x20]; 4288 4289 u8 reserved_at_40[0x40]; 4290 }; 4291 4292 struct mlx5_ifc_set_l2_table_entry_in_bits { 4293 u8 opcode[0x10]; 4294 u8 reserved_at_10[0x10]; 4295 4296 u8 reserved_at_20[0x10]; 4297 u8 op_mod[0x10]; 4298 4299 u8 reserved_at_40[0x60]; 4300 4301 u8 reserved_at_a0[0x8]; 4302 u8 table_index[0x18]; 4303 4304 u8 reserved_at_c0[0x20]; 4305 4306 u8 reserved_at_e0[0x13]; 4307 u8 vlan_valid[0x1]; 4308 u8 vlan[0xc]; 4309 4310 struct mlx5_ifc_mac_address_layout_bits mac_address; 4311 4312 u8 reserved_at_140[0xc0]; 4313 }; 4314 4315 struct mlx5_ifc_set_issi_out_bits { 4316 u8 status[0x8]; 4317 u8 reserved_at_8[0x18]; 4318 4319 u8 syndrome[0x20]; 4320 4321 u8 reserved_at_40[0x40]; 4322 }; 4323 4324 struct mlx5_ifc_set_issi_in_bits { 4325 u8 opcode[0x10]; 4326 u8 reserved_at_10[0x10]; 4327 4328 u8 reserved_at_20[0x10]; 4329 u8 op_mod[0x10]; 4330 4331 u8 reserved_at_40[0x10]; 4332 u8 current_issi[0x10]; 4333 4334 u8 reserved_at_60[0x20]; 4335 }; 4336 4337 struct mlx5_ifc_set_hca_cap_out_bits { 4338 u8 status[0x8]; 4339 u8 reserved_at_8[0x18]; 4340 4341 u8 syndrome[0x20]; 4342 4343 u8 reserved_at_40[0x40]; 4344 }; 4345 4346 struct mlx5_ifc_set_hca_cap_in_bits { 4347 u8 opcode[0x10]; 4348 u8 reserved_at_10[0x10]; 4349 4350 u8 reserved_at_20[0x10]; 4351 u8 op_mod[0x10]; 4352 4353 u8 other_function[0x1]; 4354 u8 reserved_at_41[0xf]; 4355 u8 function_id[0x10]; 4356 4357 u8 reserved_at_60[0x20]; 4358 4359 union mlx5_ifc_hca_cap_union_bits capability; 4360 }; 4361 4362 enum { 4363 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0, 4364 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1, 4365 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2, 4366 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3, 4367 MLX5_SET_FTE_MODIFY_ENABLE_MASK_IPSEC_OBJ_ID = 0x4 4368 }; 4369 4370 struct mlx5_ifc_set_fte_out_bits { 4371 u8 status[0x8]; 4372 u8 reserved_at_8[0x18]; 4373 4374 u8 syndrome[0x20]; 4375 4376 u8 reserved_at_40[0x40]; 4377 }; 4378 4379 struct mlx5_ifc_set_fte_in_bits { 4380 u8 opcode[0x10]; 4381 u8 reserved_at_10[0x10]; 4382 4383 u8 reserved_at_20[0x10]; 4384 u8 op_mod[0x10]; 4385 4386 u8 other_vport[0x1]; 4387 u8 reserved_at_41[0xf]; 4388 u8 vport_number[0x10]; 4389 4390 u8 reserved_at_60[0x20]; 4391 4392 u8 table_type[0x8]; 4393 u8 reserved_at_88[0x18]; 4394 4395 u8 reserved_at_a0[0x8]; 4396 u8 table_id[0x18]; 4397 4398 u8 ignore_flow_level[0x1]; 4399 u8 reserved_at_c1[0x17]; 4400 u8 modify_enable_mask[0x8]; 4401 4402 u8 reserved_at_e0[0x20]; 4403 4404 u8 flow_index[0x20]; 4405 4406 u8 reserved_at_120[0xe0]; 4407 4408 struct mlx5_ifc_flow_context_bits flow_context; 4409 }; 4410 4411 struct mlx5_ifc_rts2rts_qp_out_bits { 4412 u8 status[0x8]; 4413 u8 reserved_at_8[0x18]; 4414 4415 u8 syndrome[0x20]; 4416 4417 u8 reserved_at_40[0x20]; 4418 u8 ece[0x20]; 4419 }; 4420 4421 struct mlx5_ifc_rts2rts_qp_in_bits { 4422 u8 opcode[0x10]; 4423 u8 uid[0x10]; 4424 4425 u8 reserved_at_20[0x10]; 4426 u8 op_mod[0x10]; 4427 4428 u8 reserved_at_40[0x8]; 4429 u8 qpn[0x18]; 4430 4431 u8 reserved_at_60[0x20]; 4432 4433 u8 opt_param_mask[0x20]; 4434 4435 u8 ece[0x20]; 4436 4437 struct mlx5_ifc_qpc_bits qpc; 4438 4439 u8 reserved_at_800[0x80]; 4440 }; 4441 4442 struct mlx5_ifc_rtr2rts_qp_out_bits { 4443 u8 status[0x8]; 4444 u8 reserved_at_8[0x18]; 4445 4446 u8 syndrome[0x20]; 4447 4448 u8 reserved_at_40[0x20]; 4449 u8 ece[0x20]; 4450 }; 4451 4452 struct mlx5_ifc_rtr2rts_qp_in_bits { 4453 u8 opcode[0x10]; 4454 u8 uid[0x10]; 4455 4456 u8 reserved_at_20[0x10]; 4457 u8 op_mod[0x10]; 4458 4459 u8 reserved_at_40[0x8]; 4460 u8 qpn[0x18]; 4461 4462 u8 reserved_at_60[0x20]; 4463 4464 u8 opt_param_mask[0x20]; 4465 4466 u8 ece[0x20]; 4467 4468 struct mlx5_ifc_qpc_bits qpc; 4469 4470 u8 reserved_at_800[0x80]; 4471 }; 4472 4473 struct mlx5_ifc_rst2init_qp_out_bits { 4474 u8 status[0x8]; 4475 u8 reserved_at_8[0x18]; 4476 4477 u8 syndrome[0x20]; 4478 4479 u8 reserved_at_40[0x20]; 4480 u8 ece[0x20]; 4481 }; 4482 4483 struct mlx5_ifc_rst2init_qp_in_bits { 4484 u8 opcode[0x10]; 4485 u8 uid[0x10]; 4486 4487 u8 reserved_at_20[0x10]; 4488 u8 op_mod[0x10]; 4489 4490 u8 reserved_at_40[0x8]; 4491 u8 qpn[0x18]; 4492 4493 u8 reserved_at_60[0x20]; 4494 4495 u8 opt_param_mask[0x20]; 4496 4497 u8 ece[0x20]; 4498 4499 struct mlx5_ifc_qpc_bits qpc; 4500 4501 u8 reserved_at_800[0x80]; 4502 }; 4503 4504 struct mlx5_ifc_query_xrq_out_bits { 4505 u8 status[0x8]; 4506 u8 reserved_at_8[0x18]; 4507 4508 u8 syndrome[0x20]; 4509 4510 u8 reserved_at_40[0x40]; 4511 4512 struct mlx5_ifc_xrqc_bits xrq_context; 4513 }; 4514 4515 struct mlx5_ifc_query_xrq_in_bits { 4516 u8 opcode[0x10]; 4517 u8 reserved_at_10[0x10]; 4518 4519 u8 reserved_at_20[0x10]; 4520 u8 op_mod[0x10]; 4521 4522 u8 reserved_at_40[0x8]; 4523 u8 xrqn[0x18]; 4524 4525 u8 reserved_at_60[0x20]; 4526 }; 4527 4528 struct mlx5_ifc_query_xrc_srq_out_bits { 4529 u8 status[0x8]; 4530 u8 reserved_at_8[0x18]; 4531 4532 u8 syndrome[0x20]; 4533 4534 u8 reserved_at_40[0x40]; 4535 4536 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 4537 4538 u8 reserved_at_280[0x600]; 4539 4540 u8 pas[][0x40]; 4541 }; 4542 4543 struct mlx5_ifc_query_xrc_srq_in_bits { 4544 u8 opcode[0x10]; 4545 u8 reserved_at_10[0x10]; 4546 4547 u8 reserved_at_20[0x10]; 4548 u8 op_mod[0x10]; 4549 4550 u8 reserved_at_40[0x8]; 4551 u8 xrc_srqn[0x18]; 4552 4553 u8 reserved_at_60[0x20]; 4554 }; 4555 4556 enum { 4557 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0, 4558 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1, 4559 }; 4560 4561 struct mlx5_ifc_query_vport_state_out_bits { 4562 u8 status[0x8]; 4563 u8 reserved_at_8[0x18]; 4564 4565 u8 syndrome[0x20]; 4566 4567 u8 reserved_at_40[0x20]; 4568 4569 u8 reserved_at_60[0x18]; 4570 u8 admin_state[0x4]; 4571 u8 state[0x4]; 4572 }; 4573 4574 enum { 4575 MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT = 0x0, 4576 MLX5_VPORT_STATE_OP_MOD_ESW_VPORT = 0x1, 4577 MLX5_VPORT_STATE_OP_MOD_UPLINK = 0x2, 4578 }; 4579 4580 struct mlx5_ifc_arm_monitor_counter_in_bits { 4581 u8 opcode[0x10]; 4582 u8 uid[0x10]; 4583 4584 u8 reserved_at_20[0x10]; 4585 u8 op_mod[0x10]; 4586 4587 u8 reserved_at_40[0x20]; 4588 4589 u8 reserved_at_60[0x20]; 4590 }; 4591 4592 struct mlx5_ifc_arm_monitor_counter_out_bits { 4593 u8 status[0x8]; 4594 u8 reserved_at_8[0x18]; 4595 4596 u8 syndrome[0x20]; 4597 4598 u8 reserved_at_40[0x40]; 4599 }; 4600 4601 enum { 4602 MLX5_QUERY_MONITOR_CNT_TYPE_PPCNT = 0x0, 4603 MLX5_QUERY_MONITOR_CNT_TYPE_Q_COUNTER = 0x1, 4604 }; 4605 4606 enum mlx5_monitor_counter_ppcnt { 4607 MLX5_QUERY_MONITOR_PPCNT_IN_RANGE_LENGTH_ERRORS = 0x0, 4608 MLX5_QUERY_MONITOR_PPCNT_OUT_OF_RANGE_LENGTH_FIELD = 0x1, 4609 MLX5_QUERY_MONITOR_PPCNT_FRAME_TOO_LONG_ERRORS = 0x2, 4610 MLX5_QUERY_MONITOR_PPCNT_FRAME_CHECK_SEQUENCE_ERRORS = 0x3, 4611 MLX5_QUERY_MONITOR_PPCNT_ALIGNMENT_ERRORS = 0x4, 4612 MLX5_QUERY_MONITOR_PPCNT_IF_OUT_DISCARDS = 0x5, 4613 }; 4614 4615 enum { 4616 MLX5_QUERY_MONITOR_Q_COUNTER_RX_OUT_OF_BUFFER = 0x4, 4617 }; 4618 4619 struct mlx5_ifc_monitor_counter_output_bits { 4620 u8 reserved_at_0[0x4]; 4621 u8 type[0x4]; 4622 u8 reserved_at_8[0x8]; 4623 u8 counter[0x10]; 4624 4625 u8 counter_group_id[0x20]; 4626 }; 4627 4628 #define MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 (6) 4629 #define MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1 (1) 4630 #define MLX5_CMD_SET_MONITOR_NUM_COUNTER (MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 +\ 4631 MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1) 4632 4633 struct mlx5_ifc_set_monitor_counter_in_bits { 4634 u8 opcode[0x10]; 4635 u8 uid[0x10]; 4636 4637 u8 reserved_at_20[0x10]; 4638 u8 op_mod[0x10]; 4639 4640 u8 reserved_at_40[0x10]; 4641 u8 num_of_counters[0x10]; 4642 4643 u8 reserved_at_60[0x20]; 4644 4645 struct mlx5_ifc_monitor_counter_output_bits monitor_counter[MLX5_CMD_SET_MONITOR_NUM_COUNTER]; 4646 }; 4647 4648 struct mlx5_ifc_set_monitor_counter_out_bits { 4649 u8 status[0x8]; 4650 u8 reserved_at_8[0x18]; 4651 4652 u8 syndrome[0x20]; 4653 4654 u8 reserved_at_40[0x40]; 4655 }; 4656 4657 struct mlx5_ifc_query_vport_state_in_bits { 4658 u8 opcode[0x10]; 4659 u8 reserved_at_10[0x10]; 4660 4661 u8 reserved_at_20[0x10]; 4662 u8 op_mod[0x10]; 4663 4664 u8 other_vport[0x1]; 4665 u8 reserved_at_41[0xf]; 4666 u8 vport_number[0x10]; 4667 4668 u8 reserved_at_60[0x20]; 4669 }; 4670 4671 struct mlx5_ifc_query_vnic_env_out_bits { 4672 u8 status[0x8]; 4673 u8 reserved_at_8[0x18]; 4674 4675 u8 syndrome[0x20]; 4676 4677 u8 reserved_at_40[0x40]; 4678 4679 struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env; 4680 }; 4681 4682 enum { 4683 MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS = 0x0, 4684 }; 4685 4686 struct mlx5_ifc_query_vnic_env_in_bits { 4687 u8 opcode[0x10]; 4688 u8 reserved_at_10[0x10]; 4689 4690 u8 reserved_at_20[0x10]; 4691 u8 op_mod[0x10]; 4692 4693 u8 other_vport[0x1]; 4694 u8 reserved_at_41[0xf]; 4695 u8 vport_number[0x10]; 4696 4697 u8 reserved_at_60[0x20]; 4698 }; 4699 4700 struct mlx5_ifc_query_vport_counter_out_bits { 4701 u8 status[0x8]; 4702 u8 reserved_at_8[0x18]; 4703 4704 u8 syndrome[0x20]; 4705 4706 u8 reserved_at_40[0x40]; 4707 4708 struct mlx5_ifc_traffic_counter_bits received_errors; 4709 4710 struct mlx5_ifc_traffic_counter_bits transmit_errors; 4711 4712 struct mlx5_ifc_traffic_counter_bits received_ib_unicast; 4713 4714 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast; 4715 4716 struct mlx5_ifc_traffic_counter_bits received_ib_multicast; 4717 4718 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast; 4719 4720 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast; 4721 4722 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast; 4723 4724 struct mlx5_ifc_traffic_counter_bits received_eth_unicast; 4725 4726 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast; 4727 4728 struct mlx5_ifc_traffic_counter_bits received_eth_multicast; 4729 4730 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast; 4731 4732 u8 reserved_at_680[0xa00]; 4733 }; 4734 4735 enum { 4736 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0, 4737 }; 4738 4739 struct mlx5_ifc_query_vport_counter_in_bits { 4740 u8 opcode[0x10]; 4741 u8 reserved_at_10[0x10]; 4742 4743 u8 reserved_at_20[0x10]; 4744 u8 op_mod[0x10]; 4745 4746 u8 other_vport[0x1]; 4747 u8 reserved_at_41[0xb]; 4748 u8 port_num[0x4]; 4749 u8 vport_number[0x10]; 4750 4751 u8 reserved_at_60[0x60]; 4752 4753 u8 clear[0x1]; 4754 u8 reserved_at_c1[0x1f]; 4755 4756 u8 reserved_at_e0[0x20]; 4757 }; 4758 4759 struct mlx5_ifc_query_tis_out_bits { 4760 u8 status[0x8]; 4761 u8 reserved_at_8[0x18]; 4762 4763 u8 syndrome[0x20]; 4764 4765 u8 reserved_at_40[0x40]; 4766 4767 struct mlx5_ifc_tisc_bits tis_context; 4768 }; 4769 4770 struct mlx5_ifc_query_tis_in_bits { 4771 u8 opcode[0x10]; 4772 u8 reserved_at_10[0x10]; 4773 4774 u8 reserved_at_20[0x10]; 4775 u8 op_mod[0x10]; 4776 4777 u8 reserved_at_40[0x8]; 4778 u8 tisn[0x18]; 4779 4780 u8 reserved_at_60[0x20]; 4781 }; 4782 4783 struct mlx5_ifc_query_tir_out_bits { 4784 u8 status[0x8]; 4785 u8 reserved_at_8[0x18]; 4786 4787 u8 syndrome[0x20]; 4788 4789 u8 reserved_at_40[0xc0]; 4790 4791 struct mlx5_ifc_tirc_bits tir_context; 4792 }; 4793 4794 struct mlx5_ifc_query_tir_in_bits { 4795 u8 opcode[0x10]; 4796 u8 reserved_at_10[0x10]; 4797 4798 u8 reserved_at_20[0x10]; 4799 u8 op_mod[0x10]; 4800 4801 u8 reserved_at_40[0x8]; 4802 u8 tirn[0x18]; 4803 4804 u8 reserved_at_60[0x20]; 4805 }; 4806 4807 struct mlx5_ifc_query_srq_out_bits { 4808 u8 status[0x8]; 4809 u8 reserved_at_8[0x18]; 4810 4811 u8 syndrome[0x20]; 4812 4813 u8 reserved_at_40[0x40]; 4814 4815 struct mlx5_ifc_srqc_bits srq_context_entry; 4816 4817 u8 reserved_at_280[0x600]; 4818 4819 u8 pas[][0x40]; 4820 }; 4821 4822 struct mlx5_ifc_query_srq_in_bits { 4823 u8 opcode[0x10]; 4824 u8 reserved_at_10[0x10]; 4825 4826 u8 reserved_at_20[0x10]; 4827 u8 op_mod[0x10]; 4828 4829 u8 reserved_at_40[0x8]; 4830 u8 srqn[0x18]; 4831 4832 u8 reserved_at_60[0x20]; 4833 }; 4834 4835 struct mlx5_ifc_query_sq_out_bits { 4836 u8 status[0x8]; 4837 u8 reserved_at_8[0x18]; 4838 4839 u8 syndrome[0x20]; 4840 4841 u8 reserved_at_40[0xc0]; 4842 4843 struct mlx5_ifc_sqc_bits sq_context; 4844 }; 4845 4846 struct mlx5_ifc_query_sq_in_bits { 4847 u8 opcode[0x10]; 4848 u8 reserved_at_10[0x10]; 4849 4850 u8 reserved_at_20[0x10]; 4851 u8 op_mod[0x10]; 4852 4853 u8 reserved_at_40[0x8]; 4854 u8 sqn[0x18]; 4855 4856 u8 reserved_at_60[0x20]; 4857 }; 4858 4859 struct mlx5_ifc_query_special_contexts_out_bits { 4860 u8 status[0x8]; 4861 u8 reserved_at_8[0x18]; 4862 4863 u8 syndrome[0x20]; 4864 4865 u8 dump_fill_mkey[0x20]; 4866 4867 u8 resd_lkey[0x20]; 4868 4869 u8 null_mkey[0x20]; 4870 4871 u8 reserved_at_a0[0x60]; 4872 }; 4873 4874 struct mlx5_ifc_query_special_contexts_in_bits { 4875 u8 opcode[0x10]; 4876 u8 reserved_at_10[0x10]; 4877 4878 u8 reserved_at_20[0x10]; 4879 u8 op_mod[0x10]; 4880 4881 u8 reserved_at_40[0x40]; 4882 }; 4883 4884 struct mlx5_ifc_query_scheduling_element_out_bits { 4885 u8 opcode[0x10]; 4886 u8 reserved_at_10[0x10]; 4887 4888 u8 reserved_at_20[0x10]; 4889 u8 op_mod[0x10]; 4890 4891 u8 reserved_at_40[0xc0]; 4892 4893 struct mlx5_ifc_scheduling_context_bits scheduling_context; 4894 4895 u8 reserved_at_300[0x100]; 4896 }; 4897 4898 enum { 4899 SCHEDULING_HIERARCHY_E_SWITCH = 0x2, 4900 SCHEDULING_HIERARCHY_NIC = 0x3, 4901 }; 4902 4903 struct mlx5_ifc_query_scheduling_element_in_bits { 4904 u8 opcode[0x10]; 4905 u8 reserved_at_10[0x10]; 4906 4907 u8 reserved_at_20[0x10]; 4908 u8 op_mod[0x10]; 4909 4910 u8 scheduling_hierarchy[0x8]; 4911 u8 reserved_at_48[0x18]; 4912 4913 u8 scheduling_element_id[0x20]; 4914 4915 u8 reserved_at_80[0x180]; 4916 }; 4917 4918 struct mlx5_ifc_query_rqt_out_bits { 4919 u8 status[0x8]; 4920 u8 reserved_at_8[0x18]; 4921 4922 u8 syndrome[0x20]; 4923 4924 u8 reserved_at_40[0xc0]; 4925 4926 struct mlx5_ifc_rqtc_bits rqt_context; 4927 }; 4928 4929 struct mlx5_ifc_query_rqt_in_bits { 4930 u8 opcode[0x10]; 4931 u8 reserved_at_10[0x10]; 4932 4933 u8 reserved_at_20[0x10]; 4934 u8 op_mod[0x10]; 4935 4936 u8 reserved_at_40[0x8]; 4937 u8 rqtn[0x18]; 4938 4939 u8 reserved_at_60[0x20]; 4940 }; 4941 4942 struct mlx5_ifc_query_rq_out_bits { 4943 u8 status[0x8]; 4944 u8 reserved_at_8[0x18]; 4945 4946 u8 syndrome[0x20]; 4947 4948 u8 reserved_at_40[0xc0]; 4949 4950 struct mlx5_ifc_rqc_bits rq_context; 4951 }; 4952 4953 struct mlx5_ifc_query_rq_in_bits { 4954 u8 opcode[0x10]; 4955 u8 reserved_at_10[0x10]; 4956 4957 u8 reserved_at_20[0x10]; 4958 u8 op_mod[0x10]; 4959 4960 u8 reserved_at_40[0x8]; 4961 u8 rqn[0x18]; 4962 4963 u8 reserved_at_60[0x20]; 4964 }; 4965 4966 struct mlx5_ifc_query_roce_address_out_bits { 4967 u8 status[0x8]; 4968 u8 reserved_at_8[0x18]; 4969 4970 u8 syndrome[0x20]; 4971 4972 u8 reserved_at_40[0x40]; 4973 4974 struct mlx5_ifc_roce_addr_layout_bits roce_address; 4975 }; 4976 4977 struct mlx5_ifc_query_roce_address_in_bits { 4978 u8 opcode[0x10]; 4979 u8 reserved_at_10[0x10]; 4980 4981 u8 reserved_at_20[0x10]; 4982 u8 op_mod[0x10]; 4983 4984 u8 roce_address_index[0x10]; 4985 u8 reserved_at_50[0xc]; 4986 u8 vhca_port_num[0x4]; 4987 4988 u8 reserved_at_60[0x20]; 4989 }; 4990 4991 struct mlx5_ifc_query_rmp_out_bits { 4992 u8 status[0x8]; 4993 u8 reserved_at_8[0x18]; 4994 4995 u8 syndrome[0x20]; 4996 4997 u8 reserved_at_40[0xc0]; 4998 4999 struct mlx5_ifc_rmpc_bits rmp_context; 5000 }; 5001 5002 struct mlx5_ifc_query_rmp_in_bits { 5003 u8 opcode[0x10]; 5004 u8 reserved_at_10[0x10]; 5005 5006 u8 reserved_at_20[0x10]; 5007 u8 op_mod[0x10]; 5008 5009 u8 reserved_at_40[0x8]; 5010 u8 rmpn[0x18]; 5011 5012 u8 reserved_at_60[0x20]; 5013 }; 5014 5015 struct mlx5_ifc_query_qp_out_bits { 5016 u8 status[0x8]; 5017 u8 reserved_at_8[0x18]; 5018 5019 u8 syndrome[0x20]; 5020 5021 u8 reserved_at_40[0x20]; 5022 u8 ece[0x20]; 5023 5024 u8 opt_param_mask[0x20]; 5025 5026 u8 reserved_at_a0[0x20]; 5027 5028 struct mlx5_ifc_qpc_bits qpc; 5029 5030 u8 reserved_at_800[0x80]; 5031 5032 u8 pas[][0x40]; 5033 }; 5034 5035 struct mlx5_ifc_query_qp_in_bits { 5036 u8 opcode[0x10]; 5037 u8 reserved_at_10[0x10]; 5038 5039 u8 reserved_at_20[0x10]; 5040 u8 op_mod[0x10]; 5041 5042 u8 reserved_at_40[0x8]; 5043 u8 qpn[0x18]; 5044 5045 u8 reserved_at_60[0x20]; 5046 }; 5047 5048 struct mlx5_ifc_query_q_counter_out_bits { 5049 u8 status[0x8]; 5050 u8 reserved_at_8[0x18]; 5051 5052 u8 syndrome[0x20]; 5053 5054 u8 reserved_at_40[0x40]; 5055 5056 u8 rx_write_requests[0x20]; 5057 5058 u8 reserved_at_a0[0x20]; 5059 5060 u8 rx_read_requests[0x20]; 5061 5062 u8 reserved_at_e0[0x20]; 5063 5064 u8 rx_atomic_requests[0x20]; 5065 5066 u8 reserved_at_120[0x20]; 5067 5068 u8 rx_dct_connect[0x20]; 5069 5070 u8 reserved_at_160[0x20]; 5071 5072 u8 out_of_buffer[0x20]; 5073 5074 u8 reserved_at_1a0[0x20]; 5075 5076 u8 out_of_sequence[0x20]; 5077 5078 u8 reserved_at_1e0[0x20]; 5079 5080 u8 duplicate_request[0x20]; 5081 5082 u8 reserved_at_220[0x20]; 5083 5084 u8 rnr_nak_retry_err[0x20]; 5085 5086 u8 reserved_at_260[0x20]; 5087 5088 u8 packet_seq_err[0x20]; 5089 5090 u8 reserved_at_2a0[0x20]; 5091 5092 u8 implied_nak_seq_err[0x20]; 5093 5094 u8 reserved_at_2e0[0x20]; 5095 5096 u8 local_ack_timeout_err[0x20]; 5097 5098 u8 reserved_at_320[0xa0]; 5099 5100 u8 resp_local_length_error[0x20]; 5101 5102 u8 req_local_length_error[0x20]; 5103 5104 u8 resp_local_qp_error[0x20]; 5105 5106 u8 local_operation_error[0x20]; 5107 5108 u8 resp_local_protection[0x20]; 5109 5110 u8 req_local_protection[0x20]; 5111 5112 u8 resp_cqe_error[0x20]; 5113 5114 u8 req_cqe_error[0x20]; 5115 5116 u8 req_mw_binding[0x20]; 5117 5118 u8 req_bad_response[0x20]; 5119 5120 u8 req_remote_invalid_request[0x20]; 5121 5122 u8 resp_remote_invalid_request[0x20]; 5123 5124 u8 req_remote_access_errors[0x20]; 5125 5126 u8 resp_remote_access_errors[0x20]; 5127 5128 u8 req_remote_operation_errors[0x20]; 5129 5130 u8 req_transport_retries_exceeded[0x20]; 5131 5132 u8 cq_overflow[0x20]; 5133 5134 u8 resp_cqe_flush_error[0x20]; 5135 5136 u8 req_cqe_flush_error[0x20]; 5137 5138 u8 reserved_at_620[0x20]; 5139 5140 u8 roce_adp_retrans[0x20]; 5141 5142 u8 roce_adp_retrans_to[0x20]; 5143 5144 u8 roce_slow_restart[0x20]; 5145 5146 u8 roce_slow_restart_cnps[0x20]; 5147 5148 u8 roce_slow_restart_trans[0x20]; 5149 5150 u8 reserved_at_6e0[0x120]; 5151 }; 5152 5153 struct mlx5_ifc_query_q_counter_in_bits { 5154 u8 opcode[0x10]; 5155 u8 reserved_at_10[0x10]; 5156 5157 u8 reserved_at_20[0x10]; 5158 u8 op_mod[0x10]; 5159 5160 u8 reserved_at_40[0x80]; 5161 5162 u8 clear[0x1]; 5163 u8 reserved_at_c1[0x1f]; 5164 5165 u8 reserved_at_e0[0x18]; 5166 u8 counter_set_id[0x8]; 5167 }; 5168 5169 struct mlx5_ifc_query_pages_out_bits { 5170 u8 status[0x8]; 5171 u8 reserved_at_8[0x18]; 5172 5173 u8 syndrome[0x20]; 5174 5175 u8 embedded_cpu_function[0x1]; 5176 u8 reserved_at_41[0xf]; 5177 u8 function_id[0x10]; 5178 5179 u8 num_pages[0x20]; 5180 }; 5181 5182 enum { 5183 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1, 5184 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2, 5185 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3, 5186 }; 5187 5188 struct mlx5_ifc_query_pages_in_bits { 5189 u8 opcode[0x10]; 5190 u8 reserved_at_10[0x10]; 5191 5192 u8 reserved_at_20[0x10]; 5193 u8 op_mod[0x10]; 5194 5195 u8 embedded_cpu_function[0x1]; 5196 u8 reserved_at_41[0xf]; 5197 u8 function_id[0x10]; 5198 5199 u8 reserved_at_60[0x20]; 5200 }; 5201 5202 struct mlx5_ifc_query_nic_vport_context_out_bits { 5203 u8 status[0x8]; 5204 u8 reserved_at_8[0x18]; 5205 5206 u8 syndrome[0x20]; 5207 5208 u8 reserved_at_40[0x40]; 5209 5210 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 5211 }; 5212 5213 struct mlx5_ifc_query_nic_vport_context_in_bits { 5214 u8 opcode[0x10]; 5215 u8 reserved_at_10[0x10]; 5216 5217 u8 reserved_at_20[0x10]; 5218 u8 op_mod[0x10]; 5219 5220 u8 other_vport[0x1]; 5221 u8 reserved_at_41[0xf]; 5222 u8 vport_number[0x10]; 5223 5224 u8 reserved_at_60[0x5]; 5225 u8 allowed_list_type[0x3]; 5226 u8 reserved_at_68[0x18]; 5227 }; 5228 5229 struct mlx5_ifc_query_mkey_out_bits { 5230 u8 status[0x8]; 5231 u8 reserved_at_8[0x18]; 5232 5233 u8 syndrome[0x20]; 5234 5235 u8 reserved_at_40[0x40]; 5236 5237 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 5238 5239 u8 reserved_at_280[0x600]; 5240 5241 u8 bsf0_klm0_pas_mtt0_1[16][0x8]; 5242 5243 u8 bsf1_klm1_pas_mtt2_3[16][0x8]; 5244 }; 5245 5246 struct mlx5_ifc_query_mkey_in_bits { 5247 u8 opcode[0x10]; 5248 u8 reserved_at_10[0x10]; 5249 5250 u8 reserved_at_20[0x10]; 5251 u8 op_mod[0x10]; 5252 5253 u8 reserved_at_40[0x8]; 5254 u8 mkey_index[0x18]; 5255 5256 u8 pg_access[0x1]; 5257 u8 reserved_at_61[0x1f]; 5258 }; 5259 5260 struct mlx5_ifc_query_mad_demux_out_bits { 5261 u8 status[0x8]; 5262 u8 reserved_at_8[0x18]; 5263 5264 u8 syndrome[0x20]; 5265 5266 u8 reserved_at_40[0x40]; 5267 5268 u8 mad_dumux_parameters_block[0x20]; 5269 }; 5270 5271 struct mlx5_ifc_query_mad_demux_in_bits { 5272 u8 opcode[0x10]; 5273 u8 reserved_at_10[0x10]; 5274 5275 u8 reserved_at_20[0x10]; 5276 u8 op_mod[0x10]; 5277 5278 u8 reserved_at_40[0x40]; 5279 }; 5280 5281 struct mlx5_ifc_query_l2_table_entry_out_bits { 5282 u8 status[0x8]; 5283 u8 reserved_at_8[0x18]; 5284 5285 u8 syndrome[0x20]; 5286 5287 u8 reserved_at_40[0xa0]; 5288 5289 u8 reserved_at_e0[0x13]; 5290 u8 vlan_valid[0x1]; 5291 u8 vlan[0xc]; 5292 5293 struct mlx5_ifc_mac_address_layout_bits mac_address; 5294 5295 u8 reserved_at_140[0xc0]; 5296 }; 5297 5298 struct mlx5_ifc_query_l2_table_entry_in_bits { 5299 u8 opcode[0x10]; 5300 u8 reserved_at_10[0x10]; 5301 5302 u8 reserved_at_20[0x10]; 5303 u8 op_mod[0x10]; 5304 5305 u8 reserved_at_40[0x60]; 5306 5307 u8 reserved_at_a0[0x8]; 5308 u8 table_index[0x18]; 5309 5310 u8 reserved_at_c0[0x140]; 5311 }; 5312 5313 struct mlx5_ifc_query_issi_out_bits { 5314 u8 status[0x8]; 5315 u8 reserved_at_8[0x18]; 5316 5317 u8 syndrome[0x20]; 5318 5319 u8 reserved_at_40[0x10]; 5320 u8 current_issi[0x10]; 5321 5322 u8 reserved_at_60[0xa0]; 5323 5324 u8 reserved_at_100[76][0x8]; 5325 u8 supported_issi_dw0[0x20]; 5326 }; 5327 5328 struct mlx5_ifc_query_issi_in_bits { 5329 u8 opcode[0x10]; 5330 u8 reserved_at_10[0x10]; 5331 5332 u8 reserved_at_20[0x10]; 5333 u8 op_mod[0x10]; 5334 5335 u8 reserved_at_40[0x40]; 5336 }; 5337 5338 struct mlx5_ifc_set_driver_version_out_bits { 5339 u8 status[0x8]; 5340 u8 reserved_0[0x18]; 5341 5342 u8 syndrome[0x20]; 5343 u8 reserved_1[0x40]; 5344 }; 5345 5346 struct mlx5_ifc_set_driver_version_in_bits { 5347 u8 opcode[0x10]; 5348 u8 reserved_0[0x10]; 5349 5350 u8 reserved_1[0x10]; 5351 u8 op_mod[0x10]; 5352 5353 u8 reserved_2[0x40]; 5354 u8 driver_version[64][0x8]; 5355 }; 5356 5357 struct mlx5_ifc_query_hca_vport_pkey_out_bits { 5358 u8 status[0x8]; 5359 u8 reserved_at_8[0x18]; 5360 5361 u8 syndrome[0x20]; 5362 5363 u8 reserved_at_40[0x40]; 5364 5365 struct mlx5_ifc_pkey_bits pkey[]; 5366 }; 5367 5368 struct mlx5_ifc_query_hca_vport_pkey_in_bits { 5369 u8 opcode[0x10]; 5370 u8 reserved_at_10[0x10]; 5371 5372 u8 reserved_at_20[0x10]; 5373 u8 op_mod[0x10]; 5374 5375 u8 other_vport[0x1]; 5376 u8 reserved_at_41[0xb]; 5377 u8 port_num[0x4]; 5378 u8 vport_number[0x10]; 5379 5380 u8 reserved_at_60[0x10]; 5381 u8 pkey_index[0x10]; 5382 }; 5383 5384 enum { 5385 MLX5_HCA_VPORT_SEL_PORT_GUID = 1 << 0, 5386 MLX5_HCA_VPORT_SEL_NODE_GUID = 1 << 1, 5387 MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2, 5388 }; 5389 5390 struct mlx5_ifc_query_hca_vport_gid_out_bits { 5391 u8 status[0x8]; 5392 u8 reserved_at_8[0x18]; 5393 5394 u8 syndrome[0x20]; 5395 5396 u8 reserved_at_40[0x20]; 5397 5398 u8 gids_num[0x10]; 5399 u8 reserved_at_70[0x10]; 5400 5401 struct mlx5_ifc_array128_auto_bits gid[]; 5402 }; 5403 5404 struct mlx5_ifc_query_hca_vport_gid_in_bits { 5405 u8 opcode[0x10]; 5406 u8 reserved_at_10[0x10]; 5407 5408 u8 reserved_at_20[0x10]; 5409 u8 op_mod[0x10]; 5410 5411 u8 other_vport[0x1]; 5412 u8 reserved_at_41[0xb]; 5413 u8 port_num[0x4]; 5414 u8 vport_number[0x10]; 5415 5416 u8 reserved_at_60[0x10]; 5417 u8 gid_index[0x10]; 5418 }; 5419 5420 struct mlx5_ifc_query_hca_vport_context_out_bits { 5421 u8 status[0x8]; 5422 u8 reserved_at_8[0x18]; 5423 5424 u8 syndrome[0x20]; 5425 5426 u8 reserved_at_40[0x40]; 5427 5428 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 5429 }; 5430 5431 struct mlx5_ifc_query_hca_vport_context_in_bits { 5432 u8 opcode[0x10]; 5433 u8 reserved_at_10[0x10]; 5434 5435 u8 reserved_at_20[0x10]; 5436 u8 op_mod[0x10]; 5437 5438 u8 other_vport[0x1]; 5439 u8 reserved_at_41[0xb]; 5440 u8 port_num[0x4]; 5441 u8 vport_number[0x10]; 5442 5443 u8 reserved_at_60[0x20]; 5444 }; 5445 5446 struct mlx5_ifc_query_hca_cap_out_bits { 5447 u8 status[0x8]; 5448 u8 reserved_at_8[0x18]; 5449 5450 u8 syndrome[0x20]; 5451 5452 u8 reserved_at_40[0x40]; 5453 5454 union mlx5_ifc_hca_cap_union_bits capability; 5455 }; 5456 5457 struct mlx5_ifc_query_hca_cap_in_bits { 5458 u8 opcode[0x10]; 5459 u8 reserved_at_10[0x10]; 5460 5461 u8 reserved_at_20[0x10]; 5462 u8 op_mod[0x10]; 5463 5464 u8 other_function[0x1]; 5465 u8 reserved_at_41[0xf]; 5466 u8 function_id[0x10]; 5467 5468 u8 reserved_at_60[0x20]; 5469 }; 5470 5471 struct mlx5_ifc_other_hca_cap_bits { 5472 u8 roce[0x1]; 5473 u8 reserved_at_1[0x27f]; 5474 }; 5475 5476 struct mlx5_ifc_query_other_hca_cap_out_bits { 5477 u8 status[0x8]; 5478 u8 reserved_at_8[0x18]; 5479 5480 u8 syndrome[0x20]; 5481 5482 u8 reserved_at_40[0x40]; 5483 5484 struct mlx5_ifc_other_hca_cap_bits other_capability; 5485 }; 5486 5487 struct mlx5_ifc_query_other_hca_cap_in_bits { 5488 u8 opcode[0x10]; 5489 u8 reserved_at_10[0x10]; 5490 5491 u8 reserved_at_20[0x10]; 5492 u8 op_mod[0x10]; 5493 5494 u8 reserved_at_40[0x10]; 5495 u8 function_id[0x10]; 5496 5497 u8 reserved_at_60[0x20]; 5498 }; 5499 5500 struct mlx5_ifc_modify_other_hca_cap_out_bits { 5501 u8 status[0x8]; 5502 u8 reserved_at_8[0x18]; 5503 5504 u8 syndrome[0x20]; 5505 5506 u8 reserved_at_40[0x40]; 5507 }; 5508 5509 struct mlx5_ifc_modify_other_hca_cap_in_bits { 5510 u8 opcode[0x10]; 5511 u8 reserved_at_10[0x10]; 5512 5513 u8 reserved_at_20[0x10]; 5514 u8 op_mod[0x10]; 5515 5516 u8 reserved_at_40[0x10]; 5517 u8 function_id[0x10]; 5518 u8 field_select[0x20]; 5519 5520 struct mlx5_ifc_other_hca_cap_bits other_capability; 5521 }; 5522 5523 struct mlx5_ifc_flow_table_context_bits { 5524 u8 reformat_en[0x1]; 5525 u8 decap_en[0x1]; 5526 u8 sw_owner[0x1]; 5527 u8 termination_table[0x1]; 5528 u8 table_miss_action[0x4]; 5529 u8 level[0x8]; 5530 u8 reserved_at_10[0x8]; 5531 u8 log_size[0x8]; 5532 5533 u8 reserved_at_20[0x8]; 5534 u8 table_miss_id[0x18]; 5535 5536 u8 reserved_at_40[0x8]; 5537 u8 lag_master_next_table_id[0x18]; 5538 5539 u8 reserved_at_60[0x60]; 5540 5541 u8 sw_owner_icm_root_1[0x40]; 5542 5543 u8 sw_owner_icm_root_0[0x40]; 5544 5545 }; 5546 5547 struct mlx5_ifc_query_flow_table_out_bits { 5548 u8 status[0x8]; 5549 u8 reserved_at_8[0x18]; 5550 5551 u8 syndrome[0x20]; 5552 5553 u8 reserved_at_40[0x80]; 5554 5555 struct mlx5_ifc_flow_table_context_bits flow_table_context; 5556 }; 5557 5558 struct mlx5_ifc_query_flow_table_in_bits { 5559 u8 opcode[0x10]; 5560 u8 reserved_at_10[0x10]; 5561 5562 u8 reserved_at_20[0x10]; 5563 u8 op_mod[0x10]; 5564 5565 u8 reserved_at_40[0x40]; 5566 5567 u8 table_type[0x8]; 5568 u8 reserved_at_88[0x18]; 5569 5570 u8 reserved_at_a0[0x8]; 5571 u8 table_id[0x18]; 5572 5573 u8 reserved_at_c0[0x140]; 5574 }; 5575 5576 struct mlx5_ifc_query_fte_out_bits { 5577 u8 status[0x8]; 5578 u8 reserved_at_8[0x18]; 5579 5580 u8 syndrome[0x20]; 5581 5582 u8 reserved_at_40[0x1c0]; 5583 5584 struct mlx5_ifc_flow_context_bits flow_context; 5585 }; 5586 5587 struct mlx5_ifc_query_fte_in_bits { 5588 u8 opcode[0x10]; 5589 u8 reserved_at_10[0x10]; 5590 5591 u8 reserved_at_20[0x10]; 5592 u8 op_mod[0x10]; 5593 5594 u8 reserved_at_40[0x40]; 5595 5596 u8 table_type[0x8]; 5597 u8 reserved_at_88[0x18]; 5598 5599 u8 reserved_at_a0[0x8]; 5600 u8 table_id[0x18]; 5601 5602 u8 reserved_at_c0[0x40]; 5603 5604 u8 flow_index[0x20]; 5605 5606 u8 reserved_at_120[0xe0]; 5607 }; 5608 5609 enum { 5610 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 5611 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 5612 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 5613 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3, 5614 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_3 = 0x4, 5615 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_4 = 0x5, 5616 }; 5617 5618 struct mlx5_ifc_query_flow_group_out_bits { 5619 u8 status[0x8]; 5620 u8 reserved_at_8[0x18]; 5621 5622 u8 syndrome[0x20]; 5623 5624 u8 reserved_at_40[0xa0]; 5625 5626 u8 start_flow_index[0x20]; 5627 5628 u8 reserved_at_100[0x20]; 5629 5630 u8 end_flow_index[0x20]; 5631 5632 u8 reserved_at_140[0xa0]; 5633 5634 u8 reserved_at_1e0[0x18]; 5635 u8 match_criteria_enable[0x8]; 5636 5637 struct mlx5_ifc_fte_match_param_bits match_criteria; 5638 5639 u8 reserved_at_1200[0xe00]; 5640 }; 5641 5642 struct mlx5_ifc_query_flow_group_in_bits { 5643 u8 opcode[0x10]; 5644 u8 reserved_at_10[0x10]; 5645 5646 u8 reserved_at_20[0x10]; 5647 u8 op_mod[0x10]; 5648 5649 u8 reserved_at_40[0x40]; 5650 5651 u8 table_type[0x8]; 5652 u8 reserved_at_88[0x18]; 5653 5654 u8 reserved_at_a0[0x8]; 5655 u8 table_id[0x18]; 5656 5657 u8 group_id[0x20]; 5658 5659 u8 reserved_at_e0[0x120]; 5660 }; 5661 5662 struct mlx5_ifc_query_flow_counter_out_bits { 5663 u8 status[0x8]; 5664 u8 reserved_at_8[0x18]; 5665 5666 u8 syndrome[0x20]; 5667 5668 u8 reserved_at_40[0x40]; 5669 5670 struct mlx5_ifc_traffic_counter_bits flow_statistics[]; 5671 }; 5672 5673 struct mlx5_ifc_query_flow_counter_in_bits { 5674 u8 opcode[0x10]; 5675 u8 reserved_at_10[0x10]; 5676 5677 u8 reserved_at_20[0x10]; 5678 u8 op_mod[0x10]; 5679 5680 u8 reserved_at_40[0x80]; 5681 5682 u8 clear[0x1]; 5683 u8 reserved_at_c1[0xf]; 5684 u8 num_of_counters[0x10]; 5685 5686 u8 flow_counter_id[0x20]; 5687 }; 5688 5689 struct mlx5_ifc_query_esw_vport_context_out_bits { 5690 u8 status[0x8]; 5691 u8 reserved_at_8[0x18]; 5692 5693 u8 syndrome[0x20]; 5694 5695 u8 reserved_at_40[0x40]; 5696 5697 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 5698 }; 5699 5700 struct mlx5_ifc_query_esw_vport_context_in_bits { 5701 u8 opcode[0x10]; 5702 u8 reserved_at_10[0x10]; 5703 5704 u8 reserved_at_20[0x10]; 5705 u8 op_mod[0x10]; 5706 5707 u8 other_vport[0x1]; 5708 u8 reserved_at_41[0xf]; 5709 u8 vport_number[0x10]; 5710 5711 u8 reserved_at_60[0x20]; 5712 }; 5713 5714 struct mlx5_ifc_modify_esw_vport_context_out_bits { 5715 u8 status[0x8]; 5716 u8 reserved_at_8[0x18]; 5717 5718 u8 syndrome[0x20]; 5719 5720 u8 reserved_at_40[0x40]; 5721 }; 5722 5723 struct mlx5_ifc_esw_vport_context_fields_select_bits { 5724 u8 reserved_at_0[0x1b]; 5725 u8 fdb_to_vport_reg_c_id[0x1]; 5726 u8 vport_cvlan_insert[0x1]; 5727 u8 vport_svlan_insert[0x1]; 5728 u8 vport_cvlan_strip[0x1]; 5729 u8 vport_svlan_strip[0x1]; 5730 }; 5731 5732 struct mlx5_ifc_modify_esw_vport_context_in_bits { 5733 u8 opcode[0x10]; 5734 u8 reserved_at_10[0x10]; 5735 5736 u8 reserved_at_20[0x10]; 5737 u8 op_mod[0x10]; 5738 5739 u8 other_vport[0x1]; 5740 u8 reserved_at_41[0xf]; 5741 u8 vport_number[0x10]; 5742 5743 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select; 5744 5745 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 5746 }; 5747 5748 struct mlx5_ifc_query_eq_out_bits { 5749 u8 status[0x8]; 5750 u8 reserved_at_8[0x18]; 5751 5752 u8 syndrome[0x20]; 5753 5754 u8 reserved_at_40[0x40]; 5755 5756 struct mlx5_ifc_eqc_bits eq_context_entry; 5757 5758 u8 reserved_at_280[0x40]; 5759 5760 u8 event_bitmask[0x40]; 5761 5762 u8 reserved_at_300[0x580]; 5763 5764 u8 pas[][0x40]; 5765 }; 5766 5767 struct mlx5_ifc_query_eq_in_bits { 5768 u8 opcode[0x10]; 5769 u8 reserved_at_10[0x10]; 5770 5771 u8 reserved_at_20[0x10]; 5772 u8 op_mod[0x10]; 5773 5774 u8 reserved_at_40[0x18]; 5775 u8 eq_number[0x8]; 5776 5777 u8 reserved_at_60[0x20]; 5778 }; 5779 5780 struct mlx5_ifc_packet_reformat_context_in_bits { 5781 u8 reserved_at_0[0x5]; 5782 u8 reformat_type[0x3]; 5783 u8 reserved_at_8[0xe]; 5784 u8 reformat_data_size[0xa]; 5785 5786 u8 reserved_at_20[0x10]; 5787 u8 reformat_data[2][0x8]; 5788 5789 u8 more_reformat_data[][0x8]; 5790 }; 5791 5792 struct mlx5_ifc_query_packet_reformat_context_out_bits { 5793 u8 status[0x8]; 5794 u8 reserved_at_8[0x18]; 5795 5796 u8 syndrome[0x20]; 5797 5798 u8 reserved_at_40[0xa0]; 5799 5800 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context[]; 5801 }; 5802 5803 struct mlx5_ifc_query_packet_reformat_context_in_bits { 5804 u8 opcode[0x10]; 5805 u8 reserved_at_10[0x10]; 5806 5807 u8 reserved_at_20[0x10]; 5808 u8 op_mod[0x10]; 5809 5810 u8 packet_reformat_id[0x20]; 5811 5812 u8 reserved_at_60[0xa0]; 5813 }; 5814 5815 struct mlx5_ifc_alloc_packet_reformat_context_out_bits { 5816 u8 status[0x8]; 5817 u8 reserved_at_8[0x18]; 5818 5819 u8 syndrome[0x20]; 5820 5821 u8 packet_reformat_id[0x20]; 5822 5823 u8 reserved_at_60[0x20]; 5824 }; 5825 5826 enum mlx5_reformat_ctx_type { 5827 MLX5_REFORMAT_TYPE_L2_TO_VXLAN = 0x0, 5828 MLX5_REFORMAT_TYPE_L2_TO_NVGRE = 0x1, 5829 MLX5_REFORMAT_TYPE_L2_TO_L2_TUNNEL = 0x2, 5830 MLX5_REFORMAT_TYPE_L3_TUNNEL_TO_L2 = 0x3, 5831 MLX5_REFORMAT_TYPE_L2_TO_L3_TUNNEL = 0x4, 5832 }; 5833 5834 struct mlx5_ifc_alloc_packet_reformat_context_in_bits { 5835 u8 opcode[0x10]; 5836 u8 reserved_at_10[0x10]; 5837 5838 u8 reserved_at_20[0x10]; 5839 u8 op_mod[0x10]; 5840 5841 u8 reserved_at_40[0xa0]; 5842 5843 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context; 5844 }; 5845 5846 struct mlx5_ifc_dealloc_packet_reformat_context_out_bits { 5847 u8 status[0x8]; 5848 u8 reserved_at_8[0x18]; 5849 5850 u8 syndrome[0x20]; 5851 5852 u8 reserved_at_40[0x40]; 5853 }; 5854 5855 struct mlx5_ifc_dealloc_packet_reformat_context_in_bits { 5856 u8 opcode[0x10]; 5857 u8 reserved_at_10[0x10]; 5858 5859 u8 reserved_20[0x10]; 5860 u8 op_mod[0x10]; 5861 5862 u8 packet_reformat_id[0x20]; 5863 5864 u8 reserved_60[0x20]; 5865 }; 5866 5867 struct mlx5_ifc_set_action_in_bits { 5868 u8 action_type[0x4]; 5869 u8 field[0xc]; 5870 u8 reserved_at_10[0x3]; 5871 u8 offset[0x5]; 5872 u8 reserved_at_18[0x3]; 5873 u8 length[0x5]; 5874 5875 u8 data[0x20]; 5876 }; 5877 5878 struct mlx5_ifc_add_action_in_bits { 5879 u8 action_type[0x4]; 5880 u8 field[0xc]; 5881 u8 reserved_at_10[0x10]; 5882 5883 u8 data[0x20]; 5884 }; 5885 5886 struct mlx5_ifc_copy_action_in_bits { 5887 u8 action_type[0x4]; 5888 u8 src_field[0xc]; 5889 u8 reserved_at_10[0x3]; 5890 u8 src_offset[0x5]; 5891 u8 reserved_at_18[0x3]; 5892 u8 length[0x5]; 5893 5894 u8 reserved_at_20[0x4]; 5895 u8 dst_field[0xc]; 5896 u8 reserved_at_30[0x3]; 5897 u8 dst_offset[0x5]; 5898 u8 reserved_at_38[0x8]; 5899 }; 5900 5901 union mlx5_ifc_set_add_copy_action_in_auto_bits { 5902 struct mlx5_ifc_set_action_in_bits set_action_in; 5903 struct mlx5_ifc_add_action_in_bits add_action_in; 5904 struct mlx5_ifc_copy_action_in_bits copy_action_in; 5905 u8 reserved_at_0[0x40]; 5906 }; 5907 5908 enum { 5909 MLX5_ACTION_TYPE_SET = 0x1, 5910 MLX5_ACTION_TYPE_ADD = 0x2, 5911 MLX5_ACTION_TYPE_COPY = 0x3, 5912 }; 5913 5914 enum { 5915 MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16 = 0x1, 5916 MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0 = 0x2, 5917 MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE = 0x3, 5918 MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16 = 0x4, 5919 MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0 = 0x5, 5920 MLX5_ACTION_IN_FIELD_OUT_IP_DSCP = 0x6, 5921 MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS = 0x7, 5922 MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT = 0x8, 5923 MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT = 0x9, 5924 MLX5_ACTION_IN_FIELD_OUT_IP_TTL = 0xa, 5925 MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT = 0xb, 5926 MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT = 0xc, 5927 MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96 = 0xd, 5928 MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64 = 0xe, 5929 MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32 = 0xf, 5930 MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0 = 0x10, 5931 MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96 = 0x11, 5932 MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64 = 0x12, 5933 MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32 = 0x13, 5934 MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0 = 0x14, 5935 MLX5_ACTION_IN_FIELD_OUT_SIPV4 = 0x15, 5936 MLX5_ACTION_IN_FIELD_OUT_DIPV4 = 0x16, 5937 MLX5_ACTION_IN_FIELD_OUT_FIRST_VID = 0x17, 5938 MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47, 5939 MLX5_ACTION_IN_FIELD_METADATA_REG_A = 0x49, 5940 MLX5_ACTION_IN_FIELD_METADATA_REG_B = 0x50, 5941 MLX5_ACTION_IN_FIELD_METADATA_REG_C_0 = 0x51, 5942 MLX5_ACTION_IN_FIELD_METADATA_REG_C_1 = 0x52, 5943 MLX5_ACTION_IN_FIELD_METADATA_REG_C_2 = 0x53, 5944 MLX5_ACTION_IN_FIELD_METADATA_REG_C_3 = 0x54, 5945 MLX5_ACTION_IN_FIELD_METADATA_REG_C_4 = 0x55, 5946 MLX5_ACTION_IN_FIELD_METADATA_REG_C_5 = 0x56, 5947 MLX5_ACTION_IN_FIELD_METADATA_REG_C_6 = 0x57, 5948 MLX5_ACTION_IN_FIELD_METADATA_REG_C_7 = 0x58, 5949 MLX5_ACTION_IN_FIELD_OUT_TCP_SEQ_NUM = 0x59, 5950 MLX5_ACTION_IN_FIELD_OUT_TCP_ACK_NUM = 0x5B, 5951 MLX5_ACTION_IN_FIELD_IPSEC_SYNDROME = 0x5D, 5952 }; 5953 5954 struct mlx5_ifc_alloc_modify_header_context_out_bits { 5955 u8 status[0x8]; 5956 u8 reserved_at_8[0x18]; 5957 5958 u8 syndrome[0x20]; 5959 5960 u8 modify_header_id[0x20]; 5961 5962 u8 reserved_at_60[0x20]; 5963 }; 5964 5965 struct mlx5_ifc_alloc_modify_header_context_in_bits { 5966 u8 opcode[0x10]; 5967 u8 reserved_at_10[0x10]; 5968 5969 u8 reserved_at_20[0x10]; 5970 u8 op_mod[0x10]; 5971 5972 u8 reserved_at_40[0x20]; 5973 5974 u8 table_type[0x8]; 5975 u8 reserved_at_68[0x10]; 5976 u8 num_of_actions[0x8]; 5977 5978 union mlx5_ifc_set_add_copy_action_in_auto_bits actions[]; 5979 }; 5980 5981 struct mlx5_ifc_dealloc_modify_header_context_out_bits { 5982 u8 status[0x8]; 5983 u8 reserved_at_8[0x18]; 5984 5985 u8 syndrome[0x20]; 5986 5987 u8 reserved_at_40[0x40]; 5988 }; 5989 5990 struct mlx5_ifc_dealloc_modify_header_context_in_bits { 5991 u8 opcode[0x10]; 5992 u8 reserved_at_10[0x10]; 5993 5994 u8 reserved_at_20[0x10]; 5995 u8 op_mod[0x10]; 5996 5997 u8 modify_header_id[0x20]; 5998 5999 u8 reserved_at_60[0x20]; 6000 }; 6001 6002 struct mlx5_ifc_query_modify_header_context_in_bits { 6003 u8 opcode[0x10]; 6004 u8 uid[0x10]; 6005 6006 u8 reserved_at_20[0x10]; 6007 u8 op_mod[0x10]; 6008 6009 u8 modify_header_id[0x20]; 6010 6011 u8 reserved_at_60[0xa0]; 6012 }; 6013 6014 struct mlx5_ifc_query_dct_out_bits { 6015 u8 status[0x8]; 6016 u8 reserved_at_8[0x18]; 6017 6018 u8 syndrome[0x20]; 6019 6020 u8 reserved_at_40[0x40]; 6021 6022 struct mlx5_ifc_dctc_bits dct_context_entry; 6023 6024 u8 reserved_at_280[0x180]; 6025 }; 6026 6027 struct mlx5_ifc_query_dct_in_bits { 6028 u8 opcode[0x10]; 6029 u8 reserved_at_10[0x10]; 6030 6031 u8 reserved_at_20[0x10]; 6032 u8 op_mod[0x10]; 6033 6034 u8 reserved_at_40[0x8]; 6035 u8 dctn[0x18]; 6036 6037 u8 reserved_at_60[0x20]; 6038 }; 6039 6040 struct mlx5_ifc_query_cq_out_bits { 6041 u8 status[0x8]; 6042 u8 reserved_at_8[0x18]; 6043 6044 u8 syndrome[0x20]; 6045 6046 u8 reserved_at_40[0x40]; 6047 6048 struct mlx5_ifc_cqc_bits cq_context; 6049 6050 u8 reserved_at_280[0x600]; 6051 6052 u8 pas[][0x40]; 6053 }; 6054 6055 struct mlx5_ifc_query_cq_in_bits { 6056 u8 opcode[0x10]; 6057 u8 reserved_at_10[0x10]; 6058 6059 u8 reserved_at_20[0x10]; 6060 u8 op_mod[0x10]; 6061 6062 u8 reserved_at_40[0x8]; 6063 u8 cqn[0x18]; 6064 6065 u8 reserved_at_60[0x20]; 6066 }; 6067 6068 struct mlx5_ifc_query_cong_status_out_bits { 6069 u8 status[0x8]; 6070 u8 reserved_at_8[0x18]; 6071 6072 u8 syndrome[0x20]; 6073 6074 u8 reserved_at_40[0x20]; 6075 6076 u8 enable[0x1]; 6077 u8 tag_enable[0x1]; 6078 u8 reserved_at_62[0x1e]; 6079 }; 6080 6081 struct mlx5_ifc_query_cong_status_in_bits { 6082 u8 opcode[0x10]; 6083 u8 reserved_at_10[0x10]; 6084 6085 u8 reserved_at_20[0x10]; 6086 u8 op_mod[0x10]; 6087 6088 u8 reserved_at_40[0x18]; 6089 u8 priority[0x4]; 6090 u8 cong_protocol[0x4]; 6091 6092 u8 reserved_at_60[0x20]; 6093 }; 6094 6095 struct mlx5_ifc_query_cong_statistics_out_bits { 6096 u8 status[0x8]; 6097 u8 reserved_at_8[0x18]; 6098 6099 u8 syndrome[0x20]; 6100 6101 u8 reserved_at_40[0x40]; 6102 6103 u8 rp_cur_flows[0x20]; 6104 6105 u8 sum_flows[0x20]; 6106 6107 u8 rp_cnp_ignored_high[0x20]; 6108 6109 u8 rp_cnp_ignored_low[0x20]; 6110 6111 u8 rp_cnp_handled_high[0x20]; 6112 6113 u8 rp_cnp_handled_low[0x20]; 6114 6115 u8 reserved_at_140[0x100]; 6116 6117 u8 time_stamp_high[0x20]; 6118 6119 u8 time_stamp_low[0x20]; 6120 6121 u8 accumulators_period[0x20]; 6122 6123 u8 np_ecn_marked_roce_packets_high[0x20]; 6124 6125 u8 np_ecn_marked_roce_packets_low[0x20]; 6126 6127 u8 np_cnp_sent_high[0x20]; 6128 6129 u8 np_cnp_sent_low[0x20]; 6130 6131 u8 reserved_at_320[0x560]; 6132 }; 6133 6134 struct mlx5_ifc_query_cong_statistics_in_bits { 6135 u8 opcode[0x10]; 6136 u8 reserved_at_10[0x10]; 6137 6138 u8 reserved_at_20[0x10]; 6139 u8 op_mod[0x10]; 6140 6141 u8 clear[0x1]; 6142 u8 reserved_at_41[0x1f]; 6143 6144 u8 reserved_at_60[0x20]; 6145 }; 6146 6147 struct mlx5_ifc_query_cong_params_out_bits { 6148 u8 status[0x8]; 6149 u8 reserved_at_8[0x18]; 6150 6151 u8 syndrome[0x20]; 6152 6153 u8 reserved_at_40[0x40]; 6154 6155 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 6156 }; 6157 6158 struct mlx5_ifc_query_cong_params_in_bits { 6159 u8 opcode[0x10]; 6160 u8 reserved_at_10[0x10]; 6161 6162 u8 reserved_at_20[0x10]; 6163 u8 op_mod[0x10]; 6164 6165 u8 reserved_at_40[0x1c]; 6166 u8 cong_protocol[0x4]; 6167 6168 u8 reserved_at_60[0x20]; 6169 }; 6170 6171 struct mlx5_ifc_query_adapter_out_bits { 6172 u8 status[0x8]; 6173 u8 reserved_at_8[0x18]; 6174 6175 u8 syndrome[0x20]; 6176 6177 u8 reserved_at_40[0x40]; 6178 6179 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct; 6180 }; 6181 6182 struct mlx5_ifc_query_adapter_in_bits { 6183 u8 opcode[0x10]; 6184 u8 reserved_at_10[0x10]; 6185 6186 u8 reserved_at_20[0x10]; 6187 u8 op_mod[0x10]; 6188 6189 u8 reserved_at_40[0x40]; 6190 }; 6191 6192 struct mlx5_ifc_qp_2rst_out_bits { 6193 u8 status[0x8]; 6194 u8 reserved_at_8[0x18]; 6195 6196 u8 syndrome[0x20]; 6197 6198 u8 reserved_at_40[0x40]; 6199 }; 6200 6201 struct mlx5_ifc_qp_2rst_in_bits { 6202 u8 opcode[0x10]; 6203 u8 uid[0x10]; 6204 6205 u8 reserved_at_20[0x10]; 6206 u8 op_mod[0x10]; 6207 6208 u8 reserved_at_40[0x8]; 6209 u8 qpn[0x18]; 6210 6211 u8 reserved_at_60[0x20]; 6212 }; 6213 6214 struct mlx5_ifc_qp_2err_out_bits { 6215 u8 status[0x8]; 6216 u8 reserved_at_8[0x18]; 6217 6218 u8 syndrome[0x20]; 6219 6220 u8 reserved_at_40[0x40]; 6221 }; 6222 6223 struct mlx5_ifc_qp_2err_in_bits { 6224 u8 opcode[0x10]; 6225 u8 uid[0x10]; 6226 6227 u8 reserved_at_20[0x10]; 6228 u8 op_mod[0x10]; 6229 6230 u8 reserved_at_40[0x8]; 6231 u8 qpn[0x18]; 6232 6233 u8 reserved_at_60[0x20]; 6234 }; 6235 6236 struct mlx5_ifc_page_fault_resume_out_bits { 6237 u8 status[0x8]; 6238 u8 reserved_at_8[0x18]; 6239 6240 u8 syndrome[0x20]; 6241 6242 u8 reserved_at_40[0x40]; 6243 }; 6244 6245 struct mlx5_ifc_page_fault_resume_in_bits { 6246 u8 opcode[0x10]; 6247 u8 reserved_at_10[0x10]; 6248 6249 u8 reserved_at_20[0x10]; 6250 u8 op_mod[0x10]; 6251 6252 u8 error[0x1]; 6253 u8 reserved_at_41[0x4]; 6254 u8 page_fault_type[0x3]; 6255 u8 wq_number[0x18]; 6256 6257 u8 reserved_at_60[0x8]; 6258 u8 token[0x18]; 6259 }; 6260 6261 struct mlx5_ifc_nop_out_bits { 6262 u8 status[0x8]; 6263 u8 reserved_at_8[0x18]; 6264 6265 u8 syndrome[0x20]; 6266 6267 u8 reserved_at_40[0x40]; 6268 }; 6269 6270 struct mlx5_ifc_nop_in_bits { 6271 u8 opcode[0x10]; 6272 u8 reserved_at_10[0x10]; 6273 6274 u8 reserved_at_20[0x10]; 6275 u8 op_mod[0x10]; 6276 6277 u8 reserved_at_40[0x40]; 6278 }; 6279 6280 struct mlx5_ifc_modify_vport_state_out_bits { 6281 u8 status[0x8]; 6282 u8 reserved_at_8[0x18]; 6283 6284 u8 syndrome[0x20]; 6285 6286 u8 reserved_at_40[0x40]; 6287 }; 6288 6289 struct mlx5_ifc_modify_vport_state_in_bits { 6290 u8 opcode[0x10]; 6291 u8 reserved_at_10[0x10]; 6292 6293 u8 reserved_at_20[0x10]; 6294 u8 op_mod[0x10]; 6295 6296 u8 other_vport[0x1]; 6297 u8 reserved_at_41[0xf]; 6298 u8 vport_number[0x10]; 6299 6300 u8 reserved_at_60[0x18]; 6301 u8 admin_state[0x4]; 6302 u8 reserved_at_7c[0x4]; 6303 }; 6304 6305 struct mlx5_ifc_modify_tis_out_bits { 6306 u8 status[0x8]; 6307 u8 reserved_at_8[0x18]; 6308 6309 u8 syndrome[0x20]; 6310 6311 u8 reserved_at_40[0x40]; 6312 }; 6313 6314 struct mlx5_ifc_modify_tis_bitmask_bits { 6315 u8 reserved_at_0[0x20]; 6316 6317 u8 reserved_at_20[0x1d]; 6318 u8 lag_tx_port_affinity[0x1]; 6319 u8 strict_lag_tx_port_affinity[0x1]; 6320 u8 prio[0x1]; 6321 }; 6322 6323 struct mlx5_ifc_modify_tis_in_bits { 6324 u8 opcode[0x10]; 6325 u8 uid[0x10]; 6326 6327 u8 reserved_at_20[0x10]; 6328 u8 op_mod[0x10]; 6329 6330 u8 reserved_at_40[0x8]; 6331 u8 tisn[0x18]; 6332 6333 u8 reserved_at_60[0x20]; 6334 6335 struct mlx5_ifc_modify_tis_bitmask_bits bitmask; 6336 6337 u8 reserved_at_c0[0x40]; 6338 6339 struct mlx5_ifc_tisc_bits ctx; 6340 }; 6341 6342 struct mlx5_ifc_modify_tir_bitmask_bits { 6343 u8 reserved_at_0[0x20]; 6344 6345 u8 reserved_at_20[0x1b]; 6346 u8 self_lb_en[0x1]; 6347 u8 reserved_at_3c[0x1]; 6348 u8 hash[0x1]; 6349 u8 reserved_at_3e[0x1]; 6350 u8 lro[0x1]; 6351 }; 6352 6353 struct mlx5_ifc_modify_tir_out_bits { 6354 u8 status[0x8]; 6355 u8 reserved_at_8[0x18]; 6356 6357 u8 syndrome[0x20]; 6358 6359 u8 reserved_at_40[0x40]; 6360 }; 6361 6362 struct mlx5_ifc_modify_tir_in_bits { 6363 u8 opcode[0x10]; 6364 u8 uid[0x10]; 6365 6366 u8 reserved_at_20[0x10]; 6367 u8 op_mod[0x10]; 6368 6369 u8 reserved_at_40[0x8]; 6370 u8 tirn[0x18]; 6371 6372 u8 reserved_at_60[0x20]; 6373 6374 struct mlx5_ifc_modify_tir_bitmask_bits bitmask; 6375 6376 u8 reserved_at_c0[0x40]; 6377 6378 struct mlx5_ifc_tirc_bits ctx; 6379 }; 6380 6381 struct mlx5_ifc_modify_sq_out_bits { 6382 u8 status[0x8]; 6383 u8 reserved_at_8[0x18]; 6384 6385 u8 syndrome[0x20]; 6386 6387 u8 reserved_at_40[0x40]; 6388 }; 6389 6390 struct mlx5_ifc_modify_sq_in_bits { 6391 u8 opcode[0x10]; 6392 u8 uid[0x10]; 6393 6394 u8 reserved_at_20[0x10]; 6395 u8 op_mod[0x10]; 6396 6397 u8 sq_state[0x4]; 6398 u8 reserved_at_44[0x4]; 6399 u8 sqn[0x18]; 6400 6401 u8 reserved_at_60[0x20]; 6402 6403 u8 modify_bitmask[0x40]; 6404 6405 u8 reserved_at_c0[0x40]; 6406 6407 struct mlx5_ifc_sqc_bits ctx; 6408 }; 6409 6410 struct mlx5_ifc_modify_scheduling_element_out_bits { 6411 u8 status[0x8]; 6412 u8 reserved_at_8[0x18]; 6413 6414 u8 syndrome[0x20]; 6415 6416 u8 reserved_at_40[0x1c0]; 6417 }; 6418 6419 enum { 6420 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1, 6421 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2, 6422 }; 6423 6424 struct mlx5_ifc_modify_scheduling_element_in_bits { 6425 u8 opcode[0x10]; 6426 u8 reserved_at_10[0x10]; 6427 6428 u8 reserved_at_20[0x10]; 6429 u8 op_mod[0x10]; 6430 6431 u8 scheduling_hierarchy[0x8]; 6432 u8 reserved_at_48[0x18]; 6433 6434 u8 scheduling_element_id[0x20]; 6435 6436 u8 reserved_at_80[0x20]; 6437 6438 u8 modify_bitmask[0x20]; 6439 6440 u8 reserved_at_c0[0x40]; 6441 6442 struct mlx5_ifc_scheduling_context_bits scheduling_context; 6443 6444 u8 reserved_at_300[0x100]; 6445 }; 6446 6447 struct mlx5_ifc_modify_rqt_out_bits { 6448 u8 status[0x8]; 6449 u8 reserved_at_8[0x18]; 6450 6451 u8 syndrome[0x20]; 6452 6453 u8 reserved_at_40[0x40]; 6454 }; 6455 6456 struct mlx5_ifc_rqt_bitmask_bits { 6457 u8 reserved_at_0[0x20]; 6458 6459 u8 reserved_at_20[0x1f]; 6460 u8 rqn_list[0x1]; 6461 }; 6462 6463 struct mlx5_ifc_modify_rqt_in_bits { 6464 u8 opcode[0x10]; 6465 u8 uid[0x10]; 6466 6467 u8 reserved_at_20[0x10]; 6468 u8 op_mod[0x10]; 6469 6470 u8 reserved_at_40[0x8]; 6471 u8 rqtn[0x18]; 6472 6473 u8 reserved_at_60[0x20]; 6474 6475 struct mlx5_ifc_rqt_bitmask_bits bitmask; 6476 6477 u8 reserved_at_c0[0x40]; 6478 6479 struct mlx5_ifc_rqtc_bits ctx; 6480 }; 6481 6482 struct mlx5_ifc_modify_rq_out_bits { 6483 u8 status[0x8]; 6484 u8 reserved_at_8[0x18]; 6485 6486 u8 syndrome[0x20]; 6487 6488 u8 reserved_at_40[0x40]; 6489 }; 6490 6491 enum { 6492 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1, 6493 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2, 6494 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3, 6495 }; 6496 6497 struct mlx5_ifc_modify_rq_in_bits { 6498 u8 opcode[0x10]; 6499 u8 uid[0x10]; 6500 6501 u8 reserved_at_20[0x10]; 6502 u8 op_mod[0x10]; 6503 6504 u8 rq_state[0x4]; 6505 u8 reserved_at_44[0x4]; 6506 u8 rqn[0x18]; 6507 6508 u8 reserved_at_60[0x20]; 6509 6510 u8 modify_bitmask[0x40]; 6511 6512 u8 reserved_at_c0[0x40]; 6513 6514 struct mlx5_ifc_rqc_bits ctx; 6515 }; 6516 6517 struct mlx5_ifc_modify_rmp_out_bits { 6518 u8 status[0x8]; 6519 u8 reserved_at_8[0x18]; 6520 6521 u8 syndrome[0x20]; 6522 6523 u8 reserved_at_40[0x40]; 6524 }; 6525 6526 struct mlx5_ifc_rmp_bitmask_bits { 6527 u8 reserved_at_0[0x20]; 6528 6529 u8 reserved_at_20[0x1f]; 6530 u8 lwm[0x1]; 6531 }; 6532 6533 struct mlx5_ifc_modify_rmp_in_bits { 6534 u8 opcode[0x10]; 6535 u8 uid[0x10]; 6536 6537 u8 reserved_at_20[0x10]; 6538 u8 op_mod[0x10]; 6539 6540 u8 rmp_state[0x4]; 6541 u8 reserved_at_44[0x4]; 6542 u8 rmpn[0x18]; 6543 6544 u8 reserved_at_60[0x20]; 6545 6546 struct mlx5_ifc_rmp_bitmask_bits bitmask; 6547 6548 u8 reserved_at_c0[0x40]; 6549 6550 struct mlx5_ifc_rmpc_bits ctx; 6551 }; 6552 6553 struct mlx5_ifc_modify_nic_vport_context_out_bits { 6554 u8 status[0x8]; 6555 u8 reserved_at_8[0x18]; 6556 6557 u8 syndrome[0x20]; 6558 6559 u8 reserved_at_40[0x40]; 6560 }; 6561 6562 struct mlx5_ifc_modify_nic_vport_field_select_bits { 6563 u8 reserved_at_0[0x12]; 6564 u8 affiliation[0x1]; 6565 u8 reserved_at_13[0x1]; 6566 u8 disable_uc_local_lb[0x1]; 6567 u8 disable_mc_local_lb[0x1]; 6568 u8 node_guid[0x1]; 6569 u8 port_guid[0x1]; 6570 u8 min_inline[0x1]; 6571 u8 mtu[0x1]; 6572 u8 change_event[0x1]; 6573 u8 promisc[0x1]; 6574 u8 permanent_address[0x1]; 6575 u8 addresses_list[0x1]; 6576 u8 roce_en[0x1]; 6577 u8 reserved_at_1f[0x1]; 6578 }; 6579 6580 struct mlx5_ifc_modify_nic_vport_context_in_bits { 6581 u8 opcode[0x10]; 6582 u8 reserved_at_10[0x10]; 6583 6584 u8 reserved_at_20[0x10]; 6585 u8 op_mod[0x10]; 6586 6587 u8 other_vport[0x1]; 6588 u8 reserved_at_41[0xf]; 6589 u8 vport_number[0x10]; 6590 6591 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select; 6592 6593 u8 reserved_at_80[0x780]; 6594 6595 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 6596 }; 6597 6598 struct mlx5_ifc_modify_hca_vport_context_out_bits { 6599 u8 status[0x8]; 6600 u8 reserved_at_8[0x18]; 6601 6602 u8 syndrome[0x20]; 6603 6604 u8 reserved_at_40[0x40]; 6605 }; 6606 6607 struct mlx5_ifc_modify_hca_vport_context_in_bits { 6608 u8 opcode[0x10]; 6609 u8 reserved_at_10[0x10]; 6610 6611 u8 reserved_at_20[0x10]; 6612 u8 op_mod[0x10]; 6613 6614 u8 other_vport[0x1]; 6615 u8 reserved_at_41[0xb]; 6616 u8 port_num[0x4]; 6617 u8 vport_number[0x10]; 6618 6619 u8 reserved_at_60[0x20]; 6620 6621 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 6622 }; 6623 6624 struct mlx5_ifc_modify_cq_out_bits { 6625 u8 status[0x8]; 6626 u8 reserved_at_8[0x18]; 6627 6628 u8 syndrome[0x20]; 6629 6630 u8 reserved_at_40[0x40]; 6631 }; 6632 6633 enum { 6634 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0, 6635 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1, 6636 }; 6637 6638 struct mlx5_ifc_modify_cq_in_bits { 6639 u8 opcode[0x10]; 6640 u8 uid[0x10]; 6641 6642 u8 reserved_at_20[0x10]; 6643 u8 op_mod[0x10]; 6644 6645 u8 reserved_at_40[0x8]; 6646 u8 cqn[0x18]; 6647 6648 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select; 6649 6650 struct mlx5_ifc_cqc_bits cq_context; 6651 6652 u8 reserved_at_280[0x60]; 6653 6654 u8 cq_umem_valid[0x1]; 6655 u8 reserved_at_2e1[0x1f]; 6656 6657 u8 reserved_at_300[0x580]; 6658 6659 u8 pas[][0x40]; 6660 }; 6661 6662 struct mlx5_ifc_modify_cong_status_out_bits { 6663 u8 status[0x8]; 6664 u8 reserved_at_8[0x18]; 6665 6666 u8 syndrome[0x20]; 6667 6668 u8 reserved_at_40[0x40]; 6669 }; 6670 6671 struct mlx5_ifc_modify_cong_status_in_bits { 6672 u8 opcode[0x10]; 6673 u8 reserved_at_10[0x10]; 6674 6675 u8 reserved_at_20[0x10]; 6676 u8 op_mod[0x10]; 6677 6678 u8 reserved_at_40[0x18]; 6679 u8 priority[0x4]; 6680 u8 cong_protocol[0x4]; 6681 6682 u8 enable[0x1]; 6683 u8 tag_enable[0x1]; 6684 u8 reserved_at_62[0x1e]; 6685 }; 6686 6687 struct mlx5_ifc_modify_cong_params_out_bits { 6688 u8 status[0x8]; 6689 u8 reserved_at_8[0x18]; 6690 6691 u8 syndrome[0x20]; 6692 6693 u8 reserved_at_40[0x40]; 6694 }; 6695 6696 struct mlx5_ifc_modify_cong_params_in_bits { 6697 u8 opcode[0x10]; 6698 u8 reserved_at_10[0x10]; 6699 6700 u8 reserved_at_20[0x10]; 6701 u8 op_mod[0x10]; 6702 6703 u8 reserved_at_40[0x1c]; 6704 u8 cong_protocol[0x4]; 6705 6706 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select; 6707 6708 u8 reserved_at_80[0x80]; 6709 6710 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 6711 }; 6712 6713 struct mlx5_ifc_manage_pages_out_bits { 6714 u8 status[0x8]; 6715 u8 reserved_at_8[0x18]; 6716 6717 u8 syndrome[0x20]; 6718 6719 u8 output_num_entries[0x20]; 6720 6721 u8 reserved_at_60[0x20]; 6722 6723 u8 pas[][0x40]; 6724 }; 6725 6726 enum { 6727 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL = 0x0, 6728 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS = 0x1, 6729 MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES = 0x2, 6730 }; 6731 6732 struct mlx5_ifc_manage_pages_in_bits { 6733 u8 opcode[0x10]; 6734 u8 reserved_at_10[0x10]; 6735 6736 u8 reserved_at_20[0x10]; 6737 u8 op_mod[0x10]; 6738 6739 u8 embedded_cpu_function[0x1]; 6740 u8 reserved_at_41[0xf]; 6741 u8 function_id[0x10]; 6742 6743 u8 input_num_entries[0x20]; 6744 6745 u8 pas[][0x40]; 6746 }; 6747 6748 struct mlx5_ifc_mad_ifc_out_bits { 6749 u8 status[0x8]; 6750 u8 reserved_at_8[0x18]; 6751 6752 u8 syndrome[0x20]; 6753 6754 u8 reserved_at_40[0x40]; 6755 6756 u8 response_mad_packet[256][0x8]; 6757 }; 6758 6759 struct mlx5_ifc_mad_ifc_in_bits { 6760 u8 opcode[0x10]; 6761 u8 reserved_at_10[0x10]; 6762 6763 u8 reserved_at_20[0x10]; 6764 u8 op_mod[0x10]; 6765 6766 u8 remote_lid[0x10]; 6767 u8 reserved_at_50[0x8]; 6768 u8 port[0x8]; 6769 6770 u8 reserved_at_60[0x20]; 6771 6772 u8 mad[256][0x8]; 6773 }; 6774 6775 struct mlx5_ifc_init_hca_out_bits { 6776 u8 status[0x8]; 6777 u8 reserved_at_8[0x18]; 6778 6779 u8 syndrome[0x20]; 6780 6781 u8 reserved_at_40[0x40]; 6782 }; 6783 6784 struct mlx5_ifc_init_hca_in_bits { 6785 u8 opcode[0x10]; 6786 u8 reserved_at_10[0x10]; 6787 6788 u8 reserved_at_20[0x10]; 6789 u8 op_mod[0x10]; 6790 6791 u8 reserved_at_40[0x40]; 6792 u8 sw_owner_id[4][0x20]; 6793 }; 6794 6795 struct mlx5_ifc_init2rtr_qp_out_bits { 6796 u8 status[0x8]; 6797 u8 reserved_at_8[0x18]; 6798 6799 u8 syndrome[0x20]; 6800 6801 u8 reserved_at_40[0x20]; 6802 u8 ece[0x20]; 6803 }; 6804 6805 struct mlx5_ifc_init2rtr_qp_in_bits { 6806 u8 opcode[0x10]; 6807 u8 uid[0x10]; 6808 6809 u8 reserved_at_20[0x10]; 6810 u8 op_mod[0x10]; 6811 6812 u8 reserved_at_40[0x8]; 6813 u8 qpn[0x18]; 6814 6815 u8 reserved_at_60[0x20]; 6816 6817 u8 opt_param_mask[0x20]; 6818 6819 u8 ece[0x20]; 6820 6821 struct mlx5_ifc_qpc_bits qpc; 6822 6823 u8 reserved_at_800[0x80]; 6824 }; 6825 6826 struct mlx5_ifc_init2init_qp_out_bits { 6827 u8 status[0x8]; 6828 u8 reserved_at_8[0x18]; 6829 6830 u8 syndrome[0x20]; 6831 6832 u8 reserved_at_40[0x20]; 6833 u8 ece[0x20]; 6834 }; 6835 6836 struct mlx5_ifc_init2init_qp_in_bits { 6837 u8 opcode[0x10]; 6838 u8 uid[0x10]; 6839 6840 u8 reserved_at_20[0x10]; 6841 u8 op_mod[0x10]; 6842 6843 u8 reserved_at_40[0x8]; 6844 u8 qpn[0x18]; 6845 6846 u8 reserved_at_60[0x20]; 6847 6848 u8 opt_param_mask[0x20]; 6849 6850 u8 ece[0x20]; 6851 6852 struct mlx5_ifc_qpc_bits qpc; 6853 6854 u8 reserved_at_800[0x80]; 6855 }; 6856 6857 struct mlx5_ifc_get_dropped_packet_log_out_bits { 6858 u8 status[0x8]; 6859 u8 reserved_at_8[0x18]; 6860 6861 u8 syndrome[0x20]; 6862 6863 u8 reserved_at_40[0x40]; 6864 6865 u8 packet_headers_log[128][0x8]; 6866 6867 u8 packet_syndrome[64][0x8]; 6868 }; 6869 6870 struct mlx5_ifc_get_dropped_packet_log_in_bits { 6871 u8 opcode[0x10]; 6872 u8 reserved_at_10[0x10]; 6873 6874 u8 reserved_at_20[0x10]; 6875 u8 op_mod[0x10]; 6876 6877 u8 reserved_at_40[0x40]; 6878 }; 6879 6880 struct mlx5_ifc_gen_eqe_in_bits { 6881 u8 opcode[0x10]; 6882 u8 reserved_at_10[0x10]; 6883 6884 u8 reserved_at_20[0x10]; 6885 u8 op_mod[0x10]; 6886 6887 u8 reserved_at_40[0x18]; 6888 u8 eq_number[0x8]; 6889 6890 u8 reserved_at_60[0x20]; 6891 6892 u8 eqe[64][0x8]; 6893 }; 6894 6895 struct mlx5_ifc_gen_eq_out_bits { 6896 u8 status[0x8]; 6897 u8 reserved_at_8[0x18]; 6898 6899 u8 syndrome[0x20]; 6900 6901 u8 reserved_at_40[0x40]; 6902 }; 6903 6904 struct mlx5_ifc_enable_hca_out_bits { 6905 u8 status[0x8]; 6906 u8 reserved_at_8[0x18]; 6907 6908 u8 syndrome[0x20]; 6909 6910 u8 reserved_at_40[0x20]; 6911 }; 6912 6913 struct mlx5_ifc_enable_hca_in_bits { 6914 u8 opcode[0x10]; 6915 u8 reserved_at_10[0x10]; 6916 6917 u8 reserved_at_20[0x10]; 6918 u8 op_mod[0x10]; 6919 6920 u8 embedded_cpu_function[0x1]; 6921 u8 reserved_at_41[0xf]; 6922 u8 function_id[0x10]; 6923 6924 u8 reserved_at_60[0x20]; 6925 }; 6926 6927 struct mlx5_ifc_drain_dct_out_bits { 6928 u8 status[0x8]; 6929 u8 reserved_at_8[0x18]; 6930 6931 u8 syndrome[0x20]; 6932 6933 u8 reserved_at_40[0x40]; 6934 }; 6935 6936 struct mlx5_ifc_drain_dct_in_bits { 6937 u8 opcode[0x10]; 6938 u8 uid[0x10]; 6939 6940 u8 reserved_at_20[0x10]; 6941 u8 op_mod[0x10]; 6942 6943 u8 reserved_at_40[0x8]; 6944 u8 dctn[0x18]; 6945 6946 u8 reserved_at_60[0x20]; 6947 }; 6948 6949 struct mlx5_ifc_disable_hca_out_bits { 6950 u8 status[0x8]; 6951 u8 reserved_at_8[0x18]; 6952 6953 u8 syndrome[0x20]; 6954 6955 u8 reserved_at_40[0x20]; 6956 }; 6957 6958 struct mlx5_ifc_disable_hca_in_bits { 6959 u8 opcode[0x10]; 6960 u8 reserved_at_10[0x10]; 6961 6962 u8 reserved_at_20[0x10]; 6963 u8 op_mod[0x10]; 6964 6965 u8 embedded_cpu_function[0x1]; 6966 u8 reserved_at_41[0xf]; 6967 u8 function_id[0x10]; 6968 6969 u8 reserved_at_60[0x20]; 6970 }; 6971 6972 struct mlx5_ifc_detach_from_mcg_out_bits { 6973 u8 status[0x8]; 6974 u8 reserved_at_8[0x18]; 6975 6976 u8 syndrome[0x20]; 6977 6978 u8 reserved_at_40[0x40]; 6979 }; 6980 6981 struct mlx5_ifc_detach_from_mcg_in_bits { 6982 u8 opcode[0x10]; 6983 u8 uid[0x10]; 6984 6985 u8 reserved_at_20[0x10]; 6986 u8 op_mod[0x10]; 6987 6988 u8 reserved_at_40[0x8]; 6989 u8 qpn[0x18]; 6990 6991 u8 reserved_at_60[0x20]; 6992 6993 u8 multicast_gid[16][0x8]; 6994 }; 6995 6996 struct mlx5_ifc_destroy_xrq_out_bits { 6997 u8 status[0x8]; 6998 u8 reserved_at_8[0x18]; 6999 7000 u8 syndrome[0x20]; 7001 7002 u8 reserved_at_40[0x40]; 7003 }; 7004 7005 struct mlx5_ifc_destroy_xrq_in_bits { 7006 u8 opcode[0x10]; 7007 u8 uid[0x10]; 7008 7009 u8 reserved_at_20[0x10]; 7010 u8 op_mod[0x10]; 7011 7012 u8 reserved_at_40[0x8]; 7013 u8 xrqn[0x18]; 7014 7015 u8 reserved_at_60[0x20]; 7016 }; 7017 7018 struct mlx5_ifc_destroy_xrc_srq_out_bits { 7019 u8 status[0x8]; 7020 u8 reserved_at_8[0x18]; 7021 7022 u8 syndrome[0x20]; 7023 7024 u8 reserved_at_40[0x40]; 7025 }; 7026 7027 struct mlx5_ifc_destroy_xrc_srq_in_bits { 7028 u8 opcode[0x10]; 7029 u8 uid[0x10]; 7030 7031 u8 reserved_at_20[0x10]; 7032 u8 op_mod[0x10]; 7033 7034 u8 reserved_at_40[0x8]; 7035 u8 xrc_srqn[0x18]; 7036 7037 u8 reserved_at_60[0x20]; 7038 }; 7039 7040 struct mlx5_ifc_destroy_tis_out_bits { 7041 u8 status[0x8]; 7042 u8 reserved_at_8[0x18]; 7043 7044 u8 syndrome[0x20]; 7045 7046 u8 reserved_at_40[0x40]; 7047 }; 7048 7049 struct mlx5_ifc_destroy_tis_in_bits { 7050 u8 opcode[0x10]; 7051 u8 uid[0x10]; 7052 7053 u8 reserved_at_20[0x10]; 7054 u8 op_mod[0x10]; 7055 7056 u8 reserved_at_40[0x8]; 7057 u8 tisn[0x18]; 7058 7059 u8 reserved_at_60[0x20]; 7060 }; 7061 7062 struct mlx5_ifc_destroy_tir_out_bits { 7063 u8 status[0x8]; 7064 u8 reserved_at_8[0x18]; 7065 7066 u8 syndrome[0x20]; 7067 7068 u8 reserved_at_40[0x40]; 7069 }; 7070 7071 struct mlx5_ifc_destroy_tir_in_bits { 7072 u8 opcode[0x10]; 7073 u8 uid[0x10]; 7074 7075 u8 reserved_at_20[0x10]; 7076 u8 op_mod[0x10]; 7077 7078 u8 reserved_at_40[0x8]; 7079 u8 tirn[0x18]; 7080 7081 u8 reserved_at_60[0x20]; 7082 }; 7083 7084 struct mlx5_ifc_destroy_srq_out_bits { 7085 u8 status[0x8]; 7086 u8 reserved_at_8[0x18]; 7087 7088 u8 syndrome[0x20]; 7089 7090 u8 reserved_at_40[0x40]; 7091 }; 7092 7093 struct mlx5_ifc_destroy_srq_in_bits { 7094 u8 opcode[0x10]; 7095 u8 uid[0x10]; 7096 7097 u8 reserved_at_20[0x10]; 7098 u8 op_mod[0x10]; 7099 7100 u8 reserved_at_40[0x8]; 7101 u8 srqn[0x18]; 7102 7103 u8 reserved_at_60[0x20]; 7104 }; 7105 7106 struct mlx5_ifc_destroy_sq_out_bits { 7107 u8 status[0x8]; 7108 u8 reserved_at_8[0x18]; 7109 7110 u8 syndrome[0x20]; 7111 7112 u8 reserved_at_40[0x40]; 7113 }; 7114 7115 struct mlx5_ifc_destroy_sq_in_bits { 7116 u8 opcode[0x10]; 7117 u8 uid[0x10]; 7118 7119 u8 reserved_at_20[0x10]; 7120 u8 op_mod[0x10]; 7121 7122 u8 reserved_at_40[0x8]; 7123 u8 sqn[0x18]; 7124 7125 u8 reserved_at_60[0x20]; 7126 }; 7127 7128 struct mlx5_ifc_destroy_scheduling_element_out_bits { 7129 u8 status[0x8]; 7130 u8 reserved_at_8[0x18]; 7131 7132 u8 syndrome[0x20]; 7133 7134 u8 reserved_at_40[0x1c0]; 7135 }; 7136 7137 struct mlx5_ifc_destroy_scheduling_element_in_bits { 7138 u8 opcode[0x10]; 7139 u8 reserved_at_10[0x10]; 7140 7141 u8 reserved_at_20[0x10]; 7142 u8 op_mod[0x10]; 7143 7144 u8 scheduling_hierarchy[0x8]; 7145 u8 reserved_at_48[0x18]; 7146 7147 u8 scheduling_element_id[0x20]; 7148 7149 u8 reserved_at_80[0x180]; 7150 }; 7151 7152 struct mlx5_ifc_destroy_rqt_out_bits { 7153 u8 status[0x8]; 7154 u8 reserved_at_8[0x18]; 7155 7156 u8 syndrome[0x20]; 7157 7158 u8 reserved_at_40[0x40]; 7159 }; 7160 7161 struct mlx5_ifc_destroy_rqt_in_bits { 7162 u8 opcode[0x10]; 7163 u8 uid[0x10]; 7164 7165 u8 reserved_at_20[0x10]; 7166 u8 op_mod[0x10]; 7167 7168 u8 reserved_at_40[0x8]; 7169 u8 rqtn[0x18]; 7170 7171 u8 reserved_at_60[0x20]; 7172 }; 7173 7174 struct mlx5_ifc_destroy_rq_out_bits { 7175 u8 status[0x8]; 7176 u8 reserved_at_8[0x18]; 7177 7178 u8 syndrome[0x20]; 7179 7180 u8 reserved_at_40[0x40]; 7181 }; 7182 7183 struct mlx5_ifc_destroy_rq_in_bits { 7184 u8 opcode[0x10]; 7185 u8 uid[0x10]; 7186 7187 u8 reserved_at_20[0x10]; 7188 u8 op_mod[0x10]; 7189 7190 u8 reserved_at_40[0x8]; 7191 u8 rqn[0x18]; 7192 7193 u8 reserved_at_60[0x20]; 7194 }; 7195 7196 struct mlx5_ifc_set_delay_drop_params_in_bits { 7197 u8 opcode[0x10]; 7198 u8 reserved_at_10[0x10]; 7199 7200 u8 reserved_at_20[0x10]; 7201 u8 op_mod[0x10]; 7202 7203 u8 reserved_at_40[0x20]; 7204 7205 u8 reserved_at_60[0x10]; 7206 u8 delay_drop_timeout[0x10]; 7207 }; 7208 7209 struct mlx5_ifc_set_delay_drop_params_out_bits { 7210 u8 status[0x8]; 7211 u8 reserved_at_8[0x18]; 7212 7213 u8 syndrome[0x20]; 7214 7215 u8 reserved_at_40[0x40]; 7216 }; 7217 7218 struct mlx5_ifc_destroy_rmp_out_bits { 7219 u8 status[0x8]; 7220 u8 reserved_at_8[0x18]; 7221 7222 u8 syndrome[0x20]; 7223 7224 u8 reserved_at_40[0x40]; 7225 }; 7226 7227 struct mlx5_ifc_destroy_rmp_in_bits { 7228 u8 opcode[0x10]; 7229 u8 uid[0x10]; 7230 7231 u8 reserved_at_20[0x10]; 7232 u8 op_mod[0x10]; 7233 7234 u8 reserved_at_40[0x8]; 7235 u8 rmpn[0x18]; 7236 7237 u8 reserved_at_60[0x20]; 7238 }; 7239 7240 struct mlx5_ifc_destroy_qp_out_bits { 7241 u8 status[0x8]; 7242 u8 reserved_at_8[0x18]; 7243 7244 u8 syndrome[0x20]; 7245 7246 u8 reserved_at_40[0x40]; 7247 }; 7248 7249 struct mlx5_ifc_destroy_qp_in_bits { 7250 u8 opcode[0x10]; 7251 u8 uid[0x10]; 7252 7253 u8 reserved_at_20[0x10]; 7254 u8 op_mod[0x10]; 7255 7256 u8 reserved_at_40[0x8]; 7257 u8 qpn[0x18]; 7258 7259 u8 reserved_at_60[0x20]; 7260 }; 7261 7262 struct mlx5_ifc_destroy_psv_out_bits { 7263 u8 status[0x8]; 7264 u8 reserved_at_8[0x18]; 7265 7266 u8 syndrome[0x20]; 7267 7268 u8 reserved_at_40[0x40]; 7269 }; 7270 7271 struct mlx5_ifc_destroy_psv_in_bits { 7272 u8 opcode[0x10]; 7273 u8 reserved_at_10[0x10]; 7274 7275 u8 reserved_at_20[0x10]; 7276 u8 op_mod[0x10]; 7277 7278 u8 reserved_at_40[0x8]; 7279 u8 psvn[0x18]; 7280 7281 u8 reserved_at_60[0x20]; 7282 }; 7283 7284 struct mlx5_ifc_destroy_mkey_out_bits { 7285 u8 status[0x8]; 7286 u8 reserved_at_8[0x18]; 7287 7288 u8 syndrome[0x20]; 7289 7290 u8 reserved_at_40[0x40]; 7291 }; 7292 7293 struct mlx5_ifc_destroy_mkey_in_bits { 7294 u8 opcode[0x10]; 7295 u8 uid[0x10]; 7296 7297 u8 reserved_at_20[0x10]; 7298 u8 op_mod[0x10]; 7299 7300 u8 reserved_at_40[0x8]; 7301 u8 mkey_index[0x18]; 7302 7303 u8 reserved_at_60[0x20]; 7304 }; 7305 7306 struct mlx5_ifc_destroy_flow_table_out_bits { 7307 u8 status[0x8]; 7308 u8 reserved_at_8[0x18]; 7309 7310 u8 syndrome[0x20]; 7311 7312 u8 reserved_at_40[0x40]; 7313 }; 7314 7315 struct mlx5_ifc_destroy_flow_table_in_bits { 7316 u8 opcode[0x10]; 7317 u8 reserved_at_10[0x10]; 7318 7319 u8 reserved_at_20[0x10]; 7320 u8 op_mod[0x10]; 7321 7322 u8 other_vport[0x1]; 7323 u8 reserved_at_41[0xf]; 7324 u8 vport_number[0x10]; 7325 7326 u8 reserved_at_60[0x20]; 7327 7328 u8 table_type[0x8]; 7329 u8 reserved_at_88[0x18]; 7330 7331 u8 reserved_at_a0[0x8]; 7332 u8 table_id[0x18]; 7333 7334 u8 reserved_at_c0[0x140]; 7335 }; 7336 7337 struct mlx5_ifc_destroy_flow_group_out_bits { 7338 u8 status[0x8]; 7339 u8 reserved_at_8[0x18]; 7340 7341 u8 syndrome[0x20]; 7342 7343 u8 reserved_at_40[0x40]; 7344 }; 7345 7346 struct mlx5_ifc_destroy_flow_group_in_bits { 7347 u8 opcode[0x10]; 7348 u8 reserved_at_10[0x10]; 7349 7350 u8 reserved_at_20[0x10]; 7351 u8 op_mod[0x10]; 7352 7353 u8 other_vport[0x1]; 7354 u8 reserved_at_41[0xf]; 7355 u8 vport_number[0x10]; 7356 7357 u8 reserved_at_60[0x20]; 7358 7359 u8 table_type[0x8]; 7360 u8 reserved_at_88[0x18]; 7361 7362 u8 reserved_at_a0[0x8]; 7363 u8 table_id[0x18]; 7364 7365 u8 group_id[0x20]; 7366 7367 u8 reserved_at_e0[0x120]; 7368 }; 7369 7370 struct mlx5_ifc_destroy_eq_out_bits { 7371 u8 status[0x8]; 7372 u8 reserved_at_8[0x18]; 7373 7374 u8 syndrome[0x20]; 7375 7376 u8 reserved_at_40[0x40]; 7377 }; 7378 7379 struct mlx5_ifc_destroy_eq_in_bits { 7380 u8 opcode[0x10]; 7381 u8 reserved_at_10[0x10]; 7382 7383 u8 reserved_at_20[0x10]; 7384 u8 op_mod[0x10]; 7385 7386 u8 reserved_at_40[0x18]; 7387 u8 eq_number[0x8]; 7388 7389 u8 reserved_at_60[0x20]; 7390 }; 7391 7392 struct mlx5_ifc_destroy_dct_out_bits { 7393 u8 status[0x8]; 7394 u8 reserved_at_8[0x18]; 7395 7396 u8 syndrome[0x20]; 7397 7398 u8 reserved_at_40[0x40]; 7399 }; 7400 7401 struct mlx5_ifc_destroy_dct_in_bits { 7402 u8 opcode[0x10]; 7403 u8 uid[0x10]; 7404 7405 u8 reserved_at_20[0x10]; 7406 u8 op_mod[0x10]; 7407 7408 u8 reserved_at_40[0x8]; 7409 u8 dctn[0x18]; 7410 7411 u8 reserved_at_60[0x20]; 7412 }; 7413 7414 struct mlx5_ifc_destroy_cq_out_bits { 7415 u8 status[0x8]; 7416 u8 reserved_at_8[0x18]; 7417 7418 u8 syndrome[0x20]; 7419 7420 u8 reserved_at_40[0x40]; 7421 }; 7422 7423 struct mlx5_ifc_destroy_cq_in_bits { 7424 u8 opcode[0x10]; 7425 u8 uid[0x10]; 7426 7427 u8 reserved_at_20[0x10]; 7428 u8 op_mod[0x10]; 7429 7430 u8 reserved_at_40[0x8]; 7431 u8 cqn[0x18]; 7432 7433 u8 reserved_at_60[0x20]; 7434 }; 7435 7436 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits { 7437 u8 status[0x8]; 7438 u8 reserved_at_8[0x18]; 7439 7440 u8 syndrome[0x20]; 7441 7442 u8 reserved_at_40[0x40]; 7443 }; 7444 7445 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits { 7446 u8 opcode[0x10]; 7447 u8 reserved_at_10[0x10]; 7448 7449 u8 reserved_at_20[0x10]; 7450 u8 op_mod[0x10]; 7451 7452 u8 reserved_at_40[0x20]; 7453 7454 u8 reserved_at_60[0x10]; 7455 u8 vxlan_udp_port[0x10]; 7456 }; 7457 7458 struct mlx5_ifc_delete_l2_table_entry_out_bits { 7459 u8 status[0x8]; 7460 u8 reserved_at_8[0x18]; 7461 7462 u8 syndrome[0x20]; 7463 7464 u8 reserved_at_40[0x40]; 7465 }; 7466 7467 struct mlx5_ifc_delete_l2_table_entry_in_bits { 7468 u8 opcode[0x10]; 7469 u8 reserved_at_10[0x10]; 7470 7471 u8 reserved_at_20[0x10]; 7472 u8 op_mod[0x10]; 7473 7474 u8 reserved_at_40[0x60]; 7475 7476 u8 reserved_at_a0[0x8]; 7477 u8 table_index[0x18]; 7478 7479 u8 reserved_at_c0[0x140]; 7480 }; 7481 7482 struct mlx5_ifc_delete_fte_out_bits { 7483 u8 status[0x8]; 7484 u8 reserved_at_8[0x18]; 7485 7486 u8 syndrome[0x20]; 7487 7488 u8 reserved_at_40[0x40]; 7489 }; 7490 7491 struct mlx5_ifc_delete_fte_in_bits { 7492 u8 opcode[0x10]; 7493 u8 reserved_at_10[0x10]; 7494 7495 u8 reserved_at_20[0x10]; 7496 u8 op_mod[0x10]; 7497 7498 u8 other_vport[0x1]; 7499 u8 reserved_at_41[0xf]; 7500 u8 vport_number[0x10]; 7501 7502 u8 reserved_at_60[0x20]; 7503 7504 u8 table_type[0x8]; 7505 u8 reserved_at_88[0x18]; 7506 7507 u8 reserved_at_a0[0x8]; 7508 u8 table_id[0x18]; 7509 7510 u8 reserved_at_c0[0x40]; 7511 7512 u8 flow_index[0x20]; 7513 7514 u8 reserved_at_120[0xe0]; 7515 }; 7516 7517 struct mlx5_ifc_dealloc_xrcd_out_bits { 7518 u8 status[0x8]; 7519 u8 reserved_at_8[0x18]; 7520 7521 u8 syndrome[0x20]; 7522 7523 u8 reserved_at_40[0x40]; 7524 }; 7525 7526 struct mlx5_ifc_dealloc_xrcd_in_bits { 7527 u8 opcode[0x10]; 7528 u8 uid[0x10]; 7529 7530 u8 reserved_at_20[0x10]; 7531 u8 op_mod[0x10]; 7532 7533 u8 reserved_at_40[0x8]; 7534 u8 xrcd[0x18]; 7535 7536 u8 reserved_at_60[0x20]; 7537 }; 7538 7539 struct mlx5_ifc_dealloc_uar_out_bits { 7540 u8 status[0x8]; 7541 u8 reserved_at_8[0x18]; 7542 7543 u8 syndrome[0x20]; 7544 7545 u8 reserved_at_40[0x40]; 7546 }; 7547 7548 struct mlx5_ifc_dealloc_uar_in_bits { 7549 u8 opcode[0x10]; 7550 u8 reserved_at_10[0x10]; 7551 7552 u8 reserved_at_20[0x10]; 7553 u8 op_mod[0x10]; 7554 7555 u8 reserved_at_40[0x8]; 7556 u8 uar[0x18]; 7557 7558 u8 reserved_at_60[0x20]; 7559 }; 7560 7561 struct mlx5_ifc_dealloc_transport_domain_out_bits { 7562 u8 status[0x8]; 7563 u8 reserved_at_8[0x18]; 7564 7565 u8 syndrome[0x20]; 7566 7567 u8 reserved_at_40[0x40]; 7568 }; 7569 7570 struct mlx5_ifc_dealloc_transport_domain_in_bits { 7571 u8 opcode[0x10]; 7572 u8 uid[0x10]; 7573 7574 u8 reserved_at_20[0x10]; 7575 u8 op_mod[0x10]; 7576 7577 u8 reserved_at_40[0x8]; 7578 u8 transport_domain[0x18]; 7579 7580 u8 reserved_at_60[0x20]; 7581 }; 7582 7583 struct mlx5_ifc_dealloc_q_counter_out_bits { 7584 u8 status[0x8]; 7585 u8 reserved_at_8[0x18]; 7586 7587 u8 syndrome[0x20]; 7588 7589 u8 reserved_at_40[0x40]; 7590 }; 7591 7592 struct mlx5_ifc_dealloc_q_counter_in_bits { 7593 u8 opcode[0x10]; 7594 u8 reserved_at_10[0x10]; 7595 7596 u8 reserved_at_20[0x10]; 7597 u8 op_mod[0x10]; 7598 7599 u8 reserved_at_40[0x18]; 7600 u8 counter_set_id[0x8]; 7601 7602 u8 reserved_at_60[0x20]; 7603 }; 7604 7605 struct mlx5_ifc_dealloc_pd_out_bits { 7606 u8 status[0x8]; 7607 u8 reserved_at_8[0x18]; 7608 7609 u8 syndrome[0x20]; 7610 7611 u8 reserved_at_40[0x40]; 7612 }; 7613 7614 struct mlx5_ifc_dealloc_pd_in_bits { 7615 u8 opcode[0x10]; 7616 u8 uid[0x10]; 7617 7618 u8 reserved_at_20[0x10]; 7619 u8 op_mod[0x10]; 7620 7621 u8 reserved_at_40[0x8]; 7622 u8 pd[0x18]; 7623 7624 u8 reserved_at_60[0x20]; 7625 }; 7626 7627 struct mlx5_ifc_dealloc_flow_counter_out_bits { 7628 u8 status[0x8]; 7629 u8 reserved_at_8[0x18]; 7630 7631 u8 syndrome[0x20]; 7632 7633 u8 reserved_at_40[0x40]; 7634 }; 7635 7636 struct mlx5_ifc_dealloc_flow_counter_in_bits { 7637 u8 opcode[0x10]; 7638 u8 reserved_at_10[0x10]; 7639 7640 u8 reserved_at_20[0x10]; 7641 u8 op_mod[0x10]; 7642 7643 u8 flow_counter_id[0x20]; 7644 7645 u8 reserved_at_60[0x20]; 7646 }; 7647 7648 struct mlx5_ifc_create_xrq_out_bits { 7649 u8 status[0x8]; 7650 u8 reserved_at_8[0x18]; 7651 7652 u8 syndrome[0x20]; 7653 7654 u8 reserved_at_40[0x8]; 7655 u8 xrqn[0x18]; 7656 7657 u8 reserved_at_60[0x20]; 7658 }; 7659 7660 struct mlx5_ifc_create_xrq_in_bits { 7661 u8 opcode[0x10]; 7662 u8 uid[0x10]; 7663 7664 u8 reserved_at_20[0x10]; 7665 u8 op_mod[0x10]; 7666 7667 u8 reserved_at_40[0x40]; 7668 7669 struct mlx5_ifc_xrqc_bits xrq_context; 7670 }; 7671 7672 struct mlx5_ifc_create_xrc_srq_out_bits { 7673 u8 status[0x8]; 7674 u8 reserved_at_8[0x18]; 7675 7676 u8 syndrome[0x20]; 7677 7678 u8 reserved_at_40[0x8]; 7679 u8 xrc_srqn[0x18]; 7680 7681 u8 reserved_at_60[0x20]; 7682 }; 7683 7684 struct mlx5_ifc_create_xrc_srq_in_bits { 7685 u8 opcode[0x10]; 7686 u8 uid[0x10]; 7687 7688 u8 reserved_at_20[0x10]; 7689 u8 op_mod[0x10]; 7690 7691 u8 reserved_at_40[0x40]; 7692 7693 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 7694 7695 u8 reserved_at_280[0x60]; 7696 7697 u8 xrc_srq_umem_valid[0x1]; 7698 u8 reserved_at_2e1[0x1f]; 7699 7700 u8 reserved_at_300[0x580]; 7701 7702 u8 pas[][0x40]; 7703 }; 7704 7705 struct mlx5_ifc_create_tis_out_bits { 7706 u8 status[0x8]; 7707 u8 reserved_at_8[0x18]; 7708 7709 u8 syndrome[0x20]; 7710 7711 u8 reserved_at_40[0x8]; 7712 u8 tisn[0x18]; 7713 7714 u8 reserved_at_60[0x20]; 7715 }; 7716 7717 struct mlx5_ifc_create_tis_in_bits { 7718 u8 opcode[0x10]; 7719 u8 uid[0x10]; 7720 7721 u8 reserved_at_20[0x10]; 7722 u8 op_mod[0x10]; 7723 7724 u8 reserved_at_40[0xc0]; 7725 7726 struct mlx5_ifc_tisc_bits ctx; 7727 }; 7728 7729 struct mlx5_ifc_create_tir_out_bits { 7730 u8 status[0x8]; 7731 u8 icm_address_63_40[0x18]; 7732 7733 u8 syndrome[0x20]; 7734 7735 u8 icm_address_39_32[0x8]; 7736 u8 tirn[0x18]; 7737 7738 u8 icm_address_31_0[0x20]; 7739 }; 7740 7741 struct mlx5_ifc_create_tir_in_bits { 7742 u8 opcode[0x10]; 7743 u8 uid[0x10]; 7744 7745 u8 reserved_at_20[0x10]; 7746 u8 op_mod[0x10]; 7747 7748 u8 reserved_at_40[0xc0]; 7749 7750 struct mlx5_ifc_tirc_bits ctx; 7751 }; 7752 7753 struct mlx5_ifc_create_srq_out_bits { 7754 u8 status[0x8]; 7755 u8 reserved_at_8[0x18]; 7756 7757 u8 syndrome[0x20]; 7758 7759 u8 reserved_at_40[0x8]; 7760 u8 srqn[0x18]; 7761 7762 u8 reserved_at_60[0x20]; 7763 }; 7764 7765 struct mlx5_ifc_create_srq_in_bits { 7766 u8 opcode[0x10]; 7767 u8 uid[0x10]; 7768 7769 u8 reserved_at_20[0x10]; 7770 u8 op_mod[0x10]; 7771 7772 u8 reserved_at_40[0x40]; 7773 7774 struct mlx5_ifc_srqc_bits srq_context_entry; 7775 7776 u8 reserved_at_280[0x600]; 7777 7778 u8 pas[][0x40]; 7779 }; 7780 7781 struct mlx5_ifc_create_sq_out_bits { 7782 u8 status[0x8]; 7783 u8 reserved_at_8[0x18]; 7784 7785 u8 syndrome[0x20]; 7786 7787 u8 reserved_at_40[0x8]; 7788 u8 sqn[0x18]; 7789 7790 u8 reserved_at_60[0x20]; 7791 }; 7792 7793 struct mlx5_ifc_create_sq_in_bits { 7794 u8 opcode[0x10]; 7795 u8 uid[0x10]; 7796 7797 u8 reserved_at_20[0x10]; 7798 u8 op_mod[0x10]; 7799 7800 u8 reserved_at_40[0xc0]; 7801 7802 struct mlx5_ifc_sqc_bits ctx; 7803 }; 7804 7805 struct mlx5_ifc_create_scheduling_element_out_bits { 7806 u8 status[0x8]; 7807 u8 reserved_at_8[0x18]; 7808 7809 u8 syndrome[0x20]; 7810 7811 u8 reserved_at_40[0x40]; 7812 7813 u8 scheduling_element_id[0x20]; 7814 7815 u8 reserved_at_a0[0x160]; 7816 }; 7817 7818 struct mlx5_ifc_create_scheduling_element_in_bits { 7819 u8 opcode[0x10]; 7820 u8 reserved_at_10[0x10]; 7821 7822 u8 reserved_at_20[0x10]; 7823 u8 op_mod[0x10]; 7824 7825 u8 scheduling_hierarchy[0x8]; 7826 u8 reserved_at_48[0x18]; 7827 7828 u8 reserved_at_60[0xa0]; 7829 7830 struct mlx5_ifc_scheduling_context_bits scheduling_context; 7831 7832 u8 reserved_at_300[0x100]; 7833 }; 7834 7835 struct mlx5_ifc_create_rqt_out_bits { 7836 u8 status[0x8]; 7837 u8 reserved_at_8[0x18]; 7838 7839 u8 syndrome[0x20]; 7840 7841 u8 reserved_at_40[0x8]; 7842 u8 rqtn[0x18]; 7843 7844 u8 reserved_at_60[0x20]; 7845 }; 7846 7847 struct mlx5_ifc_create_rqt_in_bits { 7848 u8 opcode[0x10]; 7849 u8 uid[0x10]; 7850 7851 u8 reserved_at_20[0x10]; 7852 u8 op_mod[0x10]; 7853 7854 u8 reserved_at_40[0xc0]; 7855 7856 struct mlx5_ifc_rqtc_bits rqt_context; 7857 }; 7858 7859 struct mlx5_ifc_create_rq_out_bits { 7860 u8 status[0x8]; 7861 u8 reserved_at_8[0x18]; 7862 7863 u8 syndrome[0x20]; 7864 7865 u8 reserved_at_40[0x8]; 7866 u8 rqn[0x18]; 7867 7868 u8 reserved_at_60[0x20]; 7869 }; 7870 7871 struct mlx5_ifc_create_rq_in_bits { 7872 u8 opcode[0x10]; 7873 u8 uid[0x10]; 7874 7875 u8 reserved_at_20[0x10]; 7876 u8 op_mod[0x10]; 7877 7878 u8 reserved_at_40[0xc0]; 7879 7880 struct mlx5_ifc_rqc_bits ctx; 7881 }; 7882 7883 struct mlx5_ifc_create_rmp_out_bits { 7884 u8 status[0x8]; 7885 u8 reserved_at_8[0x18]; 7886 7887 u8 syndrome[0x20]; 7888 7889 u8 reserved_at_40[0x8]; 7890 u8 rmpn[0x18]; 7891 7892 u8 reserved_at_60[0x20]; 7893 }; 7894 7895 struct mlx5_ifc_create_rmp_in_bits { 7896 u8 opcode[0x10]; 7897 u8 uid[0x10]; 7898 7899 u8 reserved_at_20[0x10]; 7900 u8 op_mod[0x10]; 7901 7902 u8 reserved_at_40[0xc0]; 7903 7904 struct mlx5_ifc_rmpc_bits ctx; 7905 }; 7906 7907 struct mlx5_ifc_create_qp_out_bits { 7908 u8 status[0x8]; 7909 u8 reserved_at_8[0x18]; 7910 7911 u8 syndrome[0x20]; 7912 7913 u8 reserved_at_40[0x8]; 7914 u8 qpn[0x18]; 7915 7916 u8 ece[0x20]; 7917 }; 7918 7919 struct mlx5_ifc_create_qp_in_bits { 7920 u8 opcode[0x10]; 7921 u8 uid[0x10]; 7922 7923 u8 reserved_at_20[0x10]; 7924 u8 op_mod[0x10]; 7925 7926 u8 reserved_at_40[0x8]; 7927 u8 input_qpn[0x18]; 7928 7929 u8 reserved_at_60[0x20]; 7930 u8 opt_param_mask[0x20]; 7931 7932 u8 ece[0x20]; 7933 7934 struct mlx5_ifc_qpc_bits qpc; 7935 7936 u8 reserved_at_800[0x60]; 7937 7938 u8 wq_umem_valid[0x1]; 7939 u8 reserved_at_861[0x1f]; 7940 7941 u8 pas[][0x40]; 7942 }; 7943 7944 struct mlx5_ifc_create_psv_out_bits { 7945 u8 status[0x8]; 7946 u8 reserved_at_8[0x18]; 7947 7948 u8 syndrome[0x20]; 7949 7950 u8 reserved_at_40[0x40]; 7951 7952 u8 reserved_at_80[0x8]; 7953 u8 psv0_index[0x18]; 7954 7955 u8 reserved_at_a0[0x8]; 7956 u8 psv1_index[0x18]; 7957 7958 u8 reserved_at_c0[0x8]; 7959 u8 psv2_index[0x18]; 7960 7961 u8 reserved_at_e0[0x8]; 7962 u8 psv3_index[0x18]; 7963 }; 7964 7965 struct mlx5_ifc_create_psv_in_bits { 7966 u8 opcode[0x10]; 7967 u8 reserved_at_10[0x10]; 7968 7969 u8 reserved_at_20[0x10]; 7970 u8 op_mod[0x10]; 7971 7972 u8 num_psv[0x4]; 7973 u8 reserved_at_44[0x4]; 7974 u8 pd[0x18]; 7975 7976 u8 reserved_at_60[0x20]; 7977 }; 7978 7979 struct mlx5_ifc_create_mkey_out_bits { 7980 u8 status[0x8]; 7981 u8 reserved_at_8[0x18]; 7982 7983 u8 syndrome[0x20]; 7984 7985 u8 reserved_at_40[0x8]; 7986 u8 mkey_index[0x18]; 7987 7988 u8 reserved_at_60[0x20]; 7989 }; 7990 7991 struct mlx5_ifc_create_mkey_in_bits { 7992 u8 opcode[0x10]; 7993 u8 uid[0x10]; 7994 7995 u8 reserved_at_20[0x10]; 7996 u8 op_mod[0x10]; 7997 7998 u8 reserved_at_40[0x20]; 7999 8000 u8 pg_access[0x1]; 8001 u8 mkey_umem_valid[0x1]; 8002 u8 reserved_at_62[0x1e]; 8003 8004 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 8005 8006 u8 reserved_at_280[0x80]; 8007 8008 u8 translations_octword_actual_size[0x20]; 8009 8010 u8 reserved_at_320[0x560]; 8011 8012 u8 klm_pas_mtt[][0x20]; 8013 }; 8014 8015 enum { 8016 MLX5_FLOW_TABLE_TYPE_NIC_RX = 0x0, 8017 MLX5_FLOW_TABLE_TYPE_NIC_TX = 0x1, 8018 MLX5_FLOW_TABLE_TYPE_ESW_EGRESS_ACL = 0x2, 8019 MLX5_FLOW_TABLE_TYPE_ESW_INGRESS_ACL = 0x3, 8020 MLX5_FLOW_TABLE_TYPE_FDB = 0X4, 8021 MLX5_FLOW_TABLE_TYPE_SNIFFER_RX = 0X5, 8022 MLX5_FLOW_TABLE_TYPE_SNIFFER_TX = 0X6, 8023 }; 8024 8025 struct mlx5_ifc_create_flow_table_out_bits { 8026 u8 status[0x8]; 8027 u8 icm_address_63_40[0x18]; 8028 8029 u8 syndrome[0x20]; 8030 8031 u8 icm_address_39_32[0x8]; 8032 u8 table_id[0x18]; 8033 8034 u8 icm_address_31_0[0x20]; 8035 }; 8036 8037 struct mlx5_ifc_create_flow_table_in_bits { 8038 u8 opcode[0x10]; 8039 u8 reserved_at_10[0x10]; 8040 8041 u8 reserved_at_20[0x10]; 8042 u8 op_mod[0x10]; 8043 8044 u8 other_vport[0x1]; 8045 u8 reserved_at_41[0xf]; 8046 u8 vport_number[0x10]; 8047 8048 u8 reserved_at_60[0x20]; 8049 8050 u8 table_type[0x8]; 8051 u8 reserved_at_88[0x18]; 8052 8053 u8 reserved_at_a0[0x20]; 8054 8055 struct mlx5_ifc_flow_table_context_bits flow_table_context; 8056 }; 8057 8058 struct mlx5_ifc_create_flow_group_out_bits { 8059 u8 status[0x8]; 8060 u8 reserved_at_8[0x18]; 8061 8062 u8 syndrome[0x20]; 8063 8064 u8 reserved_at_40[0x8]; 8065 u8 group_id[0x18]; 8066 8067 u8 reserved_at_60[0x20]; 8068 }; 8069 8070 enum { 8071 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 8072 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 8073 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 8074 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3, 8075 }; 8076 8077 struct mlx5_ifc_create_flow_group_in_bits { 8078 u8 opcode[0x10]; 8079 u8 reserved_at_10[0x10]; 8080 8081 u8 reserved_at_20[0x10]; 8082 u8 op_mod[0x10]; 8083 8084 u8 other_vport[0x1]; 8085 u8 reserved_at_41[0xf]; 8086 u8 vport_number[0x10]; 8087 8088 u8 reserved_at_60[0x20]; 8089 8090 u8 table_type[0x8]; 8091 u8 reserved_at_88[0x18]; 8092 8093 u8 reserved_at_a0[0x8]; 8094 u8 table_id[0x18]; 8095 8096 u8 source_eswitch_owner_vhca_id_valid[0x1]; 8097 8098 u8 reserved_at_c1[0x1f]; 8099 8100 u8 start_flow_index[0x20]; 8101 8102 u8 reserved_at_100[0x20]; 8103 8104 u8 end_flow_index[0x20]; 8105 8106 u8 reserved_at_140[0xa0]; 8107 8108 u8 reserved_at_1e0[0x18]; 8109 u8 match_criteria_enable[0x8]; 8110 8111 struct mlx5_ifc_fte_match_param_bits match_criteria; 8112 8113 u8 reserved_at_1200[0xe00]; 8114 }; 8115 8116 struct mlx5_ifc_create_eq_out_bits { 8117 u8 status[0x8]; 8118 u8 reserved_at_8[0x18]; 8119 8120 u8 syndrome[0x20]; 8121 8122 u8 reserved_at_40[0x18]; 8123 u8 eq_number[0x8]; 8124 8125 u8 reserved_at_60[0x20]; 8126 }; 8127 8128 struct mlx5_ifc_create_eq_in_bits { 8129 u8 opcode[0x10]; 8130 u8 uid[0x10]; 8131 8132 u8 reserved_at_20[0x10]; 8133 u8 op_mod[0x10]; 8134 8135 u8 reserved_at_40[0x40]; 8136 8137 struct mlx5_ifc_eqc_bits eq_context_entry; 8138 8139 u8 reserved_at_280[0x40]; 8140 8141 u8 event_bitmask[4][0x40]; 8142 8143 u8 reserved_at_3c0[0x4c0]; 8144 8145 u8 pas[][0x40]; 8146 }; 8147 8148 struct mlx5_ifc_create_dct_out_bits { 8149 u8 status[0x8]; 8150 u8 reserved_at_8[0x18]; 8151 8152 u8 syndrome[0x20]; 8153 8154 u8 reserved_at_40[0x8]; 8155 u8 dctn[0x18]; 8156 8157 u8 ece[0x20]; 8158 }; 8159 8160 struct mlx5_ifc_create_dct_in_bits { 8161 u8 opcode[0x10]; 8162 u8 uid[0x10]; 8163 8164 u8 reserved_at_20[0x10]; 8165 u8 op_mod[0x10]; 8166 8167 u8 reserved_at_40[0x40]; 8168 8169 struct mlx5_ifc_dctc_bits dct_context_entry; 8170 8171 u8 reserved_at_280[0x180]; 8172 }; 8173 8174 struct mlx5_ifc_create_cq_out_bits { 8175 u8 status[0x8]; 8176 u8 reserved_at_8[0x18]; 8177 8178 u8 syndrome[0x20]; 8179 8180 u8 reserved_at_40[0x8]; 8181 u8 cqn[0x18]; 8182 8183 u8 reserved_at_60[0x20]; 8184 }; 8185 8186 struct mlx5_ifc_create_cq_in_bits { 8187 u8 opcode[0x10]; 8188 u8 uid[0x10]; 8189 8190 u8 reserved_at_20[0x10]; 8191 u8 op_mod[0x10]; 8192 8193 u8 reserved_at_40[0x40]; 8194 8195 struct mlx5_ifc_cqc_bits cq_context; 8196 8197 u8 reserved_at_280[0x60]; 8198 8199 u8 cq_umem_valid[0x1]; 8200 u8 reserved_at_2e1[0x59f]; 8201 8202 u8 pas[][0x40]; 8203 }; 8204 8205 struct mlx5_ifc_config_int_moderation_out_bits { 8206 u8 status[0x8]; 8207 u8 reserved_at_8[0x18]; 8208 8209 u8 syndrome[0x20]; 8210 8211 u8 reserved_at_40[0x4]; 8212 u8 min_delay[0xc]; 8213 u8 int_vector[0x10]; 8214 8215 u8 reserved_at_60[0x20]; 8216 }; 8217 8218 enum { 8219 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0, 8220 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1, 8221 }; 8222 8223 struct mlx5_ifc_config_int_moderation_in_bits { 8224 u8 opcode[0x10]; 8225 u8 reserved_at_10[0x10]; 8226 8227 u8 reserved_at_20[0x10]; 8228 u8 op_mod[0x10]; 8229 8230 u8 reserved_at_40[0x4]; 8231 u8 min_delay[0xc]; 8232 u8 int_vector[0x10]; 8233 8234 u8 reserved_at_60[0x20]; 8235 }; 8236 8237 struct mlx5_ifc_attach_to_mcg_out_bits { 8238 u8 status[0x8]; 8239 u8 reserved_at_8[0x18]; 8240 8241 u8 syndrome[0x20]; 8242 8243 u8 reserved_at_40[0x40]; 8244 }; 8245 8246 struct mlx5_ifc_attach_to_mcg_in_bits { 8247 u8 opcode[0x10]; 8248 u8 uid[0x10]; 8249 8250 u8 reserved_at_20[0x10]; 8251 u8 op_mod[0x10]; 8252 8253 u8 reserved_at_40[0x8]; 8254 u8 qpn[0x18]; 8255 8256 u8 reserved_at_60[0x20]; 8257 8258 u8 multicast_gid[16][0x8]; 8259 }; 8260 8261 struct mlx5_ifc_arm_xrq_out_bits { 8262 u8 status[0x8]; 8263 u8 reserved_at_8[0x18]; 8264 8265 u8 syndrome[0x20]; 8266 8267 u8 reserved_at_40[0x40]; 8268 }; 8269 8270 struct mlx5_ifc_arm_xrq_in_bits { 8271 u8 opcode[0x10]; 8272 u8 reserved_at_10[0x10]; 8273 8274 u8 reserved_at_20[0x10]; 8275 u8 op_mod[0x10]; 8276 8277 u8 reserved_at_40[0x8]; 8278 u8 xrqn[0x18]; 8279 8280 u8 reserved_at_60[0x10]; 8281 u8 lwm[0x10]; 8282 }; 8283 8284 struct mlx5_ifc_arm_xrc_srq_out_bits { 8285 u8 status[0x8]; 8286 u8 reserved_at_8[0x18]; 8287 8288 u8 syndrome[0x20]; 8289 8290 u8 reserved_at_40[0x40]; 8291 }; 8292 8293 enum { 8294 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1, 8295 }; 8296 8297 struct mlx5_ifc_arm_xrc_srq_in_bits { 8298 u8 opcode[0x10]; 8299 u8 uid[0x10]; 8300 8301 u8 reserved_at_20[0x10]; 8302 u8 op_mod[0x10]; 8303 8304 u8 reserved_at_40[0x8]; 8305 u8 xrc_srqn[0x18]; 8306 8307 u8 reserved_at_60[0x10]; 8308 u8 lwm[0x10]; 8309 }; 8310 8311 struct mlx5_ifc_arm_rq_out_bits { 8312 u8 status[0x8]; 8313 u8 reserved_at_8[0x18]; 8314 8315 u8 syndrome[0x20]; 8316 8317 u8 reserved_at_40[0x40]; 8318 }; 8319 8320 enum { 8321 MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1, 8322 MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2, 8323 }; 8324 8325 struct mlx5_ifc_arm_rq_in_bits { 8326 u8 opcode[0x10]; 8327 u8 uid[0x10]; 8328 8329 u8 reserved_at_20[0x10]; 8330 u8 op_mod[0x10]; 8331 8332 u8 reserved_at_40[0x8]; 8333 u8 srq_number[0x18]; 8334 8335 u8 reserved_at_60[0x10]; 8336 u8 lwm[0x10]; 8337 }; 8338 8339 struct mlx5_ifc_arm_dct_out_bits { 8340 u8 status[0x8]; 8341 u8 reserved_at_8[0x18]; 8342 8343 u8 syndrome[0x20]; 8344 8345 u8 reserved_at_40[0x40]; 8346 }; 8347 8348 struct mlx5_ifc_arm_dct_in_bits { 8349 u8 opcode[0x10]; 8350 u8 reserved_at_10[0x10]; 8351 8352 u8 reserved_at_20[0x10]; 8353 u8 op_mod[0x10]; 8354 8355 u8 reserved_at_40[0x8]; 8356 u8 dct_number[0x18]; 8357 8358 u8 reserved_at_60[0x20]; 8359 }; 8360 8361 struct mlx5_ifc_alloc_xrcd_out_bits { 8362 u8 status[0x8]; 8363 u8 reserved_at_8[0x18]; 8364 8365 u8 syndrome[0x20]; 8366 8367 u8 reserved_at_40[0x8]; 8368 u8 xrcd[0x18]; 8369 8370 u8 reserved_at_60[0x20]; 8371 }; 8372 8373 struct mlx5_ifc_alloc_xrcd_in_bits { 8374 u8 opcode[0x10]; 8375 u8 uid[0x10]; 8376 8377 u8 reserved_at_20[0x10]; 8378 u8 op_mod[0x10]; 8379 8380 u8 reserved_at_40[0x40]; 8381 }; 8382 8383 struct mlx5_ifc_alloc_uar_out_bits { 8384 u8 status[0x8]; 8385 u8 reserved_at_8[0x18]; 8386 8387 u8 syndrome[0x20]; 8388 8389 u8 reserved_at_40[0x8]; 8390 u8 uar[0x18]; 8391 8392 u8 reserved_at_60[0x20]; 8393 }; 8394 8395 struct mlx5_ifc_alloc_uar_in_bits { 8396 u8 opcode[0x10]; 8397 u8 reserved_at_10[0x10]; 8398 8399 u8 reserved_at_20[0x10]; 8400 u8 op_mod[0x10]; 8401 8402 u8 reserved_at_40[0x40]; 8403 }; 8404 8405 struct mlx5_ifc_alloc_transport_domain_out_bits { 8406 u8 status[0x8]; 8407 u8 reserved_at_8[0x18]; 8408 8409 u8 syndrome[0x20]; 8410 8411 u8 reserved_at_40[0x8]; 8412 u8 transport_domain[0x18]; 8413 8414 u8 reserved_at_60[0x20]; 8415 }; 8416 8417 struct mlx5_ifc_alloc_transport_domain_in_bits { 8418 u8 opcode[0x10]; 8419 u8 uid[0x10]; 8420 8421 u8 reserved_at_20[0x10]; 8422 u8 op_mod[0x10]; 8423 8424 u8 reserved_at_40[0x40]; 8425 }; 8426 8427 struct mlx5_ifc_alloc_q_counter_out_bits { 8428 u8 status[0x8]; 8429 u8 reserved_at_8[0x18]; 8430 8431 u8 syndrome[0x20]; 8432 8433 u8 reserved_at_40[0x18]; 8434 u8 counter_set_id[0x8]; 8435 8436 u8 reserved_at_60[0x20]; 8437 }; 8438 8439 struct mlx5_ifc_alloc_q_counter_in_bits { 8440 u8 opcode[0x10]; 8441 u8 uid[0x10]; 8442 8443 u8 reserved_at_20[0x10]; 8444 u8 op_mod[0x10]; 8445 8446 u8 reserved_at_40[0x40]; 8447 }; 8448 8449 struct mlx5_ifc_alloc_pd_out_bits { 8450 u8 status[0x8]; 8451 u8 reserved_at_8[0x18]; 8452 8453 u8 syndrome[0x20]; 8454 8455 u8 reserved_at_40[0x8]; 8456 u8 pd[0x18]; 8457 8458 u8 reserved_at_60[0x20]; 8459 }; 8460 8461 struct mlx5_ifc_alloc_pd_in_bits { 8462 u8 opcode[0x10]; 8463 u8 uid[0x10]; 8464 8465 u8 reserved_at_20[0x10]; 8466 u8 op_mod[0x10]; 8467 8468 u8 reserved_at_40[0x40]; 8469 }; 8470 8471 struct mlx5_ifc_alloc_flow_counter_out_bits { 8472 u8 status[0x8]; 8473 u8 reserved_at_8[0x18]; 8474 8475 u8 syndrome[0x20]; 8476 8477 u8 flow_counter_id[0x20]; 8478 8479 u8 reserved_at_60[0x20]; 8480 }; 8481 8482 struct mlx5_ifc_alloc_flow_counter_in_bits { 8483 u8 opcode[0x10]; 8484 u8 reserved_at_10[0x10]; 8485 8486 u8 reserved_at_20[0x10]; 8487 u8 op_mod[0x10]; 8488 8489 u8 reserved_at_40[0x38]; 8490 u8 flow_counter_bulk[0x8]; 8491 }; 8492 8493 struct mlx5_ifc_add_vxlan_udp_dport_out_bits { 8494 u8 status[0x8]; 8495 u8 reserved_at_8[0x18]; 8496 8497 u8 syndrome[0x20]; 8498 8499 u8 reserved_at_40[0x40]; 8500 }; 8501 8502 struct mlx5_ifc_add_vxlan_udp_dport_in_bits { 8503 u8 opcode[0x10]; 8504 u8 reserved_at_10[0x10]; 8505 8506 u8 reserved_at_20[0x10]; 8507 u8 op_mod[0x10]; 8508 8509 u8 reserved_at_40[0x20]; 8510 8511 u8 reserved_at_60[0x10]; 8512 u8 vxlan_udp_port[0x10]; 8513 }; 8514 8515 struct mlx5_ifc_set_pp_rate_limit_out_bits { 8516 u8 status[0x8]; 8517 u8 reserved_at_8[0x18]; 8518 8519 u8 syndrome[0x20]; 8520 8521 u8 reserved_at_40[0x40]; 8522 }; 8523 8524 struct mlx5_ifc_set_pp_rate_limit_context_bits { 8525 u8 rate_limit[0x20]; 8526 8527 u8 burst_upper_bound[0x20]; 8528 8529 u8 reserved_at_40[0x10]; 8530 u8 typical_packet_size[0x10]; 8531 8532 u8 reserved_at_60[0x120]; 8533 }; 8534 8535 struct mlx5_ifc_set_pp_rate_limit_in_bits { 8536 u8 opcode[0x10]; 8537 u8 uid[0x10]; 8538 8539 u8 reserved_at_20[0x10]; 8540 u8 op_mod[0x10]; 8541 8542 u8 reserved_at_40[0x10]; 8543 u8 rate_limit_index[0x10]; 8544 8545 u8 reserved_at_60[0x20]; 8546 8547 struct mlx5_ifc_set_pp_rate_limit_context_bits ctx; 8548 }; 8549 8550 struct mlx5_ifc_access_register_out_bits { 8551 u8 status[0x8]; 8552 u8 reserved_at_8[0x18]; 8553 8554 u8 syndrome[0x20]; 8555 8556 u8 reserved_at_40[0x40]; 8557 8558 u8 register_data[][0x20]; 8559 }; 8560 8561 enum { 8562 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0, 8563 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1, 8564 }; 8565 8566 struct mlx5_ifc_access_register_in_bits { 8567 u8 opcode[0x10]; 8568 u8 reserved_at_10[0x10]; 8569 8570 u8 reserved_at_20[0x10]; 8571 u8 op_mod[0x10]; 8572 8573 u8 reserved_at_40[0x10]; 8574 u8 register_id[0x10]; 8575 8576 u8 argument[0x20]; 8577 8578 u8 register_data[][0x20]; 8579 }; 8580 8581 struct mlx5_ifc_sltp_reg_bits { 8582 u8 status[0x4]; 8583 u8 version[0x4]; 8584 u8 local_port[0x8]; 8585 u8 pnat[0x2]; 8586 u8 reserved_at_12[0x2]; 8587 u8 lane[0x4]; 8588 u8 reserved_at_18[0x8]; 8589 8590 u8 reserved_at_20[0x20]; 8591 8592 u8 reserved_at_40[0x7]; 8593 u8 polarity[0x1]; 8594 u8 ob_tap0[0x8]; 8595 u8 ob_tap1[0x8]; 8596 u8 ob_tap2[0x8]; 8597 8598 u8 reserved_at_60[0xc]; 8599 u8 ob_preemp_mode[0x4]; 8600 u8 ob_reg[0x8]; 8601 u8 ob_bias[0x8]; 8602 8603 u8 reserved_at_80[0x20]; 8604 }; 8605 8606 struct mlx5_ifc_slrg_reg_bits { 8607 u8 status[0x4]; 8608 u8 version[0x4]; 8609 u8 local_port[0x8]; 8610 u8 pnat[0x2]; 8611 u8 reserved_at_12[0x2]; 8612 u8 lane[0x4]; 8613 u8 reserved_at_18[0x8]; 8614 8615 u8 time_to_link_up[0x10]; 8616 u8 reserved_at_30[0xc]; 8617 u8 grade_lane_speed[0x4]; 8618 8619 u8 grade_version[0x8]; 8620 u8 grade[0x18]; 8621 8622 u8 reserved_at_60[0x4]; 8623 u8 height_grade_type[0x4]; 8624 u8 height_grade[0x18]; 8625 8626 u8 height_dz[0x10]; 8627 u8 height_dv[0x10]; 8628 8629 u8 reserved_at_a0[0x10]; 8630 u8 height_sigma[0x10]; 8631 8632 u8 reserved_at_c0[0x20]; 8633 8634 u8 reserved_at_e0[0x4]; 8635 u8 phase_grade_type[0x4]; 8636 u8 phase_grade[0x18]; 8637 8638 u8 reserved_at_100[0x8]; 8639 u8 phase_eo_pos[0x8]; 8640 u8 reserved_at_110[0x8]; 8641 u8 phase_eo_neg[0x8]; 8642 8643 u8 ffe_set_tested[0x10]; 8644 u8 test_errors_per_lane[0x10]; 8645 }; 8646 8647 struct mlx5_ifc_pvlc_reg_bits { 8648 u8 reserved_at_0[0x8]; 8649 u8 local_port[0x8]; 8650 u8 reserved_at_10[0x10]; 8651 8652 u8 reserved_at_20[0x1c]; 8653 u8 vl_hw_cap[0x4]; 8654 8655 u8 reserved_at_40[0x1c]; 8656 u8 vl_admin[0x4]; 8657 8658 u8 reserved_at_60[0x1c]; 8659 u8 vl_operational[0x4]; 8660 }; 8661 8662 struct mlx5_ifc_pude_reg_bits { 8663 u8 swid[0x8]; 8664 u8 local_port[0x8]; 8665 u8 reserved_at_10[0x4]; 8666 u8 admin_status[0x4]; 8667 u8 reserved_at_18[0x4]; 8668 u8 oper_status[0x4]; 8669 8670 u8 reserved_at_20[0x60]; 8671 }; 8672 8673 struct mlx5_ifc_ptys_reg_bits { 8674 u8 reserved_at_0[0x1]; 8675 u8 an_disable_admin[0x1]; 8676 u8 an_disable_cap[0x1]; 8677 u8 reserved_at_3[0x5]; 8678 u8 local_port[0x8]; 8679 u8 reserved_at_10[0xd]; 8680 u8 proto_mask[0x3]; 8681 8682 u8 an_status[0x4]; 8683 u8 reserved_at_24[0xc]; 8684 u8 data_rate_oper[0x10]; 8685 8686 u8 ext_eth_proto_capability[0x20]; 8687 8688 u8 eth_proto_capability[0x20]; 8689 8690 u8 ib_link_width_capability[0x10]; 8691 u8 ib_proto_capability[0x10]; 8692 8693 u8 ext_eth_proto_admin[0x20]; 8694 8695 u8 eth_proto_admin[0x20]; 8696 8697 u8 ib_link_width_admin[0x10]; 8698 u8 ib_proto_admin[0x10]; 8699 8700 u8 ext_eth_proto_oper[0x20]; 8701 8702 u8 eth_proto_oper[0x20]; 8703 8704 u8 ib_link_width_oper[0x10]; 8705 u8 ib_proto_oper[0x10]; 8706 8707 u8 reserved_at_160[0x1c]; 8708 u8 connector_type[0x4]; 8709 8710 u8 eth_proto_lp_advertise[0x20]; 8711 8712 u8 reserved_at_1a0[0x60]; 8713 }; 8714 8715 struct mlx5_ifc_mlcr_reg_bits { 8716 u8 reserved_at_0[0x8]; 8717 u8 local_port[0x8]; 8718 u8 reserved_at_10[0x20]; 8719 8720 u8 beacon_duration[0x10]; 8721 u8 reserved_at_40[0x10]; 8722 8723 u8 beacon_remain[0x10]; 8724 }; 8725 8726 struct mlx5_ifc_ptas_reg_bits { 8727 u8 reserved_at_0[0x20]; 8728 8729 u8 algorithm_options[0x10]; 8730 u8 reserved_at_30[0x4]; 8731 u8 repetitions_mode[0x4]; 8732 u8 num_of_repetitions[0x8]; 8733 8734 u8 grade_version[0x8]; 8735 u8 height_grade_type[0x4]; 8736 u8 phase_grade_type[0x4]; 8737 u8 height_grade_weight[0x8]; 8738 u8 phase_grade_weight[0x8]; 8739 8740 u8 gisim_measure_bits[0x10]; 8741 u8 adaptive_tap_measure_bits[0x10]; 8742 8743 u8 ber_bath_high_error_threshold[0x10]; 8744 u8 ber_bath_mid_error_threshold[0x10]; 8745 8746 u8 ber_bath_low_error_threshold[0x10]; 8747 u8 one_ratio_high_threshold[0x10]; 8748 8749 u8 one_ratio_high_mid_threshold[0x10]; 8750 u8 one_ratio_low_mid_threshold[0x10]; 8751 8752 u8 one_ratio_low_threshold[0x10]; 8753 u8 ndeo_error_threshold[0x10]; 8754 8755 u8 mixer_offset_step_size[0x10]; 8756 u8 reserved_at_110[0x8]; 8757 u8 mix90_phase_for_voltage_bath[0x8]; 8758 8759 u8 mixer_offset_start[0x10]; 8760 u8 mixer_offset_end[0x10]; 8761 8762 u8 reserved_at_140[0x15]; 8763 u8 ber_test_time[0xb]; 8764 }; 8765 8766 struct mlx5_ifc_pspa_reg_bits { 8767 u8 swid[0x8]; 8768 u8 local_port[0x8]; 8769 u8 sub_port[0x8]; 8770 u8 reserved_at_18[0x8]; 8771 8772 u8 reserved_at_20[0x20]; 8773 }; 8774 8775 struct mlx5_ifc_pqdr_reg_bits { 8776 u8 reserved_at_0[0x8]; 8777 u8 local_port[0x8]; 8778 u8 reserved_at_10[0x5]; 8779 u8 prio[0x3]; 8780 u8 reserved_at_18[0x6]; 8781 u8 mode[0x2]; 8782 8783 u8 reserved_at_20[0x20]; 8784 8785 u8 reserved_at_40[0x10]; 8786 u8 min_threshold[0x10]; 8787 8788 u8 reserved_at_60[0x10]; 8789 u8 max_threshold[0x10]; 8790 8791 u8 reserved_at_80[0x10]; 8792 u8 mark_probability_denominator[0x10]; 8793 8794 u8 reserved_at_a0[0x60]; 8795 }; 8796 8797 struct mlx5_ifc_ppsc_reg_bits { 8798 u8 reserved_at_0[0x8]; 8799 u8 local_port[0x8]; 8800 u8 reserved_at_10[0x10]; 8801 8802 u8 reserved_at_20[0x60]; 8803 8804 u8 reserved_at_80[0x1c]; 8805 u8 wrps_admin[0x4]; 8806 8807 u8 reserved_at_a0[0x1c]; 8808 u8 wrps_status[0x4]; 8809 8810 u8 reserved_at_c0[0x8]; 8811 u8 up_threshold[0x8]; 8812 u8 reserved_at_d0[0x8]; 8813 u8 down_threshold[0x8]; 8814 8815 u8 reserved_at_e0[0x20]; 8816 8817 u8 reserved_at_100[0x1c]; 8818 u8 srps_admin[0x4]; 8819 8820 u8 reserved_at_120[0x1c]; 8821 u8 srps_status[0x4]; 8822 8823 u8 reserved_at_140[0x40]; 8824 }; 8825 8826 struct mlx5_ifc_pplr_reg_bits { 8827 u8 reserved_at_0[0x8]; 8828 u8 local_port[0x8]; 8829 u8 reserved_at_10[0x10]; 8830 8831 u8 reserved_at_20[0x8]; 8832 u8 lb_cap[0x8]; 8833 u8 reserved_at_30[0x8]; 8834 u8 lb_en[0x8]; 8835 }; 8836 8837 struct mlx5_ifc_pplm_reg_bits { 8838 u8 reserved_at_0[0x8]; 8839 u8 local_port[0x8]; 8840 u8 reserved_at_10[0x10]; 8841 8842 u8 reserved_at_20[0x20]; 8843 8844 u8 port_profile_mode[0x8]; 8845 u8 static_port_profile[0x8]; 8846 u8 active_port_profile[0x8]; 8847 u8 reserved_at_58[0x8]; 8848 8849 u8 retransmission_active[0x8]; 8850 u8 fec_mode_active[0x18]; 8851 8852 u8 rs_fec_correction_bypass_cap[0x4]; 8853 u8 reserved_at_84[0x8]; 8854 u8 fec_override_cap_56g[0x4]; 8855 u8 fec_override_cap_100g[0x4]; 8856 u8 fec_override_cap_50g[0x4]; 8857 u8 fec_override_cap_25g[0x4]; 8858 u8 fec_override_cap_10g_40g[0x4]; 8859 8860 u8 rs_fec_correction_bypass_admin[0x4]; 8861 u8 reserved_at_a4[0x8]; 8862 u8 fec_override_admin_56g[0x4]; 8863 u8 fec_override_admin_100g[0x4]; 8864 u8 fec_override_admin_50g[0x4]; 8865 u8 fec_override_admin_25g[0x4]; 8866 u8 fec_override_admin_10g_40g[0x4]; 8867 8868 u8 fec_override_cap_400g_8x[0x10]; 8869 u8 fec_override_cap_200g_4x[0x10]; 8870 8871 u8 fec_override_cap_100g_2x[0x10]; 8872 u8 fec_override_cap_50g_1x[0x10]; 8873 8874 u8 fec_override_admin_400g_8x[0x10]; 8875 u8 fec_override_admin_200g_4x[0x10]; 8876 8877 u8 fec_override_admin_100g_2x[0x10]; 8878 u8 fec_override_admin_50g_1x[0x10]; 8879 8880 u8 reserved_at_140[0x140]; 8881 }; 8882 8883 struct mlx5_ifc_ppcnt_reg_bits { 8884 u8 swid[0x8]; 8885 u8 local_port[0x8]; 8886 u8 pnat[0x2]; 8887 u8 reserved_at_12[0x8]; 8888 u8 grp[0x6]; 8889 8890 u8 clr[0x1]; 8891 u8 reserved_at_21[0x1c]; 8892 u8 prio_tc[0x3]; 8893 8894 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set; 8895 }; 8896 8897 struct mlx5_ifc_mpein_reg_bits { 8898 u8 reserved_at_0[0x2]; 8899 u8 depth[0x6]; 8900 u8 pcie_index[0x8]; 8901 u8 node[0x8]; 8902 u8 reserved_at_18[0x8]; 8903 8904 u8 capability_mask[0x20]; 8905 8906 u8 reserved_at_40[0x8]; 8907 u8 link_width_enabled[0x8]; 8908 u8 link_speed_enabled[0x10]; 8909 8910 u8 lane0_physical_position[0x8]; 8911 u8 link_width_active[0x8]; 8912 u8 link_speed_active[0x10]; 8913 8914 u8 num_of_pfs[0x10]; 8915 u8 num_of_vfs[0x10]; 8916 8917 u8 bdf0[0x10]; 8918 u8 reserved_at_b0[0x10]; 8919 8920 u8 max_read_request_size[0x4]; 8921 u8 max_payload_size[0x4]; 8922 u8 reserved_at_c8[0x5]; 8923 u8 pwr_status[0x3]; 8924 u8 port_type[0x4]; 8925 u8 reserved_at_d4[0xb]; 8926 u8 lane_reversal[0x1]; 8927 8928 u8 reserved_at_e0[0x14]; 8929 u8 pci_power[0xc]; 8930 8931 u8 reserved_at_100[0x20]; 8932 8933 u8 device_status[0x10]; 8934 u8 port_state[0x8]; 8935 u8 reserved_at_138[0x8]; 8936 8937 u8 reserved_at_140[0x10]; 8938 u8 receiver_detect_result[0x10]; 8939 8940 u8 reserved_at_160[0x20]; 8941 }; 8942 8943 struct mlx5_ifc_mpcnt_reg_bits { 8944 u8 reserved_at_0[0x8]; 8945 u8 pcie_index[0x8]; 8946 u8 reserved_at_10[0xa]; 8947 u8 grp[0x6]; 8948 8949 u8 clr[0x1]; 8950 u8 reserved_at_21[0x1f]; 8951 8952 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set; 8953 }; 8954 8955 struct mlx5_ifc_ppad_reg_bits { 8956 u8 reserved_at_0[0x3]; 8957 u8 single_mac[0x1]; 8958 u8 reserved_at_4[0x4]; 8959 u8 local_port[0x8]; 8960 u8 mac_47_32[0x10]; 8961 8962 u8 mac_31_0[0x20]; 8963 8964 u8 reserved_at_40[0x40]; 8965 }; 8966 8967 struct mlx5_ifc_pmtu_reg_bits { 8968 u8 reserved_at_0[0x8]; 8969 u8 local_port[0x8]; 8970 u8 reserved_at_10[0x10]; 8971 8972 u8 max_mtu[0x10]; 8973 u8 reserved_at_30[0x10]; 8974 8975 u8 admin_mtu[0x10]; 8976 u8 reserved_at_50[0x10]; 8977 8978 u8 oper_mtu[0x10]; 8979 u8 reserved_at_70[0x10]; 8980 }; 8981 8982 struct mlx5_ifc_pmpr_reg_bits { 8983 u8 reserved_at_0[0x8]; 8984 u8 module[0x8]; 8985 u8 reserved_at_10[0x10]; 8986 8987 u8 reserved_at_20[0x18]; 8988 u8 attenuation_5g[0x8]; 8989 8990 u8 reserved_at_40[0x18]; 8991 u8 attenuation_7g[0x8]; 8992 8993 u8 reserved_at_60[0x18]; 8994 u8 attenuation_12g[0x8]; 8995 }; 8996 8997 struct mlx5_ifc_pmpe_reg_bits { 8998 u8 reserved_at_0[0x8]; 8999 u8 module[0x8]; 9000 u8 reserved_at_10[0xc]; 9001 u8 module_status[0x4]; 9002 9003 u8 reserved_at_20[0x60]; 9004 }; 9005 9006 struct mlx5_ifc_pmpc_reg_bits { 9007 u8 module_state_updated[32][0x8]; 9008 }; 9009 9010 struct mlx5_ifc_pmlpn_reg_bits { 9011 u8 reserved_at_0[0x4]; 9012 u8 mlpn_status[0x4]; 9013 u8 local_port[0x8]; 9014 u8 reserved_at_10[0x10]; 9015 9016 u8 e[0x1]; 9017 u8 reserved_at_21[0x1f]; 9018 }; 9019 9020 struct mlx5_ifc_pmlp_reg_bits { 9021 u8 rxtx[0x1]; 9022 u8 reserved_at_1[0x7]; 9023 u8 local_port[0x8]; 9024 u8 reserved_at_10[0x8]; 9025 u8 width[0x8]; 9026 9027 u8 lane0_module_mapping[0x20]; 9028 9029 u8 lane1_module_mapping[0x20]; 9030 9031 u8 lane2_module_mapping[0x20]; 9032 9033 u8 lane3_module_mapping[0x20]; 9034 9035 u8 reserved_at_a0[0x160]; 9036 }; 9037 9038 struct mlx5_ifc_pmaos_reg_bits { 9039 u8 reserved_at_0[0x8]; 9040 u8 module[0x8]; 9041 u8 reserved_at_10[0x4]; 9042 u8 admin_status[0x4]; 9043 u8 reserved_at_18[0x4]; 9044 u8 oper_status[0x4]; 9045 9046 u8 ase[0x1]; 9047 u8 ee[0x1]; 9048 u8 reserved_at_22[0x1c]; 9049 u8 e[0x2]; 9050 9051 u8 reserved_at_40[0x40]; 9052 }; 9053 9054 struct mlx5_ifc_plpc_reg_bits { 9055 u8 reserved_at_0[0x4]; 9056 u8 profile_id[0xc]; 9057 u8 reserved_at_10[0x4]; 9058 u8 proto_mask[0x4]; 9059 u8 reserved_at_18[0x8]; 9060 9061 u8 reserved_at_20[0x10]; 9062 u8 lane_speed[0x10]; 9063 9064 u8 reserved_at_40[0x17]; 9065 u8 lpbf[0x1]; 9066 u8 fec_mode_policy[0x8]; 9067 9068 u8 retransmission_capability[0x8]; 9069 u8 fec_mode_capability[0x18]; 9070 9071 u8 retransmission_support_admin[0x8]; 9072 u8 fec_mode_support_admin[0x18]; 9073 9074 u8 retransmission_request_admin[0x8]; 9075 u8 fec_mode_request_admin[0x18]; 9076 9077 u8 reserved_at_c0[0x80]; 9078 }; 9079 9080 struct mlx5_ifc_plib_reg_bits { 9081 u8 reserved_at_0[0x8]; 9082 u8 local_port[0x8]; 9083 u8 reserved_at_10[0x8]; 9084 u8 ib_port[0x8]; 9085 9086 u8 reserved_at_20[0x60]; 9087 }; 9088 9089 struct mlx5_ifc_plbf_reg_bits { 9090 u8 reserved_at_0[0x8]; 9091 u8 local_port[0x8]; 9092 u8 reserved_at_10[0xd]; 9093 u8 lbf_mode[0x3]; 9094 9095 u8 reserved_at_20[0x20]; 9096 }; 9097 9098 struct mlx5_ifc_pipg_reg_bits { 9099 u8 reserved_at_0[0x8]; 9100 u8 local_port[0x8]; 9101 u8 reserved_at_10[0x10]; 9102 9103 u8 dic[0x1]; 9104 u8 reserved_at_21[0x19]; 9105 u8 ipg[0x4]; 9106 u8 reserved_at_3e[0x2]; 9107 }; 9108 9109 struct mlx5_ifc_pifr_reg_bits { 9110 u8 reserved_at_0[0x8]; 9111 u8 local_port[0x8]; 9112 u8 reserved_at_10[0x10]; 9113 9114 u8 reserved_at_20[0xe0]; 9115 9116 u8 port_filter[8][0x20]; 9117 9118 u8 port_filter_update_en[8][0x20]; 9119 }; 9120 9121 struct mlx5_ifc_pfcc_reg_bits { 9122 u8 reserved_at_0[0x8]; 9123 u8 local_port[0x8]; 9124 u8 reserved_at_10[0xb]; 9125 u8 ppan_mask_n[0x1]; 9126 u8 minor_stall_mask[0x1]; 9127 u8 critical_stall_mask[0x1]; 9128 u8 reserved_at_1e[0x2]; 9129 9130 u8 ppan[0x4]; 9131 u8 reserved_at_24[0x4]; 9132 u8 prio_mask_tx[0x8]; 9133 u8 reserved_at_30[0x8]; 9134 u8 prio_mask_rx[0x8]; 9135 9136 u8 pptx[0x1]; 9137 u8 aptx[0x1]; 9138 u8 pptx_mask_n[0x1]; 9139 u8 reserved_at_43[0x5]; 9140 u8 pfctx[0x8]; 9141 u8 reserved_at_50[0x10]; 9142 9143 u8 pprx[0x1]; 9144 u8 aprx[0x1]; 9145 u8 pprx_mask_n[0x1]; 9146 u8 reserved_at_63[0x5]; 9147 u8 pfcrx[0x8]; 9148 u8 reserved_at_70[0x10]; 9149 9150 u8 device_stall_minor_watermark[0x10]; 9151 u8 device_stall_critical_watermark[0x10]; 9152 9153 u8 reserved_at_a0[0x60]; 9154 }; 9155 9156 struct mlx5_ifc_pelc_reg_bits { 9157 u8 op[0x4]; 9158 u8 reserved_at_4[0x4]; 9159 u8 local_port[0x8]; 9160 u8 reserved_at_10[0x10]; 9161 9162 u8 op_admin[0x8]; 9163 u8 op_capability[0x8]; 9164 u8 op_request[0x8]; 9165 u8 op_active[0x8]; 9166 9167 u8 admin[0x40]; 9168 9169 u8 capability[0x40]; 9170 9171 u8 request[0x40]; 9172 9173 u8 active[0x40]; 9174 9175 u8 reserved_at_140[0x80]; 9176 }; 9177 9178 struct mlx5_ifc_peir_reg_bits { 9179 u8 reserved_at_0[0x8]; 9180 u8 local_port[0x8]; 9181 u8 reserved_at_10[0x10]; 9182 9183 u8 reserved_at_20[0xc]; 9184 u8 error_count[0x4]; 9185 u8 reserved_at_30[0x10]; 9186 9187 u8 reserved_at_40[0xc]; 9188 u8 lane[0x4]; 9189 u8 reserved_at_50[0x8]; 9190 u8 error_type[0x8]; 9191 }; 9192 9193 struct mlx5_ifc_mpegc_reg_bits { 9194 u8 reserved_at_0[0x30]; 9195 u8 field_select[0x10]; 9196 9197 u8 tx_overflow_sense[0x1]; 9198 u8 mark_cqe[0x1]; 9199 u8 mark_cnp[0x1]; 9200 u8 reserved_at_43[0x1b]; 9201 u8 tx_lossy_overflow_oper[0x2]; 9202 9203 u8 reserved_at_60[0x100]; 9204 }; 9205 9206 enum { 9207 MLX5_MTUTC_OPERATION_SET_TIME_IMMEDIATE = 0x1, 9208 MLX5_MTUTC_OPERATION_ADJUST_TIME = 0x2, 9209 MLX5_MTUTC_OPERATION_ADJUST_FREQ_UTC = 0x3, 9210 }; 9211 9212 struct mlx5_ifc_mtutc_reg_bits { 9213 u8 reserved_at_0[0x1c]; 9214 u8 operation[0x4]; 9215 9216 u8 freq_adjustment[0x20]; 9217 9218 u8 reserved_at_40[0x40]; 9219 9220 u8 utc_sec[0x20]; 9221 9222 u8 reserved_at_a0[0x2]; 9223 u8 utc_nsec[0x1e]; 9224 9225 u8 time_adjustment[0x20]; 9226 }; 9227 9228 struct mlx5_ifc_pcam_enhanced_features_bits { 9229 u8 reserved_at_0[0x68]; 9230 u8 fec_50G_per_lane_in_pplm[0x1]; 9231 u8 reserved_at_69[0x4]; 9232 u8 rx_icrc_encapsulated_counter[0x1]; 9233 u8 reserved_at_6e[0x4]; 9234 u8 ptys_extended_ethernet[0x1]; 9235 u8 reserved_at_73[0x3]; 9236 u8 pfcc_mask[0x1]; 9237 u8 reserved_at_77[0x3]; 9238 u8 per_lane_error_counters[0x1]; 9239 u8 rx_buffer_fullness_counters[0x1]; 9240 u8 ptys_connector_type[0x1]; 9241 u8 reserved_at_7d[0x1]; 9242 u8 ppcnt_discard_group[0x1]; 9243 u8 ppcnt_statistical_group[0x1]; 9244 }; 9245 9246 struct mlx5_ifc_pcam_regs_5000_to_507f_bits { 9247 u8 port_access_reg_cap_mask_127_to_96[0x20]; 9248 u8 port_access_reg_cap_mask_95_to_64[0x20]; 9249 9250 u8 port_access_reg_cap_mask_63_to_36[0x1c]; 9251 u8 pplm[0x1]; 9252 u8 port_access_reg_cap_mask_34_to_32[0x3]; 9253 9254 u8 port_access_reg_cap_mask_31_to_13[0x13]; 9255 u8 pbmc[0x1]; 9256 u8 pptb[0x1]; 9257 u8 port_access_reg_cap_mask_10_to_09[0x2]; 9258 u8 ppcnt[0x1]; 9259 u8 port_access_reg_cap_mask_07_to_00[0x8]; 9260 }; 9261 9262 struct mlx5_ifc_pcam_reg_bits { 9263 u8 reserved_at_0[0x8]; 9264 u8 feature_group[0x8]; 9265 u8 reserved_at_10[0x8]; 9266 u8 access_reg_group[0x8]; 9267 9268 u8 reserved_at_20[0x20]; 9269 9270 union { 9271 struct mlx5_ifc_pcam_regs_5000_to_507f_bits regs_5000_to_507f; 9272 u8 reserved_at_0[0x80]; 9273 } port_access_reg_cap_mask; 9274 9275 u8 reserved_at_c0[0x80]; 9276 9277 union { 9278 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features; 9279 u8 reserved_at_0[0x80]; 9280 } feature_cap_mask; 9281 9282 u8 reserved_at_1c0[0xc0]; 9283 }; 9284 9285 struct mlx5_ifc_mcam_enhanced_features_bits { 9286 u8 reserved_at_0[0x6b]; 9287 u8 ptpcyc2realtime_modify[0x1]; 9288 u8 reserved_at_6c[0x2]; 9289 u8 pci_status_and_power[0x1]; 9290 u8 reserved_at_6f[0x5]; 9291 u8 mark_tx_action_cnp[0x1]; 9292 u8 mark_tx_action_cqe[0x1]; 9293 u8 dynamic_tx_overflow[0x1]; 9294 u8 reserved_at_77[0x4]; 9295 u8 pcie_outbound_stalled[0x1]; 9296 u8 tx_overflow_buffer_pkt[0x1]; 9297 u8 mtpps_enh_out_per_adj[0x1]; 9298 u8 mtpps_fs[0x1]; 9299 u8 pcie_performance_group[0x1]; 9300 }; 9301 9302 struct mlx5_ifc_mcam_access_reg_bits { 9303 u8 reserved_at_0[0x1c]; 9304 u8 mcda[0x1]; 9305 u8 mcc[0x1]; 9306 u8 mcqi[0x1]; 9307 u8 mcqs[0x1]; 9308 9309 u8 regs_95_to_87[0x9]; 9310 u8 mpegc[0x1]; 9311 u8 mtutc[0x1]; 9312 u8 regs_84_to_68[0x11]; 9313 u8 tracer_registers[0x4]; 9314 9315 u8 regs_63_to_32[0x20]; 9316 u8 regs_31_to_0[0x20]; 9317 }; 9318 9319 struct mlx5_ifc_mcam_access_reg_bits1 { 9320 u8 regs_127_to_96[0x20]; 9321 9322 u8 regs_95_to_64[0x20]; 9323 9324 u8 regs_63_to_32[0x20]; 9325 9326 u8 regs_31_to_0[0x20]; 9327 }; 9328 9329 struct mlx5_ifc_mcam_access_reg_bits2 { 9330 u8 regs_127_to_99[0x1d]; 9331 u8 mirc[0x1]; 9332 u8 regs_97_to_96[0x2]; 9333 9334 u8 regs_95_to_64[0x20]; 9335 9336 u8 regs_63_to_32[0x20]; 9337 9338 u8 regs_31_to_0[0x20]; 9339 }; 9340 9341 struct mlx5_ifc_mcam_reg_bits { 9342 u8 reserved_at_0[0x8]; 9343 u8 feature_group[0x8]; 9344 u8 reserved_at_10[0x8]; 9345 u8 access_reg_group[0x8]; 9346 9347 u8 reserved_at_20[0x20]; 9348 9349 union { 9350 struct mlx5_ifc_mcam_access_reg_bits access_regs; 9351 struct mlx5_ifc_mcam_access_reg_bits1 access_regs1; 9352 struct mlx5_ifc_mcam_access_reg_bits2 access_regs2; 9353 u8 reserved_at_0[0x80]; 9354 } mng_access_reg_cap_mask; 9355 9356 u8 reserved_at_c0[0x80]; 9357 9358 union { 9359 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features; 9360 u8 reserved_at_0[0x80]; 9361 } mng_feature_cap_mask; 9362 9363 u8 reserved_at_1c0[0x80]; 9364 }; 9365 9366 struct mlx5_ifc_qcam_access_reg_cap_mask { 9367 u8 qcam_access_reg_cap_mask_127_to_20[0x6C]; 9368 u8 qpdpm[0x1]; 9369 u8 qcam_access_reg_cap_mask_18_to_4[0x0F]; 9370 u8 qdpm[0x1]; 9371 u8 qpts[0x1]; 9372 u8 qcap[0x1]; 9373 u8 qcam_access_reg_cap_mask_0[0x1]; 9374 }; 9375 9376 struct mlx5_ifc_qcam_qos_feature_cap_mask { 9377 u8 qcam_qos_feature_cap_mask_127_to_1[0x7F]; 9378 u8 qpts_trust_both[0x1]; 9379 }; 9380 9381 struct mlx5_ifc_qcam_reg_bits { 9382 u8 reserved_at_0[0x8]; 9383 u8 feature_group[0x8]; 9384 u8 reserved_at_10[0x8]; 9385 u8 access_reg_group[0x8]; 9386 u8 reserved_at_20[0x20]; 9387 9388 union { 9389 struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap; 9390 u8 reserved_at_0[0x80]; 9391 } qos_access_reg_cap_mask; 9392 9393 u8 reserved_at_c0[0x80]; 9394 9395 union { 9396 struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap; 9397 u8 reserved_at_0[0x80]; 9398 } qos_feature_cap_mask; 9399 9400 u8 reserved_at_1c0[0x80]; 9401 }; 9402 9403 struct mlx5_ifc_core_dump_reg_bits { 9404 u8 reserved_at_0[0x18]; 9405 u8 core_dump_type[0x8]; 9406 9407 u8 reserved_at_20[0x30]; 9408 u8 vhca_id[0x10]; 9409 9410 u8 reserved_at_60[0x8]; 9411 u8 qpn[0x18]; 9412 u8 reserved_at_80[0x180]; 9413 }; 9414 9415 struct mlx5_ifc_pcap_reg_bits { 9416 u8 reserved_at_0[0x8]; 9417 u8 local_port[0x8]; 9418 u8 reserved_at_10[0x10]; 9419 9420 u8 port_capability_mask[4][0x20]; 9421 }; 9422 9423 struct mlx5_ifc_paos_reg_bits { 9424 u8 swid[0x8]; 9425 u8 local_port[0x8]; 9426 u8 reserved_at_10[0x4]; 9427 u8 admin_status[0x4]; 9428 u8 reserved_at_18[0x4]; 9429 u8 oper_status[0x4]; 9430 9431 u8 ase[0x1]; 9432 u8 ee[0x1]; 9433 u8 reserved_at_22[0x1c]; 9434 u8 e[0x2]; 9435 9436 u8 reserved_at_40[0x40]; 9437 }; 9438 9439 struct mlx5_ifc_pamp_reg_bits { 9440 u8 reserved_at_0[0x8]; 9441 u8 opamp_group[0x8]; 9442 u8 reserved_at_10[0xc]; 9443 u8 opamp_group_type[0x4]; 9444 9445 u8 start_index[0x10]; 9446 u8 reserved_at_30[0x4]; 9447 u8 num_of_indices[0xc]; 9448 9449 u8 index_data[18][0x10]; 9450 }; 9451 9452 struct mlx5_ifc_pcmr_reg_bits { 9453 u8 reserved_at_0[0x8]; 9454 u8 local_port[0x8]; 9455 u8 reserved_at_10[0x10]; 9456 u8 entropy_force_cap[0x1]; 9457 u8 entropy_calc_cap[0x1]; 9458 u8 entropy_gre_calc_cap[0x1]; 9459 u8 reserved_at_23[0x1b]; 9460 u8 fcs_cap[0x1]; 9461 u8 reserved_at_3f[0x1]; 9462 u8 entropy_force[0x1]; 9463 u8 entropy_calc[0x1]; 9464 u8 entropy_gre_calc[0x1]; 9465 u8 reserved_at_43[0x1b]; 9466 u8 fcs_chk[0x1]; 9467 u8 reserved_at_5f[0x1]; 9468 }; 9469 9470 struct mlx5_ifc_lane_2_module_mapping_bits { 9471 u8 reserved_at_0[0x6]; 9472 u8 rx_lane[0x2]; 9473 u8 reserved_at_8[0x6]; 9474 u8 tx_lane[0x2]; 9475 u8 reserved_at_10[0x8]; 9476 u8 module[0x8]; 9477 }; 9478 9479 struct mlx5_ifc_bufferx_reg_bits { 9480 u8 reserved_at_0[0x6]; 9481 u8 lossy[0x1]; 9482 u8 epsb[0x1]; 9483 u8 reserved_at_8[0xc]; 9484 u8 size[0xc]; 9485 9486 u8 xoff_threshold[0x10]; 9487 u8 xon_threshold[0x10]; 9488 }; 9489 9490 struct mlx5_ifc_set_node_in_bits { 9491 u8 node_description[64][0x8]; 9492 }; 9493 9494 struct mlx5_ifc_register_power_settings_bits { 9495 u8 reserved_at_0[0x18]; 9496 u8 power_settings_level[0x8]; 9497 9498 u8 reserved_at_20[0x60]; 9499 }; 9500 9501 struct mlx5_ifc_register_host_endianness_bits { 9502 u8 he[0x1]; 9503 u8 reserved_at_1[0x1f]; 9504 9505 u8 reserved_at_20[0x60]; 9506 }; 9507 9508 struct mlx5_ifc_umr_pointer_desc_argument_bits { 9509 u8 reserved_at_0[0x20]; 9510 9511 u8 mkey[0x20]; 9512 9513 u8 addressh_63_32[0x20]; 9514 9515 u8 addressl_31_0[0x20]; 9516 }; 9517 9518 struct mlx5_ifc_ud_adrs_vector_bits { 9519 u8 dc_key[0x40]; 9520 9521 u8 ext[0x1]; 9522 u8 reserved_at_41[0x7]; 9523 u8 destination_qp_dct[0x18]; 9524 9525 u8 static_rate[0x4]; 9526 u8 sl_eth_prio[0x4]; 9527 u8 fl[0x1]; 9528 u8 mlid[0x7]; 9529 u8 rlid_udp_sport[0x10]; 9530 9531 u8 reserved_at_80[0x20]; 9532 9533 u8 rmac_47_16[0x20]; 9534 9535 u8 rmac_15_0[0x10]; 9536 u8 tclass[0x8]; 9537 u8 hop_limit[0x8]; 9538 9539 u8 reserved_at_e0[0x1]; 9540 u8 grh[0x1]; 9541 u8 reserved_at_e2[0x2]; 9542 u8 src_addr_index[0x8]; 9543 u8 flow_label[0x14]; 9544 9545 u8 rgid_rip[16][0x8]; 9546 }; 9547 9548 struct mlx5_ifc_pages_req_event_bits { 9549 u8 reserved_at_0[0x10]; 9550 u8 function_id[0x10]; 9551 9552 u8 num_pages[0x20]; 9553 9554 u8 reserved_at_40[0xa0]; 9555 }; 9556 9557 struct mlx5_ifc_eqe_bits { 9558 u8 reserved_at_0[0x8]; 9559 u8 event_type[0x8]; 9560 u8 reserved_at_10[0x8]; 9561 u8 event_sub_type[0x8]; 9562 9563 u8 reserved_at_20[0xe0]; 9564 9565 union mlx5_ifc_event_auto_bits event_data; 9566 9567 u8 reserved_at_1e0[0x10]; 9568 u8 signature[0x8]; 9569 u8 reserved_at_1f8[0x7]; 9570 u8 owner[0x1]; 9571 }; 9572 9573 enum { 9574 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7, 9575 }; 9576 9577 struct mlx5_ifc_cmd_queue_entry_bits { 9578 u8 type[0x8]; 9579 u8 reserved_at_8[0x18]; 9580 9581 u8 input_length[0x20]; 9582 9583 u8 input_mailbox_pointer_63_32[0x20]; 9584 9585 u8 input_mailbox_pointer_31_9[0x17]; 9586 u8 reserved_at_77[0x9]; 9587 9588 u8 command_input_inline_data[16][0x8]; 9589 9590 u8 command_output_inline_data[16][0x8]; 9591 9592 u8 output_mailbox_pointer_63_32[0x20]; 9593 9594 u8 output_mailbox_pointer_31_9[0x17]; 9595 u8 reserved_at_1b7[0x9]; 9596 9597 u8 output_length[0x20]; 9598 9599 u8 token[0x8]; 9600 u8 signature[0x8]; 9601 u8 reserved_at_1f0[0x8]; 9602 u8 status[0x7]; 9603 u8 ownership[0x1]; 9604 }; 9605 9606 struct mlx5_ifc_cmd_out_bits { 9607 u8 status[0x8]; 9608 u8 reserved_at_8[0x18]; 9609 9610 u8 syndrome[0x20]; 9611 9612 u8 command_output[0x20]; 9613 }; 9614 9615 struct mlx5_ifc_cmd_in_bits { 9616 u8 opcode[0x10]; 9617 u8 reserved_at_10[0x10]; 9618 9619 u8 reserved_at_20[0x10]; 9620 u8 op_mod[0x10]; 9621 9622 u8 command[][0x20]; 9623 }; 9624 9625 struct mlx5_ifc_cmd_if_box_bits { 9626 u8 mailbox_data[512][0x8]; 9627 9628 u8 reserved_at_1000[0x180]; 9629 9630 u8 next_pointer_63_32[0x20]; 9631 9632 u8 next_pointer_31_10[0x16]; 9633 u8 reserved_at_11b6[0xa]; 9634 9635 u8 block_number[0x20]; 9636 9637 u8 reserved_at_11e0[0x8]; 9638 u8 token[0x8]; 9639 u8 ctrl_signature[0x8]; 9640 u8 signature[0x8]; 9641 }; 9642 9643 struct mlx5_ifc_mtt_bits { 9644 u8 ptag_63_32[0x20]; 9645 9646 u8 ptag_31_8[0x18]; 9647 u8 reserved_at_38[0x6]; 9648 u8 wr_en[0x1]; 9649 u8 rd_en[0x1]; 9650 }; 9651 9652 struct mlx5_ifc_query_wol_rol_out_bits { 9653 u8 status[0x8]; 9654 u8 reserved_at_8[0x18]; 9655 9656 u8 syndrome[0x20]; 9657 9658 u8 reserved_at_40[0x10]; 9659 u8 rol_mode[0x8]; 9660 u8 wol_mode[0x8]; 9661 9662 u8 reserved_at_60[0x20]; 9663 }; 9664 9665 struct mlx5_ifc_query_wol_rol_in_bits { 9666 u8 opcode[0x10]; 9667 u8 reserved_at_10[0x10]; 9668 9669 u8 reserved_at_20[0x10]; 9670 u8 op_mod[0x10]; 9671 9672 u8 reserved_at_40[0x40]; 9673 }; 9674 9675 struct mlx5_ifc_set_wol_rol_out_bits { 9676 u8 status[0x8]; 9677 u8 reserved_at_8[0x18]; 9678 9679 u8 syndrome[0x20]; 9680 9681 u8 reserved_at_40[0x40]; 9682 }; 9683 9684 struct mlx5_ifc_set_wol_rol_in_bits { 9685 u8 opcode[0x10]; 9686 u8 reserved_at_10[0x10]; 9687 9688 u8 reserved_at_20[0x10]; 9689 u8 op_mod[0x10]; 9690 9691 u8 rol_mode_valid[0x1]; 9692 u8 wol_mode_valid[0x1]; 9693 u8 reserved_at_42[0xe]; 9694 u8 rol_mode[0x8]; 9695 u8 wol_mode[0x8]; 9696 9697 u8 reserved_at_60[0x20]; 9698 }; 9699 9700 enum { 9701 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0, 9702 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1, 9703 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2, 9704 }; 9705 9706 enum { 9707 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0, 9708 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1, 9709 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2, 9710 }; 9711 9712 enum { 9713 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR = 0x1, 9714 MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC = 0x7, 9715 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR = 0x8, 9716 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR = 0x9, 9717 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR = 0xa, 9718 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR = 0xb, 9719 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN = 0xc, 9720 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR = 0xd, 9721 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV = 0xe, 9722 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR = 0xf, 9723 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR = 0x10, 9724 }; 9725 9726 struct mlx5_ifc_initial_seg_bits { 9727 u8 fw_rev_minor[0x10]; 9728 u8 fw_rev_major[0x10]; 9729 9730 u8 cmd_interface_rev[0x10]; 9731 u8 fw_rev_subminor[0x10]; 9732 9733 u8 reserved_at_40[0x40]; 9734 9735 u8 cmdq_phy_addr_63_32[0x20]; 9736 9737 u8 cmdq_phy_addr_31_12[0x14]; 9738 u8 reserved_at_b4[0x2]; 9739 u8 nic_interface[0x2]; 9740 u8 log_cmdq_size[0x4]; 9741 u8 log_cmdq_stride[0x4]; 9742 9743 u8 command_doorbell_vector[0x20]; 9744 9745 u8 reserved_at_e0[0xf00]; 9746 9747 u8 initializing[0x1]; 9748 u8 reserved_at_fe1[0x4]; 9749 u8 nic_interface_supported[0x3]; 9750 u8 embedded_cpu[0x1]; 9751 u8 reserved_at_fe9[0x17]; 9752 9753 struct mlx5_ifc_health_buffer_bits health_buffer; 9754 9755 u8 no_dram_nic_offset[0x20]; 9756 9757 u8 reserved_at_1220[0x6e40]; 9758 9759 u8 reserved_at_8060[0x1f]; 9760 u8 clear_int[0x1]; 9761 9762 u8 health_syndrome[0x8]; 9763 u8 health_counter[0x18]; 9764 9765 u8 reserved_at_80a0[0x17fc0]; 9766 }; 9767 9768 struct mlx5_ifc_mtpps_reg_bits { 9769 u8 reserved_at_0[0xc]; 9770 u8 cap_number_of_pps_pins[0x4]; 9771 u8 reserved_at_10[0x4]; 9772 u8 cap_max_num_of_pps_in_pins[0x4]; 9773 u8 reserved_at_18[0x4]; 9774 u8 cap_max_num_of_pps_out_pins[0x4]; 9775 9776 u8 reserved_at_20[0x24]; 9777 u8 cap_pin_3_mode[0x4]; 9778 u8 reserved_at_48[0x4]; 9779 u8 cap_pin_2_mode[0x4]; 9780 u8 reserved_at_50[0x4]; 9781 u8 cap_pin_1_mode[0x4]; 9782 u8 reserved_at_58[0x4]; 9783 u8 cap_pin_0_mode[0x4]; 9784 9785 u8 reserved_at_60[0x4]; 9786 u8 cap_pin_7_mode[0x4]; 9787 u8 reserved_at_68[0x4]; 9788 u8 cap_pin_6_mode[0x4]; 9789 u8 reserved_at_70[0x4]; 9790 u8 cap_pin_5_mode[0x4]; 9791 u8 reserved_at_78[0x4]; 9792 u8 cap_pin_4_mode[0x4]; 9793 9794 u8 field_select[0x20]; 9795 u8 reserved_at_a0[0x60]; 9796 9797 u8 enable[0x1]; 9798 u8 reserved_at_101[0xb]; 9799 u8 pattern[0x4]; 9800 u8 reserved_at_110[0x4]; 9801 u8 pin_mode[0x4]; 9802 u8 pin[0x8]; 9803 9804 u8 reserved_at_120[0x20]; 9805 9806 u8 time_stamp[0x40]; 9807 9808 u8 out_pulse_duration[0x10]; 9809 u8 out_periodic_adjustment[0x10]; 9810 u8 enhanced_out_periodic_adjustment[0x20]; 9811 9812 u8 reserved_at_1c0[0x20]; 9813 }; 9814 9815 struct mlx5_ifc_mtppse_reg_bits { 9816 u8 reserved_at_0[0x18]; 9817 u8 pin[0x8]; 9818 u8 event_arm[0x1]; 9819 u8 reserved_at_21[0x1b]; 9820 u8 event_generation_mode[0x4]; 9821 u8 reserved_at_40[0x40]; 9822 }; 9823 9824 struct mlx5_ifc_mcqs_reg_bits { 9825 u8 last_index_flag[0x1]; 9826 u8 reserved_at_1[0x7]; 9827 u8 fw_device[0x8]; 9828 u8 component_index[0x10]; 9829 9830 u8 reserved_at_20[0x10]; 9831 u8 identifier[0x10]; 9832 9833 u8 reserved_at_40[0x17]; 9834 u8 component_status[0x5]; 9835 u8 component_update_state[0x4]; 9836 9837 u8 last_update_state_changer_type[0x4]; 9838 u8 last_update_state_changer_host_id[0x4]; 9839 u8 reserved_at_68[0x18]; 9840 }; 9841 9842 struct mlx5_ifc_mcqi_cap_bits { 9843 u8 supported_info_bitmask[0x20]; 9844 9845 u8 component_size[0x20]; 9846 9847 u8 max_component_size[0x20]; 9848 9849 u8 log_mcda_word_size[0x4]; 9850 u8 reserved_at_64[0xc]; 9851 u8 mcda_max_write_size[0x10]; 9852 9853 u8 rd_en[0x1]; 9854 u8 reserved_at_81[0x1]; 9855 u8 match_chip_id[0x1]; 9856 u8 match_psid[0x1]; 9857 u8 check_user_timestamp[0x1]; 9858 u8 match_base_guid_mac[0x1]; 9859 u8 reserved_at_86[0x1a]; 9860 }; 9861 9862 struct mlx5_ifc_mcqi_version_bits { 9863 u8 reserved_at_0[0x2]; 9864 u8 build_time_valid[0x1]; 9865 u8 user_defined_time_valid[0x1]; 9866 u8 reserved_at_4[0x14]; 9867 u8 version_string_length[0x8]; 9868 9869 u8 version[0x20]; 9870 9871 u8 build_time[0x40]; 9872 9873 u8 user_defined_time[0x40]; 9874 9875 u8 build_tool_version[0x20]; 9876 9877 u8 reserved_at_e0[0x20]; 9878 9879 u8 version_string[92][0x8]; 9880 }; 9881 9882 struct mlx5_ifc_mcqi_activation_method_bits { 9883 u8 pending_server_ac_power_cycle[0x1]; 9884 u8 pending_server_dc_power_cycle[0x1]; 9885 u8 pending_server_reboot[0x1]; 9886 u8 pending_fw_reset[0x1]; 9887 u8 auto_activate[0x1]; 9888 u8 all_hosts_sync[0x1]; 9889 u8 device_hw_reset[0x1]; 9890 u8 reserved_at_7[0x19]; 9891 }; 9892 9893 union mlx5_ifc_mcqi_reg_data_bits { 9894 struct mlx5_ifc_mcqi_cap_bits mcqi_caps; 9895 struct mlx5_ifc_mcqi_version_bits mcqi_version; 9896 struct mlx5_ifc_mcqi_activation_method_bits mcqi_activation_mathod; 9897 }; 9898 9899 struct mlx5_ifc_mcqi_reg_bits { 9900 u8 read_pending_component[0x1]; 9901 u8 reserved_at_1[0xf]; 9902 u8 component_index[0x10]; 9903 9904 u8 reserved_at_20[0x20]; 9905 9906 u8 reserved_at_40[0x1b]; 9907 u8 info_type[0x5]; 9908 9909 u8 info_size[0x20]; 9910 9911 u8 offset[0x20]; 9912 9913 u8 reserved_at_a0[0x10]; 9914 u8 data_size[0x10]; 9915 9916 union mlx5_ifc_mcqi_reg_data_bits data[]; 9917 }; 9918 9919 struct mlx5_ifc_mcc_reg_bits { 9920 u8 reserved_at_0[0x4]; 9921 u8 time_elapsed_since_last_cmd[0xc]; 9922 u8 reserved_at_10[0x8]; 9923 u8 instruction[0x8]; 9924 9925 u8 reserved_at_20[0x10]; 9926 u8 component_index[0x10]; 9927 9928 u8 reserved_at_40[0x8]; 9929 u8 update_handle[0x18]; 9930 9931 u8 handle_owner_type[0x4]; 9932 u8 handle_owner_host_id[0x4]; 9933 u8 reserved_at_68[0x1]; 9934 u8 control_progress[0x7]; 9935 u8 error_code[0x8]; 9936 u8 reserved_at_78[0x4]; 9937 u8 control_state[0x4]; 9938 9939 u8 component_size[0x20]; 9940 9941 u8 reserved_at_a0[0x60]; 9942 }; 9943 9944 struct mlx5_ifc_mcda_reg_bits { 9945 u8 reserved_at_0[0x8]; 9946 u8 update_handle[0x18]; 9947 9948 u8 offset[0x20]; 9949 9950 u8 reserved_at_40[0x10]; 9951 u8 size[0x10]; 9952 9953 u8 reserved_at_60[0x20]; 9954 9955 u8 data[][0x20]; 9956 }; 9957 9958 enum { 9959 MLX5_MFRL_REG_RESET_TYPE_FULL_CHIP = BIT(0), 9960 MLX5_MFRL_REG_RESET_TYPE_NET_PORT_ALIVE = BIT(1), 9961 }; 9962 9963 enum { 9964 MLX5_MFRL_REG_RESET_LEVEL0 = BIT(0), 9965 MLX5_MFRL_REG_RESET_LEVEL3 = BIT(3), 9966 MLX5_MFRL_REG_RESET_LEVEL6 = BIT(6), 9967 }; 9968 9969 struct mlx5_ifc_mfrl_reg_bits { 9970 u8 reserved_at_0[0x20]; 9971 9972 u8 reserved_at_20[0x2]; 9973 u8 pci_sync_for_fw_update_start[0x1]; 9974 u8 pci_sync_for_fw_update_resp[0x2]; 9975 u8 rst_type_sel[0x3]; 9976 u8 reserved_at_28[0x8]; 9977 u8 reset_type[0x8]; 9978 u8 reset_level[0x8]; 9979 }; 9980 9981 struct mlx5_ifc_mirc_reg_bits { 9982 u8 reserved_at_0[0x18]; 9983 u8 status_code[0x8]; 9984 9985 u8 reserved_at_20[0x20]; 9986 }; 9987 9988 struct mlx5_ifc_pddr_monitor_opcode_bits { 9989 u8 reserved_at_0[0x10]; 9990 u8 monitor_opcode[0x10]; 9991 }; 9992 9993 union mlx5_ifc_pddr_troubleshooting_page_status_opcode_auto_bits { 9994 struct mlx5_ifc_pddr_monitor_opcode_bits pddr_monitor_opcode; 9995 u8 reserved_at_0[0x20]; 9996 }; 9997 9998 enum { 9999 /* Monitor opcodes */ 10000 MLX5_PDDR_REG_TRBLSH_GROUP_OPCODE_MONITOR = 0x0, 10001 }; 10002 10003 struct mlx5_ifc_pddr_troubleshooting_page_bits { 10004 u8 reserved_at_0[0x10]; 10005 u8 group_opcode[0x10]; 10006 10007 union mlx5_ifc_pddr_troubleshooting_page_status_opcode_auto_bits status_opcode; 10008 10009 u8 reserved_at_40[0x20]; 10010 10011 u8 status_message[59][0x20]; 10012 }; 10013 10014 union mlx5_ifc_pddr_reg_page_data_auto_bits { 10015 struct mlx5_ifc_pddr_troubleshooting_page_bits pddr_troubleshooting_page; 10016 u8 reserved_at_0[0x7c0]; 10017 }; 10018 10019 enum { 10020 MLX5_PDDR_REG_PAGE_SELECT_TROUBLESHOOTING_INFO_PAGE = 0x1, 10021 }; 10022 10023 struct mlx5_ifc_pddr_reg_bits { 10024 u8 reserved_at_0[0x8]; 10025 u8 local_port[0x8]; 10026 u8 pnat[0x2]; 10027 u8 reserved_at_12[0xe]; 10028 10029 u8 reserved_at_20[0x18]; 10030 u8 page_select[0x8]; 10031 10032 union mlx5_ifc_pddr_reg_page_data_auto_bits page_data; 10033 }; 10034 10035 union mlx5_ifc_ports_control_registers_document_bits { 10036 struct mlx5_ifc_bufferx_reg_bits bufferx_reg; 10037 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 10038 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 10039 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 10040 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 10041 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 10042 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 10043 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout; 10044 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout; 10045 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping; 10046 struct mlx5_ifc_pamp_reg_bits pamp_reg; 10047 struct mlx5_ifc_paos_reg_bits paos_reg; 10048 struct mlx5_ifc_pcap_reg_bits pcap_reg; 10049 struct mlx5_ifc_pddr_monitor_opcode_bits pddr_monitor_opcode; 10050 struct mlx5_ifc_pddr_reg_bits pddr_reg; 10051 struct mlx5_ifc_pddr_troubleshooting_page_bits pddr_troubleshooting_page; 10052 struct mlx5_ifc_peir_reg_bits peir_reg; 10053 struct mlx5_ifc_pelc_reg_bits pelc_reg; 10054 struct mlx5_ifc_pfcc_reg_bits pfcc_reg; 10055 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 10056 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 10057 struct mlx5_ifc_pifr_reg_bits pifr_reg; 10058 struct mlx5_ifc_pipg_reg_bits pipg_reg; 10059 struct mlx5_ifc_plbf_reg_bits plbf_reg; 10060 struct mlx5_ifc_plib_reg_bits plib_reg; 10061 struct mlx5_ifc_plpc_reg_bits plpc_reg; 10062 struct mlx5_ifc_pmaos_reg_bits pmaos_reg; 10063 struct mlx5_ifc_pmlp_reg_bits pmlp_reg; 10064 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg; 10065 struct mlx5_ifc_pmpc_reg_bits pmpc_reg; 10066 struct mlx5_ifc_pmpe_reg_bits pmpe_reg; 10067 struct mlx5_ifc_pmpr_reg_bits pmpr_reg; 10068 struct mlx5_ifc_pmtu_reg_bits pmtu_reg; 10069 struct mlx5_ifc_ppad_reg_bits ppad_reg; 10070 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg; 10071 struct mlx5_ifc_mpein_reg_bits mpein_reg; 10072 struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg; 10073 struct mlx5_ifc_pplm_reg_bits pplm_reg; 10074 struct mlx5_ifc_pplr_reg_bits pplr_reg; 10075 struct mlx5_ifc_ppsc_reg_bits ppsc_reg; 10076 struct mlx5_ifc_pqdr_reg_bits pqdr_reg; 10077 struct mlx5_ifc_pspa_reg_bits pspa_reg; 10078 struct mlx5_ifc_ptas_reg_bits ptas_reg; 10079 struct mlx5_ifc_ptys_reg_bits ptys_reg; 10080 struct mlx5_ifc_mlcr_reg_bits mlcr_reg; 10081 struct mlx5_ifc_pude_reg_bits pude_reg; 10082 struct mlx5_ifc_pvlc_reg_bits pvlc_reg; 10083 struct mlx5_ifc_slrg_reg_bits slrg_reg; 10084 struct mlx5_ifc_sltp_reg_bits sltp_reg; 10085 struct mlx5_ifc_mtpps_reg_bits mtpps_reg; 10086 struct mlx5_ifc_mtppse_reg_bits mtppse_reg; 10087 struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg; 10088 struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits; 10089 struct mlx5_ifc_fpga_cap_bits fpga_cap_bits; 10090 struct mlx5_ifc_mcqi_reg_bits mcqi_reg; 10091 struct mlx5_ifc_mcc_reg_bits mcc_reg; 10092 struct mlx5_ifc_mcda_reg_bits mcda_reg; 10093 struct mlx5_ifc_mirc_reg_bits mirc_reg; 10094 struct mlx5_ifc_mfrl_reg_bits mfrl_reg; 10095 struct mlx5_ifc_mtutc_reg_bits mtutc_reg; 10096 u8 reserved_at_0[0x60e0]; 10097 }; 10098 10099 union mlx5_ifc_debug_enhancements_document_bits { 10100 struct mlx5_ifc_health_buffer_bits health_buffer; 10101 u8 reserved_at_0[0x200]; 10102 }; 10103 10104 union mlx5_ifc_uplink_pci_interface_document_bits { 10105 struct mlx5_ifc_initial_seg_bits initial_seg; 10106 u8 reserved_at_0[0x20060]; 10107 }; 10108 10109 struct mlx5_ifc_set_flow_table_root_out_bits { 10110 u8 status[0x8]; 10111 u8 reserved_at_8[0x18]; 10112 10113 u8 syndrome[0x20]; 10114 10115 u8 reserved_at_40[0x40]; 10116 }; 10117 10118 struct mlx5_ifc_set_flow_table_root_in_bits { 10119 u8 opcode[0x10]; 10120 u8 reserved_at_10[0x10]; 10121 10122 u8 reserved_at_20[0x10]; 10123 u8 op_mod[0x10]; 10124 10125 u8 other_vport[0x1]; 10126 u8 reserved_at_41[0xf]; 10127 u8 vport_number[0x10]; 10128 10129 u8 reserved_at_60[0x20]; 10130 10131 u8 table_type[0x8]; 10132 u8 reserved_at_88[0x7]; 10133 u8 table_of_other_vport[0x1]; 10134 u8 table_vport_number[0x10]; 10135 10136 u8 reserved_at_a0[0x8]; 10137 u8 table_id[0x18]; 10138 10139 u8 reserved_at_c0[0x8]; 10140 u8 underlay_qpn[0x18]; 10141 u8 table_eswitch_owner_vhca_id_valid[0x1]; 10142 u8 reserved_at_e1[0xf]; 10143 u8 table_eswitch_owner_vhca_id[0x10]; 10144 u8 reserved_at_100[0x100]; 10145 }; 10146 10147 enum { 10148 MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = (1UL << 0), 10149 MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15), 10150 }; 10151 10152 struct mlx5_ifc_modify_flow_table_out_bits { 10153 u8 status[0x8]; 10154 u8 reserved_at_8[0x18]; 10155 10156 u8 syndrome[0x20]; 10157 10158 u8 reserved_at_40[0x40]; 10159 }; 10160 10161 struct mlx5_ifc_modify_flow_table_in_bits { 10162 u8 opcode[0x10]; 10163 u8 reserved_at_10[0x10]; 10164 10165 u8 reserved_at_20[0x10]; 10166 u8 op_mod[0x10]; 10167 10168 u8 other_vport[0x1]; 10169 u8 reserved_at_41[0xf]; 10170 u8 vport_number[0x10]; 10171 10172 u8 reserved_at_60[0x10]; 10173 u8 modify_field_select[0x10]; 10174 10175 u8 table_type[0x8]; 10176 u8 reserved_at_88[0x18]; 10177 10178 u8 reserved_at_a0[0x8]; 10179 u8 table_id[0x18]; 10180 10181 struct mlx5_ifc_flow_table_context_bits flow_table_context; 10182 }; 10183 10184 struct mlx5_ifc_ets_tcn_config_reg_bits { 10185 u8 g[0x1]; 10186 u8 b[0x1]; 10187 u8 r[0x1]; 10188 u8 reserved_at_3[0x9]; 10189 u8 group[0x4]; 10190 u8 reserved_at_10[0x9]; 10191 u8 bw_allocation[0x7]; 10192 10193 u8 reserved_at_20[0xc]; 10194 u8 max_bw_units[0x4]; 10195 u8 reserved_at_30[0x8]; 10196 u8 max_bw_value[0x8]; 10197 }; 10198 10199 struct mlx5_ifc_ets_global_config_reg_bits { 10200 u8 reserved_at_0[0x2]; 10201 u8 r[0x1]; 10202 u8 reserved_at_3[0x1d]; 10203 10204 u8 reserved_at_20[0xc]; 10205 u8 max_bw_units[0x4]; 10206 u8 reserved_at_30[0x8]; 10207 u8 max_bw_value[0x8]; 10208 }; 10209 10210 struct mlx5_ifc_qetc_reg_bits { 10211 u8 reserved_at_0[0x8]; 10212 u8 port_number[0x8]; 10213 u8 reserved_at_10[0x30]; 10214 10215 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8]; 10216 struct mlx5_ifc_ets_global_config_reg_bits global_configuration; 10217 }; 10218 10219 struct mlx5_ifc_qpdpm_dscp_reg_bits { 10220 u8 e[0x1]; 10221 u8 reserved_at_01[0x0b]; 10222 u8 prio[0x04]; 10223 }; 10224 10225 struct mlx5_ifc_qpdpm_reg_bits { 10226 u8 reserved_at_0[0x8]; 10227 u8 local_port[0x8]; 10228 u8 reserved_at_10[0x10]; 10229 struct mlx5_ifc_qpdpm_dscp_reg_bits dscp[64]; 10230 }; 10231 10232 struct mlx5_ifc_qpts_reg_bits { 10233 u8 reserved_at_0[0x8]; 10234 u8 local_port[0x8]; 10235 u8 reserved_at_10[0x2d]; 10236 u8 trust_state[0x3]; 10237 }; 10238 10239 struct mlx5_ifc_pptb_reg_bits { 10240 u8 reserved_at_0[0x2]; 10241 u8 mm[0x2]; 10242 u8 reserved_at_4[0x4]; 10243 u8 local_port[0x8]; 10244 u8 reserved_at_10[0x6]; 10245 u8 cm[0x1]; 10246 u8 um[0x1]; 10247 u8 pm[0x8]; 10248 10249 u8 prio_x_buff[0x20]; 10250 10251 u8 pm_msb[0x8]; 10252 u8 reserved_at_48[0x10]; 10253 u8 ctrl_buff[0x4]; 10254 u8 untagged_buff[0x4]; 10255 }; 10256 10257 struct mlx5_ifc_sbcam_reg_bits { 10258 u8 reserved_at_0[0x8]; 10259 u8 feature_group[0x8]; 10260 u8 reserved_at_10[0x8]; 10261 u8 access_reg_group[0x8]; 10262 10263 u8 reserved_at_20[0x20]; 10264 10265 u8 sb_access_reg_cap_mask[4][0x20]; 10266 10267 u8 reserved_at_c0[0x80]; 10268 10269 u8 sb_feature_cap_mask[4][0x20]; 10270 10271 u8 reserved_at_1c0[0x40]; 10272 10273 u8 cap_total_buffer_size[0x20]; 10274 10275 u8 cap_cell_size[0x10]; 10276 u8 cap_max_pg_buffers[0x8]; 10277 u8 cap_num_pool_supported[0x8]; 10278 10279 u8 reserved_at_240[0x8]; 10280 u8 cap_sbsr_stat_size[0x8]; 10281 u8 cap_max_tclass_data[0x8]; 10282 u8 cap_max_cpu_ingress_tclass_sb[0x8]; 10283 }; 10284 10285 struct mlx5_ifc_pbmc_reg_bits { 10286 u8 reserved_at_0[0x8]; 10287 u8 local_port[0x8]; 10288 u8 reserved_at_10[0x10]; 10289 10290 u8 xoff_timer_value[0x10]; 10291 u8 xoff_refresh[0x10]; 10292 10293 u8 reserved_at_40[0x9]; 10294 u8 fullness_threshold[0x7]; 10295 u8 port_buffer_size[0x10]; 10296 10297 struct mlx5_ifc_bufferx_reg_bits buffer[10]; 10298 10299 u8 reserved_at_2e0[0x80]; 10300 }; 10301 10302 struct mlx5_ifc_qtct_reg_bits { 10303 u8 reserved_at_0[0x8]; 10304 u8 port_number[0x8]; 10305 u8 reserved_at_10[0xd]; 10306 u8 prio[0x3]; 10307 10308 u8 reserved_at_20[0x1d]; 10309 u8 tclass[0x3]; 10310 }; 10311 10312 struct mlx5_ifc_mcia_reg_bits { 10313 u8 l[0x1]; 10314 u8 reserved_at_1[0x7]; 10315 u8 module[0x8]; 10316 u8 reserved_at_10[0x8]; 10317 u8 status[0x8]; 10318 10319 u8 i2c_device_address[0x8]; 10320 u8 page_number[0x8]; 10321 u8 device_address[0x10]; 10322 10323 u8 reserved_at_40[0x10]; 10324 u8 size[0x10]; 10325 10326 u8 reserved_at_60[0x20]; 10327 10328 u8 dword_0[0x20]; 10329 u8 dword_1[0x20]; 10330 u8 dword_2[0x20]; 10331 u8 dword_3[0x20]; 10332 u8 dword_4[0x20]; 10333 u8 dword_5[0x20]; 10334 u8 dword_6[0x20]; 10335 u8 dword_7[0x20]; 10336 u8 dword_8[0x20]; 10337 u8 dword_9[0x20]; 10338 u8 dword_10[0x20]; 10339 u8 dword_11[0x20]; 10340 }; 10341 10342 struct mlx5_ifc_dcbx_param_bits { 10343 u8 dcbx_cee_cap[0x1]; 10344 u8 dcbx_ieee_cap[0x1]; 10345 u8 dcbx_standby_cap[0x1]; 10346 u8 reserved_at_3[0x5]; 10347 u8 port_number[0x8]; 10348 u8 reserved_at_10[0xa]; 10349 u8 max_application_table_size[6]; 10350 u8 reserved_at_20[0x15]; 10351 u8 version_oper[0x3]; 10352 u8 reserved_at_38[5]; 10353 u8 version_admin[0x3]; 10354 u8 willing_admin[0x1]; 10355 u8 reserved_at_41[0x3]; 10356 u8 pfc_cap_oper[0x4]; 10357 u8 reserved_at_48[0x4]; 10358 u8 pfc_cap_admin[0x4]; 10359 u8 reserved_at_50[0x4]; 10360 u8 num_of_tc_oper[0x4]; 10361 u8 reserved_at_58[0x4]; 10362 u8 num_of_tc_admin[0x4]; 10363 u8 remote_willing[0x1]; 10364 u8 reserved_at_61[3]; 10365 u8 remote_pfc_cap[4]; 10366 u8 reserved_at_68[0x14]; 10367 u8 remote_num_of_tc[0x4]; 10368 u8 reserved_at_80[0x18]; 10369 u8 error[0x8]; 10370 u8 reserved_at_a0[0x160]; 10371 }; 10372 10373 struct mlx5_ifc_lagc_bits { 10374 u8 fdb_selection_mode[0x1]; 10375 u8 reserved_at_1[0x1c]; 10376 u8 lag_state[0x3]; 10377 10378 u8 reserved_at_20[0x14]; 10379 u8 tx_remap_affinity_2[0x4]; 10380 u8 reserved_at_38[0x4]; 10381 u8 tx_remap_affinity_1[0x4]; 10382 }; 10383 10384 struct mlx5_ifc_create_lag_out_bits { 10385 u8 status[0x8]; 10386 u8 reserved_at_8[0x18]; 10387 10388 u8 syndrome[0x20]; 10389 10390 u8 reserved_at_40[0x40]; 10391 }; 10392 10393 struct mlx5_ifc_create_lag_in_bits { 10394 u8 opcode[0x10]; 10395 u8 reserved_at_10[0x10]; 10396 10397 u8 reserved_at_20[0x10]; 10398 u8 op_mod[0x10]; 10399 10400 struct mlx5_ifc_lagc_bits ctx; 10401 }; 10402 10403 struct mlx5_ifc_modify_lag_out_bits { 10404 u8 status[0x8]; 10405 u8 reserved_at_8[0x18]; 10406 10407 u8 syndrome[0x20]; 10408 10409 u8 reserved_at_40[0x40]; 10410 }; 10411 10412 struct mlx5_ifc_modify_lag_in_bits { 10413 u8 opcode[0x10]; 10414 u8 reserved_at_10[0x10]; 10415 10416 u8 reserved_at_20[0x10]; 10417 u8 op_mod[0x10]; 10418 10419 u8 reserved_at_40[0x20]; 10420 u8 field_select[0x20]; 10421 10422 struct mlx5_ifc_lagc_bits ctx; 10423 }; 10424 10425 struct mlx5_ifc_query_lag_out_bits { 10426 u8 status[0x8]; 10427 u8 reserved_at_8[0x18]; 10428 10429 u8 syndrome[0x20]; 10430 10431 struct mlx5_ifc_lagc_bits ctx; 10432 }; 10433 10434 struct mlx5_ifc_query_lag_in_bits { 10435 u8 opcode[0x10]; 10436 u8 reserved_at_10[0x10]; 10437 10438 u8 reserved_at_20[0x10]; 10439 u8 op_mod[0x10]; 10440 10441 u8 reserved_at_40[0x40]; 10442 }; 10443 10444 struct mlx5_ifc_destroy_lag_out_bits { 10445 u8 status[0x8]; 10446 u8 reserved_at_8[0x18]; 10447 10448 u8 syndrome[0x20]; 10449 10450 u8 reserved_at_40[0x40]; 10451 }; 10452 10453 struct mlx5_ifc_destroy_lag_in_bits { 10454 u8 opcode[0x10]; 10455 u8 reserved_at_10[0x10]; 10456 10457 u8 reserved_at_20[0x10]; 10458 u8 op_mod[0x10]; 10459 10460 u8 reserved_at_40[0x40]; 10461 }; 10462 10463 struct mlx5_ifc_create_vport_lag_out_bits { 10464 u8 status[0x8]; 10465 u8 reserved_at_8[0x18]; 10466 10467 u8 syndrome[0x20]; 10468 10469 u8 reserved_at_40[0x40]; 10470 }; 10471 10472 struct mlx5_ifc_create_vport_lag_in_bits { 10473 u8 opcode[0x10]; 10474 u8 reserved_at_10[0x10]; 10475 10476 u8 reserved_at_20[0x10]; 10477 u8 op_mod[0x10]; 10478 10479 u8 reserved_at_40[0x40]; 10480 }; 10481 10482 struct mlx5_ifc_destroy_vport_lag_out_bits { 10483 u8 status[0x8]; 10484 u8 reserved_at_8[0x18]; 10485 10486 u8 syndrome[0x20]; 10487 10488 u8 reserved_at_40[0x40]; 10489 }; 10490 10491 struct mlx5_ifc_destroy_vport_lag_in_bits { 10492 u8 opcode[0x10]; 10493 u8 reserved_at_10[0x10]; 10494 10495 u8 reserved_at_20[0x10]; 10496 u8 op_mod[0x10]; 10497 10498 u8 reserved_at_40[0x40]; 10499 }; 10500 10501 struct mlx5_ifc_alloc_memic_in_bits { 10502 u8 opcode[0x10]; 10503 u8 reserved_at_10[0x10]; 10504 10505 u8 reserved_at_20[0x10]; 10506 u8 op_mod[0x10]; 10507 10508 u8 reserved_at_30[0x20]; 10509 10510 u8 reserved_at_40[0x18]; 10511 u8 log_memic_addr_alignment[0x8]; 10512 10513 u8 range_start_addr[0x40]; 10514 10515 u8 range_size[0x20]; 10516 10517 u8 memic_size[0x20]; 10518 }; 10519 10520 struct mlx5_ifc_alloc_memic_out_bits { 10521 u8 status[0x8]; 10522 u8 reserved_at_8[0x18]; 10523 10524 u8 syndrome[0x20]; 10525 10526 u8 memic_start_addr[0x40]; 10527 }; 10528 10529 struct mlx5_ifc_dealloc_memic_in_bits { 10530 u8 opcode[0x10]; 10531 u8 reserved_at_10[0x10]; 10532 10533 u8 reserved_at_20[0x10]; 10534 u8 op_mod[0x10]; 10535 10536 u8 reserved_at_40[0x40]; 10537 10538 u8 memic_start_addr[0x40]; 10539 10540 u8 memic_size[0x20]; 10541 10542 u8 reserved_at_e0[0x20]; 10543 }; 10544 10545 struct mlx5_ifc_dealloc_memic_out_bits { 10546 u8 status[0x8]; 10547 u8 reserved_at_8[0x18]; 10548 10549 u8 syndrome[0x20]; 10550 10551 u8 reserved_at_40[0x40]; 10552 }; 10553 10554 struct mlx5_ifc_general_obj_in_cmd_hdr_bits { 10555 u8 opcode[0x10]; 10556 u8 uid[0x10]; 10557 10558 u8 vhca_tunnel_id[0x10]; 10559 u8 obj_type[0x10]; 10560 10561 u8 obj_id[0x20]; 10562 10563 u8 reserved_at_60[0x20]; 10564 }; 10565 10566 struct mlx5_ifc_general_obj_out_cmd_hdr_bits { 10567 u8 status[0x8]; 10568 u8 reserved_at_8[0x18]; 10569 10570 u8 syndrome[0x20]; 10571 10572 u8 obj_id[0x20]; 10573 10574 u8 reserved_at_60[0x20]; 10575 }; 10576 10577 struct mlx5_ifc_umem_bits { 10578 u8 reserved_at_0[0x80]; 10579 10580 u8 reserved_at_80[0x1b]; 10581 u8 log_page_size[0x5]; 10582 10583 u8 page_offset[0x20]; 10584 10585 u8 num_of_mtt[0x40]; 10586 10587 struct mlx5_ifc_mtt_bits mtt[]; 10588 }; 10589 10590 struct mlx5_ifc_uctx_bits { 10591 u8 cap[0x20]; 10592 10593 u8 reserved_at_20[0x160]; 10594 }; 10595 10596 struct mlx5_ifc_sw_icm_bits { 10597 u8 modify_field_select[0x40]; 10598 10599 u8 reserved_at_40[0x18]; 10600 u8 log_sw_icm_size[0x8]; 10601 10602 u8 reserved_at_60[0x20]; 10603 10604 u8 sw_icm_start_addr[0x40]; 10605 10606 u8 reserved_at_c0[0x140]; 10607 }; 10608 10609 struct mlx5_ifc_geneve_tlv_option_bits { 10610 u8 modify_field_select[0x40]; 10611 10612 u8 reserved_at_40[0x18]; 10613 u8 geneve_option_fte_index[0x8]; 10614 10615 u8 option_class[0x10]; 10616 u8 option_type[0x8]; 10617 u8 reserved_at_78[0x3]; 10618 u8 option_data_length[0x5]; 10619 10620 u8 reserved_at_80[0x180]; 10621 }; 10622 10623 struct mlx5_ifc_create_umem_in_bits { 10624 u8 opcode[0x10]; 10625 u8 uid[0x10]; 10626 10627 u8 reserved_at_20[0x10]; 10628 u8 op_mod[0x10]; 10629 10630 u8 reserved_at_40[0x40]; 10631 10632 struct mlx5_ifc_umem_bits umem; 10633 }; 10634 10635 struct mlx5_ifc_create_umem_out_bits { 10636 u8 status[0x8]; 10637 u8 reserved_at_8[0x18]; 10638 10639 u8 syndrome[0x20]; 10640 10641 u8 reserved_at_40[0x8]; 10642 u8 umem_id[0x18]; 10643 10644 u8 reserved_at_60[0x20]; 10645 }; 10646 10647 struct mlx5_ifc_destroy_umem_in_bits { 10648 u8 opcode[0x10]; 10649 u8 uid[0x10]; 10650 10651 u8 reserved_at_20[0x10]; 10652 u8 op_mod[0x10]; 10653 10654 u8 reserved_at_40[0x8]; 10655 u8 umem_id[0x18]; 10656 10657 u8 reserved_at_60[0x20]; 10658 }; 10659 10660 struct mlx5_ifc_destroy_umem_out_bits { 10661 u8 status[0x8]; 10662 u8 reserved_at_8[0x18]; 10663 10664 u8 syndrome[0x20]; 10665 10666 u8 reserved_at_40[0x40]; 10667 }; 10668 10669 struct mlx5_ifc_create_uctx_in_bits { 10670 u8 opcode[0x10]; 10671 u8 reserved_at_10[0x10]; 10672 10673 u8 reserved_at_20[0x10]; 10674 u8 op_mod[0x10]; 10675 10676 u8 reserved_at_40[0x40]; 10677 10678 struct mlx5_ifc_uctx_bits uctx; 10679 }; 10680 10681 struct mlx5_ifc_create_uctx_out_bits { 10682 u8 status[0x8]; 10683 u8 reserved_at_8[0x18]; 10684 10685 u8 syndrome[0x20]; 10686 10687 u8 reserved_at_40[0x10]; 10688 u8 uid[0x10]; 10689 10690 u8 reserved_at_60[0x20]; 10691 }; 10692 10693 struct mlx5_ifc_destroy_uctx_in_bits { 10694 u8 opcode[0x10]; 10695 u8 reserved_at_10[0x10]; 10696 10697 u8 reserved_at_20[0x10]; 10698 u8 op_mod[0x10]; 10699 10700 u8 reserved_at_40[0x10]; 10701 u8 uid[0x10]; 10702 10703 u8 reserved_at_60[0x20]; 10704 }; 10705 10706 struct mlx5_ifc_destroy_uctx_out_bits { 10707 u8 status[0x8]; 10708 u8 reserved_at_8[0x18]; 10709 10710 u8 syndrome[0x20]; 10711 10712 u8 reserved_at_40[0x40]; 10713 }; 10714 10715 struct mlx5_ifc_create_sw_icm_in_bits { 10716 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 10717 struct mlx5_ifc_sw_icm_bits sw_icm; 10718 }; 10719 10720 struct mlx5_ifc_create_geneve_tlv_option_in_bits { 10721 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 10722 struct mlx5_ifc_geneve_tlv_option_bits geneve_tlv_opt; 10723 }; 10724 10725 struct mlx5_ifc_mtrc_string_db_param_bits { 10726 u8 string_db_base_address[0x20]; 10727 10728 u8 reserved_at_20[0x8]; 10729 u8 string_db_size[0x18]; 10730 }; 10731 10732 struct mlx5_ifc_mtrc_cap_bits { 10733 u8 trace_owner[0x1]; 10734 u8 trace_to_memory[0x1]; 10735 u8 reserved_at_2[0x4]; 10736 u8 trc_ver[0x2]; 10737 u8 reserved_at_8[0x14]; 10738 u8 num_string_db[0x4]; 10739 10740 u8 first_string_trace[0x8]; 10741 u8 num_string_trace[0x8]; 10742 u8 reserved_at_30[0x28]; 10743 10744 u8 log_max_trace_buffer_size[0x8]; 10745 10746 u8 reserved_at_60[0x20]; 10747 10748 struct mlx5_ifc_mtrc_string_db_param_bits string_db_param[8]; 10749 10750 u8 reserved_at_280[0x180]; 10751 }; 10752 10753 struct mlx5_ifc_mtrc_conf_bits { 10754 u8 reserved_at_0[0x1c]; 10755 u8 trace_mode[0x4]; 10756 u8 reserved_at_20[0x18]; 10757 u8 log_trace_buffer_size[0x8]; 10758 u8 trace_mkey[0x20]; 10759 u8 reserved_at_60[0x3a0]; 10760 }; 10761 10762 struct mlx5_ifc_mtrc_stdb_bits { 10763 u8 string_db_index[0x4]; 10764 u8 reserved_at_4[0x4]; 10765 u8 read_size[0x18]; 10766 u8 start_offset[0x20]; 10767 u8 string_db_data[]; 10768 }; 10769 10770 struct mlx5_ifc_mtrc_ctrl_bits { 10771 u8 trace_status[0x2]; 10772 u8 reserved_at_2[0x2]; 10773 u8 arm_event[0x1]; 10774 u8 reserved_at_5[0xb]; 10775 u8 modify_field_select[0x10]; 10776 u8 reserved_at_20[0x2b]; 10777 u8 current_timestamp52_32[0x15]; 10778 u8 current_timestamp31_0[0x20]; 10779 u8 reserved_at_80[0x180]; 10780 }; 10781 10782 struct mlx5_ifc_host_params_context_bits { 10783 u8 host_number[0x8]; 10784 u8 reserved_at_8[0x7]; 10785 u8 host_pf_disabled[0x1]; 10786 u8 host_num_of_vfs[0x10]; 10787 10788 u8 host_total_vfs[0x10]; 10789 u8 host_pci_bus[0x10]; 10790 10791 u8 reserved_at_40[0x10]; 10792 u8 host_pci_device[0x10]; 10793 10794 u8 reserved_at_60[0x10]; 10795 u8 host_pci_function[0x10]; 10796 10797 u8 reserved_at_80[0x180]; 10798 }; 10799 10800 struct mlx5_ifc_query_esw_functions_in_bits { 10801 u8 opcode[0x10]; 10802 u8 reserved_at_10[0x10]; 10803 10804 u8 reserved_at_20[0x10]; 10805 u8 op_mod[0x10]; 10806 10807 u8 reserved_at_40[0x40]; 10808 }; 10809 10810 struct mlx5_ifc_query_esw_functions_out_bits { 10811 u8 status[0x8]; 10812 u8 reserved_at_8[0x18]; 10813 10814 u8 syndrome[0x20]; 10815 10816 u8 reserved_at_40[0x40]; 10817 10818 struct mlx5_ifc_host_params_context_bits host_params_context; 10819 10820 u8 reserved_at_280[0x180]; 10821 u8 host_sf_enable[][0x40]; 10822 }; 10823 10824 struct mlx5_ifc_sf_partition_bits { 10825 u8 reserved_at_0[0x10]; 10826 u8 log_num_sf[0x8]; 10827 u8 log_sf_bar_size[0x8]; 10828 }; 10829 10830 struct mlx5_ifc_query_sf_partitions_out_bits { 10831 u8 status[0x8]; 10832 u8 reserved_at_8[0x18]; 10833 10834 u8 syndrome[0x20]; 10835 10836 u8 reserved_at_40[0x18]; 10837 u8 num_sf_partitions[0x8]; 10838 10839 u8 reserved_at_60[0x20]; 10840 10841 struct mlx5_ifc_sf_partition_bits sf_partition[]; 10842 }; 10843 10844 struct mlx5_ifc_query_sf_partitions_in_bits { 10845 u8 opcode[0x10]; 10846 u8 reserved_at_10[0x10]; 10847 10848 u8 reserved_at_20[0x10]; 10849 u8 op_mod[0x10]; 10850 10851 u8 reserved_at_40[0x40]; 10852 }; 10853 10854 struct mlx5_ifc_dealloc_sf_out_bits { 10855 u8 status[0x8]; 10856 u8 reserved_at_8[0x18]; 10857 10858 u8 syndrome[0x20]; 10859 10860 u8 reserved_at_40[0x40]; 10861 }; 10862 10863 struct mlx5_ifc_dealloc_sf_in_bits { 10864 u8 opcode[0x10]; 10865 u8 reserved_at_10[0x10]; 10866 10867 u8 reserved_at_20[0x10]; 10868 u8 op_mod[0x10]; 10869 10870 u8 reserved_at_40[0x10]; 10871 u8 function_id[0x10]; 10872 10873 u8 reserved_at_60[0x20]; 10874 }; 10875 10876 struct mlx5_ifc_alloc_sf_out_bits { 10877 u8 status[0x8]; 10878 u8 reserved_at_8[0x18]; 10879 10880 u8 syndrome[0x20]; 10881 10882 u8 reserved_at_40[0x40]; 10883 }; 10884 10885 struct mlx5_ifc_alloc_sf_in_bits { 10886 u8 opcode[0x10]; 10887 u8 reserved_at_10[0x10]; 10888 10889 u8 reserved_at_20[0x10]; 10890 u8 op_mod[0x10]; 10891 10892 u8 reserved_at_40[0x10]; 10893 u8 function_id[0x10]; 10894 10895 u8 reserved_at_60[0x20]; 10896 }; 10897 10898 struct mlx5_ifc_affiliated_event_header_bits { 10899 u8 reserved_at_0[0x10]; 10900 u8 obj_type[0x10]; 10901 10902 u8 obj_id[0x20]; 10903 }; 10904 10905 enum { 10906 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = BIT_ULL(0xc), 10907 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_IPSEC = BIT_ULL(0x13), 10908 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_SAMPLER = BIT_ULL(0x20), 10909 }; 10910 10911 enum { 10912 MLX5_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = 0xc, 10913 MLX5_GENERAL_OBJECT_TYPES_IPSEC = 0x13, 10914 MLX5_GENERAL_OBJECT_TYPES_SAMPLER = 0x20, 10915 }; 10916 10917 enum { 10918 MLX5_IPSEC_OBJECT_ICV_LEN_16B, 10919 MLX5_IPSEC_OBJECT_ICV_LEN_12B, 10920 MLX5_IPSEC_OBJECT_ICV_LEN_8B, 10921 }; 10922 10923 struct mlx5_ifc_ipsec_obj_bits { 10924 u8 modify_field_select[0x40]; 10925 u8 full_offload[0x1]; 10926 u8 reserved_at_41[0x1]; 10927 u8 esn_en[0x1]; 10928 u8 esn_overlap[0x1]; 10929 u8 reserved_at_44[0x2]; 10930 u8 icv_length[0x2]; 10931 u8 reserved_at_48[0x4]; 10932 u8 aso_return_reg[0x4]; 10933 u8 reserved_at_50[0x10]; 10934 10935 u8 esn_msb[0x20]; 10936 10937 u8 reserved_at_80[0x8]; 10938 u8 dekn[0x18]; 10939 10940 u8 salt[0x20]; 10941 10942 u8 implicit_iv[0x40]; 10943 10944 u8 reserved_at_100[0x700]; 10945 }; 10946 10947 struct mlx5_ifc_create_ipsec_obj_in_bits { 10948 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 10949 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 10950 }; 10951 10952 enum { 10953 MLX5_MODIFY_IPSEC_BITMASK_ESN_OVERLAP = BIT(0), 10954 MLX5_MODIFY_IPSEC_BITMASK_ESN_MSB = BIT(1), 10955 }; 10956 10957 struct mlx5_ifc_query_ipsec_obj_out_bits { 10958 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 10959 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 10960 }; 10961 10962 struct mlx5_ifc_modify_ipsec_obj_in_bits { 10963 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 10964 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 10965 }; 10966 10967 struct mlx5_ifc_encryption_key_obj_bits { 10968 u8 modify_field_select[0x40]; 10969 10970 u8 reserved_at_40[0x14]; 10971 u8 key_size[0x4]; 10972 u8 reserved_at_58[0x4]; 10973 u8 key_type[0x4]; 10974 10975 u8 reserved_at_60[0x8]; 10976 u8 pd[0x18]; 10977 10978 u8 reserved_at_80[0x180]; 10979 u8 key[8][0x20]; 10980 10981 u8 reserved_at_300[0x500]; 10982 }; 10983 10984 struct mlx5_ifc_create_encryption_key_in_bits { 10985 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 10986 struct mlx5_ifc_encryption_key_obj_bits encryption_key_object; 10987 }; 10988 10989 struct mlx5_ifc_sampler_obj_bits { 10990 u8 modify_field_select[0x40]; 10991 10992 u8 table_type[0x8]; 10993 u8 level[0x8]; 10994 u8 reserved_at_50[0xf]; 10995 u8 ignore_flow_level[0x1]; 10996 10997 u8 sample_ratio[0x20]; 10998 10999 u8 reserved_at_80[0x8]; 11000 u8 sample_table_id[0x18]; 11001 11002 u8 reserved_at_a0[0x8]; 11003 u8 default_table_id[0x18]; 11004 11005 u8 sw_steering_icm_address_rx[0x40]; 11006 u8 sw_steering_icm_address_tx[0x40]; 11007 11008 u8 reserved_at_140[0xa0]; 11009 }; 11010 11011 struct mlx5_ifc_create_sampler_obj_in_bits { 11012 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 11013 struct mlx5_ifc_sampler_obj_bits sampler_object; 11014 }; 11015 11016 enum { 11017 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_128 = 0x0, 11018 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_256 = 0x1, 11019 }; 11020 11021 enum { 11022 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_TYPE_TLS = 0x1, 11023 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_TYPE_IPSEC = 0x2, 11024 }; 11025 11026 struct mlx5_ifc_tls_static_params_bits { 11027 u8 const_2[0x2]; 11028 u8 tls_version[0x4]; 11029 u8 const_1[0x2]; 11030 u8 reserved_at_8[0x14]; 11031 u8 encryption_standard[0x4]; 11032 11033 u8 reserved_at_20[0x20]; 11034 11035 u8 initial_record_number[0x40]; 11036 11037 u8 resync_tcp_sn[0x20]; 11038 11039 u8 gcm_iv[0x20]; 11040 11041 u8 implicit_iv[0x40]; 11042 11043 u8 reserved_at_100[0x8]; 11044 u8 dek_index[0x18]; 11045 11046 u8 reserved_at_120[0xe0]; 11047 }; 11048 11049 struct mlx5_ifc_tls_progress_params_bits { 11050 u8 next_record_tcp_sn[0x20]; 11051 11052 u8 hw_resync_tcp_sn[0x20]; 11053 11054 u8 record_tracker_state[0x2]; 11055 u8 auth_state[0x2]; 11056 u8 reserved_at_44[0x4]; 11057 u8 hw_offset_record_number[0x18]; 11058 }; 11059 11060 enum { 11061 MLX5_MTT_PERM_READ = 1 << 0, 11062 MLX5_MTT_PERM_WRITE = 1 << 1, 11063 MLX5_MTT_PERM_RW = MLX5_MTT_PERM_READ | MLX5_MTT_PERM_WRITE, 11064 }; 11065 11066 #endif /* MLX5_IFC_H */ 11067