1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 #ifndef MLX5_IFC_H 33 #define MLX5_IFC_H 34 35 #include "mlx5_ifc_fpga.h" 36 37 enum { 38 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0, 39 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1, 40 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2, 41 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3, 42 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13, 43 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14, 44 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c, 45 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d, 46 MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4, 47 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5, 48 MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED = 0x7, 49 MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT = 0xc, 50 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10, 51 MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR = 0x11, 52 MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR = 0x12, 53 MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR = 0x8, 54 MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE = 0x9, 55 MLX5_EVENT_TYPE_CODING_GPIO_EVENT = 0x15, 56 MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19, 57 MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a, 58 MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT = 0x1b, 59 MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT = 0x1f, 60 MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa, 61 MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb, 62 MLX5_EVENT_TYPE_CODING_FPGA_ERROR = 0x20, 63 MLX5_EVENT_TYPE_CODING_FPGA_QP_ERROR = 0x21 64 }; 65 66 enum { 67 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0, 68 MLX5_SET_HCA_CAP_OP_MOD_ETHERNET_OFFLOADS = 0x1, 69 MLX5_SET_HCA_CAP_OP_MOD_ODP = 0x2, 70 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3, 71 MLX5_SET_HCA_CAP_OP_MOD_ROCE = 0x4, 72 MLX5_SET_HCA_CAP_OP_MOD_IPSEC = 0x15, 73 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE2 = 0x20, 74 MLX5_SET_HCA_CAP_OP_MOD_PORT_SELECTION = 0x25, 75 }; 76 77 enum { 78 MLX5_SHARED_RESOURCE_UID = 0xffff, 79 }; 80 81 enum { 82 MLX5_OBJ_TYPE_SW_ICM = 0x0008, 83 MLX5_OBJ_TYPE_HEADER_MODIFY_ARGUMENT = 0x23, 84 }; 85 86 enum { 87 MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM = (1ULL << MLX5_OBJ_TYPE_SW_ICM), 88 MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT = (1ULL << 11), 89 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q = (1ULL << 13), 90 MLX5_GENERAL_OBJ_TYPES_CAP_HEADER_MODIFY_ARGUMENT = 91 (1ULL << MLX5_OBJ_TYPE_HEADER_MODIFY_ARGUMENT), 92 MLX5_GENERAL_OBJ_TYPES_CAP_MACSEC_OFFLOAD = (1ULL << 39), 93 }; 94 95 enum { 96 MLX5_OBJ_TYPE_GENEVE_TLV_OPT = 0x000b, 97 MLX5_OBJ_TYPE_VIRTIO_NET_Q = 0x000d, 98 MLX5_OBJ_TYPE_VIRTIO_Q_COUNTERS = 0x001c, 99 MLX5_OBJ_TYPE_MATCH_DEFINER = 0x0018, 100 MLX5_OBJ_TYPE_PAGE_TRACK = 0x46, 101 MLX5_OBJ_TYPE_MKEY = 0xff01, 102 MLX5_OBJ_TYPE_QP = 0xff02, 103 MLX5_OBJ_TYPE_PSV = 0xff03, 104 MLX5_OBJ_TYPE_RMP = 0xff04, 105 MLX5_OBJ_TYPE_XRC_SRQ = 0xff05, 106 MLX5_OBJ_TYPE_RQ = 0xff06, 107 MLX5_OBJ_TYPE_SQ = 0xff07, 108 MLX5_OBJ_TYPE_TIR = 0xff08, 109 MLX5_OBJ_TYPE_TIS = 0xff09, 110 MLX5_OBJ_TYPE_DCT = 0xff0a, 111 MLX5_OBJ_TYPE_XRQ = 0xff0b, 112 MLX5_OBJ_TYPE_RQT = 0xff0e, 113 MLX5_OBJ_TYPE_FLOW_COUNTER = 0xff0f, 114 MLX5_OBJ_TYPE_CQ = 0xff10, 115 }; 116 117 enum { 118 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100, 119 MLX5_CMD_OP_QUERY_ADAPTER = 0x101, 120 MLX5_CMD_OP_INIT_HCA = 0x102, 121 MLX5_CMD_OP_TEARDOWN_HCA = 0x103, 122 MLX5_CMD_OP_ENABLE_HCA = 0x104, 123 MLX5_CMD_OP_DISABLE_HCA = 0x105, 124 MLX5_CMD_OP_QUERY_PAGES = 0x107, 125 MLX5_CMD_OP_MANAGE_PAGES = 0x108, 126 MLX5_CMD_OP_SET_HCA_CAP = 0x109, 127 MLX5_CMD_OP_QUERY_ISSI = 0x10a, 128 MLX5_CMD_OP_SET_ISSI = 0x10b, 129 MLX5_CMD_OP_SET_DRIVER_VERSION = 0x10d, 130 MLX5_CMD_OP_QUERY_SF_PARTITION = 0x111, 131 MLX5_CMD_OP_ALLOC_SF = 0x113, 132 MLX5_CMD_OP_DEALLOC_SF = 0x114, 133 MLX5_CMD_OP_SUSPEND_VHCA = 0x115, 134 MLX5_CMD_OP_RESUME_VHCA = 0x116, 135 MLX5_CMD_OP_QUERY_VHCA_MIGRATION_STATE = 0x117, 136 MLX5_CMD_OP_SAVE_VHCA_STATE = 0x118, 137 MLX5_CMD_OP_LOAD_VHCA_STATE = 0x119, 138 MLX5_CMD_OP_CREATE_MKEY = 0x200, 139 MLX5_CMD_OP_QUERY_MKEY = 0x201, 140 MLX5_CMD_OP_DESTROY_MKEY = 0x202, 141 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203, 142 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204, 143 MLX5_CMD_OP_ALLOC_MEMIC = 0x205, 144 MLX5_CMD_OP_DEALLOC_MEMIC = 0x206, 145 MLX5_CMD_OP_MODIFY_MEMIC = 0x207, 146 MLX5_CMD_OP_CREATE_EQ = 0x301, 147 MLX5_CMD_OP_DESTROY_EQ = 0x302, 148 MLX5_CMD_OP_QUERY_EQ = 0x303, 149 MLX5_CMD_OP_GEN_EQE = 0x304, 150 MLX5_CMD_OP_CREATE_CQ = 0x400, 151 MLX5_CMD_OP_DESTROY_CQ = 0x401, 152 MLX5_CMD_OP_QUERY_CQ = 0x402, 153 MLX5_CMD_OP_MODIFY_CQ = 0x403, 154 MLX5_CMD_OP_CREATE_QP = 0x500, 155 MLX5_CMD_OP_DESTROY_QP = 0x501, 156 MLX5_CMD_OP_RST2INIT_QP = 0x502, 157 MLX5_CMD_OP_INIT2RTR_QP = 0x503, 158 MLX5_CMD_OP_RTR2RTS_QP = 0x504, 159 MLX5_CMD_OP_RTS2RTS_QP = 0x505, 160 MLX5_CMD_OP_SQERR2RTS_QP = 0x506, 161 MLX5_CMD_OP_2ERR_QP = 0x507, 162 MLX5_CMD_OP_2RST_QP = 0x50a, 163 MLX5_CMD_OP_QUERY_QP = 0x50b, 164 MLX5_CMD_OP_SQD_RTS_QP = 0x50c, 165 MLX5_CMD_OP_INIT2INIT_QP = 0x50e, 166 MLX5_CMD_OP_CREATE_PSV = 0x600, 167 MLX5_CMD_OP_DESTROY_PSV = 0x601, 168 MLX5_CMD_OP_CREATE_SRQ = 0x700, 169 MLX5_CMD_OP_DESTROY_SRQ = 0x701, 170 MLX5_CMD_OP_QUERY_SRQ = 0x702, 171 MLX5_CMD_OP_ARM_RQ = 0x703, 172 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705, 173 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706, 174 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707, 175 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708, 176 MLX5_CMD_OP_CREATE_DCT = 0x710, 177 MLX5_CMD_OP_DESTROY_DCT = 0x711, 178 MLX5_CMD_OP_DRAIN_DCT = 0x712, 179 MLX5_CMD_OP_QUERY_DCT = 0x713, 180 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714, 181 MLX5_CMD_OP_CREATE_XRQ = 0x717, 182 MLX5_CMD_OP_DESTROY_XRQ = 0x718, 183 MLX5_CMD_OP_QUERY_XRQ = 0x719, 184 MLX5_CMD_OP_ARM_XRQ = 0x71a, 185 MLX5_CMD_OP_QUERY_XRQ_DC_PARAMS_ENTRY = 0x725, 186 MLX5_CMD_OP_SET_XRQ_DC_PARAMS_ENTRY = 0x726, 187 MLX5_CMD_OP_QUERY_XRQ_ERROR_PARAMS = 0x727, 188 MLX5_CMD_OP_RELEASE_XRQ_ERROR = 0x729, 189 MLX5_CMD_OP_MODIFY_XRQ = 0x72a, 190 MLX5_CMD_OP_QUERY_ESW_FUNCTIONS = 0x740, 191 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750, 192 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751, 193 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752, 194 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753, 195 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754, 196 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755, 197 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760, 198 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761, 199 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762, 200 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763, 201 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764, 202 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765, 203 MLX5_CMD_OP_QUERY_VNIC_ENV = 0x76f, 204 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770, 205 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771, 206 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772, 207 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773, 208 MLX5_CMD_OP_SET_MONITOR_COUNTER = 0x774, 209 MLX5_CMD_OP_ARM_MONITOR_COUNTER = 0x775, 210 MLX5_CMD_OP_SET_PP_RATE_LIMIT = 0x780, 211 MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781, 212 MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT = 0x782, 213 MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT = 0x783, 214 MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT = 0x784, 215 MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT = 0x785, 216 MLX5_CMD_OP_CREATE_QOS_PARA_VPORT = 0x786, 217 MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT = 0x787, 218 MLX5_CMD_OP_ALLOC_PD = 0x800, 219 MLX5_CMD_OP_DEALLOC_PD = 0x801, 220 MLX5_CMD_OP_ALLOC_UAR = 0x802, 221 MLX5_CMD_OP_DEALLOC_UAR = 0x803, 222 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804, 223 MLX5_CMD_OP_ACCESS_REG = 0x805, 224 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806, 225 MLX5_CMD_OP_DETACH_FROM_MCG = 0x807, 226 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a, 227 MLX5_CMD_OP_MAD_IFC = 0x50d, 228 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b, 229 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c, 230 MLX5_CMD_OP_NOP = 0x80d, 231 MLX5_CMD_OP_ALLOC_XRCD = 0x80e, 232 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f, 233 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816, 234 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817, 235 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822, 236 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823, 237 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824, 238 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825, 239 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826, 240 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827, 241 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828, 242 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829, 243 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a, 244 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b, 245 MLX5_CMD_OP_SET_WOL_ROL = 0x830, 246 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831, 247 MLX5_CMD_OP_CREATE_LAG = 0x840, 248 MLX5_CMD_OP_MODIFY_LAG = 0x841, 249 MLX5_CMD_OP_QUERY_LAG = 0x842, 250 MLX5_CMD_OP_DESTROY_LAG = 0x843, 251 MLX5_CMD_OP_CREATE_VPORT_LAG = 0x844, 252 MLX5_CMD_OP_DESTROY_VPORT_LAG = 0x845, 253 MLX5_CMD_OP_CREATE_TIR = 0x900, 254 MLX5_CMD_OP_MODIFY_TIR = 0x901, 255 MLX5_CMD_OP_DESTROY_TIR = 0x902, 256 MLX5_CMD_OP_QUERY_TIR = 0x903, 257 MLX5_CMD_OP_CREATE_SQ = 0x904, 258 MLX5_CMD_OP_MODIFY_SQ = 0x905, 259 MLX5_CMD_OP_DESTROY_SQ = 0x906, 260 MLX5_CMD_OP_QUERY_SQ = 0x907, 261 MLX5_CMD_OP_CREATE_RQ = 0x908, 262 MLX5_CMD_OP_MODIFY_RQ = 0x909, 263 MLX5_CMD_OP_SET_DELAY_DROP_PARAMS = 0x910, 264 MLX5_CMD_OP_DESTROY_RQ = 0x90a, 265 MLX5_CMD_OP_QUERY_RQ = 0x90b, 266 MLX5_CMD_OP_CREATE_RMP = 0x90c, 267 MLX5_CMD_OP_MODIFY_RMP = 0x90d, 268 MLX5_CMD_OP_DESTROY_RMP = 0x90e, 269 MLX5_CMD_OP_QUERY_RMP = 0x90f, 270 MLX5_CMD_OP_CREATE_TIS = 0x912, 271 MLX5_CMD_OP_MODIFY_TIS = 0x913, 272 MLX5_CMD_OP_DESTROY_TIS = 0x914, 273 MLX5_CMD_OP_QUERY_TIS = 0x915, 274 MLX5_CMD_OP_CREATE_RQT = 0x916, 275 MLX5_CMD_OP_MODIFY_RQT = 0x917, 276 MLX5_CMD_OP_DESTROY_RQT = 0x918, 277 MLX5_CMD_OP_QUERY_RQT = 0x919, 278 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f, 279 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930, 280 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931, 281 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932, 282 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933, 283 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934, 284 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935, 285 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936, 286 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937, 287 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938, 288 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939, 289 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a, 290 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b, 291 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c, 292 MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT = 0x93d, 293 MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT = 0x93e, 294 MLX5_CMD_OP_QUERY_PACKET_REFORMAT_CONTEXT = 0x93f, 295 MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT = 0x940, 296 MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941, 297 MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT = 0x942, 298 MLX5_CMD_OP_FPGA_CREATE_QP = 0x960, 299 MLX5_CMD_OP_FPGA_MODIFY_QP = 0x961, 300 MLX5_CMD_OP_FPGA_QUERY_QP = 0x962, 301 MLX5_CMD_OP_FPGA_DESTROY_QP = 0x963, 302 MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS = 0x964, 303 MLX5_CMD_OP_CREATE_GENERAL_OBJECT = 0xa00, 304 MLX5_CMD_OP_MODIFY_GENERAL_OBJECT = 0xa01, 305 MLX5_CMD_OP_QUERY_GENERAL_OBJECT = 0xa02, 306 MLX5_CMD_OP_DESTROY_GENERAL_OBJECT = 0xa03, 307 MLX5_CMD_OP_CREATE_UCTX = 0xa04, 308 MLX5_CMD_OP_DESTROY_UCTX = 0xa06, 309 MLX5_CMD_OP_CREATE_UMEM = 0xa08, 310 MLX5_CMD_OP_DESTROY_UMEM = 0xa0a, 311 MLX5_CMD_OP_SYNC_STEERING = 0xb00, 312 MLX5_CMD_OP_QUERY_VHCA_STATE = 0xb0d, 313 MLX5_CMD_OP_MODIFY_VHCA_STATE = 0xb0e, 314 MLX5_CMD_OP_SYNC_CRYPTO = 0xb12, 315 MLX5_CMD_OP_ALLOW_OTHER_VHCA_ACCESS = 0xb16, 316 MLX5_CMD_OP_MAX 317 }; 318 319 /* Valid range for general commands that don't work over an object */ 320 enum { 321 MLX5_CMD_OP_GENERAL_START = 0xb00, 322 MLX5_CMD_OP_GENERAL_END = 0xd00, 323 }; 324 325 enum { 326 MLX5_FT_NIC_RX_2_NIC_RX_RDMA = BIT(0), 327 MLX5_FT_NIC_TX_RDMA_2_NIC_TX = BIT(1), 328 }; 329 330 enum { 331 MLX5_CMD_OP_MOD_UPDATE_HEADER_MODIFY_ARGUMENT = 0x1, 332 }; 333 334 struct mlx5_ifc_flow_table_fields_supported_bits { 335 u8 outer_dmac[0x1]; 336 u8 outer_smac[0x1]; 337 u8 outer_ether_type[0x1]; 338 u8 outer_ip_version[0x1]; 339 u8 outer_first_prio[0x1]; 340 u8 outer_first_cfi[0x1]; 341 u8 outer_first_vid[0x1]; 342 u8 outer_ipv4_ttl[0x1]; 343 u8 outer_second_prio[0x1]; 344 u8 outer_second_cfi[0x1]; 345 u8 outer_second_vid[0x1]; 346 u8 reserved_at_b[0x1]; 347 u8 outer_sip[0x1]; 348 u8 outer_dip[0x1]; 349 u8 outer_frag[0x1]; 350 u8 outer_ip_protocol[0x1]; 351 u8 outer_ip_ecn[0x1]; 352 u8 outer_ip_dscp[0x1]; 353 u8 outer_udp_sport[0x1]; 354 u8 outer_udp_dport[0x1]; 355 u8 outer_tcp_sport[0x1]; 356 u8 outer_tcp_dport[0x1]; 357 u8 outer_tcp_flags[0x1]; 358 u8 outer_gre_protocol[0x1]; 359 u8 outer_gre_key[0x1]; 360 u8 outer_vxlan_vni[0x1]; 361 u8 outer_geneve_vni[0x1]; 362 u8 outer_geneve_oam[0x1]; 363 u8 outer_geneve_protocol_type[0x1]; 364 u8 outer_geneve_opt_len[0x1]; 365 u8 source_vhca_port[0x1]; 366 u8 source_eswitch_port[0x1]; 367 368 u8 inner_dmac[0x1]; 369 u8 inner_smac[0x1]; 370 u8 inner_ether_type[0x1]; 371 u8 inner_ip_version[0x1]; 372 u8 inner_first_prio[0x1]; 373 u8 inner_first_cfi[0x1]; 374 u8 inner_first_vid[0x1]; 375 u8 reserved_at_27[0x1]; 376 u8 inner_second_prio[0x1]; 377 u8 inner_second_cfi[0x1]; 378 u8 inner_second_vid[0x1]; 379 u8 reserved_at_2b[0x1]; 380 u8 inner_sip[0x1]; 381 u8 inner_dip[0x1]; 382 u8 inner_frag[0x1]; 383 u8 inner_ip_protocol[0x1]; 384 u8 inner_ip_ecn[0x1]; 385 u8 inner_ip_dscp[0x1]; 386 u8 inner_udp_sport[0x1]; 387 u8 inner_udp_dport[0x1]; 388 u8 inner_tcp_sport[0x1]; 389 u8 inner_tcp_dport[0x1]; 390 u8 inner_tcp_flags[0x1]; 391 u8 reserved_at_37[0x9]; 392 393 u8 geneve_tlv_option_0_data[0x1]; 394 u8 geneve_tlv_option_0_exist[0x1]; 395 u8 reserved_at_42[0x3]; 396 u8 outer_first_mpls_over_udp[0x4]; 397 u8 outer_first_mpls_over_gre[0x4]; 398 u8 inner_first_mpls[0x4]; 399 u8 outer_first_mpls[0x4]; 400 u8 reserved_at_55[0x2]; 401 u8 outer_esp_spi[0x1]; 402 u8 reserved_at_58[0x2]; 403 u8 bth_dst_qp[0x1]; 404 u8 reserved_at_5b[0x5]; 405 406 u8 reserved_at_60[0x18]; 407 u8 metadata_reg_c_7[0x1]; 408 u8 metadata_reg_c_6[0x1]; 409 u8 metadata_reg_c_5[0x1]; 410 u8 metadata_reg_c_4[0x1]; 411 u8 metadata_reg_c_3[0x1]; 412 u8 metadata_reg_c_2[0x1]; 413 u8 metadata_reg_c_1[0x1]; 414 u8 metadata_reg_c_0[0x1]; 415 }; 416 417 /* Table 2170 - Flow Table Fields Supported 2 Format */ 418 struct mlx5_ifc_flow_table_fields_supported_2_bits { 419 u8 reserved_at_0[0x2]; 420 u8 inner_l4_type[0x1]; 421 u8 outer_l4_type[0x1]; 422 u8 reserved_at_4[0xa]; 423 u8 bth_opcode[0x1]; 424 u8 reserved_at_f[0x1]; 425 u8 tunnel_header_0_1[0x1]; 426 u8 reserved_at_11[0xf]; 427 428 u8 reserved_at_20[0x60]; 429 }; 430 431 struct mlx5_ifc_flow_table_prop_layout_bits { 432 u8 ft_support[0x1]; 433 u8 reserved_at_1[0x1]; 434 u8 flow_counter[0x1]; 435 u8 flow_modify_en[0x1]; 436 u8 modify_root[0x1]; 437 u8 identified_miss_table_mode[0x1]; 438 u8 flow_table_modify[0x1]; 439 u8 reformat[0x1]; 440 u8 decap[0x1]; 441 u8 reset_root_to_default[0x1]; 442 u8 pop_vlan[0x1]; 443 u8 push_vlan[0x1]; 444 u8 reserved_at_c[0x1]; 445 u8 pop_vlan_2[0x1]; 446 u8 push_vlan_2[0x1]; 447 u8 reformat_and_vlan_action[0x1]; 448 u8 reserved_at_10[0x1]; 449 u8 sw_owner[0x1]; 450 u8 reformat_l3_tunnel_to_l2[0x1]; 451 u8 reformat_l2_to_l3_tunnel[0x1]; 452 u8 reformat_and_modify_action[0x1]; 453 u8 ignore_flow_level[0x1]; 454 u8 reserved_at_16[0x1]; 455 u8 table_miss_action_domain[0x1]; 456 u8 termination_table[0x1]; 457 u8 reformat_and_fwd_to_table[0x1]; 458 u8 reserved_at_1a[0x2]; 459 u8 ipsec_encrypt[0x1]; 460 u8 ipsec_decrypt[0x1]; 461 u8 sw_owner_v2[0x1]; 462 u8 reserved_at_1f[0x1]; 463 464 u8 termination_table_raw_traffic[0x1]; 465 u8 reserved_at_21[0x1]; 466 u8 log_max_ft_size[0x6]; 467 u8 log_max_modify_header_context[0x8]; 468 u8 max_modify_header_actions[0x8]; 469 u8 max_ft_level[0x8]; 470 471 u8 reformat_add_esp_trasport[0x1]; 472 u8 reformat_l2_to_l3_esp_tunnel[0x1]; 473 u8 reformat_add_esp_transport_over_udp[0x1]; 474 u8 reformat_del_esp_trasport[0x1]; 475 u8 reformat_l3_esp_tunnel_to_l2[0x1]; 476 u8 reformat_del_esp_transport_over_udp[0x1]; 477 u8 execute_aso[0x1]; 478 u8 reserved_at_47[0x19]; 479 480 u8 reserved_at_60[0x2]; 481 u8 reformat_insert[0x1]; 482 u8 reformat_remove[0x1]; 483 u8 macsec_encrypt[0x1]; 484 u8 macsec_decrypt[0x1]; 485 u8 reserved_at_66[0x2]; 486 u8 reformat_add_macsec[0x1]; 487 u8 reformat_remove_macsec[0x1]; 488 u8 reserved_at_6a[0xe]; 489 u8 log_max_ft_num[0x8]; 490 491 u8 reserved_at_80[0x10]; 492 u8 log_max_flow_counter[0x8]; 493 u8 log_max_destination[0x8]; 494 495 u8 reserved_at_a0[0x18]; 496 u8 log_max_flow[0x8]; 497 498 u8 reserved_at_c0[0x40]; 499 500 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support; 501 502 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support; 503 }; 504 505 struct mlx5_ifc_odp_per_transport_service_cap_bits { 506 u8 send[0x1]; 507 u8 receive[0x1]; 508 u8 write[0x1]; 509 u8 read[0x1]; 510 u8 atomic[0x1]; 511 u8 srq_receive[0x1]; 512 u8 reserved_at_6[0x1a]; 513 }; 514 515 struct mlx5_ifc_ipv4_layout_bits { 516 u8 reserved_at_0[0x60]; 517 518 u8 ipv4[0x20]; 519 }; 520 521 struct mlx5_ifc_ipv6_layout_bits { 522 u8 ipv6[16][0x8]; 523 }; 524 525 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits { 526 struct mlx5_ifc_ipv6_layout_bits ipv6_layout; 527 struct mlx5_ifc_ipv4_layout_bits ipv4_layout; 528 u8 reserved_at_0[0x80]; 529 }; 530 531 enum { 532 MLX5_PACKET_L4_TYPE_NONE, 533 MLX5_PACKET_L4_TYPE_TCP, 534 MLX5_PACKET_L4_TYPE_UDP, 535 }; 536 537 struct mlx5_ifc_fte_match_set_lyr_2_4_bits { 538 u8 smac_47_16[0x20]; 539 540 u8 smac_15_0[0x10]; 541 u8 ethertype[0x10]; 542 543 u8 dmac_47_16[0x20]; 544 545 u8 dmac_15_0[0x10]; 546 u8 first_prio[0x3]; 547 u8 first_cfi[0x1]; 548 u8 first_vid[0xc]; 549 550 u8 ip_protocol[0x8]; 551 u8 ip_dscp[0x6]; 552 u8 ip_ecn[0x2]; 553 u8 cvlan_tag[0x1]; 554 u8 svlan_tag[0x1]; 555 u8 frag[0x1]; 556 u8 ip_version[0x4]; 557 u8 tcp_flags[0x9]; 558 559 u8 tcp_sport[0x10]; 560 u8 tcp_dport[0x10]; 561 562 u8 l4_type[0x2]; 563 u8 reserved_at_c2[0xe]; 564 u8 ipv4_ihl[0x4]; 565 u8 reserved_at_c4[0x4]; 566 567 u8 ttl_hoplimit[0x8]; 568 569 u8 udp_sport[0x10]; 570 u8 udp_dport[0x10]; 571 572 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6; 573 574 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6; 575 }; 576 577 struct mlx5_ifc_nvgre_key_bits { 578 u8 hi[0x18]; 579 u8 lo[0x8]; 580 }; 581 582 union mlx5_ifc_gre_key_bits { 583 struct mlx5_ifc_nvgre_key_bits nvgre; 584 u8 key[0x20]; 585 }; 586 587 struct mlx5_ifc_fte_match_set_misc_bits { 588 u8 gre_c_present[0x1]; 589 u8 reserved_at_1[0x1]; 590 u8 gre_k_present[0x1]; 591 u8 gre_s_present[0x1]; 592 u8 source_vhca_port[0x4]; 593 u8 source_sqn[0x18]; 594 595 u8 source_eswitch_owner_vhca_id[0x10]; 596 u8 source_port[0x10]; 597 598 u8 outer_second_prio[0x3]; 599 u8 outer_second_cfi[0x1]; 600 u8 outer_second_vid[0xc]; 601 u8 inner_second_prio[0x3]; 602 u8 inner_second_cfi[0x1]; 603 u8 inner_second_vid[0xc]; 604 605 u8 outer_second_cvlan_tag[0x1]; 606 u8 inner_second_cvlan_tag[0x1]; 607 u8 outer_second_svlan_tag[0x1]; 608 u8 inner_second_svlan_tag[0x1]; 609 u8 reserved_at_64[0xc]; 610 u8 gre_protocol[0x10]; 611 612 union mlx5_ifc_gre_key_bits gre_key; 613 614 u8 vxlan_vni[0x18]; 615 u8 bth_opcode[0x8]; 616 617 u8 geneve_vni[0x18]; 618 u8 reserved_at_d8[0x6]; 619 u8 geneve_tlv_option_0_exist[0x1]; 620 u8 geneve_oam[0x1]; 621 622 u8 reserved_at_e0[0xc]; 623 u8 outer_ipv6_flow_label[0x14]; 624 625 u8 reserved_at_100[0xc]; 626 u8 inner_ipv6_flow_label[0x14]; 627 628 u8 reserved_at_120[0xa]; 629 u8 geneve_opt_len[0x6]; 630 u8 geneve_protocol_type[0x10]; 631 632 u8 reserved_at_140[0x8]; 633 u8 bth_dst_qp[0x18]; 634 u8 inner_esp_spi[0x20]; 635 u8 outer_esp_spi[0x20]; 636 u8 reserved_at_1a0[0x60]; 637 }; 638 639 struct mlx5_ifc_fte_match_mpls_bits { 640 u8 mpls_label[0x14]; 641 u8 mpls_exp[0x3]; 642 u8 mpls_s_bos[0x1]; 643 u8 mpls_ttl[0x8]; 644 }; 645 646 struct mlx5_ifc_fte_match_set_misc2_bits { 647 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls; 648 649 struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls; 650 651 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre; 652 653 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp; 654 655 u8 metadata_reg_c_7[0x20]; 656 657 u8 metadata_reg_c_6[0x20]; 658 659 u8 metadata_reg_c_5[0x20]; 660 661 u8 metadata_reg_c_4[0x20]; 662 663 u8 metadata_reg_c_3[0x20]; 664 665 u8 metadata_reg_c_2[0x20]; 666 667 u8 metadata_reg_c_1[0x20]; 668 669 u8 metadata_reg_c_0[0x20]; 670 671 u8 metadata_reg_a[0x20]; 672 673 u8 reserved_at_1a0[0x8]; 674 675 u8 macsec_syndrome[0x8]; 676 u8 ipsec_syndrome[0x8]; 677 u8 reserved_at_1b8[0x8]; 678 679 u8 reserved_at_1c0[0x40]; 680 }; 681 682 struct mlx5_ifc_fte_match_set_misc3_bits { 683 u8 inner_tcp_seq_num[0x20]; 684 685 u8 outer_tcp_seq_num[0x20]; 686 687 u8 inner_tcp_ack_num[0x20]; 688 689 u8 outer_tcp_ack_num[0x20]; 690 691 u8 reserved_at_80[0x8]; 692 u8 outer_vxlan_gpe_vni[0x18]; 693 694 u8 outer_vxlan_gpe_next_protocol[0x8]; 695 u8 outer_vxlan_gpe_flags[0x8]; 696 u8 reserved_at_b0[0x10]; 697 698 u8 icmp_header_data[0x20]; 699 700 u8 icmpv6_header_data[0x20]; 701 702 u8 icmp_type[0x8]; 703 u8 icmp_code[0x8]; 704 u8 icmpv6_type[0x8]; 705 u8 icmpv6_code[0x8]; 706 707 u8 geneve_tlv_option_0_data[0x20]; 708 709 u8 gtpu_teid[0x20]; 710 711 u8 gtpu_msg_type[0x8]; 712 u8 gtpu_msg_flags[0x8]; 713 u8 reserved_at_170[0x10]; 714 715 u8 gtpu_dw_2[0x20]; 716 717 u8 gtpu_first_ext_dw_0[0x20]; 718 719 u8 gtpu_dw_0[0x20]; 720 721 u8 reserved_at_1e0[0x20]; 722 }; 723 724 struct mlx5_ifc_fte_match_set_misc4_bits { 725 u8 prog_sample_field_value_0[0x20]; 726 727 u8 prog_sample_field_id_0[0x20]; 728 729 u8 prog_sample_field_value_1[0x20]; 730 731 u8 prog_sample_field_id_1[0x20]; 732 733 u8 prog_sample_field_value_2[0x20]; 734 735 u8 prog_sample_field_id_2[0x20]; 736 737 u8 prog_sample_field_value_3[0x20]; 738 739 u8 prog_sample_field_id_3[0x20]; 740 741 u8 reserved_at_100[0x100]; 742 }; 743 744 struct mlx5_ifc_fte_match_set_misc5_bits { 745 u8 macsec_tag_0[0x20]; 746 747 u8 macsec_tag_1[0x20]; 748 749 u8 macsec_tag_2[0x20]; 750 751 u8 macsec_tag_3[0x20]; 752 753 u8 tunnel_header_0[0x20]; 754 755 u8 tunnel_header_1[0x20]; 756 757 u8 tunnel_header_2[0x20]; 758 759 u8 tunnel_header_3[0x20]; 760 761 u8 reserved_at_100[0x100]; 762 }; 763 764 struct mlx5_ifc_cmd_pas_bits { 765 u8 pa_h[0x20]; 766 767 u8 pa_l[0x14]; 768 u8 reserved_at_34[0xc]; 769 }; 770 771 struct mlx5_ifc_uint64_bits { 772 u8 hi[0x20]; 773 774 u8 lo[0x20]; 775 }; 776 777 enum { 778 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0, 779 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7, 780 MLX5_ADS_STAT_RATE_10GBPS = 0x8, 781 MLX5_ADS_STAT_RATE_30GBPS = 0x9, 782 MLX5_ADS_STAT_RATE_5GBPS = 0xa, 783 MLX5_ADS_STAT_RATE_20GBPS = 0xb, 784 MLX5_ADS_STAT_RATE_40GBPS = 0xc, 785 MLX5_ADS_STAT_RATE_60GBPS = 0xd, 786 MLX5_ADS_STAT_RATE_80GBPS = 0xe, 787 MLX5_ADS_STAT_RATE_120GBPS = 0xf, 788 }; 789 790 struct mlx5_ifc_ads_bits { 791 u8 fl[0x1]; 792 u8 free_ar[0x1]; 793 u8 reserved_at_2[0xe]; 794 u8 pkey_index[0x10]; 795 796 u8 reserved_at_20[0x8]; 797 u8 grh[0x1]; 798 u8 mlid[0x7]; 799 u8 rlid[0x10]; 800 801 u8 ack_timeout[0x5]; 802 u8 reserved_at_45[0x3]; 803 u8 src_addr_index[0x8]; 804 u8 reserved_at_50[0x4]; 805 u8 stat_rate[0x4]; 806 u8 hop_limit[0x8]; 807 808 u8 reserved_at_60[0x4]; 809 u8 tclass[0x8]; 810 u8 flow_label[0x14]; 811 812 u8 rgid_rip[16][0x8]; 813 814 u8 reserved_at_100[0x4]; 815 u8 f_dscp[0x1]; 816 u8 f_ecn[0x1]; 817 u8 reserved_at_106[0x1]; 818 u8 f_eth_prio[0x1]; 819 u8 ecn[0x2]; 820 u8 dscp[0x6]; 821 u8 udp_sport[0x10]; 822 823 u8 dei_cfi[0x1]; 824 u8 eth_prio[0x3]; 825 u8 sl[0x4]; 826 u8 vhca_port_num[0x8]; 827 u8 rmac_47_32[0x10]; 828 829 u8 rmac_31_0[0x20]; 830 }; 831 832 struct mlx5_ifc_flow_table_nic_cap_bits { 833 u8 nic_rx_multi_path_tirs[0x1]; 834 u8 nic_rx_multi_path_tirs_fts[0x1]; 835 u8 allow_sniffer_and_nic_rx_shared_tir[0x1]; 836 u8 reserved_at_3[0x4]; 837 u8 sw_owner_reformat_supported[0x1]; 838 u8 reserved_at_8[0x18]; 839 840 u8 encap_general_header[0x1]; 841 u8 reserved_at_21[0xa]; 842 u8 log_max_packet_reformat_context[0x5]; 843 u8 reserved_at_30[0x6]; 844 u8 max_encap_header_size[0xa]; 845 u8 reserved_at_40[0x1c0]; 846 847 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive; 848 849 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_rdma; 850 851 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer; 852 853 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit; 854 855 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_rdma; 856 857 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer; 858 859 u8 reserved_at_e00[0x600]; 860 861 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_receive; 862 863 u8 reserved_at_1480[0x80]; 864 865 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_receive_rdma; 866 867 u8 reserved_at_1580[0x280]; 868 869 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_transmit_rdma; 870 871 u8 reserved_at_1880[0x780]; 872 873 u8 sw_steering_nic_rx_action_drop_icm_address[0x40]; 874 875 u8 sw_steering_nic_tx_action_drop_icm_address[0x40]; 876 877 u8 sw_steering_nic_tx_action_allow_icm_address[0x40]; 878 879 u8 reserved_at_20c0[0x5f40]; 880 }; 881 882 struct mlx5_ifc_port_selection_cap_bits { 883 u8 reserved_at_0[0x10]; 884 u8 port_select_flow_table[0x1]; 885 u8 reserved_at_11[0x1]; 886 u8 port_select_flow_table_bypass[0x1]; 887 u8 reserved_at_13[0xd]; 888 889 u8 reserved_at_20[0x1e0]; 890 891 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_port_selection; 892 893 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_port_selection; 894 895 u8 reserved_at_480[0x7b80]; 896 }; 897 898 enum { 899 MLX5_FDB_TO_VPORT_REG_C_0 = 0x01, 900 MLX5_FDB_TO_VPORT_REG_C_1 = 0x02, 901 MLX5_FDB_TO_VPORT_REG_C_2 = 0x04, 902 MLX5_FDB_TO_VPORT_REG_C_3 = 0x08, 903 MLX5_FDB_TO_VPORT_REG_C_4 = 0x10, 904 MLX5_FDB_TO_VPORT_REG_C_5 = 0x20, 905 MLX5_FDB_TO_VPORT_REG_C_6 = 0x40, 906 MLX5_FDB_TO_VPORT_REG_C_7 = 0x80, 907 }; 908 909 struct mlx5_ifc_flow_table_eswitch_cap_bits { 910 u8 fdb_to_vport_reg_c_id[0x8]; 911 u8 reserved_at_8[0x5]; 912 u8 fdb_uplink_hairpin[0x1]; 913 u8 fdb_multi_path_any_table_limit_regc[0x1]; 914 u8 reserved_at_f[0x3]; 915 u8 fdb_multi_path_any_table[0x1]; 916 u8 reserved_at_13[0x2]; 917 u8 fdb_modify_header_fwd_to_table[0x1]; 918 u8 fdb_ipv4_ttl_modify[0x1]; 919 u8 flow_source[0x1]; 920 u8 reserved_at_18[0x2]; 921 u8 multi_fdb_encap[0x1]; 922 u8 egress_acl_forward_to_vport[0x1]; 923 u8 fdb_multi_path_to_table[0x1]; 924 u8 reserved_at_1d[0x3]; 925 926 u8 reserved_at_20[0x1e0]; 927 928 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb; 929 930 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress; 931 932 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress; 933 934 u8 reserved_at_800[0xC00]; 935 936 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_esw_fdb; 937 938 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_bitmask_support_2_esw_fdb; 939 940 u8 reserved_at_1500[0x300]; 941 942 u8 sw_steering_fdb_action_drop_icm_address_rx[0x40]; 943 944 u8 sw_steering_fdb_action_drop_icm_address_tx[0x40]; 945 946 u8 sw_steering_uplink_icm_address_rx[0x40]; 947 948 u8 sw_steering_uplink_icm_address_tx[0x40]; 949 950 u8 reserved_at_1900[0x6700]; 951 }; 952 953 enum { 954 MLX5_COUNTER_SOURCE_ESWITCH = 0x0, 955 MLX5_COUNTER_FLOW_ESWITCH = 0x1, 956 }; 957 958 struct mlx5_ifc_e_switch_cap_bits { 959 u8 vport_svlan_strip[0x1]; 960 u8 vport_cvlan_strip[0x1]; 961 u8 vport_svlan_insert[0x1]; 962 u8 vport_cvlan_insert_if_not_exist[0x1]; 963 u8 vport_cvlan_insert_overwrite[0x1]; 964 u8 reserved_at_5[0x1]; 965 u8 vport_cvlan_insert_always[0x1]; 966 u8 esw_shared_ingress_acl[0x1]; 967 u8 esw_uplink_ingress_acl[0x1]; 968 u8 root_ft_on_other_esw[0x1]; 969 u8 reserved_at_a[0xf]; 970 u8 esw_functions_changed[0x1]; 971 u8 reserved_at_1a[0x1]; 972 u8 ecpf_vport_exists[0x1]; 973 u8 counter_eswitch_affinity[0x1]; 974 u8 merged_eswitch[0x1]; 975 u8 nic_vport_node_guid_modify[0x1]; 976 u8 nic_vport_port_guid_modify[0x1]; 977 978 u8 vxlan_encap_decap[0x1]; 979 u8 nvgre_encap_decap[0x1]; 980 u8 reserved_at_22[0x1]; 981 u8 log_max_fdb_encap_uplink[0x5]; 982 u8 reserved_at_21[0x3]; 983 u8 log_max_packet_reformat_context[0x5]; 984 u8 reserved_2b[0x6]; 985 u8 max_encap_header_size[0xa]; 986 987 u8 reserved_at_40[0xb]; 988 u8 log_max_esw_sf[0x5]; 989 u8 esw_sf_base_id[0x10]; 990 991 u8 reserved_at_60[0x7a0]; 992 993 }; 994 995 struct mlx5_ifc_qos_cap_bits { 996 u8 packet_pacing[0x1]; 997 u8 esw_scheduling[0x1]; 998 u8 esw_bw_share[0x1]; 999 u8 esw_rate_limit[0x1]; 1000 u8 reserved_at_4[0x1]; 1001 u8 packet_pacing_burst_bound[0x1]; 1002 u8 packet_pacing_typical_size[0x1]; 1003 u8 reserved_at_7[0x1]; 1004 u8 nic_sq_scheduling[0x1]; 1005 u8 nic_bw_share[0x1]; 1006 u8 nic_rate_limit[0x1]; 1007 u8 packet_pacing_uid[0x1]; 1008 u8 log_esw_max_sched_depth[0x4]; 1009 u8 reserved_at_10[0x10]; 1010 1011 u8 reserved_at_20[0xb]; 1012 u8 log_max_qos_nic_queue_group[0x5]; 1013 u8 reserved_at_30[0x10]; 1014 1015 u8 packet_pacing_max_rate[0x20]; 1016 1017 u8 packet_pacing_min_rate[0x20]; 1018 1019 u8 reserved_at_80[0x10]; 1020 u8 packet_pacing_rate_table_size[0x10]; 1021 1022 u8 esw_element_type[0x10]; 1023 u8 esw_tsar_type[0x10]; 1024 1025 u8 reserved_at_c0[0x10]; 1026 u8 max_qos_para_vport[0x10]; 1027 1028 u8 max_tsar_bw_share[0x20]; 1029 1030 u8 reserved_at_100[0x20]; 1031 1032 u8 reserved_at_120[0x3]; 1033 u8 log_meter_aso_granularity[0x5]; 1034 u8 reserved_at_128[0x3]; 1035 u8 log_meter_aso_max_alloc[0x5]; 1036 u8 reserved_at_130[0x3]; 1037 u8 log_max_num_meter_aso[0x5]; 1038 u8 reserved_at_138[0x8]; 1039 1040 u8 reserved_at_140[0x6c0]; 1041 }; 1042 1043 struct mlx5_ifc_debug_cap_bits { 1044 u8 core_dump_general[0x1]; 1045 u8 core_dump_qp[0x1]; 1046 u8 reserved_at_2[0x7]; 1047 u8 resource_dump[0x1]; 1048 u8 reserved_at_a[0x16]; 1049 1050 u8 reserved_at_20[0x2]; 1051 u8 stall_detect[0x1]; 1052 u8 reserved_at_23[0x1d]; 1053 1054 u8 reserved_at_40[0x7c0]; 1055 }; 1056 1057 struct mlx5_ifc_per_protocol_networking_offload_caps_bits { 1058 u8 csum_cap[0x1]; 1059 u8 vlan_cap[0x1]; 1060 u8 lro_cap[0x1]; 1061 u8 lro_psh_flag[0x1]; 1062 u8 lro_time_stamp[0x1]; 1063 u8 reserved_at_5[0x2]; 1064 u8 wqe_vlan_insert[0x1]; 1065 u8 self_lb_en_modifiable[0x1]; 1066 u8 reserved_at_9[0x2]; 1067 u8 max_lso_cap[0x5]; 1068 u8 multi_pkt_send_wqe[0x2]; 1069 u8 wqe_inline_mode[0x2]; 1070 u8 rss_ind_tbl_cap[0x4]; 1071 u8 reg_umr_sq[0x1]; 1072 u8 scatter_fcs[0x1]; 1073 u8 enhanced_multi_pkt_send_wqe[0x1]; 1074 u8 tunnel_lso_const_out_ip_id[0x1]; 1075 u8 tunnel_lro_gre[0x1]; 1076 u8 tunnel_lro_vxlan[0x1]; 1077 u8 tunnel_stateless_gre[0x1]; 1078 u8 tunnel_stateless_vxlan[0x1]; 1079 1080 u8 swp[0x1]; 1081 u8 swp_csum[0x1]; 1082 u8 swp_lso[0x1]; 1083 u8 cqe_checksum_full[0x1]; 1084 u8 tunnel_stateless_geneve_tx[0x1]; 1085 u8 tunnel_stateless_mpls_over_udp[0x1]; 1086 u8 tunnel_stateless_mpls_over_gre[0x1]; 1087 u8 tunnel_stateless_vxlan_gpe[0x1]; 1088 u8 tunnel_stateless_ipv4_over_vxlan[0x1]; 1089 u8 tunnel_stateless_ip_over_ip[0x1]; 1090 u8 insert_trailer[0x1]; 1091 u8 reserved_at_2b[0x1]; 1092 u8 tunnel_stateless_ip_over_ip_rx[0x1]; 1093 u8 tunnel_stateless_ip_over_ip_tx[0x1]; 1094 u8 reserved_at_2e[0x2]; 1095 u8 max_vxlan_udp_ports[0x8]; 1096 u8 reserved_at_38[0x6]; 1097 u8 max_geneve_opt_len[0x1]; 1098 u8 tunnel_stateless_geneve_rx[0x1]; 1099 1100 u8 reserved_at_40[0x10]; 1101 u8 lro_min_mss_size[0x10]; 1102 1103 u8 reserved_at_60[0x120]; 1104 1105 u8 lro_timer_supported_periods[4][0x20]; 1106 1107 u8 reserved_at_200[0x600]; 1108 }; 1109 1110 enum { 1111 MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING = 0x0, 1112 MLX5_TIMESTAMP_FORMAT_CAP_REAL_TIME = 0x1, 1113 MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING_AND_REAL_TIME = 0x2, 1114 }; 1115 1116 struct mlx5_ifc_roce_cap_bits { 1117 u8 roce_apm[0x1]; 1118 u8 reserved_at_1[0x3]; 1119 u8 sw_r_roce_src_udp_port[0x1]; 1120 u8 fl_rc_qp_when_roce_disabled[0x1]; 1121 u8 fl_rc_qp_when_roce_enabled[0x1]; 1122 u8 roce_cc_general[0x1]; 1123 u8 qp_ooo_transmit_default[0x1]; 1124 u8 reserved_at_9[0x15]; 1125 u8 qp_ts_format[0x2]; 1126 1127 u8 reserved_at_20[0x60]; 1128 1129 u8 reserved_at_80[0xc]; 1130 u8 l3_type[0x4]; 1131 u8 reserved_at_90[0x8]; 1132 u8 roce_version[0x8]; 1133 1134 u8 reserved_at_a0[0x10]; 1135 u8 r_roce_dest_udp_port[0x10]; 1136 1137 u8 r_roce_max_src_udp_port[0x10]; 1138 u8 r_roce_min_src_udp_port[0x10]; 1139 1140 u8 reserved_at_e0[0x10]; 1141 u8 roce_address_table_size[0x10]; 1142 1143 u8 reserved_at_100[0x700]; 1144 }; 1145 1146 struct mlx5_ifc_sync_steering_in_bits { 1147 u8 opcode[0x10]; 1148 u8 uid[0x10]; 1149 1150 u8 reserved_at_20[0x10]; 1151 u8 op_mod[0x10]; 1152 1153 u8 reserved_at_40[0xc0]; 1154 }; 1155 1156 struct mlx5_ifc_sync_steering_out_bits { 1157 u8 status[0x8]; 1158 u8 reserved_at_8[0x18]; 1159 1160 u8 syndrome[0x20]; 1161 1162 u8 reserved_at_40[0x40]; 1163 }; 1164 1165 struct mlx5_ifc_sync_crypto_in_bits { 1166 u8 opcode[0x10]; 1167 u8 uid[0x10]; 1168 1169 u8 reserved_at_20[0x10]; 1170 u8 op_mod[0x10]; 1171 1172 u8 reserved_at_40[0x20]; 1173 1174 u8 reserved_at_60[0x10]; 1175 u8 crypto_type[0x10]; 1176 1177 u8 reserved_at_80[0x80]; 1178 }; 1179 1180 struct mlx5_ifc_sync_crypto_out_bits { 1181 u8 status[0x8]; 1182 u8 reserved_at_8[0x18]; 1183 1184 u8 syndrome[0x20]; 1185 1186 u8 reserved_at_40[0x40]; 1187 }; 1188 1189 struct mlx5_ifc_device_mem_cap_bits { 1190 u8 memic[0x1]; 1191 u8 reserved_at_1[0x1f]; 1192 1193 u8 reserved_at_20[0xb]; 1194 u8 log_min_memic_alloc_size[0x5]; 1195 u8 reserved_at_30[0x8]; 1196 u8 log_max_memic_addr_alignment[0x8]; 1197 1198 u8 memic_bar_start_addr[0x40]; 1199 1200 u8 memic_bar_size[0x20]; 1201 1202 u8 max_memic_size[0x20]; 1203 1204 u8 steering_sw_icm_start_address[0x40]; 1205 1206 u8 reserved_at_100[0x8]; 1207 u8 log_header_modify_sw_icm_size[0x8]; 1208 u8 reserved_at_110[0x2]; 1209 u8 log_sw_icm_alloc_granularity[0x6]; 1210 u8 log_steering_sw_icm_size[0x8]; 1211 1212 u8 log_indirect_encap_sw_icm_size[0x8]; 1213 u8 reserved_at_128[0x10]; 1214 u8 log_header_modify_pattern_sw_icm_size[0x8]; 1215 1216 u8 header_modify_sw_icm_start_address[0x40]; 1217 1218 u8 reserved_at_180[0x40]; 1219 1220 u8 header_modify_pattern_sw_icm_start_address[0x40]; 1221 1222 u8 memic_operations[0x20]; 1223 1224 u8 reserved_at_220[0x20]; 1225 1226 u8 indirect_encap_sw_icm_start_address[0x40]; 1227 1228 u8 reserved_at_280[0x580]; 1229 }; 1230 1231 struct mlx5_ifc_device_event_cap_bits { 1232 u8 user_affiliated_events[4][0x40]; 1233 1234 u8 user_unaffiliated_events[4][0x40]; 1235 }; 1236 1237 struct mlx5_ifc_virtio_emulation_cap_bits { 1238 u8 desc_tunnel_offload_type[0x1]; 1239 u8 eth_frame_offload_type[0x1]; 1240 u8 virtio_version_1_0[0x1]; 1241 u8 device_features_bits_mask[0xd]; 1242 u8 event_mode[0x8]; 1243 u8 virtio_queue_type[0x8]; 1244 1245 u8 max_tunnel_desc[0x10]; 1246 u8 reserved_at_30[0x3]; 1247 u8 log_doorbell_stride[0x5]; 1248 u8 reserved_at_38[0x3]; 1249 u8 log_doorbell_bar_size[0x5]; 1250 1251 u8 doorbell_bar_offset[0x40]; 1252 1253 u8 max_emulated_devices[0x8]; 1254 u8 max_num_virtio_queues[0x18]; 1255 1256 u8 reserved_at_a0[0x20]; 1257 1258 u8 reserved_at_c0[0x13]; 1259 u8 desc_group_mkey_supported[0x1]; 1260 u8 freeze_to_rdy_supported[0x1]; 1261 u8 reserved_at_d5[0xb]; 1262 1263 u8 reserved_at_e0[0x20]; 1264 1265 u8 umem_1_buffer_param_a[0x20]; 1266 1267 u8 umem_1_buffer_param_b[0x20]; 1268 1269 u8 umem_2_buffer_param_a[0x20]; 1270 1271 u8 umem_2_buffer_param_b[0x20]; 1272 1273 u8 umem_3_buffer_param_a[0x20]; 1274 1275 u8 umem_3_buffer_param_b[0x20]; 1276 1277 u8 reserved_at_1c0[0x640]; 1278 }; 1279 1280 enum { 1281 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0, 1282 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2, 1283 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4, 1284 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8, 1285 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10, 1286 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20, 1287 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40, 1288 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80, 1289 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100, 1290 }; 1291 1292 enum { 1293 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1, 1294 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2, 1295 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4, 1296 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8, 1297 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10, 1298 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20, 1299 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40, 1300 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80, 1301 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100, 1302 }; 1303 1304 struct mlx5_ifc_atomic_caps_bits { 1305 u8 reserved_at_0[0x40]; 1306 1307 u8 atomic_req_8B_endianness_mode[0x2]; 1308 u8 reserved_at_42[0x4]; 1309 u8 supported_atomic_req_8B_endianness_mode_1[0x1]; 1310 1311 u8 reserved_at_47[0x19]; 1312 1313 u8 reserved_at_60[0x20]; 1314 1315 u8 reserved_at_80[0x10]; 1316 u8 atomic_operations[0x10]; 1317 1318 u8 reserved_at_a0[0x10]; 1319 u8 atomic_size_qp[0x10]; 1320 1321 u8 reserved_at_c0[0x10]; 1322 u8 atomic_size_dc[0x10]; 1323 1324 u8 reserved_at_e0[0x720]; 1325 }; 1326 1327 struct mlx5_ifc_odp_cap_bits { 1328 u8 reserved_at_0[0x40]; 1329 1330 u8 sig[0x1]; 1331 u8 reserved_at_41[0x1f]; 1332 1333 u8 reserved_at_60[0x20]; 1334 1335 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps; 1336 1337 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps; 1338 1339 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps; 1340 1341 struct mlx5_ifc_odp_per_transport_service_cap_bits xrc_odp_caps; 1342 1343 struct mlx5_ifc_odp_per_transport_service_cap_bits dc_odp_caps; 1344 1345 u8 reserved_at_120[0x6E0]; 1346 }; 1347 1348 struct mlx5_ifc_tls_cap_bits { 1349 u8 tls_1_2_aes_gcm_128[0x1]; 1350 u8 tls_1_3_aes_gcm_128[0x1]; 1351 u8 tls_1_2_aes_gcm_256[0x1]; 1352 u8 tls_1_3_aes_gcm_256[0x1]; 1353 u8 reserved_at_4[0x1c]; 1354 1355 u8 reserved_at_20[0x7e0]; 1356 }; 1357 1358 struct mlx5_ifc_ipsec_cap_bits { 1359 u8 ipsec_full_offload[0x1]; 1360 u8 ipsec_crypto_offload[0x1]; 1361 u8 ipsec_esn[0x1]; 1362 u8 ipsec_crypto_esp_aes_gcm_256_encrypt[0x1]; 1363 u8 ipsec_crypto_esp_aes_gcm_128_encrypt[0x1]; 1364 u8 ipsec_crypto_esp_aes_gcm_256_decrypt[0x1]; 1365 u8 ipsec_crypto_esp_aes_gcm_128_decrypt[0x1]; 1366 u8 reserved_at_7[0x4]; 1367 u8 log_max_ipsec_offload[0x5]; 1368 u8 reserved_at_10[0x10]; 1369 1370 u8 min_log_ipsec_full_replay_window[0x8]; 1371 u8 max_log_ipsec_full_replay_window[0x8]; 1372 u8 reserved_at_30[0x7d0]; 1373 }; 1374 1375 struct mlx5_ifc_macsec_cap_bits { 1376 u8 macsec_epn[0x1]; 1377 u8 reserved_at_1[0x2]; 1378 u8 macsec_crypto_esp_aes_gcm_256_encrypt[0x1]; 1379 u8 macsec_crypto_esp_aes_gcm_128_encrypt[0x1]; 1380 u8 macsec_crypto_esp_aes_gcm_256_decrypt[0x1]; 1381 u8 macsec_crypto_esp_aes_gcm_128_decrypt[0x1]; 1382 u8 reserved_at_7[0x4]; 1383 u8 log_max_macsec_offload[0x5]; 1384 u8 reserved_at_10[0x10]; 1385 1386 u8 min_log_macsec_full_replay_window[0x8]; 1387 u8 max_log_macsec_full_replay_window[0x8]; 1388 u8 reserved_at_30[0x10]; 1389 1390 u8 reserved_at_40[0x7c0]; 1391 }; 1392 1393 enum { 1394 MLX5_WQ_TYPE_LINKED_LIST = 0x0, 1395 MLX5_WQ_TYPE_CYCLIC = 0x1, 1396 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2, 1397 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3, 1398 }; 1399 1400 enum { 1401 MLX5_WQ_END_PAD_MODE_NONE = 0x0, 1402 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1, 1403 }; 1404 1405 enum { 1406 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0, 1407 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1, 1408 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2, 1409 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3, 1410 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4, 1411 }; 1412 1413 enum { 1414 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0, 1415 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1, 1416 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2, 1417 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3, 1418 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4, 1419 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5, 1420 }; 1421 1422 enum { 1423 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0, 1424 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1, 1425 }; 1426 1427 enum { 1428 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0, 1429 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1, 1430 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3, 1431 }; 1432 1433 enum { 1434 MLX5_CAP_PORT_TYPE_IB = 0x0, 1435 MLX5_CAP_PORT_TYPE_ETH = 0x1, 1436 }; 1437 1438 enum { 1439 MLX5_CAP_UMR_FENCE_STRONG = 0x0, 1440 MLX5_CAP_UMR_FENCE_SMALL = 0x1, 1441 MLX5_CAP_UMR_FENCE_NONE = 0x2, 1442 }; 1443 1444 enum { 1445 MLX5_FLEX_PARSER_GENEVE_ENABLED = 1 << 3, 1446 MLX5_FLEX_PARSER_MPLS_OVER_GRE_ENABLED = 1 << 4, 1447 MLX5_FLEX_PARSER_MPLS_OVER_UDP_ENABLED = 1 << 5, 1448 MLX5_FLEX_PARSER_VXLAN_GPE_ENABLED = 1 << 7, 1449 MLX5_FLEX_PARSER_ICMP_V4_ENABLED = 1 << 8, 1450 MLX5_FLEX_PARSER_ICMP_V6_ENABLED = 1 << 9, 1451 MLX5_FLEX_PARSER_GENEVE_TLV_OPTION_0_ENABLED = 1 << 10, 1452 MLX5_FLEX_PARSER_GTPU_ENABLED = 1 << 11, 1453 MLX5_FLEX_PARSER_GTPU_DW_2_ENABLED = 1 << 16, 1454 MLX5_FLEX_PARSER_GTPU_FIRST_EXT_DW_0_ENABLED = 1 << 17, 1455 MLX5_FLEX_PARSER_GTPU_DW_0_ENABLED = 1 << 18, 1456 MLX5_FLEX_PARSER_GTPU_TEID_ENABLED = 1 << 19, 1457 }; 1458 1459 enum { 1460 MLX5_UCTX_CAP_RAW_TX = 1UL << 0, 1461 MLX5_UCTX_CAP_INTERNAL_DEV_RES = 1UL << 1, 1462 }; 1463 1464 #define MLX5_FC_BULK_SIZE_FACTOR 128 1465 1466 enum mlx5_fc_bulk_alloc_bitmask { 1467 MLX5_FC_BULK_128 = (1 << 0), 1468 MLX5_FC_BULK_256 = (1 << 1), 1469 MLX5_FC_BULK_512 = (1 << 2), 1470 MLX5_FC_BULK_1024 = (1 << 3), 1471 MLX5_FC_BULK_2048 = (1 << 4), 1472 MLX5_FC_BULK_4096 = (1 << 5), 1473 MLX5_FC_BULK_8192 = (1 << 6), 1474 MLX5_FC_BULK_16384 = (1 << 7), 1475 }; 1476 1477 #define MLX5_FC_BULK_NUM_FCS(fc_enum) (MLX5_FC_BULK_SIZE_FACTOR * (fc_enum)) 1478 1479 #define MLX5_FT_MAX_MULTIPATH_LEVEL 63 1480 1481 enum { 1482 MLX5_STEERING_FORMAT_CONNECTX_5 = 0, 1483 MLX5_STEERING_FORMAT_CONNECTX_6DX = 1, 1484 MLX5_STEERING_FORMAT_CONNECTX_7 = 2, 1485 }; 1486 1487 struct mlx5_ifc_cmd_hca_cap_bits { 1488 u8 reserved_at_0[0x6]; 1489 u8 page_request_disable[0x1]; 1490 u8 reserved_at_7[0x9]; 1491 u8 shared_object_to_user_object_allowed[0x1]; 1492 u8 reserved_at_13[0xe]; 1493 u8 vhca_resource_manager[0x1]; 1494 1495 u8 hca_cap_2[0x1]; 1496 u8 create_lag_when_not_master_up[0x1]; 1497 u8 dtor[0x1]; 1498 u8 event_on_vhca_state_teardown_request[0x1]; 1499 u8 event_on_vhca_state_in_use[0x1]; 1500 u8 event_on_vhca_state_active[0x1]; 1501 u8 event_on_vhca_state_allocated[0x1]; 1502 u8 event_on_vhca_state_invalid[0x1]; 1503 u8 reserved_at_28[0x8]; 1504 u8 vhca_id[0x10]; 1505 1506 u8 reserved_at_40[0x40]; 1507 1508 u8 log_max_srq_sz[0x8]; 1509 u8 log_max_qp_sz[0x8]; 1510 u8 event_cap[0x1]; 1511 u8 reserved_at_91[0x2]; 1512 u8 isolate_vl_tc_new[0x1]; 1513 u8 reserved_at_94[0x4]; 1514 u8 prio_tag_required[0x1]; 1515 u8 reserved_at_99[0x2]; 1516 u8 log_max_qp[0x5]; 1517 1518 u8 reserved_at_a0[0x3]; 1519 u8 ece_support[0x1]; 1520 u8 reserved_at_a4[0x5]; 1521 u8 reg_c_preserve[0x1]; 1522 u8 reserved_at_aa[0x1]; 1523 u8 log_max_srq[0x5]; 1524 u8 reserved_at_b0[0x1]; 1525 u8 uplink_follow[0x1]; 1526 u8 ts_cqe_to_dest_cqn[0x1]; 1527 u8 reserved_at_b3[0x6]; 1528 u8 go_back_n[0x1]; 1529 u8 shampo[0x1]; 1530 u8 reserved_at_bb[0x5]; 1531 1532 u8 max_sgl_for_optimized_performance[0x8]; 1533 u8 log_max_cq_sz[0x8]; 1534 u8 relaxed_ordering_write_umr[0x1]; 1535 u8 relaxed_ordering_read_umr[0x1]; 1536 u8 reserved_at_d2[0x7]; 1537 u8 virtio_net_device_emualtion_manager[0x1]; 1538 u8 virtio_blk_device_emualtion_manager[0x1]; 1539 u8 log_max_cq[0x5]; 1540 1541 u8 log_max_eq_sz[0x8]; 1542 u8 relaxed_ordering_write[0x1]; 1543 u8 relaxed_ordering_read_pci_enabled[0x1]; 1544 u8 log_max_mkey[0x6]; 1545 u8 reserved_at_f0[0x6]; 1546 u8 terminate_scatter_list_mkey[0x1]; 1547 u8 repeated_mkey[0x1]; 1548 u8 dump_fill_mkey[0x1]; 1549 u8 reserved_at_f9[0x2]; 1550 u8 fast_teardown[0x1]; 1551 u8 log_max_eq[0x4]; 1552 1553 u8 max_indirection[0x8]; 1554 u8 fixed_buffer_size[0x1]; 1555 u8 log_max_mrw_sz[0x7]; 1556 u8 force_teardown[0x1]; 1557 u8 reserved_at_111[0x1]; 1558 u8 log_max_bsf_list_size[0x6]; 1559 u8 umr_extended_translation_offset[0x1]; 1560 u8 null_mkey[0x1]; 1561 u8 log_max_klm_list_size[0x6]; 1562 1563 u8 reserved_at_120[0x2]; 1564 u8 qpc_extension[0x1]; 1565 u8 reserved_at_123[0x7]; 1566 u8 log_max_ra_req_dc[0x6]; 1567 u8 reserved_at_130[0x2]; 1568 u8 eth_wqe_too_small[0x1]; 1569 u8 reserved_at_133[0x6]; 1570 u8 vnic_env_cq_overrun[0x1]; 1571 u8 log_max_ra_res_dc[0x6]; 1572 1573 u8 reserved_at_140[0x5]; 1574 u8 release_all_pages[0x1]; 1575 u8 must_not_use[0x1]; 1576 u8 reserved_at_147[0x2]; 1577 u8 roce_accl[0x1]; 1578 u8 log_max_ra_req_qp[0x6]; 1579 u8 reserved_at_150[0xa]; 1580 u8 log_max_ra_res_qp[0x6]; 1581 1582 u8 end_pad[0x1]; 1583 u8 cc_query_allowed[0x1]; 1584 u8 cc_modify_allowed[0x1]; 1585 u8 start_pad[0x1]; 1586 u8 cache_line_128byte[0x1]; 1587 u8 reserved_at_165[0x4]; 1588 u8 rts2rts_qp_counters_set_id[0x1]; 1589 u8 reserved_at_16a[0x2]; 1590 u8 vnic_env_int_rq_oob[0x1]; 1591 u8 sbcam_reg[0x1]; 1592 u8 reserved_at_16e[0x1]; 1593 u8 qcam_reg[0x1]; 1594 u8 gid_table_size[0x10]; 1595 1596 u8 out_of_seq_cnt[0x1]; 1597 u8 vport_counters[0x1]; 1598 u8 retransmission_q_counters[0x1]; 1599 u8 debug[0x1]; 1600 u8 modify_rq_counter_set_id[0x1]; 1601 u8 rq_delay_drop[0x1]; 1602 u8 max_qp_cnt[0xa]; 1603 u8 pkey_table_size[0x10]; 1604 1605 u8 vport_group_manager[0x1]; 1606 u8 vhca_group_manager[0x1]; 1607 u8 ib_virt[0x1]; 1608 u8 eth_virt[0x1]; 1609 u8 vnic_env_queue_counters[0x1]; 1610 u8 ets[0x1]; 1611 u8 nic_flow_table[0x1]; 1612 u8 eswitch_manager[0x1]; 1613 u8 device_memory[0x1]; 1614 u8 mcam_reg[0x1]; 1615 u8 pcam_reg[0x1]; 1616 u8 local_ca_ack_delay[0x5]; 1617 u8 port_module_event[0x1]; 1618 u8 enhanced_error_q_counters[0x1]; 1619 u8 ports_check[0x1]; 1620 u8 reserved_at_1b3[0x1]; 1621 u8 disable_link_up[0x1]; 1622 u8 beacon_led[0x1]; 1623 u8 port_type[0x2]; 1624 u8 num_ports[0x8]; 1625 1626 u8 reserved_at_1c0[0x1]; 1627 u8 pps[0x1]; 1628 u8 pps_modify[0x1]; 1629 u8 log_max_msg[0x5]; 1630 u8 reserved_at_1c8[0x4]; 1631 u8 max_tc[0x4]; 1632 u8 temp_warn_event[0x1]; 1633 u8 dcbx[0x1]; 1634 u8 general_notification_event[0x1]; 1635 u8 reserved_at_1d3[0x2]; 1636 u8 fpga[0x1]; 1637 u8 rol_s[0x1]; 1638 u8 rol_g[0x1]; 1639 u8 reserved_at_1d8[0x1]; 1640 u8 wol_s[0x1]; 1641 u8 wol_g[0x1]; 1642 u8 wol_a[0x1]; 1643 u8 wol_b[0x1]; 1644 u8 wol_m[0x1]; 1645 u8 wol_u[0x1]; 1646 u8 wol_p[0x1]; 1647 1648 u8 stat_rate_support[0x10]; 1649 u8 reserved_at_1f0[0x1]; 1650 u8 pci_sync_for_fw_update_event[0x1]; 1651 u8 reserved_at_1f2[0x6]; 1652 u8 init2_lag_tx_port_affinity[0x1]; 1653 u8 reserved_at_1fa[0x3]; 1654 u8 cqe_version[0x4]; 1655 1656 u8 compact_address_vector[0x1]; 1657 u8 striding_rq[0x1]; 1658 u8 reserved_at_202[0x1]; 1659 u8 ipoib_enhanced_offloads[0x1]; 1660 u8 ipoib_basic_offloads[0x1]; 1661 u8 reserved_at_205[0x1]; 1662 u8 repeated_block_disabled[0x1]; 1663 u8 umr_modify_entity_size_disabled[0x1]; 1664 u8 umr_modify_atomic_disabled[0x1]; 1665 u8 umr_indirect_mkey_disabled[0x1]; 1666 u8 umr_fence[0x2]; 1667 u8 dc_req_scat_data_cqe[0x1]; 1668 u8 reserved_at_20d[0x2]; 1669 u8 drain_sigerr[0x1]; 1670 u8 cmdif_checksum[0x2]; 1671 u8 sigerr_cqe[0x1]; 1672 u8 reserved_at_213[0x1]; 1673 u8 wq_signature[0x1]; 1674 u8 sctr_data_cqe[0x1]; 1675 u8 reserved_at_216[0x1]; 1676 u8 sho[0x1]; 1677 u8 tph[0x1]; 1678 u8 rf[0x1]; 1679 u8 dct[0x1]; 1680 u8 qos[0x1]; 1681 u8 eth_net_offloads[0x1]; 1682 u8 roce[0x1]; 1683 u8 atomic[0x1]; 1684 u8 reserved_at_21f[0x1]; 1685 1686 u8 cq_oi[0x1]; 1687 u8 cq_resize[0x1]; 1688 u8 cq_moderation[0x1]; 1689 u8 cq_period_mode_modify[0x1]; 1690 u8 reserved_at_224[0x2]; 1691 u8 cq_eq_remap[0x1]; 1692 u8 pg[0x1]; 1693 u8 block_lb_mc[0x1]; 1694 u8 reserved_at_229[0x1]; 1695 u8 scqe_break_moderation[0x1]; 1696 u8 cq_period_start_from_cqe[0x1]; 1697 u8 cd[0x1]; 1698 u8 reserved_at_22d[0x1]; 1699 u8 apm[0x1]; 1700 u8 vector_calc[0x1]; 1701 u8 umr_ptr_rlky[0x1]; 1702 u8 imaicl[0x1]; 1703 u8 qp_packet_based[0x1]; 1704 u8 reserved_at_233[0x3]; 1705 u8 qkv[0x1]; 1706 u8 pkv[0x1]; 1707 u8 set_deth_sqpn[0x1]; 1708 u8 reserved_at_239[0x3]; 1709 u8 xrc[0x1]; 1710 u8 ud[0x1]; 1711 u8 uc[0x1]; 1712 u8 rc[0x1]; 1713 1714 u8 uar_4k[0x1]; 1715 u8 reserved_at_241[0x7]; 1716 u8 fl_rc_qp_when_roce_disabled[0x1]; 1717 u8 regexp_params[0x1]; 1718 u8 uar_sz[0x6]; 1719 u8 port_selection_cap[0x1]; 1720 u8 reserved_at_251[0x1]; 1721 u8 umem_uid_0[0x1]; 1722 u8 reserved_at_253[0x5]; 1723 u8 log_pg_sz[0x8]; 1724 1725 u8 bf[0x1]; 1726 u8 driver_version[0x1]; 1727 u8 pad_tx_eth_packet[0x1]; 1728 u8 reserved_at_263[0x3]; 1729 u8 mkey_by_name[0x1]; 1730 u8 reserved_at_267[0x4]; 1731 1732 u8 log_bf_reg_size[0x5]; 1733 1734 u8 reserved_at_270[0x3]; 1735 u8 qp_error_syndrome[0x1]; 1736 u8 reserved_at_274[0x2]; 1737 u8 lag_dct[0x2]; 1738 u8 lag_tx_port_affinity[0x1]; 1739 u8 lag_native_fdb_selection[0x1]; 1740 u8 reserved_at_27a[0x1]; 1741 u8 lag_master[0x1]; 1742 u8 num_lag_ports[0x4]; 1743 1744 u8 reserved_at_280[0x10]; 1745 u8 max_wqe_sz_sq[0x10]; 1746 1747 u8 reserved_at_2a0[0x10]; 1748 u8 max_wqe_sz_rq[0x10]; 1749 1750 u8 max_flow_counter_31_16[0x10]; 1751 u8 max_wqe_sz_sq_dc[0x10]; 1752 1753 u8 reserved_at_2e0[0x7]; 1754 u8 max_qp_mcg[0x19]; 1755 1756 u8 reserved_at_300[0x10]; 1757 u8 flow_counter_bulk_alloc[0x8]; 1758 u8 log_max_mcg[0x8]; 1759 1760 u8 reserved_at_320[0x3]; 1761 u8 log_max_transport_domain[0x5]; 1762 u8 reserved_at_328[0x2]; 1763 u8 relaxed_ordering_read[0x1]; 1764 u8 log_max_pd[0x5]; 1765 u8 reserved_at_330[0x6]; 1766 u8 pci_sync_for_fw_update_with_driver_unload[0x1]; 1767 u8 vnic_env_cnt_steering_fail[0x1]; 1768 u8 vport_counter_local_loopback[0x1]; 1769 u8 q_counter_aggregation[0x1]; 1770 u8 q_counter_other_vport[0x1]; 1771 u8 log_max_xrcd[0x5]; 1772 1773 u8 nic_receive_steering_discard[0x1]; 1774 u8 receive_discard_vport_down[0x1]; 1775 u8 transmit_discard_vport_down[0x1]; 1776 u8 eq_overrun_count[0x1]; 1777 u8 reserved_at_344[0x1]; 1778 u8 invalid_command_count[0x1]; 1779 u8 quota_exceeded_count[0x1]; 1780 u8 reserved_at_347[0x1]; 1781 u8 log_max_flow_counter_bulk[0x8]; 1782 u8 max_flow_counter_15_0[0x10]; 1783 1784 1785 u8 reserved_at_360[0x3]; 1786 u8 log_max_rq[0x5]; 1787 u8 reserved_at_368[0x3]; 1788 u8 log_max_sq[0x5]; 1789 u8 reserved_at_370[0x3]; 1790 u8 log_max_tir[0x5]; 1791 u8 reserved_at_378[0x3]; 1792 u8 log_max_tis[0x5]; 1793 1794 u8 basic_cyclic_rcv_wqe[0x1]; 1795 u8 reserved_at_381[0x2]; 1796 u8 log_max_rmp[0x5]; 1797 u8 reserved_at_388[0x3]; 1798 u8 log_max_rqt[0x5]; 1799 u8 reserved_at_390[0x3]; 1800 u8 log_max_rqt_size[0x5]; 1801 u8 reserved_at_398[0x3]; 1802 u8 log_max_tis_per_sq[0x5]; 1803 1804 u8 ext_stride_num_range[0x1]; 1805 u8 roce_rw_supported[0x1]; 1806 u8 log_max_current_uc_list_wr_supported[0x1]; 1807 u8 log_max_stride_sz_rq[0x5]; 1808 u8 reserved_at_3a8[0x3]; 1809 u8 log_min_stride_sz_rq[0x5]; 1810 u8 reserved_at_3b0[0x3]; 1811 u8 log_max_stride_sz_sq[0x5]; 1812 u8 reserved_at_3b8[0x3]; 1813 u8 log_min_stride_sz_sq[0x5]; 1814 1815 u8 hairpin[0x1]; 1816 u8 reserved_at_3c1[0x2]; 1817 u8 log_max_hairpin_queues[0x5]; 1818 u8 reserved_at_3c8[0x3]; 1819 u8 log_max_hairpin_wq_data_sz[0x5]; 1820 u8 reserved_at_3d0[0x3]; 1821 u8 log_max_hairpin_num_packets[0x5]; 1822 u8 reserved_at_3d8[0x3]; 1823 u8 log_max_wq_sz[0x5]; 1824 1825 u8 nic_vport_change_event[0x1]; 1826 u8 disable_local_lb_uc[0x1]; 1827 u8 disable_local_lb_mc[0x1]; 1828 u8 log_min_hairpin_wq_data_sz[0x5]; 1829 u8 reserved_at_3e8[0x1]; 1830 u8 silent_mode[0x1]; 1831 u8 vhca_state[0x1]; 1832 u8 log_max_vlan_list[0x5]; 1833 u8 reserved_at_3f0[0x3]; 1834 u8 log_max_current_mc_list[0x5]; 1835 u8 reserved_at_3f8[0x3]; 1836 u8 log_max_current_uc_list[0x5]; 1837 1838 u8 general_obj_types[0x40]; 1839 1840 u8 sq_ts_format[0x2]; 1841 u8 rq_ts_format[0x2]; 1842 u8 steering_format_version[0x4]; 1843 u8 create_qp_start_hint[0x18]; 1844 1845 u8 reserved_at_460[0x1]; 1846 u8 ats[0x1]; 1847 u8 cross_vhca_rqt[0x1]; 1848 u8 log_max_uctx[0x5]; 1849 u8 reserved_at_468[0x1]; 1850 u8 crypto[0x1]; 1851 u8 ipsec_offload[0x1]; 1852 u8 log_max_umem[0x5]; 1853 u8 max_num_eqs[0x10]; 1854 1855 u8 reserved_at_480[0x1]; 1856 u8 tls_tx[0x1]; 1857 u8 tls_rx[0x1]; 1858 u8 log_max_l2_table[0x5]; 1859 u8 reserved_at_488[0x8]; 1860 u8 log_uar_page_sz[0x10]; 1861 1862 u8 reserved_at_4a0[0x20]; 1863 u8 device_frequency_mhz[0x20]; 1864 u8 device_frequency_khz[0x20]; 1865 1866 u8 reserved_at_500[0x20]; 1867 u8 num_of_uars_per_page[0x20]; 1868 1869 u8 flex_parser_protocols[0x20]; 1870 1871 u8 max_geneve_tlv_options[0x8]; 1872 u8 reserved_at_568[0x3]; 1873 u8 max_geneve_tlv_option_data_len[0x5]; 1874 u8 reserved_at_570[0x9]; 1875 u8 adv_virtualization[0x1]; 1876 u8 reserved_at_57a[0x6]; 1877 1878 u8 reserved_at_580[0xb]; 1879 u8 log_max_dci_stream_channels[0x5]; 1880 u8 reserved_at_590[0x3]; 1881 u8 log_max_dci_errored_streams[0x5]; 1882 u8 reserved_at_598[0x8]; 1883 1884 u8 reserved_at_5a0[0x10]; 1885 u8 enhanced_cqe_compression[0x1]; 1886 u8 reserved_at_5b1[0x2]; 1887 u8 log_max_dek[0x5]; 1888 u8 reserved_at_5b8[0x4]; 1889 u8 mini_cqe_resp_stride_index[0x1]; 1890 u8 cqe_128_always[0x1]; 1891 u8 cqe_compression_128[0x1]; 1892 u8 cqe_compression[0x1]; 1893 1894 u8 cqe_compression_timeout[0x10]; 1895 u8 cqe_compression_max_num[0x10]; 1896 1897 u8 reserved_at_5e0[0x8]; 1898 u8 flex_parser_id_gtpu_dw_0[0x4]; 1899 u8 reserved_at_5ec[0x4]; 1900 u8 tag_matching[0x1]; 1901 u8 rndv_offload_rc[0x1]; 1902 u8 rndv_offload_dc[0x1]; 1903 u8 log_tag_matching_list_sz[0x5]; 1904 u8 reserved_at_5f8[0x3]; 1905 u8 log_max_xrq[0x5]; 1906 1907 u8 affiliate_nic_vport_criteria[0x8]; 1908 u8 native_port_num[0x8]; 1909 u8 num_vhca_ports[0x8]; 1910 u8 flex_parser_id_gtpu_teid[0x4]; 1911 u8 reserved_at_61c[0x2]; 1912 u8 sw_owner_id[0x1]; 1913 u8 reserved_at_61f[0x1]; 1914 1915 u8 max_num_of_monitor_counters[0x10]; 1916 u8 num_ppcnt_monitor_counters[0x10]; 1917 1918 u8 max_num_sf[0x10]; 1919 u8 num_q_monitor_counters[0x10]; 1920 1921 u8 reserved_at_660[0x20]; 1922 1923 u8 sf[0x1]; 1924 u8 sf_set_partition[0x1]; 1925 u8 reserved_at_682[0x1]; 1926 u8 log_max_sf[0x5]; 1927 u8 apu[0x1]; 1928 u8 reserved_at_689[0x4]; 1929 u8 migration[0x1]; 1930 u8 reserved_at_68e[0x2]; 1931 u8 log_min_sf_size[0x8]; 1932 u8 max_num_sf_partitions[0x8]; 1933 1934 u8 uctx_cap[0x20]; 1935 1936 u8 reserved_at_6c0[0x4]; 1937 u8 flex_parser_id_geneve_tlv_option_0[0x4]; 1938 u8 flex_parser_id_icmp_dw1[0x4]; 1939 u8 flex_parser_id_icmp_dw0[0x4]; 1940 u8 flex_parser_id_icmpv6_dw1[0x4]; 1941 u8 flex_parser_id_icmpv6_dw0[0x4]; 1942 u8 flex_parser_id_outer_first_mpls_over_gre[0x4]; 1943 u8 flex_parser_id_outer_first_mpls_over_udp_label[0x4]; 1944 1945 u8 max_num_match_definer[0x10]; 1946 u8 sf_base_id[0x10]; 1947 1948 u8 flex_parser_id_gtpu_dw_2[0x4]; 1949 u8 flex_parser_id_gtpu_first_ext_dw_0[0x4]; 1950 u8 num_total_dynamic_vf_msix[0x18]; 1951 u8 reserved_at_720[0x14]; 1952 u8 dynamic_msix_table_size[0xc]; 1953 u8 reserved_at_740[0xc]; 1954 u8 min_dynamic_vf_msix_table_size[0x4]; 1955 u8 reserved_at_750[0x4]; 1956 u8 max_dynamic_vf_msix_table_size[0xc]; 1957 1958 u8 reserved_at_760[0x3]; 1959 u8 log_max_num_header_modify_argument[0x5]; 1960 u8 reserved_at_768[0x4]; 1961 u8 log_header_modify_argument_granularity[0x4]; 1962 u8 reserved_at_770[0x3]; 1963 u8 log_header_modify_argument_max_alloc[0x5]; 1964 u8 reserved_at_778[0x8]; 1965 1966 u8 vhca_tunnel_commands[0x40]; 1967 u8 match_definer_format_supported[0x40]; 1968 }; 1969 1970 enum { 1971 MLX5_CROSS_VHCA_OBJ_TO_OBJ_SUPPORTED_LOCAL_FLOW_TABLE_TO_REMOTE_FLOW_TABLE_MISS = 0x80000, 1972 MLX5_CROSS_VHCA_OBJ_TO_OBJ_SUPPORTED_LOCAL_FLOW_TABLE_ROOT_TO_REMOTE_FLOW_TABLE = (1ULL << 20), 1973 }; 1974 1975 enum { 1976 MLX5_ALLOWED_OBJ_FOR_OTHER_VHCA_ACCESS_FLOW_TABLE = 0x200, 1977 }; 1978 1979 struct mlx5_ifc_cmd_hca_cap_2_bits { 1980 u8 reserved_at_0[0x80]; 1981 1982 u8 migratable[0x1]; 1983 u8 reserved_at_81[0x1f]; 1984 1985 u8 max_reformat_insert_size[0x8]; 1986 u8 max_reformat_insert_offset[0x8]; 1987 u8 max_reformat_remove_size[0x8]; 1988 u8 max_reformat_remove_offset[0x8]; 1989 1990 u8 reserved_at_c0[0x8]; 1991 u8 migration_multi_load[0x1]; 1992 u8 migration_tracking_state[0x1]; 1993 u8 reserved_at_ca[0x6]; 1994 u8 migration_in_chunks[0x1]; 1995 u8 reserved_at_d1[0xf]; 1996 1997 u8 cross_vhca_object_to_object_supported[0x20]; 1998 1999 u8 allowed_object_for_other_vhca_access[0x40]; 2000 2001 u8 reserved_at_140[0x60]; 2002 2003 u8 flow_table_type_2_type[0x8]; 2004 u8 reserved_at_1a8[0x3]; 2005 u8 log_min_mkey_entity_size[0x5]; 2006 u8 reserved_at_1b0[0x10]; 2007 2008 u8 reserved_at_1c0[0x60]; 2009 2010 u8 reserved_at_220[0x1]; 2011 u8 sw_vhca_id_valid[0x1]; 2012 u8 sw_vhca_id[0xe]; 2013 u8 reserved_at_230[0x10]; 2014 2015 u8 reserved_at_240[0xb]; 2016 u8 ts_cqe_metadata_size2wqe_counter[0x5]; 2017 u8 reserved_at_250[0x10]; 2018 2019 u8 reserved_at_260[0x120]; 2020 u8 reserved_at_380[0x10]; 2021 u8 ec_vf_vport_base[0x10]; 2022 2023 u8 reserved_at_3a0[0x10]; 2024 u8 max_rqt_vhca_id[0x10]; 2025 2026 u8 reserved_at_3c0[0x20]; 2027 2028 u8 reserved_at_3e0[0x10]; 2029 u8 pcc_ifa2[0x1]; 2030 u8 reserved_at_3f1[0xf]; 2031 2032 u8 reserved_at_400[0x400]; 2033 }; 2034 2035 enum mlx5_ifc_flow_destination_type { 2036 MLX5_IFC_FLOW_DESTINATION_TYPE_VPORT = 0x0, 2037 MLX5_IFC_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1, 2038 MLX5_IFC_FLOW_DESTINATION_TYPE_TIR = 0x2, 2039 MLX5_IFC_FLOW_DESTINATION_TYPE_FLOW_SAMPLER = 0x6, 2040 MLX5_IFC_FLOW_DESTINATION_TYPE_UPLINK = 0x8, 2041 MLX5_IFC_FLOW_DESTINATION_TYPE_TABLE_TYPE = 0xA, 2042 }; 2043 2044 enum mlx5_flow_table_miss_action { 2045 MLX5_FLOW_TABLE_MISS_ACTION_DEF, 2046 MLX5_FLOW_TABLE_MISS_ACTION_FWD, 2047 MLX5_FLOW_TABLE_MISS_ACTION_SWITCH_DOMAIN, 2048 }; 2049 2050 struct mlx5_ifc_dest_format_struct_bits { 2051 u8 destination_type[0x8]; 2052 u8 destination_id[0x18]; 2053 2054 u8 destination_eswitch_owner_vhca_id_valid[0x1]; 2055 u8 packet_reformat[0x1]; 2056 u8 reserved_at_22[0x6]; 2057 u8 destination_table_type[0x8]; 2058 u8 destination_eswitch_owner_vhca_id[0x10]; 2059 }; 2060 2061 struct mlx5_ifc_flow_counter_list_bits { 2062 u8 flow_counter_id[0x20]; 2063 2064 u8 reserved_at_20[0x20]; 2065 }; 2066 2067 struct mlx5_ifc_extended_dest_format_bits { 2068 struct mlx5_ifc_dest_format_struct_bits destination_entry; 2069 2070 u8 packet_reformat_id[0x20]; 2071 2072 u8 reserved_at_60[0x20]; 2073 }; 2074 2075 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits { 2076 struct mlx5_ifc_extended_dest_format_bits extended_dest_format; 2077 struct mlx5_ifc_flow_counter_list_bits flow_counter_list; 2078 }; 2079 2080 struct mlx5_ifc_fte_match_param_bits { 2081 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers; 2082 2083 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters; 2084 2085 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers; 2086 2087 struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2; 2088 2089 struct mlx5_ifc_fte_match_set_misc3_bits misc_parameters_3; 2090 2091 struct mlx5_ifc_fte_match_set_misc4_bits misc_parameters_4; 2092 2093 struct mlx5_ifc_fte_match_set_misc5_bits misc_parameters_5; 2094 2095 u8 reserved_at_e00[0x200]; 2096 }; 2097 2098 enum { 2099 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0, 2100 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1, 2101 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2, 2102 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3, 2103 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4, 2104 }; 2105 2106 struct mlx5_ifc_rx_hash_field_select_bits { 2107 u8 l3_prot_type[0x1]; 2108 u8 l4_prot_type[0x1]; 2109 u8 selected_fields[0x1e]; 2110 }; 2111 2112 enum { 2113 MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0, 2114 MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1, 2115 }; 2116 2117 enum { 2118 MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0, 2119 MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1, 2120 }; 2121 2122 struct mlx5_ifc_wq_bits { 2123 u8 wq_type[0x4]; 2124 u8 wq_signature[0x1]; 2125 u8 end_padding_mode[0x2]; 2126 u8 cd_slave[0x1]; 2127 u8 reserved_at_8[0x18]; 2128 2129 u8 hds_skip_first_sge[0x1]; 2130 u8 log2_hds_buf_size[0x3]; 2131 u8 reserved_at_24[0x7]; 2132 u8 page_offset[0x5]; 2133 u8 lwm[0x10]; 2134 2135 u8 reserved_at_40[0x8]; 2136 u8 pd[0x18]; 2137 2138 u8 reserved_at_60[0x8]; 2139 u8 uar_page[0x18]; 2140 2141 u8 dbr_addr[0x40]; 2142 2143 u8 hw_counter[0x20]; 2144 2145 u8 sw_counter[0x20]; 2146 2147 u8 reserved_at_100[0xc]; 2148 u8 log_wq_stride[0x4]; 2149 u8 reserved_at_110[0x3]; 2150 u8 log_wq_pg_sz[0x5]; 2151 u8 reserved_at_118[0x3]; 2152 u8 log_wq_sz[0x5]; 2153 2154 u8 dbr_umem_valid[0x1]; 2155 u8 wq_umem_valid[0x1]; 2156 u8 reserved_at_122[0x1]; 2157 u8 log_hairpin_num_packets[0x5]; 2158 u8 reserved_at_128[0x3]; 2159 u8 log_hairpin_data_sz[0x5]; 2160 2161 u8 reserved_at_130[0x4]; 2162 u8 log_wqe_num_of_strides[0x4]; 2163 u8 two_byte_shift_en[0x1]; 2164 u8 reserved_at_139[0x4]; 2165 u8 log_wqe_stride_size[0x3]; 2166 2167 u8 reserved_at_140[0x80]; 2168 2169 u8 headers_mkey[0x20]; 2170 2171 u8 shampo_enable[0x1]; 2172 u8 reserved_at_1e1[0x4]; 2173 u8 log_reservation_size[0x3]; 2174 u8 reserved_at_1e8[0x5]; 2175 u8 log_max_num_of_packets_per_reservation[0x3]; 2176 u8 reserved_at_1f0[0x6]; 2177 u8 log_headers_entry_size[0x2]; 2178 u8 reserved_at_1f8[0x4]; 2179 u8 log_headers_buffer_entry_num[0x4]; 2180 2181 u8 reserved_at_200[0x400]; 2182 2183 struct mlx5_ifc_cmd_pas_bits pas[]; 2184 }; 2185 2186 struct mlx5_ifc_rq_num_bits { 2187 u8 reserved_at_0[0x8]; 2188 u8 rq_num[0x18]; 2189 }; 2190 2191 struct mlx5_ifc_rq_vhca_bits { 2192 u8 reserved_at_0[0x8]; 2193 u8 rq_num[0x18]; 2194 u8 reserved_at_20[0x10]; 2195 u8 rq_vhca_id[0x10]; 2196 }; 2197 2198 struct mlx5_ifc_mac_address_layout_bits { 2199 u8 reserved_at_0[0x10]; 2200 u8 mac_addr_47_32[0x10]; 2201 2202 u8 mac_addr_31_0[0x20]; 2203 }; 2204 2205 struct mlx5_ifc_vlan_layout_bits { 2206 u8 reserved_at_0[0x14]; 2207 u8 vlan[0x0c]; 2208 2209 u8 reserved_at_20[0x20]; 2210 }; 2211 2212 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits { 2213 u8 reserved_at_0[0xa0]; 2214 2215 u8 min_time_between_cnps[0x20]; 2216 2217 u8 reserved_at_c0[0x12]; 2218 u8 cnp_dscp[0x6]; 2219 u8 reserved_at_d8[0x4]; 2220 u8 cnp_prio_mode[0x1]; 2221 u8 cnp_802p_prio[0x3]; 2222 2223 u8 reserved_at_e0[0x720]; 2224 }; 2225 2226 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits { 2227 u8 reserved_at_0[0x60]; 2228 2229 u8 reserved_at_60[0x4]; 2230 u8 clamp_tgt_rate[0x1]; 2231 u8 reserved_at_65[0x3]; 2232 u8 clamp_tgt_rate_after_time_inc[0x1]; 2233 u8 reserved_at_69[0x17]; 2234 2235 u8 reserved_at_80[0x20]; 2236 2237 u8 rpg_time_reset[0x20]; 2238 2239 u8 rpg_byte_reset[0x20]; 2240 2241 u8 rpg_threshold[0x20]; 2242 2243 u8 rpg_max_rate[0x20]; 2244 2245 u8 rpg_ai_rate[0x20]; 2246 2247 u8 rpg_hai_rate[0x20]; 2248 2249 u8 rpg_gd[0x20]; 2250 2251 u8 rpg_min_dec_fac[0x20]; 2252 2253 u8 rpg_min_rate[0x20]; 2254 2255 u8 reserved_at_1c0[0xe0]; 2256 2257 u8 rate_to_set_on_first_cnp[0x20]; 2258 2259 u8 dce_tcp_g[0x20]; 2260 2261 u8 dce_tcp_rtt[0x20]; 2262 2263 u8 rate_reduce_monitor_period[0x20]; 2264 2265 u8 reserved_at_320[0x20]; 2266 2267 u8 initial_alpha_value[0x20]; 2268 2269 u8 reserved_at_360[0x4a0]; 2270 }; 2271 2272 struct mlx5_ifc_cong_control_r_roce_general_bits { 2273 u8 reserved_at_0[0x80]; 2274 2275 u8 reserved_at_80[0x10]; 2276 u8 rtt_resp_dscp_valid[0x1]; 2277 u8 reserved_at_91[0x9]; 2278 u8 rtt_resp_dscp[0x6]; 2279 2280 u8 reserved_at_a0[0x760]; 2281 }; 2282 2283 struct mlx5_ifc_cong_control_802_1qau_rp_bits { 2284 u8 reserved_at_0[0x80]; 2285 2286 u8 rppp_max_rps[0x20]; 2287 2288 u8 rpg_time_reset[0x20]; 2289 2290 u8 rpg_byte_reset[0x20]; 2291 2292 u8 rpg_threshold[0x20]; 2293 2294 u8 rpg_max_rate[0x20]; 2295 2296 u8 rpg_ai_rate[0x20]; 2297 2298 u8 rpg_hai_rate[0x20]; 2299 2300 u8 rpg_gd[0x20]; 2301 2302 u8 rpg_min_dec_fac[0x20]; 2303 2304 u8 rpg_min_rate[0x20]; 2305 2306 u8 reserved_at_1c0[0x640]; 2307 }; 2308 2309 enum { 2310 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1, 2311 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2, 2312 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4, 2313 }; 2314 2315 struct mlx5_ifc_resize_field_select_bits { 2316 u8 resize_field_select[0x20]; 2317 }; 2318 2319 struct mlx5_ifc_resource_dump_bits { 2320 u8 more_dump[0x1]; 2321 u8 inline_dump[0x1]; 2322 u8 reserved_at_2[0xa]; 2323 u8 seq_num[0x4]; 2324 u8 segment_type[0x10]; 2325 2326 u8 reserved_at_20[0x10]; 2327 u8 vhca_id[0x10]; 2328 2329 u8 index1[0x20]; 2330 2331 u8 index2[0x20]; 2332 2333 u8 num_of_obj1[0x10]; 2334 u8 num_of_obj2[0x10]; 2335 2336 u8 reserved_at_a0[0x20]; 2337 2338 u8 device_opaque[0x40]; 2339 2340 u8 mkey[0x20]; 2341 2342 u8 size[0x20]; 2343 2344 u8 address[0x40]; 2345 2346 u8 inline_data[52][0x20]; 2347 }; 2348 2349 struct mlx5_ifc_resource_dump_menu_record_bits { 2350 u8 reserved_at_0[0x4]; 2351 u8 num_of_obj2_supports_active[0x1]; 2352 u8 num_of_obj2_supports_all[0x1]; 2353 u8 must_have_num_of_obj2[0x1]; 2354 u8 support_num_of_obj2[0x1]; 2355 u8 num_of_obj1_supports_active[0x1]; 2356 u8 num_of_obj1_supports_all[0x1]; 2357 u8 must_have_num_of_obj1[0x1]; 2358 u8 support_num_of_obj1[0x1]; 2359 u8 must_have_index2[0x1]; 2360 u8 support_index2[0x1]; 2361 u8 must_have_index1[0x1]; 2362 u8 support_index1[0x1]; 2363 u8 segment_type[0x10]; 2364 2365 u8 segment_name[4][0x20]; 2366 2367 u8 index1_name[4][0x20]; 2368 2369 u8 index2_name[4][0x20]; 2370 }; 2371 2372 struct mlx5_ifc_resource_dump_segment_header_bits { 2373 u8 length_dw[0x10]; 2374 u8 segment_type[0x10]; 2375 }; 2376 2377 struct mlx5_ifc_resource_dump_command_segment_bits { 2378 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2379 2380 u8 segment_called[0x10]; 2381 u8 vhca_id[0x10]; 2382 2383 u8 index1[0x20]; 2384 2385 u8 index2[0x20]; 2386 2387 u8 num_of_obj1[0x10]; 2388 u8 num_of_obj2[0x10]; 2389 }; 2390 2391 struct mlx5_ifc_resource_dump_error_segment_bits { 2392 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2393 2394 u8 reserved_at_20[0x10]; 2395 u8 syndrome_id[0x10]; 2396 2397 u8 reserved_at_40[0x40]; 2398 2399 u8 error[8][0x20]; 2400 }; 2401 2402 struct mlx5_ifc_resource_dump_info_segment_bits { 2403 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2404 2405 u8 reserved_at_20[0x18]; 2406 u8 dump_version[0x8]; 2407 2408 u8 hw_version[0x20]; 2409 2410 u8 fw_version[0x20]; 2411 }; 2412 2413 struct mlx5_ifc_resource_dump_menu_segment_bits { 2414 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2415 2416 u8 reserved_at_20[0x10]; 2417 u8 num_of_records[0x10]; 2418 2419 struct mlx5_ifc_resource_dump_menu_record_bits record[]; 2420 }; 2421 2422 struct mlx5_ifc_resource_dump_resource_segment_bits { 2423 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2424 2425 u8 reserved_at_20[0x20]; 2426 2427 u8 index1[0x20]; 2428 2429 u8 index2[0x20]; 2430 2431 u8 payload[][0x20]; 2432 }; 2433 2434 struct mlx5_ifc_resource_dump_terminate_segment_bits { 2435 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2436 }; 2437 2438 struct mlx5_ifc_menu_resource_dump_response_bits { 2439 struct mlx5_ifc_resource_dump_info_segment_bits info; 2440 struct mlx5_ifc_resource_dump_command_segment_bits cmd; 2441 struct mlx5_ifc_resource_dump_menu_segment_bits menu; 2442 struct mlx5_ifc_resource_dump_terminate_segment_bits terminate; 2443 }; 2444 2445 enum { 2446 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1, 2447 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2, 2448 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4, 2449 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8, 2450 }; 2451 2452 struct mlx5_ifc_modify_field_select_bits { 2453 u8 modify_field_select[0x20]; 2454 }; 2455 2456 struct mlx5_ifc_field_select_r_roce_np_bits { 2457 u8 field_select_r_roce_np[0x20]; 2458 }; 2459 2460 struct mlx5_ifc_field_select_r_roce_rp_bits { 2461 u8 field_select_r_roce_rp[0x20]; 2462 }; 2463 2464 enum { 2465 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4, 2466 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8, 2467 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10, 2468 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20, 2469 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40, 2470 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80, 2471 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100, 2472 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200, 2473 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400, 2474 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800, 2475 }; 2476 2477 struct mlx5_ifc_field_select_802_1qau_rp_bits { 2478 u8 field_select_8021qaurp[0x20]; 2479 }; 2480 2481 struct mlx5_ifc_phys_layer_cntrs_bits { 2482 u8 time_since_last_clear_high[0x20]; 2483 2484 u8 time_since_last_clear_low[0x20]; 2485 2486 u8 symbol_errors_high[0x20]; 2487 2488 u8 symbol_errors_low[0x20]; 2489 2490 u8 sync_headers_errors_high[0x20]; 2491 2492 u8 sync_headers_errors_low[0x20]; 2493 2494 u8 edpl_bip_errors_lane0_high[0x20]; 2495 2496 u8 edpl_bip_errors_lane0_low[0x20]; 2497 2498 u8 edpl_bip_errors_lane1_high[0x20]; 2499 2500 u8 edpl_bip_errors_lane1_low[0x20]; 2501 2502 u8 edpl_bip_errors_lane2_high[0x20]; 2503 2504 u8 edpl_bip_errors_lane2_low[0x20]; 2505 2506 u8 edpl_bip_errors_lane3_high[0x20]; 2507 2508 u8 edpl_bip_errors_lane3_low[0x20]; 2509 2510 u8 fc_fec_corrected_blocks_lane0_high[0x20]; 2511 2512 u8 fc_fec_corrected_blocks_lane0_low[0x20]; 2513 2514 u8 fc_fec_corrected_blocks_lane1_high[0x20]; 2515 2516 u8 fc_fec_corrected_blocks_lane1_low[0x20]; 2517 2518 u8 fc_fec_corrected_blocks_lane2_high[0x20]; 2519 2520 u8 fc_fec_corrected_blocks_lane2_low[0x20]; 2521 2522 u8 fc_fec_corrected_blocks_lane3_high[0x20]; 2523 2524 u8 fc_fec_corrected_blocks_lane3_low[0x20]; 2525 2526 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20]; 2527 2528 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20]; 2529 2530 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20]; 2531 2532 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20]; 2533 2534 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20]; 2535 2536 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20]; 2537 2538 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20]; 2539 2540 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20]; 2541 2542 u8 rs_fec_corrected_blocks_high[0x20]; 2543 2544 u8 rs_fec_corrected_blocks_low[0x20]; 2545 2546 u8 rs_fec_uncorrectable_blocks_high[0x20]; 2547 2548 u8 rs_fec_uncorrectable_blocks_low[0x20]; 2549 2550 u8 rs_fec_no_errors_blocks_high[0x20]; 2551 2552 u8 rs_fec_no_errors_blocks_low[0x20]; 2553 2554 u8 rs_fec_single_error_blocks_high[0x20]; 2555 2556 u8 rs_fec_single_error_blocks_low[0x20]; 2557 2558 u8 rs_fec_corrected_symbols_total_high[0x20]; 2559 2560 u8 rs_fec_corrected_symbols_total_low[0x20]; 2561 2562 u8 rs_fec_corrected_symbols_lane0_high[0x20]; 2563 2564 u8 rs_fec_corrected_symbols_lane0_low[0x20]; 2565 2566 u8 rs_fec_corrected_symbols_lane1_high[0x20]; 2567 2568 u8 rs_fec_corrected_symbols_lane1_low[0x20]; 2569 2570 u8 rs_fec_corrected_symbols_lane2_high[0x20]; 2571 2572 u8 rs_fec_corrected_symbols_lane2_low[0x20]; 2573 2574 u8 rs_fec_corrected_symbols_lane3_high[0x20]; 2575 2576 u8 rs_fec_corrected_symbols_lane3_low[0x20]; 2577 2578 u8 link_down_events[0x20]; 2579 2580 u8 successful_recovery_events[0x20]; 2581 2582 u8 reserved_at_640[0x180]; 2583 }; 2584 2585 struct mlx5_ifc_phys_layer_statistical_cntrs_bits { 2586 u8 time_since_last_clear_high[0x20]; 2587 2588 u8 time_since_last_clear_low[0x20]; 2589 2590 u8 phy_received_bits_high[0x20]; 2591 2592 u8 phy_received_bits_low[0x20]; 2593 2594 u8 phy_symbol_errors_high[0x20]; 2595 2596 u8 phy_symbol_errors_low[0x20]; 2597 2598 u8 phy_corrected_bits_high[0x20]; 2599 2600 u8 phy_corrected_bits_low[0x20]; 2601 2602 u8 phy_corrected_bits_lane0_high[0x20]; 2603 2604 u8 phy_corrected_bits_lane0_low[0x20]; 2605 2606 u8 phy_corrected_bits_lane1_high[0x20]; 2607 2608 u8 phy_corrected_bits_lane1_low[0x20]; 2609 2610 u8 phy_corrected_bits_lane2_high[0x20]; 2611 2612 u8 phy_corrected_bits_lane2_low[0x20]; 2613 2614 u8 phy_corrected_bits_lane3_high[0x20]; 2615 2616 u8 phy_corrected_bits_lane3_low[0x20]; 2617 2618 u8 reserved_at_200[0x5c0]; 2619 }; 2620 2621 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits { 2622 u8 symbol_error_counter[0x10]; 2623 2624 u8 link_error_recovery_counter[0x8]; 2625 2626 u8 link_downed_counter[0x8]; 2627 2628 u8 port_rcv_errors[0x10]; 2629 2630 u8 port_rcv_remote_physical_errors[0x10]; 2631 2632 u8 port_rcv_switch_relay_errors[0x10]; 2633 2634 u8 port_xmit_discards[0x10]; 2635 2636 u8 port_xmit_constraint_errors[0x8]; 2637 2638 u8 port_rcv_constraint_errors[0x8]; 2639 2640 u8 reserved_at_70[0x8]; 2641 2642 u8 link_overrun_errors[0x8]; 2643 2644 u8 reserved_at_80[0x10]; 2645 2646 u8 vl_15_dropped[0x10]; 2647 2648 u8 reserved_at_a0[0x80]; 2649 2650 u8 port_xmit_wait[0x20]; 2651 }; 2652 2653 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits { 2654 u8 transmit_queue_high[0x20]; 2655 2656 u8 transmit_queue_low[0x20]; 2657 2658 u8 no_buffer_discard_uc_high[0x20]; 2659 2660 u8 no_buffer_discard_uc_low[0x20]; 2661 2662 u8 reserved_at_80[0x740]; 2663 }; 2664 2665 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits { 2666 u8 wred_discard_high[0x20]; 2667 2668 u8 wred_discard_low[0x20]; 2669 2670 u8 ecn_marked_tc_high[0x20]; 2671 2672 u8 ecn_marked_tc_low[0x20]; 2673 2674 u8 reserved_at_80[0x740]; 2675 }; 2676 2677 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits { 2678 u8 rx_octets_high[0x20]; 2679 2680 u8 rx_octets_low[0x20]; 2681 2682 u8 reserved_at_40[0xc0]; 2683 2684 u8 rx_frames_high[0x20]; 2685 2686 u8 rx_frames_low[0x20]; 2687 2688 u8 tx_octets_high[0x20]; 2689 2690 u8 tx_octets_low[0x20]; 2691 2692 u8 reserved_at_180[0xc0]; 2693 2694 u8 tx_frames_high[0x20]; 2695 2696 u8 tx_frames_low[0x20]; 2697 2698 u8 rx_pause_high[0x20]; 2699 2700 u8 rx_pause_low[0x20]; 2701 2702 u8 rx_pause_duration_high[0x20]; 2703 2704 u8 rx_pause_duration_low[0x20]; 2705 2706 u8 tx_pause_high[0x20]; 2707 2708 u8 tx_pause_low[0x20]; 2709 2710 u8 tx_pause_duration_high[0x20]; 2711 2712 u8 tx_pause_duration_low[0x20]; 2713 2714 u8 rx_pause_transition_high[0x20]; 2715 2716 u8 rx_pause_transition_low[0x20]; 2717 2718 u8 rx_discards_high[0x20]; 2719 2720 u8 rx_discards_low[0x20]; 2721 2722 u8 device_stall_minor_watermark_cnt_high[0x20]; 2723 2724 u8 device_stall_minor_watermark_cnt_low[0x20]; 2725 2726 u8 device_stall_critical_watermark_cnt_high[0x20]; 2727 2728 u8 device_stall_critical_watermark_cnt_low[0x20]; 2729 2730 u8 reserved_at_480[0x340]; 2731 }; 2732 2733 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits { 2734 u8 port_transmit_wait_high[0x20]; 2735 2736 u8 port_transmit_wait_low[0x20]; 2737 2738 u8 reserved_at_40[0x100]; 2739 2740 u8 rx_buffer_almost_full_high[0x20]; 2741 2742 u8 rx_buffer_almost_full_low[0x20]; 2743 2744 u8 rx_buffer_full_high[0x20]; 2745 2746 u8 rx_buffer_full_low[0x20]; 2747 2748 u8 rx_icrc_encapsulated_high[0x20]; 2749 2750 u8 rx_icrc_encapsulated_low[0x20]; 2751 2752 u8 reserved_at_200[0x5c0]; 2753 }; 2754 2755 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits { 2756 u8 dot3stats_alignment_errors_high[0x20]; 2757 2758 u8 dot3stats_alignment_errors_low[0x20]; 2759 2760 u8 dot3stats_fcs_errors_high[0x20]; 2761 2762 u8 dot3stats_fcs_errors_low[0x20]; 2763 2764 u8 dot3stats_single_collision_frames_high[0x20]; 2765 2766 u8 dot3stats_single_collision_frames_low[0x20]; 2767 2768 u8 dot3stats_multiple_collision_frames_high[0x20]; 2769 2770 u8 dot3stats_multiple_collision_frames_low[0x20]; 2771 2772 u8 dot3stats_sqe_test_errors_high[0x20]; 2773 2774 u8 dot3stats_sqe_test_errors_low[0x20]; 2775 2776 u8 dot3stats_deferred_transmissions_high[0x20]; 2777 2778 u8 dot3stats_deferred_transmissions_low[0x20]; 2779 2780 u8 dot3stats_late_collisions_high[0x20]; 2781 2782 u8 dot3stats_late_collisions_low[0x20]; 2783 2784 u8 dot3stats_excessive_collisions_high[0x20]; 2785 2786 u8 dot3stats_excessive_collisions_low[0x20]; 2787 2788 u8 dot3stats_internal_mac_transmit_errors_high[0x20]; 2789 2790 u8 dot3stats_internal_mac_transmit_errors_low[0x20]; 2791 2792 u8 dot3stats_carrier_sense_errors_high[0x20]; 2793 2794 u8 dot3stats_carrier_sense_errors_low[0x20]; 2795 2796 u8 dot3stats_frame_too_longs_high[0x20]; 2797 2798 u8 dot3stats_frame_too_longs_low[0x20]; 2799 2800 u8 dot3stats_internal_mac_receive_errors_high[0x20]; 2801 2802 u8 dot3stats_internal_mac_receive_errors_low[0x20]; 2803 2804 u8 dot3stats_symbol_errors_high[0x20]; 2805 2806 u8 dot3stats_symbol_errors_low[0x20]; 2807 2808 u8 dot3control_in_unknown_opcodes_high[0x20]; 2809 2810 u8 dot3control_in_unknown_opcodes_low[0x20]; 2811 2812 u8 dot3in_pause_frames_high[0x20]; 2813 2814 u8 dot3in_pause_frames_low[0x20]; 2815 2816 u8 dot3out_pause_frames_high[0x20]; 2817 2818 u8 dot3out_pause_frames_low[0x20]; 2819 2820 u8 reserved_at_400[0x3c0]; 2821 }; 2822 2823 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits { 2824 u8 ether_stats_drop_events_high[0x20]; 2825 2826 u8 ether_stats_drop_events_low[0x20]; 2827 2828 u8 ether_stats_octets_high[0x20]; 2829 2830 u8 ether_stats_octets_low[0x20]; 2831 2832 u8 ether_stats_pkts_high[0x20]; 2833 2834 u8 ether_stats_pkts_low[0x20]; 2835 2836 u8 ether_stats_broadcast_pkts_high[0x20]; 2837 2838 u8 ether_stats_broadcast_pkts_low[0x20]; 2839 2840 u8 ether_stats_multicast_pkts_high[0x20]; 2841 2842 u8 ether_stats_multicast_pkts_low[0x20]; 2843 2844 u8 ether_stats_crc_align_errors_high[0x20]; 2845 2846 u8 ether_stats_crc_align_errors_low[0x20]; 2847 2848 u8 ether_stats_undersize_pkts_high[0x20]; 2849 2850 u8 ether_stats_undersize_pkts_low[0x20]; 2851 2852 u8 ether_stats_oversize_pkts_high[0x20]; 2853 2854 u8 ether_stats_oversize_pkts_low[0x20]; 2855 2856 u8 ether_stats_fragments_high[0x20]; 2857 2858 u8 ether_stats_fragments_low[0x20]; 2859 2860 u8 ether_stats_jabbers_high[0x20]; 2861 2862 u8 ether_stats_jabbers_low[0x20]; 2863 2864 u8 ether_stats_collisions_high[0x20]; 2865 2866 u8 ether_stats_collisions_low[0x20]; 2867 2868 u8 ether_stats_pkts64octets_high[0x20]; 2869 2870 u8 ether_stats_pkts64octets_low[0x20]; 2871 2872 u8 ether_stats_pkts65to127octets_high[0x20]; 2873 2874 u8 ether_stats_pkts65to127octets_low[0x20]; 2875 2876 u8 ether_stats_pkts128to255octets_high[0x20]; 2877 2878 u8 ether_stats_pkts128to255octets_low[0x20]; 2879 2880 u8 ether_stats_pkts256to511octets_high[0x20]; 2881 2882 u8 ether_stats_pkts256to511octets_low[0x20]; 2883 2884 u8 ether_stats_pkts512to1023octets_high[0x20]; 2885 2886 u8 ether_stats_pkts512to1023octets_low[0x20]; 2887 2888 u8 ether_stats_pkts1024to1518octets_high[0x20]; 2889 2890 u8 ether_stats_pkts1024to1518octets_low[0x20]; 2891 2892 u8 ether_stats_pkts1519to2047octets_high[0x20]; 2893 2894 u8 ether_stats_pkts1519to2047octets_low[0x20]; 2895 2896 u8 ether_stats_pkts2048to4095octets_high[0x20]; 2897 2898 u8 ether_stats_pkts2048to4095octets_low[0x20]; 2899 2900 u8 ether_stats_pkts4096to8191octets_high[0x20]; 2901 2902 u8 ether_stats_pkts4096to8191octets_low[0x20]; 2903 2904 u8 ether_stats_pkts8192to10239octets_high[0x20]; 2905 2906 u8 ether_stats_pkts8192to10239octets_low[0x20]; 2907 2908 u8 reserved_at_540[0x280]; 2909 }; 2910 2911 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits { 2912 u8 if_in_octets_high[0x20]; 2913 2914 u8 if_in_octets_low[0x20]; 2915 2916 u8 if_in_ucast_pkts_high[0x20]; 2917 2918 u8 if_in_ucast_pkts_low[0x20]; 2919 2920 u8 if_in_discards_high[0x20]; 2921 2922 u8 if_in_discards_low[0x20]; 2923 2924 u8 if_in_errors_high[0x20]; 2925 2926 u8 if_in_errors_low[0x20]; 2927 2928 u8 if_in_unknown_protos_high[0x20]; 2929 2930 u8 if_in_unknown_protos_low[0x20]; 2931 2932 u8 if_out_octets_high[0x20]; 2933 2934 u8 if_out_octets_low[0x20]; 2935 2936 u8 if_out_ucast_pkts_high[0x20]; 2937 2938 u8 if_out_ucast_pkts_low[0x20]; 2939 2940 u8 if_out_discards_high[0x20]; 2941 2942 u8 if_out_discards_low[0x20]; 2943 2944 u8 if_out_errors_high[0x20]; 2945 2946 u8 if_out_errors_low[0x20]; 2947 2948 u8 if_in_multicast_pkts_high[0x20]; 2949 2950 u8 if_in_multicast_pkts_low[0x20]; 2951 2952 u8 if_in_broadcast_pkts_high[0x20]; 2953 2954 u8 if_in_broadcast_pkts_low[0x20]; 2955 2956 u8 if_out_multicast_pkts_high[0x20]; 2957 2958 u8 if_out_multicast_pkts_low[0x20]; 2959 2960 u8 if_out_broadcast_pkts_high[0x20]; 2961 2962 u8 if_out_broadcast_pkts_low[0x20]; 2963 2964 u8 reserved_at_340[0x480]; 2965 }; 2966 2967 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits { 2968 u8 a_frames_transmitted_ok_high[0x20]; 2969 2970 u8 a_frames_transmitted_ok_low[0x20]; 2971 2972 u8 a_frames_received_ok_high[0x20]; 2973 2974 u8 a_frames_received_ok_low[0x20]; 2975 2976 u8 a_frame_check_sequence_errors_high[0x20]; 2977 2978 u8 a_frame_check_sequence_errors_low[0x20]; 2979 2980 u8 a_alignment_errors_high[0x20]; 2981 2982 u8 a_alignment_errors_low[0x20]; 2983 2984 u8 a_octets_transmitted_ok_high[0x20]; 2985 2986 u8 a_octets_transmitted_ok_low[0x20]; 2987 2988 u8 a_octets_received_ok_high[0x20]; 2989 2990 u8 a_octets_received_ok_low[0x20]; 2991 2992 u8 a_multicast_frames_xmitted_ok_high[0x20]; 2993 2994 u8 a_multicast_frames_xmitted_ok_low[0x20]; 2995 2996 u8 a_broadcast_frames_xmitted_ok_high[0x20]; 2997 2998 u8 a_broadcast_frames_xmitted_ok_low[0x20]; 2999 3000 u8 a_multicast_frames_received_ok_high[0x20]; 3001 3002 u8 a_multicast_frames_received_ok_low[0x20]; 3003 3004 u8 a_broadcast_frames_received_ok_high[0x20]; 3005 3006 u8 a_broadcast_frames_received_ok_low[0x20]; 3007 3008 u8 a_in_range_length_errors_high[0x20]; 3009 3010 u8 a_in_range_length_errors_low[0x20]; 3011 3012 u8 a_out_of_range_length_field_high[0x20]; 3013 3014 u8 a_out_of_range_length_field_low[0x20]; 3015 3016 u8 a_frame_too_long_errors_high[0x20]; 3017 3018 u8 a_frame_too_long_errors_low[0x20]; 3019 3020 u8 a_symbol_error_during_carrier_high[0x20]; 3021 3022 u8 a_symbol_error_during_carrier_low[0x20]; 3023 3024 u8 a_mac_control_frames_transmitted_high[0x20]; 3025 3026 u8 a_mac_control_frames_transmitted_low[0x20]; 3027 3028 u8 a_mac_control_frames_received_high[0x20]; 3029 3030 u8 a_mac_control_frames_received_low[0x20]; 3031 3032 u8 a_unsupported_opcodes_received_high[0x20]; 3033 3034 u8 a_unsupported_opcodes_received_low[0x20]; 3035 3036 u8 a_pause_mac_ctrl_frames_received_high[0x20]; 3037 3038 u8 a_pause_mac_ctrl_frames_received_low[0x20]; 3039 3040 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20]; 3041 3042 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20]; 3043 3044 u8 reserved_at_4c0[0x300]; 3045 }; 3046 3047 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits { 3048 u8 life_time_counter_high[0x20]; 3049 3050 u8 life_time_counter_low[0x20]; 3051 3052 u8 rx_errors[0x20]; 3053 3054 u8 tx_errors[0x20]; 3055 3056 u8 l0_to_recovery_eieos[0x20]; 3057 3058 u8 l0_to_recovery_ts[0x20]; 3059 3060 u8 l0_to_recovery_framing[0x20]; 3061 3062 u8 l0_to_recovery_retrain[0x20]; 3063 3064 u8 crc_error_dllp[0x20]; 3065 3066 u8 crc_error_tlp[0x20]; 3067 3068 u8 tx_overflow_buffer_pkt_high[0x20]; 3069 3070 u8 tx_overflow_buffer_pkt_low[0x20]; 3071 3072 u8 outbound_stalled_reads[0x20]; 3073 3074 u8 outbound_stalled_writes[0x20]; 3075 3076 u8 outbound_stalled_reads_events[0x20]; 3077 3078 u8 outbound_stalled_writes_events[0x20]; 3079 3080 u8 reserved_at_200[0x5c0]; 3081 }; 3082 3083 struct mlx5_ifc_cmd_inter_comp_event_bits { 3084 u8 command_completion_vector[0x20]; 3085 3086 u8 reserved_at_20[0xc0]; 3087 }; 3088 3089 struct mlx5_ifc_stall_vl_event_bits { 3090 u8 reserved_at_0[0x18]; 3091 u8 port_num[0x1]; 3092 u8 reserved_at_19[0x3]; 3093 u8 vl[0x4]; 3094 3095 u8 reserved_at_20[0xa0]; 3096 }; 3097 3098 struct mlx5_ifc_db_bf_congestion_event_bits { 3099 u8 event_subtype[0x8]; 3100 u8 reserved_at_8[0x8]; 3101 u8 congestion_level[0x8]; 3102 u8 reserved_at_18[0x8]; 3103 3104 u8 reserved_at_20[0xa0]; 3105 }; 3106 3107 struct mlx5_ifc_gpio_event_bits { 3108 u8 reserved_at_0[0x60]; 3109 3110 u8 gpio_event_hi[0x20]; 3111 3112 u8 gpio_event_lo[0x20]; 3113 3114 u8 reserved_at_a0[0x40]; 3115 }; 3116 3117 struct mlx5_ifc_port_state_change_event_bits { 3118 u8 reserved_at_0[0x40]; 3119 3120 u8 port_num[0x4]; 3121 u8 reserved_at_44[0x1c]; 3122 3123 u8 reserved_at_60[0x80]; 3124 }; 3125 3126 struct mlx5_ifc_dropped_packet_logged_bits { 3127 u8 reserved_at_0[0xe0]; 3128 }; 3129 3130 struct mlx5_ifc_default_timeout_bits { 3131 u8 to_multiplier[0x3]; 3132 u8 reserved_at_3[0x9]; 3133 u8 to_value[0x14]; 3134 }; 3135 3136 struct mlx5_ifc_dtor_reg_bits { 3137 u8 reserved_at_0[0x20]; 3138 3139 struct mlx5_ifc_default_timeout_bits pcie_toggle_to; 3140 3141 u8 reserved_at_40[0x60]; 3142 3143 struct mlx5_ifc_default_timeout_bits health_poll_to; 3144 3145 struct mlx5_ifc_default_timeout_bits full_crdump_to; 3146 3147 struct mlx5_ifc_default_timeout_bits fw_reset_to; 3148 3149 struct mlx5_ifc_default_timeout_bits flush_on_err_to; 3150 3151 struct mlx5_ifc_default_timeout_bits pci_sync_update_to; 3152 3153 struct mlx5_ifc_default_timeout_bits tear_down_to; 3154 3155 struct mlx5_ifc_default_timeout_bits fsm_reactivate_to; 3156 3157 struct mlx5_ifc_default_timeout_bits reclaim_pages_to; 3158 3159 struct mlx5_ifc_default_timeout_bits reclaim_vfs_pages_to; 3160 3161 struct mlx5_ifc_default_timeout_bits reset_unload_to; 3162 3163 u8 reserved_at_1c0[0x20]; 3164 }; 3165 3166 enum { 3167 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1, 3168 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2, 3169 }; 3170 3171 struct mlx5_ifc_cq_error_bits { 3172 u8 reserved_at_0[0x8]; 3173 u8 cqn[0x18]; 3174 3175 u8 reserved_at_20[0x20]; 3176 3177 u8 reserved_at_40[0x18]; 3178 u8 syndrome[0x8]; 3179 3180 u8 reserved_at_60[0x80]; 3181 }; 3182 3183 struct mlx5_ifc_rdma_page_fault_event_bits { 3184 u8 bytes_committed[0x20]; 3185 3186 u8 r_key[0x20]; 3187 3188 u8 reserved_at_40[0x10]; 3189 u8 packet_len[0x10]; 3190 3191 u8 rdma_op_len[0x20]; 3192 3193 u8 rdma_va[0x40]; 3194 3195 u8 reserved_at_c0[0x5]; 3196 u8 rdma[0x1]; 3197 u8 write[0x1]; 3198 u8 requestor[0x1]; 3199 u8 qp_number[0x18]; 3200 }; 3201 3202 struct mlx5_ifc_wqe_associated_page_fault_event_bits { 3203 u8 bytes_committed[0x20]; 3204 3205 u8 reserved_at_20[0x10]; 3206 u8 wqe_index[0x10]; 3207 3208 u8 reserved_at_40[0x10]; 3209 u8 len[0x10]; 3210 3211 u8 reserved_at_60[0x60]; 3212 3213 u8 reserved_at_c0[0x5]; 3214 u8 rdma[0x1]; 3215 u8 write_read[0x1]; 3216 u8 requestor[0x1]; 3217 u8 qpn[0x18]; 3218 }; 3219 3220 struct mlx5_ifc_qp_events_bits { 3221 u8 reserved_at_0[0xa0]; 3222 3223 u8 type[0x8]; 3224 u8 reserved_at_a8[0x18]; 3225 3226 u8 reserved_at_c0[0x8]; 3227 u8 qpn_rqn_sqn[0x18]; 3228 }; 3229 3230 struct mlx5_ifc_dct_events_bits { 3231 u8 reserved_at_0[0xc0]; 3232 3233 u8 reserved_at_c0[0x8]; 3234 u8 dct_number[0x18]; 3235 }; 3236 3237 struct mlx5_ifc_comp_event_bits { 3238 u8 reserved_at_0[0xc0]; 3239 3240 u8 reserved_at_c0[0x8]; 3241 u8 cq_number[0x18]; 3242 }; 3243 3244 enum { 3245 MLX5_QPC_STATE_RST = 0x0, 3246 MLX5_QPC_STATE_INIT = 0x1, 3247 MLX5_QPC_STATE_RTR = 0x2, 3248 MLX5_QPC_STATE_RTS = 0x3, 3249 MLX5_QPC_STATE_SQER = 0x4, 3250 MLX5_QPC_STATE_ERR = 0x6, 3251 MLX5_QPC_STATE_SQD = 0x7, 3252 MLX5_QPC_STATE_SUSPENDED = 0x9, 3253 }; 3254 3255 enum { 3256 MLX5_QPC_ST_RC = 0x0, 3257 MLX5_QPC_ST_UC = 0x1, 3258 MLX5_QPC_ST_UD = 0x2, 3259 MLX5_QPC_ST_XRC = 0x3, 3260 MLX5_QPC_ST_DCI = 0x5, 3261 MLX5_QPC_ST_QP0 = 0x7, 3262 MLX5_QPC_ST_QP1 = 0x8, 3263 MLX5_QPC_ST_RAW_DATAGRAM = 0x9, 3264 MLX5_QPC_ST_REG_UMR = 0xc, 3265 }; 3266 3267 enum { 3268 MLX5_QPC_PM_STATE_ARMED = 0x0, 3269 MLX5_QPC_PM_STATE_REARM = 0x1, 3270 MLX5_QPC_PM_STATE_RESERVED = 0x2, 3271 MLX5_QPC_PM_STATE_MIGRATED = 0x3, 3272 }; 3273 3274 enum { 3275 MLX5_QPC_OFFLOAD_TYPE_RNDV = 0x1, 3276 }; 3277 3278 enum { 3279 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0, 3280 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1, 3281 }; 3282 3283 enum { 3284 MLX5_QPC_MTU_256_BYTES = 0x1, 3285 MLX5_QPC_MTU_512_BYTES = 0x2, 3286 MLX5_QPC_MTU_1K_BYTES = 0x3, 3287 MLX5_QPC_MTU_2K_BYTES = 0x4, 3288 MLX5_QPC_MTU_4K_BYTES = 0x5, 3289 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7, 3290 }; 3291 3292 enum { 3293 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1, 3294 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2, 3295 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3, 3296 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4, 3297 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5, 3298 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6, 3299 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7, 3300 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8, 3301 }; 3302 3303 enum { 3304 MLX5_QPC_CS_REQ_DISABLE = 0x0, 3305 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11, 3306 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22, 3307 }; 3308 3309 enum { 3310 MLX5_QPC_CS_RES_DISABLE = 0x0, 3311 MLX5_QPC_CS_RES_UP_TO_32B = 0x1, 3312 MLX5_QPC_CS_RES_UP_TO_64B = 0x2, 3313 }; 3314 3315 enum { 3316 MLX5_TIMESTAMP_FORMAT_FREE_RUNNING = 0x0, 3317 MLX5_TIMESTAMP_FORMAT_DEFAULT = 0x1, 3318 MLX5_TIMESTAMP_FORMAT_REAL_TIME = 0x2, 3319 }; 3320 3321 struct mlx5_ifc_qpc_bits { 3322 u8 state[0x4]; 3323 u8 lag_tx_port_affinity[0x4]; 3324 u8 st[0x8]; 3325 u8 reserved_at_10[0x2]; 3326 u8 isolate_vl_tc[0x1]; 3327 u8 pm_state[0x2]; 3328 u8 reserved_at_15[0x1]; 3329 u8 req_e2e_credit_mode[0x2]; 3330 u8 offload_type[0x4]; 3331 u8 end_padding_mode[0x2]; 3332 u8 reserved_at_1e[0x2]; 3333 3334 u8 wq_signature[0x1]; 3335 u8 block_lb_mc[0x1]; 3336 u8 atomic_like_write_en[0x1]; 3337 u8 latency_sensitive[0x1]; 3338 u8 reserved_at_24[0x1]; 3339 u8 drain_sigerr[0x1]; 3340 u8 reserved_at_26[0x2]; 3341 u8 pd[0x18]; 3342 3343 u8 mtu[0x3]; 3344 u8 log_msg_max[0x5]; 3345 u8 reserved_at_48[0x1]; 3346 u8 log_rq_size[0x4]; 3347 u8 log_rq_stride[0x3]; 3348 u8 no_sq[0x1]; 3349 u8 log_sq_size[0x4]; 3350 u8 reserved_at_55[0x1]; 3351 u8 retry_mode[0x2]; 3352 u8 ts_format[0x2]; 3353 u8 reserved_at_5a[0x1]; 3354 u8 rlky[0x1]; 3355 u8 ulp_stateless_offload_mode[0x4]; 3356 3357 u8 counter_set_id[0x8]; 3358 u8 uar_page[0x18]; 3359 3360 u8 reserved_at_80[0x8]; 3361 u8 user_index[0x18]; 3362 3363 u8 reserved_at_a0[0x3]; 3364 u8 log_page_size[0x5]; 3365 u8 remote_qpn[0x18]; 3366 3367 struct mlx5_ifc_ads_bits primary_address_path; 3368 3369 struct mlx5_ifc_ads_bits secondary_address_path; 3370 3371 u8 log_ack_req_freq[0x4]; 3372 u8 reserved_at_384[0x4]; 3373 u8 log_sra_max[0x3]; 3374 u8 reserved_at_38b[0x2]; 3375 u8 retry_count[0x3]; 3376 u8 rnr_retry[0x3]; 3377 u8 reserved_at_393[0x1]; 3378 u8 fre[0x1]; 3379 u8 cur_rnr_retry[0x3]; 3380 u8 cur_retry_count[0x3]; 3381 u8 reserved_at_39b[0x5]; 3382 3383 u8 reserved_at_3a0[0x20]; 3384 3385 u8 reserved_at_3c0[0x8]; 3386 u8 next_send_psn[0x18]; 3387 3388 u8 reserved_at_3e0[0x3]; 3389 u8 log_num_dci_stream_channels[0x5]; 3390 u8 cqn_snd[0x18]; 3391 3392 u8 reserved_at_400[0x3]; 3393 u8 log_num_dci_errored_streams[0x5]; 3394 u8 deth_sqpn[0x18]; 3395 3396 u8 reserved_at_420[0x20]; 3397 3398 u8 reserved_at_440[0x8]; 3399 u8 last_acked_psn[0x18]; 3400 3401 u8 reserved_at_460[0x8]; 3402 u8 ssn[0x18]; 3403 3404 u8 reserved_at_480[0x8]; 3405 u8 log_rra_max[0x3]; 3406 u8 reserved_at_48b[0x1]; 3407 u8 atomic_mode[0x4]; 3408 u8 rre[0x1]; 3409 u8 rwe[0x1]; 3410 u8 rae[0x1]; 3411 u8 reserved_at_493[0x1]; 3412 u8 page_offset[0x6]; 3413 u8 reserved_at_49a[0x3]; 3414 u8 cd_slave_receive[0x1]; 3415 u8 cd_slave_send[0x1]; 3416 u8 cd_master[0x1]; 3417 3418 u8 reserved_at_4a0[0x3]; 3419 u8 min_rnr_nak[0x5]; 3420 u8 next_rcv_psn[0x18]; 3421 3422 u8 reserved_at_4c0[0x8]; 3423 u8 xrcd[0x18]; 3424 3425 u8 reserved_at_4e0[0x8]; 3426 u8 cqn_rcv[0x18]; 3427 3428 u8 dbr_addr[0x40]; 3429 3430 u8 q_key[0x20]; 3431 3432 u8 reserved_at_560[0x5]; 3433 u8 rq_type[0x3]; 3434 u8 srqn_rmpn_xrqn[0x18]; 3435 3436 u8 reserved_at_580[0x8]; 3437 u8 rmsn[0x18]; 3438 3439 u8 hw_sq_wqebb_counter[0x10]; 3440 u8 sw_sq_wqebb_counter[0x10]; 3441 3442 u8 hw_rq_counter[0x20]; 3443 3444 u8 sw_rq_counter[0x20]; 3445 3446 u8 reserved_at_600[0x20]; 3447 3448 u8 reserved_at_620[0xf]; 3449 u8 cgs[0x1]; 3450 u8 cs_req[0x8]; 3451 u8 cs_res[0x8]; 3452 3453 u8 dc_access_key[0x40]; 3454 3455 u8 reserved_at_680[0x3]; 3456 u8 dbr_umem_valid[0x1]; 3457 3458 u8 reserved_at_684[0xbc]; 3459 }; 3460 3461 struct mlx5_ifc_roce_addr_layout_bits { 3462 u8 source_l3_address[16][0x8]; 3463 3464 u8 reserved_at_80[0x3]; 3465 u8 vlan_valid[0x1]; 3466 u8 vlan_id[0xc]; 3467 u8 source_mac_47_32[0x10]; 3468 3469 u8 source_mac_31_0[0x20]; 3470 3471 u8 reserved_at_c0[0x14]; 3472 u8 roce_l3_type[0x4]; 3473 u8 roce_version[0x8]; 3474 3475 u8 reserved_at_e0[0x20]; 3476 }; 3477 3478 struct mlx5_ifc_crypto_cap_bits { 3479 u8 reserved_at_0[0x3]; 3480 u8 synchronize_dek[0x1]; 3481 u8 int_kek_manual[0x1]; 3482 u8 int_kek_auto[0x1]; 3483 u8 reserved_at_6[0x1a]; 3484 3485 u8 reserved_at_20[0x3]; 3486 u8 log_dek_max_alloc[0x5]; 3487 u8 reserved_at_28[0x3]; 3488 u8 log_max_num_deks[0x5]; 3489 u8 reserved_at_30[0x10]; 3490 3491 u8 reserved_at_40[0x20]; 3492 3493 u8 reserved_at_60[0x3]; 3494 u8 log_dek_granularity[0x5]; 3495 u8 reserved_at_68[0x3]; 3496 u8 log_max_num_int_kek[0x5]; 3497 u8 sw_wrapped_dek[0x10]; 3498 3499 u8 reserved_at_80[0x780]; 3500 }; 3501 3502 union mlx5_ifc_hca_cap_union_bits { 3503 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap; 3504 struct mlx5_ifc_cmd_hca_cap_2_bits cmd_hca_cap_2; 3505 struct mlx5_ifc_odp_cap_bits odp_cap; 3506 struct mlx5_ifc_atomic_caps_bits atomic_caps; 3507 struct mlx5_ifc_roce_cap_bits roce_cap; 3508 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps; 3509 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap; 3510 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap; 3511 struct mlx5_ifc_e_switch_cap_bits e_switch_cap; 3512 struct mlx5_ifc_port_selection_cap_bits port_selection_cap; 3513 struct mlx5_ifc_qos_cap_bits qos_cap; 3514 struct mlx5_ifc_debug_cap_bits debug_cap; 3515 struct mlx5_ifc_fpga_cap_bits fpga_cap; 3516 struct mlx5_ifc_tls_cap_bits tls_cap; 3517 struct mlx5_ifc_device_mem_cap_bits device_mem_cap; 3518 struct mlx5_ifc_virtio_emulation_cap_bits virtio_emulation_cap; 3519 struct mlx5_ifc_macsec_cap_bits macsec_cap; 3520 struct mlx5_ifc_crypto_cap_bits crypto_cap; 3521 struct mlx5_ifc_ipsec_cap_bits ipsec_cap; 3522 u8 reserved_at_0[0x8000]; 3523 }; 3524 3525 enum { 3526 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1, 3527 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2, 3528 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4, 3529 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8, 3530 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT = 0x10, 3531 MLX5_FLOW_CONTEXT_ACTION_DECAP = 0x20, 3532 MLX5_FLOW_CONTEXT_ACTION_MOD_HDR = 0x40, 3533 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP = 0x80, 3534 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100, 3535 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2 = 0x400, 3536 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2 = 0x800, 3537 MLX5_FLOW_CONTEXT_ACTION_CRYPTO_DECRYPT = 0x1000, 3538 MLX5_FLOW_CONTEXT_ACTION_CRYPTO_ENCRYPT = 0x2000, 3539 MLX5_FLOW_CONTEXT_ACTION_EXECUTE_ASO = 0x4000, 3540 }; 3541 3542 enum { 3543 MLX5_FLOW_CONTEXT_FLOW_SOURCE_ANY_VPORT = 0x0, 3544 MLX5_FLOW_CONTEXT_FLOW_SOURCE_UPLINK = 0x1, 3545 MLX5_FLOW_CONTEXT_FLOW_SOURCE_LOCAL_VPORT = 0x2, 3546 }; 3547 3548 enum { 3549 MLX5_FLOW_CONTEXT_ENCRYPT_DECRYPT_TYPE_IPSEC = 0x0, 3550 MLX5_FLOW_CONTEXT_ENCRYPT_DECRYPT_TYPE_MACSEC = 0x1, 3551 }; 3552 3553 struct mlx5_ifc_vlan_bits { 3554 u8 ethtype[0x10]; 3555 u8 prio[0x3]; 3556 u8 cfi[0x1]; 3557 u8 vid[0xc]; 3558 }; 3559 3560 enum { 3561 MLX5_FLOW_METER_COLOR_RED = 0x0, 3562 MLX5_FLOW_METER_COLOR_YELLOW = 0x1, 3563 MLX5_FLOW_METER_COLOR_GREEN = 0x2, 3564 MLX5_FLOW_METER_COLOR_UNDEFINED = 0x3, 3565 }; 3566 3567 enum { 3568 MLX5_EXE_ASO_FLOW_METER = 0x2, 3569 }; 3570 3571 struct mlx5_ifc_exe_aso_ctrl_flow_meter_bits { 3572 u8 return_reg_id[0x4]; 3573 u8 aso_type[0x4]; 3574 u8 reserved_at_8[0x14]; 3575 u8 action[0x1]; 3576 u8 init_color[0x2]; 3577 u8 meter_id[0x1]; 3578 }; 3579 3580 union mlx5_ifc_exe_aso_ctrl { 3581 struct mlx5_ifc_exe_aso_ctrl_flow_meter_bits exe_aso_ctrl_flow_meter; 3582 }; 3583 3584 struct mlx5_ifc_execute_aso_bits { 3585 u8 valid[0x1]; 3586 u8 reserved_at_1[0x7]; 3587 u8 aso_object_id[0x18]; 3588 3589 union mlx5_ifc_exe_aso_ctrl exe_aso_ctrl; 3590 }; 3591 3592 struct mlx5_ifc_flow_context_bits { 3593 struct mlx5_ifc_vlan_bits push_vlan; 3594 3595 u8 group_id[0x20]; 3596 3597 u8 reserved_at_40[0x8]; 3598 u8 flow_tag[0x18]; 3599 3600 u8 reserved_at_60[0x10]; 3601 u8 action[0x10]; 3602 3603 u8 extended_destination[0x1]; 3604 u8 uplink_hairpin_en[0x1]; 3605 u8 flow_source[0x2]; 3606 u8 encrypt_decrypt_type[0x4]; 3607 u8 destination_list_size[0x18]; 3608 3609 u8 reserved_at_a0[0x8]; 3610 u8 flow_counter_list_size[0x18]; 3611 3612 u8 packet_reformat_id[0x20]; 3613 3614 u8 modify_header_id[0x20]; 3615 3616 struct mlx5_ifc_vlan_bits push_vlan_2; 3617 3618 u8 encrypt_decrypt_obj_id[0x20]; 3619 u8 reserved_at_140[0xc0]; 3620 3621 struct mlx5_ifc_fte_match_param_bits match_value; 3622 3623 struct mlx5_ifc_execute_aso_bits execute_aso[4]; 3624 3625 u8 reserved_at_1300[0x500]; 3626 3627 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[]; 3628 }; 3629 3630 enum { 3631 MLX5_XRC_SRQC_STATE_GOOD = 0x0, 3632 MLX5_XRC_SRQC_STATE_ERROR = 0x1, 3633 }; 3634 3635 struct mlx5_ifc_xrc_srqc_bits { 3636 u8 state[0x4]; 3637 u8 log_xrc_srq_size[0x4]; 3638 u8 reserved_at_8[0x18]; 3639 3640 u8 wq_signature[0x1]; 3641 u8 cont_srq[0x1]; 3642 u8 reserved_at_22[0x1]; 3643 u8 rlky[0x1]; 3644 u8 basic_cyclic_rcv_wqe[0x1]; 3645 u8 log_rq_stride[0x3]; 3646 u8 xrcd[0x18]; 3647 3648 u8 page_offset[0x6]; 3649 u8 reserved_at_46[0x1]; 3650 u8 dbr_umem_valid[0x1]; 3651 u8 cqn[0x18]; 3652 3653 u8 reserved_at_60[0x20]; 3654 3655 u8 user_index_equal_xrc_srqn[0x1]; 3656 u8 reserved_at_81[0x1]; 3657 u8 log_page_size[0x6]; 3658 u8 user_index[0x18]; 3659 3660 u8 reserved_at_a0[0x20]; 3661 3662 u8 reserved_at_c0[0x8]; 3663 u8 pd[0x18]; 3664 3665 u8 lwm[0x10]; 3666 u8 wqe_cnt[0x10]; 3667 3668 u8 reserved_at_100[0x40]; 3669 3670 u8 db_record_addr_h[0x20]; 3671 3672 u8 db_record_addr_l[0x1e]; 3673 u8 reserved_at_17e[0x2]; 3674 3675 u8 reserved_at_180[0x80]; 3676 }; 3677 3678 struct mlx5_ifc_vnic_diagnostic_statistics_bits { 3679 u8 counter_error_queues[0x20]; 3680 3681 u8 total_error_queues[0x20]; 3682 3683 u8 send_queue_priority_update_flow[0x20]; 3684 3685 u8 reserved_at_60[0x20]; 3686 3687 u8 nic_receive_steering_discard[0x40]; 3688 3689 u8 receive_discard_vport_down[0x40]; 3690 3691 u8 transmit_discard_vport_down[0x40]; 3692 3693 u8 async_eq_overrun[0x20]; 3694 3695 u8 comp_eq_overrun[0x20]; 3696 3697 u8 reserved_at_180[0x20]; 3698 3699 u8 invalid_command[0x20]; 3700 3701 u8 quota_exceeded_command[0x20]; 3702 3703 u8 internal_rq_out_of_buffer[0x20]; 3704 3705 u8 cq_overrun[0x20]; 3706 3707 u8 eth_wqe_too_small[0x20]; 3708 3709 u8 reserved_at_220[0xc0]; 3710 3711 u8 generated_pkt_steering_fail[0x40]; 3712 3713 u8 handled_pkt_steering_fail[0x40]; 3714 3715 u8 reserved_at_360[0xc80]; 3716 }; 3717 3718 struct mlx5_ifc_traffic_counter_bits { 3719 u8 packets[0x40]; 3720 3721 u8 octets[0x40]; 3722 }; 3723 3724 struct mlx5_ifc_tisc_bits { 3725 u8 strict_lag_tx_port_affinity[0x1]; 3726 u8 tls_en[0x1]; 3727 u8 reserved_at_2[0x2]; 3728 u8 lag_tx_port_affinity[0x04]; 3729 3730 u8 reserved_at_8[0x4]; 3731 u8 prio[0x4]; 3732 u8 reserved_at_10[0x10]; 3733 3734 u8 reserved_at_20[0x100]; 3735 3736 u8 reserved_at_120[0x8]; 3737 u8 transport_domain[0x18]; 3738 3739 u8 reserved_at_140[0x8]; 3740 u8 underlay_qpn[0x18]; 3741 3742 u8 reserved_at_160[0x8]; 3743 u8 pd[0x18]; 3744 3745 u8 reserved_at_180[0x380]; 3746 }; 3747 3748 enum { 3749 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0, 3750 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1, 3751 }; 3752 3753 enum { 3754 MLX5_TIRC_PACKET_MERGE_MASK_IPV4_LRO = BIT(0), 3755 MLX5_TIRC_PACKET_MERGE_MASK_IPV6_LRO = BIT(1), 3756 }; 3757 3758 enum { 3759 MLX5_RX_HASH_FN_NONE = 0x0, 3760 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1, 3761 MLX5_RX_HASH_FN_TOEPLITZ = 0x2, 3762 }; 3763 3764 enum { 3765 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST = 0x1, 3766 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST = 0x2, 3767 }; 3768 3769 struct mlx5_ifc_tirc_bits { 3770 u8 reserved_at_0[0x20]; 3771 3772 u8 disp_type[0x4]; 3773 u8 tls_en[0x1]; 3774 u8 reserved_at_25[0x1b]; 3775 3776 u8 reserved_at_40[0x40]; 3777 3778 u8 reserved_at_80[0x4]; 3779 u8 lro_timeout_period_usecs[0x10]; 3780 u8 packet_merge_mask[0x4]; 3781 u8 lro_max_ip_payload_size[0x8]; 3782 3783 u8 reserved_at_a0[0x40]; 3784 3785 u8 reserved_at_e0[0x8]; 3786 u8 inline_rqn[0x18]; 3787 3788 u8 rx_hash_symmetric[0x1]; 3789 u8 reserved_at_101[0x1]; 3790 u8 tunneled_offload_en[0x1]; 3791 u8 reserved_at_103[0x5]; 3792 u8 indirect_table[0x18]; 3793 3794 u8 rx_hash_fn[0x4]; 3795 u8 reserved_at_124[0x2]; 3796 u8 self_lb_block[0x2]; 3797 u8 transport_domain[0x18]; 3798 3799 u8 rx_hash_toeplitz_key[10][0x20]; 3800 3801 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer; 3802 3803 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner; 3804 3805 u8 reserved_at_2c0[0x4c0]; 3806 }; 3807 3808 enum { 3809 MLX5_SRQC_STATE_GOOD = 0x0, 3810 MLX5_SRQC_STATE_ERROR = 0x1, 3811 }; 3812 3813 struct mlx5_ifc_srqc_bits { 3814 u8 state[0x4]; 3815 u8 log_srq_size[0x4]; 3816 u8 reserved_at_8[0x18]; 3817 3818 u8 wq_signature[0x1]; 3819 u8 cont_srq[0x1]; 3820 u8 reserved_at_22[0x1]; 3821 u8 rlky[0x1]; 3822 u8 reserved_at_24[0x1]; 3823 u8 log_rq_stride[0x3]; 3824 u8 xrcd[0x18]; 3825 3826 u8 page_offset[0x6]; 3827 u8 reserved_at_46[0x2]; 3828 u8 cqn[0x18]; 3829 3830 u8 reserved_at_60[0x20]; 3831 3832 u8 reserved_at_80[0x2]; 3833 u8 log_page_size[0x6]; 3834 u8 reserved_at_88[0x18]; 3835 3836 u8 reserved_at_a0[0x20]; 3837 3838 u8 reserved_at_c0[0x8]; 3839 u8 pd[0x18]; 3840 3841 u8 lwm[0x10]; 3842 u8 wqe_cnt[0x10]; 3843 3844 u8 reserved_at_100[0x40]; 3845 3846 u8 dbr_addr[0x40]; 3847 3848 u8 reserved_at_180[0x80]; 3849 }; 3850 3851 enum { 3852 MLX5_SQC_STATE_RST = 0x0, 3853 MLX5_SQC_STATE_RDY = 0x1, 3854 MLX5_SQC_STATE_ERR = 0x3, 3855 }; 3856 3857 struct mlx5_ifc_sqc_bits { 3858 u8 rlky[0x1]; 3859 u8 cd_master[0x1]; 3860 u8 fre[0x1]; 3861 u8 flush_in_error_en[0x1]; 3862 u8 allow_multi_pkt_send_wqe[0x1]; 3863 u8 min_wqe_inline_mode[0x3]; 3864 u8 state[0x4]; 3865 u8 reg_umr[0x1]; 3866 u8 allow_swp[0x1]; 3867 u8 hairpin[0x1]; 3868 u8 reserved_at_f[0xb]; 3869 u8 ts_format[0x2]; 3870 u8 reserved_at_1c[0x4]; 3871 3872 u8 reserved_at_20[0x8]; 3873 u8 user_index[0x18]; 3874 3875 u8 reserved_at_40[0x8]; 3876 u8 cqn[0x18]; 3877 3878 u8 reserved_at_60[0x8]; 3879 u8 hairpin_peer_rq[0x18]; 3880 3881 u8 reserved_at_80[0x10]; 3882 u8 hairpin_peer_vhca[0x10]; 3883 3884 u8 reserved_at_a0[0x20]; 3885 3886 u8 reserved_at_c0[0x8]; 3887 u8 ts_cqe_to_dest_cqn[0x18]; 3888 3889 u8 reserved_at_e0[0x10]; 3890 u8 packet_pacing_rate_limit_index[0x10]; 3891 u8 tis_lst_sz[0x10]; 3892 u8 qos_queue_group_id[0x10]; 3893 3894 u8 reserved_at_120[0x40]; 3895 3896 u8 reserved_at_160[0x8]; 3897 u8 tis_num_0[0x18]; 3898 3899 struct mlx5_ifc_wq_bits wq; 3900 }; 3901 3902 enum { 3903 SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0, 3904 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1, 3905 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2, 3906 SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3, 3907 SCHEDULING_CONTEXT_ELEMENT_TYPE_QUEUE_GROUP = 0x4, 3908 }; 3909 3910 enum { 3911 ELEMENT_TYPE_CAP_MASK_TASR = 1 << 0, 3912 ELEMENT_TYPE_CAP_MASK_VPORT = 1 << 1, 3913 ELEMENT_TYPE_CAP_MASK_VPORT_TC = 1 << 2, 3914 ELEMENT_TYPE_CAP_MASK_PARA_VPORT_TC = 1 << 3, 3915 }; 3916 3917 struct mlx5_ifc_scheduling_context_bits { 3918 u8 element_type[0x8]; 3919 u8 reserved_at_8[0x18]; 3920 3921 u8 element_attributes[0x20]; 3922 3923 u8 parent_element_id[0x20]; 3924 3925 u8 reserved_at_60[0x40]; 3926 3927 u8 bw_share[0x20]; 3928 3929 u8 max_average_bw[0x20]; 3930 3931 u8 reserved_at_e0[0x120]; 3932 }; 3933 3934 struct mlx5_ifc_rqtc_bits { 3935 u8 reserved_at_0[0xa0]; 3936 3937 u8 reserved_at_a0[0x5]; 3938 u8 list_q_type[0x3]; 3939 u8 reserved_at_a8[0x8]; 3940 u8 rqt_max_size[0x10]; 3941 3942 u8 rq_vhca_id_format[0x1]; 3943 u8 reserved_at_c1[0xf]; 3944 u8 rqt_actual_size[0x10]; 3945 3946 u8 reserved_at_e0[0x6a0]; 3947 3948 union { 3949 DECLARE_FLEX_ARRAY(struct mlx5_ifc_rq_num_bits, rq_num); 3950 DECLARE_FLEX_ARRAY(struct mlx5_ifc_rq_vhca_bits, rq_vhca); 3951 }; 3952 }; 3953 3954 enum { 3955 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0, 3956 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1, 3957 }; 3958 3959 enum { 3960 MLX5_RQC_STATE_RST = 0x0, 3961 MLX5_RQC_STATE_RDY = 0x1, 3962 MLX5_RQC_STATE_ERR = 0x3, 3963 }; 3964 3965 enum { 3966 MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_BYTE = 0x0, 3967 MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_STRIDE = 0x1, 3968 MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_PAGE = 0x2, 3969 }; 3970 3971 enum { 3972 MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_NO_MATCH = 0x0, 3973 MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_EXTENDED = 0x1, 3974 MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_FIVE_TUPLE = 0x2, 3975 }; 3976 3977 struct mlx5_ifc_rqc_bits { 3978 u8 rlky[0x1]; 3979 u8 delay_drop_en[0x1]; 3980 u8 scatter_fcs[0x1]; 3981 u8 vsd[0x1]; 3982 u8 mem_rq_type[0x4]; 3983 u8 state[0x4]; 3984 u8 reserved_at_c[0x1]; 3985 u8 flush_in_error_en[0x1]; 3986 u8 hairpin[0x1]; 3987 u8 reserved_at_f[0xb]; 3988 u8 ts_format[0x2]; 3989 u8 reserved_at_1c[0x4]; 3990 3991 u8 reserved_at_20[0x8]; 3992 u8 user_index[0x18]; 3993 3994 u8 reserved_at_40[0x8]; 3995 u8 cqn[0x18]; 3996 3997 u8 counter_set_id[0x8]; 3998 u8 reserved_at_68[0x18]; 3999 4000 u8 reserved_at_80[0x8]; 4001 u8 rmpn[0x18]; 4002 4003 u8 reserved_at_a0[0x8]; 4004 u8 hairpin_peer_sq[0x18]; 4005 4006 u8 reserved_at_c0[0x10]; 4007 u8 hairpin_peer_vhca[0x10]; 4008 4009 u8 reserved_at_e0[0x46]; 4010 u8 shampo_no_match_alignment_granularity[0x2]; 4011 u8 reserved_at_128[0x6]; 4012 u8 shampo_match_criteria_type[0x2]; 4013 u8 reservation_timeout[0x10]; 4014 4015 u8 reserved_at_140[0x40]; 4016 4017 struct mlx5_ifc_wq_bits wq; 4018 }; 4019 4020 enum { 4021 MLX5_RMPC_STATE_RDY = 0x1, 4022 MLX5_RMPC_STATE_ERR = 0x3, 4023 }; 4024 4025 struct mlx5_ifc_rmpc_bits { 4026 u8 reserved_at_0[0x8]; 4027 u8 state[0x4]; 4028 u8 reserved_at_c[0x14]; 4029 4030 u8 basic_cyclic_rcv_wqe[0x1]; 4031 u8 reserved_at_21[0x1f]; 4032 4033 u8 reserved_at_40[0x140]; 4034 4035 struct mlx5_ifc_wq_bits wq; 4036 }; 4037 4038 enum { 4039 VHCA_ID_TYPE_HW = 0, 4040 VHCA_ID_TYPE_SW = 1, 4041 }; 4042 4043 struct mlx5_ifc_nic_vport_context_bits { 4044 u8 reserved_at_0[0x5]; 4045 u8 min_wqe_inline_mode[0x3]; 4046 u8 reserved_at_8[0x15]; 4047 u8 disable_mc_local_lb[0x1]; 4048 u8 disable_uc_local_lb[0x1]; 4049 u8 roce_en[0x1]; 4050 4051 u8 arm_change_event[0x1]; 4052 u8 reserved_at_21[0x1a]; 4053 u8 event_on_mtu[0x1]; 4054 u8 event_on_promisc_change[0x1]; 4055 u8 event_on_vlan_change[0x1]; 4056 u8 event_on_mc_address_change[0x1]; 4057 u8 event_on_uc_address_change[0x1]; 4058 4059 u8 vhca_id_type[0x1]; 4060 u8 reserved_at_41[0xb]; 4061 u8 affiliation_criteria[0x4]; 4062 u8 affiliated_vhca_id[0x10]; 4063 4064 u8 reserved_at_60[0xa0]; 4065 4066 u8 reserved_at_100[0x1]; 4067 u8 sd_group[0x3]; 4068 u8 reserved_at_104[0x1c]; 4069 4070 u8 reserved_at_120[0x10]; 4071 u8 mtu[0x10]; 4072 4073 u8 system_image_guid[0x40]; 4074 u8 port_guid[0x40]; 4075 u8 node_guid[0x40]; 4076 4077 u8 reserved_at_200[0x140]; 4078 u8 qkey_violation_counter[0x10]; 4079 u8 reserved_at_350[0x430]; 4080 4081 u8 promisc_uc[0x1]; 4082 u8 promisc_mc[0x1]; 4083 u8 promisc_all[0x1]; 4084 u8 reserved_at_783[0x2]; 4085 u8 allowed_list_type[0x3]; 4086 u8 reserved_at_788[0xc]; 4087 u8 allowed_list_size[0xc]; 4088 4089 struct mlx5_ifc_mac_address_layout_bits permanent_address; 4090 4091 u8 reserved_at_7e0[0x20]; 4092 4093 u8 current_uc_mac_address[][0x40]; 4094 }; 4095 4096 enum { 4097 MLX5_MKC_ACCESS_MODE_PA = 0x0, 4098 MLX5_MKC_ACCESS_MODE_MTT = 0x1, 4099 MLX5_MKC_ACCESS_MODE_KLMS = 0x2, 4100 MLX5_MKC_ACCESS_MODE_KSM = 0x3, 4101 MLX5_MKC_ACCESS_MODE_SW_ICM = 0x4, 4102 MLX5_MKC_ACCESS_MODE_MEMIC = 0x5, 4103 }; 4104 4105 struct mlx5_ifc_mkc_bits { 4106 u8 reserved_at_0[0x1]; 4107 u8 free[0x1]; 4108 u8 reserved_at_2[0x1]; 4109 u8 access_mode_4_2[0x3]; 4110 u8 reserved_at_6[0x7]; 4111 u8 relaxed_ordering_write[0x1]; 4112 u8 reserved_at_e[0x1]; 4113 u8 small_fence_on_rdma_read_response[0x1]; 4114 u8 umr_en[0x1]; 4115 u8 a[0x1]; 4116 u8 rw[0x1]; 4117 u8 rr[0x1]; 4118 u8 lw[0x1]; 4119 u8 lr[0x1]; 4120 u8 access_mode_1_0[0x2]; 4121 u8 reserved_at_18[0x2]; 4122 u8 ma_translation_mode[0x2]; 4123 u8 reserved_at_1c[0x4]; 4124 4125 u8 qpn[0x18]; 4126 u8 mkey_7_0[0x8]; 4127 4128 u8 reserved_at_40[0x20]; 4129 4130 u8 length64[0x1]; 4131 u8 bsf_en[0x1]; 4132 u8 sync_umr[0x1]; 4133 u8 reserved_at_63[0x2]; 4134 u8 expected_sigerr_count[0x1]; 4135 u8 reserved_at_66[0x1]; 4136 u8 en_rinval[0x1]; 4137 u8 pd[0x18]; 4138 4139 u8 start_addr[0x40]; 4140 4141 u8 len[0x40]; 4142 4143 u8 bsf_octword_size[0x20]; 4144 4145 u8 reserved_at_120[0x80]; 4146 4147 u8 translations_octword_size[0x20]; 4148 4149 u8 reserved_at_1c0[0x19]; 4150 u8 relaxed_ordering_read[0x1]; 4151 u8 reserved_at_1d9[0x1]; 4152 u8 log_page_size[0x5]; 4153 4154 u8 reserved_at_1e0[0x20]; 4155 }; 4156 4157 struct mlx5_ifc_pkey_bits { 4158 u8 reserved_at_0[0x10]; 4159 u8 pkey[0x10]; 4160 }; 4161 4162 struct mlx5_ifc_array128_auto_bits { 4163 u8 array128_auto[16][0x8]; 4164 }; 4165 4166 struct mlx5_ifc_hca_vport_context_bits { 4167 u8 field_select[0x20]; 4168 4169 u8 reserved_at_20[0xe0]; 4170 4171 u8 sm_virt_aware[0x1]; 4172 u8 has_smi[0x1]; 4173 u8 has_raw[0x1]; 4174 u8 grh_required[0x1]; 4175 u8 reserved_at_104[0xc]; 4176 u8 port_physical_state[0x4]; 4177 u8 vport_state_policy[0x4]; 4178 u8 port_state[0x4]; 4179 u8 vport_state[0x4]; 4180 4181 u8 reserved_at_120[0x20]; 4182 4183 u8 system_image_guid[0x40]; 4184 4185 u8 port_guid[0x40]; 4186 4187 u8 node_guid[0x40]; 4188 4189 u8 cap_mask1[0x20]; 4190 4191 u8 cap_mask1_field_select[0x20]; 4192 4193 u8 cap_mask2[0x20]; 4194 4195 u8 cap_mask2_field_select[0x20]; 4196 4197 u8 reserved_at_280[0x80]; 4198 4199 u8 lid[0x10]; 4200 u8 reserved_at_310[0x4]; 4201 u8 init_type_reply[0x4]; 4202 u8 lmc[0x3]; 4203 u8 subnet_timeout[0x5]; 4204 4205 u8 sm_lid[0x10]; 4206 u8 sm_sl[0x4]; 4207 u8 reserved_at_334[0xc]; 4208 4209 u8 qkey_violation_counter[0x10]; 4210 u8 pkey_violation_counter[0x10]; 4211 4212 u8 reserved_at_360[0xca0]; 4213 }; 4214 4215 struct mlx5_ifc_esw_vport_context_bits { 4216 u8 fdb_to_vport_reg_c[0x1]; 4217 u8 reserved_at_1[0x2]; 4218 u8 vport_svlan_strip[0x1]; 4219 u8 vport_cvlan_strip[0x1]; 4220 u8 vport_svlan_insert[0x1]; 4221 u8 vport_cvlan_insert[0x2]; 4222 u8 fdb_to_vport_reg_c_id[0x8]; 4223 u8 reserved_at_10[0x10]; 4224 4225 u8 reserved_at_20[0x20]; 4226 4227 u8 svlan_cfi[0x1]; 4228 u8 svlan_pcp[0x3]; 4229 u8 svlan_id[0xc]; 4230 u8 cvlan_cfi[0x1]; 4231 u8 cvlan_pcp[0x3]; 4232 u8 cvlan_id[0xc]; 4233 4234 u8 reserved_at_60[0x720]; 4235 4236 u8 sw_steering_vport_icm_address_rx[0x40]; 4237 4238 u8 sw_steering_vport_icm_address_tx[0x40]; 4239 }; 4240 4241 enum { 4242 MLX5_EQC_STATUS_OK = 0x0, 4243 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa, 4244 }; 4245 4246 enum { 4247 MLX5_EQC_ST_ARMED = 0x9, 4248 MLX5_EQC_ST_FIRED = 0xa, 4249 }; 4250 4251 struct mlx5_ifc_eqc_bits { 4252 u8 status[0x4]; 4253 u8 reserved_at_4[0x9]; 4254 u8 ec[0x1]; 4255 u8 oi[0x1]; 4256 u8 reserved_at_f[0x5]; 4257 u8 st[0x4]; 4258 u8 reserved_at_18[0x8]; 4259 4260 u8 reserved_at_20[0x20]; 4261 4262 u8 reserved_at_40[0x14]; 4263 u8 page_offset[0x6]; 4264 u8 reserved_at_5a[0x6]; 4265 4266 u8 reserved_at_60[0x3]; 4267 u8 log_eq_size[0x5]; 4268 u8 uar_page[0x18]; 4269 4270 u8 reserved_at_80[0x20]; 4271 4272 u8 reserved_at_a0[0x14]; 4273 u8 intr[0xc]; 4274 4275 u8 reserved_at_c0[0x3]; 4276 u8 log_page_size[0x5]; 4277 u8 reserved_at_c8[0x18]; 4278 4279 u8 reserved_at_e0[0x60]; 4280 4281 u8 reserved_at_140[0x8]; 4282 u8 consumer_counter[0x18]; 4283 4284 u8 reserved_at_160[0x8]; 4285 u8 producer_counter[0x18]; 4286 4287 u8 reserved_at_180[0x80]; 4288 }; 4289 4290 enum { 4291 MLX5_DCTC_STATE_ACTIVE = 0x0, 4292 MLX5_DCTC_STATE_DRAINING = 0x1, 4293 MLX5_DCTC_STATE_DRAINED = 0x2, 4294 }; 4295 4296 enum { 4297 MLX5_DCTC_CS_RES_DISABLE = 0x0, 4298 MLX5_DCTC_CS_RES_NA = 0x1, 4299 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2, 4300 }; 4301 4302 enum { 4303 MLX5_DCTC_MTU_256_BYTES = 0x1, 4304 MLX5_DCTC_MTU_512_BYTES = 0x2, 4305 MLX5_DCTC_MTU_1K_BYTES = 0x3, 4306 MLX5_DCTC_MTU_2K_BYTES = 0x4, 4307 MLX5_DCTC_MTU_4K_BYTES = 0x5, 4308 }; 4309 4310 struct mlx5_ifc_dctc_bits { 4311 u8 reserved_at_0[0x4]; 4312 u8 state[0x4]; 4313 u8 reserved_at_8[0x18]; 4314 4315 u8 reserved_at_20[0x8]; 4316 u8 user_index[0x18]; 4317 4318 u8 reserved_at_40[0x8]; 4319 u8 cqn[0x18]; 4320 4321 u8 counter_set_id[0x8]; 4322 u8 atomic_mode[0x4]; 4323 u8 rre[0x1]; 4324 u8 rwe[0x1]; 4325 u8 rae[0x1]; 4326 u8 atomic_like_write_en[0x1]; 4327 u8 latency_sensitive[0x1]; 4328 u8 rlky[0x1]; 4329 u8 free_ar[0x1]; 4330 u8 reserved_at_73[0xd]; 4331 4332 u8 reserved_at_80[0x8]; 4333 u8 cs_res[0x8]; 4334 u8 reserved_at_90[0x3]; 4335 u8 min_rnr_nak[0x5]; 4336 u8 reserved_at_98[0x8]; 4337 4338 u8 reserved_at_a0[0x8]; 4339 u8 srqn_xrqn[0x18]; 4340 4341 u8 reserved_at_c0[0x8]; 4342 u8 pd[0x18]; 4343 4344 u8 tclass[0x8]; 4345 u8 reserved_at_e8[0x4]; 4346 u8 flow_label[0x14]; 4347 4348 u8 dc_access_key[0x40]; 4349 4350 u8 reserved_at_140[0x5]; 4351 u8 mtu[0x3]; 4352 u8 port[0x8]; 4353 u8 pkey_index[0x10]; 4354 4355 u8 reserved_at_160[0x8]; 4356 u8 my_addr_index[0x8]; 4357 u8 reserved_at_170[0x8]; 4358 u8 hop_limit[0x8]; 4359 4360 u8 dc_access_key_violation_count[0x20]; 4361 4362 u8 reserved_at_1a0[0x14]; 4363 u8 dei_cfi[0x1]; 4364 u8 eth_prio[0x3]; 4365 u8 ecn[0x2]; 4366 u8 dscp[0x6]; 4367 4368 u8 reserved_at_1c0[0x20]; 4369 u8 ece[0x20]; 4370 }; 4371 4372 enum { 4373 MLX5_CQC_STATUS_OK = 0x0, 4374 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9, 4375 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa, 4376 }; 4377 4378 enum { 4379 MLX5_CQC_CQE_SZ_64_BYTES = 0x0, 4380 MLX5_CQC_CQE_SZ_128_BYTES = 0x1, 4381 }; 4382 4383 enum { 4384 MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED = 0x6, 4385 MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED = 0x9, 4386 MLX5_CQC_ST_FIRED = 0xa, 4387 }; 4388 4389 enum mlx5_cq_period_mode { 4390 MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0, 4391 MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1, 4392 MLX5_CQ_PERIOD_NUM_MODES, 4393 }; 4394 4395 struct mlx5_ifc_cqc_bits { 4396 u8 status[0x4]; 4397 u8 reserved_at_4[0x2]; 4398 u8 dbr_umem_valid[0x1]; 4399 u8 apu_cq[0x1]; 4400 u8 cqe_sz[0x3]; 4401 u8 cc[0x1]; 4402 u8 reserved_at_c[0x1]; 4403 u8 scqe_break_moderation_en[0x1]; 4404 u8 oi[0x1]; 4405 u8 cq_period_mode[0x2]; 4406 u8 cqe_comp_en[0x1]; 4407 u8 mini_cqe_res_format[0x2]; 4408 u8 st[0x4]; 4409 u8 reserved_at_18[0x6]; 4410 u8 cqe_compression_layout[0x2]; 4411 4412 u8 reserved_at_20[0x20]; 4413 4414 u8 reserved_at_40[0x14]; 4415 u8 page_offset[0x6]; 4416 u8 reserved_at_5a[0x6]; 4417 4418 u8 reserved_at_60[0x3]; 4419 u8 log_cq_size[0x5]; 4420 u8 uar_page[0x18]; 4421 4422 u8 reserved_at_80[0x4]; 4423 u8 cq_period[0xc]; 4424 u8 cq_max_count[0x10]; 4425 4426 u8 c_eqn_or_apu_element[0x20]; 4427 4428 u8 reserved_at_c0[0x3]; 4429 u8 log_page_size[0x5]; 4430 u8 reserved_at_c8[0x18]; 4431 4432 u8 reserved_at_e0[0x20]; 4433 4434 u8 reserved_at_100[0x8]; 4435 u8 last_notified_index[0x18]; 4436 4437 u8 reserved_at_120[0x8]; 4438 u8 last_solicit_index[0x18]; 4439 4440 u8 reserved_at_140[0x8]; 4441 u8 consumer_counter[0x18]; 4442 4443 u8 reserved_at_160[0x8]; 4444 u8 producer_counter[0x18]; 4445 4446 u8 reserved_at_180[0x40]; 4447 4448 u8 dbr_addr[0x40]; 4449 }; 4450 4451 union mlx5_ifc_cong_control_roce_ecn_auto_bits { 4452 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp; 4453 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp; 4454 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np; 4455 struct mlx5_ifc_cong_control_r_roce_general_bits cong_control_r_roce_general; 4456 u8 reserved_at_0[0x800]; 4457 }; 4458 4459 struct mlx5_ifc_query_adapter_param_block_bits { 4460 u8 reserved_at_0[0xc0]; 4461 4462 u8 reserved_at_c0[0x8]; 4463 u8 ieee_vendor_id[0x18]; 4464 4465 u8 reserved_at_e0[0x10]; 4466 u8 vsd_vendor_id[0x10]; 4467 4468 u8 vsd[208][0x8]; 4469 4470 u8 vsd_contd_psid[16][0x8]; 4471 }; 4472 4473 enum { 4474 MLX5_XRQC_STATE_GOOD = 0x0, 4475 MLX5_XRQC_STATE_ERROR = 0x1, 4476 }; 4477 4478 enum { 4479 MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0, 4480 MLX5_XRQC_TOPOLOGY_TAG_MATCHING = 0x1, 4481 }; 4482 4483 enum { 4484 MLX5_XRQC_OFFLOAD_RNDV = 0x1, 4485 }; 4486 4487 struct mlx5_ifc_tag_matching_topology_context_bits { 4488 u8 log_matching_list_sz[0x4]; 4489 u8 reserved_at_4[0xc]; 4490 u8 append_next_index[0x10]; 4491 4492 u8 sw_phase_cnt[0x10]; 4493 u8 hw_phase_cnt[0x10]; 4494 4495 u8 reserved_at_40[0x40]; 4496 }; 4497 4498 struct mlx5_ifc_xrqc_bits { 4499 u8 state[0x4]; 4500 u8 rlkey[0x1]; 4501 u8 reserved_at_5[0xf]; 4502 u8 topology[0x4]; 4503 u8 reserved_at_18[0x4]; 4504 u8 offload[0x4]; 4505 4506 u8 reserved_at_20[0x8]; 4507 u8 user_index[0x18]; 4508 4509 u8 reserved_at_40[0x8]; 4510 u8 cqn[0x18]; 4511 4512 u8 reserved_at_60[0xa0]; 4513 4514 struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context; 4515 4516 u8 reserved_at_180[0x280]; 4517 4518 struct mlx5_ifc_wq_bits wq; 4519 }; 4520 4521 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits { 4522 struct mlx5_ifc_modify_field_select_bits modify_field_select; 4523 struct mlx5_ifc_resize_field_select_bits resize_field_select; 4524 u8 reserved_at_0[0x20]; 4525 }; 4526 4527 union mlx5_ifc_field_select_802_1_r_roce_auto_bits { 4528 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp; 4529 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp; 4530 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np; 4531 u8 reserved_at_0[0x20]; 4532 }; 4533 4534 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits { 4535 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 4536 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 4537 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 4538 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 4539 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 4540 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 4541 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout; 4542 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout; 4543 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 4544 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 4545 struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs; 4546 u8 reserved_at_0[0x7c0]; 4547 }; 4548 4549 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits { 4550 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout; 4551 u8 reserved_at_0[0x7c0]; 4552 }; 4553 4554 union mlx5_ifc_event_auto_bits { 4555 struct mlx5_ifc_comp_event_bits comp_event; 4556 struct mlx5_ifc_dct_events_bits dct_events; 4557 struct mlx5_ifc_qp_events_bits qp_events; 4558 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event; 4559 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event; 4560 struct mlx5_ifc_cq_error_bits cq_error; 4561 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged; 4562 struct mlx5_ifc_port_state_change_event_bits port_state_change_event; 4563 struct mlx5_ifc_gpio_event_bits gpio_event; 4564 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event; 4565 struct mlx5_ifc_stall_vl_event_bits stall_vl_event; 4566 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event; 4567 u8 reserved_at_0[0xe0]; 4568 }; 4569 4570 struct mlx5_ifc_health_buffer_bits { 4571 u8 reserved_at_0[0x100]; 4572 4573 u8 assert_existptr[0x20]; 4574 4575 u8 assert_callra[0x20]; 4576 4577 u8 reserved_at_140[0x20]; 4578 4579 u8 time[0x20]; 4580 4581 u8 fw_version[0x20]; 4582 4583 u8 hw_id[0x20]; 4584 4585 u8 rfr[0x1]; 4586 u8 reserved_at_1c1[0x3]; 4587 u8 valid[0x1]; 4588 u8 severity[0x3]; 4589 u8 reserved_at_1c8[0x18]; 4590 4591 u8 irisc_index[0x8]; 4592 u8 synd[0x8]; 4593 u8 ext_synd[0x10]; 4594 }; 4595 4596 struct mlx5_ifc_register_loopback_control_bits { 4597 u8 no_lb[0x1]; 4598 u8 reserved_at_1[0x7]; 4599 u8 port[0x8]; 4600 u8 reserved_at_10[0x10]; 4601 4602 u8 reserved_at_20[0x60]; 4603 }; 4604 4605 struct mlx5_ifc_vport_tc_element_bits { 4606 u8 traffic_class[0x4]; 4607 u8 reserved_at_4[0xc]; 4608 u8 vport_number[0x10]; 4609 }; 4610 4611 struct mlx5_ifc_vport_element_bits { 4612 u8 reserved_at_0[0x10]; 4613 u8 vport_number[0x10]; 4614 }; 4615 4616 enum { 4617 TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0, 4618 TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1, 4619 TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2, 4620 }; 4621 4622 struct mlx5_ifc_tsar_element_bits { 4623 u8 reserved_at_0[0x8]; 4624 u8 tsar_type[0x8]; 4625 u8 reserved_at_10[0x10]; 4626 }; 4627 4628 enum { 4629 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0, 4630 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1, 4631 }; 4632 4633 struct mlx5_ifc_teardown_hca_out_bits { 4634 u8 status[0x8]; 4635 u8 reserved_at_8[0x18]; 4636 4637 u8 syndrome[0x20]; 4638 4639 u8 reserved_at_40[0x3f]; 4640 4641 u8 state[0x1]; 4642 }; 4643 4644 enum { 4645 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0, 4646 MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE = 0x1, 4647 MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN = 0x2, 4648 }; 4649 4650 struct mlx5_ifc_teardown_hca_in_bits { 4651 u8 opcode[0x10]; 4652 u8 reserved_at_10[0x10]; 4653 4654 u8 reserved_at_20[0x10]; 4655 u8 op_mod[0x10]; 4656 4657 u8 reserved_at_40[0x10]; 4658 u8 profile[0x10]; 4659 4660 u8 reserved_at_60[0x20]; 4661 }; 4662 4663 struct mlx5_ifc_sqerr2rts_qp_out_bits { 4664 u8 status[0x8]; 4665 u8 reserved_at_8[0x18]; 4666 4667 u8 syndrome[0x20]; 4668 4669 u8 reserved_at_40[0x40]; 4670 }; 4671 4672 struct mlx5_ifc_sqerr2rts_qp_in_bits { 4673 u8 opcode[0x10]; 4674 u8 uid[0x10]; 4675 4676 u8 reserved_at_20[0x10]; 4677 u8 op_mod[0x10]; 4678 4679 u8 reserved_at_40[0x8]; 4680 u8 qpn[0x18]; 4681 4682 u8 reserved_at_60[0x20]; 4683 4684 u8 opt_param_mask[0x20]; 4685 4686 u8 reserved_at_a0[0x20]; 4687 4688 struct mlx5_ifc_qpc_bits qpc; 4689 4690 u8 reserved_at_800[0x80]; 4691 }; 4692 4693 struct mlx5_ifc_sqd2rts_qp_out_bits { 4694 u8 status[0x8]; 4695 u8 reserved_at_8[0x18]; 4696 4697 u8 syndrome[0x20]; 4698 4699 u8 reserved_at_40[0x40]; 4700 }; 4701 4702 struct mlx5_ifc_sqd2rts_qp_in_bits { 4703 u8 opcode[0x10]; 4704 u8 uid[0x10]; 4705 4706 u8 reserved_at_20[0x10]; 4707 u8 op_mod[0x10]; 4708 4709 u8 reserved_at_40[0x8]; 4710 u8 qpn[0x18]; 4711 4712 u8 reserved_at_60[0x20]; 4713 4714 u8 opt_param_mask[0x20]; 4715 4716 u8 reserved_at_a0[0x20]; 4717 4718 struct mlx5_ifc_qpc_bits qpc; 4719 4720 u8 reserved_at_800[0x80]; 4721 }; 4722 4723 struct mlx5_ifc_set_roce_address_out_bits { 4724 u8 status[0x8]; 4725 u8 reserved_at_8[0x18]; 4726 4727 u8 syndrome[0x20]; 4728 4729 u8 reserved_at_40[0x40]; 4730 }; 4731 4732 struct mlx5_ifc_set_roce_address_in_bits { 4733 u8 opcode[0x10]; 4734 u8 reserved_at_10[0x10]; 4735 4736 u8 reserved_at_20[0x10]; 4737 u8 op_mod[0x10]; 4738 4739 u8 roce_address_index[0x10]; 4740 u8 reserved_at_50[0xc]; 4741 u8 vhca_port_num[0x4]; 4742 4743 u8 reserved_at_60[0x20]; 4744 4745 struct mlx5_ifc_roce_addr_layout_bits roce_address; 4746 }; 4747 4748 struct mlx5_ifc_set_mad_demux_out_bits { 4749 u8 status[0x8]; 4750 u8 reserved_at_8[0x18]; 4751 4752 u8 syndrome[0x20]; 4753 4754 u8 reserved_at_40[0x40]; 4755 }; 4756 4757 enum { 4758 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0, 4759 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2, 4760 }; 4761 4762 struct mlx5_ifc_set_mad_demux_in_bits { 4763 u8 opcode[0x10]; 4764 u8 reserved_at_10[0x10]; 4765 4766 u8 reserved_at_20[0x10]; 4767 u8 op_mod[0x10]; 4768 4769 u8 reserved_at_40[0x20]; 4770 4771 u8 reserved_at_60[0x6]; 4772 u8 demux_mode[0x2]; 4773 u8 reserved_at_68[0x18]; 4774 }; 4775 4776 struct mlx5_ifc_set_l2_table_entry_out_bits { 4777 u8 status[0x8]; 4778 u8 reserved_at_8[0x18]; 4779 4780 u8 syndrome[0x20]; 4781 4782 u8 reserved_at_40[0x40]; 4783 }; 4784 4785 struct mlx5_ifc_set_l2_table_entry_in_bits { 4786 u8 opcode[0x10]; 4787 u8 reserved_at_10[0x10]; 4788 4789 u8 reserved_at_20[0x10]; 4790 u8 op_mod[0x10]; 4791 4792 u8 reserved_at_40[0x60]; 4793 4794 u8 reserved_at_a0[0x8]; 4795 u8 table_index[0x18]; 4796 4797 u8 reserved_at_c0[0x20]; 4798 4799 u8 reserved_at_e0[0x10]; 4800 u8 silent_mode_valid[0x1]; 4801 u8 silent_mode[0x1]; 4802 u8 reserved_at_f2[0x1]; 4803 u8 vlan_valid[0x1]; 4804 u8 vlan[0xc]; 4805 4806 struct mlx5_ifc_mac_address_layout_bits mac_address; 4807 4808 u8 reserved_at_140[0xc0]; 4809 }; 4810 4811 struct mlx5_ifc_set_issi_out_bits { 4812 u8 status[0x8]; 4813 u8 reserved_at_8[0x18]; 4814 4815 u8 syndrome[0x20]; 4816 4817 u8 reserved_at_40[0x40]; 4818 }; 4819 4820 struct mlx5_ifc_set_issi_in_bits { 4821 u8 opcode[0x10]; 4822 u8 reserved_at_10[0x10]; 4823 4824 u8 reserved_at_20[0x10]; 4825 u8 op_mod[0x10]; 4826 4827 u8 reserved_at_40[0x10]; 4828 u8 current_issi[0x10]; 4829 4830 u8 reserved_at_60[0x20]; 4831 }; 4832 4833 struct mlx5_ifc_set_hca_cap_out_bits { 4834 u8 status[0x8]; 4835 u8 reserved_at_8[0x18]; 4836 4837 u8 syndrome[0x20]; 4838 4839 u8 reserved_at_40[0x40]; 4840 }; 4841 4842 struct mlx5_ifc_set_hca_cap_in_bits { 4843 u8 opcode[0x10]; 4844 u8 reserved_at_10[0x10]; 4845 4846 u8 reserved_at_20[0x10]; 4847 u8 op_mod[0x10]; 4848 4849 u8 other_function[0x1]; 4850 u8 ec_vf_function[0x1]; 4851 u8 reserved_at_42[0xe]; 4852 u8 function_id[0x10]; 4853 4854 u8 reserved_at_60[0x20]; 4855 4856 union mlx5_ifc_hca_cap_union_bits capability; 4857 }; 4858 4859 enum { 4860 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0, 4861 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1, 4862 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2, 4863 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3, 4864 MLX5_SET_FTE_MODIFY_ENABLE_MASK_IPSEC_OBJ_ID = 0x4 4865 }; 4866 4867 struct mlx5_ifc_set_fte_out_bits { 4868 u8 status[0x8]; 4869 u8 reserved_at_8[0x18]; 4870 4871 u8 syndrome[0x20]; 4872 4873 u8 reserved_at_40[0x40]; 4874 }; 4875 4876 struct mlx5_ifc_set_fte_in_bits { 4877 u8 opcode[0x10]; 4878 u8 reserved_at_10[0x10]; 4879 4880 u8 reserved_at_20[0x10]; 4881 u8 op_mod[0x10]; 4882 4883 u8 other_vport[0x1]; 4884 u8 reserved_at_41[0xf]; 4885 u8 vport_number[0x10]; 4886 4887 u8 reserved_at_60[0x20]; 4888 4889 u8 table_type[0x8]; 4890 u8 reserved_at_88[0x18]; 4891 4892 u8 reserved_at_a0[0x8]; 4893 u8 table_id[0x18]; 4894 4895 u8 ignore_flow_level[0x1]; 4896 u8 reserved_at_c1[0x17]; 4897 u8 modify_enable_mask[0x8]; 4898 4899 u8 reserved_at_e0[0x20]; 4900 4901 u8 flow_index[0x20]; 4902 4903 u8 reserved_at_120[0xe0]; 4904 4905 struct mlx5_ifc_flow_context_bits flow_context; 4906 }; 4907 4908 struct mlx5_ifc_rts2rts_qp_out_bits { 4909 u8 status[0x8]; 4910 u8 reserved_at_8[0x18]; 4911 4912 u8 syndrome[0x20]; 4913 4914 u8 reserved_at_40[0x20]; 4915 u8 ece[0x20]; 4916 }; 4917 4918 struct mlx5_ifc_rts2rts_qp_in_bits { 4919 u8 opcode[0x10]; 4920 u8 uid[0x10]; 4921 4922 u8 reserved_at_20[0x10]; 4923 u8 op_mod[0x10]; 4924 4925 u8 reserved_at_40[0x8]; 4926 u8 qpn[0x18]; 4927 4928 u8 reserved_at_60[0x20]; 4929 4930 u8 opt_param_mask[0x20]; 4931 4932 u8 ece[0x20]; 4933 4934 struct mlx5_ifc_qpc_bits qpc; 4935 4936 u8 reserved_at_800[0x80]; 4937 }; 4938 4939 struct mlx5_ifc_rtr2rts_qp_out_bits { 4940 u8 status[0x8]; 4941 u8 reserved_at_8[0x18]; 4942 4943 u8 syndrome[0x20]; 4944 4945 u8 reserved_at_40[0x20]; 4946 u8 ece[0x20]; 4947 }; 4948 4949 struct mlx5_ifc_rtr2rts_qp_in_bits { 4950 u8 opcode[0x10]; 4951 u8 uid[0x10]; 4952 4953 u8 reserved_at_20[0x10]; 4954 u8 op_mod[0x10]; 4955 4956 u8 reserved_at_40[0x8]; 4957 u8 qpn[0x18]; 4958 4959 u8 reserved_at_60[0x20]; 4960 4961 u8 opt_param_mask[0x20]; 4962 4963 u8 ece[0x20]; 4964 4965 struct mlx5_ifc_qpc_bits qpc; 4966 4967 u8 reserved_at_800[0x80]; 4968 }; 4969 4970 struct mlx5_ifc_rst2init_qp_out_bits { 4971 u8 status[0x8]; 4972 u8 reserved_at_8[0x18]; 4973 4974 u8 syndrome[0x20]; 4975 4976 u8 reserved_at_40[0x20]; 4977 u8 ece[0x20]; 4978 }; 4979 4980 struct mlx5_ifc_rst2init_qp_in_bits { 4981 u8 opcode[0x10]; 4982 u8 uid[0x10]; 4983 4984 u8 reserved_at_20[0x10]; 4985 u8 op_mod[0x10]; 4986 4987 u8 reserved_at_40[0x8]; 4988 u8 qpn[0x18]; 4989 4990 u8 reserved_at_60[0x20]; 4991 4992 u8 opt_param_mask[0x20]; 4993 4994 u8 ece[0x20]; 4995 4996 struct mlx5_ifc_qpc_bits qpc; 4997 4998 u8 reserved_at_800[0x80]; 4999 }; 5000 5001 struct mlx5_ifc_query_xrq_out_bits { 5002 u8 status[0x8]; 5003 u8 reserved_at_8[0x18]; 5004 5005 u8 syndrome[0x20]; 5006 5007 u8 reserved_at_40[0x40]; 5008 5009 struct mlx5_ifc_xrqc_bits xrq_context; 5010 }; 5011 5012 struct mlx5_ifc_query_xrq_in_bits { 5013 u8 opcode[0x10]; 5014 u8 reserved_at_10[0x10]; 5015 5016 u8 reserved_at_20[0x10]; 5017 u8 op_mod[0x10]; 5018 5019 u8 reserved_at_40[0x8]; 5020 u8 xrqn[0x18]; 5021 5022 u8 reserved_at_60[0x20]; 5023 }; 5024 5025 struct mlx5_ifc_query_xrc_srq_out_bits { 5026 u8 status[0x8]; 5027 u8 reserved_at_8[0x18]; 5028 5029 u8 syndrome[0x20]; 5030 5031 u8 reserved_at_40[0x40]; 5032 5033 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 5034 5035 u8 reserved_at_280[0x600]; 5036 5037 u8 pas[][0x40]; 5038 }; 5039 5040 struct mlx5_ifc_query_xrc_srq_in_bits { 5041 u8 opcode[0x10]; 5042 u8 reserved_at_10[0x10]; 5043 5044 u8 reserved_at_20[0x10]; 5045 u8 op_mod[0x10]; 5046 5047 u8 reserved_at_40[0x8]; 5048 u8 xrc_srqn[0x18]; 5049 5050 u8 reserved_at_60[0x20]; 5051 }; 5052 5053 enum { 5054 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0, 5055 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1, 5056 }; 5057 5058 struct mlx5_ifc_query_vport_state_out_bits { 5059 u8 status[0x8]; 5060 u8 reserved_at_8[0x18]; 5061 5062 u8 syndrome[0x20]; 5063 5064 u8 reserved_at_40[0x20]; 5065 5066 u8 reserved_at_60[0x18]; 5067 u8 admin_state[0x4]; 5068 u8 state[0x4]; 5069 }; 5070 5071 enum { 5072 MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT = 0x0, 5073 MLX5_VPORT_STATE_OP_MOD_ESW_VPORT = 0x1, 5074 MLX5_VPORT_STATE_OP_MOD_UPLINK = 0x2, 5075 }; 5076 5077 struct mlx5_ifc_arm_monitor_counter_in_bits { 5078 u8 opcode[0x10]; 5079 u8 uid[0x10]; 5080 5081 u8 reserved_at_20[0x10]; 5082 u8 op_mod[0x10]; 5083 5084 u8 reserved_at_40[0x20]; 5085 5086 u8 reserved_at_60[0x20]; 5087 }; 5088 5089 struct mlx5_ifc_arm_monitor_counter_out_bits { 5090 u8 status[0x8]; 5091 u8 reserved_at_8[0x18]; 5092 5093 u8 syndrome[0x20]; 5094 5095 u8 reserved_at_40[0x40]; 5096 }; 5097 5098 enum { 5099 MLX5_QUERY_MONITOR_CNT_TYPE_PPCNT = 0x0, 5100 MLX5_QUERY_MONITOR_CNT_TYPE_Q_COUNTER = 0x1, 5101 }; 5102 5103 enum mlx5_monitor_counter_ppcnt { 5104 MLX5_QUERY_MONITOR_PPCNT_IN_RANGE_LENGTH_ERRORS = 0x0, 5105 MLX5_QUERY_MONITOR_PPCNT_OUT_OF_RANGE_LENGTH_FIELD = 0x1, 5106 MLX5_QUERY_MONITOR_PPCNT_FRAME_TOO_LONG_ERRORS = 0x2, 5107 MLX5_QUERY_MONITOR_PPCNT_FRAME_CHECK_SEQUENCE_ERRORS = 0x3, 5108 MLX5_QUERY_MONITOR_PPCNT_ALIGNMENT_ERRORS = 0x4, 5109 MLX5_QUERY_MONITOR_PPCNT_IF_OUT_DISCARDS = 0x5, 5110 }; 5111 5112 enum { 5113 MLX5_QUERY_MONITOR_Q_COUNTER_RX_OUT_OF_BUFFER = 0x4, 5114 }; 5115 5116 struct mlx5_ifc_monitor_counter_output_bits { 5117 u8 reserved_at_0[0x4]; 5118 u8 type[0x4]; 5119 u8 reserved_at_8[0x8]; 5120 u8 counter[0x10]; 5121 5122 u8 counter_group_id[0x20]; 5123 }; 5124 5125 #define MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 (6) 5126 #define MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1 (1) 5127 #define MLX5_CMD_SET_MONITOR_NUM_COUNTER (MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 +\ 5128 MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1) 5129 5130 struct mlx5_ifc_set_monitor_counter_in_bits { 5131 u8 opcode[0x10]; 5132 u8 uid[0x10]; 5133 5134 u8 reserved_at_20[0x10]; 5135 u8 op_mod[0x10]; 5136 5137 u8 reserved_at_40[0x10]; 5138 u8 num_of_counters[0x10]; 5139 5140 u8 reserved_at_60[0x20]; 5141 5142 struct mlx5_ifc_monitor_counter_output_bits monitor_counter[MLX5_CMD_SET_MONITOR_NUM_COUNTER]; 5143 }; 5144 5145 struct mlx5_ifc_set_monitor_counter_out_bits { 5146 u8 status[0x8]; 5147 u8 reserved_at_8[0x18]; 5148 5149 u8 syndrome[0x20]; 5150 5151 u8 reserved_at_40[0x40]; 5152 }; 5153 5154 struct mlx5_ifc_query_vport_state_in_bits { 5155 u8 opcode[0x10]; 5156 u8 reserved_at_10[0x10]; 5157 5158 u8 reserved_at_20[0x10]; 5159 u8 op_mod[0x10]; 5160 5161 u8 other_vport[0x1]; 5162 u8 reserved_at_41[0xf]; 5163 u8 vport_number[0x10]; 5164 5165 u8 reserved_at_60[0x20]; 5166 }; 5167 5168 struct mlx5_ifc_query_vnic_env_out_bits { 5169 u8 status[0x8]; 5170 u8 reserved_at_8[0x18]; 5171 5172 u8 syndrome[0x20]; 5173 5174 u8 reserved_at_40[0x40]; 5175 5176 struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env; 5177 }; 5178 5179 enum { 5180 MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS = 0x0, 5181 }; 5182 5183 struct mlx5_ifc_query_vnic_env_in_bits { 5184 u8 opcode[0x10]; 5185 u8 reserved_at_10[0x10]; 5186 5187 u8 reserved_at_20[0x10]; 5188 u8 op_mod[0x10]; 5189 5190 u8 other_vport[0x1]; 5191 u8 reserved_at_41[0xf]; 5192 u8 vport_number[0x10]; 5193 5194 u8 reserved_at_60[0x20]; 5195 }; 5196 5197 struct mlx5_ifc_query_vport_counter_out_bits { 5198 u8 status[0x8]; 5199 u8 reserved_at_8[0x18]; 5200 5201 u8 syndrome[0x20]; 5202 5203 u8 reserved_at_40[0x40]; 5204 5205 struct mlx5_ifc_traffic_counter_bits received_errors; 5206 5207 struct mlx5_ifc_traffic_counter_bits transmit_errors; 5208 5209 struct mlx5_ifc_traffic_counter_bits received_ib_unicast; 5210 5211 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast; 5212 5213 struct mlx5_ifc_traffic_counter_bits received_ib_multicast; 5214 5215 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast; 5216 5217 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast; 5218 5219 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast; 5220 5221 struct mlx5_ifc_traffic_counter_bits received_eth_unicast; 5222 5223 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast; 5224 5225 struct mlx5_ifc_traffic_counter_bits received_eth_multicast; 5226 5227 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast; 5228 5229 struct mlx5_ifc_traffic_counter_bits local_loopback; 5230 5231 u8 reserved_at_700[0x980]; 5232 }; 5233 5234 enum { 5235 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0, 5236 }; 5237 5238 struct mlx5_ifc_query_vport_counter_in_bits { 5239 u8 opcode[0x10]; 5240 u8 reserved_at_10[0x10]; 5241 5242 u8 reserved_at_20[0x10]; 5243 u8 op_mod[0x10]; 5244 5245 u8 other_vport[0x1]; 5246 u8 reserved_at_41[0xb]; 5247 u8 port_num[0x4]; 5248 u8 vport_number[0x10]; 5249 5250 u8 reserved_at_60[0x60]; 5251 5252 u8 clear[0x1]; 5253 u8 reserved_at_c1[0x1f]; 5254 5255 u8 reserved_at_e0[0x20]; 5256 }; 5257 5258 struct mlx5_ifc_query_tis_out_bits { 5259 u8 status[0x8]; 5260 u8 reserved_at_8[0x18]; 5261 5262 u8 syndrome[0x20]; 5263 5264 u8 reserved_at_40[0x40]; 5265 5266 struct mlx5_ifc_tisc_bits tis_context; 5267 }; 5268 5269 struct mlx5_ifc_query_tis_in_bits { 5270 u8 opcode[0x10]; 5271 u8 reserved_at_10[0x10]; 5272 5273 u8 reserved_at_20[0x10]; 5274 u8 op_mod[0x10]; 5275 5276 u8 reserved_at_40[0x8]; 5277 u8 tisn[0x18]; 5278 5279 u8 reserved_at_60[0x20]; 5280 }; 5281 5282 struct mlx5_ifc_query_tir_out_bits { 5283 u8 status[0x8]; 5284 u8 reserved_at_8[0x18]; 5285 5286 u8 syndrome[0x20]; 5287 5288 u8 reserved_at_40[0xc0]; 5289 5290 struct mlx5_ifc_tirc_bits tir_context; 5291 }; 5292 5293 struct mlx5_ifc_query_tir_in_bits { 5294 u8 opcode[0x10]; 5295 u8 reserved_at_10[0x10]; 5296 5297 u8 reserved_at_20[0x10]; 5298 u8 op_mod[0x10]; 5299 5300 u8 reserved_at_40[0x8]; 5301 u8 tirn[0x18]; 5302 5303 u8 reserved_at_60[0x20]; 5304 }; 5305 5306 struct mlx5_ifc_query_srq_out_bits { 5307 u8 status[0x8]; 5308 u8 reserved_at_8[0x18]; 5309 5310 u8 syndrome[0x20]; 5311 5312 u8 reserved_at_40[0x40]; 5313 5314 struct mlx5_ifc_srqc_bits srq_context_entry; 5315 5316 u8 reserved_at_280[0x600]; 5317 5318 u8 pas[][0x40]; 5319 }; 5320 5321 struct mlx5_ifc_query_srq_in_bits { 5322 u8 opcode[0x10]; 5323 u8 reserved_at_10[0x10]; 5324 5325 u8 reserved_at_20[0x10]; 5326 u8 op_mod[0x10]; 5327 5328 u8 reserved_at_40[0x8]; 5329 u8 srqn[0x18]; 5330 5331 u8 reserved_at_60[0x20]; 5332 }; 5333 5334 struct mlx5_ifc_query_sq_out_bits { 5335 u8 status[0x8]; 5336 u8 reserved_at_8[0x18]; 5337 5338 u8 syndrome[0x20]; 5339 5340 u8 reserved_at_40[0xc0]; 5341 5342 struct mlx5_ifc_sqc_bits sq_context; 5343 }; 5344 5345 struct mlx5_ifc_query_sq_in_bits { 5346 u8 opcode[0x10]; 5347 u8 reserved_at_10[0x10]; 5348 5349 u8 reserved_at_20[0x10]; 5350 u8 op_mod[0x10]; 5351 5352 u8 reserved_at_40[0x8]; 5353 u8 sqn[0x18]; 5354 5355 u8 reserved_at_60[0x20]; 5356 }; 5357 5358 struct mlx5_ifc_query_special_contexts_out_bits { 5359 u8 status[0x8]; 5360 u8 reserved_at_8[0x18]; 5361 5362 u8 syndrome[0x20]; 5363 5364 u8 dump_fill_mkey[0x20]; 5365 5366 u8 resd_lkey[0x20]; 5367 5368 u8 null_mkey[0x20]; 5369 5370 u8 terminate_scatter_list_mkey[0x20]; 5371 5372 u8 repeated_mkey[0x20]; 5373 5374 u8 reserved_at_a0[0x20]; 5375 }; 5376 5377 struct mlx5_ifc_query_special_contexts_in_bits { 5378 u8 opcode[0x10]; 5379 u8 reserved_at_10[0x10]; 5380 5381 u8 reserved_at_20[0x10]; 5382 u8 op_mod[0x10]; 5383 5384 u8 reserved_at_40[0x40]; 5385 }; 5386 5387 struct mlx5_ifc_query_scheduling_element_out_bits { 5388 u8 opcode[0x10]; 5389 u8 reserved_at_10[0x10]; 5390 5391 u8 reserved_at_20[0x10]; 5392 u8 op_mod[0x10]; 5393 5394 u8 reserved_at_40[0xc0]; 5395 5396 struct mlx5_ifc_scheduling_context_bits scheduling_context; 5397 5398 u8 reserved_at_300[0x100]; 5399 }; 5400 5401 enum { 5402 SCHEDULING_HIERARCHY_E_SWITCH = 0x2, 5403 SCHEDULING_HIERARCHY_NIC = 0x3, 5404 }; 5405 5406 struct mlx5_ifc_query_scheduling_element_in_bits { 5407 u8 opcode[0x10]; 5408 u8 reserved_at_10[0x10]; 5409 5410 u8 reserved_at_20[0x10]; 5411 u8 op_mod[0x10]; 5412 5413 u8 scheduling_hierarchy[0x8]; 5414 u8 reserved_at_48[0x18]; 5415 5416 u8 scheduling_element_id[0x20]; 5417 5418 u8 reserved_at_80[0x180]; 5419 }; 5420 5421 struct mlx5_ifc_query_rqt_out_bits { 5422 u8 status[0x8]; 5423 u8 reserved_at_8[0x18]; 5424 5425 u8 syndrome[0x20]; 5426 5427 u8 reserved_at_40[0xc0]; 5428 5429 struct mlx5_ifc_rqtc_bits rqt_context; 5430 }; 5431 5432 struct mlx5_ifc_query_rqt_in_bits { 5433 u8 opcode[0x10]; 5434 u8 reserved_at_10[0x10]; 5435 5436 u8 reserved_at_20[0x10]; 5437 u8 op_mod[0x10]; 5438 5439 u8 reserved_at_40[0x8]; 5440 u8 rqtn[0x18]; 5441 5442 u8 reserved_at_60[0x20]; 5443 }; 5444 5445 struct mlx5_ifc_query_rq_out_bits { 5446 u8 status[0x8]; 5447 u8 reserved_at_8[0x18]; 5448 5449 u8 syndrome[0x20]; 5450 5451 u8 reserved_at_40[0xc0]; 5452 5453 struct mlx5_ifc_rqc_bits rq_context; 5454 }; 5455 5456 struct mlx5_ifc_query_rq_in_bits { 5457 u8 opcode[0x10]; 5458 u8 reserved_at_10[0x10]; 5459 5460 u8 reserved_at_20[0x10]; 5461 u8 op_mod[0x10]; 5462 5463 u8 reserved_at_40[0x8]; 5464 u8 rqn[0x18]; 5465 5466 u8 reserved_at_60[0x20]; 5467 }; 5468 5469 struct mlx5_ifc_query_roce_address_out_bits { 5470 u8 status[0x8]; 5471 u8 reserved_at_8[0x18]; 5472 5473 u8 syndrome[0x20]; 5474 5475 u8 reserved_at_40[0x40]; 5476 5477 struct mlx5_ifc_roce_addr_layout_bits roce_address; 5478 }; 5479 5480 struct mlx5_ifc_query_roce_address_in_bits { 5481 u8 opcode[0x10]; 5482 u8 reserved_at_10[0x10]; 5483 5484 u8 reserved_at_20[0x10]; 5485 u8 op_mod[0x10]; 5486 5487 u8 roce_address_index[0x10]; 5488 u8 reserved_at_50[0xc]; 5489 u8 vhca_port_num[0x4]; 5490 5491 u8 reserved_at_60[0x20]; 5492 }; 5493 5494 struct mlx5_ifc_query_rmp_out_bits { 5495 u8 status[0x8]; 5496 u8 reserved_at_8[0x18]; 5497 5498 u8 syndrome[0x20]; 5499 5500 u8 reserved_at_40[0xc0]; 5501 5502 struct mlx5_ifc_rmpc_bits rmp_context; 5503 }; 5504 5505 struct mlx5_ifc_query_rmp_in_bits { 5506 u8 opcode[0x10]; 5507 u8 reserved_at_10[0x10]; 5508 5509 u8 reserved_at_20[0x10]; 5510 u8 op_mod[0x10]; 5511 5512 u8 reserved_at_40[0x8]; 5513 u8 rmpn[0x18]; 5514 5515 u8 reserved_at_60[0x20]; 5516 }; 5517 5518 struct mlx5_ifc_cqe_error_syndrome_bits { 5519 u8 hw_error_syndrome[0x8]; 5520 u8 hw_syndrome_type[0x4]; 5521 u8 reserved_at_c[0x4]; 5522 u8 vendor_error_syndrome[0x8]; 5523 u8 syndrome[0x8]; 5524 }; 5525 5526 struct mlx5_ifc_qp_context_extension_bits { 5527 u8 reserved_at_0[0x60]; 5528 5529 struct mlx5_ifc_cqe_error_syndrome_bits error_syndrome; 5530 5531 u8 reserved_at_80[0x580]; 5532 }; 5533 5534 struct mlx5_ifc_qpc_extension_and_pas_list_in_bits { 5535 struct mlx5_ifc_qp_context_extension_bits qpc_data_extension; 5536 5537 u8 pas[0][0x40]; 5538 }; 5539 5540 struct mlx5_ifc_qp_pas_list_in_bits { 5541 struct mlx5_ifc_cmd_pas_bits pas[0]; 5542 }; 5543 5544 union mlx5_ifc_qp_pas_or_qpc_ext_and_pas_bits { 5545 struct mlx5_ifc_qp_pas_list_in_bits qp_pas_list; 5546 struct mlx5_ifc_qpc_extension_and_pas_list_in_bits qpc_ext_and_pas_list; 5547 }; 5548 5549 struct mlx5_ifc_query_qp_out_bits { 5550 u8 status[0x8]; 5551 u8 reserved_at_8[0x18]; 5552 5553 u8 syndrome[0x20]; 5554 5555 u8 reserved_at_40[0x40]; 5556 5557 u8 opt_param_mask[0x20]; 5558 5559 u8 ece[0x20]; 5560 5561 struct mlx5_ifc_qpc_bits qpc; 5562 5563 u8 reserved_at_800[0x80]; 5564 5565 union mlx5_ifc_qp_pas_or_qpc_ext_and_pas_bits qp_pas_or_qpc_ext_and_pas; 5566 }; 5567 5568 struct mlx5_ifc_query_qp_in_bits { 5569 u8 opcode[0x10]; 5570 u8 reserved_at_10[0x10]; 5571 5572 u8 reserved_at_20[0x10]; 5573 u8 op_mod[0x10]; 5574 5575 u8 qpc_ext[0x1]; 5576 u8 reserved_at_41[0x7]; 5577 u8 qpn[0x18]; 5578 5579 u8 reserved_at_60[0x20]; 5580 }; 5581 5582 struct mlx5_ifc_query_q_counter_out_bits { 5583 u8 status[0x8]; 5584 u8 reserved_at_8[0x18]; 5585 5586 u8 syndrome[0x20]; 5587 5588 u8 reserved_at_40[0x40]; 5589 5590 u8 rx_write_requests[0x20]; 5591 5592 u8 reserved_at_a0[0x20]; 5593 5594 u8 rx_read_requests[0x20]; 5595 5596 u8 reserved_at_e0[0x20]; 5597 5598 u8 rx_atomic_requests[0x20]; 5599 5600 u8 reserved_at_120[0x20]; 5601 5602 u8 rx_dct_connect[0x20]; 5603 5604 u8 reserved_at_160[0x20]; 5605 5606 u8 out_of_buffer[0x20]; 5607 5608 u8 reserved_at_1a0[0x20]; 5609 5610 u8 out_of_sequence[0x20]; 5611 5612 u8 reserved_at_1e0[0x20]; 5613 5614 u8 duplicate_request[0x20]; 5615 5616 u8 reserved_at_220[0x20]; 5617 5618 u8 rnr_nak_retry_err[0x20]; 5619 5620 u8 reserved_at_260[0x20]; 5621 5622 u8 packet_seq_err[0x20]; 5623 5624 u8 reserved_at_2a0[0x20]; 5625 5626 u8 implied_nak_seq_err[0x20]; 5627 5628 u8 reserved_at_2e0[0x20]; 5629 5630 u8 local_ack_timeout_err[0x20]; 5631 5632 u8 reserved_at_320[0xa0]; 5633 5634 u8 resp_local_length_error[0x20]; 5635 5636 u8 req_local_length_error[0x20]; 5637 5638 u8 resp_local_qp_error[0x20]; 5639 5640 u8 local_operation_error[0x20]; 5641 5642 u8 resp_local_protection[0x20]; 5643 5644 u8 req_local_protection[0x20]; 5645 5646 u8 resp_cqe_error[0x20]; 5647 5648 u8 req_cqe_error[0x20]; 5649 5650 u8 req_mw_binding[0x20]; 5651 5652 u8 req_bad_response[0x20]; 5653 5654 u8 req_remote_invalid_request[0x20]; 5655 5656 u8 resp_remote_invalid_request[0x20]; 5657 5658 u8 req_remote_access_errors[0x20]; 5659 5660 u8 resp_remote_access_errors[0x20]; 5661 5662 u8 req_remote_operation_errors[0x20]; 5663 5664 u8 req_transport_retries_exceeded[0x20]; 5665 5666 u8 cq_overflow[0x20]; 5667 5668 u8 resp_cqe_flush_error[0x20]; 5669 5670 u8 req_cqe_flush_error[0x20]; 5671 5672 u8 reserved_at_620[0x20]; 5673 5674 u8 roce_adp_retrans[0x20]; 5675 5676 u8 roce_adp_retrans_to[0x20]; 5677 5678 u8 roce_slow_restart[0x20]; 5679 5680 u8 roce_slow_restart_cnps[0x20]; 5681 5682 u8 roce_slow_restart_trans[0x20]; 5683 5684 u8 reserved_at_6e0[0x120]; 5685 }; 5686 5687 struct mlx5_ifc_query_q_counter_in_bits { 5688 u8 opcode[0x10]; 5689 u8 reserved_at_10[0x10]; 5690 5691 u8 reserved_at_20[0x10]; 5692 u8 op_mod[0x10]; 5693 5694 u8 other_vport[0x1]; 5695 u8 reserved_at_41[0xf]; 5696 u8 vport_number[0x10]; 5697 5698 u8 reserved_at_60[0x60]; 5699 5700 u8 clear[0x1]; 5701 u8 aggregate[0x1]; 5702 u8 reserved_at_c2[0x1e]; 5703 5704 u8 reserved_at_e0[0x18]; 5705 u8 counter_set_id[0x8]; 5706 }; 5707 5708 struct mlx5_ifc_query_pages_out_bits { 5709 u8 status[0x8]; 5710 u8 reserved_at_8[0x18]; 5711 5712 u8 syndrome[0x20]; 5713 5714 u8 embedded_cpu_function[0x1]; 5715 u8 reserved_at_41[0xf]; 5716 u8 function_id[0x10]; 5717 5718 u8 num_pages[0x20]; 5719 }; 5720 5721 enum { 5722 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1, 5723 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2, 5724 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3, 5725 }; 5726 5727 struct mlx5_ifc_query_pages_in_bits { 5728 u8 opcode[0x10]; 5729 u8 reserved_at_10[0x10]; 5730 5731 u8 reserved_at_20[0x10]; 5732 u8 op_mod[0x10]; 5733 5734 u8 embedded_cpu_function[0x1]; 5735 u8 reserved_at_41[0xf]; 5736 u8 function_id[0x10]; 5737 5738 u8 reserved_at_60[0x20]; 5739 }; 5740 5741 struct mlx5_ifc_query_nic_vport_context_out_bits { 5742 u8 status[0x8]; 5743 u8 reserved_at_8[0x18]; 5744 5745 u8 syndrome[0x20]; 5746 5747 u8 reserved_at_40[0x40]; 5748 5749 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 5750 }; 5751 5752 struct mlx5_ifc_query_nic_vport_context_in_bits { 5753 u8 opcode[0x10]; 5754 u8 reserved_at_10[0x10]; 5755 5756 u8 reserved_at_20[0x10]; 5757 u8 op_mod[0x10]; 5758 5759 u8 other_vport[0x1]; 5760 u8 reserved_at_41[0xf]; 5761 u8 vport_number[0x10]; 5762 5763 u8 reserved_at_60[0x5]; 5764 u8 allowed_list_type[0x3]; 5765 u8 reserved_at_68[0x18]; 5766 }; 5767 5768 struct mlx5_ifc_query_mkey_out_bits { 5769 u8 status[0x8]; 5770 u8 reserved_at_8[0x18]; 5771 5772 u8 syndrome[0x20]; 5773 5774 u8 reserved_at_40[0x40]; 5775 5776 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 5777 5778 u8 reserved_at_280[0x600]; 5779 5780 u8 bsf0_klm0_pas_mtt0_1[16][0x8]; 5781 5782 u8 bsf1_klm1_pas_mtt2_3[16][0x8]; 5783 }; 5784 5785 struct mlx5_ifc_query_mkey_in_bits { 5786 u8 opcode[0x10]; 5787 u8 reserved_at_10[0x10]; 5788 5789 u8 reserved_at_20[0x10]; 5790 u8 op_mod[0x10]; 5791 5792 u8 reserved_at_40[0x8]; 5793 u8 mkey_index[0x18]; 5794 5795 u8 pg_access[0x1]; 5796 u8 reserved_at_61[0x1f]; 5797 }; 5798 5799 struct mlx5_ifc_query_mad_demux_out_bits { 5800 u8 status[0x8]; 5801 u8 reserved_at_8[0x18]; 5802 5803 u8 syndrome[0x20]; 5804 5805 u8 reserved_at_40[0x40]; 5806 5807 u8 mad_dumux_parameters_block[0x20]; 5808 }; 5809 5810 struct mlx5_ifc_query_mad_demux_in_bits { 5811 u8 opcode[0x10]; 5812 u8 reserved_at_10[0x10]; 5813 5814 u8 reserved_at_20[0x10]; 5815 u8 op_mod[0x10]; 5816 5817 u8 reserved_at_40[0x40]; 5818 }; 5819 5820 struct mlx5_ifc_query_l2_table_entry_out_bits { 5821 u8 status[0x8]; 5822 u8 reserved_at_8[0x18]; 5823 5824 u8 syndrome[0x20]; 5825 5826 u8 reserved_at_40[0xa0]; 5827 5828 u8 reserved_at_e0[0x13]; 5829 u8 vlan_valid[0x1]; 5830 u8 vlan[0xc]; 5831 5832 struct mlx5_ifc_mac_address_layout_bits mac_address; 5833 5834 u8 reserved_at_140[0xc0]; 5835 }; 5836 5837 struct mlx5_ifc_query_l2_table_entry_in_bits { 5838 u8 opcode[0x10]; 5839 u8 reserved_at_10[0x10]; 5840 5841 u8 reserved_at_20[0x10]; 5842 u8 op_mod[0x10]; 5843 5844 u8 reserved_at_40[0x60]; 5845 5846 u8 reserved_at_a0[0x8]; 5847 u8 table_index[0x18]; 5848 5849 u8 reserved_at_c0[0x140]; 5850 }; 5851 5852 struct mlx5_ifc_query_issi_out_bits { 5853 u8 status[0x8]; 5854 u8 reserved_at_8[0x18]; 5855 5856 u8 syndrome[0x20]; 5857 5858 u8 reserved_at_40[0x10]; 5859 u8 current_issi[0x10]; 5860 5861 u8 reserved_at_60[0xa0]; 5862 5863 u8 reserved_at_100[76][0x8]; 5864 u8 supported_issi_dw0[0x20]; 5865 }; 5866 5867 struct mlx5_ifc_query_issi_in_bits { 5868 u8 opcode[0x10]; 5869 u8 reserved_at_10[0x10]; 5870 5871 u8 reserved_at_20[0x10]; 5872 u8 op_mod[0x10]; 5873 5874 u8 reserved_at_40[0x40]; 5875 }; 5876 5877 struct mlx5_ifc_set_driver_version_out_bits { 5878 u8 status[0x8]; 5879 u8 reserved_0[0x18]; 5880 5881 u8 syndrome[0x20]; 5882 u8 reserved_1[0x40]; 5883 }; 5884 5885 struct mlx5_ifc_set_driver_version_in_bits { 5886 u8 opcode[0x10]; 5887 u8 reserved_0[0x10]; 5888 5889 u8 reserved_1[0x10]; 5890 u8 op_mod[0x10]; 5891 5892 u8 reserved_2[0x40]; 5893 u8 driver_version[64][0x8]; 5894 }; 5895 5896 struct mlx5_ifc_query_hca_vport_pkey_out_bits { 5897 u8 status[0x8]; 5898 u8 reserved_at_8[0x18]; 5899 5900 u8 syndrome[0x20]; 5901 5902 u8 reserved_at_40[0x40]; 5903 5904 struct mlx5_ifc_pkey_bits pkey[]; 5905 }; 5906 5907 struct mlx5_ifc_query_hca_vport_pkey_in_bits { 5908 u8 opcode[0x10]; 5909 u8 reserved_at_10[0x10]; 5910 5911 u8 reserved_at_20[0x10]; 5912 u8 op_mod[0x10]; 5913 5914 u8 other_vport[0x1]; 5915 u8 reserved_at_41[0xb]; 5916 u8 port_num[0x4]; 5917 u8 vport_number[0x10]; 5918 5919 u8 reserved_at_60[0x10]; 5920 u8 pkey_index[0x10]; 5921 }; 5922 5923 enum { 5924 MLX5_HCA_VPORT_SEL_PORT_GUID = 1 << 0, 5925 MLX5_HCA_VPORT_SEL_NODE_GUID = 1 << 1, 5926 MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2, 5927 }; 5928 5929 struct mlx5_ifc_query_hca_vport_gid_out_bits { 5930 u8 status[0x8]; 5931 u8 reserved_at_8[0x18]; 5932 5933 u8 syndrome[0x20]; 5934 5935 u8 reserved_at_40[0x20]; 5936 5937 u8 gids_num[0x10]; 5938 u8 reserved_at_70[0x10]; 5939 5940 struct mlx5_ifc_array128_auto_bits gid[]; 5941 }; 5942 5943 struct mlx5_ifc_query_hca_vport_gid_in_bits { 5944 u8 opcode[0x10]; 5945 u8 reserved_at_10[0x10]; 5946 5947 u8 reserved_at_20[0x10]; 5948 u8 op_mod[0x10]; 5949 5950 u8 other_vport[0x1]; 5951 u8 reserved_at_41[0xb]; 5952 u8 port_num[0x4]; 5953 u8 vport_number[0x10]; 5954 5955 u8 reserved_at_60[0x10]; 5956 u8 gid_index[0x10]; 5957 }; 5958 5959 struct mlx5_ifc_query_hca_vport_context_out_bits { 5960 u8 status[0x8]; 5961 u8 reserved_at_8[0x18]; 5962 5963 u8 syndrome[0x20]; 5964 5965 u8 reserved_at_40[0x40]; 5966 5967 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 5968 }; 5969 5970 struct mlx5_ifc_query_hca_vport_context_in_bits { 5971 u8 opcode[0x10]; 5972 u8 reserved_at_10[0x10]; 5973 5974 u8 reserved_at_20[0x10]; 5975 u8 op_mod[0x10]; 5976 5977 u8 other_vport[0x1]; 5978 u8 reserved_at_41[0xb]; 5979 u8 port_num[0x4]; 5980 u8 vport_number[0x10]; 5981 5982 u8 reserved_at_60[0x20]; 5983 }; 5984 5985 struct mlx5_ifc_query_hca_cap_out_bits { 5986 u8 status[0x8]; 5987 u8 reserved_at_8[0x18]; 5988 5989 u8 syndrome[0x20]; 5990 5991 u8 reserved_at_40[0x40]; 5992 5993 union mlx5_ifc_hca_cap_union_bits capability; 5994 }; 5995 5996 struct mlx5_ifc_query_hca_cap_in_bits { 5997 u8 opcode[0x10]; 5998 u8 reserved_at_10[0x10]; 5999 6000 u8 reserved_at_20[0x10]; 6001 u8 op_mod[0x10]; 6002 6003 u8 other_function[0x1]; 6004 u8 ec_vf_function[0x1]; 6005 u8 reserved_at_42[0xe]; 6006 u8 function_id[0x10]; 6007 6008 u8 reserved_at_60[0x20]; 6009 }; 6010 6011 struct mlx5_ifc_other_hca_cap_bits { 6012 u8 roce[0x1]; 6013 u8 reserved_at_1[0x27f]; 6014 }; 6015 6016 struct mlx5_ifc_query_other_hca_cap_out_bits { 6017 u8 status[0x8]; 6018 u8 reserved_at_8[0x18]; 6019 6020 u8 syndrome[0x20]; 6021 6022 u8 reserved_at_40[0x40]; 6023 6024 struct mlx5_ifc_other_hca_cap_bits other_capability; 6025 }; 6026 6027 struct mlx5_ifc_query_other_hca_cap_in_bits { 6028 u8 opcode[0x10]; 6029 u8 reserved_at_10[0x10]; 6030 6031 u8 reserved_at_20[0x10]; 6032 u8 op_mod[0x10]; 6033 6034 u8 reserved_at_40[0x10]; 6035 u8 function_id[0x10]; 6036 6037 u8 reserved_at_60[0x20]; 6038 }; 6039 6040 struct mlx5_ifc_modify_other_hca_cap_out_bits { 6041 u8 status[0x8]; 6042 u8 reserved_at_8[0x18]; 6043 6044 u8 syndrome[0x20]; 6045 6046 u8 reserved_at_40[0x40]; 6047 }; 6048 6049 struct mlx5_ifc_modify_other_hca_cap_in_bits { 6050 u8 opcode[0x10]; 6051 u8 reserved_at_10[0x10]; 6052 6053 u8 reserved_at_20[0x10]; 6054 u8 op_mod[0x10]; 6055 6056 u8 reserved_at_40[0x10]; 6057 u8 function_id[0x10]; 6058 u8 field_select[0x20]; 6059 6060 struct mlx5_ifc_other_hca_cap_bits other_capability; 6061 }; 6062 6063 struct mlx5_ifc_flow_table_context_bits { 6064 u8 reformat_en[0x1]; 6065 u8 decap_en[0x1]; 6066 u8 sw_owner[0x1]; 6067 u8 termination_table[0x1]; 6068 u8 table_miss_action[0x4]; 6069 u8 level[0x8]; 6070 u8 reserved_at_10[0x8]; 6071 u8 log_size[0x8]; 6072 6073 u8 reserved_at_20[0x8]; 6074 u8 table_miss_id[0x18]; 6075 6076 u8 reserved_at_40[0x8]; 6077 u8 lag_master_next_table_id[0x18]; 6078 6079 u8 reserved_at_60[0x60]; 6080 6081 u8 sw_owner_icm_root_1[0x40]; 6082 6083 u8 sw_owner_icm_root_0[0x40]; 6084 6085 }; 6086 6087 struct mlx5_ifc_query_flow_table_out_bits { 6088 u8 status[0x8]; 6089 u8 reserved_at_8[0x18]; 6090 6091 u8 syndrome[0x20]; 6092 6093 u8 reserved_at_40[0x80]; 6094 6095 struct mlx5_ifc_flow_table_context_bits flow_table_context; 6096 }; 6097 6098 struct mlx5_ifc_query_flow_table_in_bits { 6099 u8 opcode[0x10]; 6100 u8 reserved_at_10[0x10]; 6101 6102 u8 reserved_at_20[0x10]; 6103 u8 op_mod[0x10]; 6104 6105 u8 reserved_at_40[0x40]; 6106 6107 u8 table_type[0x8]; 6108 u8 reserved_at_88[0x18]; 6109 6110 u8 reserved_at_a0[0x8]; 6111 u8 table_id[0x18]; 6112 6113 u8 reserved_at_c0[0x140]; 6114 }; 6115 6116 struct mlx5_ifc_query_fte_out_bits { 6117 u8 status[0x8]; 6118 u8 reserved_at_8[0x18]; 6119 6120 u8 syndrome[0x20]; 6121 6122 u8 reserved_at_40[0x1c0]; 6123 6124 struct mlx5_ifc_flow_context_bits flow_context; 6125 }; 6126 6127 struct mlx5_ifc_query_fte_in_bits { 6128 u8 opcode[0x10]; 6129 u8 reserved_at_10[0x10]; 6130 6131 u8 reserved_at_20[0x10]; 6132 u8 op_mod[0x10]; 6133 6134 u8 reserved_at_40[0x40]; 6135 6136 u8 table_type[0x8]; 6137 u8 reserved_at_88[0x18]; 6138 6139 u8 reserved_at_a0[0x8]; 6140 u8 table_id[0x18]; 6141 6142 u8 reserved_at_c0[0x40]; 6143 6144 u8 flow_index[0x20]; 6145 6146 u8 reserved_at_120[0xe0]; 6147 }; 6148 6149 struct mlx5_ifc_match_definer_format_0_bits { 6150 u8 reserved_at_0[0x100]; 6151 6152 u8 metadata_reg_c_0[0x20]; 6153 6154 u8 metadata_reg_c_1[0x20]; 6155 6156 u8 outer_dmac_47_16[0x20]; 6157 6158 u8 outer_dmac_15_0[0x10]; 6159 u8 outer_ethertype[0x10]; 6160 6161 u8 reserved_at_180[0x1]; 6162 u8 sx_sniffer[0x1]; 6163 u8 functional_lb[0x1]; 6164 u8 outer_ip_frag[0x1]; 6165 u8 outer_qp_type[0x2]; 6166 u8 outer_encap_type[0x2]; 6167 u8 port_number[0x2]; 6168 u8 outer_l3_type[0x2]; 6169 u8 outer_l4_type[0x2]; 6170 u8 outer_first_vlan_type[0x2]; 6171 u8 outer_first_vlan_prio[0x3]; 6172 u8 outer_first_vlan_cfi[0x1]; 6173 u8 outer_first_vlan_vid[0xc]; 6174 6175 u8 outer_l4_type_ext[0x4]; 6176 u8 reserved_at_1a4[0x2]; 6177 u8 outer_ipsec_layer[0x2]; 6178 u8 outer_l2_type[0x2]; 6179 u8 force_lb[0x1]; 6180 u8 outer_l2_ok[0x1]; 6181 u8 outer_l3_ok[0x1]; 6182 u8 outer_l4_ok[0x1]; 6183 u8 outer_second_vlan_type[0x2]; 6184 u8 outer_second_vlan_prio[0x3]; 6185 u8 outer_second_vlan_cfi[0x1]; 6186 u8 outer_second_vlan_vid[0xc]; 6187 6188 u8 outer_smac_47_16[0x20]; 6189 6190 u8 outer_smac_15_0[0x10]; 6191 u8 inner_ipv4_checksum_ok[0x1]; 6192 u8 inner_l4_checksum_ok[0x1]; 6193 u8 outer_ipv4_checksum_ok[0x1]; 6194 u8 outer_l4_checksum_ok[0x1]; 6195 u8 inner_l3_ok[0x1]; 6196 u8 inner_l4_ok[0x1]; 6197 u8 outer_l3_ok_duplicate[0x1]; 6198 u8 outer_l4_ok_duplicate[0x1]; 6199 u8 outer_tcp_cwr[0x1]; 6200 u8 outer_tcp_ece[0x1]; 6201 u8 outer_tcp_urg[0x1]; 6202 u8 outer_tcp_ack[0x1]; 6203 u8 outer_tcp_psh[0x1]; 6204 u8 outer_tcp_rst[0x1]; 6205 u8 outer_tcp_syn[0x1]; 6206 u8 outer_tcp_fin[0x1]; 6207 }; 6208 6209 struct mlx5_ifc_match_definer_format_22_bits { 6210 u8 reserved_at_0[0x100]; 6211 6212 u8 outer_ip_src_addr[0x20]; 6213 6214 u8 outer_ip_dest_addr[0x20]; 6215 6216 u8 outer_l4_sport[0x10]; 6217 u8 outer_l4_dport[0x10]; 6218 6219 u8 reserved_at_160[0x1]; 6220 u8 sx_sniffer[0x1]; 6221 u8 functional_lb[0x1]; 6222 u8 outer_ip_frag[0x1]; 6223 u8 outer_qp_type[0x2]; 6224 u8 outer_encap_type[0x2]; 6225 u8 port_number[0x2]; 6226 u8 outer_l3_type[0x2]; 6227 u8 outer_l4_type[0x2]; 6228 u8 outer_first_vlan_type[0x2]; 6229 u8 outer_first_vlan_prio[0x3]; 6230 u8 outer_first_vlan_cfi[0x1]; 6231 u8 outer_first_vlan_vid[0xc]; 6232 6233 u8 metadata_reg_c_0[0x20]; 6234 6235 u8 outer_dmac_47_16[0x20]; 6236 6237 u8 outer_smac_47_16[0x20]; 6238 6239 u8 outer_smac_15_0[0x10]; 6240 u8 outer_dmac_15_0[0x10]; 6241 }; 6242 6243 struct mlx5_ifc_match_definer_format_23_bits { 6244 u8 reserved_at_0[0x100]; 6245 6246 u8 inner_ip_src_addr[0x20]; 6247 6248 u8 inner_ip_dest_addr[0x20]; 6249 6250 u8 inner_l4_sport[0x10]; 6251 u8 inner_l4_dport[0x10]; 6252 6253 u8 reserved_at_160[0x1]; 6254 u8 sx_sniffer[0x1]; 6255 u8 functional_lb[0x1]; 6256 u8 inner_ip_frag[0x1]; 6257 u8 inner_qp_type[0x2]; 6258 u8 inner_encap_type[0x2]; 6259 u8 port_number[0x2]; 6260 u8 inner_l3_type[0x2]; 6261 u8 inner_l4_type[0x2]; 6262 u8 inner_first_vlan_type[0x2]; 6263 u8 inner_first_vlan_prio[0x3]; 6264 u8 inner_first_vlan_cfi[0x1]; 6265 u8 inner_first_vlan_vid[0xc]; 6266 6267 u8 tunnel_header_0[0x20]; 6268 6269 u8 inner_dmac_47_16[0x20]; 6270 6271 u8 inner_smac_47_16[0x20]; 6272 6273 u8 inner_smac_15_0[0x10]; 6274 u8 inner_dmac_15_0[0x10]; 6275 }; 6276 6277 struct mlx5_ifc_match_definer_format_29_bits { 6278 u8 reserved_at_0[0xc0]; 6279 6280 u8 outer_ip_dest_addr[0x80]; 6281 6282 u8 outer_ip_src_addr[0x80]; 6283 6284 u8 outer_l4_sport[0x10]; 6285 u8 outer_l4_dport[0x10]; 6286 6287 u8 reserved_at_1e0[0x20]; 6288 }; 6289 6290 struct mlx5_ifc_match_definer_format_30_bits { 6291 u8 reserved_at_0[0xa0]; 6292 6293 u8 outer_ip_dest_addr[0x80]; 6294 6295 u8 outer_ip_src_addr[0x80]; 6296 6297 u8 outer_dmac_47_16[0x20]; 6298 6299 u8 outer_smac_47_16[0x20]; 6300 6301 u8 outer_smac_15_0[0x10]; 6302 u8 outer_dmac_15_0[0x10]; 6303 }; 6304 6305 struct mlx5_ifc_match_definer_format_31_bits { 6306 u8 reserved_at_0[0xc0]; 6307 6308 u8 inner_ip_dest_addr[0x80]; 6309 6310 u8 inner_ip_src_addr[0x80]; 6311 6312 u8 inner_l4_sport[0x10]; 6313 u8 inner_l4_dport[0x10]; 6314 6315 u8 reserved_at_1e0[0x20]; 6316 }; 6317 6318 struct mlx5_ifc_match_definer_format_32_bits { 6319 u8 reserved_at_0[0xa0]; 6320 6321 u8 inner_ip_dest_addr[0x80]; 6322 6323 u8 inner_ip_src_addr[0x80]; 6324 6325 u8 inner_dmac_47_16[0x20]; 6326 6327 u8 inner_smac_47_16[0x20]; 6328 6329 u8 inner_smac_15_0[0x10]; 6330 u8 inner_dmac_15_0[0x10]; 6331 }; 6332 6333 enum { 6334 MLX5_IFC_DEFINER_FORMAT_ID_SELECT = 61, 6335 }; 6336 6337 #define MLX5_IFC_DEFINER_FORMAT_OFFSET_UNUSED 0x0 6338 #define MLX5_IFC_DEFINER_FORMAT_OFFSET_OUTER_ETH_PKT_LEN 0x48 6339 #define MLX5_IFC_DEFINER_DW_SELECTORS_NUM 9 6340 #define MLX5_IFC_DEFINER_BYTE_SELECTORS_NUM 8 6341 6342 struct mlx5_ifc_match_definer_match_mask_bits { 6343 u8 reserved_at_1c0[5][0x20]; 6344 u8 match_dw_8[0x20]; 6345 u8 match_dw_7[0x20]; 6346 u8 match_dw_6[0x20]; 6347 u8 match_dw_5[0x20]; 6348 u8 match_dw_4[0x20]; 6349 u8 match_dw_3[0x20]; 6350 u8 match_dw_2[0x20]; 6351 u8 match_dw_1[0x20]; 6352 u8 match_dw_0[0x20]; 6353 6354 u8 match_byte_7[0x8]; 6355 u8 match_byte_6[0x8]; 6356 u8 match_byte_5[0x8]; 6357 u8 match_byte_4[0x8]; 6358 6359 u8 match_byte_3[0x8]; 6360 u8 match_byte_2[0x8]; 6361 u8 match_byte_1[0x8]; 6362 u8 match_byte_0[0x8]; 6363 }; 6364 6365 struct mlx5_ifc_match_definer_bits { 6366 u8 modify_field_select[0x40]; 6367 6368 u8 reserved_at_40[0x40]; 6369 6370 u8 reserved_at_80[0x10]; 6371 u8 format_id[0x10]; 6372 6373 u8 reserved_at_a0[0x60]; 6374 6375 u8 format_select_dw3[0x8]; 6376 u8 format_select_dw2[0x8]; 6377 u8 format_select_dw1[0x8]; 6378 u8 format_select_dw0[0x8]; 6379 6380 u8 format_select_dw7[0x8]; 6381 u8 format_select_dw6[0x8]; 6382 u8 format_select_dw5[0x8]; 6383 u8 format_select_dw4[0x8]; 6384 6385 u8 reserved_at_100[0x18]; 6386 u8 format_select_dw8[0x8]; 6387 6388 u8 reserved_at_120[0x20]; 6389 6390 u8 format_select_byte3[0x8]; 6391 u8 format_select_byte2[0x8]; 6392 u8 format_select_byte1[0x8]; 6393 u8 format_select_byte0[0x8]; 6394 6395 u8 format_select_byte7[0x8]; 6396 u8 format_select_byte6[0x8]; 6397 u8 format_select_byte5[0x8]; 6398 u8 format_select_byte4[0x8]; 6399 6400 u8 reserved_at_180[0x40]; 6401 6402 union { 6403 struct { 6404 u8 match_mask[16][0x20]; 6405 }; 6406 struct mlx5_ifc_match_definer_match_mask_bits match_mask_format; 6407 }; 6408 }; 6409 6410 struct mlx5_ifc_general_obj_create_param_bits { 6411 u8 alias_object[0x1]; 6412 u8 reserved_at_1[0x2]; 6413 u8 log_obj_range[0x5]; 6414 u8 reserved_at_8[0x18]; 6415 }; 6416 6417 struct mlx5_ifc_general_obj_query_param_bits { 6418 u8 alias_object[0x1]; 6419 u8 obj_offset[0x1f]; 6420 }; 6421 6422 struct mlx5_ifc_general_obj_in_cmd_hdr_bits { 6423 u8 opcode[0x10]; 6424 u8 uid[0x10]; 6425 6426 u8 vhca_tunnel_id[0x10]; 6427 u8 obj_type[0x10]; 6428 6429 u8 obj_id[0x20]; 6430 6431 union { 6432 struct mlx5_ifc_general_obj_create_param_bits create; 6433 struct mlx5_ifc_general_obj_query_param_bits query; 6434 } op_param; 6435 }; 6436 6437 struct mlx5_ifc_general_obj_out_cmd_hdr_bits { 6438 u8 status[0x8]; 6439 u8 reserved_at_8[0x18]; 6440 6441 u8 syndrome[0x20]; 6442 6443 u8 obj_id[0x20]; 6444 6445 u8 reserved_at_60[0x20]; 6446 }; 6447 6448 struct mlx5_ifc_allow_other_vhca_access_in_bits { 6449 u8 opcode[0x10]; 6450 u8 uid[0x10]; 6451 u8 reserved_at_20[0x10]; 6452 u8 op_mod[0x10]; 6453 u8 reserved_at_40[0x50]; 6454 u8 object_type_to_be_accessed[0x10]; 6455 u8 object_id_to_be_accessed[0x20]; 6456 u8 reserved_at_c0[0x40]; 6457 union { 6458 u8 access_key_raw[0x100]; 6459 u8 access_key[8][0x20]; 6460 }; 6461 }; 6462 6463 struct mlx5_ifc_allow_other_vhca_access_out_bits { 6464 u8 status[0x8]; 6465 u8 reserved_at_8[0x18]; 6466 u8 syndrome[0x20]; 6467 u8 reserved_at_40[0x40]; 6468 }; 6469 6470 struct mlx5_ifc_modify_header_arg_bits { 6471 u8 reserved_at_0[0x80]; 6472 6473 u8 reserved_at_80[0x8]; 6474 u8 access_pd[0x18]; 6475 }; 6476 6477 struct mlx5_ifc_create_modify_header_arg_in_bits { 6478 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 6479 struct mlx5_ifc_modify_header_arg_bits arg; 6480 }; 6481 6482 struct mlx5_ifc_create_match_definer_in_bits { 6483 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 6484 6485 struct mlx5_ifc_match_definer_bits obj_context; 6486 }; 6487 6488 struct mlx5_ifc_create_match_definer_out_bits { 6489 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 6490 }; 6491 6492 struct mlx5_ifc_alias_context_bits { 6493 u8 vhca_id_to_be_accessed[0x10]; 6494 u8 reserved_at_10[0xd]; 6495 u8 status[0x3]; 6496 u8 object_id_to_be_accessed[0x20]; 6497 u8 reserved_at_40[0x40]; 6498 union { 6499 u8 access_key_raw[0x100]; 6500 u8 access_key[8][0x20]; 6501 }; 6502 u8 metadata[0x80]; 6503 }; 6504 6505 struct mlx5_ifc_create_alias_obj_in_bits { 6506 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 6507 struct mlx5_ifc_alias_context_bits alias_ctx; 6508 }; 6509 6510 enum { 6511 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 6512 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 6513 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 6514 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3, 6515 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_3 = 0x4, 6516 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_4 = 0x5, 6517 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_5 = 0x6, 6518 }; 6519 6520 struct mlx5_ifc_query_flow_group_out_bits { 6521 u8 status[0x8]; 6522 u8 reserved_at_8[0x18]; 6523 6524 u8 syndrome[0x20]; 6525 6526 u8 reserved_at_40[0xa0]; 6527 6528 u8 start_flow_index[0x20]; 6529 6530 u8 reserved_at_100[0x20]; 6531 6532 u8 end_flow_index[0x20]; 6533 6534 u8 reserved_at_140[0xa0]; 6535 6536 u8 reserved_at_1e0[0x18]; 6537 u8 match_criteria_enable[0x8]; 6538 6539 struct mlx5_ifc_fte_match_param_bits match_criteria; 6540 6541 u8 reserved_at_1200[0xe00]; 6542 }; 6543 6544 struct mlx5_ifc_query_flow_group_in_bits { 6545 u8 opcode[0x10]; 6546 u8 reserved_at_10[0x10]; 6547 6548 u8 reserved_at_20[0x10]; 6549 u8 op_mod[0x10]; 6550 6551 u8 reserved_at_40[0x40]; 6552 6553 u8 table_type[0x8]; 6554 u8 reserved_at_88[0x18]; 6555 6556 u8 reserved_at_a0[0x8]; 6557 u8 table_id[0x18]; 6558 6559 u8 group_id[0x20]; 6560 6561 u8 reserved_at_e0[0x120]; 6562 }; 6563 6564 struct mlx5_ifc_query_flow_counter_out_bits { 6565 u8 status[0x8]; 6566 u8 reserved_at_8[0x18]; 6567 6568 u8 syndrome[0x20]; 6569 6570 u8 reserved_at_40[0x40]; 6571 6572 struct mlx5_ifc_traffic_counter_bits flow_statistics[]; 6573 }; 6574 6575 struct mlx5_ifc_query_flow_counter_in_bits { 6576 u8 opcode[0x10]; 6577 u8 reserved_at_10[0x10]; 6578 6579 u8 reserved_at_20[0x10]; 6580 u8 op_mod[0x10]; 6581 6582 u8 reserved_at_40[0x80]; 6583 6584 u8 clear[0x1]; 6585 u8 reserved_at_c1[0xf]; 6586 u8 num_of_counters[0x10]; 6587 6588 u8 flow_counter_id[0x20]; 6589 }; 6590 6591 struct mlx5_ifc_query_esw_vport_context_out_bits { 6592 u8 status[0x8]; 6593 u8 reserved_at_8[0x18]; 6594 6595 u8 syndrome[0x20]; 6596 6597 u8 reserved_at_40[0x40]; 6598 6599 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 6600 }; 6601 6602 struct mlx5_ifc_query_esw_vport_context_in_bits { 6603 u8 opcode[0x10]; 6604 u8 reserved_at_10[0x10]; 6605 6606 u8 reserved_at_20[0x10]; 6607 u8 op_mod[0x10]; 6608 6609 u8 other_vport[0x1]; 6610 u8 reserved_at_41[0xf]; 6611 u8 vport_number[0x10]; 6612 6613 u8 reserved_at_60[0x20]; 6614 }; 6615 6616 struct mlx5_ifc_modify_esw_vport_context_out_bits { 6617 u8 status[0x8]; 6618 u8 reserved_at_8[0x18]; 6619 6620 u8 syndrome[0x20]; 6621 6622 u8 reserved_at_40[0x40]; 6623 }; 6624 6625 struct mlx5_ifc_esw_vport_context_fields_select_bits { 6626 u8 reserved_at_0[0x1b]; 6627 u8 fdb_to_vport_reg_c_id[0x1]; 6628 u8 vport_cvlan_insert[0x1]; 6629 u8 vport_svlan_insert[0x1]; 6630 u8 vport_cvlan_strip[0x1]; 6631 u8 vport_svlan_strip[0x1]; 6632 }; 6633 6634 struct mlx5_ifc_modify_esw_vport_context_in_bits { 6635 u8 opcode[0x10]; 6636 u8 reserved_at_10[0x10]; 6637 6638 u8 reserved_at_20[0x10]; 6639 u8 op_mod[0x10]; 6640 6641 u8 other_vport[0x1]; 6642 u8 reserved_at_41[0xf]; 6643 u8 vport_number[0x10]; 6644 6645 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select; 6646 6647 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 6648 }; 6649 6650 struct mlx5_ifc_query_eq_out_bits { 6651 u8 status[0x8]; 6652 u8 reserved_at_8[0x18]; 6653 6654 u8 syndrome[0x20]; 6655 6656 u8 reserved_at_40[0x40]; 6657 6658 struct mlx5_ifc_eqc_bits eq_context_entry; 6659 6660 u8 reserved_at_280[0x40]; 6661 6662 u8 event_bitmask[0x40]; 6663 6664 u8 reserved_at_300[0x580]; 6665 6666 u8 pas[][0x40]; 6667 }; 6668 6669 struct mlx5_ifc_query_eq_in_bits { 6670 u8 opcode[0x10]; 6671 u8 reserved_at_10[0x10]; 6672 6673 u8 reserved_at_20[0x10]; 6674 u8 op_mod[0x10]; 6675 6676 u8 reserved_at_40[0x18]; 6677 u8 eq_number[0x8]; 6678 6679 u8 reserved_at_60[0x20]; 6680 }; 6681 6682 struct mlx5_ifc_packet_reformat_context_in_bits { 6683 u8 reformat_type[0x8]; 6684 u8 reserved_at_8[0x4]; 6685 u8 reformat_param_0[0x4]; 6686 u8 reserved_at_10[0x6]; 6687 u8 reformat_data_size[0xa]; 6688 6689 u8 reformat_param_1[0x8]; 6690 u8 reserved_at_28[0x8]; 6691 u8 reformat_data[2][0x8]; 6692 6693 u8 more_reformat_data[][0x8]; 6694 }; 6695 6696 struct mlx5_ifc_query_packet_reformat_context_out_bits { 6697 u8 status[0x8]; 6698 u8 reserved_at_8[0x18]; 6699 6700 u8 syndrome[0x20]; 6701 6702 u8 reserved_at_40[0xa0]; 6703 6704 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context[]; 6705 }; 6706 6707 struct mlx5_ifc_query_packet_reformat_context_in_bits { 6708 u8 opcode[0x10]; 6709 u8 reserved_at_10[0x10]; 6710 6711 u8 reserved_at_20[0x10]; 6712 u8 op_mod[0x10]; 6713 6714 u8 packet_reformat_id[0x20]; 6715 6716 u8 reserved_at_60[0xa0]; 6717 }; 6718 6719 struct mlx5_ifc_alloc_packet_reformat_context_out_bits { 6720 u8 status[0x8]; 6721 u8 reserved_at_8[0x18]; 6722 6723 u8 syndrome[0x20]; 6724 6725 u8 packet_reformat_id[0x20]; 6726 6727 u8 reserved_at_60[0x20]; 6728 }; 6729 6730 enum { 6731 MLX5_REFORMAT_CONTEXT_ANCHOR_MAC_START = 0x1, 6732 MLX5_REFORMAT_CONTEXT_ANCHOR_IP_START = 0x7, 6733 MLX5_REFORMAT_CONTEXT_ANCHOR_TCP_UDP_START = 0x9, 6734 }; 6735 6736 enum mlx5_reformat_ctx_type { 6737 MLX5_REFORMAT_TYPE_L2_TO_VXLAN = 0x0, 6738 MLX5_REFORMAT_TYPE_L2_TO_NVGRE = 0x1, 6739 MLX5_REFORMAT_TYPE_L2_TO_L2_TUNNEL = 0x2, 6740 MLX5_REFORMAT_TYPE_L3_TUNNEL_TO_L2 = 0x3, 6741 MLX5_REFORMAT_TYPE_L2_TO_L3_TUNNEL = 0x4, 6742 MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_IPV4 = 0x5, 6743 MLX5_REFORMAT_TYPE_L2_TO_L3_ESP_TUNNEL = 0x6, 6744 MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_UDPV4 = 0x7, 6745 MLX5_REFORMAT_TYPE_DEL_ESP_TRANSPORT = 0x8, 6746 MLX5_REFORMAT_TYPE_L3_ESP_TUNNEL_TO_L2 = 0x9, 6747 MLX5_REFORMAT_TYPE_DEL_ESP_TRANSPORT_OVER_UDP = 0xa, 6748 MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_IPV6 = 0xb, 6749 MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_UDPV6 = 0xc, 6750 MLX5_REFORMAT_TYPE_INSERT_HDR = 0xf, 6751 MLX5_REFORMAT_TYPE_REMOVE_HDR = 0x10, 6752 MLX5_REFORMAT_TYPE_ADD_MACSEC = 0x11, 6753 MLX5_REFORMAT_TYPE_DEL_MACSEC = 0x12, 6754 }; 6755 6756 struct mlx5_ifc_alloc_packet_reformat_context_in_bits { 6757 u8 opcode[0x10]; 6758 u8 reserved_at_10[0x10]; 6759 6760 u8 reserved_at_20[0x10]; 6761 u8 op_mod[0x10]; 6762 6763 u8 reserved_at_40[0xa0]; 6764 6765 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context; 6766 }; 6767 6768 struct mlx5_ifc_dealloc_packet_reformat_context_out_bits { 6769 u8 status[0x8]; 6770 u8 reserved_at_8[0x18]; 6771 6772 u8 syndrome[0x20]; 6773 6774 u8 reserved_at_40[0x40]; 6775 }; 6776 6777 struct mlx5_ifc_dealloc_packet_reformat_context_in_bits { 6778 u8 opcode[0x10]; 6779 u8 reserved_at_10[0x10]; 6780 6781 u8 reserved_20[0x10]; 6782 u8 op_mod[0x10]; 6783 6784 u8 packet_reformat_id[0x20]; 6785 6786 u8 reserved_60[0x20]; 6787 }; 6788 6789 struct mlx5_ifc_set_action_in_bits { 6790 u8 action_type[0x4]; 6791 u8 field[0xc]; 6792 u8 reserved_at_10[0x3]; 6793 u8 offset[0x5]; 6794 u8 reserved_at_18[0x3]; 6795 u8 length[0x5]; 6796 6797 u8 data[0x20]; 6798 }; 6799 6800 struct mlx5_ifc_add_action_in_bits { 6801 u8 action_type[0x4]; 6802 u8 field[0xc]; 6803 u8 reserved_at_10[0x10]; 6804 6805 u8 data[0x20]; 6806 }; 6807 6808 struct mlx5_ifc_copy_action_in_bits { 6809 u8 action_type[0x4]; 6810 u8 src_field[0xc]; 6811 u8 reserved_at_10[0x3]; 6812 u8 src_offset[0x5]; 6813 u8 reserved_at_18[0x3]; 6814 u8 length[0x5]; 6815 6816 u8 reserved_at_20[0x4]; 6817 u8 dst_field[0xc]; 6818 u8 reserved_at_30[0x3]; 6819 u8 dst_offset[0x5]; 6820 u8 reserved_at_38[0x8]; 6821 }; 6822 6823 union mlx5_ifc_set_add_copy_action_in_auto_bits { 6824 struct mlx5_ifc_set_action_in_bits set_action_in; 6825 struct mlx5_ifc_add_action_in_bits add_action_in; 6826 struct mlx5_ifc_copy_action_in_bits copy_action_in; 6827 u8 reserved_at_0[0x40]; 6828 }; 6829 6830 enum { 6831 MLX5_ACTION_TYPE_SET = 0x1, 6832 MLX5_ACTION_TYPE_ADD = 0x2, 6833 MLX5_ACTION_TYPE_COPY = 0x3, 6834 }; 6835 6836 enum { 6837 MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16 = 0x1, 6838 MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0 = 0x2, 6839 MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE = 0x3, 6840 MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16 = 0x4, 6841 MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0 = 0x5, 6842 MLX5_ACTION_IN_FIELD_OUT_IP_DSCP = 0x6, 6843 MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS = 0x7, 6844 MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT = 0x8, 6845 MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT = 0x9, 6846 MLX5_ACTION_IN_FIELD_OUT_IP_TTL = 0xa, 6847 MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT = 0xb, 6848 MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT = 0xc, 6849 MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96 = 0xd, 6850 MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64 = 0xe, 6851 MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32 = 0xf, 6852 MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0 = 0x10, 6853 MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96 = 0x11, 6854 MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64 = 0x12, 6855 MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32 = 0x13, 6856 MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0 = 0x14, 6857 MLX5_ACTION_IN_FIELD_OUT_SIPV4 = 0x15, 6858 MLX5_ACTION_IN_FIELD_OUT_DIPV4 = 0x16, 6859 MLX5_ACTION_IN_FIELD_OUT_FIRST_VID = 0x17, 6860 MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47, 6861 MLX5_ACTION_IN_FIELD_METADATA_REG_A = 0x49, 6862 MLX5_ACTION_IN_FIELD_METADATA_REG_B = 0x50, 6863 MLX5_ACTION_IN_FIELD_METADATA_REG_C_0 = 0x51, 6864 MLX5_ACTION_IN_FIELD_METADATA_REG_C_1 = 0x52, 6865 MLX5_ACTION_IN_FIELD_METADATA_REG_C_2 = 0x53, 6866 MLX5_ACTION_IN_FIELD_METADATA_REG_C_3 = 0x54, 6867 MLX5_ACTION_IN_FIELD_METADATA_REG_C_4 = 0x55, 6868 MLX5_ACTION_IN_FIELD_METADATA_REG_C_5 = 0x56, 6869 MLX5_ACTION_IN_FIELD_METADATA_REG_C_6 = 0x57, 6870 MLX5_ACTION_IN_FIELD_METADATA_REG_C_7 = 0x58, 6871 MLX5_ACTION_IN_FIELD_OUT_TCP_SEQ_NUM = 0x59, 6872 MLX5_ACTION_IN_FIELD_OUT_TCP_ACK_NUM = 0x5B, 6873 MLX5_ACTION_IN_FIELD_IPSEC_SYNDROME = 0x5D, 6874 MLX5_ACTION_IN_FIELD_OUT_EMD_47_32 = 0x6F, 6875 MLX5_ACTION_IN_FIELD_OUT_EMD_31_0 = 0x70, 6876 }; 6877 6878 struct mlx5_ifc_alloc_modify_header_context_out_bits { 6879 u8 status[0x8]; 6880 u8 reserved_at_8[0x18]; 6881 6882 u8 syndrome[0x20]; 6883 6884 u8 modify_header_id[0x20]; 6885 6886 u8 reserved_at_60[0x20]; 6887 }; 6888 6889 struct mlx5_ifc_alloc_modify_header_context_in_bits { 6890 u8 opcode[0x10]; 6891 u8 reserved_at_10[0x10]; 6892 6893 u8 reserved_at_20[0x10]; 6894 u8 op_mod[0x10]; 6895 6896 u8 reserved_at_40[0x20]; 6897 6898 u8 table_type[0x8]; 6899 u8 reserved_at_68[0x10]; 6900 u8 num_of_actions[0x8]; 6901 6902 union mlx5_ifc_set_add_copy_action_in_auto_bits actions[]; 6903 }; 6904 6905 struct mlx5_ifc_dealloc_modify_header_context_out_bits { 6906 u8 status[0x8]; 6907 u8 reserved_at_8[0x18]; 6908 6909 u8 syndrome[0x20]; 6910 6911 u8 reserved_at_40[0x40]; 6912 }; 6913 6914 struct mlx5_ifc_dealloc_modify_header_context_in_bits { 6915 u8 opcode[0x10]; 6916 u8 reserved_at_10[0x10]; 6917 6918 u8 reserved_at_20[0x10]; 6919 u8 op_mod[0x10]; 6920 6921 u8 modify_header_id[0x20]; 6922 6923 u8 reserved_at_60[0x20]; 6924 }; 6925 6926 struct mlx5_ifc_query_modify_header_context_in_bits { 6927 u8 opcode[0x10]; 6928 u8 uid[0x10]; 6929 6930 u8 reserved_at_20[0x10]; 6931 u8 op_mod[0x10]; 6932 6933 u8 modify_header_id[0x20]; 6934 6935 u8 reserved_at_60[0xa0]; 6936 }; 6937 6938 struct mlx5_ifc_query_dct_out_bits { 6939 u8 status[0x8]; 6940 u8 reserved_at_8[0x18]; 6941 6942 u8 syndrome[0x20]; 6943 6944 u8 reserved_at_40[0x40]; 6945 6946 struct mlx5_ifc_dctc_bits dct_context_entry; 6947 6948 u8 reserved_at_280[0x180]; 6949 }; 6950 6951 struct mlx5_ifc_query_dct_in_bits { 6952 u8 opcode[0x10]; 6953 u8 reserved_at_10[0x10]; 6954 6955 u8 reserved_at_20[0x10]; 6956 u8 op_mod[0x10]; 6957 6958 u8 reserved_at_40[0x8]; 6959 u8 dctn[0x18]; 6960 6961 u8 reserved_at_60[0x20]; 6962 }; 6963 6964 struct mlx5_ifc_query_cq_out_bits { 6965 u8 status[0x8]; 6966 u8 reserved_at_8[0x18]; 6967 6968 u8 syndrome[0x20]; 6969 6970 u8 reserved_at_40[0x40]; 6971 6972 struct mlx5_ifc_cqc_bits cq_context; 6973 6974 u8 reserved_at_280[0x600]; 6975 6976 u8 pas[][0x40]; 6977 }; 6978 6979 struct mlx5_ifc_query_cq_in_bits { 6980 u8 opcode[0x10]; 6981 u8 reserved_at_10[0x10]; 6982 6983 u8 reserved_at_20[0x10]; 6984 u8 op_mod[0x10]; 6985 6986 u8 reserved_at_40[0x8]; 6987 u8 cqn[0x18]; 6988 6989 u8 reserved_at_60[0x20]; 6990 }; 6991 6992 struct mlx5_ifc_query_cong_status_out_bits { 6993 u8 status[0x8]; 6994 u8 reserved_at_8[0x18]; 6995 6996 u8 syndrome[0x20]; 6997 6998 u8 reserved_at_40[0x20]; 6999 7000 u8 enable[0x1]; 7001 u8 tag_enable[0x1]; 7002 u8 reserved_at_62[0x1e]; 7003 }; 7004 7005 struct mlx5_ifc_query_cong_status_in_bits { 7006 u8 opcode[0x10]; 7007 u8 reserved_at_10[0x10]; 7008 7009 u8 reserved_at_20[0x10]; 7010 u8 op_mod[0x10]; 7011 7012 u8 reserved_at_40[0x18]; 7013 u8 priority[0x4]; 7014 u8 cong_protocol[0x4]; 7015 7016 u8 reserved_at_60[0x20]; 7017 }; 7018 7019 struct mlx5_ifc_query_cong_statistics_out_bits { 7020 u8 status[0x8]; 7021 u8 reserved_at_8[0x18]; 7022 7023 u8 syndrome[0x20]; 7024 7025 u8 reserved_at_40[0x40]; 7026 7027 u8 rp_cur_flows[0x20]; 7028 7029 u8 sum_flows[0x20]; 7030 7031 u8 rp_cnp_ignored_high[0x20]; 7032 7033 u8 rp_cnp_ignored_low[0x20]; 7034 7035 u8 rp_cnp_handled_high[0x20]; 7036 7037 u8 rp_cnp_handled_low[0x20]; 7038 7039 u8 reserved_at_140[0x100]; 7040 7041 u8 time_stamp_high[0x20]; 7042 7043 u8 time_stamp_low[0x20]; 7044 7045 u8 accumulators_period[0x20]; 7046 7047 u8 np_ecn_marked_roce_packets_high[0x20]; 7048 7049 u8 np_ecn_marked_roce_packets_low[0x20]; 7050 7051 u8 np_cnp_sent_high[0x20]; 7052 7053 u8 np_cnp_sent_low[0x20]; 7054 7055 u8 reserved_at_320[0x560]; 7056 }; 7057 7058 struct mlx5_ifc_query_cong_statistics_in_bits { 7059 u8 opcode[0x10]; 7060 u8 reserved_at_10[0x10]; 7061 7062 u8 reserved_at_20[0x10]; 7063 u8 op_mod[0x10]; 7064 7065 u8 clear[0x1]; 7066 u8 reserved_at_41[0x1f]; 7067 7068 u8 reserved_at_60[0x20]; 7069 }; 7070 7071 struct mlx5_ifc_query_cong_params_out_bits { 7072 u8 status[0x8]; 7073 u8 reserved_at_8[0x18]; 7074 7075 u8 syndrome[0x20]; 7076 7077 u8 reserved_at_40[0x40]; 7078 7079 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 7080 }; 7081 7082 struct mlx5_ifc_query_cong_params_in_bits { 7083 u8 opcode[0x10]; 7084 u8 reserved_at_10[0x10]; 7085 7086 u8 reserved_at_20[0x10]; 7087 u8 op_mod[0x10]; 7088 7089 u8 reserved_at_40[0x1c]; 7090 u8 cong_protocol[0x4]; 7091 7092 u8 reserved_at_60[0x20]; 7093 }; 7094 7095 struct mlx5_ifc_query_adapter_out_bits { 7096 u8 status[0x8]; 7097 u8 reserved_at_8[0x18]; 7098 7099 u8 syndrome[0x20]; 7100 7101 u8 reserved_at_40[0x40]; 7102 7103 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct; 7104 }; 7105 7106 struct mlx5_ifc_query_adapter_in_bits { 7107 u8 opcode[0x10]; 7108 u8 reserved_at_10[0x10]; 7109 7110 u8 reserved_at_20[0x10]; 7111 u8 op_mod[0x10]; 7112 7113 u8 reserved_at_40[0x40]; 7114 }; 7115 7116 struct mlx5_ifc_qp_2rst_out_bits { 7117 u8 status[0x8]; 7118 u8 reserved_at_8[0x18]; 7119 7120 u8 syndrome[0x20]; 7121 7122 u8 reserved_at_40[0x40]; 7123 }; 7124 7125 struct mlx5_ifc_qp_2rst_in_bits { 7126 u8 opcode[0x10]; 7127 u8 uid[0x10]; 7128 7129 u8 reserved_at_20[0x10]; 7130 u8 op_mod[0x10]; 7131 7132 u8 reserved_at_40[0x8]; 7133 u8 qpn[0x18]; 7134 7135 u8 reserved_at_60[0x20]; 7136 }; 7137 7138 struct mlx5_ifc_qp_2err_out_bits { 7139 u8 status[0x8]; 7140 u8 reserved_at_8[0x18]; 7141 7142 u8 syndrome[0x20]; 7143 7144 u8 reserved_at_40[0x40]; 7145 }; 7146 7147 struct mlx5_ifc_qp_2err_in_bits { 7148 u8 opcode[0x10]; 7149 u8 uid[0x10]; 7150 7151 u8 reserved_at_20[0x10]; 7152 u8 op_mod[0x10]; 7153 7154 u8 reserved_at_40[0x8]; 7155 u8 qpn[0x18]; 7156 7157 u8 reserved_at_60[0x20]; 7158 }; 7159 7160 struct mlx5_ifc_page_fault_resume_out_bits { 7161 u8 status[0x8]; 7162 u8 reserved_at_8[0x18]; 7163 7164 u8 syndrome[0x20]; 7165 7166 u8 reserved_at_40[0x40]; 7167 }; 7168 7169 struct mlx5_ifc_page_fault_resume_in_bits { 7170 u8 opcode[0x10]; 7171 u8 reserved_at_10[0x10]; 7172 7173 u8 reserved_at_20[0x10]; 7174 u8 op_mod[0x10]; 7175 7176 u8 error[0x1]; 7177 u8 reserved_at_41[0x4]; 7178 u8 page_fault_type[0x3]; 7179 u8 wq_number[0x18]; 7180 7181 u8 reserved_at_60[0x8]; 7182 u8 token[0x18]; 7183 }; 7184 7185 struct mlx5_ifc_nop_out_bits { 7186 u8 status[0x8]; 7187 u8 reserved_at_8[0x18]; 7188 7189 u8 syndrome[0x20]; 7190 7191 u8 reserved_at_40[0x40]; 7192 }; 7193 7194 struct mlx5_ifc_nop_in_bits { 7195 u8 opcode[0x10]; 7196 u8 reserved_at_10[0x10]; 7197 7198 u8 reserved_at_20[0x10]; 7199 u8 op_mod[0x10]; 7200 7201 u8 reserved_at_40[0x40]; 7202 }; 7203 7204 struct mlx5_ifc_modify_vport_state_out_bits { 7205 u8 status[0x8]; 7206 u8 reserved_at_8[0x18]; 7207 7208 u8 syndrome[0x20]; 7209 7210 u8 reserved_at_40[0x40]; 7211 }; 7212 7213 struct mlx5_ifc_modify_vport_state_in_bits { 7214 u8 opcode[0x10]; 7215 u8 reserved_at_10[0x10]; 7216 7217 u8 reserved_at_20[0x10]; 7218 u8 op_mod[0x10]; 7219 7220 u8 other_vport[0x1]; 7221 u8 reserved_at_41[0xf]; 7222 u8 vport_number[0x10]; 7223 7224 u8 reserved_at_60[0x18]; 7225 u8 admin_state[0x4]; 7226 u8 reserved_at_7c[0x4]; 7227 }; 7228 7229 struct mlx5_ifc_modify_tis_out_bits { 7230 u8 status[0x8]; 7231 u8 reserved_at_8[0x18]; 7232 7233 u8 syndrome[0x20]; 7234 7235 u8 reserved_at_40[0x40]; 7236 }; 7237 7238 struct mlx5_ifc_modify_tis_bitmask_bits { 7239 u8 reserved_at_0[0x20]; 7240 7241 u8 reserved_at_20[0x1d]; 7242 u8 lag_tx_port_affinity[0x1]; 7243 u8 strict_lag_tx_port_affinity[0x1]; 7244 u8 prio[0x1]; 7245 }; 7246 7247 struct mlx5_ifc_modify_tis_in_bits { 7248 u8 opcode[0x10]; 7249 u8 uid[0x10]; 7250 7251 u8 reserved_at_20[0x10]; 7252 u8 op_mod[0x10]; 7253 7254 u8 reserved_at_40[0x8]; 7255 u8 tisn[0x18]; 7256 7257 u8 reserved_at_60[0x20]; 7258 7259 struct mlx5_ifc_modify_tis_bitmask_bits bitmask; 7260 7261 u8 reserved_at_c0[0x40]; 7262 7263 struct mlx5_ifc_tisc_bits ctx; 7264 }; 7265 7266 struct mlx5_ifc_modify_tir_bitmask_bits { 7267 u8 reserved_at_0[0x20]; 7268 7269 u8 reserved_at_20[0x1b]; 7270 u8 self_lb_en[0x1]; 7271 u8 reserved_at_3c[0x1]; 7272 u8 hash[0x1]; 7273 u8 reserved_at_3e[0x1]; 7274 u8 packet_merge[0x1]; 7275 }; 7276 7277 struct mlx5_ifc_modify_tir_out_bits { 7278 u8 status[0x8]; 7279 u8 reserved_at_8[0x18]; 7280 7281 u8 syndrome[0x20]; 7282 7283 u8 reserved_at_40[0x40]; 7284 }; 7285 7286 struct mlx5_ifc_modify_tir_in_bits { 7287 u8 opcode[0x10]; 7288 u8 uid[0x10]; 7289 7290 u8 reserved_at_20[0x10]; 7291 u8 op_mod[0x10]; 7292 7293 u8 reserved_at_40[0x8]; 7294 u8 tirn[0x18]; 7295 7296 u8 reserved_at_60[0x20]; 7297 7298 struct mlx5_ifc_modify_tir_bitmask_bits bitmask; 7299 7300 u8 reserved_at_c0[0x40]; 7301 7302 struct mlx5_ifc_tirc_bits ctx; 7303 }; 7304 7305 struct mlx5_ifc_modify_sq_out_bits { 7306 u8 status[0x8]; 7307 u8 reserved_at_8[0x18]; 7308 7309 u8 syndrome[0x20]; 7310 7311 u8 reserved_at_40[0x40]; 7312 }; 7313 7314 struct mlx5_ifc_modify_sq_in_bits { 7315 u8 opcode[0x10]; 7316 u8 uid[0x10]; 7317 7318 u8 reserved_at_20[0x10]; 7319 u8 op_mod[0x10]; 7320 7321 u8 sq_state[0x4]; 7322 u8 reserved_at_44[0x4]; 7323 u8 sqn[0x18]; 7324 7325 u8 reserved_at_60[0x20]; 7326 7327 u8 modify_bitmask[0x40]; 7328 7329 u8 reserved_at_c0[0x40]; 7330 7331 struct mlx5_ifc_sqc_bits ctx; 7332 }; 7333 7334 struct mlx5_ifc_modify_scheduling_element_out_bits { 7335 u8 status[0x8]; 7336 u8 reserved_at_8[0x18]; 7337 7338 u8 syndrome[0x20]; 7339 7340 u8 reserved_at_40[0x1c0]; 7341 }; 7342 7343 enum { 7344 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1, 7345 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2, 7346 }; 7347 7348 struct mlx5_ifc_modify_scheduling_element_in_bits { 7349 u8 opcode[0x10]; 7350 u8 reserved_at_10[0x10]; 7351 7352 u8 reserved_at_20[0x10]; 7353 u8 op_mod[0x10]; 7354 7355 u8 scheduling_hierarchy[0x8]; 7356 u8 reserved_at_48[0x18]; 7357 7358 u8 scheduling_element_id[0x20]; 7359 7360 u8 reserved_at_80[0x20]; 7361 7362 u8 modify_bitmask[0x20]; 7363 7364 u8 reserved_at_c0[0x40]; 7365 7366 struct mlx5_ifc_scheduling_context_bits scheduling_context; 7367 7368 u8 reserved_at_300[0x100]; 7369 }; 7370 7371 struct mlx5_ifc_modify_rqt_out_bits { 7372 u8 status[0x8]; 7373 u8 reserved_at_8[0x18]; 7374 7375 u8 syndrome[0x20]; 7376 7377 u8 reserved_at_40[0x40]; 7378 }; 7379 7380 struct mlx5_ifc_rqt_bitmask_bits { 7381 u8 reserved_at_0[0x20]; 7382 7383 u8 reserved_at_20[0x1f]; 7384 u8 rqn_list[0x1]; 7385 }; 7386 7387 struct mlx5_ifc_modify_rqt_in_bits { 7388 u8 opcode[0x10]; 7389 u8 uid[0x10]; 7390 7391 u8 reserved_at_20[0x10]; 7392 u8 op_mod[0x10]; 7393 7394 u8 reserved_at_40[0x8]; 7395 u8 rqtn[0x18]; 7396 7397 u8 reserved_at_60[0x20]; 7398 7399 struct mlx5_ifc_rqt_bitmask_bits bitmask; 7400 7401 u8 reserved_at_c0[0x40]; 7402 7403 struct mlx5_ifc_rqtc_bits ctx; 7404 }; 7405 7406 struct mlx5_ifc_modify_rq_out_bits { 7407 u8 status[0x8]; 7408 u8 reserved_at_8[0x18]; 7409 7410 u8 syndrome[0x20]; 7411 7412 u8 reserved_at_40[0x40]; 7413 }; 7414 7415 enum { 7416 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1, 7417 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2, 7418 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3, 7419 }; 7420 7421 struct mlx5_ifc_modify_rq_in_bits { 7422 u8 opcode[0x10]; 7423 u8 uid[0x10]; 7424 7425 u8 reserved_at_20[0x10]; 7426 u8 op_mod[0x10]; 7427 7428 u8 rq_state[0x4]; 7429 u8 reserved_at_44[0x4]; 7430 u8 rqn[0x18]; 7431 7432 u8 reserved_at_60[0x20]; 7433 7434 u8 modify_bitmask[0x40]; 7435 7436 u8 reserved_at_c0[0x40]; 7437 7438 struct mlx5_ifc_rqc_bits ctx; 7439 }; 7440 7441 struct mlx5_ifc_modify_rmp_out_bits { 7442 u8 status[0x8]; 7443 u8 reserved_at_8[0x18]; 7444 7445 u8 syndrome[0x20]; 7446 7447 u8 reserved_at_40[0x40]; 7448 }; 7449 7450 struct mlx5_ifc_rmp_bitmask_bits { 7451 u8 reserved_at_0[0x20]; 7452 7453 u8 reserved_at_20[0x1f]; 7454 u8 lwm[0x1]; 7455 }; 7456 7457 struct mlx5_ifc_modify_rmp_in_bits { 7458 u8 opcode[0x10]; 7459 u8 uid[0x10]; 7460 7461 u8 reserved_at_20[0x10]; 7462 u8 op_mod[0x10]; 7463 7464 u8 rmp_state[0x4]; 7465 u8 reserved_at_44[0x4]; 7466 u8 rmpn[0x18]; 7467 7468 u8 reserved_at_60[0x20]; 7469 7470 struct mlx5_ifc_rmp_bitmask_bits bitmask; 7471 7472 u8 reserved_at_c0[0x40]; 7473 7474 struct mlx5_ifc_rmpc_bits ctx; 7475 }; 7476 7477 struct mlx5_ifc_modify_nic_vport_context_out_bits { 7478 u8 status[0x8]; 7479 u8 reserved_at_8[0x18]; 7480 7481 u8 syndrome[0x20]; 7482 7483 u8 reserved_at_40[0x40]; 7484 }; 7485 7486 struct mlx5_ifc_modify_nic_vport_field_select_bits { 7487 u8 reserved_at_0[0x12]; 7488 u8 affiliation[0x1]; 7489 u8 reserved_at_13[0x1]; 7490 u8 disable_uc_local_lb[0x1]; 7491 u8 disable_mc_local_lb[0x1]; 7492 u8 node_guid[0x1]; 7493 u8 port_guid[0x1]; 7494 u8 min_inline[0x1]; 7495 u8 mtu[0x1]; 7496 u8 change_event[0x1]; 7497 u8 promisc[0x1]; 7498 u8 permanent_address[0x1]; 7499 u8 addresses_list[0x1]; 7500 u8 roce_en[0x1]; 7501 u8 reserved_at_1f[0x1]; 7502 }; 7503 7504 struct mlx5_ifc_modify_nic_vport_context_in_bits { 7505 u8 opcode[0x10]; 7506 u8 reserved_at_10[0x10]; 7507 7508 u8 reserved_at_20[0x10]; 7509 u8 op_mod[0x10]; 7510 7511 u8 other_vport[0x1]; 7512 u8 reserved_at_41[0xf]; 7513 u8 vport_number[0x10]; 7514 7515 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select; 7516 7517 u8 reserved_at_80[0x780]; 7518 7519 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 7520 }; 7521 7522 struct mlx5_ifc_modify_hca_vport_context_out_bits { 7523 u8 status[0x8]; 7524 u8 reserved_at_8[0x18]; 7525 7526 u8 syndrome[0x20]; 7527 7528 u8 reserved_at_40[0x40]; 7529 }; 7530 7531 struct mlx5_ifc_modify_hca_vport_context_in_bits { 7532 u8 opcode[0x10]; 7533 u8 reserved_at_10[0x10]; 7534 7535 u8 reserved_at_20[0x10]; 7536 u8 op_mod[0x10]; 7537 7538 u8 other_vport[0x1]; 7539 u8 reserved_at_41[0xb]; 7540 u8 port_num[0x4]; 7541 u8 vport_number[0x10]; 7542 7543 u8 reserved_at_60[0x20]; 7544 7545 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 7546 }; 7547 7548 struct mlx5_ifc_modify_cq_out_bits { 7549 u8 status[0x8]; 7550 u8 reserved_at_8[0x18]; 7551 7552 u8 syndrome[0x20]; 7553 7554 u8 reserved_at_40[0x40]; 7555 }; 7556 7557 enum { 7558 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0, 7559 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1, 7560 }; 7561 7562 struct mlx5_ifc_modify_cq_in_bits { 7563 u8 opcode[0x10]; 7564 u8 uid[0x10]; 7565 7566 u8 reserved_at_20[0x10]; 7567 u8 op_mod[0x10]; 7568 7569 u8 reserved_at_40[0x8]; 7570 u8 cqn[0x18]; 7571 7572 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select; 7573 7574 struct mlx5_ifc_cqc_bits cq_context; 7575 7576 u8 reserved_at_280[0x60]; 7577 7578 u8 cq_umem_valid[0x1]; 7579 u8 reserved_at_2e1[0x1f]; 7580 7581 u8 reserved_at_300[0x580]; 7582 7583 u8 pas[][0x40]; 7584 }; 7585 7586 struct mlx5_ifc_modify_cong_status_out_bits { 7587 u8 status[0x8]; 7588 u8 reserved_at_8[0x18]; 7589 7590 u8 syndrome[0x20]; 7591 7592 u8 reserved_at_40[0x40]; 7593 }; 7594 7595 struct mlx5_ifc_modify_cong_status_in_bits { 7596 u8 opcode[0x10]; 7597 u8 reserved_at_10[0x10]; 7598 7599 u8 reserved_at_20[0x10]; 7600 u8 op_mod[0x10]; 7601 7602 u8 reserved_at_40[0x18]; 7603 u8 priority[0x4]; 7604 u8 cong_protocol[0x4]; 7605 7606 u8 enable[0x1]; 7607 u8 tag_enable[0x1]; 7608 u8 reserved_at_62[0x1e]; 7609 }; 7610 7611 struct mlx5_ifc_modify_cong_params_out_bits { 7612 u8 status[0x8]; 7613 u8 reserved_at_8[0x18]; 7614 7615 u8 syndrome[0x20]; 7616 7617 u8 reserved_at_40[0x40]; 7618 }; 7619 7620 struct mlx5_ifc_modify_cong_params_in_bits { 7621 u8 opcode[0x10]; 7622 u8 reserved_at_10[0x10]; 7623 7624 u8 reserved_at_20[0x10]; 7625 u8 op_mod[0x10]; 7626 7627 u8 reserved_at_40[0x1c]; 7628 u8 cong_protocol[0x4]; 7629 7630 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select; 7631 7632 u8 reserved_at_80[0x80]; 7633 7634 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 7635 }; 7636 7637 struct mlx5_ifc_manage_pages_out_bits { 7638 u8 status[0x8]; 7639 u8 reserved_at_8[0x18]; 7640 7641 u8 syndrome[0x20]; 7642 7643 u8 output_num_entries[0x20]; 7644 7645 u8 reserved_at_60[0x20]; 7646 7647 u8 pas[][0x40]; 7648 }; 7649 7650 enum { 7651 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL = 0x0, 7652 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS = 0x1, 7653 MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES = 0x2, 7654 }; 7655 7656 struct mlx5_ifc_manage_pages_in_bits { 7657 u8 opcode[0x10]; 7658 u8 reserved_at_10[0x10]; 7659 7660 u8 reserved_at_20[0x10]; 7661 u8 op_mod[0x10]; 7662 7663 u8 embedded_cpu_function[0x1]; 7664 u8 reserved_at_41[0xf]; 7665 u8 function_id[0x10]; 7666 7667 u8 input_num_entries[0x20]; 7668 7669 u8 pas[][0x40]; 7670 }; 7671 7672 struct mlx5_ifc_mad_ifc_out_bits { 7673 u8 status[0x8]; 7674 u8 reserved_at_8[0x18]; 7675 7676 u8 syndrome[0x20]; 7677 7678 u8 reserved_at_40[0x40]; 7679 7680 u8 response_mad_packet[256][0x8]; 7681 }; 7682 7683 struct mlx5_ifc_mad_ifc_in_bits { 7684 u8 opcode[0x10]; 7685 u8 reserved_at_10[0x10]; 7686 7687 u8 reserved_at_20[0x10]; 7688 u8 op_mod[0x10]; 7689 7690 u8 remote_lid[0x10]; 7691 u8 reserved_at_50[0x8]; 7692 u8 port[0x8]; 7693 7694 u8 reserved_at_60[0x20]; 7695 7696 u8 mad[256][0x8]; 7697 }; 7698 7699 struct mlx5_ifc_init_hca_out_bits { 7700 u8 status[0x8]; 7701 u8 reserved_at_8[0x18]; 7702 7703 u8 syndrome[0x20]; 7704 7705 u8 reserved_at_40[0x40]; 7706 }; 7707 7708 struct mlx5_ifc_init_hca_in_bits { 7709 u8 opcode[0x10]; 7710 u8 reserved_at_10[0x10]; 7711 7712 u8 reserved_at_20[0x10]; 7713 u8 op_mod[0x10]; 7714 7715 u8 reserved_at_40[0x20]; 7716 7717 u8 reserved_at_60[0x2]; 7718 u8 sw_vhca_id[0xe]; 7719 u8 reserved_at_70[0x10]; 7720 7721 u8 sw_owner_id[4][0x20]; 7722 }; 7723 7724 struct mlx5_ifc_init2rtr_qp_out_bits { 7725 u8 status[0x8]; 7726 u8 reserved_at_8[0x18]; 7727 7728 u8 syndrome[0x20]; 7729 7730 u8 reserved_at_40[0x20]; 7731 u8 ece[0x20]; 7732 }; 7733 7734 struct mlx5_ifc_init2rtr_qp_in_bits { 7735 u8 opcode[0x10]; 7736 u8 uid[0x10]; 7737 7738 u8 reserved_at_20[0x10]; 7739 u8 op_mod[0x10]; 7740 7741 u8 reserved_at_40[0x8]; 7742 u8 qpn[0x18]; 7743 7744 u8 reserved_at_60[0x20]; 7745 7746 u8 opt_param_mask[0x20]; 7747 7748 u8 ece[0x20]; 7749 7750 struct mlx5_ifc_qpc_bits qpc; 7751 7752 u8 reserved_at_800[0x80]; 7753 }; 7754 7755 struct mlx5_ifc_init2init_qp_out_bits { 7756 u8 status[0x8]; 7757 u8 reserved_at_8[0x18]; 7758 7759 u8 syndrome[0x20]; 7760 7761 u8 reserved_at_40[0x20]; 7762 u8 ece[0x20]; 7763 }; 7764 7765 struct mlx5_ifc_init2init_qp_in_bits { 7766 u8 opcode[0x10]; 7767 u8 uid[0x10]; 7768 7769 u8 reserved_at_20[0x10]; 7770 u8 op_mod[0x10]; 7771 7772 u8 reserved_at_40[0x8]; 7773 u8 qpn[0x18]; 7774 7775 u8 reserved_at_60[0x20]; 7776 7777 u8 opt_param_mask[0x20]; 7778 7779 u8 ece[0x20]; 7780 7781 struct mlx5_ifc_qpc_bits qpc; 7782 7783 u8 reserved_at_800[0x80]; 7784 }; 7785 7786 struct mlx5_ifc_get_dropped_packet_log_out_bits { 7787 u8 status[0x8]; 7788 u8 reserved_at_8[0x18]; 7789 7790 u8 syndrome[0x20]; 7791 7792 u8 reserved_at_40[0x40]; 7793 7794 u8 packet_headers_log[128][0x8]; 7795 7796 u8 packet_syndrome[64][0x8]; 7797 }; 7798 7799 struct mlx5_ifc_get_dropped_packet_log_in_bits { 7800 u8 opcode[0x10]; 7801 u8 reserved_at_10[0x10]; 7802 7803 u8 reserved_at_20[0x10]; 7804 u8 op_mod[0x10]; 7805 7806 u8 reserved_at_40[0x40]; 7807 }; 7808 7809 struct mlx5_ifc_gen_eqe_in_bits { 7810 u8 opcode[0x10]; 7811 u8 reserved_at_10[0x10]; 7812 7813 u8 reserved_at_20[0x10]; 7814 u8 op_mod[0x10]; 7815 7816 u8 reserved_at_40[0x18]; 7817 u8 eq_number[0x8]; 7818 7819 u8 reserved_at_60[0x20]; 7820 7821 u8 eqe[64][0x8]; 7822 }; 7823 7824 struct mlx5_ifc_gen_eq_out_bits { 7825 u8 status[0x8]; 7826 u8 reserved_at_8[0x18]; 7827 7828 u8 syndrome[0x20]; 7829 7830 u8 reserved_at_40[0x40]; 7831 }; 7832 7833 struct mlx5_ifc_enable_hca_out_bits { 7834 u8 status[0x8]; 7835 u8 reserved_at_8[0x18]; 7836 7837 u8 syndrome[0x20]; 7838 7839 u8 reserved_at_40[0x20]; 7840 }; 7841 7842 struct mlx5_ifc_enable_hca_in_bits { 7843 u8 opcode[0x10]; 7844 u8 reserved_at_10[0x10]; 7845 7846 u8 reserved_at_20[0x10]; 7847 u8 op_mod[0x10]; 7848 7849 u8 embedded_cpu_function[0x1]; 7850 u8 reserved_at_41[0xf]; 7851 u8 function_id[0x10]; 7852 7853 u8 reserved_at_60[0x20]; 7854 }; 7855 7856 struct mlx5_ifc_drain_dct_out_bits { 7857 u8 status[0x8]; 7858 u8 reserved_at_8[0x18]; 7859 7860 u8 syndrome[0x20]; 7861 7862 u8 reserved_at_40[0x40]; 7863 }; 7864 7865 struct mlx5_ifc_drain_dct_in_bits { 7866 u8 opcode[0x10]; 7867 u8 uid[0x10]; 7868 7869 u8 reserved_at_20[0x10]; 7870 u8 op_mod[0x10]; 7871 7872 u8 reserved_at_40[0x8]; 7873 u8 dctn[0x18]; 7874 7875 u8 reserved_at_60[0x20]; 7876 }; 7877 7878 struct mlx5_ifc_disable_hca_out_bits { 7879 u8 status[0x8]; 7880 u8 reserved_at_8[0x18]; 7881 7882 u8 syndrome[0x20]; 7883 7884 u8 reserved_at_40[0x20]; 7885 }; 7886 7887 struct mlx5_ifc_disable_hca_in_bits { 7888 u8 opcode[0x10]; 7889 u8 reserved_at_10[0x10]; 7890 7891 u8 reserved_at_20[0x10]; 7892 u8 op_mod[0x10]; 7893 7894 u8 embedded_cpu_function[0x1]; 7895 u8 reserved_at_41[0xf]; 7896 u8 function_id[0x10]; 7897 7898 u8 reserved_at_60[0x20]; 7899 }; 7900 7901 struct mlx5_ifc_detach_from_mcg_out_bits { 7902 u8 status[0x8]; 7903 u8 reserved_at_8[0x18]; 7904 7905 u8 syndrome[0x20]; 7906 7907 u8 reserved_at_40[0x40]; 7908 }; 7909 7910 struct mlx5_ifc_detach_from_mcg_in_bits { 7911 u8 opcode[0x10]; 7912 u8 uid[0x10]; 7913 7914 u8 reserved_at_20[0x10]; 7915 u8 op_mod[0x10]; 7916 7917 u8 reserved_at_40[0x8]; 7918 u8 qpn[0x18]; 7919 7920 u8 reserved_at_60[0x20]; 7921 7922 u8 multicast_gid[16][0x8]; 7923 }; 7924 7925 struct mlx5_ifc_destroy_xrq_out_bits { 7926 u8 status[0x8]; 7927 u8 reserved_at_8[0x18]; 7928 7929 u8 syndrome[0x20]; 7930 7931 u8 reserved_at_40[0x40]; 7932 }; 7933 7934 struct mlx5_ifc_destroy_xrq_in_bits { 7935 u8 opcode[0x10]; 7936 u8 uid[0x10]; 7937 7938 u8 reserved_at_20[0x10]; 7939 u8 op_mod[0x10]; 7940 7941 u8 reserved_at_40[0x8]; 7942 u8 xrqn[0x18]; 7943 7944 u8 reserved_at_60[0x20]; 7945 }; 7946 7947 struct mlx5_ifc_destroy_xrc_srq_out_bits { 7948 u8 status[0x8]; 7949 u8 reserved_at_8[0x18]; 7950 7951 u8 syndrome[0x20]; 7952 7953 u8 reserved_at_40[0x40]; 7954 }; 7955 7956 struct mlx5_ifc_destroy_xrc_srq_in_bits { 7957 u8 opcode[0x10]; 7958 u8 uid[0x10]; 7959 7960 u8 reserved_at_20[0x10]; 7961 u8 op_mod[0x10]; 7962 7963 u8 reserved_at_40[0x8]; 7964 u8 xrc_srqn[0x18]; 7965 7966 u8 reserved_at_60[0x20]; 7967 }; 7968 7969 struct mlx5_ifc_destroy_tis_out_bits { 7970 u8 status[0x8]; 7971 u8 reserved_at_8[0x18]; 7972 7973 u8 syndrome[0x20]; 7974 7975 u8 reserved_at_40[0x40]; 7976 }; 7977 7978 struct mlx5_ifc_destroy_tis_in_bits { 7979 u8 opcode[0x10]; 7980 u8 uid[0x10]; 7981 7982 u8 reserved_at_20[0x10]; 7983 u8 op_mod[0x10]; 7984 7985 u8 reserved_at_40[0x8]; 7986 u8 tisn[0x18]; 7987 7988 u8 reserved_at_60[0x20]; 7989 }; 7990 7991 struct mlx5_ifc_destroy_tir_out_bits { 7992 u8 status[0x8]; 7993 u8 reserved_at_8[0x18]; 7994 7995 u8 syndrome[0x20]; 7996 7997 u8 reserved_at_40[0x40]; 7998 }; 7999 8000 struct mlx5_ifc_destroy_tir_in_bits { 8001 u8 opcode[0x10]; 8002 u8 uid[0x10]; 8003 8004 u8 reserved_at_20[0x10]; 8005 u8 op_mod[0x10]; 8006 8007 u8 reserved_at_40[0x8]; 8008 u8 tirn[0x18]; 8009 8010 u8 reserved_at_60[0x20]; 8011 }; 8012 8013 struct mlx5_ifc_destroy_srq_out_bits { 8014 u8 status[0x8]; 8015 u8 reserved_at_8[0x18]; 8016 8017 u8 syndrome[0x20]; 8018 8019 u8 reserved_at_40[0x40]; 8020 }; 8021 8022 struct mlx5_ifc_destroy_srq_in_bits { 8023 u8 opcode[0x10]; 8024 u8 uid[0x10]; 8025 8026 u8 reserved_at_20[0x10]; 8027 u8 op_mod[0x10]; 8028 8029 u8 reserved_at_40[0x8]; 8030 u8 srqn[0x18]; 8031 8032 u8 reserved_at_60[0x20]; 8033 }; 8034 8035 struct mlx5_ifc_destroy_sq_out_bits { 8036 u8 status[0x8]; 8037 u8 reserved_at_8[0x18]; 8038 8039 u8 syndrome[0x20]; 8040 8041 u8 reserved_at_40[0x40]; 8042 }; 8043 8044 struct mlx5_ifc_destroy_sq_in_bits { 8045 u8 opcode[0x10]; 8046 u8 uid[0x10]; 8047 8048 u8 reserved_at_20[0x10]; 8049 u8 op_mod[0x10]; 8050 8051 u8 reserved_at_40[0x8]; 8052 u8 sqn[0x18]; 8053 8054 u8 reserved_at_60[0x20]; 8055 }; 8056 8057 struct mlx5_ifc_destroy_scheduling_element_out_bits { 8058 u8 status[0x8]; 8059 u8 reserved_at_8[0x18]; 8060 8061 u8 syndrome[0x20]; 8062 8063 u8 reserved_at_40[0x1c0]; 8064 }; 8065 8066 struct mlx5_ifc_destroy_scheduling_element_in_bits { 8067 u8 opcode[0x10]; 8068 u8 reserved_at_10[0x10]; 8069 8070 u8 reserved_at_20[0x10]; 8071 u8 op_mod[0x10]; 8072 8073 u8 scheduling_hierarchy[0x8]; 8074 u8 reserved_at_48[0x18]; 8075 8076 u8 scheduling_element_id[0x20]; 8077 8078 u8 reserved_at_80[0x180]; 8079 }; 8080 8081 struct mlx5_ifc_destroy_rqt_out_bits { 8082 u8 status[0x8]; 8083 u8 reserved_at_8[0x18]; 8084 8085 u8 syndrome[0x20]; 8086 8087 u8 reserved_at_40[0x40]; 8088 }; 8089 8090 struct mlx5_ifc_destroy_rqt_in_bits { 8091 u8 opcode[0x10]; 8092 u8 uid[0x10]; 8093 8094 u8 reserved_at_20[0x10]; 8095 u8 op_mod[0x10]; 8096 8097 u8 reserved_at_40[0x8]; 8098 u8 rqtn[0x18]; 8099 8100 u8 reserved_at_60[0x20]; 8101 }; 8102 8103 struct mlx5_ifc_destroy_rq_out_bits { 8104 u8 status[0x8]; 8105 u8 reserved_at_8[0x18]; 8106 8107 u8 syndrome[0x20]; 8108 8109 u8 reserved_at_40[0x40]; 8110 }; 8111 8112 struct mlx5_ifc_destroy_rq_in_bits { 8113 u8 opcode[0x10]; 8114 u8 uid[0x10]; 8115 8116 u8 reserved_at_20[0x10]; 8117 u8 op_mod[0x10]; 8118 8119 u8 reserved_at_40[0x8]; 8120 u8 rqn[0x18]; 8121 8122 u8 reserved_at_60[0x20]; 8123 }; 8124 8125 struct mlx5_ifc_set_delay_drop_params_in_bits { 8126 u8 opcode[0x10]; 8127 u8 reserved_at_10[0x10]; 8128 8129 u8 reserved_at_20[0x10]; 8130 u8 op_mod[0x10]; 8131 8132 u8 reserved_at_40[0x20]; 8133 8134 u8 reserved_at_60[0x10]; 8135 u8 delay_drop_timeout[0x10]; 8136 }; 8137 8138 struct mlx5_ifc_set_delay_drop_params_out_bits { 8139 u8 status[0x8]; 8140 u8 reserved_at_8[0x18]; 8141 8142 u8 syndrome[0x20]; 8143 8144 u8 reserved_at_40[0x40]; 8145 }; 8146 8147 struct mlx5_ifc_destroy_rmp_out_bits { 8148 u8 status[0x8]; 8149 u8 reserved_at_8[0x18]; 8150 8151 u8 syndrome[0x20]; 8152 8153 u8 reserved_at_40[0x40]; 8154 }; 8155 8156 struct mlx5_ifc_destroy_rmp_in_bits { 8157 u8 opcode[0x10]; 8158 u8 uid[0x10]; 8159 8160 u8 reserved_at_20[0x10]; 8161 u8 op_mod[0x10]; 8162 8163 u8 reserved_at_40[0x8]; 8164 u8 rmpn[0x18]; 8165 8166 u8 reserved_at_60[0x20]; 8167 }; 8168 8169 struct mlx5_ifc_destroy_qp_out_bits { 8170 u8 status[0x8]; 8171 u8 reserved_at_8[0x18]; 8172 8173 u8 syndrome[0x20]; 8174 8175 u8 reserved_at_40[0x40]; 8176 }; 8177 8178 struct mlx5_ifc_destroy_qp_in_bits { 8179 u8 opcode[0x10]; 8180 u8 uid[0x10]; 8181 8182 u8 reserved_at_20[0x10]; 8183 u8 op_mod[0x10]; 8184 8185 u8 reserved_at_40[0x8]; 8186 u8 qpn[0x18]; 8187 8188 u8 reserved_at_60[0x20]; 8189 }; 8190 8191 struct mlx5_ifc_destroy_psv_out_bits { 8192 u8 status[0x8]; 8193 u8 reserved_at_8[0x18]; 8194 8195 u8 syndrome[0x20]; 8196 8197 u8 reserved_at_40[0x40]; 8198 }; 8199 8200 struct mlx5_ifc_destroy_psv_in_bits { 8201 u8 opcode[0x10]; 8202 u8 reserved_at_10[0x10]; 8203 8204 u8 reserved_at_20[0x10]; 8205 u8 op_mod[0x10]; 8206 8207 u8 reserved_at_40[0x8]; 8208 u8 psvn[0x18]; 8209 8210 u8 reserved_at_60[0x20]; 8211 }; 8212 8213 struct mlx5_ifc_destroy_mkey_out_bits { 8214 u8 status[0x8]; 8215 u8 reserved_at_8[0x18]; 8216 8217 u8 syndrome[0x20]; 8218 8219 u8 reserved_at_40[0x40]; 8220 }; 8221 8222 struct mlx5_ifc_destroy_mkey_in_bits { 8223 u8 opcode[0x10]; 8224 u8 uid[0x10]; 8225 8226 u8 reserved_at_20[0x10]; 8227 u8 op_mod[0x10]; 8228 8229 u8 reserved_at_40[0x8]; 8230 u8 mkey_index[0x18]; 8231 8232 u8 reserved_at_60[0x20]; 8233 }; 8234 8235 struct mlx5_ifc_destroy_flow_table_out_bits { 8236 u8 status[0x8]; 8237 u8 reserved_at_8[0x18]; 8238 8239 u8 syndrome[0x20]; 8240 8241 u8 reserved_at_40[0x40]; 8242 }; 8243 8244 struct mlx5_ifc_destroy_flow_table_in_bits { 8245 u8 opcode[0x10]; 8246 u8 reserved_at_10[0x10]; 8247 8248 u8 reserved_at_20[0x10]; 8249 u8 op_mod[0x10]; 8250 8251 u8 other_vport[0x1]; 8252 u8 reserved_at_41[0xf]; 8253 u8 vport_number[0x10]; 8254 8255 u8 reserved_at_60[0x20]; 8256 8257 u8 table_type[0x8]; 8258 u8 reserved_at_88[0x18]; 8259 8260 u8 reserved_at_a0[0x8]; 8261 u8 table_id[0x18]; 8262 8263 u8 reserved_at_c0[0x140]; 8264 }; 8265 8266 struct mlx5_ifc_destroy_flow_group_out_bits { 8267 u8 status[0x8]; 8268 u8 reserved_at_8[0x18]; 8269 8270 u8 syndrome[0x20]; 8271 8272 u8 reserved_at_40[0x40]; 8273 }; 8274 8275 struct mlx5_ifc_destroy_flow_group_in_bits { 8276 u8 opcode[0x10]; 8277 u8 reserved_at_10[0x10]; 8278 8279 u8 reserved_at_20[0x10]; 8280 u8 op_mod[0x10]; 8281 8282 u8 other_vport[0x1]; 8283 u8 reserved_at_41[0xf]; 8284 u8 vport_number[0x10]; 8285 8286 u8 reserved_at_60[0x20]; 8287 8288 u8 table_type[0x8]; 8289 u8 reserved_at_88[0x18]; 8290 8291 u8 reserved_at_a0[0x8]; 8292 u8 table_id[0x18]; 8293 8294 u8 group_id[0x20]; 8295 8296 u8 reserved_at_e0[0x120]; 8297 }; 8298 8299 struct mlx5_ifc_destroy_eq_out_bits { 8300 u8 status[0x8]; 8301 u8 reserved_at_8[0x18]; 8302 8303 u8 syndrome[0x20]; 8304 8305 u8 reserved_at_40[0x40]; 8306 }; 8307 8308 struct mlx5_ifc_destroy_eq_in_bits { 8309 u8 opcode[0x10]; 8310 u8 reserved_at_10[0x10]; 8311 8312 u8 reserved_at_20[0x10]; 8313 u8 op_mod[0x10]; 8314 8315 u8 reserved_at_40[0x18]; 8316 u8 eq_number[0x8]; 8317 8318 u8 reserved_at_60[0x20]; 8319 }; 8320 8321 struct mlx5_ifc_destroy_dct_out_bits { 8322 u8 status[0x8]; 8323 u8 reserved_at_8[0x18]; 8324 8325 u8 syndrome[0x20]; 8326 8327 u8 reserved_at_40[0x40]; 8328 }; 8329 8330 struct mlx5_ifc_destroy_dct_in_bits { 8331 u8 opcode[0x10]; 8332 u8 uid[0x10]; 8333 8334 u8 reserved_at_20[0x10]; 8335 u8 op_mod[0x10]; 8336 8337 u8 reserved_at_40[0x8]; 8338 u8 dctn[0x18]; 8339 8340 u8 reserved_at_60[0x20]; 8341 }; 8342 8343 struct mlx5_ifc_destroy_cq_out_bits { 8344 u8 status[0x8]; 8345 u8 reserved_at_8[0x18]; 8346 8347 u8 syndrome[0x20]; 8348 8349 u8 reserved_at_40[0x40]; 8350 }; 8351 8352 struct mlx5_ifc_destroy_cq_in_bits { 8353 u8 opcode[0x10]; 8354 u8 uid[0x10]; 8355 8356 u8 reserved_at_20[0x10]; 8357 u8 op_mod[0x10]; 8358 8359 u8 reserved_at_40[0x8]; 8360 u8 cqn[0x18]; 8361 8362 u8 reserved_at_60[0x20]; 8363 }; 8364 8365 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits { 8366 u8 status[0x8]; 8367 u8 reserved_at_8[0x18]; 8368 8369 u8 syndrome[0x20]; 8370 8371 u8 reserved_at_40[0x40]; 8372 }; 8373 8374 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits { 8375 u8 opcode[0x10]; 8376 u8 reserved_at_10[0x10]; 8377 8378 u8 reserved_at_20[0x10]; 8379 u8 op_mod[0x10]; 8380 8381 u8 reserved_at_40[0x20]; 8382 8383 u8 reserved_at_60[0x10]; 8384 u8 vxlan_udp_port[0x10]; 8385 }; 8386 8387 struct mlx5_ifc_delete_l2_table_entry_out_bits { 8388 u8 status[0x8]; 8389 u8 reserved_at_8[0x18]; 8390 8391 u8 syndrome[0x20]; 8392 8393 u8 reserved_at_40[0x40]; 8394 }; 8395 8396 struct mlx5_ifc_delete_l2_table_entry_in_bits { 8397 u8 opcode[0x10]; 8398 u8 reserved_at_10[0x10]; 8399 8400 u8 reserved_at_20[0x10]; 8401 u8 op_mod[0x10]; 8402 8403 u8 reserved_at_40[0x60]; 8404 8405 u8 reserved_at_a0[0x8]; 8406 u8 table_index[0x18]; 8407 8408 u8 reserved_at_c0[0x140]; 8409 }; 8410 8411 struct mlx5_ifc_delete_fte_out_bits { 8412 u8 status[0x8]; 8413 u8 reserved_at_8[0x18]; 8414 8415 u8 syndrome[0x20]; 8416 8417 u8 reserved_at_40[0x40]; 8418 }; 8419 8420 struct mlx5_ifc_delete_fte_in_bits { 8421 u8 opcode[0x10]; 8422 u8 reserved_at_10[0x10]; 8423 8424 u8 reserved_at_20[0x10]; 8425 u8 op_mod[0x10]; 8426 8427 u8 other_vport[0x1]; 8428 u8 reserved_at_41[0xf]; 8429 u8 vport_number[0x10]; 8430 8431 u8 reserved_at_60[0x20]; 8432 8433 u8 table_type[0x8]; 8434 u8 reserved_at_88[0x18]; 8435 8436 u8 reserved_at_a0[0x8]; 8437 u8 table_id[0x18]; 8438 8439 u8 reserved_at_c0[0x40]; 8440 8441 u8 flow_index[0x20]; 8442 8443 u8 reserved_at_120[0xe0]; 8444 }; 8445 8446 struct mlx5_ifc_dealloc_xrcd_out_bits { 8447 u8 status[0x8]; 8448 u8 reserved_at_8[0x18]; 8449 8450 u8 syndrome[0x20]; 8451 8452 u8 reserved_at_40[0x40]; 8453 }; 8454 8455 struct mlx5_ifc_dealloc_xrcd_in_bits { 8456 u8 opcode[0x10]; 8457 u8 uid[0x10]; 8458 8459 u8 reserved_at_20[0x10]; 8460 u8 op_mod[0x10]; 8461 8462 u8 reserved_at_40[0x8]; 8463 u8 xrcd[0x18]; 8464 8465 u8 reserved_at_60[0x20]; 8466 }; 8467 8468 struct mlx5_ifc_dealloc_uar_out_bits { 8469 u8 status[0x8]; 8470 u8 reserved_at_8[0x18]; 8471 8472 u8 syndrome[0x20]; 8473 8474 u8 reserved_at_40[0x40]; 8475 }; 8476 8477 struct mlx5_ifc_dealloc_uar_in_bits { 8478 u8 opcode[0x10]; 8479 u8 uid[0x10]; 8480 8481 u8 reserved_at_20[0x10]; 8482 u8 op_mod[0x10]; 8483 8484 u8 reserved_at_40[0x8]; 8485 u8 uar[0x18]; 8486 8487 u8 reserved_at_60[0x20]; 8488 }; 8489 8490 struct mlx5_ifc_dealloc_transport_domain_out_bits { 8491 u8 status[0x8]; 8492 u8 reserved_at_8[0x18]; 8493 8494 u8 syndrome[0x20]; 8495 8496 u8 reserved_at_40[0x40]; 8497 }; 8498 8499 struct mlx5_ifc_dealloc_transport_domain_in_bits { 8500 u8 opcode[0x10]; 8501 u8 uid[0x10]; 8502 8503 u8 reserved_at_20[0x10]; 8504 u8 op_mod[0x10]; 8505 8506 u8 reserved_at_40[0x8]; 8507 u8 transport_domain[0x18]; 8508 8509 u8 reserved_at_60[0x20]; 8510 }; 8511 8512 struct mlx5_ifc_dealloc_q_counter_out_bits { 8513 u8 status[0x8]; 8514 u8 reserved_at_8[0x18]; 8515 8516 u8 syndrome[0x20]; 8517 8518 u8 reserved_at_40[0x40]; 8519 }; 8520 8521 struct mlx5_ifc_dealloc_q_counter_in_bits { 8522 u8 opcode[0x10]; 8523 u8 reserved_at_10[0x10]; 8524 8525 u8 reserved_at_20[0x10]; 8526 u8 op_mod[0x10]; 8527 8528 u8 reserved_at_40[0x18]; 8529 u8 counter_set_id[0x8]; 8530 8531 u8 reserved_at_60[0x20]; 8532 }; 8533 8534 struct mlx5_ifc_dealloc_pd_out_bits { 8535 u8 status[0x8]; 8536 u8 reserved_at_8[0x18]; 8537 8538 u8 syndrome[0x20]; 8539 8540 u8 reserved_at_40[0x40]; 8541 }; 8542 8543 struct mlx5_ifc_dealloc_pd_in_bits { 8544 u8 opcode[0x10]; 8545 u8 uid[0x10]; 8546 8547 u8 reserved_at_20[0x10]; 8548 u8 op_mod[0x10]; 8549 8550 u8 reserved_at_40[0x8]; 8551 u8 pd[0x18]; 8552 8553 u8 reserved_at_60[0x20]; 8554 }; 8555 8556 struct mlx5_ifc_dealloc_flow_counter_out_bits { 8557 u8 status[0x8]; 8558 u8 reserved_at_8[0x18]; 8559 8560 u8 syndrome[0x20]; 8561 8562 u8 reserved_at_40[0x40]; 8563 }; 8564 8565 struct mlx5_ifc_dealloc_flow_counter_in_bits { 8566 u8 opcode[0x10]; 8567 u8 reserved_at_10[0x10]; 8568 8569 u8 reserved_at_20[0x10]; 8570 u8 op_mod[0x10]; 8571 8572 u8 flow_counter_id[0x20]; 8573 8574 u8 reserved_at_60[0x20]; 8575 }; 8576 8577 struct mlx5_ifc_create_xrq_out_bits { 8578 u8 status[0x8]; 8579 u8 reserved_at_8[0x18]; 8580 8581 u8 syndrome[0x20]; 8582 8583 u8 reserved_at_40[0x8]; 8584 u8 xrqn[0x18]; 8585 8586 u8 reserved_at_60[0x20]; 8587 }; 8588 8589 struct mlx5_ifc_create_xrq_in_bits { 8590 u8 opcode[0x10]; 8591 u8 uid[0x10]; 8592 8593 u8 reserved_at_20[0x10]; 8594 u8 op_mod[0x10]; 8595 8596 u8 reserved_at_40[0x40]; 8597 8598 struct mlx5_ifc_xrqc_bits xrq_context; 8599 }; 8600 8601 struct mlx5_ifc_create_xrc_srq_out_bits { 8602 u8 status[0x8]; 8603 u8 reserved_at_8[0x18]; 8604 8605 u8 syndrome[0x20]; 8606 8607 u8 reserved_at_40[0x8]; 8608 u8 xrc_srqn[0x18]; 8609 8610 u8 reserved_at_60[0x20]; 8611 }; 8612 8613 struct mlx5_ifc_create_xrc_srq_in_bits { 8614 u8 opcode[0x10]; 8615 u8 uid[0x10]; 8616 8617 u8 reserved_at_20[0x10]; 8618 u8 op_mod[0x10]; 8619 8620 u8 reserved_at_40[0x40]; 8621 8622 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 8623 8624 u8 reserved_at_280[0x60]; 8625 8626 u8 xrc_srq_umem_valid[0x1]; 8627 u8 reserved_at_2e1[0x1f]; 8628 8629 u8 reserved_at_300[0x580]; 8630 8631 u8 pas[][0x40]; 8632 }; 8633 8634 struct mlx5_ifc_create_tis_out_bits { 8635 u8 status[0x8]; 8636 u8 reserved_at_8[0x18]; 8637 8638 u8 syndrome[0x20]; 8639 8640 u8 reserved_at_40[0x8]; 8641 u8 tisn[0x18]; 8642 8643 u8 reserved_at_60[0x20]; 8644 }; 8645 8646 struct mlx5_ifc_create_tis_in_bits { 8647 u8 opcode[0x10]; 8648 u8 uid[0x10]; 8649 8650 u8 reserved_at_20[0x10]; 8651 u8 op_mod[0x10]; 8652 8653 u8 reserved_at_40[0xc0]; 8654 8655 struct mlx5_ifc_tisc_bits ctx; 8656 }; 8657 8658 struct mlx5_ifc_create_tir_out_bits { 8659 u8 status[0x8]; 8660 u8 icm_address_63_40[0x18]; 8661 8662 u8 syndrome[0x20]; 8663 8664 u8 icm_address_39_32[0x8]; 8665 u8 tirn[0x18]; 8666 8667 u8 icm_address_31_0[0x20]; 8668 }; 8669 8670 struct mlx5_ifc_create_tir_in_bits { 8671 u8 opcode[0x10]; 8672 u8 uid[0x10]; 8673 8674 u8 reserved_at_20[0x10]; 8675 u8 op_mod[0x10]; 8676 8677 u8 reserved_at_40[0xc0]; 8678 8679 struct mlx5_ifc_tirc_bits ctx; 8680 }; 8681 8682 struct mlx5_ifc_create_srq_out_bits { 8683 u8 status[0x8]; 8684 u8 reserved_at_8[0x18]; 8685 8686 u8 syndrome[0x20]; 8687 8688 u8 reserved_at_40[0x8]; 8689 u8 srqn[0x18]; 8690 8691 u8 reserved_at_60[0x20]; 8692 }; 8693 8694 struct mlx5_ifc_create_srq_in_bits { 8695 u8 opcode[0x10]; 8696 u8 uid[0x10]; 8697 8698 u8 reserved_at_20[0x10]; 8699 u8 op_mod[0x10]; 8700 8701 u8 reserved_at_40[0x40]; 8702 8703 struct mlx5_ifc_srqc_bits srq_context_entry; 8704 8705 u8 reserved_at_280[0x600]; 8706 8707 u8 pas[][0x40]; 8708 }; 8709 8710 struct mlx5_ifc_create_sq_out_bits { 8711 u8 status[0x8]; 8712 u8 reserved_at_8[0x18]; 8713 8714 u8 syndrome[0x20]; 8715 8716 u8 reserved_at_40[0x8]; 8717 u8 sqn[0x18]; 8718 8719 u8 reserved_at_60[0x20]; 8720 }; 8721 8722 struct mlx5_ifc_create_sq_in_bits { 8723 u8 opcode[0x10]; 8724 u8 uid[0x10]; 8725 8726 u8 reserved_at_20[0x10]; 8727 u8 op_mod[0x10]; 8728 8729 u8 reserved_at_40[0xc0]; 8730 8731 struct mlx5_ifc_sqc_bits ctx; 8732 }; 8733 8734 struct mlx5_ifc_create_scheduling_element_out_bits { 8735 u8 status[0x8]; 8736 u8 reserved_at_8[0x18]; 8737 8738 u8 syndrome[0x20]; 8739 8740 u8 reserved_at_40[0x40]; 8741 8742 u8 scheduling_element_id[0x20]; 8743 8744 u8 reserved_at_a0[0x160]; 8745 }; 8746 8747 struct mlx5_ifc_create_scheduling_element_in_bits { 8748 u8 opcode[0x10]; 8749 u8 reserved_at_10[0x10]; 8750 8751 u8 reserved_at_20[0x10]; 8752 u8 op_mod[0x10]; 8753 8754 u8 scheduling_hierarchy[0x8]; 8755 u8 reserved_at_48[0x18]; 8756 8757 u8 reserved_at_60[0xa0]; 8758 8759 struct mlx5_ifc_scheduling_context_bits scheduling_context; 8760 8761 u8 reserved_at_300[0x100]; 8762 }; 8763 8764 struct mlx5_ifc_create_rqt_out_bits { 8765 u8 status[0x8]; 8766 u8 reserved_at_8[0x18]; 8767 8768 u8 syndrome[0x20]; 8769 8770 u8 reserved_at_40[0x8]; 8771 u8 rqtn[0x18]; 8772 8773 u8 reserved_at_60[0x20]; 8774 }; 8775 8776 struct mlx5_ifc_create_rqt_in_bits { 8777 u8 opcode[0x10]; 8778 u8 uid[0x10]; 8779 8780 u8 reserved_at_20[0x10]; 8781 u8 op_mod[0x10]; 8782 8783 u8 reserved_at_40[0xc0]; 8784 8785 struct mlx5_ifc_rqtc_bits rqt_context; 8786 }; 8787 8788 struct mlx5_ifc_create_rq_out_bits { 8789 u8 status[0x8]; 8790 u8 reserved_at_8[0x18]; 8791 8792 u8 syndrome[0x20]; 8793 8794 u8 reserved_at_40[0x8]; 8795 u8 rqn[0x18]; 8796 8797 u8 reserved_at_60[0x20]; 8798 }; 8799 8800 struct mlx5_ifc_create_rq_in_bits { 8801 u8 opcode[0x10]; 8802 u8 uid[0x10]; 8803 8804 u8 reserved_at_20[0x10]; 8805 u8 op_mod[0x10]; 8806 8807 u8 reserved_at_40[0xc0]; 8808 8809 struct mlx5_ifc_rqc_bits ctx; 8810 }; 8811 8812 struct mlx5_ifc_create_rmp_out_bits { 8813 u8 status[0x8]; 8814 u8 reserved_at_8[0x18]; 8815 8816 u8 syndrome[0x20]; 8817 8818 u8 reserved_at_40[0x8]; 8819 u8 rmpn[0x18]; 8820 8821 u8 reserved_at_60[0x20]; 8822 }; 8823 8824 struct mlx5_ifc_create_rmp_in_bits { 8825 u8 opcode[0x10]; 8826 u8 uid[0x10]; 8827 8828 u8 reserved_at_20[0x10]; 8829 u8 op_mod[0x10]; 8830 8831 u8 reserved_at_40[0xc0]; 8832 8833 struct mlx5_ifc_rmpc_bits ctx; 8834 }; 8835 8836 struct mlx5_ifc_create_qp_out_bits { 8837 u8 status[0x8]; 8838 u8 reserved_at_8[0x18]; 8839 8840 u8 syndrome[0x20]; 8841 8842 u8 reserved_at_40[0x8]; 8843 u8 qpn[0x18]; 8844 8845 u8 ece[0x20]; 8846 }; 8847 8848 struct mlx5_ifc_create_qp_in_bits { 8849 u8 opcode[0x10]; 8850 u8 uid[0x10]; 8851 8852 u8 reserved_at_20[0x10]; 8853 u8 op_mod[0x10]; 8854 8855 u8 qpc_ext[0x1]; 8856 u8 reserved_at_41[0x7]; 8857 u8 input_qpn[0x18]; 8858 8859 u8 reserved_at_60[0x20]; 8860 u8 opt_param_mask[0x20]; 8861 8862 u8 ece[0x20]; 8863 8864 struct mlx5_ifc_qpc_bits qpc; 8865 8866 u8 reserved_at_800[0x60]; 8867 8868 u8 wq_umem_valid[0x1]; 8869 u8 reserved_at_861[0x1f]; 8870 8871 u8 pas[][0x40]; 8872 }; 8873 8874 struct mlx5_ifc_create_psv_out_bits { 8875 u8 status[0x8]; 8876 u8 reserved_at_8[0x18]; 8877 8878 u8 syndrome[0x20]; 8879 8880 u8 reserved_at_40[0x40]; 8881 8882 u8 reserved_at_80[0x8]; 8883 u8 psv0_index[0x18]; 8884 8885 u8 reserved_at_a0[0x8]; 8886 u8 psv1_index[0x18]; 8887 8888 u8 reserved_at_c0[0x8]; 8889 u8 psv2_index[0x18]; 8890 8891 u8 reserved_at_e0[0x8]; 8892 u8 psv3_index[0x18]; 8893 }; 8894 8895 struct mlx5_ifc_create_psv_in_bits { 8896 u8 opcode[0x10]; 8897 u8 reserved_at_10[0x10]; 8898 8899 u8 reserved_at_20[0x10]; 8900 u8 op_mod[0x10]; 8901 8902 u8 num_psv[0x4]; 8903 u8 reserved_at_44[0x4]; 8904 u8 pd[0x18]; 8905 8906 u8 reserved_at_60[0x20]; 8907 }; 8908 8909 struct mlx5_ifc_create_mkey_out_bits { 8910 u8 status[0x8]; 8911 u8 reserved_at_8[0x18]; 8912 8913 u8 syndrome[0x20]; 8914 8915 u8 reserved_at_40[0x8]; 8916 u8 mkey_index[0x18]; 8917 8918 u8 reserved_at_60[0x20]; 8919 }; 8920 8921 struct mlx5_ifc_create_mkey_in_bits { 8922 u8 opcode[0x10]; 8923 u8 uid[0x10]; 8924 8925 u8 reserved_at_20[0x10]; 8926 u8 op_mod[0x10]; 8927 8928 u8 reserved_at_40[0x20]; 8929 8930 u8 pg_access[0x1]; 8931 u8 mkey_umem_valid[0x1]; 8932 u8 reserved_at_62[0x1e]; 8933 8934 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 8935 8936 u8 reserved_at_280[0x80]; 8937 8938 u8 translations_octword_actual_size[0x20]; 8939 8940 u8 reserved_at_320[0x560]; 8941 8942 u8 klm_pas_mtt[][0x20]; 8943 }; 8944 8945 enum { 8946 MLX5_FLOW_TABLE_TYPE_NIC_RX = 0x0, 8947 MLX5_FLOW_TABLE_TYPE_NIC_TX = 0x1, 8948 MLX5_FLOW_TABLE_TYPE_ESW_EGRESS_ACL = 0x2, 8949 MLX5_FLOW_TABLE_TYPE_ESW_INGRESS_ACL = 0x3, 8950 MLX5_FLOW_TABLE_TYPE_FDB = 0X4, 8951 MLX5_FLOW_TABLE_TYPE_SNIFFER_RX = 0X5, 8952 MLX5_FLOW_TABLE_TYPE_SNIFFER_TX = 0X6, 8953 }; 8954 8955 struct mlx5_ifc_create_flow_table_out_bits { 8956 u8 status[0x8]; 8957 u8 icm_address_63_40[0x18]; 8958 8959 u8 syndrome[0x20]; 8960 8961 u8 icm_address_39_32[0x8]; 8962 u8 table_id[0x18]; 8963 8964 u8 icm_address_31_0[0x20]; 8965 }; 8966 8967 struct mlx5_ifc_create_flow_table_in_bits { 8968 u8 opcode[0x10]; 8969 u8 uid[0x10]; 8970 8971 u8 reserved_at_20[0x10]; 8972 u8 op_mod[0x10]; 8973 8974 u8 other_vport[0x1]; 8975 u8 reserved_at_41[0xf]; 8976 u8 vport_number[0x10]; 8977 8978 u8 reserved_at_60[0x20]; 8979 8980 u8 table_type[0x8]; 8981 u8 reserved_at_88[0x18]; 8982 8983 u8 reserved_at_a0[0x20]; 8984 8985 struct mlx5_ifc_flow_table_context_bits flow_table_context; 8986 }; 8987 8988 struct mlx5_ifc_create_flow_group_out_bits { 8989 u8 status[0x8]; 8990 u8 reserved_at_8[0x18]; 8991 8992 u8 syndrome[0x20]; 8993 8994 u8 reserved_at_40[0x8]; 8995 u8 group_id[0x18]; 8996 8997 u8 reserved_at_60[0x20]; 8998 }; 8999 9000 enum { 9001 MLX5_CREATE_FLOW_GROUP_IN_GROUP_TYPE_TCAM_SUBTABLE = 0x0, 9002 MLX5_CREATE_FLOW_GROUP_IN_GROUP_TYPE_HASH_SPLIT = 0x1, 9003 }; 9004 9005 enum { 9006 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 9007 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 9008 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 9009 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3, 9010 }; 9011 9012 struct mlx5_ifc_create_flow_group_in_bits { 9013 u8 opcode[0x10]; 9014 u8 reserved_at_10[0x10]; 9015 9016 u8 reserved_at_20[0x10]; 9017 u8 op_mod[0x10]; 9018 9019 u8 other_vport[0x1]; 9020 u8 reserved_at_41[0xf]; 9021 u8 vport_number[0x10]; 9022 9023 u8 reserved_at_60[0x20]; 9024 9025 u8 table_type[0x8]; 9026 u8 reserved_at_88[0x4]; 9027 u8 group_type[0x4]; 9028 u8 reserved_at_90[0x10]; 9029 9030 u8 reserved_at_a0[0x8]; 9031 u8 table_id[0x18]; 9032 9033 u8 source_eswitch_owner_vhca_id_valid[0x1]; 9034 9035 u8 reserved_at_c1[0x1f]; 9036 9037 u8 start_flow_index[0x20]; 9038 9039 u8 reserved_at_100[0x20]; 9040 9041 u8 end_flow_index[0x20]; 9042 9043 u8 reserved_at_140[0x10]; 9044 u8 match_definer_id[0x10]; 9045 9046 u8 reserved_at_160[0x80]; 9047 9048 u8 reserved_at_1e0[0x18]; 9049 u8 match_criteria_enable[0x8]; 9050 9051 struct mlx5_ifc_fte_match_param_bits match_criteria; 9052 9053 u8 reserved_at_1200[0xe00]; 9054 }; 9055 9056 struct mlx5_ifc_create_eq_out_bits { 9057 u8 status[0x8]; 9058 u8 reserved_at_8[0x18]; 9059 9060 u8 syndrome[0x20]; 9061 9062 u8 reserved_at_40[0x18]; 9063 u8 eq_number[0x8]; 9064 9065 u8 reserved_at_60[0x20]; 9066 }; 9067 9068 struct mlx5_ifc_create_eq_in_bits { 9069 u8 opcode[0x10]; 9070 u8 uid[0x10]; 9071 9072 u8 reserved_at_20[0x10]; 9073 u8 op_mod[0x10]; 9074 9075 u8 reserved_at_40[0x40]; 9076 9077 struct mlx5_ifc_eqc_bits eq_context_entry; 9078 9079 u8 reserved_at_280[0x40]; 9080 9081 u8 event_bitmask[4][0x40]; 9082 9083 u8 reserved_at_3c0[0x4c0]; 9084 9085 u8 pas[][0x40]; 9086 }; 9087 9088 struct mlx5_ifc_create_dct_out_bits { 9089 u8 status[0x8]; 9090 u8 reserved_at_8[0x18]; 9091 9092 u8 syndrome[0x20]; 9093 9094 u8 reserved_at_40[0x8]; 9095 u8 dctn[0x18]; 9096 9097 u8 ece[0x20]; 9098 }; 9099 9100 struct mlx5_ifc_create_dct_in_bits { 9101 u8 opcode[0x10]; 9102 u8 uid[0x10]; 9103 9104 u8 reserved_at_20[0x10]; 9105 u8 op_mod[0x10]; 9106 9107 u8 reserved_at_40[0x40]; 9108 9109 struct mlx5_ifc_dctc_bits dct_context_entry; 9110 9111 u8 reserved_at_280[0x180]; 9112 }; 9113 9114 struct mlx5_ifc_create_cq_out_bits { 9115 u8 status[0x8]; 9116 u8 reserved_at_8[0x18]; 9117 9118 u8 syndrome[0x20]; 9119 9120 u8 reserved_at_40[0x8]; 9121 u8 cqn[0x18]; 9122 9123 u8 reserved_at_60[0x20]; 9124 }; 9125 9126 struct mlx5_ifc_create_cq_in_bits { 9127 u8 opcode[0x10]; 9128 u8 uid[0x10]; 9129 9130 u8 reserved_at_20[0x10]; 9131 u8 op_mod[0x10]; 9132 9133 u8 reserved_at_40[0x40]; 9134 9135 struct mlx5_ifc_cqc_bits cq_context; 9136 9137 u8 reserved_at_280[0x60]; 9138 9139 u8 cq_umem_valid[0x1]; 9140 u8 reserved_at_2e1[0x59f]; 9141 9142 u8 pas[][0x40]; 9143 }; 9144 9145 struct mlx5_ifc_config_int_moderation_out_bits { 9146 u8 status[0x8]; 9147 u8 reserved_at_8[0x18]; 9148 9149 u8 syndrome[0x20]; 9150 9151 u8 reserved_at_40[0x4]; 9152 u8 min_delay[0xc]; 9153 u8 int_vector[0x10]; 9154 9155 u8 reserved_at_60[0x20]; 9156 }; 9157 9158 enum { 9159 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0, 9160 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1, 9161 }; 9162 9163 struct mlx5_ifc_config_int_moderation_in_bits { 9164 u8 opcode[0x10]; 9165 u8 reserved_at_10[0x10]; 9166 9167 u8 reserved_at_20[0x10]; 9168 u8 op_mod[0x10]; 9169 9170 u8 reserved_at_40[0x4]; 9171 u8 min_delay[0xc]; 9172 u8 int_vector[0x10]; 9173 9174 u8 reserved_at_60[0x20]; 9175 }; 9176 9177 struct mlx5_ifc_attach_to_mcg_out_bits { 9178 u8 status[0x8]; 9179 u8 reserved_at_8[0x18]; 9180 9181 u8 syndrome[0x20]; 9182 9183 u8 reserved_at_40[0x40]; 9184 }; 9185 9186 struct mlx5_ifc_attach_to_mcg_in_bits { 9187 u8 opcode[0x10]; 9188 u8 uid[0x10]; 9189 9190 u8 reserved_at_20[0x10]; 9191 u8 op_mod[0x10]; 9192 9193 u8 reserved_at_40[0x8]; 9194 u8 qpn[0x18]; 9195 9196 u8 reserved_at_60[0x20]; 9197 9198 u8 multicast_gid[16][0x8]; 9199 }; 9200 9201 struct mlx5_ifc_arm_xrq_out_bits { 9202 u8 status[0x8]; 9203 u8 reserved_at_8[0x18]; 9204 9205 u8 syndrome[0x20]; 9206 9207 u8 reserved_at_40[0x40]; 9208 }; 9209 9210 struct mlx5_ifc_arm_xrq_in_bits { 9211 u8 opcode[0x10]; 9212 u8 reserved_at_10[0x10]; 9213 9214 u8 reserved_at_20[0x10]; 9215 u8 op_mod[0x10]; 9216 9217 u8 reserved_at_40[0x8]; 9218 u8 xrqn[0x18]; 9219 9220 u8 reserved_at_60[0x10]; 9221 u8 lwm[0x10]; 9222 }; 9223 9224 struct mlx5_ifc_arm_xrc_srq_out_bits { 9225 u8 status[0x8]; 9226 u8 reserved_at_8[0x18]; 9227 9228 u8 syndrome[0x20]; 9229 9230 u8 reserved_at_40[0x40]; 9231 }; 9232 9233 enum { 9234 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1, 9235 }; 9236 9237 struct mlx5_ifc_arm_xrc_srq_in_bits { 9238 u8 opcode[0x10]; 9239 u8 uid[0x10]; 9240 9241 u8 reserved_at_20[0x10]; 9242 u8 op_mod[0x10]; 9243 9244 u8 reserved_at_40[0x8]; 9245 u8 xrc_srqn[0x18]; 9246 9247 u8 reserved_at_60[0x10]; 9248 u8 lwm[0x10]; 9249 }; 9250 9251 struct mlx5_ifc_arm_rq_out_bits { 9252 u8 status[0x8]; 9253 u8 reserved_at_8[0x18]; 9254 9255 u8 syndrome[0x20]; 9256 9257 u8 reserved_at_40[0x40]; 9258 }; 9259 9260 enum { 9261 MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1, 9262 MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2, 9263 }; 9264 9265 struct mlx5_ifc_arm_rq_in_bits { 9266 u8 opcode[0x10]; 9267 u8 uid[0x10]; 9268 9269 u8 reserved_at_20[0x10]; 9270 u8 op_mod[0x10]; 9271 9272 u8 reserved_at_40[0x8]; 9273 u8 srq_number[0x18]; 9274 9275 u8 reserved_at_60[0x10]; 9276 u8 lwm[0x10]; 9277 }; 9278 9279 struct mlx5_ifc_arm_dct_out_bits { 9280 u8 status[0x8]; 9281 u8 reserved_at_8[0x18]; 9282 9283 u8 syndrome[0x20]; 9284 9285 u8 reserved_at_40[0x40]; 9286 }; 9287 9288 struct mlx5_ifc_arm_dct_in_bits { 9289 u8 opcode[0x10]; 9290 u8 reserved_at_10[0x10]; 9291 9292 u8 reserved_at_20[0x10]; 9293 u8 op_mod[0x10]; 9294 9295 u8 reserved_at_40[0x8]; 9296 u8 dct_number[0x18]; 9297 9298 u8 reserved_at_60[0x20]; 9299 }; 9300 9301 struct mlx5_ifc_alloc_xrcd_out_bits { 9302 u8 status[0x8]; 9303 u8 reserved_at_8[0x18]; 9304 9305 u8 syndrome[0x20]; 9306 9307 u8 reserved_at_40[0x8]; 9308 u8 xrcd[0x18]; 9309 9310 u8 reserved_at_60[0x20]; 9311 }; 9312 9313 struct mlx5_ifc_alloc_xrcd_in_bits { 9314 u8 opcode[0x10]; 9315 u8 uid[0x10]; 9316 9317 u8 reserved_at_20[0x10]; 9318 u8 op_mod[0x10]; 9319 9320 u8 reserved_at_40[0x40]; 9321 }; 9322 9323 struct mlx5_ifc_alloc_uar_out_bits { 9324 u8 status[0x8]; 9325 u8 reserved_at_8[0x18]; 9326 9327 u8 syndrome[0x20]; 9328 9329 u8 reserved_at_40[0x8]; 9330 u8 uar[0x18]; 9331 9332 u8 reserved_at_60[0x20]; 9333 }; 9334 9335 struct mlx5_ifc_alloc_uar_in_bits { 9336 u8 opcode[0x10]; 9337 u8 uid[0x10]; 9338 9339 u8 reserved_at_20[0x10]; 9340 u8 op_mod[0x10]; 9341 9342 u8 reserved_at_40[0x40]; 9343 }; 9344 9345 struct mlx5_ifc_alloc_transport_domain_out_bits { 9346 u8 status[0x8]; 9347 u8 reserved_at_8[0x18]; 9348 9349 u8 syndrome[0x20]; 9350 9351 u8 reserved_at_40[0x8]; 9352 u8 transport_domain[0x18]; 9353 9354 u8 reserved_at_60[0x20]; 9355 }; 9356 9357 struct mlx5_ifc_alloc_transport_domain_in_bits { 9358 u8 opcode[0x10]; 9359 u8 uid[0x10]; 9360 9361 u8 reserved_at_20[0x10]; 9362 u8 op_mod[0x10]; 9363 9364 u8 reserved_at_40[0x40]; 9365 }; 9366 9367 struct mlx5_ifc_alloc_q_counter_out_bits { 9368 u8 status[0x8]; 9369 u8 reserved_at_8[0x18]; 9370 9371 u8 syndrome[0x20]; 9372 9373 u8 reserved_at_40[0x18]; 9374 u8 counter_set_id[0x8]; 9375 9376 u8 reserved_at_60[0x20]; 9377 }; 9378 9379 struct mlx5_ifc_alloc_q_counter_in_bits { 9380 u8 opcode[0x10]; 9381 u8 uid[0x10]; 9382 9383 u8 reserved_at_20[0x10]; 9384 u8 op_mod[0x10]; 9385 9386 u8 reserved_at_40[0x40]; 9387 }; 9388 9389 struct mlx5_ifc_alloc_pd_out_bits { 9390 u8 status[0x8]; 9391 u8 reserved_at_8[0x18]; 9392 9393 u8 syndrome[0x20]; 9394 9395 u8 reserved_at_40[0x8]; 9396 u8 pd[0x18]; 9397 9398 u8 reserved_at_60[0x20]; 9399 }; 9400 9401 struct mlx5_ifc_alloc_pd_in_bits { 9402 u8 opcode[0x10]; 9403 u8 uid[0x10]; 9404 9405 u8 reserved_at_20[0x10]; 9406 u8 op_mod[0x10]; 9407 9408 u8 reserved_at_40[0x40]; 9409 }; 9410 9411 struct mlx5_ifc_alloc_flow_counter_out_bits { 9412 u8 status[0x8]; 9413 u8 reserved_at_8[0x18]; 9414 9415 u8 syndrome[0x20]; 9416 9417 u8 flow_counter_id[0x20]; 9418 9419 u8 reserved_at_60[0x20]; 9420 }; 9421 9422 struct mlx5_ifc_alloc_flow_counter_in_bits { 9423 u8 opcode[0x10]; 9424 u8 reserved_at_10[0x10]; 9425 9426 u8 reserved_at_20[0x10]; 9427 u8 op_mod[0x10]; 9428 9429 u8 reserved_at_40[0x33]; 9430 u8 flow_counter_bulk_log_size[0x5]; 9431 u8 flow_counter_bulk[0x8]; 9432 }; 9433 9434 struct mlx5_ifc_add_vxlan_udp_dport_out_bits { 9435 u8 status[0x8]; 9436 u8 reserved_at_8[0x18]; 9437 9438 u8 syndrome[0x20]; 9439 9440 u8 reserved_at_40[0x40]; 9441 }; 9442 9443 struct mlx5_ifc_add_vxlan_udp_dport_in_bits { 9444 u8 opcode[0x10]; 9445 u8 reserved_at_10[0x10]; 9446 9447 u8 reserved_at_20[0x10]; 9448 u8 op_mod[0x10]; 9449 9450 u8 reserved_at_40[0x20]; 9451 9452 u8 reserved_at_60[0x10]; 9453 u8 vxlan_udp_port[0x10]; 9454 }; 9455 9456 struct mlx5_ifc_set_pp_rate_limit_out_bits { 9457 u8 status[0x8]; 9458 u8 reserved_at_8[0x18]; 9459 9460 u8 syndrome[0x20]; 9461 9462 u8 reserved_at_40[0x40]; 9463 }; 9464 9465 struct mlx5_ifc_set_pp_rate_limit_context_bits { 9466 u8 rate_limit[0x20]; 9467 9468 u8 burst_upper_bound[0x20]; 9469 9470 u8 reserved_at_40[0x10]; 9471 u8 typical_packet_size[0x10]; 9472 9473 u8 reserved_at_60[0x120]; 9474 }; 9475 9476 struct mlx5_ifc_set_pp_rate_limit_in_bits { 9477 u8 opcode[0x10]; 9478 u8 uid[0x10]; 9479 9480 u8 reserved_at_20[0x10]; 9481 u8 op_mod[0x10]; 9482 9483 u8 reserved_at_40[0x10]; 9484 u8 rate_limit_index[0x10]; 9485 9486 u8 reserved_at_60[0x20]; 9487 9488 struct mlx5_ifc_set_pp_rate_limit_context_bits ctx; 9489 }; 9490 9491 struct mlx5_ifc_access_register_out_bits { 9492 u8 status[0x8]; 9493 u8 reserved_at_8[0x18]; 9494 9495 u8 syndrome[0x20]; 9496 9497 u8 reserved_at_40[0x40]; 9498 9499 u8 register_data[][0x20]; 9500 }; 9501 9502 enum { 9503 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0, 9504 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1, 9505 }; 9506 9507 struct mlx5_ifc_access_register_in_bits { 9508 u8 opcode[0x10]; 9509 u8 reserved_at_10[0x10]; 9510 9511 u8 reserved_at_20[0x10]; 9512 u8 op_mod[0x10]; 9513 9514 u8 reserved_at_40[0x10]; 9515 u8 register_id[0x10]; 9516 9517 u8 argument[0x20]; 9518 9519 u8 register_data[][0x20]; 9520 }; 9521 9522 struct mlx5_ifc_sltp_reg_bits { 9523 u8 status[0x4]; 9524 u8 version[0x4]; 9525 u8 local_port[0x8]; 9526 u8 pnat[0x2]; 9527 u8 reserved_at_12[0x2]; 9528 u8 lane[0x4]; 9529 u8 reserved_at_18[0x8]; 9530 9531 u8 reserved_at_20[0x20]; 9532 9533 u8 reserved_at_40[0x7]; 9534 u8 polarity[0x1]; 9535 u8 ob_tap0[0x8]; 9536 u8 ob_tap1[0x8]; 9537 u8 ob_tap2[0x8]; 9538 9539 u8 reserved_at_60[0xc]; 9540 u8 ob_preemp_mode[0x4]; 9541 u8 ob_reg[0x8]; 9542 u8 ob_bias[0x8]; 9543 9544 u8 reserved_at_80[0x20]; 9545 }; 9546 9547 struct mlx5_ifc_slrg_reg_bits { 9548 u8 status[0x4]; 9549 u8 version[0x4]; 9550 u8 local_port[0x8]; 9551 u8 pnat[0x2]; 9552 u8 reserved_at_12[0x2]; 9553 u8 lane[0x4]; 9554 u8 reserved_at_18[0x8]; 9555 9556 u8 time_to_link_up[0x10]; 9557 u8 reserved_at_30[0xc]; 9558 u8 grade_lane_speed[0x4]; 9559 9560 u8 grade_version[0x8]; 9561 u8 grade[0x18]; 9562 9563 u8 reserved_at_60[0x4]; 9564 u8 height_grade_type[0x4]; 9565 u8 height_grade[0x18]; 9566 9567 u8 height_dz[0x10]; 9568 u8 height_dv[0x10]; 9569 9570 u8 reserved_at_a0[0x10]; 9571 u8 height_sigma[0x10]; 9572 9573 u8 reserved_at_c0[0x20]; 9574 9575 u8 reserved_at_e0[0x4]; 9576 u8 phase_grade_type[0x4]; 9577 u8 phase_grade[0x18]; 9578 9579 u8 reserved_at_100[0x8]; 9580 u8 phase_eo_pos[0x8]; 9581 u8 reserved_at_110[0x8]; 9582 u8 phase_eo_neg[0x8]; 9583 9584 u8 ffe_set_tested[0x10]; 9585 u8 test_errors_per_lane[0x10]; 9586 }; 9587 9588 struct mlx5_ifc_pvlc_reg_bits { 9589 u8 reserved_at_0[0x8]; 9590 u8 local_port[0x8]; 9591 u8 reserved_at_10[0x10]; 9592 9593 u8 reserved_at_20[0x1c]; 9594 u8 vl_hw_cap[0x4]; 9595 9596 u8 reserved_at_40[0x1c]; 9597 u8 vl_admin[0x4]; 9598 9599 u8 reserved_at_60[0x1c]; 9600 u8 vl_operational[0x4]; 9601 }; 9602 9603 struct mlx5_ifc_pude_reg_bits { 9604 u8 swid[0x8]; 9605 u8 local_port[0x8]; 9606 u8 reserved_at_10[0x4]; 9607 u8 admin_status[0x4]; 9608 u8 reserved_at_18[0x4]; 9609 u8 oper_status[0x4]; 9610 9611 u8 reserved_at_20[0x60]; 9612 }; 9613 9614 struct mlx5_ifc_ptys_reg_bits { 9615 u8 reserved_at_0[0x1]; 9616 u8 an_disable_admin[0x1]; 9617 u8 an_disable_cap[0x1]; 9618 u8 reserved_at_3[0x5]; 9619 u8 local_port[0x8]; 9620 u8 reserved_at_10[0xd]; 9621 u8 proto_mask[0x3]; 9622 9623 u8 an_status[0x4]; 9624 u8 reserved_at_24[0xc]; 9625 u8 data_rate_oper[0x10]; 9626 9627 u8 ext_eth_proto_capability[0x20]; 9628 9629 u8 eth_proto_capability[0x20]; 9630 9631 u8 ib_link_width_capability[0x10]; 9632 u8 ib_proto_capability[0x10]; 9633 9634 u8 ext_eth_proto_admin[0x20]; 9635 9636 u8 eth_proto_admin[0x20]; 9637 9638 u8 ib_link_width_admin[0x10]; 9639 u8 ib_proto_admin[0x10]; 9640 9641 u8 ext_eth_proto_oper[0x20]; 9642 9643 u8 eth_proto_oper[0x20]; 9644 9645 u8 ib_link_width_oper[0x10]; 9646 u8 ib_proto_oper[0x10]; 9647 9648 u8 reserved_at_160[0x1c]; 9649 u8 connector_type[0x4]; 9650 9651 u8 eth_proto_lp_advertise[0x20]; 9652 9653 u8 reserved_at_1a0[0x60]; 9654 }; 9655 9656 struct mlx5_ifc_mlcr_reg_bits { 9657 u8 reserved_at_0[0x8]; 9658 u8 local_port[0x8]; 9659 u8 reserved_at_10[0x20]; 9660 9661 u8 beacon_duration[0x10]; 9662 u8 reserved_at_40[0x10]; 9663 9664 u8 beacon_remain[0x10]; 9665 }; 9666 9667 struct mlx5_ifc_ptas_reg_bits { 9668 u8 reserved_at_0[0x20]; 9669 9670 u8 algorithm_options[0x10]; 9671 u8 reserved_at_30[0x4]; 9672 u8 repetitions_mode[0x4]; 9673 u8 num_of_repetitions[0x8]; 9674 9675 u8 grade_version[0x8]; 9676 u8 height_grade_type[0x4]; 9677 u8 phase_grade_type[0x4]; 9678 u8 height_grade_weight[0x8]; 9679 u8 phase_grade_weight[0x8]; 9680 9681 u8 gisim_measure_bits[0x10]; 9682 u8 adaptive_tap_measure_bits[0x10]; 9683 9684 u8 ber_bath_high_error_threshold[0x10]; 9685 u8 ber_bath_mid_error_threshold[0x10]; 9686 9687 u8 ber_bath_low_error_threshold[0x10]; 9688 u8 one_ratio_high_threshold[0x10]; 9689 9690 u8 one_ratio_high_mid_threshold[0x10]; 9691 u8 one_ratio_low_mid_threshold[0x10]; 9692 9693 u8 one_ratio_low_threshold[0x10]; 9694 u8 ndeo_error_threshold[0x10]; 9695 9696 u8 mixer_offset_step_size[0x10]; 9697 u8 reserved_at_110[0x8]; 9698 u8 mix90_phase_for_voltage_bath[0x8]; 9699 9700 u8 mixer_offset_start[0x10]; 9701 u8 mixer_offset_end[0x10]; 9702 9703 u8 reserved_at_140[0x15]; 9704 u8 ber_test_time[0xb]; 9705 }; 9706 9707 struct mlx5_ifc_pspa_reg_bits { 9708 u8 swid[0x8]; 9709 u8 local_port[0x8]; 9710 u8 sub_port[0x8]; 9711 u8 reserved_at_18[0x8]; 9712 9713 u8 reserved_at_20[0x20]; 9714 }; 9715 9716 struct mlx5_ifc_pqdr_reg_bits { 9717 u8 reserved_at_0[0x8]; 9718 u8 local_port[0x8]; 9719 u8 reserved_at_10[0x5]; 9720 u8 prio[0x3]; 9721 u8 reserved_at_18[0x6]; 9722 u8 mode[0x2]; 9723 9724 u8 reserved_at_20[0x20]; 9725 9726 u8 reserved_at_40[0x10]; 9727 u8 min_threshold[0x10]; 9728 9729 u8 reserved_at_60[0x10]; 9730 u8 max_threshold[0x10]; 9731 9732 u8 reserved_at_80[0x10]; 9733 u8 mark_probability_denominator[0x10]; 9734 9735 u8 reserved_at_a0[0x60]; 9736 }; 9737 9738 struct mlx5_ifc_ppsc_reg_bits { 9739 u8 reserved_at_0[0x8]; 9740 u8 local_port[0x8]; 9741 u8 reserved_at_10[0x10]; 9742 9743 u8 reserved_at_20[0x60]; 9744 9745 u8 reserved_at_80[0x1c]; 9746 u8 wrps_admin[0x4]; 9747 9748 u8 reserved_at_a0[0x1c]; 9749 u8 wrps_status[0x4]; 9750 9751 u8 reserved_at_c0[0x8]; 9752 u8 up_threshold[0x8]; 9753 u8 reserved_at_d0[0x8]; 9754 u8 down_threshold[0x8]; 9755 9756 u8 reserved_at_e0[0x20]; 9757 9758 u8 reserved_at_100[0x1c]; 9759 u8 srps_admin[0x4]; 9760 9761 u8 reserved_at_120[0x1c]; 9762 u8 srps_status[0x4]; 9763 9764 u8 reserved_at_140[0x40]; 9765 }; 9766 9767 struct mlx5_ifc_pplr_reg_bits { 9768 u8 reserved_at_0[0x8]; 9769 u8 local_port[0x8]; 9770 u8 reserved_at_10[0x10]; 9771 9772 u8 reserved_at_20[0x8]; 9773 u8 lb_cap[0x8]; 9774 u8 reserved_at_30[0x8]; 9775 u8 lb_en[0x8]; 9776 }; 9777 9778 struct mlx5_ifc_pplm_reg_bits { 9779 u8 reserved_at_0[0x8]; 9780 u8 local_port[0x8]; 9781 u8 reserved_at_10[0x10]; 9782 9783 u8 reserved_at_20[0x20]; 9784 9785 u8 port_profile_mode[0x8]; 9786 u8 static_port_profile[0x8]; 9787 u8 active_port_profile[0x8]; 9788 u8 reserved_at_58[0x8]; 9789 9790 u8 retransmission_active[0x8]; 9791 u8 fec_mode_active[0x18]; 9792 9793 u8 rs_fec_correction_bypass_cap[0x4]; 9794 u8 reserved_at_84[0x8]; 9795 u8 fec_override_cap_56g[0x4]; 9796 u8 fec_override_cap_100g[0x4]; 9797 u8 fec_override_cap_50g[0x4]; 9798 u8 fec_override_cap_25g[0x4]; 9799 u8 fec_override_cap_10g_40g[0x4]; 9800 9801 u8 rs_fec_correction_bypass_admin[0x4]; 9802 u8 reserved_at_a4[0x8]; 9803 u8 fec_override_admin_56g[0x4]; 9804 u8 fec_override_admin_100g[0x4]; 9805 u8 fec_override_admin_50g[0x4]; 9806 u8 fec_override_admin_25g[0x4]; 9807 u8 fec_override_admin_10g_40g[0x4]; 9808 9809 u8 fec_override_cap_400g_8x[0x10]; 9810 u8 fec_override_cap_200g_4x[0x10]; 9811 9812 u8 fec_override_cap_100g_2x[0x10]; 9813 u8 fec_override_cap_50g_1x[0x10]; 9814 9815 u8 fec_override_admin_400g_8x[0x10]; 9816 u8 fec_override_admin_200g_4x[0x10]; 9817 9818 u8 fec_override_admin_100g_2x[0x10]; 9819 u8 fec_override_admin_50g_1x[0x10]; 9820 9821 u8 fec_override_cap_800g_8x[0x10]; 9822 u8 fec_override_cap_400g_4x[0x10]; 9823 9824 u8 fec_override_cap_200g_2x[0x10]; 9825 u8 fec_override_cap_100g_1x[0x10]; 9826 9827 u8 reserved_at_180[0xa0]; 9828 9829 u8 fec_override_admin_800g_8x[0x10]; 9830 u8 fec_override_admin_400g_4x[0x10]; 9831 9832 u8 fec_override_admin_200g_2x[0x10]; 9833 u8 fec_override_admin_100g_1x[0x10]; 9834 9835 u8 reserved_at_260[0x20]; 9836 }; 9837 9838 struct mlx5_ifc_ppcnt_reg_bits { 9839 u8 swid[0x8]; 9840 u8 local_port[0x8]; 9841 u8 pnat[0x2]; 9842 u8 reserved_at_12[0x8]; 9843 u8 grp[0x6]; 9844 9845 u8 clr[0x1]; 9846 u8 reserved_at_21[0x1c]; 9847 u8 prio_tc[0x3]; 9848 9849 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set; 9850 }; 9851 9852 struct mlx5_ifc_mpein_reg_bits { 9853 u8 reserved_at_0[0x2]; 9854 u8 depth[0x6]; 9855 u8 pcie_index[0x8]; 9856 u8 node[0x8]; 9857 u8 reserved_at_18[0x8]; 9858 9859 u8 capability_mask[0x20]; 9860 9861 u8 reserved_at_40[0x8]; 9862 u8 link_width_enabled[0x8]; 9863 u8 link_speed_enabled[0x10]; 9864 9865 u8 lane0_physical_position[0x8]; 9866 u8 link_width_active[0x8]; 9867 u8 link_speed_active[0x10]; 9868 9869 u8 num_of_pfs[0x10]; 9870 u8 num_of_vfs[0x10]; 9871 9872 u8 bdf0[0x10]; 9873 u8 reserved_at_b0[0x10]; 9874 9875 u8 max_read_request_size[0x4]; 9876 u8 max_payload_size[0x4]; 9877 u8 reserved_at_c8[0x5]; 9878 u8 pwr_status[0x3]; 9879 u8 port_type[0x4]; 9880 u8 reserved_at_d4[0xb]; 9881 u8 lane_reversal[0x1]; 9882 9883 u8 reserved_at_e0[0x14]; 9884 u8 pci_power[0xc]; 9885 9886 u8 reserved_at_100[0x20]; 9887 9888 u8 device_status[0x10]; 9889 u8 port_state[0x8]; 9890 u8 reserved_at_138[0x8]; 9891 9892 u8 reserved_at_140[0x10]; 9893 u8 receiver_detect_result[0x10]; 9894 9895 u8 reserved_at_160[0x20]; 9896 }; 9897 9898 struct mlx5_ifc_mpcnt_reg_bits { 9899 u8 reserved_at_0[0x8]; 9900 u8 pcie_index[0x8]; 9901 u8 reserved_at_10[0xa]; 9902 u8 grp[0x6]; 9903 9904 u8 clr[0x1]; 9905 u8 reserved_at_21[0x1f]; 9906 9907 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set; 9908 }; 9909 9910 struct mlx5_ifc_ppad_reg_bits { 9911 u8 reserved_at_0[0x3]; 9912 u8 single_mac[0x1]; 9913 u8 reserved_at_4[0x4]; 9914 u8 local_port[0x8]; 9915 u8 mac_47_32[0x10]; 9916 9917 u8 mac_31_0[0x20]; 9918 9919 u8 reserved_at_40[0x40]; 9920 }; 9921 9922 struct mlx5_ifc_pmtu_reg_bits { 9923 u8 reserved_at_0[0x8]; 9924 u8 local_port[0x8]; 9925 u8 reserved_at_10[0x10]; 9926 9927 u8 max_mtu[0x10]; 9928 u8 reserved_at_30[0x10]; 9929 9930 u8 admin_mtu[0x10]; 9931 u8 reserved_at_50[0x10]; 9932 9933 u8 oper_mtu[0x10]; 9934 u8 reserved_at_70[0x10]; 9935 }; 9936 9937 struct mlx5_ifc_pmpr_reg_bits { 9938 u8 reserved_at_0[0x8]; 9939 u8 module[0x8]; 9940 u8 reserved_at_10[0x10]; 9941 9942 u8 reserved_at_20[0x18]; 9943 u8 attenuation_5g[0x8]; 9944 9945 u8 reserved_at_40[0x18]; 9946 u8 attenuation_7g[0x8]; 9947 9948 u8 reserved_at_60[0x18]; 9949 u8 attenuation_12g[0x8]; 9950 }; 9951 9952 struct mlx5_ifc_pmpe_reg_bits { 9953 u8 reserved_at_0[0x8]; 9954 u8 module[0x8]; 9955 u8 reserved_at_10[0xc]; 9956 u8 module_status[0x4]; 9957 9958 u8 reserved_at_20[0x60]; 9959 }; 9960 9961 struct mlx5_ifc_pmpc_reg_bits { 9962 u8 module_state_updated[32][0x8]; 9963 }; 9964 9965 struct mlx5_ifc_pmlpn_reg_bits { 9966 u8 reserved_at_0[0x4]; 9967 u8 mlpn_status[0x4]; 9968 u8 local_port[0x8]; 9969 u8 reserved_at_10[0x10]; 9970 9971 u8 e[0x1]; 9972 u8 reserved_at_21[0x1f]; 9973 }; 9974 9975 struct mlx5_ifc_pmlp_reg_bits { 9976 u8 rxtx[0x1]; 9977 u8 reserved_at_1[0x7]; 9978 u8 local_port[0x8]; 9979 u8 reserved_at_10[0x8]; 9980 u8 width[0x8]; 9981 9982 u8 lane0_module_mapping[0x20]; 9983 9984 u8 lane1_module_mapping[0x20]; 9985 9986 u8 lane2_module_mapping[0x20]; 9987 9988 u8 lane3_module_mapping[0x20]; 9989 9990 u8 reserved_at_a0[0x160]; 9991 }; 9992 9993 struct mlx5_ifc_pmaos_reg_bits { 9994 u8 reserved_at_0[0x8]; 9995 u8 module[0x8]; 9996 u8 reserved_at_10[0x4]; 9997 u8 admin_status[0x4]; 9998 u8 reserved_at_18[0x4]; 9999 u8 oper_status[0x4]; 10000 10001 u8 ase[0x1]; 10002 u8 ee[0x1]; 10003 u8 reserved_at_22[0x1c]; 10004 u8 e[0x2]; 10005 10006 u8 reserved_at_40[0x40]; 10007 }; 10008 10009 struct mlx5_ifc_plpc_reg_bits { 10010 u8 reserved_at_0[0x4]; 10011 u8 profile_id[0xc]; 10012 u8 reserved_at_10[0x4]; 10013 u8 proto_mask[0x4]; 10014 u8 reserved_at_18[0x8]; 10015 10016 u8 reserved_at_20[0x10]; 10017 u8 lane_speed[0x10]; 10018 10019 u8 reserved_at_40[0x17]; 10020 u8 lpbf[0x1]; 10021 u8 fec_mode_policy[0x8]; 10022 10023 u8 retransmission_capability[0x8]; 10024 u8 fec_mode_capability[0x18]; 10025 10026 u8 retransmission_support_admin[0x8]; 10027 u8 fec_mode_support_admin[0x18]; 10028 10029 u8 retransmission_request_admin[0x8]; 10030 u8 fec_mode_request_admin[0x18]; 10031 10032 u8 reserved_at_c0[0x80]; 10033 }; 10034 10035 struct mlx5_ifc_plib_reg_bits { 10036 u8 reserved_at_0[0x8]; 10037 u8 local_port[0x8]; 10038 u8 reserved_at_10[0x8]; 10039 u8 ib_port[0x8]; 10040 10041 u8 reserved_at_20[0x60]; 10042 }; 10043 10044 struct mlx5_ifc_plbf_reg_bits { 10045 u8 reserved_at_0[0x8]; 10046 u8 local_port[0x8]; 10047 u8 reserved_at_10[0xd]; 10048 u8 lbf_mode[0x3]; 10049 10050 u8 reserved_at_20[0x20]; 10051 }; 10052 10053 struct mlx5_ifc_pipg_reg_bits { 10054 u8 reserved_at_0[0x8]; 10055 u8 local_port[0x8]; 10056 u8 reserved_at_10[0x10]; 10057 10058 u8 dic[0x1]; 10059 u8 reserved_at_21[0x19]; 10060 u8 ipg[0x4]; 10061 u8 reserved_at_3e[0x2]; 10062 }; 10063 10064 struct mlx5_ifc_pifr_reg_bits { 10065 u8 reserved_at_0[0x8]; 10066 u8 local_port[0x8]; 10067 u8 reserved_at_10[0x10]; 10068 10069 u8 reserved_at_20[0xe0]; 10070 10071 u8 port_filter[8][0x20]; 10072 10073 u8 port_filter_update_en[8][0x20]; 10074 }; 10075 10076 struct mlx5_ifc_pfcc_reg_bits { 10077 u8 reserved_at_0[0x8]; 10078 u8 local_port[0x8]; 10079 u8 reserved_at_10[0xb]; 10080 u8 ppan_mask_n[0x1]; 10081 u8 minor_stall_mask[0x1]; 10082 u8 critical_stall_mask[0x1]; 10083 u8 reserved_at_1e[0x2]; 10084 10085 u8 ppan[0x4]; 10086 u8 reserved_at_24[0x4]; 10087 u8 prio_mask_tx[0x8]; 10088 u8 reserved_at_30[0x8]; 10089 u8 prio_mask_rx[0x8]; 10090 10091 u8 pptx[0x1]; 10092 u8 aptx[0x1]; 10093 u8 pptx_mask_n[0x1]; 10094 u8 reserved_at_43[0x5]; 10095 u8 pfctx[0x8]; 10096 u8 reserved_at_50[0x10]; 10097 10098 u8 pprx[0x1]; 10099 u8 aprx[0x1]; 10100 u8 pprx_mask_n[0x1]; 10101 u8 reserved_at_63[0x5]; 10102 u8 pfcrx[0x8]; 10103 u8 reserved_at_70[0x10]; 10104 10105 u8 device_stall_minor_watermark[0x10]; 10106 u8 device_stall_critical_watermark[0x10]; 10107 10108 u8 reserved_at_a0[0x60]; 10109 }; 10110 10111 struct mlx5_ifc_pelc_reg_bits { 10112 u8 op[0x4]; 10113 u8 reserved_at_4[0x4]; 10114 u8 local_port[0x8]; 10115 u8 reserved_at_10[0x10]; 10116 10117 u8 op_admin[0x8]; 10118 u8 op_capability[0x8]; 10119 u8 op_request[0x8]; 10120 u8 op_active[0x8]; 10121 10122 u8 admin[0x40]; 10123 10124 u8 capability[0x40]; 10125 10126 u8 request[0x40]; 10127 10128 u8 active[0x40]; 10129 10130 u8 reserved_at_140[0x80]; 10131 }; 10132 10133 struct mlx5_ifc_peir_reg_bits { 10134 u8 reserved_at_0[0x8]; 10135 u8 local_port[0x8]; 10136 u8 reserved_at_10[0x10]; 10137 10138 u8 reserved_at_20[0xc]; 10139 u8 error_count[0x4]; 10140 u8 reserved_at_30[0x10]; 10141 10142 u8 reserved_at_40[0xc]; 10143 u8 lane[0x4]; 10144 u8 reserved_at_50[0x8]; 10145 u8 error_type[0x8]; 10146 }; 10147 10148 struct mlx5_ifc_mpegc_reg_bits { 10149 u8 reserved_at_0[0x30]; 10150 u8 field_select[0x10]; 10151 10152 u8 tx_overflow_sense[0x1]; 10153 u8 mark_cqe[0x1]; 10154 u8 mark_cnp[0x1]; 10155 u8 reserved_at_43[0x1b]; 10156 u8 tx_lossy_overflow_oper[0x2]; 10157 10158 u8 reserved_at_60[0x100]; 10159 }; 10160 10161 struct mlx5_ifc_mpir_reg_bits { 10162 u8 sdm[0x1]; 10163 u8 reserved_at_1[0x1b]; 10164 u8 host_buses[0x4]; 10165 10166 u8 reserved_at_20[0x20]; 10167 10168 u8 local_port[0x8]; 10169 u8 reserved_at_28[0x18]; 10170 10171 u8 reserved_at_60[0x20]; 10172 }; 10173 10174 enum { 10175 MLX5_MTUTC_FREQ_ADJ_UNITS_PPB = 0x0, 10176 MLX5_MTUTC_FREQ_ADJ_UNITS_SCALED_PPM = 0x1, 10177 }; 10178 10179 enum { 10180 MLX5_MTUTC_OPERATION_SET_TIME_IMMEDIATE = 0x1, 10181 MLX5_MTUTC_OPERATION_ADJUST_TIME = 0x2, 10182 MLX5_MTUTC_OPERATION_ADJUST_FREQ_UTC = 0x3, 10183 }; 10184 10185 struct mlx5_ifc_mtutc_reg_bits { 10186 u8 reserved_at_0[0x5]; 10187 u8 freq_adj_units[0x3]; 10188 u8 reserved_at_8[0x3]; 10189 u8 log_max_freq_adjustment[0x5]; 10190 10191 u8 reserved_at_10[0xc]; 10192 u8 operation[0x4]; 10193 10194 u8 freq_adjustment[0x20]; 10195 10196 u8 reserved_at_40[0x40]; 10197 10198 u8 utc_sec[0x20]; 10199 10200 u8 reserved_at_a0[0x2]; 10201 u8 utc_nsec[0x1e]; 10202 10203 u8 time_adjustment[0x20]; 10204 }; 10205 10206 struct mlx5_ifc_pcam_enhanced_features_bits { 10207 u8 reserved_at_0[0x48]; 10208 u8 fec_100G_per_lane_in_pplm[0x1]; 10209 u8 reserved_at_49[0x1f]; 10210 u8 fec_50G_per_lane_in_pplm[0x1]; 10211 u8 reserved_at_69[0x4]; 10212 u8 rx_icrc_encapsulated_counter[0x1]; 10213 u8 reserved_at_6e[0x4]; 10214 u8 ptys_extended_ethernet[0x1]; 10215 u8 reserved_at_73[0x3]; 10216 u8 pfcc_mask[0x1]; 10217 u8 reserved_at_77[0x3]; 10218 u8 per_lane_error_counters[0x1]; 10219 u8 rx_buffer_fullness_counters[0x1]; 10220 u8 ptys_connector_type[0x1]; 10221 u8 reserved_at_7d[0x1]; 10222 u8 ppcnt_discard_group[0x1]; 10223 u8 ppcnt_statistical_group[0x1]; 10224 }; 10225 10226 struct mlx5_ifc_pcam_regs_5000_to_507f_bits { 10227 u8 port_access_reg_cap_mask_127_to_96[0x20]; 10228 u8 port_access_reg_cap_mask_95_to_64[0x20]; 10229 10230 u8 port_access_reg_cap_mask_63_to_36[0x1c]; 10231 u8 pplm[0x1]; 10232 u8 port_access_reg_cap_mask_34_to_32[0x3]; 10233 10234 u8 port_access_reg_cap_mask_31_to_13[0x13]; 10235 u8 pbmc[0x1]; 10236 u8 pptb[0x1]; 10237 u8 port_access_reg_cap_mask_10_to_09[0x2]; 10238 u8 ppcnt[0x1]; 10239 u8 port_access_reg_cap_mask_07_to_00[0x8]; 10240 }; 10241 10242 struct mlx5_ifc_pcam_reg_bits { 10243 u8 reserved_at_0[0x8]; 10244 u8 feature_group[0x8]; 10245 u8 reserved_at_10[0x8]; 10246 u8 access_reg_group[0x8]; 10247 10248 u8 reserved_at_20[0x20]; 10249 10250 union { 10251 struct mlx5_ifc_pcam_regs_5000_to_507f_bits regs_5000_to_507f; 10252 u8 reserved_at_0[0x80]; 10253 } port_access_reg_cap_mask; 10254 10255 u8 reserved_at_c0[0x80]; 10256 10257 union { 10258 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features; 10259 u8 reserved_at_0[0x80]; 10260 } feature_cap_mask; 10261 10262 u8 reserved_at_1c0[0xc0]; 10263 }; 10264 10265 struct mlx5_ifc_mcam_enhanced_features_bits { 10266 u8 reserved_at_0[0x50]; 10267 u8 mtutc_freq_adj_units[0x1]; 10268 u8 mtutc_time_adjustment_extended_range[0x1]; 10269 u8 reserved_at_52[0xb]; 10270 u8 mcia_32dwords[0x1]; 10271 u8 out_pulse_duration_ns[0x1]; 10272 u8 npps_period[0x1]; 10273 u8 reserved_at_60[0xa]; 10274 u8 reset_state[0x1]; 10275 u8 ptpcyc2realtime_modify[0x1]; 10276 u8 reserved_at_6c[0x2]; 10277 u8 pci_status_and_power[0x1]; 10278 u8 reserved_at_6f[0x5]; 10279 u8 mark_tx_action_cnp[0x1]; 10280 u8 mark_tx_action_cqe[0x1]; 10281 u8 dynamic_tx_overflow[0x1]; 10282 u8 reserved_at_77[0x4]; 10283 u8 pcie_outbound_stalled[0x1]; 10284 u8 tx_overflow_buffer_pkt[0x1]; 10285 u8 mtpps_enh_out_per_adj[0x1]; 10286 u8 mtpps_fs[0x1]; 10287 u8 pcie_performance_group[0x1]; 10288 }; 10289 10290 struct mlx5_ifc_mcam_access_reg_bits { 10291 u8 reserved_at_0[0x1c]; 10292 u8 mcda[0x1]; 10293 u8 mcc[0x1]; 10294 u8 mcqi[0x1]; 10295 u8 mcqs[0x1]; 10296 10297 u8 regs_95_to_90[0x6]; 10298 u8 mpir[0x1]; 10299 u8 regs_88_to_87[0x2]; 10300 u8 mpegc[0x1]; 10301 u8 mtutc[0x1]; 10302 u8 regs_84_to_68[0x11]; 10303 u8 tracer_registers[0x4]; 10304 10305 u8 regs_63_to_46[0x12]; 10306 u8 mrtc[0x1]; 10307 u8 regs_44_to_41[0x4]; 10308 u8 mfrl[0x1]; 10309 u8 regs_39_to_32[0x8]; 10310 10311 u8 regs_31_to_10[0x16]; 10312 u8 mtmp[0x1]; 10313 u8 regs_8_to_0[0x9]; 10314 }; 10315 10316 struct mlx5_ifc_mcam_access_reg_bits1 { 10317 u8 regs_127_to_96[0x20]; 10318 10319 u8 regs_95_to_64[0x20]; 10320 10321 u8 regs_63_to_32[0x20]; 10322 10323 u8 regs_31_to_0[0x20]; 10324 }; 10325 10326 struct mlx5_ifc_mcam_access_reg_bits2 { 10327 u8 regs_127_to_99[0x1d]; 10328 u8 mirc[0x1]; 10329 u8 regs_97_to_96[0x2]; 10330 10331 u8 regs_95_to_87[0x09]; 10332 u8 synce_registers[0x2]; 10333 u8 regs_84_to_64[0x15]; 10334 10335 u8 regs_63_to_32[0x20]; 10336 10337 u8 regs_31_to_0[0x20]; 10338 }; 10339 10340 struct mlx5_ifc_mcam_reg_bits { 10341 u8 reserved_at_0[0x8]; 10342 u8 feature_group[0x8]; 10343 u8 reserved_at_10[0x8]; 10344 u8 access_reg_group[0x8]; 10345 10346 u8 reserved_at_20[0x20]; 10347 10348 union { 10349 struct mlx5_ifc_mcam_access_reg_bits access_regs; 10350 struct mlx5_ifc_mcam_access_reg_bits1 access_regs1; 10351 struct mlx5_ifc_mcam_access_reg_bits2 access_regs2; 10352 u8 reserved_at_0[0x80]; 10353 } mng_access_reg_cap_mask; 10354 10355 u8 reserved_at_c0[0x80]; 10356 10357 union { 10358 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features; 10359 u8 reserved_at_0[0x80]; 10360 } mng_feature_cap_mask; 10361 10362 u8 reserved_at_1c0[0x80]; 10363 }; 10364 10365 struct mlx5_ifc_qcam_access_reg_cap_mask { 10366 u8 qcam_access_reg_cap_mask_127_to_20[0x6C]; 10367 u8 qpdpm[0x1]; 10368 u8 qcam_access_reg_cap_mask_18_to_4[0x0F]; 10369 u8 qdpm[0x1]; 10370 u8 qpts[0x1]; 10371 u8 qcap[0x1]; 10372 u8 qcam_access_reg_cap_mask_0[0x1]; 10373 }; 10374 10375 struct mlx5_ifc_qcam_qos_feature_cap_mask { 10376 u8 qcam_qos_feature_cap_mask_127_to_1[0x7F]; 10377 u8 qpts_trust_both[0x1]; 10378 }; 10379 10380 struct mlx5_ifc_qcam_reg_bits { 10381 u8 reserved_at_0[0x8]; 10382 u8 feature_group[0x8]; 10383 u8 reserved_at_10[0x8]; 10384 u8 access_reg_group[0x8]; 10385 u8 reserved_at_20[0x20]; 10386 10387 union { 10388 struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap; 10389 u8 reserved_at_0[0x80]; 10390 } qos_access_reg_cap_mask; 10391 10392 u8 reserved_at_c0[0x80]; 10393 10394 union { 10395 struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap; 10396 u8 reserved_at_0[0x80]; 10397 } qos_feature_cap_mask; 10398 10399 u8 reserved_at_1c0[0x80]; 10400 }; 10401 10402 struct mlx5_ifc_core_dump_reg_bits { 10403 u8 reserved_at_0[0x18]; 10404 u8 core_dump_type[0x8]; 10405 10406 u8 reserved_at_20[0x30]; 10407 u8 vhca_id[0x10]; 10408 10409 u8 reserved_at_60[0x8]; 10410 u8 qpn[0x18]; 10411 u8 reserved_at_80[0x180]; 10412 }; 10413 10414 struct mlx5_ifc_pcap_reg_bits { 10415 u8 reserved_at_0[0x8]; 10416 u8 local_port[0x8]; 10417 u8 reserved_at_10[0x10]; 10418 10419 u8 port_capability_mask[4][0x20]; 10420 }; 10421 10422 struct mlx5_ifc_paos_reg_bits { 10423 u8 swid[0x8]; 10424 u8 local_port[0x8]; 10425 u8 reserved_at_10[0x4]; 10426 u8 admin_status[0x4]; 10427 u8 reserved_at_18[0x4]; 10428 u8 oper_status[0x4]; 10429 10430 u8 ase[0x1]; 10431 u8 ee[0x1]; 10432 u8 reserved_at_22[0x1c]; 10433 u8 e[0x2]; 10434 10435 u8 reserved_at_40[0x40]; 10436 }; 10437 10438 struct mlx5_ifc_pamp_reg_bits { 10439 u8 reserved_at_0[0x8]; 10440 u8 opamp_group[0x8]; 10441 u8 reserved_at_10[0xc]; 10442 u8 opamp_group_type[0x4]; 10443 10444 u8 start_index[0x10]; 10445 u8 reserved_at_30[0x4]; 10446 u8 num_of_indices[0xc]; 10447 10448 u8 index_data[18][0x10]; 10449 }; 10450 10451 struct mlx5_ifc_pcmr_reg_bits { 10452 u8 reserved_at_0[0x8]; 10453 u8 local_port[0x8]; 10454 u8 reserved_at_10[0x10]; 10455 10456 u8 entropy_force_cap[0x1]; 10457 u8 entropy_calc_cap[0x1]; 10458 u8 entropy_gre_calc_cap[0x1]; 10459 u8 reserved_at_23[0xf]; 10460 u8 rx_ts_over_crc_cap[0x1]; 10461 u8 reserved_at_33[0xb]; 10462 u8 fcs_cap[0x1]; 10463 u8 reserved_at_3f[0x1]; 10464 10465 u8 entropy_force[0x1]; 10466 u8 entropy_calc[0x1]; 10467 u8 entropy_gre_calc[0x1]; 10468 u8 reserved_at_43[0xf]; 10469 u8 rx_ts_over_crc[0x1]; 10470 u8 reserved_at_53[0xb]; 10471 u8 fcs_chk[0x1]; 10472 u8 reserved_at_5f[0x1]; 10473 }; 10474 10475 struct mlx5_ifc_lane_2_module_mapping_bits { 10476 u8 reserved_at_0[0x4]; 10477 u8 rx_lane[0x4]; 10478 u8 reserved_at_8[0x4]; 10479 u8 tx_lane[0x4]; 10480 u8 reserved_at_10[0x8]; 10481 u8 module[0x8]; 10482 }; 10483 10484 struct mlx5_ifc_bufferx_reg_bits { 10485 u8 reserved_at_0[0x6]; 10486 u8 lossy[0x1]; 10487 u8 epsb[0x1]; 10488 u8 reserved_at_8[0x8]; 10489 u8 size[0x10]; 10490 10491 u8 xoff_threshold[0x10]; 10492 u8 xon_threshold[0x10]; 10493 }; 10494 10495 struct mlx5_ifc_set_node_in_bits { 10496 u8 node_description[64][0x8]; 10497 }; 10498 10499 struct mlx5_ifc_register_power_settings_bits { 10500 u8 reserved_at_0[0x18]; 10501 u8 power_settings_level[0x8]; 10502 10503 u8 reserved_at_20[0x60]; 10504 }; 10505 10506 struct mlx5_ifc_register_host_endianness_bits { 10507 u8 he[0x1]; 10508 u8 reserved_at_1[0x1f]; 10509 10510 u8 reserved_at_20[0x60]; 10511 }; 10512 10513 struct mlx5_ifc_umr_pointer_desc_argument_bits { 10514 u8 reserved_at_0[0x20]; 10515 10516 u8 mkey[0x20]; 10517 10518 u8 addressh_63_32[0x20]; 10519 10520 u8 addressl_31_0[0x20]; 10521 }; 10522 10523 struct mlx5_ifc_ud_adrs_vector_bits { 10524 u8 dc_key[0x40]; 10525 10526 u8 ext[0x1]; 10527 u8 reserved_at_41[0x7]; 10528 u8 destination_qp_dct[0x18]; 10529 10530 u8 static_rate[0x4]; 10531 u8 sl_eth_prio[0x4]; 10532 u8 fl[0x1]; 10533 u8 mlid[0x7]; 10534 u8 rlid_udp_sport[0x10]; 10535 10536 u8 reserved_at_80[0x20]; 10537 10538 u8 rmac_47_16[0x20]; 10539 10540 u8 rmac_15_0[0x10]; 10541 u8 tclass[0x8]; 10542 u8 hop_limit[0x8]; 10543 10544 u8 reserved_at_e0[0x1]; 10545 u8 grh[0x1]; 10546 u8 reserved_at_e2[0x2]; 10547 u8 src_addr_index[0x8]; 10548 u8 flow_label[0x14]; 10549 10550 u8 rgid_rip[16][0x8]; 10551 }; 10552 10553 struct mlx5_ifc_pages_req_event_bits { 10554 u8 reserved_at_0[0x10]; 10555 u8 function_id[0x10]; 10556 10557 u8 num_pages[0x20]; 10558 10559 u8 reserved_at_40[0xa0]; 10560 }; 10561 10562 struct mlx5_ifc_eqe_bits { 10563 u8 reserved_at_0[0x8]; 10564 u8 event_type[0x8]; 10565 u8 reserved_at_10[0x8]; 10566 u8 event_sub_type[0x8]; 10567 10568 u8 reserved_at_20[0xe0]; 10569 10570 union mlx5_ifc_event_auto_bits event_data; 10571 10572 u8 reserved_at_1e0[0x10]; 10573 u8 signature[0x8]; 10574 u8 reserved_at_1f8[0x7]; 10575 u8 owner[0x1]; 10576 }; 10577 10578 enum { 10579 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7, 10580 }; 10581 10582 struct mlx5_ifc_cmd_queue_entry_bits { 10583 u8 type[0x8]; 10584 u8 reserved_at_8[0x18]; 10585 10586 u8 input_length[0x20]; 10587 10588 u8 input_mailbox_pointer_63_32[0x20]; 10589 10590 u8 input_mailbox_pointer_31_9[0x17]; 10591 u8 reserved_at_77[0x9]; 10592 10593 u8 command_input_inline_data[16][0x8]; 10594 10595 u8 command_output_inline_data[16][0x8]; 10596 10597 u8 output_mailbox_pointer_63_32[0x20]; 10598 10599 u8 output_mailbox_pointer_31_9[0x17]; 10600 u8 reserved_at_1b7[0x9]; 10601 10602 u8 output_length[0x20]; 10603 10604 u8 token[0x8]; 10605 u8 signature[0x8]; 10606 u8 reserved_at_1f0[0x8]; 10607 u8 status[0x7]; 10608 u8 ownership[0x1]; 10609 }; 10610 10611 struct mlx5_ifc_cmd_out_bits { 10612 u8 status[0x8]; 10613 u8 reserved_at_8[0x18]; 10614 10615 u8 syndrome[0x20]; 10616 10617 u8 command_output[0x20]; 10618 }; 10619 10620 struct mlx5_ifc_cmd_in_bits { 10621 u8 opcode[0x10]; 10622 u8 reserved_at_10[0x10]; 10623 10624 u8 reserved_at_20[0x10]; 10625 u8 op_mod[0x10]; 10626 10627 u8 command[][0x20]; 10628 }; 10629 10630 struct mlx5_ifc_cmd_if_box_bits { 10631 u8 mailbox_data[512][0x8]; 10632 10633 u8 reserved_at_1000[0x180]; 10634 10635 u8 next_pointer_63_32[0x20]; 10636 10637 u8 next_pointer_31_10[0x16]; 10638 u8 reserved_at_11b6[0xa]; 10639 10640 u8 block_number[0x20]; 10641 10642 u8 reserved_at_11e0[0x8]; 10643 u8 token[0x8]; 10644 u8 ctrl_signature[0x8]; 10645 u8 signature[0x8]; 10646 }; 10647 10648 struct mlx5_ifc_mtt_bits { 10649 u8 ptag_63_32[0x20]; 10650 10651 u8 ptag_31_8[0x18]; 10652 u8 reserved_at_38[0x6]; 10653 u8 wr_en[0x1]; 10654 u8 rd_en[0x1]; 10655 }; 10656 10657 struct mlx5_ifc_query_wol_rol_out_bits { 10658 u8 status[0x8]; 10659 u8 reserved_at_8[0x18]; 10660 10661 u8 syndrome[0x20]; 10662 10663 u8 reserved_at_40[0x10]; 10664 u8 rol_mode[0x8]; 10665 u8 wol_mode[0x8]; 10666 10667 u8 reserved_at_60[0x20]; 10668 }; 10669 10670 struct mlx5_ifc_query_wol_rol_in_bits { 10671 u8 opcode[0x10]; 10672 u8 reserved_at_10[0x10]; 10673 10674 u8 reserved_at_20[0x10]; 10675 u8 op_mod[0x10]; 10676 10677 u8 reserved_at_40[0x40]; 10678 }; 10679 10680 struct mlx5_ifc_set_wol_rol_out_bits { 10681 u8 status[0x8]; 10682 u8 reserved_at_8[0x18]; 10683 10684 u8 syndrome[0x20]; 10685 10686 u8 reserved_at_40[0x40]; 10687 }; 10688 10689 struct mlx5_ifc_set_wol_rol_in_bits { 10690 u8 opcode[0x10]; 10691 u8 reserved_at_10[0x10]; 10692 10693 u8 reserved_at_20[0x10]; 10694 u8 op_mod[0x10]; 10695 10696 u8 rol_mode_valid[0x1]; 10697 u8 wol_mode_valid[0x1]; 10698 u8 reserved_at_42[0xe]; 10699 u8 rol_mode[0x8]; 10700 u8 wol_mode[0x8]; 10701 10702 u8 reserved_at_60[0x20]; 10703 }; 10704 10705 enum { 10706 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0, 10707 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1, 10708 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2, 10709 MLX5_INITIAL_SEG_NIC_INTERFACE_SW_RESET = 0x7, 10710 }; 10711 10712 enum { 10713 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0, 10714 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1, 10715 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2, 10716 }; 10717 10718 enum { 10719 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR = 0x1, 10720 MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC = 0x7, 10721 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR = 0x8, 10722 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR = 0x9, 10723 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR = 0xa, 10724 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR = 0xb, 10725 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN = 0xc, 10726 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR = 0xd, 10727 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV = 0xe, 10728 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR = 0xf, 10729 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR = 0x10, 10730 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PCI_POISONED_ERR = 0x12, 10731 }; 10732 10733 struct mlx5_ifc_initial_seg_bits { 10734 u8 fw_rev_minor[0x10]; 10735 u8 fw_rev_major[0x10]; 10736 10737 u8 cmd_interface_rev[0x10]; 10738 u8 fw_rev_subminor[0x10]; 10739 10740 u8 reserved_at_40[0x40]; 10741 10742 u8 cmdq_phy_addr_63_32[0x20]; 10743 10744 u8 cmdq_phy_addr_31_12[0x14]; 10745 u8 reserved_at_b4[0x2]; 10746 u8 nic_interface[0x2]; 10747 u8 log_cmdq_size[0x4]; 10748 u8 log_cmdq_stride[0x4]; 10749 10750 u8 command_doorbell_vector[0x20]; 10751 10752 u8 reserved_at_e0[0xf00]; 10753 10754 u8 initializing[0x1]; 10755 u8 reserved_at_fe1[0x4]; 10756 u8 nic_interface_supported[0x3]; 10757 u8 embedded_cpu[0x1]; 10758 u8 reserved_at_fe9[0x17]; 10759 10760 struct mlx5_ifc_health_buffer_bits health_buffer; 10761 10762 u8 no_dram_nic_offset[0x20]; 10763 10764 u8 reserved_at_1220[0x6e40]; 10765 10766 u8 reserved_at_8060[0x1f]; 10767 u8 clear_int[0x1]; 10768 10769 u8 health_syndrome[0x8]; 10770 u8 health_counter[0x18]; 10771 10772 u8 reserved_at_80a0[0x17fc0]; 10773 }; 10774 10775 struct mlx5_ifc_mtpps_reg_bits { 10776 u8 reserved_at_0[0xc]; 10777 u8 cap_number_of_pps_pins[0x4]; 10778 u8 reserved_at_10[0x4]; 10779 u8 cap_max_num_of_pps_in_pins[0x4]; 10780 u8 reserved_at_18[0x4]; 10781 u8 cap_max_num_of_pps_out_pins[0x4]; 10782 10783 u8 reserved_at_20[0x13]; 10784 u8 cap_log_min_npps_period[0x5]; 10785 u8 reserved_at_38[0x3]; 10786 u8 cap_log_min_out_pulse_duration_ns[0x5]; 10787 10788 u8 reserved_at_40[0x4]; 10789 u8 cap_pin_3_mode[0x4]; 10790 u8 reserved_at_48[0x4]; 10791 u8 cap_pin_2_mode[0x4]; 10792 u8 reserved_at_50[0x4]; 10793 u8 cap_pin_1_mode[0x4]; 10794 u8 reserved_at_58[0x4]; 10795 u8 cap_pin_0_mode[0x4]; 10796 10797 u8 reserved_at_60[0x4]; 10798 u8 cap_pin_7_mode[0x4]; 10799 u8 reserved_at_68[0x4]; 10800 u8 cap_pin_6_mode[0x4]; 10801 u8 reserved_at_70[0x4]; 10802 u8 cap_pin_5_mode[0x4]; 10803 u8 reserved_at_78[0x4]; 10804 u8 cap_pin_4_mode[0x4]; 10805 10806 u8 field_select[0x20]; 10807 u8 reserved_at_a0[0x20]; 10808 10809 u8 npps_period[0x40]; 10810 10811 u8 enable[0x1]; 10812 u8 reserved_at_101[0xb]; 10813 u8 pattern[0x4]; 10814 u8 reserved_at_110[0x4]; 10815 u8 pin_mode[0x4]; 10816 u8 pin[0x8]; 10817 10818 u8 reserved_at_120[0x2]; 10819 u8 out_pulse_duration_ns[0x1e]; 10820 10821 u8 time_stamp[0x40]; 10822 10823 u8 out_pulse_duration[0x10]; 10824 u8 out_periodic_adjustment[0x10]; 10825 u8 enhanced_out_periodic_adjustment[0x20]; 10826 10827 u8 reserved_at_1c0[0x20]; 10828 }; 10829 10830 struct mlx5_ifc_mtppse_reg_bits { 10831 u8 reserved_at_0[0x18]; 10832 u8 pin[0x8]; 10833 u8 event_arm[0x1]; 10834 u8 reserved_at_21[0x1b]; 10835 u8 event_generation_mode[0x4]; 10836 u8 reserved_at_40[0x40]; 10837 }; 10838 10839 struct mlx5_ifc_mcqs_reg_bits { 10840 u8 last_index_flag[0x1]; 10841 u8 reserved_at_1[0x7]; 10842 u8 fw_device[0x8]; 10843 u8 component_index[0x10]; 10844 10845 u8 reserved_at_20[0x10]; 10846 u8 identifier[0x10]; 10847 10848 u8 reserved_at_40[0x17]; 10849 u8 component_status[0x5]; 10850 u8 component_update_state[0x4]; 10851 10852 u8 last_update_state_changer_type[0x4]; 10853 u8 last_update_state_changer_host_id[0x4]; 10854 u8 reserved_at_68[0x18]; 10855 }; 10856 10857 struct mlx5_ifc_mcqi_cap_bits { 10858 u8 supported_info_bitmask[0x20]; 10859 10860 u8 component_size[0x20]; 10861 10862 u8 max_component_size[0x20]; 10863 10864 u8 log_mcda_word_size[0x4]; 10865 u8 reserved_at_64[0xc]; 10866 u8 mcda_max_write_size[0x10]; 10867 10868 u8 rd_en[0x1]; 10869 u8 reserved_at_81[0x1]; 10870 u8 match_chip_id[0x1]; 10871 u8 match_psid[0x1]; 10872 u8 check_user_timestamp[0x1]; 10873 u8 match_base_guid_mac[0x1]; 10874 u8 reserved_at_86[0x1a]; 10875 }; 10876 10877 struct mlx5_ifc_mcqi_version_bits { 10878 u8 reserved_at_0[0x2]; 10879 u8 build_time_valid[0x1]; 10880 u8 user_defined_time_valid[0x1]; 10881 u8 reserved_at_4[0x14]; 10882 u8 version_string_length[0x8]; 10883 10884 u8 version[0x20]; 10885 10886 u8 build_time[0x40]; 10887 10888 u8 user_defined_time[0x40]; 10889 10890 u8 build_tool_version[0x20]; 10891 10892 u8 reserved_at_e0[0x20]; 10893 10894 u8 version_string[92][0x8]; 10895 }; 10896 10897 struct mlx5_ifc_mcqi_activation_method_bits { 10898 u8 pending_server_ac_power_cycle[0x1]; 10899 u8 pending_server_dc_power_cycle[0x1]; 10900 u8 pending_server_reboot[0x1]; 10901 u8 pending_fw_reset[0x1]; 10902 u8 auto_activate[0x1]; 10903 u8 all_hosts_sync[0x1]; 10904 u8 device_hw_reset[0x1]; 10905 u8 reserved_at_7[0x19]; 10906 }; 10907 10908 union mlx5_ifc_mcqi_reg_data_bits { 10909 struct mlx5_ifc_mcqi_cap_bits mcqi_caps; 10910 struct mlx5_ifc_mcqi_version_bits mcqi_version; 10911 struct mlx5_ifc_mcqi_activation_method_bits mcqi_activation_mathod; 10912 }; 10913 10914 struct mlx5_ifc_mcqi_reg_bits { 10915 u8 read_pending_component[0x1]; 10916 u8 reserved_at_1[0xf]; 10917 u8 component_index[0x10]; 10918 10919 u8 reserved_at_20[0x20]; 10920 10921 u8 reserved_at_40[0x1b]; 10922 u8 info_type[0x5]; 10923 10924 u8 info_size[0x20]; 10925 10926 u8 offset[0x20]; 10927 10928 u8 reserved_at_a0[0x10]; 10929 u8 data_size[0x10]; 10930 10931 union mlx5_ifc_mcqi_reg_data_bits data[]; 10932 }; 10933 10934 struct mlx5_ifc_mcc_reg_bits { 10935 u8 reserved_at_0[0x4]; 10936 u8 time_elapsed_since_last_cmd[0xc]; 10937 u8 reserved_at_10[0x8]; 10938 u8 instruction[0x8]; 10939 10940 u8 reserved_at_20[0x10]; 10941 u8 component_index[0x10]; 10942 10943 u8 reserved_at_40[0x8]; 10944 u8 update_handle[0x18]; 10945 10946 u8 handle_owner_type[0x4]; 10947 u8 handle_owner_host_id[0x4]; 10948 u8 reserved_at_68[0x1]; 10949 u8 control_progress[0x7]; 10950 u8 error_code[0x8]; 10951 u8 reserved_at_78[0x4]; 10952 u8 control_state[0x4]; 10953 10954 u8 component_size[0x20]; 10955 10956 u8 reserved_at_a0[0x60]; 10957 }; 10958 10959 struct mlx5_ifc_mcda_reg_bits { 10960 u8 reserved_at_0[0x8]; 10961 u8 update_handle[0x18]; 10962 10963 u8 offset[0x20]; 10964 10965 u8 reserved_at_40[0x10]; 10966 u8 size[0x10]; 10967 10968 u8 reserved_at_60[0x20]; 10969 10970 u8 data[][0x20]; 10971 }; 10972 10973 enum { 10974 MLX5_MFRL_REG_RESET_STATE_IDLE = 0, 10975 MLX5_MFRL_REG_RESET_STATE_IN_NEGOTIATION = 1, 10976 MLX5_MFRL_REG_RESET_STATE_RESET_IN_PROGRESS = 2, 10977 MLX5_MFRL_REG_RESET_STATE_NEG_TIMEOUT = 3, 10978 MLX5_MFRL_REG_RESET_STATE_NACK = 4, 10979 MLX5_MFRL_REG_RESET_STATE_UNLOAD_TIMEOUT = 5, 10980 }; 10981 10982 enum { 10983 MLX5_MFRL_REG_RESET_TYPE_FULL_CHIP = BIT(0), 10984 MLX5_MFRL_REG_RESET_TYPE_NET_PORT_ALIVE = BIT(1), 10985 }; 10986 10987 enum { 10988 MLX5_MFRL_REG_RESET_LEVEL0 = BIT(0), 10989 MLX5_MFRL_REG_RESET_LEVEL3 = BIT(3), 10990 MLX5_MFRL_REG_RESET_LEVEL6 = BIT(6), 10991 }; 10992 10993 struct mlx5_ifc_mfrl_reg_bits { 10994 u8 reserved_at_0[0x20]; 10995 10996 u8 reserved_at_20[0x2]; 10997 u8 pci_sync_for_fw_update_start[0x1]; 10998 u8 pci_sync_for_fw_update_resp[0x2]; 10999 u8 rst_type_sel[0x3]; 11000 u8 reserved_at_28[0x4]; 11001 u8 reset_state[0x4]; 11002 u8 reset_type[0x8]; 11003 u8 reset_level[0x8]; 11004 }; 11005 11006 struct mlx5_ifc_mirc_reg_bits { 11007 u8 reserved_at_0[0x18]; 11008 u8 status_code[0x8]; 11009 11010 u8 reserved_at_20[0x20]; 11011 }; 11012 11013 struct mlx5_ifc_pddr_monitor_opcode_bits { 11014 u8 reserved_at_0[0x10]; 11015 u8 monitor_opcode[0x10]; 11016 }; 11017 11018 union mlx5_ifc_pddr_troubleshooting_page_status_opcode_auto_bits { 11019 struct mlx5_ifc_pddr_monitor_opcode_bits pddr_monitor_opcode; 11020 u8 reserved_at_0[0x20]; 11021 }; 11022 11023 enum { 11024 /* Monitor opcodes */ 11025 MLX5_PDDR_REG_TRBLSH_GROUP_OPCODE_MONITOR = 0x0, 11026 }; 11027 11028 struct mlx5_ifc_pddr_troubleshooting_page_bits { 11029 u8 reserved_at_0[0x10]; 11030 u8 group_opcode[0x10]; 11031 11032 union mlx5_ifc_pddr_troubleshooting_page_status_opcode_auto_bits status_opcode; 11033 11034 u8 reserved_at_40[0x20]; 11035 11036 u8 status_message[59][0x20]; 11037 }; 11038 11039 union mlx5_ifc_pddr_reg_page_data_auto_bits { 11040 struct mlx5_ifc_pddr_troubleshooting_page_bits pddr_troubleshooting_page; 11041 u8 reserved_at_0[0x7c0]; 11042 }; 11043 11044 enum { 11045 MLX5_PDDR_REG_PAGE_SELECT_TROUBLESHOOTING_INFO_PAGE = 0x1, 11046 }; 11047 11048 struct mlx5_ifc_pddr_reg_bits { 11049 u8 reserved_at_0[0x8]; 11050 u8 local_port[0x8]; 11051 u8 pnat[0x2]; 11052 u8 reserved_at_12[0xe]; 11053 11054 u8 reserved_at_20[0x18]; 11055 u8 page_select[0x8]; 11056 11057 union mlx5_ifc_pddr_reg_page_data_auto_bits page_data; 11058 }; 11059 11060 struct mlx5_ifc_mrtc_reg_bits { 11061 u8 time_synced[0x1]; 11062 u8 reserved_at_1[0x1f]; 11063 11064 u8 reserved_at_20[0x20]; 11065 11066 u8 time_h[0x20]; 11067 11068 u8 time_l[0x20]; 11069 }; 11070 11071 struct mlx5_ifc_mtcap_reg_bits { 11072 u8 reserved_at_0[0x19]; 11073 u8 sensor_count[0x7]; 11074 11075 u8 reserved_at_20[0x20]; 11076 11077 u8 sensor_map[0x40]; 11078 }; 11079 11080 struct mlx5_ifc_mtmp_reg_bits { 11081 u8 reserved_at_0[0x14]; 11082 u8 sensor_index[0xc]; 11083 11084 u8 reserved_at_20[0x10]; 11085 u8 temperature[0x10]; 11086 11087 u8 mte[0x1]; 11088 u8 mtr[0x1]; 11089 u8 reserved_at_42[0xe]; 11090 u8 max_temperature[0x10]; 11091 11092 u8 tee[0x2]; 11093 u8 reserved_at_62[0xe]; 11094 u8 temp_threshold_hi[0x10]; 11095 11096 u8 reserved_at_80[0x10]; 11097 u8 temp_threshold_lo[0x10]; 11098 11099 u8 reserved_at_a0[0x20]; 11100 11101 u8 sensor_name_hi[0x20]; 11102 u8 sensor_name_lo[0x20]; 11103 }; 11104 11105 union mlx5_ifc_ports_control_registers_document_bits { 11106 struct mlx5_ifc_bufferx_reg_bits bufferx_reg; 11107 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 11108 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 11109 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 11110 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 11111 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 11112 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 11113 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout; 11114 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout; 11115 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping; 11116 struct mlx5_ifc_pamp_reg_bits pamp_reg; 11117 struct mlx5_ifc_paos_reg_bits paos_reg; 11118 struct mlx5_ifc_pcap_reg_bits pcap_reg; 11119 struct mlx5_ifc_pddr_monitor_opcode_bits pddr_monitor_opcode; 11120 struct mlx5_ifc_pddr_reg_bits pddr_reg; 11121 struct mlx5_ifc_pddr_troubleshooting_page_bits pddr_troubleshooting_page; 11122 struct mlx5_ifc_peir_reg_bits peir_reg; 11123 struct mlx5_ifc_pelc_reg_bits pelc_reg; 11124 struct mlx5_ifc_pfcc_reg_bits pfcc_reg; 11125 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 11126 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 11127 struct mlx5_ifc_pifr_reg_bits pifr_reg; 11128 struct mlx5_ifc_pipg_reg_bits pipg_reg; 11129 struct mlx5_ifc_plbf_reg_bits plbf_reg; 11130 struct mlx5_ifc_plib_reg_bits plib_reg; 11131 struct mlx5_ifc_plpc_reg_bits plpc_reg; 11132 struct mlx5_ifc_pmaos_reg_bits pmaos_reg; 11133 struct mlx5_ifc_pmlp_reg_bits pmlp_reg; 11134 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg; 11135 struct mlx5_ifc_pmpc_reg_bits pmpc_reg; 11136 struct mlx5_ifc_pmpe_reg_bits pmpe_reg; 11137 struct mlx5_ifc_pmpr_reg_bits pmpr_reg; 11138 struct mlx5_ifc_pmtu_reg_bits pmtu_reg; 11139 struct mlx5_ifc_ppad_reg_bits ppad_reg; 11140 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg; 11141 struct mlx5_ifc_mpein_reg_bits mpein_reg; 11142 struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg; 11143 struct mlx5_ifc_pplm_reg_bits pplm_reg; 11144 struct mlx5_ifc_pplr_reg_bits pplr_reg; 11145 struct mlx5_ifc_ppsc_reg_bits ppsc_reg; 11146 struct mlx5_ifc_pqdr_reg_bits pqdr_reg; 11147 struct mlx5_ifc_pspa_reg_bits pspa_reg; 11148 struct mlx5_ifc_ptas_reg_bits ptas_reg; 11149 struct mlx5_ifc_ptys_reg_bits ptys_reg; 11150 struct mlx5_ifc_mlcr_reg_bits mlcr_reg; 11151 struct mlx5_ifc_pude_reg_bits pude_reg; 11152 struct mlx5_ifc_pvlc_reg_bits pvlc_reg; 11153 struct mlx5_ifc_slrg_reg_bits slrg_reg; 11154 struct mlx5_ifc_sltp_reg_bits sltp_reg; 11155 struct mlx5_ifc_mtpps_reg_bits mtpps_reg; 11156 struct mlx5_ifc_mtppse_reg_bits mtppse_reg; 11157 struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg; 11158 struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits; 11159 struct mlx5_ifc_fpga_cap_bits fpga_cap_bits; 11160 struct mlx5_ifc_mcqi_reg_bits mcqi_reg; 11161 struct mlx5_ifc_mcc_reg_bits mcc_reg; 11162 struct mlx5_ifc_mcda_reg_bits mcda_reg; 11163 struct mlx5_ifc_mirc_reg_bits mirc_reg; 11164 struct mlx5_ifc_mfrl_reg_bits mfrl_reg; 11165 struct mlx5_ifc_mtutc_reg_bits mtutc_reg; 11166 struct mlx5_ifc_mrtc_reg_bits mrtc_reg; 11167 struct mlx5_ifc_mtcap_reg_bits mtcap_reg; 11168 struct mlx5_ifc_mtmp_reg_bits mtmp_reg; 11169 u8 reserved_at_0[0x60e0]; 11170 }; 11171 11172 union mlx5_ifc_debug_enhancements_document_bits { 11173 struct mlx5_ifc_health_buffer_bits health_buffer; 11174 u8 reserved_at_0[0x200]; 11175 }; 11176 11177 union mlx5_ifc_uplink_pci_interface_document_bits { 11178 struct mlx5_ifc_initial_seg_bits initial_seg; 11179 u8 reserved_at_0[0x20060]; 11180 }; 11181 11182 struct mlx5_ifc_set_flow_table_root_out_bits { 11183 u8 status[0x8]; 11184 u8 reserved_at_8[0x18]; 11185 11186 u8 syndrome[0x20]; 11187 11188 u8 reserved_at_40[0x40]; 11189 }; 11190 11191 struct mlx5_ifc_set_flow_table_root_in_bits { 11192 u8 opcode[0x10]; 11193 u8 reserved_at_10[0x10]; 11194 11195 u8 reserved_at_20[0x10]; 11196 u8 op_mod[0x10]; 11197 11198 u8 other_vport[0x1]; 11199 u8 reserved_at_41[0xf]; 11200 u8 vport_number[0x10]; 11201 11202 u8 reserved_at_60[0x20]; 11203 11204 u8 table_type[0x8]; 11205 u8 reserved_at_88[0x7]; 11206 u8 table_of_other_vport[0x1]; 11207 u8 table_vport_number[0x10]; 11208 11209 u8 reserved_at_a0[0x8]; 11210 u8 table_id[0x18]; 11211 11212 u8 reserved_at_c0[0x8]; 11213 u8 underlay_qpn[0x18]; 11214 u8 table_eswitch_owner_vhca_id_valid[0x1]; 11215 u8 reserved_at_e1[0xf]; 11216 u8 table_eswitch_owner_vhca_id[0x10]; 11217 u8 reserved_at_100[0x100]; 11218 }; 11219 11220 enum { 11221 MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = (1UL << 0), 11222 MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15), 11223 }; 11224 11225 struct mlx5_ifc_modify_flow_table_out_bits { 11226 u8 status[0x8]; 11227 u8 reserved_at_8[0x18]; 11228 11229 u8 syndrome[0x20]; 11230 11231 u8 reserved_at_40[0x40]; 11232 }; 11233 11234 struct mlx5_ifc_modify_flow_table_in_bits { 11235 u8 opcode[0x10]; 11236 u8 reserved_at_10[0x10]; 11237 11238 u8 reserved_at_20[0x10]; 11239 u8 op_mod[0x10]; 11240 11241 u8 other_vport[0x1]; 11242 u8 reserved_at_41[0xf]; 11243 u8 vport_number[0x10]; 11244 11245 u8 reserved_at_60[0x10]; 11246 u8 modify_field_select[0x10]; 11247 11248 u8 table_type[0x8]; 11249 u8 reserved_at_88[0x18]; 11250 11251 u8 reserved_at_a0[0x8]; 11252 u8 table_id[0x18]; 11253 11254 struct mlx5_ifc_flow_table_context_bits flow_table_context; 11255 }; 11256 11257 struct mlx5_ifc_ets_tcn_config_reg_bits { 11258 u8 g[0x1]; 11259 u8 b[0x1]; 11260 u8 r[0x1]; 11261 u8 reserved_at_3[0x9]; 11262 u8 group[0x4]; 11263 u8 reserved_at_10[0x9]; 11264 u8 bw_allocation[0x7]; 11265 11266 u8 reserved_at_20[0xc]; 11267 u8 max_bw_units[0x4]; 11268 u8 reserved_at_30[0x8]; 11269 u8 max_bw_value[0x8]; 11270 }; 11271 11272 struct mlx5_ifc_ets_global_config_reg_bits { 11273 u8 reserved_at_0[0x2]; 11274 u8 r[0x1]; 11275 u8 reserved_at_3[0x1d]; 11276 11277 u8 reserved_at_20[0xc]; 11278 u8 max_bw_units[0x4]; 11279 u8 reserved_at_30[0x8]; 11280 u8 max_bw_value[0x8]; 11281 }; 11282 11283 struct mlx5_ifc_qetc_reg_bits { 11284 u8 reserved_at_0[0x8]; 11285 u8 port_number[0x8]; 11286 u8 reserved_at_10[0x30]; 11287 11288 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8]; 11289 struct mlx5_ifc_ets_global_config_reg_bits global_configuration; 11290 }; 11291 11292 struct mlx5_ifc_qpdpm_dscp_reg_bits { 11293 u8 e[0x1]; 11294 u8 reserved_at_01[0x0b]; 11295 u8 prio[0x04]; 11296 }; 11297 11298 struct mlx5_ifc_qpdpm_reg_bits { 11299 u8 reserved_at_0[0x8]; 11300 u8 local_port[0x8]; 11301 u8 reserved_at_10[0x10]; 11302 struct mlx5_ifc_qpdpm_dscp_reg_bits dscp[64]; 11303 }; 11304 11305 struct mlx5_ifc_qpts_reg_bits { 11306 u8 reserved_at_0[0x8]; 11307 u8 local_port[0x8]; 11308 u8 reserved_at_10[0x2d]; 11309 u8 trust_state[0x3]; 11310 }; 11311 11312 struct mlx5_ifc_pptb_reg_bits { 11313 u8 reserved_at_0[0x2]; 11314 u8 mm[0x2]; 11315 u8 reserved_at_4[0x4]; 11316 u8 local_port[0x8]; 11317 u8 reserved_at_10[0x6]; 11318 u8 cm[0x1]; 11319 u8 um[0x1]; 11320 u8 pm[0x8]; 11321 11322 u8 prio_x_buff[0x20]; 11323 11324 u8 pm_msb[0x8]; 11325 u8 reserved_at_48[0x10]; 11326 u8 ctrl_buff[0x4]; 11327 u8 untagged_buff[0x4]; 11328 }; 11329 11330 struct mlx5_ifc_sbcam_reg_bits { 11331 u8 reserved_at_0[0x8]; 11332 u8 feature_group[0x8]; 11333 u8 reserved_at_10[0x8]; 11334 u8 access_reg_group[0x8]; 11335 11336 u8 reserved_at_20[0x20]; 11337 11338 u8 sb_access_reg_cap_mask[4][0x20]; 11339 11340 u8 reserved_at_c0[0x80]; 11341 11342 u8 sb_feature_cap_mask[4][0x20]; 11343 11344 u8 reserved_at_1c0[0x40]; 11345 11346 u8 cap_total_buffer_size[0x20]; 11347 11348 u8 cap_cell_size[0x10]; 11349 u8 cap_max_pg_buffers[0x8]; 11350 u8 cap_num_pool_supported[0x8]; 11351 11352 u8 reserved_at_240[0x8]; 11353 u8 cap_sbsr_stat_size[0x8]; 11354 u8 cap_max_tclass_data[0x8]; 11355 u8 cap_max_cpu_ingress_tclass_sb[0x8]; 11356 }; 11357 11358 struct mlx5_ifc_pbmc_reg_bits { 11359 u8 reserved_at_0[0x8]; 11360 u8 local_port[0x8]; 11361 u8 reserved_at_10[0x10]; 11362 11363 u8 xoff_timer_value[0x10]; 11364 u8 xoff_refresh[0x10]; 11365 11366 u8 reserved_at_40[0x9]; 11367 u8 fullness_threshold[0x7]; 11368 u8 port_buffer_size[0x10]; 11369 11370 struct mlx5_ifc_bufferx_reg_bits buffer[10]; 11371 11372 u8 reserved_at_2e0[0x80]; 11373 }; 11374 11375 struct mlx5_ifc_sbpr_reg_bits { 11376 u8 desc[0x1]; 11377 u8 snap[0x1]; 11378 u8 reserved_at_2[0x4]; 11379 u8 dir[0x2]; 11380 u8 reserved_at_8[0x14]; 11381 u8 pool[0x4]; 11382 11383 u8 infi_size[0x1]; 11384 u8 reserved_at_21[0x7]; 11385 u8 size[0x18]; 11386 11387 u8 reserved_at_40[0x1c]; 11388 u8 mode[0x4]; 11389 11390 u8 reserved_at_60[0x8]; 11391 u8 buff_occupancy[0x18]; 11392 11393 u8 clr[0x1]; 11394 u8 reserved_at_81[0x7]; 11395 u8 max_buff_occupancy[0x18]; 11396 11397 u8 reserved_at_a0[0x8]; 11398 u8 ext_buff_occupancy[0x18]; 11399 }; 11400 11401 struct mlx5_ifc_sbcm_reg_bits { 11402 u8 desc[0x1]; 11403 u8 snap[0x1]; 11404 u8 reserved_at_2[0x6]; 11405 u8 local_port[0x8]; 11406 u8 pnat[0x2]; 11407 u8 pg_buff[0x6]; 11408 u8 reserved_at_18[0x6]; 11409 u8 dir[0x2]; 11410 11411 u8 reserved_at_20[0x1f]; 11412 u8 exc[0x1]; 11413 11414 u8 reserved_at_40[0x40]; 11415 11416 u8 reserved_at_80[0x8]; 11417 u8 buff_occupancy[0x18]; 11418 11419 u8 clr[0x1]; 11420 u8 reserved_at_a1[0x7]; 11421 u8 max_buff_occupancy[0x18]; 11422 11423 u8 reserved_at_c0[0x8]; 11424 u8 min_buff[0x18]; 11425 11426 u8 infi_max[0x1]; 11427 u8 reserved_at_e1[0x7]; 11428 u8 max_buff[0x18]; 11429 11430 u8 reserved_at_100[0x20]; 11431 11432 u8 reserved_at_120[0x1c]; 11433 u8 pool[0x4]; 11434 }; 11435 11436 struct mlx5_ifc_qtct_reg_bits { 11437 u8 reserved_at_0[0x8]; 11438 u8 port_number[0x8]; 11439 u8 reserved_at_10[0xd]; 11440 u8 prio[0x3]; 11441 11442 u8 reserved_at_20[0x1d]; 11443 u8 tclass[0x3]; 11444 }; 11445 11446 struct mlx5_ifc_mcia_reg_bits { 11447 u8 l[0x1]; 11448 u8 reserved_at_1[0x7]; 11449 u8 module[0x8]; 11450 u8 reserved_at_10[0x8]; 11451 u8 status[0x8]; 11452 11453 u8 i2c_device_address[0x8]; 11454 u8 page_number[0x8]; 11455 u8 device_address[0x10]; 11456 11457 u8 reserved_at_40[0x10]; 11458 u8 size[0x10]; 11459 11460 u8 reserved_at_60[0x20]; 11461 11462 u8 dword_0[0x20]; 11463 u8 dword_1[0x20]; 11464 u8 dword_2[0x20]; 11465 u8 dword_3[0x20]; 11466 u8 dword_4[0x20]; 11467 u8 dword_5[0x20]; 11468 u8 dword_6[0x20]; 11469 u8 dword_7[0x20]; 11470 u8 dword_8[0x20]; 11471 u8 dword_9[0x20]; 11472 u8 dword_10[0x20]; 11473 u8 dword_11[0x20]; 11474 }; 11475 11476 struct mlx5_ifc_dcbx_param_bits { 11477 u8 dcbx_cee_cap[0x1]; 11478 u8 dcbx_ieee_cap[0x1]; 11479 u8 dcbx_standby_cap[0x1]; 11480 u8 reserved_at_3[0x5]; 11481 u8 port_number[0x8]; 11482 u8 reserved_at_10[0xa]; 11483 u8 max_application_table_size[6]; 11484 u8 reserved_at_20[0x15]; 11485 u8 version_oper[0x3]; 11486 u8 reserved_at_38[5]; 11487 u8 version_admin[0x3]; 11488 u8 willing_admin[0x1]; 11489 u8 reserved_at_41[0x3]; 11490 u8 pfc_cap_oper[0x4]; 11491 u8 reserved_at_48[0x4]; 11492 u8 pfc_cap_admin[0x4]; 11493 u8 reserved_at_50[0x4]; 11494 u8 num_of_tc_oper[0x4]; 11495 u8 reserved_at_58[0x4]; 11496 u8 num_of_tc_admin[0x4]; 11497 u8 remote_willing[0x1]; 11498 u8 reserved_at_61[3]; 11499 u8 remote_pfc_cap[4]; 11500 u8 reserved_at_68[0x14]; 11501 u8 remote_num_of_tc[0x4]; 11502 u8 reserved_at_80[0x18]; 11503 u8 error[0x8]; 11504 u8 reserved_at_a0[0x160]; 11505 }; 11506 11507 enum { 11508 MLX5_LAG_PORT_SELECT_MODE_QUEUE_AFFINITY = 0, 11509 MLX5_LAG_PORT_SELECT_MODE_PORT_SELECT_FT = 1, 11510 MLX5_LAG_PORT_SELECT_MODE_PORT_SELECT_MPESW = 2, 11511 }; 11512 11513 struct mlx5_ifc_lagc_bits { 11514 u8 fdb_selection_mode[0x1]; 11515 u8 reserved_at_1[0x14]; 11516 u8 port_select_mode[0x3]; 11517 u8 reserved_at_18[0x5]; 11518 u8 lag_state[0x3]; 11519 11520 u8 reserved_at_20[0xc]; 11521 u8 active_port[0x4]; 11522 u8 reserved_at_30[0x4]; 11523 u8 tx_remap_affinity_2[0x4]; 11524 u8 reserved_at_38[0x4]; 11525 u8 tx_remap_affinity_1[0x4]; 11526 }; 11527 11528 struct mlx5_ifc_create_lag_out_bits { 11529 u8 status[0x8]; 11530 u8 reserved_at_8[0x18]; 11531 11532 u8 syndrome[0x20]; 11533 11534 u8 reserved_at_40[0x40]; 11535 }; 11536 11537 struct mlx5_ifc_create_lag_in_bits { 11538 u8 opcode[0x10]; 11539 u8 reserved_at_10[0x10]; 11540 11541 u8 reserved_at_20[0x10]; 11542 u8 op_mod[0x10]; 11543 11544 struct mlx5_ifc_lagc_bits ctx; 11545 }; 11546 11547 struct mlx5_ifc_modify_lag_out_bits { 11548 u8 status[0x8]; 11549 u8 reserved_at_8[0x18]; 11550 11551 u8 syndrome[0x20]; 11552 11553 u8 reserved_at_40[0x40]; 11554 }; 11555 11556 struct mlx5_ifc_modify_lag_in_bits { 11557 u8 opcode[0x10]; 11558 u8 reserved_at_10[0x10]; 11559 11560 u8 reserved_at_20[0x10]; 11561 u8 op_mod[0x10]; 11562 11563 u8 reserved_at_40[0x20]; 11564 u8 field_select[0x20]; 11565 11566 struct mlx5_ifc_lagc_bits ctx; 11567 }; 11568 11569 struct mlx5_ifc_query_lag_out_bits { 11570 u8 status[0x8]; 11571 u8 reserved_at_8[0x18]; 11572 11573 u8 syndrome[0x20]; 11574 11575 struct mlx5_ifc_lagc_bits ctx; 11576 }; 11577 11578 struct mlx5_ifc_query_lag_in_bits { 11579 u8 opcode[0x10]; 11580 u8 reserved_at_10[0x10]; 11581 11582 u8 reserved_at_20[0x10]; 11583 u8 op_mod[0x10]; 11584 11585 u8 reserved_at_40[0x40]; 11586 }; 11587 11588 struct mlx5_ifc_destroy_lag_out_bits { 11589 u8 status[0x8]; 11590 u8 reserved_at_8[0x18]; 11591 11592 u8 syndrome[0x20]; 11593 11594 u8 reserved_at_40[0x40]; 11595 }; 11596 11597 struct mlx5_ifc_destroy_lag_in_bits { 11598 u8 opcode[0x10]; 11599 u8 reserved_at_10[0x10]; 11600 11601 u8 reserved_at_20[0x10]; 11602 u8 op_mod[0x10]; 11603 11604 u8 reserved_at_40[0x40]; 11605 }; 11606 11607 struct mlx5_ifc_create_vport_lag_out_bits { 11608 u8 status[0x8]; 11609 u8 reserved_at_8[0x18]; 11610 11611 u8 syndrome[0x20]; 11612 11613 u8 reserved_at_40[0x40]; 11614 }; 11615 11616 struct mlx5_ifc_create_vport_lag_in_bits { 11617 u8 opcode[0x10]; 11618 u8 reserved_at_10[0x10]; 11619 11620 u8 reserved_at_20[0x10]; 11621 u8 op_mod[0x10]; 11622 11623 u8 reserved_at_40[0x40]; 11624 }; 11625 11626 struct mlx5_ifc_destroy_vport_lag_out_bits { 11627 u8 status[0x8]; 11628 u8 reserved_at_8[0x18]; 11629 11630 u8 syndrome[0x20]; 11631 11632 u8 reserved_at_40[0x40]; 11633 }; 11634 11635 struct mlx5_ifc_destroy_vport_lag_in_bits { 11636 u8 opcode[0x10]; 11637 u8 reserved_at_10[0x10]; 11638 11639 u8 reserved_at_20[0x10]; 11640 u8 op_mod[0x10]; 11641 11642 u8 reserved_at_40[0x40]; 11643 }; 11644 11645 enum { 11646 MLX5_MODIFY_MEMIC_OP_MOD_ALLOC, 11647 MLX5_MODIFY_MEMIC_OP_MOD_DEALLOC, 11648 }; 11649 11650 struct mlx5_ifc_modify_memic_in_bits { 11651 u8 opcode[0x10]; 11652 u8 uid[0x10]; 11653 11654 u8 reserved_at_20[0x10]; 11655 u8 op_mod[0x10]; 11656 11657 u8 reserved_at_40[0x20]; 11658 11659 u8 reserved_at_60[0x18]; 11660 u8 memic_operation_type[0x8]; 11661 11662 u8 memic_start_addr[0x40]; 11663 11664 u8 reserved_at_c0[0x140]; 11665 }; 11666 11667 struct mlx5_ifc_modify_memic_out_bits { 11668 u8 status[0x8]; 11669 u8 reserved_at_8[0x18]; 11670 11671 u8 syndrome[0x20]; 11672 11673 u8 reserved_at_40[0x40]; 11674 11675 u8 memic_operation_addr[0x40]; 11676 11677 u8 reserved_at_c0[0x140]; 11678 }; 11679 11680 struct mlx5_ifc_alloc_memic_in_bits { 11681 u8 opcode[0x10]; 11682 u8 reserved_at_10[0x10]; 11683 11684 u8 reserved_at_20[0x10]; 11685 u8 op_mod[0x10]; 11686 11687 u8 reserved_at_30[0x20]; 11688 11689 u8 reserved_at_40[0x18]; 11690 u8 log_memic_addr_alignment[0x8]; 11691 11692 u8 range_start_addr[0x40]; 11693 11694 u8 range_size[0x20]; 11695 11696 u8 memic_size[0x20]; 11697 }; 11698 11699 struct mlx5_ifc_alloc_memic_out_bits { 11700 u8 status[0x8]; 11701 u8 reserved_at_8[0x18]; 11702 11703 u8 syndrome[0x20]; 11704 11705 u8 memic_start_addr[0x40]; 11706 }; 11707 11708 struct mlx5_ifc_dealloc_memic_in_bits { 11709 u8 opcode[0x10]; 11710 u8 reserved_at_10[0x10]; 11711 11712 u8 reserved_at_20[0x10]; 11713 u8 op_mod[0x10]; 11714 11715 u8 reserved_at_40[0x40]; 11716 11717 u8 memic_start_addr[0x40]; 11718 11719 u8 memic_size[0x20]; 11720 11721 u8 reserved_at_e0[0x20]; 11722 }; 11723 11724 struct mlx5_ifc_dealloc_memic_out_bits { 11725 u8 status[0x8]; 11726 u8 reserved_at_8[0x18]; 11727 11728 u8 syndrome[0x20]; 11729 11730 u8 reserved_at_40[0x40]; 11731 }; 11732 11733 struct mlx5_ifc_umem_bits { 11734 u8 reserved_at_0[0x80]; 11735 11736 u8 ats[0x1]; 11737 u8 reserved_at_81[0x1a]; 11738 u8 log_page_size[0x5]; 11739 11740 u8 page_offset[0x20]; 11741 11742 u8 num_of_mtt[0x40]; 11743 11744 struct mlx5_ifc_mtt_bits mtt[]; 11745 }; 11746 11747 struct mlx5_ifc_uctx_bits { 11748 u8 cap[0x20]; 11749 11750 u8 reserved_at_20[0x160]; 11751 }; 11752 11753 struct mlx5_ifc_sw_icm_bits { 11754 u8 modify_field_select[0x40]; 11755 11756 u8 reserved_at_40[0x18]; 11757 u8 log_sw_icm_size[0x8]; 11758 11759 u8 reserved_at_60[0x20]; 11760 11761 u8 sw_icm_start_addr[0x40]; 11762 11763 u8 reserved_at_c0[0x140]; 11764 }; 11765 11766 struct mlx5_ifc_geneve_tlv_option_bits { 11767 u8 modify_field_select[0x40]; 11768 11769 u8 reserved_at_40[0x18]; 11770 u8 geneve_option_fte_index[0x8]; 11771 11772 u8 option_class[0x10]; 11773 u8 option_type[0x8]; 11774 u8 reserved_at_78[0x3]; 11775 u8 option_data_length[0x5]; 11776 11777 u8 reserved_at_80[0x180]; 11778 }; 11779 11780 struct mlx5_ifc_create_umem_in_bits { 11781 u8 opcode[0x10]; 11782 u8 uid[0x10]; 11783 11784 u8 reserved_at_20[0x10]; 11785 u8 op_mod[0x10]; 11786 11787 u8 reserved_at_40[0x40]; 11788 11789 struct mlx5_ifc_umem_bits umem; 11790 }; 11791 11792 struct mlx5_ifc_create_umem_out_bits { 11793 u8 status[0x8]; 11794 u8 reserved_at_8[0x18]; 11795 11796 u8 syndrome[0x20]; 11797 11798 u8 reserved_at_40[0x8]; 11799 u8 umem_id[0x18]; 11800 11801 u8 reserved_at_60[0x20]; 11802 }; 11803 11804 struct mlx5_ifc_destroy_umem_in_bits { 11805 u8 opcode[0x10]; 11806 u8 uid[0x10]; 11807 11808 u8 reserved_at_20[0x10]; 11809 u8 op_mod[0x10]; 11810 11811 u8 reserved_at_40[0x8]; 11812 u8 umem_id[0x18]; 11813 11814 u8 reserved_at_60[0x20]; 11815 }; 11816 11817 struct mlx5_ifc_destroy_umem_out_bits { 11818 u8 status[0x8]; 11819 u8 reserved_at_8[0x18]; 11820 11821 u8 syndrome[0x20]; 11822 11823 u8 reserved_at_40[0x40]; 11824 }; 11825 11826 struct mlx5_ifc_create_uctx_in_bits { 11827 u8 opcode[0x10]; 11828 u8 reserved_at_10[0x10]; 11829 11830 u8 reserved_at_20[0x10]; 11831 u8 op_mod[0x10]; 11832 11833 u8 reserved_at_40[0x40]; 11834 11835 struct mlx5_ifc_uctx_bits uctx; 11836 }; 11837 11838 struct mlx5_ifc_create_uctx_out_bits { 11839 u8 status[0x8]; 11840 u8 reserved_at_8[0x18]; 11841 11842 u8 syndrome[0x20]; 11843 11844 u8 reserved_at_40[0x10]; 11845 u8 uid[0x10]; 11846 11847 u8 reserved_at_60[0x20]; 11848 }; 11849 11850 struct mlx5_ifc_destroy_uctx_in_bits { 11851 u8 opcode[0x10]; 11852 u8 reserved_at_10[0x10]; 11853 11854 u8 reserved_at_20[0x10]; 11855 u8 op_mod[0x10]; 11856 11857 u8 reserved_at_40[0x10]; 11858 u8 uid[0x10]; 11859 11860 u8 reserved_at_60[0x20]; 11861 }; 11862 11863 struct mlx5_ifc_destroy_uctx_out_bits { 11864 u8 status[0x8]; 11865 u8 reserved_at_8[0x18]; 11866 11867 u8 syndrome[0x20]; 11868 11869 u8 reserved_at_40[0x40]; 11870 }; 11871 11872 struct mlx5_ifc_create_sw_icm_in_bits { 11873 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 11874 struct mlx5_ifc_sw_icm_bits sw_icm; 11875 }; 11876 11877 struct mlx5_ifc_create_geneve_tlv_option_in_bits { 11878 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 11879 struct mlx5_ifc_geneve_tlv_option_bits geneve_tlv_opt; 11880 }; 11881 11882 struct mlx5_ifc_mtrc_string_db_param_bits { 11883 u8 string_db_base_address[0x20]; 11884 11885 u8 reserved_at_20[0x8]; 11886 u8 string_db_size[0x18]; 11887 }; 11888 11889 struct mlx5_ifc_mtrc_cap_bits { 11890 u8 trace_owner[0x1]; 11891 u8 trace_to_memory[0x1]; 11892 u8 reserved_at_2[0x4]; 11893 u8 trc_ver[0x2]; 11894 u8 reserved_at_8[0x14]; 11895 u8 num_string_db[0x4]; 11896 11897 u8 first_string_trace[0x8]; 11898 u8 num_string_trace[0x8]; 11899 u8 reserved_at_30[0x28]; 11900 11901 u8 log_max_trace_buffer_size[0x8]; 11902 11903 u8 reserved_at_60[0x20]; 11904 11905 struct mlx5_ifc_mtrc_string_db_param_bits string_db_param[8]; 11906 11907 u8 reserved_at_280[0x180]; 11908 }; 11909 11910 struct mlx5_ifc_mtrc_conf_bits { 11911 u8 reserved_at_0[0x1c]; 11912 u8 trace_mode[0x4]; 11913 u8 reserved_at_20[0x18]; 11914 u8 log_trace_buffer_size[0x8]; 11915 u8 trace_mkey[0x20]; 11916 u8 reserved_at_60[0x3a0]; 11917 }; 11918 11919 struct mlx5_ifc_mtrc_stdb_bits { 11920 u8 string_db_index[0x4]; 11921 u8 reserved_at_4[0x4]; 11922 u8 read_size[0x18]; 11923 u8 start_offset[0x20]; 11924 u8 string_db_data[]; 11925 }; 11926 11927 struct mlx5_ifc_mtrc_ctrl_bits { 11928 u8 trace_status[0x2]; 11929 u8 reserved_at_2[0x2]; 11930 u8 arm_event[0x1]; 11931 u8 reserved_at_5[0xb]; 11932 u8 modify_field_select[0x10]; 11933 u8 reserved_at_20[0x2b]; 11934 u8 current_timestamp52_32[0x15]; 11935 u8 current_timestamp31_0[0x20]; 11936 u8 reserved_at_80[0x180]; 11937 }; 11938 11939 struct mlx5_ifc_host_params_context_bits { 11940 u8 host_number[0x8]; 11941 u8 reserved_at_8[0x7]; 11942 u8 host_pf_disabled[0x1]; 11943 u8 host_num_of_vfs[0x10]; 11944 11945 u8 host_total_vfs[0x10]; 11946 u8 host_pci_bus[0x10]; 11947 11948 u8 reserved_at_40[0x10]; 11949 u8 host_pci_device[0x10]; 11950 11951 u8 reserved_at_60[0x10]; 11952 u8 host_pci_function[0x10]; 11953 11954 u8 reserved_at_80[0x180]; 11955 }; 11956 11957 struct mlx5_ifc_query_esw_functions_in_bits { 11958 u8 opcode[0x10]; 11959 u8 reserved_at_10[0x10]; 11960 11961 u8 reserved_at_20[0x10]; 11962 u8 op_mod[0x10]; 11963 11964 u8 reserved_at_40[0x40]; 11965 }; 11966 11967 struct mlx5_ifc_query_esw_functions_out_bits { 11968 u8 status[0x8]; 11969 u8 reserved_at_8[0x18]; 11970 11971 u8 syndrome[0x20]; 11972 11973 u8 reserved_at_40[0x40]; 11974 11975 struct mlx5_ifc_host_params_context_bits host_params_context; 11976 11977 u8 reserved_at_280[0x180]; 11978 u8 host_sf_enable[][0x40]; 11979 }; 11980 11981 struct mlx5_ifc_sf_partition_bits { 11982 u8 reserved_at_0[0x10]; 11983 u8 log_num_sf[0x8]; 11984 u8 log_sf_bar_size[0x8]; 11985 }; 11986 11987 struct mlx5_ifc_query_sf_partitions_out_bits { 11988 u8 status[0x8]; 11989 u8 reserved_at_8[0x18]; 11990 11991 u8 syndrome[0x20]; 11992 11993 u8 reserved_at_40[0x18]; 11994 u8 num_sf_partitions[0x8]; 11995 11996 u8 reserved_at_60[0x20]; 11997 11998 struct mlx5_ifc_sf_partition_bits sf_partition[]; 11999 }; 12000 12001 struct mlx5_ifc_query_sf_partitions_in_bits { 12002 u8 opcode[0x10]; 12003 u8 reserved_at_10[0x10]; 12004 12005 u8 reserved_at_20[0x10]; 12006 u8 op_mod[0x10]; 12007 12008 u8 reserved_at_40[0x40]; 12009 }; 12010 12011 struct mlx5_ifc_dealloc_sf_out_bits { 12012 u8 status[0x8]; 12013 u8 reserved_at_8[0x18]; 12014 12015 u8 syndrome[0x20]; 12016 12017 u8 reserved_at_40[0x40]; 12018 }; 12019 12020 struct mlx5_ifc_dealloc_sf_in_bits { 12021 u8 opcode[0x10]; 12022 u8 reserved_at_10[0x10]; 12023 12024 u8 reserved_at_20[0x10]; 12025 u8 op_mod[0x10]; 12026 12027 u8 reserved_at_40[0x10]; 12028 u8 function_id[0x10]; 12029 12030 u8 reserved_at_60[0x20]; 12031 }; 12032 12033 struct mlx5_ifc_alloc_sf_out_bits { 12034 u8 status[0x8]; 12035 u8 reserved_at_8[0x18]; 12036 12037 u8 syndrome[0x20]; 12038 12039 u8 reserved_at_40[0x40]; 12040 }; 12041 12042 struct mlx5_ifc_alloc_sf_in_bits { 12043 u8 opcode[0x10]; 12044 u8 reserved_at_10[0x10]; 12045 12046 u8 reserved_at_20[0x10]; 12047 u8 op_mod[0x10]; 12048 12049 u8 reserved_at_40[0x10]; 12050 u8 function_id[0x10]; 12051 12052 u8 reserved_at_60[0x20]; 12053 }; 12054 12055 struct mlx5_ifc_affiliated_event_header_bits { 12056 u8 reserved_at_0[0x10]; 12057 u8 obj_type[0x10]; 12058 12059 u8 obj_id[0x20]; 12060 }; 12061 12062 enum { 12063 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = BIT_ULL(0xc), 12064 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_IPSEC = BIT_ULL(0x13), 12065 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_SAMPLER = BIT_ULL(0x20), 12066 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_FLOW_METER_ASO = BIT_ULL(0x24), 12067 }; 12068 12069 enum { 12070 MLX5_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = 0xc, 12071 MLX5_GENERAL_OBJECT_TYPES_IPSEC = 0x13, 12072 MLX5_GENERAL_OBJECT_TYPES_SAMPLER = 0x20, 12073 MLX5_GENERAL_OBJECT_TYPES_FLOW_METER_ASO = 0x24, 12074 MLX5_GENERAL_OBJECT_TYPES_MACSEC = 0x27, 12075 MLX5_GENERAL_OBJECT_TYPES_INT_KEK = 0x47, 12076 MLX5_GENERAL_OBJECT_TYPES_FLOW_TABLE_ALIAS = 0xff15, 12077 }; 12078 12079 enum { 12080 MLX5_IPSEC_OBJECT_ICV_LEN_16B, 12081 }; 12082 12083 enum { 12084 MLX5_IPSEC_ASO_REG_C_0_1 = 0x0, 12085 MLX5_IPSEC_ASO_REG_C_2_3 = 0x1, 12086 MLX5_IPSEC_ASO_REG_C_4_5 = 0x2, 12087 MLX5_IPSEC_ASO_REG_C_6_7 = 0x3, 12088 }; 12089 12090 enum { 12091 MLX5_IPSEC_ASO_MODE = 0x0, 12092 MLX5_IPSEC_ASO_REPLAY_PROTECTION = 0x1, 12093 MLX5_IPSEC_ASO_INC_SN = 0x2, 12094 }; 12095 12096 enum { 12097 MLX5_IPSEC_ASO_REPLAY_WIN_32BIT = 0x0, 12098 MLX5_IPSEC_ASO_REPLAY_WIN_64BIT = 0x1, 12099 MLX5_IPSEC_ASO_REPLAY_WIN_128BIT = 0x2, 12100 MLX5_IPSEC_ASO_REPLAY_WIN_256BIT = 0x3, 12101 }; 12102 12103 struct mlx5_ifc_ipsec_aso_bits { 12104 u8 valid[0x1]; 12105 u8 reserved_at_201[0x1]; 12106 u8 mode[0x2]; 12107 u8 window_sz[0x2]; 12108 u8 soft_lft_arm[0x1]; 12109 u8 hard_lft_arm[0x1]; 12110 u8 remove_flow_enable[0x1]; 12111 u8 esn_event_arm[0x1]; 12112 u8 reserved_at_20a[0x16]; 12113 12114 u8 remove_flow_pkt_cnt[0x20]; 12115 12116 u8 remove_flow_soft_lft[0x20]; 12117 12118 u8 reserved_at_260[0x80]; 12119 12120 u8 mode_parameter[0x20]; 12121 12122 u8 replay_protection_window[0x100]; 12123 }; 12124 12125 struct mlx5_ifc_ipsec_obj_bits { 12126 u8 modify_field_select[0x40]; 12127 u8 full_offload[0x1]; 12128 u8 reserved_at_41[0x1]; 12129 u8 esn_en[0x1]; 12130 u8 esn_overlap[0x1]; 12131 u8 reserved_at_44[0x2]; 12132 u8 icv_length[0x2]; 12133 u8 reserved_at_48[0x4]; 12134 u8 aso_return_reg[0x4]; 12135 u8 reserved_at_50[0x10]; 12136 12137 u8 esn_msb[0x20]; 12138 12139 u8 reserved_at_80[0x8]; 12140 u8 dekn[0x18]; 12141 12142 u8 salt[0x20]; 12143 12144 u8 implicit_iv[0x40]; 12145 12146 u8 reserved_at_100[0x8]; 12147 u8 ipsec_aso_access_pd[0x18]; 12148 u8 reserved_at_120[0xe0]; 12149 12150 struct mlx5_ifc_ipsec_aso_bits ipsec_aso; 12151 }; 12152 12153 struct mlx5_ifc_create_ipsec_obj_in_bits { 12154 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12155 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 12156 }; 12157 12158 enum { 12159 MLX5_MODIFY_IPSEC_BITMASK_ESN_OVERLAP = BIT(0), 12160 MLX5_MODIFY_IPSEC_BITMASK_ESN_MSB = BIT(1), 12161 }; 12162 12163 struct mlx5_ifc_query_ipsec_obj_out_bits { 12164 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 12165 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 12166 }; 12167 12168 struct mlx5_ifc_modify_ipsec_obj_in_bits { 12169 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12170 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 12171 }; 12172 12173 enum { 12174 MLX5_MACSEC_ASO_REPLAY_PROTECTION = 0x1, 12175 }; 12176 12177 enum { 12178 MLX5_MACSEC_ASO_REPLAY_WIN_32BIT = 0x0, 12179 MLX5_MACSEC_ASO_REPLAY_WIN_64BIT = 0x1, 12180 MLX5_MACSEC_ASO_REPLAY_WIN_128BIT = 0x2, 12181 MLX5_MACSEC_ASO_REPLAY_WIN_256BIT = 0x3, 12182 }; 12183 12184 #define MLX5_MACSEC_ASO_INC_SN 0x2 12185 #define MLX5_MACSEC_ASO_REG_C_4_5 0x2 12186 12187 struct mlx5_ifc_macsec_aso_bits { 12188 u8 valid[0x1]; 12189 u8 reserved_at_1[0x1]; 12190 u8 mode[0x2]; 12191 u8 window_size[0x2]; 12192 u8 soft_lifetime_arm[0x1]; 12193 u8 hard_lifetime_arm[0x1]; 12194 u8 remove_flow_enable[0x1]; 12195 u8 epn_event_arm[0x1]; 12196 u8 reserved_at_a[0x16]; 12197 12198 u8 remove_flow_packet_count[0x20]; 12199 12200 u8 remove_flow_soft_lifetime[0x20]; 12201 12202 u8 reserved_at_60[0x80]; 12203 12204 u8 mode_parameter[0x20]; 12205 12206 u8 replay_protection_window[8][0x20]; 12207 }; 12208 12209 struct mlx5_ifc_macsec_offload_obj_bits { 12210 u8 modify_field_select[0x40]; 12211 12212 u8 confidentiality_en[0x1]; 12213 u8 reserved_at_41[0x1]; 12214 u8 epn_en[0x1]; 12215 u8 epn_overlap[0x1]; 12216 u8 reserved_at_44[0x2]; 12217 u8 confidentiality_offset[0x2]; 12218 u8 reserved_at_48[0x4]; 12219 u8 aso_return_reg[0x4]; 12220 u8 reserved_at_50[0x10]; 12221 12222 u8 epn_msb[0x20]; 12223 12224 u8 reserved_at_80[0x8]; 12225 u8 dekn[0x18]; 12226 12227 u8 reserved_at_a0[0x20]; 12228 12229 u8 sci[0x40]; 12230 12231 u8 reserved_at_100[0x8]; 12232 u8 macsec_aso_access_pd[0x18]; 12233 12234 u8 reserved_at_120[0x60]; 12235 12236 u8 salt[3][0x20]; 12237 12238 u8 reserved_at_1e0[0x20]; 12239 12240 struct mlx5_ifc_macsec_aso_bits macsec_aso; 12241 }; 12242 12243 struct mlx5_ifc_create_macsec_obj_in_bits { 12244 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12245 struct mlx5_ifc_macsec_offload_obj_bits macsec_object; 12246 }; 12247 12248 struct mlx5_ifc_modify_macsec_obj_in_bits { 12249 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12250 struct mlx5_ifc_macsec_offload_obj_bits macsec_object; 12251 }; 12252 12253 enum { 12254 MLX5_MODIFY_MACSEC_BITMASK_EPN_OVERLAP = BIT(0), 12255 MLX5_MODIFY_MACSEC_BITMASK_EPN_MSB = BIT(1), 12256 }; 12257 12258 struct mlx5_ifc_query_macsec_obj_out_bits { 12259 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 12260 struct mlx5_ifc_macsec_offload_obj_bits macsec_object; 12261 }; 12262 12263 struct mlx5_ifc_wrapped_dek_bits { 12264 u8 gcm_iv[0x60]; 12265 12266 u8 reserved_at_60[0x20]; 12267 12268 u8 const0[0x1]; 12269 u8 key_size[0x1]; 12270 u8 reserved_at_82[0x2]; 12271 u8 key2_invalid[0x1]; 12272 u8 reserved_at_85[0x3]; 12273 u8 pd[0x18]; 12274 12275 u8 key_purpose[0x5]; 12276 u8 reserved_at_a5[0x13]; 12277 u8 kek_id[0x8]; 12278 12279 u8 reserved_at_c0[0x40]; 12280 12281 u8 key1[0x8][0x20]; 12282 12283 u8 key2[0x8][0x20]; 12284 12285 u8 reserved_at_300[0x40]; 12286 12287 u8 const1[0x1]; 12288 u8 reserved_at_341[0x1f]; 12289 12290 u8 reserved_at_360[0x20]; 12291 12292 u8 auth_tag[0x80]; 12293 }; 12294 12295 struct mlx5_ifc_encryption_key_obj_bits { 12296 u8 modify_field_select[0x40]; 12297 12298 u8 state[0x8]; 12299 u8 sw_wrapped[0x1]; 12300 u8 reserved_at_49[0xb]; 12301 u8 key_size[0x4]; 12302 u8 reserved_at_58[0x4]; 12303 u8 key_purpose[0x4]; 12304 12305 u8 reserved_at_60[0x8]; 12306 u8 pd[0x18]; 12307 12308 u8 reserved_at_80[0x100]; 12309 12310 u8 opaque[0x40]; 12311 12312 u8 reserved_at_1c0[0x40]; 12313 12314 u8 key[8][0x80]; 12315 12316 u8 sw_wrapped_dek[8][0x80]; 12317 12318 u8 reserved_at_a00[0x600]; 12319 }; 12320 12321 struct mlx5_ifc_create_encryption_key_in_bits { 12322 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12323 struct mlx5_ifc_encryption_key_obj_bits encryption_key_object; 12324 }; 12325 12326 struct mlx5_ifc_modify_encryption_key_in_bits { 12327 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12328 struct mlx5_ifc_encryption_key_obj_bits encryption_key_object; 12329 }; 12330 12331 enum { 12332 MLX5_FLOW_METER_MODE_BYTES_IP_LENGTH = 0x0, 12333 MLX5_FLOW_METER_MODE_BYTES_CALC_WITH_L2 = 0x1, 12334 MLX5_FLOW_METER_MODE_BYTES_CALC_WITH_L2_IPG = 0x2, 12335 MLX5_FLOW_METER_MODE_NUM_PACKETS = 0x3, 12336 }; 12337 12338 struct mlx5_ifc_flow_meter_parameters_bits { 12339 u8 valid[0x1]; 12340 u8 bucket_overflow[0x1]; 12341 u8 start_color[0x2]; 12342 u8 both_buckets_on_green[0x1]; 12343 u8 reserved_at_5[0x1]; 12344 u8 meter_mode[0x2]; 12345 u8 reserved_at_8[0x18]; 12346 12347 u8 reserved_at_20[0x20]; 12348 12349 u8 reserved_at_40[0x3]; 12350 u8 cbs_exponent[0x5]; 12351 u8 cbs_mantissa[0x8]; 12352 u8 reserved_at_50[0x3]; 12353 u8 cir_exponent[0x5]; 12354 u8 cir_mantissa[0x8]; 12355 12356 u8 reserved_at_60[0x20]; 12357 12358 u8 reserved_at_80[0x3]; 12359 u8 ebs_exponent[0x5]; 12360 u8 ebs_mantissa[0x8]; 12361 u8 reserved_at_90[0x3]; 12362 u8 eir_exponent[0x5]; 12363 u8 eir_mantissa[0x8]; 12364 12365 u8 reserved_at_a0[0x60]; 12366 }; 12367 12368 struct mlx5_ifc_flow_meter_aso_obj_bits { 12369 u8 modify_field_select[0x40]; 12370 12371 u8 reserved_at_40[0x40]; 12372 12373 u8 reserved_at_80[0x8]; 12374 u8 meter_aso_access_pd[0x18]; 12375 12376 u8 reserved_at_a0[0x160]; 12377 12378 struct mlx5_ifc_flow_meter_parameters_bits flow_meter_parameters[2]; 12379 }; 12380 12381 struct mlx5_ifc_create_flow_meter_aso_obj_in_bits { 12382 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 12383 struct mlx5_ifc_flow_meter_aso_obj_bits flow_meter_aso_obj; 12384 }; 12385 12386 struct mlx5_ifc_int_kek_obj_bits { 12387 u8 modify_field_select[0x40]; 12388 12389 u8 state[0x8]; 12390 u8 auto_gen[0x1]; 12391 u8 reserved_at_49[0xb]; 12392 u8 key_size[0x4]; 12393 u8 reserved_at_58[0x8]; 12394 12395 u8 reserved_at_60[0x8]; 12396 u8 pd[0x18]; 12397 12398 u8 reserved_at_80[0x180]; 12399 u8 key[8][0x80]; 12400 12401 u8 reserved_at_600[0x200]; 12402 }; 12403 12404 struct mlx5_ifc_create_int_kek_obj_in_bits { 12405 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12406 struct mlx5_ifc_int_kek_obj_bits int_kek_object; 12407 }; 12408 12409 struct mlx5_ifc_create_int_kek_obj_out_bits { 12410 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 12411 struct mlx5_ifc_int_kek_obj_bits int_kek_object; 12412 }; 12413 12414 struct mlx5_ifc_sampler_obj_bits { 12415 u8 modify_field_select[0x40]; 12416 12417 u8 table_type[0x8]; 12418 u8 level[0x8]; 12419 u8 reserved_at_50[0xf]; 12420 u8 ignore_flow_level[0x1]; 12421 12422 u8 sample_ratio[0x20]; 12423 12424 u8 reserved_at_80[0x8]; 12425 u8 sample_table_id[0x18]; 12426 12427 u8 reserved_at_a0[0x8]; 12428 u8 default_table_id[0x18]; 12429 12430 u8 sw_steering_icm_address_rx[0x40]; 12431 u8 sw_steering_icm_address_tx[0x40]; 12432 12433 u8 reserved_at_140[0xa0]; 12434 }; 12435 12436 struct mlx5_ifc_create_sampler_obj_in_bits { 12437 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12438 struct mlx5_ifc_sampler_obj_bits sampler_object; 12439 }; 12440 12441 struct mlx5_ifc_query_sampler_obj_out_bits { 12442 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 12443 struct mlx5_ifc_sampler_obj_bits sampler_object; 12444 }; 12445 12446 enum { 12447 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_128 = 0x0, 12448 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_256 = 0x1, 12449 }; 12450 12451 enum { 12452 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_PURPOSE_TLS = 0x1, 12453 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_PURPOSE_IPSEC = 0x2, 12454 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_PURPOSE_MACSEC = 0x4, 12455 }; 12456 12457 struct mlx5_ifc_tls_static_params_bits { 12458 u8 const_2[0x2]; 12459 u8 tls_version[0x4]; 12460 u8 const_1[0x2]; 12461 u8 reserved_at_8[0x14]; 12462 u8 encryption_standard[0x4]; 12463 12464 u8 reserved_at_20[0x20]; 12465 12466 u8 initial_record_number[0x40]; 12467 12468 u8 resync_tcp_sn[0x20]; 12469 12470 u8 gcm_iv[0x20]; 12471 12472 u8 implicit_iv[0x40]; 12473 12474 u8 reserved_at_100[0x8]; 12475 u8 dek_index[0x18]; 12476 12477 u8 reserved_at_120[0xe0]; 12478 }; 12479 12480 struct mlx5_ifc_tls_progress_params_bits { 12481 u8 next_record_tcp_sn[0x20]; 12482 12483 u8 hw_resync_tcp_sn[0x20]; 12484 12485 u8 record_tracker_state[0x2]; 12486 u8 auth_state[0x2]; 12487 u8 reserved_at_44[0x4]; 12488 u8 hw_offset_record_number[0x18]; 12489 }; 12490 12491 enum { 12492 MLX5_MTT_PERM_READ = 1 << 0, 12493 MLX5_MTT_PERM_WRITE = 1 << 1, 12494 MLX5_MTT_PERM_RW = MLX5_MTT_PERM_READ | MLX5_MTT_PERM_WRITE, 12495 }; 12496 12497 enum { 12498 MLX5_SUSPEND_VHCA_IN_OP_MOD_SUSPEND_INITIATOR = 0x0, 12499 MLX5_SUSPEND_VHCA_IN_OP_MOD_SUSPEND_RESPONDER = 0x1, 12500 }; 12501 12502 struct mlx5_ifc_suspend_vhca_in_bits { 12503 u8 opcode[0x10]; 12504 u8 uid[0x10]; 12505 12506 u8 reserved_at_20[0x10]; 12507 u8 op_mod[0x10]; 12508 12509 u8 reserved_at_40[0x10]; 12510 u8 vhca_id[0x10]; 12511 12512 u8 reserved_at_60[0x20]; 12513 }; 12514 12515 struct mlx5_ifc_suspend_vhca_out_bits { 12516 u8 status[0x8]; 12517 u8 reserved_at_8[0x18]; 12518 12519 u8 syndrome[0x20]; 12520 12521 u8 reserved_at_40[0x40]; 12522 }; 12523 12524 enum { 12525 MLX5_RESUME_VHCA_IN_OP_MOD_RESUME_RESPONDER = 0x0, 12526 MLX5_RESUME_VHCA_IN_OP_MOD_RESUME_INITIATOR = 0x1, 12527 }; 12528 12529 struct mlx5_ifc_resume_vhca_in_bits { 12530 u8 opcode[0x10]; 12531 u8 uid[0x10]; 12532 12533 u8 reserved_at_20[0x10]; 12534 u8 op_mod[0x10]; 12535 12536 u8 reserved_at_40[0x10]; 12537 u8 vhca_id[0x10]; 12538 12539 u8 reserved_at_60[0x20]; 12540 }; 12541 12542 struct mlx5_ifc_resume_vhca_out_bits { 12543 u8 status[0x8]; 12544 u8 reserved_at_8[0x18]; 12545 12546 u8 syndrome[0x20]; 12547 12548 u8 reserved_at_40[0x40]; 12549 }; 12550 12551 struct mlx5_ifc_query_vhca_migration_state_in_bits { 12552 u8 opcode[0x10]; 12553 u8 uid[0x10]; 12554 12555 u8 reserved_at_20[0x10]; 12556 u8 op_mod[0x10]; 12557 12558 u8 incremental[0x1]; 12559 u8 chunk[0x1]; 12560 u8 reserved_at_42[0xe]; 12561 u8 vhca_id[0x10]; 12562 12563 u8 reserved_at_60[0x20]; 12564 }; 12565 12566 struct mlx5_ifc_query_vhca_migration_state_out_bits { 12567 u8 status[0x8]; 12568 u8 reserved_at_8[0x18]; 12569 12570 u8 syndrome[0x20]; 12571 12572 u8 reserved_at_40[0x40]; 12573 12574 u8 required_umem_size[0x20]; 12575 12576 u8 reserved_at_a0[0x20]; 12577 12578 u8 remaining_total_size[0x40]; 12579 12580 u8 reserved_at_100[0x100]; 12581 }; 12582 12583 struct mlx5_ifc_save_vhca_state_in_bits { 12584 u8 opcode[0x10]; 12585 u8 uid[0x10]; 12586 12587 u8 reserved_at_20[0x10]; 12588 u8 op_mod[0x10]; 12589 12590 u8 incremental[0x1]; 12591 u8 set_track[0x1]; 12592 u8 reserved_at_42[0xe]; 12593 u8 vhca_id[0x10]; 12594 12595 u8 reserved_at_60[0x20]; 12596 12597 u8 va[0x40]; 12598 12599 u8 mkey[0x20]; 12600 12601 u8 size[0x20]; 12602 }; 12603 12604 struct mlx5_ifc_save_vhca_state_out_bits { 12605 u8 status[0x8]; 12606 u8 reserved_at_8[0x18]; 12607 12608 u8 syndrome[0x20]; 12609 12610 u8 actual_image_size[0x20]; 12611 12612 u8 next_required_umem_size[0x20]; 12613 }; 12614 12615 struct mlx5_ifc_load_vhca_state_in_bits { 12616 u8 opcode[0x10]; 12617 u8 uid[0x10]; 12618 12619 u8 reserved_at_20[0x10]; 12620 u8 op_mod[0x10]; 12621 12622 u8 reserved_at_40[0x10]; 12623 u8 vhca_id[0x10]; 12624 12625 u8 reserved_at_60[0x20]; 12626 12627 u8 va[0x40]; 12628 12629 u8 mkey[0x20]; 12630 12631 u8 size[0x20]; 12632 }; 12633 12634 struct mlx5_ifc_load_vhca_state_out_bits { 12635 u8 status[0x8]; 12636 u8 reserved_at_8[0x18]; 12637 12638 u8 syndrome[0x20]; 12639 12640 u8 reserved_at_40[0x40]; 12641 }; 12642 12643 struct mlx5_ifc_adv_virtualization_cap_bits { 12644 u8 reserved_at_0[0x3]; 12645 u8 pg_track_log_max_num[0x5]; 12646 u8 pg_track_max_num_range[0x8]; 12647 u8 pg_track_log_min_addr_space[0x8]; 12648 u8 pg_track_log_max_addr_space[0x8]; 12649 12650 u8 reserved_at_20[0x3]; 12651 u8 pg_track_log_min_msg_size[0x5]; 12652 u8 reserved_at_28[0x3]; 12653 u8 pg_track_log_max_msg_size[0x5]; 12654 u8 reserved_at_30[0x3]; 12655 u8 pg_track_log_min_page_size[0x5]; 12656 u8 reserved_at_38[0x3]; 12657 u8 pg_track_log_max_page_size[0x5]; 12658 12659 u8 reserved_at_40[0x7c0]; 12660 }; 12661 12662 struct mlx5_ifc_page_track_report_entry_bits { 12663 u8 dirty_address_high[0x20]; 12664 12665 u8 dirty_address_low[0x20]; 12666 }; 12667 12668 enum { 12669 MLX5_PAGE_TRACK_STATE_TRACKING, 12670 MLX5_PAGE_TRACK_STATE_REPORTING, 12671 MLX5_PAGE_TRACK_STATE_ERROR, 12672 }; 12673 12674 struct mlx5_ifc_page_track_range_bits { 12675 u8 start_address[0x40]; 12676 12677 u8 length[0x40]; 12678 }; 12679 12680 struct mlx5_ifc_page_track_bits { 12681 u8 modify_field_select[0x40]; 12682 12683 u8 reserved_at_40[0x10]; 12684 u8 vhca_id[0x10]; 12685 12686 u8 reserved_at_60[0x20]; 12687 12688 u8 state[0x4]; 12689 u8 track_type[0x4]; 12690 u8 log_addr_space_size[0x8]; 12691 u8 reserved_at_90[0x3]; 12692 u8 log_page_size[0x5]; 12693 u8 reserved_at_98[0x3]; 12694 u8 log_msg_size[0x5]; 12695 12696 u8 reserved_at_a0[0x8]; 12697 u8 reporting_qpn[0x18]; 12698 12699 u8 reserved_at_c0[0x18]; 12700 u8 num_ranges[0x8]; 12701 12702 u8 reserved_at_e0[0x20]; 12703 12704 u8 range_start_address[0x40]; 12705 12706 u8 length[0x40]; 12707 12708 struct mlx5_ifc_page_track_range_bits track_range[0]; 12709 }; 12710 12711 struct mlx5_ifc_create_page_track_obj_in_bits { 12712 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12713 struct mlx5_ifc_page_track_bits obj_context; 12714 }; 12715 12716 struct mlx5_ifc_modify_page_track_obj_in_bits { 12717 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12718 struct mlx5_ifc_page_track_bits obj_context; 12719 }; 12720 12721 struct mlx5_ifc_query_page_track_obj_out_bits { 12722 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 12723 struct mlx5_ifc_page_track_bits obj_context; 12724 }; 12725 12726 struct mlx5_ifc_msecq_reg_bits { 12727 u8 reserved_at_0[0x20]; 12728 12729 u8 reserved_at_20[0x12]; 12730 u8 network_option[0x2]; 12731 u8 local_ssm_code[0x4]; 12732 u8 local_enhanced_ssm_code[0x8]; 12733 12734 u8 local_clock_identity[0x40]; 12735 12736 u8 reserved_at_80[0x180]; 12737 }; 12738 12739 enum { 12740 MLX5_MSEES_FIELD_SELECT_ENABLE = BIT(0), 12741 MLX5_MSEES_FIELD_SELECT_ADMIN_STATUS = BIT(1), 12742 MLX5_MSEES_FIELD_SELECT_ADMIN_FREQ_MEASURE = BIT(2), 12743 }; 12744 12745 enum mlx5_msees_admin_status { 12746 MLX5_MSEES_ADMIN_STATUS_FREE_RUNNING = 0x0, 12747 MLX5_MSEES_ADMIN_STATUS_TRACK = 0x1, 12748 }; 12749 12750 enum mlx5_msees_oper_status { 12751 MLX5_MSEES_OPER_STATUS_FREE_RUNNING = 0x0, 12752 MLX5_MSEES_OPER_STATUS_SELF_TRACK = 0x1, 12753 MLX5_MSEES_OPER_STATUS_OTHER_TRACK = 0x2, 12754 MLX5_MSEES_OPER_STATUS_HOLDOVER = 0x3, 12755 MLX5_MSEES_OPER_STATUS_FAIL_HOLDOVER = 0x4, 12756 MLX5_MSEES_OPER_STATUS_FAIL_FREE_RUNNING = 0x5, 12757 }; 12758 12759 enum mlx5_msees_failure_reason { 12760 MLX5_MSEES_FAILURE_REASON_UNDEFINED_ERROR = 0x0, 12761 MLX5_MSEES_FAILURE_REASON_PORT_DOWN = 0x1, 12762 MLX5_MSEES_FAILURE_REASON_TOO_HIGH_FREQUENCY_DIFF = 0x2, 12763 MLX5_MSEES_FAILURE_REASON_NET_SYNCHRONIZER_DEVICE_ERROR = 0x3, 12764 MLX5_MSEES_FAILURE_REASON_LACK_OF_RESOURCES = 0x4, 12765 }; 12766 12767 struct mlx5_ifc_msees_reg_bits { 12768 u8 reserved_at_0[0x8]; 12769 u8 local_port[0x8]; 12770 u8 pnat[0x2]; 12771 u8 lp_msb[0x2]; 12772 u8 reserved_at_14[0xc]; 12773 12774 u8 field_select[0x20]; 12775 12776 u8 admin_status[0x4]; 12777 u8 oper_status[0x4]; 12778 u8 ho_acq[0x1]; 12779 u8 reserved_at_49[0xc]; 12780 u8 admin_freq_measure[0x1]; 12781 u8 oper_freq_measure[0x1]; 12782 u8 failure_reason[0x9]; 12783 12784 u8 frequency_diff[0x20]; 12785 12786 u8 reserved_at_80[0x180]; 12787 }; 12788 12789 #endif /* MLX5_IFC_H */ 12790