1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 #ifndef MLX5_IFC_H 33 #define MLX5_IFC_H 34 35 #include "mlx5_ifc_fpga.h" 36 37 enum { 38 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0, 39 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1, 40 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2, 41 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3, 42 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13, 43 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14, 44 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c, 45 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d, 46 MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4, 47 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5, 48 MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED = 0x7, 49 MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT = 0xc, 50 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10, 51 MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR = 0x11, 52 MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR = 0x12, 53 MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR = 0x8, 54 MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE = 0x9, 55 MLX5_EVENT_TYPE_CODING_GPIO_EVENT = 0x15, 56 MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19, 57 MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a, 58 MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT = 0x1b, 59 MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT = 0x1f, 60 MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa, 61 MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb, 62 MLX5_EVENT_TYPE_CODING_FPGA_ERROR = 0x20, 63 MLX5_EVENT_TYPE_CODING_FPGA_QP_ERROR = 0x21 64 }; 65 66 enum { 67 MLX5_MODIFY_TIR_BITMASK_LRO = 0x0, 68 MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE = 0x1, 69 MLX5_MODIFY_TIR_BITMASK_HASH = 0x2, 70 MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN = 0x3 71 }; 72 73 enum { 74 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0, 75 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3, 76 }; 77 78 enum { 79 MLX5_GENERAL_OBJ_TYPES_CAP_UCTX = (1ULL << 4), 80 MLX5_GENERAL_OBJ_TYPES_CAP_UMEM = (1ULL << 5), 81 }; 82 83 enum { 84 MLX5_OBJ_TYPE_UCTX = 0x0004, 85 MLX5_OBJ_TYPE_UMEM = 0x0005, 86 }; 87 88 enum { 89 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100, 90 MLX5_CMD_OP_QUERY_ADAPTER = 0x101, 91 MLX5_CMD_OP_INIT_HCA = 0x102, 92 MLX5_CMD_OP_TEARDOWN_HCA = 0x103, 93 MLX5_CMD_OP_ENABLE_HCA = 0x104, 94 MLX5_CMD_OP_DISABLE_HCA = 0x105, 95 MLX5_CMD_OP_QUERY_PAGES = 0x107, 96 MLX5_CMD_OP_MANAGE_PAGES = 0x108, 97 MLX5_CMD_OP_SET_HCA_CAP = 0x109, 98 MLX5_CMD_OP_QUERY_ISSI = 0x10a, 99 MLX5_CMD_OP_SET_ISSI = 0x10b, 100 MLX5_CMD_OP_SET_DRIVER_VERSION = 0x10d, 101 MLX5_CMD_OP_CREATE_MKEY = 0x200, 102 MLX5_CMD_OP_QUERY_MKEY = 0x201, 103 MLX5_CMD_OP_DESTROY_MKEY = 0x202, 104 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203, 105 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204, 106 MLX5_CMD_OP_ALLOC_MEMIC = 0x205, 107 MLX5_CMD_OP_DEALLOC_MEMIC = 0x206, 108 MLX5_CMD_OP_CREATE_EQ = 0x301, 109 MLX5_CMD_OP_DESTROY_EQ = 0x302, 110 MLX5_CMD_OP_QUERY_EQ = 0x303, 111 MLX5_CMD_OP_GEN_EQE = 0x304, 112 MLX5_CMD_OP_CREATE_CQ = 0x400, 113 MLX5_CMD_OP_DESTROY_CQ = 0x401, 114 MLX5_CMD_OP_QUERY_CQ = 0x402, 115 MLX5_CMD_OP_MODIFY_CQ = 0x403, 116 MLX5_CMD_OP_CREATE_QP = 0x500, 117 MLX5_CMD_OP_DESTROY_QP = 0x501, 118 MLX5_CMD_OP_RST2INIT_QP = 0x502, 119 MLX5_CMD_OP_INIT2RTR_QP = 0x503, 120 MLX5_CMD_OP_RTR2RTS_QP = 0x504, 121 MLX5_CMD_OP_RTS2RTS_QP = 0x505, 122 MLX5_CMD_OP_SQERR2RTS_QP = 0x506, 123 MLX5_CMD_OP_2ERR_QP = 0x507, 124 MLX5_CMD_OP_2RST_QP = 0x50a, 125 MLX5_CMD_OP_QUERY_QP = 0x50b, 126 MLX5_CMD_OP_SQD_RTS_QP = 0x50c, 127 MLX5_CMD_OP_INIT2INIT_QP = 0x50e, 128 MLX5_CMD_OP_CREATE_PSV = 0x600, 129 MLX5_CMD_OP_DESTROY_PSV = 0x601, 130 MLX5_CMD_OP_CREATE_SRQ = 0x700, 131 MLX5_CMD_OP_DESTROY_SRQ = 0x701, 132 MLX5_CMD_OP_QUERY_SRQ = 0x702, 133 MLX5_CMD_OP_ARM_RQ = 0x703, 134 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705, 135 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706, 136 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707, 137 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708, 138 MLX5_CMD_OP_CREATE_DCT = 0x710, 139 MLX5_CMD_OP_DESTROY_DCT = 0x711, 140 MLX5_CMD_OP_DRAIN_DCT = 0x712, 141 MLX5_CMD_OP_QUERY_DCT = 0x713, 142 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714, 143 MLX5_CMD_OP_CREATE_XRQ = 0x717, 144 MLX5_CMD_OP_DESTROY_XRQ = 0x718, 145 MLX5_CMD_OP_QUERY_XRQ = 0x719, 146 MLX5_CMD_OP_ARM_XRQ = 0x71a, 147 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750, 148 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751, 149 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752, 150 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753, 151 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754, 152 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755, 153 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760, 154 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761, 155 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762, 156 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763, 157 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764, 158 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765, 159 MLX5_CMD_OP_QUERY_VNIC_ENV = 0x76f, 160 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770, 161 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771, 162 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772, 163 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773, 164 MLX5_CMD_OP_SET_PP_RATE_LIMIT = 0x780, 165 MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781, 166 MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT = 0x782, 167 MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT = 0x783, 168 MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT = 0x784, 169 MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT = 0x785, 170 MLX5_CMD_OP_CREATE_QOS_PARA_VPORT = 0x786, 171 MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT = 0x787, 172 MLX5_CMD_OP_ALLOC_PD = 0x800, 173 MLX5_CMD_OP_DEALLOC_PD = 0x801, 174 MLX5_CMD_OP_ALLOC_UAR = 0x802, 175 MLX5_CMD_OP_DEALLOC_UAR = 0x803, 176 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804, 177 MLX5_CMD_OP_ACCESS_REG = 0x805, 178 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806, 179 MLX5_CMD_OP_DETACH_FROM_MCG = 0x807, 180 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a, 181 MLX5_CMD_OP_MAD_IFC = 0x50d, 182 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b, 183 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c, 184 MLX5_CMD_OP_NOP = 0x80d, 185 MLX5_CMD_OP_ALLOC_XRCD = 0x80e, 186 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f, 187 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816, 188 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817, 189 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822, 190 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823, 191 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824, 192 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825, 193 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826, 194 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827, 195 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828, 196 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829, 197 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a, 198 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b, 199 MLX5_CMD_OP_SET_WOL_ROL = 0x830, 200 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831, 201 MLX5_CMD_OP_CREATE_LAG = 0x840, 202 MLX5_CMD_OP_MODIFY_LAG = 0x841, 203 MLX5_CMD_OP_QUERY_LAG = 0x842, 204 MLX5_CMD_OP_DESTROY_LAG = 0x843, 205 MLX5_CMD_OP_CREATE_VPORT_LAG = 0x844, 206 MLX5_CMD_OP_DESTROY_VPORT_LAG = 0x845, 207 MLX5_CMD_OP_CREATE_TIR = 0x900, 208 MLX5_CMD_OP_MODIFY_TIR = 0x901, 209 MLX5_CMD_OP_DESTROY_TIR = 0x902, 210 MLX5_CMD_OP_QUERY_TIR = 0x903, 211 MLX5_CMD_OP_CREATE_SQ = 0x904, 212 MLX5_CMD_OP_MODIFY_SQ = 0x905, 213 MLX5_CMD_OP_DESTROY_SQ = 0x906, 214 MLX5_CMD_OP_QUERY_SQ = 0x907, 215 MLX5_CMD_OP_CREATE_RQ = 0x908, 216 MLX5_CMD_OP_MODIFY_RQ = 0x909, 217 MLX5_CMD_OP_SET_DELAY_DROP_PARAMS = 0x910, 218 MLX5_CMD_OP_DESTROY_RQ = 0x90a, 219 MLX5_CMD_OP_QUERY_RQ = 0x90b, 220 MLX5_CMD_OP_CREATE_RMP = 0x90c, 221 MLX5_CMD_OP_MODIFY_RMP = 0x90d, 222 MLX5_CMD_OP_DESTROY_RMP = 0x90e, 223 MLX5_CMD_OP_QUERY_RMP = 0x90f, 224 MLX5_CMD_OP_CREATE_TIS = 0x912, 225 MLX5_CMD_OP_MODIFY_TIS = 0x913, 226 MLX5_CMD_OP_DESTROY_TIS = 0x914, 227 MLX5_CMD_OP_QUERY_TIS = 0x915, 228 MLX5_CMD_OP_CREATE_RQT = 0x916, 229 MLX5_CMD_OP_MODIFY_RQT = 0x917, 230 MLX5_CMD_OP_DESTROY_RQT = 0x918, 231 MLX5_CMD_OP_QUERY_RQT = 0x919, 232 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f, 233 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930, 234 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931, 235 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932, 236 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933, 237 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934, 238 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935, 239 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936, 240 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937, 241 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938, 242 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939, 243 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a, 244 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b, 245 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c, 246 MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT = 0x93d, 247 MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT = 0x93e, 248 MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT = 0x940, 249 MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941, 250 MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT = 0x942, 251 MLX5_CMD_OP_FPGA_CREATE_QP = 0x960, 252 MLX5_CMD_OP_FPGA_MODIFY_QP = 0x961, 253 MLX5_CMD_OP_FPGA_QUERY_QP = 0x962, 254 MLX5_CMD_OP_FPGA_DESTROY_QP = 0x963, 255 MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS = 0x964, 256 MLX5_CMD_OP_CREATE_GENERAL_OBJECT = 0xa00, 257 MLX5_CMD_OP_MODIFY_GENERAL_OBJECT = 0xa01, 258 MLX5_CMD_OP_QUERY_GENERAL_OBJECT = 0xa02, 259 MLX5_CMD_OP_DESTROY_GENERAL_OBJECT = 0xa03, 260 MLX5_CMD_OP_MAX 261 }; 262 263 struct mlx5_ifc_flow_table_fields_supported_bits { 264 u8 outer_dmac[0x1]; 265 u8 outer_smac[0x1]; 266 u8 outer_ether_type[0x1]; 267 u8 outer_ip_version[0x1]; 268 u8 outer_first_prio[0x1]; 269 u8 outer_first_cfi[0x1]; 270 u8 outer_first_vid[0x1]; 271 u8 outer_ipv4_ttl[0x1]; 272 u8 outer_second_prio[0x1]; 273 u8 outer_second_cfi[0x1]; 274 u8 outer_second_vid[0x1]; 275 u8 reserved_at_b[0x1]; 276 u8 outer_sip[0x1]; 277 u8 outer_dip[0x1]; 278 u8 outer_frag[0x1]; 279 u8 outer_ip_protocol[0x1]; 280 u8 outer_ip_ecn[0x1]; 281 u8 outer_ip_dscp[0x1]; 282 u8 outer_udp_sport[0x1]; 283 u8 outer_udp_dport[0x1]; 284 u8 outer_tcp_sport[0x1]; 285 u8 outer_tcp_dport[0x1]; 286 u8 outer_tcp_flags[0x1]; 287 u8 outer_gre_protocol[0x1]; 288 u8 outer_gre_key[0x1]; 289 u8 outer_vxlan_vni[0x1]; 290 u8 reserved_at_1a[0x5]; 291 u8 source_eswitch_port[0x1]; 292 293 u8 inner_dmac[0x1]; 294 u8 inner_smac[0x1]; 295 u8 inner_ether_type[0x1]; 296 u8 inner_ip_version[0x1]; 297 u8 inner_first_prio[0x1]; 298 u8 inner_first_cfi[0x1]; 299 u8 inner_first_vid[0x1]; 300 u8 reserved_at_27[0x1]; 301 u8 inner_second_prio[0x1]; 302 u8 inner_second_cfi[0x1]; 303 u8 inner_second_vid[0x1]; 304 u8 reserved_at_2b[0x1]; 305 u8 inner_sip[0x1]; 306 u8 inner_dip[0x1]; 307 u8 inner_frag[0x1]; 308 u8 inner_ip_protocol[0x1]; 309 u8 inner_ip_ecn[0x1]; 310 u8 inner_ip_dscp[0x1]; 311 u8 inner_udp_sport[0x1]; 312 u8 inner_udp_dport[0x1]; 313 u8 inner_tcp_sport[0x1]; 314 u8 inner_tcp_dport[0x1]; 315 u8 inner_tcp_flags[0x1]; 316 u8 reserved_at_37[0x9]; 317 318 u8 reserved_at_40[0x5]; 319 u8 outer_first_mpls_over_udp[0x4]; 320 u8 outer_first_mpls_over_gre[0x4]; 321 u8 inner_first_mpls[0x4]; 322 u8 outer_first_mpls[0x4]; 323 u8 reserved_at_55[0x2]; 324 u8 outer_esp_spi[0x1]; 325 u8 reserved_at_58[0x2]; 326 u8 bth_dst_qp[0x1]; 327 328 u8 reserved_at_5b[0x25]; 329 }; 330 331 struct mlx5_ifc_flow_table_prop_layout_bits { 332 u8 ft_support[0x1]; 333 u8 reserved_at_1[0x1]; 334 u8 flow_counter[0x1]; 335 u8 flow_modify_en[0x1]; 336 u8 modify_root[0x1]; 337 u8 identified_miss_table_mode[0x1]; 338 u8 flow_table_modify[0x1]; 339 u8 reformat[0x1]; 340 u8 decap[0x1]; 341 u8 reserved_at_9[0x1]; 342 u8 pop_vlan[0x1]; 343 u8 push_vlan[0x1]; 344 u8 reserved_at_c[0x1]; 345 u8 pop_vlan_2[0x1]; 346 u8 push_vlan_2[0x1]; 347 u8 reformat_and_vlan_action[0x1]; 348 u8 reserved_at_10[0x2]; 349 u8 reformat_l3_tunnel_to_l2[0x1]; 350 u8 reformat_l2_to_l3_tunnel[0x1]; 351 u8 reformat_and_modify_action[0x1]; 352 u8 reserved_at_14[0xb]; 353 u8 reserved_at_20[0x2]; 354 u8 log_max_ft_size[0x6]; 355 u8 log_max_modify_header_context[0x8]; 356 u8 max_modify_header_actions[0x8]; 357 u8 max_ft_level[0x8]; 358 359 u8 reserved_at_40[0x20]; 360 361 u8 reserved_at_60[0x18]; 362 u8 log_max_ft_num[0x8]; 363 364 u8 reserved_at_80[0x18]; 365 u8 log_max_destination[0x8]; 366 367 u8 log_max_flow_counter[0x8]; 368 u8 reserved_at_a8[0x10]; 369 u8 log_max_flow[0x8]; 370 371 u8 reserved_at_c0[0x40]; 372 373 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support; 374 375 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support; 376 }; 377 378 struct mlx5_ifc_odp_per_transport_service_cap_bits { 379 u8 send[0x1]; 380 u8 receive[0x1]; 381 u8 write[0x1]; 382 u8 read[0x1]; 383 u8 atomic[0x1]; 384 u8 srq_receive[0x1]; 385 u8 reserved_at_6[0x1a]; 386 }; 387 388 struct mlx5_ifc_fte_match_set_lyr_2_4_bits { 389 u8 smac_47_16[0x20]; 390 391 u8 smac_15_0[0x10]; 392 u8 ethertype[0x10]; 393 394 u8 dmac_47_16[0x20]; 395 396 u8 dmac_15_0[0x10]; 397 u8 first_prio[0x3]; 398 u8 first_cfi[0x1]; 399 u8 first_vid[0xc]; 400 401 u8 ip_protocol[0x8]; 402 u8 ip_dscp[0x6]; 403 u8 ip_ecn[0x2]; 404 u8 cvlan_tag[0x1]; 405 u8 svlan_tag[0x1]; 406 u8 frag[0x1]; 407 u8 ip_version[0x4]; 408 u8 tcp_flags[0x9]; 409 410 u8 tcp_sport[0x10]; 411 u8 tcp_dport[0x10]; 412 413 u8 reserved_at_c0[0x18]; 414 u8 ttl_hoplimit[0x8]; 415 416 u8 udp_sport[0x10]; 417 u8 udp_dport[0x10]; 418 419 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6; 420 421 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6; 422 }; 423 424 struct mlx5_ifc_fte_match_set_misc_bits { 425 u8 reserved_at_0[0x8]; 426 u8 source_sqn[0x18]; 427 428 u8 source_eswitch_owner_vhca_id[0x10]; 429 u8 source_port[0x10]; 430 431 u8 outer_second_prio[0x3]; 432 u8 outer_second_cfi[0x1]; 433 u8 outer_second_vid[0xc]; 434 u8 inner_second_prio[0x3]; 435 u8 inner_second_cfi[0x1]; 436 u8 inner_second_vid[0xc]; 437 438 u8 outer_second_cvlan_tag[0x1]; 439 u8 inner_second_cvlan_tag[0x1]; 440 u8 outer_second_svlan_tag[0x1]; 441 u8 inner_second_svlan_tag[0x1]; 442 u8 reserved_at_64[0xc]; 443 u8 gre_protocol[0x10]; 444 445 u8 gre_key_h[0x18]; 446 u8 gre_key_l[0x8]; 447 448 u8 vxlan_vni[0x18]; 449 u8 reserved_at_b8[0x8]; 450 451 u8 reserved_at_c0[0x20]; 452 453 u8 reserved_at_e0[0xc]; 454 u8 outer_ipv6_flow_label[0x14]; 455 456 u8 reserved_at_100[0xc]; 457 u8 inner_ipv6_flow_label[0x14]; 458 459 u8 reserved_at_120[0x28]; 460 u8 bth_dst_qp[0x18]; 461 u8 reserved_at_160[0x20]; 462 u8 outer_esp_spi[0x20]; 463 u8 reserved_at_1a0[0x60]; 464 }; 465 466 struct mlx5_ifc_fte_match_mpls_bits { 467 u8 mpls_label[0x14]; 468 u8 mpls_exp[0x3]; 469 u8 mpls_s_bos[0x1]; 470 u8 mpls_ttl[0x8]; 471 }; 472 473 struct mlx5_ifc_fte_match_set_misc2_bits { 474 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls; 475 476 struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls; 477 478 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre; 479 480 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp; 481 482 u8 reserved_at_80[0x100]; 483 484 u8 metadata_reg_a[0x20]; 485 486 u8 reserved_at_1a0[0x60]; 487 }; 488 489 struct mlx5_ifc_cmd_pas_bits { 490 u8 pa_h[0x20]; 491 492 u8 pa_l[0x14]; 493 u8 reserved_at_34[0xc]; 494 }; 495 496 struct mlx5_ifc_uint64_bits { 497 u8 hi[0x20]; 498 499 u8 lo[0x20]; 500 }; 501 502 enum { 503 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0, 504 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7, 505 MLX5_ADS_STAT_RATE_10GBPS = 0x8, 506 MLX5_ADS_STAT_RATE_30GBPS = 0x9, 507 MLX5_ADS_STAT_RATE_5GBPS = 0xa, 508 MLX5_ADS_STAT_RATE_20GBPS = 0xb, 509 MLX5_ADS_STAT_RATE_40GBPS = 0xc, 510 MLX5_ADS_STAT_RATE_60GBPS = 0xd, 511 MLX5_ADS_STAT_RATE_80GBPS = 0xe, 512 MLX5_ADS_STAT_RATE_120GBPS = 0xf, 513 }; 514 515 struct mlx5_ifc_ads_bits { 516 u8 fl[0x1]; 517 u8 free_ar[0x1]; 518 u8 reserved_at_2[0xe]; 519 u8 pkey_index[0x10]; 520 521 u8 reserved_at_20[0x8]; 522 u8 grh[0x1]; 523 u8 mlid[0x7]; 524 u8 rlid[0x10]; 525 526 u8 ack_timeout[0x5]; 527 u8 reserved_at_45[0x3]; 528 u8 src_addr_index[0x8]; 529 u8 reserved_at_50[0x4]; 530 u8 stat_rate[0x4]; 531 u8 hop_limit[0x8]; 532 533 u8 reserved_at_60[0x4]; 534 u8 tclass[0x8]; 535 u8 flow_label[0x14]; 536 537 u8 rgid_rip[16][0x8]; 538 539 u8 reserved_at_100[0x4]; 540 u8 f_dscp[0x1]; 541 u8 f_ecn[0x1]; 542 u8 reserved_at_106[0x1]; 543 u8 f_eth_prio[0x1]; 544 u8 ecn[0x2]; 545 u8 dscp[0x6]; 546 u8 udp_sport[0x10]; 547 548 u8 dei_cfi[0x1]; 549 u8 eth_prio[0x3]; 550 u8 sl[0x4]; 551 u8 vhca_port_num[0x8]; 552 u8 rmac_47_32[0x10]; 553 554 u8 rmac_31_0[0x20]; 555 }; 556 557 struct mlx5_ifc_flow_table_nic_cap_bits { 558 u8 nic_rx_multi_path_tirs[0x1]; 559 u8 nic_rx_multi_path_tirs_fts[0x1]; 560 u8 allow_sniffer_and_nic_rx_shared_tir[0x1]; 561 u8 reserved_at_3[0x1d]; 562 u8 encap_general_header[0x1]; 563 u8 reserved_at_21[0xa]; 564 u8 log_max_packet_reformat_context[0x5]; 565 u8 reserved_at_30[0x6]; 566 u8 max_encap_header_size[0xa]; 567 u8 reserved_at_40[0x1c0]; 568 569 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive; 570 571 u8 reserved_at_400[0x200]; 572 573 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer; 574 575 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit; 576 577 u8 reserved_at_a00[0x200]; 578 579 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer; 580 581 u8 reserved_at_e00[0x7200]; 582 }; 583 584 struct mlx5_ifc_flow_table_eswitch_cap_bits { 585 u8 reserved_at_0[0x1a]; 586 u8 multi_fdb_encap[0x1]; 587 u8 reserved_at_1b[0x1]; 588 u8 fdb_multi_path_to_table[0x1]; 589 u8 reserved_at_1d[0x3]; 590 591 u8 reserved_at_20[0x1e0]; 592 593 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb; 594 595 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress; 596 597 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress; 598 599 u8 reserved_at_800[0x7800]; 600 }; 601 602 struct mlx5_ifc_e_switch_cap_bits { 603 u8 vport_svlan_strip[0x1]; 604 u8 vport_cvlan_strip[0x1]; 605 u8 vport_svlan_insert[0x1]; 606 u8 vport_cvlan_insert_if_not_exist[0x1]; 607 u8 vport_cvlan_insert_overwrite[0x1]; 608 u8 reserved_at_5[0x18]; 609 u8 merged_eswitch[0x1]; 610 u8 nic_vport_node_guid_modify[0x1]; 611 u8 nic_vport_port_guid_modify[0x1]; 612 613 u8 vxlan_encap_decap[0x1]; 614 u8 nvgre_encap_decap[0x1]; 615 u8 reserved_at_22[0x9]; 616 u8 log_max_packet_reformat_context[0x5]; 617 u8 reserved_2b[0x6]; 618 u8 max_encap_header_size[0xa]; 619 620 u8 reserved_40[0x7c0]; 621 622 }; 623 624 struct mlx5_ifc_qos_cap_bits { 625 u8 packet_pacing[0x1]; 626 u8 esw_scheduling[0x1]; 627 u8 esw_bw_share[0x1]; 628 u8 esw_rate_limit[0x1]; 629 u8 reserved_at_4[0x1]; 630 u8 packet_pacing_burst_bound[0x1]; 631 u8 packet_pacing_typical_size[0x1]; 632 u8 reserved_at_7[0x19]; 633 634 u8 reserved_at_20[0x20]; 635 636 u8 packet_pacing_max_rate[0x20]; 637 638 u8 packet_pacing_min_rate[0x20]; 639 640 u8 reserved_at_80[0x10]; 641 u8 packet_pacing_rate_table_size[0x10]; 642 643 u8 esw_element_type[0x10]; 644 u8 esw_tsar_type[0x10]; 645 646 u8 reserved_at_c0[0x10]; 647 u8 max_qos_para_vport[0x10]; 648 649 u8 max_tsar_bw_share[0x20]; 650 651 u8 reserved_at_100[0x700]; 652 }; 653 654 struct mlx5_ifc_debug_cap_bits { 655 u8 reserved_at_0[0x20]; 656 657 u8 reserved_at_20[0x2]; 658 u8 stall_detect[0x1]; 659 u8 reserved_at_23[0x1d]; 660 661 u8 reserved_at_40[0x7c0]; 662 }; 663 664 struct mlx5_ifc_per_protocol_networking_offload_caps_bits { 665 u8 csum_cap[0x1]; 666 u8 vlan_cap[0x1]; 667 u8 lro_cap[0x1]; 668 u8 lro_psh_flag[0x1]; 669 u8 lro_time_stamp[0x1]; 670 u8 reserved_at_5[0x2]; 671 u8 wqe_vlan_insert[0x1]; 672 u8 self_lb_en_modifiable[0x1]; 673 u8 reserved_at_9[0x2]; 674 u8 max_lso_cap[0x5]; 675 u8 multi_pkt_send_wqe[0x2]; 676 u8 wqe_inline_mode[0x2]; 677 u8 rss_ind_tbl_cap[0x4]; 678 u8 reg_umr_sq[0x1]; 679 u8 scatter_fcs[0x1]; 680 u8 enhanced_multi_pkt_send_wqe[0x1]; 681 u8 tunnel_lso_const_out_ip_id[0x1]; 682 u8 reserved_at_1c[0x2]; 683 u8 tunnel_stateless_gre[0x1]; 684 u8 tunnel_stateless_vxlan[0x1]; 685 686 u8 swp[0x1]; 687 u8 swp_csum[0x1]; 688 u8 swp_lso[0x1]; 689 u8 reserved_at_23[0xd]; 690 u8 max_vxlan_udp_ports[0x8]; 691 u8 reserved_at_38[0x6]; 692 u8 max_geneve_opt_len[0x1]; 693 u8 tunnel_stateless_geneve_rx[0x1]; 694 695 u8 reserved_at_40[0x10]; 696 u8 lro_min_mss_size[0x10]; 697 698 u8 reserved_at_60[0x120]; 699 700 u8 lro_timer_supported_periods[4][0x20]; 701 702 u8 reserved_at_200[0x600]; 703 }; 704 705 struct mlx5_ifc_roce_cap_bits { 706 u8 roce_apm[0x1]; 707 u8 reserved_at_1[0x1f]; 708 709 u8 reserved_at_20[0x60]; 710 711 u8 reserved_at_80[0xc]; 712 u8 l3_type[0x4]; 713 u8 reserved_at_90[0x8]; 714 u8 roce_version[0x8]; 715 716 u8 reserved_at_a0[0x10]; 717 u8 r_roce_dest_udp_port[0x10]; 718 719 u8 r_roce_max_src_udp_port[0x10]; 720 u8 r_roce_min_src_udp_port[0x10]; 721 722 u8 reserved_at_e0[0x10]; 723 u8 roce_address_table_size[0x10]; 724 725 u8 reserved_at_100[0x700]; 726 }; 727 728 struct mlx5_ifc_device_mem_cap_bits { 729 u8 memic[0x1]; 730 u8 reserved_at_1[0x1f]; 731 732 u8 reserved_at_20[0xb]; 733 u8 log_min_memic_alloc_size[0x5]; 734 u8 reserved_at_30[0x8]; 735 u8 log_max_memic_addr_alignment[0x8]; 736 737 u8 memic_bar_start_addr[0x40]; 738 739 u8 memic_bar_size[0x20]; 740 741 u8 max_memic_size[0x20]; 742 743 u8 reserved_at_c0[0x740]; 744 }; 745 746 enum { 747 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0, 748 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2, 749 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4, 750 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8, 751 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10, 752 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20, 753 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40, 754 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80, 755 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100, 756 }; 757 758 enum { 759 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1, 760 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2, 761 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4, 762 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8, 763 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10, 764 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20, 765 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40, 766 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80, 767 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100, 768 }; 769 770 struct mlx5_ifc_atomic_caps_bits { 771 u8 reserved_at_0[0x40]; 772 773 u8 atomic_req_8B_endianness_mode[0x2]; 774 u8 reserved_at_42[0x4]; 775 u8 supported_atomic_req_8B_endianness_mode_1[0x1]; 776 777 u8 reserved_at_47[0x19]; 778 779 u8 reserved_at_60[0x20]; 780 781 u8 reserved_at_80[0x10]; 782 u8 atomic_operations[0x10]; 783 784 u8 reserved_at_a0[0x10]; 785 u8 atomic_size_qp[0x10]; 786 787 u8 reserved_at_c0[0x10]; 788 u8 atomic_size_dc[0x10]; 789 790 u8 reserved_at_e0[0x720]; 791 }; 792 793 struct mlx5_ifc_odp_cap_bits { 794 u8 reserved_at_0[0x40]; 795 796 u8 sig[0x1]; 797 u8 reserved_at_41[0x1f]; 798 799 u8 reserved_at_60[0x20]; 800 801 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps; 802 803 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps; 804 805 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps; 806 807 u8 reserved_at_e0[0x720]; 808 }; 809 810 struct mlx5_ifc_calc_op { 811 u8 reserved_at_0[0x10]; 812 u8 reserved_at_10[0x9]; 813 u8 op_swap_endianness[0x1]; 814 u8 op_min[0x1]; 815 u8 op_xor[0x1]; 816 u8 op_or[0x1]; 817 u8 op_and[0x1]; 818 u8 op_max[0x1]; 819 u8 op_add[0x1]; 820 }; 821 822 struct mlx5_ifc_vector_calc_cap_bits { 823 u8 calc_matrix[0x1]; 824 u8 reserved_at_1[0x1f]; 825 u8 reserved_at_20[0x8]; 826 u8 max_vec_count[0x8]; 827 u8 reserved_at_30[0xd]; 828 u8 max_chunk_size[0x3]; 829 struct mlx5_ifc_calc_op calc0; 830 struct mlx5_ifc_calc_op calc1; 831 struct mlx5_ifc_calc_op calc2; 832 struct mlx5_ifc_calc_op calc3; 833 834 u8 reserved_at_e0[0x720]; 835 }; 836 837 enum { 838 MLX5_WQ_TYPE_LINKED_LIST = 0x0, 839 MLX5_WQ_TYPE_CYCLIC = 0x1, 840 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2, 841 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3, 842 }; 843 844 enum { 845 MLX5_WQ_END_PAD_MODE_NONE = 0x0, 846 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1, 847 }; 848 849 enum { 850 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0, 851 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1, 852 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2, 853 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3, 854 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4, 855 }; 856 857 enum { 858 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0, 859 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1, 860 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2, 861 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3, 862 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4, 863 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5, 864 }; 865 866 enum { 867 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0, 868 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1, 869 }; 870 871 enum { 872 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0, 873 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1, 874 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3, 875 }; 876 877 enum { 878 MLX5_CAP_PORT_TYPE_IB = 0x0, 879 MLX5_CAP_PORT_TYPE_ETH = 0x1, 880 }; 881 882 enum { 883 MLX5_CAP_UMR_FENCE_STRONG = 0x0, 884 MLX5_CAP_UMR_FENCE_SMALL = 0x1, 885 MLX5_CAP_UMR_FENCE_NONE = 0x2, 886 }; 887 888 struct mlx5_ifc_cmd_hca_cap_bits { 889 u8 reserved_at_0[0x30]; 890 u8 vhca_id[0x10]; 891 892 u8 reserved_at_40[0x40]; 893 894 u8 log_max_srq_sz[0x8]; 895 u8 log_max_qp_sz[0x8]; 896 u8 reserved_at_90[0xb]; 897 u8 log_max_qp[0x5]; 898 899 u8 reserved_at_a0[0xb]; 900 u8 log_max_srq[0x5]; 901 u8 reserved_at_b0[0x10]; 902 903 u8 reserved_at_c0[0x8]; 904 u8 log_max_cq_sz[0x8]; 905 u8 reserved_at_d0[0xb]; 906 u8 log_max_cq[0x5]; 907 908 u8 log_max_eq_sz[0x8]; 909 u8 reserved_at_e8[0x2]; 910 u8 log_max_mkey[0x6]; 911 u8 reserved_at_f0[0x8]; 912 u8 dump_fill_mkey[0x1]; 913 u8 reserved_at_f9[0x2]; 914 u8 fast_teardown[0x1]; 915 u8 log_max_eq[0x4]; 916 917 u8 max_indirection[0x8]; 918 u8 fixed_buffer_size[0x1]; 919 u8 log_max_mrw_sz[0x7]; 920 u8 force_teardown[0x1]; 921 u8 reserved_at_111[0x1]; 922 u8 log_max_bsf_list_size[0x6]; 923 u8 umr_extended_translation_offset[0x1]; 924 u8 null_mkey[0x1]; 925 u8 log_max_klm_list_size[0x6]; 926 927 u8 reserved_at_120[0xa]; 928 u8 log_max_ra_req_dc[0x6]; 929 u8 reserved_at_130[0xa]; 930 u8 log_max_ra_res_dc[0x6]; 931 932 u8 reserved_at_140[0xa]; 933 u8 log_max_ra_req_qp[0x6]; 934 u8 reserved_at_150[0xa]; 935 u8 log_max_ra_res_qp[0x6]; 936 937 u8 end_pad[0x1]; 938 u8 cc_query_allowed[0x1]; 939 u8 cc_modify_allowed[0x1]; 940 u8 start_pad[0x1]; 941 u8 cache_line_128byte[0x1]; 942 u8 reserved_at_165[0xa]; 943 u8 qcam_reg[0x1]; 944 u8 gid_table_size[0x10]; 945 946 u8 out_of_seq_cnt[0x1]; 947 u8 vport_counters[0x1]; 948 u8 retransmission_q_counters[0x1]; 949 u8 debug[0x1]; 950 u8 modify_rq_counter_set_id[0x1]; 951 u8 rq_delay_drop[0x1]; 952 u8 max_qp_cnt[0xa]; 953 u8 pkey_table_size[0x10]; 954 955 u8 vport_group_manager[0x1]; 956 u8 vhca_group_manager[0x1]; 957 u8 ib_virt[0x1]; 958 u8 eth_virt[0x1]; 959 u8 vnic_env_queue_counters[0x1]; 960 u8 ets[0x1]; 961 u8 nic_flow_table[0x1]; 962 u8 eswitch_manager[0x1]; 963 u8 device_memory[0x1]; 964 u8 mcam_reg[0x1]; 965 u8 pcam_reg[0x1]; 966 u8 local_ca_ack_delay[0x5]; 967 u8 port_module_event[0x1]; 968 u8 enhanced_error_q_counters[0x1]; 969 u8 ports_check[0x1]; 970 u8 reserved_at_1b3[0x1]; 971 u8 disable_link_up[0x1]; 972 u8 beacon_led[0x1]; 973 u8 port_type[0x2]; 974 u8 num_ports[0x8]; 975 976 u8 reserved_at_1c0[0x1]; 977 u8 pps[0x1]; 978 u8 pps_modify[0x1]; 979 u8 log_max_msg[0x5]; 980 u8 reserved_at_1c8[0x4]; 981 u8 max_tc[0x4]; 982 u8 temp_warn_event[0x1]; 983 u8 dcbx[0x1]; 984 u8 general_notification_event[0x1]; 985 u8 reserved_at_1d3[0x2]; 986 u8 fpga[0x1]; 987 u8 rol_s[0x1]; 988 u8 rol_g[0x1]; 989 u8 reserved_at_1d8[0x1]; 990 u8 wol_s[0x1]; 991 u8 wol_g[0x1]; 992 u8 wol_a[0x1]; 993 u8 wol_b[0x1]; 994 u8 wol_m[0x1]; 995 u8 wol_u[0x1]; 996 u8 wol_p[0x1]; 997 998 u8 stat_rate_support[0x10]; 999 u8 reserved_at_1f0[0xc]; 1000 u8 cqe_version[0x4]; 1001 1002 u8 compact_address_vector[0x1]; 1003 u8 striding_rq[0x1]; 1004 u8 reserved_at_202[0x1]; 1005 u8 ipoib_enhanced_offloads[0x1]; 1006 u8 ipoib_basic_offloads[0x1]; 1007 u8 reserved_at_205[0x1]; 1008 u8 repeated_block_disabled[0x1]; 1009 u8 umr_modify_entity_size_disabled[0x1]; 1010 u8 umr_modify_atomic_disabled[0x1]; 1011 u8 umr_indirect_mkey_disabled[0x1]; 1012 u8 umr_fence[0x2]; 1013 u8 dc_req_scat_data_cqe[0x1]; 1014 u8 reserved_at_20d[0x2]; 1015 u8 drain_sigerr[0x1]; 1016 u8 cmdif_checksum[0x2]; 1017 u8 sigerr_cqe[0x1]; 1018 u8 reserved_at_213[0x1]; 1019 u8 wq_signature[0x1]; 1020 u8 sctr_data_cqe[0x1]; 1021 u8 reserved_at_216[0x1]; 1022 u8 sho[0x1]; 1023 u8 tph[0x1]; 1024 u8 rf[0x1]; 1025 u8 dct[0x1]; 1026 u8 qos[0x1]; 1027 u8 eth_net_offloads[0x1]; 1028 u8 roce[0x1]; 1029 u8 atomic[0x1]; 1030 u8 reserved_at_21f[0x1]; 1031 1032 u8 cq_oi[0x1]; 1033 u8 cq_resize[0x1]; 1034 u8 cq_moderation[0x1]; 1035 u8 reserved_at_223[0x3]; 1036 u8 cq_eq_remap[0x1]; 1037 u8 pg[0x1]; 1038 u8 block_lb_mc[0x1]; 1039 u8 reserved_at_229[0x1]; 1040 u8 scqe_break_moderation[0x1]; 1041 u8 cq_period_start_from_cqe[0x1]; 1042 u8 cd[0x1]; 1043 u8 reserved_at_22d[0x1]; 1044 u8 apm[0x1]; 1045 u8 vector_calc[0x1]; 1046 u8 umr_ptr_rlky[0x1]; 1047 u8 imaicl[0x1]; 1048 u8 reserved_at_232[0x4]; 1049 u8 qkv[0x1]; 1050 u8 pkv[0x1]; 1051 u8 set_deth_sqpn[0x1]; 1052 u8 reserved_at_239[0x3]; 1053 u8 xrc[0x1]; 1054 u8 ud[0x1]; 1055 u8 uc[0x1]; 1056 u8 rc[0x1]; 1057 1058 u8 uar_4k[0x1]; 1059 u8 reserved_at_241[0x9]; 1060 u8 uar_sz[0x6]; 1061 u8 reserved_at_250[0x8]; 1062 u8 log_pg_sz[0x8]; 1063 1064 u8 bf[0x1]; 1065 u8 driver_version[0x1]; 1066 u8 pad_tx_eth_packet[0x1]; 1067 u8 reserved_at_263[0x8]; 1068 u8 log_bf_reg_size[0x5]; 1069 1070 u8 reserved_at_270[0xb]; 1071 u8 lag_master[0x1]; 1072 u8 num_lag_ports[0x4]; 1073 1074 u8 reserved_at_280[0x10]; 1075 u8 max_wqe_sz_sq[0x10]; 1076 1077 u8 reserved_at_2a0[0x10]; 1078 u8 max_wqe_sz_rq[0x10]; 1079 1080 u8 max_flow_counter_31_16[0x10]; 1081 u8 max_wqe_sz_sq_dc[0x10]; 1082 1083 u8 reserved_at_2e0[0x7]; 1084 u8 max_qp_mcg[0x19]; 1085 1086 u8 reserved_at_300[0x18]; 1087 u8 log_max_mcg[0x8]; 1088 1089 u8 reserved_at_320[0x3]; 1090 u8 log_max_transport_domain[0x5]; 1091 u8 reserved_at_328[0x3]; 1092 u8 log_max_pd[0x5]; 1093 u8 reserved_at_330[0xb]; 1094 u8 log_max_xrcd[0x5]; 1095 1096 u8 nic_receive_steering_discard[0x1]; 1097 u8 receive_discard_vport_down[0x1]; 1098 u8 transmit_discard_vport_down[0x1]; 1099 u8 reserved_at_343[0x5]; 1100 u8 log_max_flow_counter_bulk[0x8]; 1101 u8 max_flow_counter_15_0[0x10]; 1102 1103 1104 u8 reserved_at_360[0x3]; 1105 u8 log_max_rq[0x5]; 1106 u8 reserved_at_368[0x3]; 1107 u8 log_max_sq[0x5]; 1108 u8 reserved_at_370[0x3]; 1109 u8 log_max_tir[0x5]; 1110 u8 reserved_at_378[0x3]; 1111 u8 log_max_tis[0x5]; 1112 1113 u8 basic_cyclic_rcv_wqe[0x1]; 1114 u8 reserved_at_381[0x2]; 1115 u8 log_max_rmp[0x5]; 1116 u8 reserved_at_388[0x3]; 1117 u8 log_max_rqt[0x5]; 1118 u8 reserved_at_390[0x3]; 1119 u8 log_max_rqt_size[0x5]; 1120 u8 reserved_at_398[0x3]; 1121 u8 log_max_tis_per_sq[0x5]; 1122 1123 u8 ext_stride_num_range[0x1]; 1124 u8 reserved_at_3a1[0x2]; 1125 u8 log_max_stride_sz_rq[0x5]; 1126 u8 reserved_at_3a8[0x3]; 1127 u8 log_min_stride_sz_rq[0x5]; 1128 u8 reserved_at_3b0[0x3]; 1129 u8 log_max_stride_sz_sq[0x5]; 1130 u8 reserved_at_3b8[0x3]; 1131 u8 log_min_stride_sz_sq[0x5]; 1132 1133 u8 hairpin[0x1]; 1134 u8 reserved_at_3c1[0x2]; 1135 u8 log_max_hairpin_queues[0x5]; 1136 u8 reserved_at_3c8[0x3]; 1137 u8 log_max_hairpin_wq_data_sz[0x5]; 1138 u8 reserved_at_3d0[0x3]; 1139 u8 log_max_hairpin_num_packets[0x5]; 1140 u8 reserved_at_3d8[0x3]; 1141 u8 log_max_wq_sz[0x5]; 1142 1143 u8 nic_vport_change_event[0x1]; 1144 u8 disable_local_lb_uc[0x1]; 1145 u8 disable_local_lb_mc[0x1]; 1146 u8 log_min_hairpin_wq_data_sz[0x5]; 1147 u8 reserved_at_3e8[0x3]; 1148 u8 log_max_vlan_list[0x5]; 1149 u8 reserved_at_3f0[0x3]; 1150 u8 log_max_current_mc_list[0x5]; 1151 u8 reserved_at_3f8[0x3]; 1152 u8 log_max_current_uc_list[0x5]; 1153 1154 u8 general_obj_types[0x40]; 1155 1156 u8 reserved_at_440[0x20]; 1157 1158 u8 reserved_at_460[0x10]; 1159 u8 max_num_eqs[0x10]; 1160 1161 u8 reserved_at_480[0x3]; 1162 u8 log_max_l2_table[0x5]; 1163 u8 reserved_at_488[0x8]; 1164 u8 log_uar_page_sz[0x10]; 1165 1166 u8 reserved_at_4a0[0x20]; 1167 u8 device_frequency_mhz[0x20]; 1168 u8 device_frequency_khz[0x20]; 1169 1170 u8 reserved_at_500[0x20]; 1171 u8 num_of_uars_per_page[0x20]; 1172 1173 u8 flex_parser_protocols[0x20]; 1174 u8 reserved_at_560[0x20]; 1175 1176 u8 reserved_at_580[0x3c]; 1177 u8 mini_cqe_resp_stride_index[0x1]; 1178 u8 cqe_128_always[0x1]; 1179 u8 cqe_compression_128[0x1]; 1180 u8 cqe_compression[0x1]; 1181 1182 u8 cqe_compression_timeout[0x10]; 1183 u8 cqe_compression_max_num[0x10]; 1184 1185 u8 reserved_at_5e0[0x10]; 1186 u8 tag_matching[0x1]; 1187 u8 rndv_offload_rc[0x1]; 1188 u8 rndv_offload_dc[0x1]; 1189 u8 log_tag_matching_list_sz[0x5]; 1190 u8 reserved_at_5f8[0x3]; 1191 u8 log_max_xrq[0x5]; 1192 1193 u8 affiliate_nic_vport_criteria[0x8]; 1194 u8 native_port_num[0x8]; 1195 u8 num_vhca_ports[0x8]; 1196 u8 reserved_at_618[0x6]; 1197 u8 sw_owner_id[0x1]; 1198 u8 reserved_at_61f[0x1e1]; 1199 }; 1200 1201 enum mlx5_flow_destination_type { 1202 MLX5_FLOW_DESTINATION_TYPE_VPORT = 0x0, 1203 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1, 1204 MLX5_FLOW_DESTINATION_TYPE_TIR = 0x2, 1205 1206 MLX5_FLOW_DESTINATION_TYPE_PORT = 0x99, 1207 MLX5_FLOW_DESTINATION_TYPE_COUNTER = 0x100, 1208 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE_NUM = 0x101, 1209 }; 1210 1211 struct mlx5_ifc_dest_format_struct_bits { 1212 u8 destination_type[0x8]; 1213 u8 destination_id[0x18]; 1214 u8 destination_eswitch_owner_vhca_id_valid[0x1]; 1215 u8 reserved_at_21[0xf]; 1216 u8 destination_eswitch_owner_vhca_id[0x10]; 1217 }; 1218 1219 struct mlx5_ifc_flow_counter_list_bits { 1220 u8 flow_counter_id[0x20]; 1221 1222 u8 reserved_at_20[0x20]; 1223 }; 1224 1225 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits { 1226 struct mlx5_ifc_dest_format_struct_bits dest_format_struct; 1227 struct mlx5_ifc_flow_counter_list_bits flow_counter_list; 1228 u8 reserved_at_0[0x40]; 1229 }; 1230 1231 struct mlx5_ifc_fte_match_param_bits { 1232 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers; 1233 1234 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters; 1235 1236 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers; 1237 1238 struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2; 1239 1240 u8 reserved_at_800[0x800]; 1241 }; 1242 1243 enum { 1244 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0, 1245 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1, 1246 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2, 1247 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3, 1248 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4, 1249 }; 1250 1251 struct mlx5_ifc_rx_hash_field_select_bits { 1252 u8 l3_prot_type[0x1]; 1253 u8 l4_prot_type[0x1]; 1254 u8 selected_fields[0x1e]; 1255 }; 1256 1257 enum { 1258 MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0, 1259 MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1, 1260 }; 1261 1262 enum { 1263 MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0, 1264 MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1, 1265 }; 1266 1267 struct mlx5_ifc_wq_bits { 1268 u8 wq_type[0x4]; 1269 u8 wq_signature[0x1]; 1270 u8 end_padding_mode[0x2]; 1271 u8 cd_slave[0x1]; 1272 u8 reserved_at_8[0x18]; 1273 1274 u8 hds_skip_first_sge[0x1]; 1275 u8 log2_hds_buf_size[0x3]; 1276 u8 reserved_at_24[0x7]; 1277 u8 page_offset[0x5]; 1278 u8 lwm[0x10]; 1279 1280 u8 reserved_at_40[0x8]; 1281 u8 pd[0x18]; 1282 1283 u8 reserved_at_60[0x8]; 1284 u8 uar_page[0x18]; 1285 1286 u8 dbr_addr[0x40]; 1287 1288 u8 hw_counter[0x20]; 1289 1290 u8 sw_counter[0x20]; 1291 1292 u8 reserved_at_100[0xc]; 1293 u8 log_wq_stride[0x4]; 1294 u8 reserved_at_110[0x3]; 1295 u8 log_wq_pg_sz[0x5]; 1296 u8 reserved_at_118[0x3]; 1297 u8 log_wq_sz[0x5]; 1298 1299 u8 dbr_umem_valid[0x1]; 1300 u8 wq_umem_valid[0x1]; 1301 u8 reserved_at_122[0x1]; 1302 u8 log_hairpin_num_packets[0x5]; 1303 u8 reserved_at_128[0x3]; 1304 u8 log_hairpin_data_sz[0x5]; 1305 1306 u8 reserved_at_130[0x4]; 1307 u8 log_wqe_num_of_strides[0x4]; 1308 u8 two_byte_shift_en[0x1]; 1309 u8 reserved_at_139[0x4]; 1310 u8 log_wqe_stride_size[0x3]; 1311 1312 u8 reserved_at_140[0x4c0]; 1313 1314 struct mlx5_ifc_cmd_pas_bits pas[0]; 1315 }; 1316 1317 struct mlx5_ifc_rq_num_bits { 1318 u8 reserved_at_0[0x8]; 1319 u8 rq_num[0x18]; 1320 }; 1321 1322 struct mlx5_ifc_mac_address_layout_bits { 1323 u8 reserved_at_0[0x10]; 1324 u8 mac_addr_47_32[0x10]; 1325 1326 u8 mac_addr_31_0[0x20]; 1327 }; 1328 1329 struct mlx5_ifc_vlan_layout_bits { 1330 u8 reserved_at_0[0x14]; 1331 u8 vlan[0x0c]; 1332 1333 u8 reserved_at_20[0x20]; 1334 }; 1335 1336 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits { 1337 u8 reserved_at_0[0xa0]; 1338 1339 u8 min_time_between_cnps[0x20]; 1340 1341 u8 reserved_at_c0[0x12]; 1342 u8 cnp_dscp[0x6]; 1343 u8 reserved_at_d8[0x4]; 1344 u8 cnp_prio_mode[0x1]; 1345 u8 cnp_802p_prio[0x3]; 1346 1347 u8 reserved_at_e0[0x720]; 1348 }; 1349 1350 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits { 1351 u8 reserved_at_0[0x60]; 1352 1353 u8 reserved_at_60[0x4]; 1354 u8 clamp_tgt_rate[0x1]; 1355 u8 reserved_at_65[0x3]; 1356 u8 clamp_tgt_rate_after_time_inc[0x1]; 1357 u8 reserved_at_69[0x17]; 1358 1359 u8 reserved_at_80[0x20]; 1360 1361 u8 rpg_time_reset[0x20]; 1362 1363 u8 rpg_byte_reset[0x20]; 1364 1365 u8 rpg_threshold[0x20]; 1366 1367 u8 rpg_max_rate[0x20]; 1368 1369 u8 rpg_ai_rate[0x20]; 1370 1371 u8 rpg_hai_rate[0x20]; 1372 1373 u8 rpg_gd[0x20]; 1374 1375 u8 rpg_min_dec_fac[0x20]; 1376 1377 u8 rpg_min_rate[0x20]; 1378 1379 u8 reserved_at_1c0[0xe0]; 1380 1381 u8 rate_to_set_on_first_cnp[0x20]; 1382 1383 u8 dce_tcp_g[0x20]; 1384 1385 u8 dce_tcp_rtt[0x20]; 1386 1387 u8 rate_reduce_monitor_period[0x20]; 1388 1389 u8 reserved_at_320[0x20]; 1390 1391 u8 initial_alpha_value[0x20]; 1392 1393 u8 reserved_at_360[0x4a0]; 1394 }; 1395 1396 struct mlx5_ifc_cong_control_802_1qau_rp_bits { 1397 u8 reserved_at_0[0x80]; 1398 1399 u8 rppp_max_rps[0x20]; 1400 1401 u8 rpg_time_reset[0x20]; 1402 1403 u8 rpg_byte_reset[0x20]; 1404 1405 u8 rpg_threshold[0x20]; 1406 1407 u8 rpg_max_rate[0x20]; 1408 1409 u8 rpg_ai_rate[0x20]; 1410 1411 u8 rpg_hai_rate[0x20]; 1412 1413 u8 rpg_gd[0x20]; 1414 1415 u8 rpg_min_dec_fac[0x20]; 1416 1417 u8 rpg_min_rate[0x20]; 1418 1419 u8 reserved_at_1c0[0x640]; 1420 }; 1421 1422 enum { 1423 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1, 1424 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2, 1425 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4, 1426 }; 1427 1428 struct mlx5_ifc_resize_field_select_bits { 1429 u8 resize_field_select[0x20]; 1430 }; 1431 1432 enum { 1433 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1, 1434 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2, 1435 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4, 1436 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8, 1437 }; 1438 1439 struct mlx5_ifc_modify_field_select_bits { 1440 u8 modify_field_select[0x20]; 1441 }; 1442 1443 struct mlx5_ifc_field_select_r_roce_np_bits { 1444 u8 field_select_r_roce_np[0x20]; 1445 }; 1446 1447 struct mlx5_ifc_field_select_r_roce_rp_bits { 1448 u8 field_select_r_roce_rp[0x20]; 1449 }; 1450 1451 enum { 1452 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4, 1453 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8, 1454 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10, 1455 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20, 1456 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40, 1457 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80, 1458 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100, 1459 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200, 1460 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400, 1461 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800, 1462 }; 1463 1464 struct mlx5_ifc_field_select_802_1qau_rp_bits { 1465 u8 field_select_8021qaurp[0x20]; 1466 }; 1467 1468 struct mlx5_ifc_phys_layer_cntrs_bits { 1469 u8 time_since_last_clear_high[0x20]; 1470 1471 u8 time_since_last_clear_low[0x20]; 1472 1473 u8 symbol_errors_high[0x20]; 1474 1475 u8 symbol_errors_low[0x20]; 1476 1477 u8 sync_headers_errors_high[0x20]; 1478 1479 u8 sync_headers_errors_low[0x20]; 1480 1481 u8 edpl_bip_errors_lane0_high[0x20]; 1482 1483 u8 edpl_bip_errors_lane0_low[0x20]; 1484 1485 u8 edpl_bip_errors_lane1_high[0x20]; 1486 1487 u8 edpl_bip_errors_lane1_low[0x20]; 1488 1489 u8 edpl_bip_errors_lane2_high[0x20]; 1490 1491 u8 edpl_bip_errors_lane2_low[0x20]; 1492 1493 u8 edpl_bip_errors_lane3_high[0x20]; 1494 1495 u8 edpl_bip_errors_lane3_low[0x20]; 1496 1497 u8 fc_fec_corrected_blocks_lane0_high[0x20]; 1498 1499 u8 fc_fec_corrected_blocks_lane0_low[0x20]; 1500 1501 u8 fc_fec_corrected_blocks_lane1_high[0x20]; 1502 1503 u8 fc_fec_corrected_blocks_lane1_low[0x20]; 1504 1505 u8 fc_fec_corrected_blocks_lane2_high[0x20]; 1506 1507 u8 fc_fec_corrected_blocks_lane2_low[0x20]; 1508 1509 u8 fc_fec_corrected_blocks_lane3_high[0x20]; 1510 1511 u8 fc_fec_corrected_blocks_lane3_low[0x20]; 1512 1513 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20]; 1514 1515 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20]; 1516 1517 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20]; 1518 1519 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20]; 1520 1521 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20]; 1522 1523 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20]; 1524 1525 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20]; 1526 1527 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20]; 1528 1529 u8 rs_fec_corrected_blocks_high[0x20]; 1530 1531 u8 rs_fec_corrected_blocks_low[0x20]; 1532 1533 u8 rs_fec_uncorrectable_blocks_high[0x20]; 1534 1535 u8 rs_fec_uncorrectable_blocks_low[0x20]; 1536 1537 u8 rs_fec_no_errors_blocks_high[0x20]; 1538 1539 u8 rs_fec_no_errors_blocks_low[0x20]; 1540 1541 u8 rs_fec_single_error_blocks_high[0x20]; 1542 1543 u8 rs_fec_single_error_blocks_low[0x20]; 1544 1545 u8 rs_fec_corrected_symbols_total_high[0x20]; 1546 1547 u8 rs_fec_corrected_symbols_total_low[0x20]; 1548 1549 u8 rs_fec_corrected_symbols_lane0_high[0x20]; 1550 1551 u8 rs_fec_corrected_symbols_lane0_low[0x20]; 1552 1553 u8 rs_fec_corrected_symbols_lane1_high[0x20]; 1554 1555 u8 rs_fec_corrected_symbols_lane1_low[0x20]; 1556 1557 u8 rs_fec_corrected_symbols_lane2_high[0x20]; 1558 1559 u8 rs_fec_corrected_symbols_lane2_low[0x20]; 1560 1561 u8 rs_fec_corrected_symbols_lane3_high[0x20]; 1562 1563 u8 rs_fec_corrected_symbols_lane3_low[0x20]; 1564 1565 u8 link_down_events[0x20]; 1566 1567 u8 successful_recovery_events[0x20]; 1568 1569 u8 reserved_at_640[0x180]; 1570 }; 1571 1572 struct mlx5_ifc_phys_layer_statistical_cntrs_bits { 1573 u8 time_since_last_clear_high[0x20]; 1574 1575 u8 time_since_last_clear_low[0x20]; 1576 1577 u8 phy_received_bits_high[0x20]; 1578 1579 u8 phy_received_bits_low[0x20]; 1580 1581 u8 phy_symbol_errors_high[0x20]; 1582 1583 u8 phy_symbol_errors_low[0x20]; 1584 1585 u8 phy_corrected_bits_high[0x20]; 1586 1587 u8 phy_corrected_bits_low[0x20]; 1588 1589 u8 phy_corrected_bits_lane0_high[0x20]; 1590 1591 u8 phy_corrected_bits_lane0_low[0x20]; 1592 1593 u8 phy_corrected_bits_lane1_high[0x20]; 1594 1595 u8 phy_corrected_bits_lane1_low[0x20]; 1596 1597 u8 phy_corrected_bits_lane2_high[0x20]; 1598 1599 u8 phy_corrected_bits_lane2_low[0x20]; 1600 1601 u8 phy_corrected_bits_lane3_high[0x20]; 1602 1603 u8 phy_corrected_bits_lane3_low[0x20]; 1604 1605 u8 reserved_at_200[0x5c0]; 1606 }; 1607 1608 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits { 1609 u8 symbol_error_counter[0x10]; 1610 1611 u8 link_error_recovery_counter[0x8]; 1612 1613 u8 link_downed_counter[0x8]; 1614 1615 u8 port_rcv_errors[0x10]; 1616 1617 u8 port_rcv_remote_physical_errors[0x10]; 1618 1619 u8 port_rcv_switch_relay_errors[0x10]; 1620 1621 u8 port_xmit_discards[0x10]; 1622 1623 u8 port_xmit_constraint_errors[0x8]; 1624 1625 u8 port_rcv_constraint_errors[0x8]; 1626 1627 u8 reserved_at_70[0x8]; 1628 1629 u8 link_overrun_errors[0x8]; 1630 1631 u8 reserved_at_80[0x10]; 1632 1633 u8 vl_15_dropped[0x10]; 1634 1635 u8 reserved_at_a0[0x80]; 1636 1637 u8 port_xmit_wait[0x20]; 1638 }; 1639 1640 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits { 1641 u8 transmit_queue_high[0x20]; 1642 1643 u8 transmit_queue_low[0x20]; 1644 1645 u8 reserved_at_40[0x780]; 1646 }; 1647 1648 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits { 1649 u8 rx_octets_high[0x20]; 1650 1651 u8 rx_octets_low[0x20]; 1652 1653 u8 reserved_at_40[0xc0]; 1654 1655 u8 rx_frames_high[0x20]; 1656 1657 u8 rx_frames_low[0x20]; 1658 1659 u8 tx_octets_high[0x20]; 1660 1661 u8 tx_octets_low[0x20]; 1662 1663 u8 reserved_at_180[0xc0]; 1664 1665 u8 tx_frames_high[0x20]; 1666 1667 u8 tx_frames_low[0x20]; 1668 1669 u8 rx_pause_high[0x20]; 1670 1671 u8 rx_pause_low[0x20]; 1672 1673 u8 rx_pause_duration_high[0x20]; 1674 1675 u8 rx_pause_duration_low[0x20]; 1676 1677 u8 tx_pause_high[0x20]; 1678 1679 u8 tx_pause_low[0x20]; 1680 1681 u8 tx_pause_duration_high[0x20]; 1682 1683 u8 tx_pause_duration_low[0x20]; 1684 1685 u8 rx_pause_transition_high[0x20]; 1686 1687 u8 rx_pause_transition_low[0x20]; 1688 1689 u8 reserved_at_3c0[0x40]; 1690 1691 u8 device_stall_minor_watermark_cnt_high[0x20]; 1692 1693 u8 device_stall_minor_watermark_cnt_low[0x20]; 1694 1695 u8 device_stall_critical_watermark_cnt_high[0x20]; 1696 1697 u8 device_stall_critical_watermark_cnt_low[0x20]; 1698 1699 u8 reserved_at_480[0x340]; 1700 }; 1701 1702 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits { 1703 u8 port_transmit_wait_high[0x20]; 1704 1705 u8 port_transmit_wait_low[0x20]; 1706 1707 u8 reserved_at_40[0x100]; 1708 1709 u8 rx_buffer_almost_full_high[0x20]; 1710 1711 u8 rx_buffer_almost_full_low[0x20]; 1712 1713 u8 rx_buffer_full_high[0x20]; 1714 1715 u8 rx_buffer_full_low[0x20]; 1716 1717 u8 rx_icrc_encapsulated_high[0x20]; 1718 1719 u8 rx_icrc_encapsulated_low[0x20]; 1720 1721 u8 reserved_at_200[0x5c0]; 1722 }; 1723 1724 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits { 1725 u8 dot3stats_alignment_errors_high[0x20]; 1726 1727 u8 dot3stats_alignment_errors_low[0x20]; 1728 1729 u8 dot3stats_fcs_errors_high[0x20]; 1730 1731 u8 dot3stats_fcs_errors_low[0x20]; 1732 1733 u8 dot3stats_single_collision_frames_high[0x20]; 1734 1735 u8 dot3stats_single_collision_frames_low[0x20]; 1736 1737 u8 dot3stats_multiple_collision_frames_high[0x20]; 1738 1739 u8 dot3stats_multiple_collision_frames_low[0x20]; 1740 1741 u8 dot3stats_sqe_test_errors_high[0x20]; 1742 1743 u8 dot3stats_sqe_test_errors_low[0x20]; 1744 1745 u8 dot3stats_deferred_transmissions_high[0x20]; 1746 1747 u8 dot3stats_deferred_transmissions_low[0x20]; 1748 1749 u8 dot3stats_late_collisions_high[0x20]; 1750 1751 u8 dot3stats_late_collisions_low[0x20]; 1752 1753 u8 dot3stats_excessive_collisions_high[0x20]; 1754 1755 u8 dot3stats_excessive_collisions_low[0x20]; 1756 1757 u8 dot3stats_internal_mac_transmit_errors_high[0x20]; 1758 1759 u8 dot3stats_internal_mac_transmit_errors_low[0x20]; 1760 1761 u8 dot3stats_carrier_sense_errors_high[0x20]; 1762 1763 u8 dot3stats_carrier_sense_errors_low[0x20]; 1764 1765 u8 dot3stats_frame_too_longs_high[0x20]; 1766 1767 u8 dot3stats_frame_too_longs_low[0x20]; 1768 1769 u8 dot3stats_internal_mac_receive_errors_high[0x20]; 1770 1771 u8 dot3stats_internal_mac_receive_errors_low[0x20]; 1772 1773 u8 dot3stats_symbol_errors_high[0x20]; 1774 1775 u8 dot3stats_symbol_errors_low[0x20]; 1776 1777 u8 dot3control_in_unknown_opcodes_high[0x20]; 1778 1779 u8 dot3control_in_unknown_opcodes_low[0x20]; 1780 1781 u8 dot3in_pause_frames_high[0x20]; 1782 1783 u8 dot3in_pause_frames_low[0x20]; 1784 1785 u8 dot3out_pause_frames_high[0x20]; 1786 1787 u8 dot3out_pause_frames_low[0x20]; 1788 1789 u8 reserved_at_400[0x3c0]; 1790 }; 1791 1792 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits { 1793 u8 ether_stats_drop_events_high[0x20]; 1794 1795 u8 ether_stats_drop_events_low[0x20]; 1796 1797 u8 ether_stats_octets_high[0x20]; 1798 1799 u8 ether_stats_octets_low[0x20]; 1800 1801 u8 ether_stats_pkts_high[0x20]; 1802 1803 u8 ether_stats_pkts_low[0x20]; 1804 1805 u8 ether_stats_broadcast_pkts_high[0x20]; 1806 1807 u8 ether_stats_broadcast_pkts_low[0x20]; 1808 1809 u8 ether_stats_multicast_pkts_high[0x20]; 1810 1811 u8 ether_stats_multicast_pkts_low[0x20]; 1812 1813 u8 ether_stats_crc_align_errors_high[0x20]; 1814 1815 u8 ether_stats_crc_align_errors_low[0x20]; 1816 1817 u8 ether_stats_undersize_pkts_high[0x20]; 1818 1819 u8 ether_stats_undersize_pkts_low[0x20]; 1820 1821 u8 ether_stats_oversize_pkts_high[0x20]; 1822 1823 u8 ether_stats_oversize_pkts_low[0x20]; 1824 1825 u8 ether_stats_fragments_high[0x20]; 1826 1827 u8 ether_stats_fragments_low[0x20]; 1828 1829 u8 ether_stats_jabbers_high[0x20]; 1830 1831 u8 ether_stats_jabbers_low[0x20]; 1832 1833 u8 ether_stats_collisions_high[0x20]; 1834 1835 u8 ether_stats_collisions_low[0x20]; 1836 1837 u8 ether_stats_pkts64octets_high[0x20]; 1838 1839 u8 ether_stats_pkts64octets_low[0x20]; 1840 1841 u8 ether_stats_pkts65to127octets_high[0x20]; 1842 1843 u8 ether_stats_pkts65to127octets_low[0x20]; 1844 1845 u8 ether_stats_pkts128to255octets_high[0x20]; 1846 1847 u8 ether_stats_pkts128to255octets_low[0x20]; 1848 1849 u8 ether_stats_pkts256to511octets_high[0x20]; 1850 1851 u8 ether_stats_pkts256to511octets_low[0x20]; 1852 1853 u8 ether_stats_pkts512to1023octets_high[0x20]; 1854 1855 u8 ether_stats_pkts512to1023octets_low[0x20]; 1856 1857 u8 ether_stats_pkts1024to1518octets_high[0x20]; 1858 1859 u8 ether_stats_pkts1024to1518octets_low[0x20]; 1860 1861 u8 ether_stats_pkts1519to2047octets_high[0x20]; 1862 1863 u8 ether_stats_pkts1519to2047octets_low[0x20]; 1864 1865 u8 ether_stats_pkts2048to4095octets_high[0x20]; 1866 1867 u8 ether_stats_pkts2048to4095octets_low[0x20]; 1868 1869 u8 ether_stats_pkts4096to8191octets_high[0x20]; 1870 1871 u8 ether_stats_pkts4096to8191octets_low[0x20]; 1872 1873 u8 ether_stats_pkts8192to10239octets_high[0x20]; 1874 1875 u8 ether_stats_pkts8192to10239octets_low[0x20]; 1876 1877 u8 reserved_at_540[0x280]; 1878 }; 1879 1880 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits { 1881 u8 if_in_octets_high[0x20]; 1882 1883 u8 if_in_octets_low[0x20]; 1884 1885 u8 if_in_ucast_pkts_high[0x20]; 1886 1887 u8 if_in_ucast_pkts_low[0x20]; 1888 1889 u8 if_in_discards_high[0x20]; 1890 1891 u8 if_in_discards_low[0x20]; 1892 1893 u8 if_in_errors_high[0x20]; 1894 1895 u8 if_in_errors_low[0x20]; 1896 1897 u8 if_in_unknown_protos_high[0x20]; 1898 1899 u8 if_in_unknown_protos_low[0x20]; 1900 1901 u8 if_out_octets_high[0x20]; 1902 1903 u8 if_out_octets_low[0x20]; 1904 1905 u8 if_out_ucast_pkts_high[0x20]; 1906 1907 u8 if_out_ucast_pkts_low[0x20]; 1908 1909 u8 if_out_discards_high[0x20]; 1910 1911 u8 if_out_discards_low[0x20]; 1912 1913 u8 if_out_errors_high[0x20]; 1914 1915 u8 if_out_errors_low[0x20]; 1916 1917 u8 if_in_multicast_pkts_high[0x20]; 1918 1919 u8 if_in_multicast_pkts_low[0x20]; 1920 1921 u8 if_in_broadcast_pkts_high[0x20]; 1922 1923 u8 if_in_broadcast_pkts_low[0x20]; 1924 1925 u8 if_out_multicast_pkts_high[0x20]; 1926 1927 u8 if_out_multicast_pkts_low[0x20]; 1928 1929 u8 if_out_broadcast_pkts_high[0x20]; 1930 1931 u8 if_out_broadcast_pkts_low[0x20]; 1932 1933 u8 reserved_at_340[0x480]; 1934 }; 1935 1936 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits { 1937 u8 a_frames_transmitted_ok_high[0x20]; 1938 1939 u8 a_frames_transmitted_ok_low[0x20]; 1940 1941 u8 a_frames_received_ok_high[0x20]; 1942 1943 u8 a_frames_received_ok_low[0x20]; 1944 1945 u8 a_frame_check_sequence_errors_high[0x20]; 1946 1947 u8 a_frame_check_sequence_errors_low[0x20]; 1948 1949 u8 a_alignment_errors_high[0x20]; 1950 1951 u8 a_alignment_errors_low[0x20]; 1952 1953 u8 a_octets_transmitted_ok_high[0x20]; 1954 1955 u8 a_octets_transmitted_ok_low[0x20]; 1956 1957 u8 a_octets_received_ok_high[0x20]; 1958 1959 u8 a_octets_received_ok_low[0x20]; 1960 1961 u8 a_multicast_frames_xmitted_ok_high[0x20]; 1962 1963 u8 a_multicast_frames_xmitted_ok_low[0x20]; 1964 1965 u8 a_broadcast_frames_xmitted_ok_high[0x20]; 1966 1967 u8 a_broadcast_frames_xmitted_ok_low[0x20]; 1968 1969 u8 a_multicast_frames_received_ok_high[0x20]; 1970 1971 u8 a_multicast_frames_received_ok_low[0x20]; 1972 1973 u8 a_broadcast_frames_received_ok_high[0x20]; 1974 1975 u8 a_broadcast_frames_received_ok_low[0x20]; 1976 1977 u8 a_in_range_length_errors_high[0x20]; 1978 1979 u8 a_in_range_length_errors_low[0x20]; 1980 1981 u8 a_out_of_range_length_field_high[0x20]; 1982 1983 u8 a_out_of_range_length_field_low[0x20]; 1984 1985 u8 a_frame_too_long_errors_high[0x20]; 1986 1987 u8 a_frame_too_long_errors_low[0x20]; 1988 1989 u8 a_symbol_error_during_carrier_high[0x20]; 1990 1991 u8 a_symbol_error_during_carrier_low[0x20]; 1992 1993 u8 a_mac_control_frames_transmitted_high[0x20]; 1994 1995 u8 a_mac_control_frames_transmitted_low[0x20]; 1996 1997 u8 a_mac_control_frames_received_high[0x20]; 1998 1999 u8 a_mac_control_frames_received_low[0x20]; 2000 2001 u8 a_unsupported_opcodes_received_high[0x20]; 2002 2003 u8 a_unsupported_opcodes_received_low[0x20]; 2004 2005 u8 a_pause_mac_ctrl_frames_received_high[0x20]; 2006 2007 u8 a_pause_mac_ctrl_frames_received_low[0x20]; 2008 2009 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20]; 2010 2011 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20]; 2012 2013 u8 reserved_at_4c0[0x300]; 2014 }; 2015 2016 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits { 2017 u8 life_time_counter_high[0x20]; 2018 2019 u8 life_time_counter_low[0x20]; 2020 2021 u8 rx_errors[0x20]; 2022 2023 u8 tx_errors[0x20]; 2024 2025 u8 l0_to_recovery_eieos[0x20]; 2026 2027 u8 l0_to_recovery_ts[0x20]; 2028 2029 u8 l0_to_recovery_framing[0x20]; 2030 2031 u8 l0_to_recovery_retrain[0x20]; 2032 2033 u8 crc_error_dllp[0x20]; 2034 2035 u8 crc_error_tlp[0x20]; 2036 2037 u8 tx_overflow_buffer_pkt_high[0x20]; 2038 2039 u8 tx_overflow_buffer_pkt_low[0x20]; 2040 2041 u8 outbound_stalled_reads[0x20]; 2042 2043 u8 outbound_stalled_writes[0x20]; 2044 2045 u8 outbound_stalled_reads_events[0x20]; 2046 2047 u8 outbound_stalled_writes_events[0x20]; 2048 2049 u8 reserved_at_200[0x5c0]; 2050 }; 2051 2052 struct mlx5_ifc_cmd_inter_comp_event_bits { 2053 u8 command_completion_vector[0x20]; 2054 2055 u8 reserved_at_20[0xc0]; 2056 }; 2057 2058 struct mlx5_ifc_stall_vl_event_bits { 2059 u8 reserved_at_0[0x18]; 2060 u8 port_num[0x1]; 2061 u8 reserved_at_19[0x3]; 2062 u8 vl[0x4]; 2063 2064 u8 reserved_at_20[0xa0]; 2065 }; 2066 2067 struct mlx5_ifc_db_bf_congestion_event_bits { 2068 u8 event_subtype[0x8]; 2069 u8 reserved_at_8[0x8]; 2070 u8 congestion_level[0x8]; 2071 u8 reserved_at_18[0x8]; 2072 2073 u8 reserved_at_20[0xa0]; 2074 }; 2075 2076 struct mlx5_ifc_gpio_event_bits { 2077 u8 reserved_at_0[0x60]; 2078 2079 u8 gpio_event_hi[0x20]; 2080 2081 u8 gpio_event_lo[0x20]; 2082 2083 u8 reserved_at_a0[0x40]; 2084 }; 2085 2086 struct mlx5_ifc_port_state_change_event_bits { 2087 u8 reserved_at_0[0x40]; 2088 2089 u8 port_num[0x4]; 2090 u8 reserved_at_44[0x1c]; 2091 2092 u8 reserved_at_60[0x80]; 2093 }; 2094 2095 struct mlx5_ifc_dropped_packet_logged_bits { 2096 u8 reserved_at_0[0xe0]; 2097 }; 2098 2099 enum { 2100 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1, 2101 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2, 2102 }; 2103 2104 struct mlx5_ifc_cq_error_bits { 2105 u8 reserved_at_0[0x8]; 2106 u8 cqn[0x18]; 2107 2108 u8 reserved_at_20[0x20]; 2109 2110 u8 reserved_at_40[0x18]; 2111 u8 syndrome[0x8]; 2112 2113 u8 reserved_at_60[0x80]; 2114 }; 2115 2116 struct mlx5_ifc_rdma_page_fault_event_bits { 2117 u8 bytes_committed[0x20]; 2118 2119 u8 r_key[0x20]; 2120 2121 u8 reserved_at_40[0x10]; 2122 u8 packet_len[0x10]; 2123 2124 u8 rdma_op_len[0x20]; 2125 2126 u8 rdma_va[0x40]; 2127 2128 u8 reserved_at_c0[0x5]; 2129 u8 rdma[0x1]; 2130 u8 write[0x1]; 2131 u8 requestor[0x1]; 2132 u8 qp_number[0x18]; 2133 }; 2134 2135 struct mlx5_ifc_wqe_associated_page_fault_event_bits { 2136 u8 bytes_committed[0x20]; 2137 2138 u8 reserved_at_20[0x10]; 2139 u8 wqe_index[0x10]; 2140 2141 u8 reserved_at_40[0x10]; 2142 u8 len[0x10]; 2143 2144 u8 reserved_at_60[0x60]; 2145 2146 u8 reserved_at_c0[0x5]; 2147 u8 rdma[0x1]; 2148 u8 write_read[0x1]; 2149 u8 requestor[0x1]; 2150 u8 qpn[0x18]; 2151 }; 2152 2153 struct mlx5_ifc_qp_events_bits { 2154 u8 reserved_at_0[0xa0]; 2155 2156 u8 type[0x8]; 2157 u8 reserved_at_a8[0x18]; 2158 2159 u8 reserved_at_c0[0x8]; 2160 u8 qpn_rqn_sqn[0x18]; 2161 }; 2162 2163 struct mlx5_ifc_dct_events_bits { 2164 u8 reserved_at_0[0xc0]; 2165 2166 u8 reserved_at_c0[0x8]; 2167 u8 dct_number[0x18]; 2168 }; 2169 2170 struct mlx5_ifc_comp_event_bits { 2171 u8 reserved_at_0[0xc0]; 2172 2173 u8 reserved_at_c0[0x8]; 2174 u8 cq_number[0x18]; 2175 }; 2176 2177 enum { 2178 MLX5_QPC_STATE_RST = 0x0, 2179 MLX5_QPC_STATE_INIT = 0x1, 2180 MLX5_QPC_STATE_RTR = 0x2, 2181 MLX5_QPC_STATE_RTS = 0x3, 2182 MLX5_QPC_STATE_SQER = 0x4, 2183 MLX5_QPC_STATE_ERR = 0x6, 2184 MLX5_QPC_STATE_SQD = 0x7, 2185 MLX5_QPC_STATE_SUSPENDED = 0x9, 2186 }; 2187 2188 enum { 2189 MLX5_QPC_ST_RC = 0x0, 2190 MLX5_QPC_ST_UC = 0x1, 2191 MLX5_QPC_ST_UD = 0x2, 2192 MLX5_QPC_ST_XRC = 0x3, 2193 MLX5_QPC_ST_DCI = 0x5, 2194 MLX5_QPC_ST_QP0 = 0x7, 2195 MLX5_QPC_ST_QP1 = 0x8, 2196 MLX5_QPC_ST_RAW_DATAGRAM = 0x9, 2197 MLX5_QPC_ST_REG_UMR = 0xc, 2198 }; 2199 2200 enum { 2201 MLX5_QPC_PM_STATE_ARMED = 0x0, 2202 MLX5_QPC_PM_STATE_REARM = 0x1, 2203 MLX5_QPC_PM_STATE_RESERVED = 0x2, 2204 MLX5_QPC_PM_STATE_MIGRATED = 0x3, 2205 }; 2206 2207 enum { 2208 MLX5_QPC_OFFLOAD_TYPE_RNDV = 0x1, 2209 }; 2210 2211 enum { 2212 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0, 2213 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1, 2214 }; 2215 2216 enum { 2217 MLX5_QPC_MTU_256_BYTES = 0x1, 2218 MLX5_QPC_MTU_512_BYTES = 0x2, 2219 MLX5_QPC_MTU_1K_BYTES = 0x3, 2220 MLX5_QPC_MTU_2K_BYTES = 0x4, 2221 MLX5_QPC_MTU_4K_BYTES = 0x5, 2222 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7, 2223 }; 2224 2225 enum { 2226 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1, 2227 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2, 2228 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3, 2229 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4, 2230 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5, 2231 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6, 2232 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7, 2233 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8, 2234 }; 2235 2236 enum { 2237 MLX5_QPC_CS_REQ_DISABLE = 0x0, 2238 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11, 2239 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22, 2240 }; 2241 2242 enum { 2243 MLX5_QPC_CS_RES_DISABLE = 0x0, 2244 MLX5_QPC_CS_RES_UP_TO_32B = 0x1, 2245 MLX5_QPC_CS_RES_UP_TO_64B = 0x2, 2246 }; 2247 2248 struct mlx5_ifc_qpc_bits { 2249 u8 state[0x4]; 2250 u8 lag_tx_port_affinity[0x4]; 2251 u8 st[0x8]; 2252 u8 reserved_at_10[0x3]; 2253 u8 pm_state[0x2]; 2254 u8 reserved_at_15[0x3]; 2255 u8 offload_type[0x4]; 2256 u8 end_padding_mode[0x2]; 2257 u8 reserved_at_1e[0x2]; 2258 2259 u8 wq_signature[0x1]; 2260 u8 block_lb_mc[0x1]; 2261 u8 atomic_like_write_en[0x1]; 2262 u8 latency_sensitive[0x1]; 2263 u8 reserved_at_24[0x1]; 2264 u8 drain_sigerr[0x1]; 2265 u8 reserved_at_26[0x2]; 2266 u8 pd[0x18]; 2267 2268 u8 mtu[0x3]; 2269 u8 log_msg_max[0x5]; 2270 u8 reserved_at_48[0x1]; 2271 u8 log_rq_size[0x4]; 2272 u8 log_rq_stride[0x3]; 2273 u8 no_sq[0x1]; 2274 u8 log_sq_size[0x4]; 2275 u8 reserved_at_55[0x6]; 2276 u8 rlky[0x1]; 2277 u8 ulp_stateless_offload_mode[0x4]; 2278 2279 u8 counter_set_id[0x8]; 2280 u8 uar_page[0x18]; 2281 2282 u8 reserved_at_80[0x8]; 2283 u8 user_index[0x18]; 2284 2285 u8 reserved_at_a0[0x3]; 2286 u8 log_page_size[0x5]; 2287 u8 remote_qpn[0x18]; 2288 2289 struct mlx5_ifc_ads_bits primary_address_path; 2290 2291 struct mlx5_ifc_ads_bits secondary_address_path; 2292 2293 u8 log_ack_req_freq[0x4]; 2294 u8 reserved_at_384[0x4]; 2295 u8 log_sra_max[0x3]; 2296 u8 reserved_at_38b[0x2]; 2297 u8 retry_count[0x3]; 2298 u8 rnr_retry[0x3]; 2299 u8 reserved_at_393[0x1]; 2300 u8 fre[0x1]; 2301 u8 cur_rnr_retry[0x3]; 2302 u8 cur_retry_count[0x3]; 2303 u8 reserved_at_39b[0x5]; 2304 2305 u8 reserved_at_3a0[0x20]; 2306 2307 u8 reserved_at_3c0[0x8]; 2308 u8 next_send_psn[0x18]; 2309 2310 u8 reserved_at_3e0[0x8]; 2311 u8 cqn_snd[0x18]; 2312 2313 u8 reserved_at_400[0x8]; 2314 u8 deth_sqpn[0x18]; 2315 2316 u8 reserved_at_420[0x20]; 2317 2318 u8 reserved_at_440[0x8]; 2319 u8 last_acked_psn[0x18]; 2320 2321 u8 reserved_at_460[0x8]; 2322 u8 ssn[0x18]; 2323 2324 u8 reserved_at_480[0x8]; 2325 u8 log_rra_max[0x3]; 2326 u8 reserved_at_48b[0x1]; 2327 u8 atomic_mode[0x4]; 2328 u8 rre[0x1]; 2329 u8 rwe[0x1]; 2330 u8 rae[0x1]; 2331 u8 reserved_at_493[0x1]; 2332 u8 page_offset[0x6]; 2333 u8 reserved_at_49a[0x3]; 2334 u8 cd_slave_receive[0x1]; 2335 u8 cd_slave_send[0x1]; 2336 u8 cd_master[0x1]; 2337 2338 u8 reserved_at_4a0[0x3]; 2339 u8 min_rnr_nak[0x5]; 2340 u8 next_rcv_psn[0x18]; 2341 2342 u8 reserved_at_4c0[0x8]; 2343 u8 xrcd[0x18]; 2344 2345 u8 reserved_at_4e0[0x8]; 2346 u8 cqn_rcv[0x18]; 2347 2348 u8 dbr_addr[0x40]; 2349 2350 u8 q_key[0x20]; 2351 2352 u8 reserved_at_560[0x5]; 2353 u8 rq_type[0x3]; 2354 u8 srqn_rmpn_xrqn[0x18]; 2355 2356 u8 reserved_at_580[0x8]; 2357 u8 rmsn[0x18]; 2358 2359 u8 hw_sq_wqebb_counter[0x10]; 2360 u8 sw_sq_wqebb_counter[0x10]; 2361 2362 u8 hw_rq_counter[0x20]; 2363 2364 u8 sw_rq_counter[0x20]; 2365 2366 u8 reserved_at_600[0x20]; 2367 2368 u8 reserved_at_620[0xf]; 2369 u8 cgs[0x1]; 2370 u8 cs_req[0x8]; 2371 u8 cs_res[0x8]; 2372 2373 u8 dc_access_key[0x40]; 2374 2375 u8 reserved_at_680[0x3]; 2376 u8 dbr_umem_valid[0x1]; 2377 2378 u8 reserved_at_684[0xbc]; 2379 }; 2380 2381 struct mlx5_ifc_roce_addr_layout_bits { 2382 u8 source_l3_address[16][0x8]; 2383 2384 u8 reserved_at_80[0x3]; 2385 u8 vlan_valid[0x1]; 2386 u8 vlan_id[0xc]; 2387 u8 source_mac_47_32[0x10]; 2388 2389 u8 source_mac_31_0[0x20]; 2390 2391 u8 reserved_at_c0[0x14]; 2392 u8 roce_l3_type[0x4]; 2393 u8 roce_version[0x8]; 2394 2395 u8 reserved_at_e0[0x20]; 2396 }; 2397 2398 union mlx5_ifc_hca_cap_union_bits { 2399 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap; 2400 struct mlx5_ifc_odp_cap_bits odp_cap; 2401 struct mlx5_ifc_atomic_caps_bits atomic_caps; 2402 struct mlx5_ifc_roce_cap_bits roce_cap; 2403 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps; 2404 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap; 2405 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap; 2406 struct mlx5_ifc_e_switch_cap_bits e_switch_cap; 2407 struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap; 2408 struct mlx5_ifc_qos_cap_bits qos_cap; 2409 struct mlx5_ifc_fpga_cap_bits fpga_cap; 2410 u8 reserved_at_0[0x8000]; 2411 }; 2412 2413 enum { 2414 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1, 2415 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2, 2416 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4, 2417 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8, 2418 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT = 0x10, 2419 MLX5_FLOW_CONTEXT_ACTION_DECAP = 0x20, 2420 MLX5_FLOW_CONTEXT_ACTION_MOD_HDR = 0x40, 2421 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP = 0x80, 2422 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100, 2423 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2 = 0x400, 2424 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2 = 0x800, 2425 }; 2426 2427 struct mlx5_ifc_vlan_bits { 2428 u8 ethtype[0x10]; 2429 u8 prio[0x3]; 2430 u8 cfi[0x1]; 2431 u8 vid[0xc]; 2432 }; 2433 2434 struct mlx5_ifc_flow_context_bits { 2435 struct mlx5_ifc_vlan_bits push_vlan; 2436 2437 u8 group_id[0x20]; 2438 2439 u8 reserved_at_40[0x8]; 2440 u8 flow_tag[0x18]; 2441 2442 u8 reserved_at_60[0x10]; 2443 u8 action[0x10]; 2444 2445 u8 reserved_at_80[0x8]; 2446 u8 destination_list_size[0x18]; 2447 2448 u8 reserved_at_a0[0x8]; 2449 u8 flow_counter_list_size[0x18]; 2450 2451 u8 packet_reformat_id[0x20]; 2452 2453 u8 modify_header_id[0x20]; 2454 2455 struct mlx5_ifc_vlan_bits push_vlan_2; 2456 2457 u8 reserved_at_120[0xe0]; 2458 2459 struct mlx5_ifc_fte_match_param_bits match_value; 2460 2461 u8 reserved_at_1200[0x600]; 2462 2463 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[0]; 2464 }; 2465 2466 enum { 2467 MLX5_XRC_SRQC_STATE_GOOD = 0x0, 2468 MLX5_XRC_SRQC_STATE_ERROR = 0x1, 2469 }; 2470 2471 struct mlx5_ifc_xrc_srqc_bits { 2472 u8 state[0x4]; 2473 u8 log_xrc_srq_size[0x4]; 2474 u8 reserved_at_8[0x18]; 2475 2476 u8 wq_signature[0x1]; 2477 u8 cont_srq[0x1]; 2478 u8 reserved_at_22[0x1]; 2479 u8 rlky[0x1]; 2480 u8 basic_cyclic_rcv_wqe[0x1]; 2481 u8 log_rq_stride[0x3]; 2482 u8 xrcd[0x18]; 2483 2484 u8 page_offset[0x6]; 2485 u8 reserved_at_46[0x1]; 2486 u8 dbr_umem_valid[0x1]; 2487 u8 cqn[0x18]; 2488 2489 u8 reserved_at_60[0x20]; 2490 2491 u8 user_index_equal_xrc_srqn[0x1]; 2492 u8 reserved_at_81[0x1]; 2493 u8 log_page_size[0x6]; 2494 u8 user_index[0x18]; 2495 2496 u8 reserved_at_a0[0x20]; 2497 2498 u8 reserved_at_c0[0x8]; 2499 u8 pd[0x18]; 2500 2501 u8 lwm[0x10]; 2502 u8 wqe_cnt[0x10]; 2503 2504 u8 reserved_at_100[0x40]; 2505 2506 u8 db_record_addr_h[0x20]; 2507 2508 u8 db_record_addr_l[0x1e]; 2509 u8 reserved_at_17e[0x2]; 2510 2511 u8 reserved_at_180[0x80]; 2512 }; 2513 2514 struct mlx5_ifc_vnic_diagnostic_statistics_bits { 2515 u8 counter_error_queues[0x20]; 2516 2517 u8 total_error_queues[0x20]; 2518 2519 u8 send_queue_priority_update_flow[0x20]; 2520 2521 u8 reserved_at_60[0x20]; 2522 2523 u8 nic_receive_steering_discard[0x40]; 2524 2525 u8 receive_discard_vport_down[0x40]; 2526 2527 u8 transmit_discard_vport_down[0x40]; 2528 2529 u8 reserved_at_140[0xec0]; 2530 }; 2531 2532 struct mlx5_ifc_traffic_counter_bits { 2533 u8 packets[0x40]; 2534 2535 u8 octets[0x40]; 2536 }; 2537 2538 struct mlx5_ifc_tisc_bits { 2539 u8 strict_lag_tx_port_affinity[0x1]; 2540 u8 reserved_at_1[0x3]; 2541 u8 lag_tx_port_affinity[0x04]; 2542 2543 u8 reserved_at_8[0x4]; 2544 u8 prio[0x4]; 2545 u8 reserved_at_10[0x10]; 2546 2547 u8 reserved_at_20[0x100]; 2548 2549 u8 reserved_at_120[0x8]; 2550 u8 transport_domain[0x18]; 2551 2552 u8 reserved_at_140[0x8]; 2553 u8 underlay_qpn[0x18]; 2554 u8 reserved_at_160[0x3a0]; 2555 }; 2556 2557 enum { 2558 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0, 2559 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1, 2560 }; 2561 2562 enum { 2563 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO = 0x1, 2564 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO = 0x2, 2565 }; 2566 2567 enum { 2568 MLX5_RX_HASH_FN_NONE = 0x0, 2569 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1, 2570 MLX5_RX_HASH_FN_TOEPLITZ = 0x2, 2571 }; 2572 2573 enum { 2574 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST = 0x1, 2575 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST = 0x2, 2576 }; 2577 2578 struct mlx5_ifc_tirc_bits { 2579 u8 reserved_at_0[0x20]; 2580 2581 u8 disp_type[0x4]; 2582 u8 reserved_at_24[0x1c]; 2583 2584 u8 reserved_at_40[0x40]; 2585 2586 u8 reserved_at_80[0x4]; 2587 u8 lro_timeout_period_usecs[0x10]; 2588 u8 lro_enable_mask[0x4]; 2589 u8 lro_max_ip_payload_size[0x8]; 2590 2591 u8 reserved_at_a0[0x40]; 2592 2593 u8 reserved_at_e0[0x8]; 2594 u8 inline_rqn[0x18]; 2595 2596 u8 rx_hash_symmetric[0x1]; 2597 u8 reserved_at_101[0x1]; 2598 u8 tunneled_offload_en[0x1]; 2599 u8 reserved_at_103[0x5]; 2600 u8 indirect_table[0x18]; 2601 2602 u8 rx_hash_fn[0x4]; 2603 u8 reserved_at_124[0x2]; 2604 u8 self_lb_block[0x2]; 2605 u8 transport_domain[0x18]; 2606 2607 u8 rx_hash_toeplitz_key[10][0x20]; 2608 2609 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer; 2610 2611 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner; 2612 2613 u8 reserved_at_2c0[0x4c0]; 2614 }; 2615 2616 enum { 2617 MLX5_SRQC_STATE_GOOD = 0x0, 2618 MLX5_SRQC_STATE_ERROR = 0x1, 2619 }; 2620 2621 struct mlx5_ifc_srqc_bits { 2622 u8 state[0x4]; 2623 u8 log_srq_size[0x4]; 2624 u8 reserved_at_8[0x18]; 2625 2626 u8 wq_signature[0x1]; 2627 u8 cont_srq[0x1]; 2628 u8 reserved_at_22[0x1]; 2629 u8 rlky[0x1]; 2630 u8 reserved_at_24[0x1]; 2631 u8 log_rq_stride[0x3]; 2632 u8 xrcd[0x18]; 2633 2634 u8 page_offset[0x6]; 2635 u8 reserved_at_46[0x2]; 2636 u8 cqn[0x18]; 2637 2638 u8 reserved_at_60[0x20]; 2639 2640 u8 reserved_at_80[0x2]; 2641 u8 log_page_size[0x6]; 2642 u8 reserved_at_88[0x18]; 2643 2644 u8 reserved_at_a0[0x20]; 2645 2646 u8 reserved_at_c0[0x8]; 2647 u8 pd[0x18]; 2648 2649 u8 lwm[0x10]; 2650 u8 wqe_cnt[0x10]; 2651 2652 u8 reserved_at_100[0x40]; 2653 2654 u8 dbr_addr[0x40]; 2655 2656 u8 reserved_at_180[0x80]; 2657 }; 2658 2659 enum { 2660 MLX5_SQC_STATE_RST = 0x0, 2661 MLX5_SQC_STATE_RDY = 0x1, 2662 MLX5_SQC_STATE_ERR = 0x3, 2663 }; 2664 2665 struct mlx5_ifc_sqc_bits { 2666 u8 rlky[0x1]; 2667 u8 cd_master[0x1]; 2668 u8 fre[0x1]; 2669 u8 flush_in_error_en[0x1]; 2670 u8 allow_multi_pkt_send_wqe[0x1]; 2671 u8 min_wqe_inline_mode[0x3]; 2672 u8 state[0x4]; 2673 u8 reg_umr[0x1]; 2674 u8 allow_swp[0x1]; 2675 u8 hairpin[0x1]; 2676 u8 reserved_at_f[0x11]; 2677 2678 u8 reserved_at_20[0x8]; 2679 u8 user_index[0x18]; 2680 2681 u8 reserved_at_40[0x8]; 2682 u8 cqn[0x18]; 2683 2684 u8 reserved_at_60[0x8]; 2685 u8 hairpin_peer_rq[0x18]; 2686 2687 u8 reserved_at_80[0x10]; 2688 u8 hairpin_peer_vhca[0x10]; 2689 2690 u8 reserved_at_a0[0x50]; 2691 2692 u8 packet_pacing_rate_limit_index[0x10]; 2693 u8 tis_lst_sz[0x10]; 2694 u8 reserved_at_110[0x10]; 2695 2696 u8 reserved_at_120[0x40]; 2697 2698 u8 reserved_at_160[0x8]; 2699 u8 tis_num_0[0x18]; 2700 2701 struct mlx5_ifc_wq_bits wq; 2702 }; 2703 2704 enum { 2705 SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0, 2706 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1, 2707 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2, 2708 SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3, 2709 }; 2710 2711 struct mlx5_ifc_scheduling_context_bits { 2712 u8 element_type[0x8]; 2713 u8 reserved_at_8[0x18]; 2714 2715 u8 element_attributes[0x20]; 2716 2717 u8 parent_element_id[0x20]; 2718 2719 u8 reserved_at_60[0x40]; 2720 2721 u8 bw_share[0x20]; 2722 2723 u8 max_average_bw[0x20]; 2724 2725 u8 reserved_at_e0[0x120]; 2726 }; 2727 2728 struct mlx5_ifc_rqtc_bits { 2729 u8 reserved_at_0[0xa0]; 2730 2731 u8 reserved_at_a0[0x10]; 2732 u8 rqt_max_size[0x10]; 2733 2734 u8 reserved_at_c0[0x10]; 2735 u8 rqt_actual_size[0x10]; 2736 2737 u8 reserved_at_e0[0x6a0]; 2738 2739 struct mlx5_ifc_rq_num_bits rq_num[0]; 2740 }; 2741 2742 enum { 2743 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0, 2744 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1, 2745 }; 2746 2747 enum { 2748 MLX5_RQC_STATE_RST = 0x0, 2749 MLX5_RQC_STATE_RDY = 0x1, 2750 MLX5_RQC_STATE_ERR = 0x3, 2751 }; 2752 2753 struct mlx5_ifc_rqc_bits { 2754 u8 rlky[0x1]; 2755 u8 delay_drop_en[0x1]; 2756 u8 scatter_fcs[0x1]; 2757 u8 vsd[0x1]; 2758 u8 mem_rq_type[0x4]; 2759 u8 state[0x4]; 2760 u8 reserved_at_c[0x1]; 2761 u8 flush_in_error_en[0x1]; 2762 u8 hairpin[0x1]; 2763 u8 reserved_at_f[0x11]; 2764 2765 u8 reserved_at_20[0x8]; 2766 u8 user_index[0x18]; 2767 2768 u8 reserved_at_40[0x8]; 2769 u8 cqn[0x18]; 2770 2771 u8 counter_set_id[0x8]; 2772 u8 reserved_at_68[0x18]; 2773 2774 u8 reserved_at_80[0x8]; 2775 u8 rmpn[0x18]; 2776 2777 u8 reserved_at_a0[0x8]; 2778 u8 hairpin_peer_sq[0x18]; 2779 2780 u8 reserved_at_c0[0x10]; 2781 u8 hairpin_peer_vhca[0x10]; 2782 2783 u8 reserved_at_e0[0xa0]; 2784 2785 struct mlx5_ifc_wq_bits wq; 2786 }; 2787 2788 enum { 2789 MLX5_RMPC_STATE_RDY = 0x1, 2790 MLX5_RMPC_STATE_ERR = 0x3, 2791 }; 2792 2793 struct mlx5_ifc_rmpc_bits { 2794 u8 reserved_at_0[0x8]; 2795 u8 state[0x4]; 2796 u8 reserved_at_c[0x14]; 2797 2798 u8 basic_cyclic_rcv_wqe[0x1]; 2799 u8 reserved_at_21[0x1f]; 2800 2801 u8 reserved_at_40[0x140]; 2802 2803 struct mlx5_ifc_wq_bits wq; 2804 }; 2805 2806 struct mlx5_ifc_nic_vport_context_bits { 2807 u8 reserved_at_0[0x5]; 2808 u8 min_wqe_inline_mode[0x3]; 2809 u8 reserved_at_8[0x15]; 2810 u8 disable_mc_local_lb[0x1]; 2811 u8 disable_uc_local_lb[0x1]; 2812 u8 roce_en[0x1]; 2813 2814 u8 arm_change_event[0x1]; 2815 u8 reserved_at_21[0x1a]; 2816 u8 event_on_mtu[0x1]; 2817 u8 event_on_promisc_change[0x1]; 2818 u8 event_on_vlan_change[0x1]; 2819 u8 event_on_mc_address_change[0x1]; 2820 u8 event_on_uc_address_change[0x1]; 2821 2822 u8 reserved_at_40[0xc]; 2823 2824 u8 affiliation_criteria[0x4]; 2825 u8 affiliated_vhca_id[0x10]; 2826 2827 u8 reserved_at_60[0xd0]; 2828 2829 u8 mtu[0x10]; 2830 2831 u8 system_image_guid[0x40]; 2832 u8 port_guid[0x40]; 2833 u8 node_guid[0x40]; 2834 2835 u8 reserved_at_200[0x140]; 2836 u8 qkey_violation_counter[0x10]; 2837 u8 reserved_at_350[0x430]; 2838 2839 u8 promisc_uc[0x1]; 2840 u8 promisc_mc[0x1]; 2841 u8 promisc_all[0x1]; 2842 u8 reserved_at_783[0x2]; 2843 u8 allowed_list_type[0x3]; 2844 u8 reserved_at_788[0xc]; 2845 u8 allowed_list_size[0xc]; 2846 2847 struct mlx5_ifc_mac_address_layout_bits permanent_address; 2848 2849 u8 reserved_at_7e0[0x20]; 2850 2851 u8 current_uc_mac_address[0][0x40]; 2852 }; 2853 2854 enum { 2855 MLX5_MKC_ACCESS_MODE_PA = 0x0, 2856 MLX5_MKC_ACCESS_MODE_MTT = 0x1, 2857 MLX5_MKC_ACCESS_MODE_KLMS = 0x2, 2858 MLX5_MKC_ACCESS_MODE_KSM = 0x3, 2859 MLX5_MKC_ACCESS_MODE_MEMIC = 0x5, 2860 }; 2861 2862 struct mlx5_ifc_mkc_bits { 2863 u8 reserved_at_0[0x1]; 2864 u8 free[0x1]; 2865 u8 reserved_at_2[0x1]; 2866 u8 access_mode_4_2[0x3]; 2867 u8 reserved_at_6[0x7]; 2868 u8 relaxed_ordering_write[0x1]; 2869 u8 reserved_at_e[0x1]; 2870 u8 small_fence_on_rdma_read_response[0x1]; 2871 u8 umr_en[0x1]; 2872 u8 a[0x1]; 2873 u8 rw[0x1]; 2874 u8 rr[0x1]; 2875 u8 lw[0x1]; 2876 u8 lr[0x1]; 2877 u8 access_mode_1_0[0x2]; 2878 u8 reserved_at_18[0x8]; 2879 2880 u8 qpn[0x18]; 2881 u8 mkey_7_0[0x8]; 2882 2883 u8 reserved_at_40[0x20]; 2884 2885 u8 length64[0x1]; 2886 u8 bsf_en[0x1]; 2887 u8 sync_umr[0x1]; 2888 u8 reserved_at_63[0x2]; 2889 u8 expected_sigerr_count[0x1]; 2890 u8 reserved_at_66[0x1]; 2891 u8 en_rinval[0x1]; 2892 u8 pd[0x18]; 2893 2894 u8 start_addr[0x40]; 2895 2896 u8 len[0x40]; 2897 2898 u8 bsf_octword_size[0x20]; 2899 2900 u8 reserved_at_120[0x80]; 2901 2902 u8 translations_octword_size[0x20]; 2903 2904 u8 reserved_at_1c0[0x1b]; 2905 u8 log_page_size[0x5]; 2906 2907 u8 reserved_at_1e0[0x20]; 2908 }; 2909 2910 struct mlx5_ifc_pkey_bits { 2911 u8 reserved_at_0[0x10]; 2912 u8 pkey[0x10]; 2913 }; 2914 2915 struct mlx5_ifc_array128_auto_bits { 2916 u8 array128_auto[16][0x8]; 2917 }; 2918 2919 struct mlx5_ifc_hca_vport_context_bits { 2920 u8 field_select[0x20]; 2921 2922 u8 reserved_at_20[0xe0]; 2923 2924 u8 sm_virt_aware[0x1]; 2925 u8 has_smi[0x1]; 2926 u8 has_raw[0x1]; 2927 u8 grh_required[0x1]; 2928 u8 reserved_at_104[0xc]; 2929 u8 port_physical_state[0x4]; 2930 u8 vport_state_policy[0x4]; 2931 u8 port_state[0x4]; 2932 u8 vport_state[0x4]; 2933 2934 u8 reserved_at_120[0x20]; 2935 2936 u8 system_image_guid[0x40]; 2937 2938 u8 port_guid[0x40]; 2939 2940 u8 node_guid[0x40]; 2941 2942 u8 cap_mask1[0x20]; 2943 2944 u8 cap_mask1_field_select[0x20]; 2945 2946 u8 cap_mask2[0x20]; 2947 2948 u8 cap_mask2_field_select[0x20]; 2949 2950 u8 reserved_at_280[0x80]; 2951 2952 u8 lid[0x10]; 2953 u8 reserved_at_310[0x4]; 2954 u8 init_type_reply[0x4]; 2955 u8 lmc[0x3]; 2956 u8 subnet_timeout[0x5]; 2957 2958 u8 sm_lid[0x10]; 2959 u8 sm_sl[0x4]; 2960 u8 reserved_at_334[0xc]; 2961 2962 u8 qkey_violation_counter[0x10]; 2963 u8 pkey_violation_counter[0x10]; 2964 2965 u8 reserved_at_360[0xca0]; 2966 }; 2967 2968 struct mlx5_ifc_esw_vport_context_bits { 2969 u8 reserved_at_0[0x3]; 2970 u8 vport_svlan_strip[0x1]; 2971 u8 vport_cvlan_strip[0x1]; 2972 u8 vport_svlan_insert[0x1]; 2973 u8 vport_cvlan_insert[0x2]; 2974 u8 reserved_at_8[0x18]; 2975 2976 u8 reserved_at_20[0x20]; 2977 2978 u8 svlan_cfi[0x1]; 2979 u8 svlan_pcp[0x3]; 2980 u8 svlan_id[0xc]; 2981 u8 cvlan_cfi[0x1]; 2982 u8 cvlan_pcp[0x3]; 2983 u8 cvlan_id[0xc]; 2984 2985 u8 reserved_at_60[0x7a0]; 2986 }; 2987 2988 enum { 2989 MLX5_EQC_STATUS_OK = 0x0, 2990 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa, 2991 }; 2992 2993 enum { 2994 MLX5_EQC_ST_ARMED = 0x9, 2995 MLX5_EQC_ST_FIRED = 0xa, 2996 }; 2997 2998 struct mlx5_ifc_eqc_bits { 2999 u8 status[0x4]; 3000 u8 reserved_at_4[0x9]; 3001 u8 ec[0x1]; 3002 u8 oi[0x1]; 3003 u8 reserved_at_f[0x5]; 3004 u8 st[0x4]; 3005 u8 reserved_at_18[0x8]; 3006 3007 u8 reserved_at_20[0x20]; 3008 3009 u8 reserved_at_40[0x14]; 3010 u8 page_offset[0x6]; 3011 u8 reserved_at_5a[0x6]; 3012 3013 u8 reserved_at_60[0x3]; 3014 u8 log_eq_size[0x5]; 3015 u8 uar_page[0x18]; 3016 3017 u8 reserved_at_80[0x20]; 3018 3019 u8 reserved_at_a0[0x18]; 3020 u8 intr[0x8]; 3021 3022 u8 reserved_at_c0[0x3]; 3023 u8 log_page_size[0x5]; 3024 u8 reserved_at_c8[0x18]; 3025 3026 u8 reserved_at_e0[0x60]; 3027 3028 u8 reserved_at_140[0x8]; 3029 u8 consumer_counter[0x18]; 3030 3031 u8 reserved_at_160[0x8]; 3032 u8 producer_counter[0x18]; 3033 3034 u8 reserved_at_180[0x80]; 3035 }; 3036 3037 enum { 3038 MLX5_DCTC_STATE_ACTIVE = 0x0, 3039 MLX5_DCTC_STATE_DRAINING = 0x1, 3040 MLX5_DCTC_STATE_DRAINED = 0x2, 3041 }; 3042 3043 enum { 3044 MLX5_DCTC_CS_RES_DISABLE = 0x0, 3045 MLX5_DCTC_CS_RES_NA = 0x1, 3046 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2, 3047 }; 3048 3049 enum { 3050 MLX5_DCTC_MTU_256_BYTES = 0x1, 3051 MLX5_DCTC_MTU_512_BYTES = 0x2, 3052 MLX5_DCTC_MTU_1K_BYTES = 0x3, 3053 MLX5_DCTC_MTU_2K_BYTES = 0x4, 3054 MLX5_DCTC_MTU_4K_BYTES = 0x5, 3055 }; 3056 3057 struct mlx5_ifc_dctc_bits { 3058 u8 reserved_at_0[0x4]; 3059 u8 state[0x4]; 3060 u8 reserved_at_8[0x18]; 3061 3062 u8 reserved_at_20[0x8]; 3063 u8 user_index[0x18]; 3064 3065 u8 reserved_at_40[0x8]; 3066 u8 cqn[0x18]; 3067 3068 u8 counter_set_id[0x8]; 3069 u8 atomic_mode[0x4]; 3070 u8 rre[0x1]; 3071 u8 rwe[0x1]; 3072 u8 rae[0x1]; 3073 u8 atomic_like_write_en[0x1]; 3074 u8 latency_sensitive[0x1]; 3075 u8 rlky[0x1]; 3076 u8 free_ar[0x1]; 3077 u8 reserved_at_73[0xd]; 3078 3079 u8 reserved_at_80[0x8]; 3080 u8 cs_res[0x8]; 3081 u8 reserved_at_90[0x3]; 3082 u8 min_rnr_nak[0x5]; 3083 u8 reserved_at_98[0x8]; 3084 3085 u8 reserved_at_a0[0x8]; 3086 u8 srqn_xrqn[0x18]; 3087 3088 u8 reserved_at_c0[0x8]; 3089 u8 pd[0x18]; 3090 3091 u8 tclass[0x8]; 3092 u8 reserved_at_e8[0x4]; 3093 u8 flow_label[0x14]; 3094 3095 u8 dc_access_key[0x40]; 3096 3097 u8 reserved_at_140[0x5]; 3098 u8 mtu[0x3]; 3099 u8 port[0x8]; 3100 u8 pkey_index[0x10]; 3101 3102 u8 reserved_at_160[0x8]; 3103 u8 my_addr_index[0x8]; 3104 u8 reserved_at_170[0x8]; 3105 u8 hop_limit[0x8]; 3106 3107 u8 dc_access_key_violation_count[0x20]; 3108 3109 u8 reserved_at_1a0[0x14]; 3110 u8 dei_cfi[0x1]; 3111 u8 eth_prio[0x3]; 3112 u8 ecn[0x2]; 3113 u8 dscp[0x6]; 3114 3115 u8 reserved_at_1c0[0x40]; 3116 }; 3117 3118 enum { 3119 MLX5_CQC_STATUS_OK = 0x0, 3120 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9, 3121 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa, 3122 }; 3123 3124 enum { 3125 MLX5_CQC_CQE_SZ_64_BYTES = 0x0, 3126 MLX5_CQC_CQE_SZ_128_BYTES = 0x1, 3127 }; 3128 3129 enum { 3130 MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED = 0x6, 3131 MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED = 0x9, 3132 MLX5_CQC_ST_FIRED = 0xa, 3133 }; 3134 3135 enum { 3136 MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0, 3137 MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1, 3138 MLX5_CQ_PERIOD_NUM_MODES 3139 }; 3140 3141 struct mlx5_ifc_cqc_bits { 3142 u8 status[0x4]; 3143 u8 reserved_at_4[0x2]; 3144 u8 dbr_umem_valid[0x1]; 3145 u8 reserved_at_7[0x1]; 3146 u8 cqe_sz[0x3]; 3147 u8 cc[0x1]; 3148 u8 reserved_at_c[0x1]; 3149 u8 scqe_break_moderation_en[0x1]; 3150 u8 oi[0x1]; 3151 u8 cq_period_mode[0x2]; 3152 u8 cqe_comp_en[0x1]; 3153 u8 mini_cqe_res_format[0x2]; 3154 u8 st[0x4]; 3155 u8 reserved_at_18[0x8]; 3156 3157 u8 reserved_at_20[0x20]; 3158 3159 u8 reserved_at_40[0x14]; 3160 u8 page_offset[0x6]; 3161 u8 reserved_at_5a[0x6]; 3162 3163 u8 reserved_at_60[0x3]; 3164 u8 log_cq_size[0x5]; 3165 u8 uar_page[0x18]; 3166 3167 u8 reserved_at_80[0x4]; 3168 u8 cq_period[0xc]; 3169 u8 cq_max_count[0x10]; 3170 3171 u8 reserved_at_a0[0x18]; 3172 u8 c_eqn[0x8]; 3173 3174 u8 reserved_at_c0[0x3]; 3175 u8 log_page_size[0x5]; 3176 u8 reserved_at_c8[0x18]; 3177 3178 u8 reserved_at_e0[0x20]; 3179 3180 u8 reserved_at_100[0x8]; 3181 u8 last_notified_index[0x18]; 3182 3183 u8 reserved_at_120[0x8]; 3184 u8 last_solicit_index[0x18]; 3185 3186 u8 reserved_at_140[0x8]; 3187 u8 consumer_counter[0x18]; 3188 3189 u8 reserved_at_160[0x8]; 3190 u8 producer_counter[0x18]; 3191 3192 u8 reserved_at_180[0x40]; 3193 3194 u8 dbr_addr[0x40]; 3195 }; 3196 3197 union mlx5_ifc_cong_control_roce_ecn_auto_bits { 3198 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp; 3199 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp; 3200 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np; 3201 u8 reserved_at_0[0x800]; 3202 }; 3203 3204 struct mlx5_ifc_query_adapter_param_block_bits { 3205 u8 reserved_at_0[0xc0]; 3206 3207 u8 reserved_at_c0[0x8]; 3208 u8 ieee_vendor_id[0x18]; 3209 3210 u8 reserved_at_e0[0x10]; 3211 u8 vsd_vendor_id[0x10]; 3212 3213 u8 vsd[208][0x8]; 3214 3215 u8 vsd_contd_psid[16][0x8]; 3216 }; 3217 3218 enum { 3219 MLX5_XRQC_STATE_GOOD = 0x0, 3220 MLX5_XRQC_STATE_ERROR = 0x1, 3221 }; 3222 3223 enum { 3224 MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0, 3225 MLX5_XRQC_TOPOLOGY_TAG_MATCHING = 0x1, 3226 }; 3227 3228 enum { 3229 MLX5_XRQC_OFFLOAD_RNDV = 0x1, 3230 }; 3231 3232 struct mlx5_ifc_tag_matching_topology_context_bits { 3233 u8 log_matching_list_sz[0x4]; 3234 u8 reserved_at_4[0xc]; 3235 u8 append_next_index[0x10]; 3236 3237 u8 sw_phase_cnt[0x10]; 3238 u8 hw_phase_cnt[0x10]; 3239 3240 u8 reserved_at_40[0x40]; 3241 }; 3242 3243 struct mlx5_ifc_xrqc_bits { 3244 u8 state[0x4]; 3245 u8 rlkey[0x1]; 3246 u8 reserved_at_5[0xf]; 3247 u8 topology[0x4]; 3248 u8 reserved_at_18[0x4]; 3249 u8 offload[0x4]; 3250 3251 u8 reserved_at_20[0x8]; 3252 u8 user_index[0x18]; 3253 3254 u8 reserved_at_40[0x8]; 3255 u8 cqn[0x18]; 3256 3257 u8 reserved_at_60[0xa0]; 3258 3259 struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context; 3260 3261 u8 reserved_at_180[0x280]; 3262 3263 struct mlx5_ifc_wq_bits wq; 3264 }; 3265 3266 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits { 3267 struct mlx5_ifc_modify_field_select_bits modify_field_select; 3268 struct mlx5_ifc_resize_field_select_bits resize_field_select; 3269 u8 reserved_at_0[0x20]; 3270 }; 3271 3272 union mlx5_ifc_field_select_802_1_r_roce_auto_bits { 3273 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp; 3274 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp; 3275 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np; 3276 u8 reserved_at_0[0x20]; 3277 }; 3278 3279 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits { 3280 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 3281 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 3282 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 3283 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 3284 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 3285 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 3286 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout; 3287 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 3288 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 3289 struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs; 3290 u8 reserved_at_0[0x7c0]; 3291 }; 3292 3293 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits { 3294 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout; 3295 u8 reserved_at_0[0x7c0]; 3296 }; 3297 3298 union mlx5_ifc_event_auto_bits { 3299 struct mlx5_ifc_comp_event_bits comp_event; 3300 struct mlx5_ifc_dct_events_bits dct_events; 3301 struct mlx5_ifc_qp_events_bits qp_events; 3302 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event; 3303 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event; 3304 struct mlx5_ifc_cq_error_bits cq_error; 3305 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged; 3306 struct mlx5_ifc_port_state_change_event_bits port_state_change_event; 3307 struct mlx5_ifc_gpio_event_bits gpio_event; 3308 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event; 3309 struct mlx5_ifc_stall_vl_event_bits stall_vl_event; 3310 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event; 3311 u8 reserved_at_0[0xe0]; 3312 }; 3313 3314 struct mlx5_ifc_health_buffer_bits { 3315 u8 reserved_at_0[0x100]; 3316 3317 u8 assert_existptr[0x20]; 3318 3319 u8 assert_callra[0x20]; 3320 3321 u8 reserved_at_140[0x40]; 3322 3323 u8 fw_version[0x20]; 3324 3325 u8 hw_id[0x20]; 3326 3327 u8 reserved_at_1c0[0x20]; 3328 3329 u8 irisc_index[0x8]; 3330 u8 synd[0x8]; 3331 u8 ext_synd[0x10]; 3332 }; 3333 3334 struct mlx5_ifc_register_loopback_control_bits { 3335 u8 no_lb[0x1]; 3336 u8 reserved_at_1[0x7]; 3337 u8 port[0x8]; 3338 u8 reserved_at_10[0x10]; 3339 3340 u8 reserved_at_20[0x60]; 3341 }; 3342 3343 struct mlx5_ifc_vport_tc_element_bits { 3344 u8 traffic_class[0x4]; 3345 u8 reserved_at_4[0xc]; 3346 u8 vport_number[0x10]; 3347 }; 3348 3349 struct mlx5_ifc_vport_element_bits { 3350 u8 reserved_at_0[0x10]; 3351 u8 vport_number[0x10]; 3352 }; 3353 3354 enum { 3355 TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0, 3356 TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1, 3357 TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2, 3358 }; 3359 3360 struct mlx5_ifc_tsar_element_bits { 3361 u8 reserved_at_0[0x8]; 3362 u8 tsar_type[0x8]; 3363 u8 reserved_at_10[0x10]; 3364 }; 3365 3366 enum { 3367 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0, 3368 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1, 3369 }; 3370 3371 struct mlx5_ifc_teardown_hca_out_bits { 3372 u8 status[0x8]; 3373 u8 reserved_at_8[0x18]; 3374 3375 u8 syndrome[0x20]; 3376 3377 u8 reserved_at_40[0x3f]; 3378 3379 u8 state[0x1]; 3380 }; 3381 3382 enum { 3383 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0, 3384 MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE = 0x1, 3385 MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN = 0x2, 3386 }; 3387 3388 struct mlx5_ifc_teardown_hca_in_bits { 3389 u8 opcode[0x10]; 3390 u8 reserved_at_10[0x10]; 3391 3392 u8 reserved_at_20[0x10]; 3393 u8 op_mod[0x10]; 3394 3395 u8 reserved_at_40[0x10]; 3396 u8 profile[0x10]; 3397 3398 u8 reserved_at_60[0x20]; 3399 }; 3400 3401 struct mlx5_ifc_sqerr2rts_qp_out_bits { 3402 u8 status[0x8]; 3403 u8 reserved_at_8[0x18]; 3404 3405 u8 syndrome[0x20]; 3406 3407 u8 reserved_at_40[0x40]; 3408 }; 3409 3410 struct mlx5_ifc_sqerr2rts_qp_in_bits { 3411 u8 opcode[0x10]; 3412 u8 uid[0x10]; 3413 3414 u8 reserved_at_20[0x10]; 3415 u8 op_mod[0x10]; 3416 3417 u8 reserved_at_40[0x8]; 3418 u8 qpn[0x18]; 3419 3420 u8 reserved_at_60[0x20]; 3421 3422 u8 opt_param_mask[0x20]; 3423 3424 u8 reserved_at_a0[0x20]; 3425 3426 struct mlx5_ifc_qpc_bits qpc; 3427 3428 u8 reserved_at_800[0x80]; 3429 }; 3430 3431 struct mlx5_ifc_sqd2rts_qp_out_bits { 3432 u8 status[0x8]; 3433 u8 reserved_at_8[0x18]; 3434 3435 u8 syndrome[0x20]; 3436 3437 u8 reserved_at_40[0x40]; 3438 }; 3439 3440 struct mlx5_ifc_sqd2rts_qp_in_bits { 3441 u8 opcode[0x10]; 3442 u8 uid[0x10]; 3443 3444 u8 reserved_at_20[0x10]; 3445 u8 op_mod[0x10]; 3446 3447 u8 reserved_at_40[0x8]; 3448 u8 qpn[0x18]; 3449 3450 u8 reserved_at_60[0x20]; 3451 3452 u8 opt_param_mask[0x20]; 3453 3454 u8 reserved_at_a0[0x20]; 3455 3456 struct mlx5_ifc_qpc_bits qpc; 3457 3458 u8 reserved_at_800[0x80]; 3459 }; 3460 3461 struct mlx5_ifc_set_roce_address_out_bits { 3462 u8 status[0x8]; 3463 u8 reserved_at_8[0x18]; 3464 3465 u8 syndrome[0x20]; 3466 3467 u8 reserved_at_40[0x40]; 3468 }; 3469 3470 struct mlx5_ifc_set_roce_address_in_bits { 3471 u8 opcode[0x10]; 3472 u8 reserved_at_10[0x10]; 3473 3474 u8 reserved_at_20[0x10]; 3475 u8 op_mod[0x10]; 3476 3477 u8 roce_address_index[0x10]; 3478 u8 reserved_at_50[0xc]; 3479 u8 vhca_port_num[0x4]; 3480 3481 u8 reserved_at_60[0x20]; 3482 3483 struct mlx5_ifc_roce_addr_layout_bits roce_address; 3484 }; 3485 3486 struct mlx5_ifc_set_mad_demux_out_bits { 3487 u8 status[0x8]; 3488 u8 reserved_at_8[0x18]; 3489 3490 u8 syndrome[0x20]; 3491 3492 u8 reserved_at_40[0x40]; 3493 }; 3494 3495 enum { 3496 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0, 3497 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2, 3498 }; 3499 3500 struct mlx5_ifc_set_mad_demux_in_bits { 3501 u8 opcode[0x10]; 3502 u8 reserved_at_10[0x10]; 3503 3504 u8 reserved_at_20[0x10]; 3505 u8 op_mod[0x10]; 3506 3507 u8 reserved_at_40[0x20]; 3508 3509 u8 reserved_at_60[0x6]; 3510 u8 demux_mode[0x2]; 3511 u8 reserved_at_68[0x18]; 3512 }; 3513 3514 struct mlx5_ifc_set_l2_table_entry_out_bits { 3515 u8 status[0x8]; 3516 u8 reserved_at_8[0x18]; 3517 3518 u8 syndrome[0x20]; 3519 3520 u8 reserved_at_40[0x40]; 3521 }; 3522 3523 struct mlx5_ifc_set_l2_table_entry_in_bits { 3524 u8 opcode[0x10]; 3525 u8 reserved_at_10[0x10]; 3526 3527 u8 reserved_at_20[0x10]; 3528 u8 op_mod[0x10]; 3529 3530 u8 reserved_at_40[0x60]; 3531 3532 u8 reserved_at_a0[0x8]; 3533 u8 table_index[0x18]; 3534 3535 u8 reserved_at_c0[0x20]; 3536 3537 u8 reserved_at_e0[0x13]; 3538 u8 vlan_valid[0x1]; 3539 u8 vlan[0xc]; 3540 3541 struct mlx5_ifc_mac_address_layout_bits mac_address; 3542 3543 u8 reserved_at_140[0xc0]; 3544 }; 3545 3546 struct mlx5_ifc_set_issi_out_bits { 3547 u8 status[0x8]; 3548 u8 reserved_at_8[0x18]; 3549 3550 u8 syndrome[0x20]; 3551 3552 u8 reserved_at_40[0x40]; 3553 }; 3554 3555 struct mlx5_ifc_set_issi_in_bits { 3556 u8 opcode[0x10]; 3557 u8 reserved_at_10[0x10]; 3558 3559 u8 reserved_at_20[0x10]; 3560 u8 op_mod[0x10]; 3561 3562 u8 reserved_at_40[0x10]; 3563 u8 current_issi[0x10]; 3564 3565 u8 reserved_at_60[0x20]; 3566 }; 3567 3568 struct mlx5_ifc_set_hca_cap_out_bits { 3569 u8 status[0x8]; 3570 u8 reserved_at_8[0x18]; 3571 3572 u8 syndrome[0x20]; 3573 3574 u8 reserved_at_40[0x40]; 3575 }; 3576 3577 struct mlx5_ifc_set_hca_cap_in_bits { 3578 u8 opcode[0x10]; 3579 u8 reserved_at_10[0x10]; 3580 3581 u8 reserved_at_20[0x10]; 3582 u8 op_mod[0x10]; 3583 3584 u8 reserved_at_40[0x40]; 3585 3586 union mlx5_ifc_hca_cap_union_bits capability; 3587 }; 3588 3589 enum { 3590 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0, 3591 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1, 3592 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2, 3593 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3 3594 }; 3595 3596 struct mlx5_ifc_set_fte_out_bits { 3597 u8 status[0x8]; 3598 u8 reserved_at_8[0x18]; 3599 3600 u8 syndrome[0x20]; 3601 3602 u8 reserved_at_40[0x40]; 3603 }; 3604 3605 struct mlx5_ifc_set_fte_in_bits { 3606 u8 opcode[0x10]; 3607 u8 reserved_at_10[0x10]; 3608 3609 u8 reserved_at_20[0x10]; 3610 u8 op_mod[0x10]; 3611 3612 u8 other_vport[0x1]; 3613 u8 reserved_at_41[0xf]; 3614 u8 vport_number[0x10]; 3615 3616 u8 reserved_at_60[0x20]; 3617 3618 u8 table_type[0x8]; 3619 u8 reserved_at_88[0x18]; 3620 3621 u8 reserved_at_a0[0x8]; 3622 u8 table_id[0x18]; 3623 3624 u8 reserved_at_c0[0x18]; 3625 u8 modify_enable_mask[0x8]; 3626 3627 u8 reserved_at_e0[0x20]; 3628 3629 u8 flow_index[0x20]; 3630 3631 u8 reserved_at_120[0xe0]; 3632 3633 struct mlx5_ifc_flow_context_bits flow_context; 3634 }; 3635 3636 struct mlx5_ifc_rts2rts_qp_out_bits { 3637 u8 status[0x8]; 3638 u8 reserved_at_8[0x18]; 3639 3640 u8 syndrome[0x20]; 3641 3642 u8 reserved_at_40[0x40]; 3643 }; 3644 3645 struct mlx5_ifc_rts2rts_qp_in_bits { 3646 u8 opcode[0x10]; 3647 u8 uid[0x10]; 3648 3649 u8 reserved_at_20[0x10]; 3650 u8 op_mod[0x10]; 3651 3652 u8 reserved_at_40[0x8]; 3653 u8 qpn[0x18]; 3654 3655 u8 reserved_at_60[0x20]; 3656 3657 u8 opt_param_mask[0x20]; 3658 3659 u8 reserved_at_a0[0x20]; 3660 3661 struct mlx5_ifc_qpc_bits qpc; 3662 3663 u8 reserved_at_800[0x80]; 3664 }; 3665 3666 struct mlx5_ifc_rtr2rts_qp_out_bits { 3667 u8 status[0x8]; 3668 u8 reserved_at_8[0x18]; 3669 3670 u8 syndrome[0x20]; 3671 3672 u8 reserved_at_40[0x40]; 3673 }; 3674 3675 struct mlx5_ifc_rtr2rts_qp_in_bits { 3676 u8 opcode[0x10]; 3677 u8 uid[0x10]; 3678 3679 u8 reserved_at_20[0x10]; 3680 u8 op_mod[0x10]; 3681 3682 u8 reserved_at_40[0x8]; 3683 u8 qpn[0x18]; 3684 3685 u8 reserved_at_60[0x20]; 3686 3687 u8 opt_param_mask[0x20]; 3688 3689 u8 reserved_at_a0[0x20]; 3690 3691 struct mlx5_ifc_qpc_bits qpc; 3692 3693 u8 reserved_at_800[0x80]; 3694 }; 3695 3696 struct mlx5_ifc_rst2init_qp_out_bits { 3697 u8 status[0x8]; 3698 u8 reserved_at_8[0x18]; 3699 3700 u8 syndrome[0x20]; 3701 3702 u8 reserved_at_40[0x40]; 3703 }; 3704 3705 struct mlx5_ifc_rst2init_qp_in_bits { 3706 u8 opcode[0x10]; 3707 u8 uid[0x10]; 3708 3709 u8 reserved_at_20[0x10]; 3710 u8 op_mod[0x10]; 3711 3712 u8 reserved_at_40[0x8]; 3713 u8 qpn[0x18]; 3714 3715 u8 reserved_at_60[0x20]; 3716 3717 u8 opt_param_mask[0x20]; 3718 3719 u8 reserved_at_a0[0x20]; 3720 3721 struct mlx5_ifc_qpc_bits qpc; 3722 3723 u8 reserved_at_800[0x80]; 3724 }; 3725 3726 struct mlx5_ifc_query_xrq_out_bits { 3727 u8 status[0x8]; 3728 u8 reserved_at_8[0x18]; 3729 3730 u8 syndrome[0x20]; 3731 3732 u8 reserved_at_40[0x40]; 3733 3734 struct mlx5_ifc_xrqc_bits xrq_context; 3735 }; 3736 3737 struct mlx5_ifc_query_xrq_in_bits { 3738 u8 opcode[0x10]; 3739 u8 reserved_at_10[0x10]; 3740 3741 u8 reserved_at_20[0x10]; 3742 u8 op_mod[0x10]; 3743 3744 u8 reserved_at_40[0x8]; 3745 u8 xrqn[0x18]; 3746 3747 u8 reserved_at_60[0x20]; 3748 }; 3749 3750 struct mlx5_ifc_query_xrc_srq_out_bits { 3751 u8 status[0x8]; 3752 u8 reserved_at_8[0x18]; 3753 3754 u8 syndrome[0x20]; 3755 3756 u8 reserved_at_40[0x40]; 3757 3758 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 3759 3760 u8 reserved_at_280[0x600]; 3761 3762 u8 pas[0][0x40]; 3763 }; 3764 3765 struct mlx5_ifc_query_xrc_srq_in_bits { 3766 u8 opcode[0x10]; 3767 u8 reserved_at_10[0x10]; 3768 3769 u8 reserved_at_20[0x10]; 3770 u8 op_mod[0x10]; 3771 3772 u8 reserved_at_40[0x8]; 3773 u8 xrc_srqn[0x18]; 3774 3775 u8 reserved_at_60[0x20]; 3776 }; 3777 3778 enum { 3779 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0, 3780 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1, 3781 }; 3782 3783 struct mlx5_ifc_query_vport_state_out_bits { 3784 u8 status[0x8]; 3785 u8 reserved_at_8[0x18]; 3786 3787 u8 syndrome[0x20]; 3788 3789 u8 reserved_at_40[0x20]; 3790 3791 u8 reserved_at_60[0x18]; 3792 u8 admin_state[0x4]; 3793 u8 state[0x4]; 3794 }; 3795 3796 enum { 3797 MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT = 0x0, 3798 MLX5_VPORT_STATE_OP_MOD_ESW_VPORT = 0x1, 3799 }; 3800 3801 struct mlx5_ifc_query_vport_state_in_bits { 3802 u8 opcode[0x10]; 3803 u8 reserved_at_10[0x10]; 3804 3805 u8 reserved_at_20[0x10]; 3806 u8 op_mod[0x10]; 3807 3808 u8 other_vport[0x1]; 3809 u8 reserved_at_41[0xf]; 3810 u8 vport_number[0x10]; 3811 3812 u8 reserved_at_60[0x20]; 3813 }; 3814 3815 struct mlx5_ifc_query_vnic_env_out_bits { 3816 u8 status[0x8]; 3817 u8 reserved_at_8[0x18]; 3818 3819 u8 syndrome[0x20]; 3820 3821 u8 reserved_at_40[0x40]; 3822 3823 struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env; 3824 }; 3825 3826 enum { 3827 MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS = 0x0, 3828 }; 3829 3830 struct mlx5_ifc_query_vnic_env_in_bits { 3831 u8 opcode[0x10]; 3832 u8 reserved_at_10[0x10]; 3833 3834 u8 reserved_at_20[0x10]; 3835 u8 op_mod[0x10]; 3836 3837 u8 other_vport[0x1]; 3838 u8 reserved_at_41[0xf]; 3839 u8 vport_number[0x10]; 3840 3841 u8 reserved_at_60[0x20]; 3842 }; 3843 3844 struct mlx5_ifc_query_vport_counter_out_bits { 3845 u8 status[0x8]; 3846 u8 reserved_at_8[0x18]; 3847 3848 u8 syndrome[0x20]; 3849 3850 u8 reserved_at_40[0x40]; 3851 3852 struct mlx5_ifc_traffic_counter_bits received_errors; 3853 3854 struct mlx5_ifc_traffic_counter_bits transmit_errors; 3855 3856 struct mlx5_ifc_traffic_counter_bits received_ib_unicast; 3857 3858 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast; 3859 3860 struct mlx5_ifc_traffic_counter_bits received_ib_multicast; 3861 3862 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast; 3863 3864 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast; 3865 3866 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast; 3867 3868 struct mlx5_ifc_traffic_counter_bits received_eth_unicast; 3869 3870 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast; 3871 3872 struct mlx5_ifc_traffic_counter_bits received_eth_multicast; 3873 3874 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast; 3875 3876 u8 reserved_at_680[0xa00]; 3877 }; 3878 3879 enum { 3880 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0, 3881 }; 3882 3883 struct mlx5_ifc_query_vport_counter_in_bits { 3884 u8 opcode[0x10]; 3885 u8 reserved_at_10[0x10]; 3886 3887 u8 reserved_at_20[0x10]; 3888 u8 op_mod[0x10]; 3889 3890 u8 other_vport[0x1]; 3891 u8 reserved_at_41[0xb]; 3892 u8 port_num[0x4]; 3893 u8 vport_number[0x10]; 3894 3895 u8 reserved_at_60[0x60]; 3896 3897 u8 clear[0x1]; 3898 u8 reserved_at_c1[0x1f]; 3899 3900 u8 reserved_at_e0[0x20]; 3901 }; 3902 3903 struct mlx5_ifc_query_tis_out_bits { 3904 u8 status[0x8]; 3905 u8 reserved_at_8[0x18]; 3906 3907 u8 syndrome[0x20]; 3908 3909 u8 reserved_at_40[0x40]; 3910 3911 struct mlx5_ifc_tisc_bits tis_context; 3912 }; 3913 3914 struct mlx5_ifc_query_tis_in_bits { 3915 u8 opcode[0x10]; 3916 u8 reserved_at_10[0x10]; 3917 3918 u8 reserved_at_20[0x10]; 3919 u8 op_mod[0x10]; 3920 3921 u8 reserved_at_40[0x8]; 3922 u8 tisn[0x18]; 3923 3924 u8 reserved_at_60[0x20]; 3925 }; 3926 3927 struct mlx5_ifc_query_tir_out_bits { 3928 u8 status[0x8]; 3929 u8 reserved_at_8[0x18]; 3930 3931 u8 syndrome[0x20]; 3932 3933 u8 reserved_at_40[0xc0]; 3934 3935 struct mlx5_ifc_tirc_bits tir_context; 3936 }; 3937 3938 struct mlx5_ifc_query_tir_in_bits { 3939 u8 opcode[0x10]; 3940 u8 reserved_at_10[0x10]; 3941 3942 u8 reserved_at_20[0x10]; 3943 u8 op_mod[0x10]; 3944 3945 u8 reserved_at_40[0x8]; 3946 u8 tirn[0x18]; 3947 3948 u8 reserved_at_60[0x20]; 3949 }; 3950 3951 struct mlx5_ifc_query_srq_out_bits { 3952 u8 status[0x8]; 3953 u8 reserved_at_8[0x18]; 3954 3955 u8 syndrome[0x20]; 3956 3957 u8 reserved_at_40[0x40]; 3958 3959 struct mlx5_ifc_srqc_bits srq_context_entry; 3960 3961 u8 reserved_at_280[0x600]; 3962 3963 u8 pas[0][0x40]; 3964 }; 3965 3966 struct mlx5_ifc_query_srq_in_bits { 3967 u8 opcode[0x10]; 3968 u8 reserved_at_10[0x10]; 3969 3970 u8 reserved_at_20[0x10]; 3971 u8 op_mod[0x10]; 3972 3973 u8 reserved_at_40[0x8]; 3974 u8 srqn[0x18]; 3975 3976 u8 reserved_at_60[0x20]; 3977 }; 3978 3979 struct mlx5_ifc_query_sq_out_bits { 3980 u8 status[0x8]; 3981 u8 reserved_at_8[0x18]; 3982 3983 u8 syndrome[0x20]; 3984 3985 u8 reserved_at_40[0xc0]; 3986 3987 struct mlx5_ifc_sqc_bits sq_context; 3988 }; 3989 3990 struct mlx5_ifc_query_sq_in_bits { 3991 u8 opcode[0x10]; 3992 u8 reserved_at_10[0x10]; 3993 3994 u8 reserved_at_20[0x10]; 3995 u8 op_mod[0x10]; 3996 3997 u8 reserved_at_40[0x8]; 3998 u8 sqn[0x18]; 3999 4000 u8 reserved_at_60[0x20]; 4001 }; 4002 4003 struct mlx5_ifc_query_special_contexts_out_bits { 4004 u8 status[0x8]; 4005 u8 reserved_at_8[0x18]; 4006 4007 u8 syndrome[0x20]; 4008 4009 u8 dump_fill_mkey[0x20]; 4010 4011 u8 resd_lkey[0x20]; 4012 4013 u8 null_mkey[0x20]; 4014 4015 u8 reserved_at_a0[0x60]; 4016 }; 4017 4018 struct mlx5_ifc_query_special_contexts_in_bits { 4019 u8 opcode[0x10]; 4020 u8 reserved_at_10[0x10]; 4021 4022 u8 reserved_at_20[0x10]; 4023 u8 op_mod[0x10]; 4024 4025 u8 reserved_at_40[0x40]; 4026 }; 4027 4028 struct mlx5_ifc_query_scheduling_element_out_bits { 4029 u8 opcode[0x10]; 4030 u8 reserved_at_10[0x10]; 4031 4032 u8 reserved_at_20[0x10]; 4033 u8 op_mod[0x10]; 4034 4035 u8 reserved_at_40[0xc0]; 4036 4037 struct mlx5_ifc_scheduling_context_bits scheduling_context; 4038 4039 u8 reserved_at_300[0x100]; 4040 }; 4041 4042 enum { 4043 SCHEDULING_HIERARCHY_E_SWITCH = 0x2, 4044 }; 4045 4046 struct mlx5_ifc_query_scheduling_element_in_bits { 4047 u8 opcode[0x10]; 4048 u8 reserved_at_10[0x10]; 4049 4050 u8 reserved_at_20[0x10]; 4051 u8 op_mod[0x10]; 4052 4053 u8 scheduling_hierarchy[0x8]; 4054 u8 reserved_at_48[0x18]; 4055 4056 u8 scheduling_element_id[0x20]; 4057 4058 u8 reserved_at_80[0x180]; 4059 }; 4060 4061 struct mlx5_ifc_query_rqt_out_bits { 4062 u8 status[0x8]; 4063 u8 reserved_at_8[0x18]; 4064 4065 u8 syndrome[0x20]; 4066 4067 u8 reserved_at_40[0xc0]; 4068 4069 struct mlx5_ifc_rqtc_bits rqt_context; 4070 }; 4071 4072 struct mlx5_ifc_query_rqt_in_bits { 4073 u8 opcode[0x10]; 4074 u8 reserved_at_10[0x10]; 4075 4076 u8 reserved_at_20[0x10]; 4077 u8 op_mod[0x10]; 4078 4079 u8 reserved_at_40[0x8]; 4080 u8 rqtn[0x18]; 4081 4082 u8 reserved_at_60[0x20]; 4083 }; 4084 4085 struct mlx5_ifc_query_rq_out_bits { 4086 u8 status[0x8]; 4087 u8 reserved_at_8[0x18]; 4088 4089 u8 syndrome[0x20]; 4090 4091 u8 reserved_at_40[0xc0]; 4092 4093 struct mlx5_ifc_rqc_bits rq_context; 4094 }; 4095 4096 struct mlx5_ifc_query_rq_in_bits { 4097 u8 opcode[0x10]; 4098 u8 reserved_at_10[0x10]; 4099 4100 u8 reserved_at_20[0x10]; 4101 u8 op_mod[0x10]; 4102 4103 u8 reserved_at_40[0x8]; 4104 u8 rqn[0x18]; 4105 4106 u8 reserved_at_60[0x20]; 4107 }; 4108 4109 struct mlx5_ifc_query_roce_address_out_bits { 4110 u8 status[0x8]; 4111 u8 reserved_at_8[0x18]; 4112 4113 u8 syndrome[0x20]; 4114 4115 u8 reserved_at_40[0x40]; 4116 4117 struct mlx5_ifc_roce_addr_layout_bits roce_address; 4118 }; 4119 4120 struct mlx5_ifc_query_roce_address_in_bits { 4121 u8 opcode[0x10]; 4122 u8 reserved_at_10[0x10]; 4123 4124 u8 reserved_at_20[0x10]; 4125 u8 op_mod[0x10]; 4126 4127 u8 roce_address_index[0x10]; 4128 u8 reserved_at_50[0xc]; 4129 u8 vhca_port_num[0x4]; 4130 4131 u8 reserved_at_60[0x20]; 4132 }; 4133 4134 struct mlx5_ifc_query_rmp_out_bits { 4135 u8 status[0x8]; 4136 u8 reserved_at_8[0x18]; 4137 4138 u8 syndrome[0x20]; 4139 4140 u8 reserved_at_40[0xc0]; 4141 4142 struct mlx5_ifc_rmpc_bits rmp_context; 4143 }; 4144 4145 struct mlx5_ifc_query_rmp_in_bits { 4146 u8 opcode[0x10]; 4147 u8 reserved_at_10[0x10]; 4148 4149 u8 reserved_at_20[0x10]; 4150 u8 op_mod[0x10]; 4151 4152 u8 reserved_at_40[0x8]; 4153 u8 rmpn[0x18]; 4154 4155 u8 reserved_at_60[0x20]; 4156 }; 4157 4158 struct mlx5_ifc_query_qp_out_bits { 4159 u8 status[0x8]; 4160 u8 reserved_at_8[0x18]; 4161 4162 u8 syndrome[0x20]; 4163 4164 u8 reserved_at_40[0x40]; 4165 4166 u8 opt_param_mask[0x20]; 4167 4168 u8 reserved_at_a0[0x20]; 4169 4170 struct mlx5_ifc_qpc_bits qpc; 4171 4172 u8 reserved_at_800[0x80]; 4173 4174 u8 pas[0][0x40]; 4175 }; 4176 4177 struct mlx5_ifc_query_qp_in_bits { 4178 u8 opcode[0x10]; 4179 u8 reserved_at_10[0x10]; 4180 4181 u8 reserved_at_20[0x10]; 4182 u8 op_mod[0x10]; 4183 4184 u8 reserved_at_40[0x8]; 4185 u8 qpn[0x18]; 4186 4187 u8 reserved_at_60[0x20]; 4188 }; 4189 4190 struct mlx5_ifc_query_q_counter_out_bits { 4191 u8 status[0x8]; 4192 u8 reserved_at_8[0x18]; 4193 4194 u8 syndrome[0x20]; 4195 4196 u8 reserved_at_40[0x40]; 4197 4198 u8 rx_write_requests[0x20]; 4199 4200 u8 reserved_at_a0[0x20]; 4201 4202 u8 rx_read_requests[0x20]; 4203 4204 u8 reserved_at_e0[0x20]; 4205 4206 u8 rx_atomic_requests[0x20]; 4207 4208 u8 reserved_at_120[0x20]; 4209 4210 u8 rx_dct_connect[0x20]; 4211 4212 u8 reserved_at_160[0x20]; 4213 4214 u8 out_of_buffer[0x20]; 4215 4216 u8 reserved_at_1a0[0x20]; 4217 4218 u8 out_of_sequence[0x20]; 4219 4220 u8 reserved_at_1e0[0x20]; 4221 4222 u8 duplicate_request[0x20]; 4223 4224 u8 reserved_at_220[0x20]; 4225 4226 u8 rnr_nak_retry_err[0x20]; 4227 4228 u8 reserved_at_260[0x20]; 4229 4230 u8 packet_seq_err[0x20]; 4231 4232 u8 reserved_at_2a0[0x20]; 4233 4234 u8 implied_nak_seq_err[0x20]; 4235 4236 u8 reserved_at_2e0[0x20]; 4237 4238 u8 local_ack_timeout_err[0x20]; 4239 4240 u8 reserved_at_320[0xa0]; 4241 4242 u8 resp_local_length_error[0x20]; 4243 4244 u8 req_local_length_error[0x20]; 4245 4246 u8 resp_local_qp_error[0x20]; 4247 4248 u8 local_operation_error[0x20]; 4249 4250 u8 resp_local_protection[0x20]; 4251 4252 u8 req_local_protection[0x20]; 4253 4254 u8 resp_cqe_error[0x20]; 4255 4256 u8 req_cqe_error[0x20]; 4257 4258 u8 req_mw_binding[0x20]; 4259 4260 u8 req_bad_response[0x20]; 4261 4262 u8 req_remote_invalid_request[0x20]; 4263 4264 u8 resp_remote_invalid_request[0x20]; 4265 4266 u8 req_remote_access_errors[0x20]; 4267 4268 u8 resp_remote_access_errors[0x20]; 4269 4270 u8 req_remote_operation_errors[0x20]; 4271 4272 u8 req_transport_retries_exceeded[0x20]; 4273 4274 u8 cq_overflow[0x20]; 4275 4276 u8 resp_cqe_flush_error[0x20]; 4277 4278 u8 req_cqe_flush_error[0x20]; 4279 4280 u8 reserved_at_620[0x1e0]; 4281 }; 4282 4283 struct mlx5_ifc_query_q_counter_in_bits { 4284 u8 opcode[0x10]; 4285 u8 reserved_at_10[0x10]; 4286 4287 u8 reserved_at_20[0x10]; 4288 u8 op_mod[0x10]; 4289 4290 u8 reserved_at_40[0x80]; 4291 4292 u8 clear[0x1]; 4293 u8 reserved_at_c1[0x1f]; 4294 4295 u8 reserved_at_e0[0x18]; 4296 u8 counter_set_id[0x8]; 4297 }; 4298 4299 struct mlx5_ifc_query_pages_out_bits { 4300 u8 status[0x8]; 4301 u8 reserved_at_8[0x18]; 4302 4303 u8 syndrome[0x20]; 4304 4305 u8 reserved_at_40[0x10]; 4306 u8 function_id[0x10]; 4307 4308 u8 num_pages[0x20]; 4309 }; 4310 4311 enum { 4312 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1, 4313 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2, 4314 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3, 4315 }; 4316 4317 struct mlx5_ifc_query_pages_in_bits { 4318 u8 opcode[0x10]; 4319 u8 reserved_at_10[0x10]; 4320 4321 u8 reserved_at_20[0x10]; 4322 u8 op_mod[0x10]; 4323 4324 u8 reserved_at_40[0x10]; 4325 u8 function_id[0x10]; 4326 4327 u8 reserved_at_60[0x20]; 4328 }; 4329 4330 struct mlx5_ifc_query_nic_vport_context_out_bits { 4331 u8 status[0x8]; 4332 u8 reserved_at_8[0x18]; 4333 4334 u8 syndrome[0x20]; 4335 4336 u8 reserved_at_40[0x40]; 4337 4338 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 4339 }; 4340 4341 struct mlx5_ifc_query_nic_vport_context_in_bits { 4342 u8 opcode[0x10]; 4343 u8 reserved_at_10[0x10]; 4344 4345 u8 reserved_at_20[0x10]; 4346 u8 op_mod[0x10]; 4347 4348 u8 other_vport[0x1]; 4349 u8 reserved_at_41[0xf]; 4350 u8 vport_number[0x10]; 4351 4352 u8 reserved_at_60[0x5]; 4353 u8 allowed_list_type[0x3]; 4354 u8 reserved_at_68[0x18]; 4355 }; 4356 4357 struct mlx5_ifc_query_mkey_out_bits { 4358 u8 status[0x8]; 4359 u8 reserved_at_8[0x18]; 4360 4361 u8 syndrome[0x20]; 4362 4363 u8 reserved_at_40[0x40]; 4364 4365 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 4366 4367 u8 reserved_at_280[0x600]; 4368 4369 u8 bsf0_klm0_pas_mtt0_1[16][0x8]; 4370 4371 u8 bsf1_klm1_pas_mtt2_3[16][0x8]; 4372 }; 4373 4374 struct mlx5_ifc_query_mkey_in_bits { 4375 u8 opcode[0x10]; 4376 u8 reserved_at_10[0x10]; 4377 4378 u8 reserved_at_20[0x10]; 4379 u8 op_mod[0x10]; 4380 4381 u8 reserved_at_40[0x8]; 4382 u8 mkey_index[0x18]; 4383 4384 u8 pg_access[0x1]; 4385 u8 reserved_at_61[0x1f]; 4386 }; 4387 4388 struct mlx5_ifc_query_mad_demux_out_bits { 4389 u8 status[0x8]; 4390 u8 reserved_at_8[0x18]; 4391 4392 u8 syndrome[0x20]; 4393 4394 u8 reserved_at_40[0x40]; 4395 4396 u8 mad_dumux_parameters_block[0x20]; 4397 }; 4398 4399 struct mlx5_ifc_query_mad_demux_in_bits { 4400 u8 opcode[0x10]; 4401 u8 reserved_at_10[0x10]; 4402 4403 u8 reserved_at_20[0x10]; 4404 u8 op_mod[0x10]; 4405 4406 u8 reserved_at_40[0x40]; 4407 }; 4408 4409 struct mlx5_ifc_query_l2_table_entry_out_bits { 4410 u8 status[0x8]; 4411 u8 reserved_at_8[0x18]; 4412 4413 u8 syndrome[0x20]; 4414 4415 u8 reserved_at_40[0xa0]; 4416 4417 u8 reserved_at_e0[0x13]; 4418 u8 vlan_valid[0x1]; 4419 u8 vlan[0xc]; 4420 4421 struct mlx5_ifc_mac_address_layout_bits mac_address; 4422 4423 u8 reserved_at_140[0xc0]; 4424 }; 4425 4426 struct mlx5_ifc_query_l2_table_entry_in_bits { 4427 u8 opcode[0x10]; 4428 u8 reserved_at_10[0x10]; 4429 4430 u8 reserved_at_20[0x10]; 4431 u8 op_mod[0x10]; 4432 4433 u8 reserved_at_40[0x60]; 4434 4435 u8 reserved_at_a0[0x8]; 4436 u8 table_index[0x18]; 4437 4438 u8 reserved_at_c0[0x140]; 4439 }; 4440 4441 struct mlx5_ifc_query_issi_out_bits { 4442 u8 status[0x8]; 4443 u8 reserved_at_8[0x18]; 4444 4445 u8 syndrome[0x20]; 4446 4447 u8 reserved_at_40[0x10]; 4448 u8 current_issi[0x10]; 4449 4450 u8 reserved_at_60[0xa0]; 4451 4452 u8 reserved_at_100[76][0x8]; 4453 u8 supported_issi_dw0[0x20]; 4454 }; 4455 4456 struct mlx5_ifc_query_issi_in_bits { 4457 u8 opcode[0x10]; 4458 u8 reserved_at_10[0x10]; 4459 4460 u8 reserved_at_20[0x10]; 4461 u8 op_mod[0x10]; 4462 4463 u8 reserved_at_40[0x40]; 4464 }; 4465 4466 struct mlx5_ifc_set_driver_version_out_bits { 4467 u8 status[0x8]; 4468 u8 reserved_0[0x18]; 4469 4470 u8 syndrome[0x20]; 4471 u8 reserved_1[0x40]; 4472 }; 4473 4474 struct mlx5_ifc_set_driver_version_in_bits { 4475 u8 opcode[0x10]; 4476 u8 reserved_0[0x10]; 4477 4478 u8 reserved_1[0x10]; 4479 u8 op_mod[0x10]; 4480 4481 u8 reserved_2[0x40]; 4482 u8 driver_version[64][0x8]; 4483 }; 4484 4485 struct mlx5_ifc_query_hca_vport_pkey_out_bits { 4486 u8 status[0x8]; 4487 u8 reserved_at_8[0x18]; 4488 4489 u8 syndrome[0x20]; 4490 4491 u8 reserved_at_40[0x40]; 4492 4493 struct mlx5_ifc_pkey_bits pkey[0]; 4494 }; 4495 4496 struct mlx5_ifc_query_hca_vport_pkey_in_bits { 4497 u8 opcode[0x10]; 4498 u8 reserved_at_10[0x10]; 4499 4500 u8 reserved_at_20[0x10]; 4501 u8 op_mod[0x10]; 4502 4503 u8 other_vport[0x1]; 4504 u8 reserved_at_41[0xb]; 4505 u8 port_num[0x4]; 4506 u8 vport_number[0x10]; 4507 4508 u8 reserved_at_60[0x10]; 4509 u8 pkey_index[0x10]; 4510 }; 4511 4512 enum { 4513 MLX5_HCA_VPORT_SEL_PORT_GUID = 1 << 0, 4514 MLX5_HCA_VPORT_SEL_NODE_GUID = 1 << 1, 4515 MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2, 4516 }; 4517 4518 struct mlx5_ifc_query_hca_vport_gid_out_bits { 4519 u8 status[0x8]; 4520 u8 reserved_at_8[0x18]; 4521 4522 u8 syndrome[0x20]; 4523 4524 u8 reserved_at_40[0x20]; 4525 4526 u8 gids_num[0x10]; 4527 u8 reserved_at_70[0x10]; 4528 4529 struct mlx5_ifc_array128_auto_bits gid[0]; 4530 }; 4531 4532 struct mlx5_ifc_query_hca_vport_gid_in_bits { 4533 u8 opcode[0x10]; 4534 u8 reserved_at_10[0x10]; 4535 4536 u8 reserved_at_20[0x10]; 4537 u8 op_mod[0x10]; 4538 4539 u8 other_vport[0x1]; 4540 u8 reserved_at_41[0xb]; 4541 u8 port_num[0x4]; 4542 u8 vport_number[0x10]; 4543 4544 u8 reserved_at_60[0x10]; 4545 u8 gid_index[0x10]; 4546 }; 4547 4548 struct mlx5_ifc_query_hca_vport_context_out_bits { 4549 u8 status[0x8]; 4550 u8 reserved_at_8[0x18]; 4551 4552 u8 syndrome[0x20]; 4553 4554 u8 reserved_at_40[0x40]; 4555 4556 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 4557 }; 4558 4559 struct mlx5_ifc_query_hca_vport_context_in_bits { 4560 u8 opcode[0x10]; 4561 u8 reserved_at_10[0x10]; 4562 4563 u8 reserved_at_20[0x10]; 4564 u8 op_mod[0x10]; 4565 4566 u8 other_vport[0x1]; 4567 u8 reserved_at_41[0xb]; 4568 u8 port_num[0x4]; 4569 u8 vport_number[0x10]; 4570 4571 u8 reserved_at_60[0x20]; 4572 }; 4573 4574 struct mlx5_ifc_query_hca_cap_out_bits { 4575 u8 status[0x8]; 4576 u8 reserved_at_8[0x18]; 4577 4578 u8 syndrome[0x20]; 4579 4580 u8 reserved_at_40[0x40]; 4581 4582 union mlx5_ifc_hca_cap_union_bits capability; 4583 }; 4584 4585 struct mlx5_ifc_query_hca_cap_in_bits { 4586 u8 opcode[0x10]; 4587 u8 reserved_at_10[0x10]; 4588 4589 u8 reserved_at_20[0x10]; 4590 u8 op_mod[0x10]; 4591 4592 u8 reserved_at_40[0x40]; 4593 }; 4594 4595 struct mlx5_ifc_query_flow_table_out_bits { 4596 u8 status[0x8]; 4597 u8 reserved_at_8[0x18]; 4598 4599 u8 syndrome[0x20]; 4600 4601 u8 reserved_at_40[0x80]; 4602 4603 u8 reserved_at_c0[0x8]; 4604 u8 level[0x8]; 4605 u8 reserved_at_d0[0x8]; 4606 u8 log_size[0x8]; 4607 4608 u8 reserved_at_e0[0x120]; 4609 }; 4610 4611 struct mlx5_ifc_query_flow_table_in_bits { 4612 u8 opcode[0x10]; 4613 u8 reserved_at_10[0x10]; 4614 4615 u8 reserved_at_20[0x10]; 4616 u8 op_mod[0x10]; 4617 4618 u8 reserved_at_40[0x40]; 4619 4620 u8 table_type[0x8]; 4621 u8 reserved_at_88[0x18]; 4622 4623 u8 reserved_at_a0[0x8]; 4624 u8 table_id[0x18]; 4625 4626 u8 reserved_at_c0[0x140]; 4627 }; 4628 4629 struct mlx5_ifc_query_fte_out_bits { 4630 u8 status[0x8]; 4631 u8 reserved_at_8[0x18]; 4632 4633 u8 syndrome[0x20]; 4634 4635 u8 reserved_at_40[0x1c0]; 4636 4637 struct mlx5_ifc_flow_context_bits flow_context; 4638 }; 4639 4640 struct mlx5_ifc_query_fte_in_bits { 4641 u8 opcode[0x10]; 4642 u8 reserved_at_10[0x10]; 4643 4644 u8 reserved_at_20[0x10]; 4645 u8 op_mod[0x10]; 4646 4647 u8 reserved_at_40[0x40]; 4648 4649 u8 table_type[0x8]; 4650 u8 reserved_at_88[0x18]; 4651 4652 u8 reserved_at_a0[0x8]; 4653 u8 table_id[0x18]; 4654 4655 u8 reserved_at_c0[0x40]; 4656 4657 u8 flow_index[0x20]; 4658 4659 u8 reserved_at_120[0xe0]; 4660 }; 4661 4662 enum { 4663 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 4664 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 4665 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 4666 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0X3, 4667 }; 4668 4669 struct mlx5_ifc_query_flow_group_out_bits { 4670 u8 status[0x8]; 4671 u8 reserved_at_8[0x18]; 4672 4673 u8 syndrome[0x20]; 4674 4675 u8 reserved_at_40[0xa0]; 4676 4677 u8 start_flow_index[0x20]; 4678 4679 u8 reserved_at_100[0x20]; 4680 4681 u8 end_flow_index[0x20]; 4682 4683 u8 reserved_at_140[0xa0]; 4684 4685 u8 reserved_at_1e0[0x18]; 4686 u8 match_criteria_enable[0x8]; 4687 4688 struct mlx5_ifc_fte_match_param_bits match_criteria; 4689 4690 u8 reserved_at_1200[0xe00]; 4691 }; 4692 4693 struct mlx5_ifc_query_flow_group_in_bits { 4694 u8 opcode[0x10]; 4695 u8 reserved_at_10[0x10]; 4696 4697 u8 reserved_at_20[0x10]; 4698 u8 op_mod[0x10]; 4699 4700 u8 reserved_at_40[0x40]; 4701 4702 u8 table_type[0x8]; 4703 u8 reserved_at_88[0x18]; 4704 4705 u8 reserved_at_a0[0x8]; 4706 u8 table_id[0x18]; 4707 4708 u8 group_id[0x20]; 4709 4710 u8 reserved_at_e0[0x120]; 4711 }; 4712 4713 struct mlx5_ifc_query_flow_counter_out_bits { 4714 u8 status[0x8]; 4715 u8 reserved_at_8[0x18]; 4716 4717 u8 syndrome[0x20]; 4718 4719 u8 reserved_at_40[0x40]; 4720 4721 struct mlx5_ifc_traffic_counter_bits flow_statistics[0]; 4722 }; 4723 4724 struct mlx5_ifc_query_flow_counter_in_bits { 4725 u8 opcode[0x10]; 4726 u8 reserved_at_10[0x10]; 4727 4728 u8 reserved_at_20[0x10]; 4729 u8 op_mod[0x10]; 4730 4731 u8 reserved_at_40[0x80]; 4732 4733 u8 clear[0x1]; 4734 u8 reserved_at_c1[0xf]; 4735 u8 num_of_counters[0x10]; 4736 4737 u8 flow_counter_id[0x20]; 4738 }; 4739 4740 struct mlx5_ifc_query_esw_vport_context_out_bits { 4741 u8 status[0x8]; 4742 u8 reserved_at_8[0x18]; 4743 4744 u8 syndrome[0x20]; 4745 4746 u8 reserved_at_40[0x40]; 4747 4748 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 4749 }; 4750 4751 struct mlx5_ifc_query_esw_vport_context_in_bits { 4752 u8 opcode[0x10]; 4753 u8 reserved_at_10[0x10]; 4754 4755 u8 reserved_at_20[0x10]; 4756 u8 op_mod[0x10]; 4757 4758 u8 other_vport[0x1]; 4759 u8 reserved_at_41[0xf]; 4760 u8 vport_number[0x10]; 4761 4762 u8 reserved_at_60[0x20]; 4763 }; 4764 4765 struct mlx5_ifc_modify_esw_vport_context_out_bits { 4766 u8 status[0x8]; 4767 u8 reserved_at_8[0x18]; 4768 4769 u8 syndrome[0x20]; 4770 4771 u8 reserved_at_40[0x40]; 4772 }; 4773 4774 struct mlx5_ifc_esw_vport_context_fields_select_bits { 4775 u8 reserved_at_0[0x1c]; 4776 u8 vport_cvlan_insert[0x1]; 4777 u8 vport_svlan_insert[0x1]; 4778 u8 vport_cvlan_strip[0x1]; 4779 u8 vport_svlan_strip[0x1]; 4780 }; 4781 4782 struct mlx5_ifc_modify_esw_vport_context_in_bits { 4783 u8 opcode[0x10]; 4784 u8 reserved_at_10[0x10]; 4785 4786 u8 reserved_at_20[0x10]; 4787 u8 op_mod[0x10]; 4788 4789 u8 other_vport[0x1]; 4790 u8 reserved_at_41[0xf]; 4791 u8 vport_number[0x10]; 4792 4793 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select; 4794 4795 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 4796 }; 4797 4798 struct mlx5_ifc_query_eq_out_bits { 4799 u8 status[0x8]; 4800 u8 reserved_at_8[0x18]; 4801 4802 u8 syndrome[0x20]; 4803 4804 u8 reserved_at_40[0x40]; 4805 4806 struct mlx5_ifc_eqc_bits eq_context_entry; 4807 4808 u8 reserved_at_280[0x40]; 4809 4810 u8 event_bitmask[0x40]; 4811 4812 u8 reserved_at_300[0x580]; 4813 4814 u8 pas[0][0x40]; 4815 }; 4816 4817 struct mlx5_ifc_query_eq_in_bits { 4818 u8 opcode[0x10]; 4819 u8 reserved_at_10[0x10]; 4820 4821 u8 reserved_at_20[0x10]; 4822 u8 op_mod[0x10]; 4823 4824 u8 reserved_at_40[0x18]; 4825 u8 eq_number[0x8]; 4826 4827 u8 reserved_at_60[0x20]; 4828 }; 4829 4830 struct mlx5_ifc_packet_reformat_context_in_bits { 4831 u8 reserved_at_0[0x5]; 4832 u8 reformat_type[0x3]; 4833 u8 reserved_at_8[0xe]; 4834 u8 reformat_data_size[0xa]; 4835 4836 u8 reserved_at_20[0x10]; 4837 u8 reformat_data[2][0x8]; 4838 4839 u8 more_reformat_data[0][0x8]; 4840 }; 4841 4842 struct mlx5_ifc_query_packet_reformat_context_out_bits { 4843 u8 status[0x8]; 4844 u8 reserved_at_8[0x18]; 4845 4846 u8 syndrome[0x20]; 4847 4848 u8 reserved_at_40[0xa0]; 4849 4850 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context[0]; 4851 }; 4852 4853 struct mlx5_ifc_query_packet_reformat_context_in_bits { 4854 u8 opcode[0x10]; 4855 u8 reserved_at_10[0x10]; 4856 4857 u8 reserved_at_20[0x10]; 4858 u8 op_mod[0x10]; 4859 4860 u8 packet_reformat_id[0x20]; 4861 4862 u8 reserved_at_60[0xa0]; 4863 }; 4864 4865 struct mlx5_ifc_alloc_packet_reformat_context_out_bits { 4866 u8 status[0x8]; 4867 u8 reserved_at_8[0x18]; 4868 4869 u8 syndrome[0x20]; 4870 4871 u8 packet_reformat_id[0x20]; 4872 4873 u8 reserved_at_60[0x20]; 4874 }; 4875 4876 enum { 4877 MLX5_REFORMAT_TYPE_L2_TO_VXLAN = 0x0, 4878 MLX5_REFORMAT_TYPE_L2_TO_NVGRE = 0x1, 4879 MLX5_REFORMAT_TYPE_L2_TO_L2_TUNNEL = 0x2, 4880 MLX5_REFORMAT_TYPE_L3_TUNNEL_TO_L2 = 0x3, 4881 MLX5_REFORMAT_TYPE_L2_TO_L3_TUNNEL = 0x4, 4882 }; 4883 4884 struct mlx5_ifc_alloc_packet_reformat_context_in_bits { 4885 u8 opcode[0x10]; 4886 u8 reserved_at_10[0x10]; 4887 4888 u8 reserved_at_20[0x10]; 4889 u8 op_mod[0x10]; 4890 4891 u8 reserved_at_40[0xa0]; 4892 4893 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context; 4894 }; 4895 4896 struct mlx5_ifc_dealloc_packet_reformat_context_out_bits { 4897 u8 status[0x8]; 4898 u8 reserved_at_8[0x18]; 4899 4900 u8 syndrome[0x20]; 4901 4902 u8 reserved_at_40[0x40]; 4903 }; 4904 4905 struct mlx5_ifc_dealloc_packet_reformat_context_in_bits { 4906 u8 opcode[0x10]; 4907 u8 reserved_at_10[0x10]; 4908 4909 u8 reserved_20[0x10]; 4910 u8 op_mod[0x10]; 4911 4912 u8 packet_reformat_id[0x20]; 4913 4914 u8 reserved_60[0x20]; 4915 }; 4916 4917 struct mlx5_ifc_set_action_in_bits { 4918 u8 action_type[0x4]; 4919 u8 field[0xc]; 4920 u8 reserved_at_10[0x3]; 4921 u8 offset[0x5]; 4922 u8 reserved_at_18[0x3]; 4923 u8 length[0x5]; 4924 4925 u8 data[0x20]; 4926 }; 4927 4928 struct mlx5_ifc_add_action_in_bits { 4929 u8 action_type[0x4]; 4930 u8 field[0xc]; 4931 u8 reserved_at_10[0x10]; 4932 4933 u8 data[0x20]; 4934 }; 4935 4936 union mlx5_ifc_set_action_in_add_action_in_auto_bits { 4937 struct mlx5_ifc_set_action_in_bits set_action_in; 4938 struct mlx5_ifc_add_action_in_bits add_action_in; 4939 u8 reserved_at_0[0x40]; 4940 }; 4941 4942 enum { 4943 MLX5_ACTION_TYPE_SET = 0x1, 4944 MLX5_ACTION_TYPE_ADD = 0x2, 4945 }; 4946 4947 enum { 4948 MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16 = 0x1, 4949 MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0 = 0x2, 4950 MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE = 0x3, 4951 MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16 = 0x4, 4952 MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0 = 0x5, 4953 MLX5_ACTION_IN_FIELD_OUT_IP_DSCP = 0x6, 4954 MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS = 0x7, 4955 MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT = 0x8, 4956 MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT = 0x9, 4957 MLX5_ACTION_IN_FIELD_OUT_IP_TTL = 0xa, 4958 MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT = 0xb, 4959 MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT = 0xc, 4960 MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96 = 0xd, 4961 MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64 = 0xe, 4962 MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32 = 0xf, 4963 MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0 = 0x10, 4964 MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96 = 0x11, 4965 MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64 = 0x12, 4966 MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32 = 0x13, 4967 MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0 = 0x14, 4968 MLX5_ACTION_IN_FIELD_OUT_SIPV4 = 0x15, 4969 MLX5_ACTION_IN_FIELD_OUT_DIPV4 = 0x16, 4970 MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47, 4971 }; 4972 4973 struct mlx5_ifc_alloc_modify_header_context_out_bits { 4974 u8 status[0x8]; 4975 u8 reserved_at_8[0x18]; 4976 4977 u8 syndrome[0x20]; 4978 4979 u8 modify_header_id[0x20]; 4980 4981 u8 reserved_at_60[0x20]; 4982 }; 4983 4984 struct mlx5_ifc_alloc_modify_header_context_in_bits { 4985 u8 opcode[0x10]; 4986 u8 reserved_at_10[0x10]; 4987 4988 u8 reserved_at_20[0x10]; 4989 u8 op_mod[0x10]; 4990 4991 u8 reserved_at_40[0x20]; 4992 4993 u8 table_type[0x8]; 4994 u8 reserved_at_68[0x10]; 4995 u8 num_of_actions[0x8]; 4996 4997 union mlx5_ifc_set_action_in_add_action_in_auto_bits actions[0]; 4998 }; 4999 5000 struct mlx5_ifc_dealloc_modify_header_context_out_bits { 5001 u8 status[0x8]; 5002 u8 reserved_at_8[0x18]; 5003 5004 u8 syndrome[0x20]; 5005 5006 u8 reserved_at_40[0x40]; 5007 }; 5008 5009 struct mlx5_ifc_dealloc_modify_header_context_in_bits { 5010 u8 opcode[0x10]; 5011 u8 reserved_at_10[0x10]; 5012 5013 u8 reserved_at_20[0x10]; 5014 u8 op_mod[0x10]; 5015 5016 u8 modify_header_id[0x20]; 5017 5018 u8 reserved_at_60[0x20]; 5019 }; 5020 5021 struct mlx5_ifc_query_dct_out_bits { 5022 u8 status[0x8]; 5023 u8 reserved_at_8[0x18]; 5024 5025 u8 syndrome[0x20]; 5026 5027 u8 reserved_at_40[0x40]; 5028 5029 struct mlx5_ifc_dctc_bits dct_context_entry; 5030 5031 u8 reserved_at_280[0x180]; 5032 }; 5033 5034 struct mlx5_ifc_query_dct_in_bits { 5035 u8 opcode[0x10]; 5036 u8 reserved_at_10[0x10]; 5037 5038 u8 reserved_at_20[0x10]; 5039 u8 op_mod[0x10]; 5040 5041 u8 reserved_at_40[0x8]; 5042 u8 dctn[0x18]; 5043 5044 u8 reserved_at_60[0x20]; 5045 }; 5046 5047 struct mlx5_ifc_query_cq_out_bits { 5048 u8 status[0x8]; 5049 u8 reserved_at_8[0x18]; 5050 5051 u8 syndrome[0x20]; 5052 5053 u8 reserved_at_40[0x40]; 5054 5055 struct mlx5_ifc_cqc_bits cq_context; 5056 5057 u8 reserved_at_280[0x600]; 5058 5059 u8 pas[0][0x40]; 5060 }; 5061 5062 struct mlx5_ifc_query_cq_in_bits { 5063 u8 opcode[0x10]; 5064 u8 reserved_at_10[0x10]; 5065 5066 u8 reserved_at_20[0x10]; 5067 u8 op_mod[0x10]; 5068 5069 u8 reserved_at_40[0x8]; 5070 u8 cqn[0x18]; 5071 5072 u8 reserved_at_60[0x20]; 5073 }; 5074 5075 struct mlx5_ifc_query_cong_status_out_bits { 5076 u8 status[0x8]; 5077 u8 reserved_at_8[0x18]; 5078 5079 u8 syndrome[0x20]; 5080 5081 u8 reserved_at_40[0x20]; 5082 5083 u8 enable[0x1]; 5084 u8 tag_enable[0x1]; 5085 u8 reserved_at_62[0x1e]; 5086 }; 5087 5088 struct mlx5_ifc_query_cong_status_in_bits { 5089 u8 opcode[0x10]; 5090 u8 reserved_at_10[0x10]; 5091 5092 u8 reserved_at_20[0x10]; 5093 u8 op_mod[0x10]; 5094 5095 u8 reserved_at_40[0x18]; 5096 u8 priority[0x4]; 5097 u8 cong_protocol[0x4]; 5098 5099 u8 reserved_at_60[0x20]; 5100 }; 5101 5102 struct mlx5_ifc_query_cong_statistics_out_bits { 5103 u8 status[0x8]; 5104 u8 reserved_at_8[0x18]; 5105 5106 u8 syndrome[0x20]; 5107 5108 u8 reserved_at_40[0x40]; 5109 5110 u8 rp_cur_flows[0x20]; 5111 5112 u8 sum_flows[0x20]; 5113 5114 u8 rp_cnp_ignored_high[0x20]; 5115 5116 u8 rp_cnp_ignored_low[0x20]; 5117 5118 u8 rp_cnp_handled_high[0x20]; 5119 5120 u8 rp_cnp_handled_low[0x20]; 5121 5122 u8 reserved_at_140[0x100]; 5123 5124 u8 time_stamp_high[0x20]; 5125 5126 u8 time_stamp_low[0x20]; 5127 5128 u8 accumulators_period[0x20]; 5129 5130 u8 np_ecn_marked_roce_packets_high[0x20]; 5131 5132 u8 np_ecn_marked_roce_packets_low[0x20]; 5133 5134 u8 np_cnp_sent_high[0x20]; 5135 5136 u8 np_cnp_sent_low[0x20]; 5137 5138 u8 reserved_at_320[0x560]; 5139 }; 5140 5141 struct mlx5_ifc_query_cong_statistics_in_bits { 5142 u8 opcode[0x10]; 5143 u8 reserved_at_10[0x10]; 5144 5145 u8 reserved_at_20[0x10]; 5146 u8 op_mod[0x10]; 5147 5148 u8 clear[0x1]; 5149 u8 reserved_at_41[0x1f]; 5150 5151 u8 reserved_at_60[0x20]; 5152 }; 5153 5154 struct mlx5_ifc_query_cong_params_out_bits { 5155 u8 status[0x8]; 5156 u8 reserved_at_8[0x18]; 5157 5158 u8 syndrome[0x20]; 5159 5160 u8 reserved_at_40[0x40]; 5161 5162 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 5163 }; 5164 5165 struct mlx5_ifc_query_cong_params_in_bits { 5166 u8 opcode[0x10]; 5167 u8 reserved_at_10[0x10]; 5168 5169 u8 reserved_at_20[0x10]; 5170 u8 op_mod[0x10]; 5171 5172 u8 reserved_at_40[0x1c]; 5173 u8 cong_protocol[0x4]; 5174 5175 u8 reserved_at_60[0x20]; 5176 }; 5177 5178 struct mlx5_ifc_query_adapter_out_bits { 5179 u8 status[0x8]; 5180 u8 reserved_at_8[0x18]; 5181 5182 u8 syndrome[0x20]; 5183 5184 u8 reserved_at_40[0x40]; 5185 5186 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct; 5187 }; 5188 5189 struct mlx5_ifc_query_adapter_in_bits { 5190 u8 opcode[0x10]; 5191 u8 reserved_at_10[0x10]; 5192 5193 u8 reserved_at_20[0x10]; 5194 u8 op_mod[0x10]; 5195 5196 u8 reserved_at_40[0x40]; 5197 }; 5198 5199 struct mlx5_ifc_qp_2rst_out_bits { 5200 u8 status[0x8]; 5201 u8 reserved_at_8[0x18]; 5202 5203 u8 syndrome[0x20]; 5204 5205 u8 reserved_at_40[0x40]; 5206 }; 5207 5208 struct mlx5_ifc_qp_2rst_in_bits { 5209 u8 opcode[0x10]; 5210 u8 uid[0x10]; 5211 5212 u8 reserved_at_20[0x10]; 5213 u8 op_mod[0x10]; 5214 5215 u8 reserved_at_40[0x8]; 5216 u8 qpn[0x18]; 5217 5218 u8 reserved_at_60[0x20]; 5219 }; 5220 5221 struct mlx5_ifc_qp_2err_out_bits { 5222 u8 status[0x8]; 5223 u8 reserved_at_8[0x18]; 5224 5225 u8 syndrome[0x20]; 5226 5227 u8 reserved_at_40[0x40]; 5228 }; 5229 5230 struct mlx5_ifc_qp_2err_in_bits { 5231 u8 opcode[0x10]; 5232 u8 uid[0x10]; 5233 5234 u8 reserved_at_20[0x10]; 5235 u8 op_mod[0x10]; 5236 5237 u8 reserved_at_40[0x8]; 5238 u8 qpn[0x18]; 5239 5240 u8 reserved_at_60[0x20]; 5241 }; 5242 5243 struct mlx5_ifc_page_fault_resume_out_bits { 5244 u8 status[0x8]; 5245 u8 reserved_at_8[0x18]; 5246 5247 u8 syndrome[0x20]; 5248 5249 u8 reserved_at_40[0x40]; 5250 }; 5251 5252 struct mlx5_ifc_page_fault_resume_in_bits { 5253 u8 opcode[0x10]; 5254 u8 reserved_at_10[0x10]; 5255 5256 u8 reserved_at_20[0x10]; 5257 u8 op_mod[0x10]; 5258 5259 u8 error[0x1]; 5260 u8 reserved_at_41[0x4]; 5261 u8 page_fault_type[0x3]; 5262 u8 wq_number[0x18]; 5263 5264 u8 reserved_at_60[0x8]; 5265 u8 token[0x18]; 5266 }; 5267 5268 struct mlx5_ifc_nop_out_bits { 5269 u8 status[0x8]; 5270 u8 reserved_at_8[0x18]; 5271 5272 u8 syndrome[0x20]; 5273 5274 u8 reserved_at_40[0x40]; 5275 }; 5276 5277 struct mlx5_ifc_nop_in_bits { 5278 u8 opcode[0x10]; 5279 u8 reserved_at_10[0x10]; 5280 5281 u8 reserved_at_20[0x10]; 5282 u8 op_mod[0x10]; 5283 5284 u8 reserved_at_40[0x40]; 5285 }; 5286 5287 struct mlx5_ifc_modify_vport_state_out_bits { 5288 u8 status[0x8]; 5289 u8 reserved_at_8[0x18]; 5290 5291 u8 syndrome[0x20]; 5292 5293 u8 reserved_at_40[0x40]; 5294 }; 5295 5296 struct mlx5_ifc_modify_vport_state_in_bits { 5297 u8 opcode[0x10]; 5298 u8 reserved_at_10[0x10]; 5299 5300 u8 reserved_at_20[0x10]; 5301 u8 op_mod[0x10]; 5302 5303 u8 other_vport[0x1]; 5304 u8 reserved_at_41[0xf]; 5305 u8 vport_number[0x10]; 5306 5307 u8 reserved_at_60[0x18]; 5308 u8 admin_state[0x4]; 5309 u8 reserved_at_7c[0x4]; 5310 }; 5311 5312 struct mlx5_ifc_modify_tis_out_bits { 5313 u8 status[0x8]; 5314 u8 reserved_at_8[0x18]; 5315 5316 u8 syndrome[0x20]; 5317 5318 u8 reserved_at_40[0x40]; 5319 }; 5320 5321 struct mlx5_ifc_modify_tis_bitmask_bits { 5322 u8 reserved_at_0[0x20]; 5323 5324 u8 reserved_at_20[0x1d]; 5325 u8 lag_tx_port_affinity[0x1]; 5326 u8 strict_lag_tx_port_affinity[0x1]; 5327 u8 prio[0x1]; 5328 }; 5329 5330 struct mlx5_ifc_modify_tis_in_bits { 5331 u8 opcode[0x10]; 5332 u8 uid[0x10]; 5333 5334 u8 reserved_at_20[0x10]; 5335 u8 op_mod[0x10]; 5336 5337 u8 reserved_at_40[0x8]; 5338 u8 tisn[0x18]; 5339 5340 u8 reserved_at_60[0x20]; 5341 5342 struct mlx5_ifc_modify_tis_bitmask_bits bitmask; 5343 5344 u8 reserved_at_c0[0x40]; 5345 5346 struct mlx5_ifc_tisc_bits ctx; 5347 }; 5348 5349 struct mlx5_ifc_modify_tir_bitmask_bits { 5350 u8 reserved_at_0[0x20]; 5351 5352 u8 reserved_at_20[0x1b]; 5353 u8 self_lb_en[0x1]; 5354 u8 reserved_at_3c[0x1]; 5355 u8 hash[0x1]; 5356 u8 reserved_at_3e[0x1]; 5357 u8 lro[0x1]; 5358 }; 5359 5360 struct mlx5_ifc_modify_tir_out_bits { 5361 u8 status[0x8]; 5362 u8 reserved_at_8[0x18]; 5363 5364 u8 syndrome[0x20]; 5365 5366 u8 reserved_at_40[0x40]; 5367 }; 5368 5369 struct mlx5_ifc_modify_tir_in_bits { 5370 u8 opcode[0x10]; 5371 u8 uid[0x10]; 5372 5373 u8 reserved_at_20[0x10]; 5374 u8 op_mod[0x10]; 5375 5376 u8 reserved_at_40[0x8]; 5377 u8 tirn[0x18]; 5378 5379 u8 reserved_at_60[0x20]; 5380 5381 struct mlx5_ifc_modify_tir_bitmask_bits bitmask; 5382 5383 u8 reserved_at_c0[0x40]; 5384 5385 struct mlx5_ifc_tirc_bits ctx; 5386 }; 5387 5388 struct mlx5_ifc_modify_sq_out_bits { 5389 u8 status[0x8]; 5390 u8 reserved_at_8[0x18]; 5391 5392 u8 syndrome[0x20]; 5393 5394 u8 reserved_at_40[0x40]; 5395 }; 5396 5397 struct mlx5_ifc_modify_sq_in_bits { 5398 u8 opcode[0x10]; 5399 u8 uid[0x10]; 5400 5401 u8 reserved_at_20[0x10]; 5402 u8 op_mod[0x10]; 5403 5404 u8 sq_state[0x4]; 5405 u8 reserved_at_44[0x4]; 5406 u8 sqn[0x18]; 5407 5408 u8 reserved_at_60[0x20]; 5409 5410 u8 modify_bitmask[0x40]; 5411 5412 u8 reserved_at_c0[0x40]; 5413 5414 struct mlx5_ifc_sqc_bits ctx; 5415 }; 5416 5417 struct mlx5_ifc_modify_scheduling_element_out_bits { 5418 u8 status[0x8]; 5419 u8 reserved_at_8[0x18]; 5420 5421 u8 syndrome[0x20]; 5422 5423 u8 reserved_at_40[0x1c0]; 5424 }; 5425 5426 enum { 5427 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1, 5428 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2, 5429 }; 5430 5431 struct mlx5_ifc_modify_scheduling_element_in_bits { 5432 u8 opcode[0x10]; 5433 u8 reserved_at_10[0x10]; 5434 5435 u8 reserved_at_20[0x10]; 5436 u8 op_mod[0x10]; 5437 5438 u8 scheduling_hierarchy[0x8]; 5439 u8 reserved_at_48[0x18]; 5440 5441 u8 scheduling_element_id[0x20]; 5442 5443 u8 reserved_at_80[0x20]; 5444 5445 u8 modify_bitmask[0x20]; 5446 5447 u8 reserved_at_c0[0x40]; 5448 5449 struct mlx5_ifc_scheduling_context_bits scheduling_context; 5450 5451 u8 reserved_at_300[0x100]; 5452 }; 5453 5454 struct mlx5_ifc_modify_rqt_out_bits { 5455 u8 status[0x8]; 5456 u8 reserved_at_8[0x18]; 5457 5458 u8 syndrome[0x20]; 5459 5460 u8 reserved_at_40[0x40]; 5461 }; 5462 5463 struct mlx5_ifc_rqt_bitmask_bits { 5464 u8 reserved_at_0[0x20]; 5465 5466 u8 reserved_at_20[0x1f]; 5467 u8 rqn_list[0x1]; 5468 }; 5469 5470 struct mlx5_ifc_modify_rqt_in_bits { 5471 u8 opcode[0x10]; 5472 u8 uid[0x10]; 5473 5474 u8 reserved_at_20[0x10]; 5475 u8 op_mod[0x10]; 5476 5477 u8 reserved_at_40[0x8]; 5478 u8 rqtn[0x18]; 5479 5480 u8 reserved_at_60[0x20]; 5481 5482 struct mlx5_ifc_rqt_bitmask_bits bitmask; 5483 5484 u8 reserved_at_c0[0x40]; 5485 5486 struct mlx5_ifc_rqtc_bits ctx; 5487 }; 5488 5489 struct mlx5_ifc_modify_rq_out_bits { 5490 u8 status[0x8]; 5491 u8 reserved_at_8[0x18]; 5492 5493 u8 syndrome[0x20]; 5494 5495 u8 reserved_at_40[0x40]; 5496 }; 5497 5498 enum { 5499 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1, 5500 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2, 5501 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3, 5502 }; 5503 5504 struct mlx5_ifc_modify_rq_in_bits { 5505 u8 opcode[0x10]; 5506 u8 uid[0x10]; 5507 5508 u8 reserved_at_20[0x10]; 5509 u8 op_mod[0x10]; 5510 5511 u8 rq_state[0x4]; 5512 u8 reserved_at_44[0x4]; 5513 u8 rqn[0x18]; 5514 5515 u8 reserved_at_60[0x20]; 5516 5517 u8 modify_bitmask[0x40]; 5518 5519 u8 reserved_at_c0[0x40]; 5520 5521 struct mlx5_ifc_rqc_bits ctx; 5522 }; 5523 5524 struct mlx5_ifc_modify_rmp_out_bits { 5525 u8 status[0x8]; 5526 u8 reserved_at_8[0x18]; 5527 5528 u8 syndrome[0x20]; 5529 5530 u8 reserved_at_40[0x40]; 5531 }; 5532 5533 struct mlx5_ifc_rmp_bitmask_bits { 5534 u8 reserved_at_0[0x20]; 5535 5536 u8 reserved_at_20[0x1f]; 5537 u8 lwm[0x1]; 5538 }; 5539 5540 struct mlx5_ifc_modify_rmp_in_bits { 5541 u8 opcode[0x10]; 5542 u8 uid[0x10]; 5543 5544 u8 reserved_at_20[0x10]; 5545 u8 op_mod[0x10]; 5546 5547 u8 rmp_state[0x4]; 5548 u8 reserved_at_44[0x4]; 5549 u8 rmpn[0x18]; 5550 5551 u8 reserved_at_60[0x20]; 5552 5553 struct mlx5_ifc_rmp_bitmask_bits bitmask; 5554 5555 u8 reserved_at_c0[0x40]; 5556 5557 struct mlx5_ifc_rmpc_bits ctx; 5558 }; 5559 5560 struct mlx5_ifc_modify_nic_vport_context_out_bits { 5561 u8 status[0x8]; 5562 u8 reserved_at_8[0x18]; 5563 5564 u8 syndrome[0x20]; 5565 5566 u8 reserved_at_40[0x40]; 5567 }; 5568 5569 struct mlx5_ifc_modify_nic_vport_field_select_bits { 5570 u8 reserved_at_0[0x12]; 5571 u8 affiliation[0x1]; 5572 u8 reserved_at_e[0x1]; 5573 u8 disable_uc_local_lb[0x1]; 5574 u8 disable_mc_local_lb[0x1]; 5575 u8 node_guid[0x1]; 5576 u8 port_guid[0x1]; 5577 u8 min_inline[0x1]; 5578 u8 mtu[0x1]; 5579 u8 change_event[0x1]; 5580 u8 promisc[0x1]; 5581 u8 permanent_address[0x1]; 5582 u8 addresses_list[0x1]; 5583 u8 roce_en[0x1]; 5584 u8 reserved_at_1f[0x1]; 5585 }; 5586 5587 struct mlx5_ifc_modify_nic_vport_context_in_bits { 5588 u8 opcode[0x10]; 5589 u8 reserved_at_10[0x10]; 5590 5591 u8 reserved_at_20[0x10]; 5592 u8 op_mod[0x10]; 5593 5594 u8 other_vport[0x1]; 5595 u8 reserved_at_41[0xf]; 5596 u8 vport_number[0x10]; 5597 5598 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select; 5599 5600 u8 reserved_at_80[0x780]; 5601 5602 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 5603 }; 5604 5605 struct mlx5_ifc_modify_hca_vport_context_out_bits { 5606 u8 status[0x8]; 5607 u8 reserved_at_8[0x18]; 5608 5609 u8 syndrome[0x20]; 5610 5611 u8 reserved_at_40[0x40]; 5612 }; 5613 5614 struct mlx5_ifc_modify_hca_vport_context_in_bits { 5615 u8 opcode[0x10]; 5616 u8 reserved_at_10[0x10]; 5617 5618 u8 reserved_at_20[0x10]; 5619 u8 op_mod[0x10]; 5620 5621 u8 other_vport[0x1]; 5622 u8 reserved_at_41[0xb]; 5623 u8 port_num[0x4]; 5624 u8 vport_number[0x10]; 5625 5626 u8 reserved_at_60[0x20]; 5627 5628 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 5629 }; 5630 5631 struct mlx5_ifc_modify_cq_out_bits { 5632 u8 status[0x8]; 5633 u8 reserved_at_8[0x18]; 5634 5635 u8 syndrome[0x20]; 5636 5637 u8 reserved_at_40[0x40]; 5638 }; 5639 5640 enum { 5641 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0, 5642 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1, 5643 }; 5644 5645 struct mlx5_ifc_modify_cq_in_bits { 5646 u8 opcode[0x10]; 5647 u8 uid[0x10]; 5648 5649 u8 reserved_at_20[0x10]; 5650 u8 op_mod[0x10]; 5651 5652 u8 reserved_at_40[0x8]; 5653 u8 cqn[0x18]; 5654 5655 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select; 5656 5657 struct mlx5_ifc_cqc_bits cq_context; 5658 5659 u8 reserved_at_280[0x40]; 5660 5661 u8 cq_umem_valid[0x1]; 5662 u8 reserved_at_2c1[0x5bf]; 5663 5664 u8 pas[0][0x40]; 5665 }; 5666 5667 struct mlx5_ifc_modify_cong_status_out_bits { 5668 u8 status[0x8]; 5669 u8 reserved_at_8[0x18]; 5670 5671 u8 syndrome[0x20]; 5672 5673 u8 reserved_at_40[0x40]; 5674 }; 5675 5676 struct mlx5_ifc_modify_cong_status_in_bits { 5677 u8 opcode[0x10]; 5678 u8 reserved_at_10[0x10]; 5679 5680 u8 reserved_at_20[0x10]; 5681 u8 op_mod[0x10]; 5682 5683 u8 reserved_at_40[0x18]; 5684 u8 priority[0x4]; 5685 u8 cong_protocol[0x4]; 5686 5687 u8 enable[0x1]; 5688 u8 tag_enable[0x1]; 5689 u8 reserved_at_62[0x1e]; 5690 }; 5691 5692 struct mlx5_ifc_modify_cong_params_out_bits { 5693 u8 status[0x8]; 5694 u8 reserved_at_8[0x18]; 5695 5696 u8 syndrome[0x20]; 5697 5698 u8 reserved_at_40[0x40]; 5699 }; 5700 5701 struct mlx5_ifc_modify_cong_params_in_bits { 5702 u8 opcode[0x10]; 5703 u8 reserved_at_10[0x10]; 5704 5705 u8 reserved_at_20[0x10]; 5706 u8 op_mod[0x10]; 5707 5708 u8 reserved_at_40[0x1c]; 5709 u8 cong_protocol[0x4]; 5710 5711 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select; 5712 5713 u8 reserved_at_80[0x80]; 5714 5715 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 5716 }; 5717 5718 struct mlx5_ifc_manage_pages_out_bits { 5719 u8 status[0x8]; 5720 u8 reserved_at_8[0x18]; 5721 5722 u8 syndrome[0x20]; 5723 5724 u8 output_num_entries[0x20]; 5725 5726 u8 reserved_at_60[0x20]; 5727 5728 u8 pas[0][0x40]; 5729 }; 5730 5731 enum { 5732 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL = 0x0, 5733 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS = 0x1, 5734 MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES = 0x2, 5735 }; 5736 5737 struct mlx5_ifc_manage_pages_in_bits { 5738 u8 opcode[0x10]; 5739 u8 reserved_at_10[0x10]; 5740 5741 u8 reserved_at_20[0x10]; 5742 u8 op_mod[0x10]; 5743 5744 u8 reserved_at_40[0x10]; 5745 u8 function_id[0x10]; 5746 5747 u8 input_num_entries[0x20]; 5748 5749 u8 pas[0][0x40]; 5750 }; 5751 5752 struct mlx5_ifc_mad_ifc_out_bits { 5753 u8 status[0x8]; 5754 u8 reserved_at_8[0x18]; 5755 5756 u8 syndrome[0x20]; 5757 5758 u8 reserved_at_40[0x40]; 5759 5760 u8 response_mad_packet[256][0x8]; 5761 }; 5762 5763 struct mlx5_ifc_mad_ifc_in_bits { 5764 u8 opcode[0x10]; 5765 u8 reserved_at_10[0x10]; 5766 5767 u8 reserved_at_20[0x10]; 5768 u8 op_mod[0x10]; 5769 5770 u8 remote_lid[0x10]; 5771 u8 reserved_at_50[0x8]; 5772 u8 port[0x8]; 5773 5774 u8 reserved_at_60[0x20]; 5775 5776 u8 mad[256][0x8]; 5777 }; 5778 5779 struct mlx5_ifc_init_hca_out_bits { 5780 u8 status[0x8]; 5781 u8 reserved_at_8[0x18]; 5782 5783 u8 syndrome[0x20]; 5784 5785 u8 reserved_at_40[0x40]; 5786 }; 5787 5788 struct mlx5_ifc_init_hca_in_bits { 5789 u8 opcode[0x10]; 5790 u8 reserved_at_10[0x10]; 5791 5792 u8 reserved_at_20[0x10]; 5793 u8 op_mod[0x10]; 5794 5795 u8 reserved_at_40[0x40]; 5796 u8 sw_owner_id[4][0x20]; 5797 }; 5798 5799 struct mlx5_ifc_init2rtr_qp_out_bits { 5800 u8 status[0x8]; 5801 u8 reserved_at_8[0x18]; 5802 5803 u8 syndrome[0x20]; 5804 5805 u8 reserved_at_40[0x40]; 5806 }; 5807 5808 struct mlx5_ifc_init2rtr_qp_in_bits { 5809 u8 opcode[0x10]; 5810 u8 uid[0x10]; 5811 5812 u8 reserved_at_20[0x10]; 5813 u8 op_mod[0x10]; 5814 5815 u8 reserved_at_40[0x8]; 5816 u8 qpn[0x18]; 5817 5818 u8 reserved_at_60[0x20]; 5819 5820 u8 opt_param_mask[0x20]; 5821 5822 u8 reserved_at_a0[0x20]; 5823 5824 struct mlx5_ifc_qpc_bits qpc; 5825 5826 u8 reserved_at_800[0x80]; 5827 }; 5828 5829 struct mlx5_ifc_init2init_qp_out_bits { 5830 u8 status[0x8]; 5831 u8 reserved_at_8[0x18]; 5832 5833 u8 syndrome[0x20]; 5834 5835 u8 reserved_at_40[0x40]; 5836 }; 5837 5838 struct mlx5_ifc_init2init_qp_in_bits { 5839 u8 opcode[0x10]; 5840 u8 uid[0x10]; 5841 5842 u8 reserved_at_20[0x10]; 5843 u8 op_mod[0x10]; 5844 5845 u8 reserved_at_40[0x8]; 5846 u8 qpn[0x18]; 5847 5848 u8 reserved_at_60[0x20]; 5849 5850 u8 opt_param_mask[0x20]; 5851 5852 u8 reserved_at_a0[0x20]; 5853 5854 struct mlx5_ifc_qpc_bits qpc; 5855 5856 u8 reserved_at_800[0x80]; 5857 }; 5858 5859 struct mlx5_ifc_get_dropped_packet_log_out_bits { 5860 u8 status[0x8]; 5861 u8 reserved_at_8[0x18]; 5862 5863 u8 syndrome[0x20]; 5864 5865 u8 reserved_at_40[0x40]; 5866 5867 u8 packet_headers_log[128][0x8]; 5868 5869 u8 packet_syndrome[64][0x8]; 5870 }; 5871 5872 struct mlx5_ifc_get_dropped_packet_log_in_bits { 5873 u8 opcode[0x10]; 5874 u8 reserved_at_10[0x10]; 5875 5876 u8 reserved_at_20[0x10]; 5877 u8 op_mod[0x10]; 5878 5879 u8 reserved_at_40[0x40]; 5880 }; 5881 5882 struct mlx5_ifc_gen_eqe_in_bits { 5883 u8 opcode[0x10]; 5884 u8 reserved_at_10[0x10]; 5885 5886 u8 reserved_at_20[0x10]; 5887 u8 op_mod[0x10]; 5888 5889 u8 reserved_at_40[0x18]; 5890 u8 eq_number[0x8]; 5891 5892 u8 reserved_at_60[0x20]; 5893 5894 u8 eqe[64][0x8]; 5895 }; 5896 5897 struct mlx5_ifc_gen_eq_out_bits { 5898 u8 status[0x8]; 5899 u8 reserved_at_8[0x18]; 5900 5901 u8 syndrome[0x20]; 5902 5903 u8 reserved_at_40[0x40]; 5904 }; 5905 5906 struct mlx5_ifc_enable_hca_out_bits { 5907 u8 status[0x8]; 5908 u8 reserved_at_8[0x18]; 5909 5910 u8 syndrome[0x20]; 5911 5912 u8 reserved_at_40[0x20]; 5913 }; 5914 5915 struct mlx5_ifc_enable_hca_in_bits { 5916 u8 opcode[0x10]; 5917 u8 reserved_at_10[0x10]; 5918 5919 u8 reserved_at_20[0x10]; 5920 u8 op_mod[0x10]; 5921 5922 u8 reserved_at_40[0x10]; 5923 u8 function_id[0x10]; 5924 5925 u8 reserved_at_60[0x20]; 5926 }; 5927 5928 struct mlx5_ifc_drain_dct_out_bits { 5929 u8 status[0x8]; 5930 u8 reserved_at_8[0x18]; 5931 5932 u8 syndrome[0x20]; 5933 5934 u8 reserved_at_40[0x40]; 5935 }; 5936 5937 struct mlx5_ifc_drain_dct_in_bits { 5938 u8 opcode[0x10]; 5939 u8 uid[0x10]; 5940 5941 u8 reserved_at_20[0x10]; 5942 u8 op_mod[0x10]; 5943 5944 u8 reserved_at_40[0x8]; 5945 u8 dctn[0x18]; 5946 5947 u8 reserved_at_60[0x20]; 5948 }; 5949 5950 struct mlx5_ifc_disable_hca_out_bits { 5951 u8 status[0x8]; 5952 u8 reserved_at_8[0x18]; 5953 5954 u8 syndrome[0x20]; 5955 5956 u8 reserved_at_40[0x20]; 5957 }; 5958 5959 struct mlx5_ifc_disable_hca_in_bits { 5960 u8 opcode[0x10]; 5961 u8 reserved_at_10[0x10]; 5962 5963 u8 reserved_at_20[0x10]; 5964 u8 op_mod[0x10]; 5965 5966 u8 reserved_at_40[0x10]; 5967 u8 function_id[0x10]; 5968 5969 u8 reserved_at_60[0x20]; 5970 }; 5971 5972 struct mlx5_ifc_detach_from_mcg_out_bits { 5973 u8 status[0x8]; 5974 u8 reserved_at_8[0x18]; 5975 5976 u8 syndrome[0x20]; 5977 5978 u8 reserved_at_40[0x40]; 5979 }; 5980 5981 struct mlx5_ifc_detach_from_mcg_in_bits { 5982 u8 opcode[0x10]; 5983 u8 uid[0x10]; 5984 5985 u8 reserved_at_20[0x10]; 5986 u8 op_mod[0x10]; 5987 5988 u8 reserved_at_40[0x8]; 5989 u8 qpn[0x18]; 5990 5991 u8 reserved_at_60[0x20]; 5992 5993 u8 multicast_gid[16][0x8]; 5994 }; 5995 5996 struct mlx5_ifc_destroy_xrq_out_bits { 5997 u8 status[0x8]; 5998 u8 reserved_at_8[0x18]; 5999 6000 u8 syndrome[0x20]; 6001 6002 u8 reserved_at_40[0x40]; 6003 }; 6004 6005 struct mlx5_ifc_destroy_xrq_in_bits { 6006 u8 opcode[0x10]; 6007 u8 uid[0x10]; 6008 6009 u8 reserved_at_20[0x10]; 6010 u8 op_mod[0x10]; 6011 6012 u8 reserved_at_40[0x8]; 6013 u8 xrqn[0x18]; 6014 6015 u8 reserved_at_60[0x20]; 6016 }; 6017 6018 struct mlx5_ifc_destroy_xrc_srq_out_bits { 6019 u8 status[0x8]; 6020 u8 reserved_at_8[0x18]; 6021 6022 u8 syndrome[0x20]; 6023 6024 u8 reserved_at_40[0x40]; 6025 }; 6026 6027 struct mlx5_ifc_destroy_xrc_srq_in_bits { 6028 u8 opcode[0x10]; 6029 u8 uid[0x10]; 6030 6031 u8 reserved_at_20[0x10]; 6032 u8 op_mod[0x10]; 6033 6034 u8 reserved_at_40[0x8]; 6035 u8 xrc_srqn[0x18]; 6036 6037 u8 reserved_at_60[0x20]; 6038 }; 6039 6040 struct mlx5_ifc_destroy_tis_out_bits { 6041 u8 status[0x8]; 6042 u8 reserved_at_8[0x18]; 6043 6044 u8 syndrome[0x20]; 6045 6046 u8 reserved_at_40[0x40]; 6047 }; 6048 6049 struct mlx5_ifc_destroy_tis_in_bits { 6050 u8 opcode[0x10]; 6051 u8 uid[0x10]; 6052 6053 u8 reserved_at_20[0x10]; 6054 u8 op_mod[0x10]; 6055 6056 u8 reserved_at_40[0x8]; 6057 u8 tisn[0x18]; 6058 6059 u8 reserved_at_60[0x20]; 6060 }; 6061 6062 struct mlx5_ifc_destroy_tir_out_bits { 6063 u8 status[0x8]; 6064 u8 reserved_at_8[0x18]; 6065 6066 u8 syndrome[0x20]; 6067 6068 u8 reserved_at_40[0x40]; 6069 }; 6070 6071 struct mlx5_ifc_destroy_tir_in_bits { 6072 u8 opcode[0x10]; 6073 u8 uid[0x10]; 6074 6075 u8 reserved_at_20[0x10]; 6076 u8 op_mod[0x10]; 6077 6078 u8 reserved_at_40[0x8]; 6079 u8 tirn[0x18]; 6080 6081 u8 reserved_at_60[0x20]; 6082 }; 6083 6084 struct mlx5_ifc_destroy_srq_out_bits { 6085 u8 status[0x8]; 6086 u8 reserved_at_8[0x18]; 6087 6088 u8 syndrome[0x20]; 6089 6090 u8 reserved_at_40[0x40]; 6091 }; 6092 6093 struct mlx5_ifc_destroy_srq_in_bits { 6094 u8 opcode[0x10]; 6095 u8 uid[0x10]; 6096 6097 u8 reserved_at_20[0x10]; 6098 u8 op_mod[0x10]; 6099 6100 u8 reserved_at_40[0x8]; 6101 u8 srqn[0x18]; 6102 6103 u8 reserved_at_60[0x20]; 6104 }; 6105 6106 struct mlx5_ifc_destroy_sq_out_bits { 6107 u8 status[0x8]; 6108 u8 reserved_at_8[0x18]; 6109 6110 u8 syndrome[0x20]; 6111 6112 u8 reserved_at_40[0x40]; 6113 }; 6114 6115 struct mlx5_ifc_destroy_sq_in_bits { 6116 u8 opcode[0x10]; 6117 u8 uid[0x10]; 6118 6119 u8 reserved_at_20[0x10]; 6120 u8 op_mod[0x10]; 6121 6122 u8 reserved_at_40[0x8]; 6123 u8 sqn[0x18]; 6124 6125 u8 reserved_at_60[0x20]; 6126 }; 6127 6128 struct mlx5_ifc_destroy_scheduling_element_out_bits { 6129 u8 status[0x8]; 6130 u8 reserved_at_8[0x18]; 6131 6132 u8 syndrome[0x20]; 6133 6134 u8 reserved_at_40[0x1c0]; 6135 }; 6136 6137 struct mlx5_ifc_destroy_scheduling_element_in_bits { 6138 u8 opcode[0x10]; 6139 u8 reserved_at_10[0x10]; 6140 6141 u8 reserved_at_20[0x10]; 6142 u8 op_mod[0x10]; 6143 6144 u8 scheduling_hierarchy[0x8]; 6145 u8 reserved_at_48[0x18]; 6146 6147 u8 scheduling_element_id[0x20]; 6148 6149 u8 reserved_at_80[0x180]; 6150 }; 6151 6152 struct mlx5_ifc_destroy_rqt_out_bits { 6153 u8 status[0x8]; 6154 u8 reserved_at_8[0x18]; 6155 6156 u8 syndrome[0x20]; 6157 6158 u8 reserved_at_40[0x40]; 6159 }; 6160 6161 struct mlx5_ifc_destroy_rqt_in_bits { 6162 u8 opcode[0x10]; 6163 u8 uid[0x10]; 6164 6165 u8 reserved_at_20[0x10]; 6166 u8 op_mod[0x10]; 6167 6168 u8 reserved_at_40[0x8]; 6169 u8 rqtn[0x18]; 6170 6171 u8 reserved_at_60[0x20]; 6172 }; 6173 6174 struct mlx5_ifc_destroy_rq_out_bits { 6175 u8 status[0x8]; 6176 u8 reserved_at_8[0x18]; 6177 6178 u8 syndrome[0x20]; 6179 6180 u8 reserved_at_40[0x40]; 6181 }; 6182 6183 struct mlx5_ifc_destroy_rq_in_bits { 6184 u8 opcode[0x10]; 6185 u8 uid[0x10]; 6186 6187 u8 reserved_at_20[0x10]; 6188 u8 op_mod[0x10]; 6189 6190 u8 reserved_at_40[0x8]; 6191 u8 rqn[0x18]; 6192 6193 u8 reserved_at_60[0x20]; 6194 }; 6195 6196 struct mlx5_ifc_set_delay_drop_params_in_bits { 6197 u8 opcode[0x10]; 6198 u8 reserved_at_10[0x10]; 6199 6200 u8 reserved_at_20[0x10]; 6201 u8 op_mod[0x10]; 6202 6203 u8 reserved_at_40[0x20]; 6204 6205 u8 reserved_at_60[0x10]; 6206 u8 delay_drop_timeout[0x10]; 6207 }; 6208 6209 struct mlx5_ifc_set_delay_drop_params_out_bits { 6210 u8 status[0x8]; 6211 u8 reserved_at_8[0x18]; 6212 6213 u8 syndrome[0x20]; 6214 6215 u8 reserved_at_40[0x40]; 6216 }; 6217 6218 struct mlx5_ifc_destroy_rmp_out_bits { 6219 u8 status[0x8]; 6220 u8 reserved_at_8[0x18]; 6221 6222 u8 syndrome[0x20]; 6223 6224 u8 reserved_at_40[0x40]; 6225 }; 6226 6227 struct mlx5_ifc_destroy_rmp_in_bits { 6228 u8 opcode[0x10]; 6229 u8 uid[0x10]; 6230 6231 u8 reserved_at_20[0x10]; 6232 u8 op_mod[0x10]; 6233 6234 u8 reserved_at_40[0x8]; 6235 u8 rmpn[0x18]; 6236 6237 u8 reserved_at_60[0x20]; 6238 }; 6239 6240 struct mlx5_ifc_destroy_qp_out_bits { 6241 u8 status[0x8]; 6242 u8 reserved_at_8[0x18]; 6243 6244 u8 syndrome[0x20]; 6245 6246 u8 reserved_at_40[0x40]; 6247 }; 6248 6249 struct mlx5_ifc_destroy_qp_in_bits { 6250 u8 opcode[0x10]; 6251 u8 uid[0x10]; 6252 6253 u8 reserved_at_20[0x10]; 6254 u8 op_mod[0x10]; 6255 6256 u8 reserved_at_40[0x8]; 6257 u8 qpn[0x18]; 6258 6259 u8 reserved_at_60[0x20]; 6260 }; 6261 6262 struct mlx5_ifc_destroy_psv_out_bits { 6263 u8 status[0x8]; 6264 u8 reserved_at_8[0x18]; 6265 6266 u8 syndrome[0x20]; 6267 6268 u8 reserved_at_40[0x40]; 6269 }; 6270 6271 struct mlx5_ifc_destroy_psv_in_bits { 6272 u8 opcode[0x10]; 6273 u8 reserved_at_10[0x10]; 6274 6275 u8 reserved_at_20[0x10]; 6276 u8 op_mod[0x10]; 6277 6278 u8 reserved_at_40[0x8]; 6279 u8 psvn[0x18]; 6280 6281 u8 reserved_at_60[0x20]; 6282 }; 6283 6284 struct mlx5_ifc_destroy_mkey_out_bits { 6285 u8 status[0x8]; 6286 u8 reserved_at_8[0x18]; 6287 6288 u8 syndrome[0x20]; 6289 6290 u8 reserved_at_40[0x40]; 6291 }; 6292 6293 struct mlx5_ifc_destroy_mkey_in_bits { 6294 u8 opcode[0x10]; 6295 u8 reserved_at_10[0x10]; 6296 6297 u8 reserved_at_20[0x10]; 6298 u8 op_mod[0x10]; 6299 6300 u8 reserved_at_40[0x8]; 6301 u8 mkey_index[0x18]; 6302 6303 u8 reserved_at_60[0x20]; 6304 }; 6305 6306 struct mlx5_ifc_destroy_flow_table_out_bits { 6307 u8 status[0x8]; 6308 u8 reserved_at_8[0x18]; 6309 6310 u8 syndrome[0x20]; 6311 6312 u8 reserved_at_40[0x40]; 6313 }; 6314 6315 struct mlx5_ifc_destroy_flow_table_in_bits { 6316 u8 opcode[0x10]; 6317 u8 reserved_at_10[0x10]; 6318 6319 u8 reserved_at_20[0x10]; 6320 u8 op_mod[0x10]; 6321 6322 u8 other_vport[0x1]; 6323 u8 reserved_at_41[0xf]; 6324 u8 vport_number[0x10]; 6325 6326 u8 reserved_at_60[0x20]; 6327 6328 u8 table_type[0x8]; 6329 u8 reserved_at_88[0x18]; 6330 6331 u8 reserved_at_a0[0x8]; 6332 u8 table_id[0x18]; 6333 6334 u8 reserved_at_c0[0x140]; 6335 }; 6336 6337 struct mlx5_ifc_destroy_flow_group_out_bits { 6338 u8 status[0x8]; 6339 u8 reserved_at_8[0x18]; 6340 6341 u8 syndrome[0x20]; 6342 6343 u8 reserved_at_40[0x40]; 6344 }; 6345 6346 struct mlx5_ifc_destroy_flow_group_in_bits { 6347 u8 opcode[0x10]; 6348 u8 reserved_at_10[0x10]; 6349 6350 u8 reserved_at_20[0x10]; 6351 u8 op_mod[0x10]; 6352 6353 u8 other_vport[0x1]; 6354 u8 reserved_at_41[0xf]; 6355 u8 vport_number[0x10]; 6356 6357 u8 reserved_at_60[0x20]; 6358 6359 u8 table_type[0x8]; 6360 u8 reserved_at_88[0x18]; 6361 6362 u8 reserved_at_a0[0x8]; 6363 u8 table_id[0x18]; 6364 6365 u8 group_id[0x20]; 6366 6367 u8 reserved_at_e0[0x120]; 6368 }; 6369 6370 struct mlx5_ifc_destroy_eq_out_bits { 6371 u8 status[0x8]; 6372 u8 reserved_at_8[0x18]; 6373 6374 u8 syndrome[0x20]; 6375 6376 u8 reserved_at_40[0x40]; 6377 }; 6378 6379 struct mlx5_ifc_destroy_eq_in_bits { 6380 u8 opcode[0x10]; 6381 u8 reserved_at_10[0x10]; 6382 6383 u8 reserved_at_20[0x10]; 6384 u8 op_mod[0x10]; 6385 6386 u8 reserved_at_40[0x18]; 6387 u8 eq_number[0x8]; 6388 6389 u8 reserved_at_60[0x20]; 6390 }; 6391 6392 struct mlx5_ifc_destroy_dct_out_bits { 6393 u8 status[0x8]; 6394 u8 reserved_at_8[0x18]; 6395 6396 u8 syndrome[0x20]; 6397 6398 u8 reserved_at_40[0x40]; 6399 }; 6400 6401 struct mlx5_ifc_destroy_dct_in_bits { 6402 u8 opcode[0x10]; 6403 u8 uid[0x10]; 6404 6405 u8 reserved_at_20[0x10]; 6406 u8 op_mod[0x10]; 6407 6408 u8 reserved_at_40[0x8]; 6409 u8 dctn[0x18]; 6410 6411 u8 reserved_at_60[0x20]; 6412 }; 6413 6414 struct mlx5_ifc_destroy_cq_out_bits { 6415 u8 status[0x8]; 6416 u8 reserved_at_8[0x18]; 6417 6418 u8 syndrome[0x20]; 6419 6420 u8 reserved_at_40[0x40]; 6421 }; 6422 6423 struct mlx5_ifc_destroy_cq_in_bits { 6424 u8 opcode[0x10]; 6425 u8 uid[0x10]; 6426 6427 u8 reserved_at_20[0x10]; 6428 u8 op_mod[0x10]; 6429 6430 u8 reserved_at_40[0x8]; 6431 u8 cqn[0x18]; 6432 6433 u8 reserved_at_60[0x20]; 6434 }; 6435 6436 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits { 6437 u8 status[0x8]; 6438 u8 reserved_at_8[0x18]; 6439 6440 u8 syndrome[0x20]; 6441 6442 u8 reserved_at_40[0x40]; 6443 }; 6444 6445 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits { 6446 u8 opcode[0x10]; 6447 u8 reserved_at_10[0x10]; 6448 6449 u8 reserved_at_20[0x10]; 6450 u8 op_mod[0x10]; 6451 6452 u8 reserved_at_40[0x20]; 6453 6454 u8 reserved_at_60[0x10]; 6455 u8 vxlan_udp_port[0x10]; 6456 }; 6457 6458 struct mlx5_ifc_delete_l2_table_entry_out_bits { 6459 u8 status[0x8]; 6460 u8 reserved_at_8[0x18]; 6461 6462 u8 syndrome[0x20]; 6463 6464 u8 reserved_at_40[0x40]; 6465 }; 6466 6467 struct mlx5_ifc_delete_l2_table_entry_in_bits { 6468 u8 opcode[0x10]; 6469 u8 reserved_at_10[0x10]; 6470 6471 u8 reserved_at_20[0x10]; 6472 u8 op_mod[0x10]; 6473 6474 u8 reserved_at_40[0x60]; 6475 6476 u8 reserved_at_a0[0x8]; 6477 u8 table_index[0x18]; 6478 6479 u8 reserved_at_c0[0x140]; 6480 }; 6481 6482 struct mlx5_ifc_delete_fte_out_bits { 6483 u8 status[0x8]; 6484 u8 reserved_at_8[0x18]; 6485 6486 u8 syndrome[0x20]; 6487 6488 u8 reserved_at_40[0x40]; 6489 }; 6490 6491 struct mlx5_ifc_delete_fte_in_bits { 6492 u8 opcode[0x10]; 6493 u8 reserved_at_10[0x10]; 6494 6495 u8 reserved_at_20[0x10]; 6496 u8 op_mod[0x10]; 6497 6498 u8 other_vport[0x1]; 6499 u8 reserved_at_41[0xf]; 6500 u8 vport_number[0x10]; 6501 6502 u8 reserved_at_60[0x20]; 6503 6504 u8 table_type[0x8]; 6505 u8 reserved_at_88[0x18]; 6506 6507 u8 reserved_at_a0[0x8]; 6508 u8 table_id[0x18]; 6509 6510 u8 reserved_at_c0[0x40]; 6511 6512 u8 flow_index[0x20]; 6513 6514 u8 reserved_at_120[0xe0]; 6515 }; 6516 6517 struct mlx5_ifc_dealloc_xrcd_out_bits { 6518 u8 status[0x8]; 6519 u8 reserved_at_8[0x18]; 6520 6521 u8 syndrome[0x20]; 6522 6523 u8 reserved_at_40[0x40]; 6524 }; 6525 6526 struct mlx5_ifc_dealloc_xrcd_in_bits { 6527 u8 opcode[0x10]; 6528 u8 uid[0x10]; 6529 6530 u8 reserved_at_20[0x10]; 6531 u8 op_mod[0x10]; 6532 6533 u8 reserved_at_40[0x8]; 6534 u8 xrcd[0x18]; 6535 6536 u8 reserved_at_60[0x20]; 6537 }; 6538 6539 struct mlx5_ifc_dealloc_uar_out_bits { 6540 u8 status[0x8]; 6541 u8 reserved_at_8[0x18]; 6542 6543 u8 syndrome[0x20]; 6544 6545 u8 reserved_at_40[0x40]; 6546 }; 6547 6548 struct mlx5_ifc_dealloc_uar_in_bits { 6549 u8 opcode[0x10]; 6550 u8 reserved_at_10[0x10]; 6551 6552 u8 reserved_at_20[0x10]; 6553 u8 op_mod[0x10]; 6554 6555 u8 reserved_at_40[0x8]; 6556 u8 uar[0x18]; 6557 6558 u8 reserved_at_60[0x20]; 6559 }; 6560 6561 struct mlx5_ifc_dealloc_transport_domain_out_bits { 6562 u8 status[0x8]; 6563 u8 reserved_at_8[0x18]; 6564 6565 u8 syndrome[0x20]; 6566 6567 u8 reserved_at_40[0x40]; 6568 }; 6569 6570 struct mlx5_ifc_dealloc_transport_domain_in_bits { 6571 u8 opcode[0x10]; 6572 u8 reserved_at_10[0x10]; 6573 6574 u8 reserved_at_20[0x10]; 6575 u8 op_mod[0x10]; 6576 6577 u8 reserved_at_40[0x8]; 6578 u8 transport_domain[0x18]; 6579 6580 u8 reserved_at_60[0x20]; 6581 }; 6582 6583 struct mlx5_ifc_dealloc_q_counter_out_bits { 6584 u8 status[0x8]; 6585 u8 reserved_at_8[0x18]; 6586 6587 u8 syndrome[0x20]; 6588 6589 u8 reserved_at_40[0x40]; 6590 }; 6591 6592 struct mlx5_ifc_dealloc_q_counter_in_bits { 6593 u8 opcode[0x10]; 6594 u8 reserved_at_10[0x10]; 6595 6596 u8 reserved_at_20[0x10]; 6597 u8 op_mod[0x10]; 6598 6599 u8 reserved_at_40[0x18]; 6600 u8 counter_set_id[0x8]; 6601 6602 u8 reserved_at_60[0x20]; 6603 }; 6604 6605 struct mlx5_ifc_dealloc_pd_out_bits { 6606 u8 status[0x8]; 6607 u8 reserved_at_8[0x18]; 6608 6609 u8 syndrome[0x20]; 6610 6611 u8 reserved_at_40[0x40]; 6612 }; 6613 6614 struct mlx5_ifc_dealloc_pd_in_bits { 6615 u8 opcode[0x10]; 6616 u8 uid[0x10]; 6617 6618 u8 reserved_at_20[0x10]; 6619 u8 op_mod[0x10]; 6620 6621 u8 reserved_at_40[0x8]; 6622 u8 pd[0x18]; 6623 6624 u8 reserved_at_60[0x20]; 6625 }; 6626 6627 struct mlx5_ifc_dealloc_flow_counter_out_bits { 6628 u8 status[0x8]; 6629 u8 reserved_at_8[0x18]; 6630 6631 u8 syndrome[0x20]; 6632 6633 u8 reserved_at_40[0x40]; 6634 }; 6635 6636 struct mlx5_ifc_dealloc_flow_counter_in_bits { 6637 u8 opcode[0x10]; 6638 u8 reserved_at_10[0x10]; 6639 6640 u8 reserved_at_20[0x10]; 6641 u8 op_mod[0x10]; 6642 6643 u8 flow_counter_id[0x20]; 6644 6645 u8 reserved_at_60[0x20]; 6646 }; 6647 6648 struct mlx5_ifc_create_xrq_out_bits { 6649 u8 status[0x8]; 6650 u8 reserved_at_8[0x18]; 6651 6652 u8 syndrome[0x20]; 6653 6654 u8 reserved_at_40[0x8]; 6655 u8 xrqn[0x18]; 6656 6657 u8 reserved_at_60[0x20]; 6658 }; 6659 6660 struct mlx5_ifc_create_xrq_in_bits { 6661 u8 opcode[0x10]; 6662 u8 uid[0x10]; 6663 6664 u8 reserved_at_20[0x10]; 6665 u8 op_mod[0x10]; 6666 6667 u8 reserved_at_40[0x40]; 6668 6669 struct mlx5_ifc_xrqc_bits xrq_context; 6670 }; 6671 6672 struct mlx5_ifc_create_xrc_srq_out_bits { 6673 u8 status[0x8]; 6674 u8 reserved_at_8[0x18]; 6675 6676 u8 syndrome[0x20]; 6677 6678 u8 reserved_at_40[0x8]; 6679 u8 xrc_srqn[0x18]; 6680 6681 u8 reserved_at_60[0x20]; 6682 }; 6683 6684 struct mlx5_ifc_create_xrc_srq_in_bits { 6685 u8 opcode[0x10]; 6686 u8 uid[0x10]; 6687 6688 u8 reserved_at_20[0x10]; 6689 u8 op_mod[0x10]; 6690 6691 u8 reserved_at_40[0x40]; 6692 6693 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 6694 6695 u8 reserved_at_280[0x60]; 6696 6697 u8 xrc_srq_umem_valid[0x1]; 6698 u8 reserved_at_2e1[0x1f]; 6699 6700 u8 reserved_at_300[0x580]; 6701 6702 u8 pas[0][0x40]; 6703 }; 6704 6705 struct mlx5_ifc_create_tis_out_bits { 6706 u8 status[0x8]; 6707 u8 reserved_at_8[0x18]; 6708 6709 u8 syndrome[0x20]; 6710 6711 u8 reserved_at_40[0x8]; 6712 u8 tisn[0x18]; 6713 6714 u8 reserved_at_60[0x20]; 6715 }; 6716 6717 struct mlx5_ifc_create_tis_in_bits { 6718 u8 opcode[0x10]; 6719 u8 uid[0x10]; 6720 6721 u8 reserved_at_20[0x10]; 6722 u8 op_mod[0x10]; 6723 6724 u8 reserved_at_40[0xc0]; 6725 6726 struct mlx5_ifc_tisc_bits ctx; 6727 }; 6728 6729 struct mlx5_ifc_create_tir_out_bits { 6730 u8 status[0x8]; 6731 u8 reserved_at_8[0x18]; 6732 6733 u8 syndrome[0x20]; 6734 6735 u8 reserved_at_40[0x8]; 6736 u8 tirn[0x18]; 6737 6738 u8 reserved_at_60[0x20]; 6739 }; 6740 6741 struct mlx5_ifc_create_tir_in_bits { 6742 u8 opcode[0x10]; 6743 u8 uid[0x10]; 6744 6745 u8 reserved_at_20[0x10]; 6746 u8 op_mod[0x10]; 6747 6748 u8 reserved_at_40[0xc0]; 6749 6750 struct mlx5_ifc_tirc_bits ctx; 6751 }; 6752 6753 struct mlx5_ifc_create_srq_out_bits { 6754 u8 status[0x8]; 6755 u8 reserved_at_8[0x18]; 6756 6757 u8 syndrome[0x20]; 6758 6759 u8 reserved_at_40[0x8]; 6760 u8 srqn[0x18]; 6761 6762 u8 reserved_at_60[0x20]; 6763 }; 6764 6765 struct mlx5_ifc_create_srq_in_bits { 6766 u8 opcode[0x10]; 6767 u8 uid[0x10]; 6768 6769 u8 reserved_at_20[0x10]; 6770 u8 op_mod[0x10]; 6771 6772 u8 reserved_at_40[0x40]; 6773 6774 struct mlx5_ifc_srqc_bits srq_context_entry; 6775 6776 u8 reserved_at_280[0x600]; 6777 6778 u8 pas[0][0x40]; 6779 }; 6780 6781 struct mlx5_ifc_create_sq_out_bits { 6782 u8 status[0x8]; 6783 u8 reserved_at_8[0x18]; 6784 6785 u8 syndrome[0x20]; 6786 6787 u8 reserved_at_40[0x8]; 6788 u8 sqn[0x18]; 6789 6790 u8 reserved_at_60[0x20]; 6791 }; 6792 6793 struct mlx5_ifc_create_sq_in_bits { 6794 u8 opcode[0x10]; 6795 u8 uid[0x10]; 6796 6797 u8 reserved_at_20[0x10]; 6798 u8 op_mod[0x10]; 6799 6800 u8 reserved_at_40[0xc0]; 6801 6802 struct mlx5_ifc_sqc_bits ctx; 6803 }; 6804 6805 struct mlx5_ifc_create_scheduling_element_out_bits { 6806 u8 status[0x8]; 6807 u8 reserved_at_8[0x18]; 6808 6809 u8 syndrome[0x20]; 6810 6811 u8 reserved_at_40[0x40]; 6812 6813 u8 scheduling_element_id[0x20]; 6814 6815 u8 reserved_at_a0[0x160]; 6816 }; 6817 6818 struct mlx5_ifc_create_scheduling_element_in_bits { 6819 u8 opcode[0x10]; 6820 u8 reserved_at_10[0x10]; 6821 6822 u8 reserved_at_20[0x10]; 6823 u8 op_mod[0x10]; 6824 6825 u8 scheduling_hierarchy[0x8]; 6826 u8 reserved_at_48[0x18]; 6827 6828 u8 reserved_at_60[0xa0]; 6829 6830 struct mlx5_ifc_scheduling_context_bits scheduling_context; 6831 6832 u8 reserved_at_300[0x100]; 6833 }; 6834 6835 struct mlx5_ifc_create_rqt_out_bits { 6836 u8 status[0x8]; 6837 u8 reserved_at_8[0x18]; 6838 6839 u8 syndrome[0x20]; 6840 6841 u8 reserved_at_40[0x8]; 6842 u8 rqtn[0x18]; 6843 6844 u8 reserved_at_60[0x20]; 6845 }; 6846 6847 struct mlx5_ifc_create_rqt_in_bits { 6848 u8 opcode[0x10]; 6849 u8 uid[0x10]; 6850 6851 u8 reserved_at_20[0x10]; 6852 u8 op_mod[0x10]; 6853 6854 u8 reserved_at_40[0xc0]; 6855 6856 struct mlx5_ifc_rqtc_bits rqt_context; 6857 }; 6858 6859 struct mlx5_ifc_create_rq_out_bits { 6860 u8 status[0x8]; 6861 u8 reserved_at_8[0x18]; 6862 6863 u8 syndrome[0x20]; 6864 6865 u8 reserved_at_40[0x8]; 6866 u8 rqn[0x18]; 6867 6868 u8 reserved_at_60[0x20]; 6869 }; 6870 6871 struct mlx5_ifc_create_rq_in_bits { 6872 u8 opcode[0x10]; 6873 u8 uid[0x10]; 6874 6875 u8 reserved_at_20[0x10]; 6876 u8 op_mod[0x10]; 6877 6878 u8 reserved_at_40[0xc0]; 6879 6880 struct mlx5_ifc_rqc_bits ctx; 6881 }; 6882 6883 struct mlx5_ifc_create_rmp_out_bits { 6884 u8 status[0x8]; 6885 u8 reserved_at_8[0x18]; 6886 6887 u8 syndrome[0x20]; 6888 6889 u8 reserved_at_40[0x8]; 6890 u8 rmpn[0x18]; 6891 6892 u8 reserved_at_60[0x20]; 6893 }; 6894 6895 struct mlx5_ifc_create_rmp_in_bits { 6896 u8 opcode[0x10]; 6897 u8 uid[0x10]; 6898 6899 u8 reserved_at_20[0x10]; 6900 u8 op_mod[0x10]; 6901 6902 u8 reserved_at_40[0xc0]; 6903 6904 struct mlx5_ifc_rmpc_bits ctx; 6905 }; 6906 6907 struct mlx5_ifc_create_qp_out_bits { 6908 u8 status[0x8]; 6909 u8 reserved_at_8[0x18]; 6910 6911 u8 syndrome[0x20]; 6912 6913 u8 reserved_at_40[0x8]; 6914 u8 qpn[0x18]; 6915 6916 u8 reserved_at_60[0x20]; 6917 }; 6918 6919 struct mlx5_ifc_create_qp_in_bits { 6920 u8 opcode[0x10]; 6921 u8 uid[0x10]; 6922 6923 u8 reserved_at_20[0x10]; 6924 u8 op_mod[0x10]; 6925 6926 u8 reserved_at_40[0x40]; 6927 6928 u8 opt_param_mask[0x20]; 6929 6930 u8 reserved_at_a0[0x20]; 6931 6932 struct mlx5_ifc_qpc_bits qpc; 6933 6934 u8 reserved_at_800[0x60]; 6935 6936 u8 wq_umem_valid[0x1]; 6937 u8 reserved_at_861[0x1f]; 6938 6939 u8 pas[0][0x40]; 6940 }; 6941 6942 struct mlx5_ifc_create_psv_out_bits { 6943 u8 status[0x8]; 6944 u8 reserved_at_8[0x18]; 6945 6946 u8 syndrome[0x20]; 6947 6948 u8 reserved_at_40[0x40]; 6949 6950 u8 reserved_at_80[0x8]; 6951 u8 psv0_index[0x18]; 6952 6953 u8 reserved_at_a0[0x8]; 6954 u8 psv1_index[0x18]; 6955 6956 u8 reserved_at_c0[0x8]; 6957 u8 psv2_index[0x18]; 6958 6959 u8 reserved_at_e0[0x8]; 6960 u8 psv3_index[0x18]; 6961 }; 6962 6963 struct mlx5_ifc_create_psv_in_bits { 6964 u8 opcode[0x10]; 6965 u8 reserved_at_10[0x10]; 6966 6967 u8 reserved_at_20[0x10]; 6968 u8 op_mod[0x10]; 6969 6970 u8 num_psv[0x4]; 6971 u8 reserved_at_44[0x4]; 6972 u8 pd[0x18]; 6973 6974 u8 reserved_at_60[0x20]; 6975 }; 6976 6977 struct mlx5_ifc_create_mkey_out_bits { 6978 u8 status[0x8]; 6979 u8 reserved_at_8[0x18]; 6980 6981 u8 syndrome[0x20]; 6982 6983 u8 reserved_at_40[0x8]; 6984 u8 mkey_index[0x18]; 6985 6986 u8 reserved_at_60[0x20]; 6987 }; 6988 6989 struct mlx5_ifc_create_mkey_in_bits { 6990 u8 opcode[0x10]; 6991 u8 reserved_at_10[0x10]; 6992 6993 u8 reserved_at_20[0x10]; 6994 u8 op_mod[0x10]; 6995 6996 u8 reserved_at_40[0x20]; 6997 6998 u8 pg_access[0x1]; 6999 u8 mkey_umem_valid[0x1]; 7000 u8 reserved_at_62[0x1e]; 7001 7002 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 7003 7004 u8 reserved_at_280[0x80]; 7005 7006 u8 translations_octword_actual_size[0x20]; 7007 7008 u8 reserved_at_320[0x560]; 7009 7010 u8 klm_pas_mtt[0][0x20]; 7011 }; 7012 7013 struct mlx5_ifc_create_flow_table_out_bits { 7014 u8 status[0x8]; 7015 u8 reserved_at_8[0x18]; 7016 7017 u8 syndrome[0x20]; 7018 7019 u8 reserved_at_40[0x8]; 7020 u8 table_id[0x18]; 7021 7022 u8 reserved_at_60[0x20]; 7023 }; 7024 7025 struct mlx5_ifc_flow_table_context_bits { 7026 u8 reformat_en[0x1]; 7027 u8 decap_en[0x1]; 7028 u8 reserved_at_2[0x2]; 7029 u8 table_miss_action[0x4]; 7030 u8 level[0x8]; 7031 u8 reserved_at_10[0x8]; 7032 u8 log_size[0x8]; 7033 7034 u8 reserved_at_20[0x8]; 7035 u8 table_miss_id[0x18]; 7036 7037 u8 reserved_at_40[0x8]; 7038 u8 lag_master_next_table_id[0x18]; 7039 7040 u8 reserved_at_60[0xe0]; 7041 }; 7042 7043 struct mlx5_ifc_create_flow_table_in_bits { 7044 u8 opcode[0x10]; 7045 u8 reserved_at_10[0x10]; 7046 7047 u8 reserved_at_20[0x10]; 7048 u8 op_mod[0x10]; 7049 7050 u8 other_vport[0x1]; 7051 u8 reserved_at_41[0xf]; 7052 u8 vport_number[0x10]; 7053 7054 u8 reserved_at_60[0x20]; 7055 7056 u8 table_type[0x8]; 7057 u8 reserved_at_88[0x18]; 7058 7059 u8 reserved_at_a0[0x20]; 7060 7061 struct mlx5_ifc_flow_table_context_bits flow_table_context; 7062 }; 7063 7064 struct mlx5_ifc_create_flow_group_out_bits { 7065 u8 status[0x8]; 7066 u8 reserved_at_8[0x18]; 7067 7068 u8 syndrome[0x20]; 7069 7070 u8 reserved_at_40[0x8]; 7071 u8 group_id[0x18]; 7072 7073 u8 reserved_at_60[0x20]; 7074 }; 7075 7076 enum { 7077 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 7078 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 7079 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 7080 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3, 7081 }; 7082 7083 struct mlx5_ifc_create_flow_group_in_bits { 7084 u8 opcode[0x10]; 7085 u8 reserved_at_10[0x10]; 7086 7087 u8 reserved_at_20[0x10]; 7088 u8 op_mod[0x10]; 7089 7090 u8 other_vport[0x1]; 7091 u8 reserved_at_41[0xf]; 7092 u8 vport_number[0x10]; 7093 7094 u8 reserved_at_60[0x20]; 7095 7096 u8 table_type[0x8]; 7097 u8 reserved_at_88[0x18]; 7098 7099 u8 reserved_at_a0[0x8]; 7100 u8 table_id[0x18]; 7101 7102 u8 source_eswitch_owner_vhca_id_valid[0x1]; 7103 7104 u8 reserved_at_c1[0x1f]; 7105 7106 u8 start_flow_index[0x20]; 7107 7108 u8 reserved_at_100[0x20]; 7109 7110 u8 end_flow_index[0x20]; 7111 7112 u8 reserved_at_140[0xa0]; 7113 7114 u8 reserved_at_1e0[0x18]; 7115 u8 match_criteria_enable[0x8]; 7116 7117 struct mlx5_ifc_fte_match_param_bits match_criteria; 7118 7119 u8 reserved_at_1200[0xe00]; 7120 }; 7121 7122 struct mlx5_ifc_create_eq_out_bits { 7123 u8 status[0x8]; 7124 u8 reserved_at_8[0x18]; 7125 7126 u8 syndrome[0x20]; 7127 7128 u8 reserved_at_40[0x18]; 7129 u8 eq_number[0x8]; 7130 7131 u8 reserved_at_60[0x20]; 7132 }; 7133 7134 struct mlx5_ifc_create_eq_in_bits { 7135 u8 opcode[0x10]; 7136 u8 reserved_at_10[0x10]; 7137 7138 u8 reserved_at_20[0x10]; 7139 u8 op_mod[0x10]; 7140 7141 u8 reserved_at_40[0x40]; 7142 7143 struct mlx5_ifc_eqc_bits eq_context_entry; 7144 7145 u8 reserved_at_280[0x40]; 7146 7147 u8 event_bitmask[0x40]; 7148 7149 u8 reserved_at_300[0x580]; 7150 7151 u8 pas[0][0x40]; 7152 }; 7153 7154 struct mlx5_ifc_create_dct_out_bits { 7155 u8 status[0x8]; 7156 u8 reserved_at_8[0x18]; 7157 7158 u8 syndrome[0x20]; 7159 7160 u8 reserved_at_40[0x8]; 7161 u8 dctn[0x18]; 7162 7163 u8 reserved_at_60[0x20]; 7164 }; 7165 7166 struct mlx5_ifc_create_dct_in_bits { 7167 u8 opcode[0x10]; 7168 u8 uid[0x10]; 7169 7170 u8 reserved_at_20[0x10]; 7171 u8 op_mod[0x10]; 7172 7173 u8 reserved_at_40[0x40]; 7174 7175 struct mlx5_ifc_dctc_bits dct_context_entry; 7176 7177 u8 reserved_at_280[0x180]; 7178 }; 7179 7180 struct mlx5_ifc_create_cq_out_bits { 7181 u8 status[0x8]; 7182 u8 reserved_at_8[0x18]; 7183 7184 u8 syndrome[0x20]; 7185 7186 u8 reserved_at_40[0x8]; 7187 u8 cqn[0x18]; 7188 7189 u8 reserved_at_60[0x20]; 7190 }; 7191 7192 struct mlx5_ifc_create_cq_in_bits { 7193 u8 opcode[0x10]; 7194 u8 uid[0x10]; 7195 7196 u8 reserved_at_20[0x10]; 7197 u8 op_mod[0x10]; 7198 7199 u8 reserved_at_40[0x40]; 7200 7201 struct mlx5_ifc_cqc_bits cq_context; 7202 7203 u8 reserved_at_280[0x60]; 7204 7205 u8 cq_umem_valid[0x1]; 7206 u8 reserved_at_2e1[0x59f]; 7207 7208 u8 pas[0][0x40]; 7209 }; 7210 7211 struct mlx5_ifc_config_int_moderation_out_bits { 7212 u8 status[0x8]; 7213 u8 reserved_at_8[0x18]; 7214 7215 u8 syndrome[0x20]; 7216 7217 u8 reserved_at_40[0x4]; 7218 u8 min_delay[0xc]; 7219 u8 int_vector[0x10]; 7220 7221 u8 reserved_at_60[0x20]; 7222 }; 7223 7224 enum { 7225 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0, 7226 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1, 7227 }; 7228 7229 struct mlx5_ifc_config_int_moderation_in_bits { 7230 u8 opcode[0x10]; 7231 u8 reserved_at_10[0x10]; 7232 7233 u8 reserved_at_20[0x10]; 7234 u8 op_mod[0x10]; 7235 7236 u8 reserved_at_40[0x4]; 7237 u8 min_delay[0xc]; 7238 u8 int_vector[0x10]; 7239 7240 u8 reserved_at_60[0x20]; 7241 }; 7242 7243 struct mlx5_ifc_attach_to_mcg_out_bits { 7244 u8 status[0x8]; 7245 u8 reserved_at_8[0x18]; 7246 7247 u8 syndrome[0x20]; 7248 7249 u8 reserved_at_40[0x40]; 7250 }; 7251 7252 struct mlx5_ifc_attach_to_mcg_in_bits { 7253 u8 opcode[0x10]; 7254 u8 uid[0x10]; 7255 7256 u8 reserved_at_20[0x10]; 7257 u8 op_mod[0x10]; 7258 7259 u8 reserved_at_40[0x8]; 7260 u8 qpn[0x18]; 7261 7262 u8 reserved_at_60[0x20]; 7263 7264 u8 multicast_gid[16][0x8]; 7265 }; 7266 7267 struct mlx5_ifc_arm_xrq_out_bits { 7268 u8 status[0x8]; 7269 u8 reserved_at_8[0x18]; 7270 7271 u8 syndrome[0x20]; 7272 7273 u8 reserved_at_40[0x40]; 7274 }; 7275 7276 struct mlx5_ifc_arm_xrq_in_bits { 7277 u8 opcode[0x10]; 7278 u8 reserved_at_10[0x10]; 7279 7280 u8 reserved_at_20[0x10]; 7281 u8 op_mod[0x10]; 7282 7283 u8 reserved_at_40[0x8]; 7284 u8 xrqn[0x18]; 7285 7286 u8 reserved_at_60[0x10]; 7287 u8 lwm[0x10]; 7288 }; 7289 7290 struct mlx5_ifc_arm_xrc_srq_out_bits { 7291 u8 status[0x8]; 7292 u8 reserved_at_8[0x18]; 7293 7294 u8 syndrome[0x20]; 7295 7296 u8 reserved_at_40[0x40]; 7297 }; 7298 7299 enum { 7300 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1, 7301 }; 7302 7303 struct mlx5_ifc_arm_xrc_srq_in_bits { 7304 u8 opcode[0x10]; 7305 u8 uid[0x10]; 7306 7307 u8 reserved_at_20[0x10]; 7308 u8 op_mod[0x10]; 7309 7310 u8 reserved_at_40[0x8]; 7311 u8 xrc_srqn[0x18]; 7312 7313 u8 reserved_at_60[0x10]; 7314 u8 lwm[0x10]; 7315 }; 7316 7317 struct mlx5_ifc_arm_rq_out_bits { 7318 u8 status[0x8]; 7319 u8 reserved_at_8[0x18]; 7320 7321 u8 syndrome[0x20]; 7322 7323 u8 reserved_at_40[0x40]; 7324 }; 7325 7326 enum { 7327 MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1, 7328 MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2, 7329 }; 7330 7331 struct mlx5_ifc_arm_rq_in_bits { 7332 u8 opcode[0x10]; 7333 u8 uid[0x10]; 7334 7335 u8 reserved_at_20[0x10]; 7336 u8 op_mod[0x10]; 7337 7338 u8 reserved_at_40[0x8]; 7339 u8 srq_number[0x18]; 7340 7341 u8 reserved_at_60[0x10]; 7342 u8 lwm[0x10]; 7343 }; 7344 7345 struct mlx5_ifc_arm_dct_out_bits { 7346 u8 status[0x8]; 7347 u8 reserved_at_8[0x18]; 7348 7349 u8 syndrome[0x20]; 7350 7351 u8 reserved_at_40[0x40]; 7352 }; 7353 7354 struct mlx5_ifc_arm_dct_in_bits { 7355 u8 opcode[0x10]; 7356 u8 reserved_at_10[0x10]; 7357 7358 u8 reserved_at_20[0x10]; 7359 u8 op_mod[0x10]; 7360 7361 u8 reserved_at_40[0x8]; 7362 u8 dct_number[0x18]; 7363 7364 u8 reserved_at_60[0x20]; 7365 }; 7366 7367 struct mlx5_ifc_alloc_xrcd_out_bits { 7368 u8 status[0x8]; 7369 u8 reserved_at_8[0x18]; 7370 7371 u8 syndrome[0x20]; 7372 7373 u8 reserved_at_40[0x8]; 7374 u8 xrcd[0x18]; 7375 7376 u8 reserved_at_60[0x20]; 7377 }; 7378 7379 struct mlx5_ifc_alloc_xrcd_in_bits { 7380 u8 opcode[0x10]; 7381 u8 uid[0x10]; 7382 7383 u8 reserved_at_20[0x10]; 7384 u8 op_mod[0x10]; 7385 7386 u8 reserved_at_40[0x40]; 7387 }; 7388 7389 struct mlx5_ifc_alloc_uar_out_bits { 7390 u8 status[0x8]; 7391 u8 reserved_at_8[0x18]; 7392 7393 u8 syndrome[0x20]; 7394 7395 u8 reserved_at_40[0x8]; 7396 u8 uar[0x18]; 7397 7398 u8 reserved_at_60[0x20]; 7399 }; 7400 7401 struct mlx5_ifc_alloc_uar_in_bits { 7402 u8 opcode[0x10]; 7403 u8 reserved_at_10[0x10]; 7404 7405 u8 reserved_at_20[0x10]; 7406 u8 op_mod[0x10]; 7407 7408 u8 reserved_at_40[0x40]; 7409 }; 7410 7411 struct mlx5_ifc_alloc_transport_domain_out_bits { 7412 u8 status[0x8]; 7413 u8 reserved_at_8[0x18]; 7414 7415 u8 syndrome[0x20]; 7416 7417 u8 reserved_at_40[0x8]; 7418 u8 transport_domain[0x18]; 7419 7420 u8 reserved_at_60[0x20]; 7421 }; 7422 7423 struct mlx5_ifc_alloc_transport_domain_in_bits { 7424 u8 opcode[0x10]; 7425 u8 reserved_at_10[0x10]; 7426 7427 u8 reserved_at_20[0x10]; 7428 u8 op_mod[0x10]; 7429 7430 u8 reserved_at_40[0x40]; 7431 }; 7432 7433 struct mlx5_ifc_alloc_q_counter_out_bits { 7434 u8 status[0x8]; 7435 u8 reserved_at_8[0x18]; 7436 7437 u8 syndrome[0x20]; 7438 7439 u8 reserved_at_40[0x18]; 7440 u8 counter_set_id[0x8]; 7441 7442 u8 reserved_at_60[0x20]; 7443 }; 7444 7445 struct mlx5_ifc_alloc_q_counter_in_bits { 7446 u8 opcode[0x10]; 7447 u8 reserved_at_10[0x10]; 7448 7449 u8 reserved_at_20[0x10]; 7450 u8 op_mod[0x10]; 7451 7452 u8 reserved_at_40[0x40]; 7453 }; 7454 7455 struct mlx5_ifc_alloc_pd_out_bits { 7456 u8 status[0x8]; 7457 u8 reserved_at_8[0x18]; 7458 7459 u8 syndrome[0x20]; 7460 7461 u8 reserved_at_40[0x8]; 7462 u8 pd[0x18]; 7463 7464 u8 reserved_at_60[0x20]; 7465 }; 7466 7467 struct mlx5_ifc_alloc_pd_in_bits { 7468 u8 opcode[0x10]; 7469 u8 uid[0x10]; 7470 7471 u8 reserved_at_20[0x10]; 7472 u8 op_mod[0x10]; 7473 7474 u8 reserved_at_40[0x40]; 7475 }; 7476 7477 struct mlx5_ifc_alloc_flow_counter_out_bits { 7478 u8 status[0x8]; 7479 u8 reserved_at_8[0x18]; 7480 7481 u8 syndrome[0x20]; 7482 7483 u8 flow_counter_id[0x20]; 7484 7485 u8 reserved_at_60[0x20]; 7486 }; 7487 7488 struct mlx5_ifc_alloc_flow_counter_in_bits { 7489 u8 opcode[0x10]; 7490 u8 reserved_at_10[0x10]; 7491 7492 u8 reserved_at_20[0x10]; 7493 u8 op_mod[0x10]; 7494 7495 u8 reserved_at_40[0x40]; 7496 }; 7497 7498 struct mlx5_ifc_add_vxlan_udp_dport_out_bits { 7499 u8 status[0x8]; 7500 u8 reserved_at_8[0x18]; 7501 7502 u8 syndrome[0x20]; 7503 7504 u8 reserved_at_40[0x40]; 7505 }; 7506 7507 struct mlx5_ifc_add_vxlan_udp_dport_in_bits { 7508 u8 opcode[0x10]; 7509 u8 reserved_at_10[0x10]; 7510 7511 u8 reserved_at_20[0x10]; 7512 u8 op_mod[0x10]; 7513 7514 u8 reserved_at_40[0x20]; 7515 7516 u8 reserved_at_60[0x10]; 7517 u8 vxlan_udp_port[0x10]; 7518 }; 7519 7520 struct mlx5_ifc_set_pp_rate_limit_out_bits { 7521 u8 status[0x8]; 7522 u8 reserved_at_8[0x18]; 7523 7524 u8 syndrome[0x20]; 7525 7526 u8 reserved_at_40[0x40]; 7527 }; 7528 7529 struct mlx5_ifc_set_pp_rate_limit_in_bits { 7530 u8 opcode[0x10]; 7531 u8 reserved_at_10[0x10]; 7532 7533 u8 reserved_at_20[0x10]; 7534 u8 op_mod[0x10]; 7535 7536 u8 reserved_at_40[0x10]; 7537 u8 rate_limit_index[0x10]; 7538 7539 u8 reserved_at_60[0x20]; 7540 7541 u8 rate_limit[0x20]; 7542 7543 u8 burst_upper_bound[0x20]; 7544 7545 u8 reserved_at_c0[0x10]; 7546 u8 typical_packet_size[0x10]; 7547 7548 u8 reserved_at_e0[0x120]; 7549 }; 7550 7551 struct mlx5_ifc_access_register_out_bits { 7552 u8 status[0x8]; 7553 u8 reserved_at_8[0x18]; 7554 7555 u8 syndrome[0x20]; 7556 7557 u8 reserved_at_40[0x40]; 7558 7559 u8 register_data[0][0x20]; 7560 }; 7561 7562 enum { 7563 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0, 7564 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1, 7565 }; 7566 7567 struct mlx5_ifc_access_register_in_bits { 7568 u8 opcode[0x10]; 7569 u8 reserved_at_10[0x10]; 7570 7571 u8 reserved_at_20[0x10]; 7572 u8 op_mod[0x10]; 7573 7574 u8 reserved_at_40[0x10]; 7575 u8 register_id[0x10]; 7576 7577 u8 argument[0x20]; 7578 7579 u8 register_data[0][0x20]; 7580 }; 7581 7582 struct mlx5_ifc_sltp_reg_bits { 7583 u8 status[0x4]; 7584 u8 version[0x4]; 7585 u8 local_port[0x8]; 7586 u8 pnat[0x2]; 7587 u8 reserved_at_12[0x2]; 7588 u8 lane[0x4]; 7589 u8 reserved_at_18[0x8]; 7590 7591 u8 reserved_at_20[0x20]; 7592 7593 u8 reserved_at_40[0x7]; 7594 u8 polarity[0x1]; 7595 u8 ob_tap0[0x8]; 7596 u8 ob_tap1[0x8]; 7597 u8 ob_tap2[0x8]; 7598 7599 u8 reserved_at_60[0xc]; 7600 u8 ob_preemp_mode[0x4]; 7601 u8 ob_reg[0x8]; 7602 u8 ob_bias[0x8]; 7603 7604 u8 reserved_at_80[0x20]; 7605 }; 7606 7607 struct mlx5_ifc_slrg_reg_bits { 7608 u8 status[0x4]; 7609 u8 version[0x4]; 7610 u8 local_port[0x8]; 7611 u8 pnat[0x2]; 7612 u8 reserved_at_12[0x2]; 7613 u8 lane[0x4]; 7614 u8 reserved_at_18[0x8]; 7615 7616 u8 time_to_link_up[0x10]; 7617 u8 reserved_at_30[0xc]; 7618 u8 grade_lane_speed[0x4]; 7619 7620 u8 grade_version[0x8]; 7621 u8 grade[0x18]; 7622 7623 u8 reserved_at_60[0x4]; 7624 u8 height_grade_type[0x4]; 7625 u8 height_grade[0x18]; 7626 7627 u8 height_dz[0x10]; 7628 u8 height_dv[0x10]; 7629 7630 u8 reserved_at_a0[0x10]; 7631 u8 height_sigma[0x10]; 7632 7633 u8 reserved_at_c0[0x20]; 7634 7635 u8 reserved_at_e0[0x4]; 7636 u8 phase_grade_type[0x4]; 7637 u8 phase_grade[0x18]; 7638 7639 u8 reserved_at_100[0x8]; 7640 u8 phase_eo_pos[0x8]; 7641 u8 reserved_at_110[0x8]; 7642 u8 phase_eo_neg[0x8]; 7643 7644 u8 ffe_set_tested[0x10]; 7645 u8 test_errors_per_lane[0x10]; 7646 }; 7647 7648 struct mlx5_ifc_pvlc_reg_bits { 7649 u8 reserved_at_0[0x8]; 7650 u8 local_port[0x8]; 7651 u8 reserved_at_10[0x10]; 7652 7653 u8 reserved_at_20[0x1c]; 7654 u8 vl_hw_cap[0x4]; 7655 7656 u8 reserved_at_40[0x1c]; 7657 u8 vl_admin[0x4]; 7658 7659 u8 reserved_at_60[0x1c]; 7660 u8 vl_operational[0x4]; 7661 }; 7662 7663 struct mlx5_ifc_pude_reg_bits { 7664 u8 swid[0x8]; 7665 u8 local_port[0x8]; 7666 u8 reserved_at_10[0x4]; 7667 u8 admin_status[0x4]; 7668 u8 reserved_at_18[0x4]; 7669 u8 oper_status[0x4]; 7670 7671 u8 reserved_at_20[0x60]; 7672 }; 7673 7674 struct mlx5_ifc_ptys_reg_bits { 7675 u8 reserved_at_0[0x1]; 7676 u8 an_disable_admin[0x1]; 7677 u8 an_disable_cap[0x1]; 7678 u8 reserved_at_3[0x5]; 7679 u8 local_port[0x8]; 7680 u8 reserved_at_10[0xd]; 7681 u8 proto_mask[0x3]; 7682 7683 u8 an_status[0x4]; 7684 u8 reserved_at_24[0x3c]; 7685 7686 u8 eth_proto_capability[0x20]; 7687 7688 u8 ib_link_width_capability[0x10]; 7689 u8 ib_proto_capability[0x10]; 7690 7691 u8 reserved_at_a0[0x20]; 7692 7693 u8 eth_proto_admin[0x20]; 7694 7695 u8 ib_link_width_admin[0x10]; 7696 u8 ib_proto_admin[0x10]; 7697 7698 u8 reserved_at_100[0x20]; 7699 7700 u8 eth_proto_oper[0x20]; 7701 7702 u8 ib_link_width_oper[0x10]; 7703 u8 ib_proto_oper[0x10]; 7704 7705 u8 reserved_at_160[0x1c]; 7706 u8 connector_type[0x4]; 7707 7708 u8 eth_proto_lp_advertise[0x20]; 7709 7710 u8 reserved_at_1a0[0x60]; 7711 }; 7712 7713 struct mlx5_ifc_mlcr_reg_bits { 7714 u8 reserved_at_0[0x8]; 7715 u8 local_port[0x8]; 7716 u8 reserved_at_10[0x20]; 7717 7718 u8 beacon_duration[0x10]; 7719 u8 reserved_at_40[0x10]; 7720 7721 u8 beacon_remain[0x10]; 7722 }; 7723 7724 struct mlx5_ifc_ptas_reg_bits { 7725 u8 reserved_at_0[0x20]; 7726 7727 u8 algorithm_options[0x10]; 7728 u8 reserved_at_30[0x4]; 7729 u8 repetitions_mode[0x4]; 7730 u8 num_of_repetitions[0x8]; 7731 7732 u8 grade_version[0x8]; 7733 u8 height_grade_type[0x4]; 7734 u8 phase_grade_type[0x4]; 7735 u8 height_grade_weight[0x8]; 7736 u8 phase_grade_weight[0x8]; 7737 7738 u8 gisim_measure_bits[0x10]; 7739 u8 adaptive_tap_measure_bits[0x10]; 7740 7741 u8 ber_bath_high_error_threshold[0x10]; 7742 u8 ber_bath_mid_error_threshold[0x10]; 7743 7744 u8 ber_bath_low_error_threshold[0x10]; 7745 u8 one_ratio_high_threshold[0x10]; 7746 7747 u8 one_ratio_high_mid_threshold[0x10]; 7748 u8 one_ratio_low_mid_threshold[0x10]; 7749 7750 u8 one_ratio_low_threshold[0x10]; 7751 u8 ndeo_error_threshold[0x10]; 7752 7753 u8 mixer_offset_step_size[0x10]; 7754 u8 reserved_at_110[0x8]; 7755 u8 mix90_phase_for_voltage_bath[0x8]; 7756 7757 u8 mixer_offset_start[0x10]; 7758 u8 mixer_offset_end[0x10]; 7759 7760 u8 reserved_at_140[0x15]; 7761 u8 ber_test_time[0xb]; 7762 }; 7763 7764 struct mlx5_ifc_pspa_reg_bits { 7765 u8 swid[0x8]; 7766 u8 local_port[0x8]; 7767 u8 sub_port[0x8]; 7768 u8 reserved_at_18[0x8]; 7769 7770 u8 reserved_at_20[0x20]; 7771 }; 7772 7773 struct mlx5_ifc_pqdr_reg_bits { 7774 u8 reserved_at_0[0x8]; 7775 u8 local_port[0x8]; 7776 u8 reserved_at_10[0x5]; 7777 u8 prio[0x3]; 7778 u8 reserved_at_18[0x6]; 7779 u8 mode[0x2]; 7780 7781 u8 reserved_at_20[0x20]; 7782 7783 u8 reserved_at_40[0x10]; 7784 u8 min_threshold[0x10]; 7785 7786 u8 reserved_at_60[0x10]; 7787 u8 max_threshold[0x10]; 7788 7789 u8 reserved_at_80[0x10]; 7790 u8 mark_probability_denominator[0x10]; 7791 7792 u8 reserved_at_a0[0x60]; 7793 }; 7794 7795 struct mlx5_ifc_ppsc_reg_bits { 7796 u8 reserved_at_0[0x8]; 7797 u8 local_port[0x8]; 7798 u8 reserved_at_10[0x10]; 7799 7800 u8 reserved_at_20[0x60]; 7801 7802 u8 reserved_at_80[0x1c]; 7803 u8 wrps_admin[0x4]; 7804 7805 u8 reserved_at_a0[0x1c]; 7806 u8 wrps_status[0x4]; 7807 7808 u8 reserved_at_c0[0x8]; 7809 u8 up_threshold[0x8]; 7810 u8 reserved_at_d0[0x8]; 7811 u8 down_threshold[0x8]; 7812 7813 u8 reserved_at_e0[0x20]; 7814 7815 u8 reserved_at_100[0x1c]; 7816 u8 srps_admin[0x4]; 7817 7818 u8 reserved_at_120[0x1c]; 7819 u8 srps_status[0x4]; 7820 7821 u8 reserved_at_140[0x40]; 7822 }; 7823 7824 struct mlx5_ifc_pplr_reg_bits { 7825 u8 reserved_at_0[0x8]; 7826 u8 local_port[0x8]; 7827 u8 reserved_at_10[0x10]; 7828 7829 u8 reserved_at_20[0x8]; 7830 u8 lb_cap[0x8]; 7831 u8 reserved_at_30[0x8]; 7832 u8 lb_en[0x8]; 7833 }; 7834 7835 struct mlx5_ifc_pplm_reg_bits { 7836 u8 reserved_at_0[0x8]; 7837 u8 local_port[0x8]; 7838 u8 reserved_at_10[0x10]; 7839 7840 u8 reserved_at_20[0x20]; 7841 7842 u8 port_profile_mode[0x8]; 7843 u8 static_port_profile[0x8]; 7844 u8 active_port_profile[0x8]; 7845 u8 reserved_at_58[0x8]; 7846 7847 u8 retransmission_active[0x8]; 7848 u8 fec_mode_active[0x18]; 7849 7850 u8 rs_fec_correction_bypass_cap[0x4]; 7851 u8 reserved_at_84[0x8]; 7852 u8 fec_override_cap_56g[0x4]; 7853 u8 fec_override_cap_100g[0x4]; 7854 u8 fec_override_cap_50g[0x4]; 7855 u8 fec_override_cap_25g[0x4]; 7856 u8 fec_override_cap_10g_40g[0x4]; 7857 7858 u8 rs_fec_correction_bypass_admin[0x4]; 7859 u8 reserved_at_a4[0x8]; 7860 u8 fec_override_admin_56g[0x4]; 7861 u8 fec_override_admin_100g[0x4]; 7862 u8 fec_override_admin_50g[0x4]; 7863 u8 fec_override_admin_25g[0x4]; 7864 u8 fec_override_admin_10g_40g[0x4]; 7865 }; 7866 7867 struct mlx5_ifc_ppcnt_reg_bits { 7868 u8 swid[0x8]; 7869 u8 local_port[0x8]; 7870 u8 pnat[0x2]; 7871 u8 reserved_at_12[0x8]; 7872 u8 grp[0x6]; 7873 7874 u8 clr[0x1]; 7875 u8 reserved_at_21[0x1c]; 7876 u8 prio_tc[0x3]; 7877 7878 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set; 7879 }; 7880 7881 struct mlx5_ifc_mpcnt_reg_bits { 7882 u8 reserved_at_0[0x8]; 7883 u8 pcie_index[0x8]; 7884 u8 reserved_at_10[0xa]; 7885 u8 grp[0x6]; 7886 7887 u8 clr[0x1]; 7888 u8 reserved_at_21[0x1f]; 7889 7890 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set; 7891 }; 7892 7893 struct mlx5_ifc_ppad_reg_bits { 7894 u8 reserved_at_0[0x3]; 7895 u8 single_mac[0x1]; 7896 u8 reserved_at_4[0x4]; 7897 u8 local_port[0x8]; 7898 u8 mac_47_32[0x10]; 7899 7900 u8 mac_31_0[0x20]; 7901 7902 u8 reserved_at_40[0x40]; 7903 }; 7904 7905 struct mlx5_ifc_pmtu_reg_bits { 7906 u8 reserved_at_0[0x8]; 7907 u8 local_port[0x8]; 7908 u8 reserved_at_10[0x10]; 7909 7910 u8 max_mtu[0x10]; 7911 u8 reserved_at_30[0x10]; 7912 7913 u8 admin_mtu[0x10]; 7914 u8 reserved_at_50[0x10]; 7915 7916 u8 oper_mtu[0x10]; 7917 u8 reserved_at_70[0x10]; 7918 }; 7919 7920 struct mlx5_ifc_pmpr_reg_bits { 7921 u8 reserved_at_0[0x8]; 7922 u8 module[0x8]; 7923 u8 reserved_at_10[0x10]; 7924 7925 u8 reserved_at_20[0x18]; 7926 u8 attenuation_5g[0x8]; 7927 7928 u8 reserved_at_40[0x18]; 7929 u8 attenuation_7g[0x8]; 7930 7931 u8 reserved_at_60[0x18]; 7932 u8 attenuation_12g[0x8]; 7933 }; 7934 7935 struct mlx5_ifc_pmpe_reg_bits { 7936 u8 reserved_at_0[0x8]; 7937 u8 module[0x8]; 7938 u8 reserved_at_10[0xc]; 7939 u8 module_status[0x4]; 7940 7941 u8 reserved_at_20[0x60]; 7942 }; 7943 7944 struct mlx5_ifc_pmpc_reg_bits { 7945 u8 module_state_updated[32][0x8]; 7946 }; 7947 7948 struct mlx5_ifc_pmlpn_reg_bits { 7949 u8 reserved_at_0[0x4]; 7950 u8 mlpn_status[0x4]; 7951 u8 local_port[0x8]; 7952 u8 reserved_at_10[0x10]; 7953 7954 u8 e[0x1]; 7955 u8 reserved_at_21[0x1f]; 7956 }; 7957 7958 struct mlx5_ifc_pmlp_reg_bits { 7959 u8 rxtx[0x1]; 7960 u8 reserved_at_1[0x7]; 7961 u8 local_port[0x8]; 7962 u8 reserved_at_10[0x8]; 7963 u8 width[0x8]; 7964 7965 u8 lane0_module_mapping[0x20]; 7966 7967 u8 lane1_module_mapping[0x20]; 7968 7969 u8 lane2_module_mapping[0x20]; 7970 7971 u8 lane3_module_mapping[0x20]; 7972 7973 u8 reserved_at_a0[0x160]; 7974 }; 7975 7976 struct mlx5_ifc_pmaos_reg_bits { 7977 u8 reserved_at_0[0x8]; 7978 u8 module[0x8]; 7979 u8 reserved_at_10[0x4]; 7980 u8 admin_status[0x4]; 7981 u8 reserved_at_18[0x4]; 7982 u8 oper_status[0x4]; 7983 7984 u8 ase[0x1]; 7985 u8 ee[0x1]; 7986 u8 reserved_at_22[0x1c]; 7987 u8 e[0x2]; 7988 7989 u8 reserved_at_40[0x40]; 7990 }; 7991 7992 struct mlx5_ifc_plpc_reg_bits { 7993 u8 reserved_at_0[0x4]; 7994 u8 profile_id[0xc]; 7995 u8 reserved_at_10[0x4]; 7996 u8 proto_mask[0x4]; 7997 u8 reserved_at_18[0x8]; 7998 7999 u8 reserved_at_20[0x10]; 8000 u8 lane_speed[0x10]; 8001 8002 u8 reserved_at_40[0x17]; 8003 u8 lpbf[0x1]; 8004 u8 fec_mode_policy[0x8]; 8005 8006 u8 retransmission_capability[0x8]; 8007 u8 fec_mode_capability[0x18]; 8008 8009 u8 retransmission_support_admin[0x8]; 8010 u8 fec_mode_support_admin[0x18]; 8011 8012 u8 retransmission_request_admin[0x8]; 8013 u8 fec_mode_request_admin[0x18]; 8014 8015 u8 reserved_at_c0[0x80]; 8016 }; 8017 8018 struct mlx5_ifc_plib_reg_bits { 8019 u8 reserved_at_0[0x8]; 8020 u8 local_port[0x8]; 8021 u8 reserved_at_10[0x8]; 8022 u8 ib_port[0x8]; 8023 8024 u8 reserved_at_20[0x60]; 8025 }; 8026 8027 struct mlx5_ifc_plbf_reg_bits { 8028 u8 reserved_at_0[0x8]; 8029 u8 local_port[0x8]; 8030 u8 reserved_at_10[0xd]; 8031 u8 lbf_mode[0x3]; 8032 8033 u8 reserved_at_20[0x20]; 8034 }; 8035 8036 struct mlx5_ifc_pipg_reg_bits { 8037 u8 reserved_at_0[0x8]; 8038 u8 local_port[0x8]; 8039 u8 reserved_at_10[0x10]; 8040 8041 u8 dic[0x1]; 8042 u8 reserved_at_21[0x19]; 8043 u8 ipg[0x4]; 8044 u8 reserved_at_3e[0x2]; 8045 }; 8046 8047 struct mlx5_ifc_pifr_reg_bits { 8048 u8 reserved_at_0[0x8]; 8049 u8 local_port[0x8]; 8050 u8 reserved_at_10[0x10]; 8051 8052 u8 reserved_at_20[0xe0]; 8053 8054 u8 port_filter[8][0x20]; 8055 8056 u8 port_filter_update_en[8][0x20]; 8057 }; 8058 8059 struct mlx5_ifc_pfcc_reg_bits { 8060 u8 reserved_at_0[0x8]; 8061 u8 local_port[0x8]; 8062 u8 reserved_at_10[0xb]; 8063 u8 ppan_mask_n[0x1]; 8064 u8 minor_stall_mask[0x1]; 8065 u8 critical_stall_mask[0x1]; 8066 u8 reserved_at_1e[0x2]; 8067 8068 u8 ppan[0x4]; 8069 u8 reserved_at_24[0x4]; 8070 u8 prio_mask_tx[0x8]; 8071 u8 reserved_at_30[0x8]; 8072 u8 prio_mask_rx[0x8]; 8073 8074 u8 pptx[0x1]; 8075 u8 aptx[0x1]; 8076 u8 pptx_mask_n[0x1]; 8077 u8 reserved_at_43[0x5]; 8078 u8 pfctx[0x8]; 8079 u8 reserved_at_50[0x10]; 8080 8081 u8 pprx[0x1]; 8082 u8 aprx[0x1]; 8083 u8 pprx_mask_n[0x1]; 8084 u8 reserved_at_63[0x5]; 8085 u8 pfcrx[0x8]; 8086 u8 reserved_at_70[0x10]; 8087 8088 u8 device_stall_minor_watermark[0x10]; 8089 u8 device_stall_critical_watermark[0x10]; 8090 8091 u8 reserved_at_a0[0x60]; 8092 }; 8093 8094 struct mlx5_ifc_pelc_reg_bits { 8095 u8 op[0x4]; 8096 u8 reserved_at_4[0x4]; 8097 u8 local_port[0x8]; 8098 u8 reserved_at_10[0x10]; 8099 8100 u8 op_admin[0x8]; 8101 u8 op_capability[0x8]; 8102 u8 op_request[0x8]; 8103 u8 op_active[0x8]; 8104 8105 u8 admin[0x40]; 8106 8107 u8 capability[0x40]; 8108 8109 u8 request[0x40]; 8110 8111 u8 active[0x40]; 8112 8113 u8 reserved_at_140[0x80]; 8114 }; 8115 8116 struct mlx5_ifc_peir_reg_bits { 8117 u8 reserved_at_0[0x8]; 8118 u8 local_port[0x8]; 8119 u8 reserved_at_10[0x10]; 8120 8121 u8 reserved_at_20[0xc]; 8122 u8 error_count[0x4]; 8123 u8 reserved_at_30[0x10]; 8124 8125 u8 reserved_at_40[0xc]; 8126 u8 lane[0x4]; 8127 u8 reserved_at_50[0x8]; 8128 u8 error_type[0x8]; 8129 }; 8130 8131 struct mlx5_ifc_mpegc_reg_bits { 8132 u8 reserved_at_0[0x30]; 8133 u8 field_select[0x10]; 8134 8135 u8 tx_overflow_sense[0x1]; 8136 u8 mark_cqe[0x1]; 8137 u8 mark_cnp[0x1]; 8138 u8 reserved_at_43[0x1b]; 8139 u8 tx_lossy_overflow_oper[0x2]; 8140 8141 u8 reserved_at_60[0x100]; 8142 }; 8143 8144 struct mlx5_ifc_pcam_enhanced_features_bits { 8145 u8 reserved_at_0[0x6d]; 8146 u8 rx_icrc_encapsulated_counter[0x1]; 8147 u8 reserved_at_6e[0x8]; 8148 u8 pfcc_mask[0x1]; 8149 u8 reserved_at_77[0x3]; 8150 u8 per_lane_error_counters[0x1]; 8151 u8 rx_buffer_fullness_counters[0x1]; 8152 u8 ptys_connector_type[0x1]; 8153 u8 reserved_at_7d[0x1]; 8154 u8 ppcnt_discard_group[0x1]; 8155 u8 ppcnt_statistical_group[0x1]; 8156 }; 8157 8158 struct mlx5_ifc_pcam_regs_5000_to_507f_bits { 8159 u8 port_access_reg_cap_mask_127_to_96[0x20]; 8160 u8 port_access_reg_cap_mask_95_to_64[0x20]; 8161 8162 u8 port_access_reg_cap_mask_63_to_36[0x1c]; 8163 u8 pplm[0x1]; 8164 u8 port_access_reg_cap_mask_34_to_32[0x3]; 8165 8166 u8 port_access_reg_cap_mask_31_to_13[0x13]; 8167 u8 pbmc[0x1]; 8168 u8 pptb[0x1]; 8169 u8 port_access_reg_cap_mask_10_to_0[0xb]; 8170 }; 8171 8172 struct mlx5_ifc_pcam_reg_bits { 8173 u8 reserved_at_0[0x8]; 8174 u8 feature_group[0x8]; 8175 u8 reserved_at_10[0x8]; 8176 u8 access_reg_group[0x8]; 8177 8178 u8 reserved_at_20[0x20]; 8179 8180 union { 8181 struct mlx5_ifc_pcam_regs_5000_to_507f_bits regs_5000_to_507f; 8182 u8 reserved_at_0[0x80]; 8183 } port_access_reg_cap_mask; 8184 8185 u8 reserved_at_c0[0x80]; 8186 8187 union { 8188 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features; 8189 u8 reserved_at_0[0x80]; 8190 } feature_cap_mask; 8191 8192 u8 reserved_at_1c0[0xc0]; 8193 }; 8194 8195 struct mlx5_ifc_mcam_enhanced_features_bits { 8196 u8 reserved_at_0[0x74]; 8197 u8 mark_tx_action_cnp[0x1]; 8198 u8 mark_tx_action_cqe[0x1]; 8199 u8 dynamic_tx_overflow[0x1]; 8200 u8 reserved_at_77[0x4]; 8201 u8 pcie_outbound_stalled[0x1]; 8202 u8 tx_overflow_buffer_pkt[0x1]; 8203 u8 mtpps_enh_out_per_adj[0x1]; 8204 u8 mtpps_fs[0x1]; 8205 u8 pcie_performance_group[0x1]; 8206 }; 8207 8208 struct mlx5_ifc_mcam_access_reg_bits { 8209 u8 reserved_at_0[0x1c]; 8210 u8 mcda[0x1]; 8211 u8 mcc[0x1]; 8212 u8 mcqi[0x1]; 8213 u8 reserved_at_1f[0x1]; 8214 8215 u8 regs_95_to_87[0x9]; 8216 u8 mpegc[0x1]; 8217 u8 regs_85_to_68[0x12]; 8218 u8 tracer_registers[0x4]; 8219 8220 u8 regs_63_to_32[0x20]; 8221 u8 regs_31_to_0[0x20]; 8222 }; 8223 8224 struct mlx5_ifc_mcam_reg_bits { 8225 u8 reserved_at_0[0x8]; 8226 u8 feature_group[0x8]; 8227 u8 reserved_at_10[0x8]; 8228 u8 access_reg_group[0x8]; 8229 8230 u8 reserved_at_20[0x20]; 8231 8232 union { 8233 struct mlx5_ifc_mcam_access_reg_bits access_regs; 8234 u8 reserved_at_0[0x80]; 8235 } mng_access_reg_cap_mask; 8236 8237 u8 reserved_at_c0[0x80]; 8238 8239 union { 8240 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features; 8241 u8 reserved_at_0[0x80]; 8242 } mng_feature_cap_mask; 8243 8244 u8 reserved_at_1c0[0x80]; 8245 }; 8246 8247 struct mlx5_ifc_qcam_access_reg_cap_mask { 8248 u8 qcam_access_reg_cap_mask_127_to_20[0x6C]; 8249 u8 qpdpm[0x1]; 8250 u8 qcam_access_reg_cap_mask_18_to_4[0x0F]; 8251 u8 qdpm[0x1]; 8252 u8 qpts[0x1]; 8253 u8 qcap[0x1]; 8254 u8 qcam_access_reg_cap_mask_0[0x1]; 8255 }; 8256 8257 struct mlx5_ifc_qcam_qos_feature_cap_mask { 8258 u8 qcam_qos_feature_cap_mask_127_to_1[0x7F]; 8259 u8 qpts_trust_both[0x1]; 8260 }; 8261 8262 struct mlx5_ifc_qcam_reg_bits { 8263 u8 reserved_at_0[0x8]; 8264 u8 feature_group[0x8]; 8265 u8 reserved_at_10[0x8]; 8266 u8 access_reg_group[0x8]; 8267 u8 reserved_at_20[0x20]; 8268 8269 union { 8270 struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap; 8271 u8 reserved_at_0[0x80]; 8272 } qos_access_reg_cap_mask; 8273 8274 u8 reserved_at_c0[0x80]; 8275 8276 union { 8277 struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap; 8278 u8 reserved_at_0[0x80]; 8279 } qos_feature_cap_mask; 8280 8281 u8 reserved_at_1c0[0x80]; 8282 }; 8283 8284 struct mlx5_ifc_pcap_reg_bits { 8285 u8 reserved_at_0[0x8]; 8286 u8 local_port[0x8]; 8287 u8 reserved_at_10[0x10]; 8288 8289 u8 port_capability_mask[4][0x20]; 8290 }; 8291 8292 struct mlx5_ifc_paos_reg_bits { 8293 u8 swid[0x8]; 8294 u8 local_port[0x8]; 8295 u8 reserved_at_10[0x4]; 8296 u8 admin_status[0x4]; 8297 u8 reserved_at_18[0x4]; 8298 u8 oper_status[0x4]; 8299 8300 u8 ase[0x1]; 8301 u8 ee[0x1]; 8302 u8 reserved_at_22[0x1c]; 8303 u8 e[0x2]; 8304 8305 u8 reserved_at_40[0x40]; 8306 }; 8307 8308 struct mlx5_ifc_pamp_reg_bits { 8309 u8 reserved_at_0[0x8]; 8310 u8 opamp_group[0x8]; 8311 u8 reserved_at_10[0xc]; 8312 u8 opamp_group_type[0x4]; 8313 8314 u8 start_index[0x10]; 8315 u8 reserved_at_30[0x4]; 8316 u8 num_of_indices[0xc]; 8317 8318 u8 index_data[18][0x10]; 8319 }; 8320 8321 struct mlx5_ifc_pcmr_reg_bits { 8322 u8 reserved_at_0[0x8]; 8323 u8 local_port[0x8]; 8324 u8 reserved_at_10[0x2e]; 8325 u8 fcs_cap[0x1]; 8326 u8 reserved_at_3f[0x1f]; 8327 u8 fcs_chk[0x1]; 8328 u8 reserved_at_5f[0x1]; 8329 }; 8330 8331 struct mlx5_ifc_lane_2_module_mapping_bits { 8332 u8 reserved_at_0[0x6]; 8333 u8 rx_lane[0x2]; 8334 u8 reserved_at_8[0x6]; 8335 u8 tx_lane[0x2]; 8336 u8 reserved_at_10[0x8]; 8337 u8 module[0x8]; 8338 }; 8339 8340 struct mlx5_ifc_bufferx_reg_bits { 8341 u8 reserved_at_0[0x6]; 8342 u8 lossy[0x1]; 8343 u8 epsb[0x1]; 8344 u8 reserved_at_8[0xc]; 8345 u8 size[0xc]; 8346 8347 u8 xoff_threshold[0x10]; 8348 u8 xon_threshold[0x10]; 8349 }; 8350 8351 struct mlx5_ifc_set_node_in_bits { 8352 u8 node_description[64][0x8]; 8353 }; 8354 8355 struct mlx5_ifc_register_power_settings_bits { 8356 u8 reserved_at_0[0x18]; 8357 u8 power_settings_level[0x8]; 8358 8359 u8 reserved_at_20[0x60]; 8360 }; 8361 8362 struct mlx5_ifc_register_host_endianness_bits { 8363 u8 he[0x1]; 8364 u8 reserved_at_1[0x1f]; 8365 8366 u8 reserved_at_20[0x60]; 8367 }; 8368 8369 struct mlx5_ifc_umr_pointer_desc_argument_bits { 8370 u8 reserved_at_0[0x20]; 8371 8372 u8 mkey[0x20]; 8373 8374 u8 addressh_63_32[0x20]; 8375 8376 u8 addressl_31_0[0x20]; 8377 }; 8378 8379 struct mlx5_ifc_ud_adrs_vector_bits { 8380 u8 dc_key[0x40]; 8381 8382 u8 ext[0x1]; 8383 u8 reserved_at_41[0x7]; 8384 u8 destination_qp_dct[0x18]; 8385 8386 u8 static_rate[0x4]; 8387 u8 sl_eth_prio[0x4]; 8388 u8 fl[0x1]; 8389 u8 mlid[0x7]; 8390 u8 rlid_udp_sport[0x10]; 8391 8392 u8 reserved_at_80[0x20]; 8393 8394 u8 rmac_47_16[0x20]; 8395 8396 u8 rmac_15_0[0x10]; 8397 u8 tclass[0x8]; 8398 u8 hop_limit[0x8]; 8399 8400 u8 reserved_at_e0[0x1]; 8401 u8 grh[0x1]; 8402 u8 reserved_at_e2[0x2]; 8403 u8 src_addr_index[0x8]; 8404 u8 flow_label[0x14]; 8405 8406 u8 rgid_rip[16][0x8]; 8407 }; 8408 8409 struct mlx5_ifc_pages_req_event_bits { 8410 u8 reserved_at_0[0x10]; 8411 u8 function_id[0x10]; 8412 8413 u8 num_pages[0x20]; 8414 8415 u8 reserved_at_40[0xa0]; 8416 }; 8417 8418 struct mlx5_ifc_eqe_bits { 8419 u8 reserved_at_0[0x8]; 8420 u8 event_type[0x8]; 8421 u8 reserved_at_10[0x8]; 8422 u8 event_sub_type[0x8]; 8423 8424 u8 reserved_at_20[0xe0]; 8425 8426 union mlx5_ifc_event_auto_bits event_data; 8427 8428 u8 reserved_at_1e0[0x10]; 8429 u8 signature[0x8]; 8430 u8 reserved_at_1f8[0x7]; 8431 u8 owner[0x1]; 8432 }; 8433 8434 enum { 8435 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7, 8436 }; 8437 8438 struct mlx5_ifc_cmd_queue_entry_bits { 8439 u8 type[0x8]; 8440 u8 reserved_at_8[0x18]; 8441 8442 u8 input_length[0x20]; 8443 8444 u8 input_mailbox_pointer_63_32[0x20]; 8445 8446 u8 input_mailbox_pointer_31_9[0x17]; 8447 u8 reserved_at_77[0x9]; 8448 8449 u8 command_input_inline_data[16][0x8]; 8450 8451 u8 command_output_inline_data[16][0x8]; 8452 8453 u8 output_mailbox_pointer_63_32[0x20]; 8454 8455 u8 output_mailbox_pointer_31_9[0x17]; 8456 u8 reserved_at_1b7[0x9]; 8457 8458 u8 output_length[0x20]; 8459 8460 u8 token[0x8]; 8461 u8 signature[0x8]; 8462 u8 reserved_at_1f0[0x8]; 8463 u8 status[0x7]; 8464 u8 ownership[0x1]; 8465 }; 8466 8467 struct mlx5_ifc_cmd_out_bits { 8468 u8 status[0x8]; 8469 u8 reserved_at_8[0x18]; 8470 8471 u8 syndrome[0x20]; 8472 8473 u8 command_output[0x20]; 8474 }; 8475 8476 struct mlx5_ifc_cmd_in_bits { 8477 u8 opcode[0x10]; 8478 u8 reserved_at_10[0x10]; 8479 8480 u8 reserved_at_20[0x10]; 8481 u8 op_mod[0x10]; 8482 8483 u8 command[0][0x20]; 8484 }; 8485 8486 struct mlx5_ifc_cmd_if_box_bits { 8487 u8 mailbox_data[512][0x8]; 8488 8489 u8 reserved_at_1000[0x180]; 8490 8491 u8 next_pointer_63_32[0x20]; 8492 8493 u8 next_pointer_31_10[0x16]; 8494 u8 reserved_at_11b6[0xa]; 8495 8496 u8 block_number[0x20]; 8497 8498 u8 reserved_at_11e0[0x8]; 8499 u8 token[0x8]; 8500 u8 ctrl_signature[0x8]; 8501 u8 signature[0x8]; 8502 }; 8503 8504 struct mlx5_ifc_mtt_bits { 8505 u8 ptag_63_32[0x20]; 8506 8507 u8 ptag_31_8[0x18]; 8508 u8 reserved_at_38[0x6]; 8509 u8 wr_en[0x1]; 8510 u8 rd_en[0x1]; 8511 }; 8512 8513 struct mlx5_ifc_query_wol_rol_out_bits { 8514 u8 status[0x8]; 8515 u8 reserved_at_8[0x18]; 8516 8517 u8 syndrome[0x20]; 8518 8519 u8 reserved_at_40[0x10]; 8520 u8 rol_mode[0x8]; 8521 u8 wol_mode[0x8]; 8522 8523 u8 reserved_at_60[0x20]; 8524 }; 8525 8526 struct mlx5_ifc_query_wol_rol_in_bits { 8527 u8 opcode[0x10]; 8528 u8 reserved_at_10[0x10]; 8529 8530 u8 reserved_at_20[0x10]; 8531 u8 op_mod[0x10]; 8532 8533 u8 reserved_at_40[0x40]; 8534 }; 8535 8536 struct mlx5_ifc_set_wol_rol_out_bits { 8537 u8 status[0x8]; 8538 u8 reserved_at_8[0x18]; 8539 8540 u8 syndrome[0x20]; 8541 8542 u8 reserved_at_40[0x40]; 8543 }; 8544 8545 struct mlx5_ifc_set_wol_rol_in_bits { 8546 u8 opcode[0x10]; 8547 u8 reserved_at_10[0x10]; 8548 8549 u8 reserved_at_20[0x10]; 8550 u8 op_mod[0x10]; 8551 8552 u8 rol_mode_valid[0x1]; 8553 u8 wol_mode_valid[0x1]; 8554 u8 reserved_at_42[0xe]; 8555 u8 rol_mode[0x8]; 8556 u8 wol_mode[0x8]; 8557 8558 u8 reserved_at_60[0x20]; 8559 }; 8560 8561 enum { 8562 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0, 8563 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1, 8564 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2, 8565 }; 8566 8567 enum { 8568 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0, 8569 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1, 8570 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2, 8571 }; 8572 8573 enum { 8574 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR = 0x1, 8575 MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC = 0x7, 8576 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR = 0x8, 8577 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR = 0x9, 8578 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR = 0xa, 8579 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR = 0xb, 8580 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN = 0xc, 8581 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR = 0xd, 8582 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV = 0xe, 8583 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR = 0xf, 8584 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR = 0x10, 8585 }; 8586 8587 struct mlx5_ifc_initial_seg_bits { 8588 u8 fw_rev_minor[0x10]; 8589 u8 fw_rev_major[0x10]; 8590 8591 u8 cmd_interface_rev[0x10]; 8592 u8 fw_rev_subminor[0x10]; 8593 8594 u8 reserved_at_40[0x40]; 8595 8596 u8 cmdq_phy_addr_63_32[0x20]; 8597 8598 u8 cmdq_phy_addr_31_12[0x14]; 8599 u8 reserved_at_b4[0x2]; 8600 u8 nic_interface[0x2]; 8601 u8 log_cmdq_size[0x4]; 8602 u8 log_cmdq_stride[0x4]; 8603 8604 u8 command_doorbell_vector[0x20]; 8605 8606 u8 reserved_at_e0[0xf00]; 8607 8608 u8 initializing[0x1]; 8609 u8 reserved_at_fe1[0x4]; 8610 u8 nic_interface_supported[0x3]; 8611 u8 reserved_at_fe8[0x18]; 8612 8613 struct mlx5_ifc_health_buffer_bits health_buffer; 8614 8615 u8 no_dram_nic_offset[0x20]; 8616 8617 u8 reserved_at_1220[0x6e40]; 8618 8619 u8 reserved_at_8060[0x1f]; 8620 u8 clear_int[0x1]; 8621 8622 u8 health_syndrome[0x8]; 8623 u8 health_counter[0x18]; 8624 8625 u8 reserved_at_80a0[0x17fc0]; 8626 }; 8627 8628 struct mlx5_ifc_mtpps_reg_bits { 8629 u8 reserved_at_0[0xc]; 8630 u8 cap_number_of_pps_pins[0x4]; 8631 u8 reserved_at_10[0x4]; 8632 u8 cap_max_num_of_pps_in_pins[0x4]; 8633 u8 reserved_at_18[0x4]; 8634 u8 cap_max_num_of_pps_out_pins[0x4]; 8635 8636 u8 reserved_at_20[0x24]; 8637 u8 cap_pin_3_mode[0x4]; 8638 u8 reserved_at_48[0x4]; 8639 u8 cap_pin_2_mode[0x4]; 8640 u8 reserved_at_50[0x4]; 8641 u8 cap_pin_1_mode[0x4]; 8642 u8 reserved_at_58[0x4]; 8643 u8 cap_pin_0_mode[0x4]; 8644 8645 u8 reserved_at_60[0x4]; 8646 u8 cap_pin_7_mode[0x4]; 8647 u8 reserved_at_68[0x4]; 8648 u8 cap_pin_6_mode[0x4]; 8649 u8 reserved_at_70[0x4]; 8650 u8 cap_pin_5_mode[0x4]; 8651 u8 reserved_at_78[0x4]; 8652 u8 cap_pin_4_mode[0x4]; 8653 8654 u8 field_select[0x20]; 8655 u8 reserved_at_a0[0x60]; 8656 8657 u8 enable[0x1]; 8658 u8 reserved_at_101[0xb]; 8659 u8 pattern[0x4]; 8660 u8 reserved_at_110[0x4]; 8661 u8 pin_mode[0x4]; 8662 u8 pin[0x8]; 8663 8664 u8 reserved_at_120[0x20]; 8665 8666 u8 time_stamp[0x40]; 8667 8668 u8 out_pulse_duration[0x10]; 8669 u8 out_periodic_adjustment[0x10]; 8670 u8 enhanced_out_periodic_adjustment[0x20]; 8671 8672 u8 reserved_at_1c0[0x20]; 8673 }; 8674 8675 struct mlx5_ifc_mtppse_reg_bits { 8676 u8 reserved_at_0[0x18]; 8677 u8 pin[0x8]; 8678 u8 event_arm[0x1]; 8679 u8 reserved_at_21[0x1b]; 8680 u8 event_generation_mode[0x4]; 8681 u8 reserved_at_40[0x40]; 8682 }; 8683 8684 struct mlx5_ifc_mcqi_cap_bits { 8685 u8 supported_info_bitmask[0x20]; 8686 8687 u8 component_size[0x20]; 8688 8689 u8 max_component_size[0x20]; 8690 8691 u8 log_mcda_word_size[0x4]; 8692 u8 reserved_at_64[0xc]; 8693 u8 mcda_max_write_size[0x10]; 8694 8695 u8 rd_en[0x1]; 8696 u8 reserved_at_81[0x1]; 8697 u8 match_chip_id[0x1]; 8698 u8 match_psid[0x1]; 8699 u8 check_user_timestamp[0x1]; 8700 u8 match_base_guid_mac[0x1]; 8701 u8 reserved_at_86[0x1a]; 8702 }; 8703 8704 struct mlx5_ifc_mcqi_reg_bits { 8705 u8 read_pending_component[0x1]; 8706 u8 reserved_at_1[0xf]; 8707 u8 component_index[0x10]; 8708 8709 u8 reserved_at_20[0x20]; 8710 8711 u8 reserved_at_40[0x1b]; 8712 u8 info_type[0x5]; 8713 8714 u8 info_size[0x20]; 8715 8716 u8 offset[0x20]; 8717 8718 u8 reserved_at_a0[0x10]; 8719 u8 data_size[0x10]; 8720 8721 u8 data[0][0x20]; 8722 }; 8723 8724 struct mlx5_ifc_mcc_reg_bits { 8725 u8 reserved_at_0[0x4]; 8726 u8 time_elapsed_since_last_cmd[0xc]; 8727 u8 reserved_at_10[0x8]; 8728 u8 instruction[0x8]; 8729 8730 u8 reserved_at_20[0x10]; 8731 u8 component_index[0x10]; 8732 8733 u8 reserved_at_40[0x8]; 8734 u8 update_handle[0x18]; 8735 8736 u8 handle_owner_type[0x4]; 8737 u8 handle_owner_host_id[0x4]; 8738 u8 reserved_at_68[0x1]; 8739 u8 control_progress[0x7]; 8740 u8 error_code[0x8]; 8741 u8 reserved_at_78[0x4]; 8742 u8 control_state[0x4]; 8743 8744 u8 component_size[0x20]; 8745 8746 u8 reserved_at_a0[0x60]; 8747 }; 8748 8749 struct mlx5_ifc_mcda_reg_bits { 8750 u8 reserved_at_0[0x8]; 8751 u8 update_handle[0x18]; 8752 8753 u8 offset[0x20]; 8754 8755 u8 reserved_at_40[0x10]; 8756 u8 size[0x10]; 8757 8758 u8 reserved_at_60[0x20]; 8759 8760 u8 data[0][0x20]; 8761 }; 8762 8763 union mlx5_ifc_ports_control_registers_document_bits { 8764 struct mlx5_ifc_bufferx_reg_bits bufferx_reg; 8765 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 8766 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 8767 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 8768 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 8769 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 8770 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 8771 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout; 8772 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping; 8773 struct mlx5_ifc_pamp_reg_bits pamp_reg; 8774 struct mlx5_ifc_paos_reg_bits paos_reg; 8775 struct mlx5_ifc_pcap_reg_bits pcap_reg; 8776 struct mlx5_ifc_peir_reg_bits peir_reg; 8777 struct mlx5_ifc_pelc_reg_bits pelc_reg; 8778 struct mlx5_ifc_pfcc_reg_bits pfcc_reg; 8779 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 8780 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 8781 struct mlx5_ifc_pifr_reg_bits pifr_reg; 8782 struct mlx5_ifc_pipg_reg_bits pipg_reg; 8783 struct mlx5_ifc_plbf_reg_bits plbf_reg; 8784 struct mlx5_ifc_plib_reg_bits plib_reg; 8785 struct mlx5_ifc_plpc_reg_bits plpc_reg; 8786 struct mlx5_ifc_pmaos_reg_bits pmaos_reg; 8787 struct mlx5_ifc_pmlp_reg_bits pmlp_reg; 8788 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg; 8789 struct mlx5_ifc_pmpc_reg_bits pmpc_reg; 8790 struct mlx5_ifc_pmpe_reg_bits pmpe_reg; 8791 struct mlx5_ifc_pmpr_reg_bits pmpr_reg; 8792 struct mlx5_ifc_pmtu_reg_bits pmtu_reg; 8793 struct mlx5_ifc_ppad_reg_bits ppad_reg; 8794 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg; 8795 struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg; 8796 struct mlx5_ifc_pplm_reg_bits pplm_reg; 8797 struct mlx5_ifc_pplr_reg_bits pplr_reg; 8798 struct mlx5_ifc_ppsc_reg_bits ppsc_reg; 8799 struct mlx5_ifc_pqdr_reg_bits pqdr_reg; 8800 struct mlx5_ifc_pspa_reg_bits pspa_reg; 8801 struct mlx5_ifc_ptas_reg_bits ptas_reg; 8802 struct mlx5_ifc_ptys_reg_bits ptys_reg; 8803 struct mlx5_ifc_mlcr_reg_bits mlcr_reg; 8804 struct mlx5_ifc_pude_reg_bits pude_reg; 8805 struct mlx5_ifc_pvlc_reg_bits pvlc_reg; 8806 struct mlx5_ifc_slrg_reg_bits slrg_reg; 8807 struct mlx5_ifc_sltp_reg_bits sltp_reg; 8808 struct mlx5_ifc_mtpps_reg_bits mtpps_reg; 8809 struct mlx5_ifc_mtppse_reg_bits mtppse_reg; 8810 struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg; 8811 struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits; 8812 struct mlx5_ifc_fpga_cap_bits fpga_cap_bits; 8813 struct mlx5_ifc_mcqi_reg_bits mcqi_reg; 8814 struct mlx5_ifc_mcc_reg_bits mcc_reg; 8815 struct mlx5_ifc_mcda_reg_bits mcda_reg; 8816 u8 reserved_at_0[0x60e0]; 8817 }; 8818 8819 union mlx5_ifc_debug_enhancements_document_bits { 8820 struct mlx5_ifc_health_buffer_bits health_buffer; 8821 u8 reserved_at_0[0x200]; 8822 }; 8823 8824 union mlx5_ifc_uplink_pci_interface_document_bits { 8825 struct mlx5_ifc_initial_seg_bits initial_seg; 8826 u8 reserved_at_0[0x20060]; 8827 }; 8828 8829 struct mlx5_ifc_set_flow_table_root_out_bits { 8830 u8 status[0x8]; 8831 u8 reserved_at_8[0x18]; 8832 8833 u8 syndrome[0x20]; 8834 8835 u8 reserved_at_40[0x40]; 8836 }; 8837 8838 struct mlx5_ifc_set_flow_table_root_in_bits { 8839 u8 opcode[0x10]; 8840 u8 reserved_at_10[0x10]; 8841 8842 u8 reserved_at_20[0x10]; 8843 u8 op_mod[0x10]; 8844 8845 u8 other_vport[0x1]; 8846 u8 reserved_at_41[0xf]; 8847 u8 vport_number[0x10]; 8848 8849 u8 reserved_at_60[0x20]; 8850 8851 u8 table_type[0x8]; 8852 u8 reserved_at_88[0x18]; 8853 8854 u8 reserved_at_a0[0x8]; 8855 u8 table_id[0x18]; 8856 8857 u8 reserved_at_c0[0x8]; 8858 u8 underlay_qpn[0x18]; 8859 u8 reserved_at_e0[0x120]; 8860 }; 8861 8862 enum { 8863 MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = (1UL << 0), 8864 MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15), 8865 }; 8866 8867 struct mlx5_ifc_modify_flow_table_out_bits { 8868 u8 status[0x8]; 8869 u8 reserved_at_8[0x18]; 8870 8871 u8 syndrome[0x20]; 8872 8873 u8 reserved_at_40[0x40]; 8874 }; 8875 8876 struct mlx5_ifc_modify_flow_table_in_bits { 8877 u8 opcode[0x10]; 8878 u8 reserved_at_10[0x10]; 8879 8880 u8 reserved_at_20[0x10]; 8881 u8 op_mod[0x10]; 8882 8883 u8 other_vport[0x1]; 8884 u8 reserved_at_41[0xf]; 8885 u8 vport_number[0x10]; 8886 8887 u8 reserved_at_60[0x10]; 8888 u8 modify_field_select[0x10]; 8889 8890 u8 table_type[0x8]; 8891 u8 reserved_at_88[0x18]; 8892 8893 u8 reserved_at_a0[0x8]; 8894 u8 table_id[0x18]; 8895 8896 struct mlx5_ifc_flow_table_context_bits flow_table_context; 8897 }; 8898 8899 struct mlx5_ifc_ets_tcn_config_reg_bits { 8900 u8 g[0x1]; 8901 u8 b[0x1]; 8902 u8 r[0x1]; 8903 u8 reserved_at_3[0x9]; 8904 u8 group[0x4]; 8905 u8 reserved_at_10[0x9]; 8906 u8 bw_allocation[0x7]; 8907 8908 u8 reserved_at_20[0xc]; 8909 u8 max_bw_units[0x4]; 8910 u8 reserved_at_30[0x8]; 8911 u8 max_bw_value[0x8]; 8912 }; 8913 8914 struct mlx5_ifc_ets_global_config_reg_bits { 8915 u8 reserved_at_0[0x2]; 8916 u8 r[0x1]; 8917 u8 reserved_at_3[0x1d]; 8918 8919 u8 reserved_at_20[0xc]; 8920 u8 max_bw_units[0x4]; 8921 u8 reserved_at_30[0x8]; 8922 u8 max_bw_value[0x8]; 8923 }; 8924 8925 struct mlx5_ifc_qetc_reg_bits { 8926 u8 reserved_at_0[0x8]; 8927 u8 port_number[0x8]; 8928 u8 reserved_at_10[0x30]; 8929 8930 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8]; 8931 struct mlx5_ifc_ets_global_config_reg_bits global_configuration; 8932 }; 8933 8934 struct mlx5_ifc_qpdpm_dscp_reg_bits { 8935 u8 e[0x1]; 8936 u8 reserved_at_01[0x0b]; 8937 u8 prio[0x04]; 8938 }; 8939 8940 struct mlx5_ifc_qpdpm_reg_bits { 8941 u8 reserved_at_0[0x8]; 8942 u8 local_port[0x8]; 8943 u8 reserved_at_10[0x10]; 8944 struct mlx5_ifc_qpdpm_dscp_reg_bits dscp[64]; 8945 }; 8946 8947 struct mlx5_ifc_qpts_reg_bits { 8948 u8 reserved_at_0[0x8]; 8949 u8 local_port[0x8]; 8950 u8 reserved_at_10[0x2d]; 8951 u8 trust_state[0x3]; 8952 }; 8953 8954 struct mlx5_ifc_pptb_reg_bits { 8955 u8 reserved_at_0[0x2]; 8956 u8 mm[0x2]; 8957 u8 reserved_at_4[0x4]; 8958 u8 local_port[0x8]; 8959 u8 reserved_at_10[0x6]; 8960 u8 cm[0x1]; 8961 u8 um[0x1]; 8962 u8 pm[0x8]; 8963 8964 u8 prio_x_buff[0x20]; 8965 8966 u8 pm_msb[0x8]; 8967 u8 reserved_at_48[0x10]; 8968 u8 ctrl_buff[0x4]; 8969 u8 untagged_buff[0x4]; 8970 }; 8971 8972 struct mlx5_ifc_pbmc_reg_bits { 8973 u8 reserved_at_0[0x8]; 8974 u8 local_port[0x8]; 8975 u8 reserved_at_10[0x10]; 8976 8977 u8 xoff_timer_value[0x10]; 8978 u8 xoff_refresh[0x10]; 8979 8980 u8 reserved_at_40[0x9]; 8981 u8 fullness_threshold[0x7]; 8982 u8 port_buffer_size[0x10]; 8983 8984 struct mlx5_ifc_bufferx_reg_bits buffer[10]; 8985 8986 u8 reserved_at_2e0[0x40]; 8987 }; 8988 8989 struct mlx5_ifc_qtct_reg_bits { 8990 u8 reserved_at_0[0x8]; 8991 u8 port_number[0x8]; 8992 u8 reserved_at_10[0xd]; 8993 u8 prio[0x3]; 8994 8995 u8 reserved_at_20[0x1d]; 8996 u8 tclass[0x3]; 8997 }; 8998 8999 struct mlx5_ifc_mcia_reg_bits { 9000 u8 l[0x1]; 9001 u8 reserved_at_1[0x7]; 9002 u8 module[0x8]; 9003 u8 reserved_at_10[0x8]; 9004 u8 status[0x8]; 9005 9006 u8 i2c_device_address[0x8]; 9007 u8 page_number[0x8]; 9008 u8 device_address[0x10]; 9009 9010 u8 reserved_at_40[0x10]; 9011 u8 size[0x10]; 9012 9013 u8 reserved_at_60[0x20]; 9014 9015 u8 dword_0[0x20]; 9016 u8 dword_1[0x20]; 9017 u8 dword_2[0x20]; 9018 u8 dword_3[0x20]; 9019 u8 dword_4[0x20]; 9020 u8 dword_5[0x20]; 9021 u8 dword_6[0x20]; 9022 u8 dword_7[0x20]; 9023 u8 dword_8[0x20]; 9024 u8 dword_9[0x20]; 9025 u8 dword_10[0x20]; 9026 u8 dword_11[0x20]; 9027 }; 9028 9029 struct mlx5_ifc_dcbx_param_bits { 9030 u8 dcbx_cee_cap[0x1]; 9031 u8 dcbx_ieee_cap[0x1]; 9032 u8 dcbx_standby_cap[0x1]; 9033 u8 reserved_at_0[0x5]; 9034 u8 port_number[0x8]; 9035 u8 reserved_at_10[0xa]; 9036 u8 max_application_table_size[6]; 9037 u8 reserved_at_20[0x15]; 9038 u8 version_oper[0x3]; 9039 u8 reserved_at_38[5]; 9040 u8 version_admin[0x3]; 9041 u8 willing_admin[0x1]; 9042 u8 reserved_at_41[0x3]; 9043 u8 pfc_cap_oper[0x4]; 9044 u8 reserved_at_48[0x4]; 9045 u8 pfc_cap_admin[0x4]; 9046 u8 reserved_at_50[0x4]; 9047 u8 num_of_tc_oper[0x4]; 9048 u8 reserved_at_58[0x4]; 9049 u8 num_of_tc_admin[0x4]; 9050 u8 remote_willing[0x1]; 9051 u8 reserved_at_61[3]; 9052 u8 remote_pfc_cap[4]; 9053 u8 reserved_at_68[0x14]; 9054 u8 remote_num_of_tc[0x4]; 9055 u8 reserved_at_80[0x18]; 9056 u8 error[0x8]; 9057 u8 reserved_at_a0[0x160]; 9058 }; 9059 9060 struct mlx5_ifc_lagc_bits { 9061 u8 reserved_at_0[0x1d]; 9062 u8 lag_state[0x3]; 9063 9064 u8 reserved_at_20[0x14]; 9065 u8 tx_remap_affinity_2[0x4]; 9066 u8 reserved_at_38[0x4]; 9067 u8 tx_remap_affinity_1[0x4]; 9068 }; 9069 9070 struct mlx5_ifc_create_lag_out_bits { 9071 u8 status[0x8]; 9072 u8 reserved_at_8[0x18]; 9073 9074 u8 syndrome[0x20]; 9075 9076 u8 reserved_at_40[0x40]; 9077 }; 9078 9079 struct mlx5_ifc_create_lag_in_bits { 9080 u8 opcode[0x10]; 9081 u8 reserved_at_10[0x10]; 9082 9083 u8 reserved_at_20[0x10]; 9084 u8 op_mod[0x10]; 9085 9086 struct mlx5_ifc_lagc_bits ctx; 9087 }; 9088 9089 struct mlx5_ifc_modify_lag_out_bits { 9090 u8 status[0x8]; 9091 u8 reserved_at_8[0x18]; 9092 9093 u8 syndrome[0x20]; 9094 9095 u8 reserved_at_40[0x40]; 9096 }; 9097 9098 struct mlx5_ifc_modify_lag_in_bits { 9099 u8 opcode[0x10]; 9100 u8 reserved_at_10[0x10]; 9101 9102 u8 reserved_at_20[0x10]; 9103 u8 op_mod[0x10]; 9104 9105 u8 reserved_at_40[0x20]; 9106 u8 field_select[0x20]; 9107 9108 struct mlx5_ifc_lagc_bits ctx; 9109 }; 9110 9111 struct mlx5_ifc_query_lag_out_bits { 9112 u8 status[0x8]; 9113 u8 reserved_at_8[0x18]; 9114 9115 u8 syndrome[0x20]; 9116 9117 u8 reserved_at_40[0x40]; 9118 9119 struct mlx5_ifc_lagc_bits ctx; 9120 }; 9121 9122 struct mlx5_ifc_query_lag_in_bits { 9123 u8 opcode[0x10]; 9124 u8 reserved_at_10[0x10]; 9125 9126 u8 reserved_at_20[0x10]; 9127 u8 op_mod[0x10]; 9128 9129 u8 reserved_at_40[0x40]; 9130 }; 9131 9132 struct mlx5_ifc_destroy_lag_out_bits { 9133 u8 status[0x8]; 9134 u8 reserved_at_8[0x18]; 9135 9136 u8 syndrome[0x20]; 9137 9138 u8 reserved_at_40[0x40]; 9139 }; 9140 9141 struct mlx5_ifc_destroy_lag_in_bits { 9142 u8 opcode[0x10]; 9143 u8 reserved_at_10[0x10]; 9144 9145 u8 reserved_at_20[0x10]; 9146 u8 op_mod[0x10]; 9147 9148 u8 reserved_at_40[0x40]; 9149 }; 9150 9151 struct mlx5_ifc_create_vport_lag_out_bits { 9152 u8 status[0x8]; 9153 u8 reserved_at_8[0x18]; 9154 9155 u8 syndrome[0x20]; 9156 9157 u8 reserved_at_40[0x40]; 9158 }; 9159 9160 struct mlx5_ifc_create_vport_lag_in_bits { 9161 u8 opcode[0x10]; 9162 u8 reserved_at_10[0x10]; 9163 9164 u8 reserved_at_20[0x10]; 9165 u8 op_mod[0x10]; 9166 9167 u8 reserved_at_40[0x40]; 9168 }; 9169 9170 struct mlx5_ifc_destroy_vport_lag_out_bits { 9171 u8 status[0x8]; 9172 u8 reserved_at_8[0x18]; 9173 9174 u8 syndrome[0x20]; 9175 9176 u8 reserved_at_40[0x40]; 9177 }; 9178 9179 struct mlx5_ifc_destroy_vport_lag_in_bits { 9180 u8 opcode[0x10]; 9181 u8 reserved_at_10[0x10]; 9182 9183 u8 reserved_at_20[0x10]; 9184 u8 op_mod[0x10]; 9185 9186 u8 reserved_at_40[0x40]; 9187 }; 9188 9189 struct mlx5_ifc_alloc_memic_in_bits { 9190 u8 opcode[0x10]; 9191 u8 reserved_at_10[0x10]; 9192 9193 u8 reserved_at_20[0x10]; 9194 u8 op_mod[0x10]; 9195 9196 u8 reserved_at_30[0x20]; 9197 9198 u8 reserved_at_40[0x18]; 9199 u8 log_memic_addr_alignment[0x8]; 9200 9201 u8 range_start_addr[0x40]; 9202 9203 u8 range_size[0x20]; 9204 9205 u8 memic_size[0x20]; 9206 }; 9207 9208 struct mlx5_ifc_alloc_memic_out_bits { 9209 u8 status[0x8]; 9210 u8 reserved_at_8[0x18]; 9211 9212 u8 syndrome[0x20]; 9213 9214 u8 memic_start_addr[0x40]; 9215 }; 9216 9217 struct mlx5_ifc_dealloc_memic_in_bits { 9218 u8 opcode[0x10]; 9219 u8 reserved_at_10[0x10]; 9220 9221 u8 reserved_at_20[0x10]; 9222 u8 op_mod[0x10]; 9223 9224 u8 reserved_at_40[0x40]; 9225 9226 u8 memic_start_addr[0x40]; 9227 9228 u8 memic_size[0x20]; 9229 9230 u8 reserved_at_e0[0x20]; 9231 }; 9232 9233 struct mlx5_ifc_dealloc_memic_out_bits { 9234 u8 status[0x8]; 9235 u8 reserved_at_8[0x18]; 9236 9237 u8 syndrome[0x20]; 9238 9239 u8 reserved_at_40[0x40]; 9240 }; 9241 9242 struct mlx5_ifc_general_obj_in_cmd_hdr_bits { 9243 u8 opcode[0x10]; 9244 u8 uid[0x10]; 9245 9246 u8 reserved_at_20[0x10]; 9247 u8 obj_type[0x10]; 9248 9249 u8 obj_id[0x20]; 9250 9251 u8 reserved_at_60[0x20]; 9252 }; 9253 9254 struct mlx5_ifc_general_obj_out_cmd_hdr_bits { 9255 u8 status[0x8]; 9256 u8 reserved_at_8[0x18]; 9257 9258 u8 syndrome[0x20]; 9259 9260 u8 obj_id[0x20]; 9261 9262 u8 reserved_at_60[0x20]; 9263 }; 9264 9265 struct mlx5_ifc_umem_bits { 9266 u8 modify_field_select[0x40]; 9267 9268 u8 reserved_at_40[0x5b]; 9269 u8 log_page_size[0x5]; 9270 9271 u8 page_offset[0x20]; 9272 9273 u8 num_of_mtt[0x40]; 9274 9275 struct mlx5_ifc_mtt_bits mtt[0]; 9276 }; 9277 9278 struct mlx5_ifc_uctx_bits { 9279 u8 modify_field_select[0x40]; 9280 9281 u8 reserved_at_40[0x1c0]; 9282 }; 9283 9284 struct mlx5_ifc_create_umem_in_bits { 9285 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 9286 struct mlx5_ifc_umem_bits umem; 9287 }; 9288 9289 struct mlx5_ifc_create_uctx_in_bits { 9290 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 9291 struct mlx5_ifc_uctx_bits uctx; 9292 }; 9293 9294 struct mlx5_ifc_mtrc_string_db_param_bits { 9295 u8 string_db_base_address[0x20]; 9296 9297 u8 reserved_at_20[0x8]; 9298 u8 string_db_size[0x18]; 9299 }; 9300 9301 struct mlx5_ifc_mtrc_cap_bits { 9302 u8 trace_owner[0x1]; 9303 u8 trace_to_memory[0x1]; 9304 u8 reserved_at_2[0x4]; 9305 u8 trc_ver[0x2]; 9306 u8 reserved_at_8[0x14]; 9307 u8 num_string_db[0x4]; 9308 9309 u8 first_string_trace[0x8]; 9310 u8 num_string_trace[0x8]; 9311 u8 reserved_at_30[0x28]; 9312 9313 u8 log_max_trace_buffer_size[0x8]; 9314 9315 u8 reserved_at_60[0x20]; 9316 9317 struct mlx5_ifc_mtrc_string_db_param_bits string_db_param[8]; 9318 9319 u8 reserved_at_280[0x180]; 9320 }; 9321 9322 struct mlx5_ifc_mtrc_conf_bits { 9323 u8 reserved_at_0[0x1c]; 9324 u8 trace_mode[0x4]; 9325 u8 reserved_at_20[0x18]; 9326 u8 log_trace_buffer_size[0x8]; 9327 u8 trace_mkey[0x20]; 9328 u8 reserved_at_60[0x3a0]; 9329 }; 9330 9331 struct mlx5_ifc_mtrc_stdb_bits { 9332 u8 string_db_index[0x4]; 9333 u8 reserved_at_4[0x4]; 9334 u8 read_size[0x18]; 9335 u8 start_offset[0x20]; 9336 u8 string_db_data[0]; 9337 }; 9338 9339 struct mlx5_ifc_mtrc_ctrl_bits { 9340 u8 trace_status[0x2]; 9341 u8 reserved_at_2[0x2]; 9342 u8 arm_event[0x1]; 9343 u8 reserved_at_5[0xb]; 9344 u8 modify_field_select[0x10]; 9345 u8 reserved_at_20[0x2b]; 9346 u8 current_timestamp52_32[0x15]; 9347 u8 current_timestamp31_0[0x20]; 9348 u8 reserved_at_80[0x180]; 9349 }; 9350 9351 #endif /* MLX5_IFC_H */ 9352