1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 #ifndef MLX5_IFC_H 33 #define MLX5_IFC_H 34 35 #include "mlx5_ifc_fpga.h" 36 37 enum { 38 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0, 39 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1, 40 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2, 41 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3, 42 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13, 43 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14, 44 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c, 45 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d, 46 MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4, 47 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5, 48 MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED = 0x7, 49 MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT = 0xc, 50 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10, 51 MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR = 0x11, 52 MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR = 0x12, 53 MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR = 0x8, 54 MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE = 0x9, 55 MLX5_EVENT_TYPE_CODING_GPIO_EVENT = 0x15, 56 MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19, 57 MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a, 58 MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT = 0x1b, 59 MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT = 0x1f, 60 MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa, 61 MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb, 62 MLX5_EVENT_TYPE_CODING_FPGA_ERROR = 0x20, 63 MLX5_EVENT_TYPE_CODING_FPGA_QP_ERROR = 0x21 64 }; 65 66 enum { 67 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0, 68 MLX5_SET_HCA_CAP_OP_MOD_ETHERNET_OFFLOADS = 0x1, 69 MLX5_SET_HCA_CAP_OP_MOD_ODP = 0x2, 70 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3, 71 MLX5_SET_HCA_CAP_OP_MOD_ROCE = 0x4, 72 MLX5_SET_HCA_CAP_OP_MOD_IPSEC = 0x15, 73 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE2 = 0x20, 74 MLX5_SET_HCA_CAP_OP_MOD_PORT_SELECTION = 0x25, 75 }; 76 77 enum { 78 MLX5_SHARED_RESOURCE_UID = 0xffff, 79 }; 80 81 enum { 82 MLX5_OBJ_TYPE_SW_ICM = 0x0008, 83 MLX5_OBJ_TYPE_HEADER_MODIFY_ARGUMENT = 0x23, 84 }; 85 86 enum { 87 MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM = (1ULL << MLX5_OBJ_TYPE_SW_ICM), 88 MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT = (1ULL << 11), 89 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q = (1ULL << 13), 90 MLX5_GENERAL_OBJ_TYPES_CAP_HEADER_MODIFY_ARGUMENT = 91 (1ULL << MLX5_OBJ_TYPE_HEADER_MODIFY_ARGUMENT), 92 MLX5_GENERAL_OBJ_TYPES_CAP_MACSEC_OFFLOAD = (1ULL << 39), 93 }; 94 95 enum { 96 MLX5_OBJ_TYPE_GENEVE_TLV_OPT = 0x000b, 97 MLX5_OBJ_TYPE_VIRTIO_NET_Q = 0x000d, 98 MLX5_OBJ_TYPE_VIRTIO_Q_COUNTERS = 0x001c, 99 MLX5_OBJ_TYPE_MATCH_DEFINER = 0x0018, 100 MLX5_OBJ_TYPE_PAGE_TRACK = 0x46, 101 MLX5_OBJ_TYPE_MKEY = 0xff01, 102 MLX5_OBJ_TYPE_QP = 0xff02, 103 MLX5_OBJ_TYPE_PSV = 0xff03, 104 MLX5_OBJ_TYPE_RMP = 0xff04, 105 MLX5_OBJ_TYPE_XRC_SRQ = 0xff05, 106 MLX5_OBJ_TYPE_RQ = 0xff06, 107 MLX5_OBJ_TYPE_SQ = 0xff07, 108 MLX5_OBJ_TYPE_TIR = 0xff08, 109 MLX5_OBJ_TYPE_TIS = 0xff09, 110 MLX5_OBJ_TYPE_DCT = 0xff0a, 111 MLX5_OBJ_TYPE_XRQ = 0xff0b, 112 MLX5_OBJ_TYPE_RQT = 0xff0e, 113 MLX5_OBJ_TYPE_FLOW_COUNTER = 0xff0f, 114 MLX5_OBJ_TYPE_CQ = 0xff10, 115 }; 116 117 enum { 118 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100, 119 MLX5_CMD_OP_QUERY_ADAPTER = 0x101, 120 MLX5_CMD_OP_INIT_HCA = 0x102, 121 MLX5_CMD_OP_TEARDOWN_HCA = 0x103, 122 MLX5_CMD_OP_ENABLE_HCA = 0x104, 123 MLX5_CMD_OP_DISABLE_HCA = 0x105, 124 MLX5_CMD_OP_QUERY_PAGES = 0x107, 125 MLX5_CMD_OP_MANAGE_PAGES = 0x108, 126 MLX5_CMD_OP_SET_HCA_CAP = 0x109, 127 MLX5_CMD_OP_QUERY_ISSI = 0x10a, 128 MLX5_CMD_OP_SET_ISSI = 0x10b, 129 MLX5_CMD_OP_SET_DRIVER_VERSION = 0x10d, 130 MLX5_CMD_OP_QUERY_SF_PARTITION = 0x111, 131 MLX5_CMD_OP_ALLOC_SF = 0x113, 132 MLX5_CMD_OP_DEALLOC_SF = 0x114, 133 MLX5_CMD_OP_SUSPEND_VHCA = 0x115, 134 MLX5_CMD_OP_RESUME_VHCA = 0x116, 135 MLX5_CMD_OP_QUERY_VHCA_MIGRATION_STATE = 0x117, 136 MLX5_CMD_OP_SAVE_VHCA_STATE = 0x118, 137 MLX5_CMD_OP_LOAD_VHCA_STATE = 0x119, 138 MLX5_CMD_OP_CREATE_MKEY = 0x200, 139 MLX5_CMD_OP_QUERY_MKEY = 0x201, 140 MLX5_CMD_OP_DESTROY_MKEY = 0x202, 141 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203, 142 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204, 143 MLX5_CMD_OP_ALLOC_MEMIC = 0x205, 144 MLX5_CMD_OP_DEALLOC_MEMIC = 0x206, 145 MLX5_CMD_OP_MODIFY_MEMIC = 0x207, 146 MLX5_CMD_OP_CREATE_EQ = 0x301, 147 MLX5_CMD_OP_DESTROY_EQ = 0x302, 148 MLX5_CMD_OP_QUERY_EQ = 0x303, 149 MLX5_CMD_OP_GEN_EQE = 0x304, 150 MLX5_CMD_OP_CREATE_CQ = 0x400, 151 MLX5_CMD_OP_DESTROY_CQ = 0x401, 152 MLX5_CMD_OP_QUERY_CQ = 0x402, 153 MLX5_CMD_OP_MODIFY_CQ = 0x403, 154 MLX5_CMD_OP_CREATE_QP = 0x500, 155 MLX5_CMD_OP_DESTROY_QP = 0x501, 156 MLX5_CMD_OP_RST2INIT_QP = 0x502, 157 MLX5_CMD_OP_INIT2RTR_QP = 0x503, 158 MLX5_CMD_OP_RTR2RTS_QP = 0x504, 159 MLX5_CMD_OP_RTS2RTS_QP = 0x505, 160 MLX5_CMD_OP_SQERR2RTS_QP = 0x506, 161 MLX5_CMD_OP_2ERR_QP = 0x507, 162 MLX5_CMD_OP_2RST_QP = 0x50a, 163 MLX5_CMD_OP_QUERY_QP = 0x50b, 164 MLX5_CMD_OP_SQD_RTS_QP = 0x50c, 165 MLX5_CMD_OP_INIT2INIT_QP = 0x50e, 166 MLX5_CMD_OP_CREATE_PSV = 0x600, 167 MLX5_CMD_OP_DESTROY_PSV = 0x601, 168 MLX5_CMD_OP_CREATE_SRQ = 0x700, 169 MLX5_CMD_OP_DESTROY_SRQ = 0x701, 170 MLX5_CMD_OP_QUERY_SRQ = 0x702, 171 MLX5_CMD_OP_ARM_RQ = 0x703, 172 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705, 173 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706, 174 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707, 175 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708, 176 MLX5_CMD_OP_CREATE_DCT = 0x710, 177 MLX5_CMD_OP_DESTROY_DCT = 0x711, 178 MLX5_CMD_OP_DRAIN_DCT = 0x712, 179 MLX5_CMD_OP_QUERY_DCT = 0x713, 180 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714, 181 MLX5_CMD_OP_CREATE_XRQ = 0x717, 182 MLX5_CMD_OP_DESTROY_XRQ = 0x718, 183 MLX5_CMD_OP_QUERY_XRQ = 0x719, 184 MLX5_CMD_OP_ARM_XRQ = 0x71a, 185 MLX5_CMD_OP_QUERY_XRQ_DC_PARAMS_ENTRY = 0x725, 186 MLX5_CMD_OP_SET_XRQ_DC_PARAMS_ENTRY = 0x726, 187 MLX5_CMD_OP_QUERY_XRQ_ERROR_PARAMS = 0x727, 188 MLX5_CMD_OP_RELEASE_XRQ_ERROR = 0x729, 189 MLX5_CMD_OP_MODIFY_XRQ = 0x72a, 190 MLX5_CMD_OP_QUERY_ESW_FUNCTIONS = 0x740, 191 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750, 192 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751, 193 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752, 194 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753, 195 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754, 196 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755, 197 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760, 198 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761, 199 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762, 200 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763, 201 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764, 202 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765, 203 MLX5_CMD_OP_QUERY_VNIC_ENV = 0x76f, 204 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770, 205 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771, 206 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772, 207 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773, 208 MLX5_CMD_OP_SET_MONITOR_COUNTER = 0x774, 209 MLX5_CMD_OP_ARM_MONITOR_COUNTER = 0x775, 210 MLX5_CMD_OP_SET_PP_RATE_LIMIT = 0x780, 211 MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781, 212 MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT = 0x782, 213 MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT = 0x783, 214 MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT = 0x784, 215 MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT = 0x785, 216 MLX5_CMD_OP_CREATE_QOS_PARA_VPORT = 0x786, 217 MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT = 0x787, 218 MLX5_CMD_OP_ALLOC_PD = 0x800, 219 MLX5_CMD_OP_DEALLOC_PD = 0x801, 220 MLX5_CMD_OP_ALLOC_UAR = 0x802, 221 MLX5_CMD_OP_DEALLOC_UAR = 0x803, 222 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804, 223 MLX5_CMD_OP_ACCESS_REG = 0x805, 224 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806, 225 MLX5_CMD_OP_DETACH_FROM_MCG = 0x807, 226 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a, 227 MLX5_CMD_OP_MAD_IFC = 0x50d, 228 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b, 229 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c, 230 MLX5_CMD_OP_NOP = 0x80d, 231 MLX5_CMD_OP_ALLOC_XRCD = 0x80e, 232 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f, 233 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816, 234 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817, 235 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822, 236 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823, 237 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824, 238 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825, 239 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826, 240 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827, 241 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828, 242 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829, 243 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a, 244 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b, 245 MLX5_CMD_OP_SET_WOL_ROL = 0x830, 246 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831, 247 MLX5_CMD_OP_CREATE_LAG = 0x840, 248 MLX5_CMD_OP_MODIFY_LAG = 0x841, 249 MLX5_CMD_OP_QUERY_LAG = 0x842, 250 MLX5_CMD_OP_DESTROY_LAG = 0x843, 251 MLX5_CMD_OP_CREATE_VPORT_LAG = 0x844, 252 MLX5_CMD_OP_DESTROY_VPORT_LAG = 0x845, 253 MLX5_CMD_OP_CREATE_TIR = 0x900, 254 MLX5_CMD_OP_MODIFY_TIR = 0x901, 255 MLX5_CMD_OP_DESTROY_TIR = 0x902, 256 MLX5_CMD_OP_QUERY_TIR = 0x903, 257 MLX5_CMD_OP_CREATE_SQ = 0x904, 258 MLX5_CMD_OP_MODIFY_SQ = 0x905, 259 MLX5_CMD_OP_DESTROY_SQ = 0x906, 260 MLX5_CMD_OP_QUERY_SQ = 0x907, 261 MLX5_CMD_OP_CREATE_RQ = 0x908, 262 MLX5_CMD_OP_MODIFY_RQ = 0x909, 263 MLX5_CMD_OP_SET_DELAY_DROP_PARAMS = 0x910, 264 MLX5_CMD_OP_DESTROY_RQ = 0x90a, 265 MLX5_CMD_OP_QUERY_RQ = 0x90b, 266 MLX5_CMD_OP_CREATE_RMP = 0x90c, 267 MLX5_CMD_OP_MODIFY_RMP = 0x90d, 268 MLX5_CMD_OP_DESTROY_RMP = 0x90e, 269 MLX5_CMD_OP_QUERY_RMP = 0x90f, 270 MLX5_CMD_OP_CREATE_TIS = 0x912, 271 MLX5_CMD_OP_MODIFY_TIS = 0x913, 272 MLX5_CMD_OP_DESTROY_TIS = 0x914, 273 MLX5_CMD_OP_QUERY_TIS = 0x915, 274 MLX5_CMD_OP_CREATE_RQT = 0x916, 275 MLX5_CMD_OP_MODIFY_RQT = 0x917, 276 MLX5_CMD_OP_DESTROY_RQT = 0x918, 277 MLX5_CMD_OP_QUERY_RQT = 0x919, 278 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f, 279 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930, 280 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931, 281 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932, 282 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933, 283 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934, 284 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935, 285 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936, 286 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937, 287 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938, 288 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939, 289 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a, 290 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b, 291 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c, 292 MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT = 0x93d, 293 MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT = 0x93e, 294 MLX5_CMD_OP_QUERY_PACKET_REFORMAT_CONTEXT = 0x93f, 295 MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT = 0x940, 296 MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941, 297 MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT = 0x942, 298 MLX5_CMD_OP_FPGA_CREATE_QP = 0x960, 299 MLX5_CMD_OP_FPGA_MODIFY_QP = 0x961, 300 MLX5_CMD_OP_FPGA_QUERY_QP = 0x962, 301 MLX5_CMD_OP_FPGA_DESTROY_QP = 0x963, 302 MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS = 0x964, 303 MLX5_CMD_OP_CREATE_GENERAL_OBJECT = 0xa00, 304 MLX5_CMD_OP_MODIFY_GENERAL_OBJECT = 0xa01, 305 MLX5_CMD_OP_QUERY_GENERAL_OBJECT = 0xa02, 306 MLX5_CMD_OP_DESTROY_GENERAL_OBJECT = 0xa03, 307 MLX5_CMD_OP_CREATE_UCTX = 0xa04, 308 MLX5_CMD_OP_DESTROY_UCTX = 0xa06, 309 MLX5_CMD_OP_CREATE_UMEM = 0xa08, 310 MLX5_CMD_OP_DESTROY_UMEM = 0xa0a, 311 MLX5_CMD_OP_SYNC_STEERING = 0xb00, 312 MLX5_CMD_OP_QUERY_VHCA_STATE = 0xb0d, 313 MLX5_CMD_OP_MODIFY_VHCA_STATE = 0xb0e, 314 MLX5_CMD_OP_SYNC_CRYPTO = 0xb12, 315 MLX5_CMD_OP_ALLOW_OTHER_VHCA_ACCESS = 0xb16, 316 MLX5_CMD_OP_MAX 317 }; 318 319 /* Valid range for general commands that don't work over an object */ 320 enum { 321 MLX5_CMD_OP_GENERAL_START = 0xb00, 322 MLX5_CMD_OP_GENERAL_END = 0xd00, 323 }; 324 325 enum { 326 MLX5_FT_NIC_RX_2_NIC_RX_RDMA = BIT(0), 327 MLX5_FT_NIC_TX_RDMA_2_NIC_TX = BIT(1), 328 }; 329 330 enum { 331 MLX5_CMD_OP_MOD_UPDATE_HEADER_MODIFY_ARGUMENT = 0x1, 332 }; 333 334 struct mlx5_ifc_flow_table_fields_supported_bits { 335 u8 outer_dmac[0x1]; 336 u8 outer_smac[0x1]; 337 u8 outer_ether_type[0x1]; 338 u8 outer_ip_version[0x1]; 339 u8 outer_first_prio[0x1]; 340 u8 outer_first_cfi[0x1]; 341 u8 outer_first_vid[0x1]; 342 u8 outer_ipv4_ttl[0x1]; 343 u8 outer_second_prio[0x1]; 344 u8 outer_second_cfi[0x1]; 345 u8 outer_second_vid[0x1]; 346 u8 reserved_at_b[0x1]; 347 u8 outer_sip[0x1]; 348 u8 outer_dip[0x1]; 349 u8 outer_frag[0x1]; 350 u8 outer_ip_protocol[0x1]; 351 u8 outer_ip_ecn[0x1]; 352 u8 outer_ip_dscp[0x1]; 353 u8 outer_udp_sport[0x1]; 354 u8 outer_udp_dport[0x1]; 355 u8 outer_tcp_sport[0x1]; 356 u8 outer_tcp_dport[0x1]; 357 u8 outer_tcp_flags[0x1]; 358 u8 outer_gre_protocol[0x1]; 359 u8 outer_gre_key[0x1]; 360 u8 outer_vxlan_vni[0x1]; 361 u8 outer_geneve_vni[0x1]; 362 u8 outer_geneve_oam[0x1]; 363 u8 outer_geneve_protocol_type[0x1]; 364 u8 outer_geneve_opt_len[0x1]; 365 u8 source_vhca_port[0x1]; 366 u8 source_eswitch_port[0x1]; 367 368 u8 inner_dmac[0x1]; 369 u8 inner_smac[0x1]; 370 u8 inner_ether_type[0x1]; 371 u8 inner_ip_version[0x1]; 372 u8 inner_first_prio[0x1]; 373 u8 inner_first_cfi[0x1]; 374 u8 inner_first_vid[0x1]; 375 u8 reserved_at_27[0x1]; 376 u8 inner_second_prio[0x1]; 377 u8 inner_second_cfi[0x1]; 378 u8 inner_second_vid[0x1]; 379 u8 reserved_at_2b[0x1]; 380 u8 inner_sip[0x1]; 381 u8 inner_dip[0x1]; 382 u8 inner_frag[0x1]; 383 u8 inner_ip_protocol[0x1]; 384 u8 inner_ip_ecn[0x1]; 385 u8 inner_ip_dscp[0x1]; 386 u8 inner_udp_sport[0x1]; 387 u8 inner_udp_dport[0x1]; 388 u8 inner_tcp_sport[0x1]; 389 u8 inner_tcp_dport[0x1]; 390 u8 inner_tcp_flags[0x1]; 391 u8 reserved_at_37[0x9]; 392 393 u8 geneve_tlv_option_0_data[0x1]; 394 u8 geneve_tlv_option_0_exist[0x1]; 395 u8 reserved_at_42[0x3]; 396 u8 outer_first_mpls_over_udp[0x4]; 397 u8 outer_first_mpls_over_gre[0x4]; 398 u8 inner_first_mpls[0x4]; 399 u8 outer_first_mpls[0x4]; 400 u8 reserved_at_55[0x2]; 401 u8 outer_esp_spi[0x1]; 402 u8 reserved_at_58[0x2]; 403 u8 bth_dst_qp[0x1]; 404 u8 reserved_at_5b[0x5]; 405 406 u8 reserved_at_60[0x18]; 407 u8 metadata_reg_c_7[0x1]; 408 u8 metadata_reg_c_6[0x1]; 409 u8 metadata_reg_c_5[0x1]; 410 u8 metadata_reg_c_4[0x1]; 411 u8 metadata_reg_c_3[0x1]; 412 u8 metadata_reg_c_2[0x1]; 413 u8 metadata_reg_c_1[0x1]; 414 u8 metadata_reg_c_0[0x1]; 415 }; 416 417 /* Table 2170 - Flow Table Fields Supported 2 Format */ 418 struct mlx5_ifc_flow_table_fields_supported_2_bits { 419 u8 reserved_at_0[0x2]; 420 u8 inner_l4_type[0x1]; 421 u8 outer_l4_type[0x1]; 422 u8 reserved_at_4[0xa]; 423 u8 bth_opcode[0x1]; 424 u8 reserved_at_f[0x1]; 425 u8 tunnel_header_0_1[0x1]; 426 u8 reserved_at_11[0xf]; 427 428 u8 reserved_at_20[0x60]; 429 }; 430 431 struct mlx5_ifc_flow_table_prop_layout_bits { 432 u8 ft_support[0x1]; 433 u8 reserved_at_1[0x1]; 434 u8 flow_counter[0x1]; 435 u8 flow_modify_en[0x1]; 436 u8 modify_root[0x1]; 437 u8 identified_miss_table_mode[0x1]; 438 u8 flow_table_modify[0x1]; 439 u8 reformat[0x1]; 440 u8 decap[0x1]; 441 u8 reset_root_to_default[0x1]; 442 u8 pop_vlan[0x1]; 443 u8 push_vlan[0x1]; 444 u8 reserved_at_c[0x1]; 445 u8 pop_vlan_2[0x1]; 446 u8 push_vlan_2[0x1]; 447 u8 reformat_and_vlan_action[0x1]; 448 u8 reserved_at_10[0x1]; 449 u8 sw_owner[0x1]; 450 u8 reformat_l3_tunnel_to_l2[0x1]; 451 u8 reformat_l2_to_l3_tunnel[0x1]; 452 u8 reformat_and_modify_action[0x1]; 453 u8 ignore_flow_level[0x1]; 454 u8 reserved_at_16[0x1]; 455 u8 table_miss_action_domain[0x1]; 456 u8 termination_table[0x1]; 457 u8 reformat_and_fwd_to_table[0x1]; 458 u8 reserved_at_1a[0x2]; 459 u8 ipsec_encrypt[0x1]; 460 u8 ipsec_decrypt[0x1]; 461 u8 sw_owner_v2[0x1]; 462 u8 reserved_at_1f[0x1]; 463 464 u8 termination_table_raw_traffic[0x1]; 465 u8 reserved_at_21[0x1]; 466 u8 log_max_ft_size[0x6]; 467 u8 log_max_modify_header_context[0x8]; 468 u8 max_modify_header_actions[0x8]; 469 u8 max_ft_level[0x8]; 470 471 u8 reformat_add_esp_trasport[0x1]; 472 u8 reformat_l2_to_l3_esp_tunnel[0x1]; 473 u8 reformat_add_esp_transport_over_udp[0x1]; 474 u8 reformat_del_esp_trasport[0x1]; 475 u8 reformat_l3_esp_tunnel_to_l2[0x1]; 476 u8 reformat_del_esp_transport_over_udp[0x1]; 477 u8 execute_aso[0x1]; 478 u8 reserved_at_47[0x19]; 479 480 u8 reserved_at_60[0x2]; 481 u8 reformat_insert[0x1]; 482 u8 reformat_remove[0x1]; 483 u8 macsec_encrypt[0x1]; 484 u8 macsec_decrypt[0x1]; 485 u8 reserved_at_66[0x2]; 486 u8 reformat_add_macsec[0x1]; 487 u8 reformat_remove_macsec[0x1]; 488 u8 reserved_at_6a[0xe]; 489 u8 log_max_ft_num[0x8]; 490 491 u8 reserved_at_80[0x10]; 492 u8 log_max_flow_counter[0x8]; 493 u8 log_max_destination[0x8]; 494 495 u8 reserved_at_a0[0x18]; 496 u8 log_max_flow[0x8]; 497 498 u8 reserved_at_c0[0x40]; 499 500 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support; 501 502 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support; 503 }; 504 505 struct mlx5_ifc_odp_per_transport_service_cap_bits { 506 u8 send[0x1]; 507 u8 receive[0x1]; 508 u8 write[0x1]; 509 u8 read[0x1]; 510 u8 atomic[0x1]; 511 u8 srq_receive[0x1]; 512 u8 reserved_at_6[0x1a]; 513 }; 514 515 struct mlx5_ifc_ipv4_layout_bits { 516 u8 reserved_at_0[0x60]; 517 518 u8 ipv4[0x20]; 519 }; 520 521 struct mlx5_ifc_ipv6_layout_bits { 522 u8 ipv6[16][0x8]; 523 }; 524 525 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits { 526 struct mlx5_ifc_ipv6_layout_bits ipv6_layout; 527 struct mlx5_ifc_ipv4_layout_bits ipv4_layout; 528 u8 reserved_at_0[0x80]; 529 }; 530 531 enum { 532 MLX5_PACKET_L4_TYPE_NONE, 533 MLX5_PACKET_L4_TYPE_TCP, 534 MLX5_PACKET_L4_TYPE_UDP, 535 }; 536 537 struct mlx5_ifc_fte_match_set_lyr_2_4_bits { 538 u8 smac_47_16[0x20]; 539 540 u8 smac_15_0[0x10]; 541 u8 ethertype[0x10]; 542 543 u8 dmac_47_16[0x20]; 544 545 u8 dmac_15_0[0x10]; 546 u8 first_prio[0x3]; 547 u8 first_cfi[0x1]; 548 u8 first_vid[0xc]; 549 550 u8 ip_protocol[0x8]; 551 u8 ip_dscp[0x6]; 552 u8 ip_ecn[0x2]; 553 u8 cvlan_tag[0x1]; 554 u8 svlan_tag[0x1]; 555 u8 frag[0x1]; 556 u8 ip_version[0x4]; 557 u8 tcp_flags[0x9]; 558 559 u8 tcp_sport[0x10]; 560 u8 tcp_dport[0x10]; 561 562 u8 l4_type[0x2]; 563 u8 reserved_at_c2[0xe]; 564 u8 ipv4_ihl[0x4]; 565 u8 reserved_at_c4[0x4]; 566 567 u8 ttl_hoplimit[0x8]; 568 569 u8 udp_sport[0x10]; 570 u8 udp_dport[0x10]; 571 572 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6; 573 574 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6; 575 }; 576 577 struct mlx5_ifc_nvgre_key_bits { 578 u8 hi[0x18]; 579 u8 lo[0x8]; 580 }; 581 582 union mlx5_ifc_gre_key_bits { 583 struct mlx5_ifc_nvgre_key_bits nvgre; 584 u8 key[0x20]; 585 }; 586 587 struct mlx5_ifc_fte_match_set_misc_bits { 588 u8 gre_c_present[0x1]; 589 u8 reserved_at_1[0x1]; 590 u8 gre_k_present[0x1]; 591 u8 gre_s_present[0x1]; 592 u8 source_vhca_port[0x4]; 593 u8 source_sqn[0x18]; 594 595 u8 source_eswitch_owner_vhca_id[0x10]; 596 u8 source_port[0x10]; 597 598 u8 outer_second_prio[0x3]; 599 u8 outer_second_cfi[0x1]; 600 u8 outer_second_vid[0xc]; 601 u8 inner_second_prio[0x3]; 602 u8 inner_second_cfi[0x1]; 603 u8 inner_second_vid[0xc]; 604 605 u8 outer_second_cvlan_tag[0x1]; 606 u8 inner_second_cvlan_tag[0x1]; 607 u8 outer_second_svlan_tag[0x1]; 608 u8 inner_second_svlan_tag[0x1]; 609 u8 reserved_at_64[0xc]; 610 u8 gre_protocol[0x10]; 611 612 union mlx5_ifc_gre_key_bits gre_key; 613 614 u8 vxlan_vni[0x18]; 615 u8 bth_opcode[0x8]; 616 617 u8 geneve_vni[0x18]; 618 u8 reserved_at_d8[0x6]; 619 u8 geneve_tlv_option_0_exist[0x1]; 620 u8 geneve_oam[0x1]; 621 622 u8 reserved_at_e0[0xc]; 623 u8 outer_ipv6_flow_label[0x14]; 624 625 u8 reserved_at_100[0xc]; 626 u8 inner_ipv6_flow_label[0x14]; 627 628 u8 reserved_at_120[0xa]; 629 u8 geneve_opt_len[0x6]; 630 u8 geneve_protocol_type[0x10]; 631 632 u8 reserved_at_140[0x8]; 633 u8 bth_dst_qp[0x18]; 634 u8 inner_esp_spi[0x20]; 635 u8 outer_esp_spi[0x20]; 636 u8 reserved_at_1a0[0x60]; 637 }; 638 639 struct mlx5_ifc_fte_match_mpls_bits { 640 u8 mpls_label[0x14]; 641 u8 mpls_exp[0x3]; 642 u8 mpls_s_bos[0x1]; 643 u8 mpls_ttl[0x8]; 644 }; 645 646 struct mlx5_ifc_fte_match_set_misc2_bits { 647 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls; 648 649 struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls; 650 651 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre; 652 653 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp; 654 655 u8 metadata_reg_c_7[0x20]; 656 657 u8 metadata_reg_c_6[0x20]; 658 659 u8 metadata_reg_c_5[0x20]; 660 661 u8 metadata_reg_c_4[0x20]; 662 663 u8 metadata_reg_c_3[0x20]; 664 665 u8 metadata_reg_c_2[0x20]; 666 667 u8 metadata_reg_c_1[0x20]; 668 669 u8 metadata_reg_c_0[0x20]; 670 671 u8 metadata_reg_a[0x20]; 672 673 u8 reserved_at_1a0[0x8]; 674 675 u8 macsec_syndrome[0x8]; 676 u8 ipsec_syndrome[0x8]; 677 u8 reserved_at_1b8[0x8]; 678 679 u8 reserved_at_1c0[0x40]; 680 }; 681 682 struct mlx5_ifc_fte_match_set_misc3_bits { 683 u8 inner_tcp_seq_num[0x20]; 684 685 u8 outer_tcp_seq_num[0x20]; 686 687 u8 inner_tcp_ack_num[0x20]; 688 689 u8 outer_tcp_ack_num[0x20]; 690 691 u8 reserved_at_80[0x8]; 692 u8 outer_vxlan_gpe_vni[0x18]; 693 694 u8 outer_vxlan_gpe_next_protocol[0x8]; 695 u8 outer_vxlan_gpe_flags[0x8]; 696 u8 reserved_at_b0[0x10]; 697 698 u8 icmp_header_data[0x20]; 699 700 u8 icmpv6_header_data[0x20]; 701 702 u8 icmp_type[0x8]; 703 u8 icmp_code[0x8]; 704 u8 icmpv6_type[0x8]; 705 u8 icmpv6_code[0x8]; 706 707 u8 geneve_tlv_option_0_data[0x20]; 708 709 u8 gtpu_teid[0x20]; 710 711 u8 gtpu_msg_type[0x8]; 712 u8 gtpu_msg_flags[0x8]; 713 u8 reserved_at_170[0x10]; 714 715 u8 gtpu_dw_2[0x20]; 716 717 u8 gtpu_first_ext_dw_0[0x20]; 718 719 u8 gtpu_dw_0[0x20]; 720 721 u8 reserved_at_1e0[0x20]; 722 }; 723 724 struct mlx5_ifc_fte_match_set_misc4_bits { 725 u8 prog_sample_field_value_0[0x20]; 726 727 u8 prog_sample_field_id_0[0x20]; 728 729 u8 prog_sample_field_value_1[0x20]; 730 731 u8 prog_sample_field_id_1[0x20]; 732 733 u8 prog_sample_field_value_2[0x20]; 734 735 u8 prog_sample_field_id_2[0x20]; 736 737 u8 prog_sample_field_value_3[0x20]; 738 739 u8 prog_sample_field_id_3[0x20]; 740 741 u8 reserved_at_100[0x100]; 742 }; 743 744 struct mlx5_ifc_fte_match_set_misc5_bits { 745 u8 macsec_tag_0[0x20]; 746 747 u8 macsec_tag_1[0x20]; 748 749 u8 macsec_tag_2[0x20]; 750 751 u8 macsec_tag_3[0x20]; 752 753 u8 tunnel_header_0[0x20]; 754 755 u8 tunnel_header_1[0x20]; 756 757 u8 tunnel_header_2[0x20]; 758 759 u8 tunnel_header_3[0x20]; 760 761 u8 reserved_at_100[0x100]; 762 }; 763 764 struct mlx5_ifc_cmd_pas_bits { 765 u8 pa_h[0x20]; 766 767 u8 pa_l[0x14]; 768 u8 reserved_at_34[0xc]; 769 }; 770 771 struct mlx5_ifc_uint64_bits { 772 u8 hi[0x20]; 773 774 u8 lo[0x20]; 775 }; 776 777 enum { 778 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0, 779 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7, 780 MLX5_ADS_STAT_RATE_10GBPS = 0x8, 781 MLX5_ADS_STAT_RATE_30GBPS = 0x9, 782 MLX5_ADS_STAT_RATE_5GBPS = 0xa, 783 MLX5_ADS_STAT_RATE_20GBPS = 0xb, 784 MLX5_ADS_STAT_RATE_40GBPS = 0xc, 785 MLX5_ADS_STAT_RATE_60GBPS = 0xd, 786 MLX5_ADS_STAT_RATE_80GBPS = 0xe, 787 MLX5_ADS_STAT_RATE_120GBPS = 0xf, 788 }; 789 790 struct mlx5_ifc_ads_bits { 791 u8 fl[0x1]; 792 u8 free_ar[0x1]; 793 u8 reserved_at_2[0xe]; 794 u8 pkey_index[0x10]; 795 796 u8 reserved_at_20[0x8]; 797 u8 grh[0x1]; 798 u8 mlid[0x7]; 799 u8 rlid[0x10]; 800 801 u8 ack_timeout[0x5]; 802 u8 reserved_at_45[0x3]; 803 u8 src_addr_index[0x8]; 804 u8 reserved_at_50[0x4]; 805 u8 stat_rate[0x4]; 806 u8 hop_limit[0x8]; 807 808 u8 reserved_at_60[0x4]; 809 u8 tclass[0x8]; 810 u8 flow_label[0x14]; 811 812 u8 rgid_rip[16][0x8]; 813 814 u8 reserved_at_100[0x4]; 815 u8 f_dscp[0x1]; 816 u8 f_ecn[0x1]; 817 u8 reserved_at_106[0x1]; 818 u8 f_eth_prio[0x1]; 819 u8 ecn[0x2]; 820 u8 dscp[0x6]; 821 u8 udp_sport[0x10]; 822 823 u8 dei_cfi[0x1]; 824 u8 eth_prio[0x3]; 825 u8 sl[0x4]; 826 u8 vhca_port_num[0x8]; 827 u8 rmac_47_32[0x10]; 828 829 u8 rmac_31_0[0x20]; 830 }; 831 832 struct mlx5_ifc_flow_table_nic_cap_bits { 833 u8 nic_rx_multi_path_tirs[0x1]; 834 u8 nic_rx_multi_path_tirs_fts[0x1]; 835 u8 allow_sniffer_and_nic_rx_shared_tir[0x1]; 836 u8 reserved_at_3[0x4]; 837 u8 sw_owner_reformat_supported[0x1]; 838 u8 reserved_at_8[0x18]; 839 840 u8 encap_general_header[0x1]; 841 u8 reserved_at_21[0xa]; 842 u8 log_max_packet_reformat_context[0x5]; 843 u8 reserved_at_30[0x6]; 844 u8 max_encap_header_size[0xa]; 845 u8 reserved_at_40[0x1c0]; 846 847 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive; 848 849 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_rdma; 850 851 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer; 852 853 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit; 854 855 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_rdma; 856 857 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer; 858 859 u8 reserved_at_e00[0x600]; 860 861 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_receive; 862 863 u8 reserved_at_1480[0x80]; 864 865 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_receive_rdma; 866 867 u8 reserved_at_1580[0x280]; 868 869 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_transmit_rdma; 870 871 u8 reserved_at_1880[0x780]; 872 873 u8 sw_steering_nic_rx_action_drop_icm_address[0x40]; 874 875 u8 sw_steering_nic_tx_action_drop_icm_address[0x40]; 876 877 u8 sw_steering_nic_tx_action_allow_icm_address[0x40]; 878 879 u8 reserved_at_20c0[0x5f40]; 880 }; 881 882 struct mlx5_ifc_port_selection_cap_bits { 883 u8 reserved_at_0[0x10]; 884 u8 port_select_flow_table[0x1]; 885 u8 reserved_at_11[0x1]; 886 u8 port_select_flow_table_bypass[0x1]; 887 u8 reserved_at_13[0xd]; 888 889 u8 reserved_at_20[0x1e0]; 890 891 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_port_selection; 892 893 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_port_selection; 894 895 u8 reserved_at_480[0x7b80]; 896 }; 897 898 enum { 899 MLX5_FDB_TO_VPORT_REG_C_0 = 0x01, 900 MLX5_FDB_TO_VPORT_REG_C_1 = 0x02, 901 MLX5_FDB_TO_VPORT_REG_C_2 = 0x04, 902 MLX5_FDB_TO_VPORT_REG_C_3 = 0x08, 903 MLX5_FDB_TO_VPORT_REG_C_4 = 0x10, 904 MLX5_FDB_TO_VPORT_REG_C_5 = 0x20, 905 MLX5_FDB_TO_VPORT_REG_C_6 = 0x40, 906 MLX5_FDB_TO_VPORT_REG_C_7 = 0x80, 907 }; 908 909 struct mlx5_ifc_flow_table_eswitch_cap_bits { 910 u8 fdb_to_vport_reg_c_id[0x8]; 911 u8 reserved_at_8[0x5]; 912 u8 fdb_uplink_hairpin[0x1]; 913 u8 fdb_multi_path_any_table_limit_regc[0x1]; 914 u8 reserved_at_f[0x3]; 915 u8 fdb_multi_path_any_table[0x1]; 916 u8 reserved_at_13[0x2]; 917 u8 fdb_modify_header_fwd_to_table[0x1]; 918 u8 fdb_ipv4_ttl_modify[0x1]; 919 u8 flow_source[0x1]; 920 u8 reserved_at_18[0x2]; 921 u8 multi_fdb_encap[0x1]; 922 u8 egress_acl_forward_to_vport[0x1]; 923 u8 fdb_multi_path_to_table[0x1]; 924 u8 reserved_at_1d[0x3]; 925 926 u8 reserved_at_20[0x1e0]; 927 928 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb; 929 930 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress; 931 932 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress; 933 934 u8 reserved_at_800[0xC00]; 935 936 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_esw_fdb; 937 938 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_bitmask_support_2_esw_fdb; 939 940 u8 reserved_at_1500[0x300]; 941 942 u8 sw_steering_fdb_action_drop_icm_address_rx[0x40]; 943 944 u8 sw_steering_fdb_action_drop_icm_address_tx[0x40]; 945 946 u8 sw_steering_uplink_icm_address_rx[0x40]; 947 948 u8 sw_steering_uplink_icm_address_tx[0x40]; 949 950 u8 reserved_at_1900[0x6700]; 951 }; 952 953 enum { 954 MLX5_COUNTER_SOURCE_ESWITCH = 0x0, 955 MLX5_COUNTER_FLOW_ESWITCH = 0x1, 956 }; 957 958 struct mlx5_ifc_e_switch_cap_bits { 959 u8 vport_svlan_strip[0x1]; 960 u8 vport_cvlan_strip[0x1]; 961 u8 vport_svlan_insert[0x1]; 962 u8 vport_cvlan_insert_if_not_exist[0x1]; 963 u8 vport_cvlan_insert_overwrite[0x1]; 964 u8 reserved_at_5[0x1]; 965 u8 vport_cvlan_insert_always[0x1]; 966 u8 esw_shared_ingress_acl[0x1]; 967 u8 esw_uplink_ingress_acl[0x1]; 968 u8 root_ft_on_other_esw[0x1]; 969 u8 reserved_at_a[0xf]; 970 u8 esw_functions_changed[0x1]; 971 u8 reserved_at_1a[0x1]; 972 u8 ecpf_vport_exists[0x1]; 973 u8 counter_eswitch_affinity[0x1]; 974 u8 merged_eswitch[0x1]; 975 u8 nic_vport_node_guid_modify[0x1]; 976 u8 nic_vport_port_guid_modify[0x1]; 977 978 u8 vxlan_encap_decap[0x1]; 979 u8 nvgre_encap_decap[0x1]; 980 u8 reserved_at_22[0x1]; 981 u8 log_max_fdb_encap_uplink[0x5]; 982 u8 reserved_at_21[0x3]; 983 u8 log_max_packet_reformat_context[0x5]; 984 u8 reserved_2b[0x6]; 985 u8 max_encap_header_size[0xa]; 986 987 u8 reserved_at_40[0xb]; 988 u8 log_max_esw_sf[0x5]; 989 u8 esw_sf_base_id[0x10]; 990 991 u8 reserved_at_60[0x7a0]; 992 993 }; 994 995 struct mlx5_ifc_qos_cap_bits { 996 u8 packet_pacing[0x1]; 997 u8 esw_scheduling[0x1]; 998 u8 esw_bw_share[0x1]; 999 u8 esw_rate_limit[0x1]; 1000 u8 reserved_at_4[0x1]; 1001 u8 packet_pacing_burst_bound[0x1]; 1002 u8 packet_pacing_typical_size[0x1]; 1003 u8 reserved_at_7[0x1]; 1004 u8 nic_sq_scheduling[0x1]; 1005 u8 nic_bw_share[0x1]; 1006 u8 nic_rate_limit[0x1]; 1007 u8 packet_pacing_uid[0x1]; 1008 u8 log_esw_max_sched_depth[0x4]; 1009 u8 reserved_at_10[0x10]; 1010 1011 u8 reserved_at_20[0xb]; 1012 u8 log_max_qos_nic_queue_group[0x5]; 1013 u8 reserved_at_30[0x10]; 1014 1015 u8 packet_pacing_max_rate[0x20]; 1016 1017 u8 packet_pacing_min_rate[0x20]; 1018 1019 u8 reserved_at_80[0x10]; 1020 u8 packet_pacing_rate_table_size[0x10]; 1021 1022 u8 esw_element_type[0x10]; 1023 u8 esw_tsar_type[0x10]; 1024 1025 u8 reserved_at_c0[0x10]; 1026 u8 max_qos_para_vport[0x10]; 1027 1028 u8 max_tsar_bw_share[0x20]; 1029 1030 u8 reserved_at_100[0x20]; 1031 1032 u8 reserved_at_120[0x3]; 1033 u8 log_meter_aso_granularity[0x5]; 1034 u8 reserved_at_128[0x3]; 1035 u8 log_meter_aso_max_alloc[0x5]; 1036 u8 reserved_at_130[0x3]; 1037 u8 log_max_num_meter_aso[0x5]; 1038 u8 reserved_at_138[0x8]; 1039 1040 u8 reserved_at_140[0x6c0]; 1041 }; 1042 1043 struct mlx5_ifc_debug_cap_bits { 1044 u8 core_dump_general[0x1]; 1045 u8 core_dump_qp[0x1]; 1046 u8 reserved_at_2[0x7]; 1047 u8 resource_dump[0x1]; 1048 u8 reserved_at_a[0x16]; 1049 1050 u8 reserved_at_20[0x2]; 1051 u8 stall_detect[0x1]; 1052 u8 reserved_at_23[0x1d]; 1053 1054 u8 reserved_at_40[0x7c0]; 1055 }; 1056 1057 struct mlx5_ifc_per_protocol_networking_offload_caps_bits { 1058 u8 csum_cap[0x1]; 1059 u8 vlan_cap[0x1]; 1060 u8 lro_cap[0x1]; 1061 u8 lro_psh_flag[0x1]; 1062 u8 lro_time_stamp[0x1]; 1063 u8 reserved_at_5[0x2]; 1064 u8 wqe_vlan_insert[0x1]; 1065 u8 self_lb_en_modifiable[0x1]; 1066 u8 reserved_at_9[0x2]; 1067 u8 max_lso_cap[0x5]; 1068 u8 multi_pkt_send_wqe[0x2]; 1069 u8 wqe_inline_mode[0x2]; 1070 u8 rss_ind_tbl_cap[0x4]; 1071 u8 reg_umr_sq[0x1]; 1072 u8 scatter_fcs[0x1]; 1073 u8 enhanced_multi_pkt_send_wqe[0x1]; 1074 u8 tunnel_lso_const_out_ip_id[0x1]; 1075 u8 tunnel_lro_gre[0x1]; 1076 u8 tunnel_lro_vxlan[0x1]; 1077 u8 tunnel_stateless_gre[0x1]; 1078 u8 tunnel_stateless_vxlan[0x1]; 1079 1080 u8 swp[0x1]; 1081 u8 swp_csum[0x1]; 1082 u8 swp_lso[0x1]; 1083 u8 cqe_checksum_full[0x1]; 1084 u8 tunnel_stateless_geneve_tx[0x1]; 1085 u8 tunnel_stateless_mpls_over_udp[0x1]; 1086 u8 tunnel_stateless_mpls_over_gre[0x1]; 1087 u8 tunnel_stateless_vxlan_gpe[0x1]; 1088 u8 tunnel_stateless_ipv4_over_vxlan[0x1]; 1089 u8 tunnel_stateless_ip_over_ip[0x1]; 1090 u8 insert_trailer[0x1]; 1091 u8 reserved_at_2b[0x1]; 1092 u8 tunnel_stateless_ip_over_ip_rx[0x1]; 1093 u8 tunnel_stateless_ip_over_ip_tx[0x1]; 1094 u8 reserved_at_2e[0x2]; 1095 u8 max_vxlan_udp_ports[0x8]; 1096 u8 reserved_at_38[0x6]; 1097 u8 max_geneve_opt_len[0x1]; 1098 u8 tunnel_stateless_geneve_rx[0x1]; 1099 1100 u8 reserved_at_40[0x10]; 1101 u8 lro_min_mss_size[0x10]; 1102 1103 u8 reserved_at_60[0x120]; 1104 1105 u8 lro_timer_supported_periods[4][0x20]; 1106 1107 u8 reserved_at_200[0x600]; 1108 }; 1109 1110 enum { 1111 MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING = 0x0, 1112 MLX5_TIMESTAMP_FORMAT_CAP_REAL_TIME = 0x1, 1113 MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING_AND_REAL_TIME = 0x2, 1114 }; 1115 1116 struct mlx5_ifc_roce_cap_bits { 1117 u8 roce_apm[0x1]; 1118 u8 reserved_at_1[0x3]; 1119 u8 sw_r_roce_src_udp_port[0x1]; 1120 u8 fl_rc_qp_when_roce_disabled[0x1]; 1121 u8 fl_rc_qp_when_roce_enabled[0x1]; 1122 u8 roce_cc_general[0x1]; 1123 u8 qp_ooo_transmit_default[0x1]; 1124 u8 reserved_at_9[0x15]; 1125 u8 qp_ts_format[0x2]; 1126 1127 u8 reserved_at_20[0x60]; 1128 1129 u8 reserved_at_80[0xc]; 1130 u8 l3_type[0x4]; 1131 u8 reserved_at_90[0x8]; 1132 u8 roce_version[0x8]; 1133 1134 u8 reserved_at_a0[0x10]; 1135 u8 r_roce_dest_udp_port[0x10]; 1136 1137 u8 r_roce_max_src_udp_port[0x10]; 1138 u8 r_roce_min_src_udp_port[0x10]; 1139 1140 u8 reserved_at_e0[0x10]; 1141 u8 roce_address_table_size[0x10]; 1142 1143 u8 reserved_at_100[0x700]; 1144 }; 1145 1146 struct mlx5_ifc_sync_steering_in_bits { 1147 u8 opcode[0x10]; 1148 u8 uid[0x10]; 1149 1150 u8 reserved_at_20[0x10]; 1151 u8 op_mod[0x10]; 1152 1153 u8 reserved_at_40[0xc0]; 1154 }; 1155 1156 struct mlx5_ifc_sync_steering_out_bits { 1157 u8 status[0x8]; 1158 u8 reserved_at_8[0x18]; 1159 1160 u8 syndrome[0x20]; 1161 1162 u8 reserved_at_40[0x40]; 1163 }; 1164 1165 struct mlx5_ifc_sync_crypto_in_bits { 1166 u8 opcode[0x10]; 1167 u8 uid[0x10]; 1168 1169 u8 reserved_at_20[0x10]; 1170 u8 op_mod[0x10]; 1171 1172 u8 reserved_at_40[0x20]; 1173 1174 u8 reserved_at_60[0x10]; 1175 u8 crypto_type[0x10]; 1176 1177 u8 reserved_at_80[0x80]; 1178 }; 1179 1180 struct mlx5_ifc_sync_crypto_out_bits { 1181 u8 status[0x8]; 1182 u8 reserved_at_8[0x18]; 1183 1184 u8 syndrome[0x20]; 1185 1186 u8 reserved_at_40[0x40]; 1187 }; 1188 1189 struct mlx5_ifc_device_mem_cap_bits { 1190 u8 memic[0x1]; 1191 u8 reserved_at_1[0x1f]; 1192 1193 u8 reserved_at_20[0xb]; 1194 u8 log_min_memic_alloc_size[0x5]; 1195 u8 reserved_at_30[0x8]; 1196 u8 log_max_memic_addr_alignment[0x8]; 1197 1198 u8 memic_bar_start_addr[0x40]; 1199 1200 u8 memic_bar_size[0x20]; 1201 1202 u8 max_memic_size[0x20]; 1203 1204 u8 steering_sw_icm_start_address[0x40]; 1205 1206 u8 reserved_at_100[0x8]; 1207 u8 log_header_modify_sw_icm_size[0x8]; 1208 u8 reserved_at_110[0x2]; 1209 u8 log_sw_icm_alloc_granularity[0x6]; 1210 u8 log_steering_sw_icm_size[0x8]; 1211 1212 u8 log_indirect_encap_sw_icm_size[0x8]; 1213 u8 reserved_at_128[0x10]; 1214 u8 log_header_modify_pattern_sw_icm_size[0x8]; 1215 1216 u8 header_modify_sw_icm_start_address[0x40]; 1217 1218 u8 reserved_at_180[0x40]; 1219 1220 u8 header_modify_pattern_sw_icm_start_address[0x40]; 1221 1222 u8 memic_operations[0x20]; 1223 1224 u8 reserved_at_220[0x20]; 1225 1226 u8 indirect_encap_sw_icm_start_address[0x40]; 1227 1228 u8 reserved_at_280[0x580]; 1229 }; 1230 1231 struct mlx5_ifc_device_event_cap_bits { 1232 u8 user_affiliated_events[4][0x40]; 1233 1234 u8 user_unaffiliated_events[4][0x40]; 1235 }; 1236 1237 struct mlx5_ifc_virtio_emulation_cap_bits { 1238 u8 desc_tunnel_offload_type[0x1]; 1239 u8 eth_frame_offload_type[0x1]; 1240 u8 virtio_version_1_0[0x1]; 1241 u8 device_features_bits_mask[0xd]; 1242 u8 event_mode[0x8]; 1243 u8 virtio_queue_type[0x8]; 1244 1245 u8 max_tunnel_desc[0x10]; 1246 u8 reserved_at_30[0x3]; 1247 u8 log_doorbell_stride[0x5]; 1248 u8 reserved_at_38[0x3]; 1249 u8 log_doorbell_bar_size[0x5]; 1250 1251 u8 doorbell_bar_offset[0x40]; 1252 1253 u8 max_emulated_devices[0x8]; 1254 u8 max_num_virtio_queues[0x18]; 1255 1256 u8 reserved_at_a0[0x20]; 1257 1258 u8 reserved_at_c0[0x13]; 1259 u8 desc_group_mkey_supported[0x1]; 1260 u8 freeze_to_rdy_supported[0x1]; 1261 u8 reserved_at_d5[0xb]; 1262 1263 u8 reserved_at_e0[0x20]; 1264 1265 u8 umem_1_buffer_param_a[0x20]; 1266 1267 u8 umem_1_buffer_param_b[0x20]; 1268 1269 u8 umem_2_buffer_param_a[0x20]; 1270 1271 u8 umem_2_buffer_param_b[0x20]; 1272 1273 u8 umem_3_buffer_param_a[0x20]; 1274 1275 u8 umem_3_buffer_param_b[0x20]; 1276 1277 u8 reserved_at_1c0[0x640]; 1278 }; 1279 1280 enum { 1281 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0, 1282 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2, 1283 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4, 1284 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8, 1285 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10, 1286 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20, 1287 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40, 1288 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80, 1289 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100, 1290 }; 1291 1292 enum { 1293 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1, 1294 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2, 1295 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4, 1296 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8, 1297 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10, 1298 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20, 1299 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40, 1300 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80, 1301 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100, 1302 }; 1303 1304 struct mlx5_ifc_atomic_caps_bits { 1305 u8 reserved_at_0[0x40]; 1306 1307 u8 atomic_req_8B_endianness_mode[0x2]; 1308 u8 reserved_at_42[0x4]; 1309 u8 supported_atomic_req_8B_endianness_mode_1[0x1]; 1310 1311 u8 reserved_at_47[0x19]; 1312 1313 u8 reserved_at_60[0x20]; 1314 1315 u8 reserved_at_80[0x10]; 1316 u8 atomic_operations[0x10]; 1317 1318 u8 reserved_at_a0[0x10]; 1319 u8 atomic_size_qp[0x10]; 1320 1321 u8 reserved_at_c0[0x10]; 1322 u8 atomic_size_dc[0x10]; 1323 1324 u8 reserved_at_e0[0x720]; 1325 }; 1326 1327 struct mlx5_ifc_odp_cap_bits { 1328 u8 reserved_at_0[0x40]; 1329 1330 u8 sig[0x1]; 1331 u8 reserved_at_41[0x1f]; 1332 1333 u8 reserved_at_60[0x20]; 1334 1335 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps; 1336 1337 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps; 1338 1339 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps; 1340 1341 struct mlx5_ifc_odp_per_transport_service_cap_bits xrc_odp_caps; 1342 1343 struct mlx5_ifc_odp_per_transport_service_cap_bits dc_odp_caps; 1344 1345 u8 reserved_at_120[0x6E0]; 1346 }; 1347 1348 struct mlx5_ifc_tls_cap_bits { 1349 u8 tls_1_2_aes_gcm_128[0x1]; 1350 u8 tls_1_3_aes_gcm_128[0x1]; 1351 u8 tls_1_2_aes_gcm_256[0x1]; 1352 u8 tls_1_3_aes_gcm_256[0x1]; 1353 u8 reserved_at_4[0x1c]; 1354 1355 u8 reserved_at_20[0x7e0]; 1356 }; 1357 1358 struct mlx5_ifc_ipsec_cap_bits { 1359 u8 ipsec_full_offload[0x1]; 1360 u8 ipsec_crypto_offload[0x1]; 1361 u8 ipsec_esn[0x1]; 1362 u8 ipsec_crypto_esp_aes_gcm_256_encrypt[0x1]; 1363 u8 ipsec_crypto_esp_aes_gcm_128_encrypt[0x1]; 1364 u8 ipsec_crypto_esp_aes_gcm_256_decrypt[0x1]; 1365 u8 ipsec_crypto_esp_aes_gcm_128_decrypt[0x1]; 1366 u8 reserved_at_7[0x4]; 1367 u8 log_max_ipsec_offload[0x5]; 1368 u8 reserved_at_10[0x10]; 1369 1370 u8 min_log_ipsec_full_replay_window[0x8]; 1371 u8 max_log_ipsec_full_replay_window[0x8]; 1372 u8 reserved_at_30[0x7d0]; 1373 }; 1374 1375 struct mlx5_ifc_macsec_cap_bits { 1376 u8 macsec_epn[0x1]; 1377 u8 reserved_at_1[0x2]; 1378 u8 macsec_crypto_esp_aes_gcm_256_encrypt[0x1]; 1379 u8 macsec_crypto_esp_aes_gcm_128_encrypt[0x1]; 1380 u8 macsec_crypto_esp_aes_gcm_256_decrypt[0x1]; 1381 u8 macsec_crypto_esp_aes_gcm_128_decrypt[0x1]; 1382 u8 reserved_at_7[0x4]; 1383 u8 log_max_macsec_offload[0x5]; 1384 u8 reserved_at_10[0x10]; 1385 1386 u8 min_log_macsec_full_replay_window[0x8]; 1387 u8 max_log_macsec_full_replay_window[0x8]; 1388 u8 reserved_at_30[0x10]; 1389 1390 u8 reserved_at_40[0x7c0]; 1391 }; 1392 1393 enum { 1394 MLX5_WQ_TYPE_LINKED_LIST = 0x0, 1395 MLX5_WQ_TYPE_CYCLIC = 0x1, 1396 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2, 1397 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3, 1398 }; 1399 1400 enum { 1401 MLX5_WQ_END_PAD_MODE_NONE = 0x0, 1402 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1, 1403 }; 1404 1405 enum { 1406 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0, 1407 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1, 1408 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2, 1409 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3, 1410 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4, 1411 }; 1412 1413 enum { 1414 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0, 1415 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1, 1416 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2, 1417 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3, 1418 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4, 1419 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5, 1420 }; 1421 1422 enum { 1423 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0, 1424 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1, 1425 }; 1426 1427 enum { 1428 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0, 1429 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1, 1430 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3, 1431 }; 1432 1433 enum { 1434 MLX5_CAP_PORT_TYPE_IB = 0x0, 1435 MLX5_CAP_PORT_TYPE_ETH = 0x1, 1436 }; 1437 1438 enum { 1439 MLX5_CAP_UMR_FENCE_STRONG = 0x0, 1440 MLX5_CAP_UMR_FENCE_SMALL = 0x1, 1441 MLX5_CAP_UMR_FENCE_NONE = 0x2, 1442 }; 1443 1444 enum { 1445 MLX5_FLEX_PARSER_GENEVE_ENABLED = 1 << 3, 1446 MLX5_FLEX_PARSER_MPLS_OVER_GRE_ENABLED = 1 << 4, 1447 MLX5_FLEX_PARSER_MPLS_OVER_UDP_ENABLED = 1 << 5, 1448 MLX5_FLEX_PARSER_VXLAN_GPE_ENABLED = 1 << 7, 1449 MLX5_FLEX_PARSER_ICMP_V4_ENABLED = 1 << 8, 1450 MLX5_FLEX_PARSER_ICMP_V6_ENABLED = 1 << 9, 1451 MLX5_FLEX_PARSER_GENEVE_TLV_OPTION_0_ENABLED = 1 << 10, 1452 MLX5_FLEX_PARSER_GTPU_ENABLED = 1 << 11, 1453 MLX5_FLEX_PARSER_GTPU_DW_2_ENABLED = 1 << 16, 1454 MLX5_FLEX_PARSER_GTPU_FIRST_EXT_DW_0_ENABLED = 1 << 17, 1455 MLX5_FLEX_PARSER_GTPU_DW_0_ENABLED = 1 << 18, 1456 MLX5_FLEX_PARSER_GTPU_TEID_ENABLED = 1 << 19, 1457 }; 1458 1459 enum { 1460 MLX5_UCTX_CAP_RAW_TX = 1UL << 0, 1461 MLX5_UCTX_CAP_INTERNAL_DEV_RES = 1UL << 1, 1462 }; 1463 1464 #define MLX5_FC_BULK_SIZE_FACTOR 128 1465 1466 enum mlx5_fc_bulk_alloc_bitmask { 1467 MLX5_FC_BULK_128 = (1 << 0), 1468 MLX5_FC_BULK_256 = (1 << 1), 1469 MLX5_FC_BULK_512 = (1 << 2), 1470 MLX5_FC_BULK_1024 = (1 << 3), 1471 MLX5_FC_BULK_2048 = (1 << 4), 1472 MLX5_FC_BULK_4096 = (1 << 5), 1473 MLX5_FC_BULK_8192 = (1 << 6), 1474 MLX5_FC_BULK_16384 = (1 << 7), 1475 }; 1476 1477 #define MLX5_FC_BULK_NUM_FCS(fc_enum) (MLX5_FC_BULK_SIZE_FACTOR * (fc_enum)) 1478 1479 #define MLX5_FT_MAX_MULTIPATH_LEVEL 63 1480 1481 enum { 1482 MLX5_STEERING_FORMAT_CONNECTX_5 = 0, 1483 MLX5_STEERING_FORMAT_CONNECTX_6DX = 1, 1484 MLX5_STEERING_FORMAT_CONNECTX_7 = 2, 1485 }; 1486 1487 struct mlx5_ifc_cmd_hca_cap_bits { 1488 u8 reserved_at_0[0x6]; 1489 u8 page_request_disable[0x1]; 1490 u8 reserved_at_7[0x9]; 1491 u8 shared_object_to_user_object_allowed[0x1]; 1492 u8 reserved_at_13[0xe]; 1493 u8 vhca_resource_manager[0x1]; 1494 1495 u8 hca_cap_2[0x1]; 1496 u8 create_lag_when_not_master_up[0x1]; 1497 u8 dtor[0x1]; 1498 u8 event_on_vhca_state_teardown_request[0x1]; 1499 u8 event_on_vhca_state_in_use[0x1]; 1500 u8 event_on_vhca_state_active[0x1]; 1501 u8 event_on_vhca_state_allocated[0x1]; 1502 u8 event_on_vhca_state_invalid[0x1]; 1503 u8 reserved_at_28[0x8]; 1504 u8 vhca_id[0x10]; 1505 1506 u8 reserved_at_40[0x40]; 1507 1508 u8 log_max_srq_sz[0x8]; 1509 u8 log_max_qp_sz[0x8]; 1510 u8 event_cap[0x1]; 1511 u8 reserved_at_91[0x2]; 1512 u8 isolate_vl_tc_new[0x1]; 1513 u8 reserved_at_94[0x4]; 1514 u8 prio_tag_required[0x1]; 1515 u8 reserved_at_99[0x2]; 1516 u8 log_max_qp[0x5]; 1517 1518 u8 reserved_at_a0[0x3]; 1519 u8 ece_support[0x1]; 1520 u8 reserved_at_a4[0x5]; 1521 u8 reg_c_preserve[0x1]; 1522 u8 reserved_at_aa[0x1]; 1523 u8 log_max_srq[0x5]; 1524 u8 reserved_at_b0[0x1]; 1525 u8 uplink_follow[0x1]; 1526 u8 ts_cqe_to_dest_cqn[0x1]; 1527 u8 reserved_at_b3[0x6]; 1528 u8 go_back_n[0x1]; 1529 u8 shampo[0x1]; 1530 u8 reserved_at_bb[0x5]; 1531 1532 u8 max_sgl_for_optimized_performance[0x8]; 1533 u8 log_max_cq_sz[0x8]; 1534 u8 relaxed_ordering_write_umr[0x1]; 1535 u8 relaxed_ordering_read_umr[0x1]; 1536 u8 reserved_at_d2[0x7]; 1537 u8 virtio_net_device_emualtion_manager[0x1]; 1538 u8 virtio_blk_device_emualtion_manager[0x1]; 1539 u8 log_max_cq[0x5]; 1540 1541 u8 log_max_eq_sz[0x8]; 1542 u8 relaxed_ordering_write[0x1]; 1543 u8 relaxed_ordering_read_pci_enabled[0x1]; 1544 u8 log_max_mkey[0x6]; 1545 u8 reserved_at_f0[0x6]; 1546 u8 terminate_scatter_list_mkey[0x1]; 1547 u8 repeated_mkey[0x1]; 1548 u8 dump_fill_mkey[0x1]; 1549 u8 reserved_at_f9[0x2]; 1550 u8 fast_teardown[0x1]; 1551 u8 log_max_eq[0x4]; 1552 1553 u8 max_indirection[0x8]; 1554 u8 fixed_buffer_size[0x1]; 1555 u8 log_max_mrw_sz[0x7]; 1556 u8 force_teardown[0x1]; 1557 u8 reserved_at_111[0x1]; 1558 u8 log_max_bsf_list_size[0x6]; 1559 u8 umr_extended_translation_offset[0x1]; 1560 u8 null_mkey[0x1]; 1561 u8 log_max_klm_list_size[0x6]; 1562 1563 u8 reserved_at_120[0x2]; 1564 u8 qpc_extension[0x1]; 1565 u8 reserved_at_123[0x7]; 1566 u8 log_max_ra_req_dc[0x6]; 1567 u8 reserved_at_130[0x2]; 1568 u8 eth_wqe_too_small[0x1]; 1569 u8 reserved_at_133[0x6]; 1570 u8 vnic_env_cq_overrun[0x1]; 1571 u8 log_max_ra_res_dc[0x6]; 1572 1573 u8 reserved_at_140[0x5]; 1574 u8 release_all_pages[0x1]; 1575 u8 must_not_use[0x1]; 1576 u8 reserved_at_147[0x2]; 1577 u8 roce_accl[0x1]; 1578 u8 log_max_ra_req_qp[0x6]; 1579 u8 reserved_at_150[0xa]; 1580 u8 log_max_ra_res_qp[0x6]; 1581 1582 u8 end_pad[0x1]; 1583 u8 cc_query_allowed[0x1]; 1584 u8 cc_modify_allowed[0x1]; 1585 u8 start_pad[0x1]; 1586 u8 cache_line_128byte[0x1]; 1587 u8 reserved_at_165[0x4]; 1588 u8 rts2rts_qp_counters_set_id[0x1]; 1589 u8 reserved_at_16a[0x2]; 1590 u8 vnic_env_int_rq_oob[0x1]; 1591 u8 sbcam_reg[0x1]; 1592 u8 reserved_at_16e[0x1]; 1593 u8 qcam_reg[0x1]; 1594 u8 gid_table_size[0x10]; 1595 1596 u8 out_of_seq_cnt[0x1]; 1597 u8 vport_counters[0x1]; 1598 u8 retransmission_q_counters[0x1]; 1599 u8 debug[0x1]; 1600 u8 modify_rq_counter_set_id[0x1]; 1601 u8 rq_delay_drop[0x1]; 1602 u8 max_qp_cnt[0xa]; 1603 u8 pkey_table_size[0x10]; 1604 1605 u8 vport_group_manager[0x1]; 1606 u8 vhca_group_manager[0x1]; 1607 u8 ib_virt[0x1]; 1608 u8 eth_virt[0x1]; 1609 u8 vnic_env_queue_counters[0x1]; 1610 u8 ets[0x1]; 1611 u8 nic_flow_table[0x1]; 1612 u8 eswitch_manager[0x1]; 1613 u8 device_memory[0x1]; 1614 u8 mcam_reg[0x1]; 1615 u8 pcam_reg[0x1]; 1616 u8 local_ca_ack_delay[0x5]; 1617 u8 port_module_event[0x1]; 1618 u8 enhanced_error_q_counters[0x1]; 1619 u8 ports_check[0x1]; 1620 u8 reserved_at_1b3[0x1]; 1621 u8 disable_link_up[0x1]; 1622 u8 beacon_led[0x1]; 1623 u8 port_type[0x2]; 1624 u8 num_ports[0x8]; 1625 1626 u8 reserved_at_1c0[0x1]; 1627 u8 pps[0x1]; 1628 u8 pps_modify[0x1]; 1629 u8 log_max_msg[0x5]; 1630 u8 reserved_at_1c8[0x4]; 1631 u8 max_tc[0x4]; 1632 u8 temp_warn_event[0x1]; 1633 u8 dcbx[0x1]; 1634 u8 general_notification_event[0x1]; 1635 u8 reserved_at_1d3[0x2]; 1636 u8 fpga[0x1]; 1637 u8 rol_s[0x1]; 1638 u8 rol_g[0x1]; 1639 u8 reserved_at_1d8[0x1]; 1640 u8 wol_s[0x1]; 1641 u8 wol_g[0x1]; 1642 u8 wol_a[0x1]; 1643 u8 wol_b[0x1]; 1644 u8 wol_m[0x1]; 1645 u8 wol_u[0x1]; 1646 u8 wol_p[0x1]; 1647 1648 u8 stat_rate_support[0x10]; 1649 u8 reserved_at_1f0[0x1]; 1650 u8 pci_sync_for_fw_update_event[0x1]; 1651 u8 reserved_at_1f2[0x6]; 1652 u8 init2_lag_tx_port_affinity[0x1]; 1653 u8 reserved_at_1fa[0x3]; 1654 u8 cqe_version[0x4]; 1655 1656 u8 compact_address_vector[0x1]; 1657 u8 striding_rq[0x1]; 1658 u8 reserved_at_202[0x1]; 1659 u8 ipoib_enhanced_offloads[0x1]; 1660 u8 ipoib_basic_offloads[0x1]; 1661 u8 reserved_at_205[0x1]; 1662 u8 repeated_block_disabled[0x1]; 1663 u8 umr_modify_entity_size_disabled[0x1]; 1664 u8 umr_modify_atomic_disabled[0x1]; 1665 u8 umr_indirect_mkey_disabled[0x1]; 1666 u8 umr_fence[0x2]; 1667 u8 dc_req_scat_data_cqe[0x1]; 1668 u8 reserved_at_20d[0x2]; 1669 u8 drain_sigerr[0x1]; 1670 u8 cmdif_checksum[0x2]; 1671 u8 sigerr_cqe[0x1]; 1672 u8 reserved_at_213[0x1]; 1673 u8 wq_signature[0x1]; 1674 u8 sctr_data_cqe[0x1]; 1675 u8 reserved_at_216[0x1]; 1676 u8 sho[0x1]; 1677 u8 tph[0x1]; 1678 u8 rf[0x1]; 1679 u8 dct[0x1]; 1680 u8 qos[0x1]; 1681 u8 eth_net_offloads[0x1]; 1682 u8 roce[0x1]; 1683 u8 atomic[0x1]; 1684 u8 reserved_at_21f[0x1]; 1685 1686 u8 cq_oi[0x1]; 1687 u8 cq_resize[0x1]; 1688 u8 cq_moderation[0x1]; 1689 u8 reserved_at_223[0x3]; 1690 u8 cq_eq_remap[0x1]; 1691 u8 pg[0x1]; 1692 u8 block_lb_mc[0x1]; 1693 u8 reserved_at_229[0x1]; 1694 u8 scqe_break_moderation[0x1]; 1695 u8 cq_period_start_from_cqe[0x1]; 1696 u8 cd[0x1]; 1697 u8 reserved_at_22d[0x1]; 1698 u8 apm[0x1]; 1699 u8 vector_calc[0x1]; 1700 u8 umr_ptr_rlky[0x1]; 1701 u8 imaicl[0x1]; 1702 u8 qp_packet_based[0x1]; 1703 u8 reserved_at_233[0x3]; 1704 u8 qkv[0x1]; 1705 u8 pkv[0x1]; 1706 u8 set_deth_sqpn[0x1]; 1707 u8 reserved_at_239[0x3]; 1708 u8 xrc[0x1]; 1709 u8 ud[0x1]; 1710 u8 uc[0x1]; 1711 u8 rc[0x1]; 1712 1713 u8 uar_4k[0x1]; 1714 u8 reserved_at_241[0x7]; 1715 u8 fl_rc_qp_when_roce_disabled[0x1]; 1716 u8 regexp_params[0x1]; 1717 u8 uar_sz[0x6]; 1718 u8 port_selection_cap[0x1]; 1719 u8 reserved_at_251[0x1]; 1720 u8 umem_uid_0[0x1]; 1721 u8 reserved_at_253[0x5]; 1722 u8 log_pg_sz[0x8]; 1723 1724 u8 bf[0x1]; 1725 u8 driver_version[0x1]; 1726 u8 pad_tx_eth_packet[0x1]; 1727 u8 reserved_at_263[0x3]; 1728 u8 mkey_by_name[0x1]; 1729 u8 reserved_at_267[0x4]; 1730 1731 u8 log_bf_reg_size[0x5]; 1732 1733 u8 reserved_at_270[0x3]; 1734 u8 qp_error_syndrome[0x1]; 1735 u8 reserved_at_274[0x2]; 1736 u8 lag_dct[0x2]; 1737 u8 lag_tx_port_affinity[0x1]; 1738 u8 lag_native_fdb_selection[0x1]; 1739 u8 reserved_at_27a[0x1]; 1740 u8 lag_master[0x1]; 1741 u8 num_lag_ports[0x4]; 1742 1743 u8 reserved_at_280[0x10]; 1744 u8 max_wqe_sz_sq[0x10]; 1745 1746 u8 reserved_at_2a0[0x10]; 1747 u8 max_wqe_sz_rq[0x10]; 1748 1749 u8 max_flow_counter_31_16[0x10]; 1750 u8 max_wqe_sz_sq_dc[0x10]; 1751 1752 u8 reserved_at_2e0[0x7]; 1753 u8 max_qp_mcg[0x19]; 1754 1755 u8 reserved_at_300[0x10]; 1756 u8 flow_counter_bulk_alloc[0x8]; 1757 u8 log_max_mcg[0x8]; 1758 1759 u8 reserved_at_320[0x3]; 1760 u8 log_max_transport_domain[0x5]; 1761 u8 reserved_at_328[0x2]; 1762 u8 relaxed_ordering_read[0x1]; 1763 u8 log_max_pd[0x5]; 1764 u8 reserved_at_330[0x6]; 1765 u8 pci_sync_for_fw_update_with_driver_unload[0x1]; 1766 u8 vnic_env_cnt_steering_fail[0x1]; 1767 u8 vport_counter_local_loopback[0x1]; 1768 u8 q_counter_aggregation[0x1]; 1769 u8 q_counter_other_vport[0x1]; 1770 u8 log_max_xrcd[0x5]; 1771 1772 u8 nic_receive_steering_discard[0x1]; 1773 u8 receive_discard_vport_down[0x1]; 1774 u8 transmit_discard_vport_down[0x1]; 1775 u8 eq_overrun_count[0x1]; 1776 u8 reserved_at_344[0x1]; 1777 u8 invalid_command_count[0x1]; 1778 u8 quota_exceeded_count[0x1]; 1779 u8 reserved_at_347[0x1]; 1780 u8 log_max_flow_counter_bulk[0x8]; 1781 u8 max_flow_counter_15_0[0x10]; 1782 1783 1784 u8 reserved_at_360[0x3]; 1785 u8 log_max_rq[0x5]; 1786 u8 reserved_at_368[0x3]; 1787 u8 log_max_sq[0x5]; 1788 u8 reserved_at_370[0x3]; 1789 u8 log_max_tir[0x5]; 1790 u8 reserved_at_378[0x3]; 1791 u8 log_max_tis[0x5]; 1792 1793 u8 basic_cyclic_rcv_wqe[0x1]; 1794 u8 reserved_at_381[0x2]; 1795 u8 log_max_rmp[0x5]; 1796 u8 reserved_at_388[0x3]; 1797 u8 log_max_rqt[0x5]; 1798 u8 reserved_at_390[0x3]; 1799 u8 log_max_rqt_size[0x5]; 1800 u8 reserved_at_398[0x3]; 1801 u8 log_max_tis_per_sq[0x5]; 1802 1803 u8 ext_stride_num_range[0x1]; 1804 u8 roce_rw_supported[0x1]; 1805 u8 log_max_current_uc_list_wr_supported[0x1]; 1806 u8 log_max_stride_sz_rq[0x5]; 1807 u8 reserved_at_3a8[0x3]; 1808 u8 log_min_stride_sz_rq[0x5]; 1809 u8 reserved_at_3b0[0x3]; 1810 u8 log_max_stride_sz_sq[0x5]; 1811 u8 reserved_at_3b8[0x3]; 1812 u8 log_min_stride_sz_sq[0x5]; 1813 1814 u8 hairpin[0x1]; 1815 u8 reserved_at_3c1[0x2]; 1816 u8 log_max_hairpin_queues[0x5]; 1817 u8 reserved_at_3c8[0x3]; 1818 u8 log_max_hairpin_wq_data_sz[0x5]; 1819 u8 reserved_at_3d0[0x3]; 1820 u8 log_max_hairpin_num_packets[0x5]; 1821 u8 reserved_at_3d8[0x3]; 1822 u8 log_max_wq_sz[0x5]; 1823 1824 u8 nic_vport_change_event[0x1]; 1825 u8 disable_local_lb_uc[0x1]; 1826 u8 disable_local_lb_mc[0x1]; 1827 u8 log_min_hairpin_wq_data_sz[0x5]; 1828 u8 reserved_at_3e8[0x1]; 1829 u8 silent_mode[0x1]; 1830 u8 vhca_state[0x1]; 1831 u8 log_max_vlan_list[0x5]; 1832 u8 reserved_at_3f0[0x3]; 1833 u8 log_max_current_mc_list[0x5]; 1834 u8 reserved_at_3f8[0x3]; 1835 u8 log_max_current_uc_list[0x5]; 1836 1837 u8 general_obj_types[0x40]; 1838 1839 u8 sq_ts_format[0x2]; 1840 u8 rq_ts_format[0x2]; 1841 u8 steering_format_version[0x4]; 1842 u8 create_qp_start_hint[0x18]; 1843 1844 u8 reserved_at_460[0x1]; 1845 u8 ats[0x1]; 1846 u8 cross_vhca_rqt[0x1]; 1847 u8 log_max_uctx[0x5]; 1848 u8 reserved_at_468[0x1]; 1849 u8 crypto[0x1]; 1850 u8 ipsec_offload[0x1]; 1851 u8 log_max_umem[0x5]; 1852 u8 max_num_eqs[0x10]; 1853 1854 u8 reserved_at_480[0x1]; 1855 u8 tls_tx[0x1]; 1856 u8 tls_rx[0x1]; 1857 u8 log_max_l2_table[0x5]; 1858 u8 reserved_at_488[0x8]; 1859 u8 log_uar_page_sz[0x10]; 1860 1861 u8 reserved_at_4a0[0x20]; 1862 u8 device_frequency_mhz[0x20]; 1863 u8 device_frequency_khz[0x20]; 1864 1865 u8 reserved_at_500[0x20]; 1866 u8 num_of_uars_per_page[0x20]; 1867 1868 u8 flex_parser_protocols[0x20]; 1869 1870 u8 max_geneve_tlv_options[0x8]; 1871 u8 reserved_at_568[0x3]; 1872 u8 max_geneve_tlv_option_data_len[0x5]; 1873 u8 reserved_at_570[0x9]; 1874 u8 adv_virtualization[0x1]; 1875 u8 reserved_at_57a[0x6]; 1876 1877 u8 reserved_at_580[0xb]; 1878 u8 log_max_dci_stream_channels[0x5]; 1879 u8 reserved_at_590[0x3]; 1880 u8 log_max_dci_errored_streams[0x5]; 1881 u8 reserved_at_598[0x8]; 1882 1883 u8 reserved_at_5a0[0x10]; 1884 u8 enhanced_cqe_compression[0x1]; 1885 u8 reserved_at_5b1[0x2]; 1886 u8 log_max_dek[0x5]; 1887 u8 reserved_at_5b8[0x4]; 1888 u8 mini_cqe_resp_stride_index[0x1]; 1889 u8 cqe_128_always[0x1]; 1890 u8 cqe_compression_128[0x1]; 1891 u8 cqe_compression[0x1]; 1892 1893 u8 cqe_compression_timeout[0x10]; 1894 u8 cqe_compression_max_num[0x10]; 1895 1896 u8 reserved_at_5e0[0x8]; 1897 u8 flex_parser_id_gtpu_dw_0[0x4]; 1898 u8 reserved_at_5ec[0x4]; 1899 u8 tag_matching[0x1]; 1900 u8 rndv_offload_rc[0x1]; 1901 u8 rndv_offload_dc[0x1]; 1902 u8 log_tag_matching_list_sz[0x5]; 1903 u8 reserved_at_5f8[0x3]; 1904 u8 log_max_xrq[0x5]; 1905 1906 u8 affiliate_nic_vport_criteria[0x8]; 1907 u8 native_port_num[0x8]; 1908 u8 num_vhca_ports[0x8]; 1909 u8 flex_parser_id_gtpu_teid[0x4]; 1910 u8 reserved_at_61c[0x2]; 1911 u8 sw_owner_id[0x1]; 1912 u8 reserved_at_61f[0x1]; 1913 1914 u8 max_num_of_monitor_counters[0x10]; 1915 u8 num_ppcnt_monitor_counters[0x10]; 1916 1917 u8 max_num_sf[0x10]; 1918 u8 num_q_monitor_counters[0x10]; 1919 1920 u8 reserved_at_660[0x20]; 1921 1922 u8 sf[0x1]; 1923 u8 sf_set_partition[0x1]; 1924 u8 reserved_at_682[0x1]; 1925 u8 log_max_sf[0x5]; 1926 u8 apu[0x1]; 1927 u8 reserved_at_689[0x4]; 1928 u8 migration[0x1]; 1929 u8 reserved_at_68e[0x2]; 1930 u8 log_min_sf_size[0x8]; 1931 u8 max_num_sf_partitions[0x8]; 1932 1933 u8 uctx_cap[0x20]; 1934 1935 u8 reserved_at_6c0[0x4]; 1936 u8 flex_parser_id_geneve_tlv_option_0[0x4]; 1937 u8 flex_parser_id_icmp_dw1[0x4]; 1938 u8 flex_parser_id_icmp_dw0[0x4]; 1939 u8 flex_parser_id_icmpv6_dw1[0x4]; 1940 u8 flex_parser_id_icmpv6_dw0[0x4]; 1941 u8 flex_parser_id_outer_first_mpls_over_gre[0x4]; 1942 u8 flex_parser_id_outer_first_mpls_over_udp_label[0x4]; 1943 1944 u8 max_num_match_definer[0x10]; 1945 u8 sf_base_id[0x10]; 1946 1947 u8 flex_parser_id_gtpu_dw_2[0x4]; 1948 u8 flex_parser_id_gtpu_first_ext_dw_0[0x4]; 1949 u8 num_total_dynamic_vf_msix[0x18]; 1950 u8 reserved_at_720[0x14]; 1951 u8 dynamic_msix_table_size[0xc]; 1952 u8 reserved_at_740[0xc]; 1953 u8 min_dynamic_vf_msix_table_size[0x4]; 1954 u8 reserved_at_750[0x4]; 1955 u8 max_dynamic_vf_msix_table_size[0xc]; 1956 1957 u8 reserved_at_760[0x3]; 1958 u8 log_max_num_header_modify_argument[0x5]; 1959 u8 reserved_at_768[0x4]; 1960 u8 log_header_modify_argument_granularity[0x4]; 1961 u8 reserved_at_770[0x3]; 1962 u8 log_header_modify_argument_max_alloc[0x5]; 1963 u8 reserved_at_778[0x8]; 1964 1965 u8 vhca_tunnel_commands[0x40]; 1966 u8 match_definer_format_supported[0x40]; 1967 }; 1968 1969 enum { 1970 MLX5_CROSS_VHCA_OBJ_TO_OBJ_SUPPORTED_LOCAL_FLOW_TABLE_TO_REMOTE_FLOW_TABLE_MISS = 0x80000, 1971 MLX5_CROSS_VHCA_OBJ_TO_OBJ_SUPPORTED_LOCAL_FLOW_TABLE_ROOT_TO_REMOTE_FLOW_TABLE = (1ULL << 20), 1972 }; 1973 1974 enum { 1975 MLX5_ALLOWED_OBJ_FOR_OTHER_VHCA_ACCESS_FLOW_TABLE = 0x200, 1976 }; 1977 1978 struct mlx5_ifc_cmd_hca_cap_2_bits { 1979 u8 reserved_at_0[0x80]; 1980 1981 u8 migratable[0x1]; 1982 u8 reserved_at_81[0x1f]; 1983 1984 u8 max_reformat_insert_size[0x8]; 1985 u8 max_reformat_insert_offset[0x8]; 1986 u8 max_reformat_remove_size[0x8]; 1987 u8 max_reformat_remove_offset[0x8]; 1988 1989 u8 reserved_at_c0[0x8]; 1990 u8 migration_multi_load[0x1]; 1991 u8 migration_tracking_state[0x1]; 1992 u8 reserved_at_ca[0x6]; 1993 u8 migration_in_chunks[0x1]; 1994 u8 reserved_at_d1[0xf]; 1995 1996 u8 cross_vhca_object_to_object_supported[0x20]; 1997 1998 u8 allowed_object_for_other_vhca_access[0x40]; 1999 2000 u8 reserved_at_140[0x60]; 2001 2002 u8 flow_table_type_2_type[0x8]; 2003 u8 reserved_at_1a8[0x3]; 2004 u8 log_min_mkey_entity_size[0x5]; 2005 u8 reserved_at_1b0[0x10]; 2006 2007 u8 reserved_at_1c0[0x60]; 2008 2009 u8 reserved_at_220[0x1]; 2010 u8 sw_vhca_id_valid[0x1]; 2011 u8 sw_vhca_id[0xe]; 2012 u8 reserved_at_230[0x10]; 2013 2014 u8 reserved_at_240[0xb]; 2015 u8 ts_cqe_metadata_size2wqe_counter[0x5]; 2016 u8 reserved_at_250[0x10]; 2017 2018 u8 reserved_at_260[0x120]; 2019 u8 reserved_at_380[0x10]; 2020 u8 ec_vf_vport_base[0x10]; 2021 2022 u8 reserved_at_3a0[0x10]; 2023 u8 max_rqt_vhca_id[0x10]; 2024 2025 u8 reserved_at_3c0[0x20]; 2026 2027 u8 reserved_at_3e0[0x10]; 2028 u8 pcc_ifa2[0x1]; 2029 u8 reserved_at_3f1[0xf]; 2030 2031 u8 reserved_at_400[0x400]; 2032 }; 2033 2034 enum mlx5_ifc_flow_destination_type { 2035 MLX5_IFC_FLOW_DESTINATION_TYPE_VPORT = 0x0, 2036 MLX5_IFC_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1, 2037 MLX5_IFC_FLOW_DESTINATION_TYPE_TIR = 0x2, 2038 MLX5_IFC_FLOW_DESTINATION_TYPE_FLOW_SAMPLER = 0x6, 2039 MLX5_IFC_FLOW_DESTINATION_TYPE_UPLINK = 0x8, 2040 MLX5_IFC_FLOW_DESTINATION_TYPE_TABLE_TYPE = 0xA, 2041 }; 2042 2043 enum mlx5_flow_table_miss_action { 2044 MLX5_FLOW_TABLE_MISS_ACTION_DEF, 2045 MLX5_FLOW_TABLE_MISS_ACTION_FWD, 2046 MLX5_FLOW_TABLE_MISS_ACTION_SWITCH_DOMAIN, 2047 }; 2048 2049 struct mlx5_ifc_dest_format_struct_bits { 2050 u8 destination_type[0x8]; 2051 u8 destination_id[0x18]; 2052 2053 u8 destination_eswitch_owner_vhca_id_valid[0x1]; 2054 u8 packet_reformat[0x1]; 2055 u8 reserved_at_22[0x6]; 2056 u8 destination_table_type[0x8]; 2057 u8 destination_eswitch_owner_vhca_id[0x10]; 2058 }; 2059 2060 struct mlx5_ifc_flow_counter_list_bits { 2061 u8 flow_counter_id[0x20]; 2062 2063 u8 reserved_at_20[0x20]; 2064 }; 2065 2066 struct mlx5_ifc_extended_dest_format_bits { 2067 struct mlx5_ifc_dest_format_struct_bits destination_entry; 2068 2069 u8 packet_reformat_id[0x20]; 2070 2071 u8 reserved_at_60[0x20]; 2072 }; 2073 2074 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits { 2075 struct mlx5_ifc_extended_dest_format_bits extended_dest_format; 2076 struct mlx5_ifc_flow_counter_list_bits flow_counter_list; 2077 }; 2078 2079 struct mlx5_ifc_fte_match_param_bits { 2080 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers; 2081 2082 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters; 2083 2084 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers; 2085 2086 struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2; 2087 2088 struct mlx5_ifc_fte_match_set_misc3_bits misc_parameters_3; 2089 2090 struct mlx5_ifc_fte_match_set_misc4_bits misc_parameters_4; 2091 2092 struct mlx5_ifc_fte_match_set_misc5_bits misc_parameters_5; 2093 2094 u8 reserved_at_e00[0x200]; 2095 }; 2096 2097 enum { 2098 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0, 2099 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1, 2100 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2, 2101 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3, 2102 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4, 2103 }; 2104 2105 struct mlx5_ifc_rx_hash_field_select_bits { 2106 u8 l3_prot_type[0x1]; 2107 u8 l4_prot_type[0x1]; 2108 u8 selected_fields[0x1e]; 2109 }; 2110 2111 enum { 2112 MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0, 2113 MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1, 2114 }; 2115 2116 enum { 2117 MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0, 2118 MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1, 2119 }; 2120 2121 struct mlx5_ifc_wq_bits { 2122 u8 wq_type[0x4]; 2123 u8 wq_signature[0x1]; 2124 u8 end_padding_mode[0x2]; 2125 u8 cd_slave[0x1]; 2126 u8 reserved_at_8[0x18]; 2127 2128 u8 hds_skip_first_sge[0x1]; 2129 u8 log2_hds_buf_size[0x3]; 2130 u8 reserved_at_24[0x7]; 2131 u8 page_offset[0x5]; 2132 u8 lwm[0x10]; 2133 2134 u8 reserved_at_40[0x8]; 2135 u8 pd[0x18]; 2136 2137 u8 reserved_at_60[0x8]; 2138 u8 uar_page[0x18]; 2139 2140 u8 dbr_addr[0x40]; 2141 2142 u8 hw_counter[0x20]; 2143 2144 u8 sw_counter[0x20]; 2145 2146 u8 reserved_at_100[0xc]; 2147 u8 log_wq_stride[0x4]; 2148 u8 reserved_at_110[0x3]; 2149 u8 log_wq_pg_sz[0x5]; 2150 u8 reserved_at_118[0x3]; 2151 u8 log_wq_sz[0x5]; 2152 2153 u8 dbr_umem_valid[0x1]; 2154 u8 wq_umem_valid[0x1]; 2155 u8 reserved_at_122[0x1]; 2156 u8 log_hairpin_num_packets[0x5]; 2157 u8 reserved_at_128[0x3]; 2158 u8 log_hairpin_data_sz[0x5]; 2159 2160 u8 reserved_at_130[0x4]; 2161 u8 log_wqe_num_of_strides[0x4]; 2162 u8 two_byte_shift_en[0x1]; 2163 u8 reserved_at_139[0x4]; 2164 u8 log_wqe_stride_size[0x3]; 2165 2166 u8 reserved_at_140[0x80]; 2167 2168 u8 headers_mkey[0x20]; 2169 2170 u8 shampo_enable[0x1]; 2171 u8 reserved_at_1e1[0x4]; 2172 u8 log_reservation_size[0x3]; 2173 u8 reserved_at_1e8[0x5]; 2174 u8 log_max_num_of_packets_per_reservation[0x3]; 2175 u8 reserved_at_1f0[0x6]; 2176 u8 log_headers_entry_size[0x2]; 2177 u8 reserved_at_1f8[0x4]; 2178 u8 log_headers_buffer_entry_num[0x4]; 2179 2180 u8 reserved_at_200[0x400]; 2181 2182 struct mlx5_ifc_cmd_pas_bits pas[]; 2183 }; 2184 2185 struct mlx5_ifc_rq_num_bits { 2186 u8 reserved_at_0[0x8]; 2187 u8 rq_num[0x18]; 2188 }; 2189 2190 struct mlx5_ifc_rq_vhca_bits { 2191 u8 reserved_at_0[0x8]; 2192 u8 rq_num[0x18]; 2193 u8 reserved_at_20[0x10]; 2194 u8 rq_vhca_id[0x10]; 2195 }; 2196 2197 struct mlx5_ifc_mac_address_layout_bits { 2198 u8 reserved_at_0[0x10]; 2199 u8 mac_addr_47_32[0x10]; 2200 2201 u8 mac_addr_31_0[0x20]; 2202 }; 2203 2204 struct mlx5_ifc_vlan_layout_bits { 2205 u8 reserved_at_0[0x14]; 2206 u8 vlan[0x0c]; 2207 2208 u8 reserved_at_20[0x20]; 2209 }; 2210 2211 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits { 2212 u8 reserved_at_0[0xa0]; 2213 2214 u8 min_time_between_cnps[0x20]; 2215 2216 u8 reserved_at_c0[0x12]; 2217 u8 cnp_dscp[0x6]; 2218 u8 reserved_at_d8[0x4]; 2219 u8 cnp_prio_mode[0x1]; 2220 u8 cnp_802p_prio[0x3]; 2221 2222 u8 reserved_at_e0[0x720]; 2223 }; 2224 2225 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits { 2226 u8 reserved_at_0[0x60]; 2227 2228 u8 reserved_at_60[0x4]; 2229 u8 clamp_tgt_rate[0x1]; 2230 u8 reserved_at_65[0x3]; 2231 u8 clamp_tgt_rate_after_time_inc[0x1]; 2232 u8 reserved_at_69[0x17]; 2233 2234 u8 reserved_at_80[0x20]; 2235 2236 u8 rpg_time_reset[0x20]; 2237 2238 u8 rpg_byte_reset[0x20]; 2239 2240 u8 rpg_threshold[0x20]; 2241 2242 u8 rpg_max_rate[0x20]; 2243 2244 u8 rpg_ai_rate[0x20]; 2245 2246 u8 rpg_hai_rate[0x20]; 2247 2248 u8 rpg_gd[0x20]; 2249 2250 u8 rpg_min_dec_fac[0x20]; 2251 2252 u8 rpg_min_rate[0x20]; 2253 2254 u8 reserved_at_1c0[0xe0]; 2255 2256 u8 rate_to_set_on_first_cnp[0x20]; 2257 2258 u8 dce_tcp_g[0x20]; 2259 2260 u8 dce_tcp_rtt[0x20]; 2261 2262 u8 rate_reduce_monitor_period[0x20]; 2263 2264 u8 reserved_at_320[0x20]; 2265 2266 u8 initial_alpha_value[0x20]; 2267 2268 u8 reserved_at_360[0x4a0]; 2269 }; 2270 2271 struct mlx5_ifc_cong_control_r_roce_general_bits { 2272 u8 reserved_at_0[0x80]; 2273 2274 u8 reserved_at_80[0x10]; 2275 u8 rtt_resp_dscp_valid[0x1]; 2276 u8 reserved_at_91[0x9]; 2277 u8 rtt_resp_dscp[0x6]; 2278 2279 u8 reserved_at_a0[0x760]; 2280 }; 2281 2282 struct mlx5_ifc_cong_control_802_1qau_rp_bits { 2283 u8 reserved_at_0[0x80]; 2284 2285 u8 rppp_max_rps[0x20]; 2286 2287 u8 rpg_time_reset[0x20]; 2288 2289 u8 rpg_byte_reset[0x20]; 2290 2291 u8 rpg_threshold[0x20]; 2292 2293 u8 rpg_max_rate[0x20]; 2294 2295 u8 rpg_ai_rate[0x20]; 2296 2297 u8 rpg_hai_rate[0x20]; 2298 2299 u8 rpg_gd[0x20]; 2300 2301 u8 rpg_min_dec_fac[0x20]; 2302 2303 u8 rpg_min_rate[0x20]; 2304 2305 u8 reserved_at_1c0[0x640]; 2306 }; 2307 2308 enum { 2309 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1, 2310 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2, 2311 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4, 2312 }; 2313 2314 struct mlx5_ifc_resize_field_select_bits { 2315 u8 resize_field_select[0x20]; 2316 }; 2317 2318 struct mlx5_ifc_resource_dump_bits { 2319 u8 more_dump[0x1]; 2320 u8 inline_dump[0x1]; 2321 u8 reserved_at_2[0xa]; 2322 u8 seq_num[0x4]; 2323 u8 segment_type[0x10]; 2324 2325 u8 reserved_at_20[0x10]; 2326 u8 vhca_id[0x10]; 2327 2328 u8 index1[0x20]; 2329 2330 u8 index2[0x20]; 2331 2332 u8 num_of_obj1[0x10]; 2333 u8 num_of_obj2[0x10]; 2334 2335 u8 reserved_at_a0[0x20]; 2336 2337 u8 device_opaque[0x40]; 2338 2339 u8 mkey[0x20]; 2340 2341 u8 size[0x20]; 2342 2343 u8 address[0x40]; 2344 2345 u8 inline_data[52][0x20]; 2346 }; 2347 2348 struct mlx5_ifc_resource_dump_menu_record_bits { 2349 u8 reserved_at_0[0x4]; 2350 u8 num_of_obj2_supports_active[0x1]; 2351 u8 num_of_obj2_supports_all[0x1]; 2352 u8 must_have_num_of_obj2[0x1]; 2353 u8 support_num_of_obj2[0x1]; 2354 u8 num_of_obj1_supports_active[0x1]; 2355 u8 num_of_obj1_supports_all[0x1]; 2356 u8 must_have_num_of_obj1[0x1]; 2357 u8 support_num_of_obj1[0x1]; 2358 u8 must_have_index2[0x1]; 2359 u8 support_index2[0x1]; 2360 u8 must_have_index1[0x1]; 2361 u8 support_index1[0x1]; 2362 u8 segment_type[0x10]; 2363 2364 u8 segment_name[4][0x20]; 2365 2366 u8 index1_name[4][0x20]; 2367 2368 u8 index2_name[4][0x20]; 2369 }; 2370 2371 struct mlx5_ifc_resource_dump_segment_header_bits { 2372 u8 length_dw[0x10]; 2373 u8 segment_type[0x10]; 2374 }; 2375 2376 struct mlx5_ifc_resource_dump_command_segment_bits { 2377 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2378 2379 u8 segment_called[0x10]; 2380 u8 vhca_id[0x10]; 2381 2382 u8 index1[0x20]; 2383 2384 u8 index2[0x20]; 2385 2386 u8 num_of_obj1[0x10]; 2387 u8 num_of_obj2[0x10]; 2388 }; 2389 2390 struct mlx5_ifc_resource_dump_error_segment_bits { 2391 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2392 2393 u8 reserved_at_20[0x10]; 2394 u8 syndrome_id[0x10]; 2395 2396 u8 reserved_at_40[0x40]; 2397 2398 u8 error[8][0x20]; 2399 }; 2400 2401 struct mlx5_ifc_resource_dump_info_segment_bits { 2402 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2403 2404 u8 reserved_at_20[0x18]; 2405 u8 dump_version[0x8]; 2406 2407 u8 hw_version[0x20]; 2408 2409 u8 fw_version[0x20]; 2410 }; 2411 2412 struct mlx5_ifc_resource_dump_menu_segment_bits { 2413 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2414 2415 u8 reserved_at_20[0x10]; 2416 u8 num_of_records[0x10]; 2417 2418 struct mlx5_ifc_resource_dump_menu_record_bits record[]; 2419 }; 2420 2421 struct mlx5_ifc_resource_dump_resource_segment_bits { 2422 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2423 2424 u8 reserved_at_20[0x20]; 2425 2426 u8 index1[0x20]; 2427 2428 u8 index2[0x20]; 2429 2430 u8 payload[][0x20]; 2431 }; 2432 2433 struct mlx5_ifc_resource_dump_terminate_segment_bits { 2434 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2435 }; 2436 2437 struct mlx5_ifc_menu_resource_dump_response_bits { 2438 struct mlx5_ifc_resource_dump_info_segment_bits info; 2439 struct mlx5_ifc_resource_dump_command_segment_bits cmd; 2440 struct mlx5_ifc_resource_dump_menu_segment_bits menu; 2441 struct mlx5_ifc_resource_dump_terminate_segment_bits terminate; 2442 }; 2443 2444 enum { 2445 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1, 2446 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2, 2447 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4, 2448 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8, 2449 }; 2450 2451 struct mlx5_ifc_modify_field_select_bits { 2452 u8 modify_field_select[0x20]; 2453 }; 2454 2455 struct mlx5_ifc_field_select_r_roce_np_bits { 2456 u8 field_select_r_roce_np[0x20]; 2457 }; 2458 2459 struct mlx5_ifc_field_select_r_roce_rp_bits { 2460 u8 field_select_r_roce_rp[0x20]; 2461 }; 2462 2463 enum { 2464 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4, 2465 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8, 2466 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10, 2467 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20, 2468 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40, 2469 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80, 2470 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100, 2471 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200, 2472 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400, 2473 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800, 2474 }; 2475 2476 struct mlx5_ifc_field_select_802_1qau_rp_bits { 2477 u8 field_select_8021qaurp[0x20]; 2478 }; 2479 2480 struct mlx5_ifc_phys_layer_cntrs_bits { 2481 u8 time_since_last_clear_high[0x20]; 2482 2483 u8 time_since_last_clear_low[0x20]; 2484 2485 u8 symbol_errors_high[0x20]; 2486 2487 u8 symbol_errors_low[0x20]; 2488 2489 u8 sync_headers_errors_high[0x20]; 2490 2491 u8 sync_headers_errors_low[0x20]; 2492 2493 u8 edpl_bip_errors_lane0_high[0x20]; 2494 2495 u8 edpl_bip_errors_lane0_low[0x20]; 2496 2497 u8 edpl_bip_errors_lane1_high[0x20]; 2498 2499 u8 edpl_bip_errors_lane1_low[0x20]; 2500 2501 u8 edpl_bip_errors_lane2_high[0x20]; 2502 2503 u8 edpl_bip_errors_lane2_low[0x20]; 2504 2505 u8 edpl_bip_errors_lane3_high[0x20]; 2506 2507 u8 edpl_bip_errors_lane3_low[0x20]; 2508 2509 u8 fc_fec_corrected_blocks_lane0_high[0x20]; 2510 2511 u8 fc_fec_corrected_blocks_lane0_low[0x20]; 2512 2513 u8 fc_fec_corrected_blocks_lane1_high[0x20]; 2514 2515 u8 fc_fec_corrected_blocks_lane1_low[0x20]; 2516 2517 u8 fc_fec_corrected_blocks_lane2_high[0x20]; 2518 2519 u8 fc_fec_corrected_blocks_lane2_low[0x20]; 2520 2521 u8 fc_fec_corrected_blocks_lane3_high[0x20]; 2522 2523 u8 fc_fec_corrected_blocks_lane3_low[0x20]; 2524 2525 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20]; 2526 2527 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20]; 2528 2529 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20]; 2530 2531 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20]; 2532 2533 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20]; 2534 2535 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20]; 2536 2537 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20]; 2538 2539 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20]; 2540 2541 u8 rs_fec_corrected_blocks_high[0x20]; 2542 2543 u8 rs_fec_corrected_blocks_low[0x20]; 2544 2545 u8 rs_fec_uncorrectable_blocks_high[0x20]; 2546 2547 u8 rs_fec_uncorrectable_blocks_low[0x20]; 2548 2549 u8 rs_fec_no_errors_blocks_high[0x20]; 2550 2551 u8 rs_fec_no_errors_blocks_low[0x20]; 2552 2553 u8 rs_fec_single_error_blocks_high[0x20]; 2554 2555 u8 rs_fec_single_error_blocks_low[0x20]; 2556 2557 u8 rs_fec_corrected_symbols_total_high[0x20]; 2558 2559 u8 rs_fec_corrected_symbols_total_low[0x20]; 2560 2561 u8 rs_fec_corrected_symbols_lane0_high[0x20]; 2562 2563 u8 rs_fec_corrected_symbols_lane0_low[0x20]; 2564 2565 u8 rs_fec_corrected_symbols_lane1_high[0x20]; 2566 2567 u8 rs_fec_corrected_symbols_lane1_low[0x20]; 2568 2569 u8 rs_fec_corrected_symbols_lane2_high[0x20]; 2570 2571 u8 rs_fec_corrected_symbols_lane2_low[0x20]; 2572 2573 u8 rs_fec_corrected_symbols_lane3_high[0x20]; 2574 2575 u8 rs_fec_corrected_symbols_lane3_low[0x20]; 2576 2577 u8 link_down_events[0x20]; 2578 2579 u8 successful_recovery_events[0x20]; 2580 2581 u8 reserved_at_640[0x180]; 2582 }; 2583 2584 struct mlx5_ifc_phys_layer_statistical_cntrs_bits { 2585 u8 time_since_last_clear_high[0x20]; 2586 2587 u8 time_since_last_clear_low[0x20]; 2588 2589 u8 phy_received_bits_high[0x20]; 2590 2591 u8 phy_received_bits_low[0x20]; 2592 2593 u8 phy_symbol_errors_high[0x20]; 2594 2595 u8 phy_symbol_errors_low[0x20]; 2596 2597 u8 phy_corrected_bits_high[0x20]; 2598 2599 u8 phy_corrected_bits_low[0x20]; 2600 2601 u8 phy_corrected_bits_lane0_high[0x20]; 2602 2603 u8 phy_corrected_bits_lane0_low[0x20]; 2604 2605 u8 phy_corrected_bits_lane1_high[0x20]; 2606 2607 u8 phy_corrected_bits_lane1_low[0x20]; 2608 2609 u8 phy_corrected_bits_lane2_high[0x20]; 2610 2611 u8 phy_corrected_bits_lane2_low[0x20]; 2612 2613 u8 phy_corrected_bits_lane3_high[0x20]; 2614 2615 u8 phy_corrected_bits_lane3_low[0x20]; 2616 2617 u8 reserved_at_200[0x5c0]; 2618 }; 2619 2620 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits { 2621 u8 symbol_error_counter[0x10]; 2622 2623 u8 link_error_recovery_counter[0x8]; 2624 2625 u8 link_downed_counter[0x8]; 2626 2627 u8 port_rcv_errors[0x10]; 2628 2629 u8 port_rcv_remote_physical_errors[0x10]; 2630 2631 u8 port_rcv_switch_relay_errors[0x10]; 2632 2633 u8 port_xmit_discards[0x10]; 2634 2635 u8 port_xmit_constraint_errors[0x8]; 2636 2637 u8 port_rcv_constraint_errors[0x8]; 2638 2639 u8 reserved_at_70[0x8]; 2640 2641 u8 link_overrun_errors[0x8]; 2642 2643 u8 reserved_at_80[0x10]; 2644 2645 u8 vl_15_dropped[0x10]; 2646 2647 u8 reserved_at_a0[0x80]; 2648 2649 u8 port_xmit_wait[0x20]; 2650 }; 2651 2652 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits { 2653 u8 transmit_queue_high[0x20]; 2654 2655 u8 transmit_queue_low[0x20]; 2656 2657 u8 no_buffer_discard_uc_high[0x20]; 2658 2659 u8 no_buffer_discard_uc_low[0x20]; 2660 2661 u8 reserved_at_80[0x740]; 2662 }; 2663 2664 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits { 2665 u8 wred_discard_high[0x20]; 2666 2667 u8 wred_discard_low[0x20]; 2668 2669 u8 ecn_marked_tc_high[0x20]; 2670 2671 u8 ecn_marked_tc_low[0x20]; 2672 2673 u8 reserved_at_80[0x740]; 2674 }; 2675 2676 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits { 2677 u8 rx_octets_high[0x20]; 2678 2679 u8 rx_octets_low[0x20]; 2680 2681 u8 reserved_at_40[0xc0]; 2682 2683 u8 rx_frames_high[0x20]; 2684 2685 u8 rx_frames_low[0x20]; 2686 2687 u8 tx_octets_high[0x20]; 2688 2689 u8 tx_octets_low[0x20]; 2690 2691 u8 reserved_at_180[0xc0]; 2692 2693 u8 tx_frames_high[0x20]; 2694 2695 u8 tx_frames_low[0x20]; 2696 2697 u8 rx_pause_high[0x20]; 2698 2699 u8 rx_pause_low[0x20]; 2700 2701 u8 rx_pause_duration_high[0x20]; 2702 2703 u8 rx_pause_duration_low[0x20]; 2704 2705 u8 tx_pause_high[0x20]; 2706 2707 u8 tx_pause_low[0x20]; 2708 2709 u8 tx_pause_duration_high[0x20]; 2710 2711 u8 tx_pause_duration_low[0x20]; 2712 2713 u8 rx_pause_transition_high[0x20]; 2714 2715 u8 rx_pause_transition_low[0x20]; 2716 2717 u8 rx_discards_high[0x20]; 2718 2719 u8 rx_discards_low[0x20]; 2720 2721 u8 device_stall_minor_watermark_cnt_high[0x20]; 2722 2723 u8 device_stall_minor_watermark_cnt_low[0x20]; 2724 2725 u8 device_stall_critical_watermark_cnt_high[0x20]; 2726 2727 u8 device_stall_critical_watermark_cnt_low[0x20]; 2728 2729 u8 reserved_at_480[0x340]; 2730 }; 2731 2732 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits { 2733 u8 port_transmit_wait_high[0x20]; 2734 2735 u8 port_transmit_wait_low[0x20]; 2736 2737 u8 reserved_at_40[0x100]; 2738 2739 u8 rx_buffer_almost_full_high[0x20]; 2740 2741 u8 rx_buffer_almost_full_low[0x20]; 2742 2743 u8 rx_buffer_full_high[0x20]; 2744 2745 u8 rx_buffer_full_low[0x20]; 2746 2747 u8 rx_icrc_encapsulated_high[0x20]; 2748 2749 u8 rx_icrc_encapsulated_low[0x20]; 2750 2751 u8 reserved_at_200[0x5c0]; 2752 }; 2753 2754 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits { 2755 u8 dot3stats_alignment_errors_high[0x20]; 2756 2757 u8 dot3stats_alignment_errors_low[0x20]; 2758 2759 u8 dot3stats_fcs_errors_high[0x20]; 2760 2761 u8 dot3stats_fcs_errors_low[0x20]; 2762 2763 u8 dot3stats_single_collision_frames_high[0x20]; 2764 2765 u8 dot3stats_single_collision_frames_low[0x20]; 2766 2767 u8 dot3stats_multiple_collision_frames_high[0x20]; 2768 2769 u8 dot3stats_multiple_collision_frames_low[0x20]; 2770 2771 u8 dot3stats_sqe_test_errors_high[0x20]; 2772 2773 u8 dot3stats_sqe_test_errors_low[0x20]; 2774 2775 u8 dot3stats_deferred_transmissions_high[0x20]; 2776 2777 u8 dot3stats_deferred_transmissions_low[0x20]; 2778 2779 u8 dot3stats_late_collisions_high[0x20]; 2780 2781 u8 dot3stats_late_collisions_low[0x20]; 2782 2783 u8 dot3stats_excessive_collisions_high[0x20]; 2784 2785 u8 dot3stats_excessive_collisions_low[0x20]; 2786 2787 u8 dot3stats_internal_mac_transmit_errors_high[0x20]; 2788 2789 u8 dot3stats_internal_mac_transmit_errors_low[0x20]; 2790 2791 u8 dot3stats_carrier_sense_errors_high[0x20]; 2792 2793 u8 dot3stats_carrier_sense_errors_low[0x20]; 2794 2795 u8 dot3stats_frame_too_longs_high[0x20]; 2796 2797 u8 dot3stats_frame_too_longs_low[0x20]; 2798 2799 u8 dot3stats_internal_mac_receive_errors_high[0x20]; 2800 2801 u8 dot3stats_internal_mac_receive_errors_low[0x20]; 2802 2803 u8 dot3stats_symbol_errors_high[0x20]; 2804 2805 u8 dot3stats_symbol_errors_low[0x20]; 2806 2807 u8 dot3control_in_unknown_opcodes_high[0x20]; 2808 2809 u8 dot3control_in_unknown_opcodes_low[0x20]; 2810 2811 u8 dot3in_pause_frames_high[0x20]; 2812 2813 u8 dot3in_pause_frames_low[0x20]; 2814 2815 u8 dot3out_pause_frames_high[0x20]; 2816 2817 u8 dot3out_pause_frames_low[0x20]; 2818 2819 u8 reserved_at_400[0x3c0]; 2820 }; 2821 2822 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits { 2823 u8 ether_stats_drop_events_high[0x20]; 2824 2825 u8 ether_stats_drop_events_low[0x20]; 2826 2827 u8 ether_stats_octets_high[0x20]; 2828 2829 u8 ether_stats_octets_low[0x20]; 2830 2831 u8 ether_stats_pkts_high[0x20]; 2832 2833 u8 ether_stats_pkts_low[0x20]; 2834 2835 u8 ether_stats_broadcast_pkts_high[0x20]; 2836 2837 u8 ether_stats_broadcast_pkts_low[0x20]; 2838 2839 u8 ether_stats_multicast_pkts_high[0x20]; 2840 2841 u8 ether_stats_multicast_pkts_low[0x20]; 2842 2843 u8 ether_stats_crc_align_errors_high[0x20]; 2844 2845 u8 ether_stats_crc_align_errors_low[0x20]; 2846 2847 u8 ether_stats_undersize_pkts_high[0x20]; 2848 2849 u8 ether_stats_undersize_pkts_low[0x20]; 2850 2851 u8 ether_stats_oversize_pkts_high[0x20]; 2852 2853 u8 ether_stats_oversize_pkts_low[0x20]; 2854 2855 u8 ether_stats_fragments_high[0x20]; 2856 2857 u8 ether_stats_fragments_low[0x20]; 2858 2859 u8 ether_stats_jabbers_high[0x20]; 2860 2861 u8 ether_stats_jabbers_low[0x20]; 2862 2863 u8 ether_stats_collisions_high[0x20]; 2864 2865 u8 ether_stats_collisions_low[0x20]; 2866 2867 u8 ether_stats_pkts64octets_high[0x20]; 2868 2869 u8 ether_stats_pkts64octets_low[0x20]; 2870 2871 u8 ether_stats_pkts65to127octets_high[0x20]; 2872 2873 u8 ether_stats_pkts65to127octets_low[0x20]; 2874 2875 u8 ether_stats_pkts128to255octets_high[0x20]; 2876 2877 u8 ether_stats_pkts128to255octets_low[0x20]; 2878 2879 u8 ether_stats_pkts256to511octets_high[0x20]; 2880 2881 u8 ether_stats_pkts256to511octets_low[0x20]; 2882 2883 u8 ether_stats_pkts512to1023octets_high[0x20]; 2884 2885 u8 ether_stats_pkts512to1023octets_low[0x20]; 2886 2887 u8 ether_stats_pkts1024to1518octets_high[0x20]; 2888 2889 u8 ether_stats_pkts1024to1518octets_low[0x20]; 2890 2891 u8 ether_stats_pkts1519to2047octets_high[0x20]; 2892 2893 u8 ether_stats_pkts1519to2047octets_low[0x20]; 2894 2895 u8 ether_stats_pkts2048to4095octets_high[0x20]; 2896 2897 u8 ether_stats_pkts2048to4095octets_low[0x20]; 2898 2899 u8 ether_stats_pkts4096to8191octets_high[0x20]; 2900 2901 u8 ether_stats_pkts4096to8191octets_low[0x20]; 2902 2903 u8 ether_stats_pkts8192to10239octets_high[0x20]; 2904 2905 u8 ether_stats_pkts8192to10239octets_low[0x20]; 2906 2907 u8 reserved_at_540[0x280]; 2908 }; 2909 2910 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits { 2911 u8 if_in_octets_high[0x20]; 2912 2913 u8 if_in_octets_low[0x20]; 2914 2915 u8 if_in_ucast_pkts_high[0x20]; 2916 2917 u8 if_in_ucast_pkts_low[0x20]; 2918 2919 u8 if_in_discards_high[0x20]; 2920 2921 u8 if_in_discards_low[0x20]; 2922 2923 u8 if_in_errors_high[0x20]; 2924 2925 u8 if_in_errors_low[0x20]; 2926 2927 u8 if_in_unknown_protos_high[0x20]; 2928 2929 u8 if_in_unknown_protos_low[0x20]; 2930 2931 u8 if_out_octets_high[0x20]; 2932 2933 u8 if_out_octets_low[0x20]; 2934 2935 u8 if_out_ucast_pkts_high[0x20]; 2936 2937 u8 if_out_ucast_pkts_low[0x20]; 2938 2939 u8 if_out_discards_high[0x20]; 2940 2941 u8 if_out_discards_low[0x20]; 2942 2943 u8 if_out_errors_high[0x20]; 2944 2945 u8 if_out_errors_low[0x20]; 2946 2947 u8 if_in_multicast_pkts_high[0x20]; 2948 2949 u8 if_in_multicast_pkts_low[0x20]; 2950 2951 u8 if_in_broadcast_pkts_high[0x20]; 2952 2953 u8 if_in_broadcast_pkts_low[0x20]; 2954 2955 u8 if_out_multicast_pkts_high[0x20]; 2956 2957 u8 if_out_multicast_pkts_low[0x20]; 2958 2959 u8 if_out_broadcast_pkts_high[0x20]; 2960 2961 u8 if_out_broadcast_pkts_low[0x20]; 2962 2963 u8 reserved_at_340[0x480]; 2964 }; 2965 2966 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits { 2967 u8 a_frames_transmitted_ok_high[0x20]; 2968 2969 u8 a_frames_transmitted_ok_low[0x20]; 2970 2971 u8 a_frames_received_ok_high[0x20]; 2972 2973 u8 a_frames_received_ok_low[0x20]; 2974 2975 u8 a_frame_check_sequence_errors_high[0x20]; 2976 2977 u8 a_frame_check_sequence_errors_low[0x20]; 2978 2979 u8 a_alignment_errors_high[0x20]; 2980 2981 u8 a_alignment_errors_low[0x20]; 2982 2983 u8 a_octets_transmitted_ok_high[0x20]; 2984 2985 u8 a_octets_transmitted_ok_low[0x20]; 2986 2987 u8 a_octets_received_ok_high[0x20]; 2988 2989 u8 a_octets_received_ok_low[0x20]; 2990 2991 u8 a_multicast_frames_xmitted_ok_high[0x20]; 2992 2993 u8 a_multicast_frames_xmitted_ok_low[0x20]; 2994 2995 u8 a_broadcast_frames_xmitted_ok_high[0x20]; 2996 2997 u8 a_broadcast_frames_xmitted_ok_low[0x20]; 2998 2999 u8 a_multicast_frames_received_ok_high[0x20]; 3000 3001 u8 a_multicast_frames_received_ok_low[0x20]; 3002 3003 u8 a_broadcast_frames_received_ok_high[0x20]; 3004 3005 u8 a_broadcast_frames_received_ok_low[0x20]; 3006 3007 u8 a_in_range_length_errors_high[0x20]; 3008 3009 u8 a_in_range_length_errors_low[0x20]; 3010 3011 u8 a_out_of_range_length_field_high[0x20]; 3012 3013 u8 a_out_of_range_length_field_low[0x20]; 3014 3015 u8 a_frame_too_long_errors_high[0x20]; 3016 3017 u8 a_frame_too_long_errors_low[0x20]; 3018 3019 u8 a_symbol_error_during_carrier_high[0x20]; 3020 3021 u8 a_symbol_error_during_carrier_low[0x20]; 3022 3023 u8 a_mac_control_frames_transmitted_high[0x20]; 3024 3025 u8 a_mac_control_frames_transmitted_low[0x20]; 3026 3027 u8 a_mac_control_frames_received_high[0x20]; 3028 3029 u8 a_mac_control_frames_received_low[0x20]; 3030 3031 u8 a_unsupported_opcodes_received_high[0x20]; 3032 3033 u8 a_unsupported_opcodes_received_low[0x20]; 3034 3035 u8 a_pause_mac_ctrl_frames_received_high[0x20]; 3036 3037 u8 a_pause_mac_ctrl_frames_received_low[0x20]; 3038 3039 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20]; 3040 3041 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20]; 3042 3043 u8 reserved_at_4c0[0x300]; 3044 }; 3045 3046 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits { 3047 u8 life_time_counter_high[0x20]; 3048 3049 u8 life_time_counter_low[0x20]; 3050 3051 u8 rx_errors[0x20]; 3052 3053 u8 tx_errors[0x20]; 3054 3055 u8 l0_to_recovery_eieos[0x20]; 3056 3057 u8 l0_to_recovery_ts[0x20]; 3058 3059 u8 l0_to_recovery_framing[0x20]; 3060 3061 u8 l0_to_recovery_retrain[0x20]; 3062 3063 u8 crc_error_dllp[0x20]; 3064 3065 u8 crc_error_tlp[0x20]; 3066 3067 u8 tx_overflow_buffer_pkt_high[0x20]; 3068 3069 u8 tx_overflow_buffer_pkt_low[0x20]; 3070 3071 u8 outbound_stalled_reads[0x20]; 3072 3073 u8 outbound_stalled_writes[0x20]; 3074 3075 u8 outbound_stalled_reads_events[0x20]; 3076 3077 u8 outbound_stalled_writes_events[0x20]; 3078 3079 u8 reserved_at_200[0x5c0]; 3080 }; 3081 3082 struct mlx5_ifc_cmd_inter_comp_event_bits { 3083 u8 command_completion_vector[0x20]; 3084 3085 u8 reserved_at_20[0xc0]; 3086 }; 3087 3088 struct mlx5_ifc_stall_vl_event_bits { 3089 u8 reserved_at_0[0x18]; 3090 u8 port_num[0x1]; 3091 u8 reserved_at_19[0x3]; 3092 u8 vl[0x4]; 3093 3094 u8 reserved_at_20[0xa0]; 3095 }; 3096 3097 struct mlx5_ifc_db_bf_congestion_event_bits { 3098 u8 event_subtype[0x8]; 3099 u8 reserved_at_8[0x8]; 3100 u8 congestion_level[0x8]; 3101 u8 reserved_at_18[0x8]; 3102 3103 u8 reserved_at_20[0xa0]; 3104 }; 3105 3106 struct mlx5_ifc_gpio_event_bits { 3107 u8 reserved_at_0[0x60]; 3108 3109 u8 gpio_event_hi[0x20]; 3110 3111 u8 gpio_event_lo[0x20]; 3112 3113 u8 reserved_at_a0[0x40]; 3114 }; 3115 3116 struct mlx5_ifc_port_state_change_event_bits { 3117 u8 reserved_at_0[0x40]; 3118 3119 u8 port_num[0x4]; 3120 u8 reserved_at_44[0x1c]; 3121 3122 u8 reserved_at_60[0x80]; 3123 }; 3124 3125 struct mlx5_ifc_dropped_packet_logged_bits { 3126 u8 reserved_at_0[0xe0]; 3127 }; 3128 3129 struct mlx5_ifc_default_timeout_bits { 3130 u8 to_multiplier[0x3]; 3131 u8 reserved_at_3[0x9]; 3132 u8 to_value[0x14]; 3133 }; 3134 3135 struct mlx5_ifc_dtor_reg_bits { 3136 u8 reserved_at_0[0x20]; 3137 3138 struct mlx5_ifc_default_timeout_bits pcie_toggle_to; 3139 3140 u8 reserved_at_40[0x60]; 3141 3142 struct mlx5_ifc_default_timeout_bits health_poll_to; 3143 3144 struct mlx5_ifc_default_timeout_bits full_crdump_to; 3145 3146 struct mlx5_ifc_default_timeout_bits fw_reset_to; 3147 3148 struct mlx5_ifc_default_timeout_bits flush_on_err_to; 3149 3150 struct mlx5_ifc_default_timeout_bits pci_sync_update_to; 3151 3152 struct mlx5_ifc_default_timeout_bits tear_down_to; 3153 3154 struct mlx5_ifc_default_timeout_bits fsm_reactivate_to; 3155 3156 struct mlx5_ifc_default_timeout_bits reclaim_pages_to; 3157 3158 struct mlx5_ifc_default_timeout_bits reclaim_vfs_pages_to; 3159 3160 struct mlx5_ifc_default_timeout_bits reset_unload_to; 3161 3162 u8 reserved_at_1c0[0x20]; 3163 }; 3164 3165 enum { 3166 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1, 3167 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2, 3168 }; 3169 3170 struct mlx5_ifc_cq_error_bits { 3171 u8 reserved_at_0[0x8]; 3172 u8 cqn[0x18]; 3173 3174 u8 reserved_at_20[0x20]; 3175 3176 u8 reserved_at_40[0x18]; 3177 u8 syndrome[0x8]; 3178 3179 u8 reserved_at_60[0x80]; 3180 }; 3181 3182 struct mlx5_ifc_rdma_page_fault_event_bits { 3183 u8 bytes_committed[0x20]; 3184 3185 u8 r_key[0x20]; 3186 3187 u8 reserved_at_40[0x10]; 3188 u8 packet_len[0x10]; 3189 3190 u8 rdma_op_len[0x20]; 3191 3192 u8 rdma_va[0x40]; 3193 3194 u8 reserved_at_c0[0x5]; 3195 u8 rdma[0x1]; 3196 u8 write[0x1]; 3197 u8 requestor[0x1]; 3198 u8 qp_number[0x18]; 3199 }; 3200 3201 struct mlx5_ifc_wqe_associated_page_fault_event_bits { 3202 u8 bytes_committed[0x20]; 3203 3204 u8 reserved_at_20[0x10]; 3205 u8 wqe_index[0x10]; 3206 3207 u8 reserved_at_40[0x10]; 3208 u8 len[0x10]; 3209 3210 u8 reserved_at_60[0x60]; 3211 3212 u8 reserved_at_c0[0x5]; 3213 u8 rdma[0x1]; 3214 u8 write_read[0x1]; 3215 u8 requestor[0x1]; 3216 u8 qpn[0x18]; 3217 }; 3218 3219 struct mlx5_ifc_qp_events_bits { 3220 u8 reserved_at_0[0xa0]; 3221 3222 u8 type[0x8]; 3223 u8 reserved_at_a8[0x18]; 3224 3225 u8 reserved_at_c0[0x8]; 3226 u8 qpn_rqn_sqn[0x18]; 3227 }; 3228 3229 struct mlx5_ifc_dct_events_bits { 3230 u8 reserved_at_0[0xc0]; 3231 3232 u8 reserved_at_c0[0x8]; 3233 u8 dct_number[0x18]; 3234 }; 3235 3236 struct mlx5_ifc_comp_event_bits { 3237 u8 reserved_at_0[0xc0]; 3238 3239 u8 reserved_at_c0[0x8]; 3240 u8 cq_number[0x18]; 3241 }; 3242 3243 enum { 3244 MLX5_QPC_STATE_RST = 0x0, 3245 MLX5_QPC_STATE_INIT = 0x1, 3246 MLX5_QPC_STATE_RTR = 0x2, 3247 MLX5_QPC_STATE_RTS = 0x3, 3248 MLX5_QPC_STATE_SQER = 0x4, 3249 MLX5_QPC_STATE_ERR = 0x6, 3250 MLX5_QPC_STATE_SQD = 0x7, 3251 MLX5_QPC_STATE_SUSPENDED = 0x9, 3252 }; 3253 3254 enum { 3255 MLX5_QPC_ST_RC = 0x0, 3256 MLX5_QPC_ST_UC = 0x1, 3257 MLX5_QPC_ST_UD = 0x2, 3258 MLX5_QPC_ST_XRC = 0x3, 3259 MLX5_QPC_ST_DCI = 0x5, 3260 MLX5_QPC_ST_QP0 = 0x7, 3261 MLX5_QPC_ST_QP1 = 0x8, 3262 MLX5_QPC_ST_RAW_DATAGRAM = 0x9, 3263 MLX5_QPC_ST_REG_UMR = 0xc, 3264 }; 3265 3266 enum { 3267 MLX5_QPC_PM_STATE_ARMED = 0x0, 3268 MLX5_QPC_PM_STATE_REARM = 0x1, 3269 MLX5_QPC_PM_STATE_RESERVED = 0x2, 3270 MLX5_QPC_PM_STATE_MIGRATED = 0x3, 3271 }; 3272 3273 enum { 3274 MLX5_QPC_OFFLOAD_TYPE_RNDV = 0x1, 3275 }; 3276 3277 enum { 3278 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0, 3279 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1, 3280 }; 3281 3282 enum { 3283 MLX5_QPC_MTU_256_BYTES = 0x1, 3284 MLX5_QPC_MTU_512_BYTES = 0x2, 3285 MLX5_QPC_MTU_1K_BYTES = 0x3, 3286 MLX5_QPC_MTU_2K_BYTES = 0x4, 3287 MLX5_QPC_MTU_4K_BYTES = 0x5, 3288 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7, 3289 }; 3290 3291 enum { 3292 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1, 3293 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2, 3294 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3, 3295 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4, 3296 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5, 3297 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6, 3298 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7, 3299 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8, 3300 }; 3301 3302 enum { 3303 MLX5_QPC_CS_REQ_DISABLE = 0x0, 3304 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11, 3305 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22, 3306 }; 3307 3308 enum { 3309 MLX5_QPC_CS_RES_DISABLE = 0x0, 3310 MLX5_QPC_CS_RES_UP_TO_32B = 0x1, 3311 MLX5_QPC_CS_RES_UP_TO_64B = 0x2, 3312 }; 3313 3314 enum { 3315 MLX5_TIMESTAMP_FORMAT_FREE_RUNNING = 0x0, 3316 MLX5_TIMESTAMP_FORMAT_DEFAULT = 0x1, 3317 MLX5_TIMESTAMP_FORMAT_REAL_TIME = 0x2, 3318 }; 3319 3320 struct mlx5_ifc_qpc_bits { 3321 u8 state[0x4]; 3322 u8 lag_tx_port_affinity[0x4]; 3323 u8 st[0x8]; 3324 u8 reserved_at_10[0x2]; 3325 u8 isolate_vl_tc[0x1]; 3326 u8 pm_state[0x2]; 3327 u8 reserved_at_15[0x1]; 3328 u8 req_e2e_credit_mode[0x2]; 3329 u8 offload_type[0x4]; 3330 u8 end_padding_mode[0x2]; 3331 u8 reserved_at_1e[0x2]; 3332 3333 u8 wq_signature[0x1]; 3334 u8 block_lb_mc[0x1]; 3335 u8 atomic_like_write_en[0x1]; 3336 u8 latency_sensitive[0x1]; 3337 u8 reserved_at_24[0x1]; 3338 u8 drain_sigerr[0x1]; 3339 u8 reserved_at_26[0x2]; 3340 u8 pd[0x18]; 3341 3342 u8 mtu[0x3]; 3343 u8 log_msg_max[0x5]; 3344 u8 reserved_at_48[0x1]; 3345 u8 log_rq_size[0x4]; 3346 u8 log_rq_stride[0x3]; 3347 u8 no_sq[0x1]; 3348 u8 log_sq_size[0x4]; 3349 u8 reserved_at_55[0x1]; 3350 u8 retry_mode[0x2]; 3351 u8 ts_format[0x2]; 3352 u8 reserved_at_5a[0x1]; 3353 u8 rlky[0x1]; 3354 u8 ulp_stateless_offload_mode[0x4]; 3355 3356 u8 counter_set_id[0x8]; 3357 u8 uar_page[0x18]; 3358 3359 u8 reserved_at_80[0x8]; 3360 u8 user_index[0x18]; 3361 3362 u8 reserved_at_a0[0x3]; 3363 u8 log_page_size[0x5]; 3364 u8 remote_qpn[0x18]; 3365 3366 struct mlx5_ifc_ads_bits primary_address_path; 3367 3368 struct mlx5_ifc_ads_bits secondary_address_path; 3369 3370 u8 log_ack_req_freq[0x4]; 3371 u8 reserved_at_384[0x4]; 3372 u8 log_sra_max[0x3]; 3373 u8 reserved_at_38b[0x2]; 3374 u8 retry_count[0x3]; 3375 u8 rnr_retry[0x3]; 3376 u8 reserved_at_393[0x1]; 3377 u8 fre[0x1]; 3378 u8 cur_rnr_retry[0x3]; 3379 u8 cur_retry_count[0x3]; 3380 u8 reserved_at_39b[0x5]; 3381 3382 u8 reserved_at_3a0[0x20]; 3383 3384 u8 reserved_at_3c0[0x8]; 3385 u8 next_send_psn[0x18]; 3386 3387 u8 reserved_at_3e0[0x3]; 3388 u8 log_num_dci_stream_channels[0x5]; 3389 u8 cqn_snd[0x18]; 3390 3391 u8 reserved_at_400[0x3]; 3392 u8 log_num_dci_errored_streams[0x5]; 3393 u8 deth_sqpn[0x18]; 3394 3395 u8 reserved_at_420[0x20]; 3396 3397 u8 reserved_at_440[0x8]; 3398 u8 last_acked_psn[0x18]; 3399 3400 u8 reserved_at_460[0x8]; 3401 u8 ssn[0x18]; 3402 3403 u8 reserved_at_480[0x8]; 3404 u8 log_rra_max[0x3]; 3405 u8 reserved_at_48b[0x1]; 3406 u8 atomic_mode[0x4]; 3407 u8 rre[0x1]; 3408 u8 rwe[0x1]; 3409 u8 rae[0x1]; 3410 u8 reserved_at_493[0x1]; 3411 u8 page_offset[0x6]; 3412 u8 reserved_at_49a[0x3]; 3413 u8 cd_slave_receive[0x1]; 3414 u8 cd_slave_send[0x1]; 3415 u8 cd_master[0x1]; 3416 3417 u8 reserved_at_4a0[0x3]; 3418 u8 min_rnr_nak[0x5]; 3419 u8 next_rcv_psn[0x18]; 3420 3421 u8 reserved_at_4c0[0x8]; 3422 u8 xrcd[0x18]; 3423 3424 u8 reserved_at_4e0[0x8]; 3425 u8 cqn_rcv[0x18]; 3426 3427 u8 dbr_addr[0x40]; 3428 3429 u8 q_key[0x20]; 3430 3431 u8 reserved_at_560[0x5]; 3432 u8 rq_type[0x3]; 3433 u8 srqn_rmpn_xrqn[0x18]; 3434 3435 u8 reserved_at_580[0x8]; 3436 u8 rmsn[0x18]; 3437 3438 u8 hw_sq_wqebb_counter[0x10]; 3439 u8 sw_sq_wqebb_counter[0x10]; 3440 3441 u8 hw_rq_counter[0x20]; 3442 3443 u8 sw_rq_counter[0x20]; 3444 3445 u8 reserved_at_600[0x20]; 3446 3447 u8 reserved_at_620[0xf]; 3448 u8 cgs[0x1]; 3449 u8 cs_req[0x8]; 3450 u8 cs_res[0x8]; 3451 3452 u8 dc_access_key[0x40]; 3453 3454 u8 reserved_at_680[0x3]; 3455 u8 dbr_umem_valid[0x1]; 3456 3457 u8 reserved_at_684[0xbc]; 3458 }; 3459 3460 struct mlx5_ifc_roce_addr_layout_bits { 3461 u8 source_l3_address[16][0x8]; 3462 3463 u8 reserved_at_80[0x3]; 3464 u8 vlan_valid[0x1]; 3465 u8 vlan_id[0xc]; 3466 u8 source_mac_47_32[0x10]; 3467 3468 u8 source_mac_31_0[0x20]; 3469 3470 u8 reserved_at_c0[0x14]; 3471 u8 roce_l3_type[0x4]; 3472 u8 roce_version[0x8]; 3473 3474 u8 reserved_at_e0[0x20]; 3475 }; 3476 3477 struct mlx5_ifc_crypto_cap_bits { 3478 u8 reserved_at_0[0x3]; 3479 u8 synchronize_dek[0x1]; 3480 u8 int_kek_manual[0x1]; 3481 u8 int_kek_auto[0x1]; 3482 u8 reserved_at_6[0x1a]; 3483 3484 u8 reserved_at_20[0x3]; 3485 u8 log_dek_max_alloc[0x5]; 3486 u8 reserved_at_28[0x3]; 3487 u8 log_max_num_deks[0x5]; 3488 u8 reserved_at_30[0x10]; 3489 3490 u8 reserved_at_40[0x20]; 3491 3492 u8 reserved_at_60[0x3]; 3493 u8 log_dek_granularity[0x5]; 3494 u8 reserved_at_68[0x3]; 3495 u8 log_max_num_int_kek[0x5]; 3496 u8 sw_wrapped_dek[0x10]; 3497 3498 u8 reserved_at_80[0x780]; 3499 }; 3500 3501 union mlx5_ifc_hca_cap_union_bits { 3502 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap; 3503 struct mlx5_ifc_cmd_hca_cap_2_bits cmd_hca_cap_2; 3504 struct mlx5_ifc_odp_cap_bits odp_cap; 3505 struct mlx5_ifc_atomic_caps_bits atomic_caps; 3506 struct mlx5_ifc_roce_cap_bits roce_cap; 3507 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps; 3508 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap; 3509 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap; 3510 struct mlx5_ifc_e_switch_cap_bits e_switch_cap; 3511 struct mlx5_ifc_port_selection_cap_bits port_selection_cap; 3512 struct mlx5_ifc_qos_cap_bits qos_cap; 3513 struct mlx5_ifc_debug_cap_bits debug_cap; 3514 struct mlx5_ifc_fpga_cap_bits fpga_cap; 3515 struct mlx5_ifc_tls_cap_bits tls_cap; 3516 struct mlx5_ifc_device_mem_cap_bits device_mem_cap; 3517 struct mlx5_ifc_virtio_emulation_cap_bits virtio_emulation_cap; 3518 struct mlx5_ifc_macsec_cap_bits macsec_cap; 3519 struct mlx5_ifc_crypto_cap_bits crypto_cap; 3520 struct mlx5_ifc_ipsec_cap_bits ipsec_cap; 3521 u8 reserved_at_0[0x8000]; 3522 }; 3523 3524 enum { 3525 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1, 3526 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2, 3527 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4, 3528 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8, 3529 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT = 0x10, 3530 MLX5_FLOW_CONTEXT_ACTION_DECAP = 0x20, 3531 MLX5_FLOW_CONTEXT_ACTION_MOD_HDR = 0x40, 3532 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP = 0x80, 3533 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100, 3534 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2 = 0x400, 3535 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2 = 0x800, 3536 MLX5_FLOW_CONTEXT_ACTION_CRYPTO_DECRYPT = 0x1000, 3537 MLX5_FLOW_CONTEXT_ACTION_CRYPTO_ENCRYPT = 0x2000, 3538 MLX5_FLOW_CONTEXT_ACTION_EXECUTE_ASO = 0x4000, 3539 }; 3540 3541 enum { 3542 MLX5_FLOW_CONTEXT_FLOW_SOURCE_ANY_VPORT = 0x0, 3543 MLX5_FLOW_CONTEXT_FLOW_SOURCE_UPLINK = 0x1, 3544 MLX5_FLOW_CONTEXT_FLOW_SOURCE_LOCAL_VPORT = 0x2, 3545 }; 3546 3547 enum { 3548 MLX5_FLOW_CONTEXT_ENCRYPT_DECRYPT_TYPE_IPSEC = 0x0, 3549 MLX5_FLOW_CONTEXT_ENCRYPT_DECRYPT_TYPE_MACSEC = 0x1, 3550 }; 3551 3552 struct mlx5_ifc_vlan_bits { 3553 u8 ethtype[0x10]; 3554 u8 prio[0x3]; 3555 u8 cfi[0x1]; 3556 u8 vid[0xc]; 3557 }; 3558 3559 enum { 3560 MLX5_FLOW_METER_COLOR_RED = 0x0, 3561 MLX5_FLOW_METER_COLOR_YELLOW = 0x1, 3562 MLX5_FLOW_METER_COLOR_GREEN = 0x2, 3563 MLX5_FLOW_METER_COLOR_UNDEFINED = 0x3, 3564 }; 3565 3566 enum { 3567 MLX5_EXE_ASO_FLOW_METER = 0x2, 3568 }; 3569 3570 struct mlx5_ifc_exe_aso_ctrl_flow_meter_bits { 3571 u8 return_reg_id[0x4]; 3572 u8 aso_type[0x4]; 3573 u8 reserved_at_8[0x14]; 3574 u8 action[0x1]; 3575 u8 init_color[0x2]; 3576 u8 meter_id[0x1]; 3577 }; 3578 3579 union mlx5_ifc_exe_aso_ctrl { 3580 struct mlx5_ifc_exe_aso_ctrl_flow_meter_bits exe_aso_ctrl_flow_meter; 3581 }; 3582 3583 struct mlx5_ifc_execute_aso_bits { 3584 u8 valid[0x1]; 3585 u8 reserved_at_1[0x7]; 3586 u8 aso_object_id[0x18]; 3587 3588 union mlx5_ifc_exe_aso_ctrl exe_aso_ctrl; 3589 }; 3590 3591 struct mlx5_ifc_flow_context_bits { 3592 struct mlx5_ifc_vlan_bits push_vlan; 3593 3594 u8 group_id[0x20]; 3595 3596 u8 reserved_at_40[0x8]; 3597 u8 flow_tag[0x18]; 3598 3599 u8 reserved_at_60[0x10]; 3600 u8 action[0x10]; 3601 3602 u8 extended_destination[0x1]; 3603 u8 uplink_hairpin_en[0x1]; 3604 u8 flow_source[0x2]; 3605 u8 encrypt_decrypt_type[0x4]; 3606 u8 destination_list_size[0x18]; 3607 3608 u8 reserved_at_a0[0x8]; 3609 u8 flow_counter_list_size[0x18]; 3610 3611 u8 packet_reformat_id[0x20]; 3612 3613 u8 modify_header_id[0x20]; 3614 3615 struct mlx5_ifc_vlan_bits push_vlan_2; 3616 3617 u8 encrypt_decrypt_obj_id[0x20]; 3618 u8 reserved_at_140[0xc0]; 3619 3620 struct mlx5_ifc_fte_match_param_bits match_value; 3621 3622 struct mlx5_ifc_execute_aso_bits execute_aso[4]; 3623 3624 u8 reserved_at_1300[0x500]; 3625 3626 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[]; 3627 }; 3628 3629 enum { 3630 MLX5_XRC_SRQC_STATE_GOOD = 0x0, 3631 MLX5_XRC_SRQC_STATE_ERROR = 0x1, 3632 }; 3633 3634 struct mlx5_ifc_xrc_srqc_bits { 3635 u8 state[0x4]; 3636 u8 log_xrc_srq_size[0x4]; 3637 u8 reserved_at_8[0x18]; 3638 3639 u8 wq_signature[0x1]; 3640 u8 cont_srq[0x1]; 3641 u8 reserved_at_22[0x1]; 3642 u8 rlky[0x1]; 3643 u8 basic_cyclic_rcv_wqe[0x1]; 3644 u8 log_rq_stride[0x3]; 3645 u8 xrcd[0x18]; 3646 3647 u8 page_offset[0x6]; 3648 u8 reserved_at_46[0x1]; 3649 u8 dbr_umem_valid[0x1]; 3650 u8 cqn[0x18]; 3651 3652 u8 reserved_at_60[0x20]; 3653 3654 u8 user_index_equal_xrc_srqn[0x1]; 3655 u8 reserved_at_81[0x1]; 3656 u8 log_page_size[0x6]; 3657 u8 user_index[0x18]; 3658 3659 u8 reserved_at_a0[0x20]; 3660 3661 u8 reserved_at_c0[0x8]; 3662 u8 pd[0x18]; 3663 3664 u8 lwm[0x10]; 3665 u8 wqe_cnt[0x10]; 3666 3667 u8 reserved_at_100[0x40]; 3668 3669 u8 db_record_addr_h[0x20]; 3670 3671 u8 db_record_addr_l[0x1e]; 3672 u8 reserved_at_17e[0x2]; 3673 3674 u8 reserved_at_180[0x80]; 3675 }; 3676 3677 struct mlx5_ifc_vnic_diagnostic_statistics_bits { 3678 u8 counter_error_queues[0x20]; 3679 3680 u8 total_error_queues[0x20]; 3681 3682 u8 send_queue_priority_update_flow[0x20]; 3683 3684 u8 reserved_at_60[0x20]; 3685 3686 u8 nic_receive_steering_discard[0x40]; 3687 3688 u8 receive_discard_vport_down[0x40]; 3689 3690 u8 transmit_discard_vport_down[0x40]; 3691 3692 u8 async_eq_overrun[0x20]; 3693 3694 u8 comp_eq_overrun[0x20]; 3695 3696 u8 reserved_at_180[0x20]; 3697 3698 u8 invalid_command[0x20]; 3699 3700 u8 quota_exceeded_command[0x20]; 3701 3702 u8 internal_rq_out_of_buffer[0x20]; 3703 3704 u8 cq_overrun[0x20]; 3705 3706 u8 eth_wqe_too_small[0x20]; 3707 3708 u8 reserved_at_220[0xc0]; 3709 3710 u8 generated_pkt_steering_fail[0x40]; 3711 3712 u8 handled_pkt_steering_fail[0x40]; 3713 3714 u8 reserved_at_360[0xc80]; 3715 }; 3716 3717 struct mlx5_ifc_traffic_counter_bits { 3718 u8 packets[0x40]; 3719 3720 u8 octets[0x40]; 3721 }; 3722 3723 struct mlx5_ifc_tisc_bits { 3724 u8 strict_lag_tx_port_affinity[0x1]; 3725 u8 tls_en[0x1]; 3726 u8 reserved_at_2[0x2]; 3727 u8 lag_tx_port_affinity[0x04]; 3728 3729 u8 reserved_at_8[0x4]; 3730 u8 prio[0x4]; 3731 u8 reserved_at_10[0x10]; 3732 3733 u8 reserved_at_20[0x100]; 3734 3735 u8 reserved_at_120[0x8]; 3736 u8 transport_domain[0x18]; 3737 3738 u8 reserved_at_140[0x8]; 3739 u8 underlay_qpn[0x18]; 3740 3741 u8 reserved_at_160[0x8]; 3742 u8 pd[0x18]; 3743 3744 u8 reserved_at_180[0x380]; 3745 }; 3746 3747 enum { 3748 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0, 3749 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1, 3750 }; 3751 3752 enum { 3753 MLX5_TIRC_PACKET_MERGE_MASK_IPV4_LRO = BIT(0), 3754 MLX5_TIRC_PACKET_MERGE_MASK_IPV6_LRO = BIT(1), 3755 }; 3756 3757 enum { 3758 MLX5_RX_HASH_FN_NONE = 0x0, 3759 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1, 3760 MLX5_RX_HASH_FN_TOEPLITZ = 0x2, 3761 }; 3762 3763 enum { 3764 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST = 0x1, 3765 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST = 0x2, 3766 }; 3767 3768 struct mlx5_ifc_tirc_bits { 3769 u8 reserved_at_0[0x20]; 3770 3771 u8 disp_type[0x4]; 3772 u8 tls_en[0x1]; 3773 u8 reserved_at_25[0x1b]; 3774 3775 u8 reserved_at_40[0x40]; 3776 3777 u8 reserved_at_80[0x4]; 3778 u8 lro_timeout_period_usecs[0x10]; 3779 u8 packet_merge_mask[0x4]; 3780 u8 lro_max_ip_payload_size[0x8]; 3781 3782 u8 reserved_at_a0[0x40]; 3783 3784 u8 reserved_at_e0[0x8]; 3785 u8 inline_rqn[0x18]; 3786 3787 u8 rx_hash_symmetric[0x1]; 3788 u8 reserved_at_101[0x1]; 3789 u8 tunneled_offload_en[0x1]; 3790 u8 reserved_at_103[0x5]; 3791 u8 indirect_table[0x18]; 3792 3793 u8 rx_hash_fn[0x4]; 3794 u8 reserved_at_124[0x2]; 3795 u8 self_lb_block[0x2]; 3796 u8 transport_domain[0x18]; 3797 3798 u8 rx_hash_toeplitz_key[10][0x20]; 3799 3800 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer; 3801 3802 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner; 3803 3804 u8 reserved_at_2c0[0x4c0]; 3805 }; 3806 3807 enum { 3808 MLX5_SRQC_STATE_GOOD = 0x0, 3809 MLX5_SRQC_STATE_ERROR = 0x1, 3810 }; 3811 3812 struct mlx5_ifc_srqc_bits { 3813 u8 state[0x4]; 3814 u8 log_srq_size[0x4]; 3815 u8 reserved_at_8[0x18]; 3816 3817 u8 wq_signature[0x1]; 3818 u8 cont_srq[0x1]; 3819 u8 reserved_at_22[0x1]; 3820 u8 rlky[0x1]; 3821 u8 reserved_at_24[0x1]; 3822 u8 log_rq_stride[0x3]; 3823 u8 xrcd[0x18]; 3824 3825 u8 page_offset[0x6]; 3826 u8 reserved_at_46[0x2]; 3827 u8 cqn[0x18]; 3828 3829 u8 reserved_at_60[0x20]; 3830 3831 u8 reserved_at_80[0x2]; 3832 u8 log_page_size[0x6]; 3833 u8 reserved_at_88[0x18]; 3834 3835 u8 reserved_at_a0[0x20]; 3836 3837 u8 reserved_at_c0[0x8]; 3838 u8 pd[0x18]; 3839 3840 u8 lwm[0x10]; 3841 u8 wqe_cnt[0x10]; 3842 3843 u8 reserved_at_100[0x40]; 3844 3845 u8 dbr_addr[0x40]; 3846 3847 u8 reserved_at_180[0x80]; 3848 }; 3849 3850 enum { 3851 MLX5_SQC_STATE_RST = 0x0, 3852 MLX5_SQC_STATE_RDY = 0x1, 3853 MLX5_SQC_STATE_ERR = 0x3, 3854 }; 3855 3856 struct mlx5_ifc_sqc_bits { 3857 u8 rlky[0x1]; 3858 u8 cd_master[0x1]; 3859 u8 fre[0x1]; 3860 u8 flush_in_error_en[0x1]; 3861 u8 allow_multi_pkt_send_wqe[0x1]; 3862 u8 min_wqe_inline_mode[0x3]; 3863 u8 state[0x4]; 3864 u8 reg_umr[0x1]; 3865 u8 allow_swp[0x1]; 3866 u8 hairpin[0x1]; 3867 u8 reserved_at_f[0xb]; 3868 u8 ts_format[0x2]; 3869 u8 reserved_at_1c[0x4]; 3870 3871 u8 reserved_at_20[0x8]; 3872 u8 user_index[0x18]; 3873 3874 u8 reserved_at_40[0x8]; 3875 u8 cqn[0x18]; 3876 3877 u8 reserved_at_60[0x8]; 3878 u8 hairpin_peer_rq[0x18]; 3879 3880 u8 reserved_at_80[0x10]; 3881 u8 hairpin_peer_vhca[0x10]; 3882 3883 u8 reserved_at_a0[0x20]; 3884 3885 u8 reserved_at_c0[0x8]; 3886 u8 ts_cqe_to_dest_cqn[0x18]; 3887 3888 u8 reserved_at_e0[0x10]; 3889 u8 packet_pacing_rate_limit_index[0x10]; 3890 u8 tis_lst_sz[0x10]; 3891 u8 qos_queue_group_id[0x10]; 3892 3893 u8 reserved_at_120[0x40]; 3894 3895 u8 reserved_at_160[0x8]; 3896 u8 tis_num_0[0x18]; 3897 3898 struct mlx5_ifc_wq_bits wq; 3899 }; 3900 3901 enum { 3902 SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0, 3903 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1, 3904 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2, 3905 SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3, 3906 SCHEDULING_CONTEXT_ELEMENT_TYPE_QUEUE_GROUP = 0x4, 3907 }; 3908 3909 enum { 3910 ELEMENT_TYPE_CAP_MASK_TASR = 1 << 0, 3911 ELEMENT_TYPE_CAP_MASK_VPORT = 1 << 1, 3912 ELEMENT_TYPE_CAP_MASK_VPORT_TC = 1 << 2, 3913 ELEMENT_TYPE_CAP_MASK_PARA_VPORT_TC = 1 << 3, 3914 }; 3915 3916 struct mlx5_ifc_scheduling_context_bits { 3917 u8 element_type[0x8]; 3918 u8 reserved_at_8[0x18]; 3919 3920 u8 element_attributes[0x20]; 3921 3922 u8 parent_element_id[0x20]; 3923 3924 u8 reserved_at_60[0x40]; 3925 3926 u8 bw_share[0x20]; 3927 3928 u8 max_average_bw[0x20]; 3929 3930 u8 reserved_at_e0[0x120]; 3931 }; 3932 3933 struct mlx5_ifc_rqtc_bits { 3934 u8 reserved_at_0[0xa0]; 3935 3936 u8 reserved_at_a0[0x5]; 3937 u8 list_q_type[0x3]; 3938 u8 reserved_at_a8[0x8]; 3939 u8 rqt_max_size[0x10]; 3940 3941 u8 rq_vhca_id_format[0x1]; 3942 u8 reserved_at_c1[0xf]; 3943 u8 rqt_actual_size[0x10]; 3944 3945 u8 reserved_at_e0[0x6a0]; 3946 3947 union { 3948 DECLARE_FLEX_ARRAY(struct mlx5_ifc_rq_num_bits, rq_num); 3949 DECLARE_FLEX_ARRAY(struct mlx5_ifc_rq_vhca_bits, rq_vhca); 3950 }; 3951 }; 3952 3953 enum { 3954 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0, 3955 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1, 3956 }; 3957 3958 enum { 3959 MLX5_RQC_STATE_RST = 0x0, 3960 MLX5_RQC_STATE_RDY = 0x1, 3961 MLX5_RQC_STATE_ERR = 0x3, 3962 }; 3963 3964 enum { 3965 MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_BYTE = 0x0, 3966 MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_STRIDE = 0x1, 3967 MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_PAGE = 0x2, 3968 }; 3969 3970 enum { 3971 MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_NO_MATCH = 0x0, 3972 MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_EXTENDED = 0x1, 3973 MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_FIVE_TUPLE = 0x2, 3974 }; 3975 3976 struct mlx5_ifc_rqc_bits { 3977 u8 rlky[0x1]; 3978 u8 delay_drop_en[0x1]; 3979 u8 scatter_fcs[0x1]; 3980 u8 vsd[0x1]; 3981 u8 mem_rq_type[0x4]; 3982 u8 state[0x4]; 3983 u8 reserved_at_c[0x1]; 3984 u8 flush_in_error_en[0x1]; 3985 u8 hairpin[0x1]; 3986 u8 reserved_at_f[0xb]; 3987 u8 ts_format[0x2]; 3988 u8 reserved_at_1c[0x4]; 3989 3990 u8 reserved_at_20[0x8]; 3991 u8 user_index[0x18]; 3992 3993 u8 reserved_at_40[0x8]; 3994 u8 cqn[0x18]; 3995 3996 u8 counter_set_id[0x8]; 3997 u8 reserved_at_68[0x18]; 3998 3999 u8 reserved_at_80[0x8]; 4000 u8 rmpn[0x18]; 4001 4002 u8 reserved_at_a0[0x8]; 4003 u8 hairpin_peer_sq[0x18]; 4004 4005 u8 reserved_at_c0[0x10]; 4006 u8 hairpin_peer_vhca[0x10]; 4007 4008 u8 reserved_at_e0[0x46]; 4009 u8 shampo_no_match_alignment_granularity[0x2]; 4010 u8 reserved_at_128[0x6]; 4011 u8 shampo_match_criteria_type[0x2]; 4012 u8 reservation_timeout[0x10]; 4013 4014 u8 reserved_at_140[0x40]; 4015 4016 struct mlx5_ifc_wq_bits wq; 4017 }; 4018 4019 enum { 4020 MLX5_RMPC_STATE_RDY = 0x1, 4021 MLX5_RMPC_STATE_ERR = 0x3, 4022 }; 4023 4024 struct mlx5_ifc_rmpc_bits { 4025 u8 reserved_at_0[0x8]; 4026 u8 state[0x4]; 4027 u8 reserved_at_c[0x14]; 4028 4029 u8 basic_cyclic_rcv_wqe[0x1]; 4030 u8 reserved_at_21[0x1f]; 4031 4032 u8 reserved_at_40[0x140]; 4033 4034 struct mlx5_ifc_wq_bits wq; 4035 }; 4036 4037 enum { 4038 VHCA_ID_TYPE_HW = 0, 4039 VHCA_ID_TYPE_SW = 1, 4040 }; 4041 4042 struct mlx5_ifc_nic_vport_context_bits { 4043 u8 reserved_at_0[0x5]; 4044 u8 min_wqe_inline_mode[0x3]; 4045 u8 reserved_at_8[0x15]; 4046 u8 disable_mc_local_lb[0x1]; 4047 u8 disable_uc_local_lb[0x1]; 4048 u8 roce_en[0x1]; 4049 4050 u8 arm_change_event[0x1]; 4051 u8 reserved_at_21[0x1a]; 4052 u8 event_on_mtu[0x1]; 4053 u8 event_on_promisc_change[0x1]; 4054 u8 event_on_vlan_change[0x1]; 4055 u8 event_on_mc_address_change[0x1]; 4056 u8 event_on_uc_address_change[0x1]; 4057 4058 u8 vhca_id_type[0x1]; 4059 u8 reserved_at_41[0xb]; 4060 u8 affiliation_criteria[0x4]; 4061 u8 affiliated_vhca_id[0x10]; 4062 4063 u8 reserved_at_60[0xa0]; 4064 4065 u8 reserved_at_100[0x1]; 4066 u8 sd_group[0x3]; 4067 u8 reserved_at_104[0x1c]; 4068 4069 u8 reserved_at_120[0x10]; 4070 u8 mtu[0x10]; 4071 4072 u8 system_image_guid[0x40]; 4073 u8 port_guid[0x40]; 4074 u8 node_guid[0x40]; 4075 4076 u8 reserved_at_200[0x140]; 4077 u8 qkey_violation_counter[0x10]; 4078 u8 reserved_at_350[0x430]; 4079 4080 u8 promisc_uc[0x1]; 4081 u8 promisc_mc[0x1]; 4082 u8 promisc_all[0x1]; 4083 u8 reserved_at_783[0x2]; 4084 u8 allowed_list_type[0x3]; 4085 u8 reserved_at_788[0xc]; 4086 u8 allowed_list_size[0xc]; 4087 4088 struct mlx5_ifc_mac_address_layout_bits permanent_address; 4089 4090 u8 reserved_at_7e0[0x20]; 4091 4092 u8 current_uc_mac_address[][0x40]; 4093 }; 4094 4095 enum { 4096 MLX5_MKC_ACCESS_MODE_PA = 0x0, 4097 MLX5_MKC_ACCESS_MODE_MTT = 0x1, 4098 MLX5_MKC_ACCESS_MODE_KLMS = 0x2, 4099 MLX5_MKC_ACCESS_MODE_KSM = 0x3, 4100 MLX5_MKC_ACCESS_MODE_SW_ICM = 0x4, 4101 MLX5_MKC_ACCESS_MODE_MEMIC = 0x5, 4102 }; 4103 4104 struct mlx5_ifc_mkc_bits { 4105 u8 reserved_at_0[0x1]; 4106 u8 free[0x1]; 4107 u8 reserved_at_2[0x1]; 4108 u8 access_mode_4_2[0x3]; 4109 u8 reserved_at_6[0x7]; 4110 u8 relaxed_ordering_write[0x1]; 4111 u8 reserved_at_e[0x1]; 4112 u8 small_fence_on_rdma_read_response[0x1]; 4113 u8 umr_en[0x1]; 4114 u8 a[0x1]; 4115 u8 rw[0x1]; 4116 u8 rr[0x1]; 4117 u8 lw[0x1]; 4118 u8 lr[0x1]; 4119 u8 access_mode_1_0[0x2]; 4120 u8 reserved_at_18[0x2]; 4121 u8 ma_translation_mode[0x2]; 4122 u8 reserved_at_1c[0x4]; 4123 4124 u8 qpn[0x18]; 4125 u8 mkey_7_0[0x8]; 4126 4127 u8 reserved_at_40[0x20]; 4128 4129 u8 length64[0x1]; 4130 u8 bsf_en[0x1]; 4131 u8 sync_umr[0x1]; 4132 u8 reserved_at_63[0x2]; 4133 u8 expected_sigerr_count[0x1]; 4134 u8 reserved_at_66[0x1]; 4135 u8 en_rinval[0x1]; 4136 u8 pd[0x18]; 4137 4138 u8 start_addr[0x40]; 4139 4140 u8 len[0x40]; 4141 4142 u8 bsf_octword_size[0x20]; 4143 4144 u8 reserved_at_120[0x80]; 4145 4146 u8 translations_octword_size[0x20]; 4147 4148 u8 reserved_at_1c0[0x19]; 4149 u8 relaxed_ordering_read[0x1]; 4150 u8 reserved_at_1d9[0x1]; 4151 u8 log_page_size[0x5]; 4152 4153 u8 reserved_at_1e0[0x20]; 4154 }; 4155 4156 struct mlx5_ifc_pkey_bits { 4157 u8 reserved_at_0[0x10]; 4158 u8 pkey[0x10]; 4159 }; 4160 4161 struct mlx5_ifc_array128_auto_bits { 4162 u8 array128_auto[16][0x8]; 4163 }; 4164 4165 struct mlx5_ifc_hca_vport_context_bits { 4166 u8 field_select[0x20]; 4167 4168 u8 reserved_at_20[0xe0]; 4169 4170 u8 sm_virt_aware[0x1]; 4171 u8 has_smi[0x1]; 4172 u8 has_raw[0x1]; 4173 u8 grh_required[0x1]; 4174 u8 reserved_at_104[0xc]; 4175 u8 port_physical_state[0x4]; 4176 u8 vport_state_policy[0x4]; 4177 u8 port_state[0x4]; 4178 u8 vport_state[0x4]; 4179 4180 u8 reserved_at_120[0x20]; 4181 4182 u8 system_image_guid[0x40]; 4183 4184 u8 port_guid[0x40]; 4185 4186 u8 node_guid[0x40]; 4187 4188 u8 cap_mask1[0x20]; 4189 4190 u8 cap_mask1_field_select[0x20]; 4191 4192 u8 cap_mask2[0x20]; 4193 4194 u8 cap_mask2_field_select[0x20]; 4195 4196 u8 reserved_at_280[0x80]; 4197 4198 u8 lid[0x10]; 4199 u8 reserved_at_310[0x4]; 4200 u8 init_type_reply[0x4]; 4201 u8 lmc[0x3]; 4202 u8 subnet_timeout[0x5]; 4203 4204 u8 sm_lid[0x10]; 4205 u8 sm_sl[0x4]; 4206 u8 reserved_at_334[0xc]; 4207 4208 u8 qkey_violation_counter[0x10]; 4209 u8 pkey_violation_counter[0x10]; 4210 4211 u8 reserved_at_360[0xca0]; 4212 }; 4213 4214 struct mlx5_ifc_esw_vport_context_bits { 4215 u8 fdb_to_vport_reg_c[0x1]; 4216 u8 reserved_at_1[0x2]; 4217 u8 vport_svlan_strip[0x1]; 4218 u8 vport_cvlan_strip[0x1]; 4219 u8 vport_svlan_insert[0x1]; 4220 u8 vport_cvlan_insert[0x2]; 4221 u8 fdb_to_vport_reg_c_id[0x8]; 4222 u8 reserved_at_10[0x10]; 4223 4224 u8 reserved_at_20[0x20]; 4225 4226 u8 svlan_cfi[0x1]; 4227 u8 svlan_pcp[0x3]; 4228 u8 svlan_id[0xc]; 4229 u8 cvlan_cfi[0x1]; 4230 u8 cvlan_pcp[0x3]; 4231 u8 cvlan_id[0xc]; 4232 4233 u8 reserved_at_60[0x720]; 4234 4235 u8 sw_steering_vport_icm_address_rx[0x40]; 4236 4237 u8 sw_steering_vport_icm_address_tx[0x40]; 4238 }; 4239 4240 enum { 4241 MLX5_EQC_STATUS_OK = 0x0, 4242 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa, 4243 }; 4244 4245 enum { 4246 MLX5_EQC_ST_ARMED = 0x9, 4247 MLX5_EQC_ST_FIRED = 0xa, 4248 }; 4249 4250 struct mlx5_ifc_eqc_bits { 4251 u8 status[0x4]; 4252 u8 reserved_at_4[0x9]; 4253 u8 ec[0x1]; 4254 u8 oi[0x1]; 4255 u8 reserved_at_f[0x5]; 4256 u8 st[0x4]; 4257 u8 reserved_at_18[0x8]; 4258 4259 u8 reserved_at_20[0x20]; 4260 4261 u8 reserved_at_40[0x14]; 4262 u8 page_offset[0x6]; 4263 u8 reserved_at_5a[0x6]; 4264 4265 u8 reserved_at_60[0x3]; 4266 u8 log_eq_size[0x5]; 4267 u8 uar_page[0x18]; 4268 4269 u8 reserved_at_80[0x20]; 4270 4271 u8 reserved_at_a0[0x14]; 4272 u8 intr[0xc]; 4273 4274 u8 reserved_at_c0[0x3]; 4275 u8 log_page_size[0x5]; 4276 u8 reserved_at_c8[0x18]; 4277 4278 u8 reserved_at_e0[0x60]; 4279 4280 u8 reserved_at_140[0x8]; 4281 u8 consumer_counter[0x18]; 4282 4283 u8 reserved_at_160[0x8]; 4284 u8 producer_counter[0x18]; 4285 4286 u8 reserved_at_180[0x80]; 4287 }; 4288 4289 enum { 4290 MLX5_DCTC_STATE_ACTIVE = 0x0, 4291 MLX5_DCTC_STATE_DRAINING = 0x1, 4292 MLX5_DCTC_STATE_DRAINED = 0x2, 4293 }; 4294 4295 enum { 4296 MLX5_DCTC_CS_RES_DISABLE = 0x0, 4297 MLX5_DCTC_CS_RES_NA = 0x1, 4298 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2, 4299 }; 4300 4301 enum { 4302 MLX5_DCTC_MTU_256_BYTES = 0x1, 4303 MLX5_DCTC_MTU_512_BYTES = 0x2, 4304 MLX5_DCTC_MTU_1K_BYTES = 0x3, 4305 MLX5_DCTC_MTU_2K_BYTES = 0x4, 4306 MLX5_DCTC_MTU_4K_BYTES = 0x5, 4307 }; 4308 4309 struct mlx5_ifc_dctc_bits { 4310 u8 reserved_at_0[0x4]; 4311 u8 state[0x4]; 4312 u8 reserved_at_8[0x18]; 4313 4314 u8 reserved_at_20[0x8]; 4315 u8 user_index[0x18]; 4316 4317 u8 reserved_at_40[0x8]; 4318 u8 cqn[0x18]; 4319 4320 u8 counter_set_id[0x8]; 4321 u8 atomic_mode[0x4]; 4322 u8 rre[0x1]; 4323 u8 rwe[0x1]; 4324 u8 rae[0x1]; 4325 u8 atomic_like_write_en[0x1]; 4326 u8 latency_sensitive[0x1]; 4327 u8 rlky[0x1]; 4328 u8 free_ar[0x1]; 4329 u8 reserved_at_73[0xd]; 4330 4331 u8 reserved_at_80[0x8]; 4332 u8 cs_res[0x8]; 4333 u8 reserved_at_90[0x3]; 4334 u8 min_rnr_nak[0x5]; 4335 u8 reserved_at_98[0x8]; 4336 4337 u8 reserved_at_a0[0x8]; 4338 u8 srqn_xrqn[0x18]; 4339 4340 u8 reserved_at_c0[0x8]; 4341 u8 pd[0x18]; 4342 4343 u8 tclass[0x8]; 4344 u8 reserved_at_e8[0x4]; 4345 u8 flow_label[0x14]; 4346 4347 u8 dc_access_key[0x40]; 4348 4349 u8 reserved_at_140[0x5]; 4350 u8 mtu[0x3]; 4351 u8 port[0x8]; 4352 u8 pkey_index[0x10]; 4353 4354 u8 reserved_at_160[0x8]; 4355 u8 my_addr_index[0x8]; 4356 u8 reserved_at_170[0x8]; 4357 u8 hop_limit[0x8]; 4358 4359 u8 dc_access_key_violation_count[0x20]; 4360 4361 u8 reserved_at_1a0[0x14]; 4362 u8 dei_cfi[0x1]; 4363 u8 eth_prio[0x3]; 4364 u8 ecn[0x2]; 4365 u8 dscp[0x6]; 4366 4367 u8 reserved_at_1c0[0x20]; 4368 u8 ece[0x20]; 4369 }; 4370 4371 enum { 4372 MLX5_CQC_STATUS_OK = 0x0, 4373 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9, 4374 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa, 4375 }; 4376 4377 enum { 4378 MLX5_CQC_CQE_SZ_64_BYTES = 0x0, 4379 MLX5_CQC_CQE_SZ_128_BYTES = 0x1, 4380 }; 4381 4382 enum { 4383 MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED = 0x6, 4384 MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED = 0x9, 4385 MLX5_CQC_ST_FIRED = 0xa, 4386 }; 4387 4388 enum { 4389 MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0, 4390 MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1, 4391 MLX5_CQ_PERIOD_NUM_MODES 4392 }; 4393 4394 struct mlx5_ifc_cqc_bits { 4395 u8 status[0x4]; 4396 u8 reserved_at_4[0x2]; 4397 u8 dbr_umem_valid[0x1]; 4398 u8 apu_cq[0x1]; 4399 u8 cqe_sz[0x3]; 4400 u8 cc[0x1]; 4401 u8 reserved_at_c[0x1]; 4402 u8 scqe_break_moderation_en[0x1]; 4403 u8 oi[0x1]; 4404 u8 cq_period_mode[0x2]; 4405 u8 cqe_comp_en[0x1]; 4406 u8 mini_cqe_res_format[0x2]; 4407 u8 st[0x4]; 4408 u8 reserved_at_18[0x6]; 4409 u8 cqe_compression_layout[0x2]; 4410 4411 u8 reserved_at_20[0x20]; 4412 4413 u8 reserved_at_40[0x14]; 4414 u8 page_offset[0x6]; 4415 u8 reserved_at_5a[0x6]; 4416 4417 u8 reserved_at_60[0x3]; 4418 u8 log_cq_size[0x5]; 4419 u8 uar_page[0x18]; 4420 4421 u8 reserved_at_80[0x4]; 4422 u8 cq_period[0xc]; 4423 u8 cq_max_count[0x10]; 4424 4425 u8 c_eqn_or_apu_element[0x20]; 4426 4427 u8 reserved_at_c0[0x3]; 4428 u8 log_page_size[0x5]; 4429 u8 reserved_at_c8[0x18]; 4430 4431 u8 reserved_at_e0[0x20]; 4432 4433 u8 reserved_at_100[0x8]; 4434 u8 last_notified_index[0x18]; 4435 4436 u8 reserved_at_120[0x8]; 4437 u8 last_solicit_index[0x18]; 4438 4439 u8 reserved_at_140[0x8]; 4440 u8 consumer_counter[0x18]; 4441 4442 u8 reserved_at_160[0x8]; 4443 u8 producer_counter[0x18]; 4444 4445 u8 reserved_at_180[0x40]; 4446 4447 u8 dbr_addr[0x40]; 4448 }; 4449 4450 union mlx5_ifc_cong_control_roce_ecn_auto_bits { 4451 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp; 4452 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp; 4453 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np; 4454 struct mlx5_ifc_cong_control_r_roce_general_bits cong_control_r_roce_general; 4455 u8 reserved_at_0[0x800]; 4456 }; 4457 4458 struct mlx5_ifc_query_adapter_param_block_bits { 4459 u8 reserved_at_0[0xc0]; 4460 4461 u8 reserved_at_c0[0x8]; 4462 u8 ieee_vendor_id[0x18]; 4463 4464 u8 reserved_at_e0[0x10]; 4465 u8 vsd_vendor_id[0x10]; 4466 4467 u8 vsd[208][0x8]; 4468 4469 u8 vsd_contd_psid[16][0x8]; 4470 }; 4471 4472 enum { 4473 MLX5_XRQC_STATE_GOOD = 0x0, 4474 MLX5_XRQC_STATE_ERROR = 0x1, 4475 }; 4476 4477 enum { 4478 MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0, 4479 MLX5_XRQC_TOPOLOGY_TAG_MATCHING = 0x1, 4480 }; 4481 4482 enum { 4483 MLX5_XRQC_OFFLOAD_RNDV = 0x1, 4484 }; 4485 4486 struct mlx5_ifc_tag_matching_topology_context_bits { 4487 u8 log_matching_list_sz[0x4]; 4488 u8 reserved_at_4[0xc]; 4489 u8 append_next_index[0x10]; 4490 4491 u8 sw_phase_cnt[0x10]; 4492 u8 hw_phase_cnt[0x10]; 4493 4494 u8 reserved_at_40[0x40]; 4495 }; 4496 4497 struct mlx5_ifc_xrqc_bits { 4498 u8 state[0x4]; 4499 u8 rlkey[0x1]; 4500 u8 reserved_at_5[0xf]; 4501 u8 topology[0x4]; 4502 u8 reserved_at_18[0x4]; 4503 u8 offload[0x4]; 4504 4505 u8 reserved_at_20[0x8]; 4506 u8 user_index[0x18]; 4507 4508 u8 reserved_at_40[0x8]; 4509 u8 cqn[0x18]; 4510 4511 u8 reserved_at_60[0xa0]; 4512 4513 struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context; 4514 4515 u8 reserved_at_180[0x280]; 4516 4517 struct mlx5_ifc_wq_bits wq; 4518 }; 4519 4520 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits { 4521 struct mlx5_ifc_modify_field_select_bits modify_field_select; 4522 struct mlx5_ifc_resize_field_select_bits resize_field_select; 4523 u8 reserved_at_0[0x20]; 4524 }; 4525 4526 union mlx5_ifc_field_select_802_1_r_roce_auto_bits { 4527 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp; 4528 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp; 4529 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np; 4530 u8 reserved_at_0[0x20]; 4531 }; 4532 4533 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits { 4534 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 4535 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 4536 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 4537 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 4538 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 4539 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 4540 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout; 4541 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout; 4542 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 4543 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 4544 struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs; 4545 u8 reserved_at_0[0x7c0]; 4546 }; 4547 4548 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits { 4549 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout; 4550 u8 reserved_at_0[0x7c0]; 4551 }; 4552 4553 union mlx5_ifc_event_auto_bits { 4554 struct mlx5_ifc_comp_event_bits comp_event; 4555 struct mlx5_ifc_dct_events_bits dct_events; 4556 struct mlx5_ifc_qp_events_bits qp_events; 4557 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event; 4558 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event; 4559 struct mlx5_ifc_cq_error_bits cq_error; 4560 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged; 4561 struct mlx5_ifc_port_state_change_event_bits port_state_change_event; 4562 struct mlx5_ifc_gpio_event_bits gpio_event; 4563 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event; 4564 struct mlx5_ifc_stall_vl_event_bits stall_vl_event; 4565 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event; 4566 u8 reserved_at_0[0xe0]; 4567 }; 4568 4569 struct mlx5_ifc_health_buffer_bits { 4570 u8 reserved_at_0[0x100]; 4571 4572 u8 assert_existptr[0x20]; 4573 4574 u8 assert_callra[0x20]; 4575 4576 u8 reserved_at_140[0x20]; 4577 4578 u8 time[0x20]; 4579 4580 u8 fw_version[0x20]; 4581 4582 u8 hw_id[0x20]; 4583 4584 u8 rfr[0x1]; 4585 u8 reserved_at_1c1[0x3]; 4586 u8 valid[0x1]; 4587 u8 severity[0x3]; 4588 u8 reserved_at_1c8[0x18]; 4589 4590 u8 irisc_index[0x8]; 4591 u8 synd[0x8]; 4592 u8 ext_synd[0x10]; 4593 }; 4594 4595 struct mlx5_ifc_register_loopback_control_bits { 4596 u8 no_lb[0x1]; 4597 u8 reserved_at_1[0x7]; 4598 u8 port[0x8]; 4599 u8 reserved_at_10[0x10]; 4600 4601 u8 reserved_at_20[0x60]; 4602 }; 4603 4604 struct mlx5_ifc_vport_tc_element_bits { 4605 u8 traffic_class[0x4]; 4606 u8 reserved_at_4[0xc]; 4607 u8 vport_number[0x10]; 4608 }; 4609 4610 struct mlx5_ifc_vport_element_bits { 4611 u8 reserved_at_0[0x10]; 4612 u8 vport_number[0x10]; 4613 }; 4614 4615 enum { 4616 TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0, 4617 TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1, 4618 TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2, 4619 }; 4620 4621 struct mlx5_ifc_tsar_element_bits { 4622 u8 reserved_at_0[0x8]; 4623 u8 tsar_type[0x8]; 4624 u8 reserved_at_10[0x10]; 4625 }; 4626 4627 enum { 4628 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0, 4629 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1, 4630 }; 4631 4632 struct mlx5_ifc_teardown_hca_out_bits { 4633 u8 status[0x8]; 4634 u8 reserved_at_8[0x18]; 4635 4636 u8 syndrome[0x20]; 4637 4638 u8 reserved_at_40[0x3f]; 4639 4640 u8 state[0x1]; 4641 }; 4642 4643 enum { 4644 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0, 4645 MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE = 0x1, 4646 MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN = 0x2, 4647 }; 4648 4649 struct mlx5_ifc_teardown_hca_in_bits { 4650 u8 opcode[0x10]; 4651 u8 reserved_at_10[0x10]; 4652 4653 u8 reserved_at_20[0x10]; 4654 u8 op_mod[0x10]; 4655 4656 u8 reserved_at_40[0x10]; 4657 u8 profile[0x10]; 4658 4659 u8 reserved_at_60[0x20]; 4660 }; 4661 4662 struct mlx5_ifc_sqerr2rts_qp_out_bits { 4663 u8 status[0x8]; 4664 u8 reserved_at_8[0x18]; 4665 4666 u8 syndrome[0x20]; 4667 4668 u8 reserved_at_40[0x40]; 4669 }; 4670 4671 struct mlx5_ifc_sqerr2rts_qp_in_bits { 4672 u8 opcode[0x10]; 4673 u8 uid[0x10]; 4674 4675 u8 reserved_at_20[0x10]; 4676 u8 op_mod[0x10]; 4677 4678 u8 reserved_at_40[0x8]; 4679 u8 qpn[0x18]; 4680 4681 u8 reserved_at_60[0x20]; 4682 4683 u8 opt_param_mask[0x20]; 4684 4685 u8 reserved_at_a0[0x20]; 4686 4687 struct mlx5_ifc_qpc_bits qpc; 4688 4689 u8 reserved_at_800[0x80]; 4690 }; 4691 4692 struct mlx5_ifc_sqd2rts_qp_out_bits { 4693 u8 status[0x8]; 4694 u8 reserved_at_8[0x18]; 4695 4696 u8 syndrome[0x20]; 4697 4698 u8 reserved_at_40[0x40]; 4699 }; 4700 4701 struct mlx5_ifc_sqd2rts_qp_in_bits { 4702 u8 opcode[0x10]; 4703 u8 uid[0x10]; 4704 4705 u8 reserved_at_20[0x10]; 4706 u8 op_mod[0x10]; 4707 4708 u8 reserved_at_40[0x8]; 4709 u8 qpn[0x18]; 4710 4711 u8 reserved_at_60[0x20]; 4712 4713 u8 opt_param_mask[0x20]; 4714 4715 u8 reserved_at_a0[0x20]; 4716 4717 struct mlx5_ifc_qpc_bits qpc; 4718 4719 u8 reserved_at_800[0x80]; 4720 }; 4721 4722 struct mlx5_ifc_set_roce_address_out_bits { 4723 u8 status[0x8]; 4724 u8 reserved_at_8[0x18]; 4725 4726 u8 syndrome[0x20]; 4727 4728 u8 reserved_at_40[0x40]; 4729 }; 4730 4731 struct mlx5_ifc_set_roce_address_in_bits { 4732 u8 opcode[0x10]; 4733 u8 reserved_at_10[0x10]; 4734 4735 u8 reserved_at_20[0x10]; 4736 u8 op_mod[0x10]; 4737 4738 u8 roce_address_index[0x10]; 4739 u8 reserved_at_50[0xc]; 4740 u8 vhca_port_num[0x4]; 4741 4742 u8 reserved_at_60[0x20]; 4743 4744 struct mlx5_ifc_roce_addr_layout_bits roce_address; 4745 }; 4746 4747 struct mlx5_ifc_set_mad_demux_out_bits { 4748 u8 status[0x8]; 4749 u8 reserved_at_8[0x18]; 4750 4751 u8 syndrome[0x20]; 4752 4753 u8 reserved_at_40[0x40]; 4754 }; 4755 4756 enum { 4757 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0, 4758 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2, 4759 }; 4760 4761 struct mlx5_ifc_set_mad_demux_in_bits { 4762 u8 opcode[0x10]; 4763 u8 reserved_at_10[0x10]; 4764 4765 u8 reserved_at_20[0x10]; 4766 u8 op_mod[0x10]; 4767 4768 u8 reserved_at_40[0x20]; 4769 4770 u8 reserved_at_60[0x6]; 4771 u8 demux_mode[0x2]; 4772 u8 reserved_at_68[0x18]; 4773 }; 4774 4775 struct mlx5_ifc_set_l2_table_entry_out_bits { 4776 u8 status[0x8]; 4777 u8 reserved_at_8[0x18]; 4778 4779 u8 syndrome[0x20]; 4780 4781 u8 reserved_at_40[0x40]; 4782 }; 4783 4784 struct mlx5_ifc_set_l2_table_entry_in_bits { 4785 u8 opcode[0x10]; 4786 u8 reserved_at_10[0x10]; 4787 4788 u8 reserved_at_20[0x10]; 4789 u8 op_mod[0x10]; 4790 4791 u8 reserved_at_40[0x60]; 4792 4793 u8 reserved_at_a0[0x8]; 4794 u8 table_index[0x18]; 4795 4796 u8 reserved_at_c0[0x20]; 4797 4798 u8 reserved_at_e0[0x10]; 4799 u8 silent_mode_valid[0x1]; 4800 u8 silent_mode[0x1]; 4801 u8 reserved_at_f2[0x1]; 4802 u8 vlan_valid[0x1]; 4803 u8 vlan[0xc]; 4804 4805 struct mlx5_ifc_mac_address_layout_bits mac_address; 4806 4807 u8 reserved_at_140[0xc0]; 4808 }; 4809 4810 struct mlx5_ifc_set_issi_out_bits { 4811 u8 status[0x8]; 4812 u8 reserved_at_8[0x18]; 4813 4814 u8 syndrome[0x20]; 4815 4816 u8 reserved_at_40[0x40]; 4817 }; 4818 4819 struct mlx5_ifc_set_issi_in_bits { 4820 u8 opcode[0x10]; 4821 u8 reserved_at_10[0x10]; 4822 4823 u8 reserved_at_20[0x10]; 4824 u8 op_mod[0x10]; 4825 4826 u8 reserved_at_40[0x10]; 4827 u8 current_issi[0x10]; 4828 4829 u8 reserved_at_60[0x20]; 4830 }; 4831 4832 struct mlx5_ifc_set_hca_cap_out_bits { 4833 u8 status[0x8]; 4834 u8 reserved_at_8[0x18]; 4835 4836 u8 syndrome[0x20]; 4837 4838 u8 reserved_at_40[0x40]; 4839 }; 4840 4841 struct mlx5_ifc_set_hca_cap_in_bits { 4842 u8 opcode[0x10]; 4843 u8 reserved_at_10[0x10]; 4844 4845 u8 reserved_at_20[0x10]; 4846 u8 op_mod[0x10]; 4847 4848 u8 other_function[0x1]; 4849 u8 ec_vf_function[0x1]; 4850 u8 reserved_at_42[0xe]; 4851 u8 function_id[0x10]; 4852 4853 u8 reserved_at_60[0x20]; 4854 4855 union mlx5_ifc_hca_cap_union_bits capability; 4856 }; 4857 4858 enum { 4859 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0, 4860 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1, 4861 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2, 4862 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3, 4863 MLX5_SET_FTE_MODIFY_ENABLE_MASK_IPSEC_OBJ_ID = 0x4 4864 }; 4865 4866 struct mlx5_ifc_set_fte_out_bits { 4867 u8 status[0x8]; 4868 u8 reserved_at_8[0x18]; 4869 4870 u8 syndrome[0x20]; 4871 4872 u8 reserved_at_40[0x40]; 4873 }; 4874 4875 struct mlx5_ifc_set_fte_in_bits { 4876 u8 opcode[0x10]; 4877 u8 reserved_at_10[0x10]; 4878 4879 u8 reserved_at_20[0x10]; 4880 u8 op_mod[0x10]; 4881 4882 u8 other_vport[0x1]; 4883 u8 reserved_at_41[0xf]; 4884 u8 vport_number[0x10]; 4885 4886 u8 reserved_at_60[0x20]; 4887 4888 u8 table_type[0x8]; 4889 u8 reserved_at_88[0x18]; 4890 4891 u8 reserved_at_a0[0x8]; 4892 u8 table_id[0x18]; 4893 4894 u8 ignore_flow_level[0x1]; 4895 u8 reserved_at_c1[0x17]; 4896 u8 modify_enable_mask[0x8]; 4897 4898 u8 reserved_at_e0[0x20]; 4899 4900 u8 flow_index[0x20]; 4901 4902 u8 reserved_at_120[0xe0]; 4903 4904 struct mlx5_ifc_flow_context_bits flow_context; 4905 }; 4906 4907 struct mlx5_ifc_rts2rts_qp_out_bits { 4908 u8 status[0x8]; 4909 u8 reserved_at_8[0x18]; 4910 4911 u8 syndrome[0x20]; 4912 4913 u8 reserved_at_40[0x20]; 4914 u8 ece[0x20]; 4915 }; 4916 4917 struct mlx5_ifc_rts2rts_qp_in_bits { 4918 u8 opcode[0x10]; 4919 u8 uid[0x10]; 4920 4921 u8 reserved_at_20[0x10]; 4922 u8 op_mod[0x10]; 4923 4924 u8 reserved_at_40[0x8]; 4925 u8 qpn[0x18]; 4926 4927 u8 reserved_at_60[0x20]; 4928 4929 u8 opt_param_mask[0x20]; 4930 4931 u8 ece[0x20]; 4932 4933 struct mlx5_ifc_qpc_bits qpc; 4934 4935 u8 reserved_at_800[0x80]; 4936 }; 4937 4938 struct mlx5_ifc_rtr2rts_qp_out_bits { 4939 u8 status[0x8]; 4940 u8 reserved_at_8[0x18]; 4941 4942 u8 syndrome[0x20]; 4943 4944 u8 reserved_at_40[0x20]; 4945 u8 ece[0x20]; 4946 }; 4947 4948 struct mlx5_ifc_rtr2rts_qp_in_bits { 4949 u8 opcode[0x10]; 4950 u8 uid[0x10]; 4951 4952 u8 reserved_at_20[0x10]; 4953 u8 op_mod[0x10]; 4954 4955 u8 reserved_at_40[0x8]; 4956 u8 qpn[0x18]; 4957 4958 u8 reserved_at_60[0x20]; 4959 4960 u8 opt_param_mask[0x20]; 4961 4962 u8 ece[0x20]; 4963 4964 struct mlx5_ifc_qpc_bits qpc; 4965 4966 u8 reserved_at_800[0x80]; 4967 }; 4968 4969 struct mlx5_ifc_rst2init_qp_out_bits { 4970 u8 status[0x8]; 4971 u8 reserved_at_8[0x18]; 4972 4973 u8 syndrome[0x20]; 4974 4975 u8 reserved_at_40[0x20]; 4976 u8 ece[0x20]; 4977 }; 4978 4979 struct mlx5_ifc_rst2init_qp_in_bits { 4980 u8 opcode[0x10]; 4981 u8 uid[0x10]; 4982 4983 u8 reserved_at_20[0x10]; 4984 u8 op_mod[0x10]; 4985 4986 u8 reserved_at_40[0x8]; 4987 u8 qpn[0x18]; 4988 4989 u8 reserved_at_60[0x20]; 4990 4991 u8 opt_param_mask[0x20]; 4992 4993 u8 ece[0x20]; 4994 4995 struct mlx5_ifc_qpc_bits qpc; 4996 4997 u8 reserved_at_800[0x80]; 4998 }; 4999 5000 struct mlx5_ifc_query_xrq_out_bits { 5001 u8 status[0x8]; 5002 u8 reserved_at_8[0x18]; 5003 5004 u8 syndrome[0x20]; 5005 5006 u8 reserved_at_40[0x40]; 5007 5008 struct mlx5_ifc_xrqc_bits xrq_context; 5009 }; 5010 5011 struct mlx5_ifc_query_xrq_in_bits { 5012 u8 opcode[0x10]; 5013 u8 reserved_at_10[0x10]; 5014 5015 u8 reserved_at_20[0x10]; 5016 u8 op_mod[0x10]; 5017 5018 u8 reserved_at_40[0x8]; 5019 u8 xrqn[0x18]; 5020 5021 u8 reserved_at_60[0x20]; 5022 }; 5023 5024 struct mlx5_ifc_query_xrc_srq_out_bits { 5025 u8 status[0x8]; 5026 u8 reserved_at_8[0x18]; 5027 5028 u8 syndrome[0x20]; 5029 5030 u8 reserved_at_40[0x40]; 5031 5032 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 5033 5034 u8 reserved_at_280[0x600]; 5035 5036 u8 pas[][0x40]; 5037 }; 5038 5039 struct mlx5_ifc_query_xrc_srq_in_bits { 5040 u8 opcode[0x10]; 5041 u8 reserved_at_10[0x10]; 5042 5043 u8 reserved_at_20[0x10]; 5044 u8 op_mod[0x10]; 5045 5046 u8 reserved_at_40[0x8]; 5047 u8 xrc_srqn[0x18]; 5048 5049 u8 reserved_at_60[0x20]; 5050 }; 5051 5052 enum { 5053 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0, 5054 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1, 5055 }; 5056 5057 struct mlx5_ifc_query_vport_state_out_bits { 5058 u8 status[0x8]; 5059 u8 reserved_at_8[0x18]; 5060 5061 u8 syndrome[0x20]; 5062 5063 u8 reserved_at_40[0x20]; 5064 5065 u8 reserved_at_60[0x18]; 5066 u8 admin_state[0x4]; 5067 u8 state[0x4]; 5068 }; 5069 5070 enum { 5071 MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT = 0x0, 5072 MLX5_VPORT_STATE_OP_MOD_ESW_VPORT = 0x1, 5073 MLX5_VPORT_STATE_OP_MOD_UPLINK = 0x2, 5074 }; 5075 5076 struct mlx5_ifc_arm_monitor_counter_in_bits { 5077 u8 opcode[0x10]; 5078 u8 uid[0x10]; 5079 5080 u8 reserved_at_20[0x10]; 5081 u8 op_mod[0x10]; 5082 5083 u8 reserved_at_40[0x20]; 5084 5085 u8 reserved_at_60[0x20]; 5086 }; 5087 5088 struct mlx5_ifc_arm_monitor_counter_out_bits { 5089 u8 status[0x8]; 5090 u8 reserved_at_8[0x18]; 5091 5092 u8 syndrome[0x20]; 5093 5094 u8 reserved_at_40[0x40]; 5095 }; 5096 5097 enum { 5098 MLX5_QUERY_MONITOR_CNT_TYPE_PPCNT = 0x0, 5099 MLX5_QUERY_MONITOR_CNT_TYPE_Q_COUNTER = 0x1, 5100 }; 5101 5102 enum mlx5_monitor_counter_ppcnt { 5103 MLX5_QUERY_MONITOR_PPCNT_IN_RANGE_LENGTH_ERRORS = 0x0, 5104 MLX5_QUERY_MONITOR_PPCNT_OUT_OF_RANGE_LENGTH_FIELD = 0x1, 5105 MLX5_QUERY_MONITOR_PPCNT_FRAME_TOO_LONG_ERRORS = 0x2, 5106 MLX5_QUERY_MONITOR_PPCNT_FRAME_CHECK_SEQUENCE_ERRORS = 0x3, 5107 MLX5_QUERY_MONITOR_PPCNT_ALIGNMENT_ERRORS = 0x4, 5108 MLX5_QUERY_MONITOR_PPCNT_IF_OUT_DISCARDS = 0x5, 5109 }; 5110 5111 enum { 5112 MLX5_QUERY_MONITOR_Q_COUNTER_RX_OUT_OF_BUFFER = 0x4, 5113 }; 5114 5115 struct mlx5_ifc_monitor_counter_output_bits { 5116 u8 reserved_at_0[0x4]; 5117 u8 type[0x4]; 5118 u8 reserved_at_8[0x8]; 5119 u8 counter[0x10]; 5120 5121 u8 counter_group_id[0x20]; 5122 }; 5123 5124 #define MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 (6) 5125 #define MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1 (1) 5126 #define MLX5_CMD_SET_MONITOR_NUM_COUNTER (MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 +\ 5127 MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1) 5128 5129 struct mlx5_ifc_set_monitor_counter_in_bits { 5130 u8 opcode[0x10]; 5131 u8 uid[0x10]; 5132 5133 u8 reserved_at_20[0x10]; 5134 u8 op_mod[0x10]; 5135 5136 u8 reserved_at_40[0x10]; 5137 u8 num_of_counters[0x10]; 5138 5139 u8 reserved_at_60[0x20]; 5140 5141 struct mlx5_ifc_monitor_counter_output_bits monitor_counter[MLX5_CMD_SET_MONITOR_NUM_COUNTER]; 5142 }; 5143 5144 struct mlx5_ifc_set_monitor_counter_out_bits { 5145 u8 status[0x8]; 5146 u8 reserved_at_8[0x18]; 5147 5148 u8 syndrome[0x20]; 5149 5150 u8 reserved_at_40[0x40]; 5151 }; 5152 5153 struct mlx5_ifc_query_vport_state_in_bits { 5154 u8 opcode[0x10]; 5155 u8 reserved_at_10[0x10]; 5156 5157 u8 reserved_at_20[0x10]; 5158 u8 op_mod[0x10]; 5159 5160 u8 other_vport[0x1]; 5161 u8 reserved_at_41[0xf]; 5162 u8 vport_number[0x10]; 5163 5164 u8 reserved_at_60[0x20]; 5165 }; 5166 5167 struct mlx5_ifc_query_vnic_env_out_bits { 5168 u8 status[0x8]; 5169 u8 reserved_at_8[0x18]; 5170 5171 u8 syndrome[0x20]; 5172 5173 u8 reserved_at_40[0x40]; 5174 5175 struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env; 5176 }; 5177 5178 enum { 5179 MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS = 0x0, 5180 }; 5181 5182 struct mlx5_ifc_query_vnic_env_in_bits { 5183 u8 opcode[0x10]; 5184 u8 reserved_at_10[0x10]; 5185 5186 u8 reserved_at_20[0x10]; 5187 u8 op_mod[0x10]; 5188 5189 u8 other_vport[0x1]; 5190 u8 reserved_at_41[0xf]; 5191 u8 vport_number[0x10]; 5192 5193 u8 reserved_at_60[0x20]; 5194 }; 5195 5196 struct mlx5_ifc_query_vport_counter_out_bits { 5197 u8 status[0x8]; 5198 u8 reserved_at_8[0x18]; 5199 5200 u8 syndrome[0x20]; 5201 5202 u8 reserved_at_40[0x40]; 5203 5204 struct mlx5_ifc_traffic_counter_bits received_errors; 5205 5206 struct mlx5_ifc_traffic_counter_bits transmit_errors; 5207 5208 struct mlx5_ifc_traffic_counter_bits received_ib_unicast; 5209 5210 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast; 5211 5212 struct mlx5_ifc_traffic_counter_bits received_ib_multicast; 5213 5214 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast; 5215 5216 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast; 5217 5218 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast; 5219 5220 struct mlx5_ifc_traffic_counter_bits received_eth_unicast; 5221 5222 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast; 5223 5224 struct mlx5_ifc_traffic_counter_bits received_eth_multicast; 5225 5226 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast; 5227 5228 struct mlx5_ifc_traffic_counter_bits local_loopback; 5229 5230 u8 reserved_at_700[0x980]; 5231 }; 5232 5233 enum { 5234 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0, 5235 }; 5236 5237 struct mlx5_ifc_query_vport_counter_in_bits { 5238 u8 opcode[0x10]; 5239 u8 reserved_at_10[0x10]; 5240 5241 u8 reserved_at_20[0x10]; 5242 u8 op_mod[0x10]; 5243 5244 u8 other_vport[0x1]; 5245 u8 reserved_at_41[0xb]; 5246 u8 port_num[0x4]; 5247 u8 vport_number[0x10]; 5248 5249 u8 reserved_at_60[0x60]; 5250 5251 u8 clear[0x1]; 5252 u8 reserved_at_c1[0x1f]; 5253 5254 u8 reserved_at_e0[0x20]; 5255 }; 5256 5257 struct mlx5_ifc_query_tis_out_bits { 5258 u8 status[0x8]; 5259 u8 reserved_at_8[0x18]; 5260 5261 u8 syndrome[0x20]; 5262 5263 u8 reserved_at_40[0x40]; 5264 5265 struct mlx5_ifc_tisc_bits tis_context; 5266 }; 5267 5268 struct mlx5_ifc_query_tis_in_bits { 5269 u8 opcode[0x10]; 5270 u8 reserved_at_10[0x10]; 5271 5272 u8 reserved_at_20[0x10]; 5273 u8 op_mod[0x10]; 5274 5275 u8 reserved_at_40[0x8]; 5276 u8 tisn[0x18]; 5277 5278 u8 reserved_at_60[0x20]; 5279 }; 5280 5281 struct mlx5_ifc_query_tir_out_bits { 5282 u8 status[0x8]; 5283 u8 reserved_at_8[0x18]; 5284 5285 u8 syndrome[0x20]; 5286 5287 u8 reserved_at_40[0xc0]; 5288 5289 struct mlx5_ifc_tirc_bits tir_context; 5290 }; 5291 5292 struct mlx5_ifc_query_tir_in_bits { 5293 u8 opcode[0x10]; 5294 u8 reserved_at_10[0x10]; 5295 5296 u8 reserved_at_20[0x10]; 5297 u8 op_mod[0x10]; 5298 5299 u8 reserved_at_40[0x8]; 5300 u8 tirn[0x18]; 5301 5302 u8 reserved_at_60[0x20]; 5303 }; 5304 5305 struct mlx5_ifc_query_srq_out_bits { 5306 u8 status[0x8]; 5307 u8 reserved_at_8[0x18]; 5308 5309 u8 syndrome[0x20]; 5310 5311 u8 reserved_at_40[0x40]; 5312 5313 struct mlx5_ifc_srqc_bits srq_context_entry; 5314 5315 u8 reserved_at_280[0x600]; 5316 5317 u8 pas[][0x40]; 5318 }; 5319 5320 struct mlx5_ifc_query_srq_in_bits { 5321 u8 opcode[0x10]; 5322 u8 reserved_at_10[0x10]; 5323 5324 u8 reserved_at_20[0x10]; 5325 u8 op_mod[0x10]; 5326 5327 u8 reserved_at_40[0x8]; 5328 u8 srqn[0x18]; 5329 5330 u8 reserved_at_60[0x20]; 5331 }; 5332 5333 struct mlx5_ifc_query_sq_out_bits { 5334 u8 status[0x8]; 5335 u8 reserved_at_8[0x18]; 5336 5337 u8 syndrome[0x20]; 5338 5339 u8 reserved_at_40[0xc0]; 5340 5341 struct mlx5_ifc_sqc_bits sq_context; 5342 }; 5343 5344 struct mlx5_ifc_query_sq_in_bits { 5345 u8 opcode[0x10]; 5346 u8 reserved_at_10[0x10]; 5347 5348 u8 reserved_at_20[0x10]; 5349 u8 op_mod[0x10]; 5350 5351 u8 reserved_at_40[0x8]; 5352 u8 sqn[0x18]; 5353 5354 u8 reserved_at_60[0x20]; 5355 }; 5356 5357 struct mlx5_ifc_query_special_contexts_out_bits { 5358 u8 status[0x8]; 5359 u8 reserved_at_8[0x18]; 5360 5361 u8 syndrome[0x20]; 5362 5363 u8 dump_fill_mkey[0x20]; 5364 5365 u8 resd_lkey[0x20]; 5366 5367 u8 null_mkey[0x20]; 5368 5369 u8 terminate_scatter_list_mkey[0x20]; 5370 5371 u8 repeated_mkey[0x20]; 5372 5373 u8 reserved_at_a0[0x20]; 5374 }; 5375 5376 struct mlx5_ifc_query_special_contexts_in_bits { 5377 u8 opcode[0x10]; 5378 u8 reserved_at_10[0x10]; 5379 5380 u8 reserved_at_20[0x10]; 5381 u8 op_mod[0x10]; 5382 5383 u8 reserved_at_40[0x40]; 5384 }; 5385 5386 struct mlx5_ifc_query_scheduling_element_out_bits { 5387 u8 opcode[0x10]; 5388 u8 reserved_at_10[0x10]; 5389 5390 u8 reserved_at_20[0x10]; 5391 u8 op_mod[0x10]; 5392 5393 u8 reserved_at_40[0xc0]; 5394 5395 struct mlx5_ifc_scheduling_context_bits scheduling_context; 5396 5397 u8 reserved_at_300[0x100]; 5398 }; 5399 5400 enum { 5401 SCHEDULING_HIERARCHY_E_SWITCH = 0x2, 5402 SCHEDULING_HIERARCHY_NIC = 0x3, 5403 }; 5404 5405 struct mlx5_ifc_query_scheduling_element_in_bits { 5406 u8 opcode[0x10]; 5407 u8 reserved_at_10[0x10]; 5408 5409 u8 reserved_at_20[0x10]; 5410 u8 op_mod[0x10]; 5411 5412 u8 scheduling_hierarchy[0x8]; 5413 u8 reserved_at_48[0x18]; 5414 5415 u8 scheduling_element_id[0x20]; 5416 5417 u8 reserved_at_80[0x180]; 5418 }; 5419 5420 struct mlx5_ifc_query_rqt_out_bits { 5421 u8 status[0x8]; 5422 u8 reserved_at_8[0x18]; 5423 5424 u8 syndrome[0x20]; 5425 5426 u8 reserved_at_40[0xc0]; 5427 5428 struct mlx5_ifc_rqtc_bits rqt_context; 5429 }; 5430 5431 struct mlx5_ifc_query_rqt_in_bits { 5432 u8 opcode[0x10]; 5433 u8 reserved_at_10[0x10]; 5434 5435 u8 reserved_at_20[0x10]; 5436 u8 op_mod[0x10]; 5437 5438 u8 reserved_at_40[0x8]; 5439 u8 rqtn[0x18]; 5440 5441 u8 reserved_at_60[0x20]; 5442 }; 5443 5444 struct mlx5_ifc_query_rq_out_bits { 5445 u8 status[0x8]; 5446 u8 reserved_at_8[0x18]; 5447 5448 u8 syndrome[0x20]; 5449 5450 u8 reserved_at_40[0xc0]; 5451 5452 struct mlx5_ifc_rqc_bits rq_context; 5453 }; 5454 5455 struct mlx5_ifc_query_rq_in_bits { 5456 u8 opcode[0x10]; 5457 u8 reserved_at_10[0x10]; 5458 5459 u8 reserved_at_20[0x10]; 5460 u8 op_mod[0x10]; 5461 5462 u8 reserved_at_40[0x8]; 5463 u8 rqn[0x18]; 5464 5465 u8 reserved_at_60[0x20]; 5466 }; 5467 5468 struct mlx5_ifc_query_roce_address_out_bits { 5469 u8 status[0x8]; 5470 u8 reserved_at_8[0x18]; 5471 5472 u8 syndrome[0x20]; 5473 5474 u8 reserved_at_40[0x40]; 5475 5476 struct mlx5_ifc_roce_addr_layout_bits roce_address; 5477 }; 5478 5479 struct mlx5_ifc_query_roce_address_in_bits { 5480 u8 opcode[0x10]; 5481 u8 reserved_at_10[0x10]; 5482 5483 u8 reserved_at_20[0x10]; 5484 u8 op_mod[0x10]; 5485 5486 u8 roce_address_index[0x10]; 5487 u8 reserved_at_50[0xc]; 5488 u8 vhca_port_num[0x4]; 5489 5490 u8 reserved_at_60[0x20]; 5491 }; 5492 5493 struct mlx5_ifc_query_rmp_out_bits { 5494 u8 status[0x8]; 5495 u8 reserved_at_8[0x18]; 5496 5497 u8 syndrome[0x20]; 5498 5499 u8 reserved_at_40[0xc0]; 5500 5501 struct mlx5_ifc_rmpc_bits rmp_context; 5502 }; 5503 5504 struct mlx5_ifc_query_rmp_in_bits { 5505 u8 opcode[0x10]; 5506 u8 reserved_at_10[0x10]; 5507 5508 u8 reserved_at_20[0x10]; 5509 u8 op_mod[0x10]; 5510 5511 u8 reserved_at_40[0x8]; 5512 u8 rmpn[0x18]; 5513 5514 u8 reserved_at_60[0x20]; 5515 }; 5516 5517 struct mlx5_ifc_cqe_error_syndrome_bits { 5518 u8 hw_error_syndrome[0x8]; 5519 u8 hw_syndrome_type[0x4]; 5520 u8 reserved_at_c[0x4]; 5521 u8 vendor_error_syndrome[0x8]; 5522 u8 syndrome[0x8]; 5523 }; 5524 5525 struct mlx5_ifc_qp_context_extension_bits { 5526 u8 reserved_at_0[0x60]; 5527 5528 struct mlx5_ifc_cqe_error_syndrome_bits error_syndrome; 5529 5530 u8 reserved_at_80[0x580]; 5531 }; 5532 5533 struct mlx5_ifc_qpc_extension_and_pas_list_in_bits { 5534 struct mlx5_ifc_qp_context_extension_bits qpc_data_extension; 5535 5536 u8 pas[0][0x40]; 5537 }; 5538 5539 struct mlx5_ifc_qp_pas_list_in_bits { 5540 struct mlx5_ifc_cmd_pas_bits pas[0]; 5541 }; 5542 5543 union mlx5_ifc_qp_pas_or_qpc_ext_and_pas_bits { 5544 struct mlx5_ifc_qp_pas_list_in_bits qp_pas_list; 5545 struct mlx5_ifc_qpc_extension_and_pas_list_in_bits qpc_ext_and_pas_list; 5546 }; 5547 5548 struct mlx5_ifc_query_qp_out_bits { 5549 u8 status[0x8]; 5550 u8 reserved_at_8[0x18]; 5551 5552 u8 syndrome[0x20]; 5553 5554 u8 reserved_at_40[0x40]; 5555 5556 u8 opt_param_mask[0x20]; 5557 5558 u8 ece[0x20]; 5559 5560 struct mlx5_ifc_qpc_bits qpc; 5561 5562 u8 reserved_at_800[0x80]; 5563 5564 union mlx5_ifc_qp_pas_or_qpc_ext_and_pas_bits qp_pas_or_qpc_ext_and_pas; 5565 }; 5566 5567 struct mlx5_ifc_query_qp_in_bits { 5568 u8 opcode[0x10]; 5569 u8 reserved_at_10[0x10]; 5570 5571 u8 reserved_at_20[0x10]; 5572 u8 op_mod[0x10]; 5573 5574 u8 qpc_ext[0x1]; 5575 u8 reserved_at_41[0x7]; 5576 u8 qpn[0x18]; 5577 5578 u8 reserved_at_60[0x20]; 5579 }; 5580 5581 struct mlx5_ifc_query_q_counter_out_bits { 5582 u8 status[0x8]; 5583 u8 reserved_at_8[0x18]; 5584 5585 u8 syndrome[0x20]; 5586 5587 u8 reserved_at_40[0x40]; 5588 5589 u8 rx_write_requests[0x20]; 5590 5591 u8 reserved_at_a0[0x20]; 5592 5593 u8 rx_read_requests[0x20]; 5594 5595 u8 reserved_at_e0[0x20]; 5596 5597 u8 rx_atomic_requests[0x20]; 5598 5599 u8 reserved_at_120[0x20]; 5600 5601 u8 rx_dct_connect[0x20]; 5602 5603 u8 reserved_at_160[0x20]; 5604 5605 u8 out_of_buffer[0x20]; 5606 5607 u8 reserved_at_1a0[0x20]; 5608 5609 u8 out_of_sequence[0x20]; 5610 5611 u8 reserved_at_1e0[0x20]; 5612 5613 u8 duplicate_request[0x20]; 5614 5615 u8 reserved_at_220[0x20]; 5616 5617 u8 rnr_nak_retry_err[0x20]; 5618 5619 u8 reserved_at_260[0x20]; 5620 5621 u8 packet_seq_err[0x20]; 5622 5623 u8 reserved_at_2a0[0x20]; 5624 5625 u8 implied_nak_seq_err[0x20]; 5626 5627 u8 reserved_at_2e0[0x20]; 5628 5629 u8 local_ack_timeout_err[0x20]; 5630 5631 u8 reserved_at_320[0xa0]; 5632 5633 u8 resp_local_length_error[0x20]; 5634 5635 u8 req_local_length_error[0x20]; 5636 5637 u8 resp_local_qp_error[0x20]; 5638 5639 u8 local_operation_error[0x20]; 5640 5641 u8 resp_local_protection[0x20]; 5642 5643 u8 req_local_protection[0x20]; 5644 5645 u8 resp_cqe_error[0x20]; 5646 5647 u8 req_cqe_error[0x20]; 5648 5649 u8 req_mw_binding[0x20]; 5650 5651 u8 req_bad_response[0x20]; 5652 5653 u8 req_remote_invalid_request[0x20]; 5654 5655 u8 resp_remote_invalid_request[0x20]; 5656 5657 u8 req_remote_access_errors[0x20]; 5658 5659 u8 resp_remote_access_errors[0x20]; 5660 5661 u8 req_remote_operation_errors[0x20]; 5662 5663 u8 req_transport_retries_exceeded[0x20]; 5664 5665 u8 cq_overflow[0x20]; 5666 5667 u8 resp_cqe_flush_error[0x20]; 5668 5669 u8 req_cqe_flush_error[0x20]; 5670 5671 u8 reserved_at_620[0x20]; 5672 5673 u8 roce_adp_retrans[0x20]; 5674 5675 u8 roce_adp_retrans_to[0x20]; 5676 5677 u8 roce_slow_restart[0x20]; 5678 5679 u8 roce_slow_restart_cnps[0x20]; 5680 5681 u8 roce_slow_restart_trans[0x20]; 5682 5683 u8 reserved_at_6e0[0x120]; 5684 }; 5685 5686 struct mlx5_ifc_query_q_counter_in_bits { 5687 u8 opcode[0x10]; 5688 u8 reserved_at_10[0x10]; 5689 5690 u8 reserved_at_20[0x10]; 5691 u8 op_mod[0x10]; 5692 5693 u8 other_vport[0x1]; 5694 u8 reserved_at_41[0xf]; 5695 u8 vport_number[0x10]; 5696 5697 u8 reserved_at_60[0x60]; 5698 5699 u8 clear[0x1]; 5700 u8 aggregate[0x1]; 5701 u8 reserved_at_c2[0x1e]; 5702 5703 u8 reserved_at_e0[0x18]; 5704 u8 counter_set_id[0x8]; 5705 }; 5706 5707 struct mlx5_ifc_query_pages_out_bits { 5708 u8 status[0x8]; 5709 u8 reserved_at_8[0x18]; 5710 5711 u8 syndrome[0x20]; 5712 5713 u8 embedded_cpu_function[0x1]; 5714 u8 reserved_at_41[0xf]; 5715 u8 function_id[0x10]; 5716 5717 u8 num_pages[0x20]; 5718 }; 5719 5720 enum { 5721 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1, 5722 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2, 5723 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3, 5724 }; 5725 5726 struct mlx5_ifc_query_pages_in_bits { 5727 u8 opcode[0x10]; 5728 u8 reserved_at_10[0x10]; 5729 5730 u8 reserved_at_20[0x10]; 5731 u8 op_mod[0x10]; 5732 5733 u8 embedded_cpu_function[0x1]; 5734 u8 reserved_at_41[0xf]; 5735 u8 function_id[0x10]; 5736 5737 u8 reserved_at_60[0x20]; 5738 }; 5739 5740 struct mlx5_ifc_query_nic_vport_context_out_bits { 5741 u8 status[0x8]; 5742 u8 reserved_at_8[0x18]; 5743 5744 u8 syndrome[0x20]; 5745 5746 u8 reserved_at_40[0x40]; 5747 5748 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 5749 }; 5750 5751 struct mlx5_ifc_query_nic_vport_context_in_bits { 5752 u8 opcode[0x10]; 5753 u8 reserved_at_10[0x10]; 5754 5755 u8 reserved_at_20[0x10]; 5756 u8 op_mod[0x10]; 5757 5758 u8 other_vport[0x1]; 5759 u8 reserved_at_41[0xf]; 5760 u8 vport_number[0x10]; 5761 5762 u8 reserved_at_60[0x5]; 5763 u8 allowed_list_type[0x3]; 5764 u8 reserved_at_68[0x18]; 5765 }; 5766 5767 struct mlx5_ifc_query_mkey_out_bits { 5768 u8 status[0x8]; 5769 u8 reserved_at_8[0x18]; 5770 5771 u8 syndrome[0x20]; 5772 5773 u8 reserved_at_40[0x40]; 5774 5775 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 5776 5777 u8 reserved_at_280[0x600]; 5778 5779 u8 bsf0_klm0_pas_mtt0_1[16][0x8]; 5780 5781 u8 bsf1_klm1_pas_mtt2_3[16][0x8]; 5782 }; 5783 5784 struct mlx5_ifc_query_mkey_in_bits { 5785 u8 opcode[0x10]; 5786 u8 reserved_at_10[0x10]; 5787 5788 u8 reserved_at_20[0x10]; 5789 u8 op_mod[0x10]; 5790 5791 u8 reserved_at_40[0x8]; 5792 u8 mkey_index[0x18]; 5793 5794 u8 pg_access[0x1]; 5795 u8 reserved_at_61[0x1f]; 5796 }; 5797 5798 struct mlx5_ifc_query_mad_demux_out_bits { 5799 u8 status[0x8]; 5800 u8 reserved_at_8[0x18]; 5801 5802 u8 syndrome[0x20]; 5803 5804 u8 reserved_at_40[0x40]; 5805 5806 u8 mad_dumux_parameters_block[0x20]; 5807 }; 5808 5809 struct mlx5_ifc_query_mad_demux_in_bits { 5810 u8 opcode[0x10]; 5811 u8 reserved_at_10[0x10]; 5812 5813 u8 reserved_at_20[0x10]; 5814 u8 op_mod[0x10]; 5815 5816 u8 reserved_at_40[0x40]; 5817 }; 5818 5819 struct mlx5_ifc_query_l2_table_entry_out_bits { 5820 u8 status[0x8]; 5821 u8 reserved_at_8[0x18]; 5822 5823 u8 syndrome[0x20]; 5824 5825 u8 reserved_at_40[0xa0]; 5826 5827 u8 reserved_at_e0[0x13]; 5828 u8 vlan_valid[0x1]; 5829 u8 vlan[0xc]; 5830 5831 struct mlx5_ifc_mac_address_layout_bits mac_address; 5832 5833 u8 reserved_at_140[0xc0]; 5834 }; 5835 5836 struct mlx5_ifc_query_l2_table_entry_in_bits { 5837 u8 opcode[0x10]; 5838 u8 reserved_at_10[0x10]; 5839 5840 u8 reserved_at_20[0x10]; 5841 u8 op_mod[0x10]; 5842 5843 u8 reserved_at_40[0x60]; 5844 5845 u8 reserved_at_a0[0x8]; 5846 u8 table_index[0x18]; 5847 5848 u8 reserved_at_c0[0x140]; 5849 }; 5850 5851 struct mlx5_ifc_query_issi_out_bits { 5852 u8 status[0x8]; 5853 u8 reserved_at_8[0x18]; 5854 5855 u8 syndrome[0x20]; 5856 5857 u8 reserved_at_40[0x10]; 5858 u8 current_issi[0x10]; 5859 5860 u8 reserved_at_60[0xa0]; 5861 5862 u8 reserved_at_100[76][0x8]; 5863 u8 supported_issi_dw0[0x20]; 5864 }; 5865 5866 struct mlx5_ifc_query_issi_in_bits { 5867 u8 opcode[0x10]; 5868 u8 reserved_at_10[0x10]; 5869 5870 u8 reserved_at_20[0x10]; 5871 u8 op_mod[0x10]; 5872 5873 u8 reserved_at_40[0x40]; 5874 }; 5875 5876 struct mlx5_ifc_set_driver_version_out_bits { 5877 u8 status[0x8]; 5878 u8 reserved_0[0x18]; 5879 5880 u8 syndrome[0x20]; 5881 u8 reserved_1[0x40]; 5882 }; 5883 5884 struct mlx5_ifc_set_driver_version_in_bits { 5885 u8 opcode[0x10]; 5886 u8 reserved_0[0x10]; 5887 5888 u8 reserved_1[0x10]; 5889 u8 op_mod[0x10]; 5890 5891 u8 reserved_2[0x40]; 5892 u8 driver_version[64][0x8]; 5893 }; 5894 5895 struct mlx5_ifc_query_hca_vport_pkey_out_bits { 5896 u8 status[0x8]; 5897 u8 reserved_at_8[0x18]; 5898 5899 u8 syndrome[0x20]; 5900 5901 u8 reserved_at_40[0x40]; 5902 5903 struct mlx5_ifc_pkey_bits pkey[]; 5904 }; 5905 5906 struct mlx5_ifc_query_hca_vport_pkey_in_bits { 5907 u8 opcode[0x10]; 5908 u8 reserved_at_10[0x10]; 5909 5910 u8 reserved_at_20[0x10]; 5911 u8 op_mod[0x10]; 5912 5913 u8 other_vport[0x1]; 5914 u8 reserved_at_41[0xb]; 5915 u8 port_num[0x4]; 5916 u8 vport_number[0x10]; 5917 5918 u8 reserved_at_60[0x10]; 5919 u8 pkey_index[0x10]; 5920 }; 5921 5922 enum { 5923 MLX5_HCA_VPORT_SEL_PORT_GUID = 1 << 0, 5924 MLX5_HCA_VPORT_SEL_NODE_GUID = 1 << 1, 5925 MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2, 5926 }; 5927 5928 struct mlx5_ifc_query_hca_vport_gid_out_bits { 5929 u8 status[0x8]; 5930 u8 reserved_at_8[0x18]; 5931 5932 u8 syndrome[0x20]; 5933 5934 u8 reserved_at_40[0x20]; 5935 5936 u8 gids_num[0x10]; 5937 u8 reserved_at_70[0x10]; 5938 5939 struct mlx5_ifc_array128_auto_bits gid[]; 5940 }; 5941 5942 struct mlx5_ifc_query_hca_vport_gid_in_bits { 5943 u8 opcode[0x10]; 5944 u8 reserved_at_10[0x10]; 5945 5946 u8 reserved_at_20[0x10]; 5947 u8 op_mod[0x10]; 5948 5949 u8 other_vport[0x1]; 5950 u8 reserved_at_41[0xb]; 5951 u8 port_num[0x4]; 5952 u8 vport_number[0x10]; 5953 5954 u8 reserved_at_60[0x10]; 5955 u8 gid_index[0x10]; 5956 }; 5957 5958 struct mlx5_ifc_query_hca_vport_context_out_bits { 5959 u8 status[0x8]; 5960 u8 reserved_at_8[0x18]; 5961 5962 u8 syndrome[0x20]; 5963 5964 u8 reserved_at_40[0x40]; 5965 5966 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 5967 }; 5968 5969 struct mlx5_ifc_query_hca_vport_context_in_bits { 5970 u8 opcode[0x10]; 5971 u8 reserved_at_10[0x10]; 5972 5973 u8 reserved_at_20[0x10]; 5974 u8 op_mod[0x10]; 5975 5976 u8 other_vport[0x1]; 5977 u8 reserved_at_41[0xb]; 5978 u8 port_num[0x4]; 5979 u8 vport_number[0x10]; 5980 5981 u8 reserved_at_60[0x20]; 5982 }; 5983 5984 struct mlx5_ifc_query_hca_cap_out_bits { 5985 u8 status[0x8]; 5986 u8 reserved_at_8[0x18]; 5987 5988 u8 syndrome[0x20]; 5989 5990 u8 reserved_at_40[0x40]; 5991 5992 union mlx5_ifc_hca_cap_union_bits capability; 5993 }; 5994 5995 struct mlx5_ifc_query_hca_cap_in_bits { 5996 u8 opcode[0x10]; 5997 u8 reserved_at_10[0x10]; 5998 5999 u8 reserved_at_20[0x10]; 6000 u8 op_mod[0x10]; 6001 6002 u8 other_function[0x1]; 6003 u8 ec_vf_function[0x1]; 6004 u8 reserved_at_42[0xe]; 6005 u8 function_id[0x10]; 6006 6007 u8 reserved_at_60[0x20]; 6008 }; 6009 6010 struct mlx5_ifc_other_hca_cap_bits { 6011 u8 roce[0x1]; 6012 u8 reserved_at_1[0x27f]; 6013 }; 6014 6015 struct mlx5_ifc_query_other_hca_cap_out_bits { 6016 u8 status[0x8]; 6017 u8 reserved_at_8[0x18]; 6018 6019 u8 syndrome[0x20]; 6020 6021 u8 reserved_at_40[0x40]; 6022 6023 struct mlx5_ifc_other_hca_cap_bits other_capability; 6024 }; 6025 6026 struct mlx5_ifc_query_other_hca_cap_in_bits { 6027 u8 opcode[0x10]; 6028 u8 reserved_at_10[0x10]; 6029 6030 u8 reserved_at_20[0x10]; 6031 u8 op_mod[0x10]; 6032 6033 u8 reserved_at_40[0x10]; 6034 u8 function_id[0x10]; 6035 6036 u8 reserved_at_60[0x20]; 6037 }; 6038 6039 struct mlx5_ifc_modify_other_hca_cap_out_bits { 6040 u8 status[0x8]; 6041 u8 reserved_at_8[0x18]; 6042 6043 u8 syndrome[0x20]; 6044 6045 u8 reserved_at_40[0x40]; 6046 }; 6047 6048 struct mlx5_ifc_modify_other_hca_cap_in_bits { 6049 u8 opcode[0x10]; 6050 u8 reserved_at_10[0x10]; 6051 6052 u8 reserved_at_20[0x10]; 6053 u8 op_mod[0x10]; 6054 6055 u8 reserved_at_40[0x10]; 6056 u8 function_id[0x10]; 6057 u8 field_select[0x20]; 6058 6059 struct mlx5_ifc_other_hca_cap_bits other_capability; 6060 }; 6061 6062 struct mlx5_ifc_flow_table_context_bits { 6063 u8 reformat_en[0x1]; 6064 u8 decap_en[0x1]; 6065 u8 sw_owner[0x1]; 6066 u8 termination_table[0x1]; 6067 u8 table_miss_action[0x4]; 6068 u8 level[0x8]; 6069 u8 reserved_at_10[0x8]; 6070 u8 log_size[0x8]; 6071 6072 u8 reserved_at_20[0x8]; 6073 u8 table_miss_id[0x18]; 6074 6075 u8 reserved_at_40[0x8]; 6076 u8 lag_master_next_table_id[0x18]; 6077 6078 u8 reserved_at_60[0x60]; 6079 6080 u8 sw_owner_icm_root_1[0x40]; 6081 6082 u8 sw_owner_icm_root_0[0x40]; 6083 6084 }; 6085 6086 struct mlx5_ifc_query_flow_table_out_bits { 6087 u8 status[0x8]; 6088 u8 reserved_at_8[0x18]; 6089 6090 u8 syndrome[0x20]; 6091 6092 u8 reserved_at_40[0x80]; 6093 6094 struct mlx5_ifc_flow_table_context_bits flow_table_context; 6095 }; 6096 6097 struct mlx5_ifc_query_flow_table_in_bits { 6098 u8 opcode[0x10]; 6099 u8 reserved_at_10[0x10]; 6100 6101 u8 reserved_at_20[0x10]; 6102 u8 op_mod[0x10]; 6103 6104 u8 reserved_at_40[0x40]; 6105 6106 u8 table_type[0x8]; 6107 u8 reserved_at_88[0x18]; 6108 6109 u8 reserved_at_a0[0x8]; 6110 u8 table_id[0x18]; 6111 6112 u8 reserved_at_c0[0x140]; 6113 }; 6114 6115 struct mlx5_ifc_query_fte_out_bits { 6116 u8 status[0x8]; 6117 u8 reserved_at_8[0x18]; 6118 6119 u8 syndrome[0x20]; 6120 6121 u8 reserved_at_40[0x1c0]; 6122 6123 struct mlx5_ifc_flow_context_bits flow_context; 6124 }; 6125 6126 struct mlx5_ifc_query_fte_in_bits { 6127 u8 opcode[0x10]; 6128 u8 reserved_at_10[0x10]; 6129 6130 u8 reserved_at_20[0x10]; 6131 u8 op_mod[0x10]; 6132 6133 u8 reserved_at_40[0x40]; 6134 6135 u8 table_type[0x8]; 6136 u8 reserved_at_88[0x18]; 6137 6138 u8 reserved_at_a0[0x8]; 6139 u8 table_id[0x18]; 6140 6141 u8 reserved_at_c0[0x40]; 6142 6143 u8 flow_index[0x20]; 6144 6145 u8 reserved_at_120[0xe0]; 6146 }; 6147 6148 struct mlx5_ifc_match_definer_format_0_bits { 6149 u8 reserved_at_0[0x100]; 6150 6151 u8 metadata_reg_c_0[0x20]; 6152 6153 u8 metadata_reg_c_1[0x20]; 6154 6155 u8 outer_dmac_47_16[0x20]; 6156 6157 u8 outer_dmac_15_0[0x10]; 6158 u8 outer_ethertype[0x10]; 6159 6160 u8 reserved_at_180[0x1]; 6161 u8 sx_sniffer[0x1]; 6162 u8 functional_lb[0x1]; 6163 u8 outer_ip_frag[0x1]; 6164 u8 outer_qp_type[0x2]; 6165 u8 outer_encap_type[0x2]; 6166 u8 port_number[0x2]; 6167 u8 outer_l3_type[0x2]; 6168 u8 outer_l4_type[0x2]; 6169 u8 outer_first_vlan_type[0x2]; 6170 u8 outer_first_vlan_prio[0x3]; 6171 u8 outer_first_vlan_cfi[0x1]; 6172 u8 outer_first_vlan_vid[0xc]; 6173 6174 u8 outer_l4_type_ext[0x4]; 6175 u8 reserved_at_1a4[0x2]; 6176 u8 outer_ipsec_layer[0x2]; 6177 u8 outer_l2_type[0x2]; 6178 u8 force_lb[0x1]; 6179 u8 outer_l2_ok[0x1]; 6180 u8 outer_l3_ok[0x1]; 6181 u8 outer_l4_ok[0x1]; 6182 u8 outer_second_vlan_type[0x2]; 6183 u8 outer_second_vlan_prio[0x3]; 6184 u8 outer_second_vlan_cfi[0x1]; 6185 u8 outer_second_vlan_vid[0xc]; 6186 6187 u8 outer_smac_47_16[0x20]; 6188 6189 u8 outer_smac_15_0[0x10]; 6190 u8 inner_ipv4_checksum_ok[0x1]; 6191 u8 inner_l4_checksum_ok[0x1]; 6192 u8 outer_ipv4_checksum_ok[0x1]; 6193 u8 outer_l4_checksum_ok[0x1]; 6194 u8 inner_l3_ok[0x1]; 6195 u8 inner_l4_ok[0x1]; 6196 u8 outer_l3_ok_duplicate[0x1]; 6197 u8 outer_l4_ok_duplicate[0x1]; 6198 u8 outer_tcp_cwr[0x1]; 6199 u8 outer_tcp_ece[0x1]; 6200 u8 outer_tcp_urg[0x1]; 6201 u8 outer_tcp_ack[0x1]; 6202 u8 outer_tcp_psh[0x1]; 6203 u8 outer_tcp_rst[0x1]; 6204 u8 outer_tcp_syn[0x1]; 6205 u8 outer_tcp_fin[0x1]; 6206 }; 6207 6208 struct mlx5_ifc_match_definer_format_22_bits { 6209 u8 reserved_at_0[0x100]; 6210 6211 u8 outer_ip_src_addr[0x20]; 6212 6213 u8 outer_ip_dest_addr[0x20]; 6214 6215 u8 outer_l4_sport[0x10]; 6216 u8 outer_l4_dport[0x10]; 6217 6218 u8 reserved_at_160[0x1]; 6219 u8 sx_sniffer[0x1]; 6220 u8 functional_lb[0x1]; 6221 u8 outer_ip_frag[0x1]; 6222 u8 outer_qp_type[0x2]; 6223 u8 outer_encap_type[0x2]; 6224 u8 port_number[0x2]; 6225 u8 outer_l3_type[0x2]; 6226 u8 outer_l4_type[0x2]; 6227 u8 outer_first_vlan_type[0x2]; 6228 u8 outer_first_vlan_prio[0x3]; 6229 u8 outer_first_vlan_cfi[0x1]; 6230 u8 outer_first_vlan_vid[0xc]; 6231 6232 u8 metadata_reg_c_0[0x20]; 6233 6234 u8 outer_dmac_47_16[0x20]; 6235 6236 u8 outer_smac_47_16[0x20]; 6237 6238 u8 outer_smac_15_0[0x10]; 6239 u8 outer_dmac_15_0[0x10]; 6240 }; 6241 6242 struct mlx5_ifc_match_definer_format_23_bits { 6243 u8 reserved_at_0[0x100]; 6244 6245 u8 inner_ip_src_addr[0x20]; 6246 6247 u8 inner_ip_dest_addr[0x20]; 6248 6249 u8 inner_l4_sport[0x10]; 6250 u8 inner_l4_dport[0x10]; 6251 6252 u8 reserved_at_160[0x1]; 6253 u8 sx_sniffer[0x1]; 6254 u8 functional_lb[0x1]; 6255 u8 inner_ip_frag[0x1]; 6256 u8 inner_qp_type[0x2]; 6257 u8 inner_encap_type[0x2]; 6258 u8 port_number[0x2]; 6259 u8 inner_l3_type[0x2]; 6260 u8 inner_l4_type[0x2]; 6261 u8 inner_first_vlan_type[0x2]; 6262 u8 inner_first_vlan_prio[0x3]; 6263 u8 inner_first_vlan_cfi[0x1]; 6264 u8 inner_first_vlan_vid[0xc]; 6265 6266 u8 tunnel_header_0[0x20]; 6267 6268 u8 inner_dmac_47_16[0x20]; 6269 6270 u8 inner_smac_47_16[0x20]; 6271 6272 u8 inner_smac_15_0[0x10]; 6273 u8 inner_dmac_15_0[0x10]; 6274 }; 6275 6276 struct mlx5_ifc_match_definer_format_29_bits { 6277 u8 reserved_at_0[0xc0]; 6278 6279 u8 outer_ip_dest_addr[0x80]; 6280 6281 u8 outer_ip_src_addr[0x80]; 6282 6283 u8 outer_l4_sport[0x10]; 6284 u8 outer_l4_dport[0x10]; 6285 6286 u8 reserved_at_1e0[0x20]; 6287 }; 6288 6289 struct mlx5_ifc_match_definer_format_30_bits { 6290 u8 reserved_at_0[0xa0]; 6291 6292 u8 outer_ip_dest_addr[0x80]; 6293 6294 u8 outer_ip_src_addr[0x80]; 6295 6296 u8 outer_dmac_47_16[0x20]; 6297 6298 u8 outer_smac_47_16[0x20]; 6299 6300 u8 outer_smac_15_0[0x10]; 6301 u8 outer_dmac_15_0[0x10]; 6302 }; 6303 6304 struct mlx5_ifc_match_definer_format_31_bits { 6305 u8 reserved_at_0[0xc0]; 6306 6307 u8 inner_ip_dest_addr[0x80]; 6308 6309 u8 inner_ip_src_addr[0x80]; 6310 6311 u8 inner_l4_sport[0x10]; 6312 u8 inner_l4_dport[0x10]; 6313 6314 u8 reserved_at_1e0[0x20]; 6315 }; 6316 6317 struct mlx5_ifc_match_definer_format_32_bits { 6318 u8 reserved_at_0[0xa0]; 6319 6320 u8 inner_ip_dest_addr[0x80]; 6321 6322 u8 inner_ip_src_addr[0x80]; 6323 6324 u8 inner_dmac_47_16[0x20]; 6325 6326 u8 inner_smac_47_16[0x20]; 6327 6328 u8 inner_smac_15_0[0x10]; 6329 u8 inner_dmac_15_0[0x10]; 6330 }; 6331 6332 enum { 6333 MLX5_IFC_DEFINER_FORMAT_ID_SELECT = 61, 6334 }; 6335 6336 #define MLX5_IFC_DEFINER_FORMAT_OFFSET_UNUSED 0x0 6337 #define MLX5_IFC_DEFINER_FORMAT_OFFSET_OUTER_ETH_PKT_LEN 0x48 6338 #define MLX5_IFC_DEFINER_DW_SELECTORS_NUM 9 6339 #define MLX5_IFC_DEFINER_BYTE_SELECTORS_NUM 8 6340 6341 struct mlx5_ifc_match_definer_match_mask_bits { 6342 u8 reserved_at_1c0[5][0x20]; 6343 u8 match_dw_8[0x20]; 6344 u8 match_dw_7[0x20]; 6345 u8 match_dw_6[0x20]; 6346 u8 match_dw_5[0x20]; 6347 u8 match_dw_4[0x20]; 6348 u8 match_dw_3[0x20]; 6349 u8 match_dw_2[0x20]; 6350 u8 match_dw_1[0x20]; 6351 u8 match_dw_0[0x20]; 6352 6353 u8 match_byte_7[0x8]; 6354 u8 match_byte_6[0x8]; 6355 u8 match_byte_5[0x8]; 6356 u8 match_byte_4[0x8]; 6357 6358 u8 match_byte_3[0x8]; 6359 u8 match_byte_2[0x8]; 6360 u8 match_byte_1[0x8]; 6361 u8 match_byte_0[0x8]; 6362 }; 6363 6364 struct mlx5_ifc_match_definer_bits { 6365 u8 modify_field_select[0x40]; 6366 6367 u8 reserved_at_40[0x40]; 6368 6369 u8 reserved_at_80[0x10]; 6370 u8 format_id[0x10]; 6371 6372 u8 reserved_at_a0[0x60]; 6373 6374 u8 format_select_dw3[0x8]; 6375 u8 format_select_dw2[0x8]; 6376 u8 format_select_dw1[0x8]; 6377 u8 format_select_dw0[0x8]; 6378 6379 u8 format_select_dw7[0x8]; 6380 u8 format_select_dw6[0x8]; 6381 u8 format_select_dw5[0x8]; 6382 u8 format_select_dw4[0x8]; 6383 6384 u8 reserved_at_100[0x18]; 6385 u8 format_select_dw8[0x8]; 6386 6387 u8 reserved_at_120[0x20]; 6388 6389 u8 format_select_byte3[0x8]; 6390 u8 format_select_byte2[0x8]; 6391 u8 format_select_byte1[0x8]; 6392 u8 format_select_byte0[0x8]; 6393 6394 u8 format_select_byte7[0x8]; 6395 u8 format_select_byte6[0x8]; 6396 u8 format_select_byte5[0x8]; 6397 u8 format_select_byte4[0x8]; 6398 6399 u8 reserved_at_180[0x40]; 6400 6401 union { 6402 struct { 6403 u8 match_mask[16][0x20]; 6404 }; 6405 struct mlx5_ifc_match_definer_match_mask_bits match_mask_format; 6406 }; 6407 }; 6408 6409 struct mlx5_ifc_general_obj_create_param_bits { 6410 u8 alias_object[0x1]; 6411 u8 reserved_at_1[0x2]; 6412 u8 log_obj_range[0x5]; 6413 u8 reserved_at_8[0x18]; 6414 }; 6415 6416 struct mlx5_ifc_general_obj_query_param_bits { 6417 u8 alias_object[0x1]; 6418 u8 obj_offset[0x1f]; 6419 }; 6420 6421 struct mlx5_ifc_general_obj_in_cmd_hdr_bits { 6422 u8 opcode[0x10]; 6423 u8 uid[0x10]; 6424 6425 u8 vhca_tunnel_id[0x10]; 6426 u8 obj_type[0x10]; 6427 6428 u8 obj_id[0x20]; 6429 6430 union { 6431 struct mlx5_ifc_general_obj_create_param_bits create; 6432 struct mlx5_ifc_general_obj_query_param_bits query; 6433 } op_param; 6434 }; 6435 6436 struct mlx5_ifc_general_obj_out_cmd_hdr_bits { 6437 u8 status[0x8]; 6438 u8 reserved_at_8[0x18]; 6439 6440 u8 syndrome[0x20]; 6441 6442 u8 obj_id[0x20]; 6443 6444 u8 reserved_at_60[0x20]; 6445 }; 6446 6447 struct mlx5_ifc_allow_other_vhca_access_in_bits { 6448 u8 opcode[0x10]; 6449 u8 uid[0x10]; 6450 u8 reserved_at_20[0x10]; 6451 u8 op_mod[0x10]; 6452 u8 reserved_at_40[0x50]; 6453 u8 object_type_to_be_accessed[0x10]; 6454 u8 object_id_to_be_accessed[0x20]; 6455 u8 reserved_at_c0[0x40]; 6456 union { 6457 u8 access_key_raw[0x100]; 6458 u8 access_key[8][0x20]; 6459 }; 6460 }; 6461 6462 struct mlx5_ifc_allow_other_vhca_access_out_bits { 6463 u8 status[0x8]; 6464 u8 reserved_at_8[0x18]; 6465 u8 syndrome[0x20]; 6466 u8 reserved_at_40[0x40]; 6467 }; 6468 6469 struct mlx5_ifc_modify_header_arg_bits { 6470 u8 reserved_at_0[0x80]; 6471 6472 u8 reserved_at_80[0x8]; 6473 u8 access_pd[0x18]; 6474 }; 6475 6476 struct mlx5_ifc_create_modify_header_arg_in_bits { 6477 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 6478 struct mlx5_ifc_modify_header_arg_bits arg; 6479 }; 6480 6481 struct mlx5_ifc_create_match_definer_in_bits { 6482 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 6483 6484 struct mlx5_ifc_match_definer_bits obj_context; 6485 }; 6486 6487 struct mlx5_ifc_create_match_definer_out_bits { 6488 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 6489 }; 6490 6491 struct mlx5_ifc_alias_context_bits { 6492 u8 vhca_id_to_be_accessed[0x10]; 6493 u8 reserved_at_10[0xd]; 6494 u8 status[0x3]; 6495 u8 object_id_to_be_accessed[0x20]; 6496 u8 reserved_at_40[0x40]; 6497 union { 6498 u8 access_key_raw[0x100]; 6499 u8 access_key[8][0x20]; 6500 }; 6501 u8 metadata[0x80]; 6502 }; 6503 6504 struct mlx5_ifc_create_alias_obj_in_bits { 6505 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 6506 struct mlx5_ifc_alias_context_bits alias_ctx; 6507 }; 6508 6509 enum { 6510 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 6511 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 6512 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 6513 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3, 6514 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_3 = 0x4, 6515 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_4 = 0x5, 6516 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_5 = 0x6, 6517 }; 6518 6519 struct mlx5_ifc_query_flow_group_out_bits { 6520 u8 status[0x8]; 6521 u8 reserved_at_8[0x18]; 6522 6523 u8 syndrome[0x20]; 6524 6525 u8 reserved_at_40[0xa0]; 6526 6527 u8 start_flow_index[0x20]; 6528 6529 u8 reserved_at_100[0x20]; 6530 6531 u8 end_flow_index[0x20]; 6532 6533 u8 reserved_at_140[0xa0]; 6534 6535 u8 reserved_at_1e0[0x18]; 6536 u8 match_criteria_enable[0x8]; 6537 6538 struct mlx5_ifc_fte_match_param_bits match_criteria; 6539 6540 u8 reserved_at_1200[0xe00]; 6541 }; 6542 6543 struct mlx5_ifc_query_flow_group_in_bits { 6544 u8 opcode[0x10]; 6545 u8 reserved_at_10[0x10]; 6546 6547 u8 reserved_at_20[0x10]; 6548 u8 op_mod[0x10]; 6549 6550 u8 reserved_at_40[0x40]; 6551 6552 u8 table_type[0x8]; 6553 u8 reserved_at_88[0x18]; 6554 6555 u8 reserved_at_a0[0x8]; 6556 u8 table_id[0x18]; 6557 6558 u8 group_id[0x20]; 6559 6560 u8 reserved_at_e0[0x120]; 6561 }; 6562 6563 struct mlx5_ifc_query_flow_counter_out_bits { 6564 u8 status[0x8]; 6565 u8 reserved_at_8[0x18]; 6566 6567 u8 syndrome[0x20]; 6568 6569 u8 reserved_at_40[0x40]; 6570 6571 struct mlx5_ifc_traffic_counter_bits flow_statistics[]; 6572 }; 6573 6574 struct mlx5_ifc_query_flow_counter_in_bits { 6575 u8 opcode[0x10]; 6576 u8 reserved_at_10[0x10]; 6577 6578 u8 reserved_at_20[0x10]; 6579 u8 op_mod[0x10]; 6580 6581 u8 reserved_at_40[0x80]; 6582 6583 u8 clear[0x1]; 6584 u8 reserved_at_c1[0xf]; 6585 u8 num_of_counters[0x10]; 6586 6587 u8 flow_counter_id[0x20]; 6588 }; 6589 6590 struct mlx5_ifc_query_esw_vport_context_out_bits { 6591 u8 status[0x8]; 6592 u8 reserved_at_8[0x18]; 6593 6594 u8 syndrome[0x20]; 6595 6596 u8 reserved_at_40[0x40]; 6597 6598 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 6599 }; 6600 6601 struct mlx5_ifc_query_esw_vport_context_in_bits { 6602 u8 opcode[0x10]; 6603 u8 reserved_at_10[0x10]; 6604 6605 u8 reserved_at_20[0x10]; 6606 u8 op_mod[0x10]; 6607 6608 u8 other_vport[0x1]; 6609 u8 reserved_at_41[0xf]; 6610 u8 vport_number[0x10]; 6611 6612 u8 reserved_at_60[0x20]; 6613 }; 6614 6615 struct mlx5_ifc_modify_esw_vport_context_out_bits { 6616 u8 status[0x8]; 6617 u8 reserved_at_8[0x18]; 6618 6619 u8 syndrome[0x20]; 6620 6621 u8 reserved_at_40[0x40]; 6622 }; 6623 6624 struct mlx5_ifc_esw_vport_context_fields_select_bits { 6625 u8 reserved_at_0[0x1b]; 6626 u8 fdb_to_vport_reg_c_id[0x1]; 6627 u8 vport_cvlan_insert[0x1]; 6628 u8 vport_svlan_insert[0x1]; 6629 u8 vport_cvlan_strip[0x1]; 6630 u8 vport_svlan_strip[0x1]; 6631 }; 6632 6633 struct mlx5_ifc_modify_esw_vport_context_in_bits { 6634 u8 opcode[0x10]; 6635 u8 reserved_at_10[0x10]; 6636 6637 u8 reserved_at_20[0x10]; 6638 u8 op_mod[0x10]; 6639 6640 u8 other_vport[0x1]; 6641 u8 reserved_at_41[0xf]; 6642 u8 vport_number[0x10]; 6643 6644 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select; 6645 6646 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 6647 }; 6648 6649 struct mlx5_ifc_query_eq_out_bits { 6650 u8 status[0x8]; 6651 u8 reserved_at_8[0x18]; 6652 6653 u8 syndrome[0x20]; 6654 6655 u8 reserved_at_40[0x40]; 6656 6657 struct mlx5_ifc_eqc_bits eq_context_entry; 6658 6659 u8 reserved_at_280[0x40]; 6660 6661 u8 event_bitmask[0x40]; 6662 6663 u8 reserved_at_300[0x580]; 6664 6665 u8 pas[][0x40]; 6666 }; 6667 6668 struct mlx5_ifc_query_eq_in_bits { 6669 u8 opcode[0x10]; 6670 u8 reserved_at_10[0x10]; 6671 6672 u8 reserved_at_20[0x10]; 6673 u8 op_mod[0x10]; 6674 6675 u8 reserved_at_40[0x18]; 6676 u8 eq_number[0x8]; 6677 6678 u8 reserved_at_60[0x20]; 6679 }; 6680 6681 struct mlx5_ifc_packet_reformat_context_in_bits { 6682 u8 reformat_type[0x8]; 6683 u8 reserved_at_8[0x4]; 6684 u8 reformat_param_0[0x4]; 6685 u8 reserved_at_10[0x6]; 6686 u8 reformat_data_size[0xa]; 6687 6688 u8 reformat_param_1[0x8]; 6689 u8 reserved_at_28[0x8]; 6690 u8 reformat_data[2][0x8]; 6691 6692 u8 more_reformat_data[][0x8]; 6693 }; 6694 6695 struct mlx5_ifc_query_packet_reformat_context_out_bits { 6696 u8 status[0x8]; 6697 u8 reserved_at_8[0x18]; 6698 6699 u8 syndrome[0x20]; 6700 6701 u8 reserved_at_40[0xa0]; 6702 6703 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context[]; 6704 }; 6705 6706 struct mlx5_ifc_query_packet_reformat_context_in_bits { 6707 u8 opcode[0x10]; 6708 u8 reserved_at_10[0x10]; 6709 6710 u8 reserved_at_20[0x10]; 6711 u8 op_mod[0x10]; 6712 6713 u8 packet_reformat_id[0x20]; 6714 6715 u8 reserved_at_60[0xa0]; 6716 }; 6717 6718 struct mlx5_ifc_alloc_packet_reformat_context_out_bits { 6719 u8 status[0x8]; 6720 u8 reserved_at_8[0x18]; 6721 6722 u8 syndrome[0x20]; 6723 6724 u8 packet_reformat_id[0x20]; 6725 6726 u8 reserved_at_60[0x20]; 6727 }; 6728 6729 enum { 6730 MLX5_REFORMAT_CONTEXT_ANCHOR_MAC_START = 0x1, 6731 MLX5_REFORMAT_CONTEXT_ANCHOR_IP_START = 0x7, 6732 MLX5_REFORMAT_CONTEXT_ANCHOR_TCP_UDP_START = 0x9, 6733 }; 6734 6735 enum mlx5_reformat_ctx_type { 6736 MLX5_REFORMAT_TYPE_L2_TO_VXLAN = 0x0, 6737 MLX5_REFORMAT_TYPE_L2_TO_NVGRE = 0x1, 6738 MLX5_REFORMAT_TYPE_L2_TO_L2_TUNNEL = 0x2, 6739 MLX5_REFORMAT_TYPE_L3_TUNNEL_TO_L2 = 0x3, 6740 MLX5_REFORMAT_TYPE_L2_TO_L3_TUNNEL = 0x4, 6741 MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_IPV4 = 0x5, 6742 MLX5_REFORMAT_TYPE_L2_TO_L3_ESP_TUNNEL = 0x6, 6743 MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_UDPV4 = 0x7, 6744 MLX5_REFORMAT_TYPE_DEL_ESP_TRANSPORT = 0x8, 6745 MLX5_REFORMAT_TYPE_L3_ESP_TUNNEL_TO_L2 = 0x9, 6746 MLX5_REFORMAT_TYPE_DEL_ESP_TRANSPORT_OVER_UDP = 0xa, 6747 MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_IPV6 = 0xb, 6748 MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_UDPV6 = 0xc, 6749 MLX5_REFORMAT_TYPE_INSERT_HDR = 0xf, 6750 MLX5_REFORMAT_TYPE_REMOVE_HDR = 0x10, 6751 MLX5_REFORMAT_TYPE_ADD_MACSEC = 0x11, 6752 MLX5_REFORMAT_TYPE_DEL_MACSEC = 0x12, 6753 }; 6754 6755 struct mlx5_ifc_alloc_packet_reformat_context_in_bits { 6756 u8 opcode[0x10]; 6757 u8 reserved_at_10[0x10]; 6758 6759 u8 reserved_at_20[0x10]; 6760 u8 op_mod[0x10]; 6761 6762 u8 reserved_at_40[0xa0]; 6763 6764 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context; 6765 }; 6766 6767 struct mlx5_ifc_dealloc_packet_reformat_context_out_bits { 6768 u8 status[0x8]; 6769 u8 reserved_at_8[0x18]; 6770 6771 u8 syndrome[0x20]; 6772 6773 u8 reserved_at_40[0x40]; 6774 }; 6775 6776 struct mlx5_ifc_dealloc_packet_reformat_context_in_bits { 6777 u8 opcode[0x10]; 6778 u8 reserved_at_10[0x10]; 6779 6780 u8 reserved_20[0x10]; 6781 u8 op_mod[0x10]; 6782 6783 u8 packet_reformat_id[0x20]; 6784 6785 u8 reserved_60[0x20]; 6786 }; 6787 6788 struct mlx5_ifc_set_action_in_bits { 6789 u8 action_type[0x4]; 6790 u8 field[0xc]; 6791 u8 reserved_at_10[0x3]; 6792 u8 offset[0x5]; 6793 u8 reserved_at_18[0x3]; 6794 u8 length[0x5]; 6795 6796 u8 data[0x20]; 6797 }; 6798 6799 struct mlx5_ifc_add_action_in_bits { 6800 u8 action_type[0x4]; 6801 u8 field[0xc]; 6802 u8 reserved_at_10[0x10]; 6803 6804 u8 data[0x20]; 6805 }; 6806 6807 struct mlx5_ifc_copy_action_in_bits { 6808 u8 action_type[0x4]; 6809 u8 src_field[0xc]; 6810 u8 reserved_at_10[0x3]; 6811 u8 src_offset[0x5]; 6812 u8 reserved_at_18[0x3]; 6813 u8 length[0x5]; 6814 6815 u8 reserved_at_20[0x4]; 6816 u8 dst_field[0xc]; 6817 u8 reserved_at_30[0x3]; 6818 u8 dst_offset[0x5]; 6819 u8 reserved_at_38[0x8]; 6820 }; 6821 6822 union mlx5_ifc_set_add_copy_action_in_auto_bits { 6823 struct mlx5_ifc_set_action_in_bits set_action_in; 6824 struct mlx5_ifc_add_action_in_bits add_action_in; 6825 struct mlx5_ifc_copy_action_in_bits copy_action_in; 6826 u8 reserved_at_0[0x40]; 6827 }; 6828 6829 enum { 6830 MLX5_ACTION_TYPE_SET = 0x1, 6831 MLX5_ACTION_TYPE_ADD = 0x2, 6832 MLX5_ACTION_TYPE_COPY = 0x3, 6833 }; 6834 6835 enum { 6836 MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16 = 0x1, 6837 MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0 = 0x2, 6838 MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE = 0x3, 6839 MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16 = 0x4, 6840 MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0 = 0x5, 6841 MLX5_ACTION_IN_FIELD_OUT_IP_DSCP = 0x6, 6842 MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS = 0x7, 6843 MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT = 0x8, 6844 MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT = 0x9, 6845 MLX5_ACTION_IN_FIELD_OUT_IP_TTL = 0xa, 6846 MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT = 0xb, 6847 MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT = 0xc, 6848 MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96 = 0xd, 6849 MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64 = 0xe, 6850 MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32 = 0xf, 6851 MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0 = 0x10, 6852 MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96 = 0x11, 6853 MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64 = 0x12, 6854 MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32 = 0x13, 6855 MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0 = 0x14, 6856 MLX5_ACTION_IN_FIELD_OUT_SIPV4 = 0x15, 6857 MLX5_ACTION_IN_FIELD_OUT_DIPV4 = 0x16, 6858 MLX5_ACTION_IN_FIELD_OUT_FIRST_VID = 0x17, 6859 MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47, 6860 MLX5_ACTION_IN_FIELD_METADATA_REG_A = 0x49, 6861 MLX5_ACTION_IN_FIELD_METADATA_REG_B = 0x50, 6862 MLX5_ACTION_IN_FIELD_METADATA_REG_C_0 = 0x51, 6863 MLX5_ACTION_IN_FIELD_METADATA_REG_C_1 = 0x52, 6864 MLX5_ACTION_IN_FIELD_METADATA_REG_C_2 = 0x53, 6865 MLX5_ACTION_IN_FIELD_METADATA_REG_C_3 = 0x54, 6866 MLX5_ACTION_IN_FIELD_METADATA_REG_C_4 = 0x55, 6867 MLX5_ACTION_IN_FIELD_METADATA_REG_C_5 = 0x56, 6868 MLX5_ACTION_IN_FIELD_METADATA_REG_C_6 = 0x57, 6869 MLX5_ACTION_IN_FIELD_METADATA_REG_C_7 = 0x58, 6870 MLX5_ACTION_IN_FIELD_OUT_TCP_SEQ_NUM = 0x59, 6871 MLX5_ACTION_IN_FIELD_OUT_TCP_ACK_NUM = 0x5B, 6872 MLX5_ACTION_IN_FIELD_IPSEC_SYNDROME = 0x5D, 6873 MLX5_ACTION_IN_FIELD_OUT_EMD_47_32 = 0x6F, 6874 MLX5_ACTION_IN_FIELD_OUT_EMD_31_0 = 0x70, 6875 }; 6876 6877 struct mlx5_ifc_alloc_modify_header_context_out_bits { 6878 u8 status[0x8]; 6879 u8 reserved_at_8[0x18]; 6880 6881 u8 syndrome[0x20]; 6882 6883 u8 modify_header_id[0x20]; 6884 6885 u8 reserved_at_60[0x20]; 6886 }; 6887 6888 struct mlx5_ifc_alloc_modify_header_context_in_bits { 6889 u8 opcode[0x10]; 6890 u8 reserved_at_10[0x10]; 6891 6892 u8 reserved_at_20[0x10]; 6893 u8 op_mod[0x10]; 6894 6895 u8 reserved_at_40[0x20]; 6896 6897 u8 table_type[0x8]; 6898 u8 reserved_at_68[0x10]; 6899 u8 num_of_actions[0x8]; 6900 6901 union mlx5_ifc_set_add_copy_action_in_auto_bits actions[]; 6902 }; 6903 6904 struct mlx5_ifc_dealloc_modify_header_context_out_bits { 6905 u8 status[0x8]; 6906 u8 reserved_at_8[0x18]; 6907 6908 u8 syndrome[0x20]; 6909 6910 u8 reserved_at_40[0x40]; 6911 }; 6912 6913 struct mlx5_ifc_dealloc_modify_header_context_in_bits { 6914 u8 opcode[0x10]; 6915 u8 reserved_at_10[0x10]; 6916 6917 u8 reserved_at_20[0x10]; 6918 u8 op_mod[0x10]; 6919 6920 u8 modify_header_id[0x20]; 6921 6922 u8 reserved_at_60[0x20]; 6923 }; 6924 6925 struct mlx5_ifc_query_modify_header_context_in_bits { 6926 u8 opcode[0x10]; 6927 u8 uid[0x10]; 6928 6929 u8 reserved_at_20[0x10]; 6930 u8 op_mod[0x10]; 6931 6932 u8 modify_header_id[0x20]; 6933 6934 u8 reserved_at_60[0xa0]; 6935 }; 6936 6937 struct mlx5_ifc_query_dct_out_bits { 6938 u8 status[0x8]; 6939 u8 reserved_at_8[0x18]; 6940 6941 u8 syndrome[0x20]; 6942 6943 u8 reserved_at_40[0x40]; 6944 6945 struct mlx5_ifc_dctc_bits dct_context_entry; 6946 6947 u8 reserved_at_280[0x180]; 6948 }; 6949 6950 struct mlx5_ifc_query_dct_in_bits { 6951 u8 opcode[0x10]; 6952 u8 reserved_at_10[0x10]; 6953 6954 u8 reserved_at_20[0x10]; 6955 u8 op_mod[0x10]; 6956 6957 u8 reserved_at_40[0x8]; 6958 u8 dctn[0x18]; 6959 6960 u8 reserved_at_60[0x20]; 6961 }; 6962 6963 struct mlx5_ifc_query_cq_out_bits { 6964 u8 status[0x8]; 6965 u8 reserved_at_8[0x18]; 6966 6967 u8 syndrome[0x20]; 6968 6969 u8 reserved_at_40[0x40]; 6970 6971 struct mlx5_ifc_cqc_bits cq_context; 6972 6973 u8 reserved_at_280[0x600]; 6974 6975 u8 pas[][0x40]; 6976 }; 6977 6978 struct mlx5_ifc_query_cq_in_bits { 6979 u8 opcode[0x10]; 6980 u8 reserved_at_10[0x10]; 6981 6982 u8 reserved_at_20[0x10]; 6983 u8 op_mod[0x10]; 6984 6985 u8 reserved_at_40[0x8]; 6986 u8 cqn[0x18]; 6987 6988 u8 reserved_at_60[0x20]; 6989 }; 6990 6991 struct mlx5_ifc_query_cong_status_out_bits { 6992 u8 status[0x8]; 6993 u8 reserved_at_8[0x18]; 6994 6995 u8 syndrome[0x20]; 6996 6997 u8 reserved_at_40[0x20]; 6998 6999 u8 enable[0x1]; 7000 u8 tag_enable[0x1]; 7001 u8 reserved_at_62[0x1e]; 7002 }; 7003 7004 struct mlx5_ifc_query_cong_status_in_bits { 7005 u8 opcode[0x10]; 7006 u8 reserved_at_10[0x10]; 7007 7008 u8 reserved_at_20[0x10]; 7009 u8 op_mod[0x10]; 7010 7011 u8 reserved_at_40[0x18]; 7012 u8 priority[0x4]; 7013 u8 cong_protocol[0x4]; 7014 7015 u8 reserved_at_60[0x20]; 7016 }; 7017 7018 struct mlx5_ifc_query_cong_statistics_out_bits { 7019 u8 status[0x8]; 7020 u8 reserved_at_8[0x18]; 7021 7022 u8 syndrome[0x20]; 7023 7024 u8 reserved_at_40[0x40]; 7025 7026 u8 rp_cur_flows[0x20]; 7027 7028 u8 sum_flows[0x20]; 7029 7030 u8 rp_cnp_ignored_high[0x20]; 7031 7032 u8 rp_cnp_ignored_low[0x20]; 7033 7034 u8 rp_cnp_handled_high[0x20]; 7035 7036 u8 rp_cnp_handled_low[0x20]; 7037 7038 u8 reserved_at_140[0x100]; 7039 7040 u8 time_stamp_high[0x20]; 7041 7042 u8 time_stamp_low[0x20]; 7043 7044 u8 accumulators_period[0x20]; 7045 7046 u8 np_ecn_marked_roce_packets_high[0x20]; 7047 7048 u8 np_ecn_marked_roce_packets_low[0x20]; 7049 7050 u8 np_cnp_sent_high[0x20]; 7051 7052 u8 np_cnp_sent_low[0x20]; 7053 7054 u8 reserved_at_320[0x560]; 7055 }; 7056 7057 struct mlx5_ifc_query_cong_statistics_in_bits { 7058 u8 opcode[0x10]; 7059 u8 reserved_at_10[0x10]; 7060 7061 u8 reserved_at_20[0x10]; 7062 u8 op_mod[0x10]; 7063 7064 u8 clear[0x1]; 7065 u8 reserved_at_41[0x1f]; 7066 7067 u8 reserved_at_60[0x20]; 7068 }; 7069 7070 struct mlx5_ifc_query_cong_params_out_bits { 7071 u8 status[0x8]; 7072 u8 reserved_at_8[0x18]; 7073 7074 u8 syndrome[0x20]; 7075 7076 u8 reserved_at_40[0x40]; 7077 7078 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 7079 }; 7080 7081 struct mlx5_ifc_query_cong_params_in_bits { 7082 u8 opcode[0x10]; 7083 u8 reserved_at_10[0x10]; 7084 7085 u8 reserved_at_20[0x10]; 7086 u8 op_mod[0x10]; 7087 7088 u8 reserved_at_40[0x1c]; 7089 u8 cong_protocol[0x4]; 7090 7091 u8 reserved_at_60[0x20]; 7092 }; 7093 7094 struct mlx5_ifc_query_adapter_out_bits { 7095 u8 status[0x8]; 7096 u8 reserved_at_8[0x18]; 7097 7098 u8 syndrome[0x20]; 7099 7100 u8 reserved_at_40[0x40]; 7101 7102 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct; 7103 }; 7104 7105 struct mlx5_ifc_query_adapter_in_bits { 7106 u8 opcode[0x10]; 7107 u8 reserved_at_10[0x10]; 7108 7109 u8 reserved_at_20[0x10]; 7110 u8 op_mod[0x10]; 7111 7112 u8 reserved_at_40[0x40]; 7113 }; 7114 7115 struct mlx5_ifc_qp_2rst_out_bits { 7116 u8 status[0x8]; 7117 u8 reserved_at_8[0x18]; 7118 7119 u8 syndrome[0x20]; 7120 7121 u8 reserved_at_40[0x40]; 7122 }; 7123 7124 struct mlx5_ifc_qp_2rst_in_bits { 7125 u8 opcode[0x10]; 7126 u8 uid[0x10]; 7127 7128 u8 reserved_at_20[0x10]; 7129 u8 op_mod[0x10]; 7130 7131 u8 reserved_at_40[0x8]; 7132 u8 qpn[0x18]; 7133 7134 u8 reserved_at_60[0x20]; 7135 }; 7136 7137 struct mlx5_ifc_qp_2err_out_bits { 7138 u8 status[0x8]; 7139 u8 reserved_at_8[0x18]; 7140 7141 u8 syndrome[0x20]; 7142 7143 u8 reserved_at_40[0x40]; 7144 }; 7145 7146 struct mlx5_ifc_qp_2err_in_bits { 7147 u8 opcode[0x10]; 7148 u8 uid[0x10]; 7149 7150 u8 reserved_at_20[0x10]; 7151 u8 op_mod[0x10]; 7152 7153 u8 reserved_at_40[0x8]; 7154 u8 qpn[0x18]; 7155 7156 u8 reserved_at_60[0x20]; 7157 }; 7158 7159 struct mlx5_ifc_page_fault_resume_out_bits { 7160 u8 status[0x8]; 7161 u8 reserved_at_8[0x18]; 7162 7163 u8 syndrome[0x20]; 7164 7165 u8 reserved_at_40[0x40]; 7166 }; 7167 7168 struct mlx5_ifc_page_fault_resume_in_bits { 7169 u8 opcode[0x10]; 7170 u8 reserved_at_10[0x10]; 7171 7172 u8 reserved_at_20[0x10]; 7173 u8 op_mod[0x10]; 7174 7175 u8 error[0x1]; 7176 u8 reserved_at_41[0x4]; 7177 u8 page_fault_type[0x3]; 7178 u8 wq_number[0x18]; 7179 7180 u8 reserved_at_60[0x8]; 7181 u8 token[0x18]; 7182 }; 7183 7184 struct mlx5_ifc_nop_out_bits { 7185 u8 status[0x8]; 7186 u8 reserved_at_8[0x18]; 7187 7188 u8 syndrome[0x20]; 7189 7190 u8 reserved_at_40[0x40]; 7191 }; 7192 7193 struct mlx5_ifc_nop_in_bits { 7194 u8 opcode[0x10]; 7195 u8 reserved_at_10[0x10]; 7196 7197 u8 reserved_at_20[0x10]; 7198 u8 op_mod[0x10]; 7199 7200 u8 reserved_at_40[0x40]; 7201 }; 7202 7203 struct mlx5_ifc_modify_vport_state_out_bits { 7204 u8 status[0x8]; 7205 u8 reserved_at_8[0x18]; 7206 7207 u8 syndrome[0x20]; 7208 7209 u8 reserved_at_40[0x40]; 7210 }; 7211 7212 struct mlx5_ifc_modify_vport_state_in_bits { 7213 u8 opcode[0x10]; 7214 u8 reserved_at_10[0x10]; 7215 7216 u8 reserved_at_20[0x10]; 7217 u8 op_mod[0x10]; 7218 7219 u8 other_vport[0x1]; 7220 u8 reserved_at_41[0xf]; 7221 u8 vport_number[0x10]; 7222 7223 u8 reserved_at_60[0x18]; 7224 u8 admin_state[0x4]; 7225 u8 reserved_at_7c[0x4]; 7226 }; 7227 7228 struct mlx5_ifc_modify_tis_out_bits { 7229 u8 status[0x8]; 7230 u8 reserved_at_8[0x18]; 7231 7232 u8 syndrome[0x20]; 7233 7234 u8 reserved_at_40[0x40]; 7235 }; 7236 7237 struct mlx5_ifc_modify_tis_bitmask_bits { 7238 u8 reserved_at_0[0x20]; 7239 7240 u8 reserved_at_20[0x1d]; 7241 u8 lag_tx_port_affinity[0x1]; 7242 u8 strict_lag_tx_port_affinity[0x1]; 7243 u8 prio[0x1]; 7244 }; 7245 7246 struct mlx5_ifc_modify_tis_in_bits { 7247 u8 opcode[0x10]; 7248 u8 uid[0x10]; 7249 7250 u8 reserved_at_20[0x10]; 7251 u8 op_mod[0x10]; 7252 7253 u8 reserved_at_40[0x8]; 7254 u8 tisn[0x18]; 7255 7256 u8 reserved_at_60[0x20]; 7257 7258 struct mlx5_ifc_modify_tis_bitmask_bits bitmask; 7259 7260 u8 reserved_at_c0[0x40]; 7261 7262 struct mlx5_ifc_tisc_bits ctx; 7263 }; 7264 7265 struct mlx5_ifc_modify_tir_bitmask_bits { 7266 u8 reserved_at_0[0x20]; 7267 7268 u8 reserved_at_20[0x1b]; 7269 u8 self_lb_en[0x1]; 7270 u8 reserved_at_3c[0x1]; 7271 u8 hash[0x1]; 7272 u8 reserved_at_3e[0x1]; 7273 u8 packet_merge[0x1]; 7274 }; 7275 7276 struct mlx5_ifc_modify_tir_out_bits { 7277 u8 status[0x8]; 7278 u8 reserved_at_8[0x18]; 7279 7280 u8 syndrome[0x20]; 7281 7282 u8 reserved_at_40[0x40]; 7283 }; 7284 7285 struct mlx5_ifc_modify_tir_in_bits { 7286 u8 opcode[0x10]; 7287 u8 uid[0x10]; 7288 7289 u8 reserved_at_20[0x10]; 7290 u8 op_mod[0x10]; 7291 7292 u8 reserved_at_40[0x8]; 7293 u8 tirn[0x18]; 7294 7295 u8 reserved_at_60[0x20]; 7296 7297 struct mlx5_ifc_modify_tir_bitmask_bits bitmask; 7298 7299 u8 reserved_at_c0[0x40]; 7300 7301 struct mlx5_ifc_tirc_bits ctx; 7302 }; 7303 7304 struct mlx5_ifc_modify_sq_out_bits { 7305 u8 status[0x8]; 7306 u8 reserved_at_8[0x18]; 7307 7308 u8 syndrome[0x20]; 7309 7310 u8 reserved_at_40[0x40]; 7311 }; 7312 7313 struct mlx5_ifc_modify_sq_in_bits { 7314 u8 opcode[0x10]; 7315 u8 uid[0x10]; 7316 7317 u8 reserved_at_20[0x10]; 7318 u8 op_mod[0x10]; 7319 7320 u8 sq_state[0x4]; 7321 u8 reserved_at_44[0x4]; 7322 u8 sqn[0x18]; 7323 7324 u8 reserved_at_60[0x20]; 7325 7326 u8 modify_bitmask[0x40]; 7327 7328 u8 reserved_at_c0[0x40]; 7329 7330 struct mlx5_ifc_sqc_bits ctx; 7331 }; 7332 7333 struct mlx5_ifc_modify_scheduling_element_out_bits { 7334 u8 status[0x8]; 7335 u8 reserved_at_8[0x18]; 7336 7337 u8 syndrome[0x20]; 7338 7339 u8 reserved_at_40[0x1c0]; 7340 }; 7341 7342 enum { 7343 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1, 7344 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2, 7345 }; 7346 7347 struct mlx5_ifc_modify_scheduling_element_in_bits { 7348 u8 opcode[0x10]; 7349 u8 reserved_at_10[0x10]; 7350 7351 u8 reserved_at_20[0x10]; 7352 u8 op_mod[0x10]; 7353 7354 u8 scheduling_hierarchy[0x8]; 7355 u8 reserved_at_48[0x18]; 7356 7357 u8 scheduling_element_id[0x20]; 7358 7359 u8 reserved_at_80[0x20]; 7360 7361 u8 modify_bitmask[0x20]; 7362 7363 u8 reserved_at_c0[0x40]; 7364 7365 struct mlx5_ifc_scheduling_context_bits scheduling_context; 7366 7367 u8 reserved_at_300[0x100]; 7368 }; 7369 7370 struct mlx5_ifc_modify_rqt_out_bits { 7371 u8 status[0x8]; 7372 u8 reserved_at_8[0x18]; 7373 7374 u8 syndrome[0x20]; 7375 7376 u8 reserved_at_40[0x40]; 7377 }; 7378 7379 struct mlx5_ifc_rqt_bitmask_bits { 7380 u8 reserved_at_0[0x20]; 7381 7382 u8 reserved_at_20[0x1f]; 7383 u8 rqn_list[0x1]; 7384 }; 7385 7386 struct mlx5_ifc_modify_rqt_in_bits { 7387 u8 opcode[0x10]; 7388 u8 uid[0x10]; 7389 7390 u8 reserved_at_20[0x10]; 7391 u8 op_mod[0x10]; 7392 7393 u8 reserved_at_40[0x8]; 7394 u8 rqtn[0x18]; 7395 7396 u8 reserved_at_60[0x20]; 7397 7398 struct mlx5_ifc_rqt_bitmask_bits bitmask; 7399 7400 u8 reserved_at_c0[0x40]; 7401 7402 struct mlx5_ifc_rqtc_bits ctx; 7403 }; 7404 7405 struct mlx5_ifc_modify_rq_out_bits { 7406 u8 status[0x8]; 7407 u8 reserved_at_8[0x18]; 7408 7409 u8 syndrome[0x20]; 7410 7411 u8 reserved_at_40[0x40]; 7412 }; 7413 7414 enum { 7415 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1, 7416 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2, 7417 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3, 7418 }; 7419 7420 struct mlx5_ifc_modify_rq_in_bits { 7421 u8 opcode[0x10]; 7422 u8 uid[0x10]; 7423 7424 u8 reserved_at_20[0x10]; 7425 u8 op_mod[0x10]; 7426 7427 u8 rq_state[0x4]; 7428 u8 reserved_at_44[0x4]; 7429 u8 rqn[0x18]; 7430 7431 u8 reserved_at_60[0x20]; 7432 7433 u8 modify_bitmask[0x40]; 7434 7435 u8 reserved_at_c0[0x40]; 7436 7437 struct mlx5_ifc_rqc_bits ctx; 7438 }; 7439 7440 struct mlx5_ifc_modify_rmp_out_bits { 7441 u8 status[0x8]; 7442 u8 reserved_at_8[0x18]; 7443 7444 u8 syndrome[0x20]; 7445 7446 u8 reserved_at_40[0x40]; 7447 }; 7448 7449 struct mlx5_ifc_rmp_bitmask_bits { 7450 u8 reserved_at_0[0x20]; 7451 7452 u8 reserved_at_20[0x1f]; 7453 u8 lwm[0x1]; 7454 }; 7455 7456 struct mlx5_ifc_modify_rmp_in_bits { 7457 u8 opcode[0x10]; 7458 u8 uid[0x10]; 7459 7460 u8 reserved_at_20[0x10]; 7461 u8 op_mod[0x10]; 7462 7463 u8 rmp_state[0x4]; 7464 u8 reserved_at_44[0x4]; 7465 u8 rmpn[0x18]; 7466 7467 u8 reserved_at_60[0x20]; 7468 7469 struct mlx5_ifc_rmp_bitmask_bits bitmask; 7470 7471 u8 reserved_at_c0[0x40]; 7472 7473 struct mlx5_ifc_rmpc_bits ctx; 7474 }; 7475 7476 struct mlx5_ifc_modify_nic_vport_context_out_bits { 7477 u8 status[0x8]; 7478 u8 reserved_at_8[0x18]; 7479 7480 u8 syndrome[0x20]; 7481 7482 u8 reserved_at_40[0x40]; 7483 }; 7484 7485 struct mlx5_ifc_modify_nic_vport_field_select_bits { 7486 u8 reserved_at_0[0x12]; 7487 u8 affiliation[0x1]; 7488 u8 reserved_at_13[0x1]; 7489 u8 disable_uc_local_lb[0x1]; 7490 u8 disable_mc_local_lb[0x1]; 7491 u8 node_guid[0x1]; 7492 u8 port_guid[0x1]; 7493 u8 min_inline[0x1]; 7494 u8 mtu[0x1]; 7495 u8 change_event[0x1]; 7496 u8 promisc[0x1]; 7497 u8 permanent_address[0x1]; 7498 u8 addresses_list[0x1]; 7499 u8 roce_en[0x1]; 7500 u8 reserved_at_1f[0x1]; 7501 }; 7502 7503 struct mlx5_ifc_modify_nic_vport_context_in_bits { 7504 u8 opcode[0x10]; 7505 u8 reserved_at_10[0x10]; 7506 7507 u8 reserved_at_20[0x10]; 7508 u8 op_mod[0x10]; 7509 7510 u8 other_vport[0x1]; 7511 u8 reserved_at_41[0xf]; 7512 u8 vport_number[0x10]; 7513 7514 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select; 7515 7516 u8 reserved_at_80[0x780]; 7517 7518 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 7519 }; 7520 7521 struct mlx5_ifc_modify_hca_vport_context_out_bits { 7522 u8 status[0x8]; 7523 u8 reserved_at_8[0x18]; 7524 7525 u8 syndrome[0x20]; 7526 7527 u8 reserved_at_40[0x40]; 7528 }; 7529 7530 struct mlx5_ifc_modify_hca_vport_context_in_bits { 7531 u8 opcode[0x10]; 7532 u8 reserved_at_10[0x10]; 7533 7534 u8 reserved_at_20[0x10]; 7535 u8 op_mod[0x10]; 7536 7537 u8 other_vport[0x1]; 7538 u8 reserved_at_41[0xb]; 7539 u8 port_num[0x4]; 7540 u8 vport_number[0x10]; 7541 7542 u8 reserved_at_60[0x20]; 7543 7544 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 7545 }; 7546 7547 struct mlx5_ifc_modify_cq_out_bits { 7548 u8 status[0x8]; 7549 u8 reserved_at_8[0x18]; 7550 7551 u8 syndrome[0x20]; 7552 7553 u8 reserved_at_40[0x40]; 7554 }; 7555 7556 enum { 7557 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0, 7558 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1, 7559 }; 7560 7561 struct mlx5_ifc_modify_cq_in_bits { 7562 u8 opcode[0x10]; 7563 u8 uid[0x10]; 7564 7565 u8 reserved_at_20[0x10]; 7566 u8 op_mod[0x10]; 7567 7568 u8 reserved_at_40[0x8]; 7569 u8 cqn[0x18]; 7570 7571 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select; 7572 7573 struct mlx5_ifc_cqc_bits cq_context; 7574 7575 u8 reserved_at_280[0x60]; 7576 7577 u8 cq_umem_valid[0x1]; 7578 u8 reserved_at_2e1[0x1f]; 7579 7580 u8 reserved_at_300[0x580]; 7581 7582 u8 pas[][0x40]; 7583 }; 7584 7585 struct mlx5_ifc_modify_cong_status_out_bits { 7586 u8 status[0x8]; 7587 u8 reserved_at_8[0x18]; 7588 7589 u8 syndrome[0x20]; 7590 7591 u8 reserved_at_40[0x40]; 7592 }; 7593 7594 struct mlx5_ifc_modify_cong_status_in_bits { 7595 u8 opcode[0x10]; 7596 u8 reserved_at_10[0x10]; 7597 7598 u8 reserved_at_20[0x10]; 7599 u8 op_mod[0x10]; 7600 7601 u8 reserved_at_40[0x18]; 7602 u8 priority[0x4]; 7603 u8 cong_protocol[0x4]; 7604 7605 u8 enable[0x1]; 7606 u8 tag_enable[0x1]; 7607 u8 reserved_at_62[0x1e]; 7608 }; 7609 7610 struct mlx5_ifc_modify_cong_params_out_bits { 7611 u8 status[0x8]; 7612 u8 reserved_at_8[0x18]; 7613 7614 u8 syndrome[0x20]; 7615 7616 u8 reserved_at_40[0x40]; 7617 }; 7618 7619 struct mlx5_ifc_modify_cong_params_in_bits { 7620 u8 opcode[0x10]; 7621 u8 reserved_at_10[0x10]; 7622 7623 u8 reserved_at_20[0x10]; 7624 u8 op_mod[0x10]; 7625 7626 u8 reserved_at_40[0x1c]; 7627 u8 cong_protocol[0x4]; 7628 7629 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select; 7630 7631 u8 reserved_at_80[0x80]; 7632 7633 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 7634 }; 7635 7636 struct mlx5_ifc_manage_pages_out_bits { 7637 u8 status[0x8]; 7638 u8 reserved_at_8[0x18]; 7639 7640 u8 syndrome[0x20]; 7641 7642 u8 output_num_entries[0x20]; 7643 7644 u8 reserved_at_60[0x20]; 7645 7646 u8 pas[][0x40]; 7647 }; 7648 7649 enum { 7650 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL = 0x0, 7651 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS = 0x1, 7652 MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES = 0x2, 7653 }; 7654 7655 struct mlx5_ifc_manage_pages_in_bits { 7656 u8 opcode[0x10]; 7657 u8 reserved_at_10[0x10]; 7658 7659 u8 reserved_at_20[0x10]; 7660 u8 op_mod[0x10]; 7661 7662 u8 embedded_cpu_function[0x1]; 7663 u8 reserved_at_41[0xf]; 7664 u8 function_id[0x10]; 7665 7666 u8 input_num_entries[0x20]; 7667 7668 u8 pas[][0x40]; 7669 }; 7670 7671 struct mlx5_ifc_mad_ifc_out_bits { 7672 u8 status[0x8]; 7673 u8 reserved_at_8[0x18]; 7674 7675 u8 syndrome[0x20]; 7676 7677 u8 reserved_at_40[0x40]; 7678 7679 u8 response_mad_packet[256][0x8]; 7680 }; 7681 7682 struct mlx5_ifc_mad_ifc_in_bits { 7683 u8 opcode[0x10]; 7684 u8 reserved_at_10[0x10]; 7685 7686 u8 reserved_at_20[0x10]; 7687 u8 op_mod[0x10]; 7688 7689 u8 remote_lid[0x10]; 7690 u8 reserved_at_50[0x8]; 7691 u8 port[0x8]; 7692 7693 u8 reserved_at_60[0x20]; 7694 7695 u8 mad[256][0x8]; 7696 }; 7697 7698 struct mlx5_ifc_init_hca_out_bits { 7699 u8 status[0x8]; 7700 u8 reserved_at_8[0x18]; 7701 7702 u8 syndrome[0x20]; 7703 7704 u8 reserved_at_40[0x40]; 7705 }; 7706 7707 struct mlx5_ifc_init_hca_in_bits { 7708 u8 opcode[0x10]; 7709 u8 reserved_at_10[0x10]; 7710 7711 u8 reserved_at_20[0x10]; 7712 u8 op_mod[0x10]; 7713 7714 u8 reserved_at_40[0x20]; 7715 7716 u8 reserved_at_60[0x2]; 7717 u8 sw_vhca_id[0xe]; 7718 u8 reserved_at_70[0x10]; 7719 7720 u8 sw_owner_id[4][0x20]; 7721 }; 7722 7723 struct mlx5_ifc_init2rtr_qp_out_bits { 7724 u8 status[0x8]; 7725 u8 reserved_at_8[0x18]; 7726 7727 u8 syndrome[0x20]; 7728 7729 u8 reserved_at_40[0x20]; 7730 u8 ece[0x20]; 7731 }; 7732 7733 struct mlx5_ifc_init2rtr_qp_in_bits { 7734 u8 opcode[0x10]; 7735 u8 uid[0x10]; 7736 7737 u8 reserved_at_20[0x10]; 7738 u8 op_mod[0x10]; 7739 7740 u8 reserved_at_40[0x8]; 7741 u8 qpn[0x18]; 7742 7743 u8 reserved_at_60[0x20]; 7744 7745 u8 opt_param_mask[0x20]; 7746 7747 u8 ece[0x20]; 7748 7749 struct mlx5_ifc_qpc_bits qpc; 7750 7751 u8 reserved_at_800[0x80]; 7752 }; 7753 7754 struct mlx5_ifc_init2init_qp_out_bits { 7755 u8 status[0x8]; 7756 u8 reserved_at_8[0x18]; 7757 7758 u8 syndrome[0x20]; 7759 7760 u8 reserved_at_40[0x20]; 7761 u8 ece[0x20]; 7762 }; 7763 7764 struct mlx5_ifc_init2init_qp_in_bits { 7765 u8 opcode[0x10]; 7766 u8 uid[0x10]; 7767 7768 u8 reserved_at_20[0x10]; 7769 u8 op_mod[0x10]; 7770 7771 u8 reserved_at_40[0x8]; 7772 u8 qpn[0x18]; 7773 7774 u8 reserved_at_60[0x20]; 7775 7776 u8 opt_param_mask[0x20]; 7777 7778 u8 ece[0x20]; 7779 7780 struct mlx5_ifc_qpc_bits qpc; 7781 7782 u8 reserved_at_800[0x80]; 7783 }; 7784 7785 struct mlx5_ifc_get_dropped_packet_log_out_bits { 7786 u8 status[0x8]; 7787 u8 reserved_at_8[0x18]; 7788 7789 u8 syndrome[0x20]; 7790 7791 u8 reserved_at_40[0x40]; 7792 7793 u8 packet_headers_log[128][0x8]; 7794 7795 u8 packet_syndrome[64][0x8]; 7796 }; 7797 7798 struct mlx5_ifc_get_dropped_packet_log_in_bits { 7799 u8 opcode[0x10]; 7800 u8 reserved_at_10[0x10]; 7801 7802 u8 reserved_at_20[0x10]; 7803 u8 op_mod[0x10]; 7804 7805 u8 reserved_at_40[0x40]; 7806 }; 7807 7808 struct mlx5_ifc_gen_eqe_in_bits { 7809 u8 opcode[0x10]; 7810 u8 reserved_at_10[0x10]; 7811 7812 u8 reserved_at_20[0x10]; 7813 u8 op_mod[0x10]; 7814 7815 u8 reserved_at_40[0x18]; 7816 u8 eq_number[0x8]; 7817 7818 u8 reserved_at_60[0x20]; 7819 7820 u8 eqe[64][0x8]; 7821 }; 7822 7823 struct mlx5_ifc_gen_eq_out_bits { 7824 u8 status[0x8]; 7825 u8 reserved_at_8[0x18]; 7826 7827 u8 syndrome[0x20]; 7828 7829 u8 reserved_at_40[0x40]; 7830 }; 7831 7832 struct mlx5_ifc_enable_hca_out_bits { 7833 u8 status[0x8]; 7834 u8 reserved_at_8[0x18]; 7835 7836 u8 syndrome[0x20]; 7837 7838 u8 reserved_at_40[0x20]; 7839 }; 7840 7841 struct mlx5_ifc_enable_hca_in_bits { 7842 u8 opcode[0x10]; 7843 u8 reserved_at_10[0x10]; 7844 7845 u8 reserved_at_20[0x10]; 7846 u8 op_mod[0x10]; 7847 7848 u8 embedded_cpu_function[0x1]; 7849 u8 reserved_at_41[0xf]; 7850 u8 function_id[0x10]; 7851 7852 u8 reserved_at_60[0x20]; 7853 }; 7854 7855 struct mlx5_ifc_drain_dct_out_bits { 7856 u8 status[0x8]; 7857 u8 reserved_at_8[0x18]; 7858 7859 u8 syndrome[0x20]; 7860 7861 u8 reserved_at_40[0x40]; 7862 }; 7863 7864 struct mlx5_ifc_drain_dct_in_bits { 7865 u8 opcode[0x10]; 7866 u8 uid[0x10]; 7867 7868 u8 reserved_at_20[0x10]; 7869 u8 op_mod[0x10]; 7870 7871 u8 reserved_at_40[0x8]; 7872 u8 dctn[0x18]; 7873 7874 u8 reserved_at_60[0x20]; 7875 }; 7876 7877 struct mlx5_ifc_disable_hca_out_bits { 7878 u8 status[0x8]; 7879 u8 reserved_at_8[0x18]; 7880 7881 u8 syndrome[0x20]; 7882 7883 u8 reserved_at_40[0x20]; 7884 }; 7885 7886 struct mlx5_ifc_disable_hca_in_bits { 7887 u8 opcode[0x10]; 7888 u8 reserved_at_10[0x10]; 7889 7890 u8 reserved_at_20[0x10]; 7891 u8 op_mod[0x10]; 7892 7893 u8 embedded_cpu_function[0x1]; 7894 u8 reserved_at_41[0xf]; 7895 u8 function_id[0x10]; 7896 7897 u8 reserved_at_60[0x20]; 7898 }; 7899 7900 struct mlx5_ifc_detach_from_mcg_out_bits { 7901 u8 status[0x8]; 7902 u8 reserved_at_8[0x18]; 7903 7904 u8 syndrome[0x20]; 7905 7906 u8 reserved_at_40[0x40]; 7907 }; 7908 7909 struct mlx5_ifc_detach_from_mcg_in_bits { 7910 u8 opcode[0x10]; 7911 u8 uid[0x10]; 7912 7913 u8 reserved_at_20[0x10]; 7914 u8 op_mod[0x10]; 7915 7916 u8 reserved_at_40[0x8]; 7917 u8 qpn[0x18]; 7918 7919 u8 reserved_at_60[0x20]; 7920 7921 u8 multicast_gid[16][0x8]; 7922 }; 7923 7924 struct mlx5_ifc_destroy_xrq_out_bits { 7925 u8 status[0x8]; 7926 u8 reserved_at_8[0x18]; 7927 7928 u8 syndrome[0x20]; 7929 7930 u8 reserved_at_40[0x40]; 7931 }; 7932 7933 struct mlx5_ifc_destroy_xrq_in_bits { 7934 u8 opcode[0x10]; 7935 u8 uid[0x10]; 7936 7937 u8 reserved_at_20[0x10]; 7938 u8 op_mod[0x10]; 7939 7940 u8 reserved_at_40[0x8]; 7941 u8 xrqn[0x18]; 7942 7943 u8 reserved_at_60[0x20]; 7944 }; 7945 7946 struct mlx5_ifc_destroy_xrc_srq_out_bits { 7947 u8 status[0x8]; 7948 u8 reserved_at_8[0x18]; 7949 7950 u8 syndrome[0x20]; 7951 7952 u8 reserved_at_40[0x40]; 7953 }; 7954 7955 struct mlx5_ifc_destroy_xrc_srq_in_bits { 7956 u8 opcode[0x10]; 7957 u8 uid[0x10]; 7958 7959 u8 reserved_at_20[0x10]; 7960 u8 op_mod[0x10]; 7961 7962 u8 reserved_at_40[0x8]; 7963 u8 xrc_srqn[0x18]; 7964 7965 u8 reserved_at_60[0x20]; 7966 }; 7967 7968 struct mlx5_ifc_destroy_tis_out_bits { 7969 u8 status[0x8]; 7970 u8 reserved_at_8[0x18]; 7971 7972 u8 syndrome[0x20]; 7973 7974 u8 reserved_at_40[0x40]; 7975 }; 7976 7977 struct mlx5_ifc_destroy_tis_in_bits { 7978 u8 opcode[0x10]; 7979 u8 uid[0x10]; 7980 7981 u8 reserved_at_20[0x10]; 7982 u8 op_mod[0x10]; 7983 7984 u8 reserved_at_40[0x8]; 7985 u8 tisn[0x18]; 7986 7987 u8 reserved_at_60[0x20]; 7988 }; 7989 7990 struct mlx5_ifc_destroy_tir_out_bits { 7991 u8 status[0x8]; 7992 u8 reserved_at_8[0x18]; 7993 7994 u8 syndrome[0x20]; 7995 7996 u8 reserved_at_40[0x40]; 7997 }; 7998 7999 struct mlx5_ifc_destroy_tir_in_bits { 8000 u8 opcode[0x10]; 8001 u8 uid[0x10]; 8002 8003 u8 reserved_at_20[0x10]; 8004 u8 op_mod[0x10]; 8005 8006 u8 reserved_at_40[0x8]; 8007 u8 tirn[0x18]; 8008 8009 u8 reserved_at_60[0x20]; 8010 }; 8011 8012 struct mlx5_ifc_destroy_srq_out_bits { 8013 u8 status[0x8]; 8014 u8 reserved_at_8[0x18]; 8015 8016 u8 syndrome[0x20]; 8017 8018 u8 reserved_at_40[0x40]; 8019 }; 8020 8021 struct mlx5_ifc_destroy_srq_in_bits { 8022 u8 opcode[0x10]; 8023 u8 uid[0x10]; 8024 8025 u8 reserved_at_20[0x10]; 8026 u8 op_mod[0x10]; 8027 8028 u8 reserved_at_40[0x8]; 8029 u8 srqn[0x18]; 8030 8031 u8 reserved_at_60[0x20]; 8032 }; 8033 8034 struct mlx5_ifc_destroy_sq_out_bits { 8035 u8 status[0x8]; 8036 u8 reserved_at_8[0x18]; 8037 8038 u8 syndrome[0x20]; 8039 8040 u8 reserved_at_40[0x40]; 8041 }; 8042 8043 struct mlx5_ifc_destroy_sq_in_bits { 8044 u8 opcode[0x10]; 8045 u8 uid[0x10]; 8046 8047 u8 reserved_at_20[0x10]; 8048 u8 op_mod[0x10]; 8049 8050 u8 reserved_at_40[0x8]; 8051 u8 sqn[0x18]; 8052 8053 u8 reserved_at_60[0x20]; 8054 }; 8055 8056 struct mlx5_ifc_destroy_scheduling_element_out_bits { 8057 u8 status[0x8]; 8058 u8 reserved_at_8[0x18]; 8059 8060 u8 syndrome[0x20]; 8061 8062 u8 reserved_at_40[0x1c0]; 8063 }; 8064 8065 struct mlx5_ifc_destroy_scheduling_element_in_bits { 8066 u8 opcode[0x10]; 8067 u8 reserved_at_10[0x10]; 8068 8069 u8 reserved_at_20[0x10]; 8070 u8 op_mod[0x10]; 8071 8072 u8 scheduling_hierarchy[0x8]; 8073 u8 reserved_at_48[0x18]; 8074 8075 u8 scheduling_element_id[0x20]; 8076 8077 u8 reserved_at_80[0x180]; 8078 }; 8079 8080 struct mlx5_ifc_destroy_rqt_out_bits { 8081 u8 status[0x8]; 8082 u8 reserved_at_8[0x18]; 8083 8084 u8 syndrome[0x20]; 8085 8086 u8 reserved_at_40[0x40]; 8087 }; 8088 8089 struct mlx5_ifc_destroy_rqt_in_bits { 8090 u8 opcode[0x10]; 8091 u8 uid[0x10]; 8092 8093 u8 reserved_at_20[0x10]; 8094 u8 op_mod[0x10]; 8095 8096 u8 reserved_at_40[0x8]; 8097 u8 rqtn[0x18]; 8098 8099 u8 reserved_at_60[0x20]; 8100 }; 8101 8102 struct mlx5_ifc_destroy_rq_out_bits { 8103 u8 status[0x8]; 8104 u8 reserved_at_8[0x18]; 8105 8106 u8 syndrome[0x20]; 8107 8108 u8 reserved_at_40[0x40]; 8109 }; 8110 8111 struct mlx5_ifc_destroy_rq_in_bits { 8112 u8 opcode[0x10]; 8113 u8 uid[0x10]; 8114 8115 u8 reserved_at_20[0x10]; 8116 u8 op_mod[0x10]; 8117 8118 u8 reserved_at_40[0x8]; 8119 u8 rqn[0x18]; 8120 8121 u8 reserved_at_60[0x20]; 8122 }; 8123 8124 struct mlx5_ifc_set_delay_drop_params_in_bits { 8125 u8 opcode[0x10]; 8126 u8 reserved_at_10[0x10]; 8127 8128 u8 reserved_at_20[0x10]; 8129 u8 op_mod[0x10]; 8130 8131 u8 reserved_at_40[0x20]; 8132 8133 u8 reserved_at_60[0x10]; 8134 u8 delay_drop_timeout[0x10]; 8135 }; 8136 8137 struct mlx5_ifc_set_delay_drop_params_out_bits { 8138 u8 status[0x8]; 8139 u8 reserved_at_8[0x18]; 8140 8141 u8 syndrome[0x20]; 8142 8143 u8 reserved_at_40[0x40]; 8144 }; 8145 8146 struct mlx5_ifc_destroy_rmp_out_bits { 8147 u8 status[0x8]; 8148 u8 reserved_at_8[0x18]; 8149 8150 u8 syndrome[0x20]; 8151 8152 u8 reserved_at_40[0x40]; 8153 }; 8154 8155 struct mlx5_ifc_destroy_rmp_in_bits { 8156 u8 opcode[0x10]; 8157 u8 uid[0x10]; 8158 8159 u8 reserved_at_20[0x10]; 8160 u8 op_mod[0x10]; 8161 8162 u8 reserved_at_40[0x8]; 8163 u8 rmpn[0x18]; 8164 8165 u8 reserved_at_60[0x20]; 8166 }; 8167 8168 struct mlx5_ifc_destroy_qp_out_bits { 8169 u8 status[0x8]; 8170 u8 reserved_at_8[0x18]; 8171 8172 u8 syndrome[0x20]; 8173 8174 u8 reserved_at_40[0x40]; 8175 }; 8176 8177 struct mlx5_ifc_destroy_qp_in_bits { 8178 u8 opcode[0x10]; 8179 u8 uid[0x10]; 8180 8181 u8 reserved_at_20[0x10]; 8182 u8 op_mod[0x10]; 8183 8184 u8 reserved_at_40[0x8]; 8185 u8 qpn[0x18]; 8186 8187 u8 reserved_at_60[0x20]; 8188 }; 8189 8190 struct mlx5_ifc_destroy_psv_out_bits { 8191 u8 status[0x8]; 8192 u8 reserved_at_8[0x18]; 8193 8194 u8 syndrome[0x20]; 8195 8196 u8 reserved_at_40[0x40]; 8197 }; 8198 8199 struct mlx5_ifc_destroy_psv_in_bits { 8200 u8 opcode[0x10]; 8201 u8 reserved_at_10[0x10]; 8202 8203 u8 reserved_at_20[0x10]; 8204 u8 op_mod[0x10]; 8205 8206 u8 reserved_at_40[0x8]; 8207 u8 psvn[0x18]; 8208 8209 u8 reserved_at_60[0x20]; 8210 }; 8211 8212 struct mlx5_ifc_destroy_mkey_out_bits { 8213 u8 status[0x8]; 8214 u8 reserved_at_8[0x18]; 8215 8216 u8 syndrome[0x20]; 8217 8218 u8 reserved_at_40[0x40]; 8219 }; 8220 8221 struct mlx5_ifc_destroy_mkey_in_bits { 8222 u8 opcode[0x10]; 8223 u8 uid[0x10]; 8224 8225 u8 reserved_at_20[0x10]; 8226 u8 op_mod[0x10]; 8227 8228 u8 reserved_at_40[0x8]; 8229 u8 mkey_index[0x18]; 8230 8231 u8 reserved_at_60[0x20]; 8232 }; 8233 8234 struct mlx5_ifc_destroy_flow_table_out_bits { 8235 u8 status[0x8]; 8236 u8 reserved_at_8[0x18]; 8237 8238 u8 syndrome[0x20]; 8239 8240 u8 reserved_at_40[0x40]; 8241 }; 8242 8243 struct mlx5_ifc_destroy_flow_table_in_bits { 8244 u8 opcode[0x10]; 8245 u8 reserved_at_10[0x10]; 8246 8247 u8 reserved_at_20[0x10]; 8248 u8 op_mod[0x10]; 8249 8250 u8 other_vport[0x1]; 8251 u8 reserved_at_41[0xf]; 8252 u8 vport_number[0x10]; 8253 8254 u8 reserved_at_60[0x20]; 8255 8256 u8 table_type[0x8]; 8257 u8 reserved_at_88[0x18]; 8258 8259 u8 reserved_at_a0[0x8]; 8260 u8 table_id[0x18]; 8261 8262 u8 reserved_at_c0[0x140]; 8263 }; 8264 8265 struct mlx5_ifc_destroy_flow_group_out_bits { 8266 u8 status[0x8]; 8267 u8 reserved_at_8[0x18]; 8268 8269 u8 syndrome[0x20]; 8270 8271 u8 reserved_at_40[0x40]; 8272 }; 8273 8274 struct mlx5_ifc_destroy_flow_group_in_bits { 8275 u8 opcode[0x10]; 8276 u8 reserved_at_10[0x10]; 8277 8278 u8 reserved_at_20[0x10]; 8279 u8 op_mod[0x10]; 8280 8281 u8 other_vport[0x1]; 8282 u8 reserved_at_41[0xf]; 8283 u8 vport_number[0x10]; 8284 8285 u8 reserved_at_60[0x20]; 8286 8287 u8 table_type[0x8]; 8288 u8 reserved_at_88[0x18]; 8289 8290 u8 reserved_at_a0[0x8]; 8291 u8 table_id[0x18]; 8292 8293 u8 group_id[0x20]; 8294 8295 u8 reserved_at_e0[0x120]; 8296 }; 8297 8298 struct mlx5_ifc_destroy_eq_out_bits { 8299 u8 status[0x8]; 8300 u8 reserved_at_8[0x18]; 8301 8302 u8 syndrome[0x20]; 8303 8304 u8 reserved_at_40[0x40]; 8305 }; 8306 8307 struct mlx5_ifc_destroy_eq_in_bits { 8308 u8 opcode[0x10]; 8309 u8 reserved_at_10[0x10]; 8310 8311 u8 reserved_at_20[0x10]; 8312 u8 op_mod[0x10]; 8313 8314 u8 reserved_at_40[0x18]; 8315 u8 eq_number[0x8]; 8316 8317 u8 reserved_at_60[0x20]; 8318 }; 8319 8320 struct mlx5_ifc_destroy_dct_out_bits { 8321 u8 status[0x8]; 8322 u8 reserved_at_8[0x18]; 8323 8324 u8 syndrome[0x20]; 8325 8326 u8 reserved_at_40[0x40]; 8327 }; 8328 8329 struct mlx5_ifc_destroy_dct_in_bits { 8330 u8 opcode[0x10]; 8331 u8 uid[0x10]; 8332 8333 u8 reserved_at_20[0x10]; 8334 u8 op_mod[0x10]; 8335 8336 u8 reserved_at_40[0x8]; 8337 u8 dctn[0x18]; 8338 8339 u8 reserved_at_60[0x20]; 8340 }; 8341 8342 struct mlx5_ifc_destroy_cq_out_bits { 8343 u8 status[0x8]; 8344 u8 reserved_at_8[0x18]; 8345 8346 u8 syndrome[0x20]; 8347 8348 u8 reserved_at_40[0x40]; 8349 }; 8350 8351 struct mlx5_ifc_destroy_cq_in_bits { 8352 u8 opcode[0x10]; 8353 u8 uid[0x10]; 8354 8355 u8 reserved_at_20[0x10]; 8356 u8 op_mod[0x10]; 8357 8358 u8 reserved_at_40[0x8]; 8359 u8 cqn[0x18]; 8360 8361 u8 reserved_at_60[0x20]; 8362 }; 8363 8364 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits { 8365 u8 status[0x8]; 8366 u8 reserved_at_8[0x18]; 8367 8368 u8 syndrome[0x20]; 8369 8370 u8 reserved_at_40[0x40]; 8371 }; 8372 8373 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits { 8374 u8 opcode[0x10]; 8375 u8 reserved_at_10[0x10]; 8376 8377 u8 reserved_at_20[0x10]; 8378 u8 op_mod[0x10]; 8379 8380 u8 reserved_at_40[0x20]; 8381 8382 u8 reserved_at_60[0x10]; 8383 u8 vxlan_udp_port[0x10]; 8384 }; 8385 8386 struct mlx5_ifc_delete_l2_table_entry_out_bits { 8387 u8 status[0x8]; 8388 u8 reserved_at_8[0x18]; 8389 8390 u8 syndrome[0x20]; 8391 8392 u8 reserved_at_40[0x40]; 8393 }; 8394 8395 struct mlx5_ifc_delete_l2_table_entry_in_bits { 8396 u8 opcode[0x10]; 8397 u8 reserved_at_10[0x10]; 8398 8399 u8 reserved_at_20[0x10]; 8400 u8 op_mod[0x10]; 8401 8402 u8 reserved_at_40[0x60]; 8403 8404 u8 reserved_at_a0[0x8]; 8405 u8 table_index[0x18]; 8406 8407 u8 reserved_at_c0[0x140]; 8408 }; 8409 8410 struct mlx5_ifc_delete_fte_out_bits { 8411 u8 status[0x8]; 8412 u8 reserved_at_8[0x18]; 8413 8414 u8 syndrome[0x20]; 8415 8416 u8 reserved_at_40[0x40]; 8417 }; 8418 8419 struct mlx5_ifc_delete_fte_in_bits { 8420 u8 opcode[0x10]; 8421 u8 reserved_at_10[0x10]; 8422 8423 u8 reserved_at_20[0x10]; 8424 u8 op_mod[0x10]; 8425 8426 u8 other_vport[0x1]; 8427 u8 reserved_at_41[0xf]; 8428 u8 vport_number[0x10]; 8429 8430 u8 reserved_at_60[0x20]; 8431 8432 u8 table_type[0x8]; 8433 u8 reserved_at_88[0x18]; 8434 8435 u8 reserved_at_a0[0x8]; 8436 u8 table_id[0x18]; 8437 8438 u8 reserved_at_c0[0x40]; 8439 8440 u8 flow_index[0x20]; 8441 8442 u8 reserved_at_120[0xe0]; 8443 }; 8444 8445 struct mlx5_ifc_dealloc_xrcd_out_bits { 8446 u8 status[0x8]; 8447 u8 reserved_at_8[0x18]; 8448 8449 u8 syndrome[0x20]; 8450 8451 u8 reserved_at_40[0x40]; 8452 }; 8453 8454 struct mlx5_ifc_dealloc_xrcd_in_bits { 8455 u8 opcode[0x10]; 8456 u8 uid[0x10]; 8457 8458 u8 reserved_at_20[0x10]; 8459 u8 op_mod[0x10]; 8460 8461 u8 reserved_at_40[0x8]; 8462 u8 xrcd[0x18]; 8463 8464 u8 reserved_at_60[0x20]; 8465 }; 8466 8467 struct mlx5_ifc_dealloc_uar_out_bits { 8468 u8 status[0x8]; 8469 u8 reserved_at_8[0x18]; 8470 8471 u8 syndrome[0x20]; 8472 8473 u8 reserved_at_40[0x40]; 8474 }; 8475 8476 struct mlx5_ifc_dealloc_uar_in_bits { 8477 u8 opcode[0x10]; 8478 u8 uid[0x10]; 8479 8480 u8 reserved_at_20[0x10]; 8481 u8 op_mod[0x10]; 8482 8483 u8 reserved_at_40[0x8]; 8484 u8 uar[0x18]; 8485 8486 u8 reserved_at_60[0x20]; 8487 }; 8488 8489 struct mlx5_ifc_dealloc_transport_domain_out_bits { 8490 u8 status[0x8]; 8491 u8 reserved_at_8[0x18]; 8492 8493 u8 syndrome[0x20]; 8494 8495 u8 reserved_at_40[0x40]; 8496 }; 8497 8498 struct mlx5_ifc_dealloc_transport_domain_in_bits { 8499 u8 opcode[0x10]; 8500 u8 uid[0x10]; 8501 8502 u8 reserved_at_20[0x10]; 8503 u8 op_mod[0x10]; 8504 8505 u8 reserved_at_40[0x8]; 8506 u8 transport_domain[0x18]; 8507 8508 u8 reserved_at_60[0x20]; 8509 }; 8510 8511 struct mlx5_ifc_dealloc_q_counter_out_bits { 8512 u8 status[0x8]; 8513 u8 reserved_at_8[0x18]; 8514 8515 u8 syndrome[0x20]; 8516 8517 u8 reserved_at_40[0x40]; 8518 }; 8519 8520 struct mlx5_ifc_dealloc_q_counter_in_bits { 8521 u8 opcode[0x10]; 8522 u8 reserved_at_10[0x10]; 8523 8524 u8 reserved_at_20[0x10]; 8525 u8 op_mod[0x10]; 8526 8527 u8 reserved_at_40[0x18]; 8528 u8 counter_set_id[0x8]; 8529 8530 u8 reserved_at_60[0x20]; 8531 }; 8532 8533 struct mlx5_ifc_dealloc_pd_out_bits { 8534 u8 status[0x8]; 8535 u8 reserved_at_8[0x18]; 8536 8537 u8 syndrome[0x20]; 8538 8539 u8 reserved_at_40[0x40]; 8540 }; 8541 8542 struct mlx5_ifc_dealloc_pd_in_bits { 8543 u8 opcode[0x10]; 8544 u8 uid[0x10]; 8545 8546 u8 reserved_at_20[0x10]; 8547 u8 op_mod[0x10]; 8548 8549 u8 reserved_at_40[0x8]; 8550 u8 pd[0x18]; 8551 8552 u8 reserved_at_60[0x20]; 8553 }; 8554 8555 struct mlx5_ifc_dealloc_flow_counter_out_bits { 8556 u8 status[0x8]; 8557 u8 reserved_at_8[0x18]; 8558 8559 u8 syndrome[0x20]; 8560 8561 u8 reserved_at_40[0x40]; 8562 }; 8563 8564 struct mlx5_ifc_dealloc_flow_counter_in_bits { 8565 u8 opcode[0x10]; 8566 u8 reserved_at_10[0x10]; 8567 8568 u8 reserved_at_20[0x10]; 8569 u8 op_mod[0x10]; 8570 8571 u8 flow_counter_id[0x20]; 8572 8573 u8 reserved_at_60[0x20]; 8574 }; 8575 8576 struct mlx5_ifc_create_xrq_out_bits { 8577 u8 status[0x8]; 8578 u8 reserved_at_8[0x18]; 8579 8580 u8 syndrome[0x20]; 8581 8582 u8 reserved_at_40[0x8]; 8583 u8 xrqn[0x18]; 8584 8585 u8 reserved_at_60[0x20]; 8586 }; 8587 8588 struct mlx5_ifc_create_xrq_in_bits { 8589 u8 opcode[0x10]; 8590 u8 uid[0x10]; 8591 8592 u8 reserved_at_20[0x10]; 8593 u8 op_mod[0x10]; 8594 8595 u8 reserved_at_40[0x40]; 8596 8597 struct mlx5_ifc_xrqc_bits xrq_context; 8598 }; 8599 8600 struct mlx5_ifc_create_xrc_srq_out_bits { 8601 u8 status[0x8]; 8602 u8 reserved_at_8[0x18]; 8603 8604 u8 syndrome[0x20]; 8605 8606 u8 reserved_at_40[0x8]; 8607 u8 xrc_srqn[0x18]; 8608 8609 u8 reserved_at_60[0x20]; 8610 }; 8611 8612 struct mlx5_ifc_create_xrc_srq_in_bits { 8613 u8 opcode[0x10]; 8614 u8 uid[0x10]; 8615 8616 u8 reserved_at_20[0x10]; 8617 u8 op_mod[0x10]; 8618 8619 u8 reserved_at_40[0x40]; 8620 8621 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 8622 8623 u8 reserved_at_280[0x60]; 8624 8625 u8 xrc_srq_umem_valid[0x1]; 8626 u8 reserved_at_2e1[0x1f]; 8627 8628 u8 reserved_at_300[0x580]; 8629 8630 u8 pas[][0x40]; 8631 }; 8632 8633 struct mlx5_ifc_create_tis_out_bits { 8634 u8 status[0x8]; 8635 u8 reserved_at_8[0x18]; 8636 8637 u8 syndrome[0x20]; 8638 8639 u8 reserved_at_40[0x8]; 8640 u8 tisn[0x18]; 8641 8642 u8 reserved_at_60[0x20]; 8643 }; 8644 8645 struct mlx5_ifc_create_tis_in_bits { 8646 u8 opcode[0x10]; 8647 u8 uid[0x10]; 8648 8649 u8 reserved_at_20[0x10]; 8650 u8 op_mod[0x10]; 8651 8652 u8 reserved_at_40[0xc0]; 8653 8654 struct mlx5_ifc_tisc_bits ctx; 8655 }; 8656 8657 struct mlx5_ifc_create_tir_out_bits { 8658 u8 status[0x8]; 8659 u8 icm_address_63_40[0x18]; 8660 8661 u8 syndrome[0x20]; 8662 8663 u8 icm_address_39_32[0x8]; 8664 u8 tirn[0x18]; 8665 8666 u8 icm_address_31_0[0x20]; 8667 }; 8668 8669 struct mlx5_ifc_create_tir_in_bits { 8670 u8 opcode[0x10]; 8671 u8 uid[0x10]; 8672 8673 u8 reserved_at_20[0x10]; 8674 u8 op_mod[0x10]; 8675 8676 u8 reserved_at_40[0xc0]; 8677 8678 struct mlx5_ifc_tirc_bits ctx; 8679 }; 8680 8681 struct mlx5_ifc_create_srq_out_bits { 8682 u8 status[0x8]; 8683 u8 reserved_at_8[0x18]; 8684 8685 u8 syndrome[0x20]; 8686 8687 u8 reserved_at_40[0x8]; 8688 u8 srqn[0x18]; 8689 8690 u8 reserved_at_60[0x20]; 8691 }; 8692 8693 struct mlx5_ifc_create_srq_in_bits { 8694 u8 opcode[0x10]; 8695 u8 uid[0x10]; 8696 8697 u8 reserved_at_20[0x10]; 8698 u8 op_mod[0x10]; 8699 8700 u8 reserved_at_40[0x40]; 8701 8702 struct mlx5_ifc_srqc_bits srq_context_entry; 8703 8704 u8 reserved_at_280[0x600]; 8705 8706 u8 pas[][0x40]; 8707 }; 8708 8709 struct mlx5_ifc_create_sq_out_bits { 8710 u8 status[0x8]; 8711 u8 reserved_at_8[0x18]; 8712 8713 u8 syndrome[0x20]; 8714 8715 u8 reserved_at_40[0x8]; 8716 u8 sqn[0x18]; 8717 8718 u8 reserved_at_60[0x20]; 8719 }; 8720 8721 struct mlx5_ifc_create_sq_in_bits { 8722 u8 opcode[0x10]; 8723 u8 uid[0x10]; 8724 8725 u8 reserved_at_20[0x10]; 8726 u8 op_mod[0x10]; 8727 8728 u8 reserved_at_40[0xc0]; 8729 8730 struct mlx5_ifc_sqc_bits ctx; 8731 }; 8732 8733 struct mlx5_ifc_create_scheduling_element_out_bits { 8734 u8 status[0x8]; 8735 u8 reserved_at_8[0x18]; 8736 8737 u8 syndrome[0x20]; 8738 8739 u8 reserved_at_40[0x40]; 8740 8741 u8 scheduling_element_id[0x20]; 8742 8743 u8 reserved_at_a0[0x160]; 8744 }; 8745 8746 struct mlx5_ifc_create_scheduling_element_in_bits { 8747 u8 opcode[0x10]; 8748 u8 reserved_at_10[0x10]; 8749 8750 u8 reserved_at_20[0x10]; 8751 u8 op_mod[0x10]; 8752 8753 u8 scheduling_hierarchy[0x8]; 8754 u8 reserved_at_48[0x18]; 8755 8756 u8 reserved_at_60[0xa0]; 8757 8758 struct mlx5_ifc_scheduling_context_bits scheduling_context; 8759 8760 u8 reserved_at_300[0x100]; 8761 }; 8762 8763 struct mlx5_ifc_create_rqt_out_bits { 8764 u8 status[0x8]; 8765 u8 reserved_at_8[0x18]; 8766 8767 u8 syndrome[0x20]; 8768 8769 u8 reserved_at_40[0x8]; 8770 u8 rqtn[0x18]; 8771 8772 u8 reserved_at_60[0x20]; 8773 }; 8774 8775 struct mlx5_ifc_create_rqt_in_bits { 8776 u8 opcode[0x10]; 8777 u8 uid[0x10]; 8778 8779 u8 reserved_at_20[0x10]; 8780 u8 op_mod[0x10]; 8781 8782 u8 reserved_at_40[0xc0]; 8783 8784 struct mlx5_ifc_rqtc_bits rqt_context; 8785 }; 8786 8787 struct mlx5_ifc_create_rq_out_bits { 8788 u8 status[0x8]; 8789 u8 reserved_at_8[0x18]; 8790 8791 u8 syndrome[0x20]; 8792 8793 u8 reserved_at_40[0x8]; 8794 u8 rqn[0x18]; 8795 8796 u8 reserved_at_60[0x20]; 8797 }; 8798 8799 struct mlx5_ifc_create_rq_in_bits { 8800 u8 opcode[0x10]; 8801 u8 uid[0x10]; 8802 8803 u8 reserved_at_20[0x10]; 8804 u8 op_mod[0x10]; 8805 8806 u8 reserved_at_40[0xc0]; 8807 8808 struct mlx5_ifc_rqc_bits ctx; 8809 }; 8810 8811 struct mlx5_ifc_create_rmp_out_bits { 8812 u8 status[0x8]; 8813 u8 reserved_at_8[0x18]; 8814 8815 u8 syndrome[0x20]; 8816 8817 u8 reserved_at_40[0x8]; 8818 u8 rmpn[0x18]; 8819 8820 u8 reserved_at_60[0x20]; 8821 }; 8822 8823 struct mlx5_ifc_create_rmp_in_bits { 8824 u8 opcode[0x10]; 8825 u8 uid[0x10]; 8826 8827 u8 reserved_at_20[0x10]; 8828 u8 op_mod[0x10]; 8829 8830 u8 reserved_at_40[0xc0]; 8831 8832 struct mlx5_ifc_rmpc_bits ctx; 8833 }; 8834 8835 struct mlx5_ifc_create_qp_out_bits { 8836 u8 status[0x8]; 8837 u8 reserved_at_8[0x18]; 8838 8839 u8 syndrome[0x20]; 8840 8841 u8 reserved_at_40[0x8]; 8842 u8 qpn[0x18]; 8843 8844 u8 ece[0x20]; 8845 }; 8846 8847 struct mlx5_ifc_create_qp_in_bits { 8848 u8 opcode[0x10]; 8849 u8 uid[0x10]; 8850 8851 u8 reserved_at_20[0x10]; 8852 u8 op_mod[0x10]; 8853 8854 u8 qpc_ext[0x1]; 8855 u8 reserved_at_41[0x7]; 8856 u8 input_qpn[0x18]; 8857 8858 u8 reserved_at_60[0x20]; 8859 u8 opt_param_mask[0x20]; 8860 8861 u8 ece[0x20]; 8862 8863 struct mlx5_ifc_qpc_bits qpc; 8864 8865 u8 reserved_at_800[0x60]; 8866 8867 u8 wq_umem_valid[0x1]; 8868 u8 reserved_at_861[0x1f]; 8869 8870 u8 pas[][0x40]; 8871 }; 8872 8873 struct mlx5_ifc_create_psv_out_bits { 8874 u8 status[0x8]; 8875 u8 reserved_at_8[0x18]; 8876 8877 u8 syndrome[0x20]; 8878 8879 u8 reserved_at_40[0x40]; 8880 8881 u8 reserved_at_80[0x8]; 8882 u8 psv0_index[0x18]; 8883 8884 u8 reserved_at_a0[0x8]; 8885 u8 psv1_index[0x18]; 8886 8887 u8 reserved_at_c0[0x8]; 8888 u8 psv2_index[0x18]; 8889 8890 u8 reserved_at_e0[0x8]; 8891 u8 psv3_index[0x18]; 8892 }; 8893 8894 struct mlx5_ifc_create_psv_in_bits { 8895 u8 opcode[0x10]; 8896 u8 reserved_at_10[0x10]; 8897 8898 u8 reserved_at_20[0x10]; 8899 u8 op_mod[0x10]; 8900 8901 u8 num_psv[0x4]; 8902 u8 reserved_at_44[0x4]; 8903 u8 pd[0x18]; 8904 8905 u8 reserved_at_60[0x20]; 8906 }; 8907 8908 struct mlx5_ifc_create_mkey_out_bits { 8909 u8 status[0x8]; 8910 u8 reserved_at_8[0x18]; 8911 8912 u8 syndrome[0x20]; 8913 8914 u8 reserved_at_40[0x8]; 8915 u8 mkey_index[0x18]; 8916 8917 u8 reserved_at_60[0x20]; 8918 }; 8919 8920 struct mlx5_ifc_create_mkey_in_bits { 8921 u8 opcode[0x10]; 8922 u8 uid[0x10]; 8923 8924 u8 reserved_at_20[0x10]; 8925 u8 op_mod[0x10]; 8926 8927 u8 reserved_at_40[0x20]; 8928 8929 u8 pg_access[0x1]; 8930 u8 mkey_umem_valid[0x1]; 8931 u8 reserved_at_62[0x1e]; 8932 8933 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 8934 8935 u8 reserved_at_280[0x80]; 8936 8937 u8 translations_octword_actual_size[0x20]; 8938 8939 u8 reserved_at_320[0x560]; 8940 8941 u8 klm_pas_mtt[][0x20]; 8942 }; 8943 8944 enum { 8945 MLX5_FLOW_TABLE_TYPE_NIC_RX = 0x0, 8946 MLX5_FLOW_TABLE_TYPE_NIC_TX = 0x1, 8947 MLX5_FLOW_TABLE_TYPE_ESW_EGRESS_ACL = 0x2, 8948 MLX5_FLOW_TABLE_TYPE_ESW_INGRESS_ACL = 0x3, 8949 MLX5_FLOW_TABLE_TYPE_FDB = 0X4, 8950 MLX5_FLOW_TABLE_TYPE_SNIFFER_RX = 0X5, 8951 MLX5_FLOW_TABLE_TYPE_SNIFFER_TX = 0X6, 8952 }; 8953 8954 struct mlx5_ifc_create_flow_table_out_bits { 8955 u8 status[0x8]; 8956 u8 icm_address_63_40[0x18]; 8957 8958 u8 syndrome[0x20]; 8959 8960 u8 icm_address_39_32[0x8]; 8961 u8 table_id[0x18]; 8962 8963 u8 icm_address_31_0[0x20]; 8964 }; 8965 8966 struct mlx5_ifc_create_flow_table_in_bits { 8967 u8 opcode[0x10]; 8968 u8 uid[0x10]; 8969 8970 u8 reserved_at_20[0x10]; 8971 u8 op_mod[0x10]; 8972 8973 u8 other_vport[0x1]; 8974 u8 reserved_at_41[0xf]; 8975 u8 vport_number[0x10]; 8976 8977 u8 reserved_at_60[0x20]; 8978 8979 u8 table_type[0x8]; 8980 u8 reserved_at_88[0x18]; 8981 8982 u8 reserved_at_a0[0x20]; 8983 8984 struct mlx5_ifc_flow_table_context_bits flow_table_context; 8985 }; 8986 8987 struct mlx5_ifc_create_flow_group_out_bits { 8988 u8 status[0x8]; 8989 u8 reserved_at_8[0x18]; 8990 8991 u8 syndrome[0x20]; 8992 8993 u8 reserved_at_40[0x8]; 8994 u8 group_id[0x18]; 8995 8996 u8 reserved_at_60[0x20]; 8997 }; 8998 8999 enum { 9000 MLX5_CREATE_FLOW_GROUP_IN_GROUP_TYPE_TCAM_SUBTABLE = 0x0, 9001 MLX5_CREATE_FLOW_GROUP_IN_GROUP_TYPE_HASH_SPLIT = 0x1, 9002 }; 9003 9004 enum { 9005 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 9006 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 9007 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 9008 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3, 9009 }; 9010 9011 struct mlx5_ifc_create_flow_group_in_bits { 9012 u8 opcode[0x10]; 9013 u8 reserved_at_10[0x10]; 9014 9015 u8 reserved_at_20[0x10]; 9016 u8 op_mod[0x10]; 9017 9018 u8 other_vport[0x1]; 9019 u8 reserved_at_41[0xf]; 9020 u8 vport_number[0x10]; 9021 9022 u8 reserved_at_60[0x20]; 9023 9024 u8 table_type[0x8]; 9025 u8 reserved_at_88[0x4]; 9026 u8 group_type[0x4]; 9027 u8 reserved_at_90[0x10]; 9028 9029 u8 reserved_at_a0[0x8]; 9030 u8 table_id[0x18]; 9031 9032 u8 source_eswitch_owner_vhca_id_valid[0x1]; 9033 9034 u8 reserved_at_c1[0x1f]; 9035 9036 u8 start_flow_index[0x20]; 9037 9038 u8 reserved_at_100[0x20]; 9039 9040 u8 end_flow_index[0x20]; 9041 9042 u8 reserved_at_140[0x10]; 9043 u8 match_definer_id[0x10]; 9044 9045 u8 reserved_at_160[0x80]; 9046 9047 u8 reserved_at_1e0[0x18]; 9048 u8 match_criteria_enable[0x8]; 9049 9050 struct mlx5_ifc_fte_match_param_bits match_criteria; 9051 9052 u8 reserved_at_1200[0xe00]; 9053 }; 9054 9055 struct mlx5_ifc_create_eq_out_bits { 9056 u8 status[0x8]; 9057 u8 reserved_at_8[0x18]; 9058 9059 u8 syndrome[0x20]; 9060 9061 u8 reserved_at_40[0x18]; 9062 u8 eq_number[0x8]; 9063 9064 u8 reserved_at_60[0x20]; 9065 }; 9066 9067 struct mlx5_ifc_create_eq_in_bits { 9068 u8 opcode[0x10]; 9069 u8 uid[0x10]; 9070 9071 u8 reserved_at_20[0x10]; 9072 u8 op_mod[0x10]; 9073 9074 u8 reserved_at_40[0x40]; 9075 9076 struct mlx5_ifc_eqc_bits eq_context_entry; 9077 9078 u8 reserved_at_280[0x40]; 9079 9080 u8 event_bitmask[4][0x40]; 9081 9082 u8 reserved_at_3c0[0x4c0]; 9083 9084 u8 pas[][0x40]; 9085 }; 9086 9087 struct mlx5_ifc_create_dct_out_bits { 9088 u8 status[0x8]; 9089 u8 reserved_at_8[0x18]; 9090 9091 u8 syndrome[0x20]; 9092 9093 u8 reserved_at_40[0x8]; 9094 u8 dctn[0x18]; 9095 9096 u8 ece[0x20]; 9097 }; 9098 9099 struct mlx5_ifc_create_dct_in_bits { 9100 u8 opcode[0x10]; 9101 u8 uid[0x10]; 9102 9103 u8 reserved_at_20[0x10]; 9104 u8 op_mod[0x10]; 9105 9106 u8 reserved_at_40[0x40]; 9107 9108 struct mlx5_ifc_dctc_bits dct_context_entry; 9109 9110 u8 reserved_at_280[0x180]; 9111 }; 9112 9113 struct mlx5_ifc_create_cq_out_bits { 9114 u8 status[0x8]; 9115 u8 reserved_at_8[0x18]; 9116 9117 u8 syndrome[0x20]; 9118 9119 u8 reserved_at_40[0x8]; 9120 u8 cqn[0x18]; 9121 9122 u8 reserved_at_60[0x20]; 9123 }; 9124 9125 struct mlx5_ifc_create_cq_in_bits { 9126 u8 opcode[0x10]; 9127 u8 uid[0x10]; 9128 9129 u8 reserved_at_20[0x10]; 9130 u8 op_mod[0x10]; 9131 9132 u8 reserved_at_40[0x40]; 9133 9134 struct mlx5_ifc_cqc_bits cq_context; 9135 9136 u8 reserved_at_280[0x60]; 9137 9138 u8 cq_umem_valid[0x1]; 9139 u8 reserved_at_2e1[0x59f]; 9140 9141 u8 pas[][0x40]; 9142 }; 9143 9144 struct mlx5_ifc_config_int_moderation_out_bits { 9145 u8 status[0x8]; 9146 u8 reserved_at_8[0x18]; 9147 9148 u8 syndrome[0x20]; 9149 9150 u8 reserved_at_40[0x4]; 9151 u8 min_delay[0xc]; 9152 u8 int_vector[0x10]; 9153 9154 u8 reserved_at_60[0x20]; 9155 }; 9156 9157 enum { 9158 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0, 9159 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1, 9160 }; 9161 9162 struct mlx5_ifc_config_int_moderation_in_bits { 9163 u8 opcode[0x10]; 9164 u8 reserved_at_10[0x10]; 9165 9166 u8 reserved_at_20[0x10]; 9167 u8 op_mod[0x10]; 9168 9169 u8 reserved_at_40[0x4]; 9170 u8 min_delay[0xc]; 9171 u8 int_vector[0x10]; 9172 9173 u8 reserved_at_60[0x20]; 9174 }; 9175 9176 struct mlx5_ifc_attach_to_mcg_out_bits { 9177 u8 status[0x8]; 9178 u8 reserved_at_8[0x18]; 9179 9180 u8 syndrome[0x20]; 9181 9182 u8 reserved_at_40[0x40]; 9183 }; 9184 9185 struct mlx5_ifc_attach_to_mcg_in_bits { 9186 u8 opcode[0x10]; 9187 u8 uid[0x10]; 9188 9189 u8 reserved_at_20[0x10]; 9190 u8 op_mod[0x10]; 9191 9192 u8 reserved_at_40[0x8]; 9193 u8 qpn[0x18]; 9194 9195 u8 reserved_at_60[0x20]; 9196 9197 u8 multicast_gid[16][0x8]; 9198 }; 9199 9200 struct mlx5_ifc_arm_xrq_out_bits { 9201 u8 status[0x8]; 9202 u8 reserved_at_8[0x18]; 9203 9204 u8 syndrome[0x20]; 9205 9206 u8 reserved_at_40[0x40]; 9207 }; 9208 9209 struct mlx5_ifc_arm_xrq_in_bits { 9210 u8 opcode[0x10]; 9211 u8 reserved_at_10[0x10]; 9212 9213 u8 reserved_at_20[0x10]; 9214 u8 op_mod[0x10]; 9215 9216 u8 reserved_at_40[0x8]; 9217 u8 xrqn[0x18]; 9218 9219 u8 reserved_at_60[0x10]; 9220 u8 lwm[0x10]; 9221 }; 9222 9223 struct mlx5_ifc_arm_xrc_srq_out_bits { 9224 u8 status[0x8]; 9225 u8 reserved_at_8[0x18]; 9226 9227 u8 syndrome[0x20]; 9228 9229 u8 reserved_at_40[0x40]; 9230 }; 9231 9232 enum { 9233 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1, 9234 }; 9235 9236 struct mlx5_ifc_arm_xrc_srq_in_bits { 9237 u8 opcode[0x10]; 9238 u8 uid[0x10]; 9239 9240 u8 reserved_at_20[0x10]; 9241 u8 op_mod[0x10]; 9242 9243 u8 reserved_at_40[0x8]; 9244 u8 xrc_srqn[0x18]; 9245 9246 u8 reserved_at_60[0x10]; 9247 u8 lwm[0x10]; 9248 }; 9249 9250 struct mlx5_ifc_arm_rq_out_bits { 9251 u8 status[0x8]; 9252 u8 reserved_at_8[0x18]; 9253 9254 u8 syndrome[0x20]; 9255 9256 u8 reserved_at_40[0x40]; 9257 }; 9258 9259 enum { 9260 MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1, 9261 MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2, 9262 }; 9263 9264 struct mlx5_ifc_arm_rq_in_bits { 9265 u8 opcode[0x10]; 9266 u8 uid[0x10]; 9267 9268 u8 reserved_at_20[0x10]; 9269 u8 op_mod[0x10]; 9270 9271 u8 reserved_at_40[0x8]; 9272 u8 srq_number[0x18]; 9273 9274 u8 reserved_at_60[0x10]; 9275 u8 lwm[0x10]; 9276 }; 9277 9278 struct mlx5_ifc_arm_dct_out_bits { 9279 u8 status[0x8]; 9280 u8 reserved_at_8[0x18]; 9281 9282 u8 syndrome[0x20]; 9283 9284 u8 reserved_at_40[0x40]; 9285 }; 9286 9287 struct mlx5_ifc_arm_dct_in_bits { 9288 u8 opcode[0x10]; 9289 u8 reserved_at_10[0x10]; 9290 9291 u8 reserved_at_20[0x10]; 9292 u8 op_mod[0x10]; 9293 9294 u8 reserved_at_40[0x8]; 9295 u8 dct_number[0x18]; 9296 9297 u8 reserved_at_60[0x20]; 9298 }; 9299 9300 struct mlx5_ifc_alloc_xrcd_out_bits { 9301 u8 status[0x8]; 9302 u8 reserved_at_8[0x18]; 9303 9304 u8 syndrome[0x20]; 9305 9306 u8 reserved_at_40[0x8]; 9307 u8 xrcd[0x18]; 9308 9309 u8 reserved_at_60[0x20]; 9310 }; 9311 9312 struct mlx5_ifc_alloc_xrcd_in_bits { 9313 u8 opcode[0x10]; 9314 u8 uid[0x10]; 9315 9316 u8 reserved_at_20[0x10]; 9317 u8 op_mod[0x10]; 9318 9319 u8 reserved_at_40[0x40]; 9320 }; 9321 9322 struct mlx5_ifc_alloc_uar_out_bits { 9323 u8 status[0x8]; 9324 u8 reserved_at_8[0x18]; 9325 9326 u8 syndrome[0x20]; 9327 9328 u8 reserved_at_40[0x8]; 9329 u8 uar[0x18]; 9330 9331 u8 reserved_at_60[0x20]; 9332 }; 9333 9334 struct mlx5_ifc_alloc_uar_in_bits { 9335 u8 opcode[0x10]; 9336 u8 uid[0x10]; 9337 9338 u8 reserved_at_20[0x10]; 9339 u8 op_mod[0x10]; 9340 9341 u8 reserved_at_40[0x40]; 9342 }; 9343 9344 struct mlx5_ifc_alloc_transport_domain_out_bits { 9345 u8 status[0x8]; 9346 u8 reserved_at_8[0x18]; 9347 9348 u8 syndrome[0x20]; 9349 9350 u8 reserved_at_40[0x8]; 9351 u8 transport_domain[0x18]; 9352 9353 u8 reserved_at_60[0x20]; 9354 }; 9355 9356 struct mlx5_ifc_alloc_transport_domain_in_bits { 9357 u8 opcode[0x10]; 9358 u8 uid[0x10]; 9359 9360 u8 reserved_at_20[0x10]; 9361 u8 op_mod[0x10]; 9362 9363 u8 reserved_at_40[0x40]; 9364 }; 9365 9366 struct mlx5_ifc_alloc_q_counter_out_bits { 9367 u8 status[0x8]; 9368 u8 reserved_at_8[0x18]; 9369 9370 u8 syndrome[0x20]; 9371 9372 u8 reserved_at_40[0x18]; 9373 u8 counter_set_id[0x8]; 9374 9375 u8 reserved_at_60[0x20]; 9376 }; 9377 9378 struct mlx5_ifc_alloc_q_counter_in_bits { 9379 u8 opcode[0x10]; 9380 u8 uid[0x10]; 9381 9382 u8 reserved_at_20[0x10]; 9383 u8 op_mod[0x10]; 9384 9385 u8 reserved_at_40[0x40]; 9386 }; 9387 9388 struct mlx5_ifc_alloc_pd_out_bits { 9389 u8 status[0x8]; 9390 u8 reserved_at_8[0x18]; 9391 9392 u8 syndrome[0x20]; 9393 9394 u8 reserved_at_40[0x8]; 9395 u8 pd[0x18]; 9396 9397 u8 reserved_at_60[0x20]; 9398 }; 9399 9400 struct mlx5_ifc_alloc_pd_in_bits { 9401 u8 opcode[0x10]; 9402 u8 uid[0x10]; 9403 9404 u8 reserved_at_20[0x10]; 9405 u8 op_mod[0x10]; 9406 9407 u8 reserved_at_40[0x40]; 9408 }; 9409 9410 struct mlx5_ifc_alloc_flow_counter_out_bits { 9411 u8 status[0x8]; 9412 u8 reserved_at_8[0x18]; 9413 9414 u8 syndrome[0x20]; 9415 9416 u8 flow_counter_id[0x20]; 9417 9418 u8 reserved_at_60[0x20]; 9419 }; 9420 9421 struct mlx5_ifc_alloc_flow_counter_in_bits { 9422 u8 opcode[0x10]; 9423 u8 reserved_at_10[0x10]; 9424 9425 u8 reserved_at_20[0x10]; 9426 u8 op_mod[0x10]; 9427 9428 u8 reserved_at_40[0x33]; 9429 u8 flow_counter_bulk_log_size[0x5]; 9430 u8 flow_counter_bulk[0x8]; 9431 }; 9432 9433 struct mlx5_ifc_add_vxlan_udp_dport_out_bits { 9434 u8 status[0x8]; 9435 u8 reserved_at_8[0x18]; 9436 9437 u8 syndrome[0x20]; 9438 9439 u8 reserved_at_40[0x40]; 9440 }; 9441 9442 struct mlx5_ifc_add_vxlan_udp_dport_in_bits { 9443 u8 opcode[0x10]; 9444 u8 reserved_at_10[0x10]; 9445 9446 u8 reserved_at_20[0x10]; 9447 u8 op_mod[0x10]; 9448 9449 u8 reserved_at_40[0x20]; 9450 9451 u8 reserved_at_60[0x10]; 9452 u8 vxlan_udp_port[0x10]; 9453 }; 9454 9455 struct mlx5_ifc_set_pp_rate_limit_out_bits { 9456 u8 status[0x8]; 9457 u8 reserved_at_8[0x18]; 9458 9459 u8 syndrome[0x20]; 9460 9461 u8 reserved_at_40[0x40]; 9462 }; 9463 9464 struct mlx5_ifc_set_pp_rate_limit_context_bits { 9465 u8 rate_limit[0x20]; 9466 9467 u8 burst_upper_bound[0x20]; 9468 9469 u8 reserved_at_40[0x10]; 9470 u8 typical_packet_size[0x10]; 9471 9472 u8 reserved_at_60[0x120]; 9473 }; 9474 9475 struct mlx5_ifc_set_pp_rate_limit_in_bits { 9476 u8 opcode[0x10]; 9477 u8 uid[0x10]; 9478 9479 u8 reserved_at_20[0x10]; 9480 u8 op_mod[0x10]; 9481 9482 u8 reserved_at_40[0x10]; 9483 u8 rate_limit_index[0x10]; 9484 9485 u8 reserved_at_60[0x20]; 9486 9487 struct mlx5_ifc_set_pp_rate_limit_context_bits ctx; 9488 }; 9489 9490 struct mlx5_ifc_access_register_out_bits { 9491 u8 status[0x8]; 9492 u8 reserved_at_8[0x18]; 9493 9494 u8 syndrome[0x20]; 9495 9496 u8 reserved_at_40[0x40]; 9497 9498 u8 register_data[][0x20]; 9499 }; 9500 9501 enum { 9502 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0, 9503 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1, 9504 }; 9505 9506 struct mlx5_ifc_access_register_in_bits { 9507 u8 opcode[0x10]; 9508 u8 reserved_at_10[0x10]; 9509 9510 u8 reserved_at_20[0x10]; 9511 u8 op_mod[0x10]; 9512 9513 u8 reserved_at_40[0x10]; 9514 u8 register_id[0x10]; 9515 9516 u8 argument[0x20]; 9517 9518 u8 register_data[][0x20]; 9519 }; 9520 9521 struct mlx5_ifc_sltp_reg_bits { 9522 u8 status[0x4]; 9523 u8 version[0x4]; 9524 u8 local_port[0x8]; 9525 u8 pnat[0x2]; 9526 u8 reserved_at_12[0x2]; 9527 u8 lane[0x4]; 9528 u8 reserved_at_18[0x8]; 9529 9530 u8 reserved_at_20[0x20]; 9531 9532 u8 reserved_at_40[0x7]; 9533 u8 polarity[0x1]; 9534 u8 ob_tap0[0x8]; 9535 u8 ob_tap1[0x8]; 9536 u8 ob_tap2[0x8]; 9537 9538 u8 reserved_at_60[0xc]; 9539 u8 ob_preemp_mode[0x4]; 9540 u8 ob_reg[0x8]; 9541 u8 ob_bias[0x8]; 9542 9543 u8 reserved_at_80[0x20]; 9544 }; 9545 9546 struct mlx5_ifc_slrg_reg_bits { 9547 u8 status[0x4]; 9548 u8 version[0x4]; 9549 u8 local_port[0x8]; 9550 u8 pnat[0x2]; 9551 u8 reserved_at_12[0x2]; 9552 u8 lane[0x4]; 9553 u8 reserved_at_18[0x8]; 9554 9555 u8 time_to_link_up[0x10]; 9556 u8 reserved_at_30[0xc]; 9557 u8 grade_lane_speed[0x4]; 9558 9559 u8 grade_version[0x8]; 9560 u8 grade[0x18]; 9561 9562 u8 reserved_at_60[0x4]; 9563 u8 height_grade_type[0x4]; 9564 u8 height_grade[0x18]; 9565 9566 u8 height_dz[0x10]; 9567 u8 height_dv[0x10]; 9568 9569 u8 reserved_at_a0[0x10]; 9570 u8 height_sigma[0x10]; 9571 9572 u8 reserved_at_c0[0x20]; 9573 9574 u8 reserved_at_e0[0x4]; 9575 u8 phase_grade_type[0x4]; 9576 u8 phase_grade[0x18]; 9577 9578 u8 reserved_at_100[0x8]; 9579 u8 phase_eo_pos[0x8]; 9580 u8 reserved_at_110[0x8]; 9581 u8 phase_eo_neg[0x8]; 9582 9583 u8 ffe_set_tested[0x10]; 9584 u8 test_errors_per_lane[0x10]; 9585 }; 9586 9587 struct mlx5_ifc_pvlc_reg_bits { 9588 u8 reserved_at_0[0x8]; 9589 u8 local_port[0x8]; 9590 u8 reserved_at_10[0x10]; 9591 9592 u8 reserved_at_20[0x1c]; 9593 u8 vl_hw_cap[0x4]; 9594 9595 u8 reserved_at_40[0x1c]; 9596 u8 vl_admin[0x4]; 9597 9598 u8 reserved_at_60[0x1c]; 9599 u8 vl_operational[0x4]; 9600 }; 9601 9602 struct mlx5_ifc_pude_reg_bits { 9603 u8 swid[0x8]; 9604 u8 local_port[0x8]; 9605 u8 reserved_at_10[0x4]; 9606 u8 admin_status[0x4]; 9607 u8 reserved_at_18[0x4]; 9608 u8 oper_status[0x4]; 9609 9610 u8 reserved_at_20[0x60]; 9611 }; 9612 9613 struct mlx5_ifc_ptys_reg_bits { 9614 u8 reserved_at_0[0x1]; 9615 u8 an_disable_admin[0x1]; 9616 u8 an_disable_cap[0x1]; 9617 u8 reserved_at_3[0x5]; 9618 u8 local_port[0x8]; 9619 u8 reserved_at_10[0xd]; 9620 u8 proto_mask[0x3]; 9621 9622 u8 an_status[0x4]; 9623 u8 reserved_at_24[0xc]; 9624 u8 data_rate_oper[0x10]; 9625 9626 u8 ext_eth_proto_capability[0x20]; 9627 9628 u8 eth_proto_capability[0x20]; 9629 9630 u8 ib_link_width_capability[0x10]; 9631 u8 ib_proto_capability[0x10]; 9632 9633 u8 ext_eth_proto_admin[0x20]; 9634 9635 u8 eth_proto_admin[0x20]; 9636 9637 u8 ib_link_width_admin[0x10]; 9638 u8 ib_proto_admin[0x10]; 9639 9640 u8 ext_eth_proto_oper[0x20]; 9641 9642 u8 eth_proto_oper[0x20]; 9643 9644 u8 ib_link_width_oper[0x10]; 9645 u8 ib_proto_oper[0x10]; 9646 9647 u8 reserved_at_160[0x1c]; 9648 u8 connector_type[0x4]; 9649 9650 u8 eth_proto_lp_advertise[0x20]; 9651 9652 u8 reserved_at_1a0[0x60]; 9653 }; 9654 9655 struct mlx5_ifc_mlcr_reg_bits { 9656 u8 reserved_at_0[0x8]; 9657 u8 local_port[0x8]; 9658 u8 reserved_at_10[0x20]; 9659 9660 u8 beacon_duration[0x10]; 9661 u8 reserved_at_40[0x10]; 9662 9663 u8 beacon_remain[0x10]; 9664 }; 9665 9666 struct mlx5_ifc_ptas_reg_bits { 9667 u8 reserved_at_0[0x20]; 9668 9669 u8 algorithm_options[0x10]; 9670 u8 reserved_at_30[0x4]; 9671 u8 repetitions_mode[0x4]; 9672 u8 num_of_repetitions[0x8]; 9673 9674 u8 grade_version[0x8]; 9675 u8 height_grade_type[0x4]; 9676 u8 phase_grade_type[0x4]; 9677 u8 height_grade_weight[0x8]; 9678 u8 phase_grade_weight[0x8]; 9679 9680 u8 gisim_measure_bits[0x10]; 9681 u8 adaptive_tap_measure_bits[0x10]; 9682 9683 u8 ber_bath_high_error_threshold[0x10]; 9684 u8 ber_bath_mid_error_threshold[0x10]; 9685 9686 u8 ber_bath_low_error_threshold[0x10]; 9687 u8 one_ratio_high_threshold[0x10]; 9688 9689 u8 one_ratio_high_mid_threshold[0x10]; 9690 u8 one_ratio_low_mid_threshold[0x10]; 9691 9692 u8 one_ratio_low_threshold[0x10]; 9693 u8 ndeo_error_threshold[0x10]; 9694 9695 u8 mixer_offset_step_size[0x10]; 9696 u8 reserved_at_110[0x8]; 9697 u8 mix90_phase_for_voltage_bath[0x8]; 9698 9699 u8 mixer_offset_start[0x10]; 9700 u8 mixer_offset_end[0x10]; 9701 9702 u8 reserved_at_140[0x15]; 9703 u8 ber_test_time[0xb]; 9704 }; 9705 9706 struct mlx5_ifc_pspa_reg_bits { 9707 u8 swid[0x8]; 9708 u8 local_port[0x8]; 9709 u8 sub_port[0x8]; 9710 u8 reserved_at_18[0x8]; 9711 9712 u8 reserved_at_20[0x20]; 9713 }; 9714 9715 struct mlx5_ifc_pqdr_reg_bits { 9716 u8 reserved_at_0[0x8]; 9717 u8 local_port[0x8]; 9718 u8 reserved_at_10[0x5]; 9719 u8 prio[0x3]; 9720 u8 reserved_at_18[0x6]; 9721 u8 mode[0x2]; 9722 9723 u8 reserved_at_20[0x20]; 9724 9725 u8 reserved_at_40[0x10]; 9726 u8 min_threshold[0x10]; 9727 9728 u8 reserved_at_60[0x10]; 9729 u8 max_threshold[0x10]; 9730 9731 u8 reserved_at_80[0x10]; 9732 u8 mark_probability_denominator[0x10]; 9733 9734 u8 reserved_at_a0[0x60]; 9735 }; 9736 9737 struct mlx5_ifc_ppsc_reg_bits { 9738 u8 reserved_at_0[0x8]; 9739 u8 local_port[0x8]; 9740 u8 reserved_at_10[0x10]; 9741 9742 u8 reserved_at_20[0x60]; 9743 9744 u8 reserved_at_80[0x1c]; 9745 u8 wrps_admin[0x4]; 9746 9747 u8 reserved_at_a0[0x1c]; 9748 u8 wrps_status[0x4]; 9749 9750 u8 reserved_at_c0[0x8]; 9751 u8 up_threshold[0x8]; 9752 u8 reserved_at_d0[0x8]; 9753 u8 down_threshold[0x8]; 9754 9755 u8 reserved_at_e0[0x20]; 9756 9757 u8 reserved_at_100[0x1c]; 9758 u8 srps_admin[0x4]; 9759 9760 u8 reserved_at_120[0x1c]; 9761 u8 srps_status[0x4]; 9762 9763 u8 reserved_at_140[0x40]; 9764 }; 9765 9766 struct mlx5_ifc_pplr_reg_bits { 9767 u8 reserved_at_0[0x8]; 9768 u8 local_port[0x8]; 9769 u8 reserved_at_10[0x10]; 9770 9771 u8 reserved_at_20[0x8]; 9772 u8 lb_cap[0x8]; 9773 u8 reserved_at_30[0x8]; 9774 u8 lb_en[0x8]; 9775 }; 9776 9777 struct mlx5_ifc_pplm_reg_bits { 9778 u8 reserved_at_0[0x8]; 9779 u8 local_port[0x8]; 9780 u8 reserved_at_10[0x10]; 9781 9782 u8 reserved_at_20[0x20]; 9783 9784 u8 port_profile_mode[0x8]; 9785 u8 static_port_profile[0x8]; 9786 u8 active_port_profile[0x8]; 9787 u8 reserved_at_58[0x8]; 9788 9789 u8 retransmission_active[0x8]; 9790 u8 fec_mode_active[0x18]; 9791 9792 u8 rs_fec_correction_bypass_cap[0x4]; 9793 u8 reserved_at_84[0x8]; 9794 u8 fec_override_cap_56g[0x4]; 9795 u8 fec_override_cap_100g[0x4]; 9796 u8 fec_override_cap_50g[0x4]; 9797 u8 fec_override_cap_25g[0x4]; 9798 u8 fec_override_cap_10g_40g[0x4]; 9799 9800 u8 rs_fec_correction_bypass_admin[0x4]; 9801 u8 reserved_at_a4[0x8]; 9802 u8 fec_override_admin_56g[0x4]; 9803 u8 fec_override_admin_100g[0x4]; 9804 u8 fec_override_admin_50g[0x4]; 9805 u8 fec_override_admin_25g[0x4]; 9806 u8 fec_override_admin_10g_40g[0x4]; 9807 9808 u8 fec_override_cap_400g_8x[0x10]; 9809 u8 fec_override_cap_200g_4x[0x10]; 9810 9811 u8 fec_override_cap_100g_2x[0x10]; 9812 u8 fec_override_cap_50g_1x[0x10]; 9813 9814 u8 fec_override_admin_400g_8x[0x10]; 9815 u8 fec_override_admin_200g_4x[0x10]; 9816 9817 u8 fec_override_admin_100g_2x[0x10]; 9818 u8 fec_override_admin_50g_1x[0x10]; 9819 9820 u8 fec_override_cap_800g_8x[0x10]; 9821 u8 fec_override_cap_400g_4x[0x10]; 9822 9823 u8 fec_override_cap_200g_2x[0x10]; 9824 u8 fec_override_cap_100g_1x[0x10]; 9825 9826 u8 reserved_at_180[0xa0]; 9827 9828 u8 fec_override_admin_800g_8x[0x10]; 9829 u8 fec_override_admin_400g_4x[0x10]; 9830 9831 u8 fec_override_admin_200g_2x[0x10]; 9832 u8 fec_override_admin_100g_1x[0x10]; 9833 9834 u8 reserved_at_260[0x20]; 9835 }; 9836 9837 struct mlx5_ifc_ppcnt_reg_bits { 9838 u8 swid[0x8]; 9839 u8 local_port[0x8]; 9840 u8 pnat[0x2]; 9841 u8 reserved_at_12[0x8]; 9842 u8 grp[0x6]; 9843 9844 u8 clr[0x1]; 9845 u8 reserved_at_21[0x1c]; 9846 u8 prio_tc[0x3]; 9847 9848 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set; 9849 }; 9850 9851 struct mlx5_ifc_mpein_reg_bits { 9852 u8 reserved_at_0[0x2]; 9853 u8 depth[0x6]; 9854 u8 pcie_index[0x8]; 9855 u8 node[0x8]; 9856 u8 reserved_at_18[0x8]; 9857 9858 u8 capability_mask[0x20]; 9859 9860 u8 reserved_at_40[0x8]; 9861 u8 link_width_enabled[0x8]; 9862 u8 link_speed_enabled[0x10]; 9863 9864 u8 lane0_physical_position[0x8]; 9865 u8 link_width_active[0x8]; 9866 u8 link_speed_active[0x10]; 9867 9868 u8 num_of_pfs[0x10]; 9869 u8 num_of_vfs[0x10]; 9870 9871 u8 bdf0[0x10]; 9872 u8 reserved_at_b0[0x10]; 9873 9874 u8 max_read_request_size[0x4]; 9875 u8 max_payload_size[0x4]; 9876 u8 reserved_at_c8[0x5]; 9877 u8 pwr_status[0x3]; 9878 u8 port_type[0x4]; 9879 u8 reserved_at_d4[0xb]; 9880 u8 lane_reversal[0x1]; 9881 9882 u8 reserved_at_e0[0x14]; 9883 u8 pci_power[0xc]; 9884 9885 u8 reserved_at_100[0x20]; 9886 9887 u8 device_status[0x10]; 9888 u8 port_state[0x8]; 9889 u8 reserved_at_138[0x8]; 9890 9891 u8 reserved_at_140[0x10]; 9892 u8 receiver_detect_result[0x10]; 9893 9894 u8 reserved_at_160[0x20]; 9895 }; 9896 9897 struct mlx5_ifc_mpcnt_reg_bits { 9898 u8 reserved_at_0[0x8]; 9899 u8 pcie_index[0x8]; 9900 u8 reserved_at_10[0xa]; 9901 u8 grp[0x6]; 9902 9903 u8 clr[0x1]; 9904 u8 reserved_at_21[0x1f]; 9905 9906 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set; 9907 }; 9908 9909 struct mlx5_ifc_ppad_reg_bits { 9910 u8 reserved_at_0[0x3]; 9911 u8 single_mac[0x1]; 9912 u8 reserved_at_4[0x4]; 9913 u8 local_port[0x8]; 9914 u8 mac_47_32[0x10]; 9915 9916 u8 mac_31_0[0x20]; 9917 9918 u8 reserved_at_40[0x40]; 9919 }; 9920 9921 struct mlx5_ifc_pmtu_reg_bits { 9922 u8 reserved_at_0[0x8]; 9923 u8 local_port[0x8]; 9924 u8 reserved_at_10[0x10]; 9925 9926 u8 max_mtu[0x10]; 9927 u8 reserved_at_30[0x10]; 9928 9929 u8 admin_mtu[0x10]; 9930 u8 reserved_at_50[0x10]; 9931 9932 u8 oper_mtu[0x10]; 9933 u8 reserved_at_70[0x10]; 9934 }; 9935 9936 struct mlx5_ifc_pmpr_reg_bits { 9937 u8 reserved_at_0[0x8]; 9938 u8 module[0x8]; 9939 u8 reserved_at_10[0x10]; 9940 9941 u8 reserved_at_20[0x18]; 9942 u8 attenuation_5g[0x8]; 9943 9944 u8 reserved_at_40[0x18]; 9945 u8 attenuation_7g[0x8]; 9946 9947 u8 reserved_at_60[0x18]; 9948 u8 attenuation_12g[0x8]; 9949 }; 9950 9951 struct mlx5_ifc_pmpe_reg_bits { 9952 u8 reserved_at_0[0x8]; 9953 u8 module[0x8]; 9954 u8 reserved_at_10[0xc]; 9955 u8 module_status[0x4]; 9956 9957 u8 reserved_at_20[0x60]; 9958 }; 9959 9960 struct mlx5_ifc_pmpc_reg_bits { 9961 u8 module_state_updated[32][0x8]; 9962 }; 9963 9964 struct mlx5_ifc_pmlpn_reg_bits { 9965 u8 reserved_at_0[0x4]; 9966 u8 mlpn_status[0x4]; 9967 u8 local_port[0x8]; 9968 u8 reserved_at_10[0x10]; 9969 9970 u8 e[0x1]; 9971 u8 reserved_at_21[0x1f]; 9972 }; 9973 9974 struct mlx5_ifc_pmlp_reg_bits { 9975 u8 rxtx[0x1]; 9976 u8 reserved_at_1[0x7]; 9977 u8 local_port[0x8]; 9978 u8 reserved_at_10[0x8]; 9979 u8 width[0x8]; 9980 9981 u8 lane0_module_mapping[0x20]; 9982 9983 u8 lane1_module_mapping[0x20]; 9984 9985 u8 lane2_module_mapping[0x20]; 9986 9987 u8 lane3_module_mapping[0x20]; 9988 9989 u8 reserved_at_a0[0x160]; 9990 }; 9991 9992 struct mlx5_ifc_pmaos_reg_bits { 9993 u8 reserved_at_0[0x8]; 9994 u8 module[0x8]; 9995 u8 reserved_at_10[0x4]; 9996 u8 admin_status[0x4]; 9997 u8 reserved_at_18[0x4]; 9998 u8 oper_status[0x4]; 9999 10000 u8 ase[0x1]; 10001 u8 ee[0x1]; 10002 u8 reserved_at_22[0x1c]; 10003 u8 e[0x2]; 10004 10005 u8 reserved_at_40[0x40]; 10006 }; 10007 10008 struct mlx5_ifc_plpc_reg_bits { 10009 u8 reserved_at_0[0x4]; 10010 u8 profile_id[0xc]; 10011 u8 reserved_at_10[0x4]; 10012 u8 proto_mask[0x4]; 10013 u8 reserved_at_18[0x8]; 10014 10015 u8 reserved_at_20[0x10]; 10016 u8 lane_speed[0x10]; 10017 10018 u8 reserved_at_40[0x17]; 10019 u8 lpbf[0x1]; 10020 u8 fec_mode_policy[0x8]; 10021 10022 u8 retransmission_capability[0x8]; 10023 u8 fec_mode_capability[0x18]; 10024 10025 u8 retransmission_support_admin[0x8]; 10026 u8 fec_mode_support_admin[0x18]; 10027 10028 u8 retransmission_request_admin[0x8]; 10029 u8 fec_mode_request_admin[0x18]; 10030 10031 u8 reserved_at_c0[0x80]; 10032 }; 10033 10034 struct mlx5_ifc_plib_reg_bits { 10035 u8 reserved_at_0[0x8]; 10036 u8 local_port[0x8]; 10037 u8 reserved_at_10[0x8]; 10038 u8 ib_port[0x8]; 10039 10040 u8 reserved_at_20[0x60]; 10041 }; 10042 10043 struct mlx5_ifc_plbf_reg_bits { 10044 u8 reserved_at_0[0x8]; 10045 u8 local_port[0x8]; 10046 u8 reserved_at_10[0xd]; 10047 u8 lbf_mode[0x3]; 10048 10049 u8 reserved_at_20[0x20]; 10050 }; 10051 10052 struct mlx5_ifc_pipg_reg_bits { 10053 u8 reserved_at_0[0x8]; 10054 u8 local_port[0x8]; 10055 u8 reserved_at_10[0x10]; 10056 10057 u8 dic[0x1]; 10058 u8 reserved_at_21[0x19]; 10059 u8 ipg[0x4]; 10060 u8 reserved_at_3e[0x2]; 10061 }; 10062 10063 struct mlx5_ifc_pifr_reg_bits { 10064 u8 reserved_at_0[0x8]; 10065 u8 local_port[0x8]; 10066 u8 reserved_at_10[0x10]; 10067 10068 u8 reserved_at_20[0xe0]; 10069 10070 u8 port_filter[8][0x20]; 10071 10072 u8 port_filter_update_en[8][0x20]; 10073 }; 10074 10075 struct mlx5_ifc_pfcc_reg_bits { 10076 u8 reserved_at_0[0x8]; 10077 u8 local_port[0x8]; 10078 u8 reserved_at_10[0xb]; 10079 u8 ppan_mask_n[0x1]; 10080 u8 minor_stall_mask[0x1]; 10081 u8 critical_stall_mask[0x1]; 10082 u8 reserved_at_1e[0x2]; 10083 10084 u8 ppan[0x4]; 10085 u8 reserved_at_24[0x4]; 10086 u8 prio_mask_tx[0x8]; 10087 u8 reserved_at_30[0x8]; 10088 u8 prio_mask_rx[0x8]; 10089 10090 u8 pptx[0x1]; 10091 u8 aptx[0x1]; 10092 u8 pptx_mask_n[0x1]; 10093 u8 reserved_at_43[0x5]; 10094 u8 pfctx[0x8]; 10095 u8 reserved_at_50[0x10]; 10096 10097 u8 pprx[0x1]; 10098 u8 aprx[0x1]; 10099 u8 pprx_mask_n[0x1]; 10100 u8 reserved_at_63[0x5]; 10101 u8 pfcrx[0x8]; 10102 u8 reserved_at_70[0x10]; 10103 10104 u8 device_stall_minor_watermark[0x10]; 10105 u8 device_stall_critical_watermark[0x10]; 10106 10107 u8 reserved_at_a0[0x60]; 10108 }; 10109 10110 struct mlx5_ifc_pelc_reg_bits { 10111 u8 op[0x4]; 10112 u8 reserved_at_4[0x4]; 10113 u8 local_port[0x8]; 10114 u8 reserved_at_10[0x10]; 10115 10116 u8 op_admin[0x8]; 10117 u8 op_capability[0x8]; 10118 u8 op_request[0x8]; 10119 u8 op_active[0x8]; 10120 10121 u8 admin[0x40]; 10122 10123 u8 capability[0x40]; 10124 10125 u8 request[0x40]; 10126 10127 u8 active[0x40]; 10128 10129 u8 reserved_at_140[0x80]; 10130 }; 10131 10132 struct mlx5_ifc_peir_reg_bits { 10133 u8 reserved_at_0[0x8]; 10134 u8 local_port[0x8]; 10135 u8 reserved_at_10[0x10]; 10136 10137 u8 reserved_at_20[0xc]; 10138 u8 error_count[0x4]; 10139 u8 reserved_at_30[0x10]; 10140 10141 u8 reserved_at_40[0xc]; 10142 u8 lane[0x4]; 10143 u8 reserved_at_50[0x8]; 10144 u8 error_type[0x8]; 10145 }; 10146 10147 struct mlx5_ifc_mpegc_reg_bits { 10148 u8 reserved_at_0[0x30]; 10149 u8 field_select[0x10]; 10150 10151 u8 tx_overflow_sense[0x1]; 10152 u8 mark_cqe[0x1]; 10153 u8 mark_cnp[0x1]; 10154 u8 reserved_at_43[0x1b]; 10155 u8 tx_lossy_overflow_oper[0x2]; 10156 10157 u8 reserved_at_60[0x100]; 10158 }; 10159 10160 struct mlx5_ifc_mpir_reg_bits { 10161 u8 sdm[0x1]; 10162 u8 reserved_at_1[0x1b]; 10163 u8 host_buses[0x4]; 10164 10165 u8 reserved_at_20[0x20]; 10166 10167 u8 local_port[0x8]; 10168 u8 reserved_at_28[0x18]; 10169 10170 u8 reserved_at_60[0x20]; 10171 }; 10172 10173 enum { 10174 MLX5_MTUTC_FREQ_ADJ_UNITS_PPB = 0x0, 10175 MLX5_MTUTC_FREQ_ADJ_UNITS_SCALED_PPM = 0x1, 10176 }; 10177 10178 enum { 10179 MLX5_MTUTC_OPERATION_SET_TIME_IMMEDIATE = 0x1, 10180 MLX5_MTUTC_OPERATION_ADJUST_TIME = 0x2, 10181 MLX5_MTUTC_OPERATION_ADJUST_FREQ_UTC = 0x3, 10182 }; 10183 10184 struct mlx5_ifc_mtutc_reg_bits { 10185 u8 reserved_at_0[0x5]; 10186 u8 freq_adj_units[0x3]; 10187 u8 reserved_at_8[0x3]; 10188 u8 log_max_freq_adjustment[0x5]; 10189 10190 u8 reserved_at_10[0xc]; 10191 u8 operation[0x4]; 10192 10193 u8 freq_adjustment[0x20]; 10194 10195 u8 reserved_at_40[0x40]; 10196 10197 u8 utc_sec[0x20]; 10198 10199 u8 reserved_at_a0[0x2]; 10200 u8 utc_nsec[0x1e]; 10201 10202 u8 time_adjustment[0x20]; 10203 }; 10204 10205 struct mlx5_ifc_pcam_enhanced_features_bits { 10206 u8 reserved_at_0[0x48]; 10207 u8 fec_100G_per_lane_in_pplm[0x1]; 10208 u8 reserved_at_49[0x1f]; 10209 u8 fec_50G_per_lane_in_pplm[0x1]; 10210 u8 reserved_at_69[0x4]; 10211 u8 rx_icrc_encapsulated_counter[0x1]; 10212 u8 reserved_at_6e[0x4]; 10213 u8 ptys_extended_ethernet[0x1]; 10214 u8 reserved_at_73[0x3]; 10215 u8 pfcc_mask[0x1]; 10216 u8 reserved_at_77[0x3]; 10217 u8 per_lane_error_counters[0x1]; 10218 u8 rx_buffer_fullness_counters[0x1]; 10219 u8 ptys_connector_type[0x1]; 10220 u8 reserved_at_7d[0x1]; 10221 u8 ppcnt_discard_group[0x1]; 10222 u8 ppcnt_statistical_group[0x1]; 10223 }; 10224 10225 struct mlx5_ifc_pcam_regs_5000_to_507f_bits { 10226 u8 port_access_reg_cap_mask_127_to_96[0x20]; 10227 u8 port_access_reg_cap_mask_95_to_64[0x20]; 10228 10229 u8 port_access_reg_cap_mask_63_to_36[0x1c]; 10230 u8 pplm[0x1]; 10231 u8 port_access_reg_cap_mask_34_to_32[0x3]; 10232 10233 u8 port_access_reg_cap_mask_31_to_13[0x13]; 10234 u8 pbmc[0x1]; 10235 u8 pptb[0x1]; 10236 u8 port_access_reg_cap_mask_10_to_09[0x2]; 10237 u8 ppcnt[0x1]; 10238 u8 port_access_reg_cap_mask_07_to_00[0x8]; 10239 }; 10240 10241 struct mlx5_ifc_pcam_reg_bits { 10242 u8 reserved_at_0[0x8]; 10243 u8 feature_group[0x8]; 10244 u8 reserved_at_10[0x8]; 10245 u8 access_reg_group[0x8]; 10246 10247 u8 reserved_at_20[0x20]; 10248 10249 union { 10250 struct mlx5_ifc_pcam_regs_5000_to_507f_bits regs_5000_to_507f; 10251 u8 reserved_at_0[0x80]; 10252 } port_access_reg_cap_mask; 10253 10254 u8 reserved_at_c0[0x80]; 10255 10256 union { 10257 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features; 10258 u8 reserved_at_0[0x80]; 10259 } feature_cap_mask; 10260 10261 u8 reserved_at_1c0[0xc0]; 10262 }; 10263 10264 struct mlx5_ifc_mcam_enhanced_features_bits { 10265 u8 reserved_at_0[0x50]; 10266 u8 mtutc_freq_adj_units[0x1]; 10267 u8 mtutc_time_adjustment_extended_range[0x1]; 10268 u8 reserved_at_52[0xb]; 10269 u8 mcia_32dwords[0x1]; 10270 u8 out_pulse_duration_ns[0x1]; 10271 u8 npps_period[0x1]; 10272 u8 reserved_at_60[0xa]; 10273 u8 reset_state[0x1]; 10274 u8 ptpcyc2realtime_modify[0x1]; 10275 u8 reserved_at_6c[0x2]; 10276 u8 pci_status_and_power[0x1]; 10277 u8 reserved_at_6f[0x5]; 10278 u8 mark_tx_action_cnp[0x1]; 10279 u8 mark_tx_action_cqe[0x1]; 10280 u8 dynamic_tx_overflow[0x1]; 10281 u8 reserved_at_77[0x4]; 10282 u8 pcie_outbound_stalled[0x1]; 10283 u8 tx_overflow_buffer_pkt[0x1]; 10284 u8 mtpps_enh_out_per_adj[0x1]; 10285 u8 mtpps_fs[0x1]; 10286 u8 pcie_performance_group[0x1]; 10287 }; 10288 10289 struct mlx5_ifc_mcam_access_reg_bits { 10290 u8 reserved_at_0[0x1c]; 10291 u8 mcda[0x1]; 10292 u8 mcc[0x1]; 10293 u8 mcqi[0x1]; 10294 u8 mcqs[0x1]; 10295 10296 u8 regs_95_to_90[0x6]; 10297 u8 mpir[0x1]; 10298 u8 regs_88_to_87[0x2]; 10299 u8 mpegc[0x1]; 10300 u8 mtutc[0x1]; 10301 u8 regs_84_to_68[0x11]; 10302 u8 tracer_registers[0x4]; 10303 10304 u8 regs_63_to_46[0x12]; 10305 u8 mrtc[0x1]; 10306 u8 regs_44_to_41[0x4]; 10307 u8 mfrl[0x1]; 10308 u8 regs_39_to_32[0x8]; 10309 10310 u8 regs_31_to_10[0x16]; 10311 u8 mtmp[0x1]; 10312 u8 regs_8_to_0[0x9]; 10313 }; 10314 10315 struct mlx5_ifc_mcam_access_reg_bits1 { 10316 u8 regs_127_to_96[0x20]; 10317 10318 u8 regs_95_to_64[0x20]; 10319 10320 u8 regs_63_to_32[0x20]; 10321 10322 u8 regs_31_to_0[0x20]; 10323 }; 10324 10325 struct mlx5_ifc_mcam_access_reg_bits2 { 10326 u8 regs_127_to_99[0x1d]; 10327 u8 mirc[0x1]; 10328 u8 regs_97_to_96[0x2]; 10329 10330 u8 regs_95_to_87[0x09]; 10331 u8 synce_registers[0x2]; 10332 u8 regs_84_to_64[0x15]; 10333 10334 u8 regs_63_to_32[0x20]; 10335 10336 u8 regs_31_to_0[0x20]; 10337 }; 10338 10339 struct mlx5_ifc_mcam_reg_bits { 10340 u8 reserved_at_0[0x8]; 10341 u8 feature_group[0x8]; 10342 u8 reserved_at_10[0x8]; 10343 u8 access_reg_group[0x8]; 10344 10345 u8 reserved_at_20[0x20]; 10346 10347 union { 10348 struct mlx5_ifc_mcam_access_reg_bits access_regs; 10349 struct mlx5_ifc_mcam_access_reg_bits1 access_regs1; 10350 struct mlx5_ifc_mcam_access_reg_bits2 access_regs2; 10351 u8 reserved_at_0[0x80]; 10352 } mng_access_reg_cap_mask; 10353 10354 u8 reserved_at_c0[0x80]; 10355 10356 union { 10357 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features; 10358 u8 reserved_at_0[0x80]; 10359 } mng_feature_cap_mask; 10360 10361 u8 reserved_at_1c0[0x80]; 10362 }; 10363 10364 struct mlx5_ifc_qcam_access_reg_cap_mask { 10365 u8 qcam_access_reg_cap_mask_127_to_20[0x6C]; 10366 u8 qpdpm[0x1]; 10367 u8 qcam_access_reg_cap_mask_18_to_4[0x0F]; 10368 u8 qdpm[0x1]; 10369 u8 qpts[0x1]; 10370 u8 qcap[0x1]; 10371 u8 qcam_access_reg_cap_mask_0[0x1]; 10372 }; 10373 10374 struct mlx5_ifc_qcam_qos_feature_cap_mask { 10375 u8 qcam_qos_feature_cap_mask_127_to_1[0x7F]; 10376 u8 qpts_trust_both[0x1]; 10377 }; 10378 10379 struct mlx5_ifc_qcam_reg_bits { 10380 u8 reserved_at_0[0x8]; 10381 u8 feature_group[0x8]; 10382 u8 reserved_at_10[0x8]; 10383 u8 access_reg_group[0x8]; 10384 u8 reserved_at_20[0x20]; 10385 10386 union { 10387 struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap; 10388 u8 reserved_at_0[0x80]; 10389 } qos_access_reg_cap_mask; 10390 10391 u8 reserved_at_c0[0x80]; 10392 10393 union { 10394 struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap; 10395 u8 reserved_at_0[0x80]; 10396 } qos_feature_cap_mask; 10397 10398 u8 reserved_at_1c0[0x80]; 10399 }; 10400 10401 struct mlx5_ifc_core_dump_reg_bits { 10402 u8 reserved_at_0[0x18]; 10403 u8 core_dump_type[0x8]; 10404 10405 u8 reserved_at_20[0x30]; 10406 u8 vhca_id[0x10]; 10407 10408 u8 reserved_at_60[0x8]; 10409 u8 qpn[0x18]; 10410 u8 reserved_at_80[0x180]; 10411 }; 10412 10413 struct mlx5_ifc_pcap_reg_bits { 10414 u8 reserved_at_0[0x8]; 10415 u8 local_port[0x8]; 10416 u8 reserved_at_10[0x10]; 10417 10418 u8 port_capability_mask[4][0x20]; 10419 }; 10420 10421 struct mlx5_ifc_paos_reg_bits { 10422 u8 swid[0x8]; 10423 u8 local_port[0x8]; 10424 u8 reserved_at_10[0x4]; 10425 u8 admin_status[0x4]; 10426 u8 reserved_at_18[0x4]; 10427 u8 oper_status[0x4]; 10428 10429 u8 ase[0x1]; 10430 u8 ee[0x1]; 10431 u8 reserved_at_22[0x1c]; 10432 u8 e[0x2]; 10433 10434 u8 reserved_at_40[0x40]; 10435 }; 10436 10437 struct mlx5_ifc_pamp_reg_bits { 10438 u8 reserved_at_0[0x8]; 10439 u8 opamp_group[0x8]; 10440 u8 reserved_at_10[0xc]; 10441 u8 opamp_group_type[0x4]; 10442 10443 u8 start_index[0x10]; 10444 u8 reserved_at_30[0x4]; 10445 u8 num_of_indices[0xc]; 10446 10447 u8 index_data[18][0x10]; 10448 }; 10449 10450 struct mlx5_ifc_pcmr_reg_bits { 10451 u8 reserved_at_0[0x8]; 10452 u8 local_port[0x8]; 10453 u8 reserved_at_10[0x10]; 10454 10455 u8 entropy_force_cap[0x1]; 10456 u8 entropy_calc_cap[0x1]; 10457 u8 entropy_gre_calc_cap[0x1]; 10458 u8 reserved_at_23[0xf]; 10459 u8 rx_ts_over_crc_cap[0x1]; 10460 u8 reserved_at_33[0xb]; 10461 u8 fcs_cap[0x1]; 10462 u8 reserved_at_3f[0x1]; 10463 10464 u8 entropy_force[0x1]; 10465 u8 entropy_calc[0x1]; 10466 u8 entropy_gre_calc[0x1]; 10467 u8 reserved_at_43[0xf]; 10468 u8 rx_ts_over_crc[0x1]; 10469 u8 reserved_at_53[0xb]; 10470 u8 fcs_chk[0x1]; 10471 u8 reserved_at_5f[0x1]; 10472 }; 10473 10474 struct mlx5_ifc_lane_2_module_mapping_bits { 10475 u8 reserved_at_0[0x4]; 10476 u8 rx_lane[0x4]; 10477 u8 reserved_at_8[0x4]; 10478 u8 tx_lane[0x4]; 10479 u8 reserved_at_10[0x8]; 10480 u8 module[0x8]; 10481 }; 10482 10483 struct mlx5_ifc_bufferx_reg_bits { 10484 u8 reserved_at_0[0x6]; 10485 u8 lossy[0x1]; 10486 u8 epsb[0x1]; 10487 u8 reserved_at_8[0x8]; 10488 u8 size[0x10]; 10489 10490 u8 xoff_threshold[0x10]; 10491 u8 xon_threshold[0x10]; 10492 }; 10493 10494 struct mlx5_ifc_set_node_in_bits { 10495 u8 node_description[64][0x8]; 10496 }; 10497 10498 struct mlx5_ifc_register_power_settings_bits { 10499 u8 reserved_at_0[0x18]; 10500 u8 power_settings_level[0x8]; 10501 10502 u8 reserved_at_20[0x60]; 10503 }; 10504 10505 struct mlx5_ifc_register_host_endianness_bits { 10506 u8 he[0x1]; 10507 u8 reserved_at_1[0x1f]; 10508 10509 u8 reserved_at_20[0x60]; 10510 }; 10511 10512 struct mlx5_ifc_umr_pointer_desc_argument_bits { 10513 u8 reserved_at_0[0x20]; 10514 10515 u8 mkey[0x20]; 10516 10517 u8 addressh_63_32[0x20]; 10518 10519 u8 addressl_31_0[0x20]; 10520 }; 10521 10522 struct mlx5_ifc_ud_adrs_vector_bits { 10523 u8 dc_key[0x40]; 10524 10525 u8 ext[0x1]; 10526 u8 reserved_at_41[0x7]; 10527 u8 destination_qp_dct[0x18]; 10528 10529 u8 static_rate[0x4]; 10530 u8 sl_eth_prio[0x4]; 10531 u8 fl[0x1]; 10532 u8 mlid[0x7]; 10533 u8 rlid_udp_sport[0x10]; 10534 10535 u8 reserved_at_80[0x20]; 10536 10537 u8 rmac_47_16[0x20]; 10538 10539 u8 rmac_15_0[0x10]; 10540 u8 tclass[0x8]; 10541 u8 hop_limit[0x8]; 10542 10543 u8 reserved_at_e0[0x1]; 10544 u8 grh[0x1]; 10545 u8 reserved_at_e2[0x2]; 10546 u8 src_addr_index[0x8]; 10547 u8 flow_label[0x14]; 10548 10549 u8 rgid_rip[16][0x8]; 10550 }; 10551 10552 struct mlx5_ifc_pages_req_event_bits { 10553 u8 reserved_at_0[0x10]; 10554 u8 function_id[0x10]; 10555 10556 u8 num_pages[0x20]; 10557 10558 u8 reserved_at_40[0xa0]; 10559 }; 10560 10561 struct mlx5_ifc_eqe_bits { 10562 u8 reserved_at_0[0x8]; 10563 u8 event_type[0x8]; 10564 u8 reserved_at_10[0x8]; 10565 u8 event_sub_type[0x8]; 10566 10567 u8 reserved_at_20[0xe0]; 10568 10569 union mlx5_ifc_event_auto_bits event_data; 10570 10571 u8 reserved_at_1e0[0x10]; 10572 u8 signature[0x8]; 10573 u8 reserved_at_1f8[0x7]; 10574 u8 owner[0x1]; 10575 }; 10576 10577 enum { 10578 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7, 10579 }; 10580 10581 struct mlx5_ifc_cmd_queue_entry_bits { 10582 u8 type[0x8]; 10583 u8 reserved_at_8[0x18]; 10584 10585 u8 input_length[0x20]; 10586 10587 u8 input_mailbox_pointer_63_32[0x20]; 10588 10589 u8 input_mailbox_pointer_31_9[0x17]; 10590 u8 reserved_at_77[0x9]; 10591 10592 u8 command_input_inline_data[16][0x8]; 10593 10594 u8 command_output_inline_data[16][0x8]; 10595 10596 u8 output_mailbox_pointer_63_32[0x20]; 10597 10598 u8 output_mailbox_pointer_31_9[0x17]; 10599 u8 reserved_at_1b7[0x9]; 10600 10601 u8 output_length[0x20]; 10602 10603 u8 token[0x8]; 10604 u8 signature[0x8]; 10605 u8 reserved_at_1f0[0x8]; 10606 u8 status[0x7]; 10607 u8 ownership[0x1]; 10608 }; 10609 10610 struct mlx5_ifc_cmd_out_bits { 10611 u8 status[0x8]; 10612 u8 reserved_at_8[0x18]; 10613 10614 u8 syndrome[0x20]; 10615 10616 u8 command_output[0x20]; 10617 }; 10618 10619 struct mlx5_ifc_cmd_in_bits { 10620 u8 opcode[0x10]; 10621 u8 reserved_at_10[0x10]; 10622 10623 u8 reserved_at_20[0x10]; 10624 u8 op_mod[0x10]; 10625 10626 u8 command[][0x20]; 10627 }; 10628 10629 struct mlx5_ifc_cmd_if_box_bits { 10630 u8 mailbox_data[512][0x8]; 10631 10632 u8 reserved_at_1000[0x180]; 10633 10634 u8 next_pointer_63_32[0x20]; 10635 10636 u8 next_pointer_31_10[0x16]; 10637 u8 reserved_at_11b6[0xa]; 10638 10639 u8 block_number[0x20]; 10640 10641 u8 reserved_at_11e0[0x8]; 10642 u8 token[0x8]; 10643 u8 ctrl_signature[0x8]; 10644 u8 signature[0x8]; 10645 }; 10646 10647 struct mlx5_ifc_mtt_bits { 10648 u8 ptag_63_32[0x20]; 10649 10650 u8 ptag_31_8[0x18]; 10651 u8 reserved_at_38[0x6]; 10652 u8 wr_en[0x1]; 10653 u8 rd_en[0x1]; 10654 }; 10655 10656 struct mlx5_ifc_query_wol_rol_out_bits { 10657 u8 status[0x8]; 10658 u8 reserved_at_8[0x18]; 10659 10660 u8 syndrome[0x20]; 10661 10662 u8 reserved_at_40[0x10]; 10663 u8 rol_mode[0x8]; 10664 u8 wol_mode[0x8]; 10665 10666 u8 reserved_at_60[0x20]; 10667 }; 10668 10669 struct mlx5_ifc_query_wol_rol_in_bits { 10670 u8 opcode[0x10]; 10671 u8 reserved_at_10[0x10]; 10672 10673 u8 reserved_at_20[0x10]; 10674 u8 op_mod[0x10]; 10675 10676 u8 reserved_at_40[0x40]; 10677 }; 10678 10679 struct mlx5_ifc_set_wol_rol_out_bits { 10680 u8 status[0x8]; 10681 u8 reserved_at_8[0x18]; 10682 10683 u8 syndrome[0x20]; 10684 10685 u8 reserved_at_40[0x40]; 10686 }; 10687 10688 struct mlx5_ifc_set_wol_rol_in_bits { 10689 u8 opcode[0x10]; 10690 u8 reserved_at_10[0x10]; 10691 10692 u8 reserved_at_20[0x10]; 10693 u8 op_mod[0x10]; 10694 10695 u8 rol_mode_valid[0x1]; 10696 u8 wol_mode_valid[0x1]; 10697 u8 reserved_at_42[0xe]; 10698 u8 rol_mode[0x8]; 10699 u8 wol_mode[0x8]; 10700 10701 u8 reserved_at_60[0x20]; 10702 }; 10703 10704 enum { 10705 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0, 10706 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1, 10707 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2, 10708 MLX5_INITIAL_SEG_NIC_INTERFACE_SW_RESET = 0x7, 10709 }; 10710 10711 enum { 10712 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0, 10713 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1, 10714 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2, 10715 }; 10716 10717 enum { 10718 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR = 0x1, 10719 MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC = 0x7, 10720 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR = 0x8, 10721 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR = 0x9, 10722 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR = 0xa, 10723 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR = 0xb, 10724 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN = 0xc, 10725 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR = 0xd, 10726 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV = 0xe, 10727 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR = 0xf, 10728 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR = 0x10, 10729 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PCI_POISONED_ERR = 0x12, 10730 }; 10731 10732 struct mlx5_ifc_initial_seg_bits { 10733 u8 fw_rev_minor[0x10]; 10734 u8 fw_rev_major[0x10]; 10735 10736 u8 cmd_interface_rev[0x10]; 10737 u8 fw_rev_subminor[0x10]; 10738 10739 u8 reserved_at_40[0x40]; 10740 10741 u8 cmdq_phy_addr_63_32[0x20]; 10742 10743 u8 cmdq_phy_addr_31_12[0x14]; 10744 u8 reserved_at_b4[0x2]; 10745 u8 nic_interface[0x2]; 10746 u8 log_cmdq_size[0x4]; 10747 u8 log_cmdq_stride[0x4]; 10748 10749 u8 command_doorbell_vector[0x20]; 10750 10751 u8 reserved_at_e0[0xf00]; 10752 10753 u8 initializing[0x1]; 10754 u8 reserved_at_fe1[0x4]; 10755 u8 nic_interface_supported[0x3]; 10756 u8 embedded_cpu[0x1]; 10757 u8 reserved_at_fe9[0x17]; 10758 10759 struct mlx5_ifc_health_buffer_bits health_buffer; 10760 10761 u8 no_dram_nic_offset[0x20]; 10762 10763 u8 reserved_at_1220[0x6e40]; 10764 10765 u8 reserved_at_8060[0x1f]; 10766 u8 clear_int[0x1]; 10767 10768 u8 health_syndrome[0x8]; 10769 u8 health_counter[0x18]; 10770 10771 u8 reserved_at_80a0[0x17fc0]; 10772 }; 10773 10774 struct mlx5_ifc_mtpps_reg_bits { 10775 u8 reserved_at_0[0xc]; 10776 u8 cap_number_of_pps_pins[0x4]; 10777 u8 reserved_at_10[0x4]; 10778 u8 cap_max_num_of_pps_in_pins[0x4]; 10779 u8 reserved_at_18[0x4]; 10780 u8 cap_max_num_of_pps_out_pins[0x4]; 10781 10782 u8 reserved_at_20[0x13]; 10783 u8 cap_log_min_npps_period[0x5]; 10784 u8 reserved_at_38[0x3]; 10785 u8 cap_log_min_out_pulse_duration_ns[0x5]; 10786 10787 u8 reserved_at_40[0x4]; 10788 u8 cap_pin_3_mode[0x4]; 10789 u8 reserved_at_48[0x4]; 10790 u8 cap_pin_2_mode[0x4]; 10791 u8 reserved_at_50[0x4]; 10792 u8 cap_pin_1_mode[0x4]; 10793 u8 reserved_at_58[0x4]; 10794 u8 cap_pin_0_mode[0x4]; 10795 10796 u8 reserved_at_60[0x4]; 10797 u8 cap_pin_7_mode[0x4]; 10798 u8 reserved_at_68[0x4]; 10799 u8 cap_pin_6_mode[0x4]; 10800 u8 reserved_at_70[0x4]; 10801 u8 cap_pin_5_mode[0x4]; 10802 u8 reserved_at_78[0x4]; 10803 u8 cap_pin_4_mode[0x4]; 10804 10805 u8 field_select[0x20]; 10806 u8 reserved_at_a0[0x20]; 10807 10808 u8 npps_period[0x40]; 10809 10810 u8 enable[0x1]; 10811 u8 reserved_at_101[0xb]; 10812 u8 pattern[0x4]; 10813 u8 reserved_at_110[0x4]; 10814 u8 pin_mode[0x4]; 10815 u8 pin[0x8]; 10816 10817 u8 reserved_at_120[0x2]; 10818 u8 out_pulse_duration_ns[0x1e]; 10819 10820 u8 time_stamp[0x40]; 10821 10822 u8 out_pulse_duration[0x10]; 10823 u8 out_periodic_adjustment[0x10]; 10824 u8 enhanced_out_periodic_adjustment[0x20]; 10825 10826 u8 reserved_at_1c0[0x20]; 10827 }; 10828 10829 struct mlx5_ifc_mtppse_reg_bits { 10830 u8 reserved_at_0[0x18]; 10831 u8 pin[0x8]; 10832 u8 event_arm[0x1]; 10833 u8 reserved_at_21[0x1b]; 10834 u8 event_generation_mode[0x4]; 10835 u8 reserved_at_40[0x40]; 10836 }; 10837 10838 struct mlx5_ifc_mcqs_reg_bits { 10839 u8 last_index_flag[0x1]; 10840 u8 reserved_at_1[0x7]; 10841 u8 fw_device[0x8]; 10842 u8 component_index[0x10]; 10843 10844 u8 reserved_at_20[0x10]; 10845 u8 identifier[0x10]; 10846 10847 u8 reserved_at_40[0x17]; 10848 u8 component_status[0x5]; 10849 u8 component_update_state[0x4]; 10850 10851 u8 last_update_state_changer_type[0x4]; 10852 u8 last_update_state_changer_host_id[0x4]; 10853 u8 reserved_at_68[0x18]; 10854 }; 10855 10856 struct mlx5_ifc_mcqi_cap_bits { 10857 u8 supported_info_bitmask[0x20]; 10858 10859 u8 component_size[0x20]; 10860 10861 u8 max_component_size[0x20]; 10862 10863 u8 log_mcda_word_size[0x4]; 10864 u8 reserved_at_64[0xc]; 10865 u8 mcda_max_write_size[0x10]; 10866 10867 u8 rd_en[0x1]; 10868 u8 reserved_at_81[0x1]; 10869 u8 match_chip_id[0x1]; 10870 u8 match_psid[0x1]; 10871 u8 check_user_timestamp[0x1]; 10872 u8 match_base_guid_mac[0x1]; 10873 u8 reserved_at_86[0x1a]; 10874 }; 10875 10876 struct mlx5_ifc_mcqi_version_bits { 10877 u8 reserved_at_0[0x2]; 10878 u8 build_time_valid[0x1]; 10879 u8 user_defined_time_valid[0x1]; 10880 u8 reserved_at_4[0x14]; 10881 u8 version_string_length[0x8]; 10882 10883 u8 version[0x20]; 10884 10885 u8 build_time[0x40]; 10886 10887 u8 user_defined_time[0x40]; 10888 10889 u8 build_tool_version[0x20]; 10890 10891 u8 reserved_at_e0[0x20]; 10892 10893 u8 version_string[92][0x8]; 10894 }; 10895 10896 struct mlx5_ifc_mcqi_activation_method_bits { 10897 u8 pending_server_ac_power_cycle[0x1]; 10898 u8 pending_server_dc_power_cycle[0x1]; 10899 u8 pending_server_reboot[0x1]; 10900 u8 pending_fw_reset[0x1]; 10901 u8 auto_activate[0x1]; 10902 u8 all_hosts_sync[0x1]; 10903 u8 device_hw_reset[0x1]; 10904 u8 reserved_at_7[0x19]; 10905 }; 10906 10907 union mlx5_ifc_mcqi_reg_data_bits { 10908 struct mlx5_ifc_mcqi_cap_bits mcqi_caps; 10909 struct mlx5_ifc_mcqi_version_bits mcqi_version; 10910 struct mlx5_ifc_mcqi_activation_method_bits mcqi_activation_mathod; 10911 }; 10912 10913 struct mlx5_ifc_mcqi_reg_bits { 10914 u8 read_pending_component[0x1]; 10915 u8 reserved_at_1[0xf]; 10916 u8 component_index[0x10]; 10917 10918 u8 reserved_at_20[0x20]; 10919 10920 u8 reserved_at_40[0x1b]; 10921 u8 info_type[0x5]; 10922 10923 u8 info_size[0x20]; 10924 10925 u8 offset[0x20]; 10926 10927 u8 reserved_at_a0[0x10]; 10928 u8 data_size[0x10]; 10929 10930 union mlx5_ifc_mcqi_reg_data_bits data[]; 10931 }; 10932 10933 struct mlx5_ifc_mcc_reg_bits { 10934 u8 reserved_at_0[0x4]; 10935 u8 time_elapsed_since_last_cmd[0xc]; 10936 u8 reserved_at_10[0x8]; 10937 u8 instruction[0x8]; 10938 10939 u8 reserved_at_20[0x10]; 10940 u8 component_index[0x10]; 10941 10942 u8 reserved_at_40[0x8]; 10943 u8 update_handle[0x18]; 10944 10945 u8 handle_owner_type[0x4]; 10946 u8 handle_owner_host_id[0x4]; 10947 u8 reserved_at_68[0x1]; 10948 u8 control_progress[0x7]; 10949 u8 error_code[0x8]; 10950 u8 reserved_at_78[0x4]; 10951 u8 control_state[0x4]; 10952 10953 u8 component_size[0x20]; 10954 10955 u8 reserved_at_a0[0x60]; 10956 }; 10957 10958 struct mlx5_ifc_mcda_reg_bits { 10959 u8 reserved_at_0[0x8]; 10960 u8 update_handle[0x18]; 10961 10962 u8 offset[0x20]; 10963 10964 u8 reserved_at_40[0x10]; 10965 u8 size[0x10]; 10966 10967 u8 reserved_at_60[0x20]; 10968 10969 u8 data[][0x20]; 10970 }; 10971 10972 enum { 10973 MLX5_MFRL_REG_RESET_STATE_IDLE = 0, 10974 MLX5_MFRL_REG_RESET_STATE_IN_NEGOTIATION = 1, 10975 MLX5_MFRL_REG_RESET_STATE_RESET_IN_PROGRESS = 2, 10976 MLX5_MFRL_REG_RESET_STATE_NEG_TIMEOUT = 3, 10977 MLX5_MFRL_REG_RESET_STATE_NACK = 4, 10978 MLX5_MFRL_REG_RESET_STATE_UNLOAD_TIMEOUT = 5, 10979 }; 10980 10981 enum { 10982 MLX5_MFRL_REG_RESET_TYPE_FULL_CHIP = BIT(0), 10983 MLX5_MFRL_REG_RESET_TYPE_NET_PORT_ALIVE = BIT(1), 10984 }; 10985 10986 enum { 10987 MLX5_MFRL_REG_RESET_LEVEL0 = BIT(0), 10988 MLX5_MFRL_REG_RESET_LEVEL3 = BIT(3), 10989 MLX5_MFRL_REG_RESET_LEVEL6 = BIT(6), 10990 }; 10991 10992 struct mlx5_ifc_mfrl_reg_bits { 10993 u8 reserved_at_0[0x20]; 10994 10995 u8 reserved_at_20[0x2]; 10996 u8 pci_sync_for_fw_update_start[0x1]; 10997 u8 pci_sync_for_fw_update_resp[0x2]; 10998 u8 rst_type_sel[0x3]; 10999 u8 reserved_at_28[0x4]; 11000 u8 reset_state[0x4]; 11001 u8 reset_type[0x8]; 11002 u8 reset_level[0x8]; 11003 }; 11004 11005 struct mlx5_ifc_mirc_reg_bits { 11006 u8 reserved_at_0[0x18]; 11007 u8 status_code[0x8]; 11008 11009 u8 reserved_at_20[0x20]; 11010 }; 11011 11012 struct mlx5_ifc_pddr_monitor_opcode_bits { 11013 u8 reserved_at_0[0x10]; 11014 u8 monitor_opcode[0x10]; 11015 }; 11016 11017 union mlx5_ifc_pddr_troubleshooting_page_status_opcode_auto_bits { 11018 struct mlx5_ifc_pddr_monitor_opcode_bits pddr_monitor_opcode; 11019 u8 reserved_at_0[0x20]; 11020 }; 11021 11022 enum { 11023 /* Monitor opcodes */ 11024 MLX5_PDDR_REG_TRBLSH_GROUP_OPCODE_MONITOR = 0x0, 11025 }; 11026 11027 struct mlx5_ifc_pddr_troubleshooting_page_bits { 11028 u8 reserved_at_0[0x10]; 11029 u8 group_opcode[0x10]; 11030 11031 union mlx5_ifc_pddr_troubleshooting_page_status_opcode_auto_bits status_opcode; 11032 11033 u8 reserved_at_40[0x20]; 11034 11035 u8 status_message[59][0x20]; 11036 }; 11037 11038 union mlx5_ifc_pddr_reg_page_data_auto_bits { 11039 struct mlx5_ifc_pddr_troubleshooting_page_bits pddr_troubleshooting_page; 11040 u8 reserved_at_0[0x7c0]; 11041 }; 11042 11043 enum { 11044 MLX5_PDDR_REG_PAGE_SELECT_TROUBLESHOOTING_INFO_PAGE = 0x1, 11045 }; 11046 11047 struct mlx5_ifc_pddr_reg_bits { 11048 u8 reserved_at_0[0x8]; 11049 u8 local_port[0x8]; 11050 u8 pnat[0x2]; 11051 u8 reserved_at_12[0xe]; 11052 11053 u8 reserved_at_20[0x18]; 11054 u8 page_select[0x8]; 11055 11056 union mlx5_ifc_pddr_reg_page_data_auto_bits page_data; 11057 }; 11058 11059 struct mlx5_ifc_mrtc_reg_bits { 11060 u8 time_synced[0x1]; 11061 u8 reserved_at_1[0x1f]; 11062 11063 u8 reserved_at_20[0x20]; 11064 11065 u8 time_h[0x20]; 11066 11067 u8 time_l[0x20]; 11068 }; 11069 11070 struct mlx5_ifc_mtcap_reg_bits { 11071 u8 reserved_at_0[0x19]; 11072 u8 sensor_count[0x7]; 11073 11074 u8 reserved_at_20[0x20]; 11075 11076 u8 sensor_map[0x40]; 11077 }; 11078 11079 struct mlx5_ifc_mtmp_reg_bits { 11080 u8 reserved_at_0[0x14]; 11081 u8 sensor_index[0xc]; 11082 11083 u8 reserved_at_20[0x10]; 11084 u8 temperature[0x10]; 11085 11086 u8 mte[0x1]; 11087 u8 mtr[0x1]; 11088 u8 reserved_at_42[0xe]; 11089 u8 max_temperature[0x10]; 11090 11091 u8 tee[0x2]; 11092 u8 reserved_at_62[0xe]; 11093 u8 temp_threshold_hi[0x10]; 11094 11095 u8 reserved_at_80[0x10]; 11096 u8 temp_threshold_lo[0x10]; 11097 11098 u8 reserved_at_a0[0x20]; 11099 11100 u8 sensor_name_hi[0x20]; 11101 u8 sensor_name_lo[0x20]; 11102 }; 11103 11104 union mlx5_ifc_ports_control_registers_document_bits { 11105 struct mlx5_ifc_bufferx_reg_bits bufferx_reg; 11106 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 11107 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 11108 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 11109 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 11110 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 11111 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 11112 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout; 11113 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout; 11114 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping; 11115 struct mlx5_ifc_pamp_reg_bits pamp_reg; 11116 struct mlx5_ifc_paos_reg_bits paos_reg; 11117 struct mlx5_ifc_pcap_reg_bits pcap_reg; 11118 struct mlx5_ifc_pddr_monitor_opcode_bits pddr_monitor_opcode; 11119 struct mlx5_ifc_pddr_reg_bits pddr_reg; 11120 struct mlx5_ifc_pddr_troubleshooting_page_bits pddr_troubleshooting_page; 11121 struct mlx5_ifc_peir_reg_bits peir_reg; 11122 struct mlx5_ifc_pelc_reg_bits pelc_reg; 11123 struct mlx5_ifc_pfcc_reg_bits pfcc_reg; 11124 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 11125 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 11126 struct mlx5_ifc_pifr_reg_bits pifr_reg; 11127 struct mlx5_ifc_pipg_reg_bits pipg_reg; 11128 struct mlx5_ifc_plbf_reg_bits plbf_reg; 11129 struct mlx5_ifc_plib_reg_bits plib_reg; 11130 struct mlx5_ifc_plpc_reg_bits plpc_reg; 11131 struct mlx5_ifc_pmaos_reg_bits pmaos_reg; 11132 struct mlx5_ifc_pmlp_reg_bits pmlp_reg; 11133 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg; 11134 struct mlx5_ifc_pmpc_reg_bits pmpc_reg; 11135 struct mlx5_ifc_pmpe_reg_bits pmpe_reg; 11136 struct mlx5_ifc_pmpr_reg_bits pmpr_reg; 11137 struct mlx5_ifc_pmtu_reg_bits pmtu_reg; 11138 struct mlx5_ifc_ppad_reg_bits ppad_reg; 11139 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg; 11140 struct mlx5_ifc_mpein_reg_bits mpein_reg; 11141 struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg; 11142 struct mlx5_ifc_pplm_reg_bits pplm_reg; 11143 struct mlx5_ifc_pplr_reg_bits pplr_reg; 11144 struct mlx5_ifc_ppsc_reg_bits ppsc_reg; 11145 struct mlx5_ifc_pqdr_reg_bits pqdr_reg; 11146 struct mlx5_ifc_pspa_reg_bits pspa_reg; 11147 struct mlx5_ifc_ptas_reg_bits ptas_reg; 11148 struct mlx5_ifc_ptys_reg_bits ptys_reg; 11149 struct mlx5_ifc_mlcr_reg_bits mlcr_reg; 11150 struct mlx5_ifc_pude_reg_bits pude_reg; 11151 struct mlx5_ifc_pvlc_reg_bits pvlc_reg; 11152 struct mlx5_ifc_slrg_reg_bits slrg_reg; 11153 struct mlx5_ifc_sltp_reg_bits sltp_reg; 11154 struct mlx5_ifc_mtpps_reg_bits mtpps_reg; 11155 struct mlx5_ifc_mtppse_reg_bits mtppse_reg; 11156 struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg; 11157 struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits; 11158 struct mlx5_ifc_fpga_cap_bits fpga_cap_bits; 11159 struct mlx5_ifc_mcqi_reg_bits mcqi_reg; 11160 struct mlx5_ifc_mcc_reg_bits mcc_reg; 11161 struct mlx5_ifc_mcda_reg_bits mcda_reg; 11162 struct mlx5_ifc_mirc_reg_bits mirc_reg; 11163 struct mlx5_ifc_mfrl_reg_bits mfrl_reg; 11164 struct mlx5_ifc_mtutc_reg_bits mtutc_reg; 11165 struct mlx5_ifc_mrtc_reg_bits mrtc_reg; 11166 struct mlx5_ifc_mtcap_reg_bits mtcap_reg; 11167 struct mlx5_ifc_mtmp_reg_bits mtmp_reg; 11168 u8 reserved_at_0[0x60e0]; 11169 }; 11170 11171 union mlx5_ifc_debug_enhancements_document_bits { 11172 struct mlx5_ifc_health_buffer_bits health_buffer; 11173 u8 reserved_at_0[0x200]; 11174 }; 11175 11176 union mlx5_ifc_uplink_pci_interface_document_bits { 11177 struct mlx5_ifc_initial_seg_bits initial_seg; 11178 u8 reserved_at_0[0x20060]; 11179 }; 11180 11181 struct mlx5_ifc_set_flow_table_root_out_bits { 11182 u8 status[0x8]; 11183 u8 reserved_at_8[0x18]; 11184 11185 u8 syndrome[0x20]; 11186 11187 u8 reserved_at_40[0x40]; 11188 }; 11189 11190 struct mlx5_ifc_set_flow_table_root_in_bits { 11191 u8 opcode[0x10]; 11192 u8 reserved_at_10[0x10]; 11193 11194 u8 reserved_at_20[0x10]; 11195 u8 op_mod[0x10]; 11196 11197 u8 other_vport[0x1]; 11198 u8 reserved_at_41[0xf]; 11199 u8 vport_number[0x10]; 11200 11201 u8 reserved_at_60[0x20]; 11202 11203 u8 table_type[0x8]; 11204 u8 reserved_at_88[0x7]; 11205 u8 table_of_other_vport[0x1]; 11206 u8 table_vport_number[0x10]; 11207 11208 u8 reserved_at_a0[0x8]; 11209 u8 table_id[0x18]; 11210 11211 u8 reserved_at_c0[0x8]; 11212 u8 underlay_qpn[0x18]; 11213 u8 table_eswitch_owner_vhca_id_valid[0x1]; 11214 u8 reserved_at_e1[0xf]; 11215 u8 table_eswitch_owner_vhca_id[0x10]; 11216 u8 reserved_at_100[0x100]; 11217 }; 11218 11219 enum { 11220 MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = (1UL << 0), 11221 MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15), 11222 }; 11223 11224 struct mlx5_ifc_modify_flow_table_out_bits { 11225 u8 status[0x8]; 11226 u8 reserved_at_8[0x18]; 11227 11228 u8 syndrome[0x20]; 11229 11230 u8 reserved_at_40[0x40]; 11231 }; 11232 11233 struct mlx5_ifc_modify_flow_table_in_bits { 11234 u8 opcode[0x10]; 11235 u8 reserved_at_10[0x10]; 11236 11237 u8 reserved_at_20[0x10]; 11238 u8 op_mod[0x10]; 11239 11240 u8 other_vport[0x1]; 11241 u8 reserved_at_41[0xf]; 11242 u8 vport_number[0x10]; 11243 11244 u8 reserved_at_60[0x10]; 11245 u8 modify_field_select[0x10]; 11246 11247 u8 table_type[0x8]; 11248 u8 reserved_at_88[0x18]; 11249 11250 u8 reserved_at_a0[0x8]; 11251 u8 table_id[0x18]; 11252 11253 struct mlx5_ifc_flow_table_context_bits flow_table_context; 11254 }; 11255 11256 struct mlx5_ifc_ets_tcn_config_reg_bits { 11257 u8 g[0x1]; 11258 u8 b[0x1]; 11259 u8 r[0x1]; 11260 u8 reserved_at_3[0x9]; 11261 u8 group[0x4]; 11262 u8 reserved_at_10[0x9]; 11263 u8 bw_allocation[0x7]; 11264 11265 u8 reserved_at_20[0xc]; 11266 u8 max_bw_units[0x4]; 11267 u8 reserved_at_30[0x8]; 11268 u8 max_bw_value[0x8]; 11269 }; 11270 11271 struct mlx5_ifc_ets_global_config_reg_bits { 11272 u8 reserved_at_0[0x2]; 11273 u8 r[0x1]; 11274 u8 reserved_at_3[0x1d]; 11275 11276 u8 reserved_at_20[0xc]; 11277 u8 max_bw_units[0x4]; 11278 u8 reserved_at_30[0x8]; 11279 u8 max_bw_value[0x8]; 11280 }; 11281 11282 struct mlx5_ifc_qetc_reg_bits { 11283 u8 reserved_at_0[0x8]; 11284 u8 port_number[0x8]; 11285 u8 reserved_at_10[0x30]; 11286 11287 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8]; 11288 struct mlx5_ifc_ets_global_config_reg_bits global_configuration; 11289 }; 11290 11291 struct mlx5_ifc_qpdpm_dscp_reg_bits { 11292 u8 e[0x1]; 11293 u8 reserved_at_01[0x0b]; 11294 u8 prio[0x04]; 11295 }; 11296 11297 struct mlx5_ifc_qpdpm_reg_bits { 11298 u8 reserved_at_0[0x8]; 11299 u8 local_port[0x8]; 11300 u8 reserved_at_10[0x10]; 11301 struct mlx5_ifc_qpdpm_dscp_reg_bits dscp[64]; 11302 }; 11303 11304 struct mlx5_ifc_qpts_reg_bits { 11305 u8 reserved_at_0[0x8]; 11306 u8 local_port[0x8]; 11307 u8 reserved_at_10[0x2d]; 11308 u8 trust_state[0x3]; 11309 }; 11310 11311 struct mlx5_ifc_pptb_reg_bits { 11312 u8 reserved_at_0[0x2]; 11313 u8 mm[0x2]; 11314 u8 reserved_at_4[0x4]; 11315 u8 local_port[0x8]; 11316 u8 reserved_at_10[0x6]; 11317 u8 cm[0x1]; 11318 u8 um[0x1]; 11319 u8 pm[0x8]; 11320 11321 u8 prio_x_buff[0x20]; 11322 11323 u8 pm_msb[0x8]; 11324 u8 reserved_at_48[0x10]; 11325 u8 ctrl_buff[0x4]; 11326 u8 untagged_buff[0x4]; 11327 }; 11328 11329 struct mlx5_ifc_sbcam_reg_bits { 11330 u8 reserved_at_0[0x8]; 11331 u8 feature_group[0x8]; 11332 u8 reserved_at_10[0x8]; 11333 u8 access_reg_group[0x8]; 11334 11335 u8 reserved_at_20[0x20]; 11336 11337 u8 sb_access_reg_cap_mask[4][0x20]; 11338 11339 u8 reserved_at_c0[0x80]; 11340 11341 u8 sb_feature_cap_mask[4][0x20]; 11342 11343 u8 reserved_at_1c0[0x40]; 11344 11345 u8 cap_total_buffer_size[0x20]; 11346 11347 u8 cap_cell_size[0x10]; 11348 u8 cap_max_pg_buffers[0x8]; 11349 u8 cap_num_pool_supported[0x8]; 11350 11351 u8 reserved_at_240[0x8]; 11352 u8 cap_sbsr_stat_size[0x8]; 11353 u8 cap_max_tclass_data[0x8]; 11354 u8 cap_max_cpu_ingress_tclass_sb[0x8]; 11355 }; 11356 11357 struct mlx5_ifc_pbmc_reg_bits { 11358 u8 reserved_at_0[0x8]; 11359 u8 local_port[0x8]; 11360 u8 reserved_at_10[0x10]; 11361 11362 u8 xoff_timer_value[0x10]; 11363 u8 xoff_refresh[0x10]; 11364 11365 u8 reserved_at_40[0x9]; 11366 u8 fullness_threshold[0x7]; 11367 u8 port_buffer_size[0x10]; 11368 11369 struct mlx5_ifc_bufferx_reg_bits buffer[10]; 11370 11371 u8 reserved_at_2e0[0x80]; 11372 }; 11373 11374 struct mlx5_ifc_sbpr_reg_bits { 11375 u8 desc[0x1]; 11376 u8 snap[0x1]; 11377 u8 reserved_at_2[0x4]; 11378 u8 dir[0x2]; 11379 u8 reserved_at_8[0x14]; 11380 u8 pool[0x4]; 11381 11382 u8 infi_size[0x1]; 11383 u8 reserved_at_21[0x7]; 11384 u8 size[0x18]; 11385 11386 u8 reserved_at_40[0x1c]; 11387 u8 mode[0x4]; 11388 11389 u8 reserved_at_60[0x8]; 11390 u8 buff_occupancy[0x18]; 11391 11392 u8 clr[0x1]; 11393 u8 reserved_at_81[0x7]; 11394 u8 max_buff_occupancy[0x18]; 11395 11396 u8 reserved_at_a0[0x8]; 11397 u8 ext_buff_occupancy[0x18]; 11398 }; 11399 11400 struct mlx5_ifc_sbcm_reg_bits { 11401 u8 desc[0x1]; 11402 u8 snap[0x1]; 11403 u8 reserved_at_2[0x6]; 11404 u8 local_port[0x8]; 11405 u8 pnat[0x2]; 11406 u8 pg_buff[0x6]; 11407 u8 reserved_at_18[0x6]; 11408 u8 dir[0x2]; 11409 11410 u8 reserved_at_20[0x1f]; 11411 u8 exc[0x1]; 11412 11413 u8 reserved_at_40[0x40]; 11414 11415 u8 reserved_at_80[0x8]; 11416 u8 buff_occupancy[0x18]; 11417 11418 u8 clr[0x1]; 11419 u8 reserved_at_a1[0x7]; 11420 u8 max_buff_occupancy[0x18]; 11421 11422 u8 reserved_at_c0[0x8]; 11423 u8 min_buff[0x18]; 11424 11425 u8 infi_max[0x1]; 11426 u8 reserved_at_e1[0x7]; 11427 u8 max_buff[0x18]; 11428 11429 u8 reserved_at_100[0x20]; 11430 11431 u8 reserved_at_120[0x1c]; 11432 u8 pool[0x4]; 11433 }; 11434 11435 struct mlx5_ifc_qtct_reg_bits { 11436 u8 reserved_at_0[0x8]; 11437 u8 port_number[0x8]; 11438 u8 reserved_at_10[0xd]; 11439 u8 prio[0x3]; 11440 11441 u8 reserved_at_20[0x1d]; 11442 u8 tclass[0x3]; 11443 }; 11444 11445 struct mlx5_ifc_mcia_reg_bits { 11446 u8 l[0x1]; 11447 u8 reserved_at_1[0x7]; 11448 u8 module[0x8]; 11449 u8 reserved_at_10[0x8]; 11450 u8 status[0x8]; 11451 11452 u8 i2c_device_address[0x8]; 11453 u8 page_number[0x8]; 11454 u8 device_address[0x10]; 11455 11456 u8 reserved_at_40[0x10]; 11457 u8 size[0x10]; 11458 11459 u8 reserved_at_60[0x20]; 11460 11461 u8 dword_0[0x20]; 11462 u8 dword_1[0x20]; 11463 u8 dword_2[0x20]; 11464 u8 dword_3[0x20]; 11465 u8 dword_4[0x20]; 11466 u8 dword_5[0x20]; 11467 u8 dword_6[0x20]; 11468 u8 dword_7[0x20]; 11469 u8 dword_8[0x20]; 11470 u8 dword_9[0x20]; 11471 u8 dword_10[0x20]; 11472 u8 dword_11[0x20]; 11473 }; 11474 11475 struct mlx5_ifc_dcbx_param_bits { 11476 u8 dcbx_cee_cap[0x1]; 11477 u8 dcbx_ieee_cap[0x1]; 11478 u8 dcbx_standby_cap[0x1]; 11479 u8 reserved_at_3[0x5]; 11480 u8 port_number[0x8]; 11481 u8 reserved_at_10[0xa]; 11482 u8 max_application_table_size[6]; 11483 u8 reserved_at_20[0x15]; 11484 u8 version_oper[0x3]; 11485 u8 reserved_at_38[5]; 11486 u8 version_admin[0x3]; 11487 u8 willing_admin[0x1]; 11488 u8 reserved_at_41[0x3]; 11489 u8 pfc_cap_oper[0x4]; 11490 u8 reserved_at_48[0x4]; 11491 u8 pfc_cap_admin[0x4]; 11492 u8 reserved_at_50[0x4]; 11493 u8 num_of_tc_oper[0x4]; 11494 u8 reserved_at_58[0x4]; 11495 u8 num_of_tc_admin[0x4]; 11496 u8 remote_willing[0x1]; 11497 u8 reserved_at_61[3]; 11498 u8 remote_pfc_cap[4]; 11499 u8 reserved_at_68[0x14]; 11500 u8 remote_num_of_tc[0x4]; 11501 u8 reserved_at_80[0x18]; 11502 u8 error[0x8]; 11503 u8 reserved_at_a0[0x160]; 11504 }; 11505 11506 enum { 11507 MLX5_LAG_PORT_SELECT_MODE_QUEUE_AFFINITY = 0, 11508 MLX5_LAG_PORT_SELECT_MODE_PORT_SELECT_FT = 1, 11509 MLX5_LAG_PORT_SELECT_MODE_PORT_SELECT_MPESW = 2, 11510 }; 11511 11512 struct mlx5_ifc_lagc_bits { 11513 u8 fdb_selection_mode[0x1]; 11514 u8 reserved_at_1[0x14]; 11515 u8 port_select_mode[0x3]; 11516 u8 reserved_at_18[0x5]; 11517 u8 lag_state[0x3]; 11518 11519 u8 reserved_at_20[0xc]; 11520 u8 active_port[0x4]; 11521 u8 reserved_at_30[0x4]; 11522 u8 tx_remap_affinity_2[0x4]; 11523 u8 reserved_at_38[0x4]; 11524 u8 tx_remap_affinity_1[0x4]; 11525 }; 11526 11527 struct mlx5_ifc_create_lag_out_bits { 11528 u8 status[0x8]; 11529 u8 reserved_at_8[0x18]; 11530 11531 u8 syndrome[0x20]; 11532 11533 u8 reserved_at_40[0x40]; 11534 }; 11535 11536 struct mlx5_ifc_create_lag_in_bits { 11537 u8 opcode[0x10]; 11538 u8 reserved_at_10[0x10]; 11539 11540 u8 reserved_at_20[0x10]; 11541 u8 op_mod[0x10]; 11542 11543 struct mlx5_ifc_lagc_bits ctx; 11544 }; 11545 11546 struct mlx5_ifc_modify_lag_out_bits { 11547 u8 status[0x8]; 11548 u8 reserved_at_8[0x18]; 11549 11550 u8 syndrome[0x20]; 11551 11552 u8 reserved_at_40[0x40]; 11553 }; 11554 11555 struct mlx5_ifc_modify_lag_in_bits { 11556 u8 opcode[0x10]; 11557 u8 reserved_at_10[0x10]; 11558 11559 u8 reserved_at_20[0x10]; 11560 u8 op_mod[0x10]; 11561 11562 u8 reserved_at_40[0x20]; 11563 u8 field_select[0x20]; 11564 11565 struct mlx5_ifc_lagc_bits ctx; 11566 }; 11567 11568 struct mlx5_ifc_query_lag_out_bits { 11569 u8 status[0x8]; 11570 u8 reserved_at_8[0x18]; 11571 11572 u8 syndrome[0x20]; 11573 11574 struct mlx5_ifc_lagc_bits ctx; 11575 }; 11576 11577 struct mlx5_ifc_query_lag_in_bits { 11578 u8 opcode[0x10]; 11579 u8 reserved_at_10[0x10]; 11580 11581 u8 reserved_at_20[0x10]; 11582 u8 op_mod[0x10]; 11583 11584 u8 reserved_at_40[0x40]; 11585 }; 11586 11587 struct mlx5_ifc_destroy_lag_out_bits { 11588 u8 status[0x8]; 11589 u8 reserved_at_8[0x18]; 11590 11591 u8 syndrome[0x20]; 11592 11593 u8 reserved_at_40[0x40]; 11594 }; 11595 11596 struct mlx5_ifc_destroy_lag_in_bits { 11597 u8 opcode[0x10]; 11598 u8 reserved_at_10[0x10]; 11599 11600 u8 reserved_at_20[0x10]; 11601 u8 op_mod[0x10]; 11602 11603 u8 reserved_at_40[0x40]; 11604 }; 11605 11606 struct mlx5_ifc_create_vport_lag_out_bits { 11607 u8 status[0x8]; 11608 u8 reserved_at_8[0x18]; 11609 11610 u8 syndrome[0x20]; 11611 11612 u8 reserved_at_40[0x40]; 11613 }; 11614 11615 struct mlx5_ifc_create_vport_lag_in_bits { 11616 u8 opcode[0x10]; 11617 u8 reserved_at_10[0x10]; 11618 11619 u8 reserved_at_20[0x10]; 11620 u8 op_mod[0x10]; 11621 11622 u8 reserved_at_40[0x40]; 11623 }; 11624 11625 struct mlx5_ifc_destroy_vport_lag_out_bits { 11626 u8 status[0x8]; 11627 u8 reserved_at_8[0x18]; 11628 11629 u8 syndrome[0x20]; 11630 11631 u8 reserved_at_40[0x40]; 11632 }; 11633 11634 struct mlx5_ifc_destroy_vport_lag_in_bits { 11635 u8 opcode[0x10]; 11636 u8 reserved_at_10[0x10]; 11637 11638 u8 reserved_at_20[0x10]; 11639 u8 op_mod[0x10]; 11640 11641 u8 reserved_at_40[0x40]; 11642 }; 11643 11644 enum { 11645 MLX5_MODIFY_MEMIC_OP_MOD_ALLOC, 11646 MLX5_MODIFY_MEMIC_OP_MOD_DEALLOC, 11647 }; 11648 11649 struct mlx5_ifc_modify_memic_in_bits { 11650 u8 opcode[0x10]; 11651 u8 uid[0x10]; 11652 11653 u8 reserved_at_20[0x10]; 11654 u8 op_mod[0x10]; 11655 11656 u8 reserved_at_40[0x20]; 11657 11658 u8 reserved_at_60[0x18]; 11659 u8 memic_operation_type[0x8]; 11660 11661 u8 memic_start_addr[0x40]; 11662 11663 u8 reserved_at_c0[0x140]; 11664 }; 11665 11666 struct mlx5_ifc_modify_memic_out_bits { 11667 u8 status[0x8]; 11668 u8 reserved_at_8[0x18]; 11669 11670 u8 syndrome[0x20]; 11671 11672 u8 reserved_at_40[0x40]; 11673 11674 u8 memic_operation_addr[0x40]; 11675 11676 u8 reserved_at_c0[0x140]; 11677 }; 11678 11679 struct mlx5_ifc_alloc_memic_in_bits { 11680 u8 opcode[0x10]; 11681 u8 reserved_at_10[0x10]; 11682 11683 u8 reserved_at_20[0x10]; 11684 u8 op_mod[0x10]; 11685 11686 u8 reserved_at_30[0x20]; 11687 11688 u8 reserved_at_40[0x18]; 11689 u8 log_memic_addr_alignment[0x8]; 11690 11691 u8 range_start_addr[0x40]; 11692 11693 u8 range_size[0x20]; 11694 11695 u8 memic_size[0x20]; 11696 }; 11697 11698 struct mlx5_ifc_alloc_memic_out_bits { 11699 u8 status[0x8]; 11700 u8 reserved_at_8[0x18]; 11701 11702 u8 syndrome[0x20]; 11703 11704 u8 memic_start_addr[0x40]; 11705 }; 11706 11707 struct mlx5_ifc_dealloc_memic_in_bits { 11708 u8 opcode[0x10]; 11709 u8 reserved_at_10[0x10]; 11710 11711 u8 reserved_at_20[0x10]; 11712 u8 op_mod[0x10]; 11713 11714 u8 reserved_at_40[0x40]; 11715 11716 u8 memic_start_addr[0x40]; 11717 11718 u8 memic_size[0x20]; 11719 11720 u8 reserved_at_e0[0x20]; 11721 }; 11722 11723 struct mlx5_ifc_dealloc_memic_out_bits { 11724 u8 status[0x8]; 11725 u8 reserved_at_8[0x18]; 11726 11727 u8 syndrome[0x20]; 11728 11729 u8 reserved_at_40[0x40]; 11730 }; 11731 11732 struct mlx5_ifc_umem_bits { 11733 u8 reserved_at_0[0x80]; 11734 11735 u8 ats[0x1]; 11736 u8 reserved_at_81[0x1a]; 11737 u8 log_page_size[0x5]; 11738 11739 u8 page_offset[0x20]; 11740 11741 u8 num_of_mtt[0x40]; 11742 11743 struct mlx5_ifc_mtt_bits mtt[]; 11744 }; 11745 11746 struct mlx5_ifc_uctx_bits { 11747 u8 cap[0x20]; 11748 11749 u8 reserved_at_20[0x160]; 11750 }; 11751 11752 struct mlx5_ifc_sw_icm_bits { 11753 u8 modify_field_select[0x40]; 11754 11755 u8 reserved_at_40[0x18]; 11756 u8 log_sw_icm_size[0x8]; 11757 11758 u8 reserved_at_60[0x20]; 11759 11760 u8 sw_icm_start_addr[0x40]; 11761 11762 u8 reserved_at_c0[0x140]; 11763 }; 11764 11765 struct mlx5_ifc_geneve_tlv_option_bits { 11766 u8 modify_field_select[0x40]; 11767 11768 u8 reserved_at_40[0x18]; 11769 u8 geneve_option_fte_index[0x8]; 11770 11771 u8 option_class[0x10]; 11772 u8 option_type[0x8]; 11773 u8 reserved_at_78[0x3]; 11774 u8 option_data_length[0x5]; 11775 11776 u8 reserved_at_80[0x180]; 11777 }; 11778 11779 struct mlx5_ifc_create_umem_in_bits { 11780 u8 opcode[0x10]; 11781 u8 uid[0x10]; 11782 11783 u8 reserved_at_20[0x10]; 11784 u8 op_mod[0x10]; 11785 11786 u8 reserved_at_40[0x40]; 11787 11788 struct mlx5_ifc_umem_bits umem; 11789 }; 11790 11791 struct mlx5_ifc_create_umem_out_bits { 11792 u8 status[0x8]; 11793 u8 reserved_at_8[0x18]; 11794 11795 u8 syndrome[0x20]; 11796 11797 u8 reserved_at_40[0x8]; 11798 u8 umem_id[0x18]; 11799 11800 u8 reserved_at_60[0x20]; 11801 }; 11802 11803 struct mlx5_ifc_destroy_umem_in_bits { 11804 u8 opcode[0x10]; 11805 u8 uid[0x10]; 11806 11807 u8 reserved_at_20[0x10]; 11808 u8 op_mod[0x10]; 11809 11810 u8 reserved_at_40[0x8]; 11811 u8 umem_id[0x18]; 11812 11813 u8 reserved_at_60[0x20]; 11814 }; 11815 11816 struct mlx5_ifc_destroy_umem_out_bits { 11817 u8 status[0x8]; 11818 u8 reserved_at_8[0x18]; 11819 11820 u8 syndrome[0x20]; 11821 11822 u8 reserved_at_40[0x40]; 11823 }; 11824 11825 struct mlx5_ifc_create_uctx_in_bits { 11826 u8 opcode[0x10]; 11827 u8 reserved_at_10[0x10]; 11828 11829 u8 reserved_at_20[0x10]; 11830 u8 op_mod[0x10]; 11831 11832 u8 reserved_at_40[0x40]; 11833 11834 struct mlx5_ifc_uctx_bits uctx; 11835 }; 11836 11837 struct mlx5_ifc_create_uctx_out_bits { 11838 u8 status[0x8]; 11839 u8 reserved_at_8[0x18]; 11840 11841 u8 syndrome[0x20]; 11842 11843 u8 reserved_at_40[0x10]; 11844 u8 uid[0x10]; 11845 11846 u8 reserved_at_60[0x20]; 11847 }; 11848 11849 struct mlx5_ifc_destroy_uctx_in_bits { 11850 u8 opcode[0x10]; 11851 u8 reserved_at_10[0x10]; 11852 11853 u8 reserved_at_20[0x10]; 11854 u8 op_mod[0x10]; 11855 11856 u8 reserved_at_40[0x10]; 11857 u8 uid[0x10]; 11858 11859 u8 reserved_at_60[0x20]; 11860 }; 11861 11862 struct mlx5_ifc_destroy_uctx_out_bits { 11863 u8 status[0x8]; 11864 u8 reserved_at_8[0x18]; 11865 11866 u8 syndrome[0x20]; 11867 11868 u8 reserved_at_40[0x40]; 11869 }; 11870 11871 struct mlx5_ifc_create_sw_icm_in_bits { 11872 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 11873 struct mlx5_ifc_sw_icm_bits sw_icm; 11874 }; 11875 11876 struct mlx5_ifc_create_geneve_tlv_option_in_bits { 11877 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 11878 struct mlx5_ifc_geneve_tlv_option_bits geneve_tlv_opt; 11879 }; 11880 11881 struct mlx5_ifc_mtrc_string_db_param_bits { 11882 u8 string_db_base_address[0x20]; 11883 11884 u8 reserved_at_20[0x8]; 11885 u8 string_db_size[0x18]; 11886 }; 11887 11888 struct mlx5_ifc_mtrc_cap_bits { 11889 u8 trace_owner[0x1]; 11890 u8 trace_to_memory[0x1]; 11891 u8 reserved_at_2[0x4]; 11892 u8 trc_ver[0x2]; 11893 u8 reserved_at_8[0x14]; 11894 u8 num_string_db[0x4]; 11895 11896 u8 first_string_trace[0x8]; 11897 u8 num_string_trace[0x8]; 11898 u8 reserved_at_30[0x28]; 11899 11900 u8 log_max_trace_buffer_size[0x8]; 11901 11902 u8 reserved_at_60[0x20]; 11903 11904 struct mlx5_ifc_mtrc_string_db_param_bits string_db_param[8]; 11905 11906 u8 reserved_at_280[0x180]; 11907 }; 11908 11909 struct mlx5_ifc_mtrc_conf_bits { 11910 u8 reserved_at_0[0x1c]; 11911 u8 trace_mode[0x4]; 11912 u8 reserved_at_20[0x18]; 11913 u8 log_trace_buffer_size[0x8]; 11914 u8 trace_mkey[0x20]; 11915 u8 reserved_at_60[0x3a0]; 11916 }; 11917 11918 struct mlx5_ifc_mtrc_stdb_bits { 11919 u8 string_db_index[0x4]; 11920 u8 reserved_at_4[0x4]; 11921 u8 read_size[0x18]; 11922 u8 start_offset[0x20]; 11923 u8 string_db_data[]; 11924 }; 11925 11926 struct mlx5_ifc_mtrc_ctrl_bits { 11927 u8 trace_status[0x2]; 11928 u8 reserved_at_2[0x2]; 11929 u8 arm_event[0x1]; 11930 u8 reserved_at_5[0xb]; 11931 u8 modify_field_select[0x10]; 11932 u8 reserved_at_20[0x2b]; 11933 u8 current_timestamp52_32[0x15]; 11934 u8 current_timestamp31_0[0x20]; 11935 u8 reserved_at_80[0x180]; 11936 }; 11937 11938 struct mlx5_ifc_host_params_context_bits { 11939 u8 host_number[0x8]; 11940 u8 reserved_at_8[0x7]; 11941 u8 host_pf_disabled[0x1]; 11942 u8 host_num_of_vfs[0x10]; 11943 11944 u8 host_total_vfs[0x10]; 11945 u8 host_pci_bus[0x10]; 11946 11947 u8 reserved_at_40[0x10]; 11948 u8 host_pci_device[0x10]; 11949 11950 u8 reserved_at_60[0x10]; 11951 u8 host_pci_function[0x10]; 11952 11953 u8 reserved_at_80[0x180]; 11954 }; 11955 11956 struct mlx5_ifc_query_esw_functions_in_bits { 11957 u8 opcode[0x10]; 11958 u8 reserved_at_10[0x10]; 11959 11960 u8 reserved_at_20[0x10]; 11961 u8 op_mod[0x10]; 11962 11963 u8 reserved_at_40[0x40]; 11964 }; 11965 11966 struct mlx5_ifc_query_esw_functions_out_bits { 11967 u8 status[0x8]; 11968 u8 reserved_at_8[0x18]; 11969 11970 u8 syndrome[0x20]; 11971 11972 u8 reserved_at_40[0x40]; 11973 11974 struct mlx5_ifc_host_params_context_bits host_params_context; 11975 11976 u8 reserved_at_280[0x180]; 11977 u8 host_sf_enable[][0x40]; 11978 }; 11979 11980 struct mlx5_ifc_sf_partition_bits { 11981 u8 reserved_at_0[0x10]; 11982 u8 log_num_sf[0x8]; 11983 u8 log_sf_bar_size[0x8]; 11984 }; 11985 11986 struct mlx5_ifc_query_sf_partitions_out_bits { 11987 u8 status[0x8]; 11988 u8 reserved_at_8[0x18]; 11989 11990 u8 syndrome[0x20]; 11991 11992 u8 reserved_at_40[0x18]; 11993 u8 num_sf_partitions[0x8]; 11994 11995 u8 reserved_at_60[0x20]; 11996 11997 struct mlx5_ifc_sf_partition_bits sf_partition[]; 11998 }; 11999 12000 struct mlx5_ifc_query_sf_partitions_in_bits { 12001 u8 opcode[0x10]; 12002 u8 reserved_at_10[0x10]; 12003 12004 u8 reserved_at_20[0x10]; 12005 u8 op_mod[0x10]; 12006 12007 u8 reserved_at_40[0x40]; 12008 }; 12009 12010 struct mlx5_ifc_dealloc_sf_out_bits { 12011 u8 status[0x8]; 12012 u8 reserved_at_8[0x18]; 12013 12014 u8 syndrome[0x20]; 12015 12016 u8 reserved_at_40[0x40]; 12017 }; 12018 12019 struct mlx5_ifc_dealloc_sf_in_bits { 12020 u8 opcode[0x10]; 12021 u8 reserved_at_10[0x10]; 12022 12023 u8 reserved_at_20[0x10]; 12024 u8 op_mod[0x10]; 12025 12026 u8 reserved_at_40[0x10]; 12027 u8 function_id[0x10]; 12028 12029 u8 reserved_at_60[0x20]; 12030 }; 12031 12032 struct mlx5_ifc_alloc_sf_out_bits { 12033 u8 status[0x8]; 12034 u8 reserved_at_8[0x18]; 12035 12036 u8 syndrome[0x20]; 12037 12038 u8 reserved_at_40[0x40]; 12039 }; 12040 12041 struct mlx5_ifc_alloc_sf_in_bits { 12042 u8 opcode[0x10]; 12043 u8 reserved_at_10[0x10]; 12044 12045 u8 reserved_at_20[0x10]; 12046 u8 op_mod[0x10]; 12047 12048 u8 reserved_at_40[0x10]; 12049 u8 function_id[0x10]; 12050 12051 u8 reserved_at_60[0x20]; 12052 }; 12053 12054 struct mlx5_ifc_affiliated_event_header_bits { 12055 u8 reserved_at_0[0x10]; 12056 u8 obj_type[0x10]; 12057 12058 u8 obj_id[0x20]; 12059 }; 12060 12061 enum { 12062 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = BIT_ULL(0xc), 12063 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_IPSEC = BIT_ULL(0x13), 12064 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_SAMPLER = BIT_ULL(0x20), 12065 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_FLOW_METER_ASO = BIT_ULL(0x24), 12066 }; 12067 12068 enum { 12069 MLX5_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = 0xc, 12070 MLX5_GENERAL_OBJECT_TYPES_IPSEC = 0x13, 12071 MLX5_GENERAL_OBJECT_TYPES_SAMPLER = 0x20, 12072 MLX5_GENERAL_OBJECT_TYPES_FLOW_METER_ASO = 0x24, 12073 MLX5_GENERAL_OBJECT_TYPES_MACSEC = 0x27, 12074 MLX5_GENERAL_OBJECT_TYPES_INT_KEK = 0x47, 12075 MLX5_GENERAL_OBJECT_TYPES_FLOW_TABLE_ALIAS = 0xff15, 12076 }; 12077 12078 enum { 12079 MLX5_IPSEC_OBJECT_ICV_LEN_16B, 12080 }; 12081 12082 enum { 12083 MLX5_IPSEC_ASO_REG_C_0_1 = 0x0, 12084 MLX5_IPSEC_ASO_REG_C_2_3 = 0x1, 12085 MLX5_IPSEC_ASO_REG_C_4_5 = 0x2, 12086 MLX5_IPSEC_ASO_REG_C_6_7 = 0x3, 12087 }; 12088 12089 enum { 12090 MLX5_IPSEC_ASO_MODE = 0x0, 12091 MLX5_IPSEC_ASO_REPLAY_PROTECTION = 0x1, 12092 MLX5_IPSEC_ASO_INC_SN = 0x2, 12093 }; 12094 12095 enum { 12096 MLX5_IPSEC_ASO_REPLAY_WIN_32BIT = 0x0, 12097 MLX5_IPSEC_ASO_REPLAY_WIN_64BIT = 0x1, 12098 MLX5_IPSEC_ASO_REPLAY_WIN_128BIT = 0x2, 12099 MLX5_IPSEC_ASO_REPLAY_WIN_256BIT = 0x3, 12100 }; 12101 12102 struct mlx5_ifc_ipsec_aso_bits { 12103 u8 valid[0x1]; 12104 u8 reserved_at_201[0x1]; 12105 u8 mode[0x2]; 12106 u8 window_sz[0x2]; 12107 u8 soft_lft_arm[0x1]; 12108 u8 hard_lft_arm[0x1]; 12109 u8 remove_flow_enable[0x1]; 12110 u8 esn_event_arm[0x1]; 12111 u8 reserved_at_20a[0x16]; 12112 12113 u8 remove_flow_pkt_cnt[0x20]; 12114 12115 u8 remove_flow_soft_lft[0x20]; 12116 12117 u8 reserved_at_260[0x80]; 12118 12119 u8 mode_parameter[0x20]; 12120 12121 u8 replay_protection_window[0x100]; 12122 }; 12123 12124 struct mlx5_ifc_ipsec_obj_bits { 12125 u8 modify_field_select[0x40]; 12126 u8 full_offload[0x1]; 12127 u8 reserved_at_41[0x1]; 12128 u8 esn_en[0x1]; 12129 u8 esn_overlap[0x1]; 12130 u8 reserved_at_44[0x2]; 12131 u8 icv_length[0x2]; 12132 u8 reserved_at_48[0x4]; 12133 u8 aso_return_reg[0x4]; 12134 u8 reserved_at_50[0x10]; 12135 12136 u8 esn_msb[0x20]; 12137 12138 u8 reserved_at_80[0x8]; 12139 u8 dekn[0x18]; 12140 12141 u8 salt[0x20]; 12142 12143 u8 implicit_iv[0x40]; 12144 12145 u8 reserved_at_100[0x8]; 12146 u8 ipsec_aso_access_pd[0x18]; 12147 u8 reserved_at_120[0xe0]; 12148 12149 struct mlx5_ifc_ipsec_aso_bits ipsec_aso; 12150 }; 12151 12152 struct mlx5_ifc_create_ipsec_obj_in_bits { 12153 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12154 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 12155 }; 12156 12157 enum { 12158 MLX5_MODIFY_IPSEC_BITMASK_ESN_OVERLAP = BIT(0), 12159 MLX5_MODIFY_IPSEC_BITMASK_ESN_MSB = BIT(1), 12160 }; 12161 12162 struct mlx5_ifc_query_ipsec_obj_out_bits { 12163 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 12164 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 12165 }; 12166 12167 struct mlx5_ifc_modify_ipsec_obj_in_bits { 12168 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12169 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 12170 }; 12171 12172 enum { 12173 MLX5_MACSEC_ASO_REPLAY_PROTECTION = 0x1, 12174 }; 12175 12176 enum { 12177 MLX5_MACSEC_ASO_REPLAY_WIN_32BIT = 0x0, 12178 MLX5_MACSEC_ASO_REPLAY_WIN_64BIT = 0x1, 12179 MLX5_MACSEC_ASO_REPLAY_WIN_128BIT = 0x2, 12180 MLX5_MACSEC_ASO_REPLAY_WIN_256BIT = 0x3, 12181 }; 12182 12183 #define MLX5_MACSEC_ASO_INC_SN 0x2 12184 #define MLX5_MACSEC_ASO_REG_C_4_5 0x2 12185 12186 struct mlx5_ifc_macsec_aso_bits { 12187 u8 valid[0x1]; 12188 u8 reserved_at_1[0x1]; 12189 u8 mode[0x2]; 12190 u8 window_size[0x2]; 12191 u8 soft_lifetime_arm[0x1]; 12192 u8 hard_lifetime_arm[0x1]; 12193 u8 remove_flow_enable[0x1]; 12194 u8 epn_event_arm[0x1]; 12195 u8 reserved_at_a[0x16]; 12196 12197 u8 remove_flow_packet_count[0x20]; 12198 12199 u8 remove_flow_soft_lifetime[0x20]; 12200 12201 u8 reserved_at_60[0x80]; 12202 12203 u8 mode_parameter[0x20]; 12204 12205 u8 replay_protection_window[8][0x20]; 12206 }; 12207 12208 struct mlx5_ifc_macsec_offload_obj_bits { 12209 u8 modify_field_select[0x40]; 12210 12211 u8 confidentiality_en[0x1]; 12212 u8 reserved_at_41[0x1]; 12213 u8 epn_en[0x1]; 12214 u8 epn_overlap[0x1]; 12215 u8 reserved_at_44[0x2]; 12216 u8 confidentiality_offset[0x2]; 12217 u8 reserved_at_48[0x4]; 12218 u8 aso_return_reg[0x4]; 12219 u8 reserved_at_50[0x10]; 12220 12221 u8 epn_msb[0x20]; 12222 12223 u8 reserved_at_80[0x8]; 12224 u8 dekn[0x18]; 12225 12226 u8 reserved_at_a0[0x20]; 12227 12228 u8 sci[0x40]; 12229 12230 u8 reserved_at_100[0x8]; 12231 u8 macsec_aso_access_pd[0x18]; 12232 12233 u8 reserved_at_120[0x60]; 12234 12235 u8 salt[3][0x20]; 12236 12237 u8 reserved_at_1e0[0x20]; 12238 12239 struct mlx5_ifc_macsec_aso_bits macsec_aso; 12240 }; 12241 12242 struct mlx5_ifc_create_macsec_obj_in_bits { 12243 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12244 struct mlx5_ifc_macsec_offload_obj_bits macsec_object; 12245 }; 12246 12247 struct mlx5_ifc_modify_macsec_obj_in_bits { 12248 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12249 struct mlx5_ifc_macsec_offload_obj_bits macsec_object; 12250 }; 12251 12252 enum { 12253 MLX5_MODIFY_MACSEC_BITMASK_EPN_OVERLAP = BIT(0), 12254 MLX5_MODIFY_MACSEC_BITMASK_EPN_MSB = BIT(1), 12255 }; 12256 12257 struct mlx5_ifc_query_macsec_obj_out_bits { 12258 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 12259 struct mlx5_ifc_macsec_offload_obj_bits macsec_object; 12260 }; 12261 12262 struct mlx5_ifc_wrapped_dek_bits { 12263 u8 gcm_iv[0x60]; 12264 12265 u8 reserved_at_60[0x20]; 12266 12267 u8 const0[0x1]; 12268 u8 key_size[0x1]; 12269 u8 reserved_at_82[0x2]; 12270 u8 key2_invalid[0x1]; 12271 u8 reserved_at_85[0x3]; 12272 u8 pd[0x18]; 12273 12274 u8 key_purpose[0x5]; 12275 u8 reserved_at_a5[0x13]; 12276 u8 kek_id[0x8]; 12277 12278 u8 reserved_at_c0[0x40]; 12279 12280 u8 key1[0x8][0x20]; 12281 12282 u8 key2[0x8][0x20]; 12283 12284 u8 reserved_at_300[0x40]; 12285 12286 u8 const1[0x1]; 12287 u8 reserved_at_341[0x1f]; 12288 12289 u8 reserved_at_360[0x20]; 12290 12291 u8 auth_tag[0x80]; 12292 }; 12293 12294 struct mlx5_ifc_encryption_key_obj_bits { 12295 u8 modify_field_select[0x40]; 12296 12297 u8 state[0x8]; 12298 u8 sw_wrapped[0x1]; 12299 u8 reserved_at_49[0xb]; 12300 u8 key_size[0x4]; 12301 u8 reserved_at_58[0x4]; 12302 u8 key_purpose[0x4]; 12303 12304 u8 reserved_at_60[0x8]; 12305 u8 pd[0x18]; 12306 12307 u8 reserved_at_80[0x100]; 12308 12309 u8 opaque[0x40]; 12310 12311 u8 reserved_at_1c0[0x40]; 12312 12313 u8 key[8][0x80]; 12314 12315 u8 sw_wrapped_dek[8][0x80]; 12316 12317 u8 reserved_at_a00[0x600]; 12318 }; 12319 12320 struct mlx5_ifc_create_encryption_key_in_bits { 12321 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12322 struct mlx5_ifc_encryption_key_obj_bits encryption_key_object; 12323 }; 12324 12325 struct mlx5_ifc_modify_encryption_key_in_bits { 12326 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12327 struct mlx5_ifc_encryption_key_obj_bits encryption_key_object; 12328 }; 12329 12330 enum { 12331 MLX5_FLOW_METER_MODE_BYTES_IP_LENGTH = 0x0, 12332 MLX5_FLOW_METER_MODE_BYTES_CALC_WITH_L2 = 0x1, 12333 MLX5_FLOW_METER_MODE_BYTES_CALC_WITH_L2_IPG = 0x2, 12334 MLX5_FLOW_METER_MODE_NUM_PACKETS = 0x3, 12335 }; 12336 12337 struct mlx5_ifc_flow_meter_parameters_bits { 12338 u8 valid[0x1]; 12339 u8 bucket_overflow[0x1]; 12340 u8 start_color[0x2]; 12341 u8 both_buckets_on_green[0x1]; 12342 u8 reserved_at_5[0x1]; 12343 u8 meter_mode[0x2]; 12344 u8 reserved_at_8[0x18]; 12345 12346 u8 reserved_at_20[0x20]; 12347 12348 u8 reserved_at_40[0x3]; 12349 u8 cbs_exponent[0x5]; 12350 u8 cbs_mantissa[0x8]; 12351 u8 reserved_at_50[0x3]; 12352 u8 cir_exponent[0x5]; 12353 u8 cir_mantissa[0x8]; 12354 12355 u8 reserved_at_60[0x20]; 12356 12357 u8 reserved_at_80[0x3]; 12358 u8 ebs_exponent[0x5]; 12359 u8 ebs_mantissa[0x8]; 12360 u8 reserved_at_90[0x3]; 12361 u8 eir_exponent[0x5]; 12362 u8 eir_mantissa[0x8]; 12363 12364 u8 reserved_at_a0[0x60]; 12365 }; 12366 12367 struct mlx5_ifc_flow_meter_aso_obj_bits { 12368 u8 modify_field_select[0x40]; 12369 12370 u8 reserved_at_40[0x40]; 12371 12372 u8 reserved_at_80[0x8]; 12373 u8 meter_aso_access_pd[0x18]; 12374 12375 u8 reserved_at_a0[0x160]; 12376 12377 struct mlx5_ifc_flow_meter_parameters_bits flow_meter_parameters[2]; 12378 }; 12379 12380 struct mlx5_ifc_create_flow_meter_aso_obj_in_bits { 12381 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 12382 struct mlx5_ifc_flow_meter_aso_obj_bits flow_meter_aso_obj; 12383 }; 12384 12385 struct mlx5_ifc_int_kek_obj_bits { 12386 u8 modify_field_select[0x40]; 12387 12388 u8 state[0x8]; 12389 u8 auto_gen[0x1]; 12390 u8 reserved_at_49[0xb]; 12391 u8 key_size[0x4]; 12392 u8 reserved_at_58[0x8]; 12393 12394 u8 reserved_at_60[0x8]; 12395 u8 pd[0x18]; 12396 12397 u8 reserved_at_80[0x180]; 12398 u8 key[8][0x80]; 12399 12400 u8 reserved_at_600[0x200]; 12401 }; 12402 12403 struct mlx5_ifc_create_int_kek_obj_in_bits { 12404 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12405 struct mlx5_ifc_int_kek_obj_bits int_kek_object; 12406 }; 12407 12408 struct mlx5_ifc_create_int_kek_obj_out_bits { 12409 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 12410 struct mlx5_ifc_int_kek_obj_bits int_kek_object; 12411 }; 12412 12413 struct mlx5_ifc_sampler_obj_bits { 12414 u8 modify_field_select[0x40]; 12415 12416 u8 table_type[0x8]; 12417 u8 level[0x8]; 12418 u8 reserved_at_50[0xf]; 12419 u8 ignore_flow_level[0x1]; 12420 12421 u8 sample_ratio[0x20]; 12422 12423 u8 reserved_at_80[0x8]; 12424 u8 sample_table_id[0x18]; 12425 12426 u8 reserved_at_a0[0x8]; 12427 u8 default_table_id[0x18]; 12428 12429 u8 sw_steering_icm_address_rx[0x40]; 12430 u8 sw_steering_icm_address_tx[0x40]; 12431 12432 u8 reserved_at_140[0xa0]; 12433 }; 12434 12435 struct mlx5_ifc_create_sampler_obj_in_bits { 12436 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12437 struct mlx5_ifc_sampler_obj_bits sampler_object; 12438 }; 12439 12440 struct mlx5_ifc_query_sampler_obj_out_bits { 12441 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 12442 struct mlx5_ifc_sampler_obj_bits sampler_object; 12443 }; 12444 12445 enum { 12446 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_128 = 0x0, 12447 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_256 = 0x1, 12448 }; 12449 12450 enum { 12451 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_PURPOSE_TLS = 0x1, 12452 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_PURPOSE_IPSEC = 0x2, 12453 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_PURPOSE_MACSEC = 0x4, 12454 }; 12455 12456 struct mlx5_ifc_tls_static_params_bits { 12457 u8 const_2[0x2]; 12458 u8 tls_version[0x4]; 12459 u8 const_1[0x2]; 12460 u8 reserved_at_8[0x14]; 12461 u8 encryption_standard[0x4]; 12462 12463 u8 reserved_at_20[0x20]; 12464 12465 u8 initial_record_number[0x40]; 12466 12467 u8 resync_tcp_sn[0x20]; 12468 12469 u8 gcm_iv[0x20]; 12470 12471 u8 implicit_iv[0x40]; 12472 12473 u8 reserved_at_100[0x8]; 12474 u8 dek_index[0x18]; 12475 12476 u8 reserved_at_120[0xe0]; 12477 }; 12478 12479 struct mlx5_ifc_tls_progress_params_bits { 12480 u8 next_record_tcp_sn[0x20]; 12481 12482 u8 hw_resync_tcp_sn[0x20]; 12483 12484 u8 record_tracker_state[0x2]; 12485 u8 auth_state[0x2]; 12486 u8 reserved_at_44[0x4]; 12487 u8 hw_offset_record_number[0x18]; 12488 }; 12489 12490 enum { 12491 MLX5_MTT_PERM_READ = 1 << 0, 12492 MLX5_MTT_PERM_WRITE = 1 << 1, 12493 MLX5_MTT_PERM_RW = MLX5_MTT_PERM_READ | MLX5_MTT_PERM_WRITE, 12494 }; 12495 12496 enum { 12497 MLX5_SUSPEND_VHCA_IN_OP_MOD_SUSPEND_INITIATOR = 0x0, 12498 MLX5_SUSPEND_VHCA_IN_OP_MOD_SUSPEND_RESPONDER = 0x1, 12499 }; 12500 12501 struct mlx5_ifc_suspend_vhca_in_bits { 12502 u8 opcode[0x10]; 12503 u8 uid[0x10]; 12504 12505 u8 reserved_at_20[0x10]; 12506 u8 op_mod[0x10]; 12507 12508 u8 reserved_at_40[0x10]; 12509 u8 vhca_id[0x10]; 12510 12511 u8 reserved_at_60[0x20]; 12512 }; 12513 12514 struct mlx5_ifc_suspend_vhca_out_bits { 12515 u8 status[0x8]; 12516 u8 reserved_at_8[0x18]; 12517 12518 u8 syndrome[0x20]; 12519 12520 u8 reserved_at_40[0x40]; 12521 }; 12522 12523 enum { 12524 MLX5_RESUME_VHCA_IN_OP_MOD_RESUME_RESPONDER = 0x0, 12525 MLX5_RESUME_VHCA_IN_OP_MOD_RESUME_INITIATOR = 0x1, 12526 }; 12527 12528 struct mlx5_ifc_resume_vhca_in_bits { 12529 u8 opcode[0x10]; 12530 u8 uid[0x10]; 12531 12532 u8 reserved_at_20[0x10]; 12533 u8 op_mod[0x10]; 12534 12535 u8 reserved_at_40[0x10]; 12536 u8 vhca_id[0x10]; 12537 12538 u8 reserved_at_60[0x20]; 12539 }; 12540 12541 struct mlx5_ifc_resume_vhca_out_bits { 12542 u8 status[0x8]; 12543 u8 reserved_at_8[0x18]; 12544 12545 u8 syndrome[0x20]; 12546 12547 u8 reserved_at_40[0x40]; 12548 }; 12549 12550 struct mlx5_ifc_query_vhca_migration_state_in_bits { 12551 u8 opcode[0x10]; 12552 u8 uid[0x10]; 12553 12554 u8 reserved_at_20[0x10]; 12555 u8 op_mod[0x10]; 12556 12557 u8 incremental[0x1]; 12558 u8 chunk[0x1]; 12559 u8 reserved_at_42[0xe]; 12560 u8 vhca_id[0x10]; 12561 12562 u8 reserved_at_60[0x20]; 12563 }; 12564 12565 struct mlx5_ifc_query_vhca_migration_state_out_bits { 12566 u8 status[0x8]; 12567 u8 reserved_at_8[0x18]; 12568 12569 u8 syndrome[0x20]; 12570 12571 u8 reserved_at_40[0x40]; 12572 12573 u8 required_umem_size[0x20]; 12574 12575 u8 reserved_at_a0[0x20]; 12576 12577 u8 remaining_total_size[0x40]; 12578 12579 u8 reserved_at_100[0x100]; 12580 }; 12581 12582 struct mlx5_ifc_save_vhca_state_in_bits { 12583 u8 opcode[0x10]; 12584 u8 uid[0x10]; 12585 12586 u8 reserved_at_20[0x10]; 12587 u8 op_mod[0x10]; 12588 12589 u8 incremental[0x1]; 12590 u8 set_track[0x1]; 12591 u8 reserved_at_42[0xe]; 12592 u8 vhca_id[0x10]; 12593 12594 u8 reserved_at_60[0x20]; 12595 12596 u8 va[0x40]; 12597 12598 u8 mkey[0x20]; 12599 12600 u8 size[0x20]; 12601 }; 12602 12603 struct mlx5_ifc_save_vhca_state_out_bits { 12604 u8 status[0x8]; 12605 u8 reserved_at_8[0x18]; 12606 12607 u8 syndrome[0x20]; 12608 12609 u8 actual_image_size[0x20]; 12610 12611 u8 next_required_umem_size[0x20]; 12612 }; 12613 12614 struct mlx5_ifc_load_vhca_state_in_bits { 12615 u8 opcode[0x10]; 12616 u8 uid[0x10]; 12617 12618 u8 reserved_at_20[0x10]; 12619 u8 op_mod[0x10]; 12620 12621 u8 reserved_at_40[0x10]; 12622 u8 vhca_id[0x10]; 12623 12624 u8 reserved_at_60[0x20]; 12625 12626 u8 va[0x40]; 12627 12628 u8 mkey[0x20]; 12629 12630 u8 size[0x20]; 12631 }; 12632 12633 struct mlx5_ifc_load_vhca_state_out_bits { 12634 u8 status[0x8]; 12635 u8 reserved_at_8[0x18]; 12636 12637 u8 syndrome[0x20]; 12638 12639 u8 reserved_at_40[0x40]; 12640 }; 12641 12642 struct mlx5_ifc_adv_virtualization_cap_bits { 12643 u8 reserved_at_0[0x3]; 12644 u8 pg_track_log_max_num[0x5]; 12645 u8 pg_track_max_num_range[0x8]; 12646 u8 pg_track_log_min_addr_space[0x8]; 12647 u8 pg_track_log_max_addr_space[0x8]; 12648 12649 u8 reserved_at_20[0x3]; 12650 u8 pg_track_log_min_msg_size[0x5]; 12651 u8 reserved_at_28[0x3]; 12652 u8 pg_track_log_max_msg_size[0x5]; 12653 u8 reserved_at_30[0x3]; 12654 u8 pg_track_log_min_page_size[0x5]; 12655 u8 reserved_at_38[0x3]; 12656 u8 pg_track_log_max_page_size[0x5]; 12657 12658 u8 reserved_at_40[0x7c0]; 12659 }; 12660 12661 struct mlx5_ifc_page_track_report_entry_bits { 12662 u8 dirty_address_high[0x20]; 12663 12664 u8 dirty_address_low[0x20]; 12665 }; 12666 12667 enum { 12668 MLX5_PAGE_TRACK_STATE_TRACKING, 12669 MLX5_PAGE_TRACK_STATE_REPORTING, 12670 MLX5_PAGE_TRACK_STATE_ERROR, 12671 }; 12672 12673 struct mlx5_ifc_page_track_range_bits { 12674 u8 start_address[0x40]; 12675 12676 u8 length[0x40]; 12677 }; 12678 12679 struct mlx5_ifc_page_track_bits { 12680 u8 modify_field_select[0x40]; 12681 12682 u8 reserved_at_40[0x10]; 12683 u8 vhca_id[0x10]; 12684 12685 u8 reserved_at_60[0x20]; 12686 12687 u8 state[0x4]; 12688 u8 track_type[0x4]; 12689 u8 log_addr_space_size[0x8]; 12690 u8 reserved_at_90[0x3]; 12691 u8 log_page_size[0x5]; 12692 u8 reserved_at_98[0x3]; 12693 u8 log_msg_size[0x5]; 12694 12695 u8 reserved_at_a0[0x8]; 12696 u8 reporting_qpn[0x18]; 12697 12698 u8 reserved_at_c0[0x18]; 12699 u8 num_ranges[0x8]; 12700 12701 u8 reserved_at_e0[0x20]; 12702 12703 u8 range_start_address[0x40]; 12704 12705 u8 length[0x40]; 12706 12707 struct mlx5_ifc_page_track_range_bits track_range[0]; 12708 }; 12709 12710 struct mlx5_ifc_create_page_track_obj_in_bits { 12711 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12712 struct mlx5_ifc_page_track_bits obj_context; 12713 }; 12714 12715 struct mlx5_ifc_modify_page_track_obj_in_bits { 12716 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12717 struct mlx5_ifc_page_track_bits obj_context; 12718 }; 12719 12720 struct mlx5_ifc_query_page_track_obj_out_bits { 12721 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 12722 struct mlx5_ifc_page_track_bits obj_context; 12723 }; 12724 12725 struct mlx5_ifc_msecq_reg_bits { 12726 u8 reserved_at_0[0x20]; 12727 12728 u8 reserved_at_20[0x12]; 12729 u8 network_option[0x2]; 12730 u8 local_ssm_code[0x4]; 12731 u8 local_enhanced_ssm_code[0x8]; 12732 12733 u8 local_clock_identity[0x40]; 12734 12735 u8 reserved_at_80[0x180]; 12736 }; 12737 12738 enum { 12739 MLX5_MSEES_FIELD_SELECT_ENABLE = BIT(0), 12740 MLX5_MSEES_FIELD_SELECT_ADMIN_STATUS = BIT(1), 12741 MLX5_MSEES_FIELD_SELECT_ADMIN_FREQ_MEASURE = BIT(2), 12742 }; 12743 12744 enum mlx5_msees_admin_status { 12745 MLX5_MSEES_ADMIN_STATUS_FREE_RUNNING = 0x0, 12746 MLX5_MSEES_ADMIN_STATUS_TRACK = 0x1, 12747 }; 12748 12749 enum mlx5_msees_oper_status { 12750 MLX5_MSEES_OPER_STATUS_FREE_RUNNING = 0x0, 12751 MLX5_MSEES_OPER_STATUS_SELF_TRACK = 0x1, 12752 MLX5_MSEES_OPER_STATUS_OTHER_TRACK = 0x2, 12753 MLX5_MSEES_OPER_STATUS_HOLDOVER = 0x3, 12754 MLX5_MSEES_OPER_STATUS_FAIL_HOLDOVER = 0x4, 12755 MLX5_MSEES_OPER_STATUS_FAIL_FREE_RUNNING = 0x5, 12756 }; 12757 12758 enum mlx5_msees_failure_reason { 12759 MLX5_MSEES_FAILURE_REASON_UNDEFINED_ERROR = 0x0, 12760 MLX5_MSEES_FAILURE_REASON_PORT_DOWN = 0x1, 12761 MLX5_MSEES_FAILURE_REASON_TOO_HIGH_FREQUENCY_DIFF = 0x2, 12762 MLX5_MSEES_FAILURE_REASON_NET_SYNCHRONIZER_DEVICE_ERROR = 0x3, 12763 MLX5_MSEES_FAILURE_REASON_LACK_OF_RESOURCES = 0x4, 12764 }; 12765 12766 struct mlx5_ifc_msees_reg_bits { 12767 u8 reserved_at_0[0x8]; 12768 u8 local_port[0x8]; 12769 u8 pnat[0x2]; 12770 u8 lp_msb[0x2]; 12771 u8 reserved_at_14[0xc]; 12772 12773 u8 field_select[0x20]; 12774 12775 u8 admin_status[0x4]; 12776 u8 oper_status[0x4]; 12777 u8 ho_acq[0x1]; 12778 u8 reserved_at_49[0xc]; 12779 u8 admin_freq_measure[0x1]; 12780 u8 oper_freq_measure[0x1]; 12781 u8 failure_reason[0x9]; 12782 12783 u8 frequency_diff[0x20]; 12784 12785 u8 reserved_at_80[0x180]; 12786 }; 12787 12788 #endif /* MLX5_IFC_H */ 12789