1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 #ifndef MLX5_IFC_H 33 #define MLX5_IFC_H 34 35 #include "mlx5_ifc_fpga.h" 36 37 enum { 38 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0, 39 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1, 40 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2, 41 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3, 42 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13, 43 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14, 44 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c, 45 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d, 46 MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4, 47 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5, 48 MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED = 0x7, 49 MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT = 0xc, 50 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10, 51 MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR = 0x11, 52 MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR = 0x12, 53 MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR = 0x8, 54 MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE = 0x9, 55 MLX5_EVENT_TYPE_CODING_GPIO_EVENT = 0x15, 56 MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19, 57 MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a, 58 MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT = 0x1b, 59 MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT = 0x1f, 60 MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa, 61 MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb, 62 MLX5_EVENT_TYPE_CODING_FPGA_ERROR = 0x20, 63 MLX5_EVENT_TYPE_CODING_FPGA_QP_ERROR = 0x21 64 }; 65 66 enum { 67 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0, 68 MLX5_SET_HCA_CAP_OP_MOD_ETHERNET_OFFLOADS = 0x1, 69 MLX5_SET_HCA_CAP_OP_MOD_ODP = 0x2, 70 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3, 71 MLX5_SET_HCA_CAP_OP_MOD_ROCE = 0x4, 72 MLX5_SET_HCA_CAP_OP_MOD_IPSEC = 0x15, 73 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE2 = 0x20, 74 MLX5_SET_HCA_CAP_OP_MOD_PORT_SELECTION = 0x25, 75 }; 76 77 enum { 78 MLX5_SHARED_RESOURCE_UID = 0xffff, 79 }; 80 81 enum { 82 MLX5_OBJ_TYPE_SW_ICM = 0x0008, 83 MLX5_OBJ_TYPE_GENEVE_TLV_OPT = 0x000b, 84 MLX5_OBJ_TYPE_VIRTIO_NET_Q = 0x000d, 85 MLX5_OBJ_TYPE_VIRTIO_Q_COUNTERS = 0x001c, 86 MLX5_OBJ_TYPE_MATCH_DEFINER = 0x0018, 87 MLX5_OBJ_TYPE_HEADER_MODIFY_ARGUMENT = 0x23, 88 MLX5_OBJ_TYPE_STC = 0x0040, 89 MLX5_OBJ_TYPE_RTC = 0x0041, 90 MLX5_OBJ_TYPE_STE = 0x0042, 91 MLX5_OBJ_TYPE_MODIFY_HDR_PATTERN = 0x0043, 92 MLX5_OBJ_TYPE_PAGE_TRACK = 0x46, 93 MLX5_OBJ_TYPE_MKEY = 0xff01, 94 MLX5_OBJ_TYPE_QP = 0xff02, 95 MLX5_OBJ_TYPE_PSV = 0xff03, 96 MLX5_OBJ_TYPE_RMP = 0xff04, 97 MLX5_OBJ_TYPE_XRC_SRQ = 0xff05, 98 MLX5_OBJ_TYPE_RQ = 0xff06, 99 MLX5_OBJ_TYPE_SQ = 0xff07, 100 MLX5_OBJ_TYPE_TIR = 0xff08, 101 MLX5_OBJ_TYPE_TIS = 0xff09, 102 MLX5_OBJ_TYPE_DCT = 0xff0a, 103 MLX5_OBJ_TYPE_XRQ = 0xff0b, 104 MLX5_OBJ_TYPE_RQT = 0xff0e, 105 MLX5_OBJ_TYPE_FLOW_COUNTER = 0xff0f, 106 MLX5_OBJ_TYPE_CQ = 0xff10, 107 MLX5_OBJ_TYPE_FT_ALIAS = 0xff15, 108 }; 109 110 enum { 111 MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM = (1ULL << MLX5_OBJ_TYPE_SW_ICM), 112 MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT = (1ULL << 11), 113 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q = (1ULL << 13), 114 MLX5_GENERAL_OBJ_TYPES_CAP_HEADER_MODIFY_ARGUMENT = 115 (1ULL << MLX5_OBJ_TYPE_HEADER_MODIFY_ARGUMENT), 116 MLX5_GENERAL_OBJ_TYPES_CAP_MACSEC_OFFLOAD = (1ULL << 39), 117 }; 118 119 enum { 120 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100, 121 MLX5_CMD_OP_QUERY_ADAPTER = 0x101, 122 MLX5_CMD_OP_INIT_HCA = 0x102, 123 MLX5_CMD_OP_TEARDOWN_HCA = 0x103, 124 MLX5_CMD_OP_ENABLE_HCA = 0x104, 125 MLX5_CMD_OP_DISABLE_HCA = 0x105, 126 MLX5_CMD_OP_QUERY_PAGES = 0x107, 127 MLX5_CMD_OP_MANAGE_PAGES = 0x108, 128 MLX5_CMD_OP_SET_HCA_CAP = 0x109, 129 MLX5_CMD_OP_QUERY_ISSI = 0x10a, 130 MLX5_CMD_OP_SET_ISSI = 0x10b, 131 MLX5_CMD_OP_SET_DRIVER_VERSION = 0x10d, 132 MLX5_CMD_OP_QUERY_SF_PARTITION = 0x111, 133 MLX5_CMD_OP_ALLOC_SF = 0x113, 134 MLX5_CMD_OP_DEALLOC_SF = 0x114, 135 MLX5_CMD_OP_SUSPEND_VHCA = 0x115, 136 MLX5_CMD_OP_RESUME_VHCA = 0x116, 137 MLX5_CMD_OP_QUERY_VHCA_MIGRATION_STATE = 0x117, 138 MLX5_CMD_OP_SAVE_VHCA_STATE = 0x118, 139 MLX5_CMD_OP_LOAD_VHCA_STATE = 0x119, 140 MLX5_CMD_OP_CREATE_MKEY = 0x200, 141 MLX5_CMD_OP_QUERY_MKEY = 0x201, 142 MLX5_CMD_OP_DESTROY_MKEY = 0x202, 143 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203, 144 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204, 145 MLX5_CMD_OP_ALLOC_MEMIC = 0x205, 146 MLX5_CMD_OP_DEALLOC_MEMIC = 0x206, 147 MLX5_CMD_OP_MODIFY_MEMIC = 0x207, 148 MLX5_CMD_OP_CREATE_EQ = 0x301, 149 MLX5_CMD_OP_DESTROY_EQ = 0x302, 150 MLX5_CMD_OP_QUERY_EQ = 0x303, 151 MLX5_CMD_OP_GEN_EQE = 0x304, 152 MLX5_CMD_OP_CREATE_CQ = 0x400, 153 MLX5_CMD_OP_DESTROY_CQ = 0x401, 154 MLX5_CMD_OP_QUERY_CQ = 0x402, 155 MLX5_CMD_OP_MODIFY_CQ = 0x403, 156 MLX5_CMD_OP_CREATE_QP = 0x500, 157 MLX5_CMD_OP_DESTROY_QP = 0x501, 158 MLX5_CMD_OP_RST2INIT_QP = 0x502, 159 MLX5_CMD_OP_INIT2RTR_QP = 0x503, 160 MLX5_CMD_OP_RTR2RTS_QP = 0x504, 161 MLX5_CMD_OP_RTS2RTS_QP = 0x505, 162 MLX5_CMD_OP_SQERR2RTS_QP = 0x506, 163 MLX5_CMD_OP_2ERR_QP = 0x507, 164 MLX5_CMD_OP_2RST_QP = 0x50a, 165 MLX5_CMD_OP_QUERY_QP = 0x50b, 166 MLX5_CMD_OP_SQD_RTS_QP = 0x50c, 167 MLX5_CMD_OP_INIT2INIT_QP = 0x50e, 168 MLX5_CMD_OP_CREATE_PSV = 0x600, 169 MLX5_CMD_OP_DESTROY_PSV = 0x601, 170 MLX5_CMD_OP_CREATE_SRQ = 0x700, 171 MLX5_CMD_OP_DESTROY_SRQ = 0x701, 172 MLX5_CMD_OP_QUERY_SRQ = 0x702, 173 MLX5_CMD_OP_ARM_RQ = 0x703, 174 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705, 175 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706, 176 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707, 177 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708, 178 MLX5_CMD_OP_CREATE_DCT = 0x710, 179 MLX5_CMD_OP_DESTROY_DCT = 0x711, 180 MLX5_CMD_OP_DRAIN_DCT = 0x712, 181 MLX5_CMD_OP_QUERY_DCT = 0x713, 182 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714, 183 MLX5_CMD_OP_CREATE_XRQ = 0x717, 184 MLX5_CMD_OP_DESTROY_XRQ = 0x718, 185 MLX5_CMD_OP_QUERY_XRQ = 0x719, 186 MLX5_CMD_OP_ARM_XRQ = 0x71a, 187 MLX5_CMD_OP_QUERY_XRQ_DC_PARAMS_ENTRY = 0x725, 188 MLX5_CMD_OP_SET_XRQ_DC_PARAMS_ENTRY = 0x726, 189 MLX5_CMD_OP_QUERY_XRQ_ERROR_PARAMS = 0x727, 190 MLX5_CMD_OP_RELEASE_XRQ_ERROR = 0x729, 191 MLX5_CMD_OP_MODIFY_XRQ = 0x72a, 192 MLX5_CMD_OP_QUERY_ESW_FUNCTIONS = 0x740, 193 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750, 194 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751, 195 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752, 196 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753, 197 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754, 198 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755, 199 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760, 200 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761, 201 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762, 202 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763, 203 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764, 204 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765, 205 MLX5_CMD_OP_QUERY_VNIC_ENV = 0x76f, 206 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770, 207 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771, 208 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772, 209 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773, 210 MLX5_CMD_OP_SET_MONITOR_COUNTER = 0x774, 211 MLX5_CMD_OP_ARM_MONITOR_COUNTER = 0x775, 212 MLX5_CMD_OP_SET_PP_RATE_LIMIT = 0x780, 213 MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781, 214 MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT = 0x782, 215 MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT = 0x783, 216 MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT = 0x784, 217 MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT = 0x785, 218 MLX5_CMD_OP_CREATE_QOS_PARA_VPORT = 0x786, 219 MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT = 0x787, 220 MLX5_CMD_OP_ALLOC_PD = 0x800, 221 MLX5_CMD_OP_DEALLOC_PD = 0x801, 222 MLX5_CMD_OP_ALLOC_UAR = 0x802, 223 MLX5_CMD_OP_DEALLOC_UAR = 0x803, 224 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804, 225 MLX5_CMD_OP_ACCESS_REG = 0x805, 226 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806, 227 MLX5_CMD_OP_DETACH_FROM_MCG = 0x807, 228 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a, 229 MLX5_CMD_OP_MAD_IFC = 0x50d, 230 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b, 231 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c, 232 MLX5_CMD_OP_NOP = 0x80d, 233 MLX5_CMD_OP_ALLOC_XRCD = 0x80e, 234 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f, 235 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816, 236 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817, 237 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822, 238 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823, 239 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824, 240 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825, 241 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826, 242 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827, 243 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828, 244 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829, 245 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a, 246 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b, 247 MLX5_CMD_OP_SET_WOL_ROL = 0x830, 248 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831, 249 MLX5_CMD_OP_CREATE_LAG = 0x840, 250 MLX5_CMD_OP_MODIFY_LAG = 0x841, 251 MLX5_CMD_OP_QUERY_LAG = 0x842, 252 MLX5_CMD_OP_DESTROY_LAG = 0x843, 253 MLX5_CMD_OP_CREATE_VPORT_LAG = 0x844, 254 MLX5_CMD_OP_DESTROY_VPORT_LAG = 0x845, 255 MLX5_CMD_OP_CREATE_TIR = 0x900, 256 MLX5_CMD_OP_MODIFY_TIR = 0x901, 257 MLX5_CMD_OP_DESTROY_TIR = 0x902, 258 MLX5_CMD_OP_QUERY_TIR = 0x903, 259 MLX5_CMD_OP_CREATE_SQ = 0x904, 260 MLX5_CMD_OP_MODIFY_SQ = 0x905, 261 MLX5_CMD_OP_DESTROY_SQ = 0x906, 262 MLX5_CMD_OP_QUERY_SQ = 0x907, 263 MLX5_CMD_OP_CREATE_RQ = 0x908, 264 MLX5_CMD_OP_MODIFY_RQ = 0x909, 265 MLX5_CMD_OP_SET_DELAY_DROP_PARAMS = 0x910, 266 MLX5_CMD_OP_DESTROY_RQ = 0x90a, 267 MLX5_CMD_OP_QUERY_RQ = 0x90b, 268 MLX5_CMD_OP_CREATE_RMP = 0x90c, 269 MLX5_CMD_OP_MODIFY_RMP = 0x90d, 270 MLX5_CMD_OP_DESTROY_RMP = 0x90e, 271 MLX5_CMD_OP_QUERY_RMP = 0x90f, 272 MLX5_CMD_OP_CREATE_TIS = 0x912, 273 MLX5_CMD_OP_MODIFY_TIS = 0x913, 274 MLX5_CMD_OP_DESTROY_TIS = 0x914, 275 MLX5_CMD_OP_QUERY_TIS = 0x915, 276 MLX5_CMD_OP_CREATE_RQT = 0x916, 277 MLX5_CMD_OP_MODIFY_RQT = 0x917, 278 MLX5_CMD_OP_DESTROY_RQT = 0x918, 279 MLX5_CMD_OP_QUERY_RQT = 0x919, 280 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f, 281 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930, 282 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931, 283 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932, 284 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933, 285 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934, 286 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935, 287 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936, 288 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937, 289 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938, 290 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939, 291 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a, 292 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b, 293 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c, 294 MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT = 0x93d, 295 MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT = 0x93e, 296 MLX5_CMD_OP_QUERY_PACKET_REFORMAT_CONTEXT = 0x93f, 297 MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT = 0x940, 298 MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941, 299 MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT = 0x942, 300 MLX5_CMD_OP_FPGA_CREATE_QP = 0x960, 301 MLX5_CMD_OP_FPGA_MODIFY_QP = 0x961, 302 MLX5_CMD_OP_FPGA_QUERY_QP = 0x962, 303 MLX5_CMD_OP_FPGA_DESTROY_QP = 0x963, 304 MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS = 0x964, 305 MLX5_CMD_OP_CREATE_GENERAL_OBJECT = 0xa00, 306 MLX5_CMD_OP_MODIFY_GENERAL_OBJECT = 0xa01, 307 MLX5_CMD_OP_QUERY_GENERAL_OBJECT = 0xa02, 308 MLX5_CMD_OP_DESTROY_GENERAL_OBJECT = 0xa03, 309 MLX5_CMD_OP_CREATE_UCTX = 0xa04, 310 MLX5_CMD_OP_DESTROY_UCTX = 0xa06, 311 MLX5_CMD_OP_CREATE_UMEM = 0xa08, 312 MLX5_CMD_OP_DESTROY_UMEM = 0xa0a, 313 MLX5_CMD_OP_SYNC_STEERING = 0xb00, 314 MLX5_CMD_OP_QUERY_VHCA_STATE = 0xb0d, 315 MLX5_CMD_OP_MODIFY_VHCA_STATE = 0xb0e, 316 MLX5_CMD_OP_SYNC_CRYPTO = 0xb12, 317 MLX5_CMD_OP_ALLOW_OTHER_VHCA_ACCESS = 0xb16, 318 MLX5_CMD_OP_GENERATE_WQE = 0xb17, 319 MLX5_CMD_OPCODE_QUERY_VUID = 0xb22, 320 MLX5_CMD_OP_MAX 321 }; 322 323 /* Valid range for general commands that don't work over an object */ 324 enum { 325 MLX5_CMD_OP_GENERAL_START = 0xb00, 326 MLX5_CMD_OP_GENERAL_END = 0xd00, 327 }; 328 329 enum { 330 MLX5_FT_NIC_RX_2_NIC_RX_RDMA = BIT(0), 331 MLX5_FT_NIC_TX_RDMA_2_NIC_TX = BIT(1), 332 }; 333 334 enum { 335 MLX5_CMD_OP_MOD_UPDATE_HEADER_MODIFY_ARGUMENT = 0x1, 336 }; 337 338 struct mlx5_ifc_flow_table_fields_supported_bits { 339 u8 outer_dmac[0x1]; 340 u8 outer_smac[0x1]; 341 u8 outer_ether_type[0x1]; 342 u8 outer_ip_version[0x1]; 343 u8 outer_first_prio[0x1]; 344 u8 outer_first_cfi[0x1]; 345 u8 outer_first_vid[0x1]; 346 u8 outer_ipv4_ttl[0x1]; 347 u8 outer_second_prio[0x1]; 348 u8 outer_second_cfi[0x1]; 349 u8 outer_second_vid[0x1]; 350 u8 reserved_at_b[0x1]; 351 u8 outer_sip[0x1]; 352 u8 outer_dip[0x1]; 353 u8 outer_frag[0x1]; 354 u8 outer_ip_protocol[0x1]; 355 u8 outer_ip_ecn[0x1]; 356 u8 outer_ip_dscp[0x1]; 357 u8 outer_udp_sport[0x1]; 358 u8 outer_udp_dport[0x1]; 359 u8 outer_tcp_sport[0x1]; 360 u8 outer_tcp_dport[0x1]; 361 u8 outer_tcp_flags[0x1]; 362 u8 outer_gre_protocol[0x1]; 363 u8 outer_gre_key[0x1]; 364 u8 outer_vxlan_vni[0x1]; 365 u8 outer_geneve_vni[0x1]; 366 u8 outer_geneve_oam[0x1]; 367 u8 outer_geneve_protocol_type[0x1]; 368 u8 outer_geneve_opt_len[0x1]; 369 u8 source_vhca_port[0x1]; 370 u8 source_eswitch_port[0x1]; 371 372 u8 inner_dmac[0x1]; 373 u8 inner_smac[0x1]; 374 u8 inner_ether_type[0x1]; 375 u8 inner_ip_version[0x1]; 376 u8 inner_first_prio[0x1]; 377 u8 inner_first_cfi[0x1]; 378 u8 inner_first_vid[0x1]; 379 u8 reserved_at_27[0x1]; 380 u8 inner_second_prio[0x1]; 381 u8 inner_second_cfi[0x1]; 382 u8 inner_second_vid[0x1]; 383 u8 reserved_at_2b[0x1]; 384 u8 inner_sip[0x1]; 385 u8 inner_dip[0x1]; 386 u8 inner_frag[0x1]; 387 u8 inner_ip_protocol[0x1]; 388 u8 inner_ip_ecn[0x1]; 389 u8 inner_ip_dscp[0x1]; 390 u8 inner_udp_sport[0x1]; 391 u8 inner_udp_dport[0x1]; 392 u8 inner_tcp_sport[0x1]; 393 u8 inner_tcp_dport[0x1]; 394 u8 inner_tcp_flags[0x1]; 395 u8 reserved_at_37[0x9]; 396 397 u8 geneve_tlv_option_0_data[0x1]; 398 u8 geneve_tlv_option_0_exist[0x1]; 399 u8 reserved_at_42[0x3]; 400 u8 outer_first_mpls_over_udp[0x4]; 401 u8 outer_first_mpls_over_gre[0x4]; 402 u8 inner_first_mpls[0x4]; 403 u8 outer_first_mpls[0x4]; 404 u8 reserved_at_55[0x2]; 405 u8 outer_esp_spi[0x1]; 406 u8 reserved_at_58[0x2]; 407 u8 bth_dst_qp[0x1]; 408 u8 reserved_at_5b[0x5]; 409 410 u8 reserved_at_60[0x18]; 411 u8 metadata_reg_c_7[0x1]; 412 u8 metadata_reg_c_6[0x1]; 413 u8 metadata_reg_c_5[0x1]; 414 u8 metadata_reg_c_4[0x1]; 415 u8 metadata_reg_c_3[0x1]; 416 u8 metadata_reg_c_2[0x1]; 417 u8 metadata_reg_c_1[0x1]; 418 u8 metadata_reg_c_0[0x1]; 419 }; 420 421 /* Table 2170 - Flow Table Fields Supported 2 Format */ 422 struct mlx5_ifc_flow_table_fields_supported_2_bits { 423 u8 reserved_at_0[0x2]; 424 u8 inner_l4_type[0x1]; 425 u8 outer_l4_type[0x1]; 426 u8 reserved_at_4[0xa]; 427 u8 bth_opcode[0x1]; 428 u8 reserved_at_f[0x1]; 429 u8 tunnel_header_0_1[0x1]; 430 u8 reserved_at_11[0xf]; 431 432 u8 reserved_at_20[0x60]; 433 }; 434 435 struct mlx5_ifc_flow_table_prop_layout_bits { 436 u8 ft_support[0x1]; 437 u8 reserved_at_1[0x1]; 438 u8 flow_counter[0x1]; 439 u8 flow_modify_en[0x1]; 440 u8 modify_root[0x1]; 441 u8 identified_miss_table_mode[0x1]; 442 u8 flow_table_modify[0x1]; 443 u8 reformat[0x1]; 444 u8 decap[0x1]; 445 u8 reset_root_to_default[0x1]; 446 u8 pop_vlan[0x1]; 447 u8 push_vlan[0x1]; 448 u8 reserved_at_c[0x1]; 449 u8 pop_vlan_2[0x1]; 450 u8 push_vlan_2[0x1]; 451 u8 reformat_and_vlan_action[0x1]; 452 u8 reserved_at_10[0x1]; 453 u8 sw_owner[0x1]; 454 u8 reformat_l3_tunnel_to_l2[0x1]; 455 u8 reformat_l2_to_l3_tunnel[0x1]; 456 u8 reformat_and_modify_action[0x1]; 457 u8 ignore_flow_level[0x1]; 458 u8 reserved_at_16[0x1]; 459 u8 table_miss_action_domain[0x1]; 460 u8 termination_table[0x1]; 461 u8 reformat_and_fwd_to_table[0x1]; 462 u8 reserved_at_1a[0x2]; 463 u8 ipsec_encrypt[0x1]; 464 u8 ipsec_decrypt[0x1]; 465 u8 sw_owner_v2[0x1]; 466 u8 reserved_at_1f[0x1]; 467 468 u8 termination_table_raw_traffic[0x1]; 469 u8 reserved_at_21[0x1]; 470 u8 log_max_ft_size[0x6]; 471 u8 log_max_modify_header_context[0x8]; 472 u8 max_modify_header_actions[0x8]; 473 u8 max_ft_level[0x8]; 474 475 u8 reformat_add_esp_trasport[0x1]; 476 u8 reformat_l2_to_l3_esp_tunnel[0x1]; 477 u8 reformat_add_esp_transport_over_udp[0x1]; 478 u8 reformat_del_esp_trasport[0x1]; 479 u8 reformat_l3_esp_tunnel_to_l2[0x1]; 480 u8 reformat_del_esp_transport_over_udp[0x1]; 481 u8 execute_aso[0x1]; 482 u8 reserved_at_47[0x19]; 483 484 u8 reserved_at_60[0x2]; 485 u8 reformat_insert[0x1]; 486 u8 reformat_remove[0x1]; 487 u8 macsec_encrypt[0x1]; 488 u8 macsec_decrypt[0x1]; 489 u8 reserved_at_66[0x2]; 490 u8 reformat_add_macsec[0x1]; 491 u8 reformat_remove_macsec[0x1]; 492 u8 reparse[0x1]; 493 u8 reserved_at_6b[0x1]; 494 u8 cross_vhca_object[0x1]; 495 u8 reformat_l2_to_l3_audp_tunnel[0x1]; 496 u8 reformat_l3_audp_tunnel_to_l2[0x1]; 497 u8 ignore_flow_level_rtc_valid[0x1]; 498 u8 reserved_at_70[0x8]; 499 u8 log_max_ft_num[0x8]; 500 501 u8 reserved_at_80[0x10]; 502 u8 log_max_flow_counter[0x8]; 503 u8 log_max_destination[0x8]; 504 505 u8 reserved_at_a0[0x18]; 506 u8 log_max_flow[0x8]; 507 508 u8 reserved_at_c0[0x40]; 509 510 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support; 511 512 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support; 513 }; 514 515 struct mlx5_ifc_odp_per_transport_service_cap_bits { 516 u8 send[0x1]; 517 u8 receive[0x1]; 518 u8 write[0x1]; 519 u8 read[0x1]; 520 u8 atomic[0x1]; 521 u8 srq_receive[0x1]; 522 u8 reserved_at_6[0x1a]; 523 }; 524 525 struct mlx5_ifc_ipv4_layout_bits { 526 u8 reserved_at_0[0x60]; 527 528 u8 ipv4[0x20]; 529 }; 530 531 struct mlx5_ifc_ipv6_layout_bits { 532 u8 ipv6[16][0x8]; 533 }; 534 535 struct mlx5_ifc_ipv6_simple_layout_bits { 536 u8 ipv6_127_96[0x20]; 537 u8 ipv6_95_64[0x20]; 538 u8 ipv6_63_32[0x20]; 539 u8 ipv6_31_0[0x20]; 540 }; 541 542 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits { 543 struct mlx5_ifc_ipv6_simple_layout_bits ipv6_simple_layout; 544 struct mlx5_ifc_ipv6_layout_bits ipv6_layout; 545 struct mlx5_ifc_ipv4_layout_bits ipv4_layout; 546 u8 reserved_at_0[0x80]; 547 }; 548 549 enum { 550 MLX5_PACKET_L4_TYPE_NONE, 551 MLX5_PACKET_L4_TYPE_TCP, 552 MLX5_PACKET_L4_TYPE_UDP, 553 }; 554 555 struct mlx5_ifc_fte_match_set_lyr_2_4_bits { 556 u8 smac_47_16[0x20]; 557 558 u8 smac_15_0[0x10]; 559 u8 ethertype[0x10]; 560 561 u8 dmac_47_16[0x20]; 562 563 u8 dmac_15_0[0x10]; 564 u8 first_prio[0x3]; 565 u8 first_cfi[0x1]; 566 u8 first_vid[0xc]; 567 568 u8 ip_protocol[0x8]; 569 u8 ip_dscp[0x6]; 570 u8 ip_ecn[0x2]; 571 u8 cvlan_tag[0x1]; 572 u8 svlan_tag[0x1]; 573 u8 frag[0x1]; 574 u8 ip_version[0x4]; 575 u8 tcp_flags[0x9]; 576 577 u8 tcp_sport[0x10]; 578 u8 tcp_dport[0x10]; 579 580 u8 l4_type[0x2]; 581 u8 reserved_at_c2[0xe]; 582 u8 ipv4_ihl[0x4]; 583 u8 reserved_at_c4[0x4]; 584 585 u8 ttl_hoplimit[0x8]; 586 587 u8 udp_sport[0x10]; 588 u8 udp_dport[0x10]; 589 590 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6; 591 592 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6; 593 }; 594 595 struct mlx5_ifc_nvgre_key_bits { 596 u8 hi[0x18]; 597 u8 lo[0x8]; 598 }; 599 600 union mlx5_ifc_gre_key_bits { 601 struct mlx5_ifc_nvgre_key_bits nvgre; 602 u8 key[0x20]; 603 }; 604 605 struct mlx5_ifc_fte_match_set_misc_bits { 606 u8 gre_c_present[0x1]; 607 u8 reserved_at_1[0x1]; 608 u8 gre_k_present[0x1]; 609 u8 gre_s_present[0x1]; 610 u8 source_vhca_port[0x4]; 611 u8 source_sqn[0x18]; 612 613 u8 source_eswitch_owner_vhca_id[0x10]; 614 u8 source_port[0x10]; 615 616 u8 outer_second_prio[0x3]; 617 u8 outer_second_cfi[0x1]; 618 u8 outer_second_vid[0xc]; 619 u8 inner_second_prio[0x3]; 620 u8 inner_second_cfi[0x1]; 621 u8 inner_second_vid[0xc]; 622 623 u8 outer_second_cvlan_tag[0x1]; 624 u8 inner_second_cvlan_tag[0x1]; 625 u8 outer_second_svlan_tag[0x1]; 626 u8 inner_second_svlan_tag[0x1]; 627 u8 reserved_at_64[0xc]; 628 u8 gre_protocol[0x10]; 629 630 union mlx5_ifc_gre_key_bits gre_key; 631 632 u8 vxlan_vni[0x18]; 633 u8 bth_opcode[0x8]; 634 635 u8 geneve_vni[0x18]; 636 u8 reserved_at_d8[0x6]; 637 u8 geneve_tlv_option_0_exist[0x1]; 638 u8 geneve_oam[0x1]; 639 640 u8 reserved_at_e0[0xc]; 641 u8 outer_ipv6_flow_label[0x14]; 642 643 u8 reserved_at_100[0xc]; 644 u8 inner_ipv6_flow_label[0x14]; 645 646 u8 reserved_at_120[0xa]; 647 u8 geneve_opt_len[0x6]; 648 u8 geneve_protocol_type[0x10]; 649 650 u8 reserved_at_140[0x8]; 651 u8 bth_dst_qp[0x18]; 652 u8 inner_esp_spi[0x20]; 653 u8 outer_esp_spi[0x20]; 654 u8 reserved_at_1a0[0x60]; 655 }; 656 657 struct mlx5_ifc_fte_match_mpls_bits { 658 u8 mpls_label[0x14]; 659 u8 mpls_exp[0x3]; 660 u8 mpls_s_bos[0x1]; 661 u8 mpls_ttl[0x8]; 662 }; 663 664 struct mlx5_ifc_fte_match_set_misc2_bits { 665 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls; 666 667 struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls; 668 669 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre; 670 671 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp; 672 673 u8 metadata_reg_c_7[0x20]; 674 675 u8 metadata_reg_c_6[0x20]; 676 677 u8 metadata_reg_c_5[0x20]; 678 679 u8 metadata_reg_c_4[0x20]; 680 681 u8 metadata_reg_c_3[0x20]; 682 683 u8 metadata_reg_c_2[0x20]; 684 685 u8 metadata_reg_c_1[0x20]; 686 687 u8 metadata_reg_c_0[0x20]; 688 689 u8 metadata_reg_a[0x20]; 690 691 u8 reserved_at_1a0[0x8]; 692 693 u8 macsec_syndrome[0x8]; 694 u8 ipsec_syndrome[0x8]; 695 u8 reserved_at_1b8[0x8]; 696 697 u8 reserved_at_1c0[0x40]; 698 }; 699 700 struct mlx5_ifc_fte_match_set_misc3_bits { 701 u8 inner_tcp_seq_num[0x20]; 702 703 u8 outer_tcp_seq_num[0x20]; 704 705 u8 inner_tcp_ack_num[0x20]; 706 707 u8 outer_tcp_ack_num[0x20]; 708 709 u8 reserved_at_80[0x8]; 710 u8 outer_vxlan_gpe_vni[0x18]; 711 712 u8 outer_vxlan_gpe_next_protocol[0x8]; 713 u8 outer_vxlan_gpe_flags[0x8]; 714 u8 reserved_at_b0[0x10]; 715 716 u8 icmp_header_data[0x20]; 717 718 u8 icmpv6_header_data[0x20]; 719 720 u8 icmp_type[0x8]; 721 u8 icmp_code[0x8]; 722 u8 icmpv6_type[0x8]; 723 u8 icmpv6_code[0x8]; 724 725 u8 geneve_tlv_option_0_data[0x20]; 726 727 u8 gtpu_teid[0x20]; 728 729 u8 gtpu_msg_type[0x8]; 730 u8 gtpu_msg_flags[0x8]; 731 u8 reserved_at_170[0x10]; 732 733 u8 gtpu_dw_2[0x20]; 734 735 u8 gtpu_first_ext_dw_0[0x20]; 736 737 u8 gtpu_dw_0[0x20]; 738 739 u8 reserved_at_1e0[0x20]; 740 }; 741 742 struct mlx5_ifc_fte_match_set_misc4_bits { 743 u8 prog_sample_field_value_0[0x20]; 744 745 u8 prog_sample_field_id_0[0x20]; 746 747 u8 prog_sample_field_value_1[0x20]; 748 749 u8 prog_sample_field_id_1[0x20]; 750 751 u8 prog_sample_field_value_2[0x20]; 752 753 u8 prog_sample_field_id_2[0x20]; 754 755 u8 prog_sample_field_value_3[0x20]; 756 757 u8 prog_sample_field_id_3[0x20]; 758 759 u8 reserved_at_100[0x100]; 760 }; 761 762 struct mlx5_ifc_fte_match_set_misc5_bits { 763 u8 macsec_tag_0[0x20]; 764 765 u8 macsec_tag_1[0x20]; 766 767 u8 macsec_tag_2[0x20]; 768 769 u8 macsec_tag_3[0x20]; 770 771 u8 tunnel_header_0[0x20]; 772 773 u8 tunnel_header_1[0x20]; 774 775 u8 tunnel_header_2[0x20]; 776 777 u8 tunnel_header_3[0x20]; 778 779 u8 reserved_at_100[0x100]; 780 }; 781 782 struct mlx5_ifc_cmd_pas_bits { 783 u8 pa_h[0x20]; 784 785 u8 pa_l[0x14]; 786 u8 reserved_at_34[0xc]; 787 }; 788 789 struct mlx5_ifc_uint64_bits { 790 u8 hi[0x20]; 791 792 u8 lo[0x20]; 793 }; 794 795 enum { 796 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0, 797 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7, 798 MLX5_ADS_STAT_RATE_10GBPS = 0x8, 799 MLX5_ADS_STAT_RATE_30GBPS = 0x9, 800 MLX5_ADS_STAT_RATE_5GBPS = 0xa, 801 MLX5_ADS_STAT_RATE_20GBPS = 0xb, 802 MLX5_ADS_STAT_RATE_40GBPS = 0xc, 803 MLX5_ADS_STAT_RATE_60GBPS = 0xd, 804 MLX5_ADS_STAT_RATE_80GBPS = 0xe, 805 MLX5_ADS_STAT_RATE_120GBPS = 0xf, 806 }; 807 808 struct mlx5_ifc_ads_bits { 809 u8 fl[0x1]; 810 u8 free_ar[0x1]; 811 u8 reserved_at_2[0xe]; 812 u8 pkey_index[0x10]; 813 814 u8 plane_index[0x8]; 815 u8 grh[0x1]; 816 u8 mlid[0x7]; 817 u8 rlid[0x10]; 818 819 u8 ack_timeout[0x5]; 820 u8 reserved_at_45[0x3]; 821 u8 src_addr_index[0x8]; 822 u8 reserved_at_50[0x4]; 823 u8 stat_rate[0x4]; 824 u8 hop_limit[0x8]; 825 826 u8 reserved_at_60[0x4]; 827 u8 tclass[0x8]; 828 u8 flow_label[0x14]; 829 830 u8 rgid_rip[16][0x8]; 831 832 u8 reserved_at_100[0x4]; 833 u8 f_dscp[0x1]; 834 u8 f_ecn[0x1]; 835 u8 reserved_at_106[0x1]; 836 u8 f_eth_prio[0x1]; 837 u8 ecn[0x2]; 838 u8 dscp[0x6]; 839 u8 udp_sport[0x10]; 840 841 u8 dei_cfi[0x1]; 842 u8 eth_prio[0x3]; 843 u8 sl[0x4]; 844 u8 vhca_port_num[0x8]; 845 u8 rmac_47_32[0x10]; 846 847 u8 rmac_31_0[0x20]; 848 }; 849 850 struct mlx5_ifc_flow_table_nic_cap_bits { 851 u8 nic_rx_multi_path_tirs[0x1]; 852 u8 nic_rx_multi_path_tirs_fts[0x1]; 853 u8 allow_sniffer_and_nic_rx_shared_tir[0x1]; 854 u8 reserved_at_3[0x4]; 855 u8 sw_owner_reformat_supported[0x1]; 856 u8 reserved_at_8[0x18]; 857 858 u8 encap_general_header[0x1]; 859 u8 reserved_at_21[0xa]; 860 u8 log_max_packet_reformat_context[0x5]; 861 u8 reserved_at_30[0x6]; 862 u8 max_encap_header_size[0xa]; 863 u8 reserved_at_40[0x1c0]; 864 865 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive; 866 867 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_rdma; 868 869 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer; 870 871 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit; 872 873 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_rdma; 874 875 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer; 876 877 u8 reserved_at_e00[0x600]; 878 879 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_receive; 880 881 u8 reserved_at_1480[0x80]; 882 883 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_receive_rdma; 884 885 u8 reserved_at_1580[0x280]; 886 887 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_transmit_rdma; 888 889 u8 reserved_at_1880[0x780]; 890 891 u8 sw_steering_nic_rx_action_drop_icm_address[0x40]; 892 893 u8 sw_steering_nic_tx_action_drop_icm_address[0x40]; 894 895 u8 sw_steering_nic_tx_action_allow_icm_address[0x40]; 896 897 u8 reserved_at_20c0[0x5f40]; 898 }; 899 900 struct mlx5_ifc_port_selection_cap_bits { 901 u8 reserved_at_0[0x10]; 902 u8 port_select_flow_table[0x1]; 903 u8 reserved_at_11[0x1]; 904 u8 port_select_flow_table_bypass[0x1]; 905 u8 reserved_at_13[0xd]; 906 907 u8 reserved_at_20[0x1e0]; 908 909 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_port_selection; 910 911 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_port_selection; 912 913 u8 reserved_at_480[0x7b80]; 914 }; 915 916 enum { 917 MLX5_FDB_TO_VPORT_REG_C_0 = 0x01, 918 MLX5_FDB_TO_VPORT_REG_C_1 = 0x02, 919 MLX5_FDB_TO_VPORT_REG_C_2 = 0x04, 920 MLX5_FDB_TO_VPORT_REG_C_3 = 0x08, 921 MLX5_FDB_TO_VPORT_REG_C_4 = 0x10, 922 MLX5_FDB_TO_VPORT_REG_C_5 = 0x20, 923 MLX5_FDB_TO_VPORT_REG_C_6 = 0x40, 924 MLX5_FDB_TO_VPORT_REG_C_7 = 0x80, 925 }; 926 927 struct mlx5_ifc_flow_table_eswitch_cap_bits { 928 u8 fdb_to_vport_reg_c_id[0x8]; 929 u8 reserved_at_8[0x5]; 930 u8 fdb_uplink_hairpin[0x1]; 931 u8 fdb_multi_path_any_table_limit_regc[0x1]; 932 u8 reserved_at_f[0x1]; 933 u8 fdb_dynamic_tunnel[0x1]; 934 u8 reserved_at_11[0x1]; 935 u8 fdb_multi_path_any_table[0x1]; 936 u8 reserved_at_13[0x2]; 937 u8 fdb_modify_header_fwd_to_table[0x1]; 938 u8 fdb_ipv4_ttl_modify[0x1]; 939 u8 flow_source[0x1]; 940 u8 reserved_at_18[0x2]; 941 u8 multi_fdb_encap[0x1]; 942 u8 egress_acl_forward_to_vport[0x1]; 943 u8 fdb_multi_path_to_table[0x1]; 944 u8 reserved_at_1d[0x3]; 945 946 u8 reserved_at_20[0x1e0]; 947 948 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb; 949 950 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress; 951 952 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress; 953 954 u8 reserved_at_800[0xC00]; 955 956 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_esw_fdb; 957 958 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_bitmask_support_2_esw_fdb; 959 960 u8 reserved_at_1500[0x300]; 961 962 u8 sw_steering_fdb_action_drop_icm_address_rx[0x40]; 963 964 u8 sw_steering_fdb_action_drop_icm_address_tx[0x40]; 965 966 u8 sw_steering_uplink_icm_address_rx[0x40]; 967 968 u8 sw_steering_uplink_icm_address_tx[0x40]; 969 970 u8 reserved_at_1900[0x6700]; 971 }; 972 973 struct mlx5_ifc_wqe_based_flow_table_cap_bits { 974 u8 reserved_at_0[0x3]; 975 u8 log_max_num_ste[0x5]; 976 u8 reserved_at_8[0x3]; 977 u8 log_max_num_stc[0x5]; 978 u8 reserved_at_10[0x3]; 979 u8 log_max_num_rtc[0x5]; 980 u8 reserved_at_18[0x3]; 981 u8 log_max_num_header_modify_pattern[0x5]; 982 983 u8 rtc_hash_split_table[0x1]; 984 u8 rtc_linear_lookup_table[0x1]; 985 u8 reserved_at_22[0x1]; 986 u8 stc_alloc_log_granularity[0x5]; 987 u8 reserved_at_28[0x3]; 988 u8 stc_alloc_log_max[0x5]; 989 u8 reserved_at_30[0x3]; 990 u8 ste_alloc_log_granularity[0x5]; 991 u8 reserved_at_38[0x3]; 992 u8 ste_alloc_log_max[0x5]; 993 994 u8 reserved_at_40[0xb]; 995 u8 rtc_reparse_mode[0x5]; 996 u8 reserved_at_50[0x3]; 997 u8 rtc_index_mode[0x5]; 998 u8 reserved_at_58[0x3]; 999 u8 rtc_log_depth_max[0x5]; 1000 1001 u8 reserved_at_60[0x10]; 1002 u8 ste_format[0x10]; 1003 1004 u8 stc_action_type[0x80]; 1005 1006 u8 header_insert_type[0x10]; 1007 u8 header_remove_type[0x10]; 1008 1009 u8 trivial_match_definer[0x20]; 1010 1011 u8 reserved_at_140[0x1b]; 1012 u8 rtc_max_num_hash_definer_gen_wqe[0x5]; 1013 1014 u8 reserved_at_160[0x18]; 1015 u8 access_index_mode[0x8]; 1016 1017 u8 reserved_at_180[0x10]; 1018 u8 ste_format_gen_wqe[0x10]; 1019 1020 u8 linear_match_definer_reg_c3[0x20]; 1021 1022 u8 fdb_jump_to_tir_stc[0x1]; 1023 u8 reserved_at_1c1[0x1f]; 1024 }; 1025 1026 struct mlx5_ifc_esw_cap_bits { 1027 u8 reserved_at_0[0x1d]; 1028 u8 merged_eswitch[0x1]; 1029 u8 reserved_at_1e[0x2]; 1030 1031 u8 reserved_at_20[0x40]; 1032 1033 u8 esw_manager_vport_number_valid[0x1]; 1034 u8 reserved_at_61[0xf]; 1035 u8 esw_manager_vport_number[0x10]; 1036 1037 u8 reserved_at_80[0x780]; 1038 }; 1039 1040 enum { 1041 MLX5_COUNTER_SOURCE_ESWITCH = 0x0, 1042 MLX5_COUNTER_FLOW_ESWITCH = 0x1, 1043 }; 1044 1045 struct mlx5_ifc_e_switch_cap_bits { 1046 u8 vport_svlan_strip[0x1]; 1047 u8 vport_cvlan_strip[0x1]; 1048 u8 vport_svlan_insert[0x1]; 1049 u8 vport_cvlan_insert_if_not_exist[0x1]; 1050 u8 vport_cvlan_insert_overwrite[0x1]; 1051 u8 reserved_at_5[0x1]; 1052 u8 vport_cvlan_insert_always[0x1]; 1053 u8 esw_shared_ingress_acl[0x1]; 1054 u8 esw_uplink_ingress_acl[0x1]; 1055 u8 root_ft_on_other_esw[0x1]; 1056 u8 reserved_at_a[0xf]; 1057 u8 esw_functions_changed[0x1]; 1058 u8 reserved_at_1a[0x1]; 1059 u8 ecpf_vport_exists[0x1]; 1060 u8 counter_eswitch_affinity[0x1]; 1061 u8 merged_eswitch[0x1]; 1062 u8 nic_vport_node_guid_modify[0x1]; 1063 u8 nic_vport_port_guid_modify[0x1]; 1064 1065 u8 vxlan_encap_decap[0x1]; 1066 u8 nvgre_encap_decap[0x1]; 1067 u8 reserved_at_22[0x1]; 1068 u8 log_max_fdb_encap_uplink[0x5]; 1069 u8 reserved_at_21[0x3]; 1070 u8 log_max_packet_reformat_context[0x5]; 1071 u8 reserved_2b[0x6]; 1072 u8 max_encap_header_size[0xa]; 1073 1074 u8 reserved_at_40[0xb]; 1075 u8 log_max_esw_sf[0x5]; 1076 u8 esw_sf_base_id[0x10]; 1077 1078 u8 reserved_at_60[0x7a0]; 1079 1080 }; 1081 1082 struct mlx5_ifc_qos_cap_bits { 1083 u8 packet_pacing[0x1]; 1084 u8 esw_scheduling[0x1]; 1085 u8 esw_bw_share[0x1]; 1086 u8 esw_rate_limit[0x1]; 1087 u8 reserved_at_4[0x1]; 1088 u8 packet_pacing_burst_bound[0x1]; 1089 u8 packet_pacing_typical_size[0x1]; 1090 u8 reserved_at_7[0x1]; 1091 u8 nic_sq_scheduling[0x1]; 1092 u8 nic_bw_share[0x1]; 1093 u8 nic_rate_limit[0x1]; 1094 u8 packet_pacing_uid[0x1]; 1095 u8 log_esw_max_sched_depth[0x4]; 1096 u8 reserved_at_10[0x10]; 1097 1098 u8 reserved_at_20[0x9]; 1099 u8 esw_cross_esw_sched[0x1]; 1100 u8 reserved_at_2a[0x1]; 1101 u8 log_max_qos_nic_queue_group[0x5]; 1102 u8 reserved_at_30[0x10]; 1103 1104 u8 packet_pacing_max_rate[0x20]; 1105 1106 u8 packet_pacing_min_rate[0x20]; 1107 1108 u8 reserved_at_80[0xb]; 1109 u8 log_esw_max_rate_limit[0x5]; 1110 u8 packet_pacing_rate_table_size[0x10]; 1111 1112 u8 esw_element_type[0x10]; 1113 u8 esw_tsar_type[0x10]; 1114 1115 u8 reserved_at_c0[0x10]; 1116 u8 max_qos_para_vport[0x10]; 1117 1118 u8 max_tsar_bw_share[0x20]; 1119 1120 u8 nic_element_type[0x10]; 1121 u8 nic_tsar_type[0x10]; 1122 1123 u8 reserved_at_120[0x3]; 1124 u8 log_meter_aso_granularity[0x5]; 1125 u8 reserved_at_128[0x3]; 1126 u8 log_meter_aso_max_alloc[0x5]; 1127 u8 reserved_at_130[0x3]; 1128 u8 log_max_num_meter_aso[0x5]; 1129 u8 reserved_at_138[0x8]; 1130 1131 u8 reserved_at_140[0x6c0]; 1132 }; 1133 1134 struct mlx5_ifc_debug_cap_bits { 1135 u8 core_dump_general[0x1]; 1136 u8 core_dump_qp[0x1]; 1137 u8 reserved_at_2[0x7]; 1138 u8 resource_dump[0x1]; 1139 u8 reserved_at_a[0x16]; 1140 1141 u8 reserved_at_20[0x2]; 1142 u8 stall_detect[0x1]; 1143 u8 reserved_at_23[0x1d]; 1144 1145 u8 reserved_at_40[0x7c0]; 1146 }; 1147 1148 struct mlx5_ifc_per_protocol_networking_offload_caps_bits { 1149 u8 csum_cap[0x1]; 1150 u8 vlan_cap[0x1]; 1151 u8 lro_cap[0x1]; 1152 u8 lro_psh_flag[0x1]; 1153 u8 lro_time_stamp[0x1]; 1154 u8 reserved_at_5[0x2]; 1155 u8 wqe_vlan_insert[0x1]; 1156 u8 self_lb_en_modifiable[0x1]; 1157 u8 reserved_at_9[0x2]; 1158 u8 max_lso_cap[0x5]; 1159 u8 multi_pkt_send_wqe[0x2]; 1160 u8 wqe_inline_mode[0x2]; 1161 u8 rss_ind_tbl_cap[0x4]; 1162 u8 reg_umr_sq[0x1]; 1163 u8 scatter_fcs[0x1]; 1164 u8 enhanced_multi_pkt_send_wqe[0x1]; 1165 u8 tunnel_lso_const_out_ip_id[0x1]; 1166 u8 tunnel_lro_gre[0x1]; 1167 u8 tunnel_lro_vxlan[0x1]; 1168 u8 tunnel_stateless_gre[0x1]; 1169 u8 tunnel_stateless_vxlan[0x1]; 1170 1171 u8 swp[0x1]; 1172 u8 swp_csum[0x1]; 1173 u8 swp_lso[0x1]; 1174 u8 cqe_checksum_full[0x1]; 1175 u8 tunnel_stateless_geneve_tx[0x1]; 1176 u8 tunnel_stateless_mpls_over_udp[0x1]; 1177 u8 tunnel_stateless_mpls_over_gre[0x1]; 1178 u8 tunnel_stateless_vxlan_gpe[0x1]; 1179 u8 tunnel_stateless_ipv4_over_vxlan[0x1]; 1180 u8 tunnel_stateless_ip_over_ip[0x1]; 1181 u8 insert_trailer[0x1]; 1182 u8 reserved_at_2b[0x1]; 1183 u8 tunnel_stateless_ip_over_ip_rx[0x1]; 1184 u8 tunnel_stateless_ip_over_ip_tx[0x1]; 1185 u8 reserved_at_2e[0x2]; 1186 u8 max_vxlan_udp_ports[0x8]; 1187 u8 swp_csum_l4_partial[0x1]; 1188 u8 reserved_at_39[0x5]; 1189 u8 max_geneve_opt_len[0x1]; 1190 u8 tunnel_stateless_geneve_rx[0x1]; 1191 1192 u8 reserved_at_40[0x10]; 1193 u8 lro_min_mss_size[0x10]; 1194 1195 u8 reserved_at_60[0x120]; 1196 1197 u8 lro_timer_supported_periods[4][0x20]; 1198 1199 u8 reserved_at_200[0x600]; 1200 }; 1201 1202 enum { 1203 MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING = 0x0, 1204 MLX5_TIMESTAMP_FORMAT_CAP_REAL_TIME = 0x1, 1205 MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING_AND_REAL_TIME = 0x2, 1206 }; 1207 1208 struct mlx5_ifc_roce_cap_bits { 1209 u8 roce_apm[0x1]; 1210 u8 reserved_at_1[0x3]; 1211 u8 sw_r_roce_src_udp_port[0x1]; 1212 u8 fl_rc_qp_when_roce_disabled[0x1]; 1213 u8 fl_rc_qp_when_roce_enabled[0x1]; 1214 u8 roce_cc_general[0x1]; 1215 u8 qp_ooo_transmit_default[0x1]; 1216 u8 reserved_at_9[0x15]; 1217 u8 qp_ts_format[0x2]; 1218 1219 u8 reserved_at_20[0x60]; 1220 1221 u8 reserved_at_80[0xc]; 1222 u8 l3_type[0x4]; 1223 u8 reserved_at_90[0x8]; 1224 u8 roce_version[0x8]; 1225 1226 u8 reserved_at_a0[0x10]; 1227 u8 r_roce_dest_udp_port[0x10]; 1228 1229 u8 r_roce_max_src_udp_port[0x10]; 1230 u8 r_roce_min_src_udp_port[0x10]; 1231 1232 u8 reserved_at_e0[0x10]; 1233 u8 roce_address_table_size[0x10]; 1234 1235 u8 reserved_at_100[0x700]; 1236 }; 1237 1238 struct mlx5_ifc_sync_steering_in_bits { 1239 u8 opcode[0x10]; 1240 u8 uid[0x10]; 1241 1242 u8 reserved_at_20[0x10]; 1243 u8 op_mod[0x10]; 1244 1245 u8 reserved_at_40[0xc0]; 1246 }; 1247 1248 struct mlx5_ifc_sync_steering_out_bits { 1249 u8 status[0x8]; 1250 u8 reserved_at_8[0x18]; 1251 1252 u8 syndrome[0x20]; 1253 1254 u8 reserved_at_40[0x40]; 1255 }; 1256 1257 struct mlx5_ifc_sync_crypto_in_bits { 1258 u8 opcode[0x10]; 1259 u8 uid[0x10]; 1260 1261 u8 reserved_at_20[0x10]; 1262 u8 op_mod[0x10]; 1263 1264 u8 reserved_at_40[0x20]; 1265 1266 u8 reserved_at_60[0x10]; 1267 u8 crypto_type[0x10]; 1268 1269 u8 reserved_at_80[0x80]; 1270 }; 1271 1272 struct mlx5_ifc_sync_crypto_out_bits { 1273 u8 status[0x8]; 1274 u8 reserved_at_8[0x18]; 1275 1276 u8 syndrome[0x20]; 1277 1278 u8 reserved_at_40[0x40]; 1279 }; 1280 1281 struct mlx5_ifc_device_mem_cap_bits { 1282 u8 memic[0x1]; 1283 u8 reserved_at_1[0x1f]; 1284 1285 u8 reserved_at_20[0xb]; 1286 u8 log_min_memic_alloc_size[0x5]; 1287 u8 reserved_at_30[0x8]; 1288 u8 log_max_memic_addr_alignment[0x8]; 1289 1290 u8 memic_bar_start_addr[0x40]; 1291 1292 u8 memic_bar_size[0x20]; 1293 1294 u8 max_memic_size[0x20]; 1295 1296 u8 steering_sw_icm_start_address[0x40]; 1297 1298 u8 reserved_at_100[0x8]; 1299 u8 log_header_modify_sw_icm_size[0x8]; 1300 u8 reserved_at_110[0x2]; 1301 u8 log_sw_icm_alloc_granularity[0x6]; 1302 u8 log_steering_sw_icm_size[0x8]; 1303 1304 u8 log_indirect_encap_sw_icm_size[0x8]; 1305 u8 reserved_at_128[0x10]; 1306 u8 log_header_modify_pattern_sw_icm_size[0x8]; 1307 1308 u8 header_modify_sw_icm_start_address[0x40]; 1309 1310 u8 reserved_at_180[0x40]; 1311 1312 u8 header_modify_pattern_sw_icm_start_address[0x40]; 1313 1314 u8 memic_operations[0x20]; 1315 1316 u8 reserved_at_220[0x20]; 1317 1318 u8 indirect_encap_sw_icm_start_address[0x40]; 1319 1320 u8 reserved_at_280[0x580]; 1321 }; 1322 1323 struct mlx5_ifc_device_event_cap_bits { 1324 u8 user_affiliated_events[4][0x40]; 1325 1326 u8 user_unaffiliated_events[4][0x40]; 1327 }; 1328 1329 struct mlx5_ifc_virtio_emulation_cap_bits { 1330 u8 desc_tunnel_offload_type[0x1]; 1331 u8 eth_frame_offload_type[0x1]; 1332 u8 virtio_version_1_0[0x1]; 1333 u8 device_features_bits_mask[0xd]; 1334 u8 event_mode[0x8]; 1335 u8 virtio_queue_type[0x8]; 1336 1337 u8 max_tunnel_desc[0x10]; 1338 u8 reserved_at_30[0x3]; 1339 u8 log_doorbell_stride[0x5]; 1340 u8 reserved_at_38[0x3]; 1341 u8 log_doorbell_bar_size[0x5]; 1342 1343 u8 doorbell_bar_offset[0x40]; 1344 1345 u8 max_emulated_devices[0x8]; 1346 u8 max_num_virtio_queues[0x18]; 1347 1348 u8 reserved_at_a0[0x20]; 1349 1350 u8 reserved_at_c0[0x13]; 1351 u8 desc_group_mkey_supported[0x1]; 1352 u8 freeze_to_rdy_supported[0x1]; 1353 u8 reserved_at_d5[0xb]; 1354 1355 u8 reserved_at_e0[0x20]; 1356 1357 u8 umem_1_buffer_param_a[0x20]; 1358 1359 u8 umem_1_buffer_param_b[0x20]; 1360 1361 u8 umem_2_buffer_param_a[0x20]; 1362 1363 u8 umem_2_buffer_param_b[0x20]; 1364 1365 u8 umem_3_buffer_param_a[0x20]; 1366 1367 u8 umem_3_buffer_param_b[0x20]; 1368 1369 u8 reserved_at_1c0[0x640]; 1370 }; 1371 1372 enum { 1373 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0, 1374 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2, 1375 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4, 1376 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8, 1377 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10, 1378 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20, 1379 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40, 1380 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80, 1381 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100, 1382 }; 1383 1384 enum { 1385 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1, 1386 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2, 1387 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4, 1388 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8, 1389 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10, 1390 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20, 1391 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40, 1392 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80, 1393 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100, 1394 }; 1395 1396 struct mlx5_ifc_atomic_caps_bits { 1397 u8 reserved_at_0[0x40]; 1398 1399 u8 atomic_req_8B_endianness_mode[0x2]; 1400 u8 reserved_at_42[0x4]; 1401 u8 supported_atomic_req_8B_endianness_mode_1[0x1]; 1402 1403 u8 reserved_at_47[0x19]; 1404 1405 u8 reserved_at_60[0x20]; 1406 1407 u8 reserved_at_80[0x10]; 1408 u8 atomic_operations[0x10]; 1409 1410 u8 reserved_at_a0[0x10]; 1411 u8 atomic_size_qp[0x10]; 1412 1413 u8 reserved_at_c0[0x10]; 1414 u8 atomic_size_dc[0x10]; 1415 1416 u8 reserved_at_e0[0x720]; 1417 }; 1418 1419 struct mlx5_ifc_odp_scheme_cap_bits { 1420 u8 reserved_at_0[0x40]; 1421 1422 u8 sig[0x1]; 1423 u8 reserved_at_41[0x4]; 1424 u8 page_prefetch[0x1]; 1425 u8 reserved_at_46[0x1a]; 1426 1427 u8 reserved_at_60[0x20]; 1428 1429 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps; 1430 1431 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps; 1432 1433 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps; 1434 1435 struct mlx5_ifc_odp_per_transport_service_cap_bits xrc_odp_caps; 1436 1437 struct mlx5_ifc_odp_per_transport_service_cap_bits dc_odp_caps; 1438 1439 u8 reserved_at_120[0xe0]; 1440 }; 1441 1442 struct mlx5_ifc_odp_cap_bits { 1443 struct mlx5_ifc_odp_scheme_cap_bits transport_page_fault_scheme_cap; 1444 1445 struct mlx5_ifc_odp_scheme_cap_bits memory_page_fault_scheme_cap; 1446 1447 u8 reserved_at_400[0x200]; 1448 1449 u8 mem_page_fault[0x1]; 1450 u8 reserved_at_601[0x1f]; 1451 1452 u8 reserved_at_620[0x1e0]; 1453 }; 1454 1455 struct mlx5_ifc_tls_cap_bits { 1456 u8 tls_1_2_aes_gcm_128[0x1]; 1457 u8 tls_1_3_aes_gcm_128[0x1]; 1458 u8 tls_1_2_aes_gcm_256[0x1]; 1459 u8 tls_1_3_aes_gcm_256[0x1]; 1460 u8 reserved_at_4[0x1c]; 1461 1462 u8 reserved_at_20[0x7e0]; 1463 }; 1464 1465 struct mlx5_ifc_ipsec_cap_bits { 1466 u8 ipsec_full_offload[0x1]; 1467 u8 ipsec_crypto_offload[0x1]; 1468 u8 ipsec_esn[0x1]; 1469 u8 ipsec_crypto_esp_aes_gcm_256_encrypt[0x1]; 1470 u8 ipsec_crypto_esp_aes_gcm_128_encrypt[0x1]; 1471 u8 ipsec_crypto_esp_aes_gcm_256_decrypt[0x1]; 1472 u8 ipsec_crypto_esp_aes_gcm_128_decrypt[0x1]; 1473 u8 reserved_at_7[0x4]; 1474 u8 log_max_ipsec_offload[0x5]; 1475 u8 reserved_at_10[0x10]; 1476 1477 u8 min_log_ipsec_full_replay_window[0x8]; 1478 u8 max_log_ipsec_full_replay_window[0x8]; 1479 u8 reserved_at_30[0x7d0]; 1480 }; 1481 1482 struct mlx5_ifc_macsec_cap_bits { 1483 u8 macsec_epn[0x1]; 1484 u8 reserved_at_1[0x2]; 1485 u8 macsec_crypto_esp_aes_gcm_256_encrypt[0x1]; 1486 u8 macsec_crypto_esp_aes_gcm_128_encrypt[0x1]; 1487 u8 macsec_crypto_esp_aes_gcm_256_decrypt[0x1]; 1488 u8 macsec_crypto_esp_aes_gcm_128_decrypt[0x1]; 1489 u8 reserved_at_7[0x4]; 1490 u8 log_max_macsec_offload[0x5]; 1491 u8 reserved_at_10[0x10]; 1492 1493 u8 min_log_macsec_full_replay_window[0x8]; 1494 u8 max_log_macsec_full_replay_window[0x8]; 1495 u8 reserved_at_30[0x10]; 1496 1497 u8 reserved_at_40[0x7c0]; 1498 }; 1499 1500 enum { 1501 MLX5_WQ_TYPE_LINKED_LIST = 0x0, 1502 MLX5_WQ_TYPE_CYCLIC = 0x1, 1503 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2, 1504 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3, 1505 }; 1506 1507 enum { 1508 MLX5_WQ_END_PAD_MODE_NONE = 0x0, 1509 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1, 1510 }; 1511 1512 enum { 1513 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0, 1514 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1, 1515 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2, 1516 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3, 1517 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4, 1518 }; 1519 1520 enum { 1521 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0, 1522 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1, 1523 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2, 1524 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3, 1525 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4, 1526 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5, 1527 }; 1528 1529 enum { 1530 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0, 1531 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1, 1532 }; 1533 1534 enum { 1535 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0, 1536 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1, 1537 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3, 1538 }; 1539 1540 enum { 1541 MLX5_CAP_PORT_TYPE_IB = 0x0, 1542 MLX5_CAP_PORT_TYPE_ETH = 0x1, 1543 }; 1544 1545 enum { 1546 MLX5_CAP_UMR_FENCE_STRONG = 0x0, 1547 MLX5_CAP_UMR_FENCE_SMALL = 0x1, 1548 MLX5_CAP_UMR_FENCE_NONE = 0x2, 1549 }; 1550 1551 enum { 1552 MLX5_FLEX_IPV4_OVER_VXLAN_ENABLED = 1 << 0, 1553 MLX5_FLEX_IPV6_OVER_VXLAN_ENABLED = 1 << 1, 1554 MLX5_FLEX_IPV6_OVER_IP_ENABLED = 1 << 2, 1555 MLX5_FLEX_PARSER_GENEVE_ENABLED = 1 << 3, 1556 MLX5_FLEX_PARSER_MPLS_OVER_GRE_ENABLED = 1 << 4, 1557 MLX5_FLEX_PARSER_MPLS_OVER_UDP_ENABLED = 1 << 5, 1558 MLX5_FLEX_P_BIT_VXLAN_GPE_ENABLED = 1 << 6, 1559 MLX5_FLEX_PARSER_VXLAN_GPE_ENABLED = 1 << 7, 1560 MLX5_FLEX_PARSER_ICMP_V4_ENABLED = 1 << 8, 1561 MLX5_FLEX_PARSER_ICMP_V6_ENABLED = 1 << 9, 1562 MLX5_FLEX_PARSER_GENEVE_TLV_OPTION_0_ENABLED = 1 << 10, 1563 MLX5_FLEX_PARSER_GTPU_ENABLED = 1 << 11, 1564 MLX5_FLEX_PARSER_GTPU_DW_2_ENABLED = 1 << 16, 1565 MLX5_FLEX_PARSER_GTPU_FIRST_EXT_DW_0_ENABLED = 1 << 17, 1566 MLX5_FLEX_PARSER_GTPU_DW_0_ENABLED = 1 << 18, 1567 MLX5_FLEX_PARSER_GTPU_TEID_ENABLED = 1 << 19, 1568 }; 1569 1570 enum { 1571 MLX5_UCTX_CAP_RAW_TX = 1UL << 0, 1572 MLX5_UCTX_CAP_INTERNAL_DEV_RES = 1UL << 1, 1573 }; 1574 1575 #define MLX5_FC_BULK_SIZE_FACTOR 128 1576 1577 enum mlx5_fc_bulk_alloc_bitmask { 1578 MLX5_FC_BULK_128 = (1 << 0), 1579 MLX5_FC_BULK_256 = (1 << 1), 1580 MLX5_FC_BULK_512 = (1 << 2), 1581 MLX5_FC_BULK_1024 = (1 << 3), 1582 MLX5_FC_BULK_2048 = (1 << 4), 1583 MLX5_FC_BULK_4096 = (1 << 5), 1584 MLX5_FC_BULK_8192 = (1 << 6), 1585 MLX5_FC_BULK_16384 = (1 << 7), 1586 }; 1587 1588 #define MLX5_FC_BULK_NUM_FCS(fc_enum) (MLX5_FC_BULK_SIZE_FACTOR * (fc_enum)) 1589 1590 #define MLX5_FT_MAX_MULTIPATH_LEVEL 63 1591 1592 enum { 1593 MLX5_STEERING_FORMAT_CONNECTX_5 = 0, 1594 MLX5_STEERING_FORMAT_CONNECTX_6DX = 1, 1595 MLX5_STEERING_FORMAT_CONNECTX_7 = 2, 1596 MLX5_STEERING_FORMAT_CONNECTX_8 = 3, 1597 }; 1598 1599 struct mlx5_ifc_cmd_hca_cap_bits { 1600 u8 reserved_at_0[0x6]; 1601 u8 page_request_disable[0x1]; 1602 u8 abs_native_port_num[0x1]; 1603 u8 reserved_at_8[0x8]; 1604 u8 shared_object_to_user_object_allowed[0x1]; 1605 u8 reserved_at_13[0xe]; 1606 u8 vhca_resource_manager[0x1]; 1607 1608 u8 hca_cap_2[0x1]; 1609 u8 create_lag_when_not_master_up[0x1]; 1610 u8 dtor[0x1]; 1611 u8 event_on_vhca_state_teardown_request[0x1]; 1612 u8 event_on_vhca_state_in_use[0x1]; 1613 u8 event_on_vhca_state_active[0x1]; 1614 u8 event_on_vhca_state_allocated[0x1]; 1615 u8 event_on_vhca_state_invalid[0x1]; 1616 u8 reserved_at_28[0x8]; 1617 u8 vhca_id[0x10]; 1618 1619 u8 reserved_at_40[0x40]; 1620 1621 u8 log_max_srq_sz[0x8]; 1622 u8 log_max_qp_sz[0x8]; 1623 u8 event_cap[0x1]; 1624 u8 reserved_at_91[0x2]; 1625 u8 isolate_vl_tc_new[0x1]; 1626 u8 reserved_at_94[0x4]; 1627 u8 prio_tag_required[0x1]; 1628 u8 reserved_at_99[0x2]; 1629 u8 log_max_qp[0x5]; 1630 1631 u8 reserved_at_a0[0x3]; 1632 u8 ece_support[0x1]; 1633 u8 reserved_at_a4[0x5]; 1634 u8 reg_c_preserve[0x1]; 1635 u8 reserved_at_aa[0x1]; 1636 u8 log_max_srq[0x5]; 1637 u8 reserved_at_b0[0x1]; 1638 u8 uplink_follow[0x1]; 1639 u8 ts_cqe_to_dest_cqn[0x1]; 1640 u8 reserved_at_b3[0x6]; 1641 u8 go_back_n[0x1]; 1642 u8 reserved_at_ba[0x6]; 1643 1644 u8 max_sgl_for_optimized_performance[0x8]; 1645 u8 log_max_cq_sz[0x8]; 1646 u8 relaxed_ordering_write_umr[0x1]; 1647 u8 relaxed_ordering_read_umr[0x1]; 1648 u8 reserved_at_d2[0x7]; 1649 u8 virtio_net_device_emualtion_manager[0x1]; 1650 u8 virtio_blk_device_emualtion_manager[0x1]; 1651 u8 log_max_cq[0x5]; 1652 1653 u8 log_max_eq_sz[0x8]; 1654 u8 relaxed_ordering_write[0x1]; 1655 u8 relaxed_ordering_read_pci_enabled[0x1]; 1656 u8 log_max_mkey[0x6]; 1657 u8 reserved_at_f0[0x6]; 1658 u8 terminate_scatter_list_mkey[0x1]; 1659 u8 repeated_mkey[0x1]; 1660 u8 dump_fill_mkey[0x1]; 1661 u8 reserved_at_f9[0x2]; 1662 u8 fast_teardown[0x1]; 1663 u8 log_max_eq[0x4]; 1664 1665 u8 max_indirection[0x8]; 1666 u8 fixed_buffer_size[0x1]; 1667 u8 log_max_mrw_sz[0x7]; 1668 u8 force_teardown[0x1]; 1669 u8 reserved_at_111[0x1]; 1670 u8 log_max_bsf_list_size[0x6]; 1671 u8 umr_extended_translation_offset[0x1]; 1672 u8 null_mkey[0x1]; 1673 u8 log_max_klm_list_size[0x6]; 1674 1675 u8 reserved_at_120[0x2]; 1676 u8 qpc_extension[0x1]; 1677 u8 reserved_at_123[0x7]; 1678 u8 log_max_ra_req_dc[0x6]; 1679 u8 reserved_at_130[0x2]; 1680 u8 eth_wqe_too_small[0x1]; 1681 u8 reserved_at_133[0x6]; 1682 u8 vnic_env_cq_overrun[0x1]; 1683 u8 log_max_ra_res_dc[0x6]; 1684 1685 u8 reserved_at_140[0x5]; 1686 u8 release_all_pages[0x1]; 1687 u8 must_not_use[0x1]; 1688 u8 reserved_at_147[0x2]; 1689 u8 roce_accl[0x1]; 1690 u8 log_max_ra_req_qp[0x6]; 1691 u8 reserved_at_150[0xa]; 1692 u8 log_max_ra_res_qp[0x6]; 1693 1694 u8 end_pad[0x1]; 1695 u8 cc_query_allowed[0x1]; 1696 u8 cc_modify_allowed[0x1]; 1697 u8 start_pad[0x1]; 1698 u8 cache_line_128byte[0x1]; 1699 u8 reserved_at_165[0x4]; 1700 u8 rts2rts_qp_counters_set_id[0x1]; 1701 u8 reserved_at_16a[0x2]; 1702 u8 vnic_env_int_rq_oob[0x1]; 1703 u8 sbcam_reg[0x1]; 1704 u8 reserved_at_16e[0x1]; 1705 u8 qcam_reg[0x1]; 1706 u8 gid_table_size[0x10]; 1707 1708 u8 out_of_seq_cnt[0x1]; 1709 u8 vport_counters[0x1]; 1710 u8 retransmission_q_counters[0x1]; 1711 u8 debug[0x1]; 1712 u8 modify_rq_counter_set_id[0x1]; 1713 u8 rq_delay_drop[0x1]; 1714 u8 max_qp_cnt[0xa]; 1715 u8 pkey_table_size[0x10]; 1716 1717 u8 vport_group_manager[0x1]; 1718 u8 vhca_group_manager[0x1]; 1719 u8 ib_virt[0x1]; 1720 u8 eth_virt[0x1]; 1721 u8 vnic_env_queue_counters[0x1]; 1722 u8 ets[0x1]; 1723 u8 nic_flow_table[0x1]; 1724 u8 eswitch_manager[0x1]; 1725 u8 device_memory[0x1]; 1726 u8 mcam_reg[0x1]; 1727 u8 pcam_reg[0x1]; 1728 u8 local_ca_ack_delay[0x5]; 1729 u8 port_module_event[0x1]; 1730 u8 enhanced_error_q_counters[0x1]; 1731 u8 ports_check[0x1]; 1732 u8 reserved_at_1b3[0x1]; 1733 u8 disable_link_up[0x1]; 1734 u8 beacon_led[0x1]; 1735 u8 port_type[0x2]; 1736 u8 num_ports[0x8]; 1737 1738 u8 reserved_at_1c0[0x1]; 1739 u8 pps[0x1]; 1740 u8 pps_modify[0x1]; 1741 u8 log_max_msg[0x5]; 1742 u8 reserved_at_1c8[0x4]; 1743 u8 max_tc[0x4]; 1744 u8 temp_warn_event[0x1]; 1745 u8 dcbx[0x1]; 1746 u8 general_notification_event[0x1]; 1747 u8 reserved_at_1d3[0x2]; 1748 u8 fpga[0x1]; 1749 u8 rol_s[0x1]; 1750 u8 rol_g[0x1]; 1751 u8 reserved_at_1d8[0x1]; 1752 u8 wol_s[0x1]; 1753 u8 wol_g[0x1]; 1754 u8 wol_a[0x1]; 1755 u8 wol_b[0x1]; 1756 u8 wol_m[0x1]; 1757 u8 wol_u[0x1]; 1758 u8 wol_p[0x1]; 1759 1760 u8 stat_rate_support[0x10]; 1761 u8 reserved_at_1f0[0x1]; 1762 u8 pci_sync_for_fw_update_event[0x1]; 1763 u8 reserved_at_1f2[0x6]; 1764 u8 init2_lag_tx_port_affinity[0x1]; 1765 u8 reserved_at_1fa[0x2]; 1766 u8 wqe_based_flow_table_update_cap[0x1]; 1767 u8 cqe_version[0x4]; 1768 1769 u8 compact_address_vector[0x1]; 1770 u8 striding_rq[0x1]; 1771 u8 reserved_at_202[0x1]; 1772 u8 ipoib_enhanced_offloads[0x1]; 1773 u8 ipoib_basic_offloads[0x1]; 1774 u8 reserved_at_205[0x1]; 1775 u8 repeated_block_disabled[0x1]; 1776 u8 umr_modify_entity_size_disabled[0x1]; 1777 u8 umr_modify_atomic_disabled[0x1]; 1778 u8 umr_indirect_mkey_disabled[0x1]; 1779 u8 umr_fence[0x2]; 1780 u8 dc_req_scat_data_cqe[0x1]; 1781 u8 reserved_at_20d[0x2]; 1782 u8 drain_sigerr[0x1]; 1783 u8 cmdif_checksum[0x2]; 1784 u8 sigerr_cqe[0x1]; 1785 u8 reserved_at_213[0x1]; 1786 u8 wq_signature[0x1]; 1787 u8 sctr_data_cqe[0x1]; 1788 u8 reserved_at_216[0x1]; 1789 u8 sho[0x1]; 1790 u8 tph[0x1]; 1791 u8 rf[0x1]; 1792 u8 dct[0x1]; 1793 u8 qos[0x1]; 1794 u8 eth_net_offloads[0x1]; 1795 u8 roce[0x1]; 1796 u8 atomic[0x1]; 1797 u8 reserved_at_21f[0x1]; 1798 1799 u8 cq_oi[0x1]; 1800 u8 cq_resize[0x1]; 1801 u8 cq_moderation[0x1]; 1802 u8 cq_period_mode_modify[0x1]; 1803 u8 reserved_at_224[0x2]; 1804 u8 cq_eq_remap[0x1]; 1805 u8 pg[0x1]; 1806 u8 block_lb_mc[0x1]; 1807 u8 reserved_at_229[0x1]; 1808 u8 scqe_break_moderation[0x1]; 1809 u8 cq_period_start_from_cqe[0x1]; 1810 u8 cd[0x1]; 1811 u8 reserved_at_22d[0x1]; 1812 u8 apm[0x1]; 1813 u8 vector_calc[0x1]; 1814 u8 umr_ptr_rlky[0x1]; 1815 u8 imaicl[0x1]; 1816 u8 qp_packet_based[0x1]; 1817 u8 reserved_at_233[0x3]; 1818 u8 qkv[0x1]; 1819 u8 pkv[0x1]; 1820 u8 set_deth_sqpn[0x1]; 1821 u8 reserved_at_239[0x3]; 1822 u8 xrc[0x1]; 1823 u8 ud[0x1]; 1824 u8 uc[0x1]; 1825 u8 rc[0x1]; 1826 1827 u8 uar_4k[0x1]; 1828 u8 reserved_at_241[0x7]; 1829 u8 fl_rc_qp_when_roce_disabled[0x1]; 1830 u8 regexp_params[0x1]; 1831 u8 uar_sz[0x6]; 1832 u8 port_selection_cap[0x1]; 1833 u8 reserved_at_251[0x1]; 1834 u8 umem_uid_0[0x1]; 1835 u8 reserved_at_253[0x5]; 1836 u8 log_pg_sz[0x8]; 1837 1838 u8 bf[0x1]; 1839 u8 driver_version[0x1]; 1840 u8 pad_tx_eth_packet[0x1]; 1841 u8 reserved_at_263[0x3]; 1842 u8 mkey_by_name[0x1]; 1843 u8 reserved_at_267[0x4]; 1844 1845 u8 log_bf_reg_size[0x5]; 1846 1847 u8 reserved_at_270[0x3]; 1848 u8 qp_error_syndrome[0x1]; 1849 u8 reserved_at_274[0x2]; 1850 u8 lag_dct[0x2]; 1851 u8 lag_tx_port_affinity[0x1]; 1852 u8 lag_native_fdb_selection[0x1]; 1853 u8 reserved_at_27a[0x1]; 1854 u8 lag_master[0x1]; 1855 u8 num_lag_ports[0x4]; 1856 1857 u8 reserved_at_280[0x10]; 1858 u8 max_wqe_sz_sq[0x10]; 1859 1860 u8 reserved_at_2a0[0xb]; 1861 u8 shampo[0x1]; 1862 u8 reserved_at_2ac[0x4]; 1863 u8 max_wqe_sz_rq[0x10]; 1864 1865 u8 max_flow_counter_31_16[0x10]; 1866 u8 max_wqe_sz_sq_dc[0x10]; 1867 1868 u8 reserved_at_2e0[0x7]; 1869 u8 max_qp_mcg[0x19]; 1870 1871 u8 reserved_at_300[0x10]; 1872 u8 flow_counter_bulk_alloc[0x8]; 1873 u8 log_max_mcg[0x8]; 1874 1875 u8 reserved_at_320[0x3]; 1876 u8 log_max_transport_domain[0x5]; 1877 u8 reserved_at_328[0x2]; 1878 u8 relaxed_ordering_read[0x1]; 1879 u8 log_max_pd[0x5]; 1880 u8 dp_ordering_ooo_all_ud[0x1]; 1881 u8 dp_ordering_ooo_all_uc[0x1]; 1882 u8 dp_ordering_ooo_all_xrc[0x1]; 1883 u8 dp_ordering_ooo_all_dc[0x1]; 1884 u8 dp_ordering_ooo_all_rc[0x1]; 1885 u8 pcie_reset_using_hotreset_method[0x1]; 1886 u8 pci_sync_for_fw_update_with_driver_unload[0x1]; 1887 u8 vnic_env_cnt_steering_fail[0x1]; 1888 u8 vport_counter_local_loopback[0x1]; 1889 u8 q_counter_aggregation[0x1]; 1890 u8 q_counter_other_vport[0x1]; 1891 u8 log_max_xrcd[0x5]; 1892 1893 u8 nic_receive_steering_discard[0x1]; 1894 u8 receive_discard_vport_down[0x1]; 1895 u8 transmit_discard_vport_down[0x1]; 1896 u8 eq_overrun_count[0x1]; 1897 u8 reserved_at_344[0x1]; 1898 u8 invalid_command_count[0x1]; 1899 u8 quota_exceeded_count[0x1]; 1900 u8 reserved_at_347[0x1]; 1901 u8 log_max_flow_counter_bulk[0x8]; 1902 u8 max_flow_counter_15_0[0x10]; 1903 1904 1905 u8 reserved_at_360[0x3]; 1906 u8 log_max_rq[0x5]; 1907 u8 reserved_at_368[0x3]; 1908 u8 log_max_sq[0x5]; 1909 u8 reserved_at_370[0x3]; 1910 u8 log_max_tir[0x5]; 1911 u8 reserved_at_378[0x3]; 1912 u8 log_max_tis[0x5]; 1913 1914 u8 basic_cyclic_rcv_wqe[0x1]; 1915 u8 reserved_at_381[0x2]; 1916 u8 log_max_rmp[0x5]; 1917 u8 reserved_at_388[0x3]; 1918 u8 log_max_rqt[0x5]; 1919 u8 reserved_at_390[0x3]; 1920 u8 log_max_rqt_size[0x5]; 1921 u8 reserved_at_398[0x3]; 1922 u8 log_max_tis_per_sq[0x5]; 1923 1924 u8 ext_stride_num_range[0x1]; 1925 u8 roce_rw_supported[0x1]; 1926 u8 log_max_current_uc_list_wr_supported[0x1]; 1927 u8 log_max_stride_sz_rq[0x5]; 1928 u8 reserved_at_3a8[0x3]; 1929 u8 log_min_stride_sz_rq[0x5]; 1930 u8 reserved_at_3b0[0x3]; 1931 u8 log_max_stride_sz_sq[0x5]; 1932 u8 reserved_at_3b8[0x3]; 1933 u8 log_min_stride_sz_sq[0x5]; 1934 1935 u8 hairpin[0x1]; 1936 u8 reserved_at_3c1[0x2]; 1937 u8 log_max_hairpin_queues[0x5]; 1938 u8 reserved_at_3c8[0x3]; 1939 u8 log_max_hairpin_wq_data_sz[0x5]; 1940 u8 reserved_at_3d0[0x3]; 1941 u8 log_max_hairpin_num_packets[0x5]; 1942 u8 reserved_at_3d8[0x3]; 1943 u8 log_max_wq_sz[0x5]; 1944 1945 u8 nic_vport_change_event[0x1]; 1946 u8 disable_local_lb_uc[0x1]; 1947 u8 disable_local_lb_mc[0x1]; 1948 u8 log_min_hairpin_wq_data_sz[0x5]; 1949 u8 reserved_at_3e8[0x1]; 1950 u8 silent_mode[0x1]; 1951 u8 vhca_state[0x1]; 1952 u8 log_max_vlan_list[0x5]; 1953 u8 reserved_at_3f0[0x3]; 1954 u8 log_max_current_mc_list[0x5]; 1955 u8 reserved_at_3f8[0x3]; 1956 u8 log_max_current_uc_list[0x5]; 1957 1958 u8 general_obj_types[0x40]; 1959 1960 u8 sq_ts_format[0x2]; 1961 u8 rq_ts_format[0x2]; 1962 u8 steering_format_version[0x4]; 1963 u8 create_qp_start_hint[0x18]; 1964 1965 u8 reserved_at_460[0x1]; 1966 u8 ats[0x1]; 1967 u8 cross_vhca_rqt[0x1]; 1968 u8 log_max_uctx[0x5]; 1969 u8 reserved_at_468[0x1]; 1970 u8 crypto[0x1]; 1971 u8 ipsec_offload[0x1]; 1972 u8 log_max_umem[0x5]; 1973 u8 max_num_eqs[0x10]; 1974 1975 u8 reserved_at_480[0x1]; 1976 u8 tls_tx[0x1]; 1977 u8 tls_rx[0x1]; 1978 u8 log_max_l2_table[0x5]; 1979 u8 reserved_at_488[0x8]; 1980 u8 log_uar_page_sz[0x10]; 1981 1982 u8 reserved_at_4a0[0x20]; 1983 u8 device_frequency_mhz[0x20]; 1984 u8 device_frequency_khz[0x20]; 1985 1986 u8 reserved_at_500[0x20]; 1987 u8 num_of_uars_per_page[0x20]; 1988 1989 u8 flex_parser_protocols[0x20]; 1990 1991 u8 max_geneve_tlv_options[0x8]; 1992 u8 reserved_at_568[0x3]; 1993 u8 max_geneve_tlv_option_data_len[0x5]; 1994 u8 reserved_at_570[0x9]; 1995 u8 adv_virtualization[0x1]; 1996 u8 reserved_at_57a[0x6]; 1997 1998 u8 reserved_at_580[0xb]; 1999 u8 log_max_dci_stream_channels[0x5]; 2000 u8 reserved_at_590[0x3]; 2001 u8 log_max_dci_errored_streams[0x5]; 2002 u8 reserved_at_598[0x8]; 2003 2004 u8 reserved_at_5a0[0x10]; 2005 u8 enhanced_cqe_compression[0x1]; 2006 u8 reserved_at_5b1[0x1]; 2007 u8 crossing_vhca_mkey[0x1]; 2008 u8 log_max_dek[0x5]; 2009 u8 reserved_at_5b8[0x4]; 2010 u8 mini_cqe_resp_stride_index[0x1]; 2011 u8 cqe_128_always[0x1]; 2012 u8 cqe_compression_128[0x1]; 2013 u8 cqe_compression[0x1]; 2014 2015 u8 cqe_compression_timeout[0x10]; 2016 u8 cqe_compression_max_num[0x10]; 2017 2018 u8 reserved_at_5e0[0x8]; 2019 u8 flex_parser_id_gtpu_dw_0[0x4]; 2020 u8 reserved_at_5ec[0x4]; 2021 u8 tag_matching[0x1]; 2022 u8 rndv_offload_rc[0x1]; 2023 u8 rndv_offload_dc[0x1]; 2024 u8 log_tag_matching_list_sz[0x5]; 2025 u8 reserved_at_5f8[0x3]; 2026 u8 log_max_xrq[0x5]; 2027 2028 u8 affiliate_nic_vport_criteria[0x8]; 2029 u8 native_port_num[0x8]; 2030 u8 num_vhca_ports[0x8]; 2031 u8 flex_parser_id_gtpu_teid[0x4]; 2032 u8 reserved_at_61c[0x2]; 2033 u8 sw_owner_id[0x1]; 2034 u8 reserved_at_61f[0x1]; 2035 2036 u8 max_num_of_monitor_counters[0x10]; 2037 u8 num_ppcnt_monitor_counters[0x10]; 2038 2039 u8 max_num_sf[0x10]; 2040 u8 num_q_monitor_counters[0x10]; 2041 2042 u8 reserved_at_660[0x20]; 2043 2044 u8 sf[0x1]; 2045 u8 sf_set_partition[0x1]; 2046 u8 reserved_at_682[0x1]; 2047 u8 log_max_sf[0x5]; 2048 u8 apu[0x1]; 2049 u8 reserved_at_689[0x4]; 2050 u8 migration[0x1]; 2051 u8 reserved_at_68e[0x2]; 2052 u8 log_min_sf_size[0x8]; 2053 u8 max_num_sf_partitions[0x8]; 2054 2055 u8 uctx_cap[0x20]; 2056 2057 u8 reserved_at_6c0[0x4]; 2058 u8 flex_parser_id_geneve_tlv_option_0[0x4]; 2059 u8 flex_parser_id_icmp_dw1[0x4]; 2060 u8 flex_parser_id_icmp_dw0[0x4]; 2061 u8 flex_parser_id_icmpv6_dw1[0x4]; 2062 u8 flex_parser_id_icmpv6_dw0[0x4]; 2063 u8 flex_parser_id_outer_first_mpls_over_gre[0x4]; 2064 u8 flex_parser_id_outer_first_mpls_over_udp_label[0x4]; 2065 2066 u8 max_num_match_definer[0x10]; 2067 u8 sf_base_id[0x10]; 2068 2069 u8 flex_parser_id_gtpu_dw_2[0x4]; 2070 u8 flex_parser_id_gtpu_first_ext_dw_0[0x4]; 2071 u8 num_total_dynamic_vf_msix[0x18]; 2072 u8 reserved_at_720[0x14]; 2073 u8 dynamic_msix_table_size[0xc]; 2074 u8 reserved_at_740[0xc]; 2075 u8 min_dynamic_vf_msix_table_size[0x4]; 2076 u8 reserved_at_750[0x2]; 2077 u8 data_direct[0x1]; 2078 u8 reserved_at_753[0x1]; 2079 u8 max_dynamic_vf_msix_table_size[0xc]; 2080 2081 u8 reserved_at_760[0x3]; 2082 u8 log_max_num_header_modify_argument[0x5]; 2083 u8 log_header_modify_argument_granularity_offset[0x4]; 2084 u8 log_header_modify_argument_granularity[0x4]; 2085 u8 reserved_at_770[0x3]; 2086 u8 log_header_modify_argument_max_alloc[0x5]; 2087 u8 reserved_at_778[0x8]; 2088 2089 u8 vhca_tunnel_commands[0x40]; 2090 u8 match_definer_format_supported[0x40]; 2091 }; 2092 2093 enum { 2094 MLX5_CROSS_VHCA_OBJ_TO_OBJ_SUPPORTED_LOCAL_FLOW_TABLE_TO_REMOTE_FLOW_TABLE_MISS = 0x80000, 2095 MLX5_CROSS_VHCA_OBJ_TO_OBJ_SUPPORTED_LOCAL_FLOW_TABLE_ROOT_TO_REMOTE_FLOW_TABLE = (1ULL << 20), 2096 }; 2097 2098 enum { 2099 MLX5_ALLOWED_OBJ_FOR_OTHER_VHCA_ACCESS_FLOW_TABLE = 0x200, 2100 }; 2101 2102 struct mlx5_ifc_cmd_hca_cap_2_bits { 2103 u8 reserved_at_0[0x80]; 2104 2105 u8 migratable[0x1]; 2106 u8 reserved_at_81[0x7]; 2107 u8 dp_ordering_force[0x1]; 2108 u8 reserved_at_89[0x9]; 2109 u8 query_vuid[0x1]; 2110 u8 reserved_at_93[0x5]; 2111 u8 umr_log_entity_size_5[0x1]; 2112 u8 reserved_at_99[0x7]; 2113 2114 u8 max_reformat_insert_size[0x8]; 2115 u8 max_reformat_insert_offset[0x8]; 2116 u8 max_reformat_remove_size[0x8]; 2117 u8 max_reformat_remove_offset[0x8]; 2118 2119 u8 reserved_at_c0[0x8]; 2120 u8 migration_multi_load[0x1]; 2121 u8 migration_tracking_state[0x1]; 2122 u8 multiplane_qp_ud[0x1]; 2123 u8 reserved_at_cb[0x5]; 2124 u8 migration_in_chunks[0x1]; 2125 u8 reserved_at_d1[0x1]; 2126 u8 sf_eq_usage[0x1]; 2127 u8 reserved_at_d3[0x5]; 2128 u8 multiplane[0x1]; 2129 u8 reserved_at_d9[0x7]; 2130 2131 u8 cross_vhca_object_to_object_supported[0x20]; 2132 2133 u8 allowed_object_for_other_vhca_access[0x40]; 2134 2135 u8 reserved_at_140[0x60]; 2136 2137 u8 flow_table_type_2_type[0x8]; 2138 u8 reserved_at_1a8[0x2]; 2139 u8 format_select_dw_8_6_ext[0x1]; 2140 u8 log_min_mkey_entity_size[0x5]; 2141 u8 reserved_at_1b0[0x10]; 2142 2143 u8 reserved_at_1c0[0x60]; 2144 2145 u8 reserved_at_220[0x1]; 2146 u8 sw_vhca_id_valid[0x1]; 2147 u8 sw_vhca_id[0xe]; 2148 u8 reserved_at_230[0x10]; 2149 2150 u8 reserved_at_240[0xb]; 2151 u8 ts_cqe_metadata_size2wqe_counter[0x5]; 2152 u8 reserved_at_250[0x10]; 2153 2154 u8 reserved_at_260[0x20]; 2155 2156 u8 format_select_dw_gtpu_dw_0[0x8]; 2157 u8 format_select_dw_gtpu_dw_1[0x8]; 2158 u8 format_select_dw_gtpu_dw_2[0x8]; 2159 u8 format_select_dw_gtpu_first_ext_dw_0[0x8]; 2160 2161 u8 generate_wqe_type[0x20]; 2162 2163 u8 reserved_at_2c0[0xc0]; 2164 2165 u8 reserved_at_380[0xb]; 2166 u8 min_mkey_log_entity_size_fixed_buffer[0x5]; 2167 u8 ec_vf_vport_base[0x10]; 2168 2169 u8 reserved_at_3a0[0xa]; 2170 u8 max_mkey_log_entity_size_mtt[0x6]; 2171 u8 max_rqt_vhca_id[0x10]; 2172 2173 u8 reserved_at_3c0[0x20]; 2174 2175 u8 reserved_at_3e0[0x10]; 2176 u8 pcc_ifa2[0x1]; 2177 u8 reserved_at_3f1[0xf]; 2178 2179 u8 reserved_at_400[0x1]; 2180 u8 min_mkey_log_entity_size_fixed_buffer_valid[0x1]; 2181 u8 reserved_at_402[0xe]; 2182 u8 return_reg_id[0x10]; 2183 2184 u8 reserved_at_420[0x1c]; 2185 u8 flow_table_hash_type[0x4]; 2186 2187 u8 reserved_at_440[0x8]; 2188 u8 max_num_eqs_24b[0x18]; 2189 u8 reserved_at_460[0x3a0]; 2190 }; 2191 2192 enum mlx5_ifc_flow_destination_type { 2193 MLX5_IFC_FLOW_DESTINATION_TYPE_VPORT = 0x0, 2194 MLX5_IFC_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1, 2195 MLX5_IFC_FLOW_DESTINATION_TYPE_TIR = 0x2, 2196 MLX5_IFC_FLOW_DESTINATION_TYPE_FLOW_SAMPLER = 0x6, 2197 MLX5_IFC_FLOW_DESTINATION_TYPE_UPLINK = 0x8, 2198 MLX5_IFC_FLOW_DESTINATION_TYPE_TABLE_TYPE = 0xA, 2199 }; 2200 2201 enum mlx5_flow_table_miss_action { 2202 MLX5_FLOW_TABLE_MISS_ACTION_DEF, 2203 MLX5_FLOW_TABLE_MISS_ACTION_FWD, 2204 MLX5_FLOW_TABLE_MISS_ACTION_SWITCH_DOMAIN, 2205 }; 2206 2207 struct mlx5_ifc_dest_format_struct_bits { 2208 u8 destination_type[0x8]; 2209 u8 destination_id[0x18]; 2210 2211 u8 destination_eswitch_owner_vhca_id_valid[0x1]; 2212 u8 packet_reformat[0x1]; 2213 u8 reserved_at_22[0x6]; 2214 u8 destination_table_type[0x8]; 2215 u8 destination_eswitch_owner_vhca_id[0x10]; 2216 }; 2217 2218 struct mlx5_ifc_flow_counter_list_bits { 2219 u8 flow_counter_id[0x20]; 2220 2221 u8 reserved_at_20[0x20]; 2222 }; 2223 2224 struct mlx5_ifc_extended_dest_format_bits { 2225 struct mlx5_ifc_dest_format_struct_bits destination_entry; 2226 2227 u8 packet_reformat_id[0x20]; 2228 2229 u8 reserved_at_60[0x20]; 2230 }; 2231 2232 union mlx5_ifc_dest_format_flow_counter_list_auto_bits { 2233 struct mlx5_ifc_extended_dest_format_bits extended_dest_format; 2234 struct mlx5_ifc_flow_counter_list_bits flow_counter_list; 2235 }; 2236 2237 struct mlx5_ifc_fte_match_param_bits { 2238 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers; 2239 2240 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters; 2241 2242 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers; 2243 2244 struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2; 2245 2246 struct mlx5_ifc_fte_match_set_misc3_bits misc_parameters_3; 2247 2248 struct mlx5_ifc_fte_match_set_misc4_bits misc_parameters_4; 2249 2250 struct mlx5_ifc_fte_match_set_misc5_bits misc_parameters_5; 2251 2252 u8 reserved_at_e00[0x200]; 2253 }; 2254 2255 enum { 2256 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0, 2257 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1, 2258 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2, 2259 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3, 2260 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4, 2261 }; 2262 2263 struct mlx5_ifc_rx_hash_field_select_bits { 2264 u8 l3_prot_type[0x1]; 2265 u8 l4_prot_type[0x1]; 2266 u8 selected_fields[0x1e]; 2267 }; 2268 2269 enum { 2270 MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0, 2271 MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1, 2272 }; 2273 2274 enum { 2275 MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0, 2276 MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1, 2277 }; 2278 2279 struct mlx5_ifc_wq_bits { 2280 u8 wq_type[0x4]; 2281 u8 wq_signature[0x1]; 2282 u8 end_padding_mode[0x2]; 2283 u8 cd_slave[0x1]; 2284 u8 reserved_at_8[0x18]; 2285 2286 u8 hds_skip_first_sge[0x1]; 2287 u8 log2_hds_buf_size[0x3]; 2288 u8 reserved_at_24[0x7]; 2289 u8 page_offset[0x5]; 2290 u8 lwm[0x10]; 2291 2292 u8 reserved_at_40[0x8]; 2293 u8 pd[0x18]; 2294 2295 u8 reserved_at_60[0x8]; 2296 u8 uar_page[0x18]; 2297 2298 u8 dbr_addr[0x40]; 2299 2300 u8 hw_counter[0x20]; 2301 2302 u8 sw_counter[0x20]; 2303 2304 u8 reserved_at_100[0xc]; 2305 u8 log_wq_stride[0x4]; 2306 u8 reserved_at_110[0x3]; 2307 u8 log_wq_pg_sz[0x5]; 2308 u8 reserved_at_118[0x3]; 2309 u8 log_wq_sz[0x5]; 2310 2311 u8 dbr_umem_valid[0x1]; 2312 u8 wq_umem_valid[0x1]; 2313 u8 reserved_at_122[0x1]; 2314 u8 log_hairpin_num_packets[0x5]; 2315 u8 reserved_at_128[0x3]; 2316 u8 log_hairpin_data_sz[0x5]; 2317 2318 u8 reserved_at_130[0x4]; 2319 u8 log_wqe_num_of_strides[0x4]; 2320 u8 two_byte_shift_en[0x1]; 2321 u8 reserved_at_139[0x4]; 2322 u8 log_wqe_stride_size[0x3]; 2323 2324 u8 dbr_umem_id[0x20]; 2325 u8 wq_umem_id[0x20]; 2326 2327 u8 wq_umem_offset[0x40]; 2328 2329 u8 headers_mkey[0x20]; 2330 2331 u8 shampo_enable[0x1]; 2332 u8 reserved_at_1e1[0x4]; 2333 u8 log_reservation_size[0x3]; 2334 u8 reserved_at_1e8[0x5]; 2335 u8 log_max_num_of_packets_per_reservation[0x3]; 2336 u8 reserved_at_1f0[0x6]; 2337 u8 log_headers_entry_size[0x2]; 2338 u8 reserved_at_1f8[0x4]; 2339 u8 log_headers_buffer_entry_num[0x4]; 2340 2341 u8 reserved_at_200[0x400]; 2342 2343 struct mlx5_ifc_cmd_pas_bits pas[]; 2344 }; 2345 2346 struct mlx5_ifc_rq_num_bits { 2347 u8 reserved_at_0[0x8]; 2348 u8 rq_num[0x18]; 2349 }; 2350 2351 struct mlx5_ifc_rq_vhca_bits { 2352 u8 reserved_at_0[0x8]; 2353 u8 rq_num[0x18]; 2354 u8 reserved_at_20[0x10]; 2355 u8 rq_vhca_id[0x10]; 2356 }; 2357 2358 struct mlx5_ifc_mac_address_layout_bits { 2359 u8 reserved_at_0[0x10]; 2360 u8 mac_addr_47_32[0x10]; 2361 2362 u8 mac_addr_31_0[0x20]; 2363 }; 2364 2365 struct mlx5_ifc_vlan_layout_bits { 2366 u8 reserved_at_0[0x14]; 2367 u8 vlan[0x0c]; 2368 2369 u8 reserved_at_20[0x20]; 2370 }; 2371 2372 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits { 2373 u8 reserved_at_0[0xa0]; 2374 2375 u8 min_time_between_cnps[0x20]; 2376 2377 u8 reserved_at_c0[0x12]; 2378 u8 cnp_dscp[0x6]; 2379 u8 reserved_at_d8[0x4]; 2380 u8 cnp_prio_mode[0x1]; 2381 u8 cnp_802p_prio[0x3]; 2382 2383 u8 reserved_at_e0[0x720]; 2384 }; 2385 2386 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits { 2387 u8 reserved_at_0[0x60]; 2388 2389 u8 reserved_at_60[0x4]; 2390 u8 clamp_tgt_rate[0x1]; 2391 u8 reserved_at_65[0x3]; 2392 u8 clamp_tgt_rate_after_time_inc[0x1]; 2393 u8 reserved_at_69[0x17]; 2394 2395 u8 reserved_at_80[0x20]; 2396 2397 u8 rpg_time_reset[0x20]; 2398 2399 u8 rpg_byte_reset[0x20]; 2400 2401 u8 rpg_threshold[0x20]; 2402 2403 u8 rpg_max_rate[0x20]; 2404 2405 u8 rpg_ai_rate[0x20]; 2406 2407 u8 rpg_hai_rate[0x20]; 2408 2409 u8 rpg_gd[0x20]; 2410 2411 u8 rpg_min_dec_fac[0x20]; 2412 2413 u8 rpg_min_rate[0x20]; 2414 2415 u8 reserved_at_1c0[0xe0]; 2416 2417 u8 rate_to_set_on_first_cnp[0x20]; 2418 2419 u8 dce_tcp_g[0x20]; 2420 2421 u8 dce_tcp_rtt[0x20]; 2422 2423 u8 rate_reduce_monitor_period[0x20]; 2424 2425 u8 reserved_at_320[0x20]; 2426 2427 u8 initial_alpha_value[0x20]; 2428 2429 u8 reserved_at_360[0x4a0]; 2430 }; 2431 2432 struct mlx5_ifc_cong_control_r_roce_general_bits { 2433 u8 reserved_at_0[0x80]; 2434 2435 u8 reserved_at_80[0x10]; 2436 u8 rtt_resp_dscp_valid[0x1]; 2437 u8 reserved_at_91[0x9]; 2438 u8 rtt_resp_dscp[0x6]; 2439 2440 u8 reserved_at_a0[0x760]; 2441 }; 2442 2443 struct mlx5_ifc_cong_control_802_1qau_rp_bits { 2444 u8 reserved_at_0[0x80]; 2445 2446 u8 rppp_max_rps[0x20]; 2447 2448 u8 rpg_time_reset[0x20]; 2449 2450 u8 rpg_byte_reset[0x20]; 2451 2452 u8 rpg_threshold[0x20]; 2453 2454 u8 rpg_max_rate[0x20]; 2455 2456 u8 rpg_ai_rate[0x20]; 2457 2458 u8 rpg_hai_rate[0x20]; 2459 2460 u8 rpg_gd[0x20]; 2461 2462 u8 rpg_min_dec_fac[0x20]; 2463 2464 u8 rpg_min_rate[0x20]; 2465 2466 u8 reserved_at_1c0[0x640]; 2467 }; 2468 2469 enum { 2470 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1, 2471 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2, 2472 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4, 2473 }; 2474 2475 struct mlx5_ifc_resize_field_select_bits { 2476 u8 resize_field_select[0x20]; 2477 }; 2478 2479 struct mlx5_ifc_resource_dump_bits { 2480 u8 more_dump[0x1]; 2481 u8 inline_dump[0x1]; 2482 u8 reserved_at_2[0xa]; 2483 u8 seq_num[0x4]; 2484 u8 segment_type[0x10]; 2485 2486 u8 reserved_at_20[0x10]; 2487 u8 vhca_id[0x10]; 2488 2489 u8 index1[0x20]; 2490 2491 u8 index2[0x20]; 2492 2493 u8 num_of_obj1[0x10]; 2494 u8 num_of_obj2[0x10]; 2495 2496 u8 reserved_at_a0[0x20]; 2497 2498 u8 device_opaque[0x40]; 2499 2500 u8 mkey[0x20]; 2501 2502 u8 size[0x20]; 2503 2504 u8 address[0x40]; 2505 2506 u8 inline_data[52][0x20]; 2507 }; 2508 2509 struct mlx5_ifc_resource_dump_menu_record_bits { 2510 u8 reserved_at_0[0x4]; 2511 u8 num_of_obj2_supports_active[0x1]; 2512 u8 num_of_obj2_supports_all[0x1]; 2513 u8 must_have_num_of_obj2[0x1]; 2514 u8 support_num_of_obj2[0x1]; 2515 u8 num_of_obj1_supports_active[0x1]; 2516 u8 num_of_obj1_supports_all[0x1]; 2517 u8 must_have_num_of_obj1[0x1]; 2518 u8 support_num_of_obj1[0x1]; 2519 u8 must_have_index2[0x1]; 2520 u8 support_index2[0x1]; 2521 u8 must_have_index1[0x1]; 2522 u8 support_index1[0x1]; 2523 u8 segment_type[0x10]; 2524 2525 u8 segment_name[4][0x20]; 2526 2527 u8 index1_name[4][0x20]; 2528 2529 u8 index2_name[4][0x20]; 2530 }; 2531 2532 struct mlx5_ifc_resource_dump_segment_header_bits { 2533 u8 length_dw[0x10]; 2534 u8 segment_type[0x10]; 2535 }; 2536 2537 struct mlx5_ifc_resource_dump_command_segment_bits { 2538 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2539 2540 u8 segment_called[0x10]; 2541 u8 vhca_id[0x10]; 2542 2543 u8 index1[0x20]; 2544 2545 u8 index2[0x20]; 2546 2547 u8 num_of_obj1[0x10]; 2548 u8 num_of_obj2[0x10]; 2549 }; 2550 2551 struct mlx5_ifc_resource_dump_error_segment_bits { 2552 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2553 2554 u8 reserved_at_20[0x10]; 2555 u8 syndrome_id[0x10]; 2556 2557 u8 reserved_at_40[0x40]; 2558 2559 u8 error[8][0x20]; 2560 }; 2561 2562 struct mlx5_ifc_resource_dump_info_segment_bits { 2563 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2564 2565 u8 reserved_at_20[0x18]; 2566 u8 dump_version[0x8]; 2567 2568 u8 hw_version[0x20]; 2569 2570 u8 fw_version[0x20]; 2571 }; 2572 2573 struct mlx5_ifc_resource_dump_menu_segment_bits { 2574 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2575 2576 u8 reserved_at_20[0x10]; 2577 u8 num_of_records[0x10]; 2578 2579 struct mlx5_ifc_resource_dump_menu_record_bits record[]; 2580 }; 2581 2582 struct mlx5_ifc_resource_dump_resource_segment_bits { 2583 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2584 2585 u8 reserved_at_20[0x20]; 2586 2587 u8 index1[0x20]; 2588 2589 u8 index2[0x20]; 2590 2591 u8 payload[][0x20]; 2592 }; 2593 2594 struct mlx5_ifc_resource_dump_terminate_segment_bits { 2595 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2596 }; 2597 2598 struct mlx5_ifc_menu_resource_dump_response_bits { 2599 struct mlx5_ifc_resource_dump_info_segment_bits info; 2600 struct mlx5_ifc_resource_dump_command_segment_bits cmd; 2601 struct mlx5_ifc_resource_dump_menu_segment_bits menu; 2602 struct mlx5_ifc_resource_dump_terminate_segment_bits terminate; 2603 }; 2604 2605 enum { 2606 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1, 2607 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2, 2608 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4, 2609 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8, 2610 }; 2611 2612 struct mlx5_ifc_modify_field_select_bits { 2613 u8 modify_field_select[0x20]; 2614 }; 2615 2616 struct mlx5_ifc_field_select_r_roce_np_bits { 2617 u8 field_select_r_roce_np[0x20]; 2618 }; 2619 2620 struct mlx5_ifc_field_select_r_roce_rp_bits { 2621 u8 field_select_r_roce_rp[0x20]; 2622 }; 2623 2624 enum { 2625 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4, 2626 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8, 2627 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10, 2628 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20, 2629 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40, 2630 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80, 2631 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100, 2632 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200, 2633 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400, 2634 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800, 2635 }; 2636 2637 struct mlx5_ifc_field_select_802_1qau_rp_bits { 2638 u8 field_select_8021qaurp[0x20]; 2639 }; 2640 2641 struct mlx5_ifc_phys_layer_cntrs_bits { 2642 u8 time_since_last_clear_high[0x20]; 2643 2644 u8 time_since_last_clear_low[0x20]; 2645 2646 u8 symbol_errors_high[0x20]; 2647 2648 u8 symbol_errors_low[0x20]; 2649 2650 u8 sync_headers_errors_high[0x20]; 2651 2652 u8 sync_headers_errors_low[0x20]; 2653 2654 u8 edpl_bip_errors_lane0_high[0x20]; 2655 2656 u8 edpl_bip_errors_lane0_low[0x20]; 2657 2658 u8 edpl_bip_errors_lane1_high[0x20]; 2659 2660 u8 edpl_bip_errors_lane1_low[0x20]; 2661 2662 u8 edpl_bip_errors_lane2_high[0x20]; 2663 2664 u8 edpl_bip_errors_lane2_low[0x20]; 2665 2666 u8 edpl_bip_errors_lane3_high[0x20]; 2667 2668 u8 edpl_bip_errors_lane3_low[0x20]; 2669 2670 u8 fc_fec_corrected_blocks_lane0_high[0x20]; 2671 2672 u8 fc_fec_corrected_blocks_lane0_low[0x20]; 2673 2674 u8 fc_fec_corrected_blocks_lane1_high[0x20]; 2675 2676 u8 fc_fec_corrected_blocks_lane1_low[0x20]; 2677 2678 u8 fc_fec_corrected_blocks_lane2_high[0x20]; 2679 2680 u8 fc_fec_corrected_blocks_lane2_low[0x20]; 2681 2682 u8 fc_fec_corrected_blocks_lane3_high[0x20]; 2683 2684 u8 fc_fec_corrected_blocks_lane3_low[0x20]; 2685 2686 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20]; 2687 2688 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20]; 2689 2690 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20]; 2691 2692 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20]; 2693 2694 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20]; 2695 2696 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20]; 2697 2698 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20]; 2699 2700 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20]; 2701 2702 u8 rs_fec_corrected_blocks_high[0x20]; 2703 2704 u8 rs_fec_corrected_blocks_low[0x20]; 2705 2706 u8 rs_fec_uncorrectable_blocks_high[0x20]; 2707 2708 u8 rs_fec_uncorrectable_blocks_low[0x20]; 2709 2710 u8 rs_fec_no_errors_blocks_high[0x20]; 2711 2712 u8 rs_fec_no_errors_blocks_low[0x20]; 2713 2714 u8 rs_fec_single_error_blocks_high[0x20]; 2715 2716 u8 rs_fec_single_error_blocks_low[0x20]; 2717 2718 u8 rs_fec_corrected_symbols_total_high[0x20]; 2719 2720 u8 rs_fec_corrected_symbols_total_low[0x20]; 2721 2722 u8 rs_fec_corrected_symbols_lane0_high[0x20]; 2723 2724 u8 rs_fec_corrected_symbols_lane0_low[0x20]; 2725 2726 u8 rs_fec_corrected_symbols_lane1_high[0x20]; 2727 2728 u8 rs_fec_corrected_symbols_lane1_low[0x20]; 2729 2730 u8 rs_fec_corrected_symbols_lane2_high[0x20]; 2731 2732 u8 rs_fec_corrected_symbols_lane2_low[0x20]; 2733 2734 u8 rs_fec_corrected_symbols_lane3_high[0x20]; 2735 2736 u8 rs_fec_corrected_symbols_lane3_low[0x20]; 2737 2738 u8 link_down_events[0x20]; 2739 2740 u8 successful_recovery_events[0x20]; 2741 2742 u8 reserved_at_640[0x180]; 2743 }; 2744 2745 struct mlx5_ifc_phys_layer_statistical_cntrs_bits { 2746 u8 time_since_last_clear_high[0x20]; 2747 2748 u8 time_since_last_clear_low[0x20]; 2749 2750 u8 phy_received_bits_high[0x20]; 2751 2752 u8 phy_received_bits_low[0x20]; 2753 2754 u8 phy_symbol_errors_high[0x20]; 2755 2756 u8 phy_symbol_errors_low[0x20]; 2757 2758 u8 phy_corrected_bits_high[0x20]; 2759 2760 u8 phy_corrected_bits_low[0x20]; 2761 2762 u8 phy_corrected_bits_lane0_high[0x20]; 2763 2764 u8 phy_corrected_bits_lane0_low[0x20]; 2765 2766 u8 phy_corrected_bits_lane1_high[0x20]; 2767 2768 u8 phy_corrected_bits_lane1_low[0x20]; 2769 2770 u8 phy_corrected_bits_lane2_high[0x20]; 2771 2772 u8 phy_corrected_bits_lane2_low[0x20]; 2773 2774 u8 phy_corrected_bits_lane3_high[0x20]; 2775 2776 u8 phy_corrected_bits_lane3_low[0x20]; 2777 2778 u8 reserved_at_200[0x5c0]; 2779 }; 2780 2781 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits { 2782 u8 symbol_error_counter[0x10]; 2783 2784 u8 link_error_recovery_counter[0x8]; 2785 2786 u8 link_downed_counter[0x8]; 2787 2788 u8 port_rcv_errors[0x10]; 2789 2790 u8 port_rcv_remote_physical_errors[0x10]; 2791 2792 u8 port_rcv_switch_relay_errors[0x10]; 2793 2794 u8 port_xmit_discards[0x10]; 2795 2796 u8 port_xmit_constraint_errors[0x8]; 2797 2798 u8 port_rcv_constraint_errors[0x8]; 2799 2800 u8 reserved_at_70[0x8]; 2801 2802 u8 link_overrun_errors[0x8]; 2803 2804 u8 reserved_at_80[0x10]; 2805 2806 u8 vl_15_dropped[0x10]; 2807 2808 u8 reserved_at_a0[0x80]; 2809 2810 u8 port_xmit_wait[0x20]; 2811 }; 2812 2813 struct mlx5_ifc_ib_ext_port_cntrs_grp_data_layout_bits { 2814 u8 reserved_at_0[0x300]; 2815 2816 u8 port_xmit_data_high[0x20]; 2817 2818 u8 port_xmit_data_low[0x20]; 2819 2820 u8 port_rcv_data_high[0x20]; 2821 2822 u8 port_rcv_data_low[0x20]; 2823 2824 u8 port_xmit_pkts_high[0x20]; 2825 2826 u8 port_xmit_pkts_low[0x20]; 2827 2828 u8 port_rcv_pkts_high[0x20]; 2829 2830 u8 port_rcv_pkts_low[0x20]; 2831 2832 u8 reserved_at_400[0x80]; 2833 2834 u8 port_unicast_xmit_pkts_high[0x20]; 2835 2836 u8 port_unicast_xmit_pkts_low[0x20]; 2837 2838 u8 port_multicast_xmit_pkts_high[0x20]; 2839 2840 u8 port_multicast_xmit_pkts_low[0x20]; 2841 2842 u8 port_unicast_rcv_pkts_high[0x20]; 2843 2844 u8 port_unicast_rcv_pkts_low[0x20]; 2845 2846 u8 port_multicast_rcv_pkts_high[0x20]; 2847 2848 u8 port_multicast_rcv_pkts_low[0x20]; 2849 2850 u8 reserved_at_580[0x240]; 2851 }; 2852 2853 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits { 2854 u8 transmit_queue_high[0x20]; 2855 2856 u8 transmit_queue_low[0x20]; 2857 2858 u8 no_buffer_discard_uc_high[0x20]; 2859 2860 u8 no_buffer_discard_uc_low[0x20]; 2861 2862 u8 reserved_at_80[0x740]; 2863 }; 2864 2865 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits { 2866 u8 wred_discard_high[0x20]; 2867 2868 u8 wred_discard_low[0x20]; 2869 2870 u8 ecn_marked_tc_high[0x20]; 2871 2872 u8 ecn_marked_tc_low[0x20]; 2873 2874 u8 reserved_at_80[0x740]; 2875 }; 2876 2877 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits { 2878 u8 rx_octets_high[0x20]; 2879 2880 u8 rx_octets_low[0x20]; 2881 2882 u8 reserved_at_40[0xc0]; 2883 2884 u8 rx_frames_high[0x20]; 2885 2886 u8 rx_frames_low[0x20]; 2887 2888 u8 tx_octets_high[0x20]; 2889 2890 u8 tx_octets_low[0x20]; 2891 2892 u8 reserved_at_180[0xc0]; 2893 2894 u8 tx_frames_high[0x20]; 2895 2896 u8 tx_frames_low[0x20]; 2897 2898 u8 rx_pause_high[0x20]; 2899 2900 u8 rx_pause_low[0x20]; 2901 2902 u8 rx_pause_duration_high[0x20]; 2903 2904 u8 rx_pause_duration_low[0x20]; 2905 2906 u8 tx_pause_high[0x20]; 2907 2908 u8 tx_pause_low[0x20]; 2909 2910 u8 tx_pause_duration_high[0x20]; 2911 2912 u8 tx_pause_duration_low[0x20]; 2913 2914 u8 rx_pause_transition_high[0x20]; 2915 2916 u8 rx_pause_transition_low[0x20]; 2917 2918 u8 rx_discards_high[0x20]; 2919 2920 u8 rx_discards_low[0x20]; 2921 2922 u8 device_stall_minor_watermark_cnt_high[0x20]; 2923 2924 u8 device_stall_minor_watermark_cnt_low[0x20]; 2925 2926 u8 device_stall_critical_watermark_cnt_high[0x20]; 2927 2928 u8 device_stall_critical_watermark_cnt_low[0x20]; 2929 2930 u8 reserved_at_480[0x340]; 2931 }; 2932 2933 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits { 2934 u8 port_transmit_wait_high[0x20]; 2935 2936 u8 port_transmit_wait_low[0x20]; 2937 2938 u8 reserved_at_40[0x100]; 2939 2940 u8 rx_buffer_almost_full_high[0x20]; 2941 2942 u8 rx_buffer_almost_full_low[0x20]; 2943 2944 u8 rx_buffer_full_high[0x20]; 2945 2946 u8 rx_buffer_full_low[0x20]; 2947 2948 u8 rx_icrc_encapsulated_high[0x20]; 2949 2950 u8 rx_icrc_encapsulated_low[0x20]; 2951 2952 u8 reserved_at_200[0x5c0]; 2953 }; 2954 2955 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits { 2956 u8 dot3stats_alignment_errors_high[0x20]; 2957 2958 u8 dot3stats_alignment_errors_low[0x20]; 2959 2960 u8 dot3stats_fcs_errors_high[0x20]; 2961 2962 u8 dot3stats_fcs_errors_low[0x20]; 2963 2964 u8 dot3stats_single_collision_frames_high[0x20]; 2965 2966 u8 dot3stats_single_collision_frames_low[0x20]; 2967 2968 u8 dot3stats_multiple_collision_frames_high[0x20]; 2969 2970 u8 dot3stats_multiple_collision_frames_low[0x20]; 2971 2972 u8 dot3stats_sqe_test_errors_high[0x20]; 2973 2974 u8 dot3stats_sqe_test_errors_low[0x20]; 2975 2976 u8 dot3stats_deferred_transmissions_high[0x20]; 2977 2978 u8 dot3stats_deferred_transmissions_low[0x20]; 2979 2980 u8 dot3stats_late_collisions_high[0x20]; 2981 2982 u8 dot3stats_late_collisions_low[0x20]; 2983 2984 u8 dot3stats_excessive_collisions_high[0x20]; 2985 2986 u8 dot3stats_excessive_collisions_low[0x20]; 2987 2988 u8 dot3stats_internal_mac_transmit_errors_high[0x20]; 2989 2990 u8 dot3stats_internal_mac_transmit_errors_low[0x20]; 2991 2992 u8 dot3stats_carrier_sense_errors_high[0x20]; 2993 2994 u8 dot3stats_carrier_sense_errors_low[0x20]; 2995 2996 u8 dot3stats_frame_too_longs_high[0x20]; 2997 2998 u8 dot3stats_frame_too_longs_low[0x20]; 2999 3000 u8 dot3stats_internal_mac_receive_errors_high[0x20]; 3001 3002 u8 dot3stats_internal_mac_receive_errors_low[0x20]; 3003 3004 u8 dot3stats_symbol_errors_high[0x20]; 3005 3006 u8 dot3stats_symbol_errors_low[0x20]; 3007 3008 u8 dot3control_in_unknown_opcodes_high[0x20]; 3009 3010 u8 dot3control_in_unknown_opcodes_low[0x20]; 3011 3012 u8 dot3in_pause_frames_high[0x20]; 3013 3014 u8 dot3in_pause_frames_low[0x20]; 3015 3016 u8 dot3out_pause_frames_high[0x20]; 3017 3018 u8 dot3out_pause_frames_low[0x20]; 3019 3020 u8 reserved_at_400[0x3c0]; 3021 }; 3022 3023 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits { 3024 u8 ether_stats_drop_events_high[0x20]; 3025 3026 u8 ether_stats_drop_events_low[0x20]; 3027 3028 u8 ether_stats_octets_high[0x20]; 3029 3030 u8 ether_stats_octets_low[0x20]; 3031 3032 u8 ether_stats_pkts_high[0x20]; 3033 3034 u8 ether_stats_pkts_low[0x20]; 3035 3036 u8 ether_stats_broadcast_pkts_high[0x20]; 3037 3038 u8 ether_stats_broadcast_pkts_low[0x20]; 3039 3040 u8 ether_stats_multicast_pkts_high[0x20]; 3041 3042 u8 ether_stats_multicast_pkts_low[0x20]; 3043 3044 u8 ether_stats_crc_align_errors_high[0x20]; 3045 3046 u8 ether_stats_crc_align_errors_low[0x20]; 3047 3048 u8 ether_stats_undersize_pkts_high[0x20]; 3049 3050 u8 ether_stats_undersize_pkts_low[0x20]; 3051 3052 u8 ether_stats_oversize_pkts_high[0x20]; 3053 3054 u8 ether_stats_oversize_pkts_low[0x20]; 3055 3056 u8 ether_stats_fragments_high[0x20]; 3057 3058 u8 ether_stats_fragments_low[0x20]; 3059 3060 u8 ether_stats_jabbers_high[0x20]; 3061 3062 u8 ether_stats_jabbers_low[0x20]; 3063 3064 u8 ether_stats_collisions_high[0x20]; 3065 3066 u8 ether_stats_collisions_low[0x20]; 3067 3068 u8 ether_stats_pkts64octets_high[0x20]; 3069 3070 u8 ether_stats_pkts64octets_low[0x20]; 3071 3072 u8 ether_stats_pkts65to127octets_high[0x20]; 3073 3074 u8 ether_stats_pkts65to127octets_low[0x20]; 3075 3076 u8 ether_stats_pkts128to255octets_high[0x20]; 3077 3078 u8 ether_stats_pkts128to255octets_low[0x20]; 3079 3080 u8 ether_stats_pkts256to511octets_high[0x20]; 3081 3082 u8 ether_stats_pkts256to511octets_low[0x20]; 3083 3084 u8 ether_stats_pkts512to1023octets_high[0x20]; 3085 3086 u8 ether_stats_pkts512to1023octets_low[0x20]; 3087 3088 u8 ether_stats_pkts1024to1518octets_high[0x20]; 3089 3090 u8 ether_stats_pkts1024to1518octets_low[0x20]; 3091 3092 u8 ether_stats_pkts1519to2047octets_high[0x20]; 3093 3094 u8 ether_stats_pkts1519to2047octets_low[0x20]; 3095 3096 u8 ether_stats_pkts2048to4095octets_high[0x20]; 3097 3098 u8 ether_stats_pkts2048to4095octets_low[0x20]; 3099 3100 u8 ether_stats_pkts4096to8191octets_high[0x20]; 3101 3102 u8 ether_stats_pkts4096to8191octets_low[0x20]; 3103 3104 u8 ether_stats_pkts8192to10239octets_high[0x20]; 3105 3106 u8 ether_stats_pkts8192to10239octets_low[0x20]; 3107 3108 u8 reserved_at_540[0x280]; 3109 }; 3110 3111 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits { 3112 u8 if_in_octets_high[0x20]; 3113 3114 u8 if_in_octets_low[0x20]; 3115 3116 u8 if_in_ucast_pkts_high[0x20]; 3117 3118 u8 if_in_ucast_pkts_low[0x20]; 3119 3120 u8 if_in_discards_high[0x20]; 3121 3122 u8 if_in_discards_low[0x20]; 3123 3124 u8 if_in_errors_high[0x20]; 3125 3126 u8 if_in_errors_low[0x20]; 3127 3128 u8 if_in_unknown_protos_high[0x20]; 3129 3130 u8 if_in_unknown_protos_low[0x20]; 3131 3132 u8 if_out_octets_high[0x20]; 3133 3134 u8 if_out_octets_low[0x20]; 3135 3136 u8 if_out_ucast_pkts_high[0x20]; 3137 3138 u8 if_out_ucast_pkts_low[0x20]; 3139 3140 u8 if_out_discards_high[0x20]; 3141 3142 u8 if_out_discards_low[0x20]; 3143 3144 u8 if_out_errors_high[0x20]; 3145 3146 u8 if_out_errors_low[0x20]; 3147 3148 u8 if_in_multicast_pkts_high[0x20]; 3149 3150 u8 if_in_multicast_pkts_low[0x20]; 3151 3152 u8 if_in_broadcast_pkts_high[0x20]; 3153 3154 u8 if_in_broadcast_pkts_low[0x20]; 3155 3156 u8 if_out_multicast_pkts_high[0x20]; 3157 3158 u8 if_out_multicast_pkts_low[0x20]; 3159 3160 u8 if_out_broadcast_pkts_high[0x20]; 3161 3162 u8 if_out_broadcast_pkts_low[0x20]; 3163 3164 u8 reserved_at_340[0x480]; 3165 }; 3166 3167 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits { 3168 u8 a_frames_transmitted_ok_high[0x20]; 3169 3170 u8 a_frames_transmitted_ok_low[0x20]; 3171 3172 u8 a_frames_received_ok_high[0x20]; 3173 3174 u8 a_frames_received_ok_low[0x20]; 3175 3176 u8 a_frame_check_sequence_errors_high[0x20]; 3177 3178 u8 a_frame_check_sequence_errors_low[0x20]; 3179 3180 u8 a_alignment_errors_high[0x20]; 3181 3182 u8 a_alignment_errors_low[0x20]; 3183 3184 u8 a_octets_transmitted_ok_high[0x20]; 3185 3186 u8 a_octets_transmitted_ok_low[0x20]; 3187 3188 u8 a_octets_received_ok_high[0x20]; 3189 3190 u8 a_octets_received_ok_low[0x20]; 3191 3192 u8 a_multicast_frames_xmitted_ok_high[0x20]; 3193 3194 u8 a_multicast_frames_xmitted_ok_low[0x20]; 3195 3196 u8 a_broadcast_frames_xmitted_ok_high[0x20]; 3197 3198 u8 a_broadcast_frames_xmitted_ok_low[0x20]; 3199 3200 u8 a_multicast_frames_received_ok_high[0x20]; 3201 3202 u8 a_multicast_frames_received_ok_low[0x20]; 3203 3204 u8 a_broadcast_frames_received_ok_high[0x20]; 3205 3206 u8 a_broadcast_frames_received_ok_low[0x20]; 3207 3208 u8 a_in_range_length_errors_high[0x20]; 3209 3210 u8 a_in_range_length_errors_low[0x20]; 3211 3212 u8 a_out_of_range_length_field_high[0x20]; 3213 3214 u8 a_out_of_range_length_field_low[0x20]; 3215 3216 u8 a_frame_too_long_errors_high[0x20]; 3217 3218 u8 a_frame_too_long_errors_low[0x20]; 3219 3220 u8 a_symbol_error_during_carrier_high[0x20]; 3221 3222 u8 a_symbol_error_during_carrier_low[0x20]; 3223 3224 u8 a_mac_control_frames_transmitted_high[0x20]; 3225 3226 u8 a_mac_control_frames_transmitted_low[0x20]; 3227 3228 u8 a_mac_control_frames_received_high[0x20]; 3229 3230 u8 a_mac_control_frames_received_low[0x20]; 3231 3232 u8 a_unsupported_opcodes_received_high[0x20]; 3233 3234 u8 a_unsupported_opcodes_received_low[0x20]; 3235 3236 u8 a_pause_mac_ctrl_frames_received_high[0x20]; 3237 3238 u8 a_pause_mac_ctrl_frames_received_low[0x20]; 3239 3240 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20]; 3241 3242 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20]; 3243 3244 u8 reserved_at_4c0[0x300]; 3245 }; 3246 3247 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits { 3248 u8 life_time_counter_high[0x20]; 3249 3250 u8 life_time_counter_low[0x20]; 3251 3252 u8 rx_errors[0x20]; 3253 3254 u8 tx_errors[0x20]; 3255 3256 u8 l0_to_recovery_eieos[0x20]; 3257 3258 u8 l0_to_recovery_ts[0x20]; 3259 3260 u8 l0_to_recovery_framing[0x20]; 3261 3262 u8 l0_to_recovery_retrain[0x20]; 3263 3264 u8 crc_error_dllp[0x20]; 3265 3266 u8 crc_error_tlp[0x20]; 3267 3268 u8 tx_overflow_buffer_pkt_high[0x20]; 3269 3270 u8 tx_overflow_buffer_pkt_low[0x20]; 3271 3272 u8 outbound_stalled_reads[0x20]; 3273 3274 u8 outbound_stalled_writes[0x20]; 3275 3276 u8 outbound_stalled_reads_events[0x20]; 3277 3278 u8 outbound_stalled_writes_events[0x20]; 3279 3280 u8 reserved_at_200[0x5c0]; 3281 }; 3282 3283 struct mlx5_ifc_cmd_inter_comp_event_bits { 3284 u8 command_completion_vector[0x20]; 3285 3286 u8 reserved_at_20[0xc0]; 3287 }; 3288 3289 struct mlx5_ifc_stall_vl_event_bits { 3290 u8 reserved_at_0[0x18]; 3291 u8 port_num[0x1]; 3292 u8 reserved_at_19[0x3]; 3293 u8 vl[0x4]; 3294 3295 u8 reserved_at_20[0xa0]; 3296 }; 3297 3298 struct mlx5_ifc_db_bf_congestion_event_bits { 3299 u8 event_subtype[0x8]; 3300 u8 reserved_at_8[0x8]; 3301 u8 congestion_level[0x8]; 3302 u8 reserved_at_18[0x8]; 3303 3304 u8 reserved_at_20[0xa0]; 3305 }; 3306 3307 struct mlx5_ifc_gpio_event_bits { 3308 u8 reserved_at_0[0x60]; 3309 3310 u8 gpio_event_hi[0x20]; 3311 3312 u8 gpio_event_lo[0x20]; 3313 3314 u8 reserved_at_a0[0x40]; 3315 }; 3316 3317 struct mlx5_ifc_port_state_change_event_bits { 3318 u8 reserved_at_0[0x40]; 3319 3320 u8 port_num[0x4]; 3321 u8 reserved_at_44[0x1c]; 3322 3323 u8 reserved_at_60[0x80]; 3324 }; 3325 3326 struct mlx5_ifc_dropped_packet_logged_bits { 3327 u8 reserved_at_0[0xe0]; 3328 }; 3329 3330 struct mlx5_ifc_default_timeout_bits { 3331 u8 to_multiplier[0x3]; 3332 u8 reserved_at_3[0x9]; 3333 u8 to_value[0x14]; 3334 }; 3335 3336 struct mlx5_ifc_dtor_reg_bits { 3337 u8 reserved_at_0[0x20]; 3338 3339 struct mlx5_ifc_default_timeout_bits pcie_toggle_to; 3340 3341 u8 reserved_at_40[0x60]; 3342 3343 struct mlx5_ifc_default_timeout_bits health_poll_to; 3344 3345 struct mlx5_ifc_default_timeout_bits full_crdump_to; 3346 3347 struct mlx5_ifc_default_timeout_bits fw_reset_to; 3348 3349 struct mlx5_ifc_default_timeout_bits flush_on_err_to; 3350 3351 struct mlx5_ifc_default_timeout_bits pci_sync_update_to; 3352 3353 struct mlx5_ifc_default_timeout_bits tear_down_to; 3354 3355 struct mlx5_ifc_default_timeout_bits fsm_reactivate_to; 3356 3357 struct mlx5_ifc_default_timeout_bits reclaim_pages_to; 3358 3359 struct mlx5_ifc_default_timeout_bits reclaim_vfs_pages_to; 3360 3361 struct mlx5_ifc_default_timeout_bits reset_unload_to; 3362 3363 u8 reserved_at_1c0[0x20]; 3364 }; 3365 3366 enum { 3367 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1, 3368 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2, 3369 }; 3370 3371 struct mlx5_ifc_cq_error_bits { 3372 u8 reserved_at_0[0x8]; 3373 u8 cqn[0x18]; 3374 3375 u8 reserved_at_20[0x20]; 3376 3377 u8 reserved_at_40[0x18]; 3378 u8 syndrome[0x8]; 3379 3380 u8 reserved_at_60[0x80]; 3381 }; 3382 3383 struct mlx5_ifc_rdma_page_fault_event_bits { 3384 u8 bytes_committed[0x20]; 3385 3386 u8 r_key[0x20]; 3387 3388 u8 reserved_at_40[0x10]; 3389 u8 packet_len[0x10]; 3390 3391 u8 rdma_op_len[0x20]; 3392 3393 u8 rdma_va[0x40]; 3394 3395 u8 reserved_at_c0[0x5]; 3396 u8 rdma[0x1]; 3397 u8 write[0x1]; 3398 u8 requestor[0x1]; 3399 u8 qp_number[0x18]; 3400 }; 3401 3402 struct mlx5_ifc_wqe_associated_page_fault_event_bits { 3403 u8 bytes_committed[0x20]; 3404 3405 u8 reserved_at_20[0x10]; 3406 u8 wqe_index[0x10]; 3407 3408 u8 reserved_at_40[0x10]; 3409 u8 len[0x10]; 3410 3411 u8 reserved_at_60[0x60]; 3412 3413 u8 reserved_at_c0[0x5]; 3414 u8 rdma[0x1]; 3415 u8 write_read[0x1]; 3416 u8 requestor[0x1]; 3417 u8 qpn[0x18]; 3418 }; 3419 3420 struct mlx5_ifc_qp_events_bits { 3421 u8 reserved_at_0[0xa0]; 3422 3423 u8 type[0x8]; 3424 u8 reserved_at_a8[0x18]; 3425 3426 u8 reserved_at_c0[0x8]; 3427 u8 qpn_rqn_sqn[0x18]; 3428 }; 3429 3430 struct mlx5_ifc_dct_events_bits { 3431 u8 reserved_at_0[0xc0]; 3432 3433 u8 reserved_at_c0[0x8]; 3434 u8 dct_number[0x18]; 3435 }; 3436 3437 struct mlx5_ifc_comp_event_bits { 3438 u8 reserved_at_0[0xc0]; 3439 3440 u8 reserved_at_c0[0x8]; 3441 u8 cq_number[0x18]; 3442 }; 3443 3444 enum { 3445 MLX5_QPC_STATE_RST = 0x0, 3446 MLX5_QPC_STATE_INIT = 0x1, 3447 MLX5_QPC_STATE_RTR = 0x2, 3448 MLX5_QPC_STATE_RTS = 0x3, 3449 MLX5_QPC_STATE_SQER = 0x4, 3450 MLX5_QPC_STATE_ERR = 0x6, 3451 MLX5_QPC_STATE_SQD = 0x7, 3452 MLX5_QPC_STATE_SUSPENDED = 0x9, 3453 }; 3454 3455 enum { 3456 MLX5_QPC_ST_RC = 0x0, 3457 MLX5_QPC_ST_UC = 0x1, 3458 MLX5_QPC_ST_UD = 0x2, 3459 MLX5_QPC_ST_XRC = 0x3, 3460 MLX5_QPC_ST_DCI = 0x5, 3461 MLX5_QPC_ST_QP0 = 0x7, 3462 MLX5_QPC_ST_QP1 = 0x8, 3463 MLX5_QPC_ST_RAW_DATAGRAM = 0x9, 3464 MLX5_QPC_ST_REG_UMR = 0xc, 3465 }; 3466 3467 enum { 3468 MLX5_QPC_PM_STATE_ARMED = 0x0, 3469 MLX5_QPC_PM_STATE_REARM = 0x1, 3470 MLX5_QPC_PM_STATE_RESERVED = 0x2, 3471 MLX5_QPC_PM_STATE_MIGRATED = 0x3, 3472 }; 3473 3474 enum { 3475 MLX5_QPC_OFFLOAD_TYPE_RNDV = 0x1, 3476 }; 3477 3478 enum { 3479 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0, 3480 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1, 3481 }; 3482 3483 enum { 3484 MLX5_QPC_MTU_256_BYTES = 0x1, 3485 MLX5_QPC_MTU_512_BYTES = 0x2, 3486 MLX5_QPC_MTU_1K_BYTES = 0x3, 3487 MLX5_QPC_MTU_2K_BYTES = 0x4, 3488 MLX5_QPC_MTU_4K_BYTES = 0x5, 3489 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7, 3490 }; 3491 3492 enum { 3493 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1, 3494 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2, 3495 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3, 3496 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4, 3497 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5, 3498 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6, 3499 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7, 3500 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8, 3501 }; 3502 3503 enum { 3504 MLX5_QPC_CS_REQ_DISABLE = 0x0, 3505 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11, 3506 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22, 3507 }; 3508 3509 enum { 3510 MLX5_QPC_CS_RES_DISABLE = 0x0, 3511 MLX5_QPC_CS_RES_UP_TO_32B = 0x1, 3512 MLX5_QPC_CS_RES_UP_TO_64B = 0x2, 3513 }; 3514 3515 enum { 3516 MLX5_TIMESTAMP_FORMAT_FREE_RUNNING = 0x0, 3517 MLX5_TIMESTAMP_FORMAT_DEFAULT = 0x1, 3518 MLX5_TIMESTAMP_FORMAT_REAL_TIME = 0x2, 3519 }; 3520 3521 struct mlx5_ifc_qpc_bits { 3522 u8 state[0x4]; 3523 u8 lag_tx_port_affinity[0x4]; 3524 u8 st[0x8]; 3525 u8 reserved_at_10[0x2]; 3526 u8 isolate_vl_tc[0x1]; 3527 u8 pm_state[0x2]; 3528 u8 reserved_at_15[0x1]; 3529 u8 req_e2e_credit_mode[0x2]; 3530 u8 offload_type[0x4]; 3531 u8 end_padding_mode[0x2]; 3532 u8 reserved_at_1e[0x2]; 3533 3534 u8 wq_signature[0x1]; 3535 u8 block_lb_mc[0x1]; 3536 u8 atomic_like_write_en[0x1]; 3537 u8 latency_sensitive[0x1]; 3538 u8 reserved_at_24[0x1]; 3539 u8 drain_sigerr[0x1]; 3540 u8 reserved_at_26[0x1]; 3541 u8 dp_ordering_force[0x1]; 3542 u8 pd[0x18]; 3543 3544 u8 mtu[0x3]; 3545 u8 log_msg_max[0x5]; 3546 u8 reserved_at_48[0x1]; 3547 u8 log_rq_size[0x4]; 3548 u8 log_rq_stride[0x3]; 3549 u8 no_sq[0x1]; 3550 u8 log_sq_size[0x4]; 3551 u8 reserved_at_55[0x1]; 3552 u8 retry_mode[0x2]; 3553 u8 ts_format[0x2]; 3554 u8 reserved_at_5a[0x1]; 3555 u8 rlky[0x1]; 3556 u8 ulp_stateless_offload_mode[0x4]; 3557 3558 u8 counter_set_id[0x8]; 3559 u8 uar_page[0x18]; 3560 3561 u8 reserved_at_80[0x8]; 3562 u8 user_index[0x18]; 3563 3564 u8 reserved_at_a0[0x3]; 3565 u8 log_page_size[0x5]; 3566 u8 remote_qpn[0x18]; 3567 3568 struct mlx5_ifc_ads_bits primary_address_path; 3569 3570 struct mlx5_ifc_ads_bits secondary_address_path; 3571 3572 u8 log_ack_req_freq[0x4]; 3573 u8 reserved_at_384[0x4]; 3574 u8 log_sra_max[0x3]; 3575 u8 reserved_at_38b[0x2]; 3576 u8 retry_count[0x3]; 3577 u8 rnr_retry[0x3]; 3578 u8 reserved_at_393[0x1]; 3579 u8 fre[0x1]; 3580 u8 cur_rnr_retry[0x3]; 3581 u8 cur_retry_count[0x3]; 3582 u8 reserved_at_39b[0x5]; 3583 3584 u8 reserved_at_3a0[0x20]; 3585 3586 u8 reserved_at_3c0[0x8]; 3587 u8 next_send_psn[0x18]; 3588 3589 u8 reserved_at_3e0[0x3]; 3590 u8 log_num_dci_stream_channels[0x5]; 3591 u8 cqn_snd[0x18]; 3592 3593 u8 reserved_at_400[0x3]; 3594 u8 log_num_dci_errored_streams[0x5]; 3595 u8 deth_sqpn[0x18]; 3596 3597 u8 reserved_at_420[0x20]; 3598 3599 u8 reserved_at_440[0x8]; 3600 u8 last_acked_psn[0x18]; 3601 3602 u8 reserved_at_460[0x8]; 3603 u8 ssn[0x18]; 3604 3605 u8 reserved_at_480[0x8]; 3606 u8 log_rra_max[0x3]; 3607 u8 reserved_at_48b[0x1]; 3608 u8 atomic_mode[0x4]; 3609 u8 rre[0x1]; 3610 u8 rwe[0x1]; 3611 u8 rae[0x1]; 3612 u8 reserved_at_493[0x1]; 3613 u8 page_offset[0x6]; 3614 u8 reserved_at_49a[0x2]; 3615 u8 dp_ordering_1[0x1]; 3616 u8 cd_slave_receive[0x1]; 3617 u8 cd_slave_send[0x1]; 3618 u8 cd_master[0x1]; 3619 3620 u8 reserved_at_4a0[0x3]; 3621 u8 min_rnr_nak[0x5]; 3622 u8 next_rcv_psn[0x18]; 3623 3624 u8 reserved_at_4c0[0x8]; 3625 u8 xrcd[0x18]; 3626 3627 u8 reserved_at_4e0[0x8]; 3628 u8 cqn_rcv[0x18]; 3629 3630 u8 dbr_addr[0x40]; 3631 3632 u8 q_key[0x20]; 3633 3634 u8 reserved_at_560[0x5]; 3635 u8 rq_type[0x3]; 3636 u8 srqn_rmpn_xrqn[0x18]; 3637 3638 u8 reserved_at_580[0x8]; 3639 u8 rmsn[0x18]; 3640 3641 u8 hw_sq_wqebb_counter[0x10]; 3642 u8 sw_sq_wqebb_counter[0x10]; 3643 3644 u8 hw_rq_counter[0x20]; 3645 3646 u8 sw_rq_counter[0x20]; 3647 3648 u8 reserved_at_600[0x20]; 3649 3650 u8 reserved_at_620[0xf]; 3651 u8 cgs[0x1]; 3652 u8 cs_req[0x8]; 3653 u8 cs_res[0x8]; 3654 3655 u8 dc_access_key[0x40]; 3656 3657 u8 reserved_at_680[0x3]; 3658 u8 dbr_umem_valid[0x1]; 3659 3660 u8 reserved_at_684[0xbc]; 3661 }; 3662 3663 struct mlx5_ifc_roce_addr_layout_bits { 3664 u8 source_l3_address[16][0x8]; 3665 3666 u8 reserved_at_80[0x3]; 3667 u8 vlan_valid[0x1]; 3668 u8 vlan_id[0xc]; 3669 u8 source_mac_47_32[0x10]; 3670 3671 u8 source_mac_31_0[0x20]; 3672 3673 u8 reserved_at_c0[0x14]; 3674 u8 roce_l3_type[0x4]; 3675 u8 roce_version[0x8]; 3676 3677 u8 reserved_at_e0[0x20]; 3678 }; 3679 3680 struct mlx5_ifc_crypto_cap_bits { 3681 u8 reserved_at_0[0x3]; 3682 u8 synchronize_dek[0x1]; 3683 u8 int_kek_manual[0x1]; 3684 u8 int_kek_auto[0x1]; 3685 u8 reserved_at_6[0x1a]; 3686 3687 u8 reserved_at_20[0x3]; 3688 u8 log_dek_max_alloc[0x5]; 3689 u8 reserved_at_28[0x3]; 3690 u8 log_max_num_deks[0x5]; 3691 u8 reserved_at_30[0x10]; 3692 3693 u8 reserved_at_40[0x20]; 3694 3695 u8 reserved_at_60[0x3]; 3696 u8 log_dek_granularity[0x5]; 3697 u8 reserved_at_68[0x3]; 3698 u8 log_max_num_int_kek[0x5]; 3699 u8 sw_wrapped_dek[0x10]; 3700 3701 u8 reserved_at_80[0x780]; 3702 }; 3703 3704 union mlx5_ifc_hca_cap_union_bits { 3705 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap; 3706 struct mlx5_ifc_cmd_hca_cap_2_bits cmd_hca_cap_2; 3707 struct mlx5_ifc_odp_cap_bits odp_cap; 3708 struct mlx5_ifc_atomic_caps_bits atomic_caps; 3709 struct mlx5_ifc_roce_cap_bits roce_cap; 3710 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps; 3711 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap; 3712 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap; 3713 struct mlx5_ifc_wqe_based_flow_table_cap_bits wqe_based_flow_table_cap; 3714 struct mlx5_ifc_esw_cap_bits esw_cap; 3715 struct mlx5_ifc_e_switch_cap_bits e_switch_cap; 3716 struct mlx5_ifc_port_selection_cap_bits port_selection_cap; 3717 struct mlx5_ifc_qos_cap_bits qos_cap; 3718 struct mlx5_ifc_debug_cap_bits debug_cap; 3719 struct mlx5_ifc_fpga_cap_bits fpga_cap; 3720 struct mlx5_ifc_tls_cap_bits tls_cap; 3721 struct mlx5_ifc_device_mem_cap_bits device_mem_cap; 3722 struct mlx5_ifc_virtio_emulation_cap_bits virtio_emulation_cap; 3723 struct mlx5_ifc_macsec_cap_bits macsec_cap; 3724 struct mlx5_ifc_crypto_cap_bits crypto_cap; 3725 struct mlx5_ifc_ipsec_cap_bits ipsec_cap; 3726 u8 reserved_at_0[0x8000]; 3727 }; 3728 3729 enum { 3730 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1, 3731 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2, 3732 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4, 3733 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8, 3734 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT = 0x10, 3735 MLX5_FLOW_CONTEXT_ACTION_DECAP = 0x20, 3736 MLX5_FLOW_CONTEXT_ACTION_MOD_HDR = 0x40, 3737 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP = 0x80, 3738 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100, 3739 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2 = 0x400, 3740 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2 = 0x800, 3741 MLX5_FLOW_CONTEXT_ACTION_CRYPTO_DECRYPT = 0x1000, 3742 MLX5_FLOW_CONTEXT_ACTION_CRYPTO_ENCRYPT = 0x2000, 3743 MLX5_FLOW_CONTEXT_ACTION_EXECUTE_ASO = 0x4000, 3744 }; 3745 3746 enum { 3747 MLX5_FLOW_CONTEXT_FLOW_SOURCE_ANY_VPORT = 0x0, 3748 MLX5_FLOW_CONTEXT_FLOW_SOURCE_UPLINK = 0x1, 3749 MLX5_FLOW_CONTEXT_FLOW_SOURCE_LOCAL_VPORT = 0x2, 3750 }; 3751 3752 enum { 3753 MLX5_FLOW_CONTEXT_ENCRYPT_DECRYPT_TYPE_IPSEC = 0x0, 3754 MLX5_FLOW_CONTEXT_ENCRYPT_DECRYPT_TYPE_MACSEC = 0x1, 3755 }; 3756 3757 struct mlx5_ifc_vlan_bits { 3758 u8 ethtype[0x10]; 3759 u8 prio[0x3]; 3760 u8 cfi[0x1]; 3761 u8 vid[0xc]; 3762 }; 3763 3764 enum { 3765 MLX5_FLOW_METER_COLOR_RED = 0x0, 3766 MLX5_FLOW_METER_COLOR_YELLOW = 0x1, 3767 MLX5_FLOW_METER_COLOR_GREEN = 0x2, 3768 MLX5_FLOW_METER_COLOR_UNDEFINED = 0x3, 3769 }; 3770 3771 enum { 3772 MLX5_EXE_ASO_FLOW_METER = 0x2, 3773 }; 3774 3775 struct mlx5_ifc_exe_aso_ctrl_flow_meter_bits { 3776 u8 return_reg_id[0x4]; 3777 u8 aso_type[0x4]; 3778 u8 reserved_at_8[0x14]; 3779 u8 action[0x1]; 3780 u8 init_color[0x2]; 3781 u8 meter_id[0x1]; 3782 }; 3783 3784 union mlx5_ifc_exe_aso_ctrl { 3785 struct mlx5_ifc_exe_aso_ctrl_flow_meter_bits exe_aso_ctrl_flow_meter; 3786 }; 3787 3788 struct mlx5_ifc_execute_aso_bits { 3789 u8 valid[0x1]; 3790 u8 reserved_at_1[0x7]; 3791 u8 aso_object_id[0x18]; 3792 3793 union mlx5_ifc_exe_aso_ctrl exe_aso_ctrl; 3794 }; 3795 3796 struct mlx5_ifc_flow_context_bits { 3797 struct mlx5_ifc_vlan_bits push_vlan; 3798 3799 u8 group_id[0x20]; 3800 3801 u8 reserved_at_40[0x8]; 3802 u8 flow_tag[0x18]; 3803 3804 u8 reserved_at_60[0x10]; 3805 u8 action[0x10]; 3806 3807 u8 extended_destination[0x1]; 3808 u8 uplink_hairpin_en[0x1]; 3809 u8 flow_source[0x2]; 3810 u8 encrypt_decrypt_type[0x4]; 3811 u8 destination_list_size[0x18]; 3812 3813 u8 reserved_at_a0[0x8]; 3814 u8 flow_counter_list_size[0x18]; 3815 3816 u8 packet_reformat_id[0x20]; 3817 3818 u8 modify_header_id[0x20]; 3819 3820 struct mlx5_ifc_vlan_bits push_vlan_2; 3821 3822 u8 encrypt_decrypt_obj_id[0x20]; 3823 u8 reserved_at_140[0xc0]; 3824 3825 struct mlx5_ifc_fte_match_param_bits match_value; 3826 3827 struct mlx5_ifc_execute_aso_bits execute_aso[4]; 3828 3829 u8 reserved_at_1300[0x500]; 3830 3831 union mlx5_ifc_dest_format_flow_counter_list_auto_bits destination[]; 3832 }; 3833 3834 enum { 3835 MLX5_XRC_SRQC_STATE_GOOD = 0x0, 3836 MLX5_XRC_SRQC_STATE_ERROR = 0x1, 3837 }; 3838 3839 struct mlx5_ifc_xrc_srqc_bits { 3840 u8 state[0x4]; 3841 u8 log_xrc_srq_size[0x4]; 3842 u8 reserved_at_8[0x18]; 3843 3844 u8 wq_signature[0x1]; 3845 u8 cont_srq[0x1]; 3846 u8 reserved_at_22[0x1]; 3847 u8 rlky[0x1]; 3848 u8 basic_cyclic_rcv_wqe[0x1]; 3849 u8 log_rq_stride[0x3]; 3850 u8 xrcd[0x18]; 3851 3852 u8 page_offset[0x6]; 3853 u8 reserved_at_46[0x1]; 3854 u8 dbr_umem_valid[0x1]; 3855 u8 cqn[0x18]; 3856 3857 u8 reserved_at_60[0x20]; 3858 3859 u8 user_index_equal_xrc_srqn[0x1]; 3860 u8 reserved_at_81[0x1]; 3861 u8 log_page_size[0x6]; 3862 u8 user_index[0x18]; 3863 3864 u8 reserved_at_a0[0x20]; 3865 3866 u8 reserved_at_c0[0x8]; 3867 u8 pd[0x18]; 3868 3869 u8 lwm[0x10]; 3870 u8 wqe_cnt[0x10]; 3871 3872 u8 reserved_at_100[0x40]; 3873 3874 u8 db_record_addr_h[0x20]; 3875 3876 u8 db_record_addr_l[0x1e]; 3877 u8 reserved_at_17e[0x2]; 3878 3879 u8 reserved_at_180[0x80]; 3880 }; 3881 3882 struct mlx5_ifc_vnic_diagnostic_statistics_bits { 3883 u8 counter_error_queues[0x20]; 3884 3885 u8 total_error_queues[0x20]; 3886 3887 u8 send_queue_priority_update_flow[0x20]; 3888 3889 u8 reserved_at_60[0x20]; 3890 3891 u8 nic_receive_steering_discard[0x40]; 3892 3893 u8 receive_discard_vport_down[0x40]; 3894 3895 u8 transmit_discard_vport_down[0x40]; 3896 3897 u8 async_eq_overrun[0x20]; 3898 3899 u8 comp_eq_overrun[0x20]; 3900 3901 u8 reserved_at_180[0x20]; 3902 3903 u8 invalid_command[0x20]; 3904 3905 u8 quota_exceeded_command[0x20]; 3906 3907 u8 internal_rq_out_of_buffer[0x20]; 3908 3909 u8 cq_overrun[0x20]; 3910 3911 u8 eth_wqe_too_small[0x20]; 3912 3913 u8 reserved_at_220[0xc0]; 3914 3915 u8 generated_pkt_steering_fail[0x40]; 3916 3917 u8 handled_pkt_steering_fail[0x40]; 3918 3919 u8 reserved_at_360[0xc80]; 3920 }; 3921 3922 struct mlx5_ifc_traffic_counter_bits { 3923 u8 packets[0x40]; 3924 3925 u8 octets[0x40]; 3926 }; 3927 3928 struct mlx5_ifc_tisc_bits { 3929 u8 strict_lag_tx_port_affinity[0x1]; 3930 u8 tls_en[0x1]; 3931 u8 reserved_at_2[0x2]; 3932 u8 lag_tx_port_affinity[0x04]; 3933 3934 u8 reserved_at_8[0x4]; 3935 u8 prio[0x4]; 3936 u8 reserved_at_10[0x10]; 3937 3938 u8 reserved_at_20[0x100]; 3939 3940 u8 reserved_at_120[0x8]; 3941 u8 transport_domain[0x18]; 3942 3943 u8 reserved_at_140[0x8]; 3944 u8 underlay_qpn[0x18]; 3945 3946 u8 reserved_at_160[0x8]; 3947 u8 pd[0x18]; 3948 3949 u8 reserved_at_180[0x380]; 3950 }; 3951 3952 enum { 3953 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0, 3954 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1, 3955 }; 3956 3957 enum { 3958 MLX5_TIRC_PACKET_MERGE_MASK_IPV4_LRO = BIT(0), 3959 MLX5_TIRC_PACKET_MERGE_MASK_IPV6_LRO = BIT(1), 3960 }; 3961 3962 enum { 3963 MLX5_RX_HASH_FN_NONE = 0x0, 3964 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1, 3965 MLX5_RX_HASH_FN_TOEPLITZ = 0x2, 3966 }; 3967 3968 enum { 3969 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST = 0x1, 3970 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST = 0x2, 3971 }; 3972 3973 struct mlx5_ifc_tirc_bits { 3974 u8 reserved_at_0[0x20]; 3975 3976 u8 disp_type[0x4]; 3977 u8 tls_en[0x1]; 3978 u8 reserved_at_25[0x1b]; 3979 3980 u8 reserved_at_40[0x40]; 3981 3982 u8 reserved_at_80[0x4]; 3983 u8 lro_timeout_period_usecs[0x10]; 3984 u8 packet_merge_mask[0x4]; 3985 u8 lro_max_ip_payload_size[0x8]; 3986 3987 u8 reserved_at_a0[0x40]; 3988 3989 u8 reserved_at_e0[0x8]; 3990 u8 inline_rqn[0x18]; 3991 3992 u8 rx_hash_symmetric[0x1]; 3993 u8 reserved_at_101[0x1]; 3994 u8 tunneled_offload_en[0x1]; 3995 u8 reserved_at_103[0x5]; 3996 u8 indirect_table[0x18]; 3997 3998 u8 rx_hash_fn[0x4]; 3999 u8 reserved_at_124[0x2]; 4000 u8 self_lb_block[0x2]; 4001 u8 transport_domain[0x18]; 4002 4003 u8 rx_hash_toeplitz_key[10][0x20]; 4004 4005 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer; 4006 4007 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner; 4008 4009 u8 reserved_at_2c0[0x4c0]; 4010 }; 4011 4012 enum { 4013 MLX5_SRQC_STATE_GOOD = 0x0, 4014 MLX5_SRQC_STATE_ERROR = 0x1, 4015 }; 4016 4017 struct mlx5_ifc_srqc_bits { 4018 u8 state[0x4]; 4019 u8 log_srq_size[0x4]; 4020 u8 reserved_at_8[0x18]; 4021 4022 u8 wq_signature[0x1]; 4023 u8 cont_srq[0x1]; 4024 u8 reserved_at_22[0x1]; 4025 u8 rlky[0x1]; 4026 u8 reserved_at_24[0x1]; 4027 u8 log_rq_stride[0x3]; 4028 u8 xrcd[0x18]; 4029 4030 u8 page_offset[0x6]; 4031 u8 reserved_at_46[0x2]; 4032 u8 cqn[0x18]; 4033 4034 u8 reserved_at_60[0x20]; 4035 4036 u8 reserved_at_80[0x2]; 4037 u8 log_page_size[0x6]; 4038 u8 reserved_at_88[0x18]; 4039 4040 u8 reserved_at_a0[0x20]; 4041 4042 u8 reserved_at_c0[0x8]; 4043 u8 pd[0x18]; 4044 4045 u8 lwm[0x10]; 4046 u8 wqe_cnt[0x10]; 4047 4048 u8 reserved_at_100[0x40]; 4049 4050 u8 dbr_addr[0x40]; 4051 4052 u8 reserved_at_180[0x80]; 4053 }; 4054 4055 enum { 4056 MLX5_SQC_STATE_RST = 0x0, 4057 MLX5_SQC_STATE_RDY = 0x1, 4058 MLX5_SQC_STATE_ERR = 0x3, 4059 }; 4060 4061 struct mlx5_ifc_sqc_bits { 4062 u8 rlky[0x1]; 4063 u8 cd_master[0x1]; 4064 u8 fre[0x1]; 4065 u8 flush_in_error_en[0x1]; 4066 u8 allow_multi_pkt_send_wqe[0x1]; 4067 u8 min_wqe_inline_mode[0x3]; 4068 u8 state[0x4]; 4069 u8 reg_umr[0x1]; 4070 u8 allow_swp[0x1]; 4071 u8 hairpin[0x1]; 4072 u8 non_wire[0x1]; 4073 u8 reserved_at_10[0xa]; 4074 u8 ts_format[0x2]; 4075 u8 reserved_at_1c[0x4]; 4076 4077 u8 reserved_at_20[0x8]; 4078 u8 user_index[0x18]; 4079 4080 u8 reserved_at_40[0x8]; 4081 u8 cqn[0x18]; 4082 4083 u8 reserved_at_60[0x8]; 4084 u8 hairpin_peer_rq[0x18]; 4085 4086 u8 reserved_at_80[0x10]; 4087 u8 hairpin_peer_vhca[0x10]; 4088 4089 u8 reserved_at_a0[0x20]; 4090 4091 u8 reserved_at_c0[0x8]; 4092 u8 ts_cqe_to_dest_cqn[0x18]; 4093 4094 u8 reserved_at_e0[0x10]; 4095 u8 packet_pacing_rate_limit_index[0x10]; 4096 u8 tis_lst_sz[0x10]; 4097 u8 qos_queue_group_id[0x10]; 4098 4099 u8 reserved_at_120[0x40]; 4100 4101 u8 reserved_at_160[0x8]; 4102 u8 tis_num_0[0x18]; 4103 4104 struct mlx5_ifc_wq_bits wq; 4105 }; 4106 4107 enum { 4108 SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0, 4109 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1, 4110 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2, 4111 SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3, 4112 SCHEDULING_CONTEXT_ELEMENT_TYPE_QUEUE_GROUP = 0x4, 4113 SCHEDULING_CONTEXT_ELEMENT_TYPE_RATE_LIMIT = 0x5, 4114 }; 4115 4116 enum { 4117 ELEMENT_TYPE_CAP_MASK_TSAR = 1 << 0, 4118 ELEMENT_TYPE_CAP_MASK_VPORT = 1 << 1, 4119 ELEMENT_TYPE_CAP_MASK_VPORT_TC = 1 << 2, 4120 ELEMENT_TYPE_CAP_MASK_PARA_VPORT_TC = 1 << 3, 4121 ELEMENT_TYPE_CAP_MASK_QUEUE_GROUP = 1 << 4, 4122 ELEMENT_TYPE_CAP_MASK_RATE_LIMIT = 1 << 5, 4123 }; 4124 4125 enum { 4126 TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0, 4127 TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1, 4128 TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2, 4129 TSAR_ELEMENT_TSAR_TYPE_TC_ARB = 0x3, 4130 }; 4131 4132 enum { 4133 TSAR_TYPE_CAP_MASK_DWRR = 1 << 0, 4134 TSAR_TYPE_CAP_MASK_ROUND_ROBIN = 1 << 1, 4135 TSAR_TYPE_CAP_MASK_ETS = 1 << 2, 4136 TSAR_TYPE_CAP_MASK_TC_ARB = 1 << 3, 4137 }; 4138 4139 struct mlx5_ifc_tsar_element_bits { 4140 u8 traffic_class[0x4]; 4141 u8 reserved_at_4[0x4]; 4142 u8 tsar_type[0x8]; 4143 u8 reserved_at_10[0x10]; 4144 }; 4145 4146 struct mlx5_ifc_vport_element_bits { 4147 u8 reserved_at_0[0x4]; 4148 u8 eswitch_owner_vhca_id_valid[0x1]; 4149 u8 eswitch_owner_vhca_id[0xb]; 4150 u8 vport_number[0x10]; 4151 }; 4152 4153 struct mlx5_ifc_vport_tc_element_bits { 4154 u8 traffic_class[0x4]; 4155 u8 eswitch_owner_vhca_id_valid[0x1]; 4156 u8 eswitch_owner_vhca_id[0xb]; 4157 u8 vport_number[0x10]; 4158 }; 4159 4160 union mlx5_ifc_element_attributes_bits { 4161 struct mlx5_ifc_tsar_element_bits tsar; 4162 struct mlx5_ifc_vport_element_bits vport; 4163 struct mlx5_ifc_vport_tc_element_bits vport_tc; 4164 u8 reserved_at_0[0x20]; 4165 }; 4166 4167 struct mlx5_ifc_scheduling_context_bits { 4168 u8 element_type[0x8]; 4169 u8 reserved_at_8[0x18]; 4170 4171 union mlx5_ifc_element_attributes_bits element_attributes; 4172 4173 u8 parent_element_id[0x20]; 4174 4175 u8 reserved_at_60[0x40]; 4176 4177 u8 bw_share[0x20]; 4178 4179 u8 max_average_bw[0x20]; 4180 4181 u8 max_bw_obj_id[0x20]; 4182 4183 u8 reserved_at_100[0x100]; 4184 }; 4185 4186 struct mlx5_ifc_rqtc_bits { 4187 u8 reserved_at_0[0xa0]; 4188 4189 u8 reserved_at_a0[0x5]; 4190 u8 list_q_type[0x3]; 4191 u8 reserved_at_a8[0x8]; 4192 u8 rqt_max_size[0x10]; 4193 4194 u8 rq_vhca_id_format[0x1]; 4195 u8 reserved_at_c1[0xf]; 4196 u8 rqt_actual_size[0x10]; 4197 4198 u8 reserved_at_e0[0x6a0]; 4199 4200 union { 4201 DECLARE_FLEX_ARRAY(struct mlx5_ifc_rq_num_bits, rq_num); 4202 DECLARE_FLEX_ARRAY(struct mlx5_ifc_rq_vhca_bits, rq_vhca); 4203 }; 4204 }; 4205 4206 enum { 4207 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0, 4208 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1, 4209 }; 4210 4211 enum { 4212 MLX5_RQC_STATE_RST = 0x0, 4213 MLX5_RQC_STATE_RDY = 0x1, 4214 MLX5_RQC_STATE_ERR = 0x3, 4215 }; 4216 4217 enum { 4218 MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_BYTE = 0x0, 4219 MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_STRIDE = 0x1, 4220 MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_PAGE = 0x2, 4221 }; 4222 4223 enum { 4224 MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_NO_MATCH = 0x0, 4225 MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_EXTENDED = 0x1, 4226 MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_FIVE_TUPLE = 0x2, 4227 }; 4228 4229 struct mlx5_ifc_rqc_bits { 4230 u8 rlky[0x1]; 4231 u8 delay_drop_en[0x1]; 4232 u8 scatter_fcs[0x1]; 4233 u8 vsd[0x1]; 4234 u8 mem_rq_type[0x4]; 4235 u8 state[0x4]; 4236 u8 reserved_at_c[0x1]; 4237 u8 flush_in_error_en[0x1]; 4238 u8 hairpin[0x1]; 4239 u8 reserved_at_f[0xb]; 4240 u8 ts_format[0x2]; 4241 u8 reserved_at_1c[0x4]; 4242 4243 u8 reserved_at_20[0x8]; 4244 u8 user_index[0x18]; 4245 4246 u8 reserved_at_40[0x8]; 4247 u8 cqn[0x18]; 4248 4249 u8 counter_set_id[0x8]; 4250 u8 reserved_at_68[0x18]; 4251 4252 u8 reserved_at_80[0x8]; 4253 u8 rmpn[0x18]; 4254 4255 u8 reserved_at_a0[0x8]; 4256 u8 hairpin_peer_sq[0x18]; 4257 4258 u8 reserved_at_c0[0x10]; 4259 u8 hairpin_peer_vhca[0x10]; 4260 4261 u8 reserved_at_e0[0x46]; 4262 u8 shampo_no_match_alignment_granularity[0x2]; 4263 u8 reserved_at_128[0x6]; 4264 u8 shampo_match_criteria_type[0x2]; 4265 u8 reservation_timeout[0x10]; 4266 4267 u8 reserved_at_140[0x40]; 4268 4269 struct mlx5_ifc_wq_bits wq; 4270 }; 4271 4272 enum { 4273 MLX5_RMPC_STATE_RDY = 0x1, 4274 MLX5_RMPC_STATE_ERR = 0x3, 4275 }; 4276 4277 struct mlx5_ifc_rmpc_bits { 4278 u8 reserved_at_0[0x8]; 4279 u8 state[0x4]; 4280 u8 reserved_at_c[0x14]; 4281 4282 u8 basic_cyclic_rcv_wqe[0x1]; 4283 u8 reserved_at_21[0x1f]; 4284 4285 u8 reserved_at_40[0x140]; 4286 4287 struct mlx5_ifc_wq_bits wq; 4288 }; 4289 4290 enum { 4291 VHCA_ID_TYPE_HW = 0, 4292 VHCA_ID_TYPE_SW = 1, 4293 }; 4294 4295 struct mlx5_ifc_nic_vport_context_bits { 4296 u8 reserved_at_0[0x5]; 4297 u8 min_wqe_inline_mode[0x3]; 4298 u8 reserved_at_8[0x15]; 4299 u8 disable_mc_local_lb[0x1]; 4300 u8 disable_uc_local_lb[0x1]; 4301 u8 roce_en[0x1]; 4302 4303 u8 arm_change_event[0x1]; 4304 u8 reserved_at_21[0x1a]; 4305 u8 event_on_mtu[0x1]; 4306 u8 event_on_promisc_change[0x1]; 4307 u8 event_on_vlan_change[0x1]; 4308 u8 event_on_mc_address_change[0x1]; 4309 u8 event_on_uc_address_change[0x1]; 4310 4311 u8 vhca_id_type[0x1]; 4312 u8 reserved_at_41[0xb]; 4313 u8 affiliation_criteria[0x4]; 4314 u8 affiliated_vhca_id[0x10]; 4315 4316 u8 reserved_at_60[0xa0]; 4317 4318 u8 reserved_at_100[0x1]; 4319 u8 sd_group[0x3]; 4320 u8 reserved_at_104[0x1c]; 4321 4322 u8 reserved_at_120[0x10]; 4323 u8 mtu[0x10]; 4324 4325 u8 system_image_guid[0x40]; 4326 u8 port_guid[0x40]; 4327 u8 node_guid[0x40]; 4328 4329 u8 reserved_at_200[0x140]; 4330 u8 qkey_violation_counter[0x10]; 4331 u8 reserved_at_350[0x430]; 4332 4333 u8 promisc_uc[0x1]; 4334 u8 promisc_mc[0x1]; 4335 u8 promisc_all[0x1]; 4336 u8 reserved_at_783[0x2]; 4337 u8 allowed_list_type[0x3]; 4338 u8 reserved_at_788[0xc]; 4339 u8 allowed_list_size[0xc]; 4340 4341 struct mlx5_ifc_mac_address_layout_bits permanent_address; 4342 4343 u8 reserved_at_7e0[0x20]; 4344 4345 u8 current_uc_mac_address[][0x40]; 4346 }; 4347 4348 enum { 4349 MLX5_MKC_ACCESS_MODE_PA = 0x0, 4350 MLX5_MKC_ACCESS_MODE_MTT = 0x1, 4351 MLX5_MKC_ACCESS_MODE_KLMS = 0x2, 4352 MLX5_MKC_ACCESS_MODE_KSM = 0x3, 4353 MLX5_MKC_ACCESS_MODE_SW_ICM = 0x4, 4354 MLX5_MKC_ACCESS_MODE_MEMIC = 0x5, 4355 MLX5_MKC_ACCESS_MODE_CROSSING = 0x6, 4356 }; 4357 4358 struct mlx5_ifc_mkc_bits { 4359 u8 reserved_at_0[0x1]; 4360 u8 free[0x1]; 4361 u8 reserved_at_2[0x1]; 4362 u8 access_mode_4_2[0x3]; 4363 u8 reserved_at_6[0x7]; 4364 u8 relaxed_ordering_write[0x1]; 4365 u8 reserved_at_e[0x1]; 4366 u8 small_fence_on_rdma_read_response[0x1]; 4367 u8 umr_en[0x1]; 4368 u8 a[0x1]; 4369 u8 rw[0x1]; 4370 u8 rr[0x1]; 4371 u8 lw[0x1]; 4372 u8 lr[0x1]; 4373 u8 access_mode_1_0[0x2]; 4374 u8 reserved_at_18[0x2]; 4375 u8 ma_translation_mode[0x2]; 4376 u8 reserved_at_1c[0x4]; 4377 4378 u8 qpn[0x18]; 4379 u8 mkey_7_0[0x8]; 4380 4381 u8 reserved_at_40[0x20]; 4382 4383 u8 length64[0x1]; 4384 u8 bsf_en[0x1]; 4385 u8 sync_umr[0x1]; 4386 u8 reserved_at_63[0x2]; 4387 u8 expected_sigerr_count[0x1]; 4388 u8 reserved_at_66[0x1]; 4389 u8 en_rinval[0x1]; 4390 u8 pd[0x18]; 4391 4392 u8 start_addr[0x40]; 4393 4394 u8 len[0x40]; 4395 4396 u8 bsf_octword_size[0x20]; 4397 4398 u8 reserved_at_120[0x60]; 4399 4400 u8 crossing_target_vhca_id[0x10]; 4401 u8 reserved_at_190[0x10]; 4402 4403 u8 translations_octword_size[0x20]; 4404 4405 u8 reserved_at_1c0[0x19]; 4406 u8 relaxed_ordering_read[0x1]; 4407 u8 log_page_size[0x6]; 4408 4409 u8 reserved_at_1e0[0x20]; 4410 }; 4411 4412 struct mlx5_ifc_pkey_bits { 4413 u8 reserved_at_0[0x10]; 4414 u8 pkey[0x10]; 4415 }; 4416 4417 struct mlx5_ifc_array128_auto_bits { 4418 u8 array128_auto[16][0x8]; 4419 }; 4420 4421 struct mlx5_ifc_hca_vport_context_bits { 4422 u8 field_select[0x20]; 4423 4424 u8 reserved_at_20[0xe0]; 4425 4426 u8 sm_virt_aware[0x1]; 4427 u8 has_smi[0x1]; 4428 u8 has_raw[0x1]; 4429 u8 grh_required[0x1]; 4430 u8 reserved_at_104[0x4]; 4431 u8 num_port_plane[0x8]; 4432 u8 port_physical_state[0x4]; 4433 u8 vport_state_policy[0x4]; 4434 u8 port_state[0x4]; 4435 u8 vport_state[0x4]; 4436 4437 u8 reserved_at_120[0x20]; 4438 4439 u8 system_image_guid[0x40]; 4440 4441 u8 port_guid[0x40]; 4442 4443 u8 node_guid[0x40]; 4444 4445 u8 cap_mask1[0x20]; 4446 4447 u8 cap_mask1_field_select[0x20]; 4448 4449 u8 cap_mask2[0x20]; 4450 4451 u8 cap_mask2_field_select[0x20]; 4452 4453 u8 reserved_at_280[0x80]; 4454 4455 u8 lid[0x10]; 4456 u8 reserved_at_310[0x4]; 4457 u8 init_type_reply[0x4]; 4458 u8 lmc[0x3]; 4459 u8 subnet_timeout[0x5]; 4460 4461 u8 sm_lid[0x10]; 4462 u8 sm_sl[0x4]; 4463 u8 reserved_at_334[0xc]; 4464 4465 u8 qkey_violation_counter[0x10]; 4466 u8 pkey_violation_counter[0x10]; 4467 4468 u8 reserved_at_360[0xca0]; 4469 }; 4470 4471 struct mlx5_ifc_esw_vport_context_bits { 4472 u8 fdb_to_vport_reg_c[0x1]; 4473 u8 reserved_at_1[0x2]; 4474 u8 vport_svlan_strip[0x1]; 4475 u8 vport_cvlan_strip[0x1]; 4476 u8 vport_svlan_insert[0x1]; 4477 u8 vport_cvlan_insert[0x2]; 4478 u8 fdb_to_vport_reg_c_id[0x8]; 4479 u8 reserved_at_10[0x10]; 4480 4481 u8 reserved_at_20[0x20]; 4482 4483 u8 svlan_cfi[0x1]; 4484 u8 svlan_pcp[0x3]; 4485 u8 svlan_id[0xc]; 4486 u8 cvlan_cfi[0x1]; 4487 u8 cvlan_pcp[0x3]; 4488 u8 cvlan_id[0xc]; 4489 4490 u8 reserved_at_60[0x720]; 4491 4492 u8 sw_steering_vport_icm_address_rx[0x40]; 4493 4494 u8 sw_steering_vport_icm_address_tx[0x40]; 4495 }; 4496 4497 enum { 4498 MLX5_EQC_STATUS_OK = 0x0, 4499 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa, 4500 }; 4501 4502 enum { 4503 MLX5_EQC_ST_ARMED = 0x9, 4504 MLX5_EQC_ST_FIRED = 0xa, 4505 }; 4506 4507 struct mlx5_ifc_eqc_bits { 4508 u8 status[0x4]; 4509 u8 reserved_at_4[0x9]; 4510 u8 ec[0x1]; 4511 u8 oi[0x1]; 4512 u8 reserved_at_f[0x5]; 4513 u8 st[0x4]; 4514 u8 reserved_at_18[0x8]; 4515 4516 u8 reserved_at_20[0x20]; 4517 4518 u8 reserved_at_40[0x14]; 4519 u8 page_offset[0x6]; 4520 u8 reserved_at_5a[0x6]; 4521 4522 u8 reserved_at_60[0x3]; 4523 u8 log_eq_size[0x5]; 4524 u8 uar_page[0x18]; 4525 4526 u8 reserved_at_80[0x20]; 4527 4528 u8 reserved_at_a0[0x14]; 4529 u8 intr[0xc]; 4530 4531 u8 reserved_at_c0[0x3]; 4532 u8 log_page_size[0x5]; 4533 u8 reserved_at_c8[0x18]; 4534 4535 u8 reserved_at_e0[0x60]; 4536 4537 u8 reserved_at_140[0x8]; 4538 u8 consumer_counter[0x18]; 4539 4540 u8 reserved_at_160[0x8]; 4541 u8 producer_counter[0x18]; 4542 4543 u8 reserved_at_180[0x80]; 4544 }; 4545 4546 enum { 4547 MLX5_DCTC_STATE_ACTIVE = 0x0, 4548 MLX5_DCTC_STATE_DRAINING = 0x1, 4549 MLX5_DCTC_STATE_DRAINED = 0x2, 4550 }; 4551 4552 enum { 4553 MLX5_DCTC_CS_RES_DISABLE = 0x0, 4554 MLX5_DCTC_CS_RES_NA = 0x1, 4555 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2, 4556 }; 4557 4558 enum { 4559 MLX5_DCTC_MTU_256_BYTES = 0x1, 4560 MLX5_DCTC_MTU_512_BYTES = 0x2, 4561 MLX5_DCTC_MTU_1K_BYTES = 0x3, 4562 MLX5_DCTC_MTU_2K_BYTES = 0x4, 4563 MLX5_DCTC_MTU_4K_BYTES = 0x5, 4564 }; 4565 4566 struct mlx5_ifc_dctc_bits { 4567 u8 reserved_at_0[0x4]; 4568 u8 state[0x4]; 4569 u8 reserved_at_8[0x18]; 4570 4571 u8 reserved_at_20[0x7]; 4572 u8 dp_ordering_force[0x1]; 4573 u8 user_index[0x18]; 4574 4575 u8 reserved_at_40[0x8]; 4576 u8 cqn[0x18]; 4577 4578 u8 counter_set_id[0x8]; 4579 u8 atomic_mode[0x4]; 4580 u8 rre[0x1]; 4581 u8 rwe[0x1]; 4582 u8 rae[0x1]; 4583 u8 atomic_like_write_en[0x1]; 4584 u8 latency_sensitive[0x1]; 4585 u8 rlky[0x1]; 4586 u8 free_ar[0x1]; 4587 u8 reserved_at_73[0x1]; 4588 u8 dp_ordering_1[0x1]; 4589 u8 reserved_at_75[0xb]; 4590 4591 u8 reserved_at_80[0x8]; 4592 u8 cs_res[0x8]; 4593 u8 reserved_at_90[0x3]; 4594 u8 min_rnr_nak[0x5]; 4595 u8 reserved_at_98[0x8]; 4596 4597 u8 reserved_at_a0[0x8]; 4598 u8 srqn_xrqn[0x18]; 4599 4600 u8 reserved_at_c0[0x8]; 4601 u8 pd[0x18]; 4602 4603 u8 tclass[0x8]; 4604 u8 reserved_at_e8[0x4]; 4605 u8 flow_label[0x14]; 4606 4607 u8 dc_access_key[0x40]; 4608 4609 u8 reserved_at_140[0x5]; 4610 u8 mtu[0x3]; 4611 u8 port[0x8]; 4612 u8 pkey_index[0x10]; 4613 4614 u8 reserved_at_160[0x8]; 4615 u8 my_addr_index[0x8]; 4616 u8 reserved_at_170[0x8]; 4617 u8 hop_limit[0x8]; 4618 4619 u8 dc_access_key_violation_count[0x20]; 4620 4621 u8 reserved_at_1a0[0x14]; 4622 u8 dei_cfi[0x1]; 4623 u8 eth_prio[0x3]; 4624 u8 ecn[0x2]; 4625 u8 dscp[0x6]; 4626 4627 u8 reserved_at_1c0[0x20]; 4628 u8 ece[0x20]; 4629 }; 4630 4631 enum { 4632 MLX5_CQC_STATUS_OK = 0x0, 4633 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9, 4634 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa, 4635 }; 4636 4637 enum { 4638 MLX5_CQC_CQE_SZ_64_BYTES = 0x0, 4639 MLX5_CQC_CQE_SZ_128_BYTES = 0x1, 4640 }; 4641 4642 enum { 4643 MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED = 0x6, 4644 MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED = 0x9, 4645 MLX5_CQC_ST_FIRED = 0xa, 4646 }; 4647 4648 enum mlx5_cq_period_mode { 4649 MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0, 4650 MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1, 4651 MLX5_CQ_PERIOD_NUM_MODES, 4652 }; 4653 4654 struct mlx5_ifc_cqc_bits { 4655 u8 status[0x4]; 4656 u8 reserved_at_4[0x2]; 4657 u8 dbr_umem_valid[0x1]; 4658 u8 apu_cq[0x1]; 4659 u8 cqe_sz[0x3]; 4660 u8 cc[0x1]; 4661 u8 reserved_at_c[0x1]; 4662 u8 scqe_break_moderation_en[0x1]; 4663 u8 oi[0x1]; 4664 u8 cq_period_mode[0x2]; 4665 u8 cqe_comp_en[0x1]; 4666 u8 mini_cqe_res_format[0x2]; 4667 u8 st[0x4]; 4668 u8 reserved_at_18[0x6]; 4669 u8 cqe_compression_layout[0x2]; 4670 4671 u8 reserved_at_20[0x20]; 4672 4673 u8 reserved_at_40[0x14]; 4674 u8 page_offset[0x6]; 4675 u8 reserved_at_5a[0x6]; 4676 4677 u8 reserved_at_60[0x3]; 4678 u8 log_cq_size[0x5]; 4679 u8 uar_page[0x18]; 4680 4681 u8 reserved_at_80[0x4]; 4682 u8 cq_period[0xc]; 4683 u8 cq_max_count[0x10]; 4684 4685 u8 c_eqn_or_apu_element[0x20]; 4686 4687 u8 reserved_at_c0[0x3]; 4688 u8 log_page_size[0x5]; 4689 u8 reserved_at_c8[0x18]; 4690 4691 u8 reserved_at_e0[0x20]; 4692 4693 u8 reserved_at_100[0x8]; 4694 u8 last_notified_index[0x18]; 4695 4696 u8 reserved_at_120[0x8]; 4697 u8 last_solicit_index[0x18]; 4698 4699 u8 reserved_at_140[0x8]; 4700 u8 consumer_counter[0x18]; 4701 4702 u8 reserved_at_160[0x8]; 4703 u8 producer_counter[0x18]; 4704 4705 u8 reserved_at_180[0x40]; 4706 4707 u8 dbr_addr[0x40]; 4708 }; 4709 4710 union mlx5_ifc_cong_control_roce_ecn_auto_bits { 4711 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp; 4712 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp; 4713 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np; 4714 struct mlx5_ifc_cong_control_r_roce_general_bits cong_control_r_roce_general; 4715 u8 reserved_at_0[0x800]; 4716 }; 4717 4718 struct mlx5_ifc_query_adapter_param_block_bits { 4719 u8 reserved_at_0[0xc0]; 4720 4721 u8 reserved_at_c0[0x8]; 4722 u8 ieee_vendor_id[0x18]; 4723 4724 u8 reserved_at_e0[0x10]; 4725 u8 vsd_vendor_id[0x10]; 4726 4727 u8 vsd[208][0x8]; 4728 4729 u8 vsd_contd_psid[16][0x8]; 4730 }; 4731 4732 enum { 4733 MLX5_XRQC_STATE_GOOD = 0x0, 4734 MLX5_XRQC_STATE_ERROR = 0x1, 4735 }; 4736 4737 enum { 4738 MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0, 4739 MLX5_XRQC_TOPOLOGY_TAG_MATCHING = 0x1, 4740 }; 4741 4742 enum { 4743 MLX5_XRQC_OFFLOAD_RNDV = 0x1, 4744 }; 4745 4746 struct mlx5_ifc_tag_matching_topology_context_bits { 4747 u8 log_matching_list_sz[0x4]; 4748 u8 reserved_at_4[0xc]; 4749 u8 append_next_index[0x10]; 4750 4751 u8 sw_phase_cnt[0x10]; 4752 u8 hw_phase_cnt[0x10]; 4753 4754 u8 reserved_at_40[0x40]; 4755 }; 4756 4757 struct mlx5_ifc_xrqc_bits { 4758 u8 state[0x4]; 4759 u8 rlkey[0x1]; 4760 u8 reserved_at_5[0xf]; 4761 u8 topology[0x4]; 4762 u8 reserved_at_18[0x4]; 4763 u8 offload[0x4]; 4764 4765 u8 reserved_at_20[0x8]; 4766 u8 user_index[0x18]; 4767 4768 u8 reserved_at_40[0x8]; 4769 u8 cqn[0x18]; 4770 4771 u8 reserved_at_60[0xa0]; 4772 4773 struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context; 4774 4775 u8 reserved_at_180[0x280]; 4776 4777 struct mlx5_ifc_wq_bits wq; 4778 }; 4779 4780 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits { 4781 struct mlx5_ifc_modify_field_select_bits modify_field_select; 4782 struct mlx5_ifc_resize_field_select_bits resize_field_select; 4783 u8 reserved_at_0[0x20]; 4784 }; 4785 4786 union mlx5_ifc_field_select_802_1_r_roce_auto_bits { 4787 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp; 4788 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp; 4789 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np; 4790 u8 reserved_at_0[0x20]; 4791 }; 4792 4793 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits { 4794 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 4795 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 4796 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 4797 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 4798 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 4799 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 4800 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout; 4801 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout; 4802 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 4803 struct mlx5_ifc_ib_ext_port_cntrs_grp_data_layout_bits ib_ext_port_cntrs_grp_data_layout; 4804 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 4805 struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs; 4806 u8 reserved_at_0[0x7c0]; 4807 }; 4808 4809 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits { 4810 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout; 4811 u8 reserved_at_0[0x7c0]; 4812 }; 4813 4814 union mlx5_ifc_event_auto_bits { 4815 struct mlx5_ifc_comp_event_bits comp_event; 4816 struct mlx5_ifc_dct_events_bits dct_events; 4817 struct mlx5_ifc_qp_events_bits qp_events; 4818 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event; 4819 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event; 4820 struct mlx5_ifc_cq_error_bits cq_error; 4821 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged; 4822 struct mlx5_ifc_port_state_change_event_bits port_state_change_event; 4823 struct mlx5_ifc_gpio_event_bits gpio_event; 4824 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event; 4825 struct mlx5_ifc_stall_vl_event_bits stall_vl_event; 4826 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event; 4827 u8 reserved_at_0[0xe0]; 4828 }; 4829 4830 struct mlx5_ifc_health_buffer_bits { 4831 u8 reserved_at_0[0x100]; 4832 4833 u8 assert_existptr[0x20]; 4834 4835 u8 assert_callra[0x20]; 4836 4837 u8 reserved_at_140[0x20]; 4838 4839 u8 time[0x20]; 4840 4841 u8 fw_version[0x20]; 4842 4843 u8 hw_id[0x20]; 4844 4845 u8 rfr[0x1]; 4846 u8 reserved_at_1c1[0x3]; 4847 u8 valid[0x1]; 4848 u8 severity[0x3]; 4849 u8 reserved_at_1c8[0x18]; 4850 4851 u8 irisc_index[0x8]; 4852 u8 synd[0x8]; 4853 u8 ext_synd[0x10]; 4854 }; 4855 4856 struct mlx5_ifc_register_loopback_control_bits { 4857 u8 no_lb[0x1]; 4858 u8 reserved_at_1[0x7]; 4859 u8 port[0x8]; 4860 u8 reserved_at_10[0x10]; 4861 4862 u8 reserved_at_20[0x60]; 4863 }; 4864 4865 enum { 4866 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0, 4867 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1, 4868 }; 4869 4870 struct mlx5_ifc_teardown_hca_out_bits { 4871 u8 status[0x8]; 4872 u8 reserved_at_8[0x18]; 4873 4874 u8 syndrome[0x20]; 4875 4876 u8 reserved_at_40[0x3f]; 4877 4878 u8 state[0x1]; 4879 }; 4880 4881 enum { 4882 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0, 4883 MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE = 0x1, 4884 MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN = 0x2, 4885 }; 4886 4887 struct mlx5_ifc_teardown_hca_in_bits { 4888 u8 opcode[0x10]; 4889 u8 reserved_at_10[0x10]; 4890 4891 u8 reserved_at_20[0x10]; 4892 u8 op_mod[0x10]; 4893 4894 u8 reserved_at_40[0x10]; 4895 u8 profile[0x10]; 4896 4897 u8 reserved_at_60[0x20]; 4898 }; 4899 4900 struct mlx5_ifc_sqerr2rts_qp_out_bits { 4901 u8 status[0x8]; 4902 u8 reserved_at_8[0x18]; 4903 4904 u8 syndrome[0x20]; 4905 4906 u8 reserved_at_40[0x40]; 4907 }; 4908 4909 struct mlx5_ifc_sqerr2rts_qp_in_bits { 4910 u8 opcode[0x10]; 4911 u8 uid[0x10]; 4912 4913 u8 reserved_at_20[0x10]; 4914 u8 op_mod[0x10]; 4915 4916 u8 reserved_at_40[0x8]; 4917 u8 qpn[0x18]; 4918 4919 u8 reserved_at_60[0x20]; 4920 4921 u8 opt_param_mask[0x20]; 4922 4923 u8 reserved_at_a0[0x20]; 4924 4925 struct mlx5_ifc_qpc_bits qpc; 4926 4927 u8 reserved_at_800[0x80]; 4928 }; 4929 4930 struct mlx5_ifc_sqd2rts_qp_out_bits { 4931 u8 status[0x8]; 4932 u8 reserved_at_8[0x18]; 4933 4934 u8 syndrome[0x20]; 4935 4936 u8 reserved_at_40[0x40]; 4937 }; 4938 4939 struct mlx5_ifc_sqd2rts_qp_in_bits { 4940 u8 opcode[0x10]; 4941 u8 uid[0x10]; 4942 4943 u8 reserved_at_20[0x10]; 4944 u8 op_mod[0x10]; 4945 4946 u8 reserved_at_40[0x8]; 4947 u8 qpn[0x18]; 4948 4949 u8 reserved_at_60[0x20]; 4950 4951 u8 opt_param_mask[0x20]; 4952 4953 u8 reserved_at_a0[0x20]; 4954 4955 struct mlx5_ifc_qpc_bits qpc; 4956 4957 u8 reserved_at_800[0x80]; 4958 }; 4959 4960 struct mlx5_ifc_set_roce_address_out_bits { 4961 u8 status[0x8]; 4962 u8 reserved_at_8[0x18]; 4963 4964 u8 syndrome[0x20]; 4965 4966 u8 reserved_at_40[0x40]; 4967 }; 4968 4969 struct mlx5_ifc_set_roce_address_in_bits { 4970 u8 opcode[0x10]; 4971 u8 reserved_at_10[0x10]; 4972 4973 u8 reserved_at_20[0x10]; 4974 u8 op_mod[0x10]; 4975 4976 u8 roce_address_index[0x10]; 4977 u8 reserved_at_50[0xc]; 4978 u8 vhca_port_num[0x4]; 4979 4980 u8 reserved_at_60[0x20]; 4981 4982 struct mlx5_ifc_roce_addr_layout_bits roce_address; 4983 }; 4984 4985 struct mlx5_ifc_set_mad_demux_out_bits { 4986 u8 status[0x8]; 4987 u8 reserved_at_8[0x18]; 4988 4989 u8 syndrome[0x20]; 4990 4991 u8 reserved_at_40[0x40]; 4992 }; 4993 4994 enum { 4995 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0, 4996 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2, 4997 }; 4998 4999 struct mlx5_ifc_set_mad_demux_in_bits { 5000 u8 opcode[0x10]; 5001 u8 reserved_at_10[0x10]; 5002 5003 u8 reserved_at_20[0x10]; 5004 u8 op_mod[0x10]; 5005 5006 u8 reserved_at_40[0x20]; 5007 5008 u8 reserved_at_60[0x6]; 5009 u8 demux_mode[0x2]; 5010 u8 reserved_at_68[0x18]; 5011 }; 5012 5013 struct mlx5_ifc_set_l2_table_entry_out_bits { 5014 u8 status[0x8]; 5015 u8 reserved_at_8[0x18]; 5016 5017 u8 syndrome[0x20]; 5018 5019 u8 reserved_at_40[0x40]; 5020 }; 5021 5022 struct mlx5_ifc_set_l2_table_entry_in_bits { 5023 u8 opcode[0x10]; 5024 u8 reserved_at_10[0x10]; 5025 5026 u8 reserved_at_20[0x10]; 5027 u8 op_mod[0x10]; 5028 5029 u8 reserved_at_40[0x60]; 5030 5031 u8 reserved_at_a0[0x8]; 5032 u8 table_index[0x18]; 5033 5034 u8 reserved_at_c0[0x20]; 5035 5036 u8 reserved_at_e0[0x10]; 5037 u8 silent_mode_valid[0x1]; 5038 u8 silent_mode[0x1]; 5039 u8 reserved_at_f2[0x1]; 5040 u8 vlan_valid[0x1]; 5041 u8 vlan[0xc]; 5042 5043 struct mlx5_ifc_mac_address_layout_bits mac_address; 5044 5045 u8 reserved_at_140[0xc0]; 5046 }; 5047 5048 struct mlx5_ifc_set_issi_out_bits { 5049 u8 status[0x8]; 5050 u8 reserved_at_8[0x18]; 5051 5052 u8 syndrome[0x20]; 5053 5054 u8 reserved_at_40[0x40]; 5055 }; 5056 5057 struct mlx5_ifc_set_issi_in_bits { 5058 u8 opcode[0x10]; 5059 u8 reserved_at_10[0x10]; 5060 5061 u8 reserved_at_20[0x10]; 5062 u8 op_mod[0x10]; 5063 5064 u8 reserved_at_40[0x10]; 5065 u8 current_issi[0x10]; 5066 5067 u8 reserved_at_60[0x20]; 5068 }; 5069 5070 struct mlx5_ifc_set_hca_cap_out_bits { 5071 u8 status[0x8]; 5072 u8 reserved_at_8[0x18]; 5073 5074 u8 syndrome[0x20]; 5075 5076 u8 reserved_at_40[0x40]; 5077 }; 5078 5079 struct mlx5_ifc_set_hca_cap_in_bits { 5080 u8 opcode[0x10]; 5081 u8 reserved_at_10[0x10]; 5082 5083 u8 reserved_at_20[0x10]; 5084 u8 op_mod[0x10]; 5085 5086 u8 other_function[0x1]; 5087 u8 ec_vf_function[0x1]; 5088 u8 reserved_at_42[0xe]; 5089 u8 function_id[0x10]; 5090 5091 u8 reserved_at_60[0x20]; 5092 5093 union mlx5_ifc_hca_cap_union_bits capability; 5094 }; 5095 5096 enum { 5097 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0, 5098 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1, 5099 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2, 5100 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3, 5101 MLX5_SET_FTE_MODIFY_ENABLE_MASK_IPSEC_OBJ_ID = 0x4 5102 }; 5103 5104 struct mlx5_ifc_set_fte_out_bits { 5105 u8 status[0x8]; 5106 u8 reserved_at_8[0x18]; 5107 5108 u8 syndrome[0x20]; 5109 5110 u8 reserved_at_40[0x40]; 5111 }; 5112 5113 struct mlx5_ifc_set_fte_in_bits { 5114 u8 opcode[0x10]; 5115 u8 reserved_at_10[0x10]; 5116 5117 u8 reserved_at_20[0x10]; 5118 u8 op_mod[0x10]; 5119 5120 u8 other_vport[0x1]; 5121 u8 reserved_at_41[0xf]; 5122 u8 vport_number[0x10]; 5123 5124 u8 reserved_at_60[0x20]; 5125 5126 u8 table_type[0x8]; 5127 u8 reserved_at_88[0x18]; 5128 5129 u8 reserved_at_a0[0x8]; 5130 u8 table_id[0x18]; 5131 5132 u8 ignore_flow_level[0x1]; 5133 u8 reserved_at_c1[0x17]; 5134 u8 modify_enable_mask[0x8]; 5135 5136 u8 reserved_at_e0[0x20]; 5137 5138 u8 flow_index[0x20]; 5139 5140 u8 reserved_at_120[0xe0]; 5141 5142 struct mlx5_ifc_flow_context_bits flow_context; 5143 }; 5144 5145 struct mlx5_ifc_dest_format_bits { 5146 u8 destination_type[0x8]; 5147 u8 destination_id[0x18]; 5148 5149 u8 destination_eswitch_owner_vhca_id_valid[0x1]; 5150 u8 packet_reformat[0x1]; 5151 u8 reserved_at_22[0xe]; 5152 u8 destination_eswitch_owner_vhca_id[0x10]; 5153 }; 5154 5155 struct mlx5_ifc_rts2rts_qp_out_bits { 5156 u8 status[0x8]; 5157 u8 reserved_at_8[0x18]; 5158 5159 u8 syndrome[0x20]; 5160 5161 u8 reserved_at_40[0x20]; 5162 u8 ece[0x20]; 5163 }; 5164 5165 struct mlx5_ifc_rts2rts_qp_in_bits { 5166 u8 opcode[0x10]; 5167 u8 uid[0x10]; 5168 5169 u8 reserved_at_20[0x10]; 5170 u8 op_mod[0x10]; 5171 5172 u8 reserved_at_40[0x8]; 5173 u8 qpn[0x18]; 5174 5175 u8 reserved_at_60[0x20]; 5176 5177 u8 opt_param_mask[0x20]; 5178 5179 u8 ece[0x20]; 5180 5181 struct mlx5_ifc_qpc_bits qpc; 5182 5183 u8 reserved_at_800[0x80]; 5184 }; 5185 5186 struct mlx5_ifc_rtr2rts_qp_out_bits { 5187 u8 status[0x8]; 5188 u8 reserved_at_8[0x18]; 5189 5190 u8 syndrome[0x20]; 5191 5192 u8 reserved_at_40[0x20]; 5193 u8 ece[0x20]; 5194 }; 5195 5196 struct mlx5_ifc_rtr2rts_qp_in_bits { 5197 u8 opcode[0x10]; 5198 u8 uid[0x10]; 5199 5200 u8 reserved_at_20[0x10]; 5201 u8 op_mod[0x10]; 5202 5203 u8 reserved_at_40[0x8]; 5204 u8 qpn[0x18]; 5205 5206 u8 reserved_at_60[0x20]; 5207 5208 u8 opt_param_mask[0x20]; 5209 5210 u8 ece[0x20]; 5211 5212 struct mlx5_ifc_qpc_bits qpc; 5213 5214 u8 reserved_at_800[0x80]; 5215 }; 5216 5217 struct mlx5_ifc_rst2init_qp_out_bits { 5218 u8 status[0x8]; 5219 u8 reserved_at_8[0x18]; 5220 5221 u8 syndrome[0x20]; 5222 5223 u8 reserved_at_40[0x20]; 5224 u8 ece[0x20]; 5225 }; 5226 5227 struct mlx5_ifc_rst2init_qp_in_bits { 5228 u8 opcode[0x10]; 5229 u8 uid[0x10]; 5230 5231 u8 reserved_at_20[0x10]; 5232 u8 op_mod[0x10]; 5233 5234 u8 reserved_at_40[0x8]; 5235 u8 qpn[0x18]; 5236 5237 u8 reserved_at_60[0x20]; 5238 5239 u8 opt_param_mask[0x20]; 5240 5241 u8 ece[0x20]; 5242 5243 struct mlx5_ifc_qpc_bits qpc; 5244 5245 u8 reserved_at_800[0x80]; 5246 }; 5247 5248 struct mlx5_ifc_query_xrq_out_bits { 5249 u8 status[0x8]; 5250 u8 reserved_at_8[0x18]; 5251 5252 u8 syndrome[0x20]; 5253 5254 u8 reserved_at_40[0x40]; 5255 5256 struct mlx5_ifc_xrqc_bits xrq_context; 5257 }; 5258 5259 struct mlx5_ifc_query_xrq_in_bits { 5260 u8 opcode[0x10]; 5261 u8 reserved_at_10[0x10]; 5262 5263 u8 reserved_at_20[0x10]; 5264 u8 op_mod[0x10]; 5265 5266 u8 reserved_at_40[0x8]; 5267 u8 xrqn[0x18]; 5268 5269 u8 reserved_at_60[0x20]; 5270 }; 5271 5272 struct mlx5_ifc_query_xrc_srq_out_bits { 5273 u8 status[0x8]; 5274 u8 reserved_at_8[0x18]; 5275 5276 u8 syndrome[0x20]; 5277 5278 u8 reserved_at_40[0x40]; 5279 5280 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 5281 5282 u8 reserved_at_280[0x600]; 5283 5284 u8 pas[][0x40]; 5285 }; 5286 5287 struct mlx5_ifc_query_xrc_srq_in_bits { 5288 u8 opcode[0x10]; 5289 u8 reserved_at_10[0x10]; 5290 5291 u8 reserved_at_20[0x10]; 5292 u8 op_mod[0x10]; 5293 5294 u8 reserved_at_40[0x8]; 5295 u8 xrc_srqn[0x18]; 5296 5297 u8 reserved_at_60[0x20]; 5298 }; 5299 5300 enum { 5301 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0, 5302 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1, 5303 }; 5304 5305 struct mlx5_ifc_query_vport_state_out_bits { 5306 u8 status[0x8]; 5307 u8 reserved_at_8[0x18]; 5308 5309 u8 syndrome[0x20]; 5310 5311 u8 reserved_at_40[0x20]; 5312 5313 u8 reserved_at_60[0x18]; 5314 u8 admin_state[0x4]; 5315 u8 state[0x4]; 5316 }; 5317 5318 struct mlx5_ifc_array1024_auto_bits { 5319 u8 array1024_auto[32][0x20]; 5320 }; 5321 5322 struct mlx5_ifc_query_vuid_in_bits { 5323 u8 opcode[0x10]; 5324 u8 uid[0x10]; 5325 5326 u8 reserved_at_20[0x40]; 5327 5328 u8 query_vfs_vuid[0x1]; 5329 u8 data_direct[0x1]; 5330 u8 reserved_at_62[0xe]; 5331 u8 vhca_id[0x10]; 5332 }; 5333 5334 struct mlx5_ifc_query_vuid_out_bits { 5335 u8 status[0x8]; 5336 u8 reserved_at_8[0x18]; 5337 5338 u8 syndrome[0x20]; 5339 5340 u8 reserved_at_40[0x1a0]; 5341 5342 u8 reserved_at_1e0[0x10]; 5343 u8 num_of_entries[0x10]; 5344 5345 struct mlx5_ifc_array1024_auto_bits vuid[]; 5346 }; 5347 5348 enum { 5349 MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT = 0x0, 5350 MLX5_VPORT_STATE_OP_MOD_ESW_VPORT = 0x1, 5351 MLX5_VPORT_STATE_OP_MOD_UPLINK = 0x2, 5352 }; 5353 5354 struct mlx5_ifc_arm_monitor_counter_in_bits { 5355 u8 opcode[0x10]; 5356 u8 uid[0x10]; 5357 5358 u8 reserved_at_20[0x10]; 5359 u8 op_mod[0x10]; 5360 5361 u8 reserved_at_40[0x20]; 5362 5363 u8 reserved_at_60[0x20]; 5364 }; 5365 5366 struct mlx5_ifc_arm_monitor_counter_out_bits { 5367 u8 status[0x8]; 5368 u8 reserved_at_8[0x18]; 5369 5370 u8 syndrome[0x20]; 5371 5372 u8 reserved_at_40[0x40]; 5373 }; 5374 5375 enum { 5376 MLX5_QUERY_MONITOR_CNT_TYPE_PPCNT = 0x0, 5377 MLX5_QUERY_MONITOR_CNT_TYPE_Q_COUNTER = 0x1, 5378 }; 5379 5380 enum mlx5_monitor_counter_ppcnt { 5381 MLX5_QUERY_MONITOR_PPCNT_IN_RANGE_LENGTH_ERRORS = 0x0, 5382 MLX5_QUERY_MONITOR_PPCNT_OUT_OF_RANGE_LENGTH_FIELD = 0x1, 5383 MLX5_QUERY_MONITOR_PPCNT_FRAME_TOO_LONG_ERRORS = 0x2, 5384 MLX5_QUERY_MONITOR_PPCNT_FRAME_CHECK_SEQUENCE_ERRORS = 0x3, 5385 MLX5_QUERY_MONITOR_PPCNT_ALIGNMENT_ERRORS = 0x4, 5386 MLX5_QUERY_MONITOR_PPCNT_IF_OUT_DISCARDS = 0x5, 5387 }; 5388 5389 enum { 5390 MLX5_QUERY_MONITOR_Q_COUNTER_RX_OUT_OF_BUFFER = 0x4, 5391 }; 5392 5393 struct mlx5_ifc_monitor_counter_output_bits { 5394 u8 reserved_at_0[0x4]; 5395 u8 type[0x4]; 5396 u8 reserved_at_8[0x8]; 5397 u8 counter[0x10]; 5398 5399 u8 counter_group_id[0x20]; 5400 }; 5401 5402 #define MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 (6) 5403 #define MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1 (1) 5404 #define MLX5_CMD_SET_MONITOR_NUM_COUNTER (MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 +\ 5405 MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1) 5406 5407 struct mlx5_ifc_set_monitor_counter_in_bits { 5408 u8 opcode[0x10]; 5409 u8 uid[0x10]; 5410 5411 u8 reserved_at_20[0x10]; 5412 u8 op_mod[0x10]; 5413 5414 u8 reserved_at_40[0x10]; 5415 u8 num_of_counters[0x10]; 5416 5417 u8 reserved_at_60[0x20]; 5418 5419 struct mlx5_ifc_monitor_counter_output_bits monitor_counter[MLX5_CMD_SET_MONITOR_NUM_COUNTER]; 5420 }; 5421 5422 struct mlx5_ifc_set_monitor_counter_out_bits { 5423 u8 status[0x8]; 5424 u8 reserved_at_8[0x18]; 5425 5426 u8 syndrome[0x20]; 5427 5428 u8 reserved_at_40[0x40]; 5429 }; 5430 5431 struct mlx5_ifc_query_vport_state_in_bits { 5432 u8 opcode[0x10]; 5433 u8 reserved_at_10[0x10]; 5434 5435 u8 reserved_at_20[0x10]; 5436 u8 op_mod[0x10]; 5437 5438 u8 other_vport[0x1]; 5439 u8 reserved_at_41[0xf]; 5440 u8 vport_number[0x10]; 5441 5442 u8 reserved_at_60[0x20]; 5443 }; 5444 5445 struct mlx5_ifc_query_vnic_env_out_bits { 5446 u8 status[0x8]; 5447 u8 reserved_at_8[0x18]; 5448 5449 u8 syndrome[0x20]; 5450 5451 u8 reserved_at_40[0x40]; 5452 5453 struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env; 5454 }; 5455 5456 enum { 5457 MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS = 0x0, 5458 }; 5459 5460 struct mlx5_ifc_query_vnic_env_in_bits { 5461 u8 opcode[0x10]; 5462 u8 reserved_at_10[0x10]; 5463 5464 u8 reserved_at_20[0x10]; 5465 u8 op_mod[0x10]; 5466 5467 u8 other_vport[0x1]; 5468 u8 reserved_at_41[0xf]; 5469 u8 vport_number[0x10]; 5470 5471 u8 reserved_at_60[0x20]; 5472 }; 5473 5474 struct mlx5_ifc_query_vport_counter_out_bits { 5475 u8 status[0x8]; 5476 u8 reserved_at_8[0x18]; 5477 5478 u8 syndrome[0x20]; 5479 5480 u8 reserved_at_40[0x40]; 5481 5482 struct mlx5_ifc_traffic_counter_bits received_errors; 5483 5484 struct mlx5_ifc_traffic_counter_bits transmit_errors; 5485 5486 struct mlx5_ifc_traffic_counter_bits received_ib_unicast; 5487 5488 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast; 5489 5490 struct mlx5_ifc_traffic_counter_bits received_ib_multicast; 5491 5492 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast; 5493 5494 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast; 5495 5496 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast; 5497 5498 struct mlx5_ifc_traffic_counter_bits received_eth_unicast; 5499 5500 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast; 5501 5502 struct mlx5_ifc_traffic_counter_bits received_eth_multicast; 5503 5504 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast; 5505 5506 struct mlx5_ifc_traffic_counter_bits local_loopback; 5507 5508 u8 reserved_at_700[0x980]; 5509 }; 5510 5511 enum { 5512 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0, 5513 }; 5514 5515 struct mlx5_ifc_query_vport_counter_in_bits { 5516 u8 opcode[0x10]; 5517 u8 reserved_at_10[0x10]; 5518 5519 u8 reserved_at_20[0x10]; 5520 u8 op_mod[0x10]; 5521 5522 u8 other_vport[0x1]; 5523 u8 reserved_at_41[0xb]; 5524 u8 port_num[0x4]; 5525 u8 vport_number[0x10]; 5526 5527 u8 reserved_at_60[0x60]; 5528 5529 u8 clear[0x1]; 5530 u8 reserved_at_c1[0x1f]; 5531 5532 u8 reserved_at_e0[0x20]; 5533 }; 5534 5535 struct mlx5_ifc_query_tis_out_bits { 5536 u8 status[0x8]; 5537 u8 reserved_at_8[0x18]; 5538 5539 u8 syndrome[0x20]; 5540 5541 u8 reserved_at_40[0x40]; 5542 5543 struct mlx5_ifc_tisc_bits tis_context; 5544 }; 5545 5546 struct mlx5_ifc_query_tis_in_bits { 5547 u8 opcode[0x10]; 5548 u8 reserved_at_10[0x10]; 5549 5550 u8 reserved_at_20[0x10]; 5551 u8 op_mod[0x10]; 5552 5553 u8 reserved_at_40[0x8]; 5554 u8 tisn[0x18]; 5555 5556 u8 reserved_at_60[0x20]; 5557 }; 5558 5559 struct mlx5_ifc_query_tir_out_bits { 5560 u8 status[0x8]; 5561 u8 reserved_at_8[0x18]; 5562 5563 u8 syndrome[0x20]; 5564 5565 u8 reserved_at_40[0xc0]; 5566 5567 struct mlx5_ifc_tirc_bits tir_context; 5568 }; 5569 5570 struct mlx5_ifc_query_tir_in_bits { 5571 u8 opcode[0x10]; 5572 u8 reserved_at_10[0x10]; 5573 5574 u8 reserved_at_20[0x10]; 5575 u8 op_mod[0x10]; 5576 5577 u8 reserved_at_40[0x8]; 5578 u8 tirn[0x18]; 5579 5580 u8 reserved_at_60[0x20]; 5581 }; 5582 5583 struct mlx5_ifc_query_srq_out_bits { 5584 u8 status[0x8]; 5585 u8 reserved_at_8[0x18]; 5586 5587 u8 syndrome[0x20]; 5588 5589 u8 reserved_at_40[0x40]; 5590 5591 struct mlx5_ifc_srqc_bits srq_context_entry; 5592 5593 u8 reserved_at_280[0x600]; 5594 5595 u8 pas[][0x40]; 5596 }; 5597 5598 struct mlx5_ifc_query_srq_in_bits { 5599 u8 opcode[0x10]; 5600 u8 reserved_at_10[0x10]; 5601 5602 u8 reserved_at_20[0x10]; 5603 u8 op_mod[0x10]; 5604 5605 u8 reserved_at_40[0x8]; 5606 u8 srqn[0x18]; 5607 5608 u8 reserved_at_60[0x20]; 5609 }; 5610 5611 struct mlx5_ifc_query_sq_out_bits { 5612 u8 status[0x8]; 5613 u8 reserved_at_8[0x18]; 5614 5615 u8 syndrome[0x20]; 5616 5617 u8 reserved_at_40[0xc0]; 5618 5619 struct mlx5_ifc_sqc_bits sq_context; 5620 }; 5621 5622 struct mlx5_ifc_query_sq_in_bits { 5623 u8 opcode[0x10]; 5624 u8 reserved_at_10[0x10]; 5625 5626 u8 reserved_at_20[0x10]; 5627 u8 op_mod[0x10]; 5628 5629 u8 reserved_at_40[0x8]; 5630 u8 sqn[0x18]; 5631 5632 u8 reserved_at_60[0x20]; 5633 }; 5634 5635 struct mlx5_ifc_query_special_contexts_out_bits { 5636 u8 status[0x8]; 5637 u8 reserved_at_8[0x18]; 5638 5639 u8 syndrome[0x20]; 5640 5641 u8 dump_fill_mkey[0x20]; 5642 5643 u8 resd_lkey[0x20]; 5644 5645 u8 null_mkey[0x20]; 5646 5647 u8 terminate_scatter_list_mkey[0x20]; 5648 5649 u8 repeated_mkey[0x20]; 5650 5651 u8 reserved_at_a0[0x20]; 5652 }; 5653 5654 struct mlx5_ifc_query_special_contexts_in_bits { 5655 u8 opcode[0x10]; 5656 u8 reserved_at_10[0x10]; 5657 5658 u8 reserved_at_20[0x10]; 5659 u8 op_mod[0x10]; 5660 5661 u8 reserved_at_40[0x40]; 5662 }; 5663 5664 struct mlx5_ifc_query_scheduling_element_out_bits { 5665 u8 opcode[0x10]; 5666 u8 reserved_at_10[0x10]; 5667 5668 u8 reserved_at_20[0x10]; 5669 u8 op_mod[0x10]; 5670 5671 u8 reserved_at_40[0xc0]; 5672 5673 struct mlx5_ifc_scheduling_context_bits scheduling_context; 5674 5675 u8 reserved_at_300[0x100]; 5676 }; 5677 5678 enum { 5679 SCHEDULING_HIERARCHY_E_SWITCH = 0x2, 5680 SCHEDULING_HIERARCHY_NIC = 0x3, 5681 }; 5682 5683 struct mlx5_ifc_query_scheduling_element_in_bits { 5684 u8 opcode[0x10]; 5685 u8 reserved_at_10[0x10]; 5686 5687 u8 reserved_at_20[0x10]; 5688 u8 op_mod[0x10]; 5689 5690 u8 scheduling_hierarchy[0x8]; 5691 u8 reserved_at_48[0x18]; 5692 5693 u8 scheduling_element_id[0x20]; 5694 5695 u8 reserved_at_80[0x180]; 5696 }; 5697 5698 struct mlx5_ifc_query_rqt_out_bits { 5699 u8 status[0x8]; 5700 u8 reserved_at_8[0x18]; 5701 5702 u8 syndrome[0x20]; 5703 5704 u8 reserved_at_40[0xc0]; 5705 5706 struct mlx5_ifc_rqtc_bits rqt_context; 5707 }; 5708 5709 struct mlx5_ifc_query_rqt_in_bits { 5710 u8 opcode[0x10]; 5711 u8 reserved_at_10[0x10]; 5712 5713 u8 reserved_at_20[0x10]; 5714 u8 op_mod[0x10]; 5715 5716 u8 reserved_at_40[0x8]; 5717 u8 rqtn[0x18]; 5718 5719 u8 reserved_at_60[0x20]; 5720 }; 5721 5722 struct mlx5_ifc_query_rq_out_bits { 5723 u8 status[0x8]; 5724 u8 reserved_at_8[0x18]; 5725 5726 u8 syndrome[0x20]; 5727 5728 u8 reserved_at_40[0xc0]; 5729 5730 struct mlx5_ifc_rqc_bits rq_context; 5731 }; 5732 5733 struct mlx5_ifc_query_rq_in_bits { 5734 u8 opcode[0x10]; 5735 u8 reserved_at_10[0x10]; 5736 5737 u8 reserved_at_20[0x10]; 5738 u8 op_mod[0x10]; 5739 5740 u8 reserved_at_40[0x8]; 5741 u8 rqn[0x18]; 5742 5743 u8 reserved_at_60[0x20]; 5744 }; 5745 5746 struct mlx5_ifc_query_roce_address_out_bits { 5747 u8 status[0x8]; 5748 u8 reserved_at_8[0x18]; 5749 5750 u8 syndrome[0x20]; 5751 5752 u8 reserved_at_40[0x40]; 5753 5754 struct mlx5_ifc_roce_addr_layout_bits roce_address; 5755 }; 5756 5757 struct mlx5_ifc_query_roce_address_in_bits { 5758 u8 opcode[0x10]; 5759 u8 reserved_at_10[0x10]; 5760 5761 u8 reserved_at_20[0x10]; 5762 u8 op_mod[0x10]; 5763 5764 u8 roce_address_index[0x10]; 5765 u8 reserved_at_50[0xc]; 5766 u8 vhca_port_num[0x4]; 5767 5768 u8 reserved_at_60[0x20]; 5769 }; 5770 5771 struct mlx5_ifc_query_rmp_out_bits { 5772 u8 status[0x8]; 5773 u8 reserved_at_8[0x18]; 5774 5775 u8 syndrome[0x20]; 5776 5777 u8 reserved_at_40[0xc0]; 5778 5779 struct mlx5_ifc_rmpc_bits rmp_context; 5780 }; 5781 5782 struct mlx5_ifc_query_rmp_in_bits { 5783 u8 opcode[0x10]; 5784 u8 reserved_at_10[0x10]; 5785 5786 u8 reserved_at_20[0x10]; 5787 u8 op_mod[0x10]; 5788 5789 u8 reserved_at_40[0x8]; 5790 u8 rmpn[0x18]; 5791 5792 u8 reserved_at_60[0x20]; 5793 }; 5794 5795 struct mlx5_ifc_cqe_error_syndrome_bits { 5796 u8 hw_error_syndrome[0x8]; 5797 u8 hw_syndrome_type[0x4]; 5798 u8 reserved_at_c[0x4]; 5799 u8 vendor_error_syndrome[0x8]; 5800 u8 syndrome[0x8]; 5801 }; 5802 5803 struct mlx5_ifc_qp_context_extension_bits { 5804 u8 reserved_at_0[0x60]; 5805 5806 struct mlx5_ifc_cqe_error_syndrome_bits error_syndrome; 5807 5808 u8 reserved_at_80[0x580]; 5809 }; 5810 5811 struct mlx5_ifc_qpc_extension_and_pas_list_in_bits { 5812 struct mlx5_ifc_qp_context_extension_bits qpc_data_extension; 5813 5814 u8 pas[0][0x40]; 5815 }; 5816 5817 struct mlx5_ifc_qp_pas_list_in_bits { 5818 struct mlx5_ifc_cmd_pas_bits pas[0]; 5819 }; 5820 5821 union mlx5_ifc_qp_pas_or_qpc_ext_and_pas_bits { 5822 struct mlx5_ifc_qp_pas_list_in_bits qp_pas_list; 5823 struct mlx5_ifc_qpc_extension_and_pas_list_in_bits qpc_ext_and_pas_list; 5824 }; 5825 5826 struct mlx5_ifc_query_qp_out_bits { 5827 u8 status[0x8]; 5828 u8 reserved_at_8[0x18]; 5829 5830 u8 syndrome[0x20]; 5831 5832 u8 reserved_at_40[0x40]; 5833 5834 u8 opt_param_mask[0x20]; 5835 5836 u8 ece[0x20]; 5837 5838 struct mlx5_ifc_qpc_bits qpc; 5839 5840 u8 reserved_at_800[0x80]; 5841 5842 union mlx5_ifc_qp_pas_or_qpc_ext_and_pas_bits qp_pas_or_qpc_ext_and_pas; 5843 }; 5844 5845 struct mlx5_ifc_query_qp_in_bits { 5846 u8 opcode[0x10]; 5847 u8 reserved_at_10[0x10]; 5848 5849 u8 reserved_at_20[0x10]; 5850 u8 op_mod[0x10]; 5851 5852 u8 qpc_ext[0x1]; 5853 u8 reserved_at_41[0x7]; 5854 u8 qpn[0x18]; 5855 5856 u8 reserved_at_60[0x20]; 5857 }; 5858 5859 struct mlx5_ifc_query_q_counter_out_bits { 5860 u8 status[0x8]; 5861 u8 reserved_at_8[0x18]; 5862 5863 u8 syndrome[0x20]; 5864 5865 u8 reserved_at_40[0x40]; 5866 5867 u8 rx_write_requests[0x20]; 5868 5869 u8 reserved_at_a0[0x20]; 5870 5871 u8 rx_read_requests[0x20]; 5872 5873 u8 reserved_at_e0[0x20]; 5874 5875 u8 rx_atomic_requests[0x20]; 5876 5877 u8 reserved_at_120[0x20]; 5878 5879 u8 rx_dct_connect[0x20]; 5880 5881 u8 reserved_at_160[0x20]; 5882 5883 u8 out_of_buffer[0x20]; 5884 5885 u8 reserved_at_1a0[0x20]; 5886 5887 u8 out_of_sequence[0x20]; 5888 5889 u8 reserved_at_1e0[0x20]; 5890 5891 u8 duplicate_request[0x20]; 5892 5893 u8 reserved_at_220[0x20]; 5894 5895 u8 rnr_nak_retry_err[0x20]; 5896 5897 u8 reserved_at_260[0x20]; 5898 5899 u8 packet_seq_err[0x20]; 5900 5901 u8 reserved_at_2a0[0x20]; 5902 5903 u8 implied_nak_seq_err[0x20]; 5904 5905 u8 reserved_at_2e0[0x20]; 5906 5907 u8 local_ack_timeout_err[0x20]; 5908 5909 u8 reserved_at_320[0x60]; 5910 5911 u8 req_rnr_retries_exceeded[0x20]; 5912 5913 u8 reserved_at_3a0[0x20]; 5914 5915 u8 resp_local_length_error[0x20]; 5916 5917 u8 req_local_length_error[0x20]; 5918 5919 u8 resp_local_qp_error[0x20]; 5920 5921 u8 local_operation_error[0x20]; 5922 5923 u8 resp_local_protection[0x20]; 5924 5925 u8 req_local_protection[0x20]; 5926 5927 u8 resp_cqe_error[0x20]; 5928 5929 u8 req_cqe_error[0x20]; 5930 5931 u8 req_mw_binding[0x20]; 5932 5933 u8 req_bad_response[0x20]; 5934 5935 u8 req_remote_invalid_request[0x20]; 5936 5937 u8 resp_remote_invalid_request[0x20]; 5938 5939 u8 req_remote_access_errors[0x20]; 5940 5941 u8 resp_remote_access_errors[0x20]; 5942 5943 u8 req_remote_operation_errors[0x20]; 5944 5945 u8 req_transport_retries_exceeded[0x20]; 5946 5947 u8 cq_overflow[0x20]; 5948 5949 u8 resp_cqe_flush_error[0x20]; 5950 5951 u8 req_cqe_flush_error[0x20]; 5952 5953 u8 reserved_at_620[0x20]; 5954 5955 u8 roce_adp_retrans[0x20]; 5956 5957 u8 roce_adp_retrans_to[0x20]; 5958 5959 u8 roce_slow_restart[0x20]; 5960 5961 u8 roce_slow_restart_cnps[0x20]; 5962 5963 u8 roce_slow_restart_trans[0x20]; 5964 5965 u8 reserved_at_6e0[0x120]; 5966 }; 5967 5968 struct mlx5_ifc_query_q_counter_in_bits { 5969 u8 opcode[0x10]; 5970 u8 reserved_at_10[0x10]; 5971 5972 u8 reserved_at_20[0x10]; 5973 u8 op_mod[0x10]; 5974 5975 u8 other_vport[0x1]; 5976 u8 reserved_at_41[0xf]; 5977 u8 vport_number[0x10]; 5978 5979 u8 reserved_at_60[0x60]; 5980 5981 u8 clear[0x1]; 5982 u8 aggregate[0x1]; 5983 u8 reserved_at_c2[0x1e]; 5984 5985 u8 reserved_at_e0[0x18]; 5986 u8 counter_set_id[0x8]; 5987 }; 5988 5989 struct mlx5_ifc_query_pages_out_bits { 5990 u8 status[0x8]; 5991 u8 reserved_at_8[0x18]; 5992 5993 u8 syndrome[0x20]; 5994 5995 u8 embedded_cpu_function[0x1]; 5996 u8 reserved_at_41[0xf]; 5997 u8 function_id[0x10]; 5998 5999 u8 num_pages[0x20]; 6000 }; 6001 6002 enum { 6003 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1, 6004 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2, 6005 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3, 6006 }; 6007 6008 struct mlx5_ifc_query_pages_in_bits { 6009 u8 opcode[0x10]; 6010 u8 reserved_at_10[0x10]; 6011 6012 u8 reserved_at_20[0x10]; 6013 u8 op_mod[0x10]; 6014 6015 u8 embedded_cpu_function[0x1]; 6016 u8 reserved_at_41[0xf]; 6017 u8 function_id[0x10]; 6018 6019 u8 reserved_at_60[0x20]; 6020 }; 6021 6022 struct mlx5_ifc_query_nic_vport_context_out_bits { 6023 u8 status[0x8]; 6024 u8 reserved_at_8[0x18]; 6025 6026 u8 syndrome[0x20]; 6027 6028 u8 reserved_at_40[0x40]; 6029 6030 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 6031 }; 6032 6033 struct mlx5_ifc_query_nic_vport_context_in_bits { 6034 u8 opcode[0x10]; 6035 u8 reserved_at_10[0x10]; 6036 6037 u8 reserved_at_20[0x10]; 6038 u8 op_mod[0x10]; 6039 6040 u8 other_vport[0x1]; 6041 u8 reserved_at_41[0xf]; 6042 u8 vport_number[0x10]; 6043 6044 u8 reserved_at_60[0x5]; 6045 u8 allowed_list_type[0x3]; 6046 u8 reserved_at_68[0x18]; 6047 }; 6048 6049 struct mlx5_ifc_query_mkey_out_bits { 6050 u8 status[0x8]; 6051 u8 reserved_at_8[0x18]; 6052 6053 u8 syndrome[0x20]; 6054 6055 u8 reserved_at_40[0x40]; 6056 6057 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 6058 6059 u8 reserved_at_280[0x600]; 6060 6061 u8 bsf0_klm0_pas_mtt0_1[16][0x8]; 6062 6063 u8 bsf1_klm1_pas_mtt2_3[16][0x8]; 6064 }; 6065 6066 struct mlx5_ifc_query_mkey_in_bits { 6067 u8 opcode[0x10]; 6068 u8 reserved_at_10[0x10]; 6069 6070 u8 reserved_at_20[0x10]; 6071 u8 op_mod[0x10]; 6072 6073 u8 reserved_at_40[0x8]; 6074 u8 mkey_index[0x18]; 6075 6076 u8 pg_access[0x1]; 6077 u8 reserved_at_61[0x1f]; 6078 }; 6079 6080 struct mlx5_ifc_query_mad_demux_out_bits { 6081 u8 status[0x8]; 6082 u8 reserved_at_8[0x18]; 6083 6084 u8 syndrome[0x20]; 6085 6086 u8 reserved_at_40[0x40]; 6087 6088 u8 mad_dumux_parameters_block[0x20]; 6089 }; 6090 6091 struct mlx5_ifc_query_mad_demux_in_bits { 6092 u8 opcode[0x10]; 6093 u8 reserved_at_10[0x10]; 6094 6095 u8 reserved_at_20[0x10]; 6096 u8 op_mod[0x10]; 6097 6098 u8 reserved_at_40[0x40]; 6099 }; 6100 6101 struct mlx5_ifc_query_l2_table_entry_out_bits { 6102 u8 status[0x8]; 6103 u8 reserved_at_8[0x18]; 6104 6105 u8 syndrome[0x20]; 6106 6107 u8 reserved_at_40[0xa0]; 6108 6109 u8 reserved_at_e0[0x13]; 6110 u8 vlan_valid[0x1]; 6111 u8 vlan[0xc]; 6112 6113 struct mlx5_ifc_mac_address_layout_bits mac_address; 6114 6115 u8 reserved_at_140[0xc0]; 6116 }; 6117 6118 struct mlx5_ifc_query_l2_table_entry_in_bits { 6119 u8 opcode[0x10]; 6120 u8 reserved_at_10[0x10]; 6121 6122 u8 reserved_at_20[0x10]; 6123 u8 op_mod[0x10]; 6124 6125 u8 reserved_at_40[0x60]; 6126 6127 u8 reserved_at_a0[0x8]; 6128 u8 table_index[0x18]; 6129 6130 u8 reserved_at_c0[0x140]; 6131 }; 6132 6133 struct mlx5_ifc_query_issi_out_bits { 6134 u8 status[0x8]; 6135 u8 reserved_at_8[0x18]; 6136 6137 u8 syndrome[0x20]; 6138 6139 u8 reserved_at_40[0x10]; 6140 u8 current_issi[0x10]; 6141 6142 u8 reserved_at_60[0xa0]; 6143 6144 u8 reserved_at_100[76][0x8]; 6145 u8 supported_issi_dw0[0x20]; 6146 }; 6147 6148 struct mlx5_ifc_query_issi_in_bits { 6149 u8 opcode[0x10]; 6150 u8 reserved_at_10[0x10]; 6151 6152 u8 reserved_at_20[0x10]; 6153 u8 op_mod[0x10]; 6154 6155 u8 reserved_at_40[0x40]; 6156 }; 6157 6158 struct mlx5_ifc_set_driver_version_out_bits { 6159 u8 status[0x8]; 6160 u8 reserved_0[0x18]; 6161 6162 u8 syndrome[0x20]; 6163 u8 reserved_1[0x40]; 6164 }; 6165 6166 struct mlx5_ifc_set_driver_version_in_bits { 6167 u8 opcode[0x10]; 6168 u8 reserved_0[0x10]; 6169 6170 u8 reserved_1[0x10]; 6171 u8 op_mod[0x10]; 6172 6173 u8 reserved_2[0x40]; 6174 u8 driver_version[64][0x8]; 6175 }; 6176 6177 struct mlx5_ifc_query_hca_vport_pkey_out_bits { 6178 u8 status[0x8]; 6179 u8 reserved_at_8[0x18]; 6180 6181 u8 syndrome[0x20]; 6182 6183 u8 reserved_at_40[0x40]; 6184 6185 struct mlx5_ifc_pkey_bits pkey[]; 6186 }; 6187 6188 struct mlx5_ifc_query_hca_vport_pkey_in_bits { 6189 u8 opcode[0x10]; 6190 u8 reserved_at_10[0x10]; 6191 6192 u8 reserved_at_20[0x10]; 6193 u8 op_mod[0x10]; 6194 6195 u8 other_vport[0x1]; 6196 u8 reserved_at_41[0xb]; 6197 u8 port_num[0x4]; 6198 u8 vport_number[0x10]; 6199 6200 u8 reserved_at_60[0x10]; 6201 u8 pkey_index[0x10]; 6202 }; 6203 6204 enum { 6205 MLX5_HCA_VPORT_SEL_PORT_GUID = 1 << 0, 6206 MLX5_HCA_VPORT_SEL_NODE_GUID = 1 << 1, 6207 MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2, 6208 }; 6209 6210 struct mlx5_ifc_query_hca_vport_gid_out_bits { 6211 u8 status[0x8]; 6212 u8 reserved_at_8[0x18]; 6213 6214 u8 syndrome[0x20]; 6215 6216 u8 reserved_at_40[0x20]; 6217 6218 u8 gids_num[0x10]; 6219 u8 reserved_at_70[0x10]; 6220 6221 struct mlx5_ifc_array128_auto_bits gid[]; 6222 }; 6223 6224 struct mlx5_ifc_query_hca_vport_gid_in_bits { 6225 u8 opcode[0x10]; 6226 u8 reserved_at_10[0x10]; 6227 6228 u8 reserved_at_20[0x10]; 6229 u8 op_mod[0x10]; 6230 6231 u8 other_vport[0x1]; 6232 u8 reserved_at_41[0xb]; 6233 u8 port_num[0x4]; 6234 u8 vport_number[0x10]; 6235 6236 u8 reserved_at_60[0x10]; 6237 u8 gid_index[0x10]; 6238 }; 6239 6240 struct mlx5_ifc_query_hca_vport_context_out_bits { 6241 u8 status[0x8]; 6242 u8 reserved_at_8[0x18]; 6243 6244 u8 syndrome[0x20]; 6245 6246 u8 reserved_at_40[0x40]; 6247 6248 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 6249 }; 6250 6251 struct mlx5_ifc_query_hca_vport_context_in_bits { 6252 u8 opcode[0x10]; 6253 u8 reserved_at_10[0x10]; 6254 6255 u8 reserved_at_20[0x10]; 6256 u8 op_mod[0x10]; 6257 6258 u8 other_vport[0x1]; 6259 u8 reserved_at_41[0xb]; 6260 u8 port_num[0x4]; 6261 u8 vport_number[0x10]; 6262 6263 u8 reserved_at_60[0x20]; 6264 }; 6265 6266 struct mlx5_ifc_query_hca_cap_out_bits { 6267 u8 status[0x8]; 6268 u8 reserved_at_8[0x18]; 6269 6270 u8 syndrome[0x20]; 6271 6272 u8 reserved_at_40[0x40]; 6273 6274 union mlx5_ifc_hca_cap_union_bits capability; 6275 }; 6276 6277 struct mlx5_ifc_query_hca_cap_in_bits { 6278 u8 opcode[0x10]; 6279 u8 reserved_at_10[0x10]; 6280 6281 u8 reserved_at_20[0x10]; 6282 u8 op_mod[0x10]; 6283 6284 u8 other_function[0x1]; 6285 u8 ec_vf_function[0x1]; 6286 u8 reserved_at_42[0xe]; 6287 u8 function_id[0x10]; 6288 6289 u8 reserved_at_60[0x20]; 6290 }; 6291 6292 struct mlx5_ifc_other_hca_cap_bits { 6293 u8 roce[0x1]; 6294 u8 reserved_at_1[0x27f]; 6295 }; 6296 6297 struct mlx5_ifc_query_other_hca_cap_out_bits { 6298 u8 status[0x8]; 6299 u8 reserved_at_8[0x18]; 6300 6301 u8 syndrome[0x20]; 6302 6303 u8 reserved_at_40[0x40]; 6304 6305 struct mlx5_ifc_other_hca_cap_bits other_capability; 6306 }; 6307 6308 struct mlx5_ifc_query_other_hca_cap_in_bits { 6309 u8 opcode[0x10]; 6310 u8 reserved_at_10[0x10]; 6311 6312 u8 reserved_at_20[0x10]; 6313 u8 op_mod[0x10]; 6314 6315 u8 reserved_at_40[0x10]; 6316 u8 function_id[0x10]; 6317 6318 u8 reserved_at_60[0x20]; 6319 }; 6320 6321 struct mlx5_ifc_modify_other_hca_cap_out_bits { 6322 u8 status[0x8]; 6323 u8 reserved_at_8[0x18]; 6324 6325 u8 syndrome[0x20]; 6326 6327 u8 reserved_at_40[0x40]; 6328 }; 6329 6330 struct mlx5_ifc_modify_other_hca_cap_in_bits { 6331 u8 opcode[0x10]; 6332 u8 reserved_at_10[0x10]; 6333 6334 u8 reserved_at_20[0x10]; 6335 u8 op_mod[0x10]; 6336 6337 u8 reserved_at_40[0x10]; 6338 u8 function_id[0x10]; 6339 u8 field_select[0x20]; 6340 6341 struct mlx5_ifc_other_hca_cap_bits other_capability; 6342 }; 6343 6344 struct mlx5_ifc_sw_owner_icm_root_params_bits { 6345 u8 sw_owner_icm_root_1[0x40]; 6346 6347 u8 sw_owner_icm_root_0[0x40]; 6348 }; 6349 6350 struct mlx5_ifc_rtc_params_bits { 6351 u8 rtc_id_0[0x20]; 6352 6353 u8 rtc_id_1[0x20]; 6354 6355 u8 reserved_at_40[0x40]; 6356 }; 6357 6358 struct mlx5_ifc_flow_table_context_bits { 6359 u8 reformat_en[0x1]; 6360 u8 decap_en[0x1]; 6361 u8 sw_owner[0x1]; 6362 u8 termination_table[0x1]; 6363 u8 table_miss_action[0x4]; 6364 u8 level[0x8]; 6365 u8 rtc_valid[0x1]; 6366 u8 reserved_at_11[0x7]; 6367 u8 log_size[0x8]; 6368 6369 u8 reserved_at_20[0x8]; 6370 u8 table_miss_id[0x18]; 6371 6372 u8 reserved_at_40[0x8]; 6373 u8 lag_master_next_table_id[0x18]; 6374 6375 u8 reserved_at_60[0x60]; 6376 6377 union { 6378 struct mlx5_ifc_sw_owner_icm_root_params_bits sws; 6379 struct mlx5_ifc_rtc_params_bits hws; 6380 }; 6381 }; 6382 6383 struct mlx5_ifc_query_flow_table_out_bits { 6384 u8 status[0x8]; 6385 u8 reserved_at_8[0x18]; 6386 6387 u8 syndrome[0x20]; 6388 6389 u8 reserved_at_40[0x80]; 6390 6391 struct mlx5_ifc_flow_table_context_bits flow_table_context; 6392 }; 6393 6394 struct mlx5_ifc_query_flow_table_in_bits { 6395 u8 opcode[0x10]; 6396 u8 reserved_at_10[0x10]; 6397 6398 u8 reserved_at_20[0x10]; 6399 u8 op_mod[0x10]; 6400 6401 u8 reserved_at_40[0x40]; 6402 6403 u8 table_type[0x8]; 6404 u8 reserved_at_88[0x18]; 6405 6406 u8 reserved_at_a0[0x8]; 6407 u8 table_id[0x18]; 6408 6409 u8 reserved_at_c0[0x140]; 6410 }; 6411 6412 struct mlx5_ifc_query_fte_out_bits { 6413 u8 status[0x8]; 6414 u8 reserved_at_8[0x18]; 6415 6416 u8 syndrome[0x20]; 6417 6418 u8 reserved_at_40[0x1c0]; 6419 6420 struct mlx5_ifc_flow_context_bits flow_context; 6421 }; 6422 6423 struct mlx5_ifc_query_fte_in_bits { 6424 u8 opcode[0x10]; 6425 u8 reserved_at_10[0x10]; 6426 6427 u8 reserved_at_20[0x10]; 6428 u8 op_mod[0x10]; 6429 6430 u8 reserved_at_40[0x40]; 6431 6432 u8 table_type[0x8]; 6433 u8 reserved_at_88[0x18]; 6434 6435 u8 reserved_at_a0[0x8]; 6436 u8 table_id[0x18]; 6437 6438 u8 reserved_at_c0[0x40]; 6439 6440 u8 flow_index[0x20]; 6441 6442 u8 reserved_at_120[0xe0]; 6443 }; 6444 6445 struct mlx5_ifc_match_definer_format_0_bits { 6446 u8 reserved_at_0[0x100]; 6447 6448 u8 metadata_reg_c_0[0x20]; 6449 6450 u8 metadata_reg_c_1[0x20]; 6451 6452 u8 outer_dmac_47_16[0x20]; 6453 6454 u8 outer_dmac_15_0[0x10]; 6455 u8 outer_ethertype[0x10]; 6456 6457 u8 reserved_at_180[0x1]; 6458 u8 sx_sniffer[0x1]; 6459 u8 functional_lb[0x1]; 6460 u8 outer_ip_frag[0x1]; 6461 u8 outer_qp_type[0x2]; 6462 u8 outer_encap_type[0x2]; 6463 u8 port_number[0x2]; 6464 u8 outer_l3_type[0x2]; 6465 u8 outer_l4_type[0x2]; 6466 u8 outer_first_vlan_type[0x2]; 6467 u8 outer_first_vlan_prio[0x3]; 6468 u8 outer_first_vlan_cfi[0x1]; 6469 u8 outer_first_vlan_vid[0xc]; 6470 6471 u8 outer_l4_type_ext[0x4]; 6472 u8 reserved_at_1a4[0x2]; 6473 u8 outer_ipsec_layer[0x2]; 6474 u8 outer_l2_type[0x2]; 6475 u8 force_lb[0x1]; 6476 u8 outer_l2_ok[0x1]; 6477 u8 outer_l3_ok[0x1]; 6478 u8 outer_l4_ok[0x1]; 6479 u8 outer_second_vlan_type[0x2]; 6480 u8 outer_second_vlan_prio[0x3]; 6481 u8 outer_second_vlan_cfi[0x1]; 6482 u8 outer_second_vlan_vid[0xc]; 6483 6484 u8 outer_smac_47_16[0x20]; 6485 6486 u8 outer_smac_15_0[0x10]; 6487 u8 inner_ipv4_checksum_ok[0x1]; 6488 u8 inner_l4_checksum_ok[0x1]; 6489 u8 outer_ipv4_checksum_ok[0x1]; 6490 u8 outer_l4_checksum_ok[0x1]; 6491 u8 inner_l3_ok[0x1]; 6492 u8 inner_l4_ok[0x1]; 6493 u8 outer_l3_ok_duplicate[0x1]; 6494 u8 outer_l4_ok_duplicate[0x1]; 6495 u8 outer_tcp_cwr[0x1]; 6496 u8 outer_tcp_ece[0x1]; 6497 u8 outer_tcp_urg[0x1]; 6498 u8 outer_tcp_ack[0x1]; 6499 u8 outer_tcp_psh[0x1]; 6500 u8 outer_tcp_rst[0x1]; 6501 u8 outer_tcp_syn[0x1]; 6502 u8 outer_tcp_fin[0x1]; 6503 }; 6504 6505 struct mlx5_ifc_match_definer_format_22_bits { 6506 u8 reserved_at_0[0x100]; 6507 6508 u8 outer_ip_src_addr[0x20]; 6509 6510 u8 outer_ip_dest_addr[0x20]; 6511 6512 u8 outer_l4_sport[0x10]; 6513 u8 outer_l4_dport[0x10]; 6514 6515 u8 reserved_at_160[0x1]; 6516 u8 sx_sniffer[0x1]; 6517 u8 functional_lb[0x1]; 6518 u8 outer_ip_frag[0x1]; 6519 u8 outer_qp_type[0x2]; 6520 u8 outer_encap_type[0x2]; 6521 u8 port_number[0x2]; 6522 u8 outer_l3_type[0x2]; 6523 u8 outer_l4_type[0x2]; 6524 u8 outer_first_vlan_type[0x2]; 6525 u8 outer_first_vlan_prio[0x3]; 6526 u8 outer_first_vlan_cfi[0x1]; 6527 u8 outer_first_vlan_vid[0xc]; 6528 6529 u8 metadata_reg_c_0[0x20]; 6530 6531 u8 outer_dmac_47_16[0x20]; 6532 6533 u8 outer_smac_47_16[0x20]; 6534 6535 u8 outer_smac_15_0[0x10]; 6536 u8 outer_dmac_15_0[0x10]; 6537 }; 6538 6539 struct mlx5_ifc_match_definer_format_23_bits { 6540 u8 reserved_at_0[0x100]; 6541 6542 u8 inner_ip_src_addr[0x20]; 6543 6544 u8 inner_ip_dest_addr[0x20]; 6545 6546 u8 inner_l4_sport[0x10]; 6547 u8 inner_l4_dport[0x10]; 6548 6549 u8 reserved_at_160[0x1]; 6550 u8 sx_sniffer[0x1]; 6551 u8 functional_lb[0x1]; 6552 u8 inner_ip_frag[0x1]; 6553 u8 inner_qp_type[0x2]; 6554 u8 inner_encap_type[0x2]; 6555 u8 port_number[0x2]; 6556 u8 inner_l3_type[0x2]; 6557 u8 inner_l4_type[0x2]; 6558 u8 inner_first_vlan_type[0x2]; 6559 u8 inner_first_vlan_prio[0x3]; 6560 u8 inner_first_vlan_cfi[0x1]; 6561 u8 inner_first_vlan_vid[0xc]; 6562 6563 u8 tunnel_header_0[0x20]; 6564 6565 u8 inner_dmac_47_16[0x20]; 6566 6567 u8 inner_smac_47_16[0x20]; 6568 6569 u8 inner_smac_15_0[0x10]; 6570 u8 inner_dmac_15_0[0x10]; 6571 }; 6572 6573 struct mlx5_ifc_match_definer_format_29_bits { 6574 u8 reserved_at_0[0xc0]; 6575 6576 u8 outer_ip_dest_addr[0x80]; 6577 6578 u8 outer_ip_src_addr[0x80]; 6579 6580 u8 outer_l4_sport[0x10]; 6581 u8 outer_l4_dport[0x10]; 6582 6583 u8 reserved_at_1e0[0x20]; 6584 }; 6585 6586 struct mlx5_ifc_match_definer_format_30_bits { 6587 u8 reserved_at_0[0xa0]; 6588 6589 u8 outer_ip_dest_addr[0x80]; 6590 6591 u8 outer_ip_src_addr[0x80]; 6592 6593 u8 outer_dmac_47_16[0x20]; 6594 6595 u8 outer_smac_47_16[0x20]; 6596 6597 u8 outer_smac_15_0[0x10]; 6598 u8 outer_dmac_15_0[0x10]; 6599 }; 6600 6601 struct mlx5_ifc_match_definer_format_31_bits { 6602 u8 reserved_at_0[0xc0]; 6603 6604 u8 inner_ip_dest_addr[0x80]; 6605 6606 u8 inner_ip_src_addr[0x80]; 6607 6608 u8 inner_l4_sport[0x10]; 6609 u8 inner_l4_dport[0x10]; 6610 6611 u8 reserved_at_1e0[0x20]; 6612 }; 6613 6614 struct mlx5_ifc_match_definer_format_32_bits { 6615 u8 reserved_at_0[0xa0]; 6616 6617 u8 inner_ip_dest_addr[0x80]; 6618 6619 u8 inner_ip_src_addr[0x80]; 6620 6621 u8 inner_dmac_47_16[0x20]; 6622 6623 u8 inner_smac_47_16[0x20]; 6624 6625 u8 inner_smac_15_0[0x10]; 6626 u8 inner_dmac_15_0[0x10]; 6627 }; 6628 6629 enum { 6630 MLX5_IFC_DEFINER_FORMAT_ID_SELECT = 61, 6631 }; 6632 6633 #define MLX5_IFC_DEFINER_FORMAT_OFFSET_UNUSED 0x0 6634 #define MLX5_IFC_DEFINER_FORMAT_OFFSET_OUTER_ETH_PKT_LEN 0x48 6635 #define MLX5_IFC_DEFINER_DW_SELECTORS_NUM 9 6636 #define MLX5_IFC_DEFINER_BYTE_SELECTORS_NUM 8 6637 6638 struct mlx5_ifc_match_definer_match_mask_bits { 6639 u8 reserved_at_1c0[5][0x20]; 6640 u8 match_dw_8[0x20]; 6641 u8 match_dw_7[0x20]; 6642 u8 match_dw_6[0x20]; 6643 u8 match_dw_5[0x20]; 6644 u8 match_dw_4[0x20]; 6645 u8 match_dw_3[0x20]; 6646 u8 match_dw_2[0x20]; 6647 u8 match_dw_1[0x20]; 6648 u8 match_dw_0[0x20]; 6649 6650 u8 match_byte_7[0x8]; 6651 u8 match_byte_6[0x8]; 6652 u8 match_byte_5[0x8]; 6653 u8 match_byte_4[0x8]; 6654 6655 u8 match_byte_3[0x8]; 6656 u8 match_byte_2[0x8]; 6657 u8 match_byte_1[0x8]; 6658 u8 match_byte_0[0x8]; 6659 }; 6660 6661 struct mlx5_ifc_match_definer_bits { 6662 u8 modify_field_select[0x40]; 6663 6664 u8 reserved_at_40[0x40]; 6665 6666 u8 reserved_at_80[0x10]; 6667 u8 format_id[0x10]; 6668 6669 u8 reserved_at_a0[0x60]; 6670 6671 u8 format_select_dw3[0x8]; 6672 u8 format_select_dw2[0x8]; 6673 u8 format_select_dw1[0x8]; 6674 u8 format_select_dw0[0x8]; 6675 6676 u8 format_select_dw7[0x8]; 6677 u8 format_select_dw6[0x8]; 6678 u8 format_select_dw5[0x8]; 6679 u8 format_select_dw4[0x8]; 6680 6681 u8 reserved_at_100[0x18]; 6682 u8 format_select_dw8[0x8]; 6683 6684 u8 reserved_at_120[0x20]; 6685 6686 u8 format_select_byte3[0x8]; 6687 u8 format_select_byte2[0x8]; 6688 u8 format_select_byte1[0x8]; 6689 u8 format_select_byte0[0x8]; 6690 6691 u8 format_select_byte7[0x8]; 6692 u8 format_select_byte6[0x8]; 6693 u8 format_select_byte5[0x8]; 6694 u8 format_select_byte4[0x8]; 6695 6696 u8 reserved_at_180[0x40]; 6697 6698 union { 6699 struct { 6700 u8 match_mask[16][0x20]; 6701 }; 6702 struct mlx5_ifc_match_definer_match_mask_bits match_mask_format; 6703 }; 6704 }; 6705 6706 struct mlx5_ifc_general_obj_create_param_bits { 6707 u8 alias_object[0x1]; 6708 u8 reserved_at_1[0x2]; 6709 u8 log_obj_range[0x5]; 6710 u8 reserved_at_8[0x18]; 6711 }; 6712 6713 struct mlx5_ifc_general_obj_query_param_bits { 6714 u8 alias_object[0x1]; 6715 u8 obj_offset[0x1f]; 6716 }; 6717 6718 struct mlx5_ifc_general_obj_in_cmd_hdr_bits { 6719 u8 opcode[0x10]; 6720 u8 uid[0x10]; 6721 6722 u8 vhca_tunnel_id[0x10]; 6723 u8 obj_type[0x10]; 6724 6725 u8 obj_id[0x20]; 6726 6727 union { 6728 struct mlx5_ifc_general_obj_create_param_bits create; 6729 struct mlx5_ifc_general_obj_query_param_bits query; 6730 } op_param; 6731 }; 6732 6733 struct mlx5_ifc_general_obj_out_cmd_hdr_bits { 6734 u8 status[0x8]; 6735 u8 reserved_at_8[0x18]; 6736 6737 u8 syndrome[0x20]; 6738 6739 u8 obj_id[0x20]; 6740 6741 u8 reserved_at_60[0x20]; 6742 }; 6743 6744 struct mlx5_ifc_allow_other_vhca_access_in_bits { 6745 u8 opcode[0x10]; 6746 u8 uid[0x10]; 6747 u8 reserved_at_20[0x10]; 6748 u8 op_mod[0x10]; 6749 u8 reserved_at_40[0x50]; 6750 u8 object_type_to_be_accessed[0x10]; 6751 u8 object_id_to_be_accessed[0x20]; 6752 u8 reserved_at_c0[0x40]; 6753 union { 6754 u8 access_key_raw[0x100]; 6755 u8 access_key[8][0x20]; 6756 }; 6757 }; 6758 6759 struct mlx5_ifc_allow_other_vhca_access_out_bits { 6760 u8 status[0x8]; 6761 u8 reserved_at_8[0x18]; 6762 u8 syndrome[0x20]; 6763 u8 reserved_at_40[0x40]; 6764 }; 6765 6766 struct mlx5_ifc_modify_header_arg_bits { 6767 u8 reserved_at_0[0x80]; 6768 6769 u8 reserved_at_80[0x8]; 6770 u8 access_pd[0x18]; 6771 }; 6772 6773 struct mlx5_ifc_create_modify_header_arg_in_bits { 6774 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 6775 struct mlx5_ifc_modify_header_arg_bits arg; 6776 }; 6777 6778 struct mlx5_ifc_create_match_definer_in_bits { 6779 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 6780 6781 struct mlx5_ifc_match_definer_bits obj_context; 6782 }; 6783 6784 struct mlx5_ifc_create_match_definer_out_bits { 6785 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 6786 }; 6787 6788 struct mlx5_ifc_alias_context_bits { 6789 u8 vhca_id_to_be_accessed[0x10]; 6790 u8 reserved_at_10[0xd]; 6791 u8 status[0x3]; 6792 u8 object_id_to_be_accessed[0x20]; 6793 u8 reserved_at_40[0x40]; 6794 union { 6795 u8 access_key_raw[0x100]; 6796 u8 access_key[8][0x20]; 6797 }; 6798 u8 metadata[0x80]; 6799 }; 6800 6801 struct mlx5_ifc_create_alias_obj_in_bits { 6802 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 6803 struct mlx5_ifc_alias_context_bits alias_ctx; 6804 }; 6805 6806 enum { 6807 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 6808 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 6809 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 6810 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3, 6811 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_3 = 0x4, 6812 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_4 = 0x5, 6813 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_5 = 0x6, 6814 }; 6815 6816 struct mlx5_ifc_query_flow_group_out_bits { 6817 u8 status[0x8]; 6818 u8 reserved_at_8[0x18]; 6819 6820 u8 syndrome[0x20]; 6821 6822 u8 reserved_at_40[0xa0]; 6823 6824 u8 start_flow_index[0x20]; 6825 6826 u8 reserved_at_100[0x20]; 6827 6828 u8 end_flow_index[0x20]; 6829 6830 u8 reserved_at_140[0xa0]; 6831 6832 u8 reserved_at_1e0[0x18]; 6833 u8 match_criteria_enable[0x8]; 6834 6835 struct mlx5_ifc_fte_match_param_bits match_criteria; 6836 6837 u8 reserved_at_1200[0xe00]; 6838 }; 6839 6840 struct mlx5_ifc_query_flow_group_in_bits { 6841 u8 opcode[0x10]; 6842 u8 reserved_at_10[0x10]; 6843 6844 u8 reserved_at_20[0x10]; 6845 u8 op_mod[0x10]; 6846 6847 u8 reserved_at_40[0x40]; 6848 6849 u8 table_type[0x8]; 6850 u8 reserved_at_88[0x18]; 6851 6852 u8 reserved_at_a0[0x8]; 6853 u8 table_id[0x18]; 6854 6855 u8 group_id[0x20]; 6856 6857 u8 reserved_at_e0[0x120]; 6858 }; 6859 6860 struct mlx5_ifc_query_flow_counter_out_bits { 6861 u8 status[0x8]; 6862 u8 reserved_at_8[0x18]; 6863 6864 u8 syndrome[0x20]; 6865 6866 u8 reserved_at_40[0x40]; 6867 6868 struct mlx5_ifc_traffic_counter_bits flow_statistics[]; 6869 }; 6870 6871 struct mlx5_ifc_query_flow_counter_in_bits { 6872 u8 opcode[0x10]; 6873 u8 reserved_at_10[0x10]; 6874 6875 u8 reserved_at_20[0x10]; 6876 u8 op_mod[0x10]; 6877 6878 u8 reserved_at_40[0x80]; 6879 6880 u8 clear[0x1]; 6881 u8 reserved_at_c1[0xf]; 6882 u8 num_of_counters[0x10]; 6883 6884 u8 flow_counter_id[0x20]; 6885 }; 6886 6887 struct mlx5_ifc_query_esw_vport_context_out_bits { 6888 u8 status[0x8]; 6889 u8 reserved_at_8[0x18]; 6890 6891 u8 syndrome[0x20]; 6892 6893 u8 reserved_at_40[0x40]; 6894 6895 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 6896 }; 6897 6898 struct mlx5_ifc_query_esw_vport_context_in_bits { 6899 u8 opcode[0x10]; 6900 u8 reserved_at_10[0x10]; 6901 6902 u8 reserved_at_20[0x10]; 6903 u8 op_mod[0x10]; 6904 6905 u8 other_vport[0x1]; 6906 u8 reserved_at_41[0xf]; 6907 u8 vport_number[0x10]; 6908 6909 u8 reserved_at_60[0x20]; 6910 }; 6911 6912 struct mlx5_ifc_modify_esw_vport_context_out_bits { 6913 u8 status[0x8]; 6914 u8 reserved_at_8[0x18]; 6915 6916 u8 syndrome[0x20]; 6917 6918 u8 reserved_at_40[0x40]; 6919 }; 6920 6921 struct mlx5_ifc_esw_vport_context_fields_select_bits { 6922 u8 reserved_at_0[0x1b]; 6923 u8 fdb_to_vport_reg_c_id[0x1]; 6924 u8 vport_cvlan_insert[0x1]; 6925 u8 vport_svlan_insert[0x1]; 6926 u8 vport_cvlan_strip[0x1]; 6927 u8 vport_svlan_strip[0x1]; 6928 }; 6929 6930 struct mlx5_ifc_modify_esw_vport_context_in_bits { 6931 u8 opcode[0x10]; 6932 u8 reserved_at_10[0x10]; 6933 6934 u8 reserved_at_20[0x10]; 6935 u8 op_mod[0x10]; 6936 6937 u8 other_vport[0x1]; 6938 u8 reserved_at_41[0xf]; 6939 u8 vport_number[0x10]; 6940 6941 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select; 6942 6943 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 6944 }; 6945 6946 struct mlx5_ifc_query_eq_out_bits { 6947 u8 status[0x8]; 6948 u8 reserved_at_8[0x18]; 6949 6950 u8 syndrome[0x20]; 6951 6952 u8 reserved_at_40[0x40]; 6953 6954 struct mlx5_ifc_eqc_bits eq_context_entry; 6955 6956 u8 reserved_at_280[0x40]; 6957 6958 u8 event_bitmask[0x40]; 6959 6960 u8 reserved_at_300[0x580]; 6961 6962 u8 pas[][0x40]; 6963 }; 6964 6965 struct mlx5_ifc_query_eq_in_bits { 6966 u8 opcode[0x10]; 6967 u8 reserved_at_10[0x10]; 6968 6969 u8 reserved_at_20[0x10]; 6970 u8 op_mod[0x10]; 6971 6972 u8 reserved_at_40[0x18]; 6973 u8 eq_number[0x8]; 6974 6975 u8 reserved_at_60[0x20]; 6976 }; 6977 6978 struct mlx5_ifc_packet_reformat_context_in_bits { 6979 u8 reformat_type[0x8]; 6980 u8 reserved_at_8[0x4]; 6981 u8 reformat_param_0[0x4]; 6982 u8 reserved_at_10[0x6]; 6983 u8 reformat_data_size[0xa]; 6984 6985 u8 reformat_param_1[0x8]; 6986 u8 reserved_at_28[0x8]; 6987 u8 reformat_data[2][0x8]; 6988 6989 u8 more_reformat_data[][0x8]; 6990 }; 6991 6992 struct mlx5_ifc_query_packet_reformat_context_out_bits { 6993 u8 status[0x8]; 6994 u8 reserved_at_8[0x18]; 6995 6996 u8 syndrome[0x20]; 6997 6998 u8 reserved_at_40[0xa0]; 6999 7000 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context[]; 7001 }; 7002 7003 struct mlx5_ifc_query_packet_reformat_context_in_bits { 7004 u8 opcode[0x10]; 7005 u8 reserved_at_10[0x10]; 7006 7007 u8 reserved_at_20[0x10]; 7008 u8 op_mod[0x10]; 7009 7010 u8 packet_reformat_id[0x20]; 7011 7012 u8 reserved_at_60[0xa0]; 7013 }; 7014 7015 struct mlx5_ifc_alloc_packet_reformat_context_out_bits { 7016 u8 status[0x8]; 7017 u8 reserved_at_8[0x18]; 7018 7019 u8 syndrome[0x20]; 7020 7021 u8 packet_reformat_id[0x20]; 7022 7023 u8 reserved_at_60[0x20]; 7024 }; 7025 7026 enum { 7027 MLX5_REFORMAT_CONTEXT_ANCHOR_MAC_START = 0x1, 7028 MLX5_REFORMAT_CONTEXT_ANCHOR_VLAN_START = 0x2, 7029 MLX5_REFORMAT_CONTEXT_ANCHOR_IP_START = 0x7, 7030 MLX5_REFORMAT_CONTEXT_ANCHOR_TCP_UDP_START = 0x9, 7031 }; 7032 7033 enum mlx5_reformat_ctx_type { 7034 MLX5_REFORMAT_TYPE_L2_TO_VXLAN = 0x0, 7035 MLX5_REFORMAT_TYPE_L2_TO_NVGRE = 0x1, 7036 MLX5_REFORMAT_TYPE_L2_TO_L2_TUNNEL = 0x2, 7037 MLX5_REFORMAT_TYPE_L3_TUNNEL_TO_L2 = 0x3, 7038 MLX5_REFORMAT_TYPE_L2_TO_L3_TUNNEL = 0x4, 7039 MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_IPV4 = 0x5, 7040 MLX5_REFORMAT_TYPE_L2_TO_L3_ESP_TUNNEL = 0x6, 7041 MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_UDPV4 = 0x7, 7042 MLX5_REFORMAT_TYPE_DEL_ESP_TRANSPORT = 0x8, 7043 MLX5_REFORMAT_TYPE_L3_ESP_TUNNEL_TO_L2 = 0x9, 7044 MLX5_REFORMAT_TYPE_DEL_ESP_TRANSPORT_OVER_UDP = 0xa, 7045 MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_IPV6 = 0xb, 7046 MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_UDPV6 = 0xc, 7047 MLX5_REFORMAT_TYPE_INSERT_HDR = 0xf, 7048 MLX5_REFORMAT_TYPE_REMOVE_HDR = 0x10, 7049 MLX5_REFORMAT_TYPE_ADD_MACSEC = 0x11, 7050 MLX5_REFORMAT_TYPE_DEL_MACSEC = 0x12, 7051 }; 7052 7053 struct mlx5_ifc_alloc_packet_reformat_context_in_bits { 7054 u8 opcode[0x10]; 7055 u8 reserved_at_10[0x10]; 7056 7057 u8 reserved_at_20[0x10]; 7058 u8 op_mod[0x10]; 7059 7060 u8 reserved_at_40[0xa0]; 7061 7062 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context; 7063 }; 7064 7065 struct mlx5_ifc_dealloc_packet_reformat_context_out_bits { 7066 u8 status[0x8]; 7067 u8 reserved_at_8[0x18]; 7068 7069 u8 syndrome[0x20]; 7070 7071 u8 reserved_at_40[0x40]; 7072 }; 7073 7074 struct mlx5_ifc_dealloc_packet_reformat_context_in_bits { 7075 u8 opcode[0x10]; 7076 u8 reserved_at_10[0x10]; 7077 7078 u8 reserved_20[0x10]; 7079 u8 op_mod[0x10]; 7080 7081 u8 packet_reformat_id[0x20]; 7082 7083 u8 reserved_60[0x20]; 7084 }; 7085 7086 struct mlx5_ifc_set_action_in_bits { 7087 u8 action_type[0x4]; 7088 u8 field[0xc]; 7089 u8 reserved_at_10[0x3]; 7090 u8 offset[0x5]; 7091 u8 reserved_at_18[0x3]; 7092 u8 length[0x5]; 7093 7094 u8 data[0x20]; 7095 }; 7096 7097 struct mlx5_ifc_add_action_in_bits { 7098 u8 action_type[0x4]; 7099 u8 field[0xc]; 7100 u8 reserved_at_10[0x10]; 7101 7102 u8 data[0x20]; 7103 }; 7104 7105 struct mlx5_ifc_copy_action_in_bits { 7106 u8 action_type[0x4]; 7107 u8 src_field[0xc]; 7108 u8 reserved_at_10[0x3]; 7109 u8 src_offset[0x5]; 7110 u8 reserved_at_18[0x3]; 7111 u8 length[0x5]; 7112 7113 u8 reserved_at_20[0x4]; 7114 u8 dst_field[0xc]; 7115 u8 reserved_at_30[0x3]; 7116 u8 dst_offset[0x5]; 7117 u8 reserved_at_38[0x8]; 7118 }; 7119 7120 union mlx5_ifc_set_add_copy_action_in_auto_bits { 7121 struct mlx5_ifc_set_action_in_bits set_action_in; 7122 struct mlx5_ifc_add_action_in_bits add_action_in; 7123 struct mlx5_ifc_copy_action_in_bits copy_action_in; 7124 u8 reserved_at_0[0x40]; 7125 }; 7126 7127 enum { 7128 MLX5_ACTION_TYPE_SET = 0x1, 7129 MLX5_ACTION_TYPE_ADD = 0x2, 7130 MLX5_ACTION_TYPE_COPY = 0x3, 7131 }; 7132 7133 enum { 7134 MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16 = 0x1, 7135 MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0 = 0x2, 7136 MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE = 0x3, 7137 MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16 = 0x4, 7138 MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0 = 0x5, 7139 MLX5_ACTION_IN_FIELD_OUT_IP_DSCP = 0x6, 7140 MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS = 0x7, 7141 MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT = 0x8, 7142 MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT = 0x9, 7143 MLX5_ACTION_IN_FIELD_OUT_IP_TTL = 0xa, 7144 MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT = 0xb, 7145 MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT = 0xc, 7146 MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96 = 0xd, 7147 MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64 = 0xe, 7148 MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32 = 0xf, 7149 MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0 = 0x10, 7150 MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96 = 0x11, 7151 MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64 = 0x12, 7152 MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32 = 0x13, 7153 MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0 = 0x14, 7154 MLX5_ACTION_IN_FIELD_OUT_SIPV4 = 0x15, 7155 MLX5_ACTION_IN_FIELD_OUT_DIPV4 = 0x16, 7156 MLX5_ACTION_IN_FIELD_OUT_FIRST_VID = 0x17, 7157 MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47, 7158 MLX5_ACTION_IN_FIELD_METADATA_REG_A = 0x49, 7159 MLX5_ACTION_IN_FIELD_METADATA_REG_B = 0x50, 7160 MLX5_ACTION_IN_FIELD_METADATA_REG_C_0 = 0x51, 7161 MLX5_ACTION_IN_FIELD_METADATA_REG_C_1 = 0x52, 7162 MLX5_ACTION_IN_FIELD_METADATA_REG_C_2 = 0x53, 7163 MLX5_ACTION_IN_FIELD_METADATA_REG_C_3 = 0x54, 7164 MLX5_ACTION_IN_FIELD_METADATA_REG_C_4 = 0x55, 7165 MLX5_ACTION_IN_FIELD_METADATA_REG_C_5 = 0x56, 7166 MLX5_ACTION_IN_FIELD_METADATA_REG_C_6 = 0x57, 7167 MLX5_ACTION_IN_FIELD_METADATA_REG_C_7 = 0x58, 7168 MLX5_ACTION_IN_FIELD_OUT_TCP_SEQ_NUM = 0x59, 7169 MLX5_ACTION_IN_FIELD_OUT_TCP_ACK_NUM = 0x5B, 7170 MLX5_ACTION_IN_FIELD_IPSEC_SYNDROME = 0x5D, 7171 MLX5_ACTION_IN_FIELD_OUT_EMD_47_32 = 0x6F, 7172 MLX5_ACTION_IN_FIELD_OUT_EMD_31_0 = 0x70, 7173 }; 7174 7175 struct mlx5_ifc_alloc_modify_header_context_out_bits { 7176 u8 status[0x8]; 7177 u8 reserved_at_8[0x18]; 7178 7179 u8 syndrome[0x20]; 7180 7181 u8 modify_header_id[0x20]; 7182 7183 u8 reserved_at_60[0x20]; 7184 }; 7185 7186 struct mlx5_ifc_alloc_modify_header_context_in_bits { 7187 u8 opcode[0x10]; 7188 u8 reserved_at_10[0x10]; 7189 7190 u8 reserved_at_20[0x10]; 7191 u8 op_mod[0x10]; 7192 7193 u8 reserved_at_40[0x20]; 7194 7195 u8 table_type[0x8]; 7196 u8 reserved_at_68[0x10]; 7197 u8 num_of_actions[0x8]; 7198 7199 union mlx5_ifc_set_add_copy_action_in_auto_bits actions[]; 7200 }; 7201 7202 struct mlx5_ifc_dealloc_modify_header_context_out_bits { 7203 u8 status[0x8]; 7204 u8 reserved_at_8[0x18]; 7205 7206 u8 syndrome[0x20]; 7207 7208 u8 reserved_at_40[0x40]; 7209 }; 7210 7211 struct mlx5_ifc_dealloc_modify_header_context_in_bits { 7212 u8 opcode[0x10]; 7213 u8 reserved_at_10[0x10]; 7214 7215 u8 reserved_at_20[0x10]; 7216 u8 op_mod[0x10]; 7217 7218 u8 modify_header_id[0x20]; 7219 7220 u8 reserved_at_60[0x20]; 7221 }; 7222 7223 struct mlx5_ifc_query_modify_header_context_in_bits { 7224 u8 opcode[0x10]; 7225 u8 uid[0x10]; 7226 7227 u8 reserved_at_20[0x10]; 7228 u8 op_mod[0x10]; 7229 7230 u8 modify_header_id[0x20]; 7231 7232 u8 reserved_at_60[0xa0]; 7233 }; 7234 7235 struct mlx5_ifc_query_dct_out_bits { 7236 u8 status[0x8]; 7237 u8 reserved_at_8[0x18]; 7238 7239 u8 syndrome[0x20]; 7240 7241 u8 reserved_at_40[0x40]; 7242 7243 struct mlx5_ifc_dctc_bits dct_context_entry; 7244 7245 u8 reserved_at_280[0x180]; 7246 }; 7247 7248 struct mlx5_ifc_query_dct_in_bits { 7249 u8 opcode[0x10]; 7250 u8 reserved_at_10[0x10]; 7251 7252 u8 reserved_at_20[0x10]; 7253 u8 op_mod[0x10]; 7254 7255 u8 reserved_at_40[0x8]; 7256 u8 dctn[0x18]; 7257 7258 u8 reserved_at_60[0x20]; 7259 }; 7260 7261 struct mlx5_ifc_query_cq_out_bits { 7262 u8 status[0x8]; 7263 u8 reserved_at_8[0x18]; 7264 7265 u8 syndrome[0x20]; 7266 7267 u8 reserved_at_40[0x40]; 7268 7269 struct mlx5_ifc_cqc_bits cq_context; 7270 7271 u8 reserved_at_280[0x600]; 7272 7273 u8 pas[][0x40]; 7274 }; 7275 7276 struct mlx5_ifc_query_cq_in_bits { 7277 u8 opcode[0x10]; 7278 u8 reserved_at_10[0x10]; 7279 7280 u8 reserved_at_20[0x10]; 7281 u8 op_mod[0x10]; 7282 7283 u8 reserved_at_40[0x8]; 7284 u8 cqn[0x18]; 7285 7286 u8 reserved_at_60[0x20]; 7287 }; 7288 7289 struct mlx5_ifc_query_cong_status_out_bits { 7290 u8 status[0x8]; 7291 u8 reserved_at_8[0x18]; 7292 7293 u8 syndrome[0x20]; 7294 7295 u8 reserved_at_40[0x20]; 7296 7297 u8 enable[0x1]; 7298 u8 tag_enable[0x1]; 7299 u8 reserved_at_62[0x1e]; 7300 }; 7301 7302 struct mlx5_ifc_query_cong_status_in_bits { 7303 u8 opcode[0x10]; 7304 u8 reserved_at_10[0x10]; 7305 7306 u8 reserved_at_20[0x10]; 7307 u8 op_mod[0x10]; 7308 7309 u8 reserved_at_40[0x18]; 7310 u8 priority[0x4]; 7311 u8 cong_protocol[0x4]; 7312 7313 u8 reserved_at_60[0x20]; 7314 }; 7315 7316 struct mlx5_ifc_query_cong_statistics_out_bits { 7317 u8 status[0x8]; 7318 u8 reserved_at_8[0x18]; 7319 7320 u8 syndrome[0x20]; 7321 7322 u8 reserved_at_40[0x40]; 7323 7324 u8 rp_cur_flows[0x20]; 7325 7326 u8 sum_flows[0x20]; 7327 7328 u8 rp_cnp_ignored_high[0x20]; 7329 7330 u8 rp_cnp_ignored_low[0x20]; 7331 7332 u8 rp_cnp_handled_high[0x20]; 7333 7334 u8 rp_cnp_handled_low[0x20]; 7335 7336 u8 reserved_at_140[0x100]; 7337 7338 u8 time_stamp_high[0x20]; 7339 7340 u8 time_stamp_low[0x20]; 7341 7342 u8 accumulators_period[0x20]; 7343 7344 u8 np_ecn_marked_roce_packets_high[0x20]; 7345 7346 u8 np_ecn_marked_roce_packets_low[0x20]; 7347 7348 u8 np_cnp_sent_high[0x20]; 7349 7350 u8 np_cnp_sent_low[0x20]; 7351 7352 u8 reserved_at_320[0x560]; 7353 }; 7354 7355 struct mlx5_ifc_query_cong_statistics_in_bits { 7356 u8 opcode[0x10]; 7357 u8 reserved_at_10[0x10]; 7358 7359 u8 reserved_at_20[0x10]; 7360 u8 op_mod[0x10]; 7361 7362 u8 clear[0x1]; 7363 u8 reserved_at_41[0x1f]; 7364 7365 u8 reserved_at_60[0x20]; 7366 }; 7367 7368 struct mlx5_ifc_query_cong_params_out_bits { 7369 u8 status[0x8]; 7370 u8 reserved_at_8[0x18]; 7371 7372 u8 syndrome[0x20]; 7373 7374 u8 reserved_at_40[0x40]; 7375 7376 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 7377 }; 7378 7379 struct mlx5_ifc_query_cong_params_in_bits { 7380 u8 opcode[0x10]; 7381 u8 reserved_at_10[0x10]; 7382 7383 u8 reserved_at_20[0x10]; 7384 u8 op_mod[0x10]; 7385 7386 u8 reserved_at_40[0x1c]; 7387 u8 cong_protocol[0x4]; 7388 7389 u8 reserved_at_60[0x20]; 7390 }; 7391 7392 struct mlx5_ifc_query_adapter_out_bits { 7393 u8 status[0x8]; 7394 u8 reserved_at_8[0x18]; 7395 7396 u8 syndrome[0x20]; 7397 7398 u8 reserved_at_40[0x40]; 7399 7400 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct; 7401 }; 7402 7403 struct mlx5_ifc_query_adapter_in_bits { 7404 u8 opcode[0x10]; 7405 u8 reserved_at_10[0x10]; 7406 7407 u8 reserved_at_20[0x10]; 7408 u8 op_mod[0x10]; 7409 7410 u8 reserved_at_40[0x40]; 7411 }; 7412 7413 struct mlx5_ifc_qp_2rst_out_bits { 7414 u8 status[0x8]; 7415 u8 reserved_at_8[0x18]; 7416 7417 u8 syndrome[0x20]; 7418 7419 u8 reserved_at_40[0x40]; 7420 }; 7421 7422 struct mlx5_ifc_qp_2rst_in_bits { 7423 u8 opcode[0x10]; 7424 u8 uid[0x10]; 7425 7426 u8 reserved_at_20[0x10]; 7427 u8 op_mod[0x10]; 7428 7429 u8 reserved_at_40[0x8]; 7430 u8 qpn[0x18]; 7431 7432 u8 reserved_at_60[0x20]; 7433 }; 7434 7435 struct mlx5_ifc_qp_2err_out_bits { 7436 u8 status[0x8]; 7437 u8 reserved_at_8[0x18]; 7438 7439 u8 syndrome[0x20]; 7440 7441 u8 reserved_at_40[0x40]; 7442 }; 7443 7444 struct mlx5_ifc_qp_2err_in_bits { 7445 u8 opcode[0x10]; 7446 u8 uid[0x10]; 7447 7448 u8 reserved_at_20[0x10]; 7449 u8 op_mod[0x10]; 7450 7451 u8 reserved_at_40[0x8]; 7452 u8 qpn[0x18]; 7453 7454 u8 reserved_at_60[0x20]; 7455 }; 7456 7457 struct mlx5_ifc_trans_page_fault_info_bits { 7458 u8 error[0x1]; 7459 u8 reserved_at_1[0x4]; 7460 u8 page_fault_type[0x3]; 7461 u8 wq_number[0x18]; 7462 7463 u8 reserved_at_20[0x8]; 7464 u8 fault_token[0x18]; 7465 }; 7466 7467 struct mlx5_ifc_mem_page_fault_info_bits { 7468 u8 error[0x1]; 7469 u8 reserved_at_1[0xf]; 7470 u8 fault_token_47_32[0x10]; 7471 7472 u8 fault_token_31_0[0x20]; 7473 }; 7474 7475 union mlx5_ifc_page_fault_resume_in_page_fault_info_auto_bits { 7476 struct mlx5_ifc_trans_page_fault_info_bits trans_page_fault_info; 7477 struct mlx5_ifc_mem_page_fault_info_bits mem_page_fault_info; 7478 u8 reserved_at_0[0x40]; 7479 }; 7480 7481 struct mlx5_ifc_page_fault_resume_out_bits { 7482 u8 status[0x8]; 7483 u8 reserved_at_8[0x18]; 7484 7485 u8 syndrome[0x20]; 7486 7487 u8 reserved_at_40[0x40]; 7488 }; 7489 7490 struct mlx5_ifc_page_fault_resume_in_bits { 7491 u8 opcode[0x10]; 7492 u8 reserved_at_10[0x10]; 7493 7494 u8 reserved_at_20[0x10]; 7495 u8 op_mod[0x10]; 7496 7497 union mlx5_ifc_page_fault_resume_in_page_fault_info_auto_bits 7498 page_fault_info; 7499 }; 7500 7501 struct mlx5_ifc_nop_out_bits { 7502 u8 status[0x8]; 7503 u8 reserved_at_8[0x18]; 7504 7505 u8 syndrome[0x20]; 7506 7507 u8 reserved_at_40[0x40]; 7508 }; 7509 7510 struct mlx5_ifc_nop_in_bits { 7511 u8 opcode[0x10]; 7512 u8 reserved_at_10[0x10]; 7513 7514 u8 reserved_at_20[0x10]; 7515 u8 op_mod[0x10]; 7516 7517 u8 reserved_at_40[0x40]; 7518 }; 7519 7520 struct mlx5_ifc_modify_vport_state_out_bits { 7521 u8 status[0x8]; 7522 u8 reserved_at_8[0x18]; 7523 7524 u8 syndrome[0x20]; 7525 7526 u8 reserved_at_40[0x40]; 7527 }; 7528 7529 struct mlx5_ifc_modify_vport_state_in_bits { 7530 u8 opcode[0x10]; 7531 u8 reserved_at_10[0x10]; 7532 7533 u8 reserved_at_20[0x10]; 7534 u8 op_mod[0x10]; 7535 7536 u8 other_vport[0x1]; 7537 u8 reserved_at_41[0xf]; 7538 u8 vport_number[0x10]; 7539 7540 u8 reserved_at_60[0x18]; 7541 u8 admin_state[0x4]; 7542 u8 reserved_at_7c[0x4]; 7543 }; 7544 7545 struct mlx5_ifc_modify_tis_out_bits { 7546 u8 status[0x8]; 7547 u8 reserved_at_8[0x18]; 7548 7549 u8 syndrome[0x20]; 7550 7551 u8 reserved_at_40[0x40]; 7552 }; 7553 7554 struct mlx5_ifc_modify_tis_bitmask_bits { 7555 u8 reserved_at_0[0x20]; 7556 7557 u8 reserved_at_20[0x1d]; 7558 u8 lag_tx_port_affinity[0x1]; 7559 u8 strict_lag_tx_port_affinity[0x1]; 7560 u8 prio[0x1]; 7561 }; 7562 7563 struct mlx5_ifc_modify_tis_in_bits { 7564 u8 opcode[0x10]; 7565 u8 uid[0x10]; 7566 7567 u8 reserved_at_20[0x10]; 7568 u8 op_mod[0x10]; 7569 7570 u8 reserved_at_40[0x8]; 7571 u8 tisn[0x18]; 7572 7573 u8 reserved_at_60[0x20]; 7574 7575 struct mlx5_ifc_modify_tis_bitmask_bits bitmask; 7576 7577 u8 reserved_at_c0[0x40]; 7578 7579 struct mlx5_ifc_tisc_bits ctx; 7580 }; 7581 7582 struct mlx5_ifc_modify_tir_bitmask_bits { 7583 u8 reserved_at_0[0x20]; 7584 7585 u8 reserved_at_20[0x1b]; 7586 u8 self_lb_en[0x1]; 7587 u8 reserved_at_3c[0x1]; 7588 u8 hash[0x1]; 7589 u8 reserved_at_3e[0x1]; 7590 u8 packet_merge[0x1]; 7591 }; 7592 7593 struct mlx5_ifc_modify_tir_out_bits { 7594 u8 status[0x8]; 7595 u8 reserved_at_8[0x18]; 7596 7597 u8 syndrome[0x20]; 7598 7599 u8 reserved_at_40[0x40]; 7600 }; 7601 7602 struct mlx5_ifc_modify_tir_in_bits { 7603 u8 opcode[0x10]; 7604 u8 uid[0x10]; 7605 7606 u8 reserved_at_20[0x10]; 7607 u8 op_mod[0x10]; 7608 7609 u8 reserved_at_40[0x8]; 7610 u8 tirn[0x18]; 7611 7612 u8 reserved_at_60[0x20]; 7613 7614 struct mlx5_ifc_modify_tir_bitmask_bits bitmask; 7615 7616 u8 reserved_at_c0[0x40]; 7617 7618 struct mlx5_ifc_tirc_bits ctx; 7619 }; 7620 7621 struct mlx5_ifc_modify_sq_out_bits { 7622 u8 status[0x8]; 7623 u8 reserved_at_8[0x18]; 7624 7625 u8 syndrome[0x20]; 7626 7627 u8 reserved_at_40[0x40]; 7628 }; 7629 7630 struct mlx5_ifc_modify_sq_in_bits { 7631 u8 opcode[0x10]; 7632 u8 uid[0x10]; 7633 7634 u8 reserved_at_20[0x10]; 7635 u8 op_mod[0x10]; 7636 7637 u8 sq_state[0x4]; 7638 u8 reserved_at_44[0x4]; 7639 u8 sqn[0x18]; 7640 7641 u8 reserved_at_60[0x20]; 7642 7643 u8 modify_bitmask[0x40]; 7644 7645 u8 reserved_at_c0[0x40]; 7646 7647 struct mlx5_ifc_sqc_bits ctx; 7648 }; 7649 7650 struct mlx5_ifc_modify_scheduling_element_out_bits { 7651 u8 status[0x8]; 7652 u8 reserved_at_8[0x18]; 7653 7654 u8 syndrome[0x20]; 7655 7656 u8 reserved_at_40[0x1c0]; 7657 }; 7658 7659 enum { 7660 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1, 7661 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2, 7662 }; 7663 7664 struct mlx5_ifc_modify_scheduling_element_in_bits { 7665 u8 opcode[0x10]; 7666 u8 reserved_at_10[0x10]; 7667 7668 u8 reserved_at_20[0x10]; 7669 u8 op_mod[0x10]; 7670 7671 u8 scheduling_hierarchy[0x8]; 7672 u8 reserved_at_48[0x18]; 7673 7674 u8 scheduling_element_id[0x20]; 7675 7676 u8 reserved_at_80[0x20]; 7677 7678 u8 modify_bitmask[0x20]; 7679 7680 u8 reserved_at_c0[0x40]; 7681 7682 struct mlx5_ifc_scheduling_context_bits scheduling_context; 7683 7684 u8 reserved_at_300[0x100]; 7685 }; 7686 7687 struct mlx5_ifc_modify_rqt_out_bits { 7688 u8 status[0x8]; 7689 u8 reserved_at_8[0x18]; 7690 7691 u8 syndrome[0x20]; 7692 7693 u8 reserved_at_40[0x40]; 7694 }; 7695 7696 struct mlx5_ifc_rqt_bitmask_bits { 7697 u8 reserved_at_0[0x20]; 7698 7699 u8 reserved_at_20[0x1f]; 7700 u8 rqn_list[0x1]; 7701 }; 7702 7703 struct mlx5_ifc_modify_rqt_in_bits { 7704 u8 opcode[0x10]; 7705 u8 uid[0x10]; 7706 7707 u8 reserved_at_20[0x10]; 7708 u8 op_mod[0x10]; 7709 7710 u8 reserved_at_40[0x8]; 7711 u8 rqtn[0x18]; 7712 7713 u8 reserved_at_60[0x20]; 7714 7715 struct mlx5_ifc_rqt_bitmask_bits bitmask; 7716 7717 u8 reserved_at_c0[0x40]; 7718 7719 struct mlx5_ifc_rqtc_bits ctx; 7720 }; 7721 7722 struct mlx5_ifc_modify_rq_out_bits { 7723 u8 status[0x8]; 7724 u8 reserved_at_8[0x18]; 7725 7726 u8 syndrome[0x20]; 7727 7728 u8 reserved_at_40[0x40]; 7729 }; 7730 7731 enum { 7732 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1, 7733 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2, 7734 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3, 7735 }; 7736 7737 struct mlx5_ifc_modify_rq_in_bits { 7738 u8 opcode[0x10]; 7739 u8 uid[0x10]; 7740 7741 u8 reserved_at_20[0x10]; 7742 u8 op_mod[0x10]; 7743 7744 u8 rq_state[0x4]; 7745 u8 reserved_at_44[0x4]; 7746 u8 rqn[0x18]; 7747 7748 u8 reserved_at_60[0x20]; 7749 7750 u8 modify_bitmask[0x40]; 7751 7752 u8 reserved_at_c0[0x40]; 7753 7754 struct mlx5_ifc_rqc_bits ctx; 7755 }; 7756 7757 struct mlx5_ifc_modify_rmp_out_bits { 7758 u8 status[0x8]; 7759 u8 reserved_at_8[0x18]; 7760 7761 u8 syndrome[0x20]; 7762 7763 u8 reserved_at_40[0x40]; 7764 }; 7765 7766 struct mlx5_ifc_rmp_bitmask_bits { 7767 u8 reserved_at_0[0x20]; 7768 7769 u8 reserved_at_20[0x1f]; 7770 u8 lwm[0x1]; 7771 }; 7772 7773 struct mlx5_ifc_modify_rmp_in_bits { 7774 u8 opcode[0x10]; 7775 u8 uid[0x10]; 7776 7777 u8 reserved_at_20[0x10]; 7778 u8 op_mod[0x10]; 7779 7780 u8 rmp_state[0x4]; 7781 u8 reserved_at_44[0x4]; 7782 u8 rmpn[0x18]; 7783 7784 u8 reserved_at_60[0x20]; 7785 7786 struct mlx5_ifc_rmp_bitmask_bits bitmask; 7787 7788 u8 reserved_at_c0[0x40]; 7789 7790 struct mlx5_ifc_rmpc_bits ctx; 7791 }; 7792 7793 struct mlx5_ifc_modify_nic_vport_context_out_bits { 7794 u8 status[0x8]; 7795 u8 reserved_at_8[0x18]; 7796 7797 u8 syndrome[0x20]; 7798 7799 u8 reserved_at_40[0x40]; 7800 }; 7801 7802 struct mlx5_ifc_modify_nic_vport_field_select_bits { 7803 u8 reserved_at_0[0x12]; 7804 u8 affiliation[0x1]; 7805 u8 reserved_at_13[0x1]; 7806 u8 disable_uc_local_lb[0x1]; 7807 u8 disable_mc_local_lb[0x1]; 7808 u8 node_guid[0x1]; 7809 u8 port_guid[0x1]; 7810 u8 min_inline[0x1]; 7811 u8 mtu[0x1]; 7812 u8 change_event[0x1]; 7813 u8 promisc[0x1]; 7814 u8 permanent_address[0x1]; 7815 u8 addresses_list[0x1]; 7816 u8 roce_en[0x1]; 7817 u8 reserved_at_1f[0x1]; 7818 }; 7819 7820 struct mlx5_ifc_modify_nic_vport_context_in_bits { 7821 u8 opcode[0x10]; 7822 u8 reserved_at_10[0x10]; 7823 7824 u8 reserved_at_20[0x10]; 7825 u8 op_mod[0x10]; 7826 7827 u8 other_vport[0x1]; 7828 u8 reserved_at_41[0xf]; 7829 u8 vport_number[0x10]; 7830 7831 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select; 7832 7833 u8 reserved_at_80[0x780]; 7834 7835 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 7836 }; 7837 7838 struct mlx5_ifc_modify_hca_vport_context_out_bits { 7839 u8 status[0x8]; 7840 u8 reserved_at_8[0x18]; 7841 7842 u8 syndrome[0x20]; 7843 7844 u8 reserved_at_40[0x40]; 7845 }; 7846 7847 struct mlx5_ifc_modify_hca_vport_context_in_bits { 7848 u8 opcode[0x10]; 7849 u8 reserved_at_10[0x10]; 7850 7851 u8 reserved_at_20[0x10]; 7852 u8 op_mod[0x10]; 7853 7854 u8 other_vport[0x1]; 7855 u8 reserved_at_41[0xb]; 7856 u8 port_num[0x4]; 7857 u8 vport_number[0x10]; 7858 7859 u8 reserved_at_60[0x20]; 7860 7861 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 7862 }; 7863 7864 struct mlx5_ifc_modify_cq_out_bits { 7865 u8 status[0x8]; 7866 u8 reserved_at_8[0x18]; 7867 7868 u8 syndrome[0x20]; 7869 7870 u8 reserved_at_40[0x40]; 7871 }; 7872 7873 enum { 7874 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0, 7875 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1, 7876 }; 7877 7878 struct mlx5_ifc_modify_cq_in_bits { 7879 u8 opcode[0x10]; 7880 u8 uid[0x10]; 7881 7882 u8 reserved_at_20[0x10]; 7883 u8 op_mod[0x10]; 7884 7885 u8 reserved_at_40[0x8]; 7886 u8 cqn[0x18]; 7887 7888 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select; 7889 7890 struct mlx5_ifc_cqc_bits cq_context; 7891 7892 u8 reserved_at_280[0x60]; 7893 7894 u8 cq_umem_valid[0x1]; 7895 u8 reserved_at_2e1[0x1f]; 7896 7897 u8 reserved_at_300[0x580]; 7898 7899 u8 pas[][0x40]; 7900 }; 7901 7902 struct mlx5_ifc_modify_cong_status_out_bits { 7903 u8 status[0x8]; 7904 u8 reserved_at_8[0x18]; 7905 7906 u8 syndrome[0x20]; 7907 7908 u8 reserved_at_40[0x40]; 7909 }; 7910 7911 struct mlx5_ifc_modify_cong_status_in_bits { 7912 u8 opcode[0x10]; 7913 u8 reserved_at_10[0x10]; 7914 7915 u8 reserved_at_20[0x10]; 7916 u8 op_mod[0x10]; 7917 7918 u8 reserved_at_40[0x18]; 7919 u8 priority[0x4]; 7920 u8 cong_protocol[0x4]; 7921 7922 u8 enable[0x1]; 7923 u8 tag_enable[0x1]; 7924 u8 reserved_at_62[0x1e]; 7925 }; 7926 7927 struct mlx5_ifc_modify_cong_params_out_bits { 7928 u8 status[0x8]; 7929 u8 reserved_at_8[0x18]; 7930 7931 u8 syndrome[0x20]; 7932 7933 u8 reserved_at_40[0x40]; 7934 }; 7935 7936 struct mlx5_ifc_modify_cong_params_in_bits { 7937 u8 opcode[0x10]; 7938 u8 reserved_at_10[0x10]; 7939 7940 u8 reserved_at_20[0x10]; 7941 u8 op_mod[0x10]; 7942 7943 u8 reserved_at_40[0x1c]; 7944 u8 cong_protocol[0x4]; 7945 7946 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select; 7947 7948 u8 reserved_at_80[0x80]; 7949 7950 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 7951 }; 7952 7953 struct mlx5_ifc_manage_pages_out_bits { 7954 u8 status[0x8]; 7955 u8 reserved_at_8[0x18]; 7956 7957 u8 syndrome[0x20]; 7958 7959 u8 output_num_entries[0x20]; 7960 7961 u8 reserved_at_60[0x20]; 7962 7963 u8 pas[][0x40]; 7964 }; 7965 7966 enum { 7967 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL = 0x0, 7968 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS = 0x1, 7969 MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES = 0x2, 7970 }; 7971 7972 struct mlx5_ifc_manage_pages_in_bits { 7973 u8 opcode[0x10]; 7974 u8 reserved_at_10[0x10]; 7975 7976 u8 reserved_at_20[0x10]; 7977 u8 op_mod[0x10]; 7978 7979 u8 embedded_cpu_function[0x1]; 7980 u8 reserved_at_41[0xf]; 7981 u8 function_id[0x10]; 7982 7983 u8 input_num_entries[0x20]; 7984 7985 u8 pas[][0x40]; 7986 }; 7987 7988 struct mlx5_ifc_mad_ifc_out_bits { 7989 u8 status[0x8]; 7990 u8 reserved_at_8[0x18]; 7991 7992 u8 syndrome[0x20]; 7993 7994 u8 reserved_at_40[0x40]; 7995 7996 u8 response_mad_packet[256][0x8]; 7997 }; 7998 7999 struct mlx5_ifc_mad_ifc_in_bits { 8000 u8 opcode[0x10]; 8001 u8 reserved_at_10[0x10]; 8002 8003 u8 reserved_at_20[0x10]; 8004 u8 op_mod[0x10]; 8005 8006 u8 remote_lid[0x10]; 8007 u8 plane_index[0x8]; 8008 u8 port[0x8]; 8009 8010 u8 reserved_at_60[0x20]; 8011 8012 u8 mad[256][0x8]; 8013 }; 8014 8015 struct mlx5_ifc_init_hca_out_bits { 8016 u8 status[0x8]; 8017 u8 reserved_at_8[0x18]; 8018 8019 u8 syndrome[0x20]; 8020 8021 u8 reserved_at_40[0x40]; 8022 }; 8023 8024 struct mlx5_ifc_init_hca_in_bits { 8025 u8 opcode[0x10]; 8026 u8 reserved_at_10[0x10]; 8027 8028 u8 reserved_at_20[0x10]; 8029 u8 op_mod[0x10]; 8030 8031 u8 reserved_at_40[0x20]; 8032 8033 u8 reserved_at_60[0x2]; 8034 u8 sw_vhca_id[0xe]; 8035 u8 reserved_at_70[0x10]; 8036 8037 u8 sw_owner_id[4][0x20]; 8038 }; 8039 8040 struct mlx5_ifc_init2rtr_qp_out_bits { 8041 u8 status[0x8]; 8042 u8 reserved_at_8[0x18]; 8043 8044 u8 syndrome[0x20]; 8045 8046 u8 reserved_at_40[0x20]; 8047 u8 ece[0x20]; 8048 }; 8049 8050 struct mlx5_ifc_init2rtr_qp_in_bits { 8051 u8 opcode[0x10]; 8052 u8 uid[0x10]; 8053 8054 u8 reserved_at_20[0x10]; 8055 u8 op_mod[0x10]; 8056 8057 u8 reserved_at_40[0x8]; 8058 u8 qpn[0x18]; 8059 8060 u8 reserved_at_60[0x20]; 8061 8062 u8 opt_param_mask[0x20]; 8063 8064 u8 ece[0x20]; 8065 8066 struct mlx5_ifc_qpc_bits qpc; 8067 8068 u8 reserved_at_800[0x80]; 8069 }; 8070 8071 struct mlx5_ifc_init2init_qp_out_bits { 8072 u8 status[0x8]; 8073 u8 reserved_at_8[0x18]; 8074 8075 u8 syndrome[0x20]; 8076 8077 u8 reserved_at_40[0x20]; 8078 u8 ece[0x20]; 8079 }; 8080 8081 struct mlx5_ifc_init2init_qp_in_bits { 8082 u8 opcode[0x10]; 8083 u8 uid[0x10]; 8084 8085 u8 reserved_at_20[0x10]; 8086 u8 op_mod[0x10]; 8087 8088 u8 reserved_at_40[0x8]; 8089 u8 qpn[0x18]; 8090 8091 u8 reserved_at_60[0x20]; 8092 8093 u8 opt_param_mask[0x20]; 8094 8095 u8 ece[0x20]; 8096 8097 struct mlx5_ifc_qpc_bits qpc; 8098 8099 u8 reserved_at_800[0x80]; 8100 }; 8101 8102 struct mlx5_ifc_get_dropped_packet_log_out_bits { 8103 u8 status[0x8]; 8104 u8 reserved_at_8[0x18]; 8105 8106 u8 syndrome[0x20]; 8107 8108 u8 reserved_at_40[0x40]; 8109 8110 u8 packet_headers_log[128][0x8]; 8111 8112 u8 packet_syndrome[64][0x8]; 8113 }; 8114 8115 struct mlx5_ifc_get_dropped_packet_log_in_bits { 8116 u8 opcode[0x10]; 8117 u8 reserved_at_10[0x10]; 8118 8119 u8 reserved_at_20[0x10]; 8120 u8 op_mod[0x10]; 8121 8122 u8 reserved_at_40[0x40]; 8123 }; 8124 8125 struct mlx5_ifc_gen_eqe_in_bits { 8126 u8 opcode[0x10]; 8127 u8 reserved_at_10[0x10]; 8128 8129 u8 reserved_at_20[0x10]; 8130 u8 op_mod[0x10]; 8131 8132 u8 reserved_at_40[0x18]; 8133 u8 eq_number[0x8]; 8134 8135 u8 reserved_at_60[0x20]; 8136 8137 u8 eqe[64][0x8]; 8138 }; 8139 8140 struct mlx5_ifc_gen_eq_out_bits { 8141 u8 status[0x8]; 8142 u8 reserved_at_8[0x18]; 8143 8144 u8 syndrome[0x20]; 8145 8146 u8 reserved_at_40[0x40]; 8147 }; 8148 8149 struct mlx5_ifc_enable_hca_out_bits { 8150 u8 status[0x8]; 8151 u8 reserved_at_8[0x18]; 8152 8153 u8 syndrome[0x20]; 8154 8155 u8 reserved_at_40[0x20]; 8156 }; 8157 8158 struct mlx5_ifc_enable_hca_in_bits { 8159 u8 opcode[0x10]; 8160 u8 reserved_at_10[0x10]; 8161 8162 u8 reserved_at_20[0x10]; 8163 u8 op_mod[0x10]; 8164 8165 u8 embedded_cpu_function[0x1]; 8166 u8 reserved_at_41[0xf]; 8167 u8 function_id[0x10]; 8168 8169 u8 reserved_at_60[0x20]; 8170 }; 8171 8172 struct mlx5_ifc_drain_dct_out_bits { 8173 u8 status[0x8]; 8174 u8 reserved_at_8[0x18]; 8175 8176 u8 syndrome[0x20]; 8177 8178 u8 reserved_at_40[0x40]; 8179 }; 8180 8181 struct mlx5_ifc_drain_dct_in_bits { 8182 u8 opcode[0x10]; 8183 u8 uid[0x10]; 8184 8185 u8 reserved_at_20[0x10]; 8186 u8 op_mod[0x10]; 8187 8188 u8 reserved_at_40[0x8]; 8189 u8 dctn[0x18]; 8190 8191 u8 reserved_at_60[0x20]; 8192 }; 8193 8194 struct mlx5_ifc_disable_hca_out_bits { 8195 u8 status[0x8]; 8196 u8 reserved_at_8[0x18]; 8197 8198 u8 syndrome[0x20]; 8199 8200 u8 reserved_at_40[0x20]; 8201 }; 8202 8203 struct mlx5_ifc_disable_hca_in_bits { 8204 u8 opcode[0x10]; 8205 u8 reserved_at_10[0x10]; 8206 8207 u8 reserved_at_20[0x10]; 8208 u8 op_mod[0x10]; 8209 8210 u8 embedded_cpu_function[0x1]; 8211 u8 reserved_at_41[0xf]; 8212 u8 function_id[0x10]; 8213 8214 u8 reserved_at_60[0x20]; 8215 }; 8216 8217 struct mlx5_ifc_detach_from_mcg_out_bits { 8218 u8 status[0x8]; 8219 u8 reserved_at_8[0x18]; 8220 8221 u8 syndrome[0x20]; 8222 8223 u8 reserved_at_40[0x40]; 8224 }; 8225 8226 struct mlx5_ifc_detach_from_mcg_in_bits { 8227 u8 opcode[0x10]; 8228 u8 uid[0x10]; 8229 8230 u8 reserved_at_20[0x10]; 8231 u8 op_mod[0x10]; 8232 8233 u8 reserved_at_40[0x8]; 8234 u8 qpn[0x18]; 8235 8236 u8 reserved_at_60[0x20]; 8237 8238 u8 multicast_gid[16][0x8]; 8239 }; 8240 8241 struct mlx5_ifc_destroy_xrq_out_bits { 8242 u8 status[0x8]; 8243 u8 reserved_at_8[0x18]; 8244 8245 u8 syndrome[0x20]; 8246 8247 u8 reserved_at_40[0x40]; 8248 }; 8249 8250 struct mlx5_ifc_destroy_xrq_in_bits { 8251 u8 opcode[0x10]; 8252 u8 uid[0x10]; 8253 8254 u8 reserved_at_20[0x10]; 8255 u8 op_mod[0x10]; 8256 8257 u8 reserved_at_40[0x8]; 8258 u8 xrqn[0x18]; 8259 8260 u8 reserved_at_60[0x20]; 8261 }; 8262 8263 struct mlx5_ifc_destroy_xrc_srq_out_bits { 8264 u8 status[0x8]; 8265 u8 reserved_at_8[0x18]; 8266 8267 u8 syndrome[0x20]; 8268 8269 u8 reserved_at_40[0x40]; 8270 }; 8271 8272 struct mlx5_ifc_destroy_xrc_srq_in_bits { 8273 u8 opcode[0x10]; 8274 u8 uid[0x10]; 8275 8276 u8 reserved_at_20[0x10]; 8277 u8 op_mod[0x10]; 8278 8279 u8 reserved_at_40[0x8]; 8280 u8 xrc_srqn[0x18]; 8281 8282 u8 reserved_at_60[0x20]; 8283 }; 8284 8285 struct mlx5_ifc_destroy_tis_out_bits { 8286 u8 status[0x8]; 8287 u8 reserved_at_8[0x18]; 8288 8289 u8 syndrome[0x20]; 8290 8291 u8 reserved_at_40[0x40]; 8292 }; 8293 8294 struct mlx5_ifc_destroy_tis_in_bits { 8295 u8 opcode[0x10]; 8296 u8 uid[0x10]; 8297 8298 u8 reserved_at_20[0x10]; 8299 u8 op_mod[0x10]; 8300 8301 u8 reserved_at_40[0x8]; 8302 u8 tisn[0x18]; 8303 8304 u8 reserved_at_60[0x20]; 8305 }; 8306 8307 struct mlx5_ifc_destroy_tir_out_bits { 8308 u8 status[0x8]; 8309 u8 reserved_at_8[0x18]; 8310 8311 u8 syndrome[0x20]; 8312 8313 u8 reserved_at_40[0x40]; 8314 }; 8315 8316 struct mlx5_ifc_destroy_tir_in_bits { 8317 u8 opcode[0x10]; 8318 u8 uid[0x10]; 8319 8320 u8 reserved_at_20[0x10]; 8321 u8 op_mod[0x10]; 8322 8323 u8 reserved_at_40[0x8]; 8324 u8 tirn[0x18]; 8325 8326 u8 reserved_at_60[0x20]; 8327 }; 8328 8329 struct mlx5_ifc_destroy_srq_out_bits { 8330 u8 status[0x8]; 8331 u8 reserved_at_8[0x18]; 8332 8333 u8 syndrome[0x20]; 8334 8335 u8 reserved_at_40[0x40]; 8336 }; 8337 8338 struct mlx5_ifc_destroy_srq_in_bits { 8339 u8 opcode[0x10]; 8340 u8 uid[0x10]; 8341 8342 u8 reserved_at_20[0x10]; 8343 u8 op_mod[0x10]; 8344 8345 u8 reserved_at_40[0x8]; 8346 u8 srqn[0x18]; 8347 8348 u8 reserved_at_60[0x20]; 8349 }; 8350 8351 struct mlx5_ifc_destroy_sq_out_bits { 8352 u8 status[0x8]; 8353 u8 reserved_at_8[0x18]; 8354 8355 u8 syndrome[0x20]; 8356 8357 u8 reserved_at_40[0x40]; 8358 }; 8359 8360 struct mlx5_ifc_destroy_sq_in_bits { 8361 u8 opcode[0x10]; 8362 u8 uid[0x10]; 8363 8364 u8 reserved_at_20[0x10]; 8365 u8 op_mod[0x10]; 8366 8367 u8 reserved_at_40[0x8]; 8368 u8 sqn[0x18]; 8369 8370 u8 reserved_at_60[0x20]; 8371 }; 8372 8373 struct mlx5_ifc_destroy_scheduling_element_out_bits { 8374 u8 status[0x8]; 8375 u8 reserved_at_8[0x18]; 8376 8377 u8 syndrome[0x20]; 8378 8379 u8 reserved_at_40[0x1c0]; 8380 }; 8381 8382 struct mlx5_ifc_destroy_scheduling_element_in_bits { 8383 u8 opcode[0x10]; 8384 u8 reserved_at_10[0x10]; 8385 8386 u8 reserved_at_20[0x10]; 8387 u8 op_mod[0x10]; 8388 8389 u8 scheduling_hierarchy[0x8]; 8390 u8 reserved_at_48[0x18]; 8391 8392 u8 scheduling_element_id[0x20]; 8393 8394 u8 reserved_at_80[0x180]; 8395 }; 8396 8397 struct mlx5_ifc_destroy_rqt_out_bits { 8398 u8 status[0x8]; 8399 u8 reserved_at_8[0x18]; 8400 8401 u8 syndrome[0x20]; 8402 8403 u8 reserved_at_40[0x40]; 8404 }; 8405 8406 struct mlx5_ifc_destroy_rqt_in_bits { 8407 u8 opcode[0x10]; 8408 u8 uid[0x10]; 8409 8410 u8 reserved_at_20[0x10]; 8411 u8 op_mod[0x10]; 8412 8413 u8 reserved_at_40[0x8]; 8414 u8 rqtn[0x18]; 8415 8416 u8 reserved_at_60[0x20]; 8417 }; 8418 8419 struct mlx5_ifc_destroy_rq_out_bits { 8420 u8 status[0x8]; 8421 u8 reserved_at_8[0x18]; 8422 8423 u8 syndrome[0x20]; 8424 8425 u8 reserved_at_40[0x40]; 8426 }; 8427 8428 struct mlx5_ifc_destroy_rq_in_bits { 8429 u8 opcode[0x10]; 8430 u8 uid[0x10]; 8431 8432 u8 reserved_at_20[0x10]; 8433 u8 op_mod[0x10]; 8434 8435 u8 reserved_at_40[0x8]; 8436 u8 rqn[0x18]; 8437 8438 u8 reserved_at_60[0x20]; 8439 }; 8440 8441 struct mlx5_ifc_set_delay_drop_params_in_bits { 8442 u8 opcode[0x10]; 8443 u8 reserved_at_10[0x10]; 8444 8445 u8 reserved_at_20[0x10]; 8446 u8 op_mod[0x10]; 8447 8448 u8 reserved_at_40[0x20]; 8449 8450 u8 reserved_at_60[0x10]; 8451 u8 delay_drop_timeout[0x10]; 8452 }; 8453 8454 struct mlx5_ifc_set_delay_drop_params_out_bits { 8455 u8 status[0x8]; 8456 u8 reserved_at_8[0x18]; 8457 8458 u8 syndrome[0x20]; 8459 8460 u8 reserved_at_40[0x40]; 8461 }; 8462 8463 struct mlx5_ifc_destroy_rmp_out_bits { 8464 u8 status[0x8]; 8465 u8 reserved_at_8[0x18]; 8466 8467 u8 syndrome[0x20]; 8468 8469 u8 reserved_at_40[0x40]; 8470 }; 8471 8472 struct mlx5_ifc_destroy_rmp_in_bits { 8473 u8 opcode[0x10]; 8474 u8 uid[0x10]; 8475 8476 u8 reserved_at_20[0x10]; 8477 u8 op_mod[0x10]; 8478 8479 u8 reserved_at_40[0x8]; 8480 u8 rmpn[0x18]; 8481 8482 u8 reserved_at_60[0x20]; 8483 }; 8484 8485 struct mlx5_ifc_destroy_qp_out_bits { 8486 u8 status[0x8]; 8487 u8 reserved_at_8[0x18]; 8488 8489 u8 syndrome[0x20]; 8490 8491 u8 reserved_at_40[0x40]; 8492 }; 8493 8494 struct mlx5_ifc_destroy_qp_in_bits { 8495 u8 opcode[0x10]; 8496 u8 uid[0x10]; 8497 8498 u8 reserved_at_20[0x10]; 8499 u8 op_mod[0x10]; 8500 8501 u8 reserved_at_40[0x8]; 8502 u8 qpn[0x18]; 8503 8504 u8 reserved_at_60[0x20]; 8505 }; 8506 8507 struct mlx5_ifc_destroy_psv_out_bits { 8508 u8 status[0x8]; 8509 u8 reserved_at_8[0x18]; 8510 8511 u8 syndrome[0x20]; 8512 8513 u8 reserved_at_40[0x40]; 8514 }; 8515 8516 struct mlx5_ifc_destroy_psv_in_bits { 8517 u8 opcode[0x10]; 8518 u8 reserved_at_10[0x10]; 8519 8520 u8 reserved_at_20[0x10]; 8521 u8 op_mod[0x10]; 8522 8523 u8 reserved_at_40[0x8]; 8524 u8 psvn[0x18]; 8525 8526 u8 reserved_at_60[0x20]; 8527 }; 8528 8529 struct mlx5_ifc_destroy_mkey_out_bits { 8530 u8 status[0x8]; 8531 u8 reserved_at_8[0x18]; 8532 8533 u8 syndrome[0x20]; 8534 8535 u8 reserved_at_40[0x40]; 8536 }; 8537 8538 struct mlx5_ifc_destroy_mkey_in_bits { 8539 u8 opcode[0x10]; 8540 u8 uid[0x10]; 8541 8542 u8 reserved_at_20[0x10]; 8543 u8 op_mod[0x10]; 8544 8545 u8 reserved_at_40[0x8]; 8546 u8 mkey_index[0x18]; 8547 8548 u8 reserved_at_60[0x20]; 8549 }; 8550 8551 struct mlx5_ifc_destroy_flow_table_out_bits { 8552 u8 status[0x8]; 8553 u8 reserved_at_8[0x18]; 8554 8555 u8 syndrome[0x20]; 8556 8557 u8 reserved_at_40[0x40]; 8558 }; 8559 8560 struct mlx5_ifc_destroy_flow_table_in_bits { 8561 u8 opcode[0x10]; 8562 u8 reserved_at_10[0x10]; 8563 8564 u8 reserved_at_20[0x10]; 8565 u8 op_mod[0x10]; 8566 8567 u8 other_vport[0x1]; 8568 u8 reserved_at_41[0xf]; 8569 u8 vport_number[0x10]; 8570 8571 u8 reserved_at_60[0x20]; 8572 8573 u8 table_type[0x8]; 8574 u8 reserved_at_88[0x18]; 8575 8576 u8 reserved_at_a0[0x8]; 8577 u8 table_id[0x18]; 8578 8579 u8 reserved_at_c0[0x140]; 8580 }; 8581 8582 struct mlx5_ifc_destroy_flow_group_out_bits { 8583 u8 status[0x8]; 8584 u8 reserved_at_8[0x18]; 8585 8586 u8 syndrome[0x20]; 8587 8588 u8 reserved_at_40[0x40]; 8589 }; 8590 8591 struct mlx5_ifc_destroy_flow_group_in_bits { 8592 u8 opcode[0x10]; 8593 u8 reserved_at_10[0x10]; 8594 8595 u8 reserved_at_20[0x10]; 8596 u8 op_mod[0x10]; 8597 8598 u8 other_vport[0x1]; 8599 u8 reserved_at_41[0xf]; 8600 u8 vport_number[0x10]; 8601 8602 u8 reserved_at_60[0x20]; 8603 8604 u8 table_type[0x8]; 8605 u8 reserved_at_88[0x18]; 8606 8607 u8 reserved_at_a0[0x8]; 8608 u8 table_id[0x18]; 8609 8610 u8 group_id[0x20]; 8611 8612 u8 reserved_at_e0[0x120]; 8613 }; 8614 8615 struct mlx5_ifc_destroy_eq_out_bits { 8616 u8 status[0x8]; 8617 u8 reserved_at_8[0x18]; 8618 8619 u8 syndrome[0x20]; 8620 8621 u8 reserved_at_40[0x40]; 8622 }; 8623 8624 struct mlx5_ifc_destroy_eq_in_bits { 8625 u8 opcode[0x10]; 8626 u8 reserved_at_10[0x10]; 8627 8628 u8 reserved_at_20[0x10]; 8629 u8 op_mod[0x10]; 8630 8631 u8 reserved_at_40[0x18]; 8632 u8 eq_number[0x8]; 8633 8634 u8 reserved_at_60[0x20]; 8635 }; 8636 8637 struct mlx5_ifc_destroy_dct_out_bits { 8638 u8 status[0x8]; 8639 u8 reserved_at_8[0x18]; 8640 8641 u8 syndrome[0x20]; 8642 8643 u8 reserved_at_40[0x40]; 8644 }; 8645 8646 struct mlx5_ifc_destroy_dct_in_bits { 8647 u8 opcode[0x10]; 8648 u8 uid[0x10]; 8649 8650 u8 reserved_at_20[0x10]; 8651 u8 op_mod[0x10]; 8652 8653 u8 reserved_at_40[0x8]; 8654 u8 dctn[0x18]; 8655 8656 u8 reserved_at_60[0x20]; 8657 }; 8658 8659 struct mlx5_ifc_destroy_cq_out_bits { 8660 u8 status[0x8]; 8661 u8 reserved_at_8[0x18]; 8662 8663 u8 syndrome[0x20]; 8664 8665 u8 reserved_at_40[0x40]; 8666 }; 8667 8668 struct mlx5_ifc_destroy_cq_in_bits { 8669 u8 opcode[0x10]; 8670 u8 uid[0x10]; 8671 8672 u8 reserved_at_20[0x10]; 8673 u8 op_mod[0x10]; 8674 8675 u8 reserved_at_40[0x8]; 8676 u8 cqn[0x18]; 8677 8678 u8 reserved_at_60[0x20]; 8679 }; 8680 8681 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits { 8682 u8 status[0x8]; 8683 u8 reserved_at_8[0x18]; 8684 8685 u8 syndrome[0x20]; 8686 8687 u8 reserved_at_40[0x40]; 8688 }; 8689 8690 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits { 8691 u8 opcode[0x10]; 8692 u8 reserved_at_10[0x10]; 8693 8694 u8 reserved_at_20[0x10]; 8695 u8 op_mod[0x10]; 8696 8697 u8 reserved_at_40[0x20]; 8698 8699 u8 reserved_at_60[0x10]; 8700 u8 vxlan_udp_port[0x10]; 8701 }; 8702 8703 struct mlx5_ifc_delete_l2_table_entry_out_bits { 8704 u8 status[0x8]; 8705 u8 reserved_at_8[0x18]; 8706 8707 u8 syndrome[0x20]; 8708 8709 u8 reserved_at_40[0x40]; 8710 }; 8711 8712 struct mlx5_ifc_delete_l2_table_entry_in_bits { 8713 u8 opcode[0x10]; 8714 u8 reserved_at_10[0x10]; 8715 8716 u8 reserved_at_20[0x10]; 8717 u8 op_mod[0x10]; 8718 8719 u8 reserved_at_40[0x60]; 8720 8721 u8 reserved_at_a0[0x8]; 8722 u8 table_index[0x18]; 8723 8724 u8 reserved_at_c0[0x140]; 8725 }; 8726 8727 struct mlx5_ifc_delete_fte_out_bits { 8728 u8 status[0x8]; 8729 u8 reserved_at_8[0x18]; 8730 8731 u8 syndrome[0x20]; 8732 8733 u8 reserved_at_40[0x40]; 8734 }; 8735 8736 struct mlx5_ifc_delete_fte_in_bits { 8737 u8 opcode[0x10]; 8738 u8 reserved_at_10[0x10]; 8739 8740 u8 reserved_at_20[0x10]; 8741 u8 op_mod[0x10]; 8742 8743 u8 other_vport[0x1]; 8744 u8 reserved_at_41[0xf]; 8745 u8 vport_number[0x10]; 8746 8747 u8 reserved_at_60[0x20]; 8748 8749 u8 table_type[0x8]; 8750 u8 reserved_at_88[0x18]; 8751 8752 u8 reserved_at_a0[0x8]; 8753 u8 table_id[0x18]; 8754 8755 u8 reserved_at_c0[0x40]; 8756 8757 u8 flow_index[0x20]; 8758 8759 u8 reserved_at_120[0xe0]; 8760 }; 8761 8762 struct mlx5_ifc_dealloc_xrcd_out_bits { 8763 u8 status[0x8]; 8764 u8 reserved_at_8[0x18]; 8765 8766 u8 syndrome[0x20]; 8767 8768 u8 reserved_at_40[0x40]; 8769 }; 8770 8771 struct mlx5_ifc_dealloc_xrcd_in_bits { 8772 u8 opcode[0x10]; 8773 u8 uid[0x10]; 8774 8775 u8 reserved_at_20[0x10]; 8776 u8 op_mod[0x10]; 8777 8778 u8 reserved_at_40[0x8]; 8779 u8 xrcd[0x18]; 8780 8781 u8 reserved_at_60[0x20]; 8782 }; 8783 8784 struct mlx5_ifc_dealloc_uar_out_bits { 8785 u8 status[0x8]; 8786 u8 reserved_at_8[0x18]; 8787 8788 u8 syndrome[0x20]; 8789 8790 u8 reserved_at_40[0x40]; 8791 }; 8792 8793 struct mlx5_ifc_dealloc_uar_in_bits { 8794 u8 opcode[0x10]; 8795 u8 uid[0x10]; 8796 8797 u8 reserved_at_20[0x10]; 8798 u8 op_mod[0x10]; 8799 8800 u8 reserved_at_40[0x8]; 8801 u8 uar[0x18]; 8802 8803 u8 reserved_at_60[0x20]; 8804 }; 8805 8806 struct mlx5_ifc_dealloc_transport_domain_out_bits { 8807 u8 status[0x8]; 8808 u8 reserved_at_8[0x18]; 8809 8810 u8 syndrome[0x20]; 8811 8812 u8 reserved_at_40[0x40]; 8813 }; 8814 8815 struct mlx5_ifc_dealloc_transport_domain_in_bits { 8816 u8 opcode[0x10]; 8817 u8 uid[0x10]; 8818 8819 u8 reserved_at_20[0x10]; 8820 u8 op_mod[0x10]; 8821 8822 u8 reserved_at_40[0x8]; 8823 u8 transport_domain[0x18]; 8824 8825 u8 reserved_at_60[0x20]; 8826 }; 8827 8828 struct mlx5_ifc_dealloc_q_counter_out_bits { 8829 u8 status[0x8]; 8830 u8 reserved_at_8[0x18]; 8831 8832 u8 syndrome[0x20]; 8833 8834 u8 reserved_at_40[0x40]; 8835 }; 8836 8837 struct mlx5_ifc_dealloc_q_counter_in_bits { 8838 u8 opcode[0x10]; 8839 u8 reserved_at_10[0x10]; 8840 8841 u8 reserved_at_20[0x10]; 8842 u8 op_mod[0x10]; 8843 8844 u8 reserved_at_40[0x18]; 8845 u8 counter_set_id[0x8]; 8846 8847 u8 reserved_at_60[0x20]; 8848 }; 8849 8850 struct mlx5_ifc_dealloc_pd_out_bits { 8851 u8 status[0x8]; 8852 u8 reserved_at_8[0x18]; 8853 8854 u8 syndrome[0x20]; 8855 8856 u8 reserved_at_40[0x40]; 8857 }; 8858 8859 struct mlx5_ifc_dealloc_pd_in_bits { 8860 u8 opcode[0x10]; 8861 u8 uid[0x10]; 8862 8863 u8 reserved_at_20[0x10]; 8864 u8 op_mod[0x10]; 8865 8866 u8 reserved_at_40[0x8]; 8867 u8 pd[0x18]; 8868 8869 u8 reserved_at_60[0x20]; 8870 }; 8871 8872 struct mlx5_ifc_dealloc_flow_counter_out_bits { 8873 u8 status[0x8]; 8874 u8 reserved_at_8[0x18]; 8875 8876 u8 syndrome[0x20]; 8877 8878 u8 reserved_at_40[0x40]; 8879 }; 8880 8881 struct mlx5_ifc_dealloc_flow_counter_in_bits { 8882 u8 opcode[0x10]; 8883 u8 reserved_at_10[0x10]; 8884 8885 u8 reserved_at_20[0x10]; 8886 u8 op_mod[0x10]; 8887 8888 u8 flow_counter_id[0x20]; 8889 8890 u8 reserved_at_60[0x20]; 8891 }; 8892 8893 struct mlx5_ifc_create_xrq_out_bits { 8894 u8 status[0x8]; 8895 u8 reserved_at_8[0x18]; 8896 8897 u8 syndrome[0x20]; 8898 8899 u8 reserved_at_40[0x8]; 8900 u8 xrqn[0x18]; 8901 8902 u8 reserved_at_60[0x20]; 8903 }; 8904 8905 struct mlx5_ifc_create_xrq_in_bits { 8906 u8 opcode[0x10]; 8907 u8 uid[0x10]; 8908 8909 u8 reserved_at_20[0x10]; 8910 u8 op_mod[0x10]; 8911 8912 u8 reserved_at_40[0x40]; 8913 8914 struct mlx5_ifc_xrqc_bits xrq_context; 8915 }; 8916 8917 struct mlx5_ifc_create_xrc_srq_out_bits { 8918 u8 status[0x8]; 8919 u8 reserved_at_8[0x18]; 8920 8921 u8 syndrome[0x20]; 8922 8923 u8 reserved_at_40[0x8]; 8924 u8 xrc_srqn[0x18]; 8925 8926 u8 reserved_at_60[0x20]; 8927 }; 8928 8929 struct mlx5_ifc_create_xrc_srq_in_bits { 8930 u8 opcode[0x10]; 8931 u8 uid[0x10]; 8932 8933 u8 reserved_at_20[0x10]; 8934 u8 op_mod[0x10]; 8935 8936 u8 reserved_at_40[0x40]; 8937 8938 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 8939 8940 u8 reserved_at_280[0x60]; 8941 8942 u8 xrc_srq_umem_valid[0x1]; 8943 u8 reserved_at_2e1[0x1f]; 8944 8945 u8 reserved_at_300[0x580]; 8946 8947 u8 pas[][0x40]; 8948 }; 8949 8950 struct mlx5_ifc_create_tis_out_bits { 8951 u8 status[0x8]; 8952 u8 reserved_at_8[0x18]; 8953 8954 u8 syndrome[0x20]; 8955 8956 u8 reserved_at_40[0x8]; 8957 u8 tisn[0x18]; 8958 8959 u8 reserved_at_60[0x20]; 8960 }; 8961 8962 struct mlx5_ifc_create_tis_in_bits { 8963 u8 opcode[0x10]; 8964 u8 uid[0x10]; 8965 8966 u8 reserved_at_20[0x10]; 8967 u8 op_mod[0x10]; 8968 8969 u8 reserved_at_40[0xc0]; 8970 8971 struct mlx5_ifc_tisc_bits ctx; 8972 }; 8973 8974 struct mlx5_ifc_create_tir_out_bits { 8975 u8 status[0x8]; 8976 u8 icm_address_63_40[0x18]; 8977 8978 u8 syndrome[0x20]; 8979 8980 u8 icm_address_39_32[0x8]; 8981 u8 tirn[0x18]; 8982 8983 u8 icm_address_31_0[0x20]; 8984 }; 8985 8986 struct mlx5_ifc_create_tir_in_bits { 8987 u8 opcode[0x10]; 8988 u8 uid[0x10]; 8989 8990 u8 reserved_at_20[0x10]; 8991 u8 op_mod[0x10]; 8992 8993 u8 reserved_at_40[0xc0]; 8994 8995 struct mlx5_ifc_tirc_bits ctx; 8996 }; 8997 8998 struct mlx5_ifc_create_srq_out_bits { 8999 u8 status[0x8]; 9000 u8 reserved_at_8[0x18]; 9001 9002 u8 syndrome[0x20]; 9003 9004 u8 reserved_at_40[0x8]; 9005 u8 srqn[0x18]; 9006 9007 u8 reserved_at_60[0x20]; 9008 }; 9009 9010 struct mlx5_ifc_create_srq_in_bits { 9011 u8 opcode[0x10]; 9012 u8 uid[0x10]; 9013 9014 u8 reserved_at_20[0x10]; 9015 u8 op_mod[0x10]; 9016 9017 u8 reserved_at_40[0x40]; 9018 9019 struct mlx5_ifc_srqc_bits srq_context_entry; 9020 9021 u8 reserved_at_280[0x600]; 9022 9023 u8 pas[][0x40]; 9024 }; 9025 9026 struct mlx5_ifc_create_sq_out_bits { 9027 u8 status[0x8]; 9028 u8 reserved_at_8[0x18]; 9029 9030 u8 syndrome[0x20]; 9031 9032 u8 reserved_at_40[0x8]; 9033 u8 sqn[0x18]; 9034 9035 u8 reserved_at_60[0x20]; 9036 }; 9037 9038 struct mlx5_ifc_create_sq_in_bits { 9039 u8 opcode[0x10]; 9040 u8 uid[0x10]; 9041 9042 u8 reserved_at_20[0x10]; 9043 u8 op_mod[0x10]; 9044 9045 u8 reserved_at_40[0xc0]; 9046 9047 struct mlx5_ifc_sqc_bits ctx; 9048 }; 9049 9050 struct mlx5_ifc_create_scheduling_element_out_bits { 9051 u8 status[0x8]; 9052 u8 reserved_at_8[0x18]; 9053 9054 u8 syndrome[0x20]; 9055 9056 u8 reserved_at_40[0x40]; 9057 9058 u8 scheduling_element_id[0x20]; 9059 9060 u8 reserved_at_a0[0x160]; 9061 }; 9062 9063 struct mlx5_ifc_create_scheduling_element_in_bits { 9064 u8 opcode[0x10]; 9065 u8 reserved_at_10[0x10]; 9066 9067 u8 reserved_at_20[0x10]; 9068 u8 op_mod[0x10]; 9069 9070 u8 scheduling_hierarchy[0x8]; 9071 u8 reserved_at_48[0x18]; 9072 9073 u8 reserved_at_60[0xa0]; 9074 9075 struct mlx5_ifc_scheduling_context_bits scheduling_context; 9076 9077 u8 reserved_at_300[0x100]; 9078 }; 9079 9080 struct mlx5_ifc_create_rqt_out_bits { 9081 u8 status[0x8]; 9082 u8 reserved_at_8[0x18]; 9083 9084 u8 syndrome[0x20]; 9085 9086 u8 reserved_at_40[0x8]; 9087 u8 rqtn[0x18]; 9088 9089 u8 reserved_at_60[0x20]; 9090 }; 9091 9092 struct mlx5_ifc_create_rqt_in_bits { 9093 u8 opcode[0x10]; 9094 u8 uid[0x10]; 9095 9096 u8 reserved_at_20[0x10]; 9097 u8 op_mod[0x10]; 9098 9099 u8 reserved_at_40[0xc0]; 9100 9101 struct mlx5_ifc_rqtc_bits rqt_context; 9102 }; 9103 9104 struct mlx5_ifc_create_rq_out_bits { 9105 u8 status[0x8]; 9106 u8 reserved_at_8[0x18]; 9107 9108 u8 syndrome[0x20]; 9109 9110 u8 reserved_at_40[0x8]; 9111 u8 rqn[0x18]; 9112 9113 u8 reserved_at_60[0x20]; 9114 }; 9115 9116 struct mlx5_ifc_create_rq_in_bits { 9117 u8 opcode[0x10]; 9118 u8 uid[0x10]; 9119 9120 u8 reserved_at_20[0x10]; 9121 u8 op_mod[0x10]; 9122 9123 u8 reserved_at_40[0xc0]; 9124 9125 struct mlx5_ifc_rqc_bits ctx; 9126 }; 9127 9128 struct mlx5_ifc_create_rmp_out_bits { 9129 u8 status[0x8]; 9130 u8 reserved_at_8[0x18]; 9131 9132 u8 syndrome[0x20]; 9133 9134 u8 reserved_at_40[0x8]; 9135 u8 rmpn[0x18]; 9136 9137 u8 reserved_at_60[0x20]; 9138 }; 9139 9140 struct mlx5_ifc_create_rmp_in_bits { 9141 u8 opcode[0x10]; 9142 u8 uid[0x10]; 9143 9144 u8 reserved_at_20[0x10]; 9145 u8 op_mod[0x10]; 9146 9147 u8 reserved_at_40[0xc0]; 9148 9149 struct mlx5_ifc_rmpc_bits ctx; 9150 }; 9151 9152 struct mlx5_ifc_create_qp_out_bits { 9153 u8 status[0x8]; 9154 u8 reserved_at_8[0x18]; 9155 9156 u8 syndrome[0x20]; 9157 9158 u8 reserved_at_40[0x8]; 9159 u8 qpn[0x18]; 9160 9161 u8 ece[0x20]; 9162 }; 9163 9164 struct mlx5_ifc_create_qp_in_bits { 9165 u8 opcode[0x10]; 9166 u8 uid[0x10]; 9167 9168 u8 reserved_at_20[0x10]; 9169 u8 op_mod[0x10]; 9170 9171 u8 qpc_ext[0x1]; 9172 u8 reserved_at_41[0x7]; 9173 u8 input_qpn[0x18]; 9174 9175 u8 reserved_at_60[0x20]; 9176 u8 opt_param_mask[0x20]; 9177 9178 u8 ece[0x20]; 9179 9180 struct mlx5_ifc_qpc_bits qpc; 9181 9182 u8 wq_umem_offset[0x40]; 9183 9184 u8 wq_umem_id[0x20]; 9185 9186 u8 wq_umem_valid[0x1]; 9187 u8 reserved_at_861[0x1f]; 9188 9189 u8 pas[][0x40]; 9190 }; 9191 9192 struct mlx5_ifc_create_psv_out_bits { 9193 u8 status[0x8]; 9194 u8 reserved_at_8[0x18]; 9195 9196 u8 syndrome[0x20]; 9197 9198 u8 reserved_at_40[0x40]; 9199 9200 u8 reserved_at_80[0x8]; 9201 u8 psv0_index[0x18]; 9202 9203 u8 reserved_at_a0[0x8]; 9204 u8 psv1_index[0x18]; 9205 9206 u8 reserved_at_c0[0x8]; 9207 u8 psv2_index[0x18]; 9208 9209 u8 reserved_at_e0[0x8]; 9210 u8 psv3_index[0x18]; 9211 }; 9212 9213 struct mlx5_ifc_create_psv_in_bits { 9214 u8 opcode[0x10]; 9215 u8 reserved_at_10[0x10]; 9216 9217 u8 reserved_at_20[0x10]; 9218 u8 op_mod[0x10]; 9219 9220 u8 num_psv[0x4]; 9221 u8 reserved_at_44[0x4]; 9222 u8 pd[0x18]; 9223 9224 u8 reserved_at_60[0x20]; 9225 }; 9226 9227 struct mlx5_ifc_create_mkey_out_bits { 9228 u8 status[0x8]; 9229 u8 reserved_at_8[0x18]; 9230 9231 u8 syndrome[0x20]; 9232 9233 u8 reserved_at_40[0x8]; 9234 u8 mkey_index[0x18]; 9235 9236 u8 reserved_at_60[0x20]; 9237 }; 9238 9239 struct mlx5_ifc_create_mkey_in_bits { 9240 u8 opcode[0x10]; 9241 u8 uid[0x10]; 9242 9243 u8 reserved_at_20[0x10]; 9244 u8 op_mod[0x10]; 9245 9246 u8 reserved_at_40[0x20]; 9247 9248 u8 pg_access[0x1]; 9249 u8 mkey_umem_valid[0x1]; 9250 u8 data_direct[0x1]; 9251 u8 reserved_at_63[0x1d]; 9252 9253 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 9254 9255 u8 reserved_at_280[0x80]; 9256 9257 u8 translations_octword_actual_size[0x20]; 9258 9259 u8 reserved_at_320[0x560]; 9260 9261 u8 klm_pas_mtt[][0x20]; 9262 }; 9263 9264 enum { 9265 MLX5_FLOW_TABLE_TYPE_NIC_RX = 0x0, 9266 MLX5_FLOW_TABLE_TYPE_NIC_TX = 0x1, 9267 MLX5_FLOW_TABLE_TYPE_ESW_EGRESS_ACL = 0x2, 9268 MLX5_FLOW_TABLE_TYPE_ESW_INGRESS_ACL = 0x3, 9269 MLX5_FLOW_TABLE_TYPE_FDB = 0X4, 9270 MLX5_FLOW_TABLE_TYPE_SNIFFER_RX = 0X5, 9271 MLX5_FLOW_TABLE_TYPE_SNIFFER_TX = 0X6, 9272 }; 9273 9274 struct mlx5_ifc_create_flow_table_out_bits { 9275 u8 status[0x8]; 9276 u8 icm_address_63_40[0x18]; 9277 9278 u8 syndrome[0x20]; 9279 9280 u8 icm_address_39_32[0x8]; 9281 u8 table_id[0x18]; 9282 9283 u8 icm_address_31_0[0x20]; 9284 }; 9285 9286 struct mlx5_ifc_create_flow_table_in_bits { 9287 u8 opcode[0x10]; 9288 u8 uid[0x10]; 9289 9290 u8 reserved_at_20[0x10]; 9291 u8 op_mod[0x10]; 9292 9293 u8 other_vport[0x1]; 9294 u8 reserved_at_41[0xf]; 9295 u8 vport_number[0x10]; 9296 9297 u8 reserved_at_60[0x20]; 9298 9299 u8 table_type[0x8]; 9300 u8 reserved_at_88[0x18]; 9301 9302 u8 reserved_at_a0[0x20]; 9303 9304 struct mlx5_ifc_flow_table_context_bits flow_table_context; 9305 }; 9306 9307 struct mlx5_ifc_create_flow_group_out_bits { 9308 u8 status[0x8]; 9309 u8 reserved_at_8[0x18]; 9310 9311 u8 syndrome[0x20]; 9312 9313 u8 reserved_at_40[0x8]; 9314 u8 group_id[0x18]; 9315 9316 u8 reserved_at_60[0x20]; 9317 }; 9318 9319 enum { 9320 MLX5_CREATE_FLOW_GROUP_IN_GROUP_TYPE_TCAM_SUBTABLE = 0x0, 9321 MLX5_CREATE_FLOW_GROUP_IN_GROUP_TYPE_HASH_SPLIT = 0x1, 9322 }; 9323 9324 enum { 9325 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 9326 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 9327 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 9328 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3, 9329 }; 9330 9331 struct mlx5_ifc_create_flow_group_in_bits { 9332 u8 opcode[0x10]; 9333 u8 reserved_at_10[0x10]; 9334 9335 u8 reserved_at_20[0x10]; 9336 u8 op_mod[0x10]; 9337 9338 u8 other_vport[0x1]; 9339 u8 reserved_at_41[0xf]; 9340 u8 vport_number[0x10]; 9341 9342 u8 reserved_at_60[0x20]; 9343 9344 u8 table_type[0x8]; 9345 u8 reserved_at_88[0x4]; 9346 u8 group_type[0x4]; 9347 u8 reserved_at_90[0x10]; 9348 9349 u8 reserved_at_a0[0x8]; 9350 u8 table_id[0x18]; 9351 9352 u8 source_eswitch_owner_vhca_id_valid[0x1]; 9353 9354 u8 reserved_at_c1[0x1f]; 9355 9356 u8 start_flow_index[0x20]; 9357 9358 u8 reserved_at_100[0x20]; 9359 9360 u8 end_flow_index[0x20]; 9361 9362 u8 reserved_at_140[0x10]; 9363 u8 match_definer_id[0x10]; 9364 9365 u8 reserved_at_160[0x80]; 9366 9367 u8 reserved_at_1e0[0x18]; 9368 u8 match_criteria_enable[0x8]; 9369 9370 struct mlx5_ifc_fte_match_param_bits match_criteria; 9371 9372 u8 reserved_at_1200[0xe00]; 9373 }; 9374 9375 struct mlx5_ifc_create_eq_out_bits { 9376 u8 status[0x8]; 9377 u8 reserved_at_8[0x18]; 9378 9379 u8 syndrome[0x20]; 9380 9381 u8 reserved_at_40[0x18]; 9382 u8 eq_number[0x8]; 9383 9384 u8 reserved_at_60[0x20]; 9385 }; 9386 9387 struct mlx5_ifc_create_eq_in_bits { 9388 u8 opcode[0x10]; 9389 u8 uid[0x10]; 9390 9391 u8 reserved_at_20[0x10]; 9392 u8 op_mod[0x10]; 9393 9394 u8 reserved_at_40[0x40]; 9395 9396 struct mlx5_ifc_eqc_bits eq_context_entry; 9397 9398 u8 reserved_at_280[0x40]; 9399 9400 u8 event_bitmask[4][0x40]; 9401 9402 u8 reserved_at_3c0[0x4c0]; 9403 9404 u8 pas[][0x40]; 9405 }; 9406 9407 struct mlx5_ifc_create_dct_out_bits { 9408 u8 status[0x8]; 9409 u8 reserved_at_8[0x18]; 9410 9411 u8 syndrome[0x20]; 9412 9413 u8 reserved_at_40[0x8]; 9414 u8 dctn[0x18]; 9415 9416 u8 ece[0x20]; 9417 }; 9418 9419 struct mlx5_ifc_create_dct_in_bits { 9420 u8 opcode[0x10]; 9421 u8 uid[0x10]; 9422 9423 u8 reserved_at_20[0x10]; 9424 u8 op_mod[0x10]; 9425 9426 u8 reserved_at_40[0x40]; 9427 9428 struct mlx5_ifc_dctc_bits dct_context_entry; 9429 9430 u8 reserved_at_280[0x180]; 9431 }; 9432 9433 struct mlx5_ifc_create_cq_out_bits { 9434 u8 status[0x8]; 9435 u8 reserved_at_8[0x18]; 9436 9437 u8 syndrome[0x20]; 9438 9439 u8 reserved_at_40[0x8]; 9440 u8 cqn[0x18]; 9441 9442 u8 reserved_at_60[0x20]; 9443 }; 9444 9445 struct mlx5_ifc_create_cq_in_bits { 9446 u8 opcode[0x10]; 9447 u8 uid[0x10]; 9448 9449 u8 reserved_at_20[0x10]; 9450 u8 op_mod[0x10]; 9451 9452 u8 reserved_at_40[0x40]; 9453 9454 struct mlx5_ifc_cqc_bits cq_context; 9455 9456 u8 reserved_at_280[0x60]; 9457 9458 u8 cq_umem_valid[0x1]; 9459 u8 reserved_at_2e1[0x59f]; 9460 9461 u8 pas[][0x40]; 9462 }; 9463 9464 struct mlx5_ifc_config_int_moderation_out_bits { 9465 u8 status[0x8]; 9466 u8 reserved_at_8[0x18]; 9467 9468 u8 syndrome[0x20]; 9469 9470 u8 reserved_at_40[0x4]; 9471 u8 min_delay[0xc]; 9472 u8 int_vector[0x10]; 9473 9474 u8 reserved_at_60[0x20]; 9475 }; 9476 9477 enum { 9478 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0, 9479 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1, 9480 }; 9481 9482 struct mlx5_ifc_config_int_moderation_in_bits { 9483 u8 opcode[0x10]; 9484 u8 reserved_at_10[0x10]; 9485 9486 u8 reserved_at_20[0x10]; 9487 u8 op_mod[0x10]; 9488 9489 u8 reserved_at_40[0x4]; 9490 u8 min_delay[0xc]; 9491 u8 int_vector[0x10]; 9492 9493 u8 reserved_at_60[0x20]; 9494 }; 9495 9496 struct mlx5_ifc_attach_to_mcg_out_bits { 9497 u8 status[0x8]; 9498 u8 reserved_at_8[0x18]; 9499 9500 u8 syndrome[0x20]; 9501 9502 u8 reserved_at_40[0x40]; 9503 }; 9504 9505 struct mlx5_ifc_attach_to_mcg_in_bits { 9506 u8 opcode[0x10]; 9507 u8 uid[0x10]; 9508 9509 u8 reserved_at_20[0x10]; 9510 u8 op_mod[0x10]; 9511 9512 u8 reserved_at_40[0x8]; 9513 u8 qpn[0x18]; 9514 9515 u8 reserved_at_60[0x20]; 9516 9517 u8 multicast_gid[16][0x8]; 9518 }; 9519 9520 struct mlx5_ifc_arm_xrq_out_bits { 9521 u8 status[0x8]; 9522 u8 reserved_at_8[0x18]; 9523 9524 u8 syndrome[0x20]; 9525 9526 u8 reserved_at_40[0x40]; 9527 }; 9528 9529 struct mlx5_ifc_arm_xrq_in_bits { 9530 u8 opcode[0x10]; 9531 u8 reserved_at_10[0x10]; 9532 9533 u8 reserved_at_20[0x10]; 9534 u8 op_mod[0x10]; 9535 9536 u8 reserved_at_40[0x8]; 9537 u8 xrqn[0x18]; 9538 9539 u8 reserved_at_60[0x10]; 9540 u8 lwm[0x10]; 9541 }; 9542 9543 struct mlx5_ifc_arm_xrc_srq_out_bits { 9544 u8 status[0x8]; 9545 u8 reserved_at_8[0x18]; 9546 9547 u8 syndrome[0x20]; 9548 9549 u8 reserved_at_40[0x40]; 9550 }; 9551 9552 enum { 9553 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1, 9554 }; 9555 9556 struct mlx5_ifc_arm_xrc_srq_in_bits { 9557 u8 opcode[0x10]; 9558 u8 uid[0x10]; 9559 9560 u8 reserved_at_20[0x10]; 9561 u8 op_mod[0x10]; 9562 9563 u8 reserved_at_40[0x8]; 9564 u8 xrc_srqn[0x18]; 9565 9566 u8 reserved_at_60[0x10]; 9567 u8 lwm[0x10]; 9568 }; 9569 9570 struct mlx5_ifc_arm_rq_out_bits { 9571 u8 status[0x8]; 9572 u8 reserved_at_8[0x18]; 9573 9574 u8 syndrome[0x20]; 9575 9576 u8 reserved_at_40[0x40]; 9577 }; 9578 9579 enum { 9580 MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1, 9581 MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2, 9582 }; 9583 9584 struct mlx5_ifc_arm_rq_in_bits { 9585 u8 opcode[0x10]; 9586 u8 uid[0x10]; 9587 9588 u8 reserved_at_20[0x10]; 9589 u8 op_mod[0x10]; 9590 9591 u8 reserved_at_40[0x8]; 9592 u8 srq_number[0x18]; 9593 9594 u8 reserved_at_60[0x10]; 9595 u8 lwm[0x10]; 9596 }; 9597 9598 struct mlx5_ifc_arm_dct_out_bits { 9599 u8 status[0x8]; 9600 u8 reserved_at_8[0x18]; 9601 9602 u8 syndrome[0x20]; 9603 9604 u8 reserved_at_40[0x40]; 9605 }; 9606 9607 struct mlx5_ifc_arm_dct_in_bits { 9608 u8 opcode[0x10]; 9609 u8 reserved_at_10[0x10]; 9610 9611 u8 reserved_at_20[0x10]; 9612 u8 op_mod[0x10]; 9613 9614 u8 reserved_at_40[0x8]; 9615 u8 dct_number[0x18]; 9616 9617 u8 reserved_at_60[0x20]; 9618 }; 9619 9620 struct mlx5_ifc_alloc_xrcd_out_bits { 9621 u8 status[0x8]; 9622 u8 reserved_at_8[0x18]; 9623 9624 u8 syndrome[0x20]; 9625 9626 u8 reserved_at_40[0x8]; 9627 u8 xrcd[0x18]; 9628 9629 u8 reserved_at_60[0x20]; 9630 }; 9631 9632 struct mlx5_ifc_alloc_xrcd_in_bits { 9633 u8 opcode[0x10]; 9634 u8 uid[0x10]; 9635 9636 u8 reserved_at_20[0x10]; 9637 u8 op_mod[0x10]; 9638 9639 u8 reserved_at_40[0x40]; 9640 }; 9641 9642 struct mlx5_ifc_alloc_uar_out_bits { 9643 u8 status[0x8]; 9644 u8 reserved_at_8[0x18]; 9645 9646 u8 syndrome[0x20]; 9647 9648 u8 reserved_at_40[0x8]; 9649 u8 uar[0x18]; 9650 9651 u8 reserved_at_60[0x20]; 9652 }; 9653 9654 struct mlx5_ifc_alloc_uar_in_bits { 9655 u8 opcode[0x10]; 9656 u8 uid[0x10]; 9657 9658 u8 reserved_at_20[0x10]; 9659 u8 op_mod[0x10]; 9660 9661 u8 reserved_at_40[0x40]; 9662 }; 9663 9664 struct mlx5_ifc_alloc_transport_domain_out_bits { 9665 u8 status[0x8]; 9666 u8 reserved_at_8[0x18]; 9667 9668 u8 syndrome[0x20]; 9669 9670 u8 reserved_at_40[0x8]; 9671 u8 transport_domain[0x18]; 9672 9673 u8 reserved_at_60[0x20]; 9674 }; 9675 9676 struct mlx5_ifc_alloc_transport_domain_in_bits { 9677 u8 opcode[0x10]; 9678 u8 uid[0x10]; 9679 9680 u8 reserved_at_20[0x10]; 9681 u8 op_mod[0x10]; 9682 9683 u8 reserved_at_40[0x40]; 9684 }; 9685 9686 struct mlx5_ifc_alloc_q_counter_out_bits { 9687 u8 status[0x8]; 9688 u8 reserved_at_8[0x18]; 9689 9690 u8 syndrome[0x20]; 9691 9692 u8 reserved_at_40[0x18]; 9693 u8 counter_set_id[0x8]; 9694 9695 u8 reserved_at_60[0x20]; 9696 }; 9697 9698 struct mlx5_ifc_alloc_q_counter_in_bits { 9699 u8 opcode[0x10]; 9700 u8 uid[0x10]; 9701 9702 u8 reserved_at_20[0x10]; 9703 u8 op_mod[0x10]; 9704 9705 u8 reserved_at_40[0x40]; 9706 }; 9707 9708 struct mlx5_ifc_alloc_pd_out_bits { 9709 u8 status[0x8]; 9710 u8 reserved_at_8[0x18]; 9711 9712 u8 syndrome[0x20]; 9713 9714 u8 reserved_at_40[0x8]; 9715 u8 pd[0x18]; 9716 9717 u8 reserved_at_60[0x20]; 9718 }; 9719 9720 struct mlx5_ifc_alloc_pd_in_bits { 9721 u8 opcode[0x10]; 9722 u8 uid[0x10]; 9723 9724 u8 reserved_at_20[0x10]; 9725 u8 op_mod[0x10]; 9726 9727 u8 reserved_at_40[0x40]; 9728 }; 9729 9730 struct mlx5_ifc_alloc_flow_counter_out_bits { 9731 u8 status[0x8]; 9732 u8 reserved_at_8[0x18]; 9733 9734 u8 syndrome[0x20]; 9735 9736 u8 flow_counter_id[0x20]; 9737 9738 u8 reserved_at_60[0x20]; 9739 }; 9740 9741 struct mlx5_ifc_alloc_flow_counter_in_bits { 9742 u8 opcode[0x10]; 9743 u8 reserved_at_10[0x10]; 9744 9745 u8 reserved_at_20[0x10]; 9746 u8 op_mod[0x10]; 9747 9748 u8 reserved_at_40[0x33]; 9749 u8 flow_counter_bulk_log_size[0x5]; 9750 u8 flow_counter_bulk[0x8]; 9751 }; 9752 9753 struct mlx5_ifc_add_vxlan_udp_dport_out_bits { 9754 u8 status[0x8]; 9755 u8 reserved_at_8[0x18]; 9756 9757 u8 syndrome[0x20]; 9758 9759 u8 reserved_at_40[0x40]; 9760 }; 9761 9762 struct mlx5_ifc_add_vxlan_udp_dport_in_bits { 9763 u8 opcode[0x10]; 9764 u8 reserved_at_10[0x10]; 9765 9766 u8 reserved_at_20[0x10]; 9767 u8 op_mod[0x10]; 9768 9769 u8 reserved_at_40[0x20]; 9770 9771 u8 reserved_at_60[0x10]; 9772 u8 vxlan_udp_port[0x10]; 9773 }; 9774 9775 struct mlx5_ifc_set_pp_rate_limit_out_bits { 9776 u8 status[0x8]; 9777 u8 reserved_at_8[0x18]; 9778 9779 u8 syndrome[0x20]; 9780 9781 u8 reserved_at_40[0x40]; 9782 }; 9783 9784 struct mlx5_ifc_set_pp_rate_limit_context_bits { 9785 u8 rate_limit[0x20]; 9786 9787 u8 burst_upper_bound[0x20]; 9788 9789 u8 reserved_at_40[0x10]; 9790 u8 typical_packet_size[0x10]; 9791 9792 u8 reserved_at_60[0x120]; 9793 }; 9794 9795 struct mlx5_ifc_set_pp_rate_limit_in_bits { 9796 u8 opcode[0x10]; 9797 u8 uid[0x10]; 9798 9799 u8 reserved_at_20[0x10]; 9800 u8 op_mod[0x10]; 9801 9802 u8 reserved_at_40[0x10]; 9803 u8 rate_limit_index[0x10]; 9804 9805 u8 reserved_at_60[0x20]; 9806 9807 struct mlx5_ifc_set_pp_rate_limit_context_bits ctx; 9808 }; 9809 9810 struct mlx5_ifc_access_register_out_bits { 9811 u8 status[0x8]; 9812 u8 reserved_at_8[0x18]; 9813 9814 u8 syndrome[0x20]; 9815 9816 u8 reserved_at_40[0x40]; 9817 9818 u8 register_data[][0x20]; 9819 }; 9820 9821 enum { 9822 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0, 9823 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1, 9824 }; 9825 9826 struct mlx5_ifc_access_register_in_bits { 9827 u8 opcode[0x10]; 9828 u8 reserved_at_10[0x10]; 9829 9830 u8 reserved_at_20[0x10]; 9831 u8 op_mod[0x10]; 9832 9833 u8 reserved_at_40[0x10]; 9834 u8 register_id[0x10]; 9835 9836 u8 argument[0x20]; 9837 9838 u8 register_data[][0x20]; 9839 }; 9840 9841 struct mlx5_ifc_sltp_reg_bits { 9842 u8 status[0x4]; 9843 u8 version[0x4]; 9844 u8 local_port[0x8]; 9845 u8 pnat[0x2]; 9846 u8 reserved_at_12[0x2]; 9847 u8 lane[0x4]; 9848 u8 reserved_at_18[0x8]; 9849 9850 u8 reserved_at_20[0x20]; 9851 9852 u8 reserved_at_40[0x7]; 9853 u8 polarity[0x1]; 9854 u8 ob_tap0[0x8]; 9855 u8 ob_tap1[0x8]; 9856 u8 ob_tap2[0x8]; 9857 9858 u8 reserved_at_60[0xc]; 9859 u8 ob_preemp_mode[0x4]; 9860 u8 ob_reg[0x8]; 9861 u8 ob_bias[0x8]; 9862 9863 u8 reserved_at_80[0x20]; 9864 }; 9865 9866 struct mlx5_ifc_slrg_reg_bits { 9867 u8 status[0x4]; 9868 u8 version[0x4]; 9869 u8 local_port[0x8]; 9870 u8 pnat[0x2]; 9871 u8 reserved_at_12[0x2]; 9872 u8 lane[0x4]; 9873 u8 reserved_at_18[0x8]; 9874 9875 u8 time_to_link_up[0x10]; 9876 u8 reserved_at_30[0xc]; 9877 u8 grade_lane_speed[0x4]; 9878 9879 u8 grade_version[0x8]; 9880 u8 grade[0x18]; 9881 9882 u8 reserved_at_60[0x4]; 9883 u8 height_grade_type[0x4]; 9884 u8 height_grade[0x18]; 9885 9886 u8 height_dz[0x10]; 9887 u8 height_dv[0x10]; 9888 9889 u8 reserved_at_a0[0x10]; 9890 u8 height_sigma[0x10]; 9891 9892 u8 reserved_at_c0[0x20]; 9893 9894 u8 reserved_at_e0[0x4]; 9895 u8 phase_grade_type[0x4]; 9896 u8 phase_grade[0x18]; 9897 9898 u8 reserved_at_100[0x8]; 9899 u8 phase_eo_pos[0x8]; 9900 u8 reserved_at_110[0x8]; 9901 u8 phase_eo_neg[0x8]; 9902 9903 u8 ffe_set_tested[0x10]; 9904 u8 test_errors_per_lane[0x10]; 9905 }; 9906 9907 struct mlx5_ifc_pvlc_reg_bits { 9908 u8 reserved_at_0[0x8]; 9909 u8 local_port[0x8]; 9910 u8 reserved_at_10[0x10]; 9911 9912 u8 reserved_at_20[0x1c]; 9913 u8 vl_hw_cap[0x4]; 9914 9915 u8 reserved_at_40[0x1c]; 9916 u8 vl_admin[0x4]; 9917 9918 u8 reserved_at_60[0x1c]; 9919 u8 vl_operational[0x4]; 9920 }; 9921 9922 struct mlx5_ifc_pude_reg_bits { 9923 u8 swid[0x8]; 9924 u8 local_port[0x8]; 9925 u8 reserved_at_10[0x4]; 9926 u8 admin_status[0x4]; 9927 u8 reserved_at_18[0x4]; 9928 u8 oper_status[0x4]; 9929 9930 u8 reserved_at_20[0x60]; 9931 }; 9932 9933 struct mlx5_ifc_ptys_reg_bits { 9934 u8 reserved_at_0[0x1]; 9935 u8 an_disable_admin[0x1]; 9936 u8 an_disable_cap[0x1]; 9937 u8 reserved_at_3[0x5]; 9938 u8 local_port[0x8]; 9939 u8 reserved_at_10[0x8]; 9940 u8 plane_ind[0x4]; 9941 u8 reserved_at_1c[0x1]; 9942 u8 proto_mask[0x3]; 9943 9944 u8 an_status[0x4]; 9945 u8 reserved_at_24[0xc]; 9946 u8 data_rate_oper[0x10]; 9947 9948 u8 ext_eth_proto_capability[0x20]; 9949 9950 u8 eth_proto_capability[0x20]; 9951 9952 u8 ib_link_width_capability[0x10]; 9953 u8 ib_proto_capability[0x10]; 9954 9955 u8 ext_eth_proto_admin[0x20]; 9956 9957 u8 eth_proto_admin[0x20]; 9958 9959 u8 ib_link_width_admin[0x10]; 9960 u8 ib_proto_admin[0x10]; 9961 9962 u8 ext_eth_proto_oper[0x20]; 9963 9964 u8 eth_proto_oper[0x20]; 9965 9966 u8 ib_link_width_oper[0x10]; 9967 u8 ib_proto_oper[0x10]; 9968 9969 u8 reserved_at_160[0x1c]; 9970 u8 connector_type[0x4]; 9971 9972 u8 eth_proto_lp_advertise[0x20]; 9973 9974 u8 reserved_at_1a0[0x60]; 9975 }; 9976 9977 struct mlx5_ifc_mlcr_reg_bits { 9978 u8 reserved_at_0[0x8]; 9979 u8 local_port[0x8]; 9980 u8 reserved_at_10[0x20]; 9981 9982 u8 beacon_duration[0x10]; 9983 u8 reserved_at_40[0x10]; 9984 9985 u8 beacon_remain[0x10]; 9986 }; 9987 9988 struct mlx5_ifc_ptas_reg_bits { 9989 u8 reserved_at_0[0x20]; 9990 9991 u8 algorithm_options[0x10]; 9992 u8 reserved_at_30[0x4]; 9993 u8 repetitions_mode[0x4]; 9994 u8 num_of_repetitions[0x8]; 9995 9996 u8 grade_version[0x8]; 9997 u8 height_grade_type[0x4]; 9998 u8 phase_grade_type[0x4]; 9999 u8 height_grade_weight[0x8]; 10000 u8 phase_grade_weight[0x8]; 10001 10002 u8 gisim_measure_bits[0x10]; 10003 u8 adaptive_tap_measure_bits[0x10]; 10004 10005 u8 ber_bath_high_error_threshold[0x10]; 10006 u8 ber_bath_mid_error_threshold[0x10]; 10007 10008 u8 ber_bath_low_error_threshold[0x10]; 10009 u8 one_ratio_high_threshold[0x10]; 10010 10011 u8 one_ratio_high_mid_threshold[0x10]; 10012 u8 one_ratio_low_mid_threshold[0x10]; 10013 10014 u8 one_ratio_low_threshold[0x10]; 10015 u8 ndeo_error_threshold[0x10]; 10016 10017 u8 mixer_offset_step_size[0x10]; 10018 u8 reserved_at_110[0x8]; 10019 u8 mix90_phase_for_voltage_bath[0x8]; 10020 10021 u8 mixer_offset_start[0x10]; 10022 u8 mixer_offset_end[0x10]; 10023 10024 u8 reserved_at_140[0x15]; 10025 u8 ber_test_time[0xb]; 10026 }; 10027 10028 struct mlx5_ifc_pspa_reg_bits { 10029 u8 swid[0x8]; 10030 u8 local_port[0x8]; 10031 u8 sub_port[0x8]; 10032 u8 reserved_at_18[0x8]; 10033 10034 u8 reserved_at_20[0x20]; 10035 }; 10036 10037 struct mlx5_ifc_pqdr_reg_bits { 10038 u8 reserved_at_0[0x8]; 10039 u8 local_port[0x8]; 10040 u8 reserved_at_10[0x5]; 10041 u8 prio[0x3]; 10042 u8 reserved_at_18[0x6]; 10043 u8 mode[0x2]; 10044 10045 u8 reserved_at_20[0x20]; 10046 10047 u8 reserved_at_40[0x10]; 10048 u8 min_threshold[0x10]; 10049 10050 u8 reserved_at_60[0x10]; 10051 u8 max_threshold[0x10]; 10052 10053 u8 reserved_at_80[0x10]; 10054 u8 mark_probability_denominator[0x10]; 10055 10056 u8 reserved_at_a0[0x60]; 10057 }; 10058 10059 struct mlx5_ifc_ppsc_reg_bits { 10060 u8 reserved_at_0[0x8]; 10061 u8 local_port[0x8]; 10062 u8 reserved_at_10[0x10]; 10063 10064 u8 reserved_at_20[0x60]; 10065 10066 u8 reserved_at_80[0x1c]; 10067 u8 wrps_admin[0x4]; 10068 10069 u8 reserved_at_a0[0x1c]; 10070 u8 wrps_status[0x4]; 10071 10072 u8 reserved_at_c0[0x8]; 10073 u8 up_threshold[0x8]; 10074 u8 reserved_at_d0[0x8]; 10075 u8 down_threshold[0x8]; 10076 10077 u8 reserved_at_e0[0x20]; 10078 10079 u8 reserved_at_100[0x1c]; 10080 u8 srps_admin[0x4]; 10081 10082 u8 reserved_at_120[0x1c]; 10083 u8 srps_status[0x4]; 10084 10085 u8 reserved_at_140[0x40]; 10086 }; 10087 10088 struct mlx5_ifc_pplr_reg_bits { 10089 u8 reserved_at_0[0x8]; 10090 u8 local_port[0x8]; 10091 u8 reserved_at_10[0x10]; 10092 10093 u8 reserved_at_20[0x8]; 10094 u8 lb_cap[0x8]; 10095 u8 reserved_at_30[0x8]; 10096 u8 lb_en[0x8]; 10097 }; 10098 10099 struct mlx5_ifc_pplm_reg_bits { 10100 u8 reserved_at_0[0x8]; 10101 u8 local_port[0x8]; 10102 u8 reserved_at_10[0x10]; 10103 10104 u8 reserved_at_20[0x20]; 10105 10106 u8 port_profile_mode[0x8]; 10107 u8 static_port_profile[0x8]; 10108 u8 active_port_profile[0x8]; 10109 u8 reserved_at_58[0x8]; 10110 10111 u8 retransmission_active[0x8]; 10112 u8 fec_mode_active[0x18]; 10113 10114 u8 rs_fec_correction_bypass_cap[0x4]; 10115 u8 reserved_at_84[0x8]; 10116 u8 fec_override_cap_56g[0x4]; 10117 u8 fec_override_cap_100g[0x4]; 10118 u8 fec_override_cap_50g[0x4]; 10119 u8 fec_override_cap_25g[0x4]; 10120 u8 fec_override_cap_10g_40g[0x4]; 10121 10122 u8 rs_fec_correction_bypass_admin[0x4]; 10123 u8 reserved_at_a4[0x8]; 10124 u8 fec_override_admin_56g[0x4]; 10125 u8 fec_override_admin_100g[0x4]; 10126 u8 fec_override_admin_50g[0x4]; 10127 u8 fec_override_admin_25g[0x4]; 10128 u8 fec_override_admin_10g_40g[0x4]; 10129 10130 u8 fec_override_cap_400g_8x[0x10]; 10131 u8 fec_override_cap_200g_4x[0x10]; 10132 10133 u8 fec_override_cap_100g_2x[0x10]; 10134 u8 fec_override_cap_50g_1x[0x10]; 10135 10136 u8 fec_override_admin_400g_8x[0x10]; 10137 u8 fec_override_admin_200g_4x[0x10]; 10138 10139 u8 fec_override_admin_100g_2x[0x10]; 10140 u8 fec_override_admin_50g_1x[0x10]; 10141 10142 u8 fec_override_cap_800g_8x[0x10]; 10143 u8 fec_override_cap_400g_4x[0x10]; 10144 10145 u8 fec_override_cap_200g_2x[0x10]; 10146 u8 fec_override_cap_100g_1x[0x10]; 10147 10148 u8 reserved_at_180[0xa0]; 10149 10150 u8 fec_override_admin_800g_8x[0x10]; 10151 u8 fec_override_admin_400g_4x[0x10]; 10152 10153 u8 fec_override_admin_200g_2x[0x10]; 10154 u8 fec_override_admin_100g_1x[0x10]; 10155 10156 u8 reserved_at_260[0x20]; 10157 }; 10158 10159 struct mlx5_ifc_ppcnt_reg_bits { 10160 u8 swid[0x8]; 10161 u8 local_port[0x8]; 10162 u8 pnat[0x2]; 10163 u8 reserved_at_12[0x8]; 10164 u8 grp[0x6]; 10165 10166 u8 clr[0x1]; 10167 u8 reserved_at_21[0x13]; 10168 u8 plane_ind[0x4]; 10169 u8 reserved_at_38[0x3]; 10170 u8 prio_tc[0x5]; 10171 10172 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set; 10173 }; 10174 10175 struct mlx5_ifc_mpein_reg_bits { 10176 u8 reserved_at_0[0x2]; 10177 u8 depth[0x6]; 10178 u8 pcie_index[0x8]; 10179 u8 node[0x8]; 10180 u8 reserved_at_18[0x8]; 10181 10182 u8 capability_mask[0x20]; 10183 10184 u8 reserved_at_40[0x8]; 10185 u8 link_width_enabled[0x8]; 10186 u8 link_speed_enabled[0x10]; 10187 10188 u8 lane0_physical_position[0x8]; 10189 u8 link_width_active[0x8]; 10190 u8 link_speed_active[0x10]; 10191 10192 u8 num_of_pfs[0x10]; 10193 u8 num_of_vfs[0x10]; 10194 10195 u8 bdf0[0x10]; 10196 u8 reserved_at_b0[0x10]; 10197 10198 u8 max_read_request_size[0x4]; 10199 u8 max_payload_size[0x4]; 10200 u8 reserved_at_c8[0x5]; 10201 u8 pwr_status[0x3]; 10202 u8 port_type[0x4]; 10203 u8 reserved_at_d4[0xb]; 10204 u8 lane_reversal[0x1]; 10205 10206 u8 reserved_at_e0[0x14]; 10207 u8 pci_power[0xc]; 10208 10209 u8 reserved_at_100[0x20]; 10210 10211 u8 device_status[0x10]; 10212 u8 port_state[0x8]; 10213 u8 reserved_at_138[0x8]; 10214 10215 u8 reserved_at_140[0x10]; 10216 u8 receiver_detect_result[0x10]; 10217 10218 u8 reserved_at_160[0x20]; 10219 }; 10220 10221 struct mlx5_ifc_mpcnt_reg_bits { 10222 u8 reserved_at_0[0x8]; 10223 u8 pcie_index[0x8]; 10224 u8 reserved_at_10[0xa]; 10225 u8 grp[0x6]; 10226 10227 u8 clr[0x1]; 10228 u8 reserved_at_21[0x1f]; 10229 10230 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set; 10231 }; 10232 10233 struct mlx5_ifc_ppad_reg_bits { 10234 u8 reserved_at_0[0x3]; 10235 u8 single_mac[0x1]; 10236 u8 reserved_at_4[0x4]; 10237 u8 local_port[0x8]; 10238 u8 mac_47_32[0x10]; 10239 10240 u8 mac_31_0[0x20]; 10241 10242 u8 reserved_at_40[0x40]; 10243 }; 10244 10245 struct mlx5_ifc_pmtu_reg_bits { 10246 u8 reserved_at_0[0x8]; 10247 u8 local_port[0x8]; 10248 u8 reserved_at_10[0x10]; 10249 10250 u8 max_mtu[0x10]; 10251 u8 reserved_at_30[0x10]; 10252 10253 u8 admin_mtu[0x10]; 10254 u8 reserved_at_50[0x10]; 10255 10256 u8 oper_mtu[0x10]; 10257 u8 reserved_at_70[0x10]; 10258 }; 10259 10260 struct mlx5_ifc_pmpr_reg_bits { 10261 u8 reserved_at_0[0x8]; 10262 u8 module[0x8]; 10263 u8 reserved_at_10[0x10]; 10264 10265 u8 reserved_at_20[0x18]; 10266 u8 attenuation_5g[0x8]; 10267 10268 u8 reserved_at_40[0x18]; 10269 u8 attenuation_7g[0x8]; 10270 10271 u8 reserved_at_60[0x18]; 10272 u8 attenuation_12g[0x8]; 10273 }; 10274 10275 struct mlx5_ifc_pmpe_reg_bits { 10276 u8 reserved_at_0[0x8]; 10277 u8 module[0x8]; 10278 u8 reserved_at_10[0xc]; 10279 u8 module_status[0x4]; 10280 10281 u8 reserved_at_20[0x60]; 10282 }; 10283 10284 struct mlx5_ifc_pmpc_reg_bits { 10285 u8 module_state_updated[32][0x8]; 10286 }; 10287 10288 struct mlx5_ifc_pmlpn_reg_bits { 10289 u8 reserved_at_0[0x4]; 10290 u8 mlpn_status[0x4]; 10291 u8 local_port[0x8]; 10292 u8 reserved_at_10[0x10]; 10293 10294 u8 e[0x1]; 10295 u8 reserved_at_21[0x1f]; 10296 }; 10297 10298 struct mlx5_ifc_pmlp_reg_bits { 10299 u8 rxtx[0x1]; 10300 u8 reserved_at_1[0x7]; 10301 u8 local_port[0x8]; 10302 u8 reserved_at_10[0x8]; 10303 u8 width[0x8]; 10304 10305 u8 lane0_module_mapping[0x20]; 10306 10307 u8 lane1_module_mapping[0x20]; 10308 10309 u8 lane2_module_mapping[0x20]; 10310 10311 u8 lane3_module_mapping[0x20]; 10312 10313 u8 reserved_at_a0[0x160]; 10314 }; 10315 10316 struct mlx5_ifc_pmaos_reg_bits { 10317 u8 reserved_at_0[0x8]; 10318 u8 module[0x8]; 10319 u8 reserved_at_10[0x4]; 10320 u8 admin_status[0x4]; 10321 u8 reserved_at_18[0x4]; 10322 u8 oper_status[0x4]; 10323 10324 u8 ase[0x1]; 10325 u8 ee[0x1]; 10326 u8 reserved_at_22[0x1c]; 10327 u8 e[0x2]; 10328 10329 u8 reserved_at_40[0x40]; 10330 }; 10331 10332 struct mlx5_ifc_plpc_reg_bits { 10333 u8 reserved_at_0[0x4]; 10334 u8 profile_id[0xc]; 10335 u8 reserved_at_10[0x4]; 10336 u8 proto_mask[0x4]; 10337 u8 reserved_at_18[0x8]; 10338 10339 u8 reserved_at_20[0x10]; 10340 u8 lane_speed[0x10]; 10341 10342 u8 reserved_at_40[0x17]; 10343 u8 lpbf[0x1]; 10344 u8 fec_mode_policy[0x8]; 10345 10346 u8 retransmission_capability[0x8]; 10347 u8 fec_mode_capability[0x18]; 10348 10349 u8 retransmission_support_admin[0x8]; 10350 u8 fec_mode_support_admin[0x18]; 10351 10352 u8 retransmission_request_admin[0x8]; 10353 u8 fec_mode_request_admin[0x18]; 10354 10355 u8 reserved_at_c0[0x80]; 10356 }; 10357 10358 struct mlx5_ifc_plib_reg_bits { 10359 u8 reserved_at_0[0x8]; 10360 u8 local_port[0x8]; 10361 u8 reserved_at_10[0x8]; 10362 u8 ib_port[0x8]; 10363 10364 u8 reserved_at_20[0x60]; 10365 }; 10366 10367 struct mlx5_ifc_plbf_reg_bits { 10368 u8 reserved_at_0[0x8]; 10369 u8 local_port[0x8]; 10370 u8 reserved_at_10[0xd]; 10371 u8 lbf_mode[0x3]; 10372 10373 u8 reserved_at_20[0x20]; 10374 }; 10375 10376 struct mlx5_ifc_pipg_reg_bits { 10377 u8 reserved_at_0[0x8]; 10378 u8 local_port[0x8]; 10379 u8 reserved_at_10[0x10]; 10380 10381 u8 dic[0x1]; 10382 u8 reserved_at_21[0x19]; 10383 u8 ipg[0x4]; 10384 u8 reserved_at_3e[0x2]; 10385 }; 10386 10387 struct mlx5_ifc_pifr_reg_bits { 10388 u8 reserved_at_0[0x8]; 10389 u8 local_port[0x8]; 10390 u8 reserved_at_10[0x10]; 10391 10392 u8 reserved_at_20[0xe0]; 10393 10394 u8 port_filter[8][0x20]; 10395 10396 u8 port_filter_update_en[8][0x20]; 10397 }; 10398 10399 struct mlx5_ifc_pfcc_reg_bits { 10400 u8 reserved_at_0[0x8]; 10401 u8 local_port[0x8]; 10402 u8 reserved_at_10[0xb]; 10403 u8 ppan_mask_n[0x1]; 10404 u8 minor_stall_mask[0x1]; 10405 u8 critical_stall_mask[0x1]; 10406 u8 reserved_at_1e[0x2]; 10407 10408 u8 ppan[0x4]; 10409 u8 reserved_at_24[0x4]; 10410 u8 prio_mask_tx[0x8]; 10411 u8 reserved_at_30[0x8]; 10412 u8 prio_mask_rx[0x8]; 10413 10414 u8 pptx[0x1]; 10415 u8 aptx[0x1]; 10416 u8 pptx_mask_n[0x1]; 10417 u8 reserved_at_43[0x5]; 10418 u8 pfctx[0x8]; 10419 u8 reserved_at_50[0x10]; 10420 10421 u8 pprx[0x1]; 10422 u8 aprx[0x1]; 10423 u8 pprx_mask_n[0x1]; 10424 u8 reserved_at_63[0x5]; 10425 u8 pfcrx[0x8]; 10426 u8 reserved_at_70[0x10]; 10427 10428 u8 device_stall_minor_watermark[0x10]; 10429 u8 device_stall_critical_watermark[0x10]; 10430 10431 u8 reserved_at_a0[0x60]; 10432 }; 10433 10434 struct mlx5_ifc_pelc_reg_bits { 10435 u8 op[0x4]; 10436 u8 reserved_at_4[0x4]; 10437 u8 local_port[0x8]; 10438 u8 reserved_at_10[0x10]; 10439 10440 u8 op_admin[0x8]; 10441 u8 op_capability[0x8]; 10442 u8 op_request[0x8]; 10443 u8 op_active[0x8]; 10444 10445 u8 admin[0x40]; 10446 10447 u8 capability[0x40]; 10448 10449 u8 request[0x40]; 10450 10451 u8 active[0x40]; 10452 10453 u8 reserved_at_140[0x80]; 10454 }; 10455 10456 struct mlx5_ifc_peir_reg_bits { 10457 u8 reserved_at_0[0x8]; 10458 u8 local_port[0x8]; 10459 u8 reserved_at_10[0x10]; 10460 10461 u8 reserved_at_20[0xc]; 10462 u8 error_count[0x4]; 10463 u8 reserved_at_30[0x10]; 10464 10465 u8 reserved_at_40[0xc]; 10466 u8 lane[0x4]; 10467 u8 reserved_at_50[0x8]; 10468 u8 error_type[0x8]; 10469 }; 10470 10471 struct mlx5_ifc_mpegc_reg_bits { 10472 u8 reserved_at_0[0x30]; 10473 u8 field_select[0x10]; 10474 10475 u8 tx_overflow_sense[0x1]; 10476 u8 mark_cqe[0x1]; 10477 u8 mark_cnp[0x1]; 10478 u8 reserved_at_43[0x1b]; 10479 u8 tx_lossy_overflow_oper[0x2]; 10480 10481 u8 reserved_at_60[0x100]; 10482 }; 10483 10484 struct mlx5_ifc_mpir_reg_bits { 10485 u8 sdm[0x1]; 10486 u8 reserved_at_1[0x1b]; 10487 u8 host_buses[0x4]; 10488 10489 u8 reserved_at_20[0x20]; 10490 10491 u8 local_port[0x8]; 10492 u8 reserved_at_28[0x18]; 10493 10494 u8 reserved_at_60[0x20]; 10495 }; 10496 10497 enum { 10498 MLX5_MTUTC_FREQ_ADJ_UNITS_PPB = 0x0, 10499 MLX5_MTUTC_FREQ_ADJ_UNITS_SCALED_PPM = 0x1, 10500 }; 10501 10502 enum { 10503 MLX5_MTUTC_OPERATION_SET_TIME_IMMEDIATE = 0x1, 10504 MLX5_MTUTC_OPERATION_ADJUST_TIME = 0x2, 10505 MLX5_MTUTC_OPERATION_ADJUST_FREQ_UTC = 0x3, 10506 }; 10507 10508 struct mlx5_ifc_mtutc_reg_bits { 10509 u8 reserved_at_0[0x5]; 10510 u8 freq_adj_units[0x3]; 10511 u8 reserved_at_8[0x3]; 10512 u8 log_max_freq_adjustment[0x5]; 10513 10514 u8 reserved_at_10[0xc]; 10515 u8 operation[0x4]; 10516 10517 u8 freq_adjustment[0x20]; 10518 10519 u8 reserved_at_40[0x40]; 10520 10521 u8 utc_sec[0x20]; 10522 10523 u8 reserved_at_a0[0x2]; 10524 u8 utc_nsec[0x1e]; 10525 10526 u8 time_adjustment[0x20]; 10527 }; 10528 10529 struct mlx5_ifc_pcam_enhanced_features_bits { 10530 u8 reserved_at_0[0x48]; 10531 u8 fec_100G_per_lane_in_pplm[0x1]; 10532 u8 reserved_at_49[0x1f]; 10533 u8 fec_50G_per_lane_in_pplm[0x1]; 10534 u8 reserved_at_69[0x4]; 10535 u8 rx_icrc_encapsulated_counter[0x1]; 10536 u8 reserved_at_6e[0x4]; 10537 u8 ptys_extended_ethernet[0x1]; 10538 u8 reserved_at_73[0x3]; 10539 u8 pfcc_mask[0x1]; 10540 u8 reserved_at_77[0x3]; 10541 u8 per_lane_error_counters[0x1]; 10542 u8 rx_buffer_fullness_counters[0x1]; 10543 u8 ptys_connector_type[0x1]; 10544 u8 reserved_at_7d[0x1]; 10545 u8 ppcnt_discard_group[0x1]; 10546 u8 ppcnt_statistical_group[0x1]; 10547 }; 10548 10549 struct mlx5_ifc_pcam_regs_5000_to_507f_bits { 10550 u8 port_access_reg_cap_mask_127_to_96[0x20]; 10551 u8 port_access_reg_cap_mask_95_to_64[0x20]; 10552 10553 u8 port_access_reg_cap_mask_63_to_36[0x1c]; 10554 u8 pplm[0x1]; 10555 u8 port_access_reg_cap_mask_34_to_32[0x3]; 10556 10557 u8 port_access_reg_cap_mask_31_to_13[0x13]; 10558 u8 pbmc[0x1]; 10559 u8 pptb[0x1]; 10560 u8 port_access_reg_cap_mask_10_to_09[0x2]; 10561 u8 ppcnt[0x1]; 10562 u8 port_access_reg_cap_mask_07_to_00[0x8]; 10563 }; 10564 10565 struct mlx5_ifc_pcam_reg_bits { 10566 u8 reserved_at_0[0x8]; 10567 u8 feature_group[0x8]; 10568 u8 reserved_at_10[0x8]; 10569 u8 access_reg_group[0x8]; 10570 10571 u8 reserved_at_20[0x20]; 10572 10573 union { 10574 struct mlx5_ifc_pcam_regs_5000_to_507f_bits regs_5000_to_507f; 10575 u8 reserved_at_0[0x80]; 10576 } port_access_reg_cap_mask; 10577 10578 u8 reserved_at_c0[0x80]; 10579 10580 union { 10581 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features; 10582 u8 reserved_at_0[0x80]; 10583 } feature_cap_mask; 10584 10585 u8 reserved_at_1c0[0xc0]; 10586 }; 10587 10588 struct mlx5_ifc_mcam_enhanced_features_bits { 10589 u8 reserved_at_0[0x50]; 10590 u8 mtutc_freq_adj_units[0x1]; 10591 u8 mtutc_time_adjustment_extended_range[0x1]; 10592 u8 reserved_at_52[0xb]; 10593 u8 mcia_32dwords[0x1]; 10594 u8 out_pulse_duration_ns[0x1]; 10595 u8 npps_period[0x1]; 10596 u8 reserved_at_60[0xa]; 10597 u8 reset_state[0x1]; 10598 u8 ptpcyc2realtime_modify[0x1]; 10599 u8 reserved_at_6c[0x2]; 10600 u8 pci_status_and_power[0x1]; 10601 u8 reserved_at_6f[0x5]; 10602 u8 mark_tx_action_cnp[0x1]; 10603 u8 mark_tx_action_cqe[0x1]; 10604 u8 dynamic_tx_overflow[0x1]; 10605 u8 reserved_at_77[0x4]; 10606 u8 pcie_outbound_stalled[0x1]; 10607 u8 tx_overflow_buffer_pkt[0x1]; 10608 u8 mtpps_enh_out_per_adj[0x1]; 10609 u8 mtpps_fs[0x1]; 10610 u8 pcie_performance_group[0x1]; 10611 }; 10612 10613 struct mlx5_ifc_mcam_access_reg_bits { 10614 u8 reserved_at_0[0x1c]; 10615 u8 mcda[0x1]; 10616 u8 mcc[0x1]; 10617 u8 mcqi[0x1]; 10618 u8 mcqs[0x1]; 10619 10620 u8 regs_95_to_90[0x6]; 10621 u8 mpir[0x1]; 10622 u8 regs_88_to_87[0x2]; 10623 u8 mpegc[0x1]; 10624 u8 mtutc[0x1]; 10625 u8 regs_84_to_68[0x11]; 10626 u8 tracer_registers[0x4]; 10627 10628 u8 regs_63_to_46[0x12]; 10629 u8 mrtc[0x1]; 10630 u8 regs_44_to_41[0x4]; 10631 u8 mfrl[0x1]; 10632 u8 regs_39_to_32[0x8]; 10633 10634 u8 regs_31_to_11[0x15]; 10635 u8 mtmp[0x1]; 10636 u8 regs_9_to_0[0xa]; 10637 }; 10638 10639 struct mlx5_ifc_mcam_access_reg_bits1 { 10640 u8 regs_127_to_96[0x20]; 10641 10642 u8 regs_95_to_64[0x20]; 10643 10644 u8 regs_63_to_32[0x20]; 10645 10646 u8 regs_31_to_0[0x20]; 10647 }; 10648 10649 struct mlx5_ifc_mcam_access_reg_bits2 { 10650 u8 regs_127_to_99[0x1d]; 10651 u8 mirc[0x1]; 10652 u8 regs_97_to_96[0x2]; 10653 10654 u8 regs_95_to_87[0x09]; 10655 u8 synce_registers[0x2]; 10656 u8 regs_84_to_64[0x15]; 10657 10658 u8 regs_63_to_32[0x20]; 10659 10660 u8 regs_31_to_0[0x20]; 10661 }; 10662 10663 struct mlx5_ifc_mcam_access_reg_bits3 { 10664 u8 regs_127_to_96[0x20]; 10665 10666 u8 regs_95_to_64[0x20]; 10667 10668 u8 regs_63_to_32[0x20]; 10669 10670 u8 regs_31_to_2[0x1e]; 10671 u8 mtctr[0x1]; 10672 u8 mtptm[0x1]; 10673 }; 10674 10675 struct mlx5_ifc_mcam_reg_bits { 10676 u8 reserved_at_0[0x8]; 10677 u8 feature_group[0x8]; 10678 u8 reserved_at_10[0x8]; 10679 u8 access_reg_group[0x8]; 10680 10681 u8 reserved_at_20[0x20]; 10682 10683 union { 10684 struct mlx5_ifc_mcam_access_reg_bits access_regs; 10685 struct mlx5_ifc_mcam_access_reg_bits1 access_regs1; 10686 struct mlx5_ifc_mcam_access_reg_bits2 access_regs2; 10687 struct mlx5_ifc_mcam_access_reg_bits3 access_regs3; 10688 u8 reserved_at_0[0x80]; 10689 } mng_access_reg_cap_mask; 10690 10691 u8 reserved_at_c0[0x80]; 10692 10693 union { 10694 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features; 10695 u8 reserved_at_0[0x80]; 10696 } mng_feature_cap_mask; 10697 10698 u8 reserved_at_1c0[0x80]; 10699 }; 10700 10701 struct mlx5_ifc_qcam_access_reg_cap_mask { 10702 u8 qcam_access_reg_cap_mask_127_to_20[0x6C]; 10703 u8 qpdpm[0x1]; 10704 u8 qcam_access_reg_cap_mask_18_to_4[0x0F]; 10705 u8 qdpm[0x1]; 10706 u8 qpts[0x1]; 10707 u8 qcap[0x1]; 10708 u8 qcam_access_reg_cap_mask_0[0x1]; 10709 }; 10710 10711 struct mlx5_ifc_qcam_qos_feature_cap_mask { 10712 u8 qcam_qos_feature_cap_mask_127_to_1[0x7F]; 10713 u8 qpts_trust_both[0x1]; 10714 }; 10715 10716 struct mlx5_ifc_qcam_reg_bits { 10717 u8 reserved_at_0[0x8]; 10718 u8 feature_group[0x8]; 10719 u8 reserved_at_10[0x8]; 10720 u8 access_reg_group[0x8]; 10721 u8 reserved_at_20[0x20]; 10722 10723 union { 10724 struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap; 10725 u8 reserved_at_0[0x80]; 10726 } qos_access_reg_cap_mask; 10727 10728 u8 reserved_at_c0[0x80]; 10729 10730 union { 10731 struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap; 10732 u8 reserved_at_0[0x80]; 10733 } qos_feature_cap_mask; 10734 10735 u8 reserved_at_1c0[0x80]; 10736 }; 10737 10738 struct mlx5_ifc_core_dump_reg_bits { 10739 u8 reserved_at_0[0x18]; 10740 u8 core_dump_type[0x8]; 10741 10742 u8 reserved_at_20[0x30]; 10743 u8 vhca_id[0x10]; 10744 10745 u8 reserved_at_60[0x8]; 10746 u8 qpn[0x18]; 10747 u8 reserved_at_80[0x180]; 10748 }; 10749 10750 struct mlx5_ifc_pcap_reg_bits { 10751 u8 reserved_at_0[0x8]; 10752 u8 local_port[0x8]; 10753 u8 reserved_at_10[0x10]; 10754 10755 u8 port_capability_mask[4][0x20]; 10756 }; 10757 10758 struct mlx5_ifc_paos_reg_bits { 10759 u8 swid[0x8]; 10760 u8 local_port[0x8]; 10761 u8 reserved_at_10[0x4]; 10762 u8 admin_status[0x4]; 10763 u8 reserved_at_18[0x4]; 10764 u8 oper_status[0x4]; 10765 10766 u8 ase[0x1]; 10767 u8 ee[0x1]; 10768 u8 reserved_at_22[0x1c]; 10769 u8 e[0x2]; 10770 10771 u8 reserved_at_40[0x40]; 10772 }; 10773 10774 struct mlx5_ifc_pamp_reg_bits { 10775 u8 reserved_at_0[0x8]; 10776 u8 opamp_group[0x8]; 10777 u8 reserved_at_10[0xc]; 10778 u8 opamp_group_type[0x4]; 10779 10780 u8 start_index[0x10]; 10781 u8 reserved_at_30[0x4]; 10782 u8 num_of_indices[0xc]; 10783 10784 u8 index_data[18][0x10]; 10785 }; 10786 10787 struct mlx5_ifc_pcmr_reg_bits { 10788 u8 reserved_at_0[0x8]; 10789 u8 local_port[0x8]; 10790 u8 reserved_at_10[0x10]; 10791 10792 u8 entropy_force_cap[0x1]; 10793 u8 entropy_calc_cap[0x1]; 10794 u8 entropy_gre_calc_cap[0x1]; 10795 u8 reserved_at_23[0xf]; 10796 u8 rx_ts_over_crc_cap[0x1]; 10797 u8 reserved_at_33[0xb]; 10798 u8 fcs_cap[0x1]; 10799 u8 reserved_at_3f[0x1]; 10800 10801 u8 entropy_force[0x1]; 10802 u8 entropy_calc[0x1]; 10803 u8 entropy_gre_calc[0x1]; 10804 u8 reserved_at_43[0xf]; 10805 u8 rx_ts_over_crc[0x1]; 10806 u8 reserved_at_53[0xb]; 10807 u8 fcs_chk[0x1]; 10808 u8 reserved_at_5f[0x1]; 10809 }; 10810 10811 struct mlx5_ifc_lane_2_module_mapping_bits { 10812 u8 reserved_at_0[0x4]; 10813 u8 rx_lane[0x4]; 10814 u8 reserved_at_8[0x4]; 10815 u8 tx_lane[0x4]; 10816 u8 reserved_at_10[0x8]; 10817 u8 module[0x8]; 10818 }; 10819 10820 struct mlx5_ifc_bufferx_reg_bits { 10821 u8 reserved_at_0[0x6]; 10822 u8 lossy[0x1]; 10823 u8 epsb[0x1]; 10824 u8 reserved_at_8[0x8]; 10825 u8 size[0x10]; 10826 10827 u8 xoff_threshold[0x10]; 10828 u8 xon_threshold[0x10]; 10829 }; 10830 10831 struct mlx5_ifc_set_node_in_bits { 10832 u8 node_description[64][0x8]; 10833 }; 10834 10835 struct mlx5_ifc_register_power_settings_bits { 10836 u8 reserved_at_0[0x18]; 10837 u8 power_settings_level[0x8]; 10838 10839 u8 reserved_at_20[0x60]; 10840 }; 10841 10842 struct mlx5_ifc_register_host_endianness_bits { 10843 u8 he[0x1]; 10844 u8 reserved_at_1[0x1f]; 10845 10846 u8 reserved_at_20[0x60]; 10847 }; 10848 10849 struct mlx5_ifc_umr_pointer_desc_argument_bits { 10850 u8 reserved_at_0[0x20]; 10851 10852 u8 mkey[0x20]; 10853 10854 u8 addressh_63_32[0x20]; 10855 10856 u8 addressl_31_0[0x20]; 10857 }; 10858 10859 struct mlx5_ifc_ud_adrs_vector_bits { 10860 u8 dc_key[0x40]; 10861 10862 u8 ext[0x1]; 10863 u8 reserved_at_41[0x7]; 10864 u8 destination_qp_dct[0x18]; 10865 10866 u8 static_rate[0x4]; 10867 u8 sl_eth_prio[0x4]; 10868 u8 fl[0x1]; 10869 u8 mlid[0x7]; 10870 u8 rlid_udp_sport[0x10]; 10871 10872 u8 reserved_at_80[0x20]; 10873 10874 u8 rmac_47_16[0x20]; 10875 10876 u8 rmac_15_0[0x10]; 10877 u8 tclass[0x8]; 10878 u8 hop_limit[0x8]; 10879 10880 u8 reserved_at_e0[0x1]; 10881 u8 grh[0x1]; 10882 u8 reserved_at_e2[0x2]; 10883 u8 src_addr_index[0x8]; 10884 u8 flow_label[0x14]; 10885 10886 u8 rgid_rip[16][0x8]; 10887 }; 10888 10889 struct mlx5_ifc_pages_req_event_bits { 10890 u8 reserved_at_0[0x10]; 10891 u8 function_id[0x10]; 10892 10893 u8 num_pages[0x20]; 10894 10895 u8 reserved_at_40[0xa0]; 10896 }; 10897 10898 struct mlx5_ifc_eqe_bits { 10899 u8 reserved_at_0[0x8]; 10900 u8 event_type[0x8]; 10901 u8 reserved_at_10[0x8]; 10902 u8 event_sub_type[0x8]; 10903 10904 u8 reserved_at_20[0xe0]; 10905 10906 union mlx5_ifc_event_auto_bits event_data; 10907 10908 u8 reserved_at_1e0[0x10]; 10909 u8 signature[0x8]; 10910 u8 reserved_at_1f8[0x7]; 10911 u8 owner[0x1]; 10912 }; 10913 10914 enum { 10915 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7, 10916 }; 10917 10918 struct mlx5_ifc_cmd_queue_entry_bits { 10919 u8 type[0x8]; 10920 u8 reserved_at_8[0x18]; 10921 10922 u8 input_length[0x20]; 10923 10924 u8 input_mailbox_pointer_63_32[0x20]; 10925 10926 u8 input_mailbox_pointer_31_9[0x17]; 10927 u8 reserved_at_77[0x9]; 10928 10929 u8 command_input_inline_data[16][0x8]; 10930 10931 u8 command_output_inline_data[16][0x8]; 10932 10933 u8 output_mailbox_pointer_63_32[0x20]; 10934 10935 u8 output_mailbox_pointer_31_9[0x17]; 10936 u8 reserved_at_1b7[0x9]; 10937 10938 u8 output_length[0x20]; 10939 10940 u8 token[0x8]; 10941 u8 signature[0x8]; 10942 u8 reserved_at_1f0[0x8]; 10943 u8 status[0x7]; 10944 u8 ownership[0x1]; 10945 }; 10946 10947 struct mlx5_ifc_cmd_out_bits { 10948 u8 status[0x8]; 10949 u8 reserved_at_8[0x18]; 10950 10951 u8 syndrome[0x20]; 10952 10953 u8 command_output[0x20]; 10954 }; 10955 10956 struct mlx5_ifc_cmd_in_bits { 10957 u8 opcode[0x10]; 10958 u8 reserved_at_10[0x10]; 10959 10960 u8 reserved_at_20[0x10]; 10961 u8 op_mod[0x10]; 10962 10963 u8 command[][0x20]; 10964 }; 10965 10966 struct mlx5_ifc_cmd_if_box_bits { 10967 u8 mailbox_data[512][0x8]; 10968 10969 u8 reserved_at_1000[0x180]; 10970 10971 u8 next_pointer_63_32[0x20]; 10972 10973 u8 next_pointer_31_10[0x16]; 10974 u8 reserved_at_11b6[0xa]; 10975 10976 u8 block_number[0x20]; 10977 10978 u8 reserved_at_11e0[0x8]; 10979 u8 token[0x8]; 10980 u8 ctrl_signature[0x8]; 10981 u8 signature[0x8]; 10982 }; 10983 10984 struct mlx5_ifc_mtt_bits { 10985 u8 ptag_63_32[0x20]; 10986 10987 u8 ptag_31_8[0x18]; 10988 u8 reserved_at_38[0x6]; 10989 u8 wr_en[0x1]; 10990 u8 rd_en[0x1]; 10991 }; 10992 10993 struct mlx5_ifc_query_wol_rol_out_bits { 10994 u8 status[0x8]; 10995 u8 reserved_at_8[0x18]; 10996 10997 u8 syndrome[0x20]; 10998 10999 u8 reserved_at_40[0x10]; 11000 u8 rol_mode[0x8]; 11001 u8 wol_mode[0x8]; 11002 11003 u8 reserved_at_60[0x20]; 11004 }; 11005 11006 struct mlx5_ifc_query_wol_rol_in_bits { 11007 u8 opcode[0x10]; 11008 u8 reserved_at_10[0x10]; 11009 11010 u8 reserved_at_20[0x10]; 11011 u8 op_mod[0x10]; 11012 11013 u8 reserved_at_40[0x40]; 11014 }; 11015 11016 struct mlx5_ifc_set_wol_rol_out_bits { 11017 u8 status[0x8]; 11018 u8 reserved_at_8[0x18]; 11019 11020 u8 syndrome[0x20]; 11021 11022 u8 reserved_at_40[0x40]; 11023 }; 11024 11025 struct mlx5_ifc_set_wol_rol_in_bits { 11026 u8 opcode[0x10]; 11027 u8 reserved_at_10[0x10]; 11028 11029 u8 reserved_at_20[0x10]; 11030 u8 op_mod[0x10]; 11031 11032 u8 rol_mode_valid[0x1]; 11033 u8 wol_mode_valid[0x1]; 11034 u8 reserved_at_42[0xe]; 11035 u8 rol_mode[0x8]; 11036 u8 wol_mode[0x8]; 11037 11038 u8 reserved_at_60[0x20]; 11039 }; 11040 11041 enum { 11042 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0, 11043 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1, 11044 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2, 11045 MLX5_INITIAL_SEG_NIC_INTERFACE_SW_RESET = 0x7, 11046 }; 11047 11048 enum { 11049 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0, 11050 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1, 11051 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2, 11052 }; 11053 11054 enum { 11055 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR = 0x1, 11056 MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC = 0x7, 11057 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR = 0x8, 11058 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR = 0x9, 11059 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR = 0xa, 11060 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR = 0xb, 11061 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN = 0xc, 11062 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR = 0xd, 11063 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV = 0xe, 11064 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR = 0xf, 11065 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR = 0x10, 11066 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PCI_POISONED_ERR = 0x12, 11067 }; 11068 11069 struct mlx5_ifc_initial_seg_bits { 11070 u8 fw_rev_minor[0x10]; 11071 u8 fw_rev_major[0x10]; 11072 11073 u8 cmd_interface_rev[0x10]; 11074 u8 fw_rev_subminor[0x10]; 11075 11076 u8 reserved_at_40[0x40]; 11077 11078 u8 cmdq_phy_addr_63_32[0x20]; 11079 11080 u8 cmdq_phy_addr_31_12[0x14]; 11081 u8 reserved_at_b4[0x2]; 11082 u8 nic_interface[0x2]; 11083 u8 log_cmdq_size[0x4]; 11084 u8 log_cmdq_stride[0x4]; 11085 11086 u8 command_doorbell_vector[0x20]; 11087 11088 u8 reserved_at_e0[0xf00]; 11089 11090 u8 initializing[0x1]; 11091 u8 reserved_at_fe1[0x4]; 11092 u8 nic_interface_supported[0x3]; 11093 u8 embedded_cpu[0x1]; 11094 u8 reserved_at_fe9[0x17]; 11095 11096 struct mlx5_ifc_health_buffer_bits health_buffer; 11097 11098 u8 no_dram_nic_offset[0x20]; 11099 11100 u8 reserved_at_1220[0x6e40]; 11101 11102 u8 reserved_at_8060[0x1f]; 11103 u8 clear_int[0x1]; 11104 11105 u8 health_syndrome[0x8]; 11106 u8 health_counter[0x18]; 11107 11108 u8 reserved_at_80a0[0x17fc0]; 11109 }; 11110 11111 struct mlx5_ifc_mtpps_reg_bits { 11112 u8 reserved_at_0[0xc]; 11113 u8 cap_number_of_pps_pins[0x4]; 11114 u8 reserved_at_10[0x4]; 11115 u8 cap_max_num_of_pps_in_pins[0x4]; 11116 u8 reserved_at_18[0x4]; 11117 u8 cap_max_num_of_pps_out_pins[0x4]; 11118 11119 u8 reserved_at_20[0x13]; 11120 u8 cap_log_min_npps_period[0x5]; 11121 u8 reserved_at_38[0x3]; 11122 u8 cap_log_min_out_pulse_duration_ns[0x5]; 11123 11124 u8 reserved_at_40[0x4]; 11125 u8 cap_pin_3_mode[0x4]; 11126 u8 reserved_at_48[0x4]; 11127 u8 cap_pin_2_mode[0x4]; 11128 u8 reserved_at_50[0x4]; 11129 u8 cap_pin_1_mode[0x4]; 11130 u8 reserved_at_58[0x4]; 11131 u8 cap_pin_0_mode[0x4]; 11132 11133 u8 reserved_at_60[0x4]; 11134 u8 cap_pin_7_mode[0x4]; 11135 u8 reserved_at_68[0x4]; 11136 u8 cap_pin_6_mode[0x4]; 11137 u8 reserved_at_70[0x4]; 11138 u8 cap_pin_5_mode[0x4]; 11139 u8 reserved_at_78[0x4]; 11140 u8 cap_pin_4_mode[0x4]; 11141 11142 u8 field_select[0x20]; 11143 u8 reserved_at_a0[0x20]; 11144 11145 u8 npps_period[0x40]; 11146 11147 u8 enable[0x1]; 11148 u8 reserved_at_101[0xb]; 11149 u8 pattern[0x4]; 11150 u8 reserved_at_110[0x4]; 11151 u8 pin_mode[0x4]; 11152 u8 pin[0x8]; 11153 11154 u8 reserved_at_120[0x2]; 11155 u8 out_pulse_duration_ns[0x1e]; 11156 11157 u8 time_stamp[0x40]; 11158 11159 u8 out_pulse_duration[0x10]; 11160 u8 out_periodic_adjustment[0x10]; 11161 u8 enhanced_out_periodic_adjustment[0x20]; 11162 11163 u8 reserved_at_1c0[0x20]; 11164 }; 11165 11166 struct mlx5_ifc_mtppse_reg_bits { 11167 u8 reserved_at_0[0x18]; 11168 u8 pin[0x8]; 11169 u8 event_arm[0x1]; 11170 u8 reserved_at_21[0x1b]; 11171 u8 event_generation_mode[0x4]; 11172 u8 reserved_at_40[0x40]; 11173 }; 11174 11175 struct mlx5_ifc_mcqs_reg_bits { 11176 u8 last_index_flag[0x1]; 11177 u8 reserved_at_1[0x7]; 11178 u8 fw_device[0x8]; 11179 u8 component_index[0x10]; 11180 11181 u8 reserved_at_20[0x10]; 11182 u8 identifier[0x10]; 11183 11184 u8 reserved_at_40[0x17]; 11185 u8 component_status[0x5]; 11186 u8 component_update_state[0x4]; 11187 11188 u8 last_update_state_changer_type[0x4]; 11189 u8 last_update_state_changer_host_id[0x4]; 11190 u8 reserved_at_68[0x18]; 11191 }; 11192 11193 struct mlx5_ifc_mcqi_cap_bits { 11194 u8 supported_info_bitmask[0x20]; 11195 11196 u8 component_size[0x20]; 11197 11198 u8 max_component_size[0x20]; 11199 11200 u8 log_mcda_word_size[0x4]; 11201 u8 reserved_at_64[0xc]; 11202 u8 mcda_max_write_size[0x10]; 11203 11204 u8 rd_en[0x1]; 11205 u8 reserved_at_81[0x1]; 11206 u8 match_chip_id[0x1]; 11207 u8 match_psid[0x1]; 11208 u8 check_user_timestamp[0x1]; 11209 u8 match_base_guid_mac[0x1]; 11210 u8 reserved_at_86[0x1a]; 11211 }; 11212 11213 struct mlx5_ifc_mcqi_version_bits { 11214 u8 reserved_at_0[0x2]; 11215 u8 build_time_valid[0x1]; 11216 u8 user_defined_time_valid[0x1]; 11217 u8 reserved_at_4[0x14]; 11218 u8 version_string_length[0x8]; 11219 11220 u8 version[0x20]; 11221 11222 u8 build_time[0x40]; 11223 11224 u8 user_defined_time[0x40]; 11225 11226 u8 build_tool_version[0x20]; 11227 11228 u8 reserved_at_e0[0x20]; 11229 11230 u8 version_string[92][0x8]; 11231 }; 11232 11233 struct mlx5_ifc_mcqi_activation_method_bits { 11234 u8 pending_server_ac_power_cycle[0x1]; 11235 u8 pending_server_dc_power_cycle[0x1]; 11236 u8 pending_server_reboot[0x1]; 11237 u8 pending_fw_reset[0x1]; 11238 u8 auto_activate[0x1]; 11239 u8 all_hosts_sync[0x1]; 11240 u8 device_hw_reset[0x1]; 11241 u8 reserved_at_7[0x19]; 11242 }; 11243 11244 union mlx5_ifc_mcqi_reg_data_bits { 11245 struct mlx5_ifc_mcqi_cap_bits mcqi_caps; 11246 struct mlx5_ifc_mcqi_version_bits mcqi_version; 11247 struct mlx5_ifc_mcqi_activation_method_bits mcqi_activation_mathod; 11248 }; 11249 11250 struct mlx5_ifc_mcqi_reg_bits { 11251 u8 read_pending_component[0x1]; 11252 u8 reserved_at_1[0xf]; 11253 u8 component_index[0x10]; 11254 11255 u8 reserved_at_20[0x20]; 11256 11257 u8 reserved_at_40[0x1b]; 11258 u8 info_type[0x5]; 11259 11260 u8 info_size[0x20]; 11261 11262 u8 offset[0x20]; 11263 11264 u8 reserved_at_a0[0x10]; 11265 u8 data_size[0x10]; 11266 11267 union mlx5_ifc_mcqi_reg_data_bits data[]; 11268 }; 11269 11270 struct mlx5_ifc_mcc_reg_bits { 11271 u8 reserved_at_0[0x4]; 11272 u8 time_elapsed_since_last_cmd[0xc]; 11273 u8 reserved_at_10[0x8]; 11274 u8 instruction[0x8]; 11275 11276 u8 reserved_at_20[0x10]; 11277 u8 component_index[0x10]; 11278 11279 u8 reserved_at_40[0x8]; 11280 u8 update_handle[0x18]; 11281 11282 u8 handle_owner_type[0x4]; 11283 u8 handle_owner_host_id[0x4]; 11284 u8 reserved_at_68[0x1]; 11285 u8 control_progress[0x7]; 11286 u8 error_code[0x8]; 11287 u8 reserved_at_78[0x4]; 11288 u8 control_state[0x4]; 11289 11290 u8 component_size[0x20]; 11291 11292 u8 reserved_at_a0[0x60]; 11293 }; 11294 11295 struct mlx5_ifc_mcda_reg_bits { 11296 u8 reserved_at_0[0x8]; 11297 u8 update_handle[0x18]; 11298 11299 u8 offset[0x20]; 11300 11301 u8 reserved_at_40[0x10]; 11302 u8 size[0x10]; 11303 11304 u8 reserved_at_60[0x20]; 11305 11306 u8 data[][0x20]; 11307 }; 11308 11309 enum { 11310 MLX5_MFRL_REG_PCI_RESET_METHOD_LINK_TOGGLE = 0, 11311 MLX5_MFRL_REG_PCI_RESET_METHOD_HOT_RESET = 1, 11312 }; 11313 11314 enum { 11315 MLX5_MFRL_REG_RESET_STATE_IDLE = 0, 11316 MLX5_MFRL_REG_RESET_STATE_IN_NEGOTIATION = 1, 11317 MLX5_MFRL_REG_RESET_STATE_RESET_IN_PROGRESS = 2, 11318 MLX5_MFRL_REG_RESET_STATE_NEG_TIMEOUT = 3, 11319 MLX5_MFRL_REG_RESET_STATE_NACK = 4, 11320 MLX5_MFRL_REG_RESET_STATE_UNLOAD_TIMEOUT = 5, 11321 }; 11322 11323 enum { 11324 MLX5_MFRL_REG_RESET_TYPE_FULL_CHIP = BIT(0), 11325 MLX5_MFRL_REG_RESET_TYPE_NET_PORT_ALIVE = BIT(1), 11326 }; 11327 11328 enum { 11329 MLX5_MFRL_REG_RESET_LEVEL0 = BIT(0), 11330 MLX5_MFRL_REG_RESET_LEVEL3 = BIT(3), 11331 MLX5_MFRL_REG_RESET_LEVEL6 = BIT(6), 11332 }; 11333 11334 struct mlx5_ifc_mfrl_reg_bits { 11335 u8 reserved_at_0[0x20]; 11336 11337 u8 reserved_at_20[0x2]; 11338 u8 pci_sync_for_fw_update_start[0x1]; 11339 u8 pci_sync_for_fw_update_resp[0x2]; 11340 u8 rst_type_sel[0x3]; 11341 u8 pci_reset_req_method[0x3]; 11342 u8 reserved_at_2b[0x1]; 11343 u8 reset_state[0x4]; 11344 u8 reset_type[0x8]; 11345 u8 reset_level[0x8]; 11346 }; 11347 11348 struct mlx5_ifc_mirc_reg_bits { 11349 u8 reserved_at_0[0x18]; 11350 u8 status_code[0x8]; 11351 11352 u8 reserved_at_20[0x20]; 11353 }; 11354 11355 struct mlx5_ifc_pddr_monitor_opcode_bits { 11356 u8 reserved_at_0[0x10]; 11357 u8 monitor_opcode[0x10]; 11358 }; 11359 11360 union mlx5_ifc_pddr_troubleshooting_page_status_opcode_auto_bits { 11361 struct mlx5_ifc_pddr_monitor_opcode_bits pddr_monitor_opcode; 11362 u8 reserved_at_0[0x20]; 11363 }; 11364 11365 enum { 11366 /* Monitor opcodes */ 11367 MLX5_PDDR_REG_TRBLSH_GROUP_OPCODE_MONITOR = 0x0, 11368 }; 11369 11370 struct mlx5_ifc_pddr_troubleshooting_page_bits { 11371 u8 reserved_at_0[0x10]; 11372 u8 group_opcode[0x10]; 11373 11374 union mlx5_ifc_pddr_troubleshooting_page_status_opcode_auto_bits status_opcode; 11375 11376 u8 reserved_at_40[0x20]; 11377 11378 u8 status_message[59][0x20]; 11379 }; 11380 11381 union mlx5_ifc_pddr_reg_page_data_auto_bits { 11382 struct mlx5_ifc_pddr_troubleshooting_page_bits pddr_troubleshooting_page; 11383 u8 reserved_at_0[0x7c0]; 11384 }; 11385 11386 enum { 11387 MLX5_PDDR_REG_PAGE_SELECT_TROUBLESHOOTING_INFO_PAGE = 0x1, 11388 }; 11389 11390 struct mlx5_ifc_pddr_reg_bits { 11391 u8 reserved_at_0[0x8]; 11392 u8 local_port[0x8]; 11393 u8 pnat[0x2]; 11394 u8 reserved_at_12[0xe]; 11395 11396 u8 reserved_at_20[0x18]; 11397 u8 page_select[0x8]; 11398 11399 union mlx5_ifc_pddr_reg_page_data_auto_bits page_data; 11400 }; 11401 11402 struct mlx5_ifc_mrtc_reg_bits { 11403 u8 time_synced[0x1]; 11404 u8 reserved_at_1[0x1f]; 11405 11406 u8 reserved_at_20[0x20]; 11407 11408 u8 time_h[0x20]; 11409 11410 u8 time_l[0x20]; 11411 }; 11412 11413 struct mlx5_ifc_mtcap_reg_bits { 11414 u8 reserved_at_0[0x19]; 11415 u8 sensor_count[0x7]; 11416 11417 u8 reserved_at_20[0x20]; 11418 11419 u8 sensor_map[0x40]; 11420 }; 11421 11422 struct mlx5_ifc_mtmp_reg_bits { 11423 u8 reserved_at_0[0x14]; 11424 u8 sensor_index[0xc]; 11425 11426 u8 reserved_at_20[0x10]; 11427 u8 temperature[0x10]; 11428 11429 u8 mte[0x1]; 11430 u8 mtr[0x1]; 11431 u8 reserved_at_42[0xe]; 11432 u8 max_temperature[0x10]; 11433 11434 u8 tee[0x2]; 11435 u8 reserved_at_62[0xe]; 11436 u8 temp_threshold_hi[0x10]; 11437 11438 u8 reserved_at_80[0x10]; 11439 u8 temp_threshold_lo[0x10]; 11440 11441 u8 reserved_at_a0[0x20]; 11442 11443 u8 sensor_name_hi[0x20]; 11444 u8 sensor_name_lo[0x20]; 11445 }; 11446 11447 struct mlx5_ifc_mtptm_reg_bits { 11448 u8 reserved_at_0[0x10]; 11449 u8 psta[0x1]; 11450 u8 reserved_at_11[0xf]; 11451 11452 u8 reserved_at_20[0x60]; 11453 }; 11454 11455 enum { 11456 MLX5_MTCTR_REQUEST_NOP = 0x0, 11457 MLX5_MTCTR_REQUEST_PTM_ROOT_CLOCK = 0x1, 11458 MLX5_MTCTR_REQUEST_FREE_RUNNING_COUNTER = 0x2, 11459 MLX5_MTCTR_REQUEST_REAL_TIME_CLOCK = 0x3, 11460 }; 11461 11462 struct mlx5_ifc_mtctr_reg_bits { 11463 u8 first_clock_timestamp_request[0x8]; 11464 u8 second_clock_timestamp_request[0x8]; 11465 u8 reserved_at_10[0x10]; 11466 11467 u8 first_clock_valid[0x1]; 11468 u8 second_clock_valid[0x1]; 11469 u8 reserved_at_22[0x1e]; 11470 11471 u8 first_clock_timestamp[0x40]; 11472 u8 second_clock_timestamp[0x40]; 11473 }; 11474 11475 union mlx5_ifc_ports_control_registers_document_bits { 11476 struct mlx5_ifc_bufferx_reg_bits bufferx_reg; 11477 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 11478 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 11479 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 11480 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 11481 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 11482 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 11483 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout; 11484 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout; 11485 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping; 11486 struct mlx5_ifc_pamp_reg_bits pamp_reg; 11487 struct mlx5_ifc_paos_reg_bits paos_reg; 11488 struct mlx5_ifc_pcap_reg_bits pcap_reg; 11489 struct mlx5_ifc_pddr_monitor_opcode_bits pddr_monitor_opcode; 11490 struct mlx5_ifc_pddr_reg_bits pddr_reg; 11491 struct mlx5_ifc_pddr_troubleshooting_page_bits pddr_troubleshooting_page; 11492 struct mlx5_ifc_peir_reg_bits peir_reg; 11493 struct mlx5_ifc_pelc_reg_bits pelc_reg; 11494 struct mlx5_ifc_pfcc_reg_bits pfcc_reg; 11495 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 11496 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 11497 struct mlx5_ifc_pifr_reg_bits pifr_reg; 11498 struct mlx5_ifc_pipg_reg_bits pipg_reg; 11499 struct mlx5_ifc_plbf_reg_bits plbf_reg; 11500 struct mlx5_ifc_plib_reg_bits plib_reg; 11501 struct mlx5_ifc_plpc_reg_bits plpc_reg; 11502 struct mlx5_ifc_pmaos_reg_bits pmaos_reg; 11503 struct mlx5_ifc_pmlp_reg_bits pmlp_reg; 11504 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg; 11505 struct mlx5_ifc_pmpc_reg_bits pmpc_reg; 11506 struct mlx5_ifc_pmpe_reg_bits pmpe_reg; 11507 struct mlx5_ifc_pmpr_reg_bits pmpr_reg; 11508 struct mlx5_ifc_pmtu_reg_bits pmtu_reg; 11509 struct mlx5_ifc_ppad_reg_bits ppad_reg; 11510 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg; 11511 struct mlx5_ifc_mpein_reg_bits mpein_reg; 11512 struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg; 11513 struct mlx5_ifc_pplm_reg_bits pplm_reg; 11514 struct mlx5_ifc_pplr_reg_bits pplr_reg; 11515 struct mlx5_ifc_ppsc_reg_bits ppsc_reg; 11516 struct mlx5_ifc_pqdr_reg_bits pqdr_reg; 11517 struct mlx5_ifc_pspa_reg_bits pspa_reg; 11518 struct mlx5_ifc_ptas_reg_bits ptas_reg; 11519 struct mlx5_ifc_ptys_reg_bits ptys_reg; 11520 struct mlx5_ifc_mlcr_reg_bits mlcr_reg; 11521 struct mlx5_ifc_pude_reg_bits pude_reg; 11522 struct mlx5_ifc_pvlc_reg_bits pvlc_reg; 11523 struct mlx5_ifc_slrg_reg_bits slrg_reg; 11524 struct mlx5_ifc_sltp_reg_bits sltp_reg; 11525 struct mlx5_ifc_mtpps_reg_bits mtpps_reg; 11526 struct mlx5_ifc_mtppse_reg_bits mtppse_reg; 11527 struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg; 11528 struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits; 11529 struct mlx5_ifc_fpga_cap_bits fpga_cap_bits; 11530 struct mlx5_ifc_mcqi_reg_bits mcqi_reg; 11531 struct mlx5_ifc_mcc_reg_bits mcc_reg; 11532 struct mlx5_ifc_mcda_reg_bits mcda_reg; 11533 struct mlx5_ifc_mirc_reg_bits mirc_reg; 11534 struct mlx5_ifc_mfrl_reg_bits mfrl_reg; 11535 struct mlx5_ifc_mtutc_reg_bits mtutc_reg; 11536 struct mlx5_ifc_mrtc_reg_bits mrtc_reg; 11537 struct mlx5_ifc_mtcap_reg_bits mtcap_reg; 11538 struct mlx5_ifc_mtmp_reg_bits mtmp_reg; 11539 struct mlx5_ifc_mtptm_reg_bits mtptm_reg; 11540 struct mlx5_ifc_mtctr_reg_bits mtctr_reg; 11541 u8 reserved_at_0[0x60e0]; 11542 }; 11543 11544 union mlx5_ifc_debug_enhancements_document_bits { 11545 struct mlx5_ifc_health_buffer_bits health_buffer; 11546 u8 reserved_at_0[0x200]; 11547 }; 11548 11549 union mlx5_ifc_uplink_pci_interface_document_bits { 11550 struct mlx5_ifc_initial_seg_bits initial_seg; 11551 u8 reserved_at_0[0x20060]; 11552 }; 11553 11554 struct mlx5_ifc_set_flow_table_root_out_bits { 11555 u8 status[0x8]; 11556 u8 reserved_at_8[0x18]; 11557 11558 u8 syndrome[0x20]; 11559 11560 u8 reserved_at_40[0x40]; 11561 }; 11562 11563 struct mlx5_ifc_set_flow_table_root_in_bits { 11564 u8 opcode[0x10]; 11565 u8 reserved_at_10[0x10]; 11566 11567 u8 reserved_at_20[0x10]; 11568 u8 op_mod[0x10]; 11569 11570 u8 other_vport[0x1]; 11571 u8 reserved_at_41[0xf]; 11572 u8 vport_number[0x10]; 11573 11574 u8 reserved_at_60[0x20]; 11575 11576 u8 table_type[0x8]; 11577 u8 reserved_at_88[0x7]; 11578 u8 table_of_other_vport[0x1]; 11579 u8 table_vport_number[0x10]; 11580 11581 u8 reserved_at_a0[0x8]; 11582 u8 table_id[0x18]; 11583 11584 u8 reserved_at_c0[0x8]; 11585 u8 underlay_qpn[0x18]; 11586 u8 table_eswitch_owner_vhca_id_valid[0x1]; 11587 u8 reserved_at_e1[0xf]; 11588 u8 table_eswitch_owner_vhca_id[0x10]; 11589 u8 reserved_at_100[0x100]; 11590 }; 11591 11592 enum { 11593 MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = (1UL << 0), 11594 MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15), 11595 }; 11596 11597 struct mlx5_ifc_modify_flow_table_out_bits { 11598 u8 status[0x8]; 11599 u8 reserved_at_8[0x18]; 11600 11601 u8 syndrome[0x20]; 11602 11603 u8 reserved_at_40[0x40]; 11604 }; 11605 11606 struct mlx5_ifc_modify_flow_table_in_bits { 11607 u8 opcode[0x10]; 11608 u8 reserved_at_10[0x10]; 11609 11610 u8 reserved_at_20[0x10]; 11611 u8 op_mod[0x10]; 11612 11613 u8 other_vport[0x1]; 11614 u8 reserved_at_41[0xf]; 11615 u8 vport_number[0x10]; 11616 11617 u8 reserved_at_60[0x10]; 11618 u8 modify_field_select[0x10]; 11619 11620 u8 table_type[0x8]; 11621 u8 reserved_at_88[0x18]; 11622 11623 u8 reserved_at_a0[0x8]; 11624 u8 table_id[0x18]; 11625 11626 struct mlx5_ifc_flow_table_context_bits flow_table_context; 11627 }; 11628 11629 struct mlx5_ifc_ets_tcn_config_reg_bits { 11630 u8 g[0x1]; 11631 u8 b[0x1]; 11632 u8 r[0x1]; 11633 u8 reserved_at_3[0x9]; 11634 u8 group[0x4]; 11635 u8 reserved_at_10[0x9]; 11636 u8 bw_allocation[0x7]; 11637 11638 u8 reserved_at_20[0xc]; 11639 u8 max_bw_units[0x4]; 11640 u8 reserved_at_30[0x8]; 11641 u8 max_bw_value[0x8]; 11642 }; 11643 11644 struct mlx5_ifc_ets_global_config_reg_bits { 11645 u8 reserved_at_0[0x2]; 11646 u8 r[0x1]; 11647 u8 reserved_at_3[0x1d]; 11648 11649 u8 reserved_at_20[0xc]; 11650 u8 max_bw_units[0x4]; 11651 u8 reserved_at_30[0x8]; 11652 u8 max_bw_value[0x8]; 11653 }; 11654 11655 struct mlx5_ifc_qetc_reg_bits { 11656 u8 reserved_at_0[0x8]; 11657 u8 port_number[0x8]; 11658 u8 reserved_at_10[0x30]; 11659 11660 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8]; 11661 struct mlx5_ifc_ets_global_config_reg_bits global_configuration; 11662 }; 11663 11664 struct mlx5_ifc_qpdpm_dscp_reg_bits { 11665 u8 e[0x1]; 11666 u8 reserved_at_01[0x0b]; 11667 u8 prio[0x04]; 11668 }; 11669 11670 struct mlx5_ifc_qpdpm_reg_bits { 11671 u8 reserved_at_0[0x8]; 11672 u8 local_port[0x8]; 11673 u8 reserved_at_10[0x10]; 11674 struct mlx5_ifc_qpdpm_dscp_reg_bits dscp[64]; 11675 }; 11676 11677 struct mlx5_ifc_qpts_reg_bits { 11678 u8 reserved_at_0[0x8]; 11679 u8 local_port[0x8]; 11680 u8 reserved_at_10[0x2d]; 11681 u8 trust_state[0x3]; 11682 }; 11683 11684 struct mlx5_ifc_pptb_reg_bits { 11685 u8 reserved_at_0[0x2]; 11686 u8 mm[0x2]; 11687 u8 reserved_at_4[0x4]; 11688 u8 local_port[0x8]; 11689 u8 reserved_at_10[0x6]; 11690 u8 cm[0x1]; 11691 u8 um[0x1]; 11692 u8 pm[0x8]; 11693 11694 u8 prio_x_buff[0x20]; 11695 11696 u8 pm_msb[0x8]; 11697 u8 reserved_at_48[0x10]; 11698 u8 ctrl_buff[0x4]; 11699 u8 untagged_buff[0x4]; 11700 }; 11701 11702 struct mlx5_ifc_sbcam_reg_bits { 11703 u8 reserved_at_0[0x8]; 11704 u8 feature_group[0x8]; 11705 u8 reserved_at_10[0x8]; 11706 u8 access_reg_group[0x8]; 11707 11708 u8 reserved_at_20[0x20]; 11709 11710 u8 sb_access_reg_cap_mask[4][0x20]; 11711 11712 u8 reserved_at_c0[0x80]; 11713 11714 u8 sb_feature_cap_mask[4][0x20]; 11715 11716 u8 reserved_at_1c0[0x40]; 11717 11718 u8 cap_total_buffer_size[0x20]; 11719 11720 u8 cap_cell_size[0x10]; 11721 u8 cap_max_pg_buffers[0x8]; 11722 u8 cap_num_pool_supported[0x8]; 11723 11724 u8 reserved_at_240[0x8]; 11725 u8 cap_sbsr_stat_size[0x8]; 11726 u8 cap_max_tclass_data[0x8]; 11727 u8 cap_max_cpu_ingress_tclass_sb[0x8]; 11728 }; 11729 11730 struct mlx5_ifc_pbmc_reg_bits { 11731 u8 reserved_at_0[0x8]; 11732 u8 local_port[0x8]; 11733 u8 reserved_at_10[0x10]; 11734 11735 u8 xoff_timer_value[0x10]; 11736 u8 xoff_refresh[0x10]; 11737 11738 u8 reserved_at_40[0x9]; 11739 u8 fullness_threshold[0x7]; 11740 u8 port_buffer_size[0x10]; 11741 11742 struct mlx5_ifc_bufferx_reg_bits buffer[10]; 11743 11744 u8 reserved_at_2e0[0x80]; 11745 }; 11746 11747 struct mlx5_ifc_sbpr_reg_bits { 11748 u8 desc[0x1]; 11749 u8 snap[0x1]; 11750 u8 reserved_at_2[0x4]; 11751 u8 dir[0x2]; 11752 u8 reserved_at_8[0x14]; 11753 u8 pool[0x4]; 11754 11755 u8 infi_size[0x1]; 11756 u8 reserved_at_21[0x7]; 11757 u8 size[0x18]; 11758 11759 u8 reserved_at_40[0x1c]; 11760 u8 mode[0x4]; 11761 11762 u8 reserved_at_60[0x8]; 11763 u8 buff_occupancy[0x18]; 11764 11765 u8 clr[0x1]; 11766 u8 reserved_at_81[0x7]; 11767 u8 max_buff_occupancy[0x18]; 11768 11769 u8 reserved_at_a0[0x8]; 11770 u8 ext_buff_occupancy[0x18]; 11771 }; 11772 11773 struct mlx5_ifc_sbcm_reg_bits { 11774 u8 desc[0x1]; 11775 u8 snap[0x1]; 11776 u8 reserved_at_2[0x6]; 11777 u8 local_port[0x8]; 11778 u8 pnat[0x2]; 11779 u8 pg_buff[0x6]; 11780 u8 reserved_at_18[0x6]; 11781 u8 dir[0x2]; 11782 11783 u8 reserved_at_20[0x1f]; 11784 u8 exc[0x1]; 11785 11786 u8 reserved_at_40[0x40]; 11787 11788 u8 reserved_at_80[0x8]; 11789 u8 buff_occupancy[0x18]; 11790 11791 u8 clr[0x1]; 11792 u8 reserved_at_a1[0x7]; 11793 u8 max_buff_occupancy[0x18]; 11794 11795 u8 reserved_at_c0[0x8]; 11796 u8 min_buff[0x18]; 11797 11798 u8 infi_max[0x1]; 11799 u8 reserved_at_e1[0x7]; 11800 u8 max_buff[0x18]; 11801 11802 u8 reserved_at_100[0x20]; 11803 11804 u8 reserved_at_120[0x1c]; 11805 u8 pool[0x4]; 11806 }; 11807 11808 struct mlx5_ifc_qtct_reg_bits { 11809 u8 reserved_at_0[0x8]; 11810 u8 port_number[0x8]; 11811 u8 reserved_at_10[0xd]; 11812 u8 prio[0x3]; 11813 11814 u8 reserved_at_20[0x1d]; 11815 u8 tclass[0x3]; 11816 }; 11817 11818 struct mlx5_ifc_mcia_reg_bits { 11819 u8 l[0x1]; 11820 u8 reserved_at_1[0x7]; 11821 u8 module[0x8]; 11822 u8 reserved_at_10[0x8]; 11823 u8 status[0x8]; 11824 11825 u8 i2c_device_address[0x8]; 11826 u8 page_number[0x8]; 11827 u8 device_address[0x10]; 11828 11829 u8 reserved_at_40[0x10]; 11830 u8 size[0x10]; 11831 11832 u8 reserved_at_60[0x20]; 11833 11834 u8 dword_0[0x20]; 11835 u8 dword_1[0x20]; 11836 u8 dword_2[0x20]; 11837 u8 dword_3[0x20]; 11838 u8 dword_4[0x20]; 11839 u8 dword_5[0x20]; 11840 u8 dword_6[0x20]; 11841 u8 dword_7[0x20]; 11842 u8 dword_8[0x20]; 11843 u8 dword_9[0x20]; 11844 u8 dword_10[0x20]; 11845 u8 dword_11[0x20]; 11846 }; 11847 11848 struct mlx5_ifc_dcbx_param_bits { 11849 u8 dcbx_cee_cap[0x1]; 11850 u8 dcbx_ieee_cap[0x1]; 11851 u8 dcbx_standby_cap[0x1]; 11852 u8 reserved_at_3[0x5]; 11853 u8 port_number[0x8]; 11854 u8 reserved_at_10[0xa]; 11855 u8 max_application_table_size[6]; 11856 u8 reserved_at_20[0x15]; 11857 u8 version_oper[0x3]; 11858 u8 reserved_at_38[5]; 11859 u8 version_admin[0x3]; 11860 u8 willing_admin[0x1]; 11861 u8 reserved_at_41[0x3]; 11862 u8 pfc_cap_oper[0x4]; 11863 u8 reserved_at_48[0x4]; 11864 u8 pfc_cap_admin[0x4]; 11865 u8 reserved_at_50[0x4]; 11866 u8 num_of_tc_oper[0x4]; 11867 u8 reserved_at_58[0x4]; 11868 u8 num_of_tc_admin[0x4]; 11869 u8 remote_willing[0x1]; 11870 u8 reserved_at_61[3]; 11871 u8 remote_pfc_cap[4]; 11872 u8 reserved_at_68[0x14]; 11873 u8 remote_num_of_tc[0x4]; 11874 u8 reserved_at_80[0x18]; 11875 u8 error[0x8]; 11876 u8 reserved_at_a0[0x160]; 11877 }; 11878 11879 enum { 11880 MLX5_LAG_PORT_SELECT_MODE_QUEUE_AFFINITY = 0, 11881 MLX5_LAG_PORT_SELECT_MODE_PORT_SELECT_FT = 1, 11882 MLX5_LAG_PORT_SELECT_MODE_PORT_SELECT_MPESW = 2, 11883 }; 11884 11885 struct mlx5_ifc_lagc_bits { 11886 u8 fdb_selection_mode[0x1]; 11887 u8 reserved_at_1[0x14]; 11888 u8 port_select_mode[0x3]; 11889 u8 reserved_at_18[0x5]; 11890 u8 lag_state[0x3]; 11891 11892 u8 reserved_at_20[0xc]; 11893 u8 active_port[0x4]; 11894 u8 reserved_at_30[0x4]; 11895 u8 tx_remap_affinity_2[0x4]; 11896 u8 reserved_at_38[0x4]; 11897 u8 tx_remap_affinity_1[0x4]; 11898 }; 11899 11900 struct mlx5_ifc_create_lag_out_bits { 11901 u8 status[0x8]; 11902 u8 reserved_at_8[0x18]; 11903 11904 u8 syndrome[0x20]; 11905 11906 u8 reserved_at_40[0x40]; 11907 }; 11908 11909 struct mlx5_ifc_create_lag_in_bits { 11910 u8 opcode[0x10]; 11911 u8 reserved_at_10[0x10]; 11912 11913 u8 reserved_at_20[0x10]; 11914 u8 op_mod[0x10]; 11915 11916 struct mlx5_ifc_lagc_bits ctx; 11917 }; 11918 11919 struct mlx5_ifc_modify_lag_out_bits { 11920 u8 status[0x8]; 11921 u8 reserved_at_8[0x18]; 11922 11923 u8 syndrome[0x20]; 11924 11925 u8 reserved_at_40[0x40]; 11926 }; 11927 11928 struct mlx5_ifc_modify_lag_in_bits { 11929 u8 opcode[0x10]; 11930 u8 reserved_at_10[0x10]; 11931 11932 u8 reserved_at_20[0x10]; 11933 u8 op_mod[0x10]; 11934 11935 u8 reserved_at_40[0x20]; 11936 u8 field_select[0x20]; 11937 11938 struct mlx5_ifc_lagc_bits ctx; 11939 }; 11940 11941 struct mlx5_ifc_query_lag_out_bits { 11942 u8 status[0x8]; 11943 u8 reserved_at_8[0x18]; 11944 11945 u8 syndrome[0x20]; 11946 11947 struct mlx5_ifc_lagc_bits ctx; 11948 }; 11949 11950 struct mlx5_ifc_query_lag_in_bits { 11951 u8 opcode[0x10]; 11952 u8 reserved_at_10[0x10]; 11953 11954 u8 reserved_at_20[0x10]; 11955 u8 op_mod[0x10]; 11956 11957 u8 reserved_at_40[0x40]; 11958 }; 11959 11960 struct mlx5_ifc_destroy_lag_out_bits { 11961 u8 status[0x8]; 11962 u8 reserved_at_8[0x18]; 11963 11964 u8 syndrome[0x20]; 11965 11966 u8 reserved_at_40[0x40]; 11967 }; 11968 11969 struct mlx5_ifc_destroy_lag_in_bits { 11970 u8 opcode[0x10]; 11971 u8 reserved_at_10[0x10]; 11972 11973 u8 reserved_at_20[0x10]; 11974 u8 op_mod[0x10]; 11975 11976 u8 reserved_at_40[0x40]; 11977 }; 11978 11979 struct mlx5_ifc_create_vport_lag_out_bits { 11980 u8 status[0x8]; 11981 u8 reserved_at_8[0x18]; 11982 11983 u8 syndrome[0x20]; 11984 11985 u8 reserved_at_40[0x40]; 11986 }; 11987 11988 struct mlx5_ifc_create_vport_lag_in_bits { 11989 u8 opcode[0x10]; 11990 u8 reserved_at_10[0x10]; 11991 11992 u8 reserved_at_20[0x10]; 11993 u8 op_mod[0x10]; 11994 11995 u8 reserved_at_40[0x40]; 11996 }; 11997 11998 struct mlx5_ifc_destroy_vport_lag_out_bits { 11999 u8 status[0x8]; 12000 u8 reserved_at_8[0x18]; 12001 12002 u8 syndrome[0x20]; 12003 12004 u8 reserved_at_40[0x40]; 12005 }; 12006 12007 struct mlx5_ifc_destroy_vport_lag_in_bits { 12008 u8 opcode[0x10]; 12009 u8 reserved_at_10[0x10]; 12010 12011 u8 reserved_at_20[0x10]; 12012 u8 op_mod[0x10]; 12013 12014 u8 reserved_at_40[0x40]; 12015 }; 12016 12017 enum { 12018 MLX5_MODIFY_MEMIC_OP_MOD_ALLOC, 12019 MLX5_MODIFY_MEMIC_OP_MOD_DEALLOC, 12020 }; 12021 12022 struct mlx5_ifc_modify_memic_in_bits { 12023 u8 opcode[0x10]; 12024 u8 uid[0x10]; 12025 12026 u8 reserved_at_20[0x10]; 12027 u8 op_mod[0x10]; 12028 12029 u8 reserved_at_40[0x20]; 12030 12031 u8 reserved_at_60[0x18]; 12032 u8 memic_operation_type[0x8]; 12033 12034 u8 memic_start_addr[0x40]; 12035 12036 u8 reserved_at_c0[0x140]; 12037 }; 12038 12039 struct mlx5_ifc_modify_memic_out_bits { 12040 u8 status[0x8]; 12041 u8 reserved_at_8[0x18]; 12042 12043 u8 syndrome[0x20]; 12044 12045 u8 reserved_at_40[0x40]; 12046 12047 u8 memic_operation_addr[0x40]; 12048 12049 u8 reserved_at_c0[0x140]; 12050 }; 12051 12052 struct mlx5_ifc_alloc_memic_in_bits { 12053 u8 opcode[0x10]; 12054 u8 reserved_at_10[0x10]; 12055 12056 u8 reserved_at_20[0x10]; 12057 u8 op_mod[0x10]; 12058 12059 u8 reserved_at_30[0x20]; 12060 12061 u8 reserved_at_40[0x18]; 12062 u8 log_memic_addr_alignment[0x8]; 12063 12064 u8 range_start_addr[0x40]; 12065 12066 u8 range_size[0x20]; 12067 12068 u8 memic_size[0x20]; 12069 }; 12070 12071 struct mlx5_ifc_alloc_memic_out_bits { 12072 u8 status[0x8]; 12073 u8 reserved_at_8[0x18]; 12074 12075 u8 syndrome[0x20]; 12076 12077 u8 memic_start_addr[0x40]; 12078 }; 12079 12080 struct mlx5_ifc_dealloc_memic_in_bits { 12081 u8 opcode[0x10]; 12082 u8 reserved_at_10[0x10]; 12083 12084 u8 reserved_at_20[0x10]; 12085 u8 op_mod[0x10]; 12086 12087 u8 reserved_at_40[0x40]; 12088 12089 u8 memic_start_addr[0x40]; 12090 12091 u8 memic_size[0x20]; 12092 12093 u8 reserved_at_e0[0x20]; 12094 }; 12095 12096 struct mlx5_ifc_dealloc_memic_out_bits { 12097 u8 status[0x8]; 12098 u8 reserved_at_8[0x18]; 12099 12100 u8 syndrome[0x20]; 12101 12102 u8 reserved_at_40[0x40]; 12103 }; 12104 12105 struct mlx5_ifc_umem_bits { 12106 u8 reserved_at_0[0x80]; 12107 12108 u8 ats[0x1]; 12109 u8 reserved_at_81[0x1a]; 12110 u8 log_page_size[0x5]; 12111 12112 u8 page_offset[0x20]; 12113 12114 u8 num_of_mtt[0x40]; 12115 12116 struct mlx5_ifc_mtt_bits mtt[]; 12117 }; 12118 12119 struct mlx5_ifc_uctx_bits { 12120 u8 cap[0x20]; 12121 12122 u8 reserved_at_20[0x160]; 12123 }; 12124 12125 struct mlx5_ifc_sw_icm_bits { 12126 u8 modify_field_select[0x40]; 12127 12128 u8 reserved_at_40[0x18]; 12129 u8 log_sw_icm_size[0x8]; 12130 12131 u8 reserved_at_60[0x20]; 12132 12133 u8 sw_icm_start_addr[0x40]; 12134 12135 u8 reserved_at_c0[0x140]; 12136 }; 12137 12138 struct mlx5_ifc_geneve_tlv_option_bits { 12139 u8 modify_field_select[0x40]; 12140 12141 u8 reserved_at_40[0x18]; 12142 u8 geneve_option_fte_index[0x8]; 12143 12144 u8 option_class[0x10]; 12145 u8 option_type[0x8]; 12146 u8 reserved_at_78[0x3]; 12147 u8 option_data_length[0x5]; 12148 12149 u8 reserved_at_80[0x180]; 12150 }; 12151 12152 struct mlx5_ifc_create_umem_in_bits { 12153 u8 opcode[0x10]; 12154 u8 uid[0x10]; 12155 12156 u8 reserved_at_20[0x10]; 12157 u8 op_mod[0x10]; 12158 12159 u8 reserved_at_40[0x40]; 12160 12161 struct mlx5_ifc_umem_bits umem; 12162 }; 12163 12164 struct mlx5_ifc_create_umem_out_bits { 12165 u8 status[0x8]; 12166 u8 reserved_at_8[0x18]; 12167 12168 u8 syndrome[0x20]; 12169 12170 u8 reserved_at_40[0x8]; 12171 u8 umem_id[0x18]; 12172 12173 u8 reserved_at_60[0x20]; 12174 }; 12175 12176 struct mlx5_ifc_destroy_umem_in_bits { 12177 u8 opcode[0x10]; 12178 u8 uid[0x10]; 12179 12180 u8 reserved_at_20[0x10]; 12181 u8 op_mod[0x10]; 12182 12183 u8 reserved_at_40[0x8]; 12184 u8 umem_id[0x18]; 12185 12186 u8 reserved_at_60[0x20]; 12187 }; 12188 12189 struct mlx5_ifc_destroy_umem_out_bits { 12190 u8 status[0x8]; 12191 u8 reserved_at_8[0x18]; 12192 12193 u8 syndrome[0x20]; 12194 12195 u8 reserved_at_40[0x40]; 12196 }; 12197 12198 struct mlx5_ifc_create_uctx_in_bits { 12199 u8 opcode[0x10]; 12200 u8 reserved_at_10[0x10]; 12201 12202 u8 reserved_at_20[0x10]; 12203 u8 op_mod[0x10]; 12204 12205 u8 reserved_at_40[0x40]; 12206 12207 struct mlx5_ifc_uctx_bits uctx; 12208 }; 12209 12210 struct mlx5_ifc_create_uctx_out_bits { 12211 u8 status[0x8]; 12212 u8 reserved_at_8[0x18]; 12213 12214 u8 syndrome[0x20]; 12215 12216 u8 reserved_at_40[0x10]; 12217 u8 uid[0x10]; 12218 12219 u8 reserved_at_60[0x20]; 12220 }; 12221 12222 struct mlx5_ifc_destroy_uctx_in_bits { 12223 u8 opcode[0x10]; 12224 u8 reserved_at_10[0x10]; 12225 12226 u8 reserved_at_20[0x10]; 12227 u8 op_mod[0x10]; 12228 12229 u8 reserved_at_40[0x10]; 12230 u8 uid[0x10]; 12231 12232 u8 reserved_at_60[0x20]; 12233 }; 12234 12235 struct mlx5_ifc_destroy_uctx_out_bits { 12236 u8 status[0x8]; 12237 u8 reserved_at_8[0x18]; 12238 12239 u8 syndrome[0x20]; 12240 12241 u8 reserved_at_40[0x40]; 12242 }; 12243 12244 struct mlx5_ifc_create_sw_icm_in_bits { 12245 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 12246 struct mlx5_ifc_sw_icm_bits sw_icm; 12247 }; 12248 12249 struct mlx5_ifc_create_geneve_tlv_option_in_bits { 12250 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 12251 struct mlx5_ifc_geneve_tlv_option_bits geneve_tlv_opt; 12252 }; 12253 12254 struct mlx5_ifc_mtrc_string_db_param_bits { 12255 u8 string_db_base_address[0x20]; 12256 12257 u8 reserved_at_20[0x8]; 12258 u8 string_db_size[0x18]; 12259 }; 12260 12261 struct mlx5_ifc_mtrc_cap_bits { 12262 u8 trace_owner[0x1]; 12263 u8 trace_to_memory[0x1]; 12264 u8 reserved_at_2[0x4]; 12265 u8 trc_ver[0x2]; 12266 u8 reserved_at_8[0x14]; 12267 u8 num_string_db[0x4]; 12268 12269 u8 first_string_trace[0x8]; 12270 u8 num_string_trace[0x8]; 12271 u8 reserved_at_30[0x28]; 12272 12273 u8 log_max_trace_buffer_size[0x8]; 12274 12275 u8 reserved_at_60[0x20]; 12276 12277 struct mlx5_ifc_mtrc_string_db_param_bits string_db_param[8]; 12278 12279 u8 reserved_at_280[0x180]; 12280 }; 12281 12282 struct mlx5_ifc_mtrc_conf_bits { 12283 u8 reserved_at_0[0x1c]; 12284 u8 trace_mode[0x4]; 12285 u8 reserved_at_20[0x18]; 12286 u8 log_trace_buffer_size[0x8]; 12287 u8 trace_mkey[0x20]; 12288 u8 reserved_at_60[0x3a0]; 12289 }; 12290 12291 struct mlx5_ifc_mtrc_stdb_bits { 12292 u8 string_db_index[0x4]; 12293 u8 reserved_at_4[0x4]; 12294 u8 read_size[0x18]; 12295 u8 start_offset[0x20]; 12296 u8 string_db_data[]; 12297 }; 12298 12299 struct mlx5_ifc_mtrc_ctrl_bits { 12300 u8 trace_status[0x2]; 12301 u8 reserved_at_2[0x2]; 12302 u8 arm_event[0x1]; 12303 u8 reserved_at_5[0xb]; 12304 u8 modify_field_select[0x10]; 12305 u8 reserved_at_20[0x2b]; 12306 u8 current_timestamp52_32[0x15]; 12307 u8 current_timestamp31_0[0x20]; 12308 u8 reserved_at_80[0x180]; 12309 }; 12310 12311 struct mlx5_ifc_host_params_context_bits { 12312 u8 host_number[0x8]; 12313 u8 reserved_at_8[0x7]; 12314 u8 host_pf_disabled[0x1]; 12315 u8 host_num_of_vfs[0x10]; 12316 12317 u8 host_total_vfs[0x10]; 12318 u8 host_pci_bus[0x10]; 12319 12320 u8 reserved_at_40[0x10]; 12321 u8 host_pci_device[0x10]; 12322 12323 u8 reserved_at_60[0x10]; 12324 u8 host_pci_function[0x10]; 12325 12326 u8 reserved_at_80[0x180]; 12327 }; 12328 12329 struct mlx5_ifc_query_esw_functions_in_bits { 12330 u8 opcode[0x10]; 12331 u8 reserved_at_10[0x10]; 12332 12333 u8 reserved_at_20[0x10]; 12334 u8 op_mod[0x10]; 12335 12336 u8 reserved_at_40[0x40]; 12337 }; 12338 12339 struct mlx5_ifc_query_esw_functions_out_bits { 12340 u8 status[0x8]; 12341 u8 reserved_at_8[0x18]; 12342 12343 u8 syndrome[0x20]; 12344 12345 u8 reserved_at_40[0x40]; 12346 12347 struct mlx5_ifc_host_params_context_bits host_params_context; 12348 12349 u8 reserved_at_280[0x180]; 12350 u8 host_sf_enable[][0x40]; 12351 }; 12352 12353 struct mlx5_ifc_sf_partition_bits { 12354 u8 reserved_at_0[0x10]; 12355 u8 log_num_sf[0x8]; 12356 u8 log_sf_bar_size[0x8]; 12357 }; 12358 12359 struct mlx5_ifc_query_sf_partitions_out_bits { 12360 u8 status[0x8]; 12361 u8 reserved_at_8[0x18]; 12362 12363 u8 syndrome[0x20]; 12364 12365 u8 reserved_at_40[0x18]; 12366 u8 num_sf_partitions[0x8]; 12367 12368 u8 reserved_at_60[0x20]; 12369 12370 struct mlx5_ifc_sf_partition_bits sf_partition[]; 12371 }; 12372 12373 struct mlx5_ifc_query_sf_partitions_in_bits { 12374 u8 opcode[0x10]; 12375 u8 reserved_at_10[0x10]; 12376 12377 u8 reserved_at_20[0x10]; 12378 u8 op_mod[0x10]; 12379 12380 u8 reserved_at_40[0x40]; 12381 }; 12382 12383 struct mlx5_ifc_dealloc_sf_out_bits { 12384 u8 status[0x8]; 12385 u8 reserved_at_8[0x18]; 12386 12387 u8 syndrome[0x20]; 12388 12389 u8 reserved_at_40[0x40]; 12390 }; 12391 12392 struct mlx5_ifc_dealloc_sf_in_bits { 12393 u8 opcode[0x10]; 12394 u8 reserved_at_10[0x10]; 12395 12396 u8 reserved_at_20[0x10]; 12397 u8 op_mod[0x10]; 12398 12399 u8 reserved_at_40[0x10]; 12400 u8 function_id[0x10]; 12401 12402 u8 reserved_at_60[0x20]; 12403 }; 12404 12405 struct mlx5_ifc_alloc_sf_out_bits { 12406 u8 status[0x8]; 12407 u8 reserved_at_8[0x18]; 12408 12409 u8 syndrome[0x20]; 12410 12411 u8 reserved_at_40[0x40]; 12412 }; 12413 12414 struct mlx5_ifc_alloc_sf_in_bits { 12415 u8 opcode[0x10]; 12416 u8 reserved_at_10[0x10]; 12417 12418 u8 reserved_at_20[0x10]; 12419 u8 op_mod[0x10]; 12420 12421 u8 reserved_at_40[0x10]; 12422 u8 function_id[0x10]; 12423 12424 u8 reserved_at_60[0x20]; 12425 }; 12426 12427 struct mlx5_ifc_affiliated_event_header_bits { 12428 u8 reserved_at_0[0x10]; 12429 u8 obj_type[0x10]; 12430 12431 u8 obj_id[0x20]; 12432 }; 12433 12434 enum { 12435 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = BIT_ULL(0xc), 12436 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_IPSEC = BIT_ULL(0x13), 12437 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_SAMPLER = BIT_ULL(0x20), 12438 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_FLOW_METER_ASO = BIT_ULL(0x24), 12439 }; 12440 12441 enum { 12442 MLX5_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = 0xc, 12443 MLX5_GENERAL_OBJECT_TYPES_IPSEC = 0x13, 12444 MLX5_GENERAL_OBJECT_TYPES_SAMPLER = 0x20, 12445 MLX5_GENERAL_OBJECT_TYPES_FLOW_METER_ASO = 0x24, 12446 MLX5_GENERAL_OBJECT_TYPES_MACSEC = 0x27, 12447 MLX5_GENERAL_OBJECT_TYPES_INT_KEK = 0x47, 12448 MLX5_GENERAL_OBJECT_TYPES_FLOW_TABLE_ALIAS = 0xff15, 12449 }; 12450 12451 enum { 12452 MLX5_IPSEC_OBJECT_ICV_LEN_16B, 12453 }; 12454 12455 enum { 12456 MLX5_IPSEC_ASO_REG_C_0_1 = 0x0, 12457 MLX5_IPSEC_ASO_REG_C_2_3 = 0x1, 12458 MLX5_IPSEC_ASO_REG_C_4_5 = 0x2, 12459 MLX5_IPSEC_ASO_REG_C_6_7 = 0x3, 12460 }; 12461 12462 enum { 12463 MLX5_IPSEC_ASO_MODE = 0x0, 12464 MLX5_IPSEC_ASO_REPLAY_PROTECTION = 0x1, 12465 MLX5_IPSEC_ASO_INC_SN = 0x2, 12466 }; 12467 12468 enum { 12469 MLX5_IPSEC_ASO_REPLAY_WIN_32BIT = 0x0, 12470 MLX5_IPSEC_ASO_REPLAY_WIN_64BIT = 0x1, 12471 MLX5_IPSEC_ASO_REPLAY_WIN_128BIT = 0x2, 12472 MLX5_IPSEC_ASO_REPLAY_WIN_256BIT = 0x3, 12473 }; 12474 12475 struct mlx5_ifc_ipsec_aso_bits { 12476 u8 valid[0x1]; 12477 u8 reserved_at_201[0x1]; 12478 u8 mode[0x2]; 12479 u8 window_sz[0x2]; 12480 u8 soft_lft_arm[0x1]; 12481 u8 hard_lft_arm[0x1]; 12482 u8 remove_flow_enable[0x1]; 12483 u8 esn_event_arm[0x1]; 12484 u8 reserved_at_20a[0x16]; 12485 12486 u8 remove_flow_pkt_cnt[0x20]; 12487 12488 u8 remove_flow_soft_lft[0x20]; 12489 12490 u8 reserved_at_260[0x80]; 12491 12492 u8 mode_parameter[0x20]; 12493 12494 u8 replay_protection_window[0x100]; 12495 }; 12496 12497 struct mlx5_ifc_ipsec_obj_bits { 12498 u8 modify_field_select[0x40]; 12499 u8 full_offload[0x1]; 12500 u8 reserved_at_41[0x1]; 12501 u8 esn_en[0x1]; 12502 u8 esn_overlap[0x1]; 12503 u8 reserved_at_44[0x2]; 12504 u8 icv_length[0x2]; 12505 u8 reserved_at_48[0x4]; 12506 u8 aso_return_reg[0x4]; 12507 u8 reserved_at_50[0x10]; 12508 12509 u8 esn_msb[0x20]; 12510 12511 u8 reserved_at_80[0x8]; 12512 u8 dekn[0x18]; 12513 12514 u8 salt[0x20]; 12515 12516 u8 implicit_iv[0x40]; 12517 12518 u8 reserved_at_100[0x8]; 12519 u8 ipsec_aso_access_pd[0x18]; 12520 u8 reserved_at_120[0xe0]; 12521 12522 struct mlx5_ifc_ipsec_aso_bits ipsec_aso; 12523 }; 12524 12525 struct mlx5_ifc_create_ipsec_obj_in_bits { 12526 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12527 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 12528 }; 12529 12530 enum { 12531 MLX5_MODIFY_IPSEC_BITMASK_ESN_OVERLAP = BIT(0), 12532 MLX5_MODIFY_IPSEC_BITMASK_ESN_MSB = BIT(1), 12533 }; 12534 12535 struct mlx5_ifc_query_ipsec_obj_out_bits { 12536 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 12537 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 12538 }; 12539 12540 struct mlx5_ifc_modify_ipsec_obj_in_bits { 12541 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12542 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 12543 }; 12544 12545 enum { 12546 MLX5_MACSEC_ASO_REPLAY_PROTECTION = 0x1, 12547 }; 12548 12549 enum { 12550 MLX5_MACSEC_ASO_REPLAY_WIN_32BIT = 0x0, 12551 MLX5_MACSEC_ASO_REPLAY_WIN_64BIT = 0x1, 12552 MLX5_MACSEC_ASO_REPLAY_WIN_128BIT = 0x2, 12553 MLX5_MACSEC_ASO_REPLAY_WIN_256BIT = 0x3, 12554 }; 12555 12556 #define MLX5_MACSEC_ASO_INC_SN 0x2 12557 #define MLX5_MACSEC_ASO_REG_C_4_5 0x2 12558 12559 struct mlx5_ifc_macsec_aso_bits { 12560 u8 valid[0x1]; 12561 u8 reserved_at_1[0x1]; 12562 u8 mode[0x2]; 12563 u8 window_size[0x2]; 12564 u8 soft_lifetime_arm[0x1]; 12565 u8 hard_lifetime_arm[0x1]; 12566 u8 remove_flow_enable[0x1]; 12567 u8 epn_event_arm[0x1]; 12568 u8 reserved_at_a[0x16]; 12569 12570 u8 remove_flow_packet_count[0x20]; 12571 12572 u8 remove_flow_soft_lifetime[0x20]; 12573 12574 u8 reserved_at_60[0x80]; 12575 12576 u8 mode_parameter[0x20]; 12577 12578 u8 replay_protection_window[8][0x20]; 12579 }; 12580 12581 struct mlx5_ifc_macsec_offload_obj_bits { 12582 u8 modify_field_select[0x40]; 12583 12584 u8 confidentiality_en[0x1]; 12585 u8 reserved_at_41[0x1]; 12586 u8 epn_en[0x1]; 12587 u8 epn_overlap[0x1]; 12588 u8 reserved_at_44[0x2]; 12589 u8 confidentiality_offset[0x2]; 12590 u8 reserved_at_48[0x4]; 12591 u8 aso_return_reg[0x4]; 12592 u8 reserved_at_50[0x10]; 12593 12594 u8 epn_msb[0x20]; 12595 12596 u8 reserved_at_80[0x8]; 12597 u8 dekn[0x18]; 12598 12599 u8 reserved_at_a0[0x20]; 12600 12601 u8 sci[0x40]; 12602 12603 u8 reserved_at_100[0x8]; 12604 u8 macsec_aso_access_pd[0x18]; 12605 12606 u8 reserved_at_120[0x60]; 12607 12608 u8 salt[3][0x20]; 12609 12610 u8 reserved_at_1e0[0x20]; 12611 12612 struct mlx5_ifc_macsec_aso_bits macsec_aso; 12613 }; 12614 12615 struct mlx5_ifc_create_macsec_obj_in_bits { 12616 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12617 struct mlx5_ifc_macsec_offload_obj_bits macsec_object; 12618 }; 12619 12620 struct mlx5_ifc_modify_macsec_obj_in_bits { 12621 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12622 struct mlx5_ifc_macsec_offload_obj_bits macsec_object; 12623 }; 12624 12625 enum { 12626 MLX5_MODIFY_MACSEC_BITMASK_EPN_OVERLAP = BIT(0), 12627 MLX5_MODIFY_MACSEC_BITMASK_EPN_MSB = BIT(1), 12628 }; 12629 12630 struct mlx5_ifc_query_macsec_obj_out_bits { 12631 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 12632 struct mlx5_ifc_macsec_offload_obj_bits macsec_object; 12633 }; 12634 12635 struct mlx5_ifc_wrapped_dek_bits { 12636 u8 gcm_iv[0x60]; 12637 12638 u8 reserved_at_60[0x20]; 12639 12640 u8 const0[0x1]; 12641 u8 key_size[0x1]; 12642 u8 reserved_at_82[0x2]; 12643 u8 key2_invalid[0x1]; 12644 u8 reserved_at_85[0x3]; 12645 u8 pd[0x18]; 12646 12647 u8 key_purpose[0x5]; 12648 u8 reserved_at_a5[0x13]; 12649 u8 kek_id[0x8]; 12650 12651 u8 reserved_at_c0[0x40]; 12652 12653 u8 key1[0x8][0x20]; 12654 12655 u8 key2[0x8][0x20]; 12656 12657 u8 reserved_at_300[0x40]; 12658 12659 u8 const1[0x1]; 12660 u8 reserved_at_341[0x1f]; 12661 12662 u8 reserved_at_360[0x20]; 12663 12664 u8 auth_tag[0x80]; 12665 }; 12666 12667 struct mlx5_ifc_encryption_key_obj_bits { 12668 u8 modify_field_select[0x40]; 12669 12670 u8 state[0x8]; 12671 u8 sw_wrapped[0x1]; 12672 u8 reserved_at_49[0xb]; 12673 u8 key_size[0x4]; 12674 u8 reserved_at_58[0x4]; 12675 u8 key_purpose[0x4]; 12676 12677 u8 reserved_at_60[0x8]; 12678 u8 pd[0x18]; 12679 12680 u8 reserved_at_80[0x100]; 12681 12682 u8 opaque[0x40]; 12683 12684 u8 reserved_at_1c0[0x40]; 12685 12686 u8 key[8][0x80]; 12687 12688 u8 sw_wrapped_dek[8][0x80]; 12689 12690 u8 reserved_at_a00[0x600]; 12691 }; 12692 12693 struct mlx5_ifc_create_encryption_key_in_bits { 12694 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12695 struct mlx5_ifc_encryption_key_obj_bits encryption_key_object; 12696 }; 12697 12698 struct mlx5_ifc_modify_encryption_key_in_bits { 12699 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12700 struct mlx5_ifc_encryption_key_obj_bits encryption_key_object; 12701 }; 12702 12703 enum { 12704 MLX5_FLOW_METER_MODE_BYTES_IP_LENGTH = 0x0, 12705 MLX5_FLOW_METER_MODE_BYTES_CALC_WITH_L2 = 0x1, 12706 MLX5_FLOW_METER_MODE_BYTES_CALC_WITH_L2_IPG = 0x2, 12707 MLX5_FLOW_METER_MODE_NUM_PACKETS = 0x3, 12708 }; 12709 12710 struct mlx5_ifc_flow_meter_parameters_bits { 12711 u8 valid[0x1]; 12712 u8 bucket_overflow[0x1]; 12713 u8 start_color[0x2]; 12714 u8 both_buckets_on_green[0x1]; 12715 u8 reserved_at_5[0x1]; 12716 u8 meter_mode[0x2]; 12717 u8 reserved_at_8[0x18]; 12718 12719 u8 reserved_at_20[0x20]; 12720 12721 u8 reserved_at_40[0x3]; 12722 u8 cbs_exponent[0x5]; 12723 u8 cbs_mantissa[0x8]; 12724 u8 reserved_at_50[0x3]; 12725 u8 cir_exponent[0x5]; 12726 u8 cir_mantissa[0x8]; 12727 12728 u8 reserved_at_60[0x20]; 12729 12730 u8 reserved_at_80[0x3]; 12731 u8 ebs_exponent[0x5]; 12732 u8 ebs_mantissa[0x8]; 12733 u8 reserved_at_90[0x3]; 12734 u8 eir_exponent[0x5]; 12735 u8 eir_mantissa[0x8]; 12736 12737 u8 reserved_at_a0[0x60]; 12738 }; 12739 12740 struct mlx5_ifc_flow_meter_aso_obj_bits { 12741 u8 modify_field_select[0x40]; 12742 12743 u8 reserved_at_40[0x40]; 12744 12745 u8 reserved_at_80[0x8]; 12746 u8 meter_aso_access_pd[0x18]; 12747 12748 u8 reserved_at_a0[0x160]; 12749 12750 struct mlx5_ifc_flow_meter_parameters_bits flow_meter_parameters[2]; 12751 }; 12752 12753 struct mlx5_ifc_create_flow_meter_aso_obj_in_bits { 12754 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 12755 struct mlx5_ifc_flow_meter_aso_obj_bits flow_meter_aso_obj; 12756 }; 12757 12758 struct mlx5_ifc_int_kek_obj_bits { 12759 u8 modify_field_select[0x40]; 12760 12761 u8 state[0x8]; 12762 u8 auto_gen[0x1]; 12763 u8 reserved_at_49[0xb]; 12764 u8 key_size[0x4]; 12765 u8 reserved_at_58[0x8]; 12766 12767 u8 reserved_at_60[0x8]; 12768 u8 pd[0x18]; 12769 12770 u8 reserved_at_80[0x180]; 12771 u8 key[8][0x80]; 12772 12773 u8 reserved_at_600[0x200]; 12774 }; 12775 12776 struct mlx5_ifc_create_int_kek_obj_in_bits { 12777 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12778 struct mlx5_ifc_int_kek_obj_bits int_kek_object; 12779 }; 12780 12781 struct mlx5_ifc_create_int_kek_obj_out_bits { 12782 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 12783 struct mlx5_ifc_int_kek_obj_bits int_kek_object; 12784 }; 12785 12786 struct mlx5_ifc_sampler_obj_bits { 12787 u8 modify_field_select[0x40]; 12788 12789 u8 table_type[0x8]; 12790 u8 level[0x8]; 12791 u8 reserved_at_50[0xf]; 12792 u8 ignore_flow_level[0x1]; 12793 12794 u8 sample_ratio[0x20]; 12795 12796 u8 reserved_at_80[0x8]; 12797 u8 sample_table_id[0x18]; 12798 12799 u8 reserved_at_a0[0x8]; 12800 u8 default_table_id[0x18]; 12801 12802 u8 sw_steering_icm_address_rx[0x40]; 12803 u8 sw_steering_icm_address_tx[0x40]; 12804 12805 u8 reserved_at_140[0xa0]; 12806 }; 12807 12808 struct mlx5_ifc_create_sampler_obj_in_bits { 12809 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12810 struct mlx5_ifc_sampler_obj_bits sampler_object; 12811 }; 12812 12813 struct mlx5_ifc_query_sampler_obj_out_bits { 12814 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 12815 struct mlx5_ifc_sampler_obj_bits sampler_object; 12816 }; 12817 12818 enum { 12819 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_128 = 0x0, 12820 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_256 = 0x1, 12821 }; 12822 12823 enum { 12824 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_PURPOSE_TLS = 0x1, 12825 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_PURPOSE_IPSEC = 0x2, 12826 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_PURPOSE_MACSEC = 0x4, 12827 }; 12828 12829 struct mlx5_ifc_tls_static_params_bits { 12830 u8 const_2[0x2]; 12831 u8 tls_version[0x4]; 12832 u8 const_1[0x2]; 12833 u8 reserved_at_8[0x14]; 12834 u8 encryption_standard[0x4]; 12835 12836 u8 reserved_at_20[0x20]; 12837 12838 u8 initial_record_number[0x40]; 12839 12840 u8 resync_tcp_sn[0x20]; 12841 12842 u8 gcm_iv[0x20]; 12843 12844 u8 implicit_iv[0x40]; 12845 12846 u8 reserved_at_100[0x8]; 12847 u8 dek_index[0x18]; 12848 12849 u8 reserved_at_120[0xe0]; 12850 }; 12851 12852 struct mlx5_ifc_tls_progress_params_bits { 12853 u8 next_record_tcp_sn[0x20]; 12854 12855 u8 hw_resync_tcp_sn[0x20]; 12856 12857 u8 record_tracker_state[0x2]; 12858 u8 auth_state[0x2]; 12859 u8 reserved_at_44[0x4]; 12860 u8 hw_offset_record_number[0x18]; 12861 }; 12862 12863 enum { 12864 MLX5_MTT_PERM_READ = 1 << 0, 12865 MLX5_MTT_PERM_WRITE = 1 << 1, 12866 MLX5_MTT_PERM_RW = MLX5_MTT_PERM_READ | MLX5_MTT_PERM_WRITE, 12867 }; 12868 12869 enum { 12870 MLX5_SUSPEND_VHCA_IN_OP_MOD_SUSPEND_INITIATOR = 0x0, 12871 MLX5_SUSPEND_VHCA_IN_OP_MOD_SUSPEND_RESPONDER = 0x1, 12872 }; 12873 12874 struct mlx5_ifc_suspend_vhca_in_bits { 12875 u8 opcode[0x10]; 12876 u8 uid[0x10]; 12877 12878 u8 reserved_at_20[0x10]; 12879 u8 op_mod[0x10]; 12880 12881 u8 reserved_at_40[0x10]; 12882 u8 vhca_id[0x10]; 12883 12884 u8 reserved_at_60[0x20]; 12885 }; 12886 12887 struct mlx5_ifc_suspend_vhca_out_bits { 12888 u8 status[0x8]; 12889 u8 reserved_at_8[0x18]; 12890 12891 u8 syndrome[0x20]; 12892 12893 u8 reserved_at_40[0x40]; 12894 }; 12895 12896 enum { 12897 MLX5_RESUME_VHCA_IN_OP_MOD_RESUME_RESPONDER = 0x0, 12898 MLX5_RESUME_VHCA_IN_OP_MOD_RESUME_INITIATOR = 0x1, 12899 }; 12900 12901 struct mlx5_ifc_resume_vhca_in_bits { 12902 u8 opcode[0x10]; 12903 u8 uid[0x10]; 12904 12905 u8 reserved_at_20[0x10]; 12906 u8 op_mod[0x10]; 12907 12908 u8 reserved_at_40[0x10]; 12909 u8 vhca_id[0x10]; 12910 12911 u8 reserved_at_60[0x20]; 12912 }; 12913 12914 struct mlx5_ifc_resume_vhca_out_bits { 12915 u8 status[0x8]; 12916 u8 reserved_at_8[0x18]; 12917 12918 u8 syndrome[0x20]; 12919 12920 u8 reserved_at_40[0x40]; 12921 }; 12922 12923 struct mlx5_ifc_query_vhca_migration_state_in_bits { 12924 u8 opcode[0x10]; 12925 u8 uid[0x10]; 12926 12927 u8 reserved_at_20[0x10]; 12928 u8 op_mod[0x10]; 12929 12930 u8 incremental[0x1]; 12931 u8 chunk[0x1]; 12932 u8 reserved_at_42[0xe]; 12933 u8 vhca_id[0x10]; 12934 12935 u8 reserved_at_60[0x20]; 12936 }; 12937 12938 struct mlx5_ifc_query_vhca_migration_state_out_bits { 12939 u8 status[0x8]; 12940 u8 reserved_at_8[0x18]; 12941 12942 u8 syndrome[0x20]; 12943 12944 u8 reserved_at_40[0x40]; 12945 12946 u8 required_umem_size[0x20]; 12947 12948 u8 reserved_at_a0[0x20]; 12949 12950 u8 remaining_total_size[0x40]; 12951 12952 u8 reserved_at_100[0x100]; 12953 }; 12954 12955 struct mlx5_ifc_save_vhca_state_in_bits { 12956 u8 opcode[0x10]; 12957 u8 uid[0x10]; 12958 12959 u8 reserved_at_20[0x10]; 12960 u8 op_mod[0x10]; 12961 12962 u8 incremental[0x1]; 12963 u8 set_track[0x1]; 12964 u8 reserved_at_42[0xe]; 12965 u8 vhca_id[0x10]; 12966 12967 u8 reserved_at_60[0x20]; 12968 12969 u8 va[0x40]; 12970 12971 u8 mkey[0x20]; 12972 12973 u8 size[0x20]; 12974 }; 12975 12976 struct mlx5_ifc_save_vhca_state_out_bits { 12977 u8 status[0x8]; 12978 u8 reserved_at_8[0x18]; 12979 12980 u8 syndrome[0x20]; 12981 12982 u8 actual_image_size[0x20]; 12983 12984 u8 next_required_umem_size[0x20]; 12985 }; 12986 12987 struct mlx5_ifc_load_vhca_state_in_bits { 12988 u8 opcode[0x10]; 12989 u8 uid[0x10]; 12990 12991 u8 reserved_at_20[0x10]; 12992 u8 op_mod[0x10]; 12993 12994 u8 reserved_at_40[0x10]; 12995 u8 vhca_id[0x10]; 12996 12997 u8 reserved_at_60[0x20]; 12998 12999 u8 va[0x40]; 13000 13001 u8 mkey[0x20]; 13002 13003 u8 size[0x20]; 13004 }; 13005 13006 struct mlx5_ifc_load_vhca_state_out_bits { 13007 u8 status[0x8]; 13008 u8 reserved_at_8[0x18]; 13009 13010 u8 syndrome[0x20]; 13011 13012 u8 reserved_at_40[0x40]; 13013 }; 13014 13015 struct mlx5_ifc_adv_virtualization_cap_bits { 13016 u8 reserved_at_0[0x3]; 13017 u8 pg_track_log_max_num[0x5]; 13018 u8 pg_track_max_num_range[0x8]; 13019 u8 pg_track_log_min_addr_space[0x8]; 13020 u8 pg_track_log_max_addr_space[0x8]; 13021 13022 u8 reserved_at_20[0x3]; 13023 u8 pg_track_log_min_msg_size[0x5]; 13024 u8 reserved_at_28[0x3]; 13025 u8 pg_track_log_max_msg_size[0x5]; 13026 u8 reserved_at_30[0x3]; 13027 u8 pg_track_log_min_page_size[0x5]; 13028 u8 reserved_at_38[0x3]; 13029 u8 pg_track_log_max_page_size[0x5]; 13030 13031 u8 reserved_at_40[0x7c0]; 13032 }; 13033 13034 struct mlx5_ifc_page_track_report_entry_bits { 13035 u8 dirty_address_high[0x20]; 13036 13037 u8 dirty_address_low[0x20]; 13038 }; 13039 13040 enum { 13041 MLX5_PAGE_TRACK_STATE_TRACKING, 13042 MLX5_PAGE_TRACK_STATE_REPORTING, 13043 MLX5_PAGE_TRACK_STATE_ERROR, 13044 }; 13045 13046 struct mlx5_ifc_page_track_range_bits { 13047 u8 start_address[0x40]; 13048 13049 u8 length[0x40]; 13050 }; 13051 13052 struct mlx5_ifc_page_track_bits { 13053 u8 modify_field_select[0x40]; 13054 13055 u8 reserved_at_40[0x10]; 13056 u8 vhca_id[0x10]; 13057 13058 u8 reserved_at_60[0x20]; 13059 13060 u8 state[0x4]; 13061 u8 track_type[0x4]; 13062 u8 log_addr_space_size[0x8]; 13063 u8 reserved_at_90[0x3]; 13064 u8 log_page_size[0x5]; 13065 u8 reserved_at_98[0x3]; 13066 u8 log_msg_size[0x5]; 13067 13068 u8 reserved_at_a0[0x8]; 13069 u8 reporting_qpn[0x18]; 13070 13071 u8 reserved_at_c0[0x18]; 13072 u8 num_ranges[0x8]; 13073 13074 u8 reserved_at_e0[0x20]; 13075 13076 u8 range_start_address[0x40]; 13077 13078 u8 length[0x40]; 13079 13080 struct mlx5_ifc_page_track_range_bits track_range[0]; 13081 }; 13082 13083 struct mlx5_ifc_create_page_track_obj_in_bits { 13084 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 13085 struct mlx5_ifc_page_track_bits obj_context; 13086 }; 13087 13088 struct mlx5_ifc_modify_page_track_obj_in_bits { 13089 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 13090 struct mlx5_ifc_page_track_bits obj_context; 13091 }; 13092 13093 struct mlx5_ifc_query_page_track_obj_out_bits { 13094 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 13095 struct mlx5_ifc_page_track_bits obj_context; 13096 }; 13097 13098 struct mlx5_ifc_msecq_reg_bits { 13099 u8 reserved_at_0[0x20]; 13100 13101 u8 reserved_at_20[0x12]; 13102 u8 network_option[0x2]; 13103 u8 local_ssm_code[0x4]; 13104 u8 local_enhanced_ssm_code[0x8]; 13105 13106 u8 local_clock_identity[0x40]; 13107 13108 u8 reserved_at_80[0x180]; 13109 }; 13110 13111 enum { 13112 MLX5_MSEES_FIELD_SELECT_ENABLE = BIT(0), 13113 MLX5_MSEES_FIELD_SELECT_ADMIN_STATUS = BIT(1), 13114 MLX5_MSEES_FIELD_SELECT_ADMIN_FREQ_MEASURE = BIT(2), 13115 }; 13116 13117 enum mlx5_msees_admin_status { 13118 MLX5_MSEES_ADMIN_STATUS_FREE_RUNNING = 0x0, 13119 MLX5_MSEES_ADMIN_STATUS_TRACK = 0x1, 13120 }; 13121 13122 enum mlx5_msees_oper_status { 13123 MLX5_MSEES_OPER_STATUS_FREE_RUNNING = 0x0, 13124 MLX5_MSEES_OPER_STATUS_SELF_TRACK = 0x1, 13125 MLX5_MSEES_OPER_STATUS_OTHER_TRACK = 0x2, 13126 MLX5_MSEES_OPER_STATUS_HOLDOVER = 0x3, 13127 MLX5_MSEES_OPER_STATUS_FAIL_HOLDOVER = 0x4, 13128 MLX5_MSEES_OPER_STATUS_FAIL_FREE_RUNNING = 0x5, 13129 }; 13130 13131 enum mlx5_msees_failure_reason { 13132 MLX5_MSEES_FAILURE_REASON_UNDEFINED_ERROR = 0x0, 13133 MLX5_MSEES_FAILURE_REASON_PORT_DOWN = 0x1, 13134 MLX5_MSEES_FAILURE_REASON_TOO_HIGH_FREQUENCY_DIFF = 0x2, 13135 MLX5_MSEES_FAILURE_REASON_NET_SYNCHRONIZER_DEVICE_ERROR = 0x3, 13136 MLX5_MSEES_FAILURE_REASON_LACK_OF_RESOURCES = 0x4, 13137 }; 13138 13139 struct mlx5_ifc_msees_reg_bits { 13140 u8 reserved_at_0[0x8]; 13141 u8 local_port[0x8]; 13142 u8 pnat[0x2]; 13143 u8 lp_msb[0x2]; 13144 u8 reserved_at_14[0xc]; 13145 13146 u8 field_select[0x20]; 13147 13148 u8 admin_status[0x4]; 13149 u8 oper_status[0x4]; 13150 u8 ho_acq[0x1]; 13151 u8 reserved_at_49[0xc]; 13152 u8 admin_freq_measure[0x1]; 13153 u8 oper_freq_measure[0x1]; 13154 u8 failure_reason[0x9]; 13155 13156 u8 frequency_diff[0x20]; 13157 13158 u8 reserved_at_80[0x180]; 13159 }; 13160 13161 #endif /* MLX5_IFC_H */ 13162