1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 #ifndef MLX5_IFC_H 33 #define MLX5_IFC_H 34 35 #include "mlx5_ifc_fpga.h" 36 37 enum { 38 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0, 39 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1, 40 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2, 41 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3, 42 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13, 43 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14, 44 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c, 45 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d, 46 MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4, 47 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5, 48 MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED = 0x7, 49 MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT = 0xc, 50 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10, 51 MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR = 0x11, 52 MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR = 0x12, 53 MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR = 0x8, 54 MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE = 0x9, 55 MLX5_EVENT_TYPE_CODING_GPIO_EVENT = 0x15, 56 MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19, 57 MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a, 58 MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT = 0x1b, 59 MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT = 0x1f, 60 MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa, 61 MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb, 62 MLX5_EVENT_TYPE_CODING_FPGA_ERROR = 0x20, 63 MLX5_EVENT_TYPE_CODING_FPGA_QP_ERROR = 0x21 64 }; 65 66 enum { 67 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0, 68 MLX5_SET_HCA_CAP_OP_MOD_ETHERNET_OFFLOADS = 0x1, 69 MLX5_SET_HCA_CAP_OP_MOD_ODP = 0x2, 70 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3, 71 MLX5_SET_HCA_CAP_OP_MOD_ROCE = 0x4, 72 MLX5_SET_HCA_CAP_OP_MOD_IPSEC = 0x15, 73 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE2 = 0x20, 74 MLX5_SET_HCA_CAP_OP_MOD_PORT_SELECTION = 0x25, 75 }; 76 77 enum { 78 MLX5_SHARED_RESOURCE_UID = 0xffff, 79 }; 80 81 enum { 82 MLX5_OBJ_TYPE_SW_ICM = 0x0008, 83 MLX5_OBJ_TYPE_GENEVE_TLV_OPT = 0x000b, 84 MLX5_OBJ_TYPE_VIRTIO_NET_Q = 0x000d, 85 MLX5_OBJ_TYPE_VIRTIO_Q_COUNTERS = 0x001c, 86 MLX5_OBJ_TYPE_MATCH_DEFINER = 0x0018, 87 MLX5_OBJ_TYPE_HEADER_MODIFY_ARGUMENT = 0x23, 88 MLX5_OBJ_TYPE_STC = 0x0040, 89 MLX5_OBJ_TYPE_RTC = 0x0041, 90 MLX5_OBJ_TYPE_STE = 0x0042, 91 MLX5_OBJ_TYPE_MODIFY_HDR_PATTERN = 0x0043, 92 MLX5_OBJ_TYPE_PAGE_TRACK = 0x46, 93 MLX5_OBJ_TYPE_MKEY = 0xff01, 94 MLX5_OBJ_TYPE_QP = 0xff02, 95 MLX5_OBJ_TYPE_PSV = 0xff03, 96 MLX5_OBJ_TYPE_RMP = 0xff04, 97 MLX5_OBJ_TYPE_XRC_SRQ = 0xff05, 98 MLX5_OBJ_TYPE_RQ = 0xff06, 99 MLX5_OBJ_TYPE_SQ = 0xff07, 100 MLX5_OBJ_TYPE_TIR = 0xff08, 101 MLX5_OBJ_TYPE_TIS = 0xff09, 102 MLX5_OBJ_TYPE_DCT = 0xff0a, 103 MLX5_OBJ_TYPE_XRQ = 0xff0b, 104 MLX5_OBJ_TYPE_RQT = 0xff0e, 105 MLX5_OBJ_TYPE_FLOW_COUNTER = 0xff0f, 106 MLX5_OBJ_TYPE_CQ = 0xff10, 107 MLX5_OBJ_TYPE_FT_ALIAS = 0xff15, 108 }; 109 110 enum { 111 MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM = (1ULL << MLX5_OBJ_TYPE_SW_ICM), 112 MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT = (1ULL << 11), 113 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q = (1ULL << 13), 114 MLX5_GENERAL_OBJ_TYPES_CAP_HEADER_MODIFY_ARGUMENT = 115 (1ULL << MLX5_OBJ_TYPE_HEADER_MODIFY_ARGUMENT), 116 MLX5_GENERAL_OBJ_TYPES_CAP_MACSEC_OFFLOAD = (1ULL << 39), 117 }; 118 119 enum { 120 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100, 121 MLX5_CMD_OP_QUERY_ADAPTER = 0x101, 122 MLX5_CMD_OP_INIT_HCA = 0x102, 123 MLX5_CMD_OP_TEARDOWN_HCA = 0x103, 124 MLX5_CMD_OP_ENABLE_HCA = 0x104, 125 MLX5_CMD_OP_DISABLE_HCA = 0x105, 126 MLX5_CMD_OP_QUERY_PAGES = 0x107, 127 MLX5_CMD_OP_MANAGE_PAGES = 0x108, 128 MLX5_CMD_OP_SET_HCA_CAP = 0x109, 129 MLX5_CMD_OP_QUERY_ISSI = 0x10a, 130 MLX5_CMD_OP_SET_ISSI = 0x10b, 131 MLX5_CMD_OP_SET_DRIVER_VERSION = 0x10d, 132 MLX5_CMD_OP_QUERY_SF_PARTITION = 0x111, 133 MLX5_CMD_OP_ALLOC_SF = 0x113, 134 MLX5_CMD_OP_DEALLOC_SF = 0x114, 135 MLX5_CMD_OP_SUSPEND_VHCA = 0x115, 136 MLX5_CMD_OP_RESUME_VHCA = 0x116, 137 MLX5_CMD_OP_QUERY_VHCA_MIGRATION_STATE = 0x117, 138 MLX5_CMD_OP_SAVE_VHCA_STATE = 0x118, 139 MLX5_CMD_OP_LOAD_VHCA_STATE = 0x119, 140 MLX5_CMD_OP_CREATE_MKEY = 0x200, 141 MLX5_CMD_OP_QUERY_MKEY = 0x201, 142 MLX5_CMD_OP_DESTROY_MKEY = 0x202, 143 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203, 144 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204, 145 MLX5_CMD_OP_ALLOC_MEMIC = 0x205, 146 MLX5_CMD_OP_DEALLOC_MEMIC = 0x206, 147 MLX5_CMD_OP_MODIFY_MEMIC = 0x207, 148 MLX5_CMD_OP_CREATE_EQ = 0x301, 149 MLX5_CMD_OP_DESTROY_EQ = 0x302, 150 MLX5_CMD_OP_QUERY_EQ = 0x303, 151 MLX5_CMD_OP_GEN_EQE = 0x304, 152 MLX5_CMD_OP_CREATE_CQ = 0x400, 153 MLX5_CMD_OP_DESTROY_CQ = 0x401, 154 MLX5_CMD_OP_QUERY_CQ = 0x402, 155 MLX5_CMD_OP_MODIFY_CQ = 0x403, 156 MLX5_CMD_OP_CREATE_QP = 0x500, 157 MLX5_CMD_OP_DESTROY_QP = 0x501, 158 MLX5_CMD_OP_RST2INIT_QP = 0x502, 159 MLX5_CMD_OP_INIT2RTR_QP = 0x503, 160 MLX5_CMD_OP_RTR2RTS_QP = 0x504, 161 MLX5_CMD_OP_RTS2RTS_QP = 0x505, 162 MLX5_CMD_OP_SQERR2RTS_QP = 0x506, 163 MLX5_CMD_OP_2ERR_QP = 0x507, 164 MLX5_CMD_OP_2RST_QP = 0x50a, 165 MLX5_CMD_OP_QUERY_QP = 0x50b, 166 MLX5_CMD_OP_SQD_RTS_QP = 0x50c, 167 MLX5_CMD_OP_INIT2INIT_QP = 0x50e, 168 MLX5_CMD_OP_CREATE_PSV = 0x600, 169 MLX5_CMD_OP_DESTROY_PSV = 0x601, 170 MLX5_CMD_OP_CREATE_SRQ = 0x700, 171 MLX5_CMD_OP_DESTROY_SRQ = 0x701, 172 MLX5_CMD_OP_QUERY_SRQ = 0x702, 173 MLX5_CMD_OP_ARM_RQ = 0x703, 174 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705, 175 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706, 176 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707, 177 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708, 178 MLX5_CMD_OP_CREATE_DCT = 0x710, 179 MLX5_CMD_OP_DESTROY_DCT = 0x711, 180 MLX5_CMD_OP_DRAIN_DCT = 0x712, 181 MLX5_CMD_OP_QUERY_DCT = 0x713, 182 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714, 183 MLX5_CMD_OP_CREATE_XRQ = 0x717, 184 MLX5_CMD_OP_DESTROY_XRQ = 0x718, 185 MLX5_CMD_OP_QUERY_XRQ = 0x719, 186 MLX5_CMD_OP_ARM_XRQ = 0x71a, 187 MLX5_CMD_OP_QUERY_XRQ_DC_PARAMS_ENTRY = 0x725, 188 MLX5_CMD_OP_SET_XRQ_DC_PARAMS_ENTRY = 0x726, 189 MLX5_CMD_OP_QUERY_XRQ_ERROR_PARAMS = 0x727, 190 MLX5_CMD_OP_RELEASE_XRQ_ERROR = 0x729, 191 MLX5_CMD_OP_MODIFY_XRQ = 0x72a, 192 MLX5_CMD_OP_QUERY_ESW_FUNCTIONS = 0x740, 193 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750, 194 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751, 195 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752, 196 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753, 197 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754, 198 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755, 199 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760, 200 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761, 201 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762, 202 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763, 203 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764, 204 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765, 205 MLX5_CMD_OP_QUERY_VNIC_ENV = 0x76f, 206 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770, 207 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771, 208 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772, 209 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773, 210 MLX5_CMD_OP_SET_MONITOR_COUNTER = 0x774, 211 MLX5_CMD_OP_ARM_MONITOR_COUNTER = 0x775, 212 MLX5_CMD_OP_SET_PP_RATE_LIMIT = 0x780, 213 MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781, 214 MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT = 0x782, 215 MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT = 0x783, 216 MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT = 0x784, 217 MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT = 0x785, 218 MLX5_CMD_OP_CREATE_QOS_PARA_VPORT = 0x786, 219 MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT = 0x787, 220 MLX5_CMD_OP_ALLOC_PD = 0x800, 221 MLX5_CMD_OP_DEALLOC_PD = 0x801, 222 MLX5_CMD_OP_ALLOC_UAR = 0x802, 223 MLX5_CMD_OP_DEALLOC_UAR = 0x803, 224 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804, 225 MLX5_CMD_OP_ACCESS_REG = 0x805, 226 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806, 227 MLX5_CMD_OP_DETACH_FROM_MCG = 0x807, 228 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a, 229 MLX5_CMD_OP_MAD_IFC = 0x50d, 230 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b, 231 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c, 232 MLX5_CMD_OP_NOP = 0x80d, 233 MLX5_CMD_OP_ALLOC_XRCD = 0x80e, 234 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f, 235 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816, 236 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817, 237 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822, 238 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823, 239 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824, 240 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825, 241 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826, 242 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827, 243 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828, 244 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829, 245 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a, 246 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b, 247 MLX5_CMD_OP_SET_WOL_ROL = 0x830, 248 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831, 249 MLX5_CMD_OP_CREATE_LAG = 0x840, 250 MLX5_CMD_OP_MODIFY_LAG = 0x841, 251 MLX5_CMD_OP_QUERY_LAG = 0x842, 252 MLX5_CMD_OP_DESTROY_LAG = 0x843, 253 MLX5_CMD_OP_CREATE_VPORT_LAG = 0x844, 254 MLX5_CMD_OP_DESTROY_VPORT_LAG = 0x845, 255 MLX5_CMD_OP_CREATE_TIR = 0x900, 256 MLX5_CMD_OP_MODIFY_TIR = 0x901, 257 MLX5_CMD_OP_DESTROY_TIR = 0x902, 258 MLX5_CMD_OP_QUERY_TIR = 0x903, 259 MLX5_CMD_OP_CREATE_SQ = 0x904, 260 MLX5_CMD_OP_MODIFY_SQ = 0x905, 261 MLX5_CMD_OP_DESTROY_SQ = 0x906, 262 MLX5_CMD_OP_QUERY_SQ = 0x907, 263 MLX5_CMD_OP_CREATE_RQ = 0x908, 264 MLX5_CMD_OP_MODIFY_RQ = 0x909, 265 MLX5_CMD_OP_SET_DELAY_DROP_PARAMS = 0x910, 266 MLX5_CMD_OP_DESTROY_RQ = 0x90a, 267 MLX5_CMD_OP_QUERY_RQ = 0x90b, 268 MLX5_CMD_OP_CREATE_RMP = 0x90c, 269 MLX5_CMD_OP_MODIFY_RMP = 0x90d, 270 MLX5_CMD_OP_DESTROY_RMP = 0x90e, 271 MLX5_CMD_OP_QUERY_RMP = 0x90f, 272 MLX5_CMD_OP_CREATE_TIS = 0x912, 273 MLX5_CMD_OP_MODIFY_TIS = 0x913, 274 MLX5_CMD_OP_DESTROY_TIS = 0x914, 275 MLX5_CMD_OP_QUERY_TIS = 0x915, 276 MLX5_CMD_OP_CREATE_RQT = 0x916, 277 MLX5_CMD_OP_MODIFY_RQT = 0x917, 278 MLX5_CMD_OP_DESTROY_RQT = 0x918, 279 MLX5_CMD_OP_QUERY_RQT = 0x919, 280 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f, 281 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930, 282 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931, 283 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932, 284 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933, 285 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934, 286 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935, 287 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936, 288 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937, 289 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938, 290 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939, 291 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a, 292 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b, 293 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c, 294 MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT = 0x93d, 295 MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT = 0x93e, 296 MLX5_CMD_OP_QUERY_PACKET_REFORMAT_CONTEXT = 0x93f, 297 MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT = 0x940, 298 MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941, 299 MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT = 0x942, 300 MLX5_CMD_OP_FPGA_CREATE_QP = 0x960, 301 MLX5_CMD_OP_FPGA_MODIFY_QP = 0x961, 302 MLX5_CMD_OP_FPGA_QUERY_QP = 0x962, 303 MLX5_CMD_OP_FPGA_DESTROY_QP = 0x963, 304 MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS = 0x964, 305 MLX5_CMD_OP_CREATE_GENERAL_OBJECT = 0xa00, 306 MLX5_CMD_OP_MODIFY_GENERAL_OBJECT = 0xa01, 307 MLX5_CMD_OP_QUERY_GENERAL_OBJECT = 0xa02, 308 MLX5_CMD_OP_DESTROY_GENERAL_OBJECT = 0xa03, 309 MLX5_CMD_OP_CREATE_UCTX = 0xa04, 310 MLX5_CMD_OP_DESTROY_UCTX = 0xa06, 311 MLX5_CMD_OP_CREATE_UMEM = 0xa08, 312 MLX5_CMD_OP_DESTROY_UMEM = 0xa0a, 313 MLX5_CMD_OP_SYNC_STEERING = 0xb00, 314 MLX5_CMD_OP_QUERY_VHCA_STATE = 0xb0d, 315 MLX5_CMD_OP_MODIFY_VHCA_STATE = 0xb0e, 316 MLX5_CMD_OP_SYNC_CRYPTO = 0xb12, 317 MLX5_CMD_OP_ALLOW_OTHER_VHCA_ACCESS = 0xb16, 318 MLX5_CMD_OP_GENERATE_WQE = 0xb17, 319 MLX5_CMD_OPCODE_QUERY_VUID = 0xb22, 320 MLX5_CMD_OP_MAX 321 }; 322 323 /* Valid range for general commands that don't work over an object */ 324 enum { 325 MLX5_CMD_OP_GENERAL_START = 0xb00, 326 MLX5_CMD_OP_GENERAL_END = 0xd00, 327 }; 328 329 enum { 330 MLX5_FT_NIC_RX_2_NIC_RX_RDMA = BIT(0), 331 MLX5_FT_NIC_TX_RDMA_2_NIC_TX = BIT(1), 332 }; 333 334 enum { 335 MLX5_CMD_OP_MOD_UPDATE_HEADER_MODIFY_ARGUMENT = 0x1, 336 }; 337 338 struct mlx5_ifc_flow_table_fields_supported_bits { 339 u8 outer_dmac[0x1]; 340 u8 outer_smac[0x1]; 341 u8 outer_ether_type[0x1]; 342 u8 outer_ip_version[0x1]; 343 u8 outer_first_prio[0x1]; 344 u8 outer_first_cfi[0x1]; 345 u8 outer_first_vid[0x1]; 346 u8 outer_ipv4_ttl[0x1]; 347 u8 outer_second_prio[0x1]; 348 u8 outer_second_cfi[0x1]; 349 u8 outer_second_vid[0x1]; 350 u8 reserved_at_b[0x1]; 351 u8 outer_sip[0x1]; 352 u8 outer_dip[0x1]; 353 u8 outer_frag[0x1]; 354 u8 outer_ip_protocol[0x1]; 355 u8 outer_ip_ecn[0x1]; 356 u8 outer_ip_dscp[0x1]; 357 u8 outer_udp_sport[0x1]; 358 u8 outer_udp_dport[0x1]; 359 u8 outer_tcp_sport[0x1]; 360 u8 outer_tcp_dport[0x1]; 361 u8 outer_tcp_flags[0x1]; 362 u8 outer_gre_protocol[0x1]; 363 u8 outer_gre_key[0x1]; 364 u8 outer_vxlan_vni[0x1]; 365 u8 outer_geneve_vni[0x1]; 366 u8 outer_geneve_oam[0x1]; 367 u8 outer_geneve_protocol_type[0x1]; 368 u8 outer_geneve_opt_len[0x1]; 369 u8 source_vhca_port[0x1]; 370 u8 source_eswitch_port[0x1]; 371 372 u8 inner_dmac[0x1]; 373 u8 inner_smac[0x1]; 374 u8 inner_ether_type[0x1]; 375 u8 inner_ip_version[0x1]; 376 u8 inner_first_prio[0x1]; 377 u8 inner_first_cfi[0x1]; 378 u8 inner_first_vid[0x1]; 379 u8 reserved_at_27[0x1]; 380 u8 inner_second_prio[0x1]; 381 u8 inner_second_cfi[0x1]; 382 u8 inner_second_vid[0x1]; 383 u8 reserved_at_2b[0x1]; 384 u8 inner_sip[0x1]; 385 u8 inner_dip[0x1]; 386 u8 inner_frag[0x1]; 387 u8 inner_ip_protocol[0x1]; 388 u8 inner_ip_ecn[0x1]; 389 u8 inner_ip_dscp[0x1]; 390 u8 inner_udp_sport[0x1]; 391 u8 inner_udp_dport[0x1]; 392 u8 inner_tcp_sport[0x1]; 393 u8 inner_tcp_dport[0x1]; 394 u8 inner_tcp_flags[0x1]; 395 u8 reserved_at_37[0x9]; 396 397 u8 geneve_tlv_option_0_data[0x1]; 398 u8 geneve_tlv_option_0_exist[0x1]; 399 u8 reserved_at_42[0x3]; 400 u8 outer_first_mpls_over_udp[0x4]; 401 u8 outer_first_mpls_over_gre[0x4]; 402 u8 inner_first_mpls[0x4]; 403 u8 outer_first_mpls[0x4]; 404 u8 reserved_at_55[0x2]; 405 u8 outer_esp_spi[0x1]; 406 u8 reserved_at_58[0x2]; 407 u8 bth_dst_qp[0x1]; 408 u8 reserved_at_5b[0x5]; 409 410 u8 reserved_at_60[0x18]; 411 u8 metadata_reg_c_7[0x1]; 412 u8 metadata_reg_c_6[0x1]; 413 u8 metadata_reg_c_5[0x1]; 414 u8 metadata_reg_c_4[0x1]; 415 u8 metadata_reg_c_3[0x1]; 416 u8 metadata_reg_c_2[0x1]; 417 u8 metadata_reg_c_1[0x1]; 418 u8 metadata_reg_c_0[0x1]; 419 }; 420 421 /* Table 2170 - Flow Table Fields Supported 2 Format */ 422 struct mlx5_ifc_flow_table_fields_supported_2_bits { 423 u8 reserved_at_0[0x2]; 424 u8 inner_l4_type[0x1]; 425 u8 outer_l4_type[0x1]; 426 u8 reserved_at_4[0xa]; 427 u8 bth_opcode[0x1]; 428 u8 reserved_at_f[0x1]; 429 u8 tunnel_header_0_1[0x1]; 430 u8 reserved_at_11[0xf]; 431 432 u8 reserved_at_20[0x60]; 433 }; 434 435 struct mlx5_ifc_flow_table_prop_layout_bits { 436 u8 ft_support[0x1]; 437 u8 reserved_at_1[0x1]; 438 u8 flow_counter[0x1]; 439 u8 flow_modify_en[0x1]; 440 u8 modify_root[0x1]; 441 u8 identified_miss_table_mode[0x1]; 442 u8 flow_table_modify[0x1]; 443 u8 reformat[0x1]; 444 u8 decap[0x1]; 445 u8 reset_root_to_default[0x1]; 446 u8 pop_vlan[0x1]; 447 u8 push_vlan[0x1]; 448 u8 reserved_at_c[0x1]; 449 u8 pop_vlan_2[0x1]; 450 u8 push_vlan_2[0x1]; 451 u8 reformat_and_vlan_action[0x1]; 452 u8 reserved_at_10[0x1]; 453 u8 sw_owner[0x1]; 454 u8 reformat_l3_tunnel_to_l2[0x1]; 455 u8 reformat_l2_to_l3_tunnel[0x1]; 456 u8 reformat_and_modify_action[0x1]; 457 u8 ignore_flow_level[0x1]; 458 u8 reserved_at_16[0x1]; 459 u8 table_miss_action_domain[0x1]; 460 u8 termination_table[0x1]; 461 u8 reformat_and_fwd_to_table[0x1]; 462 u8 reserved_at_1a[0x2]; 463 u8 ipsec_encrypt[0x1]; 464 u8 ipsec_decrypt[0x1]; 465 u8 sw_owner_v2[0x1]; 466 u8 reserved_at_1f[0x1]; 467 468 u8 termination_table_raw_traffic[0x1]; 469 u8 reserved_at_21[0x1]; 470 u8 log_max_ft_size[0x6]; 471 u8 log_max_modify_header_context[0x8]; 472 u8 max_modify_header_actions[0x8]; 473 u8 max_ft_level[0x8]; 474 475 u8 reformat_add_esp_trasport[0x1]; 476 u8 reformat_l2_to_l3_esp_tunnel[0x1]; 477 u8 reformat_add_esp_transport_over_udp[0x1]; 478 u8 reformat_del_esp_trasport[0x1]; 479 u8 reformat_l3_esp_tunnel_to_l2[0x1]; 480 u8 reformat_del_esp_transport_over_udp[0x1]; 481 u8 execute_aso[0x1]; 482 u8 reserved_at_47[0x19]; 483 484 u8 reserved_at_60[0x2]; 485 u8 reformat_insert[0x1]; 486 u8 reformat_remove[0x1]; 487 u8 macsec_encrypt[0x1]; 488 u8 macsec_decrypt[0x1]; 489 u8 reserved_at_66[0x2]; 490 u8 reformat_add_macsec[0x1]; 491 u8 reformat_remove_macsec[0x1]; 492 u8 reparse[0x1]; 493 u8 reserved_at_6b[0x1]; 494 u8 cross_vhca_object[0x1]; 495 u8 reformat_l2_to_l3_audp_tunnel[0x1]; 496 u8 reformat_l3_audp_tunnel_to_l2[0x1]; 497 u8 ignore_flow_level_rtc_valid[0x1]; 498 u8 reserved_at_70[0x8]; 499 u8 log_max_ft_num[0x8]; 500 501 u8 reserved_at_80[0x10]; 502 u8 log_max_flow_counter[0x8]; 503 u8 log_max_destination[0x8]; 504 505 u8 reserved_at_a0[0x18]; 506 u8 log_max_flow[0x8]; 507 508 u8 reserved_at_c0[0x40]; 509 510 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support; 511 512 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support; 513 }; 514 515 struct mlx5_ifc_odp_per_transport_service_cap_bits { 516 u8 send[0x1]; 517 u8 receive[0x1]; 518 u8 write[0x1]; 519 u8 read[0x1]; 520 u8 atomic[0x1]; 521 u8 srq_receive[0x1]; 522 u8 reserved_at_6[0x1a]; 523 }; 524 525 struct mlx5_ifc_ipv4_layout_bits { 526 u8 reserved_at_0[0x60]; 527 528 u8 ipv4[0x20]; 529 }; 530 531 struct mlx5_ifc_ipv6_layout_bits { 532 u8 ipv6[16][0x8]; 533 }; 534 535 struct mlx5_ifc_ipv6_simple_layout_bits { 536 u8 ipv6_127_96[0x20]; 537 u8 ipv6_95_64[0x20]; 538 u8 ipv6_63_32[0x20]; 539 u8 ipv6_31_0[0x20]; 540 }; 541 542 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits { 543 struct mlx5_ifc_ipv6_simple_layout_bits ipv6_simple_layout; 544 struct mlx5_ifc_ipv6_layout_bits ipv6_layout; 545 struct mlx5_ifc_ipv4_layout_bits ipv4_layout; 546 u8 reserved_at_0[0x80]; 547 }; 548 549 enum { 550 MLX5_PACKET_L4_TYPE_NONE, 551 MLX5_PACKET_L4_TYPE_TCP, 552 MLX5_PACKET_L4_TYPE_UDP, 553 }; 554 555 struct mlx5_ifc_fte_match_set_lyr_2_4_bits { 556 u8 smac_47_16[0x20]; 557 558 u8 smac_15_0[0x10]; 559 u8 ethertype[0x10]; 560 561 u8 dmac_47_16[0x20]; 562 563 u8 dmac_15_0[0x10]; 564 u8 first_prio[0x3]; 565 u8 first_cfi[0x1]; 566 u8 first_vid[0xc]; 567 568 u8 ip_protocol[0x8]; 569 u8 ip_dscp[0x6]; 570 u8 ip_ecn[0x2]; 571 u8 cvlan_tag[0x1]; 572 u8 svlan_tag[0x1]; 573 u8 frag[0x1]; 574 u8 ip_version[0x4]; 575 u8 tcp_flags[0x9]; 576 577 u8 tcp_sport[0x10]; 578 u8 tcp_dport[0x10]; 579 580 u8 l4_type[0x2]; 581 u8 reserved_at_c2[0xe]; 582 u8 ipv4_ihl[0x4]; 583 u8 reserved_at_c4[0x4]; 584 585 u8 ttl_hoplimit[0x8]; 586 587 u8 udp_sport[0x10]; 588 u8 udp_dport[0x10]; 589 590 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6; 591 592 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6; 593 }; 594 595 struct mlx5_ifc_nvgre_key_bits { 596 u8 hi[0x18]; 597 u8 lo[0x8]; 598 }; 599 600 union mlx5_ifc_gre_key_bits { 601 struct mlx5_ifc_nvgre_key_bits nvgre; 602 u8 key[0x20]; 603 }; 604 605 struct mlx5_ifc_fte_match_set_misc_bits { 606 u8 gre_c_present[0x1]; 607 u8 reserved_at_1[0x1]; 608 u8 gre_k_present[0x1]; 609 u8 gre_s_present[0x1]; 610 u8 source_vhca_port[0x4]; 611 u8 source_sqn[0x18]; 612 613 u8 source_eswitch_owner_vhca_id[0x10]; 614 u8 source_port[0x10]; 615 616 u8 outer_second_prio[0x3]; 617 u8 outer_second_cfi[0x1]; 618 u8 outer_second_vid[0xc]; 619 u8 inner_second_prio[0x3]; 620 u8 inner_second_cfi[0x1]; 621 u8 inner_second_vid[0xc]; 622 623 u8 outer_second_cvlan_tag[0x1]; 624 u8 inner_second_cvlan_tag[0x1]; 625 u8 outer_second_svlan_tag[0x1]; 626 u8 inner_second_svlan_tag[0x1]; 627 u8 reserved_at_64[0xc]; 628 u8 gre_protocol[0x10]; 629 630 union mlx5_ifc_gre_key_bits gre_key; 631 632 u8 vxlan_vni[0x18]; 633 u8 bth_opcode[0x8]; 634 635 u8 geneve_vni[0x18]; 636 u8 reserved_at_d8[0x6]; 637 u8 geneve_tlv_option_0_exist[0x1]; 638 u8 geneve_oam[0x1]; 639 640 u8 reserved_at_e0[0xc]; 641 u8 outer_ipv6_flow_label[0x14]; 642 643 u8 reserved_at_100[0xc]; 644 u8 inner_ipv6_flow_label[0x14]; 645 646 u8 reserved_at_120[0xa]; 647 u8 geneve_opt_len[0x6]; 648 u8 geneve_protocol_type[0x10]; 649 650 u8 reserved_at_140[0x8]; 651 u8 bth_dst_qp[0x18]; 652 u8 inner_esp_spi[0x20]; 653 u8 outer_esp_spi[0x20]; 654 u8 reserved_at_1a0[0x60]; 655 }; 656 657 struct mlx5_ifc_fte_match_mpls_bits { 658 u8 mpls_label[0x14]; 659 u8 mpls_exp[0x3]; 660 u8 mpls_s_bos[0x1]; 661 u8 mpls_ttl[0x8]; 662 }; 663 664 struct mlx5_ifc_fte_match_set_misc2_bits { 665 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls; 666 667 struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls; 668 669 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre; 670 671 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp; 672 673 u8 metadata_reg_c_7[0x20]; 674 675 u8 metadata_reg_c_6[0x20]; 676 677 u8 metadata_reg_c_5[0x20]; 678 679 u8 metadata_reg_c_4[0x20]; 680 681 u8 metadata_reg_c_3[0x20]; 682 683 u8 metadata_reg_c_2[0x20]; 684 685 u8 metadata_reg_c_1[0x20]; 686 687 u8 metadata_reg_c_0[0x20]; 688 689 u8 metadata_reg_a[0x20]; 690 691 u8 reserved_at_1a0[0x8]; 692 693 u8 macsec_syndrome[0x8]; 694 u8 ipsec_syndrome[0x8]; 695 u8 reserved_at_1b8[0x8]; 696 697 u8 reserved_at_1c0[0x40]; 698 }; 699 700 struct mlx5_ifc_fte_match_set_misc3_bits { 701 u8 inner_tcp_seq_num[0x20]; 702 703 u8 outer_tcp_seq_num[0x20]; 704 705 u8 inner_tcp_ack_num[0x20]; 706 707 u8 outer_tcp_ack_num[0x20]; 708 709 u8 reserved_at_80[0x8]; 710 u8 outer_vxlan_gpe_vni[0x18]; 711 712 u8 outer_vxlan_gpe_next_protocol[0x8]; 713 u8 outer_vxlan_gpe_flags[0x8]; 714 u8 reserved_at_b0[0x10]; 715 716 u8 icmp_header_data[0x20]; 717 718 u8 icmpv6_header_data[0x20]; 719 720 u8 icmp_type[0x8]; 721 u8 icmp_code[0x8]; 722 u8 icmpv6_type[0x8]; 723 u8 icmpv6_code[0x8]; 724 725 u8 geneve_tlv_option_0_data[0x20]; 726 727 u8 gtpu_teid[0x20]; 728 729 u8 gtpu_msg_type[0x8]; 730 u8 gtpu_msg_flags[0x8]; 731 u8 reserved_at_170[0x10]; 732 733 u8 gtpu_dw_2[0x20]; 734 735 u8 gtpu_first_ext_dw_0[0x20]; 736 737 u8 gtpu_dw_0[0x20]; 738 739 u8 reserved_at_1e0[0x20]; 740 }; 741 742 struct mlx5_ifc_fte_match_set_misc4_bits { 743 u8 prog_sample_field_value_0[0x20]; 744 745 u8 prog_sample_field_id_0[0x20]; 746 747 u8 prog_sample_field_value_1[0x20]; 748 749 u8 prog_sample_field_id_1[0x20]; 750 751 u8 prog_sample_field_value_2[0x20]; 752 753 u8 prog_sample_field_id_2[0x20]; 754 755 u8 prog_sample_field_value_3[0x20]; 756 757 u8 prog_sample_field_id_3[0x20]; 758 759 u8 reserved_at_100[0x100]; 760 }; 761 762 struct mlx5_ifc_fte_match_set_misc5_bits { 763 u8 macsec_tag_0[0x20]; 764 765 u8 macsec_tag_1[0x20]; 766 767 u8 macsec_tag_2[0x20]; 768 769 u8 macsec_tag_3[0x20]; 770 771 u8 tunnel_header_0[0x20]; 772 773 u8 tunnel_header_1[0x20]; 774 775 u8 tunnel_header_2[0x20]; 776 777 u8 tunnel_header_3[0x20]; 778 779 u8 reserved_at_100[0x100]; 780 }; 781 782 struct mlx5_ifc_cmd_pas_bits { 783 u8 pa_h[0x20]; 784 785 u8 pa_l[0x14]; 786 u8 reserved_at_34[0xc]; 787 }; 788 789 struct mlx5_ifc_uint64_bits { 790 u8 hi[0x20]; 791 792 u8 lo[0x20]; 793 }; 794 795 enum { 796 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0, 797 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7, 798 MLX5_ADS_STAT_RATE_10GBPS = 0x8, 799 MLX5_ADS_STAT_RATE_30GBPS = 0x9, 800 MLX5_ADS_STAT_RATE_5GBPS = 0xa, 801 MLX5_ADS_STAT_RATE_20GBPS = 0xb, 802 MLX5_ADS_STAT_RATE_40GBPS = 0xc, 803 MLX5_ADS_STAT_RATE_60GBPS = 0xd, 804 MLX5_ADS_STAT_RATE_80GBPS = 0xe, 805 MLX5_ADS_STAT_RATE_120GBPS = 0xf, 806 }; 807 808 struct mlx5_ifc_ads_bits { 809 u8 fl[0x1]; 810 u8 free_ar[0x1]; 811 u8 reserved_at_2[0xe]; 812 u8 pkey_index[0x10]; 813 814 u8 plane_index[0x8]; 815 u8 grh[0x1]; 816 u8 mlid[0x7]; 817 u8 rlid[0x10]; 818 819 u8 ack_timeout[0x5]; 820 u8 reserved_at_45[0x3]; 821 u8 src_addr_index[0x8]; 822 u8 reserved_at_50[0x4]; 823 u8 stat_rate[0x4]; 824 u8 hop_limit[0x8]; 825 826 u8 reserved_at_60[0x4]; 827 u8 tclass[0x8]; 828 u8 flow_label[0x14]; 829 830 u8 rgid_rip[16][0x8]; 831 832 u8 reserved_at_100[0x4]; 833 u8 f_dscp[0x1]; 834 u8 f_ecn[0x1]; 835 u8 reserved_at_106[0x1]; 836 u8 f_eth_prio[0x1]; 837 u8 ecn[0x2]; 838 u8 dscp[0x6]; 839 u8 udp_sport[0x10]; 840 841 u8 dei_cfi[0x1]; 842 u8 eth_prio[0x3]; 843 u8 sl[0x4]; 844 u8 vhca_port_num[0x8]; 845 u8 rmac_47_32[0x10]; 846 847 u8 rmac_31_0[0x20]; 848 }; 849 850 struct mlx5_ifc_flow_table_nic_cap_bits { 851 u8 nic_rx_multi_path_tirs[0x1]; 852 u8 nic_rx_multi_path_tirs_fts[0x1]; 853 u8 allow_sniffer_and_nic_rx_shared_tir[0x1]; 854 u8 reserved_at_3[0x4]; 855 u8 sw_owner_reformat_supported[0x1]; 856 u8 reserved_at_8[0x18]; 857 858 u8 encap_general_header[0x1]; 859 u8 reserved_at_21[0xa]; 860 u8 log_max_packet_reformat_context[0x5]; 861 u8 reserved_at_30[0x6]; 862 u8 max_encap_header_size[0xa]; 863 u8 reserved_at_40[0x1c0]; 864 865 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive; 866 867 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_rdma; 868 869 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer; 870 871 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit; 872 873 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_rdma; 874 875 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer; 876 877 u8 reserved_at_e00[0x600]; 878 879 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_receive; 880 881 u8 reserved_at_1480[0x80]; 882 883 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_receive_rdma; 884 885 u8 reserved_at_1580[0x280]; 886 887 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_transmit_rdma; 888 889 u8 reserved_at_1880[0x780]; 890 891 u8 sw_steering_nic_rx_action_drop_icm_address[0x40]; 892 893 u8 sw_steering_nic_tx_action_drop_icm_address[0x40]; 894 895 u8 sw_steering_nic_tx_action_allow_icm_address[0x40]; 896 897 u8 reserved_at_20c0[0x5f40]; 898 }; 899 900 struct mlx5_ifc_port_selection_cap_bits { 901 u8 reserved_at_0[0x10]; 902 u8 port_select_flow_table[0x1]; 903 u8 reserved_at_11[0x1]; 904 u8 port_select_flow_table_bypass[0x1]; 905 u8 reserved_at_13[0xd]; 906 907 u8 reserved_at_20[0x1e0]; 908 909 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_port_selection; 910 911 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_port_selection; 912 913 u8 reserved_at_480[0x7b80]; 914 }; 915 916 enum { 917 MLX5_FDB_TO_VPORT_REG_C_0 = 0x01, 918 MLX5_FDB_TO_VPORT_REG_C_1 = 0x02, 919 MLX5_FDB_TO_VPORT_REG_C_2 = 0x04, 920 MLX5_FDB_TO_VPORT_REG_C_3 = 0x08, 921 MLX5_FDB_TO_VPORT_REG_C_4 = 0x10, 922 MLX5_FDB_TO_VPORT_REG_C_5 = 0x20, 923 MLX5_FDB_TO_VPORT_REG_C_6 = 0x40, 924 MLX5_FDB_TO_VPORT_REG_C_7 = 0x80, 925 }; 926 927 struct mlx5_ifc_flow_table_eswitch_cap_bits { 928 u8 fdb_to_vport_reg_c_id[0x8]; 929 u8 reserved_at_8[0x5]; 930 u8 fdb_uplink_hairpin[0x1]; 931 u8 fdb_multi_path_any_table_limit_regc[0x1]; 932 u8 reserved_at_f[0x1]; 933 u8 fdb_dynamic_tunnel[0x1]; 934 u8 reserved_at_11[0x1]; 935 u8 fdb_multi_path_any_table[0x1]; 936 u8 reserved_at_13[0x2]; 937 u8 fdb_modify_header_fwd_to_table[0x1]; 938 u8 fdb_ipv4_ttl_modify[0x1]; 939 u8 flow_source[0x1]; 940 u8 reserved_at_18[0x2]; 941 u8 multi_fdb_encap[0x1]; 942 u8 egress_acl_forward_to_vport[0x1]; 943 u8 fdb_multi_path_to_table[0x1]; 944 u8 reserved_at_1d[0x3]; 945 946 u8 reserved_at_20[0x1e0]; 947 948 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb; 949 950 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress; 951 952 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress; 953 954 u8 reserved_at_800[0xC00]; 955 956 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_esw_fdb; 957 958 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_bitmask_support_2_esw_fdb; 959 960 u8 reserved_at_1500[0x300]; 961 962 u8 sw_steering_fdb_action_drop_icm_address_rx[0x40]; 963 964 u8 sw_steering_fdb_action_drop_icm_address_tx[0x40]; 965 966 u8 sw_steering_uplink_icm_address_rx[0x40]; 967 968 u8 sw_steering_uplink_icm_address_tx[0x40]; 969 970 u8 reserved_at_1900[0x6700]; 971 }; 972 973 struct mlx5_ifc_wqe_based_flow_table_cap_bits { 974 u8 reserved_at_0[0x3]; 975 u8 log_max_num_ste[0x5]; 976 u8 reserved_at_8[0x3]; 977 u8 log_max_num_stc[0x5]; 978 u8 reserved_at_10[0x3]; 979 u8 log_max_num_rtc[0x5]; 980 u8 reserved_at_18[0x3]; 981 u8 log_max_num_header_modify_pattern[0x5]; 982 983 u8 rtc_hash_split_table[0x1]; 984 u8 rtc_linear_lookup_table[0x1]; 985 u8 reserved_at_22[0x1]; 986 u8 stc_alloc_log_granularity[0x5]; 987 u8 reserved_at_28[0x3]; 988 u8 stc_alloc_log_max[0x5]; 989 u8 reserved_at_30[0x3]; 990 u8 ste_alloc_log_granularity[0x5]; 991 u8 reserved_at_38[0x3]; 992 u8 ste_alloc_log_max[0x5]; 993 994 u8 reserved_at_40[0xb]; 995 u8 rtc_reparse_mode[0x5]; 996 u8 reserved_at_50[0x3]; 997 u8 rtc_index_mode[0x5]; 998 u8 reserved_at_58[0x3]; 999 u8 rtc_log_depth_max[0x5]; 1000 1001 u8 reserved_at_60[0x10]; 1002 u8 ste_format[0x10]; 1003 1004 u8 stc_action_type[0x80]; 1005 1006 u8 header_insert_type[0x10]; 1007 u8 header_remove_type[0x10]; 1008 1009 u8 trivial_match_definer[0x20]; 1010 1011 u8 reserved_at_140[0x1b]; 1012 u8 rtc_max_num_hash_definer_gen_wqe[0x5]; 1013 1014 u8 reserved_at_160[0x18]; 1015 u8 access_index_mode[0x8]; 1016 1017 u8 reserved_at_180[0x10]; 1018 u8 ste_format_gen_wqe[0x10]; 1019 1020 u8 linear_match_definer_reg_c3[0x20]; 1021 1022 u8 fdb_jump_to_tir_stc[0x1]; 1023 u8 reserved_at_1c1[0x1f]; 1024 }; 1025 1026 struct mlx5_ifc_esw_cap_bits { 1027 u8 reserved_at_0[0x1d]; 1028 u8 merged_eswitch[0x1]; 1029 u8 reserved_at_1e[0x2]; 1030 1031 u8 reserved_at_20[0x40]; 1032 1033 u8 esw_manager_vport_number_valid[0x1]; 1034 u8 reserved_at_61[0xf]; 1035 u8 esw_manager_vport_number[0x10]; 1036 1037 u8 reserved_at_80[0x780]; 1038 }; 1039 1040 enum { 1041 MLX5_COUNTER_SOURCE_ESWITCH = 0x0, 1042 MLX5_COUNTER_FLOW_ESWITCH = 0x1, 1043 }; 1044 1045 struct mlx5_ifc_e_switch_cap_bits { 1046 u8 vport_svlan_strip[0x1]; 1047 u8 vport_cvlan_strip[0x1]; 1048 u8 vport_svlan_insert[0x1]; 1049 u8 vport_cvlan_insert_if_not_exist[0x1]; 1050 u8 vport_cvlan_insert_overwrite[0x1]; 1051 u8 reserved_at_5[0x1]; 1052 u8 vport_cvlan_insert_always[0x1]; 1053 u8 esw_shared_ingress_acl[0x1]; 1054 u8 esw_uplink_ingress_acl[0x1]; 1055 u8 root_ft_on_other_esw[0x1]; 1056 u8 reserved_at_a[0xf]; 1057 u8 esw_functions_changed[0x1]; 1058 u8 reserved_at_1a[0x1]; 1059 u8 ecpf_vport_exists[0x1]; 1060 u8 counter_eswitch_affinity[0x1]; 1061 u8 merged_eswitch[0x1]; 1062 u8 nic_vport_node_guid_modify[0x1]; 1063 u8 nic_vport_port_guid_modify[0x1]; 1064 1065 u8 vxlan_encap_decap[0x1]; 1066 u8 nvgre_encap_decap[0x1]; 1067 u8 reserved_at_22[0x1]; 1068 u8 log_max_fdb_encap_uplink[0x5]; 1069 u8 reserved_at_21[0x3]; 1070 u8 log_max_packet_reformat_context[0x5]; 1071 u8 reserved_2b[0x6]; 1072 u8 max_encap_header_size[0xa]; 1073 1074 u8 reserved_at_40[0xb]; 1075 u8 log_max_esw_sf[0x5]; 1076 u8 esw_sf_base_id[0x10]; 1077 1078 u8 reserved_at_60[0x7a0]; 1079 1080 }; 1081 1082 struct mlx5_ifc_qos_cap_bits { 1083 u8 packet_pacing[0x1]; 1084 u8 esw_scheduling[0x1]; 1085 u8 esw_bw_share[0x1]; 1086 u8 esw_rate_limit[0x1]; 1087 u8 reserved_at_4[0x1]; 1088 u8 packet_pacing_burst_bound[0x1]; 1089 u8 packet_pacing_typical_size[0x1]; 1090 u8 reserved_at_7[0x1]; 1091 u8 nic_sq_scheduling[0x1]; 1092 u8 nic_bw_share[0x1]; 1093 u8 nic_rate_limit[0x1]; 1094 u8 packet_pacing_uid[0x1]; 1095 u8 log_esw_max_sched_depth[0x4]; 1096 u8 reserved_at_10[0x10]; 1097 1098 u8 reserved_at_20[0xb]; 1099 u8 log_max_qos_nic_queue_group[0x5]; 1100 u8 reserved_at_30[0x10]; 1101 1102 u8 packet_pacing_max_rate[0x20]; 1103 1104 u8 packet_pacing_min_rate[0x20]; 1105 1106 u8 reserved_at_80[0x10]; 1107 u8 packet_pacing_rate_table_size[0x10]; 1108 1109 u8 esw_element_type[0x10]; 1110 u8 esw_tsar_type[0x10]; 1111 1112 u8 reserved_at_c0[0x10]; 1113 u8 max_qos_para_vport[0x10]; 1114 1115 u8 max_tsar_bw_share[0x20]; 1116 1117 u8 nic_element_type[0x10]; 1118 u8 nic_tsar_type[0x10]; 1119 1120 u8 reserved_at_120[0x3]; 1121 u8 log_meter_aso_granularity[0x5]; 1122 u8 reserved_at_128[0x3]; 1123 u8 log_meter_aso_max_alloc[0x5]; 1124 u8 reserved_at_130[0x3]; 1125 u8 log_max_num_meter_aso[0x5]; 1126 u8 reserved_at_138[0x8]; 1127 1128 u8 reserved_at_140[0x6c0]; 1129 }; 1130 1131 struct mlx5_ifc_debug_cap_bits { 1132 u8 core_dump_general[0x1]; 1133 u8 core_dump_qp[0x1]; 1134 u8 reserved_at_2[0x7]; 1135 u8 resource_dump[0x1]; 1136 u8 reserved_at_a[0x16]; 1137 1138 u8 reserved_at_20[0x2]; 1139 u8 stall_detect[0x1]; 1140 u8 reserved_at_23[0x1d]; 1141 1142 u8 reserved_at_40[0x7c0]; 1143 }; 1144 1145 struct mlx5_ifc_per_protocol_networking_offload_caps_bits { 1146 u8 csum_cap[0x1]; 1147 u8 vlan_cap[0x1]; 1148 u8 lro_cap[0x1]; 1149 u8 lro_psh_flag[0x1]; 1150 u8 lro_time_stamp[0x1]; 1151 u8 reserved_at_5[0x2]; 1152 u8 wqe_vlan_insert[0x1]; 1153 u8 self_lb_en_modifiable[0x1]; 1154 u8 reserved_at_9[0x2]; 1155 u8 max_lso_cap[0x5]; 1156 u8 multi_pkt_send_wqe[0x2]; 1157 u8 wqe_inline_mode[0x2]; 1158 u8 rss_ind_tbl_cap[0x4]; 1159 u8 reg_umr_sq[0x1]; 1160 u8 scatter_fcs[0x1]; 1161 u8 enhanced_multi_pkt_send_wqe[0x1]; 1162 u8 tunnel_lso_const_out_ip_id[0x1]; 1163 u8 tunnel_lro_gre[0x1]; 1164 u8 tunnel_lro_vxlan[0x1]; 1165 u8 tunnel_stateless_gre[0x1]; 1166 u8 tunnel_stateless_vxlan[0x1]; 1167 1168 u8 swp[0x1]; 1169 u8 swp_csum[0x1]; 1170 u8 swp_lso[0x1]; 1171 u8 cqe_checksum_full[0x1]; 1172 u8 tunnel_stateless_geneve_tx[0x1]; 1173 u8 tunnel_stateless_mpls_over_udp[0x1]; 1174 u8 tunnel_stateless_mpls_over_gre[0x1]; 1175 u8 tunnel_stateless_vxlan_gpe[0x1]; 1176 u8 tunnel_stateless_ipv4_over_vxlan[0x1]; 1177 u8 tunnel_stateless_ip_over_ip[0x1]; 1178 u8 insert_trailer[0x1]; 1179 u8 reserved_at_2b[0x1]; 1180 u8 tunnel_stateless_ip_over_ip_rx[0x1]; 1181 u8 tunnel_stateless_ip_over_ip_tx[0x1]; 1182 u8 reserved_at_2e[0x2]; 1183 u8 max_vxlan_udp_ports[0x8]; 1184 u8 swp_csum_l4_partial[0x1]; 1185 u8 reserved_at_39[0x5]; 1186 u8 max_geneve_opt_len[0x1]; 1187 u8 tunnel_stateless_geneve_rx[0x1]; 1188 1189 u8 reserved_at_40[0x10]; 1190 u8 lro_min_mss_size[0x10]; 1191 1192 u8 reserved_at_60[0x120]; 1193 1194 u8 lro_timer_supported_periods[4][0x20]; 1195 1196 u8 reserved_at_200[0x600]; 1197 }; 1198 1199 enum { 1200 MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING = 0x0, 1201 MLX5_TIMESTAMP_FORMAT_CAP_REAL_TIME = 0x1, 1202 MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING_AND_REAL_TIME = 0x2, 1203 }; 1204 1205 struct mlx5_ifc_roce_cap_bits { 1206 u8 roce_apm[0x1]; 1207 u8 reserved_at_1[0x3]; 1208 u8 sw_r_roce_src_udp_port[0x1]; 1209 u8 fl_rc_qp_when_roce_disabled[0x1]; 1210 u8 fl_rc_qp_when_roce_enabled[0x1]; 1211 u8 roce_cc_general[0x1]; 1212 u8 qp_ooo_transmit_default[0x1]; 1213 u8 reserved_at_9[0x15]; 1214 u8 qp_ts_format[0x2]; 1215 1216 u8 reserved_at_20[0x60]; 1217 1218 u8 reserved_at_80[0xc]; 1219 u8 l3_type[0x4]; 1220 u8 reserved_at_90[0x8]; 1221 u8 roce_version[0x8]; 1222 1223 u8 reserved_at_a0[0x10]; 1224 u8 r_roce_dest_udp_port[0x10]; 1225 1226 u8 r_roce_max_src_udp_port[0x10]; 1227 u8 r_roce_min_src_udp_port[0x10]; 1228 1229 u8 reserved_at_e0[0x10]; 1230 u8 roce_address_table_size[0x10]; 1231 1232 u8 reserved_at_100[0x700]; 1233 }; 1234 1235 struct mlx5_ifc_sync_steering_in_bits { 1236 u8 opcode[0x10]; 1237 u8 uid[0x10]; 1238 1239 u8 reserved_at_20[0x10]; 1240 u8 op_mod[0x10]; 1241 1242 u8 reserved_at_40[0xc0]; 1243 }; 1244 1245 struct mlx5_ifc_sync_steering_out_bits { 1246 u8 status[0x8]; 1247 u8 reserved_at_8[0x18]; 1248 1249 u8 syndrome[0x20]; 1250 1251 u8 reserved_at_40[0x40]; 1252 }; 1253 1254 struct mlx5_ifc_sync_crypto_in_bits { 1255 u8 opcode[0x10]; 1256 u8 uid[0x10]; 1257 1258 u8 reserved_at_20[0x10]; 1259 u8 op_mod[0x10]; 1260 1261 u8 reserved_at_40[0x20]; 1262 1263 u8 reserved_at_60[0x10]; 1264 u8 crypto_type[0x10]; 1265 1266 u8 reserved_at_80[0x80]; 1267 }; 1268 1269 struct mlx5_ifc_sync_crypto_out_bits { 1270 u8 status[0x8]; 1271 u8 reserved_at_8[0x18]; 1272 1273 u8 syndrome[0x20]; 1274 1275 u8 reserved_at_40[0x40]; 1276 }; 1277 1278 struct mlx5_ifc_device_mem_cap_bits { 1279 u8 memic[0x1]; 1280 u8 reserved_at_1[0x1f]; 1281 1282 u8 reserved_at_20[0xb]; 1283 u8 log_min_memic_alloc_size[0x5]; 1284 u8 reserved_at_30[0x8]; 1285 u8 log_max_memic_addr_alignment[0x8]; 1286 1287 u8 memic_bar_start_addr[0x40]; 1288 1289 u8 memic_bar_size[0x20]; 1290 1291 u8 max_memic_size[0x20]; 1292 1293 u8 steering_sw_icm_start_address[0x40]; 1294 1295 u8 reserved_at_100[0x8]; 1296 u8 log_header_modify_sw_icm_size[0x8]; 1297 u8 reserved_at_110[0x2]; 1298 u8 log_sw_icm_alloc_granularity[0x6]; 1299 u8 log_steering_sw_icm_size[0x8]; 1300 1301 u8 log_indirect_encap_sw_icm_size[0x8]; 1302 u8 reserved_at_128[0x10]; 1303 u8 log_header_modify_pattern_sw_icm_size[0x8]; 1304 1305 u8 header_modify_sw_icm_start_address[0x40]; 1306 1307 u8 reserved_at_180[0x40]; 1308 1309 u8 header_modify_pattern_sw_icm_start_address[0x40]; 1310 1311 u8 memic_operations[0x20]; 1312 1313 u8 reserved_at_220[0x20]; 1314 1315 u8 indirect_encap_sw_icm_start_address[0x40]; 1316 1317 u8 reserved_at_280[0x580]; 1318 }; 1319 1320 struct mlx5_ifc_device_event_cap_bits { 1321 u8 user_affiliated_events[4][0x40]; 1322 1323 u8 user_unaffiliated_events[4][0x40]; 1324 }; 1325 1326 struct mlx5_ifc_virtio_emulation_cap_bits { 1327 u8 desc_tunnel_offload_type[0x1]; 1328 u8 eth_frame_offload_type[0x1]; 1329 u8 virtio_version_1_0[0x1]; 1330 u8 device_features_bits_mask[0xd]; 1331 u8 event_mode[0x8]; 1332 u8 virtio_queue_type[0x8]; 1333 1334 u8 max_tunnel_desc[0x10]; 1335 u8 reserved_at_30[0x3]; 1336 u8 log_doorbell_stride[0x5]; 1337 u8 reserved_at_38[0x3]; 1338 u8 log_doorbell_bar_size[0x5]; 1339 1340 u8 doorbell_bar_offset[0x40]; 1341 1342 u8 max_emulated_devices[0x8]; 1343 u8 max_num_virtio_queues[0x18]; 1344 1345 u8 reserved_at_a0[0x20]; 1346 1347 u8 reserved_at_c0[0x13]; 1348 u8 desc_group_mkey_supported[0x1]; 1349 u8 freeze_to_rdy_supported[0x1]; 1350 u8 reserved_at_d5[0xb]; 1351 1352 u8 reserved_at_e0[0x20]; 1353 1354 u8 umem_1_buffer_param_a[0x20]; 1355 1356 u8 umem_1_buffer_param_b[0x20]; 1357 1358 u8 umem_2_buffer_param_a[0x20]; 1359 1360 u8 umem_2_buffer_param_b[0x20]; 1361 1362 u8 umem_3_buffer_param_a[0x20]; 1363 1364 u8 umem_3_buffer_param_b[0x20]; 1365 1366 u8 reserved_at_1c0[0x640]; 1367 }; 1368 1369 enum { 1370 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0, 1371 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2, 1372 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4, 1373 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8, 1374 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10, 1375 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20, 1376 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40, 1377 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80, 1378 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100, 1379 }; 1380 1381 enum { 1382 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1, 1383 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2, 1384 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4, 1385 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8, 1386 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10, 1387 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20, 1388 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40, 1389 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80, 1390 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100, 1391 }; 1392 1393 struct mlx5_ifc_atomic_caps_bits { 1394 u8 reserved_at_0[0x40]; 1395 1396 u8 atomic_req_8B_endianness_mode[0x2]; 1397 u8 reserved_at_42[0x4]; 1398 u8 supported_atomic_req_8B_endianness_mode_1[0x1]; 1399 1400 u8 reserved_at_47[0x19]; 1401 1402 u8 reserved_at_60[0x20]; 1403 1404 u8 reserved_at_80[0x10]; 1405 u8 atomic_operations[0x10]; 1406 1407 u8 reserved_at_a0[0x10]; 1408 u8 atomic_size_qp[0x10]; 1409 1410 u8 reserved_at_c0[0x10]; 1411 u8 atomic_size_dc[0x10]; 1412 1413 u8 reserved_at_e0[0x720]; 1414 }; 1415 1416 struct mlx5_ifc_odp_scheme_cap_bits { 1417 u8 reserved_at_0[0x40]; 1418 1419 u8 sig[0x1]; 1420 u8 reserved_at_41[0x4]; 1421 u8 page_prefetch[0x1]; 1422 u8 reserved_at_46[0x1a]; 1423 1424 u8 reserved_at_60[0x20]; 1425 1426 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps; 1427 1428 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps; 1429 1430 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps; 1431 1432 struct mlx5_ifc_odp_per_transport_service_cap_bits xrc_odp_caps; 1433 1434 struct mlx5_ifc_odp_per_transport_service_cap_bits dc_odp_caps; 1435 1436 u8 reserved_at_120[0xe0]; 1437 }; 1438 1439 struct mlx5_ifc_odp_cap_bits { 1440 struct mlx5_ifc_odp_scheme_cap_bits transport_page_fault_scheme_cap; 1441 1442 struct mlx5_ifc_odp_scheme_cap_bits memory_page_fault_scheme_cap; 1443 1444 u8 reserved_at_400[0x200]; 1445 1446 u8 mem_page_fault[0x1]; 1447 u8 reserved_at_601[0x1f]; 1448 1449 u8 reserved_at_620[0x1e0]; 1450 }; 1451 1452 struct mlx5_ifc_tls_cap_bits { 1453 u8 tls_1_2_aes_gcm_128[0x1]; 1454 u8 tls_1_3_aes_gcm_128[0x1]; 1455 u8 tls_1_2_aes_gcm_256[0x1]; 1456 u8 tls_1_3_aes_gcm_256[0x1]; 1457 u8 reserved_at_4[0x1c]; 1458 1459 u8 reserved_at_20[0x7e0]; 1460 }; 1461 1462 struct mlx5_ifc_ipsec_cap_bits { 1463 u8 ipsec_full_offload[0x1]; 1464 u8 ipsec_crypto_offload[0x1]; 1465 u8 ipsec_esn[0x1]; 1466 u8 ipsec_crypto_esp_aes_gcm_256_encrypt[0x1]; 1467 u8 ipsec_crypto_esp_aes_gcm_128_encrypt[0x1]; 1468 u8 ipsec_crypto_esp_aes_gcm_256_decrypt[0x1]; 1469 u8 ipsec_crypto_esp_aes_gcm_128_decrypt[0x1]; 1470 u8 reserved_at_7[0x4]; 1471 u8 log_max_ipsec_offload[0x5]; 1472 u8 reserved_at_10[0x10]; 1473 1474 u8 min_log_ipsec_full_replay_window[0x8]; 1475 u8 max_log_ipsec_full_replay_window[0x8]; 1476 u8 reserved_at_30[0x7d0]; 1477 }; 1478 1479 struct mlx5_ifc_macsec_cap_bits { 1480 u8 macsec_epn[0x1]; 1481 u8 reserved_at_1[0x2]; 1482 u8 macsec_crypto_esp_aes_gcm_256_encrypt[0x1]; 1483 u8 macsec_crypto_esp_aes_gcm_128_encrypt[0x1]; 1484 u8 macsec_crypto_esp_aes_gcm_256_decrypt[0x1]; 1485 u8 macsec_crypto_esp_aes_gcm_128_decrypt[0x1]; 1486 u8 reserved_at_7[0x4]; 1487 u8 log_max_macsec_offload[0x5]; 1488 u8 reserved_at_10[0x10]; 1489 1490 u8 min_log_macsec_full_replay_window[0x8]; 1491 u8 max_log_macsec_full_replay_window[0x8]; 1492 u8 reserved_at_30[0x10]; 1493 1494 u8 reserved_at_40[0x7c0]; 1495 }; 1496 1497 enum { 1498 MLX5_WQ_TYPE_LINKED_LIST = 0x0, 1499 MLX5_WQ_TYPE_CYCLIC = 0x1, 1500 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2, 1501 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3, 1502 }; 1503 1504 enum { 1505 MLX5_WQ_END_PAD_MODE_NONE = 0x0, 1506 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1, 1507 }; 1508 1509 enum { 1510 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0, 1511 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1, 1512 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2, 1513 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3, 1514 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4, 1515 }; 1516 1517 enum { 1518 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0, 1519 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1, 1520 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2, 1521 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3, 1522 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4, 1523 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5, 1524 }; 1525 1526 enum { 1527 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0, 1528 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1, 1529 }; 1530 1531 enum { 1532 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0, 1533 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1, 1534 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3, 1535 }; 1536 1537 enum { 1538 MLX5_CAP_PORT_TYPE_IB = 0x0, 1539 MLX5_CAP_PORT_TYPE_ETH = 0x1, 1540 }; 1541 1542 enum { 1543 MLX5_CAP_UMR_FENCE_STRONG = 0x0, 1544 MLX5_CAP_UMR_FENCE_SMALL = 0x1, 1545 MLX5_CAP_UMR_FENCE_NONE = 0x2, 1546 }; 1547 1548 enum { 1549 MLX5_FLEX_IPV4_OVER_VXLAN_ENABLED = 1 << 0, 1550 MLX5_FLEX_IPV6_OVER_VXLAN_ENABLED = 1 << 1, 1551 MLX5_FLEX_IPV6_OVER_IP_ENABLED = 1 << 2, 1552 MLX5_FLEX_PARSER_GENEVE_ENABLED = 1 << 3, 1553 MLX5_FLEX_PARSER_MPLS_OVER_GRE_ENABLED = 1 << 4, 1554 MLX5_FLEX_PARSER_MPLS_OVER_UDP_ENABLED = 1 << 5, 1555 MLX5_FLEX_P_BIT_VXLAN_GPE_ENABLED = 1 << 6, 1556 MLX5_FLEX_PARSER_VXLAN_GPE_ENABLED = 1 << 7, 1557 MLX5_FLEX_PARSER_ICMP_V4_ENABLED = 1 << 8, 1558 MLX5_FLEX_PARSER_ICMP_V6_ENABLED = 1 << 9, 1559 MLX5_FLEX_PARSER_GENEVE_TLV_OPTION_0_ENABLED = 1 << 10, 1560 MLX5_FLEX_PARSER_GTPU_ENABLED = 1 << 11, 1561 MLX5_FLEX_PARSER_GTPU_DW_2_ENABLED = 1 << 16, 1562 MLX5_FLEX_PARSER_GTPU_FIRST_EXT_DW_0_ENABLED = 1 << 17, 1563 MLX5_FLEX_PARSER_GTPU_DW_0_ENABLED = 1 << 18, 1564 MLX5_FLEX_PARSER_GTPU_TEID_ENABLED = 1 << 19, 1565 }; 1566 1567 enum { 1568 MLX5_UCTX_CAP_RAW_TX = 1UL << 0, 1569 MLX5_UCTX_CAP_INTERNAL_DEV_RES = 1UL << 1, 1570 }; 1571 1572 #define MLX5_FC_BULK_SIZE_FACTOR 128 1573 1574 enum mlx5_fc_bulk_alloc_bitmask { 1575 MLX5_FC_BULK_128 = (1 << 0), 1576 MLX5_FC_BULK_256 = (1 << 1), 1577 MLX5_FC_BULK_512 = (1 << 2), 1578 MLX5_FC_BULK_1024 = (1 << 3), 1579 MLX5_FC_BULK_2048 = (1 << 4), 1580 MLX5_FC_BULK_4096 = (1 << 5), 1581 MLX5_FC_BULK_8192 = (1 << 6), 1582 MLX5_FC_BULK_16384 = (1 << 7), 1583 }; 1584 1585 #define MLX5_FC_BULK_NUM_FCS(fc_enum) (MLX5_FC_BULK_SIZE_FACTOR * (fc_enum)) 1586 1587 #define MLX5_FT_MAX_MULTIPATH_LEVEL 63 1588 1589 enum { 1590 MLX5_STEERING_FORMAT_CONNECTX_5 = 0, 1591 MLX5_STEERING_FORMAT_CONNECTX_6DX = 1, 1592 MLX5_STEERING_FORMAT_CONNECTX_7 = 2, 1593 }; 1594 1595 struct mlx5_ifc_cmd_hca_cap_bits { 1596 u8 reserved_at_0[0x6]; 1597 u8 page_request_disable[0x1]; 1598 u8 reserved_at_7[0x9]; 1599 u8 shared_object_to_user_object_allowed[0x1]; 1600 u8 reserved_at_13[0xe]; 1601 u8 vhca_resource_manager[0x1]; 1602 1603 u8 hca_cap_2[0x1]; 1604 u8 create_lag_when_not_master_up[0x1]; 1605 u8 dtor[0x1]; 1606 u8 event_on_vhca_state_teardown_request[0x1]; 1607 u8 event_on_vhca_state_in_use[0x1]; 1608 u8 event_on_vhca_state_active[0x1]; 1609 u8 event_on_vhca_state_allocated[0x1]; 1610 u8 event_on_vhca_state_invalid[0x1]; 1611 u8 reserved_at_28[0x8]; 1612 u8 vhca_id[0x10]; 1613 1614 u8 reserved_at_40[0x40]; 1615 1616 u8 log_max_srq_sz[0x8]; 1617 u8 log_max_qp_sz[0x8]; 1618 u8 event_cap[0x1]; 1619 u8 reserved_at_91[0x2]; 1620 u8 isolate_vl_tc_new[0x1]; 1621 u8 reserved_at_94[0x4]; 1622 u8 prio_tag_required[0x1]; 1623 u8 reserved_at_99[0x2]; 1624 u8 log_max_qp[0x5]; 1625 1626 u8 reserved_at_a0[0x3]; 1627 u8 ece_support[0x1]; 1628 u8 reserved_at_a4[0x5]; 1629 u8 reg_c_preserve[0x1]; 1630 u8 reserved_at_aa[0x1]; 1631 u8 log_max_srq[0x5]; 1632 u8 reserved_at_b0[0x1]; 1633 u8 uplink_follow[0x1]; 1634 u8 ts_cqe_to_dest_cqn[0x1]; 1635 u8 reserved_at_b3[0x6]; 1636 u8 go_back_n[0x1]; 1637 u8 reserved_at_ba[0x6]; 1638 1639 u8 max_sgl_for_optimized_performance[0x8]; 1640 u8 log_max_cq_sz[0x8]; 1641 u8 relaxed_ordering_write_umr[0x1]; 1642 u8 relaxed_ordering_read_umr[0x1]; 1643 u8 reserved_at_d2[0x7]; 1644 u8 virtio_net_device_emualtion_manager[0x1]; 1645 u8 virtio_blk_device_emualtion_manager[0x1]; 1646 u8 log_max_cq[0x5]; 1647 1648 u8 log_max_eq_sz[0x8]; 1649 u8 relaxed_ordering_write[0x1]; 1650 u8 relaxed_ordering_read_pci_enabled[0x1]; 1651 u8 log_max_mkey[0x6]; 1652 u8 reserved_at_f0[0x6]; 1653 u8 terminate_scatter_list_mkey[0x1]; 1654 u8 repeated_mkey[0x1]; 1655 u8 dump_fill_mkey[0x1]; 1656 u8 reserved_at_f9[0x2]; 1657 u8 fast_teardown[0x1]; 1658 u8 log_max_eq[0x4]; 1659 1660 u8 max_indirection[0x8]; 1661 u8 fixed_buffer_size[0x1]; 1662 u8 log_max_mrw_sz[0x7]; 1663 u8 force_teardown[0x1]; 1664 u8 reserved_at_111[0x1]; 1665 u8 log_max_bsf_list_size[0x6]; 1666 u8 umr_extended_translation_offset[0x1]; 1667 u8 null_mkey[0x1]; 1668 u8 log_max_klm_list_size[0x6]; 1669 1670 u8 reserved_at_120[0x2]; 1671 u8 qpc_extension[0x1]; 1672 u8 reserved_at_123[0x7]; 1673 u8 log_max_ra_req_dc[0x6]; 1674 u8 reserved_at_130[0x2]; 1675 u8 eth_wqe_too_small[0x1]; 1676 u8 reserved_at_133[0x6]; 1677 u8 vnic_env_cq_overrun[0x1]; 1678 u8 log_max_ra_res_dc[0x6]; 1679 1680 u8 reserved_at_140[0x5]; 1681 u8 release_all_pages[0x1]; 1682 u8 must_not_use[0x1]; 1683 u8 reserved_at_147[0x2]; 1684 u8 roce_accl[0x1]; 1685 u8 log_max_ra_req_qp[0x6]; 1686 u8 reserved_at_150[0xa]; 1687 u8 log_max_ra_res_qp[0x6]; 1688 1689 u8 end_pad[0x1]; 1690 u8 cc_query_allowed[0x1]; 1691 u8 cc_modify_allowed[0x1]; 1692 u8 start_pad[0x1]; 1693 u8 cache_line_128byte[0x1]; 1694 u8 reserved_at_165[0x4]; 1695 u8 rts2rts_qp_counters_set_id[0x1]; 1696 u8 reserved_at_16a[0x2]; 1697 u8 vnic_env_int_rq_oob[0x1]; 1698 u8 sbcam_reg[0x1]; 1699 u8 reserved_at_16e[0x1]; 1700 u8 qcam_reg[0x1]; 1701 u8 gid_table_size[0x10]; 1702 1703 u8 out_of_seq_cnt[0x1]; 1704 u8 vport_counters[0x1]; 1705 u8 retransmission_q_counters[0x1]; 1706 u8 debug[0x1]; 1707 u8 modify_rq_counter_set_id[0x1]; 1708 u8 rq_delay_drop[0x1]; 1709 u8 max_qp_cnt[0xa]; 1710 u8 pkey_table_size[0x10]; 1711 1712 u8 vport_group_manager[0x1]; 1713 u8 vhca_group_manager[0x1]; 1714 u8 ib_virt[0x1]; 1715 u8 eth_virt[0x1]; 1716 u8 vnic_env_queue_counters[0x1]; 1717 u8 ets[0x1]; 1718 u8 nic_flow_table[0x1]; 1719 u8 eswitch_manager[0x1]; 1720 u8 device_memory[0x1]; 1721 u8 mcam_reg[0x1]; 1722 u8 pcam_reg[0x1]; 1723 u8 local_ca_ack_delay[0x5]; 1724 u8 port_module_event[0x1]; 1725 u8 enhanced_error_q_counters[0x1]; 1726 u8 ports_check[0x1]; 1727 u8 reserved_at_1b3[0x1]; 1728 u8 disable_link_up[0x1]; 1729 u8 beacon_led[0x1]; 1730 u8 port_type[0x2]; 1731 u8 num_ports[0x8]; 1732 1733 u8 reserved_at_1c0[0x1]; 1734 u8 pps[0x1]; 1735 u8 pps_modify[0x1]; 1736 u8 log_max_msg[0x5]; 1737 u8 reserved_at_1c8[0x4]; 1738 u8 max_tc[0x4]; 1739 u8 temp_warn_event[0x1]; 1740 u8 dcbx[0x1]; 1741 u8 general_notification_event[0x1]; 1742 u8 reserved_at_1d3[0x2]; 1743 u8 fpga[0x1]; 1744 u8 rol_s[0x1]; 1745 u8 rol_g[0x1]; 1746 u8 reserved_at_1d8[0x1]; 1747 u8 wol_s[0x1]; 1748 u8 wol_g[0x1]; 1749 u8 wol_a[0x1]; 1750 u8 wol_b[0x1]; 1751 u8 wol_m[0x1]; 1752 u8 wol_u[0x1]; 1753 u8 wol_p[0x1]; 1754 1755 u8 stat_rate_support[0x10]; 1756 u8 reserved_at_1f0[0x1]; 1757 u8 pci_sync_for_fw_update_event[0x1]; 1758 u8 reserved_at_1f2[0x6]; 1759 u8 init2_lag_tx_port_affinity[0x1]; 1760 u8 reserved_at_1fa[0x2]; 1761 u8 wqe_based_flow_table_update_cap[0x1]; 1762 u8 cqe_version[0x4]; 1763 1764 u8 compact_address_vector[0x1]; 1765 u8 striding_rq[0x1]; 1766 u8 reserved_at_202[0x1]; 1767 u8 ipoib_enhanced_offloads[0x1]; 1768 u8 ipoib_basic_offloads[0x1]; 1769 u8 reserved_at_205[0x1]; 1770 u8 repeated_block_disabled[0x1]; 1771 u8 umr_modify_entity_size_disabled[0x1]; 1772 u8 umr_modify_atomic_disabled[0x1]; 1773 u8 umr_indirect_mkey_disabled[0x1]; 1774 u8 umr_fence[0x2]; 1775 u8 dc_req_scat_data_cqe[0x1]; 1776 u8 reserved_at_20d[0x2]; 1777 u8 drain_sigerr[0x1]; 1778 u8 cmdif_checksum[0x2]; 1779 u8 sigerr_cqe[0x1]; 1780 u8 reserved_at_213[0x1]; 1781 u8 wq_signature[0x1]; 1782 u8 sctr_data_cqe[0x1]; 1783 u8 reserved_at_216[0x1]; 1784 u8 sho[0x1]; 1785 u8 tph[0x1]; 1786 u8 rf[0x1]; 1787 u8 dct[0x1]; 1788 u8 qos[0x1]; 1789 u8 eth_net_offloads[0x1]; 1790 u8 roce[0x1]; 1791 u8 atomic[0x1]; 1792 u8 reserved_at_21f[0x1]; 1793 1794 u8 cq_oi[0x1]; 1795 u8 cq_resize[0x1]; 1796 u8 cq_moderation[0x1]; 1797 u8 cq_period_mode_modify[0x1]; 1798 u8 reserved_at_224[0x2]; 1799 u8 cq_eq_remap[0x1]; 1800 u8 pg[0x1]; 1801 u8 block_lb_mc[0x1]; 1802 u8 reserved_at_229[0x1]; 1803 u8 scqe_break_moderation[0x1]; 1804 u8 cq_period_start_from_cqe[0x1]; 1805 u8 cd[0x1]; 1806 u8 reserved_at_22d[0x1]; 1807 u8 apm[0x1]; 1808 u8 vector_calc[0x1]; 1809 u8 umr_ptr_rlky[0x1]; 1810 u8 imaicl[0x1]; 1811 u8 qp_packet_based[0x1]; 1812 u8 reserved_at_233[0x3]; 1813 u8 qkv[0x1]; 1814 u8 pkv[0x1]; 1815 u8 set_deth_sqpn[0x1]; 1816 u8 reserved_at_239[0x3]; 1817 u8 xrc[0x1]; 1818 u8 ud[0x1]; 1819 u8 uc[0x1]; 1820 u8 rc[0x1]; 1821 1822 u8 uar_4k[0x1]; 1823 u8 reserved_at_241[0x7]; 1824 u8 fl_rc_qp_when_roce_disabled[0x1]; 1825 u8 regexp_params[0x1]; 1826 u8 uar_sz[0x6]; 1827 u8 port_selection_cap[0x1]; 1828 u8 reserved_at_251[0x1]; 1829 u8 umem_uid_0[0x1]; 1830 u8 reserved_at_253[0x5]; 1831 u8 log_pg_sz[0x8]; 1832 1833 u8 bf[0x1]; 1834 u8 driver_version[0x1]; 1835 u8 pad_tx_eth_packet[0x1]; 1836 u8 reserved_at_263[0x3]; 1837 u8 mkey_by_name[0x1]; 1838 u8 reserved_at_267[0x4]; 1839 1840 u8 log_bf_reg_size[0x5]; 1841 1842 u8 reserved_at_270[0x3]; 1843 u8 qp_error_syndrome[0x1]; 1844 u8 reserved_at_274[0x2]; 1845 u8 lag_dct[0x2]; 1846 u8 lag_tx_port_affinity[0x1]; 1847 u8 lag_native_fdb_selection[0x1]; 1848 u8 reserved_at_27a[0x1]; 1849 u8 lag_master[0x1]; 1850 u8 num_lag_ports[0x4]; 1851 1852 u8 reserved_at_280[0x10]; 1853 u8 max_wqe_sz_sq[0x10]; 1854 1855 u8 reserved_at_2a0[0xb]; 1856 u8 shampo[0x1]; 1857 u8 reserved_at_2ac[0x4]; 1858 u8 max_wqe_sz_rq[0x10]; 1859 1860 u8 max_flow_counter_31_16[0x10]; 1861 u8 max_wqe_sz_sq_dc[0x10]; 1862 1863 u8 reserved_at_2e0[0x7]; 1864 u8 max_qp_mcg[0x19]; 1865 1866 u8 reserved_at_300[0x10]; 1867 u8 flow_counter_bulk_alloc[0x8]; 1868 u8 log_max_mcg[0x8]; 1869 1870 u8 reserved_at_320[0x3]; 1871 u8 log_max_transport_domain[0x5]; 1872 u8 reserved_at_328[0x2]; 1873 u8 relaxed_ordering_read[0x1]; 1874 u8 log_max_pd[0x5]; 1875 u8 dp_ordering_ooo_all_ud[0x1]; 1876 u8 dp_ordering_ooo_all_uc[0x1]; 1877 u8 dp_ordering_ooo_all_xrc[0x1]; 1878 u8 dp_ordering_ooo_all_dc[0x1]; 1879 u8 dp_ordering_ooo_all_rc[0x1]; 1880 u8 pcie_reset_using_hotreset_method[0x1]; 1881 u8 pci_sync_for_fw_update_with_driver_unload[0x1]; 1882 u8 vnic_env_cnt_steering_fail[0x1]; 1883 u8 vport_counter_local_loopback[0x1]; 1884 u8 q_counter_aggregation[0x1]; 1885 u8 q_counter_other_vport[0x1]; 1886 u8 log_max_xrcd[0x5]; 1887 1888 u8 nic_receive_steering_discard[0x1]; 1889 u8 receive_discard_vport_down[0x1]; 1890 u8 transmit_discard_vport_down[0x1]; 1891 u8 eq_overrun_count[0x1]; 1892 u8 reserved_at_344[0x1]; 1893 u8 invalid_command_count[0x1]; 1894 u8 quota_exceeded_count[0x1]; 1895 u8 reserved_at_347[0x1]; 1896 u8 log_max_flow_counter_bulk[0x8]; 1897 u8 max_flow_counter_15_0[0x10]; 1898 1899 1900 u8 reserved_at_360[0x3]; 1901 u8 log_max_rq[0x5]; 1902 u8 reserved_at_368[0x3]; 1903 u8 log_max_sq[0x5]; 1904 u8 reserved_at_370[0x3]; 1905 u8 log_max_tir[0x5]; 1906 u8 reserved_at_378[0x3]; 1907 u8 log_max_tis[0x5]; 1908 1909 u8 basic_cyclic_rcv_wqe[0x1]; 1910 u8 reserved_at_381[0x2]; 1911 u8 log_max_rmp[0x5]; 1912 u8 reserved_at_388[0x3]; 1913 u8 log_max_rqt[0x5]; 1914 u8 reserved_at_390[0x3]; 1915 u8 log_max_rqt_size[0x5]; 1916 u8 reserved_at_398[0x3]; 1917 u8 log_max_tis_per_sq[0x5]; 1918 1919 u8 ext_stride_num_range[0x1]; 1920 u8 roce_rw_supported[0x1]; 1921 u8 log_max_current_uc_list_wr_supported[0x1]; 1922 u8 log_max_stride_sz_rq[0x5]; 1923 u8 reserved_at_3a8[0x3]; 1924 u8 log_min_stride_sz_rq[0x5]; 1925 u8 reserved_at_3b0[0x3]; 1926 u8 log_max_stride_sz_sq[0x5]; 1927 u8 reserved_at_3b8[0x3]; 1928 u8 log_min_stride_sz_sq[0x5]; 1929 1930 u8 hairpin[0x1]; 1931 u8 reserved_at_3c1[0x2]; 1932 u8 log_max_hairpin_queues[0x5]; 1933 u8 reserved_at_3c8[0x3]; 1934 u8 log_max_hairpin_wq_data_sz[0x5]; 1935 u8 reserved_at_3d0[0x3]; 1936 u8 log_max_hairpin_num_packets[0x5]; 1937 u8 reserved_at_3d8[0x3]; 1938 u8 log_max_wq_sz[0x5]; 1939 1940 u8 nic_vport_change_event[0x1]; 1941 u8 disable_local_lb_uc[0x1]; 1942 u8 disable_local_lb_mc[0x1]; 1943 u8 log_min_hairpin_wq_data_sz[0x5]; 1944 u8 reserved_at_3e8[0x1]; 1945 u8 silent_mode[0x1]; 1946 u8 vhca_state[0x1]; 1947 u8 log_max_vlan_list[0x5]; 1948 u8 reserved_at_3f0[0x3]; 1949 u8 log_max_current_mc_list[0x5]; 1950 u8 reserved_at_3f8[0x3]; 1951 u8 log_max_current_uc_list[0x5]; 1952 1953 u8 general_obj_types[0x40]; 1954 1955 u8 sq_ts_format[0x2]; 1956 u8 rq_ts_format[0x2]; 1957 u8 steering_format_version[0x4]; 1958 u8 create_qp_start_hint[0x18]; 1959 1960 u8 reserved_at_460[0x1]; 1961 u8 ats[0x1]; 1962 u8 cross_vhca_rqt[0x1]; 1963 u8 log_max_uctx[0x5]; 1964 u8 reserved_at_468[0x1]; 1965 u8 crypto[0x1]; 1966 u8 ipsec_offload[0x1]; 1967 u8 log_max_umem[0x5]; 1968 u8 max_num_eqs[0x10]; 1969 1970 u8 reserved_at_480[0x1]; 1971 u8 tls_tx[0x1]; 1972 u8 tls_rx[0x1]; 1973 u8 log_max_l2_table[0x5]; 1974 u8 reserved_at_488[0x8]; 1975 u8 log_uar_page_sz[0x10]; 1976 1977 u8 reserved_at_4a0[0x20]; 1978 u8 device_frequency_mhz[0x20]; 1979 u8 device_frequency_khz[0x20]; 1980 1981 u8 reserved_at_500[0x20]; 1982 u8 num_of_uars_per_page[0x20]; 1983 1984 u8 flex_parser_protocols[0x20]; 1985 1986 u8 max_geneve_tlv_options[0x8]; 1987 u8 reserved_at_568[0x3]; 1988 u8 max_geneve_tlv_option_data_len[0x5]; 1989 u8 reserved_at_570[0x9]; 1990 u8 adv_virtualization[0x1]; 1991 u8 reserved_at_57a[0x6]; 1992 1993 u8 reserved_at_580[0xb]; 1994 u8 log_max_dci_stream_channels[0x5]; 1995 u8 reserved_at_590[0x3]; 1996 u8 log_max_dci_errored_streams[0x5]; 1997 u8 reserved_at_598[0x8]; 1998 1999 u8 reserved_at_5a0[0x10]; 2000 u8 enhanced_cqe_compression[0x1]; 2001 u8 reserved_at_5b1[0x1]; 2002 u8 crossing_vhca_mkey[0x1]; 2003 u8 log_max_dek[0x5]; 2004 u8 reserved_at_5b8[0x4]; 2005 u8 mini_cqe_resp_stride_index[0x1]; 2006 u8 cqe_128_always[0x1]; 2007 u8 cqe_compression_128[0x1]; 2008 u8 cqe_compression[0x1]; 2009 2010 u8 cqe_compression_timeout[0x10]; 2011 u8 cqe_compression_max_num[0x10]; 2012 2013 u8 reserved_at_5e0[0x8]; 2014 u8 flex_parser_id_gtpu_dw_0[0x4]; 2015 u8 reserved_at_5ec[0x4]; 2016 u8 tag_matching[0x1]; 2017 u8 rndv_offload_rc[0x1]; 2018 u8 rndv_offload_dc[0x1]; 2019 u8 log_tag_matching_list_sz[0x5]; 2020 u8 reserved_at_5f8[0x3]; 2021 u8 log_max_xrq[0x5]; 2022 2023 u8 affiliate_nic_vport_criteria[0x8]; 2024 u8 native_port_num[0x8]; 2025 u8 num_vhca_ports[0x8]; 2026 u8 flex_parser_id_gtpu_teid[0x4]; 2027 u8 reserved_at_61c[0x2]; 2028 u8 sw_owner_id[0x1]; 2029 u8 reserved_at_61f[0x1]; 2030 2031 u8 max_num_of_monitor_counters[0x10]; 2032 u8 num_ppcnt_monitor_counters[0x10]; 2033 2034 u8 max_num_sf[0x10]; 2035 u8 num_q_monitor_counters[0x10]; 2036 2037 u8 reserved_at_660[0x20]; 2038 2039 u8 sf[0x1]; 2040 u8 sf_set_partition[0x1]; 2041 u8 reserved_at_682[0x1]; 2042 u8 log_max_sf[0x5]; 2043 u8 apu[0x1]; 2044 u8 reserved_at_689[0x4]; 2045 u8 migration[0x1]; 2046 u8 reserved_at_68e[0x2]; 2047 u8 log_min_sf_size[0x8]; 2048 u8 max_num_sf_partitions[0x8]; 2049 2050 u8 uctx_cap[0x20]; 2051 2052 u8 reserved_at_6c0[0x4]; 2053 u8 flex_parser_id_geneve_tlv_option_0[0x4]; 2054 u8 flex_parser_id_icmp_dw1[0x4]; 2055 u8 flex_parser_id_icmp_dw0[0x4]; 2056 u8 flex_parser_id_icmpv6_dw1[0x4]; 2057 u8 flex_parser_id_icmpv6_dw0[0x4]; 2058 u8 flex_parser_id_outer_first_mpls_over_gre[0x4]; 2059 u8 flex_parser_id_outer_first_mpls_over_udp_label[0x4]; 2060 2061 u8 max_num_match_definer[0x10]; 2062 u8 sf_base_id[0x10]; 2063 2064 u8 flex_parser_id_gtpu_dw_2[0x4]; 2065 u8 flex_parser_id_gtpu_first_ext_dw_0[0x4]; 2066 u8 num_total_dynamic_vf_msix[0x18]; 2067 u8 reserved_at_720[0x14]; 2068 u8 dynamic_msix_table_size[0xc]; 2069 u8 reserved_at_740[0xc]; 2070 u8 min_dynamic_vf_msix_table_size[0x4]; 2071 u8 reserved_at_750[0x2]; 2072 u8 data_direct[0x1]; 2073 u8 reserved_at_753[0x1]; 2074 u8 max_dynamic_vf_msix_table_size[0xc]; 2075 2076 u8 reserved_at_760[0x3]; 2077 u8 log_max_num_header_modify_argument[0x5]; 2078 u8 log_header_modify_argument_granularity_offset[0x4]; 2079 u8 log_header_modify_argument_granularity[0x4]; 2080 u8 reserved_at_770[0x3]; 2081 u8 log_header_modify_argument_max_alloc[0x5]; 2082 u8 reserved_at_778[0x8]; 2083 2084 u8 vhca_tunnel_commands[0x40]; 2085 u8 match_definer_format_supported[0x40]; 2086 }; 2087 2088 enum { 2089 MLX5_CROSS_VHCA_OBJ_TO_OBJ_SUPPORTED_LOCAL_FLOW_TABLE_TO_REMOTE_FLOW_TABLE_MISS = 0x80000, 2090 MLX5_CROSS_VHCA_OBJ_TO_OBJ_SUPPORTED_LOCAL_FLOW_TABLE_ROOT_TO_REMOTE_FLOW_TABLE = (1ULL << 20), 2091 }; 2092 2093 enum { 2094 MLX5_ALLOWED_OBJ_FOR_OTHER_VHCA_ACCESS_FLOW_TABLE = 0x200, 2095 }; 2096 2097 struct mlx5_ifc_cmd_hca_cap_2_bits { 2098 u8 reserved_at_0[0x80]; 2099 2100 u8 migratable[0x1]; 2101 u8 reserved_at_81[0x7]; 2102 u8 dp_ordering_force[0x1]; 2103 u8 reserved_at_89[0x9]; 2104 u8 query_vuid[0x1]; 2105 u8 reserved_at_93[0x5]; 2106 u8 umr_log_entity_size_5[0x1]; 2107 u8 reserved_at_99[0x7]; 2108 2109 u8 max_reformat_insert_size[0x8]; 2110 u8 max_reformat_insert_offset[0x8]; 2111 u8 max_reformat_remove_size[0x8]; 2112 u8 max_reformat_remove_offset[0x8]; 2113 2114 u8 reserved_at_c0[0x8]; 2115 u8 migration_multi_load[0x1]; 2116 u8 migration_tracking_state[0x1]; 2117 u8 multiplane_qp_ud[0x1]; 2118 u8 reserved_at_cb[0x5]; 2119 u8 migration_in_chunks[0x1]; 2120 u8 reserved_at_d1[0x1]; 2121 u8 sf_eq_usage[0x1]; 2122 u8 reserved_at_d3[0xd]; 2123 2124 u8 cross_vhca_object_to_object_supported[0x20]; 2125 2126 u8 allowed_object_for_other_vhca_access[0x40]; 2127 2128 u8 reserved_at_140[0x60]; 2129 2130 u8 flow_table_type_2_type[0x8]; 2131 u8 reserved_at_1a8[0x2]; 2132 u8 format_select_dw_8_6_ext[0x1]; 2133 u8 log_min_mkey_entity_size[0x5]; 2134 u8 reserved_at_1b0[0x10]; 2135 2136 u8 reserved_at_1c0[0x60]; 2137 2138 u8 reserved_at_220[0x1]; 2139 u8 sw_vhca_id_valid[0x1]; 2140 u8 sw_vhca_id[0xe]; 2141 u8 reserved_at_230[0x10]; 2142 2143 u8 reserved_at_240[0xb]; 2144 u8 ts_cqe_metadata_size2wqe_counter[0x5]; 2145 u8 reserved_at_250[0x10]; 2146 2147 u8 reserved_at_260[0x20]; 2148 2149 u8 format_select_dw_gtpu_dw_0[0x8]; 2150 u8 format_select_dw_gtpu_dw_1[0x8]; 2151 u8 format_select_dw_gtpu_dw_2[0x8]; 2152 u8 format_select_dw_gtpu_first_ext_dw_0[0x8]; 2153 2154 u8 generate_wqe_type[0x20]; 2155 2156 u8 reserved_at_2c0[0xc0]; 2157 2158 u8 reserved_at_380[0xb]; 2159 u8 min_mkey_log_entity_size_fixed_buffer[0x5]; 2160 u8 ec_vf_vport_base[0x10]; 2161 2162 u8 reserved_at_3a0[0xa]; 2163 u8 max_mkey_log_entity_size_mtt[0x6]; 2164 u8 max_rqt_vhca_id[0x10]; 2165 2166 u8 reserved_at_3c0[0x20]; 2167 2168 u8 reserved_at_3e0[0x10]; 2169 u8 pcc_ifa2[0x1]; 2170 u8 reserved_at_3f1[0xf]; 2171 2172 u8 reserved_at_400[0x1]; 2173 u8 min_mkey_log_entity_size_fixed_buffer_valid[0x1]; 2174 u8 reserved_at_402[0xe]; 2175 u8 return_reg_id[0x10]; 2176 2177 u8 reserved_at_420[0x1c]; 2178 u8 flow_table_hash_type[0x4]; 2179 2180 u8 reserved_at_440[0x8]; 2181 u8 max_num_eqs_24b[0x18]; 2182 u8 reserved_at_460[0x3a0]; 2183 }; 2184 2185 enum mlx5_ifc_flow_destination_type { 2186 MLX5_IFC_FLOW_DESTINATION_TYPE_VPORT = 0x0, 2187 MLX5_IFC_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1, 2188 MLX5_IFC_FLOW_DESTINATION_TYPE_TIR = 0x2, 2189 MLX5_IFC_FLOW_DESTINATION_TYPE_FLOW_SAMPLER = 0x6, 2190 MLX5_IFC_FLOW_DESTINATION_TYPE_UPLINK = 0x8, 2191 MLX5_IFC_FLOW_DESTINATION_TYPE_TABLE_TYPE = 0xA, 2192 }; 2193 2194 enum mlx5_flow_table_miss_action { 2195 MLX5_FLOW_TABLE_MISS_ACTION_DEF, 2196 MLX5_FLOW_TABLE_MISS_ACTION_FWD, 2197 MLX5_FLOW_TABLE_MISS_ACTION_SWITCH_DOMAIN, 2198 }; 2199 2200 struct mlx5_ifc_dest_format_struct_bits { 2201 u8 destination_type[0x8]; 2202 u8 destination_id[0x18]; 2203 2204 u8 destination_eswitch_owner_vhca_id_valid[0x1]; 2205 u8 packet_reformat[0x1]; 2206 u8 reserved_at_22[0x6]; 2207 u8 destination_table_type[0x8]; 2208 u8 destination_eswitch_owner_vhca_id[0x10]; 2209 }; 2210 2211 struct mlx5_ifc_flow_counter_list_bits { 2212 u8 flow_counter_id[0x20]; 2213 2214 u8 reserved_at_20[0x20]; 2215 }; 2216 2217 struct mlx5_ifc_extended_dest_format_bits { 2218 struct mlx5_ifc_dest_format_struct_bits destination_entry; 2219 2220 u8 packet_reformat_id[0x20]; 2221 2222 u8 reserved_at_60[0x20]; 2223 }; 2224 2225 union mlx5_ifc_dest_format_flow_counter_list_auto_bits { 2226 struct mlx5_ifc_extended_dest_format_bits extended_dest_format; 2227 struct mlx5_ifc_flow_counter_list_bits flow_counter_list; 2228 }; 2229 2230 struct mlx5_ifc_fte_match_param_bits { 2231 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers; 2232 2233 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters; 2234 2235 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers; 2236 2237 struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2; 2238 2239 struct mlx5_ifc_fte_match_set_misc3_bits misc_parameters_3; 2240 2241 struct mlx5_ifc_fte_match_set_misc4_bits misc_parameters_4; 2242 2243 struct mlx5_ifc_fte_match_set_misc5_bits misc_parameters_5; 2244 2245 u8 reserved_at_e00[0x200]; 2246 }; 2247 2248 enum { 2249 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0, 2250 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1, 2251 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2, 2252 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3, 2253 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4, 2254 }; 2255 2256 struct mlx5_ifc_rx_hash_field_select_bits { 2257 u8 l3_prot_type[0x1]; 2258 u8 l4_prot_type[0x1]; 2259 u8 selected_fields[0x1e]; 2260 }; 2261 2262 enum { 2263 MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0, 2264 MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1, 2265 }; 2266 2267 enum { 2268 MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0, 2269 MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1, 2270 }; 2271 2272 struct mlx5_ifc_wq_bits { 2273 u8 wq_type[0x4]; 2274 u8 wq_signature[0x1]; 2275 u8 end_padding_mode[0x2]; 2276 u8 cd_slave[0x1]; 2277 u8 reserved_at_8[0x18]; 2278 2279 u8 hds_skip_first_sge[0x1]; 2280 u8 log2_hds_buf_size[0x3]; 2281 u8 reserved_at_24[0x7]; 2282 u8 page_offset[0x5]; 2283 u8 lwm[0x10]; 2284 2285 u8 reserved_at_40[0x8]; 2286 u8 pd[0x18]; 2287 2288 u8 reserved_at_60[0x8]; 2289 u8 uar_page[0x18]; 2290 2291 u8 dbr_addr[0x40]; 2292 2293 u8 hw_counter[0x20]; 2294 2295 u8 sw_counter[0x20]; 2296 2297 u8 reserved_at_100[0xc]; 2298 u8 log_wq_stride[0x4]; 2299 u8 reserved_at_110[0x3]; 2300 u8 log_wq_pg_sz[0x5]; 2301 u8 reserved_at_118[0x3]; 2302 u8 log_wq_sz[0x5]; 2303 2304 u8 dbr_umem_valid[0x1]; 2305 u8 wq_umem_valid[0x1]; 2306 u8 reserved_at_122[0x1]; 2307 u8 log_hairpin_num_packets[0x5]; 2308 u8 reserved_at_128[0x3]; 2309 u8 log_hairpin_data_sz[0x5]; 2310 2311 u8 reserved_at_130[0x4]; 2312 u8 log_wqe_num_of_strides[0x4]; 2313 u8 two_byte_shift_en[0x1]; 2314 u8 reserved_at_139[0x4]; 2315 u8 log_wqe_stride_size[0x3]; 2316 2317 u8 dbr_umem_id[0x20]; 2318 u8 wq_umem_id[0x20]; 2319 2320 u8 wq_umem_offset[0x40]; 2321 2322 u8 headers_mkey[0x20]; 2323 2324 u8 shampo_enable[0x1]; 2325 u8 reserved_at_1e1[0x4]; 2326 u8 log_reservation_size[0x3]; 2327 u8 reserved_at_1e8[0x5]; 2328 u8 log_max_num_of_packets_per_reservation[0x3]; 2329 u8 reserved_at_1f0[0x6]; 2330 u8 log_headers_entry_size[0x2]; 2331 u8 reserved_at_1f8[0x4]; 2332 u8 log_headers_buffer_entry_num[0x4]; 2333 2334 u8 reserved_at_200[0x400]; 2335 2336 struct mlx5_ifc_cmd_pas_bits pas[]; 2337 }; 2338 2339 struct mlx5_ifc_rq_num_bits { 2340 u8 reserved_at_0[0x8]; 2341 u8 rq_num[0x18]; 2342 }; 2343 2344 struct mlx5_ifc_rq_vhca_bits { 2345 u8 reserved_at_0[0x8]; 2346 u8 rq_num[0x18]; 2347 u8 reserved_at_20[0x10]; 2348 u8 rq_vhca_id[0x10]; 2349 }; 2350 2351 struct mlx5_ifc_mac_address_layout_bits { 2352 u8 reserved_at_0[0x10]; 2353 u8 mac_addr_47_32[0x10]; 2354 2355 u8 mac_addr_31_0[0x20]; 2356 }; 2357 2358 struct mlx5_ifc_vlan_layout_bits { 2359 u8 reserved_at_0[0x14]; 2360 u8 vlan[0x0c]; 2361 2362 u8 reserved_at_20[0x20]; 2363 }; 2364 2365 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits { 2366 u8 reserved_at_0[0xa0]; 2367 2368 u8 min_time_between_cnps[0x20]; 2369 2370 u8 reserved_at_c0[0x12]; 2371 u8 cnp_dscp[0x6]; 2372 u8 reserved_at_d8[0x4]; 2373 u8 cnp_prio_mode[0x1]; 2374 u8 cnp_802p_prio[0x3]; 2375 2376 u8 reserved_at_e0[0x720]; 2377 }; 2378 2379 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits { 2380 u8 reserved_at_0[0x60]; 2381 2382 u8 reserved_at_60[0x4]; 2383 u8 clamp_tgt_rate[0x1]; 2384 u8 reserved_at_65[0x3]; 2385 u8 clamp_tgt_rate_after_time_inc[0x1]; 2386 u8 reserved_at_69[0x17]; 2387 2388 u8 reserved_at_80[0x20]; 2389 2390 u8 rpg_time_reset[0x20]; 2391 2392 u8 rpg_byte_reset[0x20]; 2393 2394 u8 rpg_threshold[0x20]; 2395 2396 u8 rpg_max_rate[0x20]; 2397 2398 u8 rpg_ai_rate[0x20]; 2399 2400 u8 rpg_hai_rate[0x20]; 2401 2402 u8 rpg_gd[0x20]; 2403 2404 u8 rpg_min_dec_fac[0x20]; 2405 2406 u8 rpg_min_rate[0x20]; 2407 2408 u8 reserved_at_1c0[0xe0]; 2409 2410 u8 rate_to_set_on_first_cnp[0x20]; 2411 2412 u8 dce_tcp_g[0x20]; 2413 2414 u8 dce_tcp_rtt[0x20]; 2415 2416 u8 rate_reduce_monitor_period[0x20]; 2417 2418 u8 reserved_at_320[0x20]; 2419 2420 u8 initial_alpha_value[0x20]; 2421 2422 u8 reserved_at_360[0x4a0]; 2423 }; 2424 2425 struct mlx5_ifc_cong_control_r_roce_general_bits { 2426 u8 reserved_at_0[0x80]; 2427 2428 u8 reserved_at_80[0x10]; 2429 u8 rtt_resp_dscp_valid[0x1]; 2430 u8 reserved_at_91[0x9]; 2431 u8 rtt_resp_dscp[0x6]; 2432 2433 u8 reserved_at_a0[0x760]; 2434 }; 2435 2436 struct mlx5_ifc_cong_control_802_1qau_rp_bits { 2437 u8 reserved_at_0[0x80]; 2438 2439 u8 rppp_max_rps[0x20]; 2440 2441 u8 rpg_time_reset[0x20]; 2442 2443 u8 rpg_byte_reset[0x20]; 2444 2445 u8 rpg_threshold[0x20]; 2446 2447 u8 rpg_max_rate[0x20]; 2448 2449 u8 rpg_ai_rate[0x20]; 2450 2451 u8 rpg_hai_rate[0x20]; 2452 2453 u8 rpg_gd[0x20]; 2454 2455 u8 rpg_min_dec_fac[0x20]; 2456 2457 u8 rpg_min_rate[0x20]; 2458 2459 u8 reserved_at_1c0[0x640]; 2460 }; 2461 2462 enum { 2463 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1, 2464 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2, 2465 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4, 2466 }; 2467 2468 struct mlx5_ifc_resize_field_select_bits { 2469 u8 resize_field_select[0x20]; 2470 }; 2471 2472 struct mlx5_ifc_resource_dump_bits { 2473 u8 more_dump[0x1]; 2474 u8 inline_dump[0x1]; 2475 u8 reserved_at_2[0xa]; 2476 u8 seq_num[0x4]; 2477 u8 segment_type[0x10]; 2478 2479 u8 reserved_at_20[0x10]; 2480 u8 vhca_id[0x10]; 2481 2482 u8 index1[0x20]; 2483 2484 u8 index2[0x20]; 2485 2486 u8 num_of_obj1[0x10]; 2487 u8 num_of_obj2[0x10]; 2488 2489 u8 reserved_at_a0[0x20]; 2490 2491 u8 device_opaque[0x40]; 2492 2493 u8 mkey[0x20]; 2494 2495 u8 size[0x20]; 2496 2497 u8 address[0x40]; 2498 2499 u8 inline_data[52][0x20]; 2500 }; 2501 2502 struct mlx5_ifc_resource_dump_menu_record_bits { 2503 u8 reserved_at_0[0x4]; 2504 u8 num_of_obj2_supports_active[0x1]; 2505 u8 num_of_obj2_supports_all[0x1]; 2506 u8 must_have_num_of_obj2[0x1]; 2507 u8 support_num_of_obj2[0x1]; 2508 u8 num_of_obj1_supports_active[0x1]; 2509 u8 num_of_obj1_supports_all[0x1]; 2510 u8 must_have_num_of_obj1[0x1]; 2511 u8 support_num_of_obj1[0x1]; 2512 u8 must_have_index2[0x1]; 2513 u8 support_index2[0x1]; 2514 u8 must_have_index1[0x1]; 2515 u8 support_index1[0x1]; 2516 u8 segment_type[0x10]; 2517 2518 u8 segment_name[4][0x20]; 2519 2520 u8 index1_name[4][0x20]; 2521 2522 u8 index2_name[4][0x20]; 2523 }; 2524 2525 struct mlx5_ifc_resource_dump_segment_header_bits { 2526 u8 length_dw[0x10]; 2527 u8 segment_type[0x10]; 2528 }; 2529 2530 struct mlx5_ifc_resource_dump_command_segment_bits { 2531 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2532 2533 u8 segment_called[0x10]; 2534 u8 vhca_id[0x10]; 2535 2536 u8 index1[0x20]; 2537 2538 u8 index2[0x20]; 2539 2540 u8 num_of_obj1[0x10]; 2541 u8 num_of_obj2[0x10]; 2542 }; 2543 2544 struct mlx5_ifc_resource_dump_error_segment_bits { 2545 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2546 2547 u8 reserved_at_20[0x10]; 2548 u8 syndrome_id[0x10]; 2549 2550 u8 reserved_at_40[0x40]; 2551 2552 u8 error[8][0x20]; 2553 }; 2554 2555 struct mlx5_ifc_resource_dump_info_segment_bits { 2556 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2557 2558 u8 reserved_at_20[0x18]; 2559 u8 dump_version[0x8]; 2560 2561 u8 hw_version[0x20]; 2562 2563 u8 fw_version[0x20]; 2564 }; 2565 2566 struct mlx5_ifc_resource_dump_menu_segment_bits { 2567 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2568 2569 u8 reserved_at_20[0x10]; 2570 u8 num_of_records[0x10]; 2571 2572 struct mlx5_ifc_resource_dump_menu_record_bits record[]; 2573 }; 2574 2575 struct mlx5_ifc_resource_dump_resource_segment_bits { 2576 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2577 2578 u8 reserved_at_20[0x20]; 2579 2580 u8 index1[0x20]; 2581 2582 u8 index2[0x20]; 2583 2584 u8 payload[][0x20]; 2585 }; 2586 2587 struct mlx5_ifc_resource_dump_terminate_segment_bits { 2588 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2589 }; 2590 2591 struct mlx5_ifc_menu_resource_dump_response_bits { 2592 struct mlx5_ifc_resource_dump_info_segment_bits info; 2593 struct mlx5_ifc_resource_dump_command_segment_bits cmd; 2594 struct mlx5_ifc_resource_dump_menu_segment_bits menu; 2595 struct mlx5_ifc_resource_dump_terminate_segment_bits terminate; 2596 }; 2597 2598 enum { 2599 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1, 2600 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2, 2601 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4, 2602 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8, 2603 }; 2604 2605 struct mlx5_ifc_modify_field_select_bits { 2606 u8 modify_field_select[0x20]; 2607 }; 2608 2609 struct mlx5_ifc_field_select_r_roce_np_bits { 2610 u8 field_select_r_roce_np[0x20]; 2611 }; 2612 2613 struct mlx5_ifc_field_select_r_roce_rp_bits { 2614 u8 field_select_r_roce_rp[0x20]; 2615 }; 2616 2617 enum { 2618 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4, 2619 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8, 2620 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10, 2621 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20, 2622 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40, 2623 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80, 2624 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100, 2625 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200, 2626 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400, 2627 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800, 2628 }; 2629 2630 struct mlx5_ifc_field_select_802_1qau_rp_bits { 2631 u8 field_select_8021qaurp[0x20]; 2632 }; 2633 2634 struct mlx5_ifc_phys_layer_cntrs_bits { 2635 u8 time_since_last_clear_high[0x20]; 2636 2637 u8 time_since_last_clear_low[0x20]; 2638 2639 u8 symbol_errors_high[0x20]; 2640 2641 u8 symbol_errors_low[0x20]; 2642 2643 u8 sync_headers_errors_high[0x20]; 2644 2645 u8 sync_headers_errors_low[0x20]; 2646 2647 u8 edpl_bip_errors_lane0_high[0x20]; 2648 2649 u8 edpl_bip_errors_lane0_low[0x20]; 2650 2651 u8 edpl_bip_errors_lane1_high[0x20]; 2652 2653 u8 edpl_bip_errors_lane1_low[0x20]; 2654 2655 u8 edpl_bip_errors_lane2_high[0x20]; 2656 2657 u8 edpl_bip_errors_lane2_low[0x20]; 2658 2659 u8 edpl_bip_errors_lane3_high[0x20]; 2660 2661 u8 edpl_bip_errors_lane3_low[0x20]; 2662 2663 u8 fc_fec_corrected_blocks_lane0_high[0x20]; 2664 2665 u8 fc_fec_corrected_blocks_lane0_low[0x20]; 2666 2667 u8 fc_fec_corrected_blocks_lane1_high[0x20]; 2668 2669 u8 fc_fec_corrected_blocks_lane1_low[0x20]; 2670 2671 u8 fc_fec_corrected_blocks_lane2_high[0x20]; 2672 2673 u8 fc_fec_corrected_blocks_lane2_low[0x20]; 2674 2675 u8 fc_fec_corrected_blocks_lane3_high[0x20]; 2676 2677 u8 fc_fec_corrected_blocks_lane3_low[0x20]; 2678 2679 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20]; 2680 2681 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20]; 2682 2683 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20]; 2684 2685 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20]; 2686 2687 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20]; 2688 2689 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20]; 2690 2691 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20]; 2692 2693 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20]; 2694 2695 u8 rs_fec_corrected_blocks_high[0x20]; 2696 2697 u8 rs_fec_corrected_blocks_low[0x20]; 2698 2699 u8 rs_fec_uncorrectable_blocks_high[0x20]; 2700 2701 u8 rs_fec_uncorrectable_blocks_low[0x20]; 2702 2703 u8 rs_fec_no_errors_blocks_high[0x20]; 2704 2705 u8 rs_fec_no_errors_blocks_low[0x20]; 2706 2707 u8 rs_fec_single_error_blocks_high[0x20]; 2708 2709 u8 rs_fec_single_error_blocks_low[0x20]; 2710 2711 u8 rs_fec_corrected_symbols_total_high[0x20]; 2712 2713 u8 rs_fec_corrected_symbols_total_low[0x20]; 2714 2715 u8 rs_fec_corrected_symbols_lane0_high[0x20]; 2716 2717 u8 rs_fec_corrected_symbols_lane0_low[0x20]; 2718 2719 u8 rs_fec_corrected_symbols_lane1_high[0x20]; 2720 2721 u8 rs_fec_corrected_symbols_lane1_low[0x20]; 2722 2723 u8 rs_fec_corrected_symbols_lane2_high[0x20]; 2724 2725 u8 rs_fec_corrected_symbols_lane2_low[0x20]; 2726 2727 u8 rs_fec_corrected_symbols_lane3_high[0x20]; 2728 2729 u8 rs_fec_corrected_symbols_lane3_low[0x20]; 2730 2731 u8 link_down_events[0x20]; 2732 2733 u8 successful_recovery_events[0x20]; 2734 2735 u8 reserved_at_640[0x180]; 2736 }; 2737 2738 struct mlx5_ifc_phys_layer_statistical_cntrs_bits { 2739 u8 time_since_last_clear_high[0x20]; 2740 2741 u8 time_since_last_clear_low[0x20]; 2742 2743 u8 phy_received_bits_high[0x20]; 2744 2745 u8 phy_received_bits_low[0x20]; 2746 2747 u8 phy_symbol_errors_high[0x20]; 2748 2749 u8 phy_symbol_errors_low[0x20]; 2750 2751 u8 phy_corrected_bits_high[0x20]; 2752 2753 u8 phy_corrected_bits_low[0x20]; 2754 2755 u8 phy_corrected_bits_lane0_high[0x20]; 2756 2757 u8 phy_corrected_bits_lane0_low[0x20]; 2758 2759 u8 phy_corrected_bits_lane1_high[0x20]; 2760 2761 u8 phy_corrected_bits_lane1_low[0x20]; 2762 2763 u8 phy_corrected_bits_lane2_high[0x20]; 2764 2765 u8 phy_corrected_bits_lane2_low[0x20]; 2766 2767 u8 phy_corrected_bits_lane3_high[0x20]; 2768 2769 u8 phy_corrected_bits_lane3_low[0x20]; 2770 2771 u8 reserved_at_200[0x5c0]; 2772 }; 2773 2774 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits { 2775 u8 symbol_error_counter[0x10]; 2776 2777 u8 link_error_recovery_counter[0x8]; 2778 2779 u8 link_downed_counter[0x8]; 2780 2781 u8 port_rcv_errors[0x10]; 2782 2783 u8 port_rcv_remote_physical_errors[0x10]; 2784 2785 u8 port_rcv_switch_relay_errors[0x10]; 2786 2787 u8 port_xmit_discards[0x10]; 2788 2789 u8 port_xmit_constraint_errors[0x8]; 2790 2791 u8 port_rcv_constraint_errors[0x8]; 2792 2793 u8 reserved_at_70[0x8]; 2794 2795 u8 link_overrun_errors[0x8]; 2796 2797 u8 reserved_at_80[0x10]; 2798 2799 u8 vl_15_dropped[0x10]; 2800 2801 u8 reserved_at_a0[0x80]; 2802 2803 u8 port_xmit_wait[0x20]; 2804 }; 2805 2806 struct mlx5_ifc_ib_ext_port_cntrs_grp_data_layout_bits { 2807 u8 reserved_at_0[0x300]; 2808 2809 u8 port_xmit_data_high[0x20]; 2810 2811 u8 port_xmit_data_low[0x20]; 2812 2813 u8 port_rcv_data_high[0x20]; 2814 2815 u8 port_rcv_data_low[0x20]; 2816 2817 u8 port_xmit_pkts_high[0x20]; 2818 2819 u8 port_xmit_pkts_low[0x20]; 2820 2821 u8 port_rcv_pkts_high[0x20]; 2822 2823 u8 port_rcv_pkts_low[0x20]; 2824 2825 u8 reserved_at_400[0x80]; 2826 2827 u8 port_unicast_xmit_pkts_high[0x20]; 2828 2829 u8 port_unicast_xmit_pkts_low[0x20]; 2830 2831 u8 port_multicast_xmit_pkts_high[0x20]; 2832 2833 u8 port_multicast_xmit_pkts_low[0x20]; 2834 2835 u8 port_unicast_rcv_pkts_high[0x20]; 2836 2837 u8 port_unicast_rcv_pkts_low[0x20]; 2838 2839 u8 port_multicast_rcv_pkts_high[0x20]; 2840 2841 u8 port_multicast_rcv_pkts_low[0x20]; 2842 2843 u8 reserved_at_580[0x240]; 2844 }; 2845 2846 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits { 2847 u8 transmit_queue_high[0x20]; 2848 2849 u8 transmit_queue_low[0x20]; 2850 2851 u8 no_buffer_discard_uc_high[0x20]; 2852 2853 u8 no_buffer_discard_uc_low[0x20]; 2854 2855 u8 reserved_at_80[0x740]; 2856 }; 2857 2858 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits { 2859 u8 wred_discard_high[0x20]; 2860 2861 u8 wred_discard_low[0x20]; 2862 2863 u8 ecn_marked_tc_high[0x20]; 2864 2865 u8 ecn_marked_tc_low[0x20]; 2866 2867 u8 reserved_at_80[0x740]; 2868 }; 2869 2870 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits { 2871 u8 rx_octets_high[0x20]; 2872 2873 u8 rx_octets_low[0x20]; 2874 2875 u8 reserved_at_40[0xc0]; 2876 2877 u8 rx_frames_high[0x20]; 2878 2879 u8 rx_frames_low[0x20]; 2880 2881 u8 tx_octets_high[0x20]; 2882 2883 u8 tx_octets_low[0x20]; 2884 2885 u8 reserved_at_180[0xc0]; 2886 2887 u8 tx_frames_high[0x20]; 2888 2889 u8 tx_frames_low[0x20]; 2890 2891 u8 rx_pause_high[0x20]; 2892 2893 u8 rx_pause_low[0x20]; 2894 2895 u8 rx_pause_duration_high[0x20]; 2896 2897 u8 rx_pause_duration_low[0x20]; 2898 2899 u8 tx_pause_high[0x20]; 2900 2901 u8 tx_pause_low[0x20]; 2902 2903 u8 tx_pause_duration_high[0x20]; 2904 2905 u8 tx_pause_duration_low[0x20]; 2906 2907 u8 rx_pause_transition_high[0x20]; 2908 2909 u8 rx_pause_transition_low[0x20]; 2910 2911 u8 rx_discards_high[0x20]; 2912 2913 u8 rx_discards_low[0x20]; 2914 2915 u8 device_stall_minor_watermark_cnt_high[0x20]; 2916 2917 u8 device_stall_minor_watermark_cnt_low[0x20]; 2918 2919 u8 device_stall_critical_watermark_cnt_high[0x20]; 2920 2921 u8 device_stall_critical_watermark_cnt_low[0x20]; 2922 2923 u8 reserved_at_480[0x340]; 2924 }; 2925 2926 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits { 2927 u8 port_transmit_wait_high[0x20]; 2928 2929 u8 port_transmit_wait_low[0x20]; 2930 2931 u8 reserved_at_40[0x100]; 2932 2933 u8 rx_buffer_almost_full_high[0x20]; 2934 2935 u8 rx_buffer_almost_full_low[0x20]; 2936 2937 u8 rx_buffer_full_high[0x20]; 2938 2939 u8 rx_buffer_full_low[0x20]; 2940 2941 u8 rx_icrc_encapsulated_high[0x20]; 2942 2943 u8 rx_icrc_encapsulated_low[0x20]; 2944 2945 u8 reserved_at_200[0x5c0]; 2946 }; 2947 2948 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits { 2949 u8 dot3stats_alignment_errors_high[0x20]; 2950 2951 u8 dot3stats_alignment_errors_low[0x20]; 2952 2953 u8 dot3stats_fcs_errors_high[0x20]; 2954 2955 u8 dot3stats_fcs_errors_low[0x20]; 2956 2957 u8 dot3stats_single_collision_frames_high[0x20]; 2958 2959 u8 dot3stats_single_collision_frames_low[0x20]; 2960 2961 u8 dot3stats_multiple_collision_frames_high[0x20]; 2962 2963 u8 dot3stats_multiple_collision_frames_low[0x20]; 2964 2965 u8 dot3stats_sqe_test_errors_high[0x20]; 2966 2967 u8 dot3stats_sqe_test_errors_low[0x20]; 2968 2969 u8 dot3stats_deferred_transmissions_high[0x20]; 2970 2971 u8 dot3stats_deferred_transmissions_low[0x20]; 2972 2973 u8 dot3stats_late_collisions_high[0x20]; 2974 2975 u8 dot3stats_late_collisions_low[0x20]; 2976 2977 u8 dot3stats_excessive_collisions_high[0x20]; 2978 2979 u8 dot3stats_excessive_collisions_low[0x20]; 2980 2981 u8 dot3stats_internal_mac_transmit_errors_high[0x20]; 2982 2983 u8 dot3stats_internal_mac_transmit_errors_low[0x20]; 2984 2985 u8 dot3stats_carrier_sense_errors_high[0x20]; 2986 2987 u8 dot3stats_carrier_sense_errors_low[0x20]; 2988 2989 u8 dot3stats_frame_too_longs_high[0x20]; 2990 2991 u8 dot3stats_frame_too_longs_low[0x20]; 2992 2993 u8 dot3stats_internal_mac_receive_errors_high[0x20]; 2994 2995 u8 dot3stats_internal_mac_receive_errors_low[0x20]; 2996 2997 u8 dot3stats_symbol_errors_high[0x20]; 2998 2999 u8 dot3stats_symbol_errors_low[0x20]; 3000 3001 u8 dot3control_in_unknown_opcodes_high[0x20]; 3002 3003 u8 dot3control_in_unknown_opcodes_low[0x20]; 3004 3005 u8 dot3in_pause_frames_high[0x20]; 3006 3007 u8 dot3in_pause_frames_low[0x20]; 3008 3009 u8 dot3out_pause_frames_high[0x20]; 3010 3011 u8 dot3out_pause_frames_low[0x20]; 3012 3013 u8 reserved_at_400[0x3c0]; 3014 }; 3015 3016 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits { 3017 u8 ether_stats_drop_events_high[0x20]; 3018 3019 u8 ether_stats_drop_events_low[0x20]; 3020 3021 u8 ether_stats_octets_high[0x20]; 3022 3023 u8 ether_stats_octets_low[0x20]; 3024 3025 u8 ether_stats_pkts_high[0x20]; 3026 3027 u8 ether_stats_pkts_low[0x20]; 3028 3029 u8 ether_stats_broadcast_pkts_high[0x20]; 3030 3031 u8 ether_stats_broadcast_pkts_low[0x20]; 3032 3033 u8 ether_stats_multicast_pkts_high[0x20]; 3034 3035 u8 ether_stats_multicast_pkts_low[0x20]; 3036 3037 u8 ether_stats_crc_align_errors_high[0x20]; 3038 3039 u8 ether_stats_crc_align_errors_low[0x20]; 3040 3041 u8 ether_stats_undersize_pkts_high[0x20]; 3042 3043 u8 ether_stats_undersize_pkts_low[0x20]; 3044 3045 u8 ether_stats_oversize_pkts_high[0x20]; 3046 3047 u8 ether_stats_oversize_pkts_low[0x20]; 3048 3049 u8 ether_stats_fragments_high[0x20]; 3050 3051 u8 ether_stats_fragments_low[0x20]; 3052 3053 u8 ether_stats_jabbers_high[0x20]; 3054 3055 u8 ether_stats_jabbers_low[0x20]; 3056 3057 u8 ether_stats_collisions_high[0x20]; 3058 3059 u8 ether_stats_collisions_low[0x20]; 3060 3061 u8 ether_stats_pkts64octets_high[0x20]; 3062 3063 u8 ether_stats_pkts64octets_low[0x20]; 3064 3065 u8 ether_stats_pkts65to127octets_high[0x20]; 3066 3067 u8 ether_stats_pkts65to127octets_low[0x20]; 3068 3069 u8 ether_stats_pkts128to255octets_high[0x20]; 3070 3071 u8 ether_stats_pkts128to255octets_low[0x20]; 3072 3073 u8 ether_stats_pkts256to511octets_high[0x20]; 3074 3075 u8 ether_stats_pkts256to511octets_low[0x20]; 3076 3077 u8 ether_stats_pkts512to1023octets_high[0x20]; 3078 3079 u8 ether_stats_pkts512to1023octets_low[0x20]; 3080 3081 u8 ether_stats_pkts1024to1518octets_high[0x20]; 3082 3083 u8 ether_stats_pkts1024to1518octets_low[0x20]; 3084 3085 u8 ether_stats_pkts1519to2047octets_high[0x20]; 3086 3087 u8 ether_stats_pkts1519to2047octets_low[0x20]; 3088 3089 u8 ether_stats_pkts2048to4095octets_high[0x20]; 3090 3091 u8 ether_stats_pkts2048to4095octets_low[0x20]; 3092 3093 u8 ether_stats_pkts4096to8191octets_high[0x20]; 3094 3095 u8 ether_stats_pkts4096to8191octets_low[0x20]; 3096 3097 u8 ether_stats_pkts8192to10239octets_high[0x20]; 3098 3099 u8 ether_stats_pkts8192to10239octets_low[0x20]; 3100 3101 u8 reserved_at_540[0x280]; 3102 }; 3103 3104 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits { 3105 u8 if_in_octets_high[0x20]; 3106 3107 u8 if_in_octets_low[0x20]; 3108 3109 u8 if_in_ucast_pkts_high[0x20]; 3110 3111 u8 if_in_ucast_pkts_low[0x20]; 3112 3113 u8 if_in_discards_high[0x20]; 3114 3115 u8 if_in_discards_low[0x20]; 3116 3117 u8 if_in_errors_high[0x20]; 3118 3119 u8 if_in_errors_low[0x20]; 3120 3121 u8 if_in_unknown_protos_high[0x20]; 3122 3123 u8 if_in_unknown_protos_low[0x20]; 3124 3125 u8 if_out_octets_high[0x20]; 3126 3127 u8 if_out_octets_low[0x20]; 3128 3129 u8 if_out_ucast_pkts_high[0x20]; 3130 3131 u8 if_out_ucast_pkts_low[0x20]; 3132 3133 u8 if_out_discards_high[0x20]; 3134 3135 u8 if_out_discards_low[0x20]; 3136 3137 u8 if_out_errors_high[0x20]; 3138 3139 u8 if_out_errors_low[0x20]; 3140 3141 u8 if_in_multicast_pkts_high[0x20]; 3142 3143 u8 if_in_multicast_pkts_low[0x20]; 3144 3145 u8 if_in_broadcast_pkts_high[0x20]; 3146 3147 u8 if_in_broadcast_pkts_low[0x20]; 3148 3149 u8 if_out_multicast_pkts_high[0x20]; 3150 3151 u8 if_out_multicast_pkts_low[0x20]; 3152 3153 u8 if_out_broadcast_pkts_high[0x20]; 3154 3155 u8 if_out_broadcast_pkts_low[0x20]; 3156 3157 u8 reserved_at_340[0x480]; 3158 }; 3159 3160 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits { 3161 u8 a_frames_transmitted_ok_high[0x20]; 3162 3163 u8 a_frames_transmitted_ok_low[0x20]; 3164 3165 u8 a_frames_received_ok_high[0x20]; 3166 3167 u8 a_frames_received_ok_low[0x20]; 3168 3169 u8 a_frame_check_sequence_errors_high[0x20]; 3170 3171 u8 a_frame_check_sequence_errors_low[0x20]; 3172 3173 u8 a_alignment_errors_high[0x20]; 3174 3175 u8 a_alignment_errors_low[0x20]; 3176 3177 u8 a_octets_transmitted_ok_high[0x20]; 3178 3179 u8 a_octets_transmitted_ok_low[0x20]; 3180 3181 u8 a_octets_received_ok_high[0x20]; 3182 3183 u8 a_octets_received_ok_low[0x20]; 3184 3185 u8 a_multicast_frames_xmitted_ok_high[0x20]; 3186 3187 u8 a_multicast_frames_xmitted_ok_low[0x20]; 3188 3189 u8 a_broadcast_frames_xmitted_ok_high[0x20]; 3190 3191 u8 a_broadcast_frames_xmitted_ok_low[0x20]; 3192 3193 u8 a_multicast_frames_received_ok_high[0x20]; 3194 3195 u8 a_multicast_frames_received_ok_low[0x20]; 3196 3197 u8 a_broadcast_frames_received_ok_high[0x20]; 3198 3199 u8 a_broadcast_frames_received_ok_low[0x20]; 3200 3201 u8 a_in_range_length_errors_high[0x20]; 3202 3203 u8 a_in_range_length_errors_low[0x20]; 3204 3205 u8 a_out_of_range_length_field_high[0x20]; 3206 3207 u8 a_out_of_range_length_field_low[0x20]; 3208 3209 u8 a_frame_too_long_errors_high[0x20]; 3210 3211 u8 a_frame_too_long_errors_low[0x20]; 3212 3213 u8 a_symbol_error_during_carrier_high[0x20]; 3214 3215 u8 a_symbol_error_during_carrier_low[0x20]; 3216 3217 u8 a_mac_control_frames_transmitted_high[0x20]; 3218 3219 u8 a_mac_control_frames_transmitted_low[0x20]; 3220 3221 u8 a_mac_control_frames_received_high[0x20]; 3222 3223 u8 a_mac_control_frames_received_low[0x20]; 3224 3225 u8 a_unsupported_opcodes_received_high[0x20]; 3226 3227 u8 a_unsupported_opcodes_received_low[0x20]; 3228 3229 u8 a_pause_mac_ctrl_frames_received_high[0x20]; 3230 3231 u8 a_pause_mac_ctrl_frames_received_low[0x20]; 3232 3233 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20]; 3234 3235 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20]; 3236 3237 u8 reserved_at_4c0[0x300]; 3238 }; 3239 3240 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits { 3241 u8 life_time_counter_high[0x20]; 3242 3243 u8 life_time_counter_low[0x20]; 3244 3245 u8 rx_errors[0x20]; 3246 3247 u8 tx_errors[0x20]; 3248 3249 u8 l0_to_recovery_eieos[0x20]; 3250 3251 u8 l0_to_recovery_ts[0x20]; 3252 3253 u8 l0_to_recovery_framing[0x20]; 3254 3255 u8 l0_to_recovery_retrain[0x20]; 3256 3257 u8 crc_error_dllp[0x20]; 3258 3259 u8 crc_error_tlp[0x20]; 3260 3261 u8 tx_overflow_buffer_pkt_high[0x20]; 3262 3263 u8 tx_overflow_buffer_pkt_low[0x20]; 3264 3265 u8 outbound_stalled_reads[0x20]; 3266 3267 u8 outbound_stalled_writes[0x20]; 3268 3269 u8 outbound_stalled_reads_events[0x20]; 3270 3271 u8 outbound_stalled_writes_events[0x20]; 3272 3273 u8 reserved_at_200[0x5c0]; 3274 }; 3275 3276 struct mlx5_ifc_cmd_inter_comp_event_bits { 3277 u8 command_completion_vector[0x20]; 3278 3279 u8 reserved_at_20[0xc0]; 3280 }; 3281 3282 struct mlx5_ifc_stall_vl_event_bits { 3283 u8 reserved_at_0[0x18]; 3284 u8 port_num[0x1]; 3285 u8 reserved_at_19[0x3]; 3286 u8 vl[0x4]; 3287 3288 u8 reserved_at_20[0xa0]; 3289 }; 3290 3291 struct mlx5_ifc_db_bf_congestion_event_bits { 3292 u8 event_subtype[0x8]; 3293 u8 reserved_at_8[0x8]; 3294 u8 congestion_level[0x8]; 3295 u8 reserved_at_18[0x8]; 3296 3297 u8 reserved_at_20[0xa0]; 3298 }; 3299 3300 struct mlx5_ifc_gpio_event_bits { 3301 u8 reserved_at_0[0x60]; 3302 3303 u8 gpio_event_hi[0x20]; 3304 3305 u8 gpio_event_lo[0x20]; 3306 3307 u8 reserved_at_a0[0x40]; 3308 }; 3309 3310 struct mlx5_ifc_port_state_change_event_bits { 3311 u8 reserved_at_0[0x40]; 3312 3313 u8 port_num[0x4]; 3314 u8 reserved_at_44[0x1c]; 3315 3316 u8 reserved_at_60[0x80]; 3317 }; 3318 3319 struct mlx5_ifc_dropped_packet_logged_bits { 3320 u8 reserved_at_0[0xe0]; 3321 }; 3322 3323 struct mlx5_ifc_default_timeout_bits { 3324 u8 to_multiplier[0x3]; 3325 u8 reserved_at_3[0x9]; 3326 u8 to_value[0x14]; 3327 }; 3328 3329 struct mlx5_ifc_dtor_reg_bits { 3330 u8 reserved_at_0[0x20]; 3331 3332 struct mlx5_ifc_default_timeout_bits pcie_toggle_to; 3333 3334 u8 reserved_at_40[0x60]; 3335 3336 struct mlx5_ifc_default_timeout_bits health_poll_to; 3337 3338 struct mlx5_ifc_default_timeout_bits full_crdump_to; 3339 3340 struct mlx5_ifc_default_timeout_bits fw_reset_to; 3341 3342 struct mlx5_ifc_default_timeout_bits flush_on_err_to; 3343 3344 struct mlx5_ifc_default_timeout_bits pci_sync_update_to; 3345 3346 struct mlx5_ifc_default_timeout_bits tear_down_to; 3347 3348 struct mlx5_ifc_default_timeout_bits fsm_reactivate_to; 3349 3350 struct mlx5_ifc_default_timeout_bits reclaim_pages_to; 3351 3352 struct mlx5_ifc_default_timeout_bits reclaim_vfs_pages_to; 3353 3354 struct mlx5_ifc_default_timeout_bits reset_unload_to; 3355 3356 u8 reserved_at_1c0[0x20]; 3357 }; 3358 3359 enum { 3360 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1, 3361 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2, 3362 }; 3363 3364 struct mlx5_ifc_cq_error_bits { 3365 u8 reserved_at_0[0x8]; 3366 u8 cqn[0x18]; 3367 3368 u8 reserved_at_20[0x20]; 3369 3370 u8 reserved_at_40[0x18]; 3371 u8 syndrome[0x8]; 3372 3373 u8 reserved_at_60[0x80]; 3374 }; 3375 3376 struct mlx5_ifc_rdma_page_fault_event_bits { 3377 u8 bytes_committed[0x20]; 3378 3379 u8 r_key[0x20]; 3380 3381 u8 reserved_at_40[0x10]; 3382 u8 packet_len[0x10]; 3383 3384 u8 rdma_op_len[0x20]; 3385 3386 u8 rdma_va[0x40]; 3387 3388 u8 reserved_at_c0[0x5]; 3389 u8 rdma[0x1]; 3390 u8 write[0x1]; 3391 u8 requestor[0x1]; 3392 u8 qp_number[0x18]; 3393 }; 3394 3395 struct mlx5_ifc_wqe_associated_page_fault_event_bits { 3396 u8 bytes_committed[0x20]; 3397 3398 u8 reserved_at_20[0x10]; 3399 u8 wqe_index[0x10]; 3400 3401 u8 reserved_at_40[0x10]; 3402 u8 len[0x10]; 3403 3404 u8 reserved_at_60[0x60]; 3405 3406 u8 reserved_at_c0[0x5]; 3407 u8 rdma[0x1]; 3408 u8 write_read[0x1]; 3409 u8 requestor[0x1]; 3410 u8 qpn[0x18]; 3411 }; 3412 3413 struct mlx5_ifc_qp_events_bits { 3414 u8 reserved_at_0[0xa0]; 3415 3416 u8 type[0x8]; 3417 u8 reserved_at_a8[0x18]; 3418 3419 u8 reserved_at_c0[0x8]; 3420 u8 qpn_rqn_sqn[0x18]; 3421 }; 3422 3423 struct mlx5_ifc_dct_events_bits { 3424 u8 reserved_at_0[0xc0]; 3425 3426 u8 reserved_at_c0[0x8]; 3427 u8 dct_number[0x18]; 3428 }; 3429 3430 struct mlx5_ifc_comp_event_bits { 3431 u8 reserved_at_0[0xc0]; 3432 3433 u8 reserved_at_c0[0x8]; 3434 u8 cq_number[0x18]; 3435 }; 3436 3437 enum { 3438 MLX5_QPC_STATE_RST = 0x0, 3439 MLX5_QPC_STATE_INIT = 0x1, 3440 MLX5_QPC_STATE_RTR = 0x2, 3441 MLX5_QPC_STATE_RTS = 0x3, 3442 MLX5_QPC_STATE_SQER = 0x4, 3443 MLX5_QPC_STATE_ERR = 0x6, 3444 MLX5_QPC_STATE_SQD = 0x7, 3445 MLX5_QPC_STATE_SUSPENDED = 0x9, 3446 }; 3447 3448 enum { 3449 MLX5_QPC_ST_RC = 0x0, 3450 MLX5_QPC_ST_UC = 0x1, 3451 MLX5_QPC_ST_UD = 0x2, 3452 MLX5_QPC_ST_XRC = 0x3, 3453 MLX5_QPC_ST_DCI = 0x5, 3454 MLX5_QPC_ST_QP0 = 0x7, 3455 MLX5_QPC_ST_QP1 = 0x8, 3456 MLX5_QPC_ST_RAW_DATAGRAM = 0x9, 3457 MLX5_QPC_ST_REG_UMR = 0xc, 3458 }; 3459 3460 enum { 3461 MLX5_QPC_PM_STATE_ARMED = 0x0, 3462 MLX5_QPC_PM_STATE_REARM = 0x1, 3463 MLX5_QPC_PM_STATE_RESERVED = 0x2, 3464 MLX5_QPC_PM_STATE_MIGRATED = 0x3, 3465 }; 3466 3467 enum { 3468 MLX5_QPC_OFFLOAD_TYPE_RNDV = 0x1, 3469 }; 3470 3471 enum { 3472 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0, 3473 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1, 3474 }; 3475 3476 enum { 3477 MLX5_QPC_MTU_256_BYTES = 0x1, 3478 MLX5_QPC_MTU_512_BYTES = 0x2, 3479 MLX5_QPC_MTU_1K_BYTES = 0x3, 3480 MLX5_QPC_MTU_2K_BYTES = 0x4, 3481 MLX5_QPC_MTU_4K_BYTES = 0x5, 3482 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7, 3483 }; 3484 3485 enum { 3486 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1, 3487 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2, 3488 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3, 3489 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4, 3490 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5, 3491 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6, 3492 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7, 3493 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8, 3494 }; 3495 3496 enum { 3497 MLX5_QPC_CS_REQ_DISABLE = 0x0, 3498 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11, 3499 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22, 3500 }; 3501 3502 enum { 3503 MLX5_QPC_CS_RES_DISABLE = 0x0, 3504 MLX5_QPC_CS_RES_UP_TO_32B = 0x1, 3505 MLX5_QPC_CS_RES_UP_TO_64B = 0x2, 3506 }; 3507 3508 enum { 3509 MLX5_TIMESTAMP_FORMAT_FREE_RUNNING = 0x0, 3510 MLX5_TIMESTAMP_FORMAT_DEFAULT = 0x1, 3511 MLX5_TIMESTAMP_FORMAT_REAL_TIME = 0x2, 3512 }; 3513 3514 struct mlx5_ifc_qpc_bits { 3515 u8 state[0x4]; 3516 u8 lag_tx_port_affinity[0x4]; 3517 u8 st[0x8]; 3518 u8 reserved_at_10[0x2]; 3519 u8 isolate_vl_tc[0x1]; 3520 u8 pm_state[0x2]; 3521 u8 reserved_at_15[0x1]; 3522 u8 req_e2e_credit_mode[0x2]; 3523 u8 offload_type[0x4]; 3524 u8 end_padding_mode[0x2]; 3525 u8 reserved_at_1e[0x2]; 3526 3527 u8 wq_signature[0x1]; 3528 u8 block_lb_mc[0x1]; 3529 u8 atomic_like_write_en[0x1]; 3530 u8 latency_sensitive[0x1]; 3531 u8 reserved_at_24[0x1]; 3532 u8 drain_sigerr[0x1]; 3533 u8 reserved_at_26[0x1]; 3534 u8 dp_ordering_force[0x1]; 3535 u8 pd[0x18]; 3536 3537 u8 mtu[0x3]; 3538 u8 log_msg_max[0x5]; 3539 u8 reserved_at_48[0x1]; 3540 u8 log_rq_size[0x4]; 3541 u8 log_rq_stride[0x3]; 3542 u8 no_sq[0x1]; 3543 u8 log_sq_size[0x4]; 3544 u8 reserved_at_55[0x1]; 3545 u8 retry_mode[0x2]; 3546 u8 ts_format[0x2]; 3547 u8 reserved_at_5a[0x1]; 3548 u8 rlky[0x1]; 3549 u8 ulp_stateless_offload_mode[0x4]; 3550 3551 u8 counter_set_id[0x8]; 3552 u8 uar_page[0x18]; 3553 3554 u8 reserved_at_80[0x8]; 3555 u8 user_index[0x18]; 3556 3557 u8 reserved_at_a0[0x3]; 3558 u8 log_page_size[0x5]; 3559 u8 remote_qpn[0x18]; 3560 3561 struct mlx5_ifc_ads_bits primary_address_path; 3562 3563 struct mlx5_ifc_ads_bits secondary_address_path; 3564 3565 u8 log_ack_req_freq[0x4]; 3566 u8 reserved_at_384[0x4]; 3567 u8 log_sra_max[0x3]; 3568 u8 reserved_at_38b[0x2]; 3569 u8 retry_count[0x3]; 3570 u8 rnr_retry[0x3]; 3571 u8 reserved_at_393[0x1]; 3572 u8 fre[0x1]; 3573 u8 cur_rnr_retry[0x3]; 3574 u8 cur_retry_count[0x3]; 3575 u8 reserved_at_39b[0x5]; 3576 3577 u8 reserved_at_3a0[0x20]; 3578 3579 u8 reserved_at_3c0[0x8]; 3580 u8 next_send_psn[0x18]; 3581 3582 u8 reserved_at_3e0[0x3]; 3583 u8 log_num_dci_stream_channels[0x5]; 3584 u8 cqn_snd[0x18]; 3585 3586 u8 reserved_at_400[0x3]; 3587 u8 log_num_dci_errored_streams[0x5]; 3588 u8 deth_sqpn[0x18]; 3589 3590 u8 reserved_at_420[0x20]; 3591 3592 u8 reserved_at_440[0x8]; 3593 u8 last_acked_psn[0x18]; 3594 3595 u8 reserved_at_460[0x8]; 3596 u8 ssn[0x18]; 3597 3598 u8 reserved_at_480[0x8]; 3599 u8 log_rra_max[0x3]; 3600 u8 reserved_at_48b[0x1]; 3601 u8 atomic_mode[0x4]; 3602 u8 rre[0x1]; 3603 u8 rwe[0x1]; 3604 u8 rae[0x1]; 3605 u8 reserved_at_493[0x1]; 3606 u8 page_offset[0x6]; 3607 u8 reserved_at_49a[0x2]; 3608 u8 dp_ordering_1[0x1]; 3609 u8 cd_slave_receive[0x1]; 3610 u8 cd_slave_send[0x1]; 3611 u8 cd_master[0x1]; 3612 3613 u8 reserved_at_4a0[0x3]; 3614 u8 min_rnr_nak[0x5]; 3615 u8 next_rcv_psn[0x18]; 3616 3617 u8 reserved_at_4c0[0x8]; 3618 u8 xrcd[0x18]; 3619 3620 u8 reserved_at_4e0[0x8]; 3621 u8 cqn_rcv[0x18]; 3622 3623 u8 dbr_addr[0x40]; 3624 3625 u8 q_key[0x20]; 3626 3627 u8 reserved_at_560[0x5]; 3628 u8 rq_type[0x3]; 3629 u8 srqn_rmpn_xrqn[0x18]; 3630 3631 u8 reserved_at_580[0x8]; 3632 u8 rmsn[0x18]; 3633 3634 u8 hw_sq_wqebb_counter[0x10]; 3635 u8 sw_sq_wqebb_counter[0x10]; 3636 3637 u8 hw_rq_counter[0x20]; 3638 3639 u8 sw_rq_counter[0x20]; 3640 3641 u8 reserved_at_600[0x20]; 3642 3643 u8 reserved_at_620[0xf]; 3644 u8 cgs[0x1]; 3645 u8 cs_req[0x8]; 3646 u8 cs_res[0x8]; 3647 3648 u8 dc_access_key[0x40]; 3649 3650 u8 reserved_at_680[0x3]; 3651 u8 dbr_umem_valid[0x1]; 3652 3653 u8 reserved_at_684[0xbc]; 3654 }; 3655 3656 struct mlx5_ifc_roce_addr_layout_bits { 3657 u8 source_l3_address[16][0x8]; 3658 3659 u8 reserved_at_80[0x3]; 3660 u8 vlan_valid[0x1]; 3661 u8 vlan_id[0xc]; 3662 u8 source_mac_47_32[0x10]; 3663 3664 u8 source_mac_31_0[0x20]; 3665 3666 u8 reserved_at_c0[0x14]; 3667 u8 roce_l3_type[0x4]; 3668 u8 roce_version[0x8]; 3669 3670 u8 reserved_at_e0[0x20]; 3671 }; 3672 3673 struct mlx5_ifc_crypto_cap_bits { 3674 u8 reserved_at_0[0x3]; 3675 u8 synchronize_dek[0x1]; 3676 u8 int_kek_manual[0x1]; 3677 u8 int_kek_auto[0x1]; 3678 u8 reserved_at_6[0x1a]; 3679 3680 u8 reserved_at_20[0x3]; 3681 u8 log_dek_max_alloc[0x5]; 3682 u8 reserved_at_28[0x3]; 3683 u8 log_max_num_deks[0x5]; 3684 u8 reserved_at_30[0x10]; 3685 3686 u8 reserved_at_40[0x20]; 3687 3688 u8 reserved_at_60[0x3]; 3689 u8 log_dek_granularity[0x5]; 3690 u8 reserved_at_68[0x3]; 3691 u8 log_max_num_int_kek[0x5]; 3692 u8 sw_wrapped_dek[0x10]; 3693 3694 u8 reserved_at_80[0x780]; 3695 }; 3696 3697 union mlx5_ifc_hca_cap_union_bits { 3698 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap; 3699 struct mlx5_ifc_cmd_hca_cap_2_bits cmd_hca_cap_2; 3700 struct mlx5_ifc_odp_cap_bits odp_cap; 3701 struct mlx5_ifc_atomic_caps_bits atomic_caps; 3702 struct mlx5_ifc_roce_cap_bits roce_cap; 3703 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps; 3704 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap; 3705 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap; 3706 struct mlx5_ifc_wqe_based_flow_table_cap_bits wqe_based_flow_table_cap; 3707 struct mlx5_ifc_esw_cap_bits esw_cap; 3708 struct mlx5_ifc_e_switch_cap_bits e_switch_cap; 3709 struct mlx5_ifc_port_selection_cap_bits port_selection_cap; 3710 struct mlx5_ifc_qos_cap_bits qos_cap; 3711 struct mlx5_ifc_debug_cap_bits debug_cap; 3712 struct mlx5_ifc_fpga_cap_bits fpga_cap; 3713 struct mlx5_ifc_tls_cap_bits tls_cap; 3714 struct mlx5_ifc_device_mem_cap_bits device_mem_cap; 3715 struct mlx5_ifc_virtio_emulation_cap_bits virtio_emulation_cap; 3716 struct mlx5_ifc_macsec_cap_bits macsec_cap; 3717 struct mlx5_ifc_crypto_cap_bits crypto_cap; 3718 struct mlx5_ifc_ipsec_cap_bits ipsec_cap; 3719 u8 reserved_at_0[0x8000]; 3720 }; 3721 3722 enum { 3723 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1, 3724 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2, 3725 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4, 3726 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8, 3727 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT = 0x10, 3728 MLX5_FLOW_CONTEXT_ACTION_DECAP = 0x20, 3729 MLX5_FLOW_CONTEXT_ACTION_MOD_HDR = 0x40, 3730 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP = 0x80, 3731 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100, 3732 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2 = 0x400, 3733 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2 = 0x800, 3734 MLX5_FLOW_CONTEXT_ACTION_CRYPTO_DECRYPT = 0x1000, 3735 MLX5_FLOW_CONTEXT_ACTION_CRYPTO_ENCRYPT = 0x2000, 3736 MLX5_FLOW_CONTEXT_ACTION_EXECUTE_ASO = 0x4000, 3737 }; 3738 3739 enum { 3740 MLX5_FLOW_CONTEXT_FLOW_SOURCE_ANY_VPORT = 0x0, 3741 MLX5_FLOW_CONTEXT_FLOW_SOURCE_UPLINK = 0x1, 3742 MLX5_FLOW_CONTEXT_FLOW_SOURCE_LOCAL_VPORT = 0x2, 3743 }; 3744 3745 enum { 3746 MLX5_FLOW_CONTEXT_ENCRYPT_DECRYPT_TYPE_IPSEC = 0x0, 3747 MLX5_FLOW_CONTEXT_ENCRYPT_DECRYPT_TYPE_MACSEC = 0x1, 3748 }; 3749 3750 struct mlx5_ifc_vlan_bits { 3751 u8 ethtype[0x10]; 3752 u8 prio[0x3]; 3753 u8 cfi[0x1]; 3754 u8 vid[0xc]; 3755 }; 3756 3757 enum { 3758 MLX5_FLOW_METER_COLOR_RED = 0x0, 3759 MLX5_FLOW_METER_COLOR_YELLOW = 0x1, 3760 MLX5_FLOW_METER_COLOR_GREEN = 0x2, 3761 MLX5_FLOW_METER_COLOR_UNDEFINED = 0x3, 3762 }; 3763 3764 enum { 3765 MLX5_EXE_ASO_FLOW_METER = 0x2, 3766 }; 3767 3768 struct mlx5_ifc_exe_aso_ctrl_flow_meter_bits { 3769 u8 return_reg_id[0x4]; 3770 u8 aso_type[0x4]; 3771 u8 reserved_at_8[0x14]; 3772 u8 action[0x1]; 3773 u8 init_color[0x2]; 3774 u8 meter_id[0x1]; 3775 }; 3776 3777 union mlx5_ifc_exe_aso_ctrl { 3778 struct mlx5_ifc_exe_aso_ctrl_flow_meter_bits exe_aso_ctrl_flow_meter; 3779 }; 3780 3781 struct mlx5_ifc_execute_aso_bits { 3782 u8 valid[0x1]; 3783 u8 reserved_at_1[0x7]; 3784 u8 aso_object_id[0x18]; 3785 3786 union mlx5_ifc_exe_aso_ctrl exe_aso_ctrl; 3787 }; 3788 3789 struct mlx5_ifc_flow_context_bits { 3790 struct mlx5_ifc_vlan_bits push_vlan; 3791 3792 u8 group_id[0x20]; 3793 3794 u8 reserved_at_40[0x8]; 3795 u8 flow_tag[0x18]; 3796 3797 u8 reserved_at_60[0x10]; 3798 u8 action[0x10]; 3799 3800 u8 extended_destination[0x1]; 3801 u8 uplink_hairpin_en[0x1]; 3802 u8 flow_source[0x2]; 3803 u8 encrypt_decrypt_type[0x4]; 3804 u8 destination_list_size[0x18]; 3805 3806 u8 reserved_at_a0[0x8]; 3807 u8 flow_counter_list_size[0x18]; 3808 3809 u8 packet_reformat_id[0x20]; 3810 3811 u8 modify_header_id[0x20]; 3812 3813 struct mlx5_ifc_vlan_bits push_vlan_2; 3814 3815 u8 encrypt_decrypt_obj_id[0x20]; 3816 u8 reserved_at_140[0xc0]; 3817 3818 struct mlx5_ifc_fte_match_param_bits match_value; 3819 3820 struct mlx5_ifc_execute_aso_bits execute_aso[4]; 3821 3822 u8 reserved_at_1300[0x500]; 3823 3824 union mlx5_ifc_dest_format_flow_counter_list_auto_bits destination[]; 3825 }; 3826 3827 enum { 3828 MLX5_XRC_SRQC_STATE_GOOD = 0x0, 3829 MLX5_XRC_SRQC_STATE_ERROR = 0x1, 3830 }; 3831 3832 struct mlx5_ifc_xrc_srqc_bits { 3833 u8 state[0x4]; 3834 u8 log_xrc_srq_size[0x4]; 3835 u8 reserved_at_8[0x18]; 3836 3837 u8 wq_signature[0x1]; 3838 u8 cont_srq[0x1]; 3839 u8 reserved_at_22[0x1]; 3840 u8 rlky[0x1]; 3841 u8 basic_cyclic_rcv_wqe[0x1]; 3842 u8 log_rq_stride[0x3]; 3843 u8 xrcd[0x18]; 3844 3845 u8 page_offset[0x6]; 3846 u8 reserved_at_46[0x1]; 3847 u8 dbr_umem_valid[0x1]; 3848 u8 cqn[0x18]; 3849 3850 u8 reserved_at_60[0x20]; 3851 3852 u8 user_index_equal_xrc_srqn[0x1]; 3853 u8 reserved_at_81[0x1]; 3854 u8 log_page_size[0x6]; 3855 u8 user_index[0x18]; 3856 3857 u8 reserved_at_a0[0x20]; 3858 3859 u8 reserved_at_c0[0x8]; 3860 u8 pd[0x18]; 3861 3862 u8 lwm[0x10]; 3863 u8 wqe_cnt[0x10]; 3864 3865 u8 reserved_at_100[0x40]; 3866 3867 u8 db_record_addr_h[0x20]; 3868 3869 u8 db_record_addr_l[0x1e]; 3870 u8 reserved_at_17e[0x2]; 3871 3872 u8 reserved_at_180[0x80]; 3873 }; 3874 3875 struct mlx5_ifc_vnic_diagnostic_statistics_bits { 3876 u8 counter_error_queues[0x20]; 3877 3878 u8 total_error_queues[0x20]; 3879 3880 u8 send_queue_priority_update_flow[0x20]; 3881 3882 u8 reserved_at_60[0x20]; 3883 3884 u8 nic_receive_steering_discard[0x40]; 3885 3886 u8 receive_discard_vport_down[0x40]; 3887 3888 u8 transmit_discard_vport_down[0x40]; 3889 3890 u8 async_eq_overrun[0x20]; 3891 3892 u8 comp_eq_overrun[0x20]; 3893 3894 u8 reserved_at_180[0x20]; 3895 3896 u8 invalid_command[0x20]; 3897 3898 u8 quota_exceeded_command[0x20]; 3899 3900 u8 internal_rq_out_of_buffer[0x20]; 3901 3902 u8 cq_overrun[0x20]; 3903 3904 u8 eth_wqe_too_small[0x20]; 3905 3906 u8 reserved_at_220[0xc0]; 3907 3908 u8 generated_pkt_steering_fail[0x40]; 3909 3910 u8 handled_pkt_steering_fail[0x40]; 3911 3912 u8 reserved_at_360[0xc80]; 3913 }; 3914 3915 struct mlx5_ifc_traffic_counter_bits { 3916 u8 packets[0x40]; 3917 3918 u8 octets[0x40]; 3919 }; 3920 3921 struct mlx5_ifc_tisc_bits { 3922 u8 strict_lag_tx_port_affinity[0x1]; 3923 u8 tls_en[0x1]; 3924 u8 reserved_at_2[0x2]; 3925 u8 lag_tx_port_affinity[0x04]; 3926 3927 u8 reserved_at_8[0x4]; 3928 u8 prio[0x4]; 3929 u8 reserved_at_10[0x10]; 3930 3931 u8 reserved_at_20[0x100]; 3932 3933 u8 reserved_at_120[0x8]; 3934 u8 transport_domain[0x18]; 3935 3936 u8 reserved_at_140[0x8]; 3937 u8 underlay_qpn[0x18]; 3938 3939 u8 reserved_at_160[0x8]; 3940 u8 pd[0x18]; 3941 3942 u8 reserved_at_180[0x380]; 3943 }; 3944 3945 enum { 3946 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0, 3947 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1, 3948 }; 3949 3950 enum { 3951 MLX5_TIRC_PACKET_MERGE_MASK_IPV4_LRO = BIT(0), 3952 MLX5_TIRC_PACKET_MERGE_MASK_IPV6_LRO = BIT(1), 3953 }; 3954 3955 enum { 3956 MLX5_RX_HASH_FN_NONE = 0x0, 3957 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1, 3958 MLX5_RX_HASH_FN_TOEPLITZ = 0x2, 3959 }; 3960 3961 enum { 3962 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST = 0x1, 3963 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST = 0x2, 3964 }; 3965 3966 struct mlx5_ifc_tirc_bits { 3967 u8 reserved_at_0[0x20]; 3968 3969 u8 disp_type[0x4]; 3970 u8 tls_en[0x1]; 3971 u8 reserved_at_25[0x1b]; 3972 3973 u8 reserved_at_40[0x40]; 3974 3975 u8 reserved_at_80[0x4]; 3976 u8 lro_timeout_period_usecs[0x10]; 3977 u8 packet_merge_mask[0x4]; 3978 u8 lro_max_ip_payload_size[0x8]; 3979 3980 u8 reserved_at_a0[0x40]; 3981 3982 u8 reserved_at_e0[0x8]; 3983 u8 inline_rqn[0x18]; 3984 3985 u8 rx_hash_symmetric[0x1]; 3986 u8 reserved_at_101[0x1]; 3987 u8 tunneled_offload_en[0x1]; 3988 u8 reserved_at_103[0x5]; 3989 u8 indirect_table[0x18]; 3990 3991 u8 rx_hash_fn[0x4]; 3992 u8 reserved_at_124[0x2]; 3993 u8 self_lb_block[0x2]; 3994 u8 transport_domain[0x18]; 3995 3996 u8 rx_hash_toeplitz_key[10][0x20]; 3997 3998 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer; 3999 4000 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner; 4001 4002 u8 reserved_at_2c0[0x4c0]; 4003 }; 4004 4005 enum { 4006 MLX5_SRQC_STATE_GOOD = 0x0, 4007 MLX5_SRQC_STATE_ERROR = 0x1, 4008 }; 4009 4010 struct mlx5_ifc_srqc_bits { 4011 u8 state[0x4]; 4012 u8 log_srq_size[0x4]; 4013 u8 reserved_at_8[0x18]; 4014 4015 u8 wq_signature[0x1]; 4016 u8 cont_srq[0x1]; 4017 u8 reserved_at_22[0x1]; 4018 u8 rlky[0x1]; 4019 u8 reserved_at_24[0x1]; 4020 u8 log_rq_stride[0x3]; 4021 u8 xrcd[0x18]; 4022 4023 u8 page_offset[0x6]; 4024 u8 reserved_at_46[0x2]; 4025 u8 cqn[0x18]; 4026 4027 u8 reserved_at_60[0x20]; 4028 4029 u8 reserved_at_80[0x2]; 4030 u8 log_page_size[0x6]; 4031 u8 reserved_at_88[0x18]; 4032 4033 u8 reserved_at_a0[0x20]; 4034 4035 u8 reserved_at_c0[0x8]; 4036 u8 pd[0x18]; 4037 4038 u8 lwm[0x10]; 4039 u8 wqe_cnt[0x10]; 4040 4041 u8 reserved_at_100[0x40]; 4042 4043 u8 dbr_addr[0x40]; 4044 4045 u8 reserved_at_180[0x80]; 4046 }; 4047 4048 enum { 4049 MLX5_SQC_STATE_RST = 0x0, 4050 MLX5_SQC_STATE_RDY = 0x1, 4051 MLX5_SQC_STATE_ERR = 0x3, 4052 }; 4053 4054 struct mlx5_ifc_sqc_bits { 4055 u8 rlky[0x1]; 4056 u8 cd_master[0x1]; 4057 u8 fre[0x1]; 4058 u8 flush_in_error_en[0x1]; 4059 u8 allow_multi_pkt_send_wqe[0x1]; 4060 u8 min_wqe_inline_mode[0x3]; 4061 u8 state[0x4]; 4062 u8 reg_umr[0x1]; 4063 u8 allow_swp[0x1]; 4064 u8 hairpin[0x1]; 4065 u8 non_wire[0x1]; 4066 u8 reserved_at_10[0xa]; 4067 u8 ts_format[0x2]; 4068 u8 reserved_at_1c[0x4]; 4069 4070 u8 reserved_at_20[0x8]; 4071 u8 user_index[0x18]; 4072 4073 u8 reserved_at_40[0x8]; 4074 u8 cqn[0x18]; 4075 4076 u8 reserved_at_60[0x8]; 4077 u8 hairpin_peer_rq[0x18]; 4078 4079 u8 reserved_at_80[0x10]; 4080 u8 hairpin_peer_vhca[0x10]; 4081 4082 u8 reserved_at_a0[0x20]; 4083 4084 u8 reserved_at_c0[0x8]; 4085 u8 ts_cqe_to_dest_cqn[0x18]; 4086 4087 u8 reserved_at_e0[0x10]; 4088 u8 packet_pacing_rate_limit_index[0x10]; 4089 u8 tis_lst_sz[0x10]; 4090 u8 qos_queue_group_id[0x10]; 4091 4092 u8 reserved_at_120[0x40]; 4093 4094 u8 reserved_at_160[0x8]; 4095 u8 tis_num_0[0x18]; 4096 4097 struct mlx5_ifc_wq_bits wq; 4098 }; 4099 4100 enum { 4101 SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0, 4102 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1, 4103 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2, 4104 SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3, 4105 SCHEDULING_CONTEXT_ELEMENT_TYPE_QUEUE_GROUP = 0x4, 4106 }; 4107 4108 enum { 4109 ELEMENT_TYPE_CAP_MASK_TSAR = 1 << 0, 4110 ELEMENT_TYPE_CAP_MASK_VPORT = 1 << 1, 4111 ELEMENT_TYPE_CAP_MASK_VPORT_TC = 1 << 2, 4112 ELEMENT_TYPE_CAP_MASK_PARA_VPORT_TC = 1 << 3, 4113 ELEMENT_TYPE_CAP_MASK_QUEUE_GROUP = 1 << 4, 4114 }; 4115 4116 enum { 4117 TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0, 4118 TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1, 4119 TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2, 4120 }; 4121 4122 enum { 4123 TSAR_TYPE_CAP_MASK_DWRR = 1 << 0, 4124 TSAR_TYPE_CAP_MASK_ROUND_ROBIN = 1 << 1, 4125 TSAR_TYPE_CAP_MASK_ETS = 1 << 2, 4126 }; 4127 4128 struct mlx5_ifc_tsar_element_bits { 4129 u8 reserved_at_0[0x8]; 4130 u8 tsar_type[0x8]; 4131 u8 reserved_at_10[0x10]; 4132 }; 4133 4134 struct mlx5_ifc_vport_element_bits { 4135 u8 reserved_at_0[0x10]; 4136 u8 vport_number[0x10]; 4137 }; 4138 4139 struct mlx5_ifc_vport_tc_element_bits { 4140 u8 traffic_class[0x4]; 4141 u8 reserved_at_4[0xc]; 4142 u8 vport_number[0x10]; 4143 }; 4144 4145 union mlx5_ifc_element_attributes_bits { 4146 struct mlx5_ifc_tsar_element_bits tsar; 4147 struct mlx5_ifc_vport_element_bits vport; 4148 struct mlx5_ifc_vport_tc_element_bits vport_tc; 4149 u8 reserved_at_0[0x20]; 4150 }; 4151 4152 struct mlx5_ifc_scheduling_context_bits { 4153 u8 element_type[0x8]; 4154 u8 reserved_at_8[0x18]; 4155 4156 union mlx5_ifc_element_attributes_bits element_attributes; 4157 4158 u8 parent_element_id[0x20]; 4159 4160 u8 reserved_at_60[0x40]; 4161 4162 u8 bw_share[0x20]; 4163 4164 u8 max_average_bw[0x20]; 4165 4166 u8 reserved_at_e0[0x120]; 4167 }; 4168 4169 struct mlx5_ifc_rqtc_bits { 4170 u8 reserved_at_0[0xa0]; 4171 4172 u8 reserved_at_a0[0x5]; 4173 u8 list_q_type[0x3]; 4174 u8 reserved_at_a8[0x8]; 4175 u8 rqt_max_size[0x10]; 4176 4177 u8 rq_vhca_id_format[0x1]; 4178 u8 reserved_at_c1[0xf]; 4179 u8 rqt_actual_size[0x10]; 4180 4181 u8 reserved_at_e0[0x6a0]; 4182 4183 union { 4184 DECLARE_FLEX_ARRAY(struct mlx5_ifc_rq_num_bits, rq_num); 4185 DECLARE_FLEX_ARRAY(struct mlx5_ifc_rq_vhca_bits, rq_vhca); 4186 }; 4187 }; 4188 4189 enum { 4190 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0, 4191 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1, 4192 }; 4193 4194 enum { 4195 MLX5_RQC_STATE_RST = 0x0, 4196 MLX5_RQC_STATE_RDY = 0x1, 4197 MLX5_RQC_STATE_ERR = 0x3, 4198 }; 4199 4200 enum { 4201 MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_BYTE = 0x0, 4202 MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_STRIDE = 0x1, 4203 MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_PAGE = 0x2, 4204 }; 4205 4206 enum { 4207 MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_NO_MATCH = 0x0, 4208 MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_EXTENDED = 0x1, 4209 MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_FIVE_TUPLE = 0x2, 4210 }; 4211 4212 struct mlx5_ifc_rqc_bits { 4213 u8 rlky[0x1]; 4214 u8 delay_drop_en[0x1]; 4215 u8 scatter_fcs[0x1]; 4216 u8 vsd[0x1]; 4217 u8 mem_rq_type[0x4]; 4218 u8 state[0x4]; 4219 u8 reserved_at_c[0x1]; 4220 u8 flush_in_error_en[0x1]; 4221 u8 hairpin[0x1]; 4222 u8 reserved_at_f[0xb]; 4223 u8 ts_format[0x2]; 4224 u8 reserved_at_1c[0x4]; 4225 4226 u8 reserved_at_20[0x8]; 4227 u8 user_index[0x18]; 4228 4229 u8 reserved_at_40[0x8]; 4230 u8 cqn[0x18]; 4231 4232 u8 counter_set_id[0x8]; 4233 u8 reserved_at_68[0x18]; 4234 4235 u8 reserved_at_80[0x8]; 4236 u8 rmpn[0x18]; 4237 4238 u8 reserved_at_a0[0x8]; 4239 u8 hairpin_peer_sq[0x18]; 4240 4241 u8 reserved_at_c0[0x10]; 4242 u8 hairpin_peer_vhca[0x10]; 4243 4244 u8 reserved_at_e0[0x46]; 4245 u8 shampo_no_match_alignment_granularity[0x2]; 4246 u8 reserved_at_128[0x6]; 4247 u8 shampo_match_criteria_type[0x2]; 4248 u8 reservation_timeout[0x10]; 4249 4250 u8 reserved_at_140[0x40]; 4251 4252 struct mlx5_ifc_wq_bits wq; 4253 }; 4254 4255 enum { 4256 MLX5_RMPC_STATE_RDY = 0x1, 4257 MLX5_RMPC_STATE_ERR = 0x3, 4258 }; 4259 4260 struct mlx5_ifc_rmpc_bits { 4261 u8 reserved_at_0[0x8]; 4262 u8 state[0x4]; 4263 u8 reserved_at_c[0x14]; 4264 4265 u8 basic_cyclic_rcv_wqe[0x1]; 4266 u8 reserved_at_21[0x1f]; 4267 4268 u8 reserved_at_40[0x140]; 4269 4270 struct mlx5_ifc_wq_bits wq; 4271 }; 4272 4273 enum { 4274 VHCA_ID_TYPE_HW = 0, 4275 VHCA_ID_TYPE_SW = 1, 4276 }; 4277 4278 struct mlx5_ifc_nic_vport_context_bits { 4279 u8 reserved_at_0[0x5]; 4280 u8 min_wqe_inline_mode[0x3]; 4281 u8 reserved_at_8[0x15]; 4282 u8 disable_mc_local_lb[0x1]; 4283 u8 disable_uc_local_lb[0x1]; 4284 u8 roce_en[0x1]; 4285 4286 u8 arm_change_event[0x1]; 4287 u8 reserved_at_21[0x1a]; 4288 u8 event_on_mtu[0x1]; 4289 u8 event_on_promisc_change[0x1]; 4290 u8 event_on_vlan_change[0x1]; 4291 u8 event_on_mc_address_change[0x1]; 4292 u8 event_on_uc_address_change[0x1]; 4293 4294 u8 vhca_id_type[0x1]; 4295 u8 reserved_at_41[0xb]; 4296 u8 affiliation_criteria[0x4]; 4297 u8 affiliated_vhca_id[0x10]; 4298 4299 u8 reserved_at_60[0xa0]; 4300 4301 u8 reserved_at_100[0x1]; 4302 u8 sd_group[0x3]; 4303 u8 reserved_at_104[0x1c]; 4304 4305 u8 reserved_at_120[0x10]; 4306 u8 mtu[0x10]; 4307 4308 u8 system_image_guid[0x40]; 4309 u8 port_guid[0x40]; 4310 u8 node_guid[0x40]; 4311 4312 u8 reserved_at_200[0x140]; 4313 u8 qkey_violation_counter[0x10]; 4314 u8 reserved_at_350[0x430]; 4315 4316 u8 promisc_uc[0x1]; 4317 u8 promisc_mc[0x1]; 4318 u8 promisc_all[0x1]; 4319 u8 reserved_at_783[0x2]; 4320 u8 allowed_list_type[0x3]; 4321 u8 reserved_at_788[0xc]; 4322 u8 allowed_list_size[0xc]; 4323 4324 struct mlx5_ifc_mac_address_layout_bits permanent_address; 4325 4326 u8 reserved_at_7e0[0x20]; 4327 4328 u8 current_uc_mac_address[][0x40]; 4329 }; 4330 4331 enum { 4332 MLX5_MKC_ACCESS_MODE_PA = 0x0, 4333 MLX5_MKC_ACCESS_MODE_MTT = 0x1, 4334 MLX5_MKC_ACCESS_MODE_KLMS = 0x2, 4335 MLX5_MKC_ACCESS_MODE_KSM = 0x3, 4336 MLX5_MKC_ACCESS_MODE_SW_ICM = 0x4, 4337 MLX5_MKC_ACCESS_MODE_MEMIC = 0x5, 4338 MLX5_MKC_ACCESS_MODE_CROSSING = 0x6, 4339 }; 4340 4341 struct mlx5_ifc_mkc_bits { 4342 u8 reserved_at_0[0x1]; 4343 u8 free[0x1]; 4344 u8 reserved_at_2[0x1]; 4345 u8 access_mode_4_2[0x3]; 4346 u8 reserved_at_6[0x7]; 4347 u8 relaxed_ordering_write[0x1]; 4348 u8 reserved_at_e[0x1]; 4349 u8 small_fence_on_rdma_read_response[0x1]; 4350 u8 umr_en[0x1]; 4351 u8 a[0x1]; 4352 u8 rw[0x1]; 4353 u8 rr[0x1]; 4354 u8 lw[0x1]; 4355 u8 lr[0x1]; 4356 u8 access_mode_1_0[0x2]; 4357 u8 reserved_at_18[0x2]; 4358 u8 ma_translation_mode[0x2]; 4359 u8 reserved_at_1c[0x4]; 4360 4361 u8 qpn[0x18]; 4362 u8 mkey_7_0[0x8]; 4363 4364 u8 reserved_at_40[0x20]; 4365 4366 u8 length64[0x1]; 4367 u8 bsf_en[0x1]; 4368 u8 sync_umr[0x1]; 4369 u8 reserved_at_63[0x2]; 4370 u8 expected_sigerr_count[0x1]; 4371 u8 reserved_at_66[0x1]; 4372 u8 en_rinval[0x1]; 4373 u8 pd[0x18]; 4374 4375 u8 start_addr[0x40]; 4376 4377 u8 len[0x40]; 4378 4379 u8 bsf_octword_size[0x20]; 4380 4381 u8 reserved_at_120[0x60]; 4382 4383 u8 crossing_target_vhca_id[0x10]; 4384 u8 reserved_at_190[0x10]; 4385 4386 u8 translations_octword_size[0x20]; 4387 4388 u8 reserved_at_1c0[0x19]; 4389 u8 relaxed_ordering_read[0x1]; 4390 u8 log_page_size[0x6]; 4391 4392 u8 reserved_at_1e0[0x20]; 4393 }; 4394 4395 struct mlx5_ifc_pkey_bits { 4396 u8 reserved_at_0[0x10]; 4397 u8 pkey[0x10]; 4398 }; 4399 4400 struct mlx5_ifc_array128_auto_bits { 4401 u8 array128_auto[16][0x8]; 4402 }; 4403 4404 struct mlx5_ifc_hca_vport_context_bits { 4405 u8 field_select[0x20]; 4406 4407 u8 reserved_at_20[0xe0]; 4408 4409 u8 sm_virt_aware[0x1]; 4410 u8 has_smi[0x1]; 4411 u8 has_raw[0x1]; 4412 u8 grh_required[0x1]; 4413 u8 reserved_at_104[0x4]; 4414 u8 num_port_plane[0x8]; 4415 u8 port_physical_state[0x4]; 4416 u8 vport_state_policy[0x4]; 4417 u8 port_state[0x4]; 4418 u8 vport_state[0x4]; 4419 4420 u8 reserved_at_120[0x20]; 4421 4422 u8 system_image_guid[0x40]; 4423 4424 u8 port_guid[0x40]; 4425 4426 u8 node_guid[0x40]; 4427 4428 u8 cap_mask1[0x20]; 4429 4430 u8 cap_mask1_field_select[0x20]; 4431 4432 u8 cap_mask2[0x20]; 4433 4434 u8 cap_mask2_field_select[0x20]; 4435 4436 u8 reserved_at_280[0x80]; 4437 4438 u8 lid[0x10]; 4439 u8 reserved_at_310[0x4]; 4440 u8 init_type_reply[0x4]; 4441 u8 lmc[0x3]; 4442 u8 subnet_timeout[0x5]; 4443 4444 u8 sm_lid[0x10]; 4445 u8 sm_sl[0x4]; 4446 u8 reserved_at_334[0xc]; 4447 4448 u8 qkey_violation_counter[0x10]; 4449 u8 pkey_violation_counter[0x10]; 4450 4451 u8 reserved_at_360[0xca0]; 4452 }; 4453 4454 struct mlx5_ifc_esw_vport_context_bits { 4455 u8 fdb_to_vport_reg_c[0x1]; 4456 u8 reserved_at_1[0x2]; 4457 u8 vport_svlan_strip[0x1]; 4458 u8 vport_cvlan_strip[0x1]; 4459 u8 vport_svlan_insert[0x1]; 4460 u8 vport_cvlan_insert[0x2]; 4461 u8 fdb_to_vport_reg_c_id[0x8]; 4462 u8 reserved_at_10[0x10]; 4463 4464 u8 reserved_at_20[0x20]; 4465 4466 u8 svlan_cfi[0x1]; 4467 u8 svlan_pcp[0x3]; 4468 u8 svlan_id[0xc]; 4469 u8 cvlan_cfi[0x1]; 4470 u8 cvlan_pcp[0x3]; 4471 u8 cvlan_id[0xc]; 4472 4473 u8 reserved_at_60[0x720]; 4474 4475 u8 sw_steering_vport_icm_address_rx[0x40]; 4476 4477 u8 sw_steering_vport_icm_address_tx[0x40]; 4478 }; 4479 4480 enum { 4481 MLX5_EQC_STATUS_OK = 0x0, 4482 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa, 4483 }; 4484 4485 enum { 4486 MLX5_EQC_ST_ARMED = 0x9, 4487 MLX5_EQC_ST_FIRED = 0xa, 4488 }; 4489 4490 struct mlx5_ifc_eqc_bits { 4491 u8 status[0x4]; 4492 u8 reserved_at_4[0x9]; 4493 u8 ec[0x1]; 4494 u8 oi[0x1]; 4495 u8 reserved_at_f[0x5]; 4496 u8 st[0x4]; 4497 u8 reserved_at_18[0x8]; 4498 4499 u8 reserved_at_20[0x20]; 4500 4501 u8 reserved_at_40[0x14]; 4502 u8 page_offset[0x6]; 4503 u8 reserved_at_5a[0x6]; 4504 4505 u8 reserved_at_60[0x3]; 4506 u8 log_eq_size[0x5]; 4507 u8 uar_page[0x18]; 4508 4509 u8 reserved_at_80[0x20]; 4510 4511 u8 reserved_at_a0[0x14]; 4512 u8 intr[0xc]; 4513 4514 u8 reserved_at_c0[0x3]; 4515 u8 log_page_size[0x5]; 4516 u8 reserved_at_c8[0x18]; 4517 4518 u8 reserved_at_e0[0x60]; 4519 4520 u8 reserved_at_140[0x8]; 4521 u8 consumer_counter[0x18]; 4522 4523 u8 reserved_at_160[0x8]; 4524 u8 producer_counter[0x18]; 4525 4526 u8 reserved_at_180[0x80]; 4527 }; 4528 4529 enum { 4530 MLX5_DCTC_STATE_ACTIVE = 0x0, 4531 MLX5_DCTC_STATE_DRAINING = 0x1, 4532 MLX5_DCTC_STATE_DRAINED = 0x2, 4533 }; 4534 4535 enum { 4536 MLX5_DCTC_CS_RES_DISABLE = 0x0, 4537 MLX5_DCTC_CS_RES_NA = 0x1, 4538 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2, 4539 }; 4540 4541 enum { 4542 MLX5_DCTC_MTU_256_BYTES = 0x1, 4543 MLX5_DCTC_MTU_512_BYTES = 0x2, 4544 MLX5_DCTC_MTU_1K_BYTES = 0x3, 4545 MLX5_DCTC_MTU_2K_BYTES = 0x4, 4546 MLX5_DCTC_MTU_4K_BYTES = 0x5, 4547 }; 4548 4549 struct mlx5_ifc_dctc_bits { 4550 u8 reserved_at_0[0x4]; 4551 u8 state[0x4]; 4552 u8 reserved_at_8[0x18]; 4553 4554 u8 reserved_at_20[0x7]; 4555 u8 dp_ordering_force[0x1]; 4556 u8 user_index[0x18]; 4557 4558 u8 reserved_at_40[0x8]; 4559 u8 cqn[0x18]; 4560 4561 u8 counter_set_id[0x8]; 4562 u8 atomic_mode[0x4]; 4563 u8 rre[0x1]; 4564 u8 rwe[0x1]; 4565 u8 rae[0x1]; 4566 u8 atomic_like_write_en[0x1]; 4567 u8 latency_sensitive[0x1]; 4568 u8 rlky[0x1]; 4569 u8 free_ar[0x1]; 4570 u8 reserved_at_73[0x1]; 4571 u8 dp_ordering_1[0x1]; 4572 u8 reserved_at_75[0xb]; 4573 4574 u8 reserved_at_80[0x8]; 4575 u8 cs_res[0x8]; 4576 u8 reserved_at_90[0x3]; 4577 u8 min_rnr_nak[0x5]; 4578 u8 reserved_at_98[0x8]; 4579 4580 u8 reserved_at_a0[0x8]; 4581 u8 srqn_xrqn[0x18]; 4582 4583 u8 reserved_at_c0[0x8]; 4584 u8 pd[0x18]; 4585 4586 u8 tclass[0x8]; 4587 u8 reserved_at_e8[0x4]; 4588 u8 flow_label[0x14]; 4589 4590 u8 dc_access_key[0x40]; 4591 4592 u8 reserved_at_140[0x5]; 4593 u8 mtu[0x3]; 4594 u8 port[0x8]; 4595 u8 pkey_index[0x10]; 4596 4597 u8 reserved_at_160[0x8]; 4598 u8 my_addr_index[0x8]; 4599 u8 reserved_at_170[0x8]; 4600 u8 hop_limit[0x8]; 4601 4602 u8 dc_access_key_violation_count[0x20]; 4603 4604 u8 reserved_at_1a0[0x14]; 4605 u8 dei_cfi[0x1]; 4606 u8 eth_prio[0x3]; 4607 u8 ecn[0x2]; 4608 u8 dscp[0x6]; 4609 4610 u8 reserved_at_1c0[0x20]; 4611 u8 ece[0x20]; 4612 }; 4613 4614 enum { 4615 MLX5_CQC_STATUS_OK = 0x0, 4616 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9, 4617 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa, 4618 }; 4619 4620 enum { 4621 MLX5_CQC_CQE_SZ_64_BYTES = 0x0, 4622 MLX5_CQC_CQE_SZ_128_BYTES = 0x1, 4623 }; 4624 4625 enum { 4626 MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED = 0x6, 4627 MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED = 0x9, 4628 MLX5_CQC_ST_FIRED = 0xa, 4629 }; 4630 4631 enum mlx5_cq_period_mode { 4632 MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0, 4633 MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1, 4634 MLX5_CQ_PERIOD_NUM_MODES, 4635 }; 4636 4637 struct mlx5_ifc_cqc_bits { 4638 u8 status[0x4]; 4639 u8 reserved_at_4[0x2]; 4640 u8 dbr_umem_valid[0x1]; 4641 u8 apu_cq[0x1]; 4642 u8 cqe_sz[0x3]; 4643 u8 cc[0x1]; 4644 u8 reserved_at_c[0x1]; 4645 u8 scqe_break_moderation_en[0x1]; 4646 u8 oi[0x1]; 4647 u8 cq_period_mode[0x2]; 4648 u8 cqe_comp_en[0x1]; 4649 u8 mini_cqe_res_format[0x2]; 4650 u8 st[0x4]; 4651 u8 reserved_at_18[0x6]; 4652 u8 cqe_compression_layout[0x2]; 4653 4654 u8 reserved_at_20[0x20]; 4655 4656 u8 reserved_at_40[0x14]; 4657 u8 page_offset[0x6]; 4658 u8 reserved_at_5a[0x6]; 4659 4660 u8 reserved_at_60[0x3]; 4661 u8 log_cq_size[0x5]; 4662 u8 uar_page[0x18]; 4663 4664 u8 reserved_at_80[0x4]; 4665 u8 cq_period[0xc]; 4666 u8 cq_max_count[0x10]; 4667 4668 u8 c_eqn_or_apu_element[0x20]; 4669 4670 u8 reserved_at_c0[0x3]; 4671 u8 log_page_size[0x5]; 4672 u8 reserved_at_c8[0x18]; 4673 4674 u8 reserved_at_e0[0x20]; 4675 4676 u8 reserved_at_100[0x8]; 4677 u8 last_notified_index[0x18]; 4678 4679 u8 reserved_at_120[0x8]; 4680 u8 last_solicit_index[0x18]; 4681 4682 u8 reserved_at_140[0x8]; 4683 u8 consumer_counter[0x18]; 4684 4685 u8 reserved_at_160[0x8]; 4686 u8 producer_counter[0x18]; 4687 4688 u8 reserved_at_180[0x40]; 4689 4690 u8 dbr_addr[0x40]; 4691 }; 4692 4693 union mlx5_ifc_cong_control_roce_ecn_auto_bits { 4694 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp; 4695 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp; 4696 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np; 4697 struct mlx5_ifc_cong_control_r_roce_general_bits cong_control_r_roce_general; 4698 u8 reserved_at_0[0x800]; 4699 }; 4700 4701 struct mlx5_ifc_query_adapter_param_block_bits { 4702 u8 reserved_at_0[0xc0]; 4703 4704 u8 reserved_at_c0[0x8]; 4705 u8 ieee_vendor_id[0x18]; 4706 4707 u8 reserved_at_e0[0x10]; 4708 u8 vsd_vendor_id[0x10]; 4709 4710 u8 vsd[208][0x8]; 4711 4712 u8 vsd_contd_psid[16][0x8]; 4713 }; 4714 4715 enum { 4716 MLX5_XRQC_STATE_GOOD = 0x0, 4717 MLX5_XRQC_STATE_ERROR = 0x1, 4718 }; 4719 4720 enum { 4721 MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0, 4722 MLX5_XRQC_TOPOLOGY_TAG_MATCHING = 0x1, 4723 }; 4724 4725 enum { 4726 MLX5_XRQC_OFFLOAD_RNDV = 0x1, 4727 }; 4728 4729 struct mlx5_ifc_tag_matching_topology_context_bits { 4730 u8 log_matching_list_sz[0x4]; 4731 u8 reserved_at_4[0xc]; 4732 u8 append_next_index[0x10]; 4733 4734 u8 sw_phase_cnt[0x10]; 4735 u8 hw_phase_cnt[0x10]; 4736 4737 u8 reserved_at_40[0x40]; 4738 }; 4739 4740 struct mlx5_ifc_xrqc_bits { 4741 u8 state[0x4]; 4742 u8 rlkey[0x1]; 4743 u8 reserved_at_5[0xf]; 4744 u8 topology[0x4]; 4745 u8 reserved_at_18[0x4]; 4746 u8 offload[0x4]; 4747 4748 u8 reserved_at_20[0x8]; 4749 u8 user_index[0x18]; 4750 4751 u8 reserved_at_40[0x8]; 4752 u8 cqn[0x18]; 4753 4754 u8 reserved_at_60[0xa0]; 4755 4756 struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context; 4757 4758 u8 reserved_at_180[0x280]; 4759 4760 struct mlx5_ifc_wq_bits wq; 4761 }; 4762 4763 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits { 4764 struct mlx5_ifc_modify_field_select_bits modify_field_select; 4765 struct mlx5_ifc_resize_field_select_bits resize_field_select; 4766 u8 reserved_at_0[0x20]; 4767 }; 4768 4769 union mlx5_ifc_field_select_802_1_r_roce_auto_bits { 4770 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp; 4771 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp; 4772 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np; 4773 u8 reserved_at_0[0x20]; 4774 }; 4775 4776 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits { 4777 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 4778 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 4779 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 4780 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 4781 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 4782 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 4783 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout; 4784 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout; 4785 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 4786 struct mlx5_ifc_ib_ext_port_cntrs_grp_data_layout_bits ib_ext_port_cntrs_grp_data_layout; 4787 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 4788 struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs; 4789 u8 reserved_at_0[0x7c0]; 4790 }; 4791 4792 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits { 4793 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout; 4794 u8 reserved_at_0[0x7c0]; 4795 }; 4796 4797 union mlx5_ifc_event_auto_bits { 4798 struct mlx5_ifc_comp_event_bits comp_event; 4799 struct mlx5_ifc_dct_events_bits dct_events; 4800 struct mlx5_ifc_qp_events_bits qp_events; 4801 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event; 4802 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event; 4803 struct mlx5_ifc_cq_error_bits cq_error; 4804 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged; 4805 struct mlx5_ifc_port_state_change_event_bits port_state_change_event; 4806 struct mlx5_ifc_gpio_event_bits gpio_event; 4807 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event; 4808 struct mlx5_ifc_stall_vl_event_bits stall_vl_event; 4809 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event; 4810 u8 reserved_at_0[0xe0]; 4811 }; 4812 4813 struct mlx5_ifc_health_buffer_bits { 4814 u8 reserved_at_0[0x100]; 4815 4816 u8 assert_existptr[0x20]; 4817 4818 u8 assert_callra[0x20]; 4819 4820 u8 reserved_at_140[0x20]; 4821 4822 u8 time[0x20]; 4823 4824 u8 fw_version[0x20]; 4825 4826 u8 hw_id[0x20]; 4827 4828 u8 rfr[0x1]; 4829 u8 reserved_at_1c1[0x3]; 4830 u8 valid[0x1]; 4831 u8 severity[0x3]; 4832 u8 reserved_at_1c8[0x18]; 4833 4834 u8 irisc_index[0x8]; 4835 u8 synd[0x8]; 4836 u8 ext_synd[0x10]; 4837 }; 4838 4839 struct mlx5_ifc_register_loopback_control_bits { 4840 u8 no_lb[0x1]; 4841 u8 reserved_at_1[0x7]; 4842 u8 port[0x8]; 4843 u8 reserved_at_10[0x10]; 4844 4845 u8 reserved_at_20[0x60]; 4846 }; 4847 4848 enum { 4849 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0, 4850 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1, 4851 }; 4852 4853 struct mlx5_ifc_teardown_hca_out_bits { 4854 u8 status[0x8]; 4855 u8 reserved_at_8[0x18]; 4856 4857 u8 syndrome[0x20]; 4858 4859 u8 reserved_at_40[0x3f]; 4860 4861 u8 state[0x1]; 4862 }; 4863 4864 enum { 4865 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0, 4866 MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE = 0x1, 4867 MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN = 0x2, 4868 }; 4869 4870 struct mlx5_ifc_teardown_hca_in_bits { 4871 u8 opcode[0x10]; 4872 u8 reserved_at_10[0x10]; 4873 4874 u8 reserved_at_20[0x10]; 4875 u8 op_mod[0x10]; 4876 4877 u8 reserved_at_40[0x10]; 4878 u8 profile[0x10]; 4879 4880 u8 reserved_at_60[0x20]; 4881 }; 4882 4883 struct mlx5_ifc_sqerr2rts_qp_out_bits { 4884 u8 status[0x8]; 4885 u8 reserved_at_8[0x18]; 4886 4887 u8 syndrome[0x20]; 4888 4889 u8 reserved_at_40[0x40]; 4890 }; 4891 4892 struct mlx5_ifc_sqerr2rts_qp_in_bits { 4893 u8 opcode[0x10]; 4894 u8 uid[0x10]; 4895 4896 u8 reserved_at_20[0x10]; 4897 u8 op_mod[0x10]; 4898 4899 u8 reserved_at_40[0x8]; 4900 u8 qpn[0x18]; 4901 4902 u8 reserved_at_60[0x20]; 4903 4904 u8 opt_param_mask[0x20]; 4905 4906 u8 reserved_at_a0[0x20]; 4907 4908 struct mlx5_ifc_qpc_bits qpc; 4909 4910 u8 reserved_at_800[0x80]; 4911 }; 4912 4913 struct mlx5_ifc_sqd2rts_qp_out_bits { 4914 u8 status[0x8]; 4915 u8 reserved_at_8[0x18]; 4916 4917 u8 syndrome[0x20]; 4918 4919 u8 reserved_at_40[0x40]; 4920 }; 4921 4922 struct mlx5_ifc_sqd2rts_qp_in_bits { 4923 u8 opcode[0x10]; 4924 u8 uid[0x10]; 4925 4926 u8 reserved_at_20[0x10]; 4927 u8 op_mod[0x10]; 4928 4929 u8 reserved_at_40[0x8]; 4930 u8 qpn[0x18]; 4931 4932 u8 reserved_at_60[0x20]; 4933 4934 u8 opt_param_mask[0x20]; 4935 4936 u8 reserved_at_a0[0x20]; 4937 4938 struct mlx5_ifc_qpc_bits qpc; 4939 4940 u8 reserved_at_800[0x80]; 4941 }; 4942 4943 struct mlx5_ifc_set_roce_address_out_bits { 4944 u8 status[0x8]; 4945 u8 reserved_at_8[0x18]; 4946 4947 u8 syndrome[0x20]; 4948 4949 u8 reserved_at_40[0x40]; 4950 }; 4951 4952 struct mlx5_ifc_set_roce_address_in_bits { 4953 u8 opcode[0x10]; 4954 u8 reserved_at_10[0x10]; 4955 4956 u8 reserved_at_20[0x10]; 4957 u8 op_mod[0x10]; 4958 4959 u8 roce_address_index[0x10]; 4960 u8 reserved_at_50[0xc]; 4961 u8 vhca_port_num[0x4]; 4962 4963 u8 reserved_at_60[0x20]; 4964 4965 struct mlx5_ifc_roce_addr_layout_bits roce_address; 4966 }; 4967 4968 struct mlx5_ifc_set_mad_demux_out_bits { 4969 u8 status[0x8]; 4970 u8 reserved_at_8[0x18]; 4971 4972 u8 syndrome[0x20]; 4973 4974 u8 reserved_at_40[0x40]; 4975 }; 4976 4977 enum { 4978 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0, 4979 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2, 4980 }; 4981 4982 struct mlx5_ifc_set_mad_demux_in_bits { 4983 u8 opcode[0x10]; 4984 u8 reserved_at_10[0x10]; 4985 4986 u8 reserved_at_20[0x10]; 4987 u8 op_mod[0x10]; 4988 4989 u8 reserved_at_40[0x20]; 4990 4991 u8 reserved_at_60[0x6]; 4992 u8 demux_mode[0x2]; 4993 u8 reserved_at_68[0x18]; 4994 }; 4995 4996 struct mlx5_ifc_set_l2_table_entry_out_bits { 4997 u8 status[0x8]; 4998 u8 reserved_at_8[0x18]; 4999 5000 u8 syndrome[0x20]; 5001 5002 u8 reserved_at_40[0x40]; 5003 }; 5004 5005 struct mlx5_ifc_set_l2_table_entry_in_bits { 5006 u8 opcode[0x10]; 5007 u8 reserved_at_10[0x10]; 5008 5009 u8 reserved_at_20[0x10]; 5010 u8 op_mod[0x10]; 5011 5012 u8 reserved_at_40[0x60]; 5013 5014 u8 reserved_at_a0[0x8]; 5015 u8 table_index[0x18]; 5016 5017 u8 reserved_at_c0[0x20]; 5018 5019 u8 reserved_at_e0[0x10]; 5020 u8 silent_mode_valid[0x1]; 5021 u8 silent_mode[0x1]; 5022 u8 reserved_at_f2[0x1]; 5023 u8 vlan_valid[0x1]; 5024 u8 vlan[0xc]; 5025 5026 struct mlx5_ifc_mac_address_layout_bits mac_address; 5027 5028 u8 reserved_at_140[0xc0]; 5029 }; 5030 5031 struct mlx5_ifc_set_issi_out_bits { 5032 u8 status[0x8]; 5033 u8 reserved_at_8[0x18]; 5034 5035 u8 syndrome[0x20]; 5036 5037 u8 reserved_at_40[0x40]; 5038 }; 5039 5040 struct mlx5_ifc_set_issi_in_bits { 5041 u8 opcode[0x10]; 5042 u8 reserved_at_10[0x10]; 5043 5044 u8 reserved_at_20[0x10]; 5045 u8 op_mod[0x10]; 5046 5047 u8 reserved_at_40[0x10]; 5048 u8 current_issi[0x10]; 5049 5050 u8 reserved_at_60[0x20]; 5051 }; 5052 5053 struct mlx5_ifc_set_hca_cap_out_bits { 5054 u8 status[0x8]; 5055 u8 reserved_at_8[0x18]; 5056 5057 u8 syndrome[0x20]; 5058 5059 u8 reserved_at_40[0x40]; 5060 }; 5061 5062 struct mlx5_ifc_set_hca_cap_in_bits { 5063 u8 opcode[0x10]; 5064 u8 reserved_at_10[0x10]; 5065 5066 u8 reserved_at_20[0x10]; 5067 u8 op_mod[0x10]; 5068 5069 u8 other_function[0x1]; 5070 u8 ec_vf_function[0x1]; 5071 u8 reserved_at_42[0xe]; 5072 u8 function_id[0x10]; 5073 5074 u8 reserved_at_60[0x20]; 5075 5076 union mlx5_ifc_hca_cap_union_bits capability; 5077 }; 5078 5079 enum { 5080 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0, 5081 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1, 5082 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2, 5083 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3, 5084 MLX5_SET_FTE_MODIFY_ENABLE_MASK_IPSEC_OBJ_ID = 0x4 5085 }; 5086 5087 struct mlx5_ifc_set_fte_out_bits { 5088 u8 status[0x8]; 5089 u8 reserved_at_8[0x18]; 5090 5091 u8 syndrome[0x20]; 5092 5093 u8 reserved_at_40[0x40]; 5094 }; 5095 5096 struct mlx5_ifc_set_fte_in_bits { 5097 u8 opcode[0x10]; 5098 u8 reserved_at_10[0x10]; 5099 5100 u8 reserved_at_20[0x10]; 5101 u8 op_mod[0x10]; 5102 5103 u8 other_vport[0x1]; 5104 u8 reserved_at_41[0xf]; 5105 u8 vport_number[0x10]; 5106 5107 u8 reserved_at_60[0x20]; 5108 5109 u8 table_type[0x8]; 5110 u8 reserved_at_88[0x18]; 5111 5112 u8 reserved_at_a0[0x8]; 5113 u8 table_id[0x18]; 5114 5115 u8 ignore_flow_level[0x1]; 5116 u8 reserved_at_c1[0x17]; 5117 u8 modify_enable_mask[0x8]; 5118 5119 u8 reserved_at_e0[0x20]; 5120 5121 u8 flow_index[0x20]; 5122 5123 u8 reserved_at_120[0xe0]; 5124 5125 struct mlx5_ifc_flow_context_bits flow_context; 5126 }; 5127 5128 struct mlx5_ifc_dest_format_bits { 5129 u8 destination_type[0x8]; 5130 u8 destination_id[0x18]; 5131 5132 u8 destination_eswitch_owner_vhca_id_valid[0x1]; 5133 u8 packet_reformat[0x1]; 5134 u8 reserved_at_22[0xe]; 5135 u8 destination_eswitch_owner_vhca_id[0x10]; 5136 }; 5137 5138 struct mlx5_ifc_rts2rts_qp_out_bits { 5139 u8 status[0x8]; 5140 u8 reserved_at_8[0x18]; 5141 5142 u8 syndrome[0x20]; 5143 5144 u8 reserved_at_40[0x20]; 5145 u8 ece[0x20]; 5146 }; 5147 5148 struct mlx5_ifc_rts2rts_qp_in_bits { 5149 u8 opcode[0x10]; 5150 u8 uid[0x10]; 5151 5152 u8 reserved_at_20[0x10]; 5153 u8 op_mod[0x10]; 5154 5155 u8 reserved_at_40[0x8]; 5156 u8 qpn[0x18]; 5157 5158 u8 reserved_at_60[0x20]; 5159 5160 u8 opt_param_mask[0x20]; 5161 5162 u8 ece[0x20]; 5163 5164 struct mlx5_ifc_qpc_bits qpc; 5165 5166 u8 reserved_at_800[0x80]; 5167 }; 5168 5169 struct mlx5_ifc_rtr2rts_qp_out_bits { 5170 u8 status[0x8]; 5171 u8 reserved_at_8[0x18]; 5172 5173 u8 syndrome[0x20]; 5174 5175 u8 reserved_at_40[0x20]; 5176 u8 ece[0x20]; 5177 }; 5178 5179 struct mlx5_ifc_rtr2rts_qp_in_bits { 5180 u8 opcode[0x10]; 5181 u8 uid[0x10]; 5182 5183 u8 reserved_at_20[0x10]; 5184 u8 op_mod[0x10]; 5185 5186 u8 reserved_at_40[0x8]; 5187 u8 qpn[0x18]; 5188 5189 u8 reserved_at_60[0x20]; 5190 5191 u8 opt_param_mask[0x20]; 5192 5193 u8 ece[0x20]; 5194 5195 struct mlx5_ifc_qpc_bits qpc; 5196 5197 u8 reserved_at_800[0x80]; 5198 }; 5199 5200 struct mlx5_ifc_rst2init_qp_out_bits { 5201 u8 status[0x8]; 5202 u8 reserved_at_8[0x18]; 5203 5204 u8 syndrome[0x20]; 5205 5206 u8 reserved_at_40[0x20]; 5207 u8 ece[0x20]; 5208 }; 5209 5210 struct mlx5_ifc_rst2init_qp_in_bits { 5211 u8 opcode[0x10]; 5212 u8 uid[0x10]; 5213 5214 u8 reserved_at_20[0x10]; 5215 u8 op_mod[0x10]; 5216 5217 u8 reserved_at_40[0x8]; 5218 u8 qpn[0x18]; 5219 5220 u8 reserved_at_60[0x20]; 5221 5222 u8 opt_param_mask[0x20]; 5223 5224 u8 ece[0x20]; 5225 5226 struct mlx5_ifc_qpc_bits qpc; 5227 5228 u8 reserved_at_800[0x80]; 5229 }; 5230 5231 struct mlx5_ifc_query_xrq_out_bits { 5232 u8 status[0x8]; 5233 u8 reserved_at_8[0x18]; 5234 5235 u8 syndrome[0x20]; 5236 5237 u8 reserved_at_40[0x40]; 5238 5239 struct mlx5_ifc_xrqc_bits xrq_context; 5240 }; 5241 5242 struct mlx5_ifc_query_xrq_in_bits { 5243 u8 opcode[0x10]; 5244 u8 reserved_at_10[0x10]; 5245 5246 u8 reserved_at_20[0x10]; 5247 u8 op_mod[0x10]; 5248 5249 u8 reserved_at_40[0x8]; 5250 u8 xrqn[0x18]; 5251 5252 u8 reserved_at_60[0x20]; 5253 }; 5254 5255 struct mlx5_ifc_query_xrc_srq_out_bits { 5256 u8 status[0x8]; 5257 u8 reserved_at_8[0x18]; 5258 5259 u8 syndrome[0x20]; 5260 5261 u8 reserved_at_40[0x40]; 5262 5263 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 5264 5265 u8 reserved_at_280[0x600]; 5266 5267 u8 pas[][0x40]; 5268 }; 5269 5270 struct mlx5_ifc_query_xrc_srq_in_bits { 5271 u8 opcode[0x10]; 5272 u8 reserved_at_10[0x10]; 5273 5274 u8 reserved_at_20[0x10]; 5275 u8 op_mod[0x10]; 5276 5277 u8 reserved_at_40[0x8]; 5278 u8 xrc_srqn[0x18]; 5279 5280 u8 reserved_at_60[0x20]; 5281 }; 5282 5283 enum { 5284 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0, 5285 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1, 5286 }; 5287 5288 struct mlx5_ifc_query_vport_state_out_bits { 5289 u8 status[0x8]; 5290 u8 reserved_at_8[0x18]; 5291 5292 u8 syndrome[0x20]; 5293 5294 u8 reserved_at_40[0x20]; 5295 5296 u8 reserved_at_60[0x18]; 5297 u8 admin_state[0x4]; 5298 u8 state[0x4]; 5299 }; 5300 5301 struct mlx5_ifc_array1024_auto_bits { 5302 u8 array1024_auto[32][0x20]; 5303 }; 5304 5305 struct mlx5_ifc_query_vuid_in_bits { 5306 u8 opcode[0x10]; 5307 u8 uid[0x10]; 5308 5309 u8 reserved_at_20[0x40]; 5310 5311 u8 query_vfs_vuid[0x1]; 5312 u8 data_direct[0x1]; 5313 u8 reserved_at_62[0xe]; 5314 u8 vhca_id[0x10]; 5315 }; 5316 5317 struct mlx5_ifc_query_vuid_out_bits { 5318 u8 status[0x8]; 5319 u8 reserved_at_8[0x18]; 5320 5321 u8 syndrome[0x20]; 5322 5323 u8 reserved_at_40[0x1a0]; 5324 5325 u8 reserved_at_1e0[0x10]; 5326 u8 num_of_entries[0x10]; 5327 5328 struct mlx5_ifc_array1024_auto_bits vuid[]; 5329 }; 5330 5331 enum { 5332 MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT = 0x0, 5333 MLX5_VPORT_STATE_OP_MOD_ESW_VPORT = 0x1, 5334 MLX5_VPORT_STATE_OP_MOD_UPLINK = 0x2, 5335 }; 5336 5337 struct mlx5_ifc_arm_monitor_counter_in_bits { 5338 u8 opcode[0x10]; 5339 u8 uid[0x10]; 5340 5341 u8 reserved_at_20[0x10]; 5342 u8 op_mod[0x10]; 5343 5344 u8 reserved_at_40[0x20]; 5345 5346 u8 reserved_at_60[0x20]; 5347 }; 5348 5349 struct mlx5_ifc_arm_monitor_counter_out_bits { 5350 u8 status[0x8]; 5351 u8 reserved_at_8[0x18]; 5352 5353 u8 syndrome[0x20]; 5354 5355 u8 reserved_at_40[0x40]; 5356 }; 5357 5358 enum { 5359 MLX5_QUERY_MONITOR_CNT_TYPE_PPCNT = 0x0, 5360 MLX5_QUERY_MONITOR_CNT_TYPE_Q_COUNTER = 0x1, 5361 }; 5362 5363 enum mlx5_monitor_counter_ppcnt { 5364 MLX5_QUERY_MONITOR_PPCNT_IN_RANGE_LENGTH_ERRORS = 0x0, 5365 MLX5_QUERY_MONITOR_PPCNT_OUT_OF_RANGE_LENGTH_FIELD = 0x1, 5366 MLX5_QUERY_MONITOR_PPCNT_FRAME_TOO_LONG_ERRORS = 0x2, 5367 MLX5_QUERY_MONITOR_PPCNT_FRAME_CHECK_SEQUENCE_ERRORS = 0x3, 5368 MLX5_QUERY_MONITOR_PPCNT_ALIGNMENT_ERRORS = 0x4, 5369 MLX5_QUERY_MONITOR_PPCNT_IF_OUT_DISCARDS = 0x5, 5370 }; 5371 5372 enum { 5373 MLX5_QUERY_MONITOR_Q_COUNTER_RX_OUT_OF_BUFFER = 0x4, 5374 }; 5375 5376 struct mlx5_ifc_monitor_counter_output_bits { 5377 u8 reserved_at_0[0x4]; 5378 u8 type[0x4]; 5379 u8 reserved_at_8[0x8]; 5380 u8 counter[0x10]; 5381 5382 u8 counter_group_id[0x20]; 5383 }; 5384 5385 #define MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 (6) 5386 #define MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1 (1) 5387 #define MLX5_CMD_SET_MONITOR_NUM_COUNTER (MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 +\ 5388 MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1) 5389 5390 struct mlx5_ifc_set_monitor_counter_in_bits { 5391 u8 opcode[0x10]; 5392 u8 uid[0x10]; 5393 5394 u8 reserved_at_20[0x10]; 5395 u8 op_mod[0x10]; 5396 5397 u8 reserved_at_40[0x10]; 5398 u8 num_of_counters[0x10]; 5399 5400 u8 reserved_at_60[0x20]; 5401 5402 struct mlx5_ifc_monitor_counter_output_bits monitor_counter[MLX5_CMD_SET_MONITOR_NUM_COUNTER]; 5403 }; 5404 5405 struct mlx5_ifc_set_monitor_counter_out_bits { 5406 u8 status[0x8]; 5407 u8 reserved_at_8[0x18]; 5408 5409 u8 syndrome[0x20]; 5410 5411 u8 reserved_at_40[0x40]; 5412 }; 5413 5414 struct mlx5_ifc_query_vport_state_in_bits { 5415 u8 opcode[0x10]; 5416 u8 reserved_at_10[0x10]; 5417 5418 u8 reserved_at_20[0x10]; 5419 u8 op_mod[0x10]; 5420 5421 u8 other_vport[0x1]; 5422 u8 reserved_at_41[0xf]; 5423 u8 vport_number[0x10]; 5424 5425 u8 reserved_at_60[0x20]; 5426 }; 5427 5428 struct mlx5_ifc_query_vnic_env_out_bits { 5429 u8 status[0x8]; 5430 u8 reserved_at_8[0x18]; 5431 5432 u8 syndrome[0x20]; 5433 5434 u8 reserved_at_40[0x40]; 5435 5436 struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env; 5437 }; 5438 5439 enum { 5440 MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS = 0x0, 5441 }; 5442 5443 struct mlx5_ifc_query_vnic_env_in_bits { 5444 u8 opcode[0x10]; 5445 u8 reserved_at_10[0x10]; 5446 5447 u8 reserved_at_20[0x10]; 5448 u8 op_mod[0x10]; 5449 5450 u8 other_vport[0x1]; 5451 u8 reserved_at_41[0xf]; 5452 u8 vport_number[0x10]; 5453 5454 u8 reserved_at_60[0x20]; 5455 }; 5456 5457 struct mlx5_ifc_query_vport_counter_out_bits { 5458 u8 status[0x8]; 5459 u8 reserved_at_8[0x18]; 5460 5461 u8 syndrome[0x20]; 5462 5463 u8 reserved_at_40[0x40]; 5464 5465 struct mlx5_ifc_traffic_counter_bits received_errors; 5466 5467 struct mlx5_ifc_traffic_counter_bits transmit_errors; 5468 5469 struct mlx5_ifc_traffic_counter_bits received_ib_unicast; 5470 5471 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast; 5472 5473 struct mlx5_ifc_traffic_counter_bits received_ib_multicast; 5474 5475 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast; 5476 5477 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast; 5478 5479 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast; 5480 5481 struct mlx5_ifc_traffic_counter_bits received_eth_unicast; 5482 5483 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast; 5484 5485 struct mlx5_ifc_traffic_counter_bits received_eth_multicast; 5486 5487 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast; 5488 5489 struct mlx5_ifc_traffic_counter_bits local_loopback; 5490 5491 u8 reserved_at_700[0x980]; 5492 }; 5493 5494 enum { 5495 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0, 5496 }; 5497 5498 struct mlx5_ifc_query_vport_counter_in_bits { 5499 u8 opcode[0x10]; 5500 u8 reserved_at_10[0x10]; 5501 5502 u8 reserved_at_20[0x10]; 5503 u8 op_mod[0x10]; 5504 5505 u8 other_vport[0x1]; 5506 u8 reserved_at_41[0xb]; 5507 u8 port_num[0x4]; 5508 u8 vport_number[0x10]; 5509 5510 u8 reserved_at_60[0x60]; 5511 5512 u8 clear[0x1]; 5513 u8 reserved_at_c1[0x1f]; 5514 5515 u8 reserved_at_e0[0x20]; 5516 }; 5517 5518 struct mlx5_ifc_query_tis_out_bits { 5519 u8 status[0x8]; 5520 u8 reserved_at_8[0x18]; 5521 5522 u8 syndrome[0x20]; 5523 5524 u8 reserved_at_40[0x40]; 5525 5526 struct mlx5_ifc_tisc_bits tis_context; 5527 }; 5528 5529 struct mlx5_ifc_query_tis_in_bits { 5530 u8 opcode[0x10]; 5531 u8 reserved_at_10[0x10]; 5532 5533 u8 reserved_at_20[0x10]; 5534 u8 op_mod[0x10]; 5535 5536 u8 reserved_at_40[0x8]; 5537 u8 tisn[0x18]; 5538 5539 u8 reserved_at_60[0x20]; 5540 }; 5541 5542 struct mlx5_ifc_query_tir_out_bits { 5543 u8 status[0x8]; 5544 u8 reserved_at_8[0x18]; 5545 5546 u8 syndrome[0x20]; 5547 5548 u8 reserved_at_40[0xc0]; 5549 5550 struct mlx5_ifc_tirc_bits tir_context; 5551 }; 5552 5553 struct mlx5_ifc_query_tir_in_bits { 5554 u8 opcode[0x10]; 5555 u8 reserved_at_10[0x10]; 5556 5557 u8 reserved_at_20[0x10]; 5558 u8 op_mod[0x10]; 5559 5560 u8 reserved_at_40[0x8]; 5561 u8 tirn[0x18]; 5562 5563 u8 reserved_at_60[0x20]; 5564 }; 5565 5566 struct mlx5_ifc_query_srq_out_bits { 5567 u8 status[0x8]; 5568 u8 reserved_at_8[0x18]; 5569 5570 u8 syndrome[0x20]; 5571 5572 u8 reserved_at_40[0x40]; 5573 5574 struct mlx5_ifc_srqc_bits srq_context_entry; 5575 5576 u8 reserved_at_280[0x600]; 5577 5578 u8 pas[][0x40]; 5579 }; 5580 5581 struct mlx5_ifc_query_srq_in_bits { 5582 u8 opcode[0x10]; 5583 u8 reserved_at_10[0x10]; 5584 5585 u8 reserved_at_20[0x10]; 5586 u8 op_mod[0x10]; 5587 5588 u8 reserved_at_40[0x8]; 5589 u8 srqn[0x18]; 5590 5591 u8 reserved_at_60[0x20]; 5592 }; 5593 5594 struct mlx5_ifc_query_sq_out_bits { 5595 u8 status[0x8]; 5596 u8 reserved_at_8[0x18]; 5597 5598 u8 syndrome[0x20]; 5599 5600 u8 reserved_at_40[0xc0]; 5601 5602 struct mlx5_ifc_sqc_bits sq_context; 5603 }; 5604 5605 struct mlx5_ifc_query_sq_in_bits { 5606 u8 opcode[0x10]; 5607 u8 reserved_at_10[0x10]; 5608 5609 u8 reserved_at_20[0x10]; 5610 u8 op_mod[0x10]; 5611 5612 u8 reserved_at_40[0x8]; 5613 u8 sqn[0x18]; 5614 5615 u8 reserved_at_60[0x20]; 5616 }; 5617 5618 struct mlx5_ifc_query_special_contexts_out_bits { 5619 u8 status[0x8]; 5620 u8 reserved_at_8[0x18]; 5621 5622 u8 syndrome[0x20]; 5623 5624 u8 dump_fill_mkey[0x20]; 5625 5626 u8 resd_lkey[0x20]; 5627 5628 u8 null_mkey[0x20]; 5629 5630 u8 terminate_scatter_list_mkey[0x20]; 5631 5632 u8 repeated_mkey[0x20]; 5633 5634 u8 reserved_at_a0[0x20]; 5635 }; 5636 5637 struct mlx5_ifc_query_special_contexts_in_bits { 5638 u8 opcode[0x10]; 5639 u8 reserved_at_10[0x10]; 5640 5641 u8 reserved_at_20[0x10]; 5642 u8 op_mod[0x10]; 5643 5644 u8 reserved_at_40[0x40]; 5645 }; 5646 5647 struct mlx5_ifc_query_scheduling_element_out_bits { 5648 u8 opcode[0x10]; 5649 u8 reserved_at_10[0x10]; 5650 5651 u8 reserved_at_20[0x10]; 5652 u8 op_mod[0x10]; 5653 5654 u8 reserved_at_40[0xc0]; 5655 5656 struct mlx5_ifc_scheduling_context_bits scheduling_context; 5657 5658 u8 reserved_at_300[0x100]; 5659 }; 5660 5661 enum { 5662 SCHEDULING_HIERARCHY_E_SWITCH = 0x2, 5663 SCHEDULING_HIERARCHY_NIC = 0x3, 5664 }; 5665 5666 struct mlx5_ifc_query_scheduling_element_in_bits { 5667 u8 opcode[0x10]; 5668 u8 reserved_at_10[0x10]; 5669 5670 u8 reserved_at_20[0x10]; 5671 u8 op_mod[0x10]; 5672 5673 u8 scheduling_hierarchy[0x8]; 5674 u8 reserved_at_48[0x18]; 5675 5676 u8 scheduling_element_id[0x20]; 5677 5678 u8 reserved_at_80[0x180]; 5679 }; 5680 5681 struct mlx5_ifc_query_rqt_out_bits { 5682 u8 status[0x8]; 5683 u8 reserved_at_8[0x18]; 5684 5685 u8 syndrome[0x20]; 5686 5687 u8 reserved_at_40[0xc0]; 5688 5689 struct mlx5_ifc_rqtc_bits rqt_context; 5690 }; 5691 5692 struct mlx5_ifc_query_rqt_in_bits { 5693 u8 opcode[0x10]; 5694 u8 reserved_at_10[0x10]; 5695 5696 u8 reserved_at_20[0x10]; 5697 u8 op_mod[0x10]; 5698 5699 u8 reserved_at_40[0x8]; 5700 u8 rqtn[0x18]; 5701 5702 u8 reserved_at_60[0x20]; 5703 }; 5704 5705 struct mlx5_ifc_query_rq_out_bits { 5706 u8 status[0x8]; 5707 u8 reserved_at_8[0x18]; 5708 5709 u8 syndrome[0x20]; 5710 5711 u8 reserved_at_40[0xc0]; 5712 5713 struct mlx5_ifc_rqc_bits rq_context; 5714 }; 5715 5716 struct mlx5_ifc_query_rq_in_bits { 5717 u8 opcode[0x10]; 5718 u8 reserved_at_10[0x10]; 5719 5720 u8 reserved_at_20[0x10]; 5721 u8 op_mod[0x10]; 5722 5723 u8 reserved_at_40[0x8]; 5724 u8 rqn[0x18]; 5725 5726 u8 reserved_at_60[0x20]; 5727 }; 5728 5729 struct mlx5_ifc_query_roce_address_out_bits { 5730 u8 status[0x8]; 5731 u8 reserved_at_8[0x18]; 5732 5733 u8 syndrome[0x20]; 5734 5735 u8 reserved_at_40[0x40]; 5736 5737 struct mlx5_ifc_roce_addr_layout_bits roce_address; 5738 }; 5739 5740 struct mlx5_ifc_query_roce_address_in_bits { 5741 u8 opcode[0x10]; 5742 u8 reserved_at_10[0x10]; 5743 5744 u8 reserved_at_20[0x10]; 5745 u8 op_mod[0x10]; 5746 5747 u8 roce_address_index[0x10]; 5748 u8 reserved_at_50[0xc]; 5749 u8 vhca_port_num[0x4]; 5750 5751 u8 reserved_at_60[0x20]; 5752 }; 5753 5754 struct mlx5_ifc_query_rmp_out_bits { 5755 u8 status[0x8]; 5756 u8 reserved_at_8[0x18]; 5757 5758 u8 syndrome[0x20]; 5759 5760 u8 reserved_at_40[0xc0]; 5761 5762 struct mlx5_ifc_rmpc_bits rmp_context; 5763 }; 5764 5765 struct mlx5_ifc_query_rmp_in_bits { 5766 u8 opcode[0x10]; 5767 u8 reserved_at_10[0x10]; 5768 5769 u8 reserved_at_20[0x10]; 5770 u8 op_mod[0x10]; 5771 5772 u8 reserved_at_40[0x8]; 5773 u8 rmpn[0x18]; 5774 5775 u8 reserved_at_60[0x20]; 5776 }; 5777 5778 struct mlx5_ifc_cqe_error_syndrome_bits { 5779 u8 hw_error_syndrome[0x8]; 5780 u8 hw_syndrome_type[0x4]; 5781 u8 reserved_at_c[0x4]; 5782 u8 vendor_error_syndrome[0x8]; 5783 u8 syndrome[0x8]; 5784 }; 5785 5786 struct mlx5_ifc_qp_context_extension_bits { 5787 u8 reserved_at_0[0x60]; 5788 5789 struct mlx5_ifc_cqe_error_syndrome_bits error_syndrome; 5790 5791 u8 reserved_at_80[0x580]; 5792 }; 5793 5794 struct mlx5_ifc_qpc_extension_and_pas_list_in_bits { 5795 struct mlx5_ifc_qp_context_extension_bits qpc_data_extension; 5796 5797 u8 pas[0][0x40]; 5798 }; 5799 5800 struct mlx5_ifc_qp_pas_list_in_bits { 5801 struct mlx5_ifc_cmd_pas_bits pas[0]; 5802 }; 5803 5804 union mlx5_ifc_qp_pas_or_qpc_ext_and_pas_bits { 5805 struct mlx5_ifc_qp_pas_list_in_bits qp_pas_list; 5806 struct mlx5_ifc_qpc_extension_and_pas_list_in_bits qpc_ext_and_pas_list; 5807 }; 5808 5809 struct mlx5_ifc_query_qp_out_bits { 5810 u8 status[0x8]; 5811 u8 reserved_at_8[0x18]; 5812 5813 u8 syndrome[0x20]; 5814 5815 u8 reserved_at_40[0x40]; 5816 5817 u8 opt_param_mask[0x20]; 5818 5819 u8 ece[0x20]; 5820 5821 struct mlx5_ifc_qpc_bits qpc; 5822 5823 u8 reserved_at_800[0x80]; 5824 5825 union mlx5_ifc_qp_pas_or_qpc_ext_and_pas_bits qp_pas_or_qpc_ext_and_pas; 5826 }; 5827 5828 struct mlx5_ifc_query_qp_in_bits { 5829 u8 opcode[0x10]; 5830 u8 reserved_at_10[0x10]; 5831 5832 u8 reserved_at_20[0x10]; 5833 u8 op_mod[0x10]; 5834 5835 u8 qpc_ext[0x1]; 5836 u8 reserved_at_41[0x7]; 5837 u8 qpn[0x18]; 5838 5839 u8 reserved_at_60[0x20]; 5840 }; 5841 5842 struct mlx5_ifc_query_q_counter_out_bits { 5843 u8 status[0x8]; 5844 u8 reserved_at_8[0x18]; 5845 5846 u8 syndrome[0x20]; 5847 5848 u8 reserved_at_40[0x40]; 5849 5850 u8 rx_write_requests[0x20]; 5851 5852 u8 reserved_at_a0[0x20]; 5853 5854 u8 rx_read_requests[0x20]; 5855 5856 u8 reserved_at_e0[0x20]; 5857 5858 u8 rx_atomic_requests[0x20]; 5859 5860 u8 reserved_at_120[0x20]; 5861 5862 u8 rx_dct_connect[0x20]; 5863 5864 u8 reserved_at_160[0x20]; 5865 5866 u8 out_of_buffer[0x20]; 5867 5868 u8 reserved_at_1a0[0x20]; 5869 5870 u8 out_of_sequence[0x20]; 5871 5872 u8 reserved_at_1e0[0x20]; 5873 5874 u8 duplicate_request[0x20]; 5875 5876 u8 reserved_at_220[0x20]; 5877 5878 u8 rnr_nak_retry_err[0x20]; 5879 5880 u8 reserved_at_260[0x20]; 5881 5882 u8 packet_seq_err[0x20]; 5883 5884 u8 reserved_at_2a0[0x20]; 5885 5886 u8 implied_nak_seq_err[0x20]; 5887 5888 u8 reserved_at_2e0[0x20]; 5889 5890 u8 local_ack_timeout_err[0x20]; 5891 5892 u8 reserved_at_320[0x60]; 5893 5894 u8 req_rnr_retries_exceeded[0x20]; 5895 5896 u8 reserved_at_3a0[0x20]; 5897 5898 u8 resp_local_length_error[0x20]; 5899 5900 u8 req_local_length_error[0x20]; 5901 5902 u8 resp_local_qp_error[0x20]; 5903 5904 u8 local_operation_error[0x20]; 5905 5906 u8 resp_local_protection[0x20]; 5907 5908 u8 req_local_protection[0x20]; 5909 5910 u8 resp_cqe_error[0x20]; 5911 5912 u8 req_cqe_error[0x20]; 5913 5914 u8 req_mw_binding[0x20]; 5915 5916 u8 req_bad_response[0x20]; 5917 5918 u8 req_remote_invalid_request[0x20]; 5919 5920 u8 resp_remote_invalid_request[0x20]; 5921 5922 u8 req_remote_access_errors[0x20]; 5923 5924 u8 resp_remote_access_errors[0x20]; 5925 5926 u8 req_remote_operation_errors[0x20]; 5927 5928 u8 req_transport_retries_exceeded[0x20]; 5929 5930 u8 cq_overflow[0x20]; 5931 5932 u8 resp_cqe_flush_error[0x20]; 5933 5934 u8 req_cqe_flush_error[0x20]; 5935 5936 u8 reserved_at_620[0x20]; 5937 5938 u8 roce_adp_retrans[0x20]; 5939 5940 u8 roce_adp_retrans_to[0x20]; 5941 5942 u8 roce_slow_restart[0x20]; 5943 5944 u8 roce_slow_restart_cnps[0x20]; 5945 5946 u8 roce_slow_restart_trans[0x20]; 5947 5948 u8 reserved_at_6e0[0x120]; 5949 }; 5950 5951 struct mlx5_ifc_query_q_counter_in_bits { 5952 u8 opcode[0x10]; 5953 u8 reserved_at_10[0x10]; 5954 5955 u8 reserved_at_20[0x10]; 5956 u8 op_mod[0x10]; 5957 5958 u8 other_vport[0x1]; 5959 u8 reserved_at_41[0xf]; 5960 u8 vport_number[0x10]; 5961 5962 u8 reserved_at_60[0x60]; 5963 5964 u8 clear[0x1]; 5965 u8 aggregate[0x1]; 5966 u8 reserved_at_c2[0x1e]; 5967 5968 u8 reserved_at_e0[0x18]; 5969 u8 counter_set_id[0x8]; 5970 }; 5971 5972 struct mlx5_ifc_query_pages_out_bits { 5973 u8 status[0x8]; 5974 u8 reserved_at_8[0x18]; 5975 5976 u8 syndrome[0x20]; 5977 5978 u8 embedded_cpu_function[0x1]; 5979 u8 reserved_at_41[0xf]; 5980 u8 function_id[0x10]; 5981 5982 u8 num_pages[0x20]; 5983 }; 5984 5985 enum { 5986 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1, 5987 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2, 5988 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3, 5989 }; 5990 5991 struct mlx5_ifc_query_pages_in_bits { 5992 u8 opcode[0x10]; 5993 u8 reserved_at_10[0x10]; 5994 5995 u8 reserved_at_20[0x10]; 5996 u8 op_mod[0x10]; 5997 5998 u8 embedded_cpu_function[0x1]; 5999 u8 reserved_at_41[0xf]; 6000 u8 function_id[0x10]; 6001 6002 u8 reserved_at_60[0x20]; 6003 }; 6004 6005 struct mlx5_ifc_query_nic_vport_context_out_bits { 6006 u8 status[0x8]; 6007 u8 reserved_at_8[0x18]; 6008 6009 u8 syndrome[0x20]; 6010 6011 u8 reserved_at_40[0x40]; 6012 6013 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 6014 }; 6015 6016 struct mlx5_ifc_query_nic_vport_context_in_bits { 6017 u8 opcode[0x10]; 6018 u8 reserved_at_10[0x10]; 6019 6020 u8 reserved_at_20[0x10]; 6021 u8 op_mod[0x10]; 6022 6023 u8 other_vport[0x1]; 6024 u8 reserved_at_41[0xf]; 6025 u8 vport_number[0x10]; 6026 6027 u8 reserved_at_60[0x5]; 6028 u8 allowed_list_type[0x3]; 6029 u8 reserved_at_68[0x18]; 6030 }; 6031 6032 struct mlx5_ifc_query_mkey_out_bits { 6033 u8 status[0x8]; 6034 u8 reserved_at_8[0x18]; 6035 6036 u8 syndrome[0x20]; 6037 6038 u8 reserved_at_40[0x40]; 6039 6040 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 6041 6042 u8 reserved_at_280[0x600]; 6043 6044 u8 bsf0_klm0_pas_mtt0_1[16][0x8]; 6045 6046 u8 bsf1_klm1_pas_mtt2_3[16][0x8]; 6047 }; 6048 6049 struct mlx5_ifc_query_mkey_in_bits { 6050 u8 opcode[0x10]; 6051 u8 reserved_at_10[0x10]; 6052 6053 u8 reserved_at_20[0x10]; 6054 u8 op_mod[0x10]; 6055 6056 u8 reserved_at_40[0x8]; 6057 u8 mkey_index[0x18]; 6058 6059 u8 pg_access[0x1]; 6060 u8 reserved_at_61[0x1f]; 6061 }; 6062 6063 struct mlx5_ifc_query_mad_demux_out_bits { 6064 u8 status[0x8]; 6065 u8 reserved_at_8[0x18]; 6066 6067 u8 syndrome[0x20]; 6068 6069 u8 reserved_at_40[0x40]; 6070 6071 u8 mad_dumux_parameters_block[0x20]; 6072 }; 6073 6074 struct mlx5_ifc_query_mad_demux_in_bits { 6075 u8 opcode[0x10]; 6076 u8 reserved_at_10[0x10]; 6077 6078 u8 reserved_at_20[0x10]; 6079 u8 op_mod[0x10]; 6080 6081 u8 reserved_at_40[0x40]; 6082 }; 6083 6084 struct mlx5_ifc_query_l2_table_entry_out_bits { 6085 u8 status[0x8]; 6086 u8 reserved_at_8[0x18]; 6087 6088 u8 syndrome[0x20]; 6089 6090 u8 reserved_at_40[0xa0]; 6091 6092 u8 reserved_at_e0[0x13]; 6093 u8 vlan_valid[0x1]; 6094 u8 vlan[0xc]; 6095 6096 struct mlx5_ifc_mac_address_layout_bits mac_address; 6097 6098 u8 reserved_at_140[0xc0]; 6099 }; 6100 6101 struct mlx5_ifc_query_l2_table_entry_in_bits { 6102 u8 opcode[0x10]; 6103 u8 reserved_at_10[0x10]; 6104 6105 u8 reserved_at_20[0x10]; 6106 u8 op_mod[0x10]; 6107 6108 u8 reserved_at_40[0x60]; 6109 6110 u8 reserved_at_a0[0x8]; 6111 u8 table_index[0x18]; 6112 6113 u8 reserved_at_c0[0x140]; 6114 }; 6115 6116 struct mlx5_ifc_query_issi_out_bits { 6117 u8 status[0x8]; 6118 u8 reserved_at_8[0x18]; 6119 6120 u8 syndrome[0x20]; 6121 6122 u8 reserved_at_40[0x10]; 6123 u8 current_issi[0x10]; 6124 6125 u8 reserved_at_60[0xa0]; 6126 6127 u8 reserved_at_100[76][0x8]; 6128 u8 supported_issi_dw0[0x20]; 6129 }; 6130 6131 struct mlx5_ifc_query_issi_in_bits { 6132 u8 opcode[0x10]; 6133 u8 reserved_at_10[0x10]; 6134 6135 u8 reserved_at_20[0x10]; 6136 u8 op_mod[0x10]; 6137 6138 u8 reserved_at_40[0x40]; 6139 }; 6140 6141 struct mlx5_ifc_set_driver_version_out_bits { 6142 u8 status[0x8]; 6143 u8 reserved_0[0x18]; 6144 6145 u8 syndrome[0x20]; 6146 u8 reserved_1[0x40]; 6147 }; 6148 6149 struct mlx5_ifc_set_driver_version_in_bits { 6150 u8 opcode[0x10]; 6151 u8 reserved_0[0x10]; 6152 6153 u8 reserved_1[0x10]; 6154 u8 op_mod[0x10]; 6155 6156 u8 reserved_2[0x40]; 6157 u8 driver_version[64][0x8]; 6158 }; 6159 6160 struct mlx5_ifc_query_hca_vport_pkey_out_bits { 6161 u8 status[0x8]; 6162 u8 reserved_at_8[0x18]; 6163 6164 u8 syndrome[0x20]; 6165 6166 u8 reserved_at_40[0x40]; 6167 6168 struct mlx5_ifc_pkey_bits pkey[]; 6169 }; 6170 6171 struct mlx5_ifc_query_hca_vport_pkey_in_bits { 6172 u8 opcode[0x10]; 6173 u8 reserved_at_10[0x10]; 6174 6175 u8 reserved_at_20[0x10]; 6176 u8 op_mod[0x10]; 6177 6178 u8 other_vport[0x1]; 6179 u8 reserved_at_41[0xb]; 6180 u8 port_num[0x4]; 6181 u8 vport_number[0x10]; 6182 6183 u8 reserved_at_60[0x10]; 6184 u8 pkey_index[0x10]; 6185 }; 6186 6187 enum { 6188 MLX5_HCA_VPORT_SEL_PORT_GUID = 1 << 0, 6189 MLX5_HCA_VPORT_SEL_NODE_GUID = 1 << 1, 6190 MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2, 6191 }; 6192 6193 struct mlx5_ifc_query_hca_vport_gid_out_bits { 6194 u8 status[0x8]; 6195 u8 reserved_at_8[0x18]; 6196 6197 u8 syndrome[0x20]; 6198 6199 u8 reserved_at_40[0x20]; 6200 6201 u8 gids_num[0x10]; 6202 u8 reserved_at_70[0x10]; 6203 6204 struct mlx5_ifc_array128_auto_bits gid[]; 6205 }; 6206 6207 struct mlx5_ifc_query_hca_vport_gid_in_bits { 6208 u8 opcode[0x10]; 6209 u8 reserved_at_10[0x10]; 6210 6211 u8 reserved_at_20[0x10]; 6212 u8 op_mod[0x10]; 6213 6214 u8 other_vport[0x1]; 6215 u8 reserved_at_41[0xb]; 6216 u8 port_num[0x4]; 6217 u8 vport_number[0x10]; 6218 6219 u8 reserved_at_60[0x10]; 6220 u8 gid_index[0x10]; 6221 }; 6222 6223 struct mlx5_ifc_query_hca_vport_context_out_bits { 6224 u8 status[0x8]; 6225 u8 reserved_at_8[0x18]; 6226 6227 u8 syndrome[0x20]; 6228 6229 u8 reserved_at_40[0x40]; 6230 6231 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 6232 }; 6233 6234 struct mlx5_ifc_query_hca_vport_context_in_bits { 6235 u8 opcode[0x10]; 6236 u8 reserved_at_10[0x10]; 6237 6238 u8 reserved_at_20[0x10]; 6239 u8 op_mod[0x10]; 6240 6241 u8 other_vport[0x1]; 6242 u8 reserved_at_41[0xb]; 6243 u8 port_num[0x4]; 6244 u8 vport_number[0x10]; 6245 6246 u8 reserved_at_60[0x20]; 6247 }; 6248 6249 struct mlx5_ifc_query_hca_cap_out_bits { 6250 u8 status[0x8]; 6251 u8 reserved_at_8[0x18]; 6252 6253 u8 syndrome[0x20]; 6254 6255 u8 reserved_at_40[0x40]; 6256 6257 union mlx5_ifc_hca_cap_union_bits capability; 6258 }; 6259 6260 struct mlx5_ifc_query_hca_cap_in_bits { 6261 u8 opcode[0x10]; 6262 u8 reserved_at_10[0x10]; 6263 6264 u8 reserved_at_20[0x10]; 6265 u8 op_mod[0x10]; 6266 6267 u8 other_function[0x1]; 6268 u8 ec_vf_function[0x1]; 6269 u8 reserved_at_42[0xe]; 6270 u8 function_id[0x10]; 6271 6272 u8 reserved_at_60[0x20]; 6273 }; 6274 6275 struct mlx5_ifc_other_hca_cap_bits { 6276 u8 roce[0x1]; 6277 u8 reserved_at_1[0x27f]; 6278 }; 6279 6280 struct mlx5_ifc_query_other_hca_cap_out_bits { 6281 u8 status[0x8]; 6282 u8 reserved_at_8[0x18]; 6283 6284 u8 syndrome[0x20]; 6285 6286 u8 reserved_at_40[0x40]; 6287 6288 struct mlx5_ifc_other_hca_cap_bits other_capability; 6289 }; 6290 6291 struct mlx5_ifc_query_other_hca_cap_in_bits { 6292 u8 opcode[0x10]; 6293 u8 reserved_at_10[0x10]; 6294 6295 u8 reserved_at_20[0x10]; 6296 u8 op_mod[0x10]; 6297 6298 u8 reserved_at_40[0x10]; 6299 u8 function_id[0x10]; 6300 6301 u8 reserved_at_60[0x20]; 6302 }; 6303 6304 struct mlx5_ifc_modify_other_hca_cap_out_bits { 6305 u8 status[0x8]; 6306 u8 reserved_at_8[0x18]; 6307 6308 u8 syndrome[0x20]; 6309 6310 u8 reserved_at_40[0x40]; 6311 }; 6312 6313 struct mlx5_ifc_modify_other_hca_cap_in_bits { 6314 u8 opcode[0x10]; 6315 u8 reserved_at_10[0x10]; 6316 6317 u8 reserved_at_20[0x10]; 6318 u8 op_mod[0x10]; 6319 6320 u8 reserved_at_40[0x10]; 6321 u8 function_id[0x10]; 6322 u8 field_select[0x20]; 6323 6324 struct mlx5_ifc_other_hca_cap_bits other_capability; 6325 }; 6326 6327 struct mlx5_ifc_flow_table_context_bits { 6328 u8 reformat_en[0x1]; 6329 u8 decap_en[0x1]; 6330 u8 sw_owner[0x1]; 6331 u8 termination_table[0x1]; 6332 u8 table_miss_action[0x4]; 6333 u8 level[0x8]; 6334 u8 rtc_valid[0x1]; 6335 u8 reserved_at_11[0x7]; 6336 u8 log_size[0x8]; 6337 6338 u8 reserved_at_20[0x8]; 6339 u8 table_miss_id[0x18]; 6340 6341 u8 reserved_at_40[0x8]; 6342 u8 lag_master_next_table_id[0x18]; 6343 6344 u8 reserved_at_60[0x60]; 6345 union { 6346 struct { 6347 u8 sw_owner_icm_root_1[0x40]; 6348 6349 u8 sw_owner_icm_root_0[0x40]; 6350 } sws; 6351 struct { 6352 u8 rtc_id_0[0x20]; 6353 6354 u8 rtc_id_1[0x20]; 6355 6356 u8 reserved_at_100[0x40]; 6357 6358 } hws; 6359 }; 6360 }; 6361 6362 struct mlx5_ifc_query_flow_table_out_bits { 6363 u8 status[0x8]; 6364 u8 reserved_at_8[0x18]; 6365 6366 u8 syndrome[0x20]; 6367 6368 u8 reserved_at_40[0x80]; 6369 6370 struct mlx5_ifc_flow_table_context_bits flow_table_context; 6371 }; 6372 6373 struct mlx5_ifc_query_flow_table_in_bits { 6374 u8 opcode[0x10]; 6375 u8 reserved_at_10[0x10]; 6376 6377 u8 reserved_at_20[0x10]; 6378 u8 op_mod[0x10]; 6379 6380 u8 reserved_at_40[0x40]; 6381 6382 u8 table_type[0x8]; 6383 u8 reserved_at_88[0x18]; 6384 6385 u8 reserved_at_a0[0x8]; 6386 u8 table_id[0x18]; 6387 6388 u8 reserved_at_c0[0x140]; 6389 }; 6390 6391 struct mlx5_ifc_query_fte_out_bits { 6392 u8 status[0x8]; 6393 u8 reserved_at_8[0x18]; 6394 6395 u8 syndrome[0x20]; 6396 6397 u8 reserved_at_40[0x1c0]; 6398 6399 struct mlx5_ifc_flow_context_bits flow_context; 6400 }; 6401 6402 struct mlx5_ifc_query_fte_in_bits { 6403 u8 opcode[0x10]; 6404 u8 reserved_at_10[0x10]; 6405 6406 u8 reserved_at_20[0x10]; 6407 u8 op_mod[0x10]; 6408 6409 u8 reserved_at_40[0x40]; 6410 6411 u8 table_type[0x8]; 6412 u8 reserved_at_88[0x18]; 6413 6414 u8 reserved_at_a0[0x8]; 6415 u8 table_id[0x18]; 6416 6417 u8 reserved_at_c0[0x40]; 6418 6419 u8 flow_index[0x20]; 6420 6421 u8 reserved_at_120[0xe0]; 6422 }; 6423 6424 struct mlx5_ifc_match_definer_format_0_bits { 6425 u8 reserved_at_0[0x100]; 6426 6427 u8 metadata_reg_c_0[0x20]; 6428 6429 u8 metadata_reg_c_1[0x20]; 6430 6431 u8 outer_dmac_47_16[0x20]; 6432 6433 u8 outer_dmac_15_0[0x10]; 6434 u8 outer_ethertype[0x10]; 6435 6436 u8 reserved_at_180[0x1]; 6437 u8 sx_sniffer[0x1]; 6438 u8 functional_lb[0x1]; 6439 u8 outer_ip_frag[0x1]; 6440 u8 outer_qp_type[0x2]; 6441 u8 outer_encap_type[0x2]; 6442 u8 port_number[0x2]; 6443 u8 outer_l3_type[0x2]; 6444 u8 outer_l4_type[0x2]; 6445 u8 outer_first_vlan_type[0x2]; 6446 u8 outer_first_vlan_prio[0x3]; 6447 u8 outer_first_vlan_cfi[0x1]; 6448 u8 outer_first_vlan_vid[0xc]; 6449 6450 u8 outer_l4_type_ext[0x4]; 6451 u8 reserved_at_1a4[0x2]; 6452 u8 outer_ipsec_layer[0x2]; 6453 u8 outer_l2_type[0x2]; 6454 u8 force_lb[0x1]; 6455 u8 outer_l2_ok[0x1]; 6456 u8 outer_l3_ok[0x1]; 6457 u8 outer_l4_ok[0x1]; 6458 u8 outer_second_vlan_type[0x2]; 6459 u8 outer_second_vlan_prio[0x3]; 6460 u8 outer_second_vlan_cfi[0x1]; 6461 u8 outer_second_vlan_vid[0xc]; 6462 6463 u8 outer_smac_47_16[0x20]; 6464 6465 u8 outer_smac_15_0[0x10]; 6466 u8 inner_ipv4_checksum_ok[0x1]; 6467 u8 inner_l4_checksum_ok[0x1]; 6468 u8 outer_ipv4_checksum_ok[0x1]; 6469 u8 outer_l4_checksum_ok[0x1]; 6470 u8 inner_l3_ok[0x1]; 6471 u8 inner_l4_ok[0x1]; 6472 u8 outer_l3_ok_duplicate[0x1]; 6473 u8 outer_l4_ok_duplicate[0x1]; 6474 u8 outer_tcp_cwr[0x1]; 6475 u8 outer_tcp_ece[0x1]; 6476 u8 outer_tcp_urg[0x1]; 6477 u8 outer_tcp_ack[0x1]; 6478 u8 outer_tcp_psh[0x1]; 6479 u8 outer_tcp_rst[0x1]; 6480 u8 outer_tcp_syn[0x1]; 6481 u8 outer_tcp_fin[0x1]; 6482 }; 6483 6484 struct mlx5_ifc_match_definer_format_22_bits { 6485 u8 reserved_at_0[0x100]; 6486 6487 u8 outer_ip_src_addr[0x20]; 6488 6489 u8 outer_ip_dest_addr[0x20]; 6490 6491 u8 outer_l4_sport[0x10]; 6492 u8 outer_l4_dport[0x10]; 6493 6494 u8 reserved_at_160[0x1]; 6495 u8 sx_sniffer[0x1]; 6496 u8 functional_lb[0x1]; 6497 u8 outer_ip_frag[0x1]; 6498 u8 outer_qp_type[0x2]; 6499 u8 outer_encap_type[0x2]; 6500 u8 port_number[0x2]; 6501 u8 outer_l3_type[0x2]; 6502 u8 outer_l4_type[0x2]; 6503 u8 outer_first_vlan_type[0x2]; 6504 u8 outer_first_vlan_prio[0x3]; 6505 u8 outer_first_vlan_cfi[0x1]; 6506 u8 outer_first_vlan_vid[0xc]; 6507 6508 u8 metadata_reg_c_0[0x20]; 6509 6510 u8 outer_dmac_47_16[0x20]; 6511 6512 u8 outer_smac_47_16[0x20]; 6513 6514 u8 outer_smac_15_0[0x10]; 6515 u8 outer_dmac_15_0[0x10]; 6516 }; 6517 6518 struct mlx5_ifc_match_definer_format_23_bits { 6519 u8 reserved_at_0[0x100]; 6520 6521 u8 inner_ip_src_addr[0x20]; 6522 6523 u8 inner_ip_dest_addr[0x20]; 6524 6525 u8 inner_l4_sport[0x10]; 6526 u8 inner_l4_dport[0x10]; 6527 6528 u8 reserved_at_160[0x1]; 6529 u8 sx_sniffer[0x1]; 6530 u8 functional_lb[0x1]; 6531 u8 inner_ip_frag[0x1]; 6532 u8 inner_qp_type[0x2]; 6533 u8 inner_encap_type[0x2]; 6534 u8 port_number[0x2]; 6535 u8 inner_l3_type[0x2]; 6536 u8 inner_l4_type[0x2]; 6537 u8 inner_first_vlan_type[0x2]; 6538 u8 inner_first_vlan_prio[0x3]; 6539 u8 inner_first_vlan_cfi[0x1]; 6540 u8 inner_first_vlan_vid[0xc]; 6541 6542 u8 tunnel_header_0[0x20]; 6543 6544 u8 inner_dmac_47_16[0x20]; 6545 6546 u8 inner_smac_47_16[0x20]; 6547 6548 u8 inner_smac_15_0[0x10]; 6549 u8 inner_dmac_15_0[0x10]; 6550 }; 6551 6552 struct mlx5_ifc_match_definer_format_29_bits { 6553 u8 reserved_at_0[0xc0]; 6554 6555 u8 outer_ip_dest_addr[0x80]; 6556 6557 u8 outer_ip_src_addr[0x80]; 6558 6559 u8 outer_l4_sport[0x10]; 6560 u8 outer_l4_dport[0x10]; 6561 6562 u8 reserved_at_1e0[0x20]; 6563 }; 6564 6565 struct mlx5_ifc_match_definer_format_30_bits { 6566 u8 reserved_at_0[0xa0]; 6567 6568 u8 outer_ip_dest_addr[0x80]; 6569 6570 u8 outer_ip_src_addr[0x80]; 6571 6572 u8 outer_dmac_47_16[0x20]; 6573 6574 u8 outer_smac_47_16[0x20]; 6575 6576 u8 outer_smac_15_0[0x10]; 6577 u8 outer_dmac_15_0[0x10]; 6578 }; 6579 6580 struct mlx5_ifc_match_definer_format_31_bits { 6581 u8 reserved_at_0[0xc0]; 6582 6583 u8 inner_ip_dest_addr[0x80]; 6584 6585 u8 inner_ip_src_addr[0x80]; 6586 6587 u8 inner_l4_sport[0x10]; 6588 u8 inner_l4_dport[0x10]; 6589 6590 u8 reserved_at_1e0[0x20]; 6591 }; 6592 6593 struct mlx5_ifc_match_definer_format_32_bits { 6594 u8 reserved_at_0[0xa0]; 6595 6596 u8 inner_ip_dest_addr[0x80]; 6597 6598 u8 inner_ip_src_addr[0x80]; 6599 6600 u8 inner_dmac_47_16[0x20]; 6601 6602 u8 inner_smac_47_16[0x20]; 6603 6604 u8 inner_smac_15_0[0x10]; 6605 u8 inner_dmac_15_0[0x10]; 6606 }; 6607 6608 enum { 6609 MLX5_IFC_DEFINER_FORMAT_ID_SELECT = 61, 6610 }; 6611 6612 #define MLX5_IFC_DEFINER_FORMAT_OFFSET_UNUSED 0x0 6613 #define MLX5_IFC_DEFINER_FORMAT_OFFSET_OUTER_ETH_PKT_LEN 0x48 6614 #define MLX5_IFC_DEFINER_DW_SELECTORS_NUM 9 6615 #define MLX5_IFC_DEFINER_BYTE_SELECTORS_NUM 8 6616 6617 struct mlx5_ifc_match_definer_match_mask_bits { 6618 u8 reserved_at_1c0[5][0x20]; 6619 u8 match_dw_8[0x20]; 6620 u8 match_dw_7[0x20]; 6621 u8 match_dw_6[0x20]; 6622 u8 match_dw_5[0x20]; 6623 u8 match_dw_4[0x20]; 6624 u8 match_dw_3[0x20]; 6625 u8 match_dw_2[0x20]; 6626 u8 match_dw_1[0x20]; 6627 u8 match_dw_0[0x20]; 6628 6629 u8 match_byte_7[0x8]; 6630 u8 match_byte_6[0x8]; 6631 u8 match_byte_5[0x8]; 6632 u8 match_byte_4[0x8]; 6633 6634 u8 match_byte_3[0x8]; 6635 u8 match_byte_2[0x8]; 6636 u8 match_byte_1[0x8]; 6637 u8 match_byte_0[0x8]; 6638 }; 6639 6640 struct mlx5_ifc_match_definer_bits { 6641 u8 modify_field_select[0x40]; 6642 6643 u8 reserved_at_40[0x40]; 6644 6645 u8 reserved_at_80[0x10]; 6646 u8 format_id[0x10]; 6647 6648 u8 reserved_at_a0[0x60]; 6649 6650 u8 format_select_dw3[0x8]; 6651 u8 format_select_dw2[0x8]; 6652 u8 format_select_dw1[0x8]; 6653 u8 format_select_dw0[0x8]; 6654 6655 u8 format_select_dw7[0x8]; 6656 u8 format_select_dw6[0x8]; 6657 u8 format_select_dw5[0x8]; 6658 u8 format_select_dw4[0x8]; 6659 6660 u8 reserved_at_100[0x18]; 6661 u8 format_select_dw8[0x8]; 6662 6663 u8 reserved_at_120[0x20]; 6664 6665 u8 format_select_byte3[0x8]; 6666 u8 format_select_byte2[0x8]; 6667 u8 format_select_byte1[0x8]; 6668 u8 format_select_byte0[0x8]; 6669 6670 u8 format_select_byte7[0x8]; 6671 u8 format_select_byte6[0x8]; 6672 u8 format_select_byte5[0x8]; 6673 u8 format_select_byte4[0x8]; 6674 6675 u8 reserved_at_180[0x40]; 6676 6677 union { 6678 struct { 6679 u8 match_mask[16][0x20]; 6680 }; 6681 struct mlx5_ifc_match_definer_match_mask_bits match_mask_format; 6682 }; 6683 }; 6684 6685 struct mlx5_ifc_general_obj_create_param_bits { 6686 u8 alias_object[0x1]; 6687 u8 reserved_at_1[0x2]; 6688 u8 log_obj_range[0x5]; 6689 u8 reserved_at_8[0x18]; 6690 }; 6691 6692 struct mlx5_ifc_general_obj_query_param_bits { 6693 u8 alias_object[0x1]; 6694 u8 obj_offset[0x1f]; 6695 }; 6696 6697 struct mlx5_ifc_general_obj_in_cmd_hdr_bits { 6698 u8 opcode[0x10]; 6699 u8 uid[0x10]; 6700 6701 u8 vhca_tunnel_id[0x10]; 6702 u8 obj_type[0x10]; 6703 6704 u8 obj_id[0x20]; 6705 6706 union { 6707 struct mlx5_ifc_general_obj_create_param_bits create; 6708 struct mlx5_ifc_general_obj_query_param_bits query; 6709 } op_param; 6710 }; 6711 6712 struct mlx5_ifc_general_obj_out_cmd_hdr_bits { 6713 u8 status[0x8]; 6714 u8 reserved_at_8[0x18]; 6715 6716 u8 syndrome[0x20]; 6717 6718 u8 obj_id[0x20]; 6719 6720 u8 reserved_at_60[0x20]; 6721 }; 6722 6723 struct mlx5_ifc_allow_other_vhca_access_in_bits { 6724 u8 opcode[0x10]; 6725 u8 uid[0x10]; 6726 u8 reserved_at_20[0x10]; 6727 u8 op_mod[0x10]; 6728 u8 reserved_at_40[0x50]; 6729 u8 object_type_to_be_accessed[0x10]; 6730 u8 object_id_to_be_accessed[0x20]; 6731 u8 reserved_at_c0[0x40]; 6732 union { 6733 u8 access_key_raw[0x100]; 6734 u8 access_key[8][0x20]; 6735 }; 6736 }; 6737 6738 struct mlx5_ifc_allow_other_vhca_access_out_bits { 6739 u8 status[0x8]; 6740 u8 reserved_at_8[0x18]; 6741 u8 syndrome[0x20]; 6742 u8 reserved_at_40[0x40]; 6743 }; 6744 6745 struct mlx5_ifc_modify_header_arg_bits { 6746 u8 reserved_at_0[0x80]; 6747 6748 u8 reserved_at_80[0x8]; 6749 u8 access_pd[0x18]; 6750 }; 6751 6752 struct mlx5_ifc_create_modify_header_arg_in_bits { 6753 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 6754 struct mlx5_ifc_modify_header_arg_bits arg; 6755 }; 6756 6757 struct mlx5_ifc_create_match_definer_in_bits { 6758 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 6759 6760 struct mlx5_ifc_match_definer_bits obj_context; 6761 }; 6762 6763 struct mlx5_ifc_create_match_definer_out_bits { 6764 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 6765 }; 6766 6767 struct mlx5_ifc_alias_context_bits { 6768 u8 vhca_id_to_be_accessed[0x10]; 6769 u8 reserved_at_10[0xd]; 6770 u8 status[0x3]; 6771 u8 object_id_to_be_accessed[0x20]; 6772 u8 reserved_at_40[0x40]; 6773 union { 6774 u8 access_key_raw[0x100]; 6775 u8 access_key[8][0x20]; 6776 }; 6777 u8 metadata[0x80]; 6778 }; 6779 6780 struct mlx5_ifc_create_alias_obj_in_bits { 6781 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 6782 struct mlx5_ifc_alias_context_bits alias_ctx; 6783 }; 6784 6785 enum { 6786 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 6787 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 6788 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 6789 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3, 6790 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_3 = 0x4, 6791 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_4 = 0x5, 6792 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_5 = 0x6, 6793 }; 6794 6795 struct mlx5_ifc_query_flow_group_out_bits { 6796 u8 status[0x8]; 6797 u8 reserved_at_8[0x18]; 6798 6799 u8 syndrome[0x20]; 6800 6801 u8 reserved_at_40[0xa0]; 6802 6803 u8 start_flow_index[0x20]; 6804 6805 u8 reserved_at_100[0x20]; 6806 6807 u8 end_flow_index[0x20]; 6808 6809 u8 reserved_at_140[0xa0]; 6810 6811 u8 reserved_at_1e0[0x18]; 6812 u8 match_criteria_enable[0x8]; 6813 6814 struct mlx5_ifc_fte_match_param_bits match_criteria; 6815 6816 u8 reserved_at_1200[0xe00]; 6817 }; 6818 6819 struct mlx5_ifc_query_flow_group_in_bits { 6820 u8 opcode[0x10]; 6821 u8 reserved_at_10[0x10]; 6822 6823 u8 reserved_at_20[0x10]; 6824 u8 op_mod[0x10]; 6825 6826 u8 reserved_at_40[0x40]; 6827 6828 u8 table_type[0x8]; 6829 u8 reserved_at_88[0x18]; 6830 6831 u8 reserved_at_a0[0x8]; 6832 u8 table_id[0x18]; 6833 6834 u8 group_id[0x20]; 6835 6836 u8 reserved_at_e0[0x120]; 6837 }; 6838 6839 struct mlx5_ifc_query_flow_counter_out_bits { 6840 u8 status[0x8]; 6841 u8 reserved_at_8[0x18]; 6842 6843 u8 syndrome[0x20]; 6844 6845 u8 reserved_at_40[0x40]; 6846 6847 struct mlx5_ifc_traffic_counter_bits flow_statistics[]; 6848 }; 6849 6850 struct mlx5_ifc_query_flow_counter_in_bits { 6851 u8 opcode[0x10]; 6852 u8 reserved_at_10[0x10]; 6853 6854 u8 reserved_at_20[0x10]; 6855 u8 op_mod[0x10]; 6856 6857 u8 reserved_at_40[0x80]; 6858 6859 u8 clear[0x1]; 6860 u8 reserved_at_c1[0xf]; 6861 u8 num_of_counters[0x10]; 6862 6863 u8 flow_counter_id[0x20]; 6864 }; 6865 6866 struct mlx5_ifc_query_esw_vport_context_out_bits { 6867 u8 status[0x8]; 6868 u8 reserved_at_8[0x18]; 6869 6870 u8 syndrome[0x20]; 6871 6872 u8 reserved_at_40[0x40]; 6873 6874 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 6875 }; 6876 6877 struct mlx5_ifc_query_esw_vport_context_in_bits { 6878 u8 opcode[0x10]; 6879 u8 reserved_at_10[0x10]; 6880 6881 u8 reserved_at_20[0x10]; 6882 u8 op_mod[0x10]; 6883 6884 u8 other_vport[0x1]; 6885 u8 reserved_at_41[0xf]; 6886 u8 vport_number[0x10]; 6887 6888 u8 reserved_at_60[0x20]; 6889 }; 6890 6891 struct mlx5_ifc_modify_esw_vport_context_out_bits { 6892 u8 status[0x8]; 6893 u8 reserved_at_8[0x18]; 6894 6895 u8 syndrome[0x20]; 6896 6897 u8 reserved_at_40[0x40]; 6898 }; 6899 6900 struct mlx5_ifc_esw_vport_context_fields_select_bits { 6901 u8 reserved_at_0[0x1b]; 6902 u8 fdb_to_vport_reg_c_id[0x1]; 6903 u8 vport_cvlan_insert[0x1]; 6904 u8 vport_svlan_insert[0x1]; 6905 u8 vport_cvlan_strip[0x1]; 6906 u8 vport_svlan_strip[0x1]; 6907 }; 6908 6909 struct mlx5_ifc_modify_esw_vport_context_in_bits { 6910 u8 opcode[0x10]; 6911 u8 reserved_at_10[0x10]; 6912 6913 u8 reserved_at_20[0x10]; 6914 u8 op_mod[0x10]; 6915 6916 u8 other_vport[0x1]; 6917 u8 reserved_at_41[0xf]; 6918 u8 vport_number[0x10]; 6919 6920 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select; 6921 6922 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 6923 }; 6924 6925 struct mlx5_ifc_query_eq_out_bits { 6926 u8 status[0x8]; 6927 u8 reserved_at_8[0x18]; 6928 6929 u8 syndrome[0x20]; 6930 6931 u8 reserved_at_40[0x40]; 6932 6933 struct mlx5_ifc_eqc_bits eq_context_entry; 6934 6935 u8 reserved_at_280[0x40]; 6936 6937 u8 event_bitmask[0x40]; 6938 6939 u8 reserved_at_300[0x580]; 6940 6941 u8 pas[][0x40]; 6942 }; 6943 6944 struct mlx5_ifc_query_eq_in_bits { 6945 u8 opcode[0x10]; 6946 u8 reserved_at_10[0x10]; 6947 6948 u8 reserved_at_20[0x10]; 6949 u8 op_mod[0x10]; 6950 6951 u8 reserved_at_40[0x18]; 6952 u8 eq_number[0x8]; 6953 6954 u8 reserved_at_60[0x20]; 6955 }; 6956 6957 struct mlx5_ifc_packet_reformat_context_in_bits { 6958 u8 reformat_type[0x8]; 6959 u8 reserved_at_8[0x4]; 6960 u8 reformat_param_0[0x4]; 6961 u8 reserved_at_10[0x6]; 6962 u8 reformat_data_size[0xa]; 6963 6964 u8 reformat_param_1[0x8]; 6965 u8 reserved_at_28[0x8]; 6966 u8 reformat_data[2][0x8]; 6967 6968 u8 more_reformat_data[][0x8]; 6969 }; 6970 6971 struct mlx5_ifc_query_packet_reformat_context_out_bits { 6972 u8 status[0x8]; 6973 u8 reserved_at_8[0x18]; 6974 6975 u8 syndrome[0x20]; 6976 6977 u8 reserved_at_40[0xa0]; 6978 6979 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context[]; 6980 }; 6981 6982 struct mlx5_ifc_query_packet_reformat_context_in_bits { 6983 u8 opcode[0x10]; 6984 u8 reserved_at_10[0x10]; 6985 6986 u8 reserved_at_20[0x10]; 6987 u8 op_mod[0x10]; 6988 6989 u8 packet_reformat_id[0x20]; 6990 6991 u8 reserved_at_60[0xa0]; 6992 }; 6993 6994 struct mlx5_ifc_alloc_packet_reformat_context_out_bits { 6995 u8 status[0x8]; 6996 u8 reserved_at_8[0x18]; 6997 6998 u8 syndrome[0x20]; 6999 7000 u8 packet_reformat_id[0x20]; 7001 7002 u8 reserved_at_60[0x20]; 7003 }; 7004 7005 enum { 7006 MLX5_REFORMAT_CONTEXT_ANCHOR_MAC_START = 0x1, 7007 MLX5_REFORMAT_CONTEXT_ANCHOR_IP_START = 0x7, 7008 MLX5_REFORMAT_CONTEXT_ANCHOR_TCP_UDP_START = 0x9, 7009 }; 7010 7011 enum mlx5_reformat_ctx_type { 7012 MLX5_REFORMAT_TYPE_L2_TO_VXLAN = 0x0, 7013 MLX5_REFORMAT_TYPE_L2_TO_NVGRE = 0x1, 7014 MLX5_REFORMAT_TYPE_L2_TO_L2_TUNNEL = 0x2, 7015 MLX5_REFORMAT_TYPE_L3_TUNNEL_TO_L2 = 0x3, 7016 MLX5_REFORMAT_TYPE_L2_TO_L3_TUNNEL = 0x4, 7017 MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_IPV4 = 0x5, 7018 MLX5_REFORMAT_TYPE_L2_TO_L3_ESP_TUNNEL = 0x6, 7019 MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_UDPV4 = 0x7, 7020 MLX5_REFORMAT_TYPE_DEL_ESP_TRANSPORT = 0x8, 7021 MLX5_REFORMAT_TYPE_L3_ESP_TUNNEL_TO_L2 = 0x9, 7022 MLX5_REFORMAT_TYPE_DEL_ESP_TRANSPORT_OVER_UDP = 0xa, 7023 MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_IPV6 = 0xb, 7024 MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_UDPV6 = 0xc, 7025 MLX5_REFORMAT_TYPE_INSERT_HDR = 0xf, 7026 MLX5_REFORMAT_TYPE_REMOVE_HDR = 0x10, 7027 MLX5_REFORMAT_TYPE_ADD_MACSEC = 0x11, 7028 MLX5_REFORMAT_TYPE_DEL_MACSEC = 0x12, 7029 }; 7030 7031 struct mlx5_ifc_alloc_packet_reformat_context_in_bits { 7032 u8 opcode[0x10]; 7033 u8 reserved_at_10[0x10]; 7034 7035 u8 reserved_at_20[0x10]; 7036 u8 op_mod[0x10]; 7037 7038 u8 reserved_at_40[0xa0]; 7039 7040 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context; 7041 }; 7042 7043 struct mlx5_ifc_dealloc_packet_reformat_context_out_bits { 7044 u8 status[0x8]; 7045 u8 reserved_at_8[0x18]; 7046 7047 u8 syndrome[0x20]; 7048 7049 u8 reserved_at_40[0x40]; 7050 }; 7051 7052 struct mlx5_ifc_dealloc_packet_reformat_context_in_bits { 7053 u8 opcode[0x10]; 7054 u8 reserved_at_10[0x10]; 7055 7056 u8 reserved_20[0x10]; 7057 u8 op_mod[0x10]; 7058 7059 u8 packet_reformat_id[0x20]; 7060 7061 u8 reserved_60[0x20]; 7062 }; 7063 7064 struct mlx5_ifc_set_action_in_bits { 7065 u8 action_type[0x4]; 7066 u8 field[0xc]; 7067 u8 reserved_at_10[0x3]; 7068 u8 offset[0x5]; 7069 u8 reserved_at_18[0x3]; 7070 u8 length[0x5]; 7071 7072 u8 data[0x20]; 7073 }; 7074 7075 struct mlx5_ifc_add_action_in_bits { 7076 u8 action_type[0x4]; 7077 u8 field[0xc]; 7078 u8 reserved_at_10[0x10]; 7079 7080 u8 data[0x20]; 7081 }; 7082 7083 struct mlx5_ifc_copy_action_in_bits { 7084 u8 action_type[0x4]; 7085 u8 src_field[0xc]; 7086 u8 reserved_at_10[0x3]; 7087 u8 src_offset[0x5]; 7088 u8 reserved_at_18[0x3]; 7089 u8 length[0x5]; 7090 7091 u8 reserved_at_20[0x4]; 7092 u8 dst_field[0xc]; 7093 u8 reserved_at_30[0x3]; 7094 u8 dst_offset[0x5]; 7095 u8 reserved_at_38[0x8]; 7096 }; 7097 7098 union mlx5_ifc_set_add_copy_action_in_auto_bits { 7099 struct mlx5_ifc_set_action_in_bits set_action_in; 7100 struct mlx5_ifc_add_action_in_bits add_action_in; 7101 struct mlx5_ifc_copy_action_in_bits copy_action_in; 7102 u8 reserved_at_0[0x40]; 7103 }; 7104 7105 enum { 7106 MLX5_ACTION_TYPE_SET = 0x1, 7107 MLX5_ACTION_TYPE_ADD = 0x2, 7108 MLX5_ACTION_TYPE_COPY = 0x3, 7109 }; 7110 7111 enum { 7112 MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16 = 0x1, 7113 MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0 = 0x2, 7114 MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE = 0x3, 7115 MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16 = 0x4, 7116 MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0 = 0x5, 7117 MLX5_ACTION_IN_FIELD_OUT_IP_DSCP = 0x6, 7118 MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS = 0x7, 7119 MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT = 0x8, 7120 MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT = 0x9, 7121 MLX5_ACTION_IN_FIELD_OUT_IP_TTL = 0xa, 7122 MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT = 0xb, 7123 MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT = 0xc, 7124 MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96 = 0xd, 7125 MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64 = 0xe, 7126 MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32 = 0xf, 7127 MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0 = 0x10, 7128 MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96 = 0x11, 7129 MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64 = 0x12, 7130 MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32 = 0x13, 7131 MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0 = 0x14, 7132 MLX5_ACTION_IN_FIELD_OUT_SIPV4 = 0x15, 7133 MLX5_ACTION_IN_FIELD_OUT_DIPV4 = 0x16, 7134 MLX5_ACTION_IN_FIELD_OUT_FIRST_VID = 0x17, 7135 MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47, 7136 MLX5_ACTION_IN_FIELD_METADATA_REG_A = 0x49, 7137 MLX5_ACTION_IN_FIELD_METADATA_REG_B = 0x50, 7138 MLX5_ACTION_IN_FIELD_METADATA_REG_C_0 = 0x51, 7139 MLX5_ACTION_IN_FIELD_METADATA_REG_C_1 = 0x52, 7140 MLX5_ACTION_IN_FIELD_METADATA_REG_C_2 = 0x53, 7141 MLX5_ACTION_IN_FIELD_METADATA_REG_C_3 = 0x54, 7142 MLX5_ACTION_IN_FIELD_METADATA_REG_C_4 = 0x55, 7143 MLX5_ACTION_IN_FIELD_METADATA_REG_C_5 = 0x56, 7144 MLX5_ACTION_IN_FIELD_METADATA_REG_C_6 = 0x57, 7145 MLX5_ACTION_IN_FIELD_METADATA_REG_C_7 = 0x58, 7146 MLX5_ACTION_IN_FIELD_OUT_TCP_SEQ_NUM = 0x59, 7147 MLX5_ACTION_IN_FIELD_OUT_TCP_ACK_NUM = 0x5B, 7148 MLX5_ACTION_IN_FIELD_IPSEC_SYNDROME = 0x5D, 7149 MLX5_ACTION_IN_FIELD_OUT_EMD_47_32 = 0x6F, 7150 MLX5_ACTION_IN_FIELD_OUT_EMD_31_0 = 0x70, 7151 }; 7152 7153 struct mlx5_ifc_alloc_modify_header_context_out_bits { 7154 u8 status[0x8]; 7155 u8 reserved_at_8[0x18]; 7156 7157 u8 syndrome[0x20]; 7158 7159 u8 modify_header_id[0x20]; 7160 7161 u8 reserved_at_60[0x20]; 7162 }; 7163 7164 struct mlx5_ifc_alloc_modify_header_context_in_bits { 7165 u8 opcode[0x10]; 7166 u8 reserved_at_10[0x10]; 7167 7168 u8 reserved_at_20[0x10]; 7169 u8 op_mod[0x10]; 7170 7171 u8 reserved_at_40[0x20]; 7172 7173 u8 table_type[0x8]; 7174 u8 reserved_at_68[0x10]; 7175 u8 num_of_actions[0x8]; 7176 7177 union mlx5_ifc_set_add_copy_action_in_auto_bits actions[]; 7178 }; 7179 7180 struct mlx5_ifc_dealloc_modify_header_context_out_bits { 7181 u8 status[0x8]; 7182 u8 reserved_at_8[0x18]; 7183 7184 u8 syndrome[0x20]; 7185 7186 u8 reserved_at_40[0x40]; 7187 }; 7188 7189 struct mlx5_ifc_dealloc_modify_header_context_in_bits { 7190 u8 opcode[0x10]; 7191 u8 reserved_at_10[0x10]; 7192 7193 u8 reserved_at_20[0x10]; 7194 u8 op_mod[0x10]; 7195 7196 u8 modify_header_id[0x20]; 7197 7198 u8 reserved_at_60[0x20]; 7199 }; 7200 7201 struct mlx5_ifc_query_modify_header_context_in_bits { 7202 u8 opcode[0x10]; 7203 u8 uid[0x10]; 7204 7205 u8 reserved_at_20[0x10]; 7206 u8 op_mod[0x10]; 7207 7208 u8 modify_header_id[0x20]; 7209 7210 u8 reserved_at_60[0xa0]; 7211 }; 7212 7213 struct mlx5_ifc_query_dct_out_bits { 7214 u8 status[0x8]; 7215 u8 reserved_at_8[0x18]; 7216 7217 u8 syndrome[0x20]; 7218 7219 u8 reserved_at_40[0x40]; 7220 7221 struct mlx5_ifc_dctc_bits dct_context_entry; 7222 7223 u8 reserved_at_280[0x180]; 7224 }; 7225 7226 struct mlx5_ifc_query_dct_in_bits { 7227 u8 opcode[0x10]; 7228 u8 reserved_at_10[0x10]; 7229 7230 u8 reserved_at_20[0x10]; 7231 u8 op_mod[0x10]; 7232 7233 u8 reserved_at_40[0x8]; 7234 u8 dctn[0x18]; 7235 7236 u8 reserved_at_60[0x20]; 7237 }; 7238 7239 struct mlx5_ifc_query_cq_out_bits { 7240 u8 status[0x8]; 7241 u8 reserved_at_8[0x18]; 7242 7243 u8 syndrome[0x20]; 7244 7245 u8 reserved_at_40[0x40]; 7246 7247 struct mlx5_ifc_cqc_bits cq_context; 7248 7249 u8 reserved_at_280[0x600]; 7250 7251 u8 pas[][0x40]; 7252 }; 7253 7254 struct mlx5_ifc_query_cq_in_bits { 7255 u8 opcode[0x10]; 7256 u8 reserved_at_10[0x10]; 7257 7258 u8 reserved_at_20[0x10]; 7259 u8 op_mod[0x10]; 7260 7261 u8 reserved_at_40[0x8]; 7262 u8 cqn[0x18]; 7263 7264 u8 reserved_at_60[0x20]; 7265 }; 7266 7267 struct mlx5_ifc_query_cong_status_out_bits { 7268 u8 status[0x8]; 7269 u8 reserved_at_8[0x18]; 7270 7271 u8 syndrome[0x20]; 7272 7273 u8 reserved_at_40[0x20]; 7274 7275 u8 enable[0x1]; 7276 u8 tag_enable[0x1]; 7277 u8 reserved_at_62[0x1e]; 7278 }; 7279 7280 struct mlx5_ifc_query_cong_status_in_bits { 7281 u8 opcode[0x10]; 7282 u8 reserved_at_10[0x10]; 7283 7284 u8 reserved_at_20[0x10]; 7285 u8 op_mod[0x10]; 7286 7287 u8 reserved_at_40[0x18]; 7288 u8 priority[0x4]; 7289 u8 cong_protocol[0x4]; 7290 7291 u8 reserved_at_60[0x20]; 7292 }; 7293 7294 struct mlx5_ifc_query_cong_statistics_out_bits { 7295 u8 status[0x8]; 7296 u8 reserved_at_8[0x18]; 7297 7298 u8 syndrome[0x20]; 7299 7300 u8 reserved_at_40[0x40]; 7301 7302 u8 rp_cur_flows[0x20]; 7303 7304 u8 sum_flows[0x20]; 7305 7306 u8 rp_cnp_ignored_high[0x20]; 7307 7308 u8 rp_cnp_ignored_low[0x20]; 7309 7310 u8 rp_cnp_handled_high[0x20]; 7311 7312 u8 rp_cnp_handled_low[0x20]; 7313 7314 u8 reserved_at_140[0x100]; 7315 7316 u8 time_stamp_high[0x20]; 7317 7318 u8 time_stamp_low[0x20]; 7319 7320 u8 accumulators_period[0x20]; 7321 7322 u8 np_ecn_marked_roce_packets_high[0x20]; 7323 7324 u8 np_ecn_marked_roce_packets_low[0x20]; 7325 7326 u8 np_cnp_sent_high[0x20]; 7327 7328 u8 np_cnp_sent_low[0x20]; 7329 7330 u8 reserved_at_320[0x560]; 7331 }; 7332 7333 struct mlx5_ifc_query_cong_statistics_in_bits { 7334 u8 opcode[0x10]; 7335 u8 reserved_at_10[0x10]; 7336 7337 u8 reserved_at_20[0x10]; 7338 u8 op_mod[0x10]; 7339 7340 u8 clear[0x1]; 7341 u8 reserved_at_41[0x1f]; 7342 7343 u8 reserved_at_60[0x20]; 7344 }; 7345 7346 struct mlx5_ifc_query_cong_params_out_bits { 7347 u8 status[0x8]; 7348 u8 reserved_at_8[0x18]; 7349 7350 u8 syndrome[0x20]; 7351 7352 u8 reserved_at_40[0x40]; 7353 7354 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 7355 }; 7356 7357 struct mlx5_ifc_query_cong_params_in_bits { 7358 u8 opcode[0x10]; 7359 u8 reserved_at_10[0x10]; 7360 7361 u8 reserved_at_20[0x10]; 7362 u8 op_mod[0x10]; 7363 7364 u8 reserved_at_40[0x1c]; 7365 u8 cong_protocol[0x4]; 7366 7367 u8 reserved_at_60[0x20]; 7368 }; 7369 7370 struct mlx5_ifc_query_adapter_out_bits { 7371 u8 status[0x8]; 7372 u8 reserved_at_8[0x18]; 7373 7374 u8 syndrome[0x20]; 7375 7376 u8 reserved_at_40[0x40]; 7377 7378 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct; 7379 }; 7380 7381 struct mlx5_ifc_query_adapter_in_bits { 7382 u8 opcode[0x10]; 7383 u8 reserved_at_10[0x10]; 7384 7385 u8 reserved_at_20[0x10]; 7386 u8 op_mod[0x10]; 7387 7388 u8 reserved_at_40[0x40]; 7389 }; 7390 7391 struct mlx5_ifc_qp_2rst_out_bits { 7392 u8 status[0x8]; 7393 u8 reserved_at_8[0x18]; 7394 7395 u8 syndrome[0x20]; 7396 7397 u8 reserved_at_40[0x40]; 7398 }; 7399 7400 struct mlx5_ifc_qp_2rst_in_bits { 7401 u8 opcode[0x10]; 7402 u8 uid[0x10]; 7403 7404 u8 reserved_at_20[0x10]; 7405 u8 op_mod[0x10]; 7406 7407 u8 reserved_at_40[0x8]; 7408 u8 qpn[0x18]; 7409 7410 u8 reserved_at_60[0x20]; 7411 }; 7412 7413 struct mlx5_ifc_qp_2err_out_bits { 7414 u8 status[0x8]; 7415 u8 reserved_at_8[0x18]; 7416 7417 u8 syndrome[0x20]; 7418 7419 u8 reserved_at_40[0x40]; 7420 }; 7421 7422 struct mlx5_ifc_qp_2err_in_bits { 7423 u8 opcode[0x10]; 7424 u8 uid[0x10]; 7425 7426 u8 reserved_at_20[0x10]; 7427 u8 op_mod[0x10]; 7428 7429 u8 reserved_at_40[0x8]; 7430 u8 qpn[0x18]; 7431 7432 u8 reserved_at_60[0x20]; 7433 }; 7434 7435 struct mlx5_ifc_trans_page_fault_info_bits { 7436 u8 error[0x1]; 7437 u8 reserved_at_1[0x4]; 7438 u8 page_fault_type[0x3]; 7439 u8 wq_number[0x18]; 7440 7441 u8 reserved_at_20[0x8]; 7442 u8 fault_token[0x18]; 7443 }; 7444 7445 struct mlx5_ifc_mem_page_fault_info_bits { 7446 u8 error[0x1]; 7447 u8 reserved_at_1[0xf]; 7448 u8 fault_token_47_32[0x10]; 7449 7450 u8 fault_token_31_0[0x20]; 7451 }; 7452 7453 union mlx5_ifc_page_fault_resume_in_page_fault_info_auto_bits { 7454 struct mlx5_ifc_trans_page_fault_info_bits trans_page_fault_info; 7455 struct mlx5_ifc_mem_page_fault_info_bits mem_page_fault_info; 7456 u8 reserved_at_0[0x40]; 7457 }; 7458 7459 struct mlx5_ifc_page_fault_resume_out_bits { 7460 u8 status[0x8]; 7461 u8 reserved_at_8[0x18]; 7462 7463 u8 syndrome[0x20]; 7464 7465 u8 reserved_at_40[0x40]; 7466 }; 7467 7468 struct mlx5_ifc_page_fault_resume_in_bits { 7469 u8 opcode[0x10]; 7470 u8 reserved_at_10[0x10]; 7471 7472 u8 reserved_at_20[0x10]; 7473 u8 op_mod[0x10]; 7474 7475 union mlx5_ifc_page_fault_resume_in_page_fault_info_auto_bits 7476 page_fault_info; 7477 }; 7478 7479 struct mlx5_ifc_nop_out_bits { 7480 u8 status[0x8]; 7481 u8 reserved_at_8[0x18]; 7482 7483 u8 syndrome[0x20]; 7484 7485 u8 reserved_at_40[0x40]; 7486 }; 7487 7488 struct mlx5_ifc_nop_in_bits { 7489 u8 opcode[0x10]; 7490 u8 reserved_at_10[0x10]; 7491 7492 u8 reserved_at_20[0x10]; 7493 u8 op_mod[0x10]; 7494 7495 u8 reserved_at_40[0x40]; 7496 }; 7497 7498 struct mlx5_ifc_modify_vport_state_out_bits { 7499 u8 status[0x8]; 7500 u8 reserved_at_8[0x18]; 7501 7502 u8 syndrome[0x20]; 7503 7504 u8 reserved_at_40[0x40]; 7505 }; 7506 7507 struct mlx5_ifc_modify_vport_state_in_bits { 7508 u8 opcode[0x10]; 7509 u8 reserved_at_10[0x10]; 7510 7511 u8 reserved_at_20[0x10]; 7512 u8 op_mod[0x10]; 7513 7514 u8 other_vport[0x1]; 7515 u8 reserved_at_41[0xf]; 7516 u8 vport_number[0x10]; 7517 7518 u8 reserved_at_60[0x18]; 7519 u8 admin_state[0x4]; 7520 u8 reserved_at_7c[0x4]; 7521 }; 7522 7523 struct mlx5_ifc_modify_tis_out_bits { 7524 u8 status[0x8]; 7525 u8 reserved_at_8[0x18]; 7526 7527 u8 syndrome[0x20]; 7528 7529 u8 reserved_at_40[0x40]; 7530 }; 7531 7532 struct mlx5_ifc_modify_tis_bitmask_bits { 7533 u8 reserved_at_0[0x20]; 7534 7535 u8 reserved_at_20[0x1d]; 7536 u8 lag_tx_port_affinity[0x1]; 7537 u8 strict_lag_tx_port_affinity[0x1]; 7538 u8 prio[0x1]; 7539 }; 7540 7541 struct mlx5_ifc_modify_tis_in_bits { 7542 u8 opcode[0x10]; 7543 u8 uid[0x10]; 7544 7545 u8 reserved_at_20[0x10]; 7546 u8 op_mod[0x10]; 7547 7548 u8 reserved_at_40[0x8]; 7549 u8 tisn[0x18]; 7550 7551 u8 reserved_at_60[0x20]; 7552 7553 struct mlx5_ifc_modify_tis_bitmask_bits bitmask; 7554 7555 u8 reserved_at_c0[0x40]; 7556 7557 struct mlx5_ifc_tisc_bits ctx; 7558 }; 7559 7560 struct mlx5_ifc_modify_tir_bitmask_bits { 7561 u8 reserved_at_0[0x20]; 7562 7563 u8 reserved_at_20[0x1b]; 7564 u8 self_lb_en[0x1]; 7565 u8 reserved_at_3c[0x1]; 7566 u8 hash[0x1]; 7567 u8 reserved_at_3e[0x1]; 7568 u8 packet_merge[0x1]; 7569 }; 7570 7571 struct mlx5_ifc_modify_tir_out_bits { 7572 u8 status[0x8]; 7573 u8 reserved_at_8[0x18]; 7574 7575 u8 syndrome[0x20]; 7576 7577 u8 reserved_at_40[0x40]; 7578 }; 7579 7580 struct mlx5_ifc_modify_tir_in_bits { 7581 u8 opcode[0x10]; 7582 u8 uid[0x10]; 7583 7584 u8 reserved_at_20[0x10]; 7585 u8 op_mod[0x10]; 7586 7587 u8 reserved_at_40[0x8]; 7588 u8 tirn[0x18]; 7589 7590 u8 reserved_at_60[0x20]; 7591 7592 struct mlx5_ifc_modify_tir_bitmask_bits bitmask; 7593 7594 u8 reserved_at_c0[0x40]; 7595 7596 struct mlx5_ifc_tirc_bits ctx; 7597 }; 7598 7599 struct mlx5_ifc_modify_sq_out_bits { 7600 u8 status[0x8]; 7601 u8 reserved_at_8[0x18]; 7602 7603 u8 syndrome[0x20]; 7604 7605 u8 reserved_at_40[0x40]; 7606 }; 7607 7608 struct mlx5_ifc_modify_sq_in_bits { 7609 u8 opcode[0x10]; 7610 u8 uid[0x10]; 7611 7612 u8 reserved_at_20[0x10]; 7613 u8 op_mod[0x10]; 7614 7615 u8 sq_state[0x4]; 7616 u8 reserved_at_44[0x4]; 7617 u8 sqn[0x18]; 7618 7619 u8 reserved_at_60[0x20]; 7620 7621 u8 modify_bitmask[0x40]; 7622 7623 u8 reserved_at_c0[0x40]; 7624 7625 struct mlx5_ifc_sqc_bits ctx; 7626 }; 7627 7628 struct mlx5_ifc_modify_scheduling_element_out_bits { 7629 u8 status[0x8]; 7630 u8 reserved_at_8[0x18]; 7631 7632 u8 syndrome[0x20]; 7633 7634 u8 reserved_at_40[0x1c0]; 7635 }; 7636 7637 enum { 7638 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1, 7639 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2, 7640 }; 7641 7642 struct mlx5_ifc_modify_scheduling_element_in_bits { 7643 u8 opcode[0x10]; 7644 u8 reserved_at_10[0x10]; 7645 7646 u8 reserved_at_20[0x10]; 7647 u8 op_mod[0x10]; 7648 7649 u8 scheduling_hierarchy[0x8]; 7650 u8 reserved_at_48[0x18]; 7651 7652 u8 scheduling_element_id[0x20]; 7653 7654 u8 reserved_at_80[0x20]; 7655 7656 u8 modify_bitmask[0x20]; 7657 7658 u8 reserved_at_c0[0x40]; 7659 7660 struct mlx5_ifc_scheduling_context_bits scheduling_context; 7661 7662 u8 reserved_at_300[0x100]; 7663 }; 7664 7665 struct mlx5_ifc_modify_rqt_out_bits { 7666 u8 status[0x8]; 7667 u8 reserved_at_8[0x18]; 7668 7669 u8 syndrome[0x20]; 7670 7671 u8 reserved_at_40[0x40]; 7672 }; 7673 7674 struct mlx5_ifc_rqt_bitmask_bits { 7675 u8 reserved_at_0[0x20]; 7676 7677 u8 reserved_at_20[0x1f]; 7678 u8 rqn_list[0x1]; 7679 }; 7680 7681 struct mlx5_ifc_modify_rqt_in_bits { 7682 u8 opcode[0x10]; 7683 u8 uid[0x10]; 7684 7685 u8 reserved_at_20[0x10]; 7686 u8 op_mod[0x10]; 7687 7688 u8 reserved_at_40[0x8]; 7689 u8 rqtn[0x18]; 7690 7691 u8 reserved_at_60[0x20]; 7692 7693 struct mlx5_ifc_rqt_bitmask_bits bitmask; 7694 7695 u8 reserved_at_c0[0x40]; 7696 7697 struct mlx5_ifc_rqtc_bits ctx; 7698 }; 7699 7700 struct mlx5_ifc_modify_rq_out_bits { 7701 u8 status[0x8]; 7702 u8 reserved_at_8[0x18]; 7703 7704 u8 syndrome[0x20]; 7705 7706 u8 reserved_at_40[0x40]; 7707 }; 7708 7709 enum { 7710 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1, 7711 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2, 7712 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3, 7713 }; 7714 7715 struct mlx5_ifc_modify_rq_in_bits { 7716 u8 opcode[0x10]; 7717 u8 uid[0x10]; 7718 7719 u8 reserved_at_20[0x10]; 7720 u8 op_mod[0x10]; 7721 7722 u8 rq_state[0x4]; 7723 u8 reserved_at_44[0x4]; 7724 u8 rqn[0x18]; 7725 7726 u8 reserved_at_60[0x20]; 7727 7728 u8 modify_bitmask[0x40]; 7729 7730 u8 reserved_at_c0[0x40]; 7731 7732 struct mlx5_ifc_rqc_bits ctx; 7733 }; 7734 7735 struct mlx5_ifc_modify_rmp_out_bits { 7736 u8 status[0x8]; 7737 u8 reserved_at_8[0x18]; 7738 7739 u8 syndrome[0x20]; 7740 7741 u8 reserved_at_40[0x40]; 7742 }; 7743 7744 struct mlx5_ifc_rmp_bitmask_bits { 7745 u8 reserved_at_0[0x20]; 7746 7747 u8 reserved_at_20[0x1f]; 7748 u8 lwm[0x1]; 7749 }; 7750 7751 struct mlx5_ifc_modify_rmp_in_bits { 7752 u8 opcode[0x10]; 7753 u8 uid[0x10]; 7754 7755 u8 reserved_at_20[0x10]; 7756 u8 op_mod[0x10]; 7757 7758 u8 rmp_state[0x4]; 7759 u8 reserved_at_44[0x4]; 7760 u8 rmpn[0x18]; 7761 7762 u8 reserved_at_60[0x20]; 7763 7764 struct mlx5_ifc_rmp_bitmask_bits bitmask; 7765 7766 u8 reserved_at_c0[0x40]; 7767 7768 struct mlx5_ifc_rmpc_bits ctx; 7769 }; 7770 7771 struct mlx5_ifc_modify_nic_vport_context_out_bits { 7772 u8 status[0x8]; 7773 u8 reserved_at_8[0x18]; 7774 7775 u8 syndrome[0x20]; 7776 7777 u8 reserved_at_40[0x40]; 7778 }; 7779 7780 struct mlx5_ifc_modify_nic_vport_field_select_bits { 7781 u8 reserved_at_0[0x12]; 7782 u8 affiliation[0x1]; 7783 u8 reserved_at_13[0x1]; 7784 u8 disable_uc_local_lb[0x1]; 7785 u8 disable_mc_local_lb[0x1]; 7786 u8 node_guid[0x1]; 7787 u8 port_guid[0x1]; 7788 u8 min_inline[0x1]; 7789 u8 mtu[0x1]; 7790 u8 change_event[0x1]; 7791 u8 promisc[0x1]; 7792 u8 permanent_address[0x1]; 7793 u8 addresses_list[0x1]; 7794 u8 roce_en[0x1]; 7795 u8 reserved_at_1f[0x1]; 7796 }; 7797 7798 struct mlx5_ifc_modify_nic_vport_context_in_bits { 7799 u8 opcode[0x10]; 7800 u8 reserved_at_10[0x10]; 7801 7802 u8 reserved_at_20[0x10]; 7803 u8 op_mod[0x10]; 7804 7805 u8 other_vport[0x1]; 7806 u8 reserved_at_41[0xf]; 7807 u8 vport_number[0x10]; 7808 7809 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select; 7810 7811 u8 reserved_at_80[0x780]; 7812 7813 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 7814 }; 7815 7816 struct mlx5_ifc_modify_hca_vport_context_out_bits { 7817 u8 status[0x8]; 7818 u8 reserved_at_8[0x18]; 7819 7820 u8 syndrome[0x20]; 7821 7822 u8 reserved_at_40[0x40]; 7823 }; 7824 7825 struct mlx5_ifc_modify_hca_vport_context_in_bits { 7826 u8 opcode[0x10]; 7827 u8 reserved_at_10[0x10]; 7828 7829 u8 reserved_at_20[0x10]; 7830 u8 op_mod[0x10]; 7831 7832 u8 other_vport[0x1]; 7833 u8 reserved_at_41[0xb]; 7834 u8 port_num[0x4]; 7835 u8 vport_number[0x10]; 7836 7837 u8 reserved_at_60[0x20]; 7838 7839 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 7840 }; 7841 7842 struct mlx5_ifc_modify_cq_out_bits { 7843 u8 status[0x8]; 7844 u8 reserved_at_8[0x18]; 7845 7846 u8 syndrome[0x20]; 7847 7848 u8 reserved_at_40[0x40]; 7849 }; 7850 7851 enum { 7852 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0, 7853 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1, 7854 }; 7855 7856 struct mlx5_ifc_modify_cq_in_bits { 7857 u8 opcode[0x10]; 7858 u8 uid[0x10]; 7859 7860 u8 reserved_at_20[0x10]; 7861 u8 op_mod[0x10]; 7862 7863 u8 reserved_at_40[0x8]; 7864 u8 cqn[0x18]; 7865 7866 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select; 7867 7868 struct mlx5_ifc_cqc_bits cq_context; 7869 7870 u8 reserved_at_280[0x60]; 7871 7872 u8 cq_umem_valid[0x1]; 7873 u8 reserved_at_2e1[0x1f]; 7874 7875 u8 reserved_at_300[0x580]; 7876 7877 u8 pas[][0x40]; 7878 }; 7879 7880 struct mlx5_ifc_modify_cong_status_out_bits { 7881 u8 status[0x8]; 7882 u8 reserved_at_8[0x18]; 7883 7884 u8 syndrome[0x20]; 7885 7886 u8 reserved_at_40[0x40]; 7887 }; 7888 7889 struct mlx5_ifc_modify_cong_status_in_bits { 7890 u8 opcode[0x10]; 7891 u8 reserved_at_10[0x10]; 7892 7893 u8 reserved_at_20[0x10]; 7894 u8 op_mod[0x10]; 7895 7896 u8 reserved_at_40[0x18]; 7897 u8 priority[0x4]; 7898 u8 cong_protocol[0x4]; 7899 7900 u8 enable[0x1]; 7901 u8 tag_enable[0x1]; 7902 u8 reserved_at_62[0x1e]; 7903 }; 7904 7905 struct mlx5_ifc_modify_cong_params_out_bits { 7906 u8 status[0x8]; 7907 u8 reserved_at_8[0x18]; 7908 7909 u8 syndrome[0x20]; 7910 7911 u8 reserved_at_40[0x40]; 7912 }; 7913 7914 struct mlx5_ifc_modify_cong_params_in_bits { 7915 u8 opcode[0x10]; 7916 u8 reserved_at_10[0x10]; 7917 7918 u8 reserved_at_20[0x10]; 7919 u8 op_mod[0x10]; 7920 7921 u8 reserved_at_40[0x1c]; 7922 u8 cong_protocol[0x4]; 7923 7924 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select; 7925 7926 u8 reserved_at_80[0x80]; 7927 7928 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 7929 }; 7930 7931 struct mlx5_ifc_manage_pages_out_bits { 7932 u8 status[0x8]; 7933 u8 reserved_at_8[0x18]; 7934 7935 u8 syndrome[0x20]; 7936 7937 u8 output_num_entries[0x20]; 7938 7939 u8 reserved_at_60[0x20]; 7940 7941 u8 pas[][0x40]; 7942 }; 7943 7944 enum { 7945 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL = 0x0, 7946 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS = 0x1, 7947 MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES = 0x2, 7948 }; 7949 7950 struct mlx5_ifc_manage_pages_in_bits { 7951 u8 opcode[0x10]; 7952 u8 reserved_at_10[0x10]; 7953 7954 u8 reserved_at_20[0x10]; 7955 u8 op_mod[0x10]; 7956 7957 u8 embedded_cpu_function[0x1]; 7958 u8 reserved_at_41[0xf]; 7959 u8 function_id[0x10]; 7960 7961 u8 input_num_entries[0x20]; 7962 7963 u8 pas[][0x40]; 7964 }; 7965 7966 struct mlx5_ifc_mad_ifc_out_bits { 7967 u8 status[0x8]; 7968 u8 reserved_at_8[0x18]; 7969 7970 u8 syndrome[0x20]; 7971 7972 u8 reserved_at_40[0x40]; 7973 7974 u8 response_mad_packet[256][0x8]; 7975 }; 7976 7977 struct mlx5_ifc_mad_ifc_in_bits { 7978 u8 opcode[0x10]; 7979 u8 reserved_at_10[0x10]; 7980 7981 u8 reserved_at_20[0x10]; 7982 u8 op_mod[0x10]; 7983 7984 u8 remote_lid[0x10]; 7985 u8 plane_index[0x8]; 7986 u8 port[0x8]; 7987 7988 u8 reserved_at_60[0x20]; 7989 7990 u8 mad[256][0x8]; 7991 }; 7992 7993 struct mlx5_ifc_init_hca_out_bits { 7994 u8 status[0x8]; 7995 u8 reserved_at_8[0x18]; 7996 7997 u8 syndrome[0x20]; 7998 7999 u8 reserved_at_40[0x40]; 8000 }; 8001 8002 struct mlx5_ifc_init_hca_in_bits { 8003 u8 opcode[0x10]; 8004 u8 reserved_at_10[0x10]; 8005 8006 u8 reserved_at_20[0x10]; 8007 u8 op_mod[0x10]; 8008 8009 u8 reserved_at_40[0x20]; 8010 8011 u8 reserved_at_60[0x2]; 8012 u8 sw_vhca_id[0xe]; 8013 u8 reserved_at_70[0x10]; 8014 8015 u8 sw_owner_id[4][0x20]; 8016 }; 8017 8018 struct mlx5_ifc_init2rtr_qp_out_bits { 8019 u8 status[0x8]; 8020 u8 reserved_at_8[0x18]; 8021 8022 u8 syndrome[0x20]; 8023 8024 u8 reserved_at_40[0x20]; 8025 u8 ece[0x20]; 8026 }; 8027 8028 struct mlx5_ifc_init2rtr_qp_in_bits { 8029 u8 opcode[0x10]; 8030 u8 uid[0x10]; 8031 8032 u8 reserved_at_20[0x10]; 8033 u8 op_mod[0x10]; 8034 8035 u8 reserved_at_40[0x8]; 8036 u8 qpn[0x18]; 8037 8038 u8 reserved_at_60[0x20]; 8039 8040 u8 opt_param_mask[0x20]; 8041 8042 u8 ece[0x20]; 8043 8044 struct mlx5_ifc_qpc_bits qpc; 8045 8046 u8 reserved_at_800[0x80]; 8047 }; 8048 8049 struct mlx5_ifc_init2init_qp_out_bits { 8050 u8 status[0x8]; 8051 u8 reserved_at_8[0x18]; 8052 8053 u8 syndrome[0x20]; 8054 8055 u8 reserved_at_40[0x20]; 8056 u8 ece[0x20]; 8057 }; 8058 8059 struct mlx5_ifc_init2init_qp_in_bits { 8060 u8 opcode[0x10]; 8061 u8 uid[0x10]; 8062 8063 u8 reserved_at_20[0x10]; 8064 u8 op_mod[0x10]; 8065 8066 u8 reserved_at_40[0x8]; 8067 u8 qpn[0x18]; 8068 8069 u8 reserved_at_60[0x20]; 8070 8071 u8 opt_param_mask[0x20]; 8072 8073 u8 ece[0x20]; 8074 8075 struct mlx5_ifc_qpc_bits qpc; 8076 8077 u8 reserved_at_800[0x80]; 8078 }; 8079 8080 struct mlx5_ifc_get_dropped_packet_log_out_bits { 8081 u8 status[0x8]; 8082 u8 reserved_at_8[0x18]; 8083 8084 u8 syndrome[0x20]; 8085 8086 u8 reserved_at_40[0x40]; 8087 8088 u8 packet_headers_log[128][0x8]; 8089 8090 u8 packet_syndrome[64][0x8]; 8091 }; 8092 8093 struct mlx5_ifc_get_dropped_packet_log_in_bits { 8094 u8 opcode[0x10]; 8095 u8 reserved_at_10[0x10]; 8096 8097 u8 reserved_at_20[0x10]; 8098 u8 op_mod[0x10]; 8099 8100 u8 reserved_at_40[0x40]; 8101 }; 8102 8103 struct mlx5_ifc_gen_eqe_in_bits { 8104 u8 opcode[0x10]; 8105 u8 reserved_at_10[0x10]; 8106 8107 u8 reserved_at_20[0x10]; 8108 u8 op_mod[0x10]; 8109 8110 u8 reserved_at_40[0x18]; 8111 u8 eq_number[0x8]; 8112 8113 u8 reserved_at_60[0x20]; 8114 8115 u8 eqe[64][0x8]; 8116 }; 8117 8118 struct mlx5_ifc_gen_eq_out_bits { 8119 u8 status[0x8]; 8120 u8 reserved_at_8[0x18]; 8121 8122 u8 syndrome[0x20]; 8123 8124 u8 reserved_at_40[0x40]; 8125 }; 8126 8127 struct mlx5_ifc_enable_hca_out_bits { 8128 u8 status[0x8]; 8129 u8 reserved_at_8[0x18]; 8130 8131 u8 syndrome[0x20]; 8132 8133 u8 reserved_at_40[0x20]; 8134 }; 8135 8136 struct mlx5_ifc_enable_hca_in_bits { 8137 u8 opcode[0x10]; 8138 u8 reserved_at_10[0x10]; 8139 8140 u8 reserved_at_20[0x10]; 8141 u8 op_mod[0x10]; 8142 8143 u8 embedded_cpu_function[0x1]; 8144 u8 reserved_at_41[0xf]; 8145 u8 function_id[0x10]; 8146 8147 u8 reserved_at_60[0x20]; 8148 }; 8149 8150 struct mlx5_ifc_drain_dct_out_bits { 8151 u8 status[0x8]; 8152 u8 reserved_at_8[0x18]; 8153 8154 u8 syndrome[0x20]; 8155 8156 u8 reserved_at_40[0x40]; 8157 }; 8158 8159 struct mlx5_ifc_drain_dct_in_bits { 8160 u8 opcode[0x10]; 8161 u8 uid[0x10]; 8162 8163 u8 reserved_at_20[0x10]; 8164 u8 op_mod[0x10]; 8165 8166 u8 reserved_at_40[0x8]; 8167 u8 dctn[0x18]; 8168 8169 u8 reserved_at_60[0x20]; 8170 }; 8171 8172 struct mlx5_ifc_disable_hca_out_bits { 8173 u8 status[0x8]; 8174 u8 reserved_at_8[0x18]; 8175 8176 u8 syndrome[0x20]; 8177 8178 u8 reserved_at_40[0x20]; 8179 }; 8180 8181 struct mlx5_ifc_disable_hca_in_bits { 8182 u8 opcode[0x10]; 8183 u8 reserved_at_10[0x10]; 8184 8185 u8 reserved_at_20[0x10]; 8186 u8 op_mod[0x10]; 8187 8188 u8 embedded_cpu_function[0x1]; 8189 u8 reserved_at_41[0xf]; 8190 u8 function_id[0x10]; 8191 8192 u8 reserved_at_60[0x20]; 8193 }; 8194 8195 struct mlx5_ifc_detach_from_mcg_out_bits { 8196 u8 status[0x8]; 8197 u8 reserved_at_8[0x18]; 8198 8199 u8 syndrome[0x20]; 8200 8201 u8 reserved_at_40[0x40]; 8202 }; 8203 8204 struct mlx5_ifc_detach_from_mcg_in_bits { 8205 u8 opcode[0x10]; 8206 u8 uid[0x10]; 8207 8208 u8 reserved_at_20[0x10]; 8209 u8 op_mod[0x10]; 8210 8211 u8 reserved_at_40[0x8]; 8212 u8 qpn[0x18]; 8213 8214 u8 reserved_at_60[0x20]; 8215 8216 u8 multicast_gid[16][0x8]; 8217 }; 8218 8219 struct mlx5_ifc_destroy_xrq_out_bits { 8220 u8 status[0x8]; 8221 u8 reserved_at_8[0x18]; 8222 8223 u8 syndrome[0x20]; 8224 8225 u8 reserved_at_40[0x40]; 8226 }; 8227 8228 struct mlx5_ifc_destroy_xrq_in_bits { 8229 u8 opcode[0x10]; 8230 u8 uid[0x10]; 8231 8232 u8 reserved_at_20[0x10]; 8233 u8 op_mod[0x10]; 8234 8235 u8 reserved_at_40[0x8]; 8236 u8 xrqn[0x18]; 8237 8238 u8 reserved_at_60[0x20]; 8239 }; 8240 8241 struct mlx5_ifc_destroy_xrc_srq_out_bits { 8242 u8 status[0x8]; 8243 u8 reserved_at_8[0x18]; 8244 8245 u8 syndrome[0x20]; 8246 8247 u8 reserved_at_40[0x40]; 8248 }; 8249 8250 struct mlx5_ifc_destroy_xrc_srq_in_bits { 8251 u8 opcode[0x10]; 8252 u8 uid[0x10]; 8253 8254 u8 reserved_at_20[0x10]; 8255 u8 op_mod[0x10]; 8256 8257 u8 reserved_at_40[0x8]; 8258 u8 xrc_srqn[0x18]; 8259 8260 u8 reserved_at_60[0x20]; 8261 }; 8262 8263 struct mlx5_ifc_destroy_tis_out_bits { 8264 u8 status[0x8]; 8265 u8 reserved_at_8[0x18]; 8266 8267 u8 syndrome[0x20]; 8268 8269 u8 reserved_at_40[0x40]; 8270 }; 8271 8272 struct mlx5_ifc_destroy_tis_in_bits { 8273 u8 opcode[0x10]; 8274 u8 uid[0x10]; 8275 8276 u8 reserved_at_20[0x10]; 8277 u8 op_mod[0x10]; 8278 8279 u8 reserved_at_40[0x8]; 8280 u8 tisn[0x18]; 8281 8282 u8 reserved_at_60[0x20]; 8283 }; 8284 8285 struct mlx5_ifc_destroy_tir_out_bits { 8286 u8 status[0x8]; 8287 u8 reserved_at_8[0x18]; 8288 8289 u8 syndrome[0x20]; 8290 8291 u8 reserved_at_40[0x40]; 8292 }; 8293 8294 struct mlx5_ifc_destroy_tir_in_bits { 8295 u8 opcode[0x10]; 8296 u8 uid[0x10]; 8297 8298 u8 reserved_at_20[0x10]; 8299 u8 op_mod[0x10]; 8300 8301 u8 reserved_at_40[0x8]; 8302 u8 tirn[0x18]; 8303 8304 u8 reserved_at_60[0x20]; 8305 }; 8306 8307 struct mlx5_ifc_destroy_srq_out_bits { 8308 u8 status[0x8]; 8309 u8 reserved_at_8[0x18]; 8310 8311 u8 syndrome[0x20]; 8312 8313 u8 reserved_at_40[0x40]; 8314 }; 8315 8316 struct mlx5_ifc_destroy_srq_in_bits { 8317 u8 opcode[0x10]; 8318 u8 uid[0x10]; 8319 8320 u8 reserved_at_20[0x10]; 8321 u8 op_mod[0x10]; 8322 8323 u8 reserved_at_40[0x8]; 8324 u8 srqn[0x18]; 8325 8326 u8 reserved_at_60[0x20]; 8327 }; 8328 8329 struct mlx5_ifc_destroy_sq_out_bits { 8330 u8 status[0x8]; 8331 u8 reserved_at_8[0x18]; 8332 8333 u8 syndrome[0x20]; 8334 8335 u8 reserved_at_40[0x40]; 8336 }; 8337 8338 struct mlx5_ifc_destroy_sq_in_bits { 8339 u8 opcode[0x10]; 8340 u8 uid[0x10]; 8341 8342 u8 reserved_at_20[0x10]; 8343 u8 op_mod[0x10]; 8344 8345 u8 reserved_at_40[0x8]; 8346 u8 sqn[0x18]; 8347 8348 u8 reserved_at_60[0x20]; 8349 }; 8350 8351 struct mlx5_ifc_destroy_scheduling_element_out_bits { 8352 u8 status[0x8]; 8353 u8 reserved_at_8[0x18]; 8354 8355 u8 syndrome[0x20]; 8356 8357 u8 reserved_at_40[0x1c0]; 8358 }; 8359 8360 struct mlx5_ifc_destroy_scheduling_element_in_bits { 8361 u8 opcode[0x10]; 8362 u8 reserved_at_10[0x10]; 8363 8364 u8 reserved_at_20[0x10]; 8365 u8 op_mod[0x10]; 8366 8367 u8 scheduling_hierarchy[0x8]; 8368 u8 reserved_at_48[0x18]; 8369 8370 u8 scheduling_element_id[0x20]; 8371 8372 u8 reserved_at_80[0x180]; 8373 }; 8374 8375 struct mlx5_ifc_destroy_rqt_out_bits { 8376 u8 status[0x8]; 8377 u8 reserved_at_8[0x18]; 8378 8379 u8 syndrome[0x20]; 8380 8381 u8 reserved_at_40[0x40]; 8382 }; 8383 8384 struct mlx5_ifc_destroy_rqt_in_bits { 8385 u8 opcode[0x10]; 8386 u8 uid[0x10]; 8387 8388 u8 reserved_at_20[0x10]; 8389 u8 op_mod[0x10]; 8390 8391 u8 reserved_at_40[0x8]; 8392 u8 rqtn[0x18]; 8393 8394 u8 reserved_at_60[0x20]; 8395 }; 8396 8397 struct mlx5_ifc_destroy_rq_out_bits { 8398 u8 status[0x8]; 8399 u8 reserved_at_8[0x18]; 8400 8401 u8 syndrome[0x20]; 8402 8403 u8 reserved_at_40[0x40]; 8404 }; 8405 8406 struct mlx5_ifc_destroy_rq_in_bits { 8407 u8 opcode[0x10]; 8408 u8 uid[0x10]; 8409 8410 u8 reserved_at_20[0x10]; 8411 u8 op_mod[0x10]; 8412 8413 u8 reserved_at_40[0x8]; 8414 u8 rqn[0x18]; 8415 8416 u8 reserved_at_60[0x20]; 8417 }; 8418 8419 struct mlx5_ifc_set_delay_drop_params_in_bits { 8420 u8 opcode[0x10]; 8421 u8 reserved_at_10[0x10]; 8422 8423 u8 reserved_at_20[0x10]; 8424 u8 op_mod[0x10]; 8425 8426 u8 reserved_at_40[0x20]; 8427 8428 u8 reserved_at_60[0x10]; 8429 u8 delay_drop_timeout[0x10]; 8430 }; 8431 8432 struct mlx5_ifc_set_delay_drop_params_out_bits { 8433 u8 status[0x8]; 8434 u8 reserved_at_8[0x18]; 8435 8436 u8 syndrome[0x20]; 8437 8438 u8 reserved_at_40[0x40]; 8439 }; 8440 8441 struct mlx5_ifc_destroy_rmp_out_bits { 8442 u8 status[0x8]; 8443 u8 reserved_at_8[0x18]; 8444 8445 u8 syndrome[0x20]; 8446 8447 u8 reserved_at_40[0x40]; 8448 }; 8449 8450 struct mlx5_ifc_destroy_rmp_in_bits { 8451 u8 opcode[0x10]; 8452 u8 uid[0x10]; 8453 8454 u8 reserved_at_20[0x10]; 8455 u8 op_mod[0x10]; 8456 8457 u8 reserved_at_40[0x8]; 8458 u8 rmpn[0x18]; 8459 8460 u8 reserved_at_60[0x20]; 8461 }; 8462 8463 struct mlx5_ifc_destroy_qp_out_bits { 8464 u8 status[0x8]; 8465 u8 reserved_at_8[0x18]; 8466 8467 u8 syndrome[0x20]; 8468 8469 u8 reserved_at_40[0x40]; 8470 }; 8471 8472 struct mlx5_ifc_destroy_qp_in_bits { 8473 u8 opcode[0x10]; 8474 u8 uid[0x10]; 8475 8476 u8 reserved_at_20[0x10]; 8477 u8 op_mod[0x10]; 8478 8479 u8 reserved_at_40[0x8]; 8480 u8 qpn[0x18]; 8481 8482 u8 reserved_at_60[0x20]; 8483 }; 8484 8485 struct mlx5_ifc_destroy_psv_out_bits { 8486 u8 status[0x8]; 8487 u8 reserved_at_8[0x18]; 8488 8489 u8 syndrome[0x20]; 8490 8491 u8 reserved_at_40[0x40]; 8492 }; 8493 8494 struct mlx5_ifc_destroy_psv_in_bits { 8495 u8 opcode[0x10]; 8496 u8 reserved_at_10[0x10]; 8497 8498 u8 reserved_at_20[0x10]; 8499 u8 op_mod[0x10]; 8500 8501 u8 reserved_at_40[0x8]; 8502 u8 psvn[0x18]; 8503 8504 u8 reserved_at_60[0x20]; 8505 }; 8506 8507 struct mlx5_ifc_destroy_mkey_out_bits { 8508 u8 status[0x8]; 8509 u8 reserved_at_8[0x18]; 8510 8511 u8 syndrome[0x20]; 8512 8513 u8 reserved_at_40[0x40]; 8514 }; 8515 8516 struct mlx5_ifc_destroy_mkey_in_bits { 8517 u8 opcode[0x10]; 8518 u8 uid[0x10]; 8519 8520 u8 reserved_at_20[0x10]; 8521 u8 op_mod[0x10]; 8522 8523 u8 reserved_at_40[0x8]; 8524 u8 mkey_index[0x18]; 8525 8526 u8 reserved_at_60[0x20]; 8527 }; 8528 8529 struct mlx5_ifc_destroy_flow_table_out_bits { 8530 u8 status[0x8]; 8531 u8 reserved_at_8[0x18]; 8532 8533 u8 syndrome[0x20]; 8534 8535 u8 reserved_at_40[0x40]; 8536 }; 8537 8538 struct mlx5_ifc_destroy_flow_table_in_bits { 8539 u8 opcode[0x10]; 8540 u8 reserved_at_10[0x10]; 8541 8542 u8 reserved_at_20[0x10]; 8543 u8 op_mod[0x10]; 8544 8545 u8 other_vport[0x1]; 8546 u8 reserved_at_41[0xf]; 8547 u8 vport_number[0x10]; 8548 8549 u8 reserved_at_60[0x20]; 8550 8551 u8 table_type[0x8]; 8552 u8 reserved_at_88[0x18]; 8553 8554 u8 reserved_at_a0[0x8]; 8555 u8 table_id[0x18]; 8556 8557 u8 reserved_at_c0[0x140]; 8558 }; 8559 8560 struct mlx5_ifc_destroy_flow_group_out_bits { 8561 u8 status[0x8]; 8562 u8 reserved_at_8[0x18]; 8563 8564 u8 syndrome[0x20]; 8565 8566 u8 reserved_at_40[0x40]; 8567 }; 8568 8569 struct mlx5_ifc_destroy_flow_group_in_bits { 8570 u8 opcode[0x10]; 8571 u8 reserved_at_10[0x10]; 8572 8573 u8 reserved_at_20[0x10]; 8574 u8 op_mod[0x10]; 8575 8576 u8 other_vport[0x1]; 8577 u8 reserved_at_41[0xf]; 8578 u8 vport_number[0x10]; 8579 8580 u8 reserved_at_60[0x20]; 8581 8582 u8 table_type[0x8]; 8583 u8 reserved_at_88[0x18]; 8584 8585 u8 reserved_at_a0[0x8]; 8586 u8 table_id[0x18]; 8587 8588 u8 group_id[0x20]; 8589 8590 u8 reserved_at_e0[0x120]; 8591 }; 8592 8593 struct mlx5_ifc_destroy_eq_out_bits { 8594 u8 status[0x8]; 8595 u8 reserved_at_8[0x18]; 8596 8597 u8 syndrome[0x20]; 8598 8599 u8 reserved_at_40[0x40]; 8600 }; 8601 8602 struct mlx5_ifc_destroy_eq_in_bits { 8603 u8 opcode[0x10]; 8604 u8 reserved_at_10[0x10]; 8605 8606 u8 reserved_at_20[0x10]; 8607 u8 op_mod[0x10]; 8608 8609 u8 reserved_at_40[0x18]; 8610 u8 eq_number[0x8]; 8611 8612 u8 reserved_at_60[0x20]; 8613 }; 8614 8615 struct mlx5_ifc_destroy_dct_out_bits { 8616 u8 status[0x8]; 8617 u8 reserved_at_8[0x18]; 8618 8619 u8 syndrome[0x20]; 8620 8621 u8 reserved_at_40[0x40]; 8622 }; 8623 8624 struct mlx5_ifc_destroy_dct_in_bits { 8625 u8 opcode[0x10]; 8626 u8 uid[0x10]; 8627 8628 u8 reserved_at_20[0x10]; 8629 u8 op_mod[0x10]; 8630 8631 u8 reserved_at_40[0x8]; 8632 u8 dctn[0x18]; 8633 8634 u8 reserved_at_60[0x20]; 8635 }; 8636 8637 struct mlx5_ifc_destroy_cq_out_bits { 8638 u8 status[0x8]; 8639 u8 reserved_at_8[0x18]; 8640 8641 u8 syndrome[0x20]; 8642 8643 u8 reserved_at_40[0x40]; 8644 }; 8645 8646 struct mlx5_ifc_destroy_cq_in_bits { 8647 u8 opcode[0x10]; 8648 u8 uid[0x10]; 8649 8650 u8 reserved_at_20[0x10]; 8651 u8 op_mod[0x10]; 8652 8653 u8 reserved_at_40[0x8]; 8654 u8 cqn[0x18]; 8655 8656 u8 reserved_at_60[0x20]; 8657 }; 8658 8659 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits { 8660 u8 status[0x8]; 8661 u8 reserved_at_8[0x18]; 8662 8663 u8 syndrome[0x20]; 8664 8665 u8 reserved_at_40[0x40]; 8666 }; 8667 8668 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits { 8669 u8 opcode[0x10]; 8670 u8 reserved_at_10[0x10]; 8671 8672 u8 reserved_at_20[0x10]; 8673 u8 op_mod[0x10]; 8674 8675 u8 reserved_at_40[0x20]; 8676 8677 u8 reserved_at_60[0x10]; 8678 u8 vxlan_udp_port[0x10]; 8679 }; 8680 8681 struct mlx5_ifc_delete_l2_table_entry_out_bits { 8682 u8 status[0x8]; 8683 u8 reserved_at_8[0x18]; 8684 8685 u8 syndrome[0x20]; 8686 8687 u8 reserved_at_40[0x40]; 8688 }; 8689 8690 struct mlx5_ifc_delete_l2_table_entry_in_bits { 8691 u8 opcode[0x10]; 8692 u8 reserved_at_10[0x10]; 8693 8694 u8 reserved_at_20[0x10]; 8695 u8 op_mod[0x10]; 8696 8697 u8 reserved_at_40[0x60]; 8698 8699 u8 reserved_at_a0[0x8]; 8700 u8 table_index[0x18]; 8701 8702 u8 reserved_at_c0[0x140]; 8703 }; 8704 8705 struct mlx5_ifc_delete_fte_out_bits { 8706 u8 status[0x8]; 8707 u8 reserved_at_8[0x18]; 8708 8709 u8 syndrome[0x20]; 8710 8711 u8 reserved_at_40[0x40]; 8712 }; 8713 8714 struct mlx5_ifc_delete_fte_in_bits { 8715 u8 opcode[0x10]; 8716 u8 reserved_at_10[0x10]; 8717 8718 u8 reserved_at_20[0x10]; 8719 u8 op_mod[0x10]; 8720 8721 u8 other_vport[0x1]; 8722 u8 reserved_at_41[0xf]; 8723 u8 vport_number[0x10]; 8724 8725 u8 reserved_at_60[0x20]; 8726 8727 u8 table_type[0x8]; 8728 u8 reserved_at_88[0x18]; 8729 8730 u8 reserved_at_a0[0x8]; 8731 u8 table_id[0x18]; 8732 8733 u8 reserved_at_c0[0x40]; 8734 8735 u8 flow_index[0x20]; 8736 8737 u8 reserved_at_120[0xe0]; 8738 }; 8739 8740 struct mlx5_ifc_dealloc_xrcd_out_bits { 8741 u8 status[0x8]; 8742 u8 reserved_at_8[0x18]; 8743 8744 u8 syndrome[0x20]; 8745 8746 u8 reserved_at_40[0x40]; 8747 }; 8748 8749 struct mlx5_ifc_dealloc_xrcd_in_bits { 8750 u8 opcode[0x10]; 8751 u8 uid[0x10]; 8752 8753 u8 reserved_at_20[0x10]; 8754 u8 op_mod[0x10]; 8755 8756 u8 reserved_at_40[0x8]; 8757 u8 xrcd[0x18]; 8758 8759 u8 reserved_at_60[0x20]; 8760 }; 8761 8762 struct mlx5_ifc_dealloc_uar_out_bits { 8763 u8 status[0x8]; 8764 u8 reserved_at_8[0x18]; 8765 8766 u8 syndrome[0x20]; 8767 8768 u8 reserved_at_40[0x40]; 8769 }; 8770 8771 struct mlx5_ifc_dealloc_uar_in_bits { 8772 u8 opcode[0x10]; 8773 u8 uid[0x10]; 8774 8775 u8 reserved_at_20[0x10]; 8776 u8 op_mod[0x10]; 8777 8778 u8 reserved_at_40[0x8]; 8779 u8 uar[0x18]; 8780 8781 u8 reserved_at_60[0x20]; 8782 }; 8783 8784 struct mlx5_ifc_dealloc_transport_domain_out_bits { 8785 u8 status[0x8]; 8786 u8 reserved_at_8[0x18]; 8787 8788 u8 syndrome[0x20]; 8789 8790 u8 reserved_at_40[0x40]; 8791 }; 8792 8793 struct mlx5_ifc_dealloc_transport_domain_in_bits { 8794 u8 opcode[0x10]; 8795 u8 uid[0x10]; 8796 8797 u8 reserved_at_20[0x10]; 8798 u8 op_mod[0x10]; 8799 8800 u8 reserved_at_40[0x8]; 8801 u8 transport_domain[0x18]; 8802 8803 u8 reserved_at_60[0x20]; 8804 }; 8805 8806 struct mlx5_ifc_dealloc_q_counter_out_bits { 8807 u8 status[0x8]; 8808 u8 reserved_at_8[0x18]; 8809 8810 u8 syndrome[0x20]; 8811 8812 u8 reserved_at_40[0x40]; 8813 }; 8814 8815 struct mlx5_ifc_dealloc_q_counter_in_bits { 8816 u8 opcode[0x10]; 8817 u8 reserved_at_10[0x10]; 8818 8819 u8 reserved_at_20[0x10]; 8820 u8 op_mod[0x10]; 8821 8822 u8 reserved_at_40[0x18]; 8823 u8 counter_set_id[0x8]; 8824 8825 u8 reserved_at_60[0x20]; 8826 }; 8827 8828 struct mlx5_ifc_dealloc_pd_out_bits { 8829 u8 status[0x8]; 8830 u8 reserved_at_8[0x18]; 8831 8832 u8 syndrome[0x20]; 8833 8834 u8 reserved_at_40[0x40]; 8835 }; 8836 8837 struct mlx5_ifc_dealloc_pd_in_bits { 8838 u8 opcode[0x10]; 8839 u8 uid[0x10]; 8840 8841 u8 reserved_at_20[0x10]; 8842 u8 op_mod[0x10]; 8843 8844 u8 reserved_at_40[0x8]; 8845 u8 pd[0x18]; 8846 8847 u8 reserved_at_60[0x20]; 8848 }; 8849 8850 struct mlx5_ifc_dealloc_flow_counter_out_bits { 8851 u8 status[0x8]; 8852 u8 reserved_at_8[0x18]; 8853 8854 u8 syndrome[0x20]; 8855 8856 u8 reserved_at_40[0x40]; 8857 }; 8858 8859 struct mlx5_ifc_dealloc_flow_counter_in_bits { 8860 u8 opcode[0x10]; 8861 u8 reserved_at_10[0x10]; 8862 8863 u8 reserved_at_20[0x10]; 8864 u8 op_mod[0x10]; 8865 8866 u8 flow_counter_id[0x20]; 8867 8868 u8 reserved_at_60[0x20]; 8869 }; 8870 8871 struct mlx5_ifc_create_xrq_out_bits { 8872 u8 status[0x8]; 8873 u8 reserved_at_8[0x18]; 8874 8875 u8 syndrome[0x20]; 8876 8877 u8 reserved_at_40[0x8]; 8878 u8 xrqn[0x18]; 8879 8880 u8 reserved_at_60[0x20]; 8881 }; 8882 8883 struct mlx5_ifc_create_xrq_in_bits { 8884 u8 opcode[0x10]; 8885 u8 uid[0x10]; 8886 8887 u8 reserved_at_20[0x10]; 8888 u8 op_mod[0x10]; 8889 8890 u8 reserved_at_40[0x40]; 8891 8892 struct mlx5_ifc_xrqc_bits xrq_context; 8893 }; 8894 8895 struct mlx5_ifc_create_xrc_srq_out_bits { 8896 u8 status[0x8]; 8897 u8 reserved_at_8[0x18]; 8898 8899 u8 syndrome[0x20]; 8900 8901 u8 reserved_at_40[0x8]; 8902 u8 xrc_srqn[0x18]; 8903 8904 u8 reserved_at_60[0x20]; 8905 }; 8906 8907 struct mlx5_ifc_create_xrc_srq_in_bits { 8908 u8 opcode[0x10]; 8909 u8 uid[0x10]; 8910 8911 u8 reserved_at_20[0x10]; 8912 u8 op_mod[0x10]; 8913 8914 u8 reserved_at_40[0x40]; 8915 8916 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 8917 8918 u8 reserved_at_280[0x60]; 8919 8920 u8 xrc_srq_umem_valid[0x1]; 8921 u8 reserved_at_2e1[0x1f]; 8922 8923 u8 reserved_at_300[0x580]; 8924 8925 u8 pas[][0x40]; 8926 }; 8927 8928 struct mlx5_ifc_create_tis_out_bits { 8929 u8 status[0x8]; 8930 u8 reserved_at_8[0x18]; 8931 8932 u8 syndrome[0x20]; 8933 8934 u8 reserved_at_40[0x8]; 8935 u8 tisn[0x18]; 8936 8937 u8 reserved_at_60[0x20]; 8938 }; 8939 8940 struct mlx5_ifc_create_tis_in_bits { 8941 u8 opcode[0x10]; 8942 u8 uid[0x10]; 8943 8944 u8 reserved_at_20[0x10]; 8945 u8 op_mod[0x10]; 8946 8947 u8 reserved_at_40[0xc0]; 8948 8949 struct mlx5_ifc_tisc_bits ctx; 8950 }; 8951 8952 struct mlx5_ifc_create_tir_out_bits { 8953 u8 status[0x8]; 8954 u8 icm_address_63_40[0x18]; 8955 8956 u8 syndrome[0x20]; 8957 8958 u8 icm_address_39_32[0x8]; 8959 u8 tirn[0x18]; 8960 8961 u8 icm_address_31_0[0x20]; 8962 }; 8963 8964 struct mlx5_ifc_create_tir_in_bits { 8965 u8 opcode[0x10]; 8966 u8 uid[0x10]; 8967 8968 u8 reserved_at_20[0x10]; 8969 u8 op_mod[0x10]; 8970 8971 u8 reserved_at_40[0xc0]; 8972 8973 struct mlx5_ifc_tirc_bits ctx; 8974 }; 8975 8976 struct mlx5_ifc_create_srq_out_bits { 8977 u8 status[0x8]; 8978 u8 reserved_at_8[0x18]; 8979 8980 u8 syndrome[0x20]; 8981 8982 u8 reserved_at_40[0x8]; 8983 u8 srqn[0x18]; 8984 8985 u8 reserved_at_60[0x20]; 8986 }; 8987 8988 struct mlx5_ifc_create_srq_in_bits { 8989 u8 opcode[0x10]; 8990 u8 uid[0x10]; 8991 8992 u8 reserved_at_20[0x10]; 8993 u8 op_mod[0x10]; 8994 8995 u8 reserved_at_40[0x40]; 8996 8997 struct mlx5_ifc_srqc_bits srq_context_entry; 8998 8999 u8 reserved_at_280[0x600]; 9000 9001 u8 pas[][0x40]; 9002 }; 9003 9004 struct mlx5_ifc_create_sq_out_bits { 9005 u8 status[0x8]; 9006 u8 reserved_at_8[0x18]; 9007 9008 u8 syndrome[0x20]; 9009 9010 u8 reserved_at_40[0x8]; 9011 u8 sqn[0x18]; 9012 9013 u8 reserved_at_60[0x20]; 9014 }; 9015 9016 struct mlx5_ifc_create_sq_in_bits { 9017 u8 opcode[0x10]; 9018 u8 uid[0x10]; 9019 9020 u8 reserved_at_20[0x10]; 9021 u8 op_mod[0x10]; 9022 9023 u8 reserved_at_40[0xc0]; 9024 9025 struct mlx5_ifc_sqc_bits ctx; 9026 }; 9027 9028 struct mlx5_ifc_create_scheduling_element_out_bits { 9029 u8 status[0x8]; 9030 u8 reserved_at_8[0x18]; 9031 9032 u8 syndrome[0x20]; 9033 9034 u8 reserved_at_40[0x40]; 9035 9036 u8 scheduling_element_id[0x20]; 9037 9038 u8 reserved_at_a0[0x160]; 9039 }; 9040 9041 struct mlx5_ifc_create_scheduling_element_in_bits { 9042 u8 opcode[0x10]; 9043 u8 reserved_at_10[0x10]; 9044 9045 u8 reserved_at_20[0x10]; 9046 u8 op_mod[0x10]; 9047 9048 u8 scheduling_hierarchy[0x8]; 9049 u8 reserved_at_48[0x18]; 9050 9051 u8 reserved_at_60[0xa0]; 9052 9053 struct mlx5_ifc_scheduling_context_bits scheduling_context; 9054 9055 u8 reserved_at_300[0x100]; 9056 }; 9057 9058 struct mlx5_ifc_create_rqt_out_bits { 9059 u8 status[0x8]; 9060 u8 reserved_at_8[0x18]; 9061 9062 u8 syndrome[0x20]; 9063 9064 u8 reserved_at_40[0x8]; 9065 u8 rqtn[0x18]; 9066 9067 u8 reserved_at_60[0x20]; 9068 }; 9069 9070 struct mlx5_ifc_create_rqt_in_bits { 9071 u8 opcode[0x10]; 9072 u8 uid[0x10]; 9073 9074 u8 reserved_at_20[0x10]; 9075 u8 op_mod[0x10]; 9076 9077 u8 reserved_at_40[0xc0]; 9078 9079 struct mlx5_ifc_rqtc_bits rqt_context; 9080 }; 9081 9082 struct mlx5_ifc_create_rq_out_bits { 9083 u8 status[0x8]; 9084 u8 reserved_at_8[0x18]; 9085 9086 u8 syndrome[0x20]; 9087 9088 u8 reserved_at_40[0x8]; 9089 u8 rqn[0x18]; 9090 9091 u8 reserved_at_60[0x20]; 9092 }; 9093 9094 struct mlx5_ifc_create_rq_in_bits { 9095 u8 opcode[0x10]; 9096 u8 uid[0x10]; 9097 9098 u8 reserved_at_20[0x10]; 9099 u8 op_mod[0x10]; 9100 9101 u8 reserved_at_40[0xc0]; 9102 9103 struct mlx5_ifc_rqc_bits ctx; 9104 }; 9105 9106 struct mlx5_ifc_create_rmp_out_bits { 9107 u8 status[0x8]; 9108 u8 reserved_at_8[0x18]; 9109 9110 u8 syndrome[0x20]; 9111 9112 u8 reserved_at_40[0x8]; 9113 u8 rmpn[0x18]; 9114 9115 u8 reserved_at_60[0x20]; 9116 }; 9117 9118 struct mlx5_ifc_create_rmp_in_bits { 9119 u8 opcode[0x10]; 9120 u8 uid[0x10]; 9121 9122 u8 reserved_at_20[0x10]; 9123 u8 op_mod[0x10]; 9124 9125 u8 reserved_at_40[0xc0]; 9126 9127 struct mlx5_ifc_rmpc_bits ctx; 9128 }; 9129 9130 struct mlx5_ifc_create_qp_out_bits { 9131 u8 status[0x8]; 9132 u8 reserved_at_8[0x18]; 9133 9134 u8 syndrome[0x20]; 9135 9136 u8 reserved_at_40[0x8]; 9137 u8 qpn[0x18]; 9138 9139 u8 ece[0x20]; 9140 }; 9141 9142 struct mlx5_ifc_create_qp_in_bits { 9143 u8 opcode[0x10]; 9144 u8 uid[0x10]; 9145 9146 u8 reserved_at_20[0x10]; 9147 u8 op_mod[0x10]; 9148 9149 u8 qpc_ext[0x1]; 9150 u8 reserved_at_41[0x7]; 9151 u8 input_qpn[0x18]; 9152 9153 u8 reserved_at_60[0x20]; 9154 u8 opt_param_mask[0x20]; 9155 9156 u8 ece[0x20]; 9157 9158 struct mlx5_ifc_qpc_bits qpc; 9159 9160 u8 wq_umem_offset[0x40]; 9161 9162 u8 wq_umem_id[0x20]; 9163 9164 u8 wq_umem_valid[0x1]; 9165 u8 reserved_at_861[0x1f]; 9166 9167 u8 pas[][0x40]; 9168 }; 9169 9170 struct mlx5_ifc_create_psv_out_bits { 9171 u8 status[0x8]; 9172 u8 reserved_at_8[0x18]; 9173 9174 u8 syndrome[0x20]; 9175 9176 u8 reserved_at_40[0x40]; 9177 9178 u8 reserved_at_80[0x8]; 9179 u8 psv0_index[0x18]; 9180 9181 u8 reserved_at_a0[0x8]; 9182 u8 psv1_index[0x18]; 9183 9184 u8 reserved_at_c0[0x8]; 9185 u8 psv2_index[0x18]; 9186 9187 u8 reserved_at_e0[0x8]; 9188 u8 psv3_index[0x18]; 9189 }; 9190 9191 struct mlx5_ifc_create_psv_in_bits { 9192 u8 opcode[0x10]; 9193 u8 reserved_at_10[0x10]; 9194 9195 u8 reserved_at_20[0x10]; 9196 u8 op_mod[0x10]; 9197 9198 u8 num_psv[0x4]; 9199 u8 reserved_at_44[0x4]; 9200 u8 pd[0x18]; 9201 9202 u8 reserved_at_60[0x20]; 9203 }; 9204 9205 struct mlx5_ifc_create_mkey_out_bits { 9206 u8 status[0x8]; 9207 u8 reserved_at_8[0x18]; 9208 9209 u8 syndrome[0x20]; 9210 9211 u8 reserved_at_40[0x8]; 9212 u8 mkey_index[0x18]; 9213 9214 u8 reserved_at_60[0x20]; 9215 }; 9216 9217 struct mlx5_ifc_create_mkey_in_bits { 9218 u8 opcode[0x10]; 9219 u8 uid[0x10]; 9220 9221 u8 reserved_at_20[0x10]; 9222 u8 op_mod[0x10]; 9223 9224 u8 reserved_at_40[0x20]; 9225 9226 u8 pg_access[0x1]; 9227 u8 mkey_umem_valid[0x1]; 9228 u8 data_direct[0x1]; 9229 u8 reserved_at_63[0x1d]; 9230 9231 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 9232 9233 u8 reserved_at_280[0x80]; 9234 9235 u8 translations_octword_actual_size[0x20]; 9236 9237 u8 reserved_at_320[0x560]; 9238 9239 u8 klm_pas_mtt[][0x20]; 9240 }; 9241 9242 enum { 9243 MLX5_FLOW_TABLE_TYPE_NIC_RX = 0x0, 9244 MLX5_FLOW_TABLE_TYPE_NIC_TX = 0x1, 9245 MLX5_FLOW_TABLE_TYPE_ESW_EGRESS_ACL = 0x2, 9246 MLX5_FLOW_TABLE_TYPE_ESW_INGRESS_ACL = 0x3, 9247 MLX5_FLOW_TABLE_TYPE_FDB = 0X4, 9248 MLX5_FLOW_TABLE_TYPE_SNIFFER_RX = 0X5, 9249 MLX5_FLOW_TABLE_TYPE_SNIFFER_TX = 0X6, 9250 }; 9251 9252 struct mlx5_ifc_create_flow_table_out_bits { 9253 u8 status[0x8]; 9254 u8 icm_address_63_40[0x18]; 9255 9256 u8 syndrome[0x20]; 9257 9258 u8 icm_address_39_32[0x8]; 9259 u8 table_id[0x18]; 9260 9261 u8 icm_address_31_0[0x20]; 9262 }; 9263 9264 struct mlx5_ifc_create_flow_table_in_bits { 9265 u8 opcode[0x10]; 9266 u8 uid[0x10]; 9267 9268 u8 reserved_at_20[0x10]; 9269 u8 op_mod[0x10]; 9270 9271 u8 other_vport[0x1]; 9272 u8 reserved_at_41[0xf]; 9273 u8 vport_number[0x10]; 9274 9275 u8 reserved_at_60[0x20]; 9276 9277 u8 table_type[0x8]; 9278 u8 reserved_at_88[0x18]; 9279 9280 u8 reserved_at_a0[0x20]; 9281 9282 struct mlx5_ifc_flow_table_context_bits flow_table_context; 9283 }; 9284 9285 struct mlx5_ifc_create_flow_group_out_bits { 9286 u8 status[0x8]; 9287 u8 reserved_at_8[0x18]; 9288 9289 u8 syndrome[0x20]; 9290 9291 u8 reserved_at_40[0x8]; 9292 u8 group_id[0x18]; 9293 9294 u8 reserved_at_60[0x20]; 9295 }; 9296 9297 enum { 9298 MLX5_CREATE_FLOW_GROUP_IN_GROUP_TYPE_TCAM_SUBTABLE = 0x0, 9299 MLX5_CREATE_FLOW_GROUP_IN_GROUP_TYPE_HASH_SPLIT = 0x1, 9300 }; 9301 9302 enum { 9303 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 9304 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 9305 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 9306 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3, 9307 }; 9308 9309 struct mlx5_ifc_create_flow_group_in_bits { 9310 u8 opcode[0x10]; 9311 u8 reserved_at_10[0x10]; 9312 9313 u8 reserved_at_20[0x10]; 9314 u8 op_mod[0x10]; 9315 9316 u8 other_vport[0x1]; 9317 u8 reserved_at_41[0xf]; 9318 u8 vport_number[0x10]; 9319 9320 u8 reserved_at_60[0x20]; 9321 9322 u8 table_type[0x8]; 9323 u8 reserved_at_88[0x4]; 9324 u8 group_type[0x4]; 9325 u8 reserved_at_90[0x10]; 9326 9327 u8 reserved_at_a0[0x8]; 9328 u8 table_id[0x18]; 9329 9330 u8 source_eswitch_owner_vhca_id_valid[0x1]; 9331 9332 u8 reserved_at_c1[0x1f]; 9333 9334 u8 start_flow_index[0x20]; 9335 9336 u8 reserved_at_100[0x20]; 9337 9338 u8 end_flow_index[0x20]; 9339 9340 u8 reserved_at_140[0x10]; 9341 u8 match_definer_id[0x10]; 9342 9343 u8 reserved_at_160[0x80]; 9344 9345 u8 reserved_at_1e0[0x18]; 9346 u8 match_criteria_enable[0x8]; 9347 9348 struct mlx5_ifc_fte_match_param_bits match_criteria; 9349 9350 u8 reserved_at_1200[0xe00]; 9351 }; 9352 9353 struct mlx5_ifc_create_eq_out_bits { 9354 u8 status[0x8]; 9355 u8 reserved_at_8[0x18]; 9356 9357 u8 syndrome[0x20]; 9358 9359 u8 reserved_at_40[0x18]; 9360 u8 eq_number[0x8]; 9361 9362 u8 reserved_at_60[0x20]; 9363 }; 9364 9365 struct mlx5_ifc_create_eq_in_bits { 9366 u8 opcode[0x10]; 9367 u8 uid[0x10]; 9368 9369 u8 reserved_at_20[0x10]; 9370 u8 op_mod[0x10]; 9371 9372 u8 reserved_at_40[0x40]; 9373 9374 struct mlx5_ifc_eqc_bits eq_context_entry; 9375 9376 u8 reserved_at_280[0x40]; 9377 9378 u8 event_bitmask[4][0x40]; 9379 9380 u8 reserved_at_3c0[0x4c0]; 9381 9382 u8 pas[][0x40]; 9383 }; 9384 9385 struct mlx5_ifc_create_dct_out_bits { 9386 u8 status[0x8]; 9387 u8 reserved_at_8[0x18]; 9388 9389 u8 syndrome[0x20]; 9390 9391 u8 reserved_at_40[0x8]; 9392 u8 dctn[0x18]; 9393 9394 u8 ece[0x20]; 9395 }; 9396 9397 struct mlx5_ifc_create_dct_in_bits { 9398 u8 opcode[0x10]; 9399 u8 uid[0x10]; 9400 9401 u8 reserved_at_20[0x10]; 9402 u8 op_mod[0x10]; 9403 9404 u8 reserved_at_40[0x40]; 9405 9406 struct mlx5_ifc_dctc_bits dct_context_entry; 9407 9408 u8 reserved_at_280[0x180]; 9409 }; 9410 9411 struct mlx5_ifc_create_cq_out_bits { 9412 u8 status[0x8]; 9413 u8 reserved_at_8[0x18]; 9414 9415 u8 syndrome[0x20]; 9416 9417 u8 reserved_at_40[0x8]; 9418 u8 cqn[0x18]; 9419 9420 u8 reserved_at_60[0x20]; 9421 }; 9422 9423 struct mlx5_ifc_create_cq_in_bits { 9424 u8 opcode[0x10]; 9425 u8 uid[0x10]; 9426 9427 u8 reserved_at_20[0x10]; 9428 u8 op_mod[0x10]; 9429 9430 u8 reserved_at_40[0x40]; 9431 9432 struct mlx5_ifc_cqc_bits cq_context; 9433 9434 u8 reserved_at_280[0x60]; 9435 9436 u8 cq_umem_valid[0x1]; 9437 u8 reserved_at_2e1[0x59f]; 9438 9439 u8 pas[][0x40]; 9440 }; 9441 9442 struct mlx5_ifc_config_int_moderation_out_bits { 9443 u8 status[0x8]; 9444 u8 reserved_at_8[0x18]; 9445 9446 u8 syndrome[0x20]; 9447 9448 u8 reserved_at_40[0x4]; 9449 u8 min_delay[0xc]; 9450 u8 int_vector[0x10]; 9451 9452 u8 reserved_at_60[0x20]; 9453 }; 9454 9455 enum { 9456 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0, 9457 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1, 9458 }; 9459 9460 struct mlx5_ifc_config_int_moderation_in_bits { 9461 u8 opcode[0x10]; 9462 u8 reserved_at_10[0x10]; 9463 9464 u8 reserved_at_20[0x10]; 9465 u8 op_mod[0x10]; 9466 9467 u8 reserved_at_40[0x4]; 9468 u8 min_delay[0xc]; 9469 u8 int_vector[0x10]; 9470 9471 u8 reserved_at_60[0x20]; 9472 }; 9473 9474 struct mlx5_ifc_attach_to_mcg_out_bits { 9475 u8 status[0x8]; 9476 u8 reserved_at_8[0x18]; 9477 9478 u8 syndrome[0x20]; 9479 9480 u8 reserved_at_40[0x40]; 9481 }; 9482 9483 struct mlx5_ifc_attach_to_mcg_in_bits { 9484 u8 opcode[0x10]; 9485 u8 uid[0x10]; 9486 9487 u8 reserved_at_20[0x10]; 9488 u8 op_mod[0x10]; 9489 9490 u8 reserved_at_40[0x8]; 9491 u8 qpn[0x18]; 9492 9493 u8 reserved_at_60[0x20]; 9494 9495 u8 multicast_gid[16][0x8]; 9496 }; 9497 9498 struct mlx5_ifc_arm_xrq_out_bits { 9499 u8 status[0x8]; 9500 u8 reserved_at_8[0x18]; 9501 9502 u8 syndrome[0x20]; 9503 9504 u8 reserved_at_40[0x40]; 9505 }; 9506 9507 struct mlx5_ifc_arm_xrq_in_bits { 9508 u8 opcode[0x10]; 9509 u8 reserved_at_10[0x10]; 9510 9511 u8 reserved_at_20[0x10]; 9512 u8 op_mod[0x10]; 9513 9514 u8 reserved_at_40[0x8]; 9515 u8 xrqn[0x18]; 9516 9517 u8 reserved_at_60[0x10]; 9518 u8 lwm[0x10]; 9519 }; 9520 9521 struct mlx5_ifc_arm_xrc_srq_out_bits { 9522 u8 status[0x8]; 9523 u8 reserved_at_8[0x18]; 9524 9525 u8 syndrome[0x20]; 9526 9527 u8 reserved_at_40[0x40]; 9528 }; 9529 9530 enum { 9531 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1, 9532 }; 9533 9534 struct mlx5_ifc_arm_xrc_srq_in_bits { 9535 u8 opcode[0x10]; 9536 u8 uid[0x10]; 9537 9538 u8 reserved_at_20[0x10]; 9539 u8 op_mod[0x10]; 9540 9541 u8 reserved_at_40[0x8]; 9542 u8 xrc_srqn[0x18]; 9543 9544 u8 reserved_at_60[0x10]; 9545 u8 lwm[0x10]; 9546 }; 9547 9548 struct mlx5_ifc_arm_rq_out_bits { 9549 u8 status[0x8]; 9550 u8 reserved_at_8[0x18]; 9551 9552 u8 syndrome[0x20]; 9553 9554 u8 reserved_at_40[0x40]; 9555 }; 9556 9557 enum { 9558 MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1, 9559 MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2, 9560 }; 9561 9562 struct mlx5_ifc_arm_rq_in_bits { 9563 u8 opcode[0x10]; 9564 u8 uid[0x10]; 9565 9566 u8 reserved_at_20[0x10]; 9567 u8 op_mod[0x10]; 9568 9569 u8 reserved_at_40[0x8]; 9570 u8 srq_number[0x18]; 9571 9572 u8 reserved_at_60[0x10]; 9573 u8 lwm[0x10]; 9574 }; 9575 9576 struct mlx5_ifc_arm_dct_out_bits { 9577 u8 status[0x8]; 9578 u8 reserved_at_8[0x18]; 9579 9580 u8 syndrome[0x20]; 9581 9582 u8 reserved_at_40[0x40]; 9583 }; 9584 9585 struct mlx5_ifc_arm_dct_in_bits { 9586 u8 opcode[0x10]; 9587 u8 reserved_at_10[0x10]; 9588 9589 u8 reserved_at_20[0x10]; 9590 u8 op_mod[0x10]; 9591 9592 u8 reserved_at_40[0x8]; 9593 u8 dct_number[0x18]; 9594 9595 u8 reserved_at_60[0x20]; 9596 }; 9597 9598 struct mlx5_ifc_alloc_xrcd_out_bits { 9599 u8 status[0x8]; 9600 u8 reserved_at_8[0x18]; 9601 9602 u8 syndrome[0x20]; 9603 9604 u8 reserved_at_40[0x8]; 9605 u8 xrcd[0x18]; 9606 9607 u8 reserved_at_60[0x20]; 9608 }; 9609 9610 struct mlx5_ifc_alloc_xrcd_in_bits { 9611 u8 opcode[0x10]; 9612 u8 uid[0x10]; 9613 9614 u8 reserved_at_20[0x10]; 9615 u8 op_mod[0x10]; 9616 9617 u8 reserved_at_40[0x40]; 9618 }; 9619 9620 struct mlx5_ifc_alloc_uar_out_bits { 9621 u8 status[0x8]; 9622 u8 reserved_at_8[0x18]; 9623 9624 u8 syndrome[0x20]; 9625 9626 u8 reserved_at_40[0x8]; 9627 u8 uar[0x18]; 9628 9629 u8 reserved_at_60[0x20]; 9630 }; 9631 9632 struct mlx5_ifc_alloc_uar_in_bits { 9633 u8 opcode[0x10]; 9634 u8 uid[0x10]; 9635 9636 u8 reserved_at_20[0x10]; 9637 u8 op_mod[0x10]; 9638 9639 u8 reserved_at_40[0x40]; 9640 }; 9641 9642 struct mlx5_ifc_alloc_transport_domain_out_bits { 9643 u8 status[0x8]; 9644 u8 reserved_at_8[0x18]; 9645 9646 u8 syndrome[0x20]; 9647 9648 u8 reserved_at_40[0x8]; 9649 u8 transport_domain[0x18]; 9650 9651 u8 reserved_at_60[0x20]; 9652 }; 9653 9654 struct mlx5_ifc_alloc_transport_domain_in_bits { 9655 u8 opcode[0x10]; 9656 u8 uid[0x10]; 9657 9658 u8 reserved_at_20[0x10]; 9659 u8 op_mod[0x10]; 9660 9661 u8 reserved_at_40[0x40]; 9662 }; 9663 9664 struct mlx5_ifc_alloc_q_counter_out_bits { 9665 u8 status[0x8]; 9666 u8 reserved_at_8[0x18]; 9667 9668 u8 syndrome[0x20]; 9669 9670 u8 reserved_at_40[0x18]; 9671 u8 counter_set_id[0x8]; 9672 9673 u8 reserved_at_60[0x20]; 9674 }; 9675 9676 struct mlx5_ifc_alloc_q_counter_in_bits { 9677 u8 opcode[0x10]; 9678 u8 uid[0x10]; 9679 9680 u8 reserved_at_20[0x10]; 9681 u8 op_mod[0x10]; 9682 9683 u8 reserved_at_40[0x40]; 9684 }; 9685 9686 struct mlx5_ifc_alloc_pd_out_bits { 9687 u8 status[0x8]; 9688 u8 reserved_at_8[0x18]; 9689 9690 u8 syndrome[0x20]; 9691 9692 u8 reserved_at_40[0x8]; 9693 u8 pd[0x18]; 9694 9695 u8 reserved_at_60[0x20]; 9696 }; 9697 9698 struct mlx5_ifc_alloc_pd_in_bits { 9699 u8 opcode[0x10]; 9700 u8 uid[0x10]; 9701 9702 u8 reserved_at_20[0x10]; 9703 u8 op_mod[0x10]; 9704 9705 u8 reserved_at_40[0x40]; 9706 }; 9707 9708 struct mlx5_ifc_alloc_flow_counter_out_bits { 9709 u8 status[0x8]; 9710 u8 reserved_at_8[0x18]; 9711 9712 u8 syndrome[0x20]; 9713 9714 u8 flow_counter_id[0x20]; 9715 9716 u8 reserved_at_60[0x20]; 9717 }; 9718 9719 struct mlx5_ifc_alloc_flow_counter_in_bits { 9720 u8 opcode[0x10]; 9721 u8 reserved_at_10[0x10]; 9722 9723 u8 reserved_at_20[0x10]; 9724 u8 op_mod[0x10]; 9725 9726 u8 reserved_at_40[0x33]; 9727 u8 flow_counter_bulk_log_size[0x5]; 9728 u8 flow_counter_bulk[0x8]; 9729 }; 9730 9731 struct mlx5_ifc_add_vxlan_udp_dport_out_bits { 9732 u8 status[0x8]; 9733 u8 reserved_at_8[0x18]; 9734 9735 u8 syndrome[0x20]; 9736 9737 u8 reserved_at_40[0x40]; 9738 }; 9739 9740 struct mlx5_ifc_add_vxlan_udp_dport_in_bits { 9741 u8 opcode[0x10]; 9742 u8 reserved_at_10[0x10]; 9743 9744 u8 reserved_at_20[0x10]; 9745 u8 op_mod[0x10]; 9746 9747 u8 reserved_at_40[0x20]; 9748 9749 u8 reserved_at_60[0x10]; 9750 u8 vxlan_udp_port[0x10]; 9751 }; 9752 9753 struct mlx5_ifc_set_pp_rate_limit_out_bits { 9754 u8 status[0x8]; 9755 u8 reserved_at_8[0x18]; 9756 9757 u8 syndrome[0x20]; 9758 9759 u8 reserved_at_40[0x40]; 9760 }; 9761 9762 struct mlx5_ifc_set_pp_rate_limit_context_bits { 9763 u8 rate_limit[0x20]; 9764 9765 u8 burst_upper_bound[0x20]; 9766 9767 u8 reserved_at_40[0x10]; 9768 u8 typical_packet_size[0x10]; 9769 9770 u8 reserved_at_60[0x120]; 9771 }; 9772 9773 struct mlx5_ifc_set_pp_rate_limit_in_bits { 9774 u8 opcode[0x10]; 9775 u8 uid[0x10]; 9776 9777 u8 reserved_at_20[0x10]; 9778 u8 op_mod[0x10]; 9779 9780 u8 reserved_at_40[0x10]; 9781 u8 rate_limit_index[0x10]; 9782 9783 u8 reserved_at_60[0x20]; 9784 9785 struct mlx5_ifc_set_pp_rate_limit_context_bits ctx; 9786 }; 9787 9788 struct mlx5_ifc_access_register_out_bits { 9789 u8 status[0x8]; 9790 u8 reserved_at_8[0x18]; 9791 9792 u8 syndrome[0x20]; 9793 9794 u8 reserved_at_40[0x40]; 9795 9796 u8 register_data[][0x20]; 9797 }; 9798 9799 enum { 9800 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0, 9801 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1, 9802 }; 9803 9804 struct mlx5_ifc_access_register_in_bits { 9805 u8 opcode[0x10]; 9806 u8 reserved_at_10[0x10]; 9807 9808 u8 reserved_at_20[0x10]; 9809 u8 op_mod[0x10]; 9810 9811 u8 reserved_at_40[0x10]; 9812 u8 register_id[0x10]; 9813 9814 u8 argument[0x20]; 9815 9816 u8 register_data[][0x20]; 9817 }; 9818 9819 struct mlx5_ifc_sltp_reg_bits { 9820 u8 status[0x4]; 9821 u8 version[0x4]; 9822 u8 local_port[0x8]; 9823 u8 pnat[0x2]; 9824 u8 reserved_at_12[0x2]; 9825 u8 lane[0x4]; 9826 u8 reserved_at_18[0x8]; 9827 9828 u8 reserved_at_20[0x20]; 9829 9830 u8 reserved_at_40[0x7]; 9831 u8 polarity[0x1]; 9832 u8 ob_tap0[0x8]; 9833 u8 ob_tap1[0x8]; 9834 u8 ob_tap2[0x8]; 9835 9836 u8 reserved_at_60[0xc]; 9837 u8 ob_preemp_mode[0x4]; 9838 u8 ob_reg[0x8]; 9839 u8 ob_bias[0x8]; 9840 9841 u8 reserved_at_80[0x20]; 9842 }; 9843 9844 struct mlx5_ifc_slrg_reg_bits { 9845 u8 status[0x4]; 9846 u8 version[0x4]; 9847 u8 local_port[0x8]; 9848 u8 pnat[0x2]; 9849 u8 reserved_at_12[0x2]; 9850 u8 lane[0x4]; 9851 u8 reserved_at_18[0x8]; 9852 9853 u8 time_to_link_up[0x10]; 9854 u8 reserved_at_30[0xc]; 9855 u8 grade_lane_speed[0x4]; 9856 9857 u8 grade_version[0x8]; 9858 u8 grade[0x18]; 9859 9860 u8 reserved_at_60[0x4]; 9861 u8 height_grade_type[0x4]; 9862 u8 height_grade[0x18]; 9863 9864 u8 height_dz[0x10]; 9865 u8 height_dv[0x10]; 9866 9867 u8 reserved_at_a0[0x10]; 9868 u8 height_sigma[0x10]; 9869 9870 u8 reserved_at_c0[0x20]; 9871 9872 u8 reserved_at_e0[0x4]; 9873 u8 phase_grade_type[0x4]; 9874 u8 phase_grade[0x18]; 9875 9876 u8 reserved_at_100[0x8]; 9877 u8 phase_eo_pos[0x8]; 9878 u8 reserved_at_110[0x8]; 9879 u8 phase_eo_neg[0x8]; 9880 9881 u8 ffe_set_tested[0x10]; 9882 u8 test_errors_per_lane[0x10]; 9883 }; 9884 9885 struct mlx5_ifc_pvlc_reg_bits { 9886 u8 reserved_at_0[0x8]; 9887 u8 local_port[0x8]; 9888 u8 reserved_at_10[0x10]; 9889 9890 u8 reserved_at_20[0x1c]; 9891 u8 vl_hw_cap[0x4]; 9892 9893 u8 reserved_at_40[0x1c]; 9894 u8 vl_admin[0x4]; 9895 9896 u8 reserved_at_60[0x1c]; 9897 u8 vl_operational[0x4]; 9898 }; 9899 9900 struct mlx5_ifc_pude_reg_bits { 9901 u8 swid[0x8]; 9902 u8 local_port[0x8]; 9903 u8 reserved_at_10[0x4]; 9904 u8 admin_status[0x4]; 9905 u8 reserved_at_18[0x4]; 9906 u8 oper_status[0x4]; 9907 9908 u8 reserved_at_20[0x60]; 9909 }; 9910 9911 struct mlx5_ifc_ptys_reg_bits { 9912 u8 reserved_at_0[0x1]; 9913 u8 an_disable_admin[0x1]; 9914 u8 an_disable_cap[0x1]; 9915 u8 reserved_at_3[0x5]; 9916 u8 local_port[0x8]; 9917 u8 reserved_at_10[0x8]; 9918 u8 plane_ind[0x4]; 9919 u8 reserved_at_1c[0x1]; 9920 u8 proto_mask[0x3]; 9921 9922 u8 an_status[0x4]; 9923 u8 reserved_at_24[0xc]; 9924 u8 data_rate_oper[0x10]; 9925 9926 u8 ext_eth_proto_capability[0x20]; 9927 9928 u8 eth_proto_capability[0x20]; 9929 9930 u8 ib_link_width_capability[0x10]; 9931 u8 ib_proto_capability[0x10]; 9932 9933 u8 ext_eth_proto_admin[0x20]; 9934 9935 u8 eth_proto_admin[0x20]; 9936 9937 u8 ib_link_width_admin[0x10]; 9938 u8 ib_proto_admin[0x10]; 9939 9940 u8 ext_eth_proto_oper[0x20]; 9941 9942 u8 eth_proto_oper[0x20]; 9943 9944 u8 ib_link_width_oper[0x10]; 9945 u8 ib_proto_oper[0x10]; 9946 9947 u8 reserved_at_160[0x1c]; 9948 u8 connector_type[0x4]; 9949 9950 u8 eth_proto_lp_advertise[0x20]; 9951 9952 u8 reserved_at_1a0[0x60]; 9953 }; 9954 9955 struct mlx5_ifc_mlcr_reg_bits { 9956 u8 reserved_at_0[0x8]; 9957 u8 local_port[0x8]; 9958 u8 reserved_at_10[0x20]; 9959 9960 u8 beacon_duration[0x10]; 9961 u8 reserved_at_40[0x10]; 9962 9963 u8 beacon_remain[0x10]; 9964 }; 9965 9966 struct mlx5_ifc_ptas_reg_bits { 9967 u8 reserved_at_0[0x20]; 9968 9969 u8 algorithm_options[0x10]; 9970 u8 reserved_at_30[0x4]; 9971 u8 repetitions_mode[0x4]; 9972 u8 num_of_repetitions[0x8]; 9973 9974 u8 grade_version[0x8]; 9975 u8 height_grade_type[0x4]; 9976 u8 phase_grade_type[0x4]; 9977 u8 height_grade_weight[0x8]; 9978 u8 phase_grade_weight[0x8]; 9979 9980 u8 gisim_measure_bits[0x10]; 9981 u8 adaptive_tap_measure_bits[0x10]; 9982 9983 u8 ber_bath_high_error_threshold[0x10]; 9984 u8 ber_bath_mid_error_threshold[0x10]; 9985 9986 u8 ber_bath_low_error_threshold[0x10]; 9987 u8 one_ratio_high_threshold[0x10]; 9988 9989 u8 one_ratio_high_mid_threshold[0x10]; 9990 u8 one_ratio_low_mid_threshold[0x10]; 9991 9992 u8 one_ratio_low_threshold[0x10]; 9993 u8 ndeo_error_threshold[0x10]; 9994 9995 u8 mixer_offset_step_size[0x10]; 9996 u8 reserved_at_110[0x8]; 9997 u8 mix90_phase_for_voltage_bath[0x8]; 9998 9999 u8 mixer_offset_start[0x10]; 10000 u8 mixer_offset_end[0x10]; 10001 10002 u8 reserved_at_140[0x15]; 10003 u8 ber_test_time[0xb]; 10004 }; 10005 10006 struct mlx5_ifc_pspa_reg_bits { 10007 u8 swid[0x8]; 10008 u8 local_port[0x8]; 10009 u8 sub_port[0x8]; 10010 u8 reserved_at_18[0x8]; 10011 10012 u8 reserved_at_20[0x20]; 10013 }; 10014 10015 struct mlx5_ifc_pqdr_reg_bits { 10016 u8 reserved_at_0[0x8]; 10017 u8 local_port[0x8]; 10018 u8 reserved_at_10[0x5]; 10019 u8 prio[0x3]; 10020 u8 reserved_at_18[0x6]; 10021 u8 mode[0x2]; 10022 10023 u8 reserved_at_20[0x20]; 10024 10025 u8 reserved_at_40[0x10]; 10026 u8 min_threshold[0x10]; 10027 10028 u8 reserved_at_60[0x10]; 10029 u8 max_threshold[0x10]; 10030 10031 u8 reserved_at_80[0x10]; 10032 u8 mark_probability_denominator[0x10]; 10033 10034 u8 reserved_at_a0[0x60]; 10035 }; 10036 10037 struct mlx5_ifc_ppsc_reg_bits { 10038 u8 reserved_at_0[0x8]; 10039 u8 local_port[0x8]; 10040 u8 reserved_at_10[0x10]; 10041 10042 u8 reserved_at_20[0x60]; 10043 10044 u8 reserved_at_80[0x1c]; 10045 u8 wrps_admin[0x4]; 10046 10047 u8 reserved_at_a0[0x1c]; 10048 u8 wrps_status[0x4]; 10049 10050 u8 reserved_at_c0[0x8]; 10051 u8 up_threshold[0x8]; 10052 u8 reserved_at_d0[0x8]; 10053 u8 down_threshold[0x8]; 10054 10055 u8 reserved_at_e0[0x20]; 10056 10057 u8 reserved_at_100[0x1c]; 10058 u8 srps_admin[0x4]; 10059 10060 u8 reserved_at_120[0x1c]; 10061 u8 srps_status[0x4]; 10062 10063 u8 reserved_at_140[0x40]; 10064 }; 10065 10066 struct mlx5_ifc_pplr_reg_bits { 10067 u8 reserved_at_0[0x8]; 10068 u8 local_port[0x8]; 10069 u8 reserved_at_10[0x10]; 10070 10071 u8 reserved_at_20[0x8]; 10072 u8 lb_cap[0x8]; 10073 u8 reserved_at_30[0x8]; 10074 u8 lb_en[0x8]; 10075 }; 10076 10077 struct mlx5_ifc_pplm_reg_bits { 10078 u8 reserved_at_0[0x8]; 10079 u8 local_port[0x8]; 10080 u8 reserved_at_10[0x10]; 10081 10082 u8 reserved_at_20[0x20]; 10083 10084 u8 port_profile_mode[0x8]; 10085 u8 static_port_profile[0x8]; 10086 u8 active_port_profile[0x8]; 10087 u8 reserved_at_58[0x8]; 10088 10089 u8 retransmission_active[0x8]; 10090 u8 fec_mode_active[0x18]; 10091 10092 u8 rs_fec_correction_bypass_cap[0x4]; 10093 u8 reserved_at_84[0x8]; 10094 u8 fec_override_cap_56g[0x4]; 10095 u8 fec_override_cap_100g[0x4]; 10096 u8 fec_override_cap_50g[0x4]; 10097 u8 fec_override_cap_25g[0x4]; 10098 u8 fec_override_cap_10g_40g[0x4]; 10099 10100 u8 rs_fec_correction_bypass_admin[0x4]; 10101 u8 reserved_at_a4[0x8]; 10102 u8 fec_override_admin_56g[0x4]; 10103 u8 fec_override_admin_100g[0x4]; 10104 u8 fec_override_admin_50g[0x4]; 10105 u8 fec_override_admin_25g[0x4]; 10106 u8 fec_override_admin_10g_40g[0x4]; 10107 10108 u8 fec_override_cap_400g_8x[0x10]; 10109 u8 fec_override_cap_200g_4x[0x10]; 10110 10111 u8 fec_override_cap_100g_2x[0x10]; 10112 u8 fec_override_cap_50g_1x[0x10]; 10113 10114 u8 fec_override_admin_400g_8x[0x10]; 10115 u8 fec_override_admin_200g_4x[0x10]; 10116 10117 u8 fec_override_admin_100g_2x[0x10]; 10118 u8 fec_override_admin_50g_1x[0x10]; 10119 10120 u8 fec_override_cap_800g_8x[0x10]; 10121 u8 fec_override_cap_400g_4x[0x10]; 10122 10123 u8 fec_override_cap_200g_2x[0x10]; 10124 u8 fec_override_cap_100g_1x[0x10]; 10125 10126 u8 reserved_at_180[0xa0]; 10127 10128 u8 fec_override_admin_800g_8x[0x10]; 10129 u8 fec_override_admin_400g_4x[0x10]; 10130 10131 u8 fec_override_admin_200g_2x[0x10]; 10132 u8 fec_override_admin_100g_1x[0x10]; 10133 10134 u8 reserved_at_260[0x20]; 10135 }; 10136 10137 struct mlx5_ifc_ppcnt_reg_bits { 10138 u8 swid[0x8]; 10139 u8 local_port[0x8]; 10140 u8 pnat[0x2]; 10141 u8 reserved_at_12[0x8]; 10142 u8 grp[0x6]; 10143 10144 u8 clr[0x1]; 10145 u8 reserved_at_21[0x13]; 10146 u8 plane_ind[0x4]; 10147 u8 reserved_at_38[0x3]; 10148 u8 prio_tc[0x5]; 10149 10150 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set; 10151 }; 10152 10153 struct mlx5_ifc_mpein_reg_bits { 10154 u8 reserved_at_0[0x2]; 10155 u8 depth[0x6]; 10156 u8 pcie_index[0x8]; 10157 u8 node[0x8]; 10158 u8 reserved_at_18[0x8]; 10159 10160 u8 capability_mask[0x20]; 10161 10162 u8 reserved_at_40[0x8]; 10163 u8 link_width_enabled[0x8]; 10164 u8 link_speed_enabled[0x10]; 10165 10166 u8 lane0_physical_position[0x8]; 10167 u8 link_width_active[0x8]; 10168 u8 link_speed_active[0x10]; 10169 10170 u8 num_of_pfs[0x10]; 10171 u8 num_of_vfs[0x10]; 10172 10173 u8 bdf0[0x10]; 10174 u8 reserved_at_b0[0x10]; 10175 10176 u8 max_read_request_size[0x4]; 10177 u8 max_payload_size[0x4]; 10178 u8 reserved_at_c8[0x5]; 10179 u8 pwr_status[0x3]; 10180 u8 port_type[0x4]; 10181 u8 reserved_at_d4[0xb]; 10182 u8 lane_reversal[0x1]; 10183 10184 u8 reserved_at_e0[0x14]; 10185 u8 pci_power[0xc]; 10186 10187 u8 reserved_at_100[0x20]; 10188 10189 u8 device_status[0x10]; 10190 u8 port_state[0x8]; 10191 u8 reserved_at_138[0x8]; 10192 10193 u8 reserved_at_140[0x10]; 10194 u8 receiver_detect_result[0x10]; 10195 10196 u8 reserved_at_160[0x20]; 10197 }; 10198 10199 struct mlx5_ifc_mpcnt_reg_bits { 10200 u8 reserved_at_0[0x8]; 10201 u8 pcie_index[0x8]; 10202 u8 reserved_at_10[0xa]; 10203 u8 grp[0x6]; 10204 10205 u8 clr[0x1]; 10206 u8 reserved_at_21[0x1f]; 10207 10208 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set; 10209 }; 10210 10211 struct mlx5_ifc_ppad_reg_bits { 10212 u8 reserved_at_0[0x3]; 10213 u8 single_mac[0x1]; 10214 u8 reserved_at_4[0x4]; 10215 u8 local_port[0x8]; 10216 u8 mac_47_32[0x10]; 10217 10218 u8 mac_31_0[0x20]; 10219 10220 u8 reserved_at_40[0x40]; 10221 }; 10222 10223 struct mlx5_ifc_pmtu_reg_bits { 10224 u8 reserved_at_0[0x8]; 10225 u8 local_port[0x8]; 10226 u8 reserved_at_10[0x10]; 10227 10228 u8 max_mtu[0x10]; 10229 u8 reserved_at_30[0x10]; 10230 10231 u8 admin_mtu[0x10]; 10232 u8 reserved_at_50[0x10]; 10233 10234 u8 oper_mtu[0x10]; 10235 u8 reserved_at_70[0x10]; 10236 }; 10237 10238 struct mlx5_ifc_pmpr_reg_bits { 10239 u8 reserved_at_0[0x8]; 10240 u8 module[0x8]; 10241 u8 reserved_at_10[0x10]; 10242 10243 u8 reserved_at_20[0x18]; 10244 u8 attenuation_5g[0x8]; 10245 10246 u8 reserved_at_40[0x18]; 10247 u8 attenuation_7g[0x8]; 10248 10249 u8 reserved_at_60[0x18]; 10250 u8 attenuation_12g[0x8]; 10251 }; 10252 10253 struct mlx5_ifc_pmpe_reg_bits { 10254 u8 reserved_at_0[0x8]; 10255 u8 module[0x8]; 10256 u8 reserved_at_10[0xc]; 10257 u8 module_status[0x4]; 10258 10259 u8 reserved_at_20[0x60]; 10260 }; 10261 10262 struct mlx5_ifc_pmpc_reg_bits { 10263 u8 module_state_updated[32][0x8]; 10264 }; 10265 10266 struct mlx5_ifc_pmlpn_reg_bits { 10267 u8 reserved_at_0[0x4]; 10268 u8 mlpn_status[0x4]; 10269 u8 local_port[0x8]; 10270 u8 reserved_at_10[0x10]; 10271 10272 u8 e[0x1]; 10273 u8 reserved_at_21[0x1f]; 10274 }; 10275 10276 struct mlx5_ifc_pmlp_reg_bits { 10277 u8 rxtx[0x1]; 10278 u8 reserved_at_1[0x7]; 10279 u8 local_port[0x8]; 10280 u8 reserved_at_10[0x8]; 10281 u8 width[0x8]; 10282 10283 u8 lane0_module_mapping[0x20]; 10284 10285 u8 lane1_module_mapping[0x20]; 10286 10287 u8 lane2_module_mapping[0x20]; 10288 10289 u8 lane3_module_mapping[0x20]; 10290 10291 u8 reserved_at_a0[0x160]; 10292 }; 10293 10294 struct mlx5_ifc_pmaos_reg_bits { 10295 u8 reserved_at_0[0x8]; 10296 u8 module[0x8]; 10297 u8 reserved_at_10[0x4]; 10298 u8 admin_status[0x4]; 10299 u8 reserved_at_18[0x4]; 10300 u8 oper_status[0x4]; 10301 10302 u8 ase[0x1]; 10303 u8 ee[0x1]; 10304 u8 reserved_at_22[0x1c]; 10305 u8 e[0x2]; 10306 10307 u8 reserved_at_40[0x40]; 10308 }; 10309 10310 struct mlx5_ifc_plpc_reg_bits { 10311 u8 reserved_at_0[0x4]; 10312 u8 profile_id[0xc]; 10313 u8 reserved_at_10[0x4]; 10314 u8 proto_mask[0x4]; 10315 u8 reserved_at_18[0x8]; 10316 10317 u8 reserved_at_20[0x10]; 10318 u8 lane_speed[0x10]; 10319 10320 u8 reserved_at_40[0x17]; 10321 u8 lpbf[0x1]; 10322 u8 fec_mode_policy[0x8]; 10323 10324 u8 retransmission_capability[0x8]; 10325 u8 fec_mode_capability[0x18]; 10326 10327 u8 retransmission_support_admin[0x8]; 10328 u8 fec_mode_support_admin[0x18]; 10329 10330 u8 retransmission_request_admin[0x8]; 10331 u8 fec_mode_request_admin[0x18]; 10332 10333 u8 reserved_at_c0[0x80]; 10334 }; 10335 10336 struct mlx5_ifc_plib_reg_bits { 10337 u8 reserved_at_0[0x8]; 10338 u8 local_port[0x8]; 10339 u8 reserved_at_10[0x8]; 10340 u8 ib_port[0x8]; 10341 10342 u8 reserved_at_20[0x60]; 10343 }; 10344 10345 struct mlx5_ifc_plbf_reg_bits { 10346 u8 reserved_at_0[0x8]; 10347 u8 local_port[0x8]; 10348 u8 reserved_at_10[0xd]; 10349 u8 lbf_mode[0x3]; 10350 10351 u8 reserved_at_20[0x20]; 10352 }; 10353 10354 struct mlx5_ifc_pipg_reg_bits { 10355 u8 reserved_at_0[0x8]; 10356 u8 local_port[0x8]; 10357 u8 reserved_at_10[0x10]; 10358 10359 u8 dic[0x1]; 10360 u8 reserved_at_21[0x19]; 10361 u8 ipg[0x4]; 10362 u8 reserved_at_3e[0x2]; 10363 }; 10364 10365 struct mlx5_ifc_pifr_reg_bits { 10366 u8 reserved_at_0[0x8]; 10367 u8 local_port[0x8]; 10368 u8 reserved_at_10[0x10]; 10369 10370 u8 reserved_at_20[0xe0]; 10371 10372 u8 port_filter[8][0x20]; 10373 10374 u8 port_filter_update_en[8][0x20]; 10375 }; 10376 10377 struct mlx5_ifc_pfcc_reg_bits { 10378 u8 reserved_at_0[0x8]; 10379 u8 local_port[0x8]; 10380 u8 reserved_at_10[0xb]; 10381 u8 ppan_mask_n[0x1]; 10382 u8 minor_stall_mask[0x1]; 10383 u8 critical_stall_mask[0x1]; 10384 u8 reserved_at_1e[0x2]; 10385 10386 u8 ppan[0x4]; 10387 u8 reserved_at_24[0x4]; 10388 u8 prio_mask_tx[0x8]; 10389 u8 reserved_at_30[0x8]; 10390 u8 prio_mask_rx[0x8]; 10391 10392 u8 pptx[0x1]; 10393 u8 aptx[0x1]; 10394 u8 pptx_mask_n[0x1]; 10395 u8 reserved_at_43[0x5]; 10396 u8 pfctx[0x8]; 10397 u8 reserved_at_50[0x10]; 10398 10399 u8 pprx[0x1]; 10400 u8 aprx[0x1]; 10401 u8 pprx_mask_n[0x1]; 10402 u8 reserved_at_63[0x5]; 10403 u8 pfcrx[0x8]; 10404 u8 reserved_at_70[0x10]; 10405 10406 u8 device_stall_minor_watermark[0x10]; 10407 u8 device_stall_critical_watermark[0x10]; 10408 10409 u8 reserved_at_a0[0x60]; 10410 }; 10411 10412 struct mlx5_ifc_pelc_reg_bits { 10413 u8 op[0x4]; 10414 u8 reserved_at_4[0x4]; 10415 u8 local_port[0x8]; 10416 u8 reserved_at_10[0x10]; 10417 10418 u8 op_admin[0x8]; 10419 u8 op_capability[0x8]; 10420 u8 op_request[0x8]; 10421 u8 op_active[0x8]; 10422 10423 u8 admin[0x40]; 10424 10425 u8 capability[0x40]; 10426 10427 u8 request[0x40]; 10428 10429 u8 active[0x40]; 10430 10431 u8 reserved_at_140[0x80]; 10432 }; 10433 10434 struct mlx5_ifc_peir_reg_bits { 10435 u8 reserved_at_0[0x8]; 10436 u8 local_port[0x8]; 10437 u8 reserved_at_10[0x10]; 10438 10439 u8 reserved_at_20[0xc]; 10440 u8 error_count[0x4]; 10441 u8 reserved_at_30[0x10]; 10442 10443 u8 reserved_at_40[0xc]; 10444 u8 lane[0x4]; 10445 u8 reserved_at_50[0x8]; 10446 u8 error_type[0x8]; 10447 }; 10448 10449 struct mlx5_ifc_mpegc_reg_bits { 10450 u8 reserved_at_0[0x30]; 10451 u8 field_select[0x10]; 10452 10453 u8 tx_overflow_sense[0x1]; 10454 u8 mark_cqe[0x1]; 10455 u8 mark_cnp[0x1]; 10456 u8 reserved_at_43[0x1b]; 10457 u8 tx_lossy_overflow_oper[0x2]; 10458 10459 u8 reserved_at_60[0x100]; 10460 }; 10461 10462 struct mlx5_ifc_mpir_reg_bits { 10463 u8 sdm[0x1]; 10464 u8 reserved_at_1[0x1b]; 10465 u8 host_buses[0x4]; 10466 10467 u8 reserved_at_20[0x20]; 10468 10469 u8 local_port[0x8]; 10470 u8 reserved_at_28[0x18]; 10471 10472 u8 reserved_at_60[0x20]; 10473 }; 10474 10475 enum { 10476 MLX5_MTUTC_FREQ_ADJ_UNITS_PPB = 0x0, 10477 MLX5_MTUTC_FREQ_ADJ_UNITS_SCALED_PPM = 0x1, 10478 }; 10479 10480 enum { 10481 MLX5_MTUTC_OPERATION_SET_TIME_IMMEDIATE = 0x1, 10482 MLX5_MTUTC_OPERATION_ADJUST_TIME = 0x2, 10483 MLX5_MTUTC_OPERATION_ADJUST_FREQ_UTC = 0x3, 10484 }; 10485 10486 struct mlx5_ifc_mtutc_reg_bits { 10487 u8 reserved_at_0[0x5]; 10488 u8 freq_adj_units[0x3]; 10489 u8 reserved_at_8[0x3]; 10490 u8 log_max_freq_adjustment[0x5]; 10491 10492 u8 reserved_at_10[0xc]; 10493 u8 operation[0x4]; 10494 10495 u8 freq_adjustment[0x20]; 10496 10497 u8 reserved_at_40[0x40]; 10498 10499 u8 utc_sec[0x20]; 10500 10501 u8 reserved_at_a0[0x2]; 10502 u8 utc_nsec[0x1e]; 10503 10504 u8 time_adjustment[0x20]; 10505 }; 10506 10507 struct mlx5_ifc_pcam_enhanced_features_bits { 10508 u8 reserved_at_0[0x48]; 10509 u8 fec_100G_per_lane_in_pplm[0x1]; 10510 u8 reserved_at_49[0x1f]; 10511 u8 fec_50G_per_lane_in_pplm[0x1]; 10512 u8 reserved_at_69[0x4]; 10513 u8 rx_icrc_encapsulated_counter[0x1]; 10514 u8 reserved_at_6e[0x4]; 10515 u8 ptys_extended_ethernet[0x1]; 10516 u8 reserved_at_73[0x3]; 10517 u8 pfcc_mask[0x1]; 10518 u8 reserved_at_77[0x3]; 10519 u8 per_lane_error_counters[0x1]; 10520 u8 rx_buffer_fullness_counters[0x1]; 10521 u8 ptys_connector_type[0x1]; 10522 u8 reserved_at_7d[0x1]; 10523 u8 ppcnt_discard_group[0x1]; 10524 u8 ppcnt_statistical_group[0x1]; 10525 }; 10526 10527 struct mlx5_ifc_pcam_regs_5000_to_507f_bits { 10528 u8 port_access_reg_cap_mask_127_to_96[0x20]; 10529 u8 port_access_reg_cap_mask_95_to_64[0x20]; 10530 10531 u8 port_access_reg_cap_mask_63_to_36[0x1c]; 10532 u8 pplm[0x1]; 10533 u8 port_access_reg_cap_mask_34_to_32[0x3]; 10534 10535 u8 port_access_reg_cap_mask_31_to_13[0x13]; 10536 u8 pbmc[0x1]; 10537 u8 pptb[0x1]; 10538 u8 port_access_reg_cap_mask_10_to_09[0x2]; 10539 u8 ppcnt[0x1]; 10540 u8 port_access_reg_cap_mask_07_to_00[0x8]; 10541 }; 10542 10543 struct mlx5_ifc_pcam_reg_bits { 10544 u8 reserved_at_0[0x8]; 10545 u8 feature_group[0x8]; 10546 u8 reserved_at_10[0x8]; 10547 u8 access_reg_group[0x8]; 10548 10549 u8 reserved_at_20[0x20]; 10550 10551 union { 10552 struct mlx5_ifc_pcam_regs_5000_to_507f_bits regs_5000_to_507f; 10553 u8 reserved_at_0[0x80]; 10554 } port_access_reg_cap_mask; 10555 10556 u8 reserved_at_c0[0x80]; 10557 10558 union { 10559 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features; 10560 u8 reserved_at_0[0x80]; 10561 } feature_cap_mask; 10562 10563 u8 reserved_at_1c0[0xc0]; 10564 }; 10565 10566 struct mlx5_ifc_mcam_enhanced_features_bits { 10567 u8 reserved_at_0[0x50]; 10568 u8 mtutc_freq_adj_units[0x1]; 10569 u8 mtutc_time_adjustment_extended_range[0x1]; 10570 u8 reserved_at_52[0xb]; 10571 u8 mcia_32dwords[0x1]; 10572 u8 out_pulse_duration_ns[0x1]; 10573 u8 npps_period[0x1]; 10574 u8 reserved_at_60[0xa]; 10575 u8 reset_state[0x1]; 10576 u8 ptpcyc2realtime_modify[0x1]; 10577 u8 reserved_at_6c[0x2]; 10578 u8 pci_status_and_power[0x1]; 10579 u8 reserved_at_6f[0x5]; 10580 u8 mark_tx_action_cnp[0x1]; 10581 u8 mark_tx_action_cqe[0x1]; 10582 u8 dynamic_tx_overflow[0x1]; 10583 u8 reserved_at_77[0x4]; 10584 u8 pcie_outbound_stalled[0x1]; 10585 u8 tx_overflow_buffer_pkt[0x1]; 10586 u8 mtpps_enh_out_per_adj[0x1]; 10587 u8 mtpps_fs[0x1]; 10588 u8 pcie_performance_group[0x1]; 10589 }; 10590 10591 struct mlx5_ifc_mcam_access_reg_bits { 10592 u8 reserved_at_0[0x1c]; 10593 u8 mcda[0x1]; 10594 u8 mcc[0x1]; 10595 u8 mcqi[0x1]; 10596 u8 mcqs[0x1]; 10597 10598 u8 regs_95_to_90[0x6]; 10599 u8 mpir[0x1]; 10600 u8 regs_88_to_87[0x2]; 10601 u8 mpegc[0x1]; 10602 u8 mtutc[0x1]; 10603 u8 regs_84_to_68[0x11]; 10604 u8 tracer_registers[0x4]; 10605 10606 u8 regs_63_to_46[0x12]; 10607 u8 mrtc[0x1]; 10608 u8 regs_44_to_41[0x4]; 10609 u8 mfrl[0x1]; 10610 u8 regs_39_to_32[0x8]; 10611 10612 u8 regs_31_to_11[0x15]; 10613 u8 mtmp[0x1]; 10614 u8 regs_9_to_0[0xa]; 10615 }; 10616 10617 struct mlx5_ifc_mcam_access_reg_bits1 { 10618 u8 regs_127_to_96[0x20]; 10619 10620 u8 regs_95_to_64[0x20]; 10621 10622 u8 regs_63_to_32[0x20]; 10623 10624 u8 regs_31_to_0[0x20]; 10625 }; 10626 10627 struct mlx5_ifc_mcam_access_reg_bits2 { 10628 u8 regs_127_to_99[0x1d]; 10629 u8 mirc[0x1]; 10630 u8 regs_97_to_96[0x2]; 10631 10632 u8 regs_95_to_87[0x09]; 10633 u8 synce_registers[0x2]; 10634 u8 regs_84_to_64[0x15]; 10635 10636 u8 regs_63_to_32[0x20]; 10637 10638 u8 regs_31_to_0[0x20]; 10639 }; 10640 10641 struct mlx5_ifc_mcam_access_reg_bits3 { 10642 u8 regs_127_to_96[0x20]; 10643 10644 u8 regs_95_to_64[0x20]; 10645 10646 u8 regs_63_to_32[0x20]; 10647 10648 u8 regs_31_to_2[0x1e]; 10649 u8 mtctr[0x1]; 10650 u8 mtptm[0x1]; 10651 }; 10652 10653 struct mlx5_ifc_mcam_reg_bits { 10654 u8 reserved_at_0[0x8]; 10655 u8 feature_group[0x8]; 10656 u8 reserved_at_10[0x8]; 10657 u8 access_reg_group[0x8]; 10658 10659 u8 reserved_at_20[0x20]; 10660 10661 union { 10662 struct mlx5_ifc_mcam_access_reg_bits access_regs; 10663 struct mlx5_ifc_mcam_access_reg_bits1 access_regs1; 10664 struct mlx5_ifc_mcam_access_reg_bits2 access_regs2; 10665 struct mlx5_ifc_mcam_access_reg_bits3 access_regs3; 10666 u8 reserved_at_0[0x80]; 10667 } mng_access_reg_cap_mask; 10668 10669 u8 reserved_at_c0[0x80]; 10670 10671 union { 10672 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features; 10673 u8 reserved_at_0[0x80]; 10674 } mng_feature_cap_mask; 10675 10676 u8 reserved_at_1c0[0x80]; 10677 }; 10678 10679 struct mlx5_ifc_qcam_access_reg_cap_mask { 10680 u8 qcam_access_reg_cap_mask_127_to_20[0x6C]; 10681 u8 qpdpm[0x1]; 10682 u8 qcam_access_reg_cap_mask_18_to_4[0x0F]; 10683 u8 qdpm[0x1]; 10684 u8 qpts[0x1]; 10685 u8 qcap[0x1]; 10686 u8 qcam_access_reg_cap_mask_0[0x1]; 10687 }; 10688 10689 struct mlx5_ifc_qcam_qos_feature_cap_mask { 10690 u8 qcam_qos_feature_cap_mask_127_to_1[0x7F]; 10691 u8 qpts_trust_both[0x1]; 10692 }; 10693 10694 struct mlx5_ifc_qcam_reg_bits { 10695 u8 reserved_at_0[0x8]; 10696 u8 feature_group[0x8]; 10697 u8 reserved_at_10[0x8]; 10698 u8 access_reg_group[0x8]; 10699 u8 reserved_at_20[0x20]; 10700 10701 union { 10702 struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap; 10703 u8 reserved_at_0[0x80]; 10704 } qos_access_reg_cap_mask; 10705 10706 u8 reserved_at_c0[0x80]; 10707 10708 union { 10709 struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap; 10710 u8 reserved_at_0[0x80]; 10711 } qos_feature_cap_mask; 10712 10713 u8 reserved_at_1c0[0x80]; 10714 }; 10715 10716 struct mlx5_ifc_core_dump_reg_bits { 10717 u8 reserved_at_0[0x18]; 10718 u8 core_dump_type[0x8]; 10719 10720 u8 reserved_at_20[0x30]; 10721 u8 vhca_id[0x10]; 10722 10723 u8 reserved_at_60[0x8]; 10724 u8 qpn[0x18]; 10725 u8 reserved_at_80[0x180]; 10726 }; 10727 10728 struct mlx5_ifc_pcap_reg_bits { 10729 u8 reserved_at_0[0x8]; 10730 u8 local_port[0x8]; 10731 u8 reserved_at_10[0x10]; 10732 10733 u8 port_capability_mask[4][0x20]; 10734 }; 10735 10736 struct mlx5_ifc_paos_reg_bits { 10737 u8 swid[0x8]; 10738 u8 local_port[0x8]; 10739 u8 reserved_at_10[0x4]; 10740 u8 admin_status[0x4]; 10741 u8 reserved_at_18[0x4]; 10742 u8 oper_status[0x4]; 10743 10744 u8 ase[0x1]; 10745 u8 ee[0x1]; 10746 u8 reserved_at_22[0x1c]; 10747 u8 e[0x2]; 10748 10749 u8 reserved_at_40[0x40]; 10750 }; 10751 10752 struct mlx5_ifc_pamp_reg_bits { 10753 u8 reserved_at_0[0x8]; 10754 u8 opamp_group[0x8]; 10755 u8 reserved_at_10[0xc]; 10756 u8 opamp_group_type[0x4]; 10757 10758 u8 start_index[0x10]; 10759 u8 reserved_at_30[0x4]; 10760 u8 num_of_indices[0xc]; 10761 10762 u8 index_data[18][0x10]; 10763 }; 10764 10765 struct mlx5_ifc_pcmr_reg_bits { 10766 u8 reserved_at_0[0x8]; 10767 u8 local_port[0x8]; 10768 u8 reserved_at_10[0x10]; 10769 10770 u8 entropy_force_cap[0x1]; 10771 u8 entropy_calc_cap[0x1]; 10772 u8 entropy_gre_calc_cap[0x1]; 10773 u8 reserved_at_23[0xf]; 10774 u8 rx_ts_over_crc_cap[0x1]; 10775 u8 reserved_at_33[0xb]; 10776 u8 fcs_cap[0x1]; 10777 u8 reserved_at_3f[0x1]; 10778 10779 u8 entropy_force[0x1]; 10780 u8 entropy_calc[0x1]; 10781 u8 entropy_gre_calc[0x1]; 10782 u8 reserved_at_43[0xf]; 10783 u8 rx_ts_over_crc[0x1]; 10784 u8 reserved_at_53[0xb]; 10785 u8 fcs_chk[0x1]; 10786 u8 reserved_at_5f[0x1]; 10787 }; 10788 10789 struct mlx5_ifc_lane_2_module_mapping_bits { 10790 u8 reserved_at_0[0x4]; 10791 u8 rx_lane[0x4]; 10792 u8 reserved_at_8[0x4]; 10793 u8 tx_lane[0x4]; 10794 u8 reserved_at_10[0x8]; 10795 u8 module[0x8]; 10796 }; 10797 10798 struct mlx5_ifc_bufferx_reg_bits { 10799 u8 reserved_at_0[0x6]; 10800 u8 lossy[0x1]; 10801 u8 epsb[0x1]; 10802 u8 reserved_at_8[0x8]; 10803 u8 size[0x10]; 10804 10805 u8 xoff_threshold[0x10]; 10806 u8 xon_threshold[0x10]; 10807 }; 10808 10809 struct mlx5_ifc_set_node_in_bits { 10810 u8 node_description[64][0x8]; 10811 }; 10812 10813 struct mlx5_ifc_register_power_settings_bits { 10814 u8 reserved_at_0[0x18]; 10815 u8 power_settings_level[0x8]; 10816 10817 u8 reserved_at_20[0x60]; 10818 }; 10819 10820 struct mlx5_ifc_register_host_endianness_bits { 10821 u8 he[0x1]; 10822 u8 reserved_at_1[0x1f]; 10823 10824 u8 reserved_at_20[0x60]; 10825 }; 10826 10827 struct mlx5_ifc_umr_pointer_desc_argument_bits { 10828 u8 reserved_at_0[0x20]; 10829 10830 u8 mkey[0x20]; 10831 10832 u8 addressh_63_32[0x20]; 10833 10834 u8 addressl_31_0[0x20]; 10835 }; 10836 10837 struct mlx5_ifc_ud_adrs_vector_bits { 10838 u8 dc_key[0x40]; 10839 10840 u8 ext[0x1]; 10841 u8 reserved_at_41[0x7]; 10842 u8 destination_qp_dct[0x18]; 10843 10844 u8 static_rate[0x4]; 10845 u8 sl_eth_prio[0x4]; 10846 u8 fl[0x1]; 10847 u8 mlid[0x7]; 10848 u8 rlid_udp_sport[0x10]; 10849 10850 u8 reserved_at_80[0x20]; 10851 10852 u8 rmac_47_16[0x20]; 10853 10854 u8 rmac_15_0[0x10]; 10855 u8 tclass[0x8]; 10856 u8 hop_limit[0x8]; 10857 10858 u8 reserved_at_e0[0x1]; 10859 u8 grh[0x1]; 10860 u8 reserved_at_e2[0x2]; 10861 u8 src_addr_index[0x8]; 10862 u8 flow_label[0x14]; 10863 10864 u8 rgid_rip[16][0x8]; 10865 }; 10866 10867 struct mlx5_ifc_pages_req_event_bits { 10868 u8 reserved_at_0[0x10]; 10869 u8 function_id[0x10]; 10870 10871 u8 num_pages[0x20]; 10872 10873 u8 reserved_at_40[0xa0]; 10874 }; 10875 10876 struct mlx5_ifc_eqe_bits { 10877 u8 reserved_at_0[0x8]; 10878 u8 event_type[0x8]; 10879 u8 reserved_at_10[0x8]; 10880 u8 event_sub_type[0x8]; 10881 10882 u8 reserved_at_20[0xe0]; 10883 10884 union mlx5_ifc_event_auto_bits event_data; 10885 10886 u8 reserved_at_1e0[0x10]; 10887 u8 signature[0x8]; 10888 u8 reserved_at_1f8[0x7]; 10889 u8 owner[0x1]; 10890 }; 10891 10892 enum { 10893 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7, 10894 }; 10895 10896 struct mlx5_ifc_cmd_queue_entry_bits { 10897 u8 type[0x8]; 10898 u8 reserved_at_8[0x18]; 10899 10900 u8 input_length[0x20]; 10901 10902 u8 input_mailbox_pointer_63_32[0x20]; 10903 10904 u8 input_mailbox_pointer_31_9[0x17]; 10905 u8 reserved_at_77[0x9]; 10906 10907 u8 command_input_inline_data[16][0x8]; 10908 10909 u8 command_output_inline_data[16][0x8]; 10910 10911 u8 output_mailbox_pointer_63_32[0x20]; 10912 10913 u8 output_mailbox_pointer_31_9[0x17]; 10914 u8 reserved_at_1b7[0x9]; 10915 10916 u8 output_length[0x20]; 10917 10918 u8 token[0x8]; 10919 u8 signature[0x8]; 10920 u8 reserved_at_1f0[0x8]; 10921 u8 status[0x7]; 10922 u8 ownership[0x1]; 10923 }; 10924 10925 struct mlx5_ifc_cmd_out_bits { 10926 u8 status[0x8]; 10927 u8 reserved_at_8[0x18]; 10928 10929 u8 syndrome[0x20]; 10930 10931 u8 command_output[0x20]; 10932 }; 10933 10934 struct mlx5_ifc_cmd_in_bits { 10935 u8 opcode[0x10]; 10936 u8 reserved_at_10[0x10]; 10937 10938 u8 reserved_at_20[0x10]; 10939 u8 op_mod[0x10]; 10940 10941 u8 command[][0x20]; 10942 }; 10943 10944 struct mlx5_ifc_cmd_if_box_bits { 10945 u8 mailbox_data[512][0x8]; 10946 10947 u8 reserved_at_1000[0x180]; 10948 10949 u8 next_pointer_63_32[0x20]; 10950 10951 u8 next_pointer_31_10[0x16]; 10952 u8 reserved_at_11b6[0xa]; 10953 10954 u8 block_number[0x20]; 10955 10956 u8 reserved_at_11e0[0x8]; 10957 u8 token[0x8]; 10958 u8 ctrl_signature[0x8]; 10959 u8 signature[0x8]; 10960 }; 10961 10962 struct mlx5_ifc_mtt_bits { 10963 u8 ptag_63_32[0x20]; 10964 10965 u8 ptag_31_8[0x18]; 10966 u8 reserved_at_38[0x6]; 10967 u8 wr_en[0x1]; 10968 u8 rd_en[0x1]; 10969 }; 10970 10971 struct mlx5_ifc_query_wol_rol_out_bits { 10972 u8 status[0x8]; 10973 u8 reserved_at_8[0x18]; 10974 10975 u8 syndrome[0x20]; 10976 10977 u8 reserved_at_40[0x10]; 10978 u8 rol_mode[0x8]; 10979 u8 wol_mode[0x8]; 10980 10981 u8 reserved_at_60[0x20]; 10982 }; 10983 10984 struct mlx5_ifc_query_wol_rol_in_bits { 10985 u8 opcode[0x10]; 10986 u8 reserved_at_10[0x10]; 10987 10988 u8 reserved_at_20[0x10]; 10989 u8 op_mod[0x10]; 10990 10991 u8 reserved_at_40[0x40]; 10992 }; 10993 10994 struct mlx5_ifc_set_wol_rol_out_bits { 10995 u8 status[0x8]; 10996 u8 reserved_at_8[0x18]; 10997 10998 u8 syndrome[0x20]; 10999 11000 u8 reserved_at_40[0x40]; 11001 }; 11002 11003 struct mlx5_ifc_set_wol_rol_in_bits { 11004 u8 opcode[0x10]; 11005 u8 reserved_at_10[0x10]; 11006 11007 u8 reserved_at_20[0x10]; 11008 u8 op_mod[0x10]; 11009 11010 u8 rol_mode_valid[0x1]; 11011 u8 wol_mode_valid[0x1]; 11012 u8 reserved_at_42[0xe]; 11013 u8 rol_mode[0x8]; 11014 u8 wol_mode[0x8]; 11015 11016 u8 reserved_at_60[0x20]; 11017 }; 11018 11019 enum { 11020 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0, 11021 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1, 11022 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2, 11023 MLX5_INITIAL_SEG_NIC_INTERFACE_SW_RESET = 0x7, 11024 }; 11025 11026 enum { 11027 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0, 11028 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1, 11029 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2, 11030 }; 11031 11032 enum { 11033 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR = 0x1, 11034 MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC = 0x7, 11035 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR = 0x8, 11036 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR = 0x9, 11037 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR = 0xa, 11038 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR = 0xb, 11039 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN = 0xc, 11040 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR = 0xd, 11041 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV = 0xe, 11042 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR = 0xf, 11043 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR = 0x10, 11044 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PCI_POISONED_ERR = 0x12, 11045 }; 11046 11047 struct mlx5_ifc_initial_seg_bits { 11048 u8 fw_rev_minor[0x10]; 11049 u8 fw_rev_major[0x10]; 11050 11051 u8 cmd_interface_rev[0x10]; 11052 u8 fw_rev_subminor[0x10]; 11053 11054 u8 reserved_at_40[0x40]; 11055 11056 u8 cmdq_phy_addr_63_32[0x20]; 11057 11058 u8 cmdq_phy_addr_31_12[0x14]; 11059 u8 reserved_at_b4[0x2]; 11060 u8 nic_interface[0x2]; 11061 u8 log_cmdq_size[0x4]; 11062 u8 log_cmdq_stride[0x4]; 11063 11064 u8 command_doorbell_vector[0x20]; 11065 11066 u8 reserved_at_e0[0xf00]; 11067 11068 u8 initializing[0x1]; 11069 u8 reserved_at_fe1[0x4]; 11070 u8 nic_interface_supported[0x3]; 11071 u8 embedded_cpu[0x1]; 11072 u8 reserved_at_fe9[0x17]; 11073 11074 struct mlx5_ifc_health_buffer_bits health_buffer; 11075 11076 u8 no_dram_nic_offset[0x20]; 11077 11078 u8 reserved_at_1220[0x6e40]; 11079 11080 u8 reserved_at_8060[0x1f]; 11081 u8 clear_int[0x1]; 11082 11083 u8 health_syndrome[0x8]; 11084 u8 health_counter[0x18]; 11085 11086 u8 reserved_at_80a0[0x17fc0]; 11087 }; 11088 11089 struct mlx5_ifc_mtpps_reg_bits { 11090 u8 reserved_at_0[0xc]; 11091 u8 cap_number_of_pps_pins[0x4]; 11092 u8 reserved_at_10[0x4]; 11093 u8 cap_max_num_of_pps_in_pins[0x4]; 11094 u8 reserved_at_18[0x4]; 11095 u8 cap_max_num_of_pps_out_pins[0x4]; 11096 11097 u8 reserved_at_20[0x13]; 11098 u8 cap_log_min_npps_period[0x5]; 11099 u8 reserved_at_38[0x3]; 11100 u8 cap_log_min_out_pulse_duration_ns[0x5]; 11101 11102 u8 reserved_at_40[0x4]; 11103 u8 cap_pin_3_mode[0x4]; 11104 u8 reserved_at_48[0x4]; 11105 u8 cap_pin_2_mode[0x4]; 11106 u8 reserved_at_50[0x4]; 11107 u8 cap_pin_1_mode[0x4]; 11108 u8 reserved_at_58[0x4]; 11109 u8 cap_pin_0_mode[0x4]; 11110 11111 u8 reserved_at_60[0x4]; 11112 u8 cap_pin_7_mode[0x4]; 11113 u8 reserved_at_68[0x4]; 11114 u8 cap_pin_6_mode[0x4]; 11115 u8 reserved_at_70[0x4]; 11116 u8 cap_pin_5_mode[0x4]; 11117 u8 reserved_at_78[0x4]; 11118 u8 cap_pin_4_mode[0x4]; 11119 11120 u8 field_select[0x20]; 11121 u8 reserved_at_a0[0x20]; 11122 11123 u8 npps_period[0x40]; 11124 11125 u8 enable[0x1]; 11126 u8 reserved_at_101[0xb]; 11127 u8 pattern[0x4]; 11128 u8 reserved_at_110[0x4]; 11129 u8 pin_mode[0x4]; 11130 u8 pin[0x8]; 11131 11132 u8 reserved_at_120[0x2]; 11133 u8 out_pulse_duration_ns[0x1e]; 11134 11135 u8 time_stamp[0x40]; 11136 11137 u8 out_pulse_duration[0x10]; 11138 u8 out_periodic_adjustment[0x10]; 11139 u8 enhanced_out_periodic_adjustment[0x20]; 11140 11141 u8 reserved_at_1c0[0x20]; 11142 }; 11143 11144 struct mlx5_ifc_mtppse_reg_bits { 11145 u8 reserved_at_0[0x18]; 11146 u8 pin[0x8]; 11147 u8 event_arm[0x1]; 11148 u8 reserved_at_21[0x1b]; 11149 u8 event_generation_mode[0x4]; 11150 u8 reserved_at_40[0x40]; 11151 }; 11152 11153 struct mlx5_ifc_mcqs_reg_bits { 11154 u8 last_index_flag[0x1]; 11155 u8 reserved_at_1[0x7]; 11156 u8 fw_device[0x8]; 11157 u8 component_index[0x10]; 11158 11159 u8 reserved_at_20[0x10]; 11160 u8 identifier[0x10]; 11161 11162 u8 reserved_at_40[0x17]; 11163 u8 component_status[0x5]; 11164 u8 component_update_state[0x4]; 11165 11166 u8 last_update_state_changer_type[0x4]; 11167 u8 last_update_state_changer_host_id[0x4]; 11168 u8 reserved_at_68[0x18]; 11169 }; 11170 11171 struct mlx5_ifc_mcqi_cap_bits { 11172 u8 supported_info_bitmask[0x20]; 11173 11174 u8 component_size[0x20]; 11175 11176 u8 max_component_size[0x20]; 11177 11178 u8 log_mcda_word_size[0x4]; 11179 u8 reserved_at_64[0xc]; 11180 u8 mcda_max_write_size[0x10]; 11181 11182 u8 rd_en[0x1]; 11183 u8 reserved_at_81[0x1]; 11184 u8 match_chip_id[0x1]; 11185 u8 match_psid[0x1]; 11186 u8 check_user_timestamp[0x1]; 11187 u8 match_base_guid_mac[0x1]; 11188 u8 reserved_at_86[0x1a]; 11189 }; 11190 11191 struct mlx5_ifc_mcqi_version_bits { 11192 u8 reserved_at_0[0x2]; 11193 u8 build_time_valid[0x1]; 11194 u8 user_defined_time_valid[0x1]; 11195 u8 reserved_at_4[0x14]; 11196 u8 version_string_length[0x8]; 11197 11198 u8 version[0x20]; 11199 11200 u8 build_time[0x40]; 11201 11202 u8 user_defined_time[0x40]; 11203 11204 u8 build_tool_version[0x20]; 11205 11206 u8 reserved_at_e0[0x20]; 11207 11208 u8 version_string[92][0x8]; 11209 }; 11210 11211 struct mlx5_ifc_mcqi_activation_method_bits { 11212 u8 pending_server_ac_power_cycle[0x1]; 11213 u8 pending_server_dc_power_cycle[0x1]; 11214 u8 pending_server_reboot[0x1]; 11215 u8 pending_fw_reset[0x1]; 11216 u8 auto_activate[0x1]; 11217 u8 all_hosts_sync[0x1]; 11218 u8 device_hw_reset[0x1]; 11219 u8 reserved_at_7[0x19]; 11220 }; 11221 11222 union mlx5_ifc_mcqi_reg_data_bits { 11223 struct mlx5_ifc_mcqi_cap_bits mcqi_caps; 11224 struct mlx5_ifc_mcqi_version_bits mcqi_version; 11225 struct mlx5_ifc_mcqi_activation_method_bits mcqi_activation_mathod; 11226 }; 11227 11228 struct mlx5_ifc_mcqi_reg_bits { 11229 u8 read_pending_component[0x1]; 11230 u8 reserved_at_1[0xf]; 11231 u8 component_index[0x10]; 11232 11233 u8 reserved_at_20[0x20]; 11234 11235 u8 reserved_at_40[0x1b]; 11236 u8 info_type[0x5]; 11237 11238 u8 info_size[0x20]; 11239 11240 u8 offset[0x20]; 11241 11242 u8 reserved_at_a0[0x10]; 11243 u8 data_size[0x10]; 11244 11245 union mlx5_ifc_mcqi_reg_data_bits data[]; 11246 }; 11247 11248 struct mlx5_ifc_mcc_reg_bits { 11249 u8 reserved_at_0[0x4]; 11250 u8 time_elapsed_since_last_cmd[0xc]; 11251 u8 reserved_at_10[0x8]; 11252 u8 instruction[0x8]; 11253 11254 u8 reserved_at_20[0x10]; 11255 u8 component_index[0x10]; 11256 11257 u8 reserved_at_40[0x8]; 11258 u8 update_handle[0x18]; 11259 11260 u8 handle_owner_type[0x4]; 11261 u8 handle_owner_host_id[0x4]; 11262 u8 reserved_at_68[0x1]; 11263 u8 control_progress[0x7]; 11264 u8 error_code[0x8]; 11265 u8 reserved_at_78[0x4]; 11266 u8 control_state[0x4]; 11267 11268 u8 component_size[0x20]; 11269 11270 u8 reserved_at_a0[0x60]; 11271 }; 11272 11273 struct mlx5_ifc_mcda_reg_bits { 11274 u8 reserved_at_0[0x8]; 11275 u8 update_handle[0x18]; 11276 11277 u8 offset[0x20]; 11278 11279 u8 reserved_at_40[0x10]; 11280 u8 size[0x10]; 11281 11282 u8 reserved_at_60[0x20]; 11283 11284 u8 data[][0x20]; 11285 }; 11286 11287 enum { 11288 MLX5_MFRL_REG_PCI_RESET_METHOD_LINK_TOGGLE = 0, 11289 MLX5_MFRL_REG_PCI_RESET_METHOD_HOT_RESET = 1, 11290 }; 11291 11292 enum { 11293 MLX5_MFRL_REG_RESET_STATE_IDLE = 0, 11294 MLX5_MFRL_REG_RESET_STATE_IN_NEGOTIATION = 1, 11295 MLX5_MFRL_REG_RESET_STATE_RESET_IN_PROGRESS = 2, 11296 MLX5_MFRL_REG_RESET_STATE_NEG_TIMEOUT = 3, 11297 MLX5_MFRL_REG_RESET_STATE_NACK = 4, 11298 MLX5_MFRL_REG_RESET_STATE_UNLOAD_TIMEOUT = 5, 11299 }; 11300 11301 enum { 11302 MLX5_MFRL_REG_RESET_TYPE_FULL_CHIP = BIT(0), 11303 MLX5_MFRL_REG_RESET_TYPE_NET_PORT_ALIVE = BIT(1), 11304 }; 11305 11306 enum { 11307 MLX5_MFRL_REG_RESET_LEVEL0 = BIT(0), 11308 MLX5_MFRL_REG_RESET_LEVEL3 = BIT(3), 11309 MLX5_MFRL_REG_RESET_LEVEL6 = BIT(6), 11310 }; 11311 11312 struct mlx5_ifc_mfrl_reg_bits { 11313 u8 reserved_at_0[0x20]; 11314 11315 u8 reserved_at_20[0x2]; 11316 u8 pci_sync_for_fw_update_start[0x1]; 11317 u8 pci_sync_for_fw_update_resp[0x2]; 11318 u8 rst_type_sel[0x3]; 11319 u8 pci_reset_req_method[0x3]; 11320 u8 reserved_at_2b[0x1]; 11321 u8 reset_state[0x4]; 11322 u8 reset_type[0x8]; 11323 u8 reset_level[0x8]; 11324 }; 11325 11326 struct mlx5_ifc_mirc_reg_bits { 11327 u8 reserved_at_0[0x18]; 11328 u8 status_code[0x8]; 11329 11330 u8 reserved_at_20[0x20]; 11331 }; 11332 11333 struct mlx5_ifc_pddr_monitor_opcode_bits { 11334 u8 reserved_at_0[0x10]; 11335 u8 monitor_opcode[0x10]; 11336 }; 11337 11338 union mlx5_ifc_pddr_troubleshooting_page_status_opcode_auto_bits { 11339 struct mlx5_ifc_pddr_monitor_opcode_bits pddr_monitor_opcode; 11340 u8 reserved_at_0[0x20]; 11341 }; 11342 11343 enum { 11344 /* Monitor opcodes */ 11345 MLX5_PDDR_REG_TRBLSH_GROUP_OPCODE_MONITOR = 0x0, 11346 }; 11347 11348 struct mlx5_ifc_pddr_troubleshooting_page_bits { 11349 u8 reserved_at_0[0x10]; 11350 u8 group_opcode[0x10]; 11351 11352 union mlx5_ifc_pddr_troubleshooting_page_status_opcode_auto_bits status_opcode; 11353 11354 u8 reserved_at_40[0x20]; 11355 11356 u8 status_message[59][0x20]; 11357 }; 11358 11359 union mlx5_ifc_pddr_reg_page_data_auto_bits { 11360 struct mlx5_ifc_pddr_troubleshooting_page_bits pddr_troubleshooting_page; 11361 u8 reserved_at_0[0x7c0]; 11362 }; 11363 11364 enum { 11365 MLX5_PDDR_REG_PAGE_SELECT_TROUBLESHOOTING_INFO_PAGE = 0x1, 11366 }; 11367 11368 struct mlx5_ifc_pddr_reg_bits { 11369 u8 reserved_at_0[0x8]; 11370 u8 local_port[0x8]; 11371 u8 pnat[0x2]; 11372 u8 reserved_at_12[0xe]; 11373 11374 u8 reserved_at_20[0x18]; 11375 u8 page_select[0x8]; 11376 11377 union mlx5_ifc_pddr_reg_page_data_auto_bits page_data; 11378 }; 11379 11380 struct mlx5_ifc_mrtc_reg_bits { 11381 u8 time_synced[0x1]; 11382 u8 reserved_at_1[0x1f]; 11383 11384 u8 reserved_at_20[0x20]; 11385 11386 u8 time_h[0x20]; 11387 11388 u8 time_l[0x20]; 11389 }; 11390 11391 struct mlx5_ifc_mtcap_reg_bits { 11392 u8 reserved_at_0[0x19]; 11393 u8 sensor_count[0x7]; 11394 11395 u8 reserved_at_20[0x20]; 11396 11397 u8 sensor_map[0x40]; 11398 }; 11399 11400 struct mlx5_ifc_mtmp_reg_bits { 11401 u8 reserved_at_0[0x14]; 11402 u8 sensor_index[0xc]; 11403 11404 u8 reserved_at_20[0x10]; 11405 u8 temperature[0x10]; 11406 11407 u8 mte[0x1]; 11408 u8 mtr[0x1]; 11409 u8 reserved_at_42[0xe]; 11410 u8 max_temperature[0x10]; 11411 11412 u8 tee[0x2]; 11413 u8 reserved_at_62[0xe]; 11414 u8 temp_threshold_hi[0x10]; 11415 11416 u8 reserved_at_80[0x10]; 11417 u8 temp_threshold_lo[0x10]; 11418 11419 u8 reserved_at_a0[0x20]; 11420 11421 u8 sensor_name_hi[0x20]; 11422 u8 sensor_name_lo[0x20]; 11423 }; 11424 11425 struct mlx5_ifc_mtptm_reg_bits { 11426 u8 reserved_at_0[0x10]; 11427 u8 psta[0x1]; 11428 u8 reserved_at_11[0xf]; 11429 11430 u8 reserved_at_20[0x60]; 11431 }; 11432 11433 enum { 11434 MLX5_MTCTR_REQUEST_NOP = 0x0, 11435 MLX5_MTCTR_REQUEST_PTM_ROOT_CLOCK = 0x1, 11436 MLX5_MTCTR_REQUEST_FREE_RUNNING_COUNTER = 0x2, 11437 MLX5_MTCTR_REQUEST_REAL_TIME_CLOCK = 0x3, 11438 }; 11439 11440 struct mlx5_ifc_mtctr_reg_bits { 11441 u8 first_clock_timestamp_request[0x8]; 11442 u8 second_clock_timestamp_request[0x8]; 11443 u8 reserved_at_10[0x10]; 11444 11445 u8 first_clock_valid[0x1]; 11446 u8 second_clock_valid[0x1]; 11447 u8 reserved_at_22[0x1e]; 11448 11449 u8 first_clock_timestamp[0x40]; 11450 u8 second_clock_timestamp[0x40]; 11451 }; 11452 11453 union mlx5_ifc_ports_control_registers_document_bits { 11454 struct mlx5_ifc_bufferx_reg_bits bufferx_reg; 11455 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 11456 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 11457 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 11458 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 11459 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 11460 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 11461 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout; 11462 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout; 11463 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping; 11464 struct mlx5_ifc_pamp_reg_bits pamp_reg; 11465 struct mlx5_ifc_paos_reg_bits paos_reg; 11466 struct mlx5_ifc_pcap_reg_bits pcap_reg; 11467 struct mlx5_ifc_pddr_monitor_opcode_bits pddr_monitor_opcode; 11468 struct mlx5_ifc_pddr_reg_bits pddr_reg; 11469 struct mlx5_ifc_pddr_troubleshooting_page_bits pddr_troubleshooting_page; 11470 struct mlx5_ifc_peir_reg_bits peir_reg; 11471 struct mlx5_ifc_pelc_reg_bits pelc_reg; 11472 struct mlx5_ifc_pfcc_reg_bits pfcc_reg; 11473 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 11474 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 11475 struct mlx5_ifc_pifr_reg_bits pifr_reg; 11476 struct mlx5_ifc_pipg_reg_bits pipg_reg; 11477 struct mlx5_ifc_plbf_reg_bits plbf_reg; 11478 struct mlx5_ifc_plib_reg_bits plib_reg; 11479 struct mlx5_ifc_plpc_reg_bits plpc_reg; 11480 struct mlx5_ifc_pmaos_reg_bits pmaos_reg; 11481 struct mlx5_ifc_pmlp_reg_bits pmlp_reg; 11482 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg; 11483 struct mlx5_ifc_pmpc_reg_bits pmpc_reg; 11484 struct mlx5_ifc_pmpe_reg_bits pmpe_reg; 11485 struct mlx5_ifc_pmpr_reg_bits pmpr_reg; 11486 struct mlx5_ifc_pmtu_reg_bits pmtu_reg; 11487 struct mlx5_ifc_ppad_reg_bits ppad_reg; 11488 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg; 11489 struct mlx5_ifc_mpein_reg_bits mpein_reg; 11490 struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg; 11491 struct mlx5_ifc_pplm_reg_bits pplm_reg; 11492 struct mlx5_ifc_pplr_reg_bits pplr_reg; 11493 struct mlx5_ifc_ppsc_reg_bits ppsc_reg; 11494 struct mlx5_ifc_pqdr_reg_bits pqdr_reg; 11495 struct mlx5_ifc_pspa_reg_bits pspa_reg; 11496 struct mlx5_ifc_ptas_reg_bits ptas_reg; 11497 struct mlx5_ifc_ptys_reg_bits ptys_reg; 11498 struct mlx5_ifc_mlcr_reg_bits mlcr_reg; 11499 struct mlx5_ifc_pude_reg_bits pude_reg; 11500 struct mlx5_ifc_pvlc_reg_bits pvlc_reg; 11501 struct mlx5_ifc_slrg_reg_bits slrg_reg; 11502 struct mlx5_ifc_sltp_reg_bits sltp_reg; 11503 struct mlx5_ifc_mtpps_reg_bits mtpps_reg; 11504 struct mlx5_ifc_mtppse_reg_bits mtppse_reg; 11505 struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg; 11506 struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits; 11507 struct mlx5_ifc_fpga_cap_bits fpga_cap_bits; 11508 struct mlx5_ifc_mcqi_reg_bits mcqi_reg; 11509 struct mlx5_ifc_mcc_reg_bits mcc_reg; 11510 struct mlx5_ifc_mcda_reg_bits mcda_reg; 11511 struct mlx5_ifc_mirc_reg_bits mirc_reg; 11512 struct mlx5_ifc_mfrl_reg_bits mfrl_reg; 11513 struct mlx5_ifc_mtutc_reg_bits mtutc_reg; 11514 struct mlx5_ifc_mrtc_reg_bits mrtc_reg; 11515 struct mlx5_ifc_mtcap_reg_bits mtcap_reg; 11516 struct mlx5_ifc_mtmp_reg_bits mtmp_reg; 11517 struct mlx5_ifc_mtptm_reg_bits mtptm_reg; 11518 struct mlx5_ifc_mtctr_reg_bits mtctr_reg; 11519 u8 reserved_at_0[0x60e0]; 11520 }; 11521 11522 union mlx5_ifc_debug_enhancements_document_bits { 11523 struct mlx5_ifc_health_buffer_bits health_buffer; 11524 u8 reserved_at_0[0x200]; 11525 }; 11526 11527 union mlx5_ifc_uplink_pci_interface_document_bits { 11528 struct mlx5_ifc_initial_seg_bits initial_seg; 11529 u8 reserved_at_0[0x20060]; 11530 }; 11531 11532 struct mlx5_ifc_set_flow_table_root_out_bits { 11533 u8 status[0x8]; 11534 u8 reserved_at_8[0x18]; 11535 11536 u8 syndrome[0x20]; 11537 11538 u8 reserved_at_40[0x40]; 11539 }; 11540 11541 struct mlx5_ifc_set_flow_table_root_in_bits { 11542 u8 opcode[0x10]; 11543 u8 reserved_at_10[0x10]; 11544 11545 u8 reserved_at_20[0x10]; 11546 u8 op_mod[0x10]; 11547 11548 u8 other_vport[0x1]; 11549 u8 reserved_at_41[0xf]; 11550 u8 vport_number[0x10]; 11551 11552 u8 reserved_at_60[0x20]; 11553 11554 u8 table_type[0x8]; 11555 u8 reserved_at_88[0x7]; 11556 u8 table_of_other_vport[0x1]; 11557 u8 table_vport_number[0x10]; 11558 11559 u8 reserved_at_a0[0x8]; 11560 u8 table_id[0x18]; 11561 11562 u8 reserved_at_c0[0x8]; 11563 u8 underlay_qpn[0x18]; 11564 u8 table_eswitch_owner_vhca_id_valid[0x1]; 11565 u8 reserved_at_e1[0xf]; 11566 u8 table_eswitch_owner_vhca_id[0x10]; 11567 u8 reserved_at_100[0x100]; 11568 }; 11569 11570 enum { 11571 MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = (1UL << 0), 11572 MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15), 11573 }; 11574 11575 struct mlx5_ifc_modify_flow_table_out_bits { 11576 u8 status[0x8]; 11577 u8 reserved_at_8[0x18]; 11578 11579 u8 syndrome[0x20]; 11580 11581 u8 reserved_at_40[0x40]; 11582 }; 11583 11584 struct mlx5_ifc_modify_flow_table_in_bits { 11585 u8 opcode[0x10]; 11586 u8 reserved_at_10[0x10]; 11587 11588 u8 reserved_at_20[0x10]; 11589 u8 op_mod[0x10]; 11590 11591 u8 other_vport[0x1]; 11592 u8 reserved_at_41[0xf]; 11593 u8 vport_number[0x10]; 11594 11595 u8 reserved_at_60[0x10]; 11596 u8 modify_field_select[0x10]; 11597 11598 u8 table_type[0x8]; 11599 u8 reserved_at_88[0x18]; 11600 11601 u8 reserved_at_a0[0x8]; 11602 u8 table_id[0x18]; 11603 11604 struct mlx5_ifc_flow_table_context_bits flow_table_context; 11605 }; 11606 11607 struct mlx5_ifc_ets_tcn_config_reg_bits { 11608 u8 g[0x1]; 11609 u8 b[0x1]; 11610 u8 r[0x1]; 11611 u8 reserved_at_3[0x9]; 11612 u8 group[0x4]; 11613 u8 reserved_at_10[0x9]; 11614 u8 bw_allocation[0x7]; 11615 11616 u8 reserved_at_20[0xc]; 11617 u8 max_bw_units[0x4]; 11618 u8 reserved_at_30[0x8]; 11619 u8 max_bw_value[0x8]; 11620 }; 11621 11622 struct mlx5_ifc_ets_global_config_reg_bits { 11623 u8 reserved_at_0[0x2]; 11624 u8 r[0x1]; 11625 u8 reserved_at_3[0x1d]; 11626 11627 u8 reserved_at_20[0xc]; 11628 u8 max_bw_units[0x4]; 11629 u8 reserved_at_30[0x8]; 11630 u8 max_bw_value[0x8]; 11631 }; 11632 11633 struct mlx5_ifc_qetc_reg_bits { 11634 u8 reserved_at_0[0x8]; 11635 u8 port_number[0x8]; 11636 u8 reserved_at_10[0x30]; 11637 11638 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8]; 11639 struct mlx5_ifc_ets_global_config_reg_bits global_configuration; 11640 }; 11641 11642 struct mlx5_ifc_qpdpm_dscp_reg_bits { 11643 u8 e[0x1]; 11644 u8 reserved_at_01[0x0b]; 11645 u8 prio[0x04]; 11646 }; 11647 11648 struct mlx5_ifc_qpdpm_reg_bits { 11649 u8 reserved_at_0[0x8]; 11650 u8 local_port[0x8]; 11651 u8 reserved_at_10[0x10]; 11652 struct mlx5_ifc_qpdpm_dscp_reg_bits dscp[64]; 11653 }; 11654 11655 struct mlx5_ifc_qpts_reg_bits { 11656 u8 reserved_at_0[0x8]; 11657 u8 local_port[0x8]; 11658 u8 reserved_at_10[0x2d]; 11659 u8 trust_state[0x3]; 11660 }; 11661 11662 struct mlx5_ifc_pptb_reg_bits { 11663 u8 reserved_at_0[0x2]; 11664 u8 mm[0x2]; 11665 u8 reserved_at_4[0x4]; 11666 u8 local_port[0x8]; 11667 u8 reserved_at_10[0x6]; 11668 u8 cm[0x1]; 11669 u8 um[0x1]; 11670 u8 pm[0x8]; 11671 11672 u8 prio_x_buff[0x20]; 11673 11674 u8 pm_msb[0x8]; 11675 u8 reserved_at_48[0x10]; 11676 u8 ctrl_buff[0x4]; 11677 u8 untagged_buff[0x4]; 11678 }; 11679 11680 struct mlx5_ifc_sbcam_reg_bits { 11681 u8 reserved_at_0[0x8]; 11682 u8 feature_group[0x8]; 11683 u8 reserved_at_10[0x8]; 11684 u8 access_reg_group[0x8]; 11685 11686 u8 reserved_at_20[0x20]; 11687 11688 u8 sb_access_reg_cap_mask[4][0x20]; 11689 11690 u8 reserved_at_c0[0x80]; 11691 11692 u8 sb_feature_cap_mask[4][0x20]; 11693 11694 u8 reserved_at_1c0[0x40]; 11695 11696 u8 cap_total_buffer_size[0x20]; 11697 11698 u8 cap_cell_size[0x10]; 11699 u8 cap_max_pg_buffers[0x8]; 11700 u8 cap_num_pool_supported[0x8]; 11701 11702 u8 reserved_at_240[0x8]; 11703 u8 cap_sbsr_stat_size[0x8]; 11704 u8 cap_max_tclass_data[0x8]; 11705 u8 cap_max_cpu_ingress_tclass_sb[0x8]; 11706 }; 11707 11708 struct mlx5_ifc_pbmc_reg_bits { 11709 u8 reserved_at_0[0x8]; 11710 u8 local_port[0x8]; 11711 u8 reserved_at_10[0x10]; 11712 11713 u8 xoff_timer_value[0x10]; 11714 u8 xoff_refresh[0x10]; 11715 11716 u8 reserved_at_40[0x9]; 11717 u8 fullness_threshold[0x7]; 11718 u8 port_buffer_size[0x10]; 11719 11720 struct mlx5_ifc_bufferx_reg_bits buffer[10]; 11721 11722 u8 reserved_at_2e0[0x80]; 11723 }; 11724 11725 struct mlx5_ifc_sbpr_reg_bits { 11726 u8 desc[0x1]; 11727 u8 snap[0x1]; 11728 u8 reserved_at_2[0x4]; 11729 u8 dir[0x2]; 11730 u8 reserved_at_8[0x14]; 11731 u8 pool[0x4]; 11732 11733 u8 infi_size[0x1]; 11734 u8 reserved_at_21[0x7]; 11735 u8 size[0x18]; 11736 11737 u8 reserved_at_40[0x1c]; 11738 u8 mode[0x4]; 11739 11740 u8 reserved_at_60[0x8]; 11741 u8 buff_occupancy[0x18]; 11742 11743 u8 clr[0x1]; 11744 u8 reserved_at_81[0x7]; 11745 u8 max_buff_occupancy[0x18]; 11746 11747 u8 reserved_at_a0[0x8]; 11748 u8 ext_buff_occupancy[0x18]; 11749 }; 11750 11751 struct mlx5_ifc_sbcm_reg_bits { 11752 u8 desc[0x1]; 11753 u8 snap[0x1]; 11754 u8 reserved_at_2[0x6]; 11755 u8 local_port[0x8]; 11756 u8 pnat[0x2]; 11757 u8 pg_buff[0x6]; 11758 u8 reserved_at_18[0x6]; 11759 u8 dir[0x2]; 11760 11761 u8 reserved_at_20[0x1f]; 11762 u8 exc[0x1]; 11763 11764 u8 reserved_at_40[0x40]; 11765 11766 u8 reserved_at_80[0x8]; 11767 u8 buff_occupancy[0x18]; 11768 11769 u8 clr[0x1]; 11770 u8 reserved_at_a1[0x7]; 11771 u8 max_buff_occupancy[0x18]; 11772 11773 u8 reserved_at_c0[0x8]; 11774 u8 min_buff[0x18]; 11775 11776 u8 infi_max[0x1]; 11777 u8 reserved_at_e1[0x7]; 11778 u8 max_buff[0x18]; 11779 11780 u8 reserved_at_100[0x20]; 11781 11782 u8 reserved_at_120[0x1c]; 11783 u8 pool[0x4]; 11784 }; 11785 11786 struct mlx5_ifc_qtct_reg_bits { 11787 u8 reserved_at_0[0x8]; 11788 u8 port_number[0x8]; 11789 u8 reserved_at_10[0xd]; 11790 u8 prio[0x3]; 11791 11792 u8 reserved_at_20[0x1d]; 11793 u8 tclass[0x3]; 11794 }; 11795 11796 struct mlx5_ifc_mcia_reg_bits { 11797 u8 l[0x1]; 11798 u8 reserved_at_1[0x7]; 11799 u8 module[0x8]; 11800 u8 reserved_at_10[0x8]; 11801 u8 status[0x8]; 11802 11803 u8 i2c_device_address[0x8]; 11804 u8 page_number[0x8]; 11805 u8 device_address[0x10]; 11806 11807 u8 reserved_at_40[0x10]; 11808 u8 size[0x10]; 11809 11810 u8 reserved_at_60[0x20]; 11811 11812 u8 dword_0[0x20]; 11813 u8 dword_1[0x20]; 11814 u8 dword_2[0x20]; 11815 u8 dword_3[0x20]; 11816 u8 dword_4[0x20]; 11817 u8 dword_5[0x20]; 11818 u8 dword_6[0x20]; 11819 u8 dword_7[0x20]; 11820 u8 dword_8[0x20]; 11821 u8 dword_9[0x20]; 11822 u8 dword_10[0x20]; 11823 u8 dword_11[0x20]; 11824 }; 11825 11826 struct mlx5_ifc_dcbx_param_bits { 11827 u8 dcbx_cee_cap[0x1]; 11828 u8 dcbx_ieee_cap[0x1]; 11829 u8 dcbx_standby_cap[0x1]; 11830 u8 reserved_at_3[0x5]; 11831 u8 port_number[0x8]; 11832 u8 reserved_at_10[0xa]; 11833 u8 max_application_table_size[6]; 11834 u8 reserved_at_20[0x15]; 11835 u8 version_oper[0x3]; 11836 u8 reserved_at_38[5]; 11837 u8 version_admin[0x3]; 11838 u8 willing_admin[0x1]; 11839 u8 reserved_at_41[0x3]; 11840 u8 pfc_cap_oper[0x4]; 11841 u8 reserved_at_48[0x4]; 11842 u8 pfc_cap_admin[0x4]; 11843 u8 reserved_at_50[0x4]; 11844 u8 num_of_tc_oper[0x4]; 11845 u8 reserved_at_58[0x4]; 11846 u8 num_of_tc_admin[0x4]; 11847 u8 remote_willing[0x1]; 11848 u8 reserved_at_61[3]; 11849 u8 remote_pfc_cap[4]; 11850 u8 reserved_at_68[0x14]; 11851 u8 remote_num_of_tc[0x4]; 11852 u8 reserved_at_80[0x18]; 11853 u8 error[0x8]; 11854 u8 reserved_at_a0[0x160]; 11855 }; 11856 11857 enum { 11858 MLX5_LAG_PORT_SELECT_MODE_QUEUE_AFFINITY = 0, 11859 MLX5_LAG_PORT_SELECT_MODE_PORT_SELECT_FT = 1, 11860 MLX5_LAG_PORT_SELECT_MODE_PORT_SELECT_MPESW = 2, 11861 }; 11862 11863 struct mlx5_ifc_lagc_bits { 11864 u8 fdb_selection_mode[0x1]; 11865 u8 reserved_at_1[0x14]; 11866 u8 port_select_mode[0x3]; 11867 u8 reserved_at_18[0x5]; 11868 u8 lag_state[0x3]; 11869 11870 u8 reserved_at_20[0xc]; 11871 u8 active_port[0x4]; 11872 u8 reserved_at_30[0x4]; 11873 u8 tx_remap_affinity_2[0x4]; 11874 u8 reserved_at_38[0x4]; 11875 u8 tx_remap_affinity_1[0x4]; 11876 }; 11877 11878 struct mlx5_ifc_create_lag_out_bits { 11879 u8 status[0x8]; 11880 u8 reserved_at_8[0x18]; 11881 11882 u8 syndrome[0x20]; 11883 11884 u8 reserved_at_40[0x40]; 11885 }; 11886 11887 struct mlx5_ifc_create_lag_in_bits { 11888 u8 opcode[0x10]; 11889 u8 reserved_at_10[0x10]; 11890 11891 u8 reserved_at_20[0x10]; 11892 u8 op_mod[0x10]; 11893 11894 struct mlx5_ifc_lagc_bits ctx; 11895 }; 11896 11897 struct mlx5_ifc_modify_lag_out_bits { 11898 u8 status[0x8]; 11899 u8 reserved_at_8[0x18]; 11900 11901 u8 syndrome[0x20]; 11902 11903 u8 reserved_at_40[0x40]; 11904 }; 11905 11906 struct mlx5_ifc_modify_lag_in_bits { 11907 u8 opcode[0x10]; 11908 u8 reserved_at_10[0x10]; 11909 11910 u8 reserved_at_20[0x10]; 11911 u8 op_mod[0x10]; 11912 11913 u8 reserved_at_40[0x20]; 11914 u8 field_select[0x20]; 11915 11916 struct mlx5_ifc_lagc_bits ctx; 11917 }; 11918 11919 struct mlx5_ifc_query_lag_out_bits { 11920 u8 status[0x8]; 11921 u8 reserved_at_8[0x18]; 11922 11923 u8 syndrome[0x20]; 11924 11925 struct mlx5_ifc_lagc_bits ctx; 11926 }; 11927 11928 struct mlx5_ifc_query_lag_in_bits { 11929 u8 opcode[0x10]; 11930 u8 reserved_at_10[0x10]; 11931 11932 u8 reserved_at_20[0x10]; 11933 u8 op_mod[0x10]; 11934 11935 u8 reserved_at_40[0x40]; 11936 }; 11937 11938 struct mlx5_ifc_destroy_lag_out_bits { 11939 u8 status[0x8]; 11940 u8 reserved_at_8[0x18]; 11941 11942 u8 syndrome[0x20]; 11943 11944 u8 reserved_at_40[0x40]; 11945 }; 11946 11947 struct mlx5_ifc_destroy_lag_in_bits { 11948 u8 opcode[0x10]; 11949 u8 reserved_at_10[0x10]; 11950 11951 u8 reserved_at_20[0x10]; 11952 u8 op_mod[0x10]; 11953 11954 u8 reserved_at_40[0x40]; 11955 }; 11956 11957 struct mlx5_ifc_create_vport_lag_out_bits { 11958 u8 status[0x8]; 11959 u8 reserved_at_8[0x18]; 11960 11961 u8 syndrome[0x20]; 11962 11963 u8 reserved_at_40[0x40]; 11964 }; 11965 11966 struct mlx5_ifc_create_vport_lag_in_bits { 11967 u8 opcode[0x10]; 11968 u8 reserved_at_10[0x10]; 11969 11970 u8 reserved_at_20[0x10]; 11971 u8 op_mod[0x10]; 11972 11973 u8 reserved_at_40[0x40]; 11974 }; 11975 11976 struct mlx5_ifc_destroy_vport_lag_out_bits { 11977 u8 status[0x8]; 11978 u8 reserved_at_8[0x18]; 11979 11980 u8 syndrome[0x20]; 11981 11982 u8 reserved_at_40[0x40]; 11983 }; 11984 11985 struct mlx5_ifc_destroy_vport_lag_in_bits { 11986 u8 opcode[0x10]; 11987 u8 reserved_at_10[0x10]; 11988 11989 u8 reserved_at_20[0x10]; 11990 u8 op_mod[0x10]; 11991 11992 u8 reserved_at_40[0x40]; 11993 }; 11994 11995 enum { 11996 MLX5_MODIFY_MEMIC_OP_MOD_ALLOC, 11997 MLX5_MODIFY_MEMIC_OP_MOD_DEALLOC, 11998 }; 11999 12000 struct mlx5_ifc_modify_memic_in_bits { 12001 u8 opcode[0x10]; 12002 u8 uid[0x10]; 12003 12004 u8 reserved_at_20[0x10]; 12005 u8 op_mod[0x10]; 12006 12007 u8 reserved_at_40[0x20]; 12008 12009 u8 reserved_at_60[0x18]; 12010 u8 memic_operation_type[0x8]; 12011 12012 u8 memic_start_addr[0x40]; 12013 12014 u8 reserved_at_c0[0x140]; 12015 }; 12016 12017 struct mlx5_ifc_modify_memic_out_bits { 12018 u8 status[0x8]; 12019 u8 reserved_at_8[0x18]; 12020 12021 u8 syndrome[0x20]; 12022 12023 u8 reserved_at_40[0x40]; 12024 12025 u8 memic_operation_addr[0x40]; 12026 12027 u8 reserved_at_c0[0x140]; 12028 }; 12029 12030 struct mlx5_ifc_alloc_memic_in_bits { 12031 u8 opcode[0x10]; 12032 u8 reserved_at_10[0x10]; 12033 12034 u8 reserved_at_20[0x10]; 12035 u8 op_mod[0x10]; 12036 12037 u8 reserved_at_30[0x20]; 12038 12039 u8 reserved_at_40[0x18]; 12040 u8 log_memic_addr_alignment[0x8]; 12041 12042 u8 range_start_addr[0x40]; 12043 12044 u8 range_size[0x20]; 12045 12046 u8 memic_size[0x20]; 12047 }; 12048 12049 struct mlx5_ifc_alloc_memic_out_bits { 12050 u8 status[0x8]; 12051 u8 reserved_at_8[0x18]; 12052 12053 u8 syndrome[0x20]; 12054 12055 u8 memic_start_addr[0x40]; 12056 }; 12057 12058 struct mlx5_ifc_dealloc_memic_in_bits { 12059 u8 opcode[0x10]; 12060 u8 reserved_at_10[0x10]; 12061 12062 u8 reserved_at_20[0x10]; 12063 u8 op_mod[0x10]; 12064 12065 u8 reserved_at_40[0x40]; 12066 12067 u8 memic_start_addr[0x40]; 12068 12069 u8 memic_size[0x20]; 12070 12071 u8 reserved_at_e0[0x20]; 12072 }; 12073 12074 struct mlx5_ifc_dealloc_memic_out_bits { 12075 u8 status[0x8]; 12076 u8 reserved_at_8[0x18]; 12077 12078 u8 syndrome[0x20]; 12079 12080 u8 reserved_at_40[0x40]; 12081 }; 12082 12083 struct mlx5_ifc_umem_bits { 12084 u8 reserved_at_0[0x80]; 12085 12086 u8 ats[0x1]; 12087 u8 reserved_at_81[0x1a]; 12088 u8 log_page_size[0x5]; 12089 12090 u8 page_offset[0x20]; 12091 12092 u8 num_of_mtt[0x40]; 12093 12094 struct mlx5_ifc_mtt_bits mtt[]; 12095 }; 12096 12097 struct mlx5_ifc_uctx_bits { 12098 u8 cap[0x20]; 12099 12100 u8 reserved_at_20[0x160]; 12101 }; 12102 12103 struct mlx5_ifc_sw_icm_bits { 12104 u8 modify_field_select[0x40]; 12105 12106 u8 reserved_at_40[0x18]; 12107 u8 log_sw_icm_size[0x8]; 12108 12109 u8 reserved_at_60[0x20]; 12110 12111 u8 sw_icm_start_addr[0x40]; 12112 12113 u8 reserved_at_c0[0x140]; 12114 }; 12115 12116 struct mlx5_ifc_geneve_tlv_option_bits { 12117 u8 modify_field_select[0x40]; 12118 12119 u8 reserved_at_40[0x18]; 12120 u8 geneve_option_fte_index[0x8]; 12121 12122 u8 option_class[0x10]; 12123 u8 option_type[0x8]; 12124 u8 reserved_at_78[0x3]; 12125 u8 option_data_length[0x5]; 12126 12127 u8 reserved_at_80[0x180]; 12128 }; 12129 12130 struct mlx5_ifc_create_umem_in_bits { 12131 u8 opcode[0x10]; 12132 u8 uid[0x10]; 12133 12134 u8 reserved_at_20[0x10]; 12135 u8 op_mod[0x10]; 12136 12137 u8 reserved_at_40[0x40]; 12138 12139 struct mlx5_ifc_umem_bits umem; 12140 }; 12141 12142 struct mlx5_ifc_create_umem_out_bits { 12143 u8 status[0x8]; 12144 u8 reserved_at_8[0x18]; 12145 12146 u8 syndrome[0x20]; 12147 12148 u8 reserved_at_40[0x8]; 12149 u8 umem_id[0x18]; 12150 12151 u8 reserved_at_60[0x20]; 12152 }; 12153 12154 struct mlx5_ifc_destroy_umem_in_bits { 12155 u8 opcode[0x10]; 12156 u8 uid[0x10]; 12157 12158 u8 reserved_at_20[0x10]; 12159 u8 op_mod[0x10]; 12160 12161 u8 reserved_at_40[0x8]; 12162 u8 umem_id[0x18]; 12163 12164 u8 reserved_at_60[0x20]; 12165 }; 12166 12167 struct mlx5_ifc_destroy_umem_out_bits { 12168 u8 status[0x8]; 12169 u8 reserved_at_8[0x18]; 12170 12171 u8 syndrome[0x20]; 12172 12173 u8 reserved_at_40[0x40]; 12174 }; 12175 12176 struct mlx5_ifc_create_uctx_in_bits { 12177 u8 opcode[0x10]; 12178 u8 reserved_at_10[0x10]; 12179 12180 u8 reserved_at_20[0x10]; 12181 u8 op_mod[0x10]; 12182 12183 u8 reserved_at_40[0x40]; 12184 12185 struct mlx5_ifc_uctx_bits uctx; 12186 }; 12187 12188 struct mlx5_ifc_create_uctx_out_bits { 12189 u8 status[0x8]; 12190 u8 reserved_at_8[0x18]; 12191 12192 u8 syndrome[0x20]; 12193 12194 u8 reserved_at_40[0x10]; 12195 u8 uid[0x10]; 12196 12197 u8 reserved_at_60[0x20]; 12198 }; 12199 12200 struct mlx5_ifc_destroy_uctx_in_bits { 12201 u8 opcode[0x10]; 12202 u8 reserved_at_10[0x10]; 12203 12204 u8 reserved_at_20[0x10]; 12205 u8 op_mod[0x10]; 12206 12207 u8 reserved_at_40[0x10]; 12208 u8 uid[0x10]; 12209 12210 u8 reserved_at_60[0x20]; 12211 }; 12212 12213 struct mlx5_ifc_destroy_uctx_out_bits { 12214 u8 status[0x8]; 12215 u8 reserved_at_8[0x18]; 12216 12217 u8 syndrome[0x20]; 12218 12219 u8 reserved_at_40[0x40]; 12220 }; 12221 12222 struct mlx5_ifc_create_sw_icm_in_bits { 12223 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 12224 struct mlx5_ifc_sw_icm_bits sw_icm; 12225 }; 12226 12227 struct mlx5_ifc_create_geneve_tlv_option_in_bits { 12228 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 12229 struct mlx5_ifc_geneve_tlv_option_bits geneve_tlv_opt; 12230 }; 12231 12232 struct mlx5_ifc_mtrc_string_db_param_bits { 12233 u8 string_db_base_address[0x20]; 12234 12235 u8 reserved_at_20[0x8]; 12236 u8 string_db_size[0x18]; 12237 }; 12238 12239 struct mlx5_ifc_mtrc_cap_bits { 12240 u8 trace_owner[0x1]; 12241 u8 trace_to_memory[0x1]; 12242 u8 reserved_at_2[0x4]; 12243 u8 trc_ver[0x2]; 12244 u8 reserved_at_8[0x14]; 12245 u8 num_string_db[0x4]; 12246 12247 u8 first_string_trace[0x8]; 12248 u8 num_string_trace[0x8]; 12249 u8 reserved_at_30[0x28]; 12250 12251 u8 log_max_trace_buffer_size[0x8]; 12252 12253 u8 reserved_at_60[0x20]; 12254 12255 struct mlx5_ifc_mtrc_string_db_param_bits string_db_param[8]; 12256 12257 u8 reserved_at_280[0x180]; 12258 }; 12259 12260 struct mlx5_ifc_mtrc_conf_bits { 12261 u8 reserved_at_0[0x1c]; 12262 u8 trace_mode[0x4]; 12263 u8 reserved_at_20[0x18]; 12264 u8 log_trace_buffer_size[0x8]; 12265 u8 trace_mkey[0x20]; 12266 u8 reserved_at_60[0x3a0]; 12267 }; 12268 12269 struct mlx5_ifc_mtrc_stdb_bits { 12270 u8 string_db_index[0x4]; 12271 u8 reserved_at_4[0x4]; 12272 u8 read_size[0x18]; 12273 u8 start_offset[0x20]; 12274 u8 string_db_data[]; 12275 }; 12276 12277 struct mlx5_ifc_mtrc_ctrl_bits { 12278 u8 trace_status[0x2]; 12279 u8 reserved_at_2[0x2]; 12280 u8 arm_event[0x1]; 12281 u8 reserved_at_5[0xb]; 12282 u8 modify_field_select[0x10]; 12283 u8 reserved_at_20[0x2b]; 12284 u8 current_timestamp52_32[0x15]; 12285 u8 current_timestamp31_0[0x20]; 12286 u8 reserved_at_80[0x180]; 12287 }; 12288 12289 struct mlx5_ifc_host_params_context_bits { 12290 u8 host_number[0x8]; 12291 u8 reserved_at_8[0x7]; 12292 u8 host_pf_disabled[0x1]; 12293 u8 host_num_of_vfs[0x10]; 12294 12295 u8 host_total_vfs[0x10]; 12296 u8 host_pci_bus[0x10]; 12297 12298 u8 reserved_at_40[0x10]; 12299 u8 host_pci_device[0x10]; 12300 12301 u8 reserved_at_60[0x10]; 12302 u8 host_pci_function[0x10]; 12303 12304 u8 reserved_at_80[0x180]; 12305 }; 12306 12307 struct mlx5_ifc_query_esw_functions_in_bits { 12308 u8 opcode[0x10]; 12309 u8 reserved_at_10[0x10]; 12310 12311 u8 reserved_at_20[0x10]; 12312 u8 op_mod[0x10]; 12313 12314 u8 reserved_at_40[0x40]; 12315 }; 12316 12317 struct mlx5_ifc_query_esw_functions_out_bits { 12318 u8 status[0x8]; 12319 u8 reserved_at_8[0x18]; 12320 12321 u8 syndrome[0x20]; 12322 12323 u8 reserved_at_40[0x40]; 12324 12325 struct mlx5_ifc_host_params_context_bits host_params_context; 12326 12327 u8 reserved_at_280[0x180]; 12328 u8 host_sf_enable[][0x40]; 12329 }; 12330 12331 struct mlx5_ifc_sf_partition_bits { 12332 u8 reserved_at_0[0x10]; 12333 u8 log_num_sf[0x8]; 12334 u8 log_sf_bar_size[0x8]; 12335 }; 12336 12337 struct mlx5_ifc_query_sf_partitions_out_bits { 12338 u8 status[0x8]; 12339 u8 reserved_at_8[0x18]; 12340 12341 u8 syndrome[0x20]; 12342 12343 u8 reserved_at_40[0x18]; 12344 u8 num_sf_partitions[0x8]; 12345 12346 u8 reserved_at_60[0x20]; 12347 12348 struct mlx5_ifc_sf_partition_bits sf_partition[]; 12349 }; 12350 12351 struct mlx5_ifc_query_sf_partitions_in_bits { 12352 u8 opcode[0x10]; 12353 u8 reserved_at_10[0x10]; 12354 12355 u8 reserved_at_20[0x10]; 12356 u8 op_mod[0x10]; 12357 12358 u8 reserved_at_40[0x40]; 12359 }; 12360 12361 struct mlx5_ifc_dealloc_sf_out_bits { 12362 u8 status[0x8]; 12363 u8 reserved_at_8[0x18]; 12364 12365 u8 syndrome[0x20]; 12366 12367 u8 reserved_at_40[0x40]; 12368 }; 12369 12370 struct mlx5_ifc_dealloc_sf_in_bits { 12371 u8 opcode[0x10]; 12372 u8 reserved_at_10[0x10]; 12373 12374 u8 reserved_at_20[0x10]; 12375 u8 op_mod[0x10]; 12376 12377 u8 reserved_at_40[0x10]; 12378 u8 function_id[0x10]; 12379 12380 u8 reserved_at_60[0x20]; 12381 }; 12382 12383 struct mlx5_ifc_alloc_sf_out_bits { 12384 u8 status[0x8]; 12385 u8 reserved_at_8[0x18]; 12386 12387 u8 syndrome[0x20]; 12388 12389 u8 reserved_at_40[0x40]; 12390 }; 12391 12392 struct mlx5_ifc_alloc_sf_in_bits { 12393 u8 opcode[0x10]; 12394 u8 reserved_at_10[0x10]; 12395 12396 u8 reserved_at_20[0x10]; 12397 u8 op_mod[0x10]; 12398 12399 u8 reserved_at_40[0x10]; 12400 u8 function_id[0x10]; 12401 12402 u8 reserved_at_60[0x20]; 12403 }; 12404 12405 struct mlx5_ifc_affiliated_event_header_bits { 12406 u8 reserved_at_0[0x10]; 12407 u8 obj_type[0x10]; 12408 12409 u8 obj_id[0x20]; 12410 }; 12411 12412 enum { 12413 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = BIT_ULL(0xc), 12414 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_IPSEC = BIT_ULL(0x13), 12415 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_SAMPLER = BIT_ULL(0x20), 12416 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_FLOW_METER_ASO = BIT_ULL(0x24), 12417 }; 12418 12419 enum { 12420 MLX5_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = 0xc, 12421 MLX5_GENERAL_OBJECT_TYPES_IPSEC = 0x13, 12422 MLX5_GENERAL_OBJECT_TYPES_SAMPLER = 0x20, 12423 MLX5_GENERAL_OBJECT_TYPES_FLOW_METER_ASO = 0x24, 12424 MLX5_GENERAL_OBJECT_TYPES_MACSEC = 0x27, 12425 MLX5_GENERAL_OBJECT_TYPES_INT_KEK = 0x47, 12426 MLX5_GENERAL_OBJECT_TYPES_FLOW_TABLE_ALIAS = 0xff15, 12427 }; 12428 12429 enum { 12430 MLX5_IPSEC_OBJECT_ICV_LEN_16B, 12431 }; 12432 12433 enum { 12434 MLX5_IPSEC_ASO_REG_C_0_1 = 0x0, 12435 MLX5_IPSEC_ASO_REG_C_2_3 = 0x1, 12436 MLX5_IPSEC_ASO_REG_C_4_5 = 0x2, 12437 MLX5_IPSEC_ASO_REG_C_6_7 = 0x3, 12438 }; 12439 12440 enum { 12441 MLX5_IPSEC_ASO_MODE = 0x0, 12442 MLX5_IPSEC_ASO_REPLAY_PROTECTION = 0x1, 12443 MLX5_IPSEC_ASO_INC_SN = 0x2, 12444 }; 12445 12446 enum { 12447 MLX5_IPSEC_ASO_REPLAY_WIN_32BIT = 0x0, 12448 MLX5_IPSEC_ASO_REPLAY_WIN_64BIT = 0x1, 12449 MLX5_IPSEC_ASO_REPLAY_WIN_128BIT = 0x2, 12450 MLX5_IPSEC_ASO_REPLAY_WIN_256BIT = 0x3, 12451 }; 12452 12453 struct mlx5_ifc_ipsec_aso_bits { 12454 u8 valid[0x1]; 12455 u8 reserved_at_201[0x1]; 12456 u8 mode[0x2]; 12457 u8 window_sz[0x2]; 12458 u8 soft_lft_arm[0x1]; 12459 u8 hard_lft_arm[0x1]; 12460 u8 remove_flow_enable[0x1]; 12461 u8 esn_event_arm[0x1]; 12462 u8 reserved_at_20a[0x16]; 12463 12464 u8 remove_flow_pkt_cnt[0x20]; 12465 12466 u8 remove_flow_soft_lft[0x20]; 12467 12468 u8 reserved_at_260[0x80]; 12469 12470 u8 mode_parameter[0x20]; 12471 12472 u8 replay_protection_window[0x100]; 12473 }; 12474 12475 struct mlx5_ifc_ipsec_obj_bits { 12476 u8 modify_field_select[0x40]; 12477 u8 full_offload[0x1]; 12478 u8 reserved_at_41[0x1]; 12479 u8 esn_en[0x1]; 12480 u8 esn_overlap[0x1]; 12481 u8 reserved_at_44[0x2]; 12482 u8 icv_length[0x2]; 12483 u8 reserved_at_48[0x4]; 12484 u8 aso_return_reg[0x4]; 12485 u8 reserved_at_50[0x10]; 12486 12487 u8 esn_msb[0x20]; 12488 12489 u8 reserved_at_80[0x8]; 12490 u8 dekn[0x18]; 12491 12492 u8 salt[0x20]; 12493 12494 u8 implicit_iv[0x40]; 12495 12496 u8 reserved_at_100[0x8]; 12497 u8 ipsec_aso_access_pd[0x18]; 12498 u8 reserved_at_120[0xe0]; 12499 12500 struct mlx5_ifc_ipsec_aso_bits ipsec_aso; 12501 }; 12502 12503 struct mlx5_ifc_create_ipsec_obj_in_bits { 12504 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12505 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 12506 }; 12507 12508 enum { 12509 MLX5_MODIFY_IPSEC_BITMASK_ESN_OVERLAP = BIT(0), 12510 MLX5_MODIFY_IPSEC_BITMASK_ESN_MSB = BIT(1), 12511 }; 12512 12513 struct mlx5_ifc_query_ipsec_obj_out_bits { 12514 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 12515 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 12516 }; 12517 12518 struct mlx5_ifc_modify_ipsec_obj_in_bits { 12519 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12520 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 12521 }; 12522 12523 enum { 12524 MLX5_MACSEC_ASO_REPLAY_PROTECTION = 0x1, 12525 }; 12526 12527 enum { 12528 MLX5_MACSEC_ASO_REPLAY_WIN_32BIT = 0x0, 12529 MLX5_MACSEC_ASO_REPLAY_WIN_64BIT = 0x1, 12530 MLX5_MACSEC_ASO_REPLAY_WIN_128BIT = 0x2, 12531 MLX5_MACSEC_ASO_REPLAY_WIN_256BIT = 0x3, 12532 }; 12533 12534 #define MLX5_MACSEC_ASO_INC_SN 0x2 12535 #define MLX5_MACSEC_ASO_REG_C_4_5 0x2 12536 12537 struct mlx5_ifc_macsec_aso_bits { 12538 u8 valid[0x1]; 12539 u8 reserved_at_1[0x1]; 12540 u8 mode[0x2]; 12541 u8 window_size[0x2]; 12542 u8 soft_lifetime_arm[0x1]; 12543 u8 hard_lifetime_arm[0x1]; 12544 u8 remove_flow_enable[0x1]; 12545 u8 epn_event_arm[0x1]; 12546 u8 reserved_at_a[0x16]; 12547 12548 u8 remove_flow_packet_count[0x20]; 12549 12550 u8 remove_flow_soft_lifetime[0x20]; 12551 12552 u8 reserved_at_60[0x80]; 12553 12554 u8 mode_parameter[0x20]; 12555 12556 u8 replay_protection_window[8][0x20]; 12557 }; 12558 12559 struct mlx5_ifc_macsec_offload_obj_bits { 12560 u8 modify_field_select[0x40]; 12561 12562 u8 confidentiality_en[0x1]; 12563 u8 reserved_at_41[0x1]; 12564 u8 epn_en[0x1]; 12565 u8 epn_overlap[0x1]; 12566 u8 reserved_at_44[0x2]; 12567 u8 confidentiality_offset[0x2]; 12568 u8 reserved_at_48[0x4]; 12569 u8 aso_return_reg[0x4]; 12570 u8 reserved_at_50[0x10]; 12571 12572 u8 epn_msb[0x20]; 12573 12574 u8 reserved_at_80[0x8]; 12575 u8 dekn[0x18]; 12576 12577 u8 reserved_at_a0[0x20]; 12578 12579 u8 sci[0x40]; 12580 12581 u8 reserved_at_100[0x8]; 12582 u8 macsec_aso_access_pd[0x18]; 12583 12584 u8 reserved_at_120[0x60]; 12585 12586 u8 salt[3][0x20]; 12587 12588 u8 reserved_at_1e0[0x20]; 12589 12590 struct mlx5_ifc_macsec_aso_bits macsec_aso; 12591 }; 12592 12593 struct mlx5_ifc_create_macsec_obj_in_bits { 12594 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12595 struct mlx5_ifc_macsec_offload_obj_bits macsec_object; 12596 }; 12597 12598 struct mlx5_ifc_modify_macsec_obj_in_bits { 12599 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12600 struct mlx5_ifc_macsec_offload_obj_bits macsec_object; 12601 }; 12602 12603 enum { 12604 MLX5_MODIFY_MACSEC_BITMASK_EPN_OVERLAP = BIT(0), 12605 MLX5_MODIFY_MACSEC_BITMASK_EPN_MSB = BIT(1), 12606 }; 12607 12608 struct mlx5_ifc_query_macsec_obj_out_bits { 12609 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 12610 struct mlx5_ifc_macsec_offload_obj_bits macsec_object; 12611 }; 12612 12613 struct mlx5_ifc_wrapped_dek_bits { 12614 u8 gcm_iv[0x60]; 12615 12616 u8 reserved_at_60[0x20]; 12617 12618 u8 const0[0x1]; 12619 u8 key_size[0x1]; 12620 u8 reserved_at_82[0x2]; 12621 u8 key2_invalid[0x1]; 12622 u8 reserved_at_85[0x3]; 12623 u8 pd[0x18]; 12624 12625 u8 key_purpose[0x5]; 12626 u8 reserved_at_a5[0x13]; 12627 u8 kek_id[0x8]; 12628 12629 u8 reserved_at_c0[0x40]; 12630 12631 u8 key1[0x8][0x20]; 12632 12633 u8 key2[0x8][0x20]; 12634 12635 u8 reserved_at_300[0x40]; 12636 12637 u8 const1[0x1]; 12638 u8 reserved_at_341[0x1f]; 12639 12640 u8 reserved_at_360[0x20]; 12641 12642 u8 auth_tag[0x80]; 12643 }; 12644 12645 struct mlx5_ifc_encryption_key_obj_bits { 12646 u8 modify_field_select[0x40]; 12647 12648 u8 state[0x8]; 12649 u8 sw_wrapped[0x1]; 12650 u8 reserved_at_49[0xb]; 12651 u8 key_size[0x4]; 12652 u8 reserved_at_58[0x4]; 12653 u8 key_purpose[0x4]; 12654 12655 u8 reserved_at_60[0x8]; 12656 u8 pd[0x18]; 12657 12658 u8 reserved_at_80[0x100]; 12659 12660 u8 opaque[0x40]; 12661 12662 u8 reserved_at_1c0[0x40]; 12663 12664 u8 key[8][0x80]; 12665 12666 u8 sw_wrapped_dek[8][0x80]; 12667 12668 u8 reserved_at_a00[0x600]; 12669 }; 12670 12671 struct mlx5_ifc_create_encryption_key_in_bits { 12672 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12673 struct mlx5_ifc_encryption_key_obj_bits encryption_key_object; 12674 }; 12675 12676 struct mlx5_ifc_modify_encryption_key_in_bits { 12677 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12678 struct mlx5_ifc_encryption_key_obj_bits encryption_key_object; 12679 }; 12680 12681 enum { 12682 MLX5_FLOW_METER_MODE_BYTES_IP_LENGTH = 0x0, 12683 MLX5_FLOW_METER_MODE_BYTES_CALC_WITH_L2 = 0x1, 12684 MLX5_FLOW_METER_MODE_BYTES_CALC_WITH_L2_IPG = 0x2, 12685 MLX5_FLOW_METER_MODE_NUM_PACKETS = 0x3, 12686 }; 12687 12688 struct mlx5_ifc_flow_meter_parameters_bits { 12689 u8 valid[0x1]; 12690 u8 bucket_overflow[0x1]; 12691 u8 start_color[0x2]; 12692 u8 both_buckets_on_green[0x1]; 12693 u8 reserved_at_5[0x1]; 12694 u8 meter_mode[0x2]; 12695 u8 reserved_at_8[0x18]; 12696 12697 u8 reserved_at_20[0x20]; 12698 12699 u8 reserved_at_40[0x3]; 12700 u8 cbs_exponent[0x5]; 12701 u8 cbs_mantissa[0x8]; 12702 u8 reserved_at_50[0x3]; 12703 u8 cir_exponent[0x5]; 12704 u8 cir_mantissa[0x8]; 12705 12706 u8 reserved_at_60[0x20]; 12707 12708 u8 reserved_at_80[0x3]; 12709 u8 ebs_exponent[0x5]; 12710 u8 ebs_mantissa[0x8]; 12711 u8 reserved_at_90[0x3]; 12712 u8 eir_exponent[0x5]; 12713 u8 eir_mantissa[0x8]; 12714 12715 u8 reserved_at_a0[0x60]; 12716 }; 12717 12718 struct mlx5_ifc_flow_meter_aso_obj_bits { 12719 u8 modify_field_select[0x40]; 12720 12721 u8 reserved_at_40[0x40]; 12722 12723 u8 reserved_at_80[0x8]; 12724 u8 meter_aso_access_pd[0x18]; 12725 12726 u8 reserved_at_a0[0x160]; 12727 12728 struct mlx5_ifc_flow_meter_parameters_bits flow_meter_parameters[2]; 12729 }; 12730 12731 struct mlx5_ifc_create_flow_meter_aso_obj_in_bits { 12732 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 12733 struct mlx5_ifc_flow_meter_aso_obj_bits flow_meter_aso_obj; 12734 }; 12735 12736 struct mlx5_ifc_int_kek_obj_bits { 12737 u8 modify_field_select[0x40]; 12738 12739 u8 state[0x8]; 12740 u8 auto_gen[0x1]; 12741 u8 reserved_at_49[0xb]; 12742 u8 key_size[0x4]; 12743 u8 reserved_at_58[0x8]; 12744 12745 u8 reserved_at_60[0x8]; 12746 u8 pd[0x18]; 12747 12748 u8 reserved_at_80[0x180]; 12749 u8 key[8][0x80]; 12750 12751 u8 reserved_at_600[0x200]; 12752 }; 12753 12754 struct mlx5_ifc_create_int_kek_obj_in_bits { 12755 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12756 struct mlx5_ifc_int_kek_obj_bits int_kek_object; 12757 }; 12758 12759 struct mlx5_ifc_create_int_kek_obj_out_bits { 12760 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 12761 struct mlx5_ifc_int_kek_obj_bits int_kek_object; 12762 }; 12763 12764 struct mlx5_ifc_sampler_obj_bits { 12765 u8 modify_field_select[0x40]; 12766 12767 u8 table_type[0x8]; 12768 u8 level[0x8]; 12769 u8 reserved_at_50[0xf]; 12770 u8 ignore_flow_level[0x1]; 12771 12772 u8 sample_ratio[0x20]; 12773 12774 u8 reserved_at_80[0x8]; 12775 u8 sample_table_id[0x18]; 12776 12777 u8 reserved_at_a0[0x8]; 12778 u8 default_table_id[0x18]; 12779 12780 u8 sw_steering_icm_address_rx[0x40]; 12781 u8 sw_steering_icm_address_tx[0x40]; 12782 12783 u8 reserved_at_140[0xa0]; 12784 }; 12785 12786 struct mlx5_ifc_create_sampler_obj_in_bits { 12787 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12788 struct mlx5_ifc_sampler_obj_bits sampler_object; 12789 }; 12790 12791 struct mlx5_ifc_query_sampler_obj_out_bits { 12792 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 12793 struct mlx5_ifc_sampler_obj_bits sampler_object; 12794 }; 12795 12796 enum { 12797 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_128 = 0x0, 12798 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_256 = 0x1, 12799 }; 12800 12801 enum { 12802 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_PURPOSE_TLS = 0x1, 12803 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_PURPOSE_IPSEC = 0x2, 12804 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_PURPOSE_MACSEC = 0x4, 12805 }; 12806 12807 struct mlx5_ifc_tls_static_params_bits { 12808 u8 const_2[0x2]; 12809 u8 tls_version[0x4]; 12810 u8 const_1[0x2]; 12811 u8 reserved_at_8[0x14]; 12812 u8 encryption_standard[0x4]; 12813 12814 u8 reserved_at_20[0x20]; 12815 12816 u8 initial_record_number[0x40]; 12817 12818 u8 resync_tcp_sn[0x20]; 12819 12820 u8 gcm_iv[0x20]; 12821 12822 u8 implicit_iv[0x40]; 12823 12824 u8 reserved_at_100[0x8]; 12825 u8 dek_index[0x18]; 12826 12827 u8 reserved_at_120[0xe0]; 12828 }; 12829 12830 struct mlx5_ifc_tls_progress_params_bits { 12831 u8 next_record_tcp_sn[0x20]; 12832 12833 u8 hw_resync_tcp_sn[0x20]; 12834 12835 u8 record_tracker_state[0x2]; 12836 u8 auth_state[0x2]; 12837 u8 reserved_at_44[0x4]; 12838 u8 hw_offset_record_number[0x18]; 12839 }; 12840 12841 enum { 12842 MLX5_MTT_PERM_READ = 1 << 0, 12843 MLX5_MTT_PERM_WRITE = 1 << 1, 12844 MLX5_MTT_PERM_RW = MLX5_MTT_PERM_READ | MLX5_MTT_PERM_WRITE, 12845 }; 12846 12847 enum { 12848 MLX5_SUSPEND_VHCA_IN_OP_MOD_SUSPEND_INITIATOR = 0x0, 12849 MLX5_SUSPEND_VHCA_IN_OP_MOD_SUSPEND_RESPONDER = 0x1, 12850 }; 12851 12852 struct mlx5_ifc_suspend_vhca_in_bits { 12853 u8 opcode[0x10]; 12854 u8 uid[0x10]; 12855 12856 u8 reserved_at_20[0x10]; 12857 u8 op_mod[0x10]; 12858 12859 u8 reserved_at_40[0x10]; 12860 u8 vhca_id[0x10]; 12861 12862 u8 reserved_at_60[0x20]; 12863 }; 12864 12865 struct mlx5_ifc_suspend_vhca_out_bits { 12866 u8 status[0x8]; 12867 u8 reserved_at_8[0x18]; 12868 12869 u8 syndrome[0x20]; 12870 12871 u8 reserved_at_40[0x40]; 12872 }; 12873 12874 enum { 12875 MLX5_RESUME_VHCA_IN_OP_MOD_RESUME_RESPONDER = 0x0, 12876 MLX5_RESUME_VHCA_IN_OP_MOD_RESUME_INITIATOR = 0x1, 12877 }; 12878 12879 struct mlx5_ifc_resume_vhca_in_bits { 12880 u8 opcode[0x10]; 12881 u8 uid[0x10]; 12882 12883 u8 reserved_at_20[0x10]; 12884 u8 op_mod[0x10]; 12885 12886 u8 reserved_at_40[0x10]; 12887 u8 vhca_id[0x10]; 12888 12889 u8 reserved_at_60[0x20]; 12890 }; 12891 12892 struct mlx5_ifc_resume_vhca_out_bits { 12893 u8 status[0x8]; 12894 u8 reserved_at_8[0x18]; 12895 12896 u8 syndrome[0x20]; 12897 12898 u8 reserved_at_40[0x40]; 12899 }; 12900 12901 struct mlx5_ifc_query_vhca_migration_state_in_bits { 12902 u8 opcode[0x10]; 12903 u8 uid[0x10]; 12904 12905 u8 reserved_at_20[0x10]; 12906 u8 op_mod[0x10]; 12907 12908 u8 incremental[0x1]; 12909 u8 chunk[0x1]; 12910 u8 reserved_at_42[0xe]; 12911 u8 vhca_id[0x10]; 12912 12913 u8 reserved_at_60[0x20]; 12914 }; 12915 12916 struct mlx5_ifc_query_vhca_migration_state_out_bits { 12917 u8 status[0x8]; 12918 u8 reserved_at_8[0x18]; 12919 12920 u8 syndrome[0x20]; 12921 12922 u8 reserved_at_40[0x40]; 12923 12924 u8 required_umem_size[0x20]; 12925 12926 u8 reserved_at_a0[0x20]; 12927 12928 u8 remaining_total_size[0x40]; 12929 12930 u8 reserved_at_100[0x100]; 12931 }; 12932 12933 struct mlx5_ifc_save_vhca_state_in_bits { 12934 u8 opcode[0x10]; 12935 u8 uid[0x10]; 12936 12937 u8 reserved_at_20[0x10]; 12938 u8 op_mod[0x10]; 12939 12940 u8 incremental[0x1]; 12941 u8 set_track[0x1]; 12942 u8 reserved_at_42[0xe]; 12943 u8 vhca_id[0x10]; 12944 12945 u8 reserved_at_60[0x20]; 12946 12947 u8 va[0x40]; 12948 12949 u8 mkey[0x20]; 12950 12951 u8 size[0x20]; 12952 }; 12953 12954 struct mlx5_ifc_save_vhca_state_out_bits { 12955 u8 status[0x8]; 12956 u8 reserved_at_8[0x18]; 12957 12958 u8 syndrome[0x20]; 12959 12960 u8 actual_image_size[0x20]; 12961 12962 u8 next_required_umem_size[0x20]; 12963 }; 12964 12965 struct mlx5_ifc_load_vhca_state_in_bits { 12966 u8 opcode[0x10]; 12967 u8 uid[0x10]; 12968 12969 u8 reserved_at_20[0x10]; 12970 u8 op_mod[0x10]; 12971 12972 u8 reserved_at_40[0x10]; 12973 u8 vhca_id[0x10]; 12974 12975 u8 reserved_at_60[0x20]; 12976 12977 u8 va[0x40]; 12978 12979 u8 mkey[0x20]; 12980 12981 u8 size[0x20]; 12982 }; 12983 12984 struct mlx5_ifc_load_vhca_state_out_bits { 12985 u8 status[0x8]; 12986 u8 reserved_at_8[0x18]; 12987 12988 u8 syndrome[0x20]; 12989 12990 u8 reserved_at_40[0x40]; 12991 }; 12992 12993 struct mlx5_ifc_adv_virtualization_cap_bits { 12994 u8 reserved_at_0[0x3]; 12995 u8 pg_track_log_max_num[0x5]; 12996 u8 pg_track_max_num_range[0x8]; 12997 u8 pg_track_log_min_addr_space[0x8]; 12998 u8 pg_track_log_max_addr_space[0x8]; 12999 13000 u8 reserved_at_20[0x3]; 13001 u8 pg_track_log_min_msg_size[0x5]; 13002 u8 reserved_at_28[0x3]; 13003 u8 pg_track_log_max_msg_size[0x5]; 13004 u8 reserved_at_30[0x3]; 13005 u8 pg_track_log_min_page_size[0x5]; 13006 u8 reserved_at_38[0x3]; 13007 u8 pg_track_log_max_page_size[0x5]; 13008 13009 u8 reserved_at_40[0x7c0]; 13010 }; 13011 13012 struct mlx5_ifc_page_track_report_entry_bits { 13013 u8 dirty_address_high[0x20]; 13014 13015 u8 dirty_address_low[0x20]; 13016 }; 13017 13018 enum { 13019 MLX5_PAGE_TRACK_STATE_TRACKING, 13020 MLX5_PAGE_TRACK_STATE_REPORTING, 13021 MLX5_PAGE_TRACK_STATE_ERROR, 13022 }; 13023 13024 struct mlx5_ifc_page_track_range_bits { 13025 u8 start_address[0x40]; 13026 13027 u8 length[0x40]; 13028 }; 13029 13030 struct mlx5_ifc_page_track_bits { 13031 u8 modify_field_select[0x40]; 13032 13033 u8 reserved_at_40[0x10]; 13034 u8 vhca_id[0x10]; 13035 13036 u8 reserved_at_60[0x20]; 13037 13038 u8 state[0x4]; 13039 u8 track_type[0x4]; 13040 u8 log_addr_space_size[0x8]; 13041 u8 reserved_at_90[0x3]; 13042 u8 log_page_size[0x5]; 13043 u8 reserved_at_98[0x3]; 13044 u8 log_msg_size[0x5]; 13045 13046 u8 reserved_at_a0[0x8]; 13047 u8 reporting_qpn[0x18]; 13048 13049 u8 reserved_at_c0[0x18]; 13050 u8 num_ranges[0x8]; 13051 13052 u8 reserved_at_e0[0x20]; 13053 13054 u8 range_start_address[0x40]; 13055 13056 u8 length[0x40]; 13057 13058 struct mlx5_ifc_page_track_range_bits track_range[0]; 13059 }; 13060 13061 struct mlx5_ifc_create_page_track_obj_in_bits { 13062 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 13063 struct mlx5_ifc_page_track_bits obj_context; 13064 }; 13065 13066 struct mlx5_ifc_modify_page_track_obj_in_bits { 13067 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 13068 struct mlx5_ifc_page_track_bits obj_context; 13069 }; 13070 13071 struct mlx5_ifc_query_page_track_obj_out_bits { 13072 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 13073 struct mlx5_ifc_page_track_bits obj_context; 13074 }; 13075 13076 struct mlx5_ifc_msecq_reg_bits { 13077 u8 reserved_at_0[0x20]; 13078 13079 u8 reserved_at_20[0x12]; 13080 u8 network_option[0x2]; 13081 u8 local_ssm_code[0x4]; 13082 u8 local_enhanced_ssm_code[0x8]; 13083 13084 u8 local_clock_identity[0x40]; 13085 13086 u8 reserved_at_80[0x180]; 13087 }; 13088 13089 enum { 13090 MLX5_MSEES_FIELD_SELECT_ENABLE = BIT(0), 13091 MLX5_MSEES_FIELD_SELECT_ADMIN_STATUS = BIT(1), 13092 MLX5_MSEES_FIELD_SELECT_ADMIN_FREQ_MEASURE = BIT(2), 13093 }; 13094 13095 enum mlx5_msees_admin_status { 13096 MLX5_MSEES_ADMIN_STATUS_FREE_RUNNING = 0x0, 13097 MLX5_MSEES_ADMIN_STATUS_TRACK = 0x1, 13098 }; 13099 13100 enum mlx5_msees_oper_status { 13101 MLX5_MSEES_OPER_STATUS_FREE_RUNNING = 0x0, 13102 MLX5_MSEES_OPER_STATUS_SELF_TRACK = 0x1, 13103 MLX5_MSEES_OPER_STATUS_OTHER_TRACK = 0x2, 13104 MLX5_MSEES_OPER_STATUS_HOLDOVER = 0x3, 13105 MLX5_MSEES_OPER_STATUS_FAIL_HOLDOVER = 0x4, 13106 MLX5_MSEES_OPER_STATUS_FAIL_FREE_RUNNING = 0x5, 13107 }; 13108 13109 enum mlx5_msees_failure_reason { 13110 MLX5_MSEES_FAILURE_REASON_UNDEFINED_ERROR = 0x0, 13111 MLX5_MSEES_FAILURE_REASON_PORT_DOWN = 0x1, 13112 MLX5_MSEES_FAILURE_REASON_TOO_HIGH_FREQUENCY_DIFF = 0x2, 13113 MLX5_MSEES_FAILURE_REASON_NET_SYNCHRONIZER_DEVICE_ERROR = 0x3, 13114 MLX5_MSEES_FAILURE_REASON_LACK_OF_RESOURCES = 0x4, 13115 }; 13116 13117 struct mlx5_ifc_msees_reg_bits { 13118 u8 reserved_at_0[0x8]; 13119 u8 local_port[0x8]; 13120 u8 pnat[0x2]; 13121 u8 lp_msb[0x2]; 13122 u8 reserved_at_14[0xc]; 13123 13124 u8 field_select[0x20]; 13125 13126 u8 admin_status[0x4]; 13127 u8 oper_status[0x4]; 13128 u8 ho_acq[0x1]; 13129 u8 reserved_at_49[0xc]; 13130 u8 admin_freq_measure[0x1]; 13131 u8 oper_freq_measure[0x1]; 13132 u8 failure_reason[0x9]; 13133 13134 u8 frequency_diff[0x20]; 13135 13136 u8 reserved_at_80[0x180]; 13137 }; 13138 13139 #endif /* MLX5_IFC_H */ 13140