1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 #ifndef MLX5_IFC_H 33 #define MLX5_IFC_H 34 35 #include "mlx5_ifc_fpga.h" 36 37 enum { 38 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0, 39 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1, 40 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2, 41 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3, 42 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13, 43 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14, 44 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c, 45 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d, 46 MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4, 47 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5, 48 MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED = 0x7, 49 MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT = 0xc, 50 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10, 51 MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR = 0x11, 52 MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR = 0x12, 53 MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR = 0x8, 54 MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE = 0x9, 55 MLX5_EVENT_TYPE_CODING_GPIO_EVENT = 0x15, 56 MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19, 57 MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a, 58 MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT = 0x1b, 59 MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT = 0x1f, 60 MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa, 61 MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb, 62 MLX5_EVENT_TYPE_CODING_FPGA_ERROR = 0x20, 63 MLX5_EVENT_TYPE_CODING_FPGA_QP_ERROR = 0x21 64 }; 65 66 enum { 67 MLX5_MODIFY_TIR_BITMASK_LRO = 0x0, 68 MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE = 0x1, 69 MLX5_MODIFY_TIR_BITMASK_HASH = 0x2, 70 MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN = 0x3 71 }; 72 73 enum { 74 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0, 75 MLX5_SET_HCA_CAP_OP_MOD_ODP = 0x2, 76 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3, 77 MLX5_SET_HCA_CAP_OP_MOD_ROCE = 0x4, 78 }; 79 80 enum { 81 MLX5_SHARED_RESOURCE_UID = 0xffff, 82 }; 83 84 enum { 85 MLX5_OBJ_TYPE_SW_ICM = 0x0008, 86 }; 87 88 enum { 89 MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM = (1ULL << MLX5_OBJ_TYPE_SW_ICM), 90 MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT = (1ULL << 11), 91 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q = (1ULL << 13), 92 }; 93 94 enum { 95 MLX5_OBJ_TYPE_GENEVE_TLV_OPT = 0x000b, 96 MLX5_OBJ_TYPE_MKEY = 0xff01, 97 MLX5_OBJ_TYPE_QP = 0xff02, 98 MLX5_OBJ_TYPE_PSV = 0xff03, 99 MLX5_OBJ_TYPE_RMP = 0xff04, 100 MLX5_OBJ_TYPE_XRC_SRQ = 0xff05, 101 MLX5_OBJ_TYPE_RQ = 0xff06, 102 MLX5_OBJ_TYPE_SQ = 0xff07, 103 MLX5_OBJ_TYPE_TIR = 0xff08, 104 MLX5_OBJ_TYPE_TIS = 0xff09, 105 MLX5_OBJ_TYPE_DCT = 0xff0a, 106 MLX5_OBJ_TYPE_XRQ = 0xff0b, 107 MLX5_OBJ_TYPE_RQT = 0xff0e, 108 MLX5_OBJ_TYPE_FLOW_COUNTER = 0xff0f, 109 MLX5_OBJ_TYPE_CQ = 0xff10, 110 }; 111 112 enum { 113 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100, 114 MLX5_CMD_OP_QUERY_ADAPTER = 0x101, 115 MLX5_CMD_OP_INIT_HCA = 0x102, 116 MLX5_CMD_OP_TEARDOWN_HCA = 0x103, 117 MLX5_CMD_OP_ENABLE_HCA = 0x104, 118 MLX5_CMD_OP_DISABLE_HCA = 0x105, 119 MLX5_CMD_OP_QUERY_PAGES = 0x107, 120 MLX5_CMD_OP_MANAGE_PAGES = 0x108, 121 MLX5_CMD_OP_SET_HCA_CAP = 0x109, 122 MLX5_CMD_OP_QUERY_ISSI = 0x10a, 123 MLX5_CMD_OP_SET_ISSI = 0x10b, 124 MLX5_CMD_OP_SET_DRIVER_VERSION = 0x10d, 125 MLX5_CMD_OP_QUERY_SF_PARTITION = 0x111, 126 MLX5_CMD_OP_ALLOC_SF = 0x113, 127 MLX5_CMD_OP_DEALLOC_SF = 0x114, 128 MLX5_CMD_OP_CREATE_MKEY = 0x200, 129 MLX5_CMD_OP_QUERY_MKEY = 0x201, 130 MLX5_CMD_OP_DESTROY_MKEY = 0x202, 131 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203, 132 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204, 133 MLX5_CMD_OP_ALLOC_MEMIC = 0x205, 134 MLX5_CMD_OP_DEALLOC_MEMIC = 0x206, 135 MLX5_CMD_OP_CREATE_EQ = 0x301, 136 MLX5_CMD_OP_DESTROY_EQ = 0x302, 137 MLX5_CMD_OP_QUERY_EQ = 0x303, 138 MLX5_CMD_OP_GEN_EQE = 0x304, 139 MLX5_CMD_OP_CREATE_CQ = 0x400, 140 MLX5_CMD_OP_DESTROY_CQ = 0x401, 141 MLX5_CMD_OP_QUERY_CQ = 0x402, 142 MLX5_CMD_OP_MODIFY_CQ = 0x403, 143 MLX5_CMD_OP_CREATE_QP = 0x500, 144 MLX5_CMD_OP_DESTROY_QP = 0x501, 145 MLX5_CMD_OP_RST2INIT_QP = 0x502, 146 MLX5_CMD_OP_INIT2RTR_QP = 0x503, 147 MLX5_CMD_OP_RTR2RTS_QP = 0x504, 148 MLX5_CMD_OP_RTS2RTS_QP = 0x505, 149 MLX5_CMD_OP_SQERR2RTS_QP = 0x506, 150 MLX5_CMD_OP_2ERR_QP = 0x507, 151 MLX5_CMD_OP_2RST_QP = 0x50a, 152 MLX5_CMD_OP_QUERY_QP = 0x50b, 153 MLX5_CMD_OP_SQD_RTS_QP = 0x50c, 154 MLX5_CMD_OP_INIT2INIT_QP = 0x50e, 155 MLX5_CMD_OP_CREATE_PSV = 0x600, 156 MLX5_CMD_OP_DESTROY_PSV = 0x601, 157 MLX5_CMD_OP_CREATE_SRQ = 0x700, 158 MLX5_CMD_OP_DESTROY_SRQ = 0x701, 159 MLX5_CMD_OP_QUERY_SRQ = 0x702, 160 MLX5_CMD_OP_ARM_RQ = 0x703, 161 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705, 162 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706, 163 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707, 164 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708, 165 MLX5_CMD_OP_CREATE_DCT = 0x710, 166 MLX5_CMD_OP_DESTROY_DCT = 0x711, 167 MLX5_CMD_OP_DRAIN_DCT = 0x712, 168 MLX5_CMD_OP_QUERY_DCT = 0x713, 169 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714, 170 MLX5_CMD_OP_CREATE_XRQ = 0x717, 171 MLX5_CMD_OP_DESTROY_XRQ = 0x718, 172 MLX5_CMD_OP_QUERY_XRQ = 0x719, 173 MLX5_CMD_OP_ARM_XRQ = 0x71a, 174 MLX5_CMD_OP_QUERY_XRQ_DC_PARAMS_ENTRY = 0x725, 175 MLX5_CMD_OP_SET_XRQ_DC_PARAMS_ENTRY = 0x726, 176 MLX5_CMD_OP_QUERY_XRQ_ERROR_PARAMS = 0x727, 177 MLX5_CMD_OP_RELEASE_XRQ_ERROR = 0x729, 178 MLX5_CMD_OP_MODIFY_XRQ = 0x72a, 179 MLX5_CMD_OP_QUERY_ESW_FUNCTIONS = 0x740, 180 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750, 181 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751, 182 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752, 183 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753, 184 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754, 185 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755, 186 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760, 187 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761, 188 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762, 189 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763, 190 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764, 191 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765, 192 MLX5_CMD_OP_QUERY_VNIC_ENV = 0x76f, 193 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770, 194 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771, 195 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772, 196 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773, 197 MLX5_CMD_OP_SET_MONITOR_COUNTER = 0x774, 198 MLX5_CMD_OP_ARM_MONITOR_COUNTER = 0x775, 199 MLX5_CMD_OP_SET_PP_RATE_LIMIT = 0x780, 200 MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781, 201 MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT = 0x782, 202 MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT = 0x783, 203 MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT = 0x784, 204 MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT = 0x785, 205 MLX5_CMD_OP_CREATE_QOS_PARA_VPORT = 0x786, 206 MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT = 0x787, 207 MLX5_CMD_OP_ALLOC_PD = 0x800, 208 MLX5_CMD_OP_DEALLOC_PD = 0x801, 209 MLX5_CMD_OP_ALLOC_UAR = 0x802, 210 MLX5_CMD_OP_DEALLOC_UAR = 0x803, 211 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804, 212 MLX5_CMD_OP_ACCESS_REG = 0x805, 213 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806, 214 MLX5_CMD_OP_DETACH_FROM_MCG = 0x807, 215 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a, 216 MLX5_CMD_OP_MAD_IFC = 0x50d, 217 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b, 218 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c, 219 MLX5_CMD_OP_NOP = 0x80d, 220 MLX5_CMD_OP_ALLOC_XRCD = 0x80e, 221 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f, 222 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816, 223 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817, 224 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822, 225 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823, 226 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824, 227 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825, 228 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826, 229 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827, 230 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828, 231 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829, 232 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a, 233 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b, 234 MLX5_CMD_OP_SET_WOL_ROL = 0x830, 235 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831, 236 MLX5_CMD_OP_CREATE_LAG = 0x840, 237 MLX5_CMD_OP_MODIFY_LAG = 0x841, 238 MLX5_CMD_OP_QUERY_LAG = 0x842, 239 MLX5_CMD_OP_DESTROY_LAG = 0x843, 240 MLX5_CMD_OP_CREATE_VPORT_LAG = 0x844, 241 MLX5_CMD_OP_DESTROY_VPORT_LAG = 0x845, 242 MLX5_CMD_OP_CREATE_TIR = 0x900, 243 MLX5_CMD_OP_MODIFY_TIR = 0x901, 244 MLX5_CMD_OP_DESTROY_TIR = 0x902, 245 MLX5_CMD_OP_QUERY_TIR = 0x903, 246 MLX5_CMD_OP_CREATE_SQ = 0x904, 247 MLX5_CMD_OP_MODIFY_SQ = 0x905, 248 MLX5_CMD_OP_DESTROY_SQ = 0x906, 249 MLX5_CMD_OP_QUERY_SQ = 0x907, 250 MLX5_CMD_OP_CREATE_RQ = 0x908, 251 MLX5_CMD_OP_MODIFY_RQ = 0x909, 252 MLX5_CMD_OP_SET_DELAY_DROP_PARAMS = 0x910, 253 MLX5_CMD_OP_DESTROY_RQ = 0x90a, 254 MLX5_CMD_OP_QUERY_RQ = 0x90b, 255 MLX5_CMD_OP_CREATE_RMP = 0x90c, 256 MLX5_CMD_OP_MODIFY_RMP = 0x90d, 257 MLX5_CMD_OP_DESTROY_RMP = 0x90e, 258 MLX5_CMD_OP_QUERY_RMP = 0x90f, 259 MLX5_CMD_OP_CREATE_TIS = 0x912, 260 MLX5_CMD_OP_MODIFY_TIS = 0x913, 261 MLX5_CMD_OP_DESTROY_TIS = 0x914, 262 MLX5_CMD_OP_QUERY_TIS = 0x915, 263 MLX5_CMD_OP_CREATE_RQT = 0x916, 264 MLX5_CMD_OP_MODIFY_RQT = 0x917, 265 MLX5_CMD_OP_DESTROY_RQT = 0x918, 266 MLX5_CMD_OP_QUERY_RQT = 0x919, 267 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f, 268 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930, 269 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931, 270 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932, 271 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933, 272 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934, 273 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935, 274 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936, 275 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937, 276 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938, 277 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939, 278 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a, 279 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b, 280 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c, 281 MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT = 0x93d, 282 MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT = 0x93e, 283 MLX5_CMD_OP_QUERY_PACKET_REFORMAT_CONTEXT = 0x93f, 284 MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT = 0x940, 285 MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941, 286 MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT = 0x942, 287 MLX5_CMD_OP_FPGA_CREATE_QP = 0x960, 288 MLX5_CMD_OP_FPGA_MODIFY_QP = 0x961, 289 MLX5_CMD_OP_FPGA_QUERY_QP = 0x962, 290 MLX5_CMD_OP_FPGA_DESTROY_QP = 0x963, 291 MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS = 0x964, 292 MLX5_CMD_OP_CREATE_GENERAL_OBJECT = 0xa00, 293 MLX5_CMD_OP_MODIFY_GENERAL_OBJECT = 0xa01, 294 MLX5_CMD_OP_QUERY_GENERAL_OBJECT = 0xa02, 295 MLX5_CMD_OP_DESTROY_GENERAL_OBJECT = 0xa03, 296 MLX5_CMD_OP_CREATE_UCTX = 0xa04, 297 MLX5_CMD_OP_DESTROY_UCTX = 0xa06, 298 MLX5_CMD_OP_CREATE_UMEM = 0xa08, 299 MLX5_CMD_OP_DESTROY_UMEM = 0xa0a, 300 MLX5_CMD_OP_SYNC_STEERING = 0xb00, 301 MLX5_CMD_OP_MAX 302 }; 303 304 /* Valid range for general commands that don't work over an object */ 305 enum { 306 MLX5_CMD_OP_GENERAL_START = 0xb00, 307 MLX5_CMD_OP_GENERAL_END = 0xd00, 308 }; 309 310 struct mlx5_ifc_flow_table_fields_supported_bits { 311 u8 outer_dmac[0x1]; 312 u8 outer_smac[0x1]; 313 u8 outer_ether_type[0x1]; 314 u8 outer_ip_version[0x1]; 315 u8 outer_first_prio[0x1]; 316 u8 outer_first_cfi[0x1]; 317 u8 outer_first_vid[0x1]; 318 u8 outer_ipv4_ttl[0x1]; 319 u8 outer_second_prio[0x1]; 320 u8 outer_second_cfi[0x1]; 321 u8 outer_second_vid[0x1]; 322 u8 reserved_at_b[0x1]; 323 u8 outer_sip[0x1]; 324 u8 outer_dip[0x1]; 325 u8 outer_frag[0x1]; 326 u8 outer_ip_protocol[0x1]; 327 u8 outer_ip_ecn[0x1]; 328 u8 outer_ip_dscp[0x1]; 329 u8 outer_udp_sport[0x1]; 330 u8 outer_udp_dport[0x1]; 331 u8 outer_tcp_sport[0x1]; 332 u8 outer_tcp_dport[0x1]; 333 u8 outer_tcp_flags[0x1]; 334 u8 outer_gre_protocol[0x1]; 335 u8 outer_gre_key[0x1]; 336 u8 outer_vxlan_vni[0x1]; 337 u8 outer_geneve_vni[0x1]; 338 u8 outer_geneve_oam[0x1]; 339 u8 outer_geneve_protocol_type[0x1]; 340 u8 outer_geneve_opt_len[0x1]; 341 u8 reserved_at_1e[0x1]; 342 u8 source_eswitch_port[0x1]; 343 344 u8 inner_dmac[0x1]; 345 u8 inner_smac[0x1]; 346 u8 inner_ether_type[0x1]; 347 u8 inner_ip_version[0x1]; 348 u8 inner_first_prio[0x1]; 349 u8 inner_first_cfi[0x1]; 350 u8 inner_first_vid[0x1]; 351 u8 reserved_at_27[0x1]; 352 u8 inner_second_prio[0x1]; 353 u8 inner_second_cfi[0x1]; 354 u8 inner_second_vid[0x1]; 355 u8 reserved_at_2b[0x1]; 356 u8 inner_sip[0x1]; 357 u8 inner_dip[0x1]; 358 u8 inner_frag[0x1]; 359 u8 inner_ip_protocol[0x1]; 360 u8 inner_ip_ecn[0x1]; 361 u8 inner_ip_dscp[0x1]; 362 u8 inner_udp_sport[0x1]; 363 u8 inner_udp_dport[0x1]; 364 u8 inner_tcp_sport[0x1]; 365 u8 inner_tcp_dport[0x1]; 366 u8 inner_tcp_flags[0x1]; 367 u8 reserved_at_37[0x9]; 368 369 u8 geneve_tlv_option_0_data[0x1]; 370 u8 reserved_at_41[0x4]; 371 u8 outer_first_mpls_over_udp[0x4]; 372 u8 outer_first_mpls_over_gre[0x4]; 373 u8 inner_first_mpls[0x4]; 374 u8 outer_first_mpls[0x4]; 375 u8 reserved_at_55[0x2]; 376 u8 outer_esp_spi[0x1]; 377 u8 reserved_at_58[0x2]; 378 u8 bth_dst_qp[0x1]; 379 u8 reserved_at_5b[0x5]; 380 381 u8 reserved_at_60[0x18]; 382 u8 metadata_reg_c_7[0x1]; 383 u8 metadata_reg_c_6[0x1]; 384 u8 metadata_reg_c_5[0x1]; 385 u8 metadata_reg_c_4[0x1]; 386 u8 metadata_reg_c_3[0x1]; 387 u8 metadata_reg_c_2[0x1]; 388 u8 metadata_reg_c_1[0x1]; 389 u8 metadata_reg_c_0[0x1]; 390 }; 391 392 struct mlx5_ifc_flow_table_prop_layout_bits { 393 u8 ft_support[0x1]; 394 u8 reserved_at_1[0x1]; 395 u8 flow_counter[0x1]; 396 u8 flow_modify_en[0x1]; 397 u8 modify_root[0x1]; 398 u8 identified_miss_table_mode[0x1]; 399 u8 flow_table_modify[0x1]; 400 u8 reformat[0x1]; 401 u8 decap[0x1]; 402 u8 reserved_at_9[0x1]; 403 u8 pop_vlan[0x1]; 404 u8 push_vlan[0x1]; 405 u8 reserved_at_c[0x1]; 406 u8 pop_vlan_2[0x1]; 407 u8 push_vlan_2[0x1]; 408 u8 reformat_and_vlan_action[0x1]; 409 u8 reserved_at_10[0x1]; 410 u8 sw_owner[0x1]; 411 u8 reformat_l3_tunnel_to_l2[0x1]; 412 u8 reformat_l2_to_l3_tunnel[0x1]; 413 u8 reformat_and_modify_action[0x1]; 414 u8 ignore_flow_level[0x1]; 415 u8 reserved_at_16[0x1]; 416 u8 table_miss_action_domain[0x1]; 417 u8 termination_table[0x1]; 418 u8 reformat_and_fwd_to_table[0x1]; 419 u8 reserved_at_1a[0x6]; 420 u8 termination_table_raw_traffic[0x1]; 421 u8 reserved_at_21[0x1]; 422 u8 log_max_ft_size[0x6]; 423 u8 log_max_modify_header_context[0x8]; 424 u8 max_modify_header_actions[0x8]; 425 u8 max_ft_level[0x8]; 426 427 u8 reserved_at_40[0x20]; 428 429 u8 reserved_at_60[0x18]; 430 u8 log_max_ft_num[0x8]; 431 432 u8 reserved_at_80[0x18]; 433 u8 log_max_destination[0x8]; 434 435 u8 log_max_flow_counter[0x8]; 436 u8 reserved_at_a8[0x10]; 437 u8 log_max_flow[0x8]; 438 439 u8 reserved_at_c0[0x40]; 440 441 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support; 442 443 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support; 444 }; 445 446 struct mlx5_ifc_odp_per_transport_service_cap_bits { 447 u8 send[0x1]; 448 u8 receive[0x1]; 449 u8 write[0x1]; 450 u8 read[0x1]; 451 u8 atomic[0x1]; 452 u8 srq_receive[0x1]; 453 u8 reserved_at_6[0x1a]; 454 }; 455 456 struct mlx5_ifc_fte_match_set_lyr_2_4_bits { 457 u8 smac_47_16[0x20]; 458 459 u8 smac_15_0[0x10]; 460 u8 ethertype[0x10]; 461 462 u8 dmac_47_16[0x20]; 463 464 u8 dmac_15_0[0x10]; 465 u8 first_prio[0x3]; 466 u8 first_cfi[0x1]; 467 u8 first_vid[0xc]; 468 469 u8 ip_protocol[0x8]; 470 u8 ip_dscp[0x6]; 471 u8 ip_ecn[0x2]; 472 u8 cvlan_tag[0x1]; 473 u8 svlan_tag[0x1]; 474 u8 frag[0x1]; 475 u8 ip_version[0x4]; 476 u8 tcp_flags[0x9]; 477 478 u8 tcp_sport[0x10]; 479 u8 tcp_dport[0x10]; 480 481 u8 reserved_at_c0[0x18]; 482 u8 ttl_hoplimit[0x8]; 483 484 u8 udp_sport[0x10]; 485 u8 udp_dport[0x10]; 486 487 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6; 488 489 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6; 490 }; 491 492 struct mlx5_ifc_nvgre_key_bits { 493 u8 hi[0x18]; 494 u8 lo[0x8]; 495 }; 496 497 union mlx5_ifc_gre_key_bits { 498 struct mlx5_ifc_nvgre_key_bits nvgre; 499 u8 key[0x20]; 500 }; 501 502 struct mlx5_ifc_fte_match_set_misc_bits { 503 u8 gre_c_present[0x1]; 504 u8 reserved_at_1[0x1]; 505 u8 gre_k_present[0x1]; 506 u8 gre_s_present[0x1]; 507 u8 source_vhca_port[0x4]; 508 u8 source_sqn[0x18]; 509 510 u8 source_eswitch_owner_vhca_id[0x10]; 511 u8 source_port[0x10]; 512 513 u8 outer_second_prio[0x3]; 514 u8 outer_second_cfi[0x1]; 515 u8 outer_second_vid[0xc]; 516 u8 inner_second_prio[0x3]; 517 u8 inner_second_cfi[0x1]; 518 u8 inner_second_vid[0xc]; 519 520 u8 outer_second_cvlan_tag[0x1]; 521 u8 inner_second_cvlan_tag[0x1]; 522 u8 outer_second_svlan_tag[0x1]; 523 u8 inner_second_svlan_tag[0x1]; 524 u8 reserved_at_64[0xc]; 525 u8 gre_protocol[0x10]; 526 527 union mlx5_ifc_gre_key_bits gre_key; 528 529 u8 vxlan_vni[0x18]; 530 u8 reserved_at_b8[0x8]; 531 532 u8 geneve_vni[0x18]; 533 u8 reserved_at_d8[0x7]; 534 u8 geneve_oam[0x1]; 535 536 u8 reserved_at_e0[0xc]; 537 u8 outer_ipv6_flow_label[0x14]; 538 539 u8 reserved_at_100[0xc]; 540 u8 inner_ipv6_flow_label[0x14]; 541 542 u8 reserved_at_120[0xa]; 543 u8 geneve_opt_len[0x6]; 544 u8 geneve_protocol_type[0x10]; 545 546 u8 reserved_at_140[0x8]; 547 u8 bth_dst_qp[0x18]; 548 u8 reserved_at_160[0x20]; 549 u8 outer_esp_spi[0x20]; 550 u8 reserved_at_1a0[0x60]; 551 }; 552 553 struct mlx5_ifc_fte_match_mpls_bits { 554 u8 mpls_label[0x14]; 555 u8 mpls_exp[0x3]; 556 u8 mpls_s_bos[0x1]; 557 u8 mpls_ttl[0x8]; 558 }; 559 560 struct mlx5_ifc_fte_match_set_misc2_bits { 561 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls; 562 563 struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls; 564 565 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre; 566 567 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp; 568 569 u8 metadata_reg_c_7[0x20]; 570 571 u8 metadata_reg_c_6[0x20]; 572 573 u8 metadata_reg_c_5[0x20]; 574 575 u8 metadata_reg_c_4[0x20]; 576 577 u8 metadata_reg_c_3[0x20]; 578 579 u8 metadata_reg_c_2[0x20]; 580 581 u8 metadata_reg_c_1[0x20]; 582 583 u8 metadata_reg_c_0[0x20]; 584 585 u8 metadata_reg_a[0x20]; 586 587 u8 metadata_reg_b[0x20]; 588 589 u8 reserved_at_1c0[0x40]; 590 }; 591 592 struct mlx5_ifc_fte_match_set_misc3_bits { 593 u8 inner_tcp_seq_num[0x20]; 594 595 u8 outer_tcp_seq_num[0x20]; 596 597 u8 inner_tcp_ack_num[0x20]; 598 599 u8 outer_tcp_ack_num[0x20]; 600 601 u8 reserved_at_80[0x8]; 602 u8 outer_vxlan_gpe_vni[0x18]; 603 604 u8 outer_vxlan_gpe_next_protocol[0x8]; 605 u8 outer_vxlan_gpe_flags[0x8]; 606 u8 reserved_at_b0[0x10]; 607 608 u8 icmp_header_data[0x20]; 609 610 u8 icmpv6_header_data[0x20]; 611 612 u8 icmp_type[0x8]; 613 u8 icmp_code[0x8]; 614 u8 icmpv6_type[0x8]; 615 u8 icmpv6_code[0x8]; 616 617 u8 geneve_tlv_option_0_data[0x20]; 618 619 u8 reserved_at_140[0xc0]; 620 }; 621 622 struct mlx5_ifc_cmd_pas_bits { 623 u8 pa_h[0x20]; 624 625 u8 pa_l[0x14]; 626 u8 reserved_at_34[0xc]; 627 }; 628 629 struct mlx5_ifc_uint64_bits { 630 u8 hi[0x20]; 631 632 u8 lo[0x20]; 633 }; 634 635 enum { 636 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0, 637 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7, 638 MLX5_ADS_STAT_RATE_10GBPS = 0x8, 639 MLX5_ADS_STAT_RATE_30GBPS = 0x9, 640 MLX5_ADS_STAT_RATE_5GBPS = 0xa, 641 MLX5_ADS_STAT_RATE_20GBPS = 0xb, 642 MLX5_ADS_STAT_RATE_40GBPS = 0xc, 643 MLX5_ADS_STAT_RATE_60GBPS = 0xd, 644 MLX5_ADS_STAT_RATE_80GBPS = 0xe, 645 MLX5_ADS_STAT_RATE_120GBPS = 0xf, 646 }; 647 648 struct mlx5_ifc_ads_bits { 649 u8 fl[0x1]; 650 u8 free_ar[0x1]; 651 u8 reserved_at_2[0xe]; 652 u8 pkey_index[0x10]; 653 654 u8 reserved_at_20[0x8]; 655 u8 grh[0x1]; 656 u8 mlid[0x7]; 657 u8 rlid[0x10]; 658 659 u8 ack_timeout[0x5]; 660 u8 reserved_at_45[0x3]; 661 u8 src_addr_index[0x8]; 662 u8 reserved_at_50[0x4]; 663 u8 stat_rate[0x4]; 664 u8 hop_limit[0x8]; 665 666 u8 reserved_at_60[0x4]; 667 u8 tclass[0x8]; 668 u8 flow_label[0x14]; 669 670 u8 rgid_rip[16][0x8]; 671 672 u8 reserved_at_100[0x4]; 673 u8 f_dscp[0x1]; 674 u8 f_ecn[0x1]; 675 u8 reserved_at_106[0x1]; 676 u8 f_eth_prio[0x1]; 677 u8 ecn[0x2]; 678 u8 dscp[0x6]; 679 u8 udp_sport[0x10]; 680 681 u8 dei_cfi[0x1]; 682 u8 eth_prio[0x3]; 683 u8 sl[0x4]; 684 u8 vhca_port_num[0x8]; 685 u8 rmac_47_32[0x10]; 686 687 u8 rmac_31_0[0x20]; 688 }; 689 690 struct mlx5_ifc_flow_table_nic_cap_bits { 691 u8 nic_rx_multi_path_tirs[0x1]; 692 u8 nic_rx_multi_path_tirs_fts[0x1]; 693 u8 allow_sniffer_and_nic_rx_shared_tir[0x1]; 694 u8 reserved_at_3[0x4]; 695 u8 sw_owner_reformat_supported[0x1]; 696 u8 reserved_at_8[0x18]; 697 698 u8 encap_general_header[0x1]; 699 u8 reserved_at_21[0xa]; 700 u8 log_max_packet_reformat_context[0x5]; 701 u8 reserved_at_30[0x6]; 702 u8 max_encap_header_size[0xa]; 703 u8 reserved_at_40[0x1c0]; 704 705 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive; 706 707 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_rdma; 708 709 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer; 710 711 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit; 712 713 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_rdma; 714 715 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer; 716 717 u8 reserved_at_e00[0x1200]; 718 719 u8 sw_steering_nic_rx_action_drop_icm_address[0x40]; 720 721 u8 sw_steering_nic_tx_action_drop_icm_address[0x40]; 722 723 u8 sw_steering_nic_tx_action_allow_icm_address[0x40]; 724 725 u8 reserved_at_20c0[0x5f40]; 726 }; 727 728 enum { 729 MLX5_FDB_TO_VPORT_REG_C_0 = 0x01, 730 MLX5_FDB_TO_VPORT_REG_C_1 = 0x02, 731 MLX5_FDB_TO_VPORT_REG_C_2 = 0x04, 732 MLX5_FDB_TO_VPORT_REG_C_3 = 0x08, 733 MLX5_FDB_TO_VPORT_REG_C_4 = 0x10, 734 MLX5_FDB_TO_VPORT_REG_C_5 = 0x20, 735 MLX5_FDB_TO_VPORT_REG_C_6 = 0x40, 736 MLX5_FDB_TO_VPORT_REG_C_7 = 0x80, 737 }; 738 739 struct mlx5_ifc_flow_table_eswitch_cap_bits { 740 u8 fdb_to_vport_reg_c_id[0x8]; 741 u8 reserved_at_8[0xd]; 742 u8 fdb_modify_header_fwd_to_table[0x1]; 743 u8 reserved_at_16[0x1]; 744 u8 flow_source[0x1]; 745 u8 reserved_at_18[0x2]; 746 u8 multi_fdb_encap[0x1]; 747 u8 egress_acl_forward_to_vport[0x1]; 748 u8 fdb_multi_path_to_table[0x1]; 749 u8 reserved_at_1d[0x3]; 750 751 u8 reserved_at_20[0x1e0]; 752 753 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb; 754 755 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress; 756 757 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress; 758 759 u8 reserved_at_800[0x1000]; 760 761 u8 sw_steering_fdb_action_drop_icm_address_rx[0x40]; 762 763 u8 sw_steering_fdb_action_drop_icm_address_tx[0x40]; 764 765 u8 sw_steering_uplink_icm_address_rx[0x40]; 766 767 u8 sw_steering_uplink_icm_address_tx[0x40]; 768 769 u8 reserved_at_1900[0x6700]; 770 }; 771 772 enum { 773 MLX5_COUNTER_SOURCE_ESWITCH = 0x0, 774 MLX5_COUNTER_FLOW_ESWITCH = 0x1, 775 }; 776 777 struct mlx5_ifc_e_switch_cap_bits { 778 u8 vport_svlan_strip[0x1]; 779 u8 vport_cvlan_strip[0x1]; 780 u8 vport_svlan_insert[0x1]; 781 u8 vport_cvlan_insert_if_not_exist[0x1]; 782 u8 vport_cvlan_insert_overwrite[0x1]; 783 u8 reserved_at_5[0x3]; 784 u8 esw_uplink_ingress_acl[0x1]; 785 u8 reserved_at_9[0x10]; 786 u8 esw_functions_changed[0x1]; 787 u8 reserved_at_1a[0x1]; 788 u8 ecpf_vport_exists[0x1]; 789 u8 counter_eswitch_affinity[0x1]; 790 u8 merged_eswitch[0x1]; 791 u8 nic_vport_node_guid_modify[0x1]; 792 u8 nic_vport_port_guid_modify[0x1]; 793 794 u8 vxlan_encap_decap[0x1]; 795 u8 nvgre_encap_decap[0x1]; 796 u8 reserved_at_22[0x1]; 797 u8 log_max_fdb_encap_uplink[0x5]; 798 u8 reserved_at_21[0x3]; 799 u8 log_max_packet_reformat_context[0x5]; 800 u8 reserved_2b[0x6]; 801 u8 max_encap_header_size[0xa]; 802 803 u8 reserved_at_40[0xb]; 804 u8 log_max_esw_sf[0x5]; 805 u8 esw_sf_base_id[0x10]; 806 807 u8 reserved_at_60[0x7a0]; 808 809 }; 810 811 struct mlx5_ifc_qos_cap_bits { 812 u8 packet_pacing[0x1]; 813 u8 esw_scheduling[0x1]; 814 u8 esw_bw_share[0x1]; 815 u8 esw_rate_limit[0x1]; 816 u8 reserved_at_4[0x1]; 817 u8 packet_pacing_burst_bound[0x1]; 818 u8 packet_pacing_typical_size[0x1]; 819 u8 reserved_at_7[0x4]; 820 u8 packet_pacing_uid[0x1]; 821 u8 reserved_at_c[0x14]; 822 823 u8 reserved_at_20[0x20]; 824 825 u8 packet_pacing_max_rate[0x20]; 826 827 u8 packet_pacing_min_rate[0x20]; 828 829 u8 reserved_at_80[0x10]; 830 u8 packet_pacing_rate_table_size[0x10]; 831 832 u8 esw_element_type[0x10]; 833 u8 esw_tsar_type[0x10]; 834 835 u8 reserved_at_c0[0x10]; 836 u8 max_qos_para_vport[0x10]; 837 838 u8 max_tsar_bw_share[0x20]; 839 840 u8 reserved_at_100[0x700]; 841 }; 842 843 struct mlx5_ifc_debug_cap_bits { 844 u8 core_dump_general[0x1]; 845 u8 core_dump_qp[0x1]; 846 u8 reserved_at_2[0x7]; 847 u8 resource_dump[0x1]; 848 u8 reserved_at_a[0x16]; 849 850 u8 reserved_at_20[0x2]; 851 u8 stall_detect[0x1]; 852 u8 reserved_at_23[0x1d]; 853 854 u8 reserved_at_40[0x7c0]; 855 }; 856 857 struct mlx5_ifc_per_protocol_networking_offload_caps_bits { 858 u8 csum_cap[0x1]; 859 u8 vlan_cap[0x1]; 860 u8 lro_cap[0x1]; 861 u8 lro_psh_flag[0x1]; 862 u8 lro_time_stamp[0x1]; 863 u8 reserved_at_5[0x2]; 864 u8 wqe_vlan_insert[0x1]; 865 u8 self_lb_en_modifiable[0x1]; 866 u8 reserved_at_9[0x2]; 867 u8 max_lso_cap[0x5]; 868 u8 multi_pkt_send_wqe[0x2]; 869 u8 wqe_inline_mode[0x2]; 870 u8 rss_ind_tbl_cap[0x4]; 871 u8 reg_umr_sq[0x1]; 872 u8 scatter_fcs[0x1]; 873 u8 enhanced_multi_pkt_send_wqe[0x1]; 874 u8 tunnel_lso_const_out_ip_id[0x1]; 875 u8 reserved_at_1c[0x2]; 876 u8 tunnel_stateless_gre[0x1]; 877 u8 tunnel_stateless_vxlan[0x1]; 878 879 u8 swp[0x1]; 880 u8 swp_csum[0x1]; 881 u8 swp_lso[0x1]; 882 u8 cqe_checksum_full[0x1]; 883 u8 tunnel_stateless_geneve_tx[0x1]; 884 u8 tunnel_stateless_mpls_over_udp[0x1]; 885 u8 tunnel_stateless_mpls_over_gre[0x1]; 886 u8 tunnel_stateless_vxlan_gpe[0x1]; 887 u8 tunnel_stateless_ipv4_over_vxlan[0x1]; 888 u8 tunnel_stateless_ip_over_ip[0x1]; 889 u8 insert_trailer[0x1]; 890 u8 reserved_at_2b[0x5]; 891 u8 max_vxlan_udp_ports[0x8]; 892 u8 reserved_at_38[0x6]; 893 u8 max_geneve_opt_len[0x1]; 894 u8 tunnel_stateless_geneve_rx[0x1]; 895 896 u8 reserved_at_40[0x10]; 897 u8 lro_min_mss_size[0x10]; 898 899 u8 reserved_at_60[0x120]; 900 901 u8 lro_timer_supported_periods[4][0x20]; 902 903 u8 reserved_at_200[0x600]; 904 }; 905 906 struct mlx5_ifc_roce_cap_bits { 907 u8 roce_apm[0x1]; 908 u8 reserved_at_1[0x3]; 909 u8 sw_r_roce_src_udp_port[0x1]; 910 u8 reserved_at_5[0x1b]; 911 912 u8 reserved_at_20[0x60]; 913 914 u8 reserved_at_80[0xc]; 915 u8 l3_type[0x4]; 916 u8 reserved_at_90[0x8]; 917 u8 roce_version[0x8]; 918 919 u8 reserved_at_a0[0x10]; 920 u8 r_roce_dest_udp_port[0x10]; 921 922 u8 r_roce_max_src_udp_port[0x10]; 923 u8 r_roce_min_src_udp_port[0x10]; 924 925 u8 reserved_at_e0[0x10]; 926 u8 roce_address_table_size[0x10]; 927 928 u8 reserved_at_100[0x700]; 929 }; 930 931 struct mlx5_ifc_sync_steering_in_bits { 932 u8 opcode[0x10]; 933 u8 uid[0x10]; 934 935 u8 reserved_at_20[0x10]; 936 u8 op_mod[0x10]; 937 938 u8 reserved_at_40[0xc0]; 939 }; 940 941 struct mlx5_ifc_sync_steering_out_bits { 942 u8 status[0x8]; 943 u8 reserved_at_8[0x18]; 944 945 u8 syndrome[0x20]; 946 947 u8 reserved_at_40[0x40]; 948 }; 949 950 struct mlx5_ifc_device_mem_cap_bits { 951 u8 memic[0x1]; 952 u8 reserved_at_1[0x1f]; 953 954 u8 reserved_at_20[0xb]; 955 u8 log_min_memic_alloc_size[0x5]; 956 u8 reserved_at_30[0x8]; 957 u8 log_max_memic_addr_alignment[0x8]; 958 959 u8 memic_bar_start_addr[0x40]; 960 961 u8 memic_bar_size[0x20]; 962 963 u8 max_memic_size[0x20]; 964 965 u8 steering_sw_icm_start_address[0x40]; 966 967 u8 reserved_at_100[0x8]; 968 u8 log_header_modify_sw_icm_size[0x8]; 969 u8 reserved_at_110[0x2]; 970 u8 log_sw_icm_alloc_granularity[0x6]; 971 u8 log_steering_sw_icm_size[0x8]; 972 973 u8 reserved_at_120[0x20]; 974 975 u8 header_modify_sw_icm_start_address[0x40]; 976 977 u8 reserved_at_180[0x680]; 978 }; 979 980 struct mlx5_ifc_device_event_cap_bits { 981 u8 user_affiliated_events[4][0x40]; 982 983 u8 user_unaffiliated_events[4][0x40]; 984 }; 985 986 struct mlx5_ifc_device_virtio_emulation_cap_bits { 987 u8 reserved_at_0[0x20]; 988 989 u8 reserved_at_20[0x13]; 990 u8 log_doorbell_stride[0x5]; 991 u8 reserved_at_38[0x3]; 992 u8 log_doorbell_bar_size[0x5]; 993 994 u8 doorbell_bar_offset[0x40]; 995 996 u8 reserved_at_80[0x780]; 997 }; 998 999 enum { 1000 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0, 1001 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2, 1002 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4, 1003 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8, 1004 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10, 1005 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20, 1006 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40, 1007 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80, 1008 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100, 1009 }; 1010 1011 enum { 1012 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1, 1013 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2, 1014 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4, 1015 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8, 1016 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10, 1017 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20, 1018 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40, 1019 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80, 1020 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100, 1021 }; 1022 1023 struct mlx5_ifc_atomic_caps_bits { 1024 u8 reserved_at_0[0x40]; 1025 1026 u8 atomic_req_8B_endianness_mode[0x2]; 1027 u8 reserved_at_42[0x4]; 1028 u8 supported_atomic_req_8B_endianness_mode_1[0x1]; 1029 1030 u8 reserved_at_47[0x19]; 1031 1032 u8 reserved_at_60[0x20]; 1033 1034 u8 reserved_at_80[0x10]; 1035 u8 atomic_operations[0x10]; 1036 1037 u8 reserved_at_a0[0x10]; 1038 u8 atomic_size_qp[0x10]; 1039 1040 u8 reserved_at_c0[0x10]; 1041 u8 atomic_size_dc[0x10]; 1042 1043 u8 reserved_at_e0[0x720]; 1044 }; 1045 1046 struct mlx5_ifc_odp_cap_bits { 1047 u8 reserved_at_0[0x40]; 1048 1049 u8 sig[0x1]; 1050 u8 reserved_at_41[0x1f]; 1051 1052 u8 reserved_at_60[0x20]; 1053 1054 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps; 1055 1056 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps; 1057 1058 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps; 1059 1060 struct mlx5_ifc_odp_per_transport_service_cap_bits xrc_odp_caps; 1061 1062 struct mlx5_ifc_odp_per_transport_service_cap_bits dc_odp_caps; 1063 1064 u8 reserved_at_120[0x6E0]; 1065 }; 1066 1067 struct mlx5_ifc_calc_op { 1068 u8 reserved_at_0[0x10]; 1069 u8 reserved_at_10[0x9]; 1070 u8 op_swap_endianness[0x1]; 1071 u8 op_min[0x1]; 1072 u8 op_xor[0x1]; 1073 u8 op_or[0x1]; 1074 u8 op_and[0x1]; 1075 u8 op_max[0x1]; 1076 u8 op_add[0x1]; 1077 }; 1078 1079 struct mlx5_ifc_vector_calc_cap_bits { 1080 u8 calc_matrix[0x1]; 1081 u8 reserved_at_1[0x1f]; 1082 u8 reserved_at_20[0x8]; 1083 u8 max_vec_count[0x8]; 1084 u8 reserved_at_30[0xd]; 1085 u8 max_chunk_size[0x3]; 1086 struct mlx5_ifc_calc_op calc0; 1087 struct mlx5_ifc_calc_op calc1; 1088 struct mlx5_ifc_calc_op calc2; 1089 struct mlx5_ifc_calc_op calc3; 1090 1091 u8 reserved_at_c0[0x720]; 1092 }; 1093 1094 struct mlx5_ifc_tls_cap_bits { 1095 u8 tls_1_2_aes_gcm_128[0x1]; 1096 u8 tls_1_3_aes_gcm_128[0x1]; 1097 u8 tls_1_2_aes_gcm_256[0x1]; 1098 u8 tls_1_3_aes_gcm_256[0x1]; 1099 u8 reserved_at_4[0x1c]; 1100 1101 u8 reserved_at_20[0x7e0]; 1102 }; 1103 1104 struct mlx5_ifc_ipsec_cap_bits { 1105 u8 ipsec_full_offload[0x1]; 1106 u8 ipsec_crypto_offload[0x1]; 1107 u8 ipsec_esn[0x1]; 1108 u8 ipsec_crypto_esp_aes_gcm_256_encrypt[0x1]; 1109 u8 ipsec_crypto_esp_aes_gcm_128_encrypt[0x1]; 1110 u8 ipsec_crypto_esp_aes_gcm_256_decrypt[0x1]; 1111 u8 ipsec_crypto_esp_aes_gcm_128_decrypt[0x1]; 1112 u8 reserved_at_7[0x4]; 1113 u8 log_max_ipsec_offload[0x5]; 1114 u8 reserved_at_10[0x10]; 1115 1116 u8 min_log_ipsec_full_replay_window[0x8]; 1117 u8 max_log_ipsec_full_replay_window[0x8]; 1118 u8 reserved_at_30[0x7d0]; 1119 }; 1120 1121 enum { 1122 MLX5_WQ_TYPE_LINKED_LIST = 0x0, 1123 MLX5_WQ_TYPE_CYCLIC = 0x1, 1124 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2, 1125 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3, 1126 }; 1127 1128 enum { 1129 MLX5_WQ_END_PAD_MODE_NONE = 0x0, 1130 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1, 1131 }; 1132 1133 enum { 1134 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0, 1135 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1, 1136 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2, 1137 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3, 1138 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4, 1139 }; 1140 1141 enum { 1142 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0, 1143 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1, 1144 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2, 1145 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3, 1146 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4, 1147 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5, 1148 }; 1149 1150 enum { 1151 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0, 1152 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1, 1153 }; 1154 1155 enum { 1156 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0, 1157 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1, 1158 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3, 1159 }; 1160 1161 enum { 1162 MLX5_CAP_PORT_TYPE_IB = 0x0, 1163 MLX5_CAP_PORT_TYPE_ETH = 0x1, 1164 }; 1165 1166 enum { 1167 MLX5_CAP_UMR_FENCE_STRONG = 0x0, 1168 MLX5_CAP_UMR_FENCE_SMALL = 0x1, 1169 MLX5_CAP_UMR_FENCE_NONE = 0x2, 1170 }; 1171 1172 enum { 1173 MLX5_FLEX_PARSER_GENEVE_ENABLED = 1 << 3, 1174 MLX5_FLEX_PARSER_VXLAN_GPE_ENABLED = 1 << 7, 1175 MLX5_FLEX_PARSER_ICMP_V4_ENABLED = 1 << 8, 1176 MLX5_FLEX_PARSER_ICMP_V6_ENABLED = 1 << 9, 1177 }; 1178 1179 enum { 1180 MLX5_UCTX_CAP_RAW_TX = 1UL << 0, 1181 MLX5_UCTX_CAP_INTERNAL_DEV_RES = 1UL << 1, 1182 }; 1183 1184 #define MLX5_FC_BULK_SIZE_FACTOR 128 1185 1186 enum mlx5_fc_bulk_alloc_bitmask { 1187 MLX5_FC_BULK_128 = (1 << 0), 1188 MLX5_FC_BULK_256 = (1 << 1), 1189 MLX5_FC_BULK_512 = (1 << 2), 1190 MLX5_FC_BULK_1024 = (1 << 3), 1191 MLX5_FC_BULK_2048 = (1 << 4), 1192 MLX5_FC_BULK_4096 = (1 << 5), 1193 MLX5_FC_BULK_8192 = (1 << 6), 1194 MLX5_FC_BULK_16384 = (1 << 7), 1195 }; 1196 1197 #define MLX5_FC_BULK_NUM_FCS(fc_enum) (MLX5_FC_BULK_SIZE_FACTOR * (fc_enum)) 1198 1199 struct mlx5_ifc_cmd_hca_cap_bits { 1200 u8 reserved_at_0[0x30]; 1201 u8 vhca_id[0x10]; 1202 1203 u8 reserved_at_40[0x40]; 1204 1205 u8 log_max_srq_sz[0x8]; 1206 u8 log_max_qp_sz[0x8]; 1207 u8 event_cap[0x1]; 1208 u8 reserved_at_91[0x7]; 1209 u8 prio_tag_required[0x1]; 1210 u8 reserved_at_99[0x2]; 1211 u8 log_max_qp[0x5]; 1212 1213 u8 reserved_at_a0[0xb]; 1214 u8 log_max_srq[0x5]; 1215 u8 reserved_at_b0[0x10]; 1216 1217 u8 max_sgl_for_optimized_performance[0x8]; 1218 u8 log_max_cq_sz[0x8]; 1219 u8 reserved_at_d0[0xb]; 1220 u8 log_max_cq[0x5]; 1221 1222 u8 log_max_eq_sz[0x8]; 1223 u8 relaxed_ordering_write[0x1]; 1224 u8 relaxed_ordering_read[0x1]; 1225 u8 log_max_mkey[0x6]; 1226 u8 reserved_at_f0[0x8]; 1227 u8 dump_fill_mkey[0x1]; 1228 u8 reserved_at_f9[0x2]; 1229 u8 fast_teardown[0x1]; 1230 u8 log_max_eq[0x4]; 1231 1232 u8 max_indirection[0x8]; 1233 u8 fixed_buffer_size[0x1]; 1234 u8 log_max_mrw_sz[0x7]; 1235 u8 force_teardown[0x1]; 1236 u8 reserved_at_111[0x1]; 1237 u8 log_max_bsf_list_size[0x6]; 1238 u8 umr_extended_translation_offset[0x1]; 1239 u8 null_mkey[0x1]; 1240 u8 log_max_klm_list_size[0x6]; 1241 1242 u8 reserved_at_120[0xa]; 1243 u8 log_max_ra_req_dc[0x6]; 1244 u8 reserved_at_130[0xa]; 1245 u8 log_max_ra_res_dc[0x6]; 1246 1247 u8 reserved_at_140[0x6]; 1248 u8 release_all_pages[0x1]; 1249 u8 reserved_at_147[0x2]; 1250 u8 roce_accl[0x1]; 1251 u8 log_max_ra_req_qp[0x6]; 1252 u8 reserved_at_150[0xa]; 1253 u8 log_max_ra_res_qp[0x6]; 1254 1255 u8 end_pad[0x1]; 1256 u8 cc_query_allowed[0x1]; 1257 u8 cc_modify_allowed[0x1]; 1258 u8 start_pad[0x1]; 1259 u8 cache_line_128byte[0x1]; 1260 u8 reserved_at_165[0x4]; 1261 u8 rts2rts_qp_counters_set_id[0x1]; 1262 u8 reserved_at_16a[0x2]; 1263 u8 vnic_env_int_rq_oob[0x1]; 1264 u8 sbcam_reg[0x1]; 1265 u8 reserved_at_16e[0x1]; 1266 u8 qcam_reg[0x1]; 1267 u8 gid_table_size[0x10]; 1268 1269 u8 out_of_seq_cnt[0x1]; 1270 u8 vport_counters[0x1]; 1271 u8 retransmission_q_counters[0x1]; 1272 u8 debug[0x1]; 1273 u8 modify_rq_counter_set_id[0x1]; 1274 u8 rq_delay_drop[0x1]; 1275 u8 max_qp_cnt[0xa]; 1276 u8 pkey_table_size[0x10]; 1277 1278 u8 vport_group_manager[0x1]; 1279 u8 vhca_group_manager[0x1]; 1280 u8 ib_virt[0x1]; 1281 u8 eth_virt[0x1]; 1282 u8 vnic_env_queue_counters[0x1]; 1283 u8 ets[0x1]; 1284 u8 nic_flow_table[0x1]; 1285 u8 eswitch_manager[0x1]; 1286 u8 device_memory[0x1]; 1287 u8 mcam_reg[0x1]; 1288 u8 pcam_reg[0x1]; 1289 u8 local_ca_ack_delay[0x5]; 1290 u8 port_module_event[0x1]; 1291 u8 enhanced_error_q_counters[0x1]; 1292 u8 ports_check[0x1]; 1293 u8 reserved_at_1b3[0x1]; 1294 u8 disable_link_up[0x1]; 1295 u8 beacon_led[0x1]; 1296 u8 port_type[0x2]; 1297 u8 num_ports[0x8]; 1298 1299 u8 reserved_at_1c0[0x1]; 1300 u8 pps[0x1]; 1301 u8 pps_modify[0x1]; 1302 u8 log_max_msg[0x5]; 1303 u8 reserved_at_1c8[0x4]; 1304 u8 max_tc[0x4]; 1305 u8 temp_warn_event[0x1]; 1306 u8 dcbx[0x1]; 1307 u8 general_notification_event[0x1]; 1308 u8 reserved_at_1d3[0x2]; 1309 u8 fpga[0x1]; 1310 u8 rol_s[0x1]; 1311 u8 rol_g[0x1]; 1312 u8 reserved_at_1d8[0x1]; 1313 u8 wol_s[0x1]; 1314 u8 wol_g[0x1]; 1315 u8 wol_a[0x1]; 1316 u8 wol_b[0x1]; 1317 u8 wol_m[0x1]; 1318 u8 wol_u[0x1]; 1319 u8 wol_p[0x1]; 1320 1321 u8 stat_rate_support[0x10]; 1322 u8 reserved_at_1f0[0x1]; 1323 u8 pci_sync_for_fw_update_event[0x1]; 1324 u8 reserved_at_1f2[0xa]; 1325 u8 cqe_version[0x4]; 1326 1327 u8 compact_address_vector[0x1]; 1328 u8 striding_rq[0x1]; 1329 u8 reserved_at_202[0x1]; 1330 u8 ipoib_enhanced_offloads[0x1]; 1331 u8 ipoib_basic_offloads[0x1]; 1332 u8 reserved_at_205[0x1]; 1333 u8 repeated_block_disabled[0x1]; 1334 u8 umr_modify_entity_size_disabled[0x1]; 1335 u8 umr_modify_atomic_disabled[0x1]; 1336 u8 umr_indirect_mkey_disabled[0x1]; 1337 u8 umr_fence[0x2]; 1338 u8 dc_req_scat_data_cqe[0x1]; 1339 u8 reserved_at_20d[0x2]; 1340 u8 drain_sigerr[0x1]; 1341 u8 cmdif_checksum[0x2]; 1342 u8 sigerr_cqe[0x1]; 1343 u8 reserved_at_213[0x1]; 1344 u8 wq_signature[0x1]; 1345 u8 sctr_data_cqe[0x1]; 1346 u8 reserved_at_216[0x1]; 1347 u8 sho[0x1]; 1348 u8 tph[0x1]; 1349 u8 rf[0x1]; 1350 u8 dct[0x1]; 1351 u8 qos[0x1]; 1352 u8 eth_net_offloads[0x1]; 1353 u8 roce[0x1]; 1354 u8 atomic[0x1]; 1355 u8 reserved_at_21f[0x1]; 1356 1357 u8 cq_oi[0x1]; 1358 u8 cq_resize[0x1]; 1359 u8 cq_moderation[0x1]; 1360 u8 reserved_at_223[0x3]; 1361 u8 cq_eq_remap[0x1]; 1362 u8 pg[0x1]; 1363 u8 block_lb_mc[0x1]; 1364 u8 reserved_at_229[0x1]; 1365 u8 scqe_break_moderation[0x1]; 1366 u8 cq_period_start_from_cqe[0x1]; 1367 u8 cd[0x1]; 1368 u8 reserved_at_22d[0x1]; 1369 u8 apm[0x1]; 1370 u8 vector_calc[0x1]; 1371 u8 umr_ptr_rlky[0x1]; 1372 u8 imaicl[0x1]; 1373 u8 qp_packet_based[0x1]; 1374 u8 reserved_at_233[0x3]; 1375 u8 qkv[0x1]; 1376 u8 pkv[0x1]; 1377 u8 set_deth_sqpn[0x1]; 1378 u8 reserved_at_239[0x3]; 1379 u8 xrc[0x1]; 1380 u8 ud[0x1]; 1381 u8 uc[0x1]; 1382 u8 rc[0x1]; 1383 1384 u8 uar_4k[0x1]; 1385 u8 reserved_at_241[0x9]; 1386 u8 uar_sz[0x6]; 1387 u8 reserved_at_250[0x8]; 1388 u8 log_pg_sz[0x8]; 1389 1390 u8 bf[0x1]; 1391 u8 driver_version[0x1]; 1392 u8 pad_tx_eth_packet[0x1]; 1393 u8 reserved_at_263[0x8]; 1394 u8 log_bf_reg_size[0x5]; 1395 1396 u8 reserved_at_270[0x8]; 1397 u8 lag_tx_port_affinity[0x1]; 1398 u8 reserved_at_279[0x2]; 1399 u8 lag_master[0x1]; 1400 u8 num_lag_ports[0x4]; 1401 1402 u8 reserved_at_280[0x10]; 1403 u8 max_wqe_sz_sq[0x10]; 1404 1405 u8 reserved_at_2a0[0x10]; 1406 u8 max_wqe_sz_rq[0x10]; 1407 1408 u8 max_flow_counter_31_16[0x10]; 1409 u8 max_wqe_sz_sq_dc[0x10]; 1410 1411 u8 reserved_at_2e0[0x7]; 1412 u8 max_qp_mcg[0x19]; 1413 1414 u8 reserved_at_300[0x10]; 1415 u8 flow_counter_bulk_alloc[0x8]; 1416 u8 log_max_mcg[0x8]; 1417 1418 u8 reserved_at_320[0x3]; 1419 u8 log_max_transport_domain[0x5]; 1420 u8 reserved_at_328[0x3]; 1421 u8 log_max_pd[0x5]; 1422 u8 reserved_at_330[0xb]; 1423 u8 log_max_xrcd[0x5]; 1424 1425 u8 nic_receive_steering_discard[0x1]; 1426 u8 receive_discard_vport_down[0x1]; 1427 u8 transmit_discard_vport_down[0x1]; 1428 u8 reserved_at_343[0x5]; 1429 u8 log_max_flow_counter_bulk[0x8]; 1430 u8 max_flow_counter_15_0[0x10]; 1431 1432 1433 u8 reserved_at_360[0x3]; 1434 u8 log_max_rq[0x5]; 1435 u8 reserved_at_368[0x3]; 1436 u8 log_max_sq[0x5]; 1437 u8 reserved_at_370[0x3]; 1438 u8 log_max_tir[0x5]; 1439 u8 reserved_at_378[0x3]; 1440 u8 log_max_tis[0x5]; 1441 1442 u8 basic_cyclic_rcv_wqe[0x1]; 1443 u8 reserved_at_381[0x2]; 1444 u8 log_max_rmp[0x5]; 1445 u8 reserved_at_388[0x3]; 1446 u8 log_max_rqt[0x5]; 1447 u8 reserved_at_390[0x3]; 1448 u8 log_max_rqt_size[0x5]; 1449 u8 reserved_at_398[0x3]; 1450 u8 log_max_tis_per_sq[0x5]; 1451 1452 u8 ext_stride_num_range[0x1]; 1453 u8 reserved_at_3a1[0x2]; 1454 u8 log_max_stride_sz_rq[0x5]; 1455 u8 reserved_at_3a8[0x3]; 1456 u8 log_min_stride_sz_rq[0x5]; 1457 u8 reserved_at_3b0[0x3]; 1458 u8 log_max_stride_sz_sq[0x5]; 1459 u8 reserved_at_3b8[0x3]; 1460 u8 log_min_stride_sz_sq[0x5]; 1461 1462 u8 hairpin[0x1]; 1463 u8 reserved_at_3c1[0x2]; 1464 u8 log_max_hairpin_queues[0x5]; 1465 u8 reserved_at_3c8[0x3]; 1466 u8 log_max_hairpin_wq_data_sz[0x5]; 1467 u8 reserved_at_3d0[0x3]; 1468 u8 log_max_hairpin_num_packets[0x5]; 1469 u8 reserved_at_3d8[0x3]; 1470 u8 log_max_wq_sz[0x5]; 1471 1472 u8 nic_vport_change_event[0x1]; 1473 u8 disable_local_lb_uc[0x1]; 1474 u8 disable_local_lb_mc[0x1]; 1475 u8 log_min_hairpin_wq_data_sz[0x5]; 1476 u8 reserved_at_3e8[0x3]; 1477 u8 log_max_vlan_list[0x5]; 1478 u8 reserved_at_3f0[0x3]; 1479 u8 log_max_current_mc_list[0x5]; 1480 u8 reserved_at_3f8[0x3]; 1481 u8 log_max_current_uc_list[0x5]; 1482 1483 u8 general_obj_types[0x40]; 1484 1485 u8 reserved_at_440[0x20]; 1486 1487 u8 reserved_at_460[0x3]; 1488 u8 log_max_uctx[0x5]; 1489 u8 reserved_at_468[0x2]; 1490 u8 ipsec_offload[0x1]; 1491 u8 log_max_umem[0x5]; 1492 u8 max_num_eqs[0x10]; 1493 1494 u8 reserved_at_480[0x1]; 1495 u8 tls_tx[0x1]; 1496 u8 tls_rx[0x1]; 1497 u8 log_max_l2_table[0x5]; 1498 u8 reserved_at_488[0x8]; 1499 u8 log_uar_page_sz[0x10]; 1500 1501 u8 reserved_at_4a0[0x20]; 1502 u8 device_frequency_mhz[0x20]; 1503 u8 device_frequency_khz[0x20]; 1504 1505 u8 reserved_at_500[0x20]; 1506 u8 num_of_uars_per_page[0x20]; 1507 1508 u8 flex_parser_protocols[0x20]; 1509 1510 u8 max_geneve_tlv_options[0x8]; 1511 u8 reserved_at_568[0x3]; 1512 u8 max_geneve_tlv_option_data_len[0x5]; 1513 u8 reserved_at_570[0x10]; 1514 1515 u8 reserved_at_580[0x33]; 1516 u8 log_max_dek[0x5]; 1517 u8 reserved_at_5b8[0x4]; 1518 u8 mini_cqe_resp_stride_index[0x1]; 1519 u8 cqe_128_always[0x1]; 1520 u8 cqe_compression_128[0x1]; 1521 u8 cqe_compression[0x1]; 1522 1523 u8 cqe_compression_timeout[0x10]; 1524 u8 cqe_compression_max_num[0x10]; 1525 1526 u8 reserved_at_5e0[0x10]; 1527 u8 tag_matching[0x1]; 1528 u8 rndv_offload_rc[0x1]; 1529 u8 rndv_offload_dc[0x1]; 1530 u8 log_tag_matching_list_sz[0x5]; 1531 u8 reserved_at_5f8[0x3]; 1532 u8 log_max_xrq[0x5]; 1533 1534 u8 affiliate_nic_vport_criteria[0x8]; 1535 u8 native_port_num[0x8]; 1536 u8 num_vhca_ports[0x8]; 1537 u8 reserved_at_618[0x6]; 1538 u8 sw_owner_id[0x1]; 1539 u8 reserved_at_61f[0x1]; 1540 1541 u8 max_num_of_monitor_counters[0x10]; 1542 u8 num_ppcnt_monitor_counters[0x10]; 1543 1544 u8 reserved_at_640[0x10]; 1545 u8 num_q_monitor_counters[0x10]; 1546 1547 u8 reserved_at_660[0x20]; 1548 1549 u8 sf[0x1]; 1550 u8 sf_set_partition[0x1]; 1551 u8 reserved_at_682[0x1]; 1552 u8 log_max_sf[0x5]; 1553 u8 reserved_at_688[0x8]; 1554 u8 log_min_sf_size[0x8]; 1555 u8 max_num_sf_partitions[0x8]; 1556 1557 u8 uctx_cap[0x20]; 1558 1559 u8 reserved_at_6c0[0x4]; 1560 u8 flex_parser_id_geneve_tlv_option_0[0x4]; 1561 u8 flex_parser_id_icmp_dw1[0x4]; 1562 u8 flex_parser_id_icmp_dw0[0x4]; 1563 u8 flex_parser_id_icmpv6_dw1[0x4]; 1564 u8 flex_parser_id_icmpv6_dw0[0x4]; 1565 u8 flex_parser_id_outer_first_mpls_over_gre[0x4]; 1566 u8 flex_parser_id_outer_first_mpls_over_udp_label[0x4]; 1567 1568 u8 reserved_at_6e0[0x10]; 1569 u8 sf_base_id[0x10]; 1570 1571 u8 reserved_at_700[0x80]; 1572 u8 vhca_tunnel_commands[0x40]; 1573 u8 reserved_at_7c0[0x40]; 1574 }; 1575 1576 enum mlx5_flow_destination_type { 1577 MLX5_FLOW_DESTINATION_TYPE_VPORT = 0x0, 1578 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1, 1579 MLX5_FLOW_DESTINATION_TYPE_TIR = 0x2, 1580 1581 MLX5_FLOW_DESTINATION_TYPE_PORT = 0x99, 1582 MLX5_FLOW_DESTINATION_TYPE_COUNTER = 0x100, 1583 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE_NUM = 0x101, 1584 }; 1585 1586 enum mlx5_flow_table_miss_action { 1587 MLX5_FLOW_TABLE_MISS_ACTION_DEF, 1588 MLX5_FLOW_TABLE_MISS_ACTION_FWD, 1589 MLX5_FLOW_TABLE_MISS_ACTION_SWITCH_DOMAIN, 1590 }; 1591 1592 struct mlx5_ifc_dest_format_struct_bits { 1593 u8 destination_type[0x8]; 1594 u8 destination_id[0x18]; 1595 1596 u8 destination_eswitch_owner_vhca_id_valid[0x1]; 1597 u8 packet_reformat[0x1]; 1598 u8 reserved_at_22[0xe]; 1599 u8 destination_eswitch_owner_vhca_id[0x10]; 1600 }; 1601 1602 struct mlx5_ifc_flow_counter_list_bits { 1603 u8 flow_counter_id[0x20]; 1604 1605 u8 reserved_at_20[0x20]; 1606 }; 1607 1608 struct mlx5_ifc_extended_dest_format_bits { 1609 struct mlx5_ifc_dest_format_struct_bits destination_entry; 1610 1611 u8 packet_reformat_id[0x20]; 1612 1613 u8 reserved_at_60[0x20]; 1614 }; 1615 1616 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits { 1617 struct mlx5_ifc_extended_dest_format_bits extended_dest_format; 1618 struct mlx5_ifc_flow_counter_list_bits flow_counter_list; 1619 }; 1620 1621 struct mlx5_ifc_fte_match_param_bits { 1622 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers; 1623 1624 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters; 1625 1626 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers; 1627 1628 struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2; 1629 1630 struct mlx5_ifc_fte_match_set_misc3_bits misc_parameters_3; 1631 1632 u8 reserved_at_a00[0x600]; 1633 }; 1634 1635 enum { 1636 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0, 1637 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1, 1638 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2, 1639 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3, 1640 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4, 1641 }; 1642 1643 struct mlx5_ifc_rx_hash_field_select_bits { 1644 u8 l3_prot_type[0x1]; 1645 u8 l4_prot_type[0x1]; 1646 u8 selected_fields[0x1e]; 1647 }; 1648 1649 enum { 1650 MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0, 1651 MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1, 1652 }; 1653 1654 enum { 1655 MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0, 1656 MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1, 1657 }; 1658 1659 struct mlx5_ifc_wq_bits { 1660 u8 wq_type[0x4]; 1661 u8 wq_signature[0x1]; 1662 u8 end_padding_mode[0x2]; 1663 u8 cd_slave[0x1]; 1664 u8 reserved_at_8[0x18]; 1665 1666 u8 hds_skip_first_sge[0x1]; 1667 u8 log2_hds_buf_size[0x3]; 1668 u8 reserved_at_24[0x7]; 1669 u8 page_offset[0x5]; 1670 u8 lwm[0x10]; 1671 1672 u8 reserved_at_40[0x8]; 1673 u8 pd[0x18]; 1674 1675 u8 reserved_at_60[0x8]; 1676 u8 uar_page[0x18]; 1677 1678 u8 dbr_addr[0x40]; 1679 1680 u8 hw_counter[0x20]; 1681 1682 u8 sw_counter[0x20]; 1683 1684 u8 reserved_at_100[0xc]; 1685 u8 log_wq_stride[0x4]; 1686 u8 reserved_at_110[0x3]; 1687 u8 log_wq_pg_sz[0x5]; 1688 u8 reserved_at_118[0x3]; 1689 u8 log_wq_sz[0x5]; 1690 1691 u8 dbr_umem_valid[0x1]; 1692 u8 wq_umem_valid[0x1]; 1693 u8 reserved_at_122[0x1]; 1694 u8 log_hairpin_num_packets[0x5]; 1695 u8 reserved_at_128[0x3]; 1696 u8 log_hairpin_data_sz[0x5]; 1697 1698 u8 reserved_at_130[0x4]; 1699 u8 log_wqe_num_of_strides[0x4]; 1700 u8 two_byte_shift_en[0x1]; 1701 u8 reserved_at_139[0x4]; 1702 u8 log_wqe_stride_size[0x3]; 1703 1704 u8 reserved_at_140[0x4c0]; 1705 1706 struct mlx5_ifc_cmd_pas_bits pas[0]; 1707 }; 1708 1709 struct mlx5_ifc_rq_num_bits { 1710 u8 reserved_at_0[0x8]; 1711 u8 rq_num[0x18]; 1712 }; 1713 1714 struct mlx5_ifc_mac_address_layout_bits { 1715 u8 reserved_at_0[0x10]; 1716 u8 mac_addr_47_32[0x10]; 1717 1718 u8 mac_addr_31_0[0x20]; 1719 }; 1720 1721 struct mlx5_ifc_vlan_layout_bits { 1722 u8 reserved_at_0[0x14]; 1723 u8 vlan[0x0c]; 1724 1725 u8 reserved_at_20[0x20]; 1726 }; 1727 1728 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits { 1729 u8 reserved_at_0[0xa0]; 1730 1731 u8 min_time_between_cnps[0x20]; 1732 1733 u8 reserved_at_c0[0x12]; 1734 u8 cnp_dscp[0x6]; 1735 u8 reserved_at_d8[0x4]; 1736 u8 cnp_prio_mode[0x1]; 1737 u8 cnp_802p_prio[0x3]; 1738 1739 u8 reserved_at_e0[0x720]; 1740 }; 1741 1742 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits { 1743 u8 reserved_at_0[0x60]; 1744 1745 u8 reserved_at_60[0x4]; 1746 u8 clamp_tgt_rate[0x1]; 1747 u8 reserved_at_65[0x3]; 1748 u8 clamp_tgt_rate_after_time_inc[0x1]; 1749 u8 reserved_at_69[0x17]; 1750 1751 u8 reserved_at_80[0x20]; 1752 1753 u8 rpg_time_reset[0x20]; 1754 1755 u8 rpg_byte_reset[0x20]; 1756 1757 u8 rpg_threshold[0x20]; 1758 1759 u8 rpg_max_rate[0x20]; 1760 1761 u8 rpg_ai_rate[0x20]; 1762 1763 u8 rpg_hai_rate[0x20]; 1764 1765 u8 rpg_gd[0x20]; 1766 1767 u8 rpg_min_dec_fac[0x20]; 1768 1769 u8 rpg_min_rate[0x20]; 1770 1771 u8 reserved_at_1c0[0xe0]; 1772 1773 u8 rate_to_set_on_first_cnp[0x20]; 1774 1775 u8 dce_tcp_g[0x20]; 1776 1777 u8 dce_tcp_rtt[0x20]; 1778 1779 u8 rate_reduce_monitor_period[0x20]; 1780 1781 u8 reserved_at_320[0x20]; 1782 1783 u8 initial_alpha_value[0x20]; 1784 1785 u8 reserved_at_360[0x4a0]; 1786 }; 1787 1788 struct mlx5_ifc_cong_control_802_1qau_rp_bits { 1789 u8 reserved_at_0[0x80]; 1790 1791 u8 rppp_max_rps[0x20]; 1792 1793 u8 rpg_time_reset[0x20]; 1794 1795 u8 rpg_byte_reset[0x20]; 1796 1797 u8 rpg_threshold[0x20]; 1798 1799 u8 rpg_max_rate[0x20]; 1800 1801 u8 rpg_ai_rate[0x20]; 1802 1803 u8 rpg_hai_rate[0x20]; 1804 1805 u8 rpg_gd[0x20]; 1806 1807 u8 rpg_min_dec_fac[0x20]; 1808 1809 u8 rpg_min_rate[0x20]; 1810 1811 u8 reserved_at_1c0[0x640]; 1812 }; 1813 1814 enum { 1815 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1, 1816 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2, 1817 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4, 1818 }; 1819 1820 struct mlx5_ifc_resize_field_select_bits { 1821 u8 resize_field_select[0x20]; 1822 }; 1823 1824 struct mlx5_ifc_resource_dump_bits { 1825 u8 more_dump[0x1]; 1826 u8 inline_dump[0x1]; 1827 u8 reserved_at_2[0xa]; 1828 u8 seq_num[0x4]; 1829 u8 segment_type[0x10]; 1830 1831 u8 reserved_at_20[0x10]; 1832 u8 vhca_id[0x10]; 1833 1834 u8 index1[0x20]; 1835 1836 u8 index2[0x20]; 1837 1838 u8 num_of_obj1[0x10]; 1839 u8 num_of_obj2[0x10]; 1840 1841 u8 reserved_at_a0[0x20]; 1842 1843 u8 device_opaque[0x40]; 1844 1845 u8 mkey[0x20]; 1846 1847 u8 size[0x20]; 1848 1849 u8 address[0x40]; 1850 1851 u8 inline_data[52][0x20]; 1852 }; 1853 1854 struct mlx5_ifc_resource_dump_menu_record_bits { 1855 u8 reserved_at_0[0x4]; 1856 u8 num_of_obj2_supports_active[0x1]; 1857 u8 num_of_obj2_supports_all[0x1]; 1858 u8 must_have_num_of_obj2[0x1]; 1859 u8 support_num_of_obj2[0x1]; 1860 u8 num_of_obj1_supports_active[0x1]; 1861 u8 num_of_obj1_supports_all[0x1]; 1862 u8 must_have_num_of_obj1[0x1]; 1863 u8 support_num_of_obj1[0x1]; 1864 u8 must_have_index2[0x1]; 1865 u8 support_index2[0x1]; 1866 u8 must_have_index1[0x1]; 1867 u8 support_index1[0x1]; 1868 u8 segment_type[0x10]; 1869 1870 u8 segment_name[4][0x20]; 1871 1872 u8 index1_name[4][0x20]; 1873 1874 u8 index2_name[4][0x20]; 1875 }; 1876 1877 struct mlx5_ifc_resource_dump_segment_header_bits { 1878 u8 length_dw[0x10]; 1879 u8 segment_type[0x10]; 1880 }; 1881 1882 struct mlx5_ifc_resource_dump_command_segment_bits { 1883 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 1884 1885 u8 segment_called[0x10]; 1886 u8 vhca_id[0x10]; 1887 1888 u8 index1[0x20]; 1889 1890 u8 index2[0x20]; 1891 1892 u8 num_of_obj1[0x10]; 1893 u8 num_of_obj2[0x10]; 1894 }; 1895 1896 struct mlx5_ifc_resource_dump_error_segment_bits { 1897 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 1898 1899 u8 reserved_at_20[0x10]; 1900 u8 syndrome_id[0x10]; 1901 1902 u8 reserved_at_40[0x40]; 1903 1904 u8 error[8][0x20]; 1905 }; 1906 1907 struct mlx5_ifc_resource_dump_info_segment_bits { 1908 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 1909 1910 u8 reserved_at_20[0x18]; 1911 u8 dump_version[0x8]; 1912 1913 u8 hw_version[0x20]; 1914 1915 u8 fw_version[0x20]; 1916 }; 1917 1918 struct mlx5_ifc_resource_dump_menu_segment_bits { 1919 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 1920 1921 u8 reserved_at_20[0x10]; 1922 u8 num_of_records[0x10]; 1923 1924 struct mlx5_ifc_resource_dump_menu_record_bits record[0]; 1925 }; 1926 1927 struct mlx5_ifc_resource_dump_resource_segment_bits { 1928 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 1929 1930 u8 reserved_at_20[0x20]; 1931 1932 u8 index1[0x20]; 1933 1934 u8 index2[0x20]; 1935 1936 u8 payload[0][0x20]; 1937 }; 1938 1939 struct mlx5_ifc_resource_dump_terminate_segment_bits { 1940 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 1941 }; 1942 1943 struct mlx5_ifc_menu_resource_dump_response_bits { 1944 struct mlx5_ifc_resource_dump_info_segment_bits info; 1945 struct mlx5_ifc_resource_dump_command_segment_bits cmd; 1946 struct mlx5_ifc_resource_dump_menu_segment_bits menu; 1947 struct mlx5_ifc_resource_dump_terminate_segment_bits terminate; 1948 }; 1949 1950 enum { 1951 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1, 1952 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2, 1953 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4, 1954 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8, 1955 }; 1956 1957 struct mlx5_ifc_modify_field_select_bits { 1958 u8 modify_field_select[0x20]; 1959 }; 1960 1961 struct mlx5_ifc_field_select_r_roce_np_bits { 1962 u8 field_select_r_roce_np[0x20]; 1963 }; 1964 1965 struct mlx5_ifc_field_select_r_roce_rp_bits { 1966 u8 field_select_r_roce_rp[0x20]; 1967 }; 1968 1969 enum { 1970 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4, 1971 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8, 1972 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10, 1973 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20, 1974 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40, 1975 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80, 1976 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100, 1977 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200, 1978 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400, 1979 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800, 1980 }; 1981 1982 struct mlx5_ifc_field_select_802_1qau_rp_bits { 1983 u8 field_select_8021qaurp[0x20]; 1984 }; 1985 1986 struct mlx5_ifc_phys_layer_cntrs_bits { 1987 u8 time_since_last_clear_high[0x20]; 1988 1989 u8 time_since_last_clear_low[0x20]; 1990 1991 u8 symbol_errors_high[0x20]; 1992 1993 u8 symbol_errors_low[0x20]; 1994 1995 u8 sync_headers_errors_high[0x20]; 1996 1997 u8 sync_headers_errors_low[0x20]; 1998 1999 u8 edpl_bip_errors_lane0_high[0x20]; 2000 2001 u8 edpl_bip_errors_lane0_low[0x20]; 2002 2003 u8 edpl_bip_errors_lane1_high[0x20]; 2004 2005 u8 edpl_bip_errors_lane1_low[0x20]; 2006 2007 u8 edpl_bip_errors_lane2_high[0x20]; 2008 2009 u8 edpl_bip_errors_lane2_low[0x20]; 2010 2011 u8 edpl_bip_errors_lane3_high[0x20]; 2012 2013 u8 edpl_bip_errors_lane3_low[0x20]; 2014 2015 u8 fc_fec_corrected_blocks_lane0_high[0x20]; 2016 2017 u8 fc_fec_corrected_blocks_lane0_low[0x20]; 2018 2019 u8 fc_fec_corrected_blocks_lane1_high[0x20]; 2020 2021 u8 fc_fec_corrected_blocks_lane1_low[0x20]; 2022 2023 u8 fc_fec_corrected_blocks_lane2_high[0x20]; 2024 2025 u8 fc_fec_corrected_blocks_lane2_low[0x20]; 2026 2027 u8 fc_fec_corrected_blocks_lane3_high[0x20]; 2028 2029 u8 fc_fec_corrected_blocks_lane3_low[0x20]; 2030 2031 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20]; 2032 2033 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20]; 2034 2035 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20]; 2036 2037 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20]; 2038 2039 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20]; 2040 2041 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20]; 2042 2043 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20]; 2044 2045 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20]; 2046 2047 u8 rs_fec_corrected_blocks_high[0x20]; 2048 2049 u8 rs_fec_corrected_blocks_low[0x20]; 2050 2051 u8 rs_fec_uncorrectable_blocks_high[0x20]; 2052 2053 u8 rs_fec_uncorrectable_blocks_low[0x20]; 2054 2055 u8 rs_fec_no_errors_blocks_high[0x20]; 2056 2057 u8 rs_fec_no_errors_blocks_low[0x20]; 2058 2059 u8 rs_fec_single_error_blocks_high[0x20]; 2060 2061 u8 rs_fec_single_error_blocks_low[0x20]; 2062 2063 u8 rs_fec_corrected_symbols_total_high[0x20]; 2064 2065 u8 rs_fec_corrected_symbols_total_low[0x20]; 2066 2067 u8 rs_fec_corrected_symbols_lane0_high[0x20]; 2068 2069 u8 rs_fec_corrected_symbols_lane0_low[0x20]; 2070 2071 u8 rs_fec_corrected_symbols_lane1_high[0x20]; 2072 2073 u8 rs_fec_corrected_symbols_lane1_low[0x20]; 2074 2075 u8 rs_fec_corrected_symbols_lane2_high[0x20]; 2076 2077 u8 rs_fec_corrected_symbols_lane2_low[0x20]; 2078 2079 u8 rs_fec_corrected_symbols_lane3_high[0x20]; 2080 2081 u8 rs_fec_corrected_symbols_lane3_low[0x20]; 2082 2083 u8 link_down_events[0x20]; 2084 2085 u8 successful_recovery_events[0x20]; 2086 2087 u8 reserved_at_640[0x180]; 2088 }; 2089 2090 struct mlx5_ifc_phys_layer_statistical_cntrs_bits { 2091 u8 time_since_last_clear_high[0x20]; 2092 2093 u8 time_since_last_clear_low[0x20]; 2094 2095 u8 phy_received_bits_high[0x20]; 2096 2097 u8 phy_received_bits_low[0x20]; 2098 2099 u8 phy_symbol_errors_high[0x20]; 2100 2101 u8 phy_symbol_errors_low[0x20]; 2102 2103 u8 phy_corrected_bits_high[0x20]; 2104 2105 u8 phy_corrected_bits_low[0x20]; 2106 2107 u8 phy_corrected_bits_lane0_high[0x20]; 2108 2109 u8 phy_corrected_bits_lane0_low[0x20]; 2110 2111 u8 phy_corrected_bits_lane1_high[0x20]; 2112 2113 u8 phy_corrected_bits_lane1_low[0x20]; 2114 2115 u8 phy_corrected_bits_lane2_high[0x20]; 2116 2117 u8 phy_corrected_bits_lane2_low[0x20]; 2118 2119 u8 phy_corrected_bits_lane3_high[0x20]; 2120 2121 u8 phy_corrected_bits_lane3_low[0x20]; 2122 2123 u8 reserved_at_200[0x5c0]; 2124 }; 2125 2126 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits { 2127 u8 symbol_error_counter[0x10]; 2128 2129 u8 link_error_recovery_counter[0x8]; 2130 2131 u8 link_downed_counter[0x8]; 2132 2133 u8 port_rcv_errors[0x10]; 2134 2135 u8 port_rcv_remote_physical_errors[0x10]; 2136 2137 u8 port_rcv_switch_relay_errors[0x10]; 2138 2139 u8 port_xmit_discards[0x10]; 2140 2141 u8 port_xmit_constraint_errors[0x8]; 2142 2143 u8 port_rcv_constraint_errors[0x8]; 2144 2145 u8 reserved_at_70[0x8]; 2146 2147 u8 link_overrun_errors[0x8]; 2148 2149 u8 reserved_at_80[0x10]; 2150 2151 u8 vl_15_dropped[0x10]; 2152 2153 u8 reserved_at_a0[0x80]; 2154 2155 u8 port_xmit_wait[0x20]; 2156 }; 2157 2158 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits { 2159 u8 transmit_queue_high[0x20]; 2160 2161 u8 transmit_queue_low[0x20]; 2162 2163 u8 no_buffer_discard_uc_high[0x20]; 2164 2165 u8 no_buffer_discard_uc_low[0x20]; 2166 2167 u8 reserved_at_80[0x740]; 2168 }; 2169 2170 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits { 2171 u8 wred_discard_high[0x20]; 2172 2173 u8 wred_discard_low[0x20]; 2174 2175 u8 ecn_marked_tc_high[0x20]; 2176 2177 u8 ecn_marked_tc_low[0x20]; 2178 2179 u8 reserved_at_80[0x740]; 2180 }; 2181 2182 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits { 2183 u8 rx_octets_high[0x20]; 2184 2185 u8 rx_octets_low[0x20]; 2186 2187 u8 reserved_at_40[0xc0]; 2188 2189 u8 rx_frames_high[0x20]; 2190 2191 u8 rx_frames_low[0x20]; 2192 2193 u8 tx_octets_high[0x20]; 2194 2195 u8 tx_octets_low[0x20]; 2196 2197 u8 reserved_at_180[0xc0]; 2198 2199 u8 tx_frames_high[0x20]; 2200 2201 u8 tx_frames_low[0x20]; 2202 2203 u8 rx_pause_high[0x20]; 2204 2205 u8 rx_pause_low[0x20]; 2206 2207 u8 rx_pause_duration_high[0x20]; 2208 2209 u8 rx_pause_duration_low[0x20]; 2210 2211 u8 tx_pause_high[0x20]; 2212 2213 u8 tx_pause_low[0x20]; 2214 2215 u8 tx_pause_duration_high[0x20]; 2216 2217 u8 tx_pause_duration_low[0x20]; 2218 2219 u8 rx_pause_transition_high[0x20]; 2220 2221 u8 rx_pause_transition_low[0x20]; 2222 2223 u8 rx_discards_high[0x20]; 2224 2225 u8 rx_discards_low[0x20]; 2226 2227 u8 device_stall_minor_watermark_cnt_high[0x20]; 2228 2229 u8 device_stall_minor_watermark_cnt_low[0x20]; 2230 2231 u8 device_stall_critical_watermark_cnt_high[0x20]; 2232 2233 u8 device_stall_critical_watermark_cnt_low[0x20]; 2234 2235 u8 reserved_at_480[0x340]; 2236 }; 2237 2238 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits { 2239 u8 port_transmit_wait_high[0x20]; 2240 2241 u8 port_transmit_wait_low[0x20]; 2242 2243 u8 reserved_at_40[0x100]; 2244 2245 u8 rx_buffer_almost_full_high[0x20]; 2246 2247 u8 rx_buffer_almost_full_low[0x20]; 2248 2249 u8 rx_buffer_full_high[0x20]; 2250 2251 u8 rx_buffer_full_low[0x20]; 2252 2253 u8 rx_icrc_encapsulated_high[0x20]; 2254 2255 u8 rx_icrc_encapsulated_low[0x20]; 2256 2257 u8 reserved_at_200[0x5c0]; 2258 }; 2259 2260 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits { 2261 u8 dot3stats_alignment_errors_high[0x20]; 2262 2263 u8 dot3stats_alignment_errors_low[0x20]; 2264 2265 u8 dot3stats_fcs_errors_high[0x20]; 2266 2267 u8 dot3stats_fcs_errors_low[0x20]; 2268 2269 u8 dot3stats_single_collision_frames_high[0x20]; 2270 2271 u8 dot3stats_single_collision_frames_low[0x20]; 2272 2273 u8 dot3stats_multiple_collision_frames_high[0x20]; 2274 2275 u8 dot3stats_multiple_collision_frames_low[0x20]; 2276 2277 u8 dot3stats_sqe_test_errors_high[0x20]; 2278 2279 u8 dot3stats_sqe_test_errors_low[0x20]; 2280 2281 u8 dot3stats_deferred_transmissions_high[0x20]; 2282 2283 u8 dot3stats_deferred_transmissions_low[0x20]; 2284 2285 u8 dot3stats_late_collisions_high[0x20]; 2286 2287 u8 dot3stats_late_collisions_low[0x20]; 2288 2289 u8 dot3stats_excessive_collisions_high[0x20]; 2290 2291 u8 dot3stats_excessive_collisions_low[0x20]; 2292 2293 u8 dot3stats_internal_mac_transmit_errors_high[0x20]; 2294 2295 u8 dot3stats_internal_mac_transmit_errors_low[0x20]; 2296 2297 u8 dot3stats_carrier_sense_errors_high[0x20]; 2298 2299 u8 dot3stats_carrier_sense_errors_low[0x20]; 2300 2301 u8 dot3stats_frame_too_longs_high[0x20]; 2302 2303 u8 dot3stats_frame_too_longs_low[0x20]; 2304 2305 u8 dot3stats_internal_mac_receive_errors_high[0x20]; 2306 2307 u8 dot3stats_internal_mac_receive_errors_low[0x20]; 2308 2309 u8 dot3stats_symbol_errors_high[0x20]; 2310 2311 u8 dot3stats_symbol_errors_low[0x20]; 2312 2313 u8 dot3control_in_unknown_opcodes_high[0x20]; 2314 2315 u8 dot3control_in_unknown_opcodes_low[0x20]; 2316 2317 u8 dot3in_pause_frames_high[0x20]; 2318 2319 u8 dot3in_pause_frames_low[0x20]; 2320 2321 u8 dot3out_pause_frames_high[0x20]; 2322 2323 u8 dot3out_pause_frames_low[0x20]; 2324 2325 u8 reserved_at_400[0x3c0]; 2326 }; 2327 2328 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits { 2329 u8 ether_stats_drop_events_high[0x20]; 2330 2331 u8 ether_stats_drop_events_low[0x20]; 2332 2333 u8 ether_stats_octets_high[0x20]; 2334 2335 u8 ether_stats_octets_low[0x20]; 2336 2337 u8 ether_stats_pkts_high[0x20]; 2338 2339 u8 ether_stats_pkts_low[0x20]; 2340 2341 u8 ether_stats_broadcast_pkts_high[0x20]; 2342 2343 u8 ether_stats_broadcast_pkts_low[0x20]; 2344 2345 u8 ether_stats_multicast_pkts_high[0x20]; 2346 2347 u8 ether_stats_multicast_pkts_low[0x20]; 2348 2349 u8 ether_stats_crc_align_errors_high[0x20]; 2350 2351 u8 ether_stats_crc_align_errors_low[0x20]; 2352 2353 u8 ether_stats_undersize_pkts_high[0x20]; 2354 2355 u8 ether_stats_undersize_pkts_low[0x20]; 2356 2357 u8 ether_stats_oversize_pkts_high[0x20]; 2358 2359 u8 ether_stats_oversize_pkts_low[0x20]; 2360 2361 u8 ether_stats_fragments_high[0x20]; 2362 2363 u8 ether_stats_fragments_low[0x20]; 2364 2365 u8 ether_stats_jabbers_high[0x20]; 2366 2367 u8 ether_stats_jabbers_low[0x20]; 2368 2369 u8 ether_stats_collisions_high[0x20]; 2370 2371 u8 ether_stats_collisions_low[0x20]; 2372 2373 u8 ether_stats_pkts64octets_high[0x20]; 2374 2375 u8 ether_stats_pkts64octets_low[0x20]; 2376 2377 u8 ether_stats_pkts65to127octets_high[0x20]; 2378 2379 u8 ether_stats_pkts65to127octets_low[0x20]; 2380 2381 u8 ether_stats_pkts128to255octets_high[0x20]; 2382 2383 u8 ether_stats_pkts128to255octets_low[0x20]; 2384 2385 u8 ether_stats_pkts256to511octets_high[0x20]; 2386 2387 u8 ether_stats_pkts256to511octets_low[0x20]; 2388 2389 u8 ether_stats_pkts512to1023octets_high[0x20]; 2390 2391 u8 ether_stats_pkts512to1023octets_low[0x20]; 2392 2393 u8 ether_stats_pkts1024to1518octets_high[0x20]; 2394 2395 u8 ether_stats_pkts1024to1518octets_low[0x20]; 2396 2397 u8 ether_stats_pkts1519to2047octets_high[0x20]; 2398 2399 u8 ether_stats_pkts1519to2047octets_low[0x20]; 2400 2401 u8 ether_stats_pkts2048to4095octets_high[0x20]; 2402 2403 u8 ether_stats_pkts2048to4095octets_low[0x20]; 2404 2405 u8 ether_stats_pkts4096to8191octets_high[0x20]; 2406 2407 u8 ether_stats_pkts4096to8191octets_low[0x20]; 2408 2409 u8 ether_stats_pkts8192to10239octets_high[0x20]; 2410 2411 u8 ether_stats_pkts8192to10239octets_low[0x20]; 2412 2413 u8 reserved_at_540[0x280]; 2414 }; 2415 2416 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits { 2417 u8 if_in_octets_high[0x20]; 2418 2419 u8 if_in_octets_low[0x20]; 2420 2421 u8 if_in_ucast_pkts_high[0x20]; 2422 2423 u8 if_in_ucast_pkts_low[0x20]; 2424 2425 u8 if_in_discards_high[0x20]; 2426 2427 u8 if_in_discards_low[0x20]; 2428 2429 u8 if_in_errors_high[0x20]; 2430 2431 u8 if_in_errors_low[0x20]; 2432 2433 u8 if_in_unknown_protos_high[0x20]; 2434 2435 u8 if_in_unknown_protos_low[0x20]; 2436 2437 u8 if_out_octets_high[0x20]; 2438 2439 u8 if_out_octets_low[0x20]; 2440 2441 u8 if_out_ucast_pkts_high[0x20]; 2442 2443 u8 if_out_ucast_pkts_low[0x20]; 2444 2445 u8 if_out_discards_high[0x20]; 2446 2447 u8 if_out_discards_low[0x20]; 2448 2449 u8 if_out_errors_high[0x20]; 2450 2451 u8 if_out_errors_low[0x20]; 2452 2453 u8 if_in_multicast_pkts_high[0x20]; 2454 2455 u8 if_in_multicast_pkts_low[0x20]; 2456 2457 u8 if_in_broadcast_pkts_high[0x20]; 2458 2459 u8 if_in_broadcast_pkts_low[0x20]; 2460 2461 u8 if_out_multicast_pkts_high[0x20]; 2462 2463 u8 if_out_multicast_pkts_low[0x20]; 2464 2465 u8 if_out_broadcast_pkts_high[0x20]; 2466 2467 u8 if_out_broadcast_pkts_low[0x20]; 2468 2469 u8 reserved_at_340[0x480]; 2470 }; 2471 2472 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits { 2473 u8 a_frames_transmitted_ok_high[0x20]; 2474 2475 u8 a_frames_transmitted_ok_low[0x20]; 2476 2477 u8 a_frames_received_ok_high[0x20]; 2478 2479 u8 a_frames_received_ok_low[0x20]; 2480 2481 u8 a_frame_check_sequence_errors_high[0x20]; 2482 2483 u8 a_frame_check_sequence_errors_low[0x20]; 2484 2485 u8 a_alignment_errors_high[0x20]; 2486 2487 u8 a_alignment_errors_low[0x20]; 2488 2489 u8 a_octets_transmitted_ok_high[0x20]; 2490 2491 u8 a_octets_transmitted_ok_low[0x20]; 2492 2493 u8 a_octets_received_ok_high[0x20]; 2494 2495 u8 a_octets_received_ok_low[0x20]; 2496 2497 u8 a_multicast_frames_xmitted_ok_high[0x20]; 2498 2499 u8 a_multicast_frames_xmitted_ok_low[0x20]; 2500 2501 u8 a_broadcast_frames_xmitted_ok_high[0x20]; 2502 2503 u8 a_broadcast_frames_xmitted_ok_low[0x20]; 2504 2505 u8 a_multicast_frames_received_ok_high[0x20]; 2506 2507 u8 a_multicast_frames_received_ok_low[0x20]; 2508 2509 u8 a_broadcast_frames_received_ok_high[0x20]; 2510 2511 u8 a_broadcast_frames_received_ok_low[0x20]; 2512 2513 u8 a_in_range_length_errors_high[0x20]; 2514 2515 u8 a_in_range_length_errors_low[0x20]; 2516 2517 u8 a_out_of_range_length_field_high[0x20]; 2518 2519 u8 a_out_of_range_length_field_low[0x20]; 2520 2521 u8 a_frame_too_long_errors_high[0x20]; 2522 2523 u8 a_frame_too_long_errors_low[0x20]; 2524 2525 u8 a_symbol_error_during_carrier_high[0x20]; 2526 2527 u8 a_symbol_error_during_carrier_low[0x20]; 2528 2529 u8 a_mac_control_frames_transmitted_high[0x20]; 2530 2531 u8 a_mac_control_frames_transmitted_low[0x20]; 2532 2533 u8 a_mac_control_frames_received_high[0x20]; 2534 2535 u8 a_mac_control_frames_received_low[0x20]; 2536 2537 u8 a_unsupported_opcodes_received_high[0x20]; 2538 2539 u8 a_unsupported_opcodes_received_low[0x20]; 2540 2541 u8 a_pause_mac_ctrl_frames_received_high[0x20]; 2542 2543 u8 a_pause_mac_ctrl_frames_received_low[0x20]; 2544 2545 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20]; 2546 2547 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20]; 2548 2549 u8 reserved_at_4c0[0x300]; 2550 }; 2551 2552 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits { 2553 u8 life_time_counter_high[0x20]; 2554 2555 u8 life_time_counter_low[0x20]; 2556 2557 u8 rx_errors[0x20]; 2558 2559 u8 tx_errors[0x20]; 2560 2561 u8 l0_to_recovery_eieos[0x20]; 2562 2563 u8 l0_to_recovery_ts[0x20]; 2564 2565 u8 l0_to_recovery_framing[0x20]; 2566 2567 u8 l0_to_recovery_retrain[0x20]; 2568 2569 u8 crc_error_dllp[0x20]; 2570 2571 u8 crc_error_tlp[0x20]; 2572 2573 u8 tx_overflow_buffer_pkt_high[0x20]; 2574 2575 u8 tx_overflow_buffer_pkt_low[0x20]; 2576 2577 u8 outbound_stalled_reads[0x20]; 2578 2579 u8 outbound_stalled_writes[0x20]; 2580 2581 u8 outbound_stalled_reads_events[0x20]; 2582 2583 u8 outbound_stalled_writes_events[0x20]; 2584 2585 u8 reserved_at_200[0x5c0]; 2586 }; 2587 2588 struct mlx5_ifc_cmd_inter_comp_event_bits { 2589 u8 command_completion_vector[0x20]; 2590 2591 u8 reserved_at_20[0xc0]; 2592 }; 2593 2594 struct mlx5_ifc_stall_vl_event_bits { 2595 u8 reserved_at_0[0x18]; 2596 u8 port_num[0x1]; 2597 u8 reserved_at_19[0x3]; 2598 u8 vl[0x4]; 2599 2600 u8 reserved_at_20[0xa0]; 2601 }; 2602 2603 struct mlx5_ifc_db_bf_congestion_event_bits { 2604 u8 event_subtype[0x8]; 2605 u8 reserved_at_8[0x8]; 2606 u8 congestion_level[0x8]; 2607 u8 reserved_at_18[0x8]; 2608 2609 u8 reserved_at_20[0xa0]; 2610 }; 2611 2612 struct mlx5_ifc_gpio_event_bits { 2613 u8 reserved_at_0[0x60]; 2614 2615 u8 gpio_event_hi[0x20]; 2616 2617 u8 gpio_event_lo[0x20]; 2618 2619 u8 reserved_at_a0[0x40]; 2620 }; 2621 2622 struct mlx5_ifc_port_state_change_event_bits { 2623 u8 reserved_at_0[0x40]; 2624 2625 u8 port_num[0x4]; 2626 u8 reserved_at_44[0x1c]; 2627 2628 u8 reserved_at_60[0x80]; 2629 }; 2630 2631 struct mlx5_ifc_dropped_packet_logged_bits { 2632 u8 reserved_at_0[0xe0]; 2633 }; 2634 2635 enum { 2636 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1, 2637 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2, 2638 }; 2639 2640 struct mlx5_ifc_cq_error_bits { 2641 u8 reserved_at_0[0x8]; 2642 u8 cqn[0x18]; 2643 2644 u8 reserved_at_20[0x20]; 2645 2646 u8 reserved_at_40[0x18]; 2647 u8 syndrome[0x8]; 2648 2649 u8 reserved_at_60[0x80]; 2650 }; 2651 2652 struct mlx5_ifc_rdma_page_fault_event_bits { 2653 u8 bytes_committed[0x20]; 2654 2655 u8 r_key[0x20]; 2656 2657 u8 reserved_at_40[0x10]; 2658 u8 packet_len[0x10]; 2659 2660 u8 rdma_op_len[0x20]; 2661 2662 u8 rdma_va[0x40]; 2663 2664 u8 reserved_at_c0[0x5]; 2665 u8 rdma[0x1]; 2666 u8 write[0x1]; 2667 u8 requestor[0x1]; 2668 u8 qp_number[0x18]; 2669 }; 2670 2671 struct mlx5_ifc_wqe_associated_page_fault_event_bits { 2672 u8 bytes_committed[0x20]; 2673 2674 u8 reserved_at_20[0x10]; 2675 u8 wqe_index[0x10]; 2676 2677 u8 reserved_at_40[0x10]; 2678 u8 len[0x10]; 2679 2680 u8 reserved_at_60[0x60]; 2681 2682 u8 reserved_at_c0[0x5]; 2683 u8 rdma[0x1]; 2684 u8 write_read[0x1]; 2685 u8 requestor[0x1]; 2686 u8 qpn[0x18]; 2687 }; 2688 2689 struct mlx5_ifc_qp_events_bits { 2690 u8 reserved_at_0[0xa0]; 2691 2692 u8 type[0x8]; 2693 u8 reserved_at_a8[0x18]; 2694 2695 u8 reserved_at_c0[0x8]; 2696 u8 qpn_rqn_sqn[0x18]; 2697 }; 2698 2699 struct mlx5_ifc_dct_events_bits { 2700 u8 reserved_at_0[0xc0]; 2701 2702 u8 reserved_at_c0[0x8]; 2703 u8 dct_number[0x18]; 2704 }; 2705 2706 struct mlx5_ifc_comp_event_bits { 2707 u8 reserved_at_0[0xc0]; 2708 2709 u8 reserved_at_c0[0x8]; 2710 u8 cq_number[0x18]; 2711 }; 2712 2713 enum { 2714 MLX5_QPC_STATE_RST = 0x0, 2715 MLX5_QPC_STATE_INIT = 0x1, 2716 MLX5_QPC_STATE_RTR = 0x2, 2717 MLX5_QPC_STATE_RTS = 0x3, 2718 MLX5_QPC_STATE_SQER = 0x4, 2719 MLX5_QPC_STATE_ERR = 0x6, 2720 MLX5_QPC_STATE_SQD = 0x7, 2721 MLX5_QPC_STATE_SUSPENDED = 0x9, 2722 }; 2723 2724 enum { 2725 MLX5_QPC_ST_RC = 0x0, 2726 MLX5_QPC_ST_UC = 0x1, 2727 MLX5_QPC_ST_UD = 0x2, 2728 MLX5_QPC_ST_XRC = 0x3, 2729 MLX5_QPC_ST_DCI = 0x5, 2730 MLX5_QPC_ST_QP0 = 0x7, 2731 MLX5_QPC_ST_QP1 = 0x8, 2732 MLX5_QPC_ST_RAW_DATAGRAM = 0x9, 2733 MLX5_QPC_ST_REG_UMR = 0xc, 2734 }; 2735 2736 enum { 2737 MLX5_QPC_PM_STATE_ARMED = 0x0, 2738 MLX5_QPC_PM_STATE_REARM = 0x1, 2739 MLX5_QPC_PM_STATE_RESERVED = 0x2, 2740 MLX5_QPC_PM_STATE_MIGRATED = 0x3, 2741 }; 2742 2743 enum { 2744 MLX5_QPC_OFFLOAD_TYPE_RNDV = 0x1, 2745 }; 2746 2747 enum { 2748 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0, 2749 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1, 2750 }; 2751 2752 enum { 2753 MLX5_QPC_MTU_256_BYTES = 0x1, 2754 MLX5_QPC_MTU_512_BYTES = 0x2, 2755 MLX5_QPC_MTU_1K_BYTES = 0x3, 2756 MLX5_QPC_MTU_2K_BYTES = 0x4, 2757 MLX5_QPC_MTU_4K_BYTES = 0x5, 2758 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7, 2759 }; 2760 2761 enum { 2762 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1, 2763 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2, 2764 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3, 2765 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4, 2766 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5, 2767 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6, 2768 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7, 2769 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8, 2770 }; 2771 2772 enum { 2773 MLX5_QPC_CS_REQ_DISABLE = 0x0, 2774 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11, 2775 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22, 2776 }; 2777 2778 enum { 2779 MLX5_QPC_CS_RES_DISABLE = 0x0, 2780 MLX5_QPC_CS_RES_UP_TO_32B = 0x1, 2781 MLX5_QPC_CS_RES_UP_TO_64B = 0x2, 2782 }; 2783 2784 struct mlx5_ifc_qpc_bits { 2785 u8 state[0x4]; 2786 u8 lag_tx_port_affinity[0x4]; 2787 u8 st[0x8]; 2788 u8 reserved_at_10[0x3]; 2789 u8 pm_state[0x2]; 2790 u8 reserved_at_15[0x1]; 2791 u8 req_e2e_credit_mode[0x2]; 2792 u8 offload_type[0x4]; 2793 u8 end_padding_mode[0x2]; 2794 u8 reserved_at_1e[0x2]; 2795 2796 u8 wq_signature[0x1]; 2797 u8 block_lb_mc[0x1]; 2798 u8 atomic_like_write_en[0x1]; 2799 u8 latency_sensitive[0x1]; 2800 u8 reserved_at_24[0x1]; 2801 u8 drain_sigerr[0x1]; 2802 u8 reserved_at_26[0x2]; 2803 u8 pd[0x18]; 2804 2805 u8 mtu[0x3]; 2806 u8 log_msg_max[0x5]; 2807 u8 reserved_at_48[0x1]; 2808 u8 log_rq_size[0x4]; 2809 u8 log_rq_stride[0x3]; 2810 u8 no_sq[0x1]; 2811 u8 log_sq_size[0x4]; 2812 u8 reserved_at_55[0x6]; 2813 u8 rlky[0x1]; 2814 u8 ulp_stateless_offload_mode[0x4]; 2815 2816 u8 counter_set_id[0x8]; 2817 u8 uar_page[0x18]; 2818 2819 u8 reserved_at_80[0x8]; 2820 u8 user_index[0x18]; 2821 2822 u8 reserved_at_a0[0x3]; 2823 u8 log_page_size[0x5]; 2824 u8 remote_qpn[0x18]; 2825 2826 struct mlx5_ifc_ads_bits primary_address_path; 2827 2828 struct mlx5_ifc_ads_bits secondary_address_path; 2829 2830 u8 log_ack_req_freq[0x4]; 2831 u8 reserved_at_384[0x4]; 2832 u8 log_sra_max[0x3]; 2833 u8 reserved_at_38b[0x2]; 2834 u8 retry_count[0x3]; 2835 u8 rnr_retry[0x3]; 2836 u8 reserved_at_393[0x1]; 2837 u8 fre[0x1]; 2838 u8 cur_rnr_retry[0x3]; 2839 u8 cur_retry_count[0x3]; 2840 u8 reserved_at_39b[0x5]; 2841 2842 u8 reserved_at_3a0[0x20]; 2843 2844 u8 reserved_at_3c0[0x8]; 2845 u8 next_send_psn[0x18]; 2846 2847 u8 reserved_at_3e0[0x8]; 2848 u8 cqn_snd[0x18]; 2849 2850 u8 reserved_at_400[0x8]; 2851 u8 deth_sqpn[0x18]; 2852 2853 u8 reserved_at_420[0x20]; 2854 2855 u8 reserved_at_440[0x8]; 2856 u8 last_acked_psn[0x18]; 2857 2858 u8 reserved_at_460[0x8]; 2859 u8 ssn[0x18]; 2860 2861 u8 reserved_at_480[0x8]; 2862 u8 log_rra_max[0x3]; 2863 u8 reserved_at_48b[0x1]; 2864 u8 atomic_mode[0x4]; 2865 u8 rre[0x1]; 2866 u8 rwe[0x1]; 2867 u8 rae[0x1]; 2868 u8 reserved_at_493[0x1]; 2869 u8 page_offset[0x6]; 2870 u8 reserved_at_49a[0x3]; 2871 u8 cd_slave_receive[0x1]; 2872 u8 cd_slave_send[0x1]; 2873 u8 cd_master[0x1]; 2874 2875 u8 reserved_at_4a0[0x3]; 2876 u8 min_rnr_nak[0x5]; 2877 u8 next_rcv_psn[0x18]; 2878 2879 u8 reserved_at_4c0[0x8]; 2880 u8 xrcd[0x18]; 2881 2882 u8 reserved_at_4e0[0x8]; 2883 u8 cqn_rcv[0x18]; 2884 2885 u8 dbr_addr[0x40]; 2886 2887 u8 q_key[0x20]; 2888 2889 u8 reserved_at_560[0x5]; 2890 u8 rq_type[0x3]; 2891 u8 srqn_rmpn_xrqn[0x18]; 2892 2893 u8 reserved_at_580[0x8]; 2894 u8 rmsn[0x18]; 2895 2896 u8 hw_sq_wqebb_counter[0x10]; 2897 u8 sw_sq_wqebb_counter[0x10]; 2898 2899 u8 hw_rq_counter[0x20]; 2900 2901 u8 sw_rq_counter[0x20]; 2902 2903 u8 reserved_at_600[0x20]; 2904 2905 u8 reserved_at_620[0xf]; 2906 u8 cgs[0x1]; 2907 u8 cs_req[0x8]; 2908 u8 cs_res[0x8]; 2909 2910 u8 dc_access_key[0x40]; 2911 2912 u8 reserved_at_680[0x3]; 2913 u8 dbr_umem_valid[0x1]; 2914 2915 u8 reserved_at_684[0xbc]; 2916 }; 2917 2918 struct mlx5_ifc_roce_addr_layout_bits { 2919 u8 source_l3_address[16][0x8]; 2920 2921 u8 reserved_at_80[0x3]; 2922 u8 vlan_valid[0x1]; 2923 u8 vlan_id[0xc]; 2924 u8 source_mac_47_32[0x10]; 2925 2926 u8 source_mac_31_0[0x20]; 2927 2928 u8 reserved_at_c0[0x14]; 2929 u8 roce_l3_type[0x4]; 2930 u8 roce_version[0x8]; 2931 2932 u8 reserved_at_e0[0x20]; 2933 }; 2934 2935 union mlx5_ifc_hca_cap_union_bits { 2936 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap; 2937 struct mlx5_ifc_odp_cap_bits odp_cap; 2938 struct mlx5_ifc_atomic_caps_bits atomic_caps; 2939 struct mlx5_ifc_roce_cap_bits roce_cap; 2940 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps; 2941 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap; 2942 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap; 2943 struct mlx5_ifc_e_switch_cap_bits e_switch_cap; 2944 struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap; 2945 struct mlx5_ifc_qos_cap_bits qos_cap; 2946 struct mlx5_ifc_debug_cap_bits debug_cap; 2947 struct mlx5_ifc_fpga_cap_bits fpga_cap; 2948 struct mlx5_ifc_tls_cap_bits tls_cap; 2949 struct mlx5_ifc_device_mem_cap_bits device_mem_cap; 2950 struct mlx5_ifc_device_virtio_emulation_cap_bits virtio_emulation_cap; 2951 u8 reserved_at_0[0x8000]; 2952 }; 2953 2954 enum { 2955 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1, 2956 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2, 2957 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4, 2958 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8, 2959 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT = 0x10, 2960 MLX5_FLOW_CONTEXT_ACTION_DECAP = 0x20, 2961 MLX5_FLOW_CONTEXT_ACTION_MOD_HDR = 0x40, 2962 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP = 0x80, 2963 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100, 2964 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2 = 0x400, 2965 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2 = 0x800, 2966 }; 2967 2968 enum { 2969 MLX5_FLOW_CONTEXT_FLOW_SOURCE_ANY_VPORT = 0x0, 2970 MLX5_FLOW_CONTEXT_FLOW_SOURCE_UPLINK = 0x1, 2971 MLX5_FLOW_CONTEXT_FLOW_SOURCE_LOCAL_VPORT = 0x2, 2972 }; 2973 2974 struct mlx5_ifc_vlan_bits { 2975 u8 ethtype[0x10]; 2976 u8 prio[0x3]; 2977 u8 cfi[0x1]; 2978 u8 vid[0xc]; 2979 }; 2980 2981 struct mlx5_ifc_flow_context_bits { 2982 struct mlx5_ifc_vlan_bits push_vlan; 2983 2984 u8 group_id[0x20]; 2985 2986 u8 reserved_at_40[0x8]; 2987 u8 flow_tag[0x18]; 2988 2989 u8 reserved_at_60[0x10]; 2990 u8 action[0x10]; 2991 2992 u8 extended_destination[0x1]; 2993 u8 reserved_at_81[0x1]; 2994 u8 flow_source[0x2]; 2995 u8 reserved_at_84[0x4]; 2996 u8 destination_list_size[0x18]; 2997 2998 u8 reserved_at_a0[0x8]; 2999 u8 flow_counter_list_size[0x18]; 3000 3001 u8 packet_reformat_id[0x20]; 3002 3003 u8 modify_header_id[0x20]; 3004 3005 struct mlx5_ifc_vlan_bits push_vlan_2; 3006 3007 u8 reserved_at_120[0xe0]; 3008 3009 struct mlx5_ifc_fte_match_param_bits match_value; 3010 3011 u8 reserved_at_1200[0x600]; 3012 3013 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[0]; 3014 }; 3015 3016 enum { 3017 MLX5_XRC_SRQC_STATE_GOOD = 0x0, 3018 MLX5_XRC_SRQC_STATE_ERROR = 0x1, 3019 }; 3020 3021 struct mlx5_ifc_xrc_srqc_bits { 3022 u8 state[0x4]; 3023 u8 log_xrc_srq_size[0x4]; 3024 u8 reserved_at_8[0x18]; 3025 3026 u8 wq_signature[0x1]; 3027 u8 cont_srq[0x1]; 3028 u8 reserved_at_22[0x1]; 3029 u8 rlky[0x1]; 3030 u8 basic_cyclic_rcv_wqe[0x1]; 3031 u8 log_rq_stride[0x3]; 3032 u8 xrcd[0x18]; 3033 3034 u8 page_offset[0x6]; 3035 u8 reserved_at_46[0x1]; 3036 u8 dbr_umem_valid[0x1]; 3037 u8 cqn[0x18]; 3038 3039 u8 reserved_at_60[0x20]; 3040 3041 u8 user_index_equal_xrc_srqn[0x1]; 3042 u8 reserved_at_81[0x1]; 3043 u8 log_page_size[0x6]; 3044 u8 user_index[0x18]; 3045 3046 u8 reserved_at_a0[0x20]; 3047 3048 u8 reserved_at_c0[0x8]; 3049 u8 pd[0x18]; 3050 3051 u8 lwm[0x10]; 3052 u8 wqe_cnt[0x10]; 3053 3054 u8 reserved_at_100[0x40]; 3055 3056 u8 db_record_addr_h[0x20]; 3057 3058 u8 db_record_addr_l[0x1e]; 3059 u8 reserved_at_17e[0x2]; 3060 3061 u8 reserved_at_180[0x80]; 3062 }; 3063 3064 struct mlx5_ifc_vnic_diagnostic_statistics_bits { 3065 u8 counter_error_queues[0x20]; 3066 3067 u8 total_error_queues[0x20]; 3068 3069 u8 send_queue_priority_update_flow[0x20]; 3070 3071 u8 reserved_at_60[0x20]; 3072 3073 u8 nic_receive_steering_discard[0x40]; 3074 3075 u8 receive_discard_vport_down[0x40]; 3076 3077 u8 transmit_discard_vport_down[0x40]; 3078 3079 u8 reserved_at_140[0xa0]; 3080 3081 u8 internal_rq_out_of_buffer[0x20]; 3082 3083 u8 reserved_at_200[0xe00]; 3084 }; 3085 3086 struct mlx5_ifc_traffic_counter_bits { 3087 u8 packets[0x40]; 3088 3089 u8 octets[0x40]; 3090 }; 3091 3092 struct mlx5_ifc_tisc_bits { 3093 u8 strict_lag_tx_port_affinity[0x1]; 3094 u8 tls_en[0x1]; 3095 u8 reserved_at_2[0x2]; 3096 u8 lag_tx_port_affinity[0x04]; 3097 3098 u8 reserved_at_8[0x4]; 3099 u8 prio[0x4]; 3100 u8 reserved_at_10[0x10]; 3101 3102 u8 reserved_at_20[0x100]; 3103 3104 u8 reserved_at_120[0x8]; 3105 u8 transport_domain[0x18]; 3106 3107 u8 reserved_at_140[0x8]; 3108 u8 underlay_qpn[0x18]; 3109 3110 u8 reserved_at_160[0x8]; 3111 u8 pd[0x18]; 3112 3113 u8 reserved_at_180[0x380]; 3114 }; 3115 3116 enum { 3117 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0, 3118 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1, 3119 }; 3120 3121 enum { 3122 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO = 0x1, 3123 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO = 0x2, 3124 }; 3125 3126 enum { 3127 MLX5_RX_HASH_FN_NONE = 0x0, 3128 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1, 3129 MLX5_RX_HASH_FN_TOEPLITZ = 0x2, 3130 }; 3131 3132 enum { 3133 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST = 0x1, 3134 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST = 0x2, 3135 }; 3136 3137 struct mlx5_ifc_tirc_bits { 3138 u8 reserved_at_0[0x20]; 3139 3140 u8 disp_type[0x4]; 3141 u8 tls_en[0x1]; 3142 u8 reserved_at_25[0x1b]; 3143 3144 u8 reserved_at_40[0x40]; 3145 3146 u8 reserved_at_80[0x4]; 3147 u8 lro_timeout_period_usecs[0x10]; 3148 u8 lro_enable_mask[0x4]; 3149 u8 lro_max_ip_payload_size[0x8]; 3150 3151 u8 reserved_at_a0[0x40]; 3152 3153 u8 reserved_at_e0[0x8]; 3154 u8 inline_rqn[0x18]; 3155 3156 u8 rx_hash_symmetric[0x1]; 3157 u8 reserved_at_101[0x1]; 3158 u8 tunneled_offload_en[0x1]; 3159 u8 reserved_at_103[0x5]; 3160 u8 indirect_table[0x18]; 3161 3162 u8 rx_hash_fn[0x4]; 3163 u8 reserved_at_124[0x2]; 3164 u8 self_lb_block[0x2]; 3165 u8 transport_domain[0x18]; 3166 3167 u8 rx_hash_toeplitz_key[10][0x20]; 3168 3169 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer; 3170 3171 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner; 3172 3173 u8 reserved_at_2c0[0x4c0]; 3174 }; 3175 3176 enum { 3177 MLX5_SRQC_STATE_GOOD = 0x0, 3178 MLX5_SRQC_STATE_ERROR = 0x1, 3179 }; 3180 3181 struct mlx5_ifc_srqc_bits { 3182 u8 state[0x4]; 3183 u8 log_srq_size[0x4]; 3184 u8 reserved_at_8[0x18]; 3185 3186 u8 wq_signature[0x1]; 3187 u8 cont_srq[0x1]; 3188 u8 reserved_at_22[0x1]; 3189 u8 rlky[0x1]; 3190 u8 reserved_at_24[0x1]; 3191 u8 log_rq_stride[0x3]; 3192 u8 xrcd[0x18]; 3193 3194 u8 page_offset[0x6]; 3195 u8 reserved_at_46[0x2]; 3196 u8 cqn[0x18]; 3197 3198 u8 reserved_at_60[0x20]; 3199 3200 u8 reserved_at_80[0x2]; 3201 u8 log_page_size[0x6]; 3202 u8 reserved_at_88[0x18]; 3203 3204 u8 reserved_at_a0[0x20]; 3205 3206 u8 reserved_at_c0[0x8]; 3207 u8 pd[0x18]; 3208 3209 u8 lwm[0x10]; 3210 u8 wqe_cnt[0x10]; 3211 3212 u8 reserved_at_100[0x40]; 3213 3214 u8 dbr_addr[0x40]; 3215 3216 u8 reserved_at_180[0x80]; 3217 }; 3218 3219 enum { 3220 MLX5_SQC_STATE_RST = 0x0, 3221 MLX5_SQC_STATE_RDY = 0x1, 3222 MLX5_SQC_STATE_ERR = 0x3, 3223 }; 3224 3225 struct mlx5_ifc_sqc_bits { 3226 u8 rlky[0x1]; 3227 u8 cd_master[0x1]; 3228 u8 fre[0x1]; 3229 u8 flush_in_error_en[0x1]; 3230 u8 allow_multi_pkt_send_wqe[0x1]; 3231 u8 min_wqe_inline_mode[0x3]; 3232 u8 state[0x4]; 3233 u8 reg_umr[0x1]; 3234 u8 allow_swp[0x1]; 3235 u8 hairpin[0x1]; 3236 u8 reserved_at_f[0x11]; 3237 3238 u8 reserved_at_20[0x8]; 3239 u8 user_index[0x18]; 3240 3241 u8 reserved_at_40[0x8]; 3242 u8 cqn[0x18]; 3243 3244 u8 reserved_at_60[0x8]; 3245 u8 hairpin_peer_rq[0x18]; 3246 3247 u8 reserved_at_80[0x10]; 3248 u8 hairpin_peer_vhca[0x10]; 3249 3250 u8 reserved_at_a0[0x50]; 3251 3252 u8 packet_pacing_rate_limit_index[0x10]; 3253 u8 tis_lst_sz[0x10]; 3254 u8 reserved_at_110[0x10]; 3255 3256 u8 reserved_at_120[0x40]; 3257 3258 u8 reserved_at_160[0x8]; 3259 u8 tis_num_0[0x18]; 3260 3261 struct mlx5_ifc_wq_bits wq; 3262 }; 3263 3264 enum { 3265 SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0, 3266 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1, 3267 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2, 3268 SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3, 3269 }; 3270 3271 enum { 3272 ELEMENT_TYPE_CAP_MASK_TASR = 1 << 0, 3273 ELEMENT_TYPE_CAP_MASK_VPORT = 1 << 1, 3274 ELEMENT_TYPE_CAP_MASK_VPORT_TC = 1 << 2, 3275 ELEMENT_TYPE_CAP_MASK_PARA_VPORT_TC = 1 << 3, 3276 }; 3277 3278 struct mlx5_ifc_scheduling_context_bits { 3279 u8 element_type[0x8]; 3280 u8 reserved_at_8[0x18]; 3281 3282 u8 element_attributes[0x20]; 3283 3284 u8 parent_element_id[0x20]; 3285 3286 u8 reserved_at_60[0x40]; 3287 3288 u8 bw_share[0x20]; 3289 3290 u8 max_average_bw[0x20]; 3291 3292 u8 reserved_at_e0[0x120]; 3293 }; 3294 3295 struct mlx5_ifc_rqtc_bits { 3296 u8 reserved_at_0[0xa0]; 3297 3298 u8 reserved_at_a0[0x10]; 3299 u8 rqt_max_size[0x10]; 3300 3301 u8 reserved_at_c0[0x10]; 3302 u8 rqt_actual_size[0x10]; 3303 3304 u8 reserved_at_e0[0x6a0]; 3305 3306 struct mlx5_ifc_rq_num_bits rq_num[0]; 3307 }; 3308 3309 enum { 3310 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0, 3311 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1, 3312 }; 3313 3314 enum { 3315 MLX5_RQC_STATE_RST = 0x0, 3316 MLX5_RQC_STATE_RDY = 0x1, 3317 MLX5_RQC_STATE_ERR = 0x3, 3318 }; 3319 3320 struct mlx5_ifc_rqc_bits { 3321 u8 rlky[0x1]; 3322 u8 delay_drop_en[0x1]; 3323 u8 scatter_fcs[0x1]; 3324 u8 vsd[0x1]; 3325 u8 mem_rq_type[0x4]; 3326 u8 state[0x4]; 3327 u8 reserved_at_c[0x1]; 3328 u8 flush_in_error_en[0x1]; 3329 u8 hairpin[0x1]; 3330 u8 reserved_at_f[0x11]; 3331 3332 u8 reserved_at_20[0x8]; 3333 u8 user_index[0x18]; 3334 3335 u8 reserved_at_40[0x8]; 3336 u8 cqn[0x18]; 3337 3338 u8 counter_set_id[0x8]; 3339 u8 reserved_at_68[0x18]; 3340 3341 u8 reserved_at_80[0x8]; 3342 u8 rmpn[0x18]; 3343 3344 u8 reserved_at_a0[0x8]; 3345 u8 hairpin_peer_sq[0x18]; 3346 3347 u8 reserved_at_c0[0x10]; 3348 u8 hairpin_peer_vhca[0x10]; 3349 3350 u8 reserved_at_e0[0xa0]; 3351 3352 struct mlx5_ifc_wq_bits wq; 3353 }; 3354 3355 enum { 3356 MLX5_RMPC_STATE_RDY = 0x1, 3357 MLX5_RMPC_STATE_ERR = 0x3, 3358 }; 3359 3360 struct mlx5_ifc_rmpc_bits { 3361 u8 reserved_at_0[0x8]; 3362 u8 state[0x4]; 3363 u8 reserved_at_c[0x14]; 3364 3365 u8 basic_cyclic_rcv_wqe[0x1]; 3366 u8 reserved_at_21[0x1f]; 3367 3368 u8 reserved_at_40[0x140]; 3369 3370 struct mlx5_ifc_wq_bits wq; 3371 }; 3372 3373 struct mlx5_ifc_nic_vport_context_bits { 3374 u8 reserved_at_0[0x5]; 3375 u8 min_wqe_inline_mode[0x3]; 3376 u8 reserved_at_8[0x15]; 3377 u8 disable_mc_local_lb[0x1]; 3378 u8 disable_uc_local_lb[0x1]; 3379 u8 roce_en[0x1]; 3380 3381 u8 arm_change_event[0x1]; 3382 u8 reserved_at_21[0x1a]; 3383 u8 event_on_mtu[0x1]; 3384 u8 event_on_promisc_change[0x1]; 3385 u8 event_on_vlan_change[0x1]; 3386 u8 event_on_mc_address_change[0x1]; 3387 u8 event_on_uc_address_change[0x1]; 3388 3389 u8 reserved_at_40[0xc]; 3390 3391 u8 affiliation_criteria[0x4]; 3392 u8 affiliated_vhca_id[0x10]; 3393 3394 u8 reserved_at_60[0xd0]; 3395 3396 u8 mtu[0x10]; 3397 3398 u8 system_image_guid[0x40]; 3399 u8 port_guid[0x40]; 3400 u8 node_guid[0x40]; 3401 3402 u8 reserved_at_200[0x140]; 3403 u8 qkey_violation_counter[0x10]; 3404 u8 reserved_at_350[0x430]; 3405 3406 u8 promisc_uc[0x1]; 3407 u8 promisc_mc[0x1]; 3408 u8 promisc_all[0x1]; 3409 u8 reserved_at_783[0x2]; 3410 u8 allowed_list_type[0x3]; 3411 u8 reserved_at_788[0xc]; 3412 u8 allowed_list_size[0xc]; 3413 3414 struct mlx5_ifc_mac_address_layout_bits permanent_address; 3415 3416 u8 reserved_at_7e0[0x20]; 3417 3418 u8 current_uc_mac_address[0][0x40]; 3419 }; 3420 3421 enum { 3422 MLX5_MKC_ACCESS_MODE_PA = 0x0, 3423 MLX5_MKC_ACCESS_MODE_MTT = 0x1, 3424 MLX5_MKC_ACCESS_MODE_KLMS = 0x2, 3425 MLX5_MKC_ACCESS_MODE_KSM = 0x3, 3426 MLX5_MKC_ACCESS_MODE_SW_ICM = 0x4, 3427 MLX5_MKC_ACCESS_MODE_MEMIC = 0x5, 3428 }; 3429 3430 struct mlx5_ifc_mkc_bits { 3431 u8 reserved_at_0[0x1]; 3432 u8 free[0x1]; 3433 u8 reserved_at_2[0x1]; 3434 u8 access_mode_4_2[0x3]; 3435 u8 reserved_at_6[0x7]; 3436 u8 relaxed_ordering_write[0x1]; 3437 u8 reserved_at_e[0x1]; 3438 u8 small_fence_on_rdma_read_response[0x1]; 3439 u8 umr_en[0x1]; 3440 u8 a[0x1]; 3441 u8 rw[0x1]; 3442 u8 rr[0x1]; 3443 u8 lw[0x1]; 3444 u8 lr[0x1]; 3445 u8 access_mode_1_0[0x2]; 3446 u8 reserved_at_18[0x8]; 3447 3448 u8 qpn[0x18]; 3449 u8 mkey_7_0[0x8]; 3450 3451 u8 reserved_at_40[0x20]; 3452 3453 u8 length64[0x1]; 3454 u8 bsf_en[0x1]; 3455 u8 sync_umr[0x1]; 3456 u8 reserved_at_63[0x2]; 3457 u8 expected_sigerr_count[0x1]; 3458 u8 reserved_at_66[0x1]; 3459 u8 en_rinval[0x1]; 3460 u8 pd[0x18]; 3461 3462 u8 start_addr[0x40]; 3463 3464 u8 len[0x40]; 3465 3466 u8 bsf_octword_size[0x20]; 3467 3468 u8 reserved_at_120[0x80]; 3469 3470 u8 translations_octword_size[0x20]; 3471 3472 u8 reserved_at_1c0[0x19]; 3473 u8 relaxed_ordering_read[0x1]; 3474 u8 reserved_at_1d9[0x1]; 3475 u8 log_page_size[0x5]; 3476 3477 u8 reserved_at_1e0[0x20]; 3478 }; 3479 3480 struct mlx5_ifc_pkey_bits { 3481 u8 reserved_at_0[0x10]; 3482 u8 pkey[0x10]; 3483 }; 3484 3485 struct mlx5_ifc_array128_auto_bits { 3486 u8 array128_auto[16][0x8]; 3487 }; 3488 3489 struct mlx5_ifc_hca_vport_context_bits { 3490 u8 field_select[0x20]; 3491 3492 u8 reserved_at_20[0xe0]; 3493 3494 u8 sm_virt_aware[0x1]; 3495 u8 has_smi[0x1]; 3496 u8 has_raw[0x1]; 3497 u8 grh_required[0x1]; 3498 u8 reserved_at_104[0xc]; 3499 u8 port_physical_state[0x4]; 3500 u8 vport_state_policy[0x4]; 3501 u8 port_state[0x4]; 3502 u8 vport_state[0x4]; 3503 3504 u8 reserved_at_120[0x20]; 3505 3506 u8 system_image_guid[0x40]; 3507 3508 u8 port_guid[0x40]; 3509 3510 u8 node_guid[0x40]; 3511 3512 u8 cap_mask1[0x20]; 3513 3514 u8 cap_mask1_field_select[0x20]; 3515 3516 u8 cap_mask2[0x20]; 3517 3518 u8 cap_mask2_field_select[0x20]; 3519 3520 u8 reserved_at_280[0x80]; 3521 3522 u8 lid[0x10]; 3523 u8 reserved_at_310[0x4]; 3524 u8 init_type_reply[0x4]; 3525 u8 lmc[0x3]; 3526 u8 subnet_timeout[0x5]; 3527 3528 u8 sm_lid[0x10]; 3529 u8 sm_sl[0x4]; 3530 u8 reserved_at_334[0xc]; 3531 3532 u8 qkey_violation_counter[0x10]; 3533 u8 pkey_violation_counter[0x10]; 3534 3535 u8 reserved_at_360[0xca0]; 3536 }; 3537 3538 struct mlx5_ifc_esw_vport_context_bits { 3539 u8 fdb_to_vport_reg_c[0x1]; 3540 u8 reserved_at_1[0x2]; 3541 u8 vport_svlan_strip[0x1]; 3542 u8 vport_cvlan_strip[0x1]; 3543 u8 vport_svlan_insert[0x1]; 3544 u8 vport_cvlan_insert[0x2]; 3545 u8 fdb_to_vport_reg_c_id[0x8]; 3546 u8 reserved_at_10[0x10]; 3547 3548 u8 reserved_at_20[0x20]; 3549 3550 u8 svlan_cfi[0x1]; 3551 u8 svlan_pcp[0x3]; 3552 u8 svlan_id[0xc]; 3553 u8 cvlan_cfi[0x1]; 3554 u8 cvlan_pcp[0x3]; 3555 u8 cvlan_id[0xc]; 3556 3557 u8 reserved_at_60[0x720]; 3558 3559 u8 sw_steering_vport_icm_address_rx[0x40]; 3560 3561 u8 sw_steering_vport_icm_address_tx[0x40]; 3562 }; 3563 3564 enum { 3565 MLX5_EQC_STATUS_OK = 0x0, 3566 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa, 3567 }; 3568 3569 enum { 3570 MLX5_EQC_ST_ARMED = 0x9, 3571 MLX5_EQC_ST_FIRED = 0xa, 3572 }; 3573 3574 struct mlx5_ifc_eqc_bits { 3575 u8 status[0x4]; 3576 u8 reserved_at_4[0x9]; 3577 u8 ec[0x1]; 3578 u8 oi[0x1]; 3579 u8 reserved_at_f[0x5]; 3580 u8 st[0x4]; 3581 u8 reserved_at_18[0x8]; 3582 3583 u8 reserved_at_20[0x20]; 3584 3585 u8 reserved_at_40[0x14]; 3586 u8 page_offset[0x6]; 3587 u8 reserved_at_5a[0x6]; 3588 3589 u8 reserved_at_60[0x3]; 3590 u8 log_eq_size[0x5]; 3591 u8 uar_page[0x18]; 3592 3593 u8 reserved_at_80[0x20]; 3594 3595 u8 reserved_at_a0[0x18]; 3596 u8 intr[0x8]; 3597 3598 u8 reserved_at_c0[0x3]; 3599 u8 log_page_size[0x5]; 3600 u8 reserved_at_c8[0x18]; 3601 3602 u8 reserved_at_e0[0x60]; 3603 3604 u8 reserved_at_140[0x8]; 3605 u8 consumer_counter[0x18]; 3606 3607 u8 reserved_at_160[0x8]; 3608 u8 producer_counter[0x18]; 3609 3610 u8 reserved_at_180[0x80]; 3611 }; 3612 3613 enum { 3614 MLX5_DCTC_STATE_ACTIVE = 0x0, 3615 MLX5_DCTC_STATE_DRAINING = 0x1, 3616 MLX5_DCTC_STATE_DRAINED = 0x2, 3617 }; 3618 3619 enum { 3620 MLX5_DCTC_CS_RES_DISABLE = 0x0, 3621 MLX5_DCTC_CS_RES_NA = 0x1, 3622 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2, 3623 }; 3624 3625 enum { 3626 MLX5_DCTC_MTU_256_BYTES = 0x1, 3627 MLX5_DCTC_MTU_512_BYTES = 0x2, 3628 MLX5_DCTC_MTU_1K_BYTES = 0x3, 3629 MLX5_DCTC_MTU_2K_BYTES = 0x4, 3630 MLX5_DCTC_MTU_4K_BYTES = 0x5, 3631 }; 3632 3633 struct mlx5_ifc_dctc_bits { 3634 u8 reserved_at_0[0x4]; 3635 u8 state[0x4]; 3636 u8 reserved_at_8[0x18]; 3637 3638 u8 reserved_at_20[0x8]; 3639 u8 user_index[0x18]; 3640 3641 u8 reserved_at_40[0x8]; 3642 u8 cqn[0x18]; 3643 3644 u8 counter_set_id[0x8]; 3645 u8 atomic_mode[0x4]; 3646 u8 rre[0x1]; 3647 u8 rwe[0x1]; 3648 u8 rae[0x1]; 3649 u8 atomic_like_write_en[0x1]; 3650 u8 latency_sensitive[0x1]; 3651 u8 rlky[0x1]; 3652 u8 free_ar[0x1]; 3653 u8 reserved_at_73[0xd]; 3654 3655 u8 reserved_at_80[0x8]; 3656 u8 cs_res[0x8]; 3657 u8 reserved_at_90[0x3]; 3658 u8 min_rnr_nak[0x5]; 3659 u8 reserved_at_98[0x8]; 3660 3661 u8 reserved_at_a0[0x8]; 3662 u8 srqn_xrqn[0x18]; 3663 3664 u8 reserved_at_c0[0x8]; 3665 u8 pd[0x18]; 3666 3667 u8 tclass[0x8]; 3668 u8 reserved_at_e8[0x4]; 3669 u8 flow_label[0x14]; 3670 3671 u8 dc_access_key[0x40]; 3672 3673 u8 reserved_at_140[0x5]; 3674 u8 mtu[0x3]; 3675 u8 port[0x8]; 3676 u8 pkey_index[0x10]; 3677 3678 u8 reserved_at_160[0x8]; 3679 u8 my_addr_index[0x8]; 3680 u8 reserved_at_170[0x8]; 3681 u8 hop_limit[0x8]; 3682 3683 u8 dc_access_key_violation_count[0x20]; 3684 3685 u8 reserved_at_1a0[0x14]; 3686 u8 dei_cfi[0x1]; 3687 u8 eth_prio[0x3]; 3688 u8 ecn[0x2]; 3689 u8 dscp[0x6]; 3690 3691 u8 reserved_at_1c0[0x40]; 3692 }; 3693 3694 enum { 3695 MLX5_CQC_STATUS_OK = 0x0, 3696 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9, 3697 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa, 3698 }; 3699 3700 enum { 3701 MLX5_CQC_CQE_SZ_64_BYTES = 0x0, 3702 MLX5_CQC_CQE_SZ_128_BYTES = 0x1, 3703 }; 3704 3705 enum { 3706 MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED = 0x6, 3707 MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED = 0x9, 3708 MLX5_CQC_ST_FIRED = 0xa, 3709 }; 3710 3711 enum { 3712 MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0, 3713 MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1, 3714 MLX5_CQ_PERIOD_NUM_MODES 3715 }; 3716 3717 struct mlx5_ifc_cqc_bits { 3718 u8 status[0x4]; 3719 u8 reserved_at_4[0x2]; 3720 u8 dbr_umem_valid[0x1]; 3721 u8 reserved_at_7[0x1]; 3722 u8 cqe_sz[0x3]; 3723 u8 cc[0x1]; 3724 u8 reserved_at_c[0x1]; 3725 u8 scqe_break_moderation_en[0x1]; 3726 u8 oi[0x1]; 3727 u8 cq_period_mode[0x2]; 3728 u8 cqe_comp_en[0x1]; 3729 u8 mini_cqe_res_format[0x2]; 3730 u8 st[0x4]; 3731 u8 reserved_at_18[0x8]; 3732 3733 u8 reserved_at_20[0x20]; 3734 3735 u8 reserved_at_40[0x14]; 3736 u8 page_offset[0x6]; 3737 u8 reserved_at_5a[0x6]; 3738 3739 u8 reserved_at_60[0x3]; 3740 u8 log_cq_size[0x5]; 3741 u8 uar_page[0x18]; 3742 3743 u8 reserved_at_80[0x4]; 3744 u8 cq_period[0xc]; 3745 u8 cq_max_count[0x10]; 3746 3747 u8 reserved_at_a0[0x18]; 3748 u8 c_eqn[0x8]; 3749 3750 u8 reserved_at_c0[0x3]; 3751 u8 log_page_size[0x5]; 3752 u8 reserved_at_c8[0x18]; 3753 3754 u8 reserved_at_e0[0x20]; 3755 3756 u8 reserved_at_100[0x8]; 3757 u8 last_notified_index[0x18]; 3758 3759 u8 reserved_at_120[0x8]; 3760 u8 last_solicit_index[0x18]; 3761 3762 u8 reserved_at_140[0x8]; 3763 u8 consumer_counter[0x18]; 3764 3765 u8 reserved_at_160[0x8]; 3766 u8 producer_counter[0x18]; 3767 3768 u8 reserved_at_180[0x40]; 3769 3770 u8 dbr_addr[0x40]; 3771 }; 3772 3773 union mlx5_ifc_cong_control_roce_ecn_auto_bits { 3774 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp; 3775 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp; 3776 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np; 3777 u8 reserved_at_0[0x800]; 3778 }; 3779 3780 struct mlx5_ifc_query_adapter_param_block_bits { 3781 u8 reserved_at_0[0xc0]; 3782 3783 u8 reserved_at_c0[0x8]; 3784 u8 ieee_vendor_id[0x18]; 3785 3786 u8 reserved_at_e0[0x10]; 3787 u8 vsd_vendor_id[0x10]; 3788 3789 u8 vsd[208][0x8]; 3790 3791 u8 vsd_contd_psid[16][0x8]; 3792 }; 3793 3794 enum { 3795 MLX5_XRQC_STATE_GOOD = 0x0, 3796 MLX5_XRQC_STATE_ERROR = 0x1, 3797 }; 3798 3799 enum { 3800 MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0, 3801 MLX5_XRQC_TOPOLOGY_TAG_MATCHING = 0x1, 3802 }; 3803 3804 enum { 3805 MLX5_XRQC_OFFLOAD_RNDV = 0x1, 3806 }; 3807 3808 struct mlx5_ifc_tag_matching_topology_context_bits { 3809 u8 log_matching_list_sz[0x4]; 3810 u8 reserved_at_4[0xc]; 3811 u8 append_next_index[0x10]; 3812 3813 u8 sw_phase_cnt[0x10]; 3814 u8 hw_phase_cnt[0x10]; 3815 3816 u8 reserved_at_40[0x40]; 3817 }; 3818 3819 struct mlx5_ifc_xrqc_bits { 3820 u8 state[0x4]; 3821 u8 rlkey[0x1]; 3822 u8 reserved_at_5[0xf]; 3823 u8 topology[0x4]; 3824 u8 reserved_at_18[0x4]; 3825 u8 offload[0x4]; 3826 3827 u8 reserved_at_20[0x8]; 3828 u8 user_index[0x18]; 3829 3830 u8 reserved_at_40[0x8]; 3831 u8 cqn[0x18]; 3832 3833 u8 reserved_at_60[0xa0]; 3834 3835 struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context; 3836 3837 u8 reserved_at_180[0x280]; 3838 3839 struct mlx5_ifc_wq_bits wq; 3840 }; 3841 3842 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits { 3843 struct mlx5_ifc_modify_field_select_bits modify_field_select; 3844 struct mlx5_ifc_resize_field_select_bits resize_field_select; 3845 u8 reserved_at_0[0x20]; 3846 }; 3847 3848 union mlx5_ifc_field_select_802_1_r_roce_auto_bits { 3849 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp; 3850 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp; 3851 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np; 3852 u8 reserved_at_0[0x20]; 3853 }; 3854 3855 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits { 3856 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 3857 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 3858 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 3859 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 3860 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 3861 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 3862 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout; 3863 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout; 3864 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 3865 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 3866 struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs; 3867 u8 reserved_at_0[0x7c0]; 3868 }; 3869 3870 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits { 3871 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout; 3872 u8 reserved_at_0[0x7c0]; 3873 }; 3874 3875 union mlx5_ifc_event_auto_bits { 3876 struct mlx5_ifc_comp_event_bits comp_event; 3877 struct mlx5_ifc_dct_events_bits dct_events; 3878 struct mlx5_ifc_qp_events_bits qp_events; 3879 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event; 3880 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event; 3881 struct mlx5_ifc_cq_error_bits cq_error; 3882 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged; 3883 struct mlx5_ifc_port_state_change_event_bits port_state_change_event; 3884 struct mlx5_ifc_gpio_event_bits gpio_event; 3885 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event; 3886 struct mlx5_ifc_stall_vl_event_bits stall_vl_event; 3887 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event; 3888 u8 reserved_at_0[0xe0]; 3889 }; 3890 3891 struct mlx5_ifc_health_buffer_bits { 3892 u8 reserved_at_0[0x100]; 3893 3894 u8 assert_existptr[0x20]; 3895 3896 u8 assert_callra[0x20]; 3897 3898 u8 reserved_at_140[0x40]; 3899 3900 u8 fw_version[0x20]; 3901 3902 u8 hw_id[0x20]; 3903 3904 u8 reserved_at_1c0[0x20]; 3905 3906 u8 irisc_index[0x8]; 3907 u8 synd[0x8]; 3908 u8 ext_synd[0x10]; 3909 }; 3910 3911 struct mlx5_ifc_register_loopback_control_bits { 3912 u8 no_lb[0x1]; 3913 u8 reserved_at_1[0x7]; 3914 u8 port[0x8]; 3915 u8 reserved_at_10[0x10]; 3916 3917 u8 reserved_at_20[0x60]; 3918 }; 3919 3920 struct mlx5_ifc_vport_tc_element_bits { 3921 u8 traffic_class[0x4]; 3922 u8 reserved_at_4[0xc]; 3923 u8 vport_number[0x10]; 3924 }; 3925 3926 struct mlx5_ifc_vport_element_bits { 3927 u8 reserved_at_0[0x10]; 3928 u8 vport_number[0x10]; 3929 }; 3930 3931 enum { 3932 TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0, 3933 TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1, 3934 TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2, 3935 }; 3936 3937 struct mlx5_ifc_tsar_element_bits { 3938 u8 reserved_at_0[0x8]; 3939 u8 tsar_type[0x8]; 3940 u8 reserved_at_10[0x10]; 3941 }; 3942 3943 enum { 3944 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0, 3945 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1, 3946 }; 3947 3948 struct mlx5_ifc_teardown_hca_out_bits { 3949 u8 status[0x8]; 3950 u8 reserved_at_8[0x18]; 3951 3952 u8 syndrome[0x20]; 3953 3954 u8 reserved_at_40[0x3f]; 3955 3956 u8 state[0x1]; 3957 }; 3958 3959 enum { 3960 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0, 3961 MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE = 0x1, 3962 MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN = 0x2, 3963 }; 3964 3965 struct mlx5_ifc_teardown_hca_in_bits { 3966 u8 opcode[0x10]; 3967 u8 reserved_at_10[0x10]; 3968 3969 u8 reserved_at_20[0x10]; 3970 u8 op_mod[0x10]; 3971 3972 u8 reserved_at_40[0x10]; 3973 u8 profile[0x10]; 3974 3975 u8 reserved_at_60[0x20]; 3976 }; 3977 3978 struct mlx5_ifc_sqerr2rts_qp_out_bits { 3979 u8 status[0x8]; 3980 u8 reserved_at_8[0x18]; 3981 3982 u8 syndrome[0x20]; 3983 3984 u8 reserved_at_40[0x40]; 3985 }; 3986 3987 struct mlx5_ifc_sqerr2rts_qp_in_bits { 3988 u8 opcode[0x10]; 3989 u8 uid[0x10]; 3990 3991 u8 reserved_at_20[0x10]; 3992 u8 op_mod[0x10]; 3993 3994 u8 reserved_at_40[0x8]; 3995 u8 qpn[0x18]; 3996 3997 u8 reserved_at_60[0x20]; 3998 3999 u8 opt_param_mask[0x20]; 4000 4001 u8 reserved_at_a0[0x20]; 4002 4003 struct mlx5_ifc_qpc_bits qpc; 4004 4005 u8 reserved_at_800[0x80]; 4006 }; 4007 4008 struct mlx5_ifc_sqd2rts_qp_out_bits { 4009 u8 status[0x8]; 4010 u8 reserved_at_8[0x18]; 4011 4012 u8 syndrome[0x20]; 4013 4014 u8 reserved_at_40[0x40]; 4015 }; 4016 4017 struct mlx5_ifc_sqd2rts_qp_in_bits { 4018 u8 opcode[0x10]; 4019 u8 uid[0x10]; 4020 4021 u8 reserved_at_20[0x10]; 4022 u8 op_mod[0x10]; 4023 4024 u8 reserved_at_40[0x8]; 4025 u8 qpn[0x18]; 4026 4027 u8 reserved_at_60[0x20]; 4028 4029 u8 opt_param_mask[0x20]; 4030 4031 u8 reserved_at_a0[0x20]; 4032 4033 struct mlx5_ifc_qpc_bits qpc; 4034 4035 u8 reserved_at_800[0x80]; 4036 }; 4037 4038 struct mlx5_ifc_set_roce_address_out_bits { 4039 u8 status[0x8]; 4040 u8 reserved_at_8[0x18]; 4041 4042 u8 syndrome[0x20]; 4043 4044 u8 reserved_at_40[0x40]; 4045 }; 4046 4047 struct mlx5_ifc_set_roce_address_in_bits { 4048 u8 opcode[0x10]; 4049 u8 reserved_at_10[0x10]; 4050 4051 u8 reserved_at_20[0x10]; 4052 u8 op_mod[0x10]; 4053 4054 u8 roce_address_index[0x10]; 4055 u8 reserved_at_50[0xc]; 4056 u8 vhca_port_num[0x4]; 4057 4058 u8 reserved_at_60[0x20]; 4059 4060 struct mlx5_ifc_roce_addr_layout_bits roce_address; 4061 }; 4062 4063 struct mlx5_ifc_set_mad_demux_out_bits { 4064 u8 status[0x8]; 4065 u8 reserved_at_8[0x18]; 4066 4067 u8 syndrome[0x20]; 4068 4069 u8 reserved_at_40[0x40]; 4070 }; 4071 4072 enum { 4073 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0, 4074 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2, 4075 }; 4076 4077 struct mlx5_ifc_set_mad_demux_in_bits { 4078 u8 opcode[0x10]; 4079 u8 reserved_at_10[0x10]; 4080 4081 u8 reserved_at_20[0x10]; 4082 u8 op_mod[0x10]; 4083 4084 u8 reserved_at_40[0x20]; 4085 4086 u8 reserved_at_60[0x6]; 4087 u8 demux_mode[0x2]; 4088 u8 reserved_at_68[0x18]; 4089 }; 4090 4091 struct mlx5_ifc_set_l2_table_entry_out_bits { 4092 u8 status[0x8]; 4093 u8 reserved_at_8[0x18]; 4094 4095 u8 syndrome[0x20]; 4096 4097 u8 reserved_at_40[0x40]; 4098 }; 4099 4100 struct mlx5_ifc_set_l2_table_entry_in_bits { 4101 u8 opcode[0x10]; 4102 u8 reserved_at_10[0x10]; 4103 4104 u8 reserved_at_20[0x10]; 4105 u8 op_mod[0x10]; 4106 4107 u8 reserved_at_40[0x60]; 4108 4109 u8 reserved_at_a0[0x8]; 4110 u8 table_index[0x18]; 4111 4112 u8 reserved_at_c0[0x20]; 4113 4114 u8 reserved_at_e0[0x13]; 4115 u8 vlan_valid[0x1]; 4116 u8 vlan[0xc]; 4117 4118 struct mlx5_ifc_mac_address_layout_bits mac_address; 4119 4120 u8 reserved_at_140[0xc0]; 4121 }; 4122 4123 struct mlx5_ifc_set_issi_out_bits { 4124 u8 status[0x8]; 4125 u8 reserved_at_8[0x18]; 4126 4127 u8 syndrome[0x20]; 4128 4129 u8 reserved_at_40[0x40]; 4130 }; 4131 4132 struct mlx5_ifc_set_issi_in_bits { 4133 u8 opcode[0x10]; 4134 u8 reserved_at_10[0x10]; 4135 4136 u8 reserved_at_20[0x10]; 4137 u8 op_mod[0x10]; 4138 4139 u8 reserved_at_40[0x10]; 4140 u8 current_issi[0x10]; 4141 4142 u8 reserved_at_60[0x20]; 4143 }; 4144 4145 struct mlx5_ifc_set_hca_cap_out_bits { 4146 u8 status[0x8]; 4147 u8 reserved_at_8[0x18]; 4148 4149 u8 syndrome[0x20]; 4150 4151 u8 reserved_at_40[0x40]; 4152 }; 4153 4154 struct mlx5_ifc_set_hca_cap_in_bits { 4155 u8 opcode[0x10]; 4156 u8 reserved_at_10[0x10]; 4157 4158 u8 reserved_at_20[0x10]; 4159 u8 op_mod[0x10]; 4160 4161 u8 reserved_at_40[0x40]; 4162 4163 union mlx5_ifc_hca_cap_union_bits capability; 4164 }; 4165 4166 enum { 4167 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0, 4168 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1, 4169 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2, 4170 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3, 4171 MLX5_SET_FTE_MODIFY_ENABLE_MASK_IPSEC_OBJ_ID = 0x4 4172 }; 4173 4174 struct mlx5_ifc_set_fte_out_bits { 4175 u8 status[0x8]; 4176 u8 reserved_at_8[0x18]; 4177 4178 u8 syndrome[0x20]; 4179 4180 u8 reserved_at_40[0x40]; 4181 }; 4182 4183 struct mlx5_ifc_set_fte_in_bits { 4184 u8 opcode[0x10]; 4185 u8 reserved_at_10[0x10]; 4186 4187 u8 reserved_at_20[0x10]; 4188 u8 op_mod[0x10]; 4189 4190 u8 other_vport[0x1]; 4191 u8 reserved_at_41[0xf]; 4192 u8 vport_number[0x10]; 4193 4194 u8 reserved_at_60[0x20]; 4195 4196 u8 table_type[0x8]; 4197 u8 reserved_at_88[0x18]; 4198 4199 u8 reserved_at_a0[0x8]; 4200 u8 table_id[0x18]; 4201 4202 u8 ignore_flow_level[0x1]; 4203 u8 reserved_at_c1[0x17]; 4204 u8 modify_enable_mask[0x8]; 4205 4206 u8 reserved_at_e0[0x20]; 4207 4208 u8 flow_index[0x20]; 4209 4210 u8 reserved_at_120[0xe0]; 4211 4212 struct mlx5_ifc_flow_context_bits flow_context; 4213 }; 4214 4215 struct mlx5_ifc_rts2rts_qp_out_bits { 4216 u8 status[0x8]; 4217 u8 reserved_at_8[0x18]; 4218 4219 u8 syndrome[0x20]; 4220 4221 u8 reserved_at_40[0x40]; 4222 }; 4223 4224 struct mlx5_ifc_rts2rts_qp_in_bits { 4225 u8 opcode[0x10]; 4226 u8 uid[0x10]; 4227 4228 u8 reserved_at_20[0x10]; 4229 u8 op_mod[0x10]; 4230 4231 u8 reserved_at_40[0x8]; 4232 u8 qpn[0x18]; 4233 4234 u8 reserved_at_60[0x20]; 4235 4236 u8 opt_param_mask[0x20]; 4237 4238 u8 reserved_at_a0[0x20]; 4239 4240 struct mlx5_ifc_qpc_bits qpc; 4241 4242 u8 reserved_at_800[0x80]; 4243 }; 4244 4245 struct mlx5_ifc_rtr2rts_qp_out_bits { 4246 u8 status[0x8]; 4247 u8 reserved_at_8[0x18]; 4248 4249 u8 syndrome[0x20]; 4250 4251 u8 reserved_at_40[0x40]; 4252 }; 4253 4254 struct mlx5_ifc_rtr2rts_qp_in_bits { 4255 u8 opcode[0x10]; 4256 u8 uid[0x10]; 4257 4258 u8 reserved_at_20[0x10]; 4259 u8 op_mod[0x10]; 4260 4261 u8 reserved_at_40[0x8]; 4262 u8 qpn[0x18]; 4263 4264 u8 reserved_at_60[0x20]; 4265 4266 u8 opt_param_mask[0x20]; 4267 4268 u8 reserved_at_a0[0x20]; 4269 4270 struct mlx5_ifc_qpc_bits qpc; 4271 4272 u8 reserved_at_800[0x80]; 4273 }; 4274 4275 struct mlx5_ifc_rst2init_qp_out_bits { 4276 u8 status[0x8]; 4277 u8 reserved_at_8[0x18]; 4278 4279 u8 syndrome[0x20]; 4280 4281 u8 reserved_at_40[0x40]; 4282 }; 4283 4284 struct mlx5_ifc_rst2init_qp_in_bits { 4285 u8 opcode[0x10]; 4286 u8 uid[0x10]; 4287 4288 u8 reserved_at_20[0x10]; 4289 u8 op_mod[0x10]; 4290 4291 u8 reserved_at_40[0x8]; 4292 u8 qpn[0x18]; 4293 4294 u8 reserved_at_60[0x20]; 4295 4296 u8 opt_param_mask[0x20]; 4297 4298 u8 reserved_at_a0[0x20]; 4299 4300 struct mlx5_ifc_qpc_bits qpc; 4301 4302 u8 reserved_at_800[0x80]; 4303 }; 4304 4305 struct mlx5_ifc_query_xrq_out_bits { 4306 u8 status[0x8]; 4307 u8 reserved_at_8[0x18]; 4308 4309 u8 syndrome[0x20]; 4310 4311 u8 reserved_at_40[0x40]; 4312 4313 struct mlx5_ifc_xrqc_bits xrq_context; 4314 }; 4315 4316 struct mlx5_ifc_query_xrq_in_bits { 4317 u8 opcode[0x10]; 4318 u8 reserved_at_10[0x10]; 4319 4320 u8 reserved_at_20[0x10]; 4321 u8 op_mod[0x10]; 4322 4323 u8 reserved_at_40[0x8]; 4324 u8 xrqn[0x18]; 4325 4326 u8 reserved_at_60[0x20]; 4327 }; 4328 4329 struct mlx5_ifc_query_xrc_srq_out_bits { 4330 u8 status[0x8]; 4331 u8 reserved_at_8[0x18]; 4332 4333 u8 syndrome[0x20]; 4334 4335 u8 reserved_at_40[0x40]; 4336 4337 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 4338 4339 u8 reserved_at_280[0x600]; 4340 4341 u8 pas[0][0x40]; 4342 }; 4343 4344 struct mlx5_ifc_query_xrc_srq_in_bits { 4345 u8 opcode[0x10]; 4346 u8 reserved_at_10[0x10]; 4347 4348 u8 reserved_at_20[0x10]; 4349 u8 op_mod[0x10]; 4350 4351 u8 reserved_at_40[0x8]; 4352 u8 xrc_srqn[0x18]; 4353 4354 u8 reserved_at_60[0x20]; 4355 }; 4356 4357 enum { 4358 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0, 4359 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1, 4360 }; 4361 4362 struct mlx5_ifc_query_vport_state_out_bits { 4363 u8 status[0x8]; 4364 u8 reserved_at_8[0x18]; 4365 4366 u8 syndrome[0x20]; 4367 4368 u8 reserved_at_40[0x20]; 4369 4370 u8 reserved_at_60[0x18]; 4371 u8 admin_state[0x4]; 4372 u8 state[0x4]; 4373 }; 4374 4375 enum { 4376 MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT = 0x0, 4377 MLX5_VPORT_STATE_OP_MOD_ESW_VPORT = 0x1, 4378 }; 4379 4380 struct mlx5_ifc_arm_monitor_counter_in_bits { 4381 u8 opcode[0x10]; 4382 u8 uid[0x10]; 4383 4384 u8 reserved_at_20[0x10]; 4385 u8 op_mod[0x10]; 4386 4387 u8 reserved_at_40[0x20]; 4388 4389 u8 reserved_at_60[0x20]; 4390 }; 4391 4392 struct mlx5_ifc_arm_monitor_counter_out_bits { 4393 u8 status[0x8]; 4394 u8 reserved_at_8[0x18]; 4395 4396 u8 syndrome[0x20]; 4397 4398 u8 reserved_at_40[0x40]; 4399 }; 4400 4401 enum { 4402 MLX5_QUERY_MONITOR_CNT_TYPE_PPCNT = 0x0, 4403 MLX5_QUERY_MONITOR_CNT_TYPE_Q_COUNTER = 0x1, 4404 }; 4405 4406 enum mlx5_monitor_counter_ppcnt { 4407 MLX5_QUERY_MONITOR_PPCNT_IN_RANGE_LENGTH_ERRORS = 0x0, 4408 MLX5_QUERY_MONITOR_PPCNT_OUT_OF_RANGE_LENGTH_FIELD = 0x1, 4409 MLX5_QUERY_MONITOR_PPCNT_FRAME_TOO_LONG_ERRORS = 0x2, 4410 MLX5_QUERY_MONITOR_PPCNT_FRAME_CHECK_SEQUENCE_ERRORS = 0x3, 4411 MLX5_QUERY_MONITOR_PPCNT_ALIGNMENT_ERRORS = 0x4, 4412 MLX5_QUERY_MONITOR_PPCNT_IF_OUT_DISCARDS = 0x5, 4413 }; 4414 4415 enum { 4416 MLX5_QUERY_MONITOR_Q_COUNTER_RX_OUT_OF_BUFFER = 0x4, 4417 }; 4418 4419 struct mlx5_ifc_monitor_counter_output_bits { 4420 u8 reserved_at_0[0x4]; 4421 u8 type[0x4]; 4422 u8 reserved_at_8[0x8]; 4423 u8 counter[0x10]; 4424 4425 u8 counter_group_id[0x20]; 4426 }; 4427 4428 #define MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 (6) 4429 #define MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1 (1) 4430 #define MLX5_CMD_SET_MONITOR_NUM_COUNTER (MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 +\ 4431 MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1) 4432 4433 struct mlx5_ifc_set_monitor_counter_in_bits { 4434 u8 opcode[0x10]; 4435 u8 uid[0x10]; 4436 4437 u8 reserved_at_20[0x10]; 4438 u8 op_mod[0x10]; 4439 4440 u8 reserved_at_40[0x10]; 4441 u8 num_of_counters[0x10]; 4442 4443 u8 reserved_at_60[0x20]; 4444 4445 struct mlx5_ifc_monitor_counter_output_bits monitor_counter[MLX5_CMD_SET_MONITOR_NUM_COUNTER]; 4446 }; 4447 4448 struct mlx5_ifc_set_monitor_counter_out_bits { 4449 u8 status[0x8]; 4450 u8 reserved_at_8[0x18]; 4451 4452 u8 syndrome[0x20]; 4453 4454 u8 reserved_at_40[0x40]; 4455 }; 4456 4457 struct mlx5_ifc_query_vport_state_in_bits { 4458 u8 opcode[0x10]; 4459 u8 reserved_at_10[0x10]; 4460 4461 u8 reserved_at_20[0x10]; 4462 u8 op_mod[0x10]; 4463 4464 u8 other_vport[0x1]; 4465 u8 reserved_at_41[0xf]; 4466 u8 vport_number[0x10]; 4467 4468 u8 reserved_at_60[0x20]; 4469 }; 4470 4471 struct mlx5_ifc_query_vnic_env_out_bits { 4472 u8 status[0x8]; 4473 u8 reserved_at_8[0x18]; 4474 4475 u8 syndrome[0x20]; 4476 4477 u8 reserved_at_40[0x40]; 4478 4479 struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env; 4480 }; 4481 4482 enum { 4483 MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS = 0x0, 4484 }; 4485 4486 struct mlx5_ifc_query_vnic_env_in_bits { 4487 u8 opcode[0x10]; 4488 u8 reserved_at_10[0x10]; 4489 4490 u8 reserved_at_20[0x10]; 4491 u8 op_mod[0x10]; 4492 4493 u8 other_vport[0x1]; 4494 u8 reserved_at_41[0xf]; 4495 u8 vport_number[0x10]; 4496 4497 u8 reserved_at_60[0x20]; 4498 }; 4499 4500 struct mlx5_ifc_query_vport_counter_out_bits { 4501 u8 status[0x8]; 4502 u8 reserved_at_8[0x18]; 4503 4504 u8 syndrome[0x20]; 4505 4506 u8 reserved_at_40[0x40]; 4507 4508 struct mlx5_ifc_traffic_counter_bits received_errors; 4509 4510 struct mlx5_ifc_traffic_counter_bits transmit_errors; 4511 4512 struct mlx5_ifc_traffic_counter_bits received_ib_unicast; 4513 4514 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast; 4515 4516 struct mlx5_ifc_traffic_counter_bits received_ib_multicast; 4517 4518 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast; 4519 4520 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast; 4521 4522 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast; 4523 4524 struct mlx5_ifc_traffic_counter_bits received_eth_unicast; 4525 4526 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast; 4527 4528 struct mlx5_ifc_traffic_counter_bits received_eth_multicast; 4529 4530 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast; 4531 4532 u8 reserved_at_680[0xa00]; 4533 }; 4534 4535 enum { 4536 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0, 4537 }; 4538 4539 struct mlx5_ifc_query_vport_counter_in_bits { 4540 u8 opcode[0x10]; 4541 u8 reserved_at_10[0x10]; 4542 4543 u8 reserved_at_20[0x10]; 4544 u8 op_mod[0x10]; 4545 4546 u8 other_vport[0x1]; 4547 u8 reserved_at_41[0xb]; 4548 u8 port_num[0x4]; 4549 u8 vport_number[0x10]; 4550 4551 u8 reserved_at_60[0x60]; 4552 4553 u8 clear[0x1]; 4554 u8 reserved_at_c1[0x1f]; 4555 4556 u8 reserved_at_e0[0x20]; 4557 }; 4558 4559 struct mlx5_ifc_query_tis_out_bits { 4560 u8 status[0x8]; 4561 u8 reserved_at_8[0x18]; 4562 4563 u8 syndrome[0x20]; 4564 4565 u8 reserved_at_40[0x40]; 4566 4567 struct mlx5_ifc_tisc_bits tis_context; 4568 }; 4569 4570 struct mlx5_ifc_query_tis_in_bits { 4571 u8 opcode[0x10]; 4572 u8 reserved_at_10[0x10]; 4573 4574 u8 reserved_at_20[0x10]; 4575 u8 op_mod[0x10]; 4576 4577 u8 reserved_at_40[0x8]; 4578 u8 tisn[0x18]; 4579 4580 u8 reserved_at_60[0x20]; 4581 }; 4582 4583 struct mlx5_ifc_query_tir_out_bits { 4584 u8 status[0x8]; 4585 u8 reserved_at_8[0x18]; 4586 4587 u8 syndrome[0x20]; 4588 4589 u8 reserved_at_40[0xc0]; 4590 4591 struct mlx5_ifc_tirc_bits tir_context; 4592 }; 4593 4594 struct mlx5_ifc_query_tir_in_bits { 4595 u8 opcode[0x10]; 4596 u8 reserved_at_10[0x10]; 4597 4598 u8 reserved_at_20[0x10]; 4599 u8 op_mod[0x10]; 4600 4601 u8 reserved_at_40[0x8]; 4602 u8 tirn[0x18]; 4603 4604 u8 reserved_at_60[0x20]; 4605 }; 4606 4607 struct mlx5_ifc_query_srq_out_bits { 4608 u8 status[0x8]; 4609 u8 reserved_at_8[0x18]; 4610 4611 u8 syndrome[0x20]; 4612 4613 u8 reserved_at_40[0x40]; 4614 4615 struct mlx5_ifc_srqc_bits srq_context_entry; 4616 4617 u8 reserved_at_280[0x600]; 4618 4619 u8 pas[0][0x40]; 4620 }; 4621 4622 struct mlx5_ifc_query_srq_in_bits { 4623 u8 opcode[0x10]; 4624 u8 reserved_at_10[0x10]; 4625 4626 u8 reserved_at_20[0x10]; 4627 u8 op_mod[0x10]; 4628 4629 u8 reserved_at_40[0x8]; 4630 u8 srqn[0x18]; 4631 4632 u8 reserved_at_60[0x20]; 4633 }; 4634 4635 struct mlx5_ifc_query_sq_out_bits { 4636 u8 status[0x8]; 4637 u8 reserved_at_8[0x18]; 4638 4639 u8 syndrome[0x20]; 4640 4641 u8 reserved_at_40[0xc0]; 4642 4643 struct mlx5_ifc_sqc_bits sq_context; 4644 }; 4645 4646 struct mlx5_ifc_query_sq_in_bits { 4647 u8 opcode[0x10]; 4648 u8 reserved_at_10[0x10]; 4649 4650 u8 reserved_at_20[0x10]; 4651 u8 op_mod[0x10]; 4652 4653 u8 reserved_at_40[0x8]; 4654 u8 sqn[0x18]; 4655 4656 u8 reserved_at_60[0x20]; 4657 }; 4658 4659 struct mlx5_ifc_query_special_contexts_out_bits { 4660 u8 status[0x8]; 4661 u8 reserved_at_8[0x18]; 4662 4663 u8 syndrome[0x20]; 4664 4665 u8 dump_fill_mkey[0x20]; 4666 4667 u8 resd_lkey[0x20]; 4668 4669 u8 null_mkey[0x20]; 4670 4671 u8 reserved_at_a0[0x60]; 4672 }; 4673 4674 struct mlx5_ifc_query_special_contexts_in_bits { 4675 u8 opcode[0x10]; 4676 u8 reserved_at_10[0x10]; 4677 4678 u8 reserved_at_20[0x10]; 4679 u8 op_mod[0x10]; 4680 4681 u8 reserved_at_40[0x40]; 4682 }; 4683 4684 struct mlx5_ifc_query_scheduling_element_out_bits { 4685 u8 opcode[0x10]; 4686 u8 reserved_at_10[0x10]; 4687 4688 u8 reserved_at_20[0x10]; 4689 u8 op_mod[0x10]; 4690 4691 u8 reserved_at_40[0xc0]; 4692 4693 struct mlx5_ifc_scheduling_context_bits scheduling_context; 4694 4695 u8 reserved_at_300[0x100]; 4696 }; 4697 4698 enum { 4699 SCHEDULING_HIERARCHY_E_SWITCH = 0x2, 4700 }; 4701 4702 struct mlx5_ifc_query_scheduling_element_in_bits { 4703 u8 opcode[0x10]; 4704 u8 reserved_at_10[0x10]; 4705 4706 u8 reserved_at_20[0x10]; 4707 u8 op_mod[0x10]; 4708 4709 u8 scheduling_hierarchy[0x8]; 4710 u8 reserved_at_48[0x18]; 4711 4712 u8 scheduling_element_id[0x20]; 4713 4714 u8 reserved_at_80[0x180]; 4715 }; 4716 4717 struct mlx5_ifc_query_rqt_out_bits { 4718 u8 status[0x8]; 4719 u8 reserved_at_8[0x18]; 4720 4721 u8 syndrome[0x20]; 4722 4723 u8 reserved_at_40[0xc0]; 4724 4725 struct mlx5_ifc_rqtc_bits rqt_context; 4726 }; 4727 4728 struct mlx5_ifc_query_rqt_in_bits { 4729 u8 opcode[0x10]; 4730 u8 reserved_at_10[0x10]; 4731 4732 u8 reserved_at_20[0x10]; 4733 u8 op_mod[0x10]; 4734 4735 u8 reserved_at_40[0x8]; 4736 u8 rqtn[0x18]; 4737 4738 u8 reserved_at_60[0x20]; 4739 }; 4740 4741 struct mlx5_ifc_query_rq_out_bits { 4742 u8 status[0x8]; 4743 u8 reserved_at_8[0x18]; 4744 4745 u8 syndrome[0x20]; 4746 4747 u8 reserved_at_40[0xc0]; 4748 4749 struct mlx5_ifc_rqc_bits rq_context; 4750 }; 4751 4752 struct mlx5_ifc_query_rq_in_bits { 4753 u8 opcode[0x10]; 4754 u8 reserved_at_10[0x10]; 4755 4756 u8 reserved_at_20[0x10]; 4757 u8 op_mod[0x10]; 4758 4759 u8 reserved_at_40[0x8]; 4760 u8 rqn[0x18]; 4761 4762 u8 reserved_at_60[0x20]; 4763 }; 4764 4765 struct mlx5_ifc_query_roce_address_out_bits { 4766 u8 status[0x8]; 4767 u8 reserved_at_8[0x18]; 4768 4769 u8 syndrome[0x20]; 4770 4771 u8 reserved_at_40[0x40]; 4772 4773 struct mlx5_ifc_roce_addr_layout_bits roce_address; 4774 }; 4775 4776 struct mlx5_ifc_query_roce_address_in_bits { 4777 u8 opcode[0x10]; 4778 u8 reserved_at_10[0x10]; 4779 4780 u8 reserved_at_20[0x10]; 4781 u8 op_mod[0x10]; 4782 4783 u8 roce_address_index[0x10]; 4784 u8 reserved_at_50[0xc]; 4785 u8 vhca_port_num[0x4]; 4786 4787 u8 reserved_at_60[0x20]; 4788 }; 4789 4790 struct mlx5_ifc_query_rmp_out_bits { 4791 u8 status[0x8]; 4792 u8 reserved_at_8[0x18]; 4793 4794 u8 syndrome[0x20]; 4795 4796 u8 reserved_at_40[0xc0]; 4797 4798 struct mlx5_ifc_rmpc_bits rmp_context; 4799 }; 4800 4801 struct mlx5_ifc_query_rmp_in_bits { 4802 u8 opcode[0x10]; 4803 u8 reserved_at_10[0x10]; 4804 4805 u8 reserved_at_20[0x10]; 4806 u8 op_mod[0x10]; 4807 4808 u8 reserved_at_40[0x8]; 4809 u8 rmpn[0x18]; 4810 4811 u8 reserved_at_60[0x20]; 4812 }; 4813 4814 struct mlx5_ifc_query_qp_out_bits { 4815 u8 status[0x8]; 4816 u8 reserved_at_8[0x18]; 4817 4818 u8 syndrome[0x20]; 4819 4820 u8 reserved_at_40[0x40]; 4821 4822 u8 opt_param_mask[0x20]; 4823 4824 u8 reserved_at_a0[0x20]; 4825 4826 struct mlx5_ifc_qpc_bits qpc; 4827 4828 u8 reserved_at_800[0x80]; 4829 4830 u8 pas[0][0x40]; 4831 }; 4832 4833 struct mlx5_ifc_query_qp_in_bits { 4834 u8 opcode[0x10]; 4835 u8 reserved_at_10[0x10]; 4836 4837 u8 reserved_at_20[0x10]; 4838 u8 op_mod[0x10]; 4839 4840 u8 reserved_at_40[0x8]; 4841 u8 qpn[0x18]; 4842 4843 u8 reserved_at_60[0x20]; 4844 }; 4845 4846 struct mlx5_ifc_query_q_counter_out_bits { 4847 u8 status[0x8]; 4848 u8 reserved_at_8[0x18]; 4849 4850 u8 syndrome[0x20]; 4851 4852 u8 reserved_at_40[0x40]; 4853 4854 u8 rx_write_requests[0x20]; 4855 4856 u8 reserved_at_a0[0x20]; 4857 4858 u8 rx_read_requests[0x20]; 4859 4860 u8 reserved_at_e0[0x20]; 4861 4862 u8 rx_atomic_requests[0x20]; 4863 4864 u8 reserved_at_120[0x20]; 4865 4866 u8 rx_dct_connect[0x20]; 4867 4868 u8 reserved_at_160[0x20]; 4869 4870 u8 out_of_buffer[0x20]; 4871 4872 u8 reserved_at_1a0[0x20]; 4873 4874 u8 out_of_sequence[0x20]; 4875 4876 u8 reserved_at_1e0[0x20]; 4877 4878 u8 duplicate_request[0x20]; 4879 4880 u8 reserved_at_220[0x20]; 4881 4882 u8 rnr_nak_retry_err[0x20]; 4883 4884 u8 reserved_at_260[0x20]; 4885 4886 u8 packet_seq_err[0x20]; 4887 4888 u8 reserved_at_2a0[0x20]; 4889 4890 u8 implied_nak_seq_err[0x20]; 4891 4892 u8 reserved_at_2e0[0x20]; 4893 4894 u8 local_ack_timeout_err[0x20]; 4895 4896 u8 reserved_at_320[0xa0]; 4897 4898 u8 resp_local_length_error[0x20]; 4899 4900 u8 req_local_length_error[0x20]; 4901 4902 u8 resp_local_qp_error[0x20]; 4903 4904 u8 local_operation_error[0x20]; 4905 4906 u8 resp_local_protection[0x20]; 4907 4908 u8 req_local_protection[0x20]; 4909 4910 u8 resp_cqe_error[0x20]; 4911 4912 u8 req_cqe_error[0x20]; 4913 4914 u8 req_mw_binding[0x20]; 4915 4916 u8 req_bad_response[0x20]; 4917 4918 u8 req_remote_invalid_request[0x20]; 4919 4920 u8 resp_remote_invalid_request[0x20]; 4921 4922 u8 req_remote_access_errors[0x20]; 4923 4924 u8 resp_remote_access_errors[0x20]; 4925 4926 u8 req_remote_operation_errors[0x20]; 4927 4928 u8 req_transport_retries_exceeded[0x20]; 4929 4930 u8 cq_overflow[0x20]; 4931 4932 u8 resp_cqe_flush_error[0x20]; 4933 4934 u8 req_cqe_flush_error[0x20]; 4935 4936 u8 reserved_at_620[0x20]; 4937 4938 u8 roce_adp_retrans[0x20]; 4939 4940 u8 roce_adp_retrans_to[0x20]; 4941 4942 u8 roce_slow_restart[0x20]; 4943 4944 u8 roce_slow_restart_cnps[0x20]; 4945 4946 u8 roce_slow_restart_trans[0x20]; 4947 4948 u8 reserved_at_6e0[0x120]; 4949 }; 4950 4951 struct mlx5_ifc_query_q_counter_in_bits { 4952 u8 opcode[0x10]; 4953 u8 reserved_at_10[0x10]; 4954 4955 u8 reserved_at_20[0x10]; 4956 u8 op_mod[0x10]; 4957 4958 u8 reserved_at_40[0x80]; 4959 4960 u8 clear[0x1]; 4961 u8 reserved_at_c1[0x1f]; 4962 4963 u8 reserved_at_e0[0x18]; 4964 u8 counter_set_id[0x8]; 4965 }; 4966 4967 struct mlx5_ifc_query_pages_out_bits { 4968 u8 status[0x8]; 4969 u8 reserved_at_8[0x18]; 4970 4971 u8 syndrome[0x20]; 4972 4973 u8 embedded_cpu_function[0x1]; 4974 u8 reserved_at_41[0xf]; 4975 u8 function_id[0x10]; 4976 4977 u8 num_pages[0x20]; 4978 }; 4979 4980 enum { 4981 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1, 4982 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2, 4983 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3, 4984 }; 4985 4986 struct mlx5_ifc_query_pages_in_bits { 4987 u8 opcode[0x10]; 4988 u8 reserved_at_10[0x10]; 4989 4990 u8 reserved_at_20[0x10]; 4991 u8 op_mod[0x10]; 4992 4993 u8 embedded_cpu_function[0x1]; 4994 u8 reserved_at_41[0xf]; 4995 u8 function_id[0x10]; 4996 4997 u8 reserved_at_60[0x20]; 4998 }; 4999 5000 struct mlx5_ifc_query_nic_vport_context_out_bits { 5001 u8 status[0x8]; 5002 u8 reserved_at_8[0x18]; 5003 5004 u8 syndrome[0x20]; 5005 5006 u8 reserved_at_40[0x40]; 5007 5008 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 5009 }; 5010 5011 struct mlx5_ifc_query_nic_vport_context_in_bits { 5012 u8 opcode[0x10]; 5013 u8 reserved_at_10[0x10]; 5014 5015 u8 reserved_at_20[0x10]; 5016 u8 op_mod[0x10]; 5017 5018 u8 other_vport[0x1]; 5019 u8 reserved_at_41[0xf]; 5020 u8 vport_number[0x10]; 5021 5022 u8 reserved_at_60[0x5]; 5023 u8 allowed_list_type[0x3]; 5024 u8 reserved_at_68[0x18]; 5025 }; 5026 5027 struct mlx5_ifc_query_mkey_out_bits { 5028 u8 status[0x8]; 5029 u8 reserved_at_8[0x18]; 5030 5031 u8 syndrome[0x20]; 5032 5033 u8 reserved_at_40[0x40]; 5034 5035 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 5036 5037 u8 reserved_at_280[0x600]; 5038 5039 u8 bsf0_klm0_pas_mtt0_1[16][0x8]; 5040 5041 u8 bsf1_klm1_pas_mtt2_3[16][0x8]; 5042 }; 5043 5044 struct mlx5_ifc_query_mkey_in_bits { 5045 u8 opcode[0x10]; 5046 u8 reserved_at_10[0x10]; 5047 5048 u8 reserved_at_20[0x10]; 5049 u8 op_mod[0x10]; 5050 5051 u8 reserved_at_40[0x8]; 5052 u8 mkey_index[0x18]; 5053 5054 u8 pg_access[0x1]; 5055 u8 reserved_at_61[0x1f]; 5056 }; 5057 5058 struct mlx5_ifc_query_mad_demux_out_bits { 5059 u8 status[0x8]; 5060 u8 reserved_at_8[0x18]; 5061 5062 u8 syndrome[0x20]; 5063 5064 u8 reserved_at_40[0x40]; 5065 5066 u8 mad_dumux_parameters_block[0x20]; 5067 }; 5068 5069 struct mlx5_ifc_query_mad_demux_in_bits { 5070 u8 opcode[0x10]; 5071 u8 reserved_at_10[0x10]; 5072 5073 u8 reserved_at_20[0x10]; 5074 u8 op_mod[0x10]; 5075 5076 u8 reserved_at_40[0x40]; 5077 }; 5078 5079 struct mlx5_ifc_query_l2_table_entry_out_bits { 5080 u8 status[0x8]; 5081 u8 reserved_at_8[0x18]; 5082 5083 u8 syndrome[0x20]; 5084 5085 u8 reserved_at_40[0xa0]; 5086 5087 u8 reserved_at_e0[0x13]; 5088 u8 vlan_valid[0x1]; 5089 u8 vlan[0xc]; 5090 5091 struct mlx5_ifc_mac_address_layout_bits mac_address; 5092 5093 u8 reserved_at_140[0xc0]; 5094 }; 5095 5096 struct mlx5_ifc_query_l2_table_entry_in_bits { 5097 u8 opcode[0x10]; 5098 u8 reserved_at_10[0x10]; 5099 5100 u8 reserved_at_20[0x10]; 5101 u8 op_mod[0x10]; 5102 5103 u8 reserved_at_40[0x60]; 5104 5105 u8 reserved_at_a0[0x8]; 5106 u8 table_index[0x18]; 5107 5108 u8 reserved_at_c0[0x140]; 5109 }; 5110 5111 struct mlx5_ifc_query_issi_out_bits { 5112 u8 status[0x8]; 5113 u8 reserved_at_8[0x18]; 5114 5115 u8 syndrome[0x20]; 5116 5117 u8 reserved_at_40[0x10]; 5118 u8 current_issi[0x10]; 5119 5120 u8 reserved_at_60[0xa0]; 5121 5122 u8 reserved_at_100[76][0x8]; 5123 u8 supported_issi_dw0[0x20]; 5124 }; 5125 5126 struct mlx5_ifc_query_issi_in_bits { 5127 u8 opcode[0x10]; 5128 u8 reserved_at_10[0x10]; 5129 5130 u8 reserved_at_20[0x10]; 5131 u8 op_mod[0x10]; 5132 5133 u8 reserved_at_40[0x40]; 5134 }; 5135 5136 struct mlx5_ifc_set_driver_version_out_bits { 5137 u8 status[0x8]; 5138 u8 reserved_0[0x18]; 5139 5140 u8 syndrome[0x20]; 5141 u8 reserved_1[0x40]; 5142 }; 5143 5144 struct mlx5_ifc_set_driver_version_in_bits { 5145 u8 opcode[0x10]; 5146 u8 reserved_0[0x10]; 5147 5148 u8 reserved_1[0x10]; 5149 u8 op_mod[0x10]; 5150 5151 u8 reserved_2[0x40]; 5152 u8 driver_version[64][0x8]; 5153 }; 5154 5155 struct mlx5_ifc_query_hca_vport_pkey_out_bits { 5156 u8 status[0x8]; 5157 u8 reserved_at_8[0x18]; 5158 5159 u8 syndrome[0x20]; 5160 5161 u8 reserved_at_40[0x40]; 5162 5163 struct mlx5_ifc_pkey_bits pkey[0]; 5164 }; 5165 5166 struct mlx5_ifc_query_hca_vport_pkey_in_bits { 5167 u8 opcode[0x10]; 5168 u8 reserved_at_10[0x10]; 5169 5170 u8 reserved_at_20[0x10]; 5171 u8 op_mod[0x10]; 5172 5173 u8 other_vport[0x1]; 5174 u8 reserved_at_41[0xb]; 5175 u8 port_num[0x4]; 5176 u8 vport_number[0x10]; 5177 5178 u8 reserved_at_60[0x10]; 5179 u8 pkey_index[0x10]; 5180 }; 5181 5182 enum { 5183 MLX5_HCA_VPORT_SEL_PORT_GUID = 1 << 0, 5184 MLX5_HCA_VPORT_SEL_NODE_GUID = 1 << 1, 5185 MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2, 5186 }; 5187 5188 struct mlx5_ifc_query_hca_vport_gid_out_bits { 5189 u8 status[0x8]; 5190 u8 reserved_at_8[0x18]; 5191 5192 u8 syndrome[0x20]; 5193 5194 u8 reserved_at_40[0x20]; 5195 5196 u8 gids_num[0x10]; 5197 u8 reserved_at_70[0x10]; 5198 5199 struct mlx5_ifc_array128_auto_bits gid[0]; 5200 }; 5201 5202 struct mlx5_ifc_query_hca_vport_gid_in_bits { 5203 u8 opcode[0x10]; 5204 u8 reserved_at_10[0x10]; 5205 5206 u8 reserved_at_20[0x10]; 5207 u8 op_mod[0x10]; 5208 5209 u8 other_vport[0x1]; 5210 u8 reserved_at_41[0xb]; 5211 u8 port_num[0x4]; 5212 u8 vport_number[0x10]; 5213 5214 u8 reserved_at_60[0x10]; 5215 u8 gid_index[0x10]; 5216 }; 5217 5218 struct mlx5_ifc_query_hca_vport_context_out_bits { 5219 u8 status[0x8]; 5220 u8 reserved_at_8[0x18]; 5221 5222 u8 syndrome[0x20]; 5223 5224 u8 reserved_at_40[0x40]; 5225 5226 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 5227 }; 5228 5229 struct mlx5_ifc_query_hca_vport_context_in_bits { 5230 u8 opcode[0x10]; 5231 u8 reserved_at_10[0x10]; 5232 5233 u8 reserved_at_20[0x10]; 5234 u8 op_mod[0x10]; 5235 5236 u8 other_vport[0x1]; 5237 u8 reserved_at_41[0xb]; 5238 u8 port_num[0x4]; 5239 u8 vport_number[0x10]; 5240 5241 u8 reserved_at_60[0x20]; 5242 }; 5243 5244 struct mlx5_ifc_query_hca_cap_out_bits { 5245 u8 status[0x8]; 5246 u8 reserved_at_8[0x18]; 5247 5248 u8 syndrome[0x20]; 5249 5250 u8 reserved_at_40[0x40]; 5251 5252 union mlx5_ifc_hca_cap_union_bits capability; 5253 }; 5254 5255 struct mlx5_ifc_query_hca_cap_in_bits { 5256 u8 opcode[0x10]; 5257 u8 reserved_at_10[0x10]; 5258 5259 u8 reserved_at_20[0x10]; 5260 u8 op_mod[0x10]; 5261 5262 u8 other_function[0x1]; 5263 u8 reserved_at_41[0xf]; 5264 u8 function_id[0x10]; 5265 5266 u8 reserved_at_60[0x20]; 5267 }; 5268 5269 struct mlx5_ifc_other_hca_cap_bits { 5270 u8 roce[0x1]; 5271 u8 reserved_at_1[0x27f]; 5272 }; 5273 5274 struct mlx5_ifc_query_other_hca_cap_out_bits { 5275 u8 status[0x8]; 5276 u8 reserved_at_8[0x18]; 5277 5278 u8 syndrome[0x20]; 5279 5280 u8 reserved_at_40[0x40]; 5281 5282 struct mlx5_ifc_other_hca_cap_bits other_capability; 5283 }; 5284 5285 struct mlx5_ifc_query_other_hca_cap_in_bits { 5286 u8 opcode[0x10]; 5287 u8 reserved_at_10[0x10]; 5288 5289 u8 reserved_at_20[0x10]; 5290 u8 op_mod[0x10]; 5291 5292 u8 reserved_at_40[0x10]; 5293 u8 function_id[0x10]; 5294 5295 u8 reserved_at_60[0x20]; 5296 }; 5297 5298 struct mlx5_ifc_modify_other_hca_cap_out_bits { 5299 u8 status[0x8]; 5300 u8 reserved_at_8[0x18]; 5301 5302 u8 syndrome[0x20]; 5303 5304 u8 reserved_at_40[0x40]; 5305 }; 5306 5307 struct mlx5_ifc_modify_other_hca_cap_in_bits { 5308 u8 opcode[0x10]; 5309 u8 reserved_at_10[0x10]; 5310 5311 u8 reserved_at_20[0x10]; 5312 u8 op_mod[0x10]; 5313 5314 u8 reserved_at_40[0x10]; 5315 u8 function_id[0x10]; 5316 u8 field_select[0x20]; 5317 5318 struct mlx5_ifc_other_hca_cap_bits other_capability; 5319 }; 5320 5321 struct mlx5_ifc_flow_table_context_bits { 5322 u8 reformat_en[0x1]; 5323 u8 decap_en[0x1]; 5324 u8 sw_owner[0x1]; 5325 u8 termination_table[0x1]; 5326 u8 table_miss_action[0x4]; 5327 u8 level[0x8]; 5328 u8 reserved_at_10[0x8]; 5329 u8 log_size[0x8]; 5330 5331 u8 reserved_at_20[0x8]; 5332 u8 table_miss_id[0x18]; 5333 5334 u8 reserved_at_40[0x8]; 5335 u8 lag_master_next_table_id[0x18]; 5336 5337 u8 reserved_at_60[0x60]; 5338 5339 u8 sw_owner_icm_root_1[0x40]; 5340 5341 u8 sw_owner_icm_root_0[0x40]; 5342 5343 }; 5344 5345 struct mlx5_ifc_query_flow_table_out_bits { 5346 u8 status[0x8]; 5347 u8 reserved_at_8[0x18]; 5348 5349 u8 syndrome[0x20]; 5350 5351 u8 reserved_at_40[0x80]; 5352 5353 struct mlx5_ifc_flow_table_context_bits flow_table_context; 5354 }; 5355 5356 struct mlx5_ifc_query_flow_table_in_bits { 5357 u8 opcode[0x10]; 5358 u8 reserved_at_10[0x10]; 5359 5360 u8 reserved_at_20[0x10]; 5361 u8 op_mod[0x10]; 5362 5363 u8 reserved_at_40[0x40]; 5364 5365 u8 table_type[0x8]; 5366 u8 reserved_at_88[0x18]; 5367 5368 u8 reserved_at_a0[0x8]; 5369 u8 table_id[0x18]; 5370 5371 u8 reserved_at_c0[0x140]; 5372 }; 5373 5374 struct mlx5_ifc_query_fte_out_bits { 5375 u8 status[0x8]; 5376 u8 reserved_at_8[0x18]; 5377 5378 u8 syndrome[0x20]; 5379 5380 u8 reserved_at_40[0x1c0]; 5381 5382 struct mlx5_ifc_flow_context_bits flow_context; 5383 }; 5384 5385 struct mlx5_ifc_query_fte_in_bits { 5386 u8 opcode[0x10]; 5387 u8 reserved_at_10[0x10]; 5388 5389 u8 reserved_at_20[0x10]; 5390 u8 op_mod[0x10]; 5391 5392 u8 reserved_at_40[0x40]; 5393 5394 u8 table_type[0x8]; 5395 u8 reserved_at_88[0x18]; 5396 5397 u8 reserved_at_a0[0x8]; 5398 u8 table_id[0x18]; 5399 5400 u8 reserved_at_c0[0x40]; 5401 5402 u8 flow_index[0x20]; 5403 5404 u8 reserved_at_120[0xe0]; 5405 }; 5406 5407 enum { 5408 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 5409 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 5410 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 5411 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3, 5412 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_3 = 0x4, 5413 }; 5414 5415 struct mlx5_ifc_query_flow_group_out_bits { 5416 u8 status[0x8]; 5417 u8 reserved_at_8[0x18]; 5418 5419 u8 syndrome[0x20]; 5420 5421 u8 reserved_at_40[0xa0]; 5422 5423 u8 start_flow_index[0x20]; 5424 5425 u8 reserved_at_100[0x20]; 5426 5427 u8 end_flow_index[0x20]; 5428 5429 u8 reserved_at_140[0xa0]; 5430 5431 u8 reserved_at_1e0[0x18]; 5432 u8 match_criteria_enable[0x8]; 5433 5434 struct mlx5_ifc_fte_match_param_bits match_criteria; 5435 5436 u8 reserved_at_1200[0xe00]; 5437 }; 5438 5439 struct mlx5_ifc_query_flow_group_in_bits { 5440 u8 opcode[0x10]; 5441 u8 reserved_at_10[0x10]; 5442 5443 u8 reserved_at_20[0x10]; 5444 u8 op_mod[0x10]; 5445 5446 u8 reserved_at_40[0x40]; 5447 5448 u8 table_type[0x8]; 5449 u8 reserved_at_88[0x18]; 5450 5451 u8 reserved_at_a0[0x8]; 5452 u8 table_id[0x18]; 5453 5454 u8 group_id[0x20]; 5455 5456 u8 reserved_at_e0[0x120]; 5457 }; 5458 5459 struct mlx5_ifc_query_flow_counter_out_bits { 5460 u8 status[0x8]; 5461 u8 reserved_at_8[0x18]; 5462 5463 u8 syndrome[0x20]; 5464 5465 u8 reserved_at_40[0x40]; 5466 5467 struct mlx5_ifc_traffic_counter_bits flow_statistics[0]; 5468 }; 5469 5470 struct mlx5_ifc_query_flow_counter_in_bits { 5471 u8 opcode[0x10]; 5472 u8 reserved_at_10[0x10]; 5473 5474 u8 reserved_at_20[0x10]; 5475 u8 op_mod[0x10]; 5476 5477 u8 reserved_at_40[0x80]; 5478 5479 u8 clear[0x1]; 5480 u8 reserved_at_c1[0xf]; 5481 u8 num_of_counters[0x10]; 5482 5483 u8 flow_counter_id[0x20]; 5484 }; 5485 5486 struct mlx5_ifc_query_esw_vport_context_out_bits { 5487 u8 status[0x8]; 5488 u8 reserved_at_8[0x18]; 5489 5490 u8 syndrome[0x20]; 5491 5492 u8 reserved_at_40[0x40]; 5493 5494 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 5495 }; 5496 5497 struct mlx5_ifc_query_esw_vport_context_in_bits { 5498 u8 opcode[0x10]; 5499 u8 reserved_at_10[0x10]; 5500 5501 u8 reserved_at_20[0x10]; 5502 u8 op_mod[0x10]; 5503 5504 u8 other_vport[0x1]; 5505 u8 reserved_at_41[0xf]; 5506 u8 vport_number[0x10]; 5507 5508 u8 reserved_at_60[0x20]; 5509 }; 5510 5511 struct mlx5_ifc_modify_esw_vport_context_out_bits { 5512 u8 status[0x8]; 5513 u8 reserved_at_8[0x18]; 5514 5515 u8 syndrome[0x20]; 5516 5517 u8 reserved_at_40[0x40]; 5518 }; 5519 5520 struct mlx5_ifc_esw_vport_context_fields_select_bits { 5521 u8 reserved_at_0[0x1b]; 5522 u8 fdb_to_vport_reg_c_id[0x1]; 5523 u8 vport_cvlan_insert[0x1]; 5524 u8 vport_svlan_insert[0x1]; 5525 u8 vport_cvlan_strip[0x1]; 5526 u8 vport_svlan_strip[0x1]; 5527 }; 5528 5529 struct mlx5_ifc_modify_esw_vport_context_in_bits { 5530 u8 opcode[0x10]; 5531 u8 reserved_at_10[0x10]; 5532 5533 u8 reserved_at_20[0x10]; 5534 u8 op_mod[0x10]; 5535 5536 u8 other_vport[0x1]; 5537 u8 reserved_at_41[0xf]; 5538 u8 vport_number[0x10]; 5539 5540 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select; 5541 5542 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 5543 }; 5544 5545 struct mlx5_ifc_query_eq_out_bits { 5546 u8 status[0x8]; 5547 u8 reserved_at_8[0x18]; 5548 5549 u8 syndrome[0x20]; 5550 5551 u8 reserved_at_40[0x40]; 5552 5553 struct mlx5_ifc_eqc_bits eq_context_entry; 5554 5555 u8 reserved_at_280[0x40]; 5556 5557 u8 event_bitmask[0x40]; 5558 5559 u8 reserved_at_300[0x580]; 5560 5561 u8 pas[0][0x40]; 5562 }; 5563 5564 struct mlx5_ifc_query_eq_in_bits { 5565 u8 opcode[0x10]; 5566 u8 reserved_at_10[0x10]; 5567 5568 u8 reserved_at_20[0x10]; 5569 u8 op_mod[0x10]; 5570 5571 u8 reserved_at_40[0x18]; 5572 u8 eq_number[0x8]; 5573 5574 u8 reserved_at_60[0x20]; 5575 }; 5576 5577 struct mlx5_ifc_packet_reformat_context_in_bits { 5578 u8 reserved_at_0[0x5]; 5579 u8 reformat_type[0x3]; 5580 u8 reserved_at_8[0xe]; 5581 u8 reformat_data_size[0xa]; 5582 5583 u8 reserved_at_20[0x10]; 5584 u8 reformat_data[2][0x8]; 5585 5586 u8 more_reformat_data[0][0x8]; 5587 }; 5588 5589 struct mlx5_ifc_query_packet_reformat_context_out_bits { 5590 u8 status[0x8]; 5591 u8 reserved_at_8[0x18]; 5592 5593 u8 syndrome[0x20]; 5594 5595 u8 reserved_at_40[0xa0]; 5596 5597 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context[0]; 5598 }; 5599 5600 struct mlx5_ifc_query_packet_reformat_context_in_bits { 5601 u8 opcode[0x10]; 5602 u8 reserved_at_10[0x10]; 5603 5604 u8 reserved_at_20[0x10]; 5605 u8 op_mod[0x10]; 5606 5607 u8 packet_reformat_id[0x20]; 5608 5609 u8 reserved_at_60[0xa0]; 5610 }; 5611 5612 struct mlx5_ifc_alloc_packet_reformat_context_out_bits { 5613 u8 status[0x8]; 5614 u8 reserved_at_8[0x18]; 5615 5616 u8 syndrome[0x20]; 5617 5618 u8 packet_reformat_id[0x20]; 5619 5620 u8 reserved_at_60[0x20]; 5621 }; 5622 5623 enum mlx5_reformat_ctx_type { 5624 MLX5_REFORMAT_TYPE_L2_TO_VXLAN = 0x0, 5625 MLX5_REFORMAT_TYPE_L2_TO_NVGRE = 0x1, 5626 MLX5_REFORMAT_TYPE_L2_TO_L2_TUNNEL = 0x2, 5627 MLX5_REFORMAT_TYPE_L3_TUNNEL_TO_L2 = 0x3, 5628 MLX5_REFORMAT_TYPE_L2_TO_L3_TUNNEL = 0x4, 5629 }; 5630 5631 struct mlx5_ifc_alloc_packet_reformat_context_in_bits { 5632 u8 opcode[0x10]; 5633 u8 reserved_at_10[0x10]; 5634 5635 u8 reserved_at_20[0x10]; 5636 u8 op_mod[0x10]; 5637 5638 u8 reserved_at_40[0xa0]; 5639 5640 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context; 5641 }; 5642 5643 struct mlx5_ifc_dealloc_packet_reformat_context_out_bits { 5644 u8 status[0x8]; 5645 u8 reserved_at_8[0x18]; 5646 5647 u8 syndrome[0x20]; 5648 5649 u8 reserved_at_40[0x40]; 5650 }; 5651 5652 struct mlx5_ifc_dealloc_packet_reformat_context_in_bits { 5653 u8 opcode[0x10]; 5654 u8 reserved_at_10[0x10]; 5655 5656 u8 reserved_20[0x10]; 5657 u8 op_mod[0x10]; 5658 5659 u8 packet_reformat_id[0x20]; 5660 5661 u8 reserved_60[0x20]; 5662 }; 5663 5664 struct mlx5_ifc_set_action_in_bits { 5665 u8 action_type[0x4]; 5666 u8 field[0xc]; 5667 u8 reserved_at_10[0x3]; 5668 u8 offset[0x5]; 5669 u8 reserved_at_18[0x3]; 5670 u8 length[0x5]; 5671 5672 u8 data[0x20]; 5673 }; 5674 5675 struct mlx5_ifc_add_action_in_bits { 5676 u8 action_type[0x4]; 5677 u8 field[0xc]; 5678 u8 reserved_at_10[0x10]; 5679 5680 u8 data[0x20]; 5681 }; 5682 5683 struct mlx5_ifc_copy_action_in_bits { 5684 u8 action_type[0x4]; 5685 u8 src_field[0xc]; 5686 u8 reserved_at_10[0x3]; 5687 u8 src_offset[0x5]; 5688 u8 reserved_at_18[0x3]; 5689 u8 length[0x5]; 5690 5691 u8 reserved_at_20[0x4]; 5692 u8 dst_field[0xc]; 5693 u8 reserved_at_30[0x3]; 5694 u8 dst_offset[0x5]; 5695 u8 reserved_at_38[0x8]; 5696 }; 5697 5698 union mlx5_ifc_set_add_copy_action_in_auto_bits { 5699 struct mlx5_ifc_set_action_in_bits set_action_in; 5700 struct mlx5_ifc_add_action_in_bits add_action_in; 5701 struct mlx5_ifc_copy_action_in_bits copy_action_in; 5702 u8 reserved_at_0[0x40]; 5703 }; 5704 5705 enum { 5706 MLX5_ACTION_TYPE_SET = 0x1, 5707 MLX5_ACTION_TYPE_ADD = 0x2, 5708 MLX5_ACTION_TYPE_COPY = 0x3, 5709 }; 5710 5711 enum { 5712 MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16 = 0x1, 5713 MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0 = 0x2, 5714 MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE = 0x3, 5715 MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16 = 0x4, 5716 MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0 = 0x5, 5717 MLX5_ACTION_IN_FIELD_OUT_IP_DSCP = 0x6, 5718 MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS = 0x7, 5719 MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT = 0x8, 5720 MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT = 0x9, 5721 MLX5_ACTION_IN_FIELD_OUT_IP_TTL = 0xa, 5722 MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT = 0xb, 5723 MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT = 0xc, 5724 MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96 = 0xd, 5725 MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64 = 0xe, 5726 MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32 = 0xf, 5727 MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0 = 0x10, 5728 MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96 = 0x11, 5729 MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64 = 0x12, 5730 MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32 = 0x13, 5731 MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0 = 0x14, 5732 MLX5_ACTION_IN_FIELD_OUT_SIPV4 = 0x15, 5733 MLX5_ACTION_IN_FIELD_OUT_DIPV4 = 0x16, 5734 MLX5_ACTION_IN_FIELD_OUT_FIRST_VID = 0x17, 5735 MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47, 5736 MLX5_ACTION_IN_FIELD_METADATA_REG_A = 0x49, 5737 MLX5_ACTION_IN_FIELD_METADATA_REG_B = 0x50, 5738 MLX5_ACTION_IN_FIELD_METADATA_REG_C_0 = 0x51, 5739 MLX5_ACTION_IN_FIELD_METADATA_REG_C_1 = 0x52, 5740 MLX5_ACTION_IN_FIELD_METADATA_REG_C_2 = 0x53, 5741 MLX5_ACTION_IN_FIELD_METADATA_REG_C_3 = 0x54, 5742 MLX5_ACTION_IN_FIELD_METADATA_REG_C_4 = 0x55, 5743 MLX5_ACTION_IN_FIELD_METADATA_REG_C_5 = 0x56, 5744 MLX5_ACTION_IN_FIELD_METADATA_REG_C_6 = 0x57, 5745 MLX5_ACTION_IN_FIELD_METADATA_REG_C_7 = 0x58, 5746 MLX5_ACTION_IN_FIELD_OUT_TCP_SEQ_NUM = 0x59, 5747 MLX5_ACTION_IN_FIELD_OUT_TCP_ACK_NUM = 0x5B, 5748 }; 5749 5750 struct mlx5_ifc_alloc_modify_header_context_out_bits { 5751 u8 status[0x8]; 5752 u8 reserved_at_8[0x18]; 5753 5754 u8 syndrome[0x20]; 5755 5756 u8 modify_header_id[0x20]; 5757 5758 u8 reserved_at_60[0x20]; 5759 }; 5760 5761 struct mlx5_ifc_alloc_modify_header_context_in_bits { 5762 u8 opcode[0x10]; 5763 u8 reserved_at_10[0x10]; 5764 5765 u8 reserved_at_20[0x10]; 5766 u8 op_mod[0x10]; 5767 5768 u8 reserved_at_40[0x20]; 5769 5770 u8 table_type[0x8]; 5771 u8 reserved_at_68[0x10]; 5772 u8 num_of_actions[0x8]; 5773 5774 union mlx5_ifc_set_add_copy_action_in_auto_bits actions[0]; 5775 }; 5776 5777 struct mlx5_ifc_dealloc_modify_header_context_out_bits { 5778 u8 status[0x8]; 5779 u8 reserved_at_8[0x18]; 5780 5781 u8 syndrome[0x20]; 5782 5783 u8 reserved_at_40[0x40]; 5784 }; 5785 5786 struct mlx5_ifc_dealloc_modify_header_context_in_bits { 5787 u8 opcode[0x10]; 5788 u8 reserved_at_10[0x10]; 5789 5790 u8 reserved_at_20[0x10]; 5791 u8 op_mod[0x10]; 5792 5793 u8 modify_header_id[0x20]; 5794 5795 u8 reserved_at_60[0x20]; 5796 }; 5797 5798 struct mlx5_ifc_query_dct_out_bits { 5799 u8 status[0x8]; 5800 u8 reserved_at_8[0x18]; 5801 5802 u8 syndrome[0x20]; 5803 5804 u8 reserved_at_40[0x40]; 5805 5806 struct mlx5_ifc_dctc_bits dct_context_entry; 5807 5808 u8 reserved_at_280[0x180]; 5809 }; 5810 5811 struct mlx5_ifc_query_dct_in_bits { 5812 u8 opcode[0x10]; 5813 u8 reserved_at_10[0x10]; 5814 5815 u8 reserved_at_20[0x10]; 5816 u8 op_mod[0x10]; 5817 5818 u8 reserved_at_40[0x8]; 5819 u8 dctn[0x18]; 5820 5821 u8 reserved_at_60[0x20]; 5822 }; 5823 5824 struct mlx5_ifc_query_cq_out_bits { 5825 u8 status[0x8]; 5826 u8 reserved_at_8[0x18]; 5827 5828 u8 syndrome[0x20]; 5829 5830 u8 reserved_at_40[0x40]; 5831 5832 struct mlx5_ifc_cqc_bits cq_context; 5833 5834 u8 reserved_at_280[0x600]; 5835 5836 u8 pas[0][0x40]; 5837 }; 5838 5839 struct mlx5_ifc_query_cq_in_bits { 5840 u8 opcode[0x10]; 5841 u8 reserved_at_10[0x10]; 5842 5843 u8 reserved_at_20[0x10]; 5844 u8 op_mod[0x10]; 5845 5846 u8 reserved_at_40[0x8]; 5847 u8 cqn[0x18]; 5848 5849 u8 reserved_at_60[0x20]; 5850 }; 5851 5852 struct mlx5_ifc_query_cong_status_out_bits { 5853 u8 status[0x8]; 5854 u8 reserved_at_8[0x18]; 5855 5856 u8 syndrome[0x20]; 5857 5858 u8 reserved_at_40[0x20]; 5859 5860 u8 enable[0x1]; 5861 u8 tag_enable[0x1]; 5862 u8 reserved_at_62[0x1e]; 5863 }; 5864 5865 struct mlx5_ifc_query_cong_status_in_bits { 5866 u8 opcode[0x10]; 5867 u8 reserved_at_10[0x10]; 5868 5869 u8 reserved_at_20[0x10]; 5870 u8 op_mod[0x10]; 5871 5872 u8 reserved_at_40[0x18]; 5873 u8 priority[0x4]; 5874 u8 cong_protocol[0x4]; 5875 5876 u8 reserved_at_60[0x20]; 5877 }; 5878 5879 struct mlx5_ifc_query_cong_statistics_out_bits { 5880 u8 status[0x8]; 5881 u8 reserved_at_8[0x18]; 5882 5883 u8 syndrome[0x20]; 5884 5885 u8 reserved_at_40[0x40]; 5886 5887 u8 rp_cur_flows[0x20]; 5888 5889 u8 sum_flows[0x20]; 5890 5891 u8 rp_cnp_ignored_high[0x20]; 5892 5893 u8 rp_cnp_ignored_low[0x20]; 5894 5895 u8 rp_cnp_handled_high[0x20]; 5896 5897 u8 rp_cnp_handled_low[0x20]; 5898 5899 u8 reserved_at_140[0x100]; 5900 5901 u8 time_stamp_high[0x20]; 5902 5903 u8 time_stamp_low[0x20]; 5904 5905 u8 accumulators_period[0x20]; 5906 5907 u8 np_ecn_marked_roce_packets_high[0x20]; 5908 5909 u8 np_ecn_marked_roce_packets_low[0x20]; 5910 5911 u8 np_cnp_sent_high[0x20]; 5912 5913 u8 np_cnp_sent_low[0x20]; 5914 5915 u8 reserved_at_320[0x560]; 5916 }; 5917 5918 struct mlx5_ifc_query_cong_statistics_in_bits { 5919 u8 opcode[0x10]; 5920 u8 reserved_at_10[0x10]; 5921 5922 u8 reserved_at_20[0x10]; 5923 u8 op_mod[0x10]; 5924 5925 u8 clear[0x1]; 5926 u8 reserved_at_41[0x1f]; 5927 5928 u8 reserved_at_60[0x20]; 5929 }; 5930 5931 struct mlx5_ifc_query_cong_params_out_bits { 5932 u8 status[0x8]; 5933 u8 reserved_at_8[0x18]; 5934 5935 u8 syndrome[0x20]; 5936 5937 u8 reserved_at_40[0x40]; 5938 5939 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 5940 }; 5941 5942 struct mlx5_ifc_query_cong_params_in_bits { 5943 u8 opcode[0x10]; 5944 u8 reserved_at_10[0x10]; 5945 5946 u8 reserved_at_20[0x10]; 5947 u8 op_mod[0x10]; 5948 5949 u8 reserved_at_40[0x1c]; 5950 u8 cong_protocol[0x4]; 5951 5952 u8 reserved_at_60[0x20]; 5953 }; 5954 5955 struct mlx5_ifc_query_adapter_out_bits { 5956 u8 status[0x8]; 5957 u8 reserved_at_8[0x18]; 5958 5959 u8 syndrome[0x20]; 5960 5961 u8 reserved_at_40[0x40]; 5962 5963 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct; 5964 }; 5965 5966 struct mlx5_ifc_query_adapter_in_bits { 5967 u8 opcode[0x10]; 5968 u8 reserved_at_10[0x10]; 5969 5970 u8 reserved_at_20[0x10]; 5971 u8 op_mod[0x10]; 5972 5973 u8 reserved_at_40[0x40]; 5974 }; 5975 5976 struct mlx5_ifc_qp_2rst_out_bits { 5977 u8 status[0x8]; 5978 u8 reserved_at_8[0x18]; 5979 5980 u8 syndrome[0x20]; 5981 5982 u8 reserved_at_40[0x40]; 5983 }; 5984 5985 struct mlx5_ifc_qp_2rst_in_bits { 5986 u8 opcode[0x10]; 5987 u8 uid[0x10]; 5988 5989 u8 reserved_at_20[0x10]; 5990 u8 op_mod[0x10]; 5991 5992 u8 reserved_at_40[0x8]; 5993 u8 qpn[0x18]; 5994 5995 u8 reserved_at_60[0x20]; 5996 }; 5997 5998 struct mlx5_ifc_qp_2err_out_bits { 5999 u8 status[0x8]; 6000 u8 reserved_at_8[0x18]; 6001 6002 u8 syndrome[0x20]; 6003 6004 u8 reserved_at_40[0x40]; 6005 }; 6006 6007 struct mlx5_ifc_qp_2err_in_bits { 6008 u8 opcode[0x10]; 6009 u8 uid[0x10]; 6010 6011 u8 reserved_at_20[0x10]; 6012 u8 op_mod[0x10]; 6013 6014 u8 reserved_at_40[0x8]; 6015 u8 qpn[0x18]; 6016 6017 u8 reserved_at_60[0x20]; 6018 }; 6019 6020 struct mlx5_ifc_page_fault_resume_out_bits { 6021 u8 status[0x8]; 6022 u8 reserved_at_8[0x18]; 6023 6024 u8 syndrome[0x20]; 6025 6026 u8 reserved_at_40[0x40]; 6027 }; 6028 6029 struct mlx5_ifc_page_fault_resume_in_bits { 6030 u8 opcode[0x10]; 6031 u8 reserved_at_10[0x10]; 6032 6033 u8 reserved_at_20[0x10]; 6034 u8 op_mod[0x10]; 6035 6036 u8 error[0x1]; 6037 u8 reserved_at_41[0x4]; 6038 u8 page_fault_type[0x3]; 6039 u8 wq_number[0x18]; 6040 6041 u8 reserved_at_60[0x8]; 6042 u8 token[0x18]; 6043 }; 6044 6045 struct mlx5_ifc_nop_out_bits { 6046 u8 status[0x8]; 6047 u8 reserved_at_8[0x18]; 6048 6049 u8 syndrome[0x20]; 6050 6051 u8 reserved_at_40[0x40]; 6052 }; 6053 6054 struct mlx5_ifc_nop_in_bits { 6055 u8 opcode[0x10]; 6056 u8 reserved_at_10[0x10]; 6057 6058 u8 reserved_at_20[0x10]; 6059 u8 op_mod[0x10]; 6060 6061 u8 reserved_at_40[0x40]; 6062 }; 6063 6064 struct mlx5_ifc_modify_vport_state_out_bits { 6065 u8 status[0x8]; 6066 u8 reserved_at_8[0x18]; 6067 6068 u8 syndrome[0x20]; 6069 6070 u8 reserved_at_40[0x40]; 6071 }; 6072 6073 struct mlx5_ifc_modify_vport_state_in_bits { 6074 u8 opcode[0x10]; 6075 u8 reserved_at_10[0x10]; 6076 6077 u8 reserved_at_20[0x10]; 6078 u8 op_mod[0x10]; 6079 6080 u8 other_vport[0x1]; 6081 u8 reserved_at_41[0xf]; 6082 u8 vport_number[0x10]; 6083 6084 u8 reserved_at_60[0x18]; 6085 u8 admin_state[0x4]; 6086 u8 reserved_at_7c[0x4]; 6087 }; 6088 6089 struct mlx5_ifc_modify_tis_out_bits { 6090 u8 status[0x8]; 6091 u8 reserved_at_8[0x18]; 6092 6093 u8 syndrome[0x20]; 6094 6095 u8 reserved_at_40[0x40]; 6096 }; 6097 6098 struct mlx5_ifc_modify_tis_bitmask_bits { 6099 u8 reserved_at_0[0x20]; 6100 6101 u8 reserved_at_20[0x1d]; 6102 u8 lag_tx_port_affinity[0x1]; 6103 u8 strict_lag_tx_port_affinity[0x1]; 6104 u8 prio[0x1]; 6105 }; 6106 6107 struct mlx5_ifc_modify_tis_in_bits { 6108 u8 opcode[0x10]; 6109 u8 uid[0x10]; 6110 6111 u8 reserved_at_20[0x10]; 6112 u8 op_mod[0x10]; 6113 6114 u8 reserved_at_40[0x8]; 6115 u8 tisn[0x18]; 6116 6117 u8 reserved_at_60[0x20]; 6118 6119 struct mlx5_ifc_modify_tis_bitmask_bits bitmask; 6120 6121 u8 reserved_at_c0[0x40]; 6122 6123 struct mlx5_ifc_tisc_bits ctx; 6124 }; 6125 6126 struct mlx5_ifc_modify_tir_bitmask_bits { 6127 u8 reserved_at_0[0x20]; 6128 6129 u8 reserved_at_20[0x1b]; 6130 u8 self_lb_en[0x1]; 6131 u8 reserved_at_3c[0x1]; 6132 u8 hash[0x1]; 6133 u8 reserved_at_3e[0x1]; 6134 u8 lro[0x1]; 6135 }; 6136 6137 struct mlx5_ifc_modify_tir_out_bits { 6138 u8 status[0x8]; 6139 u8 reserved_at_8[0x18]; 6140 6141 u8 syndrome[0x20]; 6142 6143 u8 reserved_at_40[0x40]; 6144 }; 6145 6146 struct mlx5_ifc_modify_tir_in_bits { 6147 u8 opcode[0x10]; 6148 u8 uid[0x10]; 6149 6150 u8 reserved_at_20[0x10]; 6151 u8 op_mod[0x10]; 6152 6153 u8 reserved_at_40[0x8]; 6154 u8 tirn[0x18]; 6155 6156 u8 reserved_at_60[0x20]; 6157 6158 struct mlx5_ifc_modify_tir_bitmask_bits bitmask; 6159 6160 u8 reserved_at_c0[0x40]; 6161 6162 struct mlx5_ifc_tirc_bits ctx; 6163 }; 6164 6165 struct mlx5_ifc_modify_sq_out_bits { 6166 u8 status[0x8]; 6167 u8 reserved_at_8[0x18]; 6168 6169 u8 syndrome[0x20]; 6170 6171 u8 reserved_at_40[0x40]; 6172 }; 6173 6174 struct mlx5_ifc_modify_sq_in_bits { 6175 u8 opcode[0x10]; 6176 u8 uid[0x10]; 6177 6178 u8 reserved_at_20[0x10]; 6179 u8 op_mod[0x10]; 6180 6181 u8 sq_state[0x4]; 6182 u8 reserved_at_44[0x4]; 6183 u8 sqn[0x18]; 6184 6185 u8 reserved_at_60[0x20]; 6186 6187 u8 modify_bitmask[0x40]; 6188 6189 u8 reserved_at_c0[0x40]; 6190 6191 struct mlx5_ifc_sqc_bits ctx; 6192 }; 6193 6194 struct mlx5_ifc_modify_scheduling_element_out_bits { 6195 u8 status[0x8]; 6196 u8 reserved_at_8[0x18]; 6197 6198 u8 syndrome[0x20]; 6199 6200 u8 reserved_at_40[0x1c0]; 6201 }; 6202 6203 enum { 6204 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1, 6205 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2, 6206 }; 6207 6208 struct mlx5_ifc_modify_scheduling_element_in_bits { 6209 u8 opcode[0x10]; 6210 u8 reserved_at_10[0x10]; 6211 6212 u8 reserved_at_20[0x10]; 6213 u8 op_mod[0x10]; 6214 6215 u8 scheduling_hierarchy[0x8]; 6216 u8 reserved_at_48[0x18]; 6217 6218 u8 scheduling_element_id[0x20]; 6219 6220 u8 reserved_at_80[0x20]; 6221 6222 u8 modify_bitmask[0x20]; 6223 6224 u8 reserved_at_c0[0x40]; 6225 6226 struct mlx5_ifc_scheduling_context_bits scheduling_context; 6227 6228 u8 reserved_at_300[0x100]; 6229 }; 6230 6231 struct mlx5_ifc_modify_rqt_out_bits { 6232 u8 status[0x8]; 6233 u8 reserved_at_8[0x18]; 6234 6235 u8 syndrome[0x20]; 6236 6237 u8 reserved_at_40[0x40]; 6238 }; 6239 6240 struct mlx5_ifc_rqt_bitmask_bits { 6241 u8 reserved_at_0[0x20]; 6242 6243 u8 reserved_at_20[0x1f]; 6244 u8 rqn_list[0x1]; 6245 }; 6246 6247 struct mlx5_ifc_modify_rqt_in_bits { 6248 u8 opcode[0x10]; 6249 u8 uid[0x10]; 6250 6251 u8 reserved_at_20[0x10]; 6252 u8 op_mod[0x10]; 6253 6254 u8 reserved_at_40[0x8]; 6255 u8 rqtn[0x18]; 6256 6257 u8 reserved_at_60[0x20]; 6258 6259 struct mlx5_ifc_rqt_bitmask_bits bitmask; 6260 6261 u8 reserved_at_c0[0x40]; 6262 6263 struct mlx5_ifc_rqtc_bits ctx; 6264 }; 6265 6266 struct mlx5_ifc_modify_rq_out_bits { 6267 u8 status[0x8]; 6268 u8 reserved_at_8[0x18]; 6269 6270 u8 syndrome[0x20]; 6271 6272 u8 reserved_at_40[0x40]; 6273 }; 6274 6275 enum { 6276 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1, 6277 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2, 6278 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3, 6279 }; 6280 6281 struct mlx5_ifc_modify_rq_in_bits { 6282 u8 opcode[0x10]; 6283 u8 uid[0x10]; 6284 6285 u8 reserved_at_20[0x10]; 6286 u8 op_mod[0x10]; 6287 6288 u8 rq_state[0x4]; 6289 u8 reserved_at_44[0x4]; 6290 u8 rqn[0x18]; 6291 6292 u8 reserved_at_60[0x20]; 6293 6294 u8 modify_bitmask[0x40]; 6295 6296 u8 reserved_at_c0[0x40]; 6297 6298 struct mlx5_ifc_rqc_bits ctx; 6299 }; 6300 6301 struct mlx5_ifc_modify_rmp_out_bits { 6302 u8 status[0x8]; 6303 u8 reserved_at_8[0x18]; 6304 6305 u8 syndrome[0x20]; 6306 6307 u8 reserved_at_40[0x40]; 6308 }; 6309 6310 struct mlx5_ifc_rmp_bitmask_bits { 6311 u8 reserved_at_0[0x20]; 6312 6313 u8 reserved_at_20[0x1f]; 6314 u8 lwm[0x1]; 6315 }; 6316 6317 struct mlx5_ifc_modify_rmp_in_bits { 6318 u8 opcode[0x10]; 6319 u8 uid[0x10]; 6320 6321 u8 reserved_at_20[0x10]; 6322 u8 op_mod[0x10]; 6323 6324 u8 rmp_state[0x4]; 6325 u8 reserved_at_44[0x4]; 6326 u8 rmpn[0x18]; 6327 6328 u8 reserved_at_60[0x20]; 6329 6330 struct mlx5_ifc_rmp_bitmask_bits bitmask; 6331 6332 u8 reserved_at_c0[0x40]; 6333 6334 struct mlx5_ifc_rmpc_bits ctx; 6335 }; 6336 6337 struct mlx5_ifc_modify_nic_vport_context_out_bits { 6338 u8 status[0x8]; 6339 u8 reserved_at_8[0x18]; 6340 6341 u8 syndrome[0x20]; 6342 6343 u8 reserved_at_40[0x40]; 6344 }; 6345 6346 struct mlx5_ifc_modify_nic_vport_field_select_bits { 6347 u8 reserved_at_0[0x12]; 6348 u8 affiliation[0x1]; 6349 u8 reserved_at_13[0x1]; 6350 u8 disable_uc_local_lb[0x1]; 6351 u8 disable_mc_local_lb[0x1]; 6352 u8 node_guid[0x1]; 6353 u8 port_guid[0x1]; 6354 u8 min_inline[0x1]; 6355 u8 mtu[0x1]; 6356 u8 change_event[0x1]; 6357 u8 promisc[0x1]; 6358 u8 permanent_address[0x1]; 6359 u8 addresses_list[0x1]; 6360 u8 roce_en[0x1]; 6361 u8 reserved_at_1f[0x1]; 6362 }; 6363 6364 struct mlx5_ifc_modify_nic_vport_context_in_bits { 6365 u8 opcode[0x10]; 6366 u8 reserved_at_10[0x10]; 6367 6368 u8 reserved_at_20[0x10]; 6369 u8 op_mod[0x10]; 6370 6371 u8 other_vport[0x1]; 6372 u8 reserved_at_41[0xf]; 6373 u8 vport_number[0x10]; 6374 6375 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select; 6376 6377 u8 reserved_at_80[0x780]; 6378 6379 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 6380 }; 6381 6382 struct mlx5_ifc_modify_hca_vport_context_out_bits { 6383 u8 status[0x8]; 6384 u8 reserved_at_8[0x18]; 6385 6386 u8 syndrome[0x20]; 6387 6388 u8 reserved_at_40[0x40]; 6389 }; 6390 6391 struct mlx5_ifc_modify_hca_vport_context_in_bits { 6392 u8 opcode[0x10]; 6393 u8 reserved_at_10[0x10]; 6394 6395 u8 reserved_at_20[0x10]; 6396 u8 op_mod[0x10]; 6397 6398 u8 other_vport[0x1]; 6399 u8 reserved_at_41[0xb]; 6400 u8 port_num[0x4]; 6401 u8 vport_number[0x10]; 6402 6403 u8 reserved_at_60[0x20]; 6404 6405 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 6406 }; 6407 6408 struct mlx5_ifc_modify_cq_out_bits { 6409 u8 status[0x8]; 6410 u8 reserved_at_8[0x18]; 6411 6412 u8 syndrome[0x20]; 6413 6414 u8 reserved_at_40[0x40]; 6415 }; 6416 6417 enum { 6418 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0, 6419 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1, 6420 }; 6421 6422 struct mlx5_ifc_modify_cq_in_bits { 6423 u8 opcode[0x10]; 6424 u8 uid[0x10]; 6425 6426 u8 reserved_at_20[0x10]; 6427 u8 op_mod[0x10]; 6428 6429 u8 reserved_at_40[0x8]; 6430 u8 cqn[0x18]; 6431 6432 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select; 6433 6434 struct mlx5_ifc_cqc_bits cq_context; 6435 6436 u8 reserved_at_280[0x60]; 6437 6438 u8 cq_umem_valid[0x1]; 6439 u8 reserved_at_2e1[0x1f]; 6440 6441 u8 reserved_at_300[0x580]; 6442 6443 u8 pas[0][0x40]; 6444 }; 6445 6446 struct mlx5_ifc_modify_cong_status_out_bits { 6447 u8 status[0x8]; 6448 u8 reserved_at_8[0x18]; 6449 6450 u8 syndrome[0x20]; 6451 6452 u8 reserved_at_40[0x40]; 6453 }; 6454 6455 struct mlx5_ifc_modify_cong_status_in_bits { 6456 u8 opcode[0x10]; 6457 u8 reserved_at_10[0x10]; 6458 6459 u8 reserved_at_20[0x10]; 6460 u8 op_mod[0x10]; 6461 6462 u8 reserved_at_40[0x18]; 6463 u8 priority[0x4]; 6464 u8 cong_protocol[0x4]; 6465 6466 u8 enable[0x1]; 6467 u8 tag_enable[0x1]; 6468 u8 reserved_at_62[0x1e]; 6469 }; 6470 6471 struct mlx5_ifc_modify_cong_params_out_bits { 6472 u8 status[0x8]; 6473 u8 reserved_at_8[0x18]; 6474 6475 u8 syndrome[0x20]; 6476 6477 u8 reserved_at_40[0x40]; 6478 }; 6479 6480 struct mlx5_ifc_modify_cong_params_in_bits { 6481 u8 opcode[0x10]; 6482 u8 reserved_at_10[0x10]; 6483 6484 u8 reserved_at_20[0x10]; 6485 u8 op_mod[0x10]; 6486 6487 u8 reserved_at_40[0x1c]; 6488 u8 cong_protocol[0x4]; 6489 6490 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select; 6491 6492 u8 reserved_at_80[0x80]; 6493 6494 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 6495 }; 6496 6497 struct mlx5_ifc_manage_pages_out_bits { 6498 u8 status[0x8]; 6499 u8 reserved_at_8[0x18]; 6500 6501 u8 syndrome[0x20]; 6502 6503 u8 output_num_entries[0x20]; 6504 6505 u8 reserved_at_60[0x20]; 6506 6507 u8 pas[0][0x40]; 6508 }; 6509 6510 enum { 6511 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL = 0x0, 6512 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS = 0x1, 6513 MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES = 0x2, 6514 }; 6515 6516 struct mlx5_ifc_manage_pages_in_bits { 6517 u8 opcode[0x10]; 6518 u8 reserved_at_10[0x10]; 6519 6520 u8 reserved_at_20[0x10]; 6521 u8 op_mod[0x10]; 6522 6523 u8 embedded_cpu_function[0x1]; 6524 u8 reserved_at_41[0xf]; 6525 u8 function_id[0x10]; 6526 6527 u8 input_num_entries[0x20]; 6528 6529 u8 pas[0][0x40]; 6530 }; 6531 6532 struct mlx5_ifc_mad_ifc_out_bits { 6533 u8 status[0x8]; 6534 u8 reserved_at_8[0x18]; 6535 6536 u8 syndrome[0x20]; 6537 6538 u8 reserved_at_40[0x40]; 6539 6540 u8 response_mad_packet[256][0x8]; 6541 }; 6542 6543 struct mlx5_ifc_mad_ifc_in_bits { 6544 u8 opcode[0x10]; 6545 u8 reserved_at_10[0x10]; 6546 6547 u8 reserved_at_20[0x10]; 6548 u8 op_mod[0x10]; 6549 6550 u8 remote_lid[0x10]; 6551 u8 reserved_at_50[0x8]; 6552 u8 port[0x8]; 6553 6554 u8 reserved_at_60[0x20]; 6555 6556 u8 mad[256][0x8]; 6557 }; 6558 6559 struct mlx5_ifc_init_hca_out_bits { 6560 u8 status[0x8]; 6561 u8 reserved_at_8[0x18]; 6562 6563 u8 syndrome[0x20]; 6564 6565 u8 reserved_at_40[0x40]; 6566 }; 6567 6568 struct mlx5_ifc_init_hca_in_bits { 6569 u8 opcode[0x10]; 6570 u8 reserved_at_10[0x10]; 6571 6572 u8 reserved_at_20[0x10]; 6573 u8 op_mod[0x10]; 6574 6575 u8 reserved_at_40[0x40]; 6576 u8 sw_owner_id[4][0x20]; 6577 }; 6578 6579 struct mlx5_ifc_init2rtr_qp_out_bits { 6580 u8 status[0x8]; 6581 u8 reserved_at_8[0x18]; 6582 6583 u8 syndrome[0x20]; 6584 6585 u8 reserved_at_40[0x40]; 6586 }; 6587 6588 struct mlx5_ifc_init2rtr_qp_in_bits { 6589 u8 opcode[0x10]; 6590 u8 uid[0x10]; 6591 6592 u8 reserved_at_20[0x10]; 6593 u8 op_mod[0x10]; 6594 6595 u8 reserved_at_40[0x8]; 6596 u8 qpn[0x18]; 6597 6598 u8 reserved_at_60[0x20]; 6599 6600 u8 opt_param_mask[0x20]; 6601 6602 u8 reserved_at_a0[0x20]; 6603 6604 struct mlx5_ifc_qpc_bits qpc; 6605 6606 u8 reserved_at_800[0x80]; 6607 }; 6608 6609 struct mlx5_ifc_init2init_qp_out_bits { 6610 u8 status[0x8]; 6611 u8 reserved_at_8[0x18]; 6612 6613 u8 syndrome[0x20]; 6614 6615 u8 reserved_at_40[0x40]; 6616 }; 6617 6618 struct mlx5_ifc_init2init_qp_in_bits { 6619 u8 opcode[0x10]; 6620 u8 uid[0x10]; 6621 6622 u8 reserved_at_20[0x10]; 6623 u8 op_mod[0x10]; 6624 6625 u8 reserved_at_40[0x8]; 6626 u8 qpn[0x18]; 6627 6628 u8 reserved_at_60[0x20]; 6629 6630 u8 opt_param_mask[0x20]; 6631 6632 u8 reserved_at_a0[0x20]; 6633 6634 struct mlx5_ifc_qpc_bits qpc; 6635 6636 u8 reserved_at_800[0x80]; 6637 }; 6638 6639 struct mlx5_ifc_get_dropped_packet_log_out_bits { 6640 u8 status[0x8]; 6641 u8 reserved_at_8[0x18]; 6642 6643 u8 syndrome[0x20]; 6644 6645 u8 reserved_at_40[0x40]; 6646 6647 u8 packet_headers_log[128][0x8]; 6648 6649 u8 packet_syndrome[64][0x8]; 6650 }; 6651 6652 struct mlx5_ifc_get_dropped_packet_log_in_bits { 6653 u8 opcode[0x10]; 6654 u8 reserved_at_10[0x10]; 6655 6656 u8 reserved_at_20[0x10]; 6657 u8 op_mod[0x10]; 6658 6659 u8 reserved_at_40[0x40]; 6660 }; 6661 6662 struct mlx5_ifc_gen_eqe_in_bits { 6663 u8 opcode[0x10]; 6664 u8 reserved_at_10[0x10]; 6665 6666 u8 reserved_at_20[0x10]; 6667 u8 op_mod[0x10]; 6668 6669 u8 reserved_at_40[0x18]; 6670 u8 eq_number[0x8]; 6671 6672 u8 reserved_at_60[0x20]; 6673 6674 u8 eqe[64][0x8]; 6675 }; 6676 6677 struct mlx5_ifc_gen_eq_out_bits { 6678 u8 status[0x8]; 6679 u8 reserved_at_8[0x18]; 6680 6681 u8 syndrome[0x20]; 6682 6683 u8 reserved_at_40[0x40]; 6684 }; 6685 6686 struct mlx5_ifc_enable_hca_out_bits { 6687 u8 status[0x8]; 6688 u8 reserved_at_8[0x18]; 6689 6690 u8 syndrome[0x20]; 6691 6692 u8 reserved_at_40[0x20]; 6693 }; 6694 6695 struct mlx5_ifc_enable_hca_in_bits { 6696 u8 opcode[0x10]; 6697 u8 reserved_at_10[0x10]; 6698 6699 u8 reserved_at_20[0x10]; 6700 u8 op_mod[0x10]; 6701 6702 u8 embedded_cpu_function[0x1]; 6703 u8 reserved_at_41[0xf]; 6704 u8 function_id[0x10]; 6705 6706 u8 reserved_at_60[0x20]; 6707 }; 6708 6709 struct mlx5_ifc_drain_dct_out_bits { 6710 u8 status[0x8]; 6711 u8 reserved_at_8[0x18]; 6712 6713 u8 syndrome[0x20]; 6714 6715 u8 reserved_at_40[0x40]; 6716 }; 6717 6718 struct mlx5_ifc_drain_dct_in_bits { 6719 u8 opcode[0x10]; 6720 u8 uid[0x10]; 6721 6722 u8 reserved_at_20[0x10]; 6723 u8 op_mod[0x10]; 6724 6725 u8 reserved_at_40[0x8]; 6726 u8 dctn[0x18]; 6727 6728 u8 reserved_at_60[0x20]; 6729 }; 6730 6731 struct mlx5_ifc_disable_hca_out_bits { 6732 u8 status[0x8]; 6733 u8 reserved_at_8[0x18]; 6734 6735 u8 syndrome[0x20]; 6736 6737 u8 reserved_at_40[0x20]; 6738 }; 6739 6740 struct mlx5_ifc_disable_hca_in_bits { 6741 u8 opcode[0x10]; 6742 u8 reserved_at_10[0x10]; 6743 6744 u8 reserved_at_20[0x10]; 6745 u8 op_mod[0x10]; 6746 6747 u8 embedded_cpu_function[0x1]; 6748 u8 reserved_at_41[0xf]; 6749 u8 function_id[0x10]; 6750 6751 u8 reserved_at_60[0x20]; 6752 }; 6753 6754 struct mlx5_ifc_detach_from_mcg_out_bits { 6755 u8 status[0x8]; 6756 u8 reserved_at_8[0x18]; 6757 6758 u8 syndrome[0x20]; 6759 6760 u8 reserved_at_40[0x40]; 6761 }; 6762 6763 struct mlx5_ifc_detach_from_mcg_in_bits { 6764 u8 opcode[0x10]; 6765 u8 uid[0x10]; 6766 6767 u8 reserved_at_20[0x10]; 6768 u8 op_mod[0x10]; 6769 6770 u8 reserved_at_40[0x8]; 6771 u8 qpn[0x18]; 6772 6773 u8 reserved_at_60[0x20]; 6774 6775 u8 multicast_gid[16][0x8]; 6776 }; 6777 6778 struct mlx5_ifc_destroy_xrq_out_bits { 6779 u8 status[0x8]; 6780 u8 reserved_at_8[0x18]; 6781 6782 u8 syndrome[0x20]; 6783 6784 u8 reserved_at_40[0x40]; 6785 }; 6786 6787 struct mlx5_ifc_destroy_xrq_in_bits { 6788 u8 opcode[0x10]; 6789 u8 uid[0x10]; 6790 6791 u8 reserved_at_20[0x10]; 6792 u8 op_mod[0x10]; 6793 6794 u8 reserved_at_40[0x8]; 6795 u8 xrqn[0x18]; 6796 6797 u8 reserved_at_60[0x20]; 6798 }; 6799 6800 struct mlx5_ifc_destroy_xrc_srq_out_bits { 6801 u8 status[0x8]; 6802 u8 reserved_at_8[0x18]; 6803 6804 u8 syndrome[0x20]; 6805 6806 u8 reserved_at_40[0x40]; 6807 }; 6808 6809 struct mlx5_ifc_destroy_xrc_srq_in_bits { 6810 u8 opcode[0x10]; 6811 u8 uid[0x10]; 6812 6813 u8 reserved_at_20[0x10]; 6814 u8 op_mod[0x10]; 6815 6816 u8 reserved_at_40[0x8]; 6817 u8 xrc_srqn[0x18]; 6818 6819 u8 reserved_at_60[0x20]; 6820 }; 6821 6822 struct mlx5_ifc_destroy_tis_out_bits { 6823 u8 status[0x8]; 6824 u8 reserved_at_8[0x18]; 6825 6826 u8 syndrome[0x20]; 6827 6828 u8 reserved_at_40[0x40]; 6829 }; 6830 6831 struct mlx5_ifc_destroy_tis_in_bits { 6832 u8 opcode[0x10]; 6833 u8 uid[0x10]; 6834 6835 u8 reserved_at_20[0x10]; 6836 u8 op_mod[0x10]; 6837 6838 u8 reserved_at_40[0x8]; 6839 u8 tisn[0x18]; 6840 6841 u8 reserved_at_60[0x20]; 6842 }; 6843 6844 struct mlx5_ifc_destroy_tir_out_bits { 6845 u8 status[0x8]; 6846 u8 reserved_at_8[0x18]; 6847 6848 u8 syndrome[0x20]; 6849 6850 u8 reserved_at_40[0x40]; 6851 }; 6852 6853 struct mlx5_ifc_destroy_tir_in_bits { 6854 u8 opcode[0x10]; 6855 u8 uid[0x10]; 6856 6857 u8 reserved_at_20[0x10]; 6858 u8 op_mod[0x10]; 6859 6860 u8 reserved_at_40[0x8]; 6861 u8 tirn[0x18]; 6862 6863 u8 reserved_at_60[0x20]; 6864 }; 6865 6866 struct mlx5_ifc_destroy_srq_out_bits { 6867 u8 status[0x8]; 6868 u8 reserved_at_8[0x18]; 6869 6870 u8 syndrome[0x20]; 6871 6872 u8 reserved_at_40[0x40]; 6873 }; 6874 6875 struct mlx5_ifc_destroy_srq_in_bits { 6876 u8 opcode[0x10]; 6877 u8 uid[0x10]; 6878 6879 u8 reserved_at_20[0x10]; 6880 u8 op_mod[0x10]; 6881 6882 u8 reserved_at_40[0x8]; 6883 u8 srqn[0x18]; 6884 6885 u8 reserved_at_60[0x20]; 6886 }; 6887 6888 struct mlx5_ifc_destroy_sq_out_bits { 6889 u8 status[0x8]; 6890 u8 reserved_at_8[0x18]; 6891 6892 u8 syndrome[0x20]; 6893 6894 u8 reserved_at_40[0x40]; 6895 }; 6896 6897 struct mlx5_ifc_destroy_sq_in_bits { 6898 u8 opcode[0x10]; 6899 u8 uid[0x10]; 6900 6901 u8 reserved_at_20[0x10]; 6902 u8 op_mod[0x10]; 6903 6904 u8 reserved_at_40[0x8]; 6905 u8 sqn[0x18]; 6906 6907 u8 reserved_at_60[0x20]; 6908 }; 6909 6910 struct mlx5_ifc_destroy_scheduling_element_out_bits { 6911 u8 status[0x8]; 6912 u8 reserved_at_8[0x18]; 6913 6914 u8 syndrome[0x20]; 6915 6916 u8 reserved_at_40[0x1c0]; 6917 }; 6918 6919 struct mlx5_ifc_destroy_scheduling_element_in_bits { 6920 u8 opcode[0x10]; 6921 u8 reserved_at_10[0x10]; 6922 6923 u8 reserved_at_20[0x10]; 6924 u8 op_mod[0x10]; 6925 6926 u8 scheduling_hierarchy[0x8]; 6927 u8 reserved_at_48[0x18]; 6928 6929 u8 scheduling_element_id[0x20]; 6930 6931 u8 reserved_at_80[0x180]; 6932 }; 6933 6934 struct mlx5_ifc_destroy_rqt_out_bits { 6935 u8 status[0x8]; 6936 u8 reserved_at_8[0x18]; 6937 6938 u8 syndrome[0x20]; 6939 6940 u8 reserved_at_40[0x40]; 6941 }; 6942 6943 struct mlx5_ifc_destroy_rqt_in_bits { 6944 u8 opcode[0x10]; 6945 u8 uid[0x10]; 6946 6947 u8 reserved_at_20[0x10]; 6948 u8 op_mod[0x10]; 6949 6950 u8 reserved_at_40[0x8]; 6951 u8 rqtn[0x18]; 6952 6953 u8 reserved_at_60[0x20]; 6954 }; 6955 6956 struct mlx5_ifc_destroy_rq_out_bits { 6957 u8 status[0x8]; 6958 u8 reserved_at_8[0x18]; 6959 6960 u8 syndrome[0x20]; 6961 6962 u8 reserved_at_40[0x40]; 6963 }; 6964 6965 struct mlx5_ifc_destroy_rq_in_bits { 6966 u8 opcode[0x10]; 6967 u8 uid[0x10]; 6968 6969 u8 reserved_at_20[0x10]; 6970 u8 op_mod[0x10]; 6971 6972 u8 reserved_at_40[0x8]; 6973 u8 rqn[0x18]; 6974 6975 u8 reserved_at_60[0x20]; 6976 }; 6977 6978 struct mlx5_ifc_set_delay_drop_params_in_bits { 6979 u8 opcode[0x10]; 6980 u8 reserved_at_10[0x10]; 6981 6982 u8 reserved_at_20[0x10]; 6983 u8 op_mod[0x10]; 6984 6985 u8 reserved_at_40[0x20]; 6986 6987 u8 reserved_at_60[0x10]; 6988 u8 delay_drop_timeout[0x10]; 6989 }; 6990 6991 struct mlx5_ifc_set_delay_drop_params_out_bits { 6992 u8 status[0x8]; 6993 u8 reserved_at_8[0x18]; 6994 6995 u8 syndrome[0x20]; 6996 6997 u8 reserved_at_40[0x40]; 6998 }; 6999 7000 struct mlx5_ifc_destroy_rmp_out_bits { 7001 u8 status[0x8]; 7002 u8 reserved_at_8[0x18]; 7003 7004 u8 syndrome[0x20]; 7005 7006 u8 reserved_at_40[0x40]; 7007 }; 7008 7009 struct mlx5_ifc_destroy_rmp_in_bits { 7010 u8 opcode[0x10]; 7011 u8 uid[0x10]; 7012 7013 u8 reserved_at_20[0x10]; 7014 u8 op_mod[0x10]; 7015 7016 u8 reserved_at_40[0x8]; 7017 u8 rmpn[0x18]; 7018 7019 u8 reserved_at_60[0x20]; 7020 }; 7021 7022 struct mlx5_ifc_destroy_qp_out_bits { 7023 u8 status[0x8]; 7024 u8 reserved_at_8[0x18]; 7025 7026 u8 syndrome[0x20]; 7027 7028 u8 reserved_at_40[0x40]; 7029 }; 7030 7031 struct mlx5_ifc_destroy_qp_in_bits { 7032 u8 opcode[0x10]; 7033 u8 uid[0x10]; 7034 7035 u8 reserved_at_20[0x10]; 7036 u8 op_mod[0x10]; 7037 7038 u8 reserved_at_40[0x8]; 7039 u8 qpn[0x18]; 7040 7041 u8 reserved_at_60[0x20]; 7042 }; 7043 7044 struct mlx5_ifc_destroy_psv_out_bits { 7045 u8 status[0x8]; 7046 u8 reserved_at_8[0x18]; 7047 7048 u8 syndrome[0x20]; 7049 7050 u8 reserved_at_40[0x40]; 7051 }; 7052 7053 struct mlx5_ifc_destroy_psv_in_bits { 7054 u8 opcode[0x10]; 7055 u8 reserved_at_10[0x10]; 7056 7057 u8 reserved_at_20[0x10]; 7058 u8 op_mod[0x10]; 7059 7060 u8 reserved_at_40[0x8]; 7061 u8 psvn[0x18]; 7062 7063 u8 reserved_at_60[0x20]; 7064 }; 7065 7066 struct mlx5_ifc_destroy_mkey_out_bits { 7067 u8 status[0x8]; 7068 u8 reserved_at_8[0x18]; 7069 7070 u8 syndrome[0x20]; 7071 7072 u8 reserved_at_40[0x40]; 7073 }; 7074 7075 struct mlx5_ifc_destroy_mkey_in_bits { 7076 u8 opcode[0x10]; 7077 u8 reserved_at_10[0x10]; 7078 7079 u8 reserved_at_20[0x10]; 7080 u8 op_mod[0x10]; 7081 7082 u8 reserved_at_40[0x8]; 7083 u8 mkey_index[0x18]; 7084 7085 u8 reserved_at_60[0x20]; 7086 }; 7087 7088 struct mlx5_ifc_destroy_flow_table_out_bits { 7089 u8 status[0x8]; 7090 u8 reserved_at_8[0x18]; 7091 7092 u8 syndrome[0x20]; 7093 7094 u8 reserved_at_40[0x40]; 7095 }; 7096 7097 struct mlx5_ifc_destroy_flow_table_in_bits { 7098 u8 opcode[0x10]; 7099 u8 reserved_at_10[0x10]; 7100 7101 u8 reserved_at_20[0x10]; 7102 u8 op_mod[0x10]; 7103 7104 u8 other_vport[0x1]; 7105 u8 reserved_at_41[0xf]; 7106 u8 vport_number[0x10]; 7107 7108 u8 reserved_at_60[0x20]; 7109 7110 u8 table_type[0x8]; 7111 u8 reserved_at_88[0x18]; 7112 7113 u8 reserved_at_a0[0x8]; 7114 u8 table_id[0x18]; 7115 7116 u8 reserved_at_c0[0x140]; 7117 }; 7118 7119 struct mlx5_ifc_destroy_flow_group_out_bits { 7120 u8 status[0x8]; 7121 u8 reserved_at_8[0x18]; 7122 7123 u8 syndrome[0x20]; 7124 7125 u8 reserved_at_40[0x40]; 7126 }; 7127 7128 struct mlx5_ifc_destroy_flow_group_in_bits { 7129 u8 opcode[0x10]; 7130 u8 reserved_at_10[0x10]; 7131 7132 u8 reserved_at_20[0x10]; 7133 u8 op_mod[0x10]; 7134 7135 u8 other_vport[0x1]; 7136 u8 reserved_at_41[0xf]; 7137 u8 vport_number[0x10]; 7138 7139 u8 reserved_at_60[0x20]; 7140 7141 u8 table_type[0x8]; 7142 u8 reserved_at_88[0x18]; 7143 7144 u8 reserved_at_a0[0x8]; 7145 u8 table_id[0x18]; 7146 7147 u8 group_id[0x20]; 7148 7149 u8 reserved_at_e0[0x120]; 7150 }; 7151 7152 struct mlx5_ifc_destroy_eq_out_bits { 7153 u8 status[0x8]; 7154 u8 reserved_at_8[0x18]; 7155 7156 u8 syndrome[0x20]; 7157 7158 u8 reserved_at_40[0x40]; 7159 }; 7160 7161 struct mlx5_ifc_destroy_eq_in_bits { 7162 u8 opcode[0x10]; 7163 u8 reserved_at_10[0x10]; 7164 7165 u8 reserved_at_20[0x10]; 7166 u8 op_mod[0x10]; 7167 7168 u8 reserved_at_40[0x18]; 7169 u8 eq_number[0x8]; 7170 7171 u8 reserved_at_60[0x20]; 7172 }; 7173 7174 struct mlx5_ifc_destroy_dct_out_bits { 7175 u8 status[0x8]; 7176 u8 reserved_at_8[0x18]; 7177 7178 u8 syndrome[0x20]; 7179 7180 u8 reserved_at_40[0x40]; 7181 }; 7182 7183 struct mlx5_ifc_destroy_dct_in_bits { 7184 u8 opcode[0x10]; 7185 u8 uid[0x10]; 7186 7187 u8 reserved_at_20[0x10]; 7188 u8 op_mod[0x10]; 7189 7190 u8 reserved_at_40[0x8]; 7191 u8 dctn[0x18]; 7192 7193 u8 reserved_at_60[0x20]; 7194 }; 7195 7196 struct mlx5_ifc_destroy_cq_out_bits { 7197 u8 status[0x8]; 7198 u8 reserved_at_8[0x18]; 7199 7200 u8 syndrome[0x20]; 7201 7202 u8 reserved_at_40[0x40]; 7203 }; 7204 7205 struct mlx5_ifc_destroy_cq_in_bits { 7206 u8 opcode[0x10]; 7207 u8 uid[0x10]; 7208 7209 u8 reserved_at_20[0x10]; 7210 u8 op_mod[0x10]; 7211 7212 u8 reserved_at_40[0x8]; 7213 u8 cqn[0x18]; 7214 7215 u8 reserved_at_60[0x20]; 7216 }; 7217 7218 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits { 7219 u8 status[0x8]; 7220 u8 reserved_at_8[0x18]; 7221 7222 u8 syndrome[0x20]; 7223 7224 u8 reserved_at_40[0x40]; 7225 }; 7226 7227 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits { 7228 u8 opcode[0x10]; 7229 u8 reserved_at_10[0x10]; 7230 7231 u8 reserved_at_20[0x10]; 7232 u8 op_mod[0x10]; 7233 7234 u8 reserved_at_40[0x20]; 7235 7236 u8 reserved_at_60[0x10]; 7237 u8 vxlan_udp_port[0x10]; 7238 }; 7239 7240 struct mlx5_ifc_delete_l2_table_entry_out_bits { 7241 u8 status[0x8]; 7242 u8 reserved_at_8[0x18]; 7243 7244 u8 syndrome[0x20]; 7245 7246 u8 reserved_at_40[0x40]; 7247 }; 7248 7249 struct mlx5_ifc_delete_l2_table_entry_in_bits { 7250 u8 opcode[0x10]; 7251 u8 reserved_at_10[0x10]; 7252 7253 u8 reserved_at_20[0x10]; 7254 u8 op_mod[0x10]; 7255 7256 u8 reserved_at_40[0x60]; 7257 7258 u8 reserved_at_a0[0x8]; 7259 u8 table_index[0x18]; 7260 7261 u8 reserved_at_c0[0x140]; 7262 }; 7263 7264 struct mlx5_ifc_delete_fte_out_bits { 7265 u8 status[0x8]; 7266 u8 reserved_at_8[0x18]; 7267 7268 u8 syndrome[0x20]; 7269 7270 u8 reserved_at_40[0x40]; 7271 }; 7272 7273 struct mlx5_ifc_delete_fte_in_bits { 7274 u8 opcode[0x10]; 7275 u8 reserved_at_10[0x10]; 7276 7277 u8 reserved_at_20[0x10]; 7278 u8 op_mod[0x10]; 7279 7280 u8 other_vport[0x1]; 7281 u8 reserved_at_41[0xf]; 7282 u8 vport_number[0x10]; 7283 7284 u8 reserved_at_60[0x20]; 7285 7286 u8 table_type[0x8]; 7287 u8 reserved_at_88[0x18]; 7288 7289 u8 reserved_at_a0[0x8]; 7290 u8 table_id[0x18]; 7291 7292 u8 reserved_at_c0[0x40]; 7293 7294 u8 flow_index[0x20]; 7295 7296 u8 reserved_at_120[0xe0]; 7297 }; 7298 7299 struct mlx5_ifc_dealloc_xrcd_out_bits { 7300 u8 status[0x8]; 7301 u8 reserved_at_8[0x18]; 7302 7303 u8 syndrome[0x20]; 7304 7305 u8 reserved_at_40[0x40]; 7306 }; 7307 7308 struct mlx5_ifc_dealloc_xrcd_in_bits { 7309 u8 opcode[0x10]; 7310 u8 uid[0x10]; 7311 7312 u8 reserved_at_20[0x10]; 7313 u8 op_mod[0x10]; 7314 7315 u8 reserved_at_40[0x8]; 7316 u8 xrcd[0x18]; 7317 7318 u8 reserved_at_60[0x20]; 7319 }; 7320 7321 struct mlx5_ifc_dealloc_uar_out_bits { 7322 u8 status[0x8]; 7323 u8 reserved_at_8[0x18]; 7324 7325 u8 syndrome[0x20]; 7326 7327 u8 reserved_at_40[0x40]; 7328 }; 7329 7330 struct mlx5_ifc_dealloc_uar_in_bits { 7331 u8 opcode[0x10]; 7332 u8 reserved_at_10[0x10]; 7333 7334 u8 reserved_at_20[0x10]; 7335 u8 op_mod[0x10]; 7336 7337 u8 reserved_at_40[0x8]; 7338 u8 uar[0x18]; 7339 7340 u8 reserved_at_60[0x20]; 7341 }; 7342 7343 struct mlx5_ifc_dealloc_transport_domain_out_bits { 7344 u8 status[0x8]; 7345 u8 reserved_at_8[0x18]; 7346 7347 u8 syndrome[0x20]; 7348 7349 u8 reserved_at_40[0x40]; 7350 }; 7351 7352 struct mlx5_ifc_dealloc_transport_domain_in_bits { 7353 u8 opcode[0x10]; 7354 u8 uid[0x10]; 7355 7356 u8 reserved_at_20[0x10]; 7357 u8 op_mod[0x10]; 7358 7359 u8 reserved_at_40[0x8]; 7360 u8 transport_domain[0x18]; 7361 7362 u8 reserved_at_60[0x20]; 7363 }; 7364 7365 struct mlx5_ifc_dealloc_q_counter_out_bits { 7366 u8 status[0x8]; 7367 u8 reserved_at_8[0x18]; 7368 7369 u8 syndrome[0x20]; 7370 7371 u8 reserved_at_40[0x40]; 7372 }; 7373 7374 struct mlx5_ifc_dealloc_q_counter_in_bits { 7375 u8 opcode[0x10]; 7376 u8 reserved_at_10[0x10]; 7377 7378 u8 reserved_at_20[0x10]; 7379 u8 op_mod[0x10]; 7380 7381 u8 reserved_at_40[0x18]; 7382 u8 counter_set_id[0x8]; 7383 7384 u8 reserved_at_60[0x20]; 7385 }; 7386 7387 struct mlx5_ifc_dealloc_pd_out_bits { 7388 u8 status[0x8]; 7389 u8 reserved_at_8[0x18]; 7390 7391 u8 syndrome[0x20]; 7392 7393 u8 reserved_at_40[0x40]; 7394 }; 7395 7396 struct mlx5_ifc_dealloc_pd_in_bits { 7397 u8 opcode[0x10]; 7398 u8 uid[0x10]; 7399 7400 u8 reserved_at_20[0x10]; 7401 u8 op_mod[0x10]; 7402 7403 u8 reserved_at_40[0x8]; 7404 u8 pd[0x18]; 7405 7406 u8 reserved_at_60[0x20]; 7407 }; 7408 7409 struct mlx5_ifc_dealloc_flow_counter_out_bits { 7410 u8 status[0x8]; 7411 u8 reserved_at_8[0x18]; 7412 7413 u8 syndrome[0x20]; 7414 7415 u8 reserved_at_40[0x40]; 7416 }; 7417 7418 struct mlx5_ifc_dealloc_flow_counter_in_bits { 7419 u8 opcode[0x10]; 7420 u8 reserved_at_10[0x10]; 7421 7422 u8 reserved_at_20[0x10]; 7423 u8 op_mod[0x10]; 7424 7425 u8 flow_counter_id[0x20]; 7426 7427 u8 reserved_at_60[0x20]; 7428 }; 7429 7430 struct mlx5_ifc_create_xrq_out_bits { 7431 u8 status[0x8]; 7432 u8 reserved_at_8[0x18]; 7433 7434 u8 syndrome[0x20]; 7435 7436 u8 reserved_at_40[0x8]; 7437 u8 xrqn[0x18]; 7438 7439 u8 reserved_at_60[0x20]; 7440 }; 7441 7442 struct mlx5_ifc_create_xrq_in_bits { 7443 u8 opcode[0x10]; 7444 u8 uid[0x10]; 7445 7446 u8 reserved_at_20[0x10]; 7447 u8 op_mod[0x10]; 7448 7449 u8 reserved_at_40[0x40]; 7450 7451 struct mlx5_ifc_xrqc_bits xrq_context; 7452 }; 7453 7454 struct mlx5_ifc_create_xrc_srq_out_bits { 7455 u8 status[0x8]; 7456 u8 reserved_at_8[0x18]; 7457 7458 u8 syndrome[0x20]; 7459 7460 u8 reserved_at_40[0x8]; 7461 u8 xrc_srqn[0x18]; 7462 7463 u8 reserved_at_60[0x20]; 7464 }; 7465 7466 struct mlx5_ifc_create_xrc_srq_in_bits { 7467 u8 opcode[0x10]; 7468 u8 uid[0x10]; 7469 7470 u8 reserved_at_20[0x10]; 7471 u8 op_mod[0x10]; 7472 7473 u8 reserved_at_40[0x40]; 7474 7475 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 7476 7477 u8 reserved_at_280[0x60]; 7478 7479 u8 xrc_srq_umem_valid[0x1]; 7480 u8 reserved_at_2e1[0x1f]; 7481 7482 u8 reserved_at_300[0x580]; 7483 7484 u8 pas[0][0x40]; 7485 }; 7486 7487 struct mlx5_ifc_create_tis_out_bits { 7488 u8 status[0x8]; 7489 u8 reserved_at_8[0x18]; 7490 7491 u8 syndrome[0x20]; 7492 7493 u8 reserved_at_40[0x8]; 7494 u8 tisn[0x18]; 7495 7496 u8 reserved_at_60[0x20]; 7497 }; 7498 7499 struct mlx5_ifc_create_tis_in_bits { 7500 u8 opcode[0x10]; 7501 u8 uid[0x10]; 7502 7503 u8 reserved_at_20[0x10]; 7504 u8 op_mod[0x10]; 7505 7506 u8 reserved_at_40[0xc0]; 7507 7508 struct mlx5_ifc_tisc_bits ctx; 7509 }; 7510 7511 struct mlx5_ifc_create_tir_out_bits { 7512 u8 status[0x8]; 7513 u8 icm_address_63_40[0x18]; 7514 7515 u8 syndrome[0x20]; 7516 7517 u8 icm_address_39_32[0x8]; 7518 u8 tirn[0x18]; 7519 7520 u8 icm_address_31_0[0x20]; 7521 }; 7522 7523 struct mlx5_ifc_create_tir_in_bits { 7524 u8 opcode[0x10]; 7525 u8 uid[0x10]; 7526 7527 u8 reserved_at_20[0x10]; 7528 u8 op_mod[0x10]; 7529 7530 u8 reserved_at_40[0xc0]; 7531 7532 struct mlx5_ifc_tirc_bits ctx; 7533 }; 7534 7535 struct mlx5_ifc_create_srq_out_bits { 7536 u8 status[0x8]; 7537 u8 reserved_at_8[0x18]; 7538 7539 u8 syndrome[0x20]; 7540 7541 u8 reserved_at_40[0x8]; 7542 u8 srqn[0x18]; 7543 7544 u8 reserved_at_60[0x20]; 7545 }; 7546 7547 struct mlx5_ifc_create_srq_in_bits { 7548 u8 opcode[0x10]; 7549 u8 uid[0x10]; 7550 7551 u8 reserved_at_20[0x10]; 7552 u8 op_mod[0x10]; 7553 7554 u8 reserved_at_40[0x40]; 7555 7556 struct mlx5_ifc_srqc_bits srq_context_entry; 7557 7558 u8 reserved_at_280[0x600]; 7559 7560 u8 pas[0][0x40]; 7561 }; 7562 7563 struct mlx5_ifc_create_sq_out_bits { 7564 u8 status[0x8]; 7565 u8 reserved_at_8[0x18]; 7566 7567 u8 syndrome[0x20]; 7568 7569 u8 reserved_at_40[0x8]; 7570 u8 sqn[0x18]; 7571 7572 u8 reserved_at_60[0x20]; 7573 }; 7574 7575 struct mlx5_ifc_create_sq_in_bits { 7576 u8 opcode[0x10]; 7577 u8 uid[0x10]; 7578 7579 u8 reserved_at_20[0x10]; 7580 u8 op_mod[0x10]; 7581 7582 u8 reserved_at_40[0xc0]; 7583 7584 struct mlx5_ifc_sqc_bits ctx; 7585 }; 7586 7587 struct mlx5_ifc_create_scheduling_element_out_bits { 7588 u8 status[0x8]; 7589 u8 reserved_at_8[0x18]; 7590 7591 u8 syndrome[0x20]; 7592 7593 u8 reserved_at_40[0x40]; 7594 7595 u8 scheduling_element_id[0x20]; 7596 7597 u8 reserved_at_a0[0x160]; 7598 }; 7599 7600 struct mlx5_ifc_create_scheduling_element_in_bits { 7601 u8 opcode[0x10]; 7602 u8 reserved_at_10[0x10]; 7603 7604 u8 reserved_at_20[0x10]; 7605 u8 op_mod[0x10]; 7606 7607 u8 scheduling_hierarchy[0x8]; 7608 u8 reserved_at_48[0x18]; 7609 7610 u8 reserved_at_60[0xa0]; 7611 7612 struct mlx5_ifc_scheduling_context_bits scheduling_context; 7613 7614 u8 reserved_at_300[0x100]; 7615 }; 7616 7617 struct mlx5_ifc_create_rqt_out_bits { 7618 u8 status[0x8]; 7619 u8 reserved_at_8[0x18]; 7620 7621 u8 syndrome[0x20]; 7622 7623 u8 reserved_at_40[0x8]; 7624 u8 rqtn[0x18]; 7625 7626 u8 reserved_at_60[0x20]; 7627 }; 7628 7629 struct mlx5_ifc_create_rqt_in_bits { 7630 u8 opcode[0x10]; 7631 u8 uid[0x10]; 7632 7633 u8 reserved_at_20[0x10]; 7634 u8 op_mod[0x10]; 7635 7636 u8 reserved_at_40[0xc0]; 7637 7638 struct mlx5_ifc_rqtc_bits rqt_context; 7639 }; 7640 7641 struct mlx5_ifc_create_rq_out_bits { 7642 u8 status[0x8]; 7643 u8 reserved_at_8[0x18]; 7644 7645 u8 syndrome[0x20]; 7646 7647 u8 reserved_at_40[0x8]; 7648 u8 rqn[0x18]; 7649 7650 u8 reserved_at_60[0x20]; 7651 }; 7652 7653 struct mlx5_ifc_create_rq_in_bits { 7654 u8 opcode[0x10]; 7655 u8 uid[0x10]; 7656 7657 u8 reserved_at_20[0x10]; 7658 u8 op_mod[0x10]; 7659 7660 u8 reserved_at_40[0xc0]; 7661 7662 struct mlx5_ifc_rqc_bits ctx; 7663 }; 7664 7665 struct mlx5_ifc_create_rmp_out_bits { 7666 u8 status[0x8]; 7667 u8 reserved_at_8[0x18]; 7668 7669 u8 syndrome[0x20]; 7670 7671 u8 reserved_at_40[0x8]; 7672 u8 rmpn[0x18]; 7673 7674 u8 reserved_at_60[0x20]; 7675 }; 7676 7677 struct mlx5_ifc_create_rmp_in_bits { 7678 u8 opcode[0x10]; 7679 u8 uid[0x10]; 7680 7681 u8 reserved_at_20[0x10]; 7682 u8 op_mod[0x10]; 7683 7684 u8 reserved_at_40[0xc0]; 7685 7686 struct mlx5_ifc_rmpc_bits ctx; 7687 }; 7688 7689 struct mlx5_ifc_create_qp_out_bits { 7690 u8 status[0x8]; 7691 u8 reserved_at_8[0x18]; 7692 7693 u8 syndrome[0x20]; 7694 7695 u8 reserved_at_40[0x8]; 7696 u8 qpn[0x18]; 7697 7698 u8 reserved_at_60[0x20]; 7699 }; 7700 7701 struct mlx5_ifc_create_qp_in_bits { 7702 u8 opcode[0x10]; 7703 u8 uid[0x10]; 7704 7705 u8 reserved_at_20[0x10]; 7706 u8 op_mod[0x10]; 7707 7708 u8 reserved_at_40[0x40]; 7709 7710 u8 opt_param_mask[0x20]; 7711 7712 u8 reserved_at_a0[0x20]; 7713 7714 struct mlx5_ifc_qpc_bits qpc; 7715 7716 u8 reserved_at_800[0x60]; 7717 7718 u8 wq_umem_valid[0x1]; 7719 u8 reserved_at_861[0x1f]; 7720 7721 u8 pas[0][0x40]; 7722 }; 7723 7724 struct mlx5_ifc_create_psv_out_bits { 7725 u8 status[0x8]; 7726 u8 reserved_at_8[0x18]; 7727 7728 u8 syndrome[0x20]; 7729 7730 u8 reserved_at_40[0x40]; 7731 7732 u8 reserved_at_80[0x8]; 7733 u8 psv0_index[0x18]; 7734 7735 u8 reserved_at_a0[0x8]; 7736 u8 psv1_index[0x18]; 7737 7738 u8 reserved_at_c0[0x8]; 7739 u8 psv2_index[0x18]; 7740 7741 u8 reserved_at_e0[0x8]; 7742 u8 psv3_index[0x18]; 7743 }; 7744 7745 struct mlx5_ifc_create_psv_in_bits { 7746 u8 opcode[0x10]; 7747 u8 reserved_at_10[0x10]; 7748 7749 u8 reserved_at_20[0x10]; 7750 u8 op_mod[0x10]; 7751 7752 u8 num_psv[0x4]; 7753 u8 reserved_at_44[0x4]; 7754 u8 pd[0x18]; 7755 7756 u8 reserved_at_60[0x20]; 7757 }; 7758 7759 struct mlx5_ifc_create_mkey_out_bits { 7760 u8 status[0x8]; 7761 u8 reserved_at_8[0x18]; 7762 7763 u8 syndrome[0x20]; 7764 7765 u8 reserved_at_40[0x8]; 7766 u8 mkey_index[0x18]; 7767 7768 u8 reserved_at_60[0x20]; 7769 }; 7770 7771 struct mlx5_ifc_create_mkey_in_bits { 7772 u8 opcode[0x10]; 7773 u8 reserved_at_10[0x10]; 7774 7775 u8 reserved_at_20[0x10]; 7776 u8 op_mod[0x10]; 7777 7778 u8 reserved_at_40[0x20]; 7779 7780 u8 pg_access[0x1]; 7781 u8 mkey_umem_valid[0x1]; 7782 u8 reserved_at_62[0x1e]; 7783 7784 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 7785 7786 u8 reserved_at_280[0x80]; 7787 7788 u8 translations_octword_actual_size[0x20]; 7789 7790 u8 reserved_at_320[0x560]; 7791 7792 u8 klm_pas_mtt[0][0x20]; 7793 }; 7794 7795 enum { 7796 MLX5_FLOW_TABLE_TYPE_NIC_RX = 0x0, 7797 MLX5_FLOW_TABLE_TYPE_NIC_TX = 0x1, 7798 MLX5_FLOW_TABLE_TYPE_ESW_EGRESS_ACL = 0x2, 7799 MLX5_FLOW_TABLE_TYPE_ESW_INGRESS_ACL = 0x3, 7800 MLX5_FLOW_TABLE_TYPE_FDB = 0X4, 7801 MLX5_FLOW_TABLE_TYPE_SNIFFER_RX = 0X5, 7802 MLX5_FLOW_TABLE_TYPE_SNIFFER_TX = 0X6, 7803 }; 7804 7805 struct mlx5_ifc_create_flow_table_out_bits { 7806 u8 status[0x8]; 7807 u8 icm_address_63_40[0x18]; 7808 7809 u8 syndrome[0x20]; 7810 7811 u8 icm_address_39_32[0x8]; 7812 u8 table_id[0x18]; 7813 7814 u8 icm_address_31_0[0x20]; 7815 }; 7816 7817 struct mlx5_ifc_create_flow_table_in_bits { 7818 u8 opcode[0x10]; 7819 u8 reserved_at_10[0x10]; 7820 7821 u8 reserved_at_20[0x10]; 7822 u8 op_mod[0x10]; 7823 7824 u8 other_vport[0x1]; 7825 u8 reserved_at_41[0xf]; 7826 u8 vport_number[0x10]; 7827 7828 u8 reserved_at_60[0x20]; 7829 7830 u8 table_type[0x8]; 7831 u8 reserved_at_88[0x18]; 7832 7833 u8 reserved_at_a0[0x20]; 7834 7835 struct mlx5_ifc_flow_table_context_bits flow_table_context; 7836 }; 7837 7838 struct mlx5_ifc_create_flow_group_out_bits { 7839 u8 status[0x8]; 7840 u8 reserved_at_8[0x18]; 7841 7842 u8 syndrome[0x20]; 7843 7844 u8 reserved_at_40[0x8]; 7845 u8 group_id[0x18]; 7846 7847 u8 reserved_at_60[0x20]; 7848 }; 7849 7850 enum { 7851 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 7852 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 7853 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 7854 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3, 7855 }; 7856 7857 struct mlx5_ifc_create_flow_group_in_bits { 7858 u8 opcode[0x10]; 7859 u8 reserved_at_10[0x10]; 7860 7861 u8 reserved_at_20[0x10]; 7862 u8 op_mod[0x10]; 7863 7864 u8 other_vport[0x1]; 7865 u8 reserved_at_41[0xf]; 7866 u8 vport_number[0x10]; 7867 7868 u8 reserved_at_60[0x20]; 7869 7870 u8 table_type[0x8]; 7871 u8 reserved_at_88[0x18]; 7872 7873 u8 reserved_at_a0[0x8]; 7874 u8 table_id[0x18]; 7875 7876 u8 source_eswitch_owner_vhca_id_valid[0x1]; 7877 7878 u8 reserved_at_c1[0x1f]; 7879 7880 u8 start_flow_index[0x20]; 7881 7882 u8 reserved_at_100[0x20]; 7883 7884 u8 end_flow_index[0x20]; 7885 7886 u8 reserved_at_140[0xa0]; 7887 7888 u8 reserved_at_1e0[0x18]; 7889 u8 match_criteria_enable[0x8]; 7890 7891 struct mlx5_ifc_fte_match_param_bits match_criteria; 7892 7893 u8 reserved_at_1200[0xe00]; 7894 }; 7895 7896 struct mlx5_ifc_create_eq_out_bits { 7897 u8 status[0x8]; 7898 u8 reserved_at_8[0x18]; 7899 7900 u8 syndrome[0x20]; 7901 7902 u8 reserved_at_40[0x18]; 7903 u8 eq_number[0x8]; 7904 7905 u8 reserved_at_60[0x20]; 7906 }; 7907 7908 struct mlx5_ifc_create_eq_in_bits { 7909 u8 opcode[0x10]; 7910 u8 uid[0x10]; 7911 7912 u8 reserved_at_20[0x10]; 7913 u8 op_mod[0x10]; 7914 7915 u8 reserved_at_40[0x40]; 7916 7917 struct mlx5_ifc_eqc_bits eq_context_entry; 7918 7919 u8 reserved_at_280[0x40]; 7920 7921 u8 event_bitmask[4][0x40]; 7922 7923 u8 reserved_at_3c0[0x4c0]; 7924 7925 u8 pas[0][0x40]; 7926 }; 7927 7928 struct mlx5_ifc_create_dct_out_bits { 7929 u8 status[0x8]; 7930 u8 reserved_at_8[0x18]; 7931 7932 u8 syndrome[0x20]; 7933 7934 u8 reserved_at_40[0x8]; 7935 u8 dctn[0x18]; 7936 7937 u8 reserved_at_60[0x20]; 7938 }; 7939 7940 struct mlx5_ifc_create_dct_in_bits { 7941 u8 opcode[0x10]; 7942 u8 uid[0x10]; 7943 7944 u8 reserved_at_20[0x10]; 7945 u8 op_mod[0x10]; 7946 7947 u8 reserved_at_40[0x40]; 7948 7949 struct mlx5_ifc_dctc_bits dct_context_entry; 7950 7951 u8 reserved_at_280[0x180]; 7952 }; 7953 7954 struct mlx5_ifc_create_cq_out_bits { 7955 u8 status[0x8]; 7956 u8 reserved_at_8[0x18]; 7957 7958 u8 syndrome[0x20]; 7959 7960 u8 reserved_at_40[0x8]; 7961 u8 cqn[0x18]; 7962 7963 u8 reserved_at_60[0x20]; 7964 }; 7965 7966 struct mlx5_ifc_create_cq_in_bits { 7967 u8 opcode[0x10]; 7968 u8 uid[0x10]; 7969 7970 u8 reserved_at_20[0x10]; 7971 u8 op_mod[0x10]; 7972 7973 u8 reserved_at_40[0x40]; 7974 7975 struct mlx5_ifc_cqc_bits cq_context; 7976 7977 u8 reserved_at_280[0x60]; 7978 7979 u8 cq_umem_valid[0x1]; 7980 u8 reserved_at_2e1[0x59f]; 7981 7982 u8 pas[0][0x40]; 7983 }; 7984 7985 struct mlx5_ifc_config_int_moderation_out_bits { 7986 u8 status[0x8]; 7987 u8 reserved_at_8[0x18]; 7988 7989 u8 syndrome[0x20]; 7990 7991 u8 reserved_at_40[0x4]; 7992 u8 min_delay[0xc]; 7993 u8 int_vector[0x10]; 7994 7995 u8 reserved_at_60[0x20]; 7996 }; 7997 7998 enum { 7999 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0, 8000 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1, 8001 }; 8002 8003 struct mlx5_ifc_config_int_moderation_in_bits { 8004 u8 opcode[0x10]; 8005 u8 reserved_at_10[0x10]; 8006 8007 u8 reserved_at_20[0x10]; 8008 u8 op_mod[0x10]; 8009 8010 u8 reserved_at_40[0x4]; 8011 u8 min_delay[0xc]; 8012 u8 int_vector[0x10]; 8013 8014 u8 reserved_at_60[0x20]; 8015 }; 8016 8017 struct mlx5_ifc_attach_to_mcg_out_bits { 8018 u8 status[0x8]; 8019 u8 reserved_at_8[0x18]; 8020 8021 u8 syndrome[0x20]; 8022 8023 u8 reserved_at_40[0x40]; 8024 }; 8025 8026 struct mlx5_ifc_attach_to_mcg_in_bits { 8027 u8 opcode[0x10]; 8028 u8 uid[0x10]; 8029 8030 u8 reserved_at_20[0x10]; 8031 u8 op_mod[0x10]; 8032 8033 u8 reserved_at_40[0x8]; 8034 u8 qpn[0x18]; 8035 8036 u8 reserved_at_60[0x20]; 8037 8038 u8 multicast_gid[16][0x8]; 8039 }; 8040 8041 struct mlx5_ifc_arm_xrq_out_bits { 8042 u8 status[0x8]; 8043 u8 reserved_at_8[0x18]; 8044 8045 u8 syndrome[0x20]; 8046 8047 u8 reserved_at_40[0x40]; 8048 }; 8049 8050 struct mlx5_ifc_arm_xrq_in_bits { 8051 u8 opcode[0x10]; 8052 u8 reserved_at_10[0x10]; 8053 8054 u8 reserved_at_20[0x10]; 8055 u8 op_mod[0x10]; 8056 8057 u8 reserved_at_40[0x8]; 8058 u8 xrqn[0x18]; 8059 8060 u8 reserved_at_60[0x10]; 8061 u8 lwm[0x10]; 8062 }; 8063 8064 struct mlx5_ifc_arm_xrc_srq_out_bits { 8065 u8 status[0x8]; 8066 u8 reserved_at_8[0x18]; 8067 8068 u8 syndrome[0x20]; 8069 8070 u8 reserved_at_40[0x40]; 8071 }; 8072 8073 enum { 8074 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1, 8075 }; 8076 8077 struct mlx5_ifc_arm_xrc_srq_in_bits { 8078 u8 opcode[0x10]; 8079 u8 uid[0x10]; 8080 8081 u8 reserved_at_20[0x10]; 8082 u8 op_mod[0x10]; 8083 8084 u8 reserved_at_40[0x8]; 8085 u8 xrc_srqn[0x18]; 8086 8087 u8 reserved_at_60[0x10]; 8088 u8 lwm[0x10]; 8089 }; 8090 8091 struct mlx5_ifc_arm_rq_out_bits { 8092 u8 status[0x8]; 8093 u8 reserved_at_8[0x18]; 8094 8095 u8 syndrome[0x20]; 8096 8097 u8 reserved_at_40[0x40]; 8098 }; 8099 8100 enum { 8101 MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1, 8102 MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2, 8103 }; 8104 8105 struct mlx5_ifc_arm_rq_in_bits { 8106 u8 opcode[0x10]; 8107 u8 uid[0x10]; 8108 8109 u8 reserved_at_20[0x10]; 8110 u8 op_mod[0x10]; 8111 8112 u8 reserved_at_40[0x8]; 8113 u8 srq_number[0x18]; 8114 8115 u8 reserved_at_60[0x10]; 8116 u8 lwm[0x10]; 8117 }; 8118 8119 struct mlx5_ifc_arm_dct_out_bits { 8120 u8 status[0x8]; 8121 u8 reserved_at_8[0x18]; 8122 8123 u8 syndrome[0x20]; 8124 8125 u8 reserved_at_40[0x40]; 8126 }; 8127 8128 struct mlx5_ifc_arm_dct_in_bits { 8129 u8 opcode[0x10]; 8130 u8 reserved_at_10[0x10]; 8131 8132 u8 reserved_at_20[0x10]; 8133 u8 op_mod[0x10]; 8134 8135 u8 reserved_at_40[0x8]; 8136 u8 dct_number[0x18]; 8137 8138 u8 reserved_at_60[0x20]; 8139 }; 8140 8141 struct mlx5_ifc_alloc_xrcd_out_bits { 8142 u8 status[0x8]; 8143 u8 reserved_at_8[0x18]; 8144 8145 u8 syndrome[0x20]; 8146 8147 u8 reserved_at_40[0x8]; 8148 u8 xrcd[0x18]; 8149 8150 u8 reserved_at_60[0x20]; 8151 }; 8152 8153 struct mlx5_ifc_alloc_xrcd_in_bits { 8154 u8 opcode[0x10]; 8155 u8 uid[0x10]; 8156 8157 u8 reserved_at_20[0x10]; 8158 u8 op_mod[0x10]; 8159 8160 u8 reserved_at_40[0x40]; 8161 }; 8162 8163 struct mlx5_ifc_alloc_uar_out_bits { 8164 u8 status[0x8]; 8165 u8 reserved_at_8[0x18]; 8166 8167 u8 syndrome[0x20]; 8168 8169 u8 reserved_at_40[0x8]; 8170 u8 uar[0x18]; 8171 8172 u8 reserved_at_60[0x20]; 8173 }; 8174 8175 struct mlx5_ifc_alloc_uar_in_bits { 8176 u8 opcode[0x10]; 8177 u8 reserved_at_10[0x10]; 8178 8179 u8 reserved_at_20[0x10]; 8180 u8 op_mod[0x10]; 8181 8182 u8 reserved_at_40[0x40]; 8183 }; 8184 8185 struct mlx5_ifc_alloc_transport_domain_out_bits { 8186 u8 status[0x8]; 8187 u8 reserved_at_8[0x18]; 8188 8189 u8 syndrome[0x20]; 8190 8191 u8 reserved_at_40[0x8]; 8192 u8 transport_domain[0x18]; 8193 8194 u8 reserved_at_60[0x20]; 8195 }; 8196 8197 struct mlx5_ifc_alloc_transport_domain_in_bits { 8198 u8 opcode[0x10]; 8199 u8 uid[0x10]; 8200 8201 u8 reserved_at_20[0x10]; 8202 u8 op_mod[0x10]; 8203 8204 u8 reserved_at_40[0x40]; 8205 }; 8206 8207 struct mlx5_ifc_alloc_q_counter_out_bits { 8208 u8 status[0x8]; 8209 u8 reserved_at_8[0x18]; 8210 8211 u8 syndrome[0x20]; 8212 8213 u8 reserved_at_40[0x18]; 8214 u8 counter_set_id[0x8]; 8215 8216 u8 reserved_at_60[0x20]; 8217 }; 8218 8219 struct mlx5_ifc_alloc_q_counter_in_bits { 8220 u8 opcode[0x10]; 8221 u8 uid[0x10]; 8222 8223 u8 reserved_at_20[0x10]; 8224 u8 op_mod[0x10]; 8225 8226 u8 reserved_at_40[0x40]; 8227 }; 8228 8229 struct mlx5_ifc_alloc_pd_out_bits { 8230 u8 status[0x8]; 8231 u8 reserved_at_8[0x18]; 8232 8233 u8 syndrome[0x20]; 8234 8235 u8 reserved_at_40[0x8]; 8236 u8 pd[0x18]; 8237 8238 u8 reserved_at_60[0x20]; 8239 }; 8240 8241 struct mlx5_ifc_alloc_pd_in_bits { 8242 u8 opcode[0x10]; 8243 u8 uid[0x10]; 8244 8245 u8 reserved_at_20[0x10]; 8246 u8 op_mod[0x10]; 8247 8248 u8 reserved_at_40[0x40]; 8249 }; 8250 8251 struct mlx5_ifc_alloc_flow_counter_out_bits { 8252 u8 status[0x8]; 8253 u8 reserved_at_8[0x18]; 8254 8255 u8 syndrome[0x20]; 8256 8257 u8 flow_counter_id[0x20]; 8258 8259 u8 reserved_at_60[0x20]; 8260 }; 8261 8262 struct mlx5_ifc_alloc_flow_counter_in_bits { 8263 u8 opcode[0x10]; 8264 u8 reserved_at_10[0x10]; 8265 8266 u8 reserved_at_20[0x10]; 8267 u8 op_mod[0x10]; 8268 8269 u8 reserved_at_40[0x38]; 8270 u8 flow_counter_bulk[0x8]; 8271 }; 8272 8273 struct mlx5_ifc_add_vxlan_udp_dport_out_bits { 8274 u8 status[0x8]; 8275 u8 reserved_at_8[0x18]; 8276 8277 u8 syndrome[0x20]; 8278 8279 u8 reserved_at_40[0x40]; 8280 }; 8281 8282 struct mlx5_ifc_add_vxlan_udp_dport_in_bits { 8283 u8 opcode[0x10]; 8284 u8 reserved_at_10[0x10]; 8285 8286 u8 reserved_at_20[0x10]; 8287 u8 op_mod[0x10]; 8288 8289 u8 reserved_at_40[0x20]; 8290 8291 u8 reserved_at_60[0x10]; 8292 u8 vxlan_udp_port[0x10]; 8293 }; 8294 8295 struct mlx5_ifc_set_pp_rate_limit_out_bits { 8296 u8 status[0x8]; 8297 u8 reserved_at_8[0x18]; 8298 8299 u8 syndrome[0x20]; 8300 8301 u8 reserved_at_40[0x40]; 8302 }; 8303 8304 struct mlx5_ifc_set_pp_rate_limit_context_bits { 8305 u8 rate_limit[0x20]; 8306 8307 u8 burst_upper_bound[0x20]; 8308 8309 u8 reserved_at_40[0x10]; 8310 u8 typical_packet_size[0x10]; 8311 8312 u8 reserved_at_60[0x120]; 8313 }; 8314 8315 struct mlx5_ifc_set_pp_rate_limit_in_bits { 8316 u8 opcode[0x10]; 8317 u8 uid[0x10]; 8318 8319 u8 reserved_at_20[0x10]; 8320 u8 op_mod[0x10]; 8321 8322 u8 reserved_at_40[0x10]; 8323 u8 rate_limit_index[0x10]; 8324 8325 u8 reserved_at_60[0x20]; 8326 8327 struct mlx5_ifc_set_pp_rate_limit_context_bits ctx; 8328 }; 8329 8330 struct mlx5_ifc_access_register_out_bits { 8331 u8 status[0x8]; 8332 u8 reserved_at_8[0x18]; 8333 8334 u8 syndrome[0x20]; 8335 8336 u8 reserved_at_40[0x40]; 8337 8338 u8 register_data[0][0x20]; 8339 }; 8340 8341 enum { 8342 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0, 8343 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1, 8344 }; 8345 8346 struct mlx5_ifc_access_register_in_bits { 8347 u8 opcode[0x10]; 8348 u8 reserved_at_10[0x10]; 8349 8350 u8 reserved_at_20[0x10]; 8351 u8 op_mod[0x10]; 8352 8353 u8 reserved_at_40[0x10]; 8354 u8 register_id[0x10]; 8355 8356 u8 argument[0x20]; 8357 8358 u8 register_data[0][0x20]; 8359 }; 8360 8361 struct mlx5_ifc_sltp_reg_bits { 8362 u8 status[0x4]; 8363 u8 version[0x4]; 8364 u8 local_port[0x8]; 8365 u8 pnat[0x2]; 8366 u8 reserved_at_12[0x2]; 8367 u8 lane[0x4]; 8368 u8 reserved_at_18[0x8]; 8369 8370 u8 reserved_at_20[0x20]; 8371 8372 u8 reserved_at_40[0x7]; 8373 u8 polarity[0x1]; 8374 u8 ob_tap0[0x8]; 8375 u8 ob_tap1[0x8]; 8376 u8 ob_tap2[0x8]; 8377 8378 u8 reserved_at_60[0xc]; 8379 u8 ob_preemp_mode[0x4]; 8380 u8 ob_reg[0x8]; 8381 u8 ob_bias[0x8]; 8382 8383 u8 reserved_at_80[0x20]; 8384 }; 8385 8386 struct mlx5_ifc_slrg_reg_bits { 8387 u8 status[0x4]; 8388 u8 version[0x4]; 8389 u8 local_port[0x8]; 8390 u8 pnat[0x2]; 8391 u8 reserved_at_12[0x2]; 8392 u8 lane[0x4]; 8393 u8 reserved_at_18[0x8]; 8394 8395 u8 time_to_link_up[0x10]; 8396 u8 reserved_at_30[0xc]; 8397 u8 grade_lane_speed[0x4]; 8398 8399 u8 grade_version[0x8]; 8400 u8 grade[0x18]; 8401 8402 u8 reserved_at_60[0x4]; 8403 u8 height_grade_type[0x4]; 8404 u8 height_grade[0x18]; 8405 8406 u8 height_dz[0x10]; 8407 u8 height_dv[0x10]; 8408 8409 u8 reserved_at_a0[0x10]; 8410 u8 height_sigma[0x10]; 8411 8412 u8 reserved_at_c0[0x20]; 8413 8414 u8 reserved_at_e0[0x4]; 8415 u8 phase_grade_type[0x4]; 8416 u8 phase_grade[0x18]; 8417 8418 u8 reserved_at_100[0x8]; 8419 u8 phase_eo_pos[0x8]; 8420 u8 reserved_at_110[0x8]; 8421 u8 phase_eo_neg[0x8]; 8422 8423 u8 ffe_set_tested[0x10]; 8424 u8 test_errors_per_lane[0x10]; 8425 }; 8426 8427 struct mlx5_ifc_pvlc_reg_bits { 8428 u8 reserved_at_0[0x8]; 8429 u8 local_port[0x8]; 8430 u8 reserved_at_10[0x10]; 8431 8432 u8 reserved_at_20[0x1c]; 8433 u8 vl_hw_cap[0x4]; 8434 8435 u8 reserved_at_40[0x1c]; 8436 u8 vl_admin[0x4]; 8437 8438 u8 reserved_at_60[0x1c]; 8439 u8 vl_operational[0x4]; 8440 }; 8441 8442 struct mlx5_ifc_pude_reg_bits { 8443 u8 swid[0x8]; 8444 u8 local_port[0x8]; 8445 u8 reserved_at_10[0x4]; 8446 u8 admin_status[0x4]; 8447 u8 reserved_at_18[0x4]; 8448 u8 oper_status[0x4]; 8449 8450 u8 reserved_at_20[0x60]; 8451 }; 8452 8453 struct mlx5_ifc_ptys_reg_bits { 8454 u8 reserved_at_0[0x1]; 8455 u8 an_disable_admin[0x1]; 8456 u8 an_disable_cap[0x1]; 8457 u8 reserved_at_3[0x5]; 8458 u8 local_port[0x8]; 8459 u8 reserved_at_10[0xd]; 8460 u8 proto_mask[0x3]; 8461 8462 u8 an_status[0x4]; 8463 u8 reserved_at_24[0xc]; 8464 u8 data_rate_oper[0x10]; 8465 8466 u8 ext_eth_proto_capability[0x20]; 8467 8468 u8 eth_proto_capability[0x20]; 8469 8470 u8 ib_link_width_capability[0x10]; 8471 u8 ib_proto_capability[0x10]; 8472 8473 u8 ext_eth_proto_admin[0x20]; 8474 8475 u8 eth_proto_admin[0x20]; 8476 8477 u8 ib_link_width_admin[0x10]; 8478 u8 ib_proto_admin[0x10]; 8479 8480 u8 ext_eth_proto_oper[0x20]; 8481 8482 u8 eth_proto_oper[0x20]; 8483 8484 u8 ib_link_width_oper[0x10]; 8485 u8 ib_proto_oper[0x10]; 8486 8487 u8 reserved_at_160[0x1c]; 8488 u8 connector_type[0x4]; 8489 8490 u8 eth_proto_lp_advertise[0x20]; 8491 8492 u8 reserved_at_1a0[0x60]; 8493 }; 8494 8495 struct mlx5_ifc_mlcr_reg_bits { 8496 u8 reserved_at_0[0x8]; 8497 u8 local_port[0x8]; 8498 u8 reserved_at_10[0x20]; 8499 8500 u8 beacon_duration[0x10]; 8501 u8 reserved_at_40[0x10]; 8502 8503 u8 beacon_remain[0x10]; 8504 }; 8505 8506 struct mlx5_ifc_ptas_reg_bits { 8507 u8 reserved_at_0[0x20]; 8508 8509 u8 algorithm_options[0x10]; 8510 u8 reserved_at_30[0x4]; 8511 u8 repetitions_mode[0x4]; 8512 u8 num_of_repetitions[0x8]; 8513 8514 u8 grade_version[0x8]; 8515 u8 height_grade_type[0x4]; 8516 u8 phase_grade_type[0x4]; 8517 u8 height_grade_weight[0x8]; 8518 u8 phase_grade_weight[0x8]; 8519 8520 u8 gisim_measure_bits[0x10]; 8521 u8 adaptive_tap_measure_bits[0x10]; 8522 8523 u8 ber_bath_high_error_threshold[0x10]; 8524 u8 ber_bath_mid_error_threshold[0x10]; 8525 8526 u8 ber_bath_low_error_threshold[0x10]; 8527 u8 one_ratio_high_threshold[0x10]; 8528 8529 u8 one_ratio_high_mid_threshold[0x10]; 8530 u8 one_ratio_low_mid_threshold[0x10]; 8531 8532 u8 one_ratio_low_threshold[0x10]; 8533 u8 ndeo_error_threshold[0x10]; 8534 8535 u8 mixer_offset_step_size[0x10]; 8536 u8 reserved_at_110[0x8]; 8537 u8 mix90_phase_for_voltage_bath[0x8]; 8538 8539 u8 mixer_offset_start[0x10]; 8540 u8 mixer_offset_end[0x10]; 8541 8542 u8 reserved_at_140[0x15]; 8543 u8 ber_test_time[0xb]; 8544 }; 8545 8546 struct mlx5_ifc_pspa_reg_bits { 8547 u8 swid[0x8]; 8548 u8 local_port[0x8]; 8549 u8 sub_port[0x8]; 8550 u8 reserved_at_18[0x8]; 8551 8552 u8 reserved_at_20[0x20]; 8553 }; 8554 8555 struct mlx5_ifc_pqdr_reg_bits { 8556 u8 reserved_at_0[0x8]; 8557 u8 local_port[0x8]; 8558 u8 reserved_at_10[0x5]; 8559 u8 prio[0x3]; 8560 u8 reserved_at_18[0x6]; 8561 u8 mode[0x2]; 8562 8563 u8 reserved_at_20[0x20]; 8564 8565 u8 reserved_at_40[0x10]; 8566 u8 min_threshold[0x10]; 8567 8568 u8 reserved_at_60[0x10]; 8569 u8 max_threshold[0x10]; 8570 8571 u8 reserved_at_80[0x10]; 8572 u8 mark_probability_denominator[0x10]; 8573 8574 u8 reserved_at_a0[0x60]; 8575 }; 8576 8577 struct mlx5_ifc_ppsc_reg_bits { 8578 u8 reserved_at_0[0x8]; 8579 u8 local_port[0x8]; 8580 u8 reserved_at_10[0x10]; 8581 8582 u8 reserved_at_20[0x60]; 8583 8584 u8 reserved_at_80[0x1c]; 8585 u8 wrps_admin[0x4]; 8586 8587 u8 reserved_at_a0[0x1c]; 8588 u8 wrps_status[0x4]; 8589 8590 u8 reserved_at_c0[0x8]; 8591 u8 up_threshold[0x8]; 8592 u8 reserved_at_d0[0x8]; 8593 u8 down_threshold[0x8]; 8594 8595 u8 reserved_at_e0[0x20]; 8596 8597 u8 reserved_at_100[0x1c]; 8598 u8 srps_admin[0x4]; 8599 8600 u8 reserved_at_120[0x1c]; 8601 u8 srps_status[0x4]; 8602 8603 u8 reserved_at_140[0x40]; 8604 }; 8605 8606 struct mlx5_ifc_pplr_reg_bits { 8607 u8 reserved_at_0[0x8]; 8608 u8 local_port[0x8]; 8609 u8 reserved_at_10[0x10]; 8610 8611 u8 reserved_at_20[0x8]; 8612 u8 lb_cap[0x8]; 8613 u8 reserved_at_30[0x8]; 8614 u8 lb_en[0x8]; 8615 }; 8616 8617 struct mlx5_ifc_pplm_reg_bits { 8618 u8 reserved_at_0[0x8]; 8619 u8 local_port[0x8]; 8620 u8 reserved_at_10[0x10]; 8621 8622 u8 reserved_at_20[0x20]; 8623 8624 u8 port_profile_mode[0x8]; 8625 u8 static_port_profile[0x8]; 8626 u8 active_port_profile[0x8]; 8627 u8 reserved_at_58[0x8]; 8628 8629 u8 retransmission_active[0x8]; 8630 u8 fec_mode_active[0x18]; 8631 8632 u8 rs_fec_correction_bypass_cap[0x4]; 8633 u8 reserved_at_84[0x8]; 8634 u8 fec_override_cap_56g[0x4]; 8635 u8 fec_override_cap_100g[0x4]; 8636 u8 fec_override_cap_50g[0x4]; 8637 u8 fec_override_cap_25g[0x4]; 8638 u8 fec_override_cap_10g_40g[0x4]; 8639 8640 u8 rs_fec_correction_bypass_admin[0x4]; 8641 u8 reserved_at_a4[0x8]; 8642 u8 fec_override_admin_56g[0x4]; 8643 u8 fec_override_admin_100g[0x4]; 8644 u8 fec_override_admin_50g[0x4]; 8645 u8 fec_override_admin_25g[0x4]; 8646 u8 fec_override_admin_10g_40g[0x4]; 8647 8648 u8 fec_override_cap_400g_8x[0x10]; 8649 u8 fec_override_cap_200g_4x[0x10]; 8650 8651 u8 fec_override_cap_100g_2x[0x10]; 8652 u8 fec_override_cap_50g_1x[0x10]; 8653 8654 u8 fec_override_admin_400g_8x[0x10]; 8655 u8 fec_override_admin_200g_4x[0x10]; 8656 8657 u8 fec_override_admin_100g_2x[0x10]; 8658 u8 fec_override_admin_50g_1x[0x10]; 8659 }; 8660 8661 struct mlx5_ifc_ppcnt_reg_bits { 8662 u8 swid[0x8]; 8663 u8 local_port[0x8]; 8664 u8 pnat[0x2]; 8665 u8 reserved_at_12[0x8]; 8666 u8 grp[0x6]; 8667 8668 u8 clr[0x1]; 8669 u8 reserved_at_21[0x1c]; 8670 u8 prio_tc[0x3]; 8671 8672 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set; 8673 }; 8674 8675 struct mlx5_ifc_mpein_reg_bits { 8676 u8 reserved_at_0[0x2]; 8677 u8 depth[0x6]; 8678 u8 pcie_index[0x8]; 8679 u8 node[0x8]; 8680 u8 reserved_at_18[0x8]; 8681 8682 u8 capability_mask[0x20]; 8683 8684 u8 reserved_at_40[0x8]; 8685 u8 link_width_enabled[0x8]; 8686 u8 link_speed_enabled[0x10]; 8687 8688 u8 lane0_physical_position[0x8]; 8689 u8 link_width_active[0x8]; 8690 u8 link_speed_active[0x10]; 8691 8692 u8 num_of_pfs[0x10]; 8693 u8 num_of_vfs[0x10]; 8694 8695 u8 bdf0[0x10]; 8696 u8 reserved_at_b0[0x10]; 8697 8698 u8 max_read_request_size[0x4]; 8699 u8 max_payload_size[0x4]; 8700 u8 reserved_at_c8[0x5]; 8701 u8 pwr_status[0x3]; 8702 u8 port_type[0x4]; 8703 u8 reserved_at_d4[0xb]; 8704 u8 lane_reversal[0x1]; 8705 8706 u8 reserved_at_e0[0x14]; 8707 u8 pci_power[0xc]; 8708 8709 u8 reserved_at_100[0x20]; 8710 8711 u8 device_status[0x10]; 8712 u8 port_state[0x8]; 8713 u8 reserved_at_138[0x8]; 8714 8715 u8 reserved_at_140[0x10]; 8716 u8 receiver_detect_result[0x10]; 8717 8718 u8 reserved_at_160[0x20]; 8719 }; 8720 8721 struct mlx5_ifc_mpcnt_reg_bits { 8722 u8 reserved_at_0[0x8]; 8723 u8 pcie_index[0x8]; 8724 u8 reserved_at_10[0xa]; 8725 u8 grp[0x6]; 8726 8727 u8 clr[0x1]; 8728 u8 reserved_at_21[0x1f]; 8729 8730 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set; 8731 }; 8732 8733 struct mlx5_ifc_ppad_reg_bits { 8734 u8 reserved_at_0[0x3]; 8735 u8 single_mac[0x1]; 8736 u8 reserved_at_4[0x4]; 8737 u8 local_port[0x8]; 8738 u8 mac_47_32[0x10]; 8739 8740 u8 mac_31_0[0x20]; 8741 8742 u8 reserved_at_40[0x40]; 8743 }; 8744 8745 struct mlx5_ifc_pmtu_reg_bits { 8746 u8 reserved_at_0[0x8]; 8747 u8 local_port[0x8]; 8748 u8 reserved_at_10[0x10]; 8749 8750 u8 max_mtu[0x10]; 8751 u8 reserved_at_30[0x10]; 8752 8753 u8 admin_mtu[0x10]; 8754 u8 reserved_at_50[0x10]; 8755 8756 u8 oper_mtu[0x10]; 8757 u8 reserved_at_70[0x10]; 8758 }; 8759 8760 struct mlx5_ifc_pmpr_reg_bits { 8761 u8 reserved_at_0[0x8]; 8762 u8 module[0x8]; 8763 u8 reserved_at_10[0x10]; 8764 8765 u8 reserved_at_20[0x18]; 8766 u8 attenuation_5g[0x8]; 8767 8768 u8 reserved_at_40[0x18]; 8769 u8 attenuation_7g[0x8]; 8770 8771 u8 reserved_at_60[0x18]; 8772 u8 attenuation_12g[0x8]; 8773 }; 8774 8775 struct mlx5_ifc_pmpe_reg_bits { 8776 u8 reserved_at_0[0x8]; 8777 u8 module[0x8]; 8778 u8 reserved_at_10[0xc]; 8779 u8 module_status[0x4]; 8780 8781 u8 reserved_at_20[0x60]; 8782 }; 8783 8784 struct mlx5_ifc_pmpc_reg_bits { 8785 u8 module_state_updated[32][0x8]; 8786 }; 8787 8788 struct mlx5_ifc_pmlpn_reg_bits { 8789 u8 reserved_at_0[0x4]; 8790 u8 mlpn_status[0x4]; 8791 u8 local_port[0x8]; 8792 u8 reserved_at_10[0x10]; 8793 8794 u8 e[0x1]; 8795 u8 reserved_at_21[0x1f]; 8796 }; 8797 8798 struct mlx5_ifc_pmlp_reg_bits { 8799 u8 rxtx[0x1]; 8800 u8 reserved_at_1[0x7]; 8801 u8 local_port[0x8]; 8802 u8 reserved_at_10[0x8]; 8803 u8 width[0x8]; 8804 8805 u8 lane0_module_mapping[0x20]; 8806 8807 u8 lane1_module_mapping[0x20]; 8808 8809 u8 lane2_module_mapping[0x20]; 8810 8811 u8 lane3_module_mapping[0x20]; 8812 8813 u8 reserved_at_a0[0x160]; 8814 }; 8815 8816 struct mlx5_ifc_pmaos_reg_bits { 8817 u8 reserved_at_0[0x8]; 8818 u8 module[0x8]; 8819 u8 reserved_at_10[0x4]; 8820 u8 admin_status[0x4]; 8821 u8 reserved_at_18[0x4]; 8822 u8 oper_status[0x4]; 8823 8824 u8 ase[0x1]; 8825 u8 ee[0x1]; 8826 u8 reserved_at_22[0x1c]; 8827 u8 e[0x2]; 8828 8829 u8 reserved_at_40[0x40]; 8830 }; 8831 8832 struct mlx5_ifc_plpc_reg_bits { 8833 u8 reserved_at_0[0x4]; 8834 u8 profile_id[0xc]; 8835 u8 reserved_at_10[0x4]; 8836 u8 proto_mask[0x4]; 8837 u8 reserved_at_18[0x8]; 8838 8839 u8 reserved_at_20[0x10]; 8840 u8 lane_speed[0x10]; 8841 8842 u8 reserved_at_40[0x17]; 8843 u8 lpbf[0x1]; 8844 u8 fec_mode_policy[0x8]; 8845 8846 u8 retransmission_capability[0x8]; 8847 u8 fec_mode_capability[0x18]; 8848 8849 u8 retransmission_support_admin[0x8]; 8850 u8 fec_mode_support_admin[0x18]; 8851 8852 u8 retransmission_request_admin[0x8]; 8853 u8 fec_mode_request_admin[0x18]; 8854 8855 u8 reserved_at_c0[0x80]; 8856 }; 8857 8858 struct mlx5_ifc_plib_reg_bits { 8859 u8 reserved_at_0[0x8]; 8860 u8 local_port[0x8]; 8861 u8 reserved_at_10[0x8]; 8862 u8 ib_port[0x8]; 8863 8864 u8 reserved_at_20[0x60]; 8865 }; 8866 8867 struct mlx5_ifc_plbf_reg_bits { 8868 u8 reserved_at_0[0x8]; 8869 u8 local_port[0x8]; 8870 u8 reserved_at_10[0xd]; 8871 u8 lbf_mode[0x3]; 8872 8873 u8 reserved_at_20[0x20]; 8874 }; 8875 8876 struct mlx5_ifc_pipg_reg_bits { 8877 u8 reserved_at_0[0x8]; 8878 u8 local_port[0x8]; 8879 u8 reserved_at_10[0x10]; 8880 8881 u8 dic[0x1]; 8882 u8 reserved_at_21[0x19]; 8883 u8 ipg[0x4]; 8884 u8 reserved_at_3e[0x2]; 8885 }; 8886 8887 struct mlx5_ifc_pifr_reg_bits { 8888 u8 reserved_at_0[0x8]; 8889 u8 local_port[0x8]; 8890 u8 reserved_at_10[0x10]; 8891 8892 u8 reserved_at_20[0xe0]; 8893 8894 u8 port_filter[8][0x20]; 8895 8896 u8 port_filter_update_en[8][0x20]; 8897 }; 8898 8899 struct mlx5_ifc_pfcc_reg_bits { 8900 u8 reserved_at_0[0x8]; 8901 u8 local_port[0x8]; 8902 u8 reserved_at_10[0xb]; 8903 u8 ppan_mask_n[0x1]; 8904 u8 minor_stall_mask[0x1]; 8905 u8 critical_stall_mask[0x1]; 8906 u8 reserved_at_1e[0x2]; 8907 8908 u8 ppan[0x4]; 8909 u8 reserved_at_24[0x4]; 8910 u8 prio_mask_tx[0x8]; 8911 u8 reserved_at_30[0x8]; 8912 u8 prio_mask_rx[0x8]; 8913 8914 u8 pptx[0x1]; 8915 u8 aptx[0x1]; 8916 u8 pptx_mask_n[0x1]; 8917 u8 reserved_at_43[0x5]; 8918 u8 pfctx[0x8]; 8919 u8 reserved_at_50[0x10]; 8920 8921 u8 pprx[0x1]; 8922 u8 aprx[0x1]; 8923 u8 pprx_mask_n[0x1]; 8924 u8 reserved_at_63[0x5]; 8925 u8 pfcrx[0x8]; 8926 u8 reserved_at_70[0x10]; 8927 8928 u8 device_stall_minor_watermark[0x10]; 8929 u8 device_stall_critical_watermark[0x10]; 8930 8931 u8 reserved_at_a0[0x60]; 8932 }; 8933 8934 struct mlx5_ifc_pelc_reg_bits { 8935 u8 op[0x4]; 8936 u8 reserved_at_4[0x4]; 8937 u8 local_port[0x8]; 8938 u8 reserved_at_10[0x10]; 8939 8940 u8 op_admin[0x8]; 8941 u8 op_capability[0x8]; 8942 u8 op_request[0x8]; 8943 u8 op_active[0x8]; 8944 8945 u8 admin[0x40]; 8946 8947 u8 capability[0x40]; 8948 8949 u8 request[0x40]; 8950 8951 u8 active[0x40]; 8952 8953 u8 reserved_at_140[0x80]; 8954 }; 8955 8956 struct mlx5_ifc_peir_reg_bits { 8957 u8 reserved_at_0[0x8]; 8958 u8 local_port[0x8]; 8959 u8 reserved_at_10[0x10]; 8960 8961 u8 reserved_at_20[0xc]; 8962 u8 error_count[0x4]; 8963 u8 reserved_at_30[0x10]; 8964 8965 u8 reserved_at_40[0xc]; 8966 u8 lane[0x4]; 8967 u8 reserved_at_50[0x8]; 8968 u8 error_type[0x8]; 8969 }; 8970 8971 struct mlx5_ifc_mpegc_reg_bits { 8972 u8 reserved_at_0[0x30]; 8973 u8 field_select[0x10]; 8974 8975 u8 tx_overflow_sense[0x1]; 8976 u8 mark_cqe[0x1]; 8977 u8 mark_cnp[0x1]; 8978 u8 reserved_at_43[0x1b]; 8979 u8 tx_lossy_overflow_oper[0x2]; 8980 8981 u8 reserved_at_60[0x100]; 8982 }; 8983 8984 struct mlx5_ifc_pcam_enhanced_features_bits { 8985 u8 reserved_at_0[0x68]; 8986 u8 fec_50G_per_lane_in_pplm[0x1]; 8987 u8 reserved_at_69[0x4]; 8988 u8 rx_icrc_encapsulated_counter[0x1]; 8989 u8 reserved_at_6e[0x4]; 8990 u8 ptys_extended_ethernet[0x1]; 8991 u8 reserved_at_73[0x3]; 8992 u8 pfcc_mask[0x1]; 8993 u8 reserved_at_77[0x3]; 8994 u8 per_lane_error_counters[0x1]; 8995 u8 rx_buffer_fullness_counters[0x1]; 8996 u8 ptys_connector_type[0x1]; 8997 u8 reserved_at_7d[0x1]; 8998 u8 ppcnt_discard_group[0x1]; 8999 u8 ppcnt_statistical_group[0x1]; 9000 }; 9001 9002 struct mlx5_ifc_pcam_regs_5000_to_507f_bits { 9003 u8 port_access_reg_cap_mask_127_to_96[0x20]; 9004 u8 port_access_reg_cap_mask_95_to_64[0x20]; 9005 9006 u8 port_access_reg_cap_mask_63_to_36[0x1c]; 9007 u8 pplm[0x1]; 9008 u8 port_access_reg_cap_mask_34_to_32[0x3]; 9009 9010 u8 port_access_reg_cap_mask_31_to_13[0x13]; 9011 u8 pbmc[0x1]; 9012 u8 pptb[0x1]; 9013 u8 port_access_reg_cap_mask_10_to_09[0x2]; 9014 u8 ppcnt[0x1]; 9015 u8 port_access_reg_cap_mask_07_to_00[0x8]; 9016 }; 9017 9018 struct mlx5_ifc_pcam_reg_bits { 9019 u8 reserved_at_0[0x8]; 9020 u8 feature_group[0x8]; 9021 u8 reserved_at_10[0x8]; 9022 u8 access_reg_group[0x8]; 9023 9024 u8 reserved_at_20[0x20]; 9025 9026 union { 9027 struct mlx5_ifc_pcam_regs_5000_to_507f_bits regs_5000_to_507f; 9028 u8 reserved_at_0[0x80]; 9029 } port_access_reg_cap_mask; 9030 9031 u8 reserved_at_c0[0x80]; 9032 9033 union { 9034 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features; 9035 u8 reserved_at_0[0x80]; 9036 } feature_cap_mask; 9037 9038 u8 reserved_at_1c0[0xc0]; 9039 }; 9040 9041 struct mlx5_ifc_mcam_enhanced_features_bits { 9042 u8 reserved_at_0[0x6e]; 9043 u8 pci_status_and_power[0x1]; 9044 u8 reserved_at_6f[0x5]; 9045 u8 mark_tx_action_cnp[0x1]; 9046 u8 mark_tx_action_cqe[0x1]; 9047 u8 dynamic_tx_overflow[0x1]; 9048 u8 reserved_at_77[0x4]; 9049 u8 pcie_outbound_stalled[0x1]; 9050 u8 tx_overflow_buffer_pkt[0x1]; 9051 u8 mtpps_enh_out_per_adj[0x1]; 9052 u8 mtpps_fs[0x1]; 9053 u8 pcie_performance_group[0x1]; 9054 }; 9055 9056 struct mlx5_ifc_mcam_access_reg_bits { 9057 u8 reserved_at_0[0x1c]; 9058 u8 mcda[0x1]; 9059 u8 mcc[0x1]; 9060 u8 mcqi[0x1]; 9061 u8 mcqs[0x1]; 9062 9063 u8 regs_95_to_87[0x9]; 9064 u8 mpegc[0x1]; 9065 u8 regs_85_to_68[0x12]; 9066 u8 tracer_registers[0x4]; 9067 9068 u8 regs_63_to_32[0x20]; 9069 u8 regs_31_to_0[0x20]; 9070 }; 9071 9072 struct mlx5_ifc_mcam_access_reg_bits1 { 9073 u8 regs_127_to_96[0x20]; 9074 9075 u8 regs_95_to_64[0x20]; 9076 9077 u8 regs_63_to_32[0x20]; 9078 9079 u8 regs_31_to_0[0x20]; 9080 }; 9081 9082 struct mlx5_ifc_mcam_access_reg_bits2 { 9083 u8 regs_127_to_99[0x1d]; 9084 u8 mirc[0x1]; 9085 u8 regs_97_to_96[0x2]; 9086 9087 u8 regs_95_to_64[0x20]; 9088 9089 u8 regs_63_to_32[0x20]; 9090 9091 u8 regs_31_to_0[0x20]; 9092 }; 9093 9094 struct mlx5_ifc_mcam_reg_bits { 9095 u8 reserved_at_0[0x8]; 9096 u8 feature_group[0x8]; 9097 u8 reserved_at_10[0x8]; 9098 u8 access_reg_group[0x8]; 9099 9100 u8 reserved_at_20[0x20]; 9101 9102 union { 9103 struct mlx5_ifc_mcam_access_reg_bits access_regs; 9104 struct mlx5_ifc_mcam_access_reg_bits1 access_regs1; 9105 struct mlx5_ifc_mcam_access_reg_bits2 access_regs2; 9106 u8 reserved_at_0[0x80]; 9107 } mng_access_reg_cap_mask; 9108 9109 u8 reserved_at_c0[0x80]; 9110 9111 union { 9112 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features; 9113 u8 reserved_at_0[0x80]; 9114 } mng_feature_cap_mask; 9115 9116 u8 reserved_at_1c0[0x80]; 9117 }; 9118 9119 struct mlx5_ifc_qcam_access_reg_cap_mask { 9120 u8 qcam_access_reg_cap_mask_127_to_20[0x6C]; 9121 u8 qpdpm[0x1]; 9122 u8 qcam_access_reg_cap_mask_18_to_4[0x0F]; 9123 u8 qdpm[0x1]; 9124 u8 qpts[0x1]; 9125 u8 qcap[0x1]; 9126 u8 qcam_access_reg_cap_mask_0[0x1]; 9127 }; 9128 9129 struct mlx5_ifc_qcam_qos_feature_cap_mask { 9130 u8 qcam_qos_feature_cap_mask_127_to_1[0x7F]; 9131 u8 qpts_trust_both[0x1]; 9132 }; 9133 9134 struct mlx5_ifc_qcam_reg_bits { 9135 u8 reserved_at_0[0x8]; 9136 u8 feature_group[0x8]; 9137 u8 reserved_at_10[0x8]; 9138 u8 access_reg_group[0x8]; 9139 u8 reserved_at_20[0x20]; 9140 9141 union { 9142 struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap; 9143 u8 reserved_at_0[0x80]; 9144 } qos_access_reg_cap_mask; 9145 9146 u8 reserved_at_c0[0x80]; 9147 9148 union { 9149 struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap; 9150 u8 reserved_at_0[0x80]; 9151 } qos_feature_cap_mask; 9152 9153 u8 reserved_at_1c0[0x80]; 9154 }; 9155 9156 struct mlx5_ifc_core_dump_reg_bits { 9157 u8 reserved_at_0[0x18]; 9158 u8 core_dump_type[0x8]; 9159 9160 u8 reserved_at_20[0x30]; 9161 u8 vhca_id[0x10]; 9162 9163 u8 reserved_at_60[0x8]; 9164 u8 qpn[0x18]; 9165 u8 reserved_at_80[0x180]; 9166 }; 9167 9168 struct mlx5_ifc_pcap_reg_bits { 9169 u8 reserved_at_0[0x8]; 9170 u8 local_port[0x8]; 9171 u8 reserved_at_10[0x10]; 9172 9173 u8 port_capability_mask[4][0x20]; 9174 }; 9175 9176 struct mlx5_ifc_paos_reg_bits { 9177 u8 swid[0x8]; 9178 u8 local_port[0x8]; 9179 u8 reserved_at_10[0x4]; 9180 u8 admin_status[0x4]; 9181 u8 reserved_at_18[0x4]; 9182 u8 oper_status[0x4]; 9183 9184 u8 ase[0x1]; 9185 u8 ee[0x1]; 9186 u8 reserved_at_22[0x1c]; 9187 u8 e[0x2]; 9188 9189 u8 reserved_at_40[0x40]; 9190 }; 9191 9192 struct mlx5_ifc_pamp_reg_bits { 9193 u8 reserved_at_0[0x8]; 9194 u8 opamp_group[0x8]; 9195 u8 reserved_at_10[0xc]; 9196 u8 opamp_group_type[0x4]; 9197 9198 u8 start_index[0x10]; 9199 u8 reserved_at_30[0x4]; 9200 u8 num_of_indices[0xc]; 9201 9202 u8 index_data[18][0x10]; 9203 }; 9204 9205 struct mlx5_ifc_pcmr_reg_bits { 9206 u8 reserved_at_0[0x8]; 9207 u8 local_port[0x8]; 9208 u8 reserved_at_10[0x10]; 9209 u8 entropy_force_cap[0x1]; 9210 u8 entropy_calc_cap[0x1]; 9211 u8 entropy_gre_calc_cap[0x1]; 9212 u8 reserved_at_23[0x1b]; 9213 u8 fcs_cap[0x1]; 9214 u8 reserved_at_3f[0x1]; 9215 u8 entropy_force[0x1]; 9216 u8 entropy_calc[0x1]; 9217 u8 entropy_gre_calc[0x1]; 9218 u8 reserved_at_43[0x1b]; 9219 u8 fcs_chk[0x1]; 9220 u8 reserved_at_5f[0x1]; 9221 }; 9222 9223 struct mlx5_ifc_lane_2_module_mapping_bits { 9224 u8 reserved_at_0[0x6]; 9225 u8 rx_lane[0x2]; 9226 u8 reserved_at_8[0x6]; 9227 u8 tx_lane[0x2]; 9228 u8 reserved_at_10[0x8]; 9229 u8 module[0x8]; 9230 }; 9231 9232 struct mlx5_ifc_bufferx_reg_bits { 9233 u8 reserved_at_0[0x6]; 9234 u8 lossy[0x1]; 9235 u8 epsb[0x1]; 9236 u8 reserved_at_8[0xc]; 9237 u8 size[0xc]; 9238 9239 u8 xoff_threshold[0x10]; 9240 u8 xon_threshold[0x10]; 9241 }; 9242 9243 struct mlx5_ifc_set_node_in_bits { 9244 u8 node_description[64][0x8]; 9245 }; 9246 9247 struct mlx5_ifc_register_power_settings_bits { 9248 u8 reserved_at_0[0x18]; 9249 u8 power_settings_level[0x8]; 9250 9251 u8 reserved_at_20[0x60]; 9252 }; 9253 9254 struct mlx5_ifc_register_host_endianness_bits { 9255 u8 he[0x1]; 9256 u8 reserved_at_1[0x1f]; 9257 9258 u8 reserved_at_20[0x60]; 9259 }; 9260 9261 struct mlx5_ifc_umr_pointer_desc_argument_bits { 9262 u8 reserved_at_0[0x20]; 9263 9264 u8 mkey[0x20]; 9265 9266 u8 addressh_63_32[0x20]; 9267 9268 u8 addressl_31_0[0x20]; 9269 }; 9270 9271 struct mlx5_ifc_ud_adrs_vector_bits { 9272 u8 dc_key[0x40]; 9273 9274 u8 ext[0x1]; 9275 u8 reserved_at_41[0x7]; 9276 u8 destination_qp_dct[0x18]; 9277 9278 u8 static_rate[0x4]; 9279 u8 sl_eth_prio[0x4]; 9280 u8 fl[0x1]; 9281 u8 mlid[0x7]; 9282 u8 rlid_udp_sport[0x10]; 9283 9284 u8 reserved_at_80[0x20]; 9285 9286 u8 rmac_47_16[0x20]; 9287 9288 u8 rmac_15_0[0x10]; 9289 u8 tclass[0x8]; 9290 u8 hop_limit[0x8]; 9291 9292 u8 reserved_at_e0[0x1]; 9293 u8 grh[0x1]; 9294 u8 reserved_at_e2[0x2]; 9295 u8 src_addr_index[0x8]; 9296 u8 flow_label[0x14]; 9297 9298 u8 rgid_rip[16][0x8]; 9299 }; 9300 9301 struct mlx5_ifc_pages_req_event_bits { 9302 u8 reserved_at_0[0x10]; 9303 u8 function_id[0x10]; 9304 9305 u8 num_pages[0x20]; 9306 9307 u8 reserved_at_40[0xa0]; 9308 }; 9309 9310 struct mlx5_ifc_eqe_bits { 9311 u8 reserved_at_0[0x8]; 9312 u8 event_type[0x8]; 9313 u8 reserved_at_10[0x8]; 9314 u8 event_sub_type[0x8]; 9315 9316 u8 reserved_at_20[0xe0]; 9317 9318 union mlx5_ifc_event_auto_bits event_data; 9319 9320 u8 reserved_at_1e0[0x10]; 9321 u8 signature[0x8]; 9322 u8 reserved_at_1f8[0x7]; 9323 u8 owner[0x1]; 9324 }; 9325 9326 enum { 9327 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7, 9328 }; 9329 9330 struct mlx5_ifc_cmd_queue_entry_bits { 9331 u8 type[0x8]; 9332 u8 reserved_at_8[0x18]; 9333 9334 u8 input_length[0x20]; 9335 9336 u8 input_mailbox_pointer_63_32[0x20]; 9337 9338 u8 input_mailbox_pointer_31_9[0x17]; 9339 u8 reserved_at_77[0x9]; 9340 9341 u8 command_input_inline_data[16][0x8]; 9342 9343 u8 command_output_inline_data[16][0x8]; 9344 9345 u8 output_mailbox_pointer_63_32[0x20]; 9346 9347 u8 output_mailbox_pointer_31_9[0x17]; 9348 u8 reserved_at_1b7[0x9]; 9349 9350 u8 output_length[0x20]; 9351 9352 u8 token[0x8]; 9353 u8 signature[0x8]; 9354 u8 reserved_at_1f0[0x8]; 9355 u8 status[0x7]; 9356 u8 ownership[0x1]; 9357 }; 9358 9359 struct mlx5_ifc_cmd_out_bits { 9360 u8 status[0x8]; 9361 u8 reserved_at_8[0x18]; 9362 9363 u8 syndrome[0x20]; 9364 9365 u8 command_output[0x20]; 9366 }; 9367 9368 struct mlx5_ifc_cmd_in_bits { 9369 u8 opcode[0x10]; 9370 u8 reserved_at_10[0x10]; 9371 9372 u8 reserved_at_20[0x10]; 9373 u8 op_mod[0x10]; 9374 9375 u8 command[0][0x20]; 9376 }; 9377 9378 struct mlx5_ifc_cmd_if_box_bits { 9379 u8 mailbox_data[512][0x8]; 9380 9381 u8 reserved_at_1000[0x180]; 9382 9383 u8 next_pointer_63_32[0x20]; 9384 9385 u8 next_pointer_31_10[0x16]; 9386 u8 reserved_at_11b6[0xa]; 9387 9388 u8 block_number[0x20]; 9389 9390 u8 reserved_at_11e0[0x8]; 9391 u8 token[0x8]; 9392 u8 ctrl_signature[0x8]; 9393 u8 signature[0x8]; 9394 }; 9395 9396 struct mlx5_ifc_mtt_bits { 9397 u8 ptag_63_32[0x20]; 9398 9399 u8 ptag_31_8[0x18]; 9400 u8 reserved_at_38[0x6]; 9401 u8 wr_en[0x1]; 9402 u8 rd_en[0x1]; 9403 }; 9404 9405 struct mlx5_ifc_query_wol_rol_out_bits { 9406 u8 status[0x8]; 9407 u8 reserved_at_8[0x18]; 9408 9409 u8 syndrome[0x20]; 9410 9411 u8 reserved_at_40[0x10]; 9412 u8 rol_mode[0x8]; 9413 u8 wol_mode[0x8]; 9414 9415 u8 reserved_at_60[0x20]; 9416 }; 9417 9418 struct mlx5_ifc_query_wol_rol_in_bits { 9419 u8 opcode[0x10]; 9420 u8 reserved_at_10[0x10]; 9421 9422 u8 reserved_at_20[0x10]; 9423 u8 op_mod[0x10]; 9424 9425 u8 reserved_at_40[0x40]; 9426 }; 9427 9428 struct mlx5_ifc_set_wol_rol_out_bits { 9429 u8 status[0x8]; 9430 u8 reserved_at_8[0x18]; 9431 9432 u8 syndrome[0x20]; 9433 9434 u8 reserved_at_40[0x40]; 9435 }; 9436 9437 struct mlx5_ifc_set_wol_rol_in_bits { 9438 u8 opcode[0x10]; 9439 u8 reserved_at_10[0x10]; 9440 9441 u8 reserved_at_20[0x10]; 9442 u8 op_mod[0x10]; 9443 9444 u8 rol_mode_valid[0x1]; 9445 u8 wol_mode_valid[0x1]; 9446 u8 reserved_at_42[0xe]; 9447 u8 rol_mode[0x8]; 9448 u8 wol_mode[0x8]; 9449 9450 u8 reserved_at_60[0x20]; 9451 }; 9452 9453 enum { 9454 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0, 9455 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1, 9456 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2, 9457 }; 9458 9459 enum { 9460 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0, 9461 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1, 9462 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2, 9463 }; 9464 9465 enum { 9466 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR = 0x1, 9467 MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC = 0x7, 9468 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR = 0x8, 9469 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR = 0x9, 9470 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR = 0xa, 9471 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR = 0xb, 9472 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN = 0xc, 9473 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR = 0xd, 9474 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV = 0xe, 9475 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR = 0xf, 9476 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR = 0x10, 9477 }; 9478 9479 struct mlx5_ifc_initial_seg_bits { 9480 u8 fw_rev_minor[0x10]; 9481 u8 fw_rev_major[0x10]; 9482 9483 u8 cmd_interface_rev[0x10]; 9484 u8 fw_rev_subminor[0x10]; 9485 9486 u8 reserved_at_40[0x40]; 9487 9488 u8 cmdq_phy_addr_63_32[0x20]; 9489 9490 u8 cmdq_phy_addr_31_12[0x14]; 9491 u8 reserved_at_b4[0x2]; 9492 u8 nic_interface[0x2]; 9493 u8 log_cmdq_size[0x4]; 9494 u8 log_cmdq_stride[0x4]; 9495 9496 u8 command_doorbell_vector[0x20]; 9497 9498 u8 reserved_at_e0[0xf00]; 9499 9500 u8 initializing[0x1]; 9501 u8 reserved_at_fe1[0x4]; 9502 u8 nic_interface_supported[0x3]; 9503 u8 embedded_cpu[0x1]; 9504 u8 reserved_at_fe9[0x17]; 9505 9506 struct mlx5_ifc_health_buffer_bits health_buffer; 9507 9508 u8 no_dram_nic_offset[0x20]; 9509 9510 u8 reserved_at_1220[0x6e40]; 9511 9512 u8 reserved_at_8060[0x1f]; 9513 u8 clear_int[0x1]; 9514 9515 u8 health_syndrome[0x8]; 9516 u8 health_counter[0x18]; 9517 9518 u8 reserved_at_80a0[0x17fc0]; 9519 }; 9520 9521 struct mlx5_ifc_mtpps_reg_bits { 9522 u8 reserved_at_0[0xc]; 9523 u8 cap_number_of_pps_pins[0x4]; 9524 u8 reserved_at_10[0x4]; 9525 u8 cap_max_num_of_pps_in_pins[0x4]; 9526 u8 reserved_at_18[0x4]; 9527 u8 cap_max_num_of_pps_out_pins[0x4]; 9528 9529 u8 reserved_at_20[0x24]; 9530 u8 cap_pin_3_mode[0x4]; 9531 u8 reserved_at_48[0x4]; 9532 u8 cap_pin_2_mode[0x4]; 9533 u8 reserved_at_50[0x4]; 9534 u8 cap_pin_1_mode[0x4]; 9535 u8 reserved_at_58[0x4]; 9536 u8 cap_pin_0_mode[0x4]; 9537 9538 u8 reserved_at_60[0x4]; 9539 u8 cap_pin_7_mode[0x4]; 9540 u8 reserved_at_68[0x4]; 9541 u8 cap_pin_6_mode[0x4]; 9542 u8 reserved_at_70[0x4]; 9543 u8 cap_pin_5_mode[0x4]; 9544 u8 reserved_at_78[0x4]; 9545 u8 cap_pin_4_mode[0x4]; 9546 9547 u8 field_select[0x20]; 9548 u8 reserved_at_a0[0x60]; 9549 9550 u8 enable[0x1]; 9551 u8 reserved_at_101[0xb]; 9552 u8 pattern[0x4]; 9553 u8 reserved_at_110[0x4]; 9554 u8 pin_mode[0x4]; 9555 u8 pin[0x8]; 9556 9557 u8 reserved_at_120[0x20]; 9558 9559 u8 time_stamp[0x40]; 9560 9561 u8 out_pulse_duration[0x10]; 9562 u8 out_periodic_adjustment[0x10]; 9563 u8 enhanced_out_periodic_adjustment[0x20]; 9564 9565 u8 reserved_at_1c0[0x20]; 9566 }; 9567 9568 struct mlx5_ifc_mtppse_reg_bits { 9569 u8 reserved_at_0[0x18]; 9570 u8 pin[0x8]; 9571 u8 event_arm[0x1]; 9572 u8 reserved_at_21[0x1b]; 9573 u8 event_generation_mode[0x4]; 9574 u8 reserved_at_40[0x40]; 9575 }; 9576 9577 struct mlx5_ifc_mcqs_reg_bits { 9578 u8 last_index_flag[0x1]; 9579 u8 reserved_at_1[0x7]; 9580 u8 fw_device[0x8]; 9581 u8 component_index[0x10]; 9582 9583 u8 reserved_at_20[0x10]; 9584 u8 identifier[0x10]; 9585 9586 u8 reserved_at_40[0x17]; 9587 u8 component_status[0x5]; 9588 u8 component_update_state[0x4]; 9589 9590 u8 last_update_state_changer_type[0x4]; 9591 u8 last_update_state_changer_host_id[0x4]; 9592 u8 reserved_at_68[0x18]; 9593 }; 9594 9595 struct mlx5_ifc_mcqi_cap_bits { 9596 u8 supported_info_bitmask[0x20]; 9597 9598 u8 component_size[0x20]; 9599 9600 u8 max_component_size[0x20]; 9601 9602 u8 log_mcda_word_size[0x4]; 9603 u8 reserved_at_64[0xc]; 9604 u8 mcda_max_write_size[0x10]; 9605 9606 u8 rd_en[0x1]; 9607 u8 reserved_at_81[0x1]; 9608 u8 match_chip_id[0x1]; 9609 u8 match_psid[0x1]; 9610 u8 check_user_timestamp[0x1]; 9611 u8 match_base_guid_mac[0x1]; 9612 u8 reserved_at_86[0x1a]; 9613 }; 9614 9615 struct mlx5_ifc_mcqi_version_bits { 9616 u8 reserved_at_0[0x2]; 9617 u8 build_time_valid[0x1]; 9618 u8 user_defined_time_valid[0x1]; 9619 u8 reserved_at_4[0x14]; 9620 u8 version_string_length[0x8]; 9621 9622 u8 version[0x20]; 9623 9624 u8 build_time[0x40]; 9625 9626 u8 user_defined_time[0x40]; 9627 9628 u8 build_tool_version[0x20]; 9629 9630 u8 reserved_at_e0[0x20]; 9631 9632 u8 version_string[92][0x8]; 9633 }; 9634 9635 struct mlx5_ifc_mcqi_activation_method_bits { 9636 u8 pending_server_ac_power_cycle[0x1]; 9637 u8 pending_server_dc_power_cycle[0x1]; 9638 u8 pending_server_reboot[0x1]; 9639 u8 pending_fw_reset[0x1]; 9640 u8 auto_activate[0x1]; 9641 u8 all_hosts_sync[0x1]; 9642 u8 device_hw_reset[0x1]; 9643 u8 reserved_at_7[0x19]; 9644 }; 9645 9646 union mlx5_ifc_mcqi_reg_data_bits { 9647 struct mlx5_ifc_mcqi_cap_bits mcqi_caps; 9648 struct mlx5_ifc_mcqi_version_bits mcqi_version; 9649 struct mlx5_ifc_mcqi_activation_method_bits mcqi_activation_mathod; 9650 }; 9651 9652 struct mlx5_ifc_mcqi_reg_bits { 9653 u8 read_pending_component[0x1]; 9654 u8 reserved_at_1[0xf]; 9655 u8 component_index[0x10]; 9656 9657 u8 reserved_at_20[0x20]; 9658 9659 u8 reserved_at_40[0x1b]; 9660 u8 info_type[0x5]; 9661 9662 u8 info_size[0x20]; 9663 9664 u8 offset[0x20]; 9665 9666 u8 reserved_at_a0[0x10]; 9667 u8 data_size[0x10]; 9668 9669 union mlx5_ifc_mcqi_reg_data_bits data[0]; 9670 }; 9671 9672 struct mlx5_ifc_mcc_reg_bits { 9673 u8 reserved_at_0[0x4]; 9674 u8 time_elapsed_since_last_cmd[0xc]; 9675 u8 reserved_at_10[0x8]; 9676 u8 instruction[0x8]; 9677 9678 u8 reserved_at_20[0x10]; 9679 u8 component_index[0x10]; 9680 9681 u8 reserved_at_40[0x8]; 9682 u8 update_handle[0x18]; 9683 9684 u8 handle_owner_type[0x4]; 9685 u8 handle_owner_host_id[0x4]; 9686 u8 reserved_at_68[0x1]; 9687 u8 control_progress[0x7]; 9688 u8 error_code[0x8]; 9689 u8 reserved_at_78[0x4]; 9690 u8 control_state[0x4]; 9691 9692 u8 component_size[0x20]; 9693 9694 u8 reserved_at_a0[0x60]; 9695 }; 9696 9697 struct mlx5_ifc_mcda_reg_bits { 9698 u8 reserved_at_0[0x8]; 9699 u8 update_handle[0x18]; 9700 9701 u8 offset[0x20]; 9702 9703 u8 reserved_at_40[0x10]; 9704 u8 size[0x10]; 9705 9706 u8 reserved_at_60[0x20]; 9707 9708 u8 data[0][0x20]; 9709 }; 9710 9711 enum { 9712 MLX5_MFRL_REG_RESET_TYPE_FULL_CHIP = BIT(0), 9713 MLX5_MFRL_REG_RESET_TYPE_NET_PORT_ALIVE = BIT(1), 9714 }; 9715 9716 enum { 9717 MLX5_MFRL_REG_RESET_LEVEL0 = BIT(0), 9718 MLX5_MFRL_REG_RESET_LEVEL3 = BIT(3), 9719 MLX5_MFRL_REG_RESET_LEVEL6 = BIT(6), 9720 }; 9721 9722 struct mlx5_ifc_mfrl_reg_bits { 9723 u8 reserved_at_0[0x20]; 9724 9725 u8 reserved_at_20[0x2]; 9726 u8 pci_sync_for_fw_update_start[0x1]; 9727 u8 pci_sync_for_fw_update_resp[0x2]; 9728 u8 rst_type_sel[0x3]; 9729 u8 reserved_at_28[0x8]; 9730 u8 reset_type[0x8]; 9731 u8 reset_level[0x8]; 9732 }; 9733 9734 struct mlx5_ifc_mirc_reg_bits { 9735 u8 reserved_at_0[0x18]; 9736 u8 status_code[0x8]; 9737 9738 u8 reserved_at_20[0x20]; 9739 }; 9740 9741 union mlx5_ifc_ports_control_registers_document_bits { 9742 struct mlx5_ifc_bufferx_reg_bits bufferx_reg; 9743 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 9744 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 9745 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 9746 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 9747 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 9748 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 9749 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout; 9750 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout; 9751 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping; 9752 struct mlx5_ifc_pamp_reg_bits pamp_reg; 9753 struct mlx5_ifc_paos_reg_bits paos_reg; 9754 struct mlx5_ifc_pcap_reg_bits pcap_reg; 9755 struct mlx5_ifc_peir_reg_bits peir_reg; 9756 struct mlx5_ifc_pelc_reg_bits pelc_reg; 9757 struct mlx5_ifc_pfcc_reg_bits pfcc_reg; 9758 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 9759 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 9760 struct mlx5_ifc_pifr_reg_bits pifr_reg; 9761 struct mlx5_ifc_pipg_reg_bits pipg_reg; 9762 struct mlx5_ifc_plbf_reg_bits plbf_reg; 9763 struct mlx5_ifc_plib_reg_bits plib_reg; 9764 struct mlx5_ifc_plpc_reg_bits plpc_reg; 9765 struct mlx5_ifc_pmaos_reg_bits pmaos_reg; 9766 struct mlx5_ifc_pmlp_reg_bits pmlp_reg; 9767 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg; 9768 struct mlx5_ifc_pmpc_reg_bits pmpc_reg; 9769 struct mlx5_ifc_pmpe_reg_bits pmpe_reg; 9770 struct mlx5_ifc_pmpr_reg_bits pmpr_reg; 9771 struct mlx5_ifc_pmtu_reg_bits pmtu_reg; 9772 struct mlx5_ifc_ppad_reg_bits ppad_reg; 9773 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg; 9774 struct mlx5_ifc_mpein_reg_bits mpein_reg; 9775 struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg; 9776 struct mlx5_ifc_pplm_reg_bits pplm_reg; 9777 struct mlx5_ifc_pplr_reg_bits pplr_reg; 9778 struct mlx5_ifc_ppsc_reg_bits ppsc_reg; 9779 struct mlx5_ifc_pqdr_reg_bits pqdr_reg; 9780 struct mlx5_ifc_pspa_reg_bits pspa_reg; 9781 struct mlx5_ifc_ptas_reg_bits ptas_reg; 9782 struct mlx5_ifc_ptys_reg_bits ptys_reg; 9783 struct mlx5_ifc_mlcr_reg_bits mlcr_reg; 9784 struct mlx5_ifc_pude_reg_bits pude_reg; 9785 struct mlx5_ifc_pvlc_reg_bits pvlc_reg; 9786 struct mlx5_ifc_slrg_reg_bits slrg_reg; 9787 struct mlx5_ifc_sltp_reg_bits sltp_reg; 9788 struct mlx5_ifc_mtpps_reg_bits mtpps_reg; 9789 struct mlx5_ifc_mtppse_reg_bits mtppse_reg; 9790 struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg; 9791 struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits; 9792 struct mlx5_ifc_fpga_cap_bits fpga_cap_bits; 9793 struct mlx5_ifc_mcqi_reg_bits mcqi_reg; 9794 struct mlx5_ifc_mcc_reg_bits mcc_reg; 9795 struct mlx5_ifc_mcda_reg_bits mcda_reg; 9796 struct mlx5_ifc_mirc_reg_bits mirc_reg; 9797 struct mlx5_ifc_mfrl_reg_bits mfrl_reg; 9798 u8 reserved_at_0[0x60e0]; 9799 }; 9800 9801 union mlx5_ifc_debug_enhancements_document_bits { 9802 struct mlx5_ifc_health_buffer_bits health_buffer; 9803 u8 reserved_at_0[0x200]; 9804 }; 9805 9806 union mlx5_ifc_uplink_pci_interface_document_bits { 9807 struct mlx5_ifc_initial_seg_bits initial_seg; 9808 u8 reserved_at_0[0x20060]; 9809 }; 9810 9811 struct mlx5_ifc_set_flow_table_root_out_bits { 9812 u8 status[0x8]; 9813 u8 reserved_at_8[0x18]; 9814 9815 u8 syndrome[0x20]; 9816 9817 u8 reserved_at_40[0x40]; 9818 }; 9819 9820 struct mlx5_ifc_set_flow_table_root_in_bits { 9821 u8 opcode[0x10]; 9822 u8 reserved_at_10[0x10]; 9823 9824 u8 reserved_at_20[0x10]; 9825 u8 op_mod[0x10]; 9826 9827 u8 other_vport[0x1]; 9828 u8 reserved_at_41[0xf]; 9829 u8 vport_number[0x10]; 9830 9831 u8 reserved_at_60[0x20]; 9832 9833 u8 table_type[0x8]; 9834 u8 reserved_at_88[0x18]; 9835 9836 u8 reserved_at_a0[0x8]; 9837 u8 table_id[0x18]; 9838 9839 u8 reserved_at_c0[0x8]; 9840 u8 underlay_qpn[0x18]; 9841 u8 reserved_at_e0[0x120]; 9842 }; 9843 9844 enum { 9845 MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = (1UL << 0), 9846 MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15), 9847 }; 9848 9849 struct mlx5_ifc_modify_flow_table_out_bits { 9850 u8 status[0x8]; 9851 u8 reserved_at_8[0x18]; 9852 9853 u8 syndrome[0x20]; 9854 9855 u8 reserved_at_40[0x40]; 9856 }; 9857 9858 struct mlx5_ifc_modify_flow_table_in_bits { 9859 u8 opcode[0x10]; 9860 u8 reserved_at_10[0x10]; 9861 9862 u8 reserved_at_20[0x10]; 9863 u8 op_mod[0x10]; 9864 9865 u8 other_vport[0x1]; 9866 u8 reserved_at_41[0xf]; 9867 u8 vport_number[0x10]; 9868 9869 u8 reserved_at_60[0x10]; 9870 u8 modify_field_select[0x10]; 9871 9872 u8 table_type[0x8]; 9873 u8 reserved_at_88[0x18]; 9874 9875 u8 reserved_at_a0[0x8]; 9876 u8 table_id[0x18]; 9877 9878 struct mlx5_ifc_flow_table_context_bits flow_table_context; 9879 }; 9880 9881 struct mlx5_ifc_ets_tcn_config_reg_bits { 9882 u8 g[0x1]; 9883 u8 b[0x1]; 9884 u8 r[0x1]; 9885 u8 reserved_at_3[0x9]; 9886 u8 group[0x4]; 9887 u8 reserved_at_10[0x9]; 9888 u8 bw_allocation[0x7]; 9889 9890 u8 reserved_at_20[0xc]; 9891 u8 max_bw_units[0x4]; 9892 u8 reserved_at_30[0x8]; 9893 u8 max_bw_value[0x8]; 9894 }; 9895 9896 struct mlx5_ifc_ets_global_config_reg_bits { 9897 u8 reserved_at_0[0x2]; 9898 u8 r[0x1]; 9899 u8 reserved_at_3[0x1d]; 9900 9901 u8 reserved_at_20[0xc]; 9902 u8 max_bw_units[0x4]; 9903 u8 reserved_at_30[0x8]; 9904 u8 max_bw_value[0x8]; 9905 }; 9906 9907 struct mlx5_ifc_qetc_reg_bits { 9908 u8 reserved_at_0[0x8]; 9909 u8 port_number[0x8]; 9910 u8 reserved_at_10[0x30]; 9911 9912 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8]; 9913 struct mlx5_ifc_ets_global_config_reg_bits global_configuration; 9914 }; 9915 9916 struct mlx5_ifc_qpdpm_dscp_reg_bits { 9917 u8 e[0x1]; 9918 u8 reserved_at_01[0x0b]; 9919 u8 prio[0x04]; 9920 }; 9921 9922 struct mlx5_ifc_qpdpm_reg_bits { 9923 u8 reserved_at_0[0x8]; 9924 u8 local_port[0x8]; 9925 u8 reserved_at_10[0x10]; 9926 struct mlx5_ifc_qpdpm_dscp_reg_bits dscp[64]; 9927 }; 9928 9929 struct mlx5_ifc_qpts_reg_bits { 9930 u8 reserved_at_0[0x8]; 9931 u8 local_port[0x8]; 9932 u8 reserved_at_10[0x2d]; 9933 u8 trust_state[0x3]; 9934 }; 9935 9936 struct mlx5_ifc_pptb_reg_bits { 9937 u8 reserved_at_0[0x2]; 9938 u8 mm[0x2]; 9939 u8 reserved_at_4[0x4]; 9940 u8 local_port[0x8]; 9941 u8 reserved_at_10[0x6]; 9942 u8 cm[0x1]; 9943 u8 um[0x1]; 9944 u8 pm[0x8]; 9945 9946 u8 prio_x_buff[0x20]; 9947 9948 u8 pm_msb[0x8]; 9949 u8 reserved_at_48[0x10]; 9950 u8 ctrl_buff[0x4]; 9951 u8 untagged_buff[0x4]; 9952 }; 9953 9954 struct mlx5_ifc_pbmc_reg_bits { 9955 u8 reserved_at_0[0x8]; 9956 u8 local_port[0x8]; 9957 u8 reserved_at_10[0x10]; 9958 9959 u8 xoff_timer_value[0x10]; 9960 u8 xoff_refresh[0x10]; 9961 9962 u8 reserved_at_40[0x9]; 9963 u8 fullness_threshold[0x7]; 9964 u8 port_buffer_size[0x10]; 9965 9966 struct mlx5_ifc_bufferx_reg_bits buffer[10]; 9967 9968 u8 reserved_at_2e0[0x40]; 9969 }; 9970 9971 struct mlx5_ifc_qtct_reg_bits { 9972 u8 reserved_at_0[0x8]; 9973 u8 port_number[0x8]; 9974 u8 reserved_at_10[0xd]; 9975 u8 prio[0x3]; 9976 9977 u8 reserved_at_20[0x1d]; 9978 u8 tclass[0x3]; 9979 }; 9980 9981 struct mlx5_ifc_mcia_reg_bits { 9982 u8 l[0x1]; 9983 u8 reserved_at_1[0x7]; 9984 u8 module[0x8]; 9985 u8 reserved_at_10[0x8]; 9986 u8 status[0x8]; 9987 9988 u8 i2c_device_address[0x8]; 9989 u8 page_number[0x8]; 9990 u8 device_address[0x10]; 9991 9992 u8 reserved_at_40[0x10]; 9993 u8 size[0x10]; 9994 9995 u8 reserved_at_60[0x20]; 9996 9997 u8 dword_0[0x20]; 9998 u8 dword_1[0x20]; 9999 u8 dword_2[0x20]; 10000 u8 dword_3[0x20]; 10001 u8 dword_4[0x20]; 10002 u8 dword_5[0x20]; 10003 u8 dword_6[0x20]; 10004 u8 dword_7[0x20]; 10005 u8 dword_8[0x20]; 10006 u8 dword_9[0x20]; 10007 u8 dword_10[0x20]; 10008 u8 dword_11[0x20]; 10009 }; 10010 10011 struct mlx5_ifc_dcbx_param_bits { 10012 u8 dcbx_cee_cap[0x1]; 10013 u8 dcbx_ieee_cap[0x1]; 10014 u8 dcbx_standby_cap[0x1]; 10015 u8 reserved_at_3[0x5]; 10016 u8 port_number[0x8]; 10017 u8 reserved_at_10[0xa]; 10018 u8 max_application_table_size[6]; 10019 u8 reserved_at_20[0x15]; 10020 u8 version_oper[0x3]; 10021 u8 reserved_at_38[5]; 10022 u8 version_admin[0x3]; 10023 u8 willing_admin[0x1]; 10024 u8 reserved_at_41[0x3]; 10025 u8 pfc_cap_oper[0x4]; 10026 u8 reserved_at_48[0x4]; 10027 u8 pfc_cap_admin[0x4]; 10028 u8 reserved_at_50[0x4]; 10029 u8 num_of_tc_oper[0x4]; 10030 u8 reserved_at_58[0x4]; 10031 u8 num_of_tc_admin[0x4]; 10032 u8 remote_willing[0x1]; 10033 u8 reserved_at_61[3]; 10034 u8 remote_pfc_cap[4]; 10035 u8 reserved_at_68[0x14]; 10036 u8 remote_num_of_tc[0x4]; 10037 u8 reserved_at_80[0x18]; 10038 u8 error[0x8]; 10039 u8 reserved_at_a0[0x160]; 10040 }; 10041 10042 struct mlx5_ifc_lagc_bits { 10043 u8 reserved_at_0[0x1d]; 10044 u8 lag_state[0x3]; 10045 10046 u8 reserved_at_20[0x14]; 10047 u8 tx_remap_affinity_2[0x4]; 10048 u8 reserved_at_38[0x4]; 10049 u8 tx_remap_affinity_1[0x4]; 10050 }; 10051 10052 struct mlx5_ifc_create_lag_out_bits { 10053 u8 status[0x8]; 10054 u8 reserved_at_8[0x18]; 10055 10056 u8 syndrome[0x20]; 10057 10058 u8 reserved_at_40[0x40]; 10059 }; 10060 10061 struct mlx5_ifc_create_lag_in_bits { 10062 u8 opcode[0x10]; 10063 u8 reserved_at_10[0x10]; 10064 10065 u8 reserved_at_20[0x10]; 10066 u8 op_mod[0x10]; 10067 10068 struct mlx5_ifc_lagc_bits ctx; 10069 }; 10070 10071 struct mlx5_ifc_modify_lag_out_bits { 10072 u8 status[0x8]; 10073 u8 reserved_at_8[0x18]; 10074 10075 u8 syndrome[0x20]; 10076 10077 u8 reserved_at_40[0x40]; 10078 }; 10079 10080 struct mlx5_ifc_modify_lag_in_bits { 10081 u8 opcode[0x10]; 10082 u8 reserved_at_10[0x10]; 10083 10084 u8 reserved_at_20[0x10]; 10085 u8 op_mod[0x10]; 10086 10087 u8 reserved_at_40[0x20]; 10088 u8 field_select[0x20]; 10089 10090 struct mlx5_ifc_lagc_bits ctx; 10091 }; 10092 10093 struct mlx5_ifc_query_lag_out_bits { 10094 u8 status[0x8]; 10095 u8 reserved_at_8[0x18]; 10096 10097 u8 syndrome[0x20]; 10098 10099 struct mlx5_ifc_lagc_bits ctx; 10100 }; 10101 10102 struct mlx5_ifc_query_lag_in_bits { 10103 u8 opcode[0x10]; 10104 u8 reserved_at_10[0x10]; 10105 10106 u8 reserved_at_20[0x10]; 10107 u8 op_mod[0x10]; 10108 10109 u8 reserved_at_40[0x40]; 10110 }; 10111 10112 struct mlx5_ifc_destroy_lag_out_bits { 10113 u8 status[0x8]; 10114 u8 reserved_at_8[0x18]; 10115 10116 u8 syndrome[0x20]; 10117 10118 u8 reserved_at_40[0x40]; 10119 }; 10120 10121 struct mlx5_ifc_destroy_lag_in_bits { 10122 u8 opcode[0x10]; 10123 u8 reserved_at_10[0x10]; 10124 10125 u8 reserved_at_20[0x10]; 10126 u8 op_mod[0x10]; 10127 10128 u8 reserved_at_40[0x40]; 10129 }; 10130 10131 struct mlx5_ifc_create_vport_lag_out_bits { 10132 u8 status[0x8]; 10133 u8 reserved_at_8[0x18]; 10134 10135 u8 syndrome[0x20]; 10136 10137 u8 reserved_at_40[0x40]; 10138 }; 10139 10140 struct mlx5_ifc_create_vport_lag_in_bits { 10141 u8 opcode[0x10]; 10142 u8 reserved_at_10[0x10]; 10143 10144 u8 reserved_at_20[0x10]; 10145 u8 op_mod[0x10]; 10146 10147 u8 reserved_at_40[0x40]; 10148 }; 10149 10150 struct mlx5_ifc_destroy_vport_lag_out_bits { 10151 u8 status[0x8]; 10152 u8 reserved_at_8[0x18]; 10153 10154 u8 syndrome[0x20]; 10155 10156 u8 reserved_at_40[0x40]; 10157 }; 10158 10159 struct mlx5_ifc_destroy_vport_lag_in_bits { 10160 u8 opcode[0x10]; 10161 u8 reserved_at_10[0x10]; 10162 10163 u8 reserved_at_20[0x10]; 10164 u8 op_mod[0x10]; 10165 10166 u8 reserved_at_40[0x40]; 10167 }; 10168 10169 struct mlx5_ifc_alloc_memic_in_bits { 10170 u8 opcode[0x10]; 10171 u8 reserved_at_10[0x10]; 10172 10173 u8 reserved_at_20[0x10]; 10174 u8 op_mod[0x10]; 10175 10176 u8 reserved_at_30[0x20]; 10177 10178 u8 reserved_at_40[0x18]; 10179 u8 log_memic_addr_alignment[0x8]; 10180 10181 u8 range_start_addr[0x40]; 10182 10183 u8 range_size[0x20]; 10184 10185 u8 memic_size[0x20]; 10186 }; 10187 10188 struct mlx5_ifc_alloc_memic_out_bits { 10189 u8 status[0x8]; 10190 u8 reserved_at_8[0x18]; 10191 10192 u8 syndrome[0x20]; 10193 10194 u8 memic_start_addr[0x40]; 10195 }; 10196 10197 struct mlx5_ifc_dealloc_memic_in_bits { 10198 u8 opcode[0x10]; 10199 u8 reserved_at_10[0x10]; 10200 10201 u8 reserved_at_20[0x10]; 10202 u8 op_mod[0x10]; 10203 10204 u8 reserved_at_40[0x40]; 10205 10206 u8 memic_start_addr[0x40]; 10207 10208 u8 memic_size[0x20]; 10209 10210 u8 reserved_at_e0[0x20]; 10211 }; 10212 10213 struct mlx5_ifc_dealloc_memic_out_bits { 10214 u8 status[0x8]; 10215 u8 reserved_at_8[0x18]; 10216 10217 u8 syndrome[0x20]; 10218 10219 u8 reserved_at_40[0x40]; 10220 }; 10221 10222 struct mlx5_ifc_general_obj_in_cmd_hdr_bits { 10223 u8 opcode[0x10]; 10224 u8 uid[0x10]; 10225 10226 u8 vhca_tunnel_id[0x10]; 10227 u8 obj_type[0x10]; 10228 10229 u8 obj_id[0x20]; 10230 10231 u8 reserved_at_60[0x20]; 10232 }; 10233 10234 struct mlx5_ifc_general_obj_out_cmd_hdr_bits { 10235 u8 status[0x8]; 10236 u8 reserved_at_8[0x18]; 10237 10238 u8 syndrome[0x20]; 10239 10240 u8 obj_id[0x20]; 10241 10242 u8 reserved_at_60[0x20]; 10243 }; 10244 10245 struct mlx5_ifc_umem_bits { 10246 u8 reserved_at_0[0x80]; 10247 10248 u8 reserved_at_80[0x1b]; 10249 u8 log_page_size[0x5]; 10250 10251 u8 page_offset[0x20]; 10252 10253 u8 num_of_mtt[0x40]; 10254 10255 struct mlx5_ifc_mtt_bits mtt[0]; 10256 }; 10257 10258 struct mlx5_ifc_uctx_bits { 10259 u8 cap[0x20]; 10260 10261 u8 reserved_at_20[0x160]; 10262 }; 10263 10264 struct mlx5_ifc_sw_icm_bits { 10265 u8 modify_field_select[0x40]; 10266 10267 u8 reserved_at_40[0x18]; 10268 u8 log_sw_icm_size[0x8]; 10269 10270 u8 reserved_at_60[0x20]; 10271 10272 u8 sw_icm_start_addr[0x40]; 10273 10274 u8 reserved_at_c0[0x140]; 10275 }; 10276 10277 struct mlx5_ifc_geneve_tlv_option_bits { 10278 u8 modify_field_select[0x40]; 10279 10280 u8 reserved_at_40[0x18]; 10281 u8 geneve_option_fte_index[0x8]; 10282 10283 u8 option_class[0x10]; 10284 u8 option_type[0x8]; 10285 u8 reserved_at_78[0x3]; 10286 u8 option_data_length[0x5]; 10287 10288 u8 reserved_at_80[0x180]; 10289 }; 10290 10291 struct mlx5_ifc_create_umem_in_bits { 10292 u8 opcode[0x10]; 10293 u8 uid[0x10]; 10294 10295 u8 reserved_at_20[0x10]; 10296 u8 op_mod[0x10]; 10297 10298 u8 reserved_at_40[0x40]; 10299 10300 struct mlx5_ifc_umem_bits umem; 10301 }; 10302 10303 struct mlx5_ifc_create_uctx_in_bits { 10304 u8 opcode[0x10]; 10305 u8 reserved_at_10[0x10]; 10306 10307 u8 reserved_at_20[0x10]; 10308 u8 op_mod[0x10]; 10309 10310 u8 reserved_at_40[0x40]; 10311 10312 struct mlx5_ifc_uctx_bits uctx; 10313 }; 10314 10315 struct mlx5_ifc_destroy_uctx_in_bits { 10316 u8 opcode[0x10]; 10317 u8 reserved_at_10[0x10]; 10318 10319 u8 reserved_at_20[0x10]; 10320 u8 op_mod[0x10]; 10321 10322 u8 reserved_at_40[0x10]; 10323 u8 uid[0x10]; 10324 10325 u8 reserved_at_60[0x20]; 10326 }; 10327 10328 struct mlx5_ifc_create_sw_icm_in_bits { 10329 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 10330 struct mlx5_ifc_sw_icm_bits sw_icm; 10331 }; 10332 10333 struct mlx5_ifc_create_geneve_tlv_option_in_bits { 10334 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 10335 struct mlx5_ifc_geneve_tlv_option_bits geneve_tlv_opt; 10336 }; 10337 10338 struct mlx5_ifc_mtrc_string_db_param_bits { 10339 u8 string_db_base_address[0x20]; 10340 10341 u8 reserved_at_20[0x8]; 10342 u8 string_db_size[0x18]; 10343 }; 10344 10345 struct mlx5_ifc_mtrc_cap_bits { 10346 u8 trace_owner[0x1]; 10347 u8 trace_to_memory[0x1]; 10348 u8 reserved_at_2[0x4]; 10349 u8 trc_ver[0x2]; 10350 u8 reserved_at_8[0x14]; 10351 u8 num_string_db[0x4]; 10352 10353 u8 first_string_trace[0x8]; 10354 u8 num_string_trace[0x8]; 10355 u8 reserved_at_30[0x28]; 10356 10357 u8 log_max_trace_buffer_size[0x8]; 10358 10359 u8 reserved_at_60[0x20]; 10360 10361 struct mlx5_ifc_mtrc_string_db_param_bits string_db_param[8]; 10362 10363 u8 reserved_at_280[0x180]; 10364 }; 10365 10366 struct mlx5_ifc_mtrc_conf_bits { 10367 u8 reserved_at_0[0x1c]; 10368 u8 trace_mode[0x4]; 10369 u8 reserved_at_20[0x18]; 10370 u8 log_trace_buffer_size[0x8]; 10371 u8 trace_mkey[0x20]; 10372 u8 reserved_at_60[0x3a0]; 10373 }; 10374 10375 struct mlx5_ifc_mtrc_stdb_bits { 10376 u8 string_db_index[0x4]; 10377 u8 reserved_at_4[0x4]; 10378 u8 read_size[0x18]; 10379 u8 start_offset[0x20]; 10380 u8 string_db_data[0]; 10381 }; 10382 10383 struct mlx5_ifc_mtrc_ctrl_bits { 10384 u8 trace_status[0x2]; 10385 u8 reserved_at_2[0x2]; 10386 u8 arm_event[0x1]; 10387 u8 reserved_at_5[0xb]; 10388 u8 modify_field_select[0x10]; 10389 u8 reserved_at_20[0x2b]; 10390 u8 current_timestamp52_32[0x15]; 10391 u8 current_timestamp31_0[0x20]; 10392 u8 reserved_at_80[0x180]; 10393 }; 10394 10395 struct mlx5_ifc_host_params_context_bits { 10396 u8 host_number[0x8]; 10397 u8 reserved_at_8[0x7]; 10398 u8 host_pf_disabled[0x1]; 10399 u8 host_num_of_vfs[0x10]; 10400 10401 u8 host_total_vfs[0x10]; 10402 u8 host_pci_bus[0x10]; 10403 10404 u8 reserved_at_40[0x10]; 10405 u8 host_pci_device[0x10]; 10406 10407 u8 reserved_at_60[0x10]; 10408 u8 host_pci_function[0x10]; 10409 10410 u8 reserved_at_80[0x180]; 10411 }; 10412 10413 struct mlx5_ifc_query_esw_functions_in_bits { 10414 u8 opcode[0x10]; 10415 u8 reserved_at_10[0x10]; 10416 10417 u8 reserved_at_20[0x10]; 10418 u8 op_mod[0x10]; 10419 10420 u8 reserved_at_40[0x40]; 10421 }; 10422 10423 struct mlx5_ifc_query_esw_functions_out_bits { 10424 u8 status[0x8]; 10425 u8 reserved_at_8[0x18]; 10426 10427 u8 syndrome[0x20]; 10428 10429 u8 reserved_at_40[0x40]; 10430 10431 struct mlx5_ifc_host_params_context_bits host_params_context; 10432 10433 u8 reserved_at_280[0x180]; 10434 u8 host_sf_enable[0][0x40]; 10435 }; 10436 10437 struct mlx5_ifc_sf_partition_bits { 10438 u8 reserved_at_0[0x10]; 10439 u8 log_num_sf[0x8]; 10440 u8 log_sf_bar_size[0x8]; 10441 }; 10442 10443 struct mlx5_ifc_query_sf_partitions_out_bits { 10444 u8 status[0x8]; 10445 u8 reserved_at_8[0x18]; 10446 10447 u8 syndrome[0x20]; 10448 10449 u8 reserved_at_40[0x18]; 10450 u8 num_sf_partitions[0x8]; 10451 10452 u8 reserved_at_60[0x20]; 10453 10454 struct mlx5_ifc_sf_partition_bits sf_partition[0]; 10455 }; 10456 10457 struct mlx5_ifc_query_sf_partitions_in_bits { 10458 u8 opcode[0x10]; 10459 u8 reserved_at_10[0x10]; 10460 10461 u8 reserved_at_20[0x10]; 10462 u8 op_mod[0x10]; 10463 10464 u8 reserved_at_40[0x40]; 10465 }; 10466 10467 struct mlx5_ifc_dealloc_sf_out_bits { 10468 u8 status[0x8]; 10469 u8 reserved_at_8[0x18]; 10470 10471 u8 syndrome[0x20]; 10472 10473 u8 reserved_at_40[0x40]; 10474 }; 10475 10476 struct mlx5_ifc_dealloc_sf_in_bits { 10477 u8 opcode[0x10]; 10478 u8 reserved_at_10[0x10]; 10479 10480 u8 reserved_at_20[0x10]; 10481 u8 op_mod[0x10]; 10482 10483 u8 reserved_at_40[0x10]; 10484 u8 function_id[0x10]; 10485 10486 u8 reserved_at_60[0x20]; 10487 }; 10488 10489 struct mlx5_ifc_alloc_sf_out_bits { 10490 u8 status[0x8]; 10491 u8 reserved_at_8[0x18]; 10492 10493 u8 syndrome[0x20]; 10494 10495 u8 reserved_at_40[0x40]; 10496 }; 10497 10498 struct mlx5_ifc_alloc_sf_in_bits { 10499 u8 opcode[0x10]; 10500 u8 reserved_at_10[0x10]; 10501 10502 u8 reserved_at_20[0x10]; 10503 u8 op_mod[0x10]; 10504 10505 u8 reserved_at_40[0x10]; 10506 u8 function_id[0x10]; 10507 10508 u8 reserved_at_60[0x20]; 10509 }; 10510 10511 struct mlx5_ifc_affiliated_event_header_bits { 10512 u8 reserved_at_0[0x10]; 10513 u8 obj_type[0x10]; 10514 10515 u8 obj_id[0x20]; 10516 }; 10517 10518 enum { 10519 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = BIT(0xc), 10520 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_IPSEC = BIT(0x13), 10521 }; 10522 10523 enum { 10524 MLX5_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = 0xc, 10525 MLX5_GENERAL_OBJECT_TYPES_IPSEC = 0x13, 10526 }; 10527 10528 enum { 10529 MLX5_IPSEC_OBJECT_ICV_LEN_16B, 10530 MLX5_IPSEC_OBJECT_ICV_LEN_12B, 10531 MLX5_IPSEC_OBJECT_ICV_LEN_8B, 10532 }; 10533 10534 struct mlx5_ifc_ipsec_obj_bits { 10535 u8 modify_field_select[0x40]; 10536 u8 full_offload[0x1]; 10537 u8 reserved_at_41[0x1]; 10538 u8 esn_en[0x1]; 10539 u8 esn_overlap[0x1]; 10540 u8 reserved_at_44[0x2]; 10541 u8 icv_length[0x2]; 10542 u8 reserved_at_48[0x4]; 10543 u8 aso_return_reg[0x4]; 10544 u8 reserved_at_50[0x10]; 10545 10546 u8 esn_msb[0x20]; 10547 10548 u8 reserved_at_80[0x8]; 10549 u8 dekn[0x18]; 10550 10551 u8 salt[0x20]; 10552 10553 u8 implicit_iv[0x40]; 10554 10555 u8 reserved_at_100[0x700]; 10556 }; 10557 10558 struct mlx5_ifc_create_ipsec_obj_in_bits { 10559 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 10560 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 10561 }; 10562 10563 enum { 10564 MLX5_MODIFY_IPSEC_BITMASK_ESN_OVERLAP = BIT(0), 10565 MLX5_MODIFY_IPSEC_BITMASK_ESN_MSB = BIT(1), 10566 }; 10567 10568 struct mlx5_ifc_query_ipsec_obj_out_bits { 10569 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 10570 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 10571 }; 10572 10573 struct mlx5_ifc_modify_ipsec_obj_in_bits { 10574 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 10575 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 10576 }; 10577 10578 struct mlx5_ifc_encryption_key_obj_bits { 10579 u8 modify_field_select[0x40]; 10580 10581 u8 reserved_at_40[0x14]; 10582 u8 key_size[0x4]; 10583 u8 reserved_at_58[0x4]; 10584 u8 key_type[0x4]; 10585 10586 u8 reserved_at_60[0x8]; 10587 u8 pd[0x18]; 10588 10589 u8 reserved_at_80[0x180]; 10590 u8 key[8][0x20]; 10591 10592 u8 reserved_at_300[0x500]; 10593 }; 10594 10595 struct mlx5_ifc_create_encryption_key_in_bits { 10596 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 10597 struct mlx5_ifc_encryption_key_obj_bits encryption_key_object; 10598 }; 10599 10600 enum { 10601 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_128 = 0x0, 10602 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_256 = 0x1, 10603 }; 10604 10605 enum { 10606 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_TYPE_TLS = 0x1, 10607 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_TYPE_IPSEC = 0x2, 10608 }; 10609 10610 struct mlx5_ifc_tls_static_params_bits { 10611 u8 const_2[0x2]; 10612 u8 tls_version[0x4]; 10613 u8 const_1[0x2]; 10614 u8 reserved_at_8[0x14]; 10615 u8 encryption_standard[0x4]; 10616 10617 u8 reserved_at_20[0x20]; 10618 10619 u8 initial_record_number[0x40]; 10620 10621 u8 resync_tcp_sn[0x20]; 10622 10623 u8 gcm_iv[0x20]; 10624 10625 u8 implicit_iv[0x40]; 10626 10627 u8 reserved_at_100[0x8]; 10628 u8 dek_index[0x18]; 10629 10630 u8 reserved_at_120[0xe0]; 10631 }; 10632 10633 struct mlx5_ifc_tls_progress_params_bits { 10634 u8 reserved_at_0[0x8]; 10635 u8 tisn[0x18]; 10636 10637 u8 next_record_tcp_sn[0x20]; 10638 10639 u8 hw_resync_tcp_sn[0x20]; 10640 10641 u8 record_tracker_state[0x2]; 10642 u8 auth_state[0x2]; 10643 u8 reserved_at_64[0x4]; 10644 u8 hw_offset_record_number[0x18]; 10645 }; 10646 10647 #endif /* MLX5_IFC_H */ 10648