1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 #ifndef MLX5_IFC_H 33 #define MLX5_IFC_H 34 35 #include "mlx5_ifc_fpga.h" 36 37 enum { 38 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0, 39 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1, 40 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2, 41 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3, 42 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13, 43 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14, 44 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c, 45 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d, 46 MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4, 47 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5, 48 MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED = 0x7, 49 MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT = 0xc, 50 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10, 51 MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR = 0x11, 52 MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR = 0x12, 53 MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR = 0x8, 54 MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE = 0x9, 55 MLX5_EVENT_TYPE_CODING_GPIO_EVENT = 0x15, 56 MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19, 57 MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a, 58 MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT = 0x1b, 59 MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT = 0x1f, 60 MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa, 61 MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb, 62 MLX5_EVENT_TYPE_CODING_FPGA_ERROR = 0x20, 63 MLX5_EVENT_TYPE_CODING_FPGA_QP_ERROR = 0x21 64 }; 65 66 enum { 67 MLX5_MODIFY_TIR_BITMASK_LRO = 0x0, 68 MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE = 0x1, 69 MLX5_MODIFY_TIR_BITMASK_HASH = 0x2, 70 MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN = 0x3 71 }; 72 73 enum { 74 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0, 75 MLX5_SET_HCA_CAP_OP_MOD_ODP = 0x2, 76 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3, 77 MLX5_SET_HCA_CAP_OP_MOD_ROCE = 0x4, 78 }; 79 80 enum { 81 MLX5_SHARED_RESOURCE_UID = 0xffff, 82 }; 83 84 enum { 85 MLX5_OBJ_TYPE_SW_ICM = 0x0008, 86 }; 87 88 enum { 89 MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM = (1ULL << MLX5_OBJ_TYPE_SW_ICM), 90 MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT = (1ULL << 11), 91 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q = (1ULL << 13), 92 }; 93 94 enum { 95 MLX5_OBJ_TYPE_GENEVE_TLV_OPT = 0x000b, 96 MLX5_OBJ_TYPE_MKEY = 0xff01, 97 MLX5_OBJ_TYPE_QP = 0xff02, 98 MLX5_OBJ_TYPE_PSV = 0xff03, 99 MLX5_OBJ_TYPE_RMP = 0xff04, 100 MLX5_OBJ_TYPE_XRC_SRQ = 0xff05, 101 MLX5_OBJ_TYPE_RQ = 0xff06, 102 MLX5_OBJ_TYPE_SQ = 0xff07, 103 MLX5_OBJ_TYPE_TIR = 0xff08, 104 MLX5_OBJ_TYPE_TIS = 0xff09, 105 MLX5_OBJ_TYPE_DCT = 0xff0a, 106 MLX5_OBJ_TYPE_XRQ = 0xff0b, 107 MLX5_OBJ_TYPE_RQT = 0xff0e, 108 MLX5_OBJ_TYPE_FLOW_COUNTER = 0xff0f, 109 MLX5_OBJ_TYPE_CQ = 0xff10, 110 }; 111 112 enum { 113 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100, 114 MLX5_CMD_OP_QUERY_ADAPTER = 0x101, 115 MLX5_CMD_OP_INIT_HCA = 0x102, 116 MLX5_CMD_OP_TEARDOWN_HCA = 0x103, 117 MLX5_CMD_OP_ENABLE_HCA = 0x104, 118 MLX5_CMD_OP_DISABLE_HCA = 0x105, 119 MLX5_CMD_OP_QUERY_PAGES = 0x107, 120 MLX5_CMD_OP_MANAGE_PAGES = 0x108, 121 MLX5_CMD_OP_SET_HCA_CAP = 0x109, 122 MLX5_CMD_OP_QUERY_ISSI = 0x10a, 123 MLX5_CMD_OP_SET_ISSI = 0x10b, 124 MLX5_CMD_OP_SET_DRIVER_VERSION = 0x10d, 125 MLX5_CMD_OP_QUERY_SF_PARTITION = 0x111, 126 MLX5_CMD_OP_ALLOC_SF = 0x113, 127 MLX5_CMD_OP_DEALLOC_SF = 0x114, 128 MLX5_CMD_OP_CREATE_MKEY = 0x200, 129 MLX5_CMD_OP_QUERY_MKEY = 0x201, 130 MLX5_CMD_OP_DESTROY_MKEY = 0x202, 131 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203, 132 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204, 133 MLX5_CMD_OP_ALLOC_MEMIC = 0x205, 134 MLX5_CMD_OP_DEALLOC_MEMIC = 0x206, 135 MLX5_CMD_OP_CREATE_EQ = 0x301, 136 MLX5_CMD_OP_DESTROY_EQ = 0x302, 137 MLX5_CMD_OP_QUERY_EQ = 0x303, 138 MLX5_CMD_OP_GEN_EQE = 0x304, 139 MLX5_CMD_OP_CREATE_CQ = 0x400, 140 MLX5_CMD_OP_DESTROY_CQ = 0x401, 141 MLX5_CMD_OP_QUERY_CQ = 0x402, 142 MLX5_CMD_OP_MODIFY_CQ = 0x403, 143 MLX5_CMD_OP_CREATE_QP = 0x500, 144 MLX5_CMD_OP_DESTROY_QP = 0x501, 145 MLX5_CMD_OP_RST2INIT_QP = 0x502, 146 MLX5_CMD_OP_INIT2RTR_QP = 0x503, 147 MLX5_CMD_OP_RTR2RTS_QP = 0x504, 148 MLX5_CMD_OP_RTS2RTS_QP = 0x505, 149 MLX5_CMD_OP_SQERR2RTS_QP = 0x506, 150 MLX5_CMD_OP_2ERR_QP = 0x507, 151 MLX5_CMD_OP_2RST_QP = 0x50a, 152 MLX5_CMD_OP_QUERY_QP = 0x50b, 153 MLX5_CMD_OP_SQD_RTS_QP = 0x50c, 154 MLX5_CMD_OP_INIT2INIT_QP = 0x50e, 155 MLX5_CMD_OP_CREATE_PSV = 0x600, 156 MLX5_CMD_OP_DESTROY_PSV = 0x601, 157 MLX5_CMD_OP_CREATE_SRQ = 0x700, 158 MLX5_CMD_OP_DESTROY_SRQ = 0x701, 159 MLX5_CMD_OP_QUERY_SRQ = 0x702, 160 MLX5_CMD_OP_ARM_RQ = 0x703, 161 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705, 162 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706, 163 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707, 164 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708, 165 MLX5_CMD_OP_CREATE_DCT = 0x710, 166 MLX5_CMD_OP_DESTROY_DCT = 0x711, 167 MLX5_CMD_OP_DRAIN_DCT = 0x712, 168 MLX5_CMD_OP_QUERY_DCT = 0x713, 169 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714, 170 MLX5_CMD_OP_CREATE_XRQ = 0x717, 171 MLX5_CMD_OP_DESTROY_XRQ = 0x718, 172 MLX5_CMD_OP_QUERY_XRQ = 0x719, 173 MLX5_CMD_OP_ARM_XRQ = 0x71a, 174 MLX5_CMD_OP_QUERY_XRQ_DC_PARAMS_ENTRY = 0x725, 175 MLX5_CMD_OP_SET_XRQ_DC_PARAMS_ENTRY = 0x726, 176 MLX5_CMD_OP_QUERY_XRQ_ERROR_PARAMS = 0x727, 177 MLX5_CMD_OP_RELEASE_XRQ_ERROR = 0x729, 178 MLX5_CMD_OP_MODIFY_XRQ = 0x72a, 179 MLX5_CMD_OP_QUERY_ESW_FUNCTIONS = 0x740, 180 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750, 181 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751, 182 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752, 183 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753, 184 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754, 185 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755, 186 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760, 187 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761, 188 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762, 189 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763, 190 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764, 191 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765, 192 MLX5_CMD_OP_QUERY_VNIC_ENV = 0x76f, 193 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770, 194 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771, 195 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772, 196 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773, 197 MLX5_CMD_OP_SET_MONITOR_COUNTER = 0x774, 198 MLX5_CMD_OP_ARM_MONITOR_COUNTER = 0x775, 199 MLX5_CMD_OP_SET_PP_RATE_LIMIT = 0x780, 200 MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781, 201 MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT = 0x782, 202 MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT = 0x783, 203 MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT = 0x784, 204 MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT = 0x785, 205 MLX5_CMD_OP_CREATE_QOS_PARA_VPORT = 0x786, 206 MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT = 0x787, 207 MLX5_CMD_OP_ALLOC_PD = 0x800, 208 MLX5_CMD_OP_DEALLOC_PD = 0x801, 209 MLX5_CMD_OP_ALLOC_UAR = 0x802, 210 MLX5_CMD_OP_DEALLOC_UAR = 0x803, 211 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804, 212 MLX5_CMD_OP_ACCESS_REG = 0x805, 213 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806, 214 MLX5_CMD_OP_DETACH_FROM_MCG = 0x807, 215 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a, 216 MLX5_CMD_OP_MAD_IFC = 0x50d, 217 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b, 218 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c, 219 MLX5_CMD_OP_NOP = 0x80d, 220 MLX5_CMD_OP_ALLOC_XRCD = 0x80e, 221 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f, 222 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816, 223 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817, 224 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822, 225 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823, 226 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824, 227 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825, 228 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826, 229 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827, 230 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828, 231 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829, 232 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a, 233 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b, 234 MLX5_CMD_OP_SET_WOL_ROL = 0x830, 235 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831, 236 MLX5_CMD_OP_CREATE_LAG = 0x840, 237 MLX5_CMD_OP_MODIFY_LAG = 0x841, 238 MLX5_CMD_OP_QUERY_LAG = 0x842, 239 MLX5_CMD_OP_DESTROY_LAG = 0x843, 240 MLX5_CMD_OP_CREATE_VPORT_LAG = 0x844, 241 MLX5_CMD_OP_DESTROY_VPORT_LAG = 0x845, 242 MLX5_CMD_OP_CREATE_TIR = 0x900, 243 MLX5_CMD_OP_MODIFY_TIR = 0x901, 244 MLX5_CMD_OP_DESTROY_TIR = 0x902, 245 MLX5_CMD_OP_QUERY_TIR = 0x903, 246 MLX5_CMD_OP_CREATE_SQ = 0x904, 247 MLX5_CMD_OP_MODIFY_SQ = 0x905, 248 MLX5_CMD_OP_DESTROY_SQ = 0x906, 249 MLX5_CMD_OP_QUERY_SQ = 0x907, 250 MLX5_CMD_OP_CREATE_RQ = 0x908, 251 MLX5_CMD_OP_MODIFY_RQ = 0x909, 252 MLX5_CMD_OP_SET_DELAY_DROP_PARAMS = 0x910, 253 MLX5_CMD_OP_DESTROY_RQ = 0x90a, 254 MLX5_CMD_OP_QUERY_RQ = 0x90b, 255 MLX5_CMD_OP_CREATE_RMP = 0x90c, 256 MLX5_CMD_OP_MODIFY_RMP = 0x90d, 257 MLX5_CMD_OP_DESTROY_RMP = 0x90e, 258 MLX5_CMD_OP_QUERY_RMP = 0x90f, 259 MLX5_CMD_OP_CREATE_TIS = 0x912, 260 MLX5_CMD_OP_MODIFY_TIS = 0x913, 261 MLX5_CMD_OP_DESTROY_TIS = 0x914, 262 MLX5_CMD_OP_QUERY_TIS = 0x915, 263 MLX5_CMD_OP_CREATE_RQT = 0x916, 264 MLX5_CMD_OP_MODIFY_RQT = 0x917, 265 MLX5_CMD_OP_DESTROY_RQT = 0x918, 266 MLX5_CMD_OP_QUERY_RQT = 0x919, 267 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f, 268 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930, 269 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931, 270 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932, 271 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933, 272 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934, 273 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935, 274 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936, 275 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937, 276 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938, 277 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939, 278 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a, 279 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b, 280 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c, 281 MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT = 0x93d, 282 MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT = 0x93e, 283 MLX5_CMD_OP_QUERY_PACKET_REFORMAT_CONTEXT = 0x93f, 284 MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT = 0x940, 285 MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941, 286 MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT = 0x942, 287 MLX5_CMD_OP_FPGA_CREATE_QP = 0x960, 288 MLX5_CMD_OP_FPGA_MODIFY_QP = 0x961, 289 MLX5_CMD_OP_FPGA_QUERY_QP = 0x962, 290 MLX5_CMD_OP_FPGA_DESTROY_QP = 0x963, 291 MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS = 0x964, 292 MLX5_CMD_OP_CREATE_GENERAL_OBJECT = 0xa00, 293 MLX5_CMD_OP_MODIFY_GENERAL_OBJECT = 0xa01, 294 MLX5_CMD_OP_QUERY_GENERAL_OBJECT = 0xa02, 295 MLX5_CMD_OP_DESTROY_GENERAL_OBJECT = 0xa03, 296 MLX5_CMD_OP_CREATE_UCTX = 0xa04, 297 MLX5_CMD_OP_DESTROY_UCTX = 0xa06, 298 MLX5_CMD_OP_CREATE_UMEM = 0xa08, 299 MLX5_CMD_OP_DESTROY_UMEM = 0xa0a, 300 MLX5_CMD_OP_SYNC_STEERING = 0xb00, 301 MLX5_CMD_OP_MAX 302 }; 303 304 /* Valid range for general commands that don't work over an object */ 305 enum { 306 MLX5_CMD_OP_GENERAL_START = 0xb00, 307 MLX5_CMD_OP_GENERAL_END = 0xd00, 308 }; 309 310 struct mlx5_ifc_flow_table_fields_supported_bits { 311 u8 outer_dmac[0x1]; 312 u8 outer_smac[0x1]; 313 u8 outer_ether_type[0x1]; 314 u8 outer_ip_version[0x1]; 315 u8 outer_first_prio[0x1]; 316 u8 outer_first_cfi[0x1]; 317 u8 outer_first_vid[0x1]; 318 u8 outer_ipv4_ttl[0x1]; 319 u8 outer_second_prio[0x1]; 320 u8 outer_second_cfi[0x1]; 321 u8 outer_second_vid[0x1]; 322 u8 reserved_at_b[0x1]; 323 u8 outer_sip[0x1]; 324 u8 outer_dip[0x1]; 325 u8 outer_frag[0x1]; 326 u8 outer_ip_protocol[0x1]; 327 u8 outer_ip_ecn[0x1]; 328 u8 outer_ip_dscp[0x1]; 329 u8 outer_udp_sport[0x1]; 330 u8 outer_udp_dport[0x1]; 331 u8 outer_tcp_sport[0x1]; 332 u8 outer_tcp_dport[0x1]; 333 u8 outer_tcp_flags[0x1]; 334 u8 outer_gre_protocol[0x1]; 335 u8 outer_gre_key[0x1]; 336 u8 outer_vxlan_vni[0x1]; 337 u8 outer_geneve_vni[0x1]; 338 u8 outer_geneve_oam[0x1]; 339 u8 outer_geneve_protocol_type[0x1]; 340 u8 outer_geneve_opt_len[0x1]; 341 u8 reserved_at_1e[0x1]; 342 u8 source_eswitch_port[0x1]; 343 344 u8 inner_dmac[0x1]; 345 u8 inner_smac[0x1]; 346 u8 inner_ether_type[0x1]; 347 u8 inner_ip_version[0x1]; 348 u8 inner_first_prio[0x1]; 349 u8 inner_first_cfi[0x1]; 350 u8 inner_first_vid[0x1]; 351 u8 reserved_at_27[0x1]; 352 u8 inner_second_prio[0x1]; 353 u8 inner_second_cfi[0x1]; 354 u8 inner_second_vid[0x1]; 355 u8 reserved_at_2b[0x1]; 356 u8 inner_sip[0x1]; 357 u8 inner_dip[0x1]; 358 u8 inner_frag[0x1]; 359 u8 inner_ip_protocol[0x1]; 360 u8 inner_ip_ecn[0x1]; 361 u8 inner_ip_dscp[0x1]; 362 u8 inner_udp_sport[0x1]; 363 u8 inner_udp_dport[0x1]; 364 u8 inner_tcp_sport[0x1]; 365 u8 inner_tcp_dport[0x1]; 366 u8 inner_tcp_flags[0x1]; 367 u8 reserved_at_37[0x9]; 368 369 u8 geneve_tlv_option_0_data[0x1]; 370 u8 reserved_at_41[0x4]; 371 u8 outer_first_mpls_over_udp[0x4]; 372 u8 outer_first_mpls_over_gre[0x4]; 373 u8 inner_first_mpls[0x4]; 374 u8 outer_first_mpls[0x4]; 375 u8 reserved_at_55[0x2]; 376 u8 outer_esp_spi[0x1]; 377 u8 reserved_at_58[0x2]; 378 u8 bth_dst_qp[0x1]; 379 u8 reserved_at_5b[0x5]; 380 381 u8 reserved_at_60[0x18]; 382 u8 metadata_reg_c_7[0x1]; 383 u8 metadata_reg_c_6[0x1]; 384 u8 metadata_reg_c_5[0x1]; 385 u8 metadata_reg_c_4[0x1]; 386 u8 metadata_reg_c_3[0x1]; 387 u8 metadata_reg_c_2[0x1]; 388 u8 metadata_reg_c_1[0x1]; 389 u8 metadata_reg_c_0[0x1]; 390 }; 391 392 struct mlx5_ifc_flow_table_prop_layout_bits { 393 u8 ft_support[0x1]; 394 u8 reserved_at_1[0x1]; 395 u8 flow_counter[0x1]; 396 u8 flow_modify_en[0x1]; 397 u8 modify_root[0x1]; 398 u8 identified_miss_table_mode[0x1]; 399 u8 flow_table_modify[0x1]; 400 u8 reformat[0x1]; 401 u8 decap[0x1]; 402 u8 reserved_at_9[0x1]; 403 u8 pop_vlan[0x1]; 404 u8 push_vlan[0x1]; 405 u8 reserved_at_c[0x1]; 406 u8 pop_vlan_2[0x1]; 407 u8 push_vlan_2[0x1]; 408 u8 reformat_and_vlan_action[0x1]; 409 u8 reserved_at_10[0x1]; 410 u8 sw_owner[0x1]; 411 u8 reformat_l3_tunnel_to_l2[0x1]; 412 u8 reformat_l2_to_l3_tunnel[0x1]; 413 u8 reformat_and_modify_action[0x1]; 414 u8 ignore_flow_level[0x1]; 415 u8 reserved_at_16[0x1]; 416 u8 table_miss_action_domain[0x1]; 417 u8 termination_table[0x1]; 418 u8 reformat_and_fwd_to_table[0x1]; 419 u8 reserved_at_1a[0x2]; 420 u8 ipsec_encrypt[0x1]; 421 u8 ipsec_decrypt[0x1]; 422 u8 reserved_at_1e[0x2]; 423 424 u8 termination_table_raw_traffic[0x1]; 425 u8 reserved_at_21[0x1]; 426 u8 log_max_ft_size[0x6]; 427 u8 log_max_modify_header_context[0x8]; 428 u8 max_modify_header_actions[0x8]; 429 u8 max_ft_level[0x8]; 430 431 u8 reserved_at_40[0x20]; 432 433 u8 reserved_at_60[0x18]; 434 u8 log_max_ft_num[0x8]; 435 436 u8 reserved_at_80[0x18]; 437 u8 log_max_destination[0x8]; 438 439 u8 log_max_flow_counter[0x8]; 440 u8 reserved_at_a8[0x10]; 441 u8 log_max_flow[0x8]; 442 443 u8 reserved_at_c0[0x40]; 444 445 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support; 446 447 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support; 448 }; 449 450 struct mlx5_ifc_odp_per_transport_service_cap_bits { 451 u8 send[0x1]; 452 u8 receive[0x1]; 453 u8 write[0x1]; 454 u8 read[0x1]; 455 u8 atomic[0x1]; 456 u8 srq_receive[0x1]; 457 u8 reserved_at_6[0x1a]; 458 }; 459 460 struct mlx5_ifc_fte_match_set_lyr_2_4_bits { 461 u8 smac_47_16[0x20]; 462 463 u8 smac_15_0[0x10]; 464 u8 ethertype[0x10]; 465 466 u8 dmac_47_16[0x20]; 467 468 u8 dmac_15_0[0x10]; 469 u8 first_prio[0x3]; 470 u8 first_cfi[0x1]; 471 u8 first_vid[0xc]; 472 473 u8 ip_protocol[0x8]; 474 u8 ip_dscp[0x6]; 475 u8 ip_ecn[0x2]; 476 u8 cvlan_tag[0x1]; 477 u8 svlan_tag[0x1]; 478 u8 frag[0x1]; 479 u8 ip_version[0x4]; 480 u8 tcp_flags[0x9]; 481 482 u8 tcp_sport[0x10]; 483 u8 tcp_dport[0x10]; 484 485 u8 reserved_at_c0[0x18]; 486 u8 ttl_hoplimit[0x8]; 487 488 u8 udp_sport[0x10]; 489 u8 udp_dport[0x10]; 490 491 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6; 492 493 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6; 494 }; 495 496 struct mlx5_ifc_nvgre_key_bits { 497 u8 hi[0x18]; 498 u8 lo[0x8]; 499 }; 500 501 union mlx5_ifc_gre_key_bits { 502 struct mlx5_ifc_nvgre_key_bits nvgre; 503 u8 key[0x20]; 504 }; 505 506 struct mlx5_ifc_fte_match_set_misc_bits { 507 u8 gre_c_present[0x1]; 508 u8 reserved_at_1[0x1]; 509 u8 gre_k_present[0x1]; 510 u8 gre_s_present[0x1]; 511 u8 source_vhca_port[0x4]; 512 u8 source_sqn[0x18]; 513 514 u8 source_eswitch_owner_vhca_id[0x10]; 515 u8 source_port[0x10]; 516 517 u8 outer_second_prio[0x3]; 518 u8 outer_second_cfi[0x1]; 519 u8 outer_second_vid[0xc]; 520 u8 inner_second_prio[0x3]; 521 u8 inner_second_cfi[0x1]; 522 u8 inner_second_vid[0xc]; 523 524 u8 outer_second_cvlan_tag[0x1]; 525 u8 inner_second_cvlan_tag[0x1]; 526 u8 outer_second_svlan_tag[0x1]; 527 u8 inner_second_svlan_tag[0x1]; 528 u8 reserved_at_64[0xc]; 529 u8 gre_protocol[0x10]; 530 531 union mlx5_ifc_gre_key_bits gre_key; 532 533 u8 vxlan_vni[0x18]; 534 u8 reserved_at_b8[0x8]; 535 536 u8 geneve_vni[0x18]; 537 u8 reserved_at_d8[0x7]; 538 u8 geneve_oam[0x1]; 539 540 u8 reserved_at_e0[0xc]; 541 u8 outer_ipv6_flow_label[0x14]; 542 543 u8 reserved_at_100[0xc]; 544 u8 inner_ipv6_flow_label[0x14]; 545 546 u8 reserved_at_120[0xa]; 547 u8 geneve_opt_len[0x6]; 548 u8 geneve_protocol_type[0x10]; 549 550 u8 reserved_at_140[0x8]; 551 u8 bth_dst_qp[0x18]; 552 u8 reserved_at_160[0x20]; 553 u8 outer_esp_spi[0x20]; 554 u8 reserved_at_1a0[0x60]; 555 }; 556 557 struct mlx5_ifc_fte_match_mpls_bits { 558 u8 mpls_label[0x14]; 559 u8 mpls_exp[0x3]; 560 u8 mpls_s_bos[0x1]; 561 u8 mpls_ttl[0x8]; 562 }; 563 564 struct mlx5_ifc_fte_match_set_misc2_bits { 565 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls; 566 567 struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls; 568 569 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre; 570 571 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp; 572 573 u8 metadata_reg_c_7[0x20]; 574 575 u8 metadata_reg_c_6[0x20]; 576 577 u8 metadata_reg_c_5[0x20]; 578 579 u8 metadata_reg_c_4[0x20]; 580 581 u8 metadata_reg_c_3[0x20]; 582 583 u8 metadata_reg_c_2[0x20]; 584 585 u8 metadata_reg_c_1[0x20]; 586 587 u8 metadata_reg_c_0[0x20]; 588 589 u8 metadata_reg_a[0x20]; 590 591 u8 reserved_at_1a0[0x60]; 592 }; 593 594 struct mlx5_ifc_fte_match_set_misc3_bits { 595 u8 inner_tcp_seq_num[0x20]; 596 597 u8 outer_tcp_seq_num[0x20]; 598 599 u8 inner_tcp_ack_num[0x20]; 600 601 u8 outer_tcp_ack_num[0x20]; 602 603 u8 reserved_at_80[0x8]; 604 u8 outer_vxlan_gpe_vni[0x18]; 605 606 u8 outer_vxlan_gpe_next_protocol[0x8]; 607 u8 outer_vxlan_gpe_flags[0x8]; 608 u8 reserved_at_b0[0x10]; 609 610 u8 icmp_header_data[0x20]; 611 612 u8 icmpv6_header_data[0x20]; 613 614 u8 icmp_type[0x8]; 615 u8 icmp_code[0x8]; 616 u8 icmpv6_type[0x8]; 617 u8 icmpv6_code[0x8]; 618 619 u8 geneve_tlv_option_0_data[0x20]; 620 621 u8 reserved_at_140[0xc0]; 622 }; 623 624 struct mlx5_ifc_cmd_pas_bits { 625 u8 pa_h[0x20]; 626 627 u8 pa_l[0x14]; 628 u8 reserved_at_34[0xc]; 629 }; 630 631 struct mlx5_ifc_uint64_bits { 632 u8 hi[0x20]; 633 634 u8 lo[0x20]; 635 }; 636 637 enum { 638 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0, 639 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7, 640 MLX5_ADS_STAT_RATE_10GBPS = 0x8, 641 MLX5_ADS_STAT_RATE_30GBPS = 0x9, 642 MLX5_ADS_STAT_RATE_5GBPS = 0xa, 643 MLX5_ADS_STAT_RATE_20GBPS = 0xb, 644 MLX5_ADS_STAT_RATE_40GBPS = 0xc, 645 MLX5_ADS_STAT_RATE_60GBPS = 0xd, 646 MLX5_ADS_STAT_RATE_80GBPS = 0xe, 647 MLX5_ADS_STAT_RATE_120GBPS = 0xf, 648 }; 649 650 struct mlx5_ifc_ads_bits { 651 u8 fl[0x1]; 652 u8 free_ar[0x1]; 653 u8 reserved_at_2[0xe]; 654 u8 pkey_index[0x10]; 655 656 u8 reserved_at_20[0x8]; 657 u8 grh[0x1]; 658 u8 mlid[0x7]; 659 u8 rlid[0x10]; 660 661 u8 ack_timeout[0x5]; 662 u8 reserved_at_45[0x3]; 663 u8 src_addr_index[0x8]; 664 u8 reserved_at_50[0x4]; 665 u8 stat_rate[0x4]; 666 u8 hop_limit[0x8]; 667 668 u8 reserved_at_60[0x4]; 669 u8 tclass[0x8]; 670 u8 flow_label[0x14]; 671 672 u8 rgid_rip[16][0x8]; 673 674 u8 reserved_at_100[0x4]; 675 u8 f_dscp[0x1]; 676 u8 f_ecn[0x1]; 677 u8 reserved_at_106[0x1]; 678 u8 f_eth_prio[0x1]; 679 u8 ecn[0x2]; 680 u8 dscp[0x6]; 681 u8 udp_sport[0x10]; 682 683 u8 dei_cfi[0x1]; 684 u8 eth_prio[0x3]; 685 u8 sl[0x4]; 686 u8 vhca_port_num[0x8]; 687 u8 rmac_47_32[0x10]; 688 689 u8 rmac_31_0[0x20]; 690 }; 691 692 struct mlx5_ifc_flow_table_nic_cap_bits { 693 u8 nic_rx_multi_path_tirs[0x1]; 694 u8 nic_rx_multi_path_tirs_fts[0x1]; 695 u8 allow_sniffer_and_nic_rx_shared_tir[0x1]; 696 u8 reserved_at_3[0x4]; 697 u8 sw_owner_reformat_supported[0x1]; 698 u8 reserved_at_8[0x18]; 699 700 u8 encap_general_header[0x1]; 701 u8 reserved_at_21[0xa]; 702 u8 log_max_packet_reformat_context[0x5]; 703 u8 reserved_at_30[0x6]; 704 u8 max_encap_header_size[0xa]; 705 u8 reserved_at_40[0x1c0]; 706 707 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive; 708 709 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_rdma; 710 711 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer; 712 713 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit; 714 715 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_rdma; 716 717 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer; 718 719 u8 reserved_at_e00[0x1200]; 720 721 u8 sw_steering_nic_rx_action_drop_icm_address[0x40]; 722 723 u8 sw_steering_nic_tx_action_drop_icm_address[0x40]; 724 725 u8 sw_steering_nic_tx_action_allow_icm_address[0x40]; 726 727 u8 reserved_at_20c0[0x5f40]; 728 }; 729 730 enum { 731 MLX5_FDB_TO_VPORT_REG_C_0 = 0x01, 732 MLX5_FDB_TO_VPORT_REG_C_1 = 0x02, 733 MLX5_FDB_TO_VPORT_REG_C_2 = 0x04, 734 MLX5_FDB_TO_VPORT_REG_C_3 = 0x08, 735 MLX5_FDB_TO_VPORT_REG_C_4 = 0x10, 736 MLX5_FDB_TO_VPORT_REG_C_5 = 0x20, 737 MLX5_FDB_TO_VPORT_REG_C_6 = 0x40, 738 MLX5_FDB_TO_VPORT_REG_C_7 = 0x80, 739 }; 740 741 struct mlx5_ifc_flow_table_eswitch_cap_bits { 742 u8 fdb_to_vport_reg_c_id[0x8]; 743 u8 reserved_at_8[0xd]; 744 u8 fdb_modify_header_fwd_to_table[0x1]; 745 u8 reserved_at_16[0x1]; 746 u8 flow_source[0x1]; 747 u8 reserved_at_18[0x2]; 748 u8 multi_fdb_encap[0x1]; 749 u8 egress_acl_forward_to_vport[0x1]; 750 u8 fdb_multi_path_to_table[0x1]; 751 u8 reserved_at_1d[0x3]; 752 753 u8 reserved_at_20[0x1e0]; 754 755 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb; 756 757 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress; 758 759 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress; 760 761 u8 reserved_at_800[0x1000]; 762 763 u8 sw_steering_fdb_action_drop_icm_address_rx[0x40]; 764 765 u8 sw_steering_fdb_action_drop_icm_address_tx[0x40]; 766 767 u8 sw_steering_uplink_icm_address_rx[0x40]; 768 769 u8 sw_steering_uplink_icm_address_tx[0x40]; 770 771 u8 reserved_at_1900[0x6700]; 772 }; 773 774 enum { 775 MLX5_COUNTER_SOURCE_ESWITCH = 0x0, 776 MLX5_COUNTER_FLOW_ESWITCH = 0x1, 777 }; 778 779 struct mlx5_ifc_e_switch_cap_bits { 780 u8 vport_svlan_strip[0x1]; 781 u8 vport_cvlan_strip[0x1]; 782 u8 vport_svlan_insert[0x1]; 783 u8 vport_cvlan_insert_if_not_exist[0x1]; 784 u8 vport_cvlan_insert_overwrite[0x1]; 785 u8 reserved_at_5[0x3]; 786 u8 esw_uplink_ingress_acl[0x1]; 787 u8 reserved_at_9[0x10]; 788 u8 esw_functions_changed[0x1]; 789 u8 reserved_at_1a[0x1]; 790 u8 ecpf_vport_exists[0x1]; 791 u8 counter_eswitch_affinity[0x1]; 792 u8 merged_eswitch[0x1]; 793 u8 nic_vport_node_guid_modify[0x1]; 794 u8 nic_vport_port_guid_modify[0x1]; 795 796 u8 vxlan_encap_decap[0x1]; 797 u8 nvgre_encap_decap[0x1]; 798 u8 reserved_at_22[0x1]; 799 u8 log_max_fdb_encap_uplink[0x5]; 800 u8 reserved_at_21[0x3]; 801 u8 log_max_packet_reformat_context[0x5]; 802 u8 reserved_2b[0x6]; 803 u8 max_encap_header_size[0xa]; 804 805 u8 reserved_at_40[0xb]; 806 u8 log_max_esw_sf[0x5]; 807 u8 esw_sf_base_id[0x10]; 808 809 u8 reserved_at_60[0x7a0]; 810 811 }; 812 813 struct mlx5_ifc_qos_cap_bits { 814 u8 packet_pacing[0x1]; 815 u8 esw_scheduling[0x1]; 816 u8 esw_bw_share[0x1]; 817 u8 esw_rate_limit[0x1]; 818 u8 reserved_at_4[0x1]; 819 u8 packet_pacing_burst_bound[0x1]; 820 u8 packet_pacing_typical_size[0x1]; 821 u8 reserved_at_7[0x4]; 822 u8 packet_pacing_uid[0x1]; 823 u8 reserved_at_c[0x14]; 824 825 u8 reserved_at_20[0x20]; 826 827 u8 packet_pacing_max_rate[0x20]; 828 829 u8 packet_pacing_min_rate[0x20]; 830 831 u8 reserved_at_80[0x10]; 832 u8 packet_pacing_rate_table_size[0x10]; 833 834 u8 esw_element_type[0x10]; 835 u8 esw_tsar_type[0x10]; 836 837 u8 reserved_at_c0[0x10]; 838 u8 max_qos_para_vport[0x10]; 839 840 u8 max_tsar_bw_share[0x20]; 841 842 u8 reserved_at_100[0x700]; 843 }; 844 845 struct mlx5_ifc_debug_cap_bits { 846 u8 core_dump_general[0x1]; 847 u8 core_dump_qp[0x1]; 848 u8 reserved_at_2[0x7]; 849 u8 resource_dump[0x1]; 850 u8 reserved_at_a[0x16]; 851 852 u8 reserved_at_20[0x2]; 853 u8 stall_detect[0x1]; 854 u8 reserved_at_23[0x1d]; 855 856 u8 reserved_at_40[0x7c0]; 857 }; 858 859 struct mlx5_ifc_per_protocol_networking_offload_caps_bits { 860 u8 csum_cap[0x1]; 861 u8 vlan_cap[0x1]; 862 u8 lro_cap[0x1]; 863 u8 lro_psh_flag[0x1]; 864 u8 lro_time_stamp[0x1]; 865 u8 reserved_at_5[0x2]; 866 u8 wqe_vlan_insert[0x1]; 867 u8 self_lb_en_modifiable[0x1]; 868 u8 reserved_at_9[0x2]; 869 u8 max_lso_cap[0x5]; 870 u8 multi_pkt_send_wqe[0x2]; 871 u8 wqe_inline_mode[0x2]; 872 u8 rss_ind_tbl_cap[0x4]; 873 u8 reg_umr_sq[0x1]; 874 u8 scatter_fcs[0x1]; 875 u8 enhanced_multi_pkt_send_wqe[0x1]; 876 u8 tunnel_lso_const_out_ip_id[0x1]; 877 u8 reserved_at_1c[0x2]; 878 u8 tunnel_stateless_gre[0x1]; 879 u8 tunnel_stateless_vxlan[0x1]; 880 881 u8 swp[0x1]; 882 u8 swp_csum[0x1]; 883 u8 swp_lso[0x1]; 884 u8 cqe_checksum_full[0x1]; 885 u8 tunnel_stateless_geneve_tx[0x1]; 886 u8 tunnel_stateless_mpls_over_udp[0x1]; 887 u8 tunnel_stateless_mpls_over_gre[0x1]; 888 u8 tunnel_stateless_vxlan_gpe[0x1]; 889 u8 tunnel_stateless_ipv4_over_vxlan[0x1]; 890 u8 tunnel_stateless_ip_over_ip[0x1]; 891 u8 insert_trailer[0x1]; 892 u8 reserved_at_2b[0x5]; 893 u8 max_vxlan_udp_ports[0x8]; 894 u8 reserved_at_38[0x6]; 895 u8 max_geneve_opt_len[0x1]; 896 u8 tunnel_stateless_geneve_rx[0x1]; 897 898 u8 reserved_at_40[0x10]; 899 u8 lro_min_mss_size[0x10]; 900 901 u8 reserved_at_60[0x120]; 902 903 u8 lro_timer_supported_periods[4][0x20]; 904 905 u8 reserved_at_200[0x600]; 906 }; 907 908 struct mlx5_ifc_roce_cap_bits { 909 u8 roce_apm[0x1]; 910 u8 reserved_at_1[0x3]; 911 u8 sw_r_roce_src_udp_port[0x1]; 912 u8 reserved_at_5[0x1b]; 913 914 u8 reserved_at_20[0x60]; 915 916 u8 reserved_at_80[0xc]; 917 u8 l3_type[0x4]; 918 u8 reserved_at_90[0x8]; 919 u8 roce_version[0x8]; 920 921 u8 reserved_at_a0[0x10]; 922 u8 r_roce_dest_udp_port[0x10]; 923 924 u8 r_roce_max_src_udp_port[0x10]; 925 u8 r_roce_min_src_udp_port[0x10]; 926 927 u8 reserved_at_e0[0x10]; 928 u8 roce_address_table_size[0x10]; 929 930 u8 reserved_at_100[0x700]; 931 }; 932 933 struct mlx5_ifc_sync_steering_in_bits { 934 u8 opcode[0x10]; 935 u8 uid[0x10]; 936 937 u8 reserved_at_20[0x10]; 938 u8 op_mod[0x10]; 939 940 u8 reserved_at_40[0xc0]; 941 }; 942 943 struct mlx5_ifc_sync_steering_out_bits { 944 u8 status[0x8]; 945 u8 reserved_at_8[0x18]; 946 947 u8 syndrome[0x20]; 948 949 u8 reserved_at_40[0x40]; 950 }; 951 952 struct mlx5_ifc_device_mem_cap_bits { 953 u8 memic[0x1]; 954 u8 reserved_at_1[0x1f]; 955 956 u8 reserved_at_20[0xb]; 957 u8 log_min_memic_alloc_size[0x5]; 958 u8 reserved_at_30[0x8]; 959 u8 log_max_memic_addr_alignment[0x8]; 960 961 u8 memic_bar_start_addr[0x40]; 962 963 u8 memic_bar_size[0x20]; 964 965 u8 max_memic_size[0x20]; 966 967 u8 steering_sw_icm_start_address[0x40]; 968 969 u8 reserved_at_100[0x8]; 970 u8 log_header_modify_sw_icm_size[0x8]; 971 u8 reserved_at_110[0x2]; 972 u8 log_sw_icm_alloc_granularity[0x6]; 973 u8 log_steering_sw_icm_size[0x8]; 974 975 u8 reserved_at_120[0x20]; 976 977 u8 header_modify_sw_icm_start_address[0x40]; 978 979 u8 reserved_at_180[0x680]; 980 }; 981 982 struct mlx5_ifc_device_event_cap_bits { 983 u8 user_affiliated_events[4][0x40]; 984 985 u8 user_unaffiliated_events[4][0x40]; 986 }; 987 988 struct mlx5_ifc_device_virtio_emulation_cap_bits { 989 u8 reserved_at_0[0x20]; 990 991 u8 reserved_at_20[0x13]; 992 u8 log_doorbell_stride[0x5]; 993 u8 reserved_at_38[0x3]; 994 u8 log_doorbell_bar_size[0x5]; 995 996 u8 doorbell_bar_offset[0x40]; 997 998 u8 reserved_at_80[0x780]; 999 }; 1000 1001 enum { 1002 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0, 1003 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2, 1004 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4, 1005 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8, 1006 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10, 1007 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20, 1008 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40, 1009 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80, 1010 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100, 1011 }; 1012 1013 enum { 1014 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1, 1015 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2, 1016 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4, 1017 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8, 1018 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10, 1019 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20, 1020 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40, 1021 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80, 1022 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100, 1023 }; 1024 1025 struct mlx5_ifc_atomic_caps_bits { 1026 u8 reserved_at_0[0x40]; 1027 1028 u8 atomic_req_8B_endianness_mode[0x2]; 1029 u8 reserved_at_42[0x4]; 1030 u8 supported_atomic_req_8B_endianness_mode_1[0x1]; 1031 1032 u8 reserved_at_47[0x19]; 1033 1034 u8 reserved_at_60[0x20]; 1035 1036 u8 reserved_at_80[0x10]; 1037 u8 atomic_operations[0x10]; 1038 1039 u8 reserved_at_a0[0x10]; 1040 u8 atomic_size_qp[0x10]; 1041 1042 u8 reserved_at_c0[0x10]; 1043 u8 atomic_size_dc[0x10]; 1044 1045 u8 reserved_at_e0[0x720]; 1046 }; 1047 1048 struct mlx5_ifc_odp_cap_bits { 1049 u8 reserved_at_0[0x40]; 1050 1051 u8 sig[0x1]; 1052 u8 reserved_at_41[0x1f]; 1053 1054 u8 reserved_at_60[0x20]; 1055 1056 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps; 1057 1058 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps; 1059 1060 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps; 1061 1062 struct mlx5_ifc_odp_per_transport_service_cap_bits xrc_odp_caps; 1063 1064 struct mlx5_ifc_odp_per_transport_service_cap_bits dc_odp_caps; 1065 1066 u8 reserved_at_120[0x6E0]; 1067 }; 1068 1069 struct mlx5_ifc_calc_op { 1070 u8 reserved_at_0[0x10]; 1071 u8 reserved_at_10[0x9]; 1072 u8 op_swap_endianness[0x1]; 1073 u8 op_min[0x1]; 1074 u8 op_xor[0x1]; 1075 u8 op_or[0x1]; 1076 u8 op_and[0x1]; 1077 u8 op_max[0x1]; 1078 u8 op_add[0x1]; 1079 }; 1080 1081 struct mlx5_ifc_vector_calc_cap_bits { 1082 u8 calc_matrix[0x1]; 1083 u8 reserved_at_1[0x1f]; 1084 u8 reserved_at_20[0x8]; 1085 u8 max_vec_count[0x8]; 1086 u8 reserved_at_30[0xd]; 1087 u8 max_chunk_size[0x3]; 1088 struct mlx5_ifc_calc_op calc0; 1089 struct mlx5_ifc_calc_op calc1; 1090 struct mlx5_ifc_calc_op calc2; 1091 struct mlx5_ifc_calc_op calc3; 1092 1093 u8 reserved_at_c0[0x720]; 1094 }; 1095 1096 struct mlx5_ifc_tls_cap_bits { 1097 u8 tls_1_2_aes_gcm_128[0x1]; 1098 u8 tls_1_3_aes_gcm_128[0x1]; 1099 u8 tls_1_2_aes_gcm_256[0x1]; 1100 u8 tls_1_3_aes_gcm_256[0x1]; 1101 u8 reserved_at_4[0x1c]; 1102 1103 u8 reserved_at_20[0x7e0]; 1104 }; 1105 1106 struct mlx5_ifc_ipsec_cap_bits { 1107 u8 ipsec_full_offload[0x1]; 1108 u8 ipsec_crypto_offload[0x1]; 1109 u8 ipsec_esn[0x1]; 1110 u8 ipsec_crypto_esp_aes_gcm_256_encrypt[0x1]; 1111 u8 ipsec_crypto_esp_aes_gcm_128_encrypt[0x1]; 1112 u8 ipsec_crypto_esp_aes_gcm_256_decrypt[0x1]; 1113 u8 ipsec_crypto_esp_aes_gcm_128_decrypt[0x1]; 1114 u8 reserved_at_7[0x4]; 1115 u8 log_max_ipsec_offload[0x5]; 1116 u8 reserved_at_10[0x10]; 1117 1118 u8 min_log_ipsec_full_replay_window[0x8]; 1119 u8 max_log_ipsec_full_replay_window[0x8]; 1120 u8 reserved_at_30[0x7d0]; 1121 }; 1122 1123 enum { 1124 MLX5_WQ_TYPE_LINKED_LIST = 0x0, 1125 MLX5_WQ_TYPE_CYCLIC = 0x1, 1126 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2, 1127 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3, 1128 }; 1129 1130 enum { 1131 MLX5_WQ_END_PAD_MODE_NONE = 0x0, 1132 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1, 1133 }; 1134 1135 enum { 1136 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0, 1137 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1, 1138 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2, 1139 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3, 1140 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4, 1141 }; 1142 1143 enum { 1144 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0, 1145 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1, 1146 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2, 1147 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3, 1148 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4, 1149 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5, 1150 }; 1151 1152 enum { 1153 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0, 1154 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1, 1155 }; 1156 1157 enum { 1158 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0, 1159 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1, 1160 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3, 1161 }; 1162 1163 enum { 1164 MLX5_CAP_PORT_TYPE_IB = 0x0, 1165 MLX5_CAP_PORT_TYPE_ETH = 0x1, 1166 }; 1167 1168 enum { 1169 MLX5_CAP_UMR_FENCE_STRONG = 0x0, 1170 MLX5_CAP_UMR_FENCE_SMALL = 0x1, 1171 MLX5_CAP_UMR_FENCE_NONE = 0x2, 1172 }; 1173 1174 enum { 1175 MLX5_FLEX_PARSER_GENEVE_ENABLED = 1 << 3, 1176 MLX5_FLEX_PARSER_VXLAN_GPE_ENABLED = 1 << 7, 1177 MLX5_FLEX_PARSER_ICMP_V4_ENABLED = 1 << 8, 1178 MLX5_FLEX_PARSER_ICMP_V6_ENABLED = 1 << 9, 1179 }; 1180 1181 enum { 1182 MLX5_UCTX_CAP_RAW_TX = 1UL << 0, 1183 MLX5_UCTX_CAP_INTERNAL_DEV_RES = 1UL << 1, 1184 }; 1185 1186 #define MLX5_FC_BULK_SIZE_FACTOR 128 1187 1188 enum mlx5_fc_bulk_alloc_bitmask { 1189 MLX5_FC_BULK_128 = (1 << 0), 1190 MLX5_FC_BULK_256 = (1 << 1), 1191 MLX5_FC_BULK_512 = (1 << 2), 1192 MLX5_FC_BULK_1024 = (1 << 3), 1193 MLX5_FC_BULK_2048 = (1 << 4), 1194 MLX5_FC_BULK_4096 = (1 << 5), 1195 MLX5_FC_BULK_8192 = (1 << 6), 1196 MLX5_FC_BULK_16384 = (1 << 7), 1197 }; 1198 1199 #define MLX5_FC_BULK_NUM_FCS(fc_enum) (MLX5_FC_BULK_SIZE_FACTOR * (fc_enum)) 1200 1201 struct mlx5_ifc_cmd_hca_cap_bits { 1202 u8 reserved_at_0[0x30]; 1203 u8 vhca_id[0x10]; 1204 1205 u8 reserved_at_40[0x40]; 1206 1207 u8 log_max_srq_sz[0x8]; 1208 u8 log_max_qp_sz[0x8]; 1209 u8 event_cap[0x1]; 1210 u8 reserved_at_91[0x7]; 1211 u8 prio_tag_required[0x1]; 1212 u8 reserved_at_99[0x2]; 1213 u8 log_max_qp[0x5]; 1214 1215 u8 reserved_at_a0[0x3]; 1216 u8 ece_support[0x1]; 1217 u8 reserved_at_a4[0x7]; 1218 u8 log_max_srq[0x5]; 1219 u8 reserved_at_b0[0x10]; 1220 1221 u8 max_sgl_for_optimized_performance[0x8]; 1222 u8 log_max_cq_sz[0x8]; 1223 u8 reserved_at_d0[0xb]; 1224 u8 log_max_cq[0x5]; 1225 1226 u8 log_max_eq_sz[0x8]; 1227 u8 relaxed_ordering_write[0x1]; 1228 u8 relaxed_ordering_read[0x1]; 1229 u8 log_max_mkey[0x6]; 1230 u8 reserved_at_f0[0x8]; 1231 u8 dump_fill_mkey[0x1]; 1232 u8 reserved_at_f9[0x2]; 1233 u8 fast_teardown[0x1]; 1234 u8 log_max_eq[0x4]; 1235 1236 u8 max_indirection[0x8]; 1237 u8 fixed_buffer_size[0x1]; 1238 u8 log_max_mrw_sz[0x7]; 1239 u8 force_teardown[0x1]; 1240 u8 reserved_at_111[0x1]; 1241 u8 log_max_bsf_list_size[0x6]; 1242 u8 umr_extended_translation_offset[0x1]; 1243 u8 null_mkey[0x1]; 1244 u8 log_max_klm_list_size[0x6]; 1245 1246 u8 reserved_at_120[0xa]; 1247 u8 log_max_ra_req_dc[0x6]; 1248 u8 reserved_at_130[0xa]; 1249 u8 log_max_ra_res_dc[0x6]; 1250 1251 u8 reserved_at_140[0x6]; 1252 u8 release_all_pages[0x1]; 1253 u8 reserved_at_147[0x2]; 1254 u8 roce_accl[0x1]; 1255 u8 log_max_ra_req_qp[0x6]; 1256 u8 reserved_at_150[0xa]; 1257 u8 log_max_ra_res_qp[0x6]; 1258 1259 u8 end_pad[0x1]; 1260 u8 cc_query_allowed[0x1]; 1261 u8 cc_modify_allowed[0x1]; 1262 u8 start_pad[0x1]; 1263 u8 cache_line_128byte[0x1]; 1264 u8 reserved_at_165[0x4]; 1265 u8 rts2rts_qp_counters_set_id[0x1]; 1266 u8 reserved_at_16a[0x2]; 1267 u8 vnic_env_int_rq_oob[0x1]; 1268 u8 sbcam_reg[0x1]; 1269 u8 reserved_at_16e[0x1]; 1270 u8 qcam_reg[0x1]; 1271 u8 gid_table_size[0x10]; 1272 1273 u8 out_of_seq_cnt[0x1]; 1274 u8 vport_counters[0x1]; 1275 u8 retransmission_q_counters[0x1]; 1276 u8 debug[0x1]; 1277 u8 modify_rq_counter_set_id[0x1]; 1278 u8 rq_delay_drop[0x1]; 1279 u8 max_qp_cnt[0xa]; 1280 u8 pkey_table_size[0x10]; 1281 1282 u8 vport_group_manager[0x1]; 1283 u8 vhca_group_manager[0x1]; 1284 u8 ib_virt[0x1]; 1285 u8 eth_virt[0x1]; 1286 u8 vnic_env_queue_counters[0x1]; 1287 u8 ets[0x1]; 1288 u8 nic_flow_table[0x1]; 1289 u8 eswitch_manager[0x1]; 1290 u8 device_memory[0x1]; 1291 u8 mcam_reg[0x1]; 1292 u8 pcam_reg[0x1]; 1293 u8 local_ca_ack_delay[0x5]; 1294 u8 port_module_event[0x1]; 1295 u8 enhanced_error_q_counters[0x1]; 1296 u8 ports_check[0x1]; 1297 u8 reserved_at_1b3[0x1]; 1298 u8 disable_link_up[0x1]; 1299 u8 beacon_led[0x1]; 1300 u8 port_type[0x2]; 1301 u8 num_ports[0x8]; 1302 1303 u8 reserved_at_1c0[0x1]; 1304 u8 pps[0x1]; 1305 u8 pps_modify[0x1]; 1306 u8 log_max_msg[0x5]; 1307 u8 reserved_at_1c8[0x4]; 1308 u8 max_tc[0x4]; 1309 u8 temp_warn_event[0x1]; 1310 u8 dcbx[0x1]; 1311 u8 general_notification_event[0x1]; 1312 u8 reserved_at_1d3[0x2]; 1313 u8 fpga[0x1]; 1314 u8 rol_s[0x1]; 1315 u8 rol_g[0x1]; 1316 u8 reserved_at_1d8[0x1]; 1317 u8 wol_s[0x1]; 1318 u8 wol_g[0x1]; 1319 u8 wol_a[0x1]; 1320 u8 wol_b[0x1]; 1321 u8 wol_m[0x1]; 1322 u8 wol_u[0x1]; 1323 u8 wol_p[0x1]; 1324 1325 u8 stat_rate_support[0x10]; 1326 u8 reserved_at_1f0[0x1]; 1327 u8 pci_sync_for_fw_update_event[0x1]; 1328 u8 reserved_at_1f2[0x6]; 1329 u8 init2_lag_tx_port_affinity[0x1]; 1330 u8 reserved_at_1fa[0x3]; 1331 u8 cqe_version[0x4]; 1332 1333 u8 compact_address_vector[0x1]; 1334 u8 striding_rq[0x1]; 1335 u8 reserved_at_202[0x1]; 1336 u8 ipoib_enhanced_offloads[0x1]; 1337 u8 ipoib_basic_offloads[0x1]; 1338 u8 reserved_at_205[0x1]; 1339 u8 repeated_block_disabled[0x1]; 1340 u8 umr_modify_entity_size_disabled[0x1]; 1341 u8 umr_modify_atomic_disabled[0x1]; 1342 u8 umr_indirect_mkey_disabled[0x1]; 1343 u8 umr_fence[0x2]; 1344 u8 dc_req_scat_data_cqe[0x1]; 1345 u8 reserved_at_20d[0x2]; 1346 u8 drain_sigerr[0x1]; 1347 u8 cmdif_checksum[0x2]; 1348 u8 sigerr_cqe[0x1]; 1349 u8 reserved_at_213[0x1]; 1350 u8 wq_signature[0x1]; 1351 u8 sctr_data_cqe[0x1]; 1352 u8 reserved_at_216[0x1]; 1353 u8 sho[0x1]; 1354 u8 tph[0x1]; 1355 u8 rf[0x1]; 1356 u8 dct[0x1]; 1357 u8 qos[0x1]; 1358 u8 eth_net_offloads[0x1]; 1359 u8 roce[0x1]; 1360 u8 atomic[0x1]; 1361 u8 reserved_at_21f[0x1]; 1362 1363 u8 cq_oi[0x1]; 1364 u8 cq_resize[0x1]; 1365 u8 cq_moderation[0x1]; 1366 u8 reserved_at_223[0x3]; 1367 u8 cq_eq_remap[0x1]; 1368 u8 pg[0x1]; 1369 u8 block_lb_mc[0x1]; 1370 u8 reserved_at_229[0x1]; 1371 u8 scqe_break_moderation[0x1]; 1372 u8 cq_period_start_from_cqe[0x1]; 1373 u8 cd[0x1]; 1374 u8 reserved_at_22d[0x1]; 1375 u8 apm[0x1]; 1376 u8 vector_calc[0x1]; 1377 u8 umr_ptr_rlky[0x1]; 1378 u8 imaicl[0x1]; 1379 u8 qp_packet_based[0x1]; 1380 u8 reserved_at_233[0x3]; 1381 u8 qkv[0x1]; 1382 u8 pkv[0x1]; 1383 u8 set_deth_sqpn[0x1]; 1384 u8 reserved_at_239[0x3]; 1385 u8 xrc[0x1]; 1386 u8 ud[0x1]; 1387 u8 uc[0x1]; 1388 u8 rc[0x1]; 1389 1390 u8 uar_4k[0x1]; 1391 u8 reserved_at_241[0x9]; 1392 u8 uar_sz[0x6]; 1393 u8 reserved_at_250[0x8]; 1394 u8 log_pg_sz[0x8]; 1395 1396 u8 bf[0x1]; 1397 u8 driver_version[0x1]; 1398 u8 pad_tx_eth_packet[0x1]; 1399 u8 reserved_at_263[0x8]; 1400 u8 log_bf_reg_size[0x5]; 1401 1402 u8 reserved_at_270[0x8]; 1403 u8 lag_tx_port_affinity[0x1]; 1404 u8 reserved_at_279[0x2]; 1405 u8 lag_master[0x1]; 1406 u8 num_lag_ports[0x4]; 1407 1408 u8 reserved_at_280[0x10]; 1409 u8 max_wqe_sz_sq[0x10]; 1410 1411 u8 reserved_at_2a0[0x10]; 1412 u8 max_wqe_sz_rq[0x10]; 1413 1414 u8 max_flow_counter_31_16[0x10]; 1415 u8 max_wqe_sz_sq_dc[0x10]; 1416 1417 u8 reserved_at_2e0[0x7]; 1418 u8 max_qp_mcg[0x19]; 1419 1420 u8 reserved_at_300[0x10]; 1421 u8 flow_counter_bulk_alloc[0x8]; 1422 u8 log_max_mcg[0x8]; 1423 1424 u8 reserved_at_320[0x3]; 1425 u8 log_max_transport_domain[0x5]; 1426 u8 reserved_at_328[0x3]; 1427 u8 log_max_pd[0x5]; 1428 u8 reserved_at_330[0xb]; 1429 u8 log_max_xrcd[0x5]; 1430 1431 u8 nic_receive_steering_discard[0x1]; 1432 u8 receive_discard_vport_down[0x1]; 1433 u8 transmit_discard_vport_down[0x1]; 1434 u8 reserved_at_343[0x5]; 1435 u8 log_max_flow_counter_bulk[0x8]; 1436 u8 max_flow_counter_15_0[0x10]; 1437 1438 1439 u8 reserved_at_360[0x3]; 1440 u8 log_max_rq[0x5]; 1441 u8 reserved_at_368[0x3]; 1442 u8 log_max_sq[0x5]; 1443 u8 reserved_at_370[0x3]; 1444 u8 log_max_tir[0x5]; 1445 u8 reserved_at_378[0x3]; 1446 u8 log_max_tis[0x5]; 1447 1448 u8 basic_cyclic_rcv_wqe[0x1]; 1449 u8 reserved_at_381[0x2]; 1450 u8 log_max_rmp[0x5]; 1451 u8 reserved_at_388[0x3]; 1452 u8 log_max_rqt[0x5]; 1453 u8 reserved_at_390[0x3]; 1454 u8 log_max_rqt_size[0x5]; 1455 u8 reserved_at_398[0x3]; 1456 u8 log_max_tis_per_sq[0x5]; 1457 1458 u8 ext_stride_num_range[0x1]; 1459 u8 reserved_at_3a1[0x2]; 1460 u8 log_max_stride_sz_rq[0x5]; 1461 u8 reserved_at_3a8[0x3]; 1462 u8 log_min_stride_sz_rq[0x5]; 1463 u8 reserved_at_3b0[0x3]; 1464 u8 log_max_stride_sz_sq[0x5]; 1465 u8 reserved_at_3b8[0x3]; 1466 u8 log_min_stride_sz_sq[0x5]; 1467 1468 u8 hairpin[0x1]; 1469 u8 reserved_at_3c1[0x2]; 1470 u8 log_max_hairpin_queues[0x5]; 1471 u8 reserved_at_3c8[0x3]; 1472 u8 log_max_hairpin_wq_data_sz[0x5]; 1473 u8 reserved_at_3d0[0x3]; 1474 u8 log_max_hairpin_num_packets[0x5]; 1475 u8 reserved_at_3d8[0x3]; 1476 u8 log_max_wq_sz[0x5]; 1477 1478 u8 nic_vport_change_event[0x1]; 1479 u8 disable_local_lb_uc[0x1]; 1480 u8 disable_local_lb_mc[0x1]; 1481 u8 log_min_hairpin_wq_data_sz[0x5]; 1482 u8 reserved_at_3e8[0x3]; 1483 u8 log_max_vlan_list[0x5]; 1484 u8 reserved_at_3f0[0x3]; 1485 u8 log_max_current_mc_list[0x5]; 1486 u8 reserved_at_3f8[0x3]; 1487 u8 log_max_current_uc_list[0x5]; 1488 1489 u8 general_obj_types[0x40]; 1490 1491 u8 reserved_at_440[0x20]; 1492 1493 u8 reserved_at_460[0x3]; 1494 u8 log_max_uctx[0x5]; 1495 u8 reserved_at_468[0x2]; 1496 u8 ipsec_offload[0x1]; 1497 u8 log_max_umem[0x5]; 1498 u8 max_num_eqs[0x10]; 1499 1500 u8 reserved_at_480[0x1]; 1501 u8 tls_tx[0x1]; 1502 u8 tls_rx[0x1]; 1503 u8 log_max_l2_table[0x5]; 1504 u8 reserved_at_488[0x8]; 1505 u8 log_uar_page_sz[0x10]; 1506 1507 u8 reserved_at_4a0[0x20]; 1508 u8 device_frequency_mhz[0x20]; 1509 u8 device_frequency_khz[0x20]; 1510 1511 u8 reserved_at_500[0x20]; 1512 u8 num_of_uars_per_page[0x20]; 1513 1514 u8 flex_parser_protocols[0x20]; 1515 1516 u8 max_geneve_tlv_options[0x8]; 1517 u8 reserved_at_568[0x3]; 1518 u8 max_geneve_tlv_option_data_len[0x5]; 1519 u8 reserved_at_570[0x10]; 1520 1521 u8 reserved_at_580[0x33]; 1522 u8 log_max_dek[0x5]; 1523 u8 reserved_at_5b8[0x4]; 1524 u8 mini_cqe_resp_stride_index[0x1]; 1525 u8 cqe_128_always[0x1]; 1526 u8 cqe_compression_128[0x1]; 1527 u8 cqe_compression[0x1]; 1528 1529 u8 cqe_compression_timeout[0x10]; 1530 u8 cqe_compression_max_num[0x10]; 1531 1532 u8 reserved_at_5e0[0x10]; 1533 u8 tag_matching[0x1]; 1534 u8 rndv_offload_rc[0x1]; 1535 u8 rndv_offload_dc[0x1]; 1536 u8 log_tag_matching_list_sz[0x5]; 1537 u8 reserved_at_5f8[0x3]; 1538 u8 log_max_xrq[0x5]; 1539 1540 u8 affiliate_nic_vport_criteria[0x8]; 1541 u8 native_port_num[0x8]; 1542 u8 num_vhca_ports[0x8]; 1543 u8 reserved_at_618[0x6]; 1544 u8 sw_owner_id[0x1]; 1545 u8 reserved_at_61f[0x1]; 1546 1547 u8 max_num_of_monitor_counters[0x10]; 1548 u8 num_ppcnt_monitor_counters[0x10]; 1549 1550 u8 reserved_at_640[0x10]; 1551 u8 num_q_monitor_counters[0x10]; 1552 1553 u8 reserved_at_660[0x20]; 1554 1555 u8 sf[0x1]; 1556 u8 sf_set_partition[0x1]; 1557 u8 reserved_at_682[0x1]; 1558 u8 log_max_sf[0x5]; 1559 u8 reserved_at_688[0x8]; 1560 u8 log_min_sf_size[0x8]; 1561 u8 max_num_sf_partitions[0x8]; 1562 1563 u8 uctx_cap[0x20]; 1564 1565 u8 reserved_at_6c0[0x4]; 1566 u8 flex_parser_id_geneve_tlv_option_0[0x4]; 1567 u8 flex_parser_id_icmp_dw1[0x4]; 1568 u8 flex_parser_id_icmp_dw0[0x4]; 1569 u8 flex_parser_id_icmpv6_dw1[0x4]; 1570 u8 flex_parser_id_icmpv6_dw0[0x4]; 1571 u8 flex_parser_id_outer_first_mpls_over_gre[0x4]; 1572 u8 flex_parser_id_outer_first_mpls_over_udp_label[0x4]; 1573 1574 u8 reserved_at_6e0[0x10]; 1575 u8 sf_base_id[0x10]; 1576 1577 u8 reserved_at_700[0x80]; 1578 u8 vhca_tunnel_commands[0x40]; 1579 u8 reserved_at_7c0[0x40]; 1580 }; 1581 1582 enum mlx5_flow_destination_type { 1583 MLX5_FLOW_DESTINATION_TYPE_VPORT = 0x0, 1584 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1, 1585 MLX5_FLOW_DESTINATION_TYPE_TIR = 0x2, 1586 1587 MLX5_FLOW_DESTINATION_TYPE_PORT = 0x99, 1588 MLX5_FLOW_DESTINATION_TYPE_COUNTER = 0x100, 1589 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE_NUM = 0x101, 1590 }; 1591 1592 enum mlx5_flow_table_miss_action { 1593 MLX5_FLOW_TABLE_MISS_ACTION_DEF, 1594 MLX5_FLOW_TABLE_MISS_ACTION_FWD, 1595 MLX5_FLOW_TABLE_MISS_ACTION_SWITCH_DOMAIN, 1596 }; 1597 1598 struct mlx5_ifc_dest_format_struct_bits { 1599 u8 destination_type[0x8]; 1600 u8 destination_id[0x18]; 1601 1602 u8 destination_eswitch_owner_vhca_id_valid[0x1]; 1603 u8 packet_reformat[0x1]; 1604 u8 reserved_at_22[0xe]; 1605 u8 destination_eswitch_owner_vhca_id[0x10]; 1606 }; 1607 1608 struct mlx5_ifc_flow_counter_list_bits { 1609 u8 flow_counter_id[0x20]; 1610 1611 u8 reserved_at_20[0x20]; 1612 }; 1613 1614 struct mlx5_ifc_extended_dest_format_bits { 1615 struct mlx5_ifc_dest_format_struct_bits destination_entry; 1616 1617 u8 packet_reformat_id[0x20]; 1618 1619 u8 reserved_at_60[0x20]; 1620 }; 1621 1622 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits { 1623 struct mlx5_ifc_extended_dest_format_bits extended_dest_format; 1624 struct mlx5_ifc_flow_counter_list_bits flow_counter_list; 1625 }; 1626 1627 struct mlx5_ifc_fte_match_param_bits { 1628 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers; 1629 1630 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters; 1631 1632 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers; 1633 1634 struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2; 1635 1636 struct mlx5_ifc_fte_match_set_misc3_bits misc_parameters_3; 1637 1638 u8 reserved_at_a00[0x600]; 1639 }; 1640 1641 enum { 1642 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0, 1643 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1, 1644 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2, 1645 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3, 1646 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4, 1647 }; 1648 1649 struct mlx5_ifc_rx_hash_field_select_bits { 1650 u8 l3_prot_type[0x1]; 1651 u8 l4_prot_type[0x1]; 1652 u8 selected_fields[0x1e]; 1653 }; 1654 1655 enum { 1656 MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0, 1657 MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1, 1658 }; 1659 1660 enum { 1661 MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0, 1662 MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1, 1663 }; 1664 1665 struct mlx5_ifc_wq_bits { 1666 u8 wq_type[0x4]; 1667 u8 wq_signature[0x1]; 1668 u8 end_padding_mode[0x2]; 1669 u8 cd_slave[0x1]; 1670 u8 reserved_at_8[0x18]; 1671 1672 u8 hds_skip_first_sge[0x1]; 1673 u8 log2_hds_buf_size[0x3]; 1674 u8 reserved_at_24[0x7]; 1675 u8 page_offset[0x5]; 1676 u8 lwm[0x10]; 1677 1678 u8 reserved_at_40[0x8]; 1679 u8 pd[0x18]; 1680 1681 u8 reserved_at_60[0x8]; 1682 u8 uar_page[0x18]; 1683 1684 u8 dbr_addr[0x40]; 1685 1686 u8 hw_counter[0x20]; 1687 1688 u8 sw_counter[0x20]; 1689 1690 u8 reserved_at_100[0xc]; 1691 u8 log_wq_stride[0x4]; 1692 u8 reserved_at_110[0x3]; 1693 u8 log_wq_pg_sz[0x5]; 1694 u8 reserved_at_118[0x3]; 1695 u8 log_wq_sz[0x5]; 1696 1697 u8 dbr_umem_valid[0x1]; 1698 u8 wq_umem_valid[0x1]; 1699 u8 reserved_at_122[0x1]; 1700 u8 log_hairpin_num_packets[0x5]; 1701 u8 reserved_at_128[0x3]; 1702 u8 log_hairpin_data_sz[0x5]; 1703 1704 u8 reserved_at_130[0x4]; 1705 u8 log_wqe_num_of_strides[0x4]; 1706 u8 two_byte_shift_en[0x1]; 1707 u8 reserved_at_139[0x4]; 1708 u8 log_wqe_stride_size[0x3]; 1709 1710 u8 reserved_at_140[0x4c0]; 1711 1712 struct mlx5_ifc_cmd_pas_bits pas[]; 1713 }; 1714 1715 struct mlx5_ifc_rq_num_bits { 1716 u8 reserved_at_0[0x8]; 1717 u8 rq_num[0x18]; 1718 }; 1719 1720 struct mlx5_ifc_mac_address_layout_bits { 1721 u8 reserved_at_0[0x10]; 1722 u8 mac_addr_47_32[0x10]; 1723 1724 u8 mac_addr_31_0[0x20]; 1725 }; 1726 1727 struct mlx5_ifc_vlan_layout_bits { 1728 u8 reserved_at_0[0x14]; 1729 u8 vlan[0x0c]; 1730 1731 u8 reserved_at_20[0x20]; 1732 }; 1733 1734 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits { 1735 u8 reserved_at_0[0xa0]; 1736 1737 u8 min_time_between_cnps[0x20]; 1738 1739 u8 reserved_at_c0[0x12]; 1740 u8 cnp_dscp[0x6]; 1741 u8 reserved_at_d8[0x4]; 1742 u8 cnp_prio_mode[0x1]; 1743 u8 cnp_802p_prio[0x3]; 1744 1745 u8 reserved_at_e0[0x720]; 1746 }; 1747 1748 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits { 1749 u8 reserved_at_0[0x60]; 1750 1751 u8 reserved_at_60[0x4]; 1752 u8 clamp_tgt_rate[0x1]; 1753 u8 reserved_at_65[0x3]; 1754 u8 clamp_tgt_rate_after_time_inc[0x1]; 1755 u8 reserved_at_69[0x17]; 1756 1757 u8 reserved_at_80[0x20]; 1758 1759 u8 rpg_time_reset[0x20]; 1760 1761 u8 rpg_byte_reset[0x20]; 1762 1763 u8 rpg_threshold[0x20]; 1764 1765 u8 rpg_max_rate[0x20]; 1766 1767 u8 rpg_ai_rate[0x20]; 1768 1769 u8 rpg_hai_rate[0x20]; 1770 1771 u8 rpg_gd[0x20]; 1772 1773 u8 rpg_min_dec_fac[0x20]; 1774 1775 u8 rpg_min_rate[0x20]; 1776 1777 u8 reserved_at_1c0[0xe0]; 1778 1779 u8 rate_to_set_on_first_cnp[0x20]; 1780 1781 u8 dce_tcp_g[0x20]; 1782 1783 u8 dce_tcp_rtt[0x20]; 1784 1785 u8 rate_reduce_monitor_period[0x20]; 1786 1787 u8 reserved_at_320[0x20]; 1788 1789 u8 initial_alpha_value[0x20]; 1790 1791 u8 reserved_at_360[0x4a0]; 1792 }; 1793 1794 struct mlx5_ifc_cong_control_802_1qau_rp_bits { 1795 u8 reserved_at_0[0x80]; 1796 1797 u8 rppp_max_rps[0x20]; 1798 1799 u8 rpg_time_reset[0x20]; 1800 1801 u8 rpg_byte_reset[0x20]; 1802 1803 u8 rpg_threshold[0x20]; 1804 1805 u8 rpg_max_rate[0x20]; 1806 1807 u8 rpg_ai_rate[0x20]; 1808 1809 u8 rpg_hai_rate[0x20]; 1810 1811 u8 rpg_gd[0x20]; 1812 1813 u8 rpg_min_dec_fac[0x20]; 1814 1815 u8 rpg_min_rate[0x20]; 1816 1817 u8 reserved_at_1c0[0x640]; 1818 }; 1819 1820 enum { 1821 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1, 1822 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2, 1823 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4, 1824 }; 1825 1826 struct mlx5_ifc_resize_field_select_bits { 1827 u8 resize_field_select[0x20]; 1828 }; 1829 1830 struct mlx5_ifc_resource_dump_bits { 1831 u8 more_dump[0x1]; 1832 u8 inline_dump[0x1]; 1833 u8 reserved_at_2[0xa]; 1834 u8 seq_num[0x4]; 1835 u8 segment_type[0x10]; 1836 1837 u8 reserved_at_20[0x10]; 1838 u8 vhca_id[0x10]; 1839 1840 u8 index1[0x20]; 1841 1842 u8 index2[0x20]; 1843 1844 u8 num_of_obj1[0x10]; 1845 u8 num_of_obj2[0x10]; 1846 1847 u8 reserved_at_a0[0x20]; 1848 1849 u8 device_opaque[0x40]; 1850 1851 u8 mkey[0x20]; 1852 1853 u8 size[0x20]; 1854 1855 u8 address[0x40]; 1856 1857 u8 inline_data[52][0x20]; 1858 }; 1859 1860 struct mlx5_ifc_resource_dump_menu_record_bits { 1861 u8 reserved_at_0[0x4]; 1862 u8 num_of_obj2_supports_active[0x1]; 1863 u8 num_of_obj2_supports_all[0x1]; 1864 u8 must_have_num_of_obj2[0x1]; 1865 u8 support_num_of_obj2[0x1]; 1866 u8 num_of_obj1_supports_active[0x1]; 1867 u8 num_of_obj1_supports_all[0x1]; 1868 u8 must_have_num_of_obj1[0x1]; 1869 u8 support_num_of_obj1[0x1]; 1870 u8 must_have_index2[0x1]; 1871 u8 support_index2[0x1]; 1872 u8 must_have_index1[0x1]; 1873 u8 support_index1[0x1]; 1874 u8 segment_type[0x10]; 1875 1876 u8 segment_name[4][0x20]; 1877 1878 u8 index1_name[4][0x20]; 1879 1880 u8 index2_name[4][0x20]; 1881 }; 1882 1883 struct mlx5_ifc_resource_dump_segment_header_bits { 1884 u8 length_dw[0x10]; 1885 u8 segment_type[0x10]; 1886 }; 1887 1888 struct mlx5_ifc_resource_dump_command_segment_bits { 1889 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 1890 1891 u8 segment_called[0x10]; 1892 u8 vhca_id[0x10]; 1893 1894 u8 index1[0x20]; 1895 1896 u8 index2[0x20]; 1897 1898 u8 num_of_obj1[0x10]; 1899 u8 num_of_obj2[0x10]; 1900 }; 1901 1902 struct mlx5_ifc_resource_dump_error_segment_bits { 1903 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 1904 1905 u8 reserved_at_20[0x10]; 1906 u8 syndrome_id[0x10]; 1907 1908 u8 reserved_at_40[0x40]; 1909 1910 u8 error[8][0x20]; 1911 }; 1912 1913 struct mlx5_ifc_resource_dump_info_segment_bits { 1914 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 1915 1916 u8 reserved_at_20[0x18]; 1917 u8 dump_version[0x8]; 1918 1919 u8 hw_version[0x20]; 1920 1921 u8 fw_version[0x20]; 1922 }; 1923 1924 struct mlx5_ifc_resource_dump_menu_segment_bits { 1925 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 1926 1927 u8 reserved_at_20[0x10]; 1928 u8 num_of_records[0x10]; 1929 1930 struct mlx5_ifc_resource_dump_menu_record_bits record[]; 1931 }; 1932 1933 struct mlx5_ifc_resource_dump_resource_segment_bits { 1934 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 1935 1936 u8 reserved_at_20[0x20]; 1937 1938 u8 index1[0x20]; 1939 1940 u8 index2[0x20]; 1941 1942 u8 payload[][0x20]; 1943 }; 1944 1945 struct mlx5_ifc_resource_dump_terminate_segment_bits { 1946 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 1947 }; 1948 1949 struct mlx5_ifc_menu_resource_dump_response_bits { 1950 struct mlx5_ifc_resource_dump_info_segment_bits info; 1951 struct mlx5_ifc_resource_dump_command_segment_bits cmd; 1952 struct mlx5_ifc_resource_dump_menu_segment_bits menu; 1953 struct mlx5_ifc_resource_dump_terminate_segment_bits terminate; 1954 }; 1955 1956 enum { 1957 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1, 1958 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2, 1959 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4, 1960 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8, 1961 }; 1962 1963 struct mlx5_ifc_modify_field_select_bits { 1964 u8 modify_field_select[0x20]; 1965 }; 1966 1967 struct mlx5_ifc_field_select_r_roce_np_bits { 1968 u8 field_select_r_roce_np[0x20]; 1969 }; 1970 1971 struct mlx5_ifc_field_select_r_roce_rp_bits { 1972 u8 field_select_r_roce_rp[0x20]; 1973 }; 1974 1975 enum { 1976 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4, 1977 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8, 1978 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10, 1979 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20, 1980 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40, 1981 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80, 1982 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100, 1983 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200, 1984 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400, 1985 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800, 1986 }; 1987 1988 struct mlx5_ifc_field_select_802_1qau_rp_bits { 1989 u8 field_select_8021qaurp[0x20]; 1990 }; 1991 1992 struct mlx5_ifc_phys_layer_cntrs_bits { 1993 u8 time_since_last_clear_high[0x20]; 1994 1995 u8 time_since_last_clear_low[0x20]; 1996 1997 u8 symbol_errors_high[0x20]; 1998 1999 u8 symbol_errors_low[0x20]; 2000 2001 u8 sync_headers_errors_high[0x20]; 2002 2003 u8 sync_headers_errors_low[0x20]; 2004 2005 u8 edpl_bip_errors_lane0_high[0x20]; 2006 2007 u8 edpl_bip_errors_lane0_low[0x20]; 2008 2009 u8 edpl_bip_errors_lane1_high[0x20]; 2010 2011 u8 edpl_bip_errors_lane1_low[0x20]; 2012 2013 u8 edpl_bip_errors_lane2_high[0x20]; 2014 2015 u8 edpl_bip_errors_lane2_low[0x20]; 2016 2017 u8 edpl_bip_errors_lane3_high[0x20]; 2018 2019 u8 edpl_bip_errors_lane3_low[0x20]; 2020 2021 u8 fc_fec_corrected_blocks_lane0_high[0x20]; 2022 2023 u8 fc_fec_corrected_blocks_lane0_low[0x20]; 2024 2025 u8 fc_fec_corrected_blocks_lane1_high[0x20]; 2026 2027 u8 fc_fec_corrected_blocks_lane1_low[0x20]; 2028 2029 u8 fc_fec_corrected_blocks_lane2_high[0x20]; 2030 2031 u8 fc_fec_corrected_blocks_lane2_low[0x20]; 2032 2033 u8 fc_fec_corrected_blocks_lane3_high[0x20]; 2034 2035 u8 fc_fec_corrected_blocks_lane3_low[0x20]; 2036 2037 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20]; 2038 2039 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20]; 2040 2041 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20]; 2042 2043 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20]; 2044 2045 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20]; 2046 2047 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20]; 2048 2049 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20]; 2050 2051 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20]; 2052 2053 u8 rs_fec_corrected_blocks_high[0x20]; 2054 2055 u8 rs_fec_corrected_blocks_low[0x20]; 2056 2057 u8 rs_fec_uncorrectable_blocks_high[0x20]; 2058 2059 u8 rs_fec_uncorrectable_blocks_low[0x20]; 2060 2061 u8 rs_fec_no_errors_blocks_high[0x20]; 2062 2063 u8 rs_fec_no_errors_blocks_low[0x20]; 2064 2065 u8 rs_fec_single_error_blocks_high[0x20]; 2066 2067 u8 rs_fec_single_error_blocks_low[0x20]; 2068 2069 u8 rs_fec_corrected_symbols_total_high[0x20]; 2070 2071 u8 rs_fec_corrected_symbols_total_low[0x20]; 2072 2073 u8 rs_fec_corrected_symbols_lane0_high[0x20]; 2074 2075 u8 rs_fec_corrected_symbols_lane0_low[0x20]; 2076 2077 u8 rs_fec_corrected_symbols_lane1_high[0x20]; 2078 2079 u8 rs_fec_corrected_symbols_lane1_low[0x20]; 2080 2081 u8 rs_fec_corrected_symbols_lane2_high[0x20]; 2082 2083 u8 rs_fec_corrected_symbols_lane2_low[0x20]; 2084 2085 u8 rs_fec_corrected_symbols_lane3_high[0x20]; 2086 2087 u8 rs_fec_corrected_symbols_lane3_low[0x20]; 2088 2089 u8 link_down_events[0x20]; 2090 2091 u8 successful_recovery_events[0x20]; 2092 2093 u8 reserved_at_640[0x180]; 2094 }; 2095 2096 struct mlx5_ifc_phys_layer_statistical_cntrs_bits { 2097 u8 time_since_last_clear_high[0x20]; 2098 2099 u8 time_since_last_clear_low[0x20]; 2100 2101 u8 phy_received_bits_high[0x20]; 2102 2103 u8 phy_received_bits_low[0x20]; 2104 2105 u8 phy_symbol_errors_high[0x20]; 2106 2107 u8 phy_symbol_errors_low[0x20]; 2108 2109 u8 phy_corrected_bits_high[0x20]; 2110 2111 u8 phy_corrected_bits_low[0x20]; 2112 2113 u8 phy_corrected_bits_lane0_high[0x20]; 2114 2115 u8 phy_corrected_bits_lane0_low[0x20]; 2116 2117 u8 phy_corrected_bits_lane1_high[0x20]; 2118 2119 u8 phy_corrected_bits_lane1_low[0x20]; 2120 2121 u8 phy_corrected_bits_lane2_high[0x20]; 2122 2123 u8 phy_corrected_bits_lane2_low[0x20]; 2124 2125 u8 phy_corrected_bits_lane3_high[0x20]; 2126 2127 u8 phy_corrected_bits_lane3_low[0x20]; 2128 2129 u8 reserved_at_200[0x5c0]; 2130 }; 2131 2132 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits { 2133 u8 symbol_error_counter[0x10]; 2134 2135 u8 link_error_recovery_counter[0x8]; 2136 2137 u8 link_downed_counter[0x8]; 2138 2139 u8 port_rcv_errors[0x10]; 2140 2141 u8 port_rcv_remote_physical_errors[0x10]; 2142 2143 u8 port_rcv_switch_relay_errors[0x10]; 2144 2145 u8 port_xmit_discards[0x10]; 2146 2147 u8 port_xmit_constraint_errors[0x8]; 2148 2149 u8 port_rcv_constraint_errors[0x8]; 2150 2151 u8 reserved_at_70[0x8]; 2152 2153 u8 link_overrun_errors[0x8]; 2154 2155 u8 reserved_at_80[0x10]; 2156 2157 u8 vl_15_dropped[0x10]; 2158 2159 u8 reserved_at_a0[0x80]; 2160 2161 u8 port_xmit_wait[0x20]; 2162 }; 2163 2164 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits { 2165 u8 transmit_queue_high[0x20]; 2166 2167 u8 transmit_queue_low[0x20]; 2168 2169 u8 no_buffer_discard_uc_high[0x20]; 2170 2171 u8 no_buffer_discard_uc_low[0x20]; 2172 2173 u8 reserved_at_80[0x740]; 2174 }; 2175 2176 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits { 2177 u8 wred_discard_high[0x20]; 2178 2179 u8 wred_discard_low[0x20]; 2180 2181 u8 ecn_marked_tc_high[0x20]; 2182 2183 u8 ecn_marked_tc_low[0x20]; 2184 2185 u8 reserved_at_80[0x740]; 2186 }; 2187 2188 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits { 2189 u8 rx_octets_high[0x20]; 2190 2191 u8 rx_octets_low[0x20]; 2192 2193 u8 reserved_at_40[0xc0]; 2194 2195 u8 rx_frames_high[0x20]; 2196 2197 u8 rx_frames_low[0x20]; 2198 2199 u8 tx_octets_high[0x20]; 2200 2201 u8 tx_octets_low[0x20]; 2202 2203 u8 reserved_at_180[0xc0]; 2204 2205 u8 tx_frames_high[0x20]; 2206 2207 u8 tx_frames_low[0x20]; 2208 2209 u8 rx_pause_high[0x20]; 2210 2211 u8 rx_pause_low[0x20]; 2212 2213 u8 rx_pause_duration_high[0x20]; 2214 2215 u8 rx_pause_duration_low[0x20]; 2216 2217 u8 tx_pause_high[0x20]; 2218 2219 u8 tx_pause_low[0x20]; 2220 2221 u8 tx_pause_duration_high[0x20]; 2222 2223 u8 tx_pause_duration_low[0x20]; 2224 2225 u8 rx_pause_transition_high[0x20]; 2226 2227 u8 rx_pause_transition_low[0x20]; 2228 2229 u8 rx_discards_high[0x20]; 2230 2231 u8 rx_discards_low[0x20]; 2232 2233 u8 device_stall_minor_watermark_cnt_high[0x20]; 2234 2235 u8 device_stall_minor_watermark_cnt_low[0x20]; 2236 2237 u8 device_stall_critical_watermark_cnt_high[0x20]; 2238 2239 u8 device_stall_critical_watermark_cnt_low[0x20]; 2240 2241 u8 reserved_at_480[0x340]; 2242 }; 2243 2244 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits { 2245 u8 port_transmit_wait_high[0x20]; 2246 2247 u8 port_transmit_wait_low[0x20]; 2248 2249 u8 reserved_at_40[0x100]; 2250 2251 u8 rx_buffer_almost_full_high[0x20]; 2252 2253 u8 rx_buffer_almost_full_low[0x20]; 2254 2255 u8 rx_buffer_full_high[0x20]; 2256 2257 u8 rx_buffer_full_low[0x20]; 2258 2259 u8 rx_icrc_encapsulated_high[0x20]; 2260 2261 u8 rx_icrc_encapsulated_low[0x20]; 2262 2263 u8 reserved_at_200[0x5c0]; 2264 }; 2265 2266 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits { 2267 u8 dot3stats_alignment_errors_high[0x20]; 2268 2269 u8 dot3stats_alignment_errors_low[0x20]; 2270 2271 u8 dot3stats_fcs_errors_high[0x20]; 2272 2273 u8 dot3stats_fcs_errors_low[0x20]; 2274 2275 u8 dot3stats_single_collision_frames_high[0x20]; 2276 2277 u8 dot3stats_single_collision_frames_low[0x20]; 2278 2279 u8 dot3stats_multiple_collision_frames_high[0x20]; 2280 2281 u8 dot3stats_multiple_collision_frames_low[0x20]; 2282 2283 u8 dot3stats_sqe_test_errors_high[0x20]; 2284 2285 u8 dot3stats_sqe_test_errors_low[0x20]; 2286 2287 u8 dot3stats_deferred_transmissions_high[0x20]; 2288 2289 u8 dot3stats_deferred_transmissions_low[0x20]; 2290 2291 u8 dot3stats_late_collisions_high[0x20]; 2292 2293 u8 dot3stats_late_collisions_low[0x20]; 2294 2295 u8 dot3stats_excessive_collisions_high[0x20]; 2296 2297 u8 dot3stats_excessive_collisions_low[0x20]; 2298 2299 u8 dot3stats_internal_mac_transmit_errors_high[0x20]; 2300 2301 u8 dot3stats_internal_mac_transmit_errors_low[0x20]; 2302 2303 u8 dot3stats_carrier_sense_errors_high[0x20]; 2304 2305 u8 dot3stats_carrier_sense_errors_low[0x20]; 2306 2307 u8 dot3stats_frame_too_longs_high[0x20]; 2308 2309 u8 dot3stats_frame_too_longs_low[0x20]; 2310 2311 u8 dot3stats_internal_mac_receive_errors_high[0x20]; 2312 2313 u8 dot3stats_internal_mac_receive_errors_low[0x20]; 2314 2315 u8 dot3stats_symbol_errors_high[0x20]; 2316 2317 u8 dot3stats_symbol_errors_low[0x20]; 2318 2319 u8 dot3control_in_unknown_opcodes_high[0x20]; 2320 2321 u8 dot3control_in_unknown_opcodes_low[0x20]; 2322 2323 u8 dot3in_pause_frames_high[0x20]; 2324 2325 u8 dot3in_pause_frames_low[0x20]; 2326 2327 u8 dot3out_pause_frames_high[0x20]; 2328 2329 u8 dot3out_pause_frames_low[0x20]; 2330 2331 u8 reserved_at_400[0x3c0]; 2332 }; 2333 2334 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits { 2335 u8 ether_stats_drop_events_high[0x20]; 2336 2337 u8 ether_stats_drop_events_low[0x20]; 2338 2339 u8 ether_stats_octets_high[0x20]; 2340 2341 u8 ether_stats_octets_low[0x20]; 2342 2343 u8 ether_stats_pkts_high[0x20]; 2344 2345 u8 ether_stats_pkts_low[0x20]; 2346 2347 u8 ether_stats_broadcast_pkts_high[0x20]; 2348 2349 u8 ether_stats_broadcast_pkts_low[0x20]; 2350 2351 u8 ether_stats_multicast_pkts_high[0x20]; 2352 2353 u8 ether_stats_multicast_pkts_low[0x20]; 2354 2355 u8 ether_stats_crc_align_errors_high[0x20]; 2356 2357 u8 ether_stats_crc_align_errors_low[0x20]; 2358 2359 u8 ether_stats_undersize_pkts_high[0x20]; 2360 2361 u8 ether_stats_undersize_pkts_low[0x20]; 2362 2363 u8 ether_stats_oversize_pkts_high[0x20]; 2364 2365 u8 ether_stats_oversize_pkts_low[0x20]; 2366 2367 u8 ether_stats_fragments_high[0x20]; 2368 2369 u8 ether_stats_fragments_low[0x20]; 2370 2371 u8 ether_stats_jabbers_high[0x20]; 2372 2373 u8 ether_stats_jabbers_low[0x20]; 2374 2375 u8 ether_stats_collisions_high[0x20]; 2376 2377 u8 ether_stats_collisions_low[0x20]; 2378 2379 u8 ether_stats_pkts64octets_high[0x20]; 2380 2381 u8 ether_stats_pkts64octets_low[0x20]; 2382 2383 u8 ether_stats_pkts65to127octets_high[0x20]; 2384 2385 u8 ether_stats_pkts65to127octets_low[0x20]; 2386 2387 u8 ether_stats_pkts128to255octets_high[0x20]; 2388 2389 u8 ether_stats_pkts128to255octets_low[0x20]; 2390 2391 u8 ether_stats_pkts256to511octets_high[0x20]; 2392 2393 u8 ether_stats_pkts256to511octets_low[0x20]; 2394 2395 u8 ether_stats_pkts512to1023octets_high[0x20]; 2396 2397 u8 ether_stats_pkts512to1023octets_low[0x20]; 2398 2399 u8 ether_stats_pkts1024to1518octets_high[0x20]; 2400 2401 u8 ether_stats_pkts1024to1518octets_low[0x20]; 2402 2403 u8 ether_stats_pkts1519to2047octets_high[0x20]; 2404 2405 u8 ether_stats_pkts1519to2047octets_low[0x20]; 2406 2407 u8 ether_stats_pkts2048to4095octets_high[0x20]; 2408 2409 u8 ether_stats_pkts2048to4095octets_low[0x20]; 2410 2411 u8 ether_stats_pkts4096to8191octets_high[0x20]; 2412 2413 u8 ether_stats_pkts4096to8191octets_low[0x20]; 2414 2415 u8 ether_stats_pkts8192to10239octets_high[0x20]; 2416 2417 u8 ether_stats_pkts8192to10239octets_low[0x20]; 2418 2419 u8 reserved_at_540[0x280]; 2420 }; 2421 2422 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits { 2423 u8 if_in_octets_high[0x20]; 2424 2425 u8 if_in_octets_low[0x20]; 2426 2427 u8 if_in_ucast_pkts_high[0x20]; 2428 2429 u8 if_in_ucast_pkts_low[0x20]; 2430 2431 u8 if_in_discards_high[0x20]; 2432 2433 u8 if_in_discards_low[0x20]; 2434 2435 u8 if_in_errors_high[0x20]; 2436 2437 u8 if_in_errors_low[0x20]; 2438 2439 u8 if_in_unknown_protos_high[0x20]; 2440 2441 u8 if_in_unknown_protos_low[0x20]; 2442 2443 u8 if_out_octets_high[0x20]; 2444 2445 u8 if_out_octets_low[0x20]; 2446 2447 u8 if_out_ucast_pkts_high[0x20]; 2448 2449 u8 if_out_ucast_pkts_low[0x20]; 2450 2451 u8 if_out_discards_high[0x20]; 2452 2453 u8 if_out_discards_low[0x20]; 2454 2455 u8 if_out_errors_high[0x20]; 2456 2457 u8 if_out_errors_low[0x20]; 2458 2459 u8 if_in_multicast_pkts_high[0x20]; 2460 2461 u8 if_in_multicast_pkts_low[0x20]; 2462 2463 u8 if_in_broadcast_pkts_high[0x20]; 2464 2465 u8 if_in_broadcast_pkts_low[0x20]; 2466 2467 u8 if_out_multicast_pkts_high[0x20]; 2468 2469 u8 if_out_multicast_pkts_low[0x20]; 2470 2471 u8 if_out_broadcast_pkts_high[0x20]; 2472 2473 u8 if_out_broadcast_pkts_low[0x20]; 2474 2475 u8 reserved_at_340[0x480]; 2476 }; 2477 2478 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits { 2479 u8 a_frames_transmitted_ok_high[0x20]; 2480 2481 u8 a_frames_transmitted_ok_low[0x20]; 2482 2483 u8 a_frames_received_ok_high[0x20]; 2484 2485 u8 a_frames_received_ok_low[0x20]; 2486 2487 u8 a_frame_check_sequence_errors_high[0x20]; 2488 2489 u8 a_frame_check_sequence_errors_low[0x20]; 2490 2491 u8 a_alignment_errors_high[0x20]; 2492 2493 u8 a_alignment_errors_low[0x20]; 2494 2495 u8 a_octets_transmitted_ok_high[0x20]; 2496 2497 u8 a_octets_transmitted_ok_low[0x20]; 2498 2499 u8 a_octets_received_ok_high[0x20]; 2500 2501 u8 a_octets_received_ok_low[0x20]; 2502 2503 u8 a_multicast_frames_xmitted_ok_high[0x20]; 2504 2505 u8 a_multicast_frames_xmitted_ok_low[0x20]; 2506 2507 u8 a_broadcast_frames_xmitted_ok_high[0x20]; 2508 2509 u8 a_broadcast_frames_xmitted_ok_low[0x20]; 2510 2511 u8 a_multicast_frames_received_ok_high[0x20]; 2512 2513 u8 a_multicast_frames_received_ok_low[0x20]; 2514 2515 u8 a_broadcast_frames_received_ok_high[0x20]; 2516 2517 u8 a_broadcast_frames_received_ok_low[0x20]; 2518 2519 u8 a_in_range_length_errors_high[0x20]; 2520 2521 u8 a_in_range_length_errors_low[0x20]; 2522 2523 u8 a_out_of_range_length_field_high[0x20]; 2524 2525 u8 a_out_of_range_length_field_low[0x20]; 2526 2527 u8 a_frame_too_long_errors_high[0x20]; 2528 2529 u8 a_frame_too_long_errors_low[0x20]; 2530 2531 u8 a_symbol_error_during_carrier_high[0x20]; 2532 2533 u8 a_symbol_error_during_carrier_low[0x20]; 2534 2535 u8 a_mac_control_frames_transmitted_high[0x20]; 2536 2537 u8 a_mac_control_frames_transmitted_low[0x20]; 2538 2539 u8 a_mac_control_frames_received_high[0x20]; 2540 2541 u8 a_mac_control_frames_received_low[0x20]; 2542 2543 u8 a_unsupported_opcodes_received_high[0x20]; 2544 2545 u8 a_unsupported_opcodes_received_low[0x20]; 2546 2547 u8 a_pause_mac_ctrl_frames_received_high[0x20]; 2548 2549 u8 a_pause_mac_ctrl_frames_received_low[0x20]; 2550 2551 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20]; 2552 2553 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20]; 2554 2555 u8 reserved_at_4c0[0x300]; 2556 }; 2557 2558 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits { 2559 u8 life_time_counter_high[0x20]; 2560 2561 u8 life_time_counter_low[0x20]; 2562 2563 u8 rx_errors[0x20]; 2564 2565 u8 tx_errors[0x20]; 2566 2567 u8 l0_to_recovery_eieos[0x20]; 2568 2569 u8 l0_to_recovery_ts[0x20]; 2570 2571 u8 l0_to_recovery_framing[0x20]; 2572 2573 u8 l0_to_recovery_retrain[0x20]; 2574 2575 u8 crc_error_dllp[0x20]; 2576 2577 u8 crc_error_tlp[0x20]; 2578 2579 u8 tx_overflow_buffer_pkt_high[0x20]; 2580 2581 u8 tx_overflow_buffer_pkt_low[0x20]; 2582 2583 u8 outbound_stalled_reads[0x20]; 2584 2585 u8 outbound_stalled_writes[0x20]; 2586 2587 u8 outbound_stalled_reads_events[0x20]; 2588 2589 u8 outbound_stalled_writes_events[0x20]; 2590 2591 u8 reserved_at_200[0x5c0]; 2592 }; 2593 2594 struct mlx5_ifc_cmd_inter_comp_event_bits { 2595 u8 command_completion_vector[0x20]; 2596 2597 u8 reserved_at_20[0xc0]; 2598 }; 2599 2600 struct mlx5_ifc_stall_vl_event_bits { 2601 u8 reserved_at_0[0x18]; 2602 u8 port_num[0x1]; 2603 u8 reserved_at_19[0x3]; 2604 u8 vl[0x4]; 2605 2606 u8 reserved_at_20[0xa0]; 2607 }; 2608 2609 struct mlx5_ifc_db_bf_congestion_event_bits { 2610 u8 event_subtype[0x8]; 2611 u8 reserved_at_8[0x8]; 2612 u8 congestion_level[0x8]; 2613 u8 reserved_at_18[0x8]; 2614 2615 u8 reserved_at_20[0xa0]; 2616 }; 2617 2618 struct mlx5_ifc_gpio_event_bits { 2619 u8 reserved_at_0[0x60]; 2620 2621 u8 gpio_event_hi[0x20]; 2622 2623 u8 gpio_event_lo[0x20]; 2624 2625 u8 reserved_at_a0[0x40]; 2626 }; 2627 2628 struct mlx5_ifc_port_state_change_event_bits { 2629 u8 reserved_at_0[0x40]; 2630 2631 u8 port_num[0x4]; 2632 u8 reserved_at_44[0x1c]; 2633 2634 u8 reserved_at_60[0x80]; 2635 }; 2636 2637 struct mlx5_ifc_dropped_packet_logged_bits { 2638 u8 reserved_at_0[0xe0]; 2639 }; 2640 2641 enum { 2642 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1, 2643 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2, 2644 }; 2645 2646 struct mlx5_ifc_cq_error_bits { 2647 u8 reserved_at_0[0x8]; 2648 u8 cqn[0x18]; 2649 2650 u8 reserved_at_20[0x20]; 2651 2652 u8 reserved_at_40[0x18]; 2653 u8 syndrome[0x8]; 2654 2655 u8 reserved_at_60[0x80]; 2656 }; 2657 2658 struct mlx5_ifc_rdma_page_fault_event_bits { 2659 u8 bytes_committed[0x20]; 2660 2661 u8 r_key[0x20]; 2662 2663 u8 reserved_at_40[0x10]; 2664 u8 packet_len[0x10]; 2665 2666 u8 rdma_op_len[0x20]; 2667 2668 u8 rdma_va[0x40]; 2669 2670 u8 reserved_at_c0[0x5]; 2671 u8 rdma[0x1]; 2672 u8 write[0x1]; 2673 u8 requestor[0x1]; 2674 u8 qp_number[0x18]; 2675 }; 2676 2677 struct mlx5_ifc_wqe_associated_page_fault_event_bits { 2678 u8 bytes_committed[0x20]; 2679 2680 u8 reserved_at_20[0x10]; 2681 u8 wqe_index[0x10]; 2682 2683 u8 reserved_at_40[0x10]; 2684 u8 len[0x10]; 2685 2686 u8 reserved_at_60[0x60]; 2687 2688 u8 reserved_at_c0[0x5]; 2689 u8 rdma[0x1]; 2690 u8 write_read[0x1]; 2691 u8 requestor[0x1]; 2692 u8 qpn[0x18]; 2693 }; 2694 2695 struct mlx5_ifc_qp_events_bits { 2696 u8 reserved_at_0[0xa0]; 2697 2698 u8 type[0x8]; 2699 u8 reserved_at_a8[0x18]; 2700 2701 u8 reserved_at_c0[0x8]; 2702 u8 qpn_rqn_sqn[0x18]; 2703 }; 2704 2705 struct mlx5_ifc_dct_events_bits { 2706 u8 reserved_at_0[0xc0]; 2707 2708 u8 reserved_at_c0[0x8]; 2709 u8 dct_number[0x18]; 2710 }; 2711 2712 struct mlx5_ifc_comp_event_bits { 2713 u8 reserved_at_0[0xc0]; 2714 2715 u8 reserved_at_c0[0x8]; 2716 u8 cq_number[0x18]; 2717 }; 2718 2719 enum { 2720 MLX5_QPC_STATE_RST = 0x0, 2721 MLX5_QPC_STATE_INIT = 0x1, 2722 MLX5_QPC_STATE_RTR = 0x2, 2723 MLX5_QPC_STATE_RTS = 0x3, 2724 MLX5_QPC_STATE_SQER = 0x4, 2725 MLX5_QPC_STATE_ERR = 0x6, 2726 MLX5_QPC_STATE_SQD = 0x7, 2727 MLX5_QPC_STATE_SUSPENDED = 0x9, 2728 }; 2729 2730 enum { 2731 MLX5_QPC_ST_RC = 0x0, 2732 MLX5_QPC_ST_UC = 0x1, 2733 MLX5_QPC_ST_UD = 0x2, 2734 MLX5_QPC_ST_XRC = 0x3, 2735 MLX5_QPC_ST_DCI = 0x5, 2736 MLX5_QPC_ST_QP0 = 0x7, 2737 MLX5_QPC_ST_QP1 = 0x8, 2738 MLX5_QPC_ST_RAW_DATAGRAM = 0x9, 2739 MLX5_QPC_ST_REG_UMR = 0xc, 2740 }; 2741 2742 enum { 2743 MLX5_QPC_PM_STATE_ARMED = 0x0, 2744 MLX5_QPC_PM_STATE_REARM = 0x1, 2745 MLX5_QPC_PM_STATE_RESERVED = 0x2, 2746 MLX5_QPC_PM_STATE_MIGRATED = 0x3, 2747 }; 2748 2749 enum { 2750 MLX5_QPC_OFFLOAD_TYPE_RNDV = 0x1, 2751 }; 2752 2753 enum { 2754 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0, 2755 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1, 2756 }; 2757 2758 enum { 2759 MLX5_QPC_MTU_256_BYTES = 0x1, 2760 MLX5_QPC_MTU_512_BYTES = 0x2, 2761 MLX5_QPC_MTU_1K_BYTES = 0x3, 2762 MLX5_QPC_MTU_2K_BYTES = 0x4, 2763 MLX5_QPC_MTU_4K_BYTES = 0x5, 2764 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7, 2765 }; 2766 2767 enum { 2768 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1, 2769 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2, 2770 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3, 2771 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4, 2772 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5, 2773 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6, 2774 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7, 2775 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8, 2776 }; 2777 2778 enum { 2779 MLX5_QPC_CS_REQ_DISABLE = 0x0, 2780 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11, 2781 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22, 2782 }; 2783 2784 enum { 2785 MLX5_QPC_CS_RES_DISABLE = 0x0, 2786 MLX5_QPC_CS_RES_UP_TO_32B = 0x1, 2787 MLX5_QPC_CS_RES_UP_TO_64B = 0x2, 2788 }; 2789 2790 struct mlx5_ifc_qpc_bits { 2791 u8 state[0x4]; 2792 u8 lag_tx_port_affinity[0x4]; 2793 u8 st[0x8]; 2794 u8 reserved_at_10[0x3]; 2795 u8 pm_state[0x2]; 2796 u8 reserved_at_15[0x1]; 2797 u8 req_e2e_credit_mode[0x2]; 2798 u8 offload_type[0x4]; 2799 u8 end_padding_mode[0x2]; 2800 u8 reserved_at_1e[0x2]; 2801 2802 u8 wq_signature[0x1]; 2803 u8 block_lb_mc[0x1]; 2804 u8 atomic_like_write_en[0x1]; 2805 u8 latency_sensitive[0x1]; 2806 u8 reserved_at_24[0x1]; 2807 u8 drain_sigerr[0x1]; 2808 u8 reserved_at_26[0x2]; 2809 u8 pd[0x18]; 2810 2811 u8 mtu[0x3]; 2812 u8 log_msg_max[0x5]; 2813 u8 reserved_at_48[0x1]; 2814 u8 log_rq_size[0x4]; 2815 u8 log_rq_stride[0x3]; 2816 u8 no_sq[0x1]; 2817 u8 log_sq_size[0x4]; 2818 u8 reserved_at_55[0x6]; 2819 u8 rlky[0x1]; 2820 u8 ulp_stateless_offload_mode[0x4]; 2821 2822 u8 counter_set_id[0x8]; 2823 u8 uar_page[0x18]; 2824 2825 u8 reserved_at_80[0x8]; 2826 u8 user_index[0x18]; 2827 2828 u8 reserved_at_a0[0x3]; 2829 u8 log_page_size[0x5]; 2830 u8 remote_qpn[0x18]; 2831 2832 struct mlx5_ifc_ads_bits primary_address_path; 2833 2834 struct mlx5_ifc_ads_bits secondary_address_path; 2835 2836 u8 log_ack_req_freq[0x4]; 2837 u8 reserved_at_384[0x4]; 2838 u8 log_sra_max[0x3]; 2839 u8 reserved_at_38b[0x2]; 2840 u8 retry_count[0x3]; 2841 u8 rnr_retry[0x3]; 2842 u8 reserved_at_393[0x1]; 2843 u8 fre[0x1]; 2844 u8 cur_rnr_retry[0x3]; 2845 u8 cur_retry_count[0x3]; 2846 u8 reserved_at_39b[0x5]; 2847 2848 u8 reserved_at_3a0[0x20]; 2849 2850 u8 reserved_at_3c0[0x8]; 2851 u8 next_send_psn[0x18]; 2852 2853 u8 reserved_at_3e0[0x8]; 2854 u8 cqn_snd[0x18]; 2855 2856 u8 reserved_at_400[0x8]; 2857 u8 deth_sqpn[0x18]; 2858 2859 u8 reserved_at_420[0x20]; 2860 2861 u8 reserved_at_440[0x8]; 2862 u8 last_acked_psn[0x18]; 2863 2864 u8 reserved_at_460[0x8]; 2865 u8 ssn[0x18]; 2866 2867 u8 reserved_at_480[0x8]; 2868 u8 log_rra_max[0x3]; 2869 u8 reserved_at_48b[0x1]; 2870 u8 atomic_mode[0x4]; 2871 u8 rre[0x1]; 2872 u8 rwe[0x1]; 2873 u8 rae[0x1]; 2874 u8 reserved_at_493[0x1]; 2875 u8 page_offset[0x6]; 2876 u8 reserved_at_49a[0x3]; 2877 u8 cd_slave_receive[0x1]; 2878 u8 cd_slave_send[0x1]; 2879 u8 cd_master[0x1]; 2880 2881 u8 reserved_at_4a0[0x3]; 2882 u8 min_rnr_nak[0x5]; 2883 u8 next_rcv_psn[0x18]; 2884 2885 u8 reserved_at_4c0[0x8]; 2886 u8 xrcd[0x18]; 2887 2888 u8 reserved_at_4e0[0x8]; 2889 u8 cqn_rcv[0x18]; 2890 2891 u8 dbr_addr[0x40]; 2892 2893 u8 q_key[0x20]; 2894 2895 u8 reserved_at_560[0x5]; 2896 u8 rq_type[0x3]; 2897 u8 srqn_rmpn_xrqn[0x18]; 2898 2899 u8 reserved_at_580[0x8]; 2900 u8 rmsn[0x18]; 2901 2902 u8 hw_sq_wqebb_counter[0x10]; 2903 u8 sw_sq_wqebb_counter[0x10]; 2904 2905 u8 hw_rq_counter[0x20]; 2906 2907 u8 sw_rq_counter[0x20]; 2908 2909 u8 reserved_at_600[0x20]; 2910 2911 u8 reserved_at_620[0xf]; 2912 u8 cgs[0x1]; 2913 u8 cs_req[0x8]; 2914 u8 cs_res[0x8]; 2915 2916 u8 dc_access_key[0x40]; 2917 2918 u8 reserved_at_680[0x3]; 2919 u8 dbr_umem_valid[0x1]; 2920 2921 u8 reserved_at_684[0xbc]; 2922 }; 2923 2924 struct mlx5_ifc_roce_addr_layout_bits { 2925 u8 source_l3_address[16][0x8]; 2926 2927 u8 reserved_at_80[0x3]; 2928 u8 vlan_valid[0x1]; 2929 u8 vlan_id[0xc]; 2930 u8 source_mac_47_32[0x10]; 2931 2932 u8 source_mac_31_0[0x20]; 2933 2934 u8 reserved_at_c0[0x14]; 2935 u8 roce_l3_type[0x4]; 2936 u8 roce_version[0x8]; 2937 2938 u8 reserved_at_e0[0x20]; 2939 }; 2940 2941 union mlx5_ifc_hca_cap_union_bits { 2942 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap; 2943 struct mlx5_ifc_odp_cap_bits odp_cap; 2944 struct mlx5_ifc_atomic_caps_bits atomic_caps; 2945 struct mlx5_ifc_roce_cap_bits roce_cap; 2946 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps; 2947 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap; 2948 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap; 2949 struct mlx5_ifc_e_switch_cap_bits e_switch_cap; 2950 struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap; 2951 struct mlx5_ifc_qos_cap_bits qos_cap; 2952 struct mlx5_ifc_debug_cap_bits debug_cap; 2953 struct mlx5_ifc_fpga_cap_bits fpga_cap; 2954 struct mlx5_ifc_tls_cap_bits tls_cap; 2955 struct mlx5_ifc_device_mem_cap_bits device_mem_cap; 2956 struct mlx5_ifc_device_virtio_emulation_cap_bits virtio_emulation_cap; 2957 u8 reserved_at_0[0x8000]; 2958 }; 2959 2960 enum { 2961 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1, 2962 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2, 2963 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4, 2964 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8, 2965 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT = 0x10, 2966 MLX5_FLOW_CONTEXT_ACTION_DECAP = 0x20, 2967 MLX5_FLOW_CONTEXT_ACTION_MOD_HDR = 0x40, 2968 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP = 0x80, 2969 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100, 2970 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2 = 0x400, 2971 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2 = 0x800, 2972 MLX5_FLOW_CONTEXT_ACTION_IPSEC_DECRYPT = 0x1000, 2973 MLX5_FLOW_CONTEXT_ACTION_IPSEC_ENCRYPT = 0x2000, 2974 }; 2975 2976 enum { 2977 MLX5_FLOW_CONTEXT_FLOW_SOURCE_ANY_VPORT = 0x0, 2978 MLX5_FLOW_CONTEXT_FLOW_SOURCE_UPLINK = 0x1, 2979 MLX5_FLOW_CONTEXT_FLOW_SOURCE_LOCAL_VPORT = 0x2, 2980 }; 2981 2982 struct mlx5_ifc_vlan_bits { 2983 u8 ethtype[0x10]; 2984 u8 prio[0x3]; 2985 u8 cfi[0x1]; 2986 u8 vid[0xc]; 2987 }; 2988 2989 struct mlx5_ifc_flow_context_bits { 2990 struct mlx5_ifc_vlan_bits push_vlan; 2991 2992 u8 group_id[0x20]; 2993 2994 u8 reserved_at_40[0x8]; 2995 u8 flow_tag[0x18]; 2996 2997 u8 reserved_at_60[0x10]; 2998 u8 action[0x10]; 2999 3000 u8 extended_destination[0x1]; 3001 u8 reserved_at_81[0x1]; 3002 u8 flow_source[0x2]; 3003 u8 reserved_at_84[0x4]; 3004 u8 destination_list_size[0x18]; 3005 3006 u8 reserved_at_a0[0x8]; 3007 u8 flow_counter_list_size[0x18]; 3008 3009 u8 packet_reformat_id[0x20]; 3010 3011 u8 modify_header_id[0x20]; 3012 3013 struct mlx5_ifc_vlan_bits push_vlan_2; 3014 3015 u8 ipsec_obj_id[0x20]; 3016 u8 reserved_at_140[0xc0]; 3017 3018 struct mlx5_ifc_fte_match_param_bits match_value; 3019 3020 u8 reserved_at_1200[0x600]; 3021 3022 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[]; 3023 }; 3024 3025 enum { 3026 MLX5_XRC_SRQC_STATE_GOOD = 0x0, 3027 MLX5_XRC_SRQC_STATE_ERROR = 0x1, 3028 }; 3029 3030 struct mlx5_ifc_xrc_srqc_bits { 3031 u8 state[0x4]; 3032 u8 log_xrc_srq_size[0x4]; 3033 u8 reserved_at_8[0x18]; 3034 3035 u8 wq_signature[0x1]; 3036 u8 cont_srq[0x1]; 3037 u8 reserved_at_22[0x1]; 3038 u8 rlky[0x1]; 3039 u8 basic_cyclic_rcv_wqe[0x1]; 3040 u8 log_rq_stride[0x3]; 3041 u8 xrcd[0x18]; 3042 3043 u8 page_offset[0x6]; 3044 u8 reserved_at_46[0x1]; 3045 u8 dbr_umem_valid[0x1]; 3046 u8 cqn[0x18]; 3047 3048 u8 reserved_at_60[0x20]; 3049 3050 u8 user_index_equal_xrc_srqn[0x1]; 3051 u8 reserved_at_81[0x1]; 3052 u8 log_page_size[0x6]; 3053 u8 user_index[0x18]; 3054 3055 u8 reserved_at_a0[0x20]; 3056 3057 u8 reserved_at_c0[0x8]; 3058 u8 pd[0x18]; 3059 3060 u8 lwm[0x10]; 3061 u8 wqe_cnt[0x10]; 3062 3063 u8 reserved_at_100[0x40]; 3064 3065 u8 db_record_addr_h[0x20]; 3066 3067 u8 db_record_addr_l[0x1e]; 3068 u8 reserved_at_17e[0x2]; 3069 3070 u8 reserved_at_180[0x80]; 3071 }; 3072 3073 struct mlx5_ifc_vnic_diagnostic_statistics_bits { 3074 u8 counter_error_queues[0x20]; 3075 3076 u8 total_error_queues[0x20]; 3077 3078 u8 send_queue_priority_update_flow[0x20]; 3079 3080 u8 reserved_at_60[0x20]; 3081 3082 u8 nic_receive_steering_discard[0x40]; 3083 3084 u8 receive_discard_vport_down[0x40]; 3085 3086 u8 transmit_discard_vport_down[0x40]; 3087 3088 u8 reserved_at_140[0xa0]; 3089 3090 u8 internal_rq_out_of_buffer[0x20]; 3091 3092 u8 reserved_at_200[0xe00]; 3093 }; 3094 3095 struct mlx5_ifc_traffic_counter_bits { 3096 u8 packets[0x40]; 3097 3098 u8 octets[0x40]; 3099 }; 3100 3101 struct mlx5_ifc_tisc_bits { 3102 u8 strict_lag_tx_port_affinity[0x1]; 3103 u8 tls_en[0x1]; 3104 u8 reserved_at_2[0x2]; 3105 u8 lag_tx_port_affinity[0x04]; 3106 3107 u8 reserved_at_8[0x4]; 3108 u8 prio[0x4]; 3109 u8 reserved_at_10[0x10]; 3110 3111 u8 reserved_at_20[0x100]; 3112 3113 u8 reserved_at_120[0x8]; 3114 u8 transport_domain[0x18]; 3115 3116 u8 reserved_at_140[0x8]; 3117 u8 underlay_qpn[0x18]; 3118 3119 u8 reserved_at_160[0x8]; 3120 u8 pd[0x18]; 3121 3122 u8 reserved_at_180[0x380]; 3123 }; 3124 3125 enum { 3126 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0, 3127 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1, 3128 }; 3129 3130 enum { 3131 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO = 0x1, 3132 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO = 0x2, 3133 }; 3134 3135 enum { 3136 MLX5_RX_HASH_FN_NONE = 0x0, 3137 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1, 3138 MLX5_RX_HASH_FN_TOEPLITZ = 0x2, 3139 }; 3140 3141 enum { 3142 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST = 0x1, 3143 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST = 0x2, 3144 }; 3145 3146 struct mlx5_ifc_tirc_bits { 3147 u8 reserved_at_0[0x20]; 3148 3149 u8 disp_type[0x4]; 3150 u8 tls_en[0x1]; 3151 u8 reserved_at_25[0x1b]; 3152 3153 u8 reserved_at_40[0x40]; 3154 3155 u8 reserved_at_80[0x4]; 3156 u8 lro_timeout_period_usecs[0x10]; 3157 u8 lro_enable_mask[0x4]; 3158 u8 lro_max_ip_payload_size[0x8]; 3159 3160 u8 reserved_at_a0[0x40]; 3161 3162 u8 reserved_at_e0[0x8]; 3163 u8 inline_rqn[0x18]; 3164 3165 u8 rx_hash_symmetric[0x1]; 3166 u8 reserved_at_101[0x1]; 3167 u8 tunneled_offload_en[0x1]; 3168 u8 reserved_at_103[0x5]; 3169 u8 indirect_table[0x18]; 3170 3171 u8 rx_hash_fn[0x4]; 3172 u8 reserved_at_124[0x2]; 3173 u8 self_lb_block[0x2]; 3174 u8 transport_domain[0x18]; 3175 3176 u8 rx_hash_toeplitz_key[10][0x20]; 3177 3178 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer; 3179 3180 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner; 3181 3182 u8 reserved_at_2c0[0x4c0]; 3183 }; 3184 3185 enum { 3186 MLX5_SRQC_STATE_GOOD = 0x0, 3187 MLX5_SRQC_STATE_ERROR = 0x1, 3188 }; 3189 3190 struct mlx5_ifc_srqc_bits { 3191 u8 state[0x4]; 3192 u8 log_srq_size[0x4]; 3193 u8 reserved_at_8[0x18]; 3194 3195 u8 wq_signature[0x1]; 3196 u8 cont_srq[0x1]; 3197 u8 reserved_at_22[0x1]; 3198 u8 rlky[0x1]; 3199 u8 reserved_at_24[0x1]; 3200 u8 log_rq_stride[0x3]; 3201 u8 xrcd[0x18]; 3202 3203 u8 page_offset[0x6]; 3204 u8 reserved_at_46[0x2]; 3205 u8 cqn[0x18]; 3206 3207 u8 reserved_at_60[0x20]; 3208 3209 u8 reserved_at_80[0x2]; 3210 u8 log_page_size[0x6]; 3211 u8 reserved_at_88[0x18]; 3212 3213 u8 reserved_at_a0[0x20]; 3214 3215 u8 reserved_at_c0[0x8]; 3216 u8 pd[0x18]; 3217 3218 u8 lwm[0x10]; 3219 u8 wqe_cnt[0x10]; 3220 3221 u8 reserved_at_100[0x40]; 3222 3223 u8 dbr_addr[0x40]; 3224 3225 u8 reserved_at_180[0x80]; 3226 }; 3227 3228 enum { 3229 MLX5_SQC_STATE_RST = 0x0, 3230 MLX5_SQC_STATE_RDY = 0x1, 3231 MLX5_SQC_STATE_ERR = 0x3, 3232 }; 3233 3234 struct mlx5_ifc_sqc_bits { 3235 u8 rlky[0x1]; 3236 u8 cd_master[0x1]; 3237 u8 fre[0x1]; 3238 u8 flush_in_error_en[0x1]; 3239 u8 allow_multi_pkt_send_wqe[0x1]; 3240 u8 min_wqe_inline_mode[0x3]; 3241 u8 state[0x4]; 3242 u8 reg_umr[0x1]; 3243 u8 allow_swp[0x1]; 3244 u8 hairpin[0x1]; 3245 u8 reserved_at_f[0x11]; 3246 3247 u8 reserved_at_20[0x8]; 3248 u8 user_index[0x18]; 3249 3250 u8 reserved_at_40[0x8]; 3251 u8 cqn[0x18]; 3252 3253 u8 reserved_at_60[0x8]; 3254 u8 hairpin_peer_rq[0x18]; 3255 3256 u8 reserved_at_80[0x10]; 3257 u8 hairpin_peer_vhca[0x10]; 3258 3259 u8 reserved_at_a0[0x50]; 3260 3261 u8 packet_pacing_rate_limit_index[0x10]; 3262 u8 tis_lst_sz[0x10]; 3263 u8 reserved_at_110[0x10]; 3264 3265 u8 reserved_at_120[0x40]; 3266 3267 u8 reserved_at_160[0x8]; 3268 u8 tis_num_0[0x18]; 3269 3270 struct mlx5_ifc_wq_bits wq; 3271 }; 3272 3273 enum { 3274 SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0, 3275 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1, 3276 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2, 3277 SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3, 3278 }; 3279 3280 enum { 3281 ELEMENT_TYPE_CAP_MASK_TASR = 1 << 0, 3282 ELEMENT_TYPE_CAP_MASK_VPORT = 1 << 1, 3283 ELEMENT_TYPE_CAP_MASK_VPORT_TC = 1 << 2, 3284 ELEMENT_TYPE_CAP_MASK_PARA_VPORT_TC = 1 << 3, 3285 }; 3286 3287 struct mlx5_ifc_scheduling_context_bits { 3288 u8 element_type[0x8]; 3289 u8 reserved_at_8[0x18]; 3290 3291 u8 element_attributes[0x20]; 3292 3293 u8 parent_element_id[0x20]; 3294 3295 u8 reserved_at_60[0x40]; 3296 3297 u8 bw_share[0x20]; 3298 3299 u8 max_average_bw[0x20]; 3300 3301 u8 reserved_at_e0[0x120]; 3302 }; 3303 3304 struct mlx5_ifc_rqtc_bits { 3305 u8 reserved_at_0[0xa0]; 3306 3307 u8 reserved_at_a0[0x10]; 3308 u8 rqt_max_size[0x10]; 3309 3310 u8 reserved_at_c0[0x10]; 3311 u8 rqt_actual_size[0x10]; 3312 3313 u8 reserved_at_e0[0x6a0]; 3314 3315 struct mlx5_ifc_rq_num_bits rq_num[]; 3316 }; 3317 3318 enum { 3319 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0, 3320 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1, 3321 }; 3322 3323 enum { 3324 MLX5_RQC_STATE_RST = 0x0, 3325 MLX5_RQC_STATE_RDY = 0x1, 3326 MLX5_RQC_STATE_ERR = 0x3, 3327 }; 3328 3329 struct mlx5_ifc_rqc_bits { 3330 u8 rlky[0x1]; 3331 u8 delay_drop_en[0x1]; 3332 u8 scatter_fcs[0x1]; 3333 u8 vsd[0x1]; 3334 u8 mem_rq_type[0x4]; 3335 u8 state[0x4]; 3336 u8 reserved_at_c[0x1]; 3337 u8 flush_in_error_en[0x1]; 3338 u8 hairpin[0x1]; 3339 u8 reserved_at_f[0x11]; 3340 3341 u8 reserved_at_20[0x8]; 3342 u8 user_index[0x18]; 3343 3344 u8 reserved_at_40[0x8]; 3345 u8 cqn[0x18]; 3346 3347 u8 counter_set_id[0x8]; 3348 u8 reserved_at_68[0x18]; 3349 3350 u8 reserved_at_80[0x8]; 3351 u8 rmpn[0x18]; 3352 3353 u8 reserved_at_a0[0x8]; 3354 u8 hairpin_peer_sq[0x18]; 3355 3356 u8 reserved_at_c0[0x10]; 3357 u8 hairpin_peer_vhca[0x10]; 3358 3359 u8 reserved_at_e0[0xa0]; 3360 3361 struct mlx5_ifc_wq_bits wq; 3362 }; 3363 3364 enum { 3365 MLX5_RMPC_STATE_RDY = 0x1, 3366 MLX5_RMPC_STATE_ERR = 0x3, 3367 }; 3368 3369 struct mlx5_ifc_rmpc_bits { 3370 u8 reserved_at_0[0x8]; 3371 u8 state[0x4]; 3372 u8 reserved_at_c[0x14]; 3373 3374 u8 basic_cyclic_rcv_wqe[0x1]; 3375 u8 reserved_at_21[0x1f]; 3376 3377 u8 reserved_at_40[0x140]; 3378 3379 struct mlx5_ifc_wq_bits wq; 3380 }; 3381 3382 struct mlx5_ifc_nic_vport_context_bits { 3383 u8 reserved_at_0[0x5]; 3384 u8 min_wqe_inline_mode[0x3]; 3385 u8 reserved_at_8[0x15]; 3386 u8 disable_mc_local_lb[0x1]; 3387 u8 disable_uc_local_lb[0x1]; 3388 u8 roce_en[0x1]; 3389 3390 u8 arm_change_event[0x1]; 3391 u8 reserved_at_21[0x1a]; 3392 u8 event_on_mtu[0x1]; 3393 u8 event_on_promisc_change[0x1]; 3394 u8 event_on_vlan_change[0x1]; 3395 u8 event_on_mc_address_change[0x1]; 3396 u8 event_on_uc_address_change[0x1]; 3397 3398 u8 reserved_at_40[0xc]; 3399 3400 u8 affiliation_criteria[0x4]; 3401 u8 affiliated_vhca_id[0x10]; 3402 3403 u8 reserved_at_60[0xd0]; 3404 3405 u8 mtu[0x10]; 3406 3407 u8 system_image_guid[0x40]; 3408 u8 port_guid[0x40]; 3409 u8 node_guid[0x40]; 3410 3411 u8 reserved_at_200[0x140]; 3412 u8 qkey_violation_counter[0x10]; 3413 u8 reserved_at_350[0x430]; 3414 3415 u8 promisc_uc[0x1]; 3416 u8 promisc_mc[0x1]; 3417 u8 promisc_all[0x1]; 3418 u8 reserved_at_783[0x2]; 3419 u8 allowed_list_type[0x3]; 3420 u8 reserved_at_788[0xc]; 3421 u8 allowed_list_size[0xc]; 3422 3423 struct mlx5_ifc_mac_address_layout_bits permanent_address; 3424 3425 u8 reserved_at_7e0[0x20]; 3426 3427 u8 current_uc_mac_address[][0x40]; 3428 }; 3429 3430 enum { 3431 MLX5_MKC_ACCESS_MODE_PA = 0x0, 3432 MLX5_MKC_ACCESS_MODE_MTT = 0x1, 3433 MLX5_MKC_ACCESS_MODE_KLMS = 0x2, 3434 MLX5_MKC_ACCESS_MODE_KSM = 0x3, 3435 MLX5_MKC_ACCESS_MODE_SW_ICM = 0x4, 3436 MLX5_MKC_ACCESS_MODE_MEMIC = 0x5, 3437 }; 3438 3439 struct mlx5_ifc_mkc_bits { 3440 u8 reserved_at_0[0x1]; 3441 u8 free[0x1]; 3442 u8 reserved_at_2[0x1]; 3443 u8 access_mode_4_2[0x3]; 3444 u8 reserved_at_6[0x7]; 3445 u8 relaxed_ordering_write[0x1]; 3446 u8 reserved_at_e[0x1]; 3447 u8 small_fence_on_rdma_read_response[0x1]; 3448 u8 umr_en[0x1]; 3449 u8 a[0x1]; 3450 u8 rw[0x1]; 3451 u8 rr[0x1]; 3452 u8 lw[0x1]; 3453 u8 lr[0x1]; 3454 u8 access_mode_1_0[0x2]; 3455 u8 reserved_at_18[0x8]; 3456 3457 u8 qpn[0x18]; 3458 u8 mkey_7_0[0x8]; 3459 3460 u8 reserved_at_40[0x20]; 3461 3462 u8 length64[0x1]; 3463 u8 bsf_en[0x1]; 3464 u8 sync_umr[0x1]; 3465 u8 reserved_at_63[0x2]; 3466 u8 expected_sigerr_count[0x1]; 3467 u8 reserved_at_66[0x1]; 3468 u8 en_rinval[0x1]; 3469 u8 pd[0x18]; 3470 3471 u8 start_addr[0x40]; 3472 3473 u8 len[0x40]; 3474 3475 u8 bsf_octword_size[0x20]; 3476 3477 u8 reserved_at_120[0x80]; 3478 3479 u8 translations_octword_size[0x20]; 3480 3481 u8 reserved_at_1c0[0x19]; 3482 u8 relaxed_ordering_read[0x1]; 3483 u8 reserved_at_1d9[0x1]; 3484 u8 log_page_size[0x5]; 3485 3486 u8 reserved_at_1e0[0x20]; 3487 }; 3488 3489 struct mlx5_ifc_pkey_bits { 3490 u8 reserved_at_0[0x10]; 3491 u8 pkey[0x10]; 3492 }; 3493 3494 struct mlx5_ifc_array128_auto_bits { 3495 u8 array128_auto[16][0x8]; 3496 }; 3497 3498 struct mlx5_ifc_hca_vport_context_bits { 3499 u8 field_select[0x20]; 3500 3501 u8 reserved_at_20[0xe0]; 3502 3503 u8 sm_virt_aware[0x1]; 3504 u8 has_smi[0x1]; 3505 u8 has_raw[0x1]; 3506 u8 grh_required[0x1]; 3507 u8 reserved_at_104[0xc]; 3508 u8 port_physical_state[0x4]; 3509 u8 vport_state_policy[0x4]; 3510 u8 port_state[0x4]; 3511 u8 vport_state[0x4]; 3512 3513 u8 reserved_at_120[0x20]; 3514 3515 u8 system_image_guid[0x40]; 3516 3517 u8 port_guid[0x40]; 3518 3519 u8 node_guid[0x40]; 3520 3521 u8 cap_mask1[0x20]; 3522 3523 u8 cap_mask1_field_select[0x20]; 3524 3525 u8 cap_mask2[0x20]; 3526 3527 u8 cap_mask2_field_select[0x20]; 3528 3529 u8 reserved_at_280[0x80]; 3530 3531 u8 lid[0x10]; 3532 u8 reserved_at_310[0x4]; 3533 u8 init_type_reply[0x4]; 3534 u8 lmc[0x3]; 3535 u8 subnet_timeout[0x5]; 3536 3537 u8 sm_lid[0x10]; 3538 u8 sm_sl[0x4]; 3539 u8 reserved_at_334[0xc]; 3540 3541 u8 qkey_violation_counter[0x10]; 3542 u8 pkey_violation_counter[0x10]; 3543 3544 u8 reserved_at_360[0xca0]; 3545 }; 3546 3547 struct mlx5_ifc_esw_vport_context_bits { 3548 u8 fdb_to_vport_reg_c[0x1]; 3549 u8 reserved_at_1[0x2]; 3550 u8 vport_svlan_strip[0x1]; 3551 u8 vport_cvlan_strip[0x1]; 3552 u8 vport_svlan_insert[0x1]; 3553 u8 vport_cvlan_insert[0x2]; 3554 u8 fdb_to_vport_reg_c_id[0x8]; 3555 u8 reserved_at_10[0x10]; 3556 3557 u8 reserved_at_20[0x20]; 3558 3559 u8 svlan_cfi[0x1]; 3560 u8 svlan_pcp[0x3]; 3561 u8 svlan_id[0xc]; 3562 u8 cvlan_cfi[0x1]; 3563 u8 cvlan_pcp[0x3]; 3564 u8 cvlan_id[0xc]; 3565 3566 u8 reserved_at_60[0x720]; 3567 3568 u8 sw_steering_vport_icm_address_rx[0x40]; 3569 3570 u8 sw_steering_vport_icm_address_tx[0x40]; 3571 }; 3572 3573 enum { 3574 MLX5_EQC_STATUS_OK = 0x0, 3575 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa, 3576 }; 3577 3578 enum { 3579 MLX5_EQC_ST_ARMED = 0x9, 3580 MLX5_EQC_ST_FIRED = 0xa, 3581 }; 3582 3583 struct mlx5_ifc_eqc_bits { 3584 u8 status[0x4]; 3585 u8 reserved_at_4[0x9]; 3586 u8 ec[0x1]; 3587 u8 oi[0x1]; 3588 u8 reserved_at_f[0x5]; 3589 u8 st[0x4]; 3590 u8 reserved_at_18[0x8]; 3591 3592 u8 reserved_at_20[0x20]; 3593 3594 u8 reserved_at_40[0x14]; 3595 u8 page_offset[0x6]; 3596 u8 reserved_at_5a[0x6]; 3597 3598 u8 reserved_at_60[0x3]; 3599 u8 log_eq_size[0x5]; 3600 u8 uar_page[0x18]; 3601 3602 u8 reserved_at_80[0x20]; 3603 3604 u8 reserved_at_a0[0x18]; 3605 u8 intr[0x8]; 3606 3607 u8 reserved_at_c0[0x3]; 3608 u8 log_page_size[0x5]; 3609 u8 reserved_at_c8[0x18]; 3610 3611 u8 reserved_at_e0[0x60]; 3612 3613 u8 reserved_at_140[0x8]; 3614 u8 consumer_counter[0x18]; 3615 3616 u8 reserved_at_160[0x8]; 3617 u8 producer_counter[0x18]; 3618 3619 u8 reserved_at_180[0x80]; 3620 }; 3621 3622 enum { 3623 MLX5_DCTC_STATE_ACTIVE = 0x0, 3624 MLX5_DCTC_STATE_DRAINING = 0x1, 3625 MLX5_DCTC_STATE_DRAINED = 0x2, 3626 }; 3627 3628 enum { 3629 MLX5_DCTC_CS_RES_DISABLE = 0x0, 3630 MLX5_DCTC_CS_RES_NA = 0x1, 3631 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2, 3632 }; 3633 3634 enum { 3635 MLX5_DCTC_MTU_256_BYTES = 0x1, 3636 MLX5_DCTC_MTU_512_BYTES = 0x2, 3637 MLX5_DCTC_MTU_1K_BYTES = 0x3, 3638 MLX5_DCTC_MTU_2K_BYTES = 0x4, 3639 MLX5_DCTC_MTU_4K_BYTES = 0x5, 3640 }; 3641 3642 struct mlx5_ifc_dctc_bits { 3643 u8 reserved_at_0[0x4]; 3644 u8 state[0x4]; 3645 u8 reserved_at_8[0x18]; 3646 3647 u8 reserved_at_20[0x8]; 3648 u8 user_index[0x18]; 3649 3650 u8 reserved_at_40[0x8]; 3651 u8 cqn[0x18]; 3652 3653 u8 counter_set_id[0x8]; 3654 u8 atomic_mode[0x4]; 3655 u8 rre[0x1]; 3656 u8 rwe[0x1]; 3657 u8 rae[0x1]; 3658 u8 atomic_like_write_en[0x1]; 3659 u8 latency_sensitive[0x1]; 3660 u8 rlky[0x1]; 3661 u8 free_ar[0x1]; 3662 u8 reserved_at_73[0xd]; 3663 3664 u8 reserved_at_80[0x8]; 3665 u8 cs_res[0x8]; 3666 u8 reserved_at_90[0x3]; 3667 u8 min_rnr_nak[0x5]; 3668 u8 reserved_at_98[0x8]; 3669 3670 u8 reserved_at_a0[0x8]; 3671 u8 srqn_xrqn[0x18]; 3672 3673 u8 reserved_at_c0[0x8]; 3674 u8 pd[0x18]; 3675 3676 u8 tclass[0x8]; 3677 u8 reserved_at_e8[0x4]; 3678 u8 flow_label[0x14]; 3679 3680 u8 dc_access_key[0x40]; 3681 3682 u8 reserved_at_140[0x5]; 3683 u8 mtu[0x3]; 3684 u8 port[0x8]; 3685 u8 pkey_index[0x10]; 3686 3687 u8 reserved_at_160[0x8]; 3688 u8 my_addr_index[0x8]; 3689 u8 reserved_at_170[0x8]; 3690 u8 hop_limit[0x8]; 3691 3692 u8 dc_access_key_violation_count[0x20]; 3693 3694 u8 reserved_at_1a0[0x14]; 3695 u8 dei_cfi[0x1]; 3696 u8 eth_prio[0x3]; 3697 u8 ecn[0x2]; 3698 u8 dscp[0x6]; 3699 3700 u8 reserved_at_1c0[0x20]; 3701 u8 ece[0x20]; 3702 }; 3703 3704 enum { 3705 MLX5_CQC_STATUS_OK = 0x0, 3706 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9, 3707 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa, 3708 }; 3709 3710 enum { 3711 MLX5_CQC_CQE_SZ_64_BYTES = 0x0, 3712 MLX5_CQC_CQE_SZ_128_BYTES = 0x1, 3713 }; 3714 3715 enum { 3716 MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED = 0x6, 3717 MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED = 0x9, 3718 MLX5_CQC_ST_FIRED = 0xa, 3719 }; 3720 3721 enum { 3722 MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0, 3723 MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1, 3724 MLX5_CQ_PERIOD_NUM_MODES 3725 }; 3726 3727 struct mlx5_ifc_cqc_bits { 3728 u8 status[0x4]; 3729 u8 reserved_at_4[0x2]; 3730 u8 dbr_umem_valid[0x1]; 3731 u8 reserved_at_7[0x1]; 3732 u8 cqe_sz[0x3]; 3733 u8 cc[0x1]; 3734 u8 reserved_at_c[0x1]; 3735 u8 scqe_break_moderation_en[0x1]; 3736 u8 oi[0x1]; 3737 u8 cq_period_mode[0x2]; 3738 u8 cqe_comp_en[0x1]; 3739 u8 mini_cqe_res_format[0x2]; 3740 u8 st[0x4]; 3741 u8 reserved_at_18[0x8]; 3742 3743 u8 reserved_at_20[0x20]; 3744 3745 u8 reserved_at_40[0x14]; 3746 u8 page_offset[0x6]; 3747 u8 reserved_at_5a[0x6]; 3748 3749 u8 reserved_at_60[0x3]; 3750 u8 log_cq_size[0x5]; 3751 u8 uar_page[0x18]; 3752 3753 u8 reserved_at_80[0x4]; 3754 u8 cq_period[0xc]; 3755 u8 cq_max_count[0x10]; 3756 3757 u8 reserved_at_a0[0x18]; 3758 u8 c_eqn[0x8]; 3759 3760 u8 reserved_at_c0[0x3]; 3761 u8 log_page_size[0x5]; 3762 u8 reserved_at_c8[0x18]; 3763 3764 u8 reserved_at_e0[0x20]; 3765 3766 u8 reserved_at_100[0x8]; 3767 u8 last_notified_index[0x18]; 3768 3769 u8 reserved_at_120[0x8]; 3770 u8 last_solicit_index[0x18]; 3771 3772 u8 reserved_at_140[0x8]; 3773 u8 consumer_counter[0x18]; 3774 3775 u8 reserved_at_160[0x8]; 3776 u8 producer_counter[0x18]; 3777 3778 u8 reserved_at_180[0x40]; 3779 3780 u8 dbr_addr[0x40]; 3781 }; 3782 3783 union mlx5_ifc_cong_control_roce_ecn_auto_bits { 3784 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp; 3785 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp; 3786 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np; 3787 u8 reserved_at_0[0x800]; 3788 }; 3789 3790 struct mlx5_ifc_query_adapter_param_block_bits { 3791 u8 reserved_at_0[0xc0]; 3792 3793 u8 reserved_at_c0[0x8]; 3794 u8 ieee_vendor_id[0x18]; 3795 3796 u8 reserved_at_e0[0x10]; 3797 u8 vsd_vendor_id[0x10]; 3798 3799 u8 vsd[208][0x8]; 3800 3801 u8 vsd_contd_psid[16][0x8]; 3802 }; 3803 3804 enum { 3805 MLX5_XRQC_STATE_GOOD = 0x0, 3806 MLX5_XRQC_STATE_ERROR = 0x1, 3807 }; 3808 3809 enum { 3810 MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0, 3811 MLX5_XRQC_TOPOLOGY_TAG_MATCHING = 0x1, 3812 }; 3813 3814 enum { 3815 MLX5_XRQC_OFFLOAD_RNDV = 0x1, 3816 }; 3817 3818 struct mlx5_ifc_tag_matching_topology_context_bits { 3819 u8 log_matching_list_sz[0x4]; 3820 u8 reserved_at_4[0xc]; 3821 u8 append_next_index[0x10]; 3822 3823 u8 sw_phase_cnt[0x10]; 3824 u8 hw_phase_cnt[0x10]; 3825 3826 u8 reserved_at_40[0x40]; 3827 }; 3828 3829 struct mlx5_ifc_xrqc_bits { 3830 u8 state[0x4]; 3831 u8 rlkey[0x1]; 3832 u8 reserved_at_5[0xf]; 3833 u8 topology[0x4]; 3834 u8 reserved_at_18[0x4]; 3835 u8 offload[0x4]; 3836 3837 u8 reserved_at_20[0x8]; 3838 u8 user_index[0x18]; 3839 3840 u8 reserved_at_40[0x8]; 3841 u8 cqn[0x18]; 3842 3843 u8 reserved_at_60[0xa0]; 3844 3845 struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context; 3846 3847 u8 reserved_at_180[0x280]; 3848 3849 struct mlx5_ifc_wq_bits wq; 3850 }; 3851 3852 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits { 3853 struct mlx5_ifc_modify_field_select_bits modify_field_select; 3854 struct mlx5_ifc_resize_field_select_bits resize_field_select; 3855 u8 reserved_at_0[0x20]; 3856 }; 3857 3858 union mlx5_ifc_field_select_802_1_r_roce_auto_bits { 3859 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp; 3860 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp; 3861 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np; 3862 u8 reserved_at_0[0x20]; 3863 }; 3864 3865 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits { 3866 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 3867 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 3868 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 3869 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 3870 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 3871 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 3872 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout; 3873 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout; 3874 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 3875 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 3876 struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs; 3877 u8 reserved_at_0[0x7c0]; 3878 }; 3879 3880 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits { 3881 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout; 3882 u8 reserved_at_0[0x7c0]; 3883 }; 3884 3885 union mlx5_ifc_event_auto_bits { 3886 struct mlx5_ifc_comp_event_bits comp_event; 3887 struct mlx5_ifc_dct_events_bits dct_events; 3888 struct mlx5_ifc_qp_events_bits qp_events; 3889 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event; 3890 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event; 3891 struct mlx5_ifc_cq_error_bits cq_error; 3892 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged; 3893 struct mlx5_ifc_port_state_change_event_bits port_state_change_event; 3894 struct mlx5_ifc_gpio_event_bits gpio_event; 3895 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event; 3896 struct mlx5_ifc_stall_vl_event_bits stall_vl_event; 3897 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event; 3898 u8 reserved_at_0[0xe0]; 3899 }; 3900 3901 struct mlx5_ifc_health_buffer_bits { 3902 u8 reserved_at_0[0x100]; 3903 3904 u8 assert_existptr[0x20]; 3905 3906 u8 assert_callra[0x20]; 3907 3908 u8 reserved_at_140[0x40]; 3909 3910 u8 fw_version[0x20]; 3911 3912 u8 hw_id[0x20]; 3913 3914 u8 reserved_at_1c0[0x20]; 3915 3916 u8 irisc_index[0x8]; 3917 u8 synd[0x8]; 3918 u8 ext_synd[0x10]; 3919 }; 3920 3921 struct mlx5_ifc_register_loopback_control_bits { 3922 u8 no_lb[0x1]; 3923 u8 reserved_at_1[0x7]; 3924 u8 port[0x8]; 3925 u8 reserved_at_10[0x10]; 3926 3927 u8 reserved_at_20[0x60]; 3928 }; 3929 3930 struct mlx5_ifc_vport_tc_element_bits { 3931 u8 traffic_class[0x4]; 3932 u8 reserved_at_4[0xc]; 3933 u8 vport_number[0x10]; 3934 }; 3935 3936 struct mlx5_ifc_vport_element_bits { 3937 u8 reserved_at_0[0x10]; 3938 u8 vport_number[0x10]; 3939 }; 3940 3941 enum { 3942 TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0, 3943 TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1, 3944 TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2, 3945 }; 3946 3947 struct mlx5_ifc_tsar_element_bits { 3948 u8 reserved_at_0[0x8]; 3949 u8 tsar_type[0x8]; 3950 u8 reserved_at_10[0x10]; 3951 }; 3952 3953 enum { 3954 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0, 3955 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1, 3956 }; 3957 3958 struct mlx5_ifc_teardown_hca_out_bits { 3959 u8 status[0x8]; 3960 u8 reserved_at_8[0x18]; 3961 3962 u8 syndrome[0x20]; 3963 3964 u8 reserved_at_40[0x3f]; 3965 3966 u8 state[0x1]; 3967 }; 3968 3969 enum { 3970 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0, 3971 MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE = 0x1, 3972 MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN = 0x2, 3973 }; 3974 3975 struct mlx5_ifc_teardown_hca_in_bits { 3976 u8 opcode[0x10]; 3977 u8 reserved_at_10[0x10]; 3978 3979 u8 reserved_at_20[0x10]; 3980 u8 op_mod[0x10]; 3981 3982 u8 reserved_at_40[0x10]; 3983 u8 profile[0x10]; 3984 3985 u8 reserved_at_60[0x20]; 3986 }; 3987 3988 struct mlx5_ifc_sqerr2rts_qp_out_bits { 3989 u8 status[0x8]; 3990 u8 reserved_at_8[0x18]; 3991 3992 u8 syndrome[0x20]; 3993 3994 u8 reserved_at_40[0x40]; 3995 }; 3996 3997 struct mlx5_ifc_sqerr2rts_qp_in_bits { 3998 u8 opcode[0x10]; 3999 u8 uid[0x10]; 4000 4001 u8 reserved_at_20[0x10]; 4002 u8 op_mod[0x10]; 4003 4004 u8 reserved_at_40[0x8]; 4005 u8 qpn[0x18]; 4006 4007 u8 reserved_at_60[0x20]; 4008 4009 u8 opt_param_mask[0x20]; 4010 4011 u8 reserved_at_a0[0x20]; 4012 4013 struct mlx5_ifc_qpc_bits qpc; 4014 4015 u8 reserved_at_800[0x80]; 4016 }; 4017 4018 struct mlx5_ifc_sqd2rts_qp_out_bits { 4019 u8 status[0x8]; 4020 u8 reserved_at_8[0x18]; 4021 4022 u8 syndrome[0x20]; 4023 4024 u8 reserved_at_40[0x40]; 4025 }; 4026 4027 struct mlx5_ifc_sqd2rts_qp_in_bits { 4028 u8 opcode[0x10]; 4029 u8 uid[0x10]; 4030 4031 u8 reserved_at_20[0x10]; 4032 u8 op_mod[0x10]; 4033 4034 u8 reserved_at_40[0x8]; 4035 u8 qpn[0x18]; 4036 4037 u8 reserved_at_60[0x20]; 4038 4039 u8 opt_param_mask[0x20]; 4040 4041 u8 reserved_at_a0[0x20]; 4042 4043 struct mlx5_ifc_qpc_bits qpc; 4044 4045 u8 reserved_at_800[0x80]; 4046 }; 4047 4048 struct mlx5_ifc_set_roce_address_out_bits { 4049 u8 status[0x8]; 4050 u8 reserved_at_8[0x18]; 4051 4052 u8 syndrome[0x20]; 4053 4054 u8 reserved_at_40[0x40]; 4055 }; 4056 4057 struct mlx5_ifc_set_roce_address_in_bits { 4058 u8 opcode[0x10]; 4059 u8 reserved_at_10[0x10]; 4060 4061 u8 reserved_at_20[0x10]; 4062 u8 op_mod[0x10]; 4063 4064 u8 roce_address_index[0x10]; 4065 u8 reserved_at_50[0xc]; 4066 u8 vhca_port_num[0x4]; 4067 4068 u8 reserved_at_60[0x20]; 4069 4070 struct mlx5_ifc_roce_addr_layout_bits roce_address; 4071 }; 4072 4073 struct mlx5_ifc_set_mad_demux_out_bits { 4074 u8 status[0x8]; 4075 u8 reserved_at_8[0x18]; 4076 4077 u8 syndrome[0x20]; 4078 4079 u8 reserved_at_40[0x40]; 4080 }; 4081 4082 enum { 4083 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0, 4084 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2, 4085 }; 4086 4087 struct mlx5_ifc_set_mad_demux_in_bits { 4088 u8 opcode[0x10]; 4089 u8 reserved_at_10[0x10]; 4090 4091 u8 reserved_at_20[0x10]; 4092 u8 op_mod[0x10]; 4093 4094 u8 reserved_at_40[0x20]; 4095 4096 u8 reserved_at_60[0x6]; 4097 u8 demux_mode[0x2]; 4098 u8 reserved_at_68[0x18]; 4099 }; 4100 4101 struct mlx5_ifc_set_l2_table_entry_out_bits { 4102 u8 status[0x8]; 4103 u8 reserved_at_8[0x18]; 4104 4105 u8 syndrome[0x20]; 4106 4107 u8 reserved_at_40[0x40]; 4108 }; 4109 4110 struct mlx5_ifc_set_l2_table_entry_in_bits { 4111 u8 opcode[0x10]; 4112 u8 reserved_at_10[0x10]; 4113 4114 u8 reserved_at_20[0x10]; 4115 u8 op_mod[0x10]; 4116 4117 u8 reserved_at_40[0x60]; 4118 4119 u8 reserved_at_a0[0x8]; 4120 u8 table_index[0x18]; 4121 4122 u8 reserved_at_c0[0x20]; 4123 4124 u8 reserved_at_e0[0x13]; 4125 u8 vlan_valid[0x1]; 4126 u8 vlan[0xc]; 4127 4128 struct mlx5_ifc_mac_address_layout_bits mac_address; 4129 4130 u8 reserved_at_140[0xc0]; 4131 }; 4132 4133 struct mlx5_ifc_set_issi_out_bits { 4134 u8 status[0x8]; 4135 u8 reserved_at_8[0x18]; 4136 4137 u8 syndrome[0x20]; 4138 4139 u8 reserved_at_40[0x40]; 4140 }; 4141 4142 struct mlx5_ifc_set_issi_in_bits { 4143 u8 opcode[0x10]; 4144 u8 reserved_at_10[0x10]; 4145 4146 u8 reserved_at_20[0x10]; 4147 u8 op_mod[0x10]; 4148 4149 u8 reserved_at_40[0x10]; 4150 u8 current_issi[0x10]; 4151 4152 u8 reserved_at_60[0x20]; 4153 }; 4154 4155 struct mlx5_ifc_set_hca_cap_out_bits { 4156 u8 status[0x8]; 4157 u8 reserved_at_8[0x18]; 4158 4159 u8 syndrome[0x20]; 4160 4161 u8 reserved_at_40[0x40]; 4162 }; 4163 4164 struct mlx5_ifc_set_hca_cap_in_bits { 4165 u8 opcode[0x10]; 4166 u8 reserved_at_10[0x10]; 4167 4168 u8 reserved_at_20[0x10]; 4169 u8 op_mod[0x10]; 4170 4171 u8 reserved_at_40[0x40]; 4172 4173 union mlx5_ifc_hca_cap_union_bits capability; 4174 }; 4175 4176 enum { 4177 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0, 4178 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1, 4179 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2, 4180 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3, 4181 MLX5_SET_FTE_MODIFY_ENABLE_MASK_IPSEC_OBJ_ID = 0x4 4182 }; 4183 4184 struct mlx5_ifc_set_fte_out_bits { 4185 u8 status[0x8]; 4186 u8 reserved_at_8[0x18]; 4187 4188 u8 syndrome[0x20]; 4189 4190 u8 reserved_at_40[0x40]; 4191 }; 4192 4193 struct mlx5_ifc_set_fte_in_bits { 4194 u8 opcode[0x10]; 4195 u8 reserved_at_10[0x10]; 4196 4197 u8 reserved_at_20[0x10]; 4198 u8 op_mod[0x10]; 4199 4200 u8 other_vport[0x1]; 4201 u8 reserved_at_41[0xf]; 4202 u8 vport_number[0x10]; 4203 4204 u8 reserved_at_60[0x20]; 4205 4206 u8 table_type[0x8]; 4207 u8 reserved_at_88[0x18]; 4208 4209 u8 reserved_at_a0[0x8]; 4210 u8 table_id[0x18]; 4211 4212 u8 ignore_flow_level[0x1]; 4213 u8 reserved_at_c1[0x17]; 4214 u8 modify_enable_mask[0x8]; 4215 4216 u8 reserved_at_e0[0x20]; 4217 4218 u8 flow_index[0x20]; 4219 4220 u8 reserved_at_120[0xe0]; 4221 4222 struct mlx5_ifc_flow_context_bits flow_context; 4223 }; 4224 4225 struct mlx5_ifc_rts2rts_qp_out_bits { 4226 u8 status[0x8]; 4227 u8 reserved_at_8[0x18]; 4228 4229 u8 syndrome[0x20]; 4230 4231 u8 reserved_at_40[0x20]; 4232 u8 ece[0x20]; 4233 }; 4234 4235 struct mlx5_ifc_rts2rts_qp_in_bits { 4236 u8 opcode[0x10]; 4237 u8 uid[0x10]; 4238 4239 u8 reserved_at_20[0x10]; 4240 u8 op_mod[0x10]; 4241 4242 u8 reserved_at_40[0x8]; 4243 u8 qpn[0x18]; 4244 4245 u8 reserved_at_60[0x20]; 4246 4247 u8 opt_param_mask[0x20]; 4248 4249 u8 ece[0x20]; 4250 4251 struct mlx5_ifc_qpc_bits qpc; 4252 4253 u8 reserved_at_800[0x80]; 4254 }; 4255 4256 struct mlx5_ifc_rtr2rts_qp_out_bits { 4257 u8 status[0x8]; 4258 u8 reserved_at_8[0x18]; 4259 4260 u8 syndrome[0x20]; 4261 4262 u8 reserved_at_40[0x20]; 4263 u8 ece[0x20]; 4264 }; 4265 4266 struct mlx5_ifc_rtr2rts_qp_in_bits { 4267 u8 opcode[0x10]; 4268 u8 uid[0x10]; 4269 4270 u8 reserved_at_20[0x10]; 4271 u8 op_mod[0x10]; 4272 4273 u8 reserved_at_40[0x8]; 4274 u8 qpn[0x18]; 4275 4276 u8 reserved_at_60[0x20]; 4277 4278 u8 opt_param_mask[0x20]; 4279 4280 u8 ece[0x20]; 4281 4282 struct mlx5_ifc_qpc_bits qpc; 4283 4284 u8 reserved_at_800[0x80]; 4285 }; 4286 4287 struct mlx5_ifc_rst2init_qp_out_bits { 4288 u8 status[0x8]; 4289 u8 reserved_at_8[0x18]; 4290 4291 u8 syndrome[0x20]; 4292 4293 u8 reserved_at_40[0x20]; 4294 u8 ece[0x20]; 4295 }; 4296 4297 struct mlx5_ifc_rst2init_qp_in_bits { 4298 u8 opcode[0x10]; 4299 u8 uid[0x10]; 4300 4301 u8 reserved_at_20[0x10]; 4302 u8 op_mod[0x10]; 4303 4304 u8 reserved_at_40[0x8]; 4305 u8 qpn[0x18]; 4306 4307 u8 reserved_at_60[0x20]; 4308 4309 u8 opt_param_mask[0x20]; 4310 4311 u8 ece[0x20]; 4312 4313 struct mlx5_ifc_qpc_bits qpc; 4314 4315 u8 reserved_at_800[0x80]; 4316 }; 4317 4318 struct mlx5_ifc_query_xrq_out_bits { 4319 u8 status[0x8]; 4320 u8 reserved_at_8[0x18]; 4321 4322 u8 syndrome[0x20]; 4323 4324 u8 reserved_at_40[0x40]; 4325 4326 struct mlx5_ifc_xrqc_bits xrq_context; 4327 }; 4328 4329 struct mlx5_ifc_query_xrq_in_bits { 4330 u8 opcode[0x10]; 4331 u8 reserved_at_10[0x10]; 4332 4333 u8 reserved_at_20[0x10]; 4334 u8 op_mod[0x10]; 4335 4336 u8 reserved_at_40[0x8]; 4337 u8 xrqn[0x18]; 4338 4339 u8 reserved_at_60[0x20]; 4340 }; 4341 4342 struct mlx5_ifc_query_xrc_srq_out_bits { 4343 u8 status[0x8]; 4344 u8 reserved_at_8[0x18]; 4345 4346 u8 syndrome[0x20]; 4347 4348 u8 reserved_at_40[0x40]; 4349 4350 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 4351 4352 u8 reserved_at_280[0x600]; 4353 4354 u8 pas[][0x40]; 4355 }; 4356 4357 struct mlx5_ifc_query_xrc_srq_in_bits { 4358 u8 opcode[0x10]; 4359 u8 reserved_at_10[0x10]; 4360 4361 u8 reserved_at_20[0x10]; 4362 u8 op_mod[0x10]; 4363 4364 u8 reserved_at_40[0x8]; 4365 u8 xrc_srqn[0x18]; 4366 4367 u8 reserved_at_60[0x20]; 4368 }; 4369 4370 enum { 4371 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0, 4372 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1, 4373 }; 4374 4375 struct mlx5_ifc_query_vport_state_out_bits { 4376 u8 status[0x8]; 4377 u8 reserved_at_8[0x18]; 4378 4379 u8 syndrome[0x20]; 4380 4381 u8 reserved_at_40[0x20]; 4382 4383 u8 reserved_at_60[0x18]; 4384 u8 admin_state[0x4]; 4385 u8 state[0x4]; 4386 }; 4387 4388 enum { 4389 MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT = 0x0, 4390 MLX5_VPORT_STATE_OP_MOD_ESW_VPORT = 0x1, 4391 MLX5_VPORT_STATE_OP_MOD_UPLINK = 0x2, 4392 }; 4393 4394 struct mlx5_ifc_arm_monitor_counter_in_bits { 4395 u8 opcode[0x10]; 4396 u8 uid[0x10]; 4397 4398 u8 reserved_at_20[0x10]; 4399 u8 op_mod[0x10]; 4400 4401 u8 reserved_at_40[0x20]; 4402 4403 u8 reserved_at_60[0x20]; 4404 }; 4405 4406 struct mlx5_ifc_arm_monitor_counter_out_bits { 4407 u8 status[0x8]; 4408 u8 reserved_at_8[0x18]; 4409 4410 u8 syndrome[0x20]; 4411 4412 u8 reserved_at_40[0x40]; 4413 }; 4414 4415 enum { 4416 MLX5_QUERY_MONITOR_CNT_TYPE_PPCNT = 0x0, 4417 MLX5_QUERY_MONITOR_CNT_TYPE_Q_COUNTER = 0x1, 4418 }; 4419 4420 enum mlx5_monitor_counter_ppcnt { 4421 MLX5_QUERY_MONITOR_PPCNT_IN_RANGE_LENGTH_ERRORS = 0x0, 4422 MLX5_QUERY_MONITOR_PPCNT_OUT_OF_RANGE_LENGTH_FIELD = 0x1, 4423 MLX5_QUERY_MONITOR_PPCNT_FRAME_TOO_LONG_ERRORS = 0x2, 4424 MLX5_QUERY_MONITOR_PPCNT_FRAME_CHECK_SEQUENCE_ERRORS = 0x3, 4425 MLX5_QUERY_MONITOR_PPCNT_ALIGNMENT_ERRORS = 0x4, 4426 MLX5_QUERY_MONITOR_PPCNT_IF_OUT_DISCARDS = 0x5, 4427 }; 4428 4429 enum { 4430 MLX5_QUERY_MONITOR_Q_COUNTER_RX_OUT_OF_BUFFER = 0x4, 4431 }; 4432 4433 struct mlx5_ifc_monitor_counter_output_bits { 4434 u8 reserved_at_0[0x4]; 4435 u8 type[0x4]; 4436 u8 reserved_at_8[0x8]; 4437 u8 counter[0x10]; 4438 4439 u8 counter_group_id[0x20]; 4440 }; 4441 4442 #define MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 (6) 4443 #define MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1 (1) 4444 #define MLX5_CMD_SET_MONITOR_NUM_COUNTER (MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 +\ 4445 MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1) 4446 4447 struct mlx5_ifc_set_monitor_counter_in_bits { 4448 u8 opcode[0x10]; 4449 u8 uid[0x10]; 4450 4451 u8 reserved_at_20[0x10]; 4452 u8 op_mod[0x10]; 4453 4454 u8 reserved_at_40[0x10]; 4455 u8 num_of_counters[0x10]; 4456 4457 u8 reserved_at_60[0x20]; 4458 4459 struct mlx5_ifc_monitor_counter_output_bits monitor_counter[MLX5_CMD_SET_MONITOR_NUM_COUNTER]; 4460 }; 4461 4462 struct mlx5_ifc_set_monitor_counter_out_bits { 4463 u8 status[0x8]; 4464 u8 reserved_at_8[0x18]; 4465 4466 u8 syndrome[0x20]; 4467 4468 u8 reserved_at_40[0x40]; 4469 }; 4470 4471 struct mlx5_ifc_query_vport_state_in_bits { 4472 u8 opcode[0x10]; 4473 u8 reserved_at_10[0x10]; 4474 4475 u8 reserved_at_20[0x10]; 4476 u8 op_mod[0x10]; 4477 4478 u8 other_vport[0x1]; 4479 u8 reserved_at_41[0xf]; 4480 u8 vport_number[0x10]; 4481 4482 u8 reserved_at_60[0x20]; 4483 }; 4484 4485 struct mlx5_ifc_query_vnic_env_out_bits { 4486 u8 status[0x8]; 4487 u8 reserved_at_8[0x18]; 4488 4489 u8 syndrome[0x20]; 4490 4491 u8 reserved_at_40[0x40]; 4492 4493 struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env; 4494 }; 4495 4496 enum { 4497 MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS = 0x0, 4498 }; 4499 4500 struct mlx5_ifc_query_vnic_env_in_bits { 4501 u8 opcode[0x10]; 4502 u8 reserved_at_10[0x10]; 4503 4504 u8 reserved_at_20[0x10]; 4505 u8 op_mod[0x10]; 4506 4507 u8 other_vport[0x1]; 4508 u8 reserved_at_41[0xf]; 4509 u8 vport_number[0x10]; 4510 4511 u8 reserved_at_60[0x20]; 4512 }; 4513 4514 struct mlx5_ifc_query_vport_counter_out_bits { 4515 u8 status[0x8]; 4516 u8 reserved_at_8[0x18]; 4517 4518 u8 syndrome[0x20]; 4519 4520 u8 reserved_at_40[0x40]; 4521 4522 struct mlx5_ifc_traffic_counter_bits received_errors; 4523 4524 struct mlx5_ifc_traffic_counter_bits transmit_errors; 4525 4526 struct mlx5_ifc_traffic_counter_bits received_ib_unicast; 4527 4528 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast; 4529 4530 struct mlx5_ifc_traffic_counter_bits received_ib_multicast; 4531 4532 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast; 4533 4534 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast; 4535 4536 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast; 4537 4538 struct mlx5_ifc_traffic_counter_bits received_eth_unicast; 4539 4540 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast; 4541 4542 struct mlx5_ifc_traffic_counter_bits received_eth_multicast; 4543 4544 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast; 4545 4546 u8 reserved_at_680[0xa00]; 4547 }; 4548 4549 enum { 4550 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0, 4551 }; 4552 4553 struct mlx5_ifc_query_vport_counter_in_bits { 4554 u8 opcode[0x10]; 4555 u8 reserved_at_10[0x10]; 4556 4557 u8 reserved_at_20[0x10]; 4558 u8 op_mod[0x10]; 4559 4560 u8 other_vport[0x1]; 4561 u8 reserved_at_41[0xb]; 4562 u8 port_num[0x4]; 4563 u8 vport_number[0x10]; 4564 4565 u8 reserved_at_60[0x60]; 4566 4567 u8 clear[0x1]; 4568 u8 reserved_at_c1[0x1f]; 4569 4570 u8 reserved_at_e0[0x20]; 4571 }; 4572 4573 struct mlx5_ifc_query_tis_out_bits { 4574 u8 status[0x8]; 4575 u8 reserved_at_8[0x18]; 4576 4577 u8 syndrome[0x20]; 4578 4579 u8 reserved_at_40[0x40]; 4580 4581 struct mlx5_ifc_tisc_bits tis_context; 4582 }; 4583 4584 struct mlx5_ifc_query_tis_in_bits { 4585 u8 opcode[0x10]; 4586 u8 reserved_at_10[0x10]; 4587 4588 u8 reserved_at_20[0x10]; 4589 u8 op_mod[0x10]; 4590 4591 u8 reserved_at_40[0x8]; 4592 u8 tisn[0x18]; 4593 4594 u8 reserved_at_60[0x20]; 4595 }; 4596 4597 struct mlx5_ifc_query_tir_out_bits { 4598 u8 status[0x8]; 4599 u8 reserved_at_8[0x18]; 4600 4601 u8 syndrome[0x20]; 4602 4603 u8 reserved_at_40[0xc0]; 4604 4605 struct mlx5_ifc_tirc_bits tir_context; 4606 }; 4607 4608 struct mlx5_ifc_query_tir_in_bits { 4609 u8 opcode[0x10]; 4610 u8 reserved_at_10[0x10]; 4611 4612 u8 reserved_at_20[0x10]; 4613 u8 op_mod[0x10]; 4614 4615 u8 reserved_at_40[0x8]; 4616 u8 tirn[0x18]; 4617 4618 u8 reserved_at_60[0x20]; 4619 }; 4620 4621 struct mlx5_ifc_query_srq_out_bits { 4622 u8 status[0x8]; 4623 u8 reserved_at_8[0x18]; 4624 4625 u8 syndrome[0x20]; 4626 4627 u8 reserved_at_40[0x40]; 4628 4629 struct mlx5_ifc_srqc_bits srq_context_entry; 4630 4631 u8 reserved_at_280[0x600]; 4632 4633 u8 pas[][0x40]; 4634 }; 4635 4636 struct mlx5_ifc_query_srq_in_bits { 4637 u8 opcode[0x10]; 4638 u8 reserved_at_10[0x10]; 4639 4640 u8 reserved_at_20[0x10]; 4641 u8 op_mod[0x10]; 4642 4643 u8 reserved_at_40[0x8]; 4644 u8 srqn[0x18]; 4645 4646 u8 reserved_at_60[0x20]; 4647 }; 4648 4649 struct mlx5_ifc_query_sq_out_bits { 4650 u8 status[0x8]; 4651 u8 reserved_at_8[0x18]; 4652 4653 u8 syndrome[0x20]; 4654 4655 u8 reserved_at_40[0xc0]; 4656 4657 struct mlx5_ifc_sqc_bits sq_context; 4658 }; 4659 4660 struct mlx5_ifc_query_sq_in_bits { 4661 u8 opcode[0x10]; 4662 u8 reserved_at_10[0x10]; 4663 4664 u8 reserved_at_20[0x10]; 4665 u8 op_mod[0x10]; 4666 4667 u8 reserved_at_40[0x8]; 4668 u8 sqn[0x18]; 4669 4670 u8 reserved_at_60[0x20]; 4671 }; 4672 4673 struct mlx5_ifc_query_special_contexts_out_bits { 4674 u8 status[0x8]; 4675 u8 reserved_at_8[0x18]; 4676 4677 u8 syndrome[0x20]; 4678 4679 u8 dump_fill_mkey[0x20]; 4680 4681 u8 resd_lkey[0x20]; 4682 4683 u8 null_mkey[0x20]; 4684 4685 u8 reserved_at_a0[0x60]; 4686 }; 4687 4688 struct mlx5_ifc_query_special_contexts_in_bits { 4689 u8 opcode[0x10]; 4690 u8 reserved_at_10[0x10]; 4691 4692 u8 reserved_at_20[0x10]; 4693 u8 op_mod[0x10]; 4694 4695 u8 reserved_at_40[0x40]; 4696 }; 4697 4698 struct mlx5_ifc_query_scheduling_element_out_bits { 4699 u8 opcode[0x10]; 4700 u8 reserved_at_10[0x10]; 4701 4702 u8 reserved_at_20[0x10]; 4703 u8 op_mod[0x10]; 4704 4705 u8 reserved_at_40[0xc0]; 4706 4707 struct mlx5_ifc_scheduling_context_bits scheduling_context; 4708 4709 u8 reserved_at_300[0x100]; 4710 }; 4711 4712 enum { 4713 SCHEDULING_HIERARCHY_E_SWITCH = 0x2, 4714 }; 4715 4716 struct mlx5_ifc_query_scheduling_element_in_bits { 4717 u8 opcode[0x10]; 4718 u8 reserved_at_10[0x10]; 4719 4720 u8 reserved_at_20[0x10]; 4721 u8 op_mod[0x10]; 4722 4723 u8 scheduling_hierarchy[0x8]; 4724 u8 reserved_at_48[0x18]; 4725 4726 u8 scheduling_element_id[0x20]; 4727 4728 u8 reserved_at_80[0x180]; 4729 }; 4730 4731 struct mlx5_ifc_query_rqt_out_bits { 4732 u8 status[0x8]; 4733 u8 reserved_at_8[0x18]; 4734 4735 u8 syndrome[0x20]; 4736 4737 u8 reserved_at_40[0xc0]; 4738 4739 struct mlx5_ifc_rqtc_bits rqt_context; 4740 }; 4741 4742 struct mlx5_ifc_query_rqt_in_bits { 4743 u8 opcode[0x10]; 4744 u8 reserved_at_10[0x10]; 4745 4746 u8 reserved_at_20[0x10]; 4747 u8 op_mod[0x10]; 4748 4749 u8 reserved_at_40[0x8]; 4750 u8 rqtn[0x18]; 4751 4752 u8 reserved_at_60[0x20]; 4753 }; 4754 4755 struct mlx5_ifc_query_rq_out_bits { 4756 u8 status[0x8]; 4757 u8 reserved_at_8[0x18]; 4758 4759 u8 syndrome[0x20]; 4760 4761 u8 reserved_at_40[0xc0]; 4762 4763 struct mlx5_ifc_rqc_bits rq_context; 4764 }; 4765 4766 struct mlx5_ifc_query_rq_in_bits { 4767 u8 opcode[0x10]; 4768 u8 reserved_at_10[0x10]; 4769 4770 u8 reserved_at_20[0x10]; 4771 u8 op_mod[0x10]; 4772 4773 u8 reserved_at_40[0x8]; 4774 u8 rqn[0x18]; 4775 4776 u8 reserved_at_60[0x20]; 4777 }; 4778 4779 struct mlx5_ifc_query_roce_address_out_bits { 4780 u8 status[0x8]; 4781 u8 reserved_at_8[0x18]; 4782 4783 u8 syndrome[0x20]; 4784 4785 u8 reserved_at_40[0x40]; 4786 4787 struct mlx5_ifc_roce_addr_layout_bits roce_address; 4788 }; 4789 4790 struct mlx5_ifc_query_roce_address_in_bits { 4791 u8 opcode[0x10]; 4792 u8 reserved_at_10[0x10]; 4793 4794 u8 reserved_at_20[0x10]; 4795 u8 op_mod[0x10]; 4796 4797 u8 roce_address_index[0x10]; 4798 u8 reserved_at_50[0xc]; 4799 u8 vhca_port_num[0x4]; 4800 4801 u8 reserved_at_60[0x20]; 4802 }; 4803 4804 struct mlx5_ifc_query_rmp_out_bits { 4805 u8 status[0x8]; 4806 u8 reserved_at_8[0x18]; 4807 4808 u8 syndrome[0x20]; 4809 4810 u8 reserved_at_40[0xc0]; 4811 4812 struct mlx5_ifc_rmpc_bits rmp_context; 4813 }; 4814 4815 struct mlx5_ifc_query_rmp_in_bits { 4816 u8 opcode[0x10]; 4817 u8 reserved_at_10[0x10]; 4818 4819 u8 reserved_at_20[0x10]; 4820 u8 op_mod[0x10]; 4821 4822 u8 reserved_at_40[0x8]; 4823 u8 rmpn[0x18]; 4824 4825 u8 reserved_at_60[0x20]; 4826 }; 4827 4828 struct mlx5_ifc_query_qp_out_bits { 4829 u8 status[0x8]; 4830 u8 reserved_at_8[0x18]; 4831 4832 u8 syndrome[0x20]; 4833 4834 u8 reserved_at_40[0x20]; 4835 u8 ece[0x20]; 4836 4837 u8 opt_param_mask[0x20]; 4838 4839 u8 reserved_at_a0[0x20]; 4840 4841 struct mlx5_ifc_qpc_bits qpc; 4842 4843 u8 reserved_at_800[0x80]; 4844 4845 u8 pas[][0x40]; 4846 }; 4847 4848 struct mlx5_ifc_query_qp_in_bits { 4849 u8 opcode[0x10]; 4850 u8 reserved_at_10[0x10]; 4851 4852 u8 reserved_at_20[0x10]; 4853 u8 op_mod[0x10]; 4854 4855 u8 reserved_at_40[0x8]; 4856 u8 qpn[0x18]; 4857 4858 u8 reserved_at_60[0x20]; 4859 }; 4860 4861 struct mlx5_ifc_query_q_counter_out_bits { 4862 u8 status[0x8]; 4863 u8 reserved_at_8[0x18]; 4864 4865 u8 syndrome[0x20]; 4866 4867 u8 reserved_at_40[0x40]; 4868 4869 u8 rx_write_requests[0x20]; 4870 4871 u8 reserved_at_a0[0x20]; 4872 4873 u8 rx_read_requests[0x20]; 4874 4875 u8 reserved_at_e0[0x20]; 4876 4877 u8 rx_atomic_requests[0x20]; 4878 4879 u8 reserved_at_120[0x20]; 4880 4881 u8 rx_dct_connect[0x20]; 4882 4883 u8 reserved_at_160[0x20]; 4884 4885 u8 out_of_buffer[0x20]; 4886 4887 u8 reserved_at_1a0[0x20]; 4888 4889 u8 out_of_sequence[0x20]; 4890 4891 u8 reserved_at_1e0[0x20]; 4892 4893 u8 duplicate_request[0x20]; 4894 4895 u8 reserved_at_220[0x20]; 4896 4897 u8 rnr_nak_retry_err[0x20]; 4898 4899 u8 reserved_at_260[0x20]; 4900 4901 u8 packet_seq_err[0x20]; 4902 4903 u8 reserved_at_2a0[0x20]; 4904 4905 u8 implied_nak_seq_err[0x20]; 4906 4907 u8 reserved_at_2e0[0x20]; 4908 4909 u8 local_ack_timeout_err[0x20]; 4910 4911 u8 reserved_at_320[0xa0]; 4912 4913 u8 resp_local_length_error[0x20]; 4914 4915 u8 req_local_length_error[0x20]; 4916 4917 u8 resp_local_qp_error[0x20]; 4918 4919 u8 local_operation_error[0x20]; 4920 4921 u8 resp_local_protection[0x20]; 4922 4923 u8 req_local_protection[0x20]; 4924 4925 u8 resp_cqe_error[0x20]; 4926 4927 u8 req_cqe_error[0x20]; 4928 4929 u8 req_mw_binding[0x20]; 4930 4931 u8 req_bad_response[0x20]; 4932 4933 u8 req_remote_invalid_request[0x20]; 4934 4935 u8 resp_remote_invalid_request[0x20]; 4936 4937 u8 req_remote_access_errors[0x20]; 4938 4939 u8 resp_remote_access_errors[0x20]; 4940 4941 u8 req_remote_operation_errors[0x20]; 4942 4943 u8 req_transport_retries_exceeded[0x20]; 4944 4945 u8 cq_overflow[0x20]; 4946 4947 u8 resp_cqe_flush_error[0x20]; 4948 4949 u8 req_cqe_flush_error[0x20]; 4950 4951 u8 reserved_at_620[0x20]; 4952 4953 u8 roce_adp_retrans[0x20]; 4954 4955 u8 roce_adp_retrans_to[0x20]; 4956 4957 u8 roce_slow_restart[0x20]; 4958 4959 u8 roce_slow_restart_cnps[0x20]; 4960 4961 u8 roce_slow_restart_trans[0x20]; 4962 4963 u8 reserved_at_6e0[0x120]; 4964 }; 4965 4966 struct mlx5_ifc_query_q_counter_in_bits { 4967 u8 opcode[0x10]; 4968 u8 reserved_at_10[0x10]; 4969 4970 u8 reserved_at_20[0x10]; 4971 u8 op_mod[0x10]; 4972 4973 u8 reserved_at_40[0x80]; 4974 4975 u8 clear[0x1]; 4976 u8 reserved_at_c1[0x1f]; 4977 4978 u8 reserved_at_e0[0x18]; 4979 u8 counter_set_id[0x8]; 4980 }; 4981 4982 struct mlx5_ifc_query_pages_out_bits { 4983 u8 status[0x8]; 4984 u8 reserved_at_8[0x18]; 4985 4986 u8 syndrome[0x20]; 4987 4988 u8 embedded_cpu_function[0x1]; 4989 u8 reserved_at_41[0xf]; 4990 u8 function_id[0x10]; 4991 4992 u8 num_pages[0x20]; 4993 }; 4994 4995 enum { 4996 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1, 4997 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2, 4998 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3, 4999 }; 5000 5001 struct mlx5_ifc_query_pages_in_bits { 5002 u8 opcode[0x10]; 5003 u8 reserved_at_10[0x10]; 5004 5005 u8 reserved_at_20[0x10]; 5006 u8 op_mod[0x10]; 5007 5008 u8 embedded_cpu_function[0x1]; 5009 u8 reserved_at_41[0xf]; 5010 u8 function_id[0x10]; 5011 5012 u8 reserved_at_60[0x20]; 5013 }; 5014 5015 struct mlx5_ifc_query_nic_vport_context_out_bits { 5016 u8 status[0x8]; 5017 u8 reserved_at_8[0x18]; 5018 5019 u8 syndrome[0x20]; 5020 5021 u8 reserved_at_40[0x40]; 5022 5023 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 5024 }; 5025 5026 struct mlx5_ifc_query_nic_vport_context_in_bits { 5027 u8 opcode[0x10]; 5028 u8 reserved_at_10[0x10]; 5029 5030 u8 reserved_at_20[0x10]; 5031 u8 op_mod[0x10]; 5032 5033 u8 other_vport[0x1]; 5034 u8 reserved_at_41[0xf]; 5035 u8 vport_number[0x10]; 5036 5037 u8 reserved_at_60[0x5]; 5038 u8 allowed_list_type[0x3]; 5039 u8 reserved_at_68[0x18]; 5040 }; 5041 5042 struct mlx5_ifc_query_mkey_out_bits { 5043 u8 status[0x8]; 5044 u8 reserved_at_8[0x18]; 5045 5046 u8 syndrome[0x20]; 5047 5048 u8 reserved_at_40[0x40]; 5049 5050 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 5051 5052 u8 reserved_at_280[0x600]; 5053 5054 u8 bsf0_klm0_pas_mtt0_1[16][0x8]; 5055 5056 u8 bsf1_klm1_pas_mtt2_3[16][0x8]; 5057 }; 5058 5059 struct mlx5_ifc_query_mkey_in_bits { 5060 u8 opcode[0x10]; 5061 u8 reserved_at_10[0x10]; 5062 5063 u8 reserved_at_20[0x10]; 5064 u8 op_mod[0x10]; 5065 5066 u8 reserved_at_40[0x8]; 5067 u8 mkey_index[0x18]; 5068 5069 u8 pg_access[0x1]; 5070 u8 reserved_at_61[0x1f]; 5071 }; 5072 5073 struct mlx5_ifc_query_mad_demux_out_bits { 5074 u8 status[0x8]; 5075 u8 reserved_at_8[0x18]; 5076 5077 u8 syndrome[0x20]; 5078 5079 u8 reserved_at_40[0x40]; 5080 5081 u8 mad_dumux_parameters_block[0x20]; 5082 }; 5083 5084 struct mlx5_ifc_query_mad_demux_in_bits { 5085 u8 opcode[0x10]; 5086 u8 reserved_at_10[0x10]; 5087 5088 u8 reserved_at_20[0x10]; 5089 u8 op_mod[0x10]; 5090 5091 u8 reserved_at_40[0x40]; 5092 }; 5093 5094 struct mlx5_ifc_query_l2_table_entry_out_bits { 5095 u8 status[0x8]; 5096 u8 reserved_at_8[0x18]; 5097 5098 u8 syndrome[0x20]; 5099 5100 u8 reserved_at_40[0xa0]; 5101 5102 u8 reserved_at_e0[0x13]; 5103 u8 vlan_valid[0x1]; 5104 u8 vlan[0xc]; 5105 5106 struct mlx5_ifc_mac_address_layout_bits mac_address; 5107 5108 u8 reserved_at_140[0xc0]; 5109 }; 5110 5111 struct mlx5_ifc_query_l2_table_entry_in_bits { 5112 u8 opcode[0x10]; 5113 u8 reserved_at_10[0x10]; 5114 5115 u8 reserved_at_20[0x10]; 5116 u8 op_mod[0x10]; 5117 5118 u8 reserved_at_40[0x60]; 5119 5120 u8 reserved_at_a0[0x8]; 5121 u8 table_index[0x18]; 5122 5123 u8 reserved_at_c0[0x140]; 5124 }; 5125 5126 struct mlx5_ifc_query_issi_out_bits { 5127 u8 status[0x8]; 5128 u8 reserved_at_8[0x18]; 5129 5130 u8 syndrome[0x20]; 5131 5132 u8 reserved_at_40[0x10]; 5133 u8 current_issi[0x10]; 5134 5135 u8 reserved_at_60[0xa0]; 5136 5137 u8 reserved_at_100[76][0x8]; 5138 u8 supported_issi_dw0[0x20]; 5139 }; 5140 5141 struct mlx5_ifc_query_issi_in_bits { 5142 u8 opcode[0x10]; 5143 u8 reserved_at_10[0x10]; 5144 5145 u8 reserved_at_20[0x10]; 5146 u8 op_mod[0x10]; 5147 5148 u8 reserved_at_40[0x40]; 5149 }; 5150 5151 struct mlx5_ifc_set_driver_version_out_bits { 5152 u8 status[0x8]; 5153 u8 reserved_0[0x18]; 5154 5155 u8 syndrome[0x20]; 5156 u8 reserved_1[0x40]; 5157 }; 5158 5159 struct mlx5_ifc_set_driver_version_in_bits { 5160 u8 opcode[0x10]; 5161 u8 reserved_0[0x10]; 5162 5163 u8 reserved_1[0x10]; 5164 u8 op_mod[0x10]; 5165 5166 u8 reserved_2[0x40]; 5167 u8 driver_version[64][0x8]; 5168 }; 5169 5170 struct mlx5_ifc_query_hca_vport_pkey_out_bits { 5171 u8 status[0x8]; 5172 u8 reserved_at_8[0x18]; 5173 5174 u8 syndrome[0x20]; 5175 5176 u8 reserved_at_40[0x40]; 5177 5178 struct mlx5_ifc_pkey_bits pkey[]; 5179 }; 5180 5181 struct mlx5_ifc_query_hca_vport_pkey_in_bits { 5182 u8 opcode[0x10]; 5183 u8 reserved_at_10[0x10]; 5184 5185 u8 reserved_at_20[0x10]; 5186 u8 op_mod[0x10]; 5187 5188 u8 other_vport[0x1]; 5189 u8 reserved_at_41[0xb]; 5190 u8 port_num[0x4]; 5191 u8 vport_number[0x10]; 5192 5193 u8 reserved_at_60[0x10]; 5194 u8 pkey_index[0x10]; 5195 }; 5196 5197 enum { 5198 MLX5_HCA_VPORT_SEL_PORT_GUID = 1 << 0, 5199 MLX5_HCA_VPORT_SEL_NODE_GUID = 1 << 1, 5200 MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2, 5201 }; 5202 5203 struct mlx5_ifc_query_hca_vport_gid_out_bits { 5204 u8 status[0x8]; 5205 u8 reserved_at_8[0x18]; 5206 5207 u8 syndrome[0x20]; 5208 5209 u8 reserved_at_40[0x20]; 5210 5211 u8 gids_num[0x10]; 5212 u8 reserved_at_70[0x10]; 5213 5214 struct mlx5_ifc_array128_auto_bits gid[]; 5215 }; 5216 5217 struct mlx5_ifc_query_hca_vport_gid_in_bits { 5218 u8 opcode[0x10]; 5219 u8 reserved_at_10[0x10]; 5220 5221 u8 reserved_at_20[0x10]; 5222 u8 op_mod[0x10]; 5223 5224 u8 other_vport[0x1]; 5225 u8 reserved_at_41[0xb]; 5226 u8 port_num[0x4]; 5227 u8 vport_number[0x10]; 5228 5229 u8 reserved_at_60[0x10]; 5230 u8 gid_index[0x10]; 5231 }; 5232 5233 struct mlx5_ifc_query_hca_vport_context_out_bits { 5234 u8 status[0x8]; 5235 u8 reserved_at_8[0x18]; 5236 5237 u8 syndrome[0x20]; 5238 5239 u8 reserved_at_40[0x40]; 5240 5241 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 5242 }; 5243 5244 struct mlx5_ifc_query_hca_vport_context_in_bits { 5245 u8 opcode[0x10]; 5246 u8 reserved_at_10[0x10]; 5247 5248 u8 reserved_at_20[0x10]; 5249 u8 op_mod[0x10]; 5250 5251 u8 other_vport[0x1]; 5252 u8 reserved_at_41[0xb]; 5253 u8 port_num[0x4]; 5254 u8 vport_number[0x10]; 5255 5256 u8 reserved_at_60[0x20]; 5257 }; 5258 5259 struct mlx5_ifc_query_hca_cap_out_bits { 5260 u8 status[0x8]; 5261 u8 reserved_at_8[0x18]; 5262 5263 u8 syndrome[0x20]; 5264 5265 u8 reserved_at_40[0x40]; 5266 5267 union mlx5_ifc_hca_cap_union_bits capability; 5268 }; 5269 5270 struct mlx5_ifc_query_hca_cap_in_bits { 5271 u8 opcode[0x10]; 5272 u8 reserved_at_10[0x10]; 5273 5274 u8 reserved_at_20[0x10]; 5275 u8 op_mod[0x10]; 5276 5277 u8 other_function[0x1]; 5278 u8 reserved_at_41[0xf]; 5279 u8 function_id[0x10]; 5280 5281 u8 reserved_at_60[0x20]; 5282 }; 5283 5284 struct mlx5_ifc_other_hca_cap_bits { 5285 u8 roce[0x1]; 5286 u8 reserved_at_1[0x27f]; 5287 }; 5288 5289 struct mlx5_ifc_query_other_hca_cap_out_bits { 5290 u8 status[0x8]; 5291 u8 reserved_at_8[0x18]; 5292 5293 u8 syndrome[0x20]; 5294 5295 u8 reserved_at_40[0x40]; 5296 5297 struct mlx5_ifc_other_hca_cap_bits other_capability; 5298 }; 5299 5300 struct mlx5_ifc_query_other_hca_cap_in_bits { 5301 u8 opcode[0x10]; 5302 u8 reserved_at_10[0x10]; 5303 5304 u8 reserved_at_20[0x10]; 5305 u8 op_mod[0x10]; 5306 5307 u8 reserved_at_40[0x10]; 5308 u8 function_id[0x10]; 5309 5310 u8 reserved_at_60[0x20]; 5311 }; 5312 5313 struct mlx5_ifc_modify_other_hca_cap_out_bits { 5314 u8 status[0x8]; 5315 u8 reserved_at_8[0x18]; 5316 5317 u8 syndrome[0x20]; 5318 5319 u8 reserved_at_40[0x40]; 5320 }; 5321 5322 struct mlx5_ifc_modify_other_hca_cap_in_bits { 5323 u8 opcode[0x10]; 5324 u8 reserved_at_10[0x10]; 5325 5326 u8 reserved_at_20[0x10]; 5327 u8 op_mod[0x10]; 5328 5329 u8 reserved_at_40[0x10]; 5330 u8 function_id[0x10]; 5331 u8 field_select[0x20]; 5332 5333 struct mlx5_ifc_other_hca_cap_bits other_capability; 5334 }; 5335 5336 struct mlx5_ifc_flow_table_context_bits { 5337 u8 reformat_en[0x1]; 5338 u8 decap_en[0x1]; 5339 u8 sw_owner[0x1]; 5340 u8 termination_table[0x1]; 5341 u8 table_miss_action[0x4]; 5342 u8 level[0x8]; 5343 u8 reserved_at_10[0x8]; 5344 u8 log_size[0x8]; 5345 5346 u8 reserved_at_20[0x8]; 5347 u8 table_miss_id[0x18]; 5348 5349 u8 reserved_at_40[0x8]; 5350 u8 lag_master_next_table_id[0x18]; 5351 5352 u8 reserved_at_60[0x60]; 5353 5354 u8 sw_owner_icm_root_1[0x40]; 5355 5356 u8 sw_owner_icm_root_0[0x40]; 5357 5358 }; 5359 5360 struct mlx5_ifc_query_flow_table_out_bits { 5361 u8 status[0x8]; 5362 u8 reserved_at_8[0x18]; 5363 5364 u8 syndrome[0x20]; 5365 5366 u8 reserved_at_40[0x80]; 5367 5368 struct mlx5_ifc_flow_table_context_bits flow_table_context; 5369 }; 5370 5371 struct mlx5_ifc_query_flow_table_in_bits { 5372 u8 opcode[0x10]; 5373 u8 reserved_at_10[0x10]; 5374 5375 u8 reserved_at_20[0x10]; 5376 u8 op_mod[0x10]; 5377 5378 u8 reserved_at_40[0x40]; 5379 5380 u8 table_type[0x8]; 5381 u8 reserved_at_88[0x18]; 5382 5383 u8 reserved_at_a0[0x8]; 5384 u8 table_id[0x18]; 5385 5386 u8 reserved_at_c0[0x140]; 5387 }; 5388 5389 struct mlx5_ifc_query_fte_out_bits { 5390 u8 status[0x8]; 5391 u8 reserved_at_8[0x18]; 5392 5393 u8 syndrome[0x20]; 5394 5395 u8 reserved_at_40[0x1c0]; 5396 5397 struct mlx5_ifc_flow_context_bits flow_context; 5398 }; 5399 5400 struct mlx5_ifc_query_fte_in_bits { 5401 u8 opcode[0x10]; 5402 u8 reserved_at_10[0x10]; 5403 5404 u8 reserved_at_20[0x10]; 5405 u8 op_mod[0x10]; 5406 5407 u8 reserved_at_40[0x40]; 5408 5409 u8 table_type[0x8]; 5410 u8 reserved_at_88[0x18]; 5411 5412 u8 reserved_at_a0[0x8]; 5413 u8 table_id[0x18]; 5414 5415 u8 reserved_at_c0[0x40]; 5416 5417 u8 flow_index[0x20]; 5418 5419 u8 reserved_at_120[0xe0]; 5420 }; 5421 5422 enum { 5423 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 5424 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 5425 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 5426 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3, 5427 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_3 = 0x4, 5428 }; 5429 5430 struct mlx5_ifc_query_flow_group_out_bits { 5431 u8 status[0x8]; 5432 u8 reserved_at_8[0x18]; 5433 5434 u8 syndrome[0x20]; 5435 5436 u8 reserved_at_40[0xa0]; 5437 5438 u8 start_flow_index[0x20]; 5439 5440 u8 reserved_at_100[0x20]; 5441 5442 u8 end_flow_index[0x20]; 5443 5444 u8 reserved_at_140[0xa0]; 5445 5446 u8 reserved_at_1e0[0x18]; 5447 u8 match_criteria_enable[0x8]; 5448 5449 struct mlx5_ifc_fte_match_param_bits match_criteria; 5450 5451 u8 reserved_at_1200[0xe00]; 5452 }; 5453 5454 struct mlx5_ifc_query_flow_group_in_bits { 5455 u8 opcode[0x10]; 5456 u8 reserved_at_10[0x10]; 5457 5458 u8 reserved_at_20[0x10]; 5459 u8 op_mod[0x10]; 5460 5461 u8 reserved_at_40[0x40]; 5462 5463 u8 table_type[0x8]; 5464 u8 reserved_at_88[0x18]; 5465 5466 u8 reserved_at_a0[0x8]; 5467 u8 table_id[0x18]; 5468 5469 u8 group_id[0x20]; 5470 5471 u8 reserved_at_e0[0x120]; 5472 }; 5473 5474 struct mlx5_ifc_query_flow_counter_out_bits { 5475 u8 status[0x8]; 5476 u8 reserved_at_8[0x18]; 5477 5478 u8 syndrome[0x20]; 5479 5480 u8 reserved_at_40[0x40]; 5481 5482 struct mlx5_ifc_traffic_counter_bits flow_statistics[]; 5483 }; 5484 5485 struct mlx5_ifc_query_flow_counter_in_bits { 5486 u8 opcode[0x10]; 5487 u8 reserved_at_10[0x10]; 5488 5489 u8 reserved_at_20[0x10]; 5490 u8 op_mod[0x10]; 5491 5492 u8 reserved_at_40[0x80]; 5493 5494 u8 clear[0x1]; 5495 u8 reserved_at_c1[0xf]; 5496 u8 num_of_counters[0x10]; 5497 5498 u8 flow_counter_id[0x20]; 5499 }; 5500 5501 struct mlx5_ifc_query_esw_vport_context_out_bits { 5502 u8 status[0x8]; 5503 u8 reserved_at_8[0x18]; 5504 5505 u8 syndrome[0x20]; 5506 5507 u8 reserved_at_40[0x40]; 5508 5509 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 5510 }; 5511 5512 struct mlx5_ifc_query_esw_vport_context_in_bits { 5513 u8 opcode[0x10]; 5514 u8 reserved_at_10[0x10]; 5515 5516 u8 reserved_at_20[0x10]; 5517 u8 op_mod[0x10]; 5518 5519 u8 other_vport[0x1]; 5520 u8 reserved_at_41[0xf]; 5521 u8 vport_number[0x10]; 5522 5523 u8 reserved_at_60[0x20]; 5524 }; 5525 5526 struct mlx5_ifc_modify_esw_vport_context_out_bits { 5527 u8 status[0x8]; 5528 u8 reserved_at_8[0x18]; 5529 5530 u8 syndrome[0x20]; 5531 5532 u8 reserved_at_40[0x40]; 5533 }; 5534 5535 struct mlx5_ifc_esw_vport_context_fields_select_bits { 5536 u8 reserved_at_0[0x1b]; 5537 u8 fdb_to_vport_reg_c_id[0x1]; 5538 u8 vport_cvlan_insert[0x1]; 5539 u8 vport_svlan_insert[0x1]; 5540 u8 vport_cvlan_strip[0x1]; 5541 u8 vport_svlan_strip[0x1]; 5542 }; 5543 5544 struct mlx5_ifc_modify_esw_vport_context_in_bits { 5545 u8 opcode[0x10]; 5546 u8 reserved_at_10[0x10]; 5547 5548 u8 reserved_at_20[0x10]; 5549 u8 op_mod[0x10]; 5550 5551 u8 other_vport[0x1]; 5552 u8 reserved_at_41[0xf]; 5553 u8 vport_number[0x10]; 5554 5555 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select; 5556 5557 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 5558 }; 5559 5560 struct mlx5_ifc_query_eq_out_bits { 5561 u8 status[0x8]; 5562 u8 reserved_at_8[0x18]; 5563 5564 u8 syndrome[0x20]; 5565 5566 u8 reserved_at_40[0x40]; 5567 5568 struct mlx5_ifc_eqc_bits eq_context_entry; 5569 5570 u8 reserved_at_280[0x40]; 5571 5572 u8 event_bitmask[0x40]; 5573 5574 u8 reserved_at_300[0x580]; 5575 5576 u8 pas[][0x40]; 5577 }; 5578 5579 struct mlx5_ifc_query_eq_in_bits { 5580 u8 opcode[0x10]; 5581 u8 reserved_at_10[0x10]; 5582 5583 u8 reserved_at_20[0x10]; 5584 u8 op_mod[0x10]; 5585 5586 u8 reserved_at_40[0x18]; 5587 u8 eq_number[0x8]; 5588 5589 u8 reserved_at_60[0x20]; 5590 }; 5591 5592 struct mlx5_ifc_packet_reformat_context_in_bits { 5593 u8 reserved_at_0[0x5]; 5594 u8 reformat_type[0x3]; 5595 u8 reserved_at_8[0xe]; 5596 u8 reformat_data_size[0xa]; 5597 5598 u8 reserved_at_20[0x10]; 5599 u8 reformat_data[2][0x8]; 5600 5601 u8 more_reformat_data[][0x8]; 5602 }; 5603 5604 struct mlx5_ifc_query_packet_reformat_context_out_bits { 5605 u8 status[0x8]; 5606 u8 reserved_at_8[0x18]; 5607 5608 u8 syndrome[0x20]; 5609 5610 u8 reserved_at_40[0xa0]; 5611 5612 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context[]; 5613 }; 5614 5615 struct mlx5_ifc_query_packet_reformat_context_in_bits { 5616 u8 opcode[0x10]; 5617 u8 reserved_at_10[0x10]; 5618 5619 u8 reserved_at_20[0x10]; 5620 u8 op_mod[0x10]; 5621 5622 u8 packet_reformat_id[0x20]; 5623 5624 u8 reserved_at_60[0xa0]; 5625 }; 5626 5627 struct mlx5_ifc_alloc_packet_reformat_context_out_bits { 5628 u8 status[0x8]; 5629 u8 reserved_at_8[0x18]; 5630 5631 u8 syndrome[0x20]; 5632 5633 u8 packet_reformat_id[0x20]; 5634 5635 u8 reserved_at_60[0x20]; 5636 }; 5637 5638 enum mlx5_reformat_ctx_type { 5639 MLX5_REFORMAT_TYPE_L2_TO_VXLAN = 0x0, 5640 MLX5_REFORMAT_TYPE_L2_TO_NVGRE = 0x1, 5641 MLX5_REFORMAT_TYPE_L2_TO_L2_TUNNEL = 0x2, 5642 MLX5_REFORMAT_TYPE_L3_TUNNEL_TO_L2 = 0x3, 5643 MLX5_REFORMAT_TYPE_L2_TO_L3_TUNNEL = 0x4, 5644 }; 5645 5646 struct mlx5_ifc_alloc_packet_reformat_context_in_bits { 5647 u8 opcode[0x10]; 5648 u8 reserved_at_10[0x10]; 5649 5650 u8 reserved_at_20[0x10]; 5651 u8 op_mod[0x10]; 5652 5653 u8 reserved_at_40[0xa0]; 5654 5655 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context; 5656 }; 5657 5658 struct mlx5_ifc_dealloc_packet_reformat_context_out_bits { 5659 u8 status[0x8]; 5660 u8 reserved_at_8[0x18]; 5661 5662 u8 syndrome[0x20]; 5663 5664 u8 reserved_at_40[0x40]; 5665 }; 5666 5667 struct mlx5_ifc_dealloc_packet_reformat_context_in_bits { 5668 u8 opcode[0x10]; 5669 u8 reserved_at_10[0x10]; 5670 5671 u8 reserved_20[0x10]; 5672 u8 op_mod[0x10]; 5673 5674 u8 packet_reformat_id[0x20]; 5675 5676 u8 reserved_60[0x20]; 5677 }; 5678 5679 struct mlx5_ifc_set_action_in_bits { 5680 u8 action_type[0x4]; 5681 u8 field[0xc]; 5682 u8 reserved_at_10[0x3]; 5683 u8 offset[0x5]; 5684 u8 reserved_at_18[0x3]; 5685 u8 length[0x5]; 5686 5687 u8 data[0x20]; 5688 }; 5689 5690 struct mlx5_ifc_add_action_in_bits { 5691 u8 action_type[0x4]; 5692 u8 field[0xc]; 5693 u8 reserved_at_10[0x10]; 5694 5695 u8 data[0x20]; 5696 }; 5697 5698 struct mlx5_ifc_copy_action_in_bits { 5699 u8 action_type[0x4]; 5700 u8 src_field[0xc]; 5701 u8 reserved_at_10[0x3]; 5702 u8 src_offset[0x5]; 5703 u8 reserved_at_18[0x3]; 5704 u8 length[0x5]; 5705 5706 u8 reserved_at_20[0x4]; 5707 u8 dst_field[0xc]; 5708 u8 reserved_at_30[0x3]; 5709 u8 dst_offset[0x5]; 5710 u8 reserved_at_38[0x8]; 5711 }; 5712 5713 union mlx5_ifc_set_add_copy_action_in_auto_bits { 5714 struct mlx5_ifc_set_action_in_bits set_action_in; 5715 struct mlx5_ifc_add_action_in_bits add_action_in; 5716 struct mlx5_ifc_copy_action_in_bits copy_action_in; 5717 u8 reserved_at_0[0x40]; 5718 }; 5719 5720 enum { 5721 MLX5_ACTION_TYPE_SET = 0x1, 5722 MLX5_ACTION_TYPE_ADD = 0x2, 5723 MLX5_ACTION_TYPE_COPY = 0x3, 5724 }; 5725 5726 enum { 5727 MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16 = 0x1, 5728 MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0 = 0x2, 5729 MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE = 0x3, 5730 MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16 = 0x4, 5731 MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0 = 0x5, 5732 MLX5_ACTION_IN_FIELD_OUT_IP_DSCP = 0x6, 5733 MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS = 0x7, 5734 MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT = 0x8, 5735 MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT = 0x9, 5736 MLX5_ACTION_IN_FIELD_OUT_IP_TTL = 0xa, 5737 MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT = 0xb, 5738 MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT = 0xc, 5739 MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96 = 0xd, 5740 MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64 = 0xe, 5741 MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32 = 0xf, 5742 MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0 = 0x10, 5743 MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96 = 0x11, 5744 MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64 = 0x12, 5745 MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32 = 0x13, 5746 MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0 = 0x14, 5747 MLX5_ACTION_IN_FIELD_OUT_SIPV4 = 0x15, 5748 MLX5_ACTION_IN_FIELD_OUT_DIPV4 = 0x16, 5749 MLX5_ACTION_IN_FIELD_OUT_FIRST_VID = 0x17, 5750 MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47, 5751 MLX5_ACTION_IN_FIELD_METADATA_REG_A = 0x49, 5752 MLX5_ACTION_IN_FIELD_METADATA_REG_B = 0x50, 5753 MLX5_ACTION_IN_FIELD_METADATA_REG_C_0 = 0x51, 5754 MLX5_ACTION_IN_FIELD_METADATA_REG_C_1 = 0x52, 5755 MLX5_ACTION_IN_FIELD_METADATA_REG_C_2 = 0x53, 5756 MLX5_ACTION_IN_FIELD_METADATA_REG_C_3 = 0x54, 5757 MLX5_ACTION_IN_FIELD_METADATA_REG_C_4 = 0x55, 5758 MLX5_ACTION_IN_FIELD_METADATA_REG_C_5 = 0x56, 5759 MLX5_ACTION_IN_FIELD_METADATA_REG_C_6 = 0x57, 5760 MLX5_ACTION_IN_FIELD_METADATA_REG_C_7 = 0x58, 5761 MLX5_ACTION_IN_FIELD_OUT_TCP_SEQ_NUM = 0x59, 5762 MLX5_ACTION_IN_FIELD_OUT_TCP_ACK_NUM = 0x5B, 5763 MLX5_ACTION_IN_FIELD_IPSEC_SYNDROME = 0x5D, 5764 }; 5765 5766 struct mlx5_ifc_alloc_modify_header_context_out_bits { 5767 u8 status[0x8]; 5768 u8 reserved_at_8[0x18]; 5769 5770 u8 syndrome[0x20]; 5771 5772 u8 modify_header_id[0x20]; 5773 5774 u8 reserved_at_60[0x20]; 5775 }; 5776 5777 struct mlx5_ifc_alloc_modify_header_context_in_bits { 5778 u8 opcode[0x10]; 5779 u8 reserved_at_10[0x10]; 5780 5781 u8 reserved_at_20[0x10]; 5782 u8 op_mod[0x10]; 5783 5784 u8 reserved_at_40[0x20]; 5785 5786 u8 table_type[0x8]; 5787 u8 reserved_at_68[0x10]; 5788 u8 num_of_actions[0x8]; 5789 5790 union mlx5_ifc_set_add_copy_action_in_auto_bits actions[0]; 5791 }; 5792 5793 struct mlx5_ifc_dealloc_modify_header_context_out_bits { 5794 u8 status[0x8]; 5795 u8 reserved_at_8[0x18]; 5796 5797 u8 syndrome[0x20]; 5798 5799 u8 reserved_at_40[0x40]; 5800 }; 5801 5802 struct mlx5_ifc_dealloc_modify_header_context_in_bits { 5803 u8 opcode[0x10]; 5804 u8 reserved_at_10[0x10]; 5805 5806 u8 reserved_at_20[0x10]; 5807 u8 op_mod[0x10]; 5808 5809 u8 modify_header_id[0x20]; 5810 5811 u8 reserved_at_60[0x20]; 5812 }; 5813 5814 struct mlx5_ifc_query_dct_out_bits { 5815 u8 status[0x8]; 5816 u8 reserved_at_8[0x18]; 5817 5818 u8 syndrome[0x20]; 5819 5820 u8 reserved_at_40[0x40]; 5821 5822 struct mlx5_ifc_dctc_bits dct_context_entry; 5823 5824 u8 reserved_at_280[0x180]; 5825 }; 5826 5827 struct mlx5_ifc_query_dct_in_bits { 5828 u8 opcode[0x10]; 5829 u8 reserved_at_10[0x10]; 5830 5831 u8 reserved_at_20[0x10]; 5832 u8 op_mod[0x10]; 5833 5834 u8 reserved_at_40[0x8]; 5835 u8 dctn[0x18]; 5836 5837 u8 reserved_at_60[0x20]; 5838 }; 5839 5840 struct mlx5_ifc_query_cq_out_bits { 5841 u8 status[0x8]; 5842 u8 reserved_at_8[0x18]; 5843 5844 u8 syndrome[0x20]; 5845 5846 u8 reserved_at_40[0x40]; 5847 5848 struct mlx5_ifc_cqc_bits cq_context; 5849 5850 u8 reserved_at_280[0x600]; 5851 5852 u8 pas[][0x40]; 5853 }; 5854 5855 struct mlx5_ifc_query_cq_in_bits { 5856 u8 opcode[0x10]; 5857 u8 reserved_at_10[0x10]; 5858 5859 u8 reserved_at_20[0x10]; 5860 u8 op_mod[0x10]; 5861 5862 u8 reserved_at_40[0x8]; 5863 u8 cqn[0x18]; 5864 5865 u8 reserved_at_60[0x20]; 5866 }; 5867 5868 struct mlx5_ifc_query_cong_status_out_bits { 5869 u8 status[0x8]; 5870 u8 reserved_at_8[0x18]; 5871 5872 u8 syndrome[0x20]; 5873 5874 u8 reserved_at_40[0x20]; 5875 5876 u8 enable[0x1]; 5877 u8 tag_enable[0x1]; 5878 u8 reserved_at_62[0x1e]; 5879 }; 5880 5881 struct mlx5_ifc_query_cong_status_in_bits { 5882 u8 opcode[0x10]; 5883 u8 reserved_at_10[0x10]; 5884 5885 u8 reserved_at_20[0x10]; 5886 u8 op_mod[0x10]; 5887 5888 u8 reserved_at_40[0x18]; 5889 u8 priority[0x4]; 5890 u8 cong_protocol[0x4]; 5891 5892 u8 reserved_at_60[0x20]; 5893 }; 5894 5895 struct mlx5_ifc_query_cong_statistics_out_bits { 5896 u8 status[0x8]; 5897 u8 reserved_at_8[0x18]; 5898 5899 u8 syndrome[0x20]; 5900 5901 u8 reserved_at_40[0x40]; 5902 5903 u8 rp_cur_flows[0x20]; 5904 5905 u8 sum_flows[0x20]; 5906 5907 u8 rp_cnp_ignored_high[0x20]; 5908 5909 u8 rp_cnp_ignored_low[0x20]; 5910 5911 u8 rp_cnp_handled_high[0x20]; 5912 5913 u8 rp_cnp_handled_low[0x20]; 5914 5915 u8 reserved_at_140[0x100]; 5916 5917 u8 time_stamp_high[0x20]; 5918 5919 u8 time_stamp_low[0x20]; 5920 5921 u8 accumulators_period[0x20]; 5922 5923 u8 np_ecn_marked_roce_packets_high[0x20]; 5924 5925 u8 np_ecn_marked_roce_packets_low[0x20]; 5926 5927 u8 np_cnp_sent_high[0x20]; 5928 5929 u8 np_cnp_sent_low[0x20]; 5930 5931 u8 reserved_at_320[0x560]; 5932 }; 5933 5934 struct mlx5_ifc_query_cong_statistics_in_bits { 5935 u8 opcode[0x10]; 5936 u8 reserved_at_10[0x10]; 5937 5938 u8 reserved_at_20[0x10]; 5939 u8 op_mod[0x10]; 5940 5941 u8 clear[0x1]; 5942 u8 reserved_at_41[0x1f]; 5943 5944 u8 reserved_at_60[0x20]; 5945 }; 5946 5947 struct mlx5_ifc_query_cong_params_out_bits { 5948 u8 status[0x8]; 5949 u8 reserved_at_8[0x18]; 5950 5951 u8 syndrome[0x20]; 5952 5953 u8 reserved_at_40[0x40]; 5954 5955 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 5956 }; 5957 5958 struct mlx5_ifc_query_cong_params_in_bits { 5959 u8 opcode[0x10]; 5960 u8 reserved_at_10[0x10]; 5961 5962 u8 reserved_at_20[0x10]; 5963 u8 op_mod[0x10]; 5964 5965 u8 reserved_at_40[0x1c]; 5966 u8 cong_protocol[0x4]; 5967 5968 u8 reserved_at_60[0x20]; 5969 }; 5970 5971 struct mlx5_ifc_query_adapter_out_bits { 5972 u8 status[0x8]; 5973 u8 reserved_at_8[0x18]; 5974 5975 u8 syndrome[0x20]; 5976 5977 u8 reserved_at_40[0x40]; 5978 5979 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct; 5980 }; 5981 5982 struct mlx5_ifc_query_adapter_in_bits { 5983 u8 opcode[0x10]; 5984 u8 reserved_at_10[0x10]; 5985 5986 u8 reserved_at_20[0x10]; 5987 u8 op_mod[0x10]; 5988 5989 u8 reserved_at_40[0x40]; 5990 }; 5991 5992 struct mlx5_ifc_qp_2rst_out_bits { 5993 u8 status[0x8]; 5994 u8 reserved_at_8[0x18]; 5995 5996 u8 syndrome[0x20]; 5997 5998 u8 reserved_at_40[0x40]; 5999 }; 6000 6001 struct mlx5_ifc_qp_2rst_in_bits { 6002 u8 opcode[0x10]; 6003 u8 uid[0x10]; 6004 6005 u8 reserved_at_20[0x10]; 6006 u8 op_mod[0x10]; 6007 6008 u8 reserved_at_40[0x8]; 6009 u8 qpn[0x18]; 6010 6011 u8 reserved_at_60[0x20]; 6012 }; 6013 6014 struct mlx5_ifc_qp_2err_out_bits { 6015 u8 status[0x8]; 6016 u8 reserved_at_8[0x18]; 6017 6018 u8 syndrome[0x20]; 6019 6020 u8 reserved_at_40[0x40]; 6021 }; 6022 6023 struct mlx5_ifc_qp_2err_in_bits { 6024 u8 opcode[0x10]; 6025 u8 uid[0x10]; 6026 6027 u8 reserved_at_20[0x10]; 6028 u8 op_mod[0x10]; 6029 6030 u8 reserved_at_40[0x8]; 6031 u8 qpn[0x18]; 6032 6033 u8 reserved_at_60[0x20]; 6034 }; 6035 6036 struct mlx5_ifc_page_fault_resume_out_bits { 6037 u8 status[0x8]; 6038 u8 reserved_at_8[0x18]; 6039 6040 u8 syndrome[0x20]; 6041 6042 u8 reserved_at_40[0x40]; 6043 }; 6044 6045 struct mlx5_ifc_page_fault_resume_in_bits { 6046 u8 opcode[0x10]; 6047 u8 reserved_at_10[0x10]; 6048 6049 u8 reserved_at_20[0x10]; 6050 u8 op_mod[0x10]; 6051 6052 u8 error[0x1]; 6053 u8 reserved_at_41[0x4]; 6054 u8 page_fault_type[0x3]; 6055 u8 wq_number[0x18]; 6056 6057 u8 reserved_at_60[0x8]; 6058 u8 token[0x18]; 6059 }; 6060 6061 struct mlx5_ifc_nop_out_bits { 6062 u8 status[0x8]; 6063 u8 reserved_at_8[0x18]; 6064 6065 u8 syndrome[0x20]; 6066 6067 u8 reserved_at_40[0x40]; 6068 }; 6069 6070 struct mlx5_ifc_nop_in_bits { 6071 u8 opcode[0x10]; 6072 u8 reserved_at_10[0x10]; 6073 6074 u8 reserved_at_20[0x10]; 6075 u8 op_mod[0x10]; 6076 6077 u8 reserved_at_40[0x40]; 6078 }; 6079 6080 struct mlx5_ifc_modify_vport_state_out_bits { 6081 u8 status[0x8]; 6082 u8 reserved_at_8[0x18]; 6083 6084 u8 syndrome[0x20]; 6085 6086 u8 reserved_at_40[0x40]; 6087 }; 6088 6089 struct mlx5_ifc_modify_vport_state_in_bits { 6090 u8 opcode[0x10]; 6091 u8 reserved_at_10[0x10]; 6092 6093 u8 reserved_at_20[0x10]; 6094 u8 op_mod[0x10]; 6095 6096 u8 other_vport[0x1]; 6097 u8 reserved_at_41[0xf]; 6098 u8 vport_number[0x10]; 6099 6100 u8 reserved_at_60[0x18]; 6101 u8 admin_state[0x4]; 6102 u8 reserved_at_7c[0x4]; 6103 }; 6104 6105 struct mlx5_ifc_modify_tis_out_bits { 6106 u8 status[0x8]; 6107 u8 reserved_at_8[0x18]; 6108 6109 u8 syndrome[0x20]; 6110 6111 u8 reserved_at_40[0x40]; 6112 }; 6113 6114 struct mlx5_ifc_modify_tis_bitmask_bits { 6115 u8 reserved_at_0[0x20]; 6116 6117 u8 reserved_at_20[0x1d]; 6118 u8 lag_tx_port_affinity[0x1]; 6119 u8 strict_lag_tx_port_affinity[0x1]; 6120 u8 prio[0x1]; 6121 }; 6122 6123 struct mlx5_ifc_modify_tis_in_bits { 6124 u8 opcode[0x10]; 6125 u8 uid[0x10]; 6126 6127 u8 reserved_at_20[0x10]; 6128 u8 op_mod[0x10]; 6129 6130 u8 reserved_at_40[0x8]; 6131 u8 tisn[0x18]; 6132 6133 u8 reserved_at_60[0x20]; 6134 6135 struct mlx5_ifc_modify_tis_bitmask_bits bitmask; 6136 6137 u8 reserved_at_c0[0x40]; 6138 6139 struct mlx5_ifc_tisc_bits ctx; 6140 }; 6141 6142 struct mlx5_ifc_modify_tir_bitmask_bits { 6143 u8 reserved_at_0[0x20]; 6144 6145 u8 reserved_at_20[0x1b]; 6146 u8 self_lb_en[0x1]; 6147 u8 reserved_at_3c[0x1]; 6148 u8 hash[0x1]; 6149 u8 reserved_at_3e[0x1]; 6150 u8 lro[0x1]; 6151 }; 6152 6153 struct mlx5_ifc_modify_tir_out_bits { 6154 u8 status[0x8]; 6155 u8 reserved_at_8[0x18]; 6156 6157 u8 syndrome[0x20]; 6158 6159 u8 reserved_at_40[0x40]; 6160 }; 6161 6162 struct mlx5_ifc_modify_tir_in_bits { 6163 u8 opcode[0x10]; 6164 u8 uid[0x10]; 6165 6166 u8 reserved_at_20[0x10]; 6167 u8 op_mod[0x10]; 6168 6169 u8 reserved_at_40[0x8]; 6170 u8 tirn[0x18]; 6171 6172 u8 reserved_at_60[0x20]; 6173 6174 struct mlx5_ifc_modify_tir_bitmask_bits bitmask; 6175 6176 u8 reserved_at_c0[0x40]; 6177 6178 struct mlx5_ifc_tirc_bits ctx; 6179 }; 6180 6181 struct mlx5_ifc_modify_sq_out_bits { 6182 u8 status[0x8]; 6183 u8 reserved_at_8[0x18]; 6184 6185 u8 syndrome[0x20]; 6186 6187 u8 reserved_at_40[0x40]; 6188 }; 6189 6190 struct mlx5_ifc_modify_sq_in_bits { 6191 u8 opcode[0x10]; 6192 u8 uid[0x10]; 6193 6194 u8 reserved_at_20[0x10]; 6195 u8 op_mod[0x10]; 6196 6197 u8 sq_state[0x4]; 6198 u8 reserved_at_44[0x4]; 6199 u8 sqn[0x18]; 6200 6201 u8 reserved_at_60[0x20]; 6202 6203 u8 modify_bitmask[0x40]; 6204 6205 u8 reserved_at_c0[0x40]; 6206 6207 struct mlx5_ifc_sqc_bits ctx; 6208 }; 6209 6210 struct mlx5_ifc_modify_scheduling_element_out_bits { 6211 u8 status[0x8]; 6212 u8 reserved_at_8[0x18]; 6213 6214 u8 syndrome[0x20]; 6215 6216 u8 reserved_at_40[0x1c0]; 6217 }; 6218 6219 enum { 6220 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1, 6221 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2, 6222 }; 6223 6224 struct mlx5_ifc_modify_scheduling_element_in_bits { 6225 u8 opcode[0x10]; 6226 u8 reserved_at_10[0x10]; 6227 6228 u8 reserved_at_20[0x10]; 6229 u8 op_mod[0x10]; 6230 6231 u8 scheduling_hierarchy[0x8]; 6232 u8 reserved_at_48[0x18]; 6233 6234 u8 scheduling_element_id[0x20]; 6235 6236 u8 reserved_at_80[0x20]; 6237 6238 u8 modify_bitmask[0x20]; 6239 6240 u8 reserved_at_c0[0x40]; 6241 6242 struct mlx5_ifc_scheduling_context_bits scheduling_context; 6243 6244 u8 reserved_at_300[0x100]; 6245 }; 6246 6247 struct mlx5_ifc_modify_rqt_out_bits { 6248 u8 status[0x8]; 6249 u8 reserved_at_8[0x18]; 6250 6251 u8 syndrome[0x20]; 6252 6253 u8 reserved_at_40[0x40]; 6254 }; 6255 6256 struct mlx5_ifc_rqt_bitmask_bits { 6257 u8 reserved_at_0[0x20]; 6258 6259 u8 reserved_at_20[0x1f]; 6260 u8 rqn_list[0x1]; 6261 }; 6262 6263 struct mlx5_ifc_modify_rqt_in_bits { 6264 u8 opcode[0x10]; 6265 u8 uid[0x10]; 6266 6267 u8 reserved_at_20[0x10]; 6268 u8 op_mod[0x10]; 6269 6270 u8 reserved_at_40[0x8]; 6271 u8 rqtn[0x18]; 6272 6273 u8 reserved_at_60[0x20]; 6274 6275 struct mlx5_ifc_rqt_bitmask_bits bitmask; 6276 6277 u8 reserved_at_c0[0x40]; 6278 6279 struct mlx5_ifc_rqtc_bits ctx; 6280 }; 6281 6282 struct mlx5_ifc_modify_rq_out_bits { 6283 u8 status[0x8]; 6284 u8 reserved_at_8[0x18]; 6285 6286 u8 syndrome[0x20]; 6287 6288 u8 reserved_at_40[0x40]; 6289 }; 6290 6291 enum { 6292 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1, 6293 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2, 6294 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3, 6295 }; 6296 6297 struct mlx5_ifc_modify_rq_in_bits { 6298 u8 opcode[0x10]; 6299 u8 uid[0x10]; 6300 6301 u8 reserved_at_20[0x10]; 6302 u8 op_mod[0x10]; 6303 6304 u8 rq_state[0x4]; 6305 u8 reserved_at_44[0x4]; 6306 u8 rqn[0x18]; 6307 6308 u8 reserved_at_60[0x20]; 6309 6310 u8 modify_bitmask[0x40]; 6311 6312 u8 reserved_at_c0[0x40]; 6313 6314 struct mlx5_ifc_rqc_bits ctx; 6315 }; 6316 6317 struct mlx5_ifc_modify_rmp_out_bits { 6318 u8 status[0x8]; 6319 u8 reserved_at_8[0x18]; 6320 6321 u8 syndrome[0x20]; 6322 6323 u8 reserved_at_40[0x40]; 6324 }; 6325 6326 struct mlx5_ifc_rmp_bitmask_bits { 6327 u8 reserved_at_0[0x20]; 6328 6329 u8 reserved_at_20[0x1f]; 6330 u8 lwm[0x1]; 6331 }; 6332 6333 struct mlx5_ifc_modify_rmp_in_bits { 6334 u8 opcode[0x10]; 6335 u8 uid[0x10]; 6336 6337 u8 reserved_at_20[0x10]; 6338 u8 op_mod[0x10]; 6339 6340 u8 rmp_state[0x4]; 6341 u8 reserved_at_44[0x4]; 6342 u8 rmpn[0x18]; 6343 6344 u8 reserved_at_60[0x20]; 6345 6346 struct mlx5_ifc_rmp_bitmask_bits bitmask; 6347 6348 u8 reserved_at_c0[0x40]; 6349 6350 struct mlx5_ifc_rmpc_bits ctx; 6351 }; 6352 6353 struct mlx5_ifc_modify_nic_vport_context_out_bits { 6354 u8 status[0x8]; 6355 u8 reserved_at_8[0x18]; 6356 6357 u8 syndrome[0x20]; 6358 6359 u8 reserved_at_40[0x40]; 6360 }; 6361 6362 struct mlx5_ifc_modify_nic_vport_field_select_bits { 6363 u8 reserved_at_0[0x12]; 6364 u8 affiliation[0x1]; 6365 u8 reserved_at_13[0x1]; 6366 u8 disable_uc_local_lb[0x1]; 6367 u8 disable_mc_local_lb[0x1]; 6368 u8 node_guid[0x1]; 6369 u8 port_guid[0x1]; 6370 u8 min_inline[0x1]; 6371 u8 mtu[0x1]; 6372 u8 change_event[0x1]; 6373 u8 promisc[0x1]; 6374 u8 permanent_address[0x1]; 6375 u8 addresses_list[0x1]; 6376 u8 roce_en[0x1]; 6377 u8 reserved_at_1f[0x1]; 6378 }; 6379 6380 struct mlx5_ifc_modify_nic_vport_context_in_bits { 6381 u8 opcode[0x10]; 6382 u8 reserved_at_10[0x10]; 6383 6384 u8 reserved_at_20[0x10]; 6385 u8 op_mod[0x10]; 6386 6387 u8 other_vport[0x1]; 6388 u8 reserved_at_41[0xf]; 6389 u8 vport_number[0x10]; 6390 6391 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select; 6392 6393 u8 reserved_at_80[0x780]; 6394 6395 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 6396 }; 6397 6398 struct mlx5_ifc_modify_hca_vport_context_out_bits { 6399 u8 status[0x8]; 6400 u8 reserved_at_8[0x18]; 6401 6402 u8 syndrome[0x20]; 6403 6404 u8 reserved_at_40[0x40]; 6405 }; 6406 6407 struct mlx5_ifc_modify_hca_vport_context_in_bits { 6408 u8 opcode[0x10]; 6409 u8 reserved_at_10[0x10]; 6410 6411 u8 reserved_at_20[0x10]; 6412 u8 op_mod[0x10]; 6413 6414 u8 other_vport[0x1]; 6415 u8 reserved_at_41[0xb]; 6416 u8 port_num[0x4]; 6417 u8 vport_number[0x10]; 6418 6419 u8 reserved_at_60[0x20]; 6420 6421 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 6422 }; 6423 6424 struct mlx5_ifc_modify_cq_out_bits { 6425 u8 status[0x8]; 6426 u8 reserved_at_8[0x18]; 6427 6428 u8 syndrome[0x20]; 6429 6430 u8 reserved_at_40[0x40]; 6431 }; 6432 6433 enum { 6434 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0, 6435 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1, 6436 }; 6437 6438 struct mlx5_ifc_modify_cq_in_bits { 6439 u8 opcode[0x10]; 6440 u8 uid[0x10]; 6441 6442 u8 reserved_at_20[0x10]; 6443 u8 op_mod[0x10]; 6444 6445 u8 reserved_at_40[0x8]; 6446 u8 cqn[0x18]; 6447 6448 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select; 6449 6450 struct mlx5_ifc_cqc_bits cq_context; 6451 6452 u8 reserved_at_280[0x60]; 6453 6454 u8 cq_umem_valid[0x1]; 6455 u8 reserved_at_2e1[0x1f]; 6456 6457 u8 reserved_at_300[0x580]; 6458 6459 u8 pas[][0x40]; 6460 }; 6461 6462 struct mlx5_ifc_modify_cong_status_out_bits { 6463 u8 status[0x8]; 6464 u8 reserved_at_8[0x18]; 6465 6466 u8 syndrome[0x20]; 6467 6468 u8 reserved_at_40[0x40]; 6469 }; 6470 6471 struct mlx5_ifc_modify_cong_status_in_bits { 6472 u8 opcode[0x10]; 6473 u8 reserved_at_10[0x10]; 6474 6475 u8 reserved_at_20[0x10]; 6476 u8 op_mod[0x10]; 6477 6478 u8 reserved_at_40[0x18]; 6479 u8 priority[0x4]; 6480 u8 cong_protocol[0x4]; 6481 6482 u8 enable[0x1]; 6483 u8 tag_enable[0x1]; 6484 u8 reserved_at_62[0x1e]; 6485 }; 6486 6487 struct mlx5_ifc_modify_cong_params_out_bits { 6488 u8 status[0x8]; 6489 u8 reserved_at_8[0x18]; 6490 6491 u8 syndrome[0x20]; 6492 6493 u8 reserved_at_40[0x40]; 6494 }; 6495 6496 struct mlx5_ifc_modify_cong_params_in_bits { 6497 u8 opcode[0x10]; 6498 u8 reserved_at_10[0x10]; 6499 6500 u8 reserved_at_20[0x10]; 6501 u8 op_mod[0x10]; 6502 6503 u8 reserved_at_40[0x1c]; 6504 u8 cong_protocol[0x4]; 6505 6506 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select; 6507 6508 u8 reserved_at_80[0x80]; 6509 6510 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 6511 }; 6512 6513 struct mlx5_ifc_manage_pages_out_bits { 6514 u8 status[0x8]; 6515 u8 reserved_at_8[0x18]; 6516 6517 u8 syndrome[0x20]; 6518 6519 u8 output_num_entries[0x20]; 6520 6521 u8 reserved_at_60[0x20]; 6522 6523 u8 pas[][0x40]; 6524 }; 6525 6526 enum { 6527 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL = 0x0, 6528 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS = 0x1, 6529 MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES = 0x2, 6530 }; 6531 6532 struct mlx5_ifc_manage_pages_in_bits { 6533 u8 opcode[0x10]; 6534 u8 reserved_at_10[0x10]; 6535 6536 u8 reserved_at_20[0x10]; 6537 u8 op_mod[0x10]; 6538 6539 u8 embedded_cpu_function[0x1]; 6540 u8 reserved_at_41[0xf]; 6541 u8 function_id[0x10]; 6542 6543 u8 input_num_entries[0x20]; 6544 6545 u8 pas[][0x40]; 6546 }; 6547 6548 struct mlx5_ifc_mad_ifc_out_bits { 6549 u8 status[0x8]; 6550 u8 reserved_at_8[0x18]; 6551 6552 u8 syndrome[0x20]; 6553 6554 u8 reserved_at_40[0x40]; 6555 6556 u8 response_mad_packet[256][0x8]; 6557 }; 6558 6559 struct mlx5_ifc_mad_ifc_in_bits { 6560 u8 opcode[0x10]; 6561 u8 reserved_at_10[0x10]; 6562 6563 u8 reserved_at_20[0x10]; 6564 u8 op_mod[0x10]; 6565 6566 u8 remote_lid[0x10]; 6567 u8 reserved_at_50[0x8]; 6568 u8 port[0x8]; 6569 6570 u8 reserved_at_60[0x20]; 6571 6572 u8 mad[256][0x8]; 6573 }; 6574 6575 struct mlx5_ifc_init_hca_out_bits { 6576 u8 status[0x8]; 6577 u8 reserved_at_8[0x18]; 6578 6579 u8 syndrome[0x20]; 6580 6581 u8 reserved_at_40[0x40]; 6582 }; 6583 6584 struct mlx5_ifc_init_hca_in_bits { 6585 u8 opcode[0x10]; 6586 u8 reserved_at_10[0x10]; 6587 6588 u8 reserved_at_20[0x10]; 6589 u8 op_mod[0x10]; 6590 6591 u8 reserved_at_40[0x40]; 6592 u8 sw_owner_id[4][0x20]; 6593 }; 6594 6595 struct mlx5_ifc_init2rtr_qp_out_bits { 6596 u8 status[0x8]; 6597 u8 reserved_at_8[0x18]; 6598 6599 u8 syndrome[0x20]; 6600 6601 u8 reserved_at_40[0x20]; 6602 u8 ece[0x20]; 6603 }; 6604 6605 struct mlx5_ifc_init2rtr_qp_in_bits { 6606 u8 opcode[0x10]; 6607 u8 uid[0x10]; 6608 6609 u8 reserved_at_20[0x10]; 6610 u8 op_mod[0x10]; 6611 6612 u8 reserved_at_40[0x8]; 6613 u8 qpn[0x18]; 6614 6615 u8 reserved_at_60[0x20]; 6616 6617 u8 opt_param_mask[0x20]; 6618 6619 u8 ece[0x20]; 6620 6621 struct mlx5_ifc_qpc_bits qpc; 6622 6623 u8 reserved_at_800[0x80]; 6624 }; 6625 6626 struct mlx5_ifc_init2init_qp_out_bits { 6627 u8 status[0x8]; 6628 u8 reserved_at_8[0x18]; 6629 6630 u8 syndrome[0x20]; 6631 6632 u8 reserved_at_40[0x20]; 6633 u8 ece[0x20]; 6634 }; 6635 6636 struct mlx5_ifc_init2init_qp_in_bits { 6637 u8 opcode[0x10]; 6638 u8 uid[0x10]; 6639 6640 u8 reserved_at_20[0x10]; 6641 u8 op_mod[0x10]; 6642 6643 u8 reserved_at_40[0x8]; 6644 u8 qpn[0x18]; 6645 6646 u8 reserved_at_60[0x20]; 6647 6648 u8 opt_param_mask[0x20]; 6649 6650 u8 ece[0x20]; 6651 6652 struct mlx5_ifc_qpc_bits qpc; 6653 6654 u8 reserved_at_800[0x80]; 6655 }; 6656 6657 struct mlx5_ifc_get_dropped_packet_log_out_bits { 6658 u8 status[0x8]; 6659 u8 reserved_at_8[0x18]; 6660 6661 u8 syndrome[0x20]; 6662 6663 u8 reserved_at_40[0x40]; 6664 6665 u8 packet_headers_log[128][0x8]; 6666 6667 u8 packet_syndrome[64][0x8]; 6668 }; 6669 6670 struct mlx5_ifc_get_dropped_packet_log_in_bits { 6671 u8 opcode[0x10]; 6672 u8 reserved_at_10[0x10]; 6673 6674 u8 reserved_at_20[0x10]; 6675 u8 op_mod[0x10]; 6676 6677 u8 reserved_at_40[0x40]; 6678 }; 6679 6680 struct mlx5_ifc_gen_eqe_in_bits { 6681 u8 opcode[0x10]; 6682 u8 reserved_at_10[0x10]; 6683 6684 u8 reserved_at_20[0x10]; 6685 u8 op_mod[0x10]; 6686 6687 u8 reserved_at_40[0x18]; 6688 u8 eq_number[0x8]; 6689 6690 u8 reserved_at_60[0x20]; 6691 6692 u8 eqe[64][0x8]; 6693 }; 6694 6695 struct mlx5_ifc_gen_eq_out_bits { 6696 u8 status[0x8]; 6697 u8 reserved_at_8[0x18]; 6698 6699 u8 syndrome[0x20]; 6700 6701 u8 reserved_at_40[0x40]; 6702 }; 6703 6704 struct mlx5_ifc_enable_hca_out_bits { 6705 u8 status[0x8]; 6706 u8 reserved_at_8[0x18]; 6707 6708 u8 syndrome[0x20]; 6709 6710 u8 reserved_at_40[0x20]; 6711 }; 6712 6713 struct mlx5_ifc_enable_hca_in_bits { 6714 u8 opcode[0x10]; 6715 u8 reserved_at_10[0x10]; 6716 6717 u8 reserved_at_20[0x10]; 6718 u8 op_mod[0x10]; 6719 6720 u8 embedded_cpu_function[0x1]; 6721 u8 reserved_at_41[0xf]; 6722 u8 function_id[0x10]; 6723 6724 u8 reserved_at_60[0x20]; 6725 }; 6726 6727 struct mlx5_ifc_drain_dct_out_bits { 6728 u8 status[0x8]; 6729 u8 reserved_at_8[0x18]; 6730 6731 u8 syndrome[0x20]; 6732 6733 u8 reserved_at_40[0x40]; 6734 }; 6735 6736 struct mlx5_ifc_drain_dct_in_bits { 6737 u8 opcode[0x10]; 6738 u8 uid[0x10]; 6739 6740 u8 reserved_at_20[0x10]; 6741 u8 op_mod[0x10]; 6742 6743 u8 reserved_at_40[0x8]; 6744 u8 dctn[0x18]; 6745 6746 u8 reserved_at_60[0x20]; 6747 }; 6748 6749 struct mlx5_ifc_disable_hca_out_bits { 6750 u8 status[0x8]; 6751 u8 reserved_at_8[0x18]; 6752 6753 u8 syndrome[0x20]; 6754 6755 u8 reserved_at_40[0x20]; 6756 }; 6757 6758 struct mlx5_ifc_disable_hca_in_bits { 6759 u8 opcode[0x10]; 6760 u8 reserved_at_10[0x10]; 6761 6762 u8 reserved_at_20[0x10]; 6763 u8 op_mod[0x10]; 6764 6765 u8 embedded_cpu_function[0x1]; 6766 u8 reserved_at_41[0xf]; 6767 u8 function_id[0x10]; 6768 6769 u8 reserved_at_60[0x20]; 6770 }; 6771 6772 struct mlx5_ifc_detach_from_mcg_out_bits { 6773 u8 status[0x8]; 6774 u8 reserved_at_8[0x18]; 6775 6776 u8 syndrome[0x20]; 6777 6778 u8 reserved_at_40[0x40]; 6779 }; 6780 6781 struct mlx5_ifc_detach_from_mcg_in_bits { 6782 u8 opcode[0x10]; 6783 u8 uid[0x10]; 6784 6785 u8 reserved_at_20[0x10]; 6786 u8 op_mod[0x10]; 6787 6788 u8 reserved_at_40[0x8]; 6789 u8 qpn[0x18]; 6790 6791 u8 reserved_at_60[0x20]; 6792 6793 u8 multicast_gid[16][0x8]; 6794 }; 6795 6796 struct mlx5_ifc_destroy_xrq_out_bits { 6797 u8 status[0x8]; 6798 u8 reserved_at_8[0x18]; 6799 6800 u8 syndrome[0x20]; 6801 6802 u8 reserved_at_40[0x40]; 6803 }; 6804 6805 struct mlx5_ifc_destroy_xrq_in_bits { 6806 u8 opcode[0x10]; 6807 u8 uid[0x10]; 6808 6809 u8 reserved_at_20[0x10]; 6810 u8 op_mod[0x10]; 6811 6812 u8 reserved_at_40[0x8]; 6813 u8 xrqn[0x18]; 6814 6815 u8 reserved_at_60[0x20]; 6816 }; 6817 6818 struct mlx5_ifc_destroy_xrc_srq_out_bits { 6819 u8 status[0x8]; 6820 u8 reserved_at_8[0x18]; 6821 6822 u8 syndrome[0x20]; 6823 6824 u8 reserved_at_40[0x40]; 6825 }; 6826 6827 struct mlx5_ifc_destroy_xrc_srq_in_bits { 6828 u8 opcode[0x10]; 6829 u8 uid[0x10]; 6830 6831 u8 reserved_at_20[0x10]; 6832 u8 op_mod[0x10]; 6833 6834 u8 reserved_at_40[0x8]; 6835 u8 xrc_srqn[0x18]; 6836 6837 u8 reserved_at_60[0x20]; 6838 }; 6839 6840 struct mlx5_ifc_destroy_tis_out_bits { 6841 u8 status[0x8]; 6842 u8 reserved_at_8[0x18]; 6843 6844 u8 syndrome[0x20]; 6845 6846 u8 reserved_at_40[0x40]; 6847 }; 6848 6849 struct mlx5_ifc_destroy_tis_in_bits { 6850 u8 opcode[0x10]; 6851 u8 uid[0x10]; 6852 6853 u8 reserved_at_20[0x10]; 6854 u8 op_mod[0x10]; 6855 6856 u8 reserved_at_40[0x8]; 6857 u8 tisn[0x18]; 6858 6859 u8 reserved_at_60[0x20]; 6860 }; 6861 6862 struct mlx5_ifc_destroy_tir_out_bits { 6863 u8 status[0x8]; 6864 u8 reserved_at_8[0x18]; 6865 6866 u8 syndrome[0x20]; 6867 6868 u8 reserved_at_40[0x40]; 6869 }; 6870 6871 struct mlx5_ifc_destroy_tir_in_bits { 6872 u8 opcode[0x10]; 6873 u8 uid[0x10]; 6874 6875 u8 reserved_at_20[0x10]; 6876 u8 op_mod[0x10]; 6877 6878 u8 reserved_at_40[0x8]; 6879 u8 tirn[0x18]; 6880 6881 u8 reserved_at_60[0x20]; 6882 }; 6883 6884 struct mlx5_ifc_destroy_srq_out_bits { 6885 u8 status[0x8]; 6886 u8 reserved_at_8[0x18]; 6887 6888 u8 syndrome[0x20]; 6889 6890 u8 reserved_at_40[0x40]; 6891 }; 6892 6893 struct mlx5_ifc_destroy_srq_in_bits { 6894 u8 opcode[0x10]; 6895 u8 uid[0x10]; 6896 6897 u8 reserved_at_20[0x10]; 6898 u8 op_mod[0x10]; 6899 6900 u8 reserved_at_40[0x8]; 6901 u8 srqn[0x18]; 6902 6903 u8 reserved_at_60[0x20]; 6904 }; 6905 6906 struct mlx5_ifc_destroy_sq_out_bits { 6907 u8 status[0x8]; 6908 u8 reserved_at_8[0x18]; 6909 6910 u8 syndrome[0x20]; 6911 6912 u8 reserved_at_40[0x40]; 6913 }; 6914 6915 struct mlx5_ifc_destroy_sq_in_bits { 6916 u8 opcode[0x10]; 6917 u8 uid[0x10]; 6918 6919 u8 reserved_at_20[0x10]; 6920 u8 op_mod[0x10]; 6921 6922 u8 reserved_at_40[0x8]; 6923 u8 sqn[0x18]; 6924 6925 u8 reserved_at_60[0x20]; 6926 }; 6927 6928 struct mlx5_ifc_destroy_scheduling_element_out_bits { 6929 u8 status[0x8]; 6930 u8 reserved_at_8[0x18]; 6931 6932 u8 syndrome[0x20]; 6933 6934 u8 reserved_at_40[0x1c0]; 6935 }; 6936 6937 struct mlx5_ifc_destroy_scheduling_element_in_bits { 6938 u8 opcode[0x10]; 6939 u8 reserved_at_10[0x10]; 6940 6941 u8 reserved_at_20[0x10]; 6942 u8 op_mod[0x10]; 6943 6944 u8 scheduling_hierarchy[0x8]; 6945 u8 reserved_at_48[0x18]; 6946 6947 u8 scheduling_element_id[0x20]; 6948 6949 u8 reserved_at_80[0x180]; 6950 }; 6951 6952 struct mlx5_ifc_destroy_rqt_out_bits { 6953 u8 status[0x8]; 6954 u8 reserved_at_8[0x18]; 6955 6956 u8 syndrome[0x20]; 6957 6958 u8 reserved_at_40[0x40]; 6959 }; 6960 6961 struct mlx5_ifc_destroy_rqt_in_bits { 6962 u8 opcode[0x10]; 6963 u8 uid[0x10]; 6964 6965 u8 reserved_at_20[0x10]; 6966 u8 op_mod[0x10]; 6967 6968 u8 reserved_at_40[0x8]; 6969 u8 rqtn[0x18]; 6970 6971 u8 reserved_at_60[0x20]; 6972 }; 6973 6974 struct mlx5_ifc_destroy_rq_out_bits { 6975 u8 status[0x8]; 6976 u8 reserved_at_8[0x18]; 6977 6978 u8 syndrome[0x20]; 6979 6980 u8 reserved_at_40[0x40]; 6981 }; 6982 6983 struct mlx5_ifc_destroy_rq_in_bits { 6984 u8 opcode[0x10]; 6985 u8 uid[0x10]; 6986 6987 u8 reserved_at_20[0x10]; 6988 u8 op_mod[0x10]; 6989 6990 u8 reserved_at_40[0x8]; 6991 u8 rqn[0x18]; 6992 6993 u8 reserved_at_60[0x20]; 6994 }; 6995 6996 struct mlx5_ifc_set_delay_drop_params_in_bits { 6997 u8 opcode[0x10]; 6998 u8 reserved_at_10[0x10]; 6999 7000 u8 reserved_at_20[0x10]; 7001 u8 op_mod[0x10]; 7002 7003 u8 reserved_at_40[0x20]; 7004 7005 u8 reserved_at_60[0x10]; 7006 u8 delay_drop_timeout[0x10]; 7007 }; 7008 7009 struct mlx5_ifc_set_delay_drop_params_out_bits { 7010 u8 status[0x8]; 7011 u8 reserved_at_8[0x18]; 7012 7013 u8 syndrome[0x20]; 7014 7015 u8 reserved_at_40[0x40]; 7016 }; 7017 7018 struct mlx5_ifc_destroy_rmp_out_bits { 7019 u8 status[0x8]; 7020 u8 reserved_at_8[0x18]; 7021 7022 u8 syndrome[0x20]; 7023 7024 u8 reserved_at_40[0x40]; 7025 }; 7026 7027 struct mlx5_ifc_destroy_rmp_in_bits { 7028 u8 opcode[0x10]; 7029 u8 uid[0x10]; 7030 7031 u8 reserved_at_20[0x10]; 7032 u8 op_mod[0x10]; 7033 7034 u8 reserved_at_40[0x8]; 7035 u8 rmpn[0x18]; 7036 7037 u8 reserved_at_60[0x20]; 7038 }; 7039 7040 struct mlx5_ifc_destroy_qp_out_bits { 7041 u8 status[0x8]; 7042 u8 reserved_at_8[0x18]; 7043 7044 u8 syndrome[0x20]; 7045 7046 u8 reserved_at_40[0x40]; 7047 }; 7048 7049 struct mlx5_ifc_destroy_qp_in_bits { 7050 u8 opcode[0x10]; 7051 u8 uid[0x10]; 7052 7053 u8 reserved_at_20[0x10]; 7054 u8 op_mod[0x10]; 7055 7056 u8 reserved_at_40[0x8]; 7057 u8 qpn[0x18]; 7058 7059 u8 reserved_at_60[0x20]; 7060 }; 7061 7062 struct mlx5_ifc_destroy_psv_out_bits { 7063 u8 status[0x8]; 7064 u8 reserved_at_8[0x18]; 7065 7066 u8 syndrome[0x20]; 7067 7068 u8 reserved_at_40[0x40]; 7069 }; 7070 7071 struct mlx5_ifc_destroy_psv_in_bits { 7072 u8 opcode[0x10]; 7073 u8 reserved_at_10[0x10]; 7074 7075 u8 reserved_at_20[0x10]; 7076 u8 op_mod[0x10]; 7077 7078 u8 reserved_at_40[0x8]; 7079 u8 psvn[0x18]; 7080 7081 u8 reserved_at_60[0x20]; 7082 }; 7083 7084 struct mlx5_ifc_destroy_mkey_out_bits { 7085 u8 status[0x8]; 7086 u8 reserved_at_8[0x18]; 7087 7088 u8 syndrome[0x20]; 7089 7090 u8 reserved_at_40[0x40]; 7091 }; 7092 7093 struct mlx5_ifc_destroy_mkey_in_bits { 7094 u8 opcode[0x10]; 7095 u8 reserved_at_10[0x10]; 7096 7097 u8 reserved_at_20[0x10]; 7098 u8 op_mod[0x10]; 7099 7100 u8 reserved_at_40[0x8]; 7101 u8 mkey_index[0x18]; 7102 7103 u8 reserved_at_60[0x20]; 7104 }; 7105 7106 struct mlx5_ifc_destroy_flow_table_out_bits { 7107 u8 status[0x8]; 7108 u8 reserved_at_8[0x18]; 7109 7110 u8 syndrome[0x20]; 7111 7112 u8 reserved_at_40[0x40]; 7113 }; 7114 7115 struct mlx5_ifc_destroy_flow_table_in_bits { 7116 u8 opcode[0x10]; 7117 u8 reserved_at_10[0x10]; 7118 7119 u8 reserved_at_20[0x10]; 7120 u8 op_mod[0x10]; 7121 7122 u8 other_vport[0x1]; 7123 u8 reserved_at_41[0xf]; 7124 u8 vport_number[0x10]; 7125 7126 u8 reserved_at_60[0x20]; 7127 7128 u8 table_type[0x8]; 7129 u8 reserved_at_88[0x18]; 7130 7131 u8 reserved_at_a0[0x8]; 7132 u8 table_id[0x18]; 7133 7134 u8 reserved_at_c0[0x140]; 7135 }; 7136 7137 struct mlx5_ifc_destroy_flow_group_out_bits { 7138 u8 status[0x8]; 7139 u8 reserved_at_8[0x18]; 7140 7141 u8 syndrome[0x20]; 7142 7143 u8 reserved_at_40[0x40]; 7144 }; 7145 7146 struct mlx5_ifc_destroy_flow_group_in_bits { 7147 u8 opcode[0x10]; 7148 u8 reserved_at_10[0x10]; 7149 7150 u8 reserved_at_20[0x10]; 7151 u8 op_mod[0x10]; 7152 7153 u8 other_vport[0x1]; 7154 u8 reserved_at_41[0xf]; 7155 u8 vport_number[0x10]; 7156 7157 u8 reserved_at_60[0x20]; 7158 7159 u8 table_type[0x8]; 7160 u8 reserved_at_88[0x18]; 7161 7162 u8 reserved_at_a0[0x8]; 7163 u8 table_id[0x18]; 7164 7165 u8 group_id[0x20]; 7166 7167 u8 reserved_at_e0[0x120]; 7168 }; 7169 7170 struct mlx5_ifc_destroy_eq_out_bits { 7171 u8 status[0x8]; 7172 u8 reserved_at_8[0x18]; 7173 7174 u8 syndrome[0x20]; 7175 7176 u8 reserved_at_40[0x40]; 7177 }; 7178 7179 struct mlx5_ifc_destroy_eq_in_bits { 7180 u8 opcode[0x10]; 7181 u8 reserved_at_10[0x10]; 7182 7183 u8 reserved_at_20[0x10]; 7184 u8 op_mod[0x10]; 7185 7186 u8 reserved_at_40[0x18]; 7187 u8 eq_number[0x8]; 7188 7189 u8 reserved_at_60[0x20]; 7190 }; 7191 7192 struct mlx5_ifc_destroy_dct_out_bits { 7193 u8 status[0x8]; 7194 u8 reserved_at_8[0x18]; 7195 7196 u8 syndrome[0x20]; 7197 7198 u8 reserved_at_40[0x40]; 7199 }; 7200 7201 struct mlx5_ifc_destroy_dct_in_bits { 7202 u8 opcode[0x10]; 7203 u8 uid[0x10]; 7204 7205 u8 reserved_at_20[0x10]; 7206 u8 op_mod[0x10]; 7207 7208 u8 reserved_at_40[0x8]; 7209 u8 dctn[0x18]; 7210 7211 u8 reserved_at_60[0x20]; 7212 }; 7213 7214 struct mlx5_ifc_destroy_cq_out_bits { 7215 u8 status[0x8]; 7216 u8 reserved_at_8[0x18]; 7217 7218 u8 syndrome[0x20]; 7219 7220 u8 reserved_at_40[0x40]; 7221 }; 7222 7223 struct mlx5_ifc_destroy_cq_in_bits { 7224 u8 opcode[0x10]; 7225 u8 uid[0x10]; 7226 7227 u8 reserved_at_20[0x10]; 7228 u8 op_mod[0x10]; 7229 7230 u8 reserved_at_40[0x8]; 7231 u8 cqn[0x18]; 7232 7233 u8 reserved_at_60[0x20]; 7234 }; 7235 7236 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits { 7237 u8 status[0x8]; 7238 u8 reserved_at_8[0x18]; 7239 7240 u8 syndrome[0x20]; 7241 7242 u8 reserved_at_40[0x40]; 7243 }; 7244 7245 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits { 7246 u8 opcode[0x10]; 7247 u8 reserved_at_10[0x10]; 7248 7249 u8 reserved_at_20[0x10]; 7250 u8 op_mod[0x10]; 7251 7252 u8 reserved_at_40[0x20]; 7253 7254 u8 reserved_at_60[0x10]; 7255 u8 vxlan_udp_port[0x10]; 7256 }; 7257 7258 struct mlx5_ifc_delete_l2_table_entry_out_bits { 7259 u8 status[0x8]; 7260 u8 reserved_at_8[0x18]; 7261 7262 u8 syndrome[0x20]; 7263 7264 u8 reserved_at_40[0x40]; 7265 }; 7266 7267 struct mlx5_ifc_delete_l2_table_entry_in_bits { 7268 u8 opcode[0x10]; 7269 u8 reserved_at_10[0x10]; 7270 7271 u8 reserved_at_20[0x10]; 7272 u8 op_mod[0x10]; 7273 7274 u8 reserved_at_40[0x60]; 7275 7276 u8 reserved_at_a0[0x8]; 7277 u8 table_index[0x18]; 7278 7279 u8 reserved_at_c0[0x140]; 7280 }; 7281 7282 struct mlx5_ifc_delete_fte_out_bits { 7283 u8 status[0x8]; 7284 u8 reserved_at_8[0x18]; 7285 7286 u8 syndrome[0x20]; 7287 7288 u8 reserved_at_40[0x40]; 7289 }; 7290 7291 struct mlx5_ifc_delete_fte_in_bits { 7292 u8 opcode[0x10]; 7293 u8 reserved_at_10[0x10]; 7294 7295 u8 reserved_at_20[0x10]; 7296 u8 op_mod[0x10]; 7297 7298 u8 other_vport[0x1]; 7299 u8 reserved_at_41[0xf]; 7300 u8 vport_number[0x10]; 7301 7302 u8 reserved_at_60[0x20]; 7303 7304 u8 table_type[0x8]; 7305 u8 reserved_at_88[0x18]; 7306 7307 u8 reserved_at_a0[0x8]; 7308 u8 table_id[0x18]; 7309 7310 u8 reserved_at_c0[0x40]; 7311 7312 u8 flow_index[0x20]; 7313 7314 u8 reserved_at_120[0xe0]; 7315 }; 7316 7317 struct mlx5_ifc_dealloc_xrcd_out_bits { 7318 u8 status[0x8]; 7319 u8 reserved_at_8[0x18]; 7320 7321 u8 syndrome[0x20]; 7322 7323 u8 reserved_at_40[0x40]; 7324 }; 7325 7326 struct mlx5_ifc_dealloc_xrcd_in_bits { 7327 u8 opcode[0x10]; 7328 u8 uid[0x10]; 7329 7330 u8 reserved_at_20[0x10]; 7331 u8 op_mod[0x10]; 7332 7333 u8 reserved_at_40[0x8]; 7334 u8 xrcd[0x18]; 7335 7336 u8 reserved_at_60[0x20]; 7337 }; 7338 7339 struct mlx5_ifc_dealloc_uar_out_bits { 7340 u8 status[0x8]; 7341 u8 reserved_at_8[0x18]; 7342 7343 u8 syndrome[0x20]; 7344 7345 u8 reserved_at_40[0x40]; 7346 }; 7347 7348 struct mlx5_ifc_dealloc_uar_in_bits { 7349 u8 opcode[0x10]; 7350 u8 reserved_at_10[0x10]; 7351 7352 u8 reserved_at_20[0x10]; 7353 u8 op_mod[0x10]; 7354 7355 u8 reserved_at_40[0x8]; 7356 u8 uar[0x18]; 7357 7358 u8 reserved_at_60[0x20]; 7359 }; 7360 7361 struct mlx5_ifc_dealloc_transport_domain_out_bits { 7362 u8 status[0x8]; 7363 u8 reserved_at_8[0x18]; 7364 7365 u8 syndrome[0x20]; 7366 7367 u8 reserved_at_40[0x40]; 7368 }; 7369 7370 struct mlx5_ifc_dealloc_transport_domain_in_bits { 7371 u8 opcode[0x10]; 7372 u8 uid[0x10]; 7373 7374 u8 reserved_at_20[0x10]; 7375 u8 op_mod[0x10]; 7376 7377 u8 reserved_at_40[0x8]; 7378 u8 transport_domain[0x18]; 7379 7380 u8 reserved_at_60[0x20]; 7381 }; 7382 7383 struct mlx5_ifc_dealloc_q_counter_out_bits { 7384 u8 status[0x8]; 7385 u8 reserved_at_8[0x18]; 7386 7387 u8 syndrome[0x20]; 7388 7389 u8 reserved_at_40[0x40]; 7390 }; 7391 7392 struct mlx5_ifc_dealloc_q_counter_in_bits { 7393 u8 opcode[0x10]; 7394 u8 reserved_at_10[0x10]; 7395 7396 u8 reserved_at_20[0x10]; 7397 u8 op_mod[0x10]; 7398 7399 u8 reserved_at_40[0x18]; 7400 u8 counter_set_id[0x8]; 7401 7402 u8 reserved_at_60[0x20]; 7403 }; 7404 7405 struct mlx5_ifc_dealloc_pd_out_bits { 7406 u8 status[0x8]; 7407 u8 reserved_at_8[0x18]; 7408 7409 u8 syndrome[0x20]; 7410 7411 u8 reserved_at_40[0x40]; 7412 }; 7413 7414 struct mlx5_ifc_dealloc_pd_in_bits { 7415 u8 opcode[0x10]; 7416 u8 uid[0x10]; 7417 7418 u8 reserved_at_20[0x10]; 7419 u8 op_mod[0x10]; 7420 7421 u8 reserved_at_40[0x8]; 7422 u8 pd[0x18]; 7423 7424 u8 reserved_at_60[0x20]; 7425 }; 7426 7427 struct mlx5_ifc_dealloc_flow_counter_out_bits { 7428 u8 status[0x8]; 7429 u8 reserved_at_8[0x18]; 7430 7431 u8 syndrome[0x20]; 7432 7433 u8 reserved_at_40[0x40]; 7434 }; 7435 7436 struct mlx5_ifc_dealloc_flow_counter_in_bits { 7437 u8 opcode[0x10]; 7438 u8 reserved_at_10[0x10]; 7439 7440 u8 reserved_at_20[0x10]; 7441 u8 op_mod[0x10]; 7442 7443 u8 flow_counter_id[0x20]; 7444 7445 u8 reserved_at_60[0x20]; 7446 }; 7447 7448 struct mlx5_ifc_create_xrq_out_bits { 7449 u8 status[0x8]; 7450 u8 reserved_at_8[0x18]; 7451 7452 u8 syndrome[0x20]; 7453 7454 u8 reserved_at_40[0x8]; 7455 u8 xrqn[0x18]; 7456 7457 u8 reserved_at_60[0x20]; 7458 }; 7459 7460 struct mlx5_ifc_create_xrq_in_bits { 7461 u8 opcode[0x10]; 7462 u8 uid[0x10]; 7463 7464 u8 reserved_at_20[0x10]; 7465 u8 op_mod[0x10]; 7466 7467 u8 reserved_at_40[0x40]; 7468 7469 struct mlx5_ifc_xrqc_bits xrq_context; 7470 }; 7471 7472 struct mlx5_ifc_create_xrc_srq_out_bits { 7473 u8 status[0x8]; 7474 u8 reserved_at_8[0x18]; 7475 7476 u8 syndrome[0x20]; 7477 7478 u8 reserved_at_40[0x8]; 7479 u8 xrc_srqn[0x18]; 7480 7481 u8 reserved_at_60[0x20]; 7482 }; 7483 7484 struct mlx5_ifc_create_xrc_srq_in_bits { 7485 u8 opcode[0x10]; 7486 u8 uid[0x10]; 7487 7488 u8 reserved_at_20[0x10]; 7489 u8 op_mod[0x10]; 7490 7491 u8 reserved_at_40[0x40]; 7492 7493 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 7494 7495 u8 reserved_at_280[0x60]; 7496 7497 u8 xrc_srq_umem_valid[0x1]; 7498 u8 reserved_at_2e1[0x1f]; 7499 7500 u8 reserved_at_300[0x580]; 7501 7502 u8 pas[][0x40]; 7503 }; 7504 7505 struct mlx5_ifc_create_tis_out_bits { 7506 u8 status[0x8]; 7507 u8 reserved_at_8[0x18]; 7508 7509 u8 syndrome[0x20]; 7510 7511 u8 reserved_at_40[0x8]; 7512 u8 tisn[0x18]; 7513 7514 u8 reserved_at_60[0x20]; 7515 }; 7516 7517 struct mlx5_ifc_create_tis_in_bits { 7518 u8 opcode[0x10]; 7519 u8 uid[0x10]; 7520 7521 u8 reserved_at_20[0x10]; 7522 u8 op_mod[0x10]; 7523 7524 u8 reserved_at_40[0xc0]; 7525 7526 struct mlx5_ifc_tisc_bits ctx; 7527 }; 7528 7529 struct mlx5_ifc_create_tir_out_bits { 7530 u8 status[0x8]; 7531 u8 icm_address_63_40[0x18]; 7532 7533 u8 syndrome[0x20]; 7534 7535 u8 icm_address_39_32[0x8]; 7536 u8 tirn[0x18]; 7537 7538 u8 icm_address_31_0[0x20]; 7539 }; 7540 7541 struct mlx5_ifc_create_tir_in_bits { 7542 u8 opcode[0x10]; 7543 u8 uid[0x10]; 7544 7545 u8 reserved_at_20[0x10]; 7546 u8 op_mod[0x10]; 7547 7548 u8 reserved_at_40[0xc0]; 7549 7550 struct mlx5_ifc_tirc_bits ctx; 7551 }; 7552 7553 struct mlx5_ifc_create_srq_out_bits { 7554 u8 status[0x8]; 7555 u8 reserved_at_8[0x18]; 7556 7557 u8 syndrome[0x20]; 7558 7559 u8 reserved_at_40[0x8]; 7560 u8 srqn[0x18]; 7561 7562 u8 reserved_at_60[0x20]; 7563 }; 7564 7565 struct mlx5_ifc_create_srq_in_bits { 7566 u8 opcode[0x10]; 7567 u8 uid[0x10]; 7568 7569 u8 reserved_at_20[0x10]; 7570 u8 op_mod[0x10]; 7571 7572 u8 reserved_at_40[0x40]; 7573 7574 struct mlx5_ifc_srqc_bits srq_context_entry; 7575 7576 u8 reserved_at_280[0x600]; 7577 7578 u8 pas[][0x40]; 7579 }; 7580 7581 struct mlx5_ifc_create_sq_out_bits { 7582 u8 status[0x8]; 7583 u8 reserved_at_8[0x18]; 7584 7585 u8 syndrome[0x20]; 7586 7587 u8 reserved_at_40[0x8]; 7588 u8 sqn[0x18]; 7589 7590 u8 reserved_at_60[0x20]; 7591 }; 7592 7593 struct mlx5_ifc_create_sq_in_bits { 7594 u8 opcode[0x10]; 7595 u8 uid[0x10]; 7596 7597 u8 reserved_at_20[0x10]; 7598 u8 op_mod[0x10]; 7599 7600 u8 reserved_at_40[0xc0]; 7601 7602 struct mlx5_ifc_sqc_bits ctx; 7603 }; 7604 7605 struct mlx5_ifc_create_scheduling_element_out_bits { 7606 u8 status[0x8]; 7607 u8 reserved_at_8[0x18]; 7608 7609 u8 syndrome[0x20]; 7610 7611 u8 reserved_at_40[0x40]; 7612 7613 u8 scheduling_element_id[0x20]; 7614 7615 u8 reserved_at_a0[0x160]; 7616 }; 7617 7618 struct mlx5_ifc_create_scheduling_element_in_bits { 7619 u8 opcode[0x10]; 7620 u8 reserved_at_10[0x10]; 7621 7622 u8 reserved_at_20[0x10]; 7623 u8 op_mod[0x10]; 7624 7625 u8 scheduling_hierarchy[0x8]; 7626 u8 reserved_at_48[0x18]; 7627 7628 u8 reserved_at_60[0xa0]; 7629 7630 struct mlx5_ifc_scheduling_context_bits scheduling_context; 7631 7632 u8 reserved_at_300[0x100]; 7633 }; 7634 7635 struct mlx5_ifc_create_rqt_out_bits { 7636 u8 status[0x8]; 7637 u8 reserved_at_8[0x18]; 7638 7639 u8 syndrome[0x20]; 7640 7641 u8 reserved_at_40[0x8]; 7642 u8 rqtn[0x18]; 7643 7644 u8 reserved_at_60[0x20]; 7645 }; 7646 7647 struct mlx5_ifc_create_rqt_in_bits { 7648 u8 opcode[0x10]; 7649 u8 uid[0x10]; 7650 7651 u8 reserved_at_20[0x10]; 7652 u8 op_mod[0x10]; 7653 7654 u8 reserved_at_40[0xc0]; 7655 7656 struct mlx5_ifc_rqtc_bits rqt_context; 7657 }; 7658 7659 struct mlx5_ifc_create_rq_out_bits { 7660 u8 status[0x8]; 7661 u8 reserved_at_8[0x18]; 7662 7663 u8 syndrome[0x20]; 7664 7665 u8 reserved_at_40[0x8]; 7666 u8 rqn[0x18]; 7667 7668 u8 reserved_at_60[0x20]; 7669 }; 7670 7671 struct mlx5_ifc_create_rq_in_bits { 7672 u8 opcode[0x10]; 7673 u8 uid[0x10]; 7674 7675 u8 reserved_at_20[0x10]; 7676 u8 op_mod[0x10]; 7677 7678 u8 reserved_at_40[0xc0]; 7679 7680 struct mlx5_ifc_rqc_bits ctx; 7681 }; 7682 7683 struct mlx5_ifc_create_rmp_out_bits { 7684 u8 status[0x8]; 7685 u8 reserved_at_8[0x18]; 7686 7687 u8 syndrome[0x20]; 7688 7689 u8 reserved_at_40[0x8]; 7690 u8 rmpn[0x18]; 7691 7692 u8 reserved_at_60[0x20]; 7693 }; 7694 7695 struct mlx5_ifc_create_rmp_in_bits { 7696 u8 opcode[0x10]; 7697 u8 uid[0x10]; 7698 7699 u8 reserved_at_20[0x10]; 7700 u8 op_mod[0x10]; 7701 7702 u8 reserved_at_40[0xc0]; 7703 7704 struct mlx5_ifc_rmpc_bits ctx; 7705 }; 7706 7707 struct mlx5_ifc_create_qp_out_bits { 7708 u8 status[0x8]; 7709 u8 reserved_at_8[0x18]; 7710 7711 u8 syndrome[0x20]; 7712 7713 u8 reserved_at_40[0x8]; 7714 u8 qpn[0x18]; 7715 7716 u8 ece[0x20]; 7717 }; 7718 7719 struct mlx5_ifc_create_qp_in_bits { 7720 u8 opcode[0x10]; 7721 u8 uid[0x10]; 7722 7723 u8 reserved_at_20[0x10]; 7724 u8 op_mod[0x10]; 7725 7726 u8 reserved_at_40[0x40]; 7727 7728 u8 opt_param_mask[0x20]; 7729 7730 u8 ece[0x20]; 7731 7732 struct mlx5_ifc_qpc_bits qpc; 7733 7734 u8 reserved_at_800[0x60]; 7735 7736 u8 wq_umem_valid[0x1]; 7737 u8 reserved_at_861[0x1f]; 7738 7739 u8 pas[][0x40]; 7740 }; 7741 7742 struct mlx5_ifc_create_psv_out_bits { 7743 u8 status[0x8]; 7744 u8 reserved_at_8[0x18]; 7745 7746 u8 syndrome[0x20]; 7747 7748 u8 reserved_at_40[0x40]; 7749 7750 u8 reserved_at_80[0x8]; 7751 u8 psv0_index[0x18]; 7752 7753 u8 reserved_at_a0[0x8]; 7754 u8 psv1_index[0x18]; 7755 7756 u8 reserved_at_c0[0x8]; 7757 u8 psv2_index[0x18]; 7758 7759 u8 reserved_at_e0[0x8]; 7760 u8 psv3_index[0x18]; 7761 }; 7762 7763 struct mlx5_ifc_create_psv_in_bits { 7764 u8 opcode[0x10]; 7765 u8 reserved_at_10[0x10]; 7766 7767 u8 reserved_at_20[0x10]; 7768 u8 op_mod[0x10]; 7769 7770 u8 num_psv[0x4]; 7771 u8 reserved_at_44[0x4]; 7772 u8 pd[0x18]; 7773 7774 u8 reserved_at_60[0x20]; 7775 }; 7776 7777 struct mlx5_ifc_create_mkey_out_bits { 7778 u8 status[0x8]; 7779 u8 reserved_at_8[0x18]; 7780 7781 u8 syndrome[0x20]; 7782 7783 u8 reserved_at_40[0x8]; 7784 u8 mkey_index[0x18]; 7785 7786 u8 reserved_at_60[0x20]; 7787 }; 7788 7789 struct mlx5_ifc_create_mkey_in_bits { 7790 u8 opcode[0x10]; 7791 u8 reserved_at_10[0x10]; 7792 7793 u8 reserved_at_20[0x10]; 7794 u8 op_mod[0x10]; 7795 7796 u8 reserved_at_40[0x20]; 7797 7798 u8 pg_access[0x1]; 7799 u8 mkey_umem_valid[0x1]; 7800 u8 reserved_at_62[0x1e]; 7801 7802 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 7803 7804 u8 reserved_at_280[0x80]; 7805 7806 u8 translations_octword_actual_size[0x20]; 7807 7808 u8 reserved_at_320[0x560]; 7809 7810 u8 klm_pas_mtt[][0x20]; 7811 }; 7812 7813 enum { 7814 MLX5_FLOW_TABLE_TYPE_NIC_RX = 0x0, 7815 MLX5_FLOW_TABLE_TYPE_NIC_TX = 0x1, 7816 MLX5_FLOW_TABLE_TYPE_ESW_EGRESS_ACL = 0x2, 7817 MLX5_FLOW_TABLE_TYPE_ESW_INGRESS_ACL = 0x3, 7818 MLX5_FLOW_TABLE_TYPE_FDB = 0X4, 7819 MLX5_FLOW_TABLE_TYPE_SNIFFER_RX = 0X5, 7820 MLX5_FLOW_TABLE_TYPE_SNIFFER_TX = 0X6, 7821 }; 7822 7823 struct mlx5_ifc_create_flow_table_out_bits { 7824 u8 status[0x8]; 7825 u8 icm_address_63_40[0x18]; 7826 7827 u8 syndrome[0x20]; 7828 7829 u8 icm_address_39_32[0x8]; 7830 u8 table_id[0x18]; 7831 7832 u8 icm_address_31_0[0x20]; 7833 }; 7834 7835 struct mlx5_ifc_create_flow_table_in_bits { 7836 u8 opcode[0x10]; 7837 u8 reserved_at_10[0x10]; 7838 7839 u8 reserved_at_20[0x10]; 7840 u8 op_mod[0x10]; 7841 7842 u8 other_vport[0x1]; 7843 u8 reserved_at_41[0xf]; 7844 u8 vport_number[0x10]; 7845 7846 u8 reserved_at_60[0x20]; 7847 7848 u8 table_type[0x8]; 7849 u8 reserved_at_88[0x18]; 7850 7851 u8 reserved_at_a0[0x20]; 7852 7853 struct mlx5_ifc_flow_table_context_bits flow_table_context; 7854 }; 7855 7856 struct mlx5_ifc_create_flow_group_out_bits { 7857 u8 status[0x8]; 7858 u8 reserved_at_8[0x18]; 7859 7860 u8 syndrome[0x20]; 7861 7862 u8 reserved_at_40[0x8]; 7863 u8 group_id[0x18]; 7864 7865 u8 reserved_at_60[0x20]; 7866 }; 7867 7868 enum { 7869 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 7870 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 7871 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 7872 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3, 7873 }; 7874 7875 struct mlx5_ifc_create_flow_group_in_bits { 7876 u8 opcode[0x10]; 7877 u8 reserved_at_10[0x10]; 7878 7879 u8 reserved_at_20[0x10]; 7880 u8 op_mod[0x10]; 7881 7882 u8 other_vport[0x1]; 7883 u8 reserved_at_41[0xf]; 7884 u8 vport_number[0x10]; 7885 7886 u8 reserved_at_60[0x20]; 7887 7888 u8 table_type[0x8]; 7889 u8 reserved_at_88[0x18]; 7890 7891 u8 reserved_at_a0[0x8]; 7892 u8 table_id[0x18]; 7893 7894 u8 source_eswitch_owner_vhca_id_valid[0x1]; 7895 7896 u8 reserved_at_c1[0x1f]; 7897 7898 u8 start_flow_index[0x20]; 7899 7900 u8 reserved_at_100[0x20]; 7901 7902 u8 end_flow_index[0x20]; 7903 7904 u8 reserved_at_140[0xa0]; 7905 7906 u8 reserved_at_1e0[0x18]; 7907 u8 match_criteria_enable[0x8]; 7908 7909 struct mlx5_ifc_fte_match_param_bits match_criteria; 7910 7911 u8 reserved_at_1200[0xe00]; 7912 }; 7913 7914 struct mlx5_ifc_create_eq_out_bits { 7915 u8 status[0x8]; 7916 u8 reserved_at_8[0x18]; 7917 7918 u8 syndrome[0x20]; 7919 7920 u8 reserved_at_40[0x18]; 7921 u8 eq_number[0x8]; 7922 7923 u8 reserved_at_60[0x20]; 7924 }; 7925 7926 struct mlx5_ifc_create_eq_in_bits { 7927 u8 opcode[0x10]; 7928 u8 uid[0x10]; 7929 7930 u8 reserved_at_20[0x10]; 7931 u8 op_mod[0x10]; 7932 7933 u8 reserved_at_40[0x40]; 7934 7935 struct mlx5_ifc_eqc_bits eq_context_entry; 7936 7937 u8 reserved_at_280[0x40]; 7938 7939 u8 event_bitmask[4][0x40]; 7940 7941 u8 reserved_at_3c0[0x4c0]; 7942 7943 u8 pas[][0x40]; 7944 }; 7945 7946 struct mlx5_ifc_create_dct_out_bits { 7947 u8 status[0x8]; 7948 u8 reserved_at_8[0x18]; 7949 7950 u8 syndrome[0x20]; 7951 7952 u8 reserved_at_40[0x8]; 7953 u8 dctn[0x18]; 7954 7955 u8 ece[0x20]; 7956 }; 7957 7958 struct mlx5_ifc_create_dct_in_bits { 7959 u8 opcode[0x10]; 7960 u8 uid[0x10]; 7961 7962 u8 reserved_at_20[0x10]; 7963 u8 op_mod[0x10]; 7964 7965 u8 reserved_at_40[0x40]; 7966 7967 struct mlx5_ifc_dctc_bits dct_context_entry; 7968 7969 u8 reserved_at_280[0x180]; 7970 }; 7971 7972 struct mlx5_ifc_create_cq_out_bits { 7973 u8 status[0x8]; 7974 u8 reserved_at_8[0x18]; 7975 7976 u8 syndrome[0x20]; 7977 7978 u8 reserved_at_40[0x8]; 7979 u8 cqn[0x18]; 7980 7981 u8 reserved_at_60[0x20]; 7982 }; 7983 7984 struct mlx5_ifc_create_cq_in_bits { 7985 u8 opcode[0x10]; 7986 u8 uid[0x10]; 7987 7988 u8 reserved_at_20[0x10]; 7989 u8 op_mod[0x10]; 7990 7991 u8 reserved_at_40[0x40]; 7992 7993 struct mlx5_ifc_cqc_bits cq_context; 7994 7995 u8 reserved_at_280[0x60]; 7996 7997 u8 cq_umem_valid[0x1]; 7998 u8 reserved_at_2e1[0x59f]; 7999 8000 u8 pas[][0x40]; 8001 }; 8002 8003 struct mlx5_ifc_config_int_moderation_out_bits { 8004 u8 status[0x8]; 8005 u8 reserved_at_8[0x18]; 8006 8007 u8 syndrome[0x20]; 8008 8009 u8 reserved_at_40[0x4]; 8010 u8 min_delay[0xc]; 8011 u8 int_vector[0x10]; 8012 8013 u8 reserved_at_60[0x20]; 8014 }; 8015 8016 enum { 8017 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0, 8018 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1, 8019 }; 8020 8021 struct mlx5_ifc_config_int_moderation_in_bits { 8022 u8 opcode[0x10]; 8023 u8 reserved_at_10[0x10]; 8024 8025 u8 reserved_at_20[0x10]; 8026 u8 op_mod[0x10]; 8027 8028 u8 reserved_at_40[0x4]; 8029 u8 min_delay[0xc]; 8030 u8 int_vector[0x10]; 8031 8032 u8 reserved_at_60[0x20]; 8033 }; 8034 8035 struct mlx5_ifc_attach_to_mcg_out_bits { 8036 u8 status[0x8]; 8037 u8 reserved_at_8[0x18]; 8038 8039 u8 syndrome[0x20]; 8040 8041 u8 reserved_at_40[0x40]; 8042 }; 8043 8044 struct mlx5_ifc_attach_to_mcg_in_bits { 8045 u8 opcode[0x10]; 8046 u8 uid[0x10]; 8047 8048 u8 reserved_at_20[0x10]; 8049 u8 op_mod[0x10]; 8050 8051 u8 reserved_at_40[0x8]; 8052 u8 qpn[0x18]; 8053 8054 u8 reserved_at_60[0x20]; 8055 8056 u8 multicast_gid[16][0x8]; 8057 }; 8058 8059 struct mlx5_ifc_arm_xrq_out_bits { 8060 u8 status[0x8]; 8061 u8 reserved_at_8[0x18]; 8062 8063 u8 syndrome[0x20]; 8064 8065 u8 reserved_at_40[0x40]; 8066 }; 8067 8068 struct mlx5_ifc_arm_xrq_in_bits { 8069 u8 opcode[0x10]; 8070 u8 reserved_at_10[0x10]; 8071 8072 u8 reserved_at_20[0x10]; 8073 u8 op_mod[0x10]; 8074 8075 u8 reserved_at_40[0x8]; 8076 u8 xrqn[0x18]; 8077 8078 u8 reserved_at_60[0x10]; 8079 u8 lwm[0x10]; 8080 }; 8081 8082 struct mlx5_ifc_arm_xrc_srq_out_bits { 8083 u8 status[0x8]; 8084 u8 reserved_at_8[0x18]; 8085 8086 u8 syndrome[0x20]; 8087 8088 u8 reserved_at_40[0x40]; 8089 }; 8090 8091 enum { 8092 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1, 8093 }; 8094 8095 struct mlx5_ifc_arm_xrc_srq_in_bits { 8096 u8 opcode[0x10]; 8097 u8 uid[0x10]; 8098 8099 u8 reserved_at_20[0x10]; 8100 u8 op_mod[0x10]; 8101 8102 u8 reserved_at_40[0x8]; 8103 u8 xrc_srqn[0x18]; 8104 8105 u8 reserved_at_60[0x10]; 8106 u8 lwm[0x10]; 8107 }; 8108 8109 struct mlx5_ifc_arm_rq_out_bits { 8110 u8 status[0x8]; 8111 u8 reserved_at_8[0x18]; 8112 8113 u8 syndrome[0x20]; 8114 8115 u8 reserved_at_40[0x40]; 8116 }; 8117 8118 enum { 8119 MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1, 8120 MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2, 8121 }; 8122 8123 struct mlx5_ifc_arm_rq_in_bits { 8124 u8 opcode[0x10]; 8125 u8 uid[0x10]; 8126 8127 u8 reserved_at_20[0x10]; 8128 u8 op_mod[0x10]; 8129 8130 u8 reserved_at_40[0x8]; 8131 u8 srq_number[0x18]; 8132 8133 u8 reserved_at_60[0x10]; 8134 u8 lwm[0x10]; 8135 }; 8136 8137 struct mlx5_ifc_arm_dct_out_bits { 8138 u8 status[0x8]; 8139 u8 reserved_at_8[0x18]; 8140 8141 u8 syndrome[0x20]; 8142 8143 u8 reserved_at_40[0x40]; 8144 }; 8145 8146 struct mlx5_ifc_arm_dct_in_bits { 8147 u8 opcode[0x10]; 8148 u8 reserved_at_10[0x10]; 8149 8150 u8 reserved_at_20[0x10]; 8151 u8 op_mod[0x10]; 8152 8153 u8 reserved_at_40[0x8]; 8154 u8 dct_number[0x18]; 8155 8156 u8 reserved_at_60[0x20]; 8157 }; 8158 8159 struct mlx5_ifc_alloc_xrcd_out_bits { 8160 u8 status[0x8]; 8161 u8 reserved_at_8[0x18]; 8162 8163 u8 syndrome[0x20]; 8164 8165 u8 reserved_at_40[0x8]; 8166 u8 xrcd[0x18]; 8167 8168 u8 reserved_at_60[0x20]; 8169 }; 8170 8171 struct mlx5_ifc_alloc_xrcd_in_bits { 8172 u8 opcode[0x10]; 8173 u8 uid[0x10]; 8174 8175 u8 reserved_at_20[0x10]; 8176 u8 op_mod[0x10]; 8177 8178 u8 reserved_at_40[0x40]; 8179 }; 8180 8181 struct mlx5_ifc_alloc_uar_out_bits { 8182 u8 status[0x8]; 8183 u8 reserved_at_8[0x18]; 8184 8185 u8 syndrome[0x20]; 8186 8187 u8 reserved_at_40[0x8]; 8188 u8 uar[0x18]; 8189 8190 u8 reserved_at_60[0x20]; 8191 }; 8192 8193 struct mlx5_ifc_alloc_uar_in_bits { 8194 u8 opcode[0x10]; 8195 u8 reserved_at_10[0x10]; 8196 8197 u8 reserved_at_20[0x10]; 8198 u8 op_mod[0x10]; 8199 8200 u8 reserved_at_40[0x40]; 8201 }; 8202 8203 struct mlx5_ifc_alloc_transport_domain_out_bits { 8204 u8 status[0x8]; 8205 u8 reserved_at_8[0x18]; 8206 8207 u8 syndrome[0x20]; 8208 8209 u8 reserved_at_40[0x8]; 8210 u8 transport_domain[0x18]; 8211 8212 u8 reserved_at_60[0x20]; 8213 }; 8214 8215 struct mlx5_ifc_alloc_transport_domain_in_bits { 8216 u8 opcode[0x10]; 8217 u8 uid[0x10]; 8218 8219 u8 reserved_at_20[0x10]; 8220 u8 op_mod[0x10]; 8221 8222 u8 reserved_at_40[0x40]; 8223 }; 8224 8225 struct mlx5_ifc_alloc_q_counter_out_bits { 8226 u8 status[0x8]; 8227 u8 reserved_at_8[0x18]; 8228 8229 u8 syndrome[0x20]; 8230 8231 u8 reserved_at_40[0x18]; 8232 u8 counter_set_id[0x8]; 8233 8234 u8 reserved_at_60[0x20]; 8235 }; 8236 8237 struct mlx5_ifc_alloc_q_counter_in_bits { 8238 u8 opcode[0x10]; 8239 u8 uid[0x10]; 8240 8241 u8 reserved_at_20[0x10]; 8242 u8 op_mod[0x10]; 8243 8244 u8 reserved_at_40[0x40]; 8245 }; 8246 8247 struct mlx5_ifc_alloc_pd_out_bits { 8248 u8 status[0x8]; 8249 u8 reserved_at_8[0x18]; 8250 8251 u8 syndrome[0x20]; 8252 8253 u8 reserved_at_40[0x8]; 8254 u8 pd[0x18]; 8255 8256 u8 reserved_at_60[0x20]; 8257 }; 8258 8259 struct mlx5_ifc_alloc_pd_in_bits { 8260 u8 opcode[0x10]; 8261 u8 uid[0x10]; 8262 8263 u8 reserved_at_20[0x10]; 8264 u8 op_mod[0x10]; 8265 8266 u8 reserved_at_40[0x40]; 8267 }; 8268 8269 struct mlx5_ifc_alloc_flow_counter_out_bits { 8270 u8 status[0x8]; 8271 u8 reserved_at_8[0x18]; 8272 8273 u8 syndrome[0x20]; 8274 8275 u8 flow_counter_id[0x20]; 8276 8277 u8 reserved_at_60[0x20]; 8278 }; 8279 8280 struct mlx5_ifc_alloc_flow_counter_in_bits { 8281 u8 opcode[0x10]; 8282 u8 reserved_at_10[0x10]; 8283 8284 u8 reserved_at_20[0x10]; 8285 u8 op_mod[0x10]; 8286 8287 u8 reserved_at_40[0x38]; 8288 u8 flow_counter_bulk[0x8]; 8289 }; 8290 8291 struct mlx5_ifc_add_vxlan_udp_dport_out_bits { 8292 u8 status[0x8]; 8293 u8 reserved_at_8[0x18]; 8294 8295 u8 syndrome[0x20]; 8296 8297 u8 reserved_at_40[0x40]; 8298 }; 8299 8300 struct mlx5_ifc_add_vxlan_udp_dport_in_bits { 8301 u8 opcode[0x10]; 8302 u8 reserved_at_10[0x10]; 8303 8304 u8 reserved_at_20[0x10]; 8305 u8 op_mod[0x10]; 8306 8307 u8 reserved_at_40[0x20]; 8308 8309 u8 reserved_at_60[0x10]; 8310 u8 vxlan_udp_port[0x10]; 8311 }; 8312 8313 struct mlx5_ifc_set_pp_rate_limit_out_bits { 8314 u8 status[0x8]; 8315 u8 reserved_at_8[0x18]; 8316 8317 u8 syndrome[0x20]; 8318 8319 u8 reserved_at_40[0x40]; 8320 }; 8321 8322 struct mlx5_ifc_set_pp_rate_limit_context_bits { 8323 u8 rate_limit[0x20]; 8324 8325 u8 burst_upper_bound[0x20]; 8326 8327 u8 reserved_at_40[0x10]; 8328 u8 typical_packet_size[0x10]; 8329 8330 u8 reserved_at_60[0x120]; 8331 }; 8332 8333 struct mlx5_ifc_set_pp_rate_limit_in_bits { 8334 u8 opcode[0x10]; 8335 u8 uid[0x10]; 8336 8337 u8 reserved_at_20[0x10]; 8338 u8 op_mod[0x10]; 8339 8340 u8 reserved_at_40[0x10]; 8341 u8 rate_limit_index[0x10]; 8342 8343 u8 reserved_at_60[0x20]; 8344 8345 struct mlx5_ifc_set_pp_rate_limit_context_bits ctx; 8346 }; 8347 8348 struct mlx5_ifc_access_register_out_bits { 8349 u8 status[0x8]; 8350 u8 reserved_at_8[0x18]; 8351 8352 u8 syndrome[0x20]; 8353 8354 u8 reserved_at_40[0x40]; 8355 8356 u8 register_data[][0x20]; 8357 }; 8358 8359 enum { 8360 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0, 8361 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1, 8362 }; 8363 8364 struct mlx5_ifc_access_register_in_bits { 8365 u8 opcode[0x10]; 8366 u8 reserved_at_10[0x10]; 8367 8368 u8 reserved_at_20[0x10]; 8369 u8 op_mod[0x10]; 8370 8371 u8 reserved_at_40[0x10]; 8372 u8 register_id[0x10]; 8373 8374 u8 argument[0x20]; 8375 8376 u8 register_data[][0x20]; 8377 }; 8378 8379 struct mlx5_ifc_sltp_reg_bits { 8380 u8 status[0x4]; 8381 u8 version[0x4]; 8382 u8 local_port[0x8]; 8383 u8 pnat[0x2]; 8384 u8 reserved_at_12[0x2]; 8385 u8 lane[0x4]; 8386 u8 reserved_at_18[0x8]; 8387 8388 u8 reserved_at_20[0x20]; 8389 8390 u8 reserved_at_40[0x7]; 8391 u8 polarity[0x1]; 8392 u8 ob_tap0[0x8]; 8393 u8 ob_tap1[0x8]; 8394 u8 ob_tap2[0x8]; 8395 8396 u8 reserved_at_60[0xc]; 8397 u8 ob_preemp_mode[0x4]; 8398 u8 ob_reg[0x8]; 8399 u8 ob_bias[0x8]; 8400 8401 u8 reserved_at_80[0x20]; 8402 }; 8403 8404 struct mlx5_ifc_slrg_reg_bits { 8405 u8 status[0x4]; 8406 u8 version[0x4]; 8407 u8 local_port[0x8]; 8408 u8 pnat[0x2]; 8409 u8 reserved_at_12[0x2]; 8410 u8 lane[0x4]; 8411 u8 reserved_at_18[0x8]; 8412 8413 u8 time_to_link_up[0x10]; 8414 u8 reserved_at_30[0xc]; 8415 u8 grade_lane_speed[0x4]; 8416 8417 u8 grade_version[0x8]; 8418 u8 grade[0x18]; 8419 8420 u8 reserved_at_60[0x4]; 8421 u8 height_grade_type[0x4]; 8422 u8 height_grade[0x18]; 8423 8424 u8 height_dz[0x10]; 8425 u8 height_dv[0x10]; 8426 8427 u8 reserved_at_a0[0x10]; 8428 u8 height_sigma[0x10]; 8429 8430 u8 reserved_at_c0[0x20]; 8431 8432 u8 reserved_at_e0[0x4]; 8433 u8 phase_grade_type[0x4]; 8434 u8 phase_grade[0x18]; 8435 8436 u8 reserved_at_100[0x8]; 8437 u8 phase_eo_pos[0x8]; 8438 u8 reserved_at_110[0x8]; 8439 u8 phase_eo_neg[0x8]; 8440 8441 u8 ffe_set_tested[0x10]; 8442 u8 test_errors_per_lane[0x10]; 8443 }; 8444 8445 struct mlx5_ifc_pvlc_reg_bits { 8446 u8 reserved_at_0[0x8]; 8447 u8 local_port[0x8]; 8448 u8 reserved_at_10[0x10]; 8449 8450 u8 reserved_at_20[0x1c]; 8451 u8 vl_hw_cap[0x4]; 8452 8453 u8 reserved_at_40[0x1c]; 8454 u8 vl_admin[0x4]; 8455 8456 u8 reserved_at_60[0x1c]; 8457 u8 vl_operational[0x4]; 8458 }; 8459 8460 struct mlx5_ifc_pude_reg_bits { 8461 u8 swid[0x8]; 8462 u8 local_port[0x8]; 8463 u8 reserved_at_10[0x4]; 8464 u8 admin_status[0x4]; 8465 u8 reserved_at_18[0x4]; 8466 u8 oper_status[0x4]; 8467 8468 u8 reserved_at_20[0x60]; 8469 }; 8470 8471 struct mlx5_ifc_ptys_reg_bits { 8472 u8 reserved_at_0[0x1]; 8473 u8 an_disable_admin[0x1]; 8474 u8 an_disable_cap[0x1]; 8475 u8 reserved_at_3[0x5]; 8476 u8 local_port[0x8]; 8477 u8 reserved_at_10[0xd]; 8478 u8 proto_mask[0x3]; 8479 8480 u8 an_status[0x4]; 8481 u8 reserved_at_24[0xc]; 8482 u8 data_rate_oper[0x10]; 8483 8484 u8 ext_eth_proto_capability[0x20]; 8485 8486 u8 eth_proto_capability[0x20]; 8487 8488 u8 ib_link_width_capability[0x10]; 8489 u8 ib_proto_capability[0x10]; 8490 8491 u8 ext_eth_proto_admin[0x20]; 8492 8493 u8 eth_proto_admin[0x20]; 8494 8495 u8 ib_link_width_admin[0x10]; 8496 u8 ib_proto_admin[0x10]; 8497 8498 u8 ext_eth_proto_oper[0x20]; 8499 8500 u8 eth_proto_oper[0x20]; 8501 8502 u8 ib_link_width_oper[0x10]; 8503 u8 ib_proto_oper[0x10]; 8504 8505 u8 reserved_at_160[0x1c]; 8506 u8 connector_type[0x4]; 8507 8508 u8 eth_proto_lp_advertise[0x20]; 8509 8510 u8 reserved_at_1a0[0x60]; 8511 }; 8512 8513 struct mlx5_ifc_mlcr_reg_bits { 8514 u8 reserved_at_0[0x8]; 8515 u8 local_port[0x8]; 8516 u8 reserved_at_10[0x20]; 8517 8518 u8 beacon_duration[0x10]; 8519 u8 reserved_at_40[0x10]; 8520 8521 u8 beacon_remain[0x10]; 8522 }; 8523 8524 struct mlx5_ifc_ptas_reg_bits { 8525 u8 reserved_at_0[0x20]; 8526 8527 u8 algorithm_options[0x10]; 8528 u8 reserved_at_30[0x4]; 8529 u8 repetitions_mode[0x4]; 8530 u8 num_of_repetitions[0x8]; 8531 8532 u8 grade_version[0x8]; 8533 u8 height_grade_type[0x4]; 8534 u8 phase_grade_type[0x4]; 8535 u8 height_grade_weight[0x8]; 8536 u8 phase_grade_weight[0x8]; 8537 8538 u8 gisim_measure_bits[0x10]; 8539 u8 adaptive_tap_measure_bits[0x10]; 8540 8541 u8 ber_bath_high_error_threshold[0x10]; 8542 u8 ber_bath_mid_error_threshold[0x10]; 8543 8544 u8 ber_bath_low_error_threshold[0x10]; 8545 u8 one_ratio_high_threshold[0x10]; 8546 8547 u8 one_ratio_high_mid_threshold[0x10]; 8548 u8 one_ratio_low_mid_threshold[0x10]; 8549 8550 u8 one_ratio_low_threshold[0x10]; 8551 u8 ndeo_error_threshold[0x10]; 8552 8553 u8 mixer_offset_step_size[0x10]; 8554 u8 reserved_at_110[0x8]; 8555 u8 mix90_phase_for_voltage_bath[0x8]; 8556 8557 u8 mixer_offset_start[0x10]; 8558 u8 mixer_offset_end[0x10]; 8559 8560 u8 reserved_at_140[0x15]; 8561 u8 ber_test_time[0xb]; 8562 }; 8563 8564 struct mlx5_ifc_pspa_reg_bits { 8565 u8 swid[0x8]; 8566 u8 local_port[0x8]; 8567 u8 sub_port[0x8]; 8568 u8 reserved_at_18[0x8]; 8569 8570 u8 reserved_at_20[0x20]; 8571 }; 8572 8573 struct mlx5_ifc_pqdr_reg_bits { 8574 u8 reserved_at_0[0x8]; 8575 u8 local_port[0x8]; 8576 u8 reserved_at_10[0x5]; 8577 u8 prio[0x3]; 8578 u8 reserved_at_18[0x6]; 8579 u8 mode[0x2]; 8580 8581 u8 reserved_at_20[0x20]; 8582 8583 u8 reserved_at_40[0x10]; 8584 u8 min_threshold[0x10]; 8585 8586 u8 reserved_at_60[0x10]; 8587 u8 max_threshold[0x10]; 8588 8589 u8 reserved_at_80[0x10]; 8590 u8 mark_probability_denominator[0x10]; 8591 8592 u8 reserved_at_a0[0x60]; 8593 }; 8594 8595 struct mlx5_ifc_ppsc_reg_bits { 8596 u8 reserved_at_0[0x8]; 8597 u8 local_port[0x8]; 8598 u8 reserved_at_10[0x10]; 8599 8600 u8 reserved_at_20[0x60]; 8601 8602 u8 reserved_at_80[0x1c]; 8603 u8 wrps_admin[0x4]; 8604 8605 u8 reserved_at_a0[0x1c]; 8606 u8 wrps_status[0x4]; 8607 8608 u8 reserved_at_c0[0x8]; 8609 u8 up_threshold[0x8]; 8610 u8 reserved_at_d0[0x8]; 8611 u8 down_threshold[0x8]; 8612 8613 u8 reserved_at_e0[0x20]; 8614 8615 u8 reserved_at_100[0x1c]; 8616 u8 srps_admin[0x4]; 8617 8618 u8 reserved_at_120[0x1c]; 8619 u8 srps_status[0x4]; 8620 8621 u8 reserved_at_140[0x40]; 8622 }; 8623 8624 struct mlx5_ifc_pplr_reg_bits { 8625 u8 reserved_at_0[0x8]; 8626 u8 local_port[0x8]; 8627 u8 reserved_at_10[0x10]; 8628 8629 u8 reserved_at_20[0x8]; 8630 u8 lb_cap[0x8]; 8631 u8 reserved_at_30[0x8]; 8632 u8 lb_en[0x8]; 8633 }; 8634 8635 struct mlx5_ifc_pplm_reg_bits { 8636 u8 reserved_at_0[0x8]; 8637 u8 local_port[0x8]; 8638 u8 reserved_at_10[0x10]; 8639 8640 u8 reserved_at_20[0x20]; 8641 8642 u8 port_profile_mode[0x8]; 8643 u8 static_port_profile[0x8]; 8644 u8 active_port_profile[0x8]; 8645 u8 reserved_at_58[0x8]; 8646 8647 u8 retransmission_active[0x8]; 8648 u8 fec_mode_active[0x18]; 8649 8650 u8 rs_fec_correction_bypass_cap[0x4]; 8651 u8 reserved_at_84[0x8]; 8652 u8 fec_override_cap_56g[0x4]; 8653 u8 fec_override_cap_100g[0x4]; 8654 u8 fec_override_cap_50g[0x4]; 8655 u8 fec_override_cap_25g[0x4]; 8656 u8 fec_override_cap_10g_40g[0x4]; 8657 8658 u8 rs_fec_correction_bypass_admin[0x4]; 8659 u8 reserved_at_a4[0x8]; 8660 u8 fec_override_admin_56g[0x4]; 8661 u8 fec_override_admin_100g[0x4]; 8662 u8 fec_override_admin_50g[0x4]; 8663 u8 fec_override_admin_25g[0x4]; 8664 u8 fec_override_admin_10g_40g[0x4]; 8665 8666 u8 fec_override_cap_400g_8x[0x10]; 8667 u8 fec_override_cap_200g_4x[0x10]; 8668 8669 u8 fec_override_cap_100g_2x[0x10]; 8670 u8 fec_override_cap_50g_1x[0x10]; 8671 8672 u8 fec_override_admin_400g_8x[0x10]; 8673 u8 fec_override_admin_200g_4x[0x10]; 8674 8675 u8 fec_override_admin_100g_2x[0x10]; 8676 u8 fec_override_admin_50g_1x[0x10]; 8677 }; 8678 8679 struct mlx5_ifc_ppcnt_reg_bits { 8680 u8 swid[0x8]; 8681 u8 local_port[0x8]; 8682 u8 pnat[0x2]; 8683 u8 reserved_at_12[0x8]; 8684 u8 grp[0x6]; 8685 8686 u8 clr[0x1]; 8687 u8 reserved_at_21[0x1c]; 8688 u8 prio_tc[0x3]; 8689 8690 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set; 8691 }; 8692 8693 struct mlx5_ifc_mpein_reg_bits { 8694 u8 reserved_at_0[0x2]; 8695 u8 depth[0x6]; 8696 u8 pcie_index[0x8]; 8697 u8 node[0x8]; 8698 u8 reserved_at_18[0x8]; 8699 8700 u8 capability_mask[0x20]; 8701 8702 u8 reserved_at_40[0x8]; 8703 u8 link_width_enabled[0x8]; 8704 u8 link_speed_enabled[0x10]; 8705 8706 u8 lane0_physical_position[0x8]; 8707 u8 link_width_active[0x8]; 8708 u8 link_speed_active[0x10]; 8709 8710 u8 num_of_pfs[0x10]; 8711 u8 num_of_vfs[0x10]; 8712 8713 u8 bdf0[0x10]; 8714 u8 reserved_at_b0[0x10]; 8715 8716 u8 max_read_request_size[0x4]; 8717 u8 max_payload_size[0x4]; 8718 u8 reserved_at_c8[0x5]; 8719 u8 pwr_status[0x3]; 8720 u8 port_type[0x4]; 8721 u8 reserved_at_d4[0xb]; 8722 u8 lane_reversal[0x1]; 8723 8724 u8 reserved_at_e0[0x14]; 8725 u8 pci_power[0xc]; 8726 8727 u8 reserved_at_100[0x20]; 8728 8729 u8 device_status[0x10]; 8730 u8 port_state[0x8]; 8731 u8 reserved_at_138[0x8]; 8732 8733 u8 reserved_at_140[0x10]; 8734 u8 receiver_detect_result[0x10]; 8735 8736 u8 reserved_at_160[0x20]; 8737 }; 8738 8739 struct mlx5_ifc_mpcnt_reg_bits { 8740 u8 reserved_at_0[0x8]; 8741 u8 pcie_index[0x8]; 8742 u8 reserved_at_10[0xa]; 8743 u8 grp[0x6]; 8744 8745 u8 clr[0x1]; 8746 u8 reserved_at_21[0x1f]; 8747 8748 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set; 8749 }; 8750 8751 struct mlx5_ifc_ppad_reg_bits { 8752 u8 reserved_at_0[0x3]; 8753 u8 single_mac[0x1]; 8754 u8 reserved_at_4[0x4]; 8755 u8 local_port[0x8]; 8756 u8 mac_47_32[0x10]; 8757 8758 u8 mac_31_0[0x20]; 8759 8760 u8 reserved_at_40[0x40]; 8761 }; 8762 8763 struct mlx5_ifc_pmtu_reg_bits { 8764 u8 reserved_at_0[0x8]; 8765 u8 local_port[0x8]; 8766 u8 reserved_at_10[0x10]; 8767 8768 u8 max_mtu[0x10]; 8769 u8 reserved_at_30[0x10]; 8770 8771 u8 admin_mtu[0x10]; 8772 u8 reserved_at_50[0x10]; 8773 8774 u8 oper_mtu[0x10]; 8775 u8 reserved_at_70[0x10]; 8776 }; 8777 8778 struct mlx5_ifc_pmpr_reg_bits { 8779 u8 reserved_at_0[0x8]; 8780 u8 module[0x8]; 8781 u8 reserved_at_10[0x10]; 8782 8783 u8 reserved_at_20[0x18]; 8784 u8 attenuation_5g[0x8]; 8785 8786 u8 reserved_at_40[0x18]; 8787 u8 attenuation_7g[0x8]; 8788 8789 u8 reserved_at_60[0x18]; 8790 u8 attenuation_12g[0x8]; 8791 }; 8792 8793 struct mlx5_ifc_pmpe_reg_bits { 8794 u8 reserved_at_0[0x8]; 8795 u8 module[0x8]; 8796 u8 reserved_at_10[0xc]; 8797 u8 module_status[0x4]; 8798 8799 u8 reserved_at_20[0x60]; 8800 }; 8801 8802 struct mlx5_ifc_pmpc_reg_bits { 8803 u8 module_state_updated[32][0x8]; 8804 }; 8805 8806 struct mlx5_ifc_pmlpn_reg_bits { 8807 u8 reserved_at_0[0x4]; 8808 u8 mlpn_status[0x4]; 8809 u8 local_port[0x8]; 8810 u8 reserved_at_10[0x10]; 8811 8812 u8 e[0x1]; 8813 u8 reserved_at_21[0x1f]; 8814 }; 8815 8816 struct mlx5_ifc_pmlp_reg_bits { 8817 u8 rxtx[0x1]; 8818 u8 reserved_at_1[0x7]; 8819 u8 local_port[0x8]; 8820 u8 reserved_at_10[0x8]; 8821 u8 width[0x8]; 8822 8823 u8 lane0_module_mapping[0x20]; 8824 8825 u8 lane1_module_mapping[0x20]; 8826 8827 u8 lane2_module_mapping[0x20]; 8828 8829 u8 lane3_module_mapping[0x20]; 8830 8831 u8 reserved_at_a0[0x160]; 8832 }; 8833 8834 struct mlx5_ifc_pmaos_reg_bits { 8835 u8 reserved_at_0[0x8]; 8836 u8 module[0x8]; 8837 u8 reserved_at_10[0x4]; 8838 u8 admin_status[0x4]; 8839 u8 reserved_at_18[0x4]; 8840 u8 oper_status[0x4]; 8841 8842 u8 ase[0x1]; 8843 u8 ee[0x1]; 8844 u8 reserved_at_22[0x1c]; 8845 u8 e[0x2]; 8846 8847 u8 reserved_at_40[0x40]; 8848 }; 8849 8850 struct mlx5_ifc_plpc_reg_bits { 8851 u8 reserved_at_0[0x4]; 8852 u8 profile_id[0xc]; 8853 u8 reserved_at_10[0x4]; 8854 u8 proto_mask[0x4]; 8855 u8 reserved_at_18[0x8]; 8856 8857 u8 reserved_at_20[0x10]; 8858 u8 lane_speed[0x10]; 8859 8860 u8 reserved_at_40[0x17]; 8861 u8 lpbf[0x1]; 8862 u8 fec_mode_policy[0x8]; 8863 8864 u8 retransmission_capability[0x8]; 8865 u8 fec_mode_capability[0x18]; 8866 8867 u8 retransmission_support_admin[0x8]; 8868 u8 fec_mode_support_admin[0x18]; 8869 8870 u8 retransmission_request_admin[0x8]; 8871 u8 fec_mode_request_admin[0x18]; 8872 8873 u8 reserved_at_c0[0x80]; 8874 }; 8875 8876 struct mlx5_ifc_plib_reg_bits { 8877 u8 reserved_at_0[0x8]; 8878 u8 local_port[0x8]; 8879 u8 reserved_at_10[0x8]; 8880 u8 ib_port[0x8]; 8881 8882 u8 reserved_at_20[0x60]; 8883 }; 8884 8885 struct mlx5_ifc_plbf_reg_bits { 8886 u8 reserved_at_0[0x8]; 8887 u8 local_port[0x8]; 8888 u8 reserved_at_10[0xd]; 8889 u8 lbf_mode[0x3]; 8890 8891 u8 reserved_at_20[0x20]; 8892 }; 8893 8894 struct mlx5_ifc_pipg_reg_bits { 8895 u8 reserved_at_0[0x8]; 8896 u8 local_port[0x8]; 8897 u8 reserved_at_10[0x10]; 8898 8899 u8 dic[0x1]; 8900 u8 reserved_at_21[0x19]; 8901 u8 ipg[0x4]; 8902 u8 reserved_at_3e[0x2]; 8903 }; 8904 8905 struct mlx5_ifc_pifr_reg_bits { 8906 u8 reserved_at_0[0x8]; 8907 u8 local_port[0x8]; 8908 u8 reserved_at_10[0x10]; 8909 8910 u8 reserved_at_20[0xe0]; 8911 8912 u8 port_filter[8][0x20]; 8913 8914 u8 port_filter_update_en[8][0x20]; 8915 }; 8916 8917 struct mlx5_ifc_pfcc_reg_bits { 8918 u8 reserved_at_0[0x8]; 8919 u8 local_port[0x8]; 8920 u8 reserved_at_10[0xb]; 8921 u8 ppan_mask_n[0x1]; 8922 u8 minor_stall_mask[0x1]; 8923 u8 critical_stall_mask[0x1]; 8924 u8 reserved_at_1e[0x2]; 8925 8926 u8 ppan[0x4]; 8927 u8 reserved_at_24[0x4]; 8928 u8 prio_mask_tx[0x8]; 8929 u8 reserved_at_30[0x8]; 8930 u8 prio_mask_rx[0x8]; 8931 8932 u8 pptx[0x1]; 8933 u8 aptx[0x1]; 8934 u8 pptx_mask_n[0x1]; 8935 u8 reserved_at_43[0x5]; 8936 u8 pfctx[0x8]; 8937 u8 reserved_at_50[0x10]; 8938 8939 u8 pprx[0x1]; 8940 u8 aprx[0x1]; 8941 u8 pprx_mask_n[0x1]; 8942 u8 reserved_at_63[0x5]; 8943 u8 pfcrx[0x8]; 8944 u8 reserved_at_70[0x10]; 8945 8946 u8 device_stall_minor_watermark[0x10]; 8947 u8 device_stall_critical_watermark[0x10]; 8948 8949 u8 reserved_at_a0[0x60]; 8950 }; 8951 8952 struct mlx5_ifc_pelc_reg_bits { 8953 u8 op[0x4]; 8954 u8 reserved_at_4[0x4]; 8955 u8 local_port[0x8]; 8956 u8 reserved_at_10[0x10]; 8957 8958 u8 op_admin[0x8]; 8959 u8 op_capability[0x8]; 8960 u8 op_request[0x8]; 8961 u8 op_active[0x8]; 8962 8963 u8 admin[0x40]; 8964 8965 u8 capability[0x40]; 8966 8967 u8 request[0x40]; 8968 8969 u8 active[0x40]; 8970 8971 u8 reserved_at_140[0x80]; 8972 }; 8973 8974 struct mlx5_ifc_peir_reg_bits { 8975 u8 reserved_at_0[0x8]; 8976 u8 local_port[0x8]; 8977 u8 reserved_at_10[0x10]; 8978 8979 u8 reserved_at_20[0xc]; 8980 u8 error_count[0x4]; 8981 u8 reserved_at_30[0x10]; 8982 8983 u8 reserved_at_40[0xc]; 8984 u8 lane[0x4]; 8985 u8 reserved_at_50[0x8]; 8986 u8 error_type[0x8]; 8987 }; 8988 8989 struct mlx5_ifc_mpegc_reg_bits { 8990 u8 reserved_at_0[0x30]; 8991 u8 field_select[0x10]; 8992 8993 u8 tx_overflow_sense[0x1]; 8994 u8 mark_cqe[0x1]; 8995 u8 mark_cnp[0x1]; 8996 u8 reserved_at_43[0x1b]; 8997 u8 tx_lossy_overflow_oper[0x2]; 8998 8999 u8 reserved_at_60[0x100]; 9000 }; 9001 9002 struct mlx5_ifc_pcam_enhanced_features_bits { 9003 u8 reserved_at_0[0x68]; 9004 u8 fec_50G_per_lane_in_pplm[0x1]; 9005 u8 reserved_at_69[0x4]; 9006 u8 rx_icrc_encapsulated_counter[0x1]; 9007 u8 reserved_at_6e[0x4]; 9008 u8 ptys_extended_ethernet[0x1]; 9009 u8 reserved_at_73[0x3]; 9010 u8 pfcc_mask[0x1]; 9011 u8 reserved_at_77[0x3]; 9012 u8 per_lane_error_counters[0x1]; 9013 u8 rx_buffer_fullness_counters[0x1]; 9014 u8 ptys_connector_type[0x1]; 9015 u8 reserved_at_7d[0x1]; 9016 u8 ppcnt_discard_group[0x1]; 9017 u8 ppcnt_statistical_group[0x1]; 9018 }; 9019 9020 struct mlx5_ifc_pcam_regs_5000_to_507f_bits { 9021 u8 port_access_reg_cap_mask_127_to_96[0x20]; 9022 u8 port_access_reg_cap_mask_95_to_64[0x20]; 9023 9024 u8 port_access_reg_cap_mask_63_to_36[0x1c]; 9025 u8 pplm[0x1]; 9026 u8 port_access_reg_cap_mask_34_to_32[0x3]; 9027 9028 u8 port_access_reg_cap_mask_31_to_13[0x13]; 9029 u8 pbmc[0x1]; 9030 u8 pptb[0x1]; 9031 u8 port_access_reg_cap_mask_10_to_09[0x2]; 9032 u8 ppcnt[0x1]; 9033 u8 port_access_reg_cap_mask_07_to_00[0x8]; 9034 }; 9035 9036 struct mlx5_ifc_pcam_reg_bits { 9037 u8 reserved_at_0[0x8]; 9038 u8 feature_group[0x8]; 9039 u8 reserved_at_10[0x8]; 9040 u8 access_reg_group[0x8]; 9041 9042 u8 reserved_at_20[0x20]; 9043 9044 union { 9045 struct mlx5_ifc_pcam_regs_5000_to_507f_bits regs_5000_to_507f; 9046 u8 reserved_at_0[0x80]; 9047 } port_access_reg_cap_mask; 9048 9049 u8 reserved_at_c0[0x80]; 9050 9051 union { 9052 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features; 9053 u8 reserved_at_0[0x80]; 9054 } feature_cap_mask; 9055 9056 u8 reserved_at_1c0[0xc0]; 9057 }; 9058 9059 struct mlx5_ifc_mcam_enhanced_features_bits { 9060 u8 reserved_at_0[0x6e]; 9061 u8 pci_status_and_power[0x1]; 9062 u8 reserved_at_6f[0x5]; 9063 u8 mark_tx_action_cnp[0x1]; 9064 u8 mark_tx_action_cqe[0x1]; 9065 u8 dynamic_tx_overflow[0x1]; 9066 u8 reserved_at_77[0x4]; 9067 u8 pcie_outbound_stalled[0x1]; 9068 u8 tx_overflow_buffer_pkt[0x1]; 9069 u8 mtpps_enh_out_per_adj[0x1]; 9070 u8 mtpps_fs[0x1]; 9071 u8 pcie_performance_group[0x1]; 9072 }; 9073 9074 struct mlx5_ifc_mcam_access_reg_bits { 9075 u8 reserved_at_0[0x1c]; 9076 u8 mcda[0x1]; 9077 u8 mcc[0x1]; 9078 u8 mcqi[0x1]; 9079 u8 mcqs[0x1]; 9080 9081 u8 regs_95_to_87[0x9]; 9082 u8 mpegc[0x1]; 9083 u8 regs_85_to_68[0x12]; 9084 u8 tracer_registers[0x4]; 9085 9086 u8 regs_63_to_32[0x20]; 9087 u8 regs_31_to_0[0x20]; 9088 }; 9089 9090 struct mlx5_ifc_mcam_access_reg_bits1 { 9091 u8 regs_127_to_96[0x20]; 9092 9093 u8 regs_95_to_64[0x20]; 9094 9095 u8 regs_63_to_32[0x20]; 9096 9097 u8 regs_31_to_0[0x20]; 9098 }; 9099 9100 struct mlx5_ifc_mcam_access_reg_bits2 { 9101 u8 regs_127_to_99[0x1d]; 9102 u8 mirc[0x1]; 9103 u8 regs_97_to_96[0x2]; 9104 9105 u8 regs_95_to_64[0x20]; 9106 9107 u8 regs_63_to_32[0x20]; 9108 9109 u8 regs_31_to_0[0x20]; 9110 }; 9111 9112 struct mlx5_ifc_mcam_reg_bits { 9113 u8 reserved_at_0[0x8]; 9114 u8 feature_group[0x8]; 9115 u8 reserved_at_10[0x8]; 9116 u8 access_reg_group[0x8]; 9117 9118 u8 reserved_at_20[0x20]; 9119 9120 union { 9121 struct mlx5_ifc_mcam_access_reg_bits access_regs; 9122 struct mlx5_ifc_mcam_access_reg_bits1 access_regs1; 9123 struct mlx5_ifc_mcam_access_reg_bits2 access_regs2; 9124 u8 reserved_at_0[0x80]; 9125 } mng_access_reg_cap_mask; 9126 9127 u8 reserved_at_c0[0x80]; 9128 9129 union { 9130 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features; 9131 u8 reserved_at_0[0x80]; 9132 } mng_feature_cap_mask; 9133 9134 u8 reserved_at_1c0[0x80]; 9135 }; 9136 9137 struct mlx5_ifc_qcam_access_reg_cap_mask { 9138 u8 qcam_access_reg_cap_mask_127_to_20[0x6C]; 9139 u8 qpdpm[0x1]; 9140 u8 qcam_access_reg_cap_mask_18_to_4[0x0F]; 9141 u8 qdpm[0x1]; 9142 u8 qpts[0x1]; 9143 u8 qcap[0x1]; 9144 u8 qcam_access_reg_cap_mask_0[0x1]; 9145 }; 9146 9147 struct mlx5_ifc_qcam_qos_feature_cap_mask { 9148 u8 qcam_qos_feature_cap_mask_127_to_1[0x7F]; 9149 u8 qpts_trust_both[0x1]; 9150 }; 9151 9152 struct mlx5_ifc_qcam_reg_bits { 9153 u8 reserved_at_0[0x8]; 9154 u8 feature_group[0x8]; 9155 u8 reserved_at_10[0x8]; 9156 u8 access_reg_group[0x8]; 9157 u8 reserved_at_20[0x20]; 9158 9159 union { 9160 struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap; 9161 u8 reserved_at_0[0x80]; 9162 } qos_access_reg_cap_mask; 9163 9164 u8 reserved_at_c0[0x80]; 9165 9166 union { 9167 struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap; 9168 u8 reserved_at_0[0x80]; 9169 } qos_feature_cap_mask; 9170 9171 u8 reserved_at_1c0[0x80]; 9172 }; 9173 9174 struct mlx5_ifc_core_dump_reg_bits { 9175 u8 reserved_at_0[0x18]; 9176 u8 core_dump_type[0x8]; 9177 9178 u8 reserved_at_20[0x30]; 9179 u8 vhca_id[0x10]; 9180 9181 u8 reserved_at_60[0x8]; 9182 u8 qpn[0x18]; 9183 u8 reserved_at_80[0x180]; 9184 }; 9185 9186 struct mlx5_ifc_pcap_reg_bits { 9187 u8 reserved_at_0[0x8]; 9188 u8 local_port[0x8]; 9189 u8 reserved_at_10[0x10]; 9190 9191 u8 port_capability_mask[4][0x20]; 9192 }; 9193 9194 struct mlx5_ifc_paos_reg_bits { 9195 u8 swid[0x8]; 9196 u8 local_port[0x8]; 9197 u8 reserved_at_10[0x4]; 9198 u8 admin_status[0x4]; 9199 u8 reserved_at_18[0x4]; 9200 u8 oper_status[0x4]; 9201 9202 u8 ase[0x1]; 9203 u8 ee[0x1]; 9204 u8 reserved_at_22[0x1c]; 9205 u8 e[0x2]; 9206 9207 u8 reserved_at_40[0x40]; 9208 }; 9209 9210 struct mlx5_ifc_pamp_reg_bits { 9211 u8 reserved_at_0[0x8]; 9212 u8 opamp_group[0x8]; 9213 u8 reserved_at_10[0xc]; 9214 u8 opamp_group_type[0x4]; 9215 9216 u8 start_index[0x10]; 9217 u8 reserved_at_30[0x4]; 9218 u8 num_of_indices[0xc]; 9219 9220 u8 index_data[18][0x10]; 9221 }; 9222 9223 struct mlx5_ifc_pcmr_reg_bits { 9224 u8 reserved_at_0[0x8]; 9225 u8 local_port[0x8]; 9226 u8 reserved_at_10[0x10]; 9227 u8 entropy_force_cap[0x1]; 9228 u8 entropy_calc_cap[0x1]; 9229 u8 entropy_gre_calc_cap[0x1]; 9230 u8 reserved_at_23[0x1b]; 9231 u8 fcs_cap[0x1]; 9232 u8 reserved_at_3f[0x1]; 9233 u8 entropy_force[0x1]; 9234 u8 entropy_calc[0x1]; 9235 u8 entropy_gre_calc[0x1]; 9236 u8 reserved_at_43[0x1b]; 9237 u8 fcs_chk[0x1]; 9238 u8 reserved_at_5f[0x1]; 9239 }; 9240 9241 struct mlx5_ifc_lane_2_module_mapping_bits { 9242 u8 reserved_at_0[0x6]; 9243 u8 rx_lane[0x2]; 9244 u8 reserved_at_8[0x6]; 9245 u8 tx_lane[0x2]; 9246 u8 reserved_at_10[0x8]; 9247 u8 module[0x8]; 9248 }; 9249 9250 struct mlx5_ifc_bufferx_reg_bits { 9251 u8 reserved_at_0[0x6]; 9252 u8 lossy[0x1]; 9253 u8 epsb[0x1]; 9254 u8 reserved_at_8[0xc]; 9255 u8 size[0xc]; 9256 9257 u8 xoff_threshold[0x10]; 9258 u8 xon_threshold[0x10]; 9259 }; 9260 9261 struct mlx5_ifc_set_node_in_bits { 9262 u8 node_description[64][0x8]; 9263 }; 9264 9265 struct mlx5_ifc_register_power_settings_bits { 9266 u8 reserved_at_0[0x18]; 9267 u8 power_settings_level[0x8]; 9268 9269 u8 reserved_at_20[0x60]; 9270 }; 9271 9272 struct mlx5_ifc_register_host_endianness_bits { 9273 u8 he[0x1]; 9274 u8 reserved_at_1[0x1f]; 9275 9276 u8 reserved_at_20[0x60]; 9277 }; 9278 9279 struct mlx5_ifc_umr_pointer_desc_argument_bits { 9280 u8 reserved_at_0[0x20]; 9281 9282 u8 mkey[0x20]; 9283 9284 u8 addressh_63_32[0x20]; 9285 9286 u8 addressl_31_0[0x20]; 9287 }; 9288 9289 struct mlx5_ifc_ud_adrs_vector_bits { 9290 u8 dc_key[0x40]; 9291 9292 u8 ext[0x1]; 9293 u8 reserved_at_41[0x7]; 9294 u8 destination_qp_dct[0x18]; 9295 9296 u8 static_rate[0x4]; 9297 u8 sl_eth_prio[0x4]; 9298 u8 fl[0x1]; 9299 u8 mlid[0x7]; 9300 u8 rlid_udp_sport[0x10]; 9301 9302 u8 reserved_at_80[0x20]; 9303 9304 u8 rmac_47_16[0x20]; 9305 9306 u8 rmac_15_0[0x10]; 9307 u8 tclass[0x8]; 9308 u8 hop_limit[0x8]; 9309 9310 u8 reserved_at_e0[0x1]; 9311 u8 grh[0x1]; 9312 u8 reserved_at_e2[0x2]; 9313 u8 src_addr_index[0x8]; 9314 u8 flow_label[0x14]; 9315 9316 u8 rgid_rip[16][0x8]; 9317 }; 9318 9319 struct mlx5_ifc_pages_req_event_bits { 9320 u8 reserved_at_0[0x10]; 9321 u8 function_id[0x10]; 9322 9323 u8 num_pages[0x20]; 9324 9325 u8 reserved_at_40[0xa0]; 9326 }; 9327 9328 struct mlx5_ifc_eqe_bits { 9329 u8 reserved_at_0[0x8]; 9330 u8 event_type[0x8]; 9331 u8 reserved_at_10[0x8]; 9332 u8 event_sub_type[0x8]; 9333 9334 u8 reserved_at_20[0xe0]; 9335 9336 union mlx5_ifc_event_auto_bits event_data; 9337 9338 u8 reserved_at_1e0[0x10]; 9339 u8 signature[0x8]; 9340 u8 reserved_at_1f8[0x7]; 9341 u8 owner[0x1]; 9342 }; 9343 9344 enum { 9345 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7, 9346 }; 9347 9348 struct mlx5_ifc_cmd_queue_entry_bits { 9349 u8 type[0x8]; 9350 u8 reserved_at_8[0x18]; 9351 9352 u8 input_length[0x20]; 9353 9354 u8 input_mailbox_pointer_63_32[0x20]; 9355 9356 u8 input_mailbox_pointer_31_9[0x17]; 9357 u8 reserved_at_77[0x9]; 9358 9359 u8 command_input_inline_data[16][0x8]; 9360 9361 u8 command_output_inline_data[16][0x8]; 9362 9363 u8 output_mailbox_pointer_63_32[0x20]; 9364 9365 u8 output_mailbox_pointer_31_9[0x17]; 9366 u8 reserved_at_1b7[0x9]; 9367 9368 u8 output_length[0x20]; 9369 9370 u8 token[0x8]; 9371 u8 signature[0x8]; 9372 u8 reserved_at_1f0[0x8]; 9373 u8 status[0x7]; 9374 u8 ownership[0x1]; 9375 }; 9376 9377 struct mlx5_ifc_cmd_out_bits { 9378 u8 status[0x8]; 9379 u8 reserved_at_8[0x18]; 9380 9381 u8 syndrome[0x20]; 9382 9383 u8 command_output[0x20]; 9384 }; 9385 9386 struct mlx5_ifc_cmd_in_bits { 9387 u8 opcode[0x10]; 9388 u8 reserved_at_10[0x10]; 9389 9390 u8 reserved_at_20[0x10]; 9391 u8 op_mod[0x10]; 9392 9393 u8 command[][0x20]; 9394 }; 9395 9396 struct mlx5_ifc_cmd_if_box_bits { 9397 u8 mailbox_data[512][0x8]; 9398 9399 u8 reserved_at_1000[0x180]; 9400 9401 u8 next_pointer_63_32[0x20]; 9402 9403 u8 next_pointer_31_10[0x16]; 9404 u8 reserved_at_11b6[0xa]; 9405 9406 u8 block_number[0x20]; 9407 9408 u8 reserved_at_11e0[0x8]; 9409 u8 token[0x8]; 9410 u8 ctrl_signature[0x8]; 9411 u8 signature[0x8]; 9412 }; 9413 9414 struct mlx5_ifc_mtt_bits { 9415 u8 ptag_63_32[0x20]; 9416 9417 u8 ptag_31_8[0x18]; 9418 u8 reserved_at_38[0x6]; 9419 u8 wr_en[0x1]; 9420 u8 rd_en[0x1]; 9421 }; 9422 9423 struct mlx5_ifc_query_wol_rol_out_bits { 9424 u8 status[0x8]; 9425 u8 reserved_at_8[0x18]; 9426 9427 u8 syndrome[0x20]; 9428 9429 u8 reserved_at_40[0x10]; 9430 u8 rol_mode[0x8]; 9431 u8 wol_mode[0x8]; 9432 9433 u8 reserved_at_60[0x20]; 9434 }; 9435 9436 struct mlx5_ifc_query_wol_rol_in_bits { 9437 u8 opcode[0x10]; 9438 u8 reserved_at_10[0x10]; 9439 9440 u8 reserved_at_20[0x10]; 9441 u8 op_mod[0x10]; 9442 9443 u8 reserved_at_40[0x40]; 9444 }; 9445 9446 struct mlx5_ifc_set_wol_rol_out_bits { 9447 u8 status[0x8]; 9448 u8 reserved_at_8[0x18]; 9449 9450 u8 syndrome[0x20]; 9451 9452 u8 reserved_at_40[0x40]; 9453 }; 9454 9455 struct mlx5_ifc_set_wol_rol_in_bits { 9456 u8 opcode[0x10]; 9457 u8 reserved_at_10[0x10]; 9458 9459 u8 reserved_at_20[0x10]; 9460 u8 op_mod[0x10]; 9461 9462 u8 rol_mode_valid[0x1]; 9463 u8 wol_mode_valid[0x1]; 9464 u8 reserved_at_42[0xe]; 9465 u8 rol_mode[0x8]; 9466 u8 wol_mode[0x8]; 9467 9468 u8 reserved_at_60[0x20]; 9469 }; 9470 9471 enum { 9472 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0, 9473 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1, 9474 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2, 9475 }; 9476 9477 enum { 9478 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0, 9479 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1, 9480 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2, 9481 }; 9482 9483 enum { 9484 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR = 0x1, 9485 MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC = 0x7, 9486 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR = 0x8, 9487 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR = 0x9, 9488 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR = 0xa, 9489 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR = 0xb, 9490 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN = 0xc, 9491 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR = 0xd, 9492 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV = 0xe, 9493 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR = 0xf, 9494 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR = 0x10, 9495 }; 9496 9497 struct mlx5_ifc_initial_seg_bits { 9498 u8 fw_rev_minor[0x10]; 9499 u8 fw_rev_major[0x10]; 9500 9501 u8 cmd_interface_rev[0x10]; 9502 u8 fw_rev_subminor[0x10]; 9503 9504 u8 reserved_at_40[0x40]; 9505 9506 u8 cmdq_phy_addr_63_32[0x20]; 9507 9508 u8 cmdq_phy_addr_31_12[0x14]; 9509 u8 reserved_at_b4[0x2]; 9510 u8 nic_interface[0x2]; 9511 u8 log_cmdq_size[0x4]; 9512 u8 log_cmdq_stride[0x4]; 9513 9514 u8 command_doorbell_vector[0x20]; 9515 9516 u8 reserved_at_e0[0xf00]; 9517 9518 u8 initializing[0x1]; 9519 u8 reserved_at_fe1[0x4]; 9520 u8 nic_interface_supported[0x3]; 9521 u8 embedded_cpu[0x1]; 9522 u8 reserved_at_fe9[0x17]; 9523 9524 struct mlx5_ifc_health_buffer_bits health_buffer; 9525 9526 u8 no_dram_nic_offset[0x20]; 9527 9528 u8 reserved_at_1220[0x6e40]; 9529 9530 u8 reserved_at_8060[0x1f]; 9531 u8 clear_int[0x1]; 9532 9533 u8 health_syndrome[0x8]; 9534 u8 health_counter[0x18]; 9535 9536 u8 reserved_at_80a0[0x17fc0]; 9537 }; 9538 9539 struct mlx5_ifc_mtpps_reg_bits { 9540 u8 reserved_at_0[0xc]; 9541 u8 cap_number_of_pps_pins[0x4]; 9542 u8 reserved_at_10[0x4]; 9543 u8 cap_max_num_of_pps_in_pins[0x4]; 9544 u8 reserved_at_18[0x4]; 9545 u8 cap_max_num_of_pps_out_pins[0x4]; 9546 9547 u8 reserved_at_20[0x24]; 9548 u8 cap_pin_3_mode[0x4]; 9549 u8 reserved_at_48[0x4]; 9550 u8 cap_pin_2_mode[0x4]; 9551 u8 reserved_at_50[0x4]; 9552 u8 cap_pin_1_mode[0x4]; 9553 u8 reserved_at_58[0x4]; 9554 u8 cap_pin_0_mode[0x4]; 9555 9556 u8 reserved_at_60[0x4]; 9557 u8 cap_pin_7_mode[0x4]; 9558 u8 reserved_at_68[0x4]; 9559 u8 cap_pin_6_mode[0x4]; 9560 u8 reserved_at_70[0x4]; 9561 u8 cap_pin_5_mode[0x4]; 9562 u8 reserved_at_78[0x4]; 9563 u8 cap_pin_4_mode[0x4]; 9564 9565 u8 field_select[0x20]; 9566 u8 reserved_at_a0[0x60]; 9567 9568 u8 enable[0x1]; 9569 u8 reserved_at_101[0xb]; 9570 u8 pattern[0x4]; 9571 u8 reserved_at_110[0x4]; 9572 u8 pin_mode[0x4]; 9573 u8 pin[0x8]; 9574 9575 u8 reserved_at_120[0x20]; 9576 9577 u8 time_stamp[0x40]; 9578 9579 u8 out_pulse_duration[0x10]; 9580 u8 out_periodic_adjustment[0x10]; 9581 u8 enhanced_out_periodic_adjustment[0x20]; 9582 9583 u8 reserved_at_1c0[0x20]; 9584 }; 9585 9586 struct mlx5_ifc_mtppse_reg_bits { 9587 u8 reserved_at_0[0x18]; 9588 u8 pin[0x8]; 9589 u8 event_arm[0x1]; 9590 u8 reserved_at_21[0x1b]; 9591 u8 event_generation_mode[0x4]; 9592 u8 reserved_at_40[0x40]; 9593 }; 9594 9595 struct mlx5_ifc_mcqs_reg_bits { 9596 u8 last_index_flag[0x1]; 9597 u8 reserved_at_1[0x7]; 9598 u8 fw_device[0x8]; 9599 u8 component_index[0x10]; 9600 9601 u8 reserved_at_20[0x10]; 9602 u8 identifier[0x10]; 9603 9604 u8 reserved_at_40[0x17]; 9605 u8 component_status[0x5]; 9606 u8 component_update_state[0x4]; 9607 9608 u8 last_update_state_changer_type[0x4]; 9609 u8 last_update_state_changer_host_id[0x4]; 9610 u8 reserved_at_68[0x18]; 9611 }; 9612 9613 struct mlx5_ifc_mcqi_cap_bits { 9614 u8 supported_info_bitmask[0x20]; 9615 9616 u8 component_size[0x20]; 9617 9618 u8 max_component_size[0x20]; 9619 9620 u8 log_mcda_word_size[0x4]; 9621 u8 reserved_at_64[0xc]; 9622 u8 mcda_max_write_size[0x10]; 9623 9624 u8 rd_en[0x1]; 9625 u8 reserved_at_81[0x1]; 9626 u8 match_chip_id[0x1]; 9627 u8 match_psid[0x1]; 9628 u8 check_user_timestamp[0x1]; 9629 u8 match_base_guid_mac[0x1]; 9630 u8 reserved_at_86[0x1a]; 9631 }; 9632 9633 struct mlx5_ifc_mcqi_version_bits { 9634 u8 reserved_at_0[0x2]; 9635 u8 build_time_valid[0x1]; 9636 u8 user_defined_time_valid[0x1]; 9637 u8 reserved_at_4[0x14]; 9638 u8 version_string_length[0x8]; 9639 9640 u8 version[0x20]; 9641 9642 u8 build_time[0x40]; 9643 9644 u8 user_defined_time[0x40]; 9645 9646 u8 build_tool_version[0x20]; 9647 9648 u8 reserved_at_e0[0x20]; 9649 9650 u8 version_string[92][0x8]; 9651 }; 9652 9653 struct mlx5_ifc_mcqi_activation_method_bits { 9654 u8 pending_server_ac_power_cycle[0x1]; 9655 u8 pending_server_dc_power_cycle[0x1]; 9656 u8 pending_server_reboot[0x1]; 9657 u8 pending_fw_reset[0x1]; 9658 u8 auto_activate[0x1]; 9659 u8 all_hosts_sync[0x1]; 9660 u8 device_hw_reset[0x1]; 9661 u8 reserved_at_7[0x19]; 9662 }; 9663 9664 union mlx5_ifc_mcqi_reg_data_bits { 9665 struct mlx5_ifc_mcqi_cap_bits mcqi_caps; 9666 struct mlx5_ifc_mcqi_version_bits mcqi_version; 9667 struct mlx5_ifc_mcqi_activation_method_bits mcqi_activation_mathod; 9668 }; 9669 9670 struct mlx5_ifc_mcqi_reg_bits { 9671 u8 read_pending_component[0x1]; 9672 u8 reserved_at_1[0xf]; 9673 u8 component_index[0x10]; 9674 9675 u8 reserved_at_20[0x20]; 9676 9677 u8 reserved_at_40[0x1b]; 9678 u8 info_type[0x5]; 9679 9680 u8 info_size[0x20]; 9681 9682 u8 offset[0x20]; 9683 9684 u8 reserved_at_a0[0x10]; 9685 u8 data_size[0x10]; 9686 9687 union mlx5_ifc_mcqi_reg_data_bits data[]; 9688 }; 9689 9690 struct mlx5_ifc_mcc_reg_bits { 9691 u8 reserved_at_0[0x4]; 9692 u8 time_elapsed_since_last_cmd[0xc]; 9693 u8 reserved_at_10[0x8]; 9694 u8 instruction[0x8]; 9695 9696 u8 reserved_at_20[0x10]; 9697 u8 component_index[0x10]; 9698 9699 u8 reserved_at_40[0x8]; 9700 u8 update_handle[0x18]; 9701 9702 u8 handle_owner_type[0x4]; 9703 u8 handle_owner_host_id[0x4]; 9704 u8 reserved_at_68[0x1]; 9705 u8 control_progress[0x7]; 9706 u8 error_code[0x8]; 9707 u8 reserved_at_78[0x4]; 9708 u8 control_state[0x4]; 9709 9710 u8 component_size[0x20]; 9711 9712 u8 reserved_at_a0[0x60]; 9713 }; 9714 9715 struct mlx5_ifc_mcda_reg_bits { 9716 u8 reserved_at_0[0x8]; 9717 u8 update_handle[0x18]; 9718 9719 u8 offset[0x20]; 9720 9721 u8 reserved_at_40[0x10]; 9722 u8 size[0x10]; 9723 9724 u8 reserved_at_60[0x20]; 9725 9726 u8 data[0][0x20]; 9727 }; 9728 9729 enum { 9730 MLX5_MFRL_REG_RESET_TYPE_FULL_CHIP = BIT(0), 9731 MLX5_MFRL_REG_RESET_TYPE_NET_PORT_ALIVE = BIT(1), 9732 }; 9733 9734 enum { 9735 MLX5_MFRL_REG_RESET_LEVEL0 = BIT(0), 9736 MLX5_MFRL_REG_RESET_LEVEL3 = BIT(3), 9737 MLX5_MFRL_REG_RESET_LEVEL6 = BIT(6), 9738 }; 9739 9740 struct mlx5_ifc_mfrl_reg_bits { 9741 u8 reserved_at_0[0x20]; 9742 9743 u8 reserved_at_20[0x2]; 9744 u8 pci_sync_for_fw_update_start[0x1]; 9745 u8 pci_sync_for_fw_update_resp[0x2]; 9746 u8 rst_type_sel[0x3]; 9747 u8 reserved_at_28[0x8]; 9748 u8 reset_type[0x8]; 9749 u8 reset_level[0x8]; 9750 }; 9751 9752 struct mlx5_ifc_mirc_reg_bits { 9753 u8 reserved_at_0[0x18]; 9754 u8 status_code[0x8]; 9755 9756 u8 reserved_at_20[0x20]; 9757 }; 9758 9759 union mlx5_ifc_ports_control_registers_document_bits { 9760 struct mlx5_ifc_bufferx_reg_bits bufferx_reg; 9761 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 9762 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 9763 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 9764 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 9765 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 9766 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 9767 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout; 9768 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout; 9769 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping; 9770 struct mlx5_ifc_pamp_reg_bits pamp_reg; 9771 struct mlx5_ifc_paos_reg_bits paos_reg; 9772 struct mlx5_ifc_pcap_reg_bits pcap_reg; 9773 struct mlx5_ifc_peir_reg_bits peir_reg; 9774 struct mlx5_ifc_pelc_reg_bits pelc_reg; 9775 struct mlx5_ifc_pfcc_reg_bits pfcc_reg; 9776 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 9777 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 9778 struct mlx5_ifc_pifr_reg_bits pifr_reg; 9779 struct mlx5_ifc_pipg_reg_bits pipg_reg; 9780 struct mlx5_ifc_plbf_reg_bits plbf_reg; 9781 struct mlx5_ifc_plib_reg_bits plib_reg; 9782 struct mlx5_ifc_plpc_reg_bits plpc_reg; 9783 struct mlx5_ifc_pmaos_reg_bits pmaos_reg; 9784 struct mlx5_ifc_pmlp_reg_bits pmlp_reg; 9785 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg; 9786 struct mlx5_ifc_pmpc_reg_bits pmpc_reg; 9787 struct mlx5_ifc_pmpe_reg_bits pmpe_reg; 9788 struct mlx5_ifc_pmpr_reg_bits pmpr_reg; 9789 struct mlx5_ifc_pmtu_reg_bits pmtu_reg; 9790 struct mlx5_ifc_ppad_reg_bits ppad_reg; 9791 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg; 9792 struct mlx5_ifc_mpein_reg_bits mpein_reg; 9793 struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg; 9794 struct mlx5_ifc_pplm_reg_bits pplm_reg; 9795 struct mlx5_ifc_pplr_reg_bits pplr_reg; 9796 struct mlx5_ifc_ppsc_reg_bits ppsc_reg; 9797 struct mlx5_ifc_pqdr_reg_bits pqdr_reg; 9798 struct mlx5_ifc_pspa_reg_bits pspa_reg; 9799 struct mlx5_ifc_ptas_reg_bits ptas_reg; 9800 struct mlx5_ifc_ptys_reg_bits ptys_reg; 9801 struct mlx5_ifc_mlcr_reg_bits mlcr_reg; 9802 struct mlx5_ifc_pude_reg_bits pude_reg; 9803 struct mlx5_ifc_pvlc_reg_bits pvlc_reg; 9804 struct mlx5_ifc_slrg_reg_bits slrg_reg; 9805 struct mlx5_ifc_sltp_reg_bits sltp_reg; 9806 struct mlx5_ifc_mtpps_reg_bits mtpps_reg; 9807 struct mlx5_ifc_mtppse_reg_bits mtppse_reg; 9808 struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg; 9809 struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits; 9810 struct mlx5_ifc_fpga_cap_bits fpga_cap_bits; 9811 struct mlx5_ifc_mcqi_reg_bits mcqi_reg; 9812 struct mlx5_ifc_mcc_reg_bits mcc_reg; 9813 struct mlx5_ifc_mcda_reg_bits mcda_reg; 9814 struct mlx5_ifc_mirc_reg_bits mirc_reg; 9815 struct mlx5_ifc_mfrl_reg_bits mfrl_reg; 9816 u8 reserved_at_0[0x60e0]; 9817 }; 9818 9819 union mlx5_ifc_debug_enhancements_document_bits { 9820 struct mlx5_ifc_health_buffer_bits health_buffer; 9821 u8 reserved_at_0[0x200]; 9822 }; 9823 9824 union mlx5_ifc_uplink_pci_interface_document_bits { 9825 struct mlx5_ifc_initial_seg_bits initial_seg; 9826 u8 reserved_at_0[0x20060]; 9827 }; 9828 9829 struct mlx5_ifc_set_flow_table_root_out_bits { 9830 u8 status[0x8]; 9831 u8 reserved_at_8[0x18]; 9832 9833 u8 syndrome[0x20]; 9834 9835 u8 reserved_at_40[0x40]; 9836 }; 9837 9838 struct mlx5_ifc_set_flow_table_root_in_bits { 9839 u8 opcode[0x10]; 9840 u8 reserved_at_10[0x10]; 9841 9842 u8 reserved_at_20[0x10]; 9843 u8 op_mod[0x10]; 9844 9845 u8 other_vport[0x1]; 9846 u8 reserved_at_41[0xf]; 9847 u8 vport_number[0x10]; 9848 9849 u8 reserved_at_60[0x20]; 9850 9851 u8 table_type[0x8]; 9852 u8 reserved_at_88[0x18]; 9853 9854 u8 reserved_at_a0[0x8]; 9855 u8 table_id[0x18]; 9856 9857 u8 reserved_at_c0[0x8]; 9858 u8 underlay_qpn[0x18]; 9859 u8 reserved_at_e0[0x120]; 9860 }; 9861 9862 enum { 9863 MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = (1UL << 0), 9864 MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15), 9865 }; 9866 9867 struct mlx5_ifc_modify_flow_table_out_bits { 9868 u8 status[0x8]; 9869 u8 reserved_at_8[0x18]; 9870 9871 u8 syndrome[0x20]; 9872 9873 u8 reserved_at_40[0x40]; 9874 }; 9875 9876 struct mlx5_ifc_modify_flow_table_in_bits { 9877 u8 opcode[0x10]; 9878 u8 reserved_at_10[0x10]; 9879 9880 u8 reserved_at_20[0x10]; 9881 u8 op_mod[0x10]; 9882 9883 u8 other_vport[0x1]; 9884 u8 reserved_at_41[0xf]; 9885 u8 vport_number[0x10]; 9886 9887 u8 reserved_at_60[0x10]; 9888 u8 modify_field_select[0x10]; 9889 9890 u8 table_type[0x8]; 9891 u8 reserved_at_88[0x18]; 9892 9893 u8 reserved_at_a0[0x8]; 9894 u8 table_id[0x18]; 9895 9896 struct mlx5_ifc_flow_table_context_bits flow_table_context; 9897 }; 9898 9899 struct mlx5_ifc_ets_tcn_config_reg_bits { 9900 u8 g[0x1]; 9901 u8 b[0x1]; 9902 u8 r[0x1]; 9903 u8 reserved_at_3[0x9]; 9904 u8 group[0x4]; 9905 u8 reserved_at_10[0x9]; 9906 u8 bw_allocation[0x7]; 9907 9908 u8 reserved_at_20[0xc]; 9909 u8 max_bw_units[0x4]; 9910 u8 reserved_at_30[0x8]; 9911 u8 max_bw_value[0x8]; 9912 }; 9913 9914 struct mlx5_ifc_ets_global_config_reg_bits { 9915 u8 reserved_at_0[0x2]; 9916 u8 r[0x1]; 9917 u8 reserved_at_3[0x1d]; 9918 9919 u8 reserved_at_20[0xc]; 9920 u8 max_bw_units[0x4]; 9921 u8 reserved_at_30[0x8]; 9922 u8 max_bw_value[0x8]; 9923 }; 9924 9925 struct mlx5_ifc_qetc_reg_bits { 9926 u8 reserved_at_0[0x8]; 9927 u8 port_number[0x8]; 9928 u8 reserved_at_10[0x30]; 9929 9930 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8]; 9931 struct mlx5_ifc_ets_global_config_reg_bits global_configuration; 9932 }; 9933 9934 struct mlx5_ifc_qpdpm_dscp_reg_bits { 9935 u8 e[0x1]; 9936 u8 reserved_at_01[0x0b]; 9937 u8 prio[0x04]; 9938 }; 9939 9940 struct mlx5_ifc_qpdpm_reg_bits { 9941 u8 reserved_at_0[0x8]; 9942 u8 local_port[0x8]; 9943 u8 reserved_at_10[0x10]; 9944 struct mlx5_ifc_qpdpm_dscp_reg_bits dscp[64]; 9945 }; 9946 9947 struct mlx5_ifc_qpts_reg_bits { 9948 u8 reserved_at_0[0x8]; 9949 u8 local_port[0x8]; 9950 u8 reserved_at_10[0x2d]; 9951 u8 trust_state[0x3]; 9952 }; 9953 9954 struct mlx5_ifc_pptb_reg_bits { 9955 u8 reserved_at_0[0x2]; 9956 u8 mm[0x2]; 9957 u8 reserved_at_4[0x4]; 9958 u8 local_port[0x8]; 9959 u8 reserved_at_10[0x6]; 9960 u8 cm[0x1]; 9961 u8 um[0x1]; 9962 u8 pm[0x8]; 9963 9964 u8 prio_x_buff[0x20]; 9965 9966 u8 pm_msb[0x8]; 9967 u8 reserved_at_48[0x10]; 9968 u8 ctrl_buff[0x4]; 9969 u8 untagged_buff[0x4]; 9970 }; 9971 9972 struct mlx5_ifc_sbcam_reg_bits { 9973 u8 reserved_at_0[0x8]; 9974 u8 feature_group[0x8]; 9975 u8 reserved_at_10[0x8]; 9976 u8 access_reg_group[0x8]; 9977 9978 u8 reserved_at_20[0x20]; 9979 9980 u8 sb_access_reg_cap_mask[4][0x20]; 9981 9982 u8 reserved_at_c0[0x80]; 9983 9984 u8 sb_feature_cap_mask[4][0x20]; 9985 9986 u8 reserved_at_1c0[0x40]; 9987 9988 u8 cap_total_buffer_size[0x20]; 9989 9990 u8 cap_cell_size[0x10]; 9991 u8 cap_max_pg_buffers[0x8]; 9992 u8 cap_num_pool_supported[0x8]; 9993 9994 u8 reserved_at_240[0x8]; 9995 u8 cap_sbsr_stat_size[0x8]; 9996 u8 cap_max_tclass_data[0x8]; 9997 u8 cap_max_cpu_ingress_tclass_sb[0x8]; 9998 }; 9999 10000 struct mlx5_ifc_pbmc_reg_bits { 10001 u8 reserved_at_0[0x8]; 10002 u8 local_port[0x8]; 10003 u8 reserved_at_10[0x10]; 10004 10005 u8 xoff_timer_value[0x10]; 10006 u8 xoff_refresh[0x10]; 10007 10008 u8 reserved_at_40[0x9]; 10009 u8 fullness_threshold[0x7]; 10010 u8 port_buffer_size[0x10]; 10011 10012 struct mlx5_ifc_bufferx_reg_bits buffer[10]; 10013 10014 u8 reserved_at_2e0[0x40]; 10015 }; 10016 10017 struct mlx5_ifc_qtct_reg_bits { 10018 u8 reserved_at_0[0x8]; 10019 u8 port_number[0x8]; 10020 u8 reserved_at_10[0xd]; 10021 u8 prio[0x3]; 10022 10023 u8 reserved_at_20[0x1d]; 10024 u8 tclass[0x3]; 10025 }; 10026 10027 struct mlx5_ifc_mcia_reg_bits { 10028 u8 l[0x1]; 10029 u8 reserved_at_1[0x7]; 10030 u8 module[0x8]; 10031 u8 reserved_at_10[0x8]; 10032 u8 status[0x8]; 10033 10034 u8 i2c_device_address[0x8]; 10035 u8 page_number[0x8]; 10036 u8 device_address[0x10]; 10037 10038 u8 reserved_at_40[0x10]; 10039 u8 size[0x10]; 10040 10041 u8 reserved_at_60[0x20]; 10042 10043 u8 dword_0[0x20]; 10044 u8 dword_1[0x20]; 10045 u8 dword_2[0x20]; 10046 u8 dword_3[0x20]; 10047 u8 dword_4[0x20]; 10048 u8 dword_5[0x20]; 10049 u8 dword_6[0x20]; 10050 u8 dword_7[0x20]; 10051 u8 dword_8[0x20]; 10052 u8 dword_9[0x20]; 10053 u8 dword_10[0x20]; 10054 u8 dword_11[0x20]; 10055 }; 10056 10057 struct mlx5_ifc_dcbx_param_bits { 10058 u8 dcbx_cee_cap[0x1]; 10059 u8 dcbx_ieee_cap[0x1]; 10060 u8 dcbx_standby_cap[0x1]; 10061 u8 reserved_at_3[0x5]; 10062 u8 port_number[0x8]; 10063 u8 reserved_at_10[0xa]; 10064 u8 max_application_table_size[6]; 10065 u8 reserved_at_20[0x15]; 10066 u8 version_oper[0x3]; 10067 u8 reserved_at_38[5]; 10068 u8 version_admin[0x3]; 10069 u8 willing_admin[0x1]; 10070 u8 reserved_at_41[0x3]; 10071 u8 pfc_cap_oper[0x4]; 10072 u8 reserved_at_48[0x4]; 10073 u8 pfc_cap_admin[0x4]; 10074 u8 reserved_at_50[0x4]; 10075 u8 num_of_tc_oper[0x4]; 10076 u8 reserved_at_58[0x4]; 10077 u8 num_of_tc_admin[0x4]; 10078 u8 remote_willing[0x1]; 10079 u8 reserved_at_61[3]; 10080 u8 remote_pfc_cap[4]; 10081 u8 reserved_at_68[0x14]; 10082 u8 remote_num_of_tc[0x4]; 10083 u8 reserved_at_80[0x18]; 10084 u8 error[0x8]; 10085 u8 reserved_at_a0[0x160]; 10086 }; 10087 10088 struct mlx5_ifc_lagc_bits { 10089 u8 reserved_at_0[0x1d]; 10090 u8 lag_state[0x3]; 10091 10092 u8 reserved_at_20[0x14]; 10093 u8 tx_remap_affinity_2[0x4]; 10094 u8 reserved_at_38[0x4]; 10095 u8 tx_remap_affinity_1[0x4]; 10096 }; 10097 10098 struct mlx5_ifc_create_lag_out_bits { 10099 u8 status[0x8]; 10100 u8 reserved_at_8[0x18]; 10101 10102 u8 syndrome[0x20]; 10103 10104 u8 reserved_at_40[0x40]; 10105 }; 10106 10107 struct mlx5_ifc_create_lag_in_bits { 10108 u8 opcode[0x10]; 10109 u8 reserved_at_10[0x10]; 10110 10111 u8 reserved_at_20[0x10]; 10112 u8 op_mod[0x10]; 10113 10114 struct mlx5_ifc_lagc_bits ctx; 10115 }; 10116 10117 struct mlx5_ifc_modify_lag_out_bits { 10118 u8 status[0x8]; 10119 u8 reserved_at_8[0x18]; 10120 10121 u8 syndrome[0x20]; 10122 10123 u8 reserved_at_40[0x40]; 10124 }; 10125 10126 struct mlx5_ifc_modify_lag_in_bits { 10127 u8 opcode[0x10]; 10128 u8 reserved_at_10[0x10]; 10129 10130 u8 reserved_at_20[0x10]; 10131 u8 op_mod[0x10]; 10132 10133 u8 reserved_at_40[0x20]; 10134 u8 field_select[0x20]; 10135 10136 struct mlx5_ifc_lagc_bits ctx; 10137 }; 10138 10139 struct mlx5_ifc_query_lag_out_bits { 10140 u8 status[0x8]; 10141 u8 reserved_at_8[0x18]; 10142 10143 u8 syndrome[0x20]; 10144 10145 struct mlx5_ifc_lagc_bits ctx; 10146 }; 10147 10148 struct mlx5_ifc_query_lag_in_bits { 10149 u8 opcode[0x10]; 10150 u8 reserved_at_10[0x10]; 10151 10152 u8 reserved_at_20[0x10]; 10153 u8 op_mod[0x10]; 10154 10155 u8 reserved_at_40[0x40]; 10156 }; 10157 10158 struct mlx5_ifc_destroy_lag_out_bits { 10159 u8 status[0x8]; 10160 u8 reserved_at_8[0x18]; 10161 10162 u8 syndrome[0x20]; 10163 10164 u8 reserved_at_40[0x40]; 10165 }; 10166 10167 struct mlx5_ifc_destroy_lag_in_bits { 10168 u8 opcode[0x10]; 10169 u8 reserved_at_10[0x10]; 10170 10171 u8 reserved_at_20[0x10]; 10172 u8 op_mod[0x10]; 10173 10174 u8 reserved_at_40[0x40]; 10175 }; 10176 10177 struct mlx5_ifc_create_vport_lag_out_bits { 10178 u8 status[0x8]; 10179 u8 reserved_at_8[0x18]; 10180 10181 u8 syndrome[0x20]; 10182 10183 u8 reserved_at_40[0x40]; 10184 }; 10185 10186 struct mlx5_ifc_create_vport_lag_in_bits { 10187 u8 opcode[0x10]; 10188 u8 reserved_at_10[0x10]; 10189 10190 u8 reserved_at_20[0x10]; 10191 u8 op_mod[0x10]; 10192 10193 u8 reserved_at_40[0x40]; 10194 }; 10195 10196 struct mlx5_ifc_destroy_vport_lag_out_bits { 10197 u8 status[0x8]; 10198 u8 reserved_at_8[0x18]; 10199 10200 u8 syndrome[0x20]; 10201 10202 u8 reserved_at_40[0x40]; 10203 }; 10204 10205 struct mlx5_ifc_destroy_vport_lag_in_bits { 10206 u8 opcode[0x10]; 10207 u8 reserved_at_10[0x10]; 10208 10209 u8 reserved_at_20[0x10]; 10210 u8 op_mod[0x10]; 10211 10212 u8 reserved_at_40[0x40]; 10213 }; 10214 10215 struct mlx5_ifc_alloc_memic_in_bits { 10216 u8 opcode[0x10]; 10217 u8 reserved_at_10[0x10]; 10218 10219 u8 reserved_at_20[0x10]; 10220 u8 op_mod[0x10]; 10221 10222 u8 reserved_at_30[0x20]; 10223 10224 u8 reserved_at_40[0x18]; 10225 u8 log_memic_addr_alignment[0x8]; 10226 10227 u8 range_start_addr[0x40]; 10228 10229 u8 range_size[0x20]; 10230 10231 u8 memic_size[0x20]; 10232 }; 10233 10234 struct mlx5_ifc_alloc_memic_out_bits { 10235 u8 status[0x8]; 10236 u8 reserved_at_8[0x18]; 10237 10238 u8 syndrome[0x20]; 10239 10240 u8 memic_start_addr[0x40]; 10241 }; 10242 10243 struct mlx5_ifc_dealloc_memic_in_bits { 10244 u8 opcode[0x10]; 10245 u8 reserved_at_10[0x10]; 10246 10247 u8 reserved_at_20[0x10]; 10248 u8 op_mod[0x10]; 10249 10250 u8 reserved_at_40[0x40]; 10251 10252 u8 memic_start_addr[0x40]; 10253 10254 u8 memic_size[0x20]; 10255 10256 u8 reserved_at_e0[0x20]; 10257 }; 10258 10259 struct mlx5_ifc_dealloc_memic_out_bits { 10260 u8 status[0x8]; 10261 u8 reserved_at_8[0x18]; 10262 10263 u8 syndrome[0x20]; 10264 10265 u8 reserved_at_40[0x40]; 10266 }; 10267 10268 struct mlx5_ifc_general_obj_in_cmd_hdr_bits { 10269 u8 opcode[0x10]; 10270 u8 uid[0x10]; 10271 10272 u8 vhca_tunnel_id[0x10]; 10273 u8 obj_type[0x10]; 10274 10275 u8 obj_id[0x20]; 10276 10277 u8 reserved_at_60[0x20]; 10278 }; 10279 10280 struct mlx5_ifc_general_obj_out_cmd_hdr_bits { 10281 u8 status[0x8]; 10282 u8 reserved_at_8[0x18]; 10283 10284 u8 syndrome[0x20]; 10285 10286 u8 obj_id[0x20]; 10287 10288 u8 reserved_at_60[0x20]; 10289 }; 10290 10291 struct mlx5_ifc_umem_bits { 10292 u8 reserved_at_0[0x80]; 10293 10294 u8 reserved_at_80[0x1b]; 10295 u8 log_page_size[0x5]; 10296 10297 u8 page_offset[0x20]; 10298 10299 u8 num_of_mtt[0x40]; 10300 10301 struct mlx5_ifc_mtt_bits mtt[]; 10302 }; 10303 10304 struct mlx5_ifc_uctx_bits { 10305 u8 cap[0x20]; 10306 10307 u8 reserved_at_20[0x160]; 10308 }; 10309 10310 struct mlx5_ifc_sw_icm_bits { 10311 u8 modify_field_select[0x40]; 10312 10313 u8 reserved_at_40[0x18]; 10314 u8 log_sw_icm_size[0x8]; 10315 10316 u8 reserved_at_60[0x20]; 10317 10318 u8 sw_icm_start_addr[0x40]; 10319 10320 u8 reserved_at_c0[0x140]; 10321 }; 10322 10323 struct mlx5_ifc_geneve_tlv_option_bits { 10324 u8 modify_field_select[0x40]; 10325 10326 u8 reserved_at_40[0x18]; 10327 u8 geneve_option_fte_index[0x8]; 10328 10329 u8 option_class[0x10]; 10330 u8 option_type[0x8]; 10331 u8 reserved_at_78[0x3]; 10332 u8 option_data_length[0x5]; 10333 10334 u8 reserved_at_80[0x180]; 10335 }; 10336 10337 struct mlx5_ifc_create_umem_in_bits { 10338 u8 opcode[0x10]; 10339 u8 uid[0x10]; 10340 10341 u8 reserved_at_20[0x10]; 10342 u8 op_mod[0x10]; 10343 10344 u8 reserved_at_40[0x40]; 10345 10346 struct mlx5_ifc_umem_bits umem; 10347 }; 10348 10349 struct mlx5_ifc_create_uctx_in_bits { 10350 u8 opcode[0x10]; 10351 u8 reserved_at_10[0x10]; 10352 10353 u8 reserved_at_20[0x10]; 10354 u8 op_mod[0x10]; 10355 10356 u8 reserved_at_40[0x40]; 10357 10358 struct mlx5_ifc_uctx_bits uctx; 10359 }; 10360 10361 struct mlx5_ifc_destroy_uctx_in_bits { 10362 u8 opcode[0x10]; 10363 u8 reserved_at_10[0x10]; 10364 10365 u8 reserved_at_20[0x10]; 10366 u8 op_mod[0x10]; 10367 10368 u8 reserved_at_40[0x10]; 10369 u8 uid[0x10]; 10370 10371 u8 reserved_at_60[0x20]; 10372 }; 10373 10374 struct mlx5_ifc_create_sw_icm_in_bits { 10375 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 10376 struct mlx5_ifc_sw_icm_bits sw_icm; 10377 }; 10378 10379 struct mlx5_ifc_create_geneve_tlv_option_in_bits { 10380 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 10381 struct mlx5_ifc_geneve_tlv_option_bits geneve_tlv_opt; 10382 }; 10383 10384 struct mlx5_ifc_mtrc_string_db_param_bits { 10385 u8 string_db_base_address[0x20]; 10386 10387 u8 reserved_at_20[0x8]; 10388 u8 string_db_size[0x18]; 10389 }; 10390 10391 struct mlx5_ifc_mtrc_cap_bits { 10392 u8 trace_owner[0x1]; 10393 u8 trace_to_memory[0x1]; 10394 u8 reserved_at_2[0x4]; 10395 u8 trc_ver[0x2]; 10396 u8 reserved_at_8[0x14]; 10397 u8 num_string_db[0x4]; 10398 10399 u8 first_string_trace[0x8]; 10400 u8 num_string_trace[0x8]; 10401 u8 reserved_at_30[0x28]; 10402 10403 u8 log_max_trace_buffer_size[0x8]; 10404 10405 u8 reserved_at_60[0x20]; 10406 10407 struct mlx5_ifc_mtrc_string_db_param_bits string_db_param[8]; 10408 10409 u8 reserved_at_280[0x180]; 10410 }; 10411 10412 struct mlx5_ifc_mtrc_conf_bits { 10413 u8 reserved_at_0[0x1c]; 10414 u8 trace_mode[0x4]; 10415 u8 reserved_at_20[0x18]; 10416 u8 log_trace_buffer_size[0x8]; 10417 u8 trace_mkey[0x20]; 10418 u8 reserved_at_60[0x3a0]; 10419 }; 10420 10421 struct mlx5_ifc_mtrc_stdb_bits { 10422 u8 string_db_index[0x4]; 10423 u8 reserved_at_4[0x4]; 10424 u8 read_size[0x18]; 10425 u8 start_offset[0x20]; 10426 u8 string_db_data[]; 10427 }; 10428 10429 struct mlx5_ifc_mtrc_ctrl_bits { 10430 u8 trace_status[0x2]; 10431 u8 reserved_at_2[0x2]; 10432 u8 arm_event[0x1]; 10433 u8 reserved_at_5[0xb]; 10434 u8 modify_field_select[0x10]; 10435 u8 reserved_at_20[0x2b]; 10436 u8 current_timestamp52_32[0x15]; 10437 u8 current_timestamp31_0[0x20]; 10438 u8 reserved_at_80[0x180]; 10439 }; 10440 10441 struct mlx5_ifc_host_params_context_bits { 10442 u8 host_number[0x8]; 10443 u8 reserved_at_8[0x7]; 10444 u8 host_pf_disabled[0x1]; 10445 u8 host_num_of_vfs[0x10]; 10446 10447 u8 host_total_vfs[0x10]; 10448 u8 host_pci_bus[0x10]; 10449 10450 u8 reserved_at_40[0x10]; 10451 u8 host_pci_device[0x10]; 10452 10453 u8 reserved_at_60[0x10]; 10454 u8 host_pci_function[0x10]; 10455 10456 u8 reserved_at_80[0x180]; 10457 }; 10458 10459 struct mlx5_ifc_query_esw_functions_in_bits { 10460 u8 opcode[0x10]; 10461 u8 reserved_at_10[0x10]; 10462 10463 u8 reserved_at_20[0x10]; 10464 u8 op_mod[0x10]; 10465 10466 u8 reserved_at_40[0x40]; 10467 }; 10468 10469 struct mlx5_ifc_query_esw_functions_out_bits { 10470 u8 status[0x8]; 10471 u8 reserved_at_8[0x18]; 10472 10473 u8 syndrome[0x20]; 10474 10475 u8 reserved_at_40[0x40]; 10476 10477 struct mlx5_ifc_host_params_context_bits host_params_context; 10478 10479 u8 reserved_at_280[0x180]; 10480 u8 host_sf_enable[][0x40]; 10481 }; 10482 10483 struct mlx5_ifc_sf_partition_bits { 10484 u8 reserved_at_0[0x10]; 10485 u8 log_num_sf[0x8]; 10486 u8 log_sf_bar_size[0x8]; 10487 }; 10488 10489 struct mlx5_ifc_query_sf_partitions_out_bits { 10490 u8 status[0x8]; 10491 u8 reserved_at_8[0x18]; 10492 10493 u8 syndrome[0x20]; 10494 10495 u8 reserved_at_40[0x18]; 10496 u8 num_sf_partitions[0x8]; 10497 10498 u8 reserved_at_60[0x20]; 10499 10500 struct mlx5_ifc_sf_partition_bits sf_partition[]; 10501 }; 10502 10503 struct mlx5_ifc_query_sf_partitions_in_bits { 10504 u8 opcode[0x10]; 10505 u8 reserved_at_10[0x10]; 10506 10507 u8 reserved_at_20[0x10]; 10508 u8 op_mod[0x10]; 10509 10510 u8 reserved_at_40[0x40]; 10511 }; 10512 10513 struct mlx5_ifc_dealloc_sf_out_bits { 10514 u8 status[0x8]; 10515 u8 reserved_at_8[0x18]; 10516 10517 u8 syndrome[0x20]; 10518 10519 u8 reserved_at_40[0x40]; 10520 }; 10521 10522 struct mlx5_ifc_dealloc_sf_in_bits { 10523 u8 opcode[0x10]; 10524 u8 reserved_at_10[0x10]; 10525 10526 u8 reserved_at_20[0x10]; 10527 u8 op_mod[0x10]; 10528 10529 u8 reserved_at_40[0x10]; 10530 u8 function_id[0x10]; 10531 10532 u8 reserved_at_60[0x20]; 10533 }; 10534 10535 struct mlx5_ifc_alloc_sf_out_bits { 10536 u8 status[0x8]; 10537 u8 reserved_at_8[0x18]; 10538 10539 u8 syndrome[0x20]; 10540 10541 u8 reserved_at_40[0x40]; 10542 }; 10543 10544 struct mlx5_ifc_alloc_sf_in_bits { 10545 u8 opcode[0x10]; 10546 u8 reserved_at_10[0x10]; 10547 10548 u8 reserved_at_20[0x10]; 10549 u8 op_mod[0x10]; 10550 10551 u8 reserved_at_40[0x10]; 10552 u8 function_id[0x10]; 10553 10554 u8 reserved_at_60[0x20]; 10555 }; 10556 10557 struct mlx5_ifc_affiliated_event_header_bits { 10558 u8 reserved_at_0[0x10]; 10559 u8 obj_type[0x10]; 10560 10561 u8 obj_id[0x20]; 10562 }; 10563 10564 enum { 10565 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = BIT(0xc), 10566 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_IPSEC = BIT(0x13), 10567 }; 10568 10569 enum { 10570 MLX5_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = 0xc, 10571 MLX5_GENERAL_OBJECT_TYPES_IPSEC = 0x13, 10572 }; 10573 10574 enum { 10575 MLX5_IPSEC_OBJECT_ICV_LEN_16B, 10576 MLX5_IPSEC_OBJECT_ICV_LEN_12B, 10577 MLX5_IPSEC_OBJECT_ICV_LEN_8B, 10578 }; 10579 10580 struct mlx5_ifc_ipsec_obj_bits { 10581 u8 modify_field_select[0x40]; 10582 u8 full_offload[0x1]; 10583 u8 reserved_at_41[0x1]; 10584 u8 esn_en[0x1]; 10585 u8 esn_overlap[0x1]; 10586 u8 reserved_at_44[0x2]; 10587 u8 icv_length[0x2]; 10588 u8 reserved_at_48[0x4]; 10589 u8 aso_return_reg[0x4]; 10590 u8 reserved_at_50[0x10]; 10591 10592 u8 esn_msb[0x20]; 10593 10594 u8 reserved_at_80[0x8]; 10595 u8 dekn[0x18]; 10596 10597 u8 salt[0x20]; 10598 10599 u8 implicit_iv[0x40]; 10600 10601 u8 reserved_at_100[0x700]; 10602 }; 10603 10604 struct mlx5_ifc_create_ipsec_obj_in_bits { 10605 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 10606 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 10607 }; 10608 10609 enum { 10610 MLX5_MODIFY_IPSEC_BITMASK_ESN_OVERLAP = BIT(0), 10611 MLX5_MODIFY_IPSEC_BITMASK_ESN_MSB = BIT(1), 10612 }; 10613 10614 struct mlx5_ifc_query_ipsec_obj_out_bits { 10615 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 10616 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 10617 }; 10618 10619 struct mlx5_ifc_modify_ipsec_obj_in_bits { 10620 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 10621 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 10622 }; 10623 10624 struct mlx5_ifc_encryption_key_obj_bits { 10625 u8 modify_field_select[0x40]; 10626 10627 u8 reserved_at_40[0x14]; 10628 u8 key_size[0x4]; 10629 u8 reserved_at_58[0x4]; 10630 u8 key_type[0x4]; 10631 10632 u8 reserved_at_60[0x8]; 10633 u8 pd[0x18]; 10634 10635 u8 reserved_at_80[0x180]; 10636 u8 key[8][0x20]; 10637 10638 u8 reserved_at_300[0x500]; 10639 }; 10640 10641 struct mlx5_ifc_create_encryption_key_in_bits { 10642 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 10643 struct mlx5_ifc_encryption_key_obj_bits encryption_key_object; 10644 }; 10645 10646 enum { 10647 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_128 = 0x0, 10648 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_256 = 0x1, 10649 }; 10650 10651 enum { 10652 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_TYPE_TLS = 0x1, 10653 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_TYPE_IPSEC = 0x2, 10654 }; 10655 10656 struct mlx5_ifc_tls_static_params_bits { 10657 u8 const_2[0x2]; 10658 u8 tls_version[0x4]; 10659 u8 const_1[0x2]; 10660 u8 reserved_at_8[0x14]; 10661 u8 encryption_standard[0x4]; 10662 10663 u8 reserved_at_20[0x20]; 10664 10665 u8 initial_record_number[0x40]; 10666 10667 u8 resync_tcp_sn[0x20]; 10668 10669 u8 gcm_iv[0x20]; 10670 10671 u8 implicit_iv[0x40]; 10672 10673 u8 reserved_at_100[0x8]; 10674 u8 dek_index[0x18]; 10675 10676 u8 reserved_at_120[0xe0]; 10677 }; 10678 10679 struct mlx5_ifc_tls_progress_params_bits { 10680 u8 next_record_tcp_sn[0x20]; 10681 10682 u8 hw_resync_tcp_sn[0x20]; 10683 10684 u8 record_tracker_state[0x2]; 10685 u8 auth_state[0x2]; 10686 u8 reserved_at_44[0x4]; 10687 u8 hw_offset_record_number[0x18]; 10688 }; 10689 10690 #endif /* MLX5_IFC_H */ 10691