1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 #ifndef MLX5_IFC_H 33 #define MLX5_IFC_H 34 35 #include "mlx5_ifc_fpga.h" 36 37 enum { 38 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0, 39 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1, 40 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2, 41 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3, 42 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13, 43 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14, 44 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c, 45 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d, 46 MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4, 47 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5, 48 MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED = 0x7, 49 MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT = 0xc, 50 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10, 51 MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR = 0x11, 52 MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR = 0x12, 53 MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR = 0x8, 54 MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE = 0x9, 55 MLX5_EVENT_TYPE_CODING_GPIO_EVENT = 0x15, 56 MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19, 57 MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a, 58 MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT = 0x1b, 59 MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT = 0x1f, 60 MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa, 61 MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb, 62 MLX5_EVENT_TYPE_CODING_FPGA_ERROR = 0x20, 63 MLX5_EVENT_TYPE_CODING_FPGA_QP_ERROR = 0x21 64 }; 65 66 enum { 67 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0, 68 MLX5_SET_HCA_CAP_OP_MOD_ETHERNET_OFFLOADS = 0x1, 69 MLX5_SET_HCA_CAP_OP_MOD_ODP = 0x2, 70 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3, 71 MLX5_SET_HCA_CAP_OP_MOD_ROCE = 0x4, 72 MLX5_SET_HCA_CAP_OP_MOD_IPSEC = 0x15, 73 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE2 = 0x20, 74 MLX5_SET_HCA_CAP_OP_MOD_PORT_SELECTION = 0x25, 75 }; 76 77 enum { 78 MLX5_SHARED_RESOURCE_UID = 0xffff, 79 }; 80 81 enum { 82 MLX5_OBJ_TYPE_SW_ICM = 0x0008, 83 MLX5_OBJ_TYPE_HEADER_MODIFY_ARGUMENT = 0x23, 84 }; 85 86 enum { 87 MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM = (1ULL << MLX5_OBJ_TYPE_SW_ICM), 88 MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT = (1ULL << 11), 89 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q = (1ULL << 13), 90 MLX5_GENERAL_OBJ_TYPES_CAP_HEADER_MODIFY_ARGUMENT = 91 (1ULL << MLX5_OBJ_TYPE_HEADER_MODIFY_ARGUMENT), 92 MLX5_GENERAL_OBJ_TYPES_CAP_MACSEC_OFFLOAD = (1ULL << 39), 93 }; 94 95 enum { 96 MLX5_OBJ_TYPE_GENEVE_TLV_OPT = 0x000b, 97 MLX5_OBJ_TYPE_VIRTIO_NET_Q = 0x000d, 98 MLX5_OBJ_TYPE_VIRTIO_Q_COUNTERS = 0x001c, 99 MLX5_OBJ_TYPE_MATCH_DEFINER = 0x0018, 100 MLX5_OBJ_TYPE_PAGE_TRACK = 0x46, 101 MLX5_OBJ_TYPE_MKEY = 0xff01, 102 MLX5_OBJ_TYPE_QP = 0xff02, 103 MLX5_OBJ_TYPE_PSV = 0xff03, 104 MLX5_OBJ_TYPE_RMP = 0xff04, 105 MLX5_OBJ_TYPE_XRC_SRQ = 0xff05, 106 MLX5_OBJ_TYPE_RQ = 0xff06, 107 MLX5_OBJ_TYPE_SQ = 0xff07, 108 MLX5_OBJ_TYPE_TIR = 0xff08, 109 MLX5_OBJ_TYPE_TIS = 0xff09, 110 MLX5_OBJ_TYPE_DCT = 0xff0a, 111 MLX5_OBJ_TYPE_XRQ = 0xff0b, 112 MLX5_OBJ_TYPE_RQT = 0xff0e, 113 MLX5_OBJ_TYPE_FLOW_COUNTER = 0xff0f, 114 MLX5_OBJ_TYPE_CQ = 0xff10, 115 }; 116 117 enum { 118 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100, 119 MLX5_CMD_OP_QUERY_ADAPTER = 0x101, 120 MLX5_CMD_OP_INIT_HCA = 0x102, 121 MLX5_CMD_OP_TEARDOWN_HCA = 0x103, 122 MLX5_CMD_OP_ENABLE_HCA = 0x104, 123 MLX5_CMD_OP_DISABLE_HCA = 0x105, 124 MLX5_CMD_OP_QUERY_PAGES = 0x107, 125 MLX5_CMD_OP_MANAGE_PAGES = 0x108, 126 MLX5_CMD_OP_SET_HCA_CAP = 0x109, 127 MLX5_CMD_OP_QUERY_ISSI = 0x10a, 128 MLX5_CMD_OP_SET_ISSI = 0x10b, 129 MLX5_CMD_OP_SET_DRIVER_VERSION = 0x10d, 130 MLX5_CMD_OP_QUERY_SF_PARTITION = 0x111, 131 MLX5_CMD_OP_ALLOC_SF = 0x113, 132 MLX5_CMD_OP_DEALLOC_SF = 0x114, 133 MLX5_CMD_OP_SUSPEND_VHCA = 0x115, 134 MLX5_CMD_OP_RESUME_VHCA = 0x116, 135 MLX5_CMD_OP_QUERY_VHCA_MIGRATION_STATE = 0x117, 136 MLX5_CMD_OP_SAVE_VHCA_STATE = 0x118, 137 MLX5_CMD_OP_LOAD_VHCA_STATE = 0x119, 138 MLX5_CMD_OP_CREATE_MKEY = 0x200, 139 MLX5_CMD_OP_QUERY_MKEY = 0x201, 140 MLX5_CMD_OP_DESTROY_MKEY = 0x202, 141 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203, 142 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204, 143 MLX5_CMD_OP_ALLOC_MEMIC = 0x205, 144 MLX5_CMD_OP_DEALLOC_MEMIC = 0x206, 145 MLX5_CMD_OP_MODIFY_MEMIC = 0x207, 146 MLX5_CMD_OP_CREATE_EQ = 0x301, 147 MLX5_CMD_OP_DESTROY_EQ = 0x302, 148 MLX5_CMD_OP_QUERY_EQ = 0x303, 149 MLX5_CMD_OP_GEN_EQE = 0x304, 150 MLX5_CMD_OP_CREATE_CQ = 0x400, 151 MLX5_CMD_OP_DESTROY_CQ = 0x401, 152 MLX5_CMD_OP_QUERY_CQ = 0x402, 153 MLX5_CMD_OP_MODIFY_CQ = 0x403, 154 MLX5_CMD_OP_CREATE_QP = 0x500, 155 MLX5_CMD_OP_DESTROY_QP = 0x501, 156 MLX5_CMD_OP_RST2INIT_QP = 0x502, 157 MLX5_CMD_OP_INIT2RTR_QP = 0x503, 158 MLX5_CMD_OP_RTR2RTS_QP = 0x504, 159 MLX5_CMD_OP_RTS2RTS_QP = 0x505, 160 MLX5_CMD_OP_SQERR2RTS_QP = 0x506, 161 MLX5_CMD_OP_2ERR_QP = 0x507, 162 MLX5_CMD_OP_2RST_QP = 0x50a, 163 MLX5_CMD_OP_QUERY_QP = 0x50b, 164 MLX5_CMD_OP_SQD_RTS_QP = 0x50c, 165 MLX5_CMD_OP_INIT2INIT_QP = 0x50e, 166 MLX5_CMD_OP_CREATE_PSV = 0x600, 167 MLX5_CMD_OP_DESTROY_PSV = 0x601, 168 MLX5_CMD_OP_CREATE_SRQ = 0x700, 169 MLX5_CMD_OP_DESTROY_SRQ = 0x701, 170 MLX5_CMD_OP_QUERY_SRQ = 0x702, 171 MLX5_CMD_OP_ARM_RQ = 0x703, 172 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705, 173 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706, 174 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707, 175 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708, 176 MLX5_CMD_OP_CREATE_DCT = 0x710, 177 MLX5_CMD_OP_DESTROY_DCT = 0x711, 178 MLX5_CMD_OP_DRAIN_DCT = 0x712, 179 MLX5_CMD_OP_QUERY_DCT = 0x713, 180 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714, 181 MLX5_CMD_OP_CREATE_XRQ = 0x717, 182 MLX5_CMD_OP_DESTROY_XRQ = 0x718, 183 MLX5_CMD_OP_QUERY_XRQ = 0x719, 184 MLX5_CMD_OP_ARM_XRQ = 0x71a, 185 MLX5_CMD_OP_QUERY_XRQ_DC_PARAMS_ENTRY = 0x725, 186 MLX5_CMD_OP_SET_XRQ_DC_PARAMS_ENTRY = 0x726, 187 MLX5_CMD_OP_QUERY_XRQ_ERROR_PARAMS = 0x727, 188 MLX5_CMD_OP_RELEASE_XRQ_ERROR = 0x729, 189 MLX5_CMD_OP_MODIFY_XRQ = 0x72a, 190 MLX5_CMD_OP_QUERY_ESW_FUNCTIONS = 0x740, 191 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750, 192 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751, 193 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752, 194 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753, 195 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754, 196 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755, 197 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760, 198 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761, 199 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762, 200 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763, 201 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764, 202 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765, 203 MLX5_CMD_OP_QUERY_VNIC_ENV = 0x76f, 204 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770, 205 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771, 206 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772, 207 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773, 208 MLX5_CMD_OP_SET_MONITOR_COUNTER = 0x774, 209 MLX5_CMD_OP_ARM_MONITOR_COUNTER = 0x775, 210 MLX5_CMD_OP_SET_PP_RATE_LIMIT = 0x780, 211 MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781, 212 MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT = 0x782, 213 MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT = 0x783, 214 MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT = 0x784, 215 MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT = 0x785, 216 MLX5_CMD_OP_CREATE_QOS_PARA_VPORT = 0x786, 217 MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT = 0x787, 218 MLX5_CMD_OP_ALLOC_PD = 0x800, 219 MLX5_CMD_OP_DEALLOC_PD = 0x801, 220 MLX5_CMD_OP_ALLOC_UAR = 0x802, 221 MLX5_CMD_OP_DEALLOC_UAR = 0x803, 222 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804, 223 MLX5_CMD_OP_ACCESS_REG = 0x805, 224 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806, 225 MLX5_CMD_OP_DETACH_FROM_MCG = 0x807, 226 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a, 227 MLX5_CMD_OP_MAD_IFC = 0x50d, 228 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b, 229 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c, 230 MLX5_CMD_OP_NOP = 0x80d, 231 MLX5_CMD_OP_ALLOC_XRCD = 0x80e, 232 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f, 233 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816, 234 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817, 235 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822, 236 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823, 237 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824, 238 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825, 239 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826, 240 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827, 241 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828, 242 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829, 243 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a, 244 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b, 245 MLX5_CMD_OP_SET_WOL_ROL = 0x830, 246 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831, 247 MLX5_CMD_OP_CREATE_LAG = 0x840, 248 MLX5_CMD_OP_MODIFY_LAG = 0x841, 249 MLX5_CMD_OP_QUERY_LAG = 0x842, 250 MLX5_CMD_OP_DESTROY_LAG = 0x843, 251 MLX5_CMD_OP_CREATE_VPORT_LAG = 0x844, 252 MLX5_CMD_OP_DESTROY_VPORT_LAG = 0x845, 253 MLX5_CMD_OP_CREATE_TIR = 0x900, 254 MLX5_CMD_OP_MODIFY_TIR = 0x901, 255 MLX5_CMD_OP_DESTROY_TIR = 0x902, 256 MLX5_CMD_OP_QUERY_TIR = 0x903, 257 MLX5_CMD_OP_CREATE_SQ = 0x904, 258 MLX5_CMD_OP_MODIFY_SQ = 0x905, 259 MLX5_CMD_OP_DESTROY_SQ = 0x906, 260 MLX5_CMD_OP_QUERY_SQ = 0x907, 261 MLX5_CMD_OP_CREATE_RQ = 0x908, 262 MLX5_CMD_OP_MODIFY_RQ = 0x909, 263 MLX5_CMD_OP_SET_DELAY_DROP_PARAMS = 0x910, 264 MLX5_CMD_OP_DESTROY_RQ = 0x90a, 265 MLX5_CMD_OP_QUERY_RQ = 0x90b, 266 MLX5_CMD_OP_CREATE_RMP = 0x90c, 267 MLX5_CMD_OP_MODIFY_RMP = 0x90d, 268 MLX5_CMD_OP_DESTROY_RMP = 0x90e, 269 MLX5_CMD_OP_QUERY_RMP = 0x90f, 270 MLX5_CMD_OP_CREATE_TIS = 0x912, 271 MLX5_CMD_OP_MODIFY_TIS = 0x913, 272 MLX5_CMD_OP_DESTROY_TIS = 0x914, 273 MLX5_CMD_OP_QUERY_TIS = 0x915, 274 MLX5_CMD_OP_CREATE_RQT = 0x916, 275 MLX5_CMD_OP_MODIFY_RQT = 0x917, 276 MLX5_CMD_OP_DESTROY_RQT = 0x918, 277 MLX5_CMD_OP_QUERY_RQT = 0x919, 278 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f, 279 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930, 280 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931, 281 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932, 282 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933, 283 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934, 284 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935, 285 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936, 286 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937, 287 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938, 288 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939, 289 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a, 290 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b, 291 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c, 292 MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT = 0x93d, 293 MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT = 0x93e, 294 MLX5_CMD_OP_QUERY_PACKET_REFORMAT_CONTEXT = 0x93f, 295 MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT = 0x940, 296 MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941, 297 MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT = 0x942, 298 MLX5_CMD_OP_FPGA_CREATE_QP = 0x960, 299 MLX5_CMD_OP_FPGA_MODIFY_QP = 0x961, 300 MLX5_CMD_OP_FPGA_QUERY_QP = 0x962, 301 MLX5_CMD_OP_FPGA_DESTROY_QP = 0x963, 302 MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS = 0x964, 303 MLX5_CMD_OP_CREATE_GENERAL_OBJECT = 0xa00, 304 MLX5_CMD_OP_MODIFY_GENERAL_OBJECT = 0xa01, 305 MLX5_CMD_OP_QUERY_GENERAL_OBJECT = 0xa02, 306 MLX5_CMD_OP_DESTROY_GENERAL_OBJECT = 0xa03, 307 MLX5_CMD_OP_CREATE_UCTX = 0xa04, 308 MLX5_CMD_OP_DESTROY_UCTX = 0xa06, 309 MLX5_CMD_OP_CREATE_UMEM = 0xa08, 310 MLX5_CMD_OP_DESTROY_UMEM = 0xa0a, 311 MLX5_CMD_OP_SYNC_STEERING = 0xb00, 312 MLX5_CMD_OP_QUERY_VHCA_STATE = 0xb0d, 313 MLX5_CMD_OP_MODIFY_VHCA_STATE = 0xb0e, 314 MLX5_CMD_OP_SYNC_CRYPTO = 0xb12, 315 MLX5_CMD_OP_ALLOW_OTHER_VHCA_ACCESS = 0xb16, 316 MLX5_CMD_OP_MAX 317 }; 318 319 /* Valid range for general commands that don't work over an object */ 320 enum { 321 MLX5_CMD_OP_GENERAL_START = 0xb00, 322 MLX5_CMD_OP_GENERAL_END = 0xd00, 323 }; 324 325 enum { 326 MLX5_FT_NIC_RX_2_NIC_RX_RDMA = BIT(0), 327 MLX5_FT_NIC_TX_RDMA_2_NIC_TX = BIT(1), 328 }; 329 330 enum { 331 MLX5_CMD_OP_MOD_UPDATE_HEADER_MODIFY_ARGUMENT = 0x1, 332 }; 333 334 struct mlx5_ifc_flow_table_fields_supported_bits { 335 u8 outer_dmac[0x1]; 336 u8 outer_smac[0x1]; 337 u8 outer_ether_type[0x1]; 338 u8 outer_ip_version[0x1]; 339 u8 outer_first_prio[0x1]; 340 u8 outer_first_cfi[0x1]; 341 u8 outer_first_vid[0x1]; 342 u8 outer_ipv4_ttl[0x1]; 343 u8 outer_second_prio[0x1]; 344 u8 outer_second_cfi[0x1]; 345 u8 outer_second_vid[0x1]; 346 u8 reserved_at_b[0x1]; 347 u8 outer_sip[0x1]; 348 u8 outer_dip[0x1]; 349 u8 outer_frag[0x1]; 350 u8 outer_ip_protocol[0x1]; 351 u8 outer_ip_ecn[0x1]; 352 u8 outer_ip_dscp[0x1]; 353 u8 outer_udp_sport[0x1]; 354 u8 outer_udp_dport[0x1]; 355 u8 outer_tcp_sport[0x1]; 356 u8 outer_tcp_dport[0x1]; 357 u8 outer_tcp_flags[0x1]; 358 u8 outer_gre_protocol[0x1]; 359 u8 outer_gre_key[0x1]; 360 u8 outer_vxlan_vni[0x1]; 361 u8 outer_geneve_vni[0x1]; 362 u8 outer_geneve_oam[0x1]; 363 u8 outer_geneve_protocol_type[0x1]; 364 u8 outer_geneve_opt_len[0x1]; 365 u8 source_vhca_port[0x1]; 366 u8 source_eswitch_port[0x1]; 367 368 u8 inner_dmac[0x1]; 369 u8 inner_smac[0x1]; 370 u8 inner_ether_type[0x1]; 371 u8 inner_ip_version[0x1]; 372 u8 inner_first_prio[0x1]; 373 u8 inner_first_cfi[0x1]; 374 u8 inner_first_vid[0x1]; 375 u8 reserved_at_27[0x1]; 376 u8 inner_second_prio[0x1]; 377 u8 inner_second_cfi[0x1]; 378 u8 inner_second_vid[0x1]; 379 u8 reserved_at_2b[0x1]; 380 u8 inner_sip[0x1]; 381 u8 inner_dip[0x1]; 382 u8 inner_frag[0x1]; 383 u8 inner_ip_protocol[0x1]; 384 u8 inner_ip_ecn[0x1]; 385 u8 inner_ip_dscp[0x1]; 386 u8 inner_udp_sport[0x1]; 387 u8 inner_udp_dport[0x1]; 388 u8 inner_tcp_sport[0x1]; 389 u8 inner_tcp_dport[0x1]; 390 u8 inner_tcp_flags[0x1]; 391 u8 reserved_at_37[0x9]; 392 393 u8 geneve_tlv_option_0_data[0x1]; 394 u8 geneve_tlv_option_0_exist[0x1]; 395 u8 reserved_at_42[0x3]; 396 u8 outer_first_mpls_over_udp[0x4]; 397 u8 outer_first_mpls_over_gre[0x4]; 398 u8 inner_first_mpls[0x4]; 399 u8 outer_first_mpls[0x4]; 400 u8 reserved_at_55[0x2]; 401 u8 outer_esp_spi[0x1]; 402 u8 reserved_at_58[0x2]; 403 u8 bth_dst_qp[0x1]; 404 u8 reserved_at_5b[0x5]; 405 406 u8 reserved_at_60[0x18]; 407 u8 metadata_reg_c_7[0x1]; 408 u8 metadata_reg_c_6[0x1]; 409 u8 metadata_reg_c_5[0x1]; 410 u8 metadata_reg_c_4[0x1]; 411 u8 metadata_reg_c_3[0x1]; 412 u8 metadata_reg_c_2[0x1]; 413 u8 metadata_reg_c_1[0x1]; 414 u8 metadata_reg_c_0[0x1]; 415 }; 416 417 /* Table 2170 - Flow Table Fields Supported 2 Format */ 418 struct mlx5_ifc_flow_table_fields_supported_2_bits { 419 u8 reserved_at_0[0x2]; 420 u8 inner_l4_type[0x1]; 421 u8 outer_l4_type[0x1]; 422 u8 reserved_at_4[0xa]; 423 u8 bth_opcode[0x1]; 424 u8 reserved_at_f[0x1]; 425 u8 tunnel_header_0_1[0x1]; 426 u8 reserved_at_11[0xf]; 427 428 u8 reserved_at_20[0x60]; 429 }; 430 431 struct mlx5_ifc_flow_table_prop_layout_bits { 432 u8 ft_support[0x1]; 433 u8 reserved_at_1[0x1]; 434 u8 flow_counter[0x1]; 435 u8 flow_modify_en[0x1]; 436 u8 modify_root[0x1]; 437 u8 identified_miss_table_mode[0x1]; 438 u8 flow_table_modify[0x1]; 439 u8 reformat[0x1]; 440 u8 decap[0x1]; 441 u8 reset_root_to_default[0x1]; 442 u8 pop_vlan[0x1]; 443 u8 push_vlan[0x1]; 444 u8 reserved_at_c[0x1]; 445 u8 pop_vlan_2[0x1]; 446 u8 push_vlan_2[0x1]; 447 u8 reformat_and_vlan_action[0x1]; 448 u8 reserved_at_10[0x1]; 449 u8 sw_owner[0x1]; 450 u8 reformat_l3_tunnel_to_l2[0x1]; 451 u8 reformat_l2_to_l3_tunnel[0x1]; 452 u8 reformat_and_modify_action[0x1]; 453 u8 ignore_flow_level[0x1]; 454 u8 reserved_at_16[0x1]; 455 u8 table_miss_action_domain[0x1]; 456 u8 termination_table[0x1]; 457 u8 reformat_and_fwd_to_table[0x1]; 458 u8 reserved_at_1a[0x2]; 459 u8 ipsec_encrypt[0x1]; 460 u8 ipsec_decrypt[0x1]; 461 u8 sw_owner_v2[0x1]; 462 u8 reserved_at_1f[0x1]; 463 464 u8 termination_table_raw_traffic[0x1]; 465 u8 reserved_at_21[0x1]; 466 u8 log_max_ft_size[0x6]; 467 u8 log_max_modify_header_context[0x8]; 468 u8 max_modify_header_actions[0x8]; 469 u8 max_ft_level[0x8]; 470 471 u8 reformat_add_esp_trasport[0x1]; 472 u8 reformat_l2_to_l3_esp_tunnel[0x1]; 473 u8 reformat_add_esp_transport_over_udp[0x1]; 474 u8 reformat_del_esp_trasport[0x1]; 475 u8 reformat_l3_esp_tunnel_to_l2[0x1]; 476 u8 reformat_del_esp_transport_over_udp[0x1]; 477 u8 execute_aso[0x1]; 478 u8 reserved_at_47[0x19]; 479 480 u8 reserved_at_60[0x2]; 481 u8 reformat_insert[0x1]; 482 u8 reformat_remove[0x1]; 483 u8 macsec_encrypt[0x1]; 484 u8 macsec_decrypt[0x1]; 485 u8 reserved_at_66[0x2]; 486 u8 reformat_add_macsec[0x1]; 487 u8 reformat_remove_macsec[0x1]; 488 u8 reserved_at_6a[0xe]; 489 u8 log_max_ft_num[0x8]; 490 491 u8 reserved_at_80[0x10]; 492 u8 log_max_flow_counter[0x8]; 493 u8 log_max_destination[0x8]; 494 495 u8 reserved_at_a0[0x18]; 496 u8 log_max_flow[0x8]; 497 498 u8 reserved_at_c0[0x40]; 499 500 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support; 501 502 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support; 503 }; 504 505 struct mlx5_ifc_odp_per_transport_service_cap_bits { 506 u8 send[0x1]; 507 u8 receive[0x1]; 508 u8 write[0x1]; 509 u8 read[0x1]; 510 u8 atomic[0x1]; 511 u8 srq_receive[0x1]; 512 u8 reserved_at_6[0x1a]; 513 }; 514 515 struct mlx5_ifc_ipv4_layout_bits { 516 u8 reserved_at_0[0x60]; 517 518 u8 ipv4[0x20]; 519 }; 520 521 struct mlx5_ifc_ipv6_layout_bits { 522 u8 ipv6[16][0x8]; 523 }; 524 525 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits { 526 struct mlx5_ifc_ipv6_layout_bits ipv6_layout; 527 struct mlx5_ifc_ipv4_layout_bits ipv4_layout; 528 u8 reserved_at_0[0x80]; 529 }; 530 531 enum { 532 MLX5_PACKET_L4_TYPE_NONE, 533 MLX5_PACKET_L4_TYPE_TCP, 534 MLX5_PACKET_L4_TYPE_UDP, 535 }; 536 537 struct mlx5_ifc_fte_match_set_lyr_2_4_bits { 538 u8 smac_47_16[0x20]; 539 540 u8 smac_15_0[0x10]; 541 u8 ethertype[0x10]; 542 543 u8 dmac_47_16[0x20]; 544 545 u8 dmac_15_0[0x10]; 546 u8 first_prio[0x3]; 547 u8 first_cfi[0x1]; 548 u8 first_vid[0xc]; 549 550 u8 ip_protocol[0x8]; 551 u8 ip_dscp[0x6]; 552 u8 ip_ecn[0x2]; 553 u8 cvlan_tag[0x1]; 554 u8 svlan_tag[0x1]; 555 u8 frag[0x1]; 556 u8 ip_version[0x4]; 557 u8 tcp_flags[0x9]; 558 559 u8 tcp_sport[0x10]; 560 u8 tcp_dport[0x10]; 561 562 u8 l4_type[0x2]; 563 u8 reserved_at_c2[0xe]; 564 u8 ipv4_ihl[0x4]; 565 u8 reserved_at_c4[0x4]; 566 567 u8 ttl_hoplimit[0x8]; 568 569 u8 udp_sport[0x10]; 570 u8 udp_dport[0x10]; 571 572 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6; 573 574 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6; 575 }; 576 577 struct mlx5_ifc_nvgre_key_bits { 578 u8 hi[0x18]; 579 u8 lo[0x8]; 580 }; 581 582 union mlx5_ifc_gre_key_bits { 583 struct mlx5_ifc_nvgre_key_bits nvgre; 584 u8 key[0x20]; 585 }; 586 587 struct mlx5_ifc_fte_match_set_misc_bits { 588 u8 gre_c_present[0x1]; 589 u8 reserved_at_1[0x1]; 590 u8 gre_k_present[0x1]; 591 u8 gre_s_present[0x1]; 592 u8 source_vhca_port[0x4]; 593 u8 source_sqn[0x18]; 594 595 u8 source_eswitch_owner_vhca_id[0x10]; 596 u8 source_port[0x10]; 597 598 u8 outer_second_prio[0x3]; 599 u8 outer_second_cfi[0x1]; 600 u8 outer_second_vid[0xc]; 601 u8 inner_second_prio[0x3]; 602 u8 inner_second_cfi[0x1]; 603 u8 inner_second_vid[0xc]; 604 605 u8 outer_second_cvlan_tag[0x1]; 606 u8 inner_second_cvlan_tag[0x1]; 607 u8 outer_second_svlan_tag[0x1]; 608 u8 inner_second_svlan_tag[0x1]; 609 u8 reserved_at_64[0xc]; 610 u8 gre_protocol[0x10]; 611 612 union mlx5_ifc_gre_key_bits gre_key; 613 614 u8 vxlan_vni[0x18]; 615 u8 bth_opcode[0x8]; 616 617 u8 geneve_vni[0x18]; 618 u8 reserved_at_d8[0x6]; 619 u8 geneve_tlv_option_0_exist[0x1]; 620 u8 geneve_oam[0x1]; 621 622 u8 reserved_at_e0[0xc]; 623 u8 outer_ipv6_flow_label[0x14]; 624 625 u8 reserved_at_100[0xc]; 626 u8 inner_ipv6_flow_label[0x14]; 627 628 u8 reserved_at_120[0xa]; 629 u8 geneve_opt_len[0x6]; 630 u8 geneve_protocol_type[0x10]; 631 632 u8 reserved_at_140[0x8]; 633 u8 bth_dst_qp[0x18]; 634 u8 inner_esp_spi[0x20]; 635 u8 outer_esp_spi[0x20]; 636 u8 reserved_at_1a0[0x60]; 637 }; 638 639 struct mlx5_ifc_fte_match_mpls_bits { 640 u8 mpls_label[0x14]; 641 u8 mpls_exp[0x3]; 642 u8 mpls_s_bos[0x1]; 643 u8 mpls_ttl[0x8]; 644 }; 645 646 struct mlx5_ifc_fte_match_set_misc2_bits { 647 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls; 648 649 struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls; 650 651 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre; 652 653 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp; 654 655 u8 metadata_reg_c_7[0x20]; 656 657 u8 metadata_reg_c_6[0x20]; 658 659 u8 metadata_reg_c_5[0x20]; 660 661 u8 metadata_reg_c_4[0x20]; 662 663 u8 metadata_reg_c_3[0x20]; 664 665 u8 metadata_reg_c_2[0x20]; 666 667 u8 metadata_reg_c_1[0x20]; 668 669 u8 metadata_reg_c_0[0x20]; 670 671 u8 metadata_reg_a[0x20]; 672 673 u8 reserved_at_1a0[0x8]; 674 675 u8 macsec_syndrome[0x8]; 676 u8 ipsec_syndrome[0x8]; 677 u8 reserved_at_1b8[0x8]; 678 679 u8 reserved_at_1c0[0x40]; 680 }; 681 682 struct mlx5_ifc_fte_match_set_misc3_bits { 683 u8 inner_tcp_seq_num[0x20]; 684 685 u8 outer_tcp_seq_num[0x20]; 686 687 u8 inner_tcp_ack_num[0x20]; 688 689 u8 outer_tcp_ack_num[0x20]; 690 691 u8 reserved_at_80[0x8]; 692 u8 outer_vxlan_gpe_vni[0x18]; 693 694 u8 outer_vxlan_gpe_next_protocol[0x8]; 695 u8 outer_vxlan_gpe_flags[0x8]; 696 u8 reserved_at_b0[0x10]; 697 698 u8 icmp_header_data[0x20]; 699 700 u8 icmpv6_header_data[0x20]; 701 702 u8 icmp_type[0x8]; 703 u8 icmp_code[0x8]; 704 u8 icmpv6_type[0x8]; 705 u8 icmpv6_code[0x8]; 706 707 u8 geneve_tlv_option_0_data[0x20]; 708 709 u8 gtpu_teid[0x20]; 710 711 u8 gtpu_msg_type[0x8]; 712 u8 gtpu_msg_flags[0x8]; 713 u8 reserved_at_170[0x10]; 714 715 u8 gtpu_dw_2[0x20]; 716 717 u8 gtpu_first_ext_dw_0[0x20]; 718 719 u8 gtpu_dw_0[0x20]; 720 721 u8 reserved_at_1e0[0x20]; 722 }; 723 724 struct mlx5_ifc_fte_match_set_misc4_bits { 725 u8 prog_sample_field_value_0[0x20]; 726 727 u8 prog_sample_field_id_0[0x20]; 728 729 u8 prog_sample_field_value_1[0x20]; 730 731 u8 prog_sample_field_id_1[0x20]; 732 733 u8 prog_sample_field_value_2[0x20]; 734 735 u8 prog_sample_field_id_2[0x20]; 736 737 u8 prog_sample_field_value_3[0x20]; 738 739 u8 prog_sample_field_id_3[0x20]; 740 741 u8 reserved_at_100[0x100]; 742 }; 743 744 struct mlx5_ifc_fte_match_set_misc5_bits { 745 u8 macsec_tag_0[0x20]; 746 747 u8 macsec_tag_1[0x20]; 748 749 u8 macsec_tag_2[0x20]; 750 751 u8 macsec_tag_3[0x20]; 752 753 u8 tunnel_header_0[0x20]; 754 755 u8 tunnel_header_1[0x20]; 756 757 u8 tunnel_header_2[0x20]; 758 759 u8 tunnel_header_3[0x20]; 760 761 u8 reserved_at_100[0x100]; 762 }; 763 764 struct mlx5_ifc_cmd_pas_bits { 765 u8 pa_h[0x20]; 766 767 u8 pa_l[0x14]; 768 u8 reserved_at_34[0xc]; 769 }; 770 771 struct mlx5_ifc_uint64_bits { 772 u8 hi[0x20]; 773 774 u8 lo[0x20]; 775 }; 776 777 enum { 778 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0, 779 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7, 780 MLX5_ADS_STAT_RATE_10GBPS = 0x8, 781 MLX5_ADS_STAT_RATE_30GBPS = 0x9, 782 MLX5_ADS_STAT_RATE_5GBPS = 0xa, 783 MLX5_ADS_STAT_RATE_20GBPS = 0xb, 784 MLX5_ADS_STAT_RATE_40GBPS = 0xc, 785 MLX5_ADS_STAT_RATE_60GBPS = 0xd, 786 MLX5_ADS_STAT_RATE_80GBPS = 0xe, 787 MLX5_ADS_STAT_RATE_120GBPS = 0xf, 788 }; 789 790 struct mlx5_ifc_ads_bits { 791 u8 fl[0x1]; 792 u8 free_ar[0x1]; 793 u8 reserved_at_2[0xe]; 794 u8 pkey_index[0x10]; 795 796 u8 reserved_at_20[0x8]; 797 u8 grh[0x1]; 798 u8 mlid[0x7]; 799 u8 rlid[0x10]; 800 801 u8 ack_timeout[0x5]; 802 u8 reserved_at_45[0x3]; 803 u8 src_addr_index[0x8]; 804 u8 reserved_at_50[0x4]; 805 u8 stat_rate[0x4]; 806 u8 hop_limit[0x8]; 807 808 u8 reserved_at_60[0x4]; 809 u8 tclass[0x8]; 810 u8 flow_label[0x14]; 811 812 u8 rgid_rip[16][0x8]; 813 814 u8 reserved_at_100[0x4]; 815 u8 f_dscp[0x1]; 816 u8 f_ecn[0x1]; 817 u8 reserved_at_106[0x1]; 818 u8 f_eth_prio[0x1]; 819 u8 ecn[0x2]; 820 u8 dscp[0x6]; 821 u8 udp_sport[0x10]; 822 823 u8 dei_cfi[0x1]; 824 u8 eth_prio[0x3]; 825 u8 sl[0x4]; 826 u8 vhca_port_num[0x8]; 827 u8 rmac_47_32[0x10]; 828 829 u8 rmac_31_0[0x20]; 830 }; 831 832 struct mlx5_ifc_flow_table_nic_cap_bits { 833 u8 nic_rx_multi_path_tirs[0x1]; 834 u8 nic_rx_multi_path_tirs_fts[0x1]; 835 u8 allow_sniffer_and_nic_rx_shared_tir[0x1]; 836 u8 reserved_at_3[0x4]; 837 u8 sw_owner_reformat_supported[0x1]; 838 u8 reserved_at_8[0x18]; 839 840 u8 encap_general_header[0x1]; 841 u8 reserved_at_21[0xa]; 842 u8 log_max_packet_reformat_context[0x5]; 843 u8 reserved_at_30[0x6]; 844 u8 max_encap_header_size[0xa]; 845 u8 reserved_at_40[0x1c0]; 846 847 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive; 848 849 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_rdma; 850 851 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer; 852 853 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit; 854 855 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_rdma; 856 857 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer; 858 859 u8 reserved_at_e00[0x600]; 860 861 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_receive; 862 863 u8 reserved_at_1480[0x80]; 864 865 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_receive_rdma; 866 867 u8 reserved_at_1580[0x280]; 868 869 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_transmit_rdma; 870 871 u8 reserved_at_1880[0x780]; 872 873 u8 sw_steering_nic_rx_action_drop_icm_address[0x40]; 874 875 u8 sw_steering_nic_tx_action_drop_icm_address[0x40]; 876 877 u8 sw_steering_nic_tx_action_allow_icm_address[0x40]; 878 879 u8 reserved_at_20c0[0x5f40]; 880 }; 881 882 struct mlx5_ifc_port_selection_cap_bits { 883 u8 reserved_at_0[0x10]; 884 u8 port_select_flow_table[0x1]; 885 u8 reserved_at_11[0x1]; 886 u8 port_select_flow_table_bypass[0x1]; 887 u8 reserved_at_13[0xd]; 888 889 u8 reserved_at_20[0x1e0]; 890 891 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_port_selection; 892 893 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_port_selection; 894 895 u8 reserved_at_480[0x7b80]; 896 }; 897 898 enum { 899 MLX5_FDB_TO_VPORT_REG_C_0 = 0x01, 900 MLX5_FDB_TO_VPORT_REG_C_1 = 0x02, 901 MLX5_FDB_TO_VPORT_REG_C_2 = 0x04, 902 MLX5_FDB_TO_VPORT_REG_C_3 = 0x08, 903 MLX5_FDB_TO_VPORT_REG_C_4 = 0x10, 904 MLX5_FDB_TO_VPORT_REG_C_5 = 0x20, 905 MLX5_FDB_TO_VPORT_REG_C_6 = 0x40, 906 MLX5_FDB_TO_VPORT_REG_C_7 = 0x80, 907 }; 908 909 struct mlx5_ifc_flow_table_eswitch_cap_bits { 910 u8 fdb_to_vport_reg_c_id[0x8]; 911 u8 reserved_at_8[0x5]; 912 u8 fdb_uplink_hairpin[0x1]; 913 u8 fdb_multi_path_any_table_limit_regc[0x1]; 914 u8 reserved_at_f[0x3]; 915 u8 fdb_multi_path_any_table[0x1]; 916 u8 reserved_at_13[0x2]; 917 u8 fdb_modify_header_fwd_to_table[0x1]; 918 u8 fdb_ipv4_ttl_modify[0x1]; 919 u8 flow_source[0x1]; 920 u8 reserved_at_18[0x2]; 921 u8 multi_fdb_encap[0x1]; 922 u8 egress_acl_forward_to_vport[0x1]; 923 u8 fdb_multi_path_to_table[0x1]; 924 u8 reserved_at_1d[0x3]; 925 926 u8 reserved_at_20[0x1e0]; 927 928 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb; 929 930 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress; 931 932 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress; 933 934 u8 reserved_at_800[0xC00]; 935 936 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_esw_fdb; 937 938 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_bitmask_support_2_esw_fdb; 939 940 u8 reserved_at_1500[0x300]; 941 942 u8 sw_steering_fdb_action_drop_icm_address_rx[0x40]; 943 944 u8 sw_steering_fdb_action_drop_icm_address_tx[0x40]; 945 946 u8 sw_steering_uplink_icm_address_rx[0x40]; 947 948 u8 sw_steering_uplink_icm_address_tx[0x40]; 949 950 u8 reserved_at_1900[0x6700]; 951 }; 952 953 enum { 954 MLX5_COUNTER_SOURCE_ESWITCH = 0x0, 955 MLX5_COUNTER_FLOW_ESWITCH = 0x1, 956 }; 957 958 struct mlx5_ifc_e_switch_cap_bits { 959 u8 vport_svlan_strip[0x1]; 960 u8 vport_cvlan_strip[0x1]; 961 u8 vport_svlan_insert[0x1]; 962 u8 vport_cvlan_insert_if_not_exist[0x1]; 963 u8 vport_cvlan_insert_overwrite[0x1]; 964 u8 reserved_at_5[0x1]; 965 u8 vport_cvlan_insert_always[0x1]; 966 u8 esw_shared_ingress_acl[0x1]; 967 u8 esw_uplink_ingress_acl[0x1]; 968 u8 root_ft_on_other_esw[0x1]; 969 u8 reserved_at_a[0xf]; 970 u8 esw_functions_changed[0x1]; 971 u8 reserved_at_1a[0x1]; 972 u8 ecpf_vport_exists[0x1]; 973 u8 counter_eswitch_affinity[0x1]; 974 u8 merged_eswitch[0x1]; 975 u8 nic_vport_node_guid_modify[0x1]; 976 u8 nic_vport_port_guid_modify[0x1]; 977 978 u8 vxlan_encap_decap[0x1]; 979 u8 nvgre_encap_decap[0x1]; 980 u8 reserved_at_22[0x1]; 981 u8 log_max_fdb_encap_uplink[0x5]; 982 u8 reserved_at_21[0x3]; 983 u8 log_max_packet_reformat_context[0x5]; 984 u8 reserved_2b[0x6]; 985 u8 max_encap_header_size[0xa]; 986 987 u8 reserved_at_40[0xb]; 988 u8 log_max_esw_sf[0x5]; 989 u8 esw_sf_base_id[0x10]; 990 991 u8 reserved_at_60[0x7a0]; 992 993 }; 994 995 struct mlx5_ifc_qos_cap_bits { 996 u8 packet_pacing[0x1]; 997 u8 esw_scheduling[0x1]; 998 u8 esw_bw_share[0x1]; 999 u8 esw_rate_limit[0x1]; 1000 u8 reserved_at_4[0x1]; 1001 u8 packet_pacing_burst_bound[0x1]; 1002 u8 packet_pacing_typical_size[0x1]; 1003 u8 reserved_at_7[0x1]; 1004 u8 nic_sq_scheduling[0x1]; 1005 u8 nic_bw_share[0x1]; 1006 u8 nic_rate_limit[0x1]; 1007 u8 packet_pacing_uid[0x1]; 1008 u8 log_esw_max_sched_depth[0x4]; 1009 u8 reserved_at_10[0x10]; 1010 1011 u8 reserved_at_20[0xb]; 1012 u8 log_max_qos_nic_queue_group[0x5]; 1013 u8 reserved_at_30[0x10]; 1014 1015 u8 packet_pacing_max_rate[0x20]; 1016 1017 u8 packet_pacing_min_rate[0x20]; 1018 1019 u8 reserved_at_80[0x10]; 1020 u8 packet_pacing_rate_table_size[0x10]; 1021 1022 u8 esw_element_type[0x10]; 1023 u8 esw_tsar_type[0x10]; 1024 1025 u8 reserved_at_c0[0x10]; 1026 u8 max_qos_para_vport[0x10]; 1027 1028 u8 max_tsar_bw_share[0x20]; 1029 1030 u8 reserved_at_100[0x20]; 1031 1032 u8 reserved_at_120[0x3]; 1033 u8 log_meter_aso_granularity[0x5]; 1034 u8 reserved_at_128[0x3]; 1035 u8 log_meter_aso_max_alloc[0x5]; 1036 u8 reserved_at_130[0x3]; 1037 u8 log_max_num_meter_aso[0x5]; 1038 u8 reserved_at_138[0x8]; 1039 1040 u8 reserved_at_140[0x6c0]; 1041 }; 1042 1043 struct mlx5_ifc_debug_cap_bits { 1044 u8 core_dump_general[0x1]; 1045 u8 core_dump_qp[0x1]; 1046 u8 reserved_at_2[0x7]; 1047 u8 resource_dump[0x1]; 1048 u8 reserved_at_a[0x16]; 1049 1050 u8 reserved_at_20[0x2]; 1051 u8 stall_detect[0x1]; 1052 u8 reserved_at_23[0x1d]; 1053 1054 u8 reserved_at_40[0x7c0]; 1055 }; 1056 1057 struct mlx5_ifc_per_protocol_networking_offload_caps_bits { 1058 u8 csum_cap[0x1]; 1059 u8 vlan_cap[0x1]; 1060 u8 lro_cap[0x1]; 1061 u8 lro_psh_flag[0x1]; 1062 u8 lro_time_stamp[0x1]; 1063 u8 reserved_at_5[0x2]; 1064 u8 wqe_vlan_insert[0x1]; 1065 u8 self_lb_en_modifiable[0x1]; 1066 u8 reserved_at_9[0x2]; 1067 u8 max_lso_cap[0x5]; 1068 u8 multi_pkt_send_wqe[0x2]; 1069 u8 wqe_inline_mode[0x2]; 1070 u8 rss_ind_tbl_cap[0x4]; 1071 u8 reg_umr_sq[0x1]; 1072 u8 scatter_fcs[0x1]; 1073 u8 enhanced_multi_pkt_send_wqe[0x1]; 1074 u8 tunnel_lso_const_out_ip_id[0x1]; 1075 u8 tunnel_lro_gre[0x1]; 1076 u8 tunnel_lro_vxlan[0x1]; 1077 u8 tunnel_stateless_gre[0x1]; 1078 u8 tunnel_stateless_vxlan[0x1]; 1079 1080 u8 swp[0x1]; 1081 u8 swp_csum[0x1]; 1082 u8 swp_lso[0x1]; 1083 u8 cqe_checksum_full[0x1]; 1084 u8 tunnel_stateless_geneve_tx[0x1]; 1085 u8 tunnel_stateless_mpls_over_udp[0x1]; 1086 u8 tunnel_stateless_mpls_over_gre[0x1]; 1087 u8 tunnel_stateless_vxlan_gpe[0x1]; 1088 u8 tunnel_stateless_ipv4_over_vxlan[0x1]; 1089 u8 tunnel_stateless_ip_over_ip[0x1]; 1090 u8 insert_trailer[0x1]; 1091 u8 reserved_at_2b[0x1]; 1092 u8 tunnel_stateless_ip_over_ip_rx[0x1]; 1093 u8 tunnel_stateless_ip_over_ip_tx[0x1]; 1094 u8 reserved_at_2e[0x2]; 1095 u8 max_vxlan_udp_ports[0x8]; 1096 u8 swp_csum_l4_partial[0x1]; 1097 u8 reserved_at_39[0x5]; 1098 u8 max_geneve_opt_len[0x1]; 1099 u8 tunnel_stateless_geneve_rx[0x1]; 1100 1101 u8 reserved_at_40[0x10]; 1102 u8 lro_min_mss_size[0x10]; 1103 1104 u8 reserved_at_60[0x120]; 1105 1106 u8 lro_timer_supported_periods[4][0x20]; 1107 1108 u8 reserved_at_200[0x600]; 1109 }; 1110 1111 enum { 1112 MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING = 0x0, 1113 MLX5_TIMESTAMP_FORMAT_CAP_REAL_TIME = 0x1, 1114 MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING_AND_REAL_TIME = 0x2, 1115 }; 1116 1117 struct mlx5_ifc_roce_cap_bits { 1118 u8 roce_apm[0x1]; 1119 u8 reserved_at_1[0x3]; 1120 u8 sw_r_roce_src_udp_port[0x1]; 1121 u8 fl_rc_qp_when_roce_disabled[0x1]; 1122 u8 fl_rc_qp_when_roce_enabled[0x1]; 1123 u8 roce_cc_general[0x1]; 1124 u8 qp_ooo_transmit_default[0x1]; 1125 u8 reserved_at_9[0x15]; 1126 u8 qp_ts_format[0x2]; 1127 1128 u8 reserved_at_20[0x60]; 1129 1130 u8 reserved_at_80[0xc]; 1131 u8 l3_type[0x4]; 1132 u8 reserved_at_90[0x8]; 1133 u8 roce_version[0x8]; 1134 1135 u8 reserved_at_a0[0x10]; 1136 u8 r_roce_dest_udp_port[0x10]; 1137 1138 u8 r_roce_max_src_udp_port[0x10]; 1139 u8 r_roce_min_src_udp_port[0x10]; 1140 1141 u8 reserved_at_e0[0x10]; 1142 u8 roce_address_table_size[0x10]; 1143 1144 u8 reserved_at_100[0x700]; 1145 }; 1146 1147 struct mlx5_ifc_sync_steering_in_bits { 1148 u8 opcode[0x10]; 1149 u8 uid[0x10]; 1150 1151 u8 reserved_at_20[0x10]; 1152 u8 op_mod[0x10]; 1153 1154 u8 reserved_at_40[0xc0]; 1155 }; 1156 1157 struct mlx5_ifc_sync_steering_out_bits { 1158 u8 status[0x8]; 1159 u8 reserved_at_8[0x18]; 1160 1161 u8 syndrome[0x20]; 1162 1163 u8 reserved_at_40[0x40]; 1164 }; 1165 1166 struct mlx5_ifc_sync_crypto_in_bits { 1167 u8 opcode[0x10]; 1168 u8 uid[0x10]; 1169 1170 u8 reserved_at_20[0x10]; 1171 u8 op_mod[0x10]; 1172 1173 u8 reserved_at_40[0x20]; 1174 1175 u8 reserved_at_60[0x10]; 1176 u8 crypto_type[0x10]; 1177 1178 u8 reserved_at_80[0x80]; 1179 }; 1180 1181 struct mlx5_ifc_sync_crypto_out_bits { 1182 u8 status[0x8]; 1183 u8 reserved_at_8[0x18]; 1184 1185 u8 syndrome[0x20]; 1186 1187 u8 reserved_at_40[0x40]; 1188 }; 1189 1190 struct mlx5_ifc_device_mem_cap_bits { 1191 u8 memic[0x1]; 1192 u8 reserved_at_1[0x1f]; 1193 1194 u8 reserved_at_20[0xb]; 1195 u8 log_min_memic_alloc_size[0x5]; 1196 u8 reserved_at_30[0x8]; 1197 u8 log_max_memic_addr_alignment[0x8]; 1198 1199 u8 memic_bar_start_addr[0x40]; 1200 1201 u8 memic_bar_size[0x20]; 1202 1203 u8 max_memic_size[0x20]; 1204 1205 u8 steering_sw_icm_start_address[0x40]; 1206 1207 u8 reserved_at_100[0x8]; 1208 u8 log_header_modify_sw_icm_size[0x8]; 1209 u8 reserved_at_110[0x2]; 1210 u8 log_sw_icm_alloc_granularity[0x6]; 1211 u8 log_steering_sw_icm_size[0x8]; 1212 1213 u8 log_indirect_encap_sw_icm_size[0x8]; 1214 u8 reserved_at_128[0x10]; 1215 u8 log_header_modify_pattern_sw_icm_size[0x8]; 1216 1217 u8 header_modify_sw_icm_start_address[0x40]; 1218 1219 u8 reserved_at_180[0x40]; 1220 1221 u8 header_modify_pattern_sw_icm_start_address[0x40]; 1222 1223 u8 memic_operations[0x20]; 1224 1225 u8 reserved_at_220[0x20]; 1226 1227 u8 indirect_encap_sw_icm_start_address[0x40]; 1228 1229 u8 reserved_at_280[0x580]; 1230 }; 1231 1232 struct mlx5_ifc_device_event_cap_bits { 1233 u8 user_affiliated_events[4][0x40]; 1234 1235 u8 user_unaffiliated_events[4][0x40]; 1236 }; 1237 1238 struct mlx5_ifc_virtio_emulation_cap_bits { 1239 u8 desc_tunnel_offload_type[0x1]; 1240 u8 eth_frame_offload_type[0x1]; 1241 u8 virtio_version_1_0[0x1]; 1242 u8 device_features_bits_mask[0xd]; 1243 u8 event_mode[0x8]; 1244 u8 virtio_queue_type[0x8]; 1245 1246 u8 max_tunnel_desc[0x10]; 1247 u8 reserved_at_30[0x3]; 1248 u8 log_doorbell_stride[0x5]; 1249 u8 reserved_at_38[0x3]; 1250 u8 log_doorbell_bar_size[0x5]; 1251 1252 u8 doorbell_bar_offset[0x40]; 1253 1254 u8 max_emulated_devices[0x8]; 1255 u8 max_num_virtio_queues[0x18]; 1256 1257 u8 reserved_at_a0[0x20]; 1258 1259 u8 reserved_at_c0[0x13]; 1260 u8 desc_group_mkey_supported[0x1]; 1261 u8 freeze_to_rdy_supported[0x1]; 1262 u8 reserved_at_d5[0xb]; 1263 1264 u8 reserved_at_e0[0x20]; 1265 1266 u8 umem_1_buffer_param_a[0x20]; 1267 1268 u8 umem_1_buffer_param_b[0x20]; 1269 1270 u8 umem_2_buffer_param_a[0x20]; 1271 1272 u8 umem_2_buffer_param_b[0x20]; 1273 1274 u8 umem_3_buffer_param_a[0x20]; 1275 1276 u8 umem_3_buffer_param_b[0x20]; 1277 1278 u8 reserved_at_1c0[0x640]; 1279 }; 1280 1281 enum { 1282 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0, 1283 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2, 1284 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4, 1285 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8, 1286 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10, 1287 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20, 1288 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40, 1289 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80, 1290 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100, 1291 }; 1292 1293 enum { 1294 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1, 1295 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2, 1296 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4, 1297 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8, 1298 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10, 1299 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20, 1300 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40, 1301 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80, 1302 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100, 1303 }; 1304 1305 struct mlx5_ifc_atomic_caps_bits { 1306 u8 reserved_at_0[0x40]; 1307 1308 u8 atomic_req_8B_endianness_mode[0x2]; 1309 u8 reserved_at_42[0x4]; 1310 u8 supported_atomic_req_8B_endianness_mode_1[0x1]; 1311 1312 u8 reserved_at_47[0x19]; 1313 1314 u8 reserved_at_60[0x20]; 1315 1316 u8 reserved_at_80[0x10]; 1317 u8 atomic_operations[0x10]; 1318 1319 u8 reserved_at_a0[0x10]; 1320 u8 atomic_size_qp[0x10]; 1321 1322 u8 reserved_at_c0[0x10]; 1323 u8 atomic_size_dc[0x10]; 1324 1325 u8 reserved_at_e0[0x720]; 1326 }; 1327 1328 struct mlx5_ifc_odp_cap_bits { 1329 u8 reserved_at_0[0x40]; 1330 1331 u8 sig[0x1]; 1332 u8 reserved_at_41[0x1f]; 1333 1334 u8 reserved_at_60[0x20]; 1335 1336 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps; 1337 1338 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps; 1339 1340 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps; 1341 1342 struct mlx5_ifc_odp_per_transport_service_cap_bits xrc_odp_caps; 1343 1344 struct mlx5_ifc_odp_per_transport_service_cap_bits dc_odp_caps; 1345 1346 u8 reserved_at_120[0x6E0]; 1347 }; 1348 1349 struct mlx5_ifc_tls_cap_bits { 1350 u8 tls_1_2_aes_gcm_128[0x1]; 1351 u8 tls_1_3_aes_gcm_128[0x1]; 1352 u8 tls_1_2_aes_gcm_256[0x1]; 1353 u8 tls_1_3_aes_gcm_256[0x1]; 1354 u8 reserved_at_4[0x1c]; 1355 1356 u8 reserved_at_20[0x7e0]; 1357 }; 1358 1359 struct mlx5_ifc_ipsec_cap_bits { 1360 u8 ipsec_full_offload[0x1]; 1361 u8 ipsec_crypto_offload[0x1]; 1362 u8 ipsec_esn[0x1]; 1363 u8 ipsec_crypto_esp_aes_gcm_256_encrypt[0x1]; 1364 u8 ipsec_crypto_esp_aes_gcm_128_encrypt[0x1]; 1365 u8 ipsec_crypto_esp_aes_gcm_256_decrypt[0x1]; 1366 u8 ipsec_crypto_esp_aes_gcm_128_decrypt[0x1]; 1367 u8 reserved_at_7[0x4]; 1368 u8 log_max_ipsec_offload[0x5]; 1369 u8 reserved_at_10[0x10]; 1370 1371 u8 min_log_ipsec_full_replay_window[0x8]; 1372 u8 max_log_ipsec_full_replay_window[0x8]; 1373 u8 reserved_at_30[0x7d0]; 1374 }; 1375 1376 struct mlx5_ifc_macsec_cap_bits { 1377 u8 macsec_epn[0x1]; 1378 u8 reserved_at_1[0x2]; 1379 u8 macsec_crypto_esp_aes_gcm_256_encrypt[0x1]; 1380 u8 macsec_crypto_esp_aes_gcm_128_encrypt[0x1]; 1381 u8 macsec_crypto_esp_aes_gcm_256_decrypt[0x1]; 1382 u8 macsec_crypto_esp_aes_gcm_128_decrypt[0x1]; 1383 u8 reserved_at_7[0x4]; 1384 u8 log_max_macsec_offload[0x5]; 1385 u8 reserved_at_10[0x10]; 1386 1387 u8 min_log_macsec_full_replay_window[0x8]; 1388 u8 max_log_macsec_full_replay_window[0x8]; 1389 u8 reserved_at_30[0x10]; 1390 1391 u8 reserved_at_40[0x7c0]; 1392 }; 1393 1394 enum { 1395 MLX5_WQ_TYPE_LINKED_LIST = 0x0, 1396 MLX5_WQ_TYPE_CYCLIC = 0x1, 1397 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2, 1398 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3, 1399 }; 1400 1401 enum { 1402 MLX5_WQ_END_PAD_MODE_NONE = 0x0, 1403 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1, 1404 }; 1405 1406 enum { 1407 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0, 1408 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1, 1409 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2, 1410 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3, 1411 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4, 1412 }; 1413 1414 enum { 1415 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0, 1416 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1, 1417 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2, 1418 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3, 1419 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4, 1420 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5, 1421 }; 1422 1423 enum { 1424 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0, 1425 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1, 1426 }; 1427 1428 enum { 1429 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0, 1430 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1, 1431 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3, 1432 }; 1433 1434 enum { 1435 MLX5_CAP_PORT_TYPE_IB = 0x0, 1436 MLX5_CAP_PORT_TYPE_ETH = 0x1, 1437 }; 1438 1439 enum { 1440 MLX5_CAP_UMR_FENCE_STRONG = 0x0, 1441 MLX5_CAP_UMR_FENCE_SMALL = 0x1, 1442 MLX5_CAP_UMR_FENCE_NONE = 0x2, 1443 }; 1444 1445 enum { 1446 MLX5_FLEX_PARSER_GENEVE_ENABLED = 1 << 3, 1447 MLX5_FLEX_PARSER_MPLS_OVER_GRE_ENABLED = 1 << 4, 1448 MLX5_FLEX_PARSER_MPLS_OVER_UDP_ENABLED = 1 << 5, 1449 MLX5_FLEX_PARSER_VXLAN_GPE_ENABLED = 1 << 7, 1450 MLX5_FLEX_PARSER_ICMP_V4_ENABLED = 1 << 8, 1451 MLX5_FLEX_PARSER_ICMP_V6_ENABLED = 1 << 9, 1452 MLX5_FLEX_PARSER_GENEVE_TLV_OPTION_0_ENABLED = 1 << 10, 1453 MLX5_FLEX_PARSER_GTPU_ENABLED = 1 << 11, 1454 MLX5_FLEX_PARSER_GTPU_DW_2_ENABLED = 1 << 16, 1455 MLX5_FLEX_PARSER_GTPU_FIRST_EXT_DW_0_ENABLED = 1 << 17, 1456 MLX5_FLEX_PARSER_GTPU_DW_0_ENABLED = 1 << 18, 1457 MLX5_FLEX_PARSER_GTPU_TEID_ENABLED = 1 << 19, 1458 }; 1459 1460 enum { 1461 MLX5_UCTX_CAP_RAW_TX = 1UL << 0, 1462 MLX5_UCTX_CAP_INTERNAL_DEV_RES = 1UL << 1, 1463 }; 1464 1465 #define MLX5_FC_BULK_SIZE_FACTOR 128 1466 1467 enum mlx5_fc_bulk_alloc_bitmask { 1468 MLX5_FC_BULK_128 = (1 << 0), 1469 MLX5_FC_BULK_256 = (1 << 1), 1470 MLX5_FC_BULK_512 = (1 << 2), 1471 MLX5_FC_BULK_1024 = (1 << 3), 1472 MLX5_FC_BULK_2048 = (1 << 4), 1473 MLX5_FC_BULK_4096 = (1 << 5), 1474 MLX5_FC_BULK_8192 = (1 << 6), 1475 MLX5_FC_BULK_16384 = (1 << 7), 1476 }; 1477 1478 #define MLX5_FC_BULK_NUM_FCS(fc_enum) (MLX5_FC_BULK_SIZE_FACTOR * (fc_enum)) 1479 1480 #define MLX5_FT_MAX_MULTIPATH_LEVEL 63 1481 1482 enum { 1483 MLX5_STEERING_FORMAT_CONNECTX_5 = 0, 1484 MLX5_STEERING_FORMAT_CONNECTX_6DX = 1, 1485 MLX5_STEERING_FORMAT_CONNECTX_7 = 2, 1486 }; 1487 1488 struct mlx5_ifc_cmd_hca_cap_bits { 1489 u8 reserved_at_0[0x6]; 1490 u8 page_request_disable[0x1]; 1491 u8 reserved_at_7[0x9]; 1492 u8 shared_object_to_user_object_allowed[0x1]; 1493 u8 reserved_at_13[0xe]; 1494 u8 vhca_resource_manager[0x1]; 1495 1496 u8 hca_cap_2[0x1]; 1497 u8 create_lag_when_not_master_up[0x1]; 1498 u8 dtor[0x1]; 1499 u8 event_on_vhca_state_teardown_request[0x1]; 1500 u8 event_on_vhca_state_in_use[0x1]; 1501 u8 event_on_vhca_state_active[0x1]; 1502 u8 event_on_vhca_state_allocated[0x1]; 1503 u8 event_on_vhca_state_invalid[0x1]; 1504 u8 reserved_at_28[0x8]; 1505 u8 vhca_id[0x10]; 1506 1507 u8 reserved_at_40[0x40]; 1508 1509 u8 log_max_srq_sz[0x8]; 1510 u8 log_max_qp_sz[0x8]; 1511 u8 event_cap[0x1]; 1512 u8 reserved_at_91[0x2]; 1513 u8 isolate_vl_tc_new[0x1]; 1514 u8 reserved_at_94[0x4]; 1515 u8 prio_tag_required[0x1]; 1516 u8 reserved_at_99[0x2]; 1517 u8 log_max_qp[0x5]; 1518 1519 u8 reserved_at_a0[0x3]; 1520 u8 ece_support[0x1]; 1521 u8 reserved_at_a4[0x5]; 1522 u8 reg_c_preserve[0x1]; 1523 u8 reserved_at_aa[0x1]; 1524 u8 log_max_srq[0x5]; 1525 u8 reserved_at_b0[0x1]; 1526 u8 uplink_follow[0x1]; 1527 u8 ts_cqe_to_dest_cqn[0x1]; 1528 u8 reserved_at_b3[0x6]; 1529 u8 go_back_n[0x1]; 1530 u8 reserved_at_ba[0x6]; 1531 1532 u8 max_sgl_for_optimized_performance[0x8]; 1533 u8 log_max_cq_sz[0x8]; 1534 u8 relaxed_ordering_write_umr[0x1]; 1535 u8 relaxed_ordering_read_umr[0x1]; 1536 u8 reserved_at_d2[0x7]; 1537 u8 virtio_net_device_emualtion_manager[0x1]; 1538 u8 virtio_blk_device_emualtion_manager[0x1]; 1539 u8 log_max_cq[0x5]; 1540 1541 u8 log_max_eq_sz[0x8]; 1542 u8 relaxed_ordering_write[0x1]; 1543 u8 relaxed_ordering_read_pci_enabled[0x1]; 1544 u8 log_max_mkey[0x6]; 1545 u8 reserved_at_f0[0x6]; 1546 u8 terminate_scatter_list_mkey[0x1]; 1547 u8 repeated_mkey[0x1]; 1548 u8 dump_fill_mkey[0x1]; 1549 u8 reserved_at_f9[0x2]; 1550 u8 fast_teardown[0x1]; 1551 u8 log_max_eq[0x4]; 1552 1553 u8 max_indirection[0x8]; 1554 u8 fixed_buffer_size[0x1]; 1555 u8 log_max_mrw_sz[0x7]; 1556 u8 force_teardown[0x1]; 1557 u8 reserved_at_111[0x1]; 1558 u8 log_max_bsf_list_size[0x6]; 1559 u8 umr_extended_translation_offset[0x1]; 1560 u8 null_mkey[0x1]; 1561 u8 log_max_klm_list_size[0x6]; 1562 1563 u8 reserved_at_120[0x2]; 1564 u8 qpc_extension[0x1]; 1565 u8 reserved_at_123[0x7]; 1566 u8 log_max_ra_req_dc[0x6]; 1567 u8 reserved_at_130[0x2]; 1568 u8 eth_wqe_too_small[0x1]; 1569 u8 reserved_at_133[0x6]; 1570 u8 vnic_env_cq_overrun[0x1]; 1571 u8 log_max_ra_res_dc[0x6]; 1572 1573 u8 reserved_at_140[0x5]; 1574 u8 release_all_pages[0x1]; 1575 u8 must_not_use[0x1]; 1576 u8 reserved_at_147[0x2]; 1577 u8 roce_accl[0x1]; 1578 u8 log_max_ra_req_qp[0x6]; 1579 u8 reserved_at_150[0xa]; 1580 u8 log_max_ra_res_qp[0x6]; 1581 1582 u8 end_pad[0x1]; 1583 u8 cc_query_allowed[0x1]; 1584 u8 cc_modify_allowed[0x1]; 1585 u8 start_pad[0x1]; 1586 u8 cache_line_128byte[0x1]; 1587 u8 reserved_at_165[0x4]; 1588 u8 rts2rts_qp_counters_set_id[0x1]; 1589 u8 reserved_at_16a[0x2]; 1590 u8 vnic_env_int_rq_oob[0x1]; 1591 u8 sbcam_reg[0x1]; 1592 u8 reserved_at_16e[0x1]; 1593 u8 qcam_reg[0x1]; 1594 u8 gid_table_size[0x10]; 1595 1596 u8 out_of_seq_cnt[0x1]; 1597 u8 vport_counters[0x1]; 1598 u8 retransmission_q_counters[0x1]; 1599 u8 debug[0x1]; 1600 u8 modify_rq_counter_set_id[0x1]; 1601 u8 rq_delay_drop[0x1]; 1602 u8 max_qp_cnt[0xa]; 1603 u8 pkey_table_size[0x10]; 1604 1605 u8 vport_group_manager[0x1]; 1606 u8 vhca_group_manager[0x1]; 1607 u8 ib_virt[0x1]; 1608 u8 eth_virt[0x1]; 1609 u8 vnic_env_queue_counters[0x1]; 1610 u8 ets[0x1]; 1611 u8 nic_flow_table[0x1]; 1612 u8 eswitch_manager[0x1]; 1613 u8 device_memory[0x1]; 1614 u8 mcam_reg[0x1]; 1615 u8 pcam_reg[0x1]; 1616 u8 local_ca_ack_delay[0x5]; 1617 u8 port_module_event[0x1]; 1618 u8 enhanced_error_q_counters[0x1]; 1619 u8 ports_check[0x1]; 1620 u8 reserved_at_1b3[0x1]; 1621 u8 disable_link_up[0x1]; 1622 u8 beacon_led[0x1]; 1623 u8 port_type[0x2]; 1624 u8 num_ports[0x8]; 1625 1626 u8 reserved_at_1c0[0x1]; 1627 u8 pps[0x1]; 1628 u8 pps_modify[0x1]; 1629 u8 log_max_msg[0x5]; 1630 u8 reserved_at_1c8[0x4]; 1631 u8 max_tc[0x4]; 1632 u8 temp_warn_event[0x1]; 1633 u8 dcbx[0x1]; 1634 u8 general_notification_event[0x1]; 1635 u8 reserved_at_1d3[0x2]; 1636 u8 fpga[0x1]; 1637 u8 rol_s[0x1]; 1638 u8 rol_g[0x1]; 1639 u8 reserved_at_1d8[0x1]; 1640 u8 wol_s[0x1]; 1641 u8 wol_g[0x1]; 1642 u8 wol_a[0x1]; 1643 u8 wol_b[0x1]; 1644 u8 wol_m[0x1]; 1645 u8 wol_u[0x1]; 1646 u8 wol_p[0x1]; 1647 1648 u8 stat_rate_support[0x10]; 1649 u8 reserved_at_1f0[0x1]; 1650 u8 pci_sync_for_fw_update_event[0x1]; 1651 u8 reserved_at_1f2[0x6]; 1652 u8 init2_lag_tx_port_affinity[0x1]; 1653 u8 reserved_at_1fa[0x3]; 1654 u8 cqe_version[0x4]; 1655 1656 u8 compact_address_vector[0x1]; 1657 u8 striding_rq[0x1]; 1658 u8 reserved_at_202[0x1]; 1659 u8 ipoib_enhanced_offloads[0x1]; 1660 u8 ipoib_basic_offloads[0x1]; 1661 u8 reserved_at_205[0x1]; 1662 u8 repeated_block_disabled[0x1]; 1663 u8 umr_modify_entity_size_disabled[0x1]; 1664 u8 umr_modify_atomic_disabled[0x1]; 1665 u8 umr_indirect_mkey_disabled[0x1]; 1666 u8 umr_fence[0x2]; 1667 u8 dc_req_scat_data_cqe[0x1]; 1668 u8 reserved_at_20d[0x2]; 1669 u8 drain_sigerr[0x1]; 1670 u8 cmdif_checksum[0x2]; 1671 u8 sigerr_cqe[0x1]; 1672 u8 reserved_at_213[0x1]; 1673 u8 wq_signature[0x1]; 1674 u8 sctr_data_cqe[0x1]; 1675 u8 reserved_at_216[0x1]; 1676 u8 sho[0x1]; 1677 u8 tph[0x1]; 1678 u8 rf[0x1]; 1679 u8 dct[0x1]; 1680 u8 qos[0x1]; 1681 u8 eth_net_offloads[0x1]; 1682 u8 roce[0x1]; 1683 u8 atomic[0x1]; 1684 u8 reserved_at_21f[0x1]; 1685 1686 u8 cq_oi[0x1]; 1687 u8 cq_resize[0x1]; 1688 u8 cq_moderation[0x1]; 1689 u8 cq_period_mode_modify[0x1]; 1690 u8 reserved_at_224[0x2]; 1691 u8 cq_eq_remap[0x1]; 1692 u8 pg[0x1]; 1693 u8 block_lb_mc[0x1]; 1694 u8 reserved_at_229[0x1]; 1695 u8 scqe_break_moderation[0x1]; 1696 u8 cq_period_start_from_cqe[0x1]; 1697 u8 cd[0x1]; 1698 u8 reserved_at_22d[0x1]; 1699 u8 apm[0x1]; 1700 u8 vector_calc[0x1]; 1701 u8 umr_ptr_rlky[0x1]; 1702 u8 imaicl[0x1]; 1703 u8 qp_packet_based[0x1]; 1704 u8 reserved_at_233[0x3]; 1705 u8 qkv[0x1]; 1706 u8 pkv[0x1]; 1707 u8 set_deth_sqpn[0x1]; 1708 u8 reserved_at_239[0x3]; 1709 u8 xrc[0x1]; 1710 u8 ud[0x1]; 1711 u8 uc[0x1]; 1712 u8 rc[0x1]; 1713 1714 u8 uar_4k[0x1]; 1715 u8 reserved_at_241[0x7]; 1716 u8 fl_rc_qp_when_roce_disabled[0x1]; 1717 u8 regexp_params[0x1]; 1718 u8 uar_sz[0x6]; 1719 u8 port_selection_cap[0x1]; 1720 u8 reserved_at_251[0x1]; 1721 u8 umem_uid_0[0x1]; 1722 u8 reserved_at_253[0x5]; 1723 u8 log_pg_sz[0x8]; 1724 1725 u8 bf[0x1]; 1726 u8 driver_version[0x1]; 1727 u8 pad_tx_eth_packet[0x1]; 1728 u8 reserved_at_263[0x3]; 1729 u8 mkey_by_name[0x1]; 1730 u8 reserved_at_267[0x4]; 1731 1732 u8 log_bf_reg_size[0x5]; 1733 1734 u8 reserved_at_270[0x3]; 1735 u8 qp_error_syndrome[0x1]; 1736 u8 reserved_at_274[0x2]; 1737 u8 lag_dct[0x2]; 1738 u8 lag_tx_port_affinity[0x1]; 1739 u8 lag_native_fdb_selection[0x1]; 1740 u8 reserved_at_27a[0x1]; 1741 u8 lag_master[0x1]; 1742 u8 num_lag_ports[0x4]; 1743 1744 u8 reserved_at_280[0x10]; 1745 u8 max_wqe_sz_sq[0x10]; 1746 1747 u8 reserved_at_2a0[0xb]; 1748 u8 shampo[0x1]; 1749 u8 reserved_at_2ac[0x4]; 1750 u8 max_wqe_sz_rq[0x10]; 1751 1752 u8 max_flow_counter_31_16[0x10]; 1753 u8 max_wqe_sz_sq_dc[0x10]; 1754 1755 u8 reserved_at_2e0[0x7]; 1756 u8 max_qp_mcg[0x19]; 1757 1758 u8 reserved_at_300[0x10]; 1759 u8 flow_counter_bulk_alloc[0x8]; 1760 u8 log_max_mcg[0x8]; 1761 1762 u8 reserved_at_320[0x3]; 1763 u8 log_max_transport_domain[0x5]; 1764 u8 reserved_at_328[0x2]; 1765 u8 relaxed_ordering_read[0x1]; 1766 u8 log_max_pd[0x5]; 1767 u8 reserved_at_330[0x6]; 1768 u8 pci_sync_for_fw_update_with_driver_unload[0x1]; 1769 u8 vnic_env_cnt_steering_fail[0x1]; 1770 u8 vport_counter_local_loopback[0x1]; 1771 u8 q_counter_aggregation[0x1]; 1772 u8 q_counter_other_vport[0x1]; 1773 u8 log_max_xrcd[0x5]; 1774 1775 u8 nic_receive_steering_discard[0x1]; 1776 u8 receive_discard_vport_down[0x1]; 1777 u8 transmit_discard_vport_down[0x1]; 1778 u8 eq_overrun_count[0x1]; 1779 u8 reserved_at_344[0x1]; 1780 u8 invalid_command_count[0x1]; 1781 u8 quota_exceeded_count[0x1]; 1782 u8 reserved_at_347[0x1]; 1783 u8 log_max_flow_counter_bulk[0x8]; 1784 u8 max_flow_counter_15_0[0x10]; 1785 1786 1787 u8 reserved_at_360[0x3]; 1788 u8 log_max_rq[0x5]; 1789 u8 reserved_at_368[0x3]; 1790 u8 log_max_sq[0x5]; 1791 u8 reserved_at_370[0x3]; 1792 u8 log_max_tir[0x5]; 1793 u8 reserved_at_378[0x3]; 1794 u8 log_max_tis[0x5]; 1795 1796 u8 basic_cyclic_rcv_wqe[0x1]; 1797 u8 reserved_at_381[0x2]; 1798 u8 log_max_rmp[0x5]; 1799 u8 reserved_at_388[0x3]; 1800 u8 log_max_rqt[0x5]; 1801 u8 reserved_at_390[0x3]; 1802 u8 log_max_rqt_size[0x5]; 1803 u8 reserved_at_398[0x3]; 1804 u8 log_max_tis_per_sq[0x5]; 1805 1806 u8 ext_stride_num_range[0x1]; 1807 u8 roce_rw_supported[0x1]; 1808 u8 log_max_current_uc_list_wr_supported[0x1]; 1809 u8 log_max_stride_sz_rq[0x5]; 1810 u8 reserved_at_3a8[0x3]; 1811 u8 log_min_stride_sz_rq[0x5]; 1812 u8 reserved_at_3b0[0x3]; 1813 u8 log_max_stride_sz_sq[0x5]; 1814 u8 reserved_at_3b8[0x3]; 1815 u8 log_min_stride_sz_sq[0x5]; 1816 1817 u8 hairpin[0x1]; 1818 u8 reserved_at_3c1[0x2]; 1819 u8 log_max_hairpin_queues[0x5]; 1820 u8 reserved_at_3c8[0x3]; 1821 u8 log_max_hairpin_wq_data_sz[0x5]; 1822 u8 reserved_at_3d0[0x3]; 1823 u8 log_max_hairpin_num_packets[0x5]; 1824 u8 reserved_at_3d8[0x3]; 1825 u8 log_max_wq_sz[0x5]; 1826 1827 u8 nic_vport_change_event[0x1]; 1828 u8 disable_local_lb_uc[0x1]; 1829 u8 disable_local_lb_mc[0x1]; 1830 u8 log_min_hairpin_wq_data_sz[0x5]; 1831 u8 reserved_at_3e8[0x1]; 1832 u8 silent_mode[0x1]; 1833 u8 vhca_state[0x1]; 1834 u8 log_max_vlan_list[0x5]; 1835 u8 reserved_at_3f0[0x3]; 1836 u8 log_max_current_mc_list[0x5]; 1837 u8 reserved_at_3f8[0x3]; 1838 u8 log_max_current_uc_list[0x5]; 1839 1840 u8 general_obj_types[0x40]; 1841 1842 u8 sq_ts_format[0x2]; 1843 u8 rq_ts_format[0x2]; 1844 u8 steering_format_version[0x4]; 1845 u8 create_qp_start_hint[0x18]; 1846 1847 u8 reserved_at_460[0x1]; 1848 u8 ats[0x1]; 1849 u8 cross_vhca_rqt[0x1]; 1850 u8 log_max_uctx[0x5]; 1851 u8 reserved_at_468[0x1]; 1852 u8 crypto[0x1]; 1853 u8 ipsec_offload[0x1]; 1854 u8 log_max_umem[0x5]; 1855 u8 max_num_eqs[0x10]; 1856 1857 u8 reserved_at_480[0x1]; 1858 u8 tls_tx[0x1]; 1859 u8 tls_rx[0x1]; 1860 u8 log_max_l2_table[0x5]; 1861 u8 reserved_at_488[0x8]; 1862 u8 log_uar_page_sz[0x10]; 1863 1864 u8 reserved_at_4a0[0x20]; 1865 u8 device_frequency_mhz[0x20]; 1866 u8 device_frequency_khz[0x20]; 1867 1868 u8 reserved_at_500[0x20]; 1869 u8 num_of_uars_per_page[0x20]; 1870 1871 u8 flex_parser_protocols[0x20]; 1872 1873 u8 max_geneve_tlv_options[0x8]; 1874 u8 reserved_at_568[0x3]; 1875 u8 max_geneve_tlv_option_data_len[0x5]; 1876 u8 reserved_at_570[0x9]; 1877 u8 adv_virtualization[0x1]; 1878 u8 reserved_at_57a[0x6]; 1879 1880 u8 reserved_at_580[0xb]; 1881 u8 log_max_dci_stream_channels[0x5]; 1882 u8 reserved_at_590[0x3]; 1883 u8 log_max_dci_errored_streams[0x5]; 1884 u8 reserved_at_598[0x8]; 1885 1886 u8 reserved_at_5a0[0x10]; 1887 u8 enhanced_cqe_compression[0x1]; 1888 u8 reserved_at_5b1[0x2]; 1889 u8 log_max_dek[0x5]; 1890 u8 reserved_at_5b8[0x4]; 1891 u8 mini_cqe_resp_stride_index[0x1]; 1892 u8 cqe_128_always[0x1]; 1893 u8 cqe_compression_128[0x1]; 1894 u8 cqe_compression[0x1]; 1895 1896 u8 cqe_compression_timeout[0x10]; 1897 u8 cqe_compression_max_num[0x10]; 1898 1899 u8 reserved_at_5e0[0x8]; 1900 u8 flex_parser_id_gtpu_dw_0[0x4]; 1901 u8 reserved_at_5ec[0x4]; 1902 u8 tag_matching[0x1]; 1903 u8 rndv_offload_rc[0x1]; 1904 u8 rndv_offload_dc[0x1]; 1905 u8 log_tag_matching_list_sz[0x5]; 1906 u8 reserved_at_5f8[0x3]; 1907 u8 log_max_xrq[0x5]; 1908 1909 u8 affiliate_nic_vport_criteria[0x8]; 1910 u8 native_port_num[0x8]; 1911 u8 num_vhca_ports[0x8]; 1912 u8 flex_parser_id_gtpu_teid[0x4]; 1913 u8 reserved_at_61c[0x2]; 1914 u8 sw_owner_id[0x1]; 1915 u8 reserved_at_61f[0x1]; 1916 1917 u8 max_num_of_monitor_counters[0x10]; 1918 u8 num_ppcnt_monitor_counters[0x10]; 1919 1920 u8 max_num_sf[0x10]; 1921 u8 num_q_monitor_counters[0x10]; 1922 1923 u8 reserved_at_660[0x20]; 1924 1925 u8 sf[0x1]; 1926 u8 sf_set_partition[0x1]; 1927 u8 reserved_at_682[0x1]; 1928 u8 log_max_sf[0x5]; 1929 u8 apu[0x1]; 1930 u8 reserved_at_689[0x4]; 1931 u8 migration[0x1]; 1932 u8 reserved_at_68e[0x2]; 1933 u8 log_min_sf_size[0x8]; 1934 u8 max_num_sf_partitions[0x8]; 1935 1936 u8 uctx_cap[0x20]; 1937 1938 u8 reserved_at_6c0[0x4]; 1939 u8 flex_parser_id_geneve_tlv_option_0[0x4]; 1940 u8 flex_parser_id_icmp_dw1[0x4]; 1941 u8 flex_parser_id_icmp_dw0[0x4]; 1942 u8 flex_parser_id_icmpv6_dw1[0x4]; 1943 u8 flex_parser_id_icmpv6_dw0[0x4]; 1944 u8 flex_parser_id_outer_first_mpls_over_gre[0x4]; 1945 u8 flex_parser_id_outer_first_mpls_over_udp_label[0x4]; 1946 1947 u8 max_num_match_definer[0x10]; 1948 u8 sf_base_id[0x10]; 1949 1950 u8 flex_parser_id_gtpu_dw_2[0x4]; 1951 u8 flex_parser_id_gtpu_first_ext_dw_0[0x4]; 1952 u8 num_total_dynamic_vf_msix[0x18]; 1953 u8 reserved_at_720[0x14]; 1954 u8 dynamic_msix_table_size[0xc]; 1955 u8 reserved_at_740[0xc]; 1956 u8 min_dynamic_vf_msix_table_size[0x4]; 1957 u8 reserved_at_750[0x4]; 1958 u8 max_dynamic_vf_msix_table_size[0xc]; 1959 1960 u8 reserved_at_760[0x3]; 1961 u8 log_max_num_header_modify_argument[0x5]; 1962 u8 reserved_at_768[0x4]; 1963 u8 log_header_modify_argument_granularity[0x4]; 1964 u8 reserved_at_770[0x3]; 1965 u8 log_header_modify_argument_max_alloc[0x5]; 1966 u8 reserved_at_778[0x8]; 1967 1968 u8 vhca_tunnel_commands[0x40]; 1969 u8 match_definer_format_supported[0x40]; 1970 }; 1971 1972 enum { 1973 MLX5_CROSS_VHCA_OBJ_TO_OBJ_SUPPORTED_LOCAL_FLOW_TABLE_TO_REMOTE_FLOW_TABLE_MISS = 0x80000, 1974 MLX5_CROSS_VHCA_OBJ_TO_OBJ_SUPPORTED_LOCAL_FLOW_TABLE_ROOT_TO_REMOTE_FLOW_TABLE = (1ULL << 20), 1975 }; 1976 1977 enum { 1978 MLX5_ALLOWED_OBJ_FOR_OTHER_VHCA_ACCESS_FLOW_TABLE = 0x200, 1979 }; 1980 1981 struct mlx5_ifc_cmd_hca_cap_2_bits { 1982 u8 reserved_at_0[0x80]; 1983 1984 u8 migratable[0x1]; 1985 u8 reserved_at_81[0x1f]; 1986 1987 u8 max_reformat_insert_size[0x8]; 1988 u8 max_reformat_insert_offset[0x8]; 1989 u8 max_reformat_remove_size[0x8]; 1990 u8 max_reformat_remove_offset[0x8]; 1991 1992 u8 reserved_at_c0[0x8]; 1993 u8 migration_multi_load[0x1]; 1994 u8 migration_tracking_state[0x1]; 1995 u8 reserved_at_ca[0x6]; 1996 u8 migration_in_chunks[0x1]; 1997 u8 reserved_at_d1[0x1]; 1998 u8 sf_eq_usage[0x1]; 1999 u8 reserved_at_d3[0xd]; 2000 2001 u8 cross_vhca_object_to_object_supported[0x20]; 2002 2003 u8 allowed_object_for_other_vhca_access[0x40]; 2004 2005 u8 reserved_at_140[0x60]; 2006 2007 u8 flow_table_type_2_type[0x8]; 2008 u8 reserved_at_1a8[0x3]; 2009 u8 log_min_mkey_entity_size[0x5]; 2010 u8 reserved_at_1b0[0x10]; 2011 2012 u8 reserved_at_1c0[0x60]; 2013 2014 u8 reserved_at_220[0x1]; 2015 u8 sw_vhca_id_valid[0x1]; 2016 u8 sw_vhca_id[0xe]; 2017 u8 reserved_at_230[0x10]; 2018 2019 u8 reserved_at_240[0xb]; 2020 u8 ts_cqe_metadata_size2wqe_counter[0x5]; 2021 u8 reserved_at_250[0x10]; 2022 2023 u8 reserved_at_260[0x120]; 2024 u8 reserved_at_380[0xb]; 2025 u8 min_mkey_log_entity_size_fixed_buffer[0x5]; 2026 u8 ec_vf_vport_base[0x10]; 2027 2028 u8 reserved_at_3a0[0x10]; 2029 u8 max_rqt_vhca_id[0x10]; 2030 2031 u8 reserved_at_3c0[0x20]; 2032 2033 u8 reserved_at_3e0[0x10]; 2034 u8 pcc_ifa2[0x1]; 2035 u8 reserved_at_3f1[0xf]; 2036 2037 u8 reserved_at_400[0x1]; 2038 u8 min_mkey_log_entity_size_fixed_buffer_valid[0x1]; 2039 u8 reserved_at_402[0x1e]; 2040 2041 u8 reserved_at_420[0x20]; 2042 2043 u8 reserved_at_440[0x8]; 2044 u8 max_num_eqs_24b[0x18]; 2045 u8 reserved_at_460[0x3a0]; 2046 }; 2047 2048 enum mlx5_ifc_flow_destination_type { 2049 MLX5_IFC_FLOW_DESTINATION_TYPE_VPORT = 0x0, 2050 MLX5_IFC_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1, 2051 MLX5_IFC_FLOW_DESTINATION_TYPE_TIR = 0x2, 2052 MLX5_IFC_FLOW_DESTINATION_TYPE_FLOW_SAMPLER = 0x6, 2053 MLX5_IFC_FLOW_DESTINATION_TYPE_UPLINK = 0x8, 2054 MLX5_IFC_FLOW_DESTINATION_TYPE_TABLE_TYPE = 0xA, 2055 }; 2056 2057 enum mlx5_flow_table_miss_action { 2058 MLX5_FLOW_TABLE_MISS_ACTION_DEF, 2059 MLX5_FLOW_TABLE_MISS_ACTION_FWD, 2060 MLX5_FLOW_TABLE_MISS_ACTION_SWITCH_DOMAIN, 2061 }; 2062 2063 struct mlx5_ifc_dest_format_struct_bits { 2064 u8 destination_type[0x8]; 2065 u8 destination_id[0x18]; 2066 2067 u8 destination_eswitch_owner_vhca_id_valid[0x1]; 2068 u8 packet_reformat[0x1]; 2069 u8 reserved_at_22[0x6]; 2070 u8 destination_table_type[0x8]; 2071 u8 destination_eswitch_owner_vhca_id[0x10]; 2072 }; 2073 2074 struct mlx5_ifc_flow_counter_list_bits { 2075 u8 flow_counter_id[0x20]; 2076 2077 u8 reserved_at_20[0x20]; 2078 }; 2079 2080 struct mlx5_ifc_extended_dest_format_bits { 2081 struct mlx5_ifc_dest_format_struct_bits destination_entry; 2082 2083 u8 packet_reformat_id[0x20]; 2084 2085 u8 reserved_at_60[0x20]; 2086 }; 2087 2088 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits { 2089 struct mlx5_ifc_extended_dest_format_bits extended_dest_format; 2090 struct mlx5_ifc_flow_counter_list_bits flow_counter_list; 2091 }; 2092 2093 struct mlx5_ifc_fte_match_param_bits { 2094 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers; 2095 2096 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters; 2097 2098 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers; 2099 2100 struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2; 2101 2102 struct mlx5_ifc_fte_match_set_misc3_bits misc_parameters_3; 2103 2104 struct mlx5_ifc_fte_match_set_misc4_bits misc_parameters_4; 2105 2106 struct mlx5_ifc_fte_match_set_misc5_bits misc_parameters_5; 2107 2108 u8 reserved_at_e00[0x200]; 2109 }; 2110 2111 enum { 2112 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0, 2113 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1, 2114 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2, 2115 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3, 2116 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4, 2117 }; 2118 2119 struct mlx5_ifc_rx_hash_field_select_bits { 2120 u8 l3_prot_type[0x1]; 2121 u8 l4_prot_type[0x1]; 2122 u8 selected_fields[0x1e]; 2123 }; 2124 2125 enum { 2126 MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0, 2127 MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1, 2128 }; 2129 2130 enum { 2131 MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0, 2132 MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1, 2133 }; 2134 2135 struct mlx5_ifc_wq_bits { 2136 u8 wq_type[0x4]; 2137 u8 wq_signature[0x1]; 2138 u8 end_padding_mode[0x2]; 2139 u8 cd_slave[0x1]; 2140 u8 reserved_at_8[0x18]; 2141 2142 u8 hds_skip_first_sge[0x1]; 2143 u8 log2_hds_buf_size[0x3]; 2144 u8 reserved_at_24[0x7]; 2145 u8 page_offset[0x5]; 2146 u8 lwm[0x10]; 2147 2148 u8 reserved_at_40[0x8]; 2149 u8 pd[0x18]; 2150 2151 u8 reserved_at_60[0x8]; 2152 u8 uar_page[0x18]; 2153 2154 u8 dbr_addr[0x40]; 2155 2156 u8 hw_counter[0x20]; 2157 2158 u8 sw_counter[0x20]; 2159 2160 u8 reserved_at_100[0xc]; 2161 u8 log_wq_stride[0x4]; 2162 u8 reserved_at_110[0x3]; 2163 u8 log_wq_pg_sz[0x5]; 2164 u8 reserved_at_118[0x3]; 2165 u8 log_wq_sz[0x5]; 2166 2167 u8 dbr_umem_valid[0x1]; 2168 u8 wq_umem_valid[0x1]; 2169 u8 reserved_at_122[0x1]; 2170 u8 log_hairpin_num_packets[0x5]; 2171 u8 reserved_at_128[0x3]; 2172 u8 log_hairpin_data_sz[0x5]; 2173 2174 u8 reserved_at_130[0x4]; 2175 u8 log_wqe_num_of_strides[0x4]; 2176 u8 two_byte_shift_en[0x1]; 2177 u8 reserved_at_139[0x4]; 2178 u8 log_wqe_stride_size[0x3]; 2179 2180 u8 reserved_at_140[0x80]; 2181 2182 u8 headers_mkey[0x20]; 2183 2184 u8 shampo_enable[0x1]; 2185 u8 reserved_at_1e1[0x4]; 2186 u8 log_reservation_size[0x3]; 2187 u8 reserved_at_1e8[0x5]; 2188 u8 log_max_num_of_packets_per_reservation[0x3]; 2189 u8 reserved_at_1f0[0x6]; 2190 u8 log_headers_entry_size[0x2]; 2191 u8 reserved_at_1f8[0x4]; 2192 u8 log_headers_buffer_entry_num[0x4]; 2193 2194 u8 reserved_at_200[0x400]; 2195 2196 struct mlx5_ifc_cmd_pas_bits pas[]; 2197 }; 2198 2199 struct mlx5_ifc_rq_num_bits { 2200 u8 reserved_at_0[0x8]; 2201 u8 rq_num[0x18]; 2202 }; 2203 2204 struct mlx5_ifc_rq_vhca_bits { 2205 u8 reserved_at_0[0x8]; 2206 u8 rq_num[0x18]; 2207 u8 reserved_at_20[0x10]; 2208 u8 rq_vhca_id[0x10]; 2209 }; 2210 2211 struct mlx5_ifc_mac_address_layout_bits { 2212 u8 reserved_at_0[0x10]; 2213 u8 mac_addr_47_32[0x10]; 2214 2215 u8 mac_addr_31_0[0x20]; 2216 }; 2217 2218 struct mlx5_ifc_vlan_layout_bits { 2219 u8 reserved_at_0[0x14]; 2220 u8 vlan[0x0c]; 2221 2222 u8 reserved_at_20[0x20]; 2223 }; 2224 2225 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits { 2226 u8 reserved_at_0[0xa0]; 2227 2228 u8 min_time_between_cnps[0x20]; 2229 2230 u8 reserved_at_c0[0x12]; 2231 u8 cnp_dscp[0x6]; 2232 u8 reserved_at_d8[0x4]; 2233 u8 cnp_prio_mode[0x1]; 2234 u8 cnp_802p_prio[0x3]; 2235 2236 u8 reserved_at_e0[0x720]; 2237 }; 2238 2239 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits { 2240 u8 reserved_at_0[0x60]; 2241 2242 u8 reserved_at_60[0x4]; 2243 u8 clamp_tgt_rate[0x1]; 2244 u8 reserved_at_65[0x3]; 2245 u8 clamp_tgt_rate_after_time_inc[0x1]; 2246 u8 reserved_at_69[0x17]; 2247 2248 u8 reserved_at_80[0x20]; 2249 2250 u8 rpg_time_reset[0x20]; 2251 2252 u8 rpg_byte_reset[0x20]; 2253 2254 u8 rpg_threshold[0x20]; 2255 2256 u8 rpg_max_rate[0x20]; 2257 2258 u8 rpg_ai_rate[0x20]; 2259 2260 u8 rpg_hai_rate[0x20]; 2261 2262 u8 rpg_gd[0x20]; 2263 2264 u8 rpg_min_dec_fac[0x20]; 2265 2266 u8 rpg_min_rate[0x20]; 2267 2268 u8 reserved_at_1c0[0xe0]; 2269 2270 u8 rate_to_set_on_first_cnp[0x20]; 2271 2272 u8 dce_tcp_g[0x20]; 2273 2274 u8 dce_tcp_rtt[0x20]; 2275 2276 u8 rate_reduce_monitor_period[0x20]; 2277 2278 u8 reserved_at_320[0x20]; 2279 2280 u8 initial_alpha_value[0x20]; 2281 2282 u8 reserved_at_360[0x4a0]; 2283 }; 2284 2285 struct mlx5_ifc_cong_control_r_roce_general_bits { 2286 u8 reserved_at_0[0x80]; 2287 2288 u8 reserved_at_80[0x10]; 2289 u8 rtt_resp_dscp_valid[0x1]; 2290 u8 reserved_at_91[0x9]; 2291 u8 rtt_resp_dscp[0x6]; 2292 2293 u8 reserved_at_a0[0x760]; 2294 }; 2295 2296 struct mlx5_ifc_cong_control_802_1qau_rp_bits { 2297 u8 reserved_at_0[0x80]; 2298 2299 u8 rppp_max_rps[0x20]; 2300 2301 u8 rpg_time_reset[0x20]; 2302 2303 u8 rpg_byte_reset[0x20]; 2304 2305 u8 rpg_threshold[0x20]; 2306 2307 u8 rpg_max_rate[0x20]; 2308 2309 u8 rpg_ai_rate[0x20]; 2310 2311 u8 rpg_hai_rate[0x20]; 2312 2313 u8 rpg_gd[0x20]; 2314 2315 u8 rpg_min_dec_fac[0x20]; 2316 2317 u8 rpg_min_rate[0x20]; 2318 2319 u8 reserved_at_1c0[0x640]; 2320 }; 2321 2322 enum { 2323 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1, 2324 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2, 2325 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4, 2326 }; 2327 2328 struct mlx5_ifc_resize_field_select_bits { 2329 u8 resize_field_select[0x20]; 2330 }; 2331 2332 struct mlx5_ifc_resource_dump_bits { 2333 u8 more_dump[0x1]; 2334 u8 inline_dump[0x1]; 2335 u8 reserved_at_2[0xa]; 2336 u8 seq_num[0x4]; 2337 u8 segment_type[0x10]; 2338 2339 u8 reserved_at_20[0x10]; 2340 u8 vhca_id[0x10]; 2341 2342 u8 index1[0x20]; 2343 2344 u8 index2[0x20]; 2345 2346 u8 num_of_obj1[0x10]; 2347 u8 num_of_obj2[0x10]; 2348 2349 u8 reserved_at_a0[0x20]; 2350 2351 u8 device_opaque[0x40]; 2352 2353 u8 mkey[0x20]; 2354 2355 u8 size[0x20]; 2356 2357 u8 address[0x40]; 2358 2359 u8 inline_data[52][0x20]; 2360 }; 2361 2362 struct mlx5_ifc_resource_dump_menu_record_bits { 2363 u8 reserved_at_0[0x4]; 2364 u8 num_of_obj2_supports_active[0x1]; 2365 u8 num_of_obj2_supports_all[0x1]; 2366 u8 must_have_num_of_obj2[0x1]; 2367 u8 support_num_of_obj2[0x1]; 2368 u8 num_of_obj1_supports_active[0x1]; 2369 u8 num_of_obj1_supports_all[0x1]; 2370 u8 must_have_num_of_obj1[0x1]; 2371 u8 support_num_of_obj1[0x1]; 2372 u8 must_have_index2[0x1]; 2373 u8 support_index2[0x1]; 2374 u8 must_have_index1[0x1]; 2375 u8 support_index1[0x1]; 2376 u8 segment_type[0x10]; 2377 2378 u8 segment_name[4][0x20]; 2379 2380 u8 index1_name[4][0x20]; 2381 2382 u8 index2_name[4][0x20]; 2383 }; 2384 2385 struct mlx5_ifc_resource_dump_segment_header_bits { 2386 u8 length_dw[0x10]; 2387 u8 segment_type[0x10]; 2388 }; 2389 2390 struct mlx5_ifc_resource_dump_command_segment_bits { 2391 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2392 2393 u8 segment_called[0x10]; 2394 u8 vhca_id[0x10]; 2395 2396 u8 index1[0x20]; 2397 2398 u8 index2[0x20]; 2399 2400 u8 num_of_obj1[0x10]; 2401 u8 num_of_obj2[0x10]; 2402 }; 2403 2404 struct mlx5_ifc_resource_dump_error_segment_bits { 2405 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2406 2407 u8 reserved_at_20[0x10]; 2408 u8 syndrome_id[0x10]; 2409 2410 u8 reserved_at_40[0x40]; 2411 2412 u8 error[8][0x20]; 2413 }; 2414 2415 struct mlx5_ifc_resource_dump_info_segment_bits { 2416 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2417 2418 u8 reserved_at_20[0x18]; 2419 u8 dump_version[0x8]; 2420 2421 u8 hw_version[0x20]; 2422 2423 u8 fw_version[0x20]; 2424 }; 2425 2426 struct mlx5_ifc_resource_dump_menu_segment_bits { 2427 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2428 2429 u8 reserved_at_20[0x10]; 2430 u8 num_of_records[0x10]; 2431 2432 struct mlx5_ifc_resource_dump_menu_record_bits record[]; 2433 }; 2434 2435 struct mlx5_ifc_resource_dump_resource_segment_bits { 2436 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2437 2438 u8 reserved_at_20[0x20]; 2439 2440 u8 index1[0x20]; 2441 2442 u8 index2[0x20]; 2443 2444 u8 payload[][0x20]; 2445 }; 2446 2447 struct mlx5_ifc_resource_dump_terminate_segment_bits { 2448 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2449 }; 2450 2451 struct mlx5_ifc_menu_resource_dump_response_bits { 2452 struct mlx5_ifc_resource_dump_info_segment_bits info; 2453 struct mlx5_ifc_resource_dump_command_segment_bits cmd; 2454 struct mlx5_ifc_resource_dump_menu_segment_bits menu; 2455 struct mlx5_ifc_resource_dump_terminate_segment_bits terminate; 2456 }; 2457 2458 enum { 2459 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1, 2460 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2, 2461 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4, 2462 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8, 2463 }; 2464 2465 struct mlx5_ifc_modify_field_select_bits { 2466 u8 modify_field_select[0x20]; 2467 }; 2468 2469 struct mlx5_ifc_field_select_r_roce_np_bits { 2470 u8 field_select_r_roce_np[0x20]; 2471 }; 2472 2473 struct mlx5_ifc_field_select_r_roce_rp_bits { 2474 u8 field_select_r_roce_rp[0x20]; 2475 }; 2476 2477 enum { 2478 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4, 2479 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8, 2480 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10, 2481 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20, 2482 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40, 2483 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80, 2484 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100, 2485 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200, 2486 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400, 2487 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800, 2488 }; 2489 2490 struct mlx5_ifc_field_select_802_1qau_rp_bits { 2491 u8 field_select_8021qaurp[0x20]; 2492 }; 2493 2494 struct mlx5_ifc_phys_layer_cntrs_bits { 2495 u8 time_since_last_clear_high[0x20]; 2496 2497 u8 time_since_last_clear_low[0x20]; 2498 2499 u8 symbol_errors_high[0x20]; 2500 2501 u8 symbol_errors_low[0x20]; 2502 2503 u8 sync_headers_errors_high[0x20]; 2504 2505 u8 sync_headers_errors_low[0x20]; 2506 2507 u8 edpl_bip_errors_lane0_high[0x20]; 2508 2509 u8 edpl_bip_errors_lane0_low[0x20]; 2510 2511 u8 edpl_bip_errors_lane1_high[0x20]; 2512 2513 u8 edpl_bip_errors_lane1_low[0x20]; 2514 2515 u8 edpl_bip_errors_lane2_high[0x20]; 2516 2517 u8 edpl_bip_errors_lane2_low[0x20]; 2518 2519 u8 edpl_bip_errors_lane3_high[0x20]; 2520 2521 u8 edpl_bip_errors_lane3_low[0x20]; 2522 2523 u8 fc_fec_corrected_blocks_lane0_high[0x20]; 2524 2525 u8 fc_fec_corrected_blocks_lane0_low[0x20]; 2526 2527 u8 fc_fec_corrected_blocks_lane1_high[0x20]; 2528 2529 u8 fc_fec_corrected_blocks_lane1_low[0x20]; 2530 2531 u8 fc_fec_corrected_blocks_lane2_high[0x20]; 2532 2533 u8 fc_fec_corrected_blocks_lane2_low[0x20]; 2534 2535 u8 fc_fec_corrected_blocks_lane3_high[0x20]; 2536 2537 u8 fc_fec_corrected_blocks_lane3_low[0x20]; 2538 2539 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20]; 2540 2541 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20]; 2542 2543 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20]; 2544 2545 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20]; 2546 2547 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20]; 2548 2549 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20]; 2550 2551 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20]; 2552 2553 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20]; 2554 2555 u8 rs_fec_corrected_blocks_high[0x20]; 2556 2557 u8 rs_fec_corrected_blocks_low[0x20]; 2558 2559 u8 rs_fec_uncorrectable_blocks_high[0x20]; 2560 2561 u8 rs_fec_uncorrectable_blocks_low[0x20]; 2562 2563 u8 rs_fec_no_errors_blocks_high[0x20]; 2564 2565 u8 rs_fec_no_errors_blocks_low[0x20]; 2566 2567 u8 rs_fec_single_error_blocks_high[0x20]; 2568 2569 u8 rs_fec_single_error_blocks_low[0x20]; 2570 2571 u8 rs_fec_corrected_symbols_total_high[0x20]; 2572 2573 u8 rs_fec_corrected_symbols_total_low[0x20]; 2574 2575 u8 rs_fec_corrected_symbols_lane0_high[0x20]; 2576 2577 u8 rs_fec_corrected_symbols_lane0_low[0x20]; 2578 2579 u8 rs_fec_corrected_symbols_lane1_high[0x20]; 2580 2581 u8 rs_fec_corrected_symbols_lane1_low[0x20]; 2582 2583 u8 rs_fec_corrected_symbols_lane2_high[0x20]; 2584 2585 u8 rs_fec_corrected_symbols_lane2_low[0x20]; 2586 2587 u8 rs_fec_corrected_symbols_lane3_high[0x20]; 2588 2589 u8 rs_fec_corrected_symbols_lane3_low[0x20]; 2590 2591 u8 link_down_events[0x20]; 2592 2593 u8 successful_recovery_events[0x20]; 2594 2595 u8 reserved_at_640[0x180]; 2596 }; 2597 2598 struct mlx5_ifc_phys_layer_statistical_cntrs_bits { 2599 u8 time_since_last_clear_high[0x20]; 2600 2601 u8 time_since_last_clear_low[0x20]; 2602 2603 u8 phy_received_bits_high[0x20]; 2604 2605 u8 phy_received_bits_low[0x20]; 2606 2607 u8 phy_symbol_errors_high[0x20]; 2608 2609 u8 phy_symbol_errors_low[0x20]; 2610 2611 u8 phy_corrected_bits_high[0x20]; 2612 2613 u8 phy_corrected_bits_low[0x20]; 2614 2615 u8 phy_corrected_bits_lane0_high[0x20]; 2616 2617 u8 phy_corrected_bits_lane0_low[0x20]; 2618 2619 u8 phy_corrected_bits_lane1_high[0x20]; 2620 2621 u8 phy_corrected_bits_lane1_low[0x20]; 2622 2623 u8 phy_corrected_bits_lane2_high[0x20]; 2624 2625 u8 phy_corrected_bits_lane2_low[0x20]; 2626 2627 u8 phy_corrected_bits_lane3_high[0x20]; 2628 2629 u8 phy_corrected_bits_lane3_low[0x20]; 2630 2631 u8 reserved_at_200[0x5c0]; 2632 }; 2633 2634 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits { 2635 u8 symbol_error_counter[0x10]; 2636 2637 u8 link_error_recovery_counter[0x8]; 2638 2639 u8 link_downed_counter[0x8]; 2640 2641 u8 port_rcv_errors[0x10]; 2642 2643 u8 port_rcv_remote_physical_errors[0x10]; 2644 2645 u8 port_rcv_switch_relay_errors[0x10]; 2646 2647 u8 port_xmit_discards[0x10]; 2648 2649 u8 port_xmit_constraint_errors[0x8]; 2650 2651 u8 port_rcv_constraint_errors[0x8]; 2652 2653 u8 reserved_at_70[0x8]; 2654 2655 u8 link_overrun_errors[0x8]; 2656 2657 u8 reserved_at_80[0x10]; 2658 2659 u8 vl_15_dropped[0x10]; 2660 2661 u8 reserved_at_a0[0x80]; 2662 2663 u8 port_xmit_wait[0x20]; 2664 }; 2665 2666 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits { 2667 u8 transmit_queue_high[0x20]; 2668 2669 u8 transmit_queue_low[0x20]; 2670 2671 u8 no_buffer_discard_uc_high[0x20]; 2672 2673 u8 no_buffer_discard_uc_low[0x20]; 2674 2675 u8 reserved_at_80[0x740]; 2676 }; 2677 2678 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits { 2679 u8 wred_discard_high[0x20]; 2680 2681 u8 wred_discard_low[0x20]; 2682 2683 u8 ecn_marked_tc_high[0x20]; 2684 2685 u8 ecn_marked_tc_low[0x20]; 2686 2687 u8 reserved_at_80[0x740]; 2688 }; 2689 2690 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits { 2691 u8 rx_octets_high[0x20]; 2692 2693 u8 rx_octets_low[0x20]; 2694 2695 u8 reserved_at_40[0xc0]; 2696 2697 u8 rx_frames_high[0x20]; 2698 2699 u8 rx_frames_low[0x20]; 2700 2701 u8 tx_octets_high[0x20]; 2702 2703 u8 tx_octets_low[0x20]; 2704 2705 u8 reserved_at_180[0xc0]; 2706 2707 u8 tx_frames_high[0x20]; 2708 2709 u8 tx_frames_low[0x20]; 2710 2711 u8 rx_pause_high[0x20]; 2712 2713 u8 rx_pause_low[0x20]; 2714 2715 u8 rx_pause_duration_high[0x20]; 2716 2717 u8 rx_pause_duration_low[0x20]; 2718 2719 u8 tx_pause_high[0x20]; 2720 2721 u8 tx_pause_low[0x20]; 2722 2723 u8 tx_pause_duration_high[0x20]; 2724 2725 u8 tx_pause_duration_low[0x20]; 2726 2727 u8 rx_pause_transition_high[0x20]; 2728 2729 u8 rx_pause_transition_low[0x20]; 2730 2731 u8 rx_discards_high[0x20]; 2732 2733 u8 rx_discards_low[0x20]; 2734 2735 u8 device_stall_minor_watermark_cnt_high[0x20]; 2736 2737 u8 device_stall_minor_watermark_cnt_low[0x20]; 2738 2739 u8 device_stall_critical_watermark_cnt_high[0x20]; 2740 2741 u8 device_stall_critical_watermark_cnt_low[0x20]; 2742 2743 u8 reserved_at_480[0x340]; 2744 }; 2745 2746 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits { 2747 u8 port_transmit_wait_high[0x20]; 2748 2749 u8 port_transmit_wait_low[0x20]; 2750 2751 u8 reserved_at_40[0x100]; 2752 2753 u8 rx_buffer_almost_full_high[0x20]; 2754 2755 u8 rx_buffer_almost_full_low[0x20]; 2756 2757 u8 rx_buffer_full_high[0x20]; 2758 2759 u8 rx_buffer_full_low[0x20]; 2760 2761 u8 rx_icrc_encapsulated_high[0x20]; 2762 2763 u8 rx_icrc_encapsulated_low[0x20]; 2764 2765 u8 reserved_at_200[0x5c0]; 2766 }; 2767 2768 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits { 2769 u8 dot3stats_alignment_errors_high[0x20]; 2770 2771 u8 dot3stats_alignment_errors_low[0x20]; 2772 2773 u8 dot3stats_fcs_errors_high[0x20]; 2774 2775 u8 dot3stats_fcs_errors_low[0x20]; 2776 2777 u8 dot3stats_single_collision_frames_high[0x20]; 2778 2779 u8 dot3stats_single_collision_frames_low[0x20]; 2780 2781 u8 dot3stats_multiple_collision_frames_high[0x20]; 2782 2783 u8 dot3stats_multiple_collision_frames_low[0x20]; 2784 2785 u8 dot3stats_sqe_test_errors_high[0x20]; 2786 2787 u8 dot3stats_sqe_test_errors_low[0x20]; 2788 2789 u8 dot3stats_deferred_transmissions_high[0x20]; 2790 2791 u8 dot3stats_deferred_transmissions_low[0x20]; 2792 2793 u8 dot3stats_late_collisions_high[0x20]; 2794 2795 u8 dot3stats_late_collisions_low[0x20]; 2796 2797 u8 dot3stats_excessive_collisions_high[0x20]; 2798 2799 u8 dot3stats_excessive_collisions_low[0x20]; 2800 2801 u8 dot3stats_internal_mac_transmit_errors_high[0x20]; 2802 2803 u8 dot3stats_internal_mac_transmit_errors_low[0x20]; 2804 2805 u8 dot3stats_carrier_sense_errors_high[0x20]; 2806 2807 u8 dot3stats_carrier_sense_errors_low[0x20]; 2808 2809 u8 dot3stats_frame_too_longs_high[0x20]; 2810 2811 u8 dot3stats_frame_too_longs_low[0x20]; 2812 2813 u8 dot3stats_internal_mac_receive_errors_high[0x20]; 2814 2815 u8 dot3stats_internal_mac_receive_errors_low[0x20]; 2816 2817 u8 dot3stats_symbol_errors_high[0x20]; 2818 2819 u8 dot3stats_symbol_errors_low[0x20]; 2820 2821 u8 dot3control_in_unknown_opcodes_high[0x20]; 2822 2823 u8 dot3control_in_unknown_opcodes_low[0x20]; 2824 2825 u8 dot3in_pause_frames_high[0x20]; 2826 2827 u8 dot3in_pause_frames_low[0x20]; 2828 2829 u8 dot3out_pause_frames_high[0x20]; 2830 2831 u8 dot3out_pause_frames_low[0x20]; 2832 2833 u8 reserved_at_400[0x3c0]; 2834 }; 2835 2836 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits { 2837 u8 ether_stats_drop_events_high[0x20]; 2838 2839 u8 ether_stats_drop_events_low[0x20]; 2840 2841 u8 ether_stats_octets_high[0x20]; 2842 2843 u8 ether_stats_octets_low[0x20]; 2844 2845 u8 ether_stats_pkts_high[0x20]; 2846 2847 u8 ether_stats_pkts_low[0x20]; 2848 2849 u8 ether_stats_broadcast_pkts_high[0x20]; 2850 2851 u8 ether_stats_broadcast_pkts_low[0x20]; 2852 2853 u8 ether_stats_multicast_pkts_high[0x20]; 2854 2855 u8 ether_stats_multicast_pkts_low[0x20]; 2856 2857 u8 ether_stats_crc_align_errors_high[0x20]; 2858 2859 u8 ether_stats_crc_align_errors_low[0x20]; 2860 2861 u8 ether_stats_undersize_pkts_high[0x20]; 2862 2863 u8 ether_stats_undersize_pkts_low[0x20]; 2864 2865 u8 ether_stats_oversize_pkts_high[0x20]; 2866 2867 u8 ether_stats_oversize_pkts_low[0x20]; 2868 2869 u8 ether_stats_fragments_high[0x20]; 2870 2871 u8 ether_stats_fragments_low[0x20]; 2872 2873 u8 ether_stats_jabbers_high[0x20]; 2874 2875 u8 ether_stats_jabbers_low[0x20]; 2876 2877 u8 ether_stats_collisions_high[0x20]; 2878 2879 u8 ether_stats_collisions_low[0x20]; 2880 2881 u8 ether_stats_pkts64octets_high[0x20]; 2882 2883 u8 ether_stats_pkts64octets_low[0x20]; 2884 2885 u8 ether_stats_pkts65to127octets_high[0x20]; 2886 2887 u8 ether_stats_pkts65to127octets_low[0x20]; 2888 2889 u8 ether_stats_pkts128to255octets_high[0x20]; 2890 2891 u8 ether_stats_pkts128to255octets_low[0x20]; 2892 2893 u8 ether_stats_pkts256to511octets_high[0x20]; 2894 2895 u8 ether_stats_pkts256to511octets_low[0x20]; 2896 2897 u8 ether_stats_pkts512to1023octets_high[0x20]; 2898 2899 u8 ether_stats_pkts512to1023octets_low[0x20]; 2900 2901 u8 ether_stats_pkts1024to1518octets_high[0x20]; 2902 2903 u8 ether_stats_pkts1024to1518octets_low[0x20]; 2904 2905 u8 ether_stats_pkts1519to2047octets_high[0x20]; 2906 2907 u8 ether_stats_pkts1519to2047octets_low[0x20]; 2908 2909 u8 ether_stats_pkts2048to4095octets_high[0x20]; 2910 2911 u8 ether_stats_pkts2048to4095octets_low[0x20]; 2912 2913 u8 ether_stats_pkts4096to8191octets_high[0x20]; 2914 2915 u8 ether_stats_pkts4096to8191octets_low[0x20]; 2916 2917 u8 ether_stats_pkts8192to10239octets_high[0x20]; 2918 2919 u8 ether_stats_pkts8192to10239octets_low[0x20]; 2920 2921 u8 reserved_at_540[0x280]; 2922 }; 2923 2924 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits { 2925 u8 if_in_octets_high[0x20]; 2926 2927 u8 if_in_octets_low[0x20]; 2928 2929 u8 if_in_ucast_pkts_high[0x20]; 2930 2931 u8 if_in_ucast_pkts_low[0x20]; 2932 2933 u8 if_in_discards_high[0x20]; 2934 2935 u8 if_in_discards_low[0x20]; 2936 2937 u8 if_in_errors_high[0x20]; 2938 2939 u8 if_in_errors_low[0x20]; 2940 2941 u8 if_in_unknown_protos_high[0x20]; 2942 2943 u8 if_in_unknown_protos_low[0x20]; 2944 2945 u8 if_out_octets_high[0x20]; 2946 2947 u8 if_out_octets_low[0x20]; 2948 2949 u8 if_out_ucast_pkts_high[0x20]; 2950 2951 u8 if_out_ucast_pkts_low[0x20]; 2952 2953 u8 if_out_discards_high[0x20]; 2954 2955 u8 if_out_discards_low[0x20]; 2956 2957 u8 if_out_errors_high[0x20]; 2958 2959 u8 if_out_errors_low[0x20]; 2960 2961 u8 if_in_multicast_pkts_high[0x20]; 2962 2963 u8 if_in_multicast_pkts_low[0x20]; 2964 2965 u8 if_in_broadcast_pkts_high[0x20]; 2966 2967 u8 if_in_broadcast_pkts_low[0x20]; 2968 2969 u8 if_out_multicast_pkts_high[0x20]; 2970 2971 u8 if_out_multicast_pkts_low[0x20]; 2972 2973 u8 if_out_broadcast_pkts_high[0x20]; 2974 2975 u8 if_out_broadcast_pkts_low[0x20]; 2976 2977 u8 reserved_at_340[0x480]; 2978 }; 2979 2980 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits { 2981 u8 a_frames_transmitted_ok_high[0x20]; 2982 2983 u8 a_frames_transmitted_ok_low[0x20]; 2984 2985 u8 a_frames_received_ok_high[0x20]; 2986 2987 u8 a_frames_received_ok_low[0x20]; 2988 2989 u8 a_frame_check_sequence_errors_high[0x20]; 2990 2991 u8 a_frame_check_sequence_errors_low[0x20]; 2992 2993 u8 a_alignment_errors_high[0x20]; 2994 2995 u8 a_alignment_errors_low[0x20]; 2996 2997 u8 a_octets_transmitted_ok_high[0x20]; 2998 2999 u8 a_octets_transmitted_ok_low[0x20]; 3000 3001 u8 a_octets_received_ok_high[0x20]; 3002 3003 u8 a_octets_received_ok_low[0x20]; 3004 3005 u8 a_multicast_frames_xmitted_ok_high[0x20]; 3006 3007 u8 a_multicast_frames_xmitted_ok_low[0x20]; 3008 3009 u8 a_broadcast_frames_xmitted_ok_high[0x20]; 3010 3011 u8 a_broadcast_frames_xmitted_ok_low[0x20]; 3012 3013 u8 a_multicast_frames_received_ok_high[0x20]; 3014 3015 u8 a_multicast_frames_received_ok_low[0x20]; 3016 3017 u8 a_broadcast_frames_received_ok_high[0x20]; 3018 3019 u8 a_broadcast_frames_received_ok_low[0x20]; 3020 3021 u8 a_in_range_length_errors_high[0x20]; 3022 3023 u8 a_in_range_length_errors_low[0x20]; 3024 3025 u8 a_out_of_range_length_field_high[0x20]; 3026 3027 u8 a_out_of_range_length_field_low[0x20]; 3028 3029 u8 a_frame_too_long_errors_high[0x20]; 3030 3031 u8 a_frame_too_long_errors_low[0x20]; 3032 3033 u8 a_symbol_error_during_carrier_high[0x20]; 3034 3035 u8 a_symbol_error_during_carrier_low[0x20]; 3036 3037 u8 a_mac_control_frames_transmitted_high[0x20]; 3038 3039 u8 a_mac_control_frames_transmitted_low[0x20]; 3040 3041 u8 a_mac_control_frames_received_high[0x20]; 3042 3043 u8 a_mac_control_frames_received_low[0x20]; 3044 3045 u8 a_unsupported_opcodes_received_high[0x20]; 3046 3047 u8 a_unsupported_opcodes_received_low[0x20]; 3048 3049 u8 a_pause_mac_ctrl_frames_received_high[0x20]; 3050 3051 u8 a_pause_mac_ctrl_frames_received_low[0x20]; 3052 3053 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20]; 3054 3055 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20]; 3056 3057 u8 reserved_at_4c0[0x300]; 3058 }; 3059 3060 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits { 3061 u8 life_time_counter_high[0x20]; 3062 3063 u8 life_time_counter_low[0x20]; 3064 3065 u8 rx_errors[0x20]; 3066 3067 u8 tx_errors[0x20]; 3068 3069 u8 l0_to_recovery_eieos[0x20]; 3070 3071 u8 l0_to_recovery_ts[0x20]; 3072 3073 u8 l0_to_recovery_framing[0x20]; 3074 3075 u8 l0_to_recovery_retrain[0x20]; 3076 3077 u8 crc_error_dllp[0x20]; 3078 3079 u8 crc_error_tlp[0x20]; 3080 3081 u8 tx_overflow_buffer_pkt_high[0x20]; 3082 3083 u8 tx_overflow_buffer_pkt_low[0x20]; 3084 3085 u8 outbound_stalled_reads[0x20]; 3086 3087 u8 outbound_stalled_writes[0x20]; 3088 3089 u8 outbound_stalled_reads_events[0x20]; 3090 3091 u8 outbound_stalled_writes_events[0x20]; 3092 3093 u8 reserved_at_200[0x5c0]; 3094 }; 3095 3096 struct mlx5_ifc_cmd_inter_comp_event_bits { 3097 u8 command_completion_vector[0x20]; 3098 3099 u8 reserved_at_20[0xc0]; 3100 }; 3101 3102 struct mlx5_ifc_stall_vl_event_bits { 3103 u8 reserved_at_0[0x18]; 3104 u8 port_num[0x1]; 3105 u8 reserved_at_19[0x3]; 3106 u8 vl[0x4]; 3107 3108 u8 reserved_at_20[0xa0]; 3109 }; 3110 3111 struct mlx5_ifc_db_bf_congestion_event_bits { 3112 u8 event_subtype[0x8]; 3113 u8 reserved_at_8[0x8]; 3114 u8 congestion_level[0x8]; 3115 u8 reserved_at_18[0x8]; 3116 3117 u8 reserved_at_20[0xa0]; 3118 }; 3119 3120 struct mlx5_ifc_gpio_event_bits { 3121 u8 reserved_at_0[0x60]; 3122 3123 u8 gpio_event_hi[0x20]; 3124 3125 u8 gpio_event_lo[0x20]; 3126 3127 u8 reserved_at_a0[0x40]; 3128 }; 3129 3130 struct mlx5_ifc_port_state_change_event_bits { 3131 u8 reserved_at_0[0x40]; 3132 3133 u8 port_num[0x4]; 3134 u8 reserved_at_44[0x1c]; 3135 3136 u8 reserved_at_60[0x80]; 3137 }; 3138 3139 struct mlx5_ifc_dropped_packet_logged_bits { 3140 u8 reserved_at_0[0xe0]; 3141 }; 3142 3143 struct mlx5_ifc_default_timeout_bits { 3144 u8 to_multiplier[0x3]; 3145 u8 reserved_at_3[0x9]; 3146 u8 to_value[0x14]; 3147 }; 3148 3149 struct mlx5_ifc_dtor_reg_bits { 3150 u8 reserved_at_0[0x20]; 3151 3152 struct mlx5_ifc_default_timeout_bits pcie_toggle_to; 3153 3154 u8 reserved_at_40[0x60]; 3155 3156 struct mlx5_ifc_default_timeout_bits health_poll_to; 3157 3158 struct mlx5_ifc_default_timeout_bits full_crdump_to; 3159 3160 struct mlx5_ifc_default_timeout_bits fw_reset_to; 3161 3162 struct mlx5_ifc_default_timeout_bits flush_on_err_to; 3163 3164 struct mlx5_ifc_default_timeout_bits pci_sync_update_to; 3165 3166 struct mlx5_ifc_default_timeout_bits tear_down_to; 3167 3168 struct mlx5_ifc_default_timeout_bits fsm_reactivate_to; 3169 3170 struct mlx5_ifc_default_timeout_bits reclaim_pages_to; 3171 3172 struct mlx5_ifc_default_timeout_bits reclaim_vfs_pages_to; 3173 3174 struct mlx5_ifc_default_timeout_bits reset_unload_to; 3175 3176 u8 reserved_at_1c0[0x20]; 3177 }; 3178 3179 enum { 3180 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1, 3181 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2, 3182 }; 3183 3184 struct mlx5_ifc_cq_error_bits { 3185 u8 reserved_at_0[0x8]; 3186 u8 cqn[0x18]; 3187 3188 u8 reserved_at_20[0x20]; 3189 3190 u8 reserved_at_40[0x18]; 3191 u8 syndrome[0x8]; 3192 3193 u8 reserved_at_60[0x80]; 3194 }; 3195 3196 struct mlx5_ifc_rdma_page_fault_event_bits { 3197 u8 bytes_committed[0x20]; 3198 3199 u8 r_key[0x20]; 3200 3201 u8 reserved_at_40[0x10]; 3202 u8 packet_len[0x10]; 3203 3204 u8 rdma_op_len[0x20]; 3205 3206 u8 rdma_va[0x40]; 3207 3208 u8 reserved_at_c0[0x5]; 3209 u8 rdma[0x1]; 3210 u8 write[0x1]; 3211 u8 requestor[0x1]; 3212 u8 qp_number[0x18]; 3213 }; 3214 3215 struct mlx5_ifc_wqe_associated_page_fault_event_bits { 3216 u8 bytes_committed[0x20]; 3217 3218 u8 reserved_at_20[0x10]; 3219 u8 wqe_index[0x10]; 3220 3221 u8 reserved_at_40[0x10]; 3222 u8 len[0x10]; 3223 3224 u8 reserved_at_60[0x60]; 3225 3226 u8 reserved_at_c0[0x5]; 3227 u8 rdma[0x1]; 3228 u8 write_read[0x1]; 3229 u8 requestor[0x1]; 3230 u8 qpn[0x18]; 3231 }; 3232 3233 struct mlx5_ifc_qp_events_bits { 3234 u8 reserved_at_0[0xa0]; 3235 3236 u8 type[0x8]; 3237 u8 reserved_at_a8[0x18]; 3238 3239 u8 reserved_at_c0[0x8]; 3240 u8 qpn_rqn_sqn[0x18]; 3241 }; 3242 3243 struct mlx5_ifc_dct_events_bits { 3244 u8 reserved_at_0[0xc0]; 3245 3246 u8 reserved_at_c0[0x8]; 3247 u8 dct_number[0x18]; 3248 }; 3249 3250 struct mlx5_ifc_comp_event_bits { 3251 u8 reserved_at_0[0xc0]; 3252 3253 u8 reserved_at_c0[0x8]; 3254 u8 cq_number[0x18]; 3255 }; 3256 3257 enum { 3258 MLX5_QPC_STATE_RST = 0x0, 3259 MLX5_QPC_STATE_INIT = 0x1, 3260 MLX5_QPC_STATE_RTR = 0x2, 3261 MLX5_QPC_STATE_RTS = 0x3, 3262 MLX5_QPC_STATE_SQER = 0x4, 3263 MLX5_QPC_STATE_ERR = 0x6, 3264 MLX5_QPC_STATE_SQD = 0x7, 3265 MLX5_QPC_STATE_SUSPENDED = 0x9, 3266 }; 3267 3268 enum { 3269 MLX5_QPC_ST_RC = 0x0, 3270 MLX5_QPC_ST_UC = 0x1, 3271 MLX5_QPC_ST_UD = 0x2, 3272 MLX5_QPC_ST_XRC = 0x3, 3273 MLX5_QPC_ST_DCI = 0x5, 3274 MLX5_QPC_ST_QP0 = 0x7, 3275 MLX5_QPC_ST_QP1 = 0x8, 3276 MLX5_QPC_ST_RAW_DATAGRAM = 0x9, 3277 MLX5_QPC_ST_REG_UMR = 0xc, 3278 }; 3279 3280 enum { 3281 MLX5_QPC_PM_STATE_ARMED = 0x0, 3282 MLX5_QPC_PM_STATE_REARM = 0x1, 3283 MLX5_QPC_PM_STATE_RESERVED = 0x2, 3284 MLX5_QPC_PM_STATE_MIGRATED = 0x3, 3285 }; 3286 3287 enum { 3288 MLX5_QPC_OFFLOAD_TYPE_RNDV = 0x1, 3289 }; 3290 3291 enum { 3292 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0, 3293 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1, 3294 }; 3295 3296 enum { 3297 MLX5_QPC_MTU_256_BYTES = 0x1, 3298 MLX5_QPC_MTU_512_BYTES = 0x2, 3299 MLX5_QPC_MTU_1K_BYTES = 0x3, 3300 MLX5_QPC_MTU_2K_BYTES = 0x4, 3301 MLX5_QPC_MTU_4K_BYTES = 0x5, 3302 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7, 3303 }; 3304 3305 enum { 3306 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1, 3307 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2, 3308 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3, 3309 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4, 3310 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5, 3311 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6, 3312 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7, 3313 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8, 3314 }; 3315 3316 enum { 3317 MLX5_QPC_CS_REQ_DISABLE = 0x0, 3318 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11, 3319 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22, 3320 }; 3321 3322 enum { 3323 MLX5_QPC_CS_RES_DISABLE = 0x0, 3324 MLX5_QPC_CS_RES_UP_TO_32B = 0x1, 3325 MLX5_QPC_CS_RES_UP_TO_64B = 0x2, 3326 }; 3327 3328 enum { 3329 MLX5_TIMESTAMP_FORMAT_FREE_RUNNING = 0x0, 3330 MLX5_TIMESTAMP_FORMAT_DEFAULT = 0x1, 3331 MLX5_TIMESTAMP_FORMAT_REAL_TIME = 0x2, 3332 }; 3333 3334 struct mlx5_ifc_qpc_bits { 3335 u8 state[0x4]; 3336 u8 lag_tx_port_affinity[0x4]; 3337 u8 st[0x8]; 3338 u8 reserved_at_10[0x2]; 3339 u8 isolate_vl_tc[0x1]; 3340 u8 pm_state[0x2]; 3341 u8 reserved_at_15[0x1]; 3342 u8 req_e2e_credit_mode[0x2]; 3343 u8 offload_type[0x4]; 3344 u8 end_padding_mode[0x2]; 3345 u8 reserved_at_1e[0x2]; 3346 3347 u8 wq_signature[0x1]; 3348 u8 block_lb_mc[0x1]; 3349 u8 atomic_like_write_en[0x1]; 3350 u8 latency_sensitive[0x1]; 3351 u8 reserved_at_24[0x1]; 3352 u8 drain_sigerr[0x1]; 3353 u8 reserved_at_26[0x2]; 3354 u8 pd[0x18]; 3355 3356 u8 mtu[0x3]; 3357 u8 log_msg_max[0x5]; 3358 u8 reserved_at_48[0x1]; 3359 u8 log_rq_size[0x4]; 3360 u8 log_rq_stride[0x3]; 3361 u8 no_sq[0x1]; 3362 u8 log_sq_size[0x4]; 3363 u8 reserved_at_55[0x1]; 3364 u8 retry_mode[0x2]; 3365 u8 ts_format[0x2]; 3366 u8 reserved_at_5a[0x1]; 3367 u8 rlky[0x1]; 3368 u8 ulp_stateless_offload_mode[0x4]; 3369 3370 u8 counter_set_id[0x8]; 3371 u8 uar_page[0x18]; 3372 3373 u8 reserved_at_80[0x8]; 3374 u8 user_index[0x18]; 3375 3376 u8 reserved_at_a0[0x3]; 3377 u8 log_page_size[0x5]; 3378 u8 remote_qpn[0x18]; 3379 3380 struct mlx5_ifc_ads_bits primary_address_path; 3381 3382 struct mlx5_ifc_ads_bits secondary_address_path; 3383 3384 u8 log_ack_req_freq[0x4]; 3385 u8 reserved_at_384[0x4]; 3386 u8 log_sra_max[0x3]; 3387 u8 reserved_at_38b[0x2]; 3388 u8 retry_count[0x3]; 3389 u8 rnr_retry[0x3]; 3390 u8 reserved_at_393[0x1]; 3391 u8 fre[0x1]; 3392 u8 cur_rnr_retry[0x3]; 3393 u8 cur_retry_count[0x3]; 3394 u8 reserved_at_39b[0x5]; 3395 3396 u8 reserved_at_3a0[0x20]; 3397 3398 u8 reserved_at_3c0[0x8]; 3399 u8 next_send_psn[0x18]; 3400 3401 u8 reserved_at_3e0[0x3]; 3402 u8 log_num_dci_stream_channels[0x5]; 3403 u8 cqn_snd[0x18]; 3404 3405 u8 reserved_at_400[0x3]; 3406 u8 log_num_dci_errored_streams[0x5]; 3407 u8 deth_sqpn[0x18]; 3408 3409 u8 reserved_at_420[0x20]; 3410 3411 u8 reserved_at_440[0x8]; 3412 u8 last_acked_psn[0x18]; 3413 3414 u8 reserved_at_460[0x8]; 3415 u8 ssn[0x18]; 3416 3417 u8 reserved_at_480[0x8]; 3418 u8 log_rra_max[0x3]; 3419 u8 reserved_at_48b[0x1]; 3420 u8 atomic_mode[0x4]; 3421 u8 rre[0x1]; 3422 u8 rwe[0x1]; 3423 u8 rae[0x1]; 3424 u8 reserved_at_493[0x1]; 3425 u8 page_offset[0x6]; 3426 u8 reserved_at_49a[0x3]; 3427 u8 cd_slave_receive[0x1]; 3428 u8 cd_slave_send[0x1]; 3429 u8 cd_master[0x1]; 3430 3431 u8 reserved_at_4a0[0x3]; 3432 u8 min_rnr_nak[0x5]; 3433 u8 next_rcv_psn[0x18]; 3434 3435 u8 reserved_at_4c0[0x8]; 3436 u8 xrcd[0x18]; 3437 3438 u8 reserved_at_4e0[0x8]; 3439 u8 cqn_rcv[0x18]; 3440 3441 u8 dbr_addr[0x40]; 3442 3443 u8 q_key[0x20]; 3444 3445 u8 reserved_at_560[0x5]; 3446 u8 rq_type[0x3]; 3447 u8 srqn_rmpn_xrqn[0x18]; 3448 3449 u8 reserved_at_580[0x8]; 3450 u8 rmsn[0x18]; 3451 3452 u8 hw_sq_wqebb_counter[0x10]; 3453 u8 sw_sq_wqebb_counter[0x10]; 3454 3455 u8 hw_rq_counter[0x20]; 3456 3457 u8 sw_rq_counter[0x20]; 3458 3459 u8 reserved_at_600[0x20]; 3460 3461 u8 reserved_at_620[0xf]; 3462 u8 cgs[0x1]; 3463 u8 cs_req[0x8]; 3464 u8 cs_res[0x8]; 3465 3466 u8 dc_access_key[0x40]; 3467 3468 u8 reserved_at_680[0x3]; 3469 u8 dbr_umem_valid[0x1]; 3470 3471 u8 reserved_at_684[0xbc]; 3472 }; 3473 3474 struct mlx5_ifc_roce_addr_layout_bits { 3475 u8 source_l3_address[16][0x8]; 3476 3477 u8 reserved_at_80[0x3]; 3478 u8 vlan_valid[0x1]; 3479 u8 vlan_id[0xc]; 3480 u8 source_mac_47_32[0x10]; 3481 3482 u8 source_mac_31_0[0x20]; 3483 3484 u8 reserved_at_c0[0x14]; 3485 u8 roce_l3_type[0x4]; 3486 u8 roce_version[0x8]; 3487 3488 u8 reserved_at_e0[0x20]; 3489 }; 3490 3491 struct mlx5_ifc_crypto_cap_bits { 3492 u8 reserved_at_0[0x3]; 3493 u8 synchronize_dek[0x1]; 3494 u8 int_kek_manual[0x1]; 3495 u8 int_kek_auto[0x1]; 3496 u8 reserved_at_6[0x1a]; 3497 3498 u8 reserved_at_20[0x3]; 3499 u8 log_dek_max_alloc[0x5]; 3500 u8 reserved_at_28[0x3]; 3501 u8 log_max_num_deks[0x5]; 3502 u8 reserved_at_30[0x10]; 3503 3504 u8 reserved_at_40[0x20]; 3505 3506 u8 reserved_at_60[0x3]; 3507 u8 log_dek_granularity[0x5]; 3508 u8 reserved_at_68[0x3]; 3509 u8 log_max_num_int_kek[0x5]; 3510 u8 sw_wrapped_dek[0x10]; 3511 3512 u8 reserved_at_80[0x780]; 3513 }; 3514 3515 union mlx5_ifc_hca_cap_union_bits { 3516 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap; 3517 struct mlx5_ifc_cmd_hca_cap_2_bits cmd_hca_cap_2; 3518 struct mlx5_ifc_odp_cap_bits odp_cap; 3519 struct mlx5_ifc_atomic_caps_bits atomic_caps; 3520 struct mlx5_ifc_roce_cap_bits roce_cap; 3521 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps; 3522 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap; 3523 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap; 3524 struct mlx5_ifc_e_switch_cap_bits e_switch_cap; 3525 struct mlx5_ifc_port_selection_cap_bits port_selection_cap; 3526 struct mlx5_ifc_qos_cap_bits qos_cap; 3527 struct mlx5_ifc_debug_cap_bits debug_cap; 3528 struct mlx5_ifc_fpga_cap_bits fpga_cap; 3529 struct mlx5_ifc_tls_cap_bits tls_cap; 3530 struct mlx5_ifc_device_mem_cap_bits device_mem_cap; 3531 struct mlx5_ifc_virtio_emulation_cap_bits virtio_emulation_cap; 3532 struct mlx5_ifc_macsec_cap_bits macsec_cap; 3533 struct mlx5_ifc_crypto_cap_bits crypto_cap; 3534 struct mlx5_ifc_ipsec_cap_bits ipsec_cap; 3535 u8 reserved_at_0[0x8000]; 3536 }; 3537 3538 enum { 3539 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1, 3540 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2, 3541 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4, 3542 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8, 3543 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT = 0x10, 3544 MLX5_FLOW_CONTEXT_ACTION_DECAP = 0x20, 3545 MLX5_FLOW_CONTEXT_ACTION_MOD_HDR = 0x40, 3546 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP = 0x80, 3547 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100, 3548 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2 = 0x400, 3549 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2 = 0x800, 3550 MLX5_FLOW_CONTEXT_ACTION_CRYPTO_DECRYPT = 0x1000, 3551 MLX5_FLOW_CONTEXT_ACTION_CRYPTO_ENCRYPT = 0x2000, 3552 MLX5_FLOW_CONTEXT_ACTION_EXECUTE_ASO = 0x4000, 3553 }; 3554 3555 enum { 3556 MLX5_FLOW_CONTEXT_FLOW_SOURCE_ANY_VPORT = 0x0, 3557 MLX5_FLOW_CONTEXT_FLOW_SOURCE_UPLINK = 0x1, 3558 MLX5_FLOW_CONTEXT_FLOW_SOURCE_LOCAL_VPORT = 0x2, 3559 }; 3560 3561 enum { 3562 MLX5_FLOW_CONTEXT_ENCRYPT_DECRYPT_TYPE_IPSEC = 0x0, 3563 MLX5_FLOW_CONTEXT_ENCRYPT_DECRYPT_TYPE_MACSEC = 0x1, 3564 }; 3565 3566 struct mlx5_ifc_vlan_bits { 3567 u8 ethtype[0x10]; 3568 u8 prio[0x3]; 3569 u8 cfi[0x1]; 3570 u8 vid[0xc]; 3571 }; 3572 3573 enum { 3574 MLX5_FLOW_METER_COLOR_RED = 0x0, 3575 MLX5_FLOW_METER_COLOR_YELLOW = 0x1, 3576 MLX5_FLOW_METER_COLOR_GREEN = 0x2, 3577 MLX5_FLOW_METER_COLOR_UNDEFINED = 0x3, 3578 }; 3579 3580 enum { 3581 MLX5_EXE_ASO_FLOW_METER = 0x2, 3582 }; 3583 3584 struct mlx5_ifc_exe_aso_ctrl_flow_meter_bits { 3585 u8 return_reg_id[0x4]; 3586 u8 aso_type[0x4]; 3587 u8 reserved_at_8[0x14]; 3588 u8 action[0x1]; 3589 u8 init_color[0x2]; 3590 u8 meter_id[0x1]; 3591 }; 3592 3593 union mlx5_ifc_exe_aso_ctrl { 3594 struct mlx5_ifc_exe_aso_ctrl_flow_meter_bits exe_aso_ctrl_flow_meter; 3595 }; 3596 3597 struct mlx5_ifc_execute_aso_bits { 3598 u8 valid[0x1]; 3599 u8 reserved_at_1[0x7]; 3600 u8 aso_object_id[0x18]; 3601 3602 union mlx5_ifc_exe_aso_ctrl exe_aso_ctrl; 3603 }; 3604 3605 struct mlx5_ifc_flow_context_bits { 3606 struct mlx5_ifc_vlan_bits push_vlan; 3607 3608 u8 group_id[0x20]; 3609 3610 u8 reserved_at_40[0x8]; 3611 u8 flow_tag[0x18]; 3612 3613 u8 reserved_at_60[0x10]; 3614 u8 action[0x10]; 3615 3616 u8 extended_destination[0x1]; 3617 u8 uplink_hairpin_en[0x1]; 3618 u8 flow_source[0x2]; 3619 u8 encrypt_decrypt_type[0x4]; 3620 u8 destination_list_size[0x18]; 3621 3622 u8 reserved_at_a0[0x8]; 3623 u8 flow_counter_list_size[0x18]; 3624 3625 u8 packet_reformat_id[0x20]; 3626 3627 u8 modify_header_id[0x20]; 3628 3629 struct mlx5_ifc_vlan_bits push_vlan_2; 3630 3631 u8 encrypt_decrypt_obj_id[0x20]; 3632 u8 reserved_at_140[0xc0]; 3633 3634 struct mlx5_ifc_fte_match_param_bits match_value; 3635 3636 struct mlx5_ifc_execute_aso_bits execute_aso[4]; 3637 3638 u8 reserved_at_1300[0x500]; 3639 3640 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[]; 3641 }; 3642 3643 enum { 3644 MLX5_XRC_SRQC_STATE_GOOD = 0x0, 3645 MLX5_XRC_SRQC_STATE_ERROR = 0x1, 3646 }; 3647 3648 struct mlx5_ifc_xrc_srqc_bits { 3649 u8 state[0x4]; 3650 u8 log_xrc_srq_size[0x4]; 3651 u8 reserved_at_8[0x18]; 3652 3653 u8 wq_signature[0x1]; 3654 u8 cont_srq[0x1]; 3655 u8 reserved_at_22[0x1]; 3656 u8 rlky[0x1]; 3657 u8 basic_cyclic_rcv_wqe[0x1]; 3658 u8 log_rq_stride[0x3]; 3659 u8 xrcd[0x18]; 3660 3661 u8 page_offset[0x6]; 3662 u8 reserved_at_46[0x1]; 3663 u8 dbr_umem_valid[0x1]; 3664 u8 cqn[0x18]; 3665 3666 u8 reserved_at_60[0x20]; 3667 3668 u8 user_index_equal_xrc_srqn[0x1]; 3669 u8 reserved_at_81[0x1]; 3670 u8 log_page_size[0x6]; 3671 u8 user_index[0x18]; 3672 3673 u8 reserved_at_a0[0x20]; 3674 3675 u8 reserved_at_c0[0x8]; 3676 u8 pd[0x18]; 3677 3678 u8 lwm[0x10]; 3679 u8 wqe_cnt[0x10]; 3680 3681 u8 reserved_at_100[0x40]; 3682 3683 u8 db_record_addr_h[0x20]; 3684 3685 u8 db_record_addr_l[0x1e]; 3686 u8 reserved_at_17e[0x2]; 3687 3688 u8 reserved_at_180[0x80]; 3689 }; 3690 3691 struct mlx5_ifc_vnic_diagnostic_statistics_bits { 3692 u8 counter_error_queues[0x20]; 3693 3694 u8 total_error_queues[0x20]; 3695 3696 u8 send_queue_priority_update_flow[0x20]; 3697 3698 u8 reserved_at_60[0x20]; 3699 3700 u8 nic_receive_steering_discard[0x40]; 3701 3702 u8 receive_discard_vport_down[0x40]; 3703 3704 u8 transmit_discard_vport_down[0x40]; 3705 3706 u8 async_eq_overrun[0x20]; 3707 3708 u8 comp_eq_overrun[0x20]; 3709 3710 u8 reserved_at_180[0x20]; 3711 3712 u8 invalid_command[0x20]; 3713 3714 u8 quota_exceeded_command[0x20]; 3715 3716 u8 internal_rq_out_of_buffer[0x20]; 3717 3718 u8 cq_overrun[0x20]; 3719 3720 u8 eth_wqe_too_small[0x20]; 3721 3722 u8 reserved_at_220[0xc0]; 3723 3724 u8 generated_pkt_steering_fail[0x40]; 3725 3726 u8 handled_pkt_steering_fail[0x40]; 3727 3728 u8 reserved_at_360[0xc80]; 3729 }; 3730 3731 struct mlx5_ifc_traffic_counter_bits { 3732 u8 packets[0x40]; 3733 3734 u8 octets[0x40]; 3735 }; 3736 3737 struct mlx5_ifc_tisc_bits { 3738 u8 strict_lag_tx_port_affinity[0x1]; 3739 u8 tls_en[0x1]; 3740 u8 reserved_at_2[0x2]; 3741 u8 lag_tx_port_affinity[0x04]; 3742 3743 u8 reserved_at_8[0x4]; 3744 u8 prio[0x4]; 3745 u8 reserved_at_10[0x10]; 3746 3747 u8 reserved_at_20[0x100]; 3748 3749 u8 reserved_at_120[0x8]; 3750 u8 transport_domain[0x18]; 3751 3752 u8 reserved_at_140[0x8]; 3753 u8 underlay_qpn[0x18]; 3754 3755 u8 reserved_at_160[0x8]; 3756 u8 pd[0x18]; 3757 3758 u8 reserved_at_180[0x380]; 3759 }; 3760 3761 enum { 3762 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0, 3763 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1, 3764 }; 3765 3766 enum { 3767 MLX5_TIRC_PACKET_MERGE_MASK_IPV4_LRO = BIT(0), 3768 MLX5_TIRC_PACKET_MERGE_MASK_IPV6_LRO = BIT(1), 3769 }; 3770 3771 enum { 3772 MLX5_RX_HASH_FN_NONE = 0x0, 3773 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1, 3774 MLX5_RX_HASH_FN_TOEPLITZ = 0x2, 3775 }; 3776 3777 enum { 3778 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST = 0x1, 3779 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST = 0x2, 3780 }; 3781 3782 struct mlx5_ifc_tirc_bits { 3783 u8 reserved_at_0[0x20]; 3784 3785 u8 disp_type[0x4]; 3786 u8 tls_en[0x1]; 3787 u8 reserved_at_25[0x1b]; 3788 3789 u8 reserved_at_40[0x40]; 3790 3791 u8 reserved_at_80[0x4]; 3792 u8 lro_timeout_period_usecs[0x10]; 3793 u8 packet_merge_mask[0x4]; 3794 u8 lro_max_ip_payload_size[0x8]; 3795 3796 u8 reserved_at_a0[0x40]; 3797 3798 u8 reserved_at_e0[0x8]; 3799 u8 inline_rqn[0x18]; 3800 3801 u8 rx_hash_symmetric[0x1]; 3802 u8 reserved_at_101[0x1]; 3803 u8 tunneled_offload_en[0x1]; 3804 u8 reserved_at_103[0x5]; 3805 u8 indirect_table[0x18]; 3806 3807 u8 rx_hash_fn[0x4]; 3808 u8 reserved_at_124[0x2]; 3809 u8 self_lb_block[0x2]; 3810 u8 transport_domain[0x18]; 3811 3812 u8 rx_hash_toeplitz_key[10][0x20]; 3813 3814 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer; 3815 3816 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner; 3817 3818 u8 reserved_at_2c0[0x4c0]; 3819 }; 3820 3821 enum { 3822 MLX5_SRQC_STATE_GOOD = 0x0, 3823 MLX5_SRQC_STATE_ERROR = 0x1, 3824 }; 3825 3826 struct mlx5_ifc_srqc_bits { 3827 u8 state[0x4]; 3828 u8 log_srq_size[0x4]; 3829 u8 reserved_at_8[0x18]; 3830 3831 u8 wq_signature[0x1]; 3832 u8 cont_srq[0x1]; 3833 u8 reserved_at_22[0x1]; 3834 u8 rlky[0x1]; 3835 u8 reserved_at_24[0x1]; 3836 u8 log_rq_stride[0x3]; 3837 u8 xrcd[0x18]; 3838 3839 u8 page_offset[0x6]; 3840 u8 reserved_at_46[0x2]; 3841 u8 cqn[0x18]; 3842 3843 u8 reserved_at_60[0x20]; 3844 3845 u8 reserved_at_80[0x2]; 3846 u8 log_page_size[0x6]; 3847 u8 reserved_at_88[0x18]; 3848 3849 u8 reserved_at_a0[0x20]; 3850 3851 u8 reserved_at_c0[0x8]; 3852 u8 pd[0x18]; 3853 3854 u8 lwm[0x10]; 3855 u8 wqe_cnt[0x10]; 3856 3857 u8 reserved_at_100[0x40]; 3858 3859 u8 dbr_addr[0x40]; 3860 3861 u8 reserved_at_180[0x80]; 3862 }; 3863 3864 enum { 3865 MLX5_SQC_STATE_RST = 0x0, 3866 MLX5_SQC_STATE_RDY = 0x1, 3867 MLX5_SQC_STATE_ERR = 0x3, 3868 }; 3869 3870 struct mlx5_ifc_sqc_bits { 3871 u8 rlky[0x1]; 3872 u8 cd_master[0x1]; 3873 u8 fre[0x1]; 3874 u8 flush_in_error_en[0x1]; 3875 u8 allow_multi_pkt_send_wqe[0x1]; 3876 u8 min_wqe_inline_mode[0x3]; 3877 u8 state[0x4]; 3878 u8 reg_umr[0x1]; 3879 u8 allow_swp[0x1]; 3880 u8 hairpin[0x1]; 3881 u8 reserved_at_f[0xb]; 3882 u8 ts_format[0x2]; 3883 u8 reserved_at_1c[0x4]; 3884 3885 u8 reserved_at_20[0x8]; 3886 u8 user_index[0x18]; 3887 3888 u8 reserved_at_40[0x8]; 3889 u8 cqn[0x18]; 3890 3891 u8 reserved_at_60[0x8]; 3892 u8 hairpin_peer_rq[0x18]; 3893 3894 u8 reserved_at_80[0x10]; 3895 u8 hairpin_peer_vhca[0x10]; 3896 3897 u8 reserved_at_a0[0x20]; 3898 3899 u8 reserved_at_c0[0x8]; 3900 u8 ts_cqe_to_dest_cqn[0x18]; 3901 3902 u8 reserved_at_e0[0x10]; 3903 u8 packet_pacing_rate_limit_index[0x10]; 3904 u8 tis_lst_sz[0x10]; 3905 u8 qos_queue_group_id[0x10]; 3906 3907 u8 reserved_at_120[0x40]; 3908 3909 u8 reserved_at_160[0x8]; 3910 u8 tis_num_0[0x18]; 3911 3912 struct mlx5_ifc_wq_bits wq; 3913 }; 3914 3915 enum { 3916 SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0, 3917 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1, 3918 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2, 3919 SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3, 3920 SCHEDULING_CONTEXT_ELEMENT_TYPE_QUEUE_GROUP = 0x4, 3921 }; 3922 3923 enum { 3924 ELEMENT_TYPE_CAP_MASK_TSAR = 1 << 0, 3925 ELEMENT_TYPE_CAP_MASK_VPORT = 1 << 1, 3926 ELEMENT_TYPE_CAP_MASK_VPORT_TC = 1 << 2, 3927 ELEMENT_TYPE_CAP_MASK_PARA_VPORT_TC = 1 << 3, 3928 }; 3929 3930 struct mlx5_ifc_scheduling_context_bits { 3931 u8 element_type[0x8]; 3932 u8 reserved_at_8[0x18]; 3933 3934 u8 element_attributes[0x20]; 3935 3936 u8 parent_element_id[0x20]; 3937 3938 u8 reserved_at_60[0x40]; 3939 3940 u8 bw_share[0x20]; 3941 3942 u8 max_average_bw[0x20]; 3943 3944 u8 reserved_at_e0[0x120]; 3945 }; 3946 3947 struct mlx5_ifc_rqtc_bits { 3948 u8 reserved_at_0[0xa0]; 3949 3950 u8 reserved_at_a0[0x5]; 3951 u8 list_q_type[0x3]; 3952 u8 reserved_at_a8[0x8]; 3953 u8 rqt_max_size[0x10]; 3954 3955 u8 rq_vhca_id_format[0x1]; 3956 u8 reserved_at_c1[0xf]; 3957 u8 rqt_actual_size[0x10]; 3958 3959 u8 reserved_at_e0[0x6a0]; 3960 3961 union { 3962 DECLARE_FLEX_ARRAY(struct mlx5_ifc_rq_num_bits, rq_num); 3963 DECLARE_FLEX_ARRAY(struct mlx5_ifc_rq_vhca_bits, rq_vhca); 3964 }; 3965 }; 3966 3967 enum { 3968 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0, 3969 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1, 3970 }; 3971 3972 enum { 3973 MLX5_RQC_STATE_RST = 0x0, 3974 MLX5_RQC_STATE_RDY = 0x1, 3975 MLX5_RQC_STATE_ERR = 0x3, 3976 }; 3977 3978 enum { 3979 MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_BYTE = 0x0, 3980 MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_STRIDE = 0x1, 3981 MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_PAGE = 0x2, 3982 }; 3983 3984 enum { 3985 MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_NO_MATCH = 0x0, 3986 MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_EXTENDED = 0x1, 3987 MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_FIVE_TUPLE = 0x2, 3988 }; 3989 3990 struct mlx5_ifc_rqc_bits { 3991 u8 rlky[0x1]; 3992 u8 delay_drop_en[0x1]; 3993 u8 scatter_fcs[0x1]; 3994 u8 vsd[0x1]; 3995 u8 mem_rq_type[0x4]; 3996 u8 state[0x4]; 3997 u8 reserved_at_c[0x1]; 3998 u8 flush_in_error_en[0x1]; 3999 u8 hairpin[0x1]; 4000 u8 reserved_at_f[0xb]; 4001 u8 ts_format[0x2]; 4002 u8 reserved_at_1c[0x4]; 4003 4004 u8 reserved_at_20[0x8]; 4005 u8 user_index[0x18]; 4006 4007 u8 reserved_at_40[0x8]; 4008 u8 cqn[0x18]; 4009 4010 u8 counter_set_id[0x8]; 4011 u8 reserved_at_68[0x18]; 4012 4013 u8 reserved_at_80[0x8]; 4014 u8 rmpn[0x18]; 4015 4016 u8 reserved_at_a0[0x8]; 4017 u8 hairpin_peer_sq[0x18]; 4018 4019 u8 reserved_at_c0[0x10]; 4020 u8 hairpin_peer_vhca[0x10]; 4021 4022 u8 reserved_at_e0[0x46]; 4023 u8 shampo_no_match_alignment_granularity[0x2]; 4024 u8 reserved_at_128[0x6]; 4025 u8 shampo_match_criteria_type[0x2]; 4026 u8 reservation_timeout[0x10]; 4027 4028 u8 reserved_at_140[0x40]; 4029 4030 struct mlx5_ifc_wq_bits wq; 4031 }; 4032 4033 enum { 4034 MLX5_RMPC_STATE_RDY = 0x1, 4035 MLX5_RMPC_STATE_ERR = 0x3, 4036 }; 4037 4038 struct mlx5_ifc_rmpc_bits { 4039 u8 reserved_at_0[0x8]; 4040 u8 state[0x4]; 4041 u8 reserved_at_c[0x14]; 4042 4043 u8 basic_cyclic_rcv_wqe[0x1]; 4044 u8 reserved_at_21[0x1f]; 4045 4046 u8 reserved_at_40[0x140]; 4047 4048 struct mlx5_ifc_wq_bits wq; 4049 }; 4050 4051 enum { 4052 VHCA_ID_TYPE_HW = 0, 4053 VHCA_ID_TYPE_SW = 1, 4054 }; 4055 4056 struct mlx5_ifc_nic_vport_context_bits { 4057 u8 reserved_at_0[0x5]; 4058 u8 min_wqe_inline_mode[0x3]; 4059 u8 reserved_at_8[0x15]; 4060 u8 disable_mc_local_lb[0x1]; 4061 u8 disable_uc_local_lb[0x1]; 4062 u8 roce_en[0x1]; 4063 4064 u8 arm_change_event[0x1]; 4065 u8 reserved_at_21[0x1a]; 4066 u8 event_on_mtu[0x1]; 4067 u8 event_on_promisc_change[0x1]; 4068 u8 event_on_vlan_change[0x1]; 4069 u8 event_on_mc_address_change[0x1]; 4070 u8 event_on_uc_address_change[0x1]; 4071 4072 u8 vhca_id_type[0x1]; 4073 u8 reserved_at_41[0xb]; 4074 u8 affiliation_criteria[0x4]; 4075 u8 affiliated_vhca_id[0x10]; 4076 4077 u8 reserved_at_60[0xa0]; 4078 4079 u8 reserved_at_100[0x1]; 4080 u8 sd_group[0x3]; 4081 u8 reserved_at_104[0x1c]; 4082 4083 u8 reserved_at_120[0x10]; 4084 u8 mtu[0x10]; 4085 4086 u8 system_image_guid[0x40]; 4087 u8 port_guid[0x40]; 4088 u8 node_guid[0x40]; 4089 4090 u8 reserved_at_200[0x140]; 4091 u8 qkey_violation_counter[0x10]; 4092 u8 reserved_at_350[0x430]; 4093 4094 u8 promisc_uc[0x1]; 4095 u8 promisc_mc[0x1]; 4096 u8 promisc_all[0x1]; 4097 u8 reserved_at_783[0x2]; 4098 u8 allowed_list_type[0x3]; 4099 u8 reserved_at_788[0xc]; 4100 u8 allowed_list_size[0xc]; 4101 4102 struct mlx5_ifc_mac_address_layout_bits permanent_address; 4103 4104 u8 reserved_at_7e0[0x20]; 4105 4106 u8 current_uc_mac_address[][0x40]; 4107 }; 4108 4109 enum { 4110 MLX5_MKC_ACCESS_MODE_PA = 0x0, 4111 MLX5_MKC_ACCESS_MODE_MTT = 0x1, 4112 MLX5_MKC_ACCESS_MODE_KLMS = 0x2, 4113 MLX5_MKC_ACCESS_MODE_KSM = 0x3, 4114 MLX5_MKC_ACCESS_MODE_SW_ICM = 0x4, 4115 MLX5_MKC_ACCESS_MODE_MEMIC = 0x5, 4116 }; 4117 4118 struct mlx5_ifc_mkc_bits { 4119 u8 reserved_at_0[0x1]; 4120 u8 free[0x1]; 4121 u8 reserved_at_2[0x1]; 4122 u8 access_mode_4_2[0x3]; 4123 u8 reserved_at_6[0x7]; 4124 u8 relaxed_ordering_write[0x1]; 4125 u8 reserved_at_e[0x1]; 4126 u8 small_fence_on_rdma_read_response[0x1]; 4127 u8 umr_en[0x1]; 4128 u8 a[0x1]; 4129 u8 rw[0x1]; 4130 u8 rr[0x1]; 4131 u8 lw[0x1]; 4132 u8 lr[0x1]; 4133 u8 access_mode_1_0[0x2]; 4134 u8 reserved_at_18[0x2]; 4135 u8 ma_translation_mode[0x2]; 4136 u8 reserved_at_1c[0x4]; 4137 4138 u8 qpn[0x18]; 4139 u8 mkey_7_0[0x8]; 4140 4141 u8 reserved_at_40[0x20]; 4142 4143 u8 length64[0x1]; 4144 u8 bsf_en[0x1]; 4145 u8 sync_umr[0x1]; 4146 u8 reserved_at_63[0x2]; 4147 u8 expected_sigerr_count[0x1]; 4148 u8 reserved_at_66[0x1]; 4149 u8 en_rinval[0x1]; 4150 u8 pd[0x18]; 4151 4152 u8 start_addr[0x40]; 4153 4154 u8 len[0x40]; 4155 4156 u8 bsf_octword_size[0x20]; 4157 4158 u8 reserved_at_120[0x80]; 4159 4160 u8 translations_octword_size[0x20]; 4161 4162 u8 reserved_at_1c0[0x19]; 4163 u8 relaxed_ordering_read[0x1]; 4164 u8 reserved_at_1d9[0x1]; 4165 u8 log_page_size[0x5]; 4166 4167 u8 reserved_at_1e0[0x20]; 4168 }; 4169 4170 struct mlx5_ifc_pkey_bits { 4171 u8 reserved_at_0[0x10]; 4172 u8 pkey[0x10]; 4173 }; 4174 4175 struct mlx5_ifc_array128_auto_bits { 4176 u8 array128_auto[16][0x8]; 4177 }; 4178 4179 struct mlx5_ifc_hca_vport_context_bits { 4180 u8 field_select[0x20]; 4181 4182 u8 reserved_at_20[0xe0]; 4183 4184 u8 sm_virt_aware[0x1]; 4185 u8 has_smi[0x1]; 4186 u8 has_raw[0x1]; 4187 u8 grh_required[0x1]; 4188 u8 reserved_at_104[0xc]; 4189 u8 port_physical_state[0x4]; 4190 u8 vport_state_policy[0x4]; 4191 u8 port_state[0x4]; 4192 u8 vport_state[0x4]; 4193 4194 u8 reserved_at_120[0x20]; 4195 4196 u8 system_image_guid[0x40]; 4197 4198 u8 port_guid[0x40]; 4199 4200 u8 node_guid[0x40]; 4201 4202 u8 cap_mask1[0x20]; 4203 4204 u8 cap_mask1_field_select[0x20]; 4205 4206 u8 cap_mask2[0x20]; 4207 4208 u8 cap_mask2_field_select[0x20]; 4209 4210 u8 reserved_at_280[0x80]; 4211 4212 u8 lid[0x10]; 4213 u8 reserved_at_310[0x4]; 4214 u8 init_type_reply[0x4]; 4215 u8 lmc[0x3]; 4216 u8 subnet_timeout[0x5]; 4217 4218 u8 sm_lid[0x10]; 4219 u8 sm_sl[0x4]; 4220 u8 reserved_at_334[0xc]; 4221 4222 u8 qkey_violation_counter[0x10]; 4223 u8 pkey_violation_counter[0x10]; 4224 4225 u8 reserved_at_360[0xca0]; 4226 }; 4227 4228 struct mlx5_ifc_esw_vport_context_bits { 4229 u8 fdb_to_vport_reg_c[0x1]; 4230 u8 reserved_at_1[0x2]; 4231 u8 vport_svlan_strip[0x1]; 4232 u8 vport_cvlan_strip[0x1]; 4233 u8 vport_svlan_insert[0x1]; 4234 u8 vport_cvlan_insert[0x2]; 4235 u8 fdb_to_vport_reg_c_id[0x8]; 4236 u8 reserved_at_10[0x10]; 4237 4238 u8 reserved_at_20[0x20]; 4239 4240 u8 svlan_cfi[0x1]; 4241 u8 svlan_pcp[0x3]; 4242 u8 svlan_id[0xc]; 4243 u8 cvlan_cfi[0x1]; 4244 u8 cvlan_pcp[0x3]; 4245 u8 cvlan_id[0xc]; 4246 4247 u8 reserved_at_60[0x720]; 4248 4249 u8 sw_steering_vport_icm_address_rx[0x40]; 4250 4251 u8 sw_steering_vport_icm_address_tx[0x40]; 4252 }; 4253 4254 enum { 4255 MLX5_EQC_STATUS_OK = 0x0, 4256 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa, 4257 }; 4258 4259 enum { 4260 MLX5_EQC_ST_ARMED = 0x9, 4261 MLX5_EQC_ST_FIRED = 0xa, 4262 }; 4263 4264 struct mlx5_ifc_eqc_bits { 4265 u8 status[0x4]; 4266 u8 reserved_at_4[0x9]; 4267 u8 ec[0x1]; 4268 u8 oi[0x1]; 4269 u8 reserved_at_f[0x5]; 4270 u8 st[0x4]; 4271 u8 reserved_at_18[0x8]; 4272 4273 u8 reserved_at_20[0x20]; 4274 4275 u8 reserved_at_40[0x14]; 4276 u8 page_offset[0x6]; 4277 u8 reserved_at_5a[0x6]; 4278 4279 u8 reserved_at_60[0x3]; 4280 u8 log_eq_size[0x5]; 4281 u8 uar_page[0x18]; 4282 4283 u8 reserved_at_80[0x20]; 4284 4285 u8 reserved_at_a0[0x14]; 4286 u8 intr[0xc]; 4287 4288 u8 reserved_at_c0[0x3]; 4289 u8 log_page_size[0x5]; 4290 u8 reserved_at_c8[0x18]; 4291 4292 u8 reserved_at_e0[0x60]; 4293 4294 u8 reserved_at_140[0x8]; 4295 u8 consumer_counter[0x18]; 4296 4297 u8 reserved_at_160[0x8]; 4298 u8 producer_counter[0x18]; 4299 4300 u8 reserved_at_180[0x80]; 4301 }; 4302 4303 enum { 4304 MLX5_DCTC_STATE_ACTIVE = 0x0, 4305 MLX5_DCTC_STATE_DRAINING = 0x1, 4306 MLX5_DCTC_STATE_DRAINED = 0x2, 4307 }; 4308 4309 enum { 4310 MLX5_DCTC_CS_RES_DISABLE = 0x0, 4311 MLX5_DCTC_CS_RES_NA = 0x1, 4312 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2, 4313 }; 4314 4315 enum { 4316 MLX5_DCTC_MTU_256_BYTES = 0x1, 4317 MLX5_DCTC_MTU_512_BYTES = 0x2, 4318 MLX5_DCTC_MTU_1K_BYTES = 0x3, 4319 MLX5_DCTC_MTU_2K_BYTES = 0x4, 4320 MLX5_DCTC_MTU_4K_BYTES = 0x5, 4321 }; 4322 4323 struct mlx5_ifc_dctc_bits { 4324 u8 reserved_at_0[0x4]; 4325 u8 state[0x4]; 4326 u8 reserved_at_8[0x18]; 4327 4328 u8 reserved_at_20[0x8]; 4329 u8 user_index[0x18]; 4330 4331 u8 reserved_at_40[0x8]; 4332 u8 cqn[0x18]; 4333 4334 u8 counter_set_id[0x8]; 4335 u8 atomic_mode[0x4]; 4336 u8 rre[0x1]; 4337 u8 rwe[0x1]; 4338 u8 rae[0x1]; 4339 u8 atomic_like_write_en[0x1]; 4340 u8 latency_sensitive[0x1]; 4341 u8 rlky[0x1]; 4342 u8 free_ar[0x1]; 4343 u8 reserved_at_73[0xd]; 4344 4345 u8 reserved_at_80[0x8]; 4346 u8 cs_res[0x8]; 4347 u8 reserved_at_90[0x3]; 4348 u8 min_rnr_nak[0x5]; 4349 u8 reserved_at_98[0x8]; 4350 4351 u8 reserved_at_a0[0x8]; 4352 u8 srqn_xrqn[0x18]; 4353 4354 u8 reserved_at_c0[0x8]; 4355 u8 pd[0x18]; 4356 4357 u8 tclass[0x8]; 4358 u8 reserved_at_e8[0x4]; 4359 u8 flow_label[0x14]; 4360 4361 u8 dc_access_key[0x40]; 4362 4363 u8 reserved_at_140[0x5]; 4364 u8 mtu[0x3]; 4365 u8 port[0x8]; 4366 u8 pkey_index[0x10]; 4367 4368 u8 reserved_at_160[0x8]; 4369 u8 my_addr_index[0x8]; 4370 u8 reserved_at_170[0x8]; 4371 u8 hop_limit[0x8]; 4372 4373 u8 dc_access_key_violation_count[0x20]; 4374 4375 u8 reserved_at_1a0[0x14]; 4376 u8 dei_cfi[0x1]; 4377 u8 eth_prio[0x3]; 4378 u8 ecn[0x2]; 4379 u8 dscp[0x6]; 4380 4381 u8 reserved_at_1c0[0x20]; 4382 u8 ece[0x20]; 4383 }; 4384 4385 enum { 4386 MLX5_CQC_STATUS_OK = 0x0, 4387 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9, 4388 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa, 4389 }; 4390 4391 enum { 4392 MLX5_CQC_CQE_SZ_64_BYTES = 0x0, 4393 MLX5_CQC_CQE_SZ_128_BYTES = 0x1, 4394 }; 4395 4396 enum { 4397 MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED = 0x6, 4398 MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED = 0x9, 4399 MLX5_CQC_ST_FIRED = 0xa, 4400 }; 4401 4402 enum mlx5_cq_period_mode { 4403 MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0, 4404 MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1, 4405 MLX5_CQ_PERIOD_NUM_MODES, 4406 }; 4407 4408 struct mlx5_ifc_cqc_bits { 4409 u8 status[0x4]; 4410 u8 reserved_at_4[0x2]; 4411 u8 dbr_umem_valid[0x1]; 4412 u8 apu_cq[0x1]; 4413 u8 cqe_sz[0x3]; 4414 u8 cc[0x1]; 4415 u8 reserved_at_c[0x1]; 4416 u8 scqe_break_moderation_en[0x1]; 4417 u8 oi[0x1]; 4418 u8 cq_period_mode[0x2]; 4419 u8 cqe_comp_en[0x1]; 4420 u8 mini_cqe_res_format[0x2]; 4421 u8 st[0x4]; 4422 u8 reserved_at_18[0x6]; 4423 u8 cqe_compression_layout[0x2]; 4424 4425 u8 reserved_at_20[0x20]; 4426 4427 u8 reserved_at_40[0x14]; 4428 u8 page_offset[0x6]; 4429 u8 reserved_at_5a[0x6]; 4430 4431 u8 reserved_at_60[0x3]; 4432 u8 log_cq_size[0x5]; 4433 u8 uar_page[0x18]; 4434 4435 u8 reserved_at_80[0x4]; 4436 u8 cq_period[0xc]; 4437 u8 cq_max_count[0x10]; 4438 4439 u8 c_eqn_or_apu_element[0x20]; 4440 4441 u8 reserved_at_c0[0x3]; 4442 u8 log_page_size[0x5]; 4443 u8 reserved_at_c8[0x18]; 4444 4445 u8 reserved_at_e0[0x20]; 4446 4447 u8 reserved_at_100[0x8]; 4448 u8 last_notified_index[0x18]; 4449 4450 u8 reserved_at_120[0x8]; 4451 u8 last_solicit_index[0x18]; 4452 4453 u8 reserved_at_140[0x8]; 4454 u8 consumer_counter[0x18]; 4455 4456 u8 reserved_at_160[0x8]; 4457 u8 producer_counter[0x18]; 4458 4459 u8 reserved_at_180[0x40]; 4460 4461 u8 dbr_addr[0x40]; 4462 }; 4463 4464 union mlx5_ifc_cong_control_roce_ecn_auto_bits { 4465 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp; 4466 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp; 4467 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np; 4468 struct mlx5_ifc_cong_control_r_roce_general_bits cong_control_r_roce_general; 4469 u8 reserved_at_0[0x800]; 4470 }; 4471 4472 struct mlx5_ifc_query_adapter_param_block_bits { 4473 u8 reserved_at_0[0xc0]; 4474 4475 u8 reserved_at_c0[0x8]; 4476 u8 ieee_vendor_id[0x18]; 4477 4478 u8 reserved_at_e0[0x10]; 4479 u8 vsd_vendor_id[0x10]; 4480 4481 u8 vsd[208][0x8]; 4482 4483 u8 vsd_contd_psid[16][0x8]; 4484 }; 4485 4486 enum { 4487 MLX5_XRQC_STATE_GOOD = 0x0, 4488 MLX5_XRQC_STATE_ERROR = 0x1, 4489 }; 4490 4491 enum { 4492 MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0, 4493 MLX5_XRQC_TOPOLOGY_TAG_MATCHING = 0x1, 4494 }; 4495 4496 enum { 4497 MLX5_XRQC_OFFLOAD_RNDV = 0x1, 4498 }; 4499 4500 struct mlx5_ifc_tag_matching_topology_context_bits { 4501 u8 log_matching_list_sz[0x4]; 4502 u8 reserved_at_4[0xc]; 4503 u8 append_next_index[0x10]; 4504 4505 u8 sw_phase_cnt[0x10]; 4506 u8 hw_phase_cnt[0x10]; 4507 4508 u8 reserved_at_40[0x40]; 4509 }; 4510 4511 struct mlx5_ifc_xrqc_bits { 4512 u8 state[0x4]; 4513 u8 rlkey[0x1]; 4514 u8 reserved_at_5[0xf]; 4515 u8 topology[0x4]; 4516 u8 reserved_at_18[0x4]; 4517 u8 offload[0x4]; 4518 4519 u8 reserved_at_20[0x8]; 4520 u8 user_index[0x18]; 4521 4522 u8 reserved_at_40[0x8]; 4523 u8 cqn[0x18]; 4524 4525 u8 reserved_at_60[0xa0]; 4526 4527 struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context; 4528 4529 u8 reserved_at_180[0x280]; 4530 4531 struct mlx5_ifc_wq_bits wq; 4532 }; 4533 4534 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits { 4535 struct mlx5_ifc_modify_field_select_bits modify_field_select; 4536 struct mlx5_ifc_resize_field_select_bits resize_field_select; 4537 u8 reserved_at_0[0x20]; 4538 }; 4539 4540 union mlx5_ifc_field_select_802_1_r_roce_auto_bits { 4541 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp; 4542 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp; 4543 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np; 4544 u8 reserved_at_0[0x20]; 4545 }; 4546 4547 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits { 4548 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 4549 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 4550 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 4551 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 4552 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 4553 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 4554 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout; 4555 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout; 4556 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 4557 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 4558 struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs; 4559 u8 reserved_at_0[0x7c0]; 4560 }; 4561 4562 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits { 4563 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout; 4564 u8 reserved_at_0[0x7c0]; 4565 }; 4566 4567 union mlx5_ifc_event_auto_bits { 4568 struct mlx5_ifc_comp_event_bits comp_event; 4569 struct mlx5_ifc_dct_events_bits dct_events; 4570 struct mlx5_ifc_qp_events_bits qp_events; 4571 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event; 4572 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event; 4573 struct mlx5_ifc_cq_error_bits cq_error; 4574 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged; 4575 struct mlx5_ifc_port_state_change_event_bits port_state_change_event; 4576 struct mlx5_ifc_gpio_event_bits gpio_event; 4577 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event; 4578 struct mlx5_ifc_stall_vl_event_bits stall_vl_event; 4579 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event; 4580 u8 reserved_at_0[0xe0]; 4581 }; 4582 4583 struct mlx5_ifc_health_buffer_bits { 4584 u8 reserved_at_0[0x100]; 4585 4586 u8 assert_existptr[0x20]; 4587 4588 u8 assert_callra[0x20]; 4589 4590 u8 reserved_at_140[0x20]; 4591 4592 u8 time[0x20]; 4593 4594 u8 fw_version[0x20]; 4595 4596 u8 hw_id[0x20]; 4597 4598 u8 rfr[0x1]; 4599 u8 reserved_at_1c1[0x3]; 4600 u8 valid[0x1]; 4601 u8 severity[0x3]; 4602 u8 reserved_at_1c8[0x18]; 4603 4604 u8 irisc_index[0x8]; 4605 u8 synd[0x8]; 4606 u8 ext_synd[0x10]; 4607 }; 4608 4609 struct mlx5_ifc_register_loopback_control_bits { 4610 u8 no_lb[0x1]; 4611 u8 reserved_at_1[0x7]; 4612 u8 port[0x8]; 4613 u8 reserved_at_10[0x10]; 4614 4615 u8 reserved_at_20[0x60]; 4616 }; 4617 4618 struct mlx5_ifc_vport_tc_element_bits { 4619 u8 traffic_class[0x4]; 4620 u8 reserved_at_4[0xc]; 4621 u8 vport_number[0x10]; 4622 }; 4623 4624 struct mlx5_ifc_vport_element_bits { 4625 u8 reserved_at_0[0x10]; 4626 u8 vport_number[0x10]; 4627 }; 4628 4629 enum { 4630 TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0, 4631 TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1, 4632 TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2, 4633 }; 4634 4635 struct mlx5_ifc_tsar_element_bits { 4636 u8 reserved_at_0[0x8]; 4637 u8 tsar_type[0x8]; 4638 u8 reserved_at_10[0x10]; 4639 }; 4640 4641 enum { 4642 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0, 4643 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1, 4644 }; 4645 4646 struct mlx5_ifc_teardown_hca_out_bits { 4647 u8 status[0x8]; 4648 u8 reserved_at_8[0x18]; 4649 4650 u8 syndrome[0x20]; 4651 4652 u8 reserved_at_40[0x3f]; 4653 4654 u8 state[0x1]; 4655 }; 4656 4657 enum { 4658 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0, 4659 MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE = 0x1, 4660 MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN = 0x2, 4661 }; 4662 4663 struct mlx5_ifc_teardown_hca_in_bits { 4664 u8 opcode[0x10]; 4665 u8 reserved_at_10[0x10]; 4666 4667 u8 reserved_at_20[0x10]; 4668 u8 op_mod[0x10]; 4669 4670 u8 reserved_at_40[0x10]; 4671 u8 profile[0x10]; 4672 4673 u8 reserved_at_60[0x20]; 4674 }; 4675 4676 struct mlx5_ifc_sqerr2rts_qp_out_bits { 4677 u8 status[0x8]; 4678 u8 reserved_at_8[0x18]; 4679 4680 u8 syndrome[0x20]; 4681 4682 u8 reserved_at_40[0x40]; 4683 }; 4684 4685 struct mlx5_ifc_sqerr2rts_qp_in_bits { 4686 u8 opcode[0x10]; 4687 u8 uid[0x10]; 4688 4689 u8 reserved_at_20[0x10]; 4690 u8 op_mod[0x10]; 4691 4692 u8 reserved_at_40[0x8]; 4693 u8 qpn[0x18]; 4694 4695 u8 reserved_at_60[0x20]; 4696 4697 u8 opt_param_mask[0x20]; 4698 4699 u8 reserved_at_a0[0x20]; 4700 4701 struct mlx5_ifc_qpc_bits qpc; 4702 4703 u8 reserved_at_800[0x80]; 4704 }; 4705 4706 struct mlx5_ifc_sqd2rts_qp_out_bits { 4707 u8 status[0x8]; 4708 u8 reserved_at_8[0x18]; 4709 4710 u8 syndrome[0x20]; 4711 4712 u8 reserved_at_40[0x40]; 4713 }; 4714 4715 struct mlx5_ifc_sqd2rts_qp_in_bits { 4716 u8 opcode[0x10]; 4717 u8 uid[0x10]; 4718 4719 u8 reserved_at_20[0x10]; 4720 u8 op_mod[0x10]; 4721 4722 u8 reserved_at_40[0x8]; 4723 u8 qpn[0x18]; 4724 4725 u8 reserved_at_60[0x20]; 4726 4727 u8 opt_param_mask[0x20]; 4728 4729 u8 reserved_at_a0[0x20]; 4730 4731 struct mlx5_ifc_qpc_bits qpc; 4732 4733 u8 reserved_at_800[0x80]; 4734 }; 4735 4736 struct mlx5_ifc_set_roce_address_out_bits { 4737 u8 status[0x8]; 4738 u8 reserved_at_8[0x18]; 4739 4740 u8 syndrome[0x20]; 4741 4742 u8 reserved_at_40[0x40]; 4743 }; 4744 4745 struct mlx5_ifc_set_roce_address_in_bits { 4746 u8 opcode[0x10]; 4747 u8 reserved_at_10[0x10]; 4748 4749 u8 reserved_at_20[0x10]; 4750 u8 op_mod[0x10]; 4751 4752 u8 roce_address_index[0x10]; 4753 u8 reserved_at_50[0xc]; 4754 u8 vhca_port_num[0x4]; 4755 4756 u8 reserved_at_60[0x20]; 4757 4758 struct mlx5_ifc_roce_addr_layout_bits roce_address; 4759 }; 4760 4761 struct mlx5_ifc_set_mad_demux_out_bits { 4762 u8 status[0x8]; 4763 u8 reserved_at_8[0x18]; 4764 4765 u8 syndrome[0x20]; 4766 4767 u8 reserved_at_40[0x40]; 4768 }; 4769 4770 enum { 4771 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0, 4772 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2, 4773 }; 4774 4775 struct mlx5_ifc_set_mad_demux_in_bits { 4776 u8 opcode[0x10]; 4777 u8 reserved_at_10[0x10]; 4778 4779 u8 reserved_at_20[0x10]; 4780 u8 op_mod[0x10]; 4781 4782 u8 reserved_at_40[0x20]; 4783 4784 u8 reserved_at_60[0x6]; 4785 u8 demux_mode[0x2]; 4786 u8 reserved_at_68[0x18]; 4787 }; 4788 4789 struct mlx5_ifc_set_l2_table_entry_out_bits { 4790 u8 status[0x8]; 4791 u8 reserved_at_8[0x18]; 4792 4793 u8 syndrome[0x20]; 4794 4795 u8 reserved_at_40[0x40]; 4796 }; 4797 4798 struct mlx5_ifc_set_l2_table_entry_in_bits { 4799 u8 opcode[0x10]; 4800 u8 reserved_at_10[0x10]; 4801 4802 u8 reserved_at_20[0x10]; 4803 u8 op_mod[0x10]; 4804 4805 u8 reserved_at_40[0x60]; 4806 4807 u8 reserved_at_a0[0x8]; 4808 u8 table_index[0x18]; 4809 4810 u8 reserved_at_c0[0x20]; 4811 4812 u8 reserved_at_e0[0x10]; 4813 u8 silent_mode_valid[0x1]; 4814 u8 silent_mode[0x1]; 4815 u8 reserved_at_f2[0x1]; 4816 u8 vlan_valid[0x1]; 4817 u8 vlan[0xc]; 4818 4819 struct mlx5_ifc_mac_address_layout_bits mac_address; 4820 4821 u8 reserved_at_140[0xc0]; 4822 }; 4823 4824 struct mlx5_ifc_set_issi_out_bits { 4825 u8 status[0x8]; 4826 u8 reserved_at_8[0x18]; 4827 4828 u8 syndrome[0x20]; 4829 4830 u8 reserved_at_40[0x40]; 4831 }; 4832 4833 struct mlx5_ifc_set_issi_in_bits { 4834 u8 opcode[0x10]; 4835 u8 reserved_at_10[0x10]; 4836 4837 u8 reserved_at_20[0x10]; 4838 u8 op_mod[0x10]; 4839 4840 u8 reserved_at_40[0x10]; 4841 u8 current_issi[0x10]; 4842 4843 u8 reserved_at_60[0x20]; 4844 }; 4845 4846 struct mlx5_ifc_set_hca_cap_out_bits { 4847 u8 status[0x8]; 4848 u8 reserved_at_8[0x18]; 4849 4850 u8 syndrome[0x20]; 4851 4852 u8 reserved_at_40[0x40]; 4853 }; 4854 4855 struct mlx5_ifc_set_hca_cap_in_bits { 4856 u8 opcode[0x10]; 4857 u8 reserved_at_10[0x10]; 4858 4859 u8 reserved_at_20[0x10]; 4860 u8 op_mod[0x10]; 4861 4862 u8 other_function[0x1]; 4863 u8 ec_vf_function[0x1]; 4864 u8 reserved_at_42[0xe]; 4865 u8 function_id[0x10]; 4866 4867 u8 reserved_at_60[0x20]; 4868 4869 union mlx5_ifc_hca_cap_union_bits capability; 4870 }; 4871 4872 enum { 4873 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0, 4874 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1, 4875 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2, 4876 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3, 4877 MLX5_SET_FTE_MODIFY_ENABLE_MASK_IPSEC_OBJ_ID = 0x4 4878 }; 4879 4880 struct mlx5_ifc_set_fte_out_bits { 4881 u8 status[0x8]; 4882 u8 reserved_at_8[0x18]; 4883 4884 u8 syndrome[0x20]; 4885 4886 u8 reserved_at_40[0x40]; 4887 }; 4888 4889 struct mlx5_ifc_set_fte_in_bits { 4890 u8 opcode[0x10]; 4891 u8 reserved_at_10[0x10]; 4892 4893 u8 reserved_at_20[0x10]; 4894 u8 op_mod[0x10]; 4895 4896 u8 other_vport[0x1]; 4897 u8 reserved_at_41[0xf]; 4898 u8 vport_number[0x10]; 4899 4900 u8 reserved_at_60[0x20]; 4901 4902 u8 table_type[0x8]; 4903 u8 reserved_at_88[0x18]; 4904 4905 u8 reserved_at_a0[0x8]; 4906 u8 table_id[0x18]; 4907 4908 u8 ignore_flow_level[0x1]; 4909 u8 reserved_at_c1[0x17]; 4910 u8 modify_enable_mask[0x8]; 4911 4912 u8 reserved_at_e0[0x20]; 4913 4914 u8 flow_index[0x20]; 4915 4916 u8 reserved_at_120[0xe0]; 4917 4918 struct mlx5_ifc_flow_context_bits flow_context; 4919 }; 4920 4921 struct mlx5_ifc_rts2rts_qp_out_bits { 4922 u8 status[0x8]; 4923 u8 reserved_at_8[0x18]; 4924 4925 u8 syndrome[0x20]; 4926 4927 u8 reserved_at_40[0x20]; 4928 u8 ece[0x20]; 4929 }; 4930 4931 struct mlx5_ifc_rts2rts_qp_in_bits { 4932 u8 opcode[0x10]; 4933 u8 uid[0x10]; 4934 4935 u8 reserved_at_20[0x10]; 4936 u8 op_mod[0x10]; 4937 4938 u8 reserved_at_40[0x8]; 4939 u8 qpn[0x18]; 4940 4941 u8 reserved_at_60[0x20]; 4942 4943 u8 opt_param_mask[0x20]; 4944 4945 u8 ece[0x20]; 4946 4947 struct mlx5_ifc_qpc_bits qpc; 4948 4949 u8 reserved_at_800[0x80]; 4950 }; 4951 4952 struct mlx5_ifc_rtr2rts_qp_out_bits { 4953 u8 status[0x8]; 4954 u8 reserved_at_8[0x18]; 4955 4956 u8 syndrome[0x20]; 4957 4958 u8 reserved_at_40[0x20]; 4959 u8 ece[0x20]; 4960 }; 4961 4962 struct mlx5_ifc_rtr2rts_qp_in_bits { 4963 u8 opcode[0x10]; 4964 u8 uid[0x10]; 4965 4966 u8 reserved_at_20[0x10]; 4967 u8 op_mod[0x10]; 4968 4969 u8 reserved_at_40[0x8]; 4970 u8 qpn[0x18]; 4971 4972 u8 reserved_at_60[0x20]; 4973 4974 u8 opt_param_mask[0x20]; 4975 4976 u8 ece[0x20]; 4977 4978 struct mlx5_ifc_qpc_bits qpc; 4979 4980 u8 reserved_at_800[0x80]; 4981 }; 4982 4983 struct mlx5_ifc_rst2init_qp_out_bits { 4984 u8 status[0x8]; 4985 u8 reserved_at_8[0x18]; 4986 4987 u8 syndrome[0x20]; 4988 4989 u8 reserved_at_40[0x20]; 4990 u8 ece[0x20]; 4991 }; 4992 4993 struct mlx5_ifc_rst2init_qp_in_bits { 4994 u8 opcode[0x10]; 4995 u8 uid[0x10]; 4996 4997 u8 reserved_at_20[0x10]; 4998 u8 op_mod[0x10]; 4999 5000 u8 reserved_at_40[0x8]; 5001 u8 qpn[0x18]; 5002 5003 u8 reserved_at_60[0x20]; 5004 5005 u8 opt_param_mask[0x20]; 5006 5007 u8 ece[0x20]; 5008 5009 struct mlx5_ifc_qpc_bits qpc; 5010 5011 u8 reserved_at_800[0x80]; 5012 }; 5013 5014 struct mlx5_ifc_query_xrq_out_bits { 5015 u8 status[0x8]; 5016 u8 reserved_at_8[0x18]; 5017 5018 u8 syndrome[0x20]; 5019 5020 u8 reserved_at_40[0x40]; 5021 5022 struct mlx5_ifc_xrqc_bits xrq_context; 5023 }; 5024 5025 struct mlx5_ifc_query_xrq_in_bits { 5026 u8 opcode[0x10]; 5027 u8 reserved_at_10[0x10]; 5028 5029 u8 reserved_at_20[0x10]; 5030 u8 op_mod[0x10]; 5031 5032 u8 reserved_at_40[0x8]; 5033 u8 xrqn[0x18]; 5034 5035 u8 reserved_at_60[0x20]; 5036 }; 5037 5038 struct mlx5_ifc_query_xrc_srq_out_bits { 5039 u8 status[0x8]; 5040 u8 reserved_at_8[0x18]; 5041 5042 u8 syndrome[0x20]; 5043 5044 u8 reserved_at_40[0x40]; 5045 5046 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 5047 5048 u8 reserved_at_280[0x600]; 5049 5050 u8 pas[][0x40]; 5051 }; 5052 5053 struct mlx5_ifc_query_xrc_srq_in_bits { 5054 u8 opcode[0x10]; 5055 u8 reserved_at_10[0x10]; 5056 5057 u8 reserved_at_20[0x10]; 5058 u8 op_mod[0x10]; 5059 5060 u8 reserved_at_40[0x8]; 5061 u8 xrc_srqn[0x18]; 5062 5063 u8 reserved_at_60[0x20]; 5064 }; 5065 5066 enum { 5067 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0, 5068 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1, 5069 }; 5070 5071 struct mlx5_ifc_query_vport_state_out_bits { 5072 u8 status[0x8]; 5073 u8 reserved_at_8[0x18]; 5074 5075 u8 syndrome[0x20]; 5076 5077 u8 reserved_at_40[0x20]; 5078 5079 u8 reserved_at_60[0x18]; 5080 u8 admin_state[0x4]; 5081 u8 state[0x4]; 5082 }; 5083 5084 enum { 5085 MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT = 0x0, 5086 MLX5_VPORT_STATE_OP_MOD_ESW_VPORT = 0x1, 5087 MLX5_VPORT_STATE_OP_MOD_UPLINK = 0x2, 5088 }; 5089 5090 struct mlx5_ifc_arm_monitor_counter_in_bits { 5091 u8 opcode[0x10]; 5092 u8 uid[0x10]; 5093 5094 u8 reserved_at_20[0x10]; 5095 u8 op_mod[0x10]; 5096 5097 u8 reserved_at_40[0x20]; 5098 5099 u8 reserved_at_60[0x20]; 5100 }; 5101 5102 struct mlx5_ifc_arm_monitor_counter_out_bits { 5103 u8 status[0x8]; 5104 u8 reserved_at_8[0x18]; 5105 5106 u8 syndrome[0x20]; 5107 5108 u8 reserved_at_40[0x40]; 5109 }; 5110 5111 enum { 5112 MLX5_QUERY_MONITOR_CNT_TYPE_PPCNT = 0x0, 5113 MLX5_QUERY_MONITOR_CNT_TYPE_Q_COUNTER = 0x1, 5114 }; 5115 5116 enum mlx5_monitor_counter_ppcnt { 5117 MLX5_QUERY_MONITOR_PPCNT_IN_RANGE_LENGTH_ERRORS = 0x0, 5118 MLX5_QUERY_MONITOR_PPCNT_OUT_OF_RANGE_LENGTH_FIELD = 0x1, 5119 MLX5_QUERY_MONITOR_PPCNT_FRAME_TOO_LONG_ERRORS = 0x2, 5120 MLX5_QUERY_MONITOR_PPCNT_FRAME_CHECK_SEQUENCE_ERRORS = 0x3, 5121 MLX5_QUERY_MONITOR_PPCNT_ALIGNMENT_ERRORS = 0x4, 5122 MLX5_QUERY_MONITOR_PPCNT_IF_OUT_DISCARDS = 0x5, 5123 }; 5124 5125 enum { 5126 MLX5_QUERY_MONITOR_Q_COUNTER_RX_OUT_OF_BUFFER = 0x4, 5127 }; 5128 5129 struct mlx5_ifc_monitor_counter_output_bits { 5130 u8 reserved_at_0[0x4]; 5131 u8 type[0x4]; 5132 u8 reserved_at_8[0x8]; 5133 u8 counter[0x10]; 5134 5135 u8 counter_group_id[0x20]; 5136 }; 5137 5138 #define MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 (6) 5139 #define MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1 (1) 5140 #define MLX5_CMD_SET_MONITOR_NUM_COUNTER (MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 +\ 5141 MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1) 5142 5143 struct mlx5_ifc_set_monitor_counter_in_bits { 5144 u8 opcode[0x10]; 5145 u8 uid[0x10]; 5146 5147 u8 reserved_at_20[0x10]; 5148 u8 op_mod[0x10]; 5149 5150 u8 reserved_at_40[0x10]; 5151 u8 num_of_counters[0x10]; 5152 5153 u8 reserved_at_60[0x20]; 5154 5155 struct mlx5_ifc_monitor_counter_output_bits monitor_counter[MLX5_CMD_SET_MONITOR_NUM_COUNTER]; 5156 }; 5157 5158 struct mlx5_ifc_set_monitor_counter_out_bits { 5159 u8 status[0x8]; 5160 u8 reserved_at_8[0x18]; 5161 5162 u8 syndrome[0x20]; 5163 5164 u8 reserved_at_40[0x40]; 5165 }; 5166 5167 struct mlx5_ifc_query_vport_state_in_bits { 5168 u8 opcode[0x10]; 5169 u8 reserved_at_10[0x10]; 5170 5171 u8 reserved_at_20[0x10]; 5172 u8 op_mod[0x10]; 5173 5174 u8 other_vport[0x1]; 5175 u8 reserved_at_41[0xf]; 5176 u8 vport_number[0x10]; 5177 5178 u8 reserved_at_60[0x20]; 5179 }; 5180 5181 struct mlx5_ifc_query_vnic_env_out_bits { 5182 u8 status[0x8]; 5183 u8 reserved_at_8[0x18]; 5184 5185 u8 syndrome[0x20]; 5186 5187 u8 reserved_at_40[0x40]; 5188 5189 struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env; 5190 }; 5191 5192 enum { 5193 MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS = 0x0, 5194 }; 5195 5196 struct mlx5_ifc_query_vnic_env_in_bits { 5197 u8 opcode[0x10]; 5198 u8 reserved_at_10[0x10]; 5199 5200 u8 reserved_at_20[0x10]; 5201 u8 op_mod[0x10]; 5202 5203 u8 other_vport[0x1]; 5204 u8 reserved_at_41[0xf]; 5205 u8 vport_number[0x10]; 5206 5207 u8 reserved_at_60[0x20]; 5208 }; 5209 5210 struct mlx5_ifc_query_vport_counter_out_bits { 5211 u8 status[0x8]; 5212 u8 reserved_at_8[0x18]; 5213 5214 u8 syndrome[0x20]; 5215 5216 u8 reserved_at_40[0x40]; 5217 5218 struct mlx5_ifc_traffic_counter_bits received_errors; 5219 5220 struct mlx5_ifc_traffic_counter_bits transmit_errors; 5221 5222 struct mlx5_ifc_traffic_counter_bits received_ib_unicast; 5223 5224 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast; 5225 5226 struct mlx5_ifc_traffic_counter_bits received_ib_multicast; 5227 5228 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast; 5229 5230 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast; 5231 5232 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast; 5233 5234 struct mlx5_ifc_traffic_counter_bits received_eth_unicast; 5235 5236 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast; 5237 5238 struct mlx5_ifc_traffic_counter_bits received_eth_multicast; 5239 5240 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast; 5241 5242 struct mlx5_ifc_traffic_counter_bits local_loopback; 5243 5244 u8 reserved_at_700[0x980]; 5245 }; 5246 5247 enum { 5248 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0, 5249 }; 5250 5251 struct mlx5_ifc_query_vport_counter_in_bits { 5252 u8 opcode[0x10]; 5253 u8 reserved_at_10[0x10]; 5254 5255 u8 reserved_at_20[0x10]; 5256 u8 op_mod[0x10]; 5257 5258 u8 other_vport[0x1]; 5259 u8 reserved_at_41[0xb]; 5260 u8 port_num[0x4]; 5261 u8 vport_number[0x10]; 5262 5263 u8 reserved_at_60[0x60]; 5264 5265 u8 clear[0x1]; 5266 u8 reserved_at_c1[0x1f]; 5267 5268 u8 reserved_at_e0[0x20]; 5269 }; 5270 5271 struct mlx5_ifc_query_tis_out_bits { 5272 u8 status[0x8]; 5273 u8 reserved_at_8[0x18]; 5274 5275 u8 syndrome[0x20]; 5276 5277 u8 reserved_at_40[0x40]; 5278 5279 struct mlx5_ifc_tisc_bits tis_context; 5280 }; 5281 5282 struct mlx5_ifc_query_tis_in_bits { 5283 u8 opcode[0x10]; 5284 u8 reserved_at_10[0x10]; 5285 5286 u8 reserved_at_20[0x10]; 5287 u8 op_mod[0x10]; 5288 5289 u8 reserved_at_40[0x8]; 5290 u8 tisn[0x18]; 5291 5292 u8 reserved_at_60[0x20]; 5293 }; 5294 5295 struct mlx5_ifc_query_tir_out_bits { 5296 u8 status[0x8]; 5297 u8 reserved_at_8[0x18]; 5298 5299 u8 syndrome[0x20]; 5300 5301 u8 reserved_at_40[0xc0]; 5302 5303 struct mlx5_ifc_tirc_bits tir_context; 5304 }; 5305 5306 struct mlx5_ifc_query_tir_in_bits { 5307 u8 opcode[0x10]; 5308 u8 reserved_at_10[0x10]; 5309 5310 u8 reserved_at_20[0x10]; 5311 u8 op_mod[0x10]; 5312 5313 u8 reserved_at_40[0x8]; 5314 u8 tirn[0x18]; 5315 5316 u8 reserved_at_60[0x20]; 5317 }; 5318 5319 struct mlx5_ifc_query_srq_out_bits { 5320 u8 status[0x8]; 5321 u8 reserved_at_8[0x18]; 5322 5323 u8 syndrome[0x20]; 5324 5325 u8 reserved_at_40[0x40]; 5326 5327 struct mlx5_ifc_srqc_bits srq_context_entry; 5328 5329 u8 reserved_at_280[0x600]; 5330 5331 u8 pas[][0x40]; 5332 }; 5333 5334 struct mlx5_ifc_query_srq_in_bits { 5335 u8 opcode[0x10]; 5336 u8 reserved_at_10[0x10]; 5337 5338 u8 reserved_at_20[0x10]; 5339 u8 op_mod[0x10]; 5340 5341 u8 reserved_at_40[0x8]; 5342 u8 srqn[0x18]; 5343 5344 u8 reserved_at_60[0x20]; 5345 }; 5346 5347 struct mlx5_ifc_query_sq_out_bits { 5348 u8 status[0x8]; 5349 u8 reserved_at_8[0x18]; 5350 5351 u8 syndrome[0x20]; 5352 5353 u8 reserved_at_40[0xc0]; 5354 5355 struct mlx5_ifc_sqc_bits sq_context; 5356 }; 5357 5358 struct mlx5_ifc_query_sq_in_bits { 5359 u8 opcode[0x10]; 5360 u8 reserved_at_10[0x10]; 5361 5362 u8 reserved_at_20[0x10]; 5363 u8 op_mod[0x10]; 5364 5365 u8 reserved_at_40[0x8]; 5366 u8 sqn[0x18]; 5367 5368 u8 reserved_at_60[0x20]; 5369 }; 5370 5371 struct mlx5_ifc_query_special_contexts_out_bits { 5372 u8 status[0x8]; 5373 u8 reserved_at_8[0x18]; 5374 5375 u8 syndrome[0x20]; 5376 5377 u8 dump_fill_mkey[0x20]; 5378 5379 u8 resd_lkey[0x20]; 5380 5381 u8 null_mkey[0x20]; 5382 5383 u8 terminate_scatter_list_mkey[0x20]; 5384 5385 u8 repeated_mkey[0x20]; 5386 5387 u8 reserved_at_a0[0x20]; 5388 }; 5389 5390 struct mlx5_ifc_query_special_contexts_in_bits { 5391 u8 opcode[0x10]; 5392 u8 reserved_at_10[0x10]; 5393 5394 u8 reserved_at_20[0x10]; 5395 u8 op_mod[0x10]; 5396 5397 u8 reserved_at_40[0x40]; 5398 }; 5399 5400 struct mlx5_ifc_query_scheduling_element_out_bits { 5401 u8 opcode[0x10]; 5402 u8 reserved_at_10[0x10]; 5403 5404 u8 reserved_at_20[0x10]; 5405 u8 op_mod[0x10]; 5406 5407 u8 reserved_at_40[0xc0]; 5408 5409 struct mlx5_ifc_scheduling_context_bits scheduling_context; 5410 5411 u8 reserved_at_300[0x100]; 5412 }; 5413 5414 enum { 5415 SCHEDULING_HIERARCHY_E_SWITCH = 0x2, 5416 SCHEDULING_HIERARCHY_NIC = 0x3, 5417 }; 5418 5419 struct mlx5_ifc_query_scheduling_element_in_bits { 5420 u8 opcode[0x10]; 5421 u8 reserved_at_10[0x10]; 5422 5423 u8 reserved_at_20[0x10]; 5424 u8 op_mod[0x10]; 5425 5426 u8 scheduling_hierarchy[0x8]; 5427 u8 reserved_at_48[0x18]; 5428 5429 u8 scheduling_element_id[0x20]; 5430 5431 u8 reserved_at_80[0x180]; 5432 }; 5433 5434 struct mlx5_ifc_query_rqt_out_bits { 5435 u8 status[0x8]; 5436 u8 reserved_at_8[0x18]; 5437 5438 u8 syndrome[0x20]; 5439 5440 u8 reserved_at_40[0xc0]; 5441 5442 struct mlx5_ifc_rqtc_bits rqt_context; 5443 }; 5444 5445 struct mlx5_ifc_query_rqt_in_bits { 5446 u8 opcode[0x10]; 5447 u8 reserved_at_10[0x10]; 5448 5449 u8 reserved_at_20[0x10]; 5450 u8 op_mod[0x10]; 5451 5452 u8 reserved_at_40[0x8]; 5453 u8 rqtn[0x18]; 5454 5455 u8 reserved_at_60[0x20]; 5456 }; 5457 5458 struct mlx5_ifc_query_rq_out_bits { 5459 u8 status[0x8]; 5460 u8 reserved_at_8[0x18]; 5461 5462 u8 syndrome[0x20]; 5463 5464 u8 reserved_at_40[0xc0]; 5465 5466 struct mlx5_ifc_rqc_bits rq_context; 5467 }; 5468 5469 struct mlx5_ifc_query_rq_in_bits { 5470 u8 opcode[0x10]; 5471 u8 reserved_at_10[0x10]; 5472 5473 u8 reserved_at_20[0x10]; 5474 u8 op_mod[0x10]; 5475 5476 u8 reserved_at_40[0x8]; 5477 u8 rqn[0x18]; 5478 5479 u8 reserved_at_60[0x20]; 5480 }; 5481 5482 struct mlx5_ifc_query_roce_address_out_bits { 5483 u8 status[0x8]; 5484 u8 reserved_at_8[0x18]; 5485 5486 u8 syndrome[0x20]; 5487 5488 u8 reserved_at_40[0x40]; 5489 5490 struct mlx5_ifc_roce_addr_layout_bits roce_address; 5491 }; 5492 5493 struct mlx5_ifc_query_roce_address_in_bits { 5494 u8 opcode[0x10]; 5495 u8 reserved_at_10[0x10]; 5496 5497 u8 reserved_at_20[0x10]; 5498 u8 op_mod[0x10]; 5499 5500 u8 roce_address_index[0x10]; 5501 u8 reserved_at_50[0xc]; 5502 u8 vhca_port_num[0x4]; 5503 5504 u8 reserved_at_60[0x20]; 5505 }; 5506 5507 struct mlx5_ifc_query_rmp_out_bits { 5508 u8 status[0x8]; 5509 u8 reserved_at_8[0x18]; 5510 5511 u8 syndrome[0x20]; 5512 5513 u8 reserved_at_40[0xc0]; 5514 5515 struct mlx5_ifc_rmpc_bits rmp_context; 5516 }; 5517 5518 struct mlx5_ifc_query_rmp_in_bits { 5519 u8 opcode[0x10]; 5520 u8 reserved_at_10[0x10]; 5521 5522 u8 reserved_at_20[0x10]; 5523 u8 op_mod[0x10]; 5524 5525 u8 reserved_at_40[0x8]; 5526 u8 rmpn[0x18]; 5527 5528 u8 reserved_at_60[0x20]; 5529 }; 5530 5531 struct mlx5_ifc_cqe_error_syndrome_bits { 5532 u8 hw_error_syndrome[0x8]; 5533 u8 hw_syndrome_type[0x4]; 5534 u8 reserved_at_c[0x4]; 5535 u8 vendor_error_syndrome[0x8]; 5536 u8 syndrome[0x8]; 5537 }; 5538 5539 struct mlx5_ifc_qp_context_extension_bits { 5540 u8 reserved_at_0[0x60]; 5541 5542 struct mlx5_ifc_cqe_error_syndrome_bits error_syndrome; 5543 5544 u8 reserved_at_80[0x580]; 5545 }; 5546 5547 struct mlx5_ifc_qpc_extension_and_pas_list_in_bits { 5548 struct mlx5_ifc_qp_context_extension_bits qpc_data_extension; 5549 5550 u8 pas[0][0x40]; 5551 }; 5552 5553 struct mlx5_ifc_qp_pas_list_in_bits { 5554 struct mlx5_ifc_cmd_pas_bits pas[0]; 5555 }; 5556 5557 union mlx5_ifc_qp_pas_or_qpc_ext_and_pas_bits { 5558 struct mlx5_ifc_qp_pas_list_in_bits qp_pas_list; 5559 struct mlx5_ifc_qpc_extension_and_pas_list_in_bits qpc_ext_and_pas_list; 5560 }; 5561 5562 struct mlx5_ifc_query_qp_out_bits { 5563 u8 status[0x8]; 5564 u8 reserved_at_8[0x18]; 5565 5566 u8 syndrome[0x20]; 5567 5568 u8 reserved_at_40[0x40]; 5569 5570 u8 opt_param_mask[0x20]; 5571 5572 u8 ece[0x20]; 5573 5574 struct mlx5_ifc_qpc_bits qpc; 5575 5576 u8 reserved_at_800[0x80]; 5577 5578 union mlx5_ifc_qp_pas_or_qpc_ext_and_pas_bits qp_pas_or_qpc_ext_and_pas; 5579 }; 5580 5581 struct mlx5_ifc_query_qp_in_bits { 5582 u8 opcode[0x10]; 5583 u8 reserved_at_10[0x10]; 5584 5585 u8 reserved_at_20[0x10]; 5586 u8 op_mod[0x10]; 5587 5588 u8 qpc_ext[0x1]; 5589 u8 reserved_at_41[0x7]; 5590 u8 qpn[0x18]; 5591 5592 u8 reserved_at_60[0x20]; 5593 }; 5594 5595 struct mlx5_ifc_query_q_counter_out_bits { 5596 u8 status[0x8]; 5597 u8 reserved_at_8[0x18]; 5598 5599 u8 syndrome[0x20]; 5600 5601 u8 reserved_at_40[0x40]; 5602 5603 u8 rx_write_requests[0x20]; 5604 5605 u8 reserved_at_a0[0x20]; 5606 5607 u8 rx_read_requests[0x20]; 5608 5609 u8 reserved_at_e0[0x20]; 5610 5611 u8 rx_atomic_requests[0x20]; 5612 5613 u8 reserved_at_120[0x20]; 5614 5615 u8 rx_dct_connect[0x20]; 5616 5617 u8 reserved_at_160[0x20]; 5618 5619 u8 out_of_buffer[0x20]; 5620 5621 u8 reserved_at_1a0[0x20]; 5622 5623 u8 out_of_sequence[0x20]; 5624 5625 u8 reserved_at_1e0[0x20]; 5626 5627 u8 duplicate_request[0x20]; 5628 5629 u8 reserved_at_220[0x20]; 5630 5631 u8 rnr_nak_retry_err[0x20]; 5632 5633 u8 reserved_at_260[0x20]; 5634 5635 u8 packet_seq_err[0x20]; 5636 5637 u8 reserved_at_2a0[0x20]; 5638 5639 u8 implied_nak_seq_err[0x20]; 5640 5641 u8 reserved_at_2e0[0x20]; 5642 5643 u8 local_ack_timeout_err[0x20]; 5644 5645 u8 reserved_at_320[0x60]; 5646 5647 u8 req_rnr_retries_exceeded[0x20]; 5648 5649 u8 reserved_at_3a0[0x20]; 5650 5651 u8 resp_local_length_error[0x20]; 5652 5653 u8 req_local_length_error[0x20]; 5654 5655 u8 resp_local_qp_error[0x20]; 5656 5657 u8 local_operation_error[0x20]; 5658 5659 u8 resp_local_protection[0x20]; 5660 5661 u8 req_local_protection[0x20]; 5662 5663 u8 resp_cqe_error[0x20]; 5664 5665 u8 req_cqe_error[0x20]; 5666 5667 u8 req_mw_binding[0x20]; 5668 5669 u8 req_bad_response[0x20]; 5670 5671 u8 req_remote_invalid_request[0x20]; 5672 5673 u8 resp_remote_invalid_request[0x20]; 5674 5675 u8 req_remote_access_errors[0x20]; 5676 5677 u8 resp_remote_access_errors[0x20]; 5678 5679 u8 req_remote_operation_errors[0x20]; 5680 5681 u8 req_transport_retries_exceeded[0x20]; 5682 5683 u8 cq_overflow[0x20]; 5684 5685 u8 resp_cqe_flush_error[0x20]; 5686 5687 u8 req_cqe_flush_error[0x20]; 5688 5689 u8 reserved_at_620[0x20]; 5690 5691 u8 roce_adp_retrans[0x20]; 5692 5693 u8 roce_adp_retrans_to[0x20]; 5694 5695 u8 roce_slow_restart[0x20]; 5696 5697 u8 roce_slow_restart_cnps[0x20]; 5698 5699 u8 roce_slow_restart_trans[0x20]; 5700 5701 u8 reserved_at_6e0[0x120]; 5702 }; 5703 5704 struct mlx5_ifc_query_q_counter_in_bits { 5705 u8 opcode[0x10]; 5706 u8 reserved_at_10[0x10]; 5707 5708 u8 reserved_at_20[0x10]; 5709 u8 op_mod[0x10]; 5710 5711 u8 other_vport[0x1]; 5712 u8 reserved_at_41[0xf]; 5713 u8 vport_number[0x10]; 5714 5715 u8 reserved_at_60[0x60]; 5716 5717 u8 clear[0x1]; 5718 u8 aggregate[0x1]; 5719 u8 reserved_at_c2[0x1e]; 5720 5721 u8 reserved_at_e0[0x18]; 5722 u8 counter_set_id[0x8]; 5723 }; 5724 5725 struct mlx5_ifc_query_pages_out_bits { 5726 u8 status[0x8]; 5727 u8 reserved_at_8[0x18]; 5728 5729 u8 syndrome[0x20]; 5730 5731 u8 embedded_cpu_function[0x1]; 5732 u8 reserved_at_41[0xf]; 5733 u8 function_id[0x10]; 5734 5735 u8 num_pages[0x20]; 5736 }; 5737 5738 enum { 5739 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1, 5740 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2, 5741 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3, 5742 }; 5743 5744 struct mlx5_ifc_query_pages_in_bits { 5745 u8 opcode[0x10]; 5746 u8 reserved_at_10[0x10]; 5747 5748 u8 reserved_at_20[0x10]; 5749 u8 op_mod[0x10]; 5750 5751 u8 embedded_cpu_function[0x1]; 5752 u8 reserved_at_41[0xf]; 5753 u8 function_id[0x10]; 5754 5755 u8 reserved_at_60[0x20]; 5756 }; 5757 5758 struct mlx5_ifc_query_nic_vport_context_out_bits { 5759 u8 status[0x8]; 5760 u8 reserved_at_8[0x18]; 5761 5762 u8 syndrome[0x20]; 5763 5764 u8 reserved_at_40[0x40]; 5765 5766 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 5767 }; 5768 5769 struct mlx5_ifc_query_nic_vport_context_in_bits { 5770 u8 opcode[0x10]; 5771 u8 reserved_at_10[0x10]; 5772 5773 u8 reserved_at_20[0x10]; 5774 u8 op_mod[0x10]; 5775 5776 u8 other_vport[0x1]; 5777 u8 reserved_at_41[0xf]; 5778 u8 vport_number[0x10]; 5779 5780 u8 reserved_at_60[0x5]; 5781 u8 allowed_list_type[0x3]; 5782 u8 reserved_at_68[0x18]; 5783 }; 5784 5785 struct mlx5_ifc_query_mkey_out_bits { 5786 u8 status[0x8]; 5787 u8 reserved_at_8[0x18]; 5788 5789 u8 syndrome[0x20]; 5790 5791 u8 reserved_at_40[0x40]; 5792 5793 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 5794 5795 u8 reserved_at_280[0x600]; 5796 5797 u8 bsf0_klm0_pas_mtt0_1[16][0x8]; 5798 5799 u8 bsf1_klm1_pas_mtt2_3[16][0x8]; 5800 }; 5801 5802 struct mlx5_ifc_query_mkey_in_bits { 5803 u8 opcode[0x10]; 5804 u8 reserved_at_10[0x10]; 5805 5806 u8 reserved_at_20[0x10]; 5807 u8 op_mod[0x10]; 5808 5809 u8 reserved_at_40[0x8]; 5810 u8 mkey_index[0x18]; 5811 5812 u8 pg_access[0x1]; 5813 u8 reserved_at_61[0x1f]; 5814 }; 5815 5816 struct mlx5_ifc_query_mad_demux_out_bits { 5817 u8 status[0x8]; 5818 u8 reserved_at_8[0x18]; 5819 5820 u8 syndrome[0x20]; 5821 5822 u8 reserved_at_40[0x40]; 5823 5824 u8 mad_dumux_parameters_block[0x20]; 5825 }; 5826 5827 struct mlx5_ifc_query_mad_demux_in_bits { 5828 u8 opcode[0x10]; 5829 u8 reserved_at_10[0x10]; 5830 5831 u8 reserved_at_20[0x10]; 5832 u8 op_mod[0x10]; 5833 5834 u8 reserved_at_40[0x40]; 5835 }; 5836 5837 struct mlx5_ifc_query_l2_table_entry_out_bits { 5838 u8 status[0x8]; 5839 u8 reserved_at_8[0x18]; 5840 5841 u8 syndrome[0x20]; 5842 5843 u8 reserved_at_40[0xa0]; 5844 5845 u8 reserved_at_e0[0x13]; 5846 u8 vlan_valid[0x1]; 5847 u8 vlan[0xc]; 5848 5849 struct mlx5_ifc_mac_address_layout_bits mac_address; 5850 5851 u8 reserved_at_140[0xc0]; 5852 }; 5853 5854 struct mlx5_ifc_query_l2_table_entry_in_bits { 5855 u8 opcode[0x10]; 5856 u8 reserved_at_10[0x10]; 5857 5858 u8 reserved_at_20[0x10]; 5859 u8 op_mod[0x10]; 5860 5861 u8 reserved_at_40[0x60]; 5862 5863 u8 reserved_at_a0[0x8]; 5864 u8 table_index[0x18]; 5865 5866 u8 reserved_at_c0[0x140]; 5867 }; 5868 5869 struct mlx5_ifc_query_issi_out_bits { 5870 u8 status[0x8]; 5871 u8 reserved_at_8[0x18]; 5872 5873 u8 syndrome[0x20]; 5874 5875 u8 reserved_at_40[0x10]; 5876 u8 current_issi[0x10]; 5877 5878 u8 reserved_at_60[0xa0]; 5879 5880 u8 reserved_at_100[76][0x8]; 5881 u8 supported_issi_dw0[0x20]; 5882 }; 5883 5884 struct mlx5_ifc_query_issi_in_bits { 5885 u8 opcode[0x10]; 5886 u8 reserved_at_10[0x10]; 5887 5888 u8 reserved_at_20[0x10]; 5889 u8 op_mod[0x10]; 5890 5891 u8 reserved_at_40[0x40]; 5892 }; 5893 5894 struct mlx5_ifc_set_driver_version_out_bits { 5895 u8 status[0x8]; 5896 u8 reserved_0[0x18]; 5897 5898 u8 syndrome[0x20]; 5899 u8 reserved_1[0x40]; 5900 }; 5901 5902 struct mlx5_ifc_set_driver_version_in_bits { 5903 u8 opcode[0x10]; 5904 u8 reserved_0[0x10]; 5905 5906 u8 reserved_1[0x10]; 5907 u8 op_mod[0x10]; 5908 5909 u8 reserved_2[0x40]; 5910 u8 driver_version[64][0x8]; 5911 }; 5912 5913 struct mlx5_ifc_query_hca_vport_pkey_out_bits { 5914 u8 status[0x8]; 5915 u8 reserved_at_8[0x18]; 5916 5917 u8 syndrome[0x20]; 5918 5919 u8 reserved_at_40[0x40]; 5920 5921 struct mlx5_ifc_pkey_bits pkey[]; 5922 }; 5923 5924 struct mlx5_ifc_query_hca_vport_pkey_in_bits { 5925 u8 opcode[0x10]; 5926 u8 reserved_at_10[0x10]; 5927 5928 u8 reserved_at_20[0x10]; 5929 u8 op_mod[0x10]; 5930 5931 u8 other_vport[0x1]; 5932 u8 reserved_at_41[0xb]; 5933 u8 port_num[0x4]; 5934 u8 vport_number[0x10]; 5935 5936 u8 reserved_at_60[0x10]; 5937 u8 pkey_index[0x10]; 5938 }; 5939 5940 enum { 5941 MLX5_HCA_VPORT_SEL_PORT_GUID = 1 << 0, 5942 MLX5_HCA_VPORT_SEL_NODE_GUID = 1 << 1, 5943 MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2, 5944 }; 5945 5946 struct mlx5_ifc_query_hca_vport_gid_out_bits { 5947 u8 status[0x8]; 5948 u8 reserved_at_8[0x18]; 5949 5950 u8 syndrome[0x20]; 5951 5952 u8 reserved_at_40[0x20]; 5953 5954 u8 gids_num[0x10]; 5955 u8 reserved_at_70[0x10]; 5956 5957 struct mlx5_ifc_array128_auto_bits gid[]; 5958 }; 5959 5960 struct mlx5_ifc_query_hca_vport_gid_in_bits { 5961 u8 opcode[0x10]; 5962 u8 reserved_at_10[0x10]; 5963 5964 u8 reserved_at_20[0x10]; 5965 u8 op_mod[0x10]; 5966 5967 u8 other_vport[0x1]; 5968 u8 reserved_at_41[0xb]; 5969 u8 port_num[0x4]; 5970 u8 vport_number[0x10]; 5971 5972 u8 reserved_at_60[0x10]; 5973 u8 gid_index[0x10]; 5974 }; 5975 5976 struct mlx5_ifc_query_hca_vport_context_out_bits { 5977 u8 status[0x8]; 5978 u8 reserved_at_8[0x18]; 5979 5980 u8 syndrome[0x20]; 5981 5982 u8 reserved_at_40[0x40]; 5983 5984 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 5985 }; 5986 5987 struct mlx5_ifc_query_hca_vport_context_in_bits { 5988 u8 opcode[0x10]; 5989 u8 reserved_at_10[0x10]; 5990 5991 u8 reserved_at_20[0x10]; 5992 u8 op_mod[0x10]; 5993 5994 u8 other_vport[0x1]; 5995 u8 reserved_at_41[0xb]; 5996 u8 port_num[0x4]; 5997 u8 vport_number[0x10]; 5998 5999 u8 reserved_at_60[0x20]; 6000 }; 6001 6002 struct mlx5_ifc_query_hca_cap_out_bits { 6003 u8 status[0x8]; 6004 u8 reserved_at_8[0x18]; 6005 6006 u8 syndrome[0x20]; 6007 6008 u8 reserved_at_40[0x40]; 6009 6010 union mlx5_ifc_hca_cap_union_bits capability; 6011 }; 6012 6013 struct mlx5_ifc_query_hca_cap_in_bits { 6014 u8 opcode[0x10]; 6015 u8 reserved_at_10[0x10]; 6016 6017 u8 reserved_at_20[0x10]; 6018 u8 op_mod[0x10]; 6019 6020 u8 other_function[0x1]; 6021 u8 ec_vf_function[0x1]; 6022 u8 reserved_at_42[0xe]; 6023 u8 function_id[0x10]; 6024 6025 u8 reserved_at_60[0x20]; 6026 }; 6027 6028 struct mlx5_ifc_other_hca_cap_bits { 6029 u8 roce[0x1]; 6030 u8 reserved_at_1[0x27f]; 6031 }; 6032 6033 struct mlx5_ifc_query_other_hca_cap_out_bits { 6034 u8 status[0x8]; 6035 u8 reserved_at_8[0x18]; 6036 6037 u8 syndrome[0x20]; 6038 6039 u8 reserved_at_40[0x40]; 6040 6041 struct mlx5_ifc_other_hca_cap_bits other_capability; 6042 }; 6043 6044 struct mlx5_ifc_query_other_hca_cap_in_bits { 6045 u8 opcode[0x10]; 6046 u8 reserved_at_10[0x10]; 6047 6048 u8 reserved_at_20[0x10]; 6049 u8 op_mod[0x10]; 6050 6051 u8 reserved_at_40[0x10]; 6052 u8 function_id[0x10]; 6053 6054 u8 reserved_at_60[0x20]; 6055 }; 6056 6057 struct mlx5_ifc_modify_other_hca_cap_out_bits { 6058 u8 status[0x8]; 6059 u8 reserved_at_8[0x18]; 6060 6061 u8 syndrome[0x20]; 6062 6063 u8 reserved_at_40[0x40]; 6064 }; 6065 6066 struct mlx5_ifc_modify_other_hca_cap_in_bits { 6067 u8 opcode[0x10]; 6068 u8 reserved_at_10[0x10]; 6069 6070 u8 reserved_at_20[0x10]; 6071 u8 op_mod[0x10]; 6072 6073 u8 reserved_at_40[0x10]; 6074 u8 function_id[0x10]; 6075 u8 field_select[0x20]; 6076 6077 struct mlx5_ifc_other_hca_cap_bits other_capability; 6078 }; 6079 6080 struct mlx5_ifc_flow_table_context_bits { 6081 u8 reformat_en[0x1]; 6082 u8 decap_en[0x1]; 6083 u8 sw_owner[0x1]; 6084 u8 termination_table[0x1]; 6085 u8 table_miss_action[0x4]; 6086 u8 level[0x8]; 6087 u8 reserved_at_10[0x8]; 6088 u8 log_size[0x8]; 6089 6090 u8 reserved_at_20[0x8]; 6091 u8 table_miss_id[0x18]; 6092 6093 u8 reserved_at_40[0x8]; 6094 u8 lag_master_next_table_id[0x18]; 6095 6096 u8 reserved_at_60[0x60]; 6097 6098 u8 sw_owner_icm_root_1[0x40]; 6099 6100 u8 sw_owner_icm_root_0[0x40]; 6101 6102 }; 6103 6104 struct mlx5_ifc_query_flow_table_out_bits { 6105 u8 status[0x8]; 6106 u8 reserved_at_8[0x18]; 6107 6108 u8 syndrome[0x20]; 6109 6110 u8 reserved_at_40[0x80]; 6111 6112 struct mlx5_ifc_flow_table_context_bits flow_table_context; 6113 }; 6114 6115 struct mlx5_ifc_query_flow_table_in_bits { 6116 u8 opcode[0x10]; 6117 u8 reserved_at_10[0x10]; 6118 6119 u8 reserved_at_20[0x10]; 6120 u8 op_mod[0x10]; 6121 6122 u8 reserved_at_40[0x40]; 6123 6124 u8 table_type[0x8]; 6125 u8 reserved_at_88[0x18]; 6126 6127 u8 reserved_at_a0[0x8]; 6128 u8 table_id[0x18]; 6129 6130 u8 reserved_at_c0[0x140]; 6131 }; 6132 6133 struct mlx5_ifc_query_fte_out_bits { 6134 u8 status[0x8]; 6135 u8 reserved_at_8[0x18]; 6136 6137 u8 syndrome[0x20]; 6138 6139 u8 reserved_at_40[0x1c0]; 6140 6141 struct mlx5_ifc_flow_context_bits flow_context; 6142 }; 6143 6144 struct mlx5_ifc_query_fte_in_bits { 6145 u8 opcode[0x10]; 6146 u8 reserved_at_10[0x10]; 6147 6148 u8 reserved_at_20[0x10]; 6149 u8 op_mod[0x10]; 6150 6151 u8 reserved_at_40[0x40]; 6152 6153 u8 table_type[0x8]; 6154 u8 reserved_at_88[0x18]; 6155 6156 u8 reserved_at_a0[0x8]; 6157 u8 table_id[0x18]; 6158 6159 u8 reserved_at_c0[0x40]; 6160 6161 u8 flow_index[0x20]; 6162 6163 u8 reserved_at_120[0xe0]; 6164 }; 6165 6166 struct mlx5_ifc_match_definer_format_0_bits { 6167 u8 reserved_at_0[0x100]; 6168 6169 u8 metadata_reg_c_0[0x20]; 6170 6171 u8 metadata_reg_c_1[0x20]; 6172 6173 u8 outer_dmac_47_16[0x20]; 6174 6175 u8 outer_dmac_15_0[0x10]; 6176 u8 outer_ethertype[0x10]; 6177 6178 u8 reserved_at_180[0x1]; 6179 u8 sx_sniffer[0x1]; 6180 u8 functional_lb[0x1]; 6181 u8 outer_ip_frag[0x1]; 6182 u8 outer_qp_type[0x2]; 6183 u8 outer_encap_type[0x2]; 6184 u8 port_number[0x2]; 6185 u8 outer_l3_type[0x2]; 6186 u8 outer_l4_type[0x2]; 6187 u8 outer_first_vlan_type[0x2]; 6188 u8 outer_first_vlan_prio[0x3]; 6189 u8 outer_first_vlan_cfi[0x1]; 6190 u8 outer_first_vlan_vid[0xc]; 6191 6192 u8 outer_l4_type_ext[0x4]; 6193 u8 reserved_at_1a4[0x2]; 6194 u8 outer_ipsec_layer[0x2]; 6195 u8 outer_l2_type[0x2]; 6196 u8 force_lb[0x1]; 6197 u8 outer_l2_ok[0x1]; 6198 u8 outer_l3_ok[0x1]; 6199 u8 outer_l4_ok[0x1]; 6200 u8 outer_second_vlan_type[0x2]; 6201 u8 outer_second_vlan_prio[0x3]; 6202 u8 outer_second_vlan_cfi[0x1]; 6203 u8 outer_second_vlan_vid[0xc]; 6204 6205 u8 outer_smac_47_16[0x20]; 6206 6207 u8 outer_smac_15_0[0x10]; 6208 u8 inner_ipv4_checksum_ok[0x1]; 6209 u8 inner_l4_checksum_ok[0x1]; 6210 u8 outer_ipv4_checksum_ok[0x1]; 6211 u8 outer_l4_checksum_ok[0x1]; 6212 u8 inner_l3_ok[0x1]; 6213 u8 inner_l4_ok[0x1]; 6214 u8 outer_l3_ok_duplicate[0x1]; 6215 u8 outer_l4_ok_duplicate[0x1]; 6216 u8 outer_tcp_cwr[0x1]; 6217 u8 outer_tcp_ece[0x1]; 6218 u8 outer_tcp_urg[0x1]; 6219 u8 outer_tcp_ack[0x1]; 6220 u8 outer_tcp_psh[0x1]; 6221 u8 outer_tcp_rst[0x1]; 6222 u8 outer_tcp_syn[0x1]; 6223 u8 outer_tcp_fin[0x1]; 6224 }; 6225 6226 struct mlx5_ifc_match_definer_format_22_bits { 6227 u8 reserved_at_0[0x100]; 6228 6229 u8 outer_ip_src_addr[0x20]; 6230 6231 u8 outer_ip_dest_addr[0x20]; 6232 6233 u8 outer_l4_sport[0x10]; 6234 u8 outer_l4_dport[0x10]; 6235 6236 u8 reserved_at_160[0x1]; 6237 u8 sx_sniffer[0x1]; 6238 u8 functional_lb[0x1]; 6239 u8 outer_ip_frag[0x1]; 6240 u8 outer_qp_type[0x2]; 6241 u8 outer_encap_type[0x2]; 6242 u8 port_number[0x2]; 6243 u8 outer_l3_type[0x2]; 6244 u8 outer_l4_type[0x2]; 6245 u8 outer_first_vlan_type[0x2]; 6246 u8 outer_first_vlan_prio[0x3]; 6247 u8 outer_first_vlan_cfi[0x1]; 6248 u8 outer_first_vlan_vid[0xc]; 6249 6250 u8 metadata_reg_c_0[0x20]; 6251 6252 u8 outer_dmac_47_16[0x20]; 6253 6254 u8 outer_smac_47_16[0x20]; 6255 6256 u8 outer_smac_15_0[0x10]; 6257 u8 outer_dmac_15_0[0x10]; 6258 }; 6259 6260 struct mlx5_ifc_match_definer_format_23_bits { 6261 u8 reserved_at_0[0x100]; 6262 6263 u8 inner_ip_src_addr[0x20]; 6264 6265 u8 inner_ip_dest_addr[0x20]; 6266 6267 u8 inner_l4_sport[0x10]; 6268 u8 inner_l4_dport[0x10]; 6269 6270 u8 reserved_at_160[0x1]; 6271 u8 sx_sniffer[0x1]; 6272 u8 functional_lb[0x1]; 6273 u8 inner_ip_frag[0x1]; 6274 u8 inner_qp_type[0x2]; 6275 u8 inner_encap_type[0x2]; 6276 u8 port_number[0x2]; 6277 u8 inner_l3_type[0x2]; 6278 u8 inner_l4_type[0x2]; 6279 u8 inner_first_vlan_type[0x2]; 6280 u8 inner_first_vlan_prio[0x3]; 6281 u8 inner_first_vlan_cfi[0x1]; 6282 u8 inner_first_vlan_vid[0xc]; 6283 6284 u8 tunnel_header_0[0x20]; 6285 6286 u8 inner_dmac_47_16[0x20]; 6287 6288 u8 inner_smac_47_16[0x20]; 6289 6290 u8 inner_smac_15_0[0x10]; 6291 u8 inner_dmac_15_0[0x10]; 6292 }; 6293 6294 struct mlx5_ifc_match_definer_format_29_bits { 6295 u8 reserved_at_0[0xc0]; 6296 6297 u8 outer_ip_dest_addr[0x80]; 6298 6299 u8 outer_ip_src_addr[0x80]; 6300 6301 u8 outer_l4_sport[0x10]; 6302 u8 outer_l4_dport[0x10]; 6303 6304 u8 reserved_at_1e0[0x20]; 6305 }; 6306 6307 struct mlx5_ifc_match_definer_format_30_bits { 6308 u8 reserved_at_0[0xa0]; 6309 6310 u8 outer_ip_dest_addr[0x80]; 6311 6312 u8 outer_ip_src_addr[0x80]; 6313 6314 u8 outer_dmac_47_16[0x20]; 6315 6316 u8 outer_smac_47_16[0x20]; 6317 6318 u8 outer_smac_15_0[0x10]; 6319 u8 outer_dmac_15_0[0x10]; 6320 }; 6321 6322 struct mlx5_ifc_match_definer_format_31_bits { 6323 u8 reserved_at_0[0xc0]; 6324 6325 u8 inner_ip_dest_addr[0x80]; 6326 6327 u8 inner_ip_src_addr[0x80]; 6328 6329 u8 inner_l4_sport[0x10]; 6330 u8 inner_l4_dport[0x10]; 6331 6332 u8 reserved_at_1e0[0x20]; 6333 }; 6334 6335 struct mlx5_ifc_match_definer_format_32_bits { 6336 u8 reserved_at_0[0xa0]; 6337 6338 u8 inner_ip_dest_addr[0x80]; 6339 6340 u8 inner_ip_src_addr[0x80]; 6341 6342 u8 inner_dmac_47_16[0x20]; 6343 6344 u8 inner_smac_47_16[0x20]; 6345 6346 u8 inner_smac_15_0[0x10]; 6347 u8 inner_dmac_15_0[0x10]; 6348 }; 6349 6350 enum { 6351 MLX5_IFC_DEFINER_FORMAT_ID_SELECT = 61, 6352 }; 6353 6354 #define MLX5_IFC_DEFINER_FORMAT_OFFSET_UNUSED 0x0 6355 #define MLX5_IFC_DEFINER_FORMAT_OFFSET_OUTER_ETH_PKT_LEN 0x48 6356 #define MLX5_IFC_DEFINER_DW_SELECTORS_NUM 9 6357 #define MLX5_IFC_DEFINER_BYTE_SELECTORS_NUM 8 6358 6359 struct mlx5_ifc_match_definer_match_mask_bits { 6360 u8 reserved_at_1c0[5][0x20]; 6361 u8 match_dw_8[0x20]; 6362 u8 match_dw_7[0x20]; 6363 u8 match_dw_6[0x20]; 6364 u8 match_dw_5[0x20]; 6365 u8 match_dw_4[0x20]; 6366 u8 match_dw_3[0x20]; 6367 u8 match_dw_2[0x20]; 6368 u8 match_dw_1[0x20]; 6369 u8 match_dw_0[0x20]; 6370 6371 u8 match_byte_7[0x8]; 6372 u8 match_byte_6[0x8]; 6373 u8 match_byte_5[0x8]; 6374 u8 match_byte_4[0x8]; 6375 6376 u8 match_byte_3[0x8]; 6377 u8 match_byte_2[0x8]; 6378 u8 match_byte_1[0x8]; 6379 u8 match_byte_0[0x8]; 6380 }; 6381 6382 struct mlx5_ifc_match_definer_bits { 6383 u8 modify_field_select[0x40]; 6384 6385 u8 reserved_at_40[0x40]; 6386 6387 u8 reserved_at_80[0x10]; 6388 u8 format_id[0x10]; 6389 6390 u8 reserved_at_a0[0x60]; 6391 6392 u8 format_select_dw3[0x8]; 6393 u8 format_select_dw2[0x8]; 6394 u8 format_select_dw1[0x8]; 6395 u8 format_select_dw0[0x8]; 6396 6397 u8 format_select_dw7[0x8]; 6398 u8 format_select_dw6[0x8]; 6399 u8 format_select_dw5[0x8]; 6400 u8 format_select_dw4[0x8]; 6401 6402 u8 reserved_at_100[0x18]; 6403 u8 format_select_dw8[0x8]; 6404 6405 u8 reserved_at_120[0x20]; 6406 6407 u8 format_select_byte3[0x8]; 6408 u8 format_select_byte2[0x8]; 6409 u8 format_select_byte1[0x8]; 6410 u8 format_select_byte0[0x8]; 6411 6412 u8 format_select_byte7[0x8]; 6413 u8 format_select_byte6[0x8]; 6414 u8 format_select_byte5[0x8]; 6415 u8 format_select_byte4[0x8]; 6416 6417 u8 reserved_at_180[0x40]; 6418 6419 union { 6420 struct { 6421 u8 match_mask[16][0x20]; 6422 }; 6423 struct mlx5_ifc_match_definer_match_mask_bits match_mask_format; 6424 }; 6425 }; 6426 6427 struct mlx5_ifc_general_obj_create_param_bits { 6428 u8 alias_object[0x1]; 6429 u8 reserved_at_1[0x2]; 6430 u8 log_obj_range[0x5]; 6431 u8 reserved_at_8[0x18]; 6432 }; 6433 6434 struct mlx5_ifc_general_obj_query_param_bits { 6435 u8 alias_object[0x1]; 6436 u8 obj_offset[0x1f]; 6437 }; 6438 6439 struct mlx5_ifc_general_obj_in_cmd_hdr_bits { 6440 u8 opcode[0x10]; 6441 u8 uid[0x10]; 6442 6443 u8 vhca_tunnel_id[0x10]; 6444 u8 obj_type[0x10]; 6445 6446 u8 obj_id[0x20]; 6447 6448 union { 6449 struct mlx5_ifc_general_obj_create_param_bits create; 6450 struct mlx5_ifc_general_obj_query_param_bits query; 6451 } op_param; 6452 }; 6453 6454 struct mlx5_ifc_general_obj_out_cmd_hdr_bits { 6455 u8 status[0x8]; 6456 u8 reserved_at_8[0x18]; 6457 6458 u8 syndrome[0x20]; 6459 6460 u8 obj_id[0x20]; 6461 6462 u8 reserved_at_60[0x20]; 6463 }; 6464 6465 struct mlx5_ifc_allow_other_vhca_access_in_bits { 6466 u8 opcode[0x10]; 6467 u8 uid[0x10]; 6468 u8 reserved_at_20[0x10]; 6469 u8 op_mod[0x10]; 6470 u8 reserved_at_40[0x50]; 6471 u8 object_type_to_be_accessed[0x10]; 6472 u8 object_id_to_be_accessed[0x20]; 6473 u8 reserved_at_c0[0x40]; 6474 union { 6475 u8 access_key_raw[0x100]; 6476 u8 access_key[8][0x20]; 6477 }; 6478 }; 6479 6480 struct mlx5_ifc_allow_other_vhca_access_out_bits { 6481 u8 status[0x8]; 6482 u8 reserved_at_8[0x18]; 6483 u8 syndrome[0x20]; 6484 u8 reserved_at_40[0x40]; 6485 }; 6486 6487 struct mlx5_ifc_modify_header_arg_bits { 6488 u8 reserved_at_0[0x80]; 6489 6490 u8 reserved_at_80[0x8]; 6491 u8 access_pd[0x18]; 6492 }; 6493 6494 struct mlx5_ifc_create_modify_header_arg_in_bits { 6495 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 6496 struct mlx5_ifc_modify_header_arg_bits arg; 6497 }; 6498 6499 struct mlx5_ifc_create_match_definer_in_bits { 6500 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 6501 6502 struct mlx5_ifc_match_definer_bits obj_context; 6503 }; 6504 6505 struct mlx5_ifc_create_match_definer_out_bits { 6506 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 6507 }; 6508 6509 struct mlx5_ifc_alias_context_bits { 6510 u8 vhca_id_to_be_accessed[0x10]; 6511 u8 reserved_at_10[0xd]; 6512 u8 status[0x3]; 6513 u8 object_id_to_be_accessed[0x20]; 6514 u8 reserved_at_40[0x40]; 6515 union { 6516 u8 access_key_raw[0x100]; 6517 u8 access_key[8][0x20]; 6518 }; 6519 u8 metadata[0x80]; 6520 }; 6521 6522 struct mlx5_ifc_create_alias_obj_in_bits { 6523 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 6524 struct mlx5_ifc_alias_context_bits alias_ctx; 6525 }; 6526 6527 enum { 6528 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 6529 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 6530 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 6531 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3, 6532 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_3 = 0x4, 6533 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_4 = 0x5, 6534 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_5 = 0x6, 6535 }; 6536 6537 struct mlx5_ifc_query_flow_group_out_bits { 6538 u8 status[0x8]; 6539 u8 reserved_at_8[0x18]; 6540 6541 u8 syndrome[0x20]; 6542 6543 u8 reserved_at_40[0xa0]; 6544 6545 u8 start_flow_index[0x20]; 6546 6547 u8 reserved_at_100[0x20]; 6548 6549 u8 end_flow_index[0x20]; 6550 6551 u8 reserved_at_140[0xa0]; 6552 6553 u8 reserved_at_1e0[0x18]; 6554 u8 match_criteria_enable[0x8]; 6555 6556 struct mlx5_ifc_fte_match_param_bits match_criteria; 6557 6558 u8 reserved_at_1200[0xe00]; 6559 }; 6560 6561 struct mlx5_ifc_query_flow_group_in_bits { 6562 u8 opcode[0x10]; 6563 u8 reserved_at_10[0x10]; 6564 6565 u8 reserved_at_20[0x10]; 6566 u8 op_mod[0x10]; 6567 6568 u8 reserved_at_40[0x40]; 6569 6570 u8 table_type[0x8]; 6571 u8 reserved_at_88[0x18]; 6572 6573 u8 reserved_at_a0[0x8]; 6574 u8 table_id[0x18]; 6575 6576 u8 group_id[0x20]; 6577 6578 u8 reserved_at_e0[0x120]; 6579 }; 6580 6581 struct mlx5_ifc_query_flow_counter_out_bits { 6582 u8 status[0x8]; 6583 u8 reserved_at_8[0x18]; 6584 6585 u8 syndrome[0x20]; 6586 6587 u8 reserved_at_40[0x40]; 6588 6589 struct mlx5_ifc_traffic_counter_bits flow_statistics[]; 6590 }; 6591 6592 struct mlx5_ifc_query_flow_counter_in_bits { 6593 u8 opcode[0x10]; 6594 u8 reserved_at_10[0x10]; 6595 6596 u8 reserved_at_20[0x10]; 6597 u8 op_mod[0x10]; 6598 6599 u8 reserved_at_40[0x80]; 6600 6601 u8 clear[0x1]; 6602 u8 reserved_at_c1[0xf]; 6603 u8 num_of_counters[0x10]; 6604 6605 u8 flow_counter_id[0x20]; 6606 }; 6607 6608 struct mlx5_ifc_query_esw_vport_context_out_bits { 6609 u8 status[0x8]; 6610 u8 reserved_at_8[0x18]; 6611 6612 u8 syndrome[0x20]; 6613 6614 u8 reserved_at_40[0x40]; 6615 6616 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 6617 }; 6618 6619 struct mlx5_ifc_query_esw_vport_context_in_bits { 6620 u8 opcode[0x10]; 6621 u8 reserved_at_10[0x10]; 6622 6623 u8 reserved_at_20[0x10]; 6624 u8 op_mod[0x10]; 6625 6626 u8 other_vport[0x1]; 6627 u8 reserved_at_41[0xf]; 6628 u8 vport_number[0x10]; 6629 6630 u8 reserved_at_60[0x20]; 6631 }; 6632 6633 struct mlx5_ifc_modify_esw_vport_context_out_bits { 6634 u8 status[0x8]; 6635 u8 reserved_at_8[0x18]; 6636 6637 u8 syndrome[0x20]; 6638 6639 u8 reserved_at_40[0x40]; 6640 }; 6641 6642 struct mlx5_ifc_esw_vport_context_fields_select_bits { 6643 u8 reserved_at_0[0x1b]; 6644 u8 fdb_to_vport_reg_c_id[0x1]; 6645 u8 vport_cvlan_insert[0x1]; 6646 u8 vport_svlan_insert[0x1]; 6647 u8 vport_cvlan_strip[0x1]; 6648 u8 vport_svlan_strip[0x1]; 6649 }; 6650 6651 struct mlx5_ifc_modify_esw_vport_context_in_bits { 6652 u8 opcode[0x10]; 6653 u8 reserved_at_10[0x10]; 6654 6655 u8 reserved_at_20[0x10]; 6656 u8 op_mod[0x10]; 6657 6658 u8 other_vport[0x1]; 6659 u8 reserved_at_41[0xf]; 6660 u8 vport_number[0x10]; 6661 6662 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select; 6663 6664 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 6665 }; 6666 6667 struct mlx5_ifc_query_eq_out_bits { 6668 u8 status[0x8]; 6669 u8 reserved_at_8[0x18]; 6670 6671 u8 syndrome[0x20]; 6672 6673 u8 reserved_at_40[0x40]; 6674 6675 struct mlx5_ifc_eqc_bits eq_context_entry; 6676 6677 u8 reserved_at_280[0x40]; 6678 6679 u8 event_bitmask[0x40]; 6680 6681 u8 reserved_at_300[0x580]; 6682 6683 u8 pas[][0x40]; 6684 }; 6685 6686 struct mlx5_ifc_query_eq_in_bits { 6687 u8 opcode[0x10]; 6688 u8 reserved_at_10[0x10]; 6689 6690 u8 reserved_at_20[0x10]; 6691 u8 op_mod[0x10]; 6692 6693 u8 reserved_at_40[0x18]; 6694 u8 eq_number[0x8]; 6695 6696 u8 reserved_at_60[0x20]; 6697 }; 6698 6699 struct mlx5_ifc_packet_reformat_context_in_bits { 6700 u8 reformat_type[0x8]; 6701 u8 reserved_at_8[0x4]; 6702 u8 reformat_param_0[0x4]; 6703 u8 reserved_at_10[0x6]; 6704 u8 reformat_data_size[0xa]; 6705 6706 u8 reformat_param_1[0x8]; 6707 u8 reserved_at_28[0x8]; 6708 u8 reformat_data[2][0x8]; 6709 6710 u8 more_reformat_data[][0x8]; 6711 }; 6712 6713 struct mlx5_ifc_query_packet_reformat_context_out_bits { 6714 u8 status[0x8]; 6715 u8 reserved_at_8[0x18]; 6716 6717 u8 syndrome[0x20]; 6718 6719 u8 reserved_at_40[0xa0]; 6720 6721 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context[]; 6722 }; 6723 6724 struct mlx5_ifc_query_packet_reformat_context_in_bits { 6725 u8 opcode[0x10]; 6726 u8 reserved_at_10[0x10]; 6727 6728 u8 reserved_at_20[0x10]; 6729 u8 op_mod[0x10]; 6730 6731 u8 packet_reformat_id[0x20]; 6732 6733 u8 reserved_at_60[0xa0]; 6734 }; 6735 6736 struct mlx5_ifc_alloc_packet_reformat_context_out_bits { 6737 u8 status[0x8]; 6738 u8 reserved_at_8[0x18]; 6739 6740 u8 syndrome[0x20]; 6741 6742 u8 packet_reformat_id[0x20]; 6743 6744 u8 reserved_at_60[0x20]; 6745 }; 6746 6747 enum { 6748 MLX5_REFORMAT_CONTEXT_ANCHOR_MAC_START = 0x1, 6749 MLX5_REFORMAT_CONTEXT_ANCHOR_IP_START = 0x7, 6750 MLX5_REFORMAT_CONTEXT_ANCHOR_TCP_UDP_START = 0x9, 6751 }; 6752 6753 enum mlx5_reformat_ctx_type { 6754 MLX5_REFORMAT_TYPE_L2_TO_VXLAN = 0x0, 6755 MLX5_REFORMAT_TYPE_L2_TO_NVGRE = 0x1, 6756 MLX5_REFORMAT_TYPE_L2_TO_L2_TUNNEL = 0x2, 6757 MLX5_REFORMAT_TYPE_L3_TUNNEL_TO_L2 = 0x3, 6758 MLX5_REFORMAT_TYPE_L2_TO_L3_TUNNEL = 0x4, 6759 MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_IPV4 = 0x5, 6760 MLX5_REFORMAT_TYPE_L2_TO_L3_ESP_TUNNEL = 0x6, 6761 MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_UDPV4 = 0x7, 6762 MLX5_REFORMAT_TYPE_DEL_ESP_TRANSPORT = 0x8, 6763 MLX5_REFORMAT_TYPE_L3_ESP_TUNNEL_TO_L2 = 0x9, 6764 MLX5_REFORMAT_TYPE_DEL_ESP_TRANSPORT_OVER_UDP = 0xa, 6765 MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_IPV6 = 0xb, 6766 MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_UDPV6 = 0xc, 6767 MLX5_REFORMAT_TYPE_INSERT_HDR = 0xf, 6768 MLX5_REFORMAT_TYPE_REMOVE_HDR = 0x10, 6769 MLX5_REFORMAT_TYPE_ADD_MACSEC = 0x11, 6770 MLX5_REFORMAT_TYPE_DEL_MACSEC = 0x12, 6771 }; 6772 6773 struct mlx5_ifc_alloc_packet_reformat_context_in_bits { 6774 u8 opcode[0x10]; 6775 u8 reserved_at_10[0x10]; 6776 6777 u8 reserved_at_20[0x10]; 6778 u8 op_mod[0x10]; 6779 6780 u8 reserved_at_40[0xa0]; 6781 6782 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context; 6783 }; 6784 6785 struct mlx5_ifc_dealloc_packet_reformat_context_out_bits { 6786 u8 status[0x8]; 6787 u8 reserved_at_8[0x18]; 6788 6789 u8 syndrome[0x20]; 6790 6791 u8 reserved_at_40[0x40]; 6792 }; 6793 6794 struct mlx5_ifc_dealloc_packet_reformat_context_in_bits { 6795 u8 opcode[0x10]; 6796 u8 reserved_at_10[0x10]; 6797 6798 u8 reserved_20[0x10]; 6799 u8 op_mod[0x10]; 6800 6801 u8 packet_reformat_id[0x20]; 6802 6803 u8 reserved_60[0x20]; 6804 }; 6805 6806 struct mlx5_ifc_set_action_in_bits { 6807 u8 action_type[0x4]; 6808 u8 field[0xc]; 6809 u8 reserved_at_10[0x3]; 6810 u8 offset[0x5]; 6811 u8 reserved_at_18[0x3]; 6812 u8 length[0x5]; 6813 6814 u8 data[0x20]; 6815 }; 6816 6817 struct mlx5_ifc_add_action_in_bits { 6818 u8 action_type[0x4]; 6819 u8 field[0xc]; 6820 u8 reserved_at_10[0x10]; 6821 6822 u8 data[0x20]; 6823 }; 6824 6825 struct mlx5_ifc_copy_action_in_bits { 6826 u8 action_type[0x4]; 6827 u8 src_field[0xc]; 6828 u8 reserved_at_10[0x3]; 6829 u8 src_offset[0x5]; 6830 u8 reserved_at_18[0x3]; 6831 u8 length[0x5]; 6832 6833 u8 reserved_at_20[0x4]; 6834 u8 dst_field[0xc]; 6835 u8 reserved_at_30[0x3]; 6836 u8 dst_offset[0x5]; 6837 u8 reserved_at_38[0x8]; 6838 }; 6839 6840 union mlx5_ifc_set_add_copy_action_in_auto_bits { 6841 struct mlx5_ifc_set_action_in_bits set_action_in; 6842 struct mlx5_ifc_add_action_in_bits add_action_in; 6843 struct mlx5_ifc_copy_action_in_bits copy_action_in; 6844 u8 reserved_at_0[0x40]; 6845 }; 6846 6847 enum { 6848 MLX5_ACTION_TYPE_SET = 0x1, 6849 MLX5_ACTION_TYPE_ADD = 0x2, 6850 MLX5_ACTION_TYPE_COPY = 0x3, 6851 }; 6852 6853 enum { 6854 MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16 = 0x1, 6855 MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0 = 0x2, 6856 MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE = 0x3, 6857 MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16 = 0x4, 6858 MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0 = 0x5, 6859 MLX5_ACTION_IN_FIELD_OUT_IP_DSCP = 0x6, 6860 MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS = 0x7, 6861 MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT = 0x8, 6862 MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT = 0x9, 6863 MLX5_ACTION_IN_FIELD_OUT_IP_TTL = 0xa, 6864 MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT = 0xb, 6865 MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT = 0xc, 6866 MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96 = 0xd, 6867 MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64 = 0xe, 6868 MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32 = 0xf, 6869 MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0 = 0x10, 6870 MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96 = 0x11, 6871 MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64 = 0x12, 6872 MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32 = 0x13, 6873 MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0 = 0x14, 6874 MLX5_ACTION_IN_FIELD_OUT_SIPV4 = 0x15, 6875 MLX5_ACTION_IN_FIELD_OUT_DIPV4 = 0x16, 6876 MLX5_ACTION_IN_FIELD_OUT_FIRST_VID = 0x17, 6877 MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47, 6878 MLX5_ACTION_IN_FIELD_METADATA_REG_A = 0x49, 6879 MLX5_ACTION_IN_FIELD_METADATA_REG_B = 0x50, 6880 MLX5_ACTION_IN_FIELD_METADATA_REG_C_0 = 0x51, 6881 MLX5_ACTION_IN_FIELD_METADATA_REG_C_1 = 0x52, 6882 MLX5_ACTION_IN_FIELD_METADATA_REG_C_2 = 0x53, 6883 MLX5_ACTION_IN_FIELD_METADATA_REG_C_3 = 0x54, 6884 MLX5_ACTION_IN_FIELD_METADATA_REG_C_4 = 0x55, 6885 MLX5_ACTION_IN_FIELD_METADATA_REG_C_5 = 0x56, 6886 MLX5_ACTION_IN_FIELD_METADATA_REG_C_6 = 0x57, 6887 MLX5_ACTION_IN_FIELD_METADATA_REG_C_7 = 0x58, 6888 MLX5_ACTION_IN_FIELD_OUT_TCP_SEQ_NUM = 0x59, 6889 MLX5_ACTION_IN_FIELD_OUT_TCP_ACK_NUM = 0x5B, 6890 MLX5_ACTION_IN_FIELD_IPSEC_SYNDROME = 0x5D, 6891 MLX5_ACTION_IN_FIELD_OUT_EMD_47_32 = 0x6F, 6892 MLX5_ACTION_IN_FIELD_OUT_EMD_31_0 = 0x70, 6893 }; 6894 6895 struct mlx5_ifc_alloc_modify_header_context_out_bits { 6896 u8 status[0x8]; 6897 u8 reserved_at_8[0x18]; 6898 6899 u8 syndrome[0x20]; 6900 6901 u8 modify_header_id[0x20]; 6902 6903 u8 reserved_at_60[0x20]; 6904 }; 6905 6906 struct mlx5_ifc_alloc_modify_header_context_in_bits { 6907 u8 opcode[0x10]; 6908 u8 reserved_at_10[0x10]; 6909 6910 u8 reserved_at_20[0x10]; 6911 u8 op_mod[0x10]; 6912 6913 u8 reserved_at_40[0x20]; 6914 6915 u8 table_type[0x8]; 6916 u8 reserved_at_68[0x10]; 6917 u8 num_of_actions[0x8]; 6918 6919 union mlx5_ifc_set_add_copy_action_in_auto_bits actions[]; 6920 }; 6921 6922 struct mlx5_ifc_dealloc_modify_header_context_out_bits { 6923 u8 status[0x8]; 6924 u8 reserved_at_8[0x18]; 6925 6926 u8 syndrome[0x20]; 6927 6928 u8 reserved_at_40[0x40]; 6929 }; 6930 6931 struct mlx5_ifc_dealloc_modify_header_context_in_bits { 6932 u8 opcode[0x10]; 6933 u8 reserved_at_10[0x10]; 6934 6935 u8 reserved_at_20[0x10]; 6936 u8 op_mod[0x10]; 6937 6938 u8 modify_header_id[0x20]; 6939 6940 u8 reserved_at_60[0x20]; 6941 }; 6942 6943 struct mlx5_ifc_query_modify_header_context_in_bits { 6944 u8 opcode[0x10]; 6945 u8 uid[0x10]; 6946 6947 u8 reserved_at_20[0x10]; 6948 u8 op_mod[0x10]; 6949 6950 u8 modify_header_id[0x20]; 6951 6952 u8 reserved_at_60[0xa0]; 6953 }; 6954 6955 struct mlx5_ifc_query_dct_out_bits { 6956 u8 status[0x8]; 6957 u8 reserved_at_8[0x18]; 6958 6959 u8 syndrome[0x20]; 6960 6961 u8 reserved_at_40[0x40]; 6962 6963 struct mlx5_ifc_dctc_bits dct_context_entry; 6964 6965 u8 reserved_at_280[0x180]; 6966 }; 6967 6968 struct mlx5_ifc_query_dct_in_bits { 6969 u8 opcode[0x10]; 6970 u8 reserved_at_10[0x10]; 6971 6972 u8 reserved_at_20[0x10]; 6973 u8 op_mod[0x10]; 6974 6975 u8 reserved_at_40[0x8]; 6976 u8 dctn[0x18]; 6977 6978 u8 reserved_at_60[0x20]; 6979 }; 6980 6981 struct mlx5_ifc_query_cq_out_bits { 6982 u8 status[0x8]; 6983 u8 reserved_at_8[0x18]; 6984 6985 u8 syndrome[0x20]; 6986 6987 u8 reserved_at_40[0x40]; 6988 6989 struct mlx5_ifc_cqc_bits cq_context; 6990 6991 u8 reserved_at_280[0x600]; 6992 6993 u8 pas[][0x40]; 6994 }; 6995 6996 struct mlx5_ifc_query_cq_in_bits { 6997 u8 opcode[0x10]; 6998 u8 reserved_at_10[0x10]; 6999 7000 u8 reserved_at_20[0x10]; 7001 u8 op_mod[0x10]; 7002 7003 u8 reserved_at_40[0x8]; 7004 u8 cqn[0x18]; 7005 7006 u8 reserved_at_60[0x20]; 7007 }; 7008 7009 struct mlx5_ifc_query_cong_status_out_bits { 7010 u8 status[0x8]; 7011 u8 reserved_at_8[0x18]; 7012 7013 u8 syndrome[0x20]; 7014 7015 u8 reserved_at_40[0x20]; 7016 7017 u8 enable[0x1]; 7018 u8 tag_enable[0x1]; 7019 u8 reserved_at_62[0x1e]; 7020 }; 7021 7022 struct mlx5_ifc_query_cong_status_in_bits { 7023 u8 opcode[0x10]; 7024 u8 reserved_at_10[0x10]; 7025 7026 u8 reserved_at_20[0x10]; 7027 u8 op_mod[0x10]; 7028 7029 u8 reserved_at_40[0x18]; 7030 u8 priority[0x4]; 7031 u8 cong_protocol[0x4]; 7032 7033 u8 reserved_at_60[0x20]; 7034 }; 7035 7036 struct mlx5_ifc_query_cong_statistics_out_bits { 7037 u8 status[0x8]; 7038 u8 reserved_at_8[0x18]; 7039 7040 u8 syndrome[0x20]; 7041 7042 u8 reserved_at_40[0x40]; 7043 7044 u8 rp_cur_flows[0x20]; 7045 7046 u8 sum_flows[0x20]; 7047 7048 u8 rp_cnp_ignored_high[0x20]; 7049 7050 u8 rp_cnp_ignored_low[0x20]; 7051 7052 u8 rp_cnp_handled_high[0x20]; 7053 7054 u8 rp_cnp_handled_low[0x20]; 7055 7056 u8 reserved_at_140[0x100]; 7057 7058 u8 time_stamp_high[0x20]; 7059 7060 u8 time_stamp_low[0x20]; 7061 7062 u8 accumulators_period[0x20]; 7063 7064 u8 np_ecn_marked_roce_packets_high[0x20]; 7065 7066 u8 np_ecn_marked_roce_packets_low[0x20]; 7067 7068 u8 np_cnp_sent_high[0x20]; 7069 7070 u8 np_cnp_sent_low[0x20]; 7071 7072 u8 reserved_at_320[0x560]; 7073 }; 7074 7075 struct mlx5_ifc_query_cong_statistics_in_bits { 7076 u8 opcode[0x10]; 7077 u8 reserved_at_10[0x10]; 7078 7079 u8 reserved_at_20[0x10]; 7080 u8 op_mod[0x10]; 7081 7082 u8 clear[0x1]; 7083 u8 reserved_at_41[0x1f]; 7084 7085 u8 reserved_at_60[0x20]; 7086 }; 7087 7088 struct mlx5_ifc_query_cong_params_out_bits { 7089 u8 status[0x8]; 7090 u8 reserved_at_8[0x18]; 7091 7092 u8 syndrome[0x20]; 7093 7094 u8 reserved_at_40[0x40]; 7095 7096 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 7097 }; 7098 7099 struct mlx5_ifc_query_cong_params_in_bits { 7100 u8 opcode[0x10]; 7101 u8 reserved_at_10[0x10]; 7102 7103 u8 reserved_at_20[0x10]; 7104 u8 op_mod[0x10]; 7105 7106 u8 reserved_at_40[0x1c]; 7107 u8 cong_protocol[0x4]; 7108 7109 u8 reserved_at_60[0x20]; 7110 }; 7111 7112 struct mlx5_ifc_query_adapter_out_bits { 7113 u8 status[0x8]; 7114 u8 reserved_at_8[0x18]; 7115 7116 u8 syndrome[0x20]; 7117 7118 u8 reserved_at_40[0x40]; 7119 7120 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct; 7121 }; 7122 7123 struct mlx5_ifc_query_adapter_in_bits { 7124 u8 opcode[0x10]; 7125 u8 reserved_at_10[0x10]; 7126 7127 u8 reserved_at_20[0x10]; 7128 u8 op_mod[0x10]; 7129 7130 u8 reserved_at_40[0x40]; 7131 }; 7132 7133 struct mlx5_ifc_qp_2rst_out_bits { 7134 u8 status[0x8]; 7135 u8 reserved_at_8[0x18]; 7136 7137 u8 syndrome[0x20]; 7138 7139 u8 reserved_at_40[0x40]; 7140 }; 7141 7142 struct mlx5_ifc_qp_2rst_in_bits { 7143 u8 opcode[0x10]; 7144 u8 uid[0x10]; 7145 7146 u8 reserved_at_20[0x10]; 7147 u8 op_mod[0x10]; 7148 7149 u8 reserved_at_40[0x8]; 7150 u8 qpn[0x18]; 7151 7152 u8 reserved_at_60[0x20]; 7153 }; 7154 7155 struct mlx5_ifc_qp_2err_out_bits { 7156 u8 status[0x8]; 7157 u8 reserved_at_8[0x18]; 7158 7159 u8 syndrome[0x20]; 7160 7161 u8 reserved_at_40[0x40]; 7162 }; 7163 7164 struct mlx5_ifc_qp_2err_in_bits { 7165 u8 opcode[0x10]; 7166 u8 uid[0x10]; 7167 7168 u8 reserved_at_20[0x10]; 7169 u8 op_mod[0x10]; 7170 7171 u8 reserved_at_40[0x8]; 7172 u8 qpn[0x18]; 7173 7174 u8 reserved_at_60[0x20]; 7175 }; 7176 7177 struct mlx5_ifc_page_fault_resume_out_bits { 7178 u8 status[0x8]; 7179 u8 reserved_at_8[0x18]; 7180 7181 u8 syndrome[0x20]; 7182 7183 u8 reserved_at_40[0x40]; 7184 }; 7185 7186 struct mlx5_ifc_page_fault_resume_in_bits { 7187 u8 opcode[0x10]; 7188 u8 reserved_at_10[0x10]; 7189 7190 u8 reserved_at_20[0x10]; 7191 u8 op_mod[0x10]; 7192 7193 u8 error[0x1]; 7194 u8 reserved_at_41[0x4]; 7195 u8 page_fault_type[0x3]; 7196 u8 wq_number[0x18]; 7197 7198 u8 reserved_at_60[0x8]; 7199 u8 token[0x18]; 7200 }; 7201 7202 struct mlx5_ifc_nop_out_bits { 7203 u8 status[0x8]; 7204 u8 reserved_at_8[0x18]; 7205 7206 u8 syndrome[0x20]; 7207 7208 u8 reserved_at_40[0x40]; 7209 }; 7210 7211 struct mlx5_ifc_nop_in_bits { 7212 u8 opcode[0x10]; 7213 u8 reserved_at_10[0x10]; 7214 7215 u8 reserved_at_20[0x10]; 7216 u8 op_mod[0x10]; 7217 7218 u8 reserved_at_40[0x40]; 7219 }; 7220 7221 struct mlx5_ifc_modify_vport_state_out_bits { 7222 u8 status[0x8]; 7223 u8 reserved_at_8[0x18]; 7224 7225 u8 syndrome[0x20]; 7226 7227 u8 reserved_at_40[0x40]; 7228 }; 7229 7230 struct mlx5_ifc_modify_vport_state_in_bits { 7231 u8 opcode[0x10]; 7232 u8 reserved_at_10[0x10]; 7233 7234 u8 reserved_at_20[0x10]; 7235 u8 op_mod[0x10]; 7236 7237 u8 other_vport[0x1]; 7238 u8 reserved_at_41[0xf]; 7239 u8 vport_number[0x10]; 7240 7241 u8 reserved_at_60[0x18]; 7242 u8 admin_state[0x4]; 7243 u8 reserved_at_7c[0x4]; 7244 }; 7245 7246 struct mlx5_ifc_modify_tis_out_bits { 7247 u8 status[0x8]; 7248 u8 reserved_at_8[0x18]; 7249 7250 u8 syndrome[0x20]; 7251 7252 u8 reserved_at_40[0x40]; 7253 }; 7254 7255 struct mlx5_ifc_modify_tis_bitmask_bits { 7256 u8 reserved_at_0[0x20]; 7257 7258 u8 reserved_at_20[0x1d]; 7259 u8 lag_tx_port_affinity[0x1]; 7260 u8 strict_lag_tx_port_affinity[0x1]; 7261 u8 prio[0x1]; 7262 }; 7263 7264 struct mlx5_ifc_modify_tis_in_bits { 7265 u8 opcode[0x10]; 7266 u8 uid[0x10]; 7267 7268 u8 reserved_at_20[0x10]; 7269 u8 op_mod[0x10]; 7270 7271 u8 reserved_at_40[0x8]; 7272 u8 tisn[0x18]; 7273 7274 u8 reserved_at_60[0x20]; 7275 7276 struct mlx5_ifc_modify_tis_bitmask_bits bitmask; 7277 7278 u8 reserved_at_c0[0x40]; 7279 7280 struct mlx5_ifc_tisc_bits ctx; 7281 }; 7282 7283 struct mlx5_ifc_modify_tir_bitmask_bits { 7284 u8 reserved_at_0[0x20]; 7285 7286 u8 reserved_at_20[0x1b]; 7287 u8 self_lb_en[0x1]; 7288 u8 reserved_at_3c[0x1]; 7289 u8 hash[0x1]; 7290 u8 reserved_at_3e[0x1]; 7291 u8 packet_merge[0x1]; 7292 }; 7293 7294 struct mlx5_ifc_modify_tir_out_bits { 7295 u8 status[0x8]; 7296 u8 reserved_at_8[0x18]; 7297 7298 u8 syndrome[0x20]; 7299 7300 u8 reserved_at_40[0x40]; 7301 }; 7302 7303 struct mlx5_ifc_modify_tir_in_bits { 7304 u8 opcode[0x10]; 7305 u8 uid[0x10]; 7306 7307 u8 reserved_at_20[0x10]; 7308 u8 op_mod[0x10]; 7309 7310 u8 reserved_at_40[0x8]; 7311 u8 tirn[0x18]; 7312 7313 u8 reserved_at_60[0x20]; 7314 7315 struct mlx5_ifc_modify_tir_bitmask_bits bitmask; 7316 7317 u8 reserved_at_c0[0x40]; 7318 7319 struct mlx5_ifc_tirc_bits ctx; 7320 }; 7321 7322 struct mlx5_ifc_modify_sq_out_bits { 7323 u8 status[0x8]; 7324 u8 reserved_at_8[0x18]; 7325 7326 u8 syndrome[0x20]; 7327 7328 u8 reserved_at_40[0x40]; 7329 }; 7330 7331 struct mlx5_ifc_modify_sq_in_bits { 7332 u8 opcode[0x10]; 7333 u8 uid[0x10]; 7334 7335 u8 reserved_at_20[0x10]; 7336 u8 op_mod[0x10]; 7337 7338 u8 sq_state[0x4]; 7339 u8 reserved_at_44[0x4]; 7340 u8 sqn[0x18]; 7341 7342 u8 reserved_at_60[0x20]; 7343 7344 u8 modify_bitmask[0x40]; 7345 7346 u8 reserved_at_c0[0x40]; 7347 7348 struct mlx5_ifc_sqc_bits ctx; 7349 }; 7350 7351 struct mlx5_ifc_modify_scheduling_element_out_bits { 7352 u8 status[0x8]; 7353 u8 reserved_at_8[0x18]; 7354 7355 u8 syndrome[0x20]; 7356 7357 u8 reserved_at_40[0x1c0]; 7358 }; 7359 7360 enum { 7361 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1, 7362 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2, 7363 }; 7364 7365 struct mlx5_ifc_modify_scheduling_element_in_bits { 7366 u8 opcode[0x10]; 7367 u8 reserved_at_10[0x10]; 7368 7369 u8 reserved_at_20[0x10]; 7370 u8 op_mod[0x10]; 7371 7372 u8 scheduling_hierarchy[0x8]; 7373 u8 reserved_at_48[0x18]; 7374 7375 u8 scheduling_element_id[0x20]; 7376 7377 u8 reserved_at_80[0x20]; 7378 7379 u8 modify_bitmask[0x20]; 7380 7381 u8 reserved_at_c0[0x40]; 7382 7383 struct mlx5_ifc_scheduling_context_bits scheduling_context; 7384 7385 u8 reserved_at_300[0x100]; 7386 }; 7387 7388 struct mlx5_ifc_modify_rqt_out_bits { 7389 u8 status[0x8]; 7390 u8 reserved_at_8[0x18]; 7391 7392 u8 syndrome[0x20]; 7393 7394 u8 reserved_at_40[0x40]; 7395 }; 7396 7397 struct mlx5_ifc_rqt_bitmask_bits { 7398 u8 reserved_at_0[0x20]; 7399 7400 u8 reserved_at_20[0x1f]; 7401 u8 rqn_list[0x1]; 7402 }; 7403 7404 struct mlx5_ifc_modify_rqt_in_bits { 7405 u8 opcode[0x10]; 7406 u8 uid[0x10]; 7407 7408 u8 reserved_at_20[0x10]; 7409 u8 op_mod[0x10]; 7410 7411 u8 reserved_at_40[0x8]; 7412 u8 rqtn[0x18]; 7413 7414 u8 reserved_at_60[0x20]; 7415 7416 struct mlx5_ifc_rqt_bitmask_bits bitmask; 7417 7418 u8 reserved_at_c0[0x40]; 7419 7420 struct mlx5_ifc_rqtc_bits ctx; 7421 }; 7422 7423 struct mlx5_ifc_modify_rq_out_bits { 7424 u8 status[0x8]; 7425 u8 reserved_at_8[0x18]; 7426 7427 u8 syndrome[0x20]; 7428 7429 u8 reserved_at_40[0x40]; 7430 }; 7431 7432 enum { 7433 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1, 7434 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2, 7435 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3, 7436 }; 7437 7438 struct mlx5_ifc_modify_rq_in_bits { 7439 u8 opcode[0x10]; 7440 u8 uid[0x10]; 7441 7442 u8 reserved_at_20[0x10]; 7443 u8 op_mod[0x10]; 7444 7445 u8 rq_state[0x4]; 7446 u8 reserved_at_44[0x4]; 7447 u8 rqn[0x18]; 7448 7449 u8 reserved_at_60[0x20]; 7450 7451 u8 modify_bitmask[0x40]; 7452 7453 u8 reserved_at_c0[0x40]; 7454 7455 struct mlx5_ifc_rqc_bits ctx; 7456 }; 7457 7458 struct mlx5_ifc_modify_rmp_out_bits { 7459 u8 status[0x8]; 7460 u8 reserved_at_8[0x18]; 7461 7462 u8 syndrome[0x20]; 7463 7464 u8 reserved_at_40[0x40]; 7465 }; 7466 7467 struct mlx5_ifc_rmp_bitmask_bits { 7468 u8 reserved_at_0[0x20]; 7469 7470 u8 reserved_at_20[0x1f]; 7471 u8 lwm[0x1]; 7472 }; 7473 7474 struct mlx5_ifc_modify_rmp_in_bits { 7475 u8 opcode[0x10]; 7476 u8 uid[0x10]; 7477 7478 u8 reserved_at_20[0x10]; 7479 u8 op_mod[0x10]; 7480 7481 u8 rmp_state[0x4]; 7482 u8 reserved_at_44[0x4]; 7483 u8 rmpn[0x18]; 7484 7485 u8 reserved_at_60[0x20]; 7486 7487 struct mlx5_ifc_rmp_bitmask_bits bitmask; 7488 7489 u8 reserved_at_c0[0x40]; 7490 7491 struct mlx5_ifc_rmpc_bits ctx; 7492 }; 7493 7494 struct mlx5_ifc_modify_nic_vport_context_out_bits { 7495 u8 status[0x8]; 7496 u8 reserved_at_8[0x18]; 7497 7498 u8 syndrome[0x20]; 7499 7500 u8 reserved_at_40[0x40]; 7501 }; 7502 7503 struct mlx5_ifc_modify_nic_vport_field_select_bits { 7504 u8 reserved_at_0[0x12]; 7505 u8 affiliation[0x1]; 7506 u8 reserved_at_13[0x1]; 7507 u8 disable_uc_local_lb[0x1]; 7508 u8 disable_mc_local_lb[0x1]; 7509 u8 node_guid[0x1]; 7510 u8 port_guid[0x1]; 7511 u8 min_inline[0x1]; 7512 u8 mtu[0x1]; 7513 u8 change_event[0x1]; 7514 u8 promisc[0x1]; 7515 u8 permanent_address[0x1]; 7516 u8 addresses_list[0x1]; 7517 u8 roce_en[0x1]; 7518 u8 reserved_at_1f[0x1]; 7519 }; 7520 7521 struct mlx5_ifc_modify_nic_vport_context_in_bits { 7522 u8 opcode[0x10]; 7523 u8 reserved_at_10[0x10]; 7524 7525 u8 reserved_at_20[0x10]; 7526 u8 op_mod[0x10]; 7527 7528 u8 other_vport[0x1]; 7529 u8 reserved_at_41[0xf]; 7530 u8 vport_number[0x10]; 7531 7532 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select; 7533 7534 u8 reserved_at_80[0x780]; 7535 7536 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 7537 }; 7538 7539 struct mlx5_ifc_modify_hca_vport_context_out_bits { 7540 u8 status[0x8]; 7541 u8 reserved_at_8[0x18]; 7542 7543 u8 syndrome[0x20]; 7544 7545 u8 reserved_at_40[0x40]; 7546 }; 7547 7548 struct mlx5_ifc_modify_hca_vport_context_in_bits { 7549 u8 opcode[0x10]; 7550 u8 reserved_at_10[0x10]; 7551 7552 u8 reserved_at_20[0x10]; 7553 u8 op_mod[0x10]; 7554 7555 u8 other_vport[0x1]; 7556 u8 reserved_at_41[0xb]; 7557 u8 port_num[0x4]; 7558 u8 vport_number[0x10]; 7559 7560 u8 reserved_at_60[0x20]; 7561 7562 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 7563 }; 7564 7565 struct mlx5_ifc_modify_cq_out_bits { 7566 u8 status[0x8]; 7567 u8 reserved_at_8[0x18]; 7568 7569 u8 syndrome[0x20]; 7570 7571 u8 reserved_at_40[0x40]; 7572 }; 7573 7574 enum { 7575 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0, 7576 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1, 7577 }; 7578 7579 struct mlx5_ifc_modify_cq_in_bits { 7580 u8 opcode[0x10]; 7581 u8 uid[0x10]; 7582 7583 u8 reserved_at_20[0x10]; 7584 u8 op_mod[0x10]; 7585 7586 u8 reserved_at_40[0x8]; 7587 u8 cqn[0x18]; 7588 7589 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select; 7590 7591 struct mlx5_ifc_cqc_bits cq_context; 7592 7593 u8 reserved_at_280[0x60]; 7594 7595 u8 cq_umem_valid[0x1]; 7596 u8 reserved_at_2e1[0x1f]; 7597 7598 u8 reserved_at_300[0x580]; 7599 7600 u8 pas[][0x40]; 7601 }; 7602 7603 struct mlx5_ifc_modify_cong_status_out_bits { 7604 u8 status[0x8]; 7605 u8 reserved_at_8[0x18]; 7606 7607 u8 syndrome[0x20]; 7608 7609 u8 reserved_at_40[0x40]; 7610 }; 7611 7612 struct mlx5_ifc_modify_cong_status_in_bits { 7613 u8 opcode[0x10]; 7614 u8 reserved_at_10[0x10]; 7615 7616 u8 reserved_at_20[0x10]; 7617 u8 op_mod[0x10]; 7618 7619 u8 reserved_at_40[0x18]; 7620 u8 priority[0x4]; 7621 u8 cong_protocol[0x4]; 7622 7623 u8 enable[0x1]; 7624 u8 tag_enable[0x1]; 7625 u8 reserved_at_62[0x1e]; 7626 }; 7627 7628 struct mlx5_ifc_modify_cong_params_out_bits { 7629 u8 status[0x8]; 7630 u8 reserved_at_8[0x18]; 7631 7632 u8 syndrome[0x20]; 7633 7634 u8 reserved_at_40[0x40]; 7635 }; 7636 7637 struct mlx5_ifc_modify_cong_params_in_bits { 7638 u8 opcode[0x10]; 7639 u8 reserved_at_10[0x10]; 7640 7641 u8 reserved_at_20[0x10]; 7642 u8 op_mod[0x10]; 7643 7644 u8 reserved_at_40[0x1c]; 7645 u8 cong_protocol[0x4]; 7646 7647 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select; 7648 7649 u8 reserved_at_80[0x80]; 7650 7651 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 7652 }; 7653 7654 struct mlx5_ifc_manage_pages_out_bits { 7655 u8 status[0x8]; 7656 u8 reserved_at_8[0x18]; 7657 7658 u8 syndrome[0x20]; 7659 7660 u8 output_num_entries[0x20]; 7661 7662 u8 reserved_at_60[0x20]; 7663 7664 u8 pas[][0x40]; 7665 }; 7666 7667 enum { 7668 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL = 0x0, 7669 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS = 0x1, 7670 MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES = 0x2, 7671 }; 7672 7673 struct mlx5_ifc_manage_pages_in_bits { 7674 u8 opcode[0x10]; 7675 u8 reserved_at_10[0x10]; 7676 7677 u8 reserved_at_20[0x10]; 7678 u8 op_mod[0x10]; 7679 7680 u8 embedded_cpu_function[0x1]; 7681 u8 reserved_at_41[0xf]; 7682 u8 function_id[0x10]; 7683 7684 u8 input_num_entries[0x20]; 7685 7686 u8 pas[][0x40]; 7687 }; 7688 7689 struct mlx5_ifc_mad_ifc_out_bits { 7690 u8 status[0x8]; 7691 u8 reserved_at_8[0x18]; 7692 7693 u8 syndrome[0x20]; 7694 7695 u8 reserved_at_40[0x40]; 7696 7697 u8 response_mad_packet[256][0x8]; 7698 }; 7699 7700 struct mlx5_ifc_mad_ifc_in_bits { 7701 u8 opcode[0x10]; 7702 u8 reserved_at_10[0x10]; 7703 7704 u8 reserved_at_20[0x10]; 7705 u8 op_mod[0x10]; 7706 7707 u8 remote_lid[0x10]; 7708 u8 reserved_at_50[0x8]; 7709 u8 port[0x8]; 7710 7711 u8 reserved_at_60[0x20]; 7712 7713 u8 mad[256][0x8]; 7714 }; 7715 7716 struct mlx5_ifc_init_hca_out_bits { 7717 u8 status[0x8]; 7718 u8 reserved_at_8[0x18]; 7719 7720 u8 syndrome[0x20]; 7721 7722 u8 reserved_at_40[0x40]; 7723 }; 7724 7725 struct mlx5_ifc_init_hca_in_bits { 7726 u8 opcode[0x10]; 7727 u8 reserved_at_10[0x10]; 7728 7729 u8 reserved_at_20[0x10]; 7730 u8 op_mod[0x10]; 7731 7732 u8 reserved_at_40[0x20]; 7733 7734 u8 reserved_at_60[0x2]; 7735 u8 sw_vhca_id[0xe]; 7736 u8 reserved_at_70[0x10]; 7737 7738 u8 sw_owner_id[4][0x20]; 7739 }; 7740 7741 struct mlx5_ifc_init2rtr_qp_out_bits { 7742 u8 status[0x8]; 7743 u8 reserved_at_8[0x18]; 7744 7745 u8 syndrome[0x20]; 7746 7747 u8 reserved_at_40[0x20]; 7748 u8 ece[0x20]; 7749 }; 7750 7751 struct mlx5_ifc_init2rtr_qp_in_bits { 7752 u8 opcode[0x10]; 7753 u8 uid[0x10]; 7754 7755 u8 reserved_at_20[0x10]; 7756 u8 op_mod[0x10]; 7757 7758 u8 reserved_at_40[0x8]; 7759 u8 qpn[0x18]; 7760 7761 u8 reserved_at_60[0x20]; 7762 7763 u8 opt_param_mask[0x20]; 7764 7765 u8 ece[0x20]; 7766 7767 struct mlx5_ifc_qpc_bits qpc; 7768 7769 u8 reserved_at_800[0x80]; 7770 }; 7771 7772 struct mlx5_ifc_init2init_qp_out_bits { 7773 u8 status[0x8]; 7774 u8 reserved_at_8[0x18]; 7775 7776 u8 syndrome[0x20]; 7777 7778 u8 reserved_at_40[0x20]; 7779 u8 ece[0x20]; 7780 }; 7781 7782 struct mlx5_ifc_init2init_qp_in_bits { 7783 u8 opcode[0x10]; 7784 u8 uid[0x10]; 7785 7786 u8 reserved_at_20[0x10]; 7787 u8 op_mod[0x10]; 7788 7789 u8 reserved_at_40[0x8]; 7790 u8 qpn[0x18]; 7791 7792 u8 reserved_at_60[0x20]; 7793 7794 u8 opt_param_mask[0x20]; 7795 7796 u8 ece[0x20]; 7797 7798 struct mlx5_ifc_qpc_bits qpc; 7799 7800 u8 reserved_at_800[0x80]; 7801 }; 7802 7803 struct mlx5_ifc_get_dropped_packet_log_out_bits { 7804 u8 status[0x8]; 7805 u8 reserved_at_8[0x18]; 7806 7807 u8 syndrome[0x20]; 7808 7809 u8 reserved_at_40[0x40]; 7810 7811 u8 packet_headers_log[128][0x8]; 7812 7813 u8 packet_syndrome[64][0x8]; 7814 }; 7815 7816 struct mlx5_ifc_get_dropped_packet_log_in_bits { 7817 u8 opcode[0x10]; 7818 u8 reserved_at_10[0x10]; 7819 7820 u8 reserved_at_20[0x10]; 7821 u8 op_mod[0x10]; 7822 7823 u8 reserved_at_40[0x40]; 7824 }; 7825 7826 struct mlx5_ifc_gen_eqe_in_bits { 7827 u8 opcode[0x10]; 7828 u8 reserved_at_10[0x10]; 7829 7830 u8 reserved_at_20[0x10]; 7831 u8 op_mod[0x10]; 7832 7833 u8 reserved_at_40[0x18]; 7834 u8 eq_number[0x8]; 7835 7836 u8 reserved_at_60[0x20]; 7837 7838 u8 eqe[64][0x8]; 7839 }; 7840 7841 struct mlx5_ifc_gen_eq_out_bits { 7842 u8 status[0x8]; 7843 u8 reserved_at_8[0x18]; 7844 7845 u8 syndrome[0x20]; 7846 7847 u8 reserved_at_40[0x40]; 7848 }; 7849 7850 struct mlx5_ifc_enable_hca_out_bits { 7851 u8 status[0x8]; 7852 u8 reserved_at_8[0x18]; 7853 7854 u8 syndrome[0x20]; 7855 7856 u8 reserved_at_40[0x20]; 7857 }; 7858 7859 struct mlx5_ifc_enable_hca_in_bits { 7860 u8 opcode[0x10]; 7861 u8 reserved_at_10[0x10]; 7862 7863 u8 reserved_at_20[0x10]; 7864 u8 op_mod[0x10]; 7865 7866 u8 embedded_cpu_function[0x1]; 7867 u8 reserved_at_41[0xf]; 7868 u8 function_id[0x10]; 7869 7870 u8 reserved_at_60[0x20]; 7871 }; 7872 7873 struct mlx5_ifc_drain_dct_out_bits { 7874 u8 status[0x8]; 7875 u8 reserved_at_8[0x18]; 7876 7877 u8 syndrome[0x20]; 7878 7879 u8 reserved_at_40[0x40]; 7880 }; 7881 7882 struct mlx5_ifc_drain_dct_in_bits { 7883 u8 opcode[0x10]; 7884 u8 uid[0x10]; 7885 7886 u8 reserved_at_20[0x10]; 7887 u8 op_mod[0x10]; 7888 7889 u8 reserved_at_40[0x8]; 7890 u8 dctn[0x18]; 7891 7892 u8 reserved_at_60[0x20]; 7893 }; 7894 7895 struct mlx5_ifc_disable_hca_out_bits { 7896 u8 status[0x8]; 7897 u8 reserved_at_8[0x18]; 7898 7899 u8 syndrome[0x20]; 7900 7901 u8 reserved_at_40[0x20]; 7902 }; 7903 7904 struct mlx5_ifc_disable_hca_in_bits { 7905 u8 opcode[0x10]; 7906 u8 reserved_at_10[0x10]; 7907 7908 u8 reserved_at_20[0x10]; 7909 u8 op_mod[0x10]; 7910 7911 u8 embedded_cpu_function[0x1]; 7912 u8 reserved_at_41[0xf]; 7913 u8 function_id[0x10]; 7914 7915 u8 reserved_at_60[0x20]; 7916 }; 7917 7918 struct mlx5_ifc_detach_from_mcg_out_bits { 7919 u8 status[0x8]; 7920 u8 reserved_at_8[0x18]; 7921 7922 u8 syndrome[0x20]; 7923 7924 u8 reserved_at_40[0x40]; 7925 }; 7926 7927 struct mlx5_ifc_detach_from_mcg_in_bits { 7928 u8 opcode[0x10]; 7929 u8 uid[0x10]; 7930 7931 u8 reserved_at_20[0x10]; 7932 u8 op_mod[0x10]; 7933 7934 u8 reserved_at_40[0x8]; 7935 u8 qpn[0x18]; 7936 7937 u8 reserved_at_60[0x20]; 7938 7939 u8 multicast_gid[16][0x8]; 7940 }; 7941 7942 struct mlx5_ifc_destroy_xrq_out_bits { 7943 u8 status[0x8]; 7944 u8 reserved_at_8[0x18]; 7945 7946 u8 syndrome[0x20]; 7947 7948 u8 reserved_at_40[0x40]; 7949 }; 7950 7951 struct mlx5_ifc_destroy_xrq_in_bits { 7952 u8 opcode[0x10]; 7953 u8 uid[0x10]; 7954 7955 u8 reserved_at_20[0x10]; 7956 u8 op_mod[0x10]; 7957 7958 u8 reserved_at_40[0x8]; 7959 u8 xrqn[0x18]; 7960 7961 u8 reserved_at_60[0x20]; 7962 }; 7963 7964 struct mlx5_ifc_destroy_xrc_srq_out_bits { 7965 u8 status[0x8]; 7966 u8 reserved_at_8[0x18]; 7967 7968 u8 syndrome[0x20]; 7969 7970 u8 reserved_at_40[0x40]; 7971 }; 7972 7973 struct mlx5_ifc_destroy_xrc_srq_in_bits { 7974 u8 opcode[0x10]; 7975 u8 uid[0x10]; 7976 7977 u8 reserved_at_20[0x10]; 7978 u8 op_mod[0x10]; 7979 7980 u8 reserved_at_40[0x8]; 7981 u8 xrc_srqn[0x18]; 7982 7983 u8 reserved_at_60[0x20]; 7984 }; 7985 7986 struct mlx5_ifc_destroy_tis_out_bits { 7987 u8 status[0x8]; 7988 u8 reserved_at_8[0x18]; 7989 7990 u8 syndrome[0x20]; 7991 7992 u8 reserved_at_40[0x40]; 7993 }; 7994 7995 struct mlx5_ifc_destroy_tis_in_bits { 7996 u8 opcode[0x10]; 7997 u8 uid[0x10]; 7998 7999 u8 reserved_at_20[0x10]; 8000 u8 op_mod[0x10]; 8001 8002 u8 reserved_at_40[0x8]; 8003 u8 tisn[0x18]; 8004 8005 u8 reserved_at_60[0x20]; 8006 }; 8007 8008 struct mlx5_ifc_destroy_tir_out_bits { 8009 u8 status[0x8]; 8010 u8 reserved_at_8[0x18]; 8011 8012 u8 syndrome[0x20]; 8013 8014 u8 reserved_at_40[0x40]; 8015 }; 8016 8017 struct mlx5_ifc_destroy_tir_in_bits { 8018 u8 opcode[0x10]; 8019 u8 uid[0x10]; 8020 8021 u8 reserved_at_20[0x10]; 8022 u8 op_mod[0x10]; 8023 8024 u8 reserved_at_40[0x8]; 8025 u8 tirn[0x18]; 8026 8027 u8 reserved_at_60[0x20]; 8028 }; 8029 8030 struct mlx5_ifc_destroy_srq_out_bits { 8031 u8 status[0x8]; 8032 u8 reserved_at_8[0x18]; 8033 8034 u8 syndrome[0x20]; 8035 8036 u8 reserved_at_40[0x40]; 8037 }; 8038 8039 struct mlx5_ifc_destroy_srq_in_bits { 8040 u8 opcode[0x10]; 8041 u8 uid[0x10]; 8042 8043 u8 reserved_at_20[0x10]; 8044 u8 op_mod[0x10]; 8045 8046 u8 reserved_at_40[0x8]; 8047 u8 srqn[0x18]; 8048 8049 u8 reserved_at_60[0x20]; 8050 }; 8051 8052 struct mlx5_ifc_destroy_sq_out_bits { 8053 u8 status[0x8]; 8054 u8 reserved_at_8[0x18]; 8055 8056 u8 syndrome[0x20]; 8057 8058 u8 reserved_at_40[0x40]; 8059 }; 8060 8061 struct mlx5_ifc_destroy_sq_in_bits { 8062 u8 opcode[0x10]; 8063 u8 uid[0x10]; 8064 8065 u8 reserved_at_20[0x10]; 8066 u8 op_mod[0x10]; 8067 8068 u8 reserved_at_40[0x8]; 8069 u8 sqn[0x18]; 8070 8071 u8 reserved_at_60[0x20]; 8072 }; 8073 8074 struct mlx5_ifc_destroy_scheduling_element_out_bits { 8075 u8 status[0x8]; 8076 u8 reserved_at_8[0x18]; 8077 8078 u8 syndrome[0x20]; 8079 8080 u8 reserved_at_40[0x1c0]; 8081 }; 8082 8083 struct mlx5_ifc_destroy_scheduling_element_in_bits { 8084 u8 opcode[0x10]; 8085 u8 reserved_at_10[0x10]; 8086 8087 u8 reserved_at_20[0x10]; 8088 u8 op_mod[0x10]; 8089 8090 u8 scheduling_hierarchy[0x8]; 8091 u8 reserved_at_48[0x18]; 8092 8093 u8 scheduling_element_id[0x20]; 8094 8095 u8 reserved_at_80[0x180]; 8096 }; 8097 8098 struct mlx5_ifc_destroy_rqt_out_bits { 8099 u8 status[0x8]; 8100 u8 reserved_at_8[0x18]; 8101 8102 u8 syndrome[0x20]; 8103 8104 u8 reserved_at_40[0x40]; 8105 }; 8106 8107 struct mlx5_ifc_destroy_rqt_in_bits { 8108 u8 opcode[0x10]; 8109 u8 uid[0x10]; 8110 8111 u8 reserved_at_20[0x10]; 8112 u8 op_mod[0x10]; 8113 8114 u8 reserved_at_40[0x8]; 8115 u8 rqtn[0x18]; 8116 8117 u8 reserved_at_60[0x20]; 8118 }; 8119 8120 struct mlx5_ifc_destroy_rq_out_bits { 8121 u8 status[0x8]; 8122 u8 reserved_at_8[0x18]; 8123 8124 u8 syndrome[0x20]; 8125 8126 u8 reserved_at_40[0x40]; 8127 }; 8128 8129 struct mlx5_ifc_destroy_rq_in_bits { 8130 u8 opcode[0x10]; 8131 u8 uid[0x10]; 8132 8133 u8 reserved_at_20[0x10]; 8134 u8 op_mod[0x10]; 8135 8136 u8 reserved_at_40[0x8]; 8137 u8 rqn[0x18]; 8138 8139 u8 reserved_at_60[0x20]; 8140 }; 8141 8142 struct mlx5_ifc_set_delay_drop_params_in_bits { 8143 u8 opcode[0x10]; 8144 u8 reserved_at_10[0x10]; 8145 8146 u8 reserved_at_20[0x10]; 8147 u8 op_mod[0x10]; 8148 8149 u8 reserved_at_40[0x20]; 8150 8151 u8 reserved_at_60[0x10]; 8152 u8 delay_drop_timeout[0x10]; 8153 }; 8154 8155 struct mlx5_ifc_set_delay_drop_params_out_bits { 8156 u8 status[0x8]; 8157 u8 reserved_at_8[0x18]; 8158 8159 u8 syndrome[0x20]; 8160 8161 u8 reserved_at_40[0x40]; 8162 }; 8163 8164 struct mlx5_ifc_destroy_rmp_out_bits { 8165 u8 status[0x8]; 8166 u8 reserved_at_8[0x18]; 8167 8168 u8 syndrome[0x20]; 8169 8170 u8 reserved_at_40[0x40]; 8171 }; 8172 8173 struct mlx5_ifc_destroy_rmp_in_bits { 8174 u8 opcode[0x10]; 8175 u8 uid[0x10]; 8176 8177 u8 reserved_at_20[0x10]; 8178 u8 op_mod[0x10]; 8179 8180 u8 reserved_at_40[0x8]; 8181 u8 rmpn[0x18]; 8182 8183 u8 reserved_at_60[0x20]; 8184 }; 8185 8186 struct mlx5_ifc_destroy_qp_out_bits { 8187 u8 status[0x8]; 8188 u8 reserved_at_8[0x18]; 8189 8190 u8 syndrome[0x20]; 8191 8192 u8 reserved_at_40[0x40]; 8193 }; 8194 8195 struct mlx5_ifc_destroy_qp_in_bits { 8196 u8 opcode[0x10]; 8197 u8 uid[0x10]; 8198 8199 u8 reserved_at_20[0x10]; 8200 u8 op_mod[0x10]; 8201 8202 u8 reserved_at_40[0x8]; 8203 u8 qpn[0x18]; 8204 8205 u8 reserved_at_60[0x20]; 8206 }; 8207 8208 struct mlx5_ifc_destroy_psv_out_bits { 8209 u8 status[0x8]; 8210 u8 reserved_at_8[0x18]; 8211 8212 u8 syndrome[0x20]; 8213 8214 u8 reserved_at_40[0x40]; 8215 }; 8216 8217 struct mlx5_ifc_destroy_psv_in_bits { 8218 u8 opcode[0x10]; 8219 u8 reserved_at_10[0x10]; 8220 8221 u8 reserved_at_20[0x10]; 8222 u8 op_mod[0x10]; 8223 8224 u8 reserved_at_40[0x8]; 8225 u8 psvn[0x18]; 8226 8227 u8 reserved_at_60[0x20]; 8228 }; 8229 8230 struct mlx5_ifc_destroy_mkey_out_bits { 8231 u8 status[0x8]; 8232 u8 reserved_at_8[0x18]; 8233 8234 u8 syndrome[0x20]; 8235 8236 u8 reserved_at_40[0x40]; 8237 }; 8238 8239 struct mlx5_ifc_destroy_mkey_in_bits { 8240 u8 opcode[0x10]; 8241 u8 uid[0x10]; 8242 8243 u8 reserved_at_20[0x10]; 8244 u8 op_mod[0x10]; 8245 8246 u8 reserved_at_40[0x8]; 8247 u8 mkey_index[0x18]; 8248 8249 u8 reserved_at_60[0x20]; 8250 }; 8251 8252 struct mlx5_ifc_destroy_flow_table_out_bits { 8253 u8 status[0x8]; 8254 u8 reserved_at_8[0x18]; 8255 8256 u8 syndrome[0x20]; 8257 8258 u8 reserved_at_40[0x40]; 8259 }; 8260 8261 struct mlx5_ifc_destroy_flow_table_in_bits { 8262 u8 opcode[0x10]; 8263 u8 reserved_at_10[0x10]; 8264 8265 u8 reserved_at_20[0x10]; 8266 u8 op_mod[0x10]; 8267 8268 u8 other_vport[0x1]; 8269 u8 reserved_at_41[0xf]; 8270 u8 vport_number[0x10]; 8271 8272 u8 reserved_at_60[0x20]; 8273 8274 u8 table_type[0x8]; 8275 u8 reserved_at_88[0x18]; 8276 8277 u8 reserved_at_a0[0x8]; 8278 u8 table_id[0x18]; 8279 8280 u8 reserved_at_c0[0x140]; 8281 }; 8282 8283 struct mlx5_ifc_destroy_flow_group_out_bits { 8284 u8 status[0x8]; 8285 u8 reserved_at_8[0x18]; 8286 8287 u8 syndrome[0x20]; 8288 8289 u8 reserved_at_40[0x40]; 8290 }; 8291 8292 struct mlx5_ifc_destroy_flow_group_in_bits { 8293 u8 opcode[0x10]; 8294 u8 reserved_at_10[0x10]; 8295 8296 u8 reserved_at_20[0x10]; 8297 u8 op_mod[0x10]; 8298 8299 u8 other_vport[0x1]; 8300 u8 reserved_at_41[0xf]; 8301 u8 vport_number[0x10]; 8302 8303 u8 reserved_at_60[0x20]; 8304 8305 u8 table_type[0x8]; 8306 u8 reserved_at_88[0x18]; 8307 8308 u8 reserved_at_a0[0x8]; 8309 u8 table_id[0x18]; 8310 8311 u8 group_id[0x20]; 8312 8313 u8 reserved_at_e0[0x120]; 8314 }; 8315 8316 struct mlx5_ifc_destroy_eq_out_bits { 8317 u8 status[0x8]; 8318 u8 reserved_at_8[0x18]; 8319 8320 u8 syndrome[0x20]; 8321 8322 u8 reserved_at_40[0x40]; 8323 }; 8324 8325 struct mlx5_ifc_destroy_eq_in_bits { 8326 u8 opcode[0x10]; 8327 u8 reserved_at_10[0x10]; 8328 8329 u8 reserved_at_20[0x10]; 8330 u8 op_mod[0x10]; 8331 8332 u8 reserved_at_40[0x18]; 8333 u8 eq_number[0x8]; 8334 8335 u8 reserved_at_60[0x20]; 8336 }; 8337 8338 struct mlx5_ifc_destroy_dct_out_bits { 8339 u8 status[0x8]; 8340 u8 reserved_at_8[0x18]; 8341 8342 u8 syndrome[0x20]; 8343 8344 u8 reserved_at_40[0x40]; 8345 }; 8346 8347 struct mlx5_ifc_destroy_dct_in_bits { 8348 u8 opcode[0x10]; 8349 u8 uid[0x10]; 8350 8351 u8 reserved_at_20[0x10]; 8352 u8 op_mod[0x10]; 8353 8354 u8 reserved_at_40[0x8]; 8355 u8 dctn[0x18]; 8356 8357 u8 reserved_at_60[0x20]; 8358 }; 8359 8360 struct mlx5_ifc_destroy_cq_out_bits { 8361 u8 status[0x8]; 8362 u8 reserved_at_8[0x18]; 8363 8364 u8 syndrome[0x20]; 8365 8366 u8 reserved_at_40[0x40]; 8367 }; 8368 8369 struct mlx5_ifc_destroy_cq_in_bits { 8370 u8 opcode[0x10]; 8371 u8 uid[0x10]; 8372 8373 u8 reserved_at_20[0x10]; 8374 u8 op_mod[0x10]; 8375 8376 u8 reserved_at_40[0x8]; 8377 u8 cqn[0x18]; 8378 8379 u8 reserved_at_60[0x20]; 8380 }; 8381 8382 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits { 8383 u8 status[0x8]; 8384 u8 reserved_at_8[0x18]; 8385 8386 u8 syndrome[0x20]; 8387 8388 u8 reserved_at_40[0x40]; 8389 }; 8390 8391 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits { 8392 u8 opcode[0x10]; 8393 u8 reserved_at_10[0x10]; 8394 8395 u8 reserved_at_20[0x10]; 8396 u8 op_mod[0x10]; 8397 8398 u8 reserved_at_40[0x20]; 8399 8400 u8 reserved_at_60[0x10]; 8401 u8 vxlan_udp_port[0x10]; 8402 }; 8403 8404 struct mlx5_ifc_delete_l2_table_entry_out_bits { 8405 u8 status[0x8]; 8406 u8 reserved_at_8[0x18]; 8407 8408 u8 syndrome[0x20]; 8409 8410 u8 reserved_at_40[0x40]; 8411 }; 8412 8413 struct mlx5_ifc_delete_l2_table_entry_in_bits { 8414 u8 opcode[0x10]; 8415 u8 reserved_at_10[0x10]; 8416 8417 u8 reserved_at_20[0x10]; 8418 u8 op_mod[0x10]; 8419 8420 u8 reserved_at_40[0x60]; 8421 8422 u8 reserved_at_a0[0x8]; 8423 u8 table_index[0x18]; 8424 8425 u8 reserved_at_c0[0x140]; 8426 }; 8427 8428 struct mlx5_ifc_delete_fte_out_bits { 8429 u8 status[0x8]; 8430 u8 reserved_at_8[0x18]; 8431 8432 u8 syndrome[0x20]; 8433 8434 u8 reserved_at_40[0x40]; 8435 }; 8436 8437 struct mlx5_ifc_delete_fte_in_bits { 8438 u8 opcode[0x10]; 8439 u8 reserved_at_10[0x10]; 8440 8441 u8 reserved_at_20[0x10]; 8442 u8 op_mod[0x10]; 8443 8444 u8 other_vport[0x1]; 8445 u8 reserved_at_41[0xf]; 8446 u8 vport_number[0x10]; 8447 8448 u8 reserved_at_60[0x20]; 8449 8450 u8 table_type[0x8]; 8451 u8 reserved_at_88[0x18]; 8452 8453 u8 reserved_at_a0[0x8]; 8454 u8 table_id[0x18]; 8455 8456 u8 reserved_at_c0[0x40]; 8457 8458 u8 flow_index[0x20]; 8459 8460 u8 reserved_at_120[0xe0]; 8461 }; 8462 8463 struct mlx5_ifc_dealloc_xrcd_out_bits { 8464 u8 status[0x8]; 8465 u8 reserved_at_8[0x18]; 8466 8467 u8 syndrome[0x20]; 8468 8469 u8 reserved_at_40[0x40]; 8470 }; 8471 8472 struct mlx5_ifc_dealloc_xrcd_in_bits { 8473 u8 opcode[0x10]; 8474 u8 uid[0x10]; 8475 8476 u8 reserved_at_20[0x10]; 8477 u8 op_mod[0x10]; 8478 8479 u8 reserved_at_40[0x8]; 8480 u8 xrcd[0x18]; 8481 8482 u8 reserved_at_60[0x20]; 8483 }; 8484 8485 struct mlx5_ifc_dealloc_uar_out_bits { 8486 u8 status[0x8]; 8487 u8 reserved_at_8[0x18]; 8488 8489 u8 syndrome[0x20]; 8490 8491 u8 reserved_at_40[0x40]; 8492 }; 8493 8494 struct mlx5_ifc_dealloc_uar_in_bits { 8495 u8 opcode[0x10]; 8496 u8 uid[0x10]; 8497 8498 u8 reserved_at_20[0x10]; 8499 u8 op_mod[0x10]; 8500 8501 u8 reserved_at_40[0x8]; 8502 u8 uar[0x18]; 8503 8504 u8 reserved_at_60[0x20]; 8505 }; 8506 8507 struct mlx5_ifc_dealloc_transport_domain_out_bits { 8508 u8 status[0x8]; 8509 u8 reserved_at_8[0x18]; 8510 8511 u8 syndrome[0x20]; 8512 8513 u8 reserved_at_40[0x40]; 8514 }; 8515 8516 struct mlx5_ifc_dealloc_transport_domain_in_bits { 8517 u8 opcode[0x10]; 8518 u8 uid[0x10]; 8519 8520 u8 reserved_at_20[0x10]; 8521 u8 op_mod[0x10]; 8522 8523 u8 reserved_at_40[0x8]; 8524 u8 transport_domain[0x18]; 8525 8526 u8 reserved_at_60[0x20]; 8527 }; 8528 8529 struct mlx5_ifc_dealloc_q_counter_out_bits { 8530 u8 status[0x8]; 8531 u8 reserved_at_8[0x18]; 8532 8533 u8 syndrome[0x20]; 8534 8535 u8 reserved_at_40[0x40]; 8536 }; 8537 8538 struct mlx5_ifc_dealloc_q_counter_in_bits { 8539 u8 opcode[0x10]; 8540 u8 reserved_at_10[0x10]; 8541 8542 u8 reserved_at_20[0x10]; 8543 u8 op_mod[0x10]; 8544 8545 u8 reserved_at_40[0x18]; 8546 u8 counter_set_id[0x8]; 8547 8548 u8 reserved_at_60[0x20]; 8549 }; 8550 8551 struct mlx5_ifc_dealloc_pd_out_bits { 8552 u8 status[0x8]; 8553 u8 reserved_at_8[0x18]; 8554 8555 u8 syndrome[0x20]; 8556 8557 u8 reserved_at_40[0x40]; 8558 }; 8559 8560 struct mlx5_ifc_dealloc_pd_in_bits { 8561 u8 opcode[0x10]; 8562 u8 uid[0x10]; 8563 8564 u8 reserved_at_20[0x10]; 8565 u8 op_mod[0x10]; 8566 8567 u8 reserved_at_40[0x8]; 8568 u8 pd[0x18]; 8569 8570 u8 reserved_at_60[0x20]; 8571 }; 8572 8573 struct mlx5_ifc_dealloc_flow_counter_out_bits { 8574 u8 status[0x8]; 8575 u8 reserved_at_8[0x18]; 8576 8577 u8 syndrome[0x20]; 8578 8579 u8 reserved_at_40[0x40]; 8580 }; 8581 8582 struct mlx5_ifc_dealloc_flow_counter_in_bits { 8583 u8 opcode[0x10]; 8584 u8 reserved_at_10[0x10]; 8585 8586 u8 reserved_at_20[0x10]; 8587 u8 op_mod[0x10]; 8588 8589 u8 flow_counter_id[0x20]; 8590 8591 u8 reserved_at_60[0x20]; 8592 }; 8593 8594 struct mlx5_ifc_create_xrq_out_bits { 8595 u8 status[0x8]; 8596 u8 reserved_at_8[0x18]; 8597 8598 u8 syndrome[0x20]; 8599 8600 u8 reserved_at_40[0x8]; 8601 u8 xrqn[0x18]; 8602 8603 u8 reserved_at_60[0x20]; 8604 }; 8605 8606 struct mlx5_ifc_create_xrq_in_bits { 8607 u8 opcode[0x10]; 8608 u8 uid[0x10]; 8609 8610 u8 reserved_at_20[0x10]; 8611 u8 op_mod[0x10]; 8612 8613 u8 reserved_at_40[0x40]; 8614 8615 struct mlx5_ifc_xrqc_bits xrq_context; 8616 }; 8617 8618 struct mlx5_ifc_create_xrc_srq_out_bits { 8619 u8 status[0x8]; 8620 u8 reserved_at_8[0x18]; 8621 8622 u8 syndrome[0x20]; 8623 8624 u8 reserved_at_40[0x8]; 8625 u8 xrc_srqn[0x18]; 8626 8627 u8 reserved_at_60[0x20]; 8628 }; 8629 8630 struct mlx5_ifc_create_xrc_srq_in_bits { 8631 u8 opcode[0x10]; 8632 u8 uid[0x10]; 8633 8634 u8 reserved_at_20[0x10]; 8635 u8 op_mod[0x10]; 8636 8637 u8 reserved_at_40[0x40]; 8638 8639 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 8640 8641 u8 reserved_at_280[0x60]; 8642 8643 u8 xrc_srq_umem_valid[0x1]; 8644 u8 reserved_at_2e1[0x1f]; 8645 8646 u8 reserved_at_300[0x580]; 8647 8648 u8 pas[][0x40]; 8649 }; 8650 8651 struct mlx5_ifc_create_tis_out_bits { 8652 u8 status[0x8]; 8653 u8 reserved_at_8[0x18]; 8654 8655 u8 syndrome[0x20]; 8656 8657 u8 reserved_at_40[0x8]; 8658 u8 tisn[0x18]; 8659 8660 u8 reserved_at_60[0x20]; 8661 }; 8662 8663 struct mlx5_ifc_create_tis_in_bits { 8664 u8 opcode[0x10]; 8665 u8 uid[0x10]; 8666 8667 u8 reserved_at_20[0x10]; 8668 u8 op_mod[0x10]; 8669 8670 u8 reserved_at_40[0xc0]; 8671 8672 struct mlx5_ifc_tisc_bits ctx; 8673 }; 8674 8675 struct mlx5_ifc_create_tir_out_bits { 8676 u8 status[0x8]; 8677 u8 icm_address_63_40[0x18]; 8678 8679 u8 syndrome[0x20]; 8680 8681 u8 icm_address_39_32[0x8]; 8682 u8 tirn[0x18]; 8683 8684 u8 icm_address_31_0[0x20]; 8685 }; 8686 8687 struct mlx5_ifc_create_tir_in_bits { 8688 u8 opcode[0x10]; 8689 u8 uid[0x10]; 8690 8691 u8 reserved_at_20[0x10]; 8692 u8 op_mod[0x10]; 8693 8694 u8 reserved_at_40[0xc0]; 8695 8696 struct mlx5_ifc_tirc_bits ctx; 8697 }; 8698 8699 struct mlx5_ifc_create_srq_out_bits { 8700 u8 status[0x8]; 8701 u8 reserved_at_8[0x18]; 8702 8703 u8 syndrome[0x20]; 8704 8705 u8 reserved_at_40[0x8]; 8706 u8 srqn[0x18]; 8707 8708 u8 reserved_at_60[0x20]; 8709 }; 8710 8711 struct mlx5_ifc_create_srq_in_bits { 8712 u8 opcode[0x10]; 8713 u8 uid[0x10]; 8714 8715 u8 reserved_at_20[0x10]; 8716 u8 op_mod[0x10]; 8717 8718 u8 reserved_at_40[0x40]; 8719 8720 struct mlx5_ifc_srqc_bits srq_context_entry; 8721 8722 u8 reserved_at_280[0x600]; 8723 8724 u8 pas[][0x40]; 8725 }; 8726 8727 struct mlx5_ifc_create_sq_out_bits { 8728 u8 status[0x8]; 8729 u8 reserved_at_8[0x18]; 8730 8731 u8 syndrome[0x20]; 8732 8733 u8 reserved_at_40[0x8]; 8734 u8 sqn[0x18]; 8735 8736 u8 reserved_at_60[0x20]; 8737 }; 8738 8739 struct mlx5_ifc_create_sq_in_bits { 8740 u8 opcode[0x10]; 8741 u8 uid[0x10]; 8742 8743 u8 reserved_at_20[0x10]; 8744 u8 op_mod[0x10]; 8745 8746 u8 reserved_at_40[0xc0]; 8747 8748 struct mlx5_ifc_sqc_bits ctx; 8749 }; 8750 8751 struct mlx5_ifc_create_scheduling_element_out_bits { 8752 u8 status[0x8]; 8753 u8 reserved_at_8[0x18]; 8754 8755 u8 syndrome[0x20]; 8756 8757 u8 reserved_at_40[0x40]; 8758 8759 u8 scheduling_element_id[0x20]; 8760 8761 u8 reserved_at_a0[0x160]; 8762 }; 8763 8764 struct mlx5_ifc_create_scheduling_element_in_bits { 8765 u8 opcode[0x10]; 8766 u8 reserved_at_10[0x10]; 8767 8768 u8 reserved_at_20[0x10]; 8769 u8 op_mod[0x10]; 8770 8771 u8 scheduling_hierarchy[0x8]; 8772 u8 reserved_at_48[0x18]; 8773 8774 u8 reserved_at_60[0xa0]; 8775 8776 struct mlx5_ifc_scheduling_context_bits scheduling_context; 8777 8778 u8 reserved_at_300[0x100]; 8779 }; 8780 8781 struct mlx5_ifc_create_rqt_out_bits { 8782 u8 status[0x8]; 8783 u8 reserved_at_8[0x18]; 8784 8785 u8 syndrome[0x20]; 8786 8787 u8 reserved_at_40[0x8]; 8788 u8 rqtn[0x18]; 8789 8790 u8 reserved_at_60[0x20]; 8791 }; 8792 8793 struct mlx5_ifc_create_rqt_in_bits { 8794 u8 opcode[0x10]; 8795 u8 uid[0x10]; 8796 8797 u8 reserved_at_20[0x10]; 8798 u8 op_mod[0x10]; 8799 8800 u8 reserved_at_40[0xc0]; 8801 8802 struct mlx5_ifc_rqtc_bits rqt_context; 8803 }; 8804 8805 struct mlx5_ifc_create_rq_out_bits { 8806 u8 status[0x8]; 8807 u8 reserved_at_8[0x18]; 8808 8809 u8 syndrome[0x20]; 8810 8811 u8 reserved_at_40[0x8]; 8812 u8 rqn[0x18]; 8813 8814 u8 reserved_at_60[0x20]; 8815 }; 8816 8817 struct mlx5_ifc_create_rq_in_bits { 8818 u8 opcode[0x10]; 8819 u8 uid[0x10]; 8820 8821 u8 reserved_at_20[0x10]; 8822 u8 op_mod[0x10]; 8823 8824 u8 reserved_at_40[0xc0]; 8825 8826 struct mlx5_ifc_rqc_bits ctx; 8827 }; 8828 8829 struct mlx5_ifc_create_rmp_out_bits { 8830 u8 status[0x8]; 8831 u8 reserved_at_8[0x18]; 8832 8833 u8 syndrome[0x20]; 8834 8835 u8 reserved_at_40[0x8]; 8836 u8 rmpn[0x18]; 8837 8838 u8 reserved_at_60[0x20]; 8839 }; 8840 8841 struct mlx5_ifc_create_rmp_in_bits { 8842 u8 opcode[0x10]; 8843 u8 uid[0x10]; 8844 8845 u8 reserved_at_20[0x10]; 8846 u8 op_mod[0x10]; 8847 8848 u8 reserved_at_40[0xc0]; 8849 8850 struct mlx5_ifc_rmpc_bits ctx; 8851 }; 8852 8853 struct mlx5_ifc_create_qp_out_bits { 8854 u8 status[0x8]; 8855 u8 reserved_at_8[0x18]; 8856 8857 u8 syndrome[0x20]; 8858 8859 u8 reserved_at_40[0x8]; 8860 u8 qpn[0x18]; 8861 8862 u8 ece[0x20]; 8863 }; 8864 8865 struct mlx5_ifc_create_qp_in_bits { 8866 u8 opcode[0x10]; 8867 u8 uid[0x10]; 8868 8869 u8 reserved_at_20[0x10]; 8870 u8 op_mod[0x10]; 8871 8872 u8 qpc_ext[0x1]; 8873 u8 reserved_at_41[0x7]; 8874 u8 input_qpn[0x18]; 8875 8876 u8 reserved_at_60[0x20]; 8877 u8 opt_param_mask[0x20]; 8878 8879 u8 ece[0x20]; 8880 8881 struct mlx5_ifc_qpc_bits qpc; 8882 8883 u8 reserved_at_800[0x60]; 8884 8885 u8 wq_umem_valid[0x1]; 8886 u8 reserved_at_861[0x1f]; 8887 8888 u8 pas[][0x40]; 8889 }; 8890 8891 struct mlx5_ifc_create_psv_out_bits { 8892 u8 status[0x8]; 8893 u8 reserved_at_8[0x18]; 8894 8895 u8 syndrome[0x20]; 8896 8897 u8 reserved_at_40[0x40]; 8898 8899 u8 reserved_at_80[0x8]; 8900 u8 psv0_index[0x18]; 8901 8902 u8 reserved_at_a0[0x8]; 8903 u8 psv1_index[0x18]; 8904 8905 u8 reserved_at_c0[0x8]; 8906 u8 psv2_index[0x18]; 8907 8908 u8 reserved_at_e0[0x8]; 8909 u8 psv3_index[0x18]; 8910 }; 8911 8912 struct mlx5_ifc_create_psv_in_bits { 8913 u8 opcode[0x10]; 8914 u8 reserved_at_10[0x10]; 8915 8916 u8 reserved_at_20[0x10]; 8917 u8 op_mod[0x10]; 8918 8919 u8 num_psv[0x4]; 8920 u8 reserved_at_44[0x4]; 8921 u8 pd[0x18]; 8922 8923 u8 reserved_at_60[0x20]; 8924 }; 8925 8926 struct mlx5_ifc_create_mkey_out_bits { 8927 u8 status[0x8]; 8928 u8 reserved_at_8[0x18]; 8929 8930 u8 syndrome[0x20]; 8931 8932 u8 reserved_at_40[0x8]; 8933 u8 mkey_index[0x18]; 8934 8935 u8 reserved_at_60[0x20]; 8936 }; 8937 8938 struct mlx5_ifc_create_mkey_in_bits { 8939 u8 opcode[0x10]; 8940 u8 uid[0x10]; 8941 8942 u8 reserved_at_20[0x10]; 8943 u8 op_mod[0x10]; 8944 8945 u8 reserved_at_40[0x20]; 8946 8947 u8 pg_access[0x1]; 8948 u8 mkey_umem_valid[0x1]; 8949 u8 reserved_at_62[0x1e]; 8950 8951 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 8952 8953 u8 reserved_at_280[0x80]; 8954 8955 u8 translations_octword_actual_size[0x20]; 8956 8957 u8 reserved_at_320[0x560]; 8958 8959 u8 klm_pas_mtt[][0x20]; 8960 }; 8961 8962 enum { 8963 MLX5_FLOW_TABLE_TYPE_NIC_RX = 0x0, 8964 MLX5_FLOW_TABLE_TYPE_NIC_TX = 0x1, 8965 MLX5_FLOW_TABLE_TYPE_ESW_EGRESS_ACL = 0x2, 8966 MLX5_FLOW_TABLE_TYPE_ESW_INGRESS_ACL = 0x3, 8967 MLX5_FLOW_TABLE_TYPE_FDB = 0X4, 8968 MLX5_FLOW_TABLE_TYPE_SNIFFER_RX = 0X5, 8969 MLX5_FLOW_TABLE_TYPE_SNIFFER_TX = 0X6, 8970 }; 8971 8972 struct mlx5_ifc_create_flow_table_out_bits { 8973 u8 status[0x8]; 8974 u8 icm_address_63_40[0x18]; 8975 8976 u8 syndrome[0x20]; 8977 8978 u8 icm_address_39_32[0x8]; 8979 u8 table_id[0x18]; 8980 8981 u8 icm_address_31_0[0x20]; 8982 }; 8983 8984 struct mlx5_ifc_create_flow_table_in_bits { 8985 u8 opcode[0x10]; 8986 u8 uid[0x10]; 8987 8988 u8 reserved_at_20[0x10]; 8989 u8 op_mod[0x10]; 8990 8991 u8 other_vport[0x1]; 8992 u8 reserved_at_41[0xf]; 8993 u8 vport_number[0x10]; 8994 8995 u8 reserved_at_60[0x20]; 8996 8997 u8 table_type[0x8]; 8998 u8 reserved_at_88[0x18]; 8999 9000 u8 reserved_at_a0[0x20]; 9001 9002 struct mlx5_ifc_flow_table_context_bits flow_table_context; 9003 }; 9004 9005 struct mlx5_ifc_create_flow_group_out_bits { 9006 u8 status[0x8]; 9007 u8 reserved_at_8[0x18]; 9008 9009 u8 syndrome[0x20]; 9010 9011 u8 reserved_at_40[0x8]; 9012 u8 group_id[0x18]; 9013 9014 u8 reserved_at_60[0x20]; 9015 }; 9016 9017 enum { 9018 MLX5_CREATE_FLOW_GROUP_IN_GROUP_TYPE_TCAM_SUBTABLE = 0x0, 9019 MLX5_CREATE_FLOW_GROUP_IN_GROUP_TYPE_HASH_SPLIT = 0x1, 9020 }; 9021 9022 enum { 9023 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 9024 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 9025 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 9026 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3, 9027 }; 9028 9029 struct mlx5_ifc_create_flow_group_in_bits { 9030 u8 opcode[0x10]; 9031 u8 reserved_at_10[0x10]; 9032 9033 u8 reserved_at_20[0x10]; 9034 u8 op_mod[0x10]; 9035 9036 u8 other_vport[0x1]; 9037 u8 reserved_at_41[0xf]; 9038 u8 vport_number[0x10]; 9039 9040 u8 reserved_at_60[0x20]; 9041 9042 u8 table_type[0x8]; 9043 u8 reserved_at_88[0x4]; 9044 u8 group_type[0x4]; 9045 u8 reserved_at_90[0x10]; 9046 9047 u8 reserved_at_a0[0x8]; 9048 u8 table_id[0x18]; 9049 9050 u8 source_eswitch_owner_vhca_id_valid[0x1]; 9051 9052 u8 reserved_at_c1[0x1f]; 9053 9054 u8 start_flow_index[0x20]; 9055 9056 u8 reserved_at_100[0x20]; 9057 9058 u8 end_flow_index[0x20]; 9059 9060 u8 reserved_at_140[0x10]; 9061 u8 match_definer_id[0x10]; 9062 9063 u8 reserved_at_160[0x80]; 9064 9065 u8 reserved_at_1e0[0x18]; 9066 u8 match_criteria_enable[0x8]; 9067 9068 struct mlx5_ifc_fte_match_param_bits match_criteria; 9069 9070 u8 reserved_at_1200[0xe00]; 9071 }; 9072 9073 struct mlx5_ifc_create_eq_out_bits { 9074 u8 status[0x8]; 9075 u8 reserved_at_8[0x18]; 9076 9077 u8 syndrome[0x20]; 9078 9079 u8 reserved_at_40[0x18]; 9080 u8 eq_number[0x8]; 9081 9082 u8 reserved_at_60[0x20]; 9083 }; 9084 9085 struct mlx5_ifc_create_eq_in_bits { 9086 u8 opcode[0x10]; 9087 u8 uid[0x10]; 9088 9089 u8 reserved_at_20[0x10]; 9090 u8 op_mod[0x10]; 9091 9092 u8 reserved_at_40[0x40]; 9093 9094 struct mlx5_ifc_eqc_bits eq_context_entry; 9095 9096 u8 reserved_at_280[0x40]; 9097 9098 u8 event_bitmask[4][0x40]; 9099 9100 u8 reserved_at_3c0[0x4c0]; 9101 9102 u8 pas[][0x40]; 9103 }; 9104 9105 struct mlx5_ifc_create_dct_out_bits { 9106 u8 status[0x8]; 9107 u8 reserved_at_8[0x18]; 9108 9109 u8 syndrome[0x20]; 9110 9111 u8 reserved_at_40[0x8]; 9112 u8 dctn[0x18]; 9113 9114 u8 ece[0x20]; 9115 }; 9116 9117 struct mlx5_ifc_create_dct_in_bits { 9118 u8 opcode[0x10]; 9119 u8 uid[0x10]; 9120 9121 u8 reserved_at_20[0x10]; 9122 u8 op_mod[0x10]; 9123 9124 u8 reserved_at_40[0x40]; 9125 9126 struct mlx5_ifc_dctc_bits dct_context_entry; 9127 9128 u8 reserved_at_280[0x180]; 9129 }; 9130 9131 struct mlx5_ifc_create_cq_out_bits { 9132 u8 status[0x8]; 9133 u8 reserved_at_8[0x18]; 9134 9135 u8 syndrome[0x20]; 9136 9137 u8 reserved_at_40[0x8]; 9138 u8 cqn[0x18]; 9139 9140 u8 reserved_at_60[0x20]; 9141 }; 9142 9143 struct mlx5_ifc_create_cq_in_bits { 9144 u8 opcode[0x10]; 9145 u8 uid[0x10]; 9146 9147 u8 reserved_at_20[0x10]; 9148 u8 op_mod[0x10]; 9149 9150 u8 reserved_at_40[0x40]; 9151 9152 struct mlx5_ifc_cqc_bits cq_context; 9153 9154 u8 reserved_at_280[0x60]; 9155 9156 u8 cq_umem_valid[0x1]; 9157 u8 reserved_at_2e1[0x59f]; 9158 9159 u8 pas[][0x40]; 9160 }; 9161 9162 struct mlx5_ifc_config_int_moderation_out_bits { 9163 u8 status[0x8]; 9164 u8 reserved_at_8[0x18]; 9165 9166 u8 syndrome[0x20]; 9167 9168 u8 reserved_at_40[0x4]; 9169 u8 min_delay[0xc]; 9170 u8 int_vector[0x10]; 9171 9172 u8 reserved_at_60[0x20]; 9173 }; 9174 9175 enum { 9176 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0, 9177 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1, 9178 }; 9179 9180 struct mlx5_ifc_config_int_moderation_in_bits { 9181 u8 opcode[0x10]; 9182 u8 reserved_at_10[0x10]; 9183 9184 u8 reserved_at_20[0x10]; 9185 u8 op_mod[0x10]; 9186 9187 u8 reserved_at_40[0x4]; 9188 u8 min_delay[0xc]; 9189 u8 int_vector[0x10]; 9190 9191 u8 reserved_at_60[0x20]; 9192 }; 9193 9194 struct mlx5_ifc_attach_to_mcg_out_bits { 9195 u8 status[0x8]; 9196 u8 reserved_at_8[0x18]; 9197 9198 u8 syndrome[0x20]; 9199 9200 u8 reserved_at_40[0x40]; 9201 }; 9202 9203 struct mlx5_ifc_attach_to_mcg_in_bits { 9204 u8 opcode[0x10]; 9205 u8 uid[0x10]; 9206 9207 u8 reserved_at_20[0x10]; 9208 u8 op_mod[0x10]; 9209 9210 u8 reserved_at_40[0x8]; 9211 u8 qpn[0x18]; 9212 9213 u8 reserved_at_60[0x20]; 9214 9215 u8 multicast_gid[16][0x8]; 9216 }; 9217 9218 struct mlx5_ifc_arm_xrq_out_bits { 9219 u8 status[0x8]; 9220 u8 reserved_at_8[0x18]; 9221 9222 u8 syndrome[0x20]; 9223 9224 u8 reserved_at_40[0x40]; 9225 }; 9226 9227 struct mlx5_ifc_arm_xrq_in_bits { 9228 u8 opcode[0x10]; 9229 u8 reserved_at_10[0x10]; 9230 9231 u8 reserved_at_20[0x10]; 9232 u8 op_mod[0x10]; 9233 9234 u8 reserved_at_40[0x8]; 9235 u8 xrqn[0x18]; 9236 9237 u8 reserved_at_60[0x10]; 9238 u8 lwm[0x10]; 9239 }; 9240 9241 struct mlx5_ifc_arm_xrc_srq_out_bits { 9242 u8 status[0x8]; 9243 u8 reserved_at_8[0x18]; 9244 9245 u8 syndrome[0x20]; 9246 9247 u8 reserved_at_40[0x40]; 9248 }; 9249 9250 enum { 9251 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1, 9252 }; 9253 9254 struct mlx5_ifc_arm_xrc_srq_in_bits { 9255 u8 opcode[0x10]; 9256 u8 uid[0x10]; 9257 9258 u8 reserved_at_20[0x10]; 9259 u8 op_mod[0x10]; 9260 9261 u8 reserved_at_40[0x8]; 9262 u8 xrc_srqn[0x18]; 9263 9264 u8 reserved_at_60[0x10]; 9265 u8 lwm[0x10]; 9266 }; 9267 9268 struct mlx5_ifc_arm_rq_out_bits { 9269 u8 status[0x8]; 9270 u8 reserved_at_8[0x18]; 9271 9272 u8 syndrome[0x20]; 9273 9274 u8 reserved_at_40[0x40]; 9275 }; 9276 9277 enum { 9278 MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1, 9279 MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2, 9280 }; 9281 9282 struct mlx5_ifc_arm_rq_in_bits { 9283 u8 opcode[0x10]; 9284 u8 uid[0x10]; 9285 9286 u8 reserved_at_20[0x10]; 9287 u8 op_mod[0x10]; 9288 9289 u8 reserved_at_40[0x8]; 9290 u8 srq_number[0x18]; 9291 9292 u8 reserved_at_60[0x10]; 9293 u8 lwm[0x10]; 9294 }; 9295 9296 struct mlx5_ifc_arm_dct_out_bits { 9297 u8 status[0x8]; 9298 u8 reserved_at_8[0x18]; 9299 9300 u8 syndrome[0x20]; 9301 9302 u8 reserved_at_40[0x40]; 9303 }; 9304 9305 struct mlx5_ifc_arm_dct_in_bits { 9306 u8 opcode[0x10]; 9307 u8 reserved_at_10[0x10]; 9308 9309 u8 reserved_at_20[0x10]; 9310 u8 op_mod[0x10]; 9311 9312 u8 reserved_at_40[0x8]; 9313 u8 dct_number[0x18]; 9314 9315 u8 reserved_at_60[0x20]; 9316 }; 9317 9318 struct mlx5_ifc_alloc_xrcd_out_bits { 9319 u8 status[0x8]; 9320 u8 reserved_at_8[0x18]; 9321 9322 u8 syndrome[0x20]; 9323 9324 u8 reserved_at_40[0x8]; 9325 u8 xrcd[0x18]; 9326 9327 u8 reserved_at_60[0x20]; 9328 }; 9329 9330 struct mlx5_ifc_alloc_xrcd_in_bits { 9331 u8 opcode[0x10]; 9332 u8 uid[0x10]; 9333 9334 u8 reserved_at_20[0x10]; 9335 u8 op_mod[0x10]; 9336 9337 u8 reserved_at_40[0x40]; 9338 }; 9339 9340 struct mlx5_ifc_alloc_uar_out_bits { 9341 u8 status[0x8]; 9342 u8 reserved_at_8[0x18]; 9343 9344 u8 syndrome[0x20]; 9345 9346 u8 reserved_at_40[0x8]; 9347 u8 uar[0x18]; 9348 9349 u8 reserved_at_60[0x20]; 9350 }; 9351 9352 struct mlx5_ifc_alloc_uar_in_bits { 9353 u8 opcode[0x10]; 9354 u8 uid[0x10]; 9355 9356 u8 reserved_at_20[0x10]; 9357 u8 op_mod[0x10]; 9358 9359 u8 reserved_at_40[0x40]; 9360 }; 9361 9362 struct mlx5_ifc_alloc_transport_domain_out_bits { 9363 u8 status[0x8]; 9364 u8 reserved_at_8[0x18]; 9365 9366 u8 syndrome[0x20]; 9367 9368 u8 reserved_at_40[0x8]; 9369 u8 transport_domain[0x18]; 9370 9371 u8 reserved_at_60[0x20]; 9372 }; 9373 9374 struct mlx5_ifc_alloc_transport_domain_in_bits { 9375 u8 opcode[0x10]; 9376 u8 uid[0x10]; 9377 9378 u8 reserved_at_20[0x10]; 9379 u8 op_mod[0x10]; 9380 9381 u8 reserved_at_40[0x40]; 9382 }; 9383 9384 struct mlx5_ifc_alloc_q_counter_out_bits { 9385 u8 status[0x8]; 9386 u8 reserved_at_8[0x18]; 9387 9388 u8 syndrome[0x20]; 9389 9390 u8 reserved_at_40[0x18]; 9391 u8 counter_set_id[0x8]; 9392 9393 u8 reserved_at_60[0x20]; 9394 }; 9395 9396 struct mlx5_ifc_alloc_q_counter_in_bits { 9397 u8 opcode[0x10]; 9398 u8 uid[0x10]; 9399 9400 u8 reserved_at_20[0x10]; 9401 u8 op_mod[0x10]; 9402 9403 u8 reserved_at_40[0x40]; 9404 }; 9405 9406 struct mlx5_ifc_alloc_pd_out_bits { 9407 u8 status[0x8]; 9408 u8 reserved_at_8[0x18]; 9409 9410 u8 syndrome[0x20]; 9411 9412 u8 reserved_at_40[0x8]; 9413 u8 pd[0x18]; 9414 9415 u8 reserved_at_60[0x20]; 9416 }; 9417 9418 struct mlx5_ifc_alloc_pd_in_bits { 9419 u8 opcode[0x10]; 9420 u8 uid[0x10]; 9421 9422 u8 reserved_at_20[0x10]; 9423 u8 op_mod[0x10]; 9424 9425 u8 reserved_at_40[0x40]; 9426 }; 9427 9428 struct mlx5_ifc_alloc_flow_counter_out_bits { 9429 u8 status[0x8]; 9430 u8 reserved_at_8[0x18]; 9431 9432 u8 syndrome[0x20]; 9433 9434 u8 flow_counter_id[0x20]; 9435 9436 u8 reserved_at_60[0x20]; 9437 }; 9438 9439 struct mlx5_ifc_alloc_flow_counter_in_bits { 9440 u8 opcode[0x10]; 9441 u8 reserved_at_10[0x10]; 9442 9443 u8 reserved_at_20[0x10]; 9444 u8 op_mod[0x10]; 9445 9446 u8 reserved_at_40[0x33]; 9447 u8 flow_counter_bulk_log_size[0x5]; 9448 u8 flow_counter_bulk[0x8]; 9449 }; 9450 9451 struct mlx5_ifc_add_vxlan_udp_dport_out_bits { 9452 u8 status[0x8]; 9453 u8 reserved_at_8[0x18]; 9454 9455 u8 syndrome[0x20]; 9456 9457 u8 reserved_at_40[0x40]; 9458 }; 9459 9460 struct mlx5_ifc_add_vxlan_udp_dport_in_bits { 9461 u8 opcode[0x10]; 9462 u8 reserved_at_10[0x10]; 9463 9464 u8 reserved_at_20[0x10]; 9465 u8 op_mod[0x10]; 9466 9467 u8 reserved_at_40[0x20]; 9468 9469 u8 reserved_at_60[0x10]; 9470 u8 vxlan_udp_port[0x10]; 9471 }; 9472 9473 struct mlx5_ifc_set_pp_rate_limit_out_bits { 9474 u8 status[0x8]; 9475 u8 reserved_at_8[0x18]; 9476 9477 u8 syndrome[0x20]; 9478 9479 u8 reserved_at_40[0x40]; 9480 }; 9481 9482 struct mlx5_ifc_set_pp_rate_limit_context_bits { 9483 u8 rate_limit[0x20]; 9484 9485 u8 burst_upper_bound[0x20]; 9486 9487 u8 reserved_at_40[0x10]; 9488 u8 typical_packet_size[0x10]; 9489 9490 u8 reserved_at_60[0x120]; 9491 }; 9492 9493 struct mlx5_ifc_set_pp_rate_limit_in_bits { 9494 u8 opcode[0x10]; 9495 u8 uid[0x10]; 9496 9497 u8 reserved_at_20[0x10]; 9498 u8 op_mod[0x10]; 9499 9500 u8 reserved_at_40[0x10]; 9501 u8 rate_limit_index[0x10]; 9502 9503 u8 reserved_at_60[0x20]; 9504 9505 struct mlx5_ifc_set_pp_rate_limit_context_bits ctx; 9506 }; 9507 9508 struct mlx5_ifc_access_register_out_bits { 9509 u8 status[0x8]; 9510 u8 reserved_at_8[0x18]; 9511 9512 u8 syndrome[0x20]; 9513 9514 u8 reserved_at_40[0x40]; 9515 9516 u8 register_data[][0x20]; 9517 }; 9518 9519 enum { 9520 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0, 9521 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1, 9522 }; 9523 9524 struct mlx5_ifc_access_register_in_bits { 9525 u8 opcode[0x10]; 9526 u8 reserved_at_10[0x10]; 9527 9528 u8 reserved_at_20[0x10]; 9529 u8 op_mod[0x10]; 9530 9531 u8 reserved_at_40[0x10]; 9532 u8 register_id[0x10]; 9533 9534 u8 argument[0x20]; 9535 9536 u8 register_data[][0x20]; 9537 }; 9538 9539 struct mlx5_ifc_sltp_reg_bits { 9540 u8 status[0x4]; 9541 u8 version[0x4]; 9542 u8 local_port[0x8]; 9543 u8 pnat[0x2]; 9544 u8 reserved_at_12[0x2]; 9545 u8 lane[0x4]; 9546 u8 reserved_at_18[0x8]; 9547 9548 u8 reserved_at_20[0x20]; 9549 9550 u8 reserved_at_40[0x7]; 9551 u8 polarity[0x1]; 9552 u8 ob_tap0[0x8]; 9553 u8 ob_tap1[0x8]; 9554 u8 ob_tap2[0x8]; 9555 9556 u8 reserved_at_60[0xc]; 9557 u8 ob_preemp_mode[0x4]; 9558 u8 ob_reg[0x8]; 9559 u8 ob_bias[0x8]; 9560 9561 u8 reserved_at_80[0x20]; 9562 }; 9563 9564 struct mlx5_ifc_slrg_reg_bits { 9565 u8 status[0x4]; 9566 u8 version[0x4]; 9567 u8 local_port[0x8]; 9568 u8 pnat[0x2]; 9569 u8 reserved_at_12[0x2]; 9570 u8 lane[0x4]; 9571 u8 reserved_at_18[0x8]; 9572 9573 u8 time_to_link_up[0x10]; 9574 u8 reserved_at_30[0xc]; 9575 u8 grade_lane_speed[0x4]; 9576 9577 u8 grade_version[0x8]; 9578 u8 grade[0x18]; 9579 9580 u8 reserved_at_60[0x4]; 9581 u8 height_grade_type[0x4]; 9582 u8 height_grade[0x18]; 9583 9584 u8 height_dz[0x10]; 9585 u8 height_dv[0x10]; 9586 9587 u8 reserved_at_a0[0x10]; 9588 u8 height_sigma[0x10]; 9589 9590 u8 reserved_at_c0[0x20]; 9591 9592 u8 reserved_at_e0[0x4]; 9593 u8 phase_grade_type[0x4]; 9594 u8 phase_grade[0x18]; 9595 9596 u8 reserved_at_100[0x8]; 9597 u8 phase_eo_pos[0x8]; 9598 u8 reserved_at_110[0x8]; 9599 u8 phase_eo_neg[0x8]; 9600 9601 u8 ffe_set_tested[0x10]; 9602 u8 test_errors_per_lane[0x10]; 9603 }; 9604 9605 struct mlx5_ifc_pvlc_reg_bits { 9606 u8 reserved_at_0[0x8]; 9607 u8 local_port[0x8]; 9608 u8 reserved_at_10[0x10]; 9609 9610 u8 reserved_at_20[0x1c]; 9611 u8 vl_hw_cap[0x4]; 9612 9613 u8 reserved_at_40[0x1c]; 9614 u8 vl_admin[0x4]; 9615 9616 u8 reserved_at_60[0x1c]; 9617 u8 vl_operational[0x4]; 9618 }; 9619 9620 struct mlx5_ifc_pude_reg_bits { 9621 u8 swid[0x8]; 9622 u8 local_port[0x8]; 9623 u8 reserved_at_10[0x4]; 9624 u8 admin_status[0x4]; 9625 u8 reserved_at_18[0x4]; 9626 u8 oper_status[0x4]; 9627 9628 u8 reserved_at_20[0x60]; 9629 }; 9630 9631 struct mlx5_ifc_ptys_reg_bits { 9632 u8 reserved_at_0[0x1]; 9633 u8 an_disable_admin[0x1]; 9634 u8 an_disable_cap[0x1]; 9635 u8 reserved_at_3[0x5]; 9636 u8 local_port[0x8]; 9637 u8 reserved_at_10[0xd]; 9638 u8 proto_mask[0x3]; 9639 9640 u8 an_status[0x4]; 9641 u8 reserved_at_24[0xc]; 9642 u8 data_rate_oper[0x10]; 9643 9644 u8 ext_eth_proto_capability[0x20]; 9645 9646 u8 eth_proto_capability[0x20]; 9647 9648 u8 ib_link_width_capability[0x10]; 9649 u8 ib_proto_capability[0x10]; 9650 9651 u8 ext_eth_proto_admin[0x20]; 9652 9653 u8 eth_proto_admin[0x20]; 9654 9655 u8 ib_link_width_admin[0x10]; 9656 u8 ib_proto_admin[0x10]; 9657 9658 u8 ext_eth_proto_oper[0x20]; 9659 9660 u8 eth_proto_oper[0x20]; 9661 9662 u8 ib_link_width_oper[0x10]; 9663 u8 ib_proto_oper[0x10]; 9664 9665 u8 reserved_at_160[0x1c]; 9666 u8 connector_type[0x4]; 9667 9668 u8 eth_proto_lp_advertise[0x20]; 9669 9670 u8 reserved_at_1a0[0x60]; 9671 }; 9672 9673 struct mlx5_ifc_mlcr_reg_bits { 9674 u8 reserved_at_0[0x8]; 9675 u8 local_port[0x8]; 9676 u8 reserved_at_10[0x20]; 9677 9678 u8 beacon_duration[0x10]; 9679 u8 reserved_at_40[0x10]; 9680 9681 u8 beacon_remain[0x10]; 9682 }; 9683 9684 struct mlx5_ifc_ptas_reg_bits { 9685 u8 reserved_at_0[0x20]; 9686 9687 u8 algorithm_options[0x10]; 9688 u8 reserved_at_30[0x4]; 9689 u8 repetitions_mode[0x4]; 9690 u8 num_of_repetitions[0x8]; 9691 9692 u8 grade_version[0x8]; 9693 u8 height_grade_type[0x4]; 9694 u8 phase_grade_type[0x4]; 9695 u8 height_grade_weight[0x8]; 9696 u8 phase_grade_weight[0x8]; 9697 9698 u8 gisim_measure_bits[0x10]; 9699 u8 adaptive_tap_measure_bits[0x10]; 9700 9701 u8 ber_bath_high_error_threshold[0x10]; 9702 u8 ber_bath_mid_error_threshold[0x10]; 9703 9704 u8 ber_bath_low_error_threshold[0x10]; 9705 u8 one_ratio_high_threshold[0x10]; 9706 9707 u8 one_ratio_high_mid_threshold[0x10]; 9708 u8 one_ratio_low_mid_threshold[0x10]; 9709 9710 u8 one_ratio_low_threshold[0x10]; 9711 u8 ndeo_error_threshold[0x10]; 9712 9713 u8 mixer_offset_step_size[0x10]; 9714 u8 reserved_at_110[0x8]; 9715 u8 mix90_phase_for_voltage_bath[0x8]; 9716 9717 u8 mixer_offset_start[0x10]; 9718 u8 mixer_offset_end[0x10]; 9719 9720 u8 reserved_at_140[0x15]; 9721 u8 ber_test_time[0xb]; 9722 }; 9723 9724 struct mlx5_ifc_pspa_reg_bits { 9725 u8 swid[0x8]; 9726 u8 local_port[0x8]; 9727 u8 sub_port[0x8]; 9728 u8 reserved_at_18[0x8]; 9729 9730 u8 reserved_at_20[0x20]; 9731 }; 9732 9733 struct mlx5_ifc_pqdr_reg_bits { 9734 u8 reserved_at_0[0x8]; 9735 u8 local_port[0x8]; 9736 u8 reserved_at_10[0x5]; 9737 u8 prio[0x3]; 9738 u8 reserved_at_18[0x6]; 9739 u8 mode[0x2]; 9740 9741 u8 reserved_at_20[0x20]; 9742 9743 u8 reserved_at_40[0x10]; 9744 u8 min_threshold[0x10]; 9745 9746 u8 reserved_at_60[0x10]; 9747 u8 max_threshold[0x10]; 9748 9749 u8 reserved_at_80[0x10]; 9750 u8 mark_probability_denominator[0x10]; 9751 9752 u8 reserved_at_a0[0x60]; 9753 }; 9754 9755 struct mlx5_ifc_ppsc_reg_bits { 9756 u8 reserved_at_0[0x8]; 9757 u8 local_port[0x8]; 9758 u8 reserved_at_10[0x10]; 9759 9760 u8 reserved_at_20[0x60]; 9761 9762 u8 reserved_at_80[0x1c]; 9763 u8 wrps_admin[0x4]; 9764 9765 u8 reserved_at_a0[0x1c]; 9766 u8 wrps_status[0x4]; 9767 9768 u8 reserved_at_c0[0x8]; 9769 u8 up_threshold[0x8]; 9770 u8 reserved_at_d0[0x8]; 9771 u8 down_threshold[0x8]; 9772 9773 u8 reserved_at_e0[0x20]; 9774 9775 u8 reserved_at_100[0x1c]; 9776 u8 srps_admin[0x4]; 9777 9778 u8 reserved_at_120[0x1c]; 9779 u8 srps_status[0x4]; 9780 9781 u8 reserved_at_140[0x40]; 9782 }; 9783 9784 struct mlx5_ifc_pplr_reg_bits { 9785 u8 reserved_at_0[0x8]; 9786 u8 local_port[0x8]; 9787 u8 reserved_at_10[0x10]; 9788 9789 u8 reserved_at_20[0x8]; 9790 u8 lb_cap[0x8]; 9791 u8 reserved_at_30[0x8]; 9792 u8 lb_en[0x8]; 9793 }; 9794 9795 struct mlx5_ifc_pplm_reg_bits { 9796 u8 reserved_at_0[0x8]; 9797 u8 local_port[0x8]; 9798 u8 reserved_at_10[0x10]; 9799 9800 u8 reserved_at_20[0x20]; 9801 9802 u8 port_profile_mode[0x8]; 9803 u8 static_port_profile[0x8]; 9804 u8 active_port_profile[0x8]; 9805 u8 reserved_at_58[0x8]; 9806 9807 u8 retransmission_active[0x8]; 9808 u8 fec_mode_active[0x18]; 9809 9810 u8 rs_fec_correction_bypass_cap[0x4]; 9811 u8 reserved_at_84[0x8]; 9812 u8 fec_override_cap_56g[0x4]; 9813 u8 fec_override_cap_100g[0x4]; 9814 u8 fec_override_cap_50g[0x4]; 9815 u8 fec_override_cap_25g[0x4]; 9816 u8 fec_override_cap_10g_40g[0x4]; 9817 9818 u8 rs_fec_correction_bypass_admin[0x4]; 9819 u8 reserved_at_a4[0x8]; 9820 u8 fec_override_admin_56g[0x4]; 9821 u8 fec_override_admin_100g[0x4]; 9822 u8 fec_override_admin_50g[0x4]; 9823 u8 fec_override_admin_25g[0x4]; 9824 u8 fec_override_admin_10g_40g[0x4]; 9825 9826 u8 fec_override_cap_400g_8x[0x10]; 9827 u8 fec_override_cap_200g_4x[0x10]; 9828 9829 u8 fec_override_cap_100g_2x[0x10]; 9830 u8 fec_override_cap_50g_1x[0x10]; 9831 9832 u8 fec_override_admin_400g_8x[0x10]; 9833 u8 fec_override_admin_200g_4x[0x10]; 9834 9835 u8 fec_override_admin_100g_2x[0x10]; 9836 u8 fec_override_admin_50g_1x[0x10]; 9837 9838 u8 fec_override_cap_800g_8x[0x10]; 9839 u8 fec_override_cap_400g_4x[0x10]; 9840 9841 u8 fec_override_cap_200g_2x[0x10]; 9842 u8 fec_override_cap_100g_1x[0x10]; 9843 9844 u8 reserved_at_180[0xa0]; 9845 9846 u8 fec_override_admin_800g_8x[0x10]; 9847 u8 fec_override_admin_400g_4x[0x10]; 9848 9849 u8 fec_override_admin_200g_2x[0x10]; 9850 u8 fec_override_admin_100g_1x[0x10]; 9851 9852 u8 reserved_at_260[0x20]; 9853 }; 9854 9855 struct mlx5_ifc_ppcnt_reg_bits { 9856 u8 swid[0x8]; 9857 u8 local_port[0x8]; 9858 u8 pnat[0x2]; 9859 u8 reserved_at_12[0x8]; 9860 u8 grp[0x6]; 9861 9862 u8 clr[0x1]; 9863 u8 reserved_at_21[0x1c]; 9864 u8 prio_tc[0x3]; 9865 9866 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set; 9867 }; 9868 9869 struct mlx5_ifc_mpein_reg_bits { 9870 u8 reserved_at_0[0x2]; 9871 u8 depth[0x6]; 9872 u8 pcie_index[0x8]; 9873 u8 node[0x8]; 9874 u8 reserved_at_18[0x8]; 9875 9876 u8 capability_mask[0x20]; 9877 9878 u8 reserved_at_40[0x8]; 9879 u8 link_width_enabled[0x8]; 9880 u8 link_speed_enabled[0x10]; 9881 9882 u8 lane0_physical_position[0x8]; 9883 u8 link_width_active[0x8]; 9884 u8 link_speed_active[0x10]; 9885 9886 u8 num_of_pfs[0x10]; 9887 u8 num_of_vfs[0x10]; 9888 9889 u8 bdf0[0x10]; 9890 u8 reserved_at_b0[0x10]; 9891 9892 u8 max_read_request_size[0x4]; 9893 u8 max_payload_size[0x4]; 9894 u8 reserved_at_c8[0x5]; 9895 u8 pwr_status[0x3]; 9896 u8 port_type[0x4]; 9897 u8 reserved_at_d4[0xb]; 9898 u8 lane_reversal[0x1]; 9899 9900 u8 reserved_at_e0[0x14]; 9901 u8 pci_power[0xc]; 9902 9903 u8 reserved_at_100[0x20]; 9904 9905 u8 device_status[0x10]; 9906 u8 port_state[0x8]; 9907 u8 reserved_at_138[0x8]; 9908 9909 u8 reserved_at_140[0x10]; 9910 u8 receiver_detect_result[0x10]; 9911 9912 u8 reserved_at_160[0x20]; 9913 }; 9914 9915 struct mlx5_ifc_mpcnt_reg_bits { 9916 u8 reserved_at_0[0x8]; 9917 u8 pcie_index[0x8]; 9918 u8 reserved_at_10[0xa]; 9919 u8 grp[0x6]; 9920 9921 u8 clr[0x1]; 9922 u8 reserved_at_21[0x1f]; 9923 9924 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set; 9925 }; 9926 9927 struct mlx5_ifc_ppad_reg_bits { 9928 u8 reserved_at_0[0x3]; 9929 u8 single_mac[0x1]; 9930 u8 reserved_at_4[0x4]; 9931 u8 local_port[0x8]; 9932 u8 mac_47_32[0x10]; 9933 9934 u8 mac_31_0[0x20]; 9935 9936 u8 reserved_at_40[0x40]; 9937 }; 9938 9939 struct mlx5_ifc_pmtu_reg_bits { 9940 u8 reserved_at_0[0x8]; 9941 u8 local_port[0x8]; 9942 u8 reserved_at_10[0x10]; 9943 9944 u8 max_mtu[0x10]; 9945 u8 reserved_at_30[0x10]; 9946 9947 u8 admin_mtu[0x10]; 9948 u8 reserved_at_50[0x10]; 9949 9950 u8 oper_mtu[0x10]; 9951 u8 reserved_at_70[0x10]; 9952 }; 9953 9954 struct mlx5_ifc_pmpr_reg_bits { 9955 u8 reserved_at_0[0x8]; 9956 u8 module[0x8]; 9957 u8 reserved_at_10[0x10]; 9958 9959 u8 reserved_at_20[0x18]; 9960 u8 attenuation_5g[0x8]; 9961 9962 u8 reserved_at_40[0x18]; 9963 u8 attenuation_7g[0x8]; 9964 9965 u8 reserved_at_60[0x18]; 9966 u8 attenuation_12g[0x8]; 9967 }; 9968 9969 struct mlx5_ifc_pmpe_reg_bits { 9970 u8 reserved_at_0[0x8]; 9971 u8 module[0x8]; 9972 u8 reserved_at_10[0xc]; 9973 u8 module_status[0x4]; 9974 9975 u8 reserved_at_20[0x60]; 9976 }; 9977 9978 struct mlx5_ifc_pmpc_reg_bits { 9979 u8 module_state_updated[32][0x8]; 9980 }; 9981 9982 struct mlx5_ifc_pmlpn_reg_bits { 9983 u8 reserved_at_0[0x4]; 9984 u8 mlpn_status[0x4]; 9985 u8 local_port[0x8]; 9986 u8 reserved_at_10[0x10]; 9987 9988 u8 e[0x1]; 9989 u8 reserved_at_21[0x1f]; 9990 }; 9991 9992 struct mlx5_ifc_pmlp_reg_bits { 9993 u8 rxtx[0x1]; 9994 u8 reserved_at_1[0x7]; 9995 u8 local_port[0x8]; 9996 u8 reserved_at_10[0x8]; 9997 u8 width[0x8]; 9998 9999 u8 lane0_module_mapping[0x20]; 10000 10001 u8 lane1_module_mapping[0x20]; 10002 10003 u8 lane2_module_mapping[0x20]; 10004 10005 u8 lane3_module_mapping[0x20]; 10006 10007 u8 reserved_at_a0[0x160]; 10008 }; 10009 10010 struct mlx5_ifc_pmaos_reg_bits { 10011 u8 reserved_at_0[0x8]; 10012 u8 module[0x8]; 10013 u8 reserved_at_10[0x4]; 10014 u8 admin_status[0x4]; 10015 u8 reserved_at_18[0x4]; 10016 u8 oper_status[0x4]; 10017 10018 u8 ase[0x1]; 10019 u8 ee[0x1]; 10020 u8 reserved_at_22[0x1c]; 10021 u8 e[0x2]; 10022 10023 u8 reserved_at_40[0x40]; 10024 }; 10025 10026 struct mlx5_ifc_plpc_reg_bits { 10027 u8 reserved_at_0[0x4]; 10028 u8 profile_id[0xc]; 10029 u8 reserved_at_10[0x4]; 10030 u8 proto_mask[0x4]; 10031 u8 reserved_at_18[0x8]; 10032 10033 u8 reserved_at_20[0x10]; 10034 u8 lane_speed[0x10]; 10035 10036 u8 reserved_at_40[0x17]; 10037 u8 lpbf[0x1]; 10038 u8 fec_mode_policy[0x8]; 10039 10040 u8 retransmission_capability[0x8]; 10041 u8 fec_mode_capability[0x18]; 10042 10043 u8 retransmission_support_admin[0x8]; 10044 u8 fec_mode_support_admin[0x18]; 10045 10046 u8 retransmission_request_admin[0x8]; 10047 u8 fec_mode_request_admin[0x18]; 10048 10049 u8 reserved_at_c0[0x80]; 10050 }; 10051 10052 struct mlx5_ifc_plib_reg_bits { 10053 u8 reserved_at_0[0x8]; 10054 u8 local_port[0x8]; 10055 u8 reserved_at_10[0x8]; 10056 u8 ib_port[0x8]; 10057 10058 u8 reserved_at_20[0x60]; 10059 }; 10060 10061 struct mlx5_ifc_plbf_reg_bits { 10062 u8 reserved_at_0[0x8]; 10063 u8 local_port[0x8]; 10064 u8 reserved_at_10[0xd]; 10065 u8 lbf_mode[0x3]; 10066 10067 u8 reserved_at_20[0x20]; 10068 }; 10069 10070 struct mlx5_ifc_pipg_reg_bits { 10071 u8 reserved_at_0[0x8]; 10072 u8 local_port[0x8]; 10073 u8 reserved_at_10[0x10]; 10074 10075 u8 dic[0x1]; 10076 u8 reserved_at_21[0x19]; 10077 u8 ipg[0x4]; 10078 u8 reserved_at_3e[0x2]; 10079 }; 10080 10081 struct mlx5_ifc_pifr_reg_bits { 10082 u8 reserved_at_0[0x8]; 10083 u8 local_port[0x8]; 10084 u8 reserved_at_10[0x10]; 10085 10086 u8 reserved_at_20[0xe0]; 10087 10088 u8 port_filter[8][0x20]; 10089 10090 u8 port_filter_update_en[8][0x20]; 10091 }; 10092 10093 struct mlx5_ifc_pfcc_reg_bits { 10094 u8 reserved_at_0[0x8]; 10095 u8 local_port[0x8]; 10096 u8 reserved_at_10[0xb]; 10097 u8 ppan_mask_n[0x1]; 10098 u8 minor_stall_mask[0x1]; 10099 u8 critical_stall_mask[0x1]; 10100 u8 reserved_at_1e[0x2]; 10101 10102 u8 ppan[0x4]; 10103 u8 reserved_at_24[0x4]; 10104 u8 prio_mask_tx[0x8]; 10105 u8 reserved_at_30[0x8]; 10106 u8 prio_mask_rx[0x8]; 10107 10108 u8 pptx[0x1]; 10109 u8 aptx[0x1]; 10110 u8 pptx_mask_n[0x1]; 10111 u8 reserved_at_43[0x5]; 10112 u8 pfctx[0x8]; 10113 u8 reserved_at_50[0x10]; 10114 10115 u8 pprx[0x1]; 10116 u8 aprx[0x1]; 10117 u8 pprx_mask_n[0x1]; 10118 u8 reserved_at_63[0x5]; 10119 u8 pfcrx[0x8]; 10120 u8 reserved_at_70[0x10]; 10121 10122 u8 device_stall_minor_watermark[0x10]; 10123 u8 device_stall_critical_watermark[0x10]; 10124 10125 u8 reserved_at_a0[0x60]; 10126 }; 10127 10128 struct mlx5_ifc_pelc_reg_bits { 10129 u8 op[0x4]; 10130 u8 reserved_at_4[0x4]; 10131 u8 local_port[0x8]; 10132 u8 reserved_at_10[0x10]; 10133 10134 u8 op_admin[0x8]; 10135 u8 op_capability[0x8]; 10136 u8 op_request[0x8]; 10137 u8 op_active[0x8]; 10138 10139 u8 admin[0x40]; 10140 10141 u8 capability[0x40]; 10142 10143 u8 request[0x40]; 10144 10145 u8 active[0x40]; 10146 10147 u8 reserved_at_140[0x80]; 10148 }; 10149 10150 struct mlx5_ifc_peir_reg_bits { 10151 u8 reserved_at_0[0x8]; 10152 u8 local_port[0x8]; 10153 u8 reserved_at_10[0x10]; 10154 10155 u8 reserved_at_20[0xc]; 10156 u8 error_count[0x4]; 10157 u8 reserved_at_30[0x10]; 10158 10159 u8 reserved_at_40[0xc]; 10160 u8 lane[0x4]; 10161 u8 reserved_at_50[0x8]; 10162 u8 error_type[0x8]; 10163 }; 10164 10165 struct mlx5_ifc_mpegc_reg_bits { 10166 u8 reserved_at_0[0x30]; 10167 u8 field_select[0x10]; 10168 10169 u8 tx_overflow_sense[0x1]; 10170 u8 mark_cqe[0x1]; 10171 u8 mark_cnp[0x1]; 10172 u8 reserved_at_43[0x1b]; 10173 u8 tx_lossy_overflow_oper[0x2]; 10174 10175 u8 reserved_at_60[0x100]; 10176 }; 10177 10178 struct mlx5_ifc_mpir_reg_bits { 10179 u8 sdm[0x1]; 10180 u8 reserved_at_1[0x1b]; 10181 u8 host_buses[0x4]; 10182 10183 u8 reserved_at_20[0x20]; 10184 10185 u8 local_port[0x8]; 10186 u8 reserved_at_28[0x18]; 10187 10188 u8 reserved_at_60[0x20]; 10189 }; 10190 10191 enum { 10192 MLX5_MTUTC_FREQ_ADJ_UNITS_PPB = 0x0, 10193 MLX5_MTUTC_FREQ_ADJ_UNITS_SCALED_PPM = 0x1, 10194 }; 10195 10196 enum { 10197 MLX5_MTUTC_OPERATION_SET_TIME_IMMEDIATE = 0x1, 10198 MLX5_MTUTC_OPERATION_ADJUST_TIME = 0x2, 10199 MLX5_MTUTC_OPERATION_ADJUST_FREQ_UTC = 0x3, 10200 }; 10201 10202 struct mlx5_ifc_mtutc_reg_bits { 10203 u8 reserved_at_0[0x5]; 10204 u8 freq_adj_units[0x3]; 10205 u8 reserved_at_8[0x3]; 10206 u8 log_max_freq_adjustment[0x5]; 10207 10208 u8 reserved_at_10[0xc]; 10209 u8 operation[0x4]; 10210 10211 u8 freq_adjustment[0x20]; 10212 10213 u8 reserved_at_40[0x40]; 10214 10215 u8 utc_sec[0x20]; 10216 10217 u8 reserved_at_a0[0x2]; 10218 u8 utc_nsec[0x1e]; 10219 10220 u8 time_adjustment[0x20]; 10221 }; 10222 10223 struct mlx5_ifc_pcam_enhanced_features_bits { 10224 u8 reserved_at_0[0x48]; 10225 u8 fec_100G_per_lane_in_pplm[0x1]; 10226 u8 reserved_at_49[0x1f]; 10227 u8 fec_50G_per_lane_in_pplm[0x1]; 10228 u8 reserved_at_69[0x4]; 10229 u8 rx_icrc_encapsulated_counter[0x1]; 10230 u8 reserved_at_6e[0x4]; 10231 u8 ptys_extended_ethernet[0x1]; 10232 u8 reserved_at_73[0x3]; 10233 u8 pfcc_mask[0x1]; 10234 u8 reserved_at_77[0x3]; 10235 u8 per_lane_error_counters[0x1]; 10236 u8 rx_buffer_fullness_counters[0x1]; 10237 u8 ptys_connector_type[0x1]; 10238 u8 reserved_at_7d[0x1]; 10239 u8 ppcnt_discard_group[0x1]; 10240 u8 ppcnt_statistical_group[0x1]; 10241 }; 10242 10243 struct mlx5_ifc_pcam_regs_5000_to_507f_bits { 10244 u8 port_access_reg_cap_mask_127_to_96[0x20]; 10245 u8 port_access_reg_cap_mask_95_to_64[0x20]; 10246 10247 u8 port_access_reg_cap_mask_63_to_36[0x1c]; 10248 u8 pplm[0x1]; 10249 u8 port_access_reg_cap_mask_34_to_32[0x3]; 10250 10251 u8 port_access_reg_cap_mask_31_to_13[0x13]; 10252 u8 pbmc[0x1]; 10253 u8 pptb[0x1]; 10254 u8 port_access_reg_cap_mask_10_to_09[0x2]; 10255 u8 ppcnt[0x1]; 10256 u8 port_access_reg_cap_mask_07_to_00[0x8]; 10257 }; 10258 10259 struct mlx5_ifc_pcam_reg_bits { 10260 u8 reserved_at_0[0x8]; 10261 u8 feature_group[0x8]; 10262 u8 reserved_at_10[0x8]; 10263 u8 access_reg_group[0x8]; 10264 10265 u8 reserved_at_20[0x20]; 10266 10267 union { 10268 struct mlx5_ifc_pcam_regs_5000_to_507f_bits regs_5000_to_507f; 10269 u8 reserved_at_0[0x80]; 10270 } port_access_reg_cap_mask; 10271 10272 u8 reserved_at_c0[0x80]; 10273 10274 union { 10275 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features; 10276 u8 reserved_at_0[0x80]; 10277 } feature_cap_mask; 10278 10279 u8 reserved_at_1c0[0xc0]; 10280 }; 10281 10282 struct mlx5_ifc_mcam_enhanced_features_bits { 10283 u8 reserved_at_0[0x50]; 10284 u8 mtutc_freq_adj_units[0x1]; 10285 u8 mtutc_time_adjustment_extended_range[0x1]; 10286 u8 reserved_at_52[0xb]; 10287 u8 mcia_32dwords[0x1]; 10288 u8 out_pulse_duration_ns[0x1]; 10289 u8 npps_period[0x1]; 10290 u8 reserved_at_60[0xa]; 10291 u8 reset_state[0x1]; 10292 u8 ptpcyc2realtime_modify[0x1]; 10293 u8 reserved_at_6c[0x2]; 10294 u8 pci_status_and_power[0x1]; 10295 u8 reserved_at_6f[0x5]; 10296 u8 mark_tx_action_cnp[0x1]; 10297 u8 mark_tx_action_cqe[0x1]; 10298 u8 dynamic_tx_overflow[0x1]; 10299 u8 reserved_at_77[0x4]; 10300 u8 pcie_outbound_stalled[0x1]; 10301 u8 tx_overflow_buffer_pkt[0x1]; 10302 u8 mtpps_enh_out_per_adj[0x1]; 10303 u8 mtpps_fs[0x1]; 10304 u8 pcie_performance_group[0x1]; 10305 }; 10306 10307 struct mlx5_ifc_mcam_access_reg_bits { 10308 u8 reserved_at_0[0x1c]; 10309 u8 mcda[0x1]; 10310 u8 mcc[0x1]; 10311 u8 mcqi[0x1]; 10312 u8 mcqs[0x1]; 10313 10314 u8 regs_95_to_90[0x6]; 10315 u8 mpir[0x1]; 10316 u8 regs_88_to_87[0x2]; 10317 u8 mpegc[0x1]; 10318 u8 mtutc[0x1]; 10319 u8 regs_84_to_68[0x11]; 10320 u8 tracer_registers[0x4]; 10321 10322 u8 regs_63_to_46[0x12]; 10323 u8 mrtc[0x1]; 10324 u8 regs_44_to_41[0x4]; 10325 u8 mfrl[0x1]; 10326 u8 regs_39_to_32[0x8]; 10327 10328 u8 regs_31_to_11[0x15]; 10329 u8 mtmp[0x1]; 10330 u8 regs_9_to_0[0xa]; 10331 }; 10332 10333 struct mlx5_ifc_mcam_access_reg_bits1 { 10334 u8 regs_127_to_96[0x20]; 10335 10336 u8 regs_95_to_64[0x20]; 10337 10338 u8 regs_63_to_32[0x20]; 10339 10340 u8 regs_31_to_0[0x20]; 10341 }; 10342 10343 struct mlx5_ifc_mcam_access_reg_bits2 { 10344 u8 regs_127_to_99[0x1d]; 10345 u8 mirc[0x1]; 10346 u8 regs_97_to_96[0x2]; 10347 10348 u8 regs_95_to_87[0x09]; 10349 u8 synce_registers[0x2]; 10350 u8 regs_84_to_64[0x15]; 10351 10352 u8 regs_63_to_32[0x20]; 10353 10354 u8 regs_31_to_0[0x20]; 10355 }; 10356 10357 struct mlx5_ifc_mcam_reg_bits { 10358 u8 reserved_at_0[0x8]; 10359 u8 feature_group[0x8]; 10360 u8 reserved_at_10[0x8]; 10361 u8 access_reg_group[0x8]; 10362 10363 u8 reserved_at_20[0x20]; 10364 10365 union { 10366 struct mlx5_ifc_mcam_access_reg_bits access_regs; 10367 struct mlx5_ifc_mcam_access_reg_bits1 access_regs1; 10368 struct mlx5_ifc_mcam_access_reg_bits2 access_regs2; 10369 u8 reserved_at_0[0x80]; 10370 } mng_access_reg_cap_mask; 10371 10372 u8 reserved_at_c0[0x80]; 10373 10374 union { 10375 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features; 10376 u8 reserved_at_0[0x80]; 10377 } mng_feature_cap_mask; 10378 10379 u8 reserved_at_1c0[0x80]; 10380 }; 10381 10382 struct mlx5_ifc_qcam_access_reg_cap_mask { 10383 u8 qcam_access_reg_cap_mask_127_to_20[0x6C]; 10384 u8 qpdpm[0x1]; 10385 u8 qcam_access_reg_cap_mask_18_to_4[0x0F]; 10386 u8 qdpm[0x1]; 10387 u8 qpts[0x1]; 10388 u8 qcap[0x1]; 10389 u8 qcam_access_reg_cap_mask_0[0x1]; 10390 }; 10391 10392 struct mlx5_ifc_qcam_qos_feature_cap_mask { 10393 u8 qcam_qos_feature_cap_mask_127_to_1[0x7F]; 10394 u8 qpts_trust_both[0x1]; 10395 }; 10396 10397 struct mlx5_ifc_qcam_reg_bits { 10398 u8 reserved_at_0[0x8]; 10399 u8 feature_group[0x8]; 10400 u8 reserved_at_10[0x8]; 10401 u8 access_reg_group[0x8]; 10402 u8 reserved_at_20[0x20]; 10403 10404 union { 10405 struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap; 10406 u8 reserved_at_0[0x80]; 10407 } qos_access_reg_cap_mask; 10408 10409 u8 reserved_at_c0[0x80]; 10410 10411 union { 10412 struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap; 10413 u8 reserved_at_0[0x80]; 10414 } qos_feature_cap_mask; 10415 10416 u8 reserved_at_1c0[0x80]; 10417 }; 10418 10419 struct mlx5_ifc_core_dump_reg_bits { 10420 u8 reserved_at_0[0x18]; 10421 u8 core_dump_type[0x8]; 10422 10423 u8 reserved_at_20[0x30]; 10424 u8 vhca_id[0x10]; 10425 10426 u8 reserved_at_60[0x8]; 10427 u8 qpn[0x18]; 10428 u8 reserved_at_80[0x180]; 10429 }; 10430 10431 struct mlx5_ifc_pcap_reg_bits { 10432 u8 reserved_at_0[0x8]; 10433 u8 local_port[0x8]; 10434 u8 reserved_at_10[0x10]; 10435 10436 u8 port_capability_mask[4][0x20]; 10437 }; 10438 10439 struct mlx5_ifc_paos_reg_bits { 10440 u8 swid[0x8]; 10441 u8 local_port[0x8]; 10442 u8 reserved_at_10[0x4]; 10443 u8 admin_status[0x4]; 10444 u8 reserved_at_18[0x4]; 10445 u8 oper_status[0x4]; 10446 10447 u8 ase[0x1]; 10448 u8 ee[0x1]; 10449 u8 reserved_at_22[0x1c]; 10450 u8 e[0x2]; 10451 10452 u8 reserved_at_40[0x40]; 10453 }; 10454 10455 struct mlx5_ifc_pamp_reg_bits { 10456 u8 reserved_at_0[0x8]; 10457 u8 opamp_group[0x8]; 10458 u8 reserved_at_10[0xc]; 10459 u8 opamp_group_type[0x4]; 10460 10461 u8 start_index[0x10]; 10462 u8 reserved_at_30[0x4]; 10463 u8 num_of_indices[0xc]; 10464 10465 u8 index_data[18][0x10]; 10466 }; 10467 10468 struct mlx5_ifc_pcmr_reg_bits { 10469 u8 reserved_at_0[0x8]; 10470 u8 local_port[0x8]; 10471 u8 reserved_at_10[0x10]; 10472 10473 u8 entropy_force_cap[0x1]; 10474 u8 entropy_calc_cap[0x1]; 10475 u8 entropy_gre_calc_cap[0x1]; 10476 u8 reserved_at_23[0xf]; 10477 u8 rx_ts_over_crc_cap[0x1]; 10478 u8 reserved_at_33[0xb]; 10479 u8 fcs_cap[0x1]; 10480 u8 reserved_at_3f[0x1]; 10481 10482 u8 entropy_force[0x1]; 10483 u8 entropy_calc[0x1]; 10484 u8 entropy_gre_calc[0x1]; 10485 u8 reserved_at_43[0xf]; 10486 u8 rx_ts_over_crc[0x1]; 10487 u8 reserved_at_53[0xb]; 10488 u8 fcs_chk[0x1]; 10489 u8 reserved_at_5f[0x1]; 10490 }; 10491 10492 struct mlx5_ifc_lane_2_module_mapping_bits { 10493 u8 reserved_at_0[0x4]; 10494 u8 rx_lane[0x4]; 10495 u8 reserved_at_8[0x4]; 10496 u8 tx_lane[0x4]; 10497 u8 reserved_at_10[0x8]; 10498 u8 module[0x8]; 10499 }; 10500 10501 struct mlx5_ifc_bufferx_reg_bits { 10502 u8 reserved_at_0[0x6]; 10503 u8 lossy[0x1]; 10504 u8 epsb[0x1]; 10505 u8 reserved_at_8[0x8]; 10506 u8 size[0x10]; 10507 10508 u8 xoff_threshold[0x10]; 10509 u8 xon_threshold[0x10]; 10510 }; 10511 10512 struct mlx5_ifc_set_node_in_bits { 10513 u8 node_description[64][0x8]; 10514 }; 10515 10516 struct mlx5_ifc_register_power_settings_bits { 10517 u8 reserved_at_0[0x18]; 10518 u8 power_settings_level[0x8]; 10519 10520 u8 reserved_at_20[0x60]; 10521 }; 10522 10523 struct mlx5_ifc_register_host_endianness_bits { 10524 u8 he[0x1]; 10525 u8 reserved_at_1[0x1f]; 10526 10527 u8 reserved_at_20[0x60]; 10528 }; 10529 10530 struct mlx5_ifc_umr_pointer_desc_argument_bits { 10531 u8 reserved_at_0[0x20]; 10532 10533 u8 mkey[0x20]; 10534 10535 u8 addressh_63_32[0x20]; 10536 10537 u8 addressl_31_0[0x20]; 10538 }; 10539 10540 struct mlx5_ifc_ud_adrs_vector_bits { 10541 u8 dc_key[0x40]; 10542 10543 u8 ext[0x1]; 10544 u8 reserved_at_41[0x7]; 10545 u8 destination_qp_dct[0x18]; 10546 10547 u8 static_rate[0x4]; 10548 u8 sl_eth_prio[0x4]; 10549 u8 fl[0x1]; 10550 u8 mlid[0x7]; 10551 u8 rlid_udp_sport[0x10]; 10552 10553 u8 reserved_at_80[0x20]; 10554 10555 u8 rmac_47_16[0x20]; 10556 10557 u8 rmac_15_0[0x10]; 10558 u8 tclass[0x8]; 10559 u8 hop_limit[0x8]; 10560 10561 u8 reserved_at_e0[0x1]; 10562 u8 grh[0x1]; 10563 u8 reserved_at_e2[0x2]; 10564 u8 src_addr_index[0x8]; 10565 u8 flow_label[0x14]; 10566 10567 u8 rgid_rip[16][0x8]; 10568 }; 10569 10570 struct mlx5_ifc_pages_req_event_bits { 10571 u8 reserved_at_0[0x10]; 10572 u8 function_id[0x10]; 10573 10574 u8 num_pages[0x20]; 10575 10576 u8 reserved_at_40[0xa0]; 10577 }; 10578 10579 struct mlx5_ifc_eqe_bits { 10580 u8 reserved_at_0[0x8]; 10581 u8 event_type[0x8]; 10582 u8 reserved_at_10[0x8]; 10583 u8 event_sub_type[0x8]; 10584 10585 u8 reserved_at_20[0xe0]; 10586 10587 union mlx5_ifc_event_auto_bits event_data; 10588 10589 u8 reserved_at_1e0[0x10]; 10590 u8 signature[0x8]; 10591 u8 reserved_at_1f8[0x7]; 10592 u8 owner[0x1]; 10593 }; 10594 10595 enum { 10596 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7, 10597 }; 10598 10599 struct mlx5_ifc_cmd_queue_entry_bits { 10600 u8 type[0x8]; 10601 u8 reserved_at_8[0x18]; 10602 10603 u8 input_length[0x20]; 10604 10605 u8 input_mailbox_pointer_63_32[0x20]; 10606 10607 u8 input_mailbox_pointer_31_9[0x17]; 10608 u8 reserved_at_77[0x9]; 10609 10610 u8 command_input_inline_data[16][0x8]; 10611 10612 u8 command_output_inline_data[16][0x8]; 10613 10614 u8 output_mailbox_pointer_63_32[0x20]; 10615 10616 u8 output_mailbox_pointer_31_9[0x17]; 10617 u8 reserved_at_1b7[0x9]; 10618 10619 u8 output_length[0x20]; 10620 10621 u8 token[0x8]; 10622 u8 signature[0x8]; 10623 u8 reserved_at_1f0[0x8]; 10624 u8 status[0x7]; 10625 u8 ownership[0x1]; 10626 }; 10627 10628 struct mlx5_ifc_cmd_out_bits { 10629 u8 status[0x8]; 10630 u8 reserved_at_8[0x18]; 10631 10632 u8 syndrome[0x20]; 10633 10634 u8 command_output[0x20]; 10635 }; 10636 10637 struct mlx5_ifc_cmd_in_bits { 10638 u8 opcode[0x10]; 10639 u8 reserved_at_10[0x10]; 10640 10641 u8 reserved_at_20[0x10]; 10642 u8 op_mod[0x10]; 10643 10644 u8 command[][0x20]; 10645 }; 10646 10647 struct mlx5_ifc_cmd_if_box_bits { 10648 u8 mailbox_data[512][0x8]; 10649 10650 u8 reserved_at_1000[0x180]; 10651 10652 u8 next_pointer_63_32[0x20]; 10653 10654 u8 next_pointer_31_10[0x16]; 10655 u8 reserved_at_11b6[0xa]; 10656 10657 u8 block_number[0x20]; 10658 10659 u8 reserved_at_11e0[0x8]; 10660 u8 token[0x8]; 10661 u8 ctrl_signature[0x8]; 10662 u8 signature[0x8]; 10663 }; 10664 10665 struct mlx5_ifc_mtt_bits { 10666 u8 ptag_63_32[0x20]; 10667 10668 u8 ptag_31_8[0x18]; 10669 u8 reserved_at_38[0x6]; 10670 u8 wr_en[0x1]; 10671 u8 rd_en[0x1]; 10672 }; 10673 10674 struct mlx5_ifc_query_wol_rol_out_bits { 10675 u8 status[0x8]; 10676 u8 reserved_at_8[0x18]; 10677 10678 u8 syndrome[0x20]; 10679 10680 u8 reserved_at_40[0x10]; 10681 u8 rol_mode[0x8]; 10682 u8 wol_mode[0x8]; 10683 10684 u8 reserved_at_60[0x20]; 10685 }; 10686 10687 struct mlx5_ifc_query_wol_rol_in_bits { 10688 u8 opcode[0x10]; 10689 u8 reserved_at_10[0x10]; 10690 10691 u8 reserved_at_20[0x10]; 10692 u8 op_mod[0x10]; 10693 10694 u8 reserved_at_40[0x40]; 10695 }; 10696 10697 struct mlx5_ifc_set_wol_rol_out_bits { 10698 u8 status[0x8]; 10699 u8 reserved_at_8[0x18]; 10700 10701 u8 syndrome[0x20]; 10702 10703 u8 reserved_at_40[0x40]; 10704 }; 10705 10706 struct mlx5_ifc_set_wol_rol_in_bits { 10707 u8 opcode[0x10]; 10708 u8 reserved_at_10[0x10]; 10709 10710 u8 reserved_at_20[0x10]; 10711 u8 op_mod[0x10]; 10712 10713 u8 rol_mode_valid[0x1]; 10714 u8 wol_mode_valid[0x1]; 10715 u8 reserved_at_42[0xe]; 10716 u8 rol_mode[0x8]; 10717 u8 wol_mode[0x8]; 10718 10719 u8 reserved_at_60[0x20]; 10720 }; 10721 10722 enum { 10723 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0, 10724 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1, 10725 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2, 10726 MLX5_INITIAL_SEG_NIC_INTERFACE_SW_RESET = 0x7, 10727 }; 10728 10729 enum { 10730 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0, 10731 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1, 10732 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2, 10733 }; 10734 10735 enum { 10736 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR = 0x1, 10737 MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC = 0x7, 10738 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR = 0x8, 10739 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR = 0x9, 10740 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR = 0xa, 10741 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR = 0xb, 10742 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN = 0xc, 10743 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR = 0xd, 10744 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV = 0xe, 10745 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR = 0xf, 10746 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR = 0x10, 10747 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PCI_POISONED_ERR = 0x12, 10748 }; 10749 10750 struct mlx5_ifc_initial_seg_bits { 10751 u8 fw_rev_minor[0x10]; 10752 u8 fw_rev_major[0x10]; 10753 10754 u8 cmd_interface_rev[0x10]; 10755 u8 fw_rev_subminor[0x10]; 10756 10757 u8 reserved_at_40[0x40]; 10758 10759 u8 cmdq_phy_addr_63_32[0x20]; 10760 10761 u8 cmdq_phy_addr_31_12[0x14]; 10762 u8 reserved_at_b4[0x2]; 10763 u8 nic_interface[0x2]; 10764 u8 log_cmdq_size[0x4]; 10765 u8 log_cmdq_stride[0x4]; 10766 10767 u8 command_doorbell_vector[0x20]; 10768 10769 u8 reserved_at_e0[0xf00]; 10770 10771 u8 initializing[0x1]; 10772 u8 reserved_at_fe1[0x4]; 10773 u8 nic_interface_supported[0x3]; 10774 u8 embedded_cpu[0x1]; 10775 u8 reserved_at_fe9[0x17]; 10776 10777 struct mlx5_ifc_health_buffer_bits health_buffer; 10778 10779 u8 no_dram_nic_offset[0x20]; 10780 10781 u8 reserved_at_1220[0x6e40]; 10782 10783 u8 reserved_at_8060[0x1f]; 10784 u8 clear_int[0x1]; 10785 10786 u8 health_syndrome[0x8]; 10787 u8 health_counter[0x18]; 10788 10789 u8 reserved_at_80a0[0x17fc0]; 10790 }; 10791 10792 struct mlx5_ifc_mtpps_reg_bits { 10793 u8 reserved_at_0[0xc]; 10794 u8 cap_number_of_pps_pins[0x4]; 10795 u8 reserved_at_10[0x4]; 10796 u8 cap_max_num_of_pps_in_pins[0x4]; 10797 u8 reserved_at_18[0x4]; 10798 u8 cap_max_num_of_pps_out_pins[0x4]; 10799 10800 u8 reserved_at_20[0x13]; 10801 u8 cap_log_min_npps_period[0x5]; 10802 u8 reserved_at_38[0x3]; 10803 u8 cap_log_min_out_pulse_duration_ns[0x5]; 10804 10805 u8 reserved_at_40[0x4]; 10806 u8 cap_pin_3_mode[0x4]; 10807 u8 reserved_at_48[0x4]; 10808 u8 cap_pin_2_mode[0x4]; 10809 u8 reserved_at_50[0x4]; 10810 u8 cap_pin_1_mode[0x4]; 10811 u8 reserved_at_58[0x4]; 10812 u8 cap_pin_0_mode[0x4]; 10813 10814 u8 reserved_at_60[0x4]; 10815 u8 cap_pin_7_mode[0x4]; 10816 u8 reserved_at_68[0x4]; 10817 u8 cap_pin_6_mode[0x4]; 10818 u8 reserved_at_70[0x4]; 10819 u8 cap_pin_5_mode[0x4]; 10820 u8 reserved_at_78[0x4]; 10821 u8 cap_pin_4_mode[0x4]; 10822 10823 u8 field_select[0x20]; 10824 u8 reserved_at_a0[0x20]; 10825 10826 u8 npps_period[0x40]; 10827 10828 u8 enable[0x1]; 10829 u8 reserved_at_101[0xb]; 10830 u8 pattern[0x4]; 10831 u8 reserved_at_110[0x4]; 10832 u8 pin_mode[0x4]; 10833 u8 pin[0x8]; 10834 10835 u8 reserved_at_120[0x2]; 10836 u8 out_pulse_duration_ns[0x1e]; 10837 10838 u8 time_stamp[0x40]; 10839 10840 u8 out_pulse_duration[0x10]; 10841 u8 out_periodic_adjustment[0x10]; 10842 u8 enhanced_out_periodic_adjustment[0x20]; 10843 10844 u8 reserved_at_1c0[0x20]; 10845 }; 10846 10847 struct mlx5_ifc_mtppse_reg_bits { 10848 u8 reserved_at_0[0x18]; 10849 u8 pin[0x8]; 10850 u8 event_arm[0x1]; 10851 u8 reserved_at_21[0x1b]; 10852 u8 event_generation_mode[0x4]; 10853 u8 reserved_at_40[0x40]; 10854 }; 10855 10856 struct mlx5_ifc_mcqs_reg_bits { 10857 u8 last_index_flag[0x1]; 10858 u8 reserved_at_1[0x7]; 10859 u8 fw_device[0x8]; 10860 u8 component_index[0x10]; 10861 10862 u8 reserved_at_20[0x10]; 10863 u8 identifier[0x10]; 10864 10865 u8 reserved_at_40[0x17]; 10866 u8 component_status[0x5]; 10867 u8 component_update_state[0x4]; 10868 10869 u8 last_update_state_changer_type[0x4]; 10870 u8 last_update_state_changer_host_id[0x4]; 10871 u8 reserved_at_68[0x18]; 10872 }; 10873 10874 struct mlx5_ifc_mcqi_cap_bits { 10875 u8 supported_info_bitmask[0x20]; 10876 10877 u8 component_size[0x20]; 10878 10879 u8 max_component_size[0x20]; 10880 10881 u8 log_mcda_word_size[0x4]; 10882 u8 reserved_at_64[0xc]; 10883 u8 mcda_max_write_size[0x10]; 10884 10885 u8 rd_en[0x1]; 10886 u8 reserved_at_81[0x1]; 10887 u8 match_chip_id[0x1]; 10888 u8 match_psid[0x1]; 10889 u8 check_user_timestamp[0x1]; 10890 u8 match_base_guid_mac[0x1]; 10891 u8 reserved_at_86[0x1a]; 10892 }; 10893 10894 struct mlx5_ifc_mcqi_version_bits { 10895 u8 reserved_at_0[0x2]; 10896 u8 build_time_valid[0x1]; 10897 u8 user_defined_time_valid[0x1]; 10898 u8 reserved_at_4[0x14]; 10899 u8 version_string_length[0x8]; 10900 10901 u8 version[0x20]; 10902 10903 u8 build_time[0x40]; 10904 10905 u8 user_defined_time[0x40]; 10906 10907 u8 build_tool_version[0x20]; 10908 10909 u8 reserved_at_e0[0x20]; 10910 10911 u8 version_string[92][0x8]; 10912 }; 10913 10914 struct mlx5_ifc_mcqi_activation_method_bits { 10915 u8 pending_server_ac_power_cycle[0x1]; 10916 u8 pending_server_dc_power_cycle[0x1]; 10917 u8 pending_server_reboot[0x1]; 10918 u8 pending_fw_reset[0x1]; 10919 u8 auto_activate[0x1]; 10920 u8 all_hosts_sync[0x1]; 10921 u8 device_hw_reset[0x1]; 10922 u8 reserved_at_7[0x19]; 10923 }; 10924 10925 union mlx5_ifc_mcqi_reg_data_bits { 10926 struct mlx5_ifc_mcqi_cap_bits mcqi_caps; 10927 struct mlx5_ifc_mcqi_version_bits mcqi_version; 10928 struct mlx5_ifc_mcqi_activation_method_bits mcqi_activation_mathod; 10929 }; 10930 10931 struct mlx5_ifc_mcqi_reg_bits { 10932 u8 read_pending_component[0x1]; 10933 u8 reserved_at_1[0xf]; 10934 u8 component_index[0x10]; 10935 10936 u8 reserved_at_20[0x20]; 10937 10938 u8 reserved_at_40[0x1b]; 10939 u8 info_type[0x5]; 10940 10941 u8 info_size[0x20]; 10942 10943 u8 offset[0x20]; 10944 10945 u8 reserved_at_a0[0x10]; 10946 u8 data_size[0x10]; 10947 10948 union mlx5_ifc_mcqi_reg_data_bits data[]; 10949 }; 10950 10951 struct mlx5_ifc_mcc_reg_bits { 10952 u8 reserved_at_0[0x4]; 10953 u8 time_elapsed_since_last_cmd[0xc]; 10954 u8 reserved_at_10[0x8]; 10955 u8 instruction[0x8]; 10956 10957 u8 reserved_at_20[0x10]; 10958 u8 component_index[0x10]; 10959 10960 u8 reserved_at_40[0x8]; 10961 u8 update_handle[0x18]; 10962 10963 u8 handle_owner_type[0x4]; 10964 u8 handle_owner_host_id[0x4]; 10965 u8 reserved_at_68[0x1]; 10966 u8 control_progress[0x7]; 10967 u8 error_code[0x8]; 10968 u8 reserved_at_78[0x4]; 10969 u8 control_state[0x4]; 10970 10971 u8 component_size[0x20]; 10972 10973 u8 reserved_at_a0[0x60]; 10974 }; 10975 10976 struct mlx5_ifc_mcda_reg_bits { 10977 u8 reserved_at_0[0x8]; 10978 u8 update_handle[0x18]; 10979 10980 u8 offset[0x20]; 10981 10982 u8 reserved_at_40[0x10]; 10983 u8 size[0x10]; 10984 10985 u8 reserved_at_60[0x20]; 10986 10987 u8 data[][0x20]; 10988 }; 10989 10990 enum { 10991 MLX5_MFRL_REG_RESET_STATE_IDLE = 0, 10992 MLX5_MFRL_REG_RESET_STATE_IN_NEGOTIATION = 1, 10993 MLX5_MFRL_REG_RESET_STATE_RESET_IN_PROGRESS = 2, 10994 MLX5_MFRL_REG_RESET_STATE_NEG_TIMEOUT = 3, 10995 MLX5_MFRL_REG_RESET_STATE_NACK = 4, 10996 MLX5_MFRL_REG_RESET_STATE_UNLOAD_TIMEOUT = 5, 10997 }; 10998 10999 enum { 11000 MLX5_MFRL_REG_RESET_TYPE_FULL_CHIP = BIT(0), 11001 MLX5_MFRL_REG_RESET_TYPE_NET_PORT_ALIVE = BIT(1), 11002 }; 11003 11004 enum { 11005 MLX5_MFRL_REG_RESET_LEVEL0 = BIT(0), 11006 MLX5_MFRL_REG_RESET_LEVEL3 = BIT(3), 11007 MLX5_MFRL_REG_RESET_LEVEL6 = BIT(6), 11008 }; 11009 11010 struct mlx5_ifc_mfrl_reg_bits { 11011 u8 reserved_at_0[0x20]; 11012 11013 u8 reserved_at_20[0x2]; 11014 u8 pci_sync_for_fw_update_start[0x1]; 11015 u8 pci_sync_for_fw_update_resp[0x2]; 11016 u8 rst_type_sel[0x3]; 11017 u8 reserved_at_28[0x4]; 11018 u8 reset_state[0x4]; 11019 u8 reset_type[0x8]; 11020 u8 reset_level[0x8]; 11021 }; 11022 11023 struct mlx5_ifc_mirc_reg_bits { 11024 u8 reserved_at_0[0x18]; 11025 u8 status_code[0x8]; 11026 11027 u8 reserved_at_20[0x20]; 11028 }; 11029 11030 struct mlx5_ifc_pddr_monitor_opcode_bits { 11031 u8 reserved_at_0[0x10]; 11032 u8 monitor_opcode[0x10]; 11033 }; 11034 11035 union mlx5_ifc_pddr_troubleshooting_page_status_opcode_auto_bits { 11036 struct mlx5_ifc_pddr_monitor_opcode_bits pddr_monitor_opcode; 11037 u8 reserved_at_0[0x20]; 11038 }; 11039 11040 enum { 11041 /* Monitor opcodes */ 11042 MLX5_PDDR_REG_TRBLSH_GROUP_OPCODE_MONITOR = 0x0, 11043 }; 11044 11045 struct mlx5_ifc_pddr_troubleshooting_page_bits { 11046 u8 reserved_at_0[0x10]; 11047 u8 group_opcode[0x10]; 11048 11049 union mlx5_ifc_pddr_troubleshooting_page_status_opcode_auto_bits status_opcode; 11050 11051 u8 reserved_at_40[0x20]; 11052 11053 u8 status_message[59][0x20]; 11054 }; 11055 11056 union mlx5_ifc_pddr_reg_page_data_auto_bits { 11057 struct mlx5_ifc_pddr_troubleshooting_page_bits pddr_troubleshooting_page; 11058 u8 reserved_at_0[0x7c0]; 11059 }; 11060 11061 enum { 11062 MLX5_PDDR_REG_PAGE_SELECT_TROUBLESHOOTING_INFO_PAGE = 0x1, 11063 }; 11064 11065 struct mlx5_ifc_pddr_reg_bits { 11066 u8 reserved_at_0[0x8]; 11067 u8 local_port[0x8]; 11068 u8 pnat[0x2]; 11069 u8 reserved_at_12[0xe]; 11070 11071 u8 reserved_at_20[0x18]; 11072 u8 page_select[0x8]; 11073 11074 union mlx5_ifc_pddr_reg_page_data_auto_bits page_data; 11075 }; 11076 11077 struct mlx5_ifc_mrtc_reg_bits { 11078 u8 time_synced[0x1]; 11079 u8 reserved_at_1[0x1f]; 11080 11081 u8 reserved_at_20[0x20]; 11082 11083 u8 time_h[0x20]; 11084 11085 u8 time_l[0x20]; 11086 }; 11087 11088 struct mlx5_ifc_mtcap_reg_bits { 11089 u8 reserved_at_0[0x19]; 11090 u8 sensor_count[0x7]; 11091 11092 u8 reserved_at_20[0x20]; 11093 11094 u8 sensor_map[0x40]; 11095 }; 11096 11097 struct mlx5_ifc_mtmp_reg_bits { 11098 u8 reserved_at_0[0x14]; 11099 u8 sensor_index[0xc]; 11100 11101 u8 reserved_at_20[0x10]; 11102 u8 temperature[0x10]; 11103 11104 u8 mte[0x1]; 11105 u8 mtr[0x1]; 11106 u8 reserved_at_42[0xe]; 11107 u8 max_temperature[0x10]; 11108 11109 u8 tee[0x2]; 11110 u8 reserved_at_62[0xe]; 11111 u8 temp_threshold_hi[0x10]; 11112 11113 u8 reserved_at_80[0x10]; 11114 u8 temp_threshold_lo[0x10]; 11115 11116 u8 reserved_at_a0[0x20]; 11117 11118 u8 sensor_name_hi[0x20]; 11119 u8 sensor_name_lo[0x20]; 11120 }; 11121 11122 union mlx5_ifc_ports_control_registers_document_bits { 11123 struct mlx5_ifc_bufferx_reg_bits bufferx_reg; 11124 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 11125 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 11126 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 11127 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 11128 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 11129 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 11130 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout; 11131 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout; 11132 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping; 11133 struct mlx5_ifc_pamp_reg_bits pamp_reg; 11134 struct mlx5_ifc_paos_reg_bits paos_reg; 11135 struct mlx5_ifc_pcap_reg_bits pcap_reg; 11136 struct mlx5_ifc_pddr_monitor_opcode_bits pddr_monitor_opcode; 11137 struct mlx5_ifc_pddr_reg_bits pddr_reg; 11138 struct mlx5_ifc_pddr_troubleshooting_page_bits pddr_troubleshooting_page; 11139 struct mlx5_ifc_peir_reg_bits peir_reg; 11140 struct mlx5_ifc_pelc_reg_bits pelc_reg; 11141 struct mlx5_ifc_pfcc_reg_bits pfcc_reg; 11142 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 11143 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 11144 struct mlx5_ifc_pifr_reg_bits pifr_reg; 11145 struct mlx5_ifc_pipg_reg_bits pipg_reg; 11146 struct mlx5_ifc_plbf_reg_bits plbf_reg; 11147 struct mlx5_ifc_plib_reg_bits plib_reg; 11148 struct mlx5_ifc_plpc_reg_bits plpc_reg; 11149 struct mlx5_ifc_pmaos_reg_bits pmaos_reg; 11150 struct mlx5_ifc_pmlp_reg_bits pmlp_reg; 11151 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg; 11152 struct mlx5_ifc_pmpc_reg_bits pmpc_reg; 11153 struct mlx5_ifc_pmpe_reg_bits pmpe_reg; 11154 struct mlx5_ifc_pmpr_reg_bits pmpr_reg; 11155 struct mlx5_ifc_pmtu_reg_bits pmtu_reg; 11156 struct mlx5_ifc_ppad_reg_bits ppad_reg; 11157 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg; 11158 struct mlx5_ifc_mpein_reg_bits mpein_reg; 11159 struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg; 11160 struct mlx5_ifc_pplm_reg_bits pplm_reg; 11161 struct mlx5_ifc_pplr_reg_bits pplr_reg; 11162 struct mlx5_ifc_ppsc_reg_bits ppsc_reg; 11163 struct mlx5_ifc_pqdr_reg_bits pqdr_reg; 11164 struct mlx5_ifc_pspa_reg_bits pspa_reg; 11165 struct mlx5_ifc_ptas_reg_bits ptas_reg; 11166 struct mlx5_ifc_ptys_reg_bits ptys_reg; 11167 struct mlx5_ifc_mlcr_reg_bits mlcr_reg; 11168 struct mlx5_ifc_pude_reg_bits pude_reg; 11169 struct mlx5_ifc_pvlc_reg_bits pvlc_reg; 11170 struct mlx5_ifc_slrg_reg_bits slrg_reg; 11171 struct mlx5_ifc_sltp_reg_bits sltp_reg; 11172 struct mlx5_ifc_mtpps_reg_bits mtpps_reg; 11173 struct mlx5_ifc_mtppse_reg_bits mtppse_reg; 11174 struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg; 11175 struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits; 11176 struct mlx5_ifc_fpga_cap_bits fpga_cap_bits; 11177 struct mlx5_ifc_mcqi_reg_bits mcqi_reg; 11178 struct mlx5_ifc_mcc_reg_bits mcc_reg; 11179 struct mlx5_ifc_mcda_reg_bits mcda_reg; 11180 struct mlx5_ifc_mirc_reg_bits mirc_reg; 11181 struct mlx5_ifc_mfrl_reg_bits mfrl_reg; 11182 struct mlx5_ifc_mtutc_reg_bits mtutc_reg; 11183 struct mlx5_ifc_mrtc_reg_bits mrtc_reg; 11184 struct mlx5_ifc_mtcap_reg_bits mtcap_reg; 11185 struct mlx5_ifc_mtmp_reg_bits mtmp_reg; 11186 u8 reserved_at_0[0x60e0]; 11187 }; 11188 11189 union mlx5_ifc_debug_enhancements_document_bits { 11190 struct mlx5_ifc_health_buffer_bits health_buffer; 11191 u8 reserved_at_0[0x200]; 11192 }; 11193 11194 union mlx5_ifc_uplink_pci_interface_document_bits { 11195 struct mlx5_ifc_initial_seg_bits initial_seg; 11196 u8 reserved_at_0[0x20060]; 11197 }; 11198 11199 struct mlx5_ifc_set_flow_table_root_out_bits { 11200 u8 status[0x8]; 11201 u8 reserved_at_8[0x18]; 11202 11203 u8 syndrome[0x20]; 11204 11205 u8 reserved_at_40[0x40]; 11206 }; 11207 11208 struct mlx5_ifc_set_flow_table_root_in_bits { 11209 u8 opcode[0x10]; 11210 u8 reserved_at_10[0x10]; 11211 11212 u8 reserved_at_20[0x10]; 11213 u8 op_mod[0x10]; 11214 11215 u8 other_vport[0x1]; 11216 u8 reserved_at_41[0xf]; 11217 u8 vport_number[0x10]; 11218 11219 u8 reserved_at_60[0x20]; 11220 11221 u8 table_type[0x8]; 11222 u8 reserved_at_88[0x7]; 11223 u8 table_of_other_vport[0x1]; 11224 u8 table_vport_number[0x10]; 11225 11226 u8 reserved_at_a0[0x8]; 11227 u8 table_id[0x18]; 11228 11229 u8 reserved_at_c0[0x8]; 11230 u8 underlay_qpn[0x18]; 11231 u8 table_eswitch_owner_vhca_id_valid[0x1]; 11232 u8 reserved_at_e1[0xf]; 11233 u8 table_eswitch_owner_vhca_id[0x10]; 11234 u8 reserved_at_100[0x100]; 11235 }; 11236 11237 enum { 11238 MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = (1UL << 0), 11239 MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15), 11240 }; 11241 11242 struct mlx5_ifc_modify_flow_table_out_bits { 11243 u8 status[0x8]; 11244 u8 reserved_at_8[0x18]; 11245 11246 u8 syndrome[0x20]; 11247 11248 u8 reserved_at_40[0x40]; 11249 }; 11250 11251 struct mlx5_ifc_modify_flow_table_in_bits { 11252 u8 opcode[0x10]; 11253 u8 reserved_at_10[0x10]; 11254 11255 u8 reserved_at_20[0x10]; 11256 u8 op_mod[0x10]; 11257 11258 u8 other_vport[0x1]; 11259 u8 reserved_at_41[0xf]; 11260 u8 vport_number[0x10]; 11261 11262 u8 reserved_at_60[0x10]; 11263 u8 modify_field_select[0x10]; 11264 11265 u8 table_type[0x8]; 11266 u8 reserved_at_88[0x18]; 11267 11268 u8 reserved_at_a0[0x8]; 11269 u8 table_id[0x18]; 11270 11271 struct mlx5_ifc_flow_table_context_bits flow_table_context; 11272 }; 11273 11274 struct mlx5_ifc_ets_tcn_config_reg_bits { 11275 u8 g[0x1]; 11276 u8 b[0x1]; 11277 u8 r[0x1]; 11278 u8 reserved_at_3[0x9]; 11279 u8 group[0x4]; 11280 u8 reserved_at_10[0x9]; 11281 u8 bw_allocation[0x7]; 11282 11283 u8 reserved_at_20[0xc]; 11284 u8 max_bw_units[0x4]; 11285 u8 reserved_at_30[0x8]; 11286 u8 max_bw_value[0x8]; 11287 }; 11288 11289 struct mlx5_ifc_ets_global_config_reg_bits { 11290 u8 reserved_at_0[0x2]; 11291 u8 r[0x1]; 11292 u8 reserved_at_3[0x1d]; 11293 11294 u8 reserved_at_20[0xc]; 11295 u8 max_bw_units[0x4]; 11296 u8 reserved_at_30[0x8]; 11297 u8 max_bw_value[0x8]; 11298 }; 11299 11300 struct mlx5_ifc_qetc_reg_bits { 11301 u8 reserved_at_0[0x8]; 11302 u8 port_number[0x8]; 11303 u8 reserved_at_10[0x30]; 11304 11305 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8]; 11306 struct mlx5_ifc_ets_global_config_reg_bits global_configuration; 11307 }; 11308 11309 struct mlx5_ifc_qpdpm_dscp_reg_bits { 11310 u8 e[0x1]; 11311 u8 reserved_at_01[0x0b]; 11312 u8 prio[0x04]; 11313 }; 11314 11315 struct mlx5_ifc_qpdpm_reg_bits { 11316 u8 reserved_at_0[0x8]; 11317 u8 local_port[0x8]; 11318 u8 reserved_at_10[0x10]; 11319 struct mlx5_ifc_qpdpm_dscp_reg_bits dscp[64]; 11320 }; 11321 11322 struct mlx5_ifc_qpts_reg_bits { 11323 u8 reserved_at_0[0x8]; 11324 u8 local_port[0x8]; 11325 u8 reserved_at_10[0x2d]; 11326 u8 trust_state[0x3]; 11327 }; 11328 11329 struct mlx5_ifc_pptb_reg_bits { 11330 u8 reserved_at_0[0x2]; 11331 u8 mm[0x2]; 11332 u8 reserved_at_4[0x4]; 11333 u8 local_port[0x8]; 11334 u8 reserved_at_10[0x6]; 11335 u8 cm[0x1]; 11336 u8 um[0x1]; 11337 u8 pm[0x8]; 11338 11339 u8 prio_x_buff[0x20]; 11340 11341 u8 pm_msb[0x8]; 11342 u8 reserved_at_48[0x10]; 11343 u8 ctrl_buff[0x4]; 11344 u8 untagged_buff[0x4]; 11345 }; 11346 11347 struct mlx5_ifc_sbcam_reg_bits { 11348 u8 reserved_at_0[0x8]; 11349 u8 feature_group[0x8]; 11350 u8 reserved_at_10[0x8]; 11351 u8 access_reg_group[0x8]; 11352 11353 u8 reserved_at_20[0x20]; 11354 11355 u8 sb_access_reg_cap_mask[4][0x20]; 11356 11357 u8 reserved_at_c0[0x80]; 11358 11359 u8 sb_feature_cap_mask[4][0x20]; 11360 11361 u8 reserved_at_1c0[0x40]; 11362 11363 u8 cap_total_buffer_size[0x20]; 11364 11365 u8 cap_cell_size[0x10]; 11366 u8 cap_max_pg_buffers[0x8]; 11367 u8 cap_num_pool_supported[0x8]; 11368 11369 u8 reserved_at_240[0x8]; 11370 u8 cap_sbsr_stat_size[0x8]; 11371 u8 cap_max_tclass_data[0x8]; 11372 u8 cap_max_cpu_ingress_tclass_sb[0x8]; 11373 }; 11374 11375 struct mlx5_ifc_pbmc_reg_bits { 11376 u8 reserved_at_0[0x8]; 11377 u8 local_port[0x8]; 11378 u8 reserved_at_10[0x10]; 11379 11380 u8 xoff_timer_value[0x10]; 11381 u8 xoff_refresh[0x10]; 11382 11383 u8 reserved_at_40[0x9]; 11384 u8 fullness_threshold[0x7]; 11385 u8 port_buffer_size[0x10]; 11386 11387 struct mlx5_ifc_bufferx_reg_bits buffer[10]; 11388 11389 u8 reserved_at_2e0[0x80]; 11390 }; 11391 11392 struct mlx5_ifc_sbpr_reg_bits { 11393 u8 desc[0x1]; 11394 u8 snap[0x1]; 11395 u8 reserved_at_2[0x4]; 11396 u8 dir[0x2]; 11397 u8 reserved_at_8[0x14]; 11398 u8 pool[0x4]; 11399 11400 u8 infi_size[0x1]; 11401 u8 reserved_at_21[0x7]; 11402 u8 size[0x18]; 11403 11404 u8 reserved_at_40[0x1c]; 11405 u8 mode[0x4]; 11406 11407 u8 reserved_at_60[0x8]; 11408 u8 buff_occupancy[0x18]; 11409 11410 u8 clr[0x1]; 11411 u8 reserved_at_81[0x7]; 11412 u8 max_buff_occupancy[0x18]; 11413 11414 u8 reserved_at_a0[0x8]; 11415 u8 ext_buff_occupancy[0x18]; 11416 }; 11417 11418 struct mlx5_ifc_sbcm_reg_bits { 11419 u8 desc[0x1]; 11420 u8 snap[0x1]; 11421 u8 reserved_at_2[0x6]; 11422 u8 local_port[0x8]; 11423 u8 pnat[0x2]; 11424 u8 pg_buff[0x6]; 11425 u8 reserved_at_18[0x6]; 11426 u8 dir[0x2]; 11427 11428 u8 reserved_at_20[0x1f]; 11429 u8 exc[0x1]; 11430 11431 u8 reserved_at_40[0x40]; 11432 11433 u8 reserved_at_80[0x8]; 11434 u8 buff_occupancy[0x18]; 11435 11436 u8 clr[0x1]; 11437 u8 reserved_at_a1[0x7]; 11438 u8 max_buff_occupancy[0x18]; 11439 11440 u8 reserved_at_c0[0x8]; 11441 u8 min_buff[0x18]; 11442 11443 u8 infi_max[0x1]; 11444 u8 reserved_at_e1[0x7]; 11445 u8 max_buff[0x18]; 11446 11447 u8 reserved_at_100[0x20]; 11448 11449 u8 reserved_at_120[0x1c]; 11450 u8 pool[0x4]; 11451 }; 11452 11453 struct mlx5_ifc_qtct_reg_bits { 11454 u8 reserved_at_0[0x8]; 11455 u8 port_number[0x8]; 11456 u8 reserved_at_10[0xd]; 11457 u8 prio[0x3]; 11458 11459 u8 reserved_at_20[0x1d]; 11460 u8 tclass[0x3]; 11461 }; 11462 11463 struct mlx5_ifc_mcia_reg_bits { 11464 u8 l[0x1]; 11465 u8 reserved_at_1[0x7]; 11466 u8 module[0x8]; 11467 u8 reserved_at_10[0x8]; 11468 u8 status[0x8]; 11469 11470 u8 i2c_device_address[0x8]; 11471 u8 page_number[0x8]; 11472 u8 device_address[0x10]; 11473 11474 u8 reserved_at_40[0x10]; 11475 u8 size[0x10]; 11476 11477 u8 reserved_at_60[0x20]; 11478 11479 u8 dword_0[0x20]; 11480 u8 dword_1[0x20]; 11481 u8 dword_2[0x20]; 11482 u8 dword_3[0x20]; 11483 u8 dword_4[0x20]; 11484 u8 dword_5[0x20]; 11485 u8 dword_6[0x20]; 11486 u8 dword_7[0x20]; 11487 u8 dword_8[0x20]; 11488 u8 dword_9[0x20]; 11489 u8 dword_10[0x20]; 11490 u8 dword_11[0x20]; 11491 }; 11492 11493 struct mlx5_ifc_dcbx_param_bits { 11494 u8 dcbx_cee_cap[0x1]; 11495 u8 dcbx_ieee_cap[0x1]; 11496 u8 dcbx_standby_cap[0x1]; 11497 u8 reserved_at_3[0x5]; 11498 u8 port_number[0x8]; 11499 u8 reserved_at_10[0xa]; 11500 u8 max_application_table_size[6]; 11501 u8 reserved_at_20[0x15]; 11502 u8 version_oper[0x3]; 11503 u8 reserved_at_38[5]; 11504 u8 version_admin[0x3]; 11505 u8 willing_admin[0x1]; 11506 u8 reserved_at_41[0x3]; 11507 u8 pfc_cap_oper[0x4]; 11508 u8 reserved_at_48[0x4]; 11509 u8 pfc_cap_admin[0x4]; 11510 u8 reserved_at_50[0x4]; 11511 u8 num_of_tc_oper[0x4]; 11512 u8 reserved_at_58[0x4]; 11513 u8 num_of_tc_admin[0x4]; 11514 u8 remote_willing[0x1]; 11515 u8 reserved_at_61[3]; 11516 u8 remote_pfc_cap[4]; 11517 u8 reserved_at_68[0x14]; 11518 u8 remote_num_of_tc[0x4]; 11519 u8 reserved_at_80[0x18]; 11520 u8 error[0x8]; 11521 u8 reserved_at_a0[0x160]; 11522 }; 11523 11524 enum { 11525 MLX5_LAG_PORT_SELECT_MODE_QUEUE_AFFINITY = 0, 11526 MLX5_LAG_PORT_SELECT_MODE_PORT_SELECT_FT = 1, 11527 MLX5_LAG_PORT_SELECT_MODE_PORT_SELECT_MPESW = 2, 11528 }; 11529 11530 struct mlx5_ifc_lagc_bits { 11531 u8 fdb_selection_mode[0x1]; 11532 u8 reserved_at_1[0x14]; 11533 u8 port_select_mode[0x3]; 11534 u8 reserved_at_18[0x5]; 11535 u8 lag_state[0x3]; 11536 11537 u8 reserved_at_20[0xc]; 11538 u8 active_port[0x4]; 11539 u8 reserved_at_30[0x4]; 11540 u8 tx_remap_affinity_2[0x4]; 11541 u8 reserved_at_38[0x4]; 11542 u8 tx_remap_affinity_1[0x4]; 11543 }; 11544 11545 struct mlx5_ifc_create_lag_out_bits { 11546 u8 status[0x8]; 11547 u8 reserved_at_8[0x18]; 11548 11549 u8 syndrome[0x20]; 11550 11551 u8 reserved_at_40[0x40]; 11552 }; 11553 11554 struct mlx5_ifc_create_lag_in_bits { 11555 u8 opcode[0x10]; 11556 u8 reserved_at_10[0x10]; 11557 11558 u8 reserved_at_20[0x10]; 11559 u8 op_mod[0x10]; 11560 11561 struct mlx5_ifc_lagc_bits ctx; 11562 }; 11563 11564 struct mlx5_ifc_modify_lag_out_bits { 11565 u8 status[0x8]; 11566 u8 reserved_at_8[0x18]; 11567 11568 u8 syndrome[0x20]; 11569 11570 u8 reserved_at_40[0x40]; 11571 }; 11572 11573 struct mlx5_ifc_modify_lag_in_bits { 11574 u8 opcode[0x10]; 11575 u8 reserved_at_10[0x10]; 11576 11577 u8 reserved_at_20[0x10]; 11578 u8 op_mod[0x10]; 11579 11580 u8 reserved_at_40[0x20]; 11581 u8 field_select[0x20]; 11582 11583 struct mlx5_ifc_lagc_bits ctx; 11584 }; 11585 11586 struct mlx5_ifc_query_lag_out_bits { 11587 u8 status[0x8]; 11588 u8 reserved_at_8[0x18]; 11589 11590 u8 syndrome[0x20]; 11591 11592 struct mlx5_ifc_lagc_bits ctx; 11593 }; 11594 11595 struct mlx5_ifc_query_lag_in_bits { 11596 u8 opcode[0x10]; 11597 u8 reserved_at_10[0x10]; 11598 11599 u8 reserved_at_20[0x10]; 11600 u8 op_mod[0x10]; 11601 11602 u8 reserved_at_40[0x40]; 11603 }; 11604 11605 struct mlx5_ifc_destroy_lag_out_bits { 11606 u8 status[0x8]; 11607 u8 reserved_at_8[0x18]; 11608 11609 u8 syndrome[0x20]; 11610 11611 u8 reserved_at_40[0x40]; 11612 }; 11613 11614 struct mlx5_ifc_destroy_lag_in_bits { 11615 u8 opcode[0x10]; 11616 u8 reserved_at_10[0x10]; 11617 11618 u8 reserved_at_20[0x10]; 11619 u8 op_mod[0x10]; 11620 11621 u8 reserved_at_40[0x40]; 11622 }; 11623 11624 struct mlx5_ifc_create_vport_lag_out_bits { 11625 u8 status[0x8]; 11626 u8 reserved_at_8[0x18]; 11627 11628 u8 syndrome[0x20]; 11629 11630 u8 reserved_at_40[0x40]; 11631 }; 11632 11633 struct mlx5_ifc_create_vport_lag_in_bits { 11634 u8 opcode[0x10]; 11635 u8 reserved_at_10[0x10]; 11636 11637 u8 reserved_at_20[0x10]; 11638 u8 op_mod[0x10]; 11639 11640 u8 reserved_at_40[0x40]; 11641 }; 11642 11643 struct mlx5_ifc_destroy_vport_lag_out_bits { 11644 u8 status[0x8]; 11645 u8 reserved_at_8[0x18]; 11646 11647 u8 syndrome[0x20]; 11648 11649 u8 reserved_at_40[0x40]; 11650 }; 11651 11652 struct mlx5_ifc_destroy_vport_lag_in_bits { 11653 u8 opcode[0x10]; 11654 u8 reserved_at_10[0x10]; 11655 11656 u8 reserved_at_20[0x10]; 11657 u8 op_mod[0x10]; 11658 11659 u8 reserved_at_40[0x40]; 11660 }; 11661 11662 enum { 11663 MLX5_MODIFY_MEMIC_OP_MOD_ALLOC, 11664 MLX5_MODIFY_MEMIC_OP_MOD_DEALLOC, 11665 }; 11666 11667 struct mlx5_ifc_modify_memic_in_bits { 11668 u8 opcode[0x10]; 11669 u8 uid[0x10]; 11670 11671 u8 reserved_at_20[0x10]; 11672 u8 op_mod[0x10]; 11673 11674 u8 reserved_at_40[0x20]; 11675 11676 u8 reserved_at_60[0x18]; 11677 u8 memic_operation_type[0x8]; 11678 11679 u8 memic_start_addr[0x40]; 11680 11681 u8 reserved_at_c0[0x140]; 11682 }; 11683 11684 struct mlx5_ifc_modify_memic_out_bits { 11685 u8 status[0x8]; 11686 u8 reserved_at_8[0x18]; 11687 11688 u8 syndrome[0x20]; 11689 11690 u8 reserved_at_40[0x40]; 11691 11692 u8 memic_operation_addr[0x40]; 11693 11694 u8 reserved_at_c0[0x140]; 11695 }; 11696 11697 struct mlx5_ifc_alloc_memic_in_bits { 11698 u8 opcode[0x10]; 11699 u8 reserved_at_10[0x10]; 11700 11701 u8 reserved_at_20[0x10]; 11702 u8 op_mod[0x10]; 11703 11704 u8 reserved_at_30[0x20]; 11705 11706 u8 reserved_at_40[0x18]; 11707 u8 log_memic_addr_alignment[0x8]; 11708 11709 u8 range_start_addr[0x40]; 11710 11711 u8 range_size[0x20]; 11712 11713 u8 memic_size[0x20]; 11714 }; 11715 11716 struct mlx5_ifc_alloc_memic_out_bits { 11717 u8 status[0x8]; 11718 u8 reserved_at_8[0x18]; 11719 11720 u8 syndrome[0x20]; 11721 11722 u8 memic_start_addr[0x40]; 11723 }; 11724 11725 struct mlx5_ifc_dealloc_memic_in_bits { 11726 u8 opcode[0x10]; 11727 u8 reserved_at_10[0x10]; 11728 11729 u8 reserved_at_20[0x10]; 11730 u8 op_mod[0x10]; 11731 11732 u8 reserved_at_40[0x40]; 11733 11734 u8 memic_start_addr[0x40]; 11735 11736 u8 memic_size[0x20]; 11737 11738 u8 reserved_at_e0[0x20]; 11739 }; 11740 11741 struct mlx5_ifc_dealloc_memic_out_bits { 11742 u8 status[0x8]; 11743 u8 reserved_at_8[0x18]; 11744 11745 u8 syndrome[0x20]; 11746 11747 u8 reserved_at_40[0x40]; 11748 }; 11749 11750 struct mlx5_ifc_umem_bits { 11751 u8 reserved_at_0[0x80]; 11752 11753 u8 ats[0x1]; 11754 u8 reserved_at_81[0x1a]; 11755 u8 log_page_size[0x5]; 11756 11757 u8 page_offset[0x20]; 11758 11759 u8 num_of_mtt[0x40]; 11760 11761 struct mlx5_ifc_mtt_bits mtt[]; 11762 }; 11763 11764 struct mlx5_ifc_uctx_bits { 11765 u8 cap[0x20]; 11766 11767 u8 reserved_at_20[0x160]; 11768 }; 11769 11770 struct mlx5_ifc_sw_icm_bits { 11771 u8 modify_field_select[0x40]; 11772 11773 u8 reserved_at_40[0x18]; 11774 u8 log_sw_icm_size[0x8]; 11775 11776 u8 reserved_at_60[0x20]; 11777 11778 u8 sw_icm_start_addr[0x40]; 11779 11780 u8 reserved_at_c0[0x140]; 11781 }; 11782 11783 struct mlx5_ifc_geneve_tlv_option_bits { 11784 u8 modify_field_select[0x40]; 11785 11786 u8 reserved_at_40[0x18]; 11787 u8 geneve_option_fte_index[0x8]; 11788 11789 u8 option_class[0x10]; 11790 u8 option_type[0x8]; 11791 u8 reserved_at_78[0x3]; 11792 u8 option_data_length[0x5]; 11793 11794 u8 reserved_at_80[0x180]; 11795 }; 11796 11797 struct mlx5_ifc_create_umem_in_bits { 11798 u8 opcode[0x10]; 11799 u8 uid[0x10]; 11800 11801 u8 reserved_at_20[0x10]; 11802 u8 op_mod[0x10]; 11803 11804 u8 reserved_at_40[0x40]; 11805 11806 struct mlx5_ifc_umem_bits umem; 11807 }; 11808 11809 struct mlx5_ifc_create_umem_out_bits { 11810 u8 status[0x8]; 11811 u8 reserved_at_8[0x18]; 11812 11813 u8 syndrome[0x20]; 11814 11815 u8 reserved_at_40[0x8]; 11816 u8 umem_id[0x18]; 11817 11818 u8 reserved_at_60[0x20]; 11819 }; 11820 11821 struct mlx5_ifc_destroy_umem_in_bits { 11822 u8 opcode[0x10]; 11823 u8 uid[0x10]; 11824 11825 u8 reserved_at_20[0x10]; 11826 u8 op_mod[0x10]; 11827 11828 u8 reserved_at_40[0x8]; 11829 u8 umem_id[0x18]; 11830 11831 u8 reserved_at_60[0x20]; 11832 }; 11833 11834 struct mlx5_ifc_destroy_umem_out_bits { 11835 u8 status[0x8]; 11836 u8 reserved_at_8[0x18]; 11837 11838 u8 syndrome[0x20]; 11839 11840 u8 reserved_at_40[0x40]; 11841 }; 11842 11843 struct mlx5_ifc_create_uctx_in_bits { 11844 u8 opcode[0x10]; 11845 u8 reserved_at_10[0x10]; 11846 11847 u8 reserved_at_20[0x10]; 11848 u8 op_mod[0x10]; 11849 11850 u8 reserved_at_40[0x40]; 11851 11852 struct mlx5_ifc_uctx_bits uctx; 11853 }; 11854 11855 struct mlx5_ifc_create_uctx_out_bits { 11856 u8 status[0x8]; 11857 u8 reserved_at_8[0x18]; 11858 11859 u8 syndrome[0x20]; 11860 11861 u8 reserved_at_40[0x10]; 11862 u8 uid[0x10]; 11863 11864 u8 reserved_at_60[0x20]; 11865 }; 11866 11867 struct mlx5_ifc_destroy_uctx_in_bits { 11868 u8 opcode[0x10]; 11869 u8 reserved_at_10[0x10]; 11870 11871 u8 reserved_at_20[0x10]; 11872 u8 op_mod[0x10]; 11873 11874 u8 reserved_at_40[0x10]; 11875 u8 uid[0x10]; 11876 11877 u8 reserved_at_60[0x20]; 11878 }; 11879 11880 struct mlx5_ifc_destroy_uctx_out_bits { 11881 u8 status[0x8]; 11882 u8 reserved_at_8[0x18]; 11883 11884 u8 syndrome[0x20]; 11885 11886 u8 reserved_at_40[0x40]; 11887 }; 11888 11889 struct mlx5_ifc_create_sw_icm_in_bits { 11890 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 11891 struct mlx5_ifc_sw_icm_bits sw_icm; 11892 }; 11893 11894 struct mlx5_ifc_create_geneve_tlv_option_in_bits { 11895 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 11896 struct mlx5_ifc_geneve_tlv_option_bits geneve_tlv_opt; 11897 }; 11898 11899 struct mlx5_ifc_mtrc_string_db_param_bits { 11900 u8 string_db_base_address[0x20]; 11901 11902 u8 reserved_at_20[0x8]; 11903 u8 string_db_size[0x18]; 11904 }; 11905 11906 struct mlx5_ifc_mtrc_cap_bits { 11907 u8 trace_owner[0x1]; 11908 u8 trace_to_memory[0x1]; 11909 u8 reserved_at_2[0x4]; 11910 u8 trc_ver[0x2]; 11911 u8 reserved_at_8[0x14]; 11912 u8 num_string_db[0x4]; 11913 11914 u8 first_string_trace[0x8]; 11915 u8 num_string_trace[0x8]; 11916 u8 reserved_at_30[0x28]; 11917 11918 u8 log_max_trace_buffer_size[0x8]; 11919 11920 u8 reserved_at_60[0x20]; 11921 11922 struct mlx5_ifc_mtrc_string_db_param_bits string_db_param[8]; 11923 11924 u8 reserved_at_280[0x180]; 11925 }; 11926 11927 struct mlx5_ifc_mtrc_conf_bits { 11928 u8 reserved_at_0[0x1c]; 11929 u8 trace_mode[0x4]; 11930 u8 reserved_at_20[0x18]; 11931 u8 log_trace_buffer_size[0x8]; 11932 u8 trace_mkey[0x20]; 11933 u8 reserved_at_60[0x3a0]; 11934 }; 11935 11936 struct mlx5_ifc_mtrc_stdb_bits { 11937 u8 string_db_index[0x4]; 11938 u8 reserved_at_4[0x4]; 11939 u8 read_size[0x18]; 11940 u8 start_offset[0x20]; 11941 u8 string_db_data[]; 11942 }; 11943 11944 struct mlx5_ifc_mtrc_ctrl_bits { 11945 u8 trace_status[0x2]; 11946 u8 reserved_at_2[0x2]; 11947 u8 arm_event[0x1]; 11948 u8 reserved_at_5[0xb]; 11949 u8 modify_field_select[0x10]; 11950 u8 reserved_at_20[0x2b]; 11951 u8 current_timestamp52_32[0x15]; 11952 u8 current_timestamp31_0[0x20]; 11953 u8 reserved_at_80[0x180]; 11954 }; 11955 11956 struct mlx5_ifc_host_params_context_bits { 11957 u8 host_number[0x8]; 11958 u8 reserved_at_8[0x7]; 11959 u8 host_pf_disabled[0x1]; 11960 u8 host_num_of_vfs[0x10]; 11961 11962 u8 host_total_vfs[0x10]; 11963 u8 host_pci_bus[0x10]; 11964 11965 u8 reserved_at_40[0x10]; 11966 u8 host_pci_device[0x10]; 11967 11968 u8 reserved_at_60[0x10]; 11969 u8 host_pci_function[0x10]; 11970 11971 u8 reserved_at_80[0x180]; 11972 }; 11973 11974 struct mlx5_ifc_query_esw_functions_in_bits { 11975 u8 opcode[0x10]; 11976 u8 reserved_at_10[0x10]; 11977 11978 u8 reserved_at_20[0x10]; 11979 u8 op_mod[0x10]; 11980 11981 u8 reserved_at_40[0x40]; 11982 }; 11983 11984 struct mlx5_ifc_query_esw_functions_out_bits { 11985 u8 status[0x8]; 11986 u8 reserved_at_8[0x18]; 11987 11988 u8 syndrome[0x20]; 11989 11990 u8 reserved_at_40[0x40]; 11991 11992 struct mlx5_ifc_host_params_context_bits host_params_context; 11993 11994 u8 reserved_at_280[0x180]; 11995 u8 host_sf_enable[][0x40]; 11996 }; 11997 11998 struct mlx5_ifc_sf_partition_bits { 11999 u8 reserved_at_0[0x10]; 12000 u8 log_num_sf[0x8]; 12001 u8 log_sf_bar_size[0x8]; 12002 }; 12003 12004 struct mlx5_ifc_query_sf_partitions_out_bits { 12005 u8 status[0x8]; 12006 u8 reserved_at_8[0x18]; 12007 12008 u8 syndrome[0x20]; 12009 12010 u8 reserved_at_40[0x18]; 12011 u8 num_sf_partitions[0x8]; 12012 12013 u8 reserved_at_60[0x20]; 12014 12015 struct mlx5_ifc_sf_partition_bits sf_partition[]; 12016 }; 12017 12018 struct mlx5_ifc_query_sf_partitions_in_bits { 12019 u8 opcode[0x10]; 12020 u8 reserved_at_10[0x10]; 12021 12022 u8 reserved_at_20[0x10]; 12023 u8 op_mod[0x10]; 12024 12025 u8 reserved_at_40[0x40]; 12026 }; 12027 12028 struct mlx5_ifc_dealloc_sf_out_bits { 12029 u8 status[0x8]; 12030 u8 reserved_at_8[0x18]; 12031 12032 u8 syndrome[0x20]; 12033 12034 u8 reserved_at_40[0x40]; 12035 }; 12036 12037 struct mlx5_ifc_dealloc_sf_in_bits { 12038 u8 opcode[0x10]; 12039 u8 reserved_at_10[0x10]; 12040 12041 u8 reserved_at_20[0x10]; 12042 u8 op_mod[0x10]; 12043 12044 u8 reserved_at_40[0x10]; 12045 u8 function_id[0x10]; 12046 12047 u8 reserved_at_60[0x20]; 12048 }; 12049 12050 struct mlx5_ifc_alloc_sf_out_bits { 12051 u8 status[0x8]; 12052 u8 reserved_at_8[0x18]; 12053 12054 u8 syndrome[0x20]; 12055 12056 u8 reserved_at_40[0x40]; 12057 }; 12058 12059 struct mlx5_ifc_alloc_sf_in_bits { 12060 u8 opcode[0x10]; 12061 u8 reserved_at_10[0x10]; 12062 12063 u8 reserved_at_20[0x10]; 12064 u8 op_mod[0x10]; 12065 12066 u8 reserved_at_40[0x10]; 12067 u8 function_id[0x10]; 12068 12069 u8 reserved_at_60[0x20]; 12070 }; 12071 12072 struct mlx5_ifc_affiliated_event_header_bits { 12073 u8 reserved_at_0[0x10]; 12074 u8 obj_type[0x10]; 12075 12076 u8 obj_id[0x20]; 12077 }; 12078 12079 enum { 12080 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = BIT_ULL(0xc), 12081 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_IPSEC = BIT_ULL(0x13), 12082 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_SAMPLER = BIT_ULL(0x20), 12083 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_FLOW_METER_ASO = BIT_ULL(0x24), 12084 }; 12085 12086 enum { 12087 MLX5_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = 0xc, 12088 MLX5_GENERAL_OBJECT_TYPES_IPSEC = 0x13, 12089 MLX5_GENERAL_OBJECT_TYPES_SAMPLER = 0x20, 12090 MLX5_GENERAL_OBJECT_TYPES_FLOW_METER_ASO = 0x24, 12091 MLX5_GENERAL_OBJECT_TYPES_MACSEC = 0x27, 12092 MLX5_GENERAL_OBJECT_TYPES_INT_KEK = 0x47, 12093 MLX5_GENERAL_OBJECT_TYPES_FLOW_TABLE_ALIAS = 0xff15, 12094 }; 12095 12096 enum { 12097 MLX5_IPSEC_OBJECT_ICV_LEN_16B, 12098 }; 12099 12100 enum { 12101 MLX5_IPSEC_ASO_REG_C_0_1 = 0x0, 12102 MLX5_IPSEC_ASO_REG_C_2_3 = 0x1, 12103 MLX5_IPSEC_ASO_REG_C_4_5 = 0x2, 12104 MLX5_IPSEC_ASO_REG_C_6_7 = 0x3, 12105 }; 12106 12107 enum { 12108 MLX5_IPSEC_ASO_MODE = 0x0, 12109 MLX5_IPSEC_ASO_REPLAY_PROTECTION = 0x1, 12110 MLX5_IPSEC_ASO_INC_SN = 0x2, 12111 }; 12112 12113 enum { 12114 MLX5_IPSEC_ASO_REPLAY_WIN_32BIT = 0x0, 12115 MLX5_IPSEC_ASO_REPLAY_WIN_64BIT = 0x1, 12116 MLX5_IPSEC_ASO_REPLAY_WIN_128BIT = 0x2, 12117 MLX5_IPSEC_ASO_REPLAY_WIN_256BIT = 0x3, 12118 }; 12119 12120 struct mlx5_ifc_ipsec_aso_bits { 12121 u8 valid[0x1]; 12122 u8 reserved_at_201[0x1]; 12123 u8 mode[0x2]; 12124 u8 window_sz[0x2]; 12125 u8 soft_lft_arm[0x1]; 12126 u8 hard_lft_arm[0x1]; 12127 u8 remove_flow_enable[0x1]; 12128 u8 esn_event_arm[0x1]; 12129 u8 reserved_at_20a[0x16]; 12130 12131 u8 remove_flow_pkt_cnt[0x20]; 12132 12133 u8 remove_flow_soft_lft[0x20]; 12134 12135 u8 reserved_at_260[0x80]; 12136 12137 u8 mode_parameter[0x20]; 12138 12139 u8 replay_protection_window[0x100]; 12140 }; 12141 12142 struct mlx5_ifc_ipsec_obj_bits { 12143 u8 modify_field_select[0x40]; 12144 u8 full_offload[0x1]; 12145 u8 reserved_at_41[0x1]; 12146 u8 esn_en[0x1]; 12147 u8 esn_overlap[0x1]; 12148 u8 reserved_at_44[0x2]; 12149 u8 icv_length[0x2]; 12150 u8 reserved_at_48[0x4]; 12151 u8 aso_return_reg[0x4]; 12152 u8 reserved_at_50[0x10]; 12153 12154 u8 esn_msb[0x20]; 12155 12156 u8 reserved_at_80[0x8]; 12157 u8 dekn[0x18]; 12158 12159 u8 salt[0x20]; 12160 12161 u8 implicit_iv[0x40]; 12162 12163 u8 reserved_at_100[0x8]; 12164 u8 ipsec_aso_access_pd[0x18]; 12165 u8 reserved_at_120[0xe0]; 12166 12167 struct mlx5_ifc_ipsec_aso_bits ipsec_aso; 12168 }; 12169 12170 struct mlx5_ifc_create_ipsec_obj_in_bits { 12171 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12172 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 12173 }; 12174 12175 enum { 12176 MLX5_MODIFY_IPSEC_BITMASK_ESN_OVERLAP = BIT(0), 12177 MLX5_MODIFY_IPSEC_BITMASK_ESN_MSB = BIT(1), 12178 }; 12179 12180 struct mlx5_ifc_query_ipsec_obj_out_bits { 12181 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 12182 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 12183 }; 12184 12185 struct mlx5_ifc_modify_ipsec_obj_in_bits { 12186 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12187 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 12188 }; 12189 12190 enum { 12191 MLX5_MACSEC_ASO_REPLAY_PROTECTION = 0x1, 12192 }; 12193 12194 enum { 12195 MLX5_MACSEC_ASO_REPLAY_WIN_32BIT = 0x0, 12196 MLX5_MACSEC_ASO_REPLAY_WIN_64BIT = 0x1, 12197 MLX5_MACSEC_ASO_REPLAY_WIN_128BIT = 0x2, 12198 MLX5_MACSEC_ASO_REPLAY_WIN_256BIT = 0x3, 12199 }; 12200 12201 #define MLX5_MACSEC_ASO_INC_SN 0x2 12202 #define MLX5_MACSEC_ASO_REG_C_4_5 0x2 12203 12204 struct mlx5_ifc_macsec_aso_bits { 12205 u8 valid[0x1]; 12206 u8 reserved_at_1[0x1]; 12207 u8 mode[0x2]; 12208 u8 window_size[0x2]; 12209 u8 soft_lifetime_arm[0x1]; 12210 u8 hard_lifetime_arm[0x1]; 12211 u8 remove_flow_enable[0x1]; 12212 u8 epn_event_arm[0x1]; 12213 u8 reserved_at_a[0x16]; 12214 12215 u8 remove_flow_packet_count[0x20]; 12216 12217 u8 remove_flow_soft_lifetime[0x20]; 12218 12219 u8 reserved_at_60[0x80]; 12220 12221 u8 mode_parameter[0x20]; 12222 12223 u8 replay_protection_window[8][0x20]; 12224 }; 12225 12226 struct mlx5_ifc_macsec_offload_obj_bits { 12227 u8 modify_field_select[0x40]; 12228 12229 u8 confidentiality_en[0x1]; 12230 u8 reserved_at_41[0x1]; 12231 u8 epn_en[0x1]; 12232 u8 epn_overlap[0x1]; 12233 u8 reserved_at_44[0x2]; 12234 u8 confidentiality_offset[0x2]; 12235 u8 reserved_at_48[0x4]; 12236 u8 aso_return_reg[0x4]; 12237 u8 reserved_at_50[0x10]; 12238 12239 u8 epn_msb[0x20]; 12240 12241 u8 reserved_at_80[0x8]; 12242 u8 dekn[0x18]; 12243 12244 u8 reserved_at_a0[0x20]; 12245 12246 u8 sci[0x40]; 12247 12248 u8 reserved_at_100[0x8]; 12249 u8 macsec_aso_access_pd[0x18]; 12250 12251 u8 reserved_at_120[0x60]; 12252 12253 u8 salt[3][0x20]; 12254 12255 u8 reserved_at_1e0[0x20]; 12256 12257 struct mlx5_ifc_macsec_aso_bits macsec_aso; 12258 }; 12259 12260 struct mlx5_ifc_create_macsec_obj_in_bits { 12261 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12262 struct mlx5_ifc_macsec_offload_obj_bits macsec_object; 12263 }; 12264 12265 struct mlx5_ifc_modify_macsec_obj_in_bits { 12266 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12267 struct mlx5_ifc_macsec_offload_obj_bits macsec_object; 12268 }; 12269 12270 enum { 12271 MLX5_MODIFY_MACSEC_BITMASK_EPN_OVERLAP = BIT(0), 12272 MLX5_MODIFY_MACSEC_BITMASK_EPN_MSB = BIT(1), 12273 }; 12274 12275 struct mlx5_ifc_query_macsec_obj_out_bits { 12276 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 12277 struct mlx5_ifc_macsec_offload_obj_bits macsec_object; 12278 }; 12279 12280 struct mlx5_ifc_wrapped_dek_bits { 12281 u8 gcm_iv[0x60]; 12282 12283 u8 reserved_at_60[0x20]; 12284 12285 u8 const0[0x1]; 12286 u8 key_size[0x1]; 12287 u8 reserved_at_82[0x2]; 12288 u8 key2_invalid[0x1]; 12289 u8 reserved_at_85[0x3]; 12290 u8 pd[0x18]; 12291 12292 u8 key_purpose[0x5]; 12293 u8 reserved_at_a5[0x13]; 12294 u8 kek_id[0x8]; 12295 12296 u8 reserved_at_c0[0x40]; 12297 12298 u8 key1[0x8][0x20]; 12299 12300 u8 key2[0x8][0x20]; 12301 12302 u8 reserved_at_300[0x40]; 12303 12304 u8 const1[0x1]; 12305 u8 reserved_at_341[0x1f]; 12306 12307 u8 reserved_at_360[0x20]; 12308 12309 u8 auth_tag[0x80]; 12310 }; 12311 12312 struct mlx5_ifc_encryption_key_obj_bits { 12313 u8 modify_field_select[0x40]; 12314 12315 u8 state[0x8]; 12316 u8 sw_wrapped[0x1]; 12317 u8 reserved_at_49[0xb]; 12318 u8 key_size[0x4]; 12319 u8 reserved_at_58[0x4]; 12320 u8 key_purpose[0x4]; 12321 12322 u8 reserved_at_60[0x8]; 12323 u8 pd[0x18]; 12324 12325 u8 reserved_at_80[0x100]; 12326 12327 u8 opaque[0x40]; 12328 12329 u8 reserved_at_1c0[0x40]; 12330 12331 u8 key[8][0x80]; 12332 12333 u8 sw_wrapped_dek[8][0x80]; 12334 12335 u8 reserved_at_a00[0x600]; 12336 }; 12337 12338 struct mlx5_ifc_create_encryption_key_in_bits { 12339 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12340 struct mlx5_ifc_encryption_key_obj_bits encryption_key_object; 12341 }; 12342 12343 struct mlx5_ifc_modify_encryption_key_in_bits { 12344 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12345 struct mlx5_ifc_encryption_key_obj_bits encryption_key_object; 12346 }; 12347 12348 enum { 12349 MLX5_FLOW_METER_MODE_BYTES_IP_LENGTH = 0x0, 12350 MLX5_FLOW_METER_MODE_BYTES_CALC_WITH_L2 = 0x1, 12351 MLX5_FLOW_METER_MODE_BYTES_CALC_WITH_L2_IPG = 0x2, 12352 MLX5_FLOW_METER_MODE_NUM_PACKETS = 0x3, 12353 }; 12354 12355 struct mlx5_ifc_flow_meter_parameters_bits { 12356 u8 valid[0x1]; 12357 u8 bucket_overflow[0x1]; 12358 u8 start_color[0x2]; 12359 u8 both_buckets_on_green[0x1]; 12360 u8 reserved_at_5[0x1]; 12361 u8 meter_mode[0x2]; 12362 u8 reserved_at_8[0x18]; 12363 12364 u8 reserved_at_20[0x20]; 12365 12366 u8 reserved_at_40[0x3]; 12367 u8 cbs_exponent[0x5]; 12368 u8 cbs_mantissa[0x8]; 12369 u8 reserved_at_50[0x3]; 12370 u8 cir_exponent[0x5]; 12371 u8 cir_mantissa[0x8]; 12372 12373 u8 reserved_at_60[0x20]; 12374 12375 u8 reserved_at_80[0x3]; 12376 u8 ebs_exponent[0x5]; 12377 u8 ebs_mantissa[0x8]; 12378 u8 reserved_at_90[0x3]; 12379 u8 eir_exponent[0x5]; 12380 u8 eir_mantissa[0x8]; 12381 12382 u8 reserved_at_a0[0x60]; 12383 }; 12384 12385 struct mlx5_ifc_flow_meter_aso_obj_bits { 12386 u8 modify_field_select[0x40]; 12387 12388 u8 reserved_at_40[0x40]; 12389 12390 u8 reserved_at_80[0x8]; 12391 u8 meter_aso_access_pd[0x18]; 12392 12393 u8 reserved_at_a0[0x160]; 12394 12395 struct mlx5_ifc_flow_meter_parameters_bits flow_meter_parameters[2]; 12396 }; 12397 12398 struct mlx5_ifc_create_flow_meter_aso_obj_in_bits { 12399 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 12400 struct mlx5_ifc_flow_meter_aso_obj_bits flow_meter_aso_obj; 12401 }; 12402 12403 struct mlx5_ifc_int_kek_obj_bits { 12404 u8 modify_field_select[0x40]; 12405 12406 u8 state[0x8]; 12407 u8 auto_gen[0x1]; 12408 u8 reserved_at_49[0xb]; 12409 u8 key_size[0x4]; 12410 u8 reserved_at_58[0x8]; 12411 12412 u8 reserved_at_60[0x8]; 12413 u8 pd[0x18]; 12414 12415 u8 reserved_at_80[0x180]; 12416 u8 key[8][0x80]; 12417 12418 u8 reserved_at_600[0x200]; 12419 }; 12420 12421 struct mlx5_ifc_create_int_kek_obj_in_bits { 12422 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12423 struct mlx5_ifc_int_kek_obj_bits int_kek_object; 12424 }; 12425 12426 struct mlx5_ifc_create_int_kek_obj_out_bits { 12427 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 12428 struct mlx5_ifc_int_kek_obj_bits int_kek_object; 12429 }; 12430 12431 struct mlx5_ifc_sampler_obj_bits { 12432 u8 modify_field_select[0x40]; 12433 12434 u8 table_type[0x8]; 12435 u8 level[0x8]; 12436 u8 reserved_at_50[0xf]; 12437 u8 ignore_flow_level[0x1]; 12438 12439 u8 sample_ratio[0x20]; 12440 12441 u8 reserved_at_80[0x8]; 12442 u8 sample_table_id[0x18]; 12443 12444 u8 reserved_at_a0[0x8]; 12445 u8 default_table_id[0x18]; 12446 12447 u8 sw_steering_icm_address_rx[0x40]; 12448 u8 sw_steering_icm_address_tx[0x40]; 12449 12450 u8 reserved_at_140[0xa0]; 12451 }; 12452 12453 struct mlx5_ifc_create_sampler_obj_in_bits { 12454 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12455 struct mlx5_ifc_sampler_obj_bits sampler_object; 12456 }; 12457 12458 struct mlx5_ifc_query_sampler_obj_out_bits { 12459 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 12460 struct mlx5_ifc_sampler_obj_bits sampler_object; 12461 }; 12462 12463 enum { 12464 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_128 = 0x0, 12465 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_256 = 0x1, 12466 }; 12467 12468 enum { 12469 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_PURPOSE_TLS = 0x1, 12470 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_PURPOSE_IPSEC = 0x2, 12471 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_PURPOSE_MACSEC = 0x4, 12472 }; 12473 12474 struct mlx5_ifc_tls_static_params_bits { 12475 u8 const_2[0x2]; 12476 u8 tls_version[0x4]; 12477 u8 const_1[0x2]; 12478 u8 reserved_at_8[0x14]; 12479 u8 encryption_standard[0x4]; 12480 12481 u8 reserved_at_20[0x20]; 12482 12483 u8 initial_record_number[0x40]; 12484 12485 u8 resync_tcp_sn[0x20]; 12486 12487 u8 gcm_iv[0x20]; 12488 12489 u8 implicit_iv[0x40]; 12490 12491 u8 reserved_at_100[0x8]; 12492 u8 dek_index[0x18]; 12493 12494 u8 reserved_at_120[0xe0]; 12495 }; 12496 12497 struct mlx5_ifc_tls_progress_params_bits { 12498 u8 next_record_tcp_sn[0x20]; 12499 12500 u8 hw_resync_tcp_sn[0x20]; 12501 12502 u8 record_tracker_state[0x2]; 12503 u8 auth_state[0x2]; 12504 u8 reserved_at_44[0x4]; 12505 u8 hw_offset_record_number[0x18]; 12506 }; 12507 12508 enum { 12509 MLX5_MTT_PERM_READ = 1 << 0, 12510 MLX5_MTT_PERM_WRITE = 1 << 1, 12511 MLX5_MTT_PERM_RW = MLX5_MTT_PERM_READ | MLX5_MTT_PERM_WRITE, 12512 }; 12513 12514 enum { 12515 MLX5_SUSPEND_VHCA_IN_OP_MOD_SUSPEND_INITIATOR = 0x0, 12516 MLX5_SUSPEND_VHCA_IN_OP_MOD_SUSPEND_RESPONDER = 0x1, 12517 }; 12518 12519 struct mlx5_ifc_suspend_vhca_in_bits { 12520 u8 opcode[0x10]; 12521 u8 uid[0x10]; 12522 12523 u8 reserved_at_20[0x10]; 12524 u8 op_mod[0x10]; 12525 12526 u8 reserved_at_40[0x10]; 12527 u8 vhca_id[0x10]; 12528 12529 u8 reserved_at_60[0x20]; 12530 }; 12531 12532 struct mlx5_ifc_suspend_vhca_out_bits { 12533 u8 status[0x8]; 12534 u8 reserved_at_8[0x18]; 12535 12536 u8 syndrome[0x20]; 12537 12538 u8 reserved_at_40[0x40]; 12539 }; 12540 12541 enum { 12542 MLX5_RESUME_VHCA_IN_OP_MOD_RESUME_RESPONDER = 0x0, 12543 MLX5_RESUME_VHCA_IN_OP_MOD_RESUME_INITIATOR = 0x1, 12544 }; 12545 12546 struct mlx5_ifc_resume_vhca_in_bits { 12547 u8 opcode[0x10]; 12548 u8 uid[0x10]; 12549 12550 u8 reserved_at_20[0x10]; 12551 u8 op_mod[0x10]; 12552 12553 u8 reserved_at_40[0x10]; 12554 u8 vhca_id[0x10]; 12555 12556 u8 reserved_at_60[0x20]; 12557 }; 12558 12559 struct mlx5_ifc_resume_vhca_out_bits { 12560 u8 status[0x8]; 12561 u8 reserved_at_8[0x18]; 12562 12563 u8 syndrome[0x20]; 12564 12565 u8 reserved_at_40[0x40]; 12566 }; 12567 12568 struct mlx5_ifc_query_vhca_migration_state_in_bits { 12569 u8 opcode[0x10]; 12570 u8 uid[0x10]; 12571 12572 u8 reserved_at_20[0x10]; 12573 u8 op_mod[0x10]; 12574 12575 u8 incremental[0x1]; 12576 u8 chunk[0x1]; 12577 u8 reserved_at_42[0xe]; 12578 u8 vhca_id[0x10]; 12579 12580 u8 reserved_at_60[0x20]; 12581 }; 12582 12583 struct mlx5_ifc_query_vhca_migration_state_out_bits { 12584 u8 status[0x8]; 12585 u8 reserved_at_8[0x18]; 12586 12587 u8 syndrome[0x20]; 12588 12589 u8 reserved_at_40[0x40]; 12590 12591 u8 required_umem_size[0x20]; 12592 12593 u8 reserved_at_a0[0x20]; 12594 12595 u8 remaining_total_size[0x40]; 12596 12597 u8 reserved_at_100[0x100]; 12598 }; 12599 12600 struct mlx5_ifc_save_vhca_state_in_bits { 12601 u8 opcode[0x10]; 12602 u8 uid[0x10]; 12603 12604 u8 reserved_at_20[0x10]; 12605 u8 op_mod[0x10]; 12606 12607 u8 incremental[0x1]; 12608 u8 set_track[0x1]; 12609 u8 reserved_at_42[0xe]; 12610 u8 vhca_id[0x10]; 12611 12612 u8 reserved_at_60[0x20]; 12613 12614 u8 va[0x40]; 12615 12616 u8 mkey[0x20]; 12617 12618 u8 size[0x20]; 12619 }; 12620 12621 struct mlx5_ifc_save_vhca_state_out_bits { 12622 u8 status[0x8]; 12623 u8 reserved_at_8[0x18]; 12624 12625 u8 syndrome[0x20]; 12626 12627 u8 actual_image_size[0x20]; 12628 12629 u8 next_required_umem_size[0x20]; 12630 }; 12631 12632 struct mlx5_ifc_load_vhca_state_in_bits { 12633 u8 opcode[0x10]; 12634 u8 uid[0x10]; 12635 12636 u8 reserved_at_20[0x10]; 12637 u8 op_mod[0x10]; 12638 12639 u8 reserved_at_40[0x10]; 12640 u8 vhca_id[0x10]; 12641 12642 u8 reserved_at_60[0x20]; 12643 12644 u8 va[0x40]; 12645 12646 u8 mkey[0x20]; 12647 12648 u8 size[0x20]; 12649 }; 12650 12651 struct mlx5_ifc_load_vhca_state_out_bits { 12652 u8 status[0x8]; 12653 u8 reserved_at_8[0x18]; 12654 12655 u8 syndrome[0x20]; 12656 12657 u8 reserved_at_40[0x40]; 12658 }; 12659 12660 struct mlx5_ifc_adv_virtualization_cap_bits { 12661 u8 reserved_at_0[0x3]; 12662 u8 pg_track_log_max_num[0x5]; 12663 u8 pg_track_max_num_range[0x8]; 12664 u8 pg_track_log_min_addr_space[0x8]; 12665 u8 pg_track_log_max_addr_space[0x8]; 12666 12667 u8 reserved_at_20[0x3]; 12668 u8 pg_track_log_min_msg_size[0x5]; 12669 u8 reserved_at_28[0x3]; 12670 u8 pg_track_log_max_msg_size[0x5]; 12671 u8 reserved_at_30[0x3]; 12672 u8 pg_track_log_min_page_size[0x5]; 12673 u8 reserved_at_38[0x3]; 12674 u8 pg_track_log_max_page_size[0x5]; 12675 12676 u8 reserved_at_40[0x7c0]; 12677 }; 12678 12679 struct mlx5_ifc_page_track_report_entry_bits { 12680 u8 dirty_address_high[0x20]; 12681 12682 u8 dirty_address_low[0x20]; 12683 }; 12684 12685 enum { 12686 MLX5_PAGE_TRACK_STATE_TRACKING, 12687 MLX5_PAGE_TRACK_STATE_REPORTING, 12688 MLX5_PAGE_TRACK_STATE_ERROR, 12689 }; 12690 12691 struct mlx5_ifc_page_track_range_bits { 12692 u8 start_address[0x40]; 12693 12694 u8 length[0x40]; 12695 }; 12696 12697 struct mlx5_ifc_page_track_bits { 12698 u8 modify_field_select[0x40]; 12699 12700 u8 reserved_at_40[0x10]; 12701 u8 vhca_id[0x10]; 12702 12703 u8 reserved_at_60[0x20]; 12704 12705 u8 state[0x4]; 12706 u8 track_type[0x4]; 12707 u8 log_addr_space_size[0x8]; 12708 u8 reserved_at_90[0x3]; 12709 u8 log_page_size[0x5]; 12710 u8 reserved_at_98[0x3]; 12711 u8 log_msg_size[0x5]; 12712 12713 u8 reserved_at_a0[0x8]; 12714 u8 reporting_qpn[0x18]; 12715 12716 u8 reserved_at_c0[0x18]; 12717 u8 num_ranges[0x8]; 12718 12719 u8 reserved_at_e0[0x20]; 12720 12721 u8 range_start_address[0x40]; 12722 12723 u8 length[0x40]; 12724 12725 struct mlx5_ifc_page_track_range_bits track_range[0]; 12726 }; 12727 12728 struct mlx5_ifc_create_page_track_obj_in_bits { 12729 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12730 struct mlx5_ifc_page_track_bits obj_context; 12731 }; 12732 12733 struct mlx5_ifc_modify_page_track_obj_in_bits { 12734 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12735 struct mlx5_ifc_page_track_bits obj_context; 12736 }; 12737 12738 struct mlx5_ifc_query_page_track_obj_out_bits { 12739 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 12740 struct mlx5_ifc_page_track_bits obj_context; 12741 }; 12742 12743 struct mlx5_ifc_msecq_reg_bits { 12744 u8 reserved_at_0[0x20]; 12745 12746 u8 reserved_at_20[0x12]; 12747 u8 network_option[0x2]; 12748 u8 local_ssm_code[0x4]; 12749 u8 local_enhanced_ssm_code[0x8]; 12750 12751 u8 local_clock_identity[0x40]; 12752 12753 u8 reserved_at_80[0x180]; 12754 }; 12755 12756 enum { 12757 MLX5_MSEES_FIELD_SELECT_ENABLE = BIT(0), 12758 MLX5_MSEES_FIELD_SELECT_ADMIN_STATUS = BIT(1), 12759 MLX5_MSEES_FIELD_SELECT_ADMIN_FREQ_MEASURE = BIT(2), 12760 }; 12761 12762 enum mlx5_msees_admin_status { 12763 MLX5_MSEES_ADMIN_STATUS_FREE_RUNNING = 0x0, 12764 MLX5_MSEES_ADMIN_STATUS_TRACK = 0x1, 12765 }; 12766 12767 enum mlx5_msees_oper_status { 12768 MLX5_MSEES_OPER_STATUS_FREE_RUNNING = 0x0, 12769 MLX5_MSEES_OPER_STATUS_SELF_TRACK = 0x1, 12770 MLX5_MSEES_OPER_STATUS_OTHER_TRACK = 0x2, 12771 MLX5_MSEES_OPER_STATUS_HOLDOVER = 0x3, 12772 MLX5_MSEES_OPER_STATUS_FAIL_HOLDOVER = 0x4, 12773 MLX5_MSEES_OPER_STATUS_FAIL_FREE_RUNNING = 0x5, 12774 }; 12775 12776 enum mlx5_msees_failure_reason { 12777 MLX5_MSEES_FAILURE_REASON_UNDEFINED_ERROR = 0x0, 12778 MLX5_MSEES_FAILURE_REASON_PORT_DOWN = 0x1, 12779 MLX5_MSEES_FAILURE_REASON_TOO_HIGH_FREQUENCY_DIFF = 0x2, 12780 MLX5_MSEES_FAILURE_REASON_NET_SYNCHRONIZER_DEVICE_ERROR = 0x3, 12781 MLX5_MSEES_FAILURE_REASON_LACK_OF_RESOURCES = 0x4, 12782 }; 12783 12784 struct mlx5_ifc_msees_reg_bits { 12785 u8 reserved_at_0[0x8]; 12786 u8 local_port[0x8]; 12787 u8 pnat[0x2]; 12788 u8 lp_msb[0x2]; 12789 u8 reserved_at_14[0xc]; 12790 12791 u8 field_select[0x20]; 12792 12793 u8 admin_status[0x4]; 12794 u8 oper_status[0x4]; 12795 u8 ho_acq[0x1]; 12796 u8 reserved_at_49[0xc]; 12797 u8 admin_freq_measure[0x1]; 12798 u8 oper_freq_measure[0x1]; 12799 u8 failure_reason[0x9]; 12800 12801 u8 frequency_diff[0x20]; 12802 12803 u8 reserved_at_80[0x180]; 12804 }; 12805 12806 #endif /* MLX5_IFC_H */ 12807