xref: /linux/include/linux/mlx5/mlx5_ifc.h (revision 67f9c312b0a7f4bc869376d2a68308e673235954) 
1 /*
2  * Copyright (c) 2013-2015, Mellanox Technologies, Ltd.  All rights reserved.
3  *
4  * This software is available to you under a choice of one of two
5  * licenses.  You may choose to be licensed under the terms of the GNU
6  * General Public License (GPL) Version 2, available from the file
7  * COPYING in the main directory of this source tree, or the
8  * OpenIB.org BSD license below:
9  *
10  *     Redistribution and use in source and binary forms, with or
11  *     without modification, are permitted provided that the following
12  *     conditions are met:
13  *
14  *      - Redistributions of source code must retain the above
15  *        copyright notice, this list of conditions and the following
16  *        disclaimer.
17  *
18  *      - Redistributions in binary form must reproduce the above
19  *        copyright notice, this list of conditions and the following
20  *        disclaimer in the documentation and/or other materials
21  *        provided with the distribution.
22  *
23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30  * SOFTWARE.
31 */
32 #ifndef MLX5_IFC_H
33 #define MLX5_IFC_H
34 
35 #include "mlx5_ifc_fpga.h"
36 
37 enum {
38 	MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS                   = 0x0,
39 	MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED             = 0x1,
40 	MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED           = 0x2,
41 	MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED                  = 0x3,
42 	MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED                    = 0x13,
43 	MLX5_EVENT_TYPE_CODING_SRQ_LIMIT                           = 0x14,
44 	MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED          = 0x1c,
45 	MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION            = 0x1d,
46 	MLX5_EVENT_TYPE_CODING_CQ_ERROR                            = 0x4,
47 	MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR         = 0x5,
48 	MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED               = 0x7,
49 	MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT                    = 0xc,
50 	MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR      = 0x10,
51 	MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR     = 0x11,
52 	MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR        = 0x12,
53 	MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR                      = 0x8,
54 	MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE                   = 0x9,
55 	MLX5_EVENT_TYPE_CODING_GPIO_EVENT                          = 0x15,
56 	MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19,
57 	MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a,
58 	MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT                      = 0x1b,
59 	MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT         = 0x1f,
60 	MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION        = 0xa,
61 	MLX5_EVENT_TYPE_CODING_PAGE_REQUEST                        = 0xb,
62 	MLX5_EVENT_TYPE_CODING_FPGA_ERROR                          = 0x20,
63 	MLX5_EVENT_TYPE_CODING_FPGA_QP_ERROR                       = 0x21
64 };
65 
66 enum {
67 	MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE        = 0x0,
68 	MLX5_SET_HCA_CAP_OP_MOD_ETHERNET_OFFLOADS     = 0x1,
69 	MLX5_SET_HCA_CAP_OP_MOD_ODP                   = 0x2,
70 	MLX5_SET_HCA_CAP_OP_MOD_ATOMIC                = 0x3,
71 	MLX5_SET_HCA_CAP_OP_MOD_ROCE                  = 0x4,
72 	MLX5_SET_HCA_CAP_OP_MOD_IPSEC                 = 0x15,
73 	MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE2       = 0x20,
74 	MLX5_SET_HCA_CAP_OP_MOD_PORT_SELECTION        = 0x25,
75 };
76 
77 enum {
78 	MLX5_SHARED_RESOURCE_UID = 0xffff,
79 };
80 
81 enum {
82 	MLX5_OBJ_TYPE_SW_ICM = 0x0008,
83 	MLX5_OBJ_TYPE_HEADER_MODIFY_ARGUMENT  = 0x23,
84 };
85 
86 enum {
87 	MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM = (1ULL << MLX5_OBJ_TYPE_SW_ICM),
88 	MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT = (1ULL << 11),
89 	MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q = (1ULL << 13),
90 	MLX5_GENERAL_OBJ_TYPES_CAP_HEADER_MODIFY_ARGUMENT =
91 		(1ULL << MLX5_OBJ_TYPE_HEADER_MODIFY_ARGUMENT),
92 	MLX5_GENERAL_OBJ_TYPES_CAP_MACSEC_OFFLOAD = (1ULL << 39),
93 };
94 
95 enum {
96 	MLX5_OBJ_TYPE_GENEVE_TLV_OPT = 0x000b,
97 	MLX5_OBJ_TYPE_VIRTIO_NET_Q = 0x000d,
98 	MLX5_OBJ_TYPE_VIRTIO_Q_COUNTERS = 0x001c,
99 	MLX5_OBJ_TYPE_MATCH_DEFINER = 0x0018,
100 	MLX5_OBJ_TYPE_PAGE_TRACK = 0x46,
101 	MLX5_OBJ_TYPE_MKEY = 0xff01,
102 	MLX5_OBJ_TYPE_QP = 0xff02,
103 	MLX5_OBJ_TYPE_PSV = 0xff03,
104 	MLX5_OBJ_TYPE_RMP = 0xff04,
105 	MLX5_OBJ_TYPE_XRC_SRQ = 0xff05,
106 	MLX5_OBJ_TYPE_RQ = 0xff06,
107 	MLX5_OBJ_TYPE_SQ = 0xff07,
108 	MLX5_OBJ_TYPE_TIR = 0xff08,
109 	MLX5_OBJ_TYPE_TIS = 0xff09,
110 	MLX5_OBJ_TYPE_DCT = 0xff0a,
111 	MLX5_OBJ_TYPE_XRQ = 0xff0b,
112 	MLX5_OBJ_TYPE_RQT = 0xff0e,
113 	MLX5_OBJ_TYPE_FLOW_COUNTER = 0xff0f,
114 	MLX5_OBJ_TYPE_CQ = 0xff10,
115 };
116 
117 enum {
118 	MLX5_CMD_OP_QUERY_HCA_CAP                 = 0x100,
119 	MLX5_CMD_OP_QUERY_ADAPTER                 = 0x101,
120 	MLX5_CMD_OP_INIT_HCA                      = 0x102,
121 	MLX5_CMD_OP_TEARDOWN_HCA                  = 0x103,
122 	MLX5_CMD_OP_ENABLE_HCA                    = 0x104,
123 	MLX5_CMD_OP_DISABLE_HCA                   = 0x105,
124 	MLX5_CMD_OP_QUERY_PAGES                   = 0x107,
125 	MLX5_CMD_OP_MANAGE_PAGES                  = 0x108,
126 	MLX5_CMD_OP_SET_HCA_CAP                   = 0x109,
127 	MLX5_CMD_OP_QUERY_ISSI                    = 0x10a,
128 	MLX5_CMD_OP_SET_ISSI                      = 0x10b,
129 	MLX5_CMD_OP_SET_DRIVER_VERSION            = 0x10d,
130 	MLX5_CMD_OP_QUERY_SF_PARTITION            = 0x111,
131 	MLX5_CMD_OP_ALLOC_SF                      = 0x113,
132 	MLX5_CMD_OP_DEALLOC_SF                    = 0x114,
133 	MLX5_CMD_OP_SUSPEND_VHCA                  = 0x115,
134 	MLX5_CMD_OP_RESUME_VHCA                   = 0x116,
135 	MLX5_CMD_OP_QUERY_VHCA_MIGRATION_STATE    = 0x117,
136 	MLX5_CMD_OP_SAVE_VHCA_STATE               = 0x118,
137 	MLX5_CMD_OP_LOAD_VHCA_STATE               = 0x119,
138 	MLX5_CMD_OP_CREATE_MKEY                   = 0x200,
139 	MLX5_CMD_OP_QUERY_MKEY                    = 0x201,
140 	MLX5_CMD_OP_DESTROY_MKEY                  = 0x202,
141 	MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS        = 0x203,
142 	MLX5_CMD_OP_PAGE_FAULT_RESUME             = 0x204,
143 	MLX5_CMD_OP_ALLOC_MEMIC                   = 0x205,
144 	MLX5_CMD_OP_DEALLOC_MEMIC                 = 0x206,
145 	MLX5_CMD_OP_MODIFY_MEMIC                  = 0x207,
146 	MLX5_CMD_OP_CREATE_EQ                     = 0x301,
147 	MLX5_CMD_OP_DESTROY_EQ                    = 0x302,
148 	MLX5_CMD_OP_QUERY_EQ                      = 0x303,
149 	MLX5_CMD_OP_GEN_EQE                       = 0x304,
150 	MLX5_CMD_OP_CREATE_CQ                     = 0x400,
151 	MLX5_CMD_OP_DESTROY_CQ                    = 0x401,
152 	MLX5_CMD_OP_QUERY_CQ                      = 0x402,
153 	MLX5_CMD_OP_MODIFY_CQ                     = 0x403,
154 	MLX5_CMD_OP_CREATE_QP                     = 0x500,
155 	MLX5_CMD_OP_DESTROY_QP                    = 0x501,
156 	MLX5_CMD_OP_RST2INIT_QP                   = 0x502,
157 	MLX5_CMD_OP_INIT2RTR_QP                   = 0x503,
158 	MLX5_CMD_OP_RTR2RTS_QP                    = 0x504,
159 	MLX5_CMD_OP_RTS2RTS_QP                    = 0x505,
160 	MLX5_CMD_OP_SQERR2RTS_QP                  = 0x506,
161 	MLX5_CMD_OP_2ERR_QP                       = 0x507,
162 	MLX5_CMD_OP_2RST_QP                       = 0x50a,
163 	MLX5_CMD_OP_QUERY_QP                      = 0x50b,
164 	MLX5_CMD_OP_SQD_RTS_QP                    = 0x50c,
165 	MLX5_CMD_OP_INIT2INIT_QP                  = 0x50e,
166 	MLX5_CMD_OP_CREATE_PSV                    = 0x600,
167 	MLX5_CMD_OP_DESTROY_PSV                   = 0x601,
168 	MLX5_CMD_OP_CREATE_SRQ                    = 0x700,
169 	MLX5_CMD_OP_DESTROY_SRQ                   = 0x701,
170 	MLX5_CMD_OP_QUERY_SRQ                     = 0x702,
171 	MLX5_CMD_OP_ARM_RQ                        = 0x703,
172 	MLX5_CMD_OP_CREATE_XRC_SRQ                = 0x705,
173 	MLX5_CMD_OP_DESTROY_XRC_SRQ               = 0x706,
174 	MLX5_CMD_OP_QUERY_XRC_SRQ                 = 0x707,
175 	MLX5_CMD_OP_ARM_XRC_SRQ                   = 0x708,
176 	MLX5_CMD_OP_CREATE_DCT                    = 0x710,
177 	MLX5_CMD_OP_DESTROY_DCT                   = 0x711,
178 	MLX5_CMD_OP_DRAIN_DCT                     = 0x712,
179 	MLX5_CMD_OP_QUERY_DCT                     = 0x713,
180 	MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION     = 0x714,
181 	MLX5_CMD_OP_CREATE_XRQ                    = 0x717,
182 	MLX5_CMD_OP_DESTROY_XRQ                   = 0x718,
183 	MLX5_CMD_OP_QUERY_XRQ                     = 0x719,
184 	MLX5_CMD_OP_ARM_XRQ                       = 0x71a,
185 	MLX5_CMD_OP_QUERY_XRQ_DC_PARAMS_ENTRY     = 0x725,
186 	MLX5_CMD_OP_SET_XRQ_DC_PARAMS_ENTRY       = 0x726,
187 	MLX5_CMD_OP_QUERY_XRQ_ERROR_PARAMS        = 0x727,
188 	MLX5_CMD_OP_RELEASE_XRQ_ERROR             = 0x729,
189 	MLX5_CMD_OP_MODIFY_XRQ                    = 0x72a,
190 	MLX5_CMD_OP_QUERY_ESW_FUNCTIONS           = 0x740,
191 	MLX5_CMD_OP_QUERY_VPORT_STATE             = 0x750,
192 	MLX5_CMD_OP_MODIFY_VPORT_STATE            = 0x751,
193 	MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT       = 0x752,
194 	MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT      = 0x753,
195 	MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT       = 0x754,
196 	MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT      = 0x755,
197 	MLX5_CMD_OP_QUERY_ROCE_ADDRESS            = 0x760,
198 	MLX5_CMD_OP_SET_ROCE_ADDRESS              = 0x761,
199 	MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT       = 0x762,
200 	MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT      = 0x763,
201 	MLX5_CMD_OP_QUERY_HCA_VPORT_GID           = 0x764,
202 	MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY          = 0x765,
203 	MLX5_CMD_OP_QUERY_VNIC_ENV                = 0x76f,
204 	MLX5_CMD_OP_QUERY_VPORT_COUNTER           = 0x770,
205 	MLX5_CMD_OP_ALLOC_Q_COUNTER               = 0x771,
206 	MLX5_CMD_OP_DEALLOC_Q_COUNTER             = 0x772,
207 	MLX5_CMD_OP_QUERY_Q_COUNTER               = 0x773,
208 	MLX5_CMD_OP_SET_MONITOR_COUNTER           = 0x774,
209 	MLX5_CMD_OP_ARM_MONITOR_COUNTER           = 0x775,
210 	MLX5_CMD_OP_SET_PP_RATE_LIMIT             = 0x780,
211 	MLX5_CMD_OP_QUERY_RATE_LIMIT              = 0x781,
212 	MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT      = 0x782,
213 	MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT     = 0x783,
214 	MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT       = 0x784,
215 	MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT      = 0x785,
216 	MLX5_CMD_OP_CREATE_QOS_PARA_VPORT         = 0x786,
217 	MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT        = 0x787,
218 	MLX5_CMD_OP_ALLOC_PD                      = 0x800,
219 	MLX5_CMD_OP_DEALLOC_PD                    = 0x801,
220 	MLX5_CMD_OP_ALLOC_UAR                     = 0x802,
221 	MLX5_CMD_OP_DEALLOC_UAR                   = 0x803,
222 	MLX5_CMD_OP_CONFIG_INT_MODERATION         = 0x804,
223 	MLX5_CMD_OP_ACCESS_REG                    = 0x805,
224 	MLX5_CMD_OP_ATTACH_TO_MCG                 = 0x806,
225 	MLX5_CMD_OP_DETACH_FROM_MCG               = 0x807,
226 	MLX5_CMD_OP_GET_DROPPED_PACKET_LOG        = 0x80a,
227 	MLX5_CMD_OP_MAD_IFC                       = 0x50d,
228 	MLX5_CMD_OP_QUERY_MAD_DEMUX               = 0x80b,
229 	MLX5_CMD_OP_SET_MAD_DEMUX                 = 0x80c,
230 	MLX5_CMD_OP_NOP                           = 0x80d,
231 	MLX5_CMD_OP_ALLOC_XRCD                    = 0x80e,
232 	MLX5_CMD_OP_DEALLOC_XRCD                  = 0x80f,
233 	MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN        = 0x816,
234 	MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN      = 0x817,
235 	MLX5_CMD_OP_QUERY_CONG_STATUS             = 0x822,
236 	MLX5_CMD_OP_MODIFY_CONG_STATUS            = 0x823,
237 	MLX5_CMD_OP_QUERY_CONG_PARAMS             = 0x824,
238 	MLX5_CMD_OP_MODIFY_CONG_PARAMS            = 0x825,
239 	MLX5_CMD_OP_QUERY_CONG_STATISTICS         = 0x826,
240 	MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT           = 0x827,
241 	MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT        = 0x828,
242 	MLX5_CMD_OP_SET_L2_TABLE_ENTRY            = 0x829,
243 	MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY          = 0x82a,
244 	MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY         = 0x82b,
245 	MLX5_CMD_OP_SET_WOL_ROL                   = 0x830,
246 	MLX5_CMD_OP_QUERY_WOL_ROL                 = 0x831,
247 	MLX5_CMD_OP_CREATE_LAG                    = 0x840,
248 	MLX5_CMD_OP_MODIFY_LAG                    = 0x841,
249 	MLX5_CMD_OP_QUERY_LAG                     = 0x842,
250 	MLX5_CMD_OP_DESTROY_LAG                   = 0x843,
251 	MLX5_CMD_OP_CREATE_VPORT_LAG              = 0x844,
252 	MLX5_CMD_OP_DESTROY_VPORT_LAG             = 0x845,
253 	MLX5_CMD_OP_CREATE_TIR                    = 0x900,
254 	MLX5_CMD_OP_MODIFY_TIR                    = 0x901,
255 	MLX5_CMD_OP_DESTROY_TIR                   = 0x902,
256 	MLX5_CMD_OP_QUERY_TIR                     = 0x903,
257 	MLX5_CMD_OP_CREATE_SQ                     = 0x904,
258 	MLX5_CMD_OP_MODIFY_SQ                     = 0x905,
259 	MLX5_CMD_OP_DESTROY_SQ                    = 0x906,
260 	MLX5_CMD_OP_QUERY_SQ                      = 0x907,
261 	MLX5_CMD_OP_CREATE_RQ                     = 0x908,
262 	MLX5_CMD_OP_MODIFY_RQ                     = 0x909,
263 	MLX5_CMD_OP_SET_DELAY_DROP_PARAMS         = 0x910,
264 	MLX5_CMD_OP_DESTROY_RQ                    = 0x90a,
265 	MLX5_CMD_OP_QUERY_RQ                      = 0x90b,
266 	MLX5_CMD_OP_CREATE_RMP                    = 0x90c,
267 	MLX5_CMD_OP_MODIFY_RMP                    = 0x90d,
268 	MLX5_CMD_OP_DESTROY_RMP                   = 0x90e,
269 	MLX5_CMD_OP_QUERY_RMP                     = 0x90f,
270 	MLX5_CMD_OP_CREATE_TIS                    = 0x912,
271 	MLX5_CMD_OP_MODIFY_TIS                    = 0x913,
272 	MLX5_CMD_OP_DESTROY_TIS                   = 0x914,
273 	MLX5_CMD_OP_QUERY_TIS                     = 0x915,
274 	MLX5_CMD_OP_CREATE_RQT                    = 0x916,
275 	MLX5_CMD_OP_MODIFY_RQT                    = 0x917,
276 	MLX5_CMD_OP_DESTROY_RQT                   = 0x918,
277 	MLX5_CMD_OP_QUERY_RQT                     = 0x919,
278 	MLX5_CMD_OP_SET_FLOW_TABLE_ROOT		  = 0x92f,
279 	MLX5_CMD_OP_CREATE_FLOW_TABLE             = 0x930,
280 	MLX5_CMD_OP_DESTROY_FLOW_TABLE            = 0x931,
281 	MLX5_CMD_OP_QUERY_FLOW_TABLE              = 0x932,
282 	MLX5_CMD_OP_CREATE_FLOW_GROUP             = 0x933,
283 	MLX5_CMD_OP_DESTROY_FLOW_GROUP            = 0x934,
284 	MLX5_CMD_OP_QUERY_FLOW_GROUP              = 0x935,
285 	MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY          = 0x936,
286 	MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY        = 0x937,
287 	MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY       = 0x938,
288 	MLX5_CMD_OP_ALLOC_FLOW_COUNTER            = 0x939,
289 	MLX5_CMD_OP_DEALLOC_FLOW_COUNTER          = 0x93a,
290 	MLX5_CMD_OP_QUERY_FLOW_COUNTER            = 0x93b,
291 	MLX5_CMD_OP_MODIFY_FLOW_TABLE             = 0x93c,
292 	MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT = 0x93d,
293 	MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT = 0x93e,
294 	MLX5_CMD_OP_QUERY_PACKET_REFORMAT_CONTEXT = 0x93f,
295 	MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT   = 0x940,
296 	MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941,
297 	MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT   = 0x942,
298 	MLX5_CMD_OP_FPGA_CREATE_QP                = 0x960,
299 	MLX5_CMD_OP_FPGA_MODIFY_QP                = 0x961,
300 	MLX5_CMD_OP_FPGA_QUERY_QP                 = 0x962,
301 	MLX5_CMD_OP_FPGA_DESTROY_QP               = 0x963,
302 	MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS        = 0x964,
303 	MLX5_CMD_OP_CREATE_GENERAL_OBJECT         = 0xa00,
304 	MLX5_CMD_OP_MODIFY_GENERAL_OBJECT         = 0xa01,
305 	MLX5_CMD_OP_QUERY_GENERAL_OBJECT          = 0xa02,
306 	MLX5_CMD_OP_DESTROY_GENERAL_OBJECT        = 0xa03,
307 	MLX5_CMD_OP_CREATE_UCTX                   = 0xa04,
308 	MLX5_CMD_OP_DESTROY_UCTX                  = 0xa06,
309 	MLX5_CMD_OP_CREATE_UMEM                   = 0xa08,
310 	MLX5_CMD_OP_DESTROY_UMEM                  = 0xa0a,
311 	MLX5_CMD_OP_SYNC_STEERING                 = 0xb00,
312 	MLX5_CMD_OP_QUERY_VHCA_STATE              = 0xb0d,
313 	MLX5_CMD_OP_MODIFY_VHCA_STATE             = 0xb0e,
314 	MLX5_CMD_OP_SYNC_CRYPTO                   = 0xb12,
315 	MLX5_CMD_OP_ALLOW_OTHER_VHCA_ACCESS       = 0xb16,
316 	MLX5_CMD_OP_MAX
317 };
318 
319 /* Valid range for general commands that don't work over an object */
320 enum {
321 	MLX5_CMD_OP_GENERAL_START = 0xb00,
322 	MLX5_CMD_OP_GENERAL_END = 0xd00,
323 };
324 
325 enum {
326 	MLX5_FT_NIC_RX_2_NIC_RX_RDMA = BIT(0),
327 	MLX5_FT_NIC_TX_RDMA_2_NIC_TX = BIT(1),
328 };
329 
330 enum {
331 	MLX5_CMD_OP_MOD_UPDATE_HEADER_MODIFY_ARGUMENT = 0x1,
332 };
333 
334 struct mlx5_ifc_flow_table_fields_supported_bits {
335 	u8         outer_dmac[0x1];
336 	u8         outer_smac[0x1];
337 	u8         outer_ether_type[0x1];
338 	u8         outer_ip_version[0x1];
339 	u8         outer_first_prio[0x1];
340 	u8         outer_first_cfi[0x1];
341 	u8         outer_first_vid[0x1];
342 	u8         outer_ipv4_ttl[0x1];
343 	u8         outer_second_prio[0x1];
344 	u8         outer_second_cfi[0x1];
345 	u8         outer_second_vid[0x1];
346 	u8         reserved_at_b[0x1];
347 	u8         outer_sip[0x1];
348 	u8         outer_dip[0x1];
349 	u8         outer_frag[0x1];
350 	u8         outer_ip_protocol[0x1];
351 	u8         outer_ip_ecn[0x1];
352 	u8         outer_ip_dscp[0x1];
353 	u8         outer_udp_sport[0x1];
354 	u8         outer_udp_dport[0x1];
355 	u8         outer_tcp_sport[0x1];
356 	u8         outer_tcp_dport[0x1];
357 	u8         outer_tcp_flags[0x1];
358 	u8         outer_gre_protocol[0x1];
359 	u8         outer_gre_key[0x1];
360 	u8         outer_vxlan_vni[0x1];
361 	u8         outer_geneve_vni[0x1];
362 	u8         outer_geneve_oam[0x1];
363 	u8         outer_geneve_protocol_type[0x1];
364 	u8         outer_geneve_opt_len[0x1];
365 	u8         source_vhca_port[0x1];
366 	u8         source_eswitch_port[0x1];
367 
368 	u8         inner_dmac[0x1];
369 	u8         inner_smac[0x1];
370 	u8         inner_ether_type[0x1];
371 	u8         inner_ip_version[0x1];
372 	u8         inner_first_prio[0x1];
373 	u8         inner_first_cfi[0x1];
374 	u8         inner_first_vid[0x1];
375 	u8         reserved_at_27[0x1];
376 	u8         inner_second_prio[0x1];
377 	u8         inner_second_cfi[0x1];
378 	u8         inner_second_vid[0x1];
379 	u8         reserved_at_2b[0x1];
380 	u8         inner_sip[0x1];
381 	u8         inner_dip[0x1];
382 	u8         inner_frag[0x1];
383 	u8         inner_ip_protocol[0x1];
384 	u8         inner_ip_ecn[0x1];
385 	u8         inner_ip_dscp[0x1];
386 	u8         inner_udp_sport[0x1];
387 	u8         inner_udp_dport[0x1];
388 	u8         inner_tcp_sport[0x1];
389 	u8         inner_tcp_dport[0x1];
390 	u8         inner_tcp_flags[0x1];
391 	u8         reserved_at_37[0x9];
392 
393 	u8         geneve_tlv_option_0_data[0x1];
394 	u8         geneve_tlv_option_0_exist[0x1];
395 	u8         reserved_at_42[0x3];
396 	u8         outer_first_mpls_over_udp[0x4];
397 	u8         outer_first_mpls_over_gre[0x4];
398 	u8         inner_first_mpls[0x4];
399 	u8         outer_first_mpls[0x4];
400 	u8         reserved_at_55[0x2];
401 	u8	   outer_esp_spi[0x1];
402 	u8         reserved_at_58[0x2];
403 	u8         bth_dst_qp[0x1];
404 	u8         reserved_at_5b[0x5];
405 
406 	u8         reserved_at_60[0x18];
407 	u8         metadata_reg_c_7[0x1];
408 	u8         metadata_reg_c_6[0x1];
409 	u8         metadata_reg_c_5[0x1];
410 	u8         metadata_reg_c_4[0x1];
411 	u8         metadata_reg_c_3[0x1];
412 	u8         metadata_reg_c_2[0x1];
413 	u8         metadata_reg_c_1[0x1];
414 	u8         metadata_reg_c_0[0x1];
415 };
416 
417 /* Table 2170 - Flow Table Fields Supported 2 Format */
418 struct mlx5_ifc_flow_table_fields_supported_2_bits {
419 	u8         reserved_at_0[0x2];
420 	u8         inner_l4_type[0x1];
421 	u8         outer_l4_type[0x1];
422 	u8         reserved_at_4[0xa];
423 	u8         bth_opcode[0x1];
424 	u8         reserved_at_f[0x1];
425 	u8         tunnel_header_0_1[0x1];
426 	u8         reserved_at_11[0xf];
427 
428 	u8         reserved_at_20[0x60];
429 };
430 
431 struct mlx5_ifc_flow_table_prop_layout_bits {
432 	u8         ft_support[0x1];
433 	u8         reserved_at_1[0x1];
434 	u8         flow_counter[0x1];
435 	u8	   flow_modify_en[0x1];
436 	u8         modify_root[0x1];
437 	u8         identified_miss_table_mode[0x1];
438 	u8         flow_table_modify[0x1];
439 	u8         reformat[0x1];
440 	u8         decap[0x1];
441 	u8         reset_root_to_default[0x1];
442 	u8         pop_vlan[0x1];
443 	u8         push_vlan[0x1];
444 	u8         reserved_at_c[0x1];
445 	u8         pop_vlan_2[0x1];
446 	u8         push_vlan_2[0x1];
447 	u8	   reformat_and_vlan_action[0x1];
448 	u8	   reserved_at_10[0x1];
449 	u8         sw_owner[0x1];
450 	u8	   reformat_l3_tunnel_to_l2[0x1];
451 	u8	   reformat_l2_to_l3_tunnel[0x1];
452 	u8	   reformat_and_modify_action[0x1];
453 	u8	   ignore_flow_level[0x1];
454 	u8         reserved_at_16[0x1];
455 	u8	   table_miss_action_domain[0x1];
456 	u8         termination_table[0x1];
457 	u8         reformat_and_fwd_to_table[0x1];
458 	u8         reserved_at_1a[0x2];
459 	u8         ipsec_encrypt[0x1];
460 	u8         ipsec_decrypt[0x1];
461 	u8         sw_owner_v2[0x1];
462 	u8         reserved_at_1f[0x1];
463 
464 	u8         termination_table_raw_traffic[0x1];
465 	u8         reserved_at_21[0x1];
466 	u8         log_max_ft_size[0x6];
467 	u8         log_max_modify_header_context[0x8];
468 	u8         max_modify_header_actions[0x8];
469 	u8         max_ft_level[0x8];
470 
471 	u8         reformat_add_esp_trasport[0x1];
472 	u8         reformat_l2_to_l3_esp_tunnel[0x1];
473 	u8         reformat_add_esp_transport_over_udp[0x1];
474 	u8         reformat_del_esp_trasport[0x1];
475 	u8         reformat_l3_esp_tunnel_to_l2[0x1];
476 	u8         reformat_del_esp_transport_over_udp[0x1];
477 	u8         execute_aso[0x1];
478 	u8         reserved_at_47[0x19];
479 
480 	u8         reserved_at_60[0x2];
481 	u8         reformat_insert[0x1];
482 	u8         reformat_remove[0x1];
483 	u8         macsec_encrypt[0x1];
484 	u8         macsec_decrypt[0x1];
485 	u8         reserved_at_66[0x2];
486 	u8         reformat_add_macsec[0x1];
487 	u8         reformat_remove_macsec[0x1];
488 	u8         reserved_at_6a[0xe];
489 	u8         log_max_ft_num[0x8];
490 
491 	u8         reserved_at_80[0x10];
492 	u8         log_max_flow_counter[0x8];
493 	u8         log_max_destination[0x8];
494 
495 	u8         reserved_at_a0[0x18];
496 	u8         log_max_flow[0x8];
497 
498 	u8         reserved_at_c0[0x40];
499 
500 	struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
501 
502 	struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
503 };
504 
505 struct mlx5_ifc_odp_per_transport_service_cap_bits {
506 	u8         send[0x1];
507 	u8         receive[0x1];
508 	u8         write[0x1];
509 	u8         read[0x1];
510 	u8         atomic[0x1];
511 	u8         srq_receive[0x1];
512 	u8         reserved_at_6[0x1a];
513 };
514 
515 struct mlx5_ifc_ipv4_layout_bits {
516 	u8         reserved_at_0[0x60];
517 
518 	u8         ipv4[0x20];
519 };
520 
521 struct mlx5_ifc_ipv6_layout_bits {
522 	u8         ipv6[16][0x8];
523 };
524 
525 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits {
526 	struct mlx5_ifc_ipv6_layout_bits ipv6_layout;
527 	struct mlx5_ifc_ipv4_layout_bits ipv4_layout;
528 	u8         reserved_at_0[0x80];
529 };
530 
531 enum {
532 	MLX5_PACKET_L4_TYPE_NONE,
533 	MLX5_PACKET_L4_TYPE_TCP,
534 	MLX5_PACKET_L4_TYPE_UDP,
535 };
536 
537 struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
538 	u8         smac_47_16[0x20];
539 
540 	u8         smac_15_0[0x10];
541 	u8         ethertype[0x10];
542 
543 	u8         dmac_47_16[0x20];
544 
545 	u8         dmac_15_0[0x10];
546 	u8         first_prio[0x3];
547 	u8         first_cfi[0x1];
548 	u8         first_vid[0xc];
549 
550 	u8         ip_protocol[0x8];
551 	u8         ip_dscp[0x6];
552 	u8         ip_ecn[0x2];
553 	u8         cvlan_tag[0x1];
554 	u8         svlan_tag[0x1];
555 	u8         frag[0x1];
556 	u8         ip_version[0x4];
557 	u8         tcp_flags[0x9];
558 
559 	u8         tcp_sport[0x10];
560 	u8         tcp_dport[0x10];
561 
562 	u8         l4_type[0x2];
563 	u8         reserved_at_c2[0xe];
564 	u8         ipv4_ihl[0x4];
565 	u8         reserved_at_c4[0x4];
566 
567 	u8         ttl_hoplimit[0x8];
568 
569 	u8         udp_sport[0x10];
570 	u8         udp_dport[0x10];
571 
572 	union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
573 
574 	union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
575 };
576 
577 struct mlx5_ifc_nvgre_key_bits {
578 	u8 hi[0x18];
579 	u8 lo[0x8];
580 };
581 
582 union mlx5_ifc_gre_key_bits {
583 	struct mlx5_ifc_nvgre_key_bits nvgre;
584 	u8 key[0x20];
585 };
586 
587 struct mlx5_ifc_fte_match_set_misc_bits {
588 	u8         gre_c_present[0x1];
589 	u8         reserved_at_1[0x1];
590 	u8         gre_k_present[0x1];
591 	u8         gre_s_present[0x1];
592 	u8         source_vhca_port[0x4];
593 	u8         source_sqn[0x18];
594 
595 	u8         source_eswitch_owner_vhca_id[0x10];
596 	u8         source_port[0x10];
597 
598 	u8         outer_second_prio[0x3];
599 	u8         outer_second_cfi[0x1];
600 	u8         outer_second_vid[0xc];
601 	u8         inner_second_prio[0x3];
602 	u8         inner_second_cfi[0x1];
603 	u8         inner_second_vid[0xc];
604 
605 	u8         outer_second_cvlan_tag[0x1];
606 	u8         inner_second_cvlan_tag[0x1];
607 	u8         outer_second_svlan_tag[0x1];
608 	u8         inner_second_svlan_tag[0x1];
609 	u8         reserved_at_64[0xc];
610 	u8         gre_protocol[0x10];
611 
612 	union mlx5_ifc_gre_key_bits gre_key;
613 
614 	u8         vxlan_vni[0x18];
615 	u8         bth_opcode[0x8];
616 
617 	u8         geneve_vni[0x18];
618 	u8         reserved_at_d8[0x6];
619 	u8         geneve_tlv_option_0_exist[0x1];
620 	u8         geneve_oam[0x1];
621 
622 	u8         reserved_at_e0[0xc];
623 	u8         outer_ipv6_flow_label[0x14];
624 
625 	u8         reserved_at_100[0xc];
626 	u8         inner_ipv6_flow_label[0x14];
627 
628 	u8         reserved_at_120[0xa];
629 	u8         geneve_opt_len[0x6];
630 	u8         geneve_protocol_type[0x10];
631 
632 	u8         reserved_at_140[0x8];
633 	u8         bth_dst_qp[0x18];
634 	u8	   inner_esp_spi[0x20];
635 	u8	   outer_esp_spi[0x20];
636 	u8         reserved_at_1a0[0x60];
637 };
638 
639 struct mlx5_ifc_fte_match_mpls_bits {
640 	u8         mpls_label[0x14];
641 	u8         mpls_exp[0x3];
642 	u8         mpls_s_bos[0x1];
643 	u8         mpls_ttl[0x8];
644 };
645 
646 struct mlx5_ifc_fte_match_set_misc2_bits {
647 	struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls;
648 
649 	struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls;
650 
651 	struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre;
652 
653 	struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp;
654 
655 	u8         metadata_reg_c_7[0x20];
656 
657 	u8         metadata_reg_c_6[0x20];
658 
659 	u8         metadata_reg_c_5[0x20];
660 
661 	u8         metadata_reg_c_4[0x20];
662 
663 	u8         metadata_reg_c_3[0x20];
664 
665 	u8         metadata_reg_c_2[0x20];
666 
667 	u8         metadata_reg_c_1[0x20];
668 
669 	u8         metadata_reg_c_0[0x20];
670 
671 	u8         metadata_reg_a[0x20];
672 
673 	u8         reserved_at_1a0[0x8];
674 
675 	u8         macsec_syndrome[0x8];
676 	u8         ipsec_syndrome[0x8];
677 	u8         reserved_at_1b8[0x8];
678 
679 	u8         reserved_at_1c0[0x40];
680 };
681 
682 struct mlx5_ifc_fte_match_set_misc3_bits {
683 	u8         inner_tcp_seq_num[0x20];
684 
685 	u8         outer_tcp_seq_num[0x20];
686 
687 	u8         inner_tcp_ack_num[0x20];
688 
689 	u8         outer_tcp_ack_num[0x20];
690 
691 	u8	   reserved_at_80[0x8];
692 	u8         outer_vxlan_gpe_vni[0x18];
693 
694 	u8         outer_vxlan_gpe_next_protocol[0x8];
695 	u8         outer_vxlan_gpe_flags[0x8];
696 	u8	   reserved_at_b0[0x10];
697 
698 	u8	   icmp_header_data[0x20];
699 
700 	u8	   icmpv6_header_data[0x20];
701 
702 	u8	   icmp_type[0x8];
703 	u8	   icmp_code[0x8];
704 	u8	   icmpv6_type[0x8];
705 	u8	   icmpv6_code[0x8];
706 
707 	u8         geneve_tlv_option_0_data[0x20];
708 
709 	u8	   gtpu_teid[0x20];
710 
711 	u8	   gtpu_msg_type[0x8];
712 	u8	   gtpu_msg_flags[0x8];
713 	u8	   reserved_at_170[0x10];
714 
715 	u8	   gtpu_dw_2[0x20];
716 
717 	u8	   gtpu_first_ext_dw_0[0x20];
718 
719 	u8	   gtpu_dw_0[0x20];
720 
721 	u8	   reserved_at_1e0[0x20];
722 };
723 
724 struct mlx5_ifc_fte_match_set_misc4_bits {
725 	u8         prog_sample_field_value_0[0x20];
726 
727 	u8         prog_sample_field_id_0[0x20];
728 
729 	u8         prog_sample_field_value_1[0x20];
730 
731 	u8         prog_sample_field_id_1[0x20];
732 
733 	u8         prog_sample_field_value_2[0x20];
734 
735 	u8         prog_sample_field_id_2[0x20];
736 
737 	u8         prog_sample_field_value_3[0x20];
738 
739 	u8         prog_sample_field_id_3[0x20];
740 
741 	u8         reserved_at_100[0x100];
742 };
743 
744 struct mlx5_ifc_fte_match_set_misc5_bits {
745 	u8         macsec_tag_0[0x20];
746 
747 	u8         macsec_tag_1[0x20];
748 
749 	u8         macsec_tag_2[0x20];
750 
751 	u8         macsec_tag_3[0x20];
752 
753 	u8         tunnel_header_0[0x20];
754 
755 	u8         tunnel_header_1[0x20];
756 
757 	u8         tunnel_header_2[0x20];
758 
759 	u8         tunnel_header_3[0x20];
760 
761 	u8         reserved_at_100[0x100];
762 };
763 
764 struct mlx5_ifc_cmd_pas_bits {
765 	u8         pa_h[0x20];
766 
767 	u8         pa_l[0x14];
768 	u8         reserved_at_34[0xc];
769 };
770 
771 struct mlx5_ifc_uint64_bits {
772 	u8         hi[0x20];
773 
774 	u8         lo[0x20];
775 };
776 
777 enum {
778 	MLX5_ADS_STAT_RATE_NO_LIMIT  = 0x0,
779 	MLX5_ADS_STAT_RATE_2_5GBPS   = 0x7,
780 	MLX5_ADS_STAT_RATE_10GBPS    = 0x8,
781 	MLX5_ADS_STAT_RATE_30GBPS    = 0x9,
782 	MLX5_ADS_STAT_RATE_5GBPS     = 0xa,
783 	MLX5_ADS_STAT_RATE_20GBPS    = 0xb,
784 	MLX5_ADS_STAT_RATE_40GBPS    = 0xc,
785 	MLX5_ADS_STAT_RATE_60GBPS    = 0xd,
786 	MLX5_ADS_STAT_RATE_80GBPS    = 0xe,
787 	MLX5_ADS_STAT_RATE_120GBPS   = 0xf,
788 };
789 
790 struct mlx5_ifc_ads_bits {
791 	u8         fl[0x1];
792 	u8         free_ar[0x1];
793 	u8         reserved_at_2[0xe];
794 	u8         pkey_index[0x10];
795 
796 	u8         reserved_at_20[0x8];
797 	u8         grh[0x1];
798 	u8         mlid[0x7];
799 	u8         rlid[0x10];
800 
801 	u8         ack_timeout[0x5];
802 	u8         reserved_at_45[0x3];
803 	u8         src_addr_index[0x8];
804 	u8         reserved_at_50[0x4];
805 	u8         stat_rate[0x4];
806 	u8         hop_limit[0x8];
807 
808 	u8         reserved_at_60[0x4];
809 	u8         tclass[0x8];
810 	u8         flow_label[0x14];
811 
812 	u8         rgid_rip[16][0x8];
813 
814 	u8         reserved_at_100[0x4];
815 	u8         f_dscp[0x1];
816 	u8         f_ecn[0x1];
817 	u8         reserved_at_106[0x1];
818 	u8         f_eth_prio[0x1];
819 	u8         ecn[0x2];
820 	u8         dscp[0x6];
821 	u8         udp_sport[0x10];
822 
823 	u8         dei_cfi[0x1];
824 	u8         eth_prio[0x3];
825 	u8         sl[0x4];
826 	u8         vhca_port_num[0x8];
827 	u8         rmac_47_32[0x10];
828 
829 	u8         rmac_31_0[0x20];
830 };
831 
832 struct mlx5_ifc_flow_table_nic_cap_bits {
833 	u8         nic_rx_multi_path_tirs[0x1];
834 	u8         nic_rx_multi_path_tirs_fts[0x1];
835 	u8         allow_sniffer_and_nic_rx_shared_tir[0x1];
836 	u8	   reserved_at_3[0x4];
837 	u8	   sw_owner_reformat_supported[0x1];
838 	u8	   reserved_at_8[0x18];
839 
840 	u8	   encap_general_header[0x1];
841 	u8	   reserved_at_21[0xa];
842 	u8	   log_max_packet_reformat_context[0x5];
843 	u8	   reserved_at_30[0x6];
844 	u8	   max_encap_header_size[0xa];
845 	u8	   reserved_at_40[0x1c0];
846 
847 	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
848 
849 	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_rdma;
850 
851 	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
852 
853 	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
854 
855 	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_rdma;
856 
857 	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
858 
859 	u8         reserved_at_e00[0x600];
860 
861 	struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_receive;
862 
863 	u8         reserved_at_1480[0x80];
864 
865 	struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_receive_rdma;
866 
867 	u8         reserved_at_1580[0x280];
868 
869 	struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_transmit_rdma;
870 
871 	u8         reserved_at_1880[0x780];
872 
873 	u8         sw_steering_nic_rx_action_drop_icm_address[0x40];
874 
875 	u8         sw_steering_nic_tx_action_drop_icm_address[0x40];
876 
877 	u8         sw_steering_nic_tx_action_allow_icm_address[0x40];
878 
879 	u8         reserved_at_20c0[0x5f40];
880 };
881 
882 struct mlx5_ifc_port_selection_cap_bits {
883 	u8         reserved_at_0[0x10];
884 	u8         port_select_flow_table[0x1];
885 	u8         reserved_at_11[0x1];
886 	u8         port_select_flow_table_bypass[0x1];
887 	u8         reserved_at_13[0xd];
888 
889 	u8         reserved_at_20[0x1e0];
890 
891 	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_port_selection;
892 
893 	struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_port_selection;
894 
895 	u8         reserved_at_480[0x7b80];
896 };
897 
898 enum {
899 	MLX5_FDB_TO_VPORT_REG_C_0 = 0x01,
900 	MLX5_FDB_TO_VPORT_REG_C_1 = 0x02,
901 	MLX5_FDB_TO_VPORT_REG_C_2 = 0x04,
902 	MLX5_FDB_TO_VPORT_REG_C_3 = 0x08,
903 	MLX5_FDB_TO_VPORT_REG_C_4 = 0x10,
904 	MLX5_FDB_TO_VPORT_REG_C_5 = 0x20,
905 	MLX5_FDB_TO_VPORT_REG_C_6 = 0x40,
906 	MLX5_FDB_TO_VPORT_REG_C_7 = 0x80,
907 };
908 
909 struct mlx5_ifc_flow_table_eswitch_cap_bits {
910 	u8      fdb_to_vport_reg_c_id[0x8];
911 	u8      reserved_at_8[0x5];
912 	u8      fdb_uplink_hairpin[0x1];
913 	u8      fdb_multi_path_any_table_limit_regc[0x1];
914 	u8      reserved_at_f[0x3];
915 	u8      fdb_multi_path_any_table[0x1];
916 	u8      reserved_at_13[0x2];
917 	u8      fdb_modify_header_fwd_to_table[0x1];
918 	u8      fdb_ipv4_ttl_modify[0x1];
919 	u8      flow_source[0x1];
920 	u8      reserved_at_18[0x2];
921 	u8      multi_fdb_encap[0x1];
922 	u8      egress_acl_forward_to_vport[0x1];
923 	u8      fdb_multi_path_to_table[0x1];
924 	u8      reserved_at_1d[0x3];
925 
926 	u8      reserved_at_20[0x1e0];
927 
928 	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb;
929 
930 	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress;
931 
932 	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress;
933 
934 	u8      reserved_at_800[0xC00];
935 
936 	struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_esw_fdb;
937 
938 	struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_bitmask_support_2_esw_fdb;
939 
940 	u8      reserved_at_1500[0x300];
941 
942 	u8      sw_steering_fdb_action_drop_icm_address_rx[0x40];
943 
944 	u8      sw_steering_fdb_action_drop_icm_address_tx[0x40];
945 
946 	u8      sw_steering_uplink_icm_address_rx[0x40];
947 
948 	u8      sw_steering_uplink_icm_address_tx[0x40];
949 
950 	u8      reserved_at_1900[0x6700];
951 };
952 
953 enum {
954 	MLX5_COUNTER_SOURCE_ESWITCH = 0x0,
955 	MLX5_COUNTER_FLOW_ESWITCH   = 0x1,
956 };
957 
958 struct mlx5_ifc_e_switch_cap_bits {
959 	u8         vport_svlan_strip[0x1];
960 	u8         vport_cvlan_strip[0x1];
961 	u8         vport_svlan_insert[0x1];
962 	u8         vport_cvlan_insert_if_not_exist[0x1];
963 	u8         vport_cvlan_insert_overwrite[0x1];
964 	u8         reserved_at_5[0x1];
965 	u8         vport_cvlan_insert_always[0x1];
966 	u8         esw_shared_ingress_acl[0x1];
967 	u8         esw_uplink_ingress_acl[0x1];
968 	u8         root_ft_on_other_esw[0x1];
969 	u8         reserved_at_a[0xf];
970 	u8         esw_functions_changed[0x1];
971 	u8         reserved_at_1a[0x1];
972 	u8         ecpf_vport_exists[0x1];
973 	u8         counter_eswitch_affinity[0x1];
974 	u8         merged_eswitch[0x1];
975 	u8         nic_vport_node_guid_modify[0x1];
976 	u8         nic_vport_port_guid_modify[0x1];
977 
978 	u8         vxlan_encap_decap[0x1];
979 	u8         nvgre_encap_decap[0x1];
980 	u8         reserved_at_22[0x1];
981 	u8         log_max_fdb_encap_uplink[0x5];
982 	u8         reserved_at_21[0x3];
983 	u8         log_max_packet_reformat_context[0x5];
984 	u8         reserved_2b[0x6];
985 	u8         max_encap_header_size[0xa];
986 
987 	u8         reserved_at_40[0xb];
988 	u8         log_max_esw_sf[0x5];
989 	u8         esw_sf_base_id[0x10];
990 
991 	u8         reserved_at_60[0x7a0];
992 
993 };
994 
995 struct mlx5_ifc_qos_cap_bits {
996 	u8         packet_pacing[0x1];
997 	u8         esw_scheduling[0x1];
998 	u8         esw_bw_share[0x1];
999 	u8         esw_rate_limit[0x1];
1000 	u8         reserved_at_4[0x1];
1001 	u8         packet_pacing_burst_bound[0x1];
1002 	u8         packet_pacing_typical_size[0x1];
1003 	u8         reserved_at_7[0x1];
1004 	u8         nic_sq_scheduling[0x1];
1005 	u8         nic_bw_share[0x1];
1006 	u8         nic_rate_limit[0x1];
1007 	u8         packet_pacing_uid[0x1];
1008 	u8         log_esw_max_sched_depth[0x4];
1009 	u8         reserved_at_10[0x10];
1010 
1011 	u8         reserved_at_20[0xb];
1012 	u8         log_max_qos_nic_queue_group[0x5];
1013 	u8         reserved_at_30[0x10];
1014 
1015 	u8         packet_pacing_max_rate[0x20];
1016 
1017 	u8         packet_pacing_min_rate[0x20];
1018 
1019 	u8         reserved_at_80[0x10];
1020 	u8         packet_pacing_rate_table_size[0x10];
1021 
1022 	u8         esw_element_type[0x10];
1023 	u8         esw_tsar_type[0x10];
1024 
1025 	u8         reserved_at_c0[0x10];
1026 	u8         max_qos_para_vport[0x10];
1027 
1028 	u8         max_tsar_bw_share[0x20];
1029 
1030 	u8         reserved_at_100[0x20];
1031 
1032 	u8         reserved_at_120[0x3];
1033 	u8         log_meter_aso_granularity[0x5];
1034 	u8         reserved_at_128[0x3];
1035 	u8         log_meter_aso_max_alloc[0x5];
1036 	u8         reserved_at_130[0x3];
1037 	u8         log_max_num_meter_aso[0x5];
1038 	u8         reserved_at_138[0x8];
1039 
1040 	u8         reserved_at_140[0x6c0];
1041 };
1042 
1043 struct mlx5_ifc_debug_cap_bits {
1044 	u8         core_dump_general[0x1];
1045 	u8         core_dump_qp[0x1];
1046 	u8         reserved_at_2[0x7];
1047 	u8         resource_dump[0x1];
1048 	u8         reserved_at_a[0x16];
1049 
1050 	u8         reserved_at_20[0x2];
1051 	u8         stall_detect[0x1];
1052 	u8         reserved_at_23[0x1d];
1053 
1054 	u8         reserved_at_40[0x7c0];
1055 };
1056 
1057 struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
1058 	u8         csum_cap[0x1];
1059 	u8         vlan_cap[0x1];
1060 	u8         lro_cap[0x1];
1061 	u8         lro_psh_flag[0x1];
1062 	u8         lro_time_stamp[0x1];
1063 	u8         reserved_at_5[0x2];
1064 	u8         wqe_vlan_insert[0x1];
1065 	u8         self_lb_en_modifiable[0x1];
1066 	u8         reserved_at_9[0x2];
1067 	u8         max_lso_cap[0x5];
1068 	u8         multi_pkt_send_wqe[0x2];
1069 	u8	   wqe_inline_mode[0x2];
1070 	u8         rss_ind_tbl_cap[0x4];
1071 	u8         reg_umr_sq[0x1];
1072 	u8         scatter_fcs[0x1];
1073 	u8         enhanced_multi_pkt_send_wqe[0x1];
1074 	u8         tunnel_lso_const_out_ip_id[0x1];
1075 	u8         tunnel_lro_gre[0x1];
1076 	u8         tunnel_lro_vxlan[0x1];
1077 	u8         tunnel_stateless_gre[0x1];
1078 	u8         tunnel_stateless_vxlan[0x1];
1079 
1080 	u8         swp[0x1];
1081 	u8         swp_csum[0x1];
1082 	u8         swp_lso[0x1];
1083 	u8         cqe_checksum_full[0x1];
1084 	u8         tunnel_stateless_geneve_tx[0x1];
1085 	u8         tunnel_stateless_mpls_over_udp[0x1];
1086 	u8         tunnel_stateless_mpls_over_gre[0x1];
1087 	u8         tunnel_stateless_vxlan_gpe[0x1];
1088 	u8         tunnel_stateless_ipv4_over_vxlan[0x1];
1089 	u8         tunnel_stateless_ip_over_ip[0x1];
1090 	u8         insert_trailer[0x1];
1091 	u8         reserved_at_2b[0x1];
1092 	u8         tunnel_stateless_ip_over_ip_rx[0x1];
1093 	u8         tunnel_stateless_ip_over_ip_tx[0x1];
1094 	u8         reserved_at_2e[0x2];
1095 	u8         max_vxlan_udp_ports[0x8];
1096 	u8         reserved_at_38[0x6];
1097 	u8         max_geneve_opt_len[0x1];
1098 	u8         tunnel_stateless_geneve_rx[0x1];
1099 
1100 	u8         reserved_at_40[0x10];
1101 	u8         lro_min_mss_size[0x10];
1102 
1103 	u8         reserved_at_60[0x120];
1104 
1105 	u8         lro_timer_supported_periods[4][0x20];
1106 
1107 	u8         reserved_at_200[0x600];
1108 };
1109 
1110 enum {
1111 	MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING               = 0x0,
1112 	MLX5_TIMESTAMP_FORMAT_CAP_REAL_TIME                  = 0x1,
1113 	MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING_AND_REAL_TIME = 0x2,
1114 };
1115 
1116 struct mlx5_ifc_roce_cap_bits {
1117 	u8         roce_apm[0x1];
1118 	u8         reserved_at_1[0x3];
1119 	u8         sw_r_roce_src_udp_port[0x1];
1120 	u8         fl_rc_qp_when_roce_disabled[0x1];
1121 	u8         fl_rc_qp_when_roce_enabled[0x1];
1122 	u8         roce_cc_general[0x1];
1123 	u8	   qp_ooo_transmit_default[0x1];
1124 	u8         reserved_at_9[0x15];
1125 	u8	   qp_ts_format[0x2];
1126 
1127 	u8         reserved_at_20[0x60];
1128 
1129 	u8         reserved_at_80[0xc];
1130 	u8         l3_type[0x4];
1131 	u8         reserved_at_90[0x8];
1132 	u8         roce_version[0x8];
1133 
1134 	u8         reserved_at_a0[0x10];
1135 	u8         r_roce_dest_udp_port[0x10];
1136 
1137 	u8         r_roce_max_src_udp_port[0x10];
1138 	u8         r_roce_min_src_udp_port[0x10];
1139 
1140 	u8         reserved_at_e0[0x10];
1141 	u8         roce_address_table_size[0x10];
1142 
1143 	u8         reserved_at_100[0x700];
1144 };
1145 
1146 struct mlx5_ifc_sync_steering_in_bits {
1147 	u8         opcode[0x10];
1148 	u8         uid[0x10];
1149 
1150 	u8         reserved_at_20[0x10];
1151 	u8         op_mod[0x10];
1152 
1153 	u8         reserved_at_40[0xc0];
1154 };
1155 
1156 struct mlx5_ifc_sync_steering_out_bits {
1157 	u8         status[0x8];
1158 	u8         reserved_at_8[0x18];
1159 
1160 	u8         syndrome[0x20];
1161 
1162 	u8         reserved_at_40[0x40];
1163 };
1164 
1165 struct mlx5_ifc_sync_crypto_in_bits {
1166 	u8         opcode[0x10];
1167 	u8         uid[0x10];
1168 
1169 	u8         reserved_at_20[0x10];
1170 	u8         op_mod[0x10];
1171 
1172 	u8         reserved_at_40[0x20];
1173 
1174 	u8         reserved_at_60[0x10];
1175 	u8         crypto_type[0x10];
1176 
1177 	u8         reserved_at_80[0x80];
1178 };
1179 
1180 struct mlx5_ifc_sync_crypto_out_bits {
1181 	u8         status[0x8];
1182 	u8         reserved_at_8[0x18];
1183 
1184 	u8         syndrome[0x20];
1185 
1186 	u8         reserved_at_40[0x40];
1187 };
1188 
1189 struct mlx5_ifc_device_mem_cap_bits {
1190 	u8         memic[0x1];
1191 	u8         reserved_at_1[0x1f];
1192 
1193 	u8         reserved_at_20[0xb];
1194 	u8         log_min_memic_alloc_size[0x5];
1195 	u8         reserved_at_30[0x8];
1196 	u8	   log_max_memic_addr_alignment[0x8];
1197 
1198 	u8         memic_bar_start_addr[0x40];
1199 
1200 	u8         memic_bar_size[0x20];
1201 
1202 	u8         max_memic_size[0x20];
1203 
1204 	u8         steering_sw_icm_start_address[0x40];
1205 
1206 	u8         reserved_at_100[0x8];
1207 	u8         log_header_modify_sw_icm_size[0x8];
1208 	u8         reserved_at_110[0x2];
1209 	u8         log_sw_icm_alloc_granularity[0x6];
1210 	u8         log_steering_sw_icm_size[0x8];
1211 
1212 	u8         log_indirect_encap_sw_icm_size[0x8];
1213 	u8         reserved_at_128[0x10];
1214 	u8         log_header_modify_pattern_sw_icm_size[0x8];
1215 
1216 	u8         header_modify_sw_icm_start_address[0x40];
1217 
1218 	u8         reserved_at_180[0x40];
1219 
1220 	u8         header_modify_pattern_sw_icm_start_address[0x40];
1221 
1222 	u8         memic_operations[0x20];
1223 
1224 	u8         reserved_at_220[0x20];
1225 
1226 	u8         indirect_encap_sw_icm_start_address[0x40];
1227 
1228 	u8         reserved_at_280[0x580];
1229 };
1230 
1231 struct mlx5_ifc_device_event_cap_bits {
1232 	u8         user_affiliated_events[4][0x40];
1233 
1234 	u8         user_unaffiliated_events[4][0x40];
1235 };
1236 
1237 struct mlx5_ifc_virtio_emulation_cap_bits {
1238 	u8         desc_tunnel_offload_type[0x1];
1239 	u8         eth_frame_offload_type[0x1];
1240 	u8         virtio_version_1_0[0x1];
1241 	u8         device_features_bits_mask[0xd];
1242 	u8         event_mode[0x8];
1243 	u8         virtio_queue_type[0x8];
1244 
1245 	u8         max_tunnel_desc[0x10];
1246 	u8         reserved_at_30[0x3];
1247 	u8         log_doorbell_stride[0x5];
1248 	u8         reserved_at_38[0x3];
1249 	u8         log_doorbell_bar_size[0x5];
1250 
1251 	u8         doorbell_bar_offset[0x40];
1252 
1253 	u8         max_emulated_devices[0x8];
1254 	u8         max_num_virtio_queues[0x18];
1255 
1256 	u8         reserved_at_a0[0x20];
1257 
1258 	u8	   reserved_at_c0[0x13];
1259 	u8         desc_group_mkey_supported[0x1];
1260 	u8         freeze_to_rdy_supported[0x1];
1261 	u8         reserved_at_d5[0xb];
1262 
1263 	u8         reserved_at_e0[0x20];
1264 
1265 	u8         umem_1_buffer_param_a[0x20];
1266 
1267 	u8         umem_1_buffer_param_b[0x20];
1268 
1269 	u8         umem_2_buffer_param_a[0x20];
1270 
1271 	u8         umem_2_buffer_param_b[0x20];
1272 
1273 	u8         umem_3_buffer_param_a[0x20];
1274 
1275 	u8         umem_3_buffer_param_b[0x20];
1276 
1277 	u8         reserved_at_1c0[0x640];
1278 };
1279 
1280 enum {
1281 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE     = 0x0,
1282 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES    = 0x2,
1283 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES    = 0x4,
1284 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES    = 0x8,
1285 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES   = 0x10,
1286 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES   = 0x20,
1287 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES   = 0x40,
1288 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES  = 0x80,
1289 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES  = 0x100,
1290 };
1291 
1292 enum {
1293 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE     = 0x1,
1294 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES    = 0x2,
1295 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES    = 0x4,
1296 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES    = 0x8,
1297 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES   = 0x10,
1298 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES   = 0x20,
1299 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES   = 0x40,
1300 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES  = 0x80,
1301 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES  = 0x100,
1302 };
1303 
1304 struct mlx5_ifc_atomic_caps_bits {
1305 	u8         reserved_at_0[0x40];
1306 
1307 	u8         atomic_req_8B_endianness_mode[0x2];
1308 	u8         reserved_at_42[0x4];
1309 	u8         supported_atomic_req_8B_endianness_mode_1[0x1];
1310 
1311 	u8         reserved_at_47[0x19];
1312 
1313 	u8         reserved_at_60[0x20];
1314 
1315 	u8         reserved_at_80[0x10];
1316 	u8         atomic_operations[0x10];
1317 
1318 	u8         reserved_at_a0[0x10];
1319 	u8         atomic_size_qp[0x10];
1320 
1321 	u8         reserved_at_c0[0x10];
1322 	u8         atomic_size_dc[0x10];
1323 
1324 	u8         reserved_at_e0[0x720];
1325 };
1326 
1327 struct mlx5_ifc_odp_cap_bits {
1328 	u8         reserved_at_0[0x40];
1329 
1330 	u8         sig[0x1];
1331 	u8         reserved_at_41[0x1f];
1332 
1333 	u8         reserved_at_60[0x20];
1334 
1335 	struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
1336 
1337 	struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
1338 
1339 	struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
1340 
1341 	struct mlx5_ifc_odp_per_transport_service_cap_bits xrc_odp_caps;
1342 
1343 	struct mlx5_ifc_odp_per_transport_service_cap_bits dc_odp_caps;
1344 
1345 	u8         reserved_at_120[0x6E0];
1346 };
1347 
1348 struct mlx5_ifc_tls_cap_bits {
1349 	u8         tls_1_2_aes_gcm_128[0x1];
1350 	u8         tls_1_3_aes_gcm_128[0x1];
1351 	u8         tls_1_2_aes_gcm_256[0x1];
1352 	u8         tls_1_3_aes_gcm_256[0x1];
1353 	u8         reserved_at_4[0x1c];
1354 
1355 	u8         reserved_at_20[0x7e0];
1356 };
1357 
1358 struct mlx5_ifc_ipsec_cap_bits {
1359 	u8         ipsec_full_offload[0x1];
1360 	u8         ipsec_crypto_offload[0x1];
1361 	u8         ipsec_esn[0x1];
1362 	u8         ipsec_crypto_esp_aes_gcm_256_encrypt[0x1];
1363 	u8         ipsec_crypto_esp_aes_gcm_128_encrypt[0x1];
1364 	u8         ipsec_crypto_esp_aes_gcm_256_decrypt[0x1];
1365 	u8         ipsec_crypto_esp_aes_gcm_128_decrypt[0x1];
1366 	u8         reserved_at_7[0x4];
1367 	u8         log_max_ipsec_offload[0x5];
1368 	u8         reserved_at_10[0x10];
1369 
1370 	u8         min_log_ipsec_full_replay_window[0x8];
1371 	u8         max_log_ipsec_full_replay_window[0x8];
1372 	u8         reserved_at_30[0x7d0];
1373 };
1374 
1375 struct mlx5_ifc_macsec_cap_bits {
1376 	u8    macsec_epn[0x1];
1377 	u8    reserved_at_1[0x2];
1378 	u8    macsec_crypto_esp_aes_gcm_256_encrypt[0x1];
1379 	u8    macsec_crypto_esp_aes_gcm_128_encrypt[0x1];
1380 	u8    macsec_crypto_esp_aes_gcm_256_decrypt[0x1];
1381 	u8    macsec_crypto_esp_aes_gcm_128_decrypt[0x1];
1382 	u8    reserved_at_7[0x4];
1383 	u8    log_max_macsec_offload[0x5];
1384 	u8    reserved_at_10[0x10];
1385 
1386 	u8    min_log_macsec_full_replay_window[0x8];
1387 	u8    max_log_macsec_full_replay_window[0x8];
1388 	u8    reserved_at_30[0x10];
1389 
1390 	u8    reserved_at_40[0x7c0];
1391 };
1392 
1393 enum {
1394 	MLX5_WQ_TYPE_LINKED_LIST  = 0x0,
1395 	MLX5_WQ_TYPE_CYCLIC       = 0x1,
1396 	MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2,
1397 	MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3,
1398 };
1399 
1400 enum {
1401 	MLX5_WQ_END_PAD_MODE_NONE   = 0x0,
1402 	MLX5_WQ_END_PAD_MODE_ALIGN  = 0x1,
1403 };
1404 
1405 enum {
1406 	MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES    = 0x0,
1407 	MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES   = 0x1,
1408 	MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES   = 0x2,
1409 	MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES   = 0x3,
1410 	MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES  = 0x4,
1411 };
1412 
1413 enum {
1414 	MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES  = 0x0,
1415 	MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES  = 0x1,
1416 	MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES  = 0x2,
1417 	MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES   = 0x3,
1418 	MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES   = 0x4,
1419 	MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES   = 0x5,
1420 };
1421 
1422 enum {
1423 	MLX5_CMD_HCA_CAP_PORT_TYPE_IB        = 0x0,
1424 	MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET  = 0x1,
1425 };
1426 
1427 enum {
1428 	MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED       = 0x0,
1429 	MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE  = 0x1,
1430 	MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED        = 0x3,
1431 };
1432 
1433 enum {
1434 	MLX5_CAP_PORT_TYPE_IB  = 0x0,
1435 	MLX5_CAP_PORT_TYPE_ETH = 0x1,
1436 };
1437 
1438 enum {
1439 	MLX5_CAP_UMR_FENCE_STRONG	= 0x0,
1440 	MLX5_CAP_UMR_FENCE_SMALL	= 0x1,
1441 	MLX5_CAP_UMR_FENCE_NONE		= 0x2,
1442 };
1443 
1444 enum {
1445 	MLX5_FLEX_PARSER_GENEVE_ENABLED		= 1 << 3,
1446 	MLX5_FLEX_PARSER_MPLS_OVER_GRE_ENABLED	= 1 << 4,
1447 	MLX5_FLEX_PARSER_MPLS_OVER_UDP_ENABLED	= 1 << 5,
1448 	MLX5_FLEX_PARSER_VXLAN_GPE_ENABLED	= 1 << 7,
1449 	MLX5_FLEX_PARSER_ICMP_V4_ENABLED	= 1 << 8,
1450 	MLX5_FLEX_PARSER_ICMP_V6_ENABLED	= 1 << 9,
1451 	MLX5_FLEX_PARSER_GENEVE_TLV_OPTION_0_ENABLED = 1 << 10,
1452 	MLX5_FLEX_PARSER_GTPU_ENABLED		= 1 << 11,
1453 	MLX5_FLEX_PARSER_GTPU_DW_2_ENABLED	= 1 << 16,
1454 	MLX5_FLEX_PARSER_GTPU_FIRST_EXT_DW_0_ENABLED = 1 << 17,
1455 	MLX5_FLEX_PARSER_GTPU_DW_0_ENABLED	= 1 << 18,
1456 	MLX5_FLEX_PARSER_GTPU_TEID_ENABLED	= 1 << 19,
1457 };
1458 
1459 enum {
1460 	MLX5_UCTX_CAP_RAW_TX = 1UL << 0,
1461 	MLX5_UCTX_CAP_INTERNAL_DEV_RES = 1UL << 1,
1462 };
1463 
1464 #define MLX5_FC_BULK_SIZE_FACTOR 128
1465 
1466 enum mlx5_fc_bulk_alloc_bitmask {
1467 	MLX5_FC_BULK_128   = (1 << 0),
1468 	MLX5_FC_BULK_256   = (1 << 1),
1469 	MLX5_FC_BULK_512   = (1 << 2),
1470 	MLX5_FC_BULK_1024  = (1 << 3),
1471 	MLX5_FC_BULK_2048  = (1 << 4),
1472 	MLX5_FC_BULK_4096  = (1 << 5),
1473 	MLX5_FC_BULK_8192  = (1 << 6),
1474 	MLX5_FC_BULK_16384 = (1 << 7),
1475 };
1476 
1477 #define MLX5_FC_BULK_NUM_FCS(fc_enum) (MLX5_FC_BULK_SIZE_FACTOR * (fc_enum))
1478 
1479 #define MLX5_FT_MAX_MULTIPATH_LEVEL 63
1480 
1481 enum {
1482 	MLX5_STEERING_FORMAT_CONNECTX_5   = 0,
1483 	MLX5_STEERING_FORMAT_CONNECTX_6DX = 1,
1484 	MLX5_STEERING_FORMAT_CONNECTX_7   = 2,
1485 };
1486 
1487 struct mlx5_ifc_cmd_hca_cap_bits {
1488 	u8         reserved_at_0[0x6];
1489 	u8         page_request_disable[0x1];
1490 	u8         reserved_at_7[0x9];
1491 	u8         shared_object_to_user_object_allowed[0x1];
1492 	u8         reserved_at_13[0xe];
1493 	u8         vhca_resource_manager[0x1];
1494 
1495 	u8         hca_cap_2[0x1];
1496 	u8         create_lag_when_not_master_up[0x1];
1497 	u8         dtor[0x1];
1498 	u8         event_on_vhca_state_teardown_request[0x1];
1499 	u8         event_on_vhca_state_in_use[0x1];
1500 	u8         event_on_vhca_state_active[0x1];
1501 	u8         event_on_vhca_state_allocated[0x1];
1502 	u8         event_on_vhca_state_invalid[0x1];
1503 	u8         reserved_at_28[0x8];
1504 	u8         vhca_id[0x10];
1505 
1506 	u8         reserved_at_40[0x40];
1507 
1508 	u8         log_max_srq_sz[0x8];
1509 	u8         log_max_qp_sz[0x8];
1510 	u8         event_cap[0x1];
1511 	u8         reserved_at_91[0x2];
1512 	u8         isolate_vl_tc_new[0x1];
1513 	u8         reserved_at_94[0x4];
1514 	u8         prio_tag_required[0x1];
1515 	u8         reserved_at_99[0x2];
1516 	u8         log_max_qp[0x5];
1517 
1518 	u8         reserved_at_a0[0x3];
1519 	u8	   ece_support[0x1];
1520 	u8	   reserved_at_a4[0x5];
1521 	u8         reg_c_preserve[0x1];
1522 	u8         reserved_at_aa[0x1];
1523 	u8         log_max_srq[0x5];
1524 	u8         reserved_at_b0[0x1];
1525 	u8         uplink_follow[0x1];
1526 	u8         ts_cqe_to_dest_cqn[0x1];
1527 	u8         reserved_at_b3[0x6];
1528 	u8         go_back_n[0x1];
1529 	u8         shampo[0x1];
1530 	u8         reserved_at_bb[0x5];
1531 
1532 	u8         max_sgl_for_optimized_performance[0x8];
1533 	u8         log_max_cq_sz[0x8];
1534 	u8         relaxed_ordering_write_umr[0x1];
1535 	u8         relaxed_ordering_read_umr[0x1];
1536 	u8         reserved_at_d2[0x7];
1537 	u8         virtio_net_device_emualtion_manager[0x1];
1538 	u8         virtio_blk_device_emualtion_manager[0x1];
1539 	u8         log_max_cq[0x5];
1540 
1541 	u8         log_max_eq_sz[0x8];
1542 	u8         relaxed_ordering_write[0x1];
1543 	u8         relaxed_ordering_read_pci_enabled[0x1];
1544 	u8         log_max_mkey[0x6];
1545 	u8         reserved_at_f0[0x6];
1546 	u8	   terminate_scatter_list_mkey[0x1];
1547 	u8	   repeated_mkey[0x1];
1548 	u8         dump_fill_mkey[0x1];
1549 	u8         reserved_at_f9[0x2];
1550 	u8         fast_teardown[0x1];
1551 	u8         log_max_eq[0x4];
1552 
1553 	u8         max_indirection[0x8];
1554 	u8         fixed_buffer_size[0x1];
1555 	u8         log_max_mrw_sz[0x7];
1556 	u8         force_teardown[0x1];
1557 	u8         reserved_at_111[0x1];
1558 	u8         log_max_bsf_list_size[0x6];
1559 	u8         umr_extended_translation_offset[0x1];
1560 	u8         null_mkey[0x1];
1561 	u8         log_max_klm_list_size[0x6];
1562 
1563 	u8         reserved_at_120[0x2];
1564 	u8	   qpc_extension[0x1];
1565 	u8	   reserved_at_123[0x7];
1566 	u8         log_max_ra_req_dc[0x6];
1567 	u8         reserved_at_130[0x2];
1568 	u8         eth_wqe_too_small[0x1];
1569 	u8         reserved_at_133[0x6];
1570 	u8         vnic_env_cq_overrun[0x1];
1571 	u8         log_max_ra_res_dc[0x6];
1572 
1573 	u8         reserved_at_140[0x5];
1574 	u8         release_all_pages[0x1];
1575 	u8         must_not_use[0x1];
1576 	u8         reserved_at_147[0x2];
1577 	u8         roce_accl[0x1];
1578 	u8         log_max_ra_req_qp[0x6];
1579 	u8         reserved_at_150[0xa];
1580 	u8         log_max_ra_res_qp[0x6];
1581 
1582 	u8         end_pad[0x1];
1583 	u8         cc_query_allowed[0x1];
1584 	u8         cc_modify_allowed[0x1];
1585 	u8         start_pad[0x1];
1586 	u8         cache_line_128byte[0x1];
1587 	u8         reserved_at_165[0x4];
1588 	u8         rts2rts_qp_counters_set_id[0x1];
1589 	u8         reserved_at_16a[0x2];
1590 	u8         vnic_env_int_rq_oob[0x1];
1591 	u8         sbcam_reg[0x1];
1592 	u8         reserved_at_16e[0x1];
1593 	u8         qcam_reg[0x1];
1594 	u8         gid_table_size[0x10];
1595 
1596 	u8         out_of_seq_cnt[0x1];
1597 	u8         vport_counters[0x1];
1598 	u8         retransmission_q_counters[0x1];
1599 	u8         debug[0x1];
1600 	u8         modify_rq_counter_set_id[0x1];
1601 	u8         rq_delay_drop[0x1];
1602 	u8         max_qp_cnt[0xa];
1603 	u8         pkey_table_size[0x10];
1604 
1605 	u8         vport_group_manager[0x1];
1606 	u8         vhca_group_manager[0x1];
1607 	u8         ib_virt[0x1];
1608 	u8         eth_virt[0x1];
1609 	u8         vnic_env_queue_counters[0x1];
1610 	u8         ets[0x1];
1611 	u8         nic_flow_table[0x1];
1612 	u8         eswitch_manager[0x1];
1613 	u8         device_memory[0x1];
1614 	u8         mcam_reg[0x1];
1615 	u8         pcam_reg[0x1];
1616 	u8         local_ca_ack_delay[0x5];
1617 	u8         port_module_event[0x1];
1618 	u8         enhanced_error_q_counters[0x1];
1619 	u8         ports_check[0x1];
1620 	u8         reserved_at_1b3[0x1];
1621 	u8         disable_link_up[0x1];
1622 	u8         beacon_led[0x1];
1623 	u8         port_type[0x2];
1624 	u8         num_ports[0x8];
1625 
1626 	u8         reserved_at_1c0[0x1];
1627 	u8         pps[0x1];
1628 	u8         pps_modify[0x1];
1629 	u8         log_max_msg[0x5];
1630 	u8         reserved_at_1c8[0x4];
1631 	u8         max_tc[0x4];
1632 	u8         temp_warn_event[0x1];
1633 	u8         dcbx[0x1];
1634 	u8         general_notification_event[0x1];
1635 	u8         reserved_at_1d3[0x2];
1636 	u8         fpga[0x1];
1637 	u8         rol_s[0x1];
1638 	u8         rol_g[0x1];
1639 	u8         reserved_at_1d8[0x1];
1640 	u8         wol_s[0x1];
1641 	u8         wol_g[0x1];
1642 	u8         wol_a[0x1];
1643 	u8         wol_b[0x1];
1644 	u8         wol_m[0x1];
1645 	u8         wol_u[0x1];
1646 	u8         wol_p[0x1];
1647 
1648 	u8         stat_rate_support[0x10];
1649 	u8         reserved_at_1f0[0x1];
1650 	u8         pci_sync_for_fw_update_event[0x1];
1651 	u8         reserved_at_1f2[0x6];
1652 	u8         init2_lag_tx_port_affinity[0x1];
1653 	u8         reserved_at_1fa[0x3];
1654 	u8         cqe_version[0x4];
1655 
1656 	u8         compact_address_vector[0x1];
1657 	u8         striding_rq[0x1];
1658 	u8         reserved_at_202[0x1];
1659 	u8         ipoib_enhanced_offloads[0x1];
1660 	u8         ipoib_basic_offloads[0x1];
1661 	u8         reserved_at_205[0x1];
1662 	u8         repeated_block_disabled[0x1];
1663 	u8         umr_modify_entity_size_disabled[0x1];
1664 	u8         umr_modify_atomic_disabled[0x1];
1665 	u8         umr_indirect_mkey_disabled[0x1];
1666 	u8         umr_fence[0x2];
1667 	u8         dc_req_scat_data_cqe[0x1];
1668 	u8         reserved_at_20d[0x2];
1669 	u8         drain_sigerr[0x1];
1670 	u8         cmdif_checksum[0x2];
1671 	u8         sigerr_cqe[0x1];
1672 	u8         reserved_at_213[0x1];
1673 	u8         wq_signature[0x1];
1674 	u8         sctr_data_cqe[0x1];
1675 	u8         reserved_at_216[0x1];
1676 	u8         sho[0x1];
1677 	u8         tph[0x1];
1678 	u8         rf[0x1];
1679 	u8         dct[0x1];
1680 	u8         qos[0x1];
1681 	u8         eth_net_offloads[0x1];
1682 	u8         roce[0x1];
1683 	u8         atomic[0x1];
1684 	u8         reserved_at_21f[0x1];
1685 
1686 	u8         cq_oi[0x1];
1687 	u8         cq_resize[0x1];
1688 	u8         cq_moderation[0x1];
1689 	u8         cq_period_mode_modify[0x1];
1690 	u8         reserved_at_224[0x2];
1691 	u8         cq_eq_remap[0x1];
1692 	u8         pg[0x1];
1693 	u8         block_lb_mc[0x1];
1694 	u8         reserved_at_229[0x1];
1695 	u8         scqe_break_moderation[0x1];
1696 	u8         cq_period_start_from_cqe[0x1];
1697 	u8         cd[0x1];
1698 	u8         reserved_at_22d[0x1];
1699 	u8         apm[0x1];
1700 	u8         vector_calc[0x1];
1701 	u8         umr_ptr_rlky[0x1];
1702 	u8	   imaicl[0x1];
1703 	u8	   qp_packet_based[0x1];
1704 	u8         reserved_at_233[0x3];
1705 	u8         qkv[0x1];
1706 	u8         pkv[0x1];
1707 	u8         set_deth_sqpn[0x1];
1708 	u8         reserved_at_239[0x3];
1709 	u8         xrc[0x1];
1710 	u8         ud[0x1];
1711 	u8         uc[0x1];
1712 	u8         rc[0x1];
1713 
1714 	u8         uar_4k[0x1];
1715 	u8         reserved_at_241[0x7];
1716 	u8         fl_rc_qp_when_roce_disabled[0x1];
1717 	u8         regexp_params[0x1];
1718 	u8         uar_sz[0x6];
1719 	u8         port_selection_cap[0x1];
1720 	u8         reserved_at_251[0x1];
1721 	u8         umem_uid_0[0x1];
1722 	u8         reserved_at_253[0x5];
1723 	u8         log_pg_sz[0x8];
1724 
1725 	u8         bf[0x1];
1726 	u8         driver_version[0x1];
1727 	u8         pad_tx_eth_packet[0x1];
1728 	u8         reserved_at_263[0x3];
1729 	u8         mkey_by_name[0x1];
1730 	u8         reserved_at_267[0x4];
1731 
1732 	u8         log_bf_reg_size[0x5];
1733 
1734 	u8         reserved_at_270[0x3];
1735 	u8	   qp_error_syndrome[0x1];
1736 	u8	   reserved_at_274[0x2];
1737 	u8         lag_dct[0x2];
1738 	u8         lag_tx_port_affinity[0x1];
1739 	u8         lag_native_fdb_selection[0x1];
1740 	u8         reserved_at_27a[0x1];
1741 	u8         lag_master[0x1];
1742 	u8         num_lag_ports[0x4];
1743 
1744 	u8         reserved_at_280[0x10];
1745 	u8         max_wqe_sz_sq[0x10];
1746 
1747 	u8         reserved_at_2a0[0x10];
1748 	u8         max_wqe_sz_rq[0x10];
1749 
1750 	u8         max_flow_counter_31_16[0x10];
1751 	u8         max_wqe_sz_sq_dc[0x10];
1752 
1753 	u8         reserved_at_2e0[0x7];
1754 	u8         max_qp_mcg[0x19];
1755 
1756 	u8         reserved_at_300[0x10];
1757 	u8         flow_counter_bulk_alloc[0x8];
1758 	u8         log_max_mcg[0x8];
1759 
1760 	u8         reserved_at_320[0x3];
1761 	u8         log_max_transport_domain[0x5];
1762 	u8         reserved_at_328[0x2];
1763 	u8	   relaxed_ordering_read[0x1];
1764 	u8         log_max_pd[0x5];
1765 	u8         reserved_at_330[0x6];
1766 	u8         pci_sync_for_fw_update_with_driver_unload[0x1];
1767 	u8         vnic_env_cnt_steering_fail[0x1];
1768 	u8         vport_counter_local_loopback[0x1];
1769 	u8         q_counter_aggregation[0x1];
1770 	u8         q_counter_other_vport[0x1];
1771 	u8         log_max_xrcd[0x5];
1772 
1773 	u8         nic_receive_steering_discard[0x1];
1774 	u8         receive_discard_vport_down[0x1];
1775 	u8         transmit_discard_vport_down[0x1];
1776 	u8         eq_overrun_count[0x1];
1777 	u8         reserved_at_344[0x1];
1778 	u8         invalid_command_count[0x1];
1779 	u8         quota_exceeded_count[0x1];
1780 	u8         reserved_at_347[0x1];
1781 	u8         log_max_flow_counter_bulk[0x8];
1782 	u8         max_flow_counter_15_0[0x10];
1783 
1784 
1785 	u8         reserved_at_360[0x3];
1786 	u8         log_max_rq[0x5];
1787 	u8         reserved_at_368[0x3];
1788 	u8         log_max_sq[0x5];
1789 	u8         reserved_at_370[0x3];
1790 	u8         log_max_tir[0x5];
1791 	u8         reserved_at_378[0x3];
1792 	u8         log_max_tis[0x5];
1793 
1794 	u8         basic_cyclic_rcv_wqe[0x1];
1795 	u8         reserved_at_381[0x2];
1796 	u8         log_max_rmp[0x5];
1797 	u8         reserved_at_388[0x3];
1798 	u8         log_max_rqt[0x5];
1799 	u8         reserved_at_390[0x3];
1800 	u8         log_max_rqt_size[0x5];
1801 	u8         reserved_at_398[0x3];
1802 	u8         log_max_tis_per_sq[0x5];
1803 
1804 	u8         ext_stride_num_range[0x1];
1805 	u8         roce_rw_supported[0x1];
1806 	u8         log_max_current_uc_list_wr_supported[0x1];
1807 	u8         log_max_stride_sz_rq[0x5];
1808 	u8         reserved_at_3a8[0x3];
1809 	u8         log_min_stride_sz_rq[0x5];
1810 	u8         reserved_at_3b0[0x3];
1811 	u8         log_max_stride_sz_sq[0x5];
1812 	u8         reserved_at_3b8[0x3];
1813 	u8         log_min_stride_sz_sq[0x5];
1814 
1815 	u8         hairpin[0x1];
1816 	u8         reserved_at_3c1[0x2];
1817 	u8         log_max_hairpin_queues[0x5];
1818 	u8         reserved_at_3c8[0x3];
1819 	u8         log_max_hairpin_wq_data_sz[0x5];
1820 	u8         reserved_at_3d0[0x3];
1821 	u8         log_max_hairpin_num_packets[0x5];
1822 	u8         reserved_at_3d8[0x3];
1823 	u8         log_max_wq_sz[0x5];
1824 
1825 	u8         nic_vport_change_event[0x1];
1826 	u8         disable_local_lb_uc[0x1];
1827 	u8         disable_local_lb_mc[0x1];
1828 	u8         log_min_hairpin_wq_data_sz[0x5];
1829 	u8         reserved_at_3e8[0x1];
1830 	u8         silent_mode[0x1];
1831 	u8         vhca_state[0x1];
1832 	u8         log_max_vlan_list[0x5];
1833 	u8         reserved_at_3f0[0x3];
1834 	u8         log_max_current_mc_list[0x5];
1835 	u8         reserved_at_3f8[0x3];
1836 	u8         log_max_current_uc_list[0x5];
1837 
1838 	u8         general_obj_types[0x40];
1839 
1840 	u8         sq_ts_format[0x2];
1841 	u8         rq_ts_format[0x2];
1842 	u8         steering_format_version[0x4];
1843 	u8         create_qp_start_hint[0x18];
1844 
1845 	u8         reserved_at_460[0x1];
1846 	u8         ats[0x1];
1847 	u8         cross_vhca_rqt[0x1];
1848 	u8         log_max_uctx[0x5];
1849 	u8         reserved_at_468[0x1];
1850 	u8         crypto[0x1];
1851 	u8         ipsec_offload[0x1];
1852 	u8         log_max_umem[0x5];
1853 	u8         max_num_eqs[0x10];
1854 
1855 	u8         reserved_at_480[0x1];
1856 	u8         tls_tx[0x1];
1857 	u8         tls_rx[0x1];
1858 	u8         log_max_l2_table[0x5];
1859 	u8         reserved_at_488[0x8];
1860 	u8         log_uar_page_sz[0x10];
1861 
1862 	u8         reserved_at_4a0[0x20];
1863 	u8         device_frequency_mhz[0x20];
1864 	u8         device_frequency_khz[0x20];
1865 
1866 	u8         reserved_at_500[0x20];
1867 	u8	   num_of_uars_per_page[0x20];
1868 
1869 	u8         flex_parser_protocols[0x20];
1870 
1871 	u8         max_geneve_tlv_options[0x8];
1872 	u8         reserved_at_568[0x3];
1873 	u8         max_geneve_tlv_option_data_len[0x5];
1874 	u8         reserved_at_570[0x9];
1875 	u8         adv_virtualization[0x1];
1876 	u8         reserved_at_57a[0x6];
1877 
1878 	u8	   reserved_at_580[0xb];
1879 	u8	   log_max_dci_stream_channels[0x5];
1880 	u8	   reserved_at_590[0x3];
1881 	u8	   log_max_dci_errored_streams[0x5];
1882 	u8	   reserved_at_598[0x8];
1883 
1884 	u8         reserved_at_5a0[0x10];
1885 	u8         enhanced_cqe_compression[0x1];
1886 	u8         reserved_at_5b1[0x2];
1887 	u8         log_max_dek[0x5];
1888 	u8         reserved_at_5b8[0x4];
1889 	u8         mini_cqe_resp_stride_index[0x1];
1890 	u8         cqe_128_always[0x1];
1891 	u8         cqe_compression_128[0x1];
1892 	u8         cqe_compression[0x1];
1893 
1894 	u8         cqe_compression_timeout[0x10];
1895 	u8         cqe_compression_max_num[0x10];
1896 
1897 	u8         reserved_at_5e0[0x8];
1898 	u8         flex_parser_id_gtpu_dw_0[0x4];
1899 	u8         reserved_at_5ec[0x4];
1900 	u8         tag_matching[0x1];
1901 	u8         rndv_offload_rc[0x1];
1902 	u8         rndv_offload_dc[0x1];
1903 	u8         log_tag_matching_list_sz[0x5];
1904 	u8         reserved_at_5f8[0x3];
1905 	u8         log_max_xrq[0x5];
1906 
1907 	u8	   affiliate_nic_vport_criteria[0x8];
1908 	u8	   native_port_num[0x8];
1909 	u8	   num_vhca_ports[0x8];
1910 	u8         flex_parser_id_gtpu_teid[0x4];
1911 	u8         reserved_at_61c[0x2];
1912 	u8	   sw_owner_id[0x1];
1913 	u8         reserved_at_61f[0x1];
1914 
1915 	u8         max_num_of_monitor_counters[0x10];
1916 	u8         num_ppcnt_monitor_counters[0x10];
1917 
1918 	u8         max_num_sf[0x10];
1919 	u8         num_q_monitor_counters[0x10];
1920 
1921 	u8         reserved_at_660[0x20];
1922 
1923 	u8         sf[0x1];
1924 	u8         sf_set_partition[0x1];
1925 	u8         reserved_at_682[0x1];
1926 	u8         log_max_sf[0x5];
1927 	u8         apu[0x1];
1928 	u8         reserved_at_689[0x4];
1929 	u8         migration[0x1];
1930 	u8         reserved_at_68e[0x2];
1931 	u8         log_min_sf_size[0x8];
1932 	u8         max_num_sf_partitions[0x8];
1933 
1934 	u8         uctx_cap[0x20];
1935 
1936 	u8         reserved_at_6c0[0x4];
1937 	u8         flex_parser_id_geneve_tlv_option_0[0x4];
1938 	u8         flex_parser_id_icmp_dw1[0x4];
1939 	u8         flex_parser_id_icmp_dw0[0x4];
1940 	u8         flex_parser_id_icmpv6_dw1[0x4];
1941 	u8         flex_parser_id_icmpv6_dw0[0x4];
1942 	u8         flex_parser_id_outer_first_mpls_over_gre[0x4];
1943 	u8         flex_parser_id_outer_first_mpls_over_udp_label[0x4];
1944 
1945 	u8         max_num_match_definer[0x10];
1946 	u8	   sf_base_id[0x10];
1947 
1948 	u8         flex_parser_id_gtpu_dw_2[0x4];
1949 	u8         flex_parser_id_gtpu_first_ext_dw_0[0x4];
1950 	u8	   num_total_dynamic_vf_msix[0x18];
1951 	u8	   reserved_at_720[0x14];
1952 	u8	   dynamic_msix_table_size[0xc];
1953 	u8	   reserved_at_740[0xc];
1954 	u8	   min_dynamic_vf_msix_table_size[0x4];
1955 	u8	   reserved_at_750[0x4];
1956 	u8	   max_dynamic_vf_msix_table_size[0xc];
1957 
1958 	u8         reserved_at_760[0x3];
1959 	u8         log_max_num_header_modify_argument[0x5];
1960 	u8         reserved_at_768[0x4];
1961 	u8         log_header_modify_argument_granularity[0x4];
1962 	u8         reserved_at_770[0x3];
1963 	u8         log_header_modify_argument_max_alloc[0x5];
1964 	u8         reserved_at_778[0x8];
1965 
1966 	u8	   vhca_tunnel_commands[0x40];
1967 	u8         match_definer_format_supported[0x40];
1968 };
1969 
1970 enum {
1971 	MLX5_CROSS_VHCA_OBJ_TO_OBJ_SUPPORTED_LOCAL_FLOW_TABLE_TO_REMOTE_FLOW_TABLE_MISS  = 0x80000,
1972 	MLX5_CROSS_VHCA_OBJ_TO_OBJ_SUPPORTED_LOCAL_FLOW_TABLE_ROOT_TO_REMOTE_FLOW_TABLE  = (1ULL << 20),
1973 };
1974 
1975 enum {
1976 	MLX5_ALLOWED_OBJ_FOR_OTHER_VHCA_ACCESS_FLOW_TABLE       = 0x200,
1977 };
1978 
1979 struct mlx5_ifc_cmd_hca_cap_2_bits {
1980 	u8	   reserved_at_0[0x80];
1981 
1982 	u8         migratable[0x1];
1983 	u8         reserved_at_81[0x1f];
1984 
1985 	u8	   max_reformat_insert_size[0x8];
1986 	u8	   max_reformat_insert_offset[0x8];
1987 	u8	   max_reformat_remove_size[0x8];
1988 	u8	   max_reformat_remove_offset[0x8];
1989 
1990 	u8	   reserved_at_c0[0x8];
1991 	u8	   migration_multi_load[0x1];
1992 	u8	   migration_tracking_state[0x1];
1993 	u8	   reserved_at_ca[0x6];
1994 	u8	   migration_in_chunks[0x1];
1995 	u8	   reserved_at_d1[0xf];
1996 
1997 	u8	   cross_vhca_object_to_object_supported[0x20];
1998 
1999 	u8	   allowed_object_for_other_vhca_access[0x40];
2000 
2001 	u8	   reserved_at_140[0x60];
2002 
2003 	u8	   flow_table_type_2_type[0x8];
2004 	u8	   reserved_at_1a8[0x3];
2005 	u8	   log_min_mkey_entity_size[0x5];
2006 	u8	   reserved_at_1b0[0x10];
2007 
2008 	u8	   reserved_at_1c0[0x60];
2009 
2010 	u8	   reserved_at_220[0x1];
2011 	u8	   sw_vhca_id_valid[0x1];
2012 	u8	   sw_vhca_id[0xe];
2013 	u8	   reserved_at_230[0x10];
2014 
2015 	u8	   reserved_at_240[0xb];
2016 	u8	   ts_cqe_metadata_size2wqe_counter[0x5];
2017 	u8	   reserved_at_250[0x10];
2018 
2019 	u8	   reserved_at_260[0x120];
2020 	u8	   reserved_at_380[0x10];
2021 	u8	   ec_vf_vport_base[0x10];
2022 
2023 	u8	   reserved_at_3a0[0x10];
2024 	u8	   max_rqt_vhca_id[0x10];
2025 
2026 	u8	   reserved_at_3c0[0x20];
2027 
2028 	u8	   reserved_at_3e0[0x10];
2029 	u8	   pcc_ifa2[0x1];
2030 	u8	   reserved_at_3f1[0xf];
2031 
2032 	u8	   reserved_at_400[0x40];
2033 
2034 	u8	   reserved_at_440[0x8];
2035 	u8	   max_num_eqs_24b[0x18];
2036 	u8	   reserved_at_460[0x3a0];
2037 };
2038 
2039 enum mlx5_ifc_flow_destination_type {
2040 	MLX5_IFC_FLOW_DESTINATION_TYPE_VPORT        = 0x0,
2041 	MLX5_IFC_FLOW_DESTINATION_TYPE_FLOW_TABLE   = 0x1,
2042 	MLX5_IFC_FLOW_DESTINATION_TYPE_TIR          = 0x2,
2043 	MLX5_IFC_FLOW_DESTINATION_TYPE_FLOW_SAMPLER = 0x6,
2044 	MLX5_IFC_FLOW_DESTINATION_TYPE_UPLINK       = 0x8,
2045 	MLX5_IFC_FLOW_DESTINATION_TYPE_TABLE_TYPE   = 0xA,
2046 };
2047 
2048 enum mlx5_flow_table_miss_action {
2049 	MLX5_FLOW_TABLE_MISS_ACTION_DEF,
2050 	MLX5_FLOW_TABLE_MISS_ACTION_FWD,
2051 	MLX5_FLOW_TABLE_MISS_ACTION_SWITCH_DOMAIN,
2052 };
2053 
2054 struct mlx5_ifc_dest_format_struct_bits {
2055 	u8         destination_type[0x8];
2056 	u8         destination_id[0x18];
2057 
2058 	u8         destination_eswitch_owner_vhca_id_valid[0x1];
2059 	u8         packet_reformat[0x1];
2060 	u8         reserved_at_22[0x6];
2061 	u8         destination_table_type[0x8];
2062 	u8         destination_eswitch_owner_vhca_id[0x10];
2063 };
2064 
2065 struct mlx5_ifc_flow_counter_list_bits {
2066 	u8         flow_counter_id[0x20];
2067 
2068 	u8         reserved_at_20[0x20];
2069 };
2070 
2071 struct mlx5_ifc_extended_dest_format_bits {
2072 	struct mlx5_ifc_dest_format_struct_bits destination_entry;
2073 
2074 	u8         packet_reformat_id[0x20];
2075 
2076 	u8         reserved_at_60[0x20];
2077 };
2078 
2079 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits {
2080 	struct mlx5_ifc_extended_dest_format_bits extended_dest_format;
2081 	struct mlx5_ifc_flow_counter_list_bits flow_counter_list;
2082 };
2083 
2084 struct mlx5_ifc_fte_match_param_bits {
2085 	struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
2086 
2087 	struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
2088 
2089 	struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
2090 
2091 	struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2;
2092 
2093 	struct mlx5_ifc_fte_match_set_misc3_bits misc_parameters_3;
2094 
2095 	struct mlx5_ifc_fte_match_set_misc4_bits misc_parameters_4;
2096 
2097 	struct mlx5_ifc_fte_match_set_misc5_bits misc_parameters_5;
2098 
2099 	u8         reserved_at_e00[0x200];
2100 };
2101 
2102 enum {
2103 	MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP     = 0x0,
2104 	MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP     = 0x1,
2105 	MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT   = 0x2,
2106 	MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT   = 0x3,
2107 	MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI  = 0x4,
2108 };
2109 
2110 struct mlx5_ifc_rx_hash_field_select_bits {
2111 	u8         l3_prot_type[0x1];
2112 	u8         l4_prot_type[0x1];
2113 	u8         selected_fields[0x1e];
2114 };
2115 
2116 enum {
2117 	MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST  = 0x0,
2118 	MLX5_WQ_WQ_TYPE_WQ_CYCLIC       = 0x1,
2119 };
2120 
2121 enum {
2122 	MLX5_WQ_END_PADDING_MODE_END_PAD_NONE   = 0x0,
2123 	MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN  = 0x1,
2124 };
2125 
2126 struct mlx5_ifc_wq_bits {
2127 	u8         wq_type[0x4];
2128 	u8         wq_signature[0x1];
2129 	u8         end_padding_mode[0x2];
2130 	u8         cd_slave[0x1];
2131 	u8         reserved_at_8[0x18];
2132 
2133 	u8         hds_skip_first_sge[0x1];
2134 	u8         log2_hds_buf_size[0x3];
2135 	u8         reserved_at_24[0x7];
2136 	u8         page_offset[0x5];
2137 	u8         lwm[0x10];
2138 
2139 	u8         reserved_at_40[0x8];
2140 	u8         pd[0x18];
2141 
2142 	u8         reserved_at_60[0x8];
2143 	u8         uar_page[0x18];
2144 
2145 	u8         dbr_addr[0x40];
2146 
2147 	u8         hw_counter[0x20];
2148 
2149 	u8         sw_counter[0x20];
2150 
2151 	u8         reserved_at_100[0xc];
2152 	u8         log_wq_stride[0x4];
2153 	u8         reserved_at_110[0x3];
2154 	u8         log_wq_pg_sz[0x5];
2155 	u8         reserved_at_118[0x3];
2156 	u8         log_wq_sz[0x5];
2157 
2158 	u8         dbr_umem_valid[0x1];
2159 	u8         wq_umem_valid[0x1];
2160 	u8         reserved_at_122[0x1];
2161 	u8         log_hairpin_num_packets[0x5];
2162 	u8         reserved_at_128[0x3];
2163 	u8         log_hairpin_data_sz[0x5];
2164 
2165 	u8         reserved_at_130[0x4];
2166 	u8         log_wqe_num_of_strides[0x4];
2167 	u8         two_byte_shift_en[0x1];
2168 	u8         reserved_at_139[0x4];
2169 	u8         log_wqe_stride_size[0x3];
2170 
2171 	u8         reserved_at_140[0x80];
2172 
2173 	u8         headers_mkey[0x20];
2174 
2175 	u8         shampo_enable[0x1];
2176 	u8         reserved_at_1e1[0x4];
2177 	u8         log_reservation_size[0x3];
2178 	u8         reserved_at_1e8[0x5];
2179 	u8         log_max_num_of_packets_per_reservation[0x3];
2180 	u8         reserved_at_1f0[0x6];
2181 	u8         log_headers_entry_size[0x2];
2182 	u8         reserved_at_1f8[0x4];
2183 	u8         log_headers_buffer_entry_num[0x4];
2184 
2185 	u8         reserved_at_200[0x400];
2186 
2187 	struct mlx5_ifc_cmd_pas_bits pas[];
2188 };
2189 
2190 struct mlx5_ifc_rq_num_bits {
2191 	u8         reserved_at_0[0x8];
2192 	u8         rq_num[0x18];
2193 };
2194 
2195 struct mlx5_ifc_rq_vhca_bits {
2196 	u8         reserved_at_0[0x8];
2197 	u8         rq_num[0x18];
2198 	u8         reserved_at_20[0x10];
2199 	u8         rq_vhca_id[0x10];
2200 };
2201 
2202 struct mlx5_ifc_mac_address_layout_bits {
2203 	u8         reserved_at_0[0x10];
2204 	u8         mac_addr_47_32[0x10];
2205 
2206 	u8         mac_addr_31_0[0x20];
2207 };
2208 
2209 struct mlx5_ifc_vlan_layout_bits {
2210 	u8         reserved_at_0[0x14];
2211 	u8         vlan[0x0c];
2212 
2213 	u8         reserved_at_20[0x20];
2214 };
2215 
2216 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
2217 	u8         reserved_at_0[0xa0];
2218 
2219 	u8         min_time_between_cnps[0x20];
2220 
2221 	u8         reserved_at_c0[0x12];
2222 	u8         cnp_dscp[0x6];
2223 	u8         reserved_at_d8[0x4];
2224 	u8         cnp_prio_mode[0x1];
2225 	u8         cnp_802p_prio[0x3];
2226 
2227 	u8         reserved_at_e0[0x720];
2228 };
2229 
2230 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
2231 	u8         reserved_at_0[0x60];
2232 
2233 	u8         reserved_at_60[0x4];
2234 	u8         clamp_tgt_rate[0x1];
2235 	u8         reserved_at_65[0x3];
2236 	u8         clamp_tgt_rate_after_time_inc[0x1];
2237 	u8         reserved_at_69[0x17];
2238 
2239 	u8         reserved_at_80[0x20];
2240 
2241 	u8         rpg_time_reset[0x20];
2242 
2243 	u8         rpg_byte_reset[0x20];
2244 
2245 	u8         rpg_threshold[0x20];
2246 
2247 	u8         rpg_max_rate[0x20];
2248 
2249 	u8         rpg_ai_rate[0x20];
2250 
2251 	u8         rpg_hai_rate[0x20];
2252 
2253 	u8         rpg_gd[0x20];
2254 
2255 	u8         rpg_min_dec_fac[0x20];
2256 
2257 	u8         rpg_min_rate[0x20];
2258 
2259 	u8         reserved_at_1c0[0xe0];
2260 
2261 	u8         rate_to_set_on_first_cnp[0x20];
2262 
2263 	u8         dce_tcp_g[0x20];
2264 
2265 	u8         dce_tcp_rtt[0x20];
2266 
2267 	u8         rate_reduce_monitor_period[0x20];
2268 
2269 	u8         reserved_at_320[0x20];
2270 
2271 	u8         initial_alpha_value[0x20];
2272 
2273 	u8         reserved_at_360[0x4a0];
2274 };
2275 
2276 struct mlx5_ifc_cong_control_r_roce_general_bits {
2277 	u8         reserved_at_0[0x80];
2278 
2279 	u8         reserved_at_80[0x10];
2280 	u8         rtt_resp_dscp_valid[0x1];
2281 	u8         reserved_at_91[0x9];
2282 	u8         rtt_resp_dscp[0x6];
2283 
2284 	u8         reserved_at_a0[0x760];
2285 };
2286 
2287 struct mlx5_ifc_cong_control_802_1qau_rp_bits {
2288 	u8         reserved_at_0[0x80];
2289 
2290 	u8         rppp_max_rps[0x20];
2291 
2292 	u8         rpg_time_reset[0x20];
2293 
2294 	u8         rpg_byte_reset[0x20];
2295 
2296 	u8         rpg_threshold[0x20];
2297 
2298 	u8         rpg_max_rate[0x20];
2299 
2300 	u8         rpg_ai_rate[0x20];
2301 
2302 	u8         rpg_hai_rate[0x20];
2303 
2304 	u8         rpg_gd[0x20];
2305 
2306 	u8         rpg_min_dec_fac[0x20];
2307 
2308 	u8         rpg_min_rate[0x20];
2309 
2310 	u8         reserved_at_1c0[0x640];
2311 };
2312 
2313 enum {
2314 	MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE    = 0x1,
2315 	MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET    = 0x2,
2316 	MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE  = 0x4,
2317 };
2318 
2319 struct mlx5_ifc_resize_field_select_bits {
2320 	u8         resize_field_select[0x20];
2321 };
2322 
2323 struct mlx5_ifc_resource_dump_bits {
2324 	u8         more_dump[0x1];
2325 	u8         inline_dump[0x1];
2326 	u8         reserved_at_2[0xa];
2327 	u8         seq_num[0x4];
2328 	u8         segment_type[0x10];
2329 
2330 	u8         reserved_at_20[0x10];
2331 	u8         vhca_id[0x10];
2332 
2333 	u8         index1[0x20];
2334 
2335 	u8         index2[0x20];
2336 
2337 	u8         num_of_obj1[0x10];
2338 	u8         num_of_obj2[0x10];
2339 
2340 	u8         reserved_at_a0[0x20];
2341 
2342 	u8         device_opaque[0x40];
2343 
2344 	u8         mkey[0x20];
2345 
2346 	u8         size[0x20];
2347 
2348 	u8         address[0x40];
2349 
2350 	u8         inline_data[52][0x20];
2351 };
2352 
2353 struct mlx5_ifc_resource_dump_menu_record_bits {
2354 	u8         reserved_at_0[0x4];
2355 	u8         num_of_obj2_supports_active[0x1];
2356 	u8         num_of_obj2_supports_all[0x1];
2357 	u8         must_have_num_of_obj2[0x1];
2358 	u8         support_num_of_obj2[0x1];
2359 	u8         num_of_obj1_supports_active[0x1];
2360 	u8         num_of_obj1_supports_all[0x1];
2361 	u8         must_have_num_of_obj1[0x1];
2362 	u8         support_num_of_obj1[0x1];
2363 	u8         must_have_index2[0x1];
2364 	u8         support_index2[0x1];
2365 	u8         must_have_index1[0x1];
2366 	u8         support_index1[0x1];
2367 	u8         segment_type[0x10];
2368 
2369 	u8         segment_name[4][0x20];
2370 
2371 	u8         index1_name[4][0x20];
2372 
2373 	u8         index2_name[4][0x20];
2374 };
2375 
2376 struct mlx5_ifc_resource_dump_segment_header_bits {
2377 	u8         length_dw[0x10];
2378 	u8         segment_type[0x10];
2379 };
2380 
2381 struct mlx5_ifc_resource_dump_command_segment_bits {
2382 	struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2383 
2384 	u8         segment_called[0x10];
2385 	u8         vhca_id[0x10];
2386 
2387 	u8         index1[0x20];
2388 
2389 	u8         index2[0x20];
2390 
2391 	u8         num_of_obj1[0x10];
2392 	u8         num_of_obj2[0x10];
2393 };
2394 
2395 struct mlx5_ifc_resource_dump_error_segment_bits {
2396 	struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2397 
2398 	u8         reserved_at_20[0x10];
2399 	u8         syndrome_id[0x10];
2400 
2401 	u8         reserved_at_40[0x40];
2402 
2403 	u8         error[8][0x20];
2404 };
2405 
2406 struct mlx5_ifc_resource_dump_info_segment_bits {
2407 	struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2408 
2409 	u8         reserved_at_20[0x18];
2410 	u8         dump_version[0x8];
2411 
2412 	u8         hw_version[0x20];
2413 
2414 	u8         fw_version[0x20];
2415 };
2416 
2417 struct mlx5_ifc_resource_dump_menu_segment_bits {
2418 	struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2419 
2420 	u8         reserved_at_20[0x10];
2421 	u8         num_of_records[0x10];
2422 
2423 	struct mlx5_ifc_resource_dump_menu_record_bits record[];
2424 };
2425 
2426 struct mlx5_ifc_resource_dump_resource_segment_bits {
2427 	struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2428 
2429 	u8         reserved_at_20[0x20];
2430 
2431 	u8         index1[0x20];
2432 
2433 	u8         index2[0x20];
2434 
2435 	u8         payload[][0x20];
2436 };
2437 
2438 struct mlx5_ifc_resource_dump_terminate_segment_bits {
2439 	struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2440 };
2441 
2442 struct mlx5_ifc_menu_resource_dump_response_bits {
2443 	struct mlx5_ifc_resource_dump_info_segment_bits info;
2444 	struct mlx5_ifc_resource_dump_command_segment_bits cmd;
2445 	struct mlx5_ifc_resource_dump_menu_segment_bits menu;
2446 	struct mlx5_ifc_resource_dump_terminate_segment_bits terminate;
2447 };
2448 
2449 enum {
2450 	MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD     = 0x1,
2451 	MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT  = 0x2,
2452 	MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI            = 0x4,
2453 	MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN         = 0x8,
2454 };
2455 
2456 struct mlx5_ifc_modify_field_select_bits {
2457 	u8         modify_field_select[0x20];
2458 };
2459 
2460 struct mlx5_ifc_field_select_r_roce_np_bits {
2461 	u8         field_select_r_roce_np[0x20];
2462 };
2463 
2464 struct mlx5_ifc_field_select_r_roce_rp_bits {
2465 	u8         field_select_r_roce_rp[0x20];
2466 };
2467 
2468 enum {
2469 	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS     = 0x4,
2470 	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET   = 0x8,
2471 	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET   = 0x10,
2472 	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD    = 0x20,
2473 	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE     = 0x40,
2474 	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE      = 0x80,
2475 	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE     = 0x100,
2476 	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD           = 0x200,
2477 	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC  = 0x400,
2478 	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE     = 0x800,
2479 };
2480 
2481 struct mlx5_ifc_field_select_802_1qau_rp_bits {
2482 	u8         field_select_8021qaurp[0x20];
2483 };
2484 
2485 struct mlx5_ifc_phys_layer_cntrs_bits {
2486 	u8         time_since_last_clear_high[0x20];
2487 
2488 	u8         time_since_last_clear_low[0x20];
2489 
2490 	u8         symbol_errors_high[0x20];
2491 
2492 	u8         symbol_errors_low[0x20];
2493 
2494 	u8         sync_headers_errors_high[0x20];
2495 
2496 	u8         sync_headers_errors_low[0x20];
2497 
2498 	u8         edpl_bip_errors_lane0_high[0x20];
2499 
2500 	u8         edpl_bip_errors_lane0_low[0x20];
2501 
2502 	u8         edpl_bip_errors_lane1_high[0x20];
2503 
2504 	u8         edpl_bip_errors_lane1_low[0x20];
2505 
2506 	u8         edpl_bip_errors_lane2_high[0x20];
2507 
2508 	u8         edpl_bip_errors_lane2_low[0x20];
2509 
2510 	u8         edpl_bip_errors_lane3_high[0x20];
2511 
2512 	u8         edpl_bip_errors_lane3_low[0x20];
2513 
2514 	u8         fc_fec_corrected_blocks_lane0_high[0x20];
2515 
2516 	u8         fc_fec_corrected_blocks_lane0_low[0x20];
2517 
2518 	u8         fc_fec_corrected_blocks_lane1_high[0x20];
2519 
2520 	u8         fc_fec_corrected_blocks_lane1_low[0x20];
2521 
2522 	u8         fc_fec_corrected_blocks_lane2_high[0x20];
2523 
2524 	u8         fc_fec_corrected_blocks_lane2_low[0x20];
2525 
2526 	u8         fc_fec_corrected_blocks_lane3_high[0x20];
2527 
2528 	u8         fc_fec_corrected_blocks_lane3_low[0x20];
2529 
2530 	u8         fc_fec_uncorrectable_blocks_lane0_high[0x20];
2531 
2532 	u8         fc_fec_uncorrectable_blocks_lane0_low[0x20];
2533 
2534 	u8         fc_fec_uncorrectable_blocks_lane1_high[0x20];
2535 
2536 	u8         fc_fec_uncorrectable_blocks_lane1_low[0x20];
2537 
2538 	u8         fc_fec_uncorrectable_blocks_lane2_high[0x20];
2539 
2540 	u8         fc_fec_uncorrectable_blocks_lane2_low[0x20];
2541 
2542 	u8         fc_fec_uncorrectable_blocks_lane3_high[0x20];
2543 
2544 	u8         fc_fec_uncorrectable_blocks_lane3_low[0x20];
2545 
2546 	u8         rs_fec_corrected_blocks_high[0x20];
2547 
2548 	u8         rs_fec_corrected_blocks_low[0x20];
2549 
2550 	u8         rs_fec_uncorrectable_blocks_high[0x20];
2551 
2552 	u8         rs_fec_uncorrectable_blocks_low[0x20];
2553 
2554 	u8         rs_fec_no_errors_blocks_high[0x20];
2555 
2556 	u8         rs_fec_no_errors_blocks_low[0x20];
2557 
2558 	u8         rs_fec_single_error_blocks_high[0x20];
2559 
2560 	u8         rs_fec_single_error_blocks_low[0x20];
2561 
2562 	u8         rs_fec_corrected_symbols_total_high[0x20];
2563 
2564 	u8         rs_fec_corrected_symbols_total_low[0x20];
2565 
2566 	u8         rs_fec_corrected_symbols_lane0_high[0x20];
2567 
2568 	u8         rs_fec_corrected_symbols_lane0_low[0x20];
2569 
2570 	u8         rs_fec_corrected_symbols_lane1_high[0x20];
2571 
2572 	u8         rs_fec_corrected_symbols_lane1_low[0x20];
2573 
2574 	u8         rs_fec_corrected_symbols_lane2_high[0x20];
2575 
2576 	u8         rs_fec_corrected_symbols_lane2_low[0x20];
2577 
2578 	u8         rs_fec_corrected_symbols_lane3_high[0x20];
2579 
2580 	u8         rs_fec_corrected_symbols_lane3_low[0x20];
2581 
2582 	u8         link_down_events[0x20];
2583 
2584 	u8         successful_recovery_events[0x20];
2585 
2586 	u8         reserved_at_640[0x180];
2587 };
2588 
2589 struct mlx5_ifc_phys_layer_statistical_cntrs_bits {
2590 	u8         time_since_last_clear_high[0x20];
2591 
2592 	u8         time_since_last_clear_low[0x20];
2593 
2594 	u8         phy_received_bits_high[0x20];
2595 
2596 	u8         phy_received_bits_low[0x20];
2597 
2598 	u8         phy_symbol_errors_high[0x20];
2599 
2600 	u8         phy_symbol_errors_low[0x20];
2601 
2602 	u8         phy_corrected_bits_high[0x20];
2603 
2604 	u8         phy_corrected_bits_low[0x20];
2605 
2606 	u8         phy_corrected_bits_lane0_high[0x20];
2607 
2608 	u8         phy_corrected_bits_lane0_low[0x20];
2609 
2610 	u8         phy_corrected_bits_lane1_high[0x20];
2611 
2612 	u8         phy_corrected_bits_lane1_low[0x20];
2613 
2614 	u8         phy_corrected_bits_lane2_high[0x20];
2615 
2616 	u8         phy_corrected_bits_lane2_low[0x20];
2617 
2618 	u8         phy_corrected_bits_lane3_high[0x20];
2619 
2620 	u8         phy_corrected_bits_lane3_low[0x20];
2621 
2622 	u8         reserved_at_200[0x5c0];
2623 };
2624 
2625 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits {
2626 	u8	   symbol_error_counter[0x10];
2627 
2628 	u8         link_error_recovery_counter[0x8];
2629 
2630 	u8         link_downed_counter[0x8];
2631 
2632 	u8         port_rcv_errors[0x10];
2633 
2634 	u8         port_rcv_remote_physical_errors[0x10];
2635 
2636 	u8         port_rcv_switch_relay_errors[0x10];
2637 
2638 	u8         port_xmit_discards[0x10];
2639 
2640 	u8         port_xmit_constraint_errors[0x8];
2641 
2642 	u8         port_rcv_constraint_errors[0x8];
2643 
2644 	u8         reserved_at_70[0x8];
2645 
2646 	u8         link_overrun_errors[0x8];
2647 
2648 	u8	   reserved_at_80[0x10];
2649 
2650 	u8         vl_15_dropped[0x10];
2651 
2652 	u8	   reserved_at_a0[0x80];
2653 
2654 	u8         port_xmit_wait[0x20];
2655 };
2656 
2657 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits {
2658 	u8         transmit_queue_high[0x20];
2659 
2660 	u8         transmit_queue_low[0x20];
2661 
2662 	u8         no_buffer_discard_uc_high[0x20];
2663 
2664 	u8         no_buffer_discard_uc_low[0x20];
2665 
2666 	u8         reserved_at_80[0x740];
2667 };
2668 
2669 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits {
2670 	u8         wred_discard_high[0x20];
2671 
2672 	u8         wred_discard_low[0x20];
2673 
2674 	u8         ecn_marked_tc_high[0x20];
2675 
2676 	u8         ecn_marked_tc_low[0x20];
2677 
2678 	u8         reserved_at_80[0x740];
2679 };
2680 
2681 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
2682 	u8         rx_octets_high[0x20];
2683 
2684 	u8         rx_octets_low[0x20];
2685 
2686 	u8         reserved_at_40[0xc0];
2687 
2688 	u8         rx_frames_high[0x20];
2689 
2690 	u8         rx_frames_low[0x20];
2691 
2692 	u8         tx_octets_high[0x20];
2693 
2694 	u8         tx_octets_low[0x20];
2695 
2696 	u8         reserved_at_180[0xc0];
2697 
2698 	u8         tx_frames_high[0x20];
2699 
2700 	u8         tx_frames_low[0x20];
2701 
2702 	u8         rx_pause_high[0x20];
2703 
2704 	u8         rx_pause_low[0x20];
2705 
2706 	u8         rx_pause_duration_high[0x20];
2707 
2708 	u8         rx_pause_duration_low[0x20];
2709 
2710 	u8         tx_pause_high[0x20];
2711 
2712 	u8         tx_pause_low[0x20];
2713 
2714 	u8         tx_pause_duration_high[0x20];
2715 
2716 	u8         tx_pause_duration_low[0x20];
2717 
2718 	u8         rx_pause_transition_high[0x20];
2719 
2720 	u8         rx_pause_transition_low[0x20];
2721 
2722 	u8         rx_discards_high[0x20];
2723 
2724 	u8         rx_discards_low[0x20];
2725 
2726 	u8         device_stall_minor_watermark_cnt_high[0x20];
2727 
2728 	u8         device_stall_minor_watermark_cnt_low[0x20];
2729 
2730 	u8         device_stall_critical_watermark_cnt_high[0x20];
2731 
2732 	u8         device_stall_critical_watermark_cnt_low[0x20];
2733 
2734 	u8         reserved_at_480[0x340];
2735 };
2736 
2737 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
2738 	u8         port_transmit_wait_high[0x20];
2739 
2740 	u8         port_transmit_wait_low[0x20];
2741 
2742 	u8         reserved_at_40[0x100];
2743 
2744 	u8         rx_buffer_almost_full_high[0x20];
2745 
2746 	u8         rx_buffer_almost_full_low[0x20];
2747 
2748 	u8         rx_buffer_full_high[0x20];
2749 
2750 	u8         rx_buffer_full_low[0x20];
2751 
2752 	u8         rx_icrc_encapsulated_high[0x20];
2753 
2754 	u8         rx_icrc_encapsulated_low[0x20];
2755 
2756 	u8         reserved_at_200[0x5c0];
2757 };
2758 
2759 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
2760 	u8         dot3stats_alignment_errors_high[0x20];
2761 
2762 	u8         dot3stats_alignment_errors_low[0x20];
2763 
2764 	u8         dot3stats_fcs_errors_high[0x20];
2765 
2766 	u8         dot3stats_fcs_errors_low[0x20];
2767 
2768 	u8         dot3stats_single_collision_frames_high[0x20];
2769 
2770 	u8         dot3stats_single_collision_frames_low[0x20];
2771 
2772 	u8         dot3stats_multiple_collision_frames_high[0x20];
2773 
2774 	u8         dot3stats_multiple_collision_frames_low[0x20];
2775 
2776 	u8         dot3stats_sqe_test_errors_high[0x20];
2777 
2778 	u8         dot3stats_sqe_test_errors_low[0x20];
2779 
2780 	u8         dot3stats_deferred_transmissions_high[0x20];
2781 
2782 	u8         dot3stats_deferred_transmissions_low[0x20];
2783 
2784 	u8         dot3stats_late_collisions_high[0x20];
2785 
2786 	u8         dot3stats_late_collisions_low[0x20];
2787 
2788 	u8         dot3stats_excessive_collisions_high[0x20];
2789 
2790 	u8         dot3stats_excessive_collisions_low[0x20];
2791 
2792 	u8         dot3stats_internal_mac_transmit_errors_high[0x20];
2793 
2794 	u8         dot3stats_internal_mac_transmit_errors_low[0x20];
2795 
2796 	u8         dot3stats_carrier_sense_errors_high[0x20];
2797 
2798 	u8         dot3stats_carrier_sense_errors_low[0x20];
2799 
2800 	u8         dot3stats_frame_too_longs_high[0x20];
2801 
2802 	u8         dot3stats_frame_too_longs_low[0x20];
2803 
2804 	u8         dot3stats_internal_mac_receive_errors_high[0x20];
2805 
2806 	u8         dot3stats_internal_mac_receive_errors_low[0x20];
2807 
2808 	u8         dot3stats_symbol_errors_high[0x20];
2809 
2810 	u8         dot3stats_symbol_errors_low[0x20];
2811 
2812 	u8         dot3control_in_unknown_opcodes_high[0x20];
2813 
2814 	u8         dot3control_in_unknown_opcodes_low[0x20];
2815 
2816 	u8         dot3in_pause_frames_high[0x20];
2817 
2818 	u8         dot3in_pause_frames_low[0x20];
2819 
2820 	u8         dot3out_pause_frames_high[0x20];
2821 
2822 	u8         dot3out_pause_frames_low[0x20];
2823 
2824 	u8         reserved_at_400[0x3c0];
2825 };
2826 
2827 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
2828 	u8         ether_stats_drop_events_high[0x20];
2829 
2830 	u8         ether_stats_drop_events_low[0x20];
2831 
2832 	u8         ether_stats_octets_high[0x20];
2833 
2834 	u8         ether_stats_octets_low[0x20];
2835 
2836 	u8         ether_stats_pkts_high[0x20];
2837 
2838 	u8         ether_stats_pkts_low[0x20];
2839 
2840 	u8         ether_stats_broadcast_pkts_high[0x20];
2841 
2842 	u8         ether_stats_broadcast_pkts_low[0x20];
2843 
2844 	u8         ether_stats_multicast_pkts_high[0x20];
2845 
2846 	u8         ether_stats_multicast_pkts_low[0x20];
2847 
2848 	u8         ether_stats_crc_align_errors_high[0x20];
2849 
2850 	u8         ether_stats_crc_align_errors_low[0x20];
2851 
2852 	u8         ether_stats_undersize_pkts_high[0x20];
2853 
2854 	u8         ether_stats_undersize_pkts_low[0x20];
2855 
2856 	u8         ether_stats_oversize_pkts_high[0x20];
2857 
2858 	u8         ether_stats_oversize_pkts_low[0x20];
2859 
2860 	u8         ether_stats_fragments_high[0x20];
2861 
2862 	u8         ether_stats_fragments_low[0x20];
2863 
2864 	u8         ether_stats_jabbers_high[0x20];
2865 
2866 	u8         ether_stats_jabbers_low[0x20];
2867 
2868 	u8         ether_stats_collisions_high[0x20];
2869 
2870 	u8         ether_stats_collisions_low[0x20];
2871 
2872 	u8         ether_stats_pkts64octets_high[0x20];
2873 
2874 	u8         ether_stats_pkts64octets_low[0x20];
2875 
2876 	u8         ether_stats_pkts65to127octets_high[0x20];
2877 
2878 	u8         ether_stats_pkts65to127octets_low[0x20];
2879 
2880 	u8         ether_stats_pkts128to255octets_high[0x20];
2881 
2882 	u8         ether_stats_pkts128to255octets_low[0x20];
2883 
2884 	u8         ether_stats_pkts256to511octets_high[0x20];
2885 
2886 	u8         ether_stats_pkts256to511octets_low[0x20];
2887 
2888 	u8         ether_stats_pkts512to1023octets_high[0x20];
2889 
2890 	u8         ether_stats_pkts512to1023octets_low[0x20];
2891 
2892 	u8         ether_stats_pkts1024to1518octets_high[0x20];
2893 
2894 	u8         ether_stats_pkts1024to1518octets_low[0x20];
2895 
2896 	u8         ether_stats_pkts1519to2047octets_high[0x20];
2897 
2898 	u8         ether_stats_pkts1519to2047octets_low[0x20];
2899 
2900 	u8         ether_stats_pkts2048to4095octets_high[0x20];
2901 
2902 	u8         ether_stats_pkts2048to4095octets_low[0x20];
2903 
2904 	u8         ether_stats_pkts4096to8191octets_high[0x20];
2905 
2906 	u8         ether_stats_pkts4096to8191octets_low[0x20];
2907 
2908 	u8         ether_stats_pkts8192to10239octets_high[0x20];
2909 
2910 	u8         ether_stats_pkts8192to10239octets_low[0x20];
2911 
2912 	u8         reserved_at_540[0x280];
2913 };
2914 
2915 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
2916 	u8         if_in_octets_high[0x20];
2917 
2918 	u8         if_in_octets_low[0x20];
2919 
2920 	u8         if_in_ucast_pkts_high[0x20];
2921 
2922 	u8         if_in_ucast_pkts_low[0x20];
2923 
2924 	u8         if_in_discards_high[0x20];
2925 
2926 	u8         if_in_discards_low[0x20];
2927 
2928 	u8         if_in_errors_high[0x20];
2929 
2930 	u8         if_in_errors_low[0x20];
2931 
2932 	u8         if_in_unknown_protos_high[0x20];
2933 
2934 	u8         if_in_unknown_protos_low[0x20];
2935 
2936 	u8         if_out_octets_high[0x20];
2937 
2938 	u8         if_out_octets_low[0x20];
2939 
2940 	u8         if_out_ucast_pkts_high[0x20];
2941 
2942 	u8         if_out_ucast_pkts_low[0x20];
2943 
2944 	u8         if_out_discards_high[0x20];
2945 
2946 	u8         if_out_discards_low[0x20];
2947 
2948 	u8         if_out_errors_high[0x20];
2949 
2950 	u8         if_out_errors_low[0x20];
2951 
2952 	u8         if_in_multicast_pkts_high[0x20];
2953 
2954 	u8         if_in_multicast_pkts_low[0x20];
2955 
2956 	u8         if_in_broadcast_pkts_high[0x20];
2957 
2958 	u8         if_in_broadcast_pkts_low[0x20];
2959 
2960 	u8         if_out_multicast_pkts_high[0x20];
2961 
2962 	u8         if_out_multicast_pkts_low[0x20];
2963 
2964 	u8         if_out_broadcast_pkts_high[0x20];
2965 
2966 	u8         if_out_broadcast_pkts_low[0x20];
2967 
2968 	u8         reserved_at_340[0x480];
2969 };
2970 
2971 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
2972 	u8         a_frames_transmitted_ok_high[0x20];
2973 
2974 	u8         a_frames_transmitted_ok_low[0x20];
2975 
2976 	u8         a_frames_received_ok_high[0x20];
2977 
2978 	u8         a_frames_received_ok_low[0x20];
2979 
2980 	u8         a_frame_check_sequence_errors_high[0x20];
2981 
2982 	u8         a_frame_check_sequence_errors_low[0x20];
2983 
2984 	u8         a_alignment_errors_high[0x20];
2985 
2986 	u8         a_alignment_errors_low[0x20];
2987 
2988 	u8         a_octets_transmitted_ok_high[0x20];
2989 
2990 	u8         a_octets_transmitted_ok_low[0x20];
2991 
2992 	u8         a_octets_received_ok_high[0x20];
2993 
2994 	u8         a_octets_received_ok_low[0x20];
2995 
2996 	u8         a_multicast_frames_xmitted_ok_high[0x20];
2997 
2998 	u8         a_multicast_frames_xmitted_ok_low[0x20];
2999 
3000 	u8         a_broadcast_frames_xmitted_ok_high[0x20];
3001 
3002 	u8         a_broadcast_frames_xmitted_ok_low[0x20];
3003 
3004 	u8         a_multicast_frames_received_ok_high[0x20];
3005 
3006 	u8         a_multicast_frames_received_ok_low[0x20];
3007 
3008 	u8         a_broadcast_frames_received_ok_high[0x20];
3009 
3010 	u8         a_broadcast_frames_received_ok_low[0x20];
3011 
3012 	u8         a_in_range_length_errors_high[0x20];
3013 
3014 	u8         a_in_range_length_errors_low[0x20];
3015 
3016 	u8         a_out_of_range_length_field_high[0x20];
3017 
3018 	u8         a_out_of_range_length_field_low[0x20];
3019 
3020 	u8         a_frame_too_long_errors_high[0x20];
3021 
3022 	u8         a_frame_too_long_errors_low[0x20];
3023 
3024 	u8         a_symbol_error_during_carrier_high[0x20];
3025 
3026 	u8         a_symbol_error_during_carrier_low[0x20];
3027 
3028 	u8         a_mac_control_frames_transmitted_high[0x20];
3029 
3030 	u8         a_mac_control_frames_transmitted_low[0x20];
3031 
3032 	u8         a_mac_control_frames_received_high[0x20];
3033 
3034 	u8         a_mac_control_frames_received_low[0x20];
3035 
3036 	u8         a_unsupported_opcodes_received_high[0x20];
3037 
3038 	u8         a_unsupported_opcodes_received_low[0x20];
3039 
3040 	u8         a_pause_mac_ctrl_frames_received_high[0x20];
3041 
3042 	u8         a_pause_mac_ctrl_frames_received_low[0x20];
3043 
3044 	u8         a_pause_mac_ctrl_frames_transmitted_high[0x20];
3045 
3046 	u8         a_pause_mac_ctrl_frames_transmitted_low[0x20];
3047 
3048 	u8         reserved_at_4c0[0x300];
3049 };
3050 
3051 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits {
3052 	u8         life_time_counter_high[0x20];
3053 
3054 	u8         life_time_counter_low[0x20];
3055 
3056 	u8         rx_errors[0x20];
3057 
3058 	u8         tx_errors[0x20];
3059 
3060 	u8         l0_to_recovery_eieos[0x20];
3061 
3062 	u8         l0_to_recovery_ts[0x20];
3063 
3064 	u8         l0_to_recovery_framing[0x20];
3065 
3066 	u8         l0_to_recovery_retrain[0x20];
3067 
3068 	u8         crc_error_dllp[0x20];
3069 
3070 	u8         crc_error_tlp[0x20];
3071 
3072 	u8         tx_overflow_buffer_pkt_high[0x20];
3073 
3074 	u8         tx_overflow_buffer_pkt_low[0x20];
3075 
3076 	u8         outbound_stalled_reads[0x20];
3077 
3078 	u8         outbound_stalled_writes[0x20];
3079 
3080 	u8         outbound_stalled_reads_events[0x20];
3081 
3082 	u8         outbound_stalled_writes_events[0x20];
3083 
3084 	u8         reserved_at_200[0x5c0];
3085 };
3086 
3087 struct mlx5_ifc_cmd_inter_comp_event_bits {
3088 	u8         command_completion_vector[0x20];
3089 
3090 	u8         reserved_at_20[0xc0];
3091 };
3092 
3093 struct mlx5_ifc_stall_vl_event_bits {
3094 	u8         reserved_at_0[0x18];
3095 	u8         port_num[0x1];
3096 	u8         reserved_at_19[0x3];
3097 	u8         vl[0x4];
3098 
3099 	u8         reserved_at_20[0xa0];
3100 };
3101 
3102 struct mlx5_ifc_db_bf_congestion_event_bits {
3103 	u8         event_subtype[0x8];
3104 	u8         reserved_at_8[0x8];
3105 	u8         congestion_level[0x8];
3106 	u8         reserved_at_18[0x8];
3107 
3108 	u8         reserved_at_20[0xa0];
3109 };
3110 
3111 struct mlx5_ifc_gpio_event_bits {
3112 	u8         reserved_at_0[0x60];
3113 
3114 	u8         gpio_event_hi[0x20];
3115 
3116 	u8         gpio_event_lo[0x20];
3117 
3118 	u8         reserved_at_a0[0x40];
3119 };
3120 
3121 struct mlx5_ifc_port_state_change_event_bits {
3122 	u8         reserved_at_0[0x40];
3123 
3124 	u8         port_num[0x4];
3125 	u8         reserved_at_44[0x1c];
3126 
3127 	u8         reserved_at_60[0x80];
3128 };
3129 
3130 struct mlx5_ifc_dropped_packet_logged_bits {
3131 	u8         reserved_at_0[0xe0];
3132 };
3133 
3134 struct mlx5_ifc_default_timeout_bits {
3135 	u8         to_multiplier[0x3];
3136 	u8         reserved_at_3[0x9];
3137 	u8         to_value[0x14];
3138 };
3139 
3140 struct mlx5_ifc_dtor_reg_bits {
3141 	u8         reserved_at_0[0x20];
3142 
3143 	struct mlx5_ifc_default_timeout_bits pcie_toggle_to;
3144 
3145 	u8         reserved_at_40[0x60];
3146 
3147 	struct mlx5_ifc_default_timeout_bits health_poll_to;
3148 
3149 	struct mlx5_ifc_default_timeout_bits full_crdump_to;
3150 
3151 	struct mlx5_ifc_default_timeout_bits fw_reset_to;
3152 
3153 	struct mlx5_ifc_default_timeout_bits flush_on_err_to;
3154 
3155 	struct mlx5_ifc_default_timeout_bits pci_sync_update_to;
3156 
3157 	struct mlx5_ifc_default_timeout_bits tear_down_to;
3158 
3159 	struct mlx5_ifc_default_timeout_bits fsm_reactivate_to;
3160 
3161 	struct mlx5_ifc_default_timeout_bits reclaim_pages_to;
3162 
3163 	struct mlx5_ifc_default_timeout_bits reclaim_vfs_pages_to;
3164 
3165 	struct mlx5_ifc_default_timeout_bits reset_unload_to;
3166 
3167 	u8         reserved_at_1c0[0x20];
3168 };
3169 
3170 enum {
3171 	MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN                 = 0x1,
3172 	MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR  = 0x2,
3173 };
3174 
3175 struct mlx5_ifc_cq_error_bits {
3176 	u8         reserved_at_0[0x8];
3177 	u8         cqn[0x18];
3178 
3179 	u8         reserved_at_20[0x20];
3180 
3181 	u8         reserved_at_40[0x18];
3182 	u8         syndrome[0x8];
3183 
3184 	u8         reserved_at_60[0x80];
3185 };
3186 
3187 struct mlx5_ifc_rdma_page_fault_event_bits {
3188 	u8         bytes_committed[0x20];
3189 
3190 	u8         r_key[0x20];
3191 
3192 	u8         reserved_at_40[0x10];
3193 	u8         packet_len[0x10];
3194 
3195 	u8         rdma_op_len[0x20];
3196 
3197 	u8         rdma_va[0x40];
3198 
3199 	u8         reserved_at_c0[0x5];
3200 	u8         rdma[0x1];
3201 	u8         write[0x1];
3202 	u8         requestor[0x1];
3203 	u8         qp_number[0x18];
3204 };
3205 
3206 struct mlx5_ifc_wqe_associated_page_fault_event_bits {
3207 	u8         bytes_committed[0x20];
3208 
3209 	u8         reserved_at_20[0x10];
3210 	u8         wqe_index[0x10];
3211 
3212 	u8         reserved_at_40[0x10];
3213 	u8         len[0x10];
3214 
3215 	u8         reserved_at_60[0x60];
3216 
3217 	u8         reserved_at_c0[0x5];
3218 	u8         rdma[0x1];
3219 	u8         write_read[0x1];
3220 	u8         requestor[0x1];
3221 	u8         qpn[0x18];
3222 };
3223 
3224 struct mlx5_ifc_qp_events_bits {
3225 	u8         reserved_at_0[0xa0];
3226 
3227 	u8         type[0x8];
3228 	u8         reserved_at_a8[0x18];
3229 
3230 	u8         reserved_at_c0[0x8];
3231 	u8         qpn_rqn_sqn[0x18];
3232 };
3233 
3234 struct mlx5_ifc_dct_events_bits {
3235 	u8         reserved_at_0[0xc0];
3236 
3237 	u8         reserved_at_c0[0x8];
3238 	u8         dct_number[0x18];
3239 };
3240 
3241 struct mlx5_ifc_comp_event_bits {
3242 	u8         reserved_at_0[0xc0];
3243 
3244 	u8         reserved_at_c0[0x8];
3245 	u8         cq_number[0x18];
3246 };
3247 
3248 enum {
3249 	MLX5_QPC_STATE_RST        = 0x0,
3250 	MLX5_QPC_STATE_INIT       = 0x1,
3251 	MLX5_QPC_STATE_RTR        = 0x2,
3252 	MLX5_QPC_STATE_RTS        = 0x3,
3253 	MLX5_QPC_STATE_SQER       = 0x4,
3254 	MLX5_QPC_STATE_ERR        = 0x6,
3255 	MLX5_QPC_STATE_SQD        = 0x7,
3256 	MLX5_QPC_STATE_SUSPENDED  = 0x9,
3257 };
3258 
3259 enum {
3260 	MLX5_QPC_ST_RC            = 0x0,
3261 	MLX5_QPC_ST_UC            = 0x1,
3262 	MLX5_QPC_ST_UD            = 0x2,
3263 	MLX5_QPC_ST_XRC           = 0x3,
3264 	MLX5_QPC_ST_DCI           = 0x5,
3265 	MLX5_QPC_ST_QP0           = 0x7,
3266 	MLX5_QPC_ST_QP1           = 0x8,
3267 	MLX5_QPC_ST_RAW_DATAGRAM  = 0x9,
3268 	MLX5_QPC_ST_REG_UMR       = 0xc,
3269 };
3270 
3271 enum {
3272 	MLX5_QPC_PM_STATE_ARMED     = 0x0,
3273 	MLX5_QPC_PM_STATE_REARM     = 0x1,
3274 	MLX5_QPC_PM_STATE_RESERVED  = 0x2,
3275 	MLX5_QPC_PM_STATE_MIGRATED  = 0x3,
3276 };
3277 
3278 enum {
3279 	MLX5_QPC_OFFLOAD_TYPE_RNDV  = 0x1,
3280 };
3281 
3282 enum {
3283 	MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS                = 0x0,
3284 	MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT  = 0x1,
3285 };
3286 
3287 enum {
3288 	MLX5_QPC_MTU_256_BYTES        = 0x1,
3289 	MLX5_QPC_MTU_512_BYTES        = 0x2,
3290 	MLX5_QPC_MTU_1K_BYTES         = 0x3,
3291 	MLX5_QPC_MTU_2K_BYTES         = 0x4,
3292 	MLX5_QPC_MTU_4K_BYTES         = 0x5,
3293 	MLX5_QPC_MTU_RAW_ETHERNET_QP  = 0x7,
3294 };
3295 
3296 enum {
3297 	MLX5_QPC_ATOMIC_MODE_IB_SPEC     = 0x1,
3298 	MLX5_QPC_ATOMIC_MODE_ONLY_8B     = 0x2,
3299 	MLX5_QPC_ATOMIC_MODE_UP_TO_8B    = 0x3,
3300 	MLX5_QPC_ATOMIC_MODE_UP_TO_16B   = 0x4,
3301 	MLX5_QPC_ATOMIC_MODE_UP_TO_32B   = 0x5,
3302 	MLX5_QPC_ATOMIC_MODE_UP_TO_64B   = 0x6,
3303 	MLX5_QPC_ATOMIC_MODE_UP_TO_128B  = 0x7,
3304 	MLX5_QPC_ATOMIC_MODE_UP_TO_256B  = 0x8,
3305 };
3306 
3307 enum {
3308 	MLX5_QPC_CS_REQ_DISABLE    = 0x0,
3309 	MLX5_QPC_CS_REQ_UP_TO_32B  = 0x11,
3310 	MLX5_QPC_CS_REQ_UP_TO_64B  = 0x22,
3311 };
3312 
3313 enum {
3314 	MLX5_QPC_CS_RES_DISABLE    = 0x0,
3315 	MLX5_QPC_CS_RES_UP_TO_32B  = 0x1,
3316 	MLX5_QPC_CS_RES_UP_TO_64B  = 0x2,
3317 };
3318 
3319 enum {
3320 	MLX5_TIMESTAMP_FORMAT_FREE_RUNNING = 0x0,
3321 	MLX5_TIMESTAMP_FORMAT_DEFAULT      = 0x1,
3322 	MLX5_TIMESTAMP_FORMAT_REAL_TIME    = 0x2,
3323 };
3324 
3325 struct mlx5_ifc_qpc_bits {
3326 	u8         state[0x4];
3327 	u8         lag_tx_port_affinity[0x4];
3328 	u8         st[0x8];
3329 	u8         reserved_at_10[0x2];
3330 	u8	   isolate_vl_tc[0x1];
3331 	u8         pm_state[0x2];
3332 	u8         reserved_at_15[0x1];
3333 	u8         req_e2e_credit_mode[0x2];
3334 	u8         offload_type[0x4];
3335 	u8         end_padding_mode[0x2];
3336 	u8         reserved_at_1e[0x2];
3337 
3338 	u8         wq_signature[0x1];
3339 	u8         block_lb_mc[0x1];
3340 	u8         atomic_like_write_en[0x1];
3341 	u8         latency_sensitive[0x1];
3342 	u8         reserved_at_24[0x1];
3343 	u8         drain_sigerr[0x1];
3344 	u8         reserved_at_26[0x2];
3345 	u8         pd[0x18];
3346 
3347 	u8         mtu[0x3];
3348 	u8         log_msg_max[0x5];
3349 	u8         reserved_at_48[0x1];
3350 	u8         log_rq_size[0x4];
3351 	u8         log_rq_stride[0x3];
3352 	u8         no_sq[0x1];
3353 	u8         log_sq_size[0x4];
3354 	u8         reserved_at_55[0x1];
3355 	u8	   retry_mode[0x2];
3356 	u8	   ts_format[0x2];
3357 	u8         reserved_at_5a[0x1];
3358 	u8         rlky[0x1];
3359 	u8         ulp_stateless_offload_mode[0x4];
3360 
3361 	u8         counter_set_id[0x8];
3362 	u8         uar_page[0x18];
3363 
3364 	u8         reserved_at_80[0x8];
3365 	u8         user_index[0x18];
3366 
3367 	u8         reserved_at_a0[0x3];
3368 	u8         log_page_size[0x5];
3369 	u8         remote_qpn[0x18];
3370 
3371 	struct mlx5_ifc_ads_bits primary_address_path;
3372 
3373 	struct mlx5_ifc_ads_bits secondary_address_path;
3374 
3375 	u8         log_ack_req_freq[0x4];
3376 	u8         reserved_at_384[0x4];
3377 	u8         log_sra_max[0x3];
3378 	u8         reserved_at_38b[0x2];
3379 	u8         retry_count[0x3];
3380 	u8         rnr_retry[0x3];
3381 	u8         reserved_at_393[0x1];
3382 	u8         fre[0x1];
3383 	u8         cur_rnr_retry[0x3];
3384 	u8         cur_retry_count[0x3];
3385 	u8         reserved_at_39b[0x5];
3386 
3387 	u8         reserved_at_3a0[0x20];
3388 
3389 	u8         reserved_at_3c0[0x8];
3390 	u8         next_send_psn[0x18];
3391 
3392 	u8         reserved_at_3e0[0x3];
3393 	u8	   log_num_dci_stream_channels[0x5];
3394 	u8         cqn_snd[0x18];
3395 
3396 	u8         reserved_at_400[0x3];
3397 	u8	   log_num_dci_errored_streams[0x5];
3398 	u8         deth_sqpn[0x18];
3399 
3400 	u8         reserved_at_420[0x20];
3401 
3402 	u8         reserved_at_440[0x8];
3403 	u8         last_acked_psn[0x18];
3404 
3405 	u8         reserved_at_460[0x8];
3406 	u8         ssn[0x18];
3407 
3408 	u8         reserved_at_480[0x8];
3409 	u8         log_rra_max[0x3];
3410 	u8         reserved_at_48b[0x1];
3411 	u8         atomic_mode[0x4];
3412 	u8         rre[0x1];
3413 	u8         rwe[0x1];
3414 	u8         rae[0x1];
3415 	u8         reserved_at_493[0x1];
3416 	u8         page_offset[0x6];
3417 	u8         reserved_at_49a[0x3];
3418 	u8         cd_slave_receive[0x1];
3419 	u8         cd_slave_send[0x1];
3420 	u8         cd_master[0x1];
3421 
3422 	u8         reserved_at_4a0[0x3];
3423 	u8         min_rnr_nak[0x5];
3424 	u8         next_rcv_psn[0x18];
3425 
3426 	u8         reserved_at_4c0[0x8];
3427 	u8         xrcd[0x18];
3428 
3429 	u8         reserved_at_4e0[0x8];
3430 	u8         cqn_rcv[0x18];
3431 
3432 	u8         dbr_addr[0x40];
3433 
3434 	u8         q_key[0x20];
3435 
3436 	u8         reserved_at_560[0x5];
3437 	u8         rq_type[0x3];
3438 	u8         srqn_rmpn_xrqn[0x18];
3439 
3440 	u8         reserved_at_580[0x8];
3441 	u8         rmsn[0x18];
3442 
3443 	u8         hw_sq_wqebb_counter[0x10];
3444 	u8         sw_sq_wqebb_counter[0x10];
3445 
3446 	u8         hw_rq_counter[0x20];
3447 
3448 	u8         sw_rq_counter[0x20];
3449 
3450 	u8         reserved_at_600[0x20];
3451 
3452 	u8         reserved_at_620[0xf];
3453 	u8         cgs[0x1];
3454 	u8         cs_req[0x8];
3455 	u8         cs_res[0x8];
3456 
3457 	u8         dc_access_key[0x40];
3458 
3459 	u8         reserved_at_680[0x3];
3460 	u8         dbr_umem_valid[0x1];
3461 
3462 	u8         reserved_at_684[0xbc];
3463 };
3464 
3465 struct mlx5_ifc_roce_addr_layout_bits {
3466 	u8         source_l3_address[16][0x8];
3467 
3468 	u8         reserved_at_80[0x3];
3469 	u8         vlan_valid[0x1];
3470 	u8         vlan_id[0xc];
3471 	u8         source_mac_47_32[0x10];
3472 
3473 	u8         source_mac_31_0[0x20];
3474 
3475 	u8         reserved_at_c0[0x14];
3476 	u8         roce_l3_type[0x4];
3477 	u8         roce_version[0x8];
3478 
3479 	u8         reserved_at_e0[0x20];
3480 };
3481 
3482 struct mlx5_ifc_crypto_cap_bits {
3483 	u8    reserved_at_0[0x3];
3484 	u8    synchronize_dek[0x1];
3485 	u8    int_kek_manual[0x1];
3486 	u8    int_kek_auto[0x1];
3487 	u8    reserved_at_6[0x1a];
3488 
3489 	u8    reserved_at_20[0x3];
3490 	u8    log_dek_max_alloc[0x5];
3491 	u8    reserved_at_28[0x3];
3492 	u8    log_max_num_deks[0x5];
3493 	u8    reserved_at_30[0x10];
3494 
3495 	u8    reserved_at_40[0x20];
3496 
3497 	u8    reserved_at_60[0x3];
3498 	u8    log_dek_granularity[0x5];
3499 	u8    reserved_at_68[0x3];
3500 	u8    log_max_num_int_kek[0x5];
3501 	u8    sw_wrapped_dek[0x10];
3502 
3503 	u8    reserved_at_80[0x780];
3504 };
3505 
3506 union mlx5_ifc_hca_cap_union_bits {
3507 	struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
3508 	struct mlx5_ifc_cmd_hca_cap_2_bits cmd_hca_cap_2;
3509 	struct mlx5_ifc_odp_cap_bits odp_cap;
3510 	struct mlx5_ifc_atomic_caps_bits atomic_caps;
3511 	struct mlx5_ifc_roce_cap_bits roce_cap;
3512 	struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
3513 	struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
3514 	struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap;
3515 	struct mlx5_ifc_e_switch_cap_bits e_switch_cap;
3516 	struct mlx5_ifc_port_selection_cap_bits port_selection_cap;
3517 	struct mlx5_ifc_qos_cap_bits qos_cap;
3518 	struct mlx5_ifc_debug_cap_bits debug_cap;
3519 	struct mlx5_ifc_fpga_cap_bits fpga_cap;
3520 	struct mlx5_ifc_tls_cap_bits tls_cap;
3521 	struct mlx5_ifc_device_mem_cap_bits device_mem_cap;
3522 	struct mlx5_ifc_virtio_emulation_cap_bits virtio_emulation_cap;
3523 	struct mlx5_ifc_macsec_cap_bits macsec_cap;
3524 	struct mlx5_ifc_crypto_cap_bits crypto_cap;
3525 	struct mlx5_ifc_ipsec_cap_bits ipsec_cap;
3526 	u8         reserved_at_0[0x8000];
3527 };
3528 
3529 enum {
3530 	MLX5_FLOW_CONTEXT_ACTION_ALLOW     = 0x1,
3531 	MLX5_FLOW_CONTEXT_ACTION_DROP      = 0x2,
3532 	MLX5_FLOW_CONTEXT_ACTION_FWD_DEST  = 0x4,
3533 	MLX5_FLOW_CONTEXT_ACTION_COUNT     = 0x8,
3534 	MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT = 0x10,
3535 	MLX5_FLOW_CONTEXT_ACTION_DECAP     = 0x20,
3536 	MLX5_FLOW_CONTEXT_ACTION_MOD_HDR   = 0x40,
3537 	MLX5_FLOW_CONTEXT_ACTION_VLAN_POP  = 0x80,
3538 	MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100,
3539 	MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2  = 0x400,
3540 	MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2 = 0x800,
3541 	MLX5_FLOW_CONTEXT_ACTION_CRYPTO_DECRYPT = 0x1000,
3542 	MLX5_FLOW_CONTEXT_ACTION_CRYPTO_ENCRYPT = 0x2000,
3543 	MLX5_FLOW_CONTEXT_ACTION_EXECUTE_ASO = 0x4000,
3544 };
3545 
3546 enum {
3547 	MLX5_FLOW_CONTEXT_FLOW_SOURCE_ANY_VPORT         = 0x0,
3548 	MLX5_FLOW_CONTEXT_FLOW_SOURCE_UPLINK            = 0x1,
3549 	MLX5_FLOW_CONTEXT_FLOW_SOURCE_LOCAL_VPORT       = 0x2,
3550 };
3551 
3552 enum {
3553 	MLX5_FLOW_CONTEXT_ENCRYPT_DECRYPT_TYPE_IPSEC   = 0x0,
3554 	MLX5_FLOW_CONTEXT_ENCRYPT_DECRYPT_TYPE_MACSEC  = 0x1,
3555 };
3556 
3557 struct mlx5_ifc_vlan_bits {
3558 	u8         ethtype[0x10];
3559 	u8         prio[0x3];
3560 	u8         cfi[0x1];
3561 	u8         vid[0xc];
3562 };
3563 
3564 enum {
3565 	MLX5_FLOW_METER_COLOR_RED	= 0x0,
3566 	MLX5_FLOW_METER_COLOR_YELLOW	= 0x1,
3567 	MLX5_FLOW_METER_COLOR_GREEN	= 0x2,
3568 	MLX5_FLOW_METER_COLOR_UNDEFINED	= 0x3,
3569 };
3570 
3571 enum {
3572 	MLX5_EXE_ASO_FLOW_METER		= 0x2,
3573 };
3574 
3575 struct mlx5_ifc_exe_aso_ctrl_flow_meter_bits {
3576 	u8        return_reg_id[0x4];
3577 	u8        aso_type[0x4];
3578 	u8        reserved_at_8[0x14];
3579 	u8        action[0x1];
3580 	u8        init_color[0x2];
3581 	u8        meter_id[0x1];
3582 };
3583 
3584 union mlx5_ifc_exe_aso_ctrl {
3585 	struct mlx5_ifc_exe_aso_ctrl_flow_meter_bits exe_aso_ctrl_flow_meter;
3586 };
3587 
3588 struct mlx5_ifc_execute_aso_bits {
3589 	u8        valid[0x1];
3590 	u8        reserved_at_1[0x7];
3591 	u8        aso_object_id[0x18];
3592 
3593 	union mlx5_ifc_exe_aso_ctrl exe_aso_ctrl;
3594 };
3595 
3596 struct mlx5_ifc_flow_context_bits {
3597 	struct mlx5_ifc_vlan_bits push_vlan;
3598 
3599 	u8         group_id[0x20];
3600 
3601 	u8         reserved_at_40[0x8];
3602 	u8         flow_tag[0x18];
3603 
3604 	u8         reserved_at_60[0x10];
3605 	u8         action[0x10];
3606 
3607 	u8         extended_destination[0x1];
3608 	u8         uplink_hairpin_en[0x1];
3609 	u8         flow_source[0x2];
3610 	u8         encrypt_decrypt_type[0x4];
3611 	u8         destination_list_size[0x18];
3612 
3613 	u8         reserved_at_a0[0x8];
3614 	u8         flow_counter_list_size[0x18];
3615 
3616 	u8         packet_reformat_id[0x20];
3617 
3618 	u8         modify_header_id[0x20];
3619 
3620 	struct mlx5_ifc_vlan_bits push_vlan_2;
3621 
3622 	u8         encrypt_decrypt_obj_id[0x20];
3623 	u8         reserved_at_140[0xc0];
3624 
3625 	struct mlx5_ifc_fte_match_param_bits match_value;
3626 
3627 	struct mlx5_ifc_execute_aso_bits execute_aso[4];
3628 
3629 	u8         reserved_at_1300[0x500];
3630 
3631 	union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[];
3632 };
3633 
3634 enum {
3635 	MLX5_XRC_SRQC_STATE_GOOD   = 0x0,
3636 	MLX5_XRC_SRQC_STATE_ERROR  = 0x1,
3637 };
3638 
3639 struct mlx5_ifc_xrc_srqc_bits {
3640 	u8         state[0x4];
3641 	u8         log_xrc_srq_size[0x4];
3642 	u8         reserved_at_8[0x18];
3643 
3644 	u8         wq_signature[0x1];
3645 	u8         cont_srq[0x1];
3646 	u8         reserved_at_22[0x1];
3647 	u8         rlky[0x1];
3648 	u8         basic_cyclic_rcv_wqe[0x1];
3649 	u8         log_rq_stride[0x3];
3650 	u8         xrcd[0x18];
3651 
3652 	u8         page_offset[0x6];
3653 	u8         reserved_at_46[0x1];
3654 	u8         dbr_umem_valid[0x1];
3655 	u8         cqn[0x18];
3656 
3657 	u8         reserved_at_60[0x20];
3658 
3659 	u8         user_index_equal_xrc_srqn[0x1];
3660 	u8         reserved_at_81[0x1];
3661 	u8         log_page_size[0x6];
3662 	u8         user_index[0x18];
3663 
3664 	u8         reserved_at_a0[0x20];
3665 
3666 	u8         reserved_at_c0[0x8];
3667 	u8         pd[0x18];
3668 
3669 	u8         lwm[0x10];
3670 	u8         wqe_cnt[0x10];
3671 
3672 	u8         reserved_at_100[0x40];
3673 
3674 	u8         db_record_addr_h[0x20];
3675 
3676 	u8         db_record_addr_l[0x1e];
3677 	u8         reserved_at_17e[0x2];
3678 
3679 	u8         reserved_at_180[0x80];
3680 };
3681 
3682 struct mlx5_ifc_vnic_diagnostic_statistics_bits {
3683 	u8         counter_error_queues[0x20];
3684 
3685 	u8         total_error_queues[0x20];
3686 
3687 	u8         send_queue_priority_update_flow[0x20];
3688 
3689 	u8         reserved_at_60[0x20];
3690 
3691 	u8         nic_receive_steering_discard[0x40];
3692 
3693 	u8         receive_discard_vport_down[0x40];
3694 
3695 	u8         transmit_discard_vport_down[0x40];
3696 
3697 	u8         async_eq_overrun[0x20];
3698 
3699 	u8         comp_eq_overrun[0x20];
3700 
3701 	u8         reserved_at_180[0x20];
3702 
3703 	u8         invalid_command[0x20];
3704 
3705 	u8         quota_exceeded_command[0x20];
3706 
3707 	u8         internal_rq_out_of_buffer[0x20];
3708 
3709 	u8         cq_overrun[0x20];
3710 
3711 	u8         eth_wqe_too_small[0x20];
3712 
3713 	u8         reserved_at_220[0xc0];
3714 
3715 	u8         generated_pkt_steering_fail[0x40];
3716 
3717 	u8         handled_pkt_steering_fail[0x40];
3718 
3719 	u8         reserved_at_360[0xc80];
3720 };
3721 
3722 struct mlx5_ifc_traffic_counter_bits {
3723 	u8         packets[0x40];
3724 
3725 	u8         octets[0x40];
3726 };
3727 
3728 struct mlx5_ifc_tisc_bits {
3729 	u8         strict_lag_tx_port_affinity[0x1];
3730 	u8         tls_en[0x1];
3731 	u8         reserved_at_2[0x2];
3732 	u8         lag_tx_port_affinity[0x04];
3733 
3734 	u8         reserved_at_8[0x4];
3735 	u8         prio[0x4];
3736 	u8         reserved_at_10[0x10];
3737 
3738 	u8         reserved_at_20[0x100];
3739 
3740 	u8         reserved_at_120[0x8];
3741 	u8         transport_domain[0x18];
3742 
3743 	u8         reserved_at_140[0x8];
3744 	u8         underlay_qpn[0x18];
3745 
3746 	u8         reserved_at_160[0x8];
3747 	u8         pd[0x18];
3748 
3749 	u8         reserved_at_180[0x380];
3750 };
3751 
3752 enum {
3753 	MLX5_TIRC_DISP_TYPE_DIRECT    = 0x0,
3754 	MLX5_TIRC_DISP_TYPE_INDIRECT  = 0x1,
3755 };
3756 
3757 enum {
3758 	MLX5_TIRC_PACKET_MERGE_MASK_IPV4_LRO  = BIT(0),
3759 	MLX5_TIRC_PACKET_MERGE_MASK_IPV6_LRO  = BIT(1),
3760 };
3761 
3762 enum {
3763 	MLX5_RX_HASH_FN_NONE           = 0x0,
3764 	MLX5_RX_HASH_FN_INVERTED_XOR8  = 0x1,
3765 	MLX5_RX_HASH_FN_TOEPLITZ       = 0x2,
3766 };
3767 
3768 enum {
3769 	MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST    = 0x1,
3770 	MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST  = 0x2,
3771 };
3772 
3773 struct mlx5_ifc_tirc_bits {
3774 	u8         reserved_at_0[0x20];
3775 
3776 	u8         disp_type[0x4];
3777 	u8         tls_en[0x1];
3778 	u8         reserved_at_25[0x1b];
3779 
3780 	u8         reserved_at_40[0x40];
3781 
3782 	u8         reserved_at_80[0x4];
3783 	u8         lro_timeout_period_usecs[0x10];
3784 	u8         packet_merge_mask[0x4];
3785 	u8         lro_max_ip_payload_size[0x8];
3786 
3787 	u8         reserved_at_a0[0x40];
3788 
3789 	u8         reserved_at_e0[0x8];
3790 	u8         inline_rqn[0x18];
3791 
3792 	u8         rx_hash_symmetric[0x1];
3793 	u8         reserved_at_101[0x1];
3794 	u8         tunneled_offload_en[0x1];
3795 	u8         reserved_at_103[0x5];
3796 	u8         indirect_table[0x18];
3797 
3798 	u8         rx_hash_fn[0x4];
3799 	u8         reserved_at_124[0x2];
3800 	u8         self_lb_block[0x2];
3801 	u8         transport_domain[0x18];
3802 
3803 	u8         rx_hash_toeplitz_key[10][0x20];
3804 
3805 	struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
3806 
3807 	struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
3808 
3809 	u8         reserved_at_2c0[0x4c0];
3810 };
3811 
3812 enum {
3813 	MLX5_SRQC_STATE_GOOD   = 0x0,
3814 	MLX5_SRQC_STATE_ERROR  = 0x1,
3815 };
3816 
3817 struct mlx5_ifc_srqc_bits {
3818 	u8         state[0x4];
3819 	u8         log_srq_size[0x4];
3820 	u8         reserved_at_8[0x18];
3821 
3822 	u8         wq_signature[0x1];
3823 	u8         cont_srq[0x1];
3824 	u8         reserved_at_22[0x1];
3825 	u8         rlky[0x1];
3826 	u8         reserved_at_24[0x1];
3827 	u8         log_rq_stride[0x3];
3828 	u8         xrcd[0x18];
3829 
3830 	u8         page_offset[0x6];
3831 	u8         reserved_at_46[0x2];
3832 	u8         cqn[0x18];
3833 
3834 	u8         reserved_at_60[0x20];
3835 
3836 	u8         reserved_at_80[0x2];
3837 	u8         log_page_size[0x6];
3838 	u8         reserved_at_88[0x18];
3839 
3840 	u8         reserved_at_a0[0x20];
3841 
3842 	u8         reserved_at_c0[0x8];
3843 	u8         pd[0x18];
3844 
3845 	u8         lwm[0x10];
3846 	u8         wqe_cnt[0x10];
3847 
3848 	u8         reserved_at_100[0x40];
3849 
3850 	u8         dbr_addr[0x40];
3851 
3852 	u8         reserved_at_180[0x80];
3853 };
3854 
3855 enum {
3856 	MLX5_SQC_STATE_RST  = 0x0,
3857 	MLX5_SQC_STATE_RDY  = 0x1,
3858 	MLX5_SQC_STATE_ERR  = 0x3,
3859 };
3860 
3861 struct mlx5_ifc_sqc_bits {
3862 	u8         rlky[0x1];
3863 	u8         cd_master[0x1];
3864 	u8         fre[0x1];
3865 	u8         flush_in_error_en[0x1];
3866 	u8         allow_multi_pkt_send_wqe[0x1];
3867 	u8	   min_wqe_inline_mode[0x3];
3868 	u8         state[0x4];
3869 	u8         reg_umr[0x1];
3870 	u8         allow_swp[0x1];
3871 	u8         hairpin[0x1];
3872 	u8         reserved_at_f[0xb];
3873 	u8	   ts_format[0x2];
3874 	u8	   reserved_at_1c[0x4];
3875 
3876 	u8         reserved_at_20[0x8];
3877 	u8         user_index[0x18];
3878 
3879 	u8         reserved_at_40[0x8];
3880 	u8         cqn[0x18];
3881 
3882 	u8         reserved_at_60[0x8];
3883 	u8         hairpin_peer_rq[0x18];
3884 
3885 	u8         reserved_at_80[0x10];
3886 	u8         hairpin_peer_vhca[0x10];
3887 
3888 	u8         reserved_at_a0[0x20];
3889 
3890 	u8         reserved_at_c0[0x8];
3891 	u8         ts_cqe_to_dest_cqn[0x18];
3892 
3893 	u8         reserved_at_e0[0x10];
3894 	u8         packet_pacing_rate_limit_index[0x10];
3895 	u8         tis_lst_sz[0x10];
3896 	u8         qos_queue_group_id[0x10];
3897 
3898 	u8         reserved_at_120[0x40];
3899 
3900 	u8         reserved_at_160[0x8];
3901 	u8         tis_num_0[0x18];
3902 
3903 	struct mlx5_ifc_wq_bits wq;
3904 };
3905 
3906 enum {
3907 	SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0,
3908 	SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1,
3909 	SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2,
3910 	SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3,
3911 	SCHEDULING_CONTEXT_ELEMENT_TYPE_QUEUE_GROUP = 0x4,
3912 };
3913 
3914 enum {
3915 	ELEMENT_TYPE_CAP_MASK_TASR		= 1 << 0,
3916 	ELEMENT_TYPE_CAP_MASK_VPORT		= 1 << 1,
3917 	ELEMENT_TYPE_CAP_MASK_VPORT_TC		= 1 << 2,
3918 	ELEMENT_TYPE_CAP_MASK_PARA_VPORT_TC	= 1 << 3,
3919 };
3920 
3921 struct mlx5_ifc_scheduling_context_bits {
3922 	u8         element_type[0x8];
3923 	u8         reserved_at_8[0x18];
3924 
3925 	u8         element_attributes[0x20];
3926 
3927 	u8         parent_element_id[0x20];
3928 
3929 	u8         reserved_at_60[0x40];
3930 
3931 	u8         bw_share[0x20];
3932 
3933 	u8         max_average_bw[0x20];
3934 
3935 	u8         reserved_at_e0[0x120];
3936 };
3937 
3938 struct mlx5_ifc_rqtc_bits {
3939 	u8    reserved_at_0[0xa0];
3940 
3941 	u8    reserved_at_a0[0x5];
3942 	u8    list_q_type[0x3];
3943 	u8    reserved_at_a8[0x8];
3944 	u8    rqt_max_size[0x10];
3945 
3946 	u8    rq_vhca_id_format[0x1];
3947 	u8    reserved_at_c1[0xf];
3948 	u8    rqt_actual_size[0x10];
3949 
3950 	u8    reserved_at_e0[0x6a0];
3951 
3952 	union {
3953 		DECLARE_FLEX_ARRAY(struct mlx5_ifc_rq_num_bits, rq_num);
3954 		DECLARE_FLEX_ARRAY(struct mlx5_ifc_rq_vhca_bits, rq_vhca);
3955 	};
3956 };
3957 
3958 enum {
3959 	MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE  = 0x0,
3960 	MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP     = 0x1,
3961 };
3962 
3963 enum {
3964 	MLX5_RQC_STATE_RST  = 0x0,
3965 	MLX5_RQC_STATE_RDY  = 0x1,
3966 	MLX5_RQC_STATE_ERR  = 0x3,
3967 };
3968 
3969 enum {
3970 	MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_BYTE    = 0x0,
3971 	MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_STRIDE  = 0x1,
3972 	MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_PAGE    = 0x2,
3973 };
3974 
3975 enum {
3976 	MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_NO_MATCH    = 0x0,
3977 	MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_EXTENDED    = 0x1,
3978 	MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_FIVE_TUPLE  = 0x2,
3979 };
3980 
3981 struct mlx5_ifc_rqc_bits {
3982 	u8         rlky[0x1];
3983 	u8	   delay_drop_en[0x1];
3984 	u8         scatter_fcs[0x1];
3985 	u8         vsd[0x1];
3986 	u8         mem_rq_type[0x4];
3987 	u8         state[0x4];
3988 	u8         reserved_at_c[0x1];
3989 	u8         flush_in_error_en[0x1];
3990 	u8         hairpin[0x1];
3991 	u8         reserved_at_f[0xb];
3992 	u8	   ts_format[0x2];
3993 	u8	   reserved_at_1c[0x4];
3994 
3995 	u8         reserved_at_20[0x8];
3996 	u8         user_index[0x18];
3997 
3998 	u8         reserved_at_40[0x8];
3999 	u8         cqn[0x18];
4000 
4001 	u8         counter_set_id[0x8];
4002 	u8         reserved_at_68[0x18];
4003 
4004 	u8         reserved_at_80[0x8];
4005 	u8         rmpn[0x18];
4006 
4007 	u8         reserved_at_a0[0x8];
4008 	u8         hairpin_peer_sq[0x18];
4009 
4010 	u8         reserved_at_c0[0x10];
4011 	u8         hairpin_peer_vhca[0x10];
4012 
4013 	u8         reserved_at_e0[0x46];
4014 	u8         shampo_no_match_alignment_granularity[0x2];
4015 	u8         reserved_at_128[0x6];
4016 	u8         shampo_match_criteria_type[0x2];
4017 	u8         reservation_timeout[0x10];
4018 
4019 	u8         reserved_at_140[0x40];
4020 
4021 	struct mlx5_ifc_wq_bits wq;
4022 };
4023 
4024 enum {
4025 	MLX5_RMPC_STATE_RDY  = 0x1,
4026 	MLX5_RMPC_STATE_ERR  = 0x3,
4027 };
4028 
4029 struct mlx5_ifc_rmpc_bits {
4030 	u8         reserved_at_0[0x8];
4031 	u8         state[0x4];
4032 	u8         reserved_at_c[0x14];
4033 
4034 	u8         basic_cyclic_rcv_wqe[0x1];
4035 	u8         reserved_at_21[0x1f];
4036 
4037 	u8         reserved_at_40[0x140];
4038 
4039 	struct mlx5_ifc_wq_bits wq;
4040 };
4041 
4042 enum {
4043 	VHCA_ID_TYPE_HW = 0,
4044 	VHCA_ID_TYPE_SW = 1,
4045 };
4046 
4047 struct mlx5_ifc_nic_vport_context_bits {
4048 	u8         reserved_at_0[0x5];
4049 	u8         min_wqe_inline_mode[0x3];
4050 	u8         reserved_at_8[0x15];
4051 	u8         disable_mc_local_lb[0x1];
4052 	u8         disable_uc_local_lb[0x1];
4053 	u8         roce_en[0x1];
4054 
4055 	u8         arm_change_event[0x1];
4056 	u8         reserved_at_21[0x1a];
4057 	u8         event_on_mtu[0x1];
4058 	u8         event_on_promisc_change[0x1];
4059 	u8         event_on_vlan_change[0x1];
4060 	u8         event_on_mc_address_change[0x1];
4061 	u8         event_on_uc_address_change[0x1];
4062 
4063 	u8         vhca_id_type[0x1];
4064 	u8         reserved_at_41[0xb];
4065 	u8	   affiliation_criteria[0x4];
4066 	u8	   affiliated_vhca_id[0x10];
4067 
4068 	u8	   reserved_at_60[0xa0];
4069 
4070 	u8	   reserved_at_100[0x1];
4071 	u8         sd_group[0x3];
4072 	u8	   reserved_at_104[0x1c];
4073 
4074 	u8	   reserved_at_120[0x10];
4075 	u8         mtu[0x10];
4076 
4077 	u8         system_image_guid[0x40];
4078 	u8         port_guid[0x40];
4079 	u8         node_guid[0x40];
4080 
4081 	u8         reserved_at_200[0x140];
4082 	u8         qkey_violation_counter[0x10];
4083 	u8         reserved_at_350[0x430];
4084 
4085 	u8         promisc_uc[0x1];
4086 	u8         promisc_mc[0x1];
4087 	u8         promisc_all[0x1];
4088 	u8         reserved_at_783[0x2];
4089 	u8         allowed_list_type[0x3];
4090 	u8         reserved_at_788[0xc];
4091 	u8         allowed_list_size[0xc];
4092 
4093 	struct mlx5_ifc_mac_address_layout_bits permanent_address;
4094 
4095 	u8         reserved_at_7e0[0x20];
4096 
4097 	u8         current_uc_mac_address[][0x40];
4098 };
4099 
4100 enum {
4101 	MLX5_MKC_ACCESS_MODE_PA    = 0x0,
4102 	MLX5_MKC_ACCESS_MODE_MTT   = 0x1,
4103 	MLX5_MKC_ACCESS_MODE_KLMS  = 0x2,
4104 	MLX5_MKC_ACCESS_MODE_KSM   = 0x3,
4105 	MLX5_MKC_ACCESS_MODE_SW_ICM = 0x4,
4106 	MLX5_MKC_ACCESS_MODE_MEMIC = 0x5,
4107 };
4108 
4109 struct mlx5_ifc_mkc_bits {
4110 	u8         reserved_at_0[0x1];
4111 	u8         free[0x1];
4112 	u8         reserved_at_2[0x1];
4113 	u8         access_mode_4_2[0x3];
4114 	u8         reserved_at_6[0x7];
4115 	u8         relaxed_ordering_write[0x1];
4116 	u8         reserved_at_e[0x1];
4117 	u8         small_fence_on_rdma_read_response[0x1];
4118 	u8         umr_en[0x1];
4119 	u8         a[0x1];
4120 	u8         rw[0x1];
4121 	u8         rr[0x1];
4122 	u8         lw[0x1];
4123 	u8         lr[0x1];
4124 	u8         access_mode_1_0[0x2];
4125 	u8         reserved_at_18[0x2];
4126 	u8         ma_translation_mode[0x2];
4127 	u8         reserved_at_1c[0x4];
4128 
4129 	u8         qpn[0x18];
4130 	u8         mkey_7_0[0x8];
4131 
4132 	u8         reserved_at_40[0x20];
4133 
4134 	u8         length64[0x1];
4135 	u8         bsf_en[0x1];
4136 	u8         sync_umr[0x1];
4137 	u8         reserved_at_63[0x2];
4138 	u8         expected_sigerr_count[0x1];
4139 	u8         reserved_at_66[0x1];
4140 	u8         en_rinval[0x1];
4141 	u8         pd[0x18];
4142 
4143 	u8         start_addr[0x40];
4144 
4145 	u8         len[0x40];
4146 
4147 	u8         bsf_octword_size[0x20];
4148 
4149 	u8         reserved_at_120[0x80];
4150 
4151 	u8         translations_octword_size[0x20];
4152 
4153 	u8         reserved_at_1c0[0x19];
4154 	u8         relaxed_ordering_read[0x1];
4155 	u8         reserved_at_1d9[0x1];
4156 	u8         log_page_size[0x5];
4157 
4158 	u8         reserved_at_1e0[0x20];
4159 };
4160 
4161 struct mlx5_ifc_pkey_bits {
4162 	u8         reserved_at_0[0x10];
4163 	u8         pkey[0x10];
4164 };
4165 
4166 struct mlx5_ifc_array128_auto_bits {
4167 	u8         array128_auto[16][0x8];
4168 };
4169 
4170 struct mlx5_ifc_hca_vport_context_bits {
4171 	u8         field_select[0x20];
4172 
4173 	u8         reserved_at_20[0xe0];
4174 
4175 	u8         sm_virt_aware[0x1];
4176 	u8         has_smi[0x1];
4177 	u8         has_raw[0x1];
4178 	u8         grh_required[0x1];
4179 	u8         reserved_at_104[0xc];
4180 	u8         port_physical_state[0x4];
4181 	u8         vport_state_policy[0x4];
4182 	u8         port_state[0x4];
4183 	u8         vport_state[0x4];
4184 
4185 	u8         reserved_at_120[0x20];
4186 
4187 	u8         system_image_guid[0x40];
4188 
4189 	u8         port_guid[0x40];
4190 
4191 	u8         node_guid[0x40];
4192 
4193 	u8         cap_mask1[0x20];
4194 
4195 	u8         cap_mask1_field_select[0x20];
4196 
4197 	u8         cap_mask2[0x20];
4198 
4199 	u8         cap_mask2_field_select[0x20];
4200 
4201 	u8         reserved_at_280[0x80];
4202 
4203 	u8         lid[0x10];
4204 	u8         reserved_at_310[0x4];
4205 	u8         init_type_reply[0x4];
4206 	u8         lmc[0x3];
4207 	u8         subnet_timeout[0x5];
4208 
4209 	u8         sm_lid[0x10];
4210 	u8         sm_sl[0x4];
4211 	u8         reserved_at_334[0xc];
4212 
4213 	u8         qkey_violation_counter[0x10];
4214 	u8         pkey_violation_counter[0x10];
4215 
4216 	u8         reserved_at_360[0xca0];
4217 };
4218 
4219 struct mlx5_ifc_esw_vport_context_bits {
4220 	u8         fdb_to_vport_reg_c[0x1];
4221 	u8         reserved_at_1[0x2];
4222 	u8         vport_svlan_strip[0x1];
4223 	u8         vport_cvlan_strip[0x1];
4224 	u8         vport_svlan_insert[0x1];
4225 	u8         vport_cvlan_insert[0x2];
4226 	u8         fdb_to_vport_reg_c_id[0x8];
4227 	u8         reserved_at_10[0x10];
4228 
4229 	u8         reserved_at_20[0x20];
4230 
4231 	u8         svlan_cfi[0x1];
4232 	u8         svlan_pcp[0x3];
4233 	u8         svlan_id[0xc];
4234 	u8         cvlan_cfi[0x1];
4235 	u8         cvlan_pcp[0x3];
4236 	u8         cvlan_id[0xc];
4237 
4238 	u8         reserved_at_60[0x720];
4239 
4240 	u8         sw_steering_vport_icm_address_rx[0x40];
4241 
4242 	u8         sw_steering_vport_icm_address_tx[0x40];
4243 };
4244 
4245 enum {
4246 	MLX5_EQC_STATUS_OK                = 0x0,
4247 	MLX5_EQC_STATUS_EQ_WRITE_FAILURE  = 0xa,
4248 };
4249 
4250 enum {
4251 	MLX5_EQC_ST_ARMED  = 0x9,
4252 	MLX5_EQC_ST_FIRED  = 0xa,
4253 };
4254 
4255 struct mlx5_ifc_eqc_bits {
4256 	u8         status[0x4];
4257 	u8         reserved_at_4[0x9];
4258 	u8         ec[0x1];
4259 	u8         oi[0x1];
4260 	u8         reserved_at_f[0x5];
4261 	u8         st[0x4];
4262 	u8         reserved_at_18[0x8];
4263 
4264 	u8         reserved_at_20[0x20];
4265 
4266 	u8         reserved_at_40[0x14];
4267 	u8         page_offset[0x6];
4268 	u8         reserved_at_5a[0x6];
4269 
4270 	u8         reserved_at_60[0x3];
4271 	u8         log_eq_size[0x5];
4272 	u8         uar_page[0x18];
4273 
4274 	u8         reserved_at_80[0x20];
4275 
4276 	u8         reserved_at_a0[0x14];
4277 	u8         intr[0xc];
4278 
4279 	u8         reserved_at_c0[0x3];
4280 	u8         log_page_size[0x5];
4281 	u8         reserved_at_c8[0x18];
4282 
4283 	u8         reserved_at_e0[0x60];
4284 
4285 	u8         reserved_at_140[0x8];
4286 	u8         consumer_counter[0x18];
4287 
4288 	u8         reserved_at_160[0x8];
4289 	u8         producer_counter[0x18];
4290 
4291 	u8         reserved_at_180[0x80];
4292 };
4293 
4294 enum {
4295 	MLX5_DCTC_STATE_ACTIVE    = 0x0,
4296 	MLX5_DCTC_STATE_DRAINING  = 0x1,
4297 	MLX5_DCTC_STATE_DRAINED   = 0x2,
4298 };
4299 
4300 enum {
4301 	MLX5_DCTC_CS_RES_DISABLE    = 0x0,
4302 	MLX5_DCTC_CS_RES_NA         = 0x1,
4303 	MLX5_DCTC_CS_RES_UP_TO_64B  = 0x2,
4304 };
4305 
4306 enum {
4307 	MLX5_DCTC_MTU_256_BYTES  = 0x1,
4308 	MLX5_DCTC_MTU_512_BYTES  = 0x2,
4309 	MLX5_DCTC_MTU_1K_BYTES   = 0x3,
4310 	MLX5_DCTC_MTU_2K_BYTES   = 0x4,
4311 	MLX5_DCTC_MTU_4K_BYTES   = 0x5,
4312 };
4313 
4314 struct mlx5_ifc_dctc_bits {
4315 	u8         reserved_at_0[0x4];
4316 	u8         state[0x4];
4317 	u8         reserved_at_8[0x18];
4318 
4319 	u8         reserved_at_20[0x8];
4320 	u8         user_index[0x18];
4321 
4322 	u8         reserved_at_40[0x8];
4323 	u8         cqn[0x18];
4324 
4325 	u8         counter_set_id[0x8];
4326 	u8         atomic_mode[0x4];
4327 	u8         rre[0x1];
4328 	u8         rwe[0x1];
4329 	u8         rae[0x1];
4330 	u8         atomic_like_write_en[0x1];
4331 	u8         latency_sensitive[0x1];
4332 	u8         rlky[0x1];
4333 	u8         free_ar[0x1];
4334 	u8         reserved_at_73[0xd];
4335 
4336 	u8         reserved_at_80[0x8];
4337 	u8         cs_res[0x8];
4338 	u8         reserved_at_90[0x3];
4339 	u8         min_rnr_nak[0x5];
4340 	u8         reserved_at_98[0x8];
4341 
4342 	u8         reserved_at_a0[0x8];
4343 	u8         srqn_xrqn[0x18];
4344 
4345 	u8         reserved_at_c0[0x8];
4346 	u8         pd[0x18];
4347 
4348 	u8         tclass[0x8];
4349 	u8         reserved_at_e8[0x4];
4350 	u8         flow_label[0x14];
4351 
4352 	u8         dc_access_key[0x40];
4353 
4354 	u8         reserved_at_140[0x5];
4355 	u8         mtu[0x3];
4356 	u8         port[0x8];
4357 	u8         pkey_index[0x10];
4358 
4359 	u8         reserved_at_160[0x8];
4360 	u8         my_addr_index[0x8];
4361 	u8         reserved_at_170[0x8];
4362 	u8         hop_limit[0x8];
4363 
4364 	u8         dc_access_key_violation_count[0x20];
4365 
4366 	u8         reserved_at_1a0[0x14];
4367 	u8         dei_cfi[0x1];
4368 	u8         eth_prio[0x3];
4369 	u8         ecn[0x2];
4370 	u8         dscp[0x6];
4371 
4372 	u8         reserved_at_1c0[0x20];
4373 	u8         ece[0x20];
4374 };
4375 
4376 enum {
4377 	MLX5_CQC_STATUS_OK             = 0x0,
4378 	MLX5_CQC_STATUS_CQ_OVERFLOW    = 0x9,
4379 	MLX5_CQC_STATUS_CQ_WRITE_FAIL  = 0xa,
4380 };
4381 
4382 enum {
4383 	MLX5_CQC_CQE_SZ_64_BYTES   = 0x0,
4384 	MLX5_CQC_CQE_SZ_128_BYTES  = 0x1,
4385 };
4386 
4387 enum {
4388 	MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED  = 0x6,
4389 	MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED            = 0x9,
4390 	MLX5_CQC_ST_FIRED                                 = 0xa,
4391 };
4392 
4393 enum mlx5_cq_period_mode {
4394 	MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0,
4395 	MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1,
4396 	MLX5_CQ_PERIOD_NUM_MODES,
4397 };
4398 
4399 struct mlx5_ifc_cqc_bits {
4400 	u8         status[0x4];
4401 	u8         reserved_at_4[0x2];
4402 	u8         dbr_umem_valid[0x1];
4403 	u8         apu_cq[0x1];
4404 	u8         cqe_sz[0x3];
4405 	u8         cc[0x1];
4406 	u8         reserved_at_c[0x1];
4407 	u8         scqe_break_moderation_en[0x1];
4408 	u8         oi[0x1];
4409 	u8         cq_period_mode[0x2];
4410 	u8         cqe_comp_en[0x1];
4411 	u8         mini_cqe_res_format[0x2];
4412 	u8         st[0x4];
4413 	u8         reserved_at_18[0x6];
4414 	u8         cqe_compression_layout[0x2];
4415 
4416 	u8         reserved_at_20[0x20];
4417 
4418 	u8         reserved_at_40[0x14];
4419 	u8         page_offset[0x6];
4420 	u8         reserved_at_5a[0x6];
4421 
4422 	u8         reserved_at_60[0x3];
4423 	u8         log_cq_size[0x5];
4424 	u8         uar_page[0x18];
4425 
4426 	u8         reserved_at_80[0x4];
4427 	u8         cq_period[0xc];
4428 	u8         cq_max_count[0x10];
4429 
4430 	u8         c_eqn_or_apu_element[0x20];
4431 
4432 	u8         reserved_at_c0[0x3];
4433 	u8         log_page_size[0x5];
4434 	u8         reserved_at_c8[0x18];
4435 
4436 	u8         reserved_at_e0[0x20];
4437 
4438 	u8         reserved_at_100[0x8];
4439 	u8         last_notified_index[0x18];
4440 
4441 	u8         reserved_at_120[0x8];
4442 	u8         last_solicit_index[0x18];
4443 
4444 	u8         reserved_at_140[0x8];
4445 	u8         consumer_counter[0x18];
4446 
4447 	u8         reserved_at_160[0x8];
4448 	u8         producer_counter[0x18];
4449 
4450 	u8         reserved_at_180[0x40];
4451 
4452 	u8         dbr_addr[0x40];
4453 };
4454 
4455 union mlx5_ifc_cong_control_roce_ecn_auto_bits {
4456 	struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
4457 	struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
4458 	struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
4459 	struct mlx5_ifc_cong_control_r_roce_general_bits cong_control_r_roce_general;
4460 	u8         reserved_at_0[0x800];
4461 };
4462 
4463 struct mlx5_ifc_query_adapter_param_block_bits {
4464 	u8         reserved_at_0[0xc0];
4465 
4466 	u8         reserved_at_c0[0x8];
4467 	u8         ieee_vendor_id[0x18];
4468 
4469 	u8         reserved_at_e0[0x10];
4470 	u8         vsd_vendor_id[0x10];
4471 
4472 	u8         vsd[208][0x8];
4473 
4474 	u8         vsd_contd_psid[16][0x8];
4475 };
4476 
4477 enum {
4478 	MLX5_XRQC_STATE_GOOD   = 0x0,
4479 	MLX5_XRQC_STATE_ERROR  = 0x1,
4480 };
4481 
4482 enum {
4483 	MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0,
4484 	MLX5_XRQC_TOPOLOGY_TAG_MATCHING        = 0x1,
4485 };
4486 
4487 enum {
4488 	MLX5_XRQC_OFFLOAD_RNDV = 0x1,
4489 };
4490 
4491 struct mlx5_ifc_tag_matching_topology_context_bits {
4492 	u8         log_matching_list_sz[0x4];
4493 	u8         reserved_at_4[0xc];
4494 	u8         append_next_index[0x10];
4495 
4496 	u8         sw_phase_cnt[0x10];
4497 	u8         hw_phase_cnt[0x10];
4498 
4499 	u8         reserved_at_40[0x40];
4500 };
4501 
4502 struct mlx5_ifc_xrqc_bits {
4503 	u8         state[0x4];
4504 	u8         rlkey[0x1];
4505 	u8         reserved_at_5[0xf];
4506 	u8         topology[0x4];
4507 	u8         reserved_at_18[0x4];
4508 	u8         offload[0x4];
4509 
4510 	u8         reserved_at_20[0x8];
4511 	u8         user_index[0x18];
4512 
4513 	u8         reserved_at_40[0x8];
4514 	u8         cqn[0x18];
4515 
4516 	u8         reserved_at_60[0xa0];
4517 
4518 	struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context;
4519 
4520 	u8         reserved_at_180[0x280];
4521 
4522 	struct mlx5_ifc_wq_bits wq;
4523 };
4524 
4525 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits {
4526 	struct mlx5_ifc_modify_field_select_bits modify_field_select;
4527 	struct mlx5_ifc_resize_field_select_bits resize_field_select;
4528 	u8         reserved_at_0[0x20];
4529 };
4530 
4531 union mlx5_ifc_field_select_802_1_r_roce_auto_bits {
4532 	struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp;
4533 	struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp;
4534 	struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np;
4535 	u8         reserved_at_0[0x20];
4536 };
4537 
4538 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
4539 	struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
4540 	struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
4541 	struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
4542 	struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
4543 	struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
4544 	struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
4545 	struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout;
4546 	struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout;
4547 	struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
4548 	struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
4549 	struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs;
4550 	u8         reserved_at_0[0x7c0];
4551 };
4552 
4553 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits {
4554 	struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout;
4555 	u8         reserved_at_0[0x7c0];
4556 };
4557 
4558 union mlx5_ifc_event_auto_bits {
4559 	struct mlx5_ifc_comp_event_bits comp_event;
4560 	struct mlx5_ifc_dct_events_bits dct_events;
4561 	struct mlx5_ifc_qp_events_bits qp_events;
4562 	struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event;
4563 	struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event;
4564 	struct mlx5_ifc_cq_error_bits cq_error;
4565 	struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged;
4566 	struct mlx5_ifc_port_state_change_event_bits port_state_change_event;
4567 	struct mlx5_ifc_gpio_event_bits gpio_event;
4568 	struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event;
4569 	struct mlx5_ifc_stall_vl_event_bits stall_vl_event;
4570 	struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event;
4571 	u8         reserved_at_0[0xe0];
4572 };
4573 
4574 struct mlx5_ifc_health_buffer_bits {
4575 	u8         reserved_at_0[0x100];
4576 
4577 	u8         assert_existptr[0x20];
4578 
4579 	u8         assert_callra[0x20];
4580 
4581 	u8         reserved_at_140[0x20];
4582 
4583 	u8         time[0x20];
4584 
4585 	u8         fw_version[0x20];
4586 
4587 	u8         hw_id[0x20];
4588 
4589 	u8         rfr[0x1];
4590 	u8         reserved_at_1c1[0x3];
4591 	u8         valid[0x1];
4592 	u8         severity[0x3];
4593 	u8         reserved_at_1c8[0x18];
4594 
4595 	u8         irisc_index[0x8];
4596 	u8         synd[0x8];
4597 	u8         ext_synd[0x10];
4598 };
4599 
4600 struct mlx5_ifc_register_loopback_control_bits {
4601 	u8         no_lb[0x1];
4602 	u8         reserved_at_1[0x7];
4603 	u8         port[0x8];
4604 	u8         reserved_at_10[0x10];
4605 
4606 	u8         reserved_at_20[0x60];
4607 };
4608 
4609 struct mlx5_ifc_vport_tc_element_bits {
4610 	u8         traffic_class[0x4];
4611 	u8         reserved_at_4[0xc];
4612 	u8         vport_number[0x10];
4613 };
4614 
4615 struct mlx5_ifc_vport_element_bits {
4616 	u8         reserved_at_0[0x10];
4617 	u8         vport_number[0x10];
4618 };
4619 
4620 enum {
4621 	TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0,
4622 	TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1,
4623 	TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2,
4624 };
4625 
4626 struct mlx5_ifc_tsar_element_bits {
4627 	u8         reserved_at_0[0x8];
4628 	u8         tsar_type[0x8];
4629 	u8         reserved_at_10[0x10];
4630 };
4631 
4632 enum {
4633 	MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0,
4634 	MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1,
4635 };
4636 
4637 struct mlx5_ifc_teardown_hca_out_bits {
4638 	u8         status[0x8];
4639 	u8         reserved_at_8[0x18];
4640 
4641 	u8         syndrome[0x20];
4642 
4643 	u8         reserved_at_40[0x3f];
4644 
4645 	u8         state[0x1];
4646 };
4647 
4648 enum {
4649 	MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE  = 0x0,
4650 	MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE     = 0x1,
4651 	MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN = 0x2,
4652 };
4653 
4654 struct mlx5_ifc_teardown_hca_in_bits {
4655 	u8         opcode[0x10];
4656 	u8         reserved_at_10[0x10];
4657 
4658 	u8         reserved_at_20[0x10];
4659 	u8         op_mod[0x10];
4660 
4661 	u8         reserved_at_40[0x10];
4662 	u8         profile[0x10];
4663 
4664 	u8         reserved_at_60[0x20];
4665 };
4666 
4667 struct mlx5_ifc_sqerr2rts_qp_out_bits {
4668 	u8         status[0x8];
4669 	u8         reserved_at_8[0x18];
4670 
4671 	u8         syndrome[0x20];
4672 
4673 	u8         reserved_at_40[0x40];
4674 };
4675 
4676 struct mlx5_ifc_sqerr2rts_qp_in_bits {
4677 	u8         opcode[0x10];
4678 	u8         uid[0x10];
4679 
4680 	u8         reserved_at_20[0x10];
4681 	u8         op_mod[0x10];
4682 
4683 	u8         reserved_at_40[0x8];
4684 	u8         qpn[0x18];
4685 
4686 	u8         reserved_at_60[0x20];
4687 
4688 	u8         opt_param_mask[0x20];
4689 
4690 	u8         reserved_at_a0[0x20];
4691 
4692 	struct mlx5_ifc_qpc_bits qpc;
4693 
4694 	u8         reserved_at_800[0x80];
4695 };
4696 
4697 struct mlx5_ifc_sqd2rts_qp_out_bits {
4698 	u8         status[0x8];
4699 	u8         reserved_at_8[0x18];
4700 
4701 	u8         syndrome[0x20];
4702 
4703 	u8         reserved_at_40[0x40];
4704 };
4705 
4706 struct mlx5_ifc_sqd2rts_qp_in_bits {
4707 	u8         opcode[0x10];
4708 	u8         uid[0x10];
4709 
4710 	u8         reserved_at_20[0x10];
4711 	u8         op_mod[0x10];
4712 
4713 	u8         reserved_at_40[0x8];
4714 	u8         qpn[0x18];
4715 
4716 	u8         reserved_at_60[0x20];
4717 
4718 	u8         opt_param_mask[0x20];
4719 
4720 	u8         reserved_at_a0[0x20];
4721 
4722 	struct mlx5_ifc_qpc_bits qpc;
4723 
4724 	u8         reserved_at_800[0x80];
4725 };
4726 
4727 struct mlx5_ifc_set_roce_address_out_bits {
4728 	u8         status[0x8];
4729 	u8         reserved_at_8[0x18];
4730 
4731 	u8         syndrome[0x20];
4732 
4733 	u8         reserved_at_40[0x40];
4734 };
4735 
4736 struct mlx5_ifc_set_roce_address_in_bits {
4737 	u8         opcode[0x10];
4738 	u8         reserved_at_10[0x10];
4739 
4740 	u8         reserved_at_20[0x10];
4741 	u8         op_mod[0x10];
4742 
4743 	u8         roce_address_index[0x10];
4744 	u8         reserved_at_50[0xc];
4745 	u8	   vhca_port_num[0x4];
4746 
4747 	u8         reserved_at_60[0x20];
4748 
4749 	struct mlx5_ifc_roce_addr_layout_bits roce_address;
4750 };
4751 
4752 struct mlx5_ifc_set_mad_demux_out_bits {
4753 	u8         status[0x8];
4754 	u8         reserved_at_8[0x18];
4755 
4756 	u8         syndrome[0x20];
4757 
4758 	u8         reserved_at_40[0x40];
4759 };
4760 
4761 enum {
4762 	MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL   = 0x0,
4763 	MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE  = 0x2,
4764 };
4765 
4766 struct mlx5_ifc_set_mad_demux_in_bits {
4767 	u8         opcode[0x10];
4768 	u8         reserved_at_10[0x10];
4769 
4770 	u8         reserved_at_20[0x10];
4771 	u8         op_mod[0x10];
4772 
4773 	u8         reserved_at_40[0x20];
4774 
4775 	u8         reserved_at_60[0x6];
4776 	u8         demux_mode[0x2];
4777 	u8         reserved_at_68[0x18];
4778 };
4779 
4780 struct mlx5_ifc_set_l2_table_entry_out_bits {
4781 	u8         status[0x8];
4782 	u8         reserved_at_8[0x18];
4783 
4784 	u8         syndrome[0x20];
4785 
4786 	u8         reserved_at_40[0x40];
4787 };
4788 
4789 struct mlx5_ifc_set_l2_table_entry_in_bits {
4790 	u8         opcode[0x10];
4791 	u8         reserved_at_10[0x10];
4792 
4793 	u8         reserved_at_20[0x10];
4794 	u8         op_mod[0x10];
4795 
4796 	u8         reserved_at_40[0x60];
4797 
4798 	u8         reserved_at_a0[0x8];
4799 	u8         table_index[0x18];
4800 
4801 	u8         reserved_at_c0[0x20];
4802 
4803 	u8         reserved_at_e0[0x10];
4804 	u8         silent_mode_valid[0x1];
4805 	u8         silent_mode[0x1];
4806 	u8         reserved_at_f2[0x1];
4807 	u8         vlan_valid[0x1];
4808 	u8         vlan[0xc];
4809 
4810 	struct mlx5_ifc_mac_address_layout_bits mac_address;
4811 
4812 	u8         reserved_at_140[0xc0];
4813 };
4814 
4815 struct mlx5_ifc_set_issi_out_bits {
4816 	u8         status[0x8];
4817 	u8         reserved_at_8[0x18];
4818 
4819 	u8         syndrome[0x20];
4820 
4821 	u8         reserved_at_40[0x40];
4822 };
4823 
4824 struct mlx5_ifc_set_issi_in_bits {
4825 	u8         opcode[0x10];
4826 	u8         reserved_at_10[0x10];
4827 
4828 	u8         reserved_at_20[0x10];
4829 	u8         op_mod[0x10];
4830 
4831 	u8         reserved_at_40[0x10];
4832 	u8         current_issi[0x10];
4833 
4834 	u8         reserved_at_60[0x20];
4835 };
4836 
4837 struct mlx5_ifc_set_hca_cap_out_bits {
4838 	u8         status[0x8];
4839 	u8         reserved_at_8[0x18];
4840 
4841 	u8         syndrome[0x20];
4842 
4843 	u8         reserved_at_40[0x40];
4844 };
4845 
4846 struct mlx5_ifc_set_hca_cap_in_bits {
4847 	u8         opcode[0x10];
4848 	u8         reserved_at_10[0x10];
4849 
4850 	u8         reserved_at_20[0x10];
4851 	u8         op_mod[0x10];
4852 
4853 	u8         other_function[0x1];
4854 	u8         ec_vf_function[0x1];
4855 	u8         reserved_at_42[0xe];
4856 	u8         function_id[0x10];
4857 
4858 	u8         reserved_at_60[0x20];
4859 
4860 	union mlx5_ifc_hca_cap_union_bits capability;
4861 };
4862 
4863 enum {
4864 	MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION    = 0x0,
4865 	MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG  = 0x1,
4866 	MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST    = 0x2,
4867 	MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS    = 0x3,
4868 	MLX5_SET_FTE_MODIFY_ENABLE_MASK_IPSEC_OBJ_ID    = 0x4
4869 };
4870 
4871 struct mlx5_ifc_set_fte_out_bits {
4872 	u8         status[0x8];
4873 	u8         reserved_at_8[0x18];
4874 
4875 	u8         syndrome[0x20];
4876 
4877 	u8         reserved_at_40[0x40];
4878 };
4879 
4880 struct mlx5_ifc_set_fte_in_bits {
4881 	u8         opcode[0x10];
4882 	u8         reserved_at_10[0x10];
4883 
4884 	u8         reserved_at_20[0x10];
4885 	u8         op_mod[0x10];
4886 
4887 	u8         other_vport[0x1];
4888 	u8         reserved_at_41[0xf];
4889 	u8         vport_number[0x10];
4890 
4891 	u8         reserved_at_60[0x20];
4892 
4893 	u8         table_type[0x8];
4894 	u8         reserved_at_88[0x18];
4895 
4896 	u8         reserved_at_a0[0x8];
4897 	u8         table_id[0x18];
4898 
4899 	u8         ignore_flow_level[0x1];
4900 	u8         reserved_at_c1[0x17];
4901 	u8         modify_enable_mask[0x8];
4902 
4903 	u8         reserved_at_e0[0x20];
4904 
4905 	u8         flow_index[0x20];
4906 
4907 	u8         reserved_at_120[0xe0];
4908 
4909 	struct mlx5_ifc_flow_context_bits flow_context;
4910 };
4911 
4912 struct mlx5_ifc_rts2rts_qp_out_bits {
4913 	u8         status[0x8];
4914 	u8         reserved_at_8[0x18];
4915 
4916 	u8         syndrome[0x20];
4917 
4918 	u8         reserved_at_40[0x20];
4919 	u8         ece[0x20];
4920 };
4921 
4922 struct mlx5_ifc_rts2rts_qp_in_bits {
4923 	u8         opcode[0x10];
4924 	u8         uid[0x10];
4925 
4926 	u8         reserved_at_20[0x10];
4927 	u8         op_mod[0x10];
4928 
4929 	u8         reserved_at_40[0x8];
4930 	u8         qpn[0x18];
4931 
4932 	u8         reserved_at_60[0x20];
4933 
4934 	u8         opt_param_mask[0x20];
4935 
4936 	u8         ece[0x20];
4937 
4938 	struct mlx5_ifc_qpc_bits qpc;
4939 
4940 	u8         reserved_at_800[0x80];
4941 };
4942 
4943 struct mlx5_ifc_rtr2rts_qp_out_bits {
4944 	u8         status[0x8];
4945 	u8         reserved_at_8[0x18];
4946 
4947 	u8         syndrome[0x20];
4948 
4949 	u8         reserved_at_40[0x20];
4950 	u8         ece[0x20];
4951 };
4952 
4953 struct mlx5_ifc_rtr2rts_qp_in_bits {
4954 	u8         opcode[0x10];
4955 	u8         uid[0x10];
4956 
4957 	u8         reserved_at_20[0x10];
4958 	u8         op_mod[0x10];
4959 
4960 	u8         reserved_at_40[0x8];
4961 	u8         qpn[0x18];
4962 
4963 	u8         reserved_at_60[0x20];
4964 
4965 	u8         opt_param_mask[0x20];
4966 
4967 	u8         ece[0x20];
4968 
4969 	struct mlx5_ifc_qpc_bits qpc;
4970 
4971 	u8         reserved_at_800[0x80];
4972 };
4973 
4974 struct mlx5_ifc_rst2init_qp_out_bits {
4975 	u8         status[0x8];
4976 	u8         reserved_at_8[0x18];
4977 
4978 	u8         syndrome[0x20];
4979 
4980 	u8         reserved_at_40[0x20];
4981 	u8         ece[0x20];
4982 };
4983 
4984 struct mlx5_ifc_rst2init_qp_in_bits {
4985 	u8         opcode[0x10];
4986 	u8         uid[0x10];
4987 
4988 	u8         reserved_at_20[0x10];
4989 	u8         op_mod[0x10];
4990 
4991 	u8         reserved_at_40[0x8];
4992 	u8         qpn[0x18];
4993 
4994 	u8         reserved_at_60[0x20];
4995 
4996 	u8         opt_param_mask[0x20];
4997 
4998 	u8         ece[0x20];
4999 
5000 	struct mlx5_ifc_qpc_bits qpc;
5001 
5002 	u8         reserved_at_800[0x80];
5003 };
5004 
5005 struct mlx5_ifc_query_xrq_out_bits {
5006 	u8         status[0x8];
5007 	u8         reserved_at_8[0x18];
5008 
5009 	u8         syndrome[0x20];
5010 
5011 	u8         reserved_at_40[0x40];
5012 
5013 	struct mlx5_ifc_xrqc_bits xrq_context;
5014 };
5015 
5016 struct mlx5_ifc_query_xrq_in_bits {
5017 	u8         opcode[0x10];
5018 	u8         reserved_at_10[0x10];
5019 
5020 	u8         reserved_at_20[0x10];
5021 	u8         op_mod[0x10];
5022 
5023 	u8         reserved_at_40[0x8];
5024 	u8         xrqn[0x18];
5025 
5026 	u8         reserved_at_60[0x20];
5027 };
5028 
5029 struct mlx5_ifc_query_xrc_srq_out_bits {
5030 	u8         status[0x8];
5031 	u8         reserved_at_8[0x18];
5032 
5033 	u8         syndrome[0x20];
5034 
5035 	u8         reserved_at_40[0x40];
5036 
5037 	struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
5038 
5039 	u8         reserved_at_280[0x600];
5040 
5041 	u8         pas[][0x40];
5042 };
5043 
5044 struct mlx5_ifc_query_xrc_srq_in_bits {
5045 	u8         opcode[0x10];
5046 	u8         reserved_at_10[0x10];
5047 
5048 	u8         reserved_at_20[0x10];
5049 	u8         op_mod[0x10];
5050 
5051 	u8         reserved_at_40[0x8];
5052 	u8         xrc_srqn[0x18];
5053 
5054 	u8         reserved_at_60[0x20];
5055 };
5056 
5057 enum {
5058 	MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN  = 0x0,
5059 	MLX5_QUERY_VPORT_STATE_OUT_STATE_UP    = 0x1,
5060 };
5061 
5062 struct mlx5_ifc_query_vport_state_out_bits {
5063 	u8         status[0x8];
5064 	u8         reserved_at_8[0x18];
5065 
5066 	u8         syndrome[0x20];
5067 
5068 	u8         reserved_at_40[0x20];
5069 
5070 	u8         reserved_at_60[0x18];
5071 	u8         admin_state[0x4];
5072 	u8         state[0x4];
5073 };
5074 
5075 enum {
5076 	MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT  = 0x0,
5077 	MLX5_VPORT_STATE_OP_MOD_ESW_VPORT   = 0x1,
5078 	MLX5_VPORT_STATE_OP_MOD_UPLINK      = 0x2,
5079 };
5080 
5081 struct mlx5_ifc_arm_monitor_counter_in_bits {
5082 	u8         opcode[0x10];
5083 	u8         uid[0x10];
5084 
5085 	u8         reserved_at_20[0x10];
5086 	u8         op_mod[0x10];
5087 
5088 	u8         reserved_at_40[0x20];
5089 
5090 	u8         reserved_at_60[0x20];
5091 };
5092 
5093 struct mlx5_ifc_arm_monitor_counter_out_bits {
5094 	u8         status[0x8];
5095 	u8         reserved_at_8[0x18];
5096 
5097 	u8         syndrome[0x20];
5098 
5099 	u8         reserved_at_40[0x40];
5100 };
5101 
5102 enum {
5103 	MLX5_QUERY_MONITOR_CNT_TYPE_PPCNT     = 0x0,
5104 	MLX5_QUERY_MONITOR_CNT_TYPE_Q_COUNTER = 0x1,
5105 };
5106 
5107 enum mlx5_monitor_counter_ppcnt {
5108 	MLX5_QUERY_MONITOR_PPCNT_IN_RANGE_LENGTH_ERRORS      = 0x0,
5109 	MLX5_QUERY_MONITOR_PPCNT_OUT_OF_RANGE_LENGTH_FIELD   = 0x1,
5110 	MLX5_QUERY_MONITOR_PPCNT_FRAME_TOO_LONG_ERRORS       = 0x2,
5111 	MLX5_QUERY_MONITOR_PPCNT_FRAME_CHECK_SEQUENCE_ERRORS = 0x3,
5112 	MLX5_QUERY_MONITOR_PPCNT_ALIGNMENT_ERRORS            = 0x4,
5113 	MLX5_QUERY_MONITOR_PPCNT_IF_OUT_DISCARDS             = 0x5,
5114 };
5115 
5116 enum {
5117 	MLX5_QUERY_MONITOR_Q_COUNTER_RX_OUT_OF_BUFFER     = 0x4,
5118 };
5119 
5120 struct mlx5_ifc_monitor_counter_output_bits {
5121 	u8         reserved_at_0[0x4];
5122 	u8         type[0x4];
5123 	u8         reserved_at_8[0x8];
5124 	u8         counter[0x10];
5125 
5126 	u8         counter_group_id[0x20];
5127 };
5128 
5129 #define MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 (6)
5130 #define MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1    (1)
5131 #define MLX5_CMD_SET_MONITOR_NUM_COUNTER (MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 +\
5132 					  MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1)
5133 
5134 struct mlx5_ifc_set_monitor_counter_in_bits {
5135 	u8         opcode[0x10];
5136 	u8         uid[0x10];
5137 
5138 	u8         reserved_at_20[0x10];
5139 	u8         op_mod[0x10];
5140 
5141 	u8         reserved_at_40[0x10];
5142 	u8         num_of_counters[0x10];
5143 
5144 	u8         reserved_at_60[0x20];
5145 
5146 	struct mlx5_ifc_monitor_counter_output_bits monitor_counter[MLX5_CMD_SET_MONITOR_NUM_COUNTER];
5147 };
5148 
5149 struct mlx5_ifc_set_monitor_counter_out_bits {
5150 	u8         status[0x8];
5151 	u8         reserved_at_8[0x18];
5152 
5153 	u8         syndrome[0x20];
5154 
5155 	u8         reserved_at_40[0x40];
5156 };
5157 
5158 struct mlx5_ifc_query_vport_state_in_bits {
5159 	u8         opcode[0x10];
5160 	u8         reserved_at_10[0x10];
5161 
5162 	u8         reserved_at_20[0x10];
5163 	u8         op_mod[0x10];
5164 
5165 	u8         other_vport[0x1];
5166 	u8         reserved_at_41[0xf];
5167 	u8         vport_number[0x10];
5168 
5169 	u8         reserved_at_60[0x20];
5170 };
5171 
5172 struct mlx5_ifc_query_vnic_env_out_bits {
5173 	u8         status[0x8];
5174 	u8         reserved_at_8[0x18];
5175 
5176 	u8         syndrome[0x20];
5177 
5178 	u8         reserved_at_40[0x40];
5179 
5180 	struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env;
5181 };
5182 
5183 enum {
5184 	MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS  = 0x0,
5185 };
5186 
5187 struct mlx5_ifc_query_vnic_env_in_bits {
5188 	u8         opcode[0x10];
5189 	u8         reserved_at_10[0x10];
5190 
5191 	u8         reserved_at_20[0x10];
5192 	u8         op_mod[0x10];
5193 
5194 	u8         other_vport[0x1];
5195 	u8         reserved_at_41[0xf];
5196 	u8         vport_number[0x10];
5197 
5198 	u8         reserved_at_60[0x20];
5199 };
5200 
5201 struct mlx5_ifc_query_vport_counter_out_bits {
5202 	u8         status[0x8];
5203 	u8         reserved_at_8[0x18];
5204 
5205 	u8         syndrome[0x20];
5206 
5207 	u8         reserved_at_40[0x40];
5208 
5209 	struct mlx5_ifc_traffic_counter_bits received_errors;
5210 
5211 	struct mlx5_ifc_traffic_counter_bits transmit_errors;
5212 
5213 	struct mlx5_ifc_traffic_counter_bits received_ib_unicast;
5214 
5215 	struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast;
5216 
5217 	struct mlx5_ifc_traffic_counter_bits received_ib_multicast;
5218 
5219 	struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast;
5220 
5221 	struct mlx5_ifc_traffic_counter_bits received_eth_broadcast;
5222 
5223 	struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast;
5224 
5225 	struct mlx5_ifc_traffic_counter_bits received_eth_unicast;
5226 
5227 	struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast;
5228 
5229 	struct mlx5_ifc_traffic_counter_bits received_eth_multicast;
5230 
5231 	struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast;
5232 
5233 	struct mlx5_ifc_traffic_counter_bits local_loopback;
5234 
5235 	u8         reserved_at_700[0x980];
5236 };
5237 
5238 enum {
5239 	MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS  = 0x0,
5240 };
5241 
5242 struct mlx5_ifc_query_vport_counter_in_bits {
5243 	u8         opcode[0x10];
5244 	u8         reserved_at_10[0x10];
5245 
5246 	u8         reserved_at_20[0x10];
5247 	u8         op_mod[0x10];
5248 
5249 	u8         other_vport[0x1];
5250 	u8         reserved_at_41[0xb];
5251 	u8	   port_num[0x4];
5252 	u8         vport_number[0x10];
5253 
5254 	u8         reserved_at_60[0x60];
5255 
5256 	u8         clear[0x1];
5257 	u8         reserved_at_c1[0x1f];
5258 
5259 	u8         reserved_at_e0[0x20];
5260 };
5261 
5262 struct mlx5_ifc_query_tis_out_bits {
5263 	u8         status[0x8];
5264 	u8         reserved_at_8[0x18];
5265 
5266 	u8         syndrome[0x20];
5267 
5268 	u8         reserved_at_40[0x40];
5269 
5270 	struct mlx5_ifc_tisc_bits tis_context;
5271 };
5272 
5273 struct mlx5_ifc_query_tis_in_bits {
5274 	u8         opcode[0x10];
5275 	u8         reserved_at_10[0x10];
5276 
5277 	u8         reserved_at_20[0x10];
5278 	u8         op_mod[0x10];
5279 
5280 	u8         reserved_at_40[0x8];
5281 	u8         tisn[0x18];
5282 
5283 	u8         reserved_at_60[0x20];
5284 };
5285 
5286 struct mlx5_ifc_query_tir_out_bits {
5287 	u8         status[0x8];
5288 	u8         reserved_at_8[0x18];
5289 
5290 	u8         syndrome[0x20];
5291 
5292 	u8         reserved_at_40[0xc0];
5293 
5294 	struct mlx5_ifc_tirc_bits tir_context;
5295 };
5296 
5297 struct mlx5_ifc_query_tir_in_bits {
5298 	u8         opcode[0x10];
5299 	u8         reserved_at_10[0x10];
5300 
5301 	u8         reserved_at_20[0x10];
5302 	u8         op_mod[0x10];
5303 
5304 	u8         reserved_at_40[0x8];
5305 	u8         tirn[0x18];
5306 
5307 	u8         reserved_at_60[0x20];
5308 };
5309 
5310 struct mlx5_ifc_query_srq_out_bits {
5311 	u8         status[0x8];
5312 	u8         reserved_at_8[0x18];
5313 
5314 	u8         syndrome[0x20];
5315 
5316 	u8         reserved_at_40[0x40];
5317 
5318 	struct mlx5_ifc_srqc_bits srq_context_entry;
5319 
5320 	u8         reserved_at_280[0x600];
5321 
5322 	u8         pas[][0x40];
5323 };
5324 
5325 struct mlx5_ifc_query_srq_in_bits {
5326 	u8         opcode[0x10];
5327 	u8         reserved_at_10[0x10];
5328 
5329 	u8         reserved_at_20[0x10];
5330 	u8         op_mod[0x10];
5331 
5332 	u8         reserved_at_40[0x8];
5333 	u8         srqn[0x18];
5334 
5335 	u8         reserved_at_60[0x20];
5336 };
5337 
5338 struct mlx5_ifc_query_sq_out_bits {
5339 	u8         status[0x8];
5340 	u8         reserved_at_8[0x18];
5341 
5342 	u8         syndrome[0x20];
5343 
5344 	u8         reserved_at_40[0xc0];
5345 
5346 	struct mlx5_ifc_sqc_bits sq_context;
5347 };
5348 
5349 struct mlx5_ifc_query_sq_in_bits {
5350 	u8         opcode[0x10];
5351 	u8         reserved_at_10[0x10];
5352 
5353 	u8         reserved_at_20[0x10];
5354 	u8         op_mod[0x10];
5355 
5356 	u8         reserved_at_40[0x8];
5357 	u8         sqn[0x18];
5358 
5359 	u8         reserved_at_60[0x20];
5360 };
5361 
5362 struct mlx5_ifc_query_special_contexts_out_bits {
5363 	u8         status[0x8];
5364 	u8         reserved_at_8[0x18];
5365 
5366 	u8         syndrome[0x20];
5367 
5368 	u8         dump_fill_mkey[0x20];
5369 
5370 	u8         resd_lkey[0x20];
5371 
5372 	u8         null_mkey[0x20];
5373 
5374 	u8	   terminate_scatter_list_mkey[0x20];
5375 
5376 	u8	   repeated_mkey[0x20];
5377 
5378 	u8         reserved_at_a0[0x20];
5379 };
5380 
5381 struct mlx5_ifc_query_special_contexts_in_bits {
5382 	u8         opcode[0x10];
5383 	u8         reserved_at_10[0x10];
5384 
5385 	u8         reserved_at_20[0x10];
5386 	u8         op_mod[0x10];
5387 
5388 	u8         reserved_at_40[0x40];
5389 };
5390 
5391 struct mlx5_ifc_query_scheduling_element_out_bits {
5392 	u8         opcode[0x10];
5393 	u8         reserved_at_10[0x10];
5394 
5395 	u8         reserved_at_20[0x10];
5396 	u8         op_mod[0x10];
5397 
5398 	u8         reserved_at_40[0xc0];
5399 
5400 	struct mlx5_ifc_scheduling_context_bits scheduling_context;
5401 
5402 	u8         reserved_at_300[0x100];
5403 };
5404 
5405 enum {
5406 	SCHEDULING_HIERARCHY_E_SWITCH = 0x2,
5407 	SCHEDULING_HIERARCHY_NIC = 0x3,
5408 };
5409 
5410 struct mlx5_ifc_query_scheduling_element_in_bits {
5411 	u8         opcode[0x10];
5412 	u8         reserved_at_10[0x10];
5413 
5414 	u8         reserved_at_20[0x10];
5415 	u8         op_mod[0x10];
5416 
5417 	u8         scheduling_hierarchy[0x8];
5418 	u8         reserved_at_48[0x18];
5419 
5420 	u8         scheduling_element_id[0x20];
5421 
5422 	u8         reserved_at_80[0x180];
5423 };
5424 
5425 struct mlx5_ifc_query_rqt_out_bits {
5426 	u8         status[0x8];
5427 	u8         reserved_at_8[0x18];
5428 
5429 	u8         syndrome[0x20];
5430 
5431 	u8         reserved_at_40[0xc0];
5432 
5433 	struct mlx5_ifc_rqtc_bits rqt_context;
5434 };
5435 
5436 struct mlx5_ifc_query_rqt_in_bits {
5437 	u8         opcode[0x10];
5438 	u8         reserved_at_10[0x10];
5439 
5440 	u8         reserved_at_20[0x10];
5441 	u8         op_mod[0x10];
5442 
5443 	u8         reserved_at_40[0x8];
5444 	u8         rqtn[0x18];
5445 
5446 	u8         reserved_at_60[0x20];
5447 };
5448 
5449 struct mlx5_ifc_query_rq_out_bits {
5450 	u8         status[0x8];
5451 	u8         reserved_at_8[0x18];
5452 
5453 	u8         syndrome[0x20];
5454 
5455 	u8         reserved_at_40[0xc0];
5456 
5457 	struct mlx5_ifc_rqc_bits rq_context;
5458 };
5459 
5460 struct mlx5_ifc_query_rq_in_bits {
5461 	u8         opcode[0x10];
5462 	u8         reserved_at_10[0x10];
5463 
5464 	u8         reserved_at_20[0x10];
5465 	u8         op_mod[0x10];
5466 
5467 	u8         reserved_at_40[0x8];
5468 	u8         rqn[0x18];
5469 
5470 	u8         reserved_at_60[0x20];
5471 };
5472 
5473 struct mlx5_ifc_query_roce_address_out_bits {
5474 	u8         status[0x8];
5475 	u8         reserved_at_8[0x18];
5476 
5477 	u8         syndrome[0x20];
5478 
5479 	u8         reserved_at_40[0x40];
5480 
5481 	struct mlx5_ifc_roce_addr_layout_bits roce_address;
5482 };
5483 
5484 struct mlx5_ifc_query_roce_address_in_bits {
5485 	u8         opcode[0x10];
5486 	u8         reserved_at_10[0x10];
5487 
5488 	u8         reserved_at_20[0x10];
5489 	u8         op_mod[0x10];
5490 
5491 	u8         roce_address_index[0x10];
5492 	u8         reserved_at_50[0xc];
5493 	u8	   vhca_port_num[0x4];
5494 
5495 	u8         reserved_at_60[0x20];
5496 };
5497 
5498 struct mlx5_ifc_query_rmp_out_bits {
5499 	u8         status[0x8];
5500 	u8         reserved_at_8[0x18];
5501 
5502 	u8         syndrome[0x20];
5503 
5504 	u8         reserved_at_40[0xc0];
5505 
5506 	struct mlx5_ifc_rmpc_bits rmp_context;
5507 };
5508 
5509 struct mlx5_ifc_query_rmp_in_bits {
5510 	u8         opcode[0x10];
5511 	u8         reserved_at_10[0x10];
5512 
5513 	u8         reserved_at_20[0x10];
5514 	u8         op_mod[0x10];
5515 
5516 	u8         reserved_at_40[0x8];
5517 	u8         rmpn[0x18];
5518 
5519 	u8         reserved_at_60[0x20];
5520 };
5521 
5522 struct mlx5_ifc_cqe_error_syndrome_bits {
5523 	u8         hw_error_syndrome[0x8];
5524 	u8         hw_syndrome_type[0x4];
5525 	u8         reserved_at_c[0x4];
5526 	u8         vendor_error_syndrome[0x8];
5527 	u8         syndrome[0x8];
5528 };
5529 
5530 struct mlx5_ifc_qp_context_extension_bits {
5531 	u8         reserved_at_0[0x60];
5532 
5533 	struct mlx5_ifc_cqe_error_syndrome_bits error_syndrome;
5534 
5535 	u8         reserved_at_80[0x580];
5536 };
5537 
5538 struct mlx5_ifc_qpc_extension_and_pas_list_in_bits {
5539 	struct mlx5_ifc_qp_context_extension_bits qpc_data_extension;
5540 
5541 	u8         pas[0][0x40];
5542 };
5543 
5544 struct mlx5_ifc_qp_pas_list_in_bits {
5545 	struct mlx5_ifc_cmd_pas_bits pas[0];
5546 };
5547 
5548 union mlx5_ifc_qp_pas_or_qpc_ext_and_pas_bits {
5549 	struct mlx5_ifc_qp_pas_list_in_bits qp_pas_list;
5550 	struct mlx5_ifc_qpc_extension_and_pas_list_in_bits qpc_ext_and_pas_list;
5551 };
5552 
5553 struct mlx5_ifc_query_qp_out_bits {
5554 	u8         status[0x8];
5555 	u8         reserved_at_8[0x18];
5556 
5557 	u8         syndrome[0x20];
5558 
5559 	u8         reserved_at_40[0x40];
5560 
5561 	u8         opt_param_mask[0x20];
5562 
5563 	u8         ece[0x20];
5564 
5565 	struct mlx5_ifc_qpc_bits qpc;
5566 
5567 	u8         reserved_at_800[0x80];
5568 
5569 	union mlx5_ifc_qp_pas_or_qpc_ext_and_pas_bits qp_pas_or_qpc_ext_and_pas;
5570 };
5571 
5572 struct mlx5_ifc_query_qp_in_bits {
5573 	u8         opcode[0x10];
5574 	u8         reserved_at_10[0x10];
5575 
5576 	u8         reserved_at_20[0x10];
5577 	u8         op_mod[0x10];
5578 
5579 	u8         qpc_ext[0x1];
5580 	u8         reserved_at_41[0x7];
5581 	u8         qpn[0x18];
5582 
5583 	u8         reserved_at_60[0x20];
5584 };
5585 
5586 struct mlx5_ifc_query_q_counter_out_bits {
5587 	u8         status[0x8];
5588 	u8         reserved_at_8[0x18];
5589 
5590 	u8         syndrome[0x20];
5591 
5592 	u8         reserved_at_40[0x40];
5593 
5594 	u8         rx_write_requests[0x20];
5595 
5596 	u8         reserved_at_a0[0x20];
5597 
5598 	u8         rx_read_requests[0x20];
5599 
5600 	u8         reserved_at_e0[0x20];
5601 
5602 	u8         rx_atomic_requests[0x20];
5603 
5604 	u8         reserved_at_120[0x20];
5605 
5606 	u8         rx_dct_connect[0x20];
5607 
5608 	u8         reserved_at_160[0x20];
5609 
5610 	u8         out_of_buffer[0x20];
5611 
5612 	u8         reserved_at_1a0[0x20];
5613 
5614 	u8         out_of_sequence[0x20];
5615 
5616 	u8         reserved_at_1e0[0x20];
5617 
5618 	u8         duplicate_request[0x20];
5619 
5620 	u8         reserved_at_220[0x20];
5621 
5622 	u8         rnr_nak_retry_err[0x20];
5623 
5624 	u8         reserved_at_260[0x20];
5625 
5626 	u8         packet_seq_err[0x20];
5627 
5628 	u8         reserved_at_2a0[0x20];
5629 
5630 	u8         implied_nak_seq_err[0x20];
5631 
5632 	u8         reserved_at_2e0[0x20];
5633 
5634 	u8         local_ack_timeout_err[0x20];
5635 
5636 	u8         reserved_at_320[0xa0];
5637 
5638 	u8         resp_local_length_error[0x20];
5639 
5640 	u8         req_local_length_error[0x20];
5641 
5642 	u8         resp_local_qp_error[0x20];
5643 
5644 	u8         local_operation_error[0x20];
5645 
5646 	u8         resp_local_protection[0x20];
5647 
5648 	u8         req_local_protection[0x20];
5649 
5650 	u8         resp_cqe_error[0x20];
5651 
5652 	u8         req_cqe_error[0x20];
5653 
5654 	u8         req_mw_binding[0x20];
5655 
5656 	u8         req_bad_response[0x20];
5657 
5658 	u8         req_remote_invalid_request[0x20];
5659 
5660 	u8         resp_remote_invalid_request[0x20];
5661 
5662 	u8         req_remote_access_errors[0x20];
5663 
5664 	u8	   resp_remote_access_errors[0x20];
5665 
5666 	u8         req_remote_operation_errors[0x20];
5667 
5668 	u8         req_transport_retries_exceeded[0x20];
5669 
5670 	u8         cq_overflow[0x20];
5671 
5672 	u8         resp_cqe_flush_error[0x20];
5673 
5674 	u8         req_cqe_flush_error[0x20];
5675 
5676 	u8         reserved_at_620[0x20];
5677 
5678 	u8         roce_adp_retrans[0x20];
5679 
5680 	u8         roce_adp_retrans_to[0x20];
5681 
5682 	u8         roce_slow_restart[0x20];
5683 
5684 	u8         roce_slow_restart_cnps[0x20];
5685 
5686 	u8         roce_slow_restart_trans[0x20];
5687 
5688 	u8         reserved_at_6e0[0x120];
5689 };
5690 
5691 struct mlx5_ifc_query_q_counter_in_bits {
5692 	u8         opcode[0x10];
5693 	u8         reserved_at_10[0x10];
5694 
5695 	u8         reserved_at_20[0x10];
5696 	u8         op_mod[0x10];
5697 
5698 	u8         other_vport[0x1];
5699 	u8         reserved_at_41[0xf];
5700 	u8         vport_number[0x10];
5701 
5702 	u8         reserved_at_60[0x60];
5703 
5704 	u8         clear[0x1];
5705 	u8         aggregate[0x1];
5706 	u8         reserved_at_c2[0x1e];
5707 
5708 	u8         reserved_at_e0[0x18];
5709 	u8         counter_set_id[0x8];
5710 };
5711 
5712 struct mlx5_ifc_query_pages_out_bits {
5713 	u8         status[0x8];
5714 	u8         reserved_at_8[0x18];
5715 
5716 	u8         syndrome[0x20];
5717 
5718 	u8         embedded_cpu_function[0x1];
5719 	u8         reserved_at_41[0xf];
5720 	u8         function_id[0x10];
5721 
5722 	u8         num_pages[0x20];
5723 };
5724 
5725 enum {
5726 	MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES     = 0x1,
5727 	MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES     = 0x2,
5728 	MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES  = 0x3,
5729 };
5730 
5731 struct mlx5_ifc_query_pages_in_bits {
5732 	u8         opcode[0x10];
5733 	u8         reserved_at_10[0x10];
5734 
5735 	u8         reserved_at_20[0x10];
5736 	u8         op_mod[0x10];
5737 
5738 	u8         embedded_cpu_function[0x1];
5739 	u8         reserved_at_41[0xf];
5740 	u8         function_id[0x10];
5741 
5742 	u8         reserved_at_60[0x20];
5743 };
5744 
5745 struct mlx5_ifc_query_nic_vport_context_out_bits {
5746 	u8         status[0x8];
5747 	u8         reserved_at_8[0x18];
5748 
5749 	u8         syndrome[0x20];
5750 
5751 	u8         reserved_at_40[0x40];
5752 
5753 	struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
5754 };
5755 
5756 struct mlx5_ifc_query_nic_vport_context_in_bits {
5757 	u8         opcode[0x10];
5758 	u8         reserved_at_10[0x10];
5759 
5760 	u8         reserved_at_20[0x10];
5761 	u8         op_mod[0x10];
5762 
5763 	u8         other_vport[0x1];
5764 	u8         reserved_at_41[0xf];
5765 	u8         vport_number[0x10];
5766 
5767 	u8         reserved_at_60[0x5];
5768 	u8         allowed_list_type[0x3];
5769 	u8         reserved_at_68[0x18];
5770 };
5771 
5772 struct mlx5_ifc_query_mkey_out_bits {
5773 	u8         status[0x8];
5774 	u8         reserved_at_8[0x18];
5775 
5776 	u8         syndrome[0x20];
5777 
5778 	u8         reserved_at_40[0x40];
5779 
5780 	struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
5781 
5782 	u8         reserved_at_280[0x600];
5783 
5784 	u8         bsf0_klm0_pas_mtt0_1[16][0x8];
5785 
5786 	u8         bsf1_klm1_pas_mtt2_3[16][0x8];
5787 };
5788 
5789 struct mlx5_ifc_query_mkey_in_bits {
5790 	u8         opcode[0x10];
5791 	u8         reserved_at_10[0x10];
5792 
5793 	u8         reserved_at_20[0x10];
5794 	u8         op_mod[0x10];
5795 
5796 	u8         reserved_at_40[0x8];
5797 	u8         mkey_index[0x18];
5798 
5799 	u8         pg_access[0x1];
5800 	u8         reserved_at_61[0x1f];
5801 };
5802 
5803 struct mlx5_ifc_query_mad_demux_out_bits {
5804 	u8         status[0x8];
5805 	u8         reserved_at_8[0x18];
5806 
5807 	u8         syndrome[0x20];
5808 
5809 	u8         reserved_at_40[0x40];
5810 
5811 	u8         mad_dumux_parameters_block[0x20];
5812 };
5813 
5814 struct mlx5_ifc_query_mad_demux_in_bits {
5815 	u8         opcode[0x10];
5816 	u8         reserved_at_10[0x10];
5817 
5818 	u8         reserved_at_20[0x10];
5819 	u8         op_mod[0x10];
5820 
5821 	u8         reserved_at_40[0x40];
5822 };
5823 
5824 struct mlx5_ifc_query_l2_table_entry_out_bits {
5825 	u8         status[0x8];
5826 	u8         reserved_at_8[0x18];
5827 
5828 	u8         syndrome[0x20];
5829 
5830 	u8         reserved_at_40[0xa0];
5831 
5832 	u8         reserved_at_e0[0x13];
5833 	u8         vlan_valid[0x1];
5834 	u8         vlan[0xc];
5835 
5836 	struct mlx5_ifc_mac_address_layout_bits mac_address;
5837 
5838 	u8         reserved_at_140[0xc0];
5839 };
5840 
5841 struct mlx5_ifc_query_l2_table_entry_in_bits {
5842 	u8         opcode[0x10];
5843 	u8         reserved_at_10[0x10];
5844 
5845 	u8         reserved_at_20[0x10];
5846 	u8         op_mod[0x10];
5847 
5848 	u8         reserved_at_40[0x60];
5849 
5850 	u8         reserved_at_a0[0x8];
5851 	u8         table_index[0x18];
5852 
5853 	u8         reserved_at_c0[0x140];
5854 };
5855 
5856 struct mlx5_ifc_query_issi_out_bits {
5857 	u8         status[0x8];
5858 	u8         reserved_at_8[0x18];
5859 
5860 	u8         syndrome[0x20];
5861 
5862 	u8         reserved_at_40[0x10];
5863 	u8         current_issi[0x10];
5864 
5865 	u8         reserved_at_60[0xa0];
5866 
5867 	u8         reserved_at_100[76][0x8];
5868 	u8         supported_issi_dw0[0x20];
5869 };
5870 
5871 struct mlx5_ifc_query_issi_in_bits {
5872 	u8         opcode[0x10];
5873 	u8         reserved_at_10[0x10];
5874 
5875 	u8         reserved_at_20[0x10];
5876 	u8         op_mod[0x10];
5877 
5878 	u8         reserved_at_40[0x40];
5879 };
5880 
5881 struct mlx5_ifc_set_driver_version_out_bits {
5882 	u8         status[0x8];
5883 	u8         reserved_0[0x18];
5884 
5885 	u8         syndrome[0x20];
5886 	u8         reserved_1[0x40];
5887 };
5888 
5889 struct mlx5_ifc_set_driver_version_in_bits {
5890 	u8         opcode[0x10];
5891 	u8         reserved_0[0x10];
5892 
5893 	u8         reserved_1[0x10];
5894 	u8         op_mod[0x10];
5895 
5896 	u8         reserved_2[0x40];
5897 	u8         driver_version[64][0x8];
5898 };
5899 
5900 struct mlx5_ifc_query_hca_vport_pkey_out_bits {
5901 	u8         status[0x8];
5902 	u8         reserved_at_8[0x18];
5903 
5904 	u8         syndrome[0x20];
5905 
5906 	u8         reserved_at_40[0x40];
5907 
5908 	struct mlx5_ifc_pkey_bits pkey[];
5909 };
5910 
5911 struct mlx5_ifc_query_hca_vport_pkey_in_bits {
5912 	u8         opcode[0x10];
5913 	u8         reserved_at_10[0x10];
5914 
5915 	u8         reserved_at_20[0x10];
5916 	u8         op_mod[0x10];
5917 
5918 	u8         other_vport[0x1];
5919 	u8         reserved_at_41[0xb];
5920 	u8         port_num[0x4];
5921 	u8         vport_number[0x10];
5922 
5923 	u8         reserved_at_60[0x10];
5924 	u8         pkey_index[0x10];
5925 };
5926 
5927 enum {
5928 	MLX5_HCA_VPORT_SEL_PORT_GUID	= 1 << 0,
5929 	MLX5_HCA_VPORT_SEL_NODE_GUID	= 1 << 1,
5930 	MLX5_HCA_VPORT_SEL_STATE_POLICY	= 1 << 2,
5931 };
5932 
5933 struct mlx5_ifc_query_hca_vport_gid_out_bits {
5934 	u8         status[0x8];
5935 	u8         reserved_at_8[0x18];
5936 
5937 	u8         syndrome[0x20];
5938 
5939 	u8         reserved_at_40[0x20];
5940 
5941 	u8         gids_num[0x10];
5942 	u8         reserved_at_70[0x10];
5943 
5944 	struct mlx5_ifc_array128_auto_bits gid[];
5945 };
5946 
5947 struct mlx5_ifc_query_hca_vport_gid_in_bits {
5948 	u8         opcode[0x10];
5949 	u8         reserved_at_10[0x10];
5950 
5951 	u8         reserved_at_20[0x10];
5952 	u8         op_mod[0x10];
5953 
5954 	u8         other_vport[0x1];
5955 	u8         reserved_at_41[0xb];
5956 	u8         port_num[0x4];
5957 	u8         vport_number[0x10];
5958 
5959 	u8         reserved_at_60[0x10];
5960 	u8         gid_index[0x10];
5961 };
5962 
5963 struct mlx5_ifc_query_hca_vport_context_out_bits {
5964 	u8         status[0x8];
5965 	u8         reserved_at_8[0x18];
5966 
5967 	u8         syndrome[0x20];
5968 
5969 	u8         reserved_at_40[0x40];
5970 
5971 	struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
5972 };
5973 
5974 struct mlx5_ifc_query_hca_vport_context_in_bits {
5975 	u8         opcode[0x10];
5976 	u8         reserved_at_10[0x10];
5977 
5978 	u8         reserved_at_20[0x10];
5979 	u8         op_mod[0x10];
5980 
5981 	u8         other_vport[0x1];
5982 	u8         reserved_at_41[0xb];
5983 	u8         port_num[0x4];
5984 	u8         vport_number[0x10];
5985 
5986 	u8         reserved_at_60[0x20];
5987 };
5988 
5989 struct mlx5_ifc_query_hca_cap_out_bits {
5990 	u8         status[0x8];
5991 	u8         reserved_at_8[0x18];
5992 
5993 	u8         syndrome[0x20];
5994 
5995 	u8         reserved_at_40[0x40];
5996 
5997 	union mlx5_ifc_hca_cap_union_bits capability;
5998 };
5999 
6000 struct mlx5_ifc_query_hca_cap_in_bits {
6001 	u8         opcode[0x10];
6002 	u8         reserved_at_10[0x10];
6003 
6004 	u8         reserved_at_20[0x10];
6005 	u8         op_mod[0x10];
6006 
6007 	u8         other_function[0x1];
6008 	u8         ec_vf_function[0x1];
6009 	u8         reserved_at_42[0xe];
6010 	u8         function_id[0x10];
6011 
6012 	u8         reserved_at_60[0x20];
6013 };
6014 
6015 struct mlx5_ifc_other_hca_cap_bits {
6016 	u8         roce[0x1];
6017 	u8         reserved_at_1[0x27f];
6018 };
6019 
6020 struct mlx5_ifc_query_other_hca_cap_out_bits {
6021 	u8         status[0x8];
6022 	u8         reserved_at_8[0x18];
6023 
6024 	u8         syndrome[0x20];
6025 
6026 	u8         reserved_at_40[0x40];
6027 
6028 	struct     mlx5_ifc_other_hca_cap_bits other_capability;
6029 };
6030 
6031 struct mlx5_ifc_query_other_hca_cap_in_bits {
6032 	u8         opcode[0x10];
6033 	u8         reserved_at_10[0x10];
6034 
6035 	u8         reserved_at_20[0x10];
6036 	u8         op_mod[0x10];
6037 
6038 	u8         reserved_at_40[0x10];
6039 	u8         function_id[0x10];
6040 
6041 	u8         reserved_at_60[0x20];
6042 };
6043 
6044 struct mlx5_ifc_modify_other_hca_cap_out_bits {
6045 	u8         status[0x8];
6046 	u8         reserved_at_8[0x18];
6047 
6048 	u8         syndrome[0x20];
6049 
6050 	u8         reserved_at_40[0x40];
6051 };
6052 
6053 struct mlx5_ifc_modify_other_hca_cap_in_bits {
6054 	u8         opcode[0x10];
6055 	u8         reserved_at_10[0x10];
6056 
6057 	u8         reserved_at_20[0x10];
6058 	u8         op_mod[0x10];
6059 
6060 	u8         reserved_at_40[0x10];
6061 	u8         function_id[0x10];
6062 	u8         field_select[0x20];
6063 
6064 	struct     mlx5_ifc_other_hca_cap_bits other_capability;
6065 };
6066 
6067 struct mlx5_ifc_flow_table_context_bits {
6068 	u8         reformat_en[0x1];
6069 	u8         decap_en[0x1];
6070 	u8         sw_owner[0x1];
6071 	u8         termination_table[0x1];
6072 	u8         table_miss_action[0x4];
6073 	u8         level[0x8];
6074 	u8         reserved_at_10[0x8];
6075 	u8         log_size[0x8];
6076 
6077 	u8         reserved_at_20[0x8];
6078 	u8         table_miss_id[0x18];
6079 
6080 	u8         reserved_at_40[0x8];
6081 	u8         lag_master_next_table_id[0x18];
6082 
6083 	u8         reserved_at_60[0x60];
6084 
6085 	u8         sw_owner_icm_root_1[0x40];
6086 
6087 	u8         sw_owner_icm_root_0[0x40];
6088 
6089 };
6090 
6091 struct mlx5_ifc_query_flow_table_out_bits {
6092 	u8         status[0x8];
6093 	u8         reserved_at_8[0x18];
6094 
6095 	u8         syndrome[0x20];
6096 
6097 	u8         reserved_at_40[0x80];
6098 
6099 	struct mlx5_ifc_flow_table_context_bits flow_table_context;
6100 };
6101 
6102 struct mlx5_ifc_query_flow_table_in_bits {
6103 	u8         opcode[0x10];
6104 	u8         reserved_at_10[0x10];
6105 
6106 	u8         reserved_at_20[0x10];
6107 	u8         op_mod[0x10];
6108 
6109 	u8         reserved_at_40[0x40];
6110 
6111 	u8         table_type[0x8];
6112 	u8         reserved_at_88[0x18];
6113 
6114 	u8         reserved_at_a0[0x8];
6115 	u8         table_id[0x18];
6116 
6117 	u8         reserved_at_c0[0x140];
6118 };
6119 
6120 struct mlx5_ifc_query_fte_out_bits {
6121 	u8         status[0x8];
6122 	u8         reserved_at_8[0x18];
6123 
6124 	u8         syndrome[0x20];
6125 
6126 	u8         reserved_at_40[0x1c0];
6127 
6128 	struct mlx5_ifc_flow_context_bits flow_context;
6129 };
6130 
6131 struct mlx5_ifc_query_fte_in_bits {
6132 	u8         opcode[0x10];
6133 	u8         reserved_at_10[0x10];
6134 
6135 	u8         reserved_at_20[0x10];
6136 	u8         op_mod[0x10];
6137 
6138 	u8         reserved_at_40[0x40];
6139 
6140 	u8         table_type[0x8];
6141 	u8         reserved_at_88[0x18];
6142 
6143 	u8         reserved_at_a0[0x8];
6144 	u8         table_id[0x18];
6145 
6146 	u8         reserved_at_c0[0x40];
6147 
6148 	u8         flow_index[0x20];
6149 
6150 	u8         reserved_at_120[0xe0];
6151 };
6152 
6153 struct mlx5_ifc_match_definer_format_0_bits {
6154 	u8         reserved_at_0[0x100];
6155 
6156 	u8         metadata_reg_c_0[0x20];
6157 
6158 	u8         metadata_reg_c_1[0x20];
6159 
6160 	u8         outer_dmac_47_16[0x20];
6161 
6162 	u8         outer_dmac_15_0[0x10];
6163 	u8         outer_ethertype[0x10];
6164 
6165 	u8         reserved_at_180[0x1];
6166 	u8         sx_sniffer[0x1];
6167 	u8         functional_lb[0x1];
6168 	u8         outer_ip_frag[0x1];
6169 	u8         outer_qp_type[0x2];
6170 	u8         outer_encap_type[0x2];
6171 	u8         port_number[0x2];
6172 	u8         outer_l3_type[0x2];
6173 	u8         outer_l4_type[0x2];
6174 	u8         outer_first_vlan_type[0x2];
6175 	u8         outer_first_vlan_prio[0x3];
6176 	u8         outer_first_vlan_cfi[0x1];
6177 	u8         outer_first_vlan_vid[0xc];
6178 
6179 	u8         outer_l4_type_ext[0x4];
6180 	u8         reserved_at_1a4[0x2];
6181 	u8         outer_ipsec_layer[0x2];
6182 	u8         outer_l2_type[0x2];
6183 	u8         force_lb[0x1];
6184 	u8         outer_l2_ok[0x1];
6185 	u8         outer_l3_ok[0x1];
6186 	u8         outer_l4_ok[0x1];
6187 	u8         outer_second_vlan_type[0x2];
6188 	u8         outer_second_vlan_prio[0x3];
6189 	u8         outer_second_vlan_cfi[0x1];
6190 	u8         outer_second_vlan_vid[0xc];
6191 
6192 	u8         outer_smac_47_16[0x20];
6193 
6194 	u8         outer_smac_15_0[0x10];
6195 	u8         inner_ipv4_checksum_ok[0x1];
6196 	u8         inner_l4_checksum_ok[0x1];
6197 	u8         outer_ipv4_checksum_ok[0x1];
6198 	u8         outer_l4_checksum_ok[0x1];
6199 	u8         inner_l3_ok[0x1];
6200 	u8         inner_l4_ok[0x1];
6201 	u8         outer_l3_ok_duplicate[0x1];
6202 	u8         outer_l4_ok_duplicate[0x1];
6203 	u8         outer_tcp_cwr[0x1];
6204 	u8         outer_tcp_ece[0x1];
6205 	u8         outer_tcp_urg[0x1];
6206 	u8         outer_tcp_ack[0x1];
6207 	u8         outer_tcp_psh[0x1];
6208 	u8         outer_tcp_rst[0x1];
6209 	u8         outer_tcp_syn[0x1];
6210 	u8         outer_tcp_fin[0x1];
6211 };
6212 
6213 struct mlx5_ifc_match_definer_format_22_bits {
6214 	u8         reserved_at_0[0x100];
6215 
6216 	u8         outer_ip_src_addr[0x20];
6217 
6218 	u8         outer_ip_dest_addr[0x20];
6219 
6220 	u8         outer_l4_sport[0x10];
6221 	u8         outer_l4_dport[0x10];
6222 
6223 	u8         reserved_at_160[0x1];
6224 	u8         sx_sniffer[0x1];
6225 	u8         functional_lb[0x1];
6226 	u8         outer_ip_frag[0x1];
6227 	u8         outer_qp_type[0x2];
6228 	u8         outer_encap_type[0x2];
6229 	u8         port_number[0x2];
6230 	u8         outer_l3_type[0x2];
6231 	u8         outer_l4_type[0x2];
6232 	u8         outer_first_vlan_type[0x2];
6233 	u8         outer_first_vlan_prio[0x3];
6234 	u8         outer_first_vlan_cfi[0x1];
6235 	u8         outer_first_vlan_vid[0xc];
6236 
6237 	u8         metadata_reg_c_0[0x20];
6238 
6239 	u8         outer_dmac_47_16[0x20];
6240 
6241 	u8         outer_smac_47_16[0x20];
6242 
6243 	u8         outer_smac_15_0[0x10];
6244 	u8         outer_dmac_15_0[0x10];
6245 };
6246 
6247 struct mlx5_ifc_match_definer_format_23_bits {
6248 	u8         reserved_at_0[0x100];
6249 
6250 	u8         inner_ip_src_addr[0x20];
6251 
6252 	u8         inner_ip_dest_addr[0x20];
6253 
6254 	u8         inner_l4_sport[0x10];
6255 	u8         inner_l4_dport[0x10];
6256 
6257 	u8         reserved_at_160[0x1];
6258 	u8         sx_sniffer[0x1];
6259 	u8         functional_lb[0x1];
6260 	u8         inner_ip_frag[0x1];
6261 	u8         inner_qp_type[0x2];
6262 	u8         inner_encap_type[0x2];
6263 	u8         port_number[0x2];
6264 	u8         inner_l3_type[0x2];
6265 	u8         inner_l4_type[0x2];
6266 	u8         inner_first_vlan_type[0x2];
6267 	u8         inner_first_vlan_prio[0x3];
6268 	u8         inner_first_vlan_cfi[0x1];
6269 	u8         inner_first_vlan_vid[0xc];
6270 
6271 	u8         tunnel_header_0[0x20];
6272 
6273 	u8         inner_dmac_47_16[0x20];
6274 
6275 	u8         inner_smac_47_16[0x20];
6276 
6277 	u8         inner_smac_15_0[0x10];
6278 	u8         inner_dmac_15_0[0x10];
6279 };
6280 
6281 struct mlx5_ifc_match_definer_format_29_bits {
6282 	u8         reserved_at_0[0xc0];
6283 
6284 	u8         outer_ip_dest_addr[0x80];
6285 
6286 	u8         outer_ip_src_addr[0x80];
6287 
6288 	u8         outer_l4_sport[0x10];
6289 	u8         outer_l4_dport[0x10];
6290 
6291 	u8         reserved_at_1e0[0x20];
6292 };
6293 
6294 struct mlx5_ifc_match_definer_format_30_bits {
6295 	u8         reserved_at_0[0xa0];
6296 
6297 	u8         outer_ip_dest_addr[0x80];
6298 
6299 	u8         outer_ip_src_addr[0x80];
6300 
6301 	u8         outer_dmac_47_16[0x20];
6302 
6303 	u8         outer_smac_47_16[0x20];
6304 
6305 	u8         outer_smac_15_0[0x10];
6306 	u8         outer_dmac_15_0[0x10];
6307 };
6308 
6309 struct mlx5_ifc_match_definer_format_31_bits {
6310 	u8         reserved_at_0[0xc0];
6311 
6312 	u8         inner_ip_dest_addr[0x80];
6313 
6314 	u8         inner_ip_src_addr[0x80];
6315 
6316 	u8         inner_l4_sport[0x10];
6317 	u8         inner_l4_dport[0x10];
6318 
6319 	u8         reserved_at_1e0[0x20];
6320 };
6321 
6322 struct mlx5_ifc_match_definer_format_32_bits {
6323 	u8         reserved_at_0[0xa0];
6324 
6325 	u8         inner_ip_dest_addr[0x80];
6326 
6327 	u8         inner_ip_src_addr[0x80];
6328 
6329 	u8         inner_dmac_47_16[0x20];
6330 
6331 	u8         inner_smac_47_16[0x20];
6332 
6333 	u8         inner_smac_15_0[0x10];
6334 	u8         inner_dmac_15_0[0x10];
6335 };
6336 
6337 enum {
6338 	MLX5_IFC_DEFINER_FORMAT_ID_SELECT = 61,
6339 };
6340 
6341 #define MLX5_IFC_DEFINER_FORMAT_OFFSET_UNUSED 0x0
6342 #define MLX5_IFC_DEFINER_FORMAT_OFFSET_OUTER_ETH_PKT_LEN 0x48
6343 #define MLX5_IFC_DEFINER_DW_SELECTORS_NUM 9
6344 #define MLX5_IFC_DEFINER_BYTE_SELECTORS_NUM 8
6345 
6346 struct mlx5_ifc_match_definer_match_mask_bits {
6347 	u8         reserved_at_1c0[5][0x20];
6348 	u8         match_dw_8[0x20];
6349 	u8         match_dw_7[0x20];
6350 	u8         match_dw_6[0x20];
6351 	u8         match_dw_5[0x20];
6352 	u8         match_dw_4[0x20];
6353 	u8         match_dw_3[0x20];
6354 	u8         match_dw_2[0x20];
6355 	u8         match_dw_1[0x20];
6356 	u8         match_dw_0[0x20];
6357 
6358 	u8         match_byte_7[0x8];
6359 	u8         match_byte_6[0x8];
6360 	u8         match_byte_5[0x8];
6361 	u8         match_byte_4[0x8];
6362 
6363 	u8         match_byte_3[0x8];
6364 	u8         match_byte_2[0x8];
6365 	u8         match_byte_1[0x8];
6366 	u8         match_byte_0[0x8];
6367 };
6368 
6369 struct mlx5_ifc_match_definer_bits {
6370 	u8         modify_field_select[0x40];
6371 
6372 	u8         reserved_at_40[0x40];
6373 
6374 	u8         reserved_at_80[0x10];
6375 	u8         format_id[0x10];
6376 
6377 	u8         reserved_at_a0[0x60];
6378 
6379 	u8         format_select_dw3[0x8];
6380 	u8         format_select_dw2[0x8];
6381 	u8         format_select_dw1[0x8];
6382 	u8         format_select_dw0[0x8];
6383 
6384 	u8         format_select_dw7[0x8];
6385 	u8         format_select_dw6[0x8];
6386 	u8         format_select_dw5[0x8];
6387 	u8         format_select_dw4[0x8];
6388 
6389 	u8         reserved_at_100[0x18];
6390 	u8         format_select_dw8[0x8];
6391 
6392 	u8         reserved_at_120[0x20];
6393 
6394 	u8         format_select_byte3[0x8];
6395 	u8         format_select_byte2[0x8];
6396 	u8         format_select_byte1[0x8];
6397 	u8         format_select_byte0[0x8];
6398 
6399 	u8         format_select_byte7[0x8];
6400 	u8         format_select_byte6[0x8];
6401 	u8         format_select_byte5[0x8];
6402 	u8         format_select_byte4[0x8];
6403 
6404 	u8         reserved_at_180[0x40];
6405 
6406 	union {
6407 		struct {
6408 			u8         match_mask[16][0x20];
6409 		};
6410 		struct mlx5_ifc_match_definer_match_mask_bits match_mask_format;
6411 	};
6412 };
6413 
6414 struct mlx5_ifc_general_obj_create_param_bits {
6415 	u8         alias_object[0x1];
6416 	u8         reserved_at_1[0x2];
6417 	u8         log_obj_range[0x5];
6418 	u8         reserved_at_8[0x18];
6419 };
6420 
6421 struct mlx5_ifc_general_obj_query_param_bits {
6422 	u8         alias_object[0x1];
6423 	u8         obj_offset[0x1f];
6424 };
6425 
6426 struct mlx5_ifc_general_obj_in_cmd_hdr_bits {
6427 	u8         opcode[0x10];
6428 	u8         uid[0x10];
6429 
6430 	u8         vhca_tunnel_id[0x10];
6431 	u8         obj_type[0x10];
6432 
6433 	u8         obj_id[0x20];
6434 
6435 	union {
6436 		struct mlx5_ifc_general_obj_create_param_bits create;
6437 		struct mlx5_ifc_general_obj_query_param_bits query;
6438 	} op_param;
6439 };
6440 
6441 struct mlx5_ifc_general_obj_out_cmd_hdr_bits {
6442 	u8         status[0x8];
6443 	u8         reserved_at_8[0x18];
6444 
6445 	u8         syndrome[0x20];
6446 
6447 	u8         obj_id[0x20];
6448 
6449 	u8         reserved_at_60[0x20];
6450 };
6451 
6452 struct mlx5_ifc_allow_other_vhca_access_in_bits {
6453 	u8 opcode[0x10];
6454 	u8 uid[0x10];
6455 	u8 reserved_at_20[0x10];
6456 	u8 op_mod[0x10];
6457 	u8 reserved_at_40[0x50];
6458 	u8 object_type_to_be_accessed[0x10];
6459 	u8 object_id_to_be_accessed[0x20];
6460 	u8 reserved_at_c0[0x40];
6461 	union {
6462 		u8 access_key_raw[0x100];
6463 		u8 access_key[8][0x20];
6464 	};
6465 };
6466 
6467 struct mlx5_ifc_allow_other_vhca_access_out_bits {
6468 	u8 status[0x8];
6469 	u8 reserved_at_8[0x18];
6470 	u8 syndrome[0x20];
6471 	u8 reserved_at_40[0x40];
6472 };
6473 
6474 struct mlx5_ifc_modify_header_arg_bits {
6475 	u8         reserved_at_0[0x80];
6476 
6477 	u8         reserved_at_80[0x8];
6478 	u8         access_pd[0x18];
6479 };
6480 
6481 struct mlx5_ifc_create_modify_header_arg_in_bits {
6482 	struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
6483 	struct mlx5_ifc_modify_header_arg_bits arg;
6484 };
6485 
6486 struct mlx5_ifc_create_match_definer_in_bits {
6487 	struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
6488 
6489 	struct mlx5_ifc_match_definer_bits obj_context;
6490 };
6491 
6492 struct mlx5_ifc_create_match_definer_out_bits {
6493 	struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr;
6494 };
6495 
6496 struct mlx5_ifc_alias_context_bits {
6497 	u8 vhca_id_to_be_accessed[0x10];
6498 	u8 reserved_at_10[0xd];
6499 	u8 status[0x3];
6500 	u8 object_id_to_be_accessed[0x20];
6501 	u8 reserved_at_40[0x40];
6502 	union {
6503 		u8 access_key_raw[0x100];
6504 		u8 access_key[8][0x20];
6505 	};
6506 	u8 metadata[0x80];
6507 };
6508 
6509 struct mlx5_ifc_create_alias_obj_in_bits {
6510 	struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
6511 	struct mlx5_ifc_alias_context_bits alias_ctx;
6512 };
6513 
6514 enum {
6515 	MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS    = 0x0,
6516 	MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS  = 0x1,
6517 	MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS    = 0x2,
6518 	MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3,
6519 	MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_3 = 0x4,
6520 	MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_4 = 0x5,
6521 	MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_5 = 0x6,
6522 };
6523 
6524 struct mlx5_ifc_query_flow_group_out_bits {
6525 	u8         status[0x8];
6526 	u8         reserved_at_8[0x18];
6527 
6528 	u8         syndrome[0x20];
6529 
6530 	u8         reserved_at_40[0xa0];
6531 
6532 	u8         start_flow_index[0x20];
6533 
6534 	u8         reserved_at_100[0x20];
6535 
6536 	u8         end_flow_index[0x20];
6537 
6538 	u8         reserved_at_140[0xa0];
6539 
6540 	u8         reserved_at_1e0[0x18];
6541 	u8         match_criteria_enable[0x8];
6542 
6543 	struct mlx5_ifc_fte_match_param_bits match_criteria;
6544 
6545 	u8         reserved_at_1200[0xe00];
6546 };
6547 
6548 struct mlx5_ifc_query_flow_group_in_bits {
6549 	u8         opcode[0x10];
6550 	u8         reserved_at_10[0x10];
6551 
6552 	u8         reserved_at_20[0x10];
6553 	u8         op_mod[0x10];
6554 
6555 	u8         reserved_at_40[0x40];
6556 
6557 	u8         table_type[0x8];
6558 	u8         reserved_at_88[0x18];
6559 
6560 	u8         reserved_at_a0[0x8];
6561 	u8         table_id[0x18];
6562 
6563 	u8         group_id[0x20];
6564 
6565 	u8         reserved_at_e0[0x120];
6566 };
6567 
6568 struct mlx5_ifc_query_flow_counter_out_bits {
6569 	u8         status[0x8];
6570 	u8         reserved_at_8[0x18];
6571 
6572 	u8         syndrome[0x20];
6573 
6574 	u8         reserved_at_40[0x40];
6575 
6576 	struct mlx5_ifc_traffic_counter_bits flow_statistics[];
6577 };
6578 
6579 struct mlx5_ifc_query_flow_counter_in_bits {
6580 	u8         opcode[0x10];
6581 	u8         reserved_at_10[0x10];
6582 
6583 	u8         reserved_at_20[0x10];
6584 	u8         op_mod[0x10];
6585 
6586 	u8         reserved_at_40[0x80];
6587 
6588 	u8         clear[0x1];
6589 	u8         reserved_at_c1[0xf];
6590 	u8         num_of_counters[0x10];
6591 
6592 	u8         flow_counter_id[0x20];
6593 };
6594 
6595 struct mlx5_ifc_query_esw_vport_context_out_bits {
6596 	u8         status[0x8];
6597 	u8         reserved_at_8[0x18];
6598 
6599 	u8         syndrome[0x20];
6600 
6601 	u8         reserved_at_40[0x40];
6602 
6603 	struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
6604 };
6605 
6606 struct mlx5_ifc_query_esw_vport_context_in_bits {
6607 	u8         opcode[0x10];
6608 	u8         reserved_at_10[0x10];
6609 
6610 	u8         reserved_at_20[0x10];
6611 	u8         op_mod[0x10];
6612 
6613 	u8         other_vport[0x1];
6614 	u8         reserved_at_41[0xf];
6615 	u8         vport_number[0x10];
6616 
6617 	u8         reserved_at_60[0x20];
6618 };
6619 
6620 struct mlx5_ifc_modify_esw_vport_context_out_bits {
6621 	u8         status[0x8];
6622 	u8         reserved_at_8[0x18];
6623 
6624 	u8         syndrome[0x20];
6625 
6626 	u8         reserved_at_40[0x40];
6627 };
6628 
6629 struct mlx5_ifc_esw_vport_context_fields_select_bits {
6630 	u8         reserved_at_0[0x1b];
6631 	u8         fdb_to_vport_reg_c_id[0x1];
6632 	u8         vport_cvlan_insert[0x1];
6633 	u8         vport_svlan_insert[0x1];
6634 	u8         vport_cvlan_strip[0x1];
6635 	u8         vport_svlan_strip[0x1];
6636 };
6637 
6638 struct mlx5_ifc_modify_esw_vport_context_in_bits {
6639 	u8         opcode[0x10];
6640 	u8         reserved_at_10[0x10];
6641 
6642 	u8         reserved_at_20[0x10];
6643 	u8         op_mod[0x10];
6644 
6645 	u8         other_vport[0x1];
6646 	u8         reserved_at_41[0xf];
6647 	u8         vport_number[0x10];
6648 
6649 	struct mlx5_ifc_esw_vport_context_fields_select_bits field_select;
6650 
6651 	struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
6652 };
6653 
6654 struct mlx5_ifc_query_eq_out_bits {
6655 	u8         status[0x8];
6656 	u8         reserved_at_8[0x18];
6657 
6658 	u8         syndrome[0x20];
6659 
6660 	u8         reserved_at_40[0x40];
6661 
6662 	struct mlx5_ifc_eqc_bits eq_context_entry;
6663 
6664 	u8         reserved_at_280[0x40];
6665 
6666 	u8         event_bitmask[0x40];
6667 
6668 	u8         reserved_at_300[0x580];
6669 
6670 	u8         pas[][0x40];
6671 };
6672 
6673 struct mlx5_ifc_query_eq_in_bits {
6674 	u8         opcode[0x10];
6675 	u8         reserved_at_10[0x10];
6676 
6677 	u8         reserved_at_20[0x10];
6678 	u8         op_mod[0x10];
6679 
6680 	u8         reserved_at_40[0x18];
6681 	u8         eq_number[0x8];
6682 
6683 	u8         reserved_at_60[0x20];
6684 };
6685 
6686 struct mlx5_ifc_packet_reformat_context_in_bits {
6687 	u8         reformat_type[0x8];
6688 	u8         reserved_at_8[0x4];
6689 	u8         reformat_param_0[0x4];
6690 	u8         reserved_at_10[0x6];
6691 	u8         reformat_data_size[0xa];
6692 
6693 	u8         reformat_param_1[0x8];
6694 	u8         reserved_at_28[0x8];
6695 	u8         reformat_data[2][0x8];
6696 
6697 	u8         more_reformat_data[][0x8];
6698 };
6699 
6700 struct mlx5_ifc_query_packet_reformat_context_out_bits {
6701 	u8         status[0x8];
6702 	u8         reserved_at_8[0x18];
6703 
6704 	u8         syndrome[0x20];
6705 
6706 	u8         reserved_at_40[0xa0];
6707 
6708 	struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context[];
6709 };
6710 
6711 struct mlx5_ifc_query_packet_reformat_context_in_bits {
6712 	u8         opcode[0x10];
6713 	u8         reserved_at_10[0x10];
6714 
6715 	u8         reserved_at_20[0x10];
6716 	u8         op_mod[0x10];
6717 
6718 	u8         packet_reformat_id[0x20];
6719 
6720 	u8         reserved_at_60[0xa0];
6721 };
6722 
6723 struct mlx5_ifc_alloc_packet_reformat_context_out_bits {
6724 	u8         status[0x8];
6725 	u8         reserved_at_8[0x18];
6726 
6727 	u8         syndrome[0x20];
6728 
6729 	u8         packet_reformat_id[0x20];
6730 
6731 	u8         reserved_at_60[0x20];
6732 };
6733 
6734 enum {
6735 	MLX5_REFORMAT_CONTEXT_ANCHOR_MAC_START = 0x1,
6736 	MLX5_REFORMAT_CONTEXT_ANCHOR_IP_START = 0x7,
6737 	MLX5_REFORMAT_CONTEXT_ANCHOR_TCP_UDP_START = 0x9,
6738 };
6739 
6740 enum mlx5_reformat_ctx_type {
6741 	MLX5_REFORMAT_TYPE_L2_TO_VXLAN = 0x0,
6742 	MLX5_REFORMAT_TYPE_L2_TO_NVGRE = 0x1,
6743 	MLX5_REFORMAT_TYPE_L2_TO_L2_TUNNEL = 0x2,
6744 	MLX5_REFORMAT_TYPE_L3_TUNNEL_TO_L2 = 0x3,
6745 	MLX5_REFORMAT_TYPE_L2_TO_L3_TUNNEL = 0x4,
6746 	MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_IPV4 = 0x5,
6747 	MLX5_REFORMAT_TYPE_L2_TO_L3_ESP_TUNNEL = 0x6,
6748 	MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_UDPV4 = 0x7,
6749 	MLX5_REFORMAT_TYPE_DEL_ESP_TRANSPORT = 0x8,
6750 	MLX5_REFORMAT_TYPE_L3_ESP_TUNNEL_TO_L2 = 0x9,
6751 	MLX5_REFORMAT_TYPE_DEL_ESP_TRANSPORT_OVER_UDP = 0xa,
6752 	MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_IPV6 = 0xb,
6753 	MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_UDPV6 = 0xc,
6754 	MLX5_REFORMAT_TYPE_INSERT_HDR = 0xf,
6755 	MLX5_REFORMAT_TYPE_REMOVE_HDR = 0x10,
6756 	MLX5_REFORMAT_TYPE_ADD_MACSEC = 0x11,
6757 	MLX5_REFORMAT_TYPE_DEL_MACSEC = 0x12,
6758 };
6759 
6760 struct mlx5_ifc_alloc_packet_reformat_context_in_bits {
6761 	u8         opcode[0x10];
6762 	u8         reserved_at_10[0x10];
6763 
6764 	u8         reserved_at_20[0x10];
6765 	u8         op_mod[0x10];
6766 
6767 	u8         reserved_at_40[0xa0];
6768 
6769 	struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context;
6770 };
6771 
6772 struct mlx5_ifc_dealloc_packet_reformat_context_out_bits {
6773 	u8         status[0x8];
6774 	u8         reserved_at_8[0x18];
6775 
6776 	u8         syndrome[0x20];
6777 
6778 	u8         reserved_at_40[0x40];
6779 };
6780 
6781 struct mlx5_ifc_dealloc_packet_reformat_context_in_bits {
6782 	u8         opcode[0x10];
6783 	u8         reserved_at_10[0x10];
6784 
6785 	u8         reserved_20[0x10];
6786 	u8         op_mod[0x10];
6787 
6788 	u8         packet_reformat_id[0x20];
6789 
6790 	u8         reserved_60[0x20];
6791 };
6792 
6793 struct mlx5_ifc_set_action_in_bits {
6794 	u8         action_type[0x4];
6795 	u8         field[0xc];
6796 	u8         reserved_at_10[0x3];
6797 	u8         offset[0x5];
6798 	u8         reserved_at_18[0x3];
6799 	u8         length[0x5];
6800 
6801 	u8         data[0x20];
6802 };
6803 
6804 struct mlx5_ifc_add_action_in_bits {
6805 	u8         action_type[0x4];
6806 	u8         field[0xc];
6807 	u8         reserved_at_10[0x10];
6808 
6809 	u8         data[0x20];
6810 };
6811 
6812 struct mlx5_ifc_copy_action_in_bits {
6813 	u8         action_type[0x4];
6814 	u8         src_field[0xc];
6815 	u8         reserved_at_10[0x3];
6816 	u8         src_offset[0x5];
6817 	u8         reserved_at_18[0x3];
6818 	u8         length[0x5];
6819 
6820 	u8         reserved_at_20[0x4];
6821 	u8         dst_field[0xc];
6822 	u8         reserved_at_30[0x3];
6823 	u8         dst_offset[0x5];
6824 	u8         reserved_at_38[0x8];
6825 };
6826 
6827 union mlx5_ifc_set_add_copy_action_in_auto_bits {
6828 	struct mlx5_ifc_set_action_in_bits  set_action_in;
6829 	struct mlx5_ifc_add_action_in_bits  add_action_in;
6830 	struct mlx5_ifc_copy_action_in_bits copy_action_in;
6831 	u8         reserved_at_0[0x40];
6832 };
6833 
6834 enum {
6835 	MLX5_ACTION_TYPE_SET   = 0x1,
6836 	MLX5_ACTION_TYPE_ADD   = 0x2,
6837 	MLX5_ACTION_TYPE_COPY  = 0x3,
6838 };
6839 
6840 enum {
6841 	MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16    = 0x1,
6842 	MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0     = 0x2,
6843 	MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE     = 0x3,
6844 	MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16    = 0x4,
6845 	MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0     = 0x5,
6846 	MLX5_ACTION_IN_FIELD_OUT_IP_DSCP       = 0x6,
6847 	MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS     = 0x7,
6848 	MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT     = 0x8,
6849 	MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT     = 0x9,
6850 	MLX5_ACTION_IN_FIELD_OUT_IP_TTL        = 0xa,
6851 	MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT     = 0xb,
6852 	MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT     = 0xc,
6853 	MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96  = 0xd,
6854 	MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64   = 0xe,
6855 	MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32   = 0xf,
6856 	MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0    = 0x10,
6857 	MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96  = 0x11,
6858 	MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64   = 0x12,
6859 	MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32   = 0x13,
6860 	MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0    = 0x14,
6861 	MLX5_ACTION_IN_FIELD_OUT_SIPV4         = 0x15,
6862 	MLX5_ACTION_IN_FIELD_OUT_DIPV4         = 0x16,
6863 	MLX5_ACTION_IN_FIELD_OUT_FIRST_VID     = 0x17,
6864 	MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47,
6865 	MLX5_ACTION_IN_FIELD_METADATA_REG_A    = 0x49,
6866 	MLX5_ACTION_IN_FIELD_METADATA_REG_B    = 0x50,
6867 	MLX5_ACTION_IN_FIELD_METADATA_REG_C_0  = 0x51,
6868 	MLX5_ACTION_IN_FIELD_METADATA_REG_C_1  = 0x52,
6869 	MLX5_ACTION_IN_FIELD_METADATA_REG_C_2  = 0x53,
6870 	MLX5_ACTION_IN_FIELD_METADATA_REG_C_3  = 0x54,
6871 	MLX5_ACTION_IN_FIELD_METADATA_REG_C_4  = 0x55,
6872 	MLX5_ACTION_IN_FIELD_METADATA_REG_C_5  = 0x56,
6873 	MLX5_ACTION_IN_FIELD_METADATA_REG_C_6  = 0x57,
6874 	MLX5_ACTION_IN_FIELD_METADATA_REG_C_7  = 0x58,
6875 	MLX5_ACTION_IN_FIELD_OUT_TCP_SEQ_NUM   = 0x59,
6876 	MLX5_ACTION_IN_FIELD_OUT_TCP_ACK_NUM   = 0x5B,
6877 	MLX5_ACTION_IN_FIELD_IPSEC_SYNDROME    = 0x5D,
6878 	MLX5_ACTION_IN_FIELD_OUT_EMD_47_32     = 0x6F,
6879 	MLX5_ACTION_IN_FIELD_OUT_EMD_31_0      = 0x70,
6880 };
6881 
6882 struct mlx5_ifc_alloc_modify_header_context_out_bits {
6883 	u8         status[0x8];
6884 	u8         reserved_at_8[0x18];
6885 
6886 	u8         syndrome[0x20];
6887 
6888 	u8         modify_header_id[0x20];
6889 
6890 	u8         reserved_at_60[0x20];
6891 };
6892 
6893 struct mlx5_ifc_alloc_modify_header_context_in_bits {
6894 	u8         opcode[0x10];
6895 	u8         reserved_at_10[0x10];
6896 
6897 	u8         reserved_at_20[0x10];
6898 	u8         op_mod[0x10];
6899 
6900 	u8         reserved_at_40[0x20];
6901 
6902 	u8         table_type[0x8];
6903 	u8         reserved_at_68[0x10];
6904 	u8         num_of_actions[0x8];
6905 
6906 	union mlx5_ifc_set_add_copy_action_in_auto_bits actions[];
6907 };
6908 
6909 struct mlx5_ifc_dealloc_modify_header_context_out_bits {
6910 	u8         status[0x8];
6911 	u8         reserved_at_8[0x18];
6912 
6913 	u8         syndrome[0x20];
6914 
6915 	u8         reserved_at_40[0x40];
6916 };
6917 
6918 struct mlx5_ifc_dealloc_modify_header_context_in_bits {
6919 	u8         opcode[0x10];
6920 	u8         reserved_at_10[0x10];
6921 
6922 	u8         reserved_at_20[0x10];
6923 	u8         op_mod[0x10];
6924 
6925 	u8         modify_header_id[0x20];
6926 
6927 	u8         reserved_at_60[0x20];
6928 };
6929 
6930 struct mlx5_ifc_query_modify_header_context_in_bits {
6931 	u8         opcode[0x10];
6932 	u8         uid[0x10];
6933 
6934 	u8         reserved_at_20[0x10];
6935 	u8         op_mod[0x10];
6936 
6937 	u8         modify_header_id[0x20];
6938 
6939 	u8         reserved_at_60[0xa0];
6940 };
6941 
6942 struct mlx5_ifc_query_dct_out_bits {
6943 	u8         status[0x8];
6944 	u8         reserved_at_8[0x18];
6945 
6946 	u8         syndrome[0x20];
6947 
6948 	u8         reserved_at_40[0x40];
6949 
6950 	struct mlx5_ifc_dctc_bits dct_context_entry;
6951 
6952 	u8         reserved_at_280[0x180];
6953 };
6954 
6955 struct mlx5_ifc_query_dct_in_bits {
6956 	u8         opcode[0x10];
6957 	u8         reserved_at_10[0x10];
6958 
6959 	u8         reserved_at_20[0x10];
6960 	u8         op_mod[0x10];
6961 
6962 	u8         reserved_at_40[0x8];
6963 	u8         dctn[0x18];
6964 
6965 	u8         reserved_at_60[0x20];
6966 };
6967 
6968 struct mlx5_ifc_query_cq_out_bits {
6969 	u8         status[0x8];
6970 	u8         reserved_at_8[0x18];
6971 
6972 	u8         syndrome[0x20];
6973 
6974 	u8         reserved_at_40[0x40];
6975 
6976 	struct mlx5_ifc_cqc_bits cq_context;
6977 
6978 	u8         reserved_at_280[0x600];
6979 
6980 	u8         pas[][0x40];
6981 };
6982 
6983 struct mlx5_ifc_query_cq_in_bits {
6984 	u8         opcode[0x10];
6985 	u8         reserved_at_10[0x10];
6986 
6987 	u8         reserved_at_20[0x10];
6988 	u8         op_mod[0x10];
6989 
6990 	u8         reserved_at_40[0x8];
6991 	u8         cqn[0x18];
6992 
6993 	u8         reserved_at_60[0x20];
6994 };
6995 
6996 struct mlx5_ifc_query_cong_status_out_bits {
6997 	u8         status[0x8];
6998 	u8         reserved_at_8[0x18];
6999 
7000 	u8         syndrome[0x20];
7001 
7002 	u8         reserved_at_40[0x20];
7003 
7004 	u8         enable[0x1];
7005 	u8         tag_enable[0x1];
7006 	u8         reserved_at_62[0x1e];
7007 };
7008 
7009 struct mlx5_ifc_query_cong_status_in_bits {
7010 	u8         opcode[0x10];
7011 	u8         reserved_at_10[0x10];
7012 
7013 	u8         reserved_at_20[0x10];
7014 	u8         op_mod[0x10];
7015 
7016 	u8         reserved_at_40[0x18];
7017 	u8         priority[0x4];
7018 	u8         cong_protocol[0x4];
7019 
7020 	u8         reserved_at_60[0x20];
7021 };
7022 
7023 struct mlx5_ifc_query_cong_statistics_out_bits {
7024 	u8         status[0x8];
7025 	u8         reserved_at_8[0x18];
7026 
7027 	u8         syndrome[0x20];
7028 
7029 	u8         reserved_at_40[0x40];
7030 
7031 	u8         rp_cur_flows[0x20];
7032 
7033 	u8         sum_flows[0x20];
7034 
7035 	u8         rp_cnp_ignored_high[0x20];
7036 
7037 	u8         rp_cnp_ignored_low[0x20];
7038 
7039 	u8         rp_cnp_handled_high[0x20];
7040 
7041 	u8         rp_cnp_handled_low[0x20];
7042 
7043 	u8         reserved_at_140[0x100];
7044 
7045 	u8         time_stamp_high[0x20];
7046 
7047 	u8         time_stamp_low[0x20];
7048 
7049 	u8         accumulators_period[0x20];
7050 
7051 	u8         np_ecn_marked_roce_packets_high[0x20];
7052 
7053 	u8         np_ecn_marked_roce_packets_low[0x20];
7054 
7055 	u8         np_cnp_sent_high[0x20];
7056 
7057 	u8         np_cnp_sent_low[0x20];
7058 
7059 	u8         reserved_at_320[0x560];
7060 };
7061 
7062 struct mlx5_ifc_query_cong_statistics_in_bits {
7063 	u8         opcode[0x10];
7064 	u8         reserved_at_10[0x10];
7065 
7066 	u8         reserved_at_20[0x10];
7067 	u8         op_mod[0x10];
7068 
7069 	u8         clear[0x1];
7070 	u8         reserved_at_41[0x1f];
7071 
7072 	u8         reserved_at_60[0x20];
7073 };
7074 
7075 struct mlx5_ifc_query_cong_params_out_bits {
7076 	u8         status[0x8];
7077 	u8         reserved_at_8[0x18];
7078 
7079 	u8         syndrome[0x20];
7080 
7081 	u8         reserved_at_40[0x40];
7082 
7083 	union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
7084 };
7085 
7086 struct mlx5_ifc_query_cong_params_in_bits {
7087 	u8         opcode[0x10];
7088 	u8         reserved_at_10[0x10];
7089 
7090 	u8         reserved_at_20[0x10];
7091 	u8         op_mod[0x10];
7092 
7093 	u8         reserved_at_40[0x1c];
7094 	u8         cong_protocol[0x4];
7095 
7096 	u8         reserved_at_60[0x20];
7097 };
7098 
7099 struct mlx5_ifc_query_adapter_out_bits {
7100 	u8         status[0x8];
7101 	u8         reserved_at_8[0x18];
7102 
7103 	u8         syndrome[0x20];
7104 
7105 	u8         reserved_at_40[0x40];
7106 
7107 	struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct;
7108 };
7109 
7110 struct mlx5_ifc_query_adapter_in_bits {
7111 	u8         opcode[0x10];
7112 	u8         reserved_at_10[0x10];
7113 
7114 	u8         reserved_at_20[0x10];
7115 	u8         op_mod[0x10];
7116 
7117 	u8         reserved_at_40[0x40];
7118 };
7119 
7120 struct mlx5_ifc_qp_2rst_out_bits {
7121 	u8         status[0x8];
7122 	u8         reserved_at_8[0x18];
7123 
7124 	u8         syndrome[0x20];
7125 
7126 	u8         reserved_at_40[0x40];
7127 };
7128 
7129 struct mlx5_ifc_qp_2rst_in_bits {
7130 	u8         opcode[0x10];
7131 	u8         uid[0x10];
7132 
7133 	u8         reserved_at_20[0x10];
7134 	u8         op_mod[0x10];
7135 
7136 	u8         reserved_at_40[0x8];
7137 	u8         qpn[0x18];
7138 
7139 	u8         reserved_at_60[0x20];
7140 };
7141 
7142 struct mlx5_ifc_qp_2err_out_bits {
7143 	u8         status[0x8];
7144 	u8         reserved_at_8[0x18];
7145 
7146 	u8         syndrome[0x20];
7147 
7148 	u8         reserved_at_40[0x40];
7149 };
7150 
7151 struct mlx5_ifc_qp_2err_in_bits {
7152 	u8         opcode[0x10];
7153 	u8         uid[0x10];
7154 
7155 	u8         reserved_at_20[0x10];
7156 	u8         op_mod[0x10];
7157 
7158 	u8         reserved_at_40[0x8];
7159 	u8         qpn[0x18];
7160 
7161 	u8         reserved_at_60[0x20];
7162 };
7163 
7164 struct mlx5_ifc_page_fault_resume_out_bits {
7165 	u8         status[0x8];
7166 	u8         reserved_at_8[0x18];
7167 
7168 	u8         syndrome[0x20];
7169 
7170 	u8         reserved_at_40[0x40];
7171 };
7172 
7173 struct mlx5_ifc_page_fault_resume_in_bits {
7174 	u8         opcode[0x10];
7175 	u8         reserved_at_10[0x10];
7176 
7177 	u8         reserved_at_20[0x10];
7178 	u8         op_mod[0x10];
7179 
7180 	u8         error[0x1];
7181 	u8         reserved_at_41[0x4];
7182 	u8         page_fault_type[0x3];
7183 	u8         wq_number[0x18];
7184 
7185 	u8         reserved_at_60[0x8];
7186 	u8         token[0x18];
7187 };
7188 
7189 struct mlx5_ifc_nop_out_bits {
7190 	u8         status[0x8];
7191 	u8         reserved_at_8[0x18];
7192 
7193 	u8         syndrome[0x20];
7194 
7195 	u8         reserved_at_40[0x40];
7196 };
7197 
7198 struct mlx5_ifc_nop_in_bits {
7199 	u8         opcode[0x10];
7200 	u8         reserved_at_10[0x10];
7201 
7202 	u8         reserved_at_20[0x10];
7203 	u8         op_mod[0x10];
7204 
7205 	u8         reserved_at_40[0x40];
7206 };
7207 
7208 struct mlx5_ifc_modify_vport_state_out_bits {
7209 	u8         status[0x8];
7210 	u8         reserved_at_8[0x18];
7211 
7212 	u8         syndrome[0x20];
7213 
7214 	u8         reserved_at_40[0x40];
7215 };
7216 
7217 struct mlx5_ifc_modify_vport_state_in_bits {
7218 	u8         opcode[0x10];
7219 	u8         reserved_at_10[0x10];
7220 
7221 	u8         reserved_at_20[0x10];
7222 	u8         op_mod[0x10];
7223 
7224 	u8         other_vport[0x1];
7225 	u8         reserved_at_41[0xf];
7226 	u8         vport_number[0x10];
7227 
7228 	u8         reserved_at_60[0x18];
7229 	u8         admin_state[0x4];
7230 	u8         reserved_at_7c[0x4];
7231 };
7232 
7233 struct mlx5_ifc_modify_tis_out_bits {
7234 	u8         status[0x8];
7235 	u8         reserved_at_8[0x18];
7236 
7237 	u8         syndrome[0x20];
7238 
7239 	u8         reserved_at_40[0x40];
7240 };
7241 
7242 struct mlx5_ifc_modify_tis_bitmask_bits {
7243 	u8         reserved_at_0[0x20];
7244 
7245 	u8         reserved_at_20[0x1d];
7246 	u8         lag_tx_port_affinity[0x1];
7247 	u8         strict_lag_tx_port_affinity[0x1];
7248 	u8         prio[0x1];
7249 };
7250 
7251 struct mlx5_ifc_modify_tis_in_bits {
7252 	u8         opcode[0x10];
7253 	u8         uid[0x10];
7254 
7255 	u8         reserved_at_20[0x10];
7256 	u8         op_mod[0x10];
7257 
7258 	u8         reserved_at_40[0x8];
7259 	u8         tisn[0x18];
7260 
7261 	u8         reserved_at_60[0x20];
7262 
7263 	struct mlx5_ifc_modify_tis_bitmask_bits bitmask;
7264 
7265 	u8         reserved_at_c0[0x40];
7266 
7267 	struct mlx5_ifc_tisc_bits ctx;
7268 };
7269 
7270 struct mlx5_ifc_modify_tir_bitmask_bits {
7271 	u8	   reserved_at_0[0x20];
7272 
7273 	u8         reserved_at_20[0x1b];
7274 	u8         self_lb_en[0x1];
7275 	u8         reserved_at_3c[0x1];
7276 	u8         hash[0x1];
7277 	u8         reserved_at_3e[0x1];
7278 	u8         packet_merge[0x1];
7279 };
7280 
7281 struct mlx5_ifc_modify_tir_out_bits {
7282 	u8         status[0x8];
7283 	u8         reserved_at_8[0x18];
7284 
7285 	u8         syndrome[0x20];
7286 
7287 	u8         reserved_at_40[0x40];
7288 };
7289 
7290 struct mlx5_ifc_modify_tir_in_bits {
7291 	u8         opcode[0x10];
7292 	u8         uid[0x10];
7293 
7294 	u8         reserved_at_20[0x10];
7295 	u8         op_mod[0x10];
7296 
7297 	u8         reserved_at_40[0x8];
7298 	u8         tirn[0x18];
7299 
7300 	u8         reserved_at_60[0x20];
7301 
7302 	struct mlx5_ifc_modify_tir_bitmask_bits bitmask;
7303 
7304 	u8         reserved_at_c0[0x40];
7305 
7306 	struct mlx5_ifc_tirc_bits ctx;
7307 };
7308 
7309 struct mlx5_ifc_modify_sq_out_bits {
7310 	u8         status[0x8];
7311 	u8         reserved_at_8[0x18];
7312 
7313 	u8         syndrome[0x20];
7314 
7315 	u8         reserved_at_40[0x40];
7316 };
7317 
7318 struct mlx5_ifc_modify_sq_in_bits {
7319 	u8         opcode[0x10];
7320 	u8         uid[0x10];
7321 
7322 	u8         reserved_at_20[0x10];
7323 	u8         op_mod[0x10];
7324 
7325 	u8         sq_state[0x4];
7326 	u8         reserved_at_44[0x4];
7327 	u8         sqn[0x18];
7328 
7329 	u8         reserved_at_60[0x20];
7330 
7331 	u8         modify_bitmask[0x40];
7332 
7333 	u8         reserved_at_c0[0x40];
7334 
7335 	struct mlx5_ifc_sqc_bits ctx;
7336 };
7337 
7338 struct mlx5_ifc_modify_scheduling_element_out_bits {
7339 	u8         status[0x8];
7340 	u8         reserved_at_8[0x18];
7341 
7342 	u8         syndrome[0x20];
7343 
7344 	u8         reserved_at_40[0x1c0];
7345 };
7346 
7347 enum {
7348 	MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1,
7349 	MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2,
7350 };
7351 
7352 struct mlx5_ifc_modify_scheduling_element_in_bits {
7353 	u8         opcode[0x10];
7354 	u8         reserved_at_10[0x10];
7355 
7356 	u8         reserved_at_20[0x10];
7357 	u8         op_mod[0x10];
7358 
7359 	u8         scheduling_hierarchy[0x8];
7360 	u8         reserved_at_48[0x18];
7361 
7362 	u8         scheduling_element_id[0x20];
7363 
7364 	u8         reserved_at_80[0x20];
7365 
7366 	u8         modify_bitmask[0x20];
7367 
7368 	u8         reserved_at_c0[0x40];
7369 
7370 	struct mlx5_ifc_scheduling_context_bits scheduling_context;
7371 
7372 	u8         reserved_at_300[0x100];
7373 };
7374 
7375 struct mlx5_ifc_modify_rqt_out_bits {
7376 	u8         status[0x8];
7377 	u8         reserved_at_8[0x18];
7378 
7379 	u8         syndrome[0x20];
7380 
7381 	u8         reserved_at_40[0x40];
7382 };
7383 
7384 struct mlx5_ifc_rqt_bitmask_bits {
7385 	u8	   reserved_at_0[0x20];
7386 
7387 	u8         reserved_at_20[0x1f];
7388 	u8         rqn_list[0x1];
7389 };
7390 
7391 struct mlx5_ifc_modify_rqt_in_bits {
7392 	u8         opcode[0x10];
7393 	u8         uid[0x10];
7394 
7395 	u8         reserved_at_20[0x10];
7396 	u8         op_mod[0x10];
7397 
7398 	u8         reserved_at_40[0x8];
7399 	u8         rqtn[0x18];
7400 
7401 	u8         reserved_at_60[0x20];
7402 
7403 	struct mlx5_ifc_rqt_bitmask_bits bitmask;
7404 
7405 	u8         reserved_at_c0[0x40];
7406 
7407 	struct mlx5_ifc_rqtc_bits ctx;
7408 };
7409 
7410 struct mlx5_ifc_modify_rq_out_bits {
7411 	u8         status[0x8];
7412 	u8         reserved_at_8[0x18];
7413 
7414 	u8         syndrome[0x20];
7415 
7416 	u8         reserved_at_40[0x40];
7417 };
7418 
7419 enum {
7420 	MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1,
7421 	MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2,
7422 	MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3,
7423 };
7424 
7425 struct mlx5_ifc_modify_rq_in_bits {
7426 	u8         opcode[0x10];
7427 	u8         uid[0x10];
7428 
7429 	u8         reserved_at_20[0x10];
7430 	u8         op_mod[0x10];
7431 
7432 	u8         rq_state[0x4];
7433 	u8         reserved_at_44[0x4];
7434 	u8         rqn[0x18];
7435 
7436 	u8         reserved_at_60[0x20];
7437 
7438 	u8         modify_bitmask[0x40];
7439 
7440 	u8         reserved_at_c0[0x40];
7441 
7442 	struct mlx5_ifc_rqc_bits ctx;
7443 };
7444 
7445 struct mlx5_ifc_modify_rmp_out_bits {
7446 	u8         status[0x8];
7447 	u8         reserved_at_8[0x18];
7448 
7449 	u8         syndrome[0x20];
7450 
7451 	u8         reserved_at_40[0x40];
7452 };
7453 
7454 struct mlx5_ifc_rmp_bitmask_bits {
7455 	u8	   reserved_at_0[0x20];
7456 
7457 	u8         reserved_at_20[0x1f];
7458 	u8         lwm[0x1];
7459 };
7460 
7461 struct mlx5_ifc_modify_rmp_in_bits {
7462 	u8         opcode[0x10];
7463 	u8         uid[0x10];
7464 
7465 	u8         reserved_at_20[0x10];
7466 	u8         op_mod[0x10];
7467 
7468 	u8         rmp_state[0x4];
7469 	u8         reserved_at_44[0x4];
7470 	u8         rmpn[0x18];
7471 
7472 	u8         reserved_at_60[0x20];
7473 
7474 	struct mlx5_ifc_rmp_bitmask_bits bitmask;
7475 
7476 	u8         reserved_at_c0[0x40];
7477 
7478 	struct mlx5_ifc_rmpc_bits ctx;
7479 };
7480 
7481 struct mlx5_ifc_modify_nic_vport_context_out_bits {
7482 	u8         status[0x8];
7483 	u8         reserved_at_8[0x18];
7484 
7485 	u8         syndrome[0x20];
7486 
7487 	u8         reserved_at_40[0x40];
7488 };
7489 
7490 struct mlx5_ifc_modify_nic_vport_field_select_bits {
7491 	u8         reserved_at_0[0x12];
7492 	u8	   affiliation[0x1];
7493 	u8	   reserved_at_13[0x1];
7494 	u8         disable_uc_local_lb[0x1];
7495 	u8         disable_mc_local_lb[0x1];
7496 	u8         node_guid[0x1];
7497 	u8         port_guid[0x1];
7498 	u8         min_inline[0x1];
7499 	u8         mtu[0x1];
7500 	u8         change_event[0x1];
7501 	u8         promisc[0x1];
7502 	u8         permanent_address[0x1];
7503 	u8         addresses_list[0x1];
7504 	u8         roce_en[0x1];
7505 	u8         reserved_at_1f[0x1];
7506 };
7507 
7508 struct mlx5_ifc_modify_nic_vport_context_in_bits {
7509 	u8         opcode[0x10];
7510 	u8         reserved_at_10[0x10];
7511 
7512 	u8         reserved_at_20[0x10];
7513 	u8         op_mod[0x10];
7514 
7515 	u8         other_vport[0x1];
7516 	u8         reserved_at_41[0xf];
7517 	u8         vport_number[0x10];
7518 
7519 	struct mlx5_ifc_modify_nic_vport_field_select_bits field_select;
7520 
7521 	u8         reserved_at_80[0x780];
7522 
7523 	struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
7524 };
7525 
7526 struct mlx5_ifc_modify_hca_vport_context_out_bits {
7527 	u8         status[0x8];
7528 	u8         reserved_at_8[0x18];
7529 
7530 	u8         syndrome[0x20];
7531 
7532 	u8         reserved_at_40[0x40];
7533 };
7534 
7535 struct mlx5_ifc_modify_hca_vport_context_in_bits {
7536 	u8         opcode[0x10];
7537 	u8         reserved_at_10[0x10];
7538 
7539 	u8         reserved_at_20[0x10];
7540 	u8         op_mod[0x10];
7541 
7542 	u8         other_vport[0x1];
7543 	u8         reserved_at_41[0xb];
7544 	u8         port_num[0x4];
7545 	u8         vport_number[0x10];
7546 
7547 	u8         reserved_at_60[0x20];
7548 
7549 	struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
7550 };
7551 
7552 struct mlx5_ifc_modify_cq_out_bits {
7553 	u8         status[0x8];
7554 	u8         reserved_at_8[0x18];
7555 
7556 	u8         syndrome[0x20];
7557 
7558 	u8         reserved_at_40[0x40];
7559 };
7560 
7561 enum {
7562 	MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ  = 0x0,
7563 	MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ  = 0x1,
7564 };
7565 
7566 struct mlx5_ifc_modify_cq_in_bits {
7567 	u8         opcode[0x10];
7568 	u8         uid[0x10];
7569 
7570 	u8         reserved_at_20[0x10];
7571 	u8         op_mod[0x10];
7572 
7573 	u8         reserved_at_40[0x8];
7574 	u8         cqn[0x18];
7575 
7576 	union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select;
7577 
7578 	struct mlx5_ifc_cqc_bits cq_context;
7579 
7580 	u8         reserved_at_280[0x60];
7581 
7582 	u8         cq_umem_valid[0x1];
7583 	u8         reserved_at_2e1[0x1f];
7584 
7585 	u8         reserved_at_300[0x580];
7586 
7587 	u8         pas[][0x40];
7588 };
7589 
7590 struct mlx5_ifc_modify_cong_status_out_bits {
7591 	u8         status[0x8];
7592 	u8         reserved_at_8[0x18];
7593 
7594 	u8         syndrome[0x20];
7595 
7596 	u8         reserved_at_40[0x40];
7597 };
7598 
7599 struct mlx5_ifc_modify_cong_status_in_bits {
7600 	u8         opcode[0x10];
7601 	u8         reserved_at_10[0x10];
7602 
7603 	u8         reserved_at_20[0x10];
7604 	u8         op_mod[0x10];
7605 
7606 	u8         reserved_at_40[0x18];
7607 	u8         priority[0x4];
7608 	u8         cong_protocol[0x4];
7609 
7610 	u8         enable[0x1];
7611 	u8         tag_enable[0x1];
7612 	u8         reserved_at_62[0x1e];
7613 };
7614 
7615 struct mlx5_ifc_modify_cong_params_out_bits {
7616 	u8         status[0x8];
7617 	u8         reserved_at_8[0x18];
7618 
7619 	u8         syndrome[0x20];
7620 
7621 	u8         reserved_at_40[0x40];
7622 };
7623 
7624 struct mlx5_ifc_modify_cong_params_in_bits {
7625 	u8         opcode[0x10];
7626 	u8         reserved_at_10[0x10];
7627 
7628 	u8         reserved_at_20[0x10];
7629 	u8         op_mod[0x10];
7630 
7631 	u8         reserved_at_40[0x1c];
7632 	u8         cong_protocol[0x4];
7633 
7634 	union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select;
7635 
7636 	u8         reserved_at_80[0x80];
7637 
7638 	union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
7639 };
7640 
7641 struct mlx5_ifc_manage_pages_out_bits {
7642 	u8         status[0x8];
7643 	u8         reserved_at_8[0x18];
7644 
7645 	u8         syndrome[0x20];
7646 
7647 	u8         output_num_entries[0x20];
7648 
7649 	u8         reserved_at_60[0x20];
7650 
7651 	u8         pas[][0x40];
7652 };
7653 
7654 enum {
7655 	MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL     = 0x0,
7656 	MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS  = 0x1,
7657 	MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES    = 0x2,
7658 };
7659 
7660 struct mlx5_ifc_manage_pages_in_bits {
7661 	u8         opcode[0x10];
7662 	u8         reserved_at_10[0x10];
7663 
7664 	u8         reserved_at_20[0x10];
7665 	u8         op_mod[0x10];
7666 
7667 	u8         embedded_cpu_function[0x1];
7668 	u8         reserved_at_41[0xf];
7669 	u8         function_id[0x10];
7670 
7671 	u8         input_num_entries[0x20];
7672 
7673 	u8         pas[][0x40];
7674 };
7675 
7676 struct mlx5_ifc_mad_ifc_out_bits {
7677 	u8         status[0x8];
7678 	u8         reserved_at_8[0x18];
7679 
7680 	u8         syndrome[0x20];
7681 
7682 	u8         reserved_at_40[0x40];
7683 
7684 	u8         response_mad_packet[256][0x8];
7685 };
7686 
7687 struct mlx5_ifc_mad_ifc_in_bits {
7688 	u8         opcode[0x10];
7689 	u8         reserved_at_10[0x10];
7690 
7691 	u8         reserved_at_20[0x10];
7692 	u8         op_mod[0x10];
7693 
7694 	u8         remote_lid[0x10];
7695 	u8         reserved_at_50[0x8];
7696 	u8         port[0x8];
7697 
7698 	u8         reserved_at_60[0x20];
7699 
7700 	u8         mad[256][0x8];
7701 };
7702 
7703 struct mlx5_ifc_init_hca_out_bits {
7704 	u8         status[0x8];
7705 	u8         reserved_at_8[0x18];
7706 
7707 	u8         syndrome[0x20];
7708 
7709 	u8         reserved_at_40[0x40];
7710 };
7711 
7712 struct mlx5_ifc_init_hca_in_bits {
7713 	u8         opcode[0x10];
7714 	u8         reserved_at_10[0x10];
7715 
7716 	u8         reserved_at_20[0x10];
7717 	u8         op_mod[0x10];
7718 
7719 	u8         reserved_at_40[0x20];
7720 
7721 	u8         reserved_at_60[0x2];
7722 	u8         sw_vhca_id[0xe];
7723 	u8         reserved_at_70[0x10];
7724 
7725 	u8	   sw_owner_id[4][0x20];
7726 };
7727 
7728 struct mlx5_ifc_init2rtr_qp_out_bits {
7729 	u8         status[0x8];
7730 	u8         reserved_at_8[0x18];
7731 
7732 	u8         syndrome[0x20];
7733 
7734 	u8         reserved_at_40[0x20];
7735 	u8         ece[0x20];
7736 };
7737 
7738 struct mlx5_ifc_init2rtr_qp_in_bits {
7739 	u8         opcode[0x10];
7740 	u8         uid[0x10];
7741 
7742 	u8         reserved_at_20[0x10];
7743 	u8         op_mod[0x10];
7744 
7745 	u8         reserved_at_40[0x8];
7746 	u8         qpn[0x18];
7747 
7748 	u8         reserved_at_60[0x20];
7749 
7750 	u8         opt_param_mask[0x20];
7751 
7752 	u8         ece[0x20];
7753 
7754 	struct mlx5_ifc_qpc_bits qpc;
7755 
7756 	u8         reserved_at_800[0x80];
7757 };
7758 
7759 struct mlx5_ifc_init2init_qp_out_bits {
7760 	u8         status[0x8];
7761 	u8         reserved_at_8[0x18];
7762 
7763 	u8         syndrome[0x20];
7764 
7765 	u8         reserved_at_40[0x20];
7766 	u8         ece[0x20];
7767 };
7768 
7769 struct mlx5_ifc_init2init_qp_in_bits {
7770 	u8         opcode[0x10];
7771 	u8         uid[0x10];
7772 
7773 	u8         reserved_at_20[0x10];
7774 	u8         op_mod[0x10];
7775 
7776 	u8         reserved_at_40[0x8];
7777 	u8         qpn[0x18];
7778 
7779 	u8         reserved_at_60[0x20];
7780 
7781 	u8         opt_param_mask[0x20];
7782 
7783 	u8         ece[0x20];
7784 
7785 	struct mlx5_ifc_qpc_bits qpc;
7786 
7787 	u8         reserved_at_800[0x80];
7788 };
7789 
7790 struct mlx5_ifc_get_dropped_packet_log_out_bits {
7791 	u8         status[0x8];
7792 	u8         reserved_at_8[0x18];
7793 
7794 	u8         syndrome[0x20];
7795 
7796 	u8         reserved_at_40[0x40];
7797 
7798 	u8         packet_headers_log[128][0x8];
7799 
7800 	u8         packet_syndrome[64][0x8];
7801 };
7802 
7803 struct mlx5_ifc_get_dropped_packet_log_in_bits {
7804 	u8         opcode[0x10];
7805 	u8         reserved_at_10[0x10];
7806 
7807 	u8         reserved_at_20[0x10];
7808 	u8         op_mod[0x10];
7809 
7810 	u8         reserved_at_40[0x40];
7811 };
7812 
7813 struct mlx5_ifc_gen_eqe_in_bits {
7814 	u8         opcode[0x10];
7815 	u8         reserved_at_10[0x10];
7816 
7817 	u8         reserved_at_20[0x10];
7818 	u8         op_mod[0x10];
7819 
7820 	u8         reserved_at_40[0x18];
7821 	u8         eq_number[0x8];
7822 
7823 	u8         reserved_at_60[0x20];
7824 
7825 	u8         eqe[64][0x8];
7826 };
7827 
7828 struct mlx5_ifc_gen_eq_out_bits {
7829 	u8         status[0x8];
7830 	u8         reserved_at_8[0x18];
7831 
7832 	u8         syndrome[0x20];
7833 
7834 	u8         reserved_at_40[0x40];
7835 };
7836 
7837 struct mlx5_ifc_enable_hca_out_bits {
7838 	u8         status[0x8];
7839 	u8         reserved_at_8[0x18];
7840 
7841 	u8         syndrome[0x20];
7842 
7843 	u8         reserved_at_40[0x20];
7844 };
7845 
7846 struct mlx5_ifc_enable_hca_in_bits {
7847 	u8         opcode[0x10];
7848 	u8         reserved_at_10[0x10];
7849 
7850 	u8         reserved_at_20[0x10];
7851 	u8         op_mod[0x10];
7852 
7853 	u8         embedded_cpu_function[0x1];
7854 	u8         reserved_at_41[0xf];
7855 	u8         function_id[0x10];
7856 
7857 	u8         reserved_at_60[0x20];
7858 };
7859 
7860 struct mlx5_ifc_drain_dct_out_bits {
7861 	u8         status[0x8];
7862 	u8         reserved_at_8[0x18];
7863 
7864 	u8         syndrome[0x20];
7865 
7866 	u8         reserved_at_40[0x40];
7867 };
7868 
7869 struct mlx5_ifc_drain_dct_in_bits {
7870 	u8         opcode[0x10];
7871 	u8         uid[0x10];
7872 
7873 	u8         reserved_at_20[0x10];
7874 	u8         op_mod[0x10];
7875 
7876 	u8         reserved_at_40[0x8];
7877 	u8         dctn[0x18];
7878 
7879 	u8         reserved_at_60[0x20];
7880 };
7881 
7882 struct mlx5_ifc_disable_hca_out_bits {
7883 	u8         status[0x8];
7884 	u8         reserved_at_8[0x18];
7885 
7886 	u8         syndrome[0x20];
7887 
7888 	u8         reserved_at_40[0x20];
7889 };
7890 
7891 struct mlx5_ifc_disable_hca_in_bits {
7892 	u8         opcode[0x10];
7893 	u8         reserved_at_10[0x10];
7894 
7895 	u8         reserved_at_20[0x10];
7896 	u8         op_mod[0x10];
7897 
7898 	u8         embedded_cpu_function[0x1];
7899 	u8         reserved_at_41[0xf];
7900 	u8         function_id[0x10];
7901 
7902 	u8         reserved_at_60[0x20];
7903 };
7904 
7905 struct mlx5_ifc_detach_from_mcg_out_bits {
7906 	u8         status[0x8];
7907 	u8         reserved_at_8[0x18];
7908 
7909 	u8         syndrome[0x20];
7910 
7911 	u8         reserved_at_40[0x40];
7912 };
7913 
7914 struct mlx5_ifc_detach_from_mcg_in_bits {
7915 	u8         opcode[0x10];
7916 	u8         uid[0x10];
7917 
7918 	u8         reserved_at_20[0x10];
7919 	u8         op_mod[0x10];
7920 
7921 	u8         reserved_at_40[0x8];
7922 	u8         qpn[0x18];
7923 
7924 	u8         reserved_at_60[0x20];
7925 
7926 	u8         multicast_gid[16][0x8];
7927 };
7928 
7929 struct mlx5_ifc_destroy_xrq_out_bits {
7930 	u8         status[0x8];
7931 	u8         reserved_at_8[0x18];
7932 
7933 	u8         syndrome[0x20];
7934 
7935 	u8         reserved_at_40[0x40];
7936 };
7937 
7938 struct mlx5_ifc_destroy_xrq_in_bits {
7939 	u8         opcode[0x10];
7940 	u8         uid[0x10];
7941 
7942 	u8         reserved_at_20[0x10];
7943 	u8         op_mod[0x10];
7944 
7945 	u8         reserved_at_40[0x8];
7946 	u8         xrqn[0x18];
7947 
7948 	u8         reserved_at_60[0x20];
7949 };
7950 
7951 struct mlx5_ifc_destroy_xrc_srq_out_bits {
7952 	u8         status[0x8];
7953 	u8         reserved_at_8[0x18];
7954 
7955 	u8         syndrome[0x20];
7956 
7957 	u8         reserved_at_40[0x40];
7958 };
7959 
7960 struct mlx5_ifc_destroy_xrc_srq_in_bits {
7961 	u8         opcode[0x10];
7962 	u8         uid[0x10];
7963 
7964 	u8         reserved_at_20[0x10];
7965 	u8         op_mod[0x10];
7966 
7967 	u8         reserved_at_40[0x8];
7968 	u8         xrc_srqn[0x18];
7969 
7970 	u8         reserved_at_60[0x20];
7971 };
7972 
7973 struct mlx5_ifc_destroy_tis_out_bits {
7974 	u8         status[0x8];
7975 	u8         reserved_at_8[0x18];
7976 
7977 	u8         syndrome[0x20];
7978 
7979 	u8         reserved_at_40[0x40];
7980 };
7981 
7982 struct mlx5_ifc_destroy_tis_in_bits {
7983 	u8         opcode[0x10];
7984 	u8         uid[0x10];
7985 
7986 	u8         reserved_at_20[0x10];
7987 	u8         op_mod[0x10];
7988 
7989 	u8         reserved_at_40[0x8];
7990 	u8         tisn[0x18];
7991 
7992 	u8         reserved_at_60[0x20];
7993 };
7994 
7995 struct mlx5_ifc_destroy_tir_out_bits {
7996 	u8         status[0x8];
7997 	u8         reserved_at_8[0x18];
7998 
7999 	u8         syndrome[0x20];
8000 
8001 	u8         reserved_at_40[0x40];
8002 };
8003 
8004 struct mlx5_ifc_destroy_tir_in_bits {
8005 	u8         opcode[0x10];
8006 	u8         uid[0x10];
8007 
8008 	u8         reserved_at_20[0x10];
8009 	u8         op_mod[0x10];
8010 
8011 	u8         reserved_at_40[0x8];
8012 	u8         tirn[0x18];
8013 
8014 	u8         reserved_at_60[0x20];
8015 };
8016 
8017 struct mlx5_ifc_destroy_srq_out_bits {
8018 	u8         status[0x8];
8019 	u8         reserved_at_8[0x18];
8020 
8021 	u8         syndrome[0x20];
8022 
8023 	u8         reserved_at_40[0x40];
8024 };
8025 
8026 struct mlx5_ifc_destroy_srq_in_bits {
8027 	u8         opcode[0x10];
8028 	u8         uid[0x10];
8029 
8030 	u8         reserved_at_20[0x10];
8031 	u8         op_mod[0x10];
8032 
8033 	u8         reserved_at_40[0x8];
8034 	u8         srqn[0x18];
8035 
8036 	u8         reserved_at_60[0x20];
8037 };
8038 
8039 struct mlx5_ifc_destroy_sq_out_bits {
8040 	u8         status[0x8];
8041 	u8         reserved_at_8[0x18];
8042 
8043 	u8         syndrome[0x20];
8044 
8045 	u8         reserved_at_40[0x40];
8046 };
8047 
8048 struct mlx5_ifc_destroy_sq_in_bits {
8049 	u8         opcode[0x10];
8050 	u8         uid[0x10];
8051 
8052 	u8         reserved_at_20[0x10];
8053 	u8         op_mod[0x10];
8054 
8055 	u8         reserved_at_40[0x8];
8056 	u8         sqn[0x18];
8057 
8058 	u8         reserved_at_60[0x20];
8059 };
8060 
8061 struct mlx5_ifc_destroy_scheduling_element_out_bits {
8062 	u8         status[0x8];
8063 	u8         reserved_at_8[0x18];
8064 
8065 	u8         syndrome[0x20];
8066 
8067 	u8         reserved_at_40[0x1c0];
8068 };
8069 
8070 struct mlx5_ifc_destroy_scheduling_element_in_bits {
8071 	u8         opcode[0x10];
8072 	u8         reserved_at_10[0x10];
8073 
8074 	u8         reserved_at_20[0x10];
8075 	u8         op_mod[0x10];
8076 
8077 	u8         scheduling_hierarchy[0x8];
8078 	u8         reserved_at_48[0x18];
8079 
8080 	u8         scheduling_element_id[0x20];
8081 
8082 	u8         reserved_at_80[0x180];
8083 };
8084 
8085 struct mlx5_ifc_destroy_rqt_out_bits {
8086 	u8         status[0x8];
8087 	u8         reserved_at_8[0x18];
8088 
8089 	u8         syndrome[0x20];
8090 
8091 	u8         reserved_at_40[0x40];
8092 };
8093 
8094 struct mlx5_ifc_destroy_rqt_in_bits {
8095 	u8         opcode[0x10];
8096 	u8         uid[0x10];
8097 
8098 	u8         reserved_at_20[0x10];
8099 	u8         op_mod[0x10];
8100 
8101 	u8         reserved_at_40[0x8];
8102 	u8         rqtn[0x18];
8103 
8104 	u8         reserved_at_60[0x20];
8105 };
8106 
8107 struct mlx5_ifc_destroy_rq_out_bits {
8108 	u8         status[0x8];
8109 	u8         reserved_at_8[0x18];
8110 
8111 	u8         syndrome[0x20];
8112 
8113 	u8         reserved_at_40[0x40];
8114 };
8115 
8116 struct mlx5_ifc_destroy_rq_in_bits {
8117 	u8         opcode[0x10];
8118 	u8         uid[0x10];
8119 
8120 	u8         reserved_at_20[0x10];
8121 	u8         op_mod[0x10];
8122 
8123 	u8         reserved_at_40[0x8];
8124 	u8         rqn[0x18];
8125 
8126 	u8         reserved_at_60[0x20];
8127 };
8128 
8129 struct mlx5_ifc_set_delay_drop_params_in_bits {
8130 	u8         opcode[0x10];
8131 	u8         reserved_at_10[0x10];
8132 
8133 	u8         reserved_at_20[0x10];
8134 	u8         op_mod[0x10];
8135 
8136 	u8         reserved_at_40[0x20];
8137 
8138 	u8         reserved_at_60[0x10];
8139 	u8         delay_drop_timeout[0x10];
8140 };
8141 
8142 struct mlx5_ifc_set_delay_drop_params_out_bits {
8143 	u8         status[0x8];
8144 	u8         reserved_at_8[0x18];
8145 
8146 	u8         syndrome[0x20];
8147 
8148 	u8         reserved_at_40[0x40];
8149 };
8150 
8151 struct mlx5_ifc_destroy_rmp_out_bits {
8152 	u8         status[0x8];
8153 	u8         reserved_at_8[0x18];
8154 
8155 	u8         syndrome[0x20];
8156 
8157 	u8         reserved_at_40[0x40];
8158 };
8159 
8160 struct mlx5_ifc_destroy_rmp_in_bits {
8161 	u8         opcode[0x10];
8162 	u8         uid[0x10];
8163 
8164 	u8         reserved_at_20[0x10];
8165 	u8         op_mod[0x10];
8166 
8167 	u8         reserved_at_40[0x8];
8168 	u8         rmpn[0x18];
8169 
8170 	u8         reserved_at_60[0x20];
8171 };
8172 
8173 struct mlx5_ifc_destroy_qp_out_bits {
8174 	u8         status[0x8];
8175 	u8         reserved_at_8[0x18];
8176 
8177 	u8         syndrome[0x20];
8178 
8179 	u8         reserved_at_40[0x40];
8180 };
8181 
8182 struct mlx5_ifc_destroy_qp_in_bits {
8183 	u8         opcode[0x10];
8184 	u8         uid[0x10];
8185 
8186 	u8         reserved_at_20[0x10];
8187 	u8         op_mod[0x10];
8188 
8189 	u8         reserved_at_40[0x8];
8190 	u8         qpn[0x18];
8191 
8192 	u8         reserved_at_60[0x20];
8193 };
8194 
8195 struct mlx5_ifc_destroy_psv_out_bits {
8196 	u8         status[0x8];
8197 	u8         reserved_at_8[0x18];
8198 
8199 	u8         syndrome[0x20];
8200 
8201 	u8         reserved_at_40[0x40];
8202 };
8203 
8204 struct mlx5_ifc_destroy_psv_in_bits {
8205 	u8         opcode[0x10];
8206 	u8         reserved_at_10[0x10];
8207 
8208 	u8         reserved_at_20[0x10];
8209 	u8         op_mod[0x10];
8210 
8211 	u8         reserved_at_40[0x8];
8212 	u8         psvn[0x18];
8213 
8214 	u8         reserved_at_60[0x20];
8215 };
8216 
8217 struct mlx5_ifc_destroy_mkey_out_bits {
8218 	u8         status[0x8];
8219 	u8         reserved_at_8[0x18];
8220 
8221 	u8         syndrome[0x20];
8222 
8223 	u8         reserved_at_40[0x40];
8224 };
8225 
8226 struct mlx5_ifc_destroy_mkey_in_bits {
8227 	u8         opcode[0x10];
8228 	u8         uid[0x10];
8229 
8230 	u8         reserved_at_20[0x10];
8231 	u8         op_mod[0x10];
8232 
8233 	u8         reserved_at_40[0x8];
8234 	u8         mkey_index[0x18];
8235 
8236 	u8         reserved_at_60[0x20];
8237 };
8238 
8239 struct mlx5_ifc_destroy_flow_table_out_bits {
8240 	u8         status[0x8];
8241 	u8         reserved_at_8[0x18];
8242 
8243 	u8         syndrome[0x20];
8244 
8245 	u8         reserved_at_40[0x40];
8246 };
8247 
8248 struct mlx5_ifc_destroy_flow_table_in_bits {
8249 	u8         opcode[0x10];
8250 	u8         reserved_at_10[0x10];
8251 
8252 	u8         reserved_at_20[0x10];
8253 	u8         op_mod[0x10];
8254 
8255 	u8         other_vport[0x1];
8256 	u8         reserved_at_41[0xf];
8257 	u8         vport_number[0x10];
8258 
8259 	u8         reserved_at_60[0x20];
8260 
8261 	u8         table_type[0x8];
8262 	u8         reserved_at_88[0x18];
8263 
8264 	u8         reserved_at_a0[0x8];
8265 	u8         table_id[0x18];
8266 
8267 	u8         reserved_at_c0[0x140];
8268 };
8269 
8270 struct mlx5_ifc_destroy_flow_group_out_bits {
8271 	u8         status[0x8];
8272 	u8         reserved_at_8[0x18];
8273 
8274 	u8         syndrome[0x20];
8275 
8276 	u8         reserved_at_40[0x40];
8277 };
8278 
8279 struct mlx5_ifc_destroy_flow_group_in_bits {
8280 	u8         opcode[0x10];
8281 	u8         reserved_at_10[0x10];
8282 
8283 	u8         reserved_at_20[0x10];
8284 	u8         op_mod[0x10];
8285 
8286 	u8         other_vport[0x1];
8287 	u8         reserved_at_41[0xf];
8288 	u8         vport_number[0x10];
8289 
8290 	u8         reserved_at_60[0x20];
8291 
8292 	u8         table_type[0x8];
8293 	u8         reserved_at_88[0x18];
8294 
8295 	u8         reserved_at_a0[0x8];
8296 	u8         table_id[0x18];
8297 
8298 	u8         group_id[0x20];
8299 
8300 	u8         reserved_at_e0[0x120];
8301 };
8302 
8303 struct mlx5_ifc_destroy_eq_out_bits {
8304 	u8         status[0x8];
8305 	u8         reserved_at_8[0x18];
8306 
8307 	u8         syndrome[0x20];
8308 
8309 	u8         reserved_at_40[0x40];
8310 };
8311 
8312 struct mlx5_ifc_destroy_eq_in_bits {
8313 	u8         opcode[0x10];
8314 	u8         reserved_at_10[0x10];
8315 
8316 	u8         reserved_at_20[0x10];
8317 	u8         op_mod[0x10];
8318 
8319 	u8         reserved_at_40[0x18];
8320 	u8         eq_number[0x8];
8321 
8322 	u8         reserved_at_60[0x20];
8323 };
8324 
8325 struct mlx5_ifc_destroy_dct_out_bits {
8326 	u8         status[0x8];
8327 	u8         reserved_at_8[0x18];
8328 
8329 	u8         syndrome[0x20];
8330 
8331 	u8         reserved_at_40[0x40];
8332 };
8333 
8334 struct mlx5_ifc_destroy_dct_in_bits {
8335 	u8         opcode[0x10];
8336 	u8         uid[0x10];
8337 
8338 	u8         reserved_at_20[0x10];
8339 	u8         op_mod[0x10];
8340 
8341 	u8         reserved_at_40[0x8];
8342 	u8         dctn[0x18];
8343 
8344 	u8         reserved_at_60[0x20];
8345 };
8346 
8347 struct mlx5_ifc_destroy_cq_out_bits {
8348 	u8         status[0x8];
8349 	u8         reserved_at_8[0x18];
8350 
8351 	u8         syndrome[0x20];
8352 
8353 	u8         reserved_at_40[0x40];
8354 };
8355 
8356 struct mlx5_ifc_destroy_cq_in_bits {
8357 	u8         opcode[0x10];
8358 	u8         uid[0x10];
8359 
8360 	u8         reserved_at_20[0x10];
8361 	u8         op_mod[0x10];
8362 
8363 	u8         reserved_at_40[0x8];
8364 	u8         cqn[0x18];
8365 
8366 	u8         reserved_at_60[0x20];
8367 };
8368 
8369 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits {
8370 	u8         status[0x8];
8371 	u8         reserved_at_8[0x18];
8372 
8373 	u8         syndrome[0x20];
8374 
8375 	u8         reserved_at_40[0x40];
8376 };
8377 
8378 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits {
8379 	u8         opcode[0x10];
8380 	u8         reserved_at_10[0x10];
8381 
8382 	u8         reserved_at_20[0x10];
8383 	u8         op_mod[0x10];
8384 
8385 	u8         reserved_at_40[0x20];
8386 
8387 	u8         reserved_at_60[0x10];
8388 	u8         vxlan_udp_port[0x10];
8389 };
8390 
8391 struct mlx5_ifc_delete_l2_table_entry_out_bits {
8392 	u8         status[0x8];
8393 	u8         reserved_at_8[0x18];
8394 
8395 	u8         syndrome[0x20];
8396 
8397 	u8         reserved_at_40[0x40];
8398 };
8399 
8400 struct mlx5_ifc_delete_l2_table_entry_in_bits {
8401 	u8         opcode[0x10];
8402 	u8         reserved_at_10[0x10];
8403 
8404 	u8         reserved_at_20[0x10];
8405 	u8         op_mod[0x10];
8406 
8407 	u8         reserved_at_40[0x60];
8408 
8409 	u8         reserved_at_a0[0x8];
8410 	u8         table_index[0x18];
8411 
8412 	u8         reserved_at_c0[0x140];
8413 };
8414 
8415 struct mlx5_ifc_delete_fte_out_bits {
8416 	u8         status[0x8];
8417 	u8         reserved_at_8[0x18];
8418 
8419 	u8         syndrome[0x20];
8420 
8421 	u8         reserved_at_40[0x40];
8422 };
8423 
8424 struct mlx5_ifc_delete_fte_in_bits {
8425 	u8         opcode[0x10];
8426 	u8         reserved_at_10[0x10];
8427 
8428 	u8         reserved_at_20[0x10];
8429 	u8         op_mod[0x10];
8430 
8431 	u8         other_vport[0x1];
8432 	u8         reserved_at_41[0xf];
8433 	u8         vport_number[0x10];
8434 
8435 	u8         reserved_at_60[0x20];
8436 
8437 	u8         table_type[0x8];
8438 	u8         reserved_at_88[0x18];
8439 
8440 	u8         reserved_at_a0[0x8];
8441 	u8         table_id[0x18];
8442 
8443 	u8         reserved_at_c0[0x40];
8444 
8445 	u8         flow_index[0x20];
8446 
8447 	u8         reserved_at_120[0xe0];
8448 };
8449 
8450 struct mlx5_ifc_dealloc_xrcd_out_bits {
8451 	u8         status[0x8];
8452 	u8         reserved_at_8[0x18];
8453 
8454 	u8         syndrome[0x20];
8455 
8456 	u8         reserved_at_40[0x40];
8457 };
8458 
8459 struct mlx5_ifc_dealloc_xrcd_in_bits {
8460 	u8         opcode[0x10];
8461 	u8         uid[0x10];
8462 
8463 	u8         reserved_at_20[0x10];
8464 	u8         op_mod[0x10];
8465 
8466 	u8         reserved_at_40[0x8];
8467 	u8         xrcd[0x18];
8468 
8469 	u8         reserved_at_60[0x20];
8470 };
8471 
8472 struct mlx5_ifc_dealloc_uar_out_bits {
8473 	u8         status[0x8];
8474 	u8         reserved_at_8[0x18];
8475 
8476 	u8         syndrome[0x20];
8477 
8478 	u8         reserved_at_40[0x40];
8479 };
8480 
8481 struct mlx5_ifc_dealloc_uar_in_bits {
8482 	u8         opcode[0x10];
8483 	u8         uid[0x10];
8484 
8485 	u8         reserved_at_20[0x10];
8486 	u8         op_mod[0x10];
8487 
8488 	u8         reserved_at_40[0x8];
8489 	u8         uar[0x18];
8490 
8491 	u8         reserved_at_60[0x20];
8492 };
8493 
8494 struct mlx5_ifc_dealloc_transport_domain_out_bits {
8495 	u8         status[0x8];
8496 	u8         reserved_at_8[0x18];
8497 
8498 	u8         syndrome[0x20];
8499 
8500 	u8         reserved_at_40[0x40];
8501 };
8502 
8503 struct mlx5_ifc_dealloc_transport_domain_in_bits {
8504 	u8         opcode[0x10];
8505 	u8         uid[0x10];
8506 
8507 	u8         reserved_at_20[0x10];
8508 	u8         op_mod[0x10];
8509 
8510 	u8         reserved_at_40[0x8];
8511 	u8         transport_domain[0x18];
8512 
8513 	u8         reserved_at_60[0x20];
8514 };
8515 
8516 struct mlx5_ifc_dealloc_q_counter_out_bits {
8517 	u8         status[0x8];
8518 	u8         reserved_at_8[0x18];
8519 
8520 	u8         syndrome[0x20];
8521 
8522 	u8         reserved_at_40[0x40];
8523 };
8524 
8525 struct mlx5_ifc_dealloc_q_counter_in_bits {
8526 	u8         opcode[0x10];
8527 	u8         reserved_at_10[0x10];
8528 
8529 	u8         reserved_at_20[0x10];
8530 	u8         op_mod[0x10];
8531 
8532 	u8         reserved_at_40[0x18];
8533 	u8         counter_set_id[0x8];
8534 
8535 	u8         reserved_at_60[0x20];
8536 };
8537 
8538 struct mlx5_ifc_dealloc_pd_out_bits {
8539 	u8         status[0x8];
8540 	u8         reserved_at_8[0x18];
8541 
8542 	u8         syndrome[0x20];
8543 
8544 	u8         reserved_at_40[0x40];
8545 };
8546 
8547 struct mlx5_ifc_dealloc_pd_in_bits {
8548 	u8         opcode[0x10];
8549 	u8         uid[0x10];
8550 
8551 	u8         reserved_at_20[0x10];
8552 	u8         op_mod[0x10];
8553 
8554 	u8         reserved_at_40[0x8];
8555 	u8         pd[0x18];
8556 
8557 	u8         reserved_at_60[0x20];
8558 };
8559 
8560 struct mlx5_ifc_dealloc_flow_counter_out_bits {
8561 	u8         status[0x8];
8562 	u8         reserved_at_8[0x18];
8563 
8564 	u8         syndrome[0x20];
8565 
8566 	u8         reserved_at_40[0x40];
8567 };
8568 
8569 struct mlx5_ifc_dealloc_flow_counter_in_bits {
8570 	u8         opcode[0x10];
8571 	u8         reserved_at_10[0x10];
8572 
8573 	u8         reserved_at_20[0x10];
8574 	u8         op_mod[0x10];
8575 
8576 	u8         flow_counter_id[0x20];
8577 
8578 	u8         reserved_at_60[0x20];
8579 };
8580 
8581 struct mlx5_ifc_create_xrq_out_bits {
8582 	u8         status[0x8];
8583 	u8         reserved_at_8[0x18];
8584 
8585 	u8         syndrome[0x20];
8586 
8587 	u8         reserved_at_40[0x8];
8588 	u8         xrqn[0x18];
8589 
8590 	u8         reserved_at_60[0x20];
8591 };
8592 
8593 struct mlx5_ifc_create_xrq_in_bits {
8594 	u8         opcode[0x10];
8595 	u8         uid[0x10];
8596 
8597 	u8         reserved_at_20[0x10];
8598 	u8         op_mod[0x10];
8599 
8600 	u8         reserved_at_40[0x40];
8601 
8602 	struct mlx5_ifc_xrqc_bits xrq_context;
8603 };
8604 
8605 struct mlx5_ifc_create_xrc_srq_out_bits {
8606 	u8         status[0x8];
8607 	u8         reserved_at_8[0x18];
8608 
8609 	u8         syndrome[0x20];
8610 
8611 	u8         reserved_at_40[0x8];
8612 	u8         xrc_srqn[0x18];
8613 
8614 	u8         reserved_at_60[0x20];
8615 };
8616 
8617 struct mlx5_ifc_create_xrc_srq_in_bits {
8618 	u8         opcode[0x10];
8619 	u8         uid[0x10];
8620 
8621 	u8         reserved_at_20[0x10];
8622 	u8         op_mod[0x10];
8623 
8624 	u8         reserved_at_40[0x40];
8625 
8626 	struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
8627 
8628 	u8         reserved_at_280[0x60];
8629 
8630 	u8         xrc_srq_umem_valid[0x1];
8631 	u8         reserved_at_2e1[0x1f];
8632 
8633 	u8         reserved_at_300[0x580];
8634 
8635 	u8         pas[][0x40];
8636 };
8637 
8638 struct mlx5_ifc_create_tis_out_bits {
8639 	u8         status[0x8];
8640 	u8         reserved_at_8[0x18];
8641 
8642 	u8         syndrome[0x20];
8643 
8644 	u8         reserved_at_40[0x8];
8645 	u8         tisn[0x18];
8646 
8647 	u8         reserved_at_60[0x20];
8648 };
8649 
8650 struct mlx5_ifc_create_tis_in_bits {
8651 	u8         opcode[0x10];
8652 	u8         uid[0x10];
8653 
8654 	u8         reserved_at_20[0x10];
8655 	u8         op_mod[0x10];
8656 
8657 	u8         reserved_at_40[0xc0];
8658 
8659 	struct mlx5_ifc_tisc_bits ctx;
8660 };
8661 
8662 struct mlx5_ifc_create_tir_out_bits {
8663 	u8         status[0x8];
8664 	u8         icm_address_63_40[0x18];
8665 
8666 	u8         syndrome[0x20];
8667 
8668 	u8         icm_address_39_32[0x8];
8669 	u8         tirn[0x18];
8670 
8671 	u8         icm_address_31_0[0x20];
8672 };
8673 
8674 struct mlx5_ifc_create_tir_in_bits {
8675 	u8         opcode[0x10];
8676 	u8         uid[0x10];
8677 
8678 	u8         reserved_at_20[0x10];
8679 	u8         op_mod[0x10];
8680 
8681 	u8         reserved_at_40[0xc0];
8682 
8683 	struct mlx5_ifc_tirc_bits ctx;
8684 };
8685 
8686 struct mlx5_ifc_create_srq_out_bits {
8687 	u8         status[0x8];
8688 	u8         reserved_at_8[0x18];
8689 
8690 	u8         syndrome[0x20];
8691 
8692 	u8         reserved_at_40[0x8];
8693 	u8         srqn[0x18];
8694 
8695 	u8         reserved_at_60[0x20];
8696 };
8697 
8698 struct mlx5_ifc_create_srq_in_bits {
8699 	u8         opcode[0x10];
8700 	u8         uid[0x10];
8701 
8702 	u8         reserved_at_20[0x10];
8703 	u8         op_mod[0x10];
8704 
8705 	u8         reserved_at_40[0x40];
8706 
8707 	struct mlx5_ifc_srqc_bits srq_context_entry;
8708 
8709 	u8         reserved_at_280[0x600];
8710 
8711 	u8         pas[][0x40];
8712 };
8713 
8714 struct mlx5_ifc_create_sq_out_bits {
8715 	u8         status[0x8];
8716 	u8         reserved_at_8[0x18];
8717 
8718 	u8         syndrome[0x20];
8719 
8720 	u8         reserved_at_40[0x8];
8721 	u8         sqn[0x18];
8722 
8723 	u8         reserved_at_60[0x20];
8724 };
8725 
8726 struct mlx5_ifc_create_sq_in_bits {
8727 	u8         opcode[0x10];
8728 	u8         uid[0x10];
8729 
8730 	u8         reserved_at_20[0x10];
8731 	u8         op_mod[0x10];
8732 
8733 	u8         reserved_at_40[0xc0];
8734 
8735 	struct mlx5_ifc_sqc_bits ctx;
8736 };
8737 
8738 struct mlx5_ifc_create_scheduling_element_out_bits {
8739 	u8         status[0x8];
8740 	u8         reserved_at_8[0x18];
8741 
8742 	u8         syndrome[0x20];
8743 
8744 	u8         reserved_at_40[0x40];
8745 
8746 	u8         scheduling_element_id[0x20];
8747 
8748 	u8         reserved_at_a0[0x160];
8749 };
8750 
8751 struct mlx5_ifc_create_scheduling_element_in_bits {
8752 	u8         opcode[0x10];
8753 	u8         reserved_at_10[0x10];
8754 
8755 	u8         reserved_at_20[0x10];
8756 	u8         op_mod[0x10];
8757 
8758 	u8         scheduling_hierarchy[0x8];
8759 	u8         reserved_at_48[0x18];
8760 
8761 	u8         reserved_at_60[0xa0];
8762 
8763 	struct mlx5_ifc_scheduling_context_bits scheduling_context;
8764 
8765 	u8         reserved_at_300[0x100];
8766 };
8767 
8768 struct mlx5_ifc_create_rqt_out_bits {
8769 	u8         status[0x8];
8770 	u8         reserved_at_8[0x18];
8771 
8772 	u8         syndrome[0x20];
8773 
8774 	u8         reserved_at_40[0x8];
8775 	u8         rqtn[0x18];
8776 
8777 	u8         reserved_at_60[0x20];
8778 };
8779 
8780 struct mlx5_ifc_create_rqt_in_bits {
8781 	u8         opcode[0x10];
8782 	u8         uid[0x10];
8783 
8784 	u8         reserved_at_20[0x10];
8785 	u8         op_mod[0x10];
8786 
8787 	u8         reserved_at_40[0xc0];
8788 
8789 	struct mlx5_ifc_rqtc_bits rqt_context;
8790 };
8791 
8792 struct mlx5_ifc_create_rq_out_bits {
8793 	u8         status[0x8];
8794 	u8         reserved_at_8[0x18];
8795 
8796 	u8         syndrome[0x20];
8797 
8798 	u8         reserved_at_40[0x8];
8799 	u8         rqn[0x18];
8800 
8801 	u8         reserved_at_60[0x20];
8802 };
8803 
8804 struct mlx5_ifc_create_rq_in_bits {
8805 	u8         opcode[0x10];
8806 	u8         uid[0x10];
8807 
8808 	u8         reserved_at_20[0x10];
8809 	u8         op_mod[0x10];
8810 
8811 	u8         reserved_at_40[0xc0];
8812 
8813 	struct mlx5_ifc_rqc_bits ctx;
8814 };
8815 
8816 struct mlx5_ifc_create_rmp_out_bits {
8817 	u8         status[0x8];
8818 	u8         reserved_at_8[0x18];
8819 
8820 	u8         syndrome[0x20];
8821 
8822 	u8         reserved_at_40[0x8];
8823 	u8         rmpn[0x18];
8824 
8825 	u8         reserved_at_60[0x20];
8826 };
8827 
8828 struct mlx5_ifc_create_rmp_in_bits {
8829 	u8         opcode[0x10];
8830 	u8         uid[0x10];
8831 
8832 	u8         reserved_at_20[0x10];
8833 	u8         op_mod[0x10];
8834 
8835 	u8         reserved_at_40[0xc0];
8836 
8837 	struct mlx5_ifc_rmpc_bits ctx;
8838 };
8839 
8840 struct mlx5_ifc_create_qp_out_bits {
8841 	u8         status[0x8];
8842 	u8         reserved_at_8[0x18];
8843 
8844 	u8         syndrome[0x20];
8845 
8846 	u8         reserved_at_40[0x8];
8847 	u8         qpn[0x18];
8848 
8849 	u8         ece[0x20];
8850 };
8851 
8852 struct mlx5_ifc_create_qp_in_bits {
8853 	u8         opcode[0x10];
8854 	u8         uid[0x10];
8855 
8856 	u8         reserved_at_20[0x10];
8857 	u8         op_mod[0x10];
8858 
8859 	u8         qpc_ext[0x1];
8860 	u8         reserved_at_41[0x7];
8861 	u8         input_qpn[0x18];
8862 
8863 	u8         reserved_at_60[0x20];
8864 	u8         opt_param_mask[0x20];
8865 
8866 	u8         ece[0x20];
8867 
8868 	struct mlx5_ifc_qpc_bits qpc;
8869 
8870 	u8         reserved_at_800[0x60];
8871 
8872 	u8         wq_umem_valid[0x1];
8873 	u8         reserved_at_861[0x1f];
8874 
8875 	u8         pas[][0x40];
8876 };
8877 
8878 struct mlx5_ifc_create_psv_out_bits {
8879 	u8         status[0x8];
8880 	u8         reserved_at_8[0x18];
8881 
8882 	u8         syndrome[0x20];
8883 
8884 	u8         reserved_at_40[0x40];
8885 
8886 	u8         reserved_at_80[0x8];
8887 	u8         psv0_index[0x18];
8888 
8889 	u8         reserved_at_a0[0x8];
8890 	u8         psv1_index[0x18];
8891 
8892 	u8         reserved_at_c0[0x8];
8893 	u8         psv2_index[0x18];
8894 
8895 	u8         reserved_at_e0[0x8];
8896 	u8         psv3_index[0x18];
8897 };
8898 
8899 struct mlx5_ifc_create_psv_in_bits {
8900 	u8         opcode[0x10];
8901 	u8         reserved_at_10[0x10];
8902 
8903 	u8         reserved_at_20[0x10];
8904 	u8         op_mod[0x10];
8905 
8906 	u8         num_psv[0x4];
8907 	u8         reserved_at_44[0x4];
8908 	u8         pd[0x18];
8909 
8910 	u8         reserved_at_60[0x20];
8911 };
8912 
8913 struct mlx5_ifc_create_mkey_out_bits {
8914 	u8         status[0x8];
8915 	u8         reserved_at_8[0x18];
8916 
8917 	u8         syndrome[0x20];
8918 
8919 	u8         reserved_at_40[0x8];
8920 	u8         mkey_index[0x18];
8921 
8922 	u8         reserved_at_60[0x20];
8923 };
8924 
8925 struct mlx5_ifc_create_mkey_in_bits {
8926 	u8         opcode[0x10];
8927 	u8         uid[0x10];
8928 
8929 	u8         reserved_at_20[0x10];
8930 	u8         op_mod[0x10];
8931 
8932 	u8         reserved_at_40[0x20];
8933 
8934 	u8         pg_access[0x1];
8935 	u8         mkey_umem_valid[0x1];
8936 	u8         reserved_at_62[0x1e];
8937 
8938 	struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
8939 
8940 	u8         reserved_at_280[0x80];
8941 
8942 	u8         translations_octword_actual_size[0x20];
8943 
8944 	u8         reserved_at_320[0x560];
8945 
8946 	u8         klm_pas_mtt[][0x20];
8947 };
8948 
8949 enum {
8950 	MLX5_FLOW_TABLE_TYPE_NIC_RX		= 0x0,
8951 	MLX5_FLOW_TABLE_TYPE_NIC_TX		= 0x1,
8952 	MLX5_FLOW_TABLE_TYPE_ESW_EGRESS_ACL	= 0x2,
8953 	MLX5_FLOW_TABLE_TYPE_ESW_INGRESS_ACL	= 0x3,
8954 	MLX5_FLOW_TABLE_TYPE_FDB		= 0X4,
8955 	MLX5_FLOW_TABLE_TYPE_SNIFFER_RX		= 0X5,
8956 	MLX5_FLOW_TABLE_TYPE_SNIFFER_TX		= 0X6,
8957 };
8958 
8959 struct mlx5_ifc_create_flow_table_out_bits {
8960 	u8         status[0x8];
8961 	u8         icm_address_63_40[0x18];
8962 
8963 	u8         syndrome[0x20];
8964 
8965 	u8         icm_address_39_32[0x8];
8966 	u8         table_id[0x18];
8967 
8968 	u8         icm_address_31_0[0x20];
8969 };
8970 
8971 struct mlx5_ifc_create_flow_table_in_bits {
8972 	u8         opcode[0x10];
8973 	u8         uid[0x10];
8974 
8975 	u8         reserved_at_20[0x10];
8976 	u8         op_mod[0x10];
8977 
8978 	u8         other_vport[0x1];
8979 	u8         reserved_at_41[0xf];
8980 	u8         vport_number[0x10];
8981 
8982 	u8         reserved_at_60[0x20];
8983 
8984 	u8         table_type[0x8];
8985 	u8         reserved_at_88[0x18];
8986 
8987 	u8         reserved_at_a0[0x20];
8988 
8989 	struct mlx5_ifc_flow_table_context_bits flow_table_context;
8990 };
8991 
8992 struct mlx5_ifc_create_flow_group_out_bits {
8993 	u8         status[0x8];
8994 	u8         reserved_at_8[0x18];
8995 
8996 	u8         syndrome[0x20];
8997 
8998 	u8         reserved_at_40[0x8];
8999 	u8         group_id[0x18];
9000 
9001 	u8         reserved_at_60[0x20];
9002 };
9003 
9004 enum {
9005 	MLX5_CREATE_FLOW_GROUP_IN_GROUP_TYPE_TCAM_SUBTABLE  = 0x0,
9006 	MLX5_CREATE_FLOW_GROUP_IN_GROUP_TYPE_HASH_SPLIT     = 0x1,
9007 };
9008 
9009 enum {
9010 	MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS     = 0x0,
9011 	MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS   = 0x1,
9012 	MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS     = 0x2,
9013 	MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3,
9014 };
9015 
9016 struct mlx5_ifc_create_flow_group_in_bits {
9017 	u8         opcode[0x10];
9018 	u8         reserved_at_10[0x10];
9019 
9020 	u8         reserved_at_20[0x10];
9021 	u8         op_mod[0x10];
9022 
9023 	u8         other_vport[0x1];
9024 	u8         reserved_at_41[0xf];
9025 	u8         vport_number[0x10];
9026 
9027 	u8         reserved_at_60[0x20];
9028 
9029 	u8         table_type[0x8];
9030 	u8         reserved_at_88[0x4];
9031 	u8         group_type[0x4];
9032 	u8         reserved_at_90[0x10];
9033 
9034 	u8         reserved_at_a0[0x8];
9035 	u8         table_id[0x18];
9036 
9037 	u8         source_eswitch_owner_vhca_id_valid[0x1];
9038 
9039 	u8         reserved_at_c1[0x1f];
9040 
9041 	u8         start_flow_index[0x20];
9042 
9043 	u8         reserved_at_100[0x20];
9044 
9045 	u8         end_flow_index[0x20];
9046 
9047 	u8         reserved_at_140[0x10];
9048 	u8         match_definer_id[0x10];
9049 
9050 	u8         reserved_at_160[0x80];
9051 
9052 	u8         reserved_at_1e0[0x18];
9053 	u8         match_criteria_enable[0x8];
9054 
9055 	struct mlx5_ifc_fte_match_param_bits match_criteria;
9056 
9057 	u8         reserved_at_1200[0xe00];
9058 };
9059 
9060 struct mlx5_ifc_create_eq_out_bits {
9061 	u8         status[0x8];
9062 	u8         reserved_at_8[0x18];
9063 
9064 	u8         syndrome[0x20];
9065 
9066 	u8         reserved_at_40[0x18];
9067 	u8         eq_number[0x8];
9068 
9069 	u8         reserved_at_60[0x20];
9070 };
9071 
9072 struct mlx5_ifc_create_eq_in_bits {
9073 	u8         opcode[0x10];
9074 	u8         uid[0x10];
9075 
9076 	u8         reserved_at_20[0x10];
9077 	u8         op_mod[0x10];
9078 
9079 	u8         reserved_at_40[0x40];
9080 
9081 	struct mlx5_ifc_eqc_bits eq_context_entry;
9082 
9083 	u8         reserved_at_280[0x40];
9084 
9085 	u8         event_bitmask[4][0x40];
9086 
9087 	u8         reserved_at_3c0[0x4c0];
9088 
9089 	u8         pas[][0x40];
9090 };
9091 
9092 struct mlx5_ifc_create_dct_out_bits {
9093 	u8         status[0x8];
9094 	u8         reserved_at_8[0x18];
9095 
9096 	u8         syndrome[0x20];
9097 
9098 	u8         reserved_at_40[0x8];
9099 	u8         dctn[0x18];
9100 
9101 	u8         ece[0x20];
9102 };
9103 
9104 struct mlx5_ifc_create_dct_in_bits {
9105 	u8         opcode[0x10];
9106 	u8         uid[0x10];
9107 
9108 	u8         reserved_at_20[0x10];
9109 	u8         op_mod[0x10];
9110 
9111 	u8         reserved_at_40[0x40];
9112 
9113 	struct mlx5_ifc_dctc_bits dct_context_entry;
9114 
9115 	u8         reserved_at_280[0x180];
9116 };
9117 
9118 struct mlx5_ifc_create_cq_out_bits {
9119 	u8         status[0x8];
9120 	u8         reserved_at_8[0x18];
9121 
9122 	u8         syndrome[0x20];
9123 
9124 	u8         reserved_at_40[0x8];
9125 	u8         cqn[0x18];
9126 
9127 	u8         reserved_at_60[0x20];
9128 };
9129 
9130 struct mlx5_ifc_create_cq_in_bits {
9131 	u8         opcode[0x10];
9132 	u8         uid[0x10];
9133 
9134 	u8         reserved_at_20[0x10];
9135 	u8         op_mod[0x10];
9136 
9137 	u8         reserved_at_40[0x40];
9138 
9139 	struct mlx5_ifc_cqc_bits cq_context;
9140 
9141 	u8         reserved_at_280[0x60];
9142 
9143 	u8         cq_umem_valid[0x1];
9144 	u8         reserved_at_2e1[0x59f];
9145 
9146 	u8         pas[][0x40];
9147 };
9148 
9149 struct mlx5_ifc_config_int_moderation_out_bits {
9150 	u8         status[0x8];
9151 	u8         reserved_at_8[0x18];
9152 
9153 	u8         syndrome[0x20];
9154 
9155 	u8         reserved_at_40[0x4];
9156 	u8         min_delay[0xc];
9157 	u8         int_vector[0x10];
9158 
9159 	u8         reserved_at_60[0x20];
9160 };
9161 
9162 enum {
9163 	MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE  = 0x0,
9164 	MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ   = 0x1,
9165 };
9166 
9167 struct mlx5_ifc_config_int_moderation_in_bits {
9168 	u8         opcode[0x10];
9169 	u8         reserved_at_10[0x10];
9170 
9171 	u8         reserved_at_20[0x10];
9172 	u8         op_mod[0x10];
9173 
9174 	u8         reserved_at_40[0x4];
9175 	u8         min_delay[0xc];
9176 	u8         int_vector[0x10];
9177 
9178 	u8         reserved_at_60[0x20];
9179 };
9180 
9181 struct mlx5_ifc_attach_to_mcg_out_bits {
9182 	u8         status[0x8];
9183 	u8         reserved_at_8[0x18];
9184 
9185 	u8         syndrome[0x20];
9186 
9187 	u8         reserved_at_40[0x40];
9188 };
9189 
9190 struct mlx5_ifc_attach_to_mcg_in_bits {
9191 	u8         opcode[0x10];
9192 	u8         uid[0x10];
9193 
9194 	u8         reserved_at_20[0x10];
9195 	u8         op_mod[0x10];
9196 
9197 	u8         reserved_at_40[0x8];
9198 	u8         qpn[0x18];
9199 
9200 	u8         reserved_at_60[0x20];
9201 
9202 	u8         multicast_gid[16][0x8];
9203 };
9204 
9205 struct mlx5_ifc_arm_xrq_out_bits {
9206 	u8         status[0x8];
9207 	u8         reserved_at_8[0x18];
9208 
9209 	u8         syndrome[0x20];
9210 
9211 	u8         reserved_at_40[0x40];
9212 };
9213 
9214 struct mlx5_ifc_arm_xrq_in_bits {
9215 	u8         opcode[0x10];
9216 	u8         reserved_at_10[0x10];
9217 
9218 	u8         reserved_at_20[0x10];
9219 	u8         op_mod[0x10];
9220 
9221 	u8         reserved_at_40[0x8];
9222 	u8         xrqn[0x18];
9223 
9224 	u8         reserved_at_60[0x10];
9225 	u8         lwm[0x10];
9226 };
9227 
9228 struct mlx5_ifc_arm_xrc_srq_out_bits {
9229 	u8         status[0x8];
9230 	u8         reserved_at_8[0x18];
9231 
9232 	u8         syndrome[0x20];
9233 
9234 	u8         reserved_at_40[0x40];
9235 };
9236 
9237 enum {
9238 	MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ  = 0x1,
9239 };
9240 
9241 struct mlx5_ifc_arm_xrc_srq_in_bits {
9242 	u8         opcode[0x10];
9243 	u8         uid[0x10];
9244 
9245 	u8         reserved_at_20[0x10];
9246 	u8         op_mod[0x10];
9247 
9248 	u8         reserved_at_40[0x8];
9249 	u8         xrc_srqn[0x18];
9250 
9251 	u8         reserved_at_60[0x10];
9252 	u8         lwm[0x10];
9253 };
9254 
9255 struct mlx5_ifc_arm_rq_out_bits {
9256 	u8         status[0x8];
9257 	u8         reserved_at_8[0x18];
9258 
9259 	u8         syndrome[0x20];
9260 
9261 	u8         reserved_at_40[0x40];
9262 };
9263 
9264 enum {
9265 	MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1,
9266 	MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2,
9267 };
9268 
9269 struct mlx5_ifc_arm_rq_in_bits {
9270 	u8         opcode[0x10];
9271 	u8         uid[0x10];
9272 
9273 	u8         reserved_at_20[0x10];
9274 	u8         op_mod[0x10];
9275 
9276 	u8         reserved_at_40[0x8];
9277 	u8         srq_number[0x18];
9278 
9279 	u8         reserved_at_60[0x10];
9280 	u8         lwm[0x10];
9281 };
9282 
9283 struct mlx5_ifc_arm_dct_out_bits {
9284 	u8         status[0x8];
9285 	u8         reserved_at_8[0x18];
9286 
9287 	u8         syndrome[0x20];
9288 
9289 	u8         reserved_at_40[0x40];
9290 };
9291 
9292 struct mlx5_ifc_arm_dct_in_bits {
9293 	u8         opcode[0x10];
9294 	u8         reserved_at_10[0x10];
9295 
9296 	u8         reserved_at_20[0x10];
9297 	u8         op_mod[0x10];
9298 
9299 	u8         reserved_at_40[0x8];
9300 	u8         dct_number[0x18];
9301 
9302 	u8         reserved_at_60[0x20];
9303 };
9304 
9305 struct mlx5_ifc_alloc_xrcd_out_bits {
9306 	u8         status[0x8];
9307 	u8         reserved_at_8[0x18];
9308 
9309 	u8         syndrome[0x20];
9310 
9311 	u8         reserved_at_40[0x8];
9312 	u8         xrcd[0x18];
9313 
9314 	u8         reserved_at_60[0x20];
9315 };
9316 
9317 struct mlx5_ifc_alloc_xrcd_in_bits {
9318 	u8         opcode[0x10];
9319 	u8         uid[0x10];
9320 
9321 	u8         reserved_at_20[0x10];
9322 	u8         op_mod[0x10];
9323 
9324 	u8         reserved_at_40[0x40];
9325 };
9326 
9327 struct mlx5_ifc_alloc_uar_out_bits {
9328 	u8         status[0x8];
9329 	u8         reserved_at_8[0x18];
9330 
9331 	u8         syndrome[0x20];
9332 
9333 	u8         reserved_at_40[0x8];
9334 	u8         uar[0x18];
9335 
9336 	u8         reserved_at_60[0x20];
9337 };
9338 
9339 struct mlx5_ifc_alloc_uar_in_bits {
9340 	u8         opcode[0x10];
9341 	u8         uid[0x10];
9342 
9343 	u8         reserved_at_20[0x10];
9344 	u8         op_mod[0x10];
9345 
9346 	u8         reserved_at_40[0x40];
9347 };
9348 
9349 struct mlx5_ifc_alloc_transport_domain_out_bits {
9350 	u8         status[0x8];
9351 	u8         reserved_at_8[0x18];
9352 
9353 	u8         syndrome[0x20];
9354 
9355 	u8         reserved_at_40[0x8];
9356 	u8         transport_domain[0x18];
9357 
9358 	u8         reserved_at_60[0x20];
9359 };
9360 
9361 struct mlx5_ifc_alloc_transport_domain_in_bits {
9362 	u8         opcode[0x10];
9363 	u8         uid[0x10];
9364 
9365 	u8         reserved_at_20[0x10];
9366 	u8         op_mod[0x10];
9367 
9368 	u8         reserved_at_40[0x40];
9369 };
9370 
9371 struct mlx5_ifc_alloc_q_counter_out_bits {
9372 	u8         status[0x8];
9373 	u8         reserved_at_8[0x18];
9374 
9375 	u8         syndrome[0x20];
9376 
9377 	u8         reserved_at_40[0x18];
9378 	u8         counter_set_id[0x8];
9379 
9380 	u8         reserved_at_60[0x20];
9381 };
9382 
9383 struct mlx5_ifc_alloc_q_counter_in_bits {
9384 	u8         opcode[0x10];
9385 	u8         uid[0x10];
9386 
9387 	u8         reserved_at_20[0x10];
9388 	u8         op_mod[0x10];
9389 
9390 	u8         reserved_at_40[0x40];
9391 };
9392 
9393 struct mlx5_ifc_alloc_pd_out_bits {
9394 	u8         status[0x8];
9395 	u8         reserved_at_8[0x18];
9396 
9397 	u8         syndrome[0x20];
9398 
9399 	u8         reserved_at_40[0x8];
9400 	u8         pd[0x18];
9401 
9402 	u8         reserved_at_60[0x20];
9403 };
9404 
9405 struct mlx5_ifc_alloc_pd_in_bits {
9406 	u8         opcode[0x10];
9407 	u8         uid[0x10];
9408 
9409 	u8         reserved_at_20[0x10];
9410 	u8         op_mod[0x10];
9411 
9412 	u8         reserved_at_40[0x40];
9413 };
9414 
9415 struct mlx5_ifc_alloc_flow_counter_out_bits {
9416 	u8         status[0x8];
9417 	u8         reserved_at_8[0x18];
9418 
9419 	u8         syndrome[0x20];
9420 
9421 	u8         flow_counter_id[0x20];
9422 
9423 	u8         reserved_at_60[0x20];
9424 };
9425 
9426 struct mlx5_ifc_alloc_flow_counter_in_bits {
9427 	u8         opcode[0x10];
9428 	u8         reserved_at_10[0x10];
9429 
9430 	u8         reserved_at_20[0x10];
9431 	u8         op_mod[0x10];
9432 
9433 	u8         reserved_at_40[0x33];
9434 	u8         flow_counter_bulk_log_size[0x5];
9435 	u8         flow_counter_bulk[0x8];
9436 };
9437 
9438 struct mlx5_ifc_add_vxlan_udp_dport_out_bits {
9439 	u8         status[0x8];
9440 	u8         reserved_at_8[0x18];
9441 
9442 	u8         syndrome[0x20];
9443 
9444 	u8         reserved_at_40[0x40];
9445 };
9446 
9447 struct mlx5_ifc_add_vxlan_udp_dport_in_bits {
9448 	u8         opcode[0x10];
9449 	u8         reserved_at_10[0x10];
9450 
9451 	u8         reserved_at_20[0x10];
9452 	u8         op_mod[0x10];
9453 
9454 	u8         reserved_at_40[0x20];
9455 
9456 	u8         reserved_at_60[0x10];
9457 	u8         vxlan_udp_port[0x10];
9458 };
9459 
9460 struct mlx5_ifc_set_pp_rate_limit_out_bits {
9461 	u8         status[0x8];
9462 	u8         reserved_at_8[0x18];
9463 
9464 	u8         syndrome[0x20];
9465 
9466 	u8         reserved_at_40[0x40];
9467 };
9468 
9469 struct mlx5_ifc_set_pp_rate_limit_context_bits {
9470 	u8         rate_limit[0x20];
9471 
9472 	u8	   burst_upper_bound[0x20];
9473 
9474 	u8         reserved_at_40[0x10];
9475 	u8	   typical_packet_size[0x10];
9476 
9477 	u8         reserved_at_60[0x120];
9478 };
9479 
9480 struct mlx5_ifc_set_pp_rate_limit_in_bits {
9481 	u8         opcode[0x10];
9482 	u8         uid[0x10];
9483 
9484 	u8         reserved_at_20[0x10];
9485 	u8         op_mod[0x10];
9486 
9487 	u8         reserved_at_40[0x10];
9488 	u8         rate_limit_index[0x10];
9489 
9490 	u8         reserved_at_60[0x20];
9491 
9492 	struct mlx5_ifc_set_pp_rate_limit_context_bits ctx;
9493 };
9494 
9495 struct mlx5_ifc_access_register_out_bits {
9496 	u8         status[0x8];
9497 	u8         reserved_at_8[0x18];
9498 
9499 	u8         syndrome[0x20];
9500 
9501 	u8         reserved_at_40[0x40];
9502 
9503 	u8         register_data[][0x20];
9504 };
9505 
9506 enum {
9507 	MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE  = 0x0,
9508 	MLX5_ACCESS_REGISTER_IN_OP_MOD_READ   = 0x1,
9509 };
9510 
9511 struct mlx5_ifc_access_register_in_bits {
9512 	u8         opcode[0x10];
9513 	u8         reserved_at_10[0x10];
9514 
9515 	u8         reserved_at_20[0x10];
9516 	u8         op_mod[0x10];
9517 
9518 	u8         reserved_at_40[0x10];
9519 	u8         register_id[0x10];
9520 
9521 	u8         argument[0x20];
9522 
9523 	u8         register_data[][0x20];
9524 };
9525 
9526 struct mlx5_ifc_sltp_reg_bits {
9527 	u8         status[0x4];
9528 	u8         version[0x4];
9529 	u8         local_port[0x8];
9530 	u8         pnat[0x2];
9531 	u8         reserved_at_12[0x2];
9532 	u8         lane[0x4];
9533 	u8         reserved_at_18[0x8];
9534 
9535 	u8         reserved_at_20[0x20];
9536 
9537 	u8         reserved_at_40[0x7];
9538 	u8         polarity[0x1];
9539 	u8         ob_tap0[0x8];
9540 	u8         ob_tap1[0x8];
9541 	u8         ob_tap2[0x8];
9542 
9543 	u8         reserved_at_60[0xc];
9544 	u8         ob_preemp_mode[0x4];
9545 	u8         ob_reg[0x8];
9546 	u8         ob_bias[0x8];
9547 
9548 	u8         reserved_at_80[0x20];
9549 };
9550 
9551 struct mlx5_ifc_slrg_reg_bits {
9552 	u8         status[0x4];
9553 	u8         version[0x4];
9554 	u8         local_port[0x8];
9555 	u8         pnat[0x2];
9556 	u8         reserved_at_12[0x2];
9557 	u8         lane[0x4];
9558 	u8         reserved_at_18[0x8];
9559 
9560 	u8         time_to_link_up[0x10];
9561 	u8         reserved_at_30[0xc];
9562 	u8         grade_lane_speed[0x4];
9563 
9564 	u8         grade_version[0x8];
9565 	u8         grade[0x18];
9566 
9567 	u8         reserved_at_60[0x4];
9568 	u8         height_grade_type[0x4];
9569 	u8         height_grade[0x18];
9570 
9571 	u8         height_dz[0x10];
9572 	u8         height_dv[0x10];
9573 
9574 	u8         reserved_at_a0[0x10];
9575 	u8         height_sigma[0x10];
9576 
9577 	u8         reserved_at_c0[0x20];
9578 
9579 	u8         reserved_at_e0[0x4];
9580 	u8         phase_grade_type[0x4];
9581 	u8         phase_grade[0x18];
9582 
9583 	u8         reserved_at_100[0x8];
9584 	u8         phase_eo_pos[0x8];
9585 	u8         reserved_at_110[0x8];
9586 	u8         phase_eo_neg[0x8];
9587 
9588 	u8         ffe_set_tested[0x10];
9589 	u8         test_errors_per_lane[0x10];
9590 };
9591 
9592 struct mlx5_ifc_pvlc_reg_bits {
9593 	u8         reserved_at_0[0x8];
9594 	u8         local_port[0x8];
9595 	u8         reserved_at_10[0x10];
9596 
9597 	u8         reserved_at_20[0x1c];
9598 	u8         vl_hw_cap[0x4];
9599 
9600 	u8         reserved_at_40[0x1c];
9601 	u8         vl_admin[0x4];
9602 
9603 	u8         reserved_at_60[0x1c];
9604 	u8         vl_operational[0x4];
9605 };
9606 
9607 struct mlx5_ifc_pude_reg_bits {
9608 	u8         swid[0x8];
9609 	u8         local_port[0x8];
9610 	u8         reserved_at_10[0x4];
9611 	u8         admin_status[0x4];
9612 	u8         reserved_at_18[0x4];
9613 	u8         oper_status[0x4];
9614 
9615 	u8         reserved_at_20[0x60];
9616 };
9617 
9618 struct mlx5_ifc_ptys_reg_bits {
9619 	u8         reserved_at_0[0x1];
9620 	u8         an_disable_admin[0x1];
9621 	u8         an_disable_cap[0x1];
9622 	u8         reserved_at_3[0x5];
9623 	u8         local_port[0x8];
9624 	u8         reserved_at_10[0xd];
9625 	u8         proto_mask[0x3];
9626 
9627 	u8         an_status[0x4];
9628 	u8         reserved_at_24[0xc];
9629 	u8         data_rate_oper[0x10];
9630 
9631 	u8         ext_eth_proto_capability[0x20];
9632 
9633 	u8         eth_proto_capability[0x20];
9634 
9635 	u8         ib_link_width_capability[0x10];
9636 	u8         ib_proto_capability[0x10];
9637 
9638 	u8         ext_eth_proto_admin[0x20];
9639 
9640 	u8         eth_proto_admin[0x20];
9641 
9642 	u8         ib_link_width_admin[0x10];
9643 	u8         ib_proto_admin[0x10];
9644 
9645 	u8         ext_eth_proto_oper[0x20];
9646 
9647 	u8         eth_proto_oper[0x20];
9648 
9649 	u8         ib_link_width_oper[0x10];
9650 	u8         ib_proto_oper[0x10];
9651 
9652 	u8         reserved_at_160[0x1c];
9653 	u8         connector_type[0x4];
9654 
9655 	u8         eth_proto_lp_advertise[0x20];
9656 
9657 	u8         reserved_at_1a0[0x60];
9658 };
9659 
9660 struct mlx5_ifc_mlcr_reg_bits {
9661 	u8         reserved_at_0[0x8];
9662 	u8         local_port[0x8];
9663 	u8         reserved_at_10[0x20];
9664 
9665 	u8         beacon_duration[0x10];
9666 	u8         reserved_at_40[0x10];
9667 
9668 	u8         beacon_remain[0x10];
9669 };
9670 
9671 struct mlx5_ifc_ptas_reg_bits {
9672 	u8         reserved_at_0[0x20];
9673 
9674 	u8         algorithm_options[0x10];
9675 	u8         reserved_at_30[0x4];
9676 	u8         repetitions_mode[0x4];
9677 	u8         num_of_repetitions[0x8];
9678 
9679 	u8         grade_version[0x8];
9680 	u8         height_grade_type[0x4];
9681 	u8         phase_grade_type[0x4];
9682 	u8         height_grade_weight[0x8];
9683 	u8         phase_grade_weight[0x8];
9684 
9685 	u8         gisim_measure_bits[0x10];
9686 	u8         adaptive_tap_measure_bits[0x10];
9687 
9688 	u8         ber_bath_high_error_threshold[0x10];
9689 	u8         ber_bath_mid_error_threshold[0x10];
9690 
9691 	u8         ber_bath_low_error_threshold[0x10];
9692 	u8         one_ratio_high_threshold[0x10];
9693 
9694 	u8         one_ratio_high_mid_threshold[0x10];
9695 	u8         one_ratio_low_mid_threshold[0x10];
9696 
9697 	u8         one_ratio_low_threshold[0x10];
9698 	u8         ndeo_error_threshold[0x10];
9699 
9700 	u8         mixer_offset_step_size[0x10];
9701 	u8         reserved_at_110[0x8];
9702 	u8         mix90_phase_for_voltage_bath[0x8];
9703 
9704 	u8         mixer_offset_start[0x10];
9705 	u8         mixer_offset_end[0x10];
9706 
9707 	u8         reserved_at_140[0x15];
9708 	u8         ber_test_time[0xb];
9709 };
9710 
9711 struct mlx5_ifc_pspa_reg_bits {
9712 	u8         swid[0x8];
9713 	u8         local_port[0x8];
9714 	u8         sub_port[0x8];
9715 	u8         reserved_at_18[0x8];
9716 
9717 	u8         reserved_at_20[0x20];
9718 };
9719 
9720 struct mlx5_ifc_pqdr_reg_bits {
9721 	u8         reserved_at_0[0x8];
9722 	u8         local_port[0x8];
9723 	u8         reserved_at_10[0x5];
9724 	u8         prio[0x3];
9725 	u8         reserved_at_18[0x6];
9726 	u8         mode[0x2];
9727 
9728 	u8         reserved_at_20[0x20];
9729 
9730 	u8         reserved_at_40[0x10];
9731 	u8         min_threshold[0x10];
9732 
9733 	u8         reserved_at_60[0x10];
9734 	u8         max_threshold[0x10];
9735 
9736 	u8         reserved_at_80[0x10];
9737 	u8         mark_probability_denominator[0x10];
9738 
9739 	u8         reserved_at_a0[0x60];
9740 };
9741 
9742 struct mlx5_ifc_ppsc_reg_bits {
9743 	u8         reserved_at_0[0x8];
9744 	u8         local_port[0x8];
9745 	u8         reserved_at_10[0x10];
9746 
9747 	u8         reserved_at_20[0x60];
9748 
9749 	u8         reserved_at_80[0x1c];
9750 	u8         wrps_admin[0x4];
9751 
9752 	u8         reserved_at_a0[0x1c];
9753 	u8         wrps_status[0x4];
9754 
9755 	u8         reserved_at_c0[0x8];
9756 	u8         up_threshold[0x8];
9757 	u8         reserved_at_d0[0x8];
9758 	u8         down_threshold[0x8];
9759 
9760 	u8         reserved_at_e0[0x20];
9761 
9762 	u8         reserved_at_100[0x1c];
9763 	u8         srps_admin[0x4];
9764 
9765 	u8         reserved_at_120[0x1c];
9766 	u8         srps_status[0x4];
9767 
9768 	u8         reserved_at_140[0x40];
9769 };
9770 
9771 struct mlx5_ifc_pplr_reg_bits {
9772 	u8         reserved_at_0[0x8];
9773 	u8         local_port[0x8];
9774 	u8         reserved_at_10[0x10];
9775 
9776 	u8         reserved_at_20[0x8];
9777 	u8         lb_cap[0x8];
9778 	u8         reserved_at_30[0x8];
9779 	u8         lb_en[0x8];
9780 };
9781 
9782 struct mlx5_ifc_pplm_reg_bits {
9783 	u8         reserved_at_0[0x8];
9784 	u8	   local_port[0x8];
9785 	u8	   reserved_at_10[0x10];
9786 
9787 	u8	   reserved_at_20[0x20];
9788 
9789 	u8	   port_profile_mode[0x8];
9790 	u8	   static_port_profile[0x8];
9791 	u8	   active_port_profile[0x8];
9792 	u8	   reserved_at_58[0x8];
9793 
9794 	u8	   retransmission_active[0x8];
9795 	u8	   fec_mode_active[0x18];
9796 
9797 	u8	   rs_fec_correction_bypass_cap[0x4];
9798 	u8	   reserved_at_84[0x8];
9799 	u8	   fec_override_cap_56g[0x4];
9800 	u8	   fec_override_cap_100g[0x4];
9801 	u8	   fec_override_cap_50g[0x4];
9802 	u8	   fec_override_cap_25g[0x4];
9803 	u8	   fec_override_cap_10g_40g[0x4];
9804 
9805 	u8	   rs_fec_correction_bypass_admin[0x4];
9806 	u8	   reserved_at_a4[0x8];
9807 	u8	   fec_override_admin_56g[0x4];
9808 	u8	   fec_override_admin_100g[0x4];
9809 	u8	   fec_override_admin_50g[0x4];
9810 	u8	   fec_override_admin_25g[0x4];
9811 	u8	   fec_override_admin_10g_40g[0x4];
9812 
9813 	u8         fec_override_cap_400g_8x[0x10];
9814 	u8         fec_override_cap_200g_4x[0x10];
9815 
9816 	u8         fec_override_cap_100g_2x[0x10];
9817 	u8         fec_override_cap_50g_1x[0x10];
9818 
9819 	u8         fec_override_admin_400g_8x[0x10];
9820 	u8         fec_override_admin_200g_4x[0x10];
9821 
9822 	u8         fec_override_admin_100g_2x[0x10];
9823 	u8         fec_override_admin_50g_1x[0x10];
9824 
9825 	u8         fec_override_cap_800g_8x[0x10];
9826 	u8         fec_override_cap_400g_4x[0x10];
9827 
9828 	u8         fec_override_cap_200g_2x[0x10];
9829 	u8         fec_override_cap_100g_1x[0x10];
9830 
9831 	u8         reserved_at_180[0xa0];
9832 
9833 	u8         fec_override_admin_800g_8x[0x10];
9834 	u8         fec_override_admin_400g_4x[0x10];
9835 
9836 	u8         fec_override_admin_200g_2x[0x10];
9837 	u8         fec_override_admin_100g_1x[0x10];
9838 
9839 	u8         reserved_at_260[0x20];
9840 };
9841 
9842 struct mlx5_ifc_ppcnt_reg_bits {
9843 	u8         swid[0x8];
9844 	u8         local_port[0x8];
9845 	u8         pnat[0x2];
9846 	u8         reserved_at_12[0x8];
9847 	u8         grp[0x6];
9848 
9849 	u8         clr[0x1];
9850 	u8         reserved_at_21[0x1c];
9851 	u8         prio_tc[0x3];
9852 
9853 	union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set;
9854 };
9855 
9856 struct mlx5_ifc_mpein_reg_bits {
9857 	u8         reserved_at_0[0x2];
9858 	u8         depth[0x6];
9859 	u8         pcie_index[0x8];
9860 	u8         node[0x8];
9861 	u8         reserved_at_18[0x8];
9862 
9863 	u8         capability_mask[0x20];
9864 
9865 	u8         reserved_at_40[0x8];
9866 	u8         link_width_enabled[0x8];
9867 	u8         link_speed_enabled[0x10];
9868 
9869 	u8         lane0_physical_position[0x8];
9870 	u8         link_width_active[0x8];
9871 	u8         link_speed_active[0x10];
9872 
9873 	u8         num_of_pfs[0x10];
9874 	u8         num_of_vfs[0x10];
9875 
9876 	u8         bdf0[0x10];
9877 	u8         reserved_at_b0[0x10];
9878 
9879 	u8         max_read_request_size[0x4];
9880 	u8         max_payload_size[0x4];
9881 	u8         reserved_at_c8[0x5];
9882 	u8         pwr_status[0x3];
9883 	u8         port_type[0x4];
9884 	u8         reserved_at_d4[0xb];
9885 	u8         lane_reversal[0x1];
9886 
9887 	u8         reserved_at_e0[0x14];
9888 	u8         pci_power[0xc];
9889 
9890 	u8         reserved_at_100[0x20];
9891 
9892 	u8         device_status[0x10];
9893 	u8         port_state[0x8];
9894 	u8         reserved_at_138[0x8];
9895 
9896 	u8         reserved_at_140[0x10];
9897 	u8         receiver_detect_result[0x10];
9898 
9899 	u8         reserved_at_160[0x20];
9900 };
9901 
9902 struct mlx5_ifc_mpcnt_reg_bits {
9903 	u8         reserved_at_0[0x8];
9904 	u8         pcie_index[0x8];
9905 	u8         reserved_at_10[0xa];
9906 	u8         grp[0x6];
9907 
9908 	u8         clr[0x1];
9909 	u8         reserved_at_21[0x1f];
9910 
9911 	union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set;
9912 };
9913 
9914 struct mlx5_ifc_ppad_reg_bits {
9915 	u8         reserved_at_0[0x3];
9916 	u8         single_mac[0x1];
9917 	u8         reserved_at_4[0x4];
9918 	u8         local_port[0x8];
9919 	u8         mac_47_32[0x10];
9920 
9921 	u8         mac_31_0[0x20];
9922 
9923 	u8         reserved_at_40[0x40];
9924 };
9925 
9926 struct mlx5_ifc_pmtu_reg_bits {
9927 	u8         reserved_at_0[0x8];
9928 	u8         local_port[0x8];
9929 	u8         reserved_at_10[0x10];
9930 
9931 	u8         max_mtu[0x10];
9932 	u8         reserved_at_30[0x10];
9933 
9934 	u8         admin_mtu[0x10];
9935 	u8         reserved_at_50[0x10];
9936 
9937 	u8         oper_mtu[0x10];
9938 	u8         reserved_at_70[0x10];
9939 };
9940 
9941 struct mlx5_ifc_pmpr_reg_bits {
9942 	u8         reserved_at_0[0x8];
9943 	u8         module[0x8];
9944 	u8         reserved_at_10[0x10];
9945 
9946 	u8         reserved_at_20[0x18];
9947 	u8         attenuation_5g[0x8];
9948 
9949 	u8         reserved_at_40[0x18];
9950 	u8         attenuation_7g[0x8];
9951 
9952 	u8         reserved_at_60[0x18];
9953 	u8         attenuation_12g[0x8];
9954 };
9955 
9956 struct mlx5_ifc_pmpe_reg_bits {
9957 	u8         reserved_at_0[0x8];
9958 	u8         module[0x8];
9959 	u8         reserved_at_10[0xc];
9960 	u8         module_status[0x4];
9961 
9962 	u8         reserved_at_20[0x60];
9963 };
9964 
9965 struct mlx5_ifc_pmpc_reg_bits {
9966 	u8         module_state_updated[32][0x8];
9967 };
9968 
9969 struct mlx5_ifc_pmlpn_reg_bits {
9970 	u8         reserved_at_0[0x4];
9971 	u8         mlpn_status[0x4];
9972 	u8         local_port[0x8];
9973 	u8         reserved_at_10[0x10];
9974 
9975 	u8         e[0x1];
9976 	u8         reserved_at_21[0x1f];
9977 };
9978 
9979 struct mlx5_ifc_pmlp_reg_bits {
9980 	u8         rxtx[0x1];
9981 	u8         reserved_at_1[0x7];
9982 	u8         local_port[0x8];
9983 	u8         reserved_at_10[0x8];
9984 	u8         width[0x8];
9985 
9986 	u8         lane0_module_mapping[0x20];
9987 
9988 	u8         lane1_module_mapping[0x20];
9989 
9990 	u8         lane2_module_mapping[0x20];
9991 
9992 	u8         lane3_module_mapping[0x20];
9993 
9994 	u8         reserved_at_a0[0x160];
9995 };
9996 
9997 struct mlx5_ifc_pmaos_reg_bits {
9998 	u8         reserved_at_0[0x8];
9999 	u8         module[0x8];
10000 	u8         reserved_at_10[0x4];
10001 	u8         admin_status[0x4];
10002 	u8         reserved_at_18[0x4];
10003 	u8         oper_status[0x4];
10004 
10005 	u8         ase[0x1];
10006 	u8         ee[0x1];
10007 	u8         reserved_at_22[0x1c];
10008 	u8         e[0x2];
10009 
10010 	u8         reserved_at_40[0x40];
10011 };
10012 
10013 struct mlx5_ifc_plpc_reg_bits {
10014 	u8         reserved_at_0[0x4];
10015 	u8         profile_id[0xc];
10016 	u8         reserved_at_10[0x4];
10017 	u8         proto_mask[0x4];
10018 	u8         reserved_at_18[0x8];
10019 
10020 	u8         reserved_at_20[0x10];
10021 	u8         lane_speed[0x10];
10022 
10023 	u8         reserved_at_40[0x17];
10024 	u8         lpbf[0x1];
10025 	u8         fec_mode_policy[0x8];
10026 
10027 	u8         retransmission_capability[0x8];
10028 	u8         fec_mode_capability[0x18];
10029 
10030 	u8         retransmission_support_admin[0x8];
10031 	u8         fec_mode_support_admin[0x18];
10032 
10033 	u8         retransmission_request_admin[0x8];
10034 	u8         fec_mode_request_admin[0x18];
10035 
10036 	u8         reserved_at_c0[0x80];
10037 };
10038 
10039 struct mlx5_ifc_plib_reg_bits {
10040 	u8         reserved_at_0[0x8];
10041 	u8         local_port[0x8];
10042 	u8         reserved_at_10[0x8];
10043 	u8         ib_port[0x8];
10044 
10045 	u8         reserved_at_20[0x60];
10046 };
10047 
10048 struct mlx5_ifc_plbf_reg_bits {
10049 	u8         reserved_at_0[0x8];
10050 	u8         local_port[0x8];
10051 	u8         reserved_at_10[0xd];
10052 	u8         lbf_mode[0x3];
10053 
10054 	u8         reserved_at_20[0x20];
10055 };
10056 
10057 struct mlx5_ifc_pipg_reg_bits {
10058 	u8         reserved_at_0[0x8];
10059 	u8         local_port[0x8];
10060 	u8         reserved_at_10[0x10];
10061 
10062 	u8         dic[0x1];
10063 	u8         reserved_at_21[0x19];
10064 	u8         ipg[0x4];
10065 	u8         reserved_at_3e[0x2];
10066 };
10067 
10068 struct mlx5_ifc_pifr_reg_bits {
10069 	u8         reserved_at_0[0x8];
10070 	u8         local_port[0x8];
10071 	u8         reserved_at_10[0x10];
10072 
10073 	u8         reserved_at_20[0xe0];
10074 
10075 	u8         port_filter[8][0x20];
10076 
10077 	u8         port_filter_update_en[8][0x20];
10078 };
10079 
10080 struct mlx5_ifc_pfcc_reg_bits {
10081 	u8         reserved_at_0[0x8];
10082 	u8         local_port[0x8];
10083 	u8         reserved_at_10[0xb];
10084 	u8         ppan_mask_n[0x1];
10085 	u8         minor_stall_mask[0x1];
10086 	u8         critical_stall_mask[0x1];
10087 	u8         reserved_at_1e[0x2];
10088 
10089 	u8         ppan[0x4];
10090 	u8         reserved_at_24[0x4];
10091 	u8         prio_mask_tx[0x8];
10092 	u8         reserved_at_30[0x8];
10093 	u8         prio_mask_rx[0x8];
10094 
10095 	u8         pptx[0x1];
10096 	u8         aptx[0x1];
10097 	u8         pptx_mask_n[0x1];
10098 	u8         reserved_at_43[0x5];
10099 	u8         pfctx[0x8];
10100 	u8         reserved_at_50[0x10];
10101 
10102 	u8         pprx[0x1];
10103 	u8         aprx[0x1];
10104 	u8         pprx_mask_n[0x1];
10105 	u8         reserved_at_63[0x5];
10106 	u8         pfcrx[0x8];
10107 	u8         reserved_at_70[0x10];
10108 
10109 	u8         device_stall_minor_watermark[0x10];
10110 	u8         device_stall_critical_watermark[0x10];
10111 
10112 	u8         reserved_at_a0[0x60];
10113 };
10114 
10115 struct mlx5_ifc_pelc_reg_bits {
10116 	u8         op[0x4];
10117 	u8         reserved_at_4[0x4];
10118 	u8         local_port[0x8];
10119 	u8         reserved_at_10[0x10];
10120 
10121 	u8         op_admin[0x8];
10122 	u8         op_capability[0x8];
10123 	u8         op_request[0x8];
10124 	u8         op_active[0x8];
10125 
10126 	u8         admin[0x40];
10127 
10128 	u8         capability[0x40];
10129 
10130 	u8         request[0x40];
10131 
10132 	u8         active[0x40];
10133 
10134 	u8         reserved_at_140[0x80];
10135 };
10136 
10137 struct mlx5_ifc_peir_reg_bits {
10138 	u8         reserved_at_0[0x8];
10139 	u8         local_port[0x8];
10140 	u8         reserved_at_10[0x10];
10141 
10142 	u8         reserved_at_20[0xc];
10143 	u8         error_count[0x4];
10144 	u8         reserved_at_30[0x10];
10145 
10146 	u8         reserved_at_40[0xc];
10147 	u8         lane[0x4];
10148 	u8         reserved_at_50[0x8];
10149 	u8         error_type[0x8];
10150 };
10151 
10152 struct mlx5_ifc_mpegc_reg_bits {
10153 	u8         reserved_at_0[0x30];
10154 	u8         field_select[0x10];
10155 
10156 	u8         tx_overflow_sense[0x1];
10157 	u8         mark_cqe[0x1];
10158 	u8         mark_cnp[0x1];
10159 	u8         reserved_at_43[0x1b];
10160 	u8         tx_lossy_overflow_oper[0x2];
10161 
10162 	u8         reserved_at_60[0x100];
10163 };
10164 
10165 struct mlx5_ifc_mpir_reg_bits {
10166 	u8         sdm[0x1];
10167 	u8         reserved_at_1[0x1b];
10168 	u8         host_buses[0x4];
10169 
10170 	u8         reserved_at_20[0x20];
10171 
10172 	u8         local_port[0x8];
10173 	u8         reserved_at_28[0x18];
10174 
10175 	u8         reserved_at_60[0x20];
10176 };
10177 
10178 enum {
10179 	MLX5_MTUTC_FREQ_ADJ_UNITS_PPB          = 0x0,
10180 	MLX5_MTUTC_FREQ_ADJ_UNITS_SCALED_PPM   = 0x1,
10181 };
10182 
10183 enum {
10184 	MLX5_MTUTC_OPERATION_SET_TIME_IMMEDIATE   = 0x1,
10185 	MLX5_MTUTC_OPERATION_ADJUST_TIME          = 0x2,
10186 	MLX5_MTUTC_OPERATION_ADJUST_FREQ_UTC      = 0x3,
10187 };
10188 
10189 struct mlx5_ifc_mtutc_reg_bits {
10190 	u8         reserved_at_0[0x5];
10191 	u8         freq_adj_units[0x3];
10192 	u8         reserved_at_8[0x3];
10193 	u8         log_max_freq_adjustment[0x5];
10194 
10195 	u8         reserved_at_10[0xc];
10196 	u8         operation[0x4];
10197 
10198 	u8         freq_adjustment[0x20];
10199 
10200 	u8         reserved_at_40[0x40];
10201 
10202 	u8         utc_sec[0x20];
10203 
10204 	u8         reserved_at_a0[0x2];
10205 	u8         utc_nsec[0x1e];
10206 
10207 	u8         time_adjustment[0x20];
10208 };
10209 
10210 struct mlx5_ifc_pcam_enhanced_features_bits {
10211 	u8         reserved_at_0[0x48];
10212 	u8         fec_100G_per_lane_in_pplm[0x1];
10213 	u8         reserved_at_49[0x1f];
10214 	u8         fec_50G_per_lane_in_pplm[0x1];
10215 	u8         reserved_at_69[0x4];
10216 	u8         rx_icrc_encapsulated_counter[0x1];
10217 	u8	   reserved_at_6e[0x4];
10218 	u8         ptys_extended_ethernet[0x1];
10219 	u8	   reserved_at_73[0x3];
10220 	u8         pfcc_mask[0x1];
10221 	u8         reserved_at_77[0x3];
10222 	u8         per_lane_error_counters[0x1];
10223 	u8         rx_buffer_fullness_counters[0x1];
10224 	u8         ptys_connector_type[0x1];
10225 	u8         reserved_at_7d[0x1];
10226 	u8         ppcnt_discard_group[0x1];
10227 	u8         ppcnt_statistical_group[0x1];
10228 };
10229 
10230 struct mlx5_ifc_pcam_regs_5000_to_507f_bits {
10231 	u8         port_access_reg_cap_mask_127_to_96[0x20];
10232 	u8         port_access_reg_cap_mask_95_to_64[0x20];
10233 
10234 	u8         port_access_reg_cap_mask_63_to_36[0x1c];
10235 	u8         pplm[0x1];
10236 	u8         port_access_reg_cap_mask_34_to_32[0x3];
10237 
10238 	u8         port_access_reg_cap_mask_31_to_13[0x13];
10239 	u8         pbmc[0x1];
10240 	u8         pptb[0x1];
10241 	u8         port_access_reg_cap_mask_10_to_09[0x2];
10242 	u8         ppcnt[0x1];
10243 	u8         port_access_reg_cap_mask_07_to_00[0x8];
10244 };
10245 
10246 struct mlx5_ifc_pcam_reg_bits {
10247 	u8         reserved_at_0[0x8];
10248 	u8         feature_group[0x8];
10249 	u8         reserved_at_10[0x8];
10250 	u8         access_reg_group[0x8];
10251 
10252 	u8         reserved_at_20[0x20];
10253 
10254 	union {
10255 		struct mlx5_ifc_pcam_regs_5000_to_507f_bits regs_5000_to_507f;
10256 		u8         reserved_at_0[0x80];
10257 	} port_access_reg_cap_mask;
10258 
10259 	u8         reserved_at_c0[0x80];
10260 
10261 	union {
10262 		struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features;
10263 		u8         reserved_at_0[0x80];
10264 	} feature_cap_mask;
10265 
10266 	u8         reserved_at_1c0[0xc0];
10267 };
10268 
10269 struct mlx5_ifc_mcam_enhanced_features_bits {
10270 	u8         reserved_at_0[0x50];
10271 	u8         mtutc_freq_adj_units[0x1];
10272 	u8         mtutc_time_adjustment_extended_range[0x1];
10273 	u8         reserved_at_52[0xb];
10274 	u8         mcia_32dwords[0x1];
10275 	u8         out_pulse_duration_ns[0x1];
10276 	u8         npps_period[0x1];
10277 	u8         reserved_at_60[0xa];
10278 	u8         reset_state[0x1];
10279 	u8         ptpcyc2realtime_modify[0x1];
10280 	u8         reserved_at_6c[0x2];
10281 	u8         pci_status_and_power[0x1];
10282 	u8         reserved_at_6f[0x5];
10283 	u8         mark_tx_action_cnp[0x1];
10284 	u8         mark_tx_action_cqe[0x1];
10285 	u8         dynamic_tx_overflow[0x1];
10286 	u8         reserved_at_77[0x4];
10287 	u8         pcie_outbound_stalled[0x1];
10288 	u8         tx_overflow_buffer_pkt[0x1];
10289 	u8         mtpps_enh_out_per_adj[0x1];
10290 	u8         mtpps_fs[0x1];
10291 	u8         pcie_performance_group[0x1];
10292 };
10293 
10294 struct mlx5_ifc_mcam_access_reg_bits {
10295 	u8         reserved_at_0[0x1c];
10296 	u8         mcda[0x1];
10297 	u8         mcc[0x1];
10298 	u8         mcqi[0x1];
10299 	u8         mcqs[0x1];
10300 
10301 	u8         regs_95_to_90[0x6];
10302 	u8         mpir[0x1];
10303 	u8         regs_88_to_87[0x2];
10304 	u8         mpegc[0x1];
10305 	u8         mtutc[0x1];
10306 	u8         regs_84_to_68[0x11];
10307 	u8         tracer_registers[0x4];
10308 
10309 	u8         regs_63_to_46[0x12];
10310 	u8         mrtc[0x1];
10311 	u8         regs_44_to_41[0x4];
10312 	u8         mfrl[0x1];
10313 	u8         regs_39_to_32[0x8];
10314 
10315 	u8         regs_31_to_11[0x15];
10316 	u8         mtmp[0x1];
10317 	u8         regs_9_to_0[0xa];
10318 };
10319 
10320 struct mlx5_ifc_mcam_access_reg_bits1 {
10321 	u8         regs_127_to_96[0x20];
10322 
10323 	u8         regs_95_to_64[0x20];
10324 
10325 	u8         regs_63_to_32[0x20];
10326 
10327 	u8         regs_31_to_0[0x20];
10328 };
10329 
10330 struct mlx5_ifc_mcam_access_reg_bits2 {
10331 	u8         regs_127_to_99[0x1d];
10332 	u8         mirc[0x1];
10333 	u8         regs_97_to_96[0x2];
10334 
10335 	u8         regs_95_to_87[0x09];
10336 	u8         synce_registers[0x2];
10337 	u8         regs_84_to_64[0x15];
10338 
10339 	u8         regs_63_to_32[0x20];
10340 
10341 	u8         regs_31_to_0[0x20];
10342 };
10343 
10344 struct mlx5_ifc_mcam_reg_bits {
10345 	u8         reserved_at_0[0x8];
10346 	u8         feature_group[0x8];
10347 	u8         reserved_at_10[0x8];
10348 	u8         access_reg_group[0x8];
10349 
10350 	u8         reserved_at_20[0x20];
10351 
10352 	union {
10353 		struct mlx5_ifc_mcam_access_reg_bits access_regs;
10354 		struct mlx5_ifc_mcam_access_reg_bits1 access_regs1;
10355 		struct mlx5_ifc_mcam_access_reg_bits2 access_regs2;
10356 		u8         reserved_at_0[0x80];
10357 	} mng_access_reg_cap_mask;
10358 
10359 	u8         reserved_at_c0[0x80];
10360 
10361 	union {
10362 		struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features;
10363 		u8         reserved_at_0[0x80];
10364 	} mng_feature_cap_mask;
10365 
10366 	u8         reserved_at_1c0[0x80];
10367 };
10368 
10369 struct mlx5_ifc_qcam_access_reg_cap_mask {
10370 	u8         qcam_access_reg_cap_mask_127_to_20[0x6C];
10371 	u8         qpdpm[0x1];
10372 	u8         qcam_access_reg_cap_mask_18_to_4[0x0F];
10373 	u8         qdpm[0x1];
10374 	u8         qpts[0x1];
10375 	u8         qcap[0x1];
10376 	u8         qcam_access_reg_cap_mask_0[0x1];
10377 };
10378 
10379 struct mlx5_ifc_qcam_qos_feature_cap_mask {
10380 	u8         qcam_qos_feature_cap_mask_127_to_1[0x7F];
10381 	u8         qpts_trust_both[0x1];
10382 };
10383 
10384 struct mlx5_ifc_qcam_reg_bits {
10385 	u8         reserved_at_0[0x8];
10386 	u8         feature_group[0x8];
10387 	u8         reserved_at_10[0x8];
10388 	u8         access_reg_group[0x8];
10389 	u8         reserved_at_20[0x20];
10390 
10391 	union {
10392 		struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap;
10393 		u8  reserved_at_0[0x80];
10394 	} qos_access_reg_cap_mask;
10395 
10396 	u8         reserved_at_c0[0x80];
10397 
10398 	union {
10399 		struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap;
10400 		u8  reserved_at_0[0x80];
10401 	} qos_feature_cap_mask;
10402 
10403 	u8         reserved_at_1c0[0x80];
10404 };
10405 
10406 struct mlx5_ifc_core_dump_reg_bits {
10407 	u8         reserved_at_0[0x18];
10408 	u8         core_dump_type[0x8];
10409 
10410 	u8         reserved_at_20[0x30];
10411 	u8         vhca_id[0x10];
10412 
10413 	u8         reserved_at_60[0x8];
10414 	u8         qpn[0x18];
10415 	u8         reserved_at_80[0x180];
10416 };
10417 
10418 struct mlx5_ifc_pcap_reg_bits {
10419 	u8         reserved_at_0[0x8];
10420 	u8         local_port[0x8];
10421 	u8         reserved_at_10[0x10];
10422 
10423 	u8         port_capability_mask[4][0x20];
10424 };
10425 
10426 struct mlx5_ifc_paos_reg_bits {
10427 	u8         swid[0x8];
10428 	u8         local_port[0x8];
10429 	u8         reserved_at_10[0x4];
10430 	u8         admin_status[0x4];
10431 	u8         reserved_at_18[0x4];
10432 	u8         oper_status[0x4];
10433 
10434 	u8         ase[0x1];
10435 	u8         ee[0x1];
10436 	u8         reserved_at_22[0x1c];
10437 	u8         e[0x2];
10438 
10439 	u8         reserved_at_40[0x40];
10440 };
10441 
10442 struct mlx5_ifc_pamp_reg_bits {
10443 	u8         reserved_at_0[0x8];
10444 	u8         opamp_group[0x8];
10445 	u8         reserved_at_10[0xc];
10446 	u8         opamp_group_type[0x4];
10447 
10448 	u8         start_index[0x10];
10449 	u8         reserved_at_30[0x4];
10450 	u8         num_of_indices[0xc];
10451 
10452 	u8         index_data[18][0x10];
10453 };
10454 
10455 struct mlx5_ifc_pcmr_reg_bits {
10456 	u8         reserved_at_0[0x8];
10457 	u8         local_port[0x8];
10458 	u8         reserved_at_10[0x10];
10459 
10460 	u8         entropy_force_cap[0x1];
10461 	u8         entropy_calc_cap[0x1];
10462 	u8         entropy_gre_calc_cap[0x1];
10463 	u8         reserved_at_23[0xf];
10464 	u8         rx_ts_over_crc_cap[0x1];
10465 	u8         reserved_at_33[0xb];
10466 	u8         fcs_cap[0x1];
10467 	u8         reserved_at_3f[0x1];
10468 
10469 	u8         entropy_force[0x1];
10470 	u8         entropy_calc[0x1];
10471 	u8         entropy_gre_calc[0x1];
10472 	u8         reserved_at_43[0xf];
10473 	u8         rx_ts_over_crc[0x1];
10474 	u8         reserved_at_53[0xb];
10475 	u8         fcs_chk[0x1];
10476 	u8         reserved_at_5f[0x1];
10477 };
10478 
10479 struct mlx5_ifc_lane_2_module_mapping_bits {
10480 	u8         reserved_at_0[0x4];
10481 	u8         rx_lane[0x4];
10482 	u8         reserved_at_8[0x4];
10483 	u8         tx_lane[0x4];
10484 	u8         reserved_at_10[0x8];
10485 	u8         module[0x8];
10486 };
10487 
10488 struct mlx5_ifc_bufferx_reg_bits {
10489 	u8         reserved_at_0[0x6];
10490 	u8         lossy[0x1];
10491 	u8         epsb[0x1];
10492 	u8         reserved_at_8[0x8];
10493 	u8         size[0x10];
10494 
10495 	u8         xoff_threshold[0x10];
10496 	u8         xon_threshold[0x10];
10497 };
10498 
10499 struct mlx5_ifc_set_node_in_bits {
10500 	u8         node_description[64][0x8];
10501 };
10502 
10503 struct mlx5_ifc_register_power_settings_bits {
10504 	u8         reserved_at_0[0x18];
10505 	u8         power_settings_level[0x8];
10506 
10507 	u8         reserved_at_20[0x60];
10508 };
10509 
10510 struct mlx5_ifc_register_host_endianness_bits {
10511 	u8         he[0x1];
10512 	u8         reserved_at_1[0x1f];
10513 
10514 	u8         reserved_at_20[0x60];
10515 };
10516 
10517 struct mlx5_ifc_umr_pointer_desc_argument_bits {
10518 	u8         reserved_at_0[0x20];
10519 
10520 	u8         mkey[0x20];
10521 
10522 	u8         addressh_63_32[0x20];
10523 
10524 	u8         addressl_31_0[0x20];
10525 };
10526 
10527 struct mlx5_ifc_ud_adrs_vector_bits {
10528 	u8         dc_key[0x40];
10529 
10530 	u8         ext[0x1];
10531 	u8         reserved_at_41[0x7];
10532 	u8         destination_qp_dct[0x18];
10533 
10534 	u8         static_rate[0x4];
10535 	u8         sl_eth_prio[0x4];
10536 	u8         fl[0x1];
10537 	u8         mlid[0x7];
10538 	u8         rlid_udp_sport[0x10];
10539 
10540 	u8         reserved_at_80[0x20];
10541 
10542 	u8         rmac_47_16[0x20];
10543 
10544 	u8         rmac_15_0[0x10];
10545 	u8         tclass[0x8];
10546 	u8         hop_limit[0x8];
10547 
10548 	u8         reserved_at_e0[0x1];
10549 	u8         grh[0x1];
10550 	u8         reserved_at_e2[0x2];
10551 	u8         src_addr_index[0x8];
10552 	u8         flow_label[0x14];
10553 
10554 	u8         rgid_rip[16][0x8];
10555 };
10556 
10557 struct mlx5_ifc_pages_req_event_bits {
10558 	u8         reserved_at_0[0x10];
10559 	u8         function_id[0x10];
10560 
10561 	u8         num_pages[0x20];
10562 
10563 	u8         reserved_at_40[0xa0];
10564 };
10565 
10566 struct mlx5_ifc_eqe_bits {
10567 	u8         reserved_at_0[0x8];
10568 	u8         event_type[0x8];
10569 	u8         reserved_at_10[0x8];
10570 	u8         event_sub_type[0x8];
10571 
10572 	u8         reserved_at_20[0xe0];
10573 
10574 	union mlx5_ifc_event_auto_bits event_data;
10575 
10576 	u8         reserved_at_1e0[0x10];
10577 	u8         signature[0x8];
10578 	u8         reserved_at_1f8[0x7];
10579 	u8         owner[0x1];
10580 };
10581 
10582 enum {
10583 	MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT  = 0x7,
10584 };
10585 
10586 struct mlx5_ifc_cmd_queue_entry_bits {
10587 	u8         type[0x8];
10588 	u8         reserved_at_8[0x18];
10589 
10590 	u8         input_length[0x20];
10591 
10592 	u8         input_mailbox_pointer_63_32[0x20];
10593 
10594 	u8         input_mailbox_pointer_31_9[0x17];
10595 	u8         reserved_at_77[0x9];
10596 
10597 	u8         command_input_inline_data[16][0x8];
10598 
10599 	u8         command_output_inline_data[16][0x8];
10600 
10601 	u8         output_mailbox_pointer_63_32[0x20];
10602 
10603 	u8         output_mailbox_pointer_31_9[0x17];
10604 	u8         reserved_at_1b7[0x9];
10605 
10606 	u8         output_length[0x20];
10607 
10608 	u8         token[0x8];
10609 	u8         signature[0x8];
10610 	u8         reserved_at_1f0[0x8];
10611 	u8         status[0x7];
10612 	u8         ownership[0x1];
10613 };
10614 
10615 struct mlx5_ifc_cmd_out_bits {
10616 	u8         status[0x8];
10617 	u8         reserved_at_8[0x18];
10618 
10619 	u8         syndrome[0x20];
10620 
10621 	u8         command_output[0x20];
10622 };
10623 
10624 struct mlx5_ifc_cmd_in_bits {
10625 	u8         opcode[0x10];
10626 	u8         reserved_at_10[0x10];
10627 
10628 	u8         reserved_at_20[0x10];
10629 	u8         op_mod[0x10];
10630 
10631 	u8         command[][0x20];
10632 };
10633 
10634 struct mlx5_ifc_cmd_if_box_bits {
10635 	u8         mailbox_data[512][0x8];
10636 
10637 	u8         reserved_at_1000[0x180];
10638 
10639 	u8         next_pointer_63_32[0x20];
10640 
10641 	u8         next_pointer_31_10[0x16];
10642 	u8         reserved_at_11b6[0xa];
10643 
10644 	u8         block_number[0x20];
10645 
10646 	u8         reserved_at_11e0[0x8];
10647 	u8         token[0x8];
10648 	u8         ctrl_signature[0x8];
10649 	u8         signature[0x8];
10650 };
10651 
10652 struct mlx5_ifc_mtt_bits {
10653 	u8         ptag_63_32[0x20];
10654 
10655 	u8         ptag_31_8[0x18];
10656 	u8         reserved_at_38[0x6];
10657 	u8         wr_en[0x1];
10658 	u8         rd_en[0x1];
10659 };
10660 
10661 struct mlx5_ifc_query_wol_rol_out_bits {
10662 	u8         status[0x8];
10663 	u8         reserved_at_8[0x18];
10664 
10665 	u8         syndrome[0x20];
10666 
10667 	u8         reserved_at_40[0x10];
10668 	u8         rol_mode[0x8];
10669 	u8         wol_mode[0x8];
10670 
10671 	u8         reserved_at_60[0x20];
10672 };
10673 
10674 struct mlx5_ifc_query_wol_rol_in_bits {
10675 	u8         opcode[0x10];
10676 	u8         reserved_at_10[0x10];
10677 
10678 	u8         reserved_at_20[0x10];
10679 	u8         op_mod[0x10];
10680 
10681 	u8         reserved_at_40[0x40];
10682 };
10683 
10684 struct mlx5_ifc_set_wol_rol_out_bits {
10685 	u8         status[0x8];
10686 	u8         reserved_at_8[0x18];
10687 
10688 	u8         syndrome[0x20];
10689 
10690 	u8         reserved_at_40[0x40];
10691 };
10692 
10693 struct mlx5_ifc_set_wol_rol_in_bits {
10694 	u8         opcode[0x10];
10695 	u8         reserved_at_10[0x10];
10696 
10697 	u8         reserved_at_20[0x10];
10698 	u8         op_mod[0x10];
10699 
10700 	u8         rol_mode_valid[0x1];
10701 	u8         wol_mode_valid[0x1];
10702 	u8         reserved_at_42[0xe];
10703 	u8         rol_mode[0x8];
10704 	u8         wol_mode[0x8];
10705 
10706 	u8         reserved_at_60[0x20];
10707 };
10708 
10709 enum {
10710 	MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER  = 0x0,
10711 	MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED     = 0x1,
10712 	MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC  = 0x2,
10713 	MLX5_INITIAL_SEG_NIC_INTERFACE_SW_RESET     = 0x7,
10714 };
10715 
10716 enum {
10717 	MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER  = 0x0,
10718 	MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED     = 0x1,
10719 	MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC  = 0x2,
10720 };
10721 
10722 enum {
10723 	MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR              = 0x1,
10724 	MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC                   = 0x7,
10725 	MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR                 = 0x8,
10726 	MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR                   = 0x9,
10727 	MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR            = 0xa,
10728 	MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR                 = 0xb,
10729 	MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN  = 0xc,
10730 	MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR                    = 0xd,
10731 	MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV                       = 0xe,
10732 	MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR                    = 0xf,
10733 	MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR                = 0x10,
10734 	MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PCI_POISONED_ERR         = 0x12,
10735 };
10736 
10737 struct mlx5_ifc_initial_seg_bits {
10738 	u8         fw_rev_minor[0x10];
10739 	u8         fw_rev_major[0x10];
10740 
10741 	u8         cmd_interface_rev[0x10];
10742 	u8         fw_rev_subminor[0x10];
10743 
10744 	u8         reserved_at_40[0x40];
10745 
10746 	u8         cmdq_phy_addr_63_32[0x20];
10747 
10748 	u8         cmdq_phy_addr_31_12[0x14];
10749 	u8         reserved_at_b4[0x2];
10750 	u8         nic_interface[0x2];
10751 	u8         log_cmdq_size[0x4];
10752 	u8         log_cmdq_stride[0x4];
10753 
10754 	u8         command_doorbell_vector[0x20];
10755 
10756 	u8         reserved_at_e0[0xf00];
10757 
10758 	u8         initializing[0x1];
10759 	u8         reserved_at_fe1[0x4];
10760 	u8         nic_interface_supported[0x3];
10761 	u8         embedded_cpu[0x1];
10762 	u8         reserved_at_fe9[0x17];
10763 
10764 	struct mlx5_ifc_health_buffer_bits health_buffer;
10765 
10766 	u8         no_dram_nic_offset[0x20];
10767 
10768 	u8         reserved_at_1220[0x6e40];
10769 
10770 	u8         reserved_at_8060[0x1f];
10771 	u8         clear_int[0x1];
10772 
10773 	u8         health_syndrome[0x8];
10774 	u8         health_counter[0x18];
10775 
10776 	u8         reserved_at_80a0[0x17fc0];
10777 };
10778 
10779 struct mlx5_ifc_mtpps_reg_bits {
10780 	u8         reserved_at_0[0xc];
10781 	u8         cap_number_of_pps_pins[0x4];
10782 	u8         reserved_at_10[0x4];
10783 	u8         cap_max_num_of_pps_in_pins[0x4];
10784 	u8         reserved_at_18[0x4];
10785 	u8         cap_max_num_of_pps_out_pins[0x4];
10786 
10787 	u8         reserved_at_20[0x13];
10788 	u8         cap_log_min_npps_period[0x5];
10789 	u8         reserved_at_38[0x3];
10790 	u8         cap_log_min_out_pulse_duration_ns[0x5];
10791 
10792 	u8         reserved_at_40[0x4];
10793 	u8         cap_pin_3_mode[0x4];
10794 	u8         reserved_at_48[0x4];
10795 	u8         cap_pin_2_mode[0x4];
10796 	u8         reserved_at_50[0x4];
10797 	u8         cap_pin_1_mode[0x4];
10798 	u8         reserved_at_58[0x4];
10799 	u8         cap_pin_0_mode[0x4];
10800 
10801 	u8         reserved_at_60[0x4];
10802 	u8         cap_pin_7_mode[0x4];
10803 	u8         reserved_at_68[0x4];
10804 	u8         cap_pin_6_mode[0x4];
10805 	u8         reserved_at_70[0x4];
10806 	u8         cap_pin_5_mode[0x4];
10807 	u8         reserved_at_78[0x4];
10808 	u8         cap_pin_4_mode[0x4];
10809 
10810 	u8         field_select[0x20];
10811 	u8         reserved_at_a0[0x20];
10812 
10813 	u8         npps_period[0x40];
10814 
10815 	u8         enable[0x1];
10816 	u8         reserved_at_101[0xb];
10817 	u8         pattern[0x4];
10818 	u8         reserved_at_110[0x4];
10819 	u8         pin_mode[0x4];
10820 	u8         pin[0x8];
10821 
10822 	u8         reserved_at_120[0x2];
10823 	u8         out_pulse_duration_ns[0x1e];
10824 
10825 	u8         time_stamp[0x40];
10826 
10827 	u8         out_pulse_duration[0x10];
10828 	u8         out_periodic_adjustment[0x10];
10829 	u8         enhanced_out_periodic_adjustment[0x20];
10830 
10831 	u8         reserved_at_1c0[0x20];
10832 };
10833 
10834 struct mlx5_ifc_mtppse_reg_bits {
10835 	u8         reserved_at_0[0x18];
10836 	u8         pin[0x8];
10837 	u8         event_arm[0x1];
10838 	u8         reserved_at_21[0x1b];
10839 	u8         event_generation_mode[0x4];
10840 	u8         reserved_at_40[0x40];
10841 };
10842 
10843 struct mlx5_ifc_mcqs_reg_bits {
10844 	u8         last_index_flag[0x1];
10845 	u8         reserved_at_1[0x7];
10846 	u8         fw_device[0x8];
10847 	u8         component_index[0x10];
10848 
10849 	u8         reserved_at_20[0x10];
10850 	u8         identifier[0x10];
10851 
10852 	u8         reserved_at_40[0x17];
10853 	u8         component_status[0x5];
10854 	u8         component_update_state[0x4];
10855 
10856 	u8         last_update_state_changer_type[0x4];
10857 	u8         last_update_state_changer_host_id[0x4];
10858 	u8         reserved_at_68[0x18];
10859 };
10860 
10861 struct mlx5_ifc_mcqi_cap_bits {
10862 	u8         supported_info_bitmask[0x20];
10863 
10864 	u8         component_size[0x20];
10865 
10866 	u8         max_component_size[0x20];
10867 
10868 	u8         log_mcda_word_size[0x4];
10869 	u8         reserved_at_64[0xc];
10870 	u8         mcda_max_write_size[0x10];
10871 
10872 	u8         rd_en[0x1];
10873 	u8         reserved_at_81[0x1];
10874 	u8         match_chip_id[0x1];
10875 	u8         match_psid[0x1];
10876 	u8         check_user_timestamp[0x1];
10877 	u8         match_base_guid_mac[0x1];
10878 	u8         reserved_at_86[0x1a];
10879 };
10880 
10881 struct mlx5_ifc_mcqi_version_bits {
10882 	u8         reserved_at_0[0x2];
10883 	u8         build_time_valid[0x1];
10884 	u8         user_defined_time_valid[0x1];
10885 	u8         reserved_at_4[0x14];
10886 	u8         version_string_length[0x8];
10887 
10888 	u8         version[0x20];
10889 
10890 	u8         build_time[0x40];
10891 
10892 	u8         user_defined_time[0x40];
10893 
10894 	u8         build_tool_version[0x20];
10895 
10896 	u8         reserved_at_e0[0x20];
10897 
10898 	u8         version_string[92][0x8];
10899 };
10900 
10901 struct mlx5_ifc_mcqi_activation_method_bits {
10902 	u8         pending_server_ac_power_cycle[0x1];
10903 	u8         pending_server_dc_power_cycle[0x1];
10904 	u8         pending_server_reboot[0x1];
10905 	u8         pending_fw_reset[0x1];
10906 	u8         auto_activate[0x1];
10907 	u8         all_hosts_sync[0x1];
10908 	u8         device_hw_reset[0x1];
10909 	u8         reserved_at_7[0x19];
10910 };
10911 
10912 union mlx5_ifc_mcqi_reg_data_bits {
10913 	struct mlx5_ifc_mcqi_cap_bits               mcqi_caps;
10914 	struct mlx5_ifc_mcqi_version_bits           mcqi_version;
10915 	struct mlx5_ifc_mcqi_activation_method_bits mcqi_activation_mathod;
10916 };
10917 
10918 struct mlx5_ifc_mcqi_reg_bits {
10919 	u8         read_pending_component[0x1];
10920 	u8         reserved_at_1[0xf];
10921 	u8         component_index[0x10];
10922 
10923 	u8         reserved_at_20[0x20];
10924 
10925 	u8         reserved_at_40[0x1b];
10926 	u8         info_type[0x5];
10927 
10928 	u8         info_size[0x20];
10929 
10930 	u8         offset[0x20];
10931 
10932 	u8         reserved_at_a0[0x10];
10933 	u8         data_size[0x10];
10934 
10935 	union mlx5_ifc_mcqi_reg_data_bits data[];
10936 };
10937 
10938 struct mlx5_ifc_mcc_reg_bits {
10939 	u8         reserved_at_0[0x4];
10940 	u8         time_elapsed_since_last_cmd[0xc];
10941 	u8         reserved_at_10[0x8];
10942 	u8         instruction[0x8];
10943 
10944 	u8         reserved_at_20[0x10];
10945 	u8         component_index[0x10];
10946 
10947 	u8         reserved_at_40[0x8];
10948 	u8         update_handle[0x18];
10949 
10950 	u8         handle_owner_type[0x4];
10951 	u8         handle_owner_host_id[0x4];
10952 	u8         reserved_at_68[0x1];
10953 	u8         control_progress[0x7];
10954 	u8         error_code[0x8];
10955 	u8         reserved_at_78[0x4];
10956 	u8         control_state[0x4];
10957 
10958 	u8         component_size[0x20];
10959 
10960 	u8         reserved_at_a0[0x60];
10961 };
10962 
10963 struct mlx5_ifc_mcda_reg_bits {
10964 	u8         reserved_at_0[0x8];
10965 	u8         update_handle[0x18];
10966 
10967 	u8         offset[0x20];
10968 
10969 	u8         reserved_at_40[0x10];
10970 	u8         size[0x10];
10971 
10972 	u8         reserved_at_60[0x20];
10973 
10974 	u8         data[][0x20];
10975 };
10976 
10977 enum {
10978 	MLX5_MFRL_REG_RESET_STATE_IDLE = 0,
10979 	MLX5_MFRL_REG_RESET_STATE_IN_NEGOTIATION = 1,
10980 	MLX5_MFRL_REG_RESET_STATE_RESET_IN_PROGRESS = 2,
10981 	MLX5_MFRL_REG_RESET_STATE_NEG_TIMEOUT = 3,
10982 	MLX5_MFRL_REG_RESET_STATE_NACK = 4,
10983 	MLX5_MFRL_REG_RESET_STATE_UNLOAD_TIMEOUT = 5,
10984 };
10985 
10986 enum {
10987 	MLX5_MFRL_REG_RESET_TYPE_FULL_CHIP = BIT(0),
10988 	MLX5_MFRL_REG_RESET_TYPE_NET_PORT_ALIVE = BIT(1),
10989 };
10990 
10991 enum {
10992 	MLX5_MFRL_REG_RESET_LEVEL0 = BIT(0),
10993 	MLX5_MFRL_REG_RESET_LEVEL3 = BIT(3),
10994 	MLX5_MFRL_REG_RESET_LEVEL6 = BIT(6),
10995 };
10996 
10997 struct mlx5_ifc_mfrl_reg_bits {
10998 	u8         reserved_at_0[0x20];
10999 
11000 	u8         reserved_at_20[0x2];
11001 	u8         pci_sync_for_fw_update_start[0x1];
11002 	u8         pci_sync_for_fw_update_resp[0x2];
11003 	u8         rst_type_sel[0x3];
11004 	u8         reserved_at_28[0x4];
11005 	u8         reset_state[0x4];
11006 	u8         reset_type[0x8];
11007 	u8         reset_level[0x8];
11008 };
11009 
11010 struct mlx5_ifc_mirc_reg_bits {
11011 	u8         reserved_at_0[0x18];
11012 	u8         status_code[0x8];
11013 
11014 	u8         reserved_at_20[0x20];
11015 };
11016 
11017 struct mlx5_ifc_pddr_monitor_opcode_bits {
11018 	u8         reserved_at_0[0x10];
11019 	u8         monitor_opcode[0x10];
11020 };
11021 
11022 union mlx5_ifc_pddr_troubleshooting_page_status_opcode_auto_bits {
11023 	struct mlx5_ifc_pddr_monitor_opcode_bits pddr_monitor_opcode;
11024 	u8         reserved_at_0[0x20];
11025 };
11026 
11027 enum {
11028 	/* Monitor opcodes */
11029 	MLX5_PDDR_REG_TRBLSH_GROUP_OPCODE_MONITOR = 0x0,
11030 };
11031 
11032 struct mlx5_ifc_pddr_troubleshooting_page_bits {
11033 	u8         reserved_at_0[0x10];
11034 	u8         group_opcode[0x10];
11035 
11036 	union mlx5_ifc_pddr_troubleshooting_page_status_opcode_auto_bits status_opcode;
11037 
11038 	u8         reserved_at_40[0x20];
11039 
11040 	u8         status_message[59][0x20];
11041 };
11042 
11043 union mlx5_ifc_pddr_reg_page_data_auto_bits {
11044 	struct mlx5_ifc_pddr_troubleshooting_page_bits pddr_troubleshooting_page;
11045 	u8         reserved_at_0[0x7c0];
11046 };
11047 
11048 enum {
11049 	MLX5_PDDR_REG_PAGE_SELECT_TROUBLESHOOTING_INFO_PAGE      = 0x1,
11050 };
11051 
11052 struct mlx5_ifc_pddr_reg_bits {
11053 	u8         reserved_at_0[0x8];
11054 	u8         local_port[0x8];
11055 	u8         pnat[0x2];
11056 	u8         reserved_at_12[0xe];
11057 
11058 	u8         reserved_at_20[0x18];
11059 	u8         page_select[0x8];
11060 
11061 	union mlx5_ifc_pddr_reg_page_data_auto_bits page_data;
11062 };
11063 
11064 struct mlx5_ifc_mrtc_reg_bits {
11065 	u8         time_synced[0x1];
11066 	u8         reserved_at_1[0x1f];
11067 
11068 	u8         reserved_at_20[0x20];
11069 
11070 	u8         time_h[0x20];
11071 
11072 	u8         time_l[0x20];
11073 };
11074 
11075 struct mlx5_ifc_mtcap_reg_bits {
11076 	u8         reserved_at_0[0x19];
11077 	u8         sensor_count[0x7];
11078 
11079 	u8         reserved_at_20[0x20];
11080 
11081 	u8         sensor_map[0x40];
11082 };
11083 
11084 struct mlx5_ifc_mtmp_reg_bits {
11085 	u8         reserved_at_0[0x14];
11086 	u8         sensor_index[0xc];
11087 
11088 	u8         reserved_at_20[0x10];
11089 	u8         temperature[0x10];
11090 
11091 	u8         mte[0x1];
11092 	u8         mtr[0x1];
11093 	u8         reserved_at_42[0xe];
11094 	u8         max_temperature[0x10];
11095 
11096 	u8         tee[0x2];
11097 	u8         reserved_at_62[0xe];
11098 	u8         temp_threshold_hi[0x10];
11099 
11100 	u8         reserved_at_80[0x10];
11101 	u8         temp_threshold_lo[0x10];
11102 
11103 	u8         reserved_at_a0[0x20];
11104 
11105 	u8         sensor_name_hi[0x20];
11106 	u8         sensor_name_lo[0x20];
11107 };
11108 
11109 union mlx5_ifc_ports_control_registers_document_bits {
11110 	struct mlx5_ifc_bufferx_reg_bits bufferx_reg;
11111 	struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
11112 	struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
11113 	struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
11114 	struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
11115 	struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
11116 	struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
11117 	struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout;
11118 	struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout;
11119 	struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping;
11120 	struct mlx5_ifc_pamp_reg_bits pamp_reg;
11121 	struct mlx5_ifc_paos_reg_bits paos_reg;
11122 	struct mlx5_ifc_pcap_reg_bits pcap_reg;
11123 	struct mlx5_ifc_pddr_monitor_opcode_bits pddr_monitor_opcode;
11124 	struct mlx5_ifc_pddr_reg_bits pddr_reg;
11125 	struct mlx5_ifc_pddr_troubleshooting_page_bits pddr_troubleshooting_page;
11126 	struct mlx5_ifc_peir_reg_bits peir_reg;
11127 	struct mlx5_ifc_pelc_reg_bits pelc_reg;
11128 	struct mlx5_ifc_pfcc_reg_bits pfcc_reg;
11129 	struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
11130 	struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
11131 	struct mlx5_ifc_pifr_reg_bits pifr_reg;
11132 	struct mlx5_ifc_pipg_reg_bits pipg_reg;
11133 	struct mlx5_ifc_plbf_reg_bits plbf_reg;
11134 	struct mlx5_ifc_plib_reg_bits plib_reg;
11135 	struct mlx5_ifc_plpc_reg_bits plpc_reg;
11136 	struct mlx5_ifc_pmaos_reg_bits pmaos_reg;
11137 	struct mlx5_ifc_pmlp_reg_bits pmlp_reg;
11138 	struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg;
11139 	struct mlx5_ifc_pmpc_reg_bits pmpc_reg;
11140 	struct mlx5_ifc_pmpe_reg_bits pmpe_reg;
11141 	struct mlx5_ifc_pmpr_reg_bits pmpr_reg;
11142 	struct mlx5_ifc_pmtu_reg_bits pmtu_reg;
11143 	struct mlx5_ifc_ppad_reg_bits ppad_reg;
11144 	struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg;
11145 	struct mlx5_ifc_mpein_reg_bits mpein_reg;
11146 	struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg;
11147 	struct mlx5_ifc_pplm_reg_bits pplm_reg;
11148 	struct mlx5_ifc_pplr_reg_bits pplr_reg;
11149 	struct mlx5_ifc_ppsc_reg_bits ppsc_reg;
11150 	struct mlx5_ifc_pqdr_reg_bits pqdr_reg;
11151 	struct mlx5_ifc_pspa_reg_bits pspa_reg;
11152 	struct mlx5_ifc_ptas_reg_bits ptas_reg;
11153 	struct mlx5_ifc_ptys_reg_bits ptys_reg;
11154 	struct mlx5_ifc_mlcr_reg_bits mlcr_reg;
11155 	struct mlx5_ifc_pude_reg_bits pude_reg;
11156 	struct mlx5_ifc_pvlc_reg_bits pvlc_reg;
11157 	struct mlx5_ifc_slrg_reg_bits slrg_reg;
11158 	struct mlx5_ifc_sltp_reg_bits sltp_reg;
11159 	struct mlx5_ifc_mtpps_reg_bits mtpps_reg;
11160 	struct mlx5_ifc_mtppse_reg_bits mtppse_reg;
11161 	struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg;
11162 	struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits;
11163 	struct mlx5_ifc_fpga_cap_bits fpga_cap_bits;
11164 	struct mlx5_ifc_mcqi_reg_bits mcqi_reg;
11165 	struct mlx5_ifc_mcc_reg_bits mcc_reg;
11166 	struct mlx5_ifc_mcda_reg_bits mcda_reg;
11167 	struct mlx5_ifc_mirc_reg_bits mirc_reg;
11168 	struct mlx5_ifc_mfrl_reg_bits mfrl_reg;
11169 	struct mlx5_ifc_mtutc_reg_bits mtutc_reg;
11170 	struct mlx5_ifc_mrtc_reg_bits mrtc_reg;
11171 	struct mlx5_ifc_mtcap_reg_bits mtcap_reg;
11172 	struct mlx5_ifc_mtmp_reg_bits mtmp_reg;
11173 	u8         reserved_at_0[0x60e0];
11174 };
11175 
11176 union mlx5_ifc_debug_enhancements_document_bits {
11177 	struct mlx5_ifc_health_buffer_bits health_buffer;
11178 	u8         reserved_at_0[0x200];
11179 };
11180 
11181 union mlx5_ifc_uplink_pci_interface_document_bits {
11182 	struct mlx5_ifc_initial_seg_bits initial_seg;
11183 	u8         reserved_at_0[0x20060];
11184 };
11185 
11186 struct mlx5_ifc_set_flow_table_root_out_bits {
11187 	u8         status[0x8];
11188 	u8         reserved_at_8[0x18];
11189 
11190 	u8         syndrome[0x20];
11191 
11192 	u8         reserved_at_40[0x40];
11193 };
11194 
11195 struct mlx5_ifc_set_flow_table_root_in_bits {
11196 	u8         opcode[0x10];
11197 	u8         reserved_at_10[0x10];
11198 
11199 	u8         reserved_at_20[0x10];
11200 	u8         op_mod[0x10];
11201 
11202 	u8         other_vport[0x1];
11203 	u8         reserved_at_41[0xf];
11204 	u8         vport_number[0x10];
11205 
11206 	u8         reserved_at_60[0x20];
11207 
11208 	u8         table_type[0x8];
11209 	u8         reserved_at_88[0x7];
11210 	u8         table_of_other_vport[0x1];
11211 	u8         table_vport_number[0x10];
11212 
11213 	u8         reserved_at_a0[0x8];
11214 	u8         table_id[0x18];
11215 
11216 	u8         reserved_at_c0[0x8];
11217 	u8         underlay_qpn[0x18];
11218 	u8         table_eswitch_owner_vhca_id_valid[0x1];
11219 	u8         reserved_at_e1[0xf];
11220 	u8         table_eswitch_owner_vhca_id[0x10];
11221 	u8         reserved_at_100[0x100];
11222 };
11223 
11224 enum {
11225 	MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID     = (1UL << 0),
11226 	MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15),
11227 };
11228 
11229 struct mlx5_ifc_modify_flow_table_out_bits {
11230 	u8         status[0x8];
11231 	u8         reserved_at_8[0x18];
11232 
11233 	u8         syndrome[0x20];
11234 
11235 	u8         reserved_at_40[0x40];
11236 };
11237 
11238 struct mlx5_ifc_modify_flow_table_in_bits {
11239 	u8         opcode[0x10];
11240 	u8         reserved_at_10[0x10];
11241 
11242 	u8         reserved_at_20[0x10];
11243 	u8         op_mod[0x10];
11244 
11245 	u8         other_vport[0x1];
11246 	u8         reserved_at_41[0xf];
11247 	u8         vport_number[0x10];
11248 
11249 	u8         reserved_at_60[0x10];
11250 	u8         modify_field_select[0x10];
11251 
11252 	u8         table_type[0x8];
11253 	u8         reserved_at_88[0x18];
11254 
11255 	u8         reserved_at_a0[0x8];
11256 	u8         table_id[0x18];
11257 
11258 	struct mlx5_ifc_flow_table_context_bits flow_table_context;
11259 };
11260 
11261 struct mlx5_ifc_ets_tcn_config_reg_bits {
11262 	u8         g[0x1];
11263 	u8         b[0x1];
11264 	u8         r[0x1];
11265 	u8         reserved_at_3[0x9];
11266 	u8         group[0x4];
11267 	u8         reserved_at_10[0x9];
11268 	u8         bw_allocation[0x7];
11269 
11270 	u8         reserved_at_20[0xc];
11271 	u8         max_bw_units[0x4];
11272 	u8         reserved_at_30[0x8];
11273 	u8         max_bw_value[0x8];
11274 };
11275 
11276 struct mlx5_ifc_ets_global_config_reg_bits {
11277 	u8         reserved_at_0[0x2];
11278 	u8         r[0x1];
11279 	u8         reserved_at_3[0x1d];
11280 
11281 	u8         reserved_at_20[0xc];
11282 	u8         max_bw_units[0x4];
11283 	u8         reserved_at_30[0x8];
11284 	u8         max_bw_value[0x8];
11285 };
11286 
11287 struct mlx5_ifc_qetc_reg_bits {
11288 	u8                                         reserved_at_0[0x8];
11289 	u8                                         port_number[0x8];
11290 	u8                                         reserved_at_10[0x30];
11291 
11292 	struct mlx5_ifc_ets_tcn_config_reg_bits    tc_configuration[0x8];
11293 	struct mlx5_ifc_ets_global_config_reg_bits global_configuration;
11294 };
11295 
11296 struct mlx5_ifc_qpdpm_dscp_reg_bits {
11297 	u8         e[0x1];
11298 	u8         reserved_at_01[0x0b];
11299 	u8         prio[0x04];
11300 };
11301 
11302 struct mlx5_ifc_qpdpm_reg_bits {
11303 	u8                                     reserved_at_0[0x8];
11304 	u8                                     local_port[0x8];
11305 	u8                                     reserved_at_10[0x10];
11306 	struct mlx5_ifc_qpdpm_dscp_reg_bits    dscp[64];
11307 };
11308 
11309 struct mlx5_ifc_qpts_reg_bits {
11310 	u8         reserved_at_0[0x8];
11311 	u8         local_port[0x8];
11312 	u8         reserved_at_10[0x2d];
11313 	u8         trust_state[0x3];
11314 };
11315 
11316 struct mlx5_ifc_pptb_reg_bits {
11317 	u8         reserved_at_0[0x2];
11318 	u8         mm[0x2];
11319 	u8         reserved_at_4[0x4];
11320 	u8         local_port[0x8];
11321 	u8         reserved_at_10[0x6];
11322 	u8         cm[0x1];
11323 	u8         um[0x1];
11324 	u8         pm[0x8];
11325 
11326 	u8         prio_x_buff[0x20];
11327 
11328 	u8         pm_msb[0x8];
11329 	u8         reserved_at_48[0x10];
11330 	u8         ctrl_buff[0x4];
11331 	u8         untagged_buff[0x4];
11332 };
11333 
11334 struct mlx5_ifc_sbcam_reg_bits {
11335 	u8         reserved_at_0[0x8];
11336 	u8         feature_group[0x8];
11337 	u8         reserved_at_10[0x8];
11338 	u8         access_reg_group[0x8];
11339 
11340 	u8         reserved_at_20[0x20];
11341 
11342 	u8         sb_access_reg_cap_mask[4][0x20];
11343 
11344 	u8         reserved_at_c0[0x80];
11345 
11346 	u8         sb_feature_cap_mask[4][0x20];
11347 
11348 	u8         reserved_at_1c0[0x40];
11349 
11350 	u8         cap_total_buffer_size[0x20];
11351 
11352 	u8         cap_cell_size[0x10];
11353 	u8         cap_max_pg_buffers[0x8];
11354 	u8         cap_num_pool_supported[0x8];
11355 
11356 	u8         reserved_at_240[0x8];
11357 	u8         cap_sbsr_stat_size[0x8];
11358 	u8         cap_max_tclass_data[0x8];
11359 	u8         cap_max_cpu_ingress_tclass_sb[0x8];
11360 };
11361 
11362 struct mlx5_ifc_pbmc_reg_bits {
11363 	u8         reserved_at_0[0x8];
11364 	u8         local_port[0x8];
11365 	u8         reserved_at_10[0x10];
11366 
11367 	u8         xoff_timer_value[0x10];
11368 	u8         xoff_refresh[0x10];
11369 
11370 	u8         reserved_at_40[0x9];
11371 	u8         fullness_threshold[0x7];
11372 	u8         port_buffer_size[0x10];
11373 
11374 	struct mlx5_ifc_bufferx_reg_bits buffer[10];
11375 
11376 	u8         reserved_at_2e0[0x80];
11377 };
11378 
11379 struct mlx5_ifc_sbpr_reg_bits {
11380 	u8         desc[0x1];
11381 	u8         snap[0x1];
11382 	u8         reserved_at_2[0x4];
11383 	u8         dir[0x2];
11384 	u8         reserved_at_8[0x14];
11385 	u8         pool[0x4];
11386 
11387 	u8         infi_size[0x1];
11388 	u8         reserved_at_21[0x7];
11389 	u8         size[0x18];
11390 
11391 	u8         reserved_at_40[0x1c];
11392 	u8         mode[0x4];
11393 
11394 	u8         reserved_at_60[0x8];
11395 	u8         buff_occupancy[0x18];
11396 
11397 	u8         clr[0x1];
11398 	u8         reserved_at_81[0x7];
11399 	u8         max_buff_occupancy[0x18];
11400 
11401 	u8         reserved_at_a0[0x8];
11402 	u8         ext_buff_occupancy[0x18];
11403 };
11404 
11405 struct mlx5_ifc_sbcm_reg_bits {
11406 	u8         desc[0x1];
11407 	u8         snap[0x1];
11408 	u8         reserved_at_2[0x6];
11409 	u8         local_port[0x8];
11410 	u8         pnat[0x2];
11411 	u8         pg_buff[0x6];
11412 	u8         reserved_at_18[0x6];
11413 	u8         dir[0x2];
11414 
11415 	u8         reserved_at_20[0x1f];
11416 	u8         exc[0x1];
11417 
11418 	u8         reserved_at_40[0x40];
11419 
11420 	u8         reserved_at_80[0x8];
11421 	u8         buff_occupancy[0x18];
11422 
11423 	u8         clr[0x1];
11424 	u8         reserved_at_a1[0x7];
11425 	u8         max_buff_occupancy[0x18];
11426 
11427 	u8         reserved_at_c0[0x8];
11428 	u8         min_buff[0x18];
11429 
11430 	u8         infi_max[0x1];
11431 	u8         reserved_at_e1[0x7];
11432 	u8         max_buff[0x18];
11433 
11434 	u8         reserved_at_100[0x20];
11435 
11436 	u8         reserved_at_120[0x1c];
11437 	u8         pool[0x4];
11438 };
11439 
11440 struct mlx5_ifc_qtct_reg_bits {
11441 	u8         reserved_at_0[0x8];
11442 	u8         port_number[0x8];
11443 	u8         reserved_at_10[0xd];
11444 	u8         prio[0x3];
11445 
11446 	u8         reserved_at_20[0x1d];
11447 	u8         tclass[0x3];
11448 };
11449 
11450 struct mlx5_ifc_mcia_reg_bits {
11451 	u8         l[0x1];
11452 	u8         reserved_at_1[0x7];
11453 	u8         module[0x8];
11454 	u8         reserved_at_10[0x8];
11455 	u8         status[0x8];
11456 
11457 	u8         i2c_device_address[0x8];
11458 	u8         page_number[0x8];
11459 	u8         device_address[0x10];
11460 
11461 	u8         reserved_at_40[0x10];
11462 	u8         size[0x10];
11463 
11464 	u8         reserved_at_60[0x20];
11465 
11466 	u8         dword_0[0x20];
11467 	u8         dword_1[0x20];
11468 	u8         dword_2[0x20];
11469 	u8         dword_3[0x20];
11470 	u8         dword_4[0x20];
11471 	u8         dword_5[0x20];
11472 	u8         dword_6[0x20];
11473 	u8         dword_7[0x20];
11474 	u8         dword_8[0x20];
11475 	u8         dword_9[0x20];
11476 	u8         dword_10[0x20];
11477 	u8         dword_11[0x20];
11478 };
11479 
11480 struct mlx5_ifc_dcbx_param_bits {
11481 	u8         dcbx_cee_cap[0x1];
11482 	u8         dcbx_ieee_cap[0x1];
11483 	u8         dcbx_standby_cap[0x1];
11484 	u8         reserved_at_3[0x5];
11485 	u8         port_number[0x8];
11486 	u8         reserved_at_10[0xa];
11487 	u8         max_application_table_size[6];
11488 	u8         reserved_at_20[0x15];
11489 	u8         version_oper[0x3];
11490 	u8         reserved_at_38[5];
11491 	u8         version_admin[0x3];
11492 	u8         willing_admin[0x1];
11493 	u8         reserved_at_41[0x3];
11494 	u8         pfc_cap_oper[0x4];
11495 	u8         reserved_at_48[0x4];
11496 	u8         pfc_cap_admin[0x4];
11497 	u8         reserved_at_50[0x4];
11498 	u8         num_of_tc_oper[0x4];
11499 	u8         reserved_at_58[0x4];
11500 	u8         num_of_tc_admin[0x4];
11501 	u8         remote_willing[0x1];
11502 	u8         reserved_at_61[3];
11503 	u8         remote_pfc_cap[4];
11504 	u8         reserved_at_68[0x14];
11505 	u8         remote_num_of_tc[0x4];
11506 	u8         reserved_at_80[0x18];
11507 	u8         error[0x8];
11508 	u8         reserved_at_a0[0x160];
11509 };
11510 
11511 enum {
11512 	MLX5_LAG_PORT_SELECT_MODE_QUEUE_AFFINITY = 0,
11513 	MLX5_LAG_PORT_SELECT_MODE_PORT_SELECT_FT = 1,
11514 	MLX5_LAG_PORT_SELECT_MODE_PORT_SELECT_MPESW = 2,
11515 };
11516 
11517 struct mlx5_ifc_lagc_bits {
11518 	u8         fdb_selection_mode[0x1];
11519 	u8         reserved_at_1[0x14];
11520 	u8         port_select_mode[0x3];
11521 	u8         reserved_at_18[0x5];
11522 	u8         lag_state[0x3];
11523 
11524 	u8         reserved_at_20[0xc];
11525 	u8         active_port[0x4];
11526 	u8         reserved_at_30[0x4];
11527 	u8         tx_remap_affinity_2[0x4];
11528 	u8         reserved_at_38[0x4];
11529 	u8         tx_remap_affinity_1[0x4];
11530 };
11531 
11532 struct mlx5_ifc_create_lag_out_bits {
11533 	u8         status[0x8];
11534 	u8         reserved_at_8[0x18];
11535 
11536 	u8         syndrome[0x20];
11537 
11538 	u8         reserved_at_40[0x40];
11539 };
11540 
11541 struct mlx5_ifc_create_lag_in_bits {
11542 	u8         opcode[0x10];
11543 	u8         reserved_at_10[0x10];
11544 
11545 	u8         reserved_at_20[0x10];
11546 	u8         op_mod[0x10];
11547 
11548 	struct mlx5_ifc_lagc_bits ctx;
11549 };
11550 
11551 struct mlx5_ifc_modify_lag_out_bits {
11552 	u8         status[0x8];
11553 	u8         reserved_at_8[0x18];
11554 
11555 	u8         syndrome[0x20];
11556 
11557 	u8         reserved_at_40[0x40];
11558 };
11559 
11560 struct mlx5_ifc_modify_lag_in_bits {
11561 	u8         opcode[0x10];
11562 	u8         reserved_at_10[0x10];
11563 
11564 	u8         reserved_at_20[0x10];
11565 	u8         op_mod[0x10];
11566 
11567 	u8         reserved_at_40[0x20];
11568 	u8         field_select[0x20];
11569 
11570 	struct mlx5_ifc_lagc_bits ctx;
11571 };
11572 
11573 struct mlx5_ifc_query_lag_out_bits {
11574 	u8         status[0x8];
11575 	u8         reserved_at_8[0x18];
11576 
11577 	u8         syndrome[0x20];
11578 
11579 	struct mlx5_ifc_lagc_bits ctx;
11580 };
11581 
11582 struct mlx5_ifc_query_lag_in_bits {
11583 	u8         opcode[0x10];
11584 	u8         reserved_at_10[0x10];
11585 
11586 	u8         reserved_at_20[0x10];
11587 	u8         op_mod[0x10];
11588 
11589 	u8         reserved_at_40[0x40];
11590 };
11591 
11592 struct mlx5_ifc_destroy_lag_out_bits {
11593 	u8         status[0x8];
11594 	u8         reserved_at_8[0x18];
11595 
11596 	u8         syndrome[0x20];
11597 
11598 	u8         reserved_at_40[0x40];
11599 };
11600 
11601 struct mlx5_ifc_destroy_lag_in_bits {
11602 	u8         opcode[0x10];
11603 	u8         reserved_at_10[0x10];
11604 
11605 	u8         reserved_at_20[0x10];
11606 	u8         op_mod[0x10];
11607 
11608 	u8         reserved_at_40[0x40];
11609 };
11610 
11611 struct mlx5_ifc_create_vport_lag_out_bits {
11612 	u8         status[0x8];
11613 	u8         reserved_at_8[0x18];
11614 
11615 	u8         syndrome[0x20];
11616 
11617 	u8         reserved_at_40[0x40];
11618 };
11619 
11620 struct mlx5_ifc_create_vport_lag_in_bits {
11621 	u8         opcode[0x10];
11622 	u8         reserved_at_10[0x10];
11623 
11624 	u8         reserved_at_20[0x10];
11625 	u8         op_mod[0x10];
11626 
11627 	u8         reserved_at_40[0x40];
11628 };
11629 
11630 struct mlx5_ifc_destroy_vport_lag_out_bits {
11631 	u8         status[0x8];
11632 	u8         reserved_at_8[0x18];
11633 
11634 	u8         syndrome[0x20];
11635 
11636 	u8         reserved_at_40[0x40];
11637 };
11638 
11639 struct mlx5_ifc_destroy_vport_lag_in_bits {
11640 	u8         opcode[0x10];
11641 	u8         reserved_at_10[0x10];
11642 
11643 	u8         reserved_at_20[0x10];
11644 	u8         op_mod[0x10];
11645 
11646 	u8         reserved_at_40[0x40];
11647 };
11648 
11649 enum {
11650 	MLX5_MODIFY_MEMIC_OP_MOD_ALLOC,
11651 	MLX5_MODIFY_MEMIC_OP_MOD_DEALLOC,
11652 };
11653 
11654 struct mlx5_ifc_modify_memic_in_bits {
11655 	u8         opcode[0x10];
11656 	u8         uid[0x10];
11657 
11658 	u8         reserved_at_20[0x10];
11659 	u8         op_mod[0x10];
11660 
11661 	u8         reserved_at_40[0x20];
11662 
11663 	u8         reserved_at_60[0x18];
11664 	u8         memic_operation_type[0x8];
11665 
11666 	u8         memic_start_addr[0x40];
11667 
11668 	u8         reserved_at_c0[0x140];
11669 };
11670 
11671 struct mlx5_ifc_modify_memic_out_bits {
11672 	u8         status[0x8];
11673 	u8         reserved_at_8[0x18];
11674 
11675 	u8         syndrome[0x20];
11676 
11677 	u8         reserved_at_40[0x40];
11678 
11679 	u8         memic_operation_addr[0x40];
11680 
11681 	u8         reserved_at_c0[0x140];
11682 };
11683 
11684 struct mlx5_ifc_alloc_memic_in_bits {
11685 	u8         opcode[0x10];
11686 	u8         reserved_at_10[0x10];
11687 
11688 	u8         reserved_at_20[0x10];
11689 	u8         op_mod[0x10];
11690 
11691 	u8         reserved_at_30[0x20];
11692 
11693 	u8	   reserved_at_40[0x18];
11694 	u8	   log_memic_addr_alignment[0x8];
11695 
11696 	u8         range_start_addr[0x40];
11697 
11698 	u8         range_size[0x20];
11699 
11700 	u8         memic_size[0x20];
11701 };
11702 
11703 struct mlx5_ifc_alloc_memic_out_bits {
11704 	u8         status[0x8];
11705 	u8         reserved_at_8[0x18];
11706 
11707 	u8         syndrome[0x20];
11708 
11709 	u8         memic_start_addr[0x40];
11710 };
11711 
11712 struct mlx5_ifc_dealloc_memic_in_bits {
11713 	u8         opcode[0x10];
11714 	u8         reserved_at_10[0x10];
11715 
11716 	u8         reserved_at_20[0x10];
11717 	u8         op_mod[0x10];
11718 
11719 	u8         reserved_at_40[0x40];
11720 
11721 	u8         memic_start_addr[0x40];
11722 
11723 	u8         memic_size[0x20];
11724 
11725 	u8         reserved_at_e0[0x20];
11726 };
11727 
11728 struct mlx5_ifc_dealloc_memic_out_bits {
11729 	u8         status[0x8];
11730 	u8         reserved_at_8[0x18];
11731 
11732 	u8         syndrome[0x20];
11733 
11734 	u8         reserved_at_40[0x40];
11735 };
11736 
11737 struct mlx5_ifc_umem_bits {
11738 	u8         reserved_at_0[0x80];
11739 
11740 	u8         ats[0x1];
11741 	u8         reserved_at_81[0x1a];
11742 	u8         log_page_size[0x5];
11743 
11744 	u8         page_offset[0x20];
11745 
11746 	u8         num_of_mtt[0x40];
11747 
11748 	struct mlx5_ifc_mtt_bits  mtt[];
11749 };
11750 
11751 struct mlx5_ifc_uctx_bits {
11752 	u8         cap[0x20];
11753 
11754 	u8         reserved_at_20[0x160];
11755 };
11756 
11757 struct mlx5_ifc_sw_icm_bits {
11758 	u8         modify_field_select[0x40];
11759 
11760 	u8	   reserved_at_40[0x18];
11761 	u8         log_sw_icm_size[0x8];
11762 
11763 	u8         reserved_at_60[0x20];
11764 
11765 	u8         sw_icm_start_addr[0x40];
11766 
11767 	u8         reserved_at_c0[0x140];
11768 };
11769 
11770 struct mlx5_ifc_geneve_tlv_option_bits {
11771 	u8         modify_field_select[0x40];
11772 
11773 	u8         reserved_at_40[0x18];
11774 	u8         geneve_option_fte_index[0x8];
11775 
11776 	u8         option_class[0x10];
11777 	u8         option_type[0x8];
11778 	u8         reserved_at_78[0x3];
11779 	u8         option_data_length[0x5];
11780 
11781 	u8         reserved_at_80[0x180];
11782 };
11783 
11784 struct mlx5_ifc_create_umem_in_bits {
11785 	u8         opcode[0x10];
11786 	u8         uid[0x10];
11787 
11788 	u8         reserved_at_20[0x10];
11789 	u8         op_mod[0x10];
11790 
11791 	u8         reserved_at_40[0x40];
11792 
11793 	struct mlx5_ifc_umem_bits  umem;
11794 };
11795 
11796 struct mlx5_ifc_create_umem_out_bits {
11797 	u8         status[0x8];
11798 	u8         reserved_at_8[0x18];
11799 
11800 	u8         syndrome[0x20];
11801 
11802 	u8         reserved_at_40[0x8];
11803 	u8         umem_id[0x18];
11804 
11805 	u8         reserved_at_60[0x20];
11806 };
11807 
11808 struct mlx5_ifc_destroy_umem_in_bits {
11809 	u8        opcode[0x10];
11810 	u8        uid[0x10];
11811 
11812 	u8        reserved_at_20[0x10];
11813 	u8        op_mod[0x10];
11814 
11815 	u8        reserved_at_40[0x8];
11816 	u8        umem_id[0x18];
11817 
11818 	u8        reserved_at_60[0x20];
11819 };
11820 
11821 struct mlx5_ifc_destroy_umem_out_bits {
11822 	u8        status[0x8];
11823 	u8        reserved_at_8[0x18];
11824 
11825 	u8        syndrome[0x20];
11826 
11827 	u8        reserved_at_40[0x40];
11828 };
11829 
11830 struct mlx5_ifc_create_uctx_in_bits {
11831 	u8         opcode[0x10];
11832 	u8         reserved_at_10[0x10];
11833 
11834 	u8         reserved_at_20[0x10];
11835 	u8         op_mod[0x10];
11836 
11837 	u8         reserved_at_40[0x40];
11838 
11839 	struct mlx5_ifc_uctx_bits  uctx;
11840 };
11841 
11842 struct mlx5_ifc_create_uctx_out_bits {
11843 	u8         status[0x8];
11844 	u8         reserved_at_8[0x18];
11845 
11846 	u8         syndrome[0x20];
11847 
11848 	u8         reserved_at_40[0x10];
11849 	u8         uid[0x10];
11850 
11851 	u8         reserved_at_60[0x20];
11852 };
11853 
11854 struct mlx5_ifc_destroy_uctx_in_bits {
11855 	u8         opcode[0x10];
11856 	u8         reserved_at_10[0x10];
11857 
11858 	u8         reserved_at_20[0x10];
11859 	u8         op_mod[0x10];
11860 
11861 	u8         reserved_at_40[0x10];
11862 	u8         uid[0x10];
11863 
11864 	u8         reserved_at_60[0x20];
11865 };
11866 
11867 struct mlx5_ifc_destroy_uctx_out_bits {
11868 	u8         status[0x8];
11869 	u8         reserved_at_8[0x18];
11870 
11871 	u8         syndrome[0x20];
11872 
11873 	u8          reserved_at_40[0x40];
11874 };
11875 
11876 struct mlx5_ifc_create_sw_icm_in_bits {
11877 	struct mlx5_ifc_general_obj_in_cmd_hdr_bits   hdr;
11878 	struct mlx5_ifc_sw_icm_bits		      sw_icm;
11879 };
11880 
11881 struct mlx5_ifc_create_geneve_tlv_option_in_bits {
11882 	struct mlx5_ifc_general_obj_in_cmd_hdr_bits   hdr;
11883 	struct mlx5_ifc_geneve_tlv_option_bits        geneve_tlv_opt;
11884 };
11885 
11886 struct mlx5_ifc_mtrc_string_db_param_bits {
11887 	u8         string_db_base_address[0x20];
11888 
11889 	u8         reserved_at_20[0x8];
11890 	u8         string_db_size[0x18];
11891 };
11892 
11893 struct mlx5_ifc_mtrc_cap_bits {
11894 	u8         trace_owner[0x1];
11895 	u8         trace_to_memory[0x1];
11896 	u8         reserved_at_2[0x4];
11897 	u8         trc_ver[0x2];
11898 	u8         reserved_at_8[0x14];
11899 	u8         num_string_db[0x4];
11900 
11901 	u8         first_string_trace[0x8];
11902 	u8         num_string_trace[0x8];
11903 	u8         reserved_at_30[0x28];
11904 
11905 	u8         log_max_trace_buffer_size[0x8];
11906 
11907 	u8         reserved_at_60[0x20];
11908 
11909 	struct mlx5_ifc_mtrc_string_db_param_bits string_db_param[8];
11910 
11911 	u8         reserved_at_280[0x180];
11912 };
11913 
11914 struct mlx5_ifc_mtrc_conf_bits {
11915 	u8         reserved_at_0[0x1c];
11916 	u8         trace_mode[0x4];
11917 	u8         reserved_at_20[0x18];
11918 	u8         log_trace_buffer_size[0x8];
11919 	u8         trace_mkey[0x20];
11920 	u8         reserved_at_60[0x3a0];
11921 };
11922 
11923 struct mlx5_ifc_mtrc_stdb_bits {
11924 	u8         string_db_index[0x4];
11925 	u8         reserved_at_4[0x4];
11926 	u8         read_size[0x18];
11927 	u8         start_offset[0x20];
11928 	u8         string_db_data[];
11929 };
11930 
11931 struct mlx5_ifc_mtrc_ctrl_bits {
11932 	u8         trace_status[0x2];
11933 	u8         reserved_at_2[0x2];
11934 	u8         arm_event[0x1];
11935 	u8         reserved_at_5[0xb];
11936 	u8         modify_field_select[0x10];
11937 	u8         reserved_at_20[0x2b];
11938 	u8         current_timestamp52_32[0x15];
11939 	u8         current_timestamp31_0[0x20];
11940 	u8         reserved_at_80[0x180];
11941 };
11942 
11943 struct mlx5_ifc_host_params_context_bits {
11944 	u8         host_number[0x8];
11945 	u8         reserved_at_8[0x7];
11946 	u8         host_pf_disabled[0x1];
11947 	u8         host_num_of_vfs[0x10];
11948 
11949 	u8         host_total_vfs[0x10];
11950 	u8         host_pci_bus[0x10];
11951 
11952 	u8         reserved_at_40[0x10];
11953 	u8         host_pci_device[0x10];
11954 
11955 	u8         reserved_at_60[0x10];
11956 	u8         host_pci_function[0x10];
11957 
11958 	u8         reserved_at_80[0x180];
11959 };
11960 
11961 struct mlx5_ifc_query_esw_functions_in_bits {
11962 	u8         opcode[0x10];
11963 	u8         reserved_at_10[0x10];
11964 
11965 	u8         reserved_at_20[0x10];
11966 	u8         op_mod[0x10];
11967 
11968 	u8         reserved_at_40[0x40];
11969 };
11970 
11971 struct mlx5_ifc_query_esw_functions_out_bits {
11972 	u8         status[0x8];
11973 	u8         reserved_at_8[0x18];
11974 
11975 	u8         syndrome[0x20];
11976 
11977 	u8         reserved_at_40[0x40];
11978 
11979 	struct mlx5_ifc_host_params_context_bits host_params_context;
11980 
11981 	u8         reserved_at_280[0x180];
11982 	u8         host_sf_enable[][0x40];
11983 };
11984 
11985 struct mlx5_ifc_sf_partition_bits {
11986 	u8         reserved_at_0[0x10];
11987 	u8         log_num_sf[0x8];
11988 	u8         log_sf_bar_size[0x8];
11989 };
11990 
11991 struct mlx5_ifc_query_sf_partitions_out_bits {
11992 	u8         status[0x8];
11993 	u8         reserved_at_8[0x18];
11994 
11995 	u8         syndrome[0x20];
11996 
11997 	u8         reserved_at_40[0x18];
11998 	u8         num_sf_partitions[0x8];
11999 
12000 	u8         reserved_at_60[0x20];
12001 
12002 	struct mlx5_ifc_sf_partition_bits sf_partition[];
12003 };
12004 
12005 struct mlx5_ifc_query_sf_partitions_in_bits {
12006 	u8         opcode[0x10];
12007 	u8         reserved_at_10[0x10];
12008 
12009 	u8         reserved_at_20[0x10];
12010 	u8         op_mod[0x10];
12011 
12012 	u8         reserved_at_40[0x40];
12013 };
12014 
12015 struct mlx5_ifc_dealloc_sf_out_bits {
12016 	u8         status[0x8];
12017 	u8         reserved_at_8[0x18];
12018 
12019 	u8         syndrome[0x20];
12020 
12021 	u8         reserved_at_40[0x40];
12022 };
12023 
12024 struct mlx5_ifc_dealloc_sf_in_bits {
12025 	u8         opcode[0x10];
12026 	u8         reserved_at_10[0x10];
12027 
12028 	u8         reserved_at_20[0x10];
12029 	u8         op_mod[0x10];
12030 
12031 	u8         reserved_at_40[0x10];
12032 	u8         function_id[0x10];
12033 
12034 	u8         reserved_at_60[0x20];
12035 };
12036 
12037 struct mlx5_ifc_alloc_sf_out_bits {
12038 	u8         status[0x8];
12039 	u8         reserved_at_8[0x18];
12040 
12041 	u8         syndrome[0x20];
12042 
12043 	u8         reserved_at_40[0x40];
12044 };
12045 
12046 struct mlx5_ifc_alloc_sf_in_bits {
12047 	u8         opcode[0x10];
12048 	u8         reserved_at_10[0x10];
12049 
12050 	u8         reserved_at_20[0x10];
12051 	u8         op_mod[0x10];
12052 
12053 	u8         reserved_at_40[0x10];
12054 	u8         function_id[0x10];
12055 
12056 	u8         reserved_at_60[0x20];
12057 };
12058 
12059 struct mlx5_ifc_affiliated_event_header_bits {
12060 	u8         reserved_at_0[0x10];
12061 	u8         obj_type[0x10];
12062 
12063 	u8         obj_id[0x20];
12064 };
12065 
12066 enum {
12067 	MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = BIT_ULL(0xc),
12068 	MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_IPSEC = BIT_ULL(0x13),
12069 	MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_SAMPLER = BIT_ULL(0x20),
12070 	MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_FLOW_METER_ASO = BIT_ULL(0x24),
12071 };
12072 
12073 enum {
12074 	MLX5_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = 0xc,
12075 	MLX5_GENERAL_OBJECT_TYPES_IPSEC = 0x13,
12076 	MLX5_GENERAL_OBJECT_TYPES_SAMPLER = 0x20,
12077 	MLX5_GENERAL_OBJECT_TYPES_FLOW_METER_ASO = 0x24,
12078 	MLX5_GENERAL_OBJECT_TYPES_MACSEC = 0x27,
12079 	MLX5_GENERAL_OBJECT_TYPES_INT_KEK = 0x47,
12080 	MLX5_GENERAL_OBJECT_TYPES_FLOW_TABLE_ALIAS = 0xff15,
12081 };
12082 
12083 enum {
12084 	MLX5_IPSEC_OBJECT_ICV_LEN_16B,
12085 };
12086 
12087 enum {
12088 	MLX5_IPSEC_ASO_REG_C_0_1 = 0x0,
12089 	MLX5_IPSEC_ASO_REG_C_2_3 = 0x1,
12090 	MLX5_IPSEC_ASO_REG_C_4_5 = 0x2,
12091 	MLX5_IPSEC_ASO_REG_C_6_7 = 0x3,
12092 };
12093 
12094 enum {
12095 	MLX5_IPSEC_ASO_MODE              = 0x0,
12096 	MLX5_IPSEC_ASO_REPLAY_PROTECTION = 0x1,
12097 	MLX5_IPSEC_ASO_INC_SN            = 0x2,
12098 };
12099 
12100 enum {
12101 	MLX5_IPSEC_ASO_REPLAY_WIN_32BIT  = 0x0,
12102 	MLX5_IPSEC_ASO_REPLAY_WIN_64BIT  = 0x1,
12103 	MLX5_IPSEC_ASO_REPLAY_WIN_128BIT = 0x2,
12104 	MLX5_IPSEC_ASO_REPLAY_WIN_256BIT = 0x3,
12105 };
12106 
12107 struct mlx5_ifc_ipsec_aso_bits {
12108 	u8         valid[0x1];
12109 	u8         reserved_at_201[0x1];
12110 	u8         mode[0x2];
12111 	u8         window_sz[0x2];
12112 	u8         soft_lft_arm[0x1];
12113 	u8         hard_lft_arm[0x1];
12114 	u8         remove_flow_enable[0x1];
12115 	u8         esn_event_arm[0x1];
12116 	u8         reserved_at_20a[0x16];
12117 
12118 	u8         remove_flow_pkt_cnt[0x20];
12119 
12120 	u8         remove_flow_soft_lft[0x20];
12121 
12122 	u8         reserved_at_260[0x80];
12123 
12124 	u8         mode_parameter[0x20];
12125 
12126 	u8         replay_protection_window[0x100];
12127 };
12128 
12129 struct mlx5_ifc_ipsec_obj_bits {
12130 	u8         modify_field_select[0x40];
12131 	u8         full_offload[0x1];
12132 	u8         reserved_at_41[0x1];
12133 	u8         esn_en[0x1];
12134 	u8         esn_overlap[0x1];
12135 	u8         reserved_at_44[0x2];
12136 	u8         icv_length[0x2];
12137 	u8         reserved_at_48[0x4];
12138 	u8         aso_return_reg[0x4];
12139 	u8         reserved_at_50[0x10];
12140 
12141 	u8         esn_msb[0x20];
12142 
12143 	u8         reserved_at_80[0x8];
12144 	u8         dekn[0x18];
12145 
12146 	u8         salt[0x20];
12147 
12148 	u8         implicit_iv[0x40];
12149 
12150 	u8         reserved_at_100[0x8];
12151 	u8         ipsec_aso_access_pd[0x18];
12152 	u8         reserved_at_120[0xe0];
12153 
12154 	struct mlx5_ifc_ipsec_aso_bits ipsec_aso;
12155 };
12156 
12157 struct mlx5_ifc_create_ipsec_obj_in_bits {
12158 	struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
12159 	struct mlx5_ifc_ipsec_obj_bits ipsec_object;
12160 };
12161 
12162 enum {
12163 	MLX5_MODIFY_IPSEC_BITMASK_ESN_OVERLAP = BIT(0),
12164 	MLX5_MODIFY_IPSEC_BITMASK_ESN_MSB = BIT(1),
12165 };
12166 
12167 struct mlx5_ifc_query_ipsec_obj_out_bits {
12168 	struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr;
12169 	struct mlx5_ifc_ipsec_obj_bits ipsec_object;
12170 };
12171 
12172 struct mlx5_ifc_modify_ipsec_obj_in_bits {
12173 	struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
12174 	struct mlx5_ifc_ipsec_obj_bits ipsec_object;
12175 };
12176 
12177 enum {
12178 	MLX5_MACSEC_ASO_REPLAY_PROTECTION = 0x1,
12179 };
12180 
12181 enum {
12182 	MLX5_MACSEC_ASO_REPLAY_WIN_32BIT  = 0x0,
12183 	MLX5_MACSEC_ASO_REPLAY_WIN_64BIT  = 0x1,
12184 	MLX5_MACSEC_ASO_REPLAY_WIN_128BIT = 0x2,
12185 	MLX5_MACSEC_ASO_REPLAY_WIN_256BIT = 0x3,
12186 };
12187 
12188 #define MLX5_MACSEC_ASO_INC_SN  0x2
12189 #define MLX5_MACSEC_ASO_REG_C_4_5 0x2
12190 
12191 struct mlx5_ifc_macsec_aso_bits {
12192 	u8    valid[0x1];
12193 	u8    reserved_at_1[0x1];
12194 	u8    mode[0x2];
12195 	u8    window_size[0x2];
12196 	u8    soft_lifetime_arm[0x1];
12197 	u8    hard_lifetime_arm[0x1];
12198 	u8    remove_flow_enable[0x1];
12199 	u8    epn_event_arm[0x1];
12200 	u8    reserved_at_a[0x16];
12201 
12202 	u8    remove_flow_packet_count[0x20];
12203 
12204 	u8    remove_flow_soft_lifetime[0x20];
12205 
12206 	u8    reserved_at_60[0x80];
12207 
12208 	u8    mode_parameter[0x20];
12209 
12210 	u8    replay_protection_window[8][0x20];
12211 };
12212 
12213 struct mlx5_ifc_macsec_offload_obj_bits {
12214 	u8    modify_field_select[0x40];
12215 
12216 	u8    confidentiality_en[0x1];
12217 	u8    reserved_at_41[0x1];
12218 	u8    epn_en[0x1];
12219 	u8    epn_overlap[0x1];
12220 	u8    reserved_at_44[0x2];
12221 	u8    confidentiality_offset[0x2];
12222 	u8    reserved_at_48[0x4];
12223 	u8    aso_return_reg[0x4];
12224 	u8    reserved_at_50[0x10];
12225 
12226 	u8    epn_msb[0x20];
12227 
12228 	u8    reserved_at_80[0x8];
12229 	u8    dekn[0x18];
12230 
12231 	u8    reserved_at_a0[0x20];
12232 
12233 	u8    sci[0x40];
12234 
12235 	u8    reserved_at_100[0x8];
12236 	u8    macsec_aso_access_pd[0x18];
12237 
12238 	u8    reserved_at_120[0x60];
12239 
12240 	u8    salt[3][0x20];
12241 
12242 	u8    reserved_at_1e0[0x20];
12243 
12244 	struct mlx5_ifc_macsec_aso_bits macsec_aso;
12245 };
12246 
12247 struct mlx5_ifc_create_macsec_obj_in_bits {
12248 	struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
12249 	struct mlx5_ifc_macsec_offload_obj_bits macsec_object;
12250 };
12251 
12252 struct mlx5_ifc_modify_macsec_obj_in_bits {
12253 	struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
12254 	struct mlx5_ifc_macsec_offload_obj_bits macsec_object;
12255 };
12256 
12257 enum {
12258 	MLX5_MODIFY_MACSEC_BITMASK_EPN_OVERLAP = BIT(0),
12259 	MLX5_MODIFY_MACSEC_BITMASK_EPN_MSB = BIT(1),
12260 };
12261 
12262 struct mlx5_ifc_query_macsec_obj_out_bits {
12263 	struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr;
12264 	struct mlx5_ifc_macsec_offload_obj_bits macsec_object;
12265 };
12266 
12267 struct mlx5_ifc_wrapped_dek_bits {
12268 	u8         gcm_iv[0x60];
12269 
12270 	u8         reserved_at_60[0x20];
12271 
12272 	u8         const0[0x1];
12273 	u8         key_size[0x1];
12274 	u8         reserved_at_82[0x2];
12275 	u8         key2_invalid[0x1];
12276 	u8         reserved_at_85[0x3];
12277 	u8         pd[0x18];
12278 
12279 	u8         key_purpose[0x5];
12280 	u8         reserved_at_a5[0x13];
12281 	u8         kek_id[0x8];
12282 
12283 	u8         reserved_at_c0[0x40];
12284 
12285 	u8         key1[0x8][0x20];
12286 
12287 	u8         key2[0x8][0x20];
12288 
12289 	u8         reserved_at_300[0x40];
12290 
12291 	u8         const1[0x1];
12292 	u8         reserved_at_341[0x1f];
12293 
12294 	u8         reserved_at_360[0x20];
12295 
12296 	u8         auth_tag[0x80];
12297 };
12298 
12299 struct mlx5_ifc_encryption_key_obj_bits {
12300 	u8         modify_field_select[0x40];
12301 
12302 	u8         state[0x8];
12303 	u8         sw_wrapped[0x1];
12304 	u8         reserved_at_49[0xb];
12305 	u8         key_size[0x4];
12306 	u8         reserved_at_58[0x4];
12307 	u8         key_purpose[0x4];
12308 
12309 	u8         reserved_at_60[0x8];
12310 	u8         pd[0x18];
12311 
12312 	u8         reserved_at_80[0x100];
12313 
12314 	u8         opaque[0x40];
12315 
12316 	u8         reserved_at_1c0[0x40];
12317 
12318 	u8         key[8][0x80];
12319 
12320 	u8         sw_wrapped_dek[8][0x80];
12321 
12322 	u8         reserved_at_a00[0x600];
12323 };
12324 
12325 struct mlx5_ifc_create_encryption_key_in_bits {
12326 	struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
12327 	struct mlx5_ifc_encryption_key_obj_bits encryption_key_object;
12328 };
12329 
12330 struct mlx5_ifc_modify_encryption_key_in_bits {
12331 	struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
12332 	struct mlx5_ifc_encryption_key_obj_bits encryption_key_object;
12333 };
12334 
12335 enum {
12336 	MLX5_FLOW_METER_MODE_BYTES_IP_LENGTH		= 0x0,
12337 	MLX5_FLOW_METER_MODE_BYTES_CALC_WITH_L2		= 0x1,
12338 	MLX5_FLOW_METER_MODE_BYTES_CALC_WITH_L2_IPG	= 0x2,
12339 	MLX5_FLOW_METER_MODE_NUM_PACKETS		= 0x3,
12340 };
12341 
12342 struct mlx5_ifc_flow_meter_parameters_bits {
12343 	u8         valid[0x1];
12344 	u8         bucket_overflow[0x1];
12345 	u8         start_color[0x2];
12346 	u8         both_buckets_on_green[0x1];
12347 	u8         reserved_at_5[0x1];
12348 	u8         meter_mode[0x2];
12349 	u8         reserved_at_8[0x18];
12350 
12351 	u8         reserved_at_20[0x20];
12352 
12353 	u8         reserved_at_40[0x3];
12354 	u8         cbs_exponent[0x5];
12355 	u8         cbs_mantissa[0x8];
12356 	u8         reserved_at_50[0x3];
12357 	u8         cir_exponent[0x5];
12358 	u8         cir_mantissa[0x8];
12359 
12360 	u8         reserved_at_60[0x20];
12361 
12362 	u8         reserved_at_80[0x3];
12363 	u8         ebs_exponent[0x5];
12364 	u8         ebs_mantissa[0x8];
12365 	u8         reserved_at_90[0x3];
12366 	u8         eir_exponent[0x5];
12367 	u8         eir_mantissa[0x8];
12368 
12369 	u8         reserved_at_a0[0x60];
12370 };
12371 
12372 struct mlx5_ifc_flow_meter_aso_obj_bits {
12373 	u8         modify_field_select[0x40];
12374 
12375 	u8         reserved_at_40[0x40];
12376 
12377 	u8         reserved_at_80[0x8];
12378 	u8         meter_aso_access_pd[0x18];
12379 
12380 	u8         reserved_at_a0[0x160];
12381 
12382 	struct mlx5_ifc_flow_meter_parameters_bits flow_meter_parameters[2];
12383 };
12384 
12385 struct mlx5_ifc_create_flow_meter_aso_obj_in_bits {
12386 	struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
12387 	struct mlx5_ifc_flow_meter_aso_obj_bits flow_meter_aso_obj;
12388 };
12389 
12390 struct mlx5_ifc_int_kek_obj_bits {
12391 	u8         modify_field_select[0x40];
12392 
12393 	u8         state[0x8];
12394 	u8         auto_gen[0x1];
12395 	u8         reserved_at_49[0xb];
12396 	u8         key_size[0x4];
12397 	u8         reserved_at_58[0x8];
12398 
12399 	u8         reserved_at_60[0x8];
12400 	u8         pd[0x18];
12401 
12402 	u8         reserved_at_80[0x180];
12403 	u8         key[8][0x80];
12404 
12405 	u8         reserved_at_600[0x200];
12406 };
12407 
12408 struct mlx5_ifc_create_int_kek_obj_in_bits {
12409 	struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
12410 	struct mlx5_ifc_int_kek_obj_bits int_kek_object;
12411 };
12412 
12413 struct mlx5_ifc_create_int_kek_obj_out_bits {
12414 	struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr;
12415 	struct mlx5_ifc_int_kek_obj_bits int_kek_object;
12416 };
12417 
12418 struct mlx5_ifc_sampler_obj_bits {
12419 	u8         modify_field_select[0x40];
12420 
12421 	u8         table_type[0x8];
12422 	u8         level[0x8];
12423 	u8         reserved_at_50[0xf];
12424 	u8         ignore_flow_level[0x1];
12425 
12426 	u8         sample_ratio[0x20];
12427 
12428 	u8         reserved_at_80[0x8];
12429 	u8         sample_table_id[0x18];
12430 
12431 	u8         reserved_at_a0[0x8];
12432 	u8         default_table_id[0x18];
12433 
12434 	u8         sw_steering_icm_address_rx[0x40];
12435 	u8         sw_steering_icm_address_tx[0x40];
12436 
12437 	u8         reserved_at_140[0xa0];
12438 };
12439 
12440 struct mlx5_ifc_create_sampler_obj_in_bits {
12441 	struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
12442 	struct mlx5_ifc_sampler_obj_bits sampler_object;
12443 };
12444 
12445 struct mlx5_ifc_query_sampler_obj_out_bits {
12446 	struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr;
12447 	struct mlx5_ifc_sampler_obj_bits sampler_object;
12448 };
12449 
12450 enum {
12451 	MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_128 = 0x0,
12452 	MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_256 = 0x1,
12453 };
12454 
12455 enum {
12456 	MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_PURPOSE_TLS = 0x1,
12457 	MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_PURPOSE_IPSEC = 0x2,
12458 	MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_PURPOSE_MACSEC = 0x4,
12459 };
12460 
12461 struct mlx5_ifc_tls_static_params_bits {
12462 	u8         const_2[0x2];
12463 	u8         tls_version[0x4];
12464 	u8         const_1[0x2];
12465 	u8         reserved_at_8[0x14];
12466 	u8         encryption_standard[0x4];
12467 
12468 	u8         reserved_at_20[0x20];
12469 
12470 	u8         initial_record_number[0x40];
12471 
12472 	u8         resync_tcp_sn[0x20];
12473 
12474 	u8         gcm_iv[0x20];
12475 
12476 	u8         implicit_iv[0x40];
12477 
12478 	u8         reserved_at_100[0x8];
12479 	u8         dek_index[0x18];
12480 
12481 	u8         reserved_at_120[0xe0];
12482 };
12483 
12484 struct mlx5_ifc_tls_progress_params_bits {
12485 	u8         next_record_tcp_sn[0x20];
12486 
12487 	u8         hw_resync_tcp_sn[0x20];
12488 
12489 	u8         record_tracker_state[0x2];
12490 	u8         auth_state[0x2];
12491 	u8         reserved_at_44[0x4];
12492 	u8         hw_offset_record_number[0x18];
12493 };
12494 
12495 enum {
12496 	MLX5_MTT_PERM_READ	= 1 << 0,
12497 	MLX5_MTT_PERM_WRITE	= 1 << 1,
12498 	MLX5_MTT_PERM_RW	= MLX5_MTT_PERM_READ | MLX5_MTT_PERM_WRITE,
12499 };
12500 
12501 enum {
12502 	MLX5_SUSPEND_VHCA_IN_OP_MOD_SUSPEND_INITIATOR  = 0x0,
12503 	MLX5_SUSPEND_VHCA_IN_OP_MOD_SUSPEND_RESPONDER  = 0x1,
12504 };
12505 
12506 struct mlx5_ifc_suspend_vhca_in_bits {
12507 	u8         opcode[0x10];
12508 	u8         uid[0x10];
12509 
12510 	u8         reserved_at_20[0x10];
12511 	u8         op_mod[0x10];
12512 
12513 	u8         reserved_at_40[0x10];
12514 	u8         vhca_id[0x10];
12515 
12516 	u8         reserved_at_60[0x20];
12517 };
12518 
12519 struct mlx5_ifc_suspend_vhca_out_bits {
12520 	u8         status[0x8];
12521 	u8         reserved_at_8[0x18];
12522 
12523 	u8         syndrome[0x20];
12524 
12525 	u8         reserved_at_40[0x40];
12526 };
12527 
12528 enum {
12529 	MLX5_RESUME_VHCA_IN_OP_MOD_RESUME_RESPONDER  = 0x0,
12530 	MLX5_RESUME_VHCA_IN_OP_MOD_RESUME_INITIATOR  = 0x1,
12531 };
12532 
12533 struct mlx5_ifc_resume_vhca_in_bits {
12534 	u8         opcode[0x10];
12535 	u8         uid[0x10];
12536 
12537 	u8         reserved_at_20[0x10];
12538 	u8         op_mod[0x10];
12539 
12540 	u8         reserved_at_40[0x10];
12541 	u8         vhca_id[0x10];
12542 
12543 	u8         reserved_at_60[0x20];
12544 };
12545 
12546 struct mlx5_ifc_resume_vhca_out_bits {
12547 	u8         status[0x8];
12548 	u8         reserved_at_8[0x18];
12549 
12550 	u8         syndrome[0x20];
12551 
12552 	u8         reserved_at_40[0x40];
12553 };
12554 
12555 struct mlx5_ifc_query_vhca_migration_state_in_bits {
12556 	u8         opcode[0x10];
12557 	u8         uid[0x10];
12558 
12559 	u8         reserved_at_20[0x10];
12560 	u8         op_mod[0x10];
12561 
12562 	u8         incremental[0x1];
12563 	u8         chunk[0x1];
12564 	u8         reserved_at_42[0xe];
12565 	u8         vhca_id[0x10];
12566 
12567 	u8         reserved_at_60[0x20];
12568 };
12569 
12570 struct mlx5_ifc_query_vhca_migration_state_out_bits {
12571 	u8         status[0x8];
12572 	u8         reserved_at_8[0x18];
12573 
12574 	u8         syndrome[0x20];
12575 
12576 	u8         reserved_at_40[0x40];
12577 
12578 	u8         required_umem_size[0x20];
12579 
12580 	u8         reserved_at_a0[0x20];
12581 
12582 	u8         remaining_total_size[0x40];
12583 
12584 	u8         reserved_at_100[0x100];
12585 };
12586 
12587 struct mlx5_ifc_save_vhca_state_in_bits {
12588 	u8         opcode[0x10];
12589 	u8         uid[0x10];
12590 
12591 	u8         reserved_at_20[0x10];
12592 	u8         op_mod[0x10];
12593 
12594 	u8         incremental[0x1];
12595 	u8         set_track[0x1];
12596 	u8         reserved_at_42[0xe];
12597 	u8         vhca_id[0x10];
12598 
12599 	u8         reserved_at_60[0x20];
12600 
12601 	u8         va[0x40];
12602 
12603 	u8         mkey[0x20];
12604 
12605 	u8         size[0x20];
12606 };
12607 
12608 struct mlx5_ifc_save_vhca_state_out_bits {
12609 	u8         status[0x8];
12610 	u8         reserved_at_8[0x18];
12611 
12612 	u8         syndrome[0x20];
12613 
12614 	u8         actual_image_size[0x20];
12615 
12616 	u8         next_required_umem_size[0x20];
12617 };
12618 
12619 struct mlx5_ifc_load_vhca_state_in_bits {
12620 	u8         opcode[0x10];
12621 	u8         uid[0x10];
12622 
12623 	u8         reserved_at_20[0x10];
12624 	u8         op_mod[0x10];
12625 
12626 	u8         reserved_at_40[0x10];
12627 	u8         vhca_id[0x10];
12628 
12629 	u8         reserved_at_60[0x20];
12630 
12631 	u8         va[0x40];
12632 
12633 	u8         mkey[0x20];
12634 
12635 	u8         size[0x20];
12636 };
12637 
12638 struct mlx5_ifc_load_vhca_state_out_bits {
12639 	u8         status[0x8];
12640 	u8         reserved_at_8[0x18];
12641 
12642 	u8         syndrome[0x20];
12643 
12644 	u8         reserved_at_40[0x40];
12645 };
12646 
12647 struct mlx5_ifc_adv_virtualization_cap_bits {
12648 	u8         reserved_at_0[0x3];
12649 	u8         pg_track_log_max_num[0x5];
12650 	u8         pg_track_max_num_range[0x8];
12651 	u8         pg_track_log_min_addr_space[0x8];
12652 	u8         pg_track_log_max_addr_space[0x8];
12653 
12654 	u8         reserved_at_20[0x3];
12655 	u8         pg_track_log_min_msg_size[0x5];
12656 	u8         reserved_at_28[0x3];
12657 	u8         pg_track_log_max_msg_size[0x5];
12658 	u8         reserved_at_30[0x3];
12659 	u8         pg_track_log_min_page_size[0x5];
12660 	u8         reserved_at_38[0x3];
12661 	u8         pg_track_log_max_page_size[0x5];
12662 
12663 	u8         reserved_at_40[0x7c0];
12664 };
12665 
12666 struct mlx5_ifc_page_track_report_entry_bits {
12667 	u8         dirty_address_high[0x20];
12668 
12669 	u8         dirty_address_low[0x20];
12670 };
12671 
12672 enum {
12673 	MLX5_PAGE_TRACK_STATE_TRACKING,
12674 	MLX5_PAGE_TRACK_STATE_REPORTING,
12675 	MLX5_PAGE_TRACK_STATE_ERROR,
12676 };
12677 
12678 struct mlx5_ifc_page_track_range_bits {
12679 	u8         start_address[0x40];
12680 
12681 	u8         length[0x40];
12682 };
12683 
12684 struct mlx5_ifc_page_track_bits {
12685 	u8         modify_field_select[0x40];
12686 
12687 	u8         reserved_at_40[0x10];
12688 	u8         vhca_id[0x10];
12689 
12690 	u8         reserved_at_60[0x20];
12691 
12692 	u8         state[0x4];
12693 	u8         track_type[0x4];
12694 	u8         log_addr_space_size[0x8];
12695 	u8         reserved_at_90[0x3];
12696 	u8         log_page_size[0x5];
12697 	u8         reserved_at_98[0x3];
12698 	u8         log_msg_size[0x5];
12699 
12700 	u8         reserved_at_a0[0x8];
12701 	u8         reporting_qpn[0x18];
12702 
12703 	u8         reserved_at_c0[0x18];
12704 	u8         num_ranges[0x8];
12705 
12706 	u8         reserved_at_e0[0x20];
12707 
12708 	u8         range_start_address[0x40];
12709 
12710 	u8         length[0x40];
12711 
12712 	struct     mlx5_ifc_page_track_range_bits track_range[0];
12713 };
12714 
12715 struct mlx5_ifc_create_page_track_obj_in_bits {
12716 	struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
12717 	struct mlx5_ifc_page_track_bits obj_context;
12718 };
12719 
12720 struct mlx5_ifc_modify_page_track_obj_in_bits {
12721 	struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
12722 	struct mlx5_ifc_page_track_bits obj_context;
12723 };
12724 
12725 struct mlx5_ifc_query_page_track_obj_out_bits {
12726 	struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr;
12727 	struct mlx5_ifc_page_track_bits obj_context;
12728 };
12729 
12730 struct mlx5_ifc_msecq_reg_bits {
12731 	u8         reserved_at_0[0x20];
12732 
12733 	u8         reserved_at_20[0x12];
12734 	u8         network_option[0x2];
12735 	u8         local_ssm_code[0x4];
12736 	u8         local_enhanced_ssm_code[0x8];
12737 
12738 	u8         local_clock_identity[0x40];
12739 
12740 	u8         reserved_at_80[0x180];
12741 };
12742 
12743 enum {
12744 	MLX5_MSEES_FIELD_SELECT_ENABLE			= BIT(0),
12745 	MLX5_MSEES_FIELD_SELECT_ADMIN_STATUS		= BIT(1),
12746 	MLX5_MSEES_FIELD_SELECT_ADMIN_FREQ_MEASURE	= BIT(2),
12747 };
12748 
12749 enum mlx5_msees_admin_status {
12750 	MLX5_MSEES_ADMIN_STATUS_FREE_RUNNING		= 0x0,
12751 	MLX5_MSEES_ADMIN_STATUS_TRACK			= 0x1,
12752 };
12753 
12754 enum mlx5_msees_oper_status {
12755 	MLX5_MSEES_OPER_STATUS_FREE_RUNNING		= 0x0,
12756 	MLX5_MSEES_OPER_STATUS_SELF_TRACK		= 0x1,
12757 	MLX5_MSEES_OPER_STATUS_OTHER_TRACK		= 0x2,
12758 	MLX5_MSEES_OPER_STATUS_HOLDOVER			= 0x3,
12759 	MLX5_MSEES_OPER_STATUS_FAIL_HOLDOVER		= 0x4,
12760 	MLX5_MSEES_OPER_STATUS_FAIL_FREE_RUNNING	= 0x5,
12761 };
12762 
12763 enum mlx5_msees_failure_reason {
12764 	MLX5_MSEES_FAILURE_REASON_UNDEFINED_ERROR		= 0x0,
12765 	MLX5_MSEES_FAILURE_REASON_PORT_DOWN			= 0x1,
12766 	MLX5_MSEES_FAILURE_REASON_TOO_HIGH_FREQUENCY_DIFF	= 0x2,
12767 	MLX5_MSEES_FAILURE_REASON_NET_SYNCHRONIZER_DEVICE_ERROR	= 0x3,
12768 	MLX5_MSEES_FAILURE_REASON_LACK_OF_RESOURCES		= 0x4,
12769 };
12770 
12771 struct mlx5_ifc_msees_reg_bits {
12772 	u8         reserved_at_0[0x8];
12773 	u8         local_port[0x8];
12774 	u8         pnat[0x2];
12775 	u8         lp_msb[0x2];
12776 	u8         reserved_at_14[0xc];
12777 
12778 	u8         field_select[0x20];
12779 
12780 	u8         admin_status[0x4];
12781 	u8         oper_status[0x4];
12782 	u8         ho_acq[0x1];
12783 	u8         reserved_at_49[0xc];
12784 	u8         admin_freq_measure[0x1];
12785 	u8         oper_freq_measure[0x1];
12786 	u8         failure_reason[0x9];
12787 
12788 	u8         frequency_diff[0x20];
12789 
12790 	u8         reserved_at_80[0x180];
12791 };
12792 
12793 #endif /* MLX5_IFC_H */
12794