1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 #ifndef MLX5_IFC_H 33 #define MLX5_IFC_H 34 35 #include "mlx5_ifc_fpga.h" 36 37 enum { 38 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0, 39 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1, 40 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2, 41 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3, 42 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13, 43 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14, 44 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c, 45 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d, 46 MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4, 47 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5, 48 MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED = 0x7, 49 MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT = 0xc, 50 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10, 51 MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR = 0x11, 52 MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR = 0x12, 53 MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR = 0x8, 54 MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE = 0x9, 55 MLX5_EVENT_TYPE_CODING_GPIO_EVENT = 0x15, 56 MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19, 57 MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a, 58 MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT = 0x1b, 59 MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT = 0x1f, 60 MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa, 61 MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb, 62 MLX5_EVENT_TYPE_CODING_FPGA_ERROR = 0x20, 63 MLX5_EVENT_TYPE_CODING_FPGA_QP_ERROR = 0x21 64 }; 65 66 enum { 67 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0, 68 MLX5_SET_HCA_CAP_OP_MOD_ODP = 0x2, 69 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3, 70 MLX5_SET_HCA_CAP_OP_MOD_ROCE = 0x4, 71 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE2 = 0x20, 72 MLX5_SET_HCA_CAP_OP_MODE_PORT_SELECTION = 0x25, 73 }; 74 75 enum { 76 MLX5_SHARED_RESOURCE_UID = 0xffff, 77 }; 78 79 enum { 80 MLX5_OBJ_TYPE_SW_ICM = 0x0008, 81 }; 82 83 enum { 84 MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM = (1ULL << MLX5_OBJ_TYPE_SW_ICM), 85 MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT = (1ULL << 11), 86 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q = (1ULL << 13), 87 MLX5_GENERAL_OBJ_TYPES_CAP_MACSEC_OFFLOAD = (1ULL << 39), 88 }; 89 90 enum { 91 MLX5_OBJ_TYPE_GENEVE_TLV_OPT = 0x000b, 92 MLX5_OBJ_TYPE_VIRTIO_NET_Q = 0x000d, 93 MLX5_OBJ_TYPE_VIRTIO_Q_COUNTERS = 0x001c, 94 MLX5_OBJ_TYPE_MATCH_DEFINER = 0x0018, 95 MLX5_OBJ_TYPE_PAGE_TRACK = 0x46, 96 MLX5_OBJ_TYPE_MKEY = 0xff01, 97 MLX5_OBJ_TYPE_QP = 0xff02, 98 MLX5_OBJ_TYPE_PSV = 0xff03, 99 MLX5_OBJ_TYPE_RMP = 0xff04, 100 MLX5_OBJ_TYPE_XRC_SRQ = 0xff05, 101 MLX5_OBJ_TYPE_RQ = 0xff06, 102 MLX5_OBJ_TYPE_SQ = 0xff07, 103 MLX5_OBJ_TYPE_TIR = 0xff08, 104 MLX5_OBJ_TYPE_TIS = 0xff09, 105 MLX5_OBJ_TYPE_DCT = 0xff0a, 106 MLX5_OBJ_TYPE_XRQ = 0xff0b, 107 MLX5_OBJ_TYPE_RQT = 0xff0e, 108 MLX5_OBJ_TYPE_FLOW_COUNTER = 0xff0f, 109 MLX5_OBJ_TYPE_CQ = 0xff10, 110 }; 111 112 enum { 113 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100, 114 MLX5_CMD_OP_QUERY_ADAPTER = 0x101, 115 MLX5_CMD_OP_INIT_HCA = 0x102, 116 MLX5_CMD_OP_TEARDOWN_HCA = 0x103, 117 MLX5_CMD_OP_ENABLE_HCA = 0x104, 118 MLX5_CMD_OP_DISABLE_HCA = 0x105, 119 MLX5_CMD_OP_QUERY_PAGES = 0x107, 120 MLX5_CMD_OP_MANAGE_PAGES = 0x108, 121 MLX5_CMD_OP_SET_HCA_CAP = 0x109, 122 MLX5_CMD_OP_QUERY_ISSI = 0x10a, 123 MLX5_CMD_OP_SET_ISSI = 0x10b, 124 MLX5_CMD_OP_SET_DRIVER_VERSION = 0x10d, 125 MLX5_CMD_OP_QUERY_SF_PARTITION = 0x111, 126 MLX5_CMD_OP_ALLOC_SF = 0x113, 127 MLX5_CMD_OP_DEALLOC_SF = 0x114, 128 MLX5_CMD_OP_SUSPEND_VHCA = 0x115, 129 MLX5_CMD_OP_RESUME_VHCA = 0x116, 130 MLX5_CMD_OP_QUERY_VHCA_MIGRATION_STATE = 0x117, 131 MLX5_CMD_OP_SAVE_VHCA_STATE = 0x118, 132 MLX5_CMD_OP_LOAD_VHCA_STATE = 0x119, 133 MLX5_CMD_OP_CREATE_MKEY = 0x200, 134 MLX5_CMD_OP_QUERY_MKEY = 0x201, 135 MLX5_CMD_OP_DESTROY_MKEY = 0x202, 136 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203, 137 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204, 138 MLX5_CMD_OP_ALLOC_MEMIC = 0x205, 139 MLX5_CMD_OP_DEALLOC_MEMIC = 0x206, 140 MLX5_CMD_OP_MODIFY_MEMIC = 0x207, 141 MLX5_CMD_OP_CREATE_EQ = 0x301, 142 MLX5_CMD_OP_DESTROY_EQ = 0x302, 143 MLX5_CMD_OP_QUERY_EQ = 0x303, 144 MLX5_CMD_OP_GEN_EQE = 0x304, 145 MLX5_CMD_OP_CREATE_CQ = 0x400, 146 MLX5_CMD_OP_DESTROY_CQ = 0x401, 147 MLX5_CMD_OP_QUERY_CQ = 0x402, 148 MLX5_CMD_OP_MODIFY_CQ = 0x403, 149 MLX5_CMD_OP_CREATE_QP = 0x500, 150 MLX5_CMD_OP_DESTROY_QP = 0x501, 151 MLX5_CMD_OP_RST2INIT_QP = 0x502, 152 MLX5_CMD_OP_INIT2RTR_QP = 0x503, 153 MLX5_CMD_OP_RTR2RTS_QP = 0x504, 154 MLX5_CMD_OP_RTS2RTS_QP = 0x505, 155 MLX5_CMD_OP_SQERR2RTS_QP = 0x506, 156 MLX5_CMD_OP_2ERR_QP = 0x507, 157 MLX5_CMD_OP_2RST_QP = 0x50a, 158 MLX5_CMD_OP_QUERY_QP = 0x50b, 159 MLX5_CMD_OP_SQD_RTS_QP = 0x50c, 160 MLX5_CMD_OP_INIT2INIT_QP = 0x50e, 161 MLX5_CMD_OP_CREATE_PSV = 0x600, 162 MLX5_CMD_OP_DESTROY_PSV = 0x601, 163 MLX5_CMD_OP_CREATE_SRQ = 0x700, 164 MLX5_CMD_OP_DESTROY_SRQ = 0x701, 165 MLX5_CMD_OP_QUERY_SRQ = 0x702, 166 MLX5_CMD_OP_ARM_RQ = 0x703, 167 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705, 168 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706, 169 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707, 170 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708, 171 MLX5_CMD_OP_CREATE_DCT = 0x710, 172 MLX5_CMD_OP_DESTROY_DCT = 0x711, 173 MLX5_CMD_OP_DRAIN_DCT = 0x712, 174 MLX5_CMD_OP_QUERY_DCT = 0x713, 175 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714, 176 MLX5_CMD_OP_CREATE_XRQ = 0x717, 177 MLX5_CMD_OP_DESTROY_XRQ = 0x718, 178 MLX5_CMD_OP_QUERY_XRQ = 0x719, 179 MLX5_CMD_OP_ARM_XRQ = 0x71a, 180 MLX5_CMD_OP_QUERY_XRQ_DC_PARAMS_ENTRY = 0x725, 181 MLX5_CMD_OP_SET_XRQ_DC_PARAMS_ENTRY = 0x726, 182 MLX5_CMD_OP_QUERY_XRQ_ERROR_PARAMS = 0x727, 183 MLX5_CMD_OP_RELEASE_XRQ_ERROR = 0x729, 184 MLX5_CMD_OP_MODIFY_XRQ = 0x72a, 185 MLX5_CMD_OP_QUERY_ESW_FUNCTIONS = 0x740, 186 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750, 187 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751, 188 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752, 189 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753, 190 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754, 191 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755, 192 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760, 193 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761, 194 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762, 195 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763, 196 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764, 197 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765, 198 MLX5_CMD_OP_QUERY_VNIC_ENV = 0x76f, 199 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770, 200 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771, 201 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772, 202 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773, 203 MLX5_CMD_OP_SET_MONITOR_COUNTER = 0x774, 204 MLX5_CMD_OP_ARM_MONITOR_COUNTER = 0x775, 205 MLX5_CMD_OP_SET_PP_RATE_LIMIT = 0x780, 206 MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781, 207 MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT = 0x782, 208 MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT = 0x783, 209 MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT = 0x784, 210 MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT = 0x785, 211 MLX5_CMD_OP_CREATE_QOS_PARA_VPORT = 0x786, 212 MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT = 0x787, 213 MLX5_CMD_OP_ALLOC_PD = 0x800, 214 MLX5_CMD_OP_DEALLOC_PD = 0x801, 215 MLX5_CMD_OP_ALLOC_UAR = 0x802, 216 MLX5_CMD_OP_DEALLOC_UAR = 0x803, 217 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804, 218 MLX5_CMD_OP_ACCESS_REG = 0x805, 219 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806, 220 MLX5_CMD_OP_DETACH_FROM_MCG = 0x807, 221 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a, 222 MLX5_CMD_OP_MAD_IFC = 0x50d, 223 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b, 224 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c, 225 MLX5_CMD_OP_NOP = 0x80d, 226 MLX5_CMD_OP_ALLOC_XRCD = 0x80e, 227 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f, 228 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816, 229 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817, 230 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822, 231 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823, 232 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824, 233 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825, 234 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826, 235 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827, 236 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828, 237 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829, 238 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a, 239 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b, 240 MLX5_CMD_OP_SET_WOL_ROL = 0x830, 241 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831, 242 MLX5_CMD_OP_CREATE_LAG = 0x840, 243 MLX5_CMD_OP_MODIFY_LAG = 0x841, 244 MLX5_CMD_OP_QUERY_LAG = 0x842, 245 MLX5_CMD_OP_DESTROY_LAG = 0x843, 246 MLX5_CMD_OP_CREATE_VPORT_LAG = 0x844, 247 MLX5_CMD_OP_DESTROY_VPORT_LAG = 0x845, 248 MLX5_CMD_OP_CREATE_TIR = 0x900, 249 MLX5_CMD_OP_MODIFY_TIR = 0x901, 250 MLX5_CMD_OP_DESTROY_TIR = 0x902, 251 MLX5_CMD_OP_QUERY_TIR = 0x903, 252 MLX5_CMD_OP_CREATE_SQ = 0x904, 253 MLX5_CMD_OP_MODIFY_SQ = 0x905, 254 MLX5_CMD_OP_DESTROY_SQ = 0x906, 255 MLX5_CMD_OP_QUERY_SQ = 0x907, 256 MLX5_CMD_OP_CREATE_RQ = 0x908, 257 MLX5_CMD_OP_MODIFY_RQ = 0x909, 258 MLX5_CMD_OP_SET_DELAY_DROP_PARAMS = 0x910, 259 MLX5_CMD_OP_DESTROY_RQ = 0x90a, 260 MLX5_CMD_OP_QUERY_RQ = 0x90b, 261 MLX5_CMD_OP_CREATE_RMP = 0x90c, 262 MLX5_CMD_OP_MODIFY_RMP = 0x90d, 263 MLX5_CMD_OP_DESTROY_RMP = 0x90e, 264 MLX5_CMD_OP_QUERY_RMP = 0x90f, 265 MLX5_CMD_OP_CREATE_TIS = 0x912, 266 MLX5_CMD_OP_MODIFY_TIS = 0x913, 267 MLX5_CMD_OP_DESTROY_TIS = 0x914, 268 MLX5_CMD_OP_QUERY_TIS = 0x915, 269 MLX5_CMD_OP_CREATE_RQT = 0x916, 270 MLX5_CMD_OP_MODIFY_RQT = 0x917, 271 MLX5_CMD_OP_DESTROY_RQT = 0x918, 272 MLX5_CMD_OP_QUERY_RQT = 0x919, 273 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f, 274 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930, 275 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931, 276 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932, 277 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933, 278 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934, 279 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935, 280 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936, 281 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937, 282 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938, 283 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939, 284 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a, 285 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b, 286 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c, 287 MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT = 0x93d, 288 MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT = 0x93e, 289 MLX5_CMD_OP_QUERY_PACKET_REFORMAT_CONTEXT = 0x93f, 290 MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT = 0x940, 291 MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941, 292 MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT = 0x942, 293 MLX5_CMD_OP_FPGA_CREATE_QP = 0x960, 294 MLX5_CMD_OP_FPGA_MODIFY_QP = 0x961, 295 MLX5_CMD_OP_FPGA_QUERY_QP = 0x962, 296 MLX5_CMD_OP_FPGA_DESTROY_QP = 0x963, 297 MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS = 0x964, 298 MLX5_CMD_OP_CREATE_GENERAL_OBJECT = 0xa00, 299 MLX5_CMD_OP_MODIFY_GENERAL_OBJECT = 0xa01, 300 MLX5_CMD_OP_QUERY_GENERAL_OBJECT = 0xa02, 301 MLX5_CMD_OP_DESTROY_GENERAL_OBJECT = 0xa03, 302 MLX5_CMD_OP_CREATE_UCTX = 0xa04, 303 MLX5_CMD_OP_DESTROY_UCTX = 0xa06, 304 MLX5_CMD_OP_CREATE_UMEM = 0xa08, 305 MLX5_CMD_OP_DESTROY_UMEM = 0xa0a, 306 MLX5_CMD_OP_SYNC_STEERING = 0xb00, 307 MLX5_CMD_OP_QUERY_VHCA_STATE = 0xb0d, 308 MLX5_CMD_OP_MODIFY_VHCA_STATE = 0xb0e, 309 MLX5_CMD_OP_SYNC_CRYPTO = 0xb12, 310 MLX5_CMD_OP_MAX 311 }; 312 313 /* Valid range for general commands that don't work over an object */ 314 enum { 315 MLX5_CMD_OP_GENERAL_START = 0xb00, 316 MLX5_CMD_OP_GENERAL_END = 0xd00, 317 }; 318 319 enum { 320 MLX5_FT_NIC_RX_2_NIC_RX_RDMA = BIT(0), 321 MLX5_FT_NIC_TX_RDMA_2_NIC_TX = BIT(1), 322 }; 323 324 struct mlx5_ifc_flow_table_fields_supported_bits { 325 u8 outer_dmac[0x1]; 326 u8 outer_smac[0x1]; 327 u8 outer_ether_type[0x1]; 328 u8 outer_ip_version[0x1]; 329 u8 outer_first_prio[0x1]; 330 u8 outer_first_cfi[0x1]; 331 u8 outer_first_vid[0x1]; 332 u8 outer_ipv4_ttl[0x1]; 333 u8 outer_second_prio[0x1]; 334 u8 outer_second_cfi[0x1]; 335 u8 outer_second_vid[0x1]; 336 u8 reserved_at_b[0x1]; 337 u8 outer_sip[0x1]; 338 u8 outer_dip[0x1]; 339 u8 outer_frag[0x1]; 340 u8 outer_ip_protocol[0x1]; 341 u8 outer_ip_ecn[0x1]; 342 u8 outer_ip_dscp[0x1]; 343 u8 outer_udp_sport[0x1]; 344 u8 outer_udp_dport[0x1]; 345 u8 outer_tcp_sport[0x1]; 346 u8 outer_tcp_dport[0x1]; 347 u8 outer_tcp_flags[0x1]; 348 u8 outer_gre_protocol[0x1]; 349 u8 outer_gre_key[0x1]; 350 u8 outer_vxlan_vni[0x1]; 351 u8 outer_geneve_vni[0x1]; 352 u8 outer_geneve_oam[0x1]; 353 u8 outer_geneve_protocol_type[0x1]; 354 u8 outer_geneve_opt_len[0x1]; 355 u8 source_vhca_port[0x1]; 356 u8 source_eswitch_port[0x1]; 357 358 u8 inner_dmac[0x1]; 359 u8 inner_smac[0x1]; 360 u8 inner_ether_type[0x1]; 361 u8 inner_ip_version[0x1]; 362 u8 inner_first_prio[0x1]; 363 u8 inner_first_cfi[0x1]; 364 u8 inner_first_vid[0x1]; 365 u8 reserved_at_27[0x1]; 366 u8 inner_second_prio[0x1]; 367 u8 inner_second_cfi[0x1]; 368 u8 inner_second_vid[0x1]; 369 u8 reserved_at_2b[0x1]; 370 u8 inner_sip[0x1]; 371 u8 inner_dip[0x1]; 372 u8 inner_frag[0x1]; 373 u8 inner_ip_protocol[0x1]; 374 u8 inner_ip_ecn[0x1]; 375 u8 inner_ip_dscp[0x1]; 376 u8 inner_udp_sport[0x1]; 377 u8 inner_udp_dport[0x1]; 378 u8 inner_tcp_sport[0x1]; 379 u8 inner_tcp_dport[0x1]; 380 u8 inner_tcp_flags[0x1]; 381 u8 reserved_at_37[0x9]; 382 383 u8 geneve_tlv_option_0_data[0x1]; 384 u8 geneve_tlv_option_0_exist[0x1]; 385 u8 reserved_at_42[0x3]; 386 u8 outer_first_mpls_over_udp[0x4]; 387 u8 outer_first_mpls_over_gre[0x4]; 388 u8 inner_first_mpls[0x4]; 389 u8 outer_first_mpls[0x4]; 390 u8 reserved_at_55[0x2]; 391 u8 outer_esp_spi[0x1]; 392 u8 reserved_at_58[0x2]; 393 u8 bth_dst_qp[0x1]; 394 u8 reserved_at_5b[0x5]; 395 396 u8 reserved_at_60[0x18]; 397 u8 metadata_reg_c_7[0x1]; 398 u8 metadata_reg_c_6[0x1]; 399 u8 metadata_reg_c_5[0x1]; 400 u8 metadata_reg_c_4[0x1]; 401 u8 metadata_reg_c_3[0x1]; 402 u8 metadata_reg_c_2[0x1]; 403 u8 metadata_reg_c_1[0x1]; 404 u8 metadata_reg_c_0[0x1]; 405 }; 406 407 struct mlx5_ifc_flow_table_fields_supported_2_bits { 408 u8 reserved_at_0[0xe]; 409 u8 bth_opcode[0x1]; 410 u8 reserved_at_f[0x11]; 411 412 u8 reserved_at_20[0x60]; 413 }; 414 415 struct mlx5_ifc_flow_table_prop_layout_bits { 416 u8 ft_support[0x1]; 417 u8 reserved_at_1[0x1]; 418 u8 flow_counter[0x1]; 419 u8 flow_modify_en[0x1]; 420 u8 modify_root[0x1]; 421 u8 identified_miss_table_mode[0x1]; 422 u8 flow_table_modify[0x1]; 423 u8 reformat[0x1]; 424 u8 decap[0x1]; 425 u8 reserved_at_9[0x1]; 426 u8 pop_vlan[0x1]; 427 u8 push_vlan[0x1]; 428 u8 reserved_at_c[0x1]; 429 u8 pop_vlan_2[0x1]; 430 u8 push_vlan_2[0x1]; 431 u8 reformat_and_vlan_action[0x1]; 432 u8 reserved_at_10[0x1]; 433 u8 sw_owner[0x1]; 434 u8 reformat_l3_tunnel_to_l2[0x1]; 435 u8 reformat_l2_to_l3_tunnel[0x1]; 436 u8 reformat_and_modify_action[0x1]; 437 u8 ignore_flow_level[0x1]; 438 u8 reserved_at_16[0x1]; 439 u8 table_miss_action_domain[0x1]; 440 u8 termination_table[0x1]; 441 u8 reformat_and_fwd_to_table[0x1]; 442 u8 reserved_at_1a[0x2]; 443 u8 ipsec_encrypt[0x1]; 444 u8 ipsec_decrypt[0x1]; 445 u8 sw_owner_v2[0x1]; 446 u8 reserved_at_1f[0x1]; 447 448 u8 termination_table_raw_traffic[0x1]; 449 u8 reserved_at_21[0x1]; 450 u8 log_max_ft_size[0x6]; 451 u8 log_max_modify_header_context[0x8]; 452 u8 max_modify_header_actions[0x8]; 453 u8 max_ft_level[0x8]; 454 455 u8 reformat_add_esp_trasport[0x1]; 456 u8 reserved_at_41[0x2]; 457 u8 reformat_del_esp_trasport[0x1]; 458 u8 reserved_at_44[0x2]; 459 u8 execute_aso[0x1]; 460 u8 reserved_at_47[0x19]; 461 462 u8 reserved_at_60[0x2]; 463 u8 reformat_insert[0x1]; 464 u8 reformat_remove[0x1]; 465 u8 macsec_encrypt[0x1]; 466 u8 macsec_decrypt[0x1]; 467 u8 reserved_at_66[0x2]; 468 u8 reformat_add_macsec[0x1]; 469 u8 reformat_remove_macsec[0x1]; 470 u8 reserved_at_6a[0xe]; 471 u8 log_max_ft_num[0x8]; 472 473 u8 reserved_at_80[0x10]; 474 u8 log_max_flow_counter[0x8]; 475 u8 log_max_destination[0x8]; 476 477 u8 reserved_at_a0[0x18]; 478 u8 log_max_flow[0x8]; 479 480 u8 reserved_at_c0[0x40]; 481 482 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support; 483 484 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support; 485 }; 486 487 struct mlx5_ifc_odp_per_transport_service_cap_bits { 488 u8 send[0x1]; 489 u8 receive[0x1]; 490 u8 write[0x1]; 491 u8 read[0x1]; 492 u8 atomic[0x1]; 493 u8 srq_receive[0x1]; 494 u8 reserved_at_6[0x1a]; 495 }; 496 497 struct mlx5_ifc_ipv4_layout_bits { 498 u8 reserved_at_0[0x60]; 499 500 u8 ipv4[0x20]; 501 }; 502 503 struct mlx5_ifc_ipv6_layout_bits { 504 u8 ipv6[16][0x8]; 505 }; 506 507 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits { 508 struct mlx5_ifc_ipv6_layout_bits ipv6_layout; 509 struct mlx5_ifc_ipv4_layout_bits ipv4_layout; 510 u8 reserved_at_0[0x80]; 511 }; 512 513 struct mlx5_ifc_fte_match_set_lyr_2_4_bits { 514 u8 smac_47_16[0x20]; 515 516 u8 smac_15_0[0x10]; 517 u8 ethertype[0x10]; 518 519 u8 dmac_47_16[0x20]; 520 521 u8 dmac_15_0[0x10]; 522 u8 first_prio[0x3]; 523 u8 first_cfi[0x1]; 524 u8 first_vid[0xc]; 525 526 u8 ip_protocol[0x8]; 527 u8 ip_dscp[0x6]; 528 u8 ip_ecn[0x2]; 529 u8 cvlan_tag[0x1]; 530 u8 svlan_tag[0x1]; 531 u8 frag[0x1]; 532 u8 ip_version[0x4]; 533 u8 tcp_flags[0x9]; 534 535 u8 tcp_sport[0x10]; 536 u8 tcp_dport[0x10]; 537 538 u8 reserved_at_c0[0x10]; 539 u8 ipv4_ihl[0x4]; 540 u8 reserved_at_c4[0x4]; 541 542 u8 ttl_hoplimit[0x8]; 543 544 u8 udp_sport[0x10]; 545 u8 udp_dport[0x10]; 546 547 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6; 548 549 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6; 550 }; 551 552 struct mlx5_ifc_nvgre_key_bits { 553 u8 hi[0x18]; 554 u8 lo[0x8]; 555 }; 556 557 union mlx5_ifc_gre_key_bits { 558 struct mlx5_ifc_nvgre_key_bits nvgre; 559 u8 key[0x20]; 560 }; 561 562 struct mlx5_ifc_fte_match_set_misc_bits { 563 u8 gre_c_present[0x1]; 564 u8 reserved_at_1[0x1]; 565 u8 gre_k_present[0x1]; 566 u8 gre_s_present[0x1]; 567 u8 source_vhca_port[0x4]; 568 u8 source_sqn[0x18]; 569 570 u8 source_eswitch_owner_vhca_id[0x10]; 571 u8 source_port[0x10]; 572 573 u8 outer_second_prio[0x3]; 574 u8 outer_second_cfi[0x1]; 575 u8 outer_second_vid[0xc]; 576 u8 inner_second_prio[0x3]; 577 u8 inner_second_cfi[0x1]; 578 u8 inner_second_vid[0xc]; 579 580 u8 outer_second_cvlan_tag[0x1]; 581 u8 inner_second_cvlan_tag[0x1]; 582 u8 outer_second_svlan_tag[0x1]; 583 u8 inner_second_svlan_tag[0x1]; 584 u8 reserved_at_64[0xc]; 585 u8 gre_protocol[0x10]; 586 587 union mlx5_ifc_gre_key_bits gre_key; 588 589 u8 vxlan_vni[0x18]; 590 u8 bth_opcode[0x8]; 591 592 u8 geneve_vni[0x18]; 593 u8 reserved_at_d8[0x6]; 594 u8 geneve_tlv_option_0_exist[0x1]; 595 u8 geneve_oam[0x1]; 596 597 u8 reserved_at_e0[0xc]; 598 u8 outer_ipv6_flow_label[0x14]; 599 600 u8 reserved_at_100[0xc]; 601 u8 inner_ipv6_flow_label[0x14]; 602 603 u8 reserved_at_120[0xa]; 604 u8 geneve_opt_len[0x6]; 605 u8 geneve_protocol_type[0x10]; 606 607 u8 reserved_at_140[0x8]; 608 u8 bth_dst_qp[0x18]; 609 u8 reserved_at_160[0x20]; 610 u8 outer_esp_spi[0x20]; 611 u8 reserved_at_1a0[0x60]; 612 }; 613 614 struct mlx5_ifc_fte_match_mpls_bits { 615 u8 mpls_label[0x14]; 616 u8 mpls_exp[0x3]; 617 u8 mpls_s_bos[0x1]; 618 u8 mpls_ttl[0x8]; 619 }; 620 621 struct mlx5_ifc_fte_match_set_misc2_bits { 622 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls; 623 624 struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls; 625 626 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre; 627 628 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp; 629 630 u8 metadata_reg_c_7[0x20]; 631 632 u8 metadata_reg_c_6[0x20]; 633 634 u8 metadata_reg_c_5[0x20]; 635 636 u8 metadata_reg_c_4[0x20]; 637 638 u8 metadata_reg_c_3[0x20]; 639 640 u8 metadata_reg_c_2[0x20]; 641 642 u8 metadata_reg_c_1[0x20]; 643 644 u8 metadata_reg_c_0[0x20]; 645 646 u8 metadata_reg_a[0x20]; 647 648 u8 reserved_at_1a0[0x8]; 649 650 u8 macsec_syndrome[0x8]; 651 u8 ipsec_syndrome[0x8]; 652 u8 reserved_at_1b8[0x8]; 653 654 u8 reserved_at_1c0[0x40]; 655 }; 656 657 struct mlx5_ifc_fte_match_set_misc3_bits { 658 u8 inner_tcp_seq_num[0x20]; 659 660 u8 outer_tcp_seq_num[0x20]; 661 662 u8 inner_tcp_ack_num[0x20]; 663 664 u8 outer_tcp_ack_num[0x20]; 665 666 u8 reserved_at_80[0x8]; 667 u8 outer_vxlan_gpe_vni[0x18]; 668 669 u8 outer_vxlan_gpe_next_protocol[0x8]; 670 u8 outer_vxlan_gpe_flags[0x8]; 671 u8 reserved_at_b0[0x10]; 672 673 u8 icmp_header_data[0x20]; 674 675 u8 icmpv6_header_data[0x20]; 676 677 u8 icmp_type[0x8]; 678 u8 icmp_code[0x8]; 679 u8 icmpv6_type[0x8]; 680 u8 icmpv6_code[0x8]; 681 682 u8 geneve_tlv_option_0_data[0x20]; 683 684 u8 gtpu_teid[0x20]; 685 686 u8 gtpu_msg_type[0x8]; 687 u8 gtpu_msg_flags[0x8]; 688 u8 reserved_at_170[0x10]; 689 690 u8 gtpu_dw_2[0x20]; 691 692 u8 gtpu_first_ext_dw_0[0x20]; 693 694 u8 gtpu_dw_0[0x20]; 695 696 u8 reserved_at_1e0[0x20]; 697 }; 698 699 struct mlx5_ifc_fte_match_set_misc4_bits { 700 u8 prog_sample_field_value_0[0x20]; 701 702 u8 prog_sample_field_id_0[0x20]; 703 704 u8 prog_sample_field_value_1[0x20]; 705 706 u8 prog_sample_field_id_1[0x20]; 707 708 u8 prog_sample_field_value_2[0x20]; 709 710 u8 prog_sample_field_id_2[0x20]; 711 712 u8 prog_sample_field_value_3[0x20]; 713 714 u8 prog_sample_field_id_3[0x20]; 715 716 u8 reserved_at_100[0x100]; 717 }; 718 719 struct mlx5_ifc_fte_match_set_misc5_bits { 720 u8 macsec_tag_0[0x20]; 721 722 u8 macsec_tag_1[0x20]; 723 724 u8 macsec_tag_2[0x20]; 725 726 u8 macsec_tag_3[0x20]; 727 728 u8 tunnel_header_0[0x20]; 729 730 u8 tunnel_header_1[0x20]; 731 732 u8 tunnel_header_2[0x20]; 733 734 u8 tunnel_header_3[0x20]; 735 736 u8 reserved_at_100[0x100]; 737 }; 738 739 struct mlx5_ifc_cmd_pas_bits { 740 u8 pa_h[0x20]; 741 742 u8 pa_l[0x14]; 743 u8 reserved_at_34[0xc]; 744 }; 745 746 struct mlx5_ifc_uint64_bits { 747 u8 hi[0x20]; 748 749 u8 lo[0x20]; 750 }; 751 752 enum { 753 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0, 754 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7, 755 MLX5_ADS_STAT_RATE_10GBPS = 0x8, 756 MLX5_ADS_STAT_RATE_30GBPS = 0x9, 757 MLX5_ADS_STAT_RATE_5GBPS = 0xa, 758 MLX5_ADS_STAT_RATE_20GBPS = 0xb, 759 MLX5_ADS_STAT_RATE_40GBPS = 0xc, 760 MLX5_ADS_STAT_RATE_60GBPS = 0xd, 761 MLX5_ADS_STAT_RATE_80GBPS = 0xe, 762 MLX5_ADS_STAT_RATE_120GBPS = 0xf, 763 }; 764 765 struct mlx5_ifc_ads_bits { 766 u8 fl[0x1]; 767 u8 free_ar[0x1]; 768 u8 reserved_at_2[0xe]; 769 u8 pkey_index[0x10]; 770 771 u8 reserved_at_20[0x8]; 772 u8 grh[0x1]; 773 u8 mlid[0x7]; 774 u8 rlid[0x10]; 775 776 u8 ack_timeout[0x5]; 777 u8 reserved_at_45[0x3]; 778 u8 src_addr_index[0x8]; 779 u8 reserved_at_50[0x4]; 780 u8 stat_rate[0x4]; 781 u8 hop_limit[0x8]; 782 783 u8 reserved_at_60[0x4]; 784 u8 tclass[0x8]; 785 u8 flow_label[0x14]; 786 787 u8 rgid_rip[16][0x8]; 788 789 u8 reserved_at_100[0x4]; 790 u8 f_dscp[0x1]; 791 u8 f_ecn[0x1]; 792 u8 reserved_at_106[0x1]; 793 u8 f_eth_prio[0x1]; 794 u8 ecn[0x2]; 795 u8 dscp[0x6]; 796 u8 udp_sport[0x10]; 797 798 u8 dei_cfi[0x1]; 799 u8 eth_prio[0x3]; 800 u8 sl[0x4]; 801 u8 vhca_port_num[0x8]; 802 u8 rmac_47_32[0x10]; 803 804 u8 rmac_31_0[0x20]; 805 }; 806 807 struct mlx5_ifc_flow_table_nic_cap_bits { 808 u8 nic_rx_multi_path_tirs[0x1]; 809 u8 nic_rx_multi_path_tirs_fts[0x1]; 810 u8 allow_sniffer_and_nic_rx_shared_tir[0x1]; 811 u8 reserved_at_3[0x4]; 812 u8 sw_owner_reformat_supported[0x1]; 813 u8 reserved_at_8[0x18]; 814 815 u8 encap_general_header[0x1]; 816 u8 reserved_at_21[0xa]; 817 u8 log_max_packet_reformat_context[0x5]; 818 u8 reserved_at_30[0x6]; 819 u8 max_encap_header_size[0xa]; 820 u8 reserved_at_40[0x1c0]; 821 822 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive; 823 824 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_rdma; 825 826 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer; 827 828 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit; 829 830 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_rdma; 831 832 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer; 833 834 u8 reserved_at_e00[0x700]; 835 836 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_receive_rdma; 837 838 u8 reserved_at_1580[0x280]; 839 840 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_transmit_rdma; 841 842 u8 reserved_at_1880[0x780]; 843 844 u8 sw_steering_nic_rx_action_drop_icm_address[0x40]; 845 846 u8 sw_steering_nic_tx_action_drop_icm_address[0x40]; 847 848 u8 sw_steering_nic_tx_action_allow_icm_address[0x40]; 849 850 u8 reserved_at_20c0[0x5f40]; 851 }; 852 853 struct mlx5_ifc_port_selection_cap_bits { 854 u8 reserved_at_0[0x10]; 855 u8 port_select_flow_table[0x1]; 856 u8 reserved_at_11[0x1]; 857 u8 port_select_flow_table_bypass[0x1]; 858 u8 reserved_at_13[0xd]; 859 860 u8 reserved_at_20[0x1e0]; 861 862 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_port_selection; 863 864 u8 reserved_at_400[0x7c00]; 865 }; 866 867 enum { 868 MLX5_FDB_TO_VPORT_REG_C_0 = 0x01, 869 MLX5_FDB_TO_VPORT_REG_C_1 = 0x02, 870 MLX5_FDB_TO_VPORT_REG_C_2 = 0x04, 871 MLX5_FDB_TO_VPORT_REG_C_3 = 0x08, 872 MLX5_FDB_TO_VPORT_REG_C_4 = 0x10, 873 MLX5_FDB_TO_VPORT_REG_C_5 = 0x20, 874 MLX5_FDB_TO_VPORT_REG_C_6 = 0x40, 875 MLX5_FDB_TO_VPORT_REG_C_7 = 0x80, 876 }; 877 878 struct mlx5_ifc_flow_table_eswitch_cap_bits { 879 u8 fdb_to_vport_reg_c_id[0x8]; 880 u8 reserved_at_8[0xd]; 881 u8 fdb_modify_header_fwd_to_table[0x1]; 882 u8 fdb_ipv4_ttl_modify[0x1]; 883 u8 flow_source[0x1]; 884 u8 reserved_at_18[0x2]; 885 u8 multi_fdb_encap[0x1]; 886 u8 egress_acl_forward_to_vport[0x1]; 887 u8 fdb_multi_path_to_table[0x1]; 888 u8 reserved_at_1d[0x3]; 889 890 u8 reserved_at_20[0x1e0]; 891 892 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb; 893 894 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress; 895 896 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress; 897 898 u8 reserved_at_800[0x1000]; 899 900 u8 sw_steering_fdb_action_drop_icm_address_rx[0x40]; 901 902 u8 sw_steering_fdb_action_drop_icm_address_tx[0x40]; 903 904 u8 sw_steering_uplink_icm_address_rx[0x40]; 905 906 u8 sw_steering_uplink_icm_address_tx[0x40]; 907 908 u8 reserved_at_1900[0x6700]; 909 }; 910 911 enum { 912 MLX5_COUNTER_SOURCE_ESWITCH = 0x0, 913 MLX5_COUNTER_FLOW_ESWITCH = 0x1, 914 }; 915 916 struct mlx5_ifc_e_switch_cap_bits { 917 u8 vport_svlan_strip[0x1]; 918 u8 vport_cvlan_strip[0x1]; 919 u8 vport_svlan_insert[0x1]; 920 u8 vport_cvlan_insert_if_not_exist[0x1]; 921 u8 vport_cvlan_insert_overwrite[0x1]; 922 u8 reserved_at_5[0x1]; 923 u8 vport_cvlan_insert_always[0x1]; 924 u8 esw_shared_ingress_acl[0x1]; 925 u8 esw_uplink_ingress_acl[0x1]; 926 u8 root_ft_on_other_esw[0x1]; 927 u8 reserved_at_a[0xf]; 928 u8 esw_functions_changed[0x1]; 929 u8 reserved_at_1a[0x1]; 930 u8 ecpf_vport_exists[0x1]; 931 u8 counter_eswitch_affinity[0x1]; 932 u8 merged_eswitch[0x1]; 933 u8 nic_vport_node_guid_modify[0x1]; 934 u8 nic_vport_port_guid_modify[0x1]; 935 936 u8 vxlan_encap_decap[0x1]; 937 u8 nvgre_encap_decap[0x1]; 938 u8 reserved_at_22[0x1]; 939 u8 log_max_fdb_encap_uplink[0x5]; 940 u8 reserved_at_21[0x3]; 941 u8 log_max_packet_reformat_context[0x5]; 942 u8 reserved_2b[0x6]; 943 u8 max_encap_header_size[0xa]; 944 945 u8 reserved_at_40[0xb]; 946 u8 log_max_esw_sf[0x5]; 947 u8 esw_sf_base_id[0x10]; 948 949 u8 reserved_at_60[0x7a0]; 950 951 }; 952 953 struct mlx5_ifc_qos_cap_bits { 954 u8 packet_pacing[0x1]; 955 u8 esw_scheduling[0x1]; 956 u8 esw_bw_share[0x1]; 957 u8 esw_rate_limit[0x1]; 958 u8 reserved_at_4[0x1]; 959 u8 packet_pacing_burst_bound[0x1]; 960 u8 packet_pacing_typical_size[0x1]; 961 u8 reserved_at_7[0x1]; 962 u8 nic_sq_scheduling[0x1]; 963 u8 nic_bw_share[0x1]; 964 u8 nic_rate_limit[0x1]; 965 u8 packet_pacing_uid[0x1]; 966 u8 log_esw_max_sched_depth[0x4]; 967 u8 reserved_at_10[0x10]; 968 969 u8 reserved_at_20[0xb]; 970 u8 log_max_qos_nic_queue_group[0x5]; 971 u8 reserved_at_30[0x10]; 972 973 u8 packet_pacing_max_rate[0x20]; 974 975 u8 packet_pacing_min_rate[0x20]; 976 977 u8 reserved_at_80[0x10]; 978 u8 packet_pacing_rate_table_size[0x10]; 979 980 u8 esw_element_type[0x10]; 981 u8 esw_tsar_type[0x10]; 982 983 u8 reserved_at_c0[0x10]; 984 u8 max_qos_para_vport[0x10]; 985 986 u8 max_tsar_bw_share[0x20]; 987 988 u8 reserved_at_100[0x20]; 989 990 u8 reserved_at_120[0x3]; 991 u8 log_meter_aso_granularity[0x5]; 992 u8 reserved_at_128[0x3]; 993 u8 log_meter_aso_max_alloc[0x5]; 994 u8 reserved_at_130[0x3]; 995 u8 log_max_num_meter_aso[0x5]; 996 u8 reserved_at_138[0x8]; 997 998 u8 reserved_at_140[0x6c0]; 999 }; 1000 1001 struct mlx5_ifc_debug_cap_bits { 1002 u8 core_dump_general[0x1]; 1003 u8 core_dump_qp[0x1]; 1004 u8 reserved_at_2[0x7]; 1005 u8 resource_dump[0x1]; 1006 u8 reserved_at_a[0x16]; 1007 1008 u8 reserved_at_20[0x2]; 1009 u8 stall_detect[0x1]; 1010 u8 reserved_at_23[0x1d]; 1011 1012 u8 reserved_at_40[0x7c0]; 1013 }; 1014 1015 struct mlx5_ifc_per_protocol_networking_offload_caps_bits { 1016 u8 csum_cap[0x1]; 1017 u8 vlan_cap[0x1]; 1018 u8 lro_cap[0x1]; 1019 u8 lro_psh_flag[0x1]; 1020 u8 lro_time_stamp[0x1]; 1021 u8 reserved_at_5[0x2]; 1022 u8 wqe_vlan_insert[0x1]; 1023 u8 self_lb_en_modifiable[0x1]; 1024 u8 reserved_at_9[0x2]; 1025 u8 max_lso_cap[0x5]; 1026 u8 multi_pkt_send_wqe[0x2]; 1027 u8 wqe_inline_mode[0x2]; 1028 u8 rss_ind_tbl_cap[0x4]; 1029 u8 reg_umr_sq[0x1]; 1030 u8 scatter_fcs[0x1]; 1031 u8 enhanced_multi_pkt_send_wqe[0x1]; 1032 u8 tunnel_lso_const_out_ip_id[0x1]; 1033 u8 tunnel_lro_gre[0x1]; 1034 u8 tunnel_lro_vxlan[0x1]; 1035 u8 tunnel_stateless_gre[0x1]; 1036 u8 tunnel_stateless_vxlan[0x1]; 1037 1038 u8 swp[0x1]; 1039 u8 swp_csum[0x1]; 1040 u8 swp_lso[0x1]; 1041 u8 cqe_checksum_full[0x1]; 1042 u8 tunnel_stateless_geneve_tx[0x1]; 1043 u8 tunnel_stateless_mpls_over_udp[0x1]; 1044 u8 tunnel_stateless_mpls_over_gre[0x1]; 1045 u8 tunnel_stateless_vxlan_gpe[0x1]; 1046 u8 tunnel_stateless_ipv4_over_vxlan[0x1]; 1047 u8 tunnel_stateless_ip_over_ip[0x1]; 1048 u8 insert_trailer[0x1]; 1049 u8 reserved_at_2b[0x1]; 1050 u8 tunnel_stateless_ip_over_ip_rx[0x1]; 1051 u8 tunnel_stateless_ip_over_ip_tx[0x1]; 1052 u8 reserved_at_2e[0x2]; 1053 u8 max_vxlan_udp_ports[0x8]; 1054 u8 reserved_at_38[0x6]; 1055 u8 max_geneve_opt_len[0x1]; 1056 u8 tunnel_stateless_geneve_rx[0x1]; 1057 1058 u8 reserved_at_40[0x10]; 1059 u8 lro_min_mss_size[0x10]; 1060 1061 u8 reserved_at_60[0x120]; 1062 1063 u8 lro_timer_supported_periods[4][0x20]; 1064 1065 u8 reserved_at_200[0x600]; 1066 }; 1067 1068 enum { 1069 MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING = 0x0, 1070 MLX5_TIMESTAMP_FORMAT_CAP_REAL_TIME = 0x1, 1071 MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING_AND_REAL_TIME = 0x2, 1072 }; 1073 1074 struct mlx5_ifc_roce_cap_bits { 1075 u8 roce_apm[0x1]; 1076 u8 reserved_at_1[0x3]; 1077 u8 sw_r_roce_src_udp_port[0x1]; 1078 u8 fl_rc_qp_when_roce_disabled[0x1]; 1079 u8 fl_rc_qp_when_roce_enabled[0x1]; 1080 u8 reserved_at_7[0x17]; 1081 u8 qp_ts_format[0x2]; 1082 1083 u8 reserved_at_20[0x60]; 1084 1085 u8 reserved_at_80[0xc]; 1086 u8 l3_type[0x4]; 1087 u8 reserved_at_90[0x8]; 1088 u8 roce_version[0x8]; 1089 1090 u8 reserved_at_a0[0x10]; 1091 u8 r_roce_dest_udp_port[0x10]; 1092 1093 u8 r_roce_max_src_udp_port[0x10]; 1094 u8 r_roce_min_src_udp_port[0x10]; 1095 1096 u8 reserved_at_e0[0x10]; 1097 u8 roce_address_table_size[0x10]; 1098 1099 u8 reserved_at_100[0x700]; 1100 }; 1101 1102 struct mlx5_ifc_sync_steering_in_bits { 1103 u8 opcode[0x10]; 1104 u8 uid[0x10]; 1105 1106 u8 reserved_at_20[0x10]; 1107 u8 op_mod[0x10]; 1108 1109 u8 reserved_at_40[0xc0]; 1110 }; 1111 1112 struct mlx5_ifc_sync_steering_out_bits { 1113 u8 status[0x8]; 1114 u8 reserved_at_8[0x18]; 1115 1116 u8 syndrome[0x20]; 1117 1118 u8 reserved_at_40[0x40]; 1119 }; 1120 1121 struct mlx5_ifc_sync_crypto_in_bits { 1122 u8 opcode[0x10]; 1123 u8 uid[0x10]; 1124 1125 u8 reserved_at_20[0x10]; 1126 u8 op_mod[0x10]; 1127 1128 u8 reserved_at_40[0x20]; 1129 1130 u8 reserved_at_60[0x10]; 1131 u8 crypto_type[0x10]; 1132 1133 u8 reserved_at_80[0x80]; 1134 }; 1135 1136 struct mlx5_ifc_sync_crypto_out_bits { 1137 u8 status[0x8]; 1138 u8 reserved_at_8[0x18]; 1139 1140 u8 syndrome[0x20]; 1141 1142 u8 reserved_at_40[0x40]; 1143 }; 1144 1145 struct mlx5_ifc_device_mem_cap_bits { 1146 u8 memic[0x1]; 1147 u8 reserved_at_1[0x1f]; 1148 1149 u8 reserved_at_20[0xb]; 1150 u8 log_min_memic_alloc_size[0x5]; 1151 u8 reserved_at_30[0x8]; 1152 u8 log_max_memic_addr_alignment[0x8]; 1153 1154 u8 memic_bar_start_addr[0x40]; 1155 1156 u8 memic_bar_size[0x20]; 1157 1158 u8 max_memic_size[0x20]; 1159 1160 u8 steering_sw_icm_start_address[0x40]; 1161 1162 u8 reserved_at_100[0x8]; 1163 u8 log_header_modify_sw_icm_size[0x8]; 1164 u8 reserved_at_110[0x2]; 1165 u8 log_sw_icm_alloc_granularity[0x6]; 1166 u8 log_steering_sw_icm_size[0x8]; 1167 1168 u8 reserved_at_120[0x18]; 1169 u8 log_header_modify_pattern_sw_icm_size[0x8]; 1170 1171 u8 header_modify_sw_icm_start_address[0x40]; 1172 1173 u8 reserved_at_180[0x40]; 1174 1175 u8 header_modify_pattern_sw_icm_start_address[0x40]; 1176 1177 u8 memic_operations[0x20]; 1178 1179 u8 reserved_at_220[0x5e0]; 1180 }; 1181 1182 struct mlx5_ifc_device_event_cap_bits { 1183 u8 user_affiliated_events[4][0x40]; 1184 1185 u8 user_unaffiliated_events[4][0x40]; 1186 }; 1187 1188 struct mlx5_ifc_virtio_emulation_cap_bits { 1189 u8 desc_tunnel_offload_type[0x1]; 1190 u8 eth_frame_offload_type[0x1]; 1191 u8 virtio_version_1_0[0x1]; 1192 u8 device_features_bits_mask[0xd]; 1193 u8 event_mode[0x8]; 1194 u8 virtio_queue_type[0x8]; 1195 1196 u8 max_tunnel_desc[0x10]; 1197 u8 reserved_at_30[0x3]; 1198 u8 log_doorbell_stride[0x5]; 1199 u8 reserved_at_38[0x3]; 1200 u8 log_doorbell_bar_size[0x5]; 1201 1202 u8 doorbell_bar_offset[0x40]; 1203 1204 u8 max_emulated_devices[0x8]; 1205 u8 max_num_virtio_queues[0x18]; 1206 1207 u8 reserved_at_a0[0x60]; 1208 1209 u8 umem_1_buffer_param_a[0x20]; 1210 1211 u8 umem_1_buffer_param_b[0x20]; 1212 1213 u8 umem_2_buffer_param_a[0x20]; 1214 1215 u8 umem_2_buffer_param_b[0x20]; 1216 1217 u8 umem_3_buffer_param_a[0x20]; 1218 1219 u8 umem_3_buffer_param_b[0x20]; 1220 1221 u8 reserved_at_1c0[0x640]; 1222 }; 1223 1224 enum { 1225 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0, 1226 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2, 1227 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4, 1228 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8, 1229 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10, 1230 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20, 1231 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40, 1232 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80, 1233 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100, 1234 }; 1235 1236 enum { 1237 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1, 1238 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2, 1239 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4, 1240 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8, 1241 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10, 1242 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20, 1243 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40, 1244 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80, 1245 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100, 1246 }; 1247 1248 struct mlx5_ifc_atomic_caps_bits { 1249 u8 reserved_at_0[0x40]; 1250 1251 u8 atomic_req_8B_endianness_mode[0x2]; 1252 u8 reserved_at_42[0x4]; 1253 u8 supported_atomic_req_8B_endianness_mode_1[0x1]; 1254 1255 u8 reserved_at_47[0x19]; 1256 1257 u8 reserved_at_60[0x20]; 1258 1259 u8 reserved_at_80[0x10]; 1260 u8 atomic_operations[0x10]; 1261 1262 u8 reserved_at_a0[0x10]; 1263 u8 atomic_size_qp[0x10]; 1264 1265 u8 reserved_at_c0[0x10]; 1266 u8 atomic_size_dc[0x10]; 1267 1268 u8 reserved_at_e0[0x720]; 1269 }; 1270 1271 struct mlx5_ifc_odp_cap_bits { 1272 u8 reserved_at_0[0x40]; 1273 1274 u8 sig[0x1]; 1275 u8 reserved_at_41[0x1f]; 1276 1277 u8 reserved_at_60[0x20]; 1278 1279 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps; 1280 1281 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps; 1282 1283 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps; 1284 1285 struct mlx5_ifc_odp_per_transport_service_cap_bits xrc_odp_caps; 1286 1287 struct mlx5_ifc_odp_per_transport_service_cap_bits dc_odp_caps; 1288 1289 u8 reserved_at_120[0x6E0]; 1290 }; 1291 1292 struct mlx5_ifc_calc_op { 1293 u8 reserved_at_0[0x10]; 1294 u8 reserved_at_10[0x9]; 1295 u8 op_swap_endianness[0x1]; 1296 u8 op_min[0x1]; 1297 u8 op_xor[0x1]; 1298 u8 op_or[0x1]; 1299 u8 op_and[0x1]; 1300 u8 op_max[0x1]; 1301 u8 op_add[0x1]; 1302 }; 1303 1304 struct mlx5_ifc_vector_calc_cap_bits { 1305 u8 calc_matrix[0x1]; 1306 u8 reserved_at_1[0x1f]; 1307 u8 reserved_at_20[0x8]; 1308 u8 max_vec_count[0x8]; 1309 u8 reserved_at_30[0xd]; 1310 u8 max_chunk_size[0x3]; 1311 struct mlx5_ifc_calc_op calc0; 1312 struct mlx5_ifc_calc_op calc1; 1313 struct mlx5_ifc_calc_op calc2; 1314 struct mlx5_ifc_calc_op calc3; 1315 1316 u8 reserved_at_c0[0x720]; 1317 }; 1318 1319 struct mlx5_ifc_tls_cap_bits { 1320 u8 tls_1_2_aes_gcm_128[0x1]; 1321 u8 tls_1_3_aes_gcm_128[0x1]; 1322 u8 tls_1_2_aes_gcm_256[0x1]; 1323 u8 tls_1_3_aes_gcm_256[0x1]; 1324 u8 reserved_at_4[0x1c]; 1325 1326 u8 reserved_at_20[0x7e0]; 1327 }; 1328 1329 struct mlx5_ifc_ipsec_cap_bits { 1330 u8 ipsec_full_offload[0x1]; 1331 u8 ipsec_crypto_offload[0x1]; 1332 u8 ipsec_esn[0x1]; 1333 u8 ipsec_crypto_esp_aes_gcm_256_encrypt[0x1]; 1334 u8 ipsec_crypto_esp_aes_gcm_128_encrypt[0x1]; 1335 u8 ipsec_crypto_esp_aes_gcm_256_decrypt[0x1]; 1336 u8 ipsec_crypto_esp_aes_gcm_128_decrypt[0x1]; 1337 u8 reserved_at_7[0x4]; 1338 u8 log_max_ipsec_offload[0x5]; 1339 u8 reserved_at_10[0x10]; 1340 1341 u8 min_log_ipsec_full_replay_window[0x8]; 1342 u8 max_log_ipsec_full_replay_window[0x8]; 1343 u8 reserved_at_30[0x7d0]; 1344 }; 1345 1346 struct mlx5_ifc_macsec_cap_bits { 1347 u8 macsec_epn[0x1]; 1348 u8 reserved_at_1[0x2]; 1349 u8 macsec_crypto_esp_aes_gcm_256_encrypt[0x1]; 1350 u8 macsec_crypto_esp_aes_gcm_128_encrypt[0x1]; 1351 u8 macsec_crypto_esp_aes_gcm_256_decrypt[0x1]; 1352 u8 macsec_crypto_esp_aes_gcm_128_decrypt[0x1]; 1353 u8 reserved_at_7[0x4]; 1354 u8 log_max_macsec_offload[0x5]; 1355 u8 reserved_at_10[0x10]; 1356 1357 u8 min_log_macsec_full_replay_window[0x8]; 1358 u8 max_log_macsec_full_replay_window[0x8]; 1359 u8 reserved_at_30[0x10]; 1360 1361 u8 reserved_at_40[0x7c0]; 1362 }; 1363 1364 enum { 1365 MLX5_WQ_TYPE_LINKED_LIST = 0x0, 1366 MLX5_WQ_TYPE_CYCLIC = 0x1, 1367 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2, 1368 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3, 1369 }; 1370 1371 enum { 1372 MLX5_WQ_END_PAD_MODE_NONE = 0x0, 1373 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1, 1374 }; 1375 1376 enum { 1377 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0, 1378 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1, 1379 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2, 1380 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3, 1381 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4, 1382 }; 1383 1384 enum { 1385 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0, 1386 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1, 1387 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2, 1388 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3, 1389 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4, 1390 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5, 1391 }; 1392 1393 enum { 1394 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0, 1395 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1, 1396 }; 1397 1398 enum { 1399 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0, 1400 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1, 1401 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3, 1402 }; 1403 1404 enum { 1405 MLX5_CAP_PORT_TYPE_IB = 0x0, 1406 MLX5_CAP_PORT_TYPE_ETH = 0x1, 1407 }; 1408 1409 enum { 1410 MLX5_CAP_UMR_FENCE_STRONG = 0x0, 1411 MLX5_CAP_UMR_FENCE_SMALL = 0x1, 1412 MLX5_CAP_UMR_FENCE_NONE = 0x2, 1413 }; 1414 1415 enum { 1416 MLX5_FLEX_PARSER_GENEVE_ENABLED = 1 << 3, 1417 MLX5_FLEX_PARSER_MPLS_OVER_GRE_ENABLED = 1 << 4, 1418 MLX5_FLEX_PARSER_MPLS_OVER_UDP_ENABLED = 1 << 5, 1419 MLX5_FLEX_PARSER_VXLAN_GPE_ENABLED = 1 << 7, 1420 MLX5_FLEX_PARSER_ICMP_V4_ENABLED = 1 << 8, 1421 MLX5_FLEX_PARSER_ICMP_V6_ENABLED = 1 << 9, 1422 MLX5_FLEX_PARSER_GENEVE_TLV_OPTION_0_ENABLED = 1 << 10, 1423 MLX5_FLEX_PARSER_GTPU_ENABLED = 1 << 11, 1424 MLX5_FLEX_PARSER_GTPU_DW_2_ENABLED = 1 << 16, 1425 MLX5_FLEX_PARSER_GTPU_FIRST_EXT_DW_0_ENABLED = 1 << 17, 1426 MLX5_FLEX_PARSER_GTPU_DW_0_ENABLED = 1 << 18, 1427 MLX5_FLEX_PARSER_GTPU_TEID_ENABLED = 1 << 19, 1428 }; 1429 1430 enum { 1431 MLX5_UCTX_CAP_RAW_TX = 1UL << 0, 1432 MLX5_UCTX_CAP_INTERNAL_DEV_RES = 1UL << 1, 1433 }; 1434 1435 #define MLX5_FC_BULK_SIZE_FACTOR 128 1436 1437 enum mlx5_fc_bulk_alloc_bitmask { 1438 MLX5_FC_BULK_128 = (1 << 0), 1439 MLX5_FC_BULK_256 = (1 << 1), 1440 MLX5_FC_BULK_512 = (1 << 2), 1441 MLX5_FC_BULK_1024 = (1 << 3), 1442 MLX5_FC_BULK_2048 = (1 << 4), 1443 MLX5_FC_BULK_4096 = (1 << 5), 1444 MLX5_FC_BULK_8192 = (1 << 6), 1445 MLX5_FC_BULK_16384 = (1 << 7), 1446 }; 1447 1448 #define MLX5_FC_BULK_NUM_FCS(fc_enum) (MLX5_FC_BULK_SIZE_FACTOR * (fc_enum)) 1449 1450 #define MLX5_FT_MAX_MULTIPATH_LEVEL 63 1451 1452 enum { 1453 MLX5_STEERING_FORMAT_CONNECTX_5 = 0, 1454 MLX5_STEERING_FORMAT_CONNECTX_6DX = 1, 1455 MLX5_STEERING_FORMAT_CONNECTX_7 = 2, 1456 }; 1457 1458 struct mlx5_ifc_cmd_hca_cap_bits { 1459 u8 reserved_at_0[0x10]; 1460 u8 shared_object_to_user_object_allowed[0x1]; 1461 u8 reserved_at_13[0xe]; 1462 u8 vhca_resource_manager[0x1]; 1463 1464 u8 hca_cap_2[0x1]; 1465 u8 create_lag_when_not_master_up[0x1]; 1466 u8 dtor[0x1]; 1467 u8 event_on_vhca_state_teardown_request[0x1]; 1468 u8 event_on_vhca_state_in_use[0x1]; 1469 u8 event_on_vhca_state_active[0x1]; 1470 u8 event_on_vhca_state_allocated[0x1]; 1471 u8 event_on_vhca_state_invalid[0x1]; 1472 u8 reserved_at_28[0x8]; 1473 u8 vhca_id[0x10]; 1474 1475 u8 reserved_at_40[0x40]; 1476 1477 u8 log_max_srq_sz[0x8]; 1478 u8 log_max_qp_sz[0x8]; 1479 u8 event_cap[0x1]; 1480 u8 reserved_at_91[0x2]; 1481 u8 isolate_vl_tc_new[0x1]; 1482 u8 reserved_at_94[0x4]; 1483 u8 prio_tag_required[0x1]; 1484 u8 reserved_at_99[0x2]; 1485 u8 log_max_qp[0x5]; 1486 1487 u8 reserved_at_a0[0x3]; 1488 u8 ece_support[0x1]; 1489 u8 reserved_at_a4[0x5]; 1490 u8 reg_c_preserve[0x1]; 1491 u8 reserved_at_aa[0x1]; 1492 u8 log_max_srq[0x5]; 1493 u8 reserved_at_b0[0x1]; 1494 u8 uplink_follow[0x1]; 1495 u8 ts_cqe_to_dest_cqn[0x1]; 1496 u8 reserved_at_b3[0x7]; 1497 u8 shampo[0x1]; 1498 u8 reserved_at_bb[0x5]; 1499 1500 u8 max_sgl_for_optimized_performance[0x8]; 1501 u8 log_max_cq_sz[0x8]; 1502 u8 relaxed_ordering_write_umr[0x1]; 1503 u8 relaxed_ordering_read_umr[0x1]; 1504 u8 reserved_at_d2[0x7]; 1505 u8 virtio_net_device_emualtion_manager[0x1]; 1506 u8 virtio_blk_device_emualtion_manager[0x1]; 1507 u8 log_max_cq[0x5]; 1508 1509 u8 log_max_eq_sz[0x8]; 1510 u8 relaxed_ordering_write[0x1]; 1511 u8 relaxed_ordering_read[0x1]; 1512 u8 log_max_mkey[0x6]; 1513 u8 reserved_at_f0[0x8]; 1514 u8 dump_fill_mkey[0x1]; 1515 u8 reserved_at_f9[0x2]; 1516 u8 fast_teardown[0x1]; 1517 u8 log_max_eq[0x4]; 1518 1519 u8 max_indirection[0x8]; 1520 u8 fixed_buffer_size[0x1]; 1521 u8 log_max_mrw_sz[0x7]; 1522 u8 force_teardown[0x1]; 1523 u8 reserved_at_111[0x1]; 1524 u8 log_max_bsf_list_size[0x6]; 1525 u8 umr_extended_translation_offset[0x1]; 1526 u8 null_mkey[0x1]; 1527 u8 log_max_klm_list_size[0x6]; 1528 1529 u8 reserved_at_120[0x2]; 1530 u8 qpc_extension[0x1]; 1531 u8 reserved_at_123[0x7]; 1532 u8 log_max_ra_req_dc[0x6]; 1533 u8 reserved_at_130[0x2]; 1534 u8 eth_wqe_too_small[0x1]; 1535 u8 reserved_at_133[0x6]; 1536 u8 vnic_env_cq_overrun[0x1]; 1537 u8 log_max_ra_res_dc[0x6]; 1538 1539 u8 reserved_at_140[0x5]; 1540 u8 release_all_pages[0x1]; 1541 u8 must_not_use[0x1]; 1542 u8 reserved_at_147[0x2]; 1543 u8 roce_accl[0x1]; 1544 u8 log_max_ra_req_qp[0x6]; 1545 u8 reserved_at_150[0xa]; 1546 u8 log_max_ra_res_qp[0x6]; 1547 1548 u8 end_pad[0x1]; 1549 u8 cc_query_allowed[0x1]; 1550 u8 cc_modify_allowed[0x1]; 1551 u8 start_pad[0x1]; 1552 u8 cache_line_128byte[0x1]; 1553 u8 reserved_at_165[0x4]; 1554 u8 rts2rts_qp_counters_set_id[0x1]; 1555 u8 reserved_at_16a[0x2]; 1556 u8 vnic_env_int_rq_oob[0x1]; 1557 u8 sbcam_reg[0x1]; 1558 u8 reserved_at_16e[0x1]; 1559 u8 qcam_reg[0x1]; 1560 u8 gid_table_size[0x10]; 1561 1562 u8 out_of_seq_cnt[0x1]; 1563 u8 vport_counters[0x1]; 1564 u8 retransmission_q_counters[0x1]; 1565 u8 debug[0x1]; 1566 u8 modify_rq_counter_set_id[0x1]; 1567 u8 rq_delay_drop[0x1]; 1568 u8 max_qp_cnt[0xa]; 1569 u8 pkey_table_size[0x10]; 1570 1571 u8 vport_group_manager[0x1]; 1572 u8 vhca_group_manager[0x1]; 1573 u8 ib_virt[0x1]; 1574 u8 eth_virt[0x1]; 1575 u8 vnic_env_queue_counters[0x1]; 1576 u8 ets[0x1]; 1577 u8 nic_flow_table[0x1]; 1578 u8 eswitch_manager[0x1]; 1579 u8 device_memory[0x1]; 1580 u8 mcam_reg[0x1]; 1581 u8 pcam_reg[0x1]; 1582 u8 local_ca_ack_delay[0x5]; 1583 u8 port_module_event[0x1]; 1584 u8 enhanced_error_q_counters[0x1]; 1585 u8 ports_check[0x1]; 1586 u8 reserved_at_1b3[0x1]; 1587 u8 disable_link_up[0x1]; 1588 u8 beacon_led[0x1]; 1589 u8 port_type[0x2]; 1590 u8 num_ports[0x8]; 1591 1592 u8 reserved_at_1c0[0x1]; 1593 u8 pps[0x1]; 1594 u8 pps_modify[0x1]; 1595 u8 log_max_msg[0x5]; 1596 u8 reserved_at_1c8[0x4]; 1597 u8 max_tc[0x4]; 1598 u8 temp_warn_event[0x1]; 1599 u8 dcbx[0x1]; 1600 u8 general_notification_event[0x1]; 1601 u8 reserved_at_1d3[0x2]; 1602 u8 fpga[0x1]; 1603 u8 rol_s[0x1]; 1604 u8 rol_g[0x1]; 1605 u8 reserved_at_1d8[0x1]; 1606 u8 wol_s[0x1]; 1607 u8 wol_g[0x1]; 1608 u8 wol_a[0x1]; 1609 u8 wol_b[0x1]; 1610 u8 wol_m[0x1]; 1611 u8 wol_u[0x1]; 1612 u8 wol_p[0x1]; 1613 1614 u8 stat_rate_support[0x10]; 1615 u8 reserved_at_1f0[0x1]; 1616 u8 pci_sync_for_fw_update_event[0x1]; 1617 u8 reserved_at_1f2[0x6]; 1618 u8 init2_lag_tx_port_affinity[0x1]; 1619 u8 reserved_at_1fa[0x3]; 1620 u8 cqe_version[0x4]; 1621 1622 u8 compact_address_vector[0x1]; 1623 u8 striding_rq[0x1]; 1624 u8 reserved_at_202[0x1]; 1625 u8 ipoib_enhanced_offloads[0x1]; 1626 u8 ipoib_basic_offloads[0x1]; 1627 u8 reserved_at_205[0x1]; 1628 u8 repeated_block_disabled[0x1]; 1629 u8 umr_modify_entity_size_disabled[0x1]; 1630 u8 umr_modify_atomic_disabled[0x1]; 1631 u8 umr_indirect_mkey_disabled[0x1]; 1632 u8 umr_fence[0x2]; 1633 u8 dc_req_scat_data_cqe[0x1]; 1634 u8 reserved_at_20d[0x2]; 1635 u8 drain_sigerr[0x1]; 1636 u8 cmdif_checksum[0x2]; 1637 u8 sigerr_cqe[0x1]; 1638 u8 reserved_at_213[0x1]; 1639 u8 wq_signature[0x1]; 1640 u8 sctr_data_cqe[0x1]; 1641 u8 reserved_at_216[0x1]; 1642 u8 sho[0x1]; 1643 u8 tph[0x1]; 1644 u8 rf[0x1]; 1645 u8 dct[0x1]; 1646 u8 qos[0x1]; 1647 u8 eth_net_offloads[0x1]; 1648 u8 roce[0x1]; 1649 u8 atomic[0x1]; 1650 u8 reserved_at_21f[0x1]; 1651 1652 u8 cq_oi[0x1]; 1653 u8 cq_resize[0x1]; 1654 u8 cq_moderation[0x1]; 1655 u8 reserved_at_223[0x3]; 1656 u8 cq_eq_remap[0x1]; 1657 u8 pg[0x1]; 1658 u8 block_lb_mc[0x1]; 1659 u8 reserved_at_229[0x1]; 1660 u8 scqe_break_moderation[0x1]; 1661 u8 cq_period_start_from_cqe[0x1]; 1662 u8 cd[0x1]; 1663 u8 reserved_at_22d[0x1]; 1664 u8 apm[0x1]; 1665 u8 vector_calc[0x1]; 1666 u8 umr_ptr_rlky[0x1]; 1667 u8 imaicl[0x1]; 1668 u8 qp_packet_based[0x1]; 1669 u8 reserved_at_233[0x3]; 1670 u8 qkv[0x1]; 1671 u8 pkv[0x1]; 1672 u8 set_deth_sqpn[0x1]; 1673 u8 reserved_at_239[0x3]; 1674 u8 xrc[0x1]; 1675 u8 ud[0x1]; 1676 u8 uc[0x1]; 1677 u8 rc[0x1]; 1678 1679 u8 uar_4k[0x1]; 1680 u8 reserved_at_241[0x9]; 1681 u8 uar_sz[0x6]; 1682 u8 port_selection_cap[0x1]; 1683 u8 reserved_at_248[0x1]; 1684 u8 umem_uid_0[0x1]; 1685 u8 reserved_at_250[0x5]; 1686 u8 log_pg_sz[0x8]; 1687 1688 u8 bf[0x1]; 1689 u8 driver_version[0x1]; 1690 u8 pad_tx_eth_packet[0x1]; 1691 u8 reserved_at_263[0x3]; 1692 u8 mkey_by_name[0x1]; 1693 u8 reserved_at_267[0x4]; 1694 1695 u8 log_bf_reg_size[0x5]; 1696 1697 u8 reserved_at_270[0x3]; 1698 u8 qp_error_syndrome[0x1]; 1699 u8 reserved_at_274[0x2]; 1700 u8 lag_dct[0x2]; 1701 u8 lag_tx_port_affinity[0x1]; 1702 u8 lag_native_fdb_selection[0x1]; 1703 u8 reserved_at_27a[0x1]; 1704 u8 lag_master[0x1]; 1705 u8 num_lag_ports[0x4]; 1706 1707 u8 reserved_at_280[0x10]; 1708 u8 max_wqe_sz_sq[0x10]; 1709 1710 u8 reserved_at_2a0[0x10]; 1711 u8 max_wqe_sz_rq[0x10]; 1712 1713 u8 max_flow_counter_31_16[0x10]; 1714 u8 max_wqe_sz_sq_dc[0x10]; 1715 1716 u8 reserved_at_2e0[0x7]; 1717 u8 max_qp_mcg[0x19]; 1718 1719 u8 reserved_at_300[0x10]; 1720 u8 flow_counter_bulk_alloc[0x8]; 1721 u8 log_max_mcg[0x8]; 1722 1723 u8 reserved_at_320[0x3]; 1724 u8 log_max_transport_domain[0x5]; 1725 u8 reserved_at_328[0x3]; 1726 u8 log_max_pd[0x5]; 1727 u8 reserved_at_330[0xb]; 1728 u8 log_max_xrcd[0x5]; 1729 1730 u8 nic_receive_steering_discard[0x1]; 1731 u8 receive_discard_vport_down[0x1]; 1732 u8 transmit_discard_vport_down[0x1]; 1733 u8 eq_overrun_count[0x1]; 1734 u8 reserved_at_344[0x1]; 1735 u8 invalid_command_count[0x1]; 1736 u8 quota_exceeded_count[0x1]; 1737 u8 reserved_at_347[0x1]; 1738 u8 log_max_flow_counter_bulk[0x8]; 1739 u8 max_flow_counter_15_0[0x10]; 1740 1741 1742 u8 reserved_at_360[0x3]; 1743 u8 log_max_rq[0x5]; 1744 u8 reserved_at_368[0x3]; 1745 u8 log_max_sq[0x5]; 1746 u8 reserved_at_370[0x3]; 1747 u8 log_max_tir[0x5]; 1748 u8 reserved_at_378[0x3]; 1749 u8 log_max_tis[0x5]; 1750 1751 u8 basic_cyclic_rcv_wqe[0x1]; 1752 u8 reserved_at_381[0x2]; 1753 u8 log_max_rmp[0x5]; 1754 u8 reserved_at_388[0x3]; 1755 u8 log_max_rqt[0x5]; 1756 u8 reserved_at_390[0x3]; 1757 u8 log_max_rqt_size[0x5]; 1758 u8 reserved_at_398[0x3]; 1759 u8 log_max_tis_per_sq[0x5]; 1760 1761 u8 ext_stride_num_range[0x1]; 1762 u8 roce_rw_supported[0x1]; 1763 u8 log_max_current_uc_list_wr_supported[0x1]; 1764 u8 log_max_stride_sz_rq[0x5]; 1765 u8 reserved_at_3a8[0x3]; 1766 u8 log_min_stride_sz_rq[0x5]; 1767 u8 reserved_at_3b0[0x3]; 1768 u8 log_max_stride_sz_sq[0x5]; 1769 u8 reserved_at_3b8[0x3]; 1770 u8 log_min_stride_sz_sq[0x5]; 1771 1772 u8 hairpin[0x1]; 1773 u8 reserved_at_3c1[0x2]; 1774 u8 log_max_hairpin_queues[0x5]; 1775 u8 reserved_at_3c8[0x3]; 1776 u8 log_max_hairpin_wq_data_sz[0x5]; 1777 u8 reserved_at_3d0[0x3]; 1778 u8 log_max_hairpin_num_packets[0x5]; 1779 u8 reserved_at_3d8[0x3]; 1780 u8 log_max_wq_sz[0x5]; 1781 1782 u8 nic_vport_change_event[0x1]; 1783 u8 disable_local_lb_uc[0x1]; 1784 u8 disable_local_lb_mc[0x1]; 1785 u8 log_min_hairpin_wq_data_sz[0x5]; 1786 u8 reserved_at_3e8[0x2]; 1787 u8 vhca_state[0x1]; 1788 u8 log_max_vlan_list[0x5]; 1789 u8 reserved_at_3f0[0x3]; 1790 u8 log_max_current_mc_list[0x5]; 1791 u8 reserved_at_3f8[0x3]; 1792 u8 log_max_current_uc_list[0x5]; 1793 1794 u8 general_obj_types[0x40]; 1795 1796 u8 sq_ts_format[0x2]; 1797 u8 rq_ts_format[0x2]; 1798 u8 steering_format_version[0x4]; 1799 u8 create_qp_start_hint[0x18]; 1800 1801 u8 reserved_at_460[0x1]; 1802 u8 ats[0x1]; 1803 u8 reserved_at_462[0x1]; 1804 u8 log_max_uctx[0x5]; 1805 u8 reserved_at_468[0x1]; 1806 u8 crypto[0x1]; 1807 u8 ipsec_offload[0x1]; 1808 u8 log_max_umem[0x5]; 1809 u8 max_num_eqs[0x10]; 1810 1811 u8 reserved_at_480[0x1]; 1812 u8 tls_tx[0x1]; 1813 u8 tls_rx[0x1]; 1814 u8 log_max_l2_table[0x5]; 1815 u8 reserved_at_488[0x8]; 1816 u8 log_uar_page_sz[0x10]; 1817 1818 u8 reserved_at_4a0[0x20]; 1819 u8 device_frequency_mhz[0x20]; 1820 u8 device_frequency_khz[0x20]; 1821 1822 u8 reserved_at_500[0x20]; 1823 u8 num_of_uars_per_page[0x20]; 1824 1825 u8 flex_parser_protocols[0x20]; 1826 1827 u8 max_geneve_tlv_options[0x8]; 1828 u8 reserved_at_568[0x3]; 1829 u8 max_geneve_tlv_option_data_len[0x5]; 1830 u8 reserved_at_570[0x9]; 1831 u8 adv_virtualization[0x1]; 1832 u8 reserved_at_57a[0x6]; 1833 1834 u8 reserved_at_580[0xb]; 1835 u8 log_max_dci_stream_channels[0x5]; 1836 u8 reserved_at_590[0x3]; 1837 u8 log_max_dci_errored_streams[0x5]; 1838 u8 reserved_at_598[0x8]; 1839 1840 u8 reserved_at_5a0[0x10]; 1841 u8 enhanced_cqe_compression[0x1]; 1842 u8 reserved_at_5b1[0x2]; 1843 u8 log_max_dek[0x5]; 1844 u8 reserved_at_5b8[0x4]; 1845 u8 mini_cqe_resp_stride_index[0x1]; 1846 u8 cqe_128_always[0x1]; 1847 u8 cqe_compression_128[0x1]; 1848 u8 cqe_compression[0x1]; 1849 1850 u8 cqe_compression_timeout[0x10]; 1851 u8 cqe_compression_max_num[0x10]; 1852 1853 u8 reserved_at_5e0[0x8]; 1854 u8 flex_parser_id_gtpu_dw_0[0x4]; 1855 u8 reserved_at_5ec[0x4]; 1856 u8 tag_matching[0x1]; 1857 u8 rndv_offload_rc[0x1]; 1858 u8 rndv_offload_dc[0x1]; 1859 u8 log_tag_matching_list_sz[0x5]; 1860 u8 reserved_at_5f8[0x3]; 1861 u8 log_max_xrq[0x5]; 1862 1863 u8 affiliate_nic_vport_criteria[0x8]; 1864 u8 native_port_num[0x8]; 1865 u8 num_vhca_ports[0x8]; 1866 u8 flex_parser_id_gtpu_teid[0x4]; 1867 u8 reserved_at_61c[0x2]; 1868 u8 sw_owner_id[0x1]; 1869 u8 reserved_at_61f[0x1]; 1870 1871 u8 max_num_of_monitor_counters[0x10]; 1872 u8 num_ppcnt_monitor_counters[0x10]; 1873 1874 u8 max_num_sf[0x10]; 1875 u8 num_q_monitor_counters[0x10]; 1876 1877 u8 reserved_at_660[0x20]; 1878 1879 u8 sf[0x1]; 1880 u8 sf_set_partition[0x1]; 1881 u8 reserved_at_682[0x1]; 1882 u8 log_max_sf[0x5]; 1883 u8 apu[0x1]; 1884 u8 reserved_at_689[0x4]; 1885 u8 migration[0x1]; 1886 u8 reserved_at_68e[0x2]; 1887 u8 log_min_sf_size[0x8]; 1888 u8 max_num_sf_partitions[0x8]; 1889 1890 u8 uctx_cap[0x20]; 1891 1892 u8 reserved_at_6c0[0x4]; 1893 u8 flex_parser_id_geneve_tlv_option_0[0x4]; 1894 u8 flex_parser_id_icmp_dw1[0x4]; 1895 u8 flex_parser_id_icmp_dw0[0x4]; 1896 u8 flex_parser_id_icmpv6_dw1[0x4]; 1897 u8 flex_parser_id_icmpv6_dw0[0x4]; 1898 u8 flex_parser_id_outer_first_mpls_over_gre[0x4]; 1899 u8 flex_parser_id_outer_first_mpls_over_udp_label[0x4]; 1900 1901 u8 max_num_match_definer[0x10]; 1902 u8 sf_base_id[0x10]; 1903 1904 u8 flex_parser_id_gtpu_dw_2[0x4]; 1905 u8 flex_parser_id_gtpu_first_ext_dw_0[0x4]; 1906 u8 num_total_dynamic_vf_msix[0x18]; 1907 u8 reserved_at_720[0x14]; 1908 u8 dynamic_msix_table_size[0xc]; 1909 u8 reserved_at_740[0xc]; 1910 u8 min_dynamic_vf_msix_table_size[0x4]; 1911 u8 reserved_at_750[0x4]; 1912 u8 max_dynamic_vf_msix_table_size[0xc]; 1913 1914 u8 reserved_at_760[0x20]; 1915 u8 vhca_tunnel_commands[0x40]; 1916 u8 match_definer_format_supported[0x40]; 1917 }; 1918 1919 struct mlx5_ifc_cmd_hca_cap_2_bits { 1920 u8 reserved_at_0[0x80]; 1921 1922 u8 migratable[0x1]; 1923 u8 reserved_at_81[0x1f]; 1924 1925 u8 max_reformat_insert_size[0x8]; 1926 u8 max_reformat_insert_offset[0x8]; 1927 u8 max_reformat_remove_size[0x8]; 1928 u8 max_reformat_remove_offset[0x8]; 1929 1930 u8 reserved_at_c0[0x8]; 1931 u8 migration_multi_load[0x1]; 1932 u8 migration_tracking_state[0x1]; 1933 u8 reserved_at_ca[0x16]; 1934 1935 u8 reserved_at_e0[0xc0]; 1936 1937 u8 flow_table_type_2_type[0x8]; 1938 u8 reserved_at_1a8[0x3]; 1939 u8 log_min_mkey_entity_size[0x5]; 1940 u8 reserved_at_1b0[0x10]; 1941 1942 u8 reserved_at_1c0[0x60]; 1943 1944 u8 reserved_at_220[0x1]; 1945 u8 sw_vhca_id_valid[0x1]; 1946 u8 sw_vhca_id[0xe]; 1947 u8 reserved_at_230[0x10]; 1948 1949 u8 reserved_at_240[0xb]; 1950 u8 ts_cqe_metadata_size2wqe_counter[0x5]; 1951 u8 reserved_at_250[0x10]; 1952 1953 u8 reserved_at_260[0x5a0]; 1954 }; 1955 1956 enum mlx5_ifc_flow_destination_type { 1957 MLX5_IFC_FLOW_DESTINATION_TYPE_VPORT = 0x0, 1958 MLX5_IFC_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1, 1959 MLX5_IFC_FLOW_DESTINATION_TYPE_TIR = 0x2, 1960 MLX5_IFC_FLOW_DESTINATION_TYPE_FLOW_SAMPLER = 0x6, 1961 MLX5_IFC_FLOW_DESTINATION_TYPE_UPLINK = 0x8, 1962 MLX5_IFC_FLOW_DESTINATION_TYPE_TABLE_TYPE = 0xA, 1963 }; 1964 1965 enum mlx5_flow_table_miss_action { 1966 MLX5_FLOW_TABLE_MISS_ACTION_DEF, 1967 MLX5_FLOW_TABLE_MISS_ACTION_FWD, 1968 MLX5_FLOW_TABLE_MISS_ACTION_SWITCH_DOMAIN, 1969 }; 1970 1971 struct mlx5_ifc_dest_format_struct_bits { 1972 u8 destination_type[0x8]; 1973 u8 destination_id[0x18]; 1974 1975 u8 destination_eswitch_owner_vhca_id_valid[0x1]; 1976 u8 packet_reformat[0x1]; 1977 u8 reserved_at_22[0x6]; 1978 u8 destination_table_type[0x8]; 1979 u8 destination_eswitch_owner_vhca_id[0x10]; 1980 }; 1981 1982 struct mlx5_ifc_flow_counter_list_bits { 1983 u8 flow_counter_id[0x20]; 1984 1985 u8 reserved_at_20[0x20]; 1986 }; 1987 1988 struct mlx5_ifc_extended_dest_format_bits { 1989 struct mlx5_ifc_dest_format_struct_bits destination_entry; 1990 1991 u8 packet_reformat_id[0x20]; 1992 1993 u8 reserved_at_60[0x20]; 1994 }; 1995 1996 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits { 1997 struct mlx5_ifc_extended_dest_format_bits extended_dest_format; 1998 struct mlx5_ifc_flow_counter_list_bits flow_counter_list; 1999 }; 2000 2001 struct mlx5_ifc_fte_match_param_bits { 2002 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers; 2003 2004 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters; 2005 2006 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers; 2007 2008 struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2; 2009 2010 struct mlx5_ifc_fte_match_set_misc3_bits misc_parameters_3; 2011 2012 struct mlx5_ifc_fte_match_set_misc4_bits misc_parameters_4; 2013 2014 struct mlx5_ifc_fte_match_set_misc5_bits misc_parameters_5; 2015 2016 u8 reserved_at_e00[0x200]; 2017 }; 2018 2019 enum { 2020 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0, 2021 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1, 2022 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2, 2023 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3, 2024 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4, 2025 }; 2026 2027 struct mlx5_ifc_rx_hash_field_select_bits { 2028 u8 l3_prot_type[0x1]; 2029 u8 l4_prot_type[0x1]; 2030 u8 selected_fields[0x1e]; 2031 }; 2032 2033 enum { 2034 MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0, 2035 MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1, 2036 }; 2037 2038 enum { 2039 MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0, 2040 MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1, 2041 }; 2042 2043 struct mlx5_ifc_wq_bits { 2044 u8 wq_type[0x4]; 2045 u8 wq_signature[0x1]; 2046 u8 end_padding_mode[0x2]; 2047 u8 cd_slave[0x1]; 2048 u8 reserved_at_8[0x18]; 2049 2050 u8 hds_skip_first_sge[0x1]; 2051 u8 log2_hds_buf_size[0x3]; 2052 u8 reserved_at_24[0x7]; 2053 u8 page_offset[0x5]; 2054 u8 lwm[0x10]; 2055 2056 u8 reserved_at_40[0x8]; 2057 u8 pd[0x18]; 2058 2059 u8 reserved_at_60[0x8]; 2060 u8 uar_page[0x18]; 2061 2062 u8 dbr_addr[0x40]; 2063 2064 u8 hw_counter[0x20]; 2065 2066 u8 sw_counter[0x20]; 2067 2068 u8 reserved_at_100[0xc]; 2069 u8 log_wq_stride[0x4]; 2070 u8 reserved_at_110[0x3]; 2071 u8 log_wq_pg_sz[0x5]; 2072 u8 reserved_at_118[0x3]; 2073 u8 log_wq_sz[0x5]; 2074 2075 u8 dbr_umem_valid[0x1]; 2076 u8 wq_umem_valid[0x1]; 2077 u8 reserved_at_122[0x1]; 2078 u8 log_hairpin_num_packets[0x5]; 2079 u8 reserved_at_128[0x3]; 2080 u8 log_hairpin_data_sz[0x5]; 2081 2082 u8 reserved_at_130[0x4]; 2083 u8 log_wqe_num_of_strides[0x4]; 2084 u8 two_byte_shift_en[0x1]; 2085 u8 reserved_at_139[0x4]; 2086 u8 log_wqe_stride_size[0x3]; 2087 2088 u8 reserved_at_140[0x80]; 2089 2090 u8 headers_mkey[0x20]; 2091 2092 u8 shampo_enable[0x1]; 2093 u8 reserved_at_1e1[0x4]; 2094 u8 log_reservation_size[0x3]; 2095 u8 reserved_at_1e8[0x5]; 2096 u8 log_max_num_of_packets_per_reservation[0x3]; 2097 u8 reserved_at_1f0[0x6]; 2098 u8 log_headers_entry_size[0x2]; 2099 u8 reserved_at_1f8[0x4]; 2100 u8 log_headers_buffer_entry_num[0x4]; 2101 2102 u8 reserved_at_200[0x400]; 2103 2104 struct mlx5_ifc_cmd_pas_bits pas[]; 2105 }; 2106 2107 struct mlx5_ifc_rq_num_bits { 2108 u8 reserved_at_0[0x8]; 2109 u8 rq_num[0x18]; 2110 }; 2111 2112 struct mlx5_ifc_mac_address_layout_bits { 2113 u8 reserved_at_0[0x10]; 2114 u8 mac_addr_47_32[0x10]; 2115 2116 u8 mac_addr_31_0[0x20]; 2117 }; 2118 2119 struct mlx5_ifc_vlan_layout_bits { 2120 u8 reserved_at_0[0x14]; 2121 u8 vlan[0x0c]; 2122 2123 u8 reserved_at_20[0x20]; 2124 }; 2125 2126 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits { 2127 u8 reserved_at_0[0xa0]; 2128 2129 u8 min_time_between_cnps[0x20]; 2130 2131 u8 reserved_at_c0[0x12]; 2132 u8 cnp_dscp[0x6]; 2133 u8 reserved_at_d8[0x4]; 2134 u8 cnp_prio_mode[0x1]; 2135 u8 cnp_802p_prio[0x3]; 2136 2137 u8 reserved_at_e0[0x720]; 2138 }; 2139 2140 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits { 2141 u8 reserved_at_0[0x60]; 2142 2143 u8 reserved_at_60[0x4]; 2144 u8 clamp_tgt_rate[0x1]; 2145 u8 reserved_at_65[0x3]; 2146 u8 clamp_tgt_rate_after_time_inc[0x1]; 2147 u8 reserved_at_69[0x17]; 2148 2149 u8 reserved_at_80[0x20]; 2150 2151 u8 rpg_time_reset[0x20]; 2152 2153 u8 rpg_byte_reset[0x20]; 2154 2155 u8 rpg_threshold[0x20]; 2156 2157 u8 rpg_max_rate[0x20]; 2158 2159 u8 rpg_ai_rate[0x20]; 2160 2161 u8 rpg_hai_rate[0x20]; 2162 2163 u8 rpg_gd[0x20]; 2164 2165 u8 rpg_min_dec_fac[0x20]; 2166 2167 u8 rpg_min_rate[0x20]; 2168 2169 u8 reserved_at_1c0[0xe0]; 2170 2171 u8 rate_to_set_on_first_cnp[0x20]; 2172 2173 u8 dce_tcp_g[0x20]; 2174 2175 u8 dce_tcp_rtt[0x20]; 2176 2177 u8 rate_reduce_monitor_period[0x20]; 2178 2179 u8 reserved_at_320[0x20]; 2180 2181 u8 initial_alpha_value[0x20]; 2182 2183 u8 reserved_at_360[0x4a0]; 2184 }; 2185 2186 struct mlx5_ifc_cong_control_802_1qau_rp_bits { 2187 u8 reserved_at_0[0x80]; 2188 2189 u8 rppp_max_rps[0x20]; 2190 2191 u8 rpg_time_reset[0x20]; 2192 2193 u8 rpg_byte_reset[0x20]; 2194 2195 u8 rpg_threshold[0x20]; 2196 2197 u8 rpg_max_rate[0x20]; 2198 2199 u8 rpg_ai_rate[0x20]; 2200 2201 u8 rpg_hai_rate[0x20]; 2202 2203 u8 rpg_gd[0x20]; 2204 2205 u8 rpg_min_dec_fac[0x20]; 2206 2207 u8 rpg_min_rate[0x20]; 2208 2209 u8 reserved_at_1c0[0x640]; 2210 }; 2211 2212 enum { 2213 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1, 2214 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2, 2215 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4, 2216 }; 2217 2218 struct mlx5_ifc_resize_field_select_bits { 2219 u8 resize_field_select[0x20]; 2220 }; 2221 2222 struct mlx5_ifc_resource_dump_bits { 2223 u8 more_dump[0x1]; 2224 u8 inline_dump[0x1]; 2225 u8 reserved_at_2[0xa]; 2226 u8 seq_num[0x4]; 2227 u8 segment_type[0x10]; 2228 2229 u8 reserved_at_20[0x10]; 2230 u8 vhca_id[0x10]; 2231 2232 u8 index1[0x20]; 2233 2234 u8 index2[0x20]; 2235 2236 u8 num_of_obj1[0x10]; 2237 u8 num_of_obj2[0x10]; 2238 2239 u8 reserved_at_a0[0x20]; 2240 2241 u8 device_opaque[0x40]; 2242 2243 u8 mkey[0x20]; 2244 2245 u8 size[0x20]; 2246 2247 u8 address[0x40]; 2248 2249 u8 inline_data[52][0x20]; 2250 }; 2251 2252 struct mlx5_ifc_resource_dump_menu_record_bits { 2253 u8 reserved_at_0[0x4]; 2254 u8 num_of_obj2_supports_active[0x1]; 2255 u8 num_of_obj2_supports_all[0x1]; 2256 u8 must_have_num_of_obj2[0x1]; 2257 u8 support_num_of_obj2[0x1]; 2258 u8 num_of_obj1_supports_active[0x1]; 2259 u8 num_of_obj1_supports_all[0x1]; 2260 u8 must_have_num_of_obj1[0x1]; 2261 u8 support_num_of_obj1[0x1]; 2262 u8 must_have_index2[0x1]; 2263 u8 support_index2[0x1]; 2264 u8 must_have_index1[0x1]; 2265 u8 support_index1[0x1]; 2266 u8 segment_type[0x10]; 2267 2268 u8 segment_name[4][0x20]; 2269 2270 u8 index1_name[4][0x20]; 2271 2272 u8 index2_name[4][0x20]; 2273 }; 2274 2275 struct mlx5_ifc_resource_dump_segment_header_bits { 2276 u8 length_dw[0x10]; 2277 u8 segment_type[0x10]; 2278 }; 2279 2280 struct mlx5_ifc_resource_dump_command_segment_bits { 2281 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2282 2283 u8 segment_called[0x10]; 2284 u8 vhca_id[0x10]; 2285 2286 u8 index1[0x20]; 2287 2288 u8 index2[0x20]; 2289 2290 u8 num_of_obj1[0x10]; 2291 u8 num_of_obj2[0x10]; 2292 }; 2293 2294 struct mlx5_ifc_resource_dump_error_segment_bits { 2295 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2296 2297 u8 reserved_at_20[0x10]; 2298 u8 syndrome_id[0x10]; 2299 2300 u8 reserved_at_40[0x40]; 2301 2302 u8 error[8][0x20]; 2303 }; 2304 2305 struct mlx5_ifc_resource_dump_info_segment_bits { 2306 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2307 2308 u8 reserved_at_20[0x18]; 2309 u8 dump_version[0x8]; 2310 2311 u8 hw_version[0x20]; 2312 2313 u8 fw_version[0x20]; 2314 }; 2315 2316 struct mlx5_ifc_resource_dump_menu_segment_bits { 2317 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2318 2319 u8 reserved_at_20[0x10]; 2320 u8 num_of_records[0x10]; 2321 2322 struct mlx5_ifc_resource_dump_menu_record_bits record[]; 2323 }; 2324 2325 struct mlx5_ifc_resource_dump_resource_segment_bits { 2326 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2327 2328 u8 reserved_at_20[0x20]; 2329 2330 u8 index1[0x20]; 2331 2332 u8 index2[0x20]; 2333 2334 u8 payload[][0x20]; 2335 }; 2336 2337 struct mlx5_ifc_resource_dump_terminate_segment_bits { 2338 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2339 }; 2340 2341 struct mlx5_ifc_menu_resource_dump_response_bits { 2342 struct mlx5_ifc_resource_dump_info_segment_bits info; 2343 struct mlx5_ifc_resource_dump_command_segment_bits cmd; 2344 struct mlx5_ifc_resource_dump_menu_segment_bits menu; 2345 struct mlx5_ifc_resource_dump_terminate_segment_bits terminate; 2346 }; 2347 2348 enum { 2349 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1, 2350 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2, 2351 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4, 2352 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8, 2353 }; 2354 2355 struct mlx5_ifc_modify_field_select_bits { 2356 u8 modify_field_select[0x20]; 2357 }; 2358 2359 struct mlx5_ifc_field_select_r_roce_np_bits { 2360 u8 field_select_r_roce_np[0x20]; 2361 }; 2362 2363 struct mlx5_ifc_field_select_r_roce_rp_bits { 2364 u8 field_select_r_roce_rp[0x20]; 2365 }; 2366 2367 enum { 2368 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4, 2369 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8, 2370 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10, 2371 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20, 2372 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40, 2373 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80, 2374 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100, 2375 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200, 2376 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400, 2377 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800, 2378 }; 2379 2380 struct mlx5_ifc_field_select_802_1qau_rp_bits { 2381 u8 field_select_8021qaurp[0x20]; 2382 }; 2383 2384 struct mlx5_ifc_phys_layer_cntrs_bits { 2385 u8 time_since_last_clear_high[0x20]; 2386 2387 u8 time_since_last_clear_low[0x20]; 2388 2389 u8 symbol_errors_high[0x20]; 2390 2391 u8 symbol_errors_low[0x20]; 2392 2393 u8 sync_headers_errors_high[0x20]; 2394 2395 u8 sync_headers_errors_low[0x20]; 2396 2397 u8 edpl_bip_errors_lane0_high[0x20]; 2398 2399 u8 edpl_bip_errors_lane0_low[0x20]; 2400 2401 u8 edpl_bip_errors_lane1_high[0x20]; 2402 2403 u8 edpl_bip_errors_lane1_low[0x20]; 2404 2405 u8 edpl_bip_errors_lane2_high[0x20]; 2406 2407 u8 edpl_bip_errors_lane2_low[0x20]; 2408 2409 u8 edpl_bip_errors_lane3_high[0x20]; 2410 2411 u8 edpl_bip_errors_lane3_low[0x20]; 2412 2413 u8 fc_fec_corrected_blocks_lane0_high[0x20]; 2414 2415 u8 fc_fec_corrected_blocks_lane0_low[0x20]; 2416 2417 u8 fc_fec_corrected_blocks_lane1_high[0x20]; 2418 2419 u8 fc_fec_corrected_blocks_lane1_low[0x20]; 2420 2421 u8 fc_fec_corrected_blocks_lane2_high[0x20]; 2422 2423 u8 fc_fec_corrected_blocks_lane2_low[0x20]; 2424 2425 u8 fc_fec_corrected_blocks_lane3_high[0x20]; 2426 2427 u8 fc_fec_corrected_blocks_lane3_low[0x20]; 2428 2429 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20]; 2430 2431 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20]; 2432 2433 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20]; 2434 2435 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20]; 2436 2437 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20]; 2438 2439 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20]; 2440 2441 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20]; 2442 2443 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20]; 2444 2445 u8 rs_fec_corrected_blocks_high[0x20]; 2446 2447 u8 rs_fec_corrected_blocks_low[0x20]; 2448 2449 u8 rs_fec_uncorrectable_blocks_high[0x20]; 2450 2451 u8 rs_fec_uncorrectable_blocks_low[0x20]; 2452 2453 u8 rs_fec_no_errors_blocks_high[0x20]; 2454 2455 u8 rs_fec_no_errors_blocks_low[0x20]; 2456 2457 u8 rs_fec_single_error_blocks_high[0x20]; 2458 2459 u8 rs_fec_single_error_blocks_low[0x20]; 2460 2461 u8 rs_fec_corrected_symbols_total_high[0x20]; 2462 2463 u8 rs_fec_corrected_symbols_total_low[0x20]; 2464 2465 u8 rs_fec_corrected_symbols_lane0_high[0x20]; 2466 2467 u8 rs_fec_corrected_symbols_lane0_low[0x20]; 2468 2469 u8 rs_fec_corrected_symbols_lane1_high[0x20]; 2470 2471 u8 rs_fec_corrected_symbols_lane1_low[0x20]; 2472 2473 u8 rs_fec_corrected_symbols_lane2_high[0x20]; 2474 2475 u8 rs_fec_corrected_symbols_lane2_low[0x20]; 2476 2477 u8 rs_fec_corrected_symbols_lane3_high[0x20]; 2478 2479 u8 rs_fec_corrected_symbols_lane3_low[0x20]; 2480 2481 u8 link_down_events[0x20]; 2482 2483 u8 successful_recovery_events[0x20]; 2484 2485 u8 reserved_at_640[0x180]; 2486 }; 2487 2488 struct mlx5_ifc_phys_layer_statistical_cntrs_bits { 2489 u8 time_since_last_clear_high[0x20]; 2490 2491 u8 time_since_last_clear_low[0x20]; 2492 2493 u8 phy_received_bits_high[0x20]; 2494 2495 u8 phy_received_bits_low[0x20]; 2496 2497 u8 phy_symbol_errors_high[0x20]; 2498 2499 u8 phy_symbol_errors_low[0x20]; 2500 2501 u8 phy_corrected_bits_high[0x20]; 2502 2503 u8 phy_corrected_bits_low[0x20]; 2504 2505 u8 phy_corrected_bits_lane0_high[0x20]; 2506 2507 u8 phy_corrected_bits_lane0_low[0x20]; 2508 2509 u8 phy_corrected_bits_lane1_high[0x20]; 2510 2511 u8 phy_corrected_bits_lane1_low[0x20]; 2512 2513 u8 phy_corrected_bits_lane2_high[0x20]; 2514 2515 u8 phy_corrected_bits_lane2_low[0x20]; 2516 2517 u8 phy_corrected_bits_lane3_high[0x20]; 2518 2519 u8 phy_corrected_bits_lane3_low[0x20]; 2520 2521 u8 reserved_at_200[0x5c0]; 2522 }; 2523 2524 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits { 2525 u8 symbol_error_counter[0x10]; 2526 2527 u8 link_error_recovery_counter[0x8]; 2528 2529 u8 link_downed_counter[0x8]; 2530 2531 u8 port_rcv_errors[0x10]; 2532 2533 u8 port_rcv_remote_physical_errors[0x10]; 2534 2535 u8 port_rcv_switch_relay_errors[0x10]; 2536 2537 u8 port_xmit_discards[0x10]; 2538 2539 u8 port_xmit_constraint_errors[0x8]; 2540 2541 u8 port_rcv_constraint_errors[0x8]; 2542 2543 u8 reserved_at_70[0x8]; 2544 2545 u8 link_overrun_errors[0x8]; 2546 2547 u8 reserved_at_80[0x10]; 2548 2549 u8 vl_15_dropped[0x10]; 2550 2551 u8 reserved_at_a0[0x80]; 2552 2553 u8 port_xmit_wait[0x20]; 2554 }; 2555 2556 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits { 2557 u8 transmit_queue_high[0x20]; 2558 2559 u8 transmit_queue_low[0x20]; 2560 2561 u8 no_buffer_discard_uc_high[0x20]; 2562 2563 u8 no_buffer_discard_uc_low[0x20]; 2564 2565 u8 reserved_at_80[0x740]; 2566 }; 2567 2568 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits { 2569 u8 wred_discard_high[0x20]; 2570 2571 u8 wred_discard_low[0x20]; 2572 2573 u8 ecn_marked_tc_high[0x20]; 2574 2575 u8 ecn_marked_tc_low[0x20]; 2576 2577 u8 reserved_at_80[0x740]; 2578 }; 2579 2580 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits { 2581 u8 rx_octets_high[0x20]; 2582 2583 u8 rx_octets_low[0x20]; 2584 2585 u8 reserved_at_40[0xc0]; 2586 2587 u8 rx_frames_high[0x20]; 2588 2589 u8 rx_frames_low[0x20]; 2590 2591 u8 tx_octets_high[0x20]; 2592 2593 u8 tx_octets_low[0x20]; 2594 2595 u8 reserved_at_180[0xc0]; 2596 2597 u8 tx_frames_high[0x20]; 2598 2599 u8 tx_frames_low[0x20]; 2600 2601 u8 rx_pause_high[0x20]; 2602 2603 u8 rx_pause_low[0x20]; 2604 2605 u8 rx_pause_duration_high[0x20]; 2606 2607 u8 rx_pause_duration_low[0x20]; 2608 2609 u8 tx_pause_high[0x20]; 2610 2611 u8 tx_pause_low[0x20]; 2612 2613 u8 tx_pause_duration_high[0x20]; 2614 2615 u8 tx_pause_duration_low[0x20]; 2616 2617 u8 rx_pause_transition_high[0x20]; 2618 2619 u8 rx_pause_transition_low[0x20]; 2620 2621 u8 rx_discards_high[0x20]; 2622 2623 u8 rx_discards_low[0x20]; 2624 2625 u8 device_stall_minor_watermark_cnt_high[0x20]; 2626 2627 u8 device_stall_minor_watermark_cnt_low[0x20]; 2628 2629 u8 device_stall_critical_watermark_cnt_high[0x20]; 2630 2631 u8 device_stall_critical_watermark_cnt_low[0x20]; 2632 2633 u8 reserved_at_480[0x340]; 2634 }; 2635 2636 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits { 2637 u8 port_transmit_wait_high[0x20]; 2638 2639 u8 port_transmit_wait_low[0x20]; 2640 2641 u8 reserved_at_40[0x100]; 2642 2643 u8 rx_buffer_almost_full_high[0x20]; 2644 2645 u8 rx_buffer_almost_full_low[0x20]; 2646 2647 u8 rx_buffer_full_high[0x20]; 2648 2649 u8 rx_buffer_full_low[0x20]; 2650 2651 u8 rx_icrc_encapsulated_high[0x20]; 2652 2653 u8 rx_icrc_encapsulated_low[0x20]; 2654 2655 u8 reserved_at_200[0x5c0]; 2656 }; 2657 2658 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits { 2659 u8 dot3stats_alignment_errors_high[0x20]; 2660 2661 u8 dot3stats_alignment_errors_low[0x20]; 2662 2663 u8 dot3stats_fcs_errors_high[0x20]; 2664 2665 u8 dot3stats_fcs_errors_low[0x20]; 2666 2667 u8 dot3stats_single_collision_frames_high[0x20]; 2668 2669 u8 dot3stats_single_collision_frames_low[0x20]; 2670 2671 u8 dot3stats_multiple_collision_frames_high[0x20]; 2672 2673 u8 dot3stats_multiple_collision_frames_low[0x20]; 2674 2675 u8 dot3stats_sqe_test_errors_high[0x20]; 2676 2677 u8 dot3stats_sqe_test_errors_low[0x20]; 2678 2679 u8 dot3stats_deferred_transmissions_high[0x20]; 2680 2681 u8 dot3stats_deferred_transmissions_low[0x20]; 2682 2683 u8 dot3stats_late_collisions_high[0x20]; 2684 2685 u8 dot3stats_late_collisions_low[0x20]; 2686 2687 u8 dot3stats_excessive_collisions_high[0x20]; 2688 2689 u8 dot3stats_excessive_collisions_low[0x20]; 2690 2691 u8 dot3stats_internal_mac_transmit_errors_high[0x20]; 2692 2693 u8 dot3stats_internal_mac_transmit_errors_low[0x20]; 2694 2695 u8 dot3stats_carrier_sense_errors_high[0x20]; 2696 2697 u8 dot3stats_carrier_sense_errors_low[0x20]; 2698 2699 u8 dot3stats_frame_too_longs_high[0x20]; 2700 2701 u8 dot3stats_frame_too_longs_low[0x20]; 2702 2703 u8 dot3stats_internal_mac_receive_errors_high[0x20]; 2704 2705 u8 dot3stats_internal_mac_receive_errors_low[0x20]; 2706 2707 u8 dot3stats_symbol_errors_high[0x20]; 2708 2709 u8 dot3stats_symbol_errors_low[0x20]; 2710 2711 u8 dot3control_in_unknown_opcodes_high[0x20]; 2712 2713 u8 dot3control_in_unknown_opcodes_low[0x20]; 2714 2715 u8 dot3in_pause_frames_high[0x20]; 2716 2717 u8 dot3in_pause_frames_low[0x20]; 2718 2719 u8 dot3out_pause_frames_high[0x20]; 2720 2721 u8 dot3out_pause_frames_low[0x20]; 2722 2723 u8 reserved_at_400[0x3c0]; 2724 }; 2725 2726 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits { 2727 u8 ether_stats_drop_events_high[0x20]; 2728 2729 u8 ether_stats_drop_events_low[0x20]; 2730 2731 u8 ether_stats_octets_high[0x20]; 2732 2733 u8 ether_stats_octets_low[0x20]; 2734 2735 u8 ether_stats_pkts_high[0x20]; 2736 2737 u8 ether_stats_pkts_low[0x20]; 2738 2739 u8 ether_stats_broadcast_pkts_high[0x20]; 2740 2741 u8 ether_stats_broadcast_pkts_low[0x20]; 2742 2743 u8 ether_stats_multicast_pkts_high[0x20]; 2744 2745 u8 ether_stats_multicast_pkts_low[0x20]; 2746 2747 u8 ether_stats_crc_align_errors_high[0x20]; 2748 2749 u8 ether_stats_crc_align_errors_low[0x20]; 2750 2751 u8 ether_stats_undersize_pkts_high[0x20]; 2752 2753 u8 ether_stats_undersize_pkts_low[0x20]; 2754 2755 u8 ether_stats_oversize_pkts_high[0x20]; 2756 2757 u8 ether_stats_oversize_pkts_low[0x20]; 2758 2759 u8 ether_stats_fragments_high[0x20]; 2760 2761 u8 ether_stats_fragments_low[0x20]; 2762 2763 u8 ether_stats_jabbers_high[0x20]; 2764 2765 u8 ether_stats_jabbers_low[0x20]; 2766 2767 u8 ether_stats_collisions_high[0x20]; 2768 2769 u8 ether_stats_collisions_low[0x20]; 2770 2771 u8 ether_stats_pkts64octets_high[0x20]; 2772 2773 u8 ether_stats_pkts64octets_low[0x20]; 2774 2775 u8 ether_stats_pkts65to127octets_high[0x20]; 2776 2777 u8 ether_stats_pkts65to127octets_low[0x20]; 2778 2779 u8 ether_stats_pkts128to255octets_high[0x20]; 2780 2781 u8 ether_stats_pkts128to255octets_low[0x20]; 2782 2783 u8 ether_stats_pkts256to511octets_high[0x20]; 2784 2785 u8 ether_stats_pkts256to511octets_low[0x20]; 2786 2787 u8 ether_stats_pkts512to1023octets_high[0x20]; 2788 2789 u8 ether_stats_pkts512to1023octets_low[0x20]; 2790 2791 u8 ether_stats_pkts1024to1518octets_high[0x20]; 2792 2793 u8 ether_stats_pkts1024to1518octets_low[0x20]; 2794 2795 u8 ether_stats_pkts1519to2047octets_high[0x20]; 2796 2797 u8 ether_stats_pkts1519to2047octets_low[0x20]; 2798 2799 u8 ether_stats_pkts2048to4095octets_high[0x20]; 2800 2801 u8 ether_stats_pkts2048to4095octets_low[0x20]; 2802 2803 u8 ether_stats_pkts4096to8191octets_high[0x20]; 2804 2805 u8 ether_stats_pkts4096to8191octets_low[0x20]; 2806 2807 u8 ether_stats_pkts8192to10239octets_high[0x20]; 2808 2809 u8 ether_stats_pkts8192to10239octets_low[0x20]; 2810 2811 u8 reserved_at_540[0x280]; 2812 }; 2813 2814 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits { 2815 u8 if_in_octets_high[0x20]; 2816 2817 u8 if_in_octets_low[0x20]; 2818 2819 u8 if_in_ucast_pkts_high[0x20]; 2820 2821 u8 if_in_ucast_pkts_low[0x20]; 2822 2823 u8 if_in_discards_high[0x20]; 2824 2825 u8 if_in_discards_low[0x20]; 2826 2827 u8 if_in_errors_high[0x20]; 2828 2829 u8 if_in_errors_low[0x20]; 2830 2831 u8 if_in_unknown_protos_high[0x20]; 2832 2833 u8 if_in_unknown_protos_low[0x20]; 2834 2835 u8 if_out_octets_high[0x20]; 2836 2837 u8 if_out_octets_low[0x20]; 2838 2839 u8 if_out_ucast_pkts_high[0x20]; 2840 2841 u8 if_out_ucast_pkts_low[0x20]; 2842 2843 u8 if_out_discards_high[0x20]; 2844 2845 u8 if_out_discards_low[0x20]; 2846 2847 u8 if_out_errors_high[0x20]; 2848 2849 u8 if_out_errors_low[0x20]; 2850 2851 u8 if_in_multicast_pkts_high[0x20]; 2852 2853 u8 if_in_multicast_pkts_low[0x20]; 2854 2855 u8 if_in_broadcast_pkts_high[0x20]; 2856 2857 u8 if_in_broadcast_pkts_low[0x20]; 2858 2859 u8 if_out_multicast_pkts_high[0x20]; 2860 2861 u8 if_out_multicast_pkts_low[0x20]; 2862 2863 u8 if_out_broadcast_pkts_high[0x20]; 2864 2865 u8 if_out_broadcast_pkts_low[0x20]; 2866 2867 u8 reserved_at_340[0x480]; 2868 }; 2869 2870 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits { 2871 u8 a_frames_transmitted_ok_high[0x20]; 2872 2873 u8 a_frames_transmitted_ok_low[0x20]; 2874 2875 u8 a_frames_received_ok_high[0x20]; 2876 2877 u8 a_frames_received_ok_low[0x20]; 2878 2879 u8 a_frame_check_sequence_errors_high[0x20]; 2880 2881 u8 a_frame_check_sequence_errors_low[0x20]; 2882 2883 u8 a_alignment_errors_high[0x20]; 2884 2885 u8 a_alignment_errors_low[0x20]; 2886 2887 u8 a_octets_transmitted_ok_high[0x20]; 2888 2889 u8 a_octets_transmitted_ok_low[0x20]; 2890 2891 u8 a_octets_received_ok_high[0x20]; 2892 2893 u8 a_octets_received_ok_low[0x20]; 2894 2895 u8 a_multicast_frames_xmitted_ok_high[0x20]; 2896 2897 u8 a_multicast_frames_xmitted_ok_low[0x20]; 2898 2899 u8 a_broadcast_frames_xmitted_ok_high[0x20]; 2900 2901 u8 a_broadcast_frames_xmitted_ok_low[0x20]; 2902 2903 u8 a_multicast_frames_received_ok_high[0x20]; 2904 2905 u8 a_multicast_frames_received_ok_low[0x20]; 2906 2907 u8 a_broadcast_frames_received_ok_high[0x20]; 2908 2909 u8 a_broadcast_frames_received_ok_low[0x20]; 2910 2911 u8 a_in_range_length_errors_high[0x20]; 2912 2913 u8 a_in_range_length_errors_low[0x20]; 2914 2915 u8 a_out_of_range_length_field_high[0x20]; 2916 2917 u8 a_out_of_range_length_field_low[0x20]; 2918 2919 u8 a_frame_too_long_errors_high[0x20]; 2920 2921 u8 a_frame_too_long_errors_low[0x20]; 2922 2923 u8 a_symbol_error_during_carrier_high[0x20]; 2924 2925 u8 a_symbol_error_during_carrier_low[0x20]; 2926 2927 u8 a_mac_control_frames_transmitted_high[0x20]; 2928 2929 u8 a_mac_control_frames_transmitted_low[0x20]; 2930 2931 u8 a_mac_control_frames_received_high[0x20]; 2932 2933 u8 a_mac_control_frames_received_low[0x20]; 2934 2935 u8 a_unsupported_opcodes_received_high[0x20]; 2936 2937 u8 a_unsupported_opcodes_received_low[0x20]; 2938 2939 u8 a_pause_mac_ctrl_frames_received_high[0x20]; 2940 2941 u8 a_pause_mac_ctrl_frames_received_low[0x20]; 2942 2943 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20]; 2944 2945 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20]; 2946 2947 u8 reserved_at_4c0[0x300]; 2948 }; 2949 2950 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits { 2951 u8 life_time_counter_high[0x20]; 2952 2953 u8 life_time_counter_low[0x20]; 2954 2955 u8 rx_errors[0x20]; 2956 2957 u8 tx_errors[0x20]; 2958 2959 u8 l0_to_recovery_eieos[0x20]; 2960 2961 u8 l0_to_recovery_ts[0x20]; 2962 2963 u8 l0_to_recovery_framing[0x20]; 2964 2965 u8 l0_to_recovery_retrain[0x20]; 2966 2967 u8 crc_error_dllp[0x20]; 2968 2969 u8 crc_error_tlp[0x20]; 2970 2971 u8 tx_overflow_buffer_pkt_high[0x20]; 2972 2973 u8 tx_overflow_buffer_pkt_low[0x20]; 2974 2975 u8 outbound_stalled_reads[0x20]; 2976 2977 u8 outbound_stalled_writes[0x20]; 2978 2979 u8 outbound_stalled_reads_events[0x20]; 2980 2981 u8 outbound_stalled_writes_events[0x20]; 2982 2983 u8 reserved_at_200[0x5c0]; 2984 }; 2985 2986 struct mlx5_ifc_cmd_inter_comp_event_bits { 2987 u8 command_completion_vector[0x20]; 2988 2989 u8 reserved_at_20[0xc0]; 2990 }; 2991 2992 struct mlx5_ifc_stall_vl_event_bits { 2993 u8 reserved_at_0[0x18]; 2994 u8 port_num[0x1]; 2995 u8 reserved_at_19[0x3]; 2996 u8 vl[0x4]; 2997 2998 u8 reserved_at_20[0xa0]; 2999 }; 3000 3001 struct mlx5_ifc_db_bf_congestion_event_bits { 3002 u8 event_subtype[0x8]; 3003 u8 reserved_at_8[0x8]; 3004 u8 congestion_level[0x8]; 3005 u8 reserved_at_18[0x8]; 3006 3007 u8 reserved_at_20[0xa0]; 3008 }; 3009 3010 struct mlx5_ifc_gpio_event_bits { 3011 u8 reserved_at_0[0x60]; 3012 3013 u8 gpio_event_hi[0x20]; 3014 3015 u8 gpio_event_lo[0x20]; 3016 3017 u8 reserved_at_a0[0x40]; 3018 }; 3019 3020 struct mlx5_ifc_port_state_change_event_bits { 3021 u8 reserved_at_0[0x40]; 3022 3023 u8 port_num[0x4]; 3024 u8 reserved_at_44[0x1c]; 3025 3026 u8 reserved_at_60[0x80]; 3027 }; 3028 3029 struct mlx5_ifc_dropped_packet_logged_bits { 3030 u8 reserved_at_0[0xe0]; 3031 }; 3032 3033 struct mlx5_ifc_default_timeout_bits { 3034 u8 to_multiplier[0x3]; 3035 u8 reserved_at_3[0x9]; 3036 u8 to_value[0x14]; 3037 }; 3038 3039 struct mlx5_ifc_dtor_reg_bits { 3040 u8 reserved_at_0[0x20]; 3041 3042 struct mlx5_ifc_default_timeout_bits pcie_toggle_to; 3043 3044 u8 reserved_at_40[0x60]; 3045 3046 struct mlx5_ifc_default_timeout_bits health_poll_to; 3047 3048 struct mlx5_ifc_default_timeout_bits full_crdump_to; 3049 3050 struct mlx5_ifc_default_timeout_bits fw_reset_to; 3051 3052 struct mlx5_ifc_default_timeout_bits flush_on_err_to; 3053 3054 struct mlx5_ifc_default_timeout_bits pci_sync_update_to; 3055 3056 struct mlx5_ifc_default_timeout_bits tear_down_to; 3057 3058 struct mlx5_ifc_default_timeout_bits fsm_reactivate_to; 3059 3060 struct mlx5_ifc_default_timeout_bits reclaim_pages_to; 3061 3062 struct mlx5_ifc_default_timeout_bits reclaim_vfs_pages_to; 3063 3064 u8 reserved_at_1c0[0x40]; 3065 }; 3066 3067 enum { 3068 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1, 3069 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2, 3070 }; 3071 3072 struct mlx5_ifc_cq_error_bits { 3073 u8 reserved_at_0[0x8]; 3074 u8 cqn[0x18]; 3075 3076 u8 reserved_at_20[0x20]; 3077 3078 u8 reserved_at_40[0x18]; 3079 u8 syndrome[0x8]; 3080 3081 u8 reserved_at_60[0x80]; 3082 }; 3083 3084 struct mlx5_ifc_rdma_page_fault_event_bits { 3085 u8 bytes_committed[0x20]; 3086 3087 u8 r_key[0x20]; 3088 3089 u8 reserved_at_40[0x10]; 3090 u8 packet_len[0x10]; 3091 3092 u8 rdma_op_len[0x20]; 3093 3094 u8 rdma_va[0x40]; 3095 3096 u8 reserved_at_c0[0x5]; 3097 u8 rdma[0x1]; 3098 u8 write[0x1]; 3099 u8 requestor[0x1]; 3100 u8 qp_number[0x18]; 3101 }; 3102 3103 struct mlx5_ifc_wqe_associated_page_fault_event_bits { 3104 u8 bytes_committed[0x20]; 3105 3106 u8 reserved_at_20[0x10]; 3107 u8 wqe_index[0x10]; 3108 3109 u8 reserved_at_40[0x10]; 3110 u8 len[0x10]; 3111 3112 u8 reserved_at_60[0x60]; 3113 3114 u8 reserved_at_c0[0x5]; 3115 u8 rdma[0x1]; 3116 u8 write_read[0x1]; 3117 u8 requestor[0x1]; 3118 u8 qpn[0x18]; 3119 }; 3120 3121 struct mlx5_ifc_qp_events_bits { 3122 u8 reserved_at_0[0xa0]; 3123 3124 u8 type[0x8]; 3125 u8 reserved_at_a8[0x18]; 3126 3127 u8 reserved_at_c0[0x8]; 3128 u8 qpn_rqn_sqn[0x18]; 3129 }; 3130 3131 struct mlx5_ifc_dct_events_bits { 3132 u8 reserved_at_0[0xc0]; 3133 3134 u8 reserved_at_c0[0x8]; 3135 u8 dct_number[0x18]; 3136 }; 3137 3138 struct mlx5_ifc_comp_event_bits { 3139 u8 reserved_at_0[0xc0]; 3140 3141 u8 reserved_at_c0[0x8]; 3142 u8 cq_number[0x18]; 3143 }; 3144 3145 enum { 3146 MLX5_QPC_STATE_RST = 0x0, 3147 MLX5_QPC_STATE_INIT = 0x1, 3148 MLX5_QPC_STATE_RTR = 0x2, 3149 MLX5_QPC_STATE_RTS = 0x3, 3150 MLX5_QPC_STATE_SQER = 0x4, 3151 MLX5_QPC_STATE_ERR = 0x6, 3152 MLX5_QPC_STATE_SQD = 0x7, 3153 MLX5_QPC_STATE_SUSPENDED = 0x9, 3154 }; 3155 3156 enum { 3157 MLX5_QPC_ST_RC = 0x0, 3158 MLX5_QPC_ST_UC = 0x1, 3159 MLX5_QPC_ST_UD = 0x2, 3160 MLX5_QPC_ST_XRC = 0x3, 3161 MLX5_QPC_ST_DCI = 0x5, 3162 MLX5_QPC_ST_QP0 = 0x7, 3163 MLX5_QPC_ST_QP1 = 0x8, 3164 MLX5_QPC_ST_RAW_DATAGRAM = 0x9, 3165 MLX5_QPC_ST_REG_UMR = 0xc, 3166 }; 3167 3168 enum { 3169 MLX5_QPC_PM_STATE_ARMED = 0x0, 3170 MLX5_QPC_PM_STATE_REARM = 0x1, 3171 MLX5_QPC_PM_STATE_RESERVED = 0x2, 3172 MLX5_QPC_PM_STATE_MIGRATED = 0x3, 3173 }; 3174 3175 enum { 3176 MLX5_QPC_OFFLOAD_TYPE_RNDV = 0x1, 3177 }; 3178 3179 enum { 3180 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0, 3181 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1, 3182 }; 3183 3184 enum { 3185 MLX5_QPC_MTU_256_BYTES = 0x1, 3186 MLX5_QPC_MTU_512_BYTES = 0x2, 3187 MLX5_QPC_MTU_1K_BYTES = 0x3, 3188 MLX5_QPC_MTU_2K_BYTES = 0x4, 3189 MLX5_QPC_MTU_4K_BYTES = 0x5, 3190 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7, 3191 }; 3192 3193 enum { 3194 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1, 3195 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2, 3196 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3, 3197 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4, 3198 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5, 3199 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6, 3200 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7, 3201 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8, 3202 }; 3203 3204 enum { 3205 MLX5_QPC_CS_REQ_DISABLE = 0x0, 3206 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11, 3207 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22, 3208 }; 3209 3210 enum { 3211 MLX5_QPC_CS_RES_DISABLE = 0x0, 3212 MLX5_QPC_CS_RES_UP_TO_32B = 0x1, 3213 MLX5_QPC_CS_RES_UP_TO_64B = 0x2, 3214 }; 3215 3216 enum { 3217 MLX5_TIMESTAMP_FORMAT_FREE_RUNNING = 0x0, 3218 MLX5_TIMESTAMP_FORMAT_DEFAULT = 0x1, 3219 MLX5_TIMESTAMP_FORMAT_REAL_TIME = 0x2, 3220 }; 3221 3222 struct mlx5_ifc_qpc_bits { 3223 u8 state[0x4]; 3224 u8 lag_tx_port_affinity[0x4]; 3225 u8 st[0x8]; 3226 u8 reserved_at_10[0x2]; 3227 u8 isolate_vl_tc[0x1]; 3228 u8 pm_state[0x2]; 3229 u8 reserved_at_15[0x1]; 3230 u8 req_e2e_credit_mode[0x2]; 3231 u8 offload_type[0x4]; 3232 u8 end_padding_mode[0x2]; 3233 u8 reserved_at_1e[0x2]; 3234 3235 u8 wq_signature[0x1]; 3236 u8 block_lb_mc[0x1]; 3237 u8 atomic_like_write_en[0x1]; 3238 u8 latency_sensitive[0x1]; 3239 u8 reserved_at_24[0x1]; 3240 u8 drain_sigerr[0x1]; 3241 u8 reserved_at_26[0x2]; 3242 u8 pd[0x18]; 3243 3244 u8 mtu[0x3]; 3245 u8 log_msg_max[0x5]; 3246 u8 reserved_at_48[0x1]; 3247 u8 log_rq_size[0x4]; 3248 u8 log_rq_stride[0x3]; 3249 u8 no_sq[0x1]; 3250 u8 log_sq_size[0x4]; 3251 u8 reserved_at_55[0x3]; 3252 u8 ts_format[0x2]; 3253 u8 reserved_at_5a[0x1]; 3254 u8 rlky[0x1]; 3255 u8 ulp_stateless_offload_mode[0x4]; 3256 3257 u8 counter_set_id[0x8]; 3258 u8 uar_page[0x18]; 3259 3260 u8 reserved_at_80[0x8]; 3261 u8 user_index[0x18]; 3262 3263 u8 reserved_at_a0[0x3]; 3264 u8 log_page_size[0x5]; 3265 u8 remote_qpn[0x18]; 3266 3267 struct mlx5_ifc_ads_bits primary_address_path; 3268 3269 struct mlx5_ifc_ads_bits secondary_address_path; 3270 3271 u8 log_ack_req_freq[0x4]; 3272 u8 reserved_at_384[0x4]; 3273 u8 log_sra_max[0x3]; 3274 u8 reserved_at_38b[0x2]; 3275 u8 retry_count[0x3]; 3276 u8 rnr_retry[0x3]; 3277 u8 reserved_at_393[0x1]; 3278 u8 fre[0x1]; 3279 u8 cur_rnr_retry[0x3]; 3280 u8 cur_retry_count[0x3]; 3281 u8 reserved_at_39b[0x5]; 3282 3283 u8 reserved_at_3a0[0x20]; 3284 3285 u8 reserved_at_3c0[0x8]; 3286 u8 next_send_psn[0x18]; 3287 3288 u8 reserved_at_3e0[0x3]; 3289 u8 log_num_dci_stream_channels[0x5]; 3290 u8 cqn_snd[0x18]; 3291 3292 u8 reserved_at_400[0x3]; 3293 u8 log_num_dci_errored_streams[0x5]; 3294 u8 deth_sqpn[0x18]; 3295 3296 u8 reserved_at_420[0x20]; 3297 3298 u8 reserved_at_440[0x8]; 3299 u8 last_acked_psn[0x18]; 3300 3301 u8 reserved_at_460[0x8]; 3302 u8 ssn[0x18]; 3303 3304 u8 reserved_at_480[0x8]; 3305 u8 log_rra_max[0x3]; 3306 u8 reserved_at_48b[0x1]; 3307 u8 atomic_mode[0x4]; 3308 u8 rre[0x1]; 3309 u8 rwe[0x1]; 3310 u8 rae[0x1]; 3311 u8 reserved_at_493[0x1]; 3312 u8 page_offset[0x6]; 3313 u8 reserved_at_49a[0x3]; 3314 u8 cd_slave_receive[0x1]; 3315 u8 cd_slave_send[0x1]; 3316 u8 cd_master[0x1]; 3317 3318 u8 reserved_at_4a0[0x3]; 3319 u8 min_rnr_nak[0x5]; 3320 u8 next_rcv_psn[0x18]; 3321 3322 u8 reserved_at_4c0[0x8]; 3323 u8 xrcd[0x18]; 3324 3325 u8 reserved_at_4e0[0x8]; 3326 u8 cqn_rcv[0x18]; 3327 3328 u8 dbr_addr[0x40]; 3329 3330 u8 q_key[0x20]; 3331 3332 u8 reserved_at_560[0x5]; 3333 u8 rq_type[0x3]; 3334 u8 srqn_rmpn_xrqn[0x18]; 3335 3336 u8 reserved_at_580[0x8]; 3337 u8 rmsn[0x18]; 3338 3339 u8 hw_sq_wqebb_counter[0x10]; 3340 u8 sw_sq_wqebb_counter[0x10]; 3341 3342 u8 hw_rq_counter[0x20]; 3343 3344 u8 sw_rq_counter[0x20]; 3345 3346 u8 reserved_at_600[0x20]; 3347 3348 u8 reserved_at_620[0xf]; 3349 u8 cgs[0x1]; 3350 u8 cs_req[0x8]; 3351 u8 cs_res[0x8]; 3352 3353 u8 dc_access_key[0x40]; 3354 3355 u8 reserved_at_680[0x3]; 3356 u8 dbr_umem_valid[0x1]; 3357 3358 u8 reserved_at_684[0xbc]; 3359 }; 3360 3361 struct mlx5_ifc_roce_addr_layout_bits { 3362 u8 source_l3_address[16][0x8]; 3363 3364 u8 reserved_at_80[0x3]; 3365 u8 vlan_valid[0x1]; 3366 u8 vlan_id[0xc]; 3367 u8 source_mac_47_32[0x10]; 3368 3369 u8 source_mac_31_0[0x20]; 3370 3371 u8 reserved_at_c0[0x14]; 3372 u8 roce_l3_type[0x4]; 3373 u8 roce_version[0x8]; 3374 3375 u8 reserved_at_e0[0x20]; 3376 }; 3377 3378 struct mlx5_ifc_shampo_cap_bits { 3379 u8 reserved_at_0[0x3]; 3380 u8 shampo_log_max_reservation_size[0x5]; 3381 u8 reserved_at_8[0x3]; 3382 u8 shampo_log_min_reservation_size[0x5]; 3383 u8 shampo_min_mss_size[0x10]; 3384 3385 u8 reserved_at_20[0x3]; 3386 u8 shampo_max_log_headers_entry_size[0x5]; 3387 u8 reserved_at_28[0x18]; 3388 3389 u8 reserved_at_40[0x7c0]; 3390 }; 3391 3392 struct mlx5_ifc_crypto_cap_bits { 3393 u8 reserved_at_0[0x3]; 3394 u8 synchronize_dek[0x1]; 3395 u8 int_kek_manual[0x1]; 3396 u8 int_kek_auto[0x1]; 3397 u8 reserved_at_6[0x1a]; 3398 3399 u8 reserved_at_20[0x3]; 3400 u8 log_dek_max_alloc[0x5]; 3401 u8 reserved_at_28[0x3]; 3402 u8 log_max_num_deks[0x5]; 3403 u8 reserved_at_30[0x10]; 3404 3405 u8 reserved_at_40[0x20]; 3406 3407 u8 reserved_at_60[0x3]; 3408 u8 log_dek_granularity[0x5]; 3409 u8 reserved_at_68[0x3]; 3410 u8 log_max_num_int_kek[0x5]; 3411 u8 sw_wrapped_dek[0x10]; 3412 3413 u8 reserved_at_80[0x780]; 3414 }; 3415 3416 union mlx5_ifc_hca_cap_union_bits { 3417 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap; 3418 struct mlx5_ifc_cmd_hca_cap_2_bits cmd_hca_cap_2; 3419 struct mlx5_ifc_odp_cap_bits odp_cap; 3420 struct mlx5_ifc_atomic_caps_bits atomic_caps; 3421 struct mlx5_ifc_roce_cap_bits roce_cap; 3422 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps; 3423 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap; 3424 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap; 3425 struct mlx5_ifc_e_switch_cap_bits e_switch_cap; 3426 struct mlx5_ifc_port_selection_cap_bits port_selection_cap; 3427 struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap; 3428 struct mlx5_ifc_qos_cap_bits qos_cap; 3429 struct mlx5_ifc_debug_cap_bits debug_cap; 3430 struct mlx5_ifc_fpga_cap_bits fpga_cap; 3431 struct mlx5_ifc_tls_cap_bits tls_cap; 3432 struct mlx5_ifc_device_mem_cap_bits device_mem_cap; 3433 struct mlx5_ifc_virtio_emulation_cap_bits virtio_emulation_cap; 3434 struct mlx5_ifc_shampo_cap_bits shampo_cap; 3435 struct mlx5_ifc_macsec_cap_bits macsec_cap; 3436 struct mlx5_ifc_crypto_cap_bits crypto_cap; 3437 u8 reserved_at_0[0x8000]; 3438 }; 3439 3440 enum { 3441 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1, 3442 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2, 3443 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4, 3444 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8, 3445 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT = 0x10, 3446 MLX5_FLOW_CONTEXT_ACTION_DECAP = 0x20, 3447 MLX5_FLOW_CONTEXT_ACTION_MOD_HDR = 0x40, 3448 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP = 0x80, 3449 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100, 3450 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2 = 0x400, 3451 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2 = 0x800, 3452 MLX5_FLOW_CONTEXT_ACTION_CRYPTO_DECRYPT = 0x1000, 3453 MLX5_FLOW_CONTEXT_ACTION_CRYPTO_ENCRYPT = 0x2000, 3454 MLX5_FLOW_CONTEXT_ACTION_EXECUTE_ASO = 0x4000, 3455 }; 3456 3457 enum { 3458 MLX5_FLOW_CONTEXT_FLOW_SOURCE_ANY_VPORT = 0x0, 3459 MLX5_FLOW_CONTEXT_FLOW_SOURCE_UPLINK = 0x1, 3460 MLX5_FLOW_CONTEXT_FLOW_SOURCE_LOCAL_VPORT = 0x2, 3461 }; 3462 3463 enum { 3464 MLX5_FLOW_CONTEXT_ENCRYPT_DECRYPT_TYPE_IPSEC = 0x0, 3465 MLX5_FLOW_CONTEXT_ENCRYPT_DECRYPT_TYPE_MACSEC = 0x1, 3466 }; 3467 3468 struct mlx5_ifc_vlan_bits { 3469 u8 ethtype[0x10]; 3470 u8 prio[0x3]; 3471 u8 cfi[0x1]; 3472 u8 vid[0xc]; 3473 }; 3474 3475 enum { 3476 MLX5_FLOW_METER_COLOR_RED = 0x0, 3477 MLX5_FLOW_METER_COLOR_YELLOW = 0x1, 3478 MLX5_FLOW_METER_COLOR_GREEN = 0x2, 3479 MLX5_FLOW_METER_COLOR_UNDEFINED = 0x3, 3480 }; 3481 3482 enum { 3483 MLX5_EXE_ASO_FLOW_METER = 0x2, 3484 }; 3485 3486 struct mlx5_ifc_exe_aso_ctrl_flow_meter_bits { 3487 u8 return_reg_id[0x4]; 3488 u8 aso_type[0x4]; 3489 u8 reserved_at_8[0x14]; 3490 u8 action[0x1]; 3491 u8 init_color[0x2]; 3492 u8 meter_id[0x1]; 3493 }; 3494 3495 union mlx5_ifc_exe_aso_ctrl { 3496 struct mlx5_ifc_exe_aso_ctrl_flow_meter_bits exe_aso_ctrl_flow_meter; 3497 }; 3498 3499 struct mlx5_ifc_execute_aso_bits { 3500 u8 valid[0x1]; 3501 u8 reserved_at_1[0x7]; 3502 u8 aso_object_id[0x18]; 3503 3504 union mlx5_ifc_exe_aso_ctrl exe_aso_ctrl; 3505 }; 3506 3507 struct mlx5_ifc_flow_context_bits { 3508 struct mlx5_ifc_vlan_bits push_vlan; 3509 3510 u8 group_id[0x20]; 3511 3512 u8 reserved_at_40[0x8]; 3513 u8 flow_tag[0x18]; 3514 3515 u8 reserved_at_60[0x10]; 3516 u8 action[0x10]; 3517 3518 u8 extended_destination[0x1]; 3519 u8 reserved_at_81[0x1]; 3520 u8 flow_source[0x2]; 3521 u8 encrypt_decrypt_type[0x4]; 3522 u8 destination_list_size[0x18]; 3523 3524 u8 reserved_at_a0[0x8]; 3525 u8 flow_counter_list_size[0x18]; 3526 3527 u8 packet_reformat_id[0x20]; 3528 3529 u8 modify_header_id[0x20]; 3530 3531 struct mlx5_ifc_vlan_bits push_vlan_2; 3532 3533 u8 encrypt_decrypt_obj_id[0x20]; 3534 u8 reserved_at_140[0xc0]; 3535 3536 struct mlx5_ifc_fte_match_param_bits match_value; 3537 3538 struct mlx5_ifc_execute_aso_bits execute_aso[4]; 3539 3540 u8 reserved_at_1300[0x500]; 3541 3542 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[]; 3543 }; 3544 3545 enum { 3546 MLX5_XRC_SRQC_STATE_GOOD = 0x0, 3547 MLX5_XRC_SRQC_STATE_ERROR = 0x1, 3548 }; 3549 3550 struct mlx5_ifc_xrc_srqc_bits { 3551 u8 state[0x4]; 3552 u8 log_xrc_srq_size[0x4]; 3553 u8 reserved_at_8[0x18]; 3554 3555 u8 wq_signature[0x1]; 3556 u8 cont_srq[0x1]; 3557 u8 reserved_at_22[0x1]; 3558 u8 rlky[0x1]; 3559 u8 basic_cyclic_rcv_wqe[0x1]; 3560 u8 log_rq_stride[0x3]; 3561 u8 xrcd[0x18]; 3562 3563 u8 page_offset[0x6]; 3564 u8 reserved_at_46[0x1]; 3565 u8 dbr_umem_valid[0x1]; 3566 u8 cqn[0x18]; 3567 3568 u8 reserved_at_60[0x20]; 3569 3570 u8 user_index_equal_xrc_srqn[0x1]; 3571 u8 reserved_at_81[0x1]; 3572 u8 log_page_size[0x6]; 3573 u8 user_index[0x18]; 3574 3575 u8 reserved_at_a0[0x20]; 3576 3577 u8 reserved_at_c0[0x8]; 3578 u8 pd[0x18]; 3579 3580 u8 lwm[0x10]; 3581 u8 wqe_cnt[0x10]; 3582 3583 u8 reserved_at_100[0x40]; 3584 3585 u8 db_record_addr_h[0x20]; 3586 3587 u8 db_record_addr_l[0x1e]; 3588 u8 reserved_at_17e[0x2]; 3589 3590 u8 reserved_at_180[0x80]; 3591 }; 3592 3593 struct mlx5_ifc_vnic_diagnostic_statistics_bits { 3594 u8 counter_error_queues[0x20]; 3595 3596 u8 total_error_queues[0x20]; 3597 3598 u8 send_queue_priority_update_flow[0x20]; 3599 3600 u8 reserved_at_60[0x20]; 3601 3602 u8 nic_receive_steering_discard[0x40]; 3603 3604 u8 receive_discard_vport_down[0x40]; 3605 3606 u8 transmit_discard_vport_down[0x40]; 3607 3608 u8 async_eq_overrun[0x20]; 3609 3610 u8 comp_eq_overrun[0x20]; 3611 3612 u8 reserved_at_180[0x20]; 3613 3614 u8 invalid_command[0x20]; 3615 3616 u8 quota_exceeded_command[0x20]; 3617 3618 u8 internal_rq_out_of_buffer[0x20]; 3619 3620 u8 cq_overrun[0x20]; 3621 3622 u8 eth_wqe_too_small[0x20]; 3623 3624 u8 reserved_at_220[0xdc0]; 3625 }; 3626 3627 struct mlx5_ifc_traffic_counter_bits { 3628 u8 packets[0x40]; 3629 3630 u8 octets[0x40]; 3631 }; 3632 3633 struct mlx5_ifc_tisc_bits { 3634 u8 strict_lag_tx_port_affinity[0x1]; 3635 u8 tls_en[0x1]; 3636 u8 reserved_at_2[0x2]; 3637 u8 lag_tx_port_affinity[0x04]; 3638 3639 u8 reserved_at_8[0x4]; 3640 u8 prio[0x4]; 3641 u8 reserved_at_10[0x10]; 3642 3643 u8 reserved_at_20[0x100]; 3644 3645 u8 reserved_at_120[0x8]; 3646 u8 transport_domain[0x18]; 3647 3648 u8 reserved_at_140[0x8]; 3649 u8 underlay_qpn[0x18]; 3650 3651 u8 reserved_at_160[0x8]; 3652 u8 pd[0x18]; 3653 3654 u8 reserved_at_180[0x380]; 3655 }; 3656 3657 enum { 3658 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0, 3659 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1, 3660 }; 3661 3662 enum { 3663 MLX5_TIRC_PACKET_MERGE_MASK_IPV4_LRO = BIT(0), 3664 MLX5_TIRC_PACKET_MERGE_MASK_IPV6_LRO = BIT(1), 3665 }; 3666 3667 enum { 3668 MLX5_RX_HASH_FN_NONE = 0x0, 3669 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1, 3670 MLX5_RX_HASH_FN_TOEPLITZ = 0x2, 3671 }; 3672 3673 enum { 3674 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST = 0x1, 3675 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST = 0x2, 3676 }; 3677 3678 struct mlx5_ifc_tirc_bits { 3679 u8 reserved_at_0[0x20]; 3680 3681 u8 disp_type[0x4]; 3682 u8 tls_en[0x1]; 3683 u8 reserved_at_25[0x1b]; 3684 3685 u8 reserved_at_40[0x40]; 3686 3687 u8 reserved_at_80[0x4]; 3688 u8 lro_timeout_period_usecs[0x10]; 3689 u8 packet_merge_mask[0x4]; 3690 u8 lro_max_ip_payload_size[0x8]; 3691 3692 u8 reserved_at_a0[0x40]; 3693 3694 u8 reserved_at_e0[0x8]; 3695 u8 inline_rqn[0x18]; 3696 3697 u8 rx_hash_symmetric[0x1]; 3698 u8 reserved_at_101[0x1]; 3699 u8 tunneled_offload_en[0x1]; 3700 u8 reserved_at_103[0x5]; 3701 u8 indirect_table[0x18]; 3702 3703 u8 rx_hash_fn[0x4]; 3704 u8 reserved_at_124[0x2]; 3705 u8 self_lb_block[0x2]; 3706 u8 transport_domain[0x18]; 3707 3708 u8 rx_hash_toeplitz_key[10][0x20]; 3709 3710 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer; 3711 3712 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner; 3713 3714 u8 reserved_at_2c0[0x4c0]; 3715 }; 3716 3717 enum { 3718 MLX5_SRQC_STATE_GOOD = 0x0, 3719 MLX5_SRQC_STATE_ERROR = 0x1, 3720 }; 3721 3722 struct mlx5_ifc_srqc_bits { 3723 u8 state[0x4]; 3724 u8 log_srq_size[0x4]; 3725 u8 reserved_at_8[0x18]; 3726 3727 u8 wq_signature[0x1]; 3728 u8 cont_srq[0x1]; 3729 u8 reserved_at_22[0x1]; 3730 u8 rlky[0x1]; 3731 u8 reserved_at_24[0x1]; 3732 u8 log_rq_stride[0x3]; 3733 u8 xrcd[0x18]; 3734 3735 u8 page_offset[0x6]; 3736 u8 reserved_at_46[0x2]; 3737 u8 cqn[0x18]; 3738 3739 u8 reserved_at_60[0x20]; 3740 3741 u8 reserved_at_80[0x2]; 3742 u8 log_page_size[0x6]; 3743 u8 reserved_at_88[0x18]; 3744 3745 u8 reserved_at_a0[0x20]; 3746 3747 u8 reserved_at_c0[0x8]; 3748 u8 pd[0x18]; 3749 3750 u8 lwm[0x10]; 3751 u8 wqe_cnt[0x10]; 3752 3753 u8 reserved_at_100[0x40]; 3754 3755 u8 dbr_addr[0x40]; 3756 3757 u8 reserved_at_180[0x80]; 3758 }; 3759 3760 enum { 3761 MLX5_SQC_STATE_RST = 0x0, 3762 MLX5_SQC_STATE_RDY = 0x1, 3763 MLX5_SQC_STATE_ERR = 0x3, 3764 }; 3765 3766 struct mlx5_ifc_sqc_bits { 3767 u8 rlky[0x1]; 3768 u8 cd_master[0x1]; 3769 u8 fre[0x1]; 3770 u8 flush_in_error_en[0x1]; 3771 u8 allow_multi_pkt_send_wqe[0x1]; 3772 u8 min_wqe_inline_mode[0x3]; 3773 u8 state[0x4]; 3774 u8 reg_umr[0x1]; 3775 u8 allow_swp[0x1]; 3776 u8 hairpin[0x1]; 3777 u8 reserved_at_f[0xb]; 3778 u8 ts_format[0x2]; 3779 u8 reserved_at_1c[0x4]; 3780 3781 u8 reserved_at_20[0x8]; 3782 u8 user_index[0x18]; 3783 3784 u8 reserved_at_40[0x8]; 3785 u8 cqn[0x18]; 3786 3787 u8 reserved_at_60[0x8]; 3788 u8 hairpin_peer_rq[0x18]; 3789 3790 u8 reserved_at_80[0x10]; 3791 u8 hairpin_peer_vhca[0x10]; 3792 3793 u8 reserved_at_a0[0x20]; 3794 3795 u8 reserved_at_c0[0x8]; 3796 u8 ts_cqe_to_dest_cqn[0x18]; 3797 3798 u8 reserved_at_e0[0x10]; 3799 u8 packet_pacing_rate_limit_index[0x10]; 3800 u8 tis_lst_sz[0x10]; 3801 u8 qos_queue_group_id[0x10]; 3802 3803 u8 reserved_at_120[0x40]; 3804 3805 u8 reserved_at_160[0x8]; 3806 u8 tis_num_0[0x18]; 3807 3808 struct mlx5_ifc_wq_bits wq; 3809 }; 3810 3811 enum { 3812 SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0, 3813 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1, 3814 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2, 3815 SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3, 3816 SCHEDULING_CONTEXT_ELEMENT_TYPE_QUEUE_GROUP = 0x4, 3817 }; 3818 3819 enum { 3820 ELEMENT_TYPE_CAP_MASK_TASR = 1 << 0, 3821 ELEMENT_TYPE_CAP_MASK_VPORT = 1 << 1, 3822 ELEMENT_TYPE_CAP_MASK_VPORT_TC = 1 << 2, 3823 ELEMENT_TYPE_CAP_MASK_PARA_VPORT_TC = 1 << 3, 3824 }; 3825 3826 struct mlx5_ifc_scheduling_context_bits { 3827 u8 element_type[0x8]; 3828 u8 reserved_at_8[0x18]; 3829 3830 u8 element_attributes[0x20]; 3831 3832 u8 parent_element_id[0x20]; 3833 3834 u8 reserved_at_60[0x40]; 3835 3836 u8 bw_share[0x20]; 3837 3838 u8 max_average_bw[0x20]; 3839 3840 u8 reserved_at_e0[0x120]; 3841 }; 3842 3843 struct mlx5_ifc_rqtc_bits { 3844 u8 reserved_at_0[0xa0]; 3845 3846 u8 reserved_at_a0[0x5]; 3847 u8 list_q_type[0x3]; 3848 u8 reserved_at_a8[0x8]; 3849 u8 rqt_max_size[0x10]; 3850 3851 u8 rq_vhca_id_format[0x1]; 3852 u8 reserved_at_c1[0xf]; 3853 u8 rqt_actual_size[0x10]; 3854 3855 u8 reserved_at_e0[0x6a0]; 3856 3857 struct mlx5_ifc_rq_num_bits rq_num[]; 3858 }; 3859 3860 enum { 3861 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0, 3862 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1, 3863 }; 3864 3865 enum { 3866 MLX5_RQC_STATE_RST = 0x0, 3867 MLX5_RQC_STATE_RDY = 0x1, 3868 MLX5_RQC_STATE_ERR = 0x3, 3869 }; 3870 3871 enum { 3872 MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_BYTE = 0x0, 3873 MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_STRIDE = 0x1, 3874 MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_PAGE = 0x2, 3875 }; 3876 3877 enum { 3878 MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_NO_MATCH = 0x0, 3879 MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_EXTENDED = 0x1, 3880 MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_FIVE_TUPLE = 0x2, 3881 }; 3882 3883 struct mlx5_ifc_rqc_bits { 3884 u8 rlky[0x1]; 3885 u8 delay_drop_en[0x1]; 3886 u8 scatter_fcs[0x1]; 3887 u8 vsd[0x1]; 3888 u8 mem_rq_type[0x4]; 3889 u8 state[0x4]; 3890 u8 reserved_at_c[0x1]; 3891 u8 flush_in_error_en[0x1]; 3892 u8 hairpin[0x1]; 3893 u8 reserved_at_f[0xb]; 3894 u8 ts_format[0x2]; 3895 u8 reserved_at_1c[0x4]; 3896 3897 u8 reserved_at_20[0x8]; 3898 u8 user_index[0x18]; 3899 3900 u8 reserved_at_40[0x8]; 3901 u8 cqn[0x18]; 3902 3903 u8 counter_set_id[0x8]; 3904 u8 reserved_at_68[0x18]; 3905 3906 u8 reserved_at_80[0x8]; 3907 u8 rmpn[0x18]; 3908 3909 u8 reserved_at_a0[0x8]; 3910 u8 hairpin_peer_sq[0x18]; 3911 3912 u8 reserved_at_c0[0x10]; 3913 u8 hairpin_peer_vhca[0x10]; 3914 3915 u8 reserved_at_e0[0x46]; 3916 u8 shampo_no_match_alignment_granularity[0x2]; 3917 u8 reserved_at_128[0x6]; 3918 u8 shampo_match_criteria_type[0x2]; 3919 u8 reservation_timeout[0x10]; 3920 3921 u8 reserved_at_140[0x40]; 3922 3923 struct mlx5_ifc_wq_bits wq; 3924 }; 3925 3926 enum { 3927 MLX5_RMPC_STATE_RDY = 0x1, 3928 MLX5_RMPC_STATE_ERR = 0x3, 3929 }; 3930 3931 struct mlx5_ifc_rmpc_bits { 3932 u8 reserved_at_0[0x8]; 3933 u8 state[0x4]; 3934 u8 reserved_at_c[0x14]; 3935 3936 u8 basic_cyclic_rcv_wqe[0x1]; 3937 u8 reserved_at_21[0x1f]; 3938 3939 u8 reserved_at_40[0x140]; 3940 3941 struct mlx5_ifc_wq_bits wq; 3942 }; 3943 3944 enum { 3945 VHCA_ID_TYPE_HW = 0, 3946 VHCA_ID_TYPE_SW = 1, 3947 }; 3948 3949 struct mlx5_ifc_nic_vport_context_bits { 3950 u8 reserved_at_0[0x5]; 3951 u8 min_wqe_inline_mode[0x3]; 3952 u8 reserved_at_8[0x15]; 3953 u8 disable_mc_local_lb[0x1]; 3954 u8 disable_uc_local_lb[0x1]; 3955 u8 roce_en[0x1]; 3956 3957 u8 arm_change_event[0x1]; 3958 u8 reserved_at_21[0x1a]; 3959 u8 event_on_mtu[0x1]; 3960 u8 event_on_promisc_change[0x1]; 3961 u8 event_on_vlan_change[0x1]; 3962 u8 event_on_mc_address_change[0x1]; 3963 u8 event_on_uc_address_change[0x1]; 3964 3965 u8 vhca_id_type[0x1]; 3966 u8 reserved_at_41[0xb]; 3967 u8 affiliation_criteria[0x4]; 3968 u8 affiliated_vhca_id[0x10]; 3969 3970 u8 reserved_at_60[0xd0]; 3971 3972 u8 mtu[0x10]; 3973 3974 u8 system_image_guid[0x40]; 3975 u8 port_guid[0x40]; 3976 u8 node_guid[0x40]; 3977 3978 u8 reserved_at_200[0x140]; 3979 u8 qkey_violation_counter[0x10]; 3980 u8 reserved_at_350[0x430]; 3981 3982 u8 promisc_uc[0x1]; 3983 u8 promisc_mc[0x1]; 3984 u8 promisc_all[0x1]; 3985 u8 reserved_at_783[0x2]; 3986 u8 allowed_list_type[0x3]; 3987 u8 reserved_at_788[0xc]; 3988 u8 allowed_list_size[0xc]; 3989 3990 struct mlx5_ifc_mac_address_layout_bits permanent_address; 3991 3992 u8 reserved_at_7e0[0x20]; 3993 3994 u8 current_uc_mac_address[][0x40]; 3995 }; 3996 3997 enum { 3998 MLX5_MKC_ACCESS_MODE_PA = 0x0, 3999 MLX5_MKC_ACCESS_MODE_MTT = 0x1, 4000 MLX5_MKC_ACCESS_MODE_KLMS = 0x2, 4001 MLX5_MKC_ACCESS_MODE_KSM = 0x3, 4002 MLX5_MKC_ACCESS_MODE_SW_ICM = 0x4, 4003 MLX5_MKC_ACCESS_MODE_MEMIC = 0x5, 4004 }; 4005 4006 struct mlx5_ifc_mkc_bits { 4007 u8 reserved_at_0[0x1]; 4008 u8 free[0x1]; 4009 u8 reserved_at_2[0x1]; 4010 u8 access_mode_4_2[0x3]; 4011 u8 reserved_at_6[0x7]; 4012 u8 relaxed_ordering_write[0x1]; 4013 u8 reserved_at_e[0x1]; 4014 u8 small_fence_on_rdma_read_response[0x1]; 4015 u8 umr_en[0x1]; 4016 u8 a[0x1]; 4017 u8 rw[0x1]; 4018 u8 rr[0x1]; 4019 u8 lw[0x1]; 4020 u8 lr[0x1]; 4021 u8 access_mode_1_0[0x2]; 4022 u8 reserved_at_18[0x2]; 4023 u8 ma_translation_mode[0x2]; 4024 u8 reserved_at_1c[0x4]; 4025 4026 u8 qpn[0x18]; 4027 u8 mkey_7_0[0x8]; 4028 4029 u8 reserved_at_40[0x20]; 4030 4031 u8 length64[0x1]; 4032 u8 bsf_en[0x1]; 4033 u8 sync_umr[0x1]; 4034 u8 reserved_at_63[0x2]; 4035 u8 expected_sigerr_count[0x1]; 4036 u8 reserved_at_66[0x1]; 4037 u8 en_rinval[0x1]; 4038 u8 pd[0x18]; 4039 4040 u8 start_addr[0x40]; 4041 4042 u8 len[0x40]; 4043 4044 u8 bsf_octword_size[0x20]; 4045 4046 u8 reserved_at_120[0x80]; 4047 4048 u8 translations_octword_size[0x20]; 4049 4050 u8 reserved_at_1c0[0x19]; 4051 u8 relaxed_ordering_read[0x1]; 4052 u8 reserved_at_1d9[0x1]; 4053 u8 log_page_size[0x5]; 4054 4055 u8 reserved_at_1e0[0x20]; 4056 }; 4057 4058 struct mlx5_ifc_pkey_bits { 4059 u8 reserved_at_0[0x10]; 4060 u8 pkey[0x10]; 4061 }; 4062 4063 struct mlx5_ifc_array128_auto_bits { 4064 u8 array128_auto[16][0x8]; 4065 }; 4066 4067 struct mlx5_ifc_hca_vport_context_bits { 4068 u8 field_select[0x20]; 4069 4070 u8 reserved_at_20[0xe0]; 4071 4072 u8 sm_virt_aware[0x1]; 4073 u8 has_smi[0x1]; 4074 u8 has_raw[0x1]; 4075 u8 grh_required[0x1]; 4076 u8 reserved_at_104[0xc]; 4077 u8 port_physical_state[0x4]; 4078 u8 vport_state_policy[0x4]; 4079 u8 port_state[0x4]; 4080 u8 vport_state[0x4]; 4081 4082 u8 reserved_at_120[0x20]; 4083 4084 u8 system_image_guid[0x40]; 4085 4086 u8 port_guid[0x40]; 4087 4088 u8 node_guid[0x40]; 4089 4090 u8 cap_mask1[0x20]; 4091 4092 u8 cap_mask1_field_select[0x20]; 4093 4094 u8 cap_mask2[0x20]; 4095 4096 u8 cap_mask2_field_select[0x20]; 4097 4098 u8 reserved_at_280[0x80]; 4099 4100 u8 lid[0x10]; 4101 u8 reserved_at_310[0x4]; 4102 u8 init_type_reply[0x4]; 4103 u8 lmc[0x3]; 4104 u8 subnet_timeout[0x5]; 4105 4106 u8 sm_lid[0x10]; 4107 u8 sm_sl[0x4]; 4108 u8 reserved_at_334[0xc]; 4109 4110 u8 qkey_violation_counter[0x10]; 4111 u8 pkey_violation_counter[0x10]; 4112 4113 u8 reserved_at_360[0xca0]; 4114 }; 4115 4116 struct mlx5_ifc_esw_vport_context_bits { 4117 u8 fdb_to_vport_reg_c[0x1]; 4118 u8 reserved_at_1[0x2]; 4119 u8 vport_svlan_strip[0x1]; 4120 u8 vport_cvlan_strip[0x1]; 4121 u8 vport_svlan_insert[0x1]; 4122 u8 vport_cvlan_insert[0x2]; 4123 u8 fdb_to_vport_reg_c_id[0x8]; 4124 u8 reserved_at_10[0x10]; 4125 4126 u8 reserved_at_20[0x20]; 4127 4128 u8 svlan_cfi[0x1]; 4129 u8 svlan_pcp[0x3]; 4130 u8 svlan_id[0xc]; 4131 u8 cvlan_cfi[0x1]; 4132 u8 cvlan_pcp[0x3]; 4133 u8 cvlan_id[0xc]; 4134 4135 u8 reserved_at_60[0x720]; 4136 4137 u8 sw_steering_vport_icm_address_rx[0x40]; 4138 4139 u8 sw_steering_vport_icm_address_tx[0x40]; 4140 }; 4141 4142 enum { 4143 MLX5_EQC_STATUS_OK = 0x0, 4144 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa, 4145 }; 4146 4147 enum { 4148 MLX5_EQC_ST_ARMED = 0x9, 4149 MLX5_EQC_ST_FIRED = 0xa, 4150 }; 4151 4152 struct mlx5_ifc_eqc_bits { 4153 u8 status[0x4]; 4154 u8 reserved_at_4[0x9]; 4155 u8 ec[0x1]; 4156 u8 oi[0x1]; 4157 u8 reserved_at_f[0x5]; 4158 u8 st[0x4]; 4159 u8 reserved_at_18[0x8]; 4160 4161 u8 reserved_at_20[0x20]; 4162 4163 u8 reserved_at_40[0x14]; 4164 u8 page_offset[0x6]; 4165 u8 reserved_at_5a[0x6]; 4166 4167 u8 reserved_at_60[0x3]; 4168 u8 log_eq_size[0x5]; 4169 u8 uar_page[0x18]; 4170 4171 u8 reserved_at_80[0x20]; 4172 4173 u8 reserved_at_a0[0x14]; 4174 u8 intr[0xc]; 4175 4176 u8 reserved_at_c0[0x3]; 4177 u8 log_page_size[0x5]; 4178 u8 reserved_at_c8[0x18]; 4179 4180 u8 reserved_at_e0[0x60]; 4181 4182 u8 reserved_at_140[0x8]; 4183 u8 consumer_counter[0x18]; 4184 4185 u8 reserved_at_160[0x8]; 4186 u8 producer_counter[0x18]; 4187 4188 u8 reserved_at_180[0x80]; 4189 }; 4190 4191 enum { 4192 MLX5_DCTC_STATE_ACTIVE = 0x0, 4193 MLX5_DCTC_STATE_DRAINING = 0x1, 4194 MLX5_DCTC_STATE_DRAINED = 0x2, 4195 }; 4196 4197 enum { 4198 MLX5_DCTC_CS_RES_DISABLE = 0x0, 4199 MLX5_DCTC_CS_RES_NA = 0x1, 4200 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2, 4201 }; 4202 4203 enum { 4204 MLX5_DCTC_MTU_256_BYTES = 0x1, 4205 MLX5_DCTC_MTU_512_BYTES = 0x2, 4206 MLX5_DCTC_MTU_1K_BYTES = 0x3, 4207 MLX5_DCTC_MTU_2K_BYTES = 0x4, 4208 MLX5_DCTC_MTU_4K_BYTES = 0x5, 4209 }; 4210 4211 struct mlx5_ifc_dctc_bits { 4212 u8 reserved_at_0[0x4]; 4213 u8 state[0x4]; 4214 u8 reserved_at_8[0x18]; 4215 4216 u8 reserved_at_20[0x8]; 4217 u8 user_index[0x18]; 4218 4219 u8 reserved_at_40[0x8]; 4220 u8 cqn[0x18]; 4221 4222 u8 counter_set_id[0x8]; 4223 u8 atomic_mode[0x4]; 4224 u8 rre[0x1]; 4225 u8 rwe[0x1]; 4226 u8 rae[0x1]; 4227 u8 atomic_like_write_en[0x1]; 4228 u8 latency_sensitive[0x1]; 4229 u8 rlky[0x1]; 4230 u8 free_ar[0x1]; 4231 u8 reserved_at_73[0xd]; 4232 4233 u8 reserved_at_80[0x8]; 4234 u8 cs_res[0x8]; 4235 u8 reserved_at_90[0x3]; 4236 u8 min_rnr_nak[0x5]; 4237 u8 reserved_at_98[0x8]; 4238 4239 u8 reserved_at_a0[0x8]; 4240 u8 srqn_xrqn[0x18]; 4241 4242 u8 reserved_at_c0[0x8]; 4243 u8 pd[0x18]; 4244 4245 u8 tclass[0x8]; 4246 u8 reserved_at_e8[0x4]; 4247 u8 flow_label[0x14]; 4248 4249 u8 dc_access_key[0x40]; 4250 4251 u8 reserved_at_140[0x5]; 4252 u8 mtu[0x3]; 4253 u8 port[0x8]; 4254 u8 pkey_index[0x10]; 4255 4256 u8 reserved_at_160[0x8]; 4257 u8 my_addr_index[0x8]; 4258 u8 reserved_at_170[0x8]; 4259 u8 hop_limit[0x8]; 4260 4261 u8 dc_access_key_violation_count[0x20]; 4262 4263 u8 reserved_at_1a0[0x14]; 4264 u8 dei_cfi[0x1]; 4265 u8 eth_prio[0x3]; 4266 u8 ecn[0x2]; 4267 u8 dscp[0x6]; 4268 4269 u8 reserved_at_1c0[0x20]; 4270 u8 ece[0x20]; 4271 }; 4272 4273 enum { 4274 MLX5_CQC_STATUS_OK = 0x0, 4275 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9, 4276 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa, 4277 }; 4278 4279 enum { 4280 MLX5_CQC_CQE_SZ_64_BYTES = 0x0, 4281 MLX5_CQC_CQE_SZ_128_BYTES = 0x1, 4282 }; 4283 4284 enum { 4285 MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED = 0x6, 4286 MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED = 0x9, 4287 MLX5_CQC_ST_FIRED = 0xa, 4288 }; 4289 4290 enum { 4291 MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0, 4292 MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1, 4293 MLX5_CQ_PERIOD_NUM_MODES 4294 }; 4295 4296 struct mlx5_ifc_cqc_bits { 4297 u8 status[0x4]; 4298 u8 reserved_at_4[0x2]; 4299 u8 dbr_umem_valid[0x1]; 4300 u8 apu_cq[0x1]; 4301 u8 cqe_sz[0x3]; 4302 u8 cc[0x1]; 4303 u8 reserved_at_c[0x1]; 4304 u8 scqe_break_moderation_en[0x1]; 4305 u8 oi[0x1]; 4306 u8 cq_period_mode[0x2]; 4307 u8 cqe_comp_en[0x1]; 4308 u8 mini_cqe_res_format[0x2]; 4309 u8 st[0x4]; 4310 u8 reserved_at_18[0x6]; 4311 u8 cqe_compression_layout[0x2]; 4312 4313 u8 reserved_at_20[0x20]; 4314 4315 u8 reserved_at_40[0x14]; 4316 u8 page_offset[0x6]; 4317 u8 reserved_at_5a[0x6]; 4318 4319 u8 reserved_at_60[0x3]; 4320 u8 log_cq_size[0x5]; 4321 u8 uar_page[0x18]; 4322 4323 u8 reserved_at_80[0x4]; 4324 u8 cq_period[0xc]; 4325 u8 cq_max_count[0x10]; 4326 4327 u8 c_eqn_or_apu_element[0x20]; 4328 4329 u8 reserved_at_c0[0x3]; 4330 u8 log_page_size[0x5]; 4331 u8 reserved_at_c8[0x18]; 4332 4333 u8 reserved_at_e0[0x20]; 4334 4335 u8 reserved_at_100[0x8]; 4336 u8 last_notified_index[0x18]; 4337 4338 u8 reserved_at_120[0x8]; 4339 u8 last_solicit_index[0x18]; 4340 4341 u8 reserved_at_140[0x8]; 4342 u8 consumer_counter[0x18]; 4343 4344 u8 reserved_at_160[0x8]; 4345 u8 producer_counter[0x18]; 4346 4347 u8 reserved_at_180[0x40]; 4348 4349 u8 dbr_addr[0x40]; 4350 }; 4351 4352 union mlx5_ifc_cong_control_roce_ecn_auto_bits { 4353 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp; 4354 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp; 4355 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np; 4356 u8 reserved_at_0[0x800]; 4357 }; 4358 4359 struct mlx5_ifc_query_adapter_param_block_bits { 4360 u8 reserved_at_0[0xc0]; 4361 4362 u8 reserved_at_c0[0x8]; 4363 u8 ieee_vendor_id[0x18]; 4364 4365 u8 reserved_at_e0[0x10]; 4366 u8 vsd_vendor_id[0x10]; 4367 4368 u8 vsd[208][0x8]; 4369 4370 u8 vsd_contd_psid[16][0x8]; 4371 }; 4372 4373 enum { 4374 MLX5_XRQC_STATE_GOOD = 0x0, 4375 MLX5_XRQC_STATE_ERROR = 0x1, 4376 }; 4377 4378 enum { 4379 MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0, 4380 MLX5_XRQC_TOPOLOGY_TAG_MATCHING = 0x1, 4381 }; 4382 4383 enum { 4384 MLX5_XRQC_OFFLOAD_RNDV = 0x1, 4385 }; 4386 4387 struct mlx5_ifc_tag_matching_topology_context_bits { 4388 u8 log_matching_list_sz[0x4]; 4389 u8 reserved_at_4[0xc]; 4390 u8 append_next_index[0x10]; 4391 4392 u8 sw_phase_cnt[0x10]; 4393 u8 hw_phase_cnt[0x10]; 4394 4395 u8 reserved_at_40[0x40]; 4396 }; 4397 4398 struct mlx5_ifc_xrqc_bits { 4399 u8 state[0x4]; 4400 u8 rlkey[0x1]; 4401 u8 reserved_at_5[0xf]; 4402 u8 topology[0x4]; 4403 u8 reserved_at_18[0x4]; 4404 u8 offload[0x4]; 4405 4406 u8 reserved_at_20[0x8]; 4407 u8 user_index[0x18]; 4408 4409 u8 reserved_at_40[0x8]; 4410 u8 cqn[0x18]; 4411 4412 u8 reserved_at_60[0xa0]; 4413 4414 struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context; 4415 4416 u8 reserved_at_180[0x280]; 4417 4418 struct mlx5_ifc_wq_bits wq; 4419 }; 4420 4421 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits { 4422 struct mlx5_ifc_modify_field_select_bits modify_field_select; 4423 struct mlx5_ifc_resize_field_select_bits resize_field_select; 4424 u8 reserved_at_0[0x20]; 4425 }; 4426 4427 union mlx5_ifc_field_select_802_1_r_roce_auto_bits { 4428 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp; 4429 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp; 4430 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np; 4431 u8 reserved_at_0[0x20]; 4432 }; 4433 4434 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits { 4435 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 4436 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 4437 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 4438 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 4439 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 4440 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 4441 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout; 4442 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout; 4443 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 4444 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 4445 struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs; 4446 u8 reserved_at_0[0x7c0]; 4447 }; 4448 4449 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits { 4450 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout; 4451 u8 reserved_at_0[0x7c0]; 4452 }; 4453 4454 union mlx5_ifc_event_auto_bits { 4455 struct mlx5_ifc_comp_event_bits comp_event; 4456 struct mlx5_ifc_dct_events_bits dct_events; 4457 struct mlx5_ifc_qp_events_bits qp_events; 4458 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event; 4459 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event; 4460 struct mlx5_ifc_cq_error_bits cq_error; 4461 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged; 4462 struct mlx5_ifc_port_state_change_event_bits port_state_change_event; 4463 struct mlx5_ifc_gpio_event_bits gpio_event; 4464 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event; 4465 struct mlx5_ifc_stall_vl_event_bits stall_vl_event; 4466 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event; 4467 u8 reserved_at_0[0xe0]; 4468 }; 4469 4470 struct mlx5_ifc_health_buffer_bits { 4471 u8 reserved_at_0[0x100]; 4472 4473 u8 assert_existptr[0x20]; 4474 4475 u8 assert_callra[0x20]; 4476 4477 u8 reserved_at_140[0x20]; 4478 4479 u8 time[0x20]; 4480 4481 u8 fw_version[0x20]; 4482 4483 u8 hw_id[0x20]; 4484 4485 u8 rfr[0x1]; 4486 u8 reserved_at_1c1[0x3]; 4487 u8 valid[0x1]; 4488 u8 severity[0x3]; 4489 u8 reserved_at_1c8[0x18]; 4490 4491 u8 irisc_index[0x8]; 4492 u8 synd[0x8]; 4493 u8 ext_synd[0x10]; 4494 }; 4495 4496 struct mlx5_ifc_register_loopback_control_bits { 4497 u8 no_lb[0x1]; 4498 u8 reserved_at_1[0x7]; 4499 u8 port[0x8]; 4500 u8 reserved_at_10[0x10]; 4501 4502 u8 reserved_at_20[0x60]; 4503 }; 4504 4505 struct mlx5_ifc_vport_tc_element_bits { 4506 u8 traffic_class[0x4]; 4507 u8 reserved_at_4[0xc]; 4508 u8 vport_number[0x10]; 4509 }; 4510 4511 struct mlx5_ifc_vport_element_bits { 4512 u8 reserved_at_0[0x10]; 4513 u8 vport_number[0x10]; 4514 }; 4515 4516 enum { 4517 TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0, 4518 TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1, 4519 TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2, 4520 }; 4521 4522 struct mlx5_ifc_tsar_element_bits { 4523 u8 reserved_at_0[0x8]; 4524 u8 tsar_type[0x8]; 4525 u8 reserved_at_10[0x10]; 4526 }; 4527 4528 enum { 4529 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0, 4530 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1, 4531 }; 4532 4533 struct mlx5_ifc_teardown_hca_out_bits { 4534 u8 status[0x8]; 4535 u8 reserved_at_8[0x18]; 4536 4537 u8 syndrome[0x20]; 4538 4539 u8 reserved_at_40[0x3f]; 4540 4541 u8 state[0x1]; 4542 }; 4543 4544 enum { 4545 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0, 4546 MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE = 0x1, 4547 MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN = 0x2, 4548 }; 4549 4550 struct mlx5_ifc_teardown_hca_in_bits { 4551 u8 opcode[0x10]; 4552 u8 reserved_at_10[0x10]; 4553 4554 u8 reserved_at_20[0x10]; 4555 u8 op_mod[0x10]; 4556 4557 u8 reserved_at_40[0x10]; 4558 u8 profile[0x10]; 4559 4560 u8 reserved_at_60[0x20]; 4561 }; 4562 4563 struct mlx5_ifc_sqerr2rts_qp_out_bits { 4564 u8 status[0x8]; 4565 u8 reserved_at_8[0x18]; 4566 4567 u8 syndrome[0x20]; 4568 4569 u8 reserved_at_40[0x40]; 4570 }; 4571 4572 struct mlx5_ifc_sqerr2rts_qp_in_bits { 4573 u8 opcode[0x10]; 4574 u8 uid[0x10]; 4575 4576 u8 reserved_at_20[0x10]; 4577 u8 op_mod[0x10]; 4578 4579 u8 reserved_at_40[0x8]; 4580 u8 qpn[0x18]; 4581 4582 u8 reserved_at_60[0x20]; 4583 4584 u8 opt_param_mask[0x20]; 4585 4586 u8 reserved_at_a0[0x20]; 4587 4588 struct mlx5_ifc_qpc_bits qpc; 4589 4590 u8 reserved_at_800[0x80]; 4591 }; 4592 4593 struct mlx5_ifc_sqd2rts_qp_out_bits { 4594 u8 status[0x8]; 4595 u8 reserved_at_8[0x18]; 4596 4597 u8 syndrome[0x20]; 4598 4599 u8 reserved_at_40[0x40]; 4600 }; 4601 4602 struct mlx5_ifc_sqd2rts_qp_in_bits { 4603 u8 opcode[0x10]; 4604 u8 uid[0x10]; 4605 4606 u8 reserved_at_20[0x10]; 4607 u8 op_mod[0x10]; 4608 4609 u8 reserved_at_40[0x8]; 4610 u8 qpn[0x18]; 4611 4612 u8 reserved_at_60[0x20]; 4613 4614 u8 opt_param_mask[0x20]; 4615 4616 u8 reserved_at_a0[0x20]; 4617 4618 struct mlx5_ifc_qpc_bits qpc; 4619 4620 u8 reserved_at_800[0x80]; 4621 }; 4622 4623 struct mlx5_ifc_set_roce_address_out_bits { 4624 u8 status[0x8]; 4625 u8 reserved_at_8[0x18]; 4626 4627 u8 syndrome[0x20]; 4628 4629 u8 reserved_at_40[0x40]; 4630 }; 4631 4632 struct mlx5_ifc_set_roce_address_in_bits { 4633 u8 opcode[0x10]; 4634 u8 reserved_at_10[0x10]; 4635 4636 u8 reserved_at_20[0x10]; 4637 u8 op_mod[0x10]; 4638 4639 u8 roce_address_index[0x10]; 4640 u8 reserved_at_50[0xc]; 4641 u8 vhca_port_num[0x4]; 4642 4643 u8 reserved_at_60[0x20]; 4644 4645 struct mlx5_ifc_roce_addr_layout_bits roce_address; 4646 }; 4647 4648 struct mlx5_ifc_set_mad_demux_out_bits { 4649 u8 status[0x8]; 4650 u8 reserved_at_8[0x18]; 4651 4652 u8 syndrome[0x20]; 4653 4654 u8 reserved_at_40[0x40]; 4655 }; 4656 4657 enum { 4658 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0, 4659 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2, 4660 }; 4661 4662 struct mlx5_ifc_set_mad_demux_in_bits { 4663 u8 opcode[0x10]; 4664 u8 reserved_at_10[0x10]; 4665 4666 u8 reserved_at_20[0x10]; 4667 u8 op_mod[0x10]; 4668 4669 u8 reserved_at_40[0x20]; 4670 4671 u8 reserved_at_60[0x6]; 4672 u8 demux_mode[0x2]; 4673 u8 reserved_at_68[0x18]; 4674 }; 4675 4676 struct mlx5_ifc_set_l2_table_entry_out_bits { 4677 u8 status[0x8]; 4678 u8 reserved_at_8[0x18]; 4679 4680 u8 syndrome[0x20]; 4681 4682 u8 reserved_at_40[0x40]; 4683 }; 4684 4685 struct mlx5_ifc_set_l2_table_entry_in_bits { 4686 u8 opcode[0x10]; 4687 u8 reserved_at_10[0x10]; 4688 4689 u8 reserved_at_20[0x10]; 4690 u8 op_mod[0x10]; 4691 4692 u8 reserved_at_40[0x60]; 4693 4694 u8 reserved_at_a0[0x8]; 4695 u8 table_index[0x18]; 4696 4697 u8 reserved_at_c0[0x20]; 4698 4699 u8 reserved_at_e0[0x13]; 4700 u8 vlan_valid[0x1]; 4701 u8 vlan[0xc]; 4702 4703 struct mlx5_ifc_mac_address_layout_bits mac_address; 4704 4705 u8 reserved_at_140[0xc0]; 4706 }; 4707 4708 struct mlx5_ifc_set_issi_out_bits { 4709 u8 status[0x8]; 4710 u8 reserved_at_8[0x18]; 4711 4712 u8 syndrome[0x20]; 4713 4714 u8 reserved_at_40[0x40]; 4715 }; 4716 4717 struct mlx5_ifc_set_issi_in_bits { 4718 u8 opcode[0x10]; 4719 u8 reserved_at_10[0x10]; 4720 4721 u8 reserved_at_20[0x10]; 4722 u8 op_mod[0x10]; 4723 4724 u8 reserved_at_40[0x10]; 4725 u8 current_issi[0x10]; 4726 4727 u8 reserved_at_60[0x20]; 4728 }; 4729 4730 struct mlx5_ifc_set_hca_cap_out_bits { 4731 u8 status[0x8]; 4732 u8 reserved_at_8[0x18]; 4733 4734 u8 syndrome[0x20]; 4735 4736 u8 reserved_at_40[0x40]; 4737 }; 4738 4739 struct mlx5_ifc_set_hca_cap_in_bits { 4740 u8 opcode[0x10]; 4741 u8 reserved_at_10[0x10]; 4742 4743 u8 reserved_at_20[0x10]; 4744 u8 op_mod[0x10]; 4745 4746 u8 other_function[0x1]; 4747 u8 reserved_at_41[0xf]; 4748 u8 function_id[0x10]; 4749 4750 u8 reserved_at_60[0x20]; 4751 4752 union mlx5_ifc_hca_cap_union_bits capability; 4753 }; 4754 4755 enum { 4756 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0, 4757 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1, 4758 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2, 4759 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3, 4760 MLX5_SET_FTE_MODIFY_ENABLE_MASK_IPSEC_OBJ_ID = 0x4 4761 }; 4762 4763 struct mlx5_ifc_set_fte_out_bits { 4764 u8 status[0x8]; 4765 u8 reserved_at_8[0x18]; 4766 4767 u8 syndrome[0x20]; 4768 4769 u8 reserved_at_40[0x40]; 4770 }; 4771 4772 struct mlx5_ifc_set_fte_in_bits { 4773 u8 opcode[0x10]; 4774 u8 reserved_at_10[0x10]; 4775 4776 u8 reserved_at_20[0x10]; 4777 u8 op_mod[0x10]; 4778 4779 u8 other_vport[0x1]; 4780 u8 reserved_at_41[0xf]; 4781 u8 vport_number[0x10]; 4782 4783 u8 reserved_at_60[0x20]; 4784 4785 u8 table_type[0x8]; 4786 u8 reserved_at_88[0x18]; 4787 4788 u8 reserved_at_a0[0x8]; 4789 u8 table_id[0x18]; 4790 4791 u8 ignore_flow_level[0x1]; 4792 u8 reserved_at_c1[0x17]; 4793 u8 modify_enable_mask[0x8]; 4794 4795 u8 reserved_at_e0[0x20]; 4796 4797 u8 flow_index[0x20]; 4798 4799 u8 reserved_at_120[0xe0]; 4800 4801 struct mlx5_ifc_flow_context_bits flow_context; 4802 }; 4803 4804 struct mlx5_ifc_rts2rts_qp_out_bits { 4805 u8 status[0x8]; 4806 u8 reserved_at_8[0x18]; 4807 4808 u8 syndrome[0x20]; 4809 4810 u8 reserved_at_40[0x20]; 4811 u8 ece[0x20]; 4812 }; 4813 4814 struct mlx5_ifc_rts2rts_qp_in_bits { 4815 u8 opcode[0x10]; 4816 u8 uid[0x10]; 4817 4818 u8 reserved_at_20[0x10]; 4819 u8 op_mod[0x10]; 4820 4821 u8 reserved_at_40[0x8]; 4822 u8 qpn[0x18]; 4823 4824 u8 reserved_at_60[0x20]; 4825 4826 u8 opt_param_mask[0x20]; 4827 4828 u8 ece[0x20]; 4829 4830 struct mlx5_ifc_qpc_bits qpc; 4831 4832 u8 reserved_at_800[0x80]; 4833 }; 4834 4835 struct mlx5_ifc_rtr2rts_qp_out_bits { 4836 u8 status[0x8]; 4837 u8 reserved_at_8[0x18]; 4838 4839 u8 syndrome[0x20]; 4840 4841 u8 reserved_at_40[0x20]; 4842 u8 ece[0x20]; 4843 }; 4844 4845 struct mlx5_ifc_rtr2rts_qp_in_bits { 4846 u8 opcode[0x10]; 4847 u8 uid[0x10]; 4848 4849 u8 reserved_at_20[0x10]; 4850 u8 op_mod[0x10]; 4851 4852 u8 reserved_at_40[0x8]; 4853 u8 qpn[0x18]; 4854 4855 u8 reserved_at_60[0x20]; 4856 4857 u8 opt_param_mask[0x20]; 4858 4859 u8 ece[0x20]; 4860 4861 struct mlx5_ifc_qpc_bits qpc; 4862 4863 u8 reserved_at_800[0x80]; 4864 }; 4865 4866 struct mlx5_ifc_rst2init_qp_out_bits { 4867 u8 status[0x8]; 4868 u8 reserved_at_8[0x18]; 4869 4870 u8 syndrome[0x20]; 4871 4872 u8 reserved_at_40[0x20]; 4873 u8 ece[0x20]; 4874 }; 4875 4876 struct mlx5_ifc_rst2init_qp_in_bits { 4877 u8 opcode[0x10]; 4878 u8 uid[0x10]; 4879 4880 u8 reserved_at_20[0x10]; 4881 u8 op_mod[0x10]; 4882 4883 u8 reserved_at_40[0x8]; 4884 u8 qpn[0x18]; 4885 4886 u8 reserved_at_60[0x20]; 4887 4888 u8 opt_param_mask[0x20]; 4889 4890 u8 ece[0x20]; 4891 4892 struct mlx5_ifc_qpc_bits qpc; 4893 4894 u8 reserved_at_800[0x80]; 4895 }; 4896 4897 struct mlx5_ifc_query_xrq_out_bits { 4898 u8 status[0x8]; 4899 u8 reserved_at_8[0x18]; 4900 4901 u8 syndrome[0x20]; 4902 4903 u8 reserved_at_40[0x40]; 4904 4905 struct mlx5_ifc_xrqc_bits xrq_context; 4906 }; 4907 4908 struct mlx5_ifc_query_xrq_in_bits { 4909 u8 opcode[0x10]; 4910 u8 reserved_at_10[0x10]; 4911 4912 u8 reserved_at_20[0x10]; 4913 u8 op_mod[0x10]; 4914 4915 u8 reserved_at_40[0x8]; 4916 u8 xrqn[0x18]; 4917 4918 u8 reserved_at_60[0x20]; 4919 }; 4920 4921 struct mlx5_ifc_query_xrc_srq_out_bits { 4922 u8 status[0x8]; 4923 u8 reserved_at_8[0x18]; 4924 4925 u8 syndrome[0x20]; 4926 4927 u8 reserved_at_40[0x40]; 4928 4929 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 4930 4931 u8 reserved_at_280[0x600]; 4932 4933 u8 pas[][0x40]; 4934 }; 4935 4936 struct mlx5_ifc_query_xrc_srq_in_bits { 4937 u8 opcode[0x10]; 4938 u8 reserved_at_10[0x10]; 4939 4940 u8 reserved_at_20[0x10]; 4941 u8 op_mod[0x10]; 4942 4943 u8 reserved_at_40[0x8]; 4944 u8 xrc_srqn[0x18]; 4945 4946 u8 reserved_at_60[0x20]; 4947 }; 4948 4949 enum { 4950 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0, 4951 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1, 4952 }; 4953 4954 struct mlx5_ifc_query_vport_state_out_bits { 4955 u8 status[0x8]; 4956 u8 reserved_at_8[0x18]; 4957 4958 u8 syndrome[0x20]; 4959 4960 u8 reserved_at_40[0x20]; 4961 4962 u8 reserved_at_60[0x18]; 4963 u8 admin_state[0x4]; 4964 u8 state[0x4]; 4965 }; 4966 4967 enum { 4968 MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT = 0x0, 4969 MLX5_VPORT_STATE_OP_MOD_ESW_VPORT = 0x1, 4970 MLX5_VPORT_STATE_OP_MOD_UPLINK = 0x2, 4971 }; 4972 4973 struct mlx5_ifc_arm_monitor_counter_in_bits { 4974 u8 opcode[0x10]; 4975 u8 uid[0x10]; 4976 4977 u8 reserved_at_20[0x10]; 4978 u8 op_mod[0x10]; 4979 4980 u8 reserved_at_40[0x20]; 4981 4982 u8 reserved_at_60[0x20]; 4983 }; 4984 4985 struct mlx5_ifc_arm_monitor_counter_out_bits { 4986 u8 status[0x8]; 4987 u8 reserved_at_8[0x18]; 4988 4989 u8 syndrome[0x20]; 4990 4991 u8 reserved_at_40[0x40]; 4992 }; 4993 4994 enum { 4995 MLX5_QUERY_MONITOR_CNT_TYPE_PPCNT = 0x0, 4996 MLX5_QUERY_MONITOR_CNT_TYPE_Q_COUNTER = 0x1, 4997 }; 4998 4999 enum mlx5_monitor_counter_ppcnt { 5000 MLX5_QUERY_MONITOR_PPCNT_IN_RANGE_LENGTH_ERRORS = 0x0, 5001 MLX5_QUERY_MONITOR_PPCNT_OUT_OF_RANGE_LENGTH_FIELD = 0x1, 5002 MLX5_QUERY_MONITOR_PPCNT_FRAME_TOO_LONG_ERRORS = 0x2, 5003 MLX5_QUERY_MONITOR_PPCNT_FRAME_CHECK_SEQUENCE_ERRORS = 0x3, 5004 MLX5_QUERY_MONITOR_PPCNT_ALIGNMENT_ERRORS = 0x4, 5005 MLX5_QUERY_MONITOR_PPCNT_IF_OUT_DISCARDS = 0x5, 5006 }; 5007 5008 enum { 5009 MLX5_QUERY_MONITOR_Q_COUNTER_RX_OUT_OF_BUFFER = 0x4, 5010 }; 5011 5012 struct mlx5_ifc_monitor_counter_output_bits { 5013 u8 reserved_at_0[0x4]; 5014 u8 type[0x4]; 5015 u8 reserved_at_8[0x8]; 5016 u8 counter[0x10]; 5017 5018 u8 counter_group_id[0x20]; 5019 }; 5020 5021 #define MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 (6) 5022 #define MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1 (1) 5023 #define MLX5_CMD_SET_MONITOR_NUM_COUNTER (MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 +\ 5024 MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1) 5025 5026 struct mlx5_ifc_set_monitor_counter_in_bits { 5027 u8 opcode[0x10]; 5028 u8 uid[0x10]; 5029 5030 u8 reserved_at_20[0x10]; 5031 u8 op_mod[0x10]; 5032 5033 u8 reserved_at_40[0x10]; 5034 u8 num_of_counters[0x10]; 5035 5036 u8 reserved_at_60[0x20]; 5037 5038 struct mlx5_ifc_monitor_counter_output_bits monitor_counter[MLX5_CMD_SET_MONITOR_NUM_COUNTER]; 5039 }; 5040 5041 struct mlx5_ifc_set_monitor_counter_out_bits { 5042 u8 status[0x8]; 5043 u8 reserved_at_8[0x18]; 5044 5045 u8 syndrome[0x20]; 5046 5047 u8 reserved_at_40[0x40]; 5048 }; 5049 5050 struct mlx5_ifc_query_vport_state_in_bits { 5051 u8 opcode[0x10]; 5052 u8 reserved_at_10[0x10]; 5053 5054 u8 reserved_at_20[0x10]; 5055 u8 op_mod[0x10]; 5056 5057 u8 other_vport[0x1]; 5058 u8 reserved_at_41[0xf]; 5059 u8 vport_number[0x10]; 5060 5061 u8 reserved_at_60[0x20]; 5062 }; 5063 5064 struct mlx5_ifc_query_vnic_env_out_bits { 5065 u8 status[0x8]; 5066 u8 reserved_at_8[0x18]; 5067 5068 u8 syndrome[0x20]; 5069 5070 u8 reserved_at_40[0x40]; 5071 5072 struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env; 5073 }; 5074 5075 enum { 5076 MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS = 0x0, 5077 }; 5078 5079 struct mlx5_ifc_query_vnic_env_in_bits { 5080 u8 opcode[0x10]; 5081 u8 reserved_at_10[0x10]; 5082 5083 u8 reserved_at_20[0x10]; 5084 u8 op_mod[0x10]; 5085 5086 u8 other_vport[0x1]; 5087 u8 reserved_at_41[0xf]; 5088 u8 vport_number[0x10]; 5089 5090 u8 reserved_at_60[0x20]; 5091 }; 5092 5093 struct mlx5_ifc_query_vport_counter_out_bits { 5094 u8 status[0x8]; 5095 u8 reserved_at_8[0x18]; 5096 5097 u8 syndrome[0x20]; 5098 5099 u8 reserved_at_40[0x40]; 5100 5101 struct mlx5_ifc_traffic_counter_bits received_errors; 5102 5103 struct mlx5_ifc_traffic_counter_bits transmit_errors; 5104 5105 struct mlx5_ifc_traffic_counter_bits received_ib_unicast; 5106 5107 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast; 5108 5109 struct mlx5_ifc_traffic_counter_bits received_ib_multicast; 5110 5111 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast; 5112 5113 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast; 5114 5115 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast; 5116 5117 struct mlx5_ifc_traffic_counter_bits received_eth_unicast; 5118 5119 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast; 5120 5121 struct mlx5_ifc_traffic_counter_bits received_eth_multicast; 5122 5123 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast; 5124 5125 u8 reserved_at_680[0xa00]; 5126 }; 5127 5128 enum { 5129 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0, 5130 }; 5131 5132 struct mlx5_ifc_query_vport_counter_in_bits { 5133 u8 opcode[0x10]; 5134 u8 reserved_at_10[0x10]; 5135 5136 u8 reserved_at_20[0x10]; 5137 u8 op_mod[0x10]; 5138 5139 u8 other_vport[0x1]; 5140 u8 reserved_at_41[0xb]; 5141 u8 port_num[0x4]; 5142 u8 vport_number[0x10]; 5143 5144 u8 reserved_at_60[0x60]; 5145 5146 u8 clear[0x1]; 5147 u8 reserved_at_c1[0x1f]; 5148 5149 u8 reserved_at_e0[0x20]; 5150 }; 5151 5152 struct mlx5_ifc_query_tis_out_bits { 5153 u8 status[0x8]; 5154 u8 reserved_at_8[0x18]; 5155 5156 u8 syndrome[0x20]; 5157 5158 u8 reserved_at_40[0x40]; 5159 5160 struct mlx5_ifc_tisc_bits tis_context; 5161 }; 5162 5163 struct mlx5_ifc_query_tis_in_bits { 5164 u8 opcode[0x10]; 5165 u8 reserved_at_10[0x10]; 5166 5167 u8 reserved_at_20[0x10]; 5168 u8 op_mod[0x10]; 5169 5170 u8 reserved_at_40[0x8]; 5171 u8 tisn[0x18]; 5172 5173 u8 reserved_at_60[0x20]; 5174 }; 5175 5176 struct mlx5_ifc_query_tir_out_bits { 5177 u8 status[0x8]; 5178 u8 reserved_at_8[0x18]; 5179 5180 u8 syndrome[0x20]; 5181 5182 u8 reserved_at_40[0xc0]; 5183 5184 struct mlx5_ifc_tirc_bits tir_context; 5185 }; 5186 5187 struct mlx5_ifc_query_tir_in_bits { 5188 u8 opcode[0x10]; 5189 u8 reserved_at_10[0x10]; 5190 5191 u8 reserved_at_20[0x10]; 5192 u8 op_mod[0x10]; 5193 5194 u8 reserved_at_40[0x8]; 5195 u8 tirn[0x18]; 5196 5197 u8 reserved_at_60[0x20]; 5198 }; 5199 5200 struct mlx5_ifc_query_srq_out_bits { 5201 u8 status[0x8]; 5202 u8 reserved_at_8[0x18]; 5203 5204 u8 syndrome[0x20]; 5205 5206 u8 reserved_at_40[0x40]; 5207 5208 struct mlx5_ifc_srqc_bits srq_context_entry; 5209 5210 u8 reserved_at_280[0x600]; 5211 5212 u8 pas[][0x40]; 5213 }; 5214 5215 struct mlx5_ifc_query_srq_in_bits { 5216 u8 opcode[0x10]; 5217 u8 reserved_at_10[0x10]; 5218 5219 u8 reserved_at_20[0x10]; 5220 u8 op_mod[0x10]; 5221 5222 u8 reserved_at_40[0x8]; 5223 u8 srqn[0x18]; 5224 5225 u8 reserved_at_60[0x20]; 5226 }; 5227 5228 struct mlx5_ifc_query_sq_out_bits { 5229 u8 status[0x8]; 5230 u8 reserved_at_8[0x18]; 5231 5232 u8 syndrome[0x20]; 5233 5234 u8 reserved_at_40[0xc0]; 5235 5236 struct mlx5_ifc_sqc_bits sq_context; 5237 }; 5238 5239 struct mlx5_ifc_query_sq_in_bits { 5240 u8 opcode[0x10]; 5241 u8 reserved_at_10[0x10]; 5242 5243 u8 reserved_at_20[0x10]; 5244 u8 op_mod[0x10]; 5245 5246 u8 reserved_at_40[0x8]; 5247 u8 sqn[0x18]; 5248 5249 u8 reserved_at_60[0x20]; 5250 }; 5251 5252 struct mlx5_ifc_query_special_contexts_out_bits { 5253 u8 status[0x8]; 5254 u8 reserved_at_8[0x18]; 5255 5256 u8 syndrome[0x20]; 5257 5258 u8 dump_fill_mkey[0x20]; 5259 5260 u8 resd_lkey[0x20]; 5261 5262 u8 null_mkey[0x20]; 5263 5264 u8 reserved_at_a0[0x60]; 5265 }; 5266 5267 struct mlx5_ifc_query_special_contexts_in_bits { 5268 u8 opcode[0x10]; 5269 u8 reserved_at_10[0x10]; 5270 5271 u8 reserved_at_20[0x10]; 5272 u8 op_mod[0x10]; 5273 5274 u8 reserved_at_40[0x40]; 5275 }; 5276 5277 struct mlx5_ifc_query_scheduling_element_out_bits { 5278 u8 opcode[0x10]; 5279 u8 reserved_at_10[0x10]; 5280 5281 u8 reserved_at_20[0x10]; 5282 u8 op_mod[0x10]; 5283 5284 u8 reserved_at_40[0xc0]; 5285 5286 struct mlx5_ifc_scheduling_context_bits scheduling_context; 5287 5288 u8 reserved_at_300[0x100]; 5289 }; 5290 5291 enum { 5292 SCHEDULING_HIERARCHY_E_SWITCH = 0x2, 5293 SCHEDULING_HIERARCHY_NIC = 0x3, 5294 }; 5295 5296 struct mlx5_ifc_query_scheduling_element_in_bits { 5297 u8 opcode[0x10]; 5298 u8 reserved_at_10[0x10]; 5299 5300 u8 reserved_at_20[0x10]; 5301 u8 op_mod[0x10]; 5302 5303 u8 scheduling_hierarchy[0x8]; 5304 u8 reserved_at_48[0x18]; 5305 5306 u8 scheduling_element_id[0x20]; 5307 5308 u8 reserved_at_80[0x180]; 5309 }; 5310 5311 struct mlx5_ifc_query_rqt_out_bits { 5312 u8 status[0x8]; 5313 u8 reserved_at_8[0x18]; 5314 5315 u8 syndrome[0x20]; 5316 5317 u8 reserved_at_40[0xc0]; 5318 5319 struct mlx5_ifc_rqtc_bits rqt_context; 5320 }; 5321 5322 struct mlx5_ifc_query_rqt_in_bits { 5323 u8 opcode[0x10]; 5324 u8 reserved_at_10[0x10]; 5325 5326 u8 reserved_at_20[0x10]; 5327 u8 op_mod[0x10]; 5328 5329 u8 reserved_at_40[0x8]; 5330 u8 rqtn[0x18]; 5331 5332 u8 reserved_at_60[0x20]; 5333 }; 5334 5335 struct mlx5_ifc_query_rq_out_bits { 5336 u8 status[0x8]; 5337 u8 reserved_at_8[0x18]; 5338 5339 u8 syndrome[0x20]; 5340 5341 u8 reserved_at_40[0xc0]; 5342 5343 struct mlx5_ifc_rqc_bits rq_context; 5344 }; 5345 5346 struct mlx5_ifc_query_rq_in_bits { 5347 u8 opcode[0x10]; 5348 u8 reserved_at_10[0x10]; 5349 5350 u8 reserved_at_20[0x10]; 5351 u8 op_mod[0x10]; 5352 5353 u8 reserved_at_40[0x8]; 5354 u8 rqn[0x18]; 5355 5356 u8 reserved_at_60[0x20]; 5357 }; 5358 5359 struct mlx5_ifc_query_roce_address_out_bits { 5360 u8 status[0x8]; 5361 u8 reserved_at_8[0x18]; 5362 5363 u8 syndrome[0x20]; 5364 5365 u8 reserved_at_40[0x40]; 5366 5367 struct mlx5_ifc_roce_addr_layout_bits roce_address; 5368 }; 5369 5370 struct mlx5_ifc_query_roce_address_in_bits { 5371 u8 opcode[0x10]; 5372 u8 reserved_at_10[0x10]; 5373 5374 u8 reserved_at_20[0x10]; 5375 u8 op_mod[0x10]; 5376 5377 u8 roce_address_index[0x10]; 5378 u8 reserved_at_50[0xc]; 5379 u8 vhca_port_num[0x4]; 5380 5381 u8 reserved_at_60[0x20]; 5382 }; 5383 5384 struct mlx5_ifc_query_rmp_out_bits { 5385 u8 status[0x8]; 5386 u8 reserved_at_8[0x18]; 5387 5388 u8 syndrome[0x20]; 5389 5390 u8 reserved_at_40[0xc0]; 5391 5392 struct mlx5_ifc_rmpc_bits rmp_context; 5393 }; 5394 5395 struct mlx5_ifc_query_rmp_in_bits { 5396 u8 opcode[0x10]; 5397 u8 reserved_at_10[0x10]; 5398 5399 u8 reserved_at_20[0x10]; 5400 u8 op_mod[0x10]; 5401 5402 u8 reserved_at_40[0x8]; 5403 u8 rmpn[0x18]; 5404 5405 u8 reserved_at_60[0x20]; 5406 }; 5407 5408 struct mlx5_ifc_cqe_error_syndrome_bits { 5409 u8 hw_error_syndrome[0x8]; 5410 u8 hw_syndrome_type[0x4]; 5411 u8 reserved_at_c[0x4]; 5412 u8 vendor_error_syndrome[0x8]; 5413 u8 syndrome[0x8]; 5414 }; 5415 5416 struct mlx5_ifc_qp_context_extension_bits { 5417 u8 reserved_at_0[0x60]; 5418 5419 struct mlx5_ifc_cqe_error_syndrome_bits error_syndrome; 5420 5421 u8 reserved_at_80[0x580]; 5422 }; 5423 5424 struct mlx5_ifc_qpc_extension_and_pas_list_in_bits { 5425 struct mlx5_ifc_qp_context_extension_bits qpc_data_extension; 5426 5427 u8 pas[0][0x40]; 5428 }; 5429 5430 struct mlx5_ifc_qp_pas_list_in_bits { 5431 struct mlx5_ifc_cmd_pas_bits pas[0]; 5432 }; 5433 5434 union mlx5_ifc_qp_pas_or_qpc_ext_and_pas_bits { 5435 struct mlx5_ifc_qp_pas_list_in_bits qp_pas_list; 5436 struct mlx5_ifc_qpc_extension_and_pas_list_in_bits qpc_ext_and_pas_list; 5437 }; 5438 5439 struct mlx5_ifc_query_qp_out_bits { 5440 u8 status[0x8]; 5441 u8 reserved_at_8[0x18]; 5442 5443 u8 syndrome[0x20]; 5444 5445 u8 reserved_at_40[0x40]; 5446 5447 u8 opt_param_mask[0x20]; 5448 5449 u8 ece[0x20]; 5450 5451 struct mlx5_ifc_qpc_bits qpc; 5452 5453 u8 reserved_at_800[0x80]; 5454 5455 union mlx5_ifc_qp_pas_or_qpc_ext_and_pas_bits qp_pas_or_qpc_ext_and_pas; 5456 }; 5457 5458 struct mlx5_ifc_query_qp_in_bits { 5459 u8 opcode[0x10]; 5460 u8 reserved_at_10[0x10]; 5461 5462 u8 reserved_at_20[0x10]; 5463 u8 op_mod[0x10]; 5464 5465 u8 qpc_ext[0x1]; 5466 u8 reserved_at_41[0x7]; 5467 u8 qpn[0x18]; 5468 5469 u8 reserved_at_60[0x20]; 5470 }; 5471 5472 struct mlx5_ifc_query_q_counter_out_bits { 5473 u8 status[0x8]; 5474 u8 reserved_at_8[0x18]; 5475 5476 u8 syndrome[0x20]; 5477 5478 u8 reserved_at_40[0x40]; 5479 5480 u8 rx_write_requests[0x20]; 5481 5482 u8 reserved_at_a0[0x20]; 5483 5484 u8 rx_read_requests[0x20]; 5485 5486 u8 reserved_at_e0[0x20]; 5487 5488 u8 rx_atomic_requests[0x20]; 5489 5490 u8 reserved_at_120[0x20]; 5491 5492 u8 rx_dct_connect[0x20]; 5493 5494 u8 reserved_at_160[0x20]; 5495 5496 u8 out_of_buffer[0x20]; 5497 5498 u8 reserved_at_1a0[0x20]; 5499 5500 u8 out_of_sequence[0x20]; 5501 5502 u8 reserved_at_1e0[0x20]; 5503 5504 u8 duplicate_request[0x20]; 5505 5506 u8 reserved_at_220[0x20]; 5507 5508 u8 rnr_nak_retry_err[0x20]; 5509 5510 u8 reserved_at_260[0x20]; 5511 5512 u8 packet_seq_err[0x20]; 5513 5514 u8 reserved_at_2a0[0x20]; 5515 5516 u8 implied_nak_seq_err[0x20]; 5517 5518 u8 reserved_at_2e0[0x20]; 5519 5520 u8 local_ack_timeout_err[0x20]; 5521 5522 u8 reserved_at_320[0xa0]; 5523 5524 u8 resp_local_length_error[0x20]; 5525 5526 u8 req_local_length_error[0x20]; 5527 5528 u8 resp_local_qp_error[0x20]; 5529 5530 u8 local_operation_error[0x20]; 5531 5532 u8 resp_local_protection[0x20]; 5533 5534 u8 req_local_protection[0x20]; 5535 5536 u8 resp_cqe_error[0x20]; 5537 5538 u8 req_cqe_error[0x20]; 5539 5540 u8 req_mw_binding[0x20]; 5541 5542 u8 req_bad_response[0x20]; 5543 5544 u8 req_remote_invalid_request[0x20]; 5545 5546 u8 resp_remote_invalid_request[0x20]; 5547 5548 u8 req_remote_access_errors[0x20]; 5549 5550 u8 resp_remote_access_errors[0x20]; 5551 5552 u8 req_remote_operation_errors[0x20]; 5553 5554 u8 req_transport_retries_exceeded[0x20]; 5555 5556 u8 cq_overflow[0x20]; 5557 5558 u8 resp_cqe_flush_error[0x20]; 5559 5560 u8 req_cqe_flush_error[0x20]; 5561 5562 u8 reserved_at_620[0x20]; 5563 5564 u8 roce_adp_retrans[0x20]; 5565 5566 u8 roce_adp_retrans_to[0x20]; 5567 5568 u8 roce_slow_restart[0x20]; 5569 5570 u8 roce_slow_restart_cnps[0x20]; 5571 5572 u8 roce_slow_restart_trans[0x20]; 5573 5574 u8 reserved_at_6e0[0x120]; 5575 }; 5576 5577 struct mlx5_ifc_query_q_counter_in_bits { 5578 u8 opcode[0x10]; 5579 u8 reserved_at_10[0x10]; 5580 5581 u8 reserved_at_20[0x10]; 5582 u8 op_mod[0x10]; 5583 5584 u8 reserved_at_40[0x80]; 5585 5586 u8 clear[0x1]; 5587 u8 reserved_at_c1[0x1f]; 5588 5589 u8 reserved_at_e0[0x18]; 5590 u8 counter_set_id[0x8]; 5591 }; 5592 5593 struct mlx5_ifc_query_pages_out_bits { 5594 u8 status[0x8]; 5595 u8 reserved_at_8[0x18]; 5596 5597 u8 syndrome[0x20]; 5598 5599 u8 embedded_cpu_function[0x1]; 5600 u8 reserved_at_41[0xf]; 5601 u8 function_id[0x10]; 5602 5603 u8 num_pages[0x20]; 5604 }; 5605 5606 enum { 5607 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1, 5608 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2, 5609 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3, 5610 }; 5611 5612 struct mlx5_ifc_query_pages_in_bits { 5613 u8 opcode[0x10]; 5614 u8 reserved_at_10[0x10]; 5615 5616 u8 reserved_at_20[0x10]; 5617 u8 op_mod[0x10]; 5618 5619 u8 embedded_cpu_function[0x1]; 5620 u8 reserved_at_41[0xf]; 5621 u8 function_id[0x10]; 5622 5623 u8 reserved_at_60[0x20]; 5624 }; 5625 5626 struct mlx5_ifc_query_nic_vport_context_out_bits { 5627 u8 status[0x8]; 5628 u8 reserved_at_8[0x18]; 5629 5630 u8 syndrome[0x20]; 5631 5632 u8 reserved_at_40[0x40]; 5633 5634 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 5635 }; 5636 5637 struct mlx5_ifc_query_nic_vport_context_in_bits { 5638 u8 opcode[0x10]; 5639 u8 reserved_at_10[0x10]; 5640 5641 u8 reserved_at_20[0x10]; 5642 u8 op_mod[0x10]; 5643 5644 u8 other_vport[0x1]; 5645 u8 reserved_at_41[0xf]; 5646 u8 vport_number[0x10]; 5647 5648 u8 reserved_at_60[0x5]; 5649 u8 allowed_list_type[0x3]; 5650 u8 reserved_at_68[0x18]; 5651 }; 5652 5653 struct mlx5_ifc_query_mkey_out_bits { 5654 u8 status[0x8]; 5655 u8 reserved_at_8[0x18]; 5656 5657 u8 syndrome[0x20]; 5658 5659 u8 reserved_at_40[0x40]; 5660 5661 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 5662 5663 u8 reserved_at_280[0x600]; 5664 5665 u8 bsf0_klm0_pas_mtt0_1[16][0x8]; 5666 5667 u8 bsf1_klm1_pas_mtt2_3[16][0x8]; 5668 }; 5669 5670 struct mlx5_ifc_query_mkey_in_bits { 5671 u8 opcode[0x10]; 5672 u8 reserved_at_10[0x10]; 5673 5674 u8 reserved_at_20[0x10]; 5675 u8 op_mod[0x10]; 5676 5677 u8 reserved_at_40[0x8]; 5678 u8 mkey_index[0x18]; 5679 5680 u8 pg_access[0x1]; 5681 u8 reserved_at_61[0x1f]; 5682 }; 5683 5684 struct mlx5_ifc_query_mad_demux_out_bits { 5685 u8 status[0x8]; 5686 u8 reserved_at_8[0x18]; 5687 5688 u8 syndrome[0x20]; 5689 5690 u8 reserved_at_40[0x40]; 5691 5692 u8 mad_dumux_parameters_block[0x20]; 5693 }; 5694 5695 struct mlx5_ifc_query_mad_demux_in_bits { 5696 u8 opcode[0x10]; 5697 u8 reserved_at_10[0x10]; 5698 5699 u8 reserved_at_20[0x10]; 5700 u8 op_mod[0x10]; 5701 5702 u8 reserved_at_40[0x40]; 5703 }; 5704 5705 struct mlx5_ifc_query_l2_table_entry_out_bits { 5706 u8 status[0x8]; 5707 u8 reserved_at_8[0x18]; 5708 5709 u8 syndrome[0x20]; 5710 5711 u8 reserved_at_40[0xa0]; 5712 5713 u8 reserved_at_e0[0x13]; 5714 u8 vlan_valid[0x1]; 5715 u8 vlan[0xc]; 5716 5717 struct mlx5_ifc_mac_address_layout_bits mac_address; 5718 5719 u8 reserved_at_140[0xc0]; 5720 }; 5721 5722 struct mlx5_ifc_query_l2_table_entry_in_bits { 5723 u8 opcode[0x10]; 5724 u8 reserved_at_10[0x10]; 5725 5726 u8 reserved_at_20[0x10]; 5727 u8 op_mod[0x10]; 5728 5729 u8 reserved_at_40[0x60]; 5730 5731 u8 reserved_at_a0[0x8]; 5732 u8 table_index[0x18]; 5733 5734 u8 reserved_at_c0[0x140]; 5735 }; 5736 5737 struct mlx5_ifc_query_issi_out_bits { 5738 u8 status[0x8]; 5739 u8 reserved_at_8[0x18]; 5740 5741 u8 syndrome[0x20]; 5742 5743 u8 reserved_at_40[0x10]; 5744 u8 current_issi[0x10]; 5745 5746 u8 reserved_at_60[0xa0]; 5747 5748 u8 reserved_at_100[76][0x8]; 5749 u8 supported_issi_dw0[0x20]; 5750 }; 5751 5752 struct mlx5_ifc_query_issi_in_bits { 5753 u8 opcode[0x10]; 5754 u8 reserved_at_10[0x10]; 5755 5756 u8 reserved_at_20[0x10]; 5757 u8 op_mod[0x10]; 5758 5759 u8 reserved_at_40[0x40]; 5760 }; 5761 5762 struct mlx5_ifc_set_driver_version_out_bits { 5763 u8 status[0x8]; 5764 u8 reserved_0[0x18]; 5765 5766 u8 syndrome[0x20]; 5767 u8 reserved_1[0x40]; 5768 }; 5769 5770 struct mlx5_ifc_set_driver_version_in_bits { 5771 u8 opcode[0x10]; 5772 u8 reserved_0[0x10]; 5773 5774 u8 reserved_1[0x10]; 5775 u8 op_mod[0x10]; 5776 5777 u8 reserved_2[0x40]; 5778 u8 driver_version[64][0x8]; 5779 }; 5780 5781 struct mlx5_ifc_query_hca_vport_pkey_out_bits { 5782 u8 status[0x8]; 5783 u8 reserved_at_8[0x18]; 5784 5785 u8 syndrome[0x20]; 5786 5787 u8 reserved_at_40[0x40]; 5788 5789 struct mlx5_ifc_pkey_bits pkey[]; 5790 }; 5791 5792 struct mlx5_ifc_query_hca_vport_pkey_in_bits { 5793 u8 opcode[0x10]; 5794 u8 reserved_at_10[0x10]; 5795 5796 u8 reserved_at_20[0x10]; 5797 u8 op_mod[0x10]; 5798 5799 u8 other_vport[0x1]; 5800 u8 reserved_at_41[0xb]; 5801 u8 port_num[0x4]; 5802 u8 vport_number[0x10]; 5803 5804 u8 reserved_at_60[0x10]; 5805 u8 pkey_index[0x10]; 5806 }; 5807 5808 enum { 5809 MLX5_HCA_VPORT_SEL_PORT_GUID = 1 << 0, 5810 MLX5_HCA_VPORT_SEL_NODE_GUID = 1 << 1, 5811 MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2, 5812 }; 5813 5814 struct mlx5_ifc_query_hca_vport_gid_out_bits { 5815 u8 status[0x8]; 5816 u8 reserved_at_8[0x18]; 5817 5818 u8 syndrome[0x20]; 5819 5820 u8 reserved_at_40[0x20]; 5821 5822 u8 gids_num[0x10]; 5823 u8 reserved_at_70[0x10]; 5824 5825 struct mlx5_ifc_array128_auto_bits gid[]; 5826 }; 5827 5828 struct mlx5_ifc_query_hca_vport_gid_in_bits { 5829 u8 opcode[0x10]; 5830 u8 reserved_at_10[0x10]; 5831 5832 u8 reserved_at_20[0x10]; 5833 u8 op_mod[0x10]; 5834 5835 u8 other_vport[0x1]; 5836 u8 reserved_at_41[0xb]; 5837 u8 port_num[0x4]; 5838 u8 vport_number[0x10]; 5839 5840 u8 reserved_at_60[0x10]; 5841 u8 gid_index[0x10]; 5842 }; 5843 5844 struct mlx5_ifc_query_hca_vport_context_out_bits { 5845 u8 status[0x8]; 5846 u8 reserved_at_8[0x18]; 5847 5848 u8 syndrome[0x20]; 5849 5850 u8 reserved_at_40[0x40]; 5851 5852 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 5853 }; 5854 5855 struct mlx5_ifc_query_hca_vport_context_in_bits { 5856 u8 opcode[0x10]; 5857 u8 reserved_at_10[0x10]; 5858 5859 u8 reserved_at_20[0x10]; 5860 u8 op_mod[0x10]; 5861 5862 u8 other_vport[0x1]; 5863 u8 reserved_at_41[0xb]; 5864 u8 port_num[0x4]; 5865 u8 vport_number[0x10]; 5866 5867 u8 reserved_at_60[0x20]; 5868 }; 5869 5870 struct mlx5_ifc_query_hca_cap_out_bits { 5871 u8 status[0x8]; 5872 u8 reserved_at_8[0x18]; 5873 5874 u8 syndrome[0x20]; 5875 5876 u8 reserved_at_40[0x40]; 5877 5878 union mlx5_ifc_hca_cap_union_bits capability; 5879 }; 5880 5881 struct mlx5_ifc_query_hca_cap_in_bits { 5882 u8 opcode[0x10]; 5883 u8 reserved_at_10[0x10]; 5884 5885 u8 reserved_at_20[0x10]; 5886 u8 op_mod[0x10]; 5887 5888 u8 other_function[0x1]; 5889 u8 reserved_at_41[0xf]; 5890 u8 function_id[0x10]; 5891 5892 u8 reserved_at_60[0x20]; 5893 }; 5894 5895 struct mlx5_ifc_other_hca_cap_bits { 5896 u8 roce[0x1]; 5897 u8 reserved_at_1[0x27f]; 5898 }; 5899 5900 struct mlx5_ifc_query_other_hca_cap_out_bits { 5901 u8 status[0x8]; 5902 u8 reserved_at_8[0x18]; 5903 5904 u8 syndrome[0x20]; 5905 5906 u8 reserved_at_40[0x40]; 5907 5908 struct mlx5_ifc_other_hca_cap_bits other_capability; 5909 }; 5910 5911 struct mlx5_ifc_query_other_hca_cap_in_bits { 5912 u8 opcode[0x10]; 5913 u8 reserved_at_10[0x10]; 5914 5915 u8 reserved_at_20[0x10]; 5916 u8 op_mod[0x10]; 5917 5918 u8 reserved_at_40[0x10]; 5919 u8 function_id[0x10]; 5920 5921 u8 reserved_at_60[0x20]; 5922 }; 5923 5924 struct mlx5_ifc_modify_other_hca_cap_out_bits { 5925 u8 status[0x8]; 5926 u8 reserved_at_8[0x18]; 5927 5928 u8 syndrome[0x20]; 5929 5930 u8 reserved_at_40[0x40]; 5931 }; 5932 5933 struct mlx5_ifc_modify_other_hca_cap_in_bits { 5934 u8 opcode[0x10]; 5935 u8 reserved_at_10[0x10]; 5936 5937 u8 reserved_at_20[0x10]; 5938 u8 op_mod[0x10]; 5939 5940 u8 reserved_at_40[0x10]; 5941 u8 function_id[0x10]; 5942 u8 field_select[0x20]; 5943 5944 struct mlx5_ifc_other_hca_cap_bits other_capability; 5945 }; 5946 5947 struct mlx5_ifc_flow_table_context_bits { 5948 u8 reformat_en[0x1]; 5949 u8 decap_en[0x1]; 5950 u8 sw_owner[0x1]; 5951 u8 termination_table[0x1]; 5952 u8 table_miss_action[0x4]; 5953 u8 level[0x8]; 5954 u8 reserved_at_10[0x8]; 5955 u8 log_size[0x8]; 5956 5957 u8 reserved_at_20[0x8]; 5958 u8 table_miss_id[0x18]; 5959 5960 u8 reserved_at_40[0x8]; 5961 u8 lag_master_next_table_id[0x18]; 5962 5963 u8 reserved_at_60[0x60]; 5964 5965 u8 sw_owner_icm_root_1[0x40]; 5966 5967 u8 sw_owner_icm_root_0[0x40]; 5968 5969 }; 5970 5971 struct mlx5_ifc_query_flow_table_out_bits { 5972 u8 status[0x8]; 5973 u8 reserved_at_8[0x18]; 5974 5975 u8 syndrome[0x20]; 5976 5977 u8 reserved_at_40[0x80]; 5978 5979 struct mlx5_ifc_flow_table_context_bits flow_table_context; 5980 }; 5981 5982 struct mlx5_ifc_query_flow_table_in_bits { 5983 u8 opcode[0x10]; 5984 u8 reserved_at_10[0x10]; 5985 5986 u8 reserved_at_20[0x10]; 5987 u8 op_mod[0x10]; 5988 5989 u8 reserved_at_40[0x40]; 5990 5991 u8 table_type[0x8]; 5992 u8 reserved_at_88[0x18]; 5993 5994 u8 reserved_at_a0[0x8]; 5995 u8 table_id[0x18]; 5996 5997 u8 reserved_at_c0[0x140]; 5998 }; 5999 6000 struct mlx5_ifc_query_fte_out_bits { 6001 u8 status[0x8]; 6002 u8 reserved_at_8[0x18]; 6003 6004 u8 syndrome[0x20]; 6005 6006 u8 reserved_at_40[0x1c0]; 6007 6008 struct mlx5_ifc_flow_context_bits flow_context; 6009 }; 6010 6011 struct mlx5_ifc_query_fte_in_bits { 6012 u8 opcode[0x10]; 6013 u8 reserved_at_10[0x10]; 6014 6015 u8 reserved_at_20[0x10]; 6016 u8 op_mod[0x10]; 6017 6018 u8 reserved_at_40[0x40]; 6019 6020 u8 table_type[0x8]; 6021 u8 reserved_at_88[0x18]; 6022 6023 u8 reserved_at_a0[0x8]; 6024 u8 table_id[0x18]; 6025 6026 u8 reserved_at_c0[0x40]; 6027 6028 u8 flow_index[0x20]; 6029 6030 u8 reserved_at_120[0xe0]; 6031 }; 6032 6033 struct mlx5_ifc_match_definer_format_0_bits { 6034 u8 reserved_at_0[0x100]; 6035 6036 u8 metadata_reg_c_0[0x20]; 6037 6038 u8 metadata_reg_c_1[0x20]; 6039 6040 u8 outer_dmac_47_16[0x20]; 6041 6042 u8 outer_dmac_15_0[0x10]; 6043 u8 outer_ethertype[0x10]; 6044 6045 u8 reserved_at_180[0x1]; 6046 u8 sx_sniffer[0x1]; 6047 u8 functional_lb[0x1]; 6048 u8 outer_ip_frag[0x1]; 6049 u8 outer_qp_type[0x2]; 6050 u8 outer_encap_type[0x2]; 6051 u8 port_number[0x2]; 6052 u8 outer_l3_type[0x2]; 6053 u8 outer_l4_type[0x2]; 6054 u8 outer_first_vlan_type[0x2]; 6055 u8 outer_first_vlan_prio[0x3]; 6056 u8 outer_first_vlan_cfi[0x1]; 6057 u8 outer_first_vlan_vid[0xc]; 6058 6059 u8 outer_l4_type_ext[0x4]; 6060 u8 reserved_at_1a4[0x2]; 6061 u8 outer_ipsec_layer[0x2]; 6062 u8 outer_l2_type[0x2]; 6063 u8 force_lb[0x1]; 6064 u8 outer_l2_ok[0x1]; 6065 u8 outer_l3_ok[0x1]; 6066 u8 outer_l4_ok[0x1]; 6067 u8 outer_second_vlan_type[0x2]; 6068 u8 outer_second_vlan_prio[0x3]; 6069 u8 outer_second_vlan_cfi[0x1]; 6070 u8 outer_second_vlan_vid[0xc]; 6071 6072 u8 outer_smac_47_16[0x20]; 6073 6074 u8 outer_smac_15_0[0x10]; 6075 u8 inner_ipv4_checksum_ok[0x1]; 6076 u8 inner_l4_checksum_ok[0x1]; 6077 u8 outer_ipv4_checksum_ok[0x1]; 6078 u8 outer_l4_checksum_ok[0x1]; 6079 u8 inner_l3_ok[0x1]; 6080 u8 inner_l4_ok[0x1]; 6081 u8 outer_l3_ok_duplicate[0x1]; 6082 u8 outer_l4_ok_duplicate[0x1]; 6083 u8 outer_tcp_cwr[0x1]; 6084 u8 outer_tcp_ece[0x1]; 6085 u8 outer_tcp_urg[0x1]; 6086 u8 outer_tcp_ack[0x1]; 6087 u8 outer_tcp_psh[0x1]; 6088 u8 outer_tcp_rst[0x1]; 6089 u8 outer_tcp_syn[0x1]; 6090 u8 outer_tcp_fin[0x1]; 6091 }; 6092 6093 struct mlx5_ifc_match_definer_format_22_bits { 6094 u8 reserved_at_0[0x100]; 6095 6096 u8 outer_ip_src_addr[0x20]; 6097 6098 u8 outer_ip_dest_addr[0x20]; 6099 6100 u8 outer_l4_sport[0x10]; 6101 u8 outer_l4_dport[0x10]; 6102 6103 u8 reserved_at_160[0x1]; 6104 u8 sx_sniffer[0x1]; 6105 u8 functional_lb[0x1]; 6106 u8 outer_ip_frag[0x1]; 6107 u8 outer_qp_type[0x2]; 6108 u8 outer_encap_type[0x2]; 6109 u8 port_number[0x2]; 6110 u8 outer_l3_type[0x2]; 6111 u8 outer_l4_type[0x2]; 6112 u8 outer_first_vlan_type[0x2]; 6113 u8 outer_first_vlan_prio[0x3]; 6114 u8 outer_first_vlan_cfi[0x1]; 6115 u8 outer_first_vlan_vid[0xc]; 6116 6117 u8 metadata_reg_c_0[0x20]; 6118 6119 u8 outer_dmac_47_16[0x20]; 6120 6121 u8 outer_smac_47_16[0x20]; 6122 6123 u8 outer_smac_15_0[0x10]; 6124 u8 outer_dmac_15_0[0x10]; 6125 }; 6126 6127 struct mlx5_ifc_match_definer_format_23_bits { 6128 u8 reserved_at_0[0x100]; 6129 6130 u8 inner_ip_src_addr[0x20]; 6131 6132 u8 inner_ip_dest_addr[0x20]; 6133 6134 u8 inner_l4_sport[0x10]; 6135 u8 inner_l4_dport[0x10]; 6136 6137 u8 reserved_at_160[0x1]; 6138 u8 sx_sniffer[0x1]; 6139 u8 functional_lb[0x1]; 6140 u8 inner_ip_frag[0x1]; 6141 u8 inner_qp_type[0x2]; 6142 u8 inner_encap_type[0x2]; 6143 u8 port_number[0x2]; 6144 u8 inner_l3_type[0x2]; 6145 u8 inner_l4_type[0x2]; 6146 u8 inner_first_vlan_type[0x2]; 6147 u8 inner_first_vlan_prio[0x3]; 6148 u8 inner_first_vlan_cfi[0x1]; 6149 u8 inner_first_vlan_vid[0xc]; 6150 6151 u8 tunnel_header_0[0x20]; 6152 6153 u8 inner_dmac_47_16[0x20]; 6154 6155 u8 inner_smac_47_16[0x20]; 6156 6157 u8 inner_smac_15_0[0x10]; 6158 u8 inner_dmac_15_0[0x10]; 6159 }; 6160 6161 struct mlx5_ifc_match_definer_format_29_bits { 6162 u8 reserved_at_0[0xc0]; 6163 6164 u8 outer_ip_dest_addr[0x80]; 6165 6166 u8 outer_ip_src_addr[0x80]; 6167 6168 u8 outer_l4_sport[0x10]; 6169 u8 outer_l4_dport[0x10]; 6170 6171 u8 reserved_at_1e0[0x20]; 6172 }; 6173 6174 struct mlx5_ifc_match_definer_format_30_bits { 6175 u8 reserved_at_0[0xa0]; 6176 6177 u8 outer_ip_dest_addr[0x80]; 6178 6179 u8 outer_ip_src_addr[0x80]; 6180 6181 u8 outer_dmac_47_16[0x20]; 6182 6183 u8 outer_smac_47_16[0x20]; 6184 6185 u8 outer_smac_15_0[0x10]; 6186 u8 outer_dmac_15_0[0x10]; 6187 }; 6188 6189 struct mlx5_ifc_match_definer_format_31_bits { 6190 u8 reserved_at_0[0xc0]; 6191 6192 u8 inner_ip_dest_addr[0x80]; 6193 6194 u8 inner_ip_src_addr[0x80]; 6195 6196 u8 inner_l4_sport[0x10]; 6197 u8 inner_l4_dport[0x10]; 6198 6199 u8 reserved_at_1e0[0x20]; 6200 }; 6201 6202 struct mlx5_ifc_match_definer_format_32_bits { 6203 u8 reserved_at_0[0xa0]; 6204 6205 u8 inner_ip_dest_addr[0x80]; 6206 6207 u8 inner_ip_src_addr[0x80]; 6208 6209 u8 inner_dmac_47_16[0x20]; 6210 6211 u8 inner_smac_47_16[0x20]; 6212 6213 u8 inner_smac_15_0[0x10]; 6214 u8 inner_dmac_15_0[0x10]; 6215 }; 6216 6217 enum { 6218 MLX5_IFC_DEFINER_FORMAT_ID_SELECT = 61, 6219 }; 6220 6221 #define MLX5_IFC_DEFINER_FORMAT_OFFSET_UNUSED 0x0 6222 #define MLX5_IFC_DEFINER_FORMAT_OFFSET_OUTER_ETH_PKT_LEN 0x48 6223 #define MLX5_IFC_DEFINER_DW_SELECTORS_NUM 9 6224 #define MLX5_IFC_DEFINER_BYTE_SELECTORS_NUM 8 6225 6226 struct mlx5_ifc_match_definer_match_mask_bits { 6227 u8 reserved_at_1c0[5][0x20]; 6228 u8 match_dw_8[0x20]; 6229 u8 match_dw_7[0x20]; 6230 u8 match_dw_6[0x20]; 6231 u8 match_dw_5[0x20]; 6232 u8 match_dw_4[0x20]; 6233 u8 match_dw_3[0x20]; 6234 u8 match_dw_2[0x20]; 6235 u8 match_dw_1[0x20]; 6236 u8 match_dw_0[0x20]; 6237 6238 u8 match_byte_7[0x8]; 6239 u8 match_byte_6[0x8]; 6240 u8 match_byte_5[0x8]; 6241 u8 match_byte_4[0x8]; 6242 6243 u8 match_byte_3[0x8]; 6244 u8 match_byte_2[0x8]; 6245 u8 match_byte_1[0x8]; 6246 u8 match_byte_0[0x8]; 6247 }; 6248 6249 struct mlx5_ifc_match_definer_bits { 6250 u8 modify_field_select[0x40]; 6251 6252 u8 reserved_at_40[0x40]; 6253 6254 u8 reserved_at_80[0x10]; 6255 u8 format_id[0x10]; 6256 6257 u8 reserved_at_a0[0x60]; 6258 6259 u8 format_select_dw3[0x8]; 6260 u8 format_select_dw2[0x8]; 6261 u8 format_select_dw1[0x8]; 6262 u8 format_select_dw0[0x8]; 6263 6264 u8 format_select_dw7[0x8]; 6265 u8 format_select_dw6[0x8]; 6266 u8 format_select_dw5[0x8]; 6267 u8 format_select_dw4[0x8]; 6268 6269 u8 reserved_at_100[0x18]; 6270 u8 format_select_dw8[0x8]; 6271 6272 u8 reserved_at_120[0x20]; 6273 6274 u8 format_select_byte3[0x8]; 6275 u8 format_select_byte2[0x8]; 6276 u8 format_select_byte1[0x8]; 6277 u8 format_select_byte0[0x8]; 6278 6279 u8 format_select_byte7[0x8]; 6280 u8 format_select_byte6[0x8]; 6281 u8 format_select_byte5[0x8]; 6282 u8 format_select_byte4[0x8]; 6283 6284 u8 reserved_at_180[0x40]; 6285 6286 union { 6287 struct { 6288 u8 match_mask[16][0x20]; 6289 }; 6290 struct mlx5_ifc_match_definer_match_mask_bits match_mask_format; 6291 }; 6292 }; 6293 6294 struct mlx5_ifc_general_obj_create_param_bits { 6295 u8 alias_object[0x1]; 6296 u8 reserved_at_1[0x2]; 6297 u8 log_obj_range[0x5]; 6298 u8 reserved_at_8[0x18]; 6299 }; 6300 6301 struct mlx5_ifc_general_obj_query_param_bits { 6302 u8 alias_object[0x1]; 6303 u8 obj_offset[0x1f]; 6304 }; 6305 6306 struct mlx5_ifc_general_obj_in_cmd_hdr_bits { 6307 u8 opcode[0x10]; 6308 u8 uid[0x10]; 6309 6310 u8 vhca_tunnel_id[0x10]; 6311 u8 obj_type[0x10]; 6312 6313 u8 obj_id[0x20]; 6314 6315 union { 6316 struct mlx5_ifc_general_obj_create_param_bits create; 6317 struct mlx5_ifc_general_obj_query_param_bits query; 6318 } op_param; 6319 }; 6320 6321 struct mlx5_ifc_general_obj_out_cmd_hdr_bits { 6322 u8 status[0x8]; 6323 u8 reserved_at_8[0x18]; 6324 6325 u8 syndrome[0x20]; 6326 6327 u8 obj_id[0x20]; 6328 6329 u8 reserved_at_60[0x20]; 6330 }; 6331 6332 struct mlx5_ifc_create_match_definer_in_bits { 6333 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 6334 6335 struct mlx5_ifc_match_definer_bits obj_context; 6336 }; 6337 6338 struct mlx5_ifc_create_match_definer_out_bits { 6339 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 6340 }; 6341 6342 enum { 6343 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 6344 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 6345 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 6346 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3, 6347 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_3 = 0x4, 6348 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_4 = 0x5, 6349 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_5 = 0x6, 6350 }; 6351 6352 struct mlx5_ifc_query_flow_group_out_bits { 6353 u8 status[0x8]; 6354 u8 reserved_at_8[0x18]; 6355 6356 u8 syndrome[0x20]; 6357 6358 u8 reserved_at_40[0xa0]; 6359 6360 u8 start_flow_index[0x20]; 6361 6362 u8 reserved_at_100[0x20]; 6363 6364 u8 end_flow_index[0x20]; 6365 6366 u8 reserved_at_140[0xa0]; 6367 6368 u8 reserved_at_1e0[0x18]; 6369 u8 match_criteria_enable[0x8]; 6370 6371 struct mlx5_ifc_fte_match_param_bits match_criteria; 6372 6373 u8 reserved_at_1200[0xe00]; 6374 }; 6375 6376 struct mlx5_ifc_query_flow_group_in_bits { 6377 u8 opcode[0x10]; 6378 u8 reserved_at_10[0x10]; 6379 6380 u8 reserved_at_20[0x10]; 6381 u8 op_mod[0x10]; 6382 6383 u8 reserved_at_40[0x40]; 6384 6385 u8 table_type[0x8]; 6386 u8 reserved_at_88[0x18]; 6387 6388 u8 reserved_at_a0[0x8]; 6389 u8 table_id[0x18]; 6390 6391 u8 group_id[0x20]; 6392 6393 u8 reserved_at_e0[0x120]; 6394 }; 6395 6396 struct mlx5_ifc_query_flow_counter_out_bits { 6397 u8 status[0x8]; 6398 u8 reserved_at_8[0x18]; 6399 6400 u8 syndrome[0x20]; 6401 6402 u8 reserved_at_40[0x40]; 6403 6404 struct mlx5_ifc_traffic_counter_bits flow_statistics[]; 6405 }; 6406 6407 struct mlx5_ifc_query_flow_counter_in_bits { 6408 u8 opcode[0x10]; 6409 u8 reserved_at_10[0x10]; 6410 6411 u8 reserved_at_20[0x10]; 6412 u8 op_mod[0x10]; 6413 6414 u8 reserved_at_40[0x80]; 6415 6416 u8 clear[0x1]; 6417 u8 reserved_at_c1[0xf]; 6418 u8 num_of_counters[0x10]; 6419 6420 u8 flow_counter_id[0x20]; 6421 }; 6422 6423 struct mlx5_ifc_query_esw_vport_context_out_bits { 6424 u8 status[0x8]; 6425 u8 reserved_at_8[0x18]; 6426 6427 u8 syndrome[0x20]; 6428 6429 u8 reserved_at_40[0x40]; 6430 6431 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 6432 }; 6433 6434 struct mlx5_ifc_query_esw_vport_context_in_bits { 6435 u8 opcode[0x10]; 6436 u8 reserved_at_10[0x10]; 6437 6438 u8 reserved_at_20[0x10]; 6439 u8 op_mod[0x10]; 6440 6441 u8 other_vport[0x1]; 6442 u8 reserved_at_41[0xf]; 6443 u8 vport_number[0x10]; 6444 6445 u8 reserved_at_60[0x20]; 6446 }; 6447 6448 struct mlx5_ifc_modify_esw_vport_context_out_bits { 6449 u8 status[0x8]; 6450 u8 reserved_at_8[0x18]; 6451 6452 u8 syndrome[0x20]; 6453 6454 u8 reserved_at_40[0x40]; 6455 }; 6456 6457 struct mlx5_ifc_esw_vport_context_fields_select_bits { 6458 u8 reserved_at_0[0x1b]; 6459 u8 fdb_to_vport_reg_c_id[0x1]; 6460 u8 vport_cvlan_insert[0x1]; 6461 u8 vport_svlan_insert[0x1]; 6462 u8 vport_cvlan_strip[0x1]; 6463 u8 vport_svlan_strip[0x1]; 6464 }; 6465 6466 struct mlx5_ifc_modify_esw_vport_context_in_bits { 6467 u8 opcode[0x10]; 6468 u8 reserved_at_10[0x10]; 6469 6470 u8 reserved_at_20[0x10]; 6471 u8 op_mod[0x10]; 6472 6473 u8 other_vport[0x1]; 6474 u8 reserved_at_41[0xf]; 6475 u8 vport_number[0x10]; 6476 6477 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select; 6478 6479 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 6480 }; 6481 6482 struct mlx5_ifc_query_eq_out_bits { 6483 u8 status[0x8]; 6484 u8 reserved_at_8[0x18]; 6485 6486 u8 syndrome[0x20]; 6487 6488 u8 reserved_at_40[0x40]; 6489 6490 struct mlx5_ifc_eqc_bits eq_context_entry; 6491 6492 u8 reserved_at_280[0x40]; 6493 6494 u8 event_bitmask[0x40]; 6495 6496 u8 reserved_at_300[0x580]; 6497 6498 u8 pas[][0x40]; 6499 }; 6500 6501 struct mlx5_ifc_query_eq_in_bits { 6502 u8 opcode[0x10]; 6503 u8 reserved_at_10[0x10]; 6504 6505 u8 reserved_at_20[0x10]; 6506 u8 op_mod[0x10]; 6507 6508 u8 reserved_at_40[0x18]; 6509 u8 eq_number[0x8]; 6510 6511 u8 reserved_at_60[0x20]; 6512 }; 6513 6514 struct mlx5_ifc_packet_reformat_context_in_bits { 6515 u8 reformat_type[0x8]; 6516 u8 reserved_at_8[0x4]; 6517 u8 reformat_param_0[0x4]; 6518 u8 reserved_at_10[0x6]; 6519 u8 reformat_data_size[0xa]; 6520 6521 u8 reformat_param_1[0x8]; 6522 u8 reserved_at_28[0x8]; 6523 u8 reformat_data[2][0x8]; 6524 6525 u8 more_reformat_data[][0x8]; 6526 }; 6527 6528 struct mlx5_ifc_query_packet_reformat_context_out_bits { 6529 u8 status[0x8]; 6530 u8 reserved_at_8[0x18]; 6531 6532 u8 syndrome[0x20]; 6533 6534 u8 reserved_at_40[0xa0]; 6535 6536 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context[]; 6537 }; 6538 6539 struct mlx5_ifc_query_packet_reformat_context_in_bits { 6540 u8 opcode[0x10]; 6541 u8 reserved_at_10[0x10]; 6542 6543 u8 reserved_at_20[0x10]; 6544 u8 op_mod[0x10]; 6545 6546 u8 packet_reformat_id[0x20]; 6547 6548 u8 reserved_at_60[0xa0]; 6549 }; 6550 6551 struct mlx5_ifc_alloc_packet_reformat_context_out_bits { 6552 u8 status[0x8]; 6553 u8 reserved_at_8[0x18]; 6554 6555 u8 syndrome[0x20]; 6556 6557 u8 packet_reformat_id[0x20]; 6558 6559 u8 reserved_at_60[0x20]; 6560 }; 6561 6562 enum { 6563 MLX5_REFORMAT_CONTEXT_ANCHOR_MAC_START = 0x1, 6564 MLX5_REFORMAT_CONTEXT_ANCHOR_IP_START = 0x7, 6565 MLX5_REFORMAT_CONTEXT_ANCHOR_TCP_UDP_START = 0x9, 6566 }; 6567 6568 enum mlx5_reformat_ctx_type { 6569 MLX5_REFORMAT_TYPE_L2_TO_VXLAN = 0x0, 6570 MLX5_REFORMAT_TYPE_L2_TO_NVGRE = 0x1, 6571 MLX5_REFORMAT_TYPE_L2_TO_L2_TUNNEL = 0x2, 6572 MLX5_REFORMAT_TYPE_L3_TUNNEL_TO_L2 = 0x3, 6573 MLX5_REFORMAT_TYPE_L2_TO_L3_TUNNEL = 0x4, 6574 MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_IPV4 = 0x5, 6575 MLX5_REFORMAT_TYPE_DEL_ESP_TRANSPORT = 0x8, 6576 MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_IPV6 = 0xb, 6577 MLX5_REFORMAT_TYPE_INSERT_HDR = 0xf, 6578 MLX5_REFORMAT_TYPE_REMOVE_HDR = 0x10, 6579 MLX5_REFORMAT_TYPE_ADD_MACSEC = 0x11, 6580 MLX5_REFORMAT_TYPE_DEL_MACSEC = 0x12, 6581 }; 6582 6583 struct mlx5_ifc_alloc_packet_reformat_context_in_bits { 6584 u8 opcode[0x10]; 6585 u8 reserved_at_10[0x10]; 6586 6587 u8 reserved_at_20[0x10]; 6588 u8 op_mod[0x10]; 6589 6590 u8 reserved_at_40[0xa0]; 6591 6592 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context; 6593 }; 6594 6595 struct mlx5_ifc_dealloc_packet_reformat_context_out_bits { 6596 u8 status[0x8]; 6597 u8 reserved_at_8[0x18]; 6598 6599 u8 syndrome[0x20]; 6600 6601 u8 reserved_at_40[0x40]; 6602 }; 6603 6604 struct mlx5_ifc_dealloc_packet_reformat_context_in_bits { 6605 u8 opcode[0x10]; 6606 u8 reserved_at_10[0x10]; 6607 6608 u8 reserved_20[0x10]; 6609 u8 op_mod[0x10]; 6610 6611 u8 packet_reformat_id[0x20]; 6612 6613 u8 reserved_60[0x20]; 6614 }; 6615 6616 struct mlx5_ifc_set_action_in_bits { 6617 u8 action_type[0x4]; 6618 u8 field[0xc]; 6619 u8 reserved_at_10[0x3]; 6620 u8 offset[0x5]; 6621 u8 reserved_at_18[0x3]; 6622 u8 length[0x5]; 6623 6624 u8 data[0x20]; 6625 }; 6626 6627 struct mlx5_ifc_add_action_in_bits { 6628 u8 action_type[0x4]; 6629 u8 field[0xc]; 6630 u8 reserved_at_10[0x10]; 6631 6632 u8 data[0x20]; 6633 }; 6634 6635 struct mlx5_ifc_copy_action_in_bits { 6636 u8 action_type[0x4]; 6637 u8 src_field[0xc]; 6638 u8 reserved_at_10[0x3]; 6639 u8 src_offset[0x5]; 6640 u8 reserved_at_18[0x3]; 6641 u8 length[0x5]; 6642 6643 u8 reserved_at_20[0x4]; 6644 u8 dst_field[0xc]; 6645 u8 reserved_at_30[0x3]; 6646 u8 dst_offset[0x5]; 6647 u8 reserved_at_38[0x8]; 6648 }; 6649 6650 union mlx5_ifc_set_add_copy_action_in_auto_bits { 6651 struct mlx5_ifc_set_action_in_bits set_action_in; 6652 struct mlx5_ifc_add_action_in_bits add_action_in; 6653 struct mlx5_ifc_copy_action_in_bits copy_action_in; 6654 u8 reserved_at_0[0x40]; 6655 }; 6656 6657 enum { 6658 MLX5_ACTION_TYPE_SET = 0x1, 6659 MLX5_ACTION_TYPE_ADD = 0x2, 6660 MLX5_ACTION_TYPE_COPY = 0x3, 6661 }; 6662 6663 enum { 6664 MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16 = 0x1, 6665 MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0 = 0x2, 6666 MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE = 0x3, 6667 MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16 = 0x4, 6668 MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0 = 0x5, 6669 MLX5_ACTION_IN_FIELD_OUT_IP_DSCP = 0x6, 6670 MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS = 0x7, 6671 MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT = 0x8, 6672 MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT = 0x9, 6673 MLX5_ACTION_IN_FIELD_OUT_IP_TTL = 0xa, 6674 MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT = 0xb, 6675 MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT = 0xc, 6676 MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96 = 0xd, 6677 MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64 = 0xe, 6678 MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32 = 0xf, 6679 MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0 = 0x10, 6680 MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96 = 0x11, 6681 MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64 = 0x12, 6682 MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32 = 0x13, 6683 MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0 = 0x14, 6684 MLX5_ACTION_IN_FIELD_OUT_SIPV4 = 0x15, 6685 MLX5_ACTION_IN_FIELD_OUT_DIPV4 = 0x16, 6686 MLX5_ACTION_IN_FIELD_OUT_FIRST_VID = 0x17, 6687 MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47, 6688 MLX5_ACTION_IN_FIELD_METADATA_REG_A = 0x49, 6689 MLX5_ACTION_IN_FIELD_METADATA_REG_B = 0x50, 6690 MLX5_ACTION_IN_FIELD_METADATA_REG_C_0 = 0x51, 6691 MLX5_ACTION_IN_FIELD_METADATA_REG_C_1 = 0x52, 6692 MLX5_ACTION_IN_FIELD_METADATA_REG_C_2 = 0x53, 6693 MLX5_ACTION_IN_FIELD_METADATA_REG_C_3 = 0x54, 6694 MLX5_ACTION_IN_FIELD_METADATA_REG_C_4 = 0x55, 6695 MLX5_ACTION_IN_FIELD_METADATA_REG_C_5 = 0x56, 6696 MLX5_ACTION_IN_FIELD_METADATA_REG_C_6 = 0x57, 6697 MLX5_ACTION_IN_FIELD_METADATA_REG_C_7 = 0x58, 6698 MLX5_ACTION_IN_FIELD_OUT_TCP_SEQ_NUM = 0x59, 6699 MLX5_ACTION_IN_FIELD_OUT_TCP_ACK_NUM = 0x5B, 6700 MLX5_ACTION_IN_FIELD_IPSEC_SYNDROME = 0x5D, 6701 MLX5_ACTION_IN_FIELD_OUT_EMD_47_32 = 0x6F, 6702 MLX5_ACTION_IN_FIELD_OUT_EMD_31_0 = 0x70, 6703 }; 6704 6705 struct mlx5_ifc_alloc_modify_header_context_out_bits { 6706 u8 status[0x8]; 6707 u8 reserved_at_8[0x18]; 6708 6709 u8 syndrome[0x20]; 6710 6711 u8 modify_header_id[0x20]; 6712 6713 u8 reserved_at_60[0x20]; 6714 }; 6715 6716 struct mlx5_ifc_alloc_modify_header_context_in_bits { 6717 u8 opcode[0x10]; 6718 u8 reserved_at_10[0x10]; 6719 6720 u8 reserved_at_20[0x10]; 6721 u8 op_mod[0x10]; 6722 6723 u8 reserved_at_40[0x20]; 6724 6725 u8 table_type[0x8]; 6726 u8 reserved_at_68[0x10]; 6727 u8 num_of_actions[0x8]; 6728 6729 union mlx5_ifc_set_add_copy_action_in_auto_bits actions[]; 6730 }; 6731 6732 struct mlx5_ifc_dealloc_modify_header_context_out_bits { 6733 u8 status[0x8]; 6734 u8 reserved_at_8[0x18]; 6735 6736 u8 syndrome[0x20]; 6737 6738 u8 reserved_at_40[0x40]; 6739 }; 6740 6741 struct mlx5_ifc_dealloc_modify_header_context_in_bits { 6742 u8 opcode[0x10]; 6743 u8 reserved_at_10[0x10]; 6744 6745 u8 reserved_at_20[0x10]; 6746 u8 op_mod[0x10]; 6747 6748 u8 modify_header_id[0x20]; 6749 6750 u8 reserved_at_60[0x20]; 6751 }; 6752 6753 struct mlx5_ifc_query_modify_header_context_in_bits { 6754 u8 opcode[0x10]; 6755 u8 uid[0x10]; 6756 6757 u8 reserved_at_20[0x10]; 6758 u8 op_mod[0x10]; 6759 6760 u8 modify_header_id[0x20]; 6761 6762 u8 reserved_at_60[0xa0]; 6763 }; 6764 6765 struct mlx5_ifc_query_dct_out_bits { 6766 u8 status[0x8]; 6767 u8 reserved_at_8[0x18]; 6768 6769 u8 syndrome[0x20]; 6770 6771 u8 reserved_at_40[0x40]; 6772 6773 struct mlx5_ifc_dctc_bits dct_context_entry; 6774 6775 u8 reserved_at_280[0x180]; 6776 }; 6777 6778 struct mlx5_ifc_query_dct_in_bits { 6779 u8 opcode[0x10]; 6780 u8 reserved_at_10[0x10]; 6781 6782 u8 reserved_at_20[0x10]; 6783 u8 op_mod[0x10]; 6784 6785 u8 reserved_at_40[0x8]; 6786 u8 dctn[0x18]; 6787 6788 u8 reserved_at_60[0x20]; 6789 }; 6790 6791 struct mlx5_ifc_query_cq_out_bits { 6792 u8 status[0x8]; 6793 u8 reserved_at_8[0x18]; 6794 6795 u8 syndrome[0x20]; 6796 6797 u8 reserved_at_40[0x40]; 6798 6799 struct mlx5_ifc_cqc_bits cq_context; 6800 6801 u8 reserved_at_280[0x600]; 6802 6803 u8 pas[][0x40]; 6804 }; 6805 6806 struct mlx5_ifc_query_cq_in_bits { 6807 u8 opcode[0x10]; 6808 u8 reserved_at_10[0x10]; 6809 6810 u8 reserved_at_20[0x10]; 6811 u8 op_mod[0x10]; 6812 6813 u8 reserved_at_40[0x8]; 6814 u8 cqn[0x18]; 6815 6816 u8 reserved_at_60[0x20]; 6817 }; 6818 6819 struct mlx5_ifc_query_cong_status_out_bits { 6820 u8 status[0x8]; 6821 u8 reserved_at_8[0x18]; 6822 6823 u8 syndrome[0x20]; 6824 6825 u8 reserved_at_40[0x20]; 6826 6827 u8 enable[0x1]; 6828 u8 tag_enable[0x1]; 6829 u8 reserved_at_62[0x1e]; 6830 }; 6831 6832 struct mlx5_ifc_query_cong_status_in_bits { 6833 u8 opcode[0x10]; 6834 u8 reserved_at_10[0x10]; 6835 6836 u8 reserved_at_20[0x10]; 6837 u8 op_mod[0x10]; 6838 6839 u8 reserved_at_40[0x18]; 6840 u8 priority[0x4]; 6841 u8 cong_protocol[0x4]; 6842 6843 u8 reserved_at_60[0x20]; 6844 }; 6845 6846 struct mlx5_ifc_query_cong_statistics_out_bits { 6847 u8 status[0x8]; 6848 u8 reserved_at_8[0x18]; 6849 6850 u8 syndrome[0x20]; 6851 6852 u8 reserved_at_40[0x40]; 6853 6854 u8 rp_cur_flows[0x20]; 6855 6856 u8 sum_flows[0x20]; 6857 6858 u8 rp_cnp_ignored_high[0x20]; 6859 6860 u8 rp_cnp_ignored_low[0x20]; 6861 6862 u8 rp_cnp_handled_high[0x20]; 6863 6864 u8 rp_cnp_handled_low[0x20]; 6865 6866 u8 reserved_at_140[0x100]; 6867 6868 u8 time_stamp_high[0x20]; 6869 6870 u8 time_stamp_low[0x20]; 6871 6872 u8 accumulators_period[0x20]; 6873 6874 u8 np_ecn_marked_roce_packets_high[0x20]; 6875 6876 u8 np_ecn_marked_roce_packets_low[0x20]; 6877 6878 u8 np_cnp_sent_high[0x20]; 6879 6880 u8 np_cnp_sent_low[0x20]; 6881 6882 u8 reserved_at_320[0x560]; 6883 }; 6884 6885 struct mlx5_ifc_query_cong_statistics_in_bits { 6886 u8 opcode[0x10]; 6887 u8 reserved_at_10[0x10]; 6888 6889 u8 reserved_at_20[0x10]; 6890 u8 op_mod[0x10]; 6891 6892 u8 clear[0x1]; 6893 u8 reserved_at_41[0x1f]; 6894 6895 u8 reserved_at_60[0x20]; 6896 }; 6897 6898 struct mlx5_ifc_query_cong_params_out_bits { 6899 u8 status[0x8]; 6900 u8 reserved_at_8[0x18]; 6901 6902 u8 syndrome[0x20]; 6903 6904 u8 reserved_at_40[0x40]; 6905 6906 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 6907 }; 6908 6909 struct mlx5_ifc_query_cong_params_in_bits { 6910 u8 opcode[0x10]; 6911 u8 reserved_at_10[0x10]; 6912 6913 u8 reserved_at_20[0x10]; 6914 u8 op_mod[0x10]; 6915 6916 u8 reserved_at_40[0x1c]; 6917 u8 cong_protocol[0x4]; 6918 6919 u8 reserved_at_60[0x20]; 6920 }; 6921 6922 struct mlx5_ifc_query_adapter_out_bits { 6923 u8 status[0x8]; 6924 u8 reserved_at_8[0x18]; 6925 6926 u8 syndrome[0x20]; 6927 6928 u8 reserved_at_40[0x40]; 6929 6930 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct; 6931 }; 6932 6933 struct mlx5_ifc_query_adapter_in_bits { 6934 u8 opcode[0x10]; 6935 u8 reserved_at_10[0x10]; 6936 6937 u8 reserved_at_20[0x10]; 6938 u8 op_mod[0x10]; 6939 6940 u8 reserved_at_40[0x40]; 6941 }; 6942 6943 struct mlx5_ifc_qp_2rst_out_bits { 6944 u8 status[0x8]; 6945 u8 reserved_at_8[0x18]; 6946 6947 u8 syndrome[0x20]; 6948 6949 u8 reserved_at_40[0x40]; 6950 }; 6951 6952 struct mlx5_ifc_qp_2rst_in_bits { 6953 u8 opcode[0x10]; 6954 u8 uid[0x10]; 6955 6956 u8 reserved_at_20[0x10]; 6957 u8 op_mod[0x10]; 6958 6959 u8 reserved_at_40[0x8]; 6960 u8 qpn[0x18]; 6961 6962 u8 reserved_at_60[0x20]; 6963 }; 6964 6965 struct mlx5_ifc_qp_2err_out_bits { 6966 u8 status[0x8]; 6967 u8 reserved_at_8[0x18]; 6968 6969 u8 syndrome[0x20]; 6970 6971 u8 reserved_at_40[0x40]; 6972 }; 6973 6974 struct mlx5_ifc_qp_2err_in_bits { 6975 u8 opcode[0x10]; 6976 u8 uid[0x10]; 6977 6978 u8 reserved_at_20[0x10]; 6979 u8 op_mod[0x10]; 6980 6981 u8 reserved_at_40[0x8]; 6982 u8 qpn[0x18]; 6983 6984 u8 reserved_at_60[0x20]; 6985 }; 6986 6987 struct mlx5_ifc_page_fault_resume_out_bits { 6988 u8 status[0x8]; 6989 u8 reserved_at_8[0x18]; 6990 6991 u8 syndrome[0x20]; 6992 6993 u8 reserved_at_40[0x40]; 6994 }; 6995 6996 struct mlx5_ifc_page_fault_resume_in_bits { 6997 u8 opcode[0x10]; 6998 u8 reserved_at_10[0x10]; 6999 7000 u8 reserved_at_20[0x10]; 7001 u8 op_mod[0x10]; 7002 7003 u8 error[0x1]; 7004 u8 reserved_at_41[0x4]; 7005 u8 page_fault_type[0x3]; 7006 u8 wq_number[0x18]; 7007 7008 u8 reserved_at_60[0x8]; 7009 u8 token[0x18]; 7010 }; 7011 7012 struct mlx5_ifc_nop_out_bits { 7013 u8 status[0x8]; 7014 u8 reserved_at_8[0x18]; 7015 7016 u8 syndrome[0x20]; 7017 7018 u8 reserved_at_40[0x40]; 7019 }; 7020 7021 struct mlx5_ifc_nop_in_bits { 7022 u8 opcode[0x10]; 7023 u8 reserved_at_10[0x10]; 7024 7025 u8 reserved_at_20[0x10]; 7026 u8 op_mod[0x10]; 7027 7028 u8 reserved_at_40[0x40]; 7029 }; 7030 7031 struct mlx5_ifc_modify_vport_state_out_bits { 7032 u8 status[0x8]; 7033 u8 reserved_at_8[0x18]; 7034 7035 u8 syndrome[0x20]; 7036 7037 u8 reserved_at_40[0x40]; 7038 }; 7039 7040 struct mlx5_ifc_modify_vport_state_in_bits { 7041 u8 opcode[0x10]; 7042 u8 reserved_at_10[0x10]; 7043 7044 u8 reserved_at_20[0x10]; 7045 u8 op_mod[0x10]; 7046 7047 u8 other_vport[0x1]; 7048 u8 reserved_at_41[0xf]; 7049 u8 vport_number[0x10]; 7050 7051 u8 reserved_at_60[0x18]; 7052 u8 admin_state[0x4]; 7053 u8 reserved_at_7c[0x4]; 7054 }; 7055 7056 struct mlx5_ifc_modify_tis_out_bits { 7057 u8 status[0x8]; 7058 u8 reserved_at_8[0x18]; 7059 7060 u8 syndrome[0x20]; 7061 7062 u8 reserved_at_40[0x40]; 7063 }; 7064 7065 struct mlx5_ifc_modify_tis_bitmask_bits { 7066 u8 reserved_at_0[0x20]; 7067 7068 u8 reserved_at_20[0x1d]; 7069 u8 lag_tx_port_affinity[0x1]; 7070 u8 strict_lag_tx_port_affinity[0x1]; 7071 u8 prio[0x1]; 7072 }; 7073 7074 struct mlx5_ifc_modify_tis_in_bits { 7075 u8 opcode[0x10]; 7076 u8 uid[0x10]; 7077 7078 u8 reserved_at_20[0x10]; 7079 u8 op_mod[0x10]; 7080 7081 u8 reserved_at_40[0x8]; 7082 u8 tisn[0x18]; 7083 7084 u8 reserved_at_60[0x20]; 7085 7086 struct mlx5_ifc_modify_tis_bitmask_bits bitmask; 7087 7088 u8 reserved_at_c0[0x40]; 7089 7090 struct mlx5_ifc_tisc_bits ctx; 7091 }; 7092 7093 struct mlx5_ifc_modify_tir_bitmask_bits { 7094 u8 reserved_at_0[0x20]; 7095 7096 u8 reserved_at_20[0x1b]; 7097 u8 self_lb_en[0x1]; 7098 u8 reserved_at_3c[0x1]; 7099 u8 hash[0x1]; 7100 u8 reserved_at_3e[0x1]; 7101 u8 packet_merge[0x1]; 7102 }; 7103 7104 struct mlx5_ifc_modify_tir_out_bits { 7105 u8 status[0x8]; 7106 u8 reserved_at_8[0x18]; 7107 7108 u8 syndrome[0x20]; 7109 7110 u8 reserved_at_40[0x40]; 7111 }; 7112 7113 struct mlx5_ifc_modify_tir_in_bits { 7114 u8 opcode[0x10]; 7115 u8 uid[0x10]; 7116 7117 u8 reserved_at_20[0x10]; 7118 u8 op_mod[0x10]; 7119 7120 u8 reserved_at_40[0x8]; 7121 u8 tirn[0x18]; 7122 7123 u8 reserved_at_60[0x20]; 7124 7125 struct mlx5_ifc_modify_tir_bitmask_bits bitmask; 7126 7127 u8 reserved_at_c0[0x40]; 7128 7129 struct mlx5_ifc_tirc_bits ctx; 7130 }; 7131 7132 struct mlx5_ifc_modify_sq_out_bits { 7133 u8 status[0x8]; 7134 u8 reserved_at_8[0x18]; 7135 7136 u8 syndrome[0x20]; 7137 7138 u8 reserved_at_40[0x40]; 7139 }; 7140 7141 struct mlx5_ifc_modify_sq_in_bits { 7142 u8 opcode[0x10]; 7143 u8 uid[0x10]; 7144 7145 u8 reserved_at_20[0x10]; 7146 u8 op_mod[0x10]; 7147 7148 u8 sq_state[0x4]; 7149 u8 reserved_at_44[0x4]; 7150 u8 sqn[0x18]; 7151 7152 u8 reserved_at_60[0x20]; 7153 7154 u8 modify_bitmask[0x40]; 7155 7156 u8 reserved_at_c0[0x40]; 7157 7158 struct mlx5_ifc_sqc_bits ctx; 7159 }; 7160 7161 struct mlx5_ifc_modify_scheduling_element_out_bits { 7162 u8 status[0x8]; 7163 u8 reserved_at_8[0x18]; 7164 7165 u8 syndrome[0x20]; 7166 7167 u8 reserved_at_40[0x1c0]; 7168 }; 7169 7170 enum { 7171 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1, 7172 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2, 7173 }; 7174 7175 struct mlx5_ifc_modify_scheduling_element_in_bits { 7176 u8 opcode[0x10]; 7177 u8 reserved_at_10[0x10]; 7178 7179 u8 reserved_at_20[0x10]; 7180 u8 op_mod[0x10]; 7181 7182 u8 scheduling_hierarchy[0x8]; 7183 u8 reserved_at_48[0x18]; 7184 7185 u8 scheduling_element_id[0x20]; 7186 7187 u8 reserved_at_80[0x20]; 7188 7189 u8 modify_bitmask[0x20]; 7190 7191 u8 reserved_at_c0[0x40]; 7192 7193 struct mlx5_ifc_scheduling_context_bits scheduling_context; 7194 7195 u8 reserved_at_300[0x100]; 7196 }; 7197 7198 struct mlx5_ifc_modify_rqt_out_bits { 7199 u8 status[0x8]; 7200 u8 reserved_at_8[0x18]; 7201 7202 u8 syndrome[0x20]; 7203 7204 u8 reserved_at_40[0x40]; 7205 }; 7206 7207 struct mlx5_ifc_rqt_bitmask_bits { 7208 u8 reserved_at_0[0x20]; 7209 7210 u8 reserved_at_20[0x1f]; 7211 u8 rqn_list[0x1]; 7212 }; 7213 7214 struct mlx5_ifc_modify_rqt_in_bits { 7215 u8 opcode[0x10]; 7216 u8 uid[0x10]; 7217 7218 u8 reserved_at_20[0x10]; 7219 u8 op_mod[0x10]; 7220 7221 u8 reserved_at_40[0x8]; 7222 u8 rqtn[0x18]; 7223 7224 u8 reserved_at_60[0x20]; 7225 7226 struct mlx5_ifc_rqt_bitmask_bits bitmask; 7227 7228 u8 reserved_at_c0[0x40]; 7229 7230 struct mlx5_ifc_rqtc_bits ctx; 7231 }; 7232 7233 struct mlx5_ifc_modify_rq_out_bits { 7234 u8 status[0x8]; 7235 u8 reserved_at_8[0x18]; 7236 7237 u8 syndrome[0x20]; 7238 7239 u8 reserved_at_40[0x40]; 7240 }; 7241 7242 enum { 7243 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1, 7244 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2, 7245 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3, 7246 }; 7247 7248 struct mlx5_ifc_modify_rq_in_bits { 7249 u8 opcode[0x10]; 7250 u8 uid[0x10]; 7251 7252 u8 reserved_at_20[0x10]; 7253 u8 op_mod[0x10]; 7254 7255 u8 rq_state[0x4]; 7256 u8 reserved_at_44[0x4]; 7257 u8 rqn[0x18]; 7258 7259 u8 reserved_at_60[0x20]; 7260 7261 u8 modify_bitmask[0x40]; 7262 7263 u8 reserved_at_c0[0x40]; 7264 7265 struct mlx5_ifc_rqc_bits ctx; 7266 }; 7267 7268 struct mlx5_ifc_modify_rmp_out_bits { 7269 u8 status[0x8]; 7270 u8 reserved_at_8[0x18]; 7271 7272 u8 syndrome[0x20]; 7273 7274 u8 reserved_at_40[0x40]; 7275 }; 7276 7277 struct mlx5_ifc_rmp_bitmask_bits { 7278 u8 reserved_at_0[0x20]; 7279 7280 u8 reserved_at_20[0x1f]; 7281 u8 lwm[0x1]; 7282 }; 7283 7284 struct mlx5_ifc_modify_rmp_in_bits { 7285 u8 opcode[0x10]; 7286 u8 uid[0x10]; 7287 7288 u8 reserved_at_20[0x10]; 7289 u8 op_mod[0x10]; 7290 7291 u8 rmp_state[0x4]; 7292 u8 reserved_at_44[0x4]; 7293 u8 rmpn[0x18]; 7294 7295 u8 reserved_at_60[0x20]; 7296 7297 struct mlx5_ifc_rmp_bitmask_bits bitmask; 7298 7299 u8 reserved_at_c0[0x40]; 7300 7301 struct mlx5_ifc_rmpc_bits ctx; 7302 }; 7303 7304 struct mlx5_ifc_modify_nic_vport_context_out_bits { 7305 u8 status[0x8]; 7306 u8 reserved_at_8[0x18]; 7307 7308 u8 syndrome[0x20]; 7309 7310 u8 reserved_at_40[0x40]; 7311 }; 7312 7313 struct mlx5_ifc_modify_nic_vport_field_select_bits { 7314 u8 reserved_at_0[0x12]; 7315 u8 affiliation[0x1]; 7316 u8 reserved_at_13[0x1]; 7317 u8 disable_uc_local_lb[0x1]; 7318 u8 disable_mc_local_lb[0x1]; 7319 u8 node_guid[0x1]; 7320 u8 port_guid[0x1]; 7321 u8 min_inline[0x1]; 7322 u8 mtu[0x1]; 7323 u8 change_event[0x1]; 7324 u8 promisc[0x1]; 7325 u8 permanent_address[0x1]; 7326 u8 addresses_list[0x1]; 7327 u8 roce_en[0x1]; 7328 u8 reserved_at_1f[0x1]; 7329 }; 7330 7331 struct mlx5_ifc_modify_nic_vport_context_in_bits { 7332 u8 opcode[0x10]; 7333 u8 reserved_at_10[0x10]; 7334 7335 u8 reserved_at_20[0x10]; 7336 u8 op_mod[0x10]; 7337 7338 u8 other_vport[0x1]; 7339 u8 reserved_at_41[0xf]; 7340 u8 vport_number[0x10]; 7341 7342 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select; 7343 7344 u8 reserved_at_80[0x780]; 7345 7346 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 7347 }; 7348 7349 struct mlx5_ifc_modify_hca_vport_context_out_bits { 7350 u8 status[0x8]; 7351 u8 reserved_at_8[0x18]; 7352 7353 u8 syndrome[0x20]; 7354 7355 u8 reserved_at_40[0x40]; 7356 }; 7357 7358 struct mlx5_ifc_modify_hca_vport_context_in_bits { 7359 u8 opcode[0x10]; 7360 u8 reserved_at_10[0x10]; 7361 7362 u8 reserved_at_20[0x10]; 7363 u8 op_mod[0x10]; 7364 7365 u8 other_vport[0x1]; 7366 u8 reserved_at_41[0xb]; 7367 u8 port_num[0x4]; 7368 u8 vport_number[0x10]; 7369 7370 u8 reserved_at_60[0x20]; 7371 7372 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 7373 }; 7374 7375 struct mlx5_ifc_modify_cq_out_bits { 7376 u8 status[0x8]; 7377 u8 reserved_at_8[0x18]; 7378 7379 u8 syndrome[0x20]; 7380 7381 u8 reserved_at_40[0x40]; 7382 }; 7383 7384 enum { 7385 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0, 7386 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1, 7387 }; 7388 7389 struct mlx5_ifc_modify_cq_in_bits { 7390 u8 opcode[0x10]; 7391 u8 uid[0x10]; 7392 7393 u8 reserved_at_20[0x10]; 7394 u8 op_mod[0x10]; 7395 7396 u8 reserved_at_40[0x8]; 7397 u8 cqn[0x18]; 7398 7399 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select; 7400 7401 struct mlx5_ifc_cqc_bits cq_context; 7402 7403 u8 reserved_at_280[0x60]; 7404 7405 u8 cq_umem_valid[0x1]; 7406 u8 reserved_at_2e1[0x1f]; 7407 7408 u8 reserved_at_300[0x580]; 7409 7410 u8 pas[][0x40]; 7411 }; 7412 7413 struct mlx5_ifc_modify_cong_status_out_bits { 7414 u8 status[0x8]; 7415 u8 reserved_at_8[0x18]; 7416 7417 u8 syndrome[0x20]; 7418 7419 u8 reserved_at_40[0x40]; 7420 }; 7421 7422 struct mlx5_ifc_modify_cong_status_in_bits { 7423 u8 opcode[0x10]; 7424 u8 reserved_at_10[0x10]; 7425 7426 u8 reserved_at_20[0x10]; 7427 u8 op_mod[0x10]; 7428 7429 u8 reserved_at_40[0x18]; 7430 u8 priority[0x4]; 7431 u8 cong_protocol[0x4]; 7432 7433 u8 enable[0x1]; 7434 u8 tag_enable[0x1]; 7435 u8 reserved_at_62[0x1e]; 7436 }; 7437 7438 struct mlx5_ifc_modify_cong_params_out_bits { 7439 u8 status[0x8]; 7440 u8 reserved_at_8[0x18]; 7441 7442 u8 syndrome[0x20]; 7443 7444 u8 reserved_at_40[0x40]; 7445 }; 7446 7447 struct mlx5_ifc_modify_cong_params_in_bits { 7448 u8 opcode[0x10]; 7449 u8 reserved_at_10[0x10]; 7450 7451 u8 reserved_at_20[0x10]; 7452 u8 op_mod[0x10]; 7453 7454 u8 reserved_at_40[0x1c]; 7455 u8 cong_protocol[0x4]; 7456 7457 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select; 7458 7459 u8 reserved_at_80[0x80]; 7460 7461 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 7462 }; 7463 7464 struct mlx5_ifc_manage_pages_out_bits { 7465 u8 status[0x8]; 7466 u8 reserved_at_8[0x18]; 7467 7468 u8 syndrome[0x20]; 7469 7470 u8 output_num_entries[0x20]; 7471 7472 u8 reserved_at_60[0x20]; 7473 7474 u8 pas[][0x40]; 7475 }; 7476 7477 enum { 7478 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL = 0x0, 7479 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS = 0x1, 7480 MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES = 0x2, 7481 }; 7482 7483 struct mlx5_ifc_manage_pages_in_bits { 7484 u8 opcode[0x10]; 7485 u8 reserved_at_10[0x10]; 7486 7487 u8 reserved_at_20[0x10]; 7488 u8 op_mod[0x10]; 7489 7490 u8 embedded_cpu_function[0x1]; 7491 u8 reserved_at_41[0xf]; 7492 u8 function_id[0x10]; 7493 7494 u8 input_num_entries[0x20]; 7495 7496 u8 pas[][0x40]; 7497 }; 7498 7499 struct mlx5_ifc_mad_ifc_out_bits { 7500 u8 status[0x8]; 7501 u8 reserved_at_8[0x18]; 7502 7503 u8 syndrome[0x20]; 7504 7505 u8 reserved_at_40[0x40]; 7506 7507 u8 response_mad_packet[256][0x8]; 7508 }; 7509 7510 struct mlx5_ifc_mad_ifc_in_bits { 7511 u8 opcode[0x10]; 7512 u8 reserved_at_10[0x10]; 7513 7514 u8 reserved_at_20[0x10]; 7515 u8 op_mod[0x10]; 7516 7517 u8 remote_lid[0x10]; 7518 u8 reserved_at_50[0x8]; 7519 u8 port[0x8]; 7520 7521 u8 reserved_at_60[0x20]; 7522 7523 u8 mad[256][0x8]; 7524 }; 7525 7526 struct mlx5_ifc_init_hca_out_bits { 7527 u8 status[0x8]; 7528 u8 reserved_at_8[0x18]; 7529 7530 u8 syndrome[0x20]; 7531 7532 u8 reserved_at_40[0x40]; 7533 }; 7534 7535 struct mlx5_ifc_init_hca_in_bits { 7536 u8 opcode[0x10]; 7537 u8 reserved_at_10[0x10]; 7538 7539 u8 reserved_at_20[0x10]; 7540 u8 op_mod[0x10]; 7541 7542 u8 reserved_at_40[0x20]; 7543 7544 u8 reserved_at_60[0x2]; 7545 u8 sw_vhca_id[0xe]; 7546 u8 reserved_at_70[0x10]; 7547 7548 u8 sw_owner_id[4][0x20]; 7549 }; 7550 7551 struct mlx5_ifc_init2rtr_qp_out_bits { 7552 u8 status[0x8]; 7553 u8 reserved_at_8[0x18]; 7554 7555 u8 syndrome[0x20]; 7556 7557 u8 reserved_at_40[0x20]; 7558 u8 ece[0x20]; 7559 }; 7560 7561 struct mlx5_ifc_init2rtr_qp_in_bits { 7562 u8 opcode[0x10]; 7563 u8 uid[0x10]; 7564 7565 u8 reserved_at_20[0x10]; 7566 u8 op_mod[0x10]; 7567 7568 u8 reserved_at_40[0x8]; 7569 u8 qpn[0x18]; 7570 7571 u8 reserved_at_60[0x20]; 7572 7573 u8 opt_param_mask[0x20]; 7574 7575 u8 ece[0x20]; 7576 7577 struct mlx5_ifc_qpc_bits qpc; 7578 7579 u8 reserved_at_800[0x80]; 7580 }; 7581 7582 struct mlx5_ifc_init2init_qp_out_bits { 7583 u8 status[0x8]; 7584 u8 reserved_at_8[0x18]; 7585 7586 u8 syndrome[0x20]; 7587 7588 u8 reserved_at_40[0x20]; 7589 u8 ece[0x20]; 7590 }; 7591 7592 struct mlx5_ifc_init2init_qp_in_bits { 7593 u8 opcode[0x10]; 7594 u8 uid[0x10]; 7595 7596 u8 reserved_at_20[0x10]; 7597 u8 op_mod[0x10]; 7598 7599 u8 reserved_at_40[0x8]; 7600 u8 qpn[0x18]; 7601 7602 u8 reserved_at_60[0x20]; 7603 7604 u8 opt_param_mask[0x20]; 7605 7606 u8 ece[0x20]; 7607 7608 struct mlx5_ifc_qpc_bits qpc; 7609 7610 u8 reserved_at_800[0x80]; 7611 }; 7612 7613 struct mlx5_ifc_get_dropped_packet_log_out_bits { 7614 u8 status[0x8]; 7615 u8 reserved_at_8[0x18]; 7616 7617 u8 syndrome[0x20]; 7618 7619 u8 reserved_at_40[0x40]; 7620 7621 u8 packet_headers_log[128][0x8]; 7622 7623 u8 packet_syndrome[64][0x8]; 7624 }; 7625 7626 struct mlx5_ifc_get_dropped_packet_log_in_bits { 7627 u8 opcode[0x10]; 7628 u8 reserved_at_10[0x10]; 7629 7630 u8 reserved_at_20[0x10]; 7631 u8 op_mod[0x10]; 7632 7633 u8 reserved_at_40[0x40]; 7634 }; 7635 7636 struct mlx5_ifc_gen_eqe_in_bits { 7637 u8 opcode[0x10]; 7638 u8 reserved_at_10[0x10]; 7639 7640 u8 reserved_at_20[0x10]; 7641 u8 op_mod[0x10]; 7642 7643 u8 reserved_at_40[0x18]; 7644 u8 eq_number[0x8]; 7645 7646 u8 reserved_at_60[0x20]; 7647 7648 u8 eqe[64][0x8]; 7649 }; 7650 7651 struct mlx5_ifc_gen_eq_out_bits { 7652 u8 status[0x8]; 7653 u8 reserved_at_8[0x18]; 7654 7655 u8 syndrome[0x20]; 7656 7657 u8 reserved_at_40[0x40]; 7658 }; 7659 7660 struct mlx5_ifc_enable_hca_out_bits { 7661 u8 status[0x8]; 7662 u8 reserved_at_8[0x18]; 7663 7664 u8 syndrome[0x20]; 7665 7666 u8 reserved_at_40[0x20]; 7667 }; 7668 7669 struct mlx5_ifc_enable_hca_in_bits { 7670 u8 opcode[0x10]; 7671 u8 reserved_at_10[0x10]; 7672 7673 u8 reserved_at_20[0x10]; 7674 u8 op_mod[0x10]; 7675 7676 u8 embedded_cpu_function[0x1]; 7677 u8 reserved_at_41[0xf]; 7678 u8 function_id[0x10]; 7679 7680 u8 reserved_at_60[0x20]; 7681 }; 7682 7683 struct mlx5_ifc_drain_dct_out_bits { 7684 u8 status[0x8]; 7685 u8 reserved_at_8[0x18]; 7686 7687 u8 syndrome[0x20]; 7688 7689 u8 reserved_at_40[0x40]; 7690 }; 7691 7692 struct mlx5_ifc_drain_dct_in_bits { 7693 u8 opcode[0x10]; 7694 u8 uid[0x10]; 7695 7696 u8 reserved_at_20[0x10]; 7697 u8 op_mod[0x10]; 7698 7699 u8 reserved_at_40[0x8]; 7700 u8 dctn[0x18]; 7701 7702 u8 reserved_at_60[0x20]; 7703 }; 7704 7705 struct mlx5_ifc_disable_hca_out_bits { 7706 u8 status[0x8]; 7707 u8 reserved_at_8[0x18]; 7708 7709 u8 syndrome[0x20]; 7710 7711 u8 reserved_at_40[0x20]; 7712 }; 7713 7714 struct mlx5_ifc_disable_hca_in_bits { 7715 u8 opcode[0x10]; 7716 u8 reserved_at_10[0x10]; 7717 7718 u8 reserved_at_20[0x10]; 7719 u8 op_mod[0x10]; 7720 7721 u8 embedded_cpu_function[0x1]; 7722 u8 reserved_at_41[0xf]; 7723 u8 function_id[0x10]; 7724 7725 u8 reserved_at_60[0x20]; 7726 }; 7727 7728 struct mlx5_ifc_detach_from_mcg_out_bits { 7729 u8 status[0x8]; 7730 u8 reserved_at_8[0x18]; 7731 7732 u8 syndrome[0x20]; 7733 7734 u8 reserved_at_40[0x40]; 7735 }; 7736 7737 struct mlx5_ifc_detach_from_mcg_in_bits { 7738 u8 opcode[0x10]; 7739 u8 uid[0x10]; 7740 7741 u8 reserved_at_20[0x10]; 7742 u8 op_mod[0x10]; 7743 7744 u8 reserved_at_40[0x8]; 7745 u8 qpn[0x18]; 7746 7747 u8 reserved_at_60[0x20]; 7748 7749 u8 multicast_gid[16][0x8]; 7750 }; 7751 7752 struct mlx5_ifc_destroy_xrq_out_bits { 7753 u8 status[0x8]; 7754 u8 reserved_at_8[0x18]; 7755 7756 u8 syndrome[0x20]; 7757 7758 u8 reserved_at_40[0x40]; 7759 }; 7760 7761 struct mlx5_ifc_destroy_xrq_in_bits { 7762 u8 opcode[0x10]; 7763 u8 uid[0x10]; 7764 7765 u8 reserved_at_20[0x10]; 7766 u8 op_mod[0x10]; 7767 7768 u8 reserved_at_40[0x8]; 7769 u8 xrqn[0x18]; 7770 7771 u8 reserved_at_60[0x20]; 7772 }; 7773 7774 struct mlx5_ifc_destroy_xrc_srq_out_bits { 7775 u8 status[0x8]; 7776 u8 reserved_at_8[0x18]; 7777 7778 u8 syndrome[0x20]; 7779 7780 u8 reserved_at_40[0x40]; 7781 }; 7782 7783 struct mlx5_ifc_destroy_xrc_srq_in_bits { 7784 u8 opcode[0x10]; 7785 u8 uid[0x10]; 7786 7787 u8 reserved_at_20[0x10]; 7788 u8 op_mod[0x10]; 7789 7790 u8 reserved_at_40[0x8]; 7791 u8 xrc_srqn[0x18]; 7792 7793 u8 reserved_at_60[0x20]; 7794 }; 7795 7796 struct mlx5_ifc_destroy_tis_out_bits { 7797 u8 status[0x8]; 7798 u8 reserved_at_8[0x18]; 7799 7800 u8 syndrome[0x20]; 7801 7802 u8 reserved_at_40[0x40]; 7803 }; 7804 7805 struct mlx5_ifc_destroy_tis_in_bits { 7806 u8 opcode[0x10]; 7807 u8 uid[0x10]; 7808 7809 u8 reserved_at_20[0x10]; 7810 u8 op_mod[0x10]; 7811 7812 u8 reserved_at_40[0x8]; 7813 u8 tisn[0x18]; 7814 7815 u8 reserved_at_60[0x20]; 7816 }; 7817 7818 struct mlx5_ifc_destroy_tir_out_bits { 7819 u8 status[0x8]; 7820 u8 reserved_at_8[0x18]; 7821 7822 u8 syndrome[0x20]; 7823 7824 u8 reserved_at_40[0x40]; 7825 }; 7826 7827 struct mlx5_ifc_destroy_tir_in_bits { 7828 u8 opcode[0x10]; 7829 u8 uid[0x10]; 7830 7831 u8 reserved_at_20[0x10]; 7832 u8 op_mod[0x10]; 7833 7834 u8 reserved_at_40[0x8]; 7835 u8 tirn[0x18]; 7836 7837 u8 reserved_at_60[0x20]; 7838 }; 7839 7840 struct mlx5_ifc_destroy_srq_out_bits { 7841 u8 status[0x8]; 7842 u8 reserved_at_8[0x18]; 7843 7844 u8 syndrome[0x20]; 7845 7846 u8 reserved_at_40[0x40]; 7847 }; 7848 7849 struct mlx5_ifc_destroy_srq_in_bits { 7850 u8 opcode[0x10]; 7851 u8 uid[0x10]; 7852 7853 u8 reserved_at_20[0x10]; 7854 u8 op_mod[0x10]; 7855 7856 u8 reserved_at_40[0x8]; 7857 u8 srqn[0x18]; 7858 7859 u8 reserved_at_60[0x20]; 7860 }; 7861 7862 struct mlx5_ifc_destroy_sq_out_bits { 7863 u8 status[0x8]; 7864 u8 reserved_at_8[0x18]; 7865 7866 u8 syndrome[0x20]; 7867 7868 u8 reserved_at_40[0x40]; 7869 }; 7870 7871 struct mlx5_ifc_destroy_sq_in_bits { 7872 u8 opcode[0x10]; 7873 u8 uid[0x10]; 7874 7875 u8 reserved_at_20[0x10]; 7876 u8 op_mod[0x10]; 7877 7878 u8 reserved_at_40[0x8]; 7879 u8 sqn[0x18]; 7880 7881 u8 reserved_at_60[0x20]; 7882 }; 7883 7884 struct mlx5_ifc_destroy_scheduling_element_out_bits { 7885 u8 status[0x8]; 7886 u8 reserved_at_8[0x18]; 7887 7888 u8 syndrome[0x20]; 7889 7890 u8 reserved_at_40[0x1c0]; 7891 }; 7892 7893 struct mlx5_ifc_destroy_scheduling_element_in_bits { 7894 u8 opcode[0x10]; 7895 u8 reserved_at_10[0x10]; 7896 7897 u8 reserved_at_20[0x10]; 7898 u8 op_mod[0x10]; 7899 7900 u8 scheduling_hierarchy[0x8]; 7901 u8 reserved_at_48[0x18]; 7902 7903 u8 scheduling_element_id[0x20]; 7904 7905 u8 reserved_at_80[0x180]; 7906 }; 7907 7908 struct mlx5_ifc_destroy_rqt_out_bits { 7909 u8 status[0x8]; 7910 u8 reserved_at_8[0x18]; 7911 7912 u8 syndrome[0x20]; 7913 7914 u8 reserved_at_40[0x40]; 7915 }; 7916 7917 struct mlx5_ifc_destroy_rqt_in_bits { 7918 u8 opcode[0x10]; 7919 u8 uid[0x10]; 7920 7921 u8 reserved_at_20[0x10]; 7922 u8 op_mod[0x10]; 7923 7924 u8 reserved_at_40[0x8]; 7925 u8 rqtn[0x18]; 7926 7927 u8 reserved_at_60[0x20]; 7928 }; 7929 7930 struct mlx5_ifc_destroy_rq_out_bits { 7931 u8 status[0x8]; 7932 u8 reserved_at_8[0x18]; 7933 7934 u8 syndrome[0x20]; 7935 7936 u8 reserved_at_40[0x40]; 7937 }; 7938 7939 struct mlx5_ifc_destroy_rq_in_bits { 7940 u8 opcode[0x10]; 7941 u8 uid[0x10]; 7942 7943 u8 reserved_at_20[0x10]; 7944 u8 op_mod[0x10]; 7945 7946 u8 reserved_at_40[0x8]; 7947 u8 rqn[0x18]; 7948 7949 u8 reserved_at_60[0x20]; 7950 }; 7951 7952 struct mlx5_ifc_set_delay_drop_params_in_bits { 7953 u8 opcode[0x10]; 7954 u8 reserved_at_10[0x10]; 7955 7956 u8 reserved_at_20[0x10]; 7957 u8 op_mod[0x10]; 7958 7959 u8 reserved_at_40[0x20]; 7960 7961 u8 reserved_at_60[0x10]; 7962 u8 delay_drop_timeout[0x10]; 7963 }; 7964 7965 struct mlx5_ifc_set_delay_drop_params_out_bits { 7966 u8 status[0x8]; 7967 u8 reserved_at_8[0x18]; 7968 7969 u8 syndrome[0x20]; 7970 7971 u8 reserved_at_40[0x40]; 7972 }; 7973 7974 struct mlx5_ifc_destroy_rmp_out_bits { 7975 u8 status[0x8]; 7976 u8 reserved_at_8[0x18]; 7977 7978 u8 syndrome[0x20]; 7979 7980 u8 reserved_at_40[0x40]; 7981 }; 7982 7983 struct mlx5_ifc_destroy_rmp_in_bits { 7984 u8 opcode[0x10]; 7985 u8 uid[0x10]; 7986 7987 u8 reserved_at_20[0x10]; 7988 u8 op_mod[0x10]; 7989 7990 u8 reserved_at_40[0x8]; 7991 u8 rmpn[0x18]; 7992 7993 u8 reserved_at_60[0x20]; 7994 }; 7995 7996 struct mlx5_ifc_destroy_qp_out_bits { 7997 u8 status[0x8]; 7998 u8 reserved_at_8[0x18]; 7999 8000 u8 syndrome[0x20]; 8001 8002 u8 reserved_at_40[0x40]; 8003 }; 8004 8005 struct mlx5_ifc_destroy_qp_in_bits { 8006 u8 opcode[0x10]; 8007 u8 uid[0x10]; 8008 8009 u8 reserved_at_20[0x10]; 8010 u8 op_mod[0x10]; 8011 8012 u8 reserved_at_40[0x8]; 8013 u8 qpn[0x18]; 8014 8015 u8 reserved_at_60[0x20]; 8016 }; 8017 8018 struct mlx5_ifc_destroy_psv_out_bits { 8019 u8 status[0x8]; 8020 u8 reserved_at_8[0x18]; 8021 8022 u8 syndrome[0x20]; 8023 8024 u8 reserved_at_40[0x40]; 8025 }; 8026 8027 struct mlx5_ifc_destroy_psv_in_bits { 8028 u8 opcode[0x10]; 8029 u8 reserved_at_10[0x10]; 8030 8031 u8 reserved_at_20[0x10]; 8032 u8 op_mod[0x10]; 8033 8034 u8 reserved_at_40[0x8]; 8035 u8 psvn[0x18]; 8036 8037 u8 reserved_at_60[0x20]; 8038 }; 8039 8040 struct mlx5_ifc_destroy_mkey_out_bits { 8041 u8 status[0x8]; 8042 u8 reserved_at_8[0x18]; 8043 8044 u8 syndrome[0x20]; 8045 8046 u8 reserved_at_40[0x40]; 8047 }; 8048 8049 struct mlx5_ifc_destroy_mkey_in_bits { 8050 u8 opcode[0x10]; 8051 u8 uid[0x10]; 8052 8053 u8 reserved_at_20[0x10]; 8054 u8 op_mod[0x10]; 8055 8056 u8 reserved_at_40[0x8]; 8057 u8 mkey_index[0x18]; 8058 8059 u8 reserved_at_60[0x20]; 8060 }; 8061 8062 struct mlx5_ifc_destroy_flow_table_out_bits { 8063 u8 status[0x8]; 8064 u8 reserved_at_8[0x18]; 8065 8066 u8 syndrome[0x20]; 8067 8068 u8 reserved_at_40[0x40]; 8069 }; 8070 8071 struct mlx5_ifc_destroy_flow_table_in_bits { 8072 u8 opcode[0x10]; 8073 u8 reserved_at_10[0x10]; 8074 8075 u8 reserved_at_20[0x10]; 8076 u8 op_mod[0x10]; 8077 8078 u8 other_vport[0x1]; 8079 u8 reserved_at_41[0xf]; 8080 u8 vport_number[0x10]; 8081 8082 u8 reserved_at_60[0x20]; 8083 8084 u8 table_type[0x8]; 8085 u8 reserved_at_88[0x18]; 8086 8087 u8 reserved_at_a0[0x8]; 8088 u8 table_id[0x18]; 8089 8090 u8 reserved_at_c0[0x140]; 8091 }; 8092 8093 struct mlx5_ifc_destroy_flow_group_out_bits { 8094 u8 status[0x8]; 8095 u8 reserved_at_8[0x18]; 8096 8097 u8 syndrome[0x20]; 8098 8099 u8 reserved_at_40[0x40]; 8100 }; 8101 8102 struct mlx5_ifc_destroy_flow_group_in_bits { 8103 u8 opcode[0x10]; 8104 u8 reserved_at_10[0x10]; 8105 8106 u8 reserved_at_20[0x10]; 8107 u8 op_mod[0x10]; 8108 8109 u8 other_vport[0x1]; 8110 u8 reserved_at_41[0xf]; 8111 u8 vport_number[0x10]; 8112 8113 u8 reserved_at_60[0x20]; 8114 8115 u8 table_type[0x8]; 8116 u8 reserved_at_88[0x18]; 8117 8118 u8 reserved_at_a0[0x8]; 8119 u8 table_id[0x18]; 8120 8121 u8 group_id[0x20]; 8122 8123 u8 reserved_at_e0[0x120]; 8124 }; 8125 8126 struct mlx5_ifc_destroy_eq_out_bits { 8127 u8 status[0x8]; 8128 u8 reserved_at_8[0x18]; 8129 8130 u8 syndrome[0x20]; 8131 8132 u8 reserved_at_40[0x40]; 8133 }; 8134 8135 struct mlx5_ifc_destroy_eq_in_bits { 8136 u8 opcode[0x10]; 8137 u8 reserved_at_10[0x10]; 8138 8139 u8 reserved_at_20[0x10]; 8140 u8 op_mod[0x10]; 8141 8142 u8 reserved_at_40[0x18]; 8143 u8 eq_number[0x8]; 8144 8145 u8 reserved_at_60[0x20]; 8146 }; 8147 8148 struct mlx5_ifc_destroy_dct_out_bits { 8149 u8 status[0x8]; 8150 u8 reserved_at_8[0x18]; 8151 8152 u8 syndrome[0x20]; 8153 8154 u8 reserved_at_40[0x40]; 8155 }; 8156 8157 struct mlx5_ifc_destroy_dct_in_bits { 8158 u8 opcode[0x10]; 8159 u8 uid[0x10]; 8160 8161 u8 reserved_at_20[0x10]; 8162 u8 op_mod[0x10]; 8163 8164 u8 reserved_at_40[0x8]; 8165 u8 dctn[0x18]; 8166 8167 u8 reserved_at_60[0x20]; 8168 }; 8169 8170 struct mlx5_ifc_destroy_cq_out_bits { 8171 u8 status[0x8]; 8172 u8 reserved_at_8[0x18]; 8173 8174 u8 syndrome[0x20]; 8175 8176 u8 reserved_at_40[0x40]; 8177 }; 8178 8179 struct mlx5_ifc_destroy_cq_in_bits { 8180 u8 opcode[0x10]; 8181 u8 uid[0x10]; 8182 8183 u8 reserved_at_20[0x10]; 8184 u8 op_mod[0x10]; 8185 8186 u8 reserved_at_40[0x8]; 8187 u8 cqn[0x18]; 8188 8189 u8 reserved_at_60[0x20]; 8190 }; 8191 8192 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits { 8193 u8 status[0x8]; 8194 u8 reserved_at_8[0x18]; 8195 8196 u8 syndrome[0x20]; 8197 8198 u8 reserved_at_40[0x40]; 8199 }; 8200 8201 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits { 8202 u8 opcode[0x10]; 8203 u8 reserved_at_10[0x10]; 8204 8205 u8 reserved_at_20[0x10]; 8206 u8 op_mod[0x10]; 8207 8208 u8 reserved_at_40[0x20]; 8209 8210 u8 reserved_at_60[0x10]; 8211 u8 vxlan_udp_port[0x10]; 8212 }; 8213 8214 struct mlx5_ifc_delete_l2_table_entry_out_bits { 8215 u8 status[0x8]; 8216 u8 reserved_at_8[0x18]; 8217 8218 u8 syndrome[0x20]; 8219 8220 u8 reserved_at_40[0x40]; 8221 }; 8222 8223 struct mlx5_ifc_delete_l2_table_entry_in_bits { 8224 u8 opcode[0x10]; 8225 u8 reserved_at_10[0x10]; 8226 8227 u8 reserved_at_20[0x10]; 8228 u8 op_mod[0x10]; 8229 8230 u8 reserved_at_40[0x60]; 8231 8232 u8 reserved_at_a0[0x8]; 8233 u8 table_index[0x18]; 8234 8235 u8 reserved_at_c0[0x140]; 8236 }; 8237 8238 struct mlx5_ifc_delete_fte_out_bits { 8239 u8 status[0x8]; 8240 u8 reserved_at_8[0x18]; 8241 8242 u8 syndrome[0x20]; 8243 8244 u8 reserved_at_40[0x40]; 8245 }; 8246 8247 struct mlx5_ifc_delete_fte_in_bits { 8248 u8 opcode[0x10]; 8249 u8 reserved_at_10[0x10]; 8250 8251 u8 reserved_at_20[0x10]; 8252 u8 op_mod[0x10]; 8253 8254 u8 other_vport[0x1]; 8255 u8 reserved_at_41[0xf]; 8256 u8 vport_number[0x10]; 8257 8258 u8 reserved_at_60[0x20]; 8259 8260 u8 table_type[0x8]; 8261 u8 reserved_at_88[0x18]; 8262 8263 u8 reserved_at_a0[0x8]; 8264 u8 table_id[0x18]; 8265 8266 u8 reserved_at_c0[0x40]; 8267 8268 u8 flow_index[0x20]; 8269 8270 u8 reserved_at_120[0xe0]; 8271 }; 8272 8273 struct mlx5_ifc_dealloc_xrcd_out_bits { 8274 u8 status[0x8]; 8275 u8 reserved_at_8[0x18]; 8276 8277 u8 syndrome[0x20]; 8278 8279 u8 reserved_at_40[0x40]; 8280 }; 8281 8282 struct mlx5_ifc_dealloc_xrcd_in_bits { 8283 u8 opcode[0x10]; 8284 u8 uid[0x10]; 8285 8286 u8 reserved_at_20[0x10]; 8287 u8 op_mod[0x10]; 8288 8289 u8 reserved_at_40[0x8]; 8290 u8 xrcd[0x18]; 8291 8292 u8 reserved_at_60[0x20]; 8293 }; 8294 8295 struct mlx5_ifc_dealloc_uar_out_bits { 8296 u8 status[0x8]; 8297 u8 reserved_at_8[0x18]; 8298 8299 u8 syndrome[0x20]; 8300 8301 u8 reserved_at_40[0x40]; 8302 }; 8303 8304 struct mlx5_ifc_dealloc_uar_in_bits { 8305 u8 opcode[0x10]; 8306 u8 uid[0x10]; 8307 8308 u8 reserved_at_20[0x10]; 8309 u8 op_mod[0x10]; 8310 8311 u8 reserved_at_40[0x8]; 8312 u8 uar[0x18]; 8313 8314 u8 reserved_at_60[0x20]; 8315 }; 8316 8317 struct mlx5_ifc_dealloc_transport_domain_out_bits { 8318 u8 status[0x8]; 8319 u8 reserved_at_8[0x18]; 8320 8321 u8 syndrome[0x20]; 8322 8323 u8 reserved_at_40[0x40]; 8324 }; 8325 8326 struct mlx5_ifc_dealloc_transport_domain_in_bits { 8327 u8 opcode[0x10]; 8328 u8 uid[0x10]; 8329 8330 u8 reserved_at_20[0x10]; 8331 u8 op_mod[0x10]; 8332 8333 u8 reserved_at_40[0x8]; 8334 u8 transport_domain[0x18]; 8335 8336 u8 reserved_at_60[0x20]; 8337 }; 8338 8339 struct mlx5_ifc_dealloc_q_counter_out_bits { 8340 u8 status[0x8]; 8341 u8 reserved_at_8[0x18]; 8342 8343 u8 syndrome[0x20]; 8344 8345 u8 reserved_at_40[0x40]; 8346 }; 8347 8348 struct mlx5_ifc_dealloc_q_counter_in_bits { 8349 u8 opcode[0x10]; 8350 u8 reserved_at_10[0x10]; 8351 8352 u8 reserved_at_20[0x10]; 8353 u8 op_mod[0x10]; 8354 8355 u8 reserved_at_40[0x18]; 8356 u8 counter_set_id[0x8]; 8357 8358 u8 reserved_at_60[0x20]; 8359 }; 8360 8361 struct mlx5_ifc_dealloc_pd_out_bits { 8362 u8 status[0x8]; 8363 u8 reserved_at_8[0x18]; 8364 8365 u8 syndrome[0x20]; 8366 8367 u8 reserved_at_40[0x40]; 8368 }; 8369 8370 struct mlx5_ifc_dealloc_pd_in_bits { 8371 u8 opcode[0x10]; 8372 u8 uid[0x10]; 8373 8374 u8 reserved_at_20[0x10]; 8375 u8 op_mod[0x10]; 8376 8377 u8 reserved_at_40[0x8]; 8378 u8 pd[0x18]; 8379 8380 u8 reserved_at_60[0x20]; 8381 }; 8382 8383 struct mlx5_ifc_dealloc_flow_counter_out_bits { 8384 u8 status[0x8]; 8385 u8 reserved_at_8[0x18]; 8386 8387 u8 syndrome[0x20]; 8388 8389 u8 reserved_at_40[0x40]; 8390 }; 8391 8392 struct mlx5_ifc_dealloc_flow_counter_in_bits { 8393 u8 opcode[0x10]; 8394 u8 reserved_at_10[0x10]; 8395 8396 u8 reserved_at_20[0x10]; 8397 u8 op_mod[0x10]; 8398 8399 u8 flow_counter_id[0x20]; 8400 8401 u8 reserved_at_60[0x20]; 8402 }; 8403 8404 struct mlx5_ifc_create_xrq_out_bits { 8405 u8 status[0x8]; 8406 u8 reserved_at_8[0x18]; 8407 8408 u8 syndrome[0x20]; 8409 8410 u8 reserved_at_40[0x8]; 8411 u8 xrqn[0x18]; 8412 8413 u8 reserved_at_60[0x20]; 8414 }; 8415 8416 struct mlx5_ifc_create_xrq_in_bits { 8417 u8 opcode[0x10]; 8418 u8 uid[0x10]; 8419 8420 u8 reserved_at_20[0x10]; 8421 u8 op_mod[0x10]; 8422 8423 u8 reserved_at_40[0x40]; 8424 8425 struct mlx5_ifc_xrqc_bits xrq_context; 8426 }; 8427 8428 struct mlx5_ifc_create_xrc_srq_out_bits { 8429 u8 status[0x8]; 8430 u8 reserved_at_8[0x18]; 8431 8432 u8 syndrome[0x20]; 8433 8434 u8 reserved_at_40[0x8]; 8435 u8 xrc_srqn[0x18]; 8436 8437 u8 reserved_at_60[0x20]; 8438 }; 8439 8440 struct mlx5_ifc_create_xrc_srq_in_bits { 8441 u8 opcode[0x10]; 8442 u8 uid[0x10]; 8443 8444 u8 reserved_at_20[0x10]; 8445 u8 op_mod[0x10]; 8446 8447 u8 reserved_at_40[0x40]; 8448 8449 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 8450 8451 u8 reserved_at_280[0x60]; 8452 8453 u8 xrc_srq_umem_valid[0x1]; 8454 u8 reserved_at_2e1[0x1f]; 8455 8456 u8 reserved_at_300[0x580]; 8457 8458 u8 pas[][0x40]; 8459 }; 8460 8461 struct mlx5_ifc_create_tis_out_bits { 8462 u8 status[0x8]; 8463 u8 reserved_at_8[0x18]; 8464 8465 u8 syndrome[0x20]; 8466 8467 u8 reserved_at_40[0x8]; 8468 u8 tisn[0x18]; 8469 8470 u8 reserved_at_60[0x20]; 8471 }; 8472 8473 struct mlx5_ifc_create_tis_in_bits { 8474 u8 opcode[0x10]; 8475 u8 uid[0x10]; 8476 8477 u8 reserved_at_20[0x10]; 8478 u8 op_mod[0x10]; 8479 8480 u8 reserved_at_40[0xc0]; 8481 8482 struct mlx5_ifc_tisc_bits ctx; 8483 }; 8484 8485 struct mlx5_ifc_create_tir_out_bits { 8486 u8 status[0x8]; 8487 u8 icm_address_63_40[0x18]; 8488 8489 u8 syndrome[0x20]; 8490 8491 u8 icm_address_39_32[0x8]; 8492 u8 tirn[0x18]; 8493 8494 u8 icm_address_31_0[0x20]; 8495 }; 8496 8497 struct mlx5_ifc_create_tir_in_bits { 8498 u8 opcode[0x10]; 8499 u8 uid[0x10]; 8500 8501 u8 reserved_at_20[0x10]; 8502 u8 op_mod[0x10]; 8503 8504 u8 reserved_at_40[0xc0]; 8505 8506 struct mlx5_ifc_tirc_bits ctx; 8507 }; 8508 8509 struct mlx5_ifc_create_srq_out_bits { 8510 u8 status[0x8]; 8511 u8 reserved_at_8[0x18]; 8512 8513 u8 syndrome[0x20]; 8514 8515 u8 reserved_at_40[0x8]; 8516 u8 srqn[0x18]; 8517 8518 u8 reserved_at_60[0x20]; 8519 }; 8520 8521 struct mlx5_ifc_create_srq_in_bits { 8522 u8 opcode[0x10]; 8523 u8 uid[0x10]; 8524 8525 u8 reserved_at_20[0x10]; 8526 u8 op_mod[0x10]; 8527 8528 u8 reserved_at_40[0x40]; 8529 8530 struct mlx5_ifc_srqc_bits srq_context_entry; 8531 8532 u8 reserved_at_280[0x600]; 8533 8534 u8 pas[][0x40]; 8535 }; 8536 8537 struct mlx5_ifc_create_sq_out_bits { 8538 u8 status[0x8]; 8539 u8 reserved_at_8[0x18]; 8540 8541 u8 syndrome[0x20]; 8542 8543 u8 reserved_at_40[0x8]; 8544 u8 sqn[0x18]; 8545 8546 u8 reserved_at_60[0x20]; 8547 }; 8548 8549 struct mlx5_ifc_create_sq_in_bits { 8550 u8 opcode[0x10]; 8551 u8 uid[0x10]; 8552 8553 u8 reserved_at_20[0x10]; 8554 u8 op_mod[0x10]; 8555 8556 u8 reserved_at_40[0xc0]; 8557 8558 struct mlx5_ifc_sqc_bits ctx; 8559 }; 8560 8561 struct mlx5_ifc_create_scheduling_element_out_bits { 8562 u8 status[0x8]; 8563 u8 reserved_at_8[0x18]; 8564 8565 u8 syndrome[0x20]; 8566 8567 u8 reserved_at_40[0x40]; 8568 8569 u8 scheduling_element_id[0x20]; 8570 8571 u8 reserved_at_a0[0x160]; 8572 }; 8573 8574 struct mlx5_ifc_create_scheduling_element_in_bits { 8575 u8 opcode[0x10]; 8576 u8 reserved_at_10[0x10]; 8577 8578 u8 reserved_at_20[0x10]; 8579 u8 op_mod[0x10]; 8580 8581 u8 scheduling_hierarchy[0x8]; 8582 u8 reserved_at_48[0x18]; 8583 8584 u8 reserved_at_60[0xa0]; 8585 8586 struct mlx5_ifc_scheduling_context_bits scheduling_context; 8587 8588 u8 reserved_at_300[0x100]; 8589 }; 8590 8591 struct mlx5_ifc_create_rqt_out_bits { 8592 u8 status[0x8]; 8593 u8 reserved_at_8[0x18]; 8594 8595 u8 syndrome[0x20]; 8596 8597 u8 reserved_at_40[0x8]; 8598 u8 rqtn[0x18]; 8599 8600 u8 reserved_at_60[0x20]; 8601 }; 8602 8603 struct mlx5_ifc_create_rqt_in_bits { 8604 u8 opcode[0x10]; 8605 u8 uid[0x10]; 8606 8607 u8 reserved_at_20[0x10]; 8608 u8 op_mod[0x10]; 8609 8610 u8 reserved_at_40[0xc0]; 8611 8612 struct mlx5_ifc_rqtc_bits rqt_context; 8613 }; 8614 8615 struct mlx5_ifc_create_rq_out_bits { 8616 u8 status[0x8]; 8617 u8 reserved_at_8[0x18]; 8618 8619 u8 syndrome[0x20]; 8620 8621 u8 reserved_at_40[0x8]; 8622 u8 rqn[0x18]; 8623 8624 u8 reserved_at_60[0x20]; 8625 }; 8626 8627 struct mlx5_ifc_create_rq_in_bits { 8628 u8 opcode[0x10]; 8629 u8 uid[0x10]; 8630 8631 u8 reserved_at_20[0x10]; 8632 u8 op_mod[0x10]; 8633 8634 u8 reserved_at_40[0xc0]; 8635 8636 struct mlx5_ifc_rqc_bits ctx; 8637 }; 8638 8639 struct mlx5_ifc_create_rmp_out_bits { 8640 u8 status[0x8]; 8641 u8 reserved_at_8[0x18]; 8642 8643 u8 syndrome[0x20]; 8644 8645 u8 reserved_at_40[0x8]; 8646 u8 rmpn[0x18]; 8647 8648 u8 reserved_at_60[0x20]; 8649 }; 8650 8651 struct mlx5_ifc_create_rmp_in_bits { 8652 u8 opcode[0x10]; 8653 u8 uid[0x10]; 8654 8655 u8 reserved_at_20[0x10]; 8656 u8 op_mod[0x10]; 8657 8658 u8 reserved_at_40[0xc0]; 8659 8660 struct mlx5_ifc_rmpc_bits ctx; 8661 }; 8662 8663 struct mlx5_ifc_create_qp_out_bits { 8664 u8 status[0x8]; 8665 u8 reserved_at_8[0x18]; 8666 8667 u8 syndrome[0x20]; 8668 8669 u8 reserved_at_40[0x8]; 8670 u8 qpn[0x18]; 8671 8672 u8 ece[0x20]; 8673 }; 8674 8675 struct mlx5_ifc_create_qp_in_bits { 8676 u8 opcode[0x10]; 8677 u8 uid[0x10]; 8678 8679 u8 reserved_at_20[0x10]; 8680 u8 op_mod[0x10]; 8681 8682 u8 qpc_ext[0x1]; 8683 u8 reserved_at_41[0x7]; 8684 u8 input_qpn[0x18]; 8685 8686 u8 reserved_at_60[0x20]; 8687 u8 opt_param_mask[0x20]; 8688 8689 u8 ece[0x20]; 8690 8691 struct mlx5_ifc_qpc_bits qpc; 8692 8693 u8 reserved_at_800[0x60]; 8694 8695 u8 wq_umem_valid[0x1]; 8696 u8 reserved_at_861[0x1f]; 8697 8698 u8 pas[][0x40]; 8699 }; 8700 8701 struct mlx5_ifc_create_psv_out_bits { 8702 u8 status[0x8]; 8703 u8 reserved_at_8[0x18]; 8704 8705 u8 syndrome[0x20]; 8706 8707 u8 reserved_at_40[0x40]; 8708 8709 u8 reserved_at_80[0x8]; 8710 u8 psv0_index[0x18]; 8711 8712 u8 reserved_at_a0[0x8]; 8713 u8 psv1_index[0x18]; 8714 8715 u8 reserved_at_c0[0x8]; 8716 u8 psv2_index[0x18]; 8717 8718 u8 reserved_at_e0[0x8]; 8719 u8 psv3_index[0x18]; 8720 }; 8721 8722 struct mlx5_ifc_create_psv_in_bits { 8723 u8 opcode[0x10]; 8724 u8 reserved_at_10[0x10]; 8725 8726 u8 reserved_at_20[0x10]; 8727 u8 op_mod[0x10]; 8728 8729 u8 num_psv[0x4]; 8730 u8 reserved_at_44[0x4]; 8731 u8 pd[0x18]; 8732 8733 u8 reserved_at_60[0x20]; 8734 }; 8735 8736 struct mlx5_ifc_create_mkey_out_bits { 8737 u8 status[0x8]; 8738 u8 reserved_at_8[0x18]; 8739 8740 u8 syndrome[0x20]; 8741 8742 u8 reserved_at_40[0x8]; 8743 u8 mkey_index[0x18]; 8744 8745 u8 reserved_at_60[0x20]; 8746 }; 8747 8748 struct mlx5_ifc_create_mkey_in_bits { 8749 u8 opcode[0x10]; 8750 u8 uid[0x10]; 8751 8752 u8 reserved_at_20[0x10]; 8753 u8 op_mod[0x10]; 8754 8755 u8 reserved_at_40[0x20]; 8756 8757 u8 pg_access[0x1]; 8758 u8 mkey_umem_valid[0x1]; 8759 u8 reserved_at_62[0x1e]; 8760 8761 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 8762 8763 u8 reserved_at_280[0x80]; 8764 8765 u8 translations_octword_actual_size[0x20]; 8766 8767 u8 reserved_at_320[0x560]; 8768 8769 u8 klm_pas_mtt[][0x20]; 8770 }; 8771 8772 enum { 8773 MLX5_FLOW_TABLE_TYPE_NIC_RX = 0x0, 8774 MLX5_FLOW_TABLE_TYPE_NIC_TX = 0x1, 8775 MLX5_FLOW_TABLE_TYPE_ESW_EGRESS_ACL = 0x2, 8776 MLX5_FLOW_TABLE_TYPE_ESW_INGRESS_ACL = 0x3, 8777 MLX5_FLOW_TABLE_TYPE_FDB = 0X4, 8778 MLX5_FLOW_TABLE_TYPE_SNIFFER_RX = 0X5, 8779 MLX5_FLOW_TABLE_TYPE_SNIFFER_TX = 0X6, 8780 }; 8781 8782 struct mlx5_ifc_create_flow_table_out_bits { 8783 u8 status[0x8]; 8784 u8 icm_address_63_40[0x18]; 8785 8786 u8 syndrome[0x20]; 8787 8788 u8 icm_address_39_32[0x8]; 8789 u8 table_id[0x18]; 8790 8791 u8 icm_address_31_0[0x20]; 8792 }; 8793 8794 struct mlx5_ifc_create_flow_table_in_bits { 8795 u8 opcode[0x10]; 8796 u8 uid[0x10]; 8797 8798 u8 reserved_at_20[0x10]; 8799 u8 op_mod[0x10]; 8800 8801 u8 other_vport[0x1]; 8802 u8 reserved_at_41[0xf]; 8803 u8 vport_number[0x10]; 8804 8805 u8 reserved_at_60[0x20]; 8806 8807 u8 table_type[0x8]; 8808 u8 reserved_at_88[0x18]; 8809 8810 u8 reserved_at_a0[0x20]; 8811 8812 struct mlx5_ifc_flow_table_context_bits flow_table_context; 8813 }; 8814 8815 struct mlx5_ifc_create_flow_group_out_bits { 8816 u8 status[0x8]; 8817 u8 reserved_at_8[0x18]; 8818 8819 u8 syndrome[0x20]; 8820 8821 u8 reserved_at_40[0x8]; 8822 u8 group_id[0x18]; 8823 8824 u8 reserved_at_60[0x20]; 8825 }; 8826 8827 enum { 8828 MLX5_CREATE_FLOW_GROUP_IN_GROUP_TYPE_TCAM_SUBTABLE = 0x0, 8829 MLX5_CREATE_FLOW_GROUP_IN_GROUP_TYPE_HASH_SPLIT = 0x1, 8830 }; 8831 8832 enum { 8833 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 8834 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 8835 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 8836 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3, 8837 }; 8838 8839 struct mlx5_ifc_create_flow_group_in_bits { 8840 u8 opcode[0x10]; 8841 u8 reserved_at_10[0x10]; 8842 8843 u8 reserved_at_20[0x10]; 8844 u8 op_mod[0x10]; 8845 8846 u8 other_vport[0x1]; 8847 u8 reserved_at_41[0xf]; 8848 u8 vport_number[0x10]; 8849 8850 u8 reserved_at_60[0x20]; 8851 8852 u8 table_type[0x8]; 8853 u8 reserved_at_88[0x4]; 8854 u8 group_type[0x4]; 8855 u8 reserved_at_90[0x10]; 8856 8857 u8 reserved_at_a0[0x8]; 8858 u8 table_id[0x18]; 8859 8860 u8 source_eswitch_owner_vhca_id_valid[0x1]; 8861 8862 u8 reserved_at_c1[0x1f]; 8863 8864 u8 start_flow_index[0x20]; 8865 8866 u8 reserved_at_100[0x20]; 8867 8868 u8 end_flow_index[0x20]; 8869 8870 u8 reserved_at_140[0x10]; 8871 u8 match_definer_id[0x10]; 8872 8873 u8 reserved_at_160[0x80]; 8874 8875 u8 reserved_at_1e0[0x18]; 8876 u8 match_criteria_enable[0x8]; 8877 8878 struct mlx5_ifc_fte_match_param_bits match_criteria; 8879 8880 u8 reserved_at_1200[0xe00]; 8881 }; 8882 8883 struct mlx5_ifc_create_eq_out_bits { 8884 u8 status[0x8]; 8885 u8 reserved_at_8[0x18]; 8886 8887 u8 syndrome[0x20]; 8888 8889 u8 reserved_at_40[0x18]; 8890 u8 eq_number[0x8]; 8891 8892 u8 reserved_at_60[0x20]; 8893 }; 8894 8895 struct mlx5_ifc_create_eq_in_bits { 8896 u8 opcode[0x10]; 8897 u8 uid[0x10]; 8898 8899 u8 reserved_at_20[0x10]; 8900 u8 op_mod[0x10]; 8901 8902 u8 reserved_at_40[0x40]; 8903 8904 struct mlx5_ifc_eqc_bits eq_context_entry; 8905 8906 u8 reserved_at_280[0x40]; 8907 8908 u8 event_bitmask[4][0x40]; 8909 8910 u8 reserved_at_3c0[0x4c0]; 8911 8912 u8 pas[][0x40]; 8913 }; 8914 8915 struct mlx5_ifc_create_dct_out_bits { 8916 u8 status[0x8]; 8917 u8 reserved_at_8[0x18]; 8918 8919 u8 syndrome[0x20]; 8920 8921 u8 reserved_at_40[0x8]; 8922 u8 dctn[0x18]; 8923 8924 u8 ece[0x20]; 8925 }; 8926 8927 struct mlx5_ifc_create_dct_in_bits { 8928 u8 opcode[0x10]; 8929 u8 uid[0x10]; 8930 8931 u8 reserved_at_20[0x10]; 8932 u8 op_mod[0x10]; 8933 8934 u8 reserved_at_40[0x40]; 8935 8936 struct mlx5_ifc_dctc_bits dct_context_entry; 8937 8938 u8 reserved_at_280[0x180]; 8939 }; 8940 8941 struct mlx5_ifc_create_cq_out_bits { 8942 u8 status[0x8]; 8943 u8 reserved_at_8[0x18]; 8944 8945 u8 syndrome[0x20]; 8946 8947 u8 reserved_at_40[0x8]; 8948 u8 cqn[0x18]; 8949 8950 u8 reserved_at_60[0x20]; 8951 }; 8952 8953 struct mlx5_ifc_create_cq_in_bits { 8954 u8 opcode[0x10]; 8955 u8 uid[0x10]; 8956 8957 u8 reserved_at_20[0x10]; 8958 u8 op_mod[0x10]; 8959 8960 u8 reserved_at_40[0x40]; 8961 8962 struct mlx5_ifc_cqc_bits cq_context; 8963 8964 u8 reserved_at_280[0x60]; 8965 8966 u8 cq_umem_valid[0x1]; 8967 u8 reserved_at_2e1[0x59f]; 8968 8969 u8 pas[][0x40]; 8970 }; 8971 8972 struct mlx5_ifc_config_int_moderation_out_bits { 8973 u8 status[0x8]; 8974 u8 reserved_at_8[0x18]; 8975 8976 u8 syndrome[0x20]; 8977 8978 u8 reserved_at_40[0x4]; 8979 u8 min_delay[0xc]; 8980 u8 int_vector[0x10]; 8981 8982 u8 reserved_at_60[0x20]; 8983 }; 8984 8985 enum { 8986 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0, 8987 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1, 8988 }; 8989 8990 struct mlx5_ifc_config_int_moderation_in_bits { 8991 u8 opcode[0x10]; 8992 u8 reserved_at_10[0x10]; 8993 8994 u8 reserved_at_20[0x10]; 8995 u8 op_mod[0x10]; 8996 8997 u8 reserved_at_40[0x4]; 8998 u8 min_delay[0xc]; 8999 u8 int_vector[0x10]; 9000 9001 u8 reserved_at_60[0x20]; 9002 }; 9003 9004 struct mlx5_ifc_attach_to_mcg_out_bits { 9005 u8 status[0x8]; 9006 u8 reserved_at_8[0x18]; 9007 9008 u8 syndrome[0x20]; 9009 9010 u8 reserved_at_40[0x40]; 9011 }; 9012 9013 struct mlx5_ifc_attach_to_mcg_in_bits { 9014 u8 opcode[0x10]; 9015 u8 uid[0x10]; 9016 9017 u8 reserved_at_20[0x10]; 9018 u8 op_mod[0x10]; 9019 9020 u8 reserved_at_40[0x8]; 9021 u8 qpn[0x18]; 9022 9023 u8 reserved_at_60[0x20]; 9024 9025 u8 multicast_gid[16][0x8]; 9026 }; 9027 9028 struct mlx5_ifc_arm_xrq_out_bits { 9029 u8 status[0x8]; 9030 u8 reserved_at_8[0x18]; 9031 9032 u8 syndrome[0x20]; 9033 9034 u8 reserved_at_40[0x40]; 9035 }; 9036 9037 struct mlx5_ifc_arm_xrq_in_bits { 9038 u8 opcode[0x10]; 9039 u8 reserved_at_10[0x10]; 9040 9041 u8 reserved_at_20[0x10]; 9042 u8 op_mod[0x10]; 9043 9044 u8 reserved_at_40[0x8]; 9045 u8 xrqn[0x18]; 9046 9047 u8 reserved_at_60[0x10]; 9048 u8 lwm[0x10]; 9049 }; 9050 9051 struct mlx5_ifc_arm_xrc_srq_out_bits { 9052 u8 status[0x8]; 9053 u8 reserved_at_8[0x18]; 9054 9055 u8 syndrome[0x20]; 9056 9057 u8 reserved_at_40[0x40]; 9058 }; 9059 9060 enum { 9061 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1, 9062 }; 9063 9064 struct mlx5_ifc_arm_xrc_srq_in_bits { 9065 u8 opcode[0x10]; 9066 u8 uid[0x10]; 9067 9068 u8 reserved_at_20[0x10]; 9069 u8 op_mod[0x10]; 9070 9071 u8 reserved_at_40[0x8]; 9072 u8 xrc_srqn[0x18]; 9073 9074 u8 reserved_at_60[0x10]; 9075 u8 lwm[0x10]; 9076 }; 9077 9078 struct mlx5_ifc_arm_rq_out_bits { 9079 u8 status[0x8]; 9080 u8 reserved_at_8[0x18]; 9081 9082 u8 syndrome[0x20]; 9083 9084 u8 reserved_at_40[0x40]; 9085 }; 9086 9087 enum { 9088 MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1, 9089 MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2, 9090 }; 9091 9092 struct mlx5_ifc_arm_rq_in_bits { 9093 u8 opcode[0x10]; 9094 u8 uid[0x10]; 9095 9096 u8 reserved_at_20[0x10]; 9097 u8 op_mod[0x10]; 9098 9099 u8 reserved_at_40[0x8]; 9100 u8 srq_number[0x18]; 9101 9102 u8 reserved_at_60[0x10]; 9103 u8 lwm[0x10]; 9104 }; 9105 9106 struct mlx5_ifc_arm_dct_out_bits { 9107 u8 status[0x8]; 9108 u8 reserved_at_8[0x18]; 9109 9110 u8 syndrome[0x20]; 9111 9112 u8 reserved_at_40[0x40]; 9113 }; 9114 9115 struct mlx5_ifc_arm_dct_in_bits { 9116 u8 opcode[0x10]; 9117 u8 reserved_at_10[0x10]; 9118 9119 u8 reserved_at_20[0x10]; 9120 u8 op_mod[0x10]; 9121 9122 u8 reserved_at_40[0x8]; 9123 u8 dct_number[0x18]; 9124 9125 u8 reserved_at_60[0x20]; 9126 }; 9127 9128 struct mlx5_ifc_alloc_xrcd_out_bits { 9129 u8 status[0x8]; 9130 u8 reserved_at_8[0x18]; 9131 9132 u8 syndrome[0x20]; 9133 9134 u8 reserved_at_40[0x8]; 9135 u8 xrcd[0x18]; 9136 9137 u8 reserved_at_60[0x20]; 9138 }; 9139 9140 struct mlx5_ifc_alloc_xrcd_in_bits { 9141 u8 opcode[0x10]; 9142 u8 uid[0x10]; 9143 9144 u8 reserved_at_20[0x10]; 9145 u8 op_mod[0x10]; 9146 9147 u8 reserved_at_40[0x40]; 9148 }; 9149 9150 struct mlx5_ifc_alloc_uar_out_bits { 9151 u8 status[0x8]; 9152 u8 reserved_at_8[0x18]; 9153 9154 u8 syndrome[0x20]; 9155 9156 u8 reserved_at_40[0x8]; 9157 u8 uar[0x18]; 9158 9159 u8 reserved_at_60[0x20]; 9160 }; 9161 9162 struct mlx5_ifc_alloc_uar_in_bits { 9163 u8 opcode[0x10]; 9164 u8 uid[0x10]; 9165 9166 u8 reserved_at_20[0x10]; 9167 u8 op_mod[0x10]; 9168 9169 u8 reserved_at_40[0x40]; 9170 }; 9171 9172 struct mlx5_ifc_alloc_transport_domain_out_bits { 9173 u8 status[0x8]; 9174 u8 reserved_at_8[0x18]; 9175 9176 u8 syndrome[0x20]; 9177 9178 u8 reserved_at_40[0x8]; 9179 u8 transport_domain[0x18]; 9180 9181 u8 reserved_at_60[0x20]; 9182 }; 9183 9184 struct mlx5_ifc_alloc_transport_domain_in_bits { 9185 u8 opcode[0x10]; 9186 u8 uid[0x10]; 9187 9188 u8 reserved_at_20[0x10]; 9189 u8 op_mod[0x10]; 9190 9191 u8 reserved_at_40[0x40]; 9192 }; 9193 9194 struct mlx5_ifc_alloc_q_counter_out_bits { 9195 u8 status[0x8]; 9196 u8 reserved_at_8[0x18]; 9197 9198 u8 syndrome[0x20]; 9199 9200 u8 reserved_at_40[0x18]; 9201 u8 counter_set_id[0x8]; 9202 9203 u8 reserved_at_60[0x20]; 9204 }; 9205 9206 struct mlx5_ifc_alloc_q_counter_in_bits { 9207 u8 opcode[0x10]; 9208 u8 uid[0x10]; 9209 9210 u8 reserved_at_20[0x10]; 9211 u8 op_mod[0x10]; 9212 9213 u8 reserved_at_40[0x40]; 9214 }; 9215 9216 struct mlx5_ifc_alloc_pd_out_bits { 9217 u8 status[0x8]; 9218 u8 reserved_at_8[0x18]; 9219 9220 u8 syndrome[0x20]; 9221 9222 u8 reserved_at_40[0x8]; 9223 u8 pd[0x18]; 9224 9225 u8 reserved_at_60[0x20]; 9226 }; 9227 9228 struct mlx5_ifc_alloc_pd_in_bits { 9229 u8 opcode[0x10]; 9230 u8 uid[0x10]; 9231 9232 u8 reserved_at_20[0x10]; 9233 u8 op_mod[0x10]; 9234 9235 u8 reserved_at_40[0x40]; 9236 }; 9237 9238 struct mlx5_ifc_alloc_flow_counter_out_bits { 9239 u8 status[0x8]; 9240 u8 reserved_at_8[0x18]; 9241 9242 u8 syndrome[0x20]; 9243 9244 u8 flow_counter_id[0x20]; 9245 9246 u8 reserved_at_60[0x20]; 9247 }; 9248 9249 struct mlx5_ifc_alloc_flow_counter_in_bits { 9250 u8 opcode[0x10]; 9251 u8 reserved_at_10[0x10]; 9252 9253 u8 reserved_at_20[0x10]; 9254 u8 op_mod[0x10]; 9255 9256 u8 reserved_at_40[0x38]; 9257 u8 flow_counter_bulk[0x8]; 9258 }; 9259 9260 struct mlx5_ifc_add_vxlan_udp_dport_out_bits { 9261 u8 status[0x8]; 9262 u8 reserved_at_8[0x18]; 9263 9264 u8 syndrome[0x20]; 9265 9266 u8 reserved_at_40[0x40]; 9267 }; 9268 9269 struct mlx5_ifc_add_vxlan_udp_dport_in_bits { 9270 u8 opcode[0x10]; 9271 u8 reserved_at_10[0x10]; 9272 9273 u8 reserved_at_20[0x10]; 9274 u8 op_mod[0x10]; 9275 9276 u8 reserved_at_40[0x20]; 9277 9278 u8 reserved_at_60[0x10]; 9279 u8 vxlan_udp_port[0x10]; 9280 }; 9281 9282 struct mlx5_ifc_set_pp_rate_limit_out_bits { 9283 u8 status[0x8]; 9284 u8 reserved_at_8[0x18]; 9285 9286 u8 syndrome[0x20]; 9287 9288 u8 reserved_at_40[0x40]; 9289 }; 9290 9291 struct mlx5_ifc_set_pp_rate_limit_context_bits { 9292 u8 rate_limit[0x20]; 9293 9294 u8 burst_upper_bound[0x20]; 9295 9296 u8 reserved_at_40[0x10]; 9297 u8 typical_packet_size[0x10]; 9298 9299 u8 reserved_at_60[0x120]; 9300 }; 9301 9302 struct mlx5_ifc_set_pp_rate_limit_in_bits { 9303 u8 opcode[0x10]; 9304 u8 uid[0x10]; 9305 9306 u8 reserved_at_20[0x10]; 9307 u8 op_mod[0x10]; 9308 9309 u8 reserved_at_40[0x10]; 9310 u8 rate_limit_index[0x10]; 9311 9312 u8 reserved_at_60[0x20]; 9313 9314 struct mlx5_ifc_set_pp_rate_limit_context_bits ctx; 9315 }; 9316 9317 struct mlx5_ifc_access_register_out_bits { 9318 u8 status[0x8]; 9319 u8 reserved_at_8[0x18]; 9320 9321 u8 syndrome[0x20]; 9322 9323 u8 reserved_at_40[0x40]; 9324 9325 u8 register_data[][0x20]; 9326 }; 9327 9328 enum { 9329 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0, 9330 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1, 9331 }; 9332 9333 struct mlx5_ifc_access_register_in_bits { 9334 u8 opcode[0x10]; 9335 u8 reserved_at_10[0x10]; 9336 9337 u8 reserved_at_20[0x10]; 9338 u8 op_mod[0x10]; 9339 9340 u8 reserved_at_40[0x10]; 9341 u8 register_id[0x10]; 9342 9343 u8 argument[0x20]; 9344 9345 u8 register_data[][0x20]; 9346 }; 9347 9348 struct mlx5_ifc_sltp_reg_bits { 9349 u8 status[0x4]; 9350 u8 version[0x4]; 9351 u8 local_port[0x8]; 9352 u8 pnat[0x2]; 9353 u8 reserved_at_12[0x2]; 9354 u8 lane[0x4]; 9355 u8 reserved_at_18[0x8]; 9356 9357 u8 reserved_at_20[0x20]; 9358 9359 u8 reserved_at_40[0x7]; 9360 u8 polarity[0x1]; 9361 u8 ob_tap0[0x8]; 9362 u8 ob_tap1[0x8]; 9363 u8 ob_tap2[0x8]; 9364 9365 u8 reserved_at_60[0xc]; 9366 u8 ob_preemp_mode[0x4]; 9367 u8 ob_reg[0x8]; 9368 u8 ob_bias[0x8]; 9369 9370 u8 reserved_at_80[0x20]; 9371 }; 9372 9373 struct mlx5_ifc_slrg_reg_bits { 9374 u8 status[0x4]; 9375 u8 version[0x4]; 9376 u8 local_port[0x8]; 9377 u8 pnat[0x2]; 9378 u8 reserved_at_12[0x2]; 9379 u8 lane[0x4]; 9380 u8 reserved_at_18[0x8]; 9381 9382 u8 time_to_link_up[0x10]; 9383 u8 reserved_at_30[0xc]; 9384 u8 grade_lane_speed[0x4]; 9385 9386 u8 grade_version[0x8]; 9387 u8 grade[0x18]; 9388 9389 u8 reserved_at_60[0x4]; 9390 u8 height_grade_type[0x4]; 9391 u8 height_grade[0x18]; 9392 9393 u8 height_dz[0x10]; 9394 u8 height_dv[0x10]; 9395 9396 u8 reserved_at_a0[0x10]; 9397 u8 height_sigma[0x10]; 9398 9399 u8 reserved_at_c0[0x20]; 9400 9401 u8 reserved_at_e0[0x4]; 9402 u8 phase_grade_type[0x4]; 9403 u8 phase_grade[0x18]; 9404 9405 u8 reserved_at_100[0x8]; 9406 u8 phase_eo_pos[0x8]; 9407 u8 reserved_at_110[0x8]; 9408 u8 phase_eo_neg[0x8]; 9409 9410 u8 ffe_set_tested[0x10]; 9411 u8 test_errors_per_lane[0x10]; 9412 }; 9413 9414 struct mlx5_ifc_pvlc_reg_bits { 9415 u8 reserved_at_0[0x8]; 9416 u8 local_port[0x8]; 9417 u8 reserved_at_10[0x10]; 9418 9419 u8 reserved_at_20[0x1c]; 9420 u8 vl_hw_cap[0x4]; 9421 9422 u8 reserved_at_40[0x1c]; 9423 u8 vl_admin[0x4]; 9424 9425 u8 reserved_at_60[0x1c]; 9426 u8 vl_operational[0x4]; 9427 }; 9428 9429 struct mlx5_ifc_pude_reg_bits { 9430 u8 swid[0x8]; 9431 u8 local_port[0x8]; 9432 u8 reserved_at_10[0x4]; 9433 u8 admin_status[0x4]; 9434 u8 reserved_at_18[0x4]; 9435 u8 oper_status[0x4]; 9436 9437 u8 reserved_at_20[0x60]; 9438 }; 9439 9440 struct mlx5_ifc_ptys_reg_bits { 9441 u8 reserved_at_0[0x1]; 9442 u8 an_disable_admin[0x1]; 9443 u8 an_disable_cap[0x1]; 9444 u8 reserved_at_3[0x5]; 9445 u8 local_port[0x8]; 9446 u8 reserved_at_10[0xd]; 9447 u8 proto_mask[0x3]; 9448 9449 u8 an_status[0x4]; 9450 u8 reserved_at_24[0xc]; 9451 u8 data_rate_oper[0x10]; 9452 9453 u8 ext_eth_proto_capability[0x20]; 9454 9455 u8 eth_proto_capability[0x20]; 9456 9457 u8 ib_link_width_capability[0x10]; 9458 u8 ib_proto_capability[0x10]; 9459 9460 u8 ext_eth_proto_admin[0x20]; 9461 9462 u8 eth_proto_admin[0x20]; 9463 9464 u8 ib_link_width_admin[0x10]; 9465 u8 ib_proto_admin[0x10]; 9466 9467 u8 ext_eth_proto_oper[0x20]; 9468 9469 u8 eth_proto_oper[0x20]; 9470 9471 u8 ib_link_width_oper[0x10]; 9472 u8 ib_proto_oper[0x10]; 9473 9474 u8 reserved_at_160[0x1c]; 9475 u8 connector_type[0x4]; 9476 9477 u8 eth_proto_lp_advertise[0x20]; 9478 9479 u8 reserved_at_1a0[0x60]; 9480 }; 9481 9482 struct mlx5_ifc_mlcr_reg_bits { 9483 u8 reserved_at_0[0x8]; 9484 u8 local_port[0x8]; 9485 u8 reserved_at_10[0x20]; 9486 9487 u8 beacon_duration[0x10]; 9488 u8 reserved_at_40[0x10]; 9489 9490 u8 beacon_remain[0x10]; 9491 }; 9492 9493 struct mlx5_ifc_ptas_reg_bits { 9494 u8 reserved_at_0[0x20]; 9495 9496 u8 algorithm_options[0x10]; 9497 u8 reserved_at_30[0x4]; 9498 u8 repetitions_mode[0x4]; 9499 u8 num_of_repetitions[0x8]; 9500 9501 u8 grade_version[0x8]; 9502 u8 height_grade_type[0x4]; 9503 u8 phase_grade_type[0x4]; 9504 u8 height_grade_weight[0x8]; 9505 u8 phase_grade_weight[0x8]; 9506 9507 u8 gisim_measure_bits[0x10]; 9508 u8 adaptive_tap_measure_bits[0x10]; 9509 9510 u8 ber_bath_high_error_threshold[0x10]; 9511 u8 ber_bath_mid_error_threshold[0x10]; 9512 9513 u8 ber_bath_low_error_threshold[0x10]; 9514 u8 one_ratio_high_threshold[0x10]; 9515 9516 u8 one_ratio_high_mid_threshold[0x10]; 9517 u8 one_ratio_low_mid_threshold[0x10]; 9518 9519 u8 one_ratio_low_threshold[0x10]; 9520 u8 ndeo_error_threshold[0x10]; 9521 9522 u8 mixer_offset_step_size[0x10]; 9523 u8 reserved_at_110[0x8]; 9524 u8 mix90_phase_for_voltage_bath[0x8]; 9525 9526 u8 mixer_offset_start[0x10]; 9527 u8 mixer_offset_end[0x10]; 9528 9529 u8 reserved_at_140[0x15]; 9530 u8 ber_test_time[0xb]; 9531 }; 9532 9533 struct mlx5_ifc_pspa_reg_bits { 9534 u8 swid[0x8]; 9535 u8 local_port[0x8]; 9536 u8 sub_port[0x8]; 9537 u8 reserved_at_18[0x8]; 9538 9539 u8 reserved_at_20[0x20]; 9540 }; 9541 9542 struct mlx5_ifc_pqdr_reg_bits { 9543 u8 reserved_at_0[0x8]; 9544 u8 local_port[0x8]; 9545 u8 reserved_at_10[0x5]; 9546 u8 prio[0x3]; 9547 u8 reserved_at_18[0x6]; 9548 u8 mode[0x2]; 9549 9550 u8 reserved_at_20[0x20]; 9551 9552 u8 reserved_at_40[0x10]; 9553 u8 min_threshold[0x10]; 9554 9555 u8 reserved_at_60[0x10]; 9556 u8 max_threshold[0x10]; 9557 9558 u8 reserved_at_80[0x10]; 9559 u8 mark_probability_denominator[0x10]; 9560 9561 u8 reserved_at_a0[0x60]; 9562 }; 9563 9564 struct mlx5_ifc_ppsc_reg_bits { 9565 u8 reserved_at_0[0x8]; 9566 u8 local_port[0x8]; 9567 u8 reserved_at_10[0x10]; 9568 9569 u8 reserved_at_20[0x60]; 9570 9571 u8 reserved_at_80[0x1c]; 9572 u8 wrps_admin[0x4]; 9573 9574 u8 reserved_at_a0[0x1c]; 9575 u8 wrps_status[0x4]; 9576 9577 u8 reserved_at_c0[0x8]; 9578 u8 up_threshold[0x8]; 9579 u8 reserved_at_d0[0x8]; 9580 u8 down_threshold[0x8]; 9581 9582 u8 reserved_at_e0[0x20]; 9583 9584 u8 reserved_at_100[0x1c]; 9585 u8 srps_admin[0x4]; 9586 9587 u8 reserved_at_120[0x1c]; 9588 u8 srps_status[0x4]; 9589 9590 u8 reserved_at_140[0x40]; 9591 }; 9592 9593 struct mlx5_ifc_pplr_reg_bits { 9594 u8 reserved_at_0[0x8]; 9595 u8 local_port[0x8]; 9596 u8 reserved_at_10[0x10]; 9597 9598 u8 reserved_at_20[0x8]; 9599 u8 lb_cap[0x8]; 9600 u8 reserved_at_30[0x8]; 9601 u8 lb_en[0x8]; 9602 }; 9603 9604 struct mlx5_ifc_pplm_reg_bits { 9605 u8 reserved_at_0[0x8]; 9606 u8 local_port[0x8]; 9607 u8 reserved_at_10[0x10]; 9608 9609 u8 reserved_at_20[0x20]; 9610 9611 u8 port_profile_mode[0x8]; 9612 u8 static_port_profile[0x8]; 9613 u8 active_port_profile[0x8]; 9614 u8 reserved_at_58[0x8]; 9615 9616 u8 retransmission_active[0x8]; 9617 u8 fec_mode_active[0x18]; 9618 9619 u8 rs_fec_correction_bypass_cap[0x4]; 9620 u8 reserved_at_84[0x8]; 9621 u8 fec_override_cap_56g[0x4]; 9622 u8 fec_override_cap_100g[0x4]; 9623 u8 fec_override_cap_50g[0x4]; 9624 u8 fec_override_cap_25g[0x4]; 9625 u8 fec_override_cap_10g_40g[0x4]; 9626 9627 u8 rs_fec_correction_bypass_admin[0x4]; 9628 u8 reserved_at_a4[0x8]; 9629 u8 fec_override_admin_56g[0x4]; 9630 u8 fec_override_admin_100g[0x4]; 9631 u8 fec_override_admin_50g[0x4]; 9632 u8 fec_override_admin_25g[0x4]; 9633 u8 fec_override_admin_10g_40g[0x4]; 9634 9635 u8 fec_override_cap_400g_8x[0x10]; 9636 u8 fec_override_cap_200g_4x[0x10]; 9637 9638 u8 fec_override_cap_100g_2x[0x10]; 9639 u8 fec_override_cap_50g_1x[0x10]; 9640 9641 u8 fec_override_admin_400g_8x[0x10]; 9642 u8 fec_override_admin_200g_4x[0x10]; 9643 9644 u8 fec_override_admin_100g_2x[0x10]; 9645 u8 fec_override_admin_50g_1x[0x10]; 9646 9647 u8 reserved_at_140[0x140]; 9648 }; 9649 9650 struct mlx5_ifc_ppcnt_reg_bits { 9651 u8 swid[0x8]; 9652 u8 local_port[0x8]; 9653 u8 pnat[0x2]; 9654 u8 reserved_at_12[0x8]; 9655 u8 grp[0x6]; 9656 9657 u8 clr[0x1]; 9658 u8 reserved_at_21[0x1c]; 9659 u8 prio_tc[0x3]; 9660 9661 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set; 9662 }; 9663 9664 struct mlx5_ifc_mpein_reg_bits { 9665 u8 reserved_at_0[0x2]; 9666 u8 depth[0x6]; 9667 u8 pcie_index[0x8]; 9668 u8 node[0x8]; 9669 u8 reserved_at_18[0x8]; 9670 9671 u8 capability_mask[0x20]; 9672 9673 u8 reserved_at_40[0x8]; 9674 u8 link_width_enabled[0x8]; 9675 u8 link_speed_enabled[0x10]; 9676 9677 u8 lane0_physical_position[0x8]; 9678 u8 link_width_active[0x8]; 9679 u8 link_speed_active[0x10]; 9680 9681 u8 num_of_pfs[0x10]; 9682 u8 num_of_vfs[0x10]; 9683 9684 u8 bdf0[0x10]; 9685 u8 reserved_at_b0[0x10]; 9686 9687 u8 max_read_request_size[0x4]; 9688 u8 max_payload_size[0x4]; 9689 u8 reserved_at_c8[0x5]; 9690 u8 pwr_status[0x3]; 9691 u8 port_type[0x4]; 9692 u8 reserved_at_d4[0xb]; 9693 u8 lane_reversal[0x1]; 9694 9695 u8 reserved_at_e0[0x14]; 9696 u8 pci_power[0xc]; 9697 9698 u8 reserved_at_100[0x20]; 9699 9700 u8 device_status[0x10]; 9701 u8 port_state[0x8]; 9702 u8 reserved_at_138[0x8]; 9703 9704 u8 reserved_at_140[0x10]; 9705 u8 receiver_detect_result[0x10]; 9706 9707 u8 reserved_at_160[0x20]; 9708 }; 9709 9710 struct mlx5_ifc_mpcnt_reg_bits { 9711 u8 reserved_at_0[0x8]; 9712 u8 pcie_index[0x8]; 9713 u8 reserved_at_10[0xa]; 9714 u8 grp[0x6]; 9715 9716 u8 clr[0x1]; 9717 u8 reserved_at_21[0x1f]; 9718 9719 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set; 9720 }; 9721 9722 struct mlx5_ifc_ppad_reg_bits { 9723 u8 reserved_at_0[0x3]; 9724 u8 single_mac[0x1]; 9725 u8 reserved_at_4[0x4]; 9726 u8 local_port[0x8]; 9727 u8 mac_47_32[0x10]; 9728 9729 u8 mac_31_0[0x20]; 9730 9731 u8 reserved_at_40[0x40]; 9732 }; 9733 9734 struct mlx5_ifc_pmtu_reg_bits { 9735 u8 reserved_at_0[0x8]; 9736 u8 local_port[0x8]; 9737 u8 reserved_at_10[0x10]; 9738 9739 u8 max_mtu[0x10]; 9740 u8 reserved_at_30[0x10]; 9741 9742 u8 admin_mtu[0x10]; 9743 u8 reserved_at_50[0x10]; 9744 9745 u8 oper_mtu[0x10]; 9746 u8 reserved_at_70[0x10]; 9747 }; 9748 9749 struct mlx5_ifc_pmpr_reg_bits { 9750 u8 reserved_at_0[0x8]; 9751 u8 module[0x8]; 9752 u8 reserved_at_10[0x10]; 9753 9754 u8 reserved_at_20[0x18]; 9755 u8 attenuation_5g[0x8]; 9756 9757 u8 reserved_at_40[0x18]; 9758 u8 attenuation_7g[0x8]; 9759 9760 u8 reserved_at_60[0x18]; 9761 u8 attenuation_12g[0x8]; 9762 }; 9763 9764 struct mlx5_ifc_pmpe_reg_bits { 9765 u8 reserved_at_0[0x8]; 9766 u8 module[0x8]; 9767 u8 reserved_at_10[0xc]; 9768 u8 module_status[0x4]; 9769 9770 u8 reserved_at_20[0x60]; 9771 }; 9772 9773 struct mlx5_ifc_pmpc_reg_bits { 9774 u8 module_state_updated[32][0x8]; 9775 }; 9776 9777 struct mlx5_ifc_pmlpn_reg_bits { 9778 u8 reserved_at_0[0x4]; 9779 u8 mlpn_status[0x4]; 9780 u8 local_port[0x8]; 9781 u8 reserved_at_10[0x10]; 9782 9783 u8 e[0x1]; 9784 u8 reserved_at_21[0x1f]; 9785 }; 9786 9787 struct mlx5_ifc_pmlp_reg_bits { 9788 u8 rxtx[0x1]; 9789 u8 reserved_at_1[0x7]; 9790 u8 local_port[0x8]; 9791 u8 reserved_at_10[0x8]; 9792 u8 width[0x8]; 9793 9794 u8 lane0_module_mapping[0x20]; 9795 9796 u8 lane1_module_mapping[0x20]; 9797 9798 u8 lane2_module_mapping[0x20]; 9799 9800 u8 lane3_module_mapping[0x20]; 9801 9802 u8 reserved_at_a0[0x160]; 9803 }; 9804 9805 struct mlx5_ifc_pmaos_reg_bits { 9806 u8 reserved_at_0[0x8]; 9807 u8 module[0x8]; 9808 u8 reserved_at_10[0x4]; 9809 u8 admin_status[0x4]; 9810 u8 reserved_at_18[0x4]; 9811 u8 oper_status[0x4]; 9812 9813 u8 ase[0x1]; 9814 u8 ee[0x1]; 9815 u8 reserved_at_22[0x1c]; 9816 u8 e[0x2]; 9817 9818 u8 reserved_at_40[0x40]; 9819 }; 9820 9821 struct mlx5_ifc_plpc_reg_bits { 9822 u8 reserved_at_0[0x4]; 9823 u8 profile_id[0xc]; 9824 u8 reserved_at_10[0x4]; 9825 u8 proto_mask[0x4]; 9826 u8 reserved_at_18[0x8]; 9827 9828 u8 reserved_at_20[0x10]; 9829 u8 lane_speed[0x10]; 9830 9831 u8 reserved_at_40[0x17]; 9832 u8 lpbf[0x1]; 9833 u8 fec_mode_policy[0x8]; 9834 9835 u8 retransmission_capability[0x8]; 9836 u8 fec_mode_capability[0x18]; 9837 9838 u8 retransmission_support_admin[0x8]; 9839 u8 fec_mode_support_admin[0x18]; 9840 9841 u8 retransmission_request_admin[0x8]; 9842 u8 fec_mode_request_admin[0x18]; 9843 9844 u8 reserved_at_c0[0x80]; 9845 }; 9846 9847 struct mlx5_ifc_plib_reg_bits { 9848 u8 reserved_at_0[0x8]; 9849 u8 local_port[0x8]; 9850 u8 reserved_at_10[0x8]; 9851 u8 ib_port[0x8]; 9852 9853 u8 reserved_at_20[0x60]; 9854 }; 9855 9856 struct mlx5_ifc_plbf_reg_bits { 9857 u8 reserved_at_0[0x8]; 9858 u8 local_port[0x8]; 9859 u8 reserved_at_10[0xd]; 9860 u8 lbf_mode[0x3]; 9861 9862 u8 reserved_at_20[0x20]; 9863 }; 9864 9865 struct mlx5_ifc_pipg_reg_bits { 9866 u8 reserved_at_0[0x8]; 9867 u8 local_port[0x8]; 9868 u8 reserved_at_10[0x10]; 9869 9870 u8 dic[0x1]; 9871 u8 reserved_at_21[0x19]; 9872 u8 ipg[0x4]; 9873 u8 reserved_at_3e[0x2]; 9874 }; 9875 9876 struct mlx5_ifc_pifr_reg_bits { 9877 u8 reserved_at_0[0x8]; 9878 u8 local_port[0x8]; 9879 u8 reserved_at_10[0x10]; 9880 9881 u8 reserved_at_20[0xe0]; 9882 9883 u8 port_filter[8][0x20]; 9884 9885 u8 port_filter_update_en[8][0x20]; 9886 }; 9887 9888 struct mlx5_ifc_pfcc_reg_bits { 9889 u8 reserved_at_0[0x8]; 9890 u8 local_port[0x8]; 9891 u8 reserved_at_10[0xb]; 9892 u8 ppan_mask_n[0x1]; 9893 u8 minor_stall_mask[0x1]; 9894 u8 critical_stall_mask[0x1]; 9895 u8 reserved_at_1e[0x2]; 9896 9897 u8 ppan[0x4]; 9898 u8 reserved_at_24[0x4]; 9899 u8 prio_mask_tx[0x8]; 9900 u8 reserved_at_30[0x8]; 9901 u8 prio_mask_rx[0x8]; 9902 9903 u8 pptx[0x1]; 9904 u8 aptx[0x1]; 9905 u8 pptx_mask_n[0x1]; 9906 u8 reserved_at_43[0x5]; 9907 u8 pfctx[0x8]; 9908 u8 reserved_at_50[0x10]; 9909 9910 u8 pprx[0x1]; 9911 u8 aprx[0x1]; 9912 u8 pprx_mask_n[0x1]; 9913 u8 reserved_at_63[0x5]; 9914 u8 pfcrx[0x8]; 9915 u8 reserved_at_70[0x10]; 9916 9917 u8 device_stall_minor_watermark[0x10]; 9918 u8 device_stall_critical_watermark[0x10]; 9919 9920 u8 reserved_at_a0[0x60]; 9921 }; 9922 9923 struct mlx5_ifc_pelc_reg_bits { 9924 u8 op[0x4]; 9925 u8 reserved_at_4[0x4]; 9926 u8 local_port[0x8]; 9927 u8 reserved_at_10[0x10]; 9928 9929 u8 op_admin[0x8]; 9930 u8 op_capability[0x8]; 9931 u8 op_request[0x8]; 9932 u8 op_active[0x8]; 9933 9934 u8 admin[0x40]; 9935 9936 u8 capability[0x40]; 9937 9938 u8 request[0x40]; 9939 9940 u8 active[0x40]; 9941 9942 u8 reserved_at_140[0x80]; 9943 }; 9944 9945 struct mlx5_ifc_peir_reg_bits { 9946 u8 reserved_at_0[0x8]; 9947 u8 local_port[0x8]; 9948 u8 reserved_at_10[0x10]; 9949 9950 u8 reserved_at_20[0xc]; 9951 u8 error_count[0x4]; 9952 u8 reserved_at_30[0x10]; 9953 9954 u8 reserved_at_40[0xc]; 9955 u8 lane[0x4]; 9956 u8 reserved_at_50[0x8]; 9957 u8 error_type[0x8]; 9958 }; 9959 9960 struct mlx5_ifc_mpegc_reg_bits { 9961 u8 reserved_at_0[0x30]; 9962 u8 field_select[0x10]; 9963 9964 u8 tx_overflow_sense[0x1]; 9965 u8 mark_cqe[0x1]; 9966 u8 mark_cnp[0x1]; 9967 u8 reserved_at_43[0x1b]; 9968 u8 tx_lossy_overflow_oper[0x2]; 9969 9970 u8 reserved_at_60[0x100]; 9971 }; 9972 9973 enum { 9974 MLX5_MTUTC_FREQ_ADJ_UNITS_PPB = 0x0, 9975 MLX5_MTUTC_FREQ_ADJ_UNITS_SCALED_PPM = 0x1, 9976 }; 9977 9978 enum { 9979 MLX5_MTUTC_OPERATION_SET_TIME_IMMEDIATE = 0x1, 9980 MLX5_MTUTC_OPERATION_ADJUST_TIME = 0x2, 9981 MLX5_MTUTC_OPERATION_ADJUST_FREQ_UTC = 0x3, 9982 }; 9983 9984 struct mlx5_ifc_mtutc_reg_bits { 9985 u8 reserved_at_0[0x5]; 9986 u8 freq_adj_units[0x3]; 9987 u8 reserved_at_8[0x14]; 9988 u8 operation[0x4]; 9989 9990 u8 freq_adjustment[0x20]; 9991 9992 u8 reserved_at_40[0x40]; 9993 9994 u8 utc_sec[0x20]; 9995 9996 u8 reserved_at_a0[0x2]; 9997 u8 utc_nsec[0x1e]; 9998 9999 u8 time_adjustment[0x20]; 10000 }; 10001 10002 struct mlx5_ifc_pcam_enhanced_features_bits { 10003 u8 reserved_at_0[0x68]; 10004 u8 fec_50G_per_lane_in_pplm[0x1]; 10005 u8 reserved_at_69[0x4]; 10006 u8 rx_icrc_encapsulated_counter[0x1]; 10007 u8 reserved_at_6e[0x4]; 10008 u8 ptys_extended_ethernet[0x1]; 10009 u8 reserved_at_73[0x3]; 10010 u8 pfcc_mask[0x1]; 10011 u8 reserved_at_77[0x3]; 10012 u8 per_lane_error_counters[0x1]; 10013 u8 rx_buffer_fullness_counters[0x1]; 10014 u8 ptys_connector_type[0x1]; 10015 u8 reserved_at_7d[0x1]; 10016 u8 ppcnt_discard_group[0x1]; 10017 u8 ppcnt_statistical_group[0x1]; 10018 }; 10019 10020 struct mlx5_ifc_pcam_regs_5000_to_507f_bits { 10021 u8 port_access_reg_cap_mask_127_to_96[0x20]; 10022 u8 port_access_reg_cap_mask_95_to_64[0x20]; 10023 10024 u8 port_access_reg_cap_mask_63_to_36[0x1c]; 10025 u8 pplm[0x1]; 10026 u8 port_access_reg_cap_mask_34_to_32[0x3]; 10027 10028 u8 port_access_reg_cap_mask_31_to_13[0x13]; 10029 u8 pbmc[0x1]; 10030 u8 pptb[0x1]; 10031 u8 port_access_reg_cap_mask_10_to_09[0x2]; 10032 u8 ppcnt[0x1]; 10033 u8 port_access_reg_cap_mask_07_to_00[0x8]; 10034 }; 10035 10036 struct mlx5_ifc_pcam_reg_bits { 10037 u8 reserved_at_0[0x8]; 10038 u8 feature_group[0x8]; 10039 u8 reserved_at_10[0x8]; 10040 u8 access_reg_group[0x8]; 10041 10042 u8 reserved_at_20[0x20]; 10043 10044 union { 10045 struct mlx5_ifc_pcam_regs_5000_to_507f_bits regs_5000_to_507f; 10046 u8 reserved_at_0[0x80]; 10047 } port_access_reg_cap_mask; 10048 10049 u8 reserved_at_c0[0x80]; 10050 10051 union { 10052 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features; 10053 u8 reserved_at_0[0x80]; 10054 } feature_cap_mask; 10055 10056 u8 reserved_at_1c0[0xc0]; 10057 }; 10058 10059 struct mlx5_ifc_mcam_enhanced_features_bits { 10060 u8 reserved_at_0[0x50]; 10061 u8 mtutc_freq_adj_units[0x1]; 10062 u8 mtutc_time_adjustment_extended_range[0x1]; 10063 u8 reserved_at_52[0xb]; 10064 u8 mcia_32dwords[0x1]; 10065 u8 out_pulse_duration_ns[0x1]; 10066 u8 npps_period[0x1]; 10067 u8 reserved_at_60[0xa]; 10068 u8 reset_state[0x1]; 10069 u8 ptpcyc2realtime_modify[0x1]; 10070 u8 reserved_at_6c[0x2]; 10071 u8 pci_status_and_power[0x1]; 10072 u8 reserved_at_6f[0x5]; 10073 u8 mark_tx_action_cnp[0x1]; 10074 u8 mark_tx_action_cqe[0x1]; 10075 u8 dynamic_tx_overflow[0x1]; 10076 u8 reserved_at_77[0x4]; 10077 u8 pcie_outbound_stalled[0x1]; 10078 u8 tx_overflow_buffer_pkt[0x1]; 10079 u8 mtpps_enh_out_per_adj[0x1]; 10080 u8 mtpps_fs[0x1]; 10081 u8 pcie_performance_group[0x1]; 10082 }; 10083 10084 struct mlx5_ifc_mcam_access_reg_bits { 10085 u8 reserved_at_0[0x1c]; 10086 u8 mcda[0x1]; 10087 u8 mcc[0x1]; 10088 u8 mcqi[0x1]; 10089 u8 mcqs[0x1]; 10090 10091 u8 regs_95_to_87[0x9]; 10092 u8 mpegc[0x1]; 10093 u8 mtutc[0x1]; 10094 u8 regs_84_to_68[0x11]; 10095 u8 tracer_registers[0x4]; 10096 10097 u8 regs_63_to_46[0x12]; 10098 u8 mrtc[0x1]; 10099 u8 regs_44_to_32[0xd]; 10100 10101 u8 regs_31_to_0[0x20]; 10102 }; 10103 10104 struct mlx5_ifc_mcam_access_reg_bits1 { 10105 u8 regs_127_to_96[0x20]; 10106 10107 u8 regs_95_to_64[0x20]; 10108 10109 u8 regs_63_to_32[0x20]; 10110 10111 u8 regs_31_to_0[0x20]; 10112 }; 10113 10114 struct mlx5_ifc_mcam_access_reg_bits2 { 10115 u8 regs_127_to_99[0x1d]; 10116 u8 mirc[0x1]; 10117 u8 regs_97_to_96[0x2]; 10118 10119 u8 regs_95_to_64[0x20]; 10120 10121 u8 regs_63_to_32[0x20]; 10122 10123 u8 regs_31_to_0[0x20]; 10124 }; 10125 10126 struct mlx5_ifc_mcam_reg_bits { 10127 u8 reserved_at_0[0x8]; 10128 u8 feature_group[0x8]; 10129 u8 reserved_at_10[0x8]; 10130 u8 access_reg_group[0x8]; 10131 10132 u8 reserved_at_20[0x20]; 10133 10134 union { 10135 struct mlx5_ifc_mcam_access_reg_bits access_regs; 10136 struct mlx5_ifc_mcam_access_reg_bits1 access_regs1; 10137 struct mlx5_ifc_mcam_access_reg_bits2 access_regs2; 10138 u8 reserved_at_0[0x80]; 10139 } mng_access_reg_cap_mask; 10140 10141 u8 reserved_at_c0[0x80]; 10142 10143 union { 10144 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features; 10145 u8 reserved_at_0[0x80]; 10146 } mng_feature_cap_mask; 10147 10148 u8 reserved_at_1c0[0x80]; 10149 }; 10150 10151 struct mlx5_ifc_qcam_access_reg_cap_mask { 10152 u8 qcam_access_reg_cap_mask_127_to_20[0x6C]; 10153 u8 qpdpm[0x1]; 10154 u8 qcam_access_reg_cap_mask_18_to_4[0x0F]; 10155 u8 qdpm[0x1]; 10156 u8 qpts[0x1]; 10157 u8 qcap[0x1]; 10158 u8 qcam_access_reg_cap_mask_0[0x1]; 10159 }; 10160 10161 struct mlx5_ifc_qcam_qos_feature_cap_mask { 10162 u8 qcam_qos_feature_cap_mask_127_to_1[0x7F]; 10163 u8 qpts_trust_both[0x1]; 10164 }; 10165 10166 struct mlx5_ifc_qcam_reg_bits { 10167 u8 reserved_at_0[0x8]; 10168 u8 feature_group[0x8]; 10169 u8 reserved_at_10[0x8]; 10170 u8 access_reg_group[0x8]; 10171 u8 reserved_at_20[0x20]; 10172 10173 union { 10174 struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap; 10175 u8 reserved_at_0[0x80]; 10176 } qos_access_reg_cap_mask; 10177 10178 u8 reserved_at_c0[0x80]; 10179 10180 union { 10181 struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap; 10182 u8 reserved_at_0[0x80]; 10183 } qos_feature_cap_mask; 10184 10185 u8 reserved_at_1c0[0x80]; 10186 }; 10187 10188 struct mlx5_ifc_core_dump_reg_bits { 10189 u8 reserved_at_0[0x18]; 10190 u8 core_dump_type[0x8]; 10191 10192 u8 reserved_at_20[0x30]; 10193 u8 vhca_id[0x10]; 10194 10195 u8 reserved_at_60[0x8]; 10196 u8 qpn[0x18]; 10197 u8 reserved_at_80[0x180]; 10198 }; 10199 10200 struct mlx5_ifc_pcap_reg_bits { 10201 u8 reserved_at_0[0x8]; 10202 u8 local_port[0x8]; 10203 u8 reserved_at_10[0x10]; 10204 10205 u8 port_capability_mask[4][0x20]; 10206 }; 10207 10208 struct mlx5_ifc_paos_reg_bits { 10209 u8 swid[0x8]; 10210 u8 local_port[0x8]; 10211 u8 reserved_at_10[0x4]; 10212 u8 admin_status[0x4]; 10213 u8 reserved_at_18[0x4]; 10214 u8 oper_status[0x4]; 10215 10216 u8 ase[0x1]; 10217 u8 ee[0x1]; 10218 u8 reserved_at_22[0x1c]; 10219 u8 e[0x2]; 10220 10221 u8 reserved_at_40[0x40]; 10222 }; 10223 10224 struct mlx5_ifc_pamp_reg_bits { 10225 u8 reserved_at_0[0x8]; 10226 u8 opamp_group[0x8]; 10227 u8 reserved_at_10[0xc]; 10228 u8 opamp_group_type[0x4]; 10229 10230 u8 start_index[0x10]; 10231 u8 reserved_at_30[0x4]; 10232 u8 num_of_indices[0xc]; 10233 10234 u8 index_data[18][0x10]; 10235 }; 10236 10237 struct mlx5_ifc_pcmr_reg_bits { 10238 u8 reserved_at_0[0x8]; 10239 u8 local_port[0x8]; 10240 u8 reserved_at_10[0x10]; 10241 10242 u8 entropy_force_cap[0x1]; 10243 u8 entropy_calc_cap[0x1]; 10244 u8 entropy_gre_calc_cap[0x1]; 10245 u8 reserved_at_23[0xf]; 10246 u8 rx_ts_over_crc_cap[0x1]; 10247 u8 reserved_at_33[0xb]; 10248 u8 fcs_cap[0x1]; 10249 u8 reserved_at_3f[0x1]; 10250 10251 u8 entropy_force[0x1]; 10252 u8 entropy_calc[0x1]; 10253 u8 entropy_gre_calc[0x1]; 10254 u8 reserved_at_43[0xf]; 10255 u8 rx_ts_over_crc[0x1]; 10256 u8 reserved_at_53[0xb]; 10257 u8 fcs_chk[0x1]; 10258 u8 reserved_at_5f[0x1]; 10259 }; 10260 10261 struct mlx5_ifc_lane_2_module_mapping_bits { 10262 u8 reserved_at_0[0x4]; 10263 u8 rx_lane[0x4]; 10264 u8 reserved_at_8[0x4]; 10265 u8 tx_lane[0x4]; 10266 u8 reserved_at_10[0x8]; 10267 u8 module[0x8]; 10268 }; 10269 10270 struct mlx5_ifc_bufferx_reg_bits { 10271 u8 reserved_at_0[0x6]; 10272 u8 lossy[0x1]; 10273 u8 epsb[0x1]; 10274 u8 reserved_at_8[0x8]; 10275 u8 size[0x10]; 10276 10277 u8 xoff_threshold[0x10]; 10278 u8 xon_threshold[0x10]; 10279 }; 10280 10281 struct mlx5_ifc_set_node_in_bits { 10282 u8 node_description[64][0x8]; 10283 }; 10284 10285 struct mlx5_ifc_register_power_settings_bits { 10286 u8 reserved_at_0[0x18]; 10287 u8 power_settings_level[0x8]; 10288 10289 u8 reserved_at_20[0x60]; 10290 }; 10291 10292 struct mlx5_ifc_register_host_endianness_bits { 10293 u8 he[0x1]; 10294 u8 reserved_at_1[0x1f]; 10295 10296 u8 reserved_at_20[0x60]; 10297 }; 10298 10299 struct mlx5_ifc_umr_pointer_desc_argument_bits { 10300 u8 reserved_at_0[0x20]; 10301 10302 u8 mkey[0x20]; 10303 10304 u8 addressh_63_32[0x20]; 10305 10306 u8 addressl_31_0[0x20]; 10307 }; 10308 10309 struct mlx5_ifc_ud_adrs_vector_bits { 10310 u8 dc_key[0x40]; 10311 10312 u8 ext[0x1]; 10313 u8 reserved_at_41[0x7]; 10314 u8 destination_qp_dct[0x18]; 10315 10316 u8 static_rate[0x4]; 10317 u8 sl_eth_prio[0x4]; 10318 u8 fl[0x1]; 10319 u8 mlid[0x7]; 10320 u8 rlid_udp_sport[0x10]; 10321 10322 u8 reserved_at_80[0x20]; 10323 10324 u8 rmac_47_16[0x20]; 10325 10326 u8 rmac_15_0[0x10]; 10327 u8 tclass[0x8]; 10328 u8 hop_limit[0x8]; 10329 10330 u8 reserved_at_e0[0x1]; 10331 u8 grh[0x1]; 10332 u8 reserved_at_e2[0x2]; 10333 u8 src_addr_index[0x8]; 10334 u8 flow_label[0x14]; 10335 10336 u8 rgid_rip[16][0x8]; 10337 }; 10338 10339 struct mlx5_ifc_pages_req_event_bits { 10340 u8 reserved_at_0[0x10]; 10341 u8 function_id[0x10]; 10342 10343 u8 num_pages[0x20]; 10344 10345 u8 reserved_at_40[0xa0]; 10346 }; 10347 10348 struct mlx5_ifc_eqe_bits { 10349 u8 reserved_at_0[0x8]; 10350 u8 event_type[0x8]; 10351 u8 reserved_at_10[0x8]; 10352 u8 event_sub_type[0x8]; 10353 10354 u8 reserved_at_20[0xe0]; 10355 10356 union mlx5_ifc_event_auto_bits event_data; 10357 10358 u8 reserved_at_1e0[0x10]; 10359 u8 signature[0x8]; 10360 u8 reserved_at_1f8[0x7]; 10361 u8 owner[0x1]; 10362 }; 10363 10364 enum { 10365 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7, 10366 }; 10367 10368 struct mlx5_ifc_cmd_queue_entry_bits { 10369 u8 type[0x8]; 10370 u8 reserved_at_8[0x18]; 10371 10372 u8 input_length[0x20]; 10373 10374 u8 input_mailbox_pointer_63_32[0x20]; 10375 10376 u8 input_mailbox_pointer_31_9[0x17]; 10377 u8 reserved_at_77[0x9]; 10378 10379 u8 command_input_inline_data[16][0x8]; 10380 10381 u8 command_output_inline_data[16][0x8]; 10382 10383 u8 output_mailbox_pointer_63_32[0x20]; 10384 10385 u8 output_mailbox_pointer_31_9[0x17]; 10386 u8 reserved_at_1b7[0x9]; 10387 10388 u8 output_length[0x20]; 10389 10390 u8 token[0x8]; 10391 u8 signature[0x8]; 10392 u8 reserved_at_1f0[0x8]; 10393 u8 status[0x7]; 10394 u8 ownership[0x1]; 10395 }; 10396 10397 struct mlx5_ifc_cmd_out_bits { 10398 u8 status[0x8]; 10399 u8 reserved_at_8[0x18]; 10400 10401 u8 syndrome[0x20]; 10402 10403 u8 command_output[0x20]; 10404 }; 10405 10406 struct mlx5_ifc_cmd_in_bits { 10407 u8 opcode[0x10]; 10408 u8 reserved_at_10[0x10]; 10409 10410 u8 reserved_at_20[0x10]; 10411 u8 op_mod[0x10]; 10412 10413 u8 command[][0x20]; 10414 }; 10415 10416 struct mlx5_ifc_cmd_if_box_bits { 10417 u8 mailbox_data[512][0x8]; 10418 10419 u8 reserved_at_1000[0x180]; 10420 10421 u8 next_pointer_63_32[0x20]; 10422 10423 u8 next_pointer_31_10[0x16]; 10424 u8 reserved_at_11b6[0xa]; 10425 10426 u8 block_number[0x20]; 10427 10428 u8 reserved_at_11e0[0x8]; 10429 u8 token[0x8]; 10430 u8 ctrl_signature[0x8]; 10431 u8 signature[0x8]; 10432 }; 10433 10434 struct mlx5_ifc_mtt_bits { 10435 u8 ptag_63_32[0x20]; 10436 10437 u8 ptag_31_8[0x18]; 10438 u8 reserved_at_38[0x6]; 10439 u8 wr_en[0x1]; 10440 u8 rd_en[0x1]; 10441 }; 10442 10443 struct mlx5_ifc_query_wol_rol_out_bits { 10444 u8 status[0x8]; 10445 u8 reserved_at_8[0x18]; 10446 10447 u8 syndrome[0x20]; 10448 10449 u8 reserved_at_40[0x10]; 10450 u8 rol_mode[0x8]; 10451 u8 wol_mode[0x8]; 10452 10453 u8 reserved_at_60[0x20]; 10454 }; 10455 10456 struct mlx5_ifc_query_wol_rol_in_bits { 10457 u8 opcode[0x10]; 10458 u8 reserved_at_10[0x10]; 10459 10460 u8 reserved_at_20[0x10]; 10461 u8 op_mod[0x10]; 10462 10463 u8 reserved_at_40[0x40]; 10464 }; 10465 10466 struct mlx5_ifc_set_wol_rol_out_bits { 10467 u8 status[0x8]; 10468 u8 reserved_at_8[0x18]; 10469 10470 u8 syndrome[0x20]; 10471 10472 u8 reserved_at_40[0x40]; 10473 }; 10474 10475 struct mlx5_ifc_set_wol_rol_in_bits { 10476 u8 opcode[0x10]; 10477 u8 reserved_at_10[0x10]; 10478 10479 u8 reserved_at_20[0x10]; 10480 u8 op_mod[0x10]; 10481 10482 u8 rol_mode_valid[0x1]; 10483 u8 wol_mode_valid[0x1]; 10484 u8 reserved_at_42[0xe]; 10485 u8 rol_mode[0x8]; 10486 u8 wol_mode[0x8]; 10487 10488 u8 reserved_at_60[0x20]; 10489 }; 10490 10491 enum { 10492 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0, 10493 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1, 10494 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2, 10495 }; 10496 10497 enum { 10498 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0, 10499 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1, 10500 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2, 10501 }; 10502 10503 enum { 10504 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR = 0x1, 10505 MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC = 0x7, 10506 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR = 0x8, 10507 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR = 0x9, 10508 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR = 0xa, 10509 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR = 0xb, 10510 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN = 0xc, 10511 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR = 0xd, 10512 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV = 0xe, 10513 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR = 0xf, 10514 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR = 0x10, 10515 }; 10516 10517 struct mlx5_ifc_initial_seg_bits { 10518 u8 fw_rev_minor[0x10]; 10519 u8 fw_rev_major[0x10]; 10520 10521 u8 cmd_interface_rev[0x10]; 10522 u8 fw_rev_subminor[0x10]; 10523 10524 u8 reserved_at_40[0x40]; 10525 10526 u8 cmdq_phy_addr_63_32[0x20]; 10527 10528 u8 cmdq_phy_addr_31_12[0x14]; 10529 u8 reserved_at_b4[0x2]; 10530 u8 nic_interface[0x2]; 10531 u8 log_cmdq_size[0x4]; 10532 u8 log_cmdq_stride[0x4]; 10533 10534 u8 command_doorbell_vector[0x20]; 10535 10536 u8 reserved_at_e0[0xf00]; 10537 10538 u8 initializing[0x1]; 10539 u8 reserved_at_fe1[0x4]; 10540 u8 nic_interface_supported[0x3]; 10541 u8 embedded_cpu[0x1]; 10542 u8 reserved_at_fe9[0x17]; 10543 10544 struct mlx5_ifc_health_buffer_bits health_buffer; 10545 10546 u8 no_dram_nic_offset[0x20]; 10547 10548 u8 reserved_at_1220[0x6e40]; 10549 10550 u8 reserved_at_8060[0x1f]; 10551 u8 clear_int[0x1]; 10552 10553 u8 health_syndrome[0x8]; 10554 u8 health_counter[0x18]; 10555 10556 u8 reserved_at_80a0[0x17fc0]; 10557 }; 10558 10559 struct mlx5_ifc_mtpps_reg_bits { 10560 u8 reserved_at_0[0xc]; 10561 u8 cap_number_of_pps_pins[0x4]; 10562 u8 reserved_at_10[0x4]; 10563 u8 cap_max_num_of_pps_in_pins[0x4]; 10564 u8 reserved_at_18[0x4]; 10565 u8 cap_max_num_of_pps_out_pins[0x4]; 10566 10567 u8 reserved_at_20[0x13]; 10568 u8 cap_log_min_npps_period[0x5]; 10569 u8 reserved_at_38[0x3]; 10570 u8 cap_log_min_out_pulse_duration_ns[0x5]; 10571 10572 u8 reserved_at_40[0x4]; 10573 u8 cap_pin_3_mode[0x4]; 10574 u8 reserved_at_48[0x4]; 10575 u8 cap_pin_2_mode[0x4]; 10576 u8 reserved_at_50[0x4]; 10577 u8 cap_pin_1_mode[0x4]; 10578 u8 reserved_at_58[0x4]; 10579 u8 cap_pin_0_mode[0x4]; 10580 10581 u8 reserved_at_60[0x4]; 10582 u8 cap_pin_7_mode[0x4]; 10583 u8 reserved_at_68[0x4]; 10584 u8 cap_pin_6_mode[0x4]; 10585 u8 reserved_at_70[0x4]; 10586 u8 cap_pin_5_mode[0x4]; 10587 u8 reserved_at_78[0x4]; 10588 u8 cap_pin_4_mode[0x4]; 10589 10590 u8 field_select[0x20]; 10591 u8 reserved_at_a0[0x20]; 10592 10593 u8 npps_period[0x40]; 10594 10595 u8 enable[0x1]; 10596 u8 reserved_at_101[0xb]; 10597 u8 pattern[0x4]; 10598 u8 reserved_at_110[0x4]; 10599 u8 pin_mode[0x4]; 10600 u8 pin[0x8]; 10601 10602 u8 reserved_at_120[0x2]; 10603 u8 out_pulse_duration_ns[0x1e]; 10604 10605 u8 time_stamp[0x40]; 10606 10607 u8 out_pulse_duration[0x10]; 10608 u8 out_periodic_adjustment[0x10]; 10609 u8 enhanced_out_periodic_adjustment[0x20]; 10610 10611 u8 reserved_at_1c0[0x20]; 10612 }; 10613 10614 struct mlx5_ifc_mtppse_reg_bits { 10615 u8 reserved_at_0[0x18]; 10616 u8 pin[0x8]; 10617 u8 event_arm[0x1]; 10618 u8 reserved_at_21[0x1b]; 10619 u8 event_generation_mode[0x4]; 10620 u8 reserved_at_40[0x40]; 10621 }; 10622 10623 struct mlx5_ifc_mcqs_reg_bits { 10624 u8 last_index_flag[0x1]; 10625 u8 reserved_at_1[0x7]; 10626 u8 fw_device[0x8]; 10627 u8 component_index[0x10]; 10628 10629 u8 reserved_at_20[0x10]; 10630 u8 identifier[0x10]; 10631 10632 u8 reserved_at_40[0x17]; 10633 u8 component_status[0x5]; 10634 u8 component_update_state[0x4]; 10635 10636 u8 last_update_state_changer_type[0x4]; 10637 u8 last_update_state_changer_host_id[0x4]; 10638 u8 reserved_at_68[0x18]; 10639 }; 10640 10641 struct mlx5_ifc_mcqi_cap_bits { 10642 u8 supported_info_bitmask[0x20]; 10643 10644 u8 component_size[0x20]; 10645 10646 u8 max_component_size[0x20]; 10647 10648 u8 log_mcda_word_size[0x4]; 10649 u8 reserved_at_64[0xc]; 10650 u8 mcda_max_write_size[0x10]; 10651 10652 u8 rd_en[0x1]; 10653 u8 reserved_at_81[0x1]; 10654 u8 match_chip_id[0x1]; 10655 u8 match_psid[0x1]; 10656 u8 check_user_timestamp[0x1]; 10657 u8 match_base_guid_mac[0x1]; 10658 u8 reserved_at_86[0x1a]; 10659 }; 10660 10661 struct mlx5_ifc_mcqi_version_bits { 10662 u8 reserved_at_0[0x2]; 10663 u8 build_time_valid[0x1]; 10664 u8 user_defined_time_valid[0x1]; 10665 u8 reserved_at_4[0x14]; 10666 u8 version_string_length[0x8]; 10667 10668 u8 version[0x20]; 10669 10670 u8 build_time[0x40]; 10671 10672 u8 user_defined_time[0x40]; 10673 10674 u8 build_tool_version[0x20]; 10675 10676 u8 reserved_at_e0[0x20]; 10677 10678 u8 version_string[92][0x8]; 10679 }; 10680 10681 struct mlx5_ifc_mcqi_activation_method_bits { 10682 u8 pending_server_ac_power_cycle[0x1]; 10683 u8 pending_server_dc_power_cycle[0x1]; 10684 u8 pending_server_reboot[0x1]; 10685 u8 pending_fw_reset[0x1]; 10686 u8 auto_activate[0x1]; 10687 u8 all_hosts_sync[0x1]; 10688 u8 device_hw_reset[0x1]; 10689 u8 reserved_at_7[0x19]; 10690 }; 10691 10692 union mlx5_ifc_mcqi_reg_data_bits { 10693 struct mlx5_ifc_mcqi_cap_bits mcqi_caps; 10694 struct mlx5_ifc_mcqi_version_bits mcqi_version; 10695 struct mlx5_ifc_mcqi_activation_method_bits mcqi_activation_mathod; 10696 }; 10697 10698 struct mlx5_ifc_mcqi_reg_bits { 10699 u8 read_pending_component[0x1]; 10700 u8 reserved_at_1[0xf]; 10701 u8 component_index[0x10]; 10702 10703 u8 reserved_at_20[0x20]; 10704 10705 u8 reserved_at_40[0x1b]; 10706 u8 info_type[0x5]; 10707 10708 u8 info_size[0x20]; 10709 10710 u8 offset[0x20]; 10711 10712 u8 reserved_at_a0[0x10]; 10713 u8 data_size[0x10]; 10714 10715 union mlx5_ifc_mcqi_reg_data_bits data[]; 10716 }; 10717 10718 struct mlx5_ifc_mcc_reg_bits { 10719 u8 reserved_at_0[0x4]; 10720 u8 time_elapsed_since_last_cmd[0xc]; 10721 u8 reserved_at_10[0x8]; 10722 u8 instruction[0x8]; 10723 10724 u8 reserved_at_20[0x10]; 10725 u8 component_index[0x10]; 10726 10727 u8 reserved_at_40[0x8]; 10728 u8 update_handle[0x18]; 10729 10730 u8 handle_owner_type[0x4]; 10731 u8 handle_owner_host_id[0x4]; 10732 u8 reserved_at_68[0x1]; 10733 u8 control_progress[0x7]; 10734 u8 error_code[0x8]; 10735 u8 reserved_at_78[0x4]; 10736 u8 control_state[0x4]; 10737 10738 u8 component_size[0x20]; 10739 10740 u8 reserved_at_a0[0x60]; 10741 }; 10742 10743 struct mlx5_ifc_mcda_reg_bits { 10744 u8 reserved_at_0[0x8]; 10745 u8 update_handle[0x18]; 10746 10747 u8 offset[0x20]; 10748 10749 u8 reserved_at_40[0x10]; 10750 u8 size[0x10]; 10751 10752 u8 reserved_at_60[0x20]; 10753 10754 u8 data[][0x20]; 10755 }; 10756 10757 enum { 10758 MLX5_MFRL_REG_RESET_STATE_IDLE = 0, 10759 MLX5_MFRL_REG_RESET_STATE_IN_NEGOTIATION = 1, 10760 MLX5_MFRL_REG_RESET_STATE_RESET_IN_PROGRESS = 2, 10761 MLX5_MFRL_REG_RESET_STATE_TIMEOUT = 3, 10762 MLX5_MFRL_REG_RESET_STATE_NACK = 4, 10763 }; 10764 10765 enum { 10766 MLX5_MFRL_REG_RESET_TYPE_FULL_CHIP = BIT(0), 10767 MLX5_MFRL_REG_RESET_TYPE_NET_PORT_ALIVE = BIT(1), 10768 }; 10769 10770 enum { 10771 MLX5_MFRL_REG_RESET_LEVEL0 = BIT(0), 10772 MLX5_MFRL_REG_RESET_LEVEL3 = BIT(3), 10773 MLX5_MFRL_REG_RESET_LEVEL6 = BIT(6), 10774 }; 10775 10776 struct mlx5_ifc_mfrl_reg_bits { 10777 u8 reserved_at_0[0x20]; 10778 10779 u8 reserved_at_20[0x2]; 10780 u8 pci_sync_for_fw_update_start[0x1]; 10781 u8 pci_sync_for_fw_update_resp[0x2]; 10782 u8 rst_type_sel[0x3]; 10783 u8 reserved_at_28[0x4]; 10784 u8 reset_state[0x4]; 10785 u8 reset_type[0x8]; 10786 u8 reset_level[0x8]; 10787 }; 10788 10789 struct mlx5_ifc_mirc_reg_bits { 10790 u8 reserved_at_0[0x18]; 10791 u8 status_code[0x8]; 10792 10793 u8 reserved_at_20[0x20]; 10794 }; 10795 10796 struct mlx5_ifc_pddr_monitor_opcode_bits { 10797 u8 reserved_at_0[0x10]; 10798 u8 monitor_opcode[0x10]; 10799 }; 10800 10801 union mlx5_ifc_pddr_troubleshooting_page_status_opcode_auto_bits { 10802 struct mlx5_ifc_pddr_monitor_opcode_bits pddr_monitor_opcode; 10803 u8 reserved_at_0[0x20]; 10804 }; 10805 10806 enum { 10807 /* Monitor opcodes */ 10808 MLX5_PDDR_REG_TRBLSH_GROUP_OPCODE_MONITOR = 0x0, 10809 }; 10810 10811 struct mlx5_ifc_pddr_troubleshooting_page_bits { 10812 u8 reserved_at_0[0x10]; 10813 u8 group_opcode[0x10]; 10814 10815 union mlx5_ifc_pddr_troubleshooting_page_status_opcode_auto_bits status_opcode; 10816 10817 u8 reserved_at_40[0x20]; 10818 10819 u8 status_message[59][0x20]; 10820 }; 10821 10822 union mlx5_ifc_pddr_reg_page_data_auto_bits { 10823 struct mlx5_ifc_pddr_troubleshooting_page_bits pddr_troubleshooting_page; 10824 u8 reserved_at_0[0x7c0]; 10825 }; 10826 10827 enum { 10828 MLX5_PDDR_REG_PAGE_SELECT_TROUBLESHOOTING_INFO_PAGE = 0x1, 10829 }; 10830 10831 struct mlx5_ifc_pddr_reg_bits { 10832 u8 reserved_at_0[0x8]; 10833 u8 local_port[0x8]; 10834 u8 pnat[0x2]; 10835 u8 reserved_at_12[0xe]; 10836 10837 u8 reserved_at_20[0x18]; 10838 u8 page_select[0x8]; 10839 10840 union mlx5_ifc_pddr_reg_page_data_auto_bits page_data; 10841 }; 10842 10843 struct mlx5_ifc_mrtc_reg_bits { 10844 u8 time_synced[0x1]; 10845 u8 reserved_at_1[0x1f]; 10846 10847 u8 reserved_at_20[0x20]; 10848 10849 u8 time_h[0x20]; 10850 10851 u8 time_l[0x20]; 10852 }; 10853 10854 union mlx5_ifc_ports_control_registers_document_bits { 10855 struct mlx5_ifc_bufferx_reg_bits bufferx_reg; 10856 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 10857 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 10858 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 10859 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 10860 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 10861 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 10862 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout; 10863 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout; 10864 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping; 10865 struct mlx5_ifc_pamp_reg_bits pamp_reg; 10866 struct mlx5_ifc_paos_reg_bits paos_reg; 10867 struct mlx5_ifc_pcap_reg_bits pcap_reg; 10868 struct mlx5_ifc_pddr_monitor_opcode_bits pddr_monitor_opcode; 10869 struct mlx5_ifc_pddr_reg_bits pddr_reg; 10870 struct mlx5_ifc_pddr_troubleshooting_page_bits pddr_troubleshooting_page; 10871 struct mlx5_ifc_peir_reg_bits peir_reg; 10872 struct mlx5_ifc_pelc_reg_bits pelc_reg; 10873 struct mlx5_ifc_pfcc_reg_bits pfcc_reg; 10874 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 10875 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 10876 struct mlx5_ifc_pifr_reg_bits pifr_reg; 10877 struct mlx5_ifc_pipg_reg_bits pipg_reg; 10878 struct mlx5_ifc_plbf_reg_bits plbf_reg; 10879 struct mlx5_ifc_plib_reg_bits plib_reg; 10880 struct mlx5_ifc_plpc_reg_bits plpc_reg; 10881 struct mlx5_ifc_pmaos_reg_bits pmaos_reg; 10882 struct mlx5_ifc_pmlp_reg_bits pmlp_reg; 10883 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg; 10884 struct mlx5_ifc_pmpc_reg_bits pmpc_reg; 10885 struct mlx5_ifc_pmpe_reg_bits pmpe_reg; 10886 struct mlx5_ifc_pmpr_reg_bits pmpr_reg; 10887 struct mlx5_ifc_pmtu_reg_bits pmtu_reg; 10888 struct mlx5_ifc_ppad_reg_bits ppad_reg; 10889 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg; 10890 struct mlx5_ifc_mpein_reg_bits mpein_reg; 10891 struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg; 10892 struct mlx5_ifc_pplm_reg_bits pplm_reg; 10893 struct mlx5_ifc_pplr_reg_bits pplr_reg; 10894 struct mlx5_ifc_ppsc_reg_bits ppsc_reg; 10895 struct mlx5_ifc_pqdr_reg_bits pqdr_reg; 10896 struct mlx5_ifc_pspa_reg_bits pspa_reg; 10897 struct mlx5_ifc_ptas_reg_bits ptas_reg; 10898 struct mlx5_ifc_ptys_reg_bits ptys_reg; 10899 struct mlx5_ifc_mlcr_reg_bits mlcr_reg; 10900 struct mlx5_ifc_pude_reg_bits pude_reg; 10901 struct mlx5_ifc_pvlc_reg_bits pvlc_reg; 10902 struct mlx5_ifc_slrg_reg_bits slrg_reg; 10903 struct mlx5_ifc_sltp_reg_bits sltp_reg; 10904 struct mlx5_ifc_mtpps_reg_bits mtpps_reg; 10905 struct mlx5_ifc_mtppse_reg_bits mtppse_reg; 10906 struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg; 10907 struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits; 10908 struct mlx5_ifc_fpga_cap_bits fpga_cap_bits; 10909 struct mlx5_ifc_mcqi_reg_bits mcqi_reg; 10910 struct mlx5_ifc_mcc_reg_bits mcc_reg; 10911 struct mlx5_ifc_mcda_reg_bits mcda_reg; 10912 struct mlx5_ifc_mirc_reg_bits mirc_reg; 10913 struct mlx5_ifc_mfrl_reg_bits mfrl_reg; 10914 struct mlx5_ifc_mtutc_reg_bits mtutc_reg; 10915 struct mlx5_ifc_mrtc_reg_bits mrtc_reg; 10916 u8 reserved_at_0[0x60e0]; 10917 }; 10918 10919 union mlx5_ifc_debug_enhancements_document_bits { 10920 struct mlx5_ifc_health_buffer_bits health_buffer; 10921 u8 reserved_at_0[0x200]; 10922 }; 10923 10924 union mlx5_ifc_uplink_pci_interface_document_bits { 10925 struct mlx5_ifc_initial_seg_bits initial_seg; 10926 u8 reserved_at_0[0x20060]; 10927 }; 10928 10929 struct mlx5_ifc_set_flow_table_root_out_bits { 10930 u8 status[0x8]; 10931 u8 reserved_at_8[0x18]; 10932 10933 u8 syndrome[0x20]; 10934 10935 u8 reserved_at_40[0x40]; 10936 }; 10937 10938 struct mlx5_ifc_set_flow_table_root_in_bits { 10939 u8 opcode[0x10]; 10940 u8 reserved_at_10[0x10]; 10941 10942 u8 reserved_at_20[0x10]; 10943 u8 op_mod[0x10]; 10944 10945 u8 other_vport[0x1]; 10946 u8 reserved_at_41[0xf]; 10947 u8 vport_number[0x10]; 10948 10949 u8 reserved_at_60[0x20]; 10950 10951 u8 table_type[0x8]; 10952 u8 reserved_at_88[0x7]; 10953 u8 table_of_other_vport[0x1]; 10954 u8 table_vport_number[0x10]; 10955 10956 u8 reserved_at_a0[0x8]; 10957 u8 table_id[0x18]; 10958 10959 u8 reserved_at_c0[0x8]; 10960 u8 underlay_qpn[0x18]; 10961 u8 table_eswitch_owner_vhca_id_valid[0x1]; 10962 u8 reserved_at_e1[0xf]; 10963 u8 table_eswitch_owner_vhca_id[0x10]; 10964 u8 reserved_at_100[0x100]; 10965 }; 10966 10967 enum { 10968 MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = (1UL << 0), 10969 MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15), 10970 }; 10971 10972 struct mlx5_ifc_modify_flow_table_out_bits { 10973 u8 status[0x8]; 10974 u8 reserved_at_8[0x18]; 10975 10976 u8 syndrome[0x20]; 10977 10978 u8 reserved_at_40[0x40]; 10979 }; 10980 10981 struct mlx5_ifc_modify_flow_table_in_bits { 10982 u8 opcode[0x10]; 10983 u8 reserved_at_10[0x10]; 10984 10985 u8 reserved_at_20[0x10]; 10986 u8 op_mod[0x10]; 10987 10988 u8 other_vport[0x1]; 10989 u8 reserved_at_41[0xf]; 10990 u8 vport_number[0x10]; 10991 10992 u8 reserved_at_60[0x10]; 10993 u8 modify_field_select[0x10]; 10994 10995 u8 table_type[0x8]; 10996 u8 reserved_at_88[0x18]; 10997 10998 u8 reserved_at_a0[0x8]; 10999 u8 table_id[0x18]; 11000 11001 struct mlx5_ifc_flow_table_context_bits flow_table_context; 11002 }; 11003 11004 struct mlx5_ifc_ets_tcn_config_reg_bits { 11005 u8 g[0x1]; 11006 u8 b[0x1]; 11007 u8 r[0x1]; 11008 u8 reserved_at_3[0x9]; 11009 u8 group[0x4]; 11010 u8 reserved_at_10[0x9]; 11011 u8 bw_allocation[0x7]; 11012 11013 u8 reserved_at_20[0xc]; 11014 u8 max_bw_units[0x4]; 11015 u8 reserved_at_30[0x8]; 11016 u8 max_bw_value[0x8]; 11017 }; 11018 11019 struct mlx5_ifc_ets_global_config_reg_bits { 11020 u8 reserved_at_0[0x2]; 11021 u8 r[0x1]; 11022 u8 reserved_at_3[0x1d]; 11023 11024 u8 reserved_at_20[0xc]; 11025 u8 max_bw_units[0x4]; 11026 u8 reserved_at_30[0x8]; 11027 u8 max_bw_value[0x8]; 11028 }; 11029 11030 struct mlx5_ifc_qetc_reg_bits { 11031 u8 reserved_at_0[0x8]; 11032 u8 port_number[0x8]; 11033 u8 reserved_at_10[0x30]; 11034 11035 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8]; 11036 struct mlx5_ifc_ets_global_config_reg_bits global_configuration; 11037 }; 11038 11039 struct mlx5_ifc_qpdpm_dscp_reg_bits { 11040 u8 e[0x1]; 11041 u8 reserved_at_01[0x0b]; 11042 u8 prio[0x04]; 11043 }; 11044 11045 struct mlx5_ifc_qpdpm_reg_bits { 11046 u8 reserved_at_0[0x8]; 11047 u8 local_port[0x8]; 11048 u8 reserved_at_10[0x10]; 11049 struct mlx5_ifc_qpdpm_dscp_reg_bits dscp[64]; 11050 }; 11051 11052 struct mlx5_ifc_qpts_reg_bits { 11053 u8 reserved_at_0[0x8]; 11054 u8 local_port[0x8]; 11055 u8 reserved_at_10[0x2d]; 11056 u8 trust_state[0x3]; 11057 }; 11058 11059 struct mlx5_ifc_pptb_reg_bits { 11060 u8 reserved_at_0[0x2]; 11061 u8 mm[0x2]; 11062 u8 reserved_at_4[0x4]; 11063 u8 local_port[0x8]; 11064 u8 reserved_at_10[0x6]; 11065 u8 cm[0x1]; 11066 u8 um[0x1]; 11067 u8 pm[0x8]; 11068 11069 u8 prio_x_buff[0x20]; 11070 11071 u8 pm_msb[0x8]; 11072 u8 reserved_at_48[0x10]; 11073 u8 ctrl_buff[0x4]; 11074 u8 untagged_buff[0x4]; 11075 }; 11076 11077 struct mlx5_ifc_sbcam_reg_bits { 11078 u8 reserved_at_0[0x8]; 11079 u8 feature_group[0x8]; 11080 u8 reserved_at_10[0x8]; 11081 u8 access_reg_group[0x8]; 11082 11083 u8 reserved_at_20[0x20]; 11084 11085 u8 sb_access_reg_cap_mask[4][0x20]; 11086 11087 u8 reserved_at_c0[0x80]; 11088 11089 u8 sb_feature_cap_mask[4][0x20]; 11090 11091 u8 reserved_at_1c0[0x40]; 11092 11093 u8 cap_total_buffer_size[0x20]; 11094 11095 u8 cap_cell_size[0x10]; 11096 u8 cap_max_pg_buffers[0x8]; 11097 u8 cap_num_pool_supported[0x8]; 11098 11099 u8 reserved_at_240[0x8]; 11100 u8 cap_sbsr_stat_size[0x8]; 11101 u8 cap_max_tclass_data[0x8]; 11102 u8 cap_max_cpu_ingress_tclass_sb[0x8]; 11103 }; 11104 11105 struct mlx5_ifc_pbmc_reg_bits { 11106 u8 reserved_at_0[0x8]; 11107 u8 local_port[0x8]; 11108 u8 reserved_at_10[0x10]; 11109 11110 u8 xoff_timer_value[0x10]; 11111 u8 xoff_refresh[0x10]; 11112 11113 u8 reserved_at_40[0x9]; 11114 u8 fullness_threshold[0x7]; 11115 u8 port_buffer_size[0x10]; 11116 11117 struct mlx5_ifc_bufferx_reg_bits buffer[10]; 11118 11119 u8 reserved_at_2e0[0x80]; 11120 }; 11121 11122 struct mlx5_ifc_sbpr_reg_bits { 11123 u8 desc[0x1]; 11124 u8 snap[0x1]; 11125 u8 reserved_at_2[0x4]; 11126 u8 dir[0x2]; 11127 u8 reserved_at_8[0x14]; 11128 u8 pool[0x4]; 11129 11130 u8 infi_size[0x1]; 11131 u8 reserved_at_21[0x7]; 11132 u8 size[0x18]; 11133 11134 u8 reserved_at_40[0x1c]; 11135 u8 mode[0x4]; 11136 11137 u8 reserved_at_60[0x8]; 11138 u8 buff_occupancy[0x18]; 11139 11140 u8 clr[0x1]; 11141 u8 reserved_at_81[0x7]; 11142 u8 max_buff_occupancy[0x18]; 11143 11144 u8 reserved_at_a0[0x8]; 11145 u8 ext_buff_occupancy[0x18]; 11146 }; 11147 11148 struct mlx5_ifc_sbcm_reg_bits { 11149 u8 desc[0x1]; 11150 u8 snap[0x1]; 11151 u8 reserved_at_2[0x6]; 11152 u8 local_port[0x8]; 11153 u8 pnat[0x2]; 11154 u8 pg_buff[0x6]; 11155 u8 reserved_at_18[0x6]; 11156 u8 dir[0x2]; 11157 11158 u8 reserved_at_20[0x1f]; 11159 u8 exc[0x1]; 11160 11161 u8 reserved_at_40[0x40]; 11162 11163 u8 reserved_at_80[0x8]; 11164 u8 buff_occupancy[0x18]; 11165 11166 u8 clr[0x1]; 11167 u8 reserved_at_a1[0x7]; 11168 u8 max_buff_occupancy[0x18]; 11169 11170 u8 reserved_at_c0[0x8]; 11171 u8 min_buff[0x18]; 11172 11173 u8 infi_max[0x1]; 11174 u8 reserved_at_e1[0x7]; 11175 u8 max_buff[0x18]; 11176 11177 u8 reserved_at_100[0x20]; 11178 11179 u8 reserved_at_120[0x1c]; 11180 u8 pool[0x4]; 11181 }; 11182 11183 struct mlx5_ifc_qtct_reg_bits { 11184 u8 reserved_at_0[0x8]; 11185 u8 port_number[0x8]; 11186 u8 reserved_at_10[0xd]; 11187 u8 prio[0x3]; 11188 11189 u8 reserved_at_20[0x1d]; 11190 u8 tclass[0x3]; 11191 }; 11192 11193 struct mlx5_ifc_mcia_reg_bits { 11194 u8 l[0x1]; 11195 u8 reserved_at_1[0x7]; 11196 u8 module[0x8]; 11197 u8 reserved_at_10[0x8]; 11198 u8 status[0x8]; 11199 11200 u8 i2c_device_address[0x8]; 11201 u8 page_number[0x8]; 11202 u8 device_address[0x10]; 11203 11204 u8 reserved_at_40[0x10]; 11205 u8 size[0x10]; 11206 11207 u8 reserved_at_60[0x20]; 11208 11209 u8 dword_0[0x20]; 11210 u8 dword_1[0x20]; 11211 u8 dword_2[0x20]; 11212 u8 dword_3[0x20]; 11213 u8 dword_4[0x20]; 11214 u8 dword_5[0x20]; 11215 u8 dword_6[0x20]; 11216 u8 dword_7[0x20]; 11217 u8 dword_8[0x20]; 11218 u8 dword_9[0x20]; 11219 u8 dword_10[0x20]; 11220 u8 dword_11[0x20]; 11221 }; 11222 11223 struct mlx5_ifc_dcbx_param_bits { 11224 u8 dcbx_cee_cap[0x1]; 11225 u8 dcbx_ieee_cap[0x1]; 11226 u8 dcbx_standby_cap[0x1]; 11227 u8 reserved_at_3[0x5]; 11228 u8 port_number[0x8]; 11229 u8 reserved_at_10[0xa]; 11230 u8 max_application_table_size[6]; 11231 u8 reserved_at_20[0x15]; 11232 u8 version_oper[0x3]; 11233 u8 reserved_at_38[5]; 11234 u8 version_admin[0x3]; 11235 u8 willing_admin[0x1]; 11236 u8 reserved_at_41[0x3]; 11237 u8 pfc_cap_oper[0x4]; 11238 u8 reserved_at_48[0x4]; 11239 u8 pfc_cap_admin[0x4]; 11240 u8 reserved_at_50[0x4]; 11241 u8 num_of_tc_oper[0x4]; 11242 u8 reserved_at_58[0x4]; 11243 u8 num_of_tc_admin[0x4]; 11244 u8 remote_willing[0x1]; 11245 u8 reserved_at_61[3]; 11246 u8 remote_pfc_cap[4]; 11247 u8 reserved_at_68[0x14]; 11248 u8 remote_num_of_tc[0x4]; 11249 u8 reserved_at_80[0x18]; 11250 u8 error[0x8]; 11251 u8 reserved_at_a0[0x160]; 11252 }; 11253 11254 enum { 11255 MLX5_LAG_PORT_SELECT_MODE_QUEUE_AFFINITY = 0, 11256 MLX5_LAG_PORT_SELECT_MODE_PORT_SELECT_FT = 1, 11257 MLX5_LAG_PORT_SELECT_MODE_PORT_SELECT_MPESW = 2, 11258 }; 11259 11260 struct mlx5_ifc_lagc_bits { 11261 u8 fdb_selection_mode[0x1]; 11262 u8 reserved_at_1[0x14]; 11263 u8 port_select_mode[0x3]; 11264 u8 reserved_at_18[0x5]; 11265 u8 lag_state[0x3]; 11266 11267 u8 reserved_at_20[0xc]; 11268 u8 active_port[0x4]; 11269 u8 reserved_at_30[0x4]; 11270 u8 tx_remap_affinity_2[0x4]; 11271 u8 reserved_at_38[0x4]; 11272 u8 tx_remap_affinity_1[0x4]; 11273 }; 11274 11275 struct mlx5_ifc_create_lag_out_bits { 11276 u8 status[0x8]; 11277 u8 reserved_at_8[0x18]; 11278 11279 u8 syndrome[0x20]; 11280 11281 u8 reserved_at_40[0x40]; 11282 }; 11283 11284 struct mlx5_ifc_create_lag_in_bits { 11285 u8 opcode[0x10]; 11286 u8 reserved_at_10[0x10]; 11287 11288 u8 reserved_at_20[0x10]; 11289 u8 op_mod[0x10]; 11290 11291 struct mlx5_ifc_lagc_bits ctx; 11292 }; 11293 11294 struct mlx5_ifc_modify_lag_out_bits { 11295 u8 status[0x8]; 11296 u8 reserved_at_8[0x18]; 11297 11298 u8 syndrome[0x20]; 11299 11300 u8 reserved_at_40[0x40]; 11301 }; 11302 11303 struct mlx5_ifc_modify_lag_in_bits { 11304 u8 opcode[0x10]; 11305 u8 reserved_at_10[0x10]; 11306 11307 u8 reserved_at_20[0x10]; 11308 u8 op_mod[0x10]; 11309 11310 u8 reserved_at_40[0x20]; 11311 u8 field_select[0x20]; 11312 11313 struct mlx5_ifc_lagc_bits ctx; 11314 }; 11315 11316 struct mlx5_ifc_query_lag_out_bits { 11317 u8 status[0x8]; 11318 u8 reserved_at_8[0x18]; 11319 11320 u8 syndrome[0x20]; 11321 11322 struct mlx5_ifc_lagc_bits ctx; 11323 }; 11324 11325 struct mlx5_ifc_query_lag_in_bits { 11326 u8 opcode[0x10]; 11327 u8 reserved_at_10[0x10]; 11328 11329 u8 reserved_at_20[0x10]; 11330 u8 op_mod[0x10]; 11331 11332 u8 reserved_at_40[0x40]; 11333 }; 11334 11335 struct mlx5_ifc_destroy_lag_out_bits { 11336 u8 status[0x8]; 11337 u8 reserved_at_8[0x18]; 11338 11339 u8 syndrome[0x20]; 11340 11341 u8 reserved_at_40[0x40]; 11342 }; 11343 11344 struct mlx5_ifc_destroy_lag_in_bits { 11345 u8 opcode[0x10]; 11346 u8 reserved_at_10[0x10]; 11347 11348 u8 reserved_at_20[0x10]; 11349 u8 op_mod[0x10]; 11350 11351 u8 reserved_at_40[0x40]; 11352 }; 11353 11354 struct mlx5_ifc_create_vport_lag_out_bits { 11355 u8 status[0x8]; 11356 u8 reserved_at_8[0x18]; 11357 11358 u8 syndrome[0x20]; 11359 11360 u8 reserved_at_40[0x40]; 11361 }; 11362 11363 struct mlx5_ifc_create_vport_lag_in_bits { 11364 u8 opcode[0x10]; 11365 u8 reserved_at_10[0x10]; 11366 11367 u8 reserved_at_20[0x10]; 11368 u8 op_mod[0x10]; 11369 11370 u8 reserved_at_40[0x40]; 11371 }; 11372 11373 struct mlx5_ifc_destroy_vport_lag_out_bits { 11374 u8 status[0x8]; 11375 u8 reserved_at_8[0x18]; 11376 11377 u8 syndrome[0x20]; 11378 11379 u8 reserved_at_40[0x40]; 11380 }; 11381 11382 struct mlx5_ifc_destroy_vport_lag_in_bits { 11383 u8 opcode[0x10]; 11384 u8 reserved_at_10[0x10]; 11385 11386 u8 reserved_at_20[0x10]; 11387 u8 op_mod[0x10]; 11388 11389 u8 reserved_at_40[0x40]; 11390 }; 11391 11392 enum { 11393 MLX5_MODIFY_MEMIC_OP_MOD_ALLOC, 11394 MLX5_MODIFY_MEMIC_OP_MOD_DEALLOC, 11395 }; 11396 11397 struct mlx5_ifc_modify_memic_in_bits { 11398 u8 opcode[0x10]; 11399 u8 uid[0x10]; 11400 11401 u8 reserved_at_20[0x10]; 11402 u8 op_mod[0x10]; 11403 11404 u8 reserved_at_40[0x20]; 11405 11406 u8 reserved_at_60[0x18]; 11407 u8 memic_operation_type[0x8]; 11408 11409 u8 memic_start_addr[0x40]; 11410 11411 u8 reserved_at_c0[0x140]; 11412 }; 11413 11414 struct mlx5_ifc_modify_memic_out_bits { 11415 u8 status[0x8]; 11416 u8 reserved_at_8[0x18]; 11417 11418 u8 syndrome[0x20]; 11419 11420 u8 reserved_at_40[0x40]; 11421 11422 u8 memic_operation_addr[0x40]; 11423 11424 u8 reserved_at_c0[0x140]; 11425 }; 11426 11427 struct mlx5_ifc_alloc_memic_in_bits { 11428 u8 opcode[0x10]; 11429 u8 reserved_at_10[0x10]; 11430 11431 u8 reserved_at_20[0x10]; 11432 u8 op_mod[0x10]; 11433 11434 u8 reserved_at_30[0x20]; 11435 11436 u8 reserved_at_40[0x18]; 11437 u8 log_memic_addr_alignment[0x8]; 11438 11439 u8 range_start_addr[0x40]; 11440 11441 u8 range_size[0x20]; 11442 11443 u8 memic_size[0x20]; 11444 }; 11445 11446 struct mlx5_ifc_alloc_memic_out_bits { 11447 u8 status[0x8]; 11448 u8 reserved_at_8[0x18]; 11449 11450 u8 syndrome[0x20]; 11451 11452 u8 memic_start_addr[0x40]; 11453 }; 11454 11455 struct mlx5_ifc_dealloc_memic_in_bits { 11456 u8 opcode[0x10]; 11457 u8 reserved_at_10[0x10]; 11458 11459 u8 reserved_at_20[0x10]; 11460 u8 op_mod[0x10]; 11461 11462 u8 reserved_at_40[0x40]; 11463 11464 u8 memic_start_addr[0x40]; 11465 11466 u8 memic_size[0x20]; 11467 11468 u8 reserved_at_e0[0x20]; 11469 }; 11470 11471 struct mlx5_ifc_dealloc_memic_out_bits { 11472 u8 status[0x8]; 11473 u8 reserved_at_8[0x18]; 11474 11475 u8 syndrome[0x20]; 11476 11477 u8 reserved_at_40[0x40]; 11478 }; 11479 11480 struct mlx5_ifc_umem_bits { 11481 u8 reserved_at_0[0x80]; 11482 11483 u8 ats[0x1]; 11484 u8 reserved_at_81[0x1a]; 11485 u8 log_page_size[0x5]; 11486 11487 u8 page_offset[0x20]; 11488 11489 u8 num_of_mtt[0x40]; 11490 11491 struct mlx5_ifc_mtt_bits mtt[]; 11492 }; 11493 11494 struct mlx5_ifc_uctx_bits { 11495 u8 cap[0x20]; 11496 11497 u8 reserved_at_20[0x160]; 11498 }; 11499 11500 struct mlx5_ifc_sw_icm_bits { 11501 u8 modify_field_select[0x40]; 11502 11503 u8 reserved_at_40[0x18]; 11504 u8 log_sw_icm_size[0x8]; 11505 11506 u8 reserved_at_60[0x20]; 11507 11508 u8 sw_icm_start_addr[0x40]; 11509 11510 u8 reserved_at_c0[0x140]; 11511 }; 11512 11513 struct mlx5_ifc_geneve_tlv_option_bits { 11514 u8 modify_field_select[0x40]; 11515 11516 u8 reserved_at_40[0x18]; 11517 u8 geneve_option_fte_index[0x8]; 11518 11519 u8 option_class[0x10]; 11520 u8 option_type[0x8]; 11521 u8 reserved_at_78[0x3]; 11522 u8 option_data_length[0x5]; 11523 11524 u8 reserved_at_80[0x180]; 11525 }; 11526 11527 struct mlx5_ifc_create_umem_in_bits { 11528 u8 opcode[0x10]; 11529 u8 uid[0x10]; 11530 11531 u8 reserved_at_20[0x10]; 11532 u8 op_mod[0x10]; 11533 11534 u8 reserved_at_40[0x40]; 11535 11536 struct mlx5_ifc_umem_bits umem; 11537 }; 11538 11539 struct mlx5_ifc_create_umem_out_bits { 11540 u8 status[0x8]; 11541 u8 reserved_at_8[0x18]; 11542 11543 u8 syndrome[0x20]; 11544 11545 u8 reserved_at_40[0x8]; 11546 u8 umem_id[0x18]; 11547 11548 u8 reserved_at_60[0x20]; 11549 }; 11550 11551 struct mlx5_ifc_destroy_umem_in_bits { 11552 u8 opcode[0x10]; 11553 u8 uid[0x10]; 11554 11555 u8 reserved_at_20[0x10]; 11556 u8 op_mod[0x10]; 11557 11558 u8 reserved_at_40[0x8]; 11559 u8 umem_id[0x18]; 11560 11561 u8 reserved_at_60[0x20]; 11562 }; 11563 11564 struct mlx5_ifc_destroy_umem_out_bits { 11565 u8 status[0x8]; 11566 u8 reserved_at_8[0x18]; 11567 11568 u8 syndrome[0x20]; 11569 11570 u8 reserved_at_40[0x40]; 11571 }; 11572 11573 struct mlx5_ifc_create_uctx_in_bits { 11574 u8 opcode[0x10]; 11575 u8 reserved_at_10[0x10]; 11576 11577 u8 reserved_at_20[0x10]; 11578 u8 op_mod[0x10]; 11579 11580 u8 reserved_at_40[0x40]; 11581 11582 struct mlx5_ifc_uctx_bits uctx; 11583 }; 11584 11585 struct mlx5_ifc_create_uctx_out_bits { 11586 u8 status[0x8]; 11587 u8 reserved_at_8[0x18]; 11588 11589 u8 syndrome[0x20]; 11590 11591 u8 reserved_at_40[0x10]; 11592 u8 uid[0x10]; 11593 11594 u8 reserved_at_60[0x20]; 11595 }; 11596 11597 struct mlx5_ifc_destroy_uctx_in_bits { 11598 u8 opcode[0x10]; 11599 u8 reserved_at_10[0x10]; 11600 11601 u8 reserved_at_20[0x10]; 11602 u8 op_mod[0x10]; 11603 11604 u8 reserved_at_40[0x10]; 11605 u8 uid[0x10]; 11606 11607 u8 reserved_at_60[0x20]; 11608 }; 11609 11610 struct mlx5_ifc_destroy_uctx_out_bits { 11611 u8 status[0x8]; 11612 u8 reserved_at_8[0x18]; 11613 11614 u8 syndrome[0x20]; 11615 11616 u8 reserved_at_40[0x40]; 11617 }; 11618 11619 struct mlx5_ifc_create_sw_icm_in_bits { 11620 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 11621 struct mlx5_ifc_sw_icm_bits sw_icm; 11622 }; 11623 11624 struct mlx5_ifc_create_geneve_tlv_option_in_bits { 11625 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 11626 struct mlx5_ifc_geneve_tlv_option_bits geneve_tlv_opt; 11627 }; 11628 11629 struct mlx5_ifc_mtrc_string_db_param_bits { 11630 u8 string_db_base_address[0x20]; 11631 11632 u8 reserved_at_20[0x8]; 11633 u8 string_db_size[0x18]; 11634 }; 11635 11636 struct mlx5_ifc_mtrc_cap_bits { 11637 u8 trace_owner[0x1]; 11638 u8 trace_to_memory[0x1]; 11639 u8 reserved_at_2[0x4]; 11640 u8 trc_ver[0x2]; 11641 u8 reserved_at_8[0x14]; 11642 u8 num_string_db[0x4]; 11643 11644 u8 first_string_trace[0x8]; 11645 u8 num_string_trace[0x8]; 11646 u8 reserved_at_30[0x28]; 11647 11648 u8 log_max_trace_buffer_size[0x8]; 11649 11650 u8 reserved_at_60[0x20]; 11651 11652 struct mlx5_ifc_mtrc_string_db_param_bits string_db_param[8]; 11653 11654 u8 reserved_at_280[0x180]; 11655 }; 11656 11657 struct mlx5_ifc_mtrc_conf_bits { 11658 u8 reserved_at_0[0x1c]; 11659 u8 trace_mode[0x4]; 11660 u8 reserved_at_20[0x18]; 11661 u8 log_trace_buffer_size[0x8]; 11662 u8 trace_mkey[0x20]; 11663 u8 reserved_at_60[0x3a0]; 11664 }; 11665 11666 struct mlx5_ifc_mtrc_stdb_bits { 11667 u8 string_db_index[0x4]; 11668 u8 reserved_at_4[0x4]; 11669 u8 read_size[0x18]; 11670 u8 start_offset[0x20]; 11671 u8 string_db_data[]; 11672 }; 11673 11674 struct mlx5_ifc_mtrc_ctrl_bits { 11675 u8 trace_status[0x2]; 11676 u8 reserved_at_2[0x2]; 11677 u8 arm_event[0x1]; 11678 u8 reserved_at_5[0xb]; 11679 u8 modify_field_select[0x10]; 11680 u8 reserved_at_20[0x2b]; 11681 u8 current_timestamp52_32[0x15]; 11682 u8 current_timestamp31_0[0x20]; 11683 u8 reserved_at_80[0x180]; 11684 }; 11685 11686 struct mlx5_ifc_host_params_context_bits { 11687 u8 host_number[0x8]; 11688 u8 reserved_at_8[0x7]; 11689 u8 host_pf_disabled[0x1]; 11690 u8 host_num_of_vfs[0x10]; 11691 11692 u8 host_total_vfs[0x10]; 11693 u8 host_pci_bus[0x10]; 11694 11695 u8 reserved_at_40[0x10]; 11696 u8 host_pci_device[0x10]; 11697 11698 u8 reserved_at_60[0x10]; 11699 u8 host_pci_function[0x10]; 11700 11701 u8 reserved_at_80[0x180]; 11702 }; 11703 11704 struct mlx5_ifc_query_esw_functions_in_bits { 11705 u8 opcode[0x10]; 11706 u8 reserved_at_10[0x10]; 11707 11708 u8 reserved_at_20[0x10]; 11709 u8 op_mod[0x10]; 11710 11711 u8 reserved_at_40[0x40]; 11712 }; 11713 11714 struct mlx5_ifc_query_esw_functions_out_bits { 11715 u8 status[0x8]; 11716 u8 reserved_at_8[0x18]; 11717 11718 u8 syndrome[0x20]; 11719 11720 u8 reserved_at_40[0x40]; 11721 11722 struct mlx5_ifc_host_params_context_bits host_params_context; 11723 11724 u8 reserved_at_280[0x180]; 11725 u8 host_sf_enable[][0x40]; 11726 }; 11727 11728 struct mlx5_ifc_sf_partition_bits { 11729 u8 reserved_at_0[0x10]; 11730 u8 log_num_sf[0x8]; 11731 u8 log_sf_bar_size[0x8]; 11732 }; 11733 11734 struct mlx5_ifc_query_sf_partitions_out_bits { 11735 u8 status[0x8]; 11736 u8 reserved_at_8[0x18]; 11737 11738 u8 syndrome[0x20]; 11739 11740 u8 reserved_at_40[0x18]; 11741 u8 num_sf_partitions[0x8]; 11742 11743 u8 reserved_at_60[0x20]; 11744 11745 struct mlx5_ifc_sf_partition_bits sf_partition[]; 11746 }; 11747 11748 struct mlx5_ifc_query_sf_partitions_in_bits { 11749 u8 opcode[0x10]; 11750 u8 reserved_at_10[0x10]; 11751 11752 u8 reserved_at_20[0x10]; 11753 u8 op_mod[0x10]; 11754 11755 u8 reserved_at_40[0x40]; 11756 }; 11757 11758 struct mlx5_ifc_dealloc_sf_out_bits { 11759 u8 status[0x8]; 11760 u8 reserved_at_8[0x18]; 11761 11762 u8 syndrome[0x20]; 11763 11764 u8 reserved_at_40[0x40]; 11765 }; 11766 11767 struct mlx5_ifc_dealloc_sf_in_bits { 11768 u8 opcode[0x10]; 11769 u8 reserved_at_10[0x10]; 11770 11771 u8 reserved_at_20[0x10]; 11772 u8 op_mod[0x10]; 11773 11774 u8 reserved_at_40[0x10]; 11775 u8 function_id[0x10]; 11776 11777 u8 reserved_at_60[0x20]; 11778 }; 11779 11780 struct mlx5_ifc_alloc_sf_out_bits { 11781 u8 status[0x8]; 11782 u8 reserved_at_8[0x18]; 11783 11784 u8 syndrome[0x20]; 11785 11786 u8 reserved_at_40[0x40]; 11787 }; 11788 11789 struct mlx5_ifc_alloc_sf_in_bits { 11790 u8 opcode[0x10]; 11791 u8 reserved_at_10[0x10]; 11792 11793 u8 reserved_at_20[0x10]; 11794 u8 op_mod[0x10]; 11795 11796 u8 reserved_at_40[0x10]; 11797 u8 function_id[0x10]; 11798 11799 u8 reserved_at_60[0x20]; 11800 }; 11801 11802 struct mlx5_ifc_affiliated_event_header_bits { 11803 u8 reserved_at_0[0x10]; 11804 u8 obj_type[0x10]; 11805 11806 u8 obj_id[0x20]; 11807 }; 11808 11809 enum { 11810 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = BIT_ULL(0xc), 11811 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_IPSEC = BIT_ULL(0x13), 11812 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_SAMPLER = BIT_ULL(0x20), 11813 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_FLOW_METER_ASO = BIT_ULL(0x24), 11814 }; 11815 11816 enum { 11817 MLX5_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = 0xc, 11818 MLX5_GENERAL_OBJECT_TYPES_IPSEC = 0x13, 11819 MLX5_GENERAL_OBJECT_TYPES_SAMPLER = 0x20, 11820 MLX5_GENERAL_OBJECT_TYPES_FLOW_METER_ASO = 0x24, 11821 MLX5_GENERAL_OBJECT_TYPES_MACSEC = 0x27, 11822 MLX5_GENERAL_OBJECT_TYPES_INT_KEK = 0x47, 11823 }; 11824 11825 enum { 11826 MLX5_IPSEC_OBJECT_ICV_LEN_16B, 11827 }; 11828 11829 enum { 11830 MLX5_IPSEC_ASO_REG_C_0_1 = 0x0, 11831 MLX5_IPSEC_ASO_REG_C_2_3 = 0x1, 11832 MLX5_IPSEC_ASO_REG_C_4_5 = 0x2, 11833 MLX5_IPSEC_ASO_REG_C_6_7 = 0x3, 11834 }; 11835 11836 enum { 11837 MLX5_IPSEC_ASO_MODE = 0x0, 11838 MLX5_IPSEC_ASO_REPLAY_PROTECTION = 0x1, 11839 MLX5_IPSEC_ASO_INC_SN = 0x2, 11840 }; 11841 11842 struct mlx5_ifc_ipsec_aso_bits { 11843 u8 valid[0x1]; 11844 u8 reserved_at_201[0x1]; 11845 u8 mode[0x2]; 11846 u8 window_sz[0x2]; 11847 u8 soft_lft_arm[0x1]; 11848 u8 hard_lft_arm[0x1]; 11849 u8 remove_flow_enable[0x1]; 11850 u8 esn_event_arm[0x1]; 11851 u8 reserved_at_20a[0x16]; 11852 11853 u8 remove_flow_pkt_cnt[0x20]; 11854 11855 u8 remove_flow_soft_lft[0x20]; 11856 11857 u8 reserved_at_260[0x80]; 11858 11859 u8 mode_parameter[0x20]; 11860 11861 u8 replay_protection_window[0x100]; 11862 }; 11863 11864 struct mlx5_ifc_ipsec_obj_bits { 11865 u8 modify_field_select[0x40]; 11866 u8 full_offload[0x1]; 11867 u8 reserved_at_41[0x1]; 11868 u8 esn_en[0x1]; 11869 u8 esn_overlap[0x1]; 11870 u8 reserved_at_44[0x2]; 11871 u8 icv_length[0x2]; 11872 u8 reserved_at_48[0x4]; 11873 u8 aso_return_reg[0x4]; 11874 u8 reserved_at_50[0x10]; 11875 11876 u8 esn_msb[0x20]; 11877 11878 u8 reserved_at_80[0x8]; 11879 u8 dekn[0x18]; 11880 11881 u8 salt[0x20]; 11882 11883 u8 implicit_iv[0x40]; 11884 11885 u8 reserved_at_100[0x8]; 11886 u8 ipsec_aso_access_pd[0x18]; 11887 u8 reserved_at_120[0xe0]; 11888 11889 struct mlx5_ifc_ipsec_aso_bits ipsec_aso; 11890 }; 11891 11892 struct mlx5_ifc_create_ipsec_obj_in_bits { 11893 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 11894 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 11895 }; 11896 11897 enum { 11898 MLX5_MODIFY_IPSEC_BITMASK_ESN_OVERLAP = BIT(0), 11899 MLX5_MODIFY_IPSEC_BITMASK_ESN_MSB = BIT(1), 11900 }; 11901 11902 struct mlx5_ifc_query_ipsec_obj_out_bits { 11903 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 11904 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 11905 }; 11906 11907 struct mlx5_ifc_modify_ipsec_obj_in_bits { 11908 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 11909 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 11910 }; 11911 11912 enum { 11913 MLX5_MACSEC_ASO_REPLAY_PROTECTION = 0x1, 11914 }; 11915 11916 enum { 11917 MLX5_MACSEC_ASO_REPLAY_WIN_32BIT = 0x0, 11918 MLX5_MACSEC_ASO_REPLAY_WIN_64BIT = 0x1, 11919 MLX5_MACSEC_ASO_REPLAY_WIN_128BIT = 0x2, 11920 MLX5_MACSEC_ASO_REPLAY_WIN_256BIT = 0x3, 11921 }; 11922 11923 #define MLX5_MACSEC_ASO_INC_SN 0x2 11924 #define MLX5_MACSEC_ASO_REG_C_4_5 0x2 11925 11926 struct mlx5_ifc_macsec_aso_bits { 11927 u8 valid[0x1]; 11928 u8 reserved_at_1[0x1]; 11929 u8 mode[0x2]; 11930 u8 window_size[0x2]; 11931 u8 soft_lifetime_arm[0x1]; 11932 u8 hard_lifetime_arm[0x1]; 11933 u8 remove_flow_enable[0x1]; 11934 u8 epn_event_arm[0x1]; 11935 u8 reserved_at_a[0x16]; 11936 11937 u8 remove_flow_packet_count[0x20]; 11938 11939 u8 remove_flow_soft_lifetime[0x20]; 11940 11941 u8 reserved_at_60[0x80]; 11942 11943 u8 mode_parameter[0x20]; 11944 11945 u8 replay_protection_window[8][0x20]; 11946 }; 11947 11948 struct mlx5_ifc_macsec_offload_obj_bits { 11949 u8 modify_field_select[0x40]; 11950 11951 u8 confidentiality_en[0x1]; 11952 u8 reserved_at_41[0x1]; 11953 u8 epn_en[0x1]; 11954 u8 epn_overlap[0x1]; 11955 u8 reserved_at_44[0x2]; 11956 u8 confidentiality_offset[0x2]; 11957 u8 reserved_at_48[0x4]; 11958 u8 aso_return_reg[0x4]; 11959 u8 reserved_at_50[0x10]; 11960 11961 u8 epn_msb[0x20]; 11962 11963 u8 reserved_at_80[0x8]; 11964 u8 dekn[0x18]; 11965 11966 u8 reserved_at_a0[0x20]; 11967 11968 u8 sci[0x40]; 11969 11970 u8 reserved_at_100[0x8]; 11971 u8 macsec_aso_access_pd[0x18]; 11972 11973 u8 reserved_at_120[0x60]; 11974 11975 u8 salt[3][0x20]; 11976 11977 u8 reserved_at_1e0[0x20]; 11978 11979 struct mlx5_ifc_macsec_aso_bits macsec_aso; 11980 }; 11981 11982 struct mlx5_ifc_create_macsec_obj_in_bits { 11983 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 11984 struct mlx5_ifc_macsec_offload_obj_bits macsec_object; 11985 }; 11986 11987 struct mlx5_ifc_modify_macsec_obj_in_bits { 11988 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 11989 struct mlx5_ifc_macsec_offload_obj_bits macsec_object; 11990 }; 11991 11992 enum { 11993 MLX5_MODIFY_MACSEC_BITMASK_EPN_OVERLAP = BIT(0), 11994 MLX5_MODIFY_MACSEC_BITMASK_EPN_MSB = BIT(1), 11995 }; 11996 11997 struct mlx5_ifc_query_macsec_obj_out_bits { 11998 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 11999 struct mlx5_ifc_macsec_offload_obj_bits macsec_object; 12000 }; 12001 12002 struct mlx5_ifc_wrapped_dek_bits { 12003 u8 gcm_iv[0x60]; 12004 12005 u8 reserved_at_60[0x20]; 12006 12007 u8 const0[0x1]; 12008 u8 key_size[0x1]; 12009 u8 reserved_at_82[0x2]; 12010 u8 key2_invalid[0x1]; 12011 u8 reserved_at_85[0x3]; 12012 u8 pd[0x18]; 12013 12014 u8 key_purpose[0x5]; 12015 u8 reserved_at_a5[0x13]; 12016 u8 kek_id[0x8]; 12017 12018 u8 reserved_at_c0[0x40]; 12019 12020 u8 key1[0x8][0x20]; 12021 12022 u8 key2[0x8][0x20]; 12023 12024 u8 reserved_at_300[0x40]; 12025 12026 u8 const1[0x1]; 12027 u8 reserved_at_341[0x1f]; 12028 12029 u8 reserved_at_360[0x20]; 12030 12031 u8 auth_tag[0x80]; 12032 }; 12033 12034 struct mlx5_ifc_encryption_key_obj_bits { 12035 u8 modify_field_select[0x40]; 12036 12037 u8 state[0x8]; 12038 u8 sw_wrapped[0x1]; 12039 u8 reserved_at_49[0xb]; 12040 u8 key_size[0x4]; 12041 u8 reserved_at_58[0x4]; 12042 u8 key_purpose[0x4]; 12043 12044 u8 reserved_at_60[0x8]; 12045 u8 pd[0x18]; 12046 12047 u8 reserved_at_80[0x100]; 12048 12049 u8 opaque[0x40]; 12050 12051 u8 reserved_at_1c0[0x40]; 12052 12053 u8 key[8][0x80]; 12054 12055 u8 sw_wrapped_dek[8][0x80]; 12056 12057 u8 reserved_at_a00[0x600]; 12058 }; 12059 12060 struct mlx5_ifc_create_encryption_key_in_bits { 12061 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12062 struct mlx5_ifc_encryption_key_obj_bits encryption_key_object; 12063 }; 12064 12065 struct mlx5_ifc_modify_encryption_key_in_bits { 12066 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12067 struct mlx5_ifc_encryption_key_obj_bits encryption_key_object; 12068 }; 12069 12070 enum { 12071 MLX5_FLOW_METER_MODE_BYTES_IP_LENGTH = 0x0, 12072 MLX5_FLOW_METER_MODE_BYTES_CALC_WITH_L2 = 0x1, 12073 MLX5_FLOW_METER_MODE_BYTES_CALC_WITH_L2_IPG = 0x2, 12074 MLX5_FLOW_METER_MODE_NUM_PACKETS = 0x3, 12075 }; 12076 12077 struct mlx5_ifc_flow_meter_parameters_bits { 12078 u8 valid[0x1]; 12079 u8 bucket_overflow[0x1]; 12080 u8 start_color[0x2]; 12081 u8 both_buckets_on_green[0x1]; 12082 u8 reserved_at_5[0x1]; 12083 u8 meter_mode[0x2]; 12084 u8 reserved_at_8[0x18]; 12085 12086 u8 reserved_at_20[0x20]; 12087 12088 u8 reserved_at_40[0x3]; 12089 u8 cbs_exponent[0x5]; 12090 u8 cbs_mantissa[0x8]; 12091 u8 reserved_at_50[0x3]; 12092 u8 cir_exponent[0x5]; 12093 u8 cir_mantissa[0x8]; 12094 12095 u8 reserved_at_60[0x20]; 12096 12097 u8 reserved_at_80[0x3]; 12098 u8 ebs_exponent[0x5]; 12099 u8 ebs_mantissa[0x8]; 12100 u8 reserved_at_90[0x3]; 12101 u8 eir_exponent[0x5]; 12102 u8 eir_mantissa[0x8]; 12103 12104 u8 reserved_at_a0[0x60]; 12105 }; 12106 12107 struct mlx5_ifc_flow_meter_aso_obj_bits { 12108 u8 modify_field_select[0x40]; 12109 12110 u8 reserved_at_40[0x40]; 12111 12112 u8 reserved_at_80[0x8]; 12113 u8 meter_aso_access_pd[0x18]; 12114 12115 u8 reserved_at_a0[0x160]; 12116 12117 struct mlx5_ifc_flow_meter_parameters_bits flow_meter_parameters[2]; 12118 }; 12119 12120 struct mlx5_ifc_create_flow_meter_aso_obj_in_bits { 12121 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 12122 struct mlx5_ifc_flow_meter_aso_obj_bits flow_meter_aso_obj; 12123 }; 12124 12125 struct mlx5_ifc_int_kek_obj_bits { 12126 u8 modify_field_select[0x40]; 12127 12128 u8 state[0x8]; 12129 u8 auto_gen[0x1]; 12130 u8 reserved_at_49[0xb]; 12131 u8 key_size[0x4]; 12132 u8 reserved_at_58[0x8]; 12133 12134 u8 reserved_at_60[0x8]; 12135 u8 pd[0x18]; 12136 12137 u8 reserved_at_80[0x180]; 12138 u8 key[8][0x80]; 12139 12140 u8 reserved_at_600[0x200]; 12141 }; 12142 12143 struct mlx5_ifc_create_int_kek_obj_in_bits { 12144 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12145 struct mlx5_ifc_int_kek_obj_bits int_kek_object; 12146 }; 12147 12148 struct mlx5_ifc_create_int_kek_obj_out_bits { 12149 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 12150 struct mlx5_ifc_int_kek_obj_bits int_kek_object; 12151 }; 12152 12153 struct mlx5_ifc_sampler_obj_bits { 12154 u8 modify_field_select[0x40]; 12155 12156 u8 table_type[0x8]; 12157 u8 level[0x8]; 12158 u8 reserved_at_50[0xf]; 12159 u8 ignore_flow_level[0x1]; 12160 12161 u8 sample_ratio[0x20]; 12162 12163 u8 reserved_at_80[0x8]; 12164 u8 sample_table_id[0x18]; 12165 12166 u8 reserved_at_a0[0x8]; 12167 u8 default_table_id[0x18]; 12168 12169 u8 sw_steering_icm_address_rx[0x40]; 12170 u8 sw_steering_icm_address_tx[0x40]; 12171 12172 u8 reserved_at_140[0xa0]; 12173 }; 12174 12175 struct mlx5_ifc_create_sampler_obj_in_bits { 12176 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12177 struct mlx5_ifc_sampler_obj_bits sampler_object; 12178 }; 12179 12180 struct mlx5_ifc_query_sampler_obj_out_bits { 12181 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 12182 struct mlx5_ifc_sampler_obj_bits sampler_object; 12183 }; 12184 12185 enum { 12186 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_128 = 0x0, 12187 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_256 = 0x1, 12188 }; 12189 12190 enum { 12191 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_PURPOSE_TLS = 0x1, 12192 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_PURPOSE_IPSEC = 0x2, 12193 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_PURPOSE_MACSEC = 0x4, 12194 }; 12195 12196 struct mlx5_ifc_tls_static_params_bits { 12197 u8 const_2[0x2]; 12198 u8 tls_version[0x4]; 12199 u8 const_1[0x2]; 12200 u8 reserved_at_8[0x14]; 12201 u8 encryption_standard[0x4]; 12202 12203 u8 reserved_at_20[0x20]; 12204 12205 u8 initial_record_number[0x40]; 12206 12207 u8 resync_tcp_sn[0x20]; 12208 12209 u8 gcm_iv[0x20]; 12210 12211 u8 implicit_iv[0x40]; 12212 12213 u8 reserved_at_100[0x8]; 12214 u8 dek_index[0x18]; 12215 12216 u8 reserved_at_120[0xe0]; 12217 }; 12218 12219 struct mlx5_ifc_tls_progress_params_bits { 12220 u8 next_record_tcp_sn[0x20]; 12221 12222 u8 hw_resync_tcp_sn[0x20]; 12223 12224 u8 record_tracker_state[0x2]; 12225 u8 auth_state[0x2]; 12226 u8 reserved_at_44[0x4]; 12227 u8 hw_offset_record_number[0x18]; 12228 }; 12229 12230 enum { 12231 MLX5_MTT_PERM_READ = 1 << 0, 12232 MLX5_MTT_PERM_WRITE = 1 << 1, 12233 MLX5_MTT_PERM_RW = MLX5_MTT_PERM_READ | MLX5_MTT_PERM_WRITE, 12234 }; 12235 12236 enum { 12237 MLX5_SUSPEND_VHCA_IN_OP_MOD_SUSPEND_INITIATOR = 0x0, 12238 MLX5_SUSPEND_VHCA_IN_OP_MOD_SUSPEND_RESPONDER = 0x1, 12239 }; 12240 12241 struct mlx5_ifc_suspend_vhca_in_bits { 12242 u8 opcode[0x10]; 12243 u8 uid[0x10]; 12244 12245 u8 reserved_at_20[0x10]; 12246 u8 op_mod[0x10]; 12247 12248 u8 reserved_at_40[0x10]; 12249 u8 vhca_id[0x10]; 12250 12251 u8 reserved_at_60[0x20]; 12252 }; 12253 12254 struct mlx5_ifc_suspend_vhca_out_bits { 12255 u8 status[0x8]; 12256 u8 reserved_at_8[0x18]; 12257 12258 u8 syndrome[0x20]; 12259 12260 u8 reserved_at_40[0x40]; 12261 }; 12262 12263 enum { 12264 MLX5_RESUME_VHCA_IN_OP_MOD_RESUME_RESPONDER = 0x0, 12265 MLX5_RESUME_VHCA_IN_OP_MOD_RESUME_INITIATOR = 0x1, 12266 }; 12267 12268 struct mlx5_ifc_resume_vhca_in_bits { 12269 u8 opcode[0x10]; 12270 u8 uid[0x10]; 12271 12272 u8 reserved_at_20[0x10]; 12273 u8 op_mod[0x10]; 12274 12275 u8 reserved_at_40[0x10]; 12276 u8 vhca_id[0x10]; 12277 12278 u8 reserved_at_60[0x20]; 12279 }; 12280 12281 struct mlx5_ifc_resume_vhca_out_bits { 12282 u8 status[0x8]; 12283 u8 reserved_at_8[0x18]; 12284 12285 u8 syndrome[0x20]; 12286 12287 u8 reserved_at_40[0x40]; 12288 }; 12289 12290 struct mlx5_ifc_query_vhca_migration_state_in_bits { 12291 u8 opcode[0x10]; 12292 u8 uid[0x10]; 12293 12294 u8 reserved_at_20[0x10]; 12295 u8 op_mod[0x10]; 12296 12297 u8 incremental[0x1]; 12298 u8 reserved_at_41[0xf]; 12299 u8 vhca_id[0x10]; 12300 12301 u8 reserved_at_60[0x20]; 12302 }; 12303 12304 struct mlx5_ifc_query_vhca_migration_state_out_bits { 12305 u8 status[0x8]; 12306 u8 reserved_at_8[0x18]; 12307 12308 u8 syndrome[0x20]; 12309 12310 u8 reserved_at_40[0x40]; 12311 12312 u8 required_umem_size[0x20]; 12313 12314 u8 reserved_at_a0[0x160]; 12315 }; 12316 12317 struct mlx5_ifc_save_vhca_state_in_bits { 12318 u8 opcode[0x10]; 12319 u8 uid[0x10]; 12320 12321 u8 reserved_at_20[0x10]; 12322 u8 op_mod[0x10]; 12323 12324 u8 incremental[0x1]; 12325 u8 set_track[0x1]; 12326 u8 reserved_at_42[0xe]; 12327 u8 vhca_id[0x10]; 12328 12329 u8 reserved_at_60[0x20]; 12330 12331 u8 va[0x40]; 12332 12333 u8 mkey[0x20]; 12334 12335 u8 size[0x20]; 12336 }; 12337 12338 struct mlx5_ifc_save_vhca_state_out_bits { 12339 u8 status[0x8]; 12340 u8 reserved_at_8[0x18]; 12341 12342 u8 syndrome[0x20]; 12343 12344 u8 actual_image_size[0x20]; 12345 12346 u8 reserved_at_60[0x20]; 12347 }; 12348 12349 struct mlx5_ifc_load_vhca_state_in_bits { 12350 u8 opcode[0x10]; 12351 u8 uid[0x10]; 12352 12353 u8 reserved_at_20[0x10]; 12354 u8 op_mod[0x10]; 12355 12356 u8 reserved_at_40[0x10]; 12357 u8 vhca_id[0x10]; 12358 12359 u8 reserved_at_60[0x20]; 12360 12361 u8 va[0x40]; 12362 12363 u8 mkey[0x20]; 12364 12365 u8 size[0x20]; 12366 }; 12367 12368 struct mlx5_ifc_load_vhca_state_out_bits { 12369 u8 status[0x8]; 12370 u8 reserved_at_8[0x18]; 12371 12372 u8 syndrome[0x20]; 12373 12374 u8 reserved_at_40[0x40]; 12375 }; 12376 12377 struct mlx5_ifc_adv_virtualization_cap_bits { 12378 u8 reserved_at_0[0x3]; 12379 u8 pg_track_log_max_num[0x5]; 12380 u8 pg_track_max_num_range[0x8]; 12381 u8 pg_track_log_min_addr_space[0x8]; 12382 u8 pg_track_log_max_addr_space[0x8]; 12383 12384 u8 reserved_at_20[0x3]; 12385 u8 pg_track_log_min_msg_size[0x5]; 12386 u8 reserved_at_28[0x3]; 12387 u8 pg_track_log_max_msg_size[0x5]; 12388 u8 reserved_at_30[0x3]; 12389 u8 pg_track_log_min_page_size[0x5]; 12390 u8 reserved_at_38[0x3]; 12391 u8 pg_track_log_max_page_size[0x5]; 12392 12393 u8 reserved_at_40[0x7c0]; 12394 }; 12395 12396 struct mlx5_ifc_page_track_report_entry_bits { 12397 u8 dirty_address_high[0x20]; 12398 12399 u8 dirty_address_low[0x20]; 12400 }; 12401 12402 enum { 12403 MLX5_PAGE_TRACK_STATE_TRACKING, 12404 MLX5_PAGE_TRACK_STATE_REPORTING, 12405 MLX5_PAGE_TRACK_STATE_ERROR, 12406 }; 12407 12408 struct mlx5_ifc_page_track_range_bits { 12409 u8 start_address[0x40]; 12410 12411 u8 length[0x40]; 12412 }; 12413 12414 struct mlx5_ifc_page_track_bits { 12415 u8 modify_field_select[0x40]; 12416 12417 u8 reserved_at_40[0x10]; 12418 u8 vhca_id[0x10]; 12419 12420 u8 reserved_at_60[0x20]; 12421 12422 u8 state[0x4]; 12423 u8 track_type[0x4]; 12424 u8 log_addr_space_size[0x8]; 12425 u8 reserved_at_90[0x3]; 12426 u8 log_page_size[0x5]; 12427 u8 reserved_at_98[0x3]; 12428 u8 log_msg_size[0x5]; 12429 12430 u8 reserved_at_a0[0x8]; 12431 u8 reporting_qpn[0x18]; 12432 12433 u8 reserved_at_c0[0x18]; 12434 u8 num_ranges[0x8]; 12435 12436 u8 reserved_at_e0[0x20]; 12437 12438 u8 range_start_address[0x40]; 12439 12440 u8 length[0x40]; 12441 12442 struct mlx5_ifc_page_track_range_bits track_range[0]; 12443 }; 12444 12445 struct mlx5_ifc_create_page_track_obj_in_bits { 12446 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12447 struct mlx5_ifc_page_track_bits obj_context; 12448 }; 12449 12450 struct mlx5_ifc_modify_page_track_obj_in_bits { 12451 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12452 struct mlx5_ifc_page_track_bits obj_context; 12453 }; 12454 12455 #endif /* MLX5_IFC_H */ 12456