1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 #ifndef MLX5_IFC_H 33 #define MLX5_IFC_H 34 35 #include "mlx5_ifc_fpga.h" 36 37 enum { 38 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0, 39 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1, 40 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2, 41 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3, 42 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13, 43 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14, 44 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c, 45 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d, 46 MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4, 47 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5, 48 MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED = 0x7, 49 MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT = 0xc, 50 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10, 51 MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR = 0x11, 52 MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR = 0x12, 53 MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR = 0x8, 54 MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE = 0x9, 55 MLX5_EVENT_TYPE_CODING_GPIO_EVENT = 0x15, 56 MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19, 57 MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a, 58 MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT = 0x1b, 59 MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT = 0x1f, 60 MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa, 61 MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb, 62 MLX5_EVENT_TYPE_CODING_FPGA_ERROR = 0x20, 63 MLX5_EVENT_TYPE_CODING_FPGA_QP_ERROR = 0x21 64 }; 65 66 enum { 67 MLX5_MODIFY_TIR_BITMASK_LRO = 0x0, 68 MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE = 0x1, 69 MLX5_MODIFY_TIR_BITMASK_HASH = 0x2, 70 MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN = 0x3 71 }; 72 73 enum { 74 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0, 75 MLX5_SET_HCA_CAP_OP_MOD_ODP = 0x2, 76 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3, 77 MLX5_SET_HCA_CAP_OP_MOD_ROCE = 0x4, 78 }; 79 80 enum { 81 MLX5_SHARED_RESOURCE_UID = 0xffff, 82 }; 83 84 enum { 85 MLX5_OBJ_TYPE_SW_ICM = 0x0008, 86 }; 87 88 enum { 89 MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM = (1ULL << MLX5_OBJ_TYPE_SW_ICM), 90 MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT = (1ULL << 11), 91 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q = (1ULL << 13), 92 }; 93 94 enum { 95 MLX5_OBJ_TYPE_GENEVE_TLV_OPT = 0x000b, 96 MLX5_OBJ_TYPE_VIRTIO_NET_Q = 0x000d, 97 MLX5_OBJ_TYPE_MATCH_DEFINER = 0x0018, 98 MLX5_OBJ_TYPE_MKEY = 0xff01, 99 MLX5_OBJ_TYPE_QP = 0xff02, 100 MLX5_OBJ_TYPE_PSV = 0xff03, 101 MLX5_OBJ_TYPE_RMP = 0xff04, 102 MLX5_OBJ_TYPE_XRC_SRQ = 0xff05, 103 MLX5_OBJ_TYPE_RQ = 0xff06, 104 MLX5_OBJ_TYPE_SQ = 0xff07, 105 MLX5_OBJ_TYPE_TIR = 0xff08, 106 MLX5_OBJ_TYPE_TIS = 0xff09, 107 MLX5_OBJ_TYPE_DCT = 0xff0a, 108 MLX5_OBJ_TYPE_XRQ = 0xff0b, 109 MLX5_OBJ_TYPE_RQT = 0xff0e, 110 MLX5_OBJ_TYPE_FLOW_COUNTER = 0xff0f, 111 MLX5_OBJ_TYPE_CQ = 0xff10, 112 }; 113 114 enum { 115 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100, 116 MLX5_CMD_OP_QUERY_ADAPTER = 0x101, 117 MLX5_CMD_OP_INIT_HCA = 0x102, 118 MLX5_CMD_OP_TEARDOWN_HCA = 0x103, 119 MLX5_CMD_OP_ENABLE_HCA = 0x104, 120 MLX5_CMD_OP_DISABLE_HCA = 0x105, 121 MLX5_CMD_OP_QUERY_PAGES = 0x107, 122 MLX5_CMD_OP_MANAGE_PAGES = 0x108, 123 MLX5_CMD_OP_SET_HCA_CAP = 0x109, 124 MLX5_CMD_OP_QUERY_ISSI = 0x10a, 125 MLX5_CMD_OP_SET_ISSI = 0x10b, 126 MLX5_CMD_OP_SET_DRIVER_VERSION = 0x10d, 127 MLX5_CMD_OP_QUERY_SF_PARTITION = 0x111, 128 MLX5_CMD_OP_ALLOC_SF = 0x113, 129 MLX5_CMD_OP_DEALLOC_SF = 0x114, 130 MLX5_CMD_OP_CREATE_MKEY = 0x200, 131 MLX5_CMD_OP_QUERY_MKEY = 0x201, 132 MLX5_CMD_OP_DESTROY_MKEY = 0x202, 133 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203, 134 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204, 135 MLX5_CMD_OP_ALLOC_MEMIC = 0x205, 136 MLX5_CMD_OP_DEALLOC_MEMIC = 0x206, 137 MLX5_CMD_OP_MODIFY_MEMIC = 0x207, 138 MLX5_CMD_OP_CREATE_EQ = 0x301, 139 MLX5_CMD_OP_DESTROY_EQ = 0x302, 140 MLX5_CMD_OP_QUERY_EQ = 0x303, 141 MLX5_CMD_OP_GEN_EQE = 0x304, 142 MLX5_CMD_OP_CREATE_CQ = 0x400, 143 MLX5_CMD_OP_DESTROY_CQ = 0x401, 144 MLX5_CMD_OP_QUERY_CQ = 0x402, 145 MLX5_CMD_OP_MODIFY_CQ = 0x403, 146 MLX5_CMD_OP_CREATE_QP = 0x500, 147 MLX5_CMD_OP_DESTROY_QP = 0x501, 148 MLX5_CMD_OP_RST2INIT_QP = 0x502, 149 MLX5_CMD_OP_INIT2RTR_QP = 0x503, 150 MLX5_CMD_OP_RTR2RTS_QP = 0x504, 151 MLX5_CMD_OP_RTS2RTS_QP = 0x505, 152 MLX5_CMD_OP_SQERR2RTS_QP = 0x506, 153 MLX5_CMD_OP_2ERR_QP = 0x507, 154 MLX5_CMD_OP_2RST_QP = 0x50a, 155 MLX5_CMD_OP_QUERY_QP = 0x50b, 156 MLX5_CMD_OP_SQD_RTS_QP = 0x50c, 157 MLX5_CMD_OP_INIT2INIT_QP = 0x50e, 158 MLX5_CMD_OP_CREATE_PSV = 0x600, 159 MLX5_CMD_OP_DESTROY_PSV = 0x601, 160 MLX5_CMD_OP_CREATE_SRQ = 0x700, 161 MLX5_CMD_OP_DESTROY_SRQ = 0x701, 162 MLX5_CMD_OP_QUERY_SRQ = 0x702, 163 MLX5_CMD_OP_ARM_RQ = 0x703, 164 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705, 165 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706, 166 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707, 167 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708, 168 MLX5_CMD_OP_CREATE_DCT = 0x710, 169 MLX5_CMD_OP_DESTROY_DCT = 0x711, 170 MLX5_CMD_OP_DRAIN_DCT = 0x712, 171 MLX5_CMD_OP_QUERY_DCT = 0x713, 172 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714, 173 MLX5_CMD_OP_CREATE_XRQ = 0x717, 174 MLX5_CMD_OP_DESTROY_XRQ = 0x718, 175 MLX5_CMD_OP_QUERY_XRQ = 0x719, 176 MLX5_CMD_OP_ARM_XRQ = 0x71a, 177 MLX5_CMD_OP_QUERY_XRQ_DC_PARAMS_ENTRY = 0x725, 178 MLX5_CMD_OP_SET_XRQ_DC_PARAMS_ENTRY = 0x726, 179 MLX5_CMD_OP_QUERY_XRQ_ERROR_PARAMS = 0x727, 180 MLX5_CMD_OP_RELEASE_XRQ_ERROR = 0x729, 181 MLX5_CMD_OP_MODIFY_XRQ = 0x72a, 182 MLX5_CMD_OP_QUERY_ESW_FUNCTIONS = 0x740, 183 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750, 184 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751, 185 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752, 186 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753, 187 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754, 188 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755, 189 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760, 190 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761, 191 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762, 192 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763, 193 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764, 194 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765, 195 MLX5_CMD_OP_QUERY_VNIC_ENV = 0x76f, 196 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770, 197 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771, 198 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772, 199 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773, 200 MLX5_CMD_OP_SET_MONITOR_COUNTER = 0x774, 201 MLX5_CMD_OP_ARM_MONITOR_COUNTER = 0x775, 202 MLX5_CMD_OP_SET_PP_RATE_LIMIT = 0x780, 203 MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781, 204 MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT = 0x782, 205 MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT = 0x783, 206 MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT = 0x784, 207 MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT = 0x785, 208 MLX5_CMD_OP_CREATE_QOS_PARA_VPORT = 0x786, 209 MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT = 0x787, 210 MLX5_CMD_OP_ALLOC_PD = 0x800, 211 MLX5_CMD_OP_DEALLOC_PD = 0x801, 212 MLX5_CMD_OP_ALLOC_UAR = 0x802, 213 MLX5_CMD_OP_DEALLOC_UAR = 0x803, 214 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804, 215 MLX5_CMD_OP_ACCESS_REG = 0x805, 216 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806, 217 MLX5_CMD_OP_DETACH_FROM_MCG = 0x807, 218 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a, 219 MLX5_CMD_OP_MAD_IFC = 0x50d, 220 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b, 221 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c, 222 MLX5_CMD_OP_NOP = 0x80d, 223 MLX5_CMD_OP_ALLOC_XRCD = 0x80e, 224 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f, 225 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816, 226 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817, 227 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822, 228 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823, 229 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824, 230 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825, 231 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826, 232 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827, 233 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828, 234 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829, 235 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a, 236 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b, 237 MLX5_CMD_OP_SET_WOL_ROL = 0x830, 238 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831, 239 MLX5_CMD_OP_CREATE_LAG = 0x840, 240 MLX5_CMD_OP_MODIFY_LAG = 0x841, 241 MLX5_CMD_OP_QUERY_LAG = 0x842, 242 MLX5_CMD_OP_DESTROY_LAG = 0x843, 243 MLX5_CMD_OP_CREATE_VPORT_LAG = 0x844, 244 MLX5_CMD_OP_DESTROY_VPORT_LAG = 0x845, 245 MLX5_CMD_OP_CREATE_TIR = 0x900, 246 MLX5_CMD_OP_MODIFY_TIR = 0x901, 247 MLX5_CMD_OP_DESTROY_TIR = 0x902, 248 MLX5_CMD_OP_QUERY_TIR = 0x903, 249 MLX5_CMD_OP_CREATE_SQ = 0x904, 250 MLX5_CMD_OP_MODIFY_SQ = 0x905, 251 MLX5_CMD_OP_DESTROY_SQ = 0x906, 252 MLX5_CMD_OP_QUERY_SQ = 0x907, 253 MLX5_CMD_OP_CREATE_RQ = 0x908, 254 MLX5_CMD_OP_MODIFY_RQ = 0x909, 255 MLX5_CMD_OP_SET_DELAY_DROP_PARAMS = 0x910, 256 MLX5_CMD_OP_DESTROY_RQ = 0x90a, 257 MLX5_CMD_OP_QUERY_RQ = 0x90b, 258 MLX5_CMD_OP_CREATE_RMP = 0x90c, 259 MLX5_CMD_OP_MODIFY_RMP = 0x90d, 260 MLX5_CMD_OP_DESTROY_RMP = 0x90e, 261 MLX5_CMD_OP_QUERY_RMP = 0x90f, 262 MLX5_CMD_OP_CREATE_TIS = 0x912, 263 MLX5_CMD_OP_MODIFY_TIS = 0x913, 264 MLX5_CMD_OP_DESTROY_TIS = 0x914, 265 MLX5_CMD_OP_QUERY_TIS = 0x915, 266 MLX5_CMD_OP_CREATE_RQT = 0x916, 267 MLX5_CMD_OP_MODIFY_RQT = 0x917, 268 MLX5_CMD_OP_DESTROY_RQT = 0x918, 269 MLX5_CMD_OP_QUERY_RQT = 0x919, 270 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f, 271 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930, 272 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931, 273 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932, 274 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933, 275 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934, 276 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935, 277 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936, 278 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937, 279 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938, 280 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939, 281 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a, 282 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b, 283 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c, 284 MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT = 0x93d, 285 MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT = 0x93e, 286 MLX5_CMD_OP_QUERY_PACKET_REFORMAT_CONTEXT = 0x93f, 287 MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT = 0x940, 288 MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941, 289 MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT = 0x942, 290 MLX5_CMD_OP_FPGA_CREATE_QP = 0x960, 291 MLX5_CMD_OP_FPGA_MODIFY_QP = 0x961, 292 MLX5_CMD_OP_FPGA_QUERY_QP = 0x962, 293 MLX5_CMD_OP_FPGA_DESTROY_QP = 0x963, 294 MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS = 0x964, 295 MLX5_CMD_OP_CREATE_GENERAL_OBJECT = 0xa00, 296 MLX5_CMD_OP_MODIFY_GENERAL_OBJECT = 0xa01, 297 MLX5_CMD_OP_QUERY_GENERAL_OBJECT = 0xa02, 298 MLX5_CMD_OP_DESTROY_GENERAL_OBJECT = 0xa03, 299 MLX5_CMD_OP_CREATE_UCTX = 0xa04, 300 MLX5_CMD_OP_DESTROY_UCTX = 0xa06, 301 MLX5_CMD_OP_CREATE_UMEM = 0xa08, 302 MLX5_CMD_OP_DESTROY_UMEM = 0xa0a, 303 MLX5_CMD_OP_SYNC_STEERING = 0xb00, 304 MLX5_CMD_OP_QUERY_VHCA_STATE = 0xb0d, 305 MLX5_CMD_OP_MODIFY_VHCA_STATE = 0xb0e, 306 MLX5_CMD_OP_MAX 307 }; 308 309 /* Valid range for general commands that don't work over an object */ 310 enum { 311 MLX5_CMD_OP_GENERAL_START = 0xb00, 312 MLX5_CMD_OP_GENERAL_END = 0xd00, 313 }; 314 315 struct mlx5_ifc_flow_table_fields_supported_bits { 316 u8 outer_dmac[0x1]; 317 u8 outer_smac[0x1]; 318 u8 outer_ether_type[0x1]; 319 u8 outer_ip_version[0x1]; 320 u8 outer_first_prio[0x1]; 321 u8 outer_first_cfi[0x1]; 322 u8 outer_first_vid[0x1]; 323 u8 outer_ipv4_ttl[0x1]; 324 u8 outer_second_prio[0x1]; 325 u8 outer_second_cfi[0x1]; 326 u8 outer_second_vid[0x1]; 327 u8 reserved_at_b[0x1]; 328 u8 outer_sip[0x1]; 329 u8 outer_dip[0x1]; 330 u8 outer_frag[0x1]; 331 u8 outer_ip_protocol[0x1]; 332 u8 outer_ip_ecn[0x1]; 333 u8 outer_ip_dscp[0x1]; 334 u8 outer_udp_sport[0x1]; 335 u8 outer_udp_dport[0x1]; 336 u8 outer_tcp_sport[0x1]; 337 u8 outer_tcp_dport[0x1]; 338 u8 outer_tcp_flags[0x1]; 339 u8 outer_gre_protocol[0x1]; 340 u8 outer_gre_key[0x1]; 341 u8 outer_vxlan_vni[0x1]; 342 u8 outer_geneve_vni[0x1]; 343 u8 outer_geneve_oam[0x1]; 344 u8 outer_geneve_protocol_type[0x1]; 345 u8 outer_geneve_opt_len[0x1]; 346 u8 reserved_at_1e[0x1]; 347 u8 source_eswitch_port[0x1]; 348 349 u8 inner_dmac[0x1]; 350 u8 inner_smac[0x1]; 351 u8 inner_ether_type[0x1]; 352 u8 inner_ip_version[0x1]; 353 u8 inner_first_prio[0x1]; 354 u8 inner_first_cfi[0x1]; 355 u8 inner_first_vid[0x1]; 356 u8 reserved_at_27[0x1]; 357 u8 inner_second_prio[0x1]; 358 u8 inner_second_cfi[0x1]; 359 u8 inner_second_vid[0x1]; 360 u8 reserved_at_2b[0x1]; 361 u8 inner_sip[0x1]; 362 u8 inner_dip[0x1]; 363 u8 inner_frag[0x1]; 364 u8 inner_ip_protocol[0x1]; 365 u8 inner_ip_ecn[0x1]; 366 u8 inner_ip_dscp[0x1]; 367 u8 inner_udp_sport[0x1]; 368 u8 inner_udp_dport[0x1]; 369 u8 inner_tcp_sport[0x1]; 370 u8 inner_tcp_dport[0x1]; 371 u8 inner_tcp_flags[0x1]; 372 u8 reserved_at_37[0x9]; 373 374 u8 geneve_tlv_option_0_data[0x1]; 375 u8 reserved_at_41[0x4]; 376 u8 outer_first_mpls_over_udp[0x4]; 377 u8 outer_first_mpls_over_gre[0x4]; 378 u8 inner_first_mpls[0x4]; 379 u8 outer_first_mpls[0x4]; 380 u8 reserved_at_55[0x2]; 381 u8 outer_esp_spi[0x1]; 382 u8 reserved_at_58[0x2]; 383 u8 bth_dst_qp[0x1]; 384 u8 reserved_at_5b[0x5]; 385 386 u8 reserved_at_60[0x18]; 387 u8 metadata_reg_c_7[0x1]; 388 u8 metadata_reg_c_6[0x1]; 389 u8 metadata_reg_c_5[0x1]; 390 u8 metadata_reg_c_4[0x1]; 391 u8 metadata_reg_c_3[0x1]; 392 u8 metadata_reg_c_2[0x1]; 393 u8 metadata_reg_c_1[0x1]; 394 u8 metadata_reg_c_0[0x1]; 395 }; 396 397 struct mlx5_ifc_flow_table_prop_layout_bits { 398 u8 ft_support[0x1]; 399 u8 reserved_at_1[0x1]; 400 u8 flow_counter[0x1]; 401 u8 flow_modify_en[0x1]; 402 u8 modify_root[0x1]; 403 u8 identified_miss_table_mode[0x1]; 404 u8 flow_table_modify[0x1]; 405 u8 reformat[0x1]; 406 u8 decap[0x1]; 407 u8 reserved_at_9[0x1]; 408 u8 pop_vlan[0x1]; 409 u8 push_vlan[0x1]; 410 u8 reserved_at_c[0x1]; 411 u8 pop_vlan_2[0x1]; 412 u8 push_vlan_2[0x1]; 413 u8 reformat_and_vlan_action[0x1]; 414 u8 reserved_at_10[0x1]; 415 u8 sw_owner[0x1]; 416 u8 reformat_l3_tunnel_to_l2[0x1]; 417 u8 reformat_l2_to_l3_tunnel[0x1]; 418 u8 reformat_and_modify_action[0x1]; 419 u8 ignore_flow_level[0x1]; 420 u8 reserved_at_16[0x1]; 421 u8 table_miss_action_domain[0x1]; 422 u8 termination_table[0x1]; 423 u8 reformat_and_fwd_to_table[0x1]; 424 u8 reserved_at_1a[0x2]; 425 u8 ipsec_encrypt[0x1]; 426 u8 ipsec_decrypt[0x1]; 427 u8 sw_owner_v2[0x1]; 428 u8 reserved_at_1f[0x1]; 429 430 u8 termination_table_raw_traffic[0x1]; 431 u8 reserved_at_21[0x1]; 432 u8 log_max_ft_size[0x6]; 433 u8 log_max_modify_header_context[0x8]; 434 u8 max_modify_header_actions[0x8]; 435 u8 max_ft_level[0x8]; 436 437 u8 reserved_at_40[0x20]; 438 439 u8 reserved_at_60[0x2]; 440 u8 reformat_insert[0x1]; 441 u8 reformat_remove[0x1]; 442 u8 reserver_at_64[0x14]; 443 u8 log_max_ft_num[0x8]; 444 445 u8 reserved_at_80[0x10]; 446 u8 log_max_flow_counter[0x8]; 447 u8 log_max_destination[0x8]; 448 449 u8 reserved_at_a0[0x18]; 450 u8 log_max_flow[0x8]; 451 452 u8 reserved_at_c0[0x40]; 453 454 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support; 455 456 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support; 457 }; 458 459 struct mlx5_ifc_odp_per_transport_service_cap_bits { 460 u8 send[0x1]; 461 u8 receive[0x1]; 462 u8 write[0x1]; 463 u8 read[0x1]; 464 u8 atomic[0x1]; 465 u8 srq_receive[0x1]; 466 u8 reserved_at_6[0x1a]; 467 }; 468 469 struct mlx5_ifc_fte_match_set_lyr_2_4_bits { 470 u8 smac_47_16[0x20]; 471 472 u8 smac_15_0[0x10]; 473 u8 ethertype[0x10]; 474 475 u8 dmac_47_16[0x20]; 476 477 u8 dmac_15_0[0x10]; 478 u8 first_prio[0x3]; 479 u8 first_cfi[0x1]; 480 u8 first_vid[0xc]; 481 482 u8 ip_protocol[0x8]; 483 u8 ip_dscp[0x6]; 484 u8 ip_ecn[0x2]; 485 u8 cvlan_tag[0x1]; 486 u8 svlan_tag[0x1]; 487 u8 frag[0x1]; 488 u8 ip_version[0x4]; 489 u8 tcp_flags[0x9]; 490 491 u8 tcp_sport[0x10]; 492 u8 tcp_dport[0x10]; 493 494 u8 reserved_at_c0[0x18]; 495 u8 ttl_hoplimit[0x8]; 496 497 u8 udp_sport[0x10]; 498 u8 udp_dport[0x10]; 499 500 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6; 501 502 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6; 503 }; 504 505 struct mlx5_ifc_nvgre_key_bits { 506 u8 hi[0x18]; 507 u8 lo[0x8]; 508 }; 509 510 union mlx5_ifc_gre_key_bits { 511 struct mlx5_ifc_nvgre_key_bits nvgre; 512 u8 key[0x20]; 513 }; 514 515 struct mlx5_ifc_fte_match_set_misc_bits { 516 u8 gre_c_present[0x1]; 517 u8 reserved_at_1[0x1]; 518 u8 gre_k_present[0x1]; 519 u8 gre_s_present[0x1]; 520 u8 source_vhca_port[0x4]; 521 u8 source_sqn[0x18]; 522 523 u8 source_eswitch_owner_vhca_id[0x10]; 524 u8 source_port[0x10]; 525 526 u8 outer_second_prio[0x3]; 527 u8 outer_second_cfi[0x1]; 528 u8 outer_second_vid[0xc]; 529 u8 inner_second_prio[0x3]; 530 u8 inner_second_cfi[0x1]; 531 u8 inner_second_vid[0xc]; 532 533 u8 outer_second_cvlan_tag[0x1]; 534 u8 inner_second_cvlan_tag[0x1]; 535 u8 outer_second_svlan_tag[0x1]; 536 u8 inner_second_svlan_tag[0x1]; 537 u8 reserved_at_64[0xc]; 538 u8 gre_protocol[0x10]; 539 540 union mlx5_ifc_gre_key_bits gre_key; 541 542 u8 vxlan_vni[0x18]; 543 u8 reserved_at_b8[0x8]; 544 545 u8 geneve_vni[0x18]; 546 u8 reserved_at_d8[0x7]; 547 u8 geneve_oam[0x1]; 548 549 u8 reserved_at_e0[0xc]; 550 u8 outer_ipv6_flow_label[0x14]; 551 552 u8 reserved_at_100[0xc]; 553 u8 inner_ipv6_flow_label[0x14]; 554 555 u8 reserved_at_120[0xa]; 556 u8 geneve_opt_len[0x6]; 557 u8 geneve_protocol_type[0x10]; 558 559 u8 reserved_at_140[0x8]; 560 u8 bth_dst_qp[0x18]; 561 u8 reserved_at_160[0x20]; 562 u8 outer_esp_spi[0x20]; 563 u8 reserved_at_1a0[0x60]; 564 }; 565 566 struct mlx5_ifc_fte_match_mpls_bits { 567 u8 mpls_label[0x14]; 568 u8 mpls_exp[0x3]; 569 u8 mpls_s_bos[0x1]; 570 u8 mpls_ttl[0x8]; 571 }; 572 573 struct mlx5_ifc_fte_match_set_misc2_bits { 574 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls; 575 576 struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls; 577 578 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre; 579 580 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp; 581 582 u8 metadata_reg_c_7[0x20]; 583 584 u8 metadata_reg_c_6[0x20]; 585 586 u8 metadata_reg_c_5[0x20]; 587 588 u8 metadata_reg_c_4[0x20]; 589 590 u8 metadata_reg_c_3[0x20]; 591 592 u8 metadata_reg_c_2[0x20]; 593 594 u8 metadata_reg_c_1[0x20]; 595 596 u8 metadata_reg_c_0[0x20]; 597 598 u8 metadata_reg_a[0x20]; 599 600 u8 reserved_at_1a0[0x60]; 601 }; 602 603 struct mlx5_ifc_fte_match_set_misc3_bits { 604 u8 inner_tcp_seq_num[0x20]; 605 606 u8 outer_tcp_seq_num[0x20]; 607 608 u8 inner_tcp_ack_num[0x20]; 609 610 u8 outer_tcp_ack_num[0x20]; 611 612 u8 reserved_at_80[0x8]; 613 u8 outer_vxlan_gpe_vni[0x18]; 614 615 u8 outer_vxlan_gpe_next_protocol[0x8]; 616 u8 outer_vxlan_gpe_flags[0x8]; 617 u8 reserved_at_b0[0x10]; 618 619 u8 icmp_header_data[0x20]; 620 621 u8 icmpv6_header_data[0x20]; 622 623 u8 icmp_type[0x8]; 624 u8 icmp_code[0x8]; 625 u8 icmpv6_type[0x8]; 626 u8 icmpv6_code[0x8]; 627 628 u8 geneve_tlv_option_0_data[0x20]; 629 630 u8 gtpu_teid[0x20]; 631 632 u8 gtpu_msg_type[0x8]; 633 u8 gtpu_msg_flags[0x8]; 634 u8 reserved_at_170[0x10]; 635 636 u8 gtpu_dw_2[0x20]; 637 638 u8 gtpu_first_ext_dw_0[0x20]; 639 640 u8 gtpu_dw_0[0x20]; 641 642 u8 reserved_at_1e0[0x20]; 643 }; 644 645 struct mlx5_ifc_fte_match_set_misc4_bits { 646 u8 prog_sample_field_value_0[0x20]; 647 648 u8 prog_sample_field_id_0[0x20]; 649 650 u8 prog_sample_field_value_1[0x20]; 651 652 u8 prog_sample_field_id_1[0x20]; 653 654 u8 prog_sample_field_value_2[0x20]; 655 656 u8 prog_sample_field_id_2[0x20]; 657 658 u8 prog_sample_field_value_3[0x20]; 659 660 u8 prog_sample_field_id_3[0x20]; 661 662 u8 reserved_at_100[0x100]; 663 }; 664 665 struct mlx5_ifc_cmd_pas_bits { 666 u8 pa_h[0x20]; 667 668 u8 pa_l[0x14]; 669 u8 reserved_at_34[0xc]; 670 }; 671 672 struct mlx5_ifc_uint64_bits { 673 u8 hi[0x20]; 674 675 u8 lo[0x20]; 676 }; 677 678 enum { 679 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0, 680 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7, 681 MLX5_ADS_STAT_RATE_10GBPS = 0x8, 682 MLX5_ADS_STAT_RATE_30GBPS = 0x9, 683 MLX5_ADS_STAT_RATE_5GBPS = 0xa, 684 MLX5_ADS_STAT_RATE_20GBPS = 0xb, 685 MLX5_ADS_STAT_RATE_40GBPS = 0xc, 686 MLX5_ADS_STAT_RATE_60GBPS = 0xd, 687 MLX5_ADS_STAT_RATE_80GBPS = 0xe, 688 MLX5_ADS_STAT_RATE_120GBPS = 0xf, 689 }; 690 691 struct mlx5_ifc_ads_bits { 692 u8 fl[0x1]; 693 u8 free_ar[0x1]; 694 u8 reserved_at_2[0xe]; 695 u8 pkey_index[0x10]; 696 697 u8 reserved_at_20[0x8]; 698 u8 grh[0x1]; 699 u8 mlid[0x7]; 700 u8 rlid[0x10]; 701 702 u8 ack_timeout[0x5]; 703 u8 reserved_at_45[0x3]; 704 u8 src_addr_index[0x8]; 705 u8 reserved_at_50[0x4]; 706 u8 stat_rate[0x4]; 707 u8 hop_limit[0x8]; 708 709 u8 reserved_at_60[0x4]; 710 u8 tclass[0x8]; 711 u8 flow_label[0x14]; 712 713 u8 rgid_rip[16][0x8]; 714 715 u8 reserved_at_100[0x4]; 716 u8 f_dscp[0x1]; 717 u8 f_ecn[0x1]; 718 u8 reserved_at_106[0x1]; 719 u8 f_eth_prio[0x1]; 720 u8 ecn[0x2]; 721 u8 dscp[0x6]; 722 u8 udp_sport[0x10]; 723 724 u8 dei_cfi[0x1]; 725 u8 eth_prio[0x3]; 726 u8 sl[0x4]; 727 u8 vhca_port_num[0x8]; 728 u8 rmac_47_32[0x10]; 729 730 u8 rmac_31_0[0x20]; 731 }; 732 733 struct mlx5_ifc_flow_table_nic_cap_bits { 734 u8 nic_rx_multi_path_tirs[0x1]; 735 u8 nic_rx_multi_path_tirs_fts[0x1]; 736 u8 allow_sniffer_and_nic_rx_shared_tir[0x1]; 737 u8 reserved_at_3[0x4]; 738 u8 sw_owner_reformat_supported[0x1]; 739 u8 reserved_at_8[0x18]; 740 741 u8 encap_general_header[0x1]; 742 u8 reserved_at_21[0xa]; 743 u8 log_max_packet_reformat_context[0x5]; 744 u8 reserved_at_30[0x6]; 745 u8 max_encap_header_size[0xa]; 746 u8 reserved_at_40[0x1c0]; 747 748 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive; 749 750 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_rdma; 751 752 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer; 753 754 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit; 755 756 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_rdma; 757 758 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer; 759 760 u8 reserved_at_e00[0x1200]; 761 762 u8 sw_steering_nic_rx_action_drop_icm_address[0x40]; 763 764 u8 sw_steering_nic_tx_action_drop_icm_address[0x40]; 765 766 u8 sw_steering_nic_tx_action_allow_icm_address[0x40]; 767 768 u8 reserved_at_20c0[0x5f40]; 769 }; 770 771 struct mlx5_ifc_port_selection_cap_bits { 772 u8 reserved_at_0[0x10]; 773 u8 port_select_flow_table[0x1]; 774 u8 reserved_at_11[0xf]; 775 776 u8 reserved_at_20[0x1e0]; 777 778 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_port_selection; 779 780 u8 reserved_at_400[0x7c00]; 781 }; 782 783 enum { 784 MLX5_FDB_TO_VPORT_REG_C_0 = 0x01, 785 MLX5_FDB_TO_VPORT_REG_C_1 = 0x02, 786 MLX5_FDB_TO_VPORT_REG_C_2 = 0x04, 787 MLX5_FDB_TO_VPORT_REG_C_3 = 0x08, 788 MLX5_FDB_TO_VPORT_REG_C_4 = 0x10, 789 MLX5_FDB_TO_VPORT_REG_C_5 = 0x20, 790 MLX5_FDB_TO_VPORT_REG_C_6 = 0x40, 791 MLX5_FDB_TO_VPORT_REG_C_7 = 0x80, 792 }; 793 794 struct mlx5_ifc_flow_table_eswitch_cap_bits { 795 u8 fdb_to_vport_reg_c_id[0x8]; 796 u8 reserved_at_8[0xd]; 797 u8 fdb_modify_header_fwd_to_table[0x1]; 798 u8 reserved_at_16[0x1]; 799 u8 flow_source[0x1]; 800 u8 reserved_at_18[0x2]; 801 u8 multi_fdb_encap[0x1]; 802 u8 egress_acl_forward_to_vport[0x1]; 803 u8 fdb_multi_path_to_table[0x1]; 804 u8 reserved_at_1d[0x3]; 805 806 u8 reserved_at_20[0x1e0]; 807 808 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb; 809 810 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress; 811 812 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress; 813 814 u8 reserved_at_800[0x1000]; 815 816 u8 sw_steering_fdb_action_drop_icm_address_rx[0x40]; 817 818 u8 sw_steering_fdb_action_drop_icm_address_tx[0x40]; 819 820 u8 sw_steering_uplink_icm_address_rx[0x40]; 821 822 u8 sw_steering_uplink_icm_address_tx[0x40]; 823 824 u8 reserved_at_1900[0x6700]; 825 }; 826 827 enum { 828 MLX5_COUNTER_SOURCE_ESWITCH = 0x0, 829 MLX5_COUNTER_FLOW_ESWITCH = 0x1, 830 }; 831 832 struct mlx5_ifc_e_switch_cap_bits { 833 u8 vport_svlan_strip[0x1]; 834 u8 vport_cvlan_strip[0x1]; 835 u8 vport_svlan_insert[0x1]; 836 u8 vport_cvlan_insert_if_not_exist[0x1]; 837 u8 vport_cvlan_insert_overwrite[0x1]; 838 u8 reserved_at_5[0x2]; 839 u8 esw_shared_ingress_acl[0x1]; 840 u8 esw_uplink_ingress_acl[0x1]; 841 u8 root_ft_on_other_esw[0x1]; 842 u8 reserved_at_a[0xf]; 843 u8 esw_functions_changed[0x1]; 844 u8 reserved_at_1a[0x1]; 845 u8 ecpf_vport_exists[0x1]; 846 u8 counter_eswitch_affinity[0x1]; 847 u8 merged_eswitch[0x1]; 848 u8 nic_vport_node_guid_modify[0x1]; 849 u8 nic_vport_port_guid_modify[0x1]; 850 851 u8 vxlan_encap_decap[0x1]; 852 u8 nvgre_encap_decap[0x1]; 853 u8 reserved_at_22[0x1]; 854 u8 log_max_fdb_encap_uplink[0x5]; 855 u8 reserved_at_21[0x3]; 856 u8 log_max_packet_reformat_context[0x5]; 857 u8 reserved_2b[0x6]; 858 u8 max_encap_header_size[0xa]; 859 860 u8 reserved_at_40[0xb]; 861 u8 log_max_esw_sf[0x5]; 862 u8 esw_sf_base_id[0x10]; 863 864 u8 reserved_at_60[0x7a0]; 865 866 }; 867 868 struct mlx5_ifc_qos_cap_bits { 869 u8 packet_pacing[0x1]; 870 u8 esw_scheduling[0x1]; 871 u8 esw_bw_share[0x1]; 872 u8 esw_rate_limit[0x1]; 873 u8 reserved_at_4[0x1]; 874 u8 packet_pacing_burst_bound[0x1]; 875 u8 packet_pacing_typical_size[0x1]; 876 u8 reserved_at_7[0x1]; 877 u8 nic_sq_scheduling[0x1]; 878 u8 nic_bw_share[0x1]; 879 u8 nic_rate_limit[0x1]; 880 u8 packet_pacing_uid[0x1]; 881 u8 log_esw_max_sched_depth[0x4]; 882 u8 reserved_at_10[0x10]; 883 884 u8 reserved_at_20[0xb]; 885 u8 log_max_qos_nic_queue_group[0x5]; 886 u8 reserved_at_30[0x10]; 887 888 u8 packet_pacing_max_rate[0x20]; 889 890 u8 packet_pacing_min_rate[0x20]; 891 892 u8 reserved_at_80[0x10]; 893 u8 packet_pacing_rate_table_size[0x10]; 894 895 u8 esw_element_type[0x10]; 896 u8 esw_tsar_type[0x10]; 897 898 u8 reserved_at_c0[0x10]; 899 u8 max_qos_para_vport[0x10]; 900 901 u8 max_tsar_bw_share[0x20]; 902 903 u8 reserved_at_100[0x700]; 904 }; 905 906 struct mlx5_ifc_debug_cap_bits { 907 u8 core_dump_general[0x1]; 908 u8 core_dump_qp[0x1]; 909 u8 reserved_at_2[0x7]; 910 u8 resource_dump[0x1]; 911 u8 reserved_at_a[0x16]; 912 913 u8 reserved_at_20[0x2]; 914 u8 stall_detect[0x1]; 915 u8 reserved_at_23[0x1d]; 916 917 u8 reserved_at_40[0x7c0]; 918 }; 919 920 struct mlx5_ifc_per_protocol_networking_offload_caps_bits { 921 u8 csum_cap[0x1]; 922 u8 vlan_cap[0x1]; 923 u8 lro_cap[0x1]; 924 u8 lro_psh_flag[0x1]; 925 u8 lro_time_stamp[0x1]; 926 u8 reserved_at_5[0x2]; 927 u8 wqe_vlan_insert[0x1]; 928 u8 self_lb_en_modifiable[0x1]; 929 u8 reserved_at_9[0x2]; 930 u8 max_lso_cap[0x5]; 931 u8 multi_pkt_send_wqe[0x2]; 932 u8 wqe_inline_mode[0x2]; 933 u8 rss_ind_tbl_cap[0x4]; 934 u8 reg_umr_sq[0x1]; 935 u8 scatter_fcs[0x1]; 936 u8 enhanced_multi_pkt_send_wqe[0x1]; 937 u8 tunnel_lso_const_out_ip_id[0x1]; 938 u8 tunnel_lro_gre[0x1]; 939 u8 tunnel_lro_vxlan[0x1]; 940 u8 tunnel_stateless_gre[0x1]; 941 u8 tunnel_stateless_vxlan[0x1]; 942 943 u8 swp[0x1]; 944 u8 swp_csum[0x1]; 945 u8 swp_lso[0x1]; 946 u8 cqe_checksum_full[0x1]; 947 u8 tunnel_stateless_geneve_tx[0x1]; 948 u8 tunnel_stateless_mpls_over_udp[0x1]; 949 u8 tunnel_stateless_mpls_over_gre[0x1]; 950 u8 tunnel_stateless_vxlan_gpe[0x1]; 951 u8 tunnel_stateless_ipv4_over_vxlan[0x1]; 952 u8 tunnel_stateless_ip_over_ip[0x1]; 953 u8 insert_trailer[0x1]; 954 u8 reserved_at_2b[0x1]; 955 u8 tunnel_stateless_ip_over_ip_rx[0x1]; 956 u8 tunnel_stateless_ip_over_ip_tx[0x1]; 957 u8 reserved_at_2e[0x2]; 958 u8 max_vxlan_udp_ports[0x8]; 959 u8 reserved_at_38[0x6]; 960 u8 max_geneve_opt_len[0x1]; 961 u8 tunnel_stateless_geneve_rx[0x1]; 962 963 u8 reserved_at_40[0x10]; 964 u8 lro_min_mss_size[0x10]; 965 966 u8 reserved_at_60[0x120]; 967 968 u8 lro_timer_supported_periods[4][0x20]; 969 970 u8 reserved_at_200[0x600]; 971 }; 972 973 enum { 974 MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING = 0x0, 975 MLX5_TIMESTAMP_FORMAT_CAP_REAL_TIME = 0x1, 976 MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING_AND_REAL_TIME = 0x2, 977 }; 978 979 struct mlx5_ifc_roce_cap_bits { 980 u8 roce_apm[0x1]; 981 u8 reserved_at_1[0x3]; 982 u8 sw_r_roce_src_udp_port[0x1]; 983 u8 fl_rc_qp_when_roce_disabled[0x1]; 984 u8 fl_rc_qp_when_roce_enabled[0x1]; 985 u8 reserved_at_7[0x17]; 986 u8 qp_ts_format[0x2]; 987 988 u8 reserved_at_20[0x60]; 989 990 u8 reserved_at_80[0xc]; 991 u8 l3_type[0x4]; 992 u8 reserved_at_90[0x8]; 993 u8 roce_version[0x8]; 994 995 u8 reserved_at_a0[0x10]; 996 u8 r_roce_dest_udp_port[0x10]; 997 998 u8 r_roce_max_src_udp_port[0x10]; 999 u8 r_roce_min_src_udp_port[0x10]; 1000 1001 u8 reserved_at_e0[0x10]; 1002 u8 roce_address_table_size[0x10]; 1003 1004 u8 reserved_at_100[0x700]; 1005 }; 1006 1007 struct mlx5_ifc_sync_steering_in_bits { 1008 u8 opcode[0x10]; 1009 u8 uid[0x10]; 1010 1011 u8 reserved_at_20[0x10]; 1012 u8 op_mod[0x10]; 1013 1014 u8 reserved_at_40[0xc0]; 1015 }; 1016 1017 struct mlx5_ifc_sync_steering_out_bits { 1018 u8 status[0x8]; 1019 u8 reserved_at_8[0x18]; 1020 1021 u8 syndrome[0x20]; 1022 1023 u8 reserved_at_40[0x40]; 1024 }; 1025 1026 struct mlx5_ifc_device_mem_cap_bits { 1027 u8 memic[0x1]; 1028 u8 reserved_at_1[0x1f]; 1029 1030 u8 reserved_at_20[0xb]; 1031 u8 log_min_memic_alloc_size[0x5]; 1032 u8 reserved_at_30[0x8]; 1033 u8 log_max_memic_addr_alignment[0x8]; 1034 1035 u8 memic_bar_start_addr[0x40]; 1036 1037 u8 memic_bar_size[0x20]; 1038 1039 u8 max_memic_size[0x20]; 1040 1041 u8 steering_sw_icm_start_address[0x40]; 1042 1043 u8 reserved_at_100[0x8]; 1044 u8 log_header_modify_sw_icm_size[0x8]; 1045 u8 reserved_at_110[0x2]; 1046 u8 log_sw_icm_alloc_granularity[0x6]; 1047 u8 log_steering_sw_icm_size[0x8]; 1048 1049 u8 reserved_at_120[0x20]; 1050 1051 u8 header_modify_sw_icm_start_address[0x40]; 1052 1053 u8 reserved_at_180[0x80]; 1054 1055 u8 memic_operations[0x20]; 1056 1057 u8 reserved_at_220[0x5e0]; 1058 }; 1059 1060 struct mlx5_ifc_device_event_cap_bits { 1061 u8 user_affiliated_events[4][0x40]; 1062 1063 u8 user_unaffiliated_events[4][0x40]; 1064 }; 1065 1066 struct mlx5_ifc_virtio_emulation_cap_bits { 1067 u8 desc_tunnel_offload_type[0x1]; 1068 u8 eth_frame_offload_type[0x1]; 1069 u8 virtio_version_1_0[0x1]; 1070 u8 device_features_bits_mask[0xd]; 1071 u8 event_mode[0x8]; 1072 u8 virtio_queue_type[0x8]; 1073 1074 u8 max_tunnel_desc[0x10]; 1075 u8 reserved_at_30[0x3]; 1076 u8 log_doorbell_stride[0x5]; 1077 u8 reserved_at_38[0x3]; 1078 u8 log_doorbell_bar_size[0x5]; 1079 1080 u8 doorbell_bar_offset[0x40]; 1081 1082 u8 max_emulated_devices[0x8]; 1083 u8 max_num_virtio_queues[0x18]; 1084 1085 u8 reserved_at_a0[0x60]; 1086 1087 u8 umem_1_buffer_param_a[0x20]; 1088 1089 u8 umem_1_buffer_param_b[0x20]; 1090 1091 u8 umem_2_buffer_param_a[0x20]; 1092 1093 u8 umem_2_buffer_param_b[0x20]; 1094 1095 u8 umem_3_buffer_param_a[0x20]; 1096 1097 u8 umem_3_buffer_param_b[0x20]; 1098 1099 u8 reserved_at_1c0[0x640]; 1100 }; 1101 1102 enum { 1103 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0, 1104 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2, 1105 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4, 1106 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8, 1107 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10, 1108 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20, 1109 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40, 1110 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80, 1111 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100, 1112 }; 1113 1114 enum { 1115 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1, 1116 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2, 1117 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4, 1118 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8, 1119 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10, 1120 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20, 1121 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40, 1122 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80, 1123 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100, 1124 }; 1125 1126 struct mlx5_ifc_atomic_caps_bits { 1127 u8 reserved_at_0[0x40]; 1128 1129 u8 atomic_req_8B_endianness_mode[0x2]; 1130 u8 reserved_at_42[0x4]; 1131 u8 supported_atomic_req_8B_endianness_mode_1[0x1]; 1132 1133 u8 reserved_at_47[0x19]; 1134 1135 u8 reserved_at_60[0x20]; 1136 1137 u8 reserved_at_80[0x10]; 1138 u8 atomic_operations[0x10]; 1139 1140 u8 reserved_at_a0[0x10]; 1141 u8 atomic_size_qp[0x10]; 1142 1143 u8 reserved_at_c0[0x10]; 1144 u8 atomic_size_dc[0x10]; 1145 1146 u8 reserved_at_e0[0x720]; 1147 }; 1148 1149 struct mlx5_ifc_odp_cap_bits { 1150 u8 reserved_at_0[0x40]; 1151 1152 u8 sig[0x1]; 1153 u8 reserved_at_41[0x1f]; 1154 1155 u8 reserved_at_60[0x20]; 1156 1157 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps; 1158 1159 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps; 1160 1161 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps; 1162 1163 struct mlx5_ifc_odp_per_transport_service_cap_bits xrc_odp_caps; 1164 1165 struct mlx5_ifc_odp_per_transport_service_cap_bits dc_odp_caps; 1166 1167 u8 reserved_at_120[0x6E0]; 1168 }; 1169 1170 struct mlx5_ifc_calc_op { 1171 u8 reserved_at_0[0x10]; 1172 u8 reserved_at_10[0x9]; 1173 u8 op_swap_endianness[0x1]; 1174 u8 op_min[0x1]; 1175 u8 op_xor[0x1]; 1176 u8 op_or[0x1]; 1177 u8 op_and[0x1]; 1178 u8 op_max[0x1]; 1179 u8 op_add[0x1]; 1180 }; 1181 1182 struct mlx5_ifc_vector_calc_cap_bits { 1183 u8 calc_matrix[0x1]; 1184 u8 reserved_at_1[0x1f]; 1185 u8 reserved_at_20[0x8]; 1186 u8 max_vec_count[0x8]; 1187 u8 reserved_at_30[0xd]; 1188 u8 max_chunk_size[0x3]; 1189 struct mlx5_ifc_calc_op calc0; 1190 struct mlx5_ifc_calc_op calc1; 1191 struct mlx5_ifc_calc_op calc2; 1192 struct mlx5_ifc_calc_op calc3; 1193 1194 u8 reserved_at_c0[0x720]; 1195 }; 1196 1197 struct mlx5_ifc_tls_cap_bits { 1198 u8 tls_1_2_aes_gcm_128[0x1]; 1199 u8 tls_1_3_aes_gcm_128[0x1]; 1200 u8 tls_1_2_aes_gcm_256[0x1]; 1201 u8 tls_1_3_aes_gcm_256[0x1]; 1202 u8 reserved_at_4[0x1c]; 1203 1204 u8 reserved_at_20[0x7e0]; 1205 }; 1206 1207 struct mlx5_ifc_ipsec_cap_bits { 1208 u8 ipsec_full_offload[0x1]; 1209 u8 ipsec_crypto_offload[0x1]; 1210 u8 ipsec_esn[0x1]; 1211 u8 ipsec_crypto_esp_aes_gcm_256_encrypt[0x1]; 1212 u8 ipsec_crypto_esp_aes_gcm_128_encrypt[0x1]; 1213 u8 ipsec_crypto_esp_aes_gcm_256_decrypt[0x1]; 1214 u8 ipsec_crypto_esp_aes_gcm_128_decrypt[0x1]; 1215 u8 reserved_at_7[0x4]; 1216 u8 log_max_ipsec_offload[0x5]; 1217 u8 reserved_at_10[0x10]; 1218 1219 u8 min_log_ipsec_full_replay_window[0x8]; 1220 u8 max_log_ipsec_full_replay_window[0x8]; 1221 u8 reserved_at_30[0x7d0]; 1222 }; 1223 1224 enum { 1225 MLX5_WQ_TYPE_LINKED_LIST = 0x0, 1226 MLX5_WQ_TYPE_CYCLIC = 0x1, 1227 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2, 1228 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3, 1229 }; 1230 1231 enum { 1232 MLX5_WQ_END_PAD_MODE_NONE = 0x0, 1233 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1, 1234 }; 1235 1236 enum { 1237 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0, 1238 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1, 1239 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2, 1240 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3, 1241 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4, 1242 }; 1243 1244 enum { 1245 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0, 1246 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1, 1247 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2, 1248 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3, 1249 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4, 1250 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5, 1251 }; 1252 1253 enum { 1254 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0, 1255 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1, 1256 }; 1257 1258 enum { 1259 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0, 1260 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1, 1261 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3, 1262 }; 1263 1264 enum { 1265 MLX5_CAP_PORT_TYPE_IB = 0x0, 1266 MLX5_CAP_PORT_TYPE_ETH = 0x1, 1267 }; 1268 1269 enum { 1270 MLX5_CAP_UMR_FENCE_STRONG = 0x0, 1271 MLX5_CAP_UMR_FENCE_SMALL = 0x1, 1272 MLX5_CAP_UMR_FENCE_NONE = 0x2, 1273 }; 1274 1275 enum { 1276 MLX5_FLEX_PARSER_GENEVE_ENABLED = 1 << 3, 1277 MLX5_FLEX_PARSER_MPLS_OVER_GRE_ENABLED = 1 << 4, 1278 mlx5_FLEX_PARSER_MPLS_OVER_UDP_ENABLED = 1 << 5, 1279 MLX5_FLEX_PARSER_VXLAN_GPE_ENABLED = 1 << 7, 1280 MLX5_FLEX_PARSER_ICMP_V4_ENABLED = 1 << 8, 1281 MLX5_FLEX_PARSER_ICMP_V6_ENABLED = 1 << 9, 1282 MLX5_FLEX_PARSER_GENEVE_TLV_OPTION_0_ENABLED = 1 << 10, 1283 MLX5_FLEX_PARSER_GTPU_ENABLED = 1 << 11, 1284 MLX5_FLEX_PARSER_GTPU_DW_2_ENABLED = 1 << 16, 1285 MLX5_FLEX_PARSER_GTPU_FIRST_EXT_DW_0_ENABLED = 1 << 17, 1286 MLX5_FLEX_PARSER_GTPU_DW_0_ENABLED = 1 << 18, 1287 MLX5_FLEX_PARSER_GTPU_TEID_ENABLED = 1 << 19, 1288 }; 1289 1290 enum { 1291 MLX5_UCTX_CAP_RAW_TX = 1UL << 0, 1292 MLX5_UCTX_CAP_INTERNAL_DEV_RES = 1UL << 1, 1293 }; 1294 1295 #define MLX5_FC_BULK_SIZE_FACTOR 128 1296 1297 enum mlx5_fc_bulk_alloc_bitmask { 1298 MLX5_FC_BULK_128 = (1 << 0), 1299 MLX5_FC_BULK_256 = (1 << 1), 1300 MLX5_FC_BULK_512 = (1 << 2), 1301 MLX5_FC_BULK_1024 = (1 << 3), 1302 MLX5_FC_BULK_2048 = (1 << 4), 1303 MLX5_FC_BULK_4096 = (1 << 5), 1304 MLX5_FC_BULK_8192 = (1 << 6), 1305 MLX5_FC_BULK_16384 = (1 << 7), 1306 }; 1307 1308 #define MLX5_FC_BULK_NUM_FCS(fc_enum) (MLX5_FC_BULK_SIZE_FACTOR * (fc_enum)) 1309 1310 #define MLX5_FT_MAX_MULTIPATH_LEVEL 63 1311 1312 enum { 1313 MLX5_STEERING_FORMAT_CONNECTX_5 = 0, 1314 MLX5_STEERING_FORMAT_CONNECTX_6DX = 1, 1315 }; 1316 1317 struct mlx5_ifc_cmd_hca_cap_bits { 1318 u8 reserved_at_0[0x1f]; 1319 u8 vhca_resource_manager[0x1]; 1320 1321 u8 hca_cap_2[0x1]; 1322 u8 reserved_at_21[0x1]; 1323 u8 dtor[0x1]; 1324 u8 event_on_vhca_state_teardown_request[0x1]; 1325 u8 event_on_vhca_state_in_use[0x1]; 1326 u8 event_on_vhca_state_active[0x1]; 1327 u8 event_on_vhca_state_allocated[0x1]; 1328 u8 event_on_vhca_state_invalid[0x1]; 1329 u8 reserved_at_28[0x8]; 1330 u8 vhca_id[0x10]; 1331 1332 u8 reserved_at_40[0x40]; 1333 1334 u8 log_max_srq_sz[0x8]; 1335 u8 log_max_qp_sz[0x8]; 1336 u8 event_cap[0x1]; 1337 u8 reserved_at_91[0x2]; 1338 u8 isolate_vl_tc_new[0x1]; 1339 u8 reserved_at_94[0x4]; 1340 u8 prio_tag_required[0x1]; 1341 u8 reserved_at_99[0x2]; 1342 u8 log_max_qp[0x5]; 1343 1344 u8 reserved_at_a0[0x3]; 1345 u8 ece_support[0x1]; 1346 u8 reserved_at_a4[0x5]; 1347 u8 reg_c_preserve[0x1]; 1348 u8 reserved_at_aa[0x1]; 1349 u8 log_max_srq[0x5]; 1350 u8 reserved_at_b0[0x1]; 1351 u8 uplink_follow[0x1]; 1352 u8 ts_cqe_to_dest_cqn[0x1]; 1353 u8 reserved_at_b3[0xd]; 1354 1355 u8 max_sgl_for_optimized_performance[0x8]; 1356 u8 log_max_cq_sz[0x8]; 1357 u8 relaxed_ordering_write_umr[0x1]; 1358 u8 relaxed_ordering_read_umr[0x1]; 1359 u8 reserved_at_d2[0x7]; 1360 u8 virtio_net_device_emualtion_manager[0x1]; 1361 u8 virtio_blk_device_emualtion_manager[0x1]; 1362 u8 log_max_cq[0x5]; 1363 1364 u8 log_max_eq_sz[0x8]; 1365 u8 relaxed_ordering_write[0x1]; 1366 u8 relaxed_ordering_read[0x1]; 1367 u8 log_max_mkey[0x6]; 1368 u8 reserved_at_f0[0x8]; 1369 u8 dump_fill_mkey[0x1]; 1370 u8 reserved_at_f9[0x2]; 1371 u8 fast_teardown[0x1]; 1372 u8 log_max_eq[0x4]; 1373 1374 u8 max_indirection[0x8]; 1375 u8 fixed_buffer_size[0x1]; 1376 u8 log_max_mrw_sz[0x7]; 1377 u8 force_teardown[0x1]; 1378 u8 reserved_at_111[0x1]; 1379 u8 log_max_bsf_list_size[0x6]; 1380 u8 umr_extended_translation_offset[0x1]; 1381 u8 null_mkey[0x1]; 1382 u8 log_max_klm_list_size[0x6]; 1383 1384 u8 reserved_at_120[0xa]; 1385 u8 log_max_ra_req_dc[0x6]; 1386 u8 reserved_at_130[0xa]; 1387 u8 log_max_ra_res_dc[0x6]; 1388 1389 u8 reserved_at_140[0x6]; 1390 u8 release_all_pages[0x1]; 1391 u8 reserved_at_147[0x2]; 1392 u8 roce_accl[0x1]; 1393 u8 log_max_ra_req_qp[0x6]; 1394 u8 reserved_at_150[0xa]; 1395 u8 log_max_ra_res_qp[0x6]; 1396 1397 u8 end_pad[0x1]; 1398 u8 cc_query_allowed[0x1]; 1399 u8 cc_modify_allowed[0x1]; 1400 u8 start_pad[0x1]; 1401 u8 cache_line_128byte[0x1]; 1402 u8 reserved_at_165[0x4]; 1403 u8 rts2rts_qp_counters_set_id[0x1]; 1404 u8 reserved_at_16a[0x2]; 1405 u8 vnic_env_int_rq_oob[0x1]; 1406 u8 sbcam_reg[0x1]; 1407 u8 reserved_at_16e[0x1]; 1408 u8 qcam_reg[0x1]; 1409 u8 gid_table_size[0x10]; 1410 1411 u8 out_of_seq_cnt[0x1]; 1412 u8 vport_counters[0x1]; 1413 u8 retransmission_q_counters[0x1]; 1414 u8 debug[0x1]; 1415 u8 modify_rq_counter_set_id[0x1]; 1416 u8 rq_delay_drop[0x1]; 1417 u8 max_qp_cnt[0xa]; 1418 u8 pkey_table_size[0x10]; 1419 1420 u8 vport_group_manager[0x1]; 1421 u8 vhca_group_manager[0x1]; 1422 u8 ib_virt[0x1]; 1423 u8 eth_virt[0x1]; 1424 u8 vnic_env_queue_counters[0x1]; 1425 u8 ets[0x1]; 1426 u8 nic_flow_table[0x1]; 1427 u8 eswitch_manager[0x1]; 1428 u8 device_memory[0x1]; 1429 u8 mcam_reg[0x1]; 1430 u8 pcam_reg[0x1]; 1431 u8 local_ca_ack_delay[0x5]; 1432 u8 port_module_event[0x1]; 1433 u8 enhanced_error_q_counters[0x1]; 1434 u8 ports_check[0x1]; 1435 u8 reserved_at_1b3[0x1]; 1436 u8 disable_link_up[0x1]; 1437 u8 beacon_led[0x1]; 1438 u8 port_type[0x2]; 1439 u8 num_ports[0x8]; 1440 1441 u8 reserved_at_1c0[0x1]; 1442 u8 pps[0x1]; 1443 u8 pps_modify[0x1]; 1444 u8 log_max_msg[0x5]; 1445 u8 reserved_at_1c8[0x4]; 1446 u8 max_tc[0x4]; 1447 u8 temp_warn_event[0x1]; 1448 u8 dcbx[0x1]; 1449 u8 general_notification_event[0x1]; 1450 u8 reserved_at_1d3[0x2]; 1451 u8 fpga[0x1]; 1452 u8 rol_s[0x1]; 1453 u8 rol_g[0x1]; 1454 u8 reserved_at_1d8[0x1]; 1455 u8 wol_s[0x1]; 1456 u8 wol_g[0x1]; 1457 u8 wol_a[0x1]; 1458 u8 wol_b[0x1]; 1459 u8 wol_m[0x1]; 1460 u8 wol_u[0x1]; 1461 u8 wol_p[0x1]; 1462 1463 u8 stat_rate_support[0x10]; 1464 u8 reserved_at_1f0[0x1]; 1465 u8 pci_sync_for_fw_update_event[0x1]; 1466 u8 reserved_at_1f2[0x6]; 1467 u8 init2_lag_tx_port_affinity[0x1]; 1468 u8 reserved_at_1fa[0x3]; 1469 u8 cqe_version[0x4]; 1470 1471 u8 compact_address_vector[0x1]; 1472 u8 striding_rq[0x1]; 1473 u8 reserved_at_202[0x1]; 1474 u8 ipoib_enhanced_offloads[0x1]; 1475 u8 ipoib_basic_offloads[0x1]; 1476 u8 reserved_at_205[0x1]; 1477 u8 repeated_block_disabled[0x1]; 1478 u8 umr_modify_entity_size_disabled[0x1]; 1479 u8 umr_modify_atomic_disabled[0x1]; 1480 u8 umr_indirect_mkey_disabled[0x1]; 1481 u8 umr_fence[0x2]; 1482 u8 dc_req_scat_data_cqe[0x1]; 1483 u8 reserved_at_20d[0x2]; 1484 u8 drain_sigerr[0x1]; 1485 u8 cmdif_checksum[0x2]; 1486 u8 sigerr_cqe[0x1]; 1487 u8 reserved_at_213[0x1]; 1488 u8 wq_signature[0x1]; 1489 u8 sctr_data_cqe[0x1]; 1490 u8 reserved_at_216[0x1]; 1491 u8 sho[0x1]; 1492 u8 tph[0x1]; 1493 u8 rf[0x1]; 1494 u8 dct[0x1]; 1495 u8 qos[0x1]; 1496 u8 eth_net_offloads[0x1]; 1497 u8 roce[0x1]; 1498 u8 atomic[0x1]; 1499 u8 reserved_at_21f[0x1]; 1500 1501 u8 cq_oi[0x1]; 1502 u8 cq_resize[0x1]; 1503 u8 cq_moderation[0x1]; 1504 u8 reserved_at_223[0x3]; 1505 u8 cq_eq_remap[0x1]; 1506 u8 pg[0x1]; 1507 u8 block_lb_mc[0x1]; 1508 u8 reserved_at_229[0x1]; 1509 u8 scqe_break_moderation[0x1]; 1510 u8 cq_period_start_from_cqe[0x1]; 1511 u8 cd[0x1]; 1512 u8 reserved_at_22d[0x1]; 1513 u8 apm[0x1]; 1514 u8 vector_calc[0x1]; 1515 u8 umr_ptr_rlky[0x1]; 1516 u8 imaicl[0x1]; 1517 u8 qp_packet_based[0x1]; 1518 u8 reserved_at_233[0x3]; 1519 u8 qkv[0x1]; 1520 u8 pkv[0x1]; 1521 u8 set_deth_sqpn[0x1]; 1522 u8 reserved_at_239[0x3]; 1523 u8 xrc[0x1]; 1524 u8 ud[0x1]; 1525 u8 uc[0x1]; 1526 u8 rc[0x1]; 1527 1528 u8 uar_4k[0x1]; 1529 u8 reserved_at_241[0x9]; 1530 u8 uar_sz[0x6]; 1531 u8 port_selection_cap[0x1]; 1532 u8 reserved_at_248[0x1]; 1533 u8 umem_uid_0[0x1]; 1534 u8 reserved_at_250[0x5]; 1535 u8 log_pg_sz[0x8]; 1536 1537 u8 bf[0x1]; 1538 u8 driver_version[0x1]; 1539 u8 pad_tx_eth_packet[0x1]; 1540 u8 reserved_at_263[0x3]; 1541 u8 mkey_by_name[0x1]; 1542 u8 reserved_at_267[0x4]; 1543 1544 u8 log_bf_reg_size[0x5]; 1545 1546 u8 reserved_at_270[0x6]; 1547 u8 lag_dct[0x2]; 1548 u8 lag_tx_port_affinity[0x1]; 1549 u8 lag_native_fdb_selection[0x1]; 1550 u8 reserved_at_27a[0x1]; 1551 u8 lag_master[0x1]; 1552 u8 num_lag_ports[0x4]; 1553 1554 u8 reserved_at_280[0x10]; 1555 u8 max_wqe_sz_sq[0x10]; 1556 1557 u8 reserved_at_2a0[0x10]; 1558 u8 max_wqe_sz_rq[0x10]; 1559 1560 u8 max_flow_counter_31_16[0x10]; 1561 u8 max_wqe_sz_sq_dc[0x10]; 1562 1563 u8 reserved_at_2e0[0x7]; 1564 u8 max_qp_mcg[0x19]; 1565 1566 u8 reserved_at_300[0x10]; 1567 u8 flow_counter_bulk_alloc[0x8]; 1568 u8 log_max_mcg[0x8]; 1569 1570 u8 reserved_at_320[0x3]; 1571 u8 log_max_transport_domain[0x5]; 1572 u8 reserved_at_328[0x3]; 1573 u8 log_max_pd[0x5]; 1574 u8 reserved_at_330[0xb]; 1575 u8 log_max_xrcd[0x5]; 1576 1577 u8 nic_receive_steering_discard[0x1]; 1578 u8 receive_discard_vport_down[0x1]; 1579 u8 transmit_discard_vport_down[0x1]; 1580 u8 reserved_at_343[0x5]; 1581 u8 log_max_flow_counter_bulk[0x8]; 1582 u8 max_flow_counter_15_0[0x10]; 1583 1584 1585 u8 reserved_at_360[0x3]; 1586 u8 log_max_rq[0x5]; 1587 u8 reserved_at_368[0x3]; 1588 u8 log_max_sq[0x5]; 1589 u8 reserved_at_370[0x3]; 1590 u8 log_max_tir[0x5]; 1591 u8 reserved_at_378[0x3]; 1592 u8 log_max_tis[0x5]; 1593 1594 u8 basic_cyclic_rcv_wqe[0x1]; 1595 u8 reserved_at_381[0x2]; 1596 u8 log_max_rmp[0x5]; 1597 u8 reserved_at_388[0x3]; 1598 u8 log_max_rqt[0x5]; 1599 u8 reserved_at_390[0x3]; 1600 u8 log_max_rqt_size[0x5]; 1601 u8 reserved_at_398[0x3]; 1602 u8 log_max_tis_per_sq[0x5]; 1603 1604 u8 ext_stride_num_range[0x1]; 1605 u8 roce_rw_supported[0x1]; 1606 u8 reserved_at_3a2[0x1]; 1607 u8 log_max_stride_sz_rq[0x5]; 1608 u8 reserved_at_3a8[0x3]; 1609 u8 log_min_stride_sz_rq[0x5]; 1610 u8 reserved_at_3b0[0x3]; 1611 u8 log_max_stride_sz_sq[0x5]; 1612 u8 reserved_at_3b8[0x3]; 1613 u8 log_min_stride_sz_sq[0x5]; 1614 1615 u8 hairpin[0x1]; 1616 u8 reserved_at_3c1[0x2]; 1617 u8 log_max_hairpin_queues[0x5]; 1618 u8 reserved_at_3c8[0x3]; 1619 u8 log_max_hairpin_wq_data_sz[0x5]; 1620 u8 reserved_at_3d0[0x3]; 1621 u8 log_max_hairpin_num_packets[0x5]; 1622 u8 reserved_at_3d8[0x3]; 1623 u8 log_max_wq_sz[0x5]; 1624 1625 u8 nic_vport_change_event[0x1]; 1626 u8 disable_local_lb_uc[0x1]; 1627 u8 disable_local_lb_mc[0x1]; 1628 u8 log_min_hairpin_wq_data_sz[0x5]; 1629 u8 reserved_at_3e8[0x2]; 1630 u8 vhca_state[0x1]; 1631 u8 log_max_vlan_list[0x5]; 1632 u8 reserved_at_3f0[0x3]; 1633 u8 log_max_current_mc_list[0x5]; 1634 u8 reserved_at_3f8[0x3]; 1635 u8 log_max_current_uc_list[0x5]; 1636 1637 u8 general_obj_types[0x40]; 1638 1639 u8 sq_ts_format[0x2]; 1640 u8 rq_ts_format[0x2]; 1641 u8 steering_format_version[0x4]; 1642 u8 create_qp_start_hint[0x18]; 1643 1644 u8 reserved_at_460[0x3]; 1645 u8 log_max_uctx[0x5]; 1646 u8 reserved_at_468[0x2]; 1647 u8 ipsec_offload[0x1]; 1648 u8 log_max_umem[0x5]; 1649 u8 max_num_eqs[0x10]; 1650 1651 u8 reserved_at_480[0x1]; 1652 u8 tls_tx[0x1]; 1653 u8 tls_rx[0x1]; 1654 u8 log_max_l2_table[0x5]; 1655 u8 reserved_at_488[0x8]; 1656 u8 log_uar_page_sz[0x10]; 1657 1658 u8 reserved_at_4a0[0x20]; 1659 u8 device_frequency_mhz[0x20]; 1660 u8 device_frequency_khz[0x20]; 1661 1662 u8 reserved_at_500[0x20]; 1663 u8 num_of_uars_per_page[0x20]; 1664 1665 u8 flex_parser_protocols[0x20]; 1666 1667 u8 max_geneve_tlv_options[0x8]; 1668 u8 reserved_at_568[0x3]; 1669 u8 max_geneve_tlv_option_data_len[0x5]; 1670 u8 reserved_at_570[0x10]; 1671 1672 u8 reserved_at_580[0xb]; 1673 u8 log_max_dci_stream_channels[0x5]; 1674 u8 reserved_at_590[0x3]; 1675 u8 log_max_dci_errored_streams[0x5]; 1676 u8 reserved_at_598[0x8]; 1677 1678 u8 reserved_at_5a0[0x13]; 1679 u8 log_max_dek[0x5]; 1680 u8 reserved_at_5b8[0x4]; 1681 u8 mini_cqe_resp_stride_index[0x1]; 1682 u8 cqe_128_always[0x1]; 1683 u8 cqe_compression_128[0x1]; 1684 u8 cqe_compression[0x1]; 1685 1686 u8 cqe_compression_timeout[0x10]; 1687 u8 cqe_compression_max_num[0x10]; 1688 1689 u8 reserved_at_5e0[0x8]; 1690 u8 flex_parser_id_gtpu_dw_0[0x4]; 1691 u8 reserved_at_5ec[0x4]; 1692 u8 tag_matching[0x1]; 1693 u8 rndv_offload_rc[0x1]; 1694 u8 rndv_offload_dc[0x1]; 1695 u8 log_tag_matching_list_sz[0x5]; 1696 u8 reserved_at_5f8[0x3]; 1697 u8 log_max_xrq[0x5]; 1698 1699 u8 affiliate_nic_vport_criteria[0x8]; 1700 u8 native_port_num[0x8]; 1701 u8 num_vhca_ports[0x8]; 1702 u8 flex_parser_id_gtpu_teid[0x4]; 1703 u8 reserved_at_61c[0x2]; 1704 u8 sw_owner_id[0x1]; 1705 u8 reserved_at_61f[0x1]; 1706 1707 u8 max_num_of_monitor_counters[0x10]; 1708 u8 num_ppcnt_monitor_counters[0x10]; 1709 1710 u8 max_num_sf[0x10]; 1711 u8 num_q_monitor_counters[0x10]; 1712 1713 u8 reserved_at_660[0x20]; 1714 1715 u8 sf[0x1]; 1716 u8 sf_set_partition[0x1]; 1717 u8 reserved_at_682[0x1]; 1718 u8 log_max_sf[0x5]; 1719 u8 apu[0x1]; 1720 u8 reserved_at_689[0x7]; 1721 u8 log_min_sf_size[0x8]; 1722 u8 max_num_sf_partitions[0x8]; 1723 1724 u8 uctx_cap[0x20]; 1725 1726 u8 reserved_at_6c0[0x4]; 1727 u8 flex_parser_id_geneve_tlv_option_0[0x4]; 1728 u8 flex_parser_id_icmp_dw1[0x4]; 1729 u8 flex_parser_id_icmp_dw0[0x4]; 1730 u8 flex_parser_id_icmpv6_dw1[0x4]; 1731 u8 flex_parser_id_icmpv6_dw0[0x4]; 1732 u8 flex_parser_id_outer_first_mpls_over_gre[0x4]; 1733 u8 flex_parser_id_outer_first_mpls_over_udp_label[0x4]; 1734 1735 u8 max_num_match_definer[0x10]; 1736 u8 sf_base_id[0x10]; 1737 1738 u8 flex_parser_id_gtpu_dw_2[0x4]; 1739 u8 flex_parser_id_gtpu_first_ext_dw_0[0x4]; 1740 u8 num_total_dynamic_vf_msix[0x18]; 1741 u8 reserved_at_720[0x14]; 1742 u8 dynamic_msix_table_size[0xc]; 1743 u8 reserved_at_740[0xc]; 1744 u8 min_dynamic_vf_msix_table_size[0x4]; 1745 u8 reserved_at_750[0x4]; 1746 u8 max_dynamic_vf_msix_table_size[0xc]; 1747 1748 u8 reserved_at_760[0x20]; 1749 u8 vhca_tunnel_commands[0x40]; 1750 u8 match_definer_format_supported[0x40]; 1751 }; 1752 1753 struct mlx5_ifc_cmd_hca_cap_2_bits { 1754 u8 reserved_at_0[0xa0]; 1755 1756 u8 max_reformat_insert_size[0x8]; 1757 u8 max_reformat_insert_offset[0x8]; 1758 u8 max_reformat_remove_size[0x8]; 1759 u8 max_reformat_remove_offset[0x8]; 1760 1761 u8 reserved_at_c0[0x740]; 1762 }; 1763 1764 enum mlx5_flow_destination_type { 1765 MLX5_FLOW_DESTINATION_TYPE_VPORT = 0x0, 1766 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1, 1767 MLX5_FLOW_DESTINATION_TYPE_TIR = 0x2, 1768 MLX5_FLOW_DESTINATION_TYPE_FLOW_SAMPLER = 0x6, 1769 MLX5_FLOW_DESTINATION_TYPE_UPLINK = 0x8, 1770 1771 MLX5_FLOW_DESTINATION_TYPE_PORT = 0x99, 1772 MLX5_FLOW_DESTINATION_TYPE_COUNTER = 0x100, 1773 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE_NUM = 0x101, 1774 }; 1775 1776 enum mlx5_flow_table_miss_action { 1777 MLX5_FLOW_TABLE_MISS_ACTION_DEF, 1778 MLX5_FLOW_TABLE_MISS_ACTION_FWD, 1779 MLX5_FLOW_TABLE_MISS_ACTION_SWITCH_DOMAIN, 1780 }; 1781 1782 struct mlx5_ifc_dest_format_struct_bits { 1783 u8 destination_type[0x8]; 1784 u8 destination_id[0x18]; 1785 1786 u8 destination_eswitch_owner_vhca_id_valid[0x1]; 1787 u8 packet_reformat[0x1]; 1788 u8 reserved_at_22[0xe]; 1789 u8 destination_eswitch_owner_vhca_id[0x10]; 1790 }; 1791 1792 struct mlx5_ifc_flow_counter_list_bits { 1793 u8 flow_counter_id[0x20]; 1794 1795 u8 reserved_at_20[0x20]; 1796 }; 1797 1798 struct mlx5_ifc_extended_dest_format_bits { 1799 struct mlx5_ifc_dest_format_struct_bits destination_entry; 1800 1801 u8 packet_reformat_id[0x20]; 1802 1803 u8 reserved_at_60[0x20]; 1804 }; 1805 1806 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits { 1807 struct mlx5_ifc_extended_dest_format_bits extended_dest_format; 1808 struct mlx5_ifc_flow_counter_list_bits flow_counter_list; 1809 }; 1810 1811 struct mlx5_ifc_fte_match_param_bits { 1812 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers; 1813 1814 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters; 1815 1816 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers; 1817 1818 struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2; 1819 1820 struct mlx5_ifc_fte_match_set_misc3_bits misc_parameters_3; 1821 1822 struct mlx5_ifc_fte_match_set_misc4_bits misc_parameters_4; 1823 1824 u8 reserved_at_c00[0x400]; 1825 }; 1826 1827 enum { 1828 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0, 1829 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1, 1830 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2, 1831 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3, 1832 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4, 1833 }; 1834 1835 struct mlx5_ifc_rx_hash_field_select_bits { 1836 u8 l3_prot_type[0x1]; 1837 u8 l4_prot_type[0x1]; 1838 u8 selected_fields[0x1e]; 1839 }; 1840 1841 enum { 1842 MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0, 1843 MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1, 1844 }; 1845 1846 enum { 1847 MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0, 1848 MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1, 1849 }; 1850 1851 struct mlx5_ifc_wq_bits { 1852 u8 wq_type[0x4]; 1853 u8 wq_signature[0x1]; 1854 u8 end_padding_mode[0x2]; 1855 u8 cd_slave[0x1]; 1856 u8 reserved_at_8[0x18]; 1857 1858 u8 hds_skip_first_sge[0x1]; 1859 u8 log2_hds_buf_size[0x3]; 1860 u8 reserved_at_24[0x7]; 1861 u8 page_offset[0x5]; 1862 u8 lwm[0x10]; 1863 1864 u8 reserved_at_40[0x8]; 1865 u8 pd[0x18]; 1866 1867 u8 reserved_at_60[0x8]; 1868 u8 uar_page[0x18]; 1869 1870 u8 dbr_addr[0x40]; 1871 1872 u8 hw_counter[0x20]; 1873 1874 u8 sw_counter[0x20]; 1875 1876 u8 reserved_at_100[0xc]; 1877 u8 log_wq_stride[0x4]; 1878 u8 reserved_at_110[0x3]; 1879 u8 log_wq_pg_sz[0x5]; 1880 u8 reserved_at_118[0x3]; 1881 u8 log_wq_sz[0x5]; 1882 1883 u8 dbr_umem_valid[0x1]; 1884 u8 wq_umem_valid[0x1]; 1885 u8 reserved_at_122[0x1]; 1886 u8 log_hairpin_num_packets[0x5]; 1887 u8 reserved_at_128[0x3]; 1888 u8 log_hairpin_data_sz[0x5]; 1889 1890 u8 reserved_at_130[0x4]; 1891 u8 log_wqe_num_of_strides[0x4]; 1892 u8 two_byte_shift_en[0x1]; 1893 u8 reserved_at_139[0x4]; 1894 u8 log_wqe_stride_size[0x3]; 1895 1896 u8 reserved_at_140[0x4c0]; 1897 1898 struct mlx5_ifc_cmd_pas_bits pas[]; 1899 }; 1900 1901 struct mlx5_ifc_rq_num_bits { 1902 u8 reserved_at_0[0x8]; 1903 u8 rq_num[0x18]; 1904 }; 1905 1906 struct mlx5_ifc_mac_address_layout_bits { 1907 u8 reserved_at_0[0x10]; 1908 u8 mac_addr_47_32[0x10]; 1909 1910 u8 mac_addr_31_0[0x20]; 1911 }; 1912 1913 struct mlx5_ifc_vlan_layout_bits { 1914 u8 reserved_at_0[0x14]; 1915 u8 vlan[0x0c]; 1916 1917 u8 reserved_at_20[0x20]; 1918 }; 1919 1920 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits { 1921 u8 reserved_at_0[0xa0]; 1922 1923 u8 min_time_between_cnps[0x20]; 1924 1925 u8 reserved_at_c0[0x12]; 1926 u8 cnp_dscp[0x6]; 1927 u8 reserved_at_d8[0x4]; 1928 u8 cnp_prio_mode[0x1]; 1929 u8 cnp_802p_prio[0x3]; 1930 1931 u8 reserved_at_e0[0x720]; 1932 }; 1933 1934 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits { 1935 u8 reserved_at_0[0x60]; 1936 1937 u8 reserved_at_60[0x4]; 1938 u8 clamp_tgt_rate[0x1]; 1939 u8 reserved_at_65[0x3]; 1940 u8 clamp_tgt_rate_after_time_inc[0x1]; 1941 u8 reserved_at_69[0x17]; 1942 1943 u8 reserved_at_80[0x20]; 1944 1945 u8 rpg_time_reset[0x20]; 1946 1947 u8 rpg_byte_reset[0x20]; 1948 1949 u8 rpg_threshold[0x20]; 1950 1951 u8 rpg_max_rate[0x20]; 1952 1953 u8 rpg_ai_rate[0x20]; 1954 1955 u8 rpg_hai_rate[0x20]; 1956 1957 u8 rpg_gd[0x20]; 1958 1959 u8 rpg_min_dec_fac[0x20]; 1960 1961 u8 rpg_min_rate[0x20]; 1962 1963 u8 reserved_at_1c0[0xe0]; 1964 1965 u8 rate_to_set_on_first_cnp[0x20]; 1966 1967 u8 dce_tcp_g[0x20]; 1968 1969 u8 dce_tcp_rtt[0x20]; 1970 1971 u8 rate_reduce_monitor_period[0x20]; 1972 1973 u8 reserved_at_320[0x20]; 1974 1975 u8 initial_alpha_value[0x20]; 1976 1977 u8 reserved_at_360[0x4a0]; 1978 }; 1979 1980 struct mlx5_ifc_cong_control_802_1qau_rp_bits { 1981 u8 reserved_at_0[0x80]; 1982 1983 u8 rppp_max_rps[0x20]; 1984 1985 u8 rpg_time_reset[0x20]; 1986 1987 u8 rpg_byte_reset[0x20]; 1988 1989 u8 rpg_threshold[0x20]; 1990 1991 u8 rpg_max_rate[0x20]; 1992 1993 u8 rpg_ai_rate[0x20]; 1994 1995 u8 rpg_hai_rate[0x20]; 1996 1997 u8 rpg_gd[0x20]; 1998 1999 u8 rpg_min_dec_fac[0x20]; 2000 2001 u8 rpg_min_rate[0x20]; 2002 2003 u8 reserved_at_1c0[0x640]; 2004 }; 2005 2006 enum { 2007 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1, 2008 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2, 2009 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4, 2010 }; 2011 2012 struct mlx5_ifc_resize_field_select_bits { 2013 u8 resize_field_select[0x20]; 2014 }; 2015 2016 struct mlx5_ifc_resource_dump_bits { 2017 u8 more_dump[0x1]; 2018 u8 inline_dump[0x1]; 2019 u8 reserved_at_2[0xa]; 2020 u8 seq_num[0x4]; 2021 u8 segment_type[0x10]; 2022 2023 u8 reserved_at_20[0x10]; 2024 u8 vhca_id[0x10]; 2025 2026 u8 index1[0x20]; 2027 2028 u8 index2[0x20]; 2029 2030 u8 num_of_obj1[0x10]; 2031 u8 num_of_obj2[0x10]; 2032 2033 u8 reserved_at_a0[0x20]; 2034 2035 u8 device_opaque[0x40]; 2036 2037 u8 mkey[0x20]; 2038 2039 u8 size[0x20]; 2040 2041 u8 address[0x40]; 2042 2043 u8 inline_data[52][0x20]; 2044 }; 2045 2046 struct mlx5_ifc_resource_dump_menu_record_bits { 2047 u8 reserved_at_0[0x4]; 2048 u8 num_of_obj2_supports_active[0x1]; 2049 u8 num_of_obj2_supports_all[0x1]; 2050 u8 must_have_num_of_obj2[0x1]; 2051 u8 support_num_of_obj2[0x1]; 2052 u8 num_of_obj1_supports_active[0x1]; 2053 u8 num_of_obj1_supports_all[0x1]; 2054 u8 must_have_num_of_obj1[0x1]; 2055 u8 support_num_of_obj1[0x1]; 2056 u8 must_have_index2[0x1]; 2057 u8 support_index2[0x1]; 2058 u8 must_have_index1[0x1]; 2059 u8 support_index1[0x1]; 2060 u8 segment_type[0x10]; 2061 2062 u8 segment_name[4][0x20]; 2063 2064 u8 index1_name[4][0x20]; 2065 2066 u8 index2_name[4][0x20]; 2067 }; 2068 2069 struct mlx5_ifc_resource_dump_segment_header_bits { 2070 u8 length_dw[0x10]; 2071 u8 segment_type[0x10]; 2072 }; 2073 2074 struct mlx5_ifc_resource_dump_command_segment_bits { 2075 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2076 2077 u8 segment_called[0x10]; 2078 u8 vhca_id[0x10]; 2079 2080 u8 index1[0x20]; 2081 2082 u8 index2[0x20]; 2083 2084 u8 num_of_obj1[0x10]; 2085 u8 num_of_obj2[0x10]; 2086 }; 2087 2088 struct mlx5_ifc_resource_dump_error_segment_bits { 2089 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2090 2091 u8 reserved_at_20[0x10]; 2092 u8 syndrome_id[0x10]; 2093 2094 u8 reserved_at_40[0x40]; 2095 2096 u8 error[8][0x20]; 2097 }; 2098 2099 struct mlx5_ifc_resource_dump_info_segment_bits { 2100 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2101 2102 u8 reserved_at_20[0x18]; 2103 u8 dump_version[0x8]; 2104 2105 u8 hw_version[0x20]; 2106 2107 u8 fw_version[0x20]; 2108 }; 2109 2110 struct mlx5_ifc_resource_dump_menu_segment_bits { 2111 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2112 2113 u8 reserved_at_20[0x10]; 2114 u8 num_of_records[0x10]; 2115 2116 struct mlx5_ifc_resource_dump_menu_record_bits record[]; 2117 }; 2118 2119 struct mlx5_ifc_resource_dump_resource_segment_bits { 2120 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2121 2122 u8 reserved_at_20[0x20]; 2123 2124 u8 index1[0x20]; 2125 2126 u8 index2[0x20]; 2127 2128 u8 payload[][0x20]; 2129 }; 2130 2131 struct mlx5_ifc_resource_dump_terminate_segment_bits { 2132 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2133 }; 2134 2135 struct mlx5_ifc_menu_resource_dump_response_bits { 2136 struct mlx5_ifc_resource_dump_info_segment_bits info; 2137 struct mlx5_ifc_resource_dump_command_segment_bits cmd; 2138 struct mlx5_ifc_resource_dump_menu_segment_bits menu; 2139 struct mlx5_ifc_resource_dump_terminate_segment_bits terminate; 2140 }; 2141 2142 enum { 2143 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1, 2144 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2, 2145 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4, 2146 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8, 2147 }; 2148 2149 struct mlx5_ifc_modify_field_select_bits { 2150 u8 modify_field_select[0x20]; 2151 }; 2152 2153 struct mlx5_ifc_field_select_r_roce_np_bits { 2154 u8 field_select_r_roce_np[0x20]; 2155 }; 2156 2157 struct mlx5_ifc_field_select_r_roce_rp_bits { 2158 u8 field_select_r_roce_rp[0x20]; 2159 }; 2160 2161 enum { 2162 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4, 2163 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8, 2164 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10, 2165 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20, 2166 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40, 2167 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80, 2168 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100, 2169 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200, 2170 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400, 2171 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800, 2172 }; 2173 2174 struct mlx5_ifc_field_select_802_1qau_rp_bits { 2175 u8 field_select_8021qaurp[0x20]; 2176 }; 2177 2178 struct mlx5_ifc_phys_layer_cntrs_bits { 2179 u8 time_since_last_clear_high[0x20]; 2180 2181 u8 time_since_last_clear_low[0x20]; 2182 2183 u8 symbol_errors_high[0x20]; 2184 2185 u8 symbol_errors_low[0x20]; 2186 2187 u8 sync_headers_errors_high[0x20]; 2188 2189 u8 sync_headers_errors_low[0x20]; 2190 2191 u8 edpl_bip_errors_lane0_high[0x20]; 2192 2193 u8 edpl_bip_errors_lane0_low[0x20]; 2194 2195 u8 edpl_bip_errors_lane1_high[0x20]; 2196 2197 u8 edpl_bip_errors_lane1_low[0x20]; 2198 2199 u8 edpl_bip_errors_lane2_high[0x20]; 2200 2201 u8 edpl_bip_errors_lane2_low[0x20]; 2202 2203 u8 edpl_bip_errors_lane3_high[0x20]; 2204 2205 u8 edpl_bip_errors_lane3_low[0x20]; 2206 2207 u8 fc_fec_corrected_blocks_lane0_high[0x20]; 2208 2209 u8 fc_fec_corrected_blocks_lane0_low[0x20]; 2210 2211 u8 fc_fec_corrected_blocks_lane1_high[0x20]; 2212 2213 u8 fc_fec_corrected_blocks_lane1_low[0x20]; 2214 2215 u8 fc_fec_corrected_blocks_lane2_high[0x20]; 2216 2217 u8 fc_fec_corrected_blocks_lane2_low[0x20]; 2218 2219 u8 fc_fec_corrected_blocks_lane3_high[0x20]; 2220 2221 u8 fc_fec_corrected_blocks_lane3_low[0x20]; 2222 2223 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20]; 2224 2225 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20]; 2226 2227 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20]; 2228 2229 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20]; 2230 2231 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20]; 2232 2233 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20]; 2234 2235 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20]; 2236 2237 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20]; 2238 2239 u8 rs_fec_corrected_blocks_high[0x20]; 2240 2241 u8 rs_fec_corrected_blocks_low[0x20]; 2242 2243 u8 rs_fec_uncorrectable_blocks_high[0x20]; 2244 2245 u8 rs_fec_uncorrectable_blocks_low[0x20]; 2246 2247 u8 rs_fec_no_errors_blocks_high[0x20]; 2248 2249 u8 rs_fec_no_errors_blocks_low[0x20]; 2250 2251 u8 rs_fec_single_error_blocks_high[0x20]; 2252 2253 u8 rs_fec_single_error_blocks_low[0x20]; 2254 2255 u8 rs_fec_corrected_symbols_total_high[0x20]; 2256 2257 u8 rs_fec_corrected_symbols_total_low[0x20]; 2258 2259 u8 rs_fec_corrected_symbols_lane0_high[0x20]; 2260 2261 u8 rs_fec_corrected_symbols_lane0_low[0x20]; 2262 2263 u8 rs_fec_corrected_symbols_lane1_high[0x20]; 2264 2265 u8 rs_fec_corrected_symbols_lane1_low[0x20]; 2266 2267 u8 rs_fec_corrected_symbols_lane2_high[0x20]; 2268 2269 u8 rs_fec_corrected_symbols_lane2_low[0x20]; 2270 2271 u8 rs_fec_corrected_symbols_lane3_high[0x20]; 2272 2273 u8 rs_fec_corrected_symbols_lane3_low[0x20]; 2274 2275 u8 link_down_events[0x20]; 2276 2277 u8 successful_recovery_events[0x20]; 2278 2279 u8 reserved_at_640[0x180]; 2280 }; 2281 2282 struct mlx5_ifc_phys_layer_statistical_cntrs_bits { 2283 u8 time_since_last_clear_high[0x20]; 2284 2285 u8 time_since_last_clear_low[0x20]; 2286 2287 u8 phy_received_bits_high[0x20]; 2288 2289 u8 phy_received_bits_low[0x20]; 2290 2291 u8 phy_symbol_errors_high[0x20]; 2292 2293 u8 phy_symbol_errors_low[0x20]; 2294 2295 u8 phy_corrected_bits_high[0x20]; 2296 2297 u8 phy_corrected_bits_low[0x20]; 2298 2299 u8 phy_corrected_bits_lane0_high[0x20]; 2300 2301 u8 phy_corrected_bits_lane0_low[0x20]; 2302 2303 u8 phy_corrected_bits_lane1_high[0x20]; 2304 2305 u8 phy_corrected_bits_lane1_low[0x20]; 2306 2307 u8 phy_corrected_bits_lane2_high[0x20]; 2308 2309 u8 phy_corrected_bits_lane2_low[0x20]; 2310 2311 u8 phy_corrected_bits_lane3_high[0x20]; 2312 2313 u8 phy_corrected_bits_lane3_low[0x20]; 2314 2315 u8 reserved_at_200[0x5c0]; 2316 }; 2317 2318 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits { 2319 u8 symbol_error_counter[0x10]; 2320 2321 u8 link_error_recovery_counter[0x8]; 2322 2323 u8 link_downed_counter[0x8]; 2324 2325 u8 port_rcv_errors[0x10]; 2326 2327 u8 port_rcv_remote_physical_errors[0x10]; 2328 2329 u8 port_rcv_switch_relay_errors[0x10]; 2330 2331 u8 port_xmit_discards[0x10]; 2332 2333 u8 port_xmit_constraint_errors[0x8]; 2334 2335 u8 port_rcv_constraint_errors[0x8]; 2336 2337 u8 reserved_at_70[0x8]; 2338 2339 u8 link_overrun_errors[0x8]; 2340 2341 u8 reserved_at_80[0x10]; 2342 2343 u8 vl_15_dropped[0x10]; 2344 2345 u8 reserved_at_a0[0x80]; 2346 2347 u8 port_xmit_wait[0x20]; 2348 }; 2349 2350 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits { 2351 u8 transmit_queue_high[0x20]; 2352 2353 u8 transmit_queue_low[0x20]; 2354 2355 u8 no_buffer_discard_uc_high[0x20]; 2356 2357 u8 no_buffer_discard_uc_low[0x20]; 2358 2359 u8 reserved_at_80[0x740]; 2360 }; 2361 2362 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits { 2363 u8 wred_discard_high[0x20]; 2364 2365 u8 wred_discard_low[0x20]; 2366 2367 u8 ecn_marked_tc_high[0x20]; 2368 2369 u8 ecn_marked_tc_low[0x20]; 2370 2371 u8 reserved_at_80[0x740]; 2372 }; 2373 2374 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits { 2375 u8 rx_octets_high[0x20]; 2376 2377 u8 rx_octets_low[0x20]; 2378 2379 u8 reserved_at_40[0xc0]; 2380 2381 u8 rx_frames_high[0x20]; 2382 2383 u8 rx_frames_low[0x20]; 2384 2385 u8 tx_octets_high[0x20]; 2386 2387 u8 tx_octets_low[0x20]; 2388 2389 u8 reserved_at_180[0xc0]; 2390 2391 u8 tx_frames_high[0x20]; 2392 2393 u8 tx_frames_low[0x20]; 2394 2395 u8 rx_pause_high[0x20]; 2396 2397 u8 rx_pause_low[0x20]; 2398 2399 u8 rx_pause_duration_high[0x20]; 2400 2401 u8 rx_pause_duration_low[0x20]; 2402 2403 u8 tx_pause_high[0x20]; 2404 2405 u8 tx_pause_low[0x20]; 2406 2407 u8 tx_pause_duration_high[0x20]; 2408 2409 u8 tx_pause_duration_low[0x20]; 2410 2411 u8 rx_pause_transition_high[0x20]; 2412 2413 u8 rx_pause_transition_low[0x20]; 2414 2415 u8 rx_discards_high[0x20]; 2416 2417 u8 rx_discards_low[0x20]; 2418 2419 u8 device_stall_minor_watermark_cnt_high[0x20]; 2420 2421 u8 device_stall_minor_watermark_cnt_low[0x20]; 2422 2423 u8 device_stall_critical_watermark_cnt_high[0x20]; 2424 2425 u8 device_stall_critical_watermark_cnt_low[0x20]; 2426 2427 u8 reserved_at_480[0x340]; 2428 }; 2429 2430 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits { 2431 u8 port_transmit_wait_high[0x20]; 2432 2433 u8 port_transmit_wait_low[0x20]; 2434 2435 u8 reserved_at_40[0x100]; 2436 2437 u8 rx_buffer_almost_full_high[0x20]; 2438 2439 u8 rx_buffer_almost_full_low[0x20]; 2440 2441 u8 rx_buffer_full_high[0x20]; 2442 2443 u8 rx_buffer_full_low[0x20]; 2444 2445 u8 rx_icrc_encapsulated_high[0x20]; 2446 2447 u8 rx_icrc_encapsulated_low[0x20]; 2448 2449 u8 reserved_at_200[0x5c0]; 2450 }; 2451 2452 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits { 2453 u8 dot3stats_alignment_errors_high[0x20]; 2454 2455 u8 dot3stats_alignment_errors_low[0x20]; 2456 2457 u8 dot3stats_fcs_errors_high[0x20]; 2458 2459 u8 dot3stats_fcs_errors_low[0x20]; 2460 2461 u8 dot3stats_single_collision_frames_high[0x20]; 2462 2463 u8 dot3stats_single_collision_frames_low[0x20]; 2464 2465 u8 dot3stats_multiple_collision_frames_high[0x20]; 2466 2467 u8 dot3stats_multiple_collision_frames_low[0x20]; 2468 2469 u8 dot3stats_sqe_test_errors_high[0x20]; 2470 2471 u8 dot3stats_sqe_test_errors_low[0x20]; 2472 2473 u8 dot3stats_deferred_transmissions_high[0x20]; 2474 2475 u8 dot3stats_deferred_transmissions_low[0x20]; 2476 2477 u8 dot3stats_late_collisions_high[0x20]; 2478 2479 u8 dot3stats_late_collisions_low[0x20]; 2480 2481 u8 dot3stats_excessive_collisions_high[0x20]; 2482 2483 u8 dot3stats_excessive_collisions_low[0x20]; 2484 2485 u8 dot3stats_internal_mac_transmit_errors_high[0x20]; 2486 2487 u8 dot3stats_internal_mac_transmit_errors_low[0x20]; 2488 2489 u8 dot3stats_carrier_sense_errors_high[0x20]; 2490 2491 u8 dot3stats_carrier_sense_errors_low[0x20]; 2492 2493 u8 dot3stats_frame_too_longs_high[0x20]; 2494 2495 u8 dot3stats_frame_too_longs_low[0x20]; 2496 2497 u8 dot3stats_internal_mac_receive_errors_high[0x20]; 2498 2499 u8 dot3stats_internal_mac_receive_errors_low[0x20]; 2500 2501 u8 dot3stats_symbol_errors_high[0x20]; 2502 2503 u8 dot3stats_symbol_errors_low[0x20]; 2504 2505 u8 dot3control_in_unknown_opcodes_high[0x20]; 2506 2507 u8 dot3control_in_unknown_opcodes_low[0x20]; 2508 2509 u8 dot3in_pause_frames_high[0x20]; 2510 2511 u8 dot3in_pause_frames_low[0x20]; 2512 2513 u8 dot3out_pause_frames_high[0x20]; 2514 2515 u8 dot3out_pause_frames_low[0x20]; 2516 2517 u8 reserved_at_400[0x3c0]; 2518 }; 2519 2520 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits { 2521 u8 ether_stats_drop_events_high[0x20]; 2522 2523 u8 ether_stats_drop_events_low[0x20]; 2524 2525 u8 ether_stats_octets_high[0x20]; 2526 2527 u8 ether_stats_octets_low[0x20]; 2528 2529 u8 ether_stats_pkts_high[0x20]; 2530 2531 u8 ether_stats_pkts_low[0x20]; 2532 2533 u8 ether_stats_broadcast_pkts_high[0x20]; 2534 2535 u8 ether_stats_broadcast_pkts_low[0x20]; 2536 2537 u8 ether_stats_multicast_pkts_high[0x20]; 2538 2539 u8 ether_stats_multicast_pkts_low[0x20]; 2540 2541 u8 ether_stats_crc_align_errors_high[0x20]; 2542 2543 u8 ether_stats_crc_align_errors_low[0x20]; 2544 2545 u8 ether_stats_undersize_pkts_high[0x20]; 2546 2547 u8 ether_stats_undersize_pkts_low[0x20]; 2548 2549 u8 ether_stats_oversize_pkts_high[0x20]; 2550 2551 u8 ether_stats_oversize_pkts_low[0x20]; 2552 2553 u8 ether_stats_fragments_high[0x20]; 2554 2555 u8 ether_stats_fragments_low[0x20]; 2556 2557 u8 ether_stats_jabbers_high[0x20]; 2558 2559 u8 ether_stats_jabbers_low[0x20]; 2560 2561 u8 ether_stats_collisions_high[0x20]; 2562 2563 u8 ether_stats_collisions_low[0x20]; 2564 2565 u8 ether_stats_pkts64octets_high[0x20]; 2566 2567 u8 ether_stats_pkts64octets_low[0x20]; 2568 2569 u8 ether_stats_pkts65to127octets_high[0x20]; 2570 2571 u8 ether_stats_pkts65to127octets_low[0x20]; 2572 2573 u8 ether_stats_pkts128to255octets_high[0x20]; 2574 2575 u8 ether_stats_pkts128to255octets_low[0x20]; 2576 2577 u8 ether_stats_pkts256to511octets_high[0x20]; 2578 2579 u8 ether_stats_pkts256to511octets_low[0x20]; 2580 2581 u8 ether_stats_pkts512to1023octets_high[0x20]; 2582 2583 u8 ether_stats_pkts512to1023octets_low[0x20]; 2584 2585 u8 ether_stats_pkts1024to1518octets_high[0x20]; 2586 2587 u8 ether_stats_pkts1024to1518octets_low[0x20]; 2588 2589 u8 ether_stats_pkts1519to2047octets_high[0x20]; 2590 2591 u8 ether_stats_pkts1519to2047octets_low[0x20]; 2592 2593 u8 ether_stats_pkts2048to4095octets_high[0x20]; 2594 2595 u8 ether_stats_pkts2048to4095octets_low[0x20]; 2596 2597 u8 ether_stats_pkts4096to8191octets_high[0x20]; 2598 2599 u8 ether_stats_pkts4096to8191octets_low[0x20]; 2600 2601 u8 ether_stats_pkts8192to10239octets_high[0x20]; 2602 2603 u8 ether_stats_pkts8192to10239octets_low[0x20]; 2604 2605 u8 reserved_at_540[0x280]; 2606 }; 2607 2608 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits { 2609 u8 if_in_octets_high[0x20]; 2610 2611 u8 if_in_octets_low[0x20]; 2612 2613 u8 if_in_ucast_pkts_high[0x20]; 2614 2615 u8 if_in_ucast_pkts_low[0x20]; 2616 2617 u8 if_in_discards_high[0x20]; 2618 2619 u8 if_in_discards_low[0x20]; 2620 2621 u8 if_in_errors_high[0x20]; 2622 2623 u8 if_in_errors_low[0x20]; 2624 2625 u8 if_in_unknown_protos_high[0x20]; 2626 2627 u8 if_in_unknown_protos_low[0x20]; 2628 2629 u8 if_out_octets_high[0x20]; 2630 2631 u8 if_out_octets_low[0x20]; 2632 2633 u8 if_out_ucast_pkts_high[0x20]; 2634 2635 u8 if_out_ucast_pkts_low[0x20]; 2636 2637 u8 if_out_discards_high[0x20]; 2638 2639 u8 if_out_discards_low[0x20]; 2640 2641 u8 if_out_errors_high[0x20]; 2642 2643 u8 if_out_errors_low[0x20]; 2644 2645 u8 if_in_multicast_pkts_high[0x20]; 2646 2647 u8 if_in_multicast_pkts_low[0x20]; 2648 2649 u8 if_in_broadcast_pkts_high[0x20]; 2650 2651 u8 if_in_broadcast_pkts_low[0x20]; 2652 2653 u8 if_out_multicast_pkts_high[0x20]; 2654 2655 u8 if_out_multicast_pkts_low[0x20]; 2656 2657 u8 if_out_broadcast_pkts_high[0x20]; 2658 2659 u8 if_out_broadcast_pkts_low[0x20]; 2660 2661 u8 reserved_at_340[0x480]; 2662 }; 2663 2664 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits { 2665 u8 a_frames_transmitted_ok_high[0x20]; 2666 2667 u8 a_frames_transmitted_ok_low[0x20]; 2668 2669 u8 a_frames_received_ok_high[0x20]; 2670 2671 u8 a_frames_received_ok_low[0x20]; 2672 2673 u8 a_frame_check_sequence_errors_high[0x20]; 2674 2675 u8 a_frame_check_sequence_errors_low[0x20]; 2676 2677 u8 a_alignment_errors_high[0x20]; 2678 2679 u8 a_alignment_errors_low[0x20]; 2680 2681 u8 a_octets_transmitted_ok_high[0x20]; 2682 2683 u8 a_octets_transmitted_ok_low[0x20]; 2684 2685 u8 a_octets_received_ok_high[0x20]; 2686 2687 u8 a_octets_received_ok_low[0x20]; 2688 2689 u8 a_multicast_frames_xmitted_ok_high[0x20]; 2690 2691 u8 a_multicast_frames_xmitted_ok_low[0x20]; 2692 2693 u8 a_broadcast_frames_xmitted_ok_high[0x20]; 2694 2695 u8 a_broadcast_frames_xmitted_ok_low[0x20]; 2696 2697 u8 a_multicast_frames_received_ok_high[0x20]; 2698 2699 u8 a_multicast_frames_received_ok_low[0x20]; 2700 2701 u8 a_broadcast_frames_received_ok_high[0x20]; 2702 2703 u8 a_broadcast_frames_received_ok_low[0x20]; 2704 2705 u8 a_in_range_length_errors_high[0x20]; 2706 2707 u8 a_in_range_length_errors_low[0x20]; 2708 2709 u8 a_out_of_range_length_field_high[0x20]; 2710 2711 u8 a_out_of_range_length_field_low[0x20]; 2712 2713 u8 a_frame_too_long_errors_high[0x20]; 2714 2715 u8 a_frame_too_long_errors_low[0x20]; 2716 2717 u8 a_symbol_error_during_carrier_high[0x20]; 2718 2719 u8 a_symbol_error_during_carrier_low[0x20]; 2720 2721 u8 a_mac_control_frames_transmitted_high[0x20]; 2722 2723 u8 a_mac_control_frames_transmitted_low[0x20]; 2724 2725 u8 a_mac_control_frames_received_high[0x20]; 2726 2727 u8 a_mac_control_frames_received_low[0x20]; 2728 2729 u8 a_unsupported_opcodes_received_high[0x20]; 2730 2731 u8 a_unsupported_opcodes_received_low[0x20]; 2732 2733 u8 a_pause_mac_ctrl_frames_received_high[0x20]; 2734 2735 u8 a_pause_mac_ctrl_frames_received_low[0x20]; 2736 2737 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20]; 2738 2739 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20]; 2740 2741 u8 reserved_at_4c0[0x300]; 2742 }; 2743 2744 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits { 2745 u8 life_time_counter_high[0x20]; 2746 2747 u8 life_time_counter_low[0x20]; 2748 2749 u8 rx_errors[0x20]; 2750 2751 u8 tx_errors[0x20]; 2752 2753 u8 l0_to_recovery_eieos[0x20]; 2754 2755 u8 l0_to_recovery_ts[0x20]; 2756 2757 u8 l0_to_recovery_framing[0x20]; 2758 2759 u8 l0_to_recovery_retrain[0x20]; 2760 2761 u8 crc_error_dllp[0x20]; 2762 2763 u8 crc_error_tlp[0x20]; 2764 2765 u8 tx_overflow_buffer_pkt_high[0x20]; 2766 2767 u8 tx_overflow_buffer_pkt_low[0x20]; 2768 2769 u8 outbound_stalled_reads[0x20]; 2770 2771 u8 outbound_stalled_writes[0x20]; 2772 2773 u8 outbound_stalled_reads_events[0x20]; 2774 2775 u8 outbound_stalled_writes_events[0x20]; 2776 2777 u8 reserved_at_200[0x5c0]; 2778 }; 2779 2780 struct mlx5_ifc_cmd_inter_comp_event_bits { 2781 u8 command_completion_vector[0x20]; 2782 2783 u8 reserved_at_20[0xc0]; 2784 }; 2785 2786 struct mlx5_ifc_stall_vl_event_bits { 2787 u8 reserved_at_0[0x18]; 2788 u8 port_num[0x1]; 2789 u8 reserved_at_19[0x3]; 2790 u8 vl[0x4]; 2791 2792 u8 reserved_at_20[0xa0]; 2793 }; 2794 2795 struct mlx5_ifc_db_bf_congestion_event_bits { 2796 u8 event_subtype[0x8]; 2797 u8 reserved_at_8[0x8]; 2798 u8 congestion_level[0x8]; 2799 u8 reserved_at_18[0x8]; 2800 2801 u8 reserved_at_20[0xa0]; 2802 }; 2803 2804 struct mlx5_ifc_gpio_event_bits { 2805 u8 reserved_at_0[0x60]; 2806 2807 u8 gpio_event_hi[0x20]; 2808 2809 u8 gpio_event_lo[0x20]; 2810 2811 u8 reserved_at_a0[0x40]; 2812 }; 2813 2814 struct mlx5_ifc_port_state_change_event_bits { 2815 u8 reserved_at_0[0x40]; 2816 2817 u8 port_num[0x4]; 2818 u8 reserved_at_44[0x1c]; 2819 2820 u8 reserved_at_60[0x80]; 2821 }; 2822 2823 struct mlx5_ifc_dropped_packet_logged_bits { 2824 u8 reserved_at_0[0xe0]; 2825 }; 2826 2827 struct mlx5_ifc_default_timeout_bits { 2828 u8 to_multiplier[0x3]; 2829 u8 reserved_at_3[0x9]; 2830 u8 to_value[0x14]; 2831 }; 2832 2833 struct mlx5_ifc_dtor_reg_bits { 2834 u8 reserved_at_0[0x20]; 2835 2836 struct mlx5_ifc_default_timeout_bits pcie_toggle_to; 2837 2838 u8 reserved_at_40[0x60]; 2839 2840 struct mlx5_ifc_default_timeout_bits health_poll_to; 2841 2842 struct mlx5_ifc_default_timeout_bits full_crdump_to; 2843 2844 struct mlx5_ifc_default_timeout_bits fw_reset_to; 2845 2846 struct mlx5_ifc_default_timeout_bits flush_on_err_to; 2847 2848 struct mlx5_ifc_default_timeout_bits pci_sync_update_to; 2849 2850 struct mlx5_ifc_default_timeout_bits tear_down_to; 2851 2852 struct mlx5_ifc_default_timeout_bits fsm_reactivate_to; 2853 2854 struct mlx5_ifc_default_timeout_bits reclaim_pages_to; 2855 2856 struct mlx5_ifc_default_timeout_bits reclaim_vfs_pages_to; 2857 2858 u8 reserved_at_1c0[0x40]; 2859 }; 2860 2861 enum { 2862 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1, 2863 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2, 2864 }; 2865 2866 struct mlx5_ifc_cq_error_bits { 2867 u8 reserved_at_0[0x8]; 2868 u8 cqn[0x18]; 2869 2870 u8 reserved_at_20[0x20]; 2871 2872 u8 reserved_at_40[0x18]; 2873 u8 syndrome[0x8]; 2874 2875 u8 reserved_at_60[0x80]; 2876 }; 2877 2878 struct mlx5_ifc_rdma_page_fault_event_bits { 2879 u8 bytes_committed[0x20]; 2880 2881 u8 r_key[0x20]; 2882 2883 u8 reserved_at_40[0x10]; 2884 u8 packet_len[0x10]; 2885 2886 u8 rdma_op_len[0x20]; 2887 2888 u8 rdma_va[0x40]; 2889 2890 u8 reserved_at_c0[0x5]; 2891 u8 rdma[0x1]; 2892 u8 write[0x1]; 2893 u8 requestor[0x1]; 2894 u8 qp_number[0x18]; 2895 }; 2896 2897 struct mlx5_ifc_wqe_associated_page_fault_event_bits { 2898 u8 bytes_committed[0x20]; 2899 2900 u8 reserved_at_20[0x10]; 2901 u8 wqe_index[0x10]; 2902 2903 u8 reserved_at_40[0x10]; 2904 u8 len[0x10]; 2905 2906 u8 reserved_at_60[0x60]; 2907 2908 u8 reserved_at_c0[0x5]; 2909 u8 rdma[0x1]; 2910 u8 write_read[0x1]; 2911 u8 requestor[0x1]; 2912 u8 qpn[0x18]; 2913 }; 2914 2915 struct mlx5_ifc_qp_events_bits { 2916 u8 reserved_at_0[0xa0]; 2917 2918 u8 type[0x8]; 2919 u8 reserved_at_a8[0x18]; 2920 2921 u8 reserved_at_c0[0x8]; 2922 u8 qpn_rqn_sqn[0x18]; 2923 }; 2924 2925 struct mlx5_ifc_dct_events_bits { 2926 u8 reserved_at_0[0xc0]; 2927 2928 u8 reserved_at_c0[0x8]; 2929 u8 dct_number[0x18]; 2930 }; 2931 2932 struct mlx5_ifc_comp_event_bits { 2933 u8 reserved_at_0[0xc0]; 2934 2935 u8 reserved_at_c0[0x8]; 2936 u8 cq_number[0x18]; 2937 }; 2938 2939 enum { 2940 MLX5_QPC_STATE_RST = 0x0, 2941 MLX5_QPC_STATE_INIT = 0x1, 2942 MLX5_QPC_STATE_RTR = 0x2, 2943 MLX5_QPC_STATE_RTS = 0x3, 2944 MLX5_QPC_STATE_SQER = 0x4, 2945 MLX5_QPC_STATE_ERR = 0x6, 2946 MLX5_QPC_STATE_SQD = 0x7, 2947 MLX5_QPC_STATE_SUSPENDED = 0x9, 2948 }; 2949 2950 enum { 2951 MLX5_QPC_ST_RC = 0x0, 2952 MLX5_QPC_ST_UC = 0x1, 2953 MLX5_QPC_ST_UD = 0x2, 2954 MLX5_QPC_ST_XRC = 0x3, 2955 MLX5_QPC_ST_DCI = 0x5, 2956 MLX5_QPC_ST_QP0 = 0x7, 2957 MLX5_QPC_ST_QP1 = 0x8, 2958 MLX5_QPC_ST_RAW_DATAGRAM = 0x9, 2959 MLX5_QPC_ST_REG_UMR = 0xc, 2960 }; 2961 2962 enum { 2963 MLX5_QPC_PM_STATE_ARMED = 0x0, 2964 MLX5_QPC_PM_STATE_REARM = 0x1, 2965 MLX5_QPC_PM_STATE_RESERVED = 0x2, 2966 MLX5_QPC_PM_STATE_MIGRATED = 0x3, 2967 }; 2968 2969 enum { 2970 MLX5_QPC_OFFLOAD_TYPE_RNDV = 0x1, 2971 }; 2972 2973 enum { 2974 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0, 2975 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1, 2976 }; 2977 2978 enum { 2979 MLX5_QPC_MTU_256_BYTES = 0x1, 2980 MLX5_QPC_MTU_512_BYTES = 0x2, 2981 MLX5_QPC_MTU_1K_BYTES = 0x3, 2982 MLX5_QPC_MTU_2K_BYTES = 0x4, 2983 MLX5_QPC_MTU_4K_BYTES = 0x5, 2984 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7, 2985 }; 2986 2987 enum { 2988 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1, 2989 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2, 2990 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3, 2991 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4, 2992 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5, 2993 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6, 2994 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7, 2995 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8, 2996 }; 2997 2998 enum { 2999 MLX5_QPC_CS_REQ_DISABLE = 0x0, 3000 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11, 3001 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22, 3002 }; 3003 3004 enum { 3005 MLX5_QPC_CS_RES_DISABLE = 0x0, 3006 MLX5_QPC_CS_RES_UP_TO_32B = 0x1, 3007 MLX5_QPC_CS_RES_UP_TO_64B = 0x2, 3008 }; 3009 3010 enum { 3011 MLX5_TIMESTAMP_FORMAT_FREE_RUNNING = 0x0, 3012 MLX5_TIMESTAMP_FORMAT_DEFAULT = 0x1, 3013 MLX5_TIMESTAMP_FORMAT_REAL_TIME = 0x2, 3014 }; 3015 3016 struct mlx5_ifc_qpc_bits { 3017 u8 state[0x4]; 3018 u8 lag_tx_port_affinity[0x4]; 3019 u8 st[0x8]; 3020 u8 reserved_at_10[0x2]; 3021 u8 isolate_vl_tc[0x1]; 3022 u8 pm_state[0x2]; 3023 u8 reserved_at_15[0x1]; 3024 u8 req_e2e_credit_mode[0x2]; 3025 u8 offload_type[0x4]; 3026 u8 end_padding_mode[0x2]; 3027 u8 reserved_at_1e[0x2]; 3028 3029 u8 wq_signature[0x1]; 3030 u8 block_lb_mc[0x1]; 3031 u8 atomic_like_write_en[0x1]; 3032 u8 latency_sensitive[0x1]; 3033 u8 reserved_at_24[0x1]; 3034 u8 drain_sigerr[0x1]; 3035 u8 reserved_at_26[0x2]; 3036 u8 pd[0x18]; 3037 3038 u8 mtu[0x3]; 3039 u8 log_msg_max[0x5]; 3040 u8 reserved_at_48[0x1]; 3041 u8 log_rq_size[0x4]; 3042 u8 log_rq_stride[0x3]; 3043 u8 no_sq[0x1]; 3044 u8 log_sq_size[0x4]; 3045 u8 reserved_at_55[0x3]; 3046 u8 ts_format[0x2]; 3047 u8 reserved_at_5a[0x1]; 3048 u8 rlky[0x1]; 3049 u8 ulp_stateless_offload_mode[0x4]; 3050 3051 u8 counter_set_id[0x8]; 3052 u8 uar_page[0x18]; 3053 3054 u8 reserved_at_80[0x8]; 3055 u8 user_index[0x18]; 3056 3057 u8 reserved_at_a0[0x3]; 3058 u8 log_page_size[0x5]; 3059 u8 remote_qpn[0x18]; 3060 3061 struct mlx5_ifc_ads_bits primary_address_path; 3062 3063 struct mlx5_ifc_ads_bits secondary_address_path; 3064 3065 u8 log_ack_req_freq[0x4]; 3066 u8 reserved_at_384[0x4]; 3067 u8 log_sra_max[0x3]; 3068 u8 reserved_at_38b[0x2]; 3069 u8 retry_count[0x3]; 3070 u8 rnr_retry[0x3]; 3071 u8 reserved_at_393[0x1]; 3072 u8 fre[0x1]; 3073 u8 cur_rnr_retry[0x3]; 3074 u8 cur_retry_count[0x3]; 3075 u8 reserved_at_39b[0x5]; 3076 3077 u8 reserved_at_3a0[0x20]; 3078 3079 u8 reserved_at_3c0[0x8]; 3080 u8 next_send_psn[0x18]; 3081 3082 u8 reserved_at_3e0[0x3]; 3083 u8 log_num_dci_stream_channels[0x5]; 3084 u8 cqn_snd[0x18]; 3085 3086 u8 reserved_at_400[0x3]; 3087 u8 log_num_dci_errored_streams[0x5]; 3088 u8 deth_sqpn[0x18]; 3089 3090 u8 reserved_at_420[0x20]; 3091 3092 u8 reserved_at_440[0x8]; 3093 u8 last_acked_psn[0x18]; 3094 3095 u8 reserved_at_460[0x8]; 3096 u8 ssn[0x18]; 3097 3098 u8 reserved_at_480[0x8]; 3099 u8 log_rra_max[0x3]; 3100 u8 reserved_at_48b[0x1]; 3101 u8 atomic_mode[0x4]; 3102 u8 rre[0x1]; 3103 u8 rwe[0x1]; 3104 u8 rae[0x1]; 3105 u8 reserved_at_493[0x1]; 3106 u8 page_offset[0x6]; 3107 u8 reserved_at_49a[0x3]; 3108 u8 cd_slave_receive[0x1]; 3109 u8 cd_slave_send[0x1]; 3110 u8 cd_master[0x1]; 3111 3112 u8 reserved_at_4a0[0x3]; 3113 u8 min_rnr_nak[0x5]; 3114 u8 next_rcv_psn[0x18]; 3115 3116 u8 reserved_at_4c0[0x8]; 3117 u8 xrcd[0x18]; 3118 3119 u8 reserved_at_4e0[0x8]; 3120 u8 cqn_rcv[0x18]; 3121 3122 u8 dbr_addr[0x40]; 3123 3124 u8 q_key[0x20]; 3125 3126 u8 reserved_at_560[0x5]; 3127 u8 rq_type[0x3]; 3128 u8 srqn_rmpn_xrqn[0x18]; 3129 3130 u8 reserved_at_580[0x8]; 3131 u8 rmsn[0x18]; 3132 3133 u8 hw_sq_wqebb_counter[0x10]; 3134 u8 sw_sq_wqebb_counter[0x10]; 3135 3136 u8 hw_rq_counter[0x20]; 3137 3138 u8 sw_rq_counter[0x20]; 3139 3140 u8 reserved_at_600[0x20]; 3141 3142 u8 reserved_at_620[0xf]; 3143 u8 cgs[0x1]; 3144 u8 cs_req[0x8]; 3145 u8 cs_res[0x8]; 3146 3147 u8 dc_access_key[0x40]; 3148 3149 u8 reserved_at_680[0x3]; 3150 u8 dbr_umem_valid[0x1]; 3151 3152 u8 reserved_at_684[0xbc]; 3153 }; 3154 3155 struct mlx5_ifc_roce_addr_layout_bits { 3156 u8 source_l3_address[16][0x8]; 3157 3158 u8 reserved_at_80[0x3]; 3159 u8 vlan_valid[0x1]; 3160 u8 vlan_id[0xc]; 3161 u8 source_mac_47_32[0x10]; 3162 3163 u8 source_mac_31_0[0x20]; 3164 3165 u8 reserved_at_c0[0x14]; 3166 u8 roce_l3_type[0x4]; 3167 u8 roce_version[0x8]; 3168 3169 u8 reserved_at_e0[0x20]; 3170 }; 3171 3172 union mlx5_ifc_hca_cap_union_bits { 3173 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap; 3174 struct mlx5_ifc_cmd_hca_cap_2_bits cmd_hca_cap_2; 3175 struct mlx5_ifc_odp_cap_bits odp_cap; 3176 struct mlx5_ifc_atomic_caps_bits atomic_caps; 3177 struct mlx5_ifc_roce_cap_bits roce_cap; 3178 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps; 3179 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap; 3180 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap; 3181 struct mlx5_ifc_e_switch_cap_bits e_switch_cap; 3182 struct mlx5_ifc_port_selection_cap_bits port_selection_cap; 3183 struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap; 3184 struct mlx5_ifc_qos_cap_bits qos_cap; 3185 struct mlx5_ifc_debug_cap_bits debug_cap; 3186 struct mlx5_ifc_fpga_cap_bits fpga_cap; 3187 struct mlx5_ifc_tls_cap_bits tls_cap; 3188 struct mlx5_ifc_device_mem_cap_bits device_mem_cap; 3189 struct mlx5_ifc_virtio_emulation_cap_bits virtio_emulation_cap; 3190 u8 reserved_at_0[0x8000]; 3191 }; 3192 3193 enum { 3194 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1, 3195 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2, 3196 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4, 3197 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8, 3198 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT = 0x10, 3199 MLX5_FLOW_CONTEXT_ACTION_DECAP = 0x20, 3200 MLX5_FLOW_CONTEXT_ACTION_MOD_HDR = 0x40, 3201 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP = 0x80, 3202 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100, 3203 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2 = 0x400, 3204 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2 = 0x800, 3205 MLX5_FLOW_CONTEXT_ACTION_IPSEC_DECRYPT = 0x1000, 3206 MLX5_FLOW_CONTEXT_ACTION_IPSEC_ENCRYPT = 0x2000, 3207 }; 3208 3209 enum { 3210 MLX5_FLOW_CONTEXT_FLOW_SOURCE_ANY_VPORT = 0x0, 3211 MLX5_FLOW_CONTEXT_FLOW_SOURCE_UPLINK = 0x1, 3212 MLX5_FLOW_CONTEXT_FLOW_SOURCE_LOCAL_VPORT = 0x2, 3213 }; 3214 3215 struct mlx5_ifc_vlan_bits { 3216 u8 ethtype[0x10]; 3217 u8 prio[0x3]; 3218 u8 cfi[0x1]; 3219 u8 vid[0xc]; 3220 }; 3221 3222 struct mlx5_ifc_flow_context_bits { 3223 struct mlx5_ifc_vlan_bits push_vlan; 3224 3225 u8 group_id[0x20]; 3226 3227 u8 reserved_at_40[0x8]; 3228 u8 flow_tag[0x18]; 3229 3230 u8 reserved_at_60[0x10]; 3231 u8 action[0x10]; 3232 3233 u8 extended_destination[0x1]; 3234 u8 reserved_at_81[0x1]; 3235 u8 flow_source[0x2]; 3236 u8 reserved_at_84[0x4]; 3237 u8 destination_list_size[0x18]; 3238 3239 u8 reserved_at_a0[0x8]; 3240 u8 flow_counter_list_size[0x18]; 3241 3242 u8 packet_reformat_id[0x20]; 3243 3244 u8 modify_header_id[0x20]; 3245 3246 struct mlx5_ifc_vlan_bits push_vlan_2; 3247 3248 u8 ipsec_obj_id[0x20]; 3249 u8 reserved_at_140[0xc0]; 3250 3251 struct mlx5_ifc_fte_match_param_bits match_value; 3252 3253 u8 reserved_at_1200[0x600]; 3254 3255 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[]; 3256 }; 3257 3258 enum { 3259 MLX5_XRC_SRQC_STATE_GOOD = 0x0, 3260 MLX5_XRC_SRQC_STATE_ERROR = 0x1, 3261 }; 3262 3263 struct mlx5_ifc_xrc_srqc_bits { 3264 u8 state[0x4]; 3265 u8 log_xrc_srq_size[0x4]; 3266 u8 reserved_at_8[0x18]; 3267 3268 u8 wq_signature[0x1]; 3269 u8 cont_srq[0x1]; 3270 u8 reserved_at_22[0x1]; 3271 u8 rlky[0x1]; 3272 u8 basic_cyclic_rcv_wqe[0x1]; 3273 u8 log_rq_stride[0x3]; 3274 u8 xrcd[0x18]; 3275 3276 u8 page_offset[0x6]; 3277 u8 reserved_at_46[0x1]; 3278 u8 dbr_umem_valid[0x1]; 3279 u8 cqn[0x18]; 3280 3281 u8 reserved_at_60[0x20]; 3282 3283 u8 user_index_equal_xrc_srqn[0x1]; 3284 u8 reserved_at_81[0x1]; 3285 u8 log_page_size[0x6]; 3286 u8 user_index[0x18]; 3287 3288 u8 reserved_at_a0[0x20]; 3289 3290 u8 reserved_at_c0[0x8]; 3291 u8 pd[0x18]; 3292 3293 u8 lwm[0x10]; 3294 u8 wqe_cnt[0x10]; 3295 3296 u8 reserved_at_100[0x40]; 3297 3298 u8 db_record_addr_h[0x20]; 3299 3300 u8 db_record_addr_l[0x1e]; 3301 u8 reserved_at_17e[0x2]; 3302 3303 u8 reserved_at_180[0x80]; 3304 }; 3305 3306 struct mlx5_ifc_vnic_diagnostic_statistics_bits { 3307 u8 counter_error_queues[0x20]; 3308 3309 u8 total_error_queues[0x20]; 3310 3311 u8 send_queue_priority_update_flow[0x20]; 3312 3313 u8 reserved_at_60[0x20]; 3314 3315 u8 nic_receive_steering_discard[0x40]; 3316 3317 u8 receive_discard_vport_down[0x40]; 3318 3319 u8 transmit_discard_vport_down[0x40]; 3320 3321 u8 reserved_at_140[0xa0]; 3322 3323 u8 internal_rq_out_of_buffer[0x20]; 3324 3325 u8 reserved_at_200[0xe00]; 3326 }; 3327 3328 struct mlx5_ifc_traffic_counter_bits { 3329 u8 packets[0x40]; 3330 3331 u8 octets[0x40]; 3332 }; 3333 3334 struct mlx5_ifc_tisc_bits { 3335 u8 strict_lag_tx_port_affinity[0x1]; 3336 u8 tls_en[0x1]; 3337 u8 reserved_at_2[0x2]; 3338 u8 lag_tx_port_affinity[0x04]; 3339 3340 u8 reserved_at_8[0x4]; 3341 u8 prio[0x4]; 3342 u8 reserved_at_10[0x10]; 3343 3344 u8 reserved_at_20[0x100]; 3345 3346 u8 reserved_at_120[0x8]; 3347 u8 transport_domain[0x18]; 3348 3349 u8 reserved_at_140[0x8]; 3350 u8 underlay_qpn[0x18]; 3351 3352 u8 reserved_at_160[0x8]; 3353 u8 pd[0x18]; 3354 3355 u8 reserved_at_180[0x380]; 3356 }; 3357 3358 enum { 3359 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0, 3360 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1, 3361 }; 3362 3363 enum { 3364 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO = 0x1, 3365 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO = 0x2, 3366 }; 3367 3368 enum { 3369 MLX5_RX_HASH_FN_NONE = 0x0, 3370 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1, 3371 MLX5_RX_HASH_FN_TOEPLITZ = 0x2, 3372 }; 3373 3374 enum { 3375 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST = 0x1, 3376 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST = 0x2, 3377 }; 3378 3379 struct mlx5_ifc_tirc_bits { 3380 u8 reserved_at_0[0x20]; 3381 3382 u8 disp_type[0x4]; 3383 u8 tls_en[0x1]; 3384 u8 reserved_at_25[0x1b]; 3385 3386 u8 reserved_at_40[0x40]; 3387 3388 u8 reserved_at_80[0x4]; 3389 u8 lro_timeout_period_usecs[0x10]; 3390 u8 lro_enable_mask[0x4]; 3391 u8 lro_max_ip_payload_size[0x8]; 3392 3393 u8 reserved_at_a0[0x40]; 3394 3395 u8 reserved_at_e0[0x8]; 3396 u8 inline_rqn[0x18]; 3397 3398 u8 rx_hash_symmetric[0x1]; 3399 u8 reserved_at_101[0x1]; 3400 u8 tunneled_offload_en[0x1]; 3401 u8 reserved_at_103[0x5]; 3402 u8 indirect_table[0x18]; 3403 3404 u8 rx_hash_fn[0x4]; 3405 u8 reserved_at_124[0x2]; 3406 u8 self_lb_block[0x2]; 3407 u8 transport_domain[0x18]; 3408 3409 u8 rx_hash_toeplitz_key[10][0x20]; 3410 3411 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer; 3412 3413 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner; 3414 3415 u8 reserved_at_2c0[0x4c0]; 3416 }; 3417 3418 enum { 3419 MLX5_SRQC_STATE_GOOD = 0x0, 3420 MLX5_SRQC_STATE_ERROR = 0x1, 3421 }; 3422 3423 struct mlx5_ifc_srqc_bits { 3424 u8 state[0x4]; 3425 u8 log_srq_size[0x4]; 3426 u8 reserved_at_8[0x18]; 3427 3428 u8 wq_signature[0x1]; 3429 u8 cont_srq[0x1]; 3430 u8 reserved_at_22[0x1]; 3431 u8 rlky[0x1]; 3432 u8 reserved_at_24[0x1]; 3433 u8 log_rq_stride[0x3]; 3434 u8 xrcd[0x18]; 3435 3436 u8 page_offset[0x6]; 3437 u8 reserved_at_46[0x2]; 3438 u8 cqn[0x18]; 3439 3440 u8 reserved_at_60[0x20]; 3441 3442 u8 reserved_at_80[0x2]; 3443 u8 log_page_size[0x6]; 3444 u8 reserved_at_88[0x18]; 3445 3446 u8 reserved_at_a0[0x20]; 3447 3448 u8 reserved_at_c0[0x8]; 3449 u8 pd[0x18]; 3450 3451 u8 lwm[0x10]; 3452 u8 wqe_cnt[0x10]; 3453 3454 u8 reserved_at_100[0x40]; 3455 3456 u8 dbr_addr[0x40]; 3457 3458 u8 reserved_at_180[0x80]; 3459 }; 3460 3461 enum { 3462 MLX5_SQC_STATE_RST = 0x0, 3463 MLX5_SQC_STATE_RDY = 0x1, 3464 MLX5_SQC_STATE_ERR = 0x3, 3465 }; 3466 3467 struct mlx5_ifc_sqc_bits { 3468 u8 rlky[0x1]; 3469 u8 cd_master[0x1]; 3470 u8 fre[0x1]; 3471 u8 flush_in_error_en[0x1]; 3472 u8 allow_multi_pkt_send_wqe[0x1]; 3473 u8 min_wqe_inline_mode[0x3]; 3474 u8 state[0x4]; 3475 u8 reg_umr[0x1]; 3476 u8 allow_swp[0x1]; 3477 u8 hairpin[0x1]; 3478 u8 reserved_at_f[0xb]; 3479 u8 ts_format[0x2]; 3480 u8 reserved_at_1c[0x4]; 3481 3482 u8 reserved_at_20[0x8]; 3483 u8 user_index[0x18]; 3484 3485 u8 reserved_at_40[0x8]; 3486 u8 cqn[0x18]; 3487 3488 u8 reserved_at_60[0x8]; 3489 u8 hairpin_peer_rq[0x18]; 3490 3491 u8 reserved_at_80[0x10]; 3492 u8 hairpin_peer_vhca[0x10]; 3493 3494 u8 reserved_at_a0[0x20]; 3495 3496 u8 reserved_at_c0[0x8]; 3497 u8 ts_cqe_to_dest_cqn[0x18]; 3498 3499 u8 reserved_at_e0[0x10]; 3500 u8 packet_pacing_rate_limit_index[0x10]; 3501 u8 tis_lst_sz[0x10]; 3502 u8 qos_queue_group_id[0x10]; 3503 3504 u8 reserved_at_120[0x40]; 3505 3506 u8 reserved_at_160[0x8]; 3507 u8 tis_num_0[0x18]; 3508 3509 struct mlx5_ifc_wq_bits wq; 3510 }; 3511 3512 enum { 3513 SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0, 3514 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1, 3515 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2, 3516 SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3, 3517 SCHEDULING_CONTEXT_ELEMENT_TYPE_QUEUE_GROUP = 0x4, 3518 }; 3519 3520 enum { 3521 ELEMENT_TYPE_CAP_MASK_TASR = 1 << 0, 3522 ELEMENT_TYPE_CAP_MASK_VPORT = 1 << 1, 3523 ELEMENT_TYPE_CAP_MASK_VPORT_TC = 1 << 2, 3524 ELEMENT_TYPE_CAP_MASK_PARA_VPORT_TC = 1 << 3, 3525 }; 3526 3527 struct mlx5_ifc_scheduling_context_bits { 3528 u8 element_type[0x8]; 3529 u8 reserved_at_8[0x18]; 3530 3531 u8 element_attributes[0x20]; 3532 3533 u8 parent_element_id[0x20]; 3534 3535 u8 reserved_at_60[0x40]; 3536 3537 u8 bw_share[0x20]; 3538 3539 u8 max_average_bw[0x20]; 3540 3541 u8 reserved_at_e0[0x120]; 3542 }; 3543 3544 struct mlx5_ifc_rqtc_bits { 3545 u8 reserved_at_0[0xa0]; 3546 3547 u8 reserved_at_a0[0x5]; 3548 u8 list_q_type[0x3]; 3549 u8 reserved_at_a8[0x8]; 3550 u8 rqt_max_size[0x10]; 3551 3552 u8 rq_vhca_id_format[0x1]; 3553 u8 reserved_at_c1[0xf]; 3554 u8 rqt_actual_size[0x10]; 3555 3556 u8 reserved_at_e0[0x6a0]; 3557 3558 struct mlx5_ifc_rq_num_bits rq_num[]; 3559 }; 3560 3561 enum { 3562 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0, 3563 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1, 3564 }; 3565 3566 enum { 3567 MLX5_RQC_STATE_RST = 0x0, 3568 MLX5_RQC_STATE_RDY = 0x1, 3569 MLX5_RQC_STATE_ERR = 0x3, 3570 }; 3571 3572 struct mlx5_ifc_rqc_bits { 3573 u8 rlky[0x1]; 3574 u8 delay_drop_en[0x1]; 3575 u8 scatter_fcs[0x1]; 3576 u8 vsd[0x1]; 3577 u8 mem_rq_type[0x4]; 3578 u8 state[0x4]; 3579 u8 reserved_at_c[0x1]; 3580 u8 flush_in_error_en[0x1]; 3581 u8 hairpin[0x1]; 3582 u8 reserved_at_f[0xb]; 3583 u8 ts_format[0x2]; 3584 u8 reserved_at_1c[0x4]; 3585 3586 u8 reserved_at_20[0x8]; 3587 u8 user_index[0x18]; 3588 3589 u8 reserved_at_40[0x8]; 3590 u8 cqn[0x18]; 3591 3592 u8 counter_set_id[0x8]; 3593 u8 reserved_at_68[0x18]; 3594 3595 u8 reserved_at_80[0x8]; 3596 u8 rmpn[0x18]; 3597 3598 u8 reserved_at_a0[0x8]; 3599 u8 hairpin_peer_sq[0x18]; 3600 3601 u8 reserved_at_c0[0x10]; 3602 u8 hairpin_peer_vhca[0x10]; 3603 3604 u8 reserved_at_e0[0xa0]; 3605 3606 struct mlx5_ifc_wq_bits wq; 3607 }; 3608 3609 enum { 3610 MLX5_RMPC_STATE_RDY = 0x1, 3611 MLX5_RMPC_STATE_ERR = 0x3, 3612 }; 3613 3614 struct mlx5_ifc_rmpc_bits { 3615 u8 reserved_at_0[0x8]; 3616 u8 state[0x4]; 3617 u8 reserved_at_c[0x14]; 3618 3619 u8 basic_cyclic_rcv_wqe[0x1]; 3620 u8 reserved_at_21[0x1f]; 3621 3622 u8 reserved_at_40[0x140]; 3623 3624 struct mlx5_ifc_wq_bits wq; 3625 }; 3626 3627 struct mlx5_ifc_nic_vport_context_bits { 3628 u8 reserved_at_0[0x5]; 3629 u8 min_wqe_inline_mode[0x3]; 3630 u8 reserved_at_8[0x15]; 3631 u8 disable_mc_local_lb[0x1]; 3632 u8 disable_uc_local_lb[0x1]; 3633 u8 roce_en[0x1]; 3634 3635 u8 arm_change_event[0x1]; 3636 u8 reserved_at_21[0x1a]; 3637 u8 event_on_mtu[0x1]; 3638 u8 event_on_promisc_change[0x1]; 3639 u8 event_on_vlan_change[0x1]; 3640 u8 event_on_mc_address_change[0x1]; 3641 u8 event_on_uc_address_change[0x1]; 3642 3643 u8 reserved_at_40[0xc]; 3644 3645 u8 affiliation_criteria[0x4]; 3646 u8 affiliated_vhca_id[0x10]; 3647 3648 u8 reserved_at_60[0xd0]; 3649 3650 u8 mtu[0x10]; 3651 3652 u8 system_image_guid[0x40]; 3653 u8 port_guid[0x40]; 3654 u8 node_guid[0x40]; 3655 3656 u8 reserved_at_200[0x140]; 3657 u8 qkey_violation_counter[0x10]; 3658 u8 reserved_at_350[0x430]; 3659 3660 u8 promisc_uc[0x1]; 3661 u8 promisc_mc[0x1]; 3662 u8 promisc_all[0x1]; 3663 u8 reserved_at_783[0x2]; 3664 u8 allowed_list_type[0x3]; 3665 u8 reserved_at_788[0xc]; 3666 u8 allowed_list_size[0xc]; 3667 3668 struct mlx5_ifc_mac_address_layout_bits permanent_address; 3669 3670 u8 reserved_at_7e0[0x20]; 3671 3672 u8 current_uc_mac_address[][0x40]; 3673 }; 3674 3675 enum { 3676 MLX5_MKC_ACCESS_MODE_PA = 0x0, 3677 MLX5_MKC_ACCESS_MODE_MTT = 0x1, 3678 MLX5_MKC_ACCESS_MODE_KLMS = 0x2, 3679 MLX5_MKC_ACCESS_MODE_KSM = 0x3, 3680 MLX5_MKC_ACCESS_MODE_SW_ICM = 0x4, 3681 MLX5_MKC_ACCESS_MODE_MEMIC = 0x5, 3682 }; 3683 3684 struct mlx5_ifc_mkc_bits { 3685 u8 reserved_at_0[0x1]; 3686 u8 free[0x1]; 3687 u8 reserved_at_2[0x1]; 3688 u8 access_mode_4_2[0x3]; 3689 u8 reserved_at_6[0x7]; 3690 u8 relaxed_ordering_write[0x1]; 3691 u8 reserved_at_e[0x1]; 3692 u8 small_fence_on_rdma_read_response[0x1]; 3693 u8 umr_en[0x1]; 3694 u8 a[0x1]; 3695 u8 rw[0x1]; 3696 u8 rr[0x1]; 3697 u8 lw[0x1]; 3698 u8 lr[0x1]; 3699 u8 access_mode_1_0[0x2]; 3700 u8 reserved_at_18[0x8]; 3701 3702 u8 qpn[0x18]; 3703 u8 mkey_7_0[0x8]; 3704 3705 u8 reserved_at_40[0x20]; 3706 3707 u8 length64[0x1]; 3708 u8 bsf_en[0x1]; 3709 u8 sync_umr[0x1]; 3710 u8 reserved_at_63[0x2]; 3711 u8 expected_sigerr_count[0x1]; 3712 u8 reserved_at_66[0x1]; 3713 u8 en_rinval[0x1]; 3714 u8 pd[0x18]; 3715 3716 u8 start_addr[0x40]; 3717 3718 u8 len[0x40]; 3719 3720 u8 bsf_octword_size[0x20]; 3721 3722 u8 reserved_at_120[0x80]; 3723 3724 u8 translations_octword_size[0x20]; 3725 3726 u8 reserved_at_1c0[0x19]; 3727 u8 relaxed_ordering_read[0x1]; 3728 u8 reserved_at_1d9[0x1]; 3729 u8 log_page_size[0x5]; 3730 3731 u8 reserved_at_1e0[0x20]; 3732 }; 3733 3734 struct mlx5_ifc_pkey_bits { 3735 u8 reserved_at_0[0x10]; 3736 u8 pkey[0x10]; 3737 }; 3738 3739 struct mlx5_ifc_array128_auto_bits { 3740 u8 array128_auto[16][0x8]; 3741 }; 3742 3743 struct mlx5_ifc_hca_vport_context_bits { 3744 u8 field_select[0x20]; 3745 3746 u8 reserved_at_20[0xe0]; 3747 3748 u8 sm_virt_aware[0x1]; 3749 u8 has_smi[0x1]; 3750 u8 has_raw[0x1]; 3751 u8 grh_required[0x1]; 3752 u8 reserved_at_104[0xc]; 3753 u8 port_physical_state[0x4]; 3754 u8 vport_state_policy[0x4]; 3755 u8 port_state[0x4]; 3756 u8 vport_state[0x4]; 3757 3758 u8 reserved_at_120[0x20]; 3759 3760 u8 system_image_guid[0x40]; 3761 3762 u8 port_guid[0x40]; 3763 3764 u8 node_guid[0x40]; 3765 3766 u8 cap_mask1[0x20]; 3767 3768 u8 cap_mask1_field_select[0x20]; 3769 3770 u8 cap_mask2[0x20]; 3771 3772 u8 cap_mask2_field_select[0x20]; 3773 3774 u8 reserved_at_280[0x80]; 3775 3776 u8 lid[0x10]; 3777 u8 reserved_at_310[0x4]; 3778 u8 init_type_reply[0x4]; 3779 u8 lmc[0x3]; 3780 u8 subnet_timeout[0x5]; 3781 3782 u8 sm_lid[0x10]; 3783 u8 sm_sl[0x4]; 3784 u8 reserved_at_334[0xc]; 3785 3786 u8 qkey_violation_counter[0x10]; 3787 u8 pkey_violation_counter[0x10]; 3788 3789 u8 reserved_at_360[0xca0]; 3790 }; 3791 3792 struct mlx5_ifc_esw_vport_context_bits { 3793 u8 fdb_to_vport_reg_c[0x1]; 3794 u8 reserved_at_1[0x2]; 3795 u8 vport_svlan_strip[0x1]; 3796 u8 vport_cvlan_strip[0x1]; 3797 u8 vport_svlan_insert[0x1]; 3798 u8 vport_cvlan_insert[0x2]; 3799 u8 fdb_to_vport_reg_c_id[0x8]; 3800 u8 reserved_at_10[0x10]; 3801 3802 u8 reserved_at_20[0x20]; 3803 3804 u8 svlan_cfi[0x1]; 3805 u8 svlan_pcp[0x3]; 3806 u8 svlan_id[0xc]; 3807 u8 cvlan_cfi[0x1]; 3808 u8 cvlan_pcp[0x3]; 3809 u8 cvlan_id[0xc]; 3810 3811 u8 reserved_at_60[0x720]; 3812 3813 u8 sw_steering_vport_icm_address_rx[0x40]; 3814 3815 u8 sw_steering_vport_icm_address_tx[0x40]; 3816 }; 3817 3818 enum { 3819 MLX5_EQC_STATUS_OK = 0x0, 3820 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa, 3821 }; 3822 3823 enum { 3824 MLX5_EQC_ST_ARMED = 0x9, 3825 MLX5_EQC_ST_FIRED = 0xa, 3826 }; 3827 3828 struct mlx5_ifc_eqc_bits { 3829 u8 status[0x4]; 3830 u8 reserved_at_4[0x9]; 3831 u8 ec[0x1]; 3832 u8 oi[0x1]; 3833 u8 reserved_at_f[0x5]; 3834 u8 st[0x4]; 3835 u8 reserved_at_18[0x8]; 3836 3837 u8 reserved_at_20[0x20]; 3838 3839 u8 reserved_at_40[0x14]; 3840 u8 page_offset[0x6]; 3841 u8 reserved_at_5a[0x6]; 3842 3843 u8 reserved_at_60[0x3]; 3844 u8 log_eq_size[0x5]; 3845 u8 uar_page[0x18]; 3846 3847 u8 reserved_at_80[0x20]; 3848 3849 u8 reserved_at_a0[0x14]; 3850 u8 intr[0xc]; 3851 3852 u8 reserved_at_c0[0x3]; 3853 u8 log_page_size[0x5]; 3854 u8 reserved_at_c8[0x18]; 3855 3856 u8 reserved_at_e0[0x60]; 3857 3858 u8 reserved_at_140[0x8]; 3859 u8 consumer_counter[0x18]; 3860 3861 u8 reserved_at_160[0x8]; 3862 u8 producer_counter[0x18]; 3863 3864 u8 reserved_at_180[0x80]; 3865 }; 3866 3867 enum { 3868 MLX5_DCTC_STATE_ACTIVE = 0x0, 3869 MLX5_DCTC_STATE_DRAINING = 0x1, 3870 MLX5_DCTC_STATE_DRAINED = 0x2, 3871 }; 3872 3873 enum { 3874 MLX5_DCTC_CS_RES_DISABLE = 0x0, 3875 MLX5_DCTC_CS_RES_NA = 0x1, 3876 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2, 3877 }; 3878 3879 enum { 3880 MLX5_DCTC_MTU_256_BYTES = 0x1, 3881 MLX5_DCTC_MTU_512_BYTES = 0x2, 3882 MLX5_DCTC_MTU_1K_BYTES = 0x3, 3883 MLX5_DCTC_MTU_2K_BYTES = 0x4, 3884 MLX5_DCTC_MTU_4K_BYTES = 0x5, 3885 }; 3886 3887 struct mlx5_ifc_dctc_bits { 3888 u8 reserved_at_0[0x4]; 3889 u8 state[0x4]; 3890 u8 reserved_at_8[0x18]; 3891 3892 u8 reserved_at_20[0x8]; 3893 u8 user_index[0x18]; 3894 3895 u8 reserved_at_40[0x8]; 3896 u8 cqn[0x18]; 3897 3898 u8 counter_set_id[0x8]; 3899 u8 atomic_mode[0x4]; 3900 u8 rre[0x1]; 3901 u8 rwe[0x1]; 3902 u8 rae[0x1]; 3903 u8 atomic_like_write_en[0x1]; 3904 u8 latency_sensitive[0x1]; 3905 u8 rlky[0x1]; 3906 u8 free_ar[0x1]; 3907 u8 reserved_at_73[0xd]; 3908 3909 u8 reserved_at_80[0x8]; 3910 u8 cs_res[0x8]; 3911 u8 reserved_at_90[0x3]; 3912 u8 min_rnr_nak[0x5]; 3913 u8 reserved_at_98[0x8]; 3914 3915 u8 reserved_at_a0[0x8]; 3916 u8 srqn_xrqn[0x18]; 3917 3918 u8 reserved_at_c0[0x8]; 3919 u8 pd[0x18]; 3920 3921 u8 tclass[0x8]; 3922 u8 reserved_at_e8[0x4]; 3923 u8 flow_label[0x14]; 3924 3925 u8 dc_access_key[0x40]; 3926 3927 u8 reserved_at_140[0x5]; 3928 u8 mtu[0x3]; 3929 u8 port[0x8]; 3930 u8 pkey_index[0x10]; 3931 3932 u8 reserved_at_160[0x8]; 3933 u8 my_addr_index[0x8]; 3934 u8 reserved_at_170[0x8]; 3935 u8 hop_limit[0x8]; 3936 3937 u8 dc_access_key_violation_count[0x20]; 3938 3939 u8 reserved_at_1a0[0x14]; 3940 u8 dei_cfi[0x1]; 3941 u8 eth_prio[0x3]; 3942 u8 ecn[0x2]; 3943 u8 dscp[0x6]; 3944 3945 u8 reserved_at_1c0[0x20]; 3946 u8 ece[0x20]; 3947 }; 3948 3949 enum { 3950 MLX5_CQC_STATUS_OK = 0x0, 3951 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9, 3952 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa, 3953 }; 3954 3955 enum { 3956 MLX5_CQC_CQE_SZ_64_BYTES = 0x0, 3957 MLX5_CQC_CQE_SZ_128_BYTES = 0x1, 3958 }; 3959 3960 enum { 3961 MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED = 0x6, 3962 MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED = 0x9, 3963 MLX5_CQC_ST_FIRED = 0xa, 3964 }; 3965 3966 enum { 3967 MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0, 3968 MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1, 3969 MLX5_CQ_PERIOD_NUM_MODES 3970 }; 3971 3972 struct mlx5_ifc_cqc_bits { 3973 u8 status[0x4]; 3974 u8 reserved_at_4[0x2]; 3975 u8 dbr_umem_valid[0x1]; 3976 u8 apu_cq[0x1]; 3977 u8 cqe_sz[0x3]; 3978 u8 cc[0x1]; 3979 u8 reserved_at_c[0x1]; 3980 u8 scqe_break_moderation_en[0x1]; 3981 u8 oi[0x1]; 3982 u8 cq_period_mode[0x2]; 3983 u8 cqe_comp_en[0x1]; 3984 u8 mini_cqe_res_format[0x2]; 3985 u8 st[0x4]; 3986 u8 reserved_at_18[0x8]; 3987 3988 u8 reserved_at_20[0x20]; 3989 3990 u8 reserved_at_40[0x14]; 3991 u8 page_offset[0x6]; 3992 u8 reserved_at_5a[0x6]; 3993 3994 u8 reserved_at_60[0x3]; 3995 u8 log_cq_size[0x5]; 3996 u8 uar_page[0x18]; 3997 3998 u8 reserved_at_80[0x4]; 3999 u8 cq_period[0xc]; 4000 u8 cq_max_count[0x10]; 4001 4002 u8 c_eqn_or_apu_element[0x20]; 4003 4004 u8 reserved_at_c0[0x3]; 4005 u8 log_page_size[0x5]; 4006 u8 reserved_at_c8[0x18]; 4007 4008 u8 reserved_at_e0[0x20]; 4009 4010 u8 reserved_at_100[0x8]; 4011 u8 last_notified_index[0x18]; 4012 4013 u8 reserved_at_120[0x8]; 4014 u8 last_solicit_index[0x18]; 4015 4016 u8 reserved_at_140[0x8]; 4017 u8 consumer_counter[0x18]; 4018 4019 u8 reserved_at_160[0x8]; 4020 u8 producer_counter[0x18]; 4021 4022 u8 reserved_at_180[0x40]; 4023 4024 u8 dbr_addr[0x40]; 4025 }; 4026 4027 union mlx5_ifc_cong_control_roce_ecn_auto_bits { 4028 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp; 4029 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp; 4030 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np; 4031 u8 reserved_at_0[0x800]; 4032 }; 4033 4034 struct mlx5_ifc_query_adapter_param_block_bits { 4035 u8 reserved_at_0[0xc0]; 4036 4037 u8 reserved_at_c0[0x8]; 4038 u8 ieee_vendor_id[0x18]; 4039 4040 u8 reserved_at_e0[0x10]; 4041 u8 vsd_vendor_id[0x10]; 4042 4043 u8 vsd[208][0x8]; 4044 4045 u8 vsd_contd_psid[16][0x8]; 4046 }; 4047 4048 enum { 4049 MLX5_XRQC_STATE_GOOD = 0x0, 4050 MLX5_XRQC_STATE_ERROR = 0x1, 4051 }; 4052 4053 enum { 4054 MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0, 4055 MLX5_XRQC_TOPOLOGY_TAG_MATCHING = 0x1, 4056 }; 4057 4058 enum { 4059 MLX5_XRQC_OFFLOAD_RNDV = 0x1, 4060 }; 4061 4062 struct mlx5_ifc_tag_matching_topology_context_bits { 4063 u8 log_matching_list_sz[0x4]; 4064 u8 reserved_at_4[0xc]; 4065 u8 append_next_index[0x10]; 4066 4067 u8 sw_phase_cnt[0x10]; 4068 u8 hw_phase_cnt[0x10]; 4069 4070 u8 reserved_at_40[0x40]; 4071 }; 4072 4073 struct mlx5_ifc_xrqc_bits { 4074 u8 state[0x4]; 4075 u8 rlkey[0x1]; 4076 u8 reserved_at_5[0xf]; 4077 u8 topology[0x4]; 4078 u8 reserved_at_18[0x4]; 4079 u8 offload[0x4]; 4080 4081 u8 reserved_at_20[0x8]; 4082 u8 user_index[0x18]; 4083 4084 u8 reserved_at_40[0x8]; 4085 u8 cqn[0x18]; 4086 4087 u8 reserved_at_60[0xa0]; 4088 4089 struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context; 4090 4091 u8 reserved_at_180[0x280]; 4092 4093 struct mlx5_ifc_wq_bits wq; 4094 }; 4095 4096 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits { 4097 struct mlx5_ifc_modify_field_select_bits modify_field_select; 4098 struct mlx5_ifc_resize_field_select_bits resize_field_select; 4099 u8 reserved_at_0[0x20]; 4100 }; 4101 4102 union mlx5_ifc_field_select_802_1_r_roce_auto_bits { 4103 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp; 4104 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp; 4105 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np; 4106 u8 reserved_at_0[0x20]; 4107 }; 4108 4109 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits { 4110 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 4111 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 4112 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 4113 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 4114 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 4115 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 4116 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout; 4117 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout; 4118 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 4119 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 4120 struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs; 4121 u8 reserved_at_0[0x7c0]; 4122 }; 4123 4124 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits { 4125 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout; 4126 u8 reserved_at_0[0x7c0]; 4127 }; 4128 4129 union mlx5_ifc_event_auto_bits { 4130 struct mlx5_ifc_comp_event_bits comp_event; 4131 struct mlx5_ifc_dct_events_bits dct_events; 4132 struct mlx5_ifc_qp_events_bits qp_events; 4133 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event; 4134 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event; 4135 struct mlx5_ifc_cq_error_bits cq_error; 4136 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged; 4137 struct mlx5_ifc_port_state_change_event_bits port_state_change_event; 4138 struct mlx5_ifc_gpio_event_bits gpio_event; 4139 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event; 4140 struct mlx5_ifc_stall_vl_event_bits stall_vl_event; 4141 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event; 4142 u8 reserved_at_0[0xe0]; 4143 }; 4144 4145 struct mlx5_ifc_health_buffer_bits { 4146 u8 reserved_at_0[0x100]; 4147 4148 u8 assert_existptr[0x20]; 4149 4150 u8 assert_callra[0x20]; 4151 4152 u8 reserved_at_140[0x40]; 4153 4154 u8 fw_version[0x20]; 4155 4156 u8 hw_id[0x20]; 4157 4158 u8 reserved_at_1c0[0x20]; 4159 4160 u8 irisc_index[0x8]; 4161 u8 synd[0x8]; 4162 u8 ext_synd[0x10]; 4163 }; 4164 4165 struct mlx5_ifc_register_loopback_control_bits { 4166 u8 no_lb[0x1]; 4167 u8 reserved_at_1[0x7]; 4168 u8 port[0x8]; 4169 u8 reserved_at_10[0x10]; 4170 4171 u8 reserved_at_20[0x60]; 4172 }; 4173 4174 struct mlx5_ifc_vport_tc_element_bits { 4175 u8 traffic_class[0x4]; 4176 u8 reserved_at_4[0xc]; 4177 u8 vport_number[0x10]; 4178 }; 4179 4180 struct mlx5_ifc_vport_element_bits { 4181 u8 reserved_at_0[0x10]; 4182 u8 vport_number[0x10]; 4183 }; 4184 4185 enum { 4186 TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0, 4187 TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1, 4188 TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2, 4189 }; 4190 4191 struct mlx5_ifc_tsar_element_bits { 4192 u8 reserved_at_0[0x8]; 4193 u8 tsar_type[0x8]; 4194 u8 reserved_at_10[0x10]; 4195 }; 4196 4197 enum { 4198 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0, 4199 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1, 4200 }; 4201 4202 struct mlx5_ifc_teardown_hca_out_bits { 4203 u8 status[0x8]; 4204 u8 reserved_at_8[0x18]; 4205 4206 u8 syndrome[0x20]; 4207 4208 u8 reserved_at_40[0x3f]; 4209 4210 u8 state[0x1]; 4211 }; 4212 4213 enum { 4214 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0, 4215 MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE = 0x1, 4216 MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN = 0x2, 4217 }; 4218 4219 struct mlx5_ifc_teardown_hca_in_bits { 4220 u8 opcode[0x10]; 4221 u8 reserved_at_10[0x10]; 4222 4223 u8 reserved_at_20[0x10]; 4224 u8 op_mod[0x10]; 4225 4226 u8 reserved_at_40[0x10]; 4227 u8 profile[0x10]; 4228 4229 u8 reserved_at_60[0x20]; 4230 }; 4231 4232 struct mlx5_ifc_sqerr2rts_qp_out_bits { 4233 u8 status[0x8]; 4234 u8 reserved_at_8[0x18]; 4235 4236 u8 syndrome[0x20]; 4237 4238 u8 reserved_at_40[0x40]; 4239 }; 4240 4241 struct mlx5_ifc_sqerr2rts_qp_in_bits { 4242 u8 opcode[0x10]; 4243 u8 uid[0x10]; 4244 4245 u8 reserved_at_20[0x10]; 4246 u8 op_mod[0x10]; 4247 4248 u8 reserved_at_40[0x8]; 4249 u8 qpn[0x18]; 4250 4251 u8 reserved_at_60[0x20]; 4252 4253 u8 opt_param_mask[0x20]; 4254 4255 u8 reserved_at_a0[0x20]; 4256 4257 struct mlx5_ifc_qpc_bits qpc; 4258 4259 u8 reserved_at_800[0x80]; 4260 }; 4261 4262 struct mlx5_ifc_sqd2rts_qp_out_bits { 4263 u8 status[0x8]; 4264 u8 reserved_at_8[0x18]; 4265 4266 u8 syndrome[0x20]; 4267 4268 u8 reserved_at_40[0x40]; 4269 }; 4270 4271 struct mlx5_ifc_sqd2rts_qp_in_bits { 4272 u8 opcode[0x10]; 4273 u8 uid[0x10]; 4274 4275 u8 reserved_at_20[0x10]; 4276 u8 op_mod[0x10]; 4277 4278 u8 reserved_at_40[0x8]; 4279 u8 qpn[0x18]; 4280 4281 u8 reserved_at_60[0x20]; 4282 4283 u8 opt_param_mask[0x20]; 4284 4285 u8 reserved_at_a0[0x20]; 4286 4287 struct mlx5_ifc_qpc_bits qpc; 4288 4289 u8 reserved_at_800[0x80]; 4290 }; 4291 4292 struct mlx5_ifc_set_roce_address_out_bits { 4293 u8 status[0x8]; 4294 u8 reserved_at_8[0x18]; 4295 4296 u8 syndrome[0x20]; 4297 4298 u8 reserved_at_40[0x40]; 4299 }; 4300 4301 struct mlx5_ifc_set_roce_address_in_bits { 4302 u8 opcode[0x10]; 4303 u8 reserved_at_10[0x10]; 4304 4305 u8 reserved_at_20[0x10]; 4306 u8 op_mod[0x10]; 4307 4308 u8 roce_address_index[0x10]; 4309 u8 reserved_at_50[0xc]; 4310 u8 vhca_port_num[0x4]; 4311 4312 u8 reserved_at_60[0x20]; 4313 4314 struct mlx5_ifc_roce_addr_layout_bits roce_address; 4315 }; 4316 4317 struct mlx5_ifc_set_mad_demux_out_bits { 4318 u8 status[0x8]; 4319 u8 reserved_at_8[0x18]; 4320 4321 u8 syndrome[0x20]; 4322 4323 u8 reserved_at_40[0x40]; 4324 }; 4325 4326 enum { 4327 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0, 4328 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2, 4329 }; 4330 4331 struct mlx5_ifc_set_mad_demux_in_bits { 4332 u8 opcode[0x10]; 4333 u8 reserved_at_10[0x10]; 4334 4335 u8 reserved_at_20[0x10]; 4336 u8 op_mod[0x10]; 4337 4338 u8 reserved_at_40[0x20]; 4339 4340 u8 reserved_at_60[0x6]; 4341 u8 demux_mode[0x2]; 4342 u8 reserved_at_68[0x18]; 4343 }; 4344 4345 struct mlx5_ifc_set_l2_table_entry_out_bits { 4346 u8 status[0x8]; 4347 u8 reserved_at_8[0x18]; 4348 4349 u8 syndrome[0x20]; 4350 4351 u8 reserved_at_40[0x40]; 4352 }; 4353 4354 struct mlx5_ifc_set_l2_table_entry_in_bits { 4355 u8 opcode[0x10]; 4356 u8 reserved_at_10[0x10]; 4357 4358 u8 reserved_at_20[0x10]; 4359 u8 op_mod[0x10]; 4360 4361 u8 reserved_at_40[0x60]; 4362 4363 u8 reserved_at_a0[0x8]; 4364 u8 table_index[0x18]; 4365 4366 u8 reserved_at_c0[0x20]; 4367 4368 u8 reserved_at_e0[0x13]; 4369 u8 vlan_valid[0x1]; 4370 u8 vlan[0xc]; 4371 4372 struct mlx5_ifc_mac_address_layout_bits mac_address; 4373 4374 u8 reserved_at_140[0xc0]; 4375 }; 4376 4377 struct mlx5_ifc_set_issi_out_bits { 4378 u8 status[0x8]; 4379 u8 reserved_at_8[0x18]; 4380 4381 u8 syndrome[0x20]; 4382 4383 u8 reserved_at_40[0x40]; 4384 }; 4385 4386 struct mlx5_ifc_set_issi_in_bits { 4387 u8 opcode[0x10]; 4388 u8 reserved_at_10[0x10]; 4389 4390 u8 reserved_at_20[0x10]; 4391 u8 op_mod[0x10]; 4392 4393 u8 reserved_at_40[0x10]; 4394 u8 current_issi[0x10]; 4395 4396 u8 reserved_at_60[0x20]; 4397 }; 4398 4399 struct mlx5_ifc_set_hca_cap_out_bits { 4400 u8 status[0x8]; 4401 u8 reserved_at_8[0x18]; 4402 4403 u8 syndrome[0x20]; 4404 4405 u8 reserved_at_40[0x40]; 4406 }; 4407 4408 struct mlx5_ifc_set_hca_cap_in_bits { 4409 u8 opcode[0x10]; 4410 u8 reserved_at_10[0x10]; 4411 4412 u8 reserved_at_20[0x10]; 4413 u8 op_mod[0x10]; 4414 4415 u8 other_function[0x1]; 4416 u8 reserved_at_41[0xf]; 4417 u8 function_id[0x10]; 4418 4419 u8 reserved_at_60[0x20]; 4420 4421 union mlx5_ifc_hca_cap_union_bits capability; 4422 }; 4423 4424 enum { 4425 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0, 4426 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1, 4427 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2, 4428 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3, 4429 MLX5_SET_FTE_MODIFY_ENABLE_MASK_IPSEC_OBJ_ID = 0x4 4430 }; 4431 4432 struct mlx5_ifc_set_fte_out_bits { 4433 u8 status[0x8]; 4434 u8 reserved_at_8[0x18]; 4435 4436 u8 syndrome[0x20]; 4437 4438 u8 reserved_at_40[0x40]; 4439 }; 4440 4441 struct mlx5_ifc_set_fte_in_bits { 4442 u8 opcode[0x10]; 4443 u8 reserved_at_10[0x10]; 4444 4445 u8 reserved_at_20[0x10]; 4446 u8 op_mod[0x10]; 4447 4448 u8 other_vport[0x1]; 4449 u8 reserved_at_41[0xf]; 4450 u8 vport_number[0x10]; 4451 4452 u8 reserved_at_60[0x20]; 4453 4454 u8 table_type[0x8]; 4455 u8 reserved_at_88[0x18]; 4456 4457 u8 reserved_at_a0[0x8]; 4458 u8 table_id[0x18]; 4459 4460 u8 ignore_flow_level[0x1]; 4461 u8 reserved_at_c1[0x17]; 4462 u8 modify_enable_mask[0x8]; 4463 4464 u8 reserved_at_e0[0x20]; 4465 4466 u8 flow_index[0x20]; 4467 4468 u8 reserved_at_120[0xe0]; 4469 4470 struct mlx5_ifc_flow_context_bits flow_context; 4471 }; 4472 4473 struct mlx5_ifc_rts2rts_qp_out_bits { 4474 u8 status[0x8]; 4475 u8 reserved_at_8[0x18]; 4476 4477 u8 syndrome[0x20]; 4478 4479 u8 reserved_at_40[0x20]; 4480 u8 ece[0x20]; 4481 }; 4482 4483 struct mlx5_ifc_rts2rts_qp_in_bits { 4484 u8 opcode[0x10]; 4485 u8 uid[0x10]; 4486 4487 u8 reserved_at_20[0x10]; 4488 u8 op_mod[0x10]; 4489 4490 u8 reserved_at_40[0x8]; 4491 u8 qpn[0x18]; 4492 4493 u8 reserved_at_60[0x20]; 4494 4495 u8 opt_param_mask[0x20]; 4496 4497 u8 ece[0x20]; 4498 4499 struct mlx5_ifc_qpc_bits qpc; 4500 4501 u8 reserved_at_800[0x80]; 4502 }; 4503 4504 struct mlx5_ifc_rtr2rts_qp_out_bits { 4505 u8 status[0x8]; 4506 u8 reserved_at_8[0x18]; 4507 4508 u8 syndrome[0x20]; 4509 4510 u8 reserved_at_40[0x20]; 4511 u8 ece[0x20]; 4512 }; 4513 4514 struct mlx5_ifc_rtr2rts_qp_in_bits { 4515 u8 opcode[0x10]; 4516 u8 uid[0x10]; 4517 4518 u8 reserved_at_20[0x10]; 4519 u8 op_mod[0x10]; 4520 4521 u8 reserved_at_40[0x8]; 4522 u8 qpn[0x18]; 4523 4524 u8 reserved_at_60[0x20]; 4525 4526 u8 opt_param_mask[0x20]; 4527 4528 u8 ece[0x20]; 4529 4530 struct mlx5_ifc_qpc_bits qpc; 4531 4532 u8 reserved_at_800[0x80]; 4533 }; 4534 4535 struct mlx5_ifc_rst2init_qp_out_bits { 4536 u8 status[0x8]; 4537 u8 reserved_at_8[0x18]; 4538 4539 u8 syndrome[0x20]; 4540 4541 u8 reserved_at_40[0x20]; 4542 u8 ece[0x20]; 4543 }; 4544 4545 struct mlx5_ifc_rst2init_qp_in_bits { 4546 u8 opcode[0x10]; 4547 u8 uid[0x10]; 4548 4549 u8 reserved_at_20[0x10]; 4550 u8 op_mod[0x10]; 4551 4552 u8 reserved_at_40[0x8]; 4553 u8 qpn[0x18]; 4554 4555 u8 reserved_at_60[0x20]; 4556 4557 u8 opt_param_mask[0x20]; 4558 4559 u8 ece[0x20]; 4560 4561 struct mlx5_ifc_qpc_bits qpc; 4562 4563 u8 reserved_at_800[0x80]; 4564 }; 4565 4566 struct mlx5_ifc_query_xrq_out_bits { 4567 u8 status[0x8]; 4568 u8 reserved_at_8[0x18]; 4569 4570 u8 syndrome[0x20]; 4571 4572 u8 reserved_at_40[0x40]; 4573 4574 struct mlx5_ifc_xrqc_bits xrq_context; 4575 }; 4576 4577 struct mlx5_ifc_query_xrq_in_bits { 4578 u8 opcode[0x10]; 4579 u8 reserved_at_10[0x10]; 4580 4581 u8 reserved_at_20[0x10]; 4582 u8 op_mod[0x10]; 4583 4584 u8 reserved_at_40[0x8]; 4585 u8 xrqn[0x18]; 4586 4587 u8 reserved_at_60[0x20]; 4588 }; 4589 4590 struct mlx5_ifc_query_xrc_srq_out_bits { 4591 u8 status[0x8]; 4592 u8 reserved_at_8[0x18]; 4593 4594 u8 syndrome[0x20]; 4595 4596 u8 reserved_at_40[0x40]; 4597 4598 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 4599 4600 u8 reserved_at_280[0x600]; 4601 4602 u8 pas[][0x40]; 4603 }; 4604 4605 struct mlx5_ifc_query_xrc_srq_in_bits { 4606 u8 opcode[0x10]; 4607 u8 reserved_at_10[0x10]; 4608 4609 u8 reserved_at_20[0x10]; 4610 u8 op_mod[0x10]; 4611 4612 u8 reserved_at_40[0x8]; 4613 u8 xrc_srqn[0x18]; 4614 4615 u8 reserved_at_60[0x20]; 4616 }; 4617 4618 enum { 4619 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0, 4620 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1, 4621 }; 4622 4623 struct mlx5_ifc_query_vport_state_out_bits { 4624 u8 status[0x8]; 4625 u8 reserved_at_8[0x18]; 4626 4627 u8 syndrome[0x20]; 4628 4629 u8 reserved_at_40[0x20]; 4630 4631 u8 reserved_at_60[0x18]; 4632 u8 admin_state[0x4]; 4633 u8 state[0x4]; 4634 }; 4635 4636 enum { 4637 MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT = 0x0, 4638 MLX5_VPORT_STATE_OP_MOD_ESW_VPORT = 0x1, 4639 MLX5_VPORT_STATE_OP_MOD_UPLINK = 0x2, 4640 }; 4641 4642 struct mlx5_ifc_arm_monitor_counter_in_bits { 4643 u8 opcode[0x10]; 4644 u8 uid[0x10]; 4645 4646 u8 reserved_at_20[0x10]; 4647 u8 op_mod[0x10]; 4648 4649 u8 reserved_at_40[0x20]; 4650 4651 u8 reserved_at_60[0x20]; 4652 }; 4653 4654 struct mlx5_ifc_arm_monitor_counter_out_bits { 4655 u8 status[0x8]; 4656 u8 reserved_at_8[0x18]; 4657 4658 u8 syndrome[0x20]; 4659 4660 u8 reserved_at_40[0x40]; 4661 }; 4662 4663 enum { 4664 MLX5_QUERY_MONITOR_CNT_TYPE_PPCNT = 0x0, 4665 MLX5_QUERY_MONITOR_CNT_TYPE_Q_COUNTER = 0x1, 4666 }; 4667 4668 enum mlx5_monitor_counter_ppcnt { 4669 MLX5_QUERY_MONITOR_PPCNT_IN_RANGE_LENGTH_ERRORS = 0x0, 4670 MLX5_QUERY_MONITOR_PPCNT_OUT_OF_RANGE_LENGTH_FIELD = 0x1, 4671 MLX5_QUERY_MONITOR_PPCNT_FRAME_TOO_LONG_ERRORS = 0x2, 4672 MLX5_QUERY_MONITOR_PPCNT_FRAME_CHECK_SEQUENCE_ERRORS = 0x3, 4673 MLX5_QUERY_MONITOR_PPCNT_ALIGNMENT_ERRORS = 0x4, 4674 MLX5_QUERY_MONITOR_PPCNT_IF_OUT_DISCARDS = 0x5, 4675 }; 4676 4677 enum { 4678 MLX5_QUERY_MONITOR_Q_COUNTER_RX_OUT_OF_BUFFER = 0x4, 4679 }; 4680 4681 struct mlx5_ifc_monitor_counter_output_bits { 4682 u8 reserved_at_0[0x4]; 4683 u8 type[0x4]; 4684 u8 reserved_at_8[0x8]; 4685 u8 counter[0x10]; 4686 4687 u8 counter_group_id[0x20]; 4688 }; 4689 4690 #define MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 (6) 4691 #define MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1 (1) 4692 #define MLX5_CMD_SET_MONITOR_NUM_COUNTER (MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 +\ 4693 MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1) 4694 4695 struct mlx5_ifc_set_monitor_counter_in_bits { 4696 u8 opcode[0x10]; 4697 u8 uid[0x10]; 4698 4699 u8 reserved_at_20[0x10]; 4700 u8 op_mod[0x10]; 4701 4702 u8 reserved_at_40[0x10]; 4703 u8 num_of_counters[0x10]; 4704 4705 u8 reserved_at_60[0x20]; 4706 4707 struct mlx5_ifc_monitor_counter_output_bits monitor_counter[MLX5_CMD_SET_MONITOR_NUM_COUNTER]; 4708 }; 4709 4710 struct mlx5_ifc_set_monitor_counter_out_bits { 4711 u8 status[0x8]; 4712 u8 reserved_at_8[0x18]; 4713 4714 u8 syndrome[0x20]; 4715 4716 u8 reserved_at_40[0x40]; 4717 }; 4718 4719 struct mlx5_ifc_query_vport_state_in_bits { 4720 u8 opcode[0x10]; 4721 u8 reserved_at_10[0x10]; 4722 4723 u8 reserved_at_20[0x10]; 4724 u8 op_mod[0x10]; 4725 4726 u8 other_vport[0x1]; 4727 u8 reserved_at_41[0xf]; 4728 u8 vport_number[0x10]; 4729 4730 u8 reserved_at_60[0x20]; 4731 }; 4732 4733 struct mlx5_ifc_query_vnic_env_out_bits { 4734 u8 status[0x8]; 4735 u8 reserved_at_8[0x18]; 4736 4737 u8 syndrome[0x20]; 4738 4739 u8 reserved_at_40[0x40]; 4740 4741 struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env; 4742 }; 4743 4744 enum { 4745 MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS = 0x0, 4746 }; 4747 4748 struct mlx5_ifc_query_vnic_env_in_bits { 4749 u8 opcode[0x10]; 4750 u8 reserved_at_10[0x10]; 4751 4752 u8 reserved_at_20[0x10]; 4753 u8 op_mod[0x10]; 4754 4755 u8 other_vport[0x1]; 4756 u8 reserved_at_41[0xf]; 4757 u8 vport_number[0x10]; 4758 4759 u8 reserved_at_60[0x20]; 4760 }; 4761 4762 struct mlx5_ifc_query_vport_counter_out_bits { 4763 u8 status[0x8]; 4764 u8 reserved_at_8[0x18]; 4765 4766 u8 syndrome[0x20]; 4767 4768 u8 reserved_at_40[0x40]; 4769 4770 struct mlx5_ifc_traffic_counter_bits received_errors; 4771 4772 struct mlx5_ifc_traffic_counter_bits transmit_errors; 4773 4774 struct mlx5_ifc_traffic_counter_bits received_ib_unicast; 4775 4776 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast; 4777 4778 struct mlx5_ifc_traffic_counter_bits received_ib_multicast; 4779 4780 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast; 4781 4782 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast; 4783 4784 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast; 4785 4786 struct mlx5_ifc_traffic_counter_bits received_eth_unicast; 4787 4788 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast; 4789 4790 struct mlx5_ifc_traffic_counter_bits received_eth_multicast; 4791 4792 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast; 4793 4794 u8 reserved_at_680[0xa00]; 4795 }; 4796 4797 enum { 4798 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0, 4799 }; 4800 4801 struct mlx5_ifc_query_vport_counter_in_bits { 4802 u8 opcode[0x10]; 4803 u8 reserved_at_10[0x10]; 4804 4805 u8 reserved_at_20[0x10]; 4806 u8 op_mod[0x10]; 4807 4808 u8 other_vport[0x1]; 4809 u8 reserved_at_41[0xb]; 4810 u8 port_num[0x4]; 4811 u8 vport_number[0x10]; 4812 4813 u8 reserved_at_60[0x60]; 4814 4815 u8 clear[0x1]; 4816 u8 reserved_at_c1[0x1f]; 4817 4818 u8 reserved_at_e0[0x20]; 4819 }; 4820 4821 struct mlx5_ifc_query_tis_out_bits { 4822 u8 status[0x8]; 4823 u8 reserved_at_8[0x18]; 4824 4825 u8 syndrome[0x20]; 4826 4827 u8 reserved_at_40[0x40]; 4828 4829 struct mlx5_ifc_tisc_bits tis_context; 4830 }; 4831 4832 struct mlx5_ifc_query_tis_in_bits { 4833 u8 opcode[0x10]; 4834 u8 reserved_at_10[0x10]; 4835 4836 u8 reserved_at_20[0x10]; 4837 u8 op_mod[0x10]; 4838 4839 u8 reserved_at_40[0x8]; 4840 u8 tisn[0x18]; 4841 4842 u8 reserved_at_60[0x20]; 4843 }; 4844 4845 struct mlx5_ifc_query_tir_out_bits { 4846 u8 status[0x8]; 4847 u8 reserved_at_8[0x18]; 4848 4849 u8 syndrome[0x20]; 4850 4851 u8 reserved_at_40[0xc0]; 4852 4853 struct mlx5_ifc_tirc_bits tir_context; 4854 }; 4855 4856 struct mlx5_ifc_query_tir_in_bits { 4857 u8 opcode[0x10]; 4858 u8 reserved_at_10[0x10]; 4859 4860 u8 reserved_at_20[0x10]; 4861 u8 op_mod[0x10]; 4862 4863 u8 reserved_at_40[0x8]; 4864 u8 tirn[0x18]; 4865 4866 u8 reserved_at_60[0x20]; 4867 }; 4868 4869 struct mlx5_ifc_query_srq_out_bits { 4870 u8 status[0x8]; 4871 u8 reserved_at_8[0x18]; 4872 4873 u8 syndrome[0x20]; 4874 4875 u8 reserved_at_40[0x40]; 4876 4877 struct mlx5_ifc_srqc_bits srq_context_entry; 4878 4879 u8 reserved_at_280[0x600]; 4880 4881 u8 pas[][0x40]; 4882 }; 4883 4884 struct mlx5_ifc_query_srq_in_bits { 4885 u8 opcode[0x10]; 4886 u8 reserved_at_10[0x10]; 4887 4888 u8 reserved_at_20[0x10]; 4889 u8 op_mod[0x10]; 4890 4891 u8 reserved_at_40[0x8]; 4892 u8 srqn[0x18]; 4893 4894 u8 reserved_at_60[0x20]; 4895 }; 4896 4897 struct mlx5_ifc_query_sq_out_bits { 4898 u8 status[0x8]; 4899 u8 reserved_at_8[0x18]; 4900 4901 u8 syndrome[0x20]; 4902 4903 u8 reserved_at_40[0xc0]; 4904 4905 struct mlx5_ifc_sqc_bits sq_context; 4906 }; 4907 4908 struct mlx5_ifc_query_sq_in_bits { 4909 u8 opcode[0x10]; 4910 u8 reserved_at_10[0x10]; 4911 4912 u8 reserved_at_20[0x10]; 4913 u8 op_mod[0x10]; 4914 4915 u8 reserved_at_40[0x8]; 4916 u8 sqn[0x18]; 4917 4918 u8 reserved_at_60[0x20]; 4919 }; 4920 4921 struct mlx5_ifc_query_special_contexts_out_bits { 4922 u8 status[0x8]; 4923 u8 reserved_at_8[0x18]; 4924 4925 u8 syndrome[0x20]; 4926 4927 u8 dump_fill_mkey[0x20]; 4928 4929 u8 resd_lkey[0x20]; 4930 4931 u8 null_mkey[0x20]; 4932 4933 u8 reserved_at_a0[0x60]; 4934 }; 4935 4936 struct mlx5_ifc_query_special_contexts_in_bits { 4937 u8 opcode[0x10]; 4938 u8 reserved_at_10[0x10]; 4939 4940 u8 reserved_at_20[0x10]; 4941 u8 op_mod[0x10]; 4942 4943 u8 reserved_at_40[0x40]; 4944 }; 4945 4946 struct mlx5_ifc_query_scheduling_element_out_bits { 4947 u8 opcode[0x10]; 4948 u8 reserved_at_10[0x10]; 4949 4950 u8 reserved_at_20[0x10]; 4951 u8 op_mod[0x10]; 4952 4953 u8 reserved_at_40[0xc0]; 4954 4955 struct mlx5_ifc_scheduling_context_bits scheduling_context; 4956 4957 u8 reserved_at_300[0x100]; 4958 }; 4959 4960 enum { 4961 SCHEDULING_HIERARCHY_E_SWITCH = 0x2, 4962 SCHEDULING_HIERARCHY_NIC = 0x3, 4963 }; 4964 4965 struct mlx5_ifc_query_scheduling_element_in_bits { 4966 u8 opcode[0x10]; 4967 u8 reserved_at_10[0x10]; 4968 4969 u8 reserved_at_20[0x10]; 4970 u8 op_mod[0x10]; 4971 4972 u8 scheduling_hierarchy[0x8]; 4973 u8 reserved_at_48[0x18]; 4974 4975 u8 scheduling_element_id[0x20]; 4976 4977 u8 reserved_at_80[0x180]; 4978 }; 4979 4980 struct mlx5_ifc_query_rqt_out_bits { 4981 u8 status[0x8]; 4982 u8 reserved_at_8[0x18]; 4983 4984 u8 syndrome[0x20]; 4985 4986 u8 reserved_at_40[0xc0]; 4987 4988 struct mlx5_ifc_rqtc_bits rqt_context; 4989 }; 4990 4991 struct mlx5_ifc_query_rqt_in_bits { 4992 u8 opcode[0x10]; 4993 u8 reserved_at_10[0x10]; 4994 4995 u8 reserved_at_20[0x10]; 4996 u8 op_mod[0x10]; 4997 4998 u8 reserved_at_40[0x8]; 4999 u8 rqtn[0x18]; 5000 5001 u8 reserved_at_60[0x20]; 5002 }; 5003 5004 struct mlx5_ifc_query_rq_out_bits { 5005 u8 status[0x8]; 5006 u8 reserved_at_8[0x18]; 5007 5008 u8 syndrome[0x20]; 5009 5010 u8 reserved_at_40[0xc0]; 5011 5012 struct mlx5_ifc_rqc_bits rq_context; 5013 }; 5014 5015 struct mlx5_ifc_query_rq_in_bits { 5016 u8 opcode[0x10]; 5017 u8 reserved_at_10[0x10]; 5018 5019 u8 reserved_at_20[0x10]; 5020 u8 op_mod[0x10]; 5021 5022 u8 reserved_at_40[0x8]; 5023 u8 rqn[0x18]; 5024 5025 u8 reserved_at_60[0x20]; 5026 }; 5027 5028 struct mlx5_ifc_query_roce_address_out_bits { 5029 u8 status[0x8]; 5030 u8 reserved_at_8[0x18]; 5031 5032 u8 syndrome[0x20]; 5033 5034 u8 reserved_at_40[0x40]; 5035 5036 struct mlx5_ifc_roce_addr_layout_bits roce_address; 5037 }; 5038 5039 struct mlx5_ifc_query_roce_address_in_bits { 5040 u8 opcode[0x10]; 5041 u8 reserved_at_10[0x10]; 5042 5043 u8 reserved_at_20[0x10]; 5044 u8 op_mod[0x10]; 5045 5046 u8 roce_address_index[0x10]; 5047 u8 reserved_at_50[0xc]; 5048 u8 vhca_port_num[0x4]; 5049 5050 u8 reserved_at_60[0x20]; 5051 }; 5052 5053 struct mlx5_ifc_query_rmp_out_bits { 5054 u8 status[0x8]; 5055 u8 reserved_at_8[0x18]; 5056 5057 u8 syndrome[0x20]; 5058 5059 u8 reserved_at_40[0xc0]; 5060 5061 struct mlx5_ifc_rmpc_bits rmp_context; 5062 }; 5063 5064 struct mlx5_ifc_query_rmp_in_bits { 5065 u8 opcode[0x10]; 5066 u8 reserved_at_10[0x10]; 5067 5068 u8 reserved_at_20[0x10]; 5069 u8 op_mod[0x10]; 5070 5071 u8 reserved_at_40[0x8]; 5072 u8 rmpn[0x18]; 5073 5074 u8 reserved_at_60[0x20]; 5075 }; 5076 5077 struct mlx5_ifc_query_qp_out_bits { 5078 u8 status[0x8]; 5079 u8 reserved_at_8[0x18]; 5080 5081 u8 syndrome[0x20]; 5082 5083 u8 reserved_at_40[0x20]; 5084 u8 ece[0x20]; 5085 5086 u8 opt_param_mask[0x20]; 5087 5088 u8 reserved_at_a0[0x20]; 5089 5090 struct mlx5_ifc_qpc_bits qpc; 5091 5092 u8 reserved_at_800[0x80]; 5093 5094 u8 pas[][0x40]; 5095 }; 5096 5097 struct mlx5_ifc_query_qp_in_bits { 5098 u8 opcode[0x10]; 5099 u8 reserved_at_10[0x10]; 5100 5101 u8 reserved_at_20[0x10]; 5102 u8 op_mod[0x10]; 5103 5104 u8 reserved_at_40[0x8]; 5105 u8 qpn[0x18]; 5106 5107 u8 reserved_at_60[0x20]; 5108 }; 5109 5110 struct mlx5_ifc_query_q_counter_out_bits { 5111 u8 status[0x8]; 5112 u8 reserved_at_8[0x18]; 5113 5114 u8 syndrome[0x20]; 5115 5116 u8 reserved_at_40[0x40]; 5117 5118 u8 rx_write_requests[0x20]; 5119 5120 u8 reserved_at_a0[0x20]; 5121 5122 u8 rx_read_requests[0x20]; 5123 5124 u8 reserved_at_e0[0x20]; 5125 5126 u8 rx_atomic_requests[0x20]; 5127 5128 u8 reserved_at_120[0x20]; 5129 5130 u8 rx_dct_connect[0x20]; 5131 5132 u8 reserved_at_160[0x20]; 5133 5134 u8 out_of_buffer[0x20]; 5135 5136 u8 reserved_at_1a0[0x20]; 5137 5138 u8 out_of_sequence[0x20]; 5139 5140 u8 reserved_at_1e0[0x20]; 5141 5142 u8 duplicate_request[0x20]; 5143 5144 u8 reserved_at_220[0x20]; 5145 5146 u8 rnr_nak_retry_err[0x20]; 5147 5148 u8 reserved_at_260[0x20]; 5149 5150 u8 packet_seq_err[0x20]; 5151 5152 u8 reserved_at_2a0[0x20]; 5153 5154 u8 implied_nak_seq_err[0x20]; 5155 5156 u8 reserved_at_2e0[0x20]; 5157 5158 u8 local_ack_timeout_err[0x20]; 5159 5160 u8 reserved_at_320[0xa0]; 5161 5162 u8 resp_local_length_error[0x20]; 5163 5164 u8 req_local_length_error[0x20]; 5165 5166 u8 resp_local_qp_error[0x20]; 5167 5168 u8 local_operation_error[0x20]; 5169 5170 u8 resp_local_protection[0x20]; 5171 5172 u8 req_local_protection[0x20]; 5173 5174 u8 resp_cqe_error[0x20]; 5175 5176 u8 req_cqe_error[0x20]; 5177 5178 u8 req_mw_binding[0x20]; 5179 5180 u8 req_bad_response[0x20]; 5181 5182 u8 req_remote_invalid_request[0x20]; 5183 5184 u8 resp_remote_invalid_request[0x20]; 5185 5186 u8 req_remote_access_errors[0x20]; 5187 5188 u8 resp_remote_access_errors[0x20]; 5189 5190 u8 req_remote_operation_errors[0x20]; 5191 5192 u8 req_transport_retries_exceeded[0x20]; 5193 5194 u8 cq_overflow[0x20]; 5195 5196 u8 resp_cqe_flush_error[0x20]; 5197 5198 u8 req_cqe_flush_error[0x20]; 5199 5200 u8 reserved_at_620[0x20]; 5201 5202 u8 roce_adp_retrans[0x20]; 5203 5204 u8 roce_adp_retrans_to[0x20]; 5205 5206 u8 roce_slow_restart[0x20]; 5207 5208 u8 roce_slow_restart_cnps[0x20]; 5209 5210 u8 roce_slow_restart_trans[0x20]; 5211 5212 u8 reserved_at_6e0[0x120]; 5213 }; 5214 5215 struct mlx5_ifc_query_q_counter_in_bits { 5216 u8 opcode[0x10]; 5217 u8 reserved_at_10[0x10]; 5218 5219 u8 reserved_at_20[0x10]; 5220 u8 op_mod[0x10]; 5221 5222 u8 reserved_at_40[0x80]; 5223 5224 u8 clear[0x1]; 5225 u8 reserved_at_c1[0x1f]; 5226 5227 u8 reserved_at_e0[0x18]; 5228 u8 counter_set_id[0x8]; 5229 }; 5230 5231 struct mlx5_ifc_query_pages_out_bits { 5232 u8 status[0x8]; 5233 u8 reserved_at_8[0x18]; 5234 5235 u8 syndrome[0x20]; 5236 5237 u8 embedded_cpu_function[0x1]; 5238 u8 reserved_at_41[0xf]; 5239 u8 function_id[0x10]; 5240 5241 u8 num_pages[0x20]; 5242 }; 5243 5244 enum { 5245 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1, 5246 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2, 5247 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3, 5248 }; 5249 5250 struct mlx5_ifc_query_pages_in_bits { 5251 u8 opcode[0x10]; 5252 u8 reserved_at_10[0x10]; 5253 5254 u8 reserved_at_20[0x10]; 5255 u8 op_mod[0x10]; 5256 5257 u8 embedded_cpu_function[0x1]; 5258 u8 reserved_at_41[0xf]; 5259 u8 function_id[0x10]; 5260 5261 u8 reserved_at_60[0x20]; 5262 }; 5263 5264 struct mlx5_ifc_query_nic_vport_context_out_bits { 5265 u8 status[0x8]; 5266 u8 reserved_at_8[0x18]; 5267 5268 u8 syndrome[0x20]; 5269 5270 u8 reserved_at_40[0x40]; 5271 5272 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 5273 }; 5274 5275 struct mlx5_ifc_query_nic_vport_context_in_bits { 5276 u8 opcode[0x10]; 5277 u8 reserved_at_10[0x10]; 5278 5279 u8 reserved_at_20[0x10]; 5280 u8 op_mod[0x10]; 5281 5282 u8 other_vport[0x1]; 5283 u8 reserved_at_41[0xf]; 5284 u8 vport_number[0x10]; 5285 5286 u8 reserved_at_60[0x5]; 5287 u8 allowed_list_type[0x3]; 5288 u8 reserved_at_68[0x18]; 5289 }; 5290 5291 struct mlx5_ifc_query_mkey_out_bits { 5292 u8 status[0x8]; 5293 u8 reserved_at_8[0x18]; 5294 5295 u8 syndrome[0x20]; 5296 5297 u8 reserved_at_40[0x40]; 5298 5299 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 5300 5301 u8 reserved_at_280[0x600]; 5302 5303 u8 bsf0_klm0_pas_mtt0_1[16][0x8]; 5304 5305 u8 bsf1_klm1_pas_mtt2_3[16][0x8]; 5306 }; 5307 5308 struct mlx5_ifc_query_mkey_in_bits { 5309 u8 opcode[0x10]; 5310 u8 reserved_at_10[0x10]; 5311 5312 u8 reserved_at_20[0x10]; 5313 u8 op_mod[0x10]; 5314 5315 u8 reserved_at_40[0x8]; 5316 u8 mkey_index[0x18]; 5317 5318 u8 pg_access[0x1]; 5319 u8 reserved_at_61[0x1f]; 5320 }; 5321 5322 struct mlx5_ifc_query_mad_demux_out_bits { 5323 u8 status[0x8]; 5324 u8 reserved_at_8[0x18]; 5325 5326 u8 syndrome[0x20]; 5327 5328 u8 reserved_at_40[0x40]; 5329 5330 u8 mad_dumux_parameters_block[0x20]; 5331 }; 5332 5333 struct mlx5_ifc_query_mad_demux_in_bits { 5334 u8 opcode[0x10]; 5335 u8 reserved_at_10[0x10]; 5336 5337 u8 reserved_at_20[0x10]; 5338 u8 op_mod[0x10]; 5339 5340 u8 reserved_at_40[0x40]; 5341 }; 5342 5343 struct mlx5_ifc_query_l2_table_entry_out_bits { 5344 u8 status[0x8]; 5345 u8 reserved_at_8[0x18]; 5346 5347 u8 syndrome[0x20]; 5348 5349 u8 reserved_at_40[0xa0]; 5350 5351 u8 reserved_at_e0[0x13]; 5352 u8 vlan_valid[0x1]; 5353 u8 vlan[0xc]; 5354 5355 struct mlx5_ifc_mac_address_layout_bits mac_address; 5356 5357 u8 reserved_at_140[0xc0]; 5358 }; 5359 5360 struct mlx5_ifc_query_l2_table_entry_in_bits { 5361 u8 opcode[0x10]; 5362 u8 reserved_at_10[0x10]; 5363 5364 u8 reserved_at_20[0x10]; 5365 u8 op_mod[0x10]; 5366 5367 u8 reserved_at_40[0x60]; 5368 5369 u8 reserved_at_a0[0x8]; 5370 u8 table_index[0x18]; 5371 5372 u8 reserved_at_c0[0x140]; 5373 }; 5374 5375 struct mlx5_ifc_query_issi_out_bits { 5376 u8 status[0x8]; 5377 u8 reserved_at_8[0x18]; 5378 5379 u8 syndrome[0x20]; 5380 5381 u8 reserved_at_40[0x10]; 5382 u8 current_issi[0x10]; 5383 5384 u8 reserved_at_60[0xa0]; 5385 5386 u8 reserved_at_100[76][0x8]; 5387 u8 supported_issi_dw0[0x20]; 5388 }; 5389 5390 struct mlx5_ifc_query_issi_in_bits { 5391 u8 opcode[0x10]; 5392 u8 reserved_at_10[0x10]; 5393 5394 u8 reserved_at_20[0x10]; 5395 u8 op_mod[0x10]; 5396 5397 u8 reserved_at_40[0x40]; 5398 }; 5399 5400 struct mlx5_ifc_set_driver_version_out_bits { 5401 u8 status[0x8]; 5402 u8 reserved_0[0x18]; 5403 5404 u8 syndrome[0x20]; 5405 u8 reserved_1[0x40]; 5406 }; 5407 5408 struct mlx5_ifc_set_driver_version_in_bits { 5409 u8 opcode[0x10]; 5410 u8 reserved_0[0x10]; 5411 5412 u8 reserved_1[0x10]; 5413 u8 op_mod[0x10]; 5414 5415 u8 reserved_2[0x40]; 5416 u8 driver_version[64][0x8]; 5417 }; 5418 5419 struct mlx5_ifc_query_hca_vport_pkey_out_bits { 5420 u8 status[0x8]; 5421 u8 reserved_at_8[0x18]; 5422 5423 u8 syndrome[0x20]; 5424 5425 u8 reserved_at_40[0x40]; 5426 5427 struct mlx5_ifc_pkey_bits pkey[]; 5428 }; 5429 5430 struct mlx5_ifc_query_hca_vport_pkey_in_bits { 5431 u8 opcode[0x10]; 5432 u8 reserved_at_10[0x10]; 5433 5434 u8 reserved_at_20[0x10]; 5435 u8 op_mod[0x10]; 5436 5437 u8 other_vport[0x1]; 5438 u8 reserved_at_41[0xb]; 5439 u8 port_num[0x4]; 5440 u8 vport_number[0x10]; 5441 5442 u8 reserved_at_60[0x10]; 5443 u8 pkey_index[0x10]; 5444 }; 5445 5446 enum { 5447 MLX5_HCA_VPORT_SEL_PORT_GUID = 1 << 0, 5448 MLX5_HCA_VPORT_SEL_NODE_GUID = 1 << 1, 5449 MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2, 5450 }; 5451 5452 struct mlx5_ifc_query_hca_vport_gid_out_bits { 5453 u8 status[0x8]; 5454 u8 reserved_at_8[0x18]; 5455 5456 u8 syndrome[0x20]; 5457 5458 u8 reserved_at_40[0x20]; 5459 5460 u8 gids_num[0x10]; 5461 u8 reserved_at_70[0x10]; 5462 5463 struct mlx5_ifc_array128_auto_bits gid[]; 5464 }; 5465 5466 struct mlx5_ifc_query_hca_vport_gid_in_bits { 5467 u8 opcode[0x10]; 5468 u8 reserved_at_10[0x10]; 5469 5470 u8 reserved_at_20[0x10]; 5471 u8 op_mod[0x10]; 5472 5473 u8 other_vport[0x1]; 5474 u8 reserved_at_41[0xb]; 5475 u8 port_num[0x4]; 5476 u8 vport_number[0x10]; 5477 5478 u8 reserved_at_60[0x10]; 5479 u8 gid_index[0x10]; 5480 }; 5481 5482 struct mlx5_ifc_query_hca_vport_context_out_bits { 5483 u8 status[0x8]; 5484 u8 reserved_at_8[0x18]; 5485 5486 u8 syndrome[0x20]; 5487 5488 u8 reserved_at_40[0x40]; 5489 5490 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 5491 }; 5492 5493 struct mlx5_ifc_query_hca_vport_context_in_bits { 5494 u8 opcode[0x10]; 5495 u8 reserved_at_10[0x10]; 5496 5497 u8 reserved_at_20[0x10]; 5498 u8 op_mod[0x10]; 5499 5500 u8 other_vport[0x1]; 5501 u8 reserved_at_41[0xb]; 5502 u8 port_num[0x4]; 5503 u8 vport_number[0x10]; 5504 5505 u8 reserved_at_60[0x20]; 5506 }; 5507 5508 struct mlx5_ifc_query_hca_cap_out_bits { 5509 u8 status[0x8]; 5510 u8 reserved_at_8[0x18]; 5511 5512 u8 syndrome[0x20]; 5513 5514 u8 reserved_at_40[0x40]; 5515 5516 union mlx5_ifc_hca_cap_union_bits capability; 5517 }; 5518 5519 struct mlx5_ifc_query_hca_cap_in_bits { 5520 u8 opcode[0x10]; 5521 u8 reserved_at_10[0x10]; 5522 5523 u8 reserved_at_20[0x10]; 5524 u8 op_mod[0x10]; 5525 5526 u8 other_function[0x1]; 5527 u8 reserved_at_41[0xf]; 5528 u8 function_id[0x10]; 5529 5530 u8 reserved_at_60[0x20]; 5531 }; 5532 5533 struct mlx5_ifc_other_hca_cap_bits { 5534 u8 roce[0x1]; 5535 u8 reserved_at_1[0x27f]; 5536 }; 5537 5538 struct mlx5_ifc_query_other_hca_cap_out_bits { 5539 u8 status[0x8]; 5540 u8 reserved_at_8[0x18]; 5541 5542 u8 syndrome[0x20]; 5543 5544 u8 reserved_at_40[0x40]; 5545 5546 struct mlx5_ifc_other_hca_cap_bits other_capability; 5547 }; 5548 5549 struct mlx5_ifc_query_other_hca_cap_in_bits { 5550 u8 opcode[0x10]; 5551 u8 reserved_at_10[0x10]; 5552 5553 u8 reserved_at_20[0x10]; 5554 u8 op_mod[0x10]; 5555 5556 u8 reserved_at_40[0x10]; 5557 u8 function_id[0x10]; 5558 5559 u8 reserved_at_60[0x20]; 5560 }; 5561 5562 struct mlx5_ifc_modify_other_hca_cap_out_bits { 5563 u8 status[0x8]; 5564 u8 reserved_at_8[0x18]; 5565 5566 u8 syndrome[0x20]; 5567 5568 u8 reserved_at_40[0x40]; 5569 }; 5570 5571 struct mlx5_ifc_modify_other_hca_cap_in_bits { 5572 u8 opcode[0x10]; 5573 u8 reserved_at_10[0x10]; 5574 5575 u8 reserved_at_20[0x10]; 5576 u8 op_mod[0x10]; 5577 5578 u8 reserved_at_40[0x10]; 5579 u8 function_id[0x10]; 5580 u8 field_select[0x20]; 5581 5582 struct mlx5_ifc_other_hca_cap_bits other_capability; 5583 }; 5584 5585 struct mlx5_ifc_flow_table_context_bits { 5586 u8 reformat_en[0x1]; 5587 u8 decap_en[0x1]; 5588 u8 sw_owner[0x1]; 5589 u8 termination_table[0x1]; 5590 u8 table_miss_action[0x4]; 5591 u8 level[0x8]; 5592 u8 reserved_at_10[0x8]; 5593 u8 log_size[0x8]; 5594 5595 u8 reserved_at_20[0x8]; 5596 u8 table_miss_id[0x18]; 5597 5598 u8 reserved_at_40[0x8]; 5599 u8 lag_master_next_table_id[0x18]; 5600 5601 u8 reserved_at_60[0x60]; 5602 5603 u8 sw_owner_icm_root_1[0x40]; 5604 5605 u8 sw_owner_icm_root_0[0x40]; 5606 5607 }; 5608 5609 struct mlx5_ifc_query_flow_table_out_bits { 5610 u8 status[0x8]; 5611 u8 reserved_at_8[0x18]; 5612 5613 u8 syndrome[0x20]; 5614 5615 u8 reserved_at_40[0x80]; 5616 5617 struct mlx5_ifc_flow_table_context_bits flow_table_context; 5618 }; 5619 5620 struct mlx5_ifc_query_flow_table_in_bits { 5621 u8 opcode[0x10]; 5622 u8 reserved_at_10[0x10]; 5623 5624 u8 reserved_at_20[0x10]; 5625 u8 op_mod[0x10]; 5626 5627 u8 reserved_at_40[0x40]; 5628 5629 u8 table_type[0x8]; 5630 u8 reserved_at_88[0x18]; 5631 5632 u8 reserved_at_a0[0x8]; 5633 u8 table_id[0x18]; 5634 5635 u8 reserved_at_c0[0x140]; 5636 }; 5637 5638 struct mlx5_ifc_query_fte_out_bits { 5639 u8 status[0x8]; 5640 u8 reserved_at_8[0x18]; 5641 5642 u8 syndrome[0x20]; 5643 5644 u8 reserved_at_40[0x1c0]; 5645 5646 struct mlx5_ifc_flow_context_bits flow_context; 5647 }; 5648 5649 struct mlx5_ifc_query_fte_in_bits { 5650 u8 opcode[0x10]; 5651 u8 reserved_at_10[0x10]; 5652 5653 u8 reserved_at_20[0x10]; 5654 u8 op_mod[0x10]; 5655 5656 u8 reserved_at_40[0x40]; 5657 5658 u8 table_type[0x8]; 5659 u8 reserved_at_88[0x18]; 5660 5661 u8 reserved_at_a0[0x8]; 5662 u8 table_id[0x18]; 5663 5664 u8 reserved_at_c0[0x40]; 5665 5666 u8 flow_index[0x20]; 5667 5668 u8 reserved_at_120[0xe0]; 5669 }; 5670 5671 struct mlx5_ifc_match_definer_format_0_bits { 5672 u8 reserved_at_0[0x100]; 5673 5674 u8 metadata_reg_c_0[0x20]; 5675 5676 u8 metadata_reg_c_1[0x20]; 5677 5678 u8 outer_dmac_47_16[0x20]; 5679 5680 u8 outer_dmac_15_0[0x10]; 5681 u8 outer_ethertype[0x10]; 5682 5683 u8 reserved_at_180[0x1]; 5684 u8 sx_sniffer[0x1]; 5685 u8 functional_lb[0x1]; 5686 u8 outer_ip_frag[0x1]; 5687 u8 outer_qp_type[0x2]; 5688 u8 outer_encap_type[0x2]; 5689 u8 port_number[0x2]; 5690 u8 outer_l3_type[0x2]; 5691 u8 outer_l4_type[0x2]; 5692 u8 outer_first_vlan_type[0x2]; 5693 u8 outer_first_vlan_prio[0x3]; 5694 u8 outer_first_vlan_cfi[0x1]; 5695 u8 outer_first_vlan_vid[0xc]; 5696 5697 u8 outer_l4_type_ext[0x4]; 5698 u8 reserved_at_1a4[0x2]; 5699 u8 outer_ipsec_layer[0x2]; 5700 u8 outer_l2_type[0x2]; 5701 u8 force_lb[0x1]; 5702 u8 outer_l2_ok[0x1]; 5703 u8 outer_l3_ok[0x1]; 5704 u8 outer_l4_ok[0x1]; 5705 u8 outer_second_vlan_type[0x2]; 5706 u8 outer_second_vlan_prio[0x3]; 5707 u8 outer_second_vlan_cfi[0x1]; 5708 u8 outer_second_vlan_vid[0xc]; 5709 5710 u8 outer_smac_47_16[0x20]; 5711 5712 u8 outer_smac_15_0[0x10]; 5713 u8 inner_ipv4_checksum_ok[0x1]; 5714 u8 inner_l4_checksum_ok[0x1]; 5715 u8 outer_ipv4_checksum_ok[0x1]; 5716 u8 outer_l4_checksum_ok[0x1]; 5717 u8 inner_l3_ok[0x1]; 5718 u8 inner_l4_ok[0x1]; 5719 u8 outer_l3_ok_duplicate[0x1]; 5720 u8 outer_l4_ok_duplicate[0x1]; 5721 u8 outer_tcp_cwr[0x1]; 5722 u8 outer_tcp_ece[0x1]; 5723 u8 outer_tcp_urg[0x1]; 5724 u8 outer_tcp_ack[0x1]; 5725 u8 outer_tcp_psh[0x1]; 5726 u8 outer_tcp_rst[0x1]; 5727 u8 outer_tcp_syn[0x1]; 5728 u8 outer_tcp_fin[0x1]; 5729 }; 5730 5731 struct mlx5_ifc_match_definer_format_22_bits { 5732 u8 reserved_at_0[0x100]; 5733 5734 u8 outer_ip_src_addr[0x20]; 5735 5736 u8 outer_ip_dest_addr[0x20]; 5737 5738 u8 outer_l4_sport[0x10]; 5739 u8 outer_l4_dport[0x10]; 5740 5741 u8 reserved_at_160[0x1]; 5742 u8 sx_sniffer[0x1]; 5743 u8 functional_lb[0x1]; 5744 u8 outer_ip_frag[0x1]; 5745 u8 outer_qp_type[0x2]; 5746 u8 outer_encap_type[0x2]; 5747 u8 port_number[0x2]; 5748 u8 outer_l3_type[0x2]; 5749 u8 outer_l4_type[0x2]; 5750 u8 outer_first_vlan_type[0x2]; 5751 u8 outer_first_vlan_prio[0x3]; 5752 u8 outer_first_vlan_cfi[0x1]; 5753 u8 outer_first_vlan_vid[0xc]; 5754 5755 u8 metadata_reg_c_0[0x20]; 5756 5757 u8 outer_dmac_47_16[0x20]; 5758 5759 u8 outer_smac_47_16[0x20]; 5760 5761 u8 outer_smac_15_0[0x10]; 5762 u8 outer_dmac_15_0[0x10]; 5763 }; 5764 5765 struct mlx5_ifc_match_definer_format_23_bits { 5766 u8 reserved_at_0[0x100]; 5767 5768 u8 inner_ip_src_addr[0x20]; 5769 5770 u8 inner_ip_dest_addr[0x20]; 5771 5772 u8 inner_l4_sport[0x10]; 5773 u8 inner_l4_dport[0x10]; 5774 5775 u8 reserved_at_160[0x1]; 5776 u8 sx_sniffer[0x1]; 5777 u8 functional_lb[0x1]; 5778 u8 inner_ip_frag[0x1]; 5779 u8 inner_qp_type[0x2]; 5780 u8 inner_encap_type[0x2]; 5781 u8 port_number[0x2]; 5782 u8 inner_l3_type[0x2]; 5783 u8 inner_l4_type[0x2]; 5784 u8 inner_first_vlan_type[0x2]; 5785 u8 inner_first_vlan_prio[0x3]; 5786 u8 inner_first_vlan_cfi[0x1]; 5787 u8 inner_first_vlan_vid[0xc]; 5788 5789 u8 tunnel_header_0[0x20]; 5790 5791 u8 inner_dmac_47_16[0x20]; 5792 5793 u8 inner_smac_47_16[0x20]; 5794 5795 u8 inner_smac_15_0[0x10]; 5796 u8 inner_dmac_15_0[0x10]; 5797 }; 5798 5799 struct mlx5_ifc_match_definer_format_29_bits { 5800 u8 reserved_at_0[0xc0]; 5801 5802 u8 outer_ip_dest_addr[0x80]; 5803 5804 u8 outer_ip_src_addr[0x80]; 5805 5806 u8 outer_l4_sport[0x10]; 5807 u8 outer_l4_dport[0x10]; 5808 5809 u8 reserved_at_1e0[0x20]; 5810 }; 5811 5812 struct mlx5_ifc_match_definer_format_30_bits { 5813 u8 reserved_at_0[0xa0]; 5814 5815 u8 outer_ip_dest_addr[0x80]; 5816 5817 u8 outer_ip_src_addr[0x80]; 5818 5819 u8 outer_dmac_47_16[0x20]; 5820 5821 u8 outer_smac_47_16[0x20]; 5822 5823 u8 outer_smac_15_0[0x10]; 5824 u8 outer_dmac_15_0[0x10]; 5825 }; 5826 5827 struct mlx5_ifc_match_definer_format_31_bits { 5828 u8 reserved_at_0[0xc0]; 5829 5830 u8 inner_ip_dest_addr[0x80]; 5831 5832 u8 inner_ip_src_addr[0x80]; 5833 5834 u8 inner_l4_sport[0x10]; 5835 u8 inner_l4_dport[0x10]; 5836 5837 u8 reserved_at_1e0[0x20]; 5838 }; 5839 5840 struct mlx5_ifc_match_definer_format_32_bits { 5841 u8 reserved_at_0[0xa0]; 5842 5843 u8 inner_ip_dest_addr[0x80]; 5844 5845 u8 inner_ip_src_addr[0x80]; 5846 5847 u8 inner_dmac_47_16[0x20]; 5848 5849 u8 inner_smac_47_16[0x20]; 5850 5851 u8 inner_smac_15_0[0x10]; 5852 u8 inner_dmac_15_0[0x10]; 5853 }; 5854 5855 struct mlx5_ifc_match_definer_bits { 5856 u8 modify_field_select[0x40]; 5857 5858 u8 reserved_at_40[0x40]; 5859 5860 u8 reserved_at_80[0x10]; 5861 u8 format_id[0x10]; 5862 5863 u8 reserved_at_a0[0x160]; 5864 5865 u8 match_mask[16][0x20]; 5866 }; 5867 5868 struct mlx5_ifc_general_obj_in_cmd_hdr_bits { 5869 u8 opcode[0x10]; 5870 u8 uid[0x10]; 5871 5872 u8 vhca_tunnel_id[0x10]; 5873 u8 obj_type[0x10]; 5874 5875 u8 obj_id[0x20]; 5876 5877 u8 reserved_at_60[0x20]; 5878 }; 5879 5880 struct mlx5_ifc_general_obj_out_cmd_hdr_bits { 5881 u8 status[0x8]; 5882 u8 reserved_at_8[0x18]; 5883 5884 u8 syndrome[0x20]; 5885 5886 u8 obj_id[0x20]; 5887 5888 u8 reserved_at_60[0x20]; 5889 }; 5890 5891 struct mlx5_ifc_create_match_definer_in_bits { 5892 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 5893 5894 struct mlx5_ifc_match_definer_bits obj_context; 5895 }; 5896 5897 struct mlx5_ifc_create_match_definer_out_bits { 5898 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 5899 }; 5900 5901 enum { 5902 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 5903 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 5904 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 5905 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3, 5906 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_3 = 0x4, 5907 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_4 = 0x5, 5908 }; 5909 5910 struct mlx5_ifc_query_flow_group_out_bits { 5911 u8 status[0x8]; 5912 u8 reserved_at_8[0x18]; 5913 5914 u8 syndrome[0x20]; 5915 5916 u8 reserved_at_40[0xa0]; 5917 5918 u8 start_flow_index[0x20]; 5919 5920 u8 reserved_at_100[0x20]; 5921 5922 u8 end_flow_index[0x20]; 5923 5924 u8 reserved_at_140[0xa0]; 5925 5926 u8 reserved_at_1e0[0x18]; 5927 u8 match_criteria_enable[0x8]; 5928 5929 struct mlx5_ifc_fte_match_param_bits match_criteria; 5930 5931 u8 reserved_at_1200[0xe00]; 5932 }; 5933 5934 struct mlx5_ifc_query_flow_group_in_bits { 5935 u8 opcode[0x10]; 5936 u8 reserved_at_10[0x10]; 5937 5938 u8 reserved_at_20[0x10]; 5939 u8 op_mod[0x10]; 5940 5941 u8 reserved_at_40[0x40]; 5942 5943 u8 table_type[0x8]; 5944 u8 reserved_at_88[0x18]; 5945 5946 u8 reserved_at_a0[0x8]; 5947 u8 table_id[0x18]; 5948 5949 u8 group_id[0x20]; 5950 5951 u8 reserved_at_e0[0x120]; 5952 }; 5953 5954 struct mlx5_ifc_query_flow_counter_out_bits { 5955 u8 status[0x8]; 5956 u8 reserved_at_8[0x18]; 5957 5958 u8 syndrome[0x20]; 5959 5960 u8 reserved_at_40[0x40]; 5961 5962 struct mlx5_ifc_traffic_counter_bits flow_statistics[]; 5963 }; 5964 5965 struct mlx5_ifc_query_flow_counter_in_bits { 5966 u8 opcode[0x10]; 5967 u8 reserved_at_10[0x10]; 5968 5969 u8 reserved_at_20[0x10]; 5970 u8 op_mod[0x10]; 5971 5972 u8 reserved_at_40[0x80]; 5973 5974 u8 clear[0x1]; 5975 u8 reserved_at_c1[0xf]; 5976 u8 num_of_counters[0x10]; 5977 5978 u8 flow_counter_id[0x20]; 5979 }; 5980 5981 struct mlx5_ifc_query_esw_vport_context_out_bits { 5982 u8 status[0x8]; 5983 u8 reserved_at_8[0x18]; 5984 5985 u8 syndrome[0x20]; 5986 5987 u8 reserved_at_40[0x40]; 5988 5989 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 5990 }; 5991 5992 struct mlx5_ifc_query_esw_vport_context_in_bits { 5993 u8 opcode[0x10]; 5994 u8 reserved_at_10[0x10]; 5995 5996 u8 reserved_at_20[0x10]; 5997 u8 op_mod[0x10]; 5998 5999 u8 other_vport[0x1]; 6000 u8 reserved_at_41[0xf]; 6001 u8 vport_number[0x10]; 6002 6003 u8 reserved_at_60[0x20]; 6004 }; 6005 6006 struct mlx5_ifc_modify_esw_vport_context_out_bits { 6007 u8 status[0x8]; 6008 u8 reserved_at_8[0x18]; 6009 6010 u8 syndrome[0x20]; 6011 6012 u8 reserved_at_40[0x40]; 6013 }; 6014 6015 struct mlx5_ifc_esw_vport_context_fields_select_bits { 6016 u8 reserved_at_0[0x1b]; 6017 u8 fdb_to_vport_reg_c_id[0x1]; 6018 u8 vport_cvlan_insert[0x1]; 6019 u8 vport_svlan_insert[0x1]; 6020 u8 vport_cvlan_strip[0x1]; 6021 u8 vport_svlan_strip[0x1]; 6022 }; 6023 6024 struct mlx5_ifc_modify_esw_vport_context_in_bits { 6025 u8 opcode[0x10]; 6026 u8 reserved_at_10[0x10]; 6027 6028 u8 reserved_at_20[0x10]; 6029 u8 op_mod[0x10]; 6030 6031 u8 other_vport[0x1]; 6032 u8 reserved_at_41[0xf]; 6033 u8 vport_number[0x10]; 6034 6035 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select; 6036 6037 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 6038 }; 6039 6040 struct mlx5_ifc_query_eq_out_bits { 6041 u8 status[0x8]; 6042 u8 reserved_at_8[0x18]; 6043 6044 u8 syndrome[0x20]; 6045 6046 u8 reserved_at_40[0x40]; 6047 6048 struct mlx5_ifc_eqc_bits eq_context_entry; 6049 6050 u8 reserved_at_280[0x40]; 6051 6052 u8 event_bitmask[0x40]; 6053 6054 u8 reserved_at_300[0x580]; 6055 6056 u8 pas[][0x40]; 6057 }; 6058 6059 struct mlx5_ifc_query_eq_in_bits { 6060 u8 opcode[0x10]; 6061 u8 reserved_at_10[0x10]; 6062 6063 u8 reserved_at_20[0x10]; 6064 u8 op_mod[0x10]; 6065 6066 u8 reserved_at_40[0x18]; 6067 u8 eq_number[0x8]; 6068 6069 u8 reserved_at_60[0x20]; 6070 }; 6071 6072 struct mlx5_ifc_packet_reformat_context_in_bits { 6073 u8 reformat_type[0x8]; 6074 u8 reserved_at_8[0x4]; 6075 u8 reformat_param_0[0x4]; 6076 u8 reserved_at_10[0x6]; 6077 u8 reformat_data_size[0xa]; 6078 6079 u8 reformat_param_1[0x8]; 6080 u8 reserved_at_28[0x8]; 6081 u8 reformat_data[2][0x8]; 6082 6083 u8 more_reformat_data[][0x8]; 6084 }; 6085 6086 struct mlx5_ifc_query_packet_reformat_context_out_bits { 6087 u8 status[0x8]; 6088 u8 reserved_at_8[0x18]; 6089 6090 u8 syndrome[0x20]; 6091 6092 u8 reserved_at_40[0xa0]; 6093 6094 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context[]; 6095 }; 6096 6097 struct mlx5_ifc_query_packet_reformat_context_in_bits { 6098 u8 opcode[0x10]; 6099 u8 reserved_at_10[0x10]; 6100 6101 u8 reserved_at_20[0x10]; 6102 u8 op_mod[0x10]; 6103 6104 u8 packet_reformat_id[0x20]; 6105 6106 u8 reserved_at_60[0xa0]; 6107 }; 6108 6109 struct mlx5_ifc_alloc_packet_reformat_context_out_bits { 6110 u8 status[0x8]; 6111 u8 reserved_at_8[0x18]; 6112 6113 u8 syndrome[0x20]; 6114 6115 u8 packet_reformat_id[0x20]; 6116 6117 u8 reserved_at_60[0x20]; 6118 }; 6119 6120 enum { 6121 MLX5_REFORMAT_CONTEXT_ANCHOR_MAC_START = 0x1, 6122 MLX5_REFORMAT_CONTEXT_ANCHOR_IP_START = 0x7, 6123 MLX5_REFORMAT_CONTEXT_ANCHOR_TCP_UDP_START = 0x9, 6124 }; 6125 6126 enum mlx5_reformat_ctx_type { 6127 MLX5_REFORMAT_TYPE_L2_TO_VXLAN = 0x0, 6128 MLX5_REFORMAT_TYPE_L2_TO_NVGRE = 0x1, 6129 MLX5_REFORMAT_TYPE_L2_TO_L2_TUNNEL = 0x2, 6130 MLX5_REFORMAT_TYPE_L3_TUNNEL_TO_L2 = 0x3, 6131 MLX5_REFORMAT_TYPE_L2_TO_L3_TUNNEL = 0x4, 6132 MLX5_REFORMAT_TYPE_INSERT_HDR = 0xf, 6133 MLX5_REFORMAT_TYPE_REMOVE_HDR = 0x10, 6134 }; 6135 6136 struct mlx5_ifc_alloc_packet_reformat_context_in_bits { 6137 u8 opcode[0x10]; 6138 u8 reserved_at_10[0x10]; 6139 6140 u8 reserved_at_20[0x10]; 6141 u8 op_mod[0x10]; 6142 6143 u8 reserved_at_40[0xa0]; 6144 6145 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context; 6146 }; 6147 6148 struct mlx5_ifc_dealloc_packet_reformat_context_out_bits { 6149 u8 status[0x8]; 6150 u8 reserved_at_8[0x18]; 6151 6152 u8 syndrome[0x20]; 6153 6154 u8 reserved_at_40[0x40]; 6155 }; 6156 6157 struct mlx5_ifc_dealloc_packet_reformat_context_in_bits { 6158 u8 opcode[0x10]; 6159 u8 reserved_at_10[0x10]; 6160 6161 u8 reserved_20[0x10]; 6162 u8 op_mod[0x10]; 6163 6164 u8 packet_reformat_id[0x20]; 6165 6166 u8 reserved_60[0x20]; 6167 }; 6168 6169 struct mlx5_ifc_set_action_in_bits { 6170 u8 action_type[0x4]; 6171 u8 field[0xc]; 6172 u8 reserved_at_10[0x3]; 6173 u8 offset[0x5]; 6174 u8 reserved_at_18[0x3]; 6175 u8 length[0x5]; 6176 6177 u8 data[0x20]; 6178 }; 6179 6180 struct mlx5_ifc_add_action_in_bits { 6181 u8 action_type[0x4]; 6182 u8 field[0xc]; 6183 u8 reserved_at_10[0x10]; 6184 6185 u8 data[0x20]; 6186 }; 6187 6188 struct mlx5_ifc_copy_action_in_bits { 6189 u8 action_type[0x4]; 6190 u8 src_field[0xc]; 6191 u8 reserved_at_10[0x3]; 6192 u8 src_offset[0x5]; 6193 u8 reserved_at_18[0x3]; 6194 u8 length[0x5]; 6195 6196 u8 reserved_at_20[0x4]; 6197 u8 dst_field[0xc]; 6198 u8 reserved_at_30[0x3]; 6199 u8 dst_offset[0x5]; 6200 u8 reserved_at_38[0x8]; 6201 }; 6202 6203 union mlx5_ifc_set_add_copy_action_in_auto_bits { 6204 struct mlx5_ifc_set_action_in_bits set_action_in; 6205 struct mlx5_ifc_add_action_in_bits add_action_in; 6206 struct mlx5_ifc_copy_action_in_bits copy_action_in; 6207 u8 reserved_at_0[0x40]; 6208 }; 6209 6210 enum { 6211 MLX5_ACTION_TYPE_SET = 0x1, 6212 MLX5_ACTION_TYPE_ADD = 0x2, 6213 MLX5_ACTION_TYPE_COPY = 0x3, 6214 }; 6215 6216 enum { 6217 MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16 = 0x1, 6218 MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0 = 0x2, 6219 MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE = 0x3, 6220 MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16 = 0x4, 6221 MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0 = 0x5, 6222 MLX5_ACTION_IN_FIELD_OUT_IP_DSCP = 0x6, 6223 MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS = 0x7, 6224 MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT = 0x8, 6225 MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT = 0x9, 6226 MLX5_ACTION_IN_FIELD_OUT_IP_TTL = 0xa, 6227 MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT = 0xb, 6228 MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT = 0xc, 6229 MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96 = 0xd, 6230 MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64 = 0xe, 6231 MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32 = 0xf, 6232 MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0 = 0x10, 6233 MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96 = 0x11, 6234 MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64 = 0x12, 6235 MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32 = 0x13, 6236 MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0 = 0x14, 6237 MLX5_ACTION_IN_FIELD_OUT_SIPV4 = 0x15, 6238 MLX5_ACTION_IN_FIELD_OUT_DIPV4 = 0x16, 6239 MLX5_ACTION_IN_FIELD_OUT_FIRST_VID = 0x17, 6240 MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47, 6241 MLX5_ACTION_IN_FIELD_METADATA_REG_A = 0x49, 6242 MLX5_ACTION_IN_FIELD_METADATA_REG_B = 0x50, 6243 MLX5_ACTION_IN_FIELD_METADATA_REG_C_0 = 0x51, 6244 MLX5_ACTION_IN_FIELD_METADATA_REG_C_1 = 0x52, 6245 MLX5_ACTION_IN_FIELD_METADATA_REG_C_2 = 0x53, 6246 MLX5_ACTION_IN_FIELD_METADATA_REG_C_3 = 0x54, 6247 MLX5_ACTION_IN_FIELD_METADATA_REG_C_4 = 0x55, 6248 MLX5_ACTION_IN_FIELD_METADATA_REG_C_5 = 0x56, 6249 MLX5_ACTION_IN_FIELD_METADATA_REG_C_6 = 0x57, 6250 MLX5_ACTION_IN_FIELD_METADATA_REG_C_7 = 0x58, 6251 MLX5_ACTION_IN_FIELD_OUT_TCP_SEQ_NUM = 0x59, 6252 MLX5_ACTION_IN_FIELD_OUT_TCP_ACK_NUM = 0x5B, 6253 MLX5_ACTION_IN_FIELD_IPSEC_SYNDROME = 0x5D, 6254 MLX5_ACTION_IN_FIELD_OUT_EMD_47_32 = 0x6F, 6255 MLX5_ACTION_IN_FIELD_OUT_EMD_31_0 = 0x70, 6256 }; 6257 6258 struct mlx5_ifc_alloc_modify_header_context_out_bits { 6259 u8 status[0x8]; 6260 u8 reserved_at_8[0x18]; 6261 6262 u8 syndrome[0x20]; 6263 6264 u8 modify_header_id[0x20]; 6265 6266 u8 reserved_at_60[0x20]; 6267 }; 6268 6269 struct mlx5_ifc_alloc_modify_header_context_in_bits { 6270 u8 opcode[0x10]; 6271 u8 reserved_at_10[0x10]; 6272 6273 u8 reserved_at_20[0x10]; 6274 u8 op_mod[0x10]; 6275 6276 u8 reserved_at_40[0x20]; 6277 6278 u8 table_type[0x8]; 6279 u8 reserved_at_68[0x10]; 6280 u8 num_of_actions[0x8]; 6281 6282 union mlx5_ifc_set_add_copy_action_in_auto_bits actions[]; 6283 }; 6284 6285 struct mlx5_ifc_dealloc_modify_header_context_out_bits { 6286 u8 status[0x8]; 6287 u8 reserved_at_8[0x18]; 6288 6289 u8 syndrome[0x20]; 6290 6291 u8 reserved_at_40[0x40]; 6292 }; 6293 6294 struct mlx5_ifc_dealloc_modify_header_context_in_bits { 6295 u8 opcode[0x10]; 6296 u8 reserved_at_10[0x10]; 6297 6298 u8 reserved_at_20[0x10]; 6299 u8 op_mod[0x10]; 6300 6301 u8 modify_header_id[0x20]; 6302 6303 u8 reserved_at_60[0x20]; 6304 }; 6305 6306 struct mlx5_ifc_query_modify_header_context_in_bits { 6307 u8 opcode[0x10]; 6308 u8 uid[0x10]; 6309 6310 u8 reserved_at_20[0x10]; 6311 u8 op_mod[0x10]; 6312 6313 u8 modify_header_id[0x20]; 6314 6315 u8 reserved_at_60[0xa0]; 6316 }; 6317 6318 struct mlx5_ifc_query_dct_out_bits { 6319 u8 status[0x8]; 6320 u8 reserved_at_8[0x18]; 6321 6322 u8 syndrome[0x20]; 6323 6324 u8 reserved_at_40[0x40]; 6325 6326 struct mlx5_ifc_dctc_bits dct_context_entry; 6327 6328 u8 reserved_at_280[0x180]; 6329 }; 6330 6331 struct mlx5_ifc_query_dct_in_bits { 6332 u8 opcode[0x10]; 6333 u8 reserved_at_10[0x10]; 6334 6335 u8 reserved_at_20[0x10]; 6336 u8 op_mod[0x10]; 6337 6338 u8 reserved_at_40[0x8]; 6339 u8 dctn[0x18]; 6340 6341 u8 reserved_at_60[0x20]; 6342 }; 6343 6344 struct mlx5_ifc_query_cq_out_bits { 6345 u8 status[0x8]; 6346 u8 reserved_at_8[0x18]; 6347 6348 u8 syndrome[0x20]; 6349 6350 u8 reserved_at_40[0x40]; 6351 6352 struct mlx5_ifc_cqc_bits cq_context; 6353 6354 u8 reserved_at_280[0x600]; 6355 6356 u8 pas[][0x40]; 6357 }; 6358 6359 struct mlx5_ifc_query_cq_in_bits { 6360 u8 opcode[0x10]; 6361 u8 reserved_at_10[0x10]; 6362 6363 u8 reserved_at_20[0x10]; 6364 u8 op_mod[0x10]; 6365 6366 u8 reserved_at_40[0x8]; 6367 u8 cqn[0x18]; 6368 6369 u8 reserved_at_60[0x20]; 6370 }; 6371 6372 struct mlx5_ifc_query_cong_status_out_bits { 6373 u8 status[0x8]; 6374 u8 reserved_at_8[0x18]; 6375 6376 u8 syndrome[0x20]; 6377 6378 u8 reserved_at_40[0x20]; 6379 6380 u8 enable[0x1]; 6381 u8 tag_enable[0x1]; 6382 u8 reserved_at_62[0x1e]; 6383 }; 6384 6385 struct mlx5_ifc_query_cong_status_in_bits { 6386 u8 opcode[0x10]; 6387 u8 reserved_at_10[0x10]; 6388 6389 u8 reserved_at_20[0x10]; 6390 u8 op_mod[0x10]; 6391 6392 u8 reserved_at_40[0x18]; 6393 u8 priority[0x4]; 6394 u8 cong_protocol[0x4]; 6395 6396 u8 reserved_at_60[0x20]; 6397 }; 6398 6399 struct mlx5_ifc_query_cong_statistics_out_bits { 6400 u8 status[0x8]; 6401 u8 reserved_at_8[0x18]; 6402 6403 u8 syndrome[0x20]; 6404 6405 u8 reserved_at_40[0x40]; 6406 6407 u8 rp_cur_flows[0x20]; 6408 6409 u8 sum_flows[0x20]; 6410 6411 u8 rp_cnp_ignored_high[0x20]; 6412 6413 u8 rp_cnp_ignored_low[0x20]; 6414 6415 u8 rp_cnp_handled_high[0x20]; 6416 6417 u8 rp_cnp_handled_low[0x20]; 6418 6419 u8 reserved_at_140[0x100]; 6420 6421 u8 time_stamp_high[0x20]; 6422 6423 u8 time_stamp_low[0x20]; 6424 6425 u8 accumulators_period[0x20]; 6426 6427 u8 np_ecn_marked_roce_packets_high[0x20]; 6428 6429 u8 np_ecn_marked_roce_packets_low[0x20]; 6430 6431 u8 np_cnp_sent_high[0x20]; 6432 6433 u8 np_cnp_sent_low[0x20]; 6434 6435 u8 reserved_at_320[0x560]; 6436 }; 6437 6438 struct mlx5_ifc_query_cong_statistics_in_bits { 6439 u8 opcode[0x10]; 6440 u8 reserved_at_10[0x10]; 6441 6442 u8 reserved_at_20[0x10]; 6443 u8 op_mod[0x10]; 6444 6445 u8 clear[0x1]; 6446 u8 reserved_at_41[0x1f]; 6447 6448 u8 reserved_at_60[0x20]; 6449 }; 6450 6451 struct mlx5_ifc_query_cong_params_out_bits { 6452 u8 status[0x8]; 6453 u8 reserved_at_8[0x18]; 6454 6455 u8 syndrome[0x20]; 6456 6457 u8 reserved_at_40[0x40]; 6458 6459 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 6460 }; 6461 6462 struct mlx5_ifc_query_cong_params_in_bits { 6463 u8 opcode[0x10]; 6464 u8 reserved_at_10[0x10]; 6465 6466 u8 reserved_at_20[0x10]; 6467 u8 op_mod[0x10]; 6468 6469 u8 reserved_at_40[0x1c]; 6470 u8 cong_protocol[0x4]; 6471 6472 u8 reserved_at_60[0x20]; 6473 }; 6474 6475 struct mlx5_ifc_query_adapter_out_bits { 6476 u8 status[0x8]; 6477 u8 reserved_at_8[0x18]; 6478 6479 u8 syndrome[0x20]; 6480 6481 u8 reserved_at_40[0x40]; 6482 6483 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct; 6484 }; 6485 6486 struct mlx5_ifc_query_adapter_in_bits { 6487 u8 opcode[0x10]; 6488 u8 reserved_at_10[0x10]; 6489 6490 u8 reserved_at_20[0x10]; 6491 u8 op_mod[0x10]; 6492 6493 u8 reserved_at_40[0x40]; 6494 }; 6495 6496 struct mlx5_ifc_qp_2rst_out_bits { 6497 u8 status[0x8]; 6498 u8 reserved_at_8[0x18]; 6499 6500 u8 syndrome[0x20]; 6501 6502 u8 reserved_at_40[0x40]; 6503 }; 6504 6505 struct mlx5_ifc_qp_2rst_in_bits { 6506 u8 opcode[0x10]; 6507 u8 uid[0x10]; 6508 6509 u8 reserved_at_20[0x10]; 6510 u8 op_mod[0x10]; 6511 6512 u8 reserved_at_40[0x8]; 6513 u8 qpn[0x18]; 6514 6515 u8 reserved_at_60[0x20]; 6516 }; 6517 6518 struct mlx5_ifc_qp_2err_out_bits { 6519 u8 status[0x8]; 6520 u8 reserved_at_8[0x18]; 6521 6522 u8 syndrome[0x20]; 6523 6524 u8 reserved_at_40[0x40]; 6525 }; 6526 6527 struct mlx5_ifc_qp_2err_in_bits { 6528 u8 opcode[0x10]; 6529 u8 uid[0x10]; 6530 6531 u8 reserved_at_20[0x10]; 6532 u8 op_mod[0x10]; 6533 6534 u8 reserved_at_40[0x8]; 6535 u8 qpn[0x18]; 6536 6537 u8 reserved_at_60[0x20]; 6538 }; 6539 6540 struct mlx5_ifc_page_fault_resume_out_bits { 6541 u8 status[0x8]; 6542 u8 reserved_at_8[0x18]; 6543 6544 u8 syndrome[0x20]; 6545 6546 u8 reserved_at_40[0x40]; 6547 }; 6548 6549 struct mlx5_ifc_page_fault_resume_in_bits { 6550 u8 opcode[0x10]; 6551 u8 reserved_at_10[0x10]; 6552 6553 u8 reserved_at_20[0x10]; 6554 u8 op_mod[0x10]; 6555 6556 u8 error[0x1]; 6557 u8 reserved_at_41[0x4]; 6558 u8 page_fault_type[0x3]; 6559 u8 wq_number[0x18]; 6560 6561 u8 reserved_at_60[0x8]; 6562 u8 token[0x18]; 6563 }; 6564 6565 struct mlx5_ifc_nop_out_bits { 6566 u8 status[0x8]; 6567 u8 reserved_at_8[0x18]; 6568 6569 u8 syndrome[0x20]; 6570 6571 u8 reserved_at_40[0x40]; 6572 }; 6573 6574 struct mlx5_ifc_nop_in_bits { 6575 u8 opcode[0x10]; 6576 u8 reserved_at_10[0x10]; 6577 6578 u8 reserved_at_20[0x10]; 6579 u8 op_mod[0x10]; 6580 6581 u8 reserved_at_40[0x40]; 6582 }; 6583 6584 struct mlx5_ifc_modify_vport_state_out_bits { 6585 u8 status[0x8]; 6586 u8 reserved_at_8[0x18]; 6587 6588 u8 syndrome[0x20]; 6589 6590 u8 reserved_at_40[0x40]; 6591 }; 6592 6593 struct mlx5_ifc_modify_vport_state_in_bits { 6594 u8 opcode[0x10]; 6595 u8 reserved_at_10[0x10]; 6596 6597 u8 reserved_at_20[0x10]; 6598 u8 op_mod[0x10]; 6599 6600 u8 other_vport[0x1]; 6601 u8 reserved_at_41[0xf]; 6602 u8 vport_number[0x10]; 6603 6604 u8 reserved_at_60[0x18]; 6605 u8 admin_state[0x4]; 6606 u8 reserved_at_7c[0x4]; 6607 }; 6608 6609 struct mlx5_ifc_modify_tis_out_bits { 6610 u8 status[0x8]; 6611 u8 reserved_at_8[0x18]; 6612 6613 u8 syndrome[0x20]; 6614 6615 u8 reserved_at_40[0x40]; 6616 }; 6617 6618 struct mlx5_ifc_modify_tis_bitmask_bits { 6619 u8 reserved_at_0[0x20]; 6620 6621 u8 reserved_at_20[0x1d]; 6622 u8 lag_tx_port_affinity[0x1]; 6623 u8 strict_lag_tx_port_affinity[0x1]; 6624 u8 prio[0x1]; 6625 }; 6626 6627 struct mlx5_ifc_modify_tis_in_bits { 6628 u8 opcode[0x10]; 6629 u8 uid[0x10]; 6630 6631 u8 reserved_at_20[0x10]; 6632 u8 op_mod[0x10]; 6633 6634 u8 reserved_at_40[0x8]; 6635 u8 tisn[0x18]; 6636 6637 u8 reserved_at_60[0x20]; 6638 6639 struct mlx5_ifc_modify_tis_bitmask_bits bitmask; 6640 6641 u8 reserved_at_c0[0x40]; 6642 6643 struct mlx5_ifc_tisc_bits ctx; 6644 }; 6645 6646 struct mlx5_ifc_modify_tir_bitmask_bits { 6647 u8 reserved_at_0[0x20]; 6648 6649 u8 reserved_at_20[0x1b]; 6650 u8 self_lb_en[0x1]; 6651 u8 reserved_at_3c[0x1]; 6652 u8 hash[0x1]; 6653 u8 reserved_at_3e[0x1]; 6654 u8 lro[0x1]; 6655 }; 6656 6657 struct mlx5_ifc_modify_tir_out_bits { 6658 u8 status[0x8]; 6659 u8 reserved_at_8[0x18]; 6660 6661 u8 syndrome[0x20]; 6662 6663 u8 reserved_at_40[0x40]; 6664 }; 6665 6666 struct mlx5_ifc_modify_tir_in_bits { 6667 u8 opcode[0x10]; 6668 u8 uid[0x10]; 6669 6670 u8 reserved_at_20[0x10]; 6671 u8 op_mod[0x10]; 6672 6673 u8 reserved_at_40[0x8]; 6674 u8 tirn[0x18]; 6675 6676 u8 reserved_at_60[0x20]; 6677 6678 struct mlx5_ifc_modify_tir_bitmask_bits bitmask; 6679 6680 u8 reserved_at_c0[0x40]; 6681 6682 struct mlx5_ifc_tirc_bits ctx; 6683 }; 6684 6685 struct mlx5_ifc_modify_sq_out_bits { 6686 u8 status[0x8]; 6687 u8 reserved_at_8[0x18]; 6688 6689 u8 syndrome[0x20]; 6690 6691 u8 reserved_at_40[0x40]; 6692 }; 6693 6694 struct mlx5_ifc_modify_sq_in_bits { 6695 u8 opcode[0x10]; 6696 u8 uid[0x10]; 6697 6698 u8 reserved_at_20[0x10]; 6699 u8 op_mod[0x10]; 6700 6701 u8 sq_state[0x4]; 6702 u8 reserved_at_44[0x4]; 6703 u8 sqn[0x18]; 6704 6705 u8 reserved_at_60[0x20]; 6706 6707 u8 modify_bitmask[0x40]; 6708 6709 u8 reserved_at_c0[0x40]; 6710 6711 struct mlx5_ifc_sqc_bits ctx; 6712 }; 6713 6714 struct mlx5_ifc_modify_scheduling_element_out_bits { 6715 u8 status[0x8]; 6716 u8 reserved_at_8[0x18]; 6717 6718 u8 syndrome[0x20]; 6719 6720 u8 reserved_at_40[0x1c0]; 6721 }; 6722 6723 enum { 6724 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1, 6725 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2, 6726 }; 6727 6728 struct mlx5_ifc_modify_scheduling_element_in_bits { 6729 u8 opcode[0x10]; 6730 u8 reserved_at_10[0x10]; 6731 6732 u8 reserved_at_20[0x10]; 6733 u8 op_mod[0x10]; 6734 6735 u8 scheduling_hierarchy[0x8]; 6736 u8 reserved_at_48[0x18]; 6737 6738 u8 scheduling_element_id[0x20]; 6739 6740 u8 reserved_at_80[0x20]; 6741 6742 u8 modify_bitmask[0x20]; 6743 6744 u8 reserved_at_c0[0x40]; 6745 6746 struct mlx5_ifc_scheduling_context_bits scheduling_context; 6747 6748 u8 reserved_at_300[0x100]; 6749 }; 6750 6751 struct mlx5_ifc_modify_rqt_out_bits { 6752 u8 status[0x8]; 6753 u8 reserved_at_8[0x18]; 6754 6755 u8 syndrome[0x20]; 6756 6757 u8 reserved_at_40[0x40]; 6758 }; 6759 6760 struct mlx5_ifc_rqt_bitmask_bits { 6761 u8 reserved_at_0[0x20]; 6762 6763 u8 reserved_at_20[0x1f]; 6764 u8 rqn_list[0x1]; 6765 }; 6766 6767 struct mlx5_ifc_modify_rqt_in_bits { 6768 u8 opcode[0x10]; 6769 u8 uid[0x10]; 6770 6771 u8 reserved_at_20[0x10]; 6772 u8 op_mod[0x10]; 6773 6774 u8 reserved_at_40[0x8]; 6775 u8 rqtn[0x18]; 6776 6777 u8 reserved_at_60[0x20]; 6778 6779 struct mlx5_ifc_rqt_bitmask_bits bitmask; 6780 6781 u8 reserved_at_c0[0x40]; 6782 6783 struct mlx5_ifc_rqtc_bits ctx; 6784 }; 6785 6786 struct mlx5_ifc_modify_rq_out_bits { 6787 u8 status[0x8]; 6788 u8 reserved_at_8[0x18]; 6789 6790 u8 syndrome[0x20]; 6791 6792 u8 reserved_at_40[0x40]; 6793 }; 6794 6795 enum { 6796 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1, 6797 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2, 6798 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3, 6799 }; 6800 6801 struct mlx5_ifc_modify_rq_in_bits { 6802 u8 opcode[0x10]; 6803 u8 uid[0x10]; 6804 6805 u8 reserved_at_20[0x10]; 6806 u8 op_mod[0x10]; 6807 6808 u8 rq_state[0x4]; 6809 u8 reserved_at_44[0x4]; 6810 u8 rqn[0x18]; 6811 6812 u8 reserved_at_60[0x20]; 6813 6814 u8 modify_bitmask[0x40]; 6815 6816 u8 reserved_at_c0[0x40]; 6817 6818 struct mlx5_ifc_rqc_bits ctx; 6819 }; 6820 6821 struct mlx5_ifc_modify_rmp_out_bits { 6822 u8 status[0x8]; 6823 u8 reserved_at_8[0x18]; 6824 6825 u8 syndrome[0x20]; 6826 6827 u8 reserved_at_40[0x40]; 6828 }; 6829 6830 struct mlx5_ifc_rmp_bitmask_bits { 6831 u8 reserved_at_0[0x20]; 6832 6833 u8 reserved_at_20[0x1f]; 6834 u8 lwm[0x1]; 6835 }; 6836 6837 struct mlx5_ifc_modify_rmp_in_bits { 6838 u8 opcode[0x10]; 6839 u8 uid[0x10]; 6840 6841 u8 reserved_at_20[0x10]; 6842 u8 op_mod[0x10]; 6843 6844 u8 rmp_state[0x4]; 6845 u8 reserved_at_44[0x4]; 6846 u8 rmpn[0x18]; 6847 6848 u8 reserved_at_60[0x20]; 6849 6850 struct mlx5_ifc_rmp_bitmask_bits bitmask; 6851 6852 u8 reserved_at_c0[0x40]; 6853 6854 struct mlx5_ifc_rmpc_bits ctx; 6855 }; 6856 6857 struct mlx5_ifc_modify_nic_vport_context_out_bits { 6858 u8 status[0x8]; 6859 u8 reserved_at_8[0x18]; 6860 6861 u8 syndrome[0x20]; 6862 6863 u8 reserved_at_40[0x40]; 6864 }; 6865 6866 struct mlx5_ifc_modify_nic_vport_field_select_bits { 6867 u8 reserved_at_0[0x12]; 6868 u8 affiliation[0x1]; 6869 u8 reserved_at_13[0x1]; 6870 u8 disable_uc_local_lb[0x1]; 6871 u8 disable_mc_local_lb[0x1]; 6872 u8 node_guid[0x1]; 6873 u8 port_guid[0x1]; 6874 u8 min_inline[0x1]; 6875 u8 mtu[0x1]; 6876 u8 change_event[0x1]; 6877 u8 promisc[0x1]; 6878 u8 permanent_address[0x1]; 6879 u8 addresses_list[0x1]; 6880 u8 roce_en[0x1]; 6881 u8 reserved_at_1f[0x1]; 6882 }; 6883 6884 struct mlx5_ifc_modify_nic_vport_context_in_bits { 6885 u8 opcode[0x10]; 6886 u8 reserved_at_10[0x10]; 6887 6888 u8 reserved_at_20[0x10]; 6889 u8 op_mod[0x10]; 6890 6891 u8 other_vport[0x1]; 6892 u8 reserved_at_41[0xf]; 6893 u8 vport_number[0x10]; 6894 6895 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select; 6896 6897 u8 reserved_at_80[0x780]; 6898 6899 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 6900 }; 6901 6902 struct mlx5_ifc_modify_hca_vport_context_out_bits { 6903 u8 status[0x8]; 6904 u8 reserved_at_8[0x18]; 6905 6906 u8 syndrome[0x20]; 6907 6908 u8 reserved_at_40[0x40]; 6909 }; 6910 6911 struct mlx5_ifc_modify_hca_vport_context_in_bits { 6912 u8 opcode[0x10]; 6913 u8 reserved_at_10[0x10]; 6914 6915 u8 reserved_at_20[0x10]; 6916 u8 op_mod[0x10]; 6917 6918 u8 other_vport[0x1]; 6919 u8 reserved_at_41[0xb]; 6920 u8 port_num[0x4]; 6921 u8 vport_number[0x10]; 6922 6923 u8 reserved_at_60[0x20]; 6924 6925 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 6926 }; 6927 6928 struct mlx5_ifc_modify_cq_out_bits { 6929 u8 status[0x8]; 6930 u8 reserved_at_8[0x18]; 6931 6932 u8 syndrome[0x20]; 6933 6934 u8 reserved_at_40[0x40]; 6935 }; 6936 6937 enum { 6938 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0, 6939 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1, 6940 }; 6941 6942 struct mlx5_ifc_modify_cq_in_bits { 6943 u8 opcode[0x10]; 6944 u8 uid[0x10]; 6945 6946 u8 reserved_at_20[0x10]; 6947 u8 op_mod[0x10]; 6948 6949 u8 reserved_at_40[0x8]; 6950 u8 cqn[0x18]; 6951 6952 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select; 6953 6954 struct mlx5_ifc_cqc_bits cq_context; 6955 6956 u8 reserved_at_280[0x60]; 6957 6958 u8 cq_umem_valid[0x1]; 6959 u8 reserved_at_2e1[0x1f]; 6960 6961 u8 reserved_at_300[0x580]; 6962 6963 u8 pas[][0x40]; 6964 }; 6965 6966 struct mlx5_ifc_modify_cong_status_out_bits { 6967 u8 status[0x8]; 6968 u8 reserved_at_8[0x18]; 6969 6970 u8 syndrome[0x20]; 6971 6972 u8 reserved_at_40[0x40]; 6973 }; 6974 6975 struct mlx5_ifc_modify_cong_status_in_bits { 6976 u8 opcode[0x10]; 6977 u8 reserved_at_10[0x10]; 6978 6979 u8 reserved_at_20[0x10]; 6980 u8 op_mod[0x10]; 6981 6982 u8 reserved_at_40[0x18]; 6983 u8 priority[0x4]; 6984 u8 cong_protocol[0x4]; 6985 6986 u8 enable[0x1]; 6987 u8 tag_enable[0x1]; 6988 u8 reserved_at_62[0x1e]; 6989 }; 6990 6991 struct mlx5_ifc_modify_cong_params_out_bits { 6992 u8 status[0x8]; 6993 u8 reserved_at_8[0x18]; 6994 6995 u8 syndrome[0x20]; 6996 6997 u8 reserved_at_40[0x40]; 6998 }; 6999 7000 struct mlx5_ifc_modify_cong_params_in_bits { 7001 u8 opcode[0x10]; 7002 u8 reserved_at_10[0x10]; 7003 7004 u8 reserved_at_20[0x10]; 7005 u8 op_mod[0x10]; 7006 7007 u8 reserved_at_40[0x1c]; 7008 u8 cong_protocol[0x4]; 7009 7010 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select; 7011 7012 u8 reserved_at_80[0x80]; 7013 7014 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 7015 }; 7016 7017 struct mlx5_ifc_manage_pages_out_bits { 7018 u8 status[0x8]; 7019 u8 reserved_at_8[0x18]; 7020 7021 u8 syndrome[0x20]; 7022 7023 u8 output_num_entries[0x20]; 7024 7025 u8 reserved_at_60[0x20]; 7026 7027 u8 pas[][0x40]; 7028 }; 7029 7030 enum { 7031 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL = 0x0, 7032 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS = 0x1, 7033 MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES = 0x2, 7034 }; 7035 7036 struct mlx5_ifc_manage_pages_in_bits { 7037 u8 opcode[0x10]; 7038 u8 reserved_at_10[0x10]; 7039 7040 u8 reserved_at_20[0x10]; 7041 u8 op_mod[0x10]; 7042 7043 u8 embedded_cpu_function[0x1]; 7044 u8 reserved_at_41[0xf]; 7045 u8 function_id[0x10]; 7046 7047 u8 input_num_entries[0x20]; 7048 7049 u8 pas[][0x40]; 7050 }; 7051 7052 struct mlx5_ifc_mad_ifc_out_bits { 7053 u8 status[0x8]; 7054 u8 reserved_at_8[0x18]; 7055 7056 u8 syndrome[0x20]; 7057 7058 u8 reserved_at_40[0x40]; 7059 7060 u8 response_mad_packet[256][0x8]; 7061 }; 7062 7063 struct mlx5_ifc_mad_ifc_in_bits { 7064 u8 opcode[0x10]; 7065 u8 reserved_at_10[0x10]; 7066 7067 u8 reserved_at_20[0x10]; 7068 u8 op_mod[0x10]; 7069 7070 u8 remote_lid[0x10]; 7071 u8 reserved_at_50[0x8]; 7072 u8 port[0x8]; 7073 7074 u8 reserved_at_60[0x20]; 7075 7076 u8 mad[256][0x8]; 7077 }; 7078 7079 struct mlx5_ifc_init_hca_out_bits { 7080 u8 status[0x8]; 7081 u8 reserved_at_8[0x18]; 7082 7083 u8 syndrome[0x20]; 7084 7085 u8 reserved_at_40[0x40]; 7086 }; 7087 7088 struct mlx5_ifc_init_hca_in_bits { 7089 u8 opcode[0x10]; 7090 u8 reserved_at_10[0x10]; 7091 7092 u8 reserved_at_20[0x10]; 7093 u8 op_mod[0x10]; 7094 7095 u8 reserved_at_40[0x40]; 7096 u8 sw_owner_id[4][0x20]; 7097 }; 7098 7099 struct mlx5_ifc_init2rtr_qp_out_bits { 7100 u8 status[0x8]; 7101 u8 reserved_at_8[0x18]; 7102 7103 u8 syndrome[0x20]; 7104 7105 u8 reserved_at_40[0x20]; 7106 u8 ece[0x20]; 7107 }; 7108 7109 struct mlx5_ifc_init2rtr_qp_in_bits { 7110 u8 opcode[0x10]; 7111 u8 uid[0x10]; 7112 7113 u8 reserved_at_20[0x10]; 7114 u8 op_mod[0x10]; 7115 7116 u8 reserved_at_40[0x8]; 7117 u8 qpn[0x18]; 7118 7119 u8 reserved_at_60[0x20]; 7120 7121 u8 opt_param_mask[0x20]; 7122 7123 u8 ece[0x20]; 7124 7125 struct mlx5_ifc_qpc_bits qpc; 7126 7127 u8 reserved_at_800[0x80]; 7128 }; 7129 7130 struct mlx5_ifc_init2init_qp_out_bits { 7131 u8 status[0x8]; 7132 u8 reserved_at_8[0x18]; 7133 7134 u8 syndrome[0x20]; 7135 7136 u8 reserved_at_40[0x20]; 7137 u8 ece[0x20]; 7138 }; 7139 7140 struct mlx5_ifc_init2init_qp_in_bits { 7141 u8 opcode[0x10]; 7142 u8 uid[0x10]; 7143 7144 u8 reserved_at_20[0x10]; 7145 u8 op_mod[0x10]; 7146 7147 u8 reserved_at_40[0x8]; 7148 u8 qpn[0x18]; 7149 7150 u8 reserved_at_60[0x20]; 7151 7152 u8 opt_param_mask[0x20]; 7153 7154 u8 ece[0x20]; 7155 7156 struct mlx5_ifc_qpc_bits qpc; 7157 7158 u8 reserved_at_800[0x80]; 7159 }; 7160 7161 struct mlx5_ifc_get_dropped_packet_log_out_bits { 7162 u8 status[0x8]; 7163 u8 reserved_at_8[0x18]; 7164 7165 u8 syndrome[0x20]; 7166 7167 u8 reserved_at_40[0x40]; 7168 7169 u8 packet_headers_log[128][0x8]; 7170 7171 u8 packet_syndrome[64][0x8]; 7172 }; 7173 7174 struct mlx5_ifc_get_dropped_packet_log_in_bits { 7175 u8 opcode[0x10]; 7176 u8 reserved_at_10[0x10]; 7177 7178 u8 reserved_at_20[0x10]; 7179 u8 op_mod[0x10]; 7180 7181 u8 reserved_at_40[0x40]; 7182 }; 7183 7184 struct mlx5_ifc_gen_eqe_in_bits { 7185 u8 opcode[0x10]; 7186 u8 reserved_at_10[0x10]; 7187 7188 u8 reserved_at_20[0x10]; 7189 u8 op_mod[0x10]; 7190 7191 u8 reserved_at_40[0x18]; 7192 u8 eq_number[0x8]; 7193 7194 u8 reserved_at_60[0x20]; 7195 7196 u8 eqe[64][0x8]; 7197 }; 7198 7199 struct mlx5_ifc_gen_eq_out_bits { 7200 u8 status[0x8]; 7201 u8 reserved_at_8[0x18]; 7202 7203 u8 syndrome[0x20]; 7204 7205 u8 reserved_at_40[0x40]; 7206 }; 7207 7208 struct mlx5_ifc_enable_hca_out_bits { 7209 u8 status[0x8]; 7210 u8 reserved_at_8[0x18]; 7211 7212 u8 syndrome[0x20]; 7213 7214 u8 reserved_at_40[0x20]; 7215 }; 7216 7217 struct mlx5_ifc_enable_hca_in_bits { 7218 u8 opcode[0x10]; 7219 u8 reserved_at_10[0x10]; 7220 7221 u8 reserved_at_20[0x10]; 7222 u8 op_mod[0x10]; 7223 7224 u8 embedded_cpu_function[0x1]; 7225 u8 reserved_at_41[0xf]; 7226 u8 function_id[0x10]; 7227 7228 u8 reserved_at_60[0x20]; 7229 }; 7230 7231 struct mlx5_ifc_drain_dct_out_bits { 7232 u8 status[0x8]; 7233 u8 reserved_at_8[0x18]; 7234 7235 u8 syndrome[0x20]; 7236 7237 u8 reserved_at_40[0x40]; 7238 }; 7239 7240 struct mlx5_ifc_drain_dct_in_bits { 7241 u8 opcode[0x10]; 7242 u8 uid[0x10]; 7243 7244 u8 reserved_at_20[0x10]; 7245 u8 op_mod[0x10]; 7246 7247 u8 reserved_at_40[0x8]; 7248 u8 dctn[0x18]; 7249 7250 u8 reserved_at_60[0x20]; 7251 }; 7252 7253 struct mlx5_ifc_disable_hca_out_bits { 7254 u8 status[0x8]; 7255 u8 reserved_at_8[0x18]; 7256 7257 u8 syndrome[0x20]; 7258 7259 u8 reserved_at_40[0x20]; 7260 }; 7261 7262 struct mlx5_ifc_disable_hca_in_bits { 7263 u8 opcode[0x10]; 7264 u8 reserved_at_10[0x10]; 7265 7266 u8 reserved_at_20[0x10]; 7267 u8 op_mod[0x10]; 7268 7269 u8 embedded_cpu_function[0x1]; 7270 u8 reserved_at_41[0xf]; 7271 u8 function_id[0x10]; 7272 7273 u8 reserved_at_60[0x20]; 7274 }; 7275 7276 struct mlx5_ifc_detach_from_mcg_out_bits { 7277 u8 status[0x8]; 7278 u8 reserved_at_8[0x18]; 7279 7280 u8 syndrome[0x20]; 7281 7282 u8 reserved_at_40[0x40]; 7283 }; 7284 7285 struct mlx5_ifc_detach_from_mcg_in_bits { 7286 u8 opcode[0x10]; 7287 u8 uid[0x10]; 7288 7289 u8 reserved_at_20[0x10]; 7290 u8 op_mod[0x10]; 7291 7292 u8 reserved_at_40[0x8]; 7293 u8 qpn[0x18]; 7294 7295 u8 reserved_at_60[0x20]; 7296 7297 u8 multicast_gid[16][0x8]; 7298 }; 7299 7300 struct mlx5_ifc_destroy_xrq_out_bits { 7301 u8 status[0x8]; 7302 u8 reserved_at_8[0x18]; 7303 7304 u8 syndrome[0x20]; 7305 7306 u8 reserved_at_40[0x40]; 7307 }; 7308 7309 struct mlx5_ifc_destroy_xrq_in_bits { 7310 u8 opcode[0x10]; 7311 u8 uid[0x10]; 7312 7313 u8 reserved_at_20[0x10]; 7314 u8 op_mod[0x10]; 7315 7316 u8 reserved_at_40[0x8]; 7317 u8 xrqn[0x18]; 7318 7319 u8 reserved_at_60[0x20]; 7320 }; 7321 7322 struct mlx5_ifc_destroy_xrc_srq_out_bits { 7323 u8 status[0x8]; 7324 u8 reserved_at_8[0x18]; 7325 7326 u8 syndrome[0x20]; 7327 7328 u8 reserved_at_40[0x40]; 7329 }; 7330 7331 struct mlx5_ifc_destroy_xrc_srq_in_bits { 7332 u8 opcode[0x10]; 7333 u8 uid[0x10]; 7334 7335 u8 reserved_at_20[0x10]; 7336 u8 op_mod[0x10]; 7337 7338 u8 reserved_at_40[0x8]; 7339 u8 xrc_srqn[0x18]; 7340 7341 u8 reserved_at_60[0x20]; 7342 }; 7343 7344 struct mlx5_ifc_destroy_tis_out_bits { 7345 u8 status[0x8]; 7346 u8 reserved_at_8[0x18]; 7347 7348 u8 syndrome[0x20]; 7349 7350 u8 reserved_at_40[0x40]; 7351 }; 7352 7353 struct mlx5_ifc_destroy_tis_in_bits { 7354 u8 opcode[0x10]; 7355 u8 uid[0x10]; 7356 7357 u8 reserved_at_20[0x10]; 7358 u8 op_mod[0x10]; 7359 7360 u8 reserved_at_40[0x8]; 7361 u8 tisn[0x18]; 7362 7363 u8 reserved_at_60[0x20]; 7364 }; 7365 7366 struct mlx5_ifc_destroy_tir_out_bits { 7367 u8 status[0x8]; 7368 u8 reserved_at_8[0x18]; 7369 7370 u8 syndrome[0x20]; 7371 7372 u8 reserved_at_40[0x40]; 7373 }; 7374 7375 struct mlx5_ifc_destroy_tir_in_bits { 7376 u8 opcode[0x10]; 7377 u8 uid[0x10]; 7378 7379 u8 reserved_at_20[0x10]; 7380 u8 op_mod[0x10]; 7381 7382 u8 reserved_at_40[0x8]; 7383 u8 tirn[0x18]; 7384 7385 u8 reserved_at_60[0x20]; 7386 }; 7387 7388 struct mlx5_ifc_destroy_srq_out_bits { 7389 u8 status[0x8]; 7390 u8 reserved_at_8[0x18]; 7391 7392 u8 syndrome[0x20]; 7393 7394 u8 reserved_at_40[0x40]; 7395 }; 7396 7397 struct mlx5_ifc_destroy_srq_in_bits { 7398 u8 opcode[0x10]; 7399 u8 uid[0x10]; 7400 7401 u8 reserved_at_20[0x10]; 7402 u8 op_mod[0x10]; 7403 7404 u8 reserved_at_40[0x8]; 7405 u8 srqn[0x18]; 7406 7407 u8 reserved_at_60[0x20]; 7408 }; 7409 7410 struct mlx5_ifc_destroy_sq_out_bits { 7411 u8 status[0x8]; 7412 u8 reserved_at_8[0x18]; 7413 7414 u8 syndrome[0x20]; 7415 7416 u8 reserved_at_40[0x40]; 7417 }; 7418 7419 struct mlx5_ifc_destroy_sq_in_bits { 7420 u8 opcode[0x10]; 7421 u8 uid[0x10]; 7422 7423 u8 reserved_at_20[0x10]; 7424 u8 op_mod[0x10]; 7425 7426 u8 reserved_at_40[0x8]; 7427 u8 sqn[0x18]; 7428 7429 u8 reserved_at_60[0x20]; 7430 }; 7431 7432 struct mlx5_ifc_destroy_scheduling_element_out_bits { 7433 u8 status[0x8]; 7434 u8 reserved_at_8[0x18]; 7435 7436 u8 syndrome[0x20]; 7437 7438 u8 reserved_at_40[0x1c0]; 7439 }; 7440 7441 struct mlx5_ifc_destroy_scheduling_element_in_bits { 7442 u8 opcode[0x10]; 7443 u8 reserved_at_10[0x10]; 7444 7445 u8 reserved_at_20[0x10]; 7446 u8 op_mod[0x10]; 7447 7448 u8 scheduling_hierarchy[0x8]; 7449 u8 reserved_at_48[0x18]; 7450 7451 u8 scheduling_element_id[0x20]; 7452 7453 u8 reserved_at_80[0x180]; 7454 }; 7455 7456 struct mlx5_ifc_destroy_rqt_out_bits { 7457 u8 status[0x8]; 7458 u8 reserved_at_8[0x18]; 7459 7460 u8 syndrome[0x20]; 7461 7462 u8 reserved_at_40[0x40]; 7463 }; 7464 7465 struct mlx5_ifc_destroy_rqt_in_bits { 7466 u8 opcode[0x10]; 7467 u8 uid[0x10]; 7468 7469 u8 reserved_at_20[0x10]; 7470 u8 op_mod[0x10]; 7471 7472 u8 reserved_at_40[0x8]; 7473 u8 rqtn[0x18]; 7474 7475 u8 reserved_at_60[0x20]; 7476 }; 7477 7478 struct mlx5_ifc_destroy_rq_out_bits { 7479 u8 status[0x8]; 7480 u8 reserved_at_8[0x18]; 7481 7482 u8 syndrome[0x20]; 7483 7484 u8 reserved_at_40[0x40]; 7485 }; 7486 7487 struct mlx5_ifc_destroy_rq_in_bits { 7488 u8 opcode[0x10]; 7489 u8 uid[0x10]; 7490 7491 u8 reserved_at_20[0x10]; 7492 u8 op_mod[0x10]; 7493 7494 u8 reserved_at_40[0x8]; 7495 u8 rqn[0x18]; 7496 7497 u8 reserved_at_60[0x20]; 7498 }; 7499 7500 struct mlx5_ifc_set_delay_drop_params_in_bits { 7501 u8 opcode[0x10]; 7502 u8 reserved_at_10[0x10]; 7503 7504 u8 reserved_at_20[0x10]; 7505 u8 op_mod[0x10]; 7506 7507 u8 reserved_at_40[0x20]; 7508 7509 u8 reserved_at_60[0x10]; 7510 u8 delay_drop_timeout[0x10]; 7511 }; 7512 7513 struct mlx5_ifc_set_delay_drop_params_out_bits { 7514 u8 status[0x8]; 7515 u8 reserved_at_8[0x18]; 7516 7517 u8 syndrome[0x20]; 7518 7519 u8 reserved_at_40[0x40]; 7520 }; 7521 7522 struct mlx5_ifc_destroy_rmp_out_bits { 7523 u8 status[0x8]; 7524 u8 reserved_at_8[0x18]; 7525 7526 u8 syndrome[0x20]; 7527 7528 u8 reserved_at_40[0x40]; 7529 }; 7530 7531 struct mlx5_ifc_destroy_rmp_in_bits { 7532 u8 opcode[0x10]; 7533 u8 uid[0x10]; 7534 7535 u8 reserved_at_20[0x10]; 7536 u8 op_mod[0x10]; 7537 7538 u8 reserved_at_40[0x8]; 7539 u8 rmpn[0x18]; 7540 7541 u8 reserved_at_60[0x20]; 7542 }; 7543 7544 struct mlx5_ifc_destroy_qp_out_bits { 7545 u8 status[0x8]; 7546 u8 reserved_at_8[0x18]; 7547 7548 u8 syndrome[0x20]; 7549 7550 u8 reserved_at_40[0x40]; 7551 }; 7552 7553 struct mlx5_ifc_destroy_qp_in_bits { 7554 u8 opcode[0x10]; 7555 u8 uid[0x10]; 7556 7557 u8 reserved_at_20[0x10]; 7558 u8 op_mod[0x10]; 7559 7560 u8 reserved_at_40[0x8]; 7561 u8 qpn[0x18]; 7562 7563 u8 reserved_at_60[0x20]; 7564 }; 7565 7566 struct mlx5_ifc_destroy_psv_out_bits { 7567 u8 status[0x8]; 7568 u8 reserved_at_8[0x18]; 7569 7570 u8 syndrome[0x20]; 7571 7572 u8 reserved_at_40[0x40]; 7573 }; 7574 7575 struct mlx5_ifc_destroy_psv_in_bits { 7576 u8 opcode[0x10]; 7577 u8 reserved_at_10[0x10]; 7578 7579 u8 reserved_at_20[0x10]; 7580 u8 op_mod[0x10]; 7581 7582 u8 reserved_at_40[0x8]; 7583 u8 psvn[0x18]; 7584 7585 u8 reserved_at_60[0x20]; 7586 }; 7587 7588 struct mlx5_ifc_destroy_mkey_out_bits { 7589 u8 status[0x8]; 7590 u8 reserved_at_8[0x18]; 7591 7592 u8 syndrome[0x20]; 7593 7594 u8 reserved_at_40[0x40]; 7595 }; 7596 7597 struct mlx5_ifc_destroy_mkey_in_bits { 7598 u8 opcode[0x10]; 7599 u8 uid[0x10]; 7600 7601 u8 reserved_at_20[0x10]; 7602 u8 op_mod[0x10]; 7603 7604 u8 reserved_at_40[0x8]; 7605 u8 mkey_index[0x18]; 7606 7607 u8 reserved_at_60[0x20]; 7608 }; 7609 7610 struct mlx5_ifc_destroy_flow_table_out_bits { 7611 u8 status[0x8]; 7612 u8 reserved_at_8[0x18]; 7613 7614 u8 syndrome[0x20]; 7615 7616 u8 reserved_at_40[0x40]; 7617 }; 7618 7619 struct mlx5_ifc_destroy_flow_table_in_bits { 7620 u8 opcode[0x10]; 7621 u8 reserved_at_10[0x10]; 7622 7623 u8 reserved_at_20[0x10]; 7624 u8 op_mod[0x10]; 7625 7626 u8 other_vport[0x1]; 7627 u8 reserved_at_41[0xf]; 7628 u8 vport_number[0x10]; 7629 7630 u8 reserved_at_60[0x20]; 7631 7632 u8 table_type[0x8]; 7633 u8 reserved_at_88[0x18]; 7634 7635 u8 reserved_at_a0[0x8]; 7636 u8 table_id[0x18]; 7637 7638 u8 reserved_at_c0[0x140]; 7639 }; 7640 7641 struct mlx5_ifc_destroy_flow_group_out_bits { 7642 u8 status[0x8]; 7643 u8 reserved_at_8[0x18]; 7644 7645 u8 syndrome[0x20]; 7646 7647 u8 reserved_at_40[0x40]; 7648 }; 7649 7650 struct mlx5_ifc_destroy_flow_group_in_bits { 7651 u8 opcode[0x10]; 7652 u8 reserved_at_10[0x10]; 7653 7654 u8 reserved_at_20[0x10]; 7655 u8 op_mod[0x10]; 7656 7657 u8 other_vport[0x1]; 7658 u8 reserved_at_41[0xf]; 7659 u8 vport_number[0x10]; 7660 7661 u8 reserved_at_60[0x20]; 7662 7663 u8 table_type[0x8]; 7664 u8 reserved_at_88[0x18]; 7665 7666 u8 reserved_at_a0[0x8]; 7667 u8 table_id[0x18]; 7668 7669 u8 group_id[0x20]; 7670 7671 u8 reserved_at_e0[0x120]; 7672 }; 7673 7674 struct mlx5_ifc_destroy_eq_out_bits { 7675 u8 status[0x8]; 7676 u8 reserved_at_8[0x18]; 7677 7678 u8 syndrome[0x20]; 7679 7680 u8 reserved_at_40[0x40]; 7681 }; 7682 7683 struct mlx5_ifc_destroy_eq_in_bits { 7684 u8 opcode[0x10]; 7685 u8 reserved_at_10[0x10]; 7686 7687 u8 reserved_at_20[0x10]; 7688 u8 op_mod[0x10]; 7689 7690 u8 reserved_at_40[0x18]; 7691 u8 eq_number[0x8]; 7692 7693 u8 reserved_at_60[0x20]; 7694 }; 7695 7696 struct mlx5_ifc_destroy_dct_out_bits { 7697 u8 status[0x8]; 7698 u8 reserved_at_8[0x18]; 7699 7700 u8 syndrome[0x20]; 7701 7702 u8 reserved_at_40[0x40]; 7703 }; 7704 7705 struct mlx5_ifc_destroy_dct_in_bits { 7706 u8 opcode[0x10]; 7707 u8 uid[0x10]; 7708 7709 u8 reserved_at_20[0x10]; 7710 u8 op_mod[0x10]; 7711 7712 u8 reserved_at_40[0x8]; 7713 u8 dctn[0x18]; 7714 7715 u8 reserved_at_60[0x20]; 7716 }; 7717 7718 struct mlx5_ifc_destroy_cq_out_bits { 7719 u8 status[0x8]; 7720 u8 reserved_at_8[0x18]; 7721 7722 u8 syndrome[0x20]; 7723 7724 u8 reserved_at_40[0x40]; 7725 }; 7726 7727 struct mlx5_ifc_destroy_cq_in_bits { 7728 u8 opcode[0x10]; 7729 u8 uid[0x10]; 7730 7731 u8 reserved_at_20[0x10]; 7732 u8 op_mod[0x10]; 7733 7734 u8 reserved_at_40[0x8]; 7735 u8 cqn[0x18]; 7736 7737 u8 reserved_at_60[0x20]; 7738 }; 7739 7740 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits { 7741 u8 status[0x8]; 7742 u8 reserved_at_8[0x18]; 7743 7744 u8 syndrome[0x20]; 7745 7746 u8 reserved_at_40[0x40]; 7747 }; 7748 7749 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits { 7750 u8 opcode[0x10]; 7751 u8 reserved_at_10[0x10]; 7752 7753 u8 reserved_at_20[0x10]; 7754 u8 op_mod[0x10]; 7755 7756 u8 reserved_at_40[0x20]; 7757 7758 u8 reserved_at_60[0x10]; 7759 u8 vxlan_udp_port[0x10]; 7760 }; 7761 7762 struct mlx5_ifc_delete_l2_table_entry_out_bits { 7763 u8 status[0x8]; 7764 u8 reserved_at_8[0x18]; 7765 7766 u8 syndrome[0x20]; 7767 7768 u8 reserved_at_40[0x40]; 7769 }; 7770 7771 struct mlx5_ifc_delete_l2_table_entry_in_bits { 7772 u8 opcode[0x10]; 7773 u8 reserved_at_10[0x10]; 7774 7775 u8 reserved_at_20[0x10]; 7776 u8 op_mod[0x10]; 7777 7778 u8 reserved_at_40[0x60]; 7779 7780 u8 reserved_at_a0[0x8]; 7781 u8 table_index[0x18]; 7782 7783 u8 reserved_at_c0[0x140]; 7784 }; 7785 7786 struct mlx5_ifc_delete_fte_out_bits { 7787 u8 status[0x8]; 7788 u8 reserved_at_8[0x18]; 7789 7790 u8 syndrome[0x20]; 7791 7792 u8 reserved_at_40[0x40]; 7793 }; 7794 7795 struct mlx5_ifc_delete_fte_in_bits { 7796 u8 opcode[0x10]; 7797 u8 reserved_at_10[0x10]; 7798 7799 u8 reserved_at_20[0x10]; 7800 u8 op_mod[0x10]; 7801 7802 u8 other_vport[0x1]; 7803 u8 reserved_at_41[0xf]; 7804 u8 vport_number[0x10]; 7805 7806 u8 reserved_at_60[0x20]; 7807 7808 u8 table_type[0x8]; 7809 u8 reserved_at_88[0x18]; 7810 7811 u8 reserved_at_a0[0x8]; 7812 u8 table_id[0x18]; 7813 7814 u8 reserved_at_c0[0x40]; 7815 7816 u8 flow_index[0x20]; 7817 7818 u8 reserved_at_120[0xe0]; 7819 }; 7820 7821 struct mlx5_ifc_dealloc_xrcd_out_bits { 7822 u8 status[0x8]; 7823 u8 reserved_at_8[0x18]; 7824 7825 u8 syndrome[0x20]; 7826 7827 u8 reserved_at_40[0x40]; 7828 }; 7829 7830 struct mlx5_ifc_dealloc_xrcd_in_bits { 7831 u8 opcode[0x10]; 7832 u8 uid[0x10]; 7833 7834 u8 reserved_at_20[0x10]; 7835 u8 op_mod[0x10]; 7836 7837 u8 reserved_at_40[0x8]; 7838 u8 xrcd[0x18]; 7839 7840 u8 reserved_at_60[0x20]; 7841 }; 7842 7843 struct mlx5_ifc_dealloc_uar_out_bits { 7844 u8 status[0x8]; 7845 u8 reserved_at_8[0x18]; 7846 7847 u8 syndrome[0x20]; 7848 7849 u8 reserved_at_40[0x40]; 7850 }; 7851 7852 struct mlx5_ifc_dealloc_uar_in_bits { 7853 u8 opcode[0x10]; 7854 u8 reserved_at_10[0x10]; 7855 7856 u8 reserved_at_20[0x10]; 7857 u8 op_mod[0x10]; 7858 7859 u8 reserved_at_40[0x8]; 7860 u8 uar[0x18]; 7861 7862 u8 reserved_at_60[0x20]; 7863 }; 7864 7865 struct mlx5_ifc_dealloc_transport_domain_out_bits { 7866 u8 status[0x8]; 7867 u8 reserved_at_8[0x18]; 7868 7869 u8 syndrome[0x20]; 7870 7871 u8 reserved_at_40[0x40]; 7872 }; 7873 7874 struct mlx5_ifc_dealloc_transport_domain_in_bits { 7875 u8 opcode[0x10]; 7876 u8 uid[0x10]; 7877 7878 u8 reserved_at_20[0x10]; 7879 u8 op_mod[0x10]; 7880 7881 u8 reserved_at_40[0x8]; 7882 u8 transport_domain[0x18]; 7883 7884 u8 reserved_at_60[0x20]; 7885 }; 7886 7887 struct mlx5_ifc_dealloc_q_counter_out_bits { 7888 u8 status[0x8]; 7889 u8 reserved_at_8[0x18]; 7890 7891 u8 syndrome[0x20]; 7892 7893 u8 reserved_at_40[0x40]; 7894 }; 7895 7896 struct mlx5_ifc_dealloc_q_counter_in_bits { 7897 u8 opcode[0x10]; 7898 u8 reserved_at_10[0x10]; 7899 7900 u8 reserved_at_20[0x10]; 7901 u8 op_mod[0x10]; 7902 7903 u8 reserved_at_40[0x18]; 7904 u8 counter_set_id[0x8]; 7905 7906 u8 reserved_at_60[0x20]; 7907 }; 7908 7909 struct mlx5_ifc_dealloc_pd_out_bits { 7910 u8 status[0x8]; 7911 u8 reserved_at_8[0x18]; 7912 7913 u8 syndrome[0x20]; 7914 7915 u8 reserved_at_40[0x40]; 7916 }; 7917 7918 struct mlx5_ifc_dealloc_pd_in_bits { 7919 u8 opcode[0x10]; 7920 u8 uid[0x10]; 7921 7922 u8 reserved_at_20[0x10]; 7923 u8 op_mod[0x10]; 7924 7925 u8 reserved_at_40[0x8]; 7926 u8 pd[0x18]; 7927 7928 u8 reserved_at_60[0x20]; 7929 }; 7930 7931 struct mlx5_ifc_dealloc_flow_counter_out_bits { 7932 u8 status[0x8]; 7933 u8 reserved_at_8[0x18]; 7934 7935 u8 syndrome[0x20]; 7936 7937 u8 reserved_at_40[0x40]; 7938 }; 7939 7940 struct mlx5_ifc_dealloc_flow_counter_in_bits { 7941 u8 opcode[0x10]; 7942 u8 reserved_at_10[0x10]; 7943 7944 u8 reserved_at_20[0x10]; 7945 u8 op_mod[0x10]; 7946 7947 u8 flow_counter_id[0x20]; 7948 7949 u8 reserved_at_60[0x20]; 7950 }; 7951 7952 struct mlx5_ifc_create_xrq_out_bits { 7953 u8 status[0x8]; 7954 u8 reserved_at_8[0x18]; 7955 7956 u8 syndrome[0x20]; 7957 7958 u8 reserved_at_40[0x8]; 7959 u8 xrqn[0x18]; 7960 7961 u8 reserved_at_60[0x20]; 7962 }; 7963 7964 struct mlx5_ifc_create_xrq_in_bits { 7965 u8 opcode[0x10]; 7966 u8 uid[0x10]; 7967 7968 u8 reserved_at_20[0x10]; 7969 u8 op_mod[0x10]; 7970 7971 u8 reserved_at_40[0x40]; 7972 7973 struct mlx5_ifc_xrqc_bits xrq_context; 7974 }; 7975 7976 struct mlx5_ifc_create_xrc_srq_out_bits { 7977 u8 status[0x8]; 7978 u8 reserved_at_8[0x18]; 7979 7980 u8 syndrome[0x20]; 7981 7982 u8 reserved_at_40[0x8]; 7983 u8 xrc_srqn[0x18]; 7984 7985 u8 reserved_at_60[0x20]; 7986 }; 7987 7988 struct mlx5_ifc_create_xrc_srq_in_bits { 7989 u8 opcode[0x10]; 7990 u8 uid[0x10]; 7991 7992 u8 reserved_at_20[0x10]; 7993 u8 op_mod[0x10]; 7994 7995 u8 reserved_at_40[0x40]; 7996 7997 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 7998 7999 u8 reserved_at_280[0x60]; 8000 8001 u8 xrc_srq_umem_valid[0x1]; 8002 u8 reserved_at_2e1[0x1f]; 8003 8004 u8 reserved_at_300[0x580]; 8005 8006 u8 pas[][0x40]; 8007 }; 8008 8009 struct mlx5_ifc_create_tis_out_bits { 8010 u8 status[0x8]; 8011 u8 reserved_at_8[0x18]; 8012 8013 u8 syndrome[0x20]; 8014 8015 u8 reserved_at_40[0x8]; 8016 u8 tisn[0x18]; 8017 8018 u8 reserved_at_60[0x20]; 8019 }; 8020 8021 struct mlx5_ifc_create_tis_in_bits { 8022 u8 opcode[0x10]; 8023 u8 uid[0x10]; 8024 8025 u8 reserved_at_20[0x10]; 8026 u8 op_mod[0x10]; 8027 8028 u8 reserved_at_40[0xc0]; 8029 8030 struct mlx5_ifc_tisc_bits ctx; 8031 }; 8032 8033 struct mlx5_ifc_create_tir_out_bits { 8034 u8 status[0x8]; 8035 u8 icm_address_63_40[0x18]; 8036 8037 u8 syndrome[0x20]; 8038 8039 u8 icm_address_39_32[0x8]; 8040 u8 tirn[0x18]; 8041 8042 u8 icm_address_31_0[0x20]; 8043 }; 8044 8045 struct mlx5_ifc_create_tir_in_bits { 8046 u8 opcode[0x10]; 8047 u8 uid[0x10]; 8048 8049 u8 reserved_at_20[0x10]; 8050 u8 op_mod[0x10]; 8051 8052 u8 reserved_at_40[0xc0]; 8053 8054 struct mlx5_ifc_tirc_bits ctx; 8055 }; 8056 8057 struct mlx5_ifc_create_srq_out_bits { 8058 u8 status[0x8]; 8059 u8 reserved_at_8[0x18]; 8060 8061 u8 syndrome[0x20]; 8062 8063 u8 reserved_at_40[0x8]; 8064 u8 srqn[0x18]; 8065 8066 u8 reserved_at_60[0x20]; 8067 }; 8068 8069 struct mlx5_ifc_create_srq_in_bits { 8070 u8 opcode[0x10]; 8071 u8 uid[0x10]; 8072 8073 u8 reserved_at_20[0x10]; 8074 u8 op_mod[0x10]; 8075 8076 u8 reserved_at_40[0x40]; 8077 8078 struct mlx5_ifc_srqc_bits srq_context_entry; 8079 8080 u8 reserved_at_280[0x600]; 8081 8082 u8 pas[][0x40]; 8083 }; 8084 8085 struct mlx5_ifc_create_sq_out_bits { 8086 u8 status[0x8]; 8087 u8 reserved_at_8[0x18]; 8088 8089 u8 syndrome[0x20]; 8090 8091 u8 reserved_at_40[0x8]; 8092 u8 sqn[0x18]; 8093 8094 u8 reserved_at_60[0x20]; 8095 }; 8096 8097 struct mlx5_ifc_create_sq_in_bits { 8098 u8 opcode[0x10]; 8099 u8 uid[0x10]; 8100 8101 u8 reserved_at_20[0x10]; 8102 u8 op_mod[0x10]; 8103 8104 u8 reserved_at_40[0xc0]; 8105 8106 struct mlx5_ifc_sqc_bits ctx; 8107 }; 8108 8109 struct mlx5_ifc_create_scheduling_element_out_bits { 8110 u8 status[0x8]; 8111 u8 reserved_at_8[0x18]; 8112 8113 u8 syndrome[0x20]; 8114 8115 u8 reserved_at_40[0x40]; 8116 8117 u8 scheduling_element_id[0x20]; 8118 8119 u8 reserved_at_a0[0x160]; 8120 }; 8121 8122 struct mlx5_ifc_create_scheduling_element_in_bits { 8123 u8 opcode[0x10]; 8124 u8 reserved_at_10[0x10]; 8125 8126 u8 reserved_at_20[0x10]; 8127 u8 op_mod[0x10]; 8128 8129 u8 scheduling_hierarchy[0x8]; 8130 u8 reserved_at_48[0x18]; 8131 8132 u8 reserved_at_60[0xa0]; 8133 8134 struct mlx5_ifc_scheduling_context_bits scheduling_context; 8135 8136 u8 reserved_at_300[0x100]; 8137 }; 8138 8139 struct mlx5_ifc_create_rqt_out_bits { 8140 u8 status[0x8]; 8141 u8 reserved_at_8[0x18]; 8142 8143 u8 syndrome[0x20]; 8144 8145 u8 reserved_at_40[0x8]; 8146 u8 rqtn[0x18]; 8147 8148 u8 reserved_at_60[0x20]; 8149 }; 8150 8151 struct mlx5_ifc_create_rqt_in_bits { 8152 u8 opcode[0x10]; 8153 u8 uid[0x10]; 8154 8155 u8 reserved_at_20[0x10]; 8156 u8 op_mod[0x10]; 8157 8158 u8 reserved_at_40[0xc0]; 8159 8160 struct mlx5_ifc_rqtc_bits rqt_context; 8161 }; 8162 8163 struct mlx5_ifc_create_rq_out_bits { 8164 u8 status[0x8]; 8165 u8 reserved_at_8[0x18]; 8166 8167 u8 syndrome[0x20]; 8168 8169 u8 reserved_at_40[0x8]; 8170 u8 rqn[0x18]; 8171 8172 u8 reserved_at_60[0x20]; 8173 }; 8174 8175 struct mlx5_ifc_create_rq_in_bits { 8176 u8 opcode[0x10]; 8177 u8 uid[0x10]; 8178 8179 u8 reserved_at_20[0x10]; 8180 u8 op_mod[0x10]; 8181 8182 u8 reserved_at_40[0xc0]; 8183 8184 struct mlx5_ifc_rqc_bits ctx; 8185 }; 8186 8187 struct mlx5_ifc_create_rmp_out_bits { 8188 u8 status[0x8]; 8189 u8 reserved_at_8[0x18]; 8190 8191 u8 syndrome[0x20]; 8192 8193 u8 reserved_at_40[0x8]; 8194 u8 rmpn[0x18]; 8195 8196 u8 reserved_at_60[0x20]; 8197 }; 8198 8199 struct mlx5_ifc_create_rmp_in_bits { 8200 u8 opcode[0x10]; 8201 u8 uid[0x10]; 8202 8203 u8 reserved_at_20[0x10]; 8204 u8 op_mod[0x10]; 8205 8206 u8 reserved_at_40[0xc0]; 8207 8208 struct mlx5_ifc_rmpc_bits ctx; 8209 }; 8210 8211 struct mlx5_ifc_create_qp_out_bits { 8212 u8 status[0x8]; 8213 u8 reserved_at_8[0x18]; 8214 8215 u8 syndrome[0x20]; 8216 8217 u8 reserved_at_40[0x8]; 8218 u8 qpn[0x18]; 8219 8220 u8 ece[0x20]; 8221 }; 8222 8223 struct mlx5_ifc_create_qp_in_bits { 8224 u8 opcode[0x10]; 8225 u8 uid[0x10]; 8226 8227 u8 reserved_at_20[0x10]; 8228 u8 op_mod[0x10]; 8229 8230 u8 reserved_at_40[0x8]; 8231 u8 input_qpn[0x18]; 8232 8233 u8 reserved_at_60[0x20]; 8234 u8 opt_param_mask[0x20]; 8235 8236 u8 ece[0x20]; 8237 8238 struct mlx5_ifc_qpc_bits qpc; 8239 8240 u8 reserved_at_800[0x60]; 8241 8242 u8 wq_umem_valid[0x1]; 8243 u8 reserved_at_861[0x1f]; 8244 8245 u8 pas[][0x40]; 8246 }; 8247 8248 struct mlx5_ifc_create_psv_out_bits { 8249 u8 status[0x8]; 8250 u8 reserved_at_8[0x18]; 8251 8252 u8 syndrome[0x20]; 8253 8254 u8 reserved_at_40[0x40]; 8255 8256 u8 reserved_at_80[0x8]; 8257 u8 psv0_index[0x18]; 8258 8259 u8 reserved_at_a0[0x8]; 8260 u8 psv1_index[0x18]; 8261 8262 u8 reserved_at_c0[0x8]; 8263 u8 psv2_index[0x18]; 8264 8265 u8 reserved_at_e0[0x8]; 8266 u8 psv3_index[0x18]; 8267 }; 8268 8269 struct mlx5_ifc_create_psv_in_bits { 8270 u8 opcode[0x10]; 8271 u8 reserved_at_10[0x10]; 8272 8273 u8 reserved_at_20[0x10]; 8274 u8 op_mod[0x10]; 8275 8276 u8 num_psv[0x4]; 8277 u8 reserved_at_44[0x4]; 8278 u8 pd[0x18]; 8279 8280 u8 reserved_at_60[0x20]; 8281 }; 8282 8283 struct mlx5_ifc_create_mkey_out_bits { 8284 u8 status[0x8]; 8285 u8 reserved_at_8[0x18]; 8286 8287 u8 syndrome[0x20]; 8288 8289 u8 reserved_at_40[0x8]; 8290 u8 mkey_index[0x18]; 8291 8292 u8 reserved_at_60[0x20]; 8293 }; 8294 8295 struct mlx5_ifc_create_mkey_in_bits { 8296 u8 opcode[0x10]; 8297 u8 uid[0x10]; 8298 8299 u8 reserved_at_20[0x10]; 8300 u8 op_mod[0x10]; 8301 8302 u8 reserved_at_40[0x20]; 8303 8304 u8 pg_access[0x1]; 8305 u8 mkey_umem_valid[0x1]; 8306 u8 reserved_at_62[0x1e]; 8307 8308 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 8309 8310 u8 reserved_at_280[0x80]; 8311 8312 u8 translations_octword_actual_size[0x20]; 8313 8314 u8 reserved_at_320[0x560]; 8315 8316 u8 klm_pas_mtt[][0x20]; 8317 }; 8318 8319 enum { 8320 MLX5_FLOW_TABLE_TYPE_NIC_RX = 0x0, 8321 MLX5_FLOW_TABLE_TYPE_NIC_TX = 0x1, 8322 MLX5_FLOW_TABLE_TYPE_ESW_EGRESS_ACL = 0x2, 8323 MLX5_FLOW_TABLE_TYPE_ESW_INGRESS_ACL = 0x3, 8324 MLX5_FLOW_TABLE_TYPE_FDB = 0X4, 8325 MLX5_FLOW_TABLE_TYPE_SNIFFER_RX = 0X5, 8326 MLX5_FLOW_TABLE_TYPE_SNIFFER_TX = 0X6, 8327 }; 8328 8329 struct mlx5_ifc_create_flow_table_out_bits { 8330 u8 status[0x8]; 8331 u8 icm_address_63_40[0x18]; 8332 8333 u8 syndrome[0x20]; 8334 8335 u8 icm_address_39_32[0x8]; 8336 u8 table_id[0x18]; 8337 8338 u8 icm_address_31_0[0x20]; 8339 }; 8340 8341 struct mlx5_ifc_create_flow_table_in_bits { 8342 u8 opcode[0x10]; 8343 u8 reserved_at_10[0x10]; 8344 8345 u8 reserved_at_20[0x10]; 8346 u8 op_mod[0x10]; 8347 8348 u8 other_vport[0x1]; 8349 u8 reserved_at_41[0xf]; 8350 u8 vport_number[0x10]; 8351 8352 u8 reserved_at_60[0x20]; 8353 8354 u8 table_type[0x8]; 8355 u8 reserved_at_88[0x18]; 8356 8357 u8 reserved_at_a0[0x20]; 8358 8359 struct mlx5_ifc_flow_table_context_bits flow_table_context; 8360 }; 8361 8362 struct mlx5_ifc_create_flow_group_out_bits { 8363 u8 status[0x8]; 8364 u8 reserved_at_8[0x18]; 8365 8366 u8 syndrome[0x20]; 8367 8368 u8 reserved_at_40[0x8]; 8369 u8 group_id[0x18]; 8370 8371 u8 reserved_at_60[0x20]; 8372 }; 8373 8374 enum { 8375 MLX5_CREATE_FLOW_GROUP_IN_GROUP_TYPE_TCAM_SUBTABLE = 0x0, 8376 MLX5_CREATE_FLOW_GROUP_IN_GROUP_TYPE_HASH_SPLIT = 0x1, 8377 }; 8378 8379 enum { 8380 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 8381 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 8382 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 8383 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3, 8384 }; 8385 8386 struct mlx5_ifc_create_flow_group_in_bits { 8387 u8 opcode[0x10]; 8388 u8 reserved_at_10[0x10]; 8389 8390 u8 reserved_at_20[0x10]; 8391 u8 op_mod[0x10]; 8392 8393 u8 other_vport[0x1]; 8394 u8 reserved_at_41[0xf]; 8395 u8 vport_number[0x10]; 8396 8397 u8 reserved_at_60[0x20]; 8398 8399 u8 table_type[0x8]; 8400 u8 reserved_at_88[0x4]; 8401 u8 group_type[0x4]; 8402 u8 reserved_at_90[0x10]; 8403 8404 u8 reserved_at_a0[0x8]; 8405 u8 table_id[0x18]; 8406 8407 u8 source_eswitch_owner_vhca_id_valid[0x1]; 8408 8409 u8 reserved_at_c1[0x1f]; 8410 8411 u8 start_flow_index[0x20]; 8412 8413 u8 reserved_at_100[0x20]; 8414 8415 u8 end_flow_index[0x20]; 8416 8417 u8 reserved_at_140[0x10]; 8418 u8 match_definer_id[0x10]; 8419 8420 u8 reserved_at_160[0x80]; 8421 8422 u8 reserved_at_1e0[0x18]; 8423 u8 match_criteria_enable[0x8]; 8424 8425 struct mlx5_ifc_fte_match_param_bits match_criteria; 8426 8427 u8 reserved_at_1200[0xe00]; 8428 }; 8429 8430 struct mlx5_ifc_create_eq_out_bits { 8431 u8 status[0x8]; 8432 u8 reserved_at_8[0x18]; 8433 8434 u8 syndrome[0x20]; 8435 8436 u8 reserved_at_40[0x18]; 8437 u8 eq_number[0x8]; 8438 8439 u8 reserved_at_60[0x20]; 8440 }; 8441 8442 struct mlx5_ifc_create_eq_in_bits { 8443 u8 opcode[0x10]; 8444 u8 uid[0x10]; 8445 8446 u8 reserved_at_20[0x10]; 8447 u8 op_mod[0x10]; 8448 8449 u8 reserved_at_40[0x40]; 8450 8451 struct mlx5_ifc_eqc_bits eq_context_entry; 8452 8453 u8 reserved_at_280[0x40]; 8454 8455 u8 event_bitmask[4][0x40]; 8456 8457 u8 reserved_at_3c0[0x4c0]; 8458 8459 u8 pas[][0x40]; 8460 }; 8461 8462 struct mlx5_ifc_create_dct_out_bits { 8463 u8 status[0x8]; 8464 u8 reserved_at_8[0x18]; 8465 8466 u8 syndrome[0x20]; 8467 8468 u8 reserved_at_40[0x8]; 8469 u8 dctn[0x18]; 8470 8471 u8 ece[0x20]; 8472 }; 8473 8474 struct mlx5_ifc_create_dct_in_bits { 8475 u8 opcode[0x10]; 8476 u8 uid[0x10]; 8477 8478 u8 reserved_at_20[0x10]; 8479 u8 op_mod[0x10]; 8480 8481 u8 reserved_at_40[0x40]; 8482 8483 struct mlx5_ifc_dctc_bits dct_context_entry; 8484 8485 u8 reserved_at_280[0x180]; 8486 }; 8487 8488 struct mlx5_ifc_create_cq_out_bits { 8489 u8 status[0x8]; 8490 u8 reserved_at_8[0x18]; 8491 8492 u8 syndrome[0x20]; 8493 8494 u8 reserved_at_40[0x8]; 8495 u8 cqn[0x18]; 8496 8497 u8 reserved_at_60[0x20]; 8498 }; 8499 8500 struct mlx5_ifc_create_cq_in_bits { 8501 u8 opcode[0x10]; 8502 u8 uid[0x10]; 8503 8504 u8 reserved_at_20[0x10]; 8505 u8 op_mod[0x10]; 8506 8507 u8 reserved_at_40[0x40]; 8508 8509 struct mlx5_ifc_cqc_bits cq_context; 8510 8511 u8 reserved_at_280[0x60]; 8512 8513 u8 cq_umem_valid[0x1]; 8514 u8 reserved_at_2e1[0x59f]; 8515 8516 u8 pas[][0x40]; 8517 }; 8518 8519 struct mlx5_ifc_config_int_moderation_out_bits { 8520 u8 status[0x8]; 8521 u8 reserved_at_8[0x18]; 8522 8523 u8 syndrome[0x20]; 8524 8525 u8 reserved_at_40[0x4]; 8526 u8 min_delay[0xc]; 8527 u8 int_vector[0x10]; 8528 8529 u8 reserved_at_60[0x20]; 8530 }; 8531 8532 enum { 8533 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0, 8534 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1, 8535 }; 8536 8537 struct mlx5_ifc_config_int_moderation_in_bits { 8538 u8 opcode[0x10]; 8539 u8 reserved_at_10[0x10]; 8540 8541 u8 reserved_at_20[0x10]; 8542 u8 op_mod[0x10]; 8543 8544 u8 reserved_at_40[0x4]; 8545 u8 min_delay[0xc]; 8546 u8 int_vector[0x10]; 8547 8548 u8 reserved_at_60[0x20]; 8549 }; 8550 8551 struct mlx5_ifc_attach_to_mcg_out_bits { 8552 u8 status[0x8]; 8553 u8 reserved_at_8[0x18]; 8554 8555 u8 syndrome[0x20]; 8556 8557 u8 reserved_at_40[0x40]; 8558 }; 8559 8560 struct mlx5_ifc_attach_to_mcg_in_bits { 8561 u8 opcode[0x10]; 8562 u8 uid[0x10]; 8563 8564 u8 reserved_at_20[0x10]; 8565 u8 op_mod[0x10]; 8566 8567 u8 reserved_at_40[0x8]; 8568 u8 qpn[0x18]; 8569 8570 u8 reserved_at_60[0x20]; 8571 8572 u8 multicast_gid[16][0x8]; 8573 }; 8574 8575 struct mlx5_ifc_arm_xrq_out_bits { 8576 u8 status[0x8]; 8577 u8 reserved_at_8[0x18]; 8578 8579 u8 syndrome[0x20]; 8580 8581 u8 reserved_at_40[0x40]; 8582 }; 8583 8584 struct mlx5_ifc_arm_xrq_in_bits { 8585 u8 opcode[0x10]; 8586 u8 reserved_at_10[0x10]; 8587 8588 u8 reserved_at_20[0x10]; 8589 u8 op_mod[0x10]; 8590 8591 u8 reserved_at_40[0x8]; 8592 u8 xrqn[0x18]; 8593 8594 u8 reserved_at_60[0x10]; 8595 u8 lwm[0x10]; 8596 }; 8597 8598 struct mlx5_ifc_arm_xrc_srq_out_bits { 8599 u8 status[0x8]; 8600 u8 reserved_at_8[0x18]; 8601 8602 u8 syndrome[0x20]; 8603 8604 u8 reserved_at_40[0x40]; 8605 }; 8606 8607 enum { 8608 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1, 8609 }; 8610 8611 struct mlx5_ifc_arm_xrc_srq_in_bits { 8612 u8 opcode[0x10]; 8613 u8 uid[0x10]; 8614 8615 u8 reserved_at_20[0x10]; 8616 u8 op_mod[0x10]; 8617 8618 u8 reserved_at_40[0x8]; 8619 u8 xrc_srqn[0x18]; 8620 8621 u8 reserved_at_60[0x10]; 8622 u8 lwm[0x10]; 8623 }; 8624 8625 struct mlx5_ifc_arm_rq_out_bits { 8626 u8 status[0x8]; 8627 u8 reserved_at_8[0x18]; 8628 8629 u8 syndrome[0x20]; 8630 8631 u8 reserved_at_40[0x40]; 8632 }; 8633 8634 enum { 8635 MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1, 8636 MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2, 8637 }; 8638 8639 struct mlx5_ifc_arm_rq_in_bits { 8640 u8 opcode[0x10]; 8641 u8 uid[0x10]; 8642 8643 u8 reserved_at_20[0x10]; 8644 u8 op_mod[0x10]; 8645 8646 u8 reserved_at_40[0x8]; 8647 u8 srq_number[0x18]; 8648 8649 u8 reserved_at_60[0x10]; 8650 u8 lwm[0x10]; 8651 }; 8652 8653 struct mlx5_ifc_arm_dct_out_bits { 8654 u8 status[0x8]; 8655 u8 reserved_at_8[0x18]; 8656 8657 u8 syndrome[0x20]; 8658 8659 u8 reserved_at_40[0x40]; 8660 }; 8661 8662 struct mlx5_ifc_arm_dct_in_bits { 8663 u8 opcode[0x10]; 8664 u8 reserved_at_10[0x10]; 8665 8666 u8 reserved_at_20[0x10]; 8667 u8 op_mod[0x10]; 8668 8669 u8 reserved_at_40[0x8]; 8670 u8 dct_number[0x18]; 8671 8672 u8 reserved_at_60[0x20]; 8673 }; 8674 8675 struct mlx5_ifc_alloc_xrcd_out_bits { 8676 u8 status[0x8]; 8677 u8 reserved_at_8[0x18]; 8678 8679 u8 syndrome[0x20]; 8680 8681 u8 reserved_at_40[0x8]; 8682 u8 xrcd[0x18]; 8683 8684 u8 reserved_at_60[0x20]; 8685 }; 8686 8687 struct mlx5_ifc_alloc_xrcd_in_bits { 8688 u8 opcode[0x10]; 8689 u8 uid[0x10]; 8690 8691 u8 reserved_at_20[0x10]; 8692 u8 op_mod[0x10]; 8693 8694 u8 reserved_at_40[0x40]; 8695 }; 8696 8697 struct mlx5_ifc_alloc_uar_out_bits { 8698 u8 status[0x8]; 8699 u8 reserved_at_8[0x18]; 8700 8701 u8 syndrome[0x20]; 8702 8703 u8 reserved_at_40[0x8]; 8704 u8 uar[0x18]; 8705 8706 u8 reserved_at_60[0x20]; 8707 }; 8708 8709 struct mlx5_ifc_alloc_uar_in_bits { 8710 u8 opcode[0x10]; 8711 u8 reserved_at_10[0x10]; 8712 8713 u8 reserved_at_20[0x10]; 8714 u8 op_mod[0x10]; 8715 8716 u8 reserved_at_40[0x40]; 8717 }; 8718 8719 struct mlx5_ifc_alloc_transport_domain_out_bits { 8720 u8 status[0x8]; 8721 u8 reserved_at_8[0x18]; 8722 8723 u8 syndrome[0x20]; 8724 8725 u8 reserved_at_40[0x8]; 8726 u8 transport_domain[0x18]; 8727 8728 u8 reserved_at_60[0x20]; 8729 }; 8730 8731 struct mlx5_ifc_alloc_transport_domain_in_bits { 8732 u8 opcode[0x10]; 8733 u8 uid[0x10]; 8734 8735 u8 reserved_at_20[0x10]; 8736 u8 op_mod[0x10]; 8737 8738 u8 reserved_at_40[0x40]; 8739 }; 8740 8741 struct mlx5_ifc_alloc_q_counter_out_bits { 8742 u8 status[0x8]; 8743 u8 reserved_at_8[0x18]; 8744 8745 u8 syndrome[0x20]; 8746 8747 u8 reserved_at_40[0x18]; 8748 u8 counter_set_id[0x8]; 8749 8750 u8 reserved_at_60[0x20]; 8751 }; 8752 8753 struct mlx5_ifc_alloc_q_counter_in_bits { 8754 u8 opcode[0x10]; 8755 u8 uid[0x10]; 8756 8757 u8 reserved_at_20[0x10]; 8758 u8 op_mod[0x10]; 8759 8760 u8 reserved_at_40[0x40]; 8761 }; 8762 8763 struct mlx5_ifc_alloc_pd_out_bits { 8764 u8 status[0x8]; 8765 u8 reserved_at_8[0x18]; 8766 8767 u8 syndrome[0x20]; 8768 8769 u8 reserved_at_40[0x8]; 8770 u8 pd[0x18]; 8771 8772 u8 reserved_at_60[0x20]; 8773 }; 8774 8775 struct mlx5_ifc_alloc_pd_in_bits { 8776 u8 opcode[0x10]; 8777 u8 uid[0x10]; 8778 8779 u8 reserved_at_20[0x10]; 8780 u8 op_mod[0x10]; 8781 8782 u8 reserved_at_40[0x40]; 8783 }; 8784 8785 struct mlx5_ifc_alloc_flow_counter_out_bits { 8786 u8 status[0x8]; 8787 u8 reserved_at_8[0x18]; 8788 8789 u8 syndrome[0x20]; 8790 8791 u8 flow_counter_id[0x20]; 8792 8793 u8 reserved_at_60[0x20]; 8794 }; 8795 8796 struct mlx5_ifc_alloc_flow_counter_in_bits { 8797 u8 opcode[0x10]; 8798 u8 reserved_at_10[0x10]; 8799 8800 u8 reserved_at_20[0x10]; 8801 u8 op_mod[0x10]; 8802 8803 u8 reserved_at_40[0x38]; 8804 u8 flow_counter_bulk[0x8]; 8805 }; 8806 8807 struct mlx5_ifc_add_vxlan_udp_dport_out_bits { 8808 u8 status[0x8]; 8809 u8 reserved_at_8[0x18]; 8810 8811 u8 syndrome[0x20]; 8812 8813 u8 reserved_at_40[0x40]; 8814 }; 8815 8816 struct mlx5_ifc_add_vxlan_udp_dport_in_bits { 8817 u8 opcode[0x10]; 8818 u8 reserved_at_10[0x10]; 8819 8820 u8 reserved_at_20[0x10]; 8821 u8 op_mod[0x10]; 8822 8823 u8 reserved_at_40[0x20]; 8824 8825 u8 reserved_at_60[0x10]; 8826 u8 vxlan_udp_port[0x10]; 8827 }; 8828 8829 struct mlx5_ifc_set_pp_rate_limit_out_bits { 8830 u8 status[0x8]; 8831 u8 reserved_at_8[0x18]; 8832 8833 u8 syndrome[0x20]; 8834 8835 u8 reserved_at_40[0x40]; 8836 }; 8837 8838 struct mlx5_ifc_set_pp_rate_limit_context_bits { 8839 u8 rate_limit[0x20]; 8840 8841 u8 burst_upper_bound[0x20]; 8842 8843 u8 reserved_at_40[0x10]; 8844 u8 typical_packet_size[0x10]; 8845 8846 u8 reserved_at_60[0x120]; 8847 }; 8848 8849 struct mlx5_ifc_set_pp_rate_limit_in_bits { 8850 u8 opcode[0x10]; 8851 u8 uid[0x10]; 8852 8853 u8 reserved_at_20[0x10]; 8854 u8 op_mod[0x10]; 8855 8856 u8 reserved_at_40[0x10]; 8857 u8 rate_limit_index[0x10]; 8858 8859 u8 reserved_at_60[0x20]; 8860 8861 struct mlx5_ifc_set_pp_rate_limit_context_bits ctx; 8862 }; 8863 8864 struct mlx5_ifc_access_register_out_bits { 8865 u8 status[0x8]; 8866 u8 reserved_at_8[0x18]; 8867 8868 u8 syndrome[0x20]; 8869 8870 u8 reserved_at_40[0x40]; 8871 8872 u8 register_data[][0x20]; 8873 }; 8874 8875 enum { 8876 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0, 8877 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1, 8878 }; 8879 8880 struct mlx5_ifc_access_register_in_bits { 8881 u8 opcode[0x10]; 8882 u8 reserved_at_10[0x10]; 8883 8884 u8 reserved_at_20[0x10]; 8885 u8 op_mod[0x10]; 8886 8887 u8 reserved_at_40[0x10]; 8888 u8 register_id[0x10]; 8889 8890 u8 argument[0x20]; 8891 8892 u8 register_data[][0x20]; 8893 }; 8894 8895 struct mlx5_ifc_sltp_reg_bits { 8896 u8 status[0x4]; 8897 u8 version[0x4]; 8898 u8 local_port[0x8]; 8899 u8 pnat[0x2]; 8900 u8 reserved_at_12[0x2]; 8901 u8 lane[0x4]; 8902 u8 reserved_at_18[0x8]; 8903 8904 u8 reserved_at_20[0x20]; 8905 8906 u8 reserved_at_40[0x7]; 8907 u8 polarity[0x1]; 8908 u8 ob_tap0[0x8]; 8909 u8 ob_tap1[0x8]; 8910 u8 ob_tap2[0x8]; 8911 8912 u8 reserved_at_60[0xc]; 8913 u8 ob_preemp_mode[0x4]; 8914 u8 ob_reg[0x8]; 8915 u8 ob_bias[0x8]; 8916 8917 u8 reserved_at_80[0x20]; 8918 }; 8919 8920 struct mlx5_ifc_slrg_reg_bits { 8921 u8 status[0x4]; 8922 u8 version[0x4]; 8923 u8 local_port[0x8]; 8924 u8 pnat[0x2]; 8925 u8 reserved_at_12[0x2]; 8926 u8 lane[0x4]; 8927 u8 reserved_at_18[0x8]; 8928 8929 u8 time_to_link_up[0x10]; 8930 u8 reserved_at_30[0xc]; 8931 u8 grade_lane_speed[0x4]; 8932 8933 u8 grade_version[0x8]; 8934 u8 grade[0x18]; 8935 8936 u8 reserved_at_60[0x4]; 8937 u8 height_grade_type[0x4]; 8938 u8 height_grade[0x18]; 8939 8940 u8 height_dz[0x10]; 8941 u8 height_dv[0x10]; 8942 8943 u8 reserved_at_a0[0x10]; 8944 u8 height_sigma[0x10]; 8945 8946 u8 reserved_at_c0[0x20]; 8947 8948 u8 reserved_at_e0[0x4]; 8949 u8 phase_grade_type[0x4]; 8950 u8 phase_grade[0x18]; 8951 8952 u8 reserved_at_100[0x8]; 8953 u8 phase_eo_pos[0x8]; 8954 u8 reserved_at_110[0x8]; 8955 u8 phase_eo_neg[0x8]; 8956 8957 u8 ffe_set_tested[0x10]; 8958 u8 test_errors_per_lane[0x10]; 8959 }; 8960 8961 struct mlx5_ifc_pvlc_reg_bits { 8962 u8 reserved_at_0[0x8]; 8963 u8 local_port[0x8]; 8964 u8 reserved_at_10[0x10]; 8965 8966 u8 reserved_at_20[0x1c]; 8967 u8 vl_hw_cap[0x4]; 8968 8969 u8 reserved_at_40[0x1c]; 8970 u8 vl_admin[0x4]; 8971 8972 u8 reserved_at_60[0x1c]; 8973 u8 vl_operational[0x4]; 8974 }; 8975 8976 struct mlx5_ifc_pude_reg_bits { 8977 u8 swid[0x8]; 8978 u8 local_port[0x8]; 8979 u8 reserved_at_10[0x4]; 8980 u8 admin_status[0x4]; 8981 u8 reserved_at_18[0x4]; 8982 u8 oper_status[0x4]; 8983 8984 u8 reserved_at_20[0x60]; 8985 }; 8986 8987 struct mlx5_ifc_ptys_reg_bits { 8988 u8 reserved_at_0[0x1]; 8989 u8 an_disable_admin[0x1]; 8990 u8 an_disable_cap[0x1]; 8991 u8 reserved_at_3[0x5]; 8992 u8 local_port[0x8]; 8993 u8 reserved_at_10[0xd]; 8994 u8 proto_mask[0x3]; 8995 8996 u8 an_status[0x4]; 8997 u8 reserved_at_24[0xc]; 8998 u8 data_rate_oper[0x10]; 8999 9000 u8 ext_eth_proto_capability[0x20]; 9001 9002 u8 eth_proto_capability[0x20]; 9003 9004 u8 ib_link_width_capability[0x10]; 9005 u8 ib_proto_capability[0x10]; 9006 9007 u8 ext_eth_proto_admin[0x20]; 9008 9009 u8 eth_proto_admin[0x20]; 9010 9011 u8 ib_link_width_admin[0x10]; 9012 u8 ib_proto_admin[0x10]; 9013 9014 u8 ext_eth_proto_oper[0x20]; 9015 9016 u8 eth_proto_oper[0x20]; 9017 9018 u8 ib_link_width_oper[0x10]; 9019 u8 ib_proto_oper[0x10]; 9020 9021 u8 reserved_at_160[0x1c]; 9022 u8 connector_type[0x4]; 9023 9024 u8 eth_proto_lp_advertise[0x20]; 9025 9026 u8 reserved_at_1a0[0x60]; 9027 }; 9028 9029 struct mlx5_ifc_mlcr_reg_bits { 9030 u8 reserved_at_0[0x8]; 9031 u8 local_port[0x8]; 9032 u8 reserved_at_10[0x20]; 9033 9034 u8 beacon_duration[0x10]; 9035 u8 reserved_at_40[0x10]; 9036 9037 u8 beacon_remain[0x10]; 9038 }; 9039 9040 struct mlx5_ifc_ptas_reg_bits { 9041 u8 reserved_at_0[0x20]; 9042 9043 u8 algorithm_options[0x10]; 9044 u8 reserved_at_30[0x4]; 9045 u8 repetitions_mode[0x4]; 9046 u8 num_of_repetitions[0x8]; 9047 9048 u8 grade_version[0x8]; 9049 u8 height_grade_type[0x4]; 9050 u8 phase_grade_type[0x4]; 9051 u8 height_grade_weight[0x8]; 9052 u8 phase_grade_weight[0x8]; 9053 9054 u8 gisim_measure_bits[0x10]; 9055 u8 adaptive_tap_measure_bits[0x10]; 9056 9057 u8 ber_bath_high_error_threshold[0x10]; 9058 u8 ber_bath_mid_error_threshold[0x10]; 9059 9060 u8 ber_bath_low_error_threshold[0x10]; 9061 u8 one_ratio_high_threshold[0x10]; 9062 9063 u8 one_ratio_high_mid_threshold[0x10]; 9064 u8 one_ratio_low_mid_threshold[0x10]; 9065 9066 u8 one_ratio_low_threshold[0x10]; 9067 u8 ndeo_error_threshold[0x10]; 9068 9069 u8 mixer_offset_step_size[0x10]; 9070 u8 reserved_at_110[0x8]; 9071 u8 mix90_phase_for_voltage_bath[0x8]; 9072 9073 u8 mixer_offset_start[0x10]; 9074 u8 mixer_offset_end[0x10]; 9075 9076 u8 reserved_at_140[0x15]; 9077 u8 ber_test_time[0xb]; 9078 }; 9079 9080 struct mlx5_ifc_pspa_reg_bits { 9081 u8 swid[0x8]; 9082 u8 local_port[0x8]; 9083 u8 sub_port[0x8]; 9084 u8 reserved_at_18[0x8]; 9085 9086 u8 reserved_at_20[0x20]; 9087 }; 9088 9089 struct mlx5_ifc_pqdr_reg_bits { 9090 u8 reserved_at_0[0x8]; 9091 u8 local_port[0x8]; 9092 u8 reserved_at_10[0x5]; 9093 u8 prio[0x3]; 9094 u8 reserved_at_18[0x6]; 9095 u8 mode[0x2]; 9096 9097 u8 reserved_at_20[0x20]; 9098 9099 u8 reserved_at_40[0x10]; 9100 u8 min_threshold[0x10]; 9101 9102 u8 reserved_at_60[0x10]; 9103 u8 max_threshold[0x10]; 9104 9105 u8 reserved_at_80[0x10]; 9106 u8 mark_probability_denominator[0x10]; 9107 9108 u8 reserved_at_a0[0x60]; 9109 }; 9110 9111 struct mlx5_ifc_ppsc_reg_bits { 9112 u8 reserved_at_0[0x8]; 9113 u8 local_port[0x8]; 9114 u8 reserved_at_10[0x10]; 9115 9116 u8 reserved_at_20[0x60]; 9117 9118 u8 reserved_at_80[0x1c]; 9119 u8 wrps_admin[0x4]; 9120 9121 u8 reserved_at_a0[0x1c]; 9122 u8 wrps_status[0x4]; 9123 9124 u8 reserved_at_c0[0x8]; 9125 u8 up_threshold[0x8]; 9126 u8 reserved_at_d0[0x8]; 9127 u8 down_threshold[0x8]; 9128 9129 u8 reserved_at_e0[0x20]; 9130 9131 u8 reserved_at_100[0x1c]; 9132 u8 srps_admin[0x4]; 9133 9134 u8 reserved_at_120[0x1c]; 9135 u8 srps_status[0x4]; 9136 9137 u8 reserved_at_140[0x40]; 9138 }; 9139 9140 struct mlx5_ifc_pplr_reg_bits { 9141 u8 reserved_at_0[0x8]; 9142 u8 local_port[0x8]; 9143 u8 reserved_at_10[0x10]; 9144 9145 u8 reserved_at_20[0x8]; 9146 u8 lb_cap[0x8]; 9147 u8 reserved_at_30[0x8]; 9148 u8 lb_en[0x8]; 9149 }; 9150 9151 struct mlx5_ifc_pplm_reg_bits { 9152 u8 reserved_at_0[0x8]; 9153 u8 local_port[0x8]; 9154 u8 reserved_at_10[0x10]; 9155 9156 u8 reserved_at_20[0x20]; 9157 9158 u8 port_profile_mode[0x8]; 9159 u8 static_port_profile[0x8]; 9160 u8 active_port_profile[0x8]; 9161 u8 reserved_at_58[0x8]; 9162 9163 u8 retransmission_active[0x8]; 9164 u8 fec_mode_active[0x18]; 9165 9166 u8 rs_fec_correction_bypass_cap[0x4]; 9167 u8 reserved_at_84[0x8]; 9168 u8 fec_override_cap_56g[0x4]; 9169 u8 fec_override_cap_100g[0x4]; 9170 u8 fec_override_cap_50g[0x4]; 9171 u8 fec_override_cap_25g[0x4]; 9172 u8 fec_override_cap_10g_40g[0x4]; 9173 9174 u8 rs_fec_correction_bypass_admin[0x4]; 9175 u8 reserved_at_a4[0x8]; 9176 u8 fec_override_admin_56g[0x4]; 9177 u8 fec_override_admin_100g[0x4]; 9178 u8 fec_override_admin_50g[0x4]; 9179 u8 fec_override_admin_25g[0x4]; 9180 u8 fec_override_admin_10g_40g[0x4]; 9181 9182 u8 fec_override_cap_400g_8x[0x10]; 9183 u8 fec_override_cap_200g_4x[0x10]; 9184 9185 u8 fec_override_cap_100g_2x[0x10]; 9186 u8 fec_override_cap_50g_1x[0x10]; 9187 9188 u8 fec_override_admin_400g_8x[0x10]; 9189 u8 fec_override_admin_200g_4x[0x10]; 9190 9191 u8 fec_override_admin_100g_2x[0x10]; 9192 u8 fec_override_admin_50g_1x[0x10]; 9193 9194 u8 reserved_at_140[0x140]; 9195 }; 9196 9197 struct mlx5_ifc_ppcnt_reg_bits { 9198 u8 swid[0x8]; 9199 u8 local_port[0x8]; 9200 u8 pnat[0x2]; 9201 u8 reserved_at_12[0x8]; 9202 u8 grp[0x6]; 9203 9204 u8 clr[0x1]; 9205 u8 reserved_at_21[0x1c]; 9206 u8 prio_tc[0x3]; 9207 9208 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set; 9209 }; 9210 9211 struct mlx5_ifc_mpein_reg_bits { 9212 u8 reserved_at_0[0x2]; 9213 u8 depth[0x6]; 9214 u8 pcie_index[0x8]; 9215 u8 node[0x8]; 9216 u8 reserved_at_18[0x8]; 9217 9218 u8 capability_mask[0x20]; 9219 9220 u8 reserved_at_40[0x8]; 9221 u8 link_width_enabled[0x8]; 9222 u8 link_speed_enabled[0x10]; 9223 9224 u8 lane0_physical_position[0x8]; 9225 u8 link_width_active[0x8]; 9226 u8 link_speed_active[0x10]; 9227 9228 u8 num_of_pfs[0x10]; 9229 u8 num_of_vfs[0x10]; 9230 9231 u8 bdf0[0x10]; 9232 u8 reserved_at_b0[0x10]; 9233 9234 u8 max_read_request_size[0x4]; 9235 u8 max_payload_size[0x4]; 9236 u8 reserved_at_c8[0x5]; 9237 u8 pwr_status[0x3]; 9238 u8 port_type[0x4]; 9239 u8 reserved_at_d4[0xb]; 9240 u8 lane_reversal[0x1]; 9241 9242 u8 reserved_at_e0[0x14]; 9243 u8 pci_power[0xc]; 9244 9245 u8 reserved_at_100[0x20]; 9246 9247 u8 device_status[0x10]; 9248 u8 port_state[0x8]; 9249 u8 reserved_at_138[0x8]; 9250 9251 u8 reserved_at_140[0x10]; 9252 u8 receiver_detect_result[0x10]; 9253 9254 u8 reserved_at_160[0x20]; 9255 }; 9256 9257 struct mlx5_ifc_mpcnt_reg_bits { 9258 u8 reserved_at_0[0x8]; 9259 u8 pcie_index[0x8]; 9260 u8 reserved_at_10[0xa]; 9261 u8 grp[0x6]; 9262 9263 u8 clr[0x1]; 9264 u8 reserved_at_21[0x1f]; 9265 9266 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set; 9267 }; 9268 9269 struct mlx5_ifc_ppad_reg_bits { 9270 u8 reserved_at_0[0x3]; 9271 u8 single_mac[0x1]; 9272 u8 reserved_at_4[0x4]; 9273 u8 local_port[0x8]; 9274 u8 mac_47_32[0x10]; 9275 9276 u8 mac_31_0[0x20]; 9277 9278 u8 reserved_at_40[0x40]; 9279 }; 9280 9281 struct mlx5_ifc_pmtu_reg_bits { 9282 u8 reserved_at_0[0x8]; 9283 u8 local_port[0x8]; 9284 u8 reserved_at_10[0x10]; 9285 9286 u8 max_mtu[0x10]; 9287 u8 reserved_at_30[0x10]; 9288 9289 u8 admin_mtu[0x10]; 9290 u8 reserved_at_50[0x10]; 9291 9292 u8 oper_mtu[0x10]; 9293 u8 reserved_at_70[0x10]; 9294 }; 9295 9296 struct mlx5_ifc_pmpr_reg_bits { 9297 u8 reserved_at_0[0x8]; 9298 u8 module[0x8]; 9299 u8 reserved_at_10[0x10]; 9300 9301 u8 reserved_at_20[0x18]; 9302 u8 attenuation_5g[0x8]; 9303 9304 u8 reserved_at_40[0x18]; 9305 u8 attenuation_7g[0x8]; 9306 9307 u8 reserved_at_60[0x18]; 9308 u8 attenuation_12g[0x8]; 9309 }; 9310 9311 struct mlx5_ifc_pmpe_reg_bits { 9312 u8 reserved_at_0[0x8]; 9313 u8 module[0x8]; 9314 u8 reserved_at_10[0xc]; 9315 u8 module_status[0x4]; 9316 9317 u8 reserved_at_20[0x60]; 9318 }; 9319 9320 struct mlx5_ifc_pmpc_reg_bits { 9321 u8 module_state_updated[32][0x8]; 9322 }; 9323 9324 struct mlx5_ifc_pmlpn_reg_bits { 9325 u8 reserved_at_0[0x4]; 9326 u8 mlpn_status[0x4]; 9327 u8 local_port[0x8]; 9328 u8 reserved_at_10[0x10]; 9329 9330 u8 e[0x1]; 9331 u8 reserved_at_21[0x1f]; 9332 }; 9333 9334 struct mlx5_ifc_pmlp_reg_bits { 9335 u8 rxtx[0x1]; 9336 u8 reserved_at_1[0x7]; 9337 u8 local_port[0x8]; 9338 u8 reserved_at_10[0x8]; 9339 u8 width[0x8]; 9340 9341 u8 lane0_module_mapping[0x20]; 9342 9343 u8 lane1_module_mapping[0x20]; 9344 9345 u8 lane2_module_mapping[0x20]; 9346 9347 u8 lane3_module_mapping[0x20]; 9348 9349 u8 reserved_at_a0[0x160]; 9350 }; 9351 9352 struct mlx5_ifc_pmaos_reg_bits { 9353 u8 reserved_at_0[0x8]; 9354 u8 module[0x8]; 9355 u8 reserved_at_10[0x4]; 9356 u8 admin_status[0x4]; 9357 u8 reserved_at_18[0x4]; 9358 u8 oper_status[0x4]; 9359 9360 u8 ase[0x1]; 9361 u8 ee[0x1]; 9362 u8 reserved_at_22[0x1c]; 9363 u8 e[0x2]; 9364 9365 u8 reserved_at_40[0x40]; 9366 }; 9367 9368 struct mlx5_ifc_plpc_reg_bits { 9369 u8 reserved_at_0[0x4]; 9370 u8 profile_id[0xc]; 9371 u8 reserved_at_10[0x4]; 9372 u8 proto_mask[0x4]; 9373 u8 reserved_at_18[0x8]; 9374 9375 u8 reserved_at_20[0x10]; 9376 u8 lane_speed[0x10]; 9377 9378 u8 reserved_at_40[0x17]; 9379 u8 lpbf[0x1]; 9380 u8 fec_mode_policy[0x8]; 9381 9382 u8 retransmission_capability[0x8]; 9383 u8 fec_mode_capability[0x18]; 9384 9385 u8 retransmission_support_admin[0x8]; 9386 u8 fec_mode_support_admin[0x18]; 9387 9388 u8 retransmission_request_admin[0x8]; 9389 u8 fec_mode_request_admin[0x18]; 9390 9391 u8 reserved_at_c0[0x80]; 9392 }; 9393 9394 struct mlx5_ifc_plib_reg_bits { 9395 u8 reserved_at_0[0x8]; 9396 u8 local_port[0x8]; 9397 u8 reserved_at_10[0x8]; 9398 u8 ib_port[0x8]; 9399 9400 u8 reserved_at_20[0x60]; 9401 }; 9402 9403 struct mlx5_ifc_plbf_reg_bits { 9404 u8 reserved_at_0[0x8]; 9405 u8 local_port[0x8]; 9406 u8 reserved_at_10[0xd]; 9407 u8 lbf_mode[0x3]; 9408 9409 u8 reserved_at_20[0x20]; 9410 }; 9411 9412 struct mlx5_ifc_pipg_reg_bits { 9413 u8 reserved_at_0[0x8]; 9414 u8 local_port[0x8]; 9415 u8 reserved_at_10[0x10]; 9416 9417 u8 dic[0x1]; 9418 u8 reserved_at_21[0x19]; 9419 u8 ipg[0x4]; 9420 u8 reserved_at_3e[0x2]; 9421 }; 9422 9423 struct mlx5_ifc_pifr_reg_bits { 9424 u8 reserved_at_0[0x8]; 9425 u8 local_port[0x8]; 9426 u8 reserved_at_10[0x10]; 9427 9428 u8 reserved_at_20[0xe0]; 9429 9430 u8 port_filter[8][0x20]; 9431 9432 u8 port_filter_update_en[8][0x20]; 9433 }; 9434 9435 struct mlx5_ifc_pfcc_reg_bits { 9436 u8 reserved_at_0[0x8]; 9437 u8 local_port[0x8]; 9438 u8 reserved_at_10[0xb]; 9439 u8 ppan_mask_n[0x1]; 9440 u8 minor_stall_mask[0x1]; 9441 u8 critical_stall_mask[0x1]; 9442 u8 reserved_at_1e[0x2]; 9443 9444 u8 ppan[0x4]; 9445 u8 reserved_at_24[0x4]; 9446 u8 prio_mask_tx[0x8]; 9447 u8 reserved_at_30[0x8]; 9448 u8 prio_mask_rx[0x8]; 9449 9450 u8 pptx[0x1]; 9451 u8 aptx[0x1]; 9452 u8 pptx_mask_n[0x1]; 9453 u8 reserved_at_43[0x5]; 9454 u8 pfctx[0x8]; 9455 u8 reserved_at_50[0x10]; 9456 9457 u8 pprx[0x1]; 9458 u8 aprx[0x1]; 9459 u8 pprx_mask_n[0x1]; 9460 u8 reserved_at_63[0x5]; 9461 u8 pfcrx[0x8]; 9462 u8 reserved_at_70[0x10]; 9463 9464 u8 device_stall_minor_watermark[0x10]; 9465 u8 device_stall_critical_watermark[0x10]; 9466 9467 u8 reserved_at_a0[0x60]; 9468 }; 9469 9470 struct mlx5_ifc_pelc_reg_bits { 9471 u8 op[0x4]; 9472 u8 reserved_at_4[0x4]; 9473 u8 local_port[0x8]; 9474 u8 reserved_at_10[0x10]; 9475 9476 u8 op_admin[0x8]; 9477 u8 op_capability[0x8]; 9478 u8 op_request[0x8]; 9479 u8 op_active[0x8]; 9480 9481 u8 admin[0x40]; 9482 9483 u8 capability[0x40]; 9484 9485 u8 request[0x40]; 9486 9487 u8 active[0x40]; 9488 9489 u8 reserved_at_140[0x80]; 9490 }; 9491 9492 struct mlx5_ifc_peir_reg_bits { 9493 u8 reserved_at_0[0x8]; 9494 u8 local_port[0x8]; 9495 u8 reserved_at_10[0x10]; 9496 9497 u8 reserved_at_20[0xc]; 9498 u8 error_count[0x4]; 9499 u8 reserved_at_30[0x10]; 9500 9501 u8 reserved_at_40[0xc]; 9502 u8 lane[0x4]; 9503 u8 reserved_at_50[0x8]; 9504 u8 error_type[0x8]; 9505 }; 9506 9507 struct mlx5_ifc_mpegc_reg_bits { 9508 u8 reserved_at_0[0x30]; 9509 u8 field_select[0x10]; 9510 9511 u8 tx_overflow_sense[0x1]; 9512 u8 mark_cqe[0x1]; 9513 u8 mark_cnp[0x1]; 9514 u8 reserved_at_43[0x1b]; 9515 u8 tx_lossy_overflow_oper[0x2]; 9516 9517 u8 reserved_at_60[0x100]; 9518 }; 9519 9520 enum { 9521 MLX5_MTUTC_OPERATION_SET_TIME_IMMEDIATE = 0x1, 9522 MLX5_MTUTC_OPERATION_ADJUST_TIME = 0x2, 9523 MLX5_MTUTC_OPERATION_ADJUST_FREQ_UTC = 0x3, 9524 }; 9525 9526 struct mlx5_ifc_mtutc_reg_bits { 9527 u8 reserved_at_0[0x1c]; 9528 u8 operation[0x4]; 9529 9530 u8 freq_adjustment[0x20]; 9531 9532 u8 reserved_at_40[0x40]; 9533 9534 u8 utc_sec[0x20]; 9535 9536 u8 reserved_at_a0[0x2]; 9537 u8 utc_nsec[0x1e]; 9538 9539 u8 time_adjustment[0x20]; 9540 }; 9541 9542 struct mlx5_ifc_pcam_enhanced_features_bits { 9543 u8 reserved_at_0[0x68]; 9544 u8 fec_50G_per_lane_in_pplm[0x1]; 9545 u8 reserved_at_69[0x4]; 9546 u8 rx_icrc_encapsulated_counter[0x1]; 9547 u8 reserved_at_6e[0x4]; 9548 u8 ptys_extended_ethernet[0x1]; 9549 u8 reserved_at_73[0x3]; 9550 u8 pfcc_mask[0x1]; 9551 u8 reserved_at_77[0x3]; 9552 u8 per_lane_error_counters[0x1]; 9553 u8 rx_buffer_fullness_counters[0x1]; 9554 u8 ptys_connector_type[0x1]; 9555 u8 reserved_at_7d[0x1]; 9556 u8 ppcnt_discard_group[0x1]; 9557 u8 ppcnt_statistical_group[0x1]; 9558 }; 9559 9560 struct mlx5_ifc_pcam_regs_5000_to_507f_bits { 9561 u8 port_access_reg_cap_mask_127_to_96[0x20]; 9562 u8 port_access_reg_cap_mask_95_to_64[0x20]; 9563 9564 u8 port_access_reg_cap_mask_63_to_36[0x1c]; 9565 u8 pplm[0x1]; 9566 u8 port_access_reg_cap_mask_34_to_32[0x3]; 9567 9568 u8 port_access_reg_cap_mask_31_to_13[0x13]; 9569 u8 pbmc[0x1]; 9570 u8 pptb[0x1]; 9571 u8 port_access_reg_cap_mask_10_to_09[0x2]; 9572 u8 ppcnt[0x1]; 9573 u8 port_access_reg_cap_mask_07_to_00[0x8]; 9574 }; 9575 9576 struct mlx5_ifc_pcam_reg_bits { 9577 u8 reserved_at_0[0x8]; 9578 u8 feature_group[0x8]; 9579 u8 reserved_at_10[0x8]; 9580 u8 access_reg_group[0x8]; 9581 9582 u8 reserved_at_20[0x20]; 9583 9584 union { 9585 struct mlx5_ifc_pcam_regs_5000_to_507f_bits regs_5000_to_507f; 9586 u8 reserved_at_0[0x80]; 9587 } port_access_reg_cap_mask; 9588 9589 u8 reserved_at_c0[0x80]; 9590 9591 union { 9592 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features; 9593 u8 reserved_at_0[0x80]; 9594 } feature_cap_mask; 9595 9596 u8 reserved_at_1c0[0xc0]; 9597 }; 9598 9599 struct mlx5_ifc_mcam_enhanced_features_bits { 9600 u8 reserved_at_0[0x6b]; 9601 u8 ptpcyc2realtime_modify[0x1]; 9602 u8 reserved_at_6c[0x2]; 9603 u8 pci_status_and_power[0x1]; 9604 u8 reserved_at_6f[0x5]; 9605 u8 mark_tx_action_cnp[0x1]; 9606 u8 mark_tx_action_cqe[0x1]; 9607 u8 dynamic_tx_overflow[0x1]; 9608 u8 reserved_at_77[0x4]; 9609 u8 pcie_outbound_stalled[0x1]; 9610 u8 tx_overflow_buffer_pkt[0x1]; 9611 u8 mtpps_enh_out_per_adj[0x1]; 9612 u8 mtpps_fs[0x1]; 9613 u8 pcie_performance_group[0x1]; 9614 }; 9615 9616 struct mlx5_ifc_mcam_access_reg_bits { 9617 u8 reserved_at_0[0x1c]; 9618 u8 mcda[0x1]; 9619 u8 mcc[0x1]; 9620 u8 mcqi[0x1]; 9621 u8 mcqs[0x1]; 9622 9623 u8 regs_95_to_87[0x9]; 9624 u8 mpegc[0x1]; 9625 u8 mtutc[0x1]; 9626 u8 regs_84_to_68[0x11]; 9627 u8 tracer_registers[0x4]; 9628 9629 u8 regs_63_to_32[0x20]; 9630 u8 regs_31_to_0[0x20]; 9631 }; 9632 9633 struct mlx5_ifc_mcam_access_reg_bits1 { 9634 u8 regs_127_to_96[0x20]; 9635 9636 u8 regs_95_to_64[0x20]; 9637 9638 u8 regs_63_to_32[0x20]; 9639 9640 u8 regs_31_to_0[0x20]; 9641 }; 9642 9643 struct mlx5_ifc_mcam_access_reg_bits2 { 9644 u8 regs_127_to_99[0x1d]; 9645 u8 mirc[0x1]; 9646 u8 regs_97_to_96[0x2]; 9647 9648 u8 regs_95_to_64[0x20]; 9649 9650 u8 regs_63_to_32[0x20]; 9651 9652 u8 regs_31_to_0[0x20]; 9653 }; 9654 9655 struct mlx5_ifc_mcam_reg_bits { 9656 u8 reserved_at_0[0x8]; 9657 u8 feature_group[0x8]; 9658 u8 reserved_at_10[0x8]; 9659 u8 access_reg_group[0x8]; 9660 9661 u8 reserved_at_20[0x20]; 9662 9663 union { 9664 struct mlx5_ifc_mcam_access_reg_bits access_regs; 9665 struct mlx5_ifc_mcam_access_reg_bits1 access_regs1; 9666 struct mlx5_ifc_mcam_access_reg_bits2 access_regs2; 9667 u8 reserved_at_0[0x80]; 9668 } mng_access_reg_cap_mask; 9669 9670 u8 reserved_at_c0[0x80]; 9671 9672 union { 9673 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features; 9674 u8 reserved_at_0[0x80]; 9675 } mng_feature_cap_mask; 9676 9677 u8 reserved_at_1c0[0x80]; 9678 }; 9679 9680 struct mlx5_ifc_qcam_access_reg_cap_mask { 9681 u8 qcam_access_reg_cap_mask_127_to_20[0x6C]; 9682 u8 qpdpm[0x1]; 9683 u8 qcam_access_reg_cap_mask_18_to_4[0x0F]; 9684 u8 qdpm[0x1]; 9685 u8 qpts[0x1]; 9686 u8 qcap[0x1]; 9687 u8 qcam_access_reg_cap_mask_0[0x1]; 9688 }; 9689 9690 struct mlx5_ifc_qcam_qos_feature_cap_mask { 9691 u8 qcam_qos_feature_cap_mask_127_to_1[0x7F]; 9692 u8 qpts_trust_both[0x1]; 9693 }; 9694 9695 struct mlx5_ifc_qcam_reg_bits { 9696 u8 reserved_at_0[0x8]; 9697 u8 feature_group[0x8]; 9698 u8 reserved_at_10[0x8]; 9699 u8 access_reg_group[0x8]; 9700 u8 reserved_at_20[0x20]; 9701 9702 union { 9703 struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap; 9704 u8 reserved_at_0[0x80]; 9705 } qos_access_reg_cap_mask; 9706 9707 u8 reserved_at_c0[0x80]; 9708 9709 union { 9710 struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap; 9711 u8 reserved_at_0[0x80]; 9712 } qos_feature_cap_mask; 9713 9714 u8 reserved_at_1c0[0x80]; 9715 }; 9716 9717 struct mlx5_ifc_core_dump_reg_bits { 9718 u8 reserved_at_0[0x18]; 9719 u8 core_dump_type[0x8]; 9720 9721 u8 reserved_at_20[0x30]; 9722 u8 vhca_id[0x10]; 9723 9724 u8 reserved_at_60[0x8]; 9725 u8 qpn[0x18]; 9726 u8 reserved_at_80[0x180]; 9727 }; 9728 9729 struct mlx5_ifc_pcap_reg_bits { 9730 u8 reserved_at_0[0x8]; 9731 u8 local_port[0x8]; 9732 u8 reserved_at_10[0x10]; 9733 9734 u8 port_capability_mask[4][0x20]; 9735 }; 9736 9737 struct mlx5_ifc_paos_reg_bits { 9738 u8 swid[0x8]; 9739 u8 local_port[0x8]; 9740 u8 reserved_at_10[0x4]; 9741 u8 admin_status[0x4]; 9742 u8 reserved_at_18[0x4]; 9743 u8 oper_status[0x4]; 9744 9745 u8 ase[0x1]; 9746 u8 ee[0x1]; 9747 u8 reserved_at_22[0x1c]; 9748 u8 e[0x2]; 9749 9750 u8 reserved_at_40[0x40]; 9751 }; 9752 9753 struct mlx5_ifc_pamp_reg_bits { 9754 u8 reserved_at_0[0x8]; 9755 u8 opamp_group[0x8]; 9756 u8 reserved_at_10[0xc]; 9757 u8 opamp_group_type[0x4]; 9758 9759 u8 start_index[0x10]; 9760 u8 reserved_at_30[0x4]; 9761 u8 num_of_indices[0xc]; 9762 9763 u8 index_data[18][0x10]; 9764 }; 9765 9766 struct mlx5_ifc_pcmr_reg_bits { 9767 u8 reserved_at_0[0x8]; 9768 u8 local_port[0x8]; 9769 u8 reserved_at_10[0x10]; 9770 9771 u8 entropy_force_cap[0x1]; 9772 u8 entropy_calc_cap[0x1]; 9773 u8 entropy_gre_calc_cap[0x1]; 9774 u8 reserved_at_23[0xf]; 9775 u8 rx_ts_over_crc_cap[0x1]; 9776 u8 reserved_at_33[0xb]; 9777 u8 fcs_cap[0x1]; 9778 u8 reserved_at_3f[0x1]; 9779 9780 u8 entropy_force[0x1]; 9781 u8 entropy_calc[0x1]; 9782 u8 entropy_gre_calc[0x1]; 9783 u8 reserved_at_43[0xf]; 9784 u8 rx_ts_over_crc[0x1]; 9785 u8 reserved_at_53[0xb]; 9786 u8 fcs_chk[0x1]; 9787 u8 reserved_at_5f[0x1]; 9788 }; 9789 9790 struct mlx5_ifc_lane_2_module_mapping_bits { 9791 u8 reserved_at_0[0x6]; 9792 u8 rx_lane[0x2]; 9793 u8 reserved_at_8[0x6]; 9794 u8 tx_lane[0x2]; 9795 u8 reserved_at_10[0x8]; 9796 u8 module[0x8]; 9797 }; 9798 9799 struct mlx5_ifc_bufferx_reg_bits { 9800 u8 reserved_at_0[0x6]; 9801 u8 lossy[0x1]; 9802 u8 epsb[0x1]; 9803 u8 reserved_at_8[0xc]; 9804 u8 size[0xc]; 9805 9806 u8 xoff_threshold[0x10]; 9807 u8 xon_threshold[0x10]; 9808 }; 9809 9810 struct mlx5_ifc_set_node_in_bits { 9811 u8 node_description[64][0x8]; 9812 }; 9813 9814 struct mlx5_ifc_register_power_settings_bits { 9815 u8 reserved_at_0[0x18]; 9816 u8 power_settings_level[0x8]; 9817 9818 u8 reserved_at_20[0x60]; 9819 }; 9820 9821 struct mlx5_ifc_register_host_endianness_bits { 9822 u8 he[0x1]; 9823 u8 reserved_at_1[0x1f]; 9824 9825 u8 reserved_at_20[0x60]; 9826 }; 9827 9828 struct mlx5_ifc_umr_pointer_desc_argument_bits { 9829 u8 reserved_at_0[0x20]; 9830 9831 u8 mkey[0x20]; 9832 9833 u8 addressh_63_32[0x20]; 9834 9835 u8 addressl_31_0[0x20]; 9836 }; 9837 9838 struct mlx5_ifc_ud_adrs_vector_bits { 9839 u8 dc_key[0x40]; 9840 9841 u8 ext[0x1]; 9842 u8 reserved_at_41[0x7]; 9843 u8 destination_qp_dct[0x18]; 9844 9845 u8 static_rate[0x4]; 9846 u8 sl_eth_prio[0x4]; 9847 u8 fl[0x1]; 9848 u8 mlid[0x7]; 9849 u8 rlid_udp_sport[0x10]; 9850 9851 u8 reserved_at_80[0x20]; 9852 9853 u8 rmac_47_16[0x20]; 9854 9855 u8 rmac_15_0[0x10]; 9856 u8 tclass[0x8]; 9857 u8 hop_limit[0x8]; 9858 9859 u8 reserved_at_e0[0x1]; 9860 u8 grh[0x1]; 9861 u8 reserved_at_e2[0x2]; 9862 u8 src_addr_index[0x8]; 9863 u8 flow_label[0x14]; 9864 9865 u8 rgid_rip[16][0x8]; 9866 }; 9867 9868 struct mlx5_ifc_pages_req_event_bits { 9869 u8 reserved_at_0[0x10]; 9870 u8 function_id[0x10]; 9871 9872 u8 num_pages[0x20]; 9873 9874 u8 reserved_at_40[0xa0]; 9875 }; 9876 9877 struct mlx5_ifc_eqe_bits { 9878 u8 reserved_at_0[0x8]; 9879 u8 event_type[0x8]; 9880 u8 reserved_at_10[0x8]; 9881 u8 event_sub_type[0x8]; 9882 9883 u8 reserved_at_20[0xe0]; 9884 9885 union mlx5_ifc_event_auto_bits event_data; 9886 9887 u8 reserved_at_1e0[0x10]; 9888 u8 signature[0x8]; 9889 u8 reserved_at_1f8[0x7]; 9890 u8 owner[0x1]; 9891 }; 9892 9893 enum { 9894 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7, 9895 }; 9896 9897 struct mlx5_ifc_cmd_queue_entry_bits { 9898 u8 type[0x8]; 9899 u8 reserved_at_8[0x18]; 9900 9901 u8 input_length[0x20]; 9902 9903 u8 input_mailbox_pointer_63_32[0x20]; 9904 9905 u8 input_mailbox_pointer_31_9[0x17]; 9906 u8 reserved_at_77[0x9]; 9907 9908 u8 command_input_inline_data[16][0x8]; 9909 9910 u8 command_output_inline_data[16][0x8]; 9911 9912 u8 output_mailbox_pointer_63_32[0x20]; 9913 9914 u8 output_mailbox_pointer_31_9[0x17]; 9915 u8 reserved_at_1b7[0x9]; 9916 9917 u8 output_length[0x20]; 9918 9919 u8 token[0x8]; 9920 u8 signature[0x8]; 9921 u8 reserved_at_1f0[0x8]; 9922 u8 status[0x7]; 9923 u8 ownership[0x1]; 9924 }; 9925 9926 struct mlx5_ifc_cmd_out_bits { 9927 u8 status[0x8]; 9928 u8 reserved_at_8[0x18]; 9929 9930 u8 syndrome[0x20]; 9931 9932 u8 command_output[0x20]; 9933 }; 9934 9935 struct mlx5_ifc_cmd_in_bits { 9936 u8 opcode[0x10]; 9937 u8 reserved_at_10[0x10]; 9938 9939 u8 reserved_at_20[0x10]; 9940 u8 op_mod[0x10]; 9941 9942 u8 command[][0x20]; 9943 }; 9944 9945 struct mlx5_ifc_cmd_if_box_bits { 9946 u8 mailbox_data[512][0x8]; 9947 9948 u8 reserved_at_1000[0x180]; 9949 9950 u8 next_pointer_63_32[0x20]; 9951 9952 u8 next_pointer_31_10[0x16]; 9953 u8 reserved_at_11b6[0xa]; 9954 9955 u8 block_number[0x20]; 9956 9957 u8 reserved_at_11e0[0x8]; 9958 u8 token[0x8]; 9959 u8 ctrl_signature[0x8]; 9960 u8 signature[0x8]; 9961 }; 9962 9963 struct mlx5_ifc_mtt_bits { 9964 u8 ptag_63_32[0x20]; 9965 9966 u8 ptag_31_8[0x18]; 9967 u8 reserved_at_38[0x6]; 9968 u8 wr_en[0x1]; 9969 u8 rd_en[0x1]; 9970 }; 9971 9972 struct mlx5_ifc_query_wol_rol_out_bits { 9973 u8 status[0x8]; 9974 u8 reserved_at_8[0x18]; 9975 9976 u8 syndrome[0x20]; 9977 9978 u8 reserved_at_40[0x10]; 9979 u8 rol_mode[0x8]; 9980 u8 wol_mode[0x8]; 9981 9982 u8 reserved_at_60[0x20]; 9983 }; 9984 9985 struct mlx5_ifc_query_wol_rol_in_bits { 9986 u8 opcode[0x10]; 9987 u8 reserved_at_10[0x10]; 9988 9989 u8 reserved_at_20[0x10]; 9990 u8 op_mod[0x10]; 9991 9992 u8 reserved_at_40[0x40]; 9993 }; 9994 9995 struct mlx5_ifc_set_wol_rol_out_bits { 9996 u8 status[0x8]; 9997 u8 reserved_at_8[0x18]; 9998 9999 u8 syndrome[0x20]; 10000 10001 u8 reserved_at_40[0x40]; 10002 }; 10003 10004 struct mlx5_ifc_set_wol_rol_in_bits { 10005 u8 opcode[0x10]; 10006 u8 reserved_at_10[0x10]; 10007 10008 u8 reserved_at_20[0x10]; 10009 u8 op_mod[0x10]; 10010 10011 u8 rol_mode_valid[0x1]; 10012 u8 wol_mode_valid[0x1]; 10013 u8 reserved_at_42[0xe]; 10014 u8 rol_mode[0x8]; 10015 u8 wol_mode[0x8]; 10016 10017 u8 reserved_at_60[0x20]; 10018 }; 10019 10020 enum { 10021 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0, 10022 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1, 10023 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2, 10024 }; 10025 10026 enum { 10027 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0, 10028 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1, 10029 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2, 10030 }; 10031 10032 enum { 10033 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR = 0x1, 10034 MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC = 0x7, 10035 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR = 0x8, 10036 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR = 0x9, 10037 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR = 0xa, 10038 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR = 0xb, 10039 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN = 0xc, 10040 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR = 0xd, 10041 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV = 0xe, 10042 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR = 0xf, 10043 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR = 0x10, 10044 }; 10045 10046 struct mlx5_ifc_initial_seg_bits { 10047 u8 fw_rev_minor[0x10]; 10048 u8 fw_rev_major[0x10]; 10049 10050 u8 cmd_interface_rev[0x10]; 10051 u8 fw_rev_subminor[0x10]; 10052 10053 u8 reserved_at_40[0x40]; 10054 10055 u8 cmdq_phy_addr_63_32[0x20]; 10056 10057 u8 cmdq_phy_addr_31_12[0x14]; 10058 u8 reserved_at_b4[0x2]; 10059 u8 nic_interface[0x2]; 10060 u8 log_cmdq_size[0x4]; 10061 u8 log_cmdq_stride[0x4]; 10062 10063 u8 command_doorbell_vector[0x20]; 10064 10065 u8 reserved_at_e0[0xf00]; 10066 10067 u8 initializing[0x1]; 10068 u8 reserved_at_fe1[0x4]; 10069 u8 nic_interface_supported[0x3]; 10070 u8 embedded_cpu[0x1]; 10071 u8 reserved_at_fe9[0x17]; 10072 10073 struct mlx5_ifc_health_buffer_bits health_buffer; 10074 10075 u8 no_dram_nic_offset[0x20]; 10076 10077 u8 reserved_at_1220[0x6e40]; 10078 10079 u8 reserved_at_8060[0x1f]; 10080 u8 clear_int[0x1]; 10081 10082 u8 health_syndrome[0x8]; 10083 u8 health_counter[0x18]; 10084 10085 u8 reserved_at_80a0[0x17fc0]; 10086 }; 10087 10088 struct mlx5_ifc_mtpps_reg_bits { 10089 u8 reserved_at_0[0xc]; 10090 u8 cap_number_of_pps_pins[0x4]; 10091 u8 reserved_at_10[0x4]; 10092 u8 cap_max_num_of_pps_in_pins[0x4]; 10093 u8 reserved_at_18[0x4]; 10094 u8 cap_max_num_of_pps_out_pins[0x4]; 10095 10096 u8 reserved_at_20[0x24]; 10097 u8 cap_pin_3_mode[0x4]; 10098 u8 reserved_at_48[0x4]; 10099 u8 cap_pin_2_mode[0x4]; 10100 u8 reserved_at_50[0x4]; 10101 u8 cap_pin_1_mode[0x4]; 10102 u8 reserved_at_58[0x4]; 10103 u8 cap_pin_0_mode[0x4]; 10104 10105 u8 reserved_at_60[0x4]; 10106 u8 cap_pin_7_mode[0x4]; 10107 u8 reserved_at_68[0x4]; 10108 u8 cap_pin_6_mode[0x4]; 10109 u8 reserved_at_70[0x4]; 10110 u8 cap_pin_5_mode[0x4]; 10111 u8 reserved_at_78[0x4]; 10112 u8 cap_pin_4_mode[0x4]; 10113 10114 u8 field_select[0x20]; 10115 u8 reserved_at_a0[0x60]; 10116 10117 u8 enable[0x1]; 10118 u8 reserved_at_101[0xb]; 10119 u8 pattern[0x4]; 10120 u8 reserved_at_110[0x4]; 10121 u8 pin_mode[0x4]; 10122 u8 pin[0x8]; 10123 10124 u8 reserved_at_120[0x20]; 10125 10126 u8 time_stamp[0x40]; 10127 10128 u8 out_pulse_duration[0x10]; 10129 u8 out_periodic_adjustment[0x10]; 10130 u8 enhanced_out_periodic_adjustment[0x20]; 10131 10132 u8 reserved_at_1c0[0x20]; 10133 }; 10134 10135 struct mlx5_ifc_mtppse_reg_bits { 10136 u8 reserved_at_0[0x18]; 10137 u8 pin[0x8]; 10138 u8 event_arm[0x1]; 10139 u8 reserved_at_21[0x1b]; 10140 u8 event_generation_mode[0x4]; 10141 u8 reserved_at_40[0x40]; 10142 }; 10143 10144 struct mlx5_ifc_mcqs_reg_bits { 10145 u8 last_index_flag[0x1]; 10146 u8 reserved_at_1[0x7]; 10147 u8 fw_device[0x8]; 10148 u8 component_index[0x10]; 10149 10150 u8 reserved_at_20[0x10]; 10151 u8 identifier[0x10]; 10152 10153 u8 reserved_at_40[0x17]; 10154 u8 component_status[0x5]; 10155 u8 component_update_state[0x4]; 10156 10157 u8 last_update_state_changer_type[0x4]; 10158 u8 last_update_state_changer_host_id[0x4]; 10159 u8 reserved_at_68[0x18]; 10160 }; 10161 10162 struct mlx5_ifc_mcqi_cap_bits { 10163 u8 supported_info_bitmask[0x20]; 10164 10165 u8 component_size[0x20]; 10166 10167 u8 max_component_size[0x20]; 10168 10169 u8 log_mcda_word_size[0x4]; 10170 u8 reserved_at_64[0xc]; 10171 u8 mcda_max_write_size[0x10]; 10172 10173 u8 rd_en[0x1]; 10174 u8 reserved_at_81[0x1]; 10175 u8 match_chip_id[0x1]; 10176 u8 match_psid[0x1]; 10177 u8 check_user_timestamp[0x1]; 10178 u8 match_base_guid_mac[0x1]; 10179 u8 reserved_at_86[0x1a]; 10180 }; 10181 10182 struct mlx5_ifc_mcqi_version_bits { 10183 u8 reserved_at_0[0x2]; 10184 u8 build_time_valid[0x1]; 10185 u8 user_defined_time_valid[0x1]; 10186 u8 reserved_at_4[0x14]; 10187 u8 version_string_length[0x8]; 10188 10189 u8 version[0x20]; 10190 10191 u8 build_time[0x40]; 10192 10193 u8 user_defined_time[0x40]; 10194 10195 u8 build_tool_version[0x20]; 10196 10197 u8 reserved_at_e0[0x20]; 10198 10199 u8 version_string[92][0x8]; 10200 }; 10201 10202 struct mlx5_ifc_mcqi_activation_method_bits { 10203 u8 pending_server_ac_power_cycle[0x1]; 10204 u8 pending_server_dc_power_cycle[0x1]; 10205 u8 pending_server_reboot[0x1]; 10206 u8 pending_fw_reset[0x1]; 10207 u8 auto_activate[0x1]; 10208 u8 all_hosts_sync[0x1]; 10209 u8 device_hw_reset[0x1]; 10210 u8 reserved_at_7[0x19]; 10211 }; 10212 10213 union mlx5_ifc_mcqi_reg_data_bits { 10214 struct mlx5_ifc_mcqi_cap_bits mcqi_caps; 10215 struct mlx5_ifc_mcqi_version_bits mcqi_version; 10216 struct mlx5_ifc_mcqi_activation_method_bits mcqi_activation_mathod; 10217 }; 10218 10219 struct mlx5_ifc_mcqi_reg_bits { 10220 u8 read_pending_component[0x1]; 10221 u8 reserved_at_1[0xf]; 10222 u8 component_index[0x10]; 10223 10224 u8 reserved_at_20[0x20]; 10225 10226 u8 reserved_at_40[0x1b]; 10227 u8 info_type[0x5]; 10228 10229 u8 info_size[0x20]; 10230 10231 u8 offset[0x20]; 10232 10233 u8 reserved_at_a0[0x10]; 10234 u8 data_size[0x10]; 10235 10236 union mlx5_ifc_mcqi_reg_data_bits data[]; 10237 }; 10238 10239 struct mlx5_ifc_mcc_reg_bits { 10240 u8 reserved_at_0[0x4]; 10241 u8 time_elapsed_since_last_cmd[0xc]; 10242 u8 reserved_at_10[0x8]; 10243 u8 instruction[0x8]; 10244 10245 u8 reserved_at_20[0x10]; 10246 u8 component_index[0x10]; 10247 10248 u8 reserved_at_40[0x8]; 10249 u8 update_handle[0x18]; 10250 10251 u8 handle_owner_type[0x4]; 10252 u8 handle_owner_host_id[0x4]; 10253 u8 reserved_at_68[0x1]; 10254 u8 control_progress[0x7]; 10255 u8 error_code[0x8]; 10256 u8 reserved_at_78[0x4]; 10257 u8 control_state[0x4]; 10258 10259 u8 component_size[0x20]; 10260 10261 u8 reserved_at_a0[0x60]; 10262 }; 10263 10264 struct mlx5_ifc_mcda_reg_bits { 10265 u8 reserved_at_0[0x8]; 10266 u8 update_handle[0x18]; 10267 10268 u8 offset[0x20]; 10269 10270 u8 reserved_at_40[0x10]; 10271 u8 size[0x10]; 10272 10273 u8 reserved_at_60[0x20]; 10274 10275 u8 data[][0x20]; 10276 }; 10277 10278 enum { 10279 MLX5_MFRL_REG_RESET_TYPE_FULL_CHIP = BIT(0), 10280 MLX5_MFRL_REG_RESET_TYPE_NET_PORT_ALIVE = BIT(1), 10281 }; 10282 10283 enum { 10284 MLX5_MFRL_REG_RESET_LEVEL0 = BIT(0), 10285 MLX5_MFRL_REG_RESET_LEVEL3 = BIT(3), 10286 MLX5_MFRL_REG_RESET_LEVEL6 = BIT(6), 10287 }; 10288 10289 struct mlx5_ifc_mfrl_reg_bits { 10290 u8 reserved_at_0[0x20]; 10291 10292 u8 reserved_at_20[0x2]; 10293 u8 pci_sync_for_fw_update_start[0x1]; 10294 u8 pci_sync_for_fw_update_resp[0x2]; 10295 u8 rst_type_sel[0x3]; 10296 u8 reserved_at_28[0x8]; 10297 u8 reset_type[0x8]; 10298 u8 reset_level[0x8]; 10299 }; 10300 10301 struct mlx5_ifc_mirc_reg_bits { 10302 u8 reserved_at_0[0x18]; 10303 u8 status_code[0x8]; 10304 10305 u8 reserved_at_20[0x20]; 10306 }; 10307 10308 struct mlx5_ifc_pddr_monitor_opcode_bits { 10309 u8 reserved_at_0[0x10]; 10310 u8 monitor_opcode[0x10]; 10311 }; 10312 10313 union mlx5_ifc_pddr_troubleshooting_page_status_opcode_auto_bits { 10314 struct mlx5_ifc_pddr_monitor_opcode_bits pddr_monitor_opcode; 10315 u8 reserved_at_0[0x20]; 10316 }; 10317 10318 enum { 10319 /* Monitor opcodes */ 10320 MLX5_PDDR_REG_TRBLSH_GROUP_OPCODE_MONITOR = 0x0, 10321 }; 10322 10323 struct mlx5_ifc_pddr_troubleshooting_page_bits { 10324 u8 reserved_at_0[0x10]; 10325 u8 group_opcode[0x10]; 10326 10327 union mlx5_ifc_pddr_troubleshooting_page_status_opcode_auto_bits status_opcode; 10328 10329 u8 reserved_at_40[0x20]; 10330 10331 u8 status_message[59][0x20]; 10332 }; 10333 10334 union mlx5_ifc_pddr_reg_page_data_auto_bits { 10335 struct mlx5_ifc_pddr_troubleshooting_page_bits pddr_troubleshooting_page; 10336 u8 reserved_at_0[0x7c0]; 10337 }; 10338 10339 enum { 10340 MLX5_PDDR_REG_PAGE_SELECT_TROUBLESHOOTING_INFO_PAGE = 0x1, 10341 }; 10342 10343 struct mlx5_ifc_pddr_reg_bits { 10344 u8 reserved_at_0[0x8]; 10345 u8 local_port[0x8]; 10346 u8 pnat[0x2]; 10347 u8 reserved_at_12[0xe]; 10348 10349 u8 reserved_at_20[0x18]; 10350 u8 page_select[0x8]; 10351 10352 union mlx5_ifc_pddr_reg_page_data_auto_bits page_data; 10353 }; 10354 10355 union mlx5_ifc_ports_control_registers_document_bits { 10356 struct mlx5_ifc_bufferx_reg_bits bufferx_reg; 10357 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 10358 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 10359 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 10360 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 10361 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 10362 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 10363 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout; 10364 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout; 10365 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping; 10366 struct mlx5_ifc_pamp_reg_bits pamp_reg; 10367 struct mlx5_ifc_paos_reg_bits paos_reg; 10368 struct mlx5_ifc_pcap_reg_bits pcap_reg; 10369 struct mlx5_ifc_pddr_monitor_opcode_bits pddr_monitor_opcode; 10370 struct mlx5_ifc_pddr_reg_bits pddr_reg; 10371 struct mlx5_ifc_pddr_troubleshooting_page_bits pddr_troubleshooting_page; 10372 struct mlx5_ifc_peir_reg_bits peir_reg; 10373 struct mlx5_ifc_pelc_reg_bits pelc_reg; 10374 struct mlx5_ifc_pfcc_reg_bits pfcc_reg; 10375 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 10376 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 10377 struct mlx5_ifc_pifr_reg_bits pifr_reg; 10378 struct mlx5_ifc_pipg_reg_bits pipg_reg; 10379 struct mlx5_ifc_plbf_reg_bits plbf_reg; 10380 struct mlx5_ifc_plib_reg_bits plib_reg; 10381 struct mlx5_ifc_plpc_reg_bits plpc_reg; 10382 struct mlx5_ifc_pmaos_reg_bits pmaos_reg; 10383 struct mlx5_ifc_pmlp_reg_bits pmlp_reg; 10384 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg; 10385 struct mlx5_ifc_pmpc_reg_bits pmpc_reg; 10386 struct mlx5_ifc_pmpe_reg_bits pmpe_reg; 10387 struct mlx5_ifc_pmpr_reg_bits pmpr_reg; 10388 struct mlx5_ifc_pmtu_reg_bits pmtu_reg; 10389 struct mlx5_ifc_ppad_reg_bits ppad_reg; 10390 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg; 10391 struct mlx5_ifc_mpein_reg_bits mpein_reg; 10392 struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg; 10393 struct mlx5_ifc_pplm_reg_bits pplm_reg; 10394 struct mlx5_ifc_pplr_reg_bits pplr_reg; 10395 struct mlx5_ifc_ppsc_reg_bits ppsc_reg; 10396 struct mlx5_ifc_pqdr_reg_bits pqdr_reg; 10397 struct mlx5_ifc_pspa_reg_bits pspa_reg; 10398 struct mlx5_ifc_ptas_reg_bits ptas_reg; 10399 struct mlx5_ifc_ptys_reg_bits ptys_reg; 10400 struct mlx5_ifc_mlcr_reg_bits mlcr_reg; 10401 struct mlx5_ifc_pude_reg_bits pude_reg; 10402 struct mlx5_ifc_pvlc_reg_bits pvlc_reg; 10403 struct mlx5_ifc_slrg_reg_bits slrg_reg; 10404 struct mlx5_ifc_sltp_reg_bits sltp_reg; 10405 struct mlx5_ifc_mtpps_reg_bits mtpps_reg; 10406 struct mlx5_ifc_mtppse_reg_bits mtppse_reg; 10407 struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg; 10408 struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits; 10409 struct mlx5_ifc_fpga_cap_bits fpga_cap_bits; 10410 struct mlx5_ifc_mcqi_reg_bits mcqi_reg; 10411 struct mlx5_ifc_mcc_reg_bits mcc_reg; 10412 struct mlx5_ifc_mcda_reg_bits mcda_reg; 10413 struct mlx5_ifc_mirc_reg_bits mirc_reg; 10414 struct mlx5_ifc_mfrl_reg_bits mfrl_reg; 10415 struct mlx5_ifc_mtutc_reg_bits mtutc_reg; 10416 u8 reserved_at_0[0x60e0]; 10417 }; 10418 10419 union mlx5_ifc_debug_enhancements_document_bits { 10420 struct mlx5_ifc_health_buffer_bits health_buffer; 10421 u8 reserved_at_0[0x200]; 10422 }; 10423 10424 union mlx5_ifc_uplink_pci_interface_document_bits { 10425 struct mlx5_ifc_initial_seg_bits initial_seg; 10426 u8 reserved_at_0[0x20060]; 10427 }; 10428 10429 struct mlx5_ifc_set_flow_table_root_out_bits { 10430 u8 status[0x8]; 10431 u8 reserved_at_8[0x18]; 10432 10433 u8 syndrome[0x20]; 10434 10435 u8 reserved_at_40[0x40]; 10436 }; 10437 10438 struct mlx5_ifc_set_flow_table_root_in_bits { 10439 u8 opcode[0x10]; 10440 u8 reserved_at_10[0x10]; 10441 10442 u8 reserved_at_20[0x10]; 10443 u8 op_mod[0x10]; 10444 10445 u8 other_vport[0x1]; 10446 u8 reserved_at_41[0xf]; 10447 u8 vport_number[0x10]; 10448 10449 u8 reserved_at_60[0x20]; 10450 10451 u8 table_type[0x8]; 10452 u8 reserved_at_88[0x7]; 10453 u8 table_of_other_vport[0x1]; 10454 u8 table_vport_number[0x10]; 10455 10456 u8 reserved_at_a0[0x8]; 10457 u8 table_id[0x18]; 10458 10459 u8 reserved_at_c0[0x8]; 10460 u8 underlay_qpn[0x18]; 10461 u8 table_eswitch_owner_vhca_id_valid[0x1]; 10462 u8 reserved_at_e1[0xf]; 10463 u8 table_eswitch_owner_vhca_id[0x10]; 10464 u8 reserved_at_100[0x100]; 10465 }; 10466 10467 enum { 10468 MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = (1UL << 0), 10469 MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15), 10470 }; 10471 10472 struct mlx5_ifc_modify_flow_table_out_bits { 10473 u8 status[0x8]; 10474 u8 reserved_at_8[0x18]; 10475 10476 u8 syndrome[0x20]; 10477 10478 u8 reserved_at_40[0x40]; 10479 }; 10480 10481 struct mlx5_ifc_modify_flow_table_in_bits { 10482 u8 opcode[0x10]; 10483 u8 reserved_at_10[0x10]; 10484 10485 u8 reserved_at_20[0x10]; 10486 u8 op_mod[0x10]; 10487 10488 u8 other_vport[0x1]; 10489 u8 reserved_at_41[0xf]; 10490 u8 vport_number[0x10]; 10491 10492 u8 reserved_at_60[0x10]; 10493 u8 modify_field_select[0x10]; 10494 10495 u8 table_type[0x8]; 10496 u8 reserved_at_88[0x18]; 10497 10498 u8 reserved_at_a0[0x8]; 10499 u8 table_id[0x18]; 10500 10501 struct mlx5_ifc_flow_table_context_bits flow_table_context; 10502 }; 10503 10504 struct mlx5_ifc_ets_tcn_config_reg_bits { 10505 u8 g[0x1]; 10506 u8 b[0x1]; 10507 u8 r[0x1]; 10508 u8 reserved_at_3[0x9]; 10509 u8 group[0x4]; 10510 u8 reserved_at_10[0x9]; 10511 u8 bw_allocation[0x7]; 10512 10513 u8 reserved_at_20[0xc]; 10514 u8 max_bw_units[0x4]; 10515 u8 reserved_at_30[0x8]; 10516 u8 max_bw_value[0x8]; 10517 }; 10518 10519 struct mlx5_ifc_ets_global_config_reg_bits { 10520 u8 reserved_at_0[0x2]; 10521 u8 r[0x1]; 10522 u8 reserved_at_3[0x1d]; 10523 10524 u8 reserved_at_20[0xc]; 10525 u8 max_bw_units[0x4]; 10526 u8 reserved_at_30[0x8]; 10527 u8 max_bw_value[0x8]; 10528 }; 10529 10530 struct mlx5_ifc_qetc_reg_bits { 10531 u8 reserved_at_0[0x8]; 10532 u8 port_number[0x8]; 10533 u8 reserved_at_10[0x30]; 10534 10535 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8]; 10536 struct mlx5_ifc_ets_global_config_reg_bits global_configuration; 10537 }; 10538 10539 struct mlx5_ifc_qpdpm_dscp_reg_bits { 10540 u8 e[0x1]; 10541 u8 reserved_at_01[0x0b]; 10542 u8 prio[0x04]; 10543 }; 10544 10545 struct mlx5_ifc_qpdpm_reg_bits { 10546 u8 reserved_at_0[0x8]; 10547 u8 local_port[0x8]; 10548 u8 reserved_at_10[0x10]; 10549 struct mlx5_ifc_qpdpm_dscp_reg_bits dscp[64]; 10550 }; 10551 10552 struct mlx5_ifc_qpts_reg_bits { 10553 u8 reserved_at_0[0x8]; 10554 u8 local_port[0x8]; 10555 u8 reserved_at_10[0x2d]; 10556 u8 trust_state[0x3]; 10557 }; 10558 10559 struct mlx5_ifc_pptb_reg_bits { 10560 u8 reserved_at_0[0x2]; 10561 u8 mm[0x2]; 10562 u8 reserved_at_4[0x4]; 10563 u8 local_port[0x8]; 10564 u8 reserved_at_10[0x6]; 10565 u8 cm[0x1]; 10566 u8 um[0x1]; 10567 u8 pm[0x8]; 10568 10569 u8 prio_x_buff[0x20]; 10570 10571 u8 pm_msb[0x8]; 10572 u8 reserved_at_48[0x10]; 10573 u8 ctrl_buff[0x4]; 10574 u8 untagged_buff[0x4]; 10575 }; 10576 10577 struct mlx5_ifc_sbcam_reg_bits { 10578 u8 reserved_at_0[0x8]; 10579 u8 feature_group[0x8]; 10580 u8 reserved_at_10[0x8]; 10581 u8 access_reg_group[0x8]; 10582 10583 u8 reserved_at_20[0x20]; 10584 10585 u8 sb_access_reg_cap_mask[4][0x20]; 10586 10587 u8 reserved_at_c0[0x80]; 10588 10589 u8 sb_feature_cap_mask[4][0x20]; 10590 10591 u8 reserved_at_1c0[0x40]; 10592 10593 u8 cap_total_buffer_size[0x20]; 10594 10595 u8 cap_cell_size[0x10]; 10596 u8 cap_max_pg_buffers[0x8]; 10597 u8 cap_num_pool_supported[0x8]; 10598 10599 u8 reserved_at_240[0x8]; 10600 u8 cap_sbsr_stat_size[0x8]; 10601 u8 cap_max_tclass_data[0x8]; 10602 u8 cap_max_cpu_ingress_tclass_sb[0x8]; 10603 }; 10604 10605 struct mlx5_ifc_pbmc_reg_bits { 10606 u8 reserved_at_0[0x8]; 10607 u8 local_port[0x8]; 10608 u8 reserved_at_10[0x10]; 10609 10610 u8 xoff_timer_value[0x10]; 10611 u8 xoff_refresh[0x10]; 10612 10613 u8 reserved_at_40[0x9]; 10614 u8 fullness_threshold[0x7]; 10615 u8 port_buffer_size[0x10]; 10616 10617 struct mlx5_ifc_bufferx_reg_bits buffer[10]; 10618 10619 u8 reserved_at_2e0[0x80]; 10620 }; 10621 10622 struct mlx5_ifc_qtct_reg_bits { 10623 u8 reserved_at_0[0x8]; 10624 u8 port_number[0x8]; 10625 u8 reserved_at_10[0xd]; 10626 u8 prio[0x3]; 10627 10628 u8 reserved_at_20[0x1d]; 10629 u8 tclass[0x3]; 10630 }; 10631 10632 struct mlx5_ifc_mcia_reg_bits { 10633 u8 l[0x1]; 10634 u8 reserved_at_1[0x7]; 10635 u8 module[0x8]; 10636 u8 reserved_at_10[0x8]; 10637 u8 status[0x8]; 10638 10639 u8 i2c_device_address[0x8]; 10640 u8 page_number[0x8]; 10641 u8 device_address[0x10]; 10642 10643 u8 reserved_at_40[0x10]; 10644 u8 size[0x10]; 10645 10646 u8 reserved_at_60[0x20]; 10647 10648 u8 dword_0[0x20]; 10649 u8 dword_1[0x20]; 10650 u8 dword_2[0x20]; 10651 u8 dword_3[0x20]; 10652 u8 dword_4[0x20]; 10653 u8 dword_5[0x20]; 10654 u8 dword_6[0x20]; 10655 u8 dword_7[0x20]; 10656 u8 dword_8[0x20]; 10657 u8 dword_9[0x20]; 10658 u8 dword_10[0x20]; 10659 u8 dword_11[0x20]; 10660 }; 10661 10662 struct mlx5_ifc_dcbx_param_bits { 10663 u8 dcbx_cee_cap[0x1]; 10664 u8 dcbx_ieee_cap[0x1]; 10665 u8 dcbx_standby_cap[0x1]; 10666 u8 reserved_at_3[0x5]; 10667 u8 port_number[0x8]; 10668 u8 reserved_at_10[0xa]; 10669 u8 max_application_table_size[6]; 10670 u8 reserved_at_20[0x15]; 10671 u8 version_oper[0x3]; 10672 u8 reserved_at_38[5]; 10673 u8 version_admin[0x3]; 10674 u8 willing_admin[0x1]; 10675 u8 reserved_at_41[0x3]; 10676 u8 pfc_cap_oper[0x4]; 10677 u8 reserved_at_48[0x4]; 10678 u8 pfc_cap_admin[0x4]; 10679 u8 reserved_at_50[0x4]; 10680 u8 num_of_tc_oper[0x4]; 10681 u8 reserved_at_58[0x4]; 10682 u8 num_of_tc_admin[0x4]; 10683 u8 remote_willing[0x1]; 10684 u8 reserved_at_61[3]; 10685 u8 remote_pfc_cap[4]; 10686 u8 reserved_at_68[0x14]; 10687 u8 remote_num_of_tc[0x4]; 10688 u8 reserved_at_80[0x18]; 10689 u8 error[0x8]; 10690 u8 reserved_at_a0[0x160]; 10691 }; 10692 10693 enum { 10694 MLX5_LAG_PORT_SELECT_MODE_QUEUE_AFFINITY = 0, 10695 MLX5_LAG_PORT_SELECT_MODE_PORT_SELECT_FT, 10696 }; 10697 10698 struct mlx5_ifc_lagc_bits { 10699 u8 fdb_selection_mode[0x1]; 10700 u8 reserved_at_1[0x14]; 10701 u8 port_select_mode[0x3]; 10702 u8 reserved_at_18[0x5]; 10703 u8 lag_state[0x3]; 10704 10705 u8 reserved_at_20[0x14]; 10706 u8 tx_remap_affinity_2[0x4]; 10707 u8 reserved_at_38[0x4]; 10708 u8 tx_remap_affinity_1[0x4]; 10709 }; 10710 10711 struct mlx5_ifc_create_lag_out_bits { 10712 u8 status[0x8]; 10713 u8 reserved_at_8[0x18]; 10714 10715 u8 syndrome[0x20]; 10716 10717 u8 reserved_at_40[0x40]; 10718 }; 10719 10720 struct mlx5_ifc_create_lag_in_bits { 10721 u8 opcode[0x10]; 10722 u8 reserved_at_10[0x10]; 10723 10724 u8 reserved_at_20[0x10]; 10725 u8 op_mod[0x10]; 10726 10727 struct mlx5_ifc_lagc_bits ctx; 10728 }; 10729 10730 struct mlx5_ifc_modify_lag_out_bits { 10731 u8 status[0x8]; 10732 u8 reserved_at_8[0x18]; 10733 10734 u8 syndrome[0x20]; 10735 10736 u8 reserved_at_40[0x40]; 10737 }; 10738 10739 struct mlx5_ifc_modify_lag_in_bits { 10740 u8 opcode[0x10]; 10741 u8 reserved_at_10[0x10]; 10742 10743 u8 reserved_at_20[0x10]; 10744 u8 op_mod[0x10]; 10745 10746 u8 reserved_at_40[0x20]; 10747 u8 field_select[0x20]; 10748 10749 struct mlx5_ifc_lagc_bits ctx; 10750 }; 10751 10752 struct mlx5_ifc_query_lag_out_bits { 10753 u8 status[0x8]; 10754 u8 reserved_at_8[0x18]; 10755 10756 u8 syndrome[0x20]; 10757 10758 struct mlx5_ifc_lagc_bits ctx; 10759 }; 10760 10761 struct mlx5_ifc_query_lag_in_bits { 10762 u8 opcode[0x10]; 10763 u8 reserved_at_10[0x10]; 10764 10765 u8 reserved_at_20[0x10]; 10766 u8 op_mod[0x10]; 10767 10768 u8 reserved_at_40[0x40]; 10769 }; 10770 10771 struct mlx5_ifc_destroy_lag_out_bits { 10772 u8 status[0x8]; 10773 u8 reserved_at_8[0x18]; 10774 10775 u8 syndrome[0x20]; 10776 10777 u8 reserved_at_40[0x40]; 10778 }; 10779 10780 struct mlx5_ifc_destroy_lag_in_bits { 10781 u8 opcode[0x10]; 10782 u8 reserved_at_10[0x10]; 10783 10784 u8 reserved_at_20[0x10]; 10785 u8 op_mod[0x10]; 10786 10787 u8 reserved_at_40[0x40]; 10788 }; 10789 10790 struct mlx5_ifc_create_vport_lag_out_bits { 10791 u8 status[0x8]; 10792 u8 reserved_at_8[0x18]; 10793 10794 u8 syndrome[0x20]; 10795 10796 u8 reserved_at_40[0x40]; 10797 }; 10798 10799 struct mlx5_ifc_create_vport_lag_in_bits { 10800 u8 opcode[0x10]; 10801 u8 reserved_at_10[0x10]; 10802 10803 u8 reserved_at_20[0x10]; 10804 u8 op_mod[0x10]; 10805 10806 u8 reserved_at_40[0x40]; 10807 }; 10808 10809 struct mlx5_ifc_destroy_vport_lag_out_bits { 10810 u8 status[0x8]; 10811 u8 reserved_at_8[0x18]; 10812 10813 u8 syndrome[0x20]; 10814 10815 u8 reserved_at_40[0x40]; 10816 }; 10817 10818 struct mlx5_ifc_destroy_vport_lag_in_bits { 10819 u8 opcode[0x10]; 10820 u8 reserved_at_10[0x10]; 10821 10822 u8 reserved_at_20[0x10]; 10823 u8 op_mod[0x10]; 10824 10825 u8 reserved_at_40[0x40]; 10826 }; 10827 10828 enum { 10829 MLX5_MODIFY_MEMIC_OP_MOD_ALLOC, 10830 MLX5_MODIFY_MEMIC_OP_MOD_DEALLOC, 10831 }; 10832 10833 struct mlx5_ifc_modify_memic_in_bits { 10834 u8 opcode[0x10]; 10835 u8 uid[0x10]; 10836 10837 u8 reserved_at_20[0x10]; 10838 u8 op_mod[0x10]; 10839 10840 u8 reserved_at_40[0x20]; 10841 10842 u8 reserved_at_60[0x18]; 10843 u8 memic_operation_type[0x8]; 10844 10845 u8 memic_start_addr[0x40]; 10846 10847 u8 reserved_at_c0[0x140]; 10848 }; 10849 10850 struct mlx5_ifc_modify_memic_out_bits { 10851 u8 status[0x8]; 10852 u8 reserved_at_8[0x18]; 10853 10854 u8 syndrome[0x20]; 10855 10856 u8 reserved_at_40[0x40]; 10857 10858 u8 memic_operation_addr[0x40]; 10859 10860 u8 reserved_at_c0[0x140]; 10861 }; 10862 10863 struct mlx5_ifc_alloc_memic_in_bits { 10864 u8 opcode[0x10]; 10865 u8 reserved_at_10[0x10]; 10866 10867 u8 reserved_at_20[0x10]; 10868 u8 op_mod[0x10]; 10869 10870 u8 reserved_at_30[0x20]; 10871 10872 u8 reserved_at_40[0x18]; 10873 u8 log_memic_addr_alignment[0x8]; 10874 10875 u8 range_start_addr[0x40]; 10876 10877 u8 range_size[0x20]; 10878 10879 u8 memic_size[0x20]; 10880 }; 10881 10882 struct mlx5_ifc_alloc_memic_out_bits { 10883 u8 status[0x8]; 10884 u8 reserved_at_8[0x18]; 10885 10886 u8 syndrome[0x20]; 10887 10888 u8 memic_start_addr[0x40]; 10889 }; 10890 10891 struct mlx5_ifc_dealloc_memic_in_bits { 10892 u8 opcode[0x10]; 10893 u8 reserved_at_10[0x10]; 10894 10895 u8 reserved_at_20[0x10]; 10896 u8 op_mod[0x10]; 10897 10898 u8 reserved_at_40[0x40]; 10899 10900 u8 memic_start_addr[0x40]; 10901 10902 u8 memic_size[0x20]; 10903 10904 u8 reserved_at_e0[0x20]; 10905 }; 10906 10907 struct mlx5_ifc_dealloc_memic_out_bits { 10908 u8 status[0x8]; 10909 u8 reserved_at_8[0x18]; 10910 10911 u8 syndrome[0x20]; 10912 10913 u8 reserved_at_40[0x40]; 10914 }; 10915 10916 struct mlx5_ifc_umem_bits { 10917 u8 reserved_at_0[0x80]; 10918 10919 u8 reserved_at_80[0x1b]; 10920 u8 log_page_size[0x5]; 10921 10922 u8 page_offset[0x20]; 10923 10924 u8 num_of_mtt[0x40]; 10925 10926 struct mlx5_ifc_mtt_bits mtt[]; 10927 }; 10928 10929 struct mlx5_ifc_uctx_bits { 10930 u8 cap[0x20]; 10931 10932 u8 reserved_at_20[0x160]; 10933 }; 10934 10935 struct mlx5_ifc_sw_icm_bits { 10936 u8 modify_field_select[0x40]; 10937 10938 u8 reserved_at_40[0x18]; 10939 u8 log_sw_icm_size[0x8]; 10940 10941 u8 reserved_at_60[0x20]; 10942 10943 u8 sw_icm_start_addr[0x40]; 10944 10945 u8 reserved_at_c0[0x140]; 10946 }; 10947 10948 struct mlx5_ifc_geneve_tlv_option_bits { 10949 u8 modify_field_select[0x40]; 10950 10951 u8 reserved_at_40[0x18]; 10952 u8 geneve_option_fte_index[0x8]; 10953 10954 u8 option_class[0x10]; 10955 u8 option_type[0x8]; 10956 u8 reserved_at_78[0x3]; 10957 u8 option_data_length[0x5]; 10958 10959 u8 reserved_at_80[0x180]; 10960 }; 10961 10962 struct mlx5_ifc_create_umem_in_bits { 10963 u8 opcode[0x10]; 10964 u8 uid[0x10]; 10965 10966 u8 reserved_at_20[0x10]; 10967 u8 op_mod[0x10]; 10968 10969 u8 reserved_at_40[0x40]; 10970 10971 struct mlx5_ifc_umem_bits umem; 10972 }; 10973 10974 struct mlx5_ifc_create_umem_out_bits { 10975 u8 status[0x8]; 10976 u8 reserved_at_8[0x18]; 10977 10978 u8 syndrome[0x20]; 10979 10980 u8 reserved_at_40[0x8]; 10981 u8 umem_id[0x18]; 10982 10983 u8 reserved_at_60[0x20]; 10984 }; 10985 10986 struct mlx5_ifc_destroy_umem_in_bits { 10987 u8 opcode[0x10]; 10988 u8 uid[0x10]; 10989 10990 u8 reserved_at_20[0x10]; 10991 u8 op_mod[0x10]; 10992 10993 u8 reserved_at_40[0x8]; 10994 u8 umem_id[0x18]; 10995 10996 u8 reserved_at_60[0x20]; 10997 }; 10998 10999 struct mlx5_ifc_destroy_umem_out_bits { 11000 u8 status[0x8]; 11001 u8 reserved_at_8[0x18]; 11002 11003 u8 syndrome[0x20]; 11004 11005 u8 reserved_at_40[0x40]; 11006 }; 11007 11008 struct mlx5_ifc_create_uctx_in_bits { 11009 u8 opcode[0x10]; 11010 u8 reserved_at_10[0x10]; 11011 11012 u8 reserved_at_20[0x10]; 11013 u8 op_mod[0x10]; 11014 11015 u8 reserved_at_40[0x40]; 11016 11017 struct mlx5_ifc_uctx_bits uctx; 11018 }; 11019 11020 struct mlx5_ifc_create_uctx_out_bits { 11021 u8 status[0x8]; 11022 u8 reserved_at_8[0x18]; 11023 11024 u8 syndrome[0x20]; 11025 11026 u8 reserved_at_40[0x10]; 11027 u8 uid[0x10]; 11028 11029 u8 reserved_at_60[0x20]; 11030 }; 11031 11032 struct mlx5_ifc_destroy_uctx_in_bits { 11033 u8 opcode[0x10]; 11034 u8 reserved_at_10[0x10]; 11035 11036 u8 reserved_at_20[0x10]; 11037 u8 op_mod[0x10]; 11038 11039 u8 reserved_at_40[0x10]; 11040 u8 uid[0x10]; 11041 11042 u8 reserved_at_60[0x20]; 11043 }; 11044 11045 struct mlx5_ifc_destroy_uctx_out_bits { 11046 u8 status[0x8]; 11047 u8 reserved_at_8[0x18]; 11048 11049 u8 syndrome[0x20]; 11050 11051 u8 reserved_at_40[0x40]; 11052 }; 11053 11054 struct mlx5_ifc_create_sw_icm_in_bits { 11055 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 11056 struct mlx5_ifc_sw_icm_bits sw_icm; 11057 }; 11058 11059 struct mlx5_ifc_create_geneve_tlv_option_in_bits { 11060 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 11061 struct mlx5_ifc_geneve_tlv_option_bits geneve_tlv_opt; 11062 }; 11063 11064 struct mlx5_ifc_mtrc_string_db_param_bits { 11065 u8 string_db_base_address[0x20]; 11066 11067 u8 reserved_at_20[0x8]; 11068 u8 string_db_size[0x18]; 11069 }; 11070 11071 struct mlx5_ifc_mtrc_cap_bits { 11072 u8 trace_owner[0x1]; 11073 u8 trace_to_memory[0x1]; 11074 u8 reserved_at_2[0x4]; 11075 u8 trc_ver[0x2]; 11076 u8 reserved_at_8[0x14]; 11077 u8 num_string_db[0x4]; 11078 11079 u8 first_string_trace[0x8]; 11080 u8 num_string_trace[0x8]; 11081 u8 reserved_at_30[0x28]; 11082 11083 u8 log_max_trace_buffer_size[0x8]; 11084 11085 u8 reserved_at_60[0x20]; 11086 11087 struct mlx5_ifc_mtrc_string_db_param_bits string_db_param[8]; 11088 11089 u8 reserved_at_280[0x180]; 11090 }; 11091 11092 struct mlx5_ifc_mtrc_conf_bits { 11093 u8 reserved_at_0[0x1c]; 11094 u8 trace_mode[0x4]; 11095 u8 reserved_at_20[0x18]; 11096 u8 log_trace_buffer_size[0x8]; 11097 u8 trace_mkey[0x20]; 11098 u8 reserved_at_60[0x3a0]; 11099 }; 11100 11101 struct mlx5_ifc_mtrc_stdb_bits { 11102 u8 string_db_index[0x4]; 11103 u8 reserved_at_4[0x4]; 11104 u8 read_size[0x18]; 11105 u8 start_offset[0x20]; 11106 u8 string_db_data[]; 11107 }; 11108 11109 struct mlx5_ifc_mtrc_ctrl_bits { 11110 u8 trace_status[0x2]; 11111 u8 reserved_at_2[0x2]; 11112 u8 arm_event[0x1]; 11113 u8 reserved_at_5[0xb]; 11114 u8 modify_field_select[0x10]; 11115 u8 reserved_at_20[0x2b]; 11116 u8 current_timestamp52_32[0x15]; 11117 u8 current_timestamp31_0[0x20]; 11118 u8 reserved_at_80[0x180]; 11119 }; 11120 11121 struct mlx5_ifc_host_params_context_bits { 11122 u8 host_number[0x8]; 11123 u8 reserved_at_8[0x7]; 11124 u8 host_pf_disabled[0x1]; 11125 u8 host_num_of_vfs[0x10]; 11126 11127 u8 host_total_vfs[0x10]; 11128 u8 host_pci_bus[0x10]; 11129 11130 u8 reserved_at_40[0x10]; 11131 u8 host_pci_device[0x10]; 11132 11133 u8 reserved_at_60[0x10]; 11134 u8 host_pci_function[0x10]; 11135 11136 u8 reserved_at_80[0x180]; 11137 }; 11138 11139 struct mlx5_ifc_query_esw_functions_in_bits { 11140 u8 opcode[0x10]; 11141 u8 reserved_at_10[0x10]; 11142 11143 u8 reserved_at_20[0x10]; 11144 u8 op_mod[0x10]; 11145 11146 u8 reserved_at_40[0x40]; 11147 }; 11148 11149 struct mlx5_ifc_query_esw_functions_out_bits { 11150 u8 status[0x8]; 11151 u8 reserved_at_8[0x18]; 11152 11153 u8 syndrome[0x20]; 11154 11155 u8 reserved_at_40[0x40]; 11156 11157 struct mlx5_ifc_host_params_context_bits host_params_context; 11158 11159 u8 reserved_at_280[0x180]; 11160 u8 host_sf_enable[][0x40]; 11161 }; 11162 11163 struct mlx5_ifc_sf_partition_bits { 11164 u8 reserved_at_0[0x10]; 11165 u8 log_num_sf[0x8]; 11166 u8 log_sf_bar_size[0x8]; 11167 }; 11168 11169 struct mlx5_ifc_query_sf_partitions_out_bits { 11170 u8 status[0x8]; 11171 u8 reserved_at_8[0x18]; 11172 11173 u8 syndrome[0x20]; 11174 11175 u8 reserved_at_40[0x18]; 11176 u8 num_sf_partitions[0x8]; 11177 11178 u8 reserved_at_60[0x20]; 11179 11180 struct mlx5_ifc_sf_partition_bits sf_partition[]; 11181 }; 11182 11183 struct mlx5_ifc_query_sf_partitions_in_bits { 11184 u8 opcode[0x10]; 11185 u8 reserved_at_10[0x10]; 11186 11187 u8 reserved_at_20[0x10]; 11188 u8 op_mod[0x10]; 11189 11190 u8 reserved_at_40[0x40]; 11191 }; 11192 11193 struct mlx5_ifc_dealloc_sf_out_bits { 11194 u8 status[0x8]; 11195 u8 reserved_at_8[0x18]; 11196 11197 u8 syndrome[0x20]; 11198 11199 u8 reserved_at_40[0x40]; 11200 }; 11201 11202 struct mlx5_ifc_dealloc_sf_in_bits { 11203 u8 opcode[0x10]; 11204 u8 reserved_at_10[0x10]; 11205 11206 u8 reserved_at_20[0x10]; 11207 u8 op_mod[0x10]; 11208 11209 u8 reserved_at_40[0x10]; 11210 u8 function_id[0x10]; 11211 11212 u8 reserved_at_60[0x20]; 11213 }; 11214 11215 struct mlx5_ifc_alloc_sf_out_bits { 11216 u8 status[0x8]; 11217 u8 reserved_at_8[0x18]; 11218 11219 u8 syndrome[0x20]; 11220 11221 u8 reserved_at_40[0x40]; 11222 }; 11223 11224 struct mlx5_ifc_alloc_sf_in_bits { 11225 u8 opcode[0x10]; 11226 u8 reserved_at_10[0x10]; 11227 11228 u8 reserved_at_20[0x10]; 11229 u8 op_mod[0x10]; 11230 11231 u8 reserved_at_40[0x10]; 11232 u8 function_id[0x10]; 11233 11234 u8 reserved_at_60[0x20]; 11235 }; 11236 11237 struct mlx5_ifc_affiliated_event_header_bits { 11238 u8 reserved_at_0[0x10]; 11239 u8 obj_type[0x10]; 11240 11241 u8 obj_id[0x20]; 11242 }; 11243 11244 enum { 11245 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = BIT_ULL(0xc), 11246 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_IPSEC = BIT_ULL(0x13), 11247 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_SAMPLER = BIT_ULL(0x20), 11248 }; 11249 11250 enum { 11251 MLX5_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = 0xc, 11252 MLX5_GENERAL_OBJECT_TYPES_IPSEC = 0x13, 11253 MLX5_GENERAL_OBJECT_TYPES_SAMPLER = 0x20, 11254 }; 11255 11256 enum { 11257 MLX5_IPSEC_OBJECT_ICV_LEN_16B, 11258 MLX5_IPSEC_OBJECT_ICV_LEN_12B, 11259 MLX5_IPSEC_OBJECT_ICV_LEN_8B, 11260 }; 11261 11262 struct mlx5_ifc_ipsec_obj_bits { 11263 u8 modify_field_select[0x40]; 11264 u8 full_offload[0x1]; 11265 u8 reserved_at_41[0x1]; 11266 u8 esn_en[0x1]; 11267 u8 esn_overlap[0x1]; 11268 u8 reserved_at_44[0x2]; 11269 u8 icv_length[0x2]; 11270 u8 reserved_at_48[0x4]; 11271 u8 aso_return_reg[0x4]; 11272 u8 reserved_at_50[0x10]; 11273 11274 u8 esn_msb[0x20]; 11275 11276 u8 reserved_at_80[0x8]; 11277 u8 dekn[0x18]; 11278 11279 u8 salt[0x20]; 11280 11281 u8 implicit_iv[0x40]; 11282 11283 u8 reserved_at_100[0x700]; 11284 }; 11285 11286 struct mlx5_ifc_create_ipsec_obj_in_bits { 11287 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 11288 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 11289 }; 11290 11291 enum { 11292 MLX5_MODIFY_IPSEC_BITMASK_ESN_OVERLAP = BIT(0), 11293 MLX5_MODIFY_IPSEC_BITMASK_ESN_MSB = BIT(1), 11294 }; 11295 11296 struct mlx5_ifc_query_ipsec_obj_out_bits { 11297 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 11298 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 11299 }; 11300 11301 struct mlx5_ifc_modify_ipsec_obj_in_bits { 11302 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 11303 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 11304 }; 11305 11306 struct mlx5_ifc_encryption_key_obj_bits { 11307 u8 modify_field_select[0x40]; 11308 11309 u8 reserved_at_40[0x14]; 11310 u8 key_size[0x4]; 11311 u8 reserved_at_58[0x4]; 11312 u8 key_type[0x4]; 11313 11314 u8 reserved_at_60[0x8]; 11315 u8 pd[0x18]; 11316 11317 u8 reserved_at_80[0x180]; 11318 u8 key[8][0x20]; 11319 11320 u8 reserved_at_300[0x500]; 11321 }; 11322 11323 struct mlx5_ifc_create_encryption_key_in_bits { 11324 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 11325 struct mlx5_ifc_encryption_key_obj_bits encryption_key_object; 11326 }; 11327 11328 struct mlx5_ifc_sampler_obj_bits { 11329 u8 modify_field_select[0x40]; 11330 11331 u8 table_type[0x8]; 11332 u8 level[0x8]; 11333 u8 reserved_at_50[0xf]; 11334 u8 ignore_flow_level[0x1]; 11335 11336 u8 sample_ratio[0x20]; 11337 11338 u8 reserved_at_80[0x8]; 11339 u8 sample_table_id[0x18]; 11340 11341 u8 reserved_at_a0[0x8]; 11342 u8 default_table_id[0x18]; 11343 11344 u8 sw_steering_icm_address_rx[0x40]; 11345 u8 sw_steering_icm_address_tx[0x40]; 11346 11347 u8 reserved_at_140[0xa0]; 11348 }; 11349 11350 struct mlx5_ifc_create_sampler_obj_in_bits { 11351 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 11352 struct mlx5_ifc_sampler_obj_bits sampler_object; 11353 }; 11354 11355 struct mlx5_ifc_query_sampler_obj_out_bits { 11356 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 11357 struct mlx5_ifc_sampler_obj_bits sampler_object; 11358 }; 11359 11360 enum { 11361 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_128 = 0x0, 11362 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_256 = 0x1, 11363 }; 11364 11365 enum { 11366 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_TYPE_TLS = 0x1, 11367 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_TYPE_IPSEC = 0x2, 11368 }; 11369 11370 struct mlx5_ifc_tls_static_params_bits { 11371 u8 const_2[0x2]; 11372 u8 tls_version[0x4]; 11373 u8 const_1[0x2]; 11374 u8 reserved_at_8[0x14]; 11375 u8 encryption_standard[0x4]; 11376 11377 u8 reserved_at_20[0x20]; 11378 11379 u8 initial_record_number[0x40]; 11380 11381 u8 resync_tcp_sn[0x20]; 11382 11383 u8 gcm_iv[0x20]; 11384 11385 u8 implicit_iv[0x40]; 11386 11387 u8 reserved_at_100[0x8]; 11388 u8 dek_index[0x18]; 11389 11390 u8 reserved_at_120[0xe0]; 11391 }; 11392 11393 struct mlx5_ifc_tls_progress_params_bits { 11394 u8 next_record_tcp_sn[0x20]; 11395 11396 u8 hw_resync_tcp_sn[0x20]; 11397 11398 u8 record_tracker_state[0x2]; 11399 u8 auth_state[0x2]; 11400 u8 reserved_at_44[0x4]; 11401 u8 hw_offset_record_number[0x18]; 11402 }; 11403 11404 enum { 11405 MLX5_MTT_PERM_READ = 1 << 0, 11406 MLX5_MTT_PERM_WRITE = 1 << 1, 11407 MLX5_MTT_PERM_RW = MLX5_MTT_PERM_READ | MLX5_MTT_PERM_WRITE, 11408 }; 11409 11410 #endif /* MLX5_IFC_H */ 11411